From bb0df2740e251ce1046afcfdb2cad2657c881d0c Mon Sep 17 00:00:00 2001
From: Jacob Potter <jacob@j4cbo.com>
Date: Sat, 31 Oct 2020 11:03:55 -0600
Subject: [PATCH 0001/2085] Add CDC NCM driver

---
 src/class/cdc/cdc.h            |   6 +-
 src/class/cdc/cdc_ncm_device.c | 493 +++++++++++++++++++++++++++++++++
 src/class/cdc/cdc_ncm_device.h |  88 ++++++
 src/device/usbd.c              |  13 +
 src/device/usbd.h              |  33 +++
 src/tusb.h                     |   4 +
 6 files changed, 635 insertions(+), 2 deletions(-)
 create mode 100644 src/class/cdc/cdc_ncm_device.c
 create mode 100644 src/class/cdc/cdc_ncm_device.h

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index 2c044ac7f..2a44f0fc8 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -69,7 +69,8 @@ typedef enum
   CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT                 , ///< Device Management  [USBWMC1.1]
   CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL          , ///< Mobile Direct Line Model  [USBWMC1.1]
   CDC_COMM_SUBCLASS_OBEX                              , ///< OBEX  [USBWMC1.1]
-  CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL            ///< Ethernet Emulation Model  [USBEEM1.0]
+  CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL          , ///< Ethernet Emulation Model  [USBEEM1.0]
+  CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL               ///< Network Control Model  [USBNCM1.0]
 } cdc_comm_sublcass_type_t;
 
 /// Communication Interface Protocol Codes
@@ -114,7 +115,8 @@ typedef enum
   CDC_FUNC_DESC_COMMAND_SET                                      = 0x16 , ///< Command Set Functional Descriptor
   CDC_FUNC_DESC_COMMAND_SET_DETAIL                               = 0x17 , ///< Command Set Detail Functional Descriptor
   CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL                          = 0x18 , ///< Telephone Control Model Functional Descriptor
-  CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER                          = 0x19   ///< OBEX Service Identifier Functional Descriptor
+  CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER                          = 0x19 , ///< OBEX Service Identifier Functional Descriptor
+  CDC_FUNC_DESC_NCM                                              = 0x1A , ///< NCM Functional Descriptor
 }cdc_func_desc_type_t;
 
 //--------------------------------------------------------------------+
diff --git a/src/class/cdc/cdc_ncm_device.c b/src/class/cdc/cdc_ncm_device.c
new file mode 100644
index 000000000..e6d65171d
--- /dev/null
+++ b/src/class/cdc/cdc_ncm_device.c
@@ -0,0 +1,493 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jacob Berg Potter
+ * Copyright (c) 2020 Peter Lawrence
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NCM )
+
+#include "device/usbd_pvt.h"
+#include "cdc_device.h"
+#include "cdc_ncm_device.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+#define NTH16_SIGNATURE 0x484D434E
+#define NDP16_SIGNATURE_NCM0 0x304D434E
+#define NDP16_SIGNATURE_NCM1 0x314D434E
+
+typedef struct
+{
+  uint8_t itf_num;      // Index number of Management Interface, +1 for Data Interface
+  uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active
+
+  uint8_t ep_notif;
+  uint8_t ep_in;
+  uint8_t ep_out;
+
+  // Endpoint descriptor use to open/close when receving SetInterface
+  // TODO since configuration descriptor may not be long-lived memory, we should
+  // keep a copy of endpoint attribute instead
+  uint8_t const * ecm_desc_epdata;
+
+  enum {
+    REPORT_SPEED,
+    REPORT_CONNECTED,
+    REPORT_DONE
+  } report_state;
+  bool report_pending;
+
+  uint8_t current_ntb; // Index in transmit_ntb[] that is currently being filled with datagrams
+  uint8_t datagram_count; // Number of datagrams in transmit_ntb[current_ntb]
+  uint16_t next_datagram_offset; // Offset in transmit_ntb[current_ntb].data to place the next datagram
+  uint16_t ntb_in_size; // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE
+  uint8_t max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
+
+  uint16_t nth_sequence; // Sequence number counter for transmitted NTBs
+
+  bool transferring;
+
+} ncm_interface_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  uint16_t wLength;
+  uint16_t bmNtbFormatsSupported;
+  uint32_t dwNtbInMaxSize;
+  uint16_t wNdbInDivisor;
+  uint16_t wNdbInPayloadRemainder;
+  uint16_t wNdbInAlignment;
+  uint16_t wReserved;
+  uint32_t dwNtbOutMaxSize;
+  uint16_t wNdbOutDivisor;
+  uint16_t wNdbOutPayloadRemainder;
+  uint16_t wNdbOutAlignment;
+  uint16_t wNtbOutMaxDatagrams;
+} ntb_parameters_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  uint32_t dwSignature;
+  uint16_t wHeaderLength;
+  uint16_t wSequence;
+  uint16_t wBlockLength;
+  uint16_t wNdpIndex;
+} nth16_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  uint16_t wDatagramIndex;
+  uint16_t wDatagramLength;
+} ndp16_datagram_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  uint32_t dwSignature;
+  uint16_t wLength;
+  uint16_t wNextNdpIndex;
+  ndp16_datagram_t datagram[];
+} ndp16_t;
+
+typedef union TU_ATTR_PACKED {
+  struct {
+    nth16_t nth;
+    ndp16_t ndp;
+  };
+  uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
+} transmit_ntb_t;
+
+struct ecm_notify_struct
+{
+  tusb_control_request_t header;
+  uint32_t downlink, uplink;
+};
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parameters = {
+    .wLength = sizeof(ntb_parameters_t),
+    .bmNtbFormatsSupported = 0x01,
+    .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
+    .wNdbInDivisor = 4,
+    .wNdbInPayloadRemainder = 0,
+    .wNdbInAlignment = CFG_TUD_NCM_ALIGNMENT,
+    .wReserved = 0,
+    .dwNtbOutMaxSize = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
+    .wNdbOutDivisor = 4,
+    .wNdbOutPayloadRemainder = 0,
+    .wNdbOutAlignment = CFG_TUD_NCM_ALIGNMENT,
+    .wNtbOutMaxDatagrams = 0
+};
+
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static transmit_ntb_t transmit_ntb[2];
+
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+
+static ncm_interface_t ncm_interface;
+
+/*
+ * Set up the NTB state in ncm_interface to be ready to add datagrams.
+ */
+static void ncm_prepare_for_tx() {
+  ncm_interface.datagram_count = 0;
+  // datagrams start after all the headers
+  ncm_interface.next_datagram_offset = sizeof(nth16_t) + sizeof(ndp16_t)
+      + ((CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + 1) * sizeof(ndp16_datagram_t));
+}
+
+/*
+ * If not already transmitting, start sending the current NTB to the host and swap buffers
+ * to start filling the other one with datagrams.
+ */
+static void ncm_start_tx() {
+  if (ncm_interface.transferring) {
+    return;
+  }
+
+  transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
+  size_t ntb_length = ncm_interface.next_datagram_offset;
+
+  // Fill in NTB header
+  ntb->nth.dwSignature = NTH16_SIGNATURE;
+  ntb->nth.wHeaderLength = sizeof(nth16_t);
+  ntb->nth.wSequence = ncm_interface.nth_sequence++;
+  ntb->nth.wBlockLength = ntb_length;
+  ntb->nth.wNdpIndex = sizeof(nth16_t);
+
+  // Fill in NDP16 header and terminator
+  ntb->ndp.dwSignature = NDP16_SIGNATURE_NCM0;
+  ntb->ndp.wLength = sizeof(ndp16_t) + (ncm_interface.datagram_count + 1) * sizeof(ndp16_datagram_t);
+  ntb->ndp.wNextNdpIndex = 0;
+  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = 0;
+  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = 0;
+
+  // Kick off an endpoint transfer
+  usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_in, ntb->data, ntb_length);
+  ncm_interface.transferring = true;
+
+  // Swap to the other NTB and clear it out
+  ncm_interface.current_ntb = 1 - ncm_interface.current_ntb;
+  ncm_prepare_for_tx();
+}
+
+static struct ecm_notify_struct ncm_notify_connected =
+    {
+        .header = {
+            .bmRequestType = 0xA1,
+            .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */,
+            .wValue = 1 /* Connected */,
+            .wLength = 0,
+        },
+    };
+
+static struct ecm_notify_struct ncm_notify_speed_change =
+    {
+        .header = {
+            .bmRequestType = 0xA1,
+            .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */,
+            .wLength = 8,
+        },
+        .downlink = 10000000,
+        .uplink = 10000000,
+    };
+
+void ncm_receive_renew(void)
+{
+  usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_out, receive_ntb, sizeof(receive_ntb));
+}
+
+//--------------------------------------------------------------------+
+// USBD Driver API
+//--------------------------------------------------------------------+
+
+void ncmd_init(void)
+{
+  tu_memclr(&ncm_interface, sizeof(ncm_interface));
+  ncm_interface.ntb_in_size = CFG_TUD_NCM_IN_NTB_MAX_SIZE;
+  ncm_interface.max_datagrams_per_ntb = CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB;
+  ncm_prepare_for_tx();
+}
+
+void ncmd_reset(uint8_t rhport)
+{
+  (void) rhport;
+
+  ncmd_init();
+}
+
+uint16_t ncmd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
+{
+  // confirm interface hasn't already been allocated
+  TU_ASSERT(0 == ncm_interface.ep_notif, 0);
+
+  //------------- Management Interface -------------//
+  ncm_interface.itf_num = itf_desc->bInterfaceNumber;
+
+  uint16_t drv_len = sizeof(tusb_desc_interface_t);
+  uint8_t const * p_desc = tu_desc_next( itf_desc );
+
+  // Communication Functional Descriptors
+  while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
+  {
+    drv_len += tu_desc_len(p_desc);
+    p_desc   = tu_desc_next(p_desc);
+  }
+
+  // notification endpoint (if any)
+  if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
+  {
+    TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 );
+
+    ncm_interface.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+
+    drv_len += tu_desc_len(p_desc);
+    p_desc   = tu_desc_next(p_desc);
+  }
+
+  //------------- Data Interface -------------//
+  // - CDC-NCM data interface has 2 alternate settings
+  //   - 0 : zero endpoints for inactive (default)
+  //   - 1 : IN & OUT endpoints for transfer of NTBs
+  TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0);
+
+  do
+  {
+    tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc;
+    TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0);
+
+    drv_len += tu_desc_len(p_desc);
+    p_desc   = tu_desc_next(p_desc);
+  } while((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len));
+
+  // Pair of endpoints
+  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0);
+
+  // ECM by default is in-active, save the endpoint attribute
+  // to open later when receive_ntb setInterface
+  ncm_interface.ecm_desc_epdata = p_desc;
+
+  drv_len += 2*sizeof(tusb_desc_endpoint_t);
+
+  return drv_len;
+}
+
+// Invoked when class request DATA stage is finished.
+bool ncmd_control_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  (void) rhport;
+  (void) request;
+  return true;
+}
+
+static void ncm_report()
+{
+  if (ncm_interface.report_state == REPORT_SPEED) {
+    ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
+    usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
+    ncm_interface.report_state = REPORT_CONNECTED;
+    ncm_interface.report_pending = true;
+  } else if (ncm_interface.report_state == REPORT_CONNECTED) {
+    ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
+    usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected));
+    ncm_interface.report_state = REPORT_DONE;
+    ncm_interface.report_pending = true;
+  }
+}
+
+// Handle class control request
+// return false to stall control endpoint (e.g unsupported request)
+bool ncmd_control_request(uint8_t rhport, tusb_control_request_t const * request)
+{
+  switch ( request->bmRequestType_bit.type )
+  {
+    case TUSB_REQ_TYPE_STANDARD:
+      switch ( request->bRequest )
+      {
+        case TUSB_REQ_GET_INTERFACE:
+        {
+          uint8_t const req_itfnum = (uint8_t) request->wIndex;
+          TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum);
+
+          tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
+        }
+          break;
+
+        case TUSB_REQ_SET_INTERFACE:
+        {
+          uint8_t const req_itfnum = (uint8_t) request->wIndex;
+          uint8_t const req_alt    = (uint8_t) request->wValue;
+
+          // Only valid for Data Interface with Alternate is either 0 or 1
+          TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum && req_alt < 2);
+
+          ncm_interface.itf_data_alt = req_alt;
+
+          if ( ncm_interface.itf_data_alt )
+          {
+            // TODO since we don't actually close endpoint
+            // hack here to not re-open it
+            if (ncm_interface.ep_in == 0 && ncm_interface.ep_out == 0)
+            {
+              TU_ASSERT(ncm_interface.ecm_desc_epdata);
+              TU_ASSERT( usbd_open_edpt_pair(rhport, ncm_interface.ecm_desc_epdata, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) );
+
+              // TODO set flag indicating tx allowed?
+              ncm_receive_renew(); // prepare for incoming datagrams
+              tud_ncm_link_state_cb(true);
+            }
+          } else {
+            // TODO close the endpoint pair
+            // For now pretend that we did, this should have no harm since host won't try to
+            // communicate with the endpoints again
+            // ncm_interface.ep_in = ncm_interface.ep_out = 0
+            // ncm_interface.report_pending = 0;
+          }
+
+          tud_control_status(rhport, request);
+
+          if (!ncm_interface.report_pending) ncm_report();
+
+        }
+          break;
+
+          // unsupported request
+        default: return false;
+      }
+      break;
+
+    case TUSB_REQ_TYPE_CLASS:
+      TU_VERIFY (ncm_interface.itf_num == request->wIndex);
+
+      if (0x80 /* GET_NTB_PARAMETERS */ == request->bRequest)
+      {
+        tud_control_xfer(rhport, request, (void*)&ntb_parameters, sizeof(ntb_parameters));
+      }
+
+      break;
+
+      // unsupported request
+    default: return false;
+  }
+
+  return true;
+}
+
+static void handle_incoming_datagram(uint32_t len)
+{
+  uint32_t size = len;
+
+  if (len == 0) {
+    return;
+  }
+
+  TU_ASSERT(size >= sizeof(nth16_t), );
+
+  const nth16_t *hdr = (const nth16_t *)receive_ntb;
+  TU_ASSERT(hdr->dwSignature == NTH16_SIGNATURE, );
+  TU_ASSERT(hdr->wNdpIndex >= sizeof(nth16_t) && (hdr->wNdpIndex + sizeof(ndp16_t)) <= len, );
+
+  const ndp16_t *ndp = (const ndp16_t *)(receive_ntb + hdr->wNdpIndex);
+  TU_ASSERT(ndp->dwSignature == NDP16_SIGNATURE_NCM0 || ndp->dwSignature == NDP16_SIGNATURE_NCM1, );
+  TU_ASSERT(hdr->wNdpIndex + ndp->wLength <= len, );
+
+  int num_datagrams = (ndp->wLength - 12) / 4;
+  for (int i = 0; i < num_datagrams && ndp->datagram[i].wDatagramIndex && ndp->datagram[i].wDatagramLength; i++) {
+    tud_ncm_receive_cb(receive_ntb + ndp->datagram[i].wDatagramIndex, ndp->datagram[i].wDatagramLength);
+  }
+
+  ncm_receive_renew();
+}
+
+bool ncmd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+{
+  (void) rhport;
+  (void) result;
+
+  /* new datagram receive_ntb */
+  if (ep_addr == ncm_interface.ep_out )
+  {
+    handle_incoming_datagram(xferred_bytes);
+  }
+
+  /* data transmission finished */
+  if (ep_addr == ncm_interface.ep_in )
+  {
+    if (ncm_interface.transferring) {
+      ncm_interface.transferring = false;
+    }
+
+    // If there are datagrams queued up that we tried to send while this NTB was being emitted, send them now
+    if (ncm_interface.datagram_count) {
+      ncm_start_tx();
+    }
+  }
+
+  if (ep_addr == ncm_interface.ep_notif )
+  {
+    ncm_interface.report_pending = false;
+    ncm_report();
+  }
+
+  return true;
+}
+
+bool tud_ncm_xmit(void *arg, uint16_t size, void (*flatten)(void *, uint8_t *, uint16_t)) {
+  transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
+
+  if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) {
+    return false;
+  }
+
+  size_t next_datagram_offset = ncm_interface.next_datagram_offset;
+  if (next_datagram_offset + size > ncm_interface.ntb_in_size) {
+    return false;
+  }
+
+  flatten(arg, ntb->data + next_datagram_offset, size);
+
+  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = ncm_interface.next_datagram_offset;
+  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = size;
+
+  ncm_interface.datagram_count++;
+  next_datagram_offset += size;
+
+  // round up so the next datagram is aligned correctly
+  next_datagram_offset += (CFG_TUD_NCM_ALIGNMENT - 1);
+  next_datagram_offset -= (next_datagram_offset % CFG_TUD_NCM_ALIGNMENT);
+
+  ncm_interface.next_datagram_offset = next_datagram_offset;
+
+  ncm_start_tx();
+
+  return true;
+}
+
+#endif
\ No newline at end of file
diff --git a/src/class/cdc/cdc_ncm_device.h b/src/class/cdc/cdc_ncm_device.h
new file mode 100644
index 000000000..1c767cad2
--- /dev/null
+++ b/src/class/cdc/cdc_ncm_device.h
@@ -0,0 +1,88 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_CDC_NCM_DEVICE_H_
+#define _TUSB_CDC_NCM_DEVICE_H_
+
+#include "common/tusb_common.h"
+#include "device/usbd.h"
+#include "cdc.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef CFG_TUD_NCM_EP_BUFSIZE
+#define CFG_TUD_NCM_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#endif
+
+#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
+#define CFG_TUD_NCM_IN_NTB_MAX_SIZE 3200
+#endif
+
+#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE
+#define CFG_TUD_NCM_OUT_NTB_MAX_SIZE 3200
+#endif
+
+#ifndef CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
+#define CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB 8
+#endif
+
+#ifndef CFG_TUD_NCM_ALIGNMENT
+#define CFG_TUD_NCM_ALIGNMENT 4
+#endif
+
+/**
+ * Transmit data. Returns true if successful, false if the packet was rejected (transmit buffer full,
+ * interface not up).
+ *
+ * This is structured with a callback to avoid the need for multiple copies; some network stacks,
+ * including LwIP, allow for non-contiguous buffers and provide a function to flatten them. In the
+ * LwIP case, a thin wrapper around pbuf_copy_partial() can be passed here.
+ */
+bool tud_ncm_xmit(void *arg, uint16_t size, void (*flatten)(void *arg, uint8_t *buffer, uint16_t size));
+
+//--------------------------------------------------------------------+
+// Application Callback API
+//--------------------------------------------------------------------+
+void tud_ncm_receive_cb(uint8_t *data, size_t length);
+void tud_ncm_link_state_cb(bool state);
+
+//--------------------------------------------------------------------+
+// INTERNAL USBD-CLASS DRIVER API
+//--------------------------------------------------------------------+
+void     ncmd_init             (void);
+void     ncmd_reset            (uint8_t rhport);
+uint16_t ncmd_open             (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
+bool     ncmd_control_request  (uint8_t rhport, tusb_control_request_t const * request);
+bool     ncmd_control_complete (uint8_t rhport, tusb_control_request_t const * request);
+bool     ncmd_xfer_cb          (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CDC_NCM_DEVICE_H_ */
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 90edc3dde..2edcf79f3 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -220,6 +220,19 @@ static usbd_class_driver_t const _usbd_driver[] =
       .sof              = NULL
   },
   #endif
+
+  #if CFG_TUD_NCM
+  {
+      DRIVER_NAME("NCM")
+      .init             = ncmd_init,
+      .reset            = ncmd_reset,
+      .open             = ncmd_open,
+      .control_request  = ncmd_control_request,
+      .control_complete = ncmd_control_complete,
+      .xfer_cb          = ncmd_xfer_cb,
+      .sof              = NULL
+  },
+  #endif
 };
 
 enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) };
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 0a446fdc2..45caa7871 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -671,6 +671,39 @@ TU_ATTR_WEAK bool tud_vendor_control_complete_cb(uint8_t rhport, tusb_control_re
   TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \
   TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__)
 
+
+//------------- CDC-NCM -------------//
+
+// Length of template descriptor
+#define TUD_CDC_NCM_DESC_LEN  (8+9+5+5+13+6+7+9+9+7+7)
+
+// CDC-ECM Descriptor Template
+// Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size.
+#define TUD_CDC_NCM_DESCRIPTOR(_itfnum, _desc_stridx, _mac_stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize, _maxsegmentsize) \
+  /* Interface Association */\
+  8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, 0,\
+  /* CDC Control Interface */\
+  9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, _desc_stridx,\
+  /* CDC-NCM Header */\
+  5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110),\
+  /* CDC-NCM Union */\
+  5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\
+  /* CDC-ECM Functional Descriptor */\
+  13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0, \
+  /* CDC-ECM Functional Descriptor */\
+  6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, \
+  /* Endpoint Notification */\
+  7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1,\
+  /* CDC Data Interface (default inactive) */\
+  9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 1, 0,\
+  /* CDC Data Interface (alternative active) */\
+  9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, 1, 0,\
+  /* Endpoint In */\
+  7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\
+  /* Endpoint Out */\
+  7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/tusb.h b/src/tusb.h
index 8b0dd103c..d4a692d4a 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -103,6 +103,10 @@
   #if CFG_TUD_BTH
     #include "class/bth/bth_device.h"
   #endif
+
+  #if CFG_TUD_NCM
+    #include "class/cdc/cdc_ncm_device.h"
+  #endif
 #endif
 
 

From a3d6e8fc52db0d1272290a7d5cb7963909254ad5 Mon Sep 17 00:00:00 2001
From: Jacob Potter <jacob@j4cbo.com>
Date: Wed, 4 Nov 2020 21:18:44 -0700
Subject: [PATCH 0002/2085] Add default for CFG_TUD_NCM

---
 src/tusb_option.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 393940282..b1ce62768 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -237,6 +237,10 @@
   #define CFG_TUD_BTH             0
 #endif
 
+#ifndef CFG_TUD_NCM
+  #define CFG_TUD_NCM             0
+#endif
+
 //--------------------------------------------------------------------
 // HOST OPTIONS
 //--------------------------------------------------------------------

From a3fdcbdf160a7780240e8b669826a917dce877f0 Mon Sep 17 00:00:00 2001
From: Jacob Potter <jacob@j4cbo.com>
Date: Wed, 4 Nov 2020 23:53:03 -0700
Subject: [PATCH 0003/2085] Just leave the endpoints open, instead of
 closing/reopening

---
 src/class/cdc/cdc_ncm_device.c | 46 +++++++++++-----------------------
 1 file changed, 15 insertions(+), 31 deletions(-)

diff --git a/src/class/cdc/cdc_ncm_device.c b/src/class/cdc/cdc_ncm_device.c
index e6d65171d..e1759ff2f 100644
--- a/src/class/cdc/cdc_ncm_device.c
+++ b/src/class/cdc/cdc_ncm_device.c
@@ -51,11 +51,6 @@ typedef struct
   uint8_t ep_in;
   uint8_t ep_out;
 
-  // Endpoint descriptor use to open/close when receving SetInterface
-  // TODO since configuration descriptor may not be long-lived memory, we should
-  // keep a copy of endpoint attribute instead
-  uint8_t const * ecm_desc_epdata;
-
   enum {
     REPORT_SPEED,
     REPORT_CONNECTED,
@@ -290,9 +285,7 @@ uint16_t ncmd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
   // Pair of endpoints
   TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0);
 
-  // ECM by default is in-active, save the endpoint attribute
-  // to open later when receive_ntb setInterface
-  ncm_interface.ecm_desc_epdata = p_desc;
+  TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) );
 
   drv_len += 2*sizeof(tusb_desc_endpoint_t);
 
@@ -348,33 +341,22 @@ bool ncmd_control_request(uint8_t rhport, tusb_control_request_t const * request
           // Only valid for Data Interface with Alternate is either 0 or 1
           TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum && req_alt < 2);
 
-          ncm_interface.itf_data_alt = req_alt;
+          if (req_alt != ncm_interface.itf_data_alt) {
+            ncm_interface.itf_data_alt = req_alt;
 
-          if ( ncm_interface.itf_data_alt )
-          {
-            // TODO since we don't actually close endpoint
-            // hack here to not re-open it
-            if (ncm_interface.ep_in == 0 && ncm_interface.ep_out == 0)
-            {
-              TU_ASSERT(ncm_interface.ecm_desc_epdata);
-              TU_ASSERT( usbd_open_edpt_pair(rhport, ncm_interface.ecm_desc_epdata, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) );
-
-              // TODO set flag indicating tx allowed?
-              ncm_receive_renew(); // prepare for incoming datagrams
-              tud_ncm_link_state_cb(true);
+            if (ncm_interface.itf_data_alt) {
+              if (!usbd_edpt_busy(rhport, ncm_interface.ep_out)) {
+                ncm_receive_renew(); // prepare for incoming datagrams
+              }
+              if (!ncm_interface.report_pending) {
+                ncm_report();
+              }
             }
-          } else {
-            // TODO close the endpoint pair
-            // For now pretend that we did, this should have no harm since host won't try to
-            // communicate with the endpoints again
-            // ncm_interface.ep_in = ncm_interface.ep_out = 0
-            // ncm_interface.report_pending = 0;
+
+            tud_ncm_link_state_cb(ncm_interface.itf_data_alt);
           }
 
           tud_control_status(rhport, request);
-
-          if (!ncm_interface.report_pending) ncm_report();
-
         }
           break;
 
@@ -445,7 +427,7 @@ bool ncmd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
     }
 
     // If there are datagrams queued up that we tried to send while this NTB was being emitted, send them now
-    if (ncm_interface.datagram_count) {
+    if (ncm_interface.datagram_count && ncm_interface.itf_data_alt == 1) {
       ncm_start_tx();
     }
   }
@@ -462,6 +444,8 @@ bool ncmd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
 bool tud_ncm_xmit(void *arg, uint16_t size, void (*flatten)(void *, uint8_t *, uint16_t)) {
   transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
 
+  TU_VERIFY(ncm_interface.itf_data_alt == 1);
+
   if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) {
     return false;
   }

From 377f8ce76f98ab199d808a263023432649266372 Mon Sep 17 00:00:00 2001
From: Jacob Potter <jacob@j4cbo.com>
Date: Thu, 5 Nov 2020 10:18:29 -0700
Subject: [PATCH 0004/2085] Log on full NTBs

---
 src/class/cdc/cdc_ncm_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/class/cdc/cdc_ncm_device.c b/src/class/cdc/cdc_ncm_device.c
index e1759ff2f..4698fa9c2 100644
--- a/src/class/cdc/cdc_ncm_device.c
+++ b/src/class/cdc/cdc_ncm_device.c
@@ -447,11 +447,13 @@ bool tud_ncm_xmit(void *arg, uint16_t size, void (*flatten)(void *, uint8_t *, u
   TU_VERIFY(ncm_interface.itf_data_alt == 1);
 
   if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) {
+    TU_LOG2("NTB full [by count]\r\n");
     return false;
   }
 
   size_t next_datagram_offset = ncm_interface.next_datagram_offset;
   if (next_datagram_offset + size > ncm_interface.ntb_in_size) {
+    TU_LOG2("ntb full [by size]\r\n");
     return false;
   }
 

From 226efdcec0d880feb4af3995129b85fae9b8ddb8 Mon Sep 17 00:00:00 2001
From: Jacob Potter <jacob@j4cbo.com>
Date: Thu, 5 Nov 2020 18:14:56 -0700
Subject: [PATCH 0005/2085] Reduce excessive poll rate on interrupt endpoint

---
 src/device/usbd.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/usbd.h b/src/device/usbd.h
index 45caa7871..c547ceeee 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -693,7 +693,7 @@ TU_ATTR_WEAK bool tud_vendor_control_complete_cb(uint8_t rhport, tusb_control_re
   /* CDC-ECM Functional Descriptor */\
   6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, \
   /* Endpoint Notification */\
-  7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1,\
+  7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 50,\
   /* CDC Data Interface (default inactive) */\
   9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 1, 0,\
   /* CDC Data Interface (alternative active) */\

From 3158b323d8d701f70b80dca986f8b0e8e60eba97 Mon Sep 17 00:00:00 2001
From: Jacob Potter <jacob@j4cbo.com>
Date: Sun, 3 Jan 2021 15:16:54 -0700
Subject: [PATCH 0006/2085] Adapt to new control xfer callback

---
 src/class/cdc/cdc_ncm_device.c | 12 +++---------
 src/class/cdc/cdc_ncm_device.h |  3 +--
 src/device/usbd.c              |  3 +--
 3 files changed, 5 insertions(+), 13 deletions(-)

diff --git a/src/class/cdc/cdc_ncm_device.c b/src/class/cdc/cdc_ncm_device.c
index 4698fa9c2..a8983dd91 100644
--- a/src/class/cdc/cdc_ncm_device.c
+++ b/src/class/cdc/cdc_ncm_device.c
@@ -292,14 +292,6 @@ uint16_t ncmd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
   return drv_len;
 }
 
-// Invoked when class request DATA stage is finished.
-bool ncmd_control_complete(uint8_t rhport, tusb_control_request_t const * request)
-{
-  (void) rhport;
-  (void) request;
-  return true;
-}
-
 static void ncm_report()
 {
   if (ncm_interface.report_state == REPORT_SPEED) {
@@ -317,8 +309,10 @@ static void ncm_report()
 
 // Handle class control request
 // return false to stall control endpoint (e.g unsupported request)
-bool ncmd_control_request(uint8_t rhport, tusb_control_request_t const * request)
+bool ncmd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
 {
+  if ( stage != CONTROL_STAGE_SETUP ) return true;
+
   switch ( request->bmRequestType_bit.type )
   {
     case TUSB_REQ_TYPE_STANDARD:
diff --git a/src/class/cdc/cdc_ncm_device.h b/src/class/cdc/cdc_ncm_device.h
index 1c767cad2..e6c7237b1 100644
--- a/src/class/cdc/cdc_ncm_device.h
+++ b/src/class/cdc/cdc_ncm_device.h
@@ -77,8 +77,7 @@ void tud_ncm_link_state_cb(bool state);
 void     ncmd_init             (void);
 void     ncmd_reset            (uint8_t rhport);
 uint16_t ncmd_open             (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
-bool     ncmd_control_request  (uint8_t rhport, tusb_control_request_t const * request);
-bool     ncmd_control_complete (uint8_t rhport, tusb_control_request_t const * request);
+bool     ncmd_control_xfer_cb  (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 bool     ncmd_xfer_cb          (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
 #ifdef __cplusplus
diff --git a/src/device/usbd.c b/src/device/usbd.c
index e2110b7a8..c6124263f 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -217,8 +217,7 @@ static usbd_class_driver_t const _usbd_driver[] =
       .init             = ncmd_init,
       .reset            = ncmd_reset,
       .open             = ncmd_open,
-      .control_request  = ncmd_control_request,
-      .control_complete = ncmd_control_complete,
+      .control_xfer_cb  = ncmd_control_xfer_cb,
       .xfer_cb          = ncmd_xfer_cb,
       .sof              = NULL
   },

From b4f092ec74d85d4e5567ebb45e1bd0dec20f0e02 Mon Sep 17 00:00:00 2001
From: Wini-Buh <info@winformatik.ch>
Date: Sat, 29 May 2021 21:23:39 +0200
Subject: [PATCH 0007/2085] Adaptations for Renesas CCRX toolchain and Rx72N
 controller performed

---
 src/class/cdc/cdc.h                  |  48 ++++++++++-
 src/class/cdc/cdc_device.c           |  23 +++--
 src/class/cdc/cdc_device.h           |  57 +++++++++++++
 src/common/tusb_compiler.h           |  92 +++++++++++++++++++-
 src/common/tusb_types.h              |  39 ++++++++-
 src/device/dcd.h                     |  42 +++++++--
 src/device/usbd.c                    |  67 ++++++++++-----
 src/device/usbd.h                    |  74 +++++++++++++++-
 src/device/usbd_control.c            |  15 +++-
 src/device/usbd_pvt.h                |  11 +++
 src/osal/osal_freertos.h             |  25 ++++++
 src/portable/renesas/usba/dcd_usba.c | 122 ++++++++++++++++++++++-----
 src/tusb_option.h                    |   1 +
 13 files changed, 543 insertions(+), 73 deletions(-)

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index f59bf0f1a..e5af9fc0c 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -216,6 +216,7 @@ typedef enum
 //--------------------------------------------------------------------+
 
 /// Header Functional Descriptor (Communication Interface)
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
@@ -223,8 +224,10 @@ typedef struct TU_ATTR_PACKED
   uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUNC_DESC_
   uint16_t bcdCDC            ; ///< CDC release number in Binary-Coded Decimal
 }cdc_desc_func_header_t;
+TU_PACK_STRUCT_END
 
 /// Union Functional Descriptor (Communication Interface)
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength                  ; ///< Size of this descriptor in bytes.
@@ -233,17 +236,21 @@ typedef struct TU_ATTR_PACKED
   uint8_t bControlInterface        ; ///< Interface number of Communication Interface
   uint8_t bSubordinateInterface    ; ///< Array of Interface number of Data Interface
 }cdc_desc_func_union_t;
+TU_PACK_STRUCT_END
 
 #define cdc_desc_func_union_n_t(no_slave)\
- struct TU_ATTR_PACKED { \
+ TU_PACK_STRUCT_BEGIN                      \
+ struct TU_ATTR_PACKED {                   \
   uint8_t bLength                         ;\
   uint8_t bDescriptorType                 ;\
   uint8_t bDescriptorSubType              ;\
   uint8_t bControlInterface               ;\
   uint8_t bSubordinateInterface[no_slave] ;\
-}
+}                                          \
+TU_PACK_STRUCT_END
 
 /// Country Selection Functional Descriptor (Communication Interface)
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength             ; ///< Size of this descriptor in bytes.
@@ -252,15 +259,18 @@ typedef struct TU_ATTR_PACKED
   uint8_t iCountryCodeRelDate ; ///< Index of a string giving the release date for the implemented ISO 3166 Country Codes.
   uint16_t wCountryCode       ; ///< Country code in the format as defined in [ISO3166], release date as specified inoffset 3 for the first supported country.
 }cdc_desc_func_country_selection_t;
+TU_PACK_STRUCT_END
 
 #define cdc_desc_func_country_selection_n_t(no_country) \
-  struct TU_ATTR_PACKED {\
+  TU_PACK_STRUCT_BEGIN               \
+  struct TU_ATTR_PACKED {            \
   uint8_t bLength                   ;\
   uint8_t bDescriptorType           ;\
   uint8_t bDescriptorSubType        ;\
   uint8_t iCountryCodeRelDate       ;\
   uint16_t wCountryCode[no_country] ;\
-}
+}                                    \
+TU_PACK_STRUCT_END
 
 //--------------------------------------------------------------------+
 // PUBLIC SWITCHED TELEPHONE NETWORK (PSTN) SUBCLASS
@@ -268,22 +278,28 @@ typedef struct TU_ATTR_PACKED
 
 /// \brief Call Management Functional Descriptor
 /// \details This functional descriptor describes the processing of calls for the Communications Class interface.
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
   uint8_t bDescriptorType    ; ///< Descriptor Type, must be Class-Specific
   uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
 
+  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     uint8_t handle_call    : 1; ///< 0 - Device sends/receives call management information only over the Communications Class interface. 1 - Device can send/receive call management information over a Data Class interface.
     uint8_t send_recv_call : 1; ///< 0 - Device does not handle call management itself. 1 - Device handles call management itself.
     uint8_t TU_RESERVED    : 6;
   } bmCapabilities;
+  TU_BIT_FIELD_ORDER_END
 
   uint8_t bDataInterface;
 }cdc_desc_func_call_management_t;
+TU_PACK_STRUCT_END
 
 
+TU_PACK_STRUCT_BEGIN
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t support_comm_request                    : 1; ///< Device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature.
@@ -292,11 +308,14 @@ typedef struct TU_ATTR_PACKED
   uint8_t support_notification_network_connection : 1; ///< Device supports the notification Network_Connection.
   uint8_t TU_RESERVED                             : 4;
 }cdc_acm_capability_t;
+TU_BIT_FIELD_ORDER_END
+TU_PACK_STRUCT_END
 
 TU_VERIFY_STATIC(sizeof(cdc_acm_capability_t) == 1, "mostly problem with compiler");
 
 /// \brief Abstract Control Management Functional Descriptor
 /// \details This functional descriptor describes the commands supported by by the Communications Class interface with SubClass code of \ref CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength                  ; ///< Size of this descriptor in bytes.
@@ -304,25 +323,31 @@ typedef struct TU_ATTR_PACKED
   uint8_t bDescriptorSubType       ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
   cdc_acm_capability_t bmCapabilities ;
 }cdc_desc_func_acm_t;
+TU_PACK_STRUCT_END
 
 /// \brief Direct Line Management Functional Descriptor
 /// \details This functional descriptor describes the commands supported by the Communications Class interface with SubClass code of \ref CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
   uint8_t bDescriptorType    ; ///< Descriptor Type, must be Class-Specific
   uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     uint8_t require_pulse_setup   : 1; ///< Device requires extra Pulse_Setup request during pulse dialing sequence to disengage holding circuit.
     uint8_t support_aux_request   : 1; ///< Device supports the request combination of Set_Aux_Line_State, Ring_Aux_Jack, and notification Aux_Jack_Hook_State.
     uint8_t support_pulse_request : 1; ///< Device supports the request combination of Pulse_Setup, Send_Pulse, and Set_Pulse_Time.
     uint8_t TU_RESERVED           : 5;
   } bmCapabilities;
+  TU_BIT_FIELD_ORDER_END
 }cdc_desc_func_direct_line_management_t;
+TU_PACK_STRUCT_END
 
 /// \brief Telephone Ringer Functional Descriptor
 /// \details The Telephone Ringer functional descriptor describes the ringer capabilities supported by the Communications Class interface,
 /// with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
@@ -331,31 +356,38 @@ typedef struct TU_ATTR_PACKED
   uint8_t bRingerVolSteps    ;
   uint8_t bNumRingerPatterns ;
 }cdc_desc_func_telephone_ringer_t;
+TU_PACK_STRUCT_END
 
 /// \brief Telephone Operational Modes Functional Descriptor
 /// \details The Telephone Operational Modes functional descriptor describes the operational modes supported by
 /// the Communications Class interface, with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
   uint8_t bDescriptorType    ; ///< Descriptor Type, must be Class-Specific
   uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     uint8_t simple_mode           : 1;
     uint8_t standalone_mode       : 1;
     uint8_t computer_centric_mode : 1;
     uint8_t TU_RESERVED           : 5;
   } bmCapabilities;
+  TU_BIT_FIELD_ORDER_END
 }cdc_desc_func_telephone_operational_modes_t;
+TU_PACK_STRUCT_END
 
 /// \brief Telephone Call and Line State Reporting Capabilities Descriptor
 /// \details The Telephone Call and Line State Reporting Capabilities functional descriptor describes the abilities of a
 /// telephone device to report optional call and line states.
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
   uint8_t bDescriptorType    ; ///< Descriptor Type, must be Class-Specific
   uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     uint32_t interrupted_dialtone   : 1; ///< 0 : Reports only dialtone (does not differentiate between normal and interrupted dialtone). 1 : Reports interrupted dialtone in addition to normal dialtone
     uint32_t ringback_busy_fastbusy : 1; ///< 0 : Reports only dialing state. 1 : Reports ringback, busy, and fast busy states.
@@ -365,7 +397,9 @@ typedef struct TU_ATTR_PACKED
     uint32_t line_state_change      : 1; ///< 0 : Does not support line state change notification. 1 : Does support line state change notification
     uint32_t TU_RESERVED            : 26;
   } bmCapabilities;
+  TU_BIT_FIELD_ORDER_END
 }cdc_desc_func_telephone_call_state_reporting_capabilities_t;
+TU_PACK_STRUCT_END
 
 static inline uint8_t cdc_functional_desc_typeof(uint8_t const * p_desc)
 {
@@ -375,6 +409,7 @@ static inline uint8_t cdc_functional_desc_typeof(uint8_t const * p_desc)
 //--------------------------------------------------------------------+
 // Requests
 //--------------------------------------------------------------------+
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint32_t bit_rate;
@@ -382,15 +417,20 @@ typedef struct TU_ATTR_PACKED
   uint8_t  parity;    ///< 0: None - 1: Odd - 2: Even - 3: Mark - 4: Space
   uint8_t  data_bits; ///< can be 5, 6, 7, 8 or 16
 } cdc_line_coding_t;
+TU_PACK_STRUCT_END
 
 TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct");
 
+TU_PACK_STRUCT_BEGIN
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint16_t dte_is_present : 1; ///< Indicates to DCE if DTE is presentor not. This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR.
   uint16_t half_duplex_carrier_control : 1;
   uint16_t : 14;
 } cdc_line_control_state_t;
+TU_BIT_FIELD_ORDER_END
+TU_PACK_STRUCT_END
 
 TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct");
 
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index f5853fddb..cf2ec64c8 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -31,6 +31,15 @@
 #include "cdc_device.h"
 #include "device/usbd_pvt.h"
 
+#if defined(TU_HAS_NO_ATTR_WEAK)
+static void (*const MAKE_WEAK_FUNC(tud_cdc_rx_cb))(uint8_t) = TUD_CDC_RX_CB;
+static void (*const MAKE_WEAK_FUNC(tud_cdc_rx_wanted_cb))(uint8_t, char) = TUD_CDC_RX_WANTED_CB;
+static void (*const MAKE_WEAK_FUNC(tud_cdc_tx_complete_cb))(uint8_t) = TUD_CDC_TX_COMPLETE_CB;
+static void (*const MAKE_WEAK_FUNC(tud_cdc_line_state_cb))(uint8_t, bool, bool) = TUD_CDC_LINE_STATE_CB;
+static void (*const MAKE_WEAK_FUNC(tud_cdc_line_coding_cb))(uint8_t, cdc_line_coding_t const*) = TUD_CDC_LINE_CODING_CB;
+static void (*const MAKE_WEAK_FUNC(tud_cdc_send_break_cb))(uint8_t, uint16_t) = TUD_CDC_SEND_BREAK_CB;
+#endif
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -359,7 +368,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
       }
       else if ( stage == CONTROL_STAGE_ACK)
       {
-        if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
+        if ( MAKE_WEAK_FUNC(tud_cdc_line_coding_cb) ) MAKE_WEAK_FUNC(tud_cdc_line_coding_cb)(itf, &p_cdc->line_coding);
       }
     break;
 
@@ -394,7 +403,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         TU_LOG2("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
 
         // Invoke callback
-        if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
+        if ( MAKE_WEAK_FUNC(tud_cdc_line_state_cb) ) MAKE_WEAK_FUNC(tud_cdc_line_state_cb)(itf, dtr, rts);
       }
     break;
     case CDC_REQUEST_SEND_BREAK:
@@ -405,7 +414,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
       else if (stage == CONTROL_STAGE_ACK)
       {
         TU_LOG2("  Send Break\r\n");
-        if ( tud_cdc_send_break_cb ) tud_cdc_send_break_cb(itf, request->wValue);
+        if ( MAKE_WEAK_FUNC(tud_cdc_send_break_cb) ) MAKE_WEAK_FUNC(tud_cdc_send_break_cb)(itf, request->wValue);
       }
     break;
 
@@ -436,19 +445,19 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
     tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, xferred_bytes);
     
     // Check for wanted char and invoke callback if needed
-    if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) )
+    if ( MAKE_WEAK_FUNC(tud_cdc_rx_wanted_cb) && (((signed char) p_cdc->wanted_char) != -1) )
     {
       for ( uint32_t i = 0; i < xferred_bytes; i++ )
       {
         if ( (p_cdc->wanted_char == p_cdc->epout_buf[i]) && !tu_fifo_empty(&p_cdc->rx_ff) )
         {
-          tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char);
+          MAKE_WEAK_FUNC(tud_cdc_rx_wanted_cb)(itf, p_cdc->wanted_char);
         }
       }
     }
     
     // invoke receive callback (if there is still data)
-    if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff) ) tud_cdc_rx_cb(itf);
+    if (MAKE_WEAK_FUNC(tud_cdc_rx_cb) && !tu_fifo_empty(&p_cdc->rx_ff) ) MAKE_WEAK_FUNC(tud_cdc_rx_cb)(itf);
     
     // prepare for OUT transaction
     _prep_out_transaction(p_cdc);
@@ -460,7 +469,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   if ( ep_addr == p_cdc->ep_in )
   {
     // invoke transmit callback to possibly refill tx fifo
-    if ( tud_cdc_tx_complete_cb ) tud_cdc_tx_complete_cb(itf);
+    if ( MAKE_WEAK_FUNC(tud_cdc_tx_complete_cb) ) MAKE_WEAK_FUNC(tud_cdc_tx_complete_cb)(itf);
 
     if ( 0 == tud_cdc_n_write_flush(itf) )
     {
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index 986585c5b..ed816b707 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -130,6 +130,7 @@ static inline bool     tud_cdc_write_clear     (void);
 // Application Callback API (weak is optional)
 //--------------------------------------------------------------------+
 
+#if !defined(TU_HAS_NO_ATTR_WEAK)
 // Invoked when received new data
 TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf);
 
@@ -148,6 +149,62 @@ TU_ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* p
 // Invoked when received send break
 TU_ATTR_WEAK void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms);
 
+#else
+ #if  ADD_WEAK_FUNC_TUD_CDC_RX_CB
+  #define TUD_CDC_RX_CB  tud_cdc_rx_cb
+ #endif
+ #ifndef TUD_CDC_RX_CB
+  #define TUD_CDC_RX_CB    NULL
+ #else
+  extern void TUD_CDC_RX_CB(uint8_t itf);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_CDC_RX_WANTED_CB
+  #define TUD_CDC_RX_WANTED_CB  tud_cdc_rx_wanted_cb
+ #endif
+ #ifndef TUD_CDC_RX_WANTED_CB
+  #define TUD_CDC_RX_WANTED_CB    NULL
+ #else
+  extern void TUD_CDC_RX_WANTED_CB(uint8_t itf, char wanted_char);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_CDC_TX_COMPLETE_CB
+  #define TUD_CDC_TX_COMPLETE_CB  tud_cdc_tx_complete_cb
+ #endif
+ #ifndef TUD_CDC_TX_COMPLETE_CB
+  #define TUD_CDC_TX_COMPLETE_CB    NULL
+ #else
+  extern void TUD_CDC_TX_COMPLETE_CB(uint8_t itf);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_CDC_LINE_STATE_CB
+  #define TUD_CDC_LINE_STATE_CB  tud_cdc_line_state_cb
+ #endif
+ #ifndef TUD_CDC_LINE_STATE_CB
+  #define TUD_CDC_LINE_STATE_CB    NULL
+ #else
+  extern void TUD_CDC_LINE_STATE_CB(uint8_t itf, bool dtr, bool rts);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_CDC_LINE_CODING_CB
+  #define TUD_CDC_LINE_CODING_CB  tud_cdc_line_coding_cb
+ #endif
+ #ifndef TUD_CDC_LINE_CODING_CB
+  #define TUD_CDC_LINE_CODING_CB    NULL
+ #else
+  extern void TUD_CDC_LINE_CODING_CB(uint8_t itf, cdc_line_coding_t const* p_line_coding);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_CDC_SEND_BREAK_CB
+  #define TUD_CDC_SEND_BREAK_CB  tud_cdc_send_break_cb
+ #endif
+ #ifndef TUD_CDC_SEND_BREAK_CB
+  #define TUD_CDC_SEND_BREAK_CB    NULL
+ #else
+  extern void TUD_CDC_SEND_BREAK_CB(uint8_t itf, uint16_t duration_ms);
+ #endif
+#endif
+
 //--------------------------------------------------------------------+
 // Inline Functions
 //--------------------------------------------------------------------+
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 679060b20..508bb126e 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -48,6 +48,8 @@
   #define TU_VERIFY_STATIC   _Static_assert
 #elif defined (__cplusplus) && __cplusplus >= 201103L
   #define TU_VERIFY_STATIC   static_assert
+#elif defined(__CCRX__)
+  #define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT(Line, __LINE__)[(const_expr) ? 1 : 0];
 #else
   #define TU_VERIFY_STATIC(const_expr, _mess) enum { TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1/(!!(const_expr)) }
 #endif
@@ -62,6 +64,9 @@
 // Compiler porting with Attribute and Endian
 //--------------------------------------------------------------------+
 
+// define the standard definition of this macro to construct a "weak" function name
+#define MAKE_WEAK_FUNC(func_name)  func_name
+
 // TODO refactor since __attribute__ is supported across many compiler
 #if defined(__GNUC__)
   #define TU_ATTR_ALIGNED(Bytes)        __attribute__ ((aligned(Bytes)))
@@ -73,9 +78,17 @@
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))             // Function/Variable is meant to be used
 
+  #define TU_PACK_STRUCT_BEGIN
+  #define TU_PACK_STRUCT_END
+
+  #define TU_BIT_FIELD_ORDER_BEGIN
+  #define TU_BIT_FIELD_ORDER_END
+
   // Endian conversion use well-known host to network (big endian) naming
   #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
     #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
+    #define TU_ENDIAN_LITTLE_BEGIN
+    #define TU_ENDIAN_LITTLE_END
   #else
     #define TU_BYTE_ORDER TU_BIG_ENDIAN
   #endif
@@ -123,6 +136,77 @@
 
   #define TU_BSWAP16(u16) (__iar_builtin_REV16(u16))
   #define TU_BSWAP32(u32) (__iar_builtin_REV(u32))
+
+#elif defined(__CCRX__)
+  #define TU_ATTR_ALIGNED(Bytes)
+  #define TU_ATTR_SECTION(sec_name)
+  #define TU_ATTR_PACKED
+  #define TU_ATTR_WEAK
+  #define TU_ATTR_ALWAYS_INLINE
+  #define TU_ATTR_DEPRECATED(mess)
+  #define TU_ATTR_UNUSED
+  #define TU_ATTR_USED
+
+  #define TU_PACK_STRUCT_BEGIN _Pragma("pack")
+  #define TU_PACK_STRUCT_END _Pragma("packoption")
+
+  #define TU_BIT_FIELD_ORDER_BEGIN _Pragma("bit_order right")
+  #define TU_BIT_FIELD_ORDER_END _Pragma("bit_order")
+
+  // Endian conversion use well-known host to network (big endian) naming
+  #if defined(__LIT)
+    #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
+    #define TU_ENDIAN_LITTLE_BEGIN
+    #define TU_ENDIAN_LITTLE_END
+  #else
+    #define TU_BYTE_ORDER TU_BIG_ENDIAN
+    #define TU_ENDIAN_LITTLE_BEGIN _Pragma("endian little")
+    #define TU_ENDIAN_LITTLE_END _Pragma("endian")
+  #endif
+
+  #define TU_BSWAP16(u16) ((unsigned short)_builtin_revw((unsigned long)u16))
+  #define TU_BSWAP32(u32) (_builtin_revl(u32))
+
+  /* activate the "aligned" emulation, because this toolchain does not know
+     the aligned attribute (or something similar yet) */
+  #define TU_HAS_NO_ATTR_ALIGNED
+
+  /* activate the "weak" function emulation, because this toolchain does not
+     know the weak attribute (or something similar yet) */
+  #define TU_HAS_NO_ATTR_WEAK
+
+  // make sure to define away the standard definition of this macro
+  #undef MAKE_WEAK_FUNC
+  // Helper macro to construct a "weak" function name
+  #define MAKE_WEAK_FUNC(func_name)  weak_ ## func_name
+
+  #if defined(TU_HAS_NO_ATTR_WEAK)
+  // "Weak function" emulation defined in cdc_device.h
+  #define ADD_WEAK_FUNC_TUD_CDC_RX_CB           0
+  #define ADD_WEAK_FUNC_TUD_CDC_RX_WANTED_CB    0
+  #define ADD_WEAK_FUNC_TUD_CDC_TX_COMPLETE_CB  0
+  #define ADD_WEAK_FUNC_TUD_CDC_LINE_STATE_CB   0
+  #define ADD_WEAK_FUNC_TUD_CDC_LINE_CODING_CB  0
+  #define ADD_WEAK_FUNC_TUD_CDC_SEND_BREAK_CB   0
+
+  // "Weak function" emulation defined in usbd_pvt.h
+  #define ADD_WEAK_FUNC_USBD_APP_DRIVER_GET_CB  0
+
+  // "Weak function" emulation defined in usbd.h
+  #define ADD_WEAK_FUNC_TUD_DESCRIPTOR_BOS_CB               0
+  #define ADD_WEAK_FUNC_TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB  0
+  #define ADD_WEAK_FUNC_TUD_MOUNT_CB                        0
+  #define ADD_WEAK_FUNC_TUD_UMOUNT_CB                       0
+  #define ADD_WEAK_FUNC_TUD_SUSPEND_CB                      0
+  #define ADD_WEAK_FUNC_TUD_RESUME_CB                       0
+  #define ADD_WEAK_FUNC_TUD_VENDOR_CONTROL_XFER_CB          0
+
+  // "Weak function" emulation defined in dcd.h
+  #define ADD_WEAK_FUNC_DCD_EDPT0_STATUS_COMPLETE  0
+  #define ADD_WEAK_FUNC_DCD_EDPT_CLOSE             0
+  #define ADD_WEAK_FUNC_DCD_EDPT_XFER_FIFO         0
+  #endif
+
 #else 
   #error "Compiler attribute porting is required"
 #endif
@@ -149,11 +233,11 @@
   #define tu_htonl(u32)  (u32)
   #define tu_ntohl(u32)  (u32)
 
-  #define tu_htole16(u16) (tu_bswap16(u16))
-  #define tu_le16toh(u16) (tu_bswap16(u16))
+  #define tu_htole16(u16) (TU_BSWAP16(u16))
+  #define tu_le16toh(u16) (TU_BSWAP16(u16))
 
-  #define tu_htole32(u32) (tu_bswap32(u32))
-  #define tu_le32toh(u32) (tu_bswap32(u32))
+  #define tu_htole32(u32) (TU_BSWAP32(u32))
+  #define tu_le32toh(u32) (TU_BSWAP32(u32))
 
 #else
   #error Byte order is undefined
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index ec58a3181..b20ea2974 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -263,6 +263,7 @@ enum
 //--------------------------------------------------------------------+
 
 /// USB Device Descriptor
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes.
@@ -283,10 +284,12 @@ typedef struct TU_ATTR_PACKED
 
   uint8_t  bNumConfigurations ; ///< Number of possible configurations.
 } tusb_desc_device_t;
+TU_PACK_STRUCT_END
 
 TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct");
 
 // USB Binary Device Object Store (BOS) Descriptor
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
@@ -294,8 +297,10 @@ typedef struct TU_ATTR_PACKED
   uint16_t wTotalLength    ; ///< Total length of data returned for this descriptor
   uint8_t  bNumDeviceCaps  ; ///< Number of device capability descriptors in the BOS
 } tusb_desc_bos_t;
+TU_PACK_STRUCT_END
 
 /// USB Configuration Descriptor
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength             ; ///< Size of this descriptor in bytes
@@ -308,10 +313,10 @@ typedef struct TU_ATTR_PACKED
   uint8_t  bmAttributes        ; ///< Configuration characteristics \n D7: Reserved (set to one)\n D6: Self-powered \n D5: Remote Wakeup \n D4...0: Reserved (reset to zero) \n D7 is reserved and must be set to one for historical reasons. \n A device configuration that uses power from the bus and a local source reports a non-zero value in bMaxPower to indicate the amount of bus power required and sets D6. The actual power source at runtime may be determined using the GetStatus(DEVICE) request (see USB 2.0 spec Section 9.4.5). \n If a device configuration supports remote wakeup, D5 is set to one.
   uint8_t  bMaxPower           ; ///< Maximum power consumption of the USB device from the bus in this specific configuration when the device is fully operational. Expressed in 2 mA units (i.e., 50 = 100 mA).
 } tusb_desc_configuration_t;
-
-TU_VERIFY_STATIC( sizeof(tusb_desc_configuration_t) == 9, "size is not correct");
+TU_PACK_STRUCT_END
 
 /// USB Interface Descriptor
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes
@@ -325,8 +330,10 @@ typedef struct TU_ATTR_PACKED
   uint8_t  bInterfaceProtocol ; ///< Protocol code (assigned by the USB). \n These codes are qualified by the value of the bInterfaceClass and the bInterfaceSubClass fields. If an interface supports class-specific requests, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use a class-specific protocol on this interface. \li If this field is set to FFH, the device uses a vendor-specific protocol for this interface.
   uint8_t  iInterface         ; ///< Index of string descriptor describing this interface
 } tusb_desc_interface_t;
+TU_PACK_STRUCT_END
 
 /// USB Endpoint Descriptor
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength          ; ///< Size of this descriptor in bytes
@@ -334,23 +341,32 @@ typedef struct TU_ATTR_PACKED
 
   uint8_t  bEndpointAddress ; ///< The address of the endpoint on the USB device described by this descriptor. The address is encoded as follows: \n Bit 3...0: The endpoint number \n Bit 6...4: Reserved, reset to zero \n Bit 7: Direction, ignored for control endpoints 0 = OUT endpoint 1 = IN endpoint.
 
+  TU_BIT_FIELD_ORDER_BEGIN
   struct TU_ATTR_PACKED {
     uint8_t xfer  : 2;
     uint8_t sync  : 2;
     uint8_t usage : 2;
     uint8_t       : 2;
   } bmAttributes     ; ///< This field describes the endpoint's attributes when it is configured using the bConfigurationValue. \n Bits 1..0: Transfer Type \n- 00 = Control \n- 01 = Isochronous \n- 10 = Bulk \n- 11 = Interrupt \n If not an isochronous endpoint, bits 5..2 are reserved and must be set to zero. If isochronous, they are defined as follows: \n Bits 3..2: Synchronization Type \n- 00 = No Synchronization \n- 01 = Asynchronous \n- 10 = Adaptive \n- 11 = Synchronous \n Bits 5..4: Usage Type \n- 00 = Data endpoint \n- 01 = Feedback endpoint \n- 10 = Implicit feedback Data endpoint \n- 11 = Reserved \n Refer to Chapter 5 of USB 2.0 specification for more information. \n All other bits are reserved and must be reset to zero. Reserved bits must be ignored by the host.
+  TU_BIT_FIELD_ORDER_END
 
   struct TU_ATTR_PACKED {
+#if defined(__CCRX__)
+    //FIXME the original defined bit field has a problem with the CCRX toolchain, so only a size field is defined
+    uint16_t size;
+#else
     uint16_t size           : 11; ///< Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. \n For isochronous endpoints, this value is used to reserve the bus time in the schedule, required for the per-(micro)frame data payloads. The pipe may, on an ongoing basis, actually use less bandwidth than that reserved. The device reports, if necessary, the actual bandwidth used via its normal, non-USB defined mechanisms. \n For all endpoints, bits 10..0 specify the maximum packet size (in bytes). \n For high-speed isochronous and interrupt endpoints: \n Bits 12..11 specify the number of additional transaction opportunities per microframe: \n- 00 = None (1 transaction per microframe) \n- 01 = 1 additional (2 per microframe) \n- 10 = 2 additional (3 per microframe) \n- 11 = Reserved \n Bits 15..13 are reserved and must be set to zero.
     uint16_t hs_period_mult : 2;
     uint16_t TU_RESERVED    : 3;
+#endif
   }wMaxPacketSize;
 
   uint8_t  bInterval        ; ///< Interval for polling endpoint for data transfers. Expressed in frames or microframes depending on the device operating speed (i.e., either 1 millisecond or 125 us units). \n- For full-/high-speed isochronous endpoints, this value must be in the range from 1 to 16. The bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \n- For full-/low-speed interrupt endpoints, the value of this field may be from 1 to 255. \n- For high-speed interrupt endpoints, the bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value must be from 1 to 16. \n- For high-speed bulk/control OUT endpoints, the bInterval must specify the maximum NAK rate of the endpoint. A value of 0 indicates the endpoint never NAKs. Other values indicate at most 1 NAK each bInterval number of microframes. This value must be in the range from 0 to 255. \n Refer to Chapter 5 of USB 2.0 specification for more information.
 } tusb_desc_endpoint_t;
+TU_PACK_STRUCT_END
 
 /// USB Other Speed Configuration Descriptor
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength             ; ///< Size of descriptor
@@ -363,8 +379,10 @@ typedef struct TU_ATTR_PACKED
   uint8_t  bmAttributes        ; ///< Same as Configuration descriptor
   uint8_t  bMaxPower           ; ///< Same as Configuration descriptor
 } tusb_desc_other_speed_t;
+TU_PACK_STRUCT_END
 
 /// USB Device Qualifier Descriptor
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength            ; ///< Size of descriptor
@@ -378,8 +396,10 @@ typedef struct TU_ATTR_PACKED
   uint8_t  bNumConfigurations ; ///< Number of Other-speed Configurations
   uint8_t  bReserved          ; ///< Reserved for future use, must be zero
 } tusb_desc_device_qualifier_t;
+TU_PACK_STRUCT_END
 
 /// USB Interface Association Descriptor (IAD ECN)
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength           ; ///< Size of descriptor
@@ -394,16 +414,20 @@ typedef struct TU_ATTR_PACKED
 
   uint8_t iFunction         ; ///< Index of the string descriptor describing the interface association.
 } tusb_desc_interface_assoc_t;
+TU_PACK_STRUCT_END
 
 // USB String Descriptor
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType ; ///< Descriptor Type
   uint16_t unicode_string[];
 } tusb_desc_string_t;
+TU_PACK_STRUCT_END
 
 // USB Binary Device Object Store (BOS)
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength;
@@ -413,8 +437,10 @@ typedef struct TU_ATTR_PACKED
   uint8_t PlatformCapabilityUUID[16];
   uint8_t CapabilityData[];
 } tusb_desc_bos_platform_t;
+TU_PACK_STRUCT_END
 
 // USB WebuSB URL Descriptor
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength;
@@ -422,14 +448,17 @@ typedef struct TU_ATTR_PACKED
   uint8_t bScheme;
   char    url[];
 } tusb_desc_webusb_url_t;
+TU_PACK_STRUCT_END
 
 // DFU Functional Descriptor
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
 
   union {
+    TU_BIT_FIELD_ORDER_BEGIN
     struct TU_ATTR_PACKED {
       uint8_t bitCanDnload             : 1;
       uint8_t bitCanUpload             : 1;
@@ -437,6 +466,7 @@ typedef struct TU_ATTR_PACKED
       uint8_t bitWillDetach            : 1;
       uint8_t reserved                 : 4;
     } bmAttributes;
+    TU_BIT_FIELD_ORDER_END
 
     uint8_t bAttributes;
   };
@@ -445,17 +475,21 @@ typedef struct TU_ATTR_PACKED
   uint16_t wTransferSize;
   uint16_t bcdDFUVersion;
 } tusb_desc_dfu_functional_t;
+TU_PACK_STRUCT_END
 
 /*------------------------------------------------------------------*/
 /* Types
  *------------------------------------------------------------------*/
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED{
   union {
+    TU_BIT_FIELD_ORDER_BEGIN
     struct TU_ATTR_PACKED {
       uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.
       uint8_t type      :  2; ///< Request type tusb_request_type_t.
       uint8_t direction :  1; ///< Direction type. tusb_dir_t
     } bmRequestType_bit;
+    TU_BIT_FIELD_ORDER_END
 
     uint8_t bmRequestType;
   };
@@ -465,6 +499,7 @@ typedef struct TU_ATTR_PACKED{
   uint16_t wIndex;
   uint16_t wLength;
 } tusb_control_request_t;
+TU_PACK_STRUCT_END
 
 TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 71e88054c..fd87686bf 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -116,24 +116,54 @@ void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK;
 // Endpoint API
 //--------------------------------------------------------------------+
 
+#if !defined(TU_HAS_NO_ATTR_WEAK)
 // Invoked when a control transfer's status stage is complete.
 // May help DCD to prepare for next control transfer, this API is optional.
 void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) TU_ATTR_WEAK;
 
-// Configure endpoint's registers according to descriptor
-bool dcd_edpt_open            (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
-
 // Close an endpoint.
 // Since it is weak, caller must TU_ASSERT this function's existence before calling it.
 void dcd_edpt_close           (uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK;
 
-// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
-bool dcd_edpt_xfer            (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
-
 // Submit an transfer using fifo, When complete dcd_event_xfer_complete() is invoked to notify the stack
 // This API is optional, may be useful for register-based for transferring data.
 bool dcd_edpt_xfer_fifo       (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) TU_ATTR_WEAK;
 
+#else
+ #if ADD_WEAK_FUNC_DCD_EDPT0_STATUS_COMPLETE
+  #define DCD_EDPT0_STATUS_COMPLETE  dcd_edpt0_status_complete
+ #endif
+ #ifndef DCD_EDPT0_STATUS_COMPLETE
+  #define DCD_EDPT0_STATUS_COMPLETE    NULL
+ #else
+  extern void DCD_EDPT0_STATUS_COMPLETE(uint8_t rhport, tusb_control_request_t const * request);
+ #endif
+
+ #if ADD_WEAK_FUNC_DCD_EDPT_CLOSE
+  #define DCD_EDPT_CLOSE  dcd_edpt_close
+ #endif
+ #ifndef DCD_EDPT_CLOSE
+  #define DCD_EDPT_CLOSE    NULL
+ #else
+  extern void DCD_EDPT_CLOSE(uint8_t rhport, uint8_t ep_addr);
+ #endif
+
+ #if ADD_WEAK_FUNC_DCD_EDPT_XFER_FIFO
+  #define DCD_EDPT_XFER_FIFO  dcd_edpt_xfer_fifo
+ #endif
+ #ifndef DCD_EDPT_XFER_FIFO
+  #define DCD_EDPT_XFER_FIFO    NULL
+ #else
+  extern void DCD_EDPT_XFER_FIFO(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes);
+ #endif
+#endif
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open            (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer            (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
+
 // Stall endpoint
 void dcd_edpt_stall           (uint8_t rhport, uint8_t ep_addr);
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 8454a2951..fa86c28c7 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -33,6 +33,19 @@
 #include "device/usbd_pvt.h"
 #include "device/dcd.h"
 
+#if defined(TU_HAS_NO_ATTR_WEAK)
+static uint8_t const* (*const MAKE_WEAK_FUNC(tud_descriptor_bos_cb))(void) = TUD_DESCRIPTOR_BOS_CB;
+static uint8_t const* (*const MAKE_WEAK_FUNC(tud_descriptor_device_qualifier_cb))(void) = TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB;
+static void (*const MAKE_WEAK_FUNC(tud_mount_cb))(void) = TUD_MOUNT_CB;
+static void (*const MAKE_WEAK_FUNC(tud_umount_cb))(void) = TUD_UMOUNT_CB;
+static void (*const MAKE_WEAK_FUNC(tud_suspend_cb))(_Bool) = TUD_SUSPEND_CB;
+static void (*const MAKE_WEAK_FUNC(tud_resume_cb))(void) = TUD_RESUME_CB;
+static _Bool (*const MAKE_WEAK_FUNC(tud_vendor_control_xfer_cb))(uint8_t, uint8_t, tusb_control_request_t const *) = TUD_RESUME_CB;
+static usbd_class_driver_t const* (*const MAKE_WEAK_FUNC(usbd_app_driver_get_cb))(uint8_t*) = USBD_APP_DRIVER_GET_CB;
+static bool (*const MAKE_WEAK_FUNC(dcd_edpt_xfer_fifo))(uint8_t, uint8_t, tu_fifo_t *, uint16_t) = DCD_EDPT_XFER_FIFO;
+static void (*const MAKE_WEAK_FUNC(dcd_edpt_close))(uint8_t, uint8_t) = DCD_EDPT_CLOSE;
+#endif
+
 #ifndef CFG_TUD_TASK_QUEUE_SZ
 #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
@@ -50,6 +63,8 @@ enum { DRVID_INVALID = 0xFFu };
 
 typedef struct
 {
+  TU_PACK_STRUCT_BEGIN
+  TU_BIT_FIELD_ORDER_BEGIN
   struct TU_ATTR_PACKED
   {
     volatile uint8_t connected    : 1;
@@ -60,6 +75,8 @@ typedef struct
     uint8_t remote_wakeup_support : 1; // configuration descriptor's attribute
     uint8_t self_powered          : 1; // configuration descriptor's attribute
   };
+  TU_BIT_FIELD_ORDER_END
+  TU_PACK_STRUCT_END
 
   volatile uint8_t cfg_num; // current active configuration (0x00 is not configured)
   uint8_t speed;
@@ -67,6 +84,8 @@ typedef struct
   uint8_t itf2drv[16];     // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUD_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid )
 
+  TU_PACK_STRUCT_BEGIN
+  TU_BIT_FIELD_ORDER_BEGIN
   struct TU_ATTR_PACKED
   {
     volatile bool busy    : 1;
@@ -75,6 +94,8 @@ typedef struct
 
     // TODO merge ep2drv here, 4-bit should be sufficient
   }ep_status[CFG_TUD_EP_MAX][2];
+  TU_BIT_FIELD_ORDER_END
+  TU_PACK_STRUCT_END
 
 }usbd_device_t;
 
@@ -236,7 +257,7 @@ static uint8_t _app_driver_count = 0;
 static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 {
   // Application drivers
-  if ( usbd_app_driver_get_cb )
+  if ( MAKE_WEAK_FUNC(usbd_app_driver_get_cb) )
   {
     if ( drvid < _app_driver_count ) return &_app_driver[drvid];
     drvid -= _app_driver_count;
@@ -408,9 +429,9 @@ bool tud_init (uint8_t rhport)
   TU_ASSERT(_usbd_q);
 
   // Get application driver if available
-  if ( usbd_app_driver_get_cb )
+  if ( MAKE_WEAK_FUNC(usbd_app_driver_get_cb) )
   {
-    _app_driver = usbd_app_driver_get_cb(&_app_driver_count);
+    _app_driver = MAKE_WEAK_FUNC(usbd_app_driver_get_cb)(&_app_driver_count);
   }
 
   // Init class drivers
@@ -501,7 +522,7 @@ void tud_task (void)
         usbd_reset(event.rhport);
 
         // invoke callback
-        if (tud_umount_cb) tud_umount_cb();
+        if (MAKE_WEAK_FUNC(tud_umount_cb)) MAKE_WEAK_FUNC(tud_umount_cb)();
       break;
 
       case DCD_EVENT_SETUP_RECEIVED:
@@ -557,12 +578,12 @@ void tud_task (void)
 
       case DCD_EVENT_SUSPEND:
         TU_LOG2("\r\n");
-        if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
+        if (MAKE_WEAK_FUNC(tud_suspend_cb)) MAKE_WEAK_FUNC(tud_suspend_cb)(_usbd_dev.remote_wakeup_en);
       break;
 
       case DCD_EVENT_RESUME:
         TU_LOG2("\r\n");
-        if (tud_resume_cb) tud_resume_cb();
+        if (MAKE_WEAK_FUNC(tud_resume_cb)) MAKE_WEAK_FUNC(tud_resume_cb)();
       break;
 
       case DCD_EVENT_SOF:
@@ -609,10 +630,10 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
   // Vendor request
   if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR )
   {
-    TU_VERIFY(tud_vendor_control_xfer_cb);
+    TU_VERIFY(MAKE_WEAK_FUNC(tud_vendor_control_xfer_cb));
 
-    usbd_control_set_complete_callback(tud_vendor_control_xfer_cb);
-    return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request);
+    usbd_control_set_complete_callback(MAKE_WEAK_FUNC(tud_vendor_control_xfer_cb));
+    return MAKE_WEAK_FUNC(tud_vendor_control_xfer_cb)(rhport, CONTROL_STAGE_SETUP, p_request);
   }
 
 #if CFG_TUSB_DEBUG >= 2
@@ -831,7 +852,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
 
   // Parse interface descriptor
   uint8_t const * p_desc   = ((uint8_t const*) desc_cfg) + sizeof(tusb_desc_configuration_t);
-  uint8_t const * desc_end = ((uint8_t const*) desc_cfg) + desc_cfg->wTotalLength;
+  uint8_t const * desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
 
   while( p_desc < desc_end )
   {
@@ -892,7 +913,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
   }
 
   // invoke callback
-  if (tud_mount_cb) tud_mount_cb();
+  if (MAKE_WEAK_FUNC(tud_mount_cb)) MAKE_WEAK_FUNC(tud_mount_cb)();
 
   return true;
 }
@@ -949,15 +970,15 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       TU_LOG2(" BOS\r\n");
 
       // requested by host if USB > 2.0 ( i.e 2.1 or 3.x )
-      if (!tud_descriptor_bos_cb) return false;
+      if (!MAKE_WEAK_FUNC(tud_descriptor_bos_cb)) return false;
 
-      tusb_desc_bos_t const* desc_bos = (tusb_desc_bos_t const*) tud_descriptor_bos_cb();
+      tusb_desc_bos_t const* desc_bos = (tusb_desc_bos_t const*)MAKE_WEAK_FUNC(tud_descriptor_bos_cb)();
 
       uint16_t total_len;
       // Use offsetof to avoid pointer to the odd/misaligned address
       memcpy(&total_len, (uint8_t*) desc_bos + offsetof(tusb_desc_bos_t, wTotalLength), 2);
 
-      return tud_control_xfer(rhport, p_request, (void*) desc_bos, total_len);
+      return tud_control_xfer(rhport, p_request, (void*) desc_bos, tu_le16toh(total_len));
     }
     break;
 
@@ -972,7 +993,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       // Use offsetof to avoid pointer to the odd/misaligned address
       memcpy(&total_len, (uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength), 2);
 
-      return tud_control_xfer(rhport, p_request, (void*) desc_config, total_len);
+      return tud_control_xfer(rhport, p_request, (void*) desc_config, tu_le16toh(total_len));
     }
     break;
 
@@ -995,9 +1016,9 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       // Host sends this request to ask why our device with USB BCD from 2.0
       // but is running at Full/Low Speed. If not highspeed capable stall this request,
       // otherwise return the descriptor that could work in highspeed mode
-      if ( tud_descriptor_device_qualifier_cb )
+      if (MAKE_WEAK_FUNC(tud_descriptor_device_qualifier_cb))
       {
-        uint8_t const* desc_qualifier = tud_descriptor_device_qualifier_cb();
+        uint8_t const* desc_qualifier = MAKE_WEAK_FUNC(tud_descriptor_device_qualifier_cb)();
         TU_ASSERT(desc_qualifier);
 
         // first byte of descriptor is its size
@@ -1165,18 +1186,18 @@ bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
       if (_usbd_dev.speed == TUSB_SPEED_HIGH)
       {
         // Bulk highspeed must be EXACTLY 512
-        TU_ASSERT(desc_ep->wMaxPacketSize.size == 512);
+        TU_ASSERT(tu_le16toh(desc_ep->wMaxPacketSize.size) == 512);
       }else
       {
         // TODO Bulk fullspeed can only be 8, 16, 32, 64
-        TU_ASSERT(desc_ep->wMaxPacketSize.size <= 64);
+        TU_ASSERT(tu_le16toh(desc_ep->wMaxPacketSize.size) <= 64);
       }
     break;
 
     case TUSB_XFER_INTERRUPT:
     {
       uint16_t const max_epsize = (_usbd_dev.speed == TUSB_SPEED_HIGH ? 1024 : 64);
-      TU_ASSERT(desc_ep->wMaxPacketSize.size <= max_epsize);
+      TU_ASSERT(tu_le16toh(desc_ep->wMaxPacketSize.size) <= max_epsize);
     }
     break;
 
@@ -1285,7 +1306,7 @@ bool usbd_edpt_iso_xfer(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
   // and usbd task can preempt and clear the busy
   _usbd_dev.ep_status[epnum][dir].busy = true;
 
-  if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes))
+  if (MAKE_WEAK_FUNC(dcd_edpt_xfer_fifo)(rhport, ep_addr, ff, total_bytes))
   {
     TU_LOG2("OK\r\n");
     return true;
@@ -1348,10 +1369,10 @@ bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
  */
 void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
-  TU_ASSERT(dcd_edpt_close, /**/);
+  TU_ASSERT(MAKE_WEAK_FUNC(dcd_edpt_close), /**/);
   TU_LOG2("  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
 
-  dcd_edpt_close(rhport, ep_addr);
+  MAKE_WEAK_FUNC(dcd_edpt_close(rhport, ep_addr));
 
   return;
 }
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 53519c4de..04597a215 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -103,10 +103,6 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request);
 // Application return pointer to descriptor
 uint8_t const * tud_descriptor_device_cb(void);
 
-// Invoked when received GET BOS DESCRIPTOR request
-// Application return pointer to descriptor
-TU_ATTR_WEAK uint8_t const * tud_descriptor_bos_cb(void);
-
 // Invoked when received GET CONFIGURATION DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
 uint8_t const * tud_descriptor_configuration_cb(uint8_t index);
@@ -115,6 +111,11 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index);
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
 uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid);
 
+#if !defined(TU_HAS_NO_ATTR_WEAK)
+// Invoked when received GET BOS DESCRIPTOR request
+// Application return pointer to descriptor
+TU_ATTR_WEAK uint8_t const * tud_descriptor_bos_cb(void);
+
 // Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
 TU_ATTR_WEAK uint8_t const* tud_descriptor_device_qualifier_cb(void);
@@ -135,6 +136,71 @@ TU_ATTR_WEAK void tud_resume_cb(void);
 // Invoked when received control request with VENDOR TYPE
 TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 
+#else
+ #if ADD_WEAK_FUNC_TUD_DESCRIPTOR_BOS_CB
+  #define TUD_DESCRIPTOR_BOS_CB  tud_descriptor_bos_cb
+ #endif
+ #ifndef TUD_DESCRIPTOR_BOS_CB
+  #define TUD_DESCRIPTOR_BOS_CB    NULL
+ #else
+  extern uint8_t const* TUD_DESCRIPTOR_BOS_CB(void);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB
+  #define TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB  tud_descriptor_device_qualifier_cb
+ #endif
+ #ifndef TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB
+  #define TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB    NULL
+ #else
+  extern uint8_t const* TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB(void);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_MOUNT_CB
+  #define TUD_MOUNT_CB  tud_mount_cb
+ #endif
+ #ifndef TUD_MOUNT_CB
+  #define TUD_MOUNT_CB    NULL
+ #else
+  extern void TUD_MOUNT_CB(void);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_UMOUNT_CB
+  #define TUD_UMOUNT_CB  tud_umount_cb
+ #endif
+ #ifndef TUD_UMOUNT_CB
+  #define TUD_UMOUNT_CB    NULL
+ #else
+  extern void TUD_UMOUNT_CB(void);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_SUSPEND_CB
+  #define TUD_SUSPEND_CB  tud_suspend_cb
+ #endif
+ #ifndef TUD_SUSPEND_CB
+  #define TUD_SUSPEND_CB    NULL
+ #else
+  extern void TUD_SUSPEND_CB(bool remote_wakeup_en);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_RESUME_CB
+  #define TUD_RESUME_CB  tud_resume_cb
+ #endif
+ #ifndef TUD_RESUME_CB
+  #define TUD_RESUME_CB    NULL
+ #else
+  extern void TUD_RESUME_CB(void);
+ #endif
+
+ #if ADD_WEAK_FUNC_TUD_VENDOR_CONTROL_XFER_CB
+  #define TUD_VENDOR_CONTROL_XFER_CB  tud_vendor_control_xfer_cb
+ #endif
+ #ifndef TUD_VENDOR_CONTROL_XFER_CB
+  #define TUD_VENDOR_CONTROL_XFER_CB    NULL
+ #else
+  extern bool TUD_VENDOR_CONTROL_XFER_CB(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+ #endif
+#endif
+
 //--------------------------------------------------------------------+
 // Binary Device Object Store (BOS) Descriptor Templates
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 724c652e6..76f999f86 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -36,6 +36,10 @@
 extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
 #endif
 
+#if defined(TU_HAS_NO_ATTR_WEAK)
+static void (*const MAKE_WEAK_FUNC(dcd_edpt0_status_complete))(uint8_t, tusb_control_request_t const *) = DCD_EDPT0_STATUS_COMPLETE;
+#endif
+
 enum
 {
   EDPT_CTRL_OUT = 0x00,
@@ -55,8 +59,17 @@ typedef struct
 
 static usbd_control_xfer_t _ctrl_xfer;
 
+#if defined(TU_HAS_NO_ATTR_ALIGNED)
+// Helper union to overcome the lack of the alignment attribute/pragma
+static union {
+  uint16_t : (sizeof(uint16_t) * 8);  // Alignment of at least the size of the used type
+  uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
+} Align_usbd_ctrl_buf_;
+static uint8_t *_usbd_ctrl_buf = (uint8_t*)&Align_usbd_ctrl_buf_;
+#else
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
 static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
+#endif
 
 //--------------------------------------------------------------------+
 // Application API
@@ -171,7 +184,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
     TU_ASSERT(0 == xferred_bytes);
 
     // invoke optional dcd hook if available
-    if (dcd_edpt0_status_complete) dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
+    if (MAKE_WEAK_FUNC(dcd_edpt0_status_complete)) MAKE_WEAK_FUNC(dcd_edpt0_status_complete)(rhport, &_ctrl_xfer.request);
 
     if (_ctrl_xfer.complete_cb)
     {
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 44310f022..1d60e5ae2 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -51,10 +51,21 @@ typedef struct
   void     (* sof              ) (uint8_t rhport); /* optional */
 } usbd_class_driver_t;
 
+#if !defined(TU_HAS_NO_ATTR_WEAK)
 // Invoked when initializing device stack to get additional class drivers.
 // Can optionally implemented by application to extend/overwrite class driver support.
 // Note: The drivers array must be accessible at all time when stack is active
 usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
+#else
+ #if ADD_WEAK_FUNC_USBD_APP_DRIVER_GET_CB
+  #define USBD_APP_DRIVER_GET_CB  usbd_app_driver_get_cb
+ #endif
+ #ifndef USBD_APP_DRIVER_GET_CB
+  #define USBD_APP_DRIVER_GET_CB    NULL
+ #else
+  extern usbd_class_driver_t const* USBD_APP_DRIVER_GET_CB(uint8_t* driver_count);
+ #endif
+#endif
 
 
 typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 66070c273..ec33b317d 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -51,6 +51,7 @@ static inline void osal_task_delay(uint32_t msec)
 typedef StaticSemaphore_t osal_semaphore_def_t;
 typedef SemaphoreHandle_t osal_semaphore_t;
 
+#if (configSUPPORT_STATIC_ALLOCATION == 1)  //FIXME Only static API supported
 static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
 {
   return xSemaphoreCreateBinaryStatic(semdef);
@@ -76,6 +77,7 @@ static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
     return res != 0;
   }
 }
+#endif
 
 static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
 {
@@ -96,7 +98,12 @@ typedef SemaphoreHandle_t osal_mutex_t;
 
 static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
+#if (configSUPPORT_STATIC_ALLOCATION == 0) //FIXME Only static API supported
+  (void)mdef;
+  return xSemaphoreCreateMutex();
+#else
   return xSemaphoreCreateMutexStatic(mdef);
+#endif
 }
 
 static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
@@ -131,7 +138,11 @@ typedef QueueHandle_t osal_queue_t;
 
 static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
+#if defined(__Tx36V5_Maincard__)
+  return xQueueCreate(qdef->depth, qdef->item_sz);
+#else
   return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
+#endif
 }
 
 static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
@@ -139,6 +150,19 @@ static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
   return xQueueReceive(qhdl, data, portMAX_DELAY);
 }
 
+#if defined(__Tx36V5_Maincard__)
+extern BaseType_t UsbTaskWoken;
+static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
+{
+  if (!in_isr) {
+    return(xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER));
+
+  } else {
+    BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &UsbTaskWoken);
+    return(res != 0);
+  }
+}
+#else
 static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
 {
   if ( !in_isr )
@@ -159,6 +183,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
     return res != 0;
   }
 }
+#endif
 
 static inline bool osal_queue_empty(osal_queue_t qhdl)
 {
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 06ea1a3f9..54410ff0b 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X )
+#if TUSB_OPT_DEVICE_ENABLED && (( CFG_TUSB_MCU == OPT_MCU_RX63X ) || ( CFG_TUSB_MCU == OPT_MCU_RX72N ))
 
 #include "device/dcd.h"
 #include "iodefine.h"
@@ -38,6 +38,7 @@
 #define SYSTEM_PRCR_PRKEY    (0xA5u<<8)
 
 #define USB_FIFOSEL_TX       ((uint16_t)(1u<<5))
+#define USB_FIFOSEL_BIGEND   ((uint16_t)(1u<<8))
 #define USB_FIFOSEL_MBW_8    ((uint16_t)(0u<<10))
 #define USB_FIFOSEL_MBW_16   ((uint16_t)(1u<<10))
 #define USB_IS0_CTSQ         ((uint16_t)(7u))
@@ -91,39 +92,47 @@
 
 typedef struct {
   union {
+    TU_BIT_FIELD_ORDER_BEGIN
     struct {
       uint16_t      : 8;
       uint16_t TRCLR: 1;
       uint16_t TRENB: 1;
       uint16_t      : 0;
     };
+    TU_BIT_FIELD_ORDER_END
     uint16_t TRE;
   };
   uint16_t TRN;
 } reg_pipetre_t;
 
 typedef union {
+  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     volatile uint16_t u8: 8;
     volatile uint16_t   : 0;
   };
+  TU_BIT_FIELD_ORDER_END
   volatile uint16_t u16;
 } hw_fifo_t;
 
+TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uintptr_t addr;      /* the start address of a transfer data buffer */
   uint16_t  length;    /* the number of bytes in the buffer */
   uint16_t  remaining; /* the number of bytes remaining in the buffer */
+  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     uint32_t ep  : 8;  /* an assigned endpoint address */
     uint32_t     : 0;
   };
+  TU_BIT_FIELD_ORDER_END
 } pipe_state_t;
+TU_PACK_STRUCT_END
 
 typedef struct
 {
-  pipe_state_t pipe[9];
+  pipe_state_t pipe[10];
   uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
 } dcd_data_t;
 
@@ -135,14 +144,23 @@ CFG_TUSB_MEM_SECTION static dcd_data_t _dcd;
 static uint32_t disable_interrupt(void)
 {
   uint32_t pswi;
+#if defined(__CCRX__)
+  pswi = get_psw() & 0x010000;
+  clrpsw_i();
+#else
   pswi = __builtin_rx_mvfc(0) & 0x010000;
   __builtin_rx_clrpsw('I');
+#endif
   return pswi;
 }
 
 static void enable_interrupt(uint32_t pswi)
 {
+#if defined(__CCRX__)
+  set_psw(get_psw() | pswi);
+#else
   __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
+#endif
 }
 
 static unsigned find_pipe(unsigned xfer)
@@ -226,7 +244,7 @@ static unsigned select_pipe(unsigned num, unsigned attr)
 {
   USB0.PIPESEL.WORD  = num;
   USB0.D0FIFOSEL.WORD = num | attr;
-  while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
+  while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
   return wait_for_pipe_ready();
 }
 
@@ -270,11 +288,11 @@ static int fifo_read(volatile void *fifo, pipe_state_t* pipe, unsigned mps, size
   if (rem < len) len = rem;
   pipe->remaining = rem - len;
 
-  hw_fifo_t *reg = (hw_fifo_t*)fifo;
+  uint8_t *reg = (uint8_t*)fifo;  /* byte access is always at base register address */
   uintptr_t addr = pipe->addr;
   unsigned  loop = len;
   while (loop--) {
-    *(uint8_t *)addr = reg->u8;
+    *(uint8_t *)addr = *reg;
     ++addr;
   }
   pipe->addr = addr;
@@ -292,6 +310,13 @@ static void process_setup_packet(uint8_t rhport)
   setup_packet[1] = USB0.USBVAL;
   setup_packet[2] = USB0.USBINDX;
   setup_packet[3] = USB0.USBLENG;
+#if TU_BYTE_ORDER==TU_BIG_ENDIAN
+ #if defined(__CCRX__)
+  setup_packet[0] = tu_le16toh(setup_packet[0]);
+ #else
+ //FIXME needs to implemented for other tool chains
+ #endif
+#endif
   USB0.INTSTS0.WORD = ~USB_IS0_VALID;
   dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
 }
@@ -317,7 +342,11 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   pipe_state_t *pipe = &_dcd.pipe[0];
   /* configure fifo direction and access unit settings */
   if (ep_addr) { /* IN, 2 bytes */
+#if TU_BYTE_ORDER == TU_BIG_ENDIAN
+    USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | USB_FIFOSEL_BIGEND;
+#else
     USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16;
+#endif
     while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
   } else {       /* OUT, a byte */
     USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8;
@@ -329,7 +358,7 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
     pipe->remaining = total_bytes;
     if (ep_addr) { /* IN */
       TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
-      if (fifo_write(&USB0.CFIFO.WORD, pipe, 64)) {
+      if (fifo_write((void*)&USB0.CFIFO.WORD, pipe, 64)) {
         USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
       }
     }
@@ -350,7 +379,7 @@ static void process_edpt0_bemp(uint8_t rhport)
   const unsigned rem = pipe->remaining;
   if (rem > 64) {
     pipe->remaining = rem - 64;
-    int r = fifo_write(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
+    int r = fifo_write((void*)&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
     if (r) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
     return;
   }
@@ -363,7 +392,7 @@ static void process_edpt0_bemp(uint8_t rhport)
 static void process_edpt0_brdy(uint8_t rhport)
 {
   size_t len = USB0.CFIFOCTR.BIT.DTLN;
-  int cplt = fifo_read(&USB0.CFIFO.WORD, &_dcd.pipe[0], 64, len);
+  int cplt = fifo_read((void*)&USB0.CFIFO.WORD, &_dcd.pipe[0], 64, len);
   if (cplt || (len < 64)) {
     if (2 != cplt) {
       USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
@@ -392,11 +421,16 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   USB0.PIPESEL.WORD  = num;
   const unsigned mps = USB0.PIPEMAXP.WORD;
   if (dir) { /* IN */
+#if TU_BYTE_ORDER == TU_BIG_ENDIAN
+    USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | USB_FIFOSEL_BIGEND;
+#else
     USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16;
-    while (!(USB0.D0FIFOSEL.BIT.CURPIPE != num)) ;
-    int r = fifo_write(&USB0.D0FIFO.WORD, pipe, mps);
+#endif
+    while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
+    int r = fifo_write((void*)&USB0.D0FIFO.WORD, pipe, mps);
     if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
     USB0.D0FIFOSEL.WORD = 0;
+    while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   } else {
     volatile reg_pipetre_t *pt = get_pipetre(num);
     if (pt) {
@@ -416,19 +450,25 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
 {
   pipe_state_t *pipe = &_dcd.pipe[num];
   if (tu_edpt_dir(pipe->ep)) { /* IN */
+#if TU_BYTE_ORDER == TU_BIG_ENDIAN
+    select_pipe(num, USB_FIFOSEL_MBW_16 | USB_FIFOSEL_BIGEND);
+#else
     select_pipe(num, USB_FIFOSEL_MBW_16);
+#endif
     const unsigned mps = USB0.PIPEMAXP.WORD;
     unsigned rem       = pipe->remaining;
     rem               -= TU_MIN(rem, mps);
     pipe->remaining    = rem;
     if (rem) {
       int r = 0;
-      r = fifo_write(&USB0.D0FIFO.WORD, pipe, mps);
+      r = fifo_write((void*)&USB0.D0FIFO.WORD, pipe, mps);
       if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
       USB0.D0FIFOSEL.WORD = 0;
+      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
       return;
     }
     USB0.D0FIFOSEL.WORD = 0;
+    while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
     pipe->addr      = 0;
     pipe->remaining = 0;
     dcd_event_xfer_complete(rhport, pipe->ep, pipe->length,
@@ -437,18 +477,20 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
     const unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_8);
     const unsigned len = ctr & USB_FIFOCTR_DTLN;
     const unsigned mps = USB0.PIPEMAXP.WORD;
-    int cplt = fifo_read(&USB0.D0FIFO.WORD, pipe, mps, len);
+    int cplt = fifo_read((void*)&USB0.D0FIFO.WORD, pipe, mps, len);
     if (cplt || (len < mps)) {
       if (2 != cplt) {
         USB0.D0FIFO.WORD = USB_FIFOCTR_BCLR;
       }
       USB0.D0FIFOSEL.WORD = 0;
+      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
       dcd_event_xfer_complete(rhport, pipe->ep,
                               pipe->length - pipe->remaining,
                               XFER_RESULT_SUCCESS, true);
       return;
     }
     USB0.D0FIFOSEL.WORD = 0;
+    while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   }
 }
 
@@ -458,7 +500,9 @@ static void process_bus_reset(uint8_t rhport)
   USB0.BRDYENB.WORD   = 1;
   USB0.CFIFOCTR.WORD  = USB_FIFOCTR_BCLR;
   USB0.D0FIFOSEL.WORD = 0;
+  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   USB0.D1FIFOSEL.WORD = 0;
+  while (USB0.D1FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1CTR.WORD));
   volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1TRE.WORD));
   for (int i = 1; i <= 5; ++i) {
@@ -485,13 +529,22 @@ static void process_set_address(uint8_t rhport)
 {
   const uint32_t addr = USB0.USBADDR.BIT.USBADDR;
   if (!addr) return;
+#if defined(__CCRX__)
+  tusb_control_request_t setup_packet;
+  setup_packet.bmRequestType = 0;
+  setup_packet.bRequest = 5;
+  setup_packet.wValue = addr;
+  setup_packet.wIndex = 0;
+  setup_packet.wLength = 0;
+#else
   const tusb_control_request_t setup_packet = {
-    .bmRequestType = 0,
-    .bRequest      = 5,
-    .wValue        = addr,
-    .wIndex        = 0,
-    .wLength       = 0,
-  };
+      .bmRequestType = 0,
+      .bRequest      = 5,
+      .wValue        = addr,
+      .wIndex        = 0,
+      .wLength       = 0,
+    };
+#endif
   dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true);
 }
 
@@ -513,7 +566,13 @@ void dcd_init(uint8_t rhport)
   USB0.SYSCFG.BIT.DCFM = 0;
   USB0.SYSCFG.BIT.USBE = 1;
 
+  USB0.PHYSLEW.LONG = 0x5;
+  USB.DPUSR0R.BIT.FIXPHY0 = 0u;    /* USB0 Transceiver Output fixed */
+#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
+  IR(PERIB, INTB185) = 0;
+#else
   IR(USB0, USBI0)   = 0;
+#endif
 
   /* Setup default control pipe */
   USB0.DCPMAXP.BIT.MXPS  = 64;
@@ -529,13 +588,21 @@ void dcd_init(uint8_t rhport)
 void dcd_int_enable(uint8_t rhport)
 {
   (void)rhport;
+#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
+  IEN(PERIB, INTB185) = 1;
+#else
   IEN(USB0, USBI0) = 1;
+#endif
 }
 
 void dcd_int_disable(uint8_t rhport)
 {
   (void)rhport;
+#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
+  IEN(PERIB, INTB185) = 0;
+#else
   IEN(USB0, USBI0) = 0;
+#endif
 }
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
@@ -574,7 +641,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   const unsigned dir     = tu_edpt_dir(ep_addr);
   const unsigned xfer    = ep_desc->bmAttributes.xfer;
 
-  const unsigned mps = ep_desc->wMaxPacketSize.size;
+  const unsigned mps = tu_le16toh(ep_desc->wMaxPacketSize.size);
   if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
     /* USBa supports up to 256 bytes */
     return false;
@@ -680,8 +747,8 @@ void dcd_int_handler(uint8_t rhport)
   (void)rhport;
 
   unsigned is0 = USB0.INTSTS0.WORD;
-  /* clear bits except VALID */
-  USB0.INTSTS0.WORD = USB_IS0_VALID;
+  /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
+  USB0.INTSTS0.WORD = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID;
   if (is0 & USB_IS0_VBINT) {
     if (USB0.INTSTS0.BIT.VBSTS) {
       dcd_connect(rhport);
@@ -720,13 +787,24 @@ void dcd_int_handler(uint8_t rhport)
   if (is0 & USB_IS0_BRDY) {
     const unsigned m = USB0.BRDYENB.WORD;
     unsigned s       = USB0.BRDYSTS.WORD & m;
-    USB0.BRDYSTS.WORD = 0;
+    /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
+    USB0.BRDYSTS.WORD = ~s;
     if (s & 1) {
       process_edpt0_brdy(rhport);
       s &= ~1;
     }
     while (s) {
+#if defined(__CCRX__)
+      static const int Mod37BitPosition[] = {
+        -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4,
+        7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
+        20, 8, 19, 18
+      };
+
+      const unsigned num = Mod37BitPosition[(-s & s) % 37];
+#else
       const unsigned num = __builtin_ctz(s);
+#endif
       process_pipe_brdy(rhport, num);
       s &= ~TU_BIT(num);
     }
diff --git a/src/tusb_option.h b/src/tusb_option.h
index b317f7630..d04542e61 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -112,6 +112,7 @@
 
 // Renesas RX
 #define OPT_MCU_RX63X            1400 ///< Renesas RX63N/631
+#define OPT_MCU_RX72N            1401 ///< Renesas RX72N
 
 /** @} */
 

From e26cf6b26ca0d7c54f71332896d4bed9c418844a Mon Sep 17 00:00:00 2001
From: Wini-Buh <info@winformatik.ch>
Date: Wed, 2 Jun 2021 21:33:32 +0200
Subject: [PATCH 0008/2085] Missing RX device dependency corrected

---
 src/portable/renesas/usba/dcd_usba.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 54410ff0b..0e7881383 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -566,9 +566,9 @@ void dcd_init(uint8_t rhport)
   USB0.SYSCFG.BIT.DCFM = 0;
   USB0.SYSCFG.BIT.USBE = 1;
 
-  USB0.PHYSLEW.LONG = 0x5;
   USB.DPUSR0R.BIT.FIXPHY0 = 0u;    /* USB0 Transceiver Output fixed */
 #if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
+  USB0.PHYSLEW.LONG = 0x5;
   IR(PERIB, INTB185) = 0;
 #else
   IR(USB0, USBI0)   = 0;

From c81bc38d422f419cd8949019fd5f2eadc9ec2333 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Thu, 3 Jun 2021 10:10:44 -0500
Subject: [PATCH 0009/2085] Add __unused to variables that are only used if
 TU_LOG does something

---
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 32d20051f..33f3ecd41 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -134,11 +134,11 @@ typedef union TU_ATTR_PACKED
 
 TU_VERIFY_STATIC(sizeof(rp2040_buffer_control_t) == 2, "size is not correct");
 
-static inline void print_bufctrl16(uint32_t u16)
+static inline void print_bufctrl16(uint32_t __unused u16)
 {
-  rp2040_buffer_control_t bufctrl;
-
-  bufctrl.u16 = u16;
+  rp2040_buffer_control_t __unused bufctrl = {
+      .u16 = u16
+  };
 
   TU_LOG(2, "len = %u, available = %u, stall = %u, reset = %u, toggle = %u, last = %u, full = %u\r\n",
          bufctrl.xfer_len, bufctrl.available, bufctrl.stall, bufctrl.reset_bufsel, bufctrl.data_toggle, bufctrl.last_buf, bufctrl.full);

From 26b9fc38ed5a525428d81e4ebfc05bfc366083e8 Mon Sep 17 00:00:00 2001
From: zhangslice <54609269+zhangslice@users.noreply.github.com>
Date: Mon, 7 Jun 2021 18:32:46 +0800
Subject: [PATCH 0010/2085] Add MM32 SDK and USB driver (#869)

* Add MM32 SDK and USB driver
* add mindmotion mm32sdk as submodule
remove the local copy of mm32
* mit  license
Signed-off-by: zhangslice <1304224508@qq.com>
Co-authored-by: hathach <thach@tinyusb.org>
---
 .gitmodules                           |   3 +
 hw/mcu/mindmotion/mm32sdk             |   1 +
 src/portable/mm32/dcd_mm32f327x_otg.c | 471 ++++++++++++++++++++++++++
 3 files changed, 475 insertions(+)
 create mode 160000 hw/mcu/mindmotion/mm32sdk
 create mode 100644 src/portable/mm32/dcd_mm32f327x_otg.c

diff --git a/.gitmodules b/.gitmodules
index 79ef8e0ad..c0e6f8f91 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -121,3 +121,6 @@
 [submodule "hw/mcu/nxp/nxp_sdk"]
 	path = hw/mcu/nxp/nxp_sdk
 	url = https://github.com/hathach/nxp_sdk.git
+[submodule "hw/mcu/mindmotion/mm32sdk"]
+	path = hw/mcu/mindmotion/mm32sdk
+	url = https://github.com/zhangslice/mm32sdk.git
diff --git a/hw/mcu/mindmotion/mm32sdk b/hw/mcu/mindmotion/mm32sdk
new file mode 160000
index 000000000..b6b99de3a
--- /dev/null
+++ b/hw/mcu/mindmotion/mm32sdk
@@ -0,0 +1 @@
+Subproject commit b6b99de3ab26218784ec158488bdd91377288f94
diff --git a/src/portable/mm32/dcd_mm32f327x_otg.c b/src/portable/mm32/dcd_mm32f327x_otg.c
new file mode 100644
index 000000000..e7518830e
--- /dev/null
+++ b/src/portable/mm32/dcd_mm32f327x_otg.c
@@ -0,0 +1,471 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+#include "reg_usb_otg_fs.h"
+#include "mm32_device.h"
+#include "hal_conf.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MM32F327X )
+
+#include "device/dcd.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+enum {
+  TOK_PID_OUT   = 0x1u,
+  TOK_PID_IN    = 0x9u,
+  TOK_PID_SETUP = 0xDu,
+};
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t head;
+    struct {
+      union {
+        struct {
+          uint16_t          :  2;
+          uint16_t tok_pid  :  4;
+          uint16_t data     :  1;
+          uint16_t own      :  1;
+          uint16_t          :  8;
+        };
+        struct {
+          uint16_t          :  2;
+          uint16_t bdt_stall:  1;
+          uint16_t dts      :  1;
+          uint16_t ninc     :  1;
+          uint16_t keep     :  1;
+          uint16_t          : 10;
+        };
+      };
+      uint16_t bc          : 10;
+      uint16_t             :  6;
+    };
+  };
+  uint8_t *addr;
+}buffer_descriptor_t;
+
+TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t state;
+    struct {
+      uint32_t max_packet_size :11;
+      uint32_t                 : 5;
+      uint32_t odd             : 1;
+      uint32_t                 :15;
+    };
+  };
+  uint16_t length;
+  uint16_t remaining;
+}endpoint_state_t;
+
+TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
+
+typedef struct
+{
+  union {
+    /* [#EP][OUT,IN][EVEN,ODD] */
+    buffer_descriptor_t bdt[16][2][2];
+    uint16_t            bda[512];
+  };
+  TU_ATTR_ALIGNED(4) union {
+    endpoint_state_t endpoint[16][2];
+    endpoint_state_t endpoint_unified[16 * 2];
+  };
+  uint8_t setup_packet[8];
+  uint8_t addr;
+}dcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+// BDT(Buffer Descriptor Table) must be 256-byte aligned
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
+
+TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
+
+static void prepare_next_setup_packet(uint8_t rhport)
+{
+  const unsigned out_odd = _dcd.endpoint[0][0].odd;
+  const unsigned in_odd  = _dcd.endpoint[0][1].odd;
+  if (_dcd.bdt[0][0][out_odd].own) {
+    TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd);
+    return;
+  }
+  _dcd.bdt[0][0][out_odd].data     = 0;
+  _dcd.bdt[0][0][out_odd ^ 1].data = 1;
+  _dcd.bdt[0][1][in_odd].data      = 1;
+  _dcd.bdt[0][1][in_odd ^ 1].data  = 0;
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
+                _dcd.setup_packet, sizeof(_dcd.setup_packet));
+}
+
+static void process_stall(uint8_t rhport)
+{
+  if (USB_OTG_FS->EP_CTL[0] & USB_ENDPT_EPSTALL_MASK) {
+    /* clear stall condition of the control pipe */
+    prepare_next_setup_packet(rhport);
+    USB_OTG_FS->EP_CTL[0] &= ~USB_ENDPT_EPSTALL_MASK;
+  }
+}
+
+static void process_tokdne(uint8_t rhport)
+{
+  const unsigned s = USB_OTG_FS->STAT;
+  USB_OTG_FS->INT_STAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
+  buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
+  endpoint_state_t    *ep = &_dcd.endpoint_unified[s >> 3];
+  unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0;
+
+  /* fetch pid before discarded by the next steps */
+  const unsigned pid = bd->tok_pid;
+  /* reset values for a next transfer */
+  bd->bdt_stall = 0;
+  bd->dts       = 1;
+  bd->ninc      = 0;
+  bd->keep      = 0;
+  /* update the odd variable to prepare for the next transfer */
+  ep->odd       = odd ^ 1;
+  if (pid == TOK_PID_SETUP) {
+    dcd_event_setup_received(rhport, bd->addr, true);
+    USB_OTG_FS->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+    return;
+  }
+  if (s >> 4) {
+    TU_LOG1("TKDNE %x\r\n", s);
+  }
+
+  const unsigned bc = bd->bc;
+  const unsigned remaining = ep->remaining - bc;
+  if (remaining && bc == ep->max_packet_size) {
+    /* continue the transferring consecutive data */
+    ep->remaining = remaining;
+    const int next_remaining = remaining - ep->max_packet_size;
+    if (next_remaining > 0) {
+      /* prepare to the after next transfer */
+      bd->addr += ep->max_packet_size * 2;
+      bd->bc    = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
+      __DSB();
+      bd->own   = 1; /* the own bit must set after addr */
+    }
+    return;
+  }
+  const unsigned length = ep->length;
+  dcd_event_xfer_complete(rhport,
+                          ((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT),
+                          length - remaining, XFER_RESULT_SUCCESS, true);
+  if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) {
+    /* After completion a ZLP of control transfer,
+     * it prepares for the next steup transfer. */
+    if (_dcd.addr) {
+      /* When the transfer was the SetAddress,
+       * the device address should be updated here. */
+      USB_OTG_FS->ADDR = _dcd.addr;
+      _dcd.addr  = 0;
+    }
+    prepare_next_setup_packet(rhport);
+  }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+  USB_OTG_FS->CTL     |= USB_CTL_ODDRST_MASK;
+  USB_OTG_FS->ADDR     = 0;
+  USB_OTG_FS->INT_ENB    = (USB_OTG_FS->INT_ENB & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
+
+  USB_OTG_FS->EP_CTL[0] = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
+  for (unsigned i = 1; i < 16; ++i) {
+    USB_OTG_FS->EP_CTL[i] = 0;
+  }
+  buffer_descriptor_t *bd = _dcd.bdt[0][0];
+  for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
+    bd->head = 0;
+  }
+  const endpoint_state_t ep0 = {
+    .max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
+    .odd             = 0,
+    .length          = 0,
+    .remaining       = 0,
+  };
+  _dcd.endpoint[0][0] = ep0;
+  _dcd.endpoint[0][1] = ep0;
+  tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
+  _dcd.addr = 0;
+  prepare_next_setup_packet(rhport);
+  USB_OTG_FS->CTL &= ~USB_CTL_ODDRST_MASK;
+  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+}
+
+static void process_bus_inactive(uint8_t rhport)
+{
+  (void) rhport;
+  const unsigned inten = USB_OTG_FS->INT_ENB;
+  USB_OTG_FS->INT_ENB    = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
+  dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+}
+
+static void process_bus_active(uint8_t rhport)
+{
+  (void) rhport;
+  const unsigned inten = USB_OTG_FS->INT_ENB;
+  USB_OTG_FS->INT_ENB    = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
+  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+void dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  tu_memclr(&_dcd, sizeof(_dcd));
+  USB_OTG_FS->BDT_PAGE_01 = (uint8_t)((uintptr_t)_dcd.bdt >>  8);
+  USB_OTG_FS->BDT_PAGE_02 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
+  USB_OTG_FS->BDT_PAGE_03 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
+
+  dcd_connect(rhport);
+  NVIC_ClearPendingIRQ(USB_FS_IRQn);
+}
+#define USB_DEVICE_INTERRUPT_PRIORITY (3U)
+void dcd_int_enable(uint8_t rhport)
+{
+  uint8_t irqNumber;
+  irqNumber = USB_FS_IRQn;
+  (void) rhport;
+  USB_OTG_FS->INT_ENB = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK |
+    USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
+  NVIC_SetPriority((IRQn_Type)irqNumber, USB_DEVICE_INTERRUPT_PRIORITY);
+  NVIC_EnableIRQ(USB_FS_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB_FS_IRQn);
+  USB_OTG_FS->INT_ENB = 0;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+  _dcd.addr = dev_addr & 0x7F;
+  /* Response with status first before changing device address */
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+extern u32 SystemCoreClock ;
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+  unsigned cnt = SystemCoreClock / 100;
+  USB_OTG_FS->CTL |= USB_CTL_RESUME_MASK;
+  while (cnt--) __NOP();
+  USB_OTG_FS->CTL &= ~USB_CTL_RESUME_MASK;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  USB_OTG_FS->CTL     |= USB_CTL_USBENSOFEN_MASK;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  (void) rhport;
+  USB_OTG_FS->CTL      = 0;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+
+  const unsigned ep_addr  = ep_desc->bEndpointAddress;
+  const unsigned epn      = ep_addr & 0xFu;
+  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned xfer     = ep_desc->bmAttributes.xfer;
+  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
+  const unsigned odd      = ep->odd;
+  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
+
+  /* No support for control transfer */
+  TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
+
+  ep->max_packet_size = ep_desc->wMaxPacketSize.size;
+  unsigned val = USB_ENDPT_EPCTLDIS_MASK;
+  val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
+  val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+  USB_OTG_FS->EP_CTL[epn] |= val;
+
+  if (xfer != TUSB_XFER_ISOCHRONOUS) {
+    bd[odd].dts      = 1;
+    bd[odd].data     = 0;
+    bd[odd ^ 1].dts  = 1;
+    bd[odd ^ 1].data = 1;
+  }
+
+  return true;
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  const unsigned epn      = ep_addr & 0xFu;
+  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
+  const unsigned msk      = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+  USB_OTG_FS->EP_CTL[epn] &= ~msk;
+  ep->max_packet_size = 0;
+  ep->length          = 0;
+  ep->remaining       = 0;
+  bd->head            = 0;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB_FS_IRQn);
+  const unsigned epn = ep_addr & 0xFu;
+  const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
+
+  if (bd->own) {
+    TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head);
+    return false; /* The last transfer has not completed */
+  }
+  ep->length    = total_bytes;
+  ep->remaining = total_bytes;
+
+  const unsigned mps = ep->max_packet_size;
+  if (total_bytes > mps) {
+    buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
+    /* When total_bytes is greater than the max packet size,
+     * it prepares to the next transfer to avoid NAK in advance. */
+    next->bc   = total_bytes >= 2 * mps ? mps: total_bytes - mps;
+    next->addr = buffer + mps;
+    next->own  = 1;
+  }
+  bd->bc        = total_bytes >= mps ? mps: total_bytes;
+  bd->addr      = buffer;
+  __DSB();
+  bd->own  = 1; /* the own bit must set after addr */
+  NVIC_EnableIRQ(USB_FS_IRQn);
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  const unsigned epn = ep_addr & 0xFu;
+  if (0 == epn) {
+    USB_OTG_FS->EP_CTL[epn] |=  USB_ENDPT_EPSTALL_MASK;
+  } else {
+    const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+    buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+    bd[0].bdt_stall = 1;
+    bd[1].bdt_stall = 1;
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  const unsigned epn      = ep_addr & 0xFu;
+  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned odd      = _dcd.endpoint[epn][dir].odd;
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+
+  bd[odd ^ 1].own       = 0;
+  bd[odd ^ 1].data      = 1;
+  bd[odd ^ 1].bdt_stall = 0;
+  bd[odd].own           = 0;
+  bd[odd].data          = 0;
+  bd[odd].bdt_stall     = 0;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_int_handler(uint8_t rhport)
+{
+  (void) rhport;
+
+  uint32_t is  = USB_OTG_FS->INT_STAT;
+  uint32_t msk = USB_OTG_FS->INT_ENB;
+  USB_OTG_FS->INT_STAT = is & ~msk;
+  is &= msk;
+  if (is & USB_ISTAT_ERROR_MASK) {
+    /* TODO: */
+    uint32_t es = USB_OTG_FS->ERR_STAT;
+    USB_OTG_FS->ERR_STAT = es;
+    USB_OTG_FS->INT_STAT   = is; /* discard any pending events */
+    return;
+  }
+
+  if (is & USB_ISTAT_USBRST_MASK) {
+    USB_OTG_FS->INT_STAT = is; /* discard any pending events */
+    process_bus_reset(rhport);
+    return;
+  }
+  if (is & USB_ISTAT_SLEEP_MASK) {
+    USB_OTG_FS->INT_STAT = USB_ISTAT_SLEEP_MASK;
+    process_bus_inactive(rhport);
+    return;
+  }
+  if (is & USB_ISTAT_RESUME_MASK) {
+    USB_OTG_FS->INT_STAT = USB_ISTAT_RESUME_MASK;
+    process_bus_active(rhport);
+    return;
+  }
+  if (is & USB_ISTAT_SOFTOK_MASK) {
+    USB_OTG_FS->INT_STAT = USB_ISTAT_SOFTOK_MASK;
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+    return;
+  }
+  if (is & USB_ISTAT_STALL_MASK) {
+    USB_OTG_FS->INT_STAT = USB_ISTAT_STALL_MASK;
+    process_stall(rhport);
+    return;
+  }
+  if (is & USB_ISTAT_TOKDNE_MASK) {
+    process_tokdne(rhport);
+    return;
+  }
+}
+
+#endif

From c2b85c8d6d7fb0cc202e4f1dd0f5e8b359c27396 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Jun 2021 18:51:44 +0700
Subject: [PATCH 0011/2085] add OPT_MCU_MM32F327X

move dcd_mm32f into mindmotion folder
---
 src/portable/{ => mindmotion}/mm32/dcd_mm32f327x_otg.c | 8 ++++----
 src/tusb_option.h                                      | 3 +++
 2 files changed, 7 insertions(+), 4 deletions(-)
 rename src/portable/{ => mindmotion}/mm32/dcd_mm32f327x_otg.c (99%)

diff --git a/src/portable/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
similarity index 99%
rename from src/portable/mm32/dcd_mm32f327x_otg.c
rename to src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
index e7518830e..59a40dc68 100644
--- a/src/portable/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 SE TEAM
@@ -25,12 +25,12 @@
  */
 
 #include "tusb_option.h"
-#include "reg_usb_otg_fs.h"
-#include "mm32_device.h"
-#include "hal_conf.h"
 
 #if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MM32F327X )
 
+#include "reg_usb_otg_fs.h"
+#include "mm32_device.h"
+#include "hal_conf.h"
 #include "device/dcd.h"
 
 //--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index cdaf074db..5cfcc08e2 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -113,6 +113,9 @@
 // Renesas RX
 #define OPT_MCU_RX63X            1400 ///< Renesas RX63N/631
 
+// Mind Motion
+#define OPT_MCU_MM32F327X        1500 ///< Mind Motion MM32F327
+
 /** @} */
 
 /** \defgroup group_supported_os Supported RTOS

From fee323e42b8f9b840946efbb7e5517e0b8f18914 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Mon, 7 Jun 2021 19:04:21 +0200
Subject: [PATCH 0012/2085] Add optional support for 32 gamepad buttons

---
 src/class/hid/hid.h        | 40 ++++++++++++++++++++++++++++++++++++--
 src/class/hid/hid_device.h |  9 ++++-----
 src/tusb_option.h          |  6 ++++++
 3 files changed, 48 insertions(+), 7 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 5cc9233b5..3c45dc6c1 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -33,10 +33,12 @@
 
 #include "common/tusb_common.h"
 
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
+
 //--------------------------------------------------------------------+
 // Common Definitions
 //--------------------------------------------------------------------+
@@ -150,6 +152,22 @@ typedef enum
 
 /** @} */
 
+#ifndef CFG_TUD_HID_EP_BUFSIZE
+  #define CFG_TUD_HID_EP_BUFSIZE     64
+#endif
+
+#ifndef CFG_TUSB_MAX_BUTTONS
+  #define CFG_TUSB_MAX_BUTTONS       16
+#endif
+
+#if (CFG_TUSB_MAX_BUTTONS == 16)
+  typedef uint16_t hid_gamepad_buttons_t;
+#elif (CFG_TUSB_MAX_BUTTONS == 32)
+  typedef uint32_t hid_gamepad_buttons_t;
+#else
+  #error "Invalid CFG_TUSB_MAX_BUTTONS value."
+#endif
+
 //--------------------------------------------------------------------+
 // GAMEPAD
 //--------------------------------------------------------------------+
@@ -201,7 +219,7 @@ typedef struct TU_ATTR_PACKED
   int8_t  rx;        ///< Delta Rx movement of analog left trigger
   int8_t  ry;        ///< Delta Ry movement of analog right trigger
   uint8_t hat;       ///< Buttons mask for currently pressed buttons in the DPad/hat
-  uint16_t buttons;  ///< Buttons mask for currently pressed buttons
+  hid_gamepad_buttons_t buttons;  ///< Buttons mask for currently pressed buttons
 }hid_gamepad_report_t;
 
 /// Standard Gamepad Buttons Bitmap (from Linux input event codes)
@@ -222,7 +240,25 @@ typedef enum
   GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
   GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
-//GAMEPAD_BUTTON_       = TU_BIT(15), ///< Undefined button
+  GAMEPAD_BUTTON_15     = TU_BIT(15), ///< Button 15
+#ifdef CFG_TUSB_MAX_BUTTONS_32
+  GAMEPAD_BUTTON_17     = TU_BIT(16), ///< Button 17
+  GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 16
+  GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 16
+  GAMEPAD_BUTTON_20     = TU_BIT(19), ///< Button 16
+  GAMEPAD_BUTTON_21     = TU_BIT(20), ///< Button 16
+  GAMEPAD_BUTTON_22     = TU_BIT(21), ///< Button 16
+  GAMEPAD_BUTTON_23     = TU_BIT(22), ///< Button 16
+  GAMEPAD_BUTTON_24     = TU_BIT(23), ///< Button 16
+  GAMEPAD_BUTTON_25     = TU_BIT(24), ///< Button 16
+  GAMEPAD_BUTTON_26     = TU_BIT(25), ///< Button 16
+  GAMEPAD_BUTTON_27     = TU_BIT(26), ///< Button 16
+  GAMEPAD_BUTTON_28     = TU_BIT(27), ///< Button 16
+  GAMEPAD_BUTTON_29     = TU_BIT(28), ///< Button 16
+  GAMEPAD_BUTTON_30     = TU_BIT(29), ///< Button 16
+  GAMEPAD_BUTTON_31     = TU_BIT(30), ///< Button 16
+  GAMEPAD_BUTTON_32     = TU_BIT(31), ///< Button 16
+#endif
 }hid_gamepad_button_bm_t;
 
 /// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes)
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index beb755888..0ff5cab3f 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -43,9 +43,8 @@
   #define CFG_TUD_HID_EP_BUFSIZE  CFG_TUD_HID_BUFSIZE
 #endif
 
-#ifndef CFG_TUD_HID_EP_BUFSIZE
-  #define CFG_TUD_HID_EP_BUFSIZE     64
-#endif
+
+
 
 //--------------------------------------------------------------------+
 // Application API (Multiple Instances)
@@ -344,10 +343,10 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     /* 16 bit Button Map */ \
     HID_USAGE_PAGE   ( HID_USAGE_PAGE_BUTTON                  ) ,\
     HID_USAGE_MIN    ( 1                                      ) ,\
-    HID_USAGE_MAX    ( 16                                     ) ,\
+    HID_USAGE_MAX    ( CFG_TUSB_MAX_BUTTONS                   ) ,\
     HID_LOGICAL_MIN  ( 0                                      ) ,\
     HID_LOGICAL_MAX  ( 1                                      ) ,\
-    HID_REPORT_COUNT ( 16                                     ) ,\
+    HID_REPORT_COUNT ( CFG_TUSB_MAX_BUTTONS                   ) ,\
     HID_REPORT_SIZE  ( 1                                      ) ,\
     HID_INPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
   HID_COLLECTION_END \
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 5cfcc08e2..a7939d9c7 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -316,6 +316,12 @@
   #error Control Endpoint Max Packet Size cannot be larger than 64
 #endif
 
+#ifndef TUD_OPT_GAMEPAD_32_BUTTONS
+  #define CFG_TUSB_MAX_BUTTONS  16
+#else
+  #define CFG_TUSB_MAX_BUTTONS  32
+#endif
+
 #endif /* _TUSB_OPTION_H_ */
 
 /** @} */

From 10fca2371cf95fe4ef485c83118262c7456355a9 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Mon, 7 Jun 2021 20:16:05 +0200
Subject: [PATCH 0013/2085] clean up

---
 src/class/hid/hid.h        | 16 ++++++----------
 src/class/hid/hid_device.h |  4 ++--
 src/tusb_option.h          | 17 +++++++++++++----
 3 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 3c45dc6c1..eac30c62e 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -152,20 +152,16 @@ typedef enum
 
 /** @} */
 
-#ifndef CFG_TUD_HID_EP_BUFSIZE
-  #define CFG_TUD_HID_EP_BUFSIZE     64
+#ifndef CFG_TUD_MAX_BUTTONS
+  #define CFG_TUD_MAX_BUTTONS     16
 #endif
 
-#ifndef CFG_TUSB_MAX_BUTTONS
-  #define CFG_TUSB_MAX_BUTTONS       16
-#endif
-
-#if (CFG_TUSB_MAX_BUTTONS == 16)
+#if (CFG_TUD_MAX_BUTTONS == 16)
   typedef uint16_t hid_gamepad_buttons_t;
-#elif (CFG_TUSB_MAX_BUTTONS == 32)
+#elif (CFG_TUD_MAX_BUTTONS == 32)
   typedef uint32_t hid_gamepad_buttons_t;
 #else
-  #error "Invalid CFG_TUSB_MAX_BUTTONS value."
+  #error "Invalid CFG_TUD_MAX_BUTTONS value."
 #endif
 
 //--------------------------------------------------------------------+
@@ -241,7 +237,7 @@ typedef enum
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
   GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
   GAMEPAD_BUTTON_15     = TU_BIT(15), ///< Button 15
-#ifdef CFG_TUSB_MAX_BUTTONS_32
+#if (CFG_TUD_MAX_BUTTONS > 16)
   GAMEPAD_BUTTON_17     = TU_BIT(16), ///< Button 17
   GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 16
   GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 16
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 0ff5cab3f..39ec6be76 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -343,10 +343,10 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     /* 16 bit Button Map */ \
     HID_USAGE_PAGE   ( HID_USAGE_PAGE_BUTTON                  ) ,\
     HID_USAGE_MIN    ( 1                                      ) ,\
-    HID_USAGE_MAX    ( CFG_TUSB_MAX_BUTTONS                   ) ,\
+    HID_USAGE_MAX    ( CFG_TUD_MAX_BUTTONS                    ) ,\
     HID_LOGICAL_MIN  ( 0                                      ) ,\
     HID_LOGICAL_MAX  ( 1                                      ) ,\
-    HID_REPORT_COUNT ( CFG_TUSB_MAX_BUTTONS                   ) ,\
+    HID_REPORT_COUNT ( CFG_TUD_MAX_BUTTONS                    ) ,\
     HID_REPORT_SIZE  ( 1                                      ) ,\
     HID_INPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
   HID_COLLECTION_END \
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a7939d9c7..3adb4fcf9 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -309,6 +309,16 @@
   #define TUP_MCU_STRICT_ALIGN   0
 #endif
 
+//--------------------------------------------------------------------+
+// HID Gamepad options
+//--------------------------------------------------------------------+
+
+// CFG_TUD_MAX_BUTTONS lets you choose if you want 16 or 32 buttons  on you HID gamepad
+#ifndef CFG_TUD_MAX_BUTTONS
+  #define CFG_TUD_MAX_BUTTONS  16
+#endif
+
+
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------
@@ -316,10 +326,9 @@
   #error Control Endpoint Max Packet Size cannot be larger than 64
 #endif
 
-#ifndef TUD_OPT_GAMEPAD_32_BUTTONS
-  #define CFG_TUSB_MAX_BUTTONS  16
-#else
-  #define CFG_TUSB_MAX_BUTTONS  32
+
+#if (CFG_TUD_MAX_BUTTONS != 16 && CFG_TUD_MAX_BUTTONS != 32)
+  #error "Unsupported CFG_TUD_MAX_BUTTONS"
 #endif
 
 #endif /* _TUSB_OPTION_H_ */

From 8915e6be9297050049939218cf2833cf9f94dce7 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Mon, 7 Jun 2021 20:44:53 +0200
Subject: [PATCH 0014/2085] remove excess empty lines

---
 src/class/hid/hid.h | 2 --
 src/tusb_option.h   | 1 -
 2 files changed, 3 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index eac30c62e..0764bc228 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -33,12 +33,10 @@
 
 #include "common/tusb_common.h"
 
-
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-
 //--------------------------------------------------------------------+
 // Common Definitions
 //--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 3adb4fcf9..6a6e31ee9 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -318,7 +318,6 @@
   #define CFG_TUD_MAX_BUTTONS  16
 #endif
 
-
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------

From 89a53457d4859c794ca5d42ae720b3d777089068 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Mon, 7 Jun 2021 21:29:24 +0200
Subject: [PATCH 0015/2085] Add CFG_TUD_MAX_BUTTONS to the example

---
 examples/device/hid_composite/src/tusb_config.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index 3e608ed37..bc9192d13 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -104,6 +104,10 @@
 // HID buffer size Should be sufficient to hold ID (if any) + Data
 #define CFG_TUD_HID_EP_BUFSIZE    16
 
+// Number of button on the gamepad 16 or 32
+#define CFG_TUD_MAX_BUTTONS       16
+
+
 #ifdef __cplusplus
  }
 #endif

From 501de2a5e8232752defb28f8cd97f24595a61cf2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Jun 2021 14:33:24 +0700
Subject: [PATCH 0016/2085] fix computing transferred bytes with E4

---
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index a0263612f..31381e6c2 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -205,10 +205,7 @@ void _hw_endpoint_xfer_sync(struct hw_endpoint *ep)
     // Update hw endpoint struct with info from hardware
     // after a buff status interrupt
 
-    // Get the buffer state and amount of bytes we have
-    // transferred
     uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
-    uint16_t transferred_bytes = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
 
 #if TUSB_OPT_HOST_ENABLED
     // RP2040-E4
@@ -227,6 +224,9 @@ void _hw_endpoint_xfer_sync(struct hw_endpoint *ep)
     // end::host_buf_sel_fix[]
 #endif
 
+    // Get tranferred bytes after adjusted buf sel
+    uint16_t const transferred_bytes = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
+
     // We are continuing a transfer here. If we are TX, we have successfullly
     // sent some data can increase the length we have sent
     if (!ep->rx)
@@ -249,7 +249,7 @@ void _hw_endpoint_xfer_sync(struct hw_endpoint *ep)
     // Sometimes the host will send less data than we expect...
     // If this is a short out transfer update the total length of the transfer
     // to be the current length
-    if ((ep->rx) && (transferred_bytes < ep->transfer_size))
+    if ((ep->rx) && (transferred_bytes < ep->wMaxPacketSize))
     {
         pico_trace("Short rx transfer\n");
         // Reduce total length as this is last packet
@@ -289,8 +289,7 @@ bool _hw_endpoint_xfer_continue(struct hw_endpoint *ep)
     {
         pico_trace("Completed transfer of %d bytes on ep %d %s\n",
                    ep->len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
-        // Notify caller we are done so it can notify the tinyusb
-        // stack
+        // Notify caller we are done so it can notify the tinyusb stack
         _hw_endpoint_lock_update(ep, -1);
         return true;
     }

From 05d30b0c3766832329bb4e414f91e72be62d3c45 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Tue, 8 Jun 2021 09:24:50 +0200
Subject: [PATCH 0017/2085] Pull request changes

Remove configuration options and just bump number of buttons to 32
Fix button numbereing and comments in
---
 .../device/hid_composite/src/tusb_config.h    |  4 --
 src/class/hid/hid.h                           | 48 +++++++------------
 src/class/hid/hid_device.h                    |  4 +-
 src/tusb_option.h                             | 14 ------
 4 files changed, 19 insertions(+), 51 deletions(-)

diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index bc9192d13..3e608ed37 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -104,10 +104,6 @@
 // HID buffer size Should be sufficient to hold ID (if any) + Data
 #define CFG_TUD_HID_EP_BUFSIZE    16
 
-// Number of button on the gamepad 16 or 32
-#define CFG_TUD_MAX_BUTTONS       16
-
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 0764bc228..a344c9100 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -150,18 +150,6 @@ typedef enum
 
 /** @} */
 
-#ifndef CFG_TUD_MAX_BUTTONS
-  #define CFG_TUD_MAX_BUTTONS     16
-#endif
-
-#if (CFG_TUD_MAX_BUTTONS == 16)
-  typedef uint16_t hid_gamepad_buttons_t;
-#elif (CFG_TUD_MAX_BUTTONS == 32)
-  typedef uint32_t hid_gamepad_buttons_t;
-#else
-  #error "Invalid CFG_TUD_MAX_BUTTONS value."
-#endif
-
 //--------------------------------------------------------------------+
 // GAMEPAD
 //--------------------------------------------------------------------+
@@ -213,7 +201,7 @@ typedef struct TU_ATTR_PACKED
   int8_t  rx;        ///< Delta Rx movement of analog left trigger
   int8_t  ry;        ///< Delta Ry movement of analog right trigger
   uint8_t hat;       ///< Buttons mask for currently pressed buttons in the DPad/hat
-  hid_gamepad_buttons_t buttons;  ///< Buttons mask for currently pressed buttons
+  uint32_t buttons;  ///< Buttons mask for currently pressed buttons
 }hid_gamepad_report_t;
 
 /// Standard Gamepad Buttons Bitmap (from Linux input event codes)
@@ -234,25 +222,23 @@ typedef enum
   GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
   GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
-  GAMEPAD_BUTTON_15     = TU_BIT(15), ///< Button 15
-#if (CFG_TUD_MAX_BUTTONS > 16)
+  GAMEPAD_BUTTON_16     = TU_BIT(15), ///< Button 15
   GAMEPAD_BUTTON_17     = TU_BIT(16), ///< Button 17
-  GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 16
-  GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 16
-  GAMEPAD_BUTTON_20     = TU_BIT(19), ///< Button 16
-  GAMEPAD_BUTTON_21     = TU_BIT(20), ///< Button 16
-  GAMEPAD_BUTTON_22     = TU_BIT(21), ///< Button 16
-  GAMEPAD_BUTTON_23     = TU_BIT(22), ///< Button 16
-  GAMEPAD_BUTTON_24     = TU_BIT(23), ///< Button 16
-  GAMEPAD_BUTTON_25     = TU_BIT(24), ///< Button 16
-  GAMEPAD_BUTTON_26     = TU_BIT(25), ///< Button 16
-  GAMEPAD_BUTTON_27     = TU_BIT(26), ///< Button 16
-  GAMEPAD_BUTTON_28     = TU_BIT(27), ///< Button 16
-  GAMEPAD_BUTTON_29     = TU_BIT(28), ///< Button 16
-  GAMEPAD_BUTTON_30     = TU_BIT(29), ///< Button 16
-  GAMEPAD_BUTTON_31     = TU_BIT(30), ///< Button 16
-  GAMEPAD_BUTTON_32     = TU_BIT(31), ///< Button 16
-#endif
+  GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 18
+  GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 19
+  GAMEPAD_BUTTON_20     = TU_BIT(19), ///< Button 20
+  GAMEPAD_BUTTON_21     = TU_BIT(20), ///< Button 21
+  GAMEPAD_BUTTON_22     = TU_BIT(21), ///< Button 22
+  GAMEPAD_BUTTON_23     = TU_BIT(22), ///< Button 23
+  GAMEPAD_BUTTON_24     = TU_BIT(23), ///< Button 24
+  GAMEPAD_BUTTON_25     = TU_BIT(24), ///< Button 25
+  GAMEPAD_BUTTON_26     = TU_BIT(25), ///< Button 26
+  GAMEPAD_BUTTON_27     = TU_BIT(26), ///< Button 27
+  GAMEPAD_BUTTON_28     = TU_BIT(27), ///< Button 28
+  GAMEPAD_BUTTON_29     = TU_BIT(28), ///< Button 29
+  GAMEPAD_BUTTON_30     = TU_BIT(29), ///< Button 30
+  GAMEPAD_BUTTON_31     = TU_BIT(30), ///< Button 31
+  GAMEPAD_BUTTON_32     = TU_BIT(31), ///< Button 32
 }hid_gamepad_button_bm_t;
 
 /// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes)
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 39ec6be76..543bc3b3b 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -343,10 +343,10 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     /* 16 bit Button Map */ \
     HID_USAGE_PAGE   ( HID_USAGE_PAGE_BUTTON                  ) ,\
     HID_USAGE_MIN    ( 1                                      ) ,\
-    HID_USAGE_MAX    ( CFG_TUD_MAX_BUTTONS                    ) ,\
+    HID_USAGE_MAX    ( 32                                     ) ,\
     HID_LOGICAL_MIN  ( 0                                      ) ,\
     HID_LOGICAL_MAX  ( 1                                      ) ,\
-    HID_REPORT_COUNT ( CFG_TUD_MAX_BUTTONS                    ) ,\
+    HID_REPORT_COUNT ( 32                                     ) ,\
     HID_REPORT_SIZE  ( 1                                      ) ,\
     HID_INPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
   HID_COLLECTION_END \
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 6a6e31ee9..5cfcc08e2 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -309,15 +309,6 @@
   #define TUP_MCU_STRICT_ALIGN   0
 #endif
 
-//--------------------------------------------------------------------+
-// HID Gamepad options
-//--------------------------------------------------------------------+
-
-// CFG_TUD_MAX_BUTTONS lets you choose if you want 16 or 32 buttons  on you HID gamepad
-#ifndef CFG_TUD_MAX_BUTTONS
-  #define CFG_TUD_MAX_BUTTONS  16
-#endif
-
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------
@@ -325,11 +316,6 @@
   #error Control Endpoint Max Packet Size cannot be larger than 64
 #endif
 
-
-#if (CFG_TUD_MAX_BUTTONS != 16 && CFG_TUD_MAX_BUTTONS != 32)
-  #error "Unsupported CFG_TUD_MAX_BUTTONS"
-#endif
-
 #endif /* _TUSB_OPTION_H_ */
 
 /** @} */

From 05b39aac5ff80103d154bf59970957b93e0c2d84 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Tue, 8 Jun 2021 09:26:17 +0200
Subject: [PATCH 0018/2085] Fix comment in hid.h

---
 src/class/hid/hid.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index a344c9100..8ab24ab3e 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -217,12 +217,12 @@ typedef enum
   GAMEPAD_BUTTON_TR     = TU_BIT(7),  ///< R1 button
   GAMEPAD_BUTTON_TL2    = TU_BIT(8),  ///< L2 button
   GAMEPAD_BUTTON_TR2    = TU_BIT(9),  ///< R2 button
-  GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button
+ GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button
   GAMEPAD_BUTTON_START  = TU_BIT(11), ///< Start button
   GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
   GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
-  GAMEPAD_BUTTON_16     = TU_BIT(15), ///< Button 15
+  GAMEPAD_BUTTON_16     = TU_BIT(15), ///< Button 16
   GAMEPAD_BUTTON_17     = TU_BIT(16), ///< Button 17
   GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 18
   GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 19

From b18769fe8e22a49a41bc5c8bac2fe97bbe19634f Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Tue, 8 Jun 2021 09:31:40 +0200
Subject: [PATCH 0019/2085] indent fix

---
 src/class/hid/hid.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 8ab24ab3e..782a1a552 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -217,7 +217,7 @@ typedef enum
   GAMEPAD_BUTTON_TR     = TU_BIT(7),  ///< R1 button
   GAMEPAD_BUTTON_TL2    = TU_BIT(8),  ///< L2 button
   GAMEPAD_BUTTON_TR2    = TU_BIT(9),  ///< R2 button
- GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button
+  GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button
   GAMEPAD_BUTTON_START  = TU_BIT(11), ///< Start button
   GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button

From 95481d4c7fc88e3f1887e88831f5d75336879581 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Tue, 8 Jun 2021 09:39:53 +0200
Subject: [PATCH 0020/2085] re-adding ifdef removed accidentally

---
 src/class/hid/hid_device.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 543bc3b3b..1d1213e3f 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -43,8 +43,9 @@
   #define CFG_TUD_HID_EP_BUFSIZE  CFG_TUD_HID_BUFSIZE
 #endif
 
-
-
+#ifndef CFG_TUD_HID_EP_BUFSIZE
+  #define CFG_TUD_HID_EP_BUFSIZE     64
+#endif
 
 //--------------------------------------------------------------------+
 // Application API (Multiple Instances)

From d5f8da44d13d3410f6c710432062807b52ebf407 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Mon, 7 Jun 2021 19:04:21 +0200
Subject: [PATCH 0021/2085] Add optional support for 32 gamepad buttons

---
 src/class/hid/hid.h        | 40 ++++++++++++++++++++++++++++++++++++--
 src/class/hid/hid_device.h |  9 ++++-----
 src/tusb_option.h          |  6 ++++++
 3 files changed, 48 insertions(+), 7 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 5cc9233b5..3c45dc6c1 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -33,10 +33,12 @@
 
 #include "common/tusb_common.h"
 
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
+
 //--------------------------------------------------------------------+
 // Common Definitions
 //--------------------------------------------------------------------+
@@ -150,6 +152,22 @@ typedef enum
 
 /** @} */
 
+#ifndef CFG_TUD_HID_EP_BUFSIZE
+  #define CFG_TUD_HID_EP_BUFSIZE     64
+#endif
+
+#ifndef CFG_TUSB_MAX_BUTTONS
+  #define CFG_TUSB_MAX_BUTTONS       16
+#endif
+
+#if (CFG_TUSB_MAX_BUTTONS == 16)
+  typedef uint16_t hid_gamepad_buttons_t;
+#elif (CFG_TUSB_MAX_BUTTONS == 32)
+  typedef uint32_t hid_gamepad_buttons_t;
+#else
+  #error "Invalid CFG_TUSB_MAX_BUTTONS value."
+#endif
+
 //--------------------------------------------------------------------+
 // GAMEPAD
 //--------------------------------------------------------------------+
@@ -201,7 +219,7 @@ typedef struct TU_ATTR_PACKED
   int8_t  rx;        ///< Delta Rx movement of analog left trigger
   int8_t  ry;        ///< Delta Ry movement of analog right trigger
   uint8_t hat;       ///< Buttons mask for currently pressed buttons in the DPad/hat
-  uint16_t buttons;  ///< Buttons mask for currently pressed buttons
+  hid_gamepad_buttons_t buttons;  ///< Buttons mask for currently pressed buttons
 }hid_gamepad_report_t;
 
 /// Standard Gamepad Buttons Bitmap (from Linux input event codes)
@@ -222,7 +240,25 @@ typedef enum
   GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
   GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
-//GAMEPAD_BUTTON_       = TU_BIT(15), ///< Undefined button
+  GAMEPAD_BUTTON_15     = TU_BIT(15), ///< Button 15
+#ifdef CFG_TUSB_MAX_BUTTONS_32
+  GAMEPAD_BUTTON_17     = TU_BIT(16), ///< Button 17
+  GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 16
+  GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 16
+  GAMEPAD_BUTTON_20     = TU_BIT(19), ///< Button 16
+  GAMEPAD_BUTTON_21     = TU_BIT(20), ///< Button 16
+  GAMEPAD_BUTTON_22     = TU_BIT(21), ///< Button 16
+  GAMEPAD_BUTTON_23     = TU_BIT(22), ///< Button 16
+  GAMEPAD_BUTTON_24     = TU_BIT(23), ///< Button 16
+  GAMEPAD_BUTTON_25     = TU_BIT(24), ///< Button 16
+  GAMEPAD_BUTTON_26     = TU_BIT(25), ///< Button 16
+  GAMEPAD_BUTTON_27     = TU_BIT(26), ///< Button 16
+  GAMEPAD_BUTTON_28     = TU_BIT(27), ///< Button 16
+  GAMEPAD_BUTTON_29     = TU_BIT(28), ///< Button 16
+  GAMEPAD_BUTTON_30     = TU_BIT(29), ///< Button 16
+  GAMEPAD_BUTTON_31     = TU_BIT(30), ///< Button 16
+  GAMEPAD_BUTTON_32     = TU_BIT(31), ///< Button 16
+#endif
 }hid_gamepad_button_bm_t;
 
 /// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes)
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index beb755888..0ff5cab3f 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -43,9 +43,8 @@
   #define CFG_TUD_HID_EP_BUFSIZE  CFG_TUD_HID_BUFSIZE
 #endif
 
-#ifndef CFG_TUD_HID_EP_BUFSIZE
-  #define CFG_TUD_HID_EP_BUFSIZE     64
-#endif
+
+
 
 //--------------------------------------------------------------------+
 // Application API (Multiple Instances)
@@ -344,10 +343,10 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     /* 16 bit Button Map */ \
     HID_USAGE_PAGE   ( HID_USAGE_PAGE_BUTTON                  ) ,\
     HID_USAGE_MIN    ( 1                                      ) ,\
-    HID_USAGE_MAX    ( 16                                     ) ,\
+    HID_USAGE_MAX    ( CFG_TUSB_MAX_BUTTONS                   ) ,\
     HID_LOGICAL_MIN  ( 0                                      ) ,\
     HID_LOGICAL_MAX  ( 1                                      ) ,\
-    HID_REPORT_COUNT ( 16                                     ) ,\
+    HID_REPORT_COUNT ( CFG_TUSB_MAX_BUTTONS                   ) ,\
     HID_REPORT_SIZE  ( 1                                      ) ,\
     HID_INPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
   HID_COLLECTION_END \
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 5cfcc08e2..a7939d9c7 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -316,6 +316,12 @@
   #error Control Endpoint Max Packet Size cannot be larger than 64
 #endif
 
+#ifndef TUD_OPT_GAMEPAD_32_BUTTONS
+  #define CFG_TUSB_MAX_BUTTONS  16
+#else
+  #define CFG_TUSB_MAX_BUTTONS  32
+#endif
+
 #endif /* _TUSB_OPTION_H_ */
 
 /** @} */

From 3842c806a6bd90a3be8431c4fa3fb8c46220a6bf Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Mon, 7 Jun 2021 20:16:05 +0200
Subject: [PATCH 0022/2085] clean up

---
 src/class/hid/hid.h        | 16 ++++++----------
 src/class/hid/hid_device.h |  4 ++--
 src/tusb_option.h          | 17 +++++++++++++----
 3 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 3c45dc6c1..eac30c62e 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -152,20 +152,16 @@ typedef enum
 
 /** @} */
 
-#ifndef CFG_TUD_HID_EP_BUFSIZE
-  #define CFG_TUD_HID_EP_BUFSIZE     64
+#ifndef CFG_TUD_MAX_BUTTONS
+  #define CFG_TUD_MAX_BUTTONS     16
 #endif
 
-#ifndef CFG_TUSB_MAX_BUTTONS
-  #define CFG_TUSB_MAX_BUTTONS       16
-#endif
-
-#if (CFG_TUSB_MAX_BUTTONS == 16)
+#if (CFG_TUD_MAX_BUTTONS == 16)
   typedef uint16_t hid_gamepad_buttons_t;
-#elif (CFG_TUSB_MAX_BUTTONS == 32)
+#elif (CFG_TUD_MAX_BUTTONS == 32)
   typedef uint32_t hid_gamepad_buttons_t;
 #else
-  #error "Invalid CFG_TUSB_MAX_BUTTONS value."
+  #error "Invalid CFG_TUD_MAX_BUTTONS value."
 #endif
 
 //--------------------------------------------------------------------+
@@ -241,7 +237,7 @@ typedef enum
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
   GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
   GAMEPAD_BUTTON_15     = TU_BIT(15), ///< Button 15
-#ifdef CFG_TUSB_MAX_BUTTONS_32
+#if (CFG_TUD_MAX_BUTTONS > 16)
   GAMEPAD_BUTTON_17     = TU_BIT(16), ///< Button 17
   GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 16
   GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 16
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 0ff5cab3f..39ec6be76 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -343,10 +343,10 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     /* 16 bit Button Map */ \
     HID_USAGE_PAGE   ( HID_USAGE_PAGE_BUTTON                  ) ,\
     HID_USAGE_MIN    ( 1                                      ) ,\
-    HID_USAGE_MAX    ( CFG_TUSB_MAX_BUTTONS                   ) ,\
+    HID_USAGE_MAX    ( CFG_TUD_MAX_BUTTONS                    ) ,\
     HID_LOGICAL_MIN  ( 0                                      ) ,\
     HID_LOGICAL_MAX  ( 1                                      ) ,\
-    HID_REPORT_COUNT ( CFG_TUSB_MAX_BUTTONS                   ) ,\
+    HID_REPORT_COUNT ( CFG_TUD_MAX_BUTTONS                    ) ,\
     HID_REPORT_SIZE  ( 1                                      ) ,\
     HID_INPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
   HID_COLLECTION_END \
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a7939d9c7..3adb4fcf9 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -309,6 +309,16 @@
   #define TUP_MCU_STRICT_ALIGN   0
 #endif
 
+//--------------------------------------------------------------------+
+// HID Gamepad options
+//--------------------------------------------------------------------+
+
+// CFG_TUD_MAX_BUTTONS lets you choose if you want 16 or 32 buttons  on you HID gamepad
+#ifndef CFG_TUD_MAX_BUTTONS
+  #define CFG_TUD_MAX_BUTTONS  16
+#endif
+
+
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------
@@ -316,10 +326,9 @@
   #error Control Endpoint Max Packet Size cannot be larger than 64
 #endif
 
-#ifndef TUD_OPT_GAMEPAD_32_BUTTONS
-  #define CFG_TUSB_MAX_BUTTONS  16
-#else
-  #define CFG_TUSB_MAX_BUTTONS  32
+
+#if (CFG_TUD_MAX_BUTTONS != 16 && CFG_TUD_MAX_BUTTONS != 32)
+  #error "Unsupported CFG_TUD_MAX_BUTTONS"
 #endif
 
 #endif /* _TUSB_OPTION_H_ */

From ce634f226e59cccfb236371f85a62cb610ef80f6 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Mon, 7 Jun 2021 20:44:53 +0200
Subject: [PATCH 0023/2085] remove excess empty lines

---
 src/class/hid/hid.h | 2 --
 src/tusb_option.h   | 1 -
 2 files changed, 3 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index eac30c62e..0764bc228 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -33,12 +33,10 @@
 
 #include "common/tusb_common.h"
 
-
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-
 //--------------------------------------------------------------------+
 // Common Definitions
 //--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 3adb4fcf9..6a6e31ee9 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -318,7 +318,6 @@
   #define CFG_TUD_MAX_BUTTONS  16
 #endif
 
-
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------

From f37c8ed749a7bdc264de132f8d81dec47a7972f6 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Mon, 7 Jun 2021 21:29:24 +0200
Subject: [PATCH 0024/2085] Add CFG_TUD_MAX_BUTTONS to the example

---
 examples/device/hid_composite/src/tusb_config.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index 3e608ed37..bc9192d13 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -104,6 +104,10 @@
 // HID buffer size Should be sufficient to hold ID (if any) + Data
 #define CFG_TUD_HID_EP_BUFSIZE    16
 
+// Number of button on the gamepad 16 or 32
+#define CFG_TUD_MAX_BUTTONS       16
+
+
 #ifdef __cplusplus
  }
 #endif

From e12195705c2b849379145618691c2e8564762aa7 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Tue, 8 Jun 2021 09:24:50 +0200
Subject: [PATCH 0025/2085] Pull request changes

Remove configuration options and just bump number of buttons to 32
Fix button numbereing and comments in
---
 .../device/hid_composite/src/tusb_config.h    |  4 --
 src/class/hid/hid.h                           | 48 +++++++------------
 src/class/hid/hid_device.h                    |  4 +-
 src/tusb_option.h                             | 14 ------
 4 files changed, 19 insertions(+), 51 deletions(-)

diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index bc9192d13..3e608ed37 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -104,10 +104,6 @@
 // HID buffer size Should be sufficient to hold ID (if any) + Data
 #define CFG_TUD_HID_EP_BUFSIZE    16
 
-// Number of button on the gamepad 16 or 32
-#define CFG_TUD_MAX_BUTTONS       16
-
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 0764bc228..a344c9100 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -150,18 +150,6 @@ typedef enum
 
 /** @} */
 
-#ifndef CFG_TUD_MAX_BUTTONS
-  #define CFG_TUD_MAX_BUTTONS     16
-#endif
-
-#if (CFG_TUD_MAX_BUTTONS == 16)
-  typedef uint16_t hid_gamepad_buttons_t;
-#elif (CFG_TUD_MAX_BUTTONS == 32)
-  typedef uint32_t hid_gamepad_buttons_t;
-#else
-  #error "Invalid CFG_TUD_MAX_BUTTONS value."
-#endif
-
 //--------------------------------------------------------------------+
 // GAMEPAD
 //--------------------------------------------------------------------+
@@ -213,7 +201,7 @@ typedef struct TU_ATTR_PACKED
   int8_t  rx;        ///< Delta Rx movement of analog left trigger
   int8_t  ry;        ///< Delta Ry movement of analog right trigger
   uint8_t hat;       ///< Buttons mask for currently pressed buttons in the DPad/hat
-  hid_gamepad_buttons_t buttons;  ///< Buttons mask for currently pressed buttons
+  uint32_t buttons;  ///< Buttons mask for currently pressed buttons
 }hid_gamepad_report_t;
 
 /// Standard Gamepad Buttons Bitmap (from Linux input event codes)
@@ -234,25 +222,23 @@ typedef enum
   GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
   GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
-  GAMEPAD_BUTTON_15     = TU_BIT(15), ///< Button 15
-#if (CFG_TUD_MAX_BUTTONS > 16)
+  GAMEPAD_BUTTON_16     = TU_BIT(15), ///< Button 15
   GAMEPAD_BUTTON_17     = TU_BIT(16), ///< Button 17
-  GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 16
-  GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 16
-  GAMEPAD_BUTTON_20     = TU_BIT(19), ///< Button 16
-  GAMEPAD_BUTTON_21     = TU_BIT(20), ///< Button 16
-  GAMEPAD_BUTTON_22     = TU_BIT(21), ///< Button 16
-  GAMEPAD_BUTTON_23     = TU_BIT(22), ///< Button 16
-  GAMEPAD_BUTTON_24     = TU_BIT(23), ///< Button 16
-  GAMEPAD_BUTTON_25     = TU_BIT(24), ///< Button 16
-  GAMEPAD_BUTTON_26     = TU_BIT(25), ///< Button 16
-  GAMEPAD_BUTTON_27     = TU_BIT(26), ///< Button 16
-  GAMEPAD_BUTTON_28     = TU_BIT(27), ///< Button 16
-  GAMEPAD_BUTTON_29     = TU_BIT(28), ///< Button 16
-  GAMEPAD_BUTTON_30     = TU_BIT(29), ///< Button 16
-  GAMEPAD_BUTTON_31     = TU_BIT(30), ///< Button 16
-  GAMEPAD_BUTTON_32     = TU_BIT(31), ///< Button 16
-#endif
+  GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 18
+  GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 19
+  GAMEPAD_BUTTON_20     = TU_BIT(19), ///< Button 20
+  GAMEPAD_BUTTON_21     = TU_BIT(20), ///< Button 21
+  GAMEPAD_BUTTON_22     = TU_BIT(21), ///< Button 22
+  GAMEPAD_BUTTON_23     = TU_BIT(22), ///< Button 23
+  GAMEPAD_BUTTON_24     = TU_BIT(23), ///< Button 24
+  GAMEPAD_BUTTON_25     = TU_BIT(24), ///< Button 25
+  GAMEPAD_BUTTON_26     = TU_BIT(25), ///< Button 26
+  GAMEPAD_BUTTON_27     = TU_BIT(26), ///< Button 27
+  GAMEPAD_BUTTON_28     = TU_BIT(27), ///< Button 28
+  GAMEPAD_BUTTON_29     = TU_BIT(28), ///< Button 29
+  GAMEPAD_BUTTON_30     = TU_BIT(29), ///< Button 30
+  GAMEPAD_BUTTON_31     = TU_BIT(30), ///< Button 31
+  GAMEPAD_BUTTON_32     = TU_BIT(31), ///< Button 32
 }hid_gamepad_button_bm_t;
 
 /// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes)
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 39ec6be76..543bc3b3b 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -343,10 +343,10 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     /* 16 bit Button Map */ \
     HID_USAGE_PAGE   ( HID_USAGE_PAGE_BUTTON                  ) ,\
     HID_USAGE_MIN    ( 1                                      ) ,\
-    HID_USAGE_MAX    ( CFG_TUD_MAX_BUTTONS                    ) ,\
+    HID_USAGE_MAX    ( 32                                     ) ,\
     HID_LOGICAL_MIN  ( 0                                      ) ,\
     HID_LOGICAL_MAX  ( 1                                      ) ,\
-    HID_REPORT_COUNT ( CFG_TUD_MAX_BUTTONS                    ) ,\
+    HID_REPORT_COUNT ( 32                                     ) ,\
     HID_REPORT_SIZE  ( 1                                      ) ,\
     HID_INPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
   HID_COLLECTION_END \
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 6a6e31ee9..5cfcc08e2 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -309,15 +309,6 @@
   #define TUP_MCU_STRICT_ALIGN   0
 #endif
 
-//--------------------------------------------------------------------+
-// HID Gamepad options
-//--------------------------------------------------------------------+
-
-// CFG_TUD_MAX_BUTTONS lets you choose if you want 16 or 32 buttons  on you HID gamepad
-#ifndef CFG_TUD_MAX_BUTTONS
-  #define CFG_TUD_MAX_BUTTONS  16
-#endif
-
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------
@@ -325,11 +316,6 @@
   #error Control Endpoint Max Packet Size cannot be larger than 64
 #endif
 
-
-#if (CFG_TUD_MAX_BUTTONS != 16 && CFG_TUD_MAX_BUTTONS != 32)
-  #error "Unsupported CFG_TUD_MAX_BUTTONS"
-#endif
-
 #endif /* _TUSB_OPTION_H_ */
 
 /** @} */

From de71e72e31ca1d534e5e0413f9da0a0e84a9aa69 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Tue, 8 Jun 2021 09:26:17 +0200
Subject: [PATCH 0026/2085] Fix comment in hid.h

---
 src/class/hid/hid.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index a344c9100..8ab24ab3e 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -217,12 +217,12 @@ typedef enum
   GAMEPAD_BUTTON_TR     = TU_BIT(7),  ///< R1 button
   GAMEPAD_BUTTON_TL2    = TU_BIT(8),  ///< L2 button
   GAMEPAD_BUTTON_TR2    = TU_BIT(9),  ///< R2 button
-  GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button
+ GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button
   GAMEPAD_BUTTON_START  = TU_BIT(11), ///< Start button
   GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
   GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
-  GAMEPAD_BUTTON_16     = TU_BIT(15), ///< Button 15
+  GAMEPAD_BUTTON_16     = TU_BIT(15), ///< Button 16
   GAMEPAD_BUTTON_17     = TU_BIT(16), ///< Button 17
   GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 18
   GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 19

From d3b6e28387c63a1519cd1958ee7e21bd2980d099 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Tue, 8 Jun 2021 09:31:40 +0200
Subject: [PATCH 0027/2085] indent fix

---
 src/class/hid/hid.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 8ab24ab3e..782a1a552 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -217,7 +217,7 @@ typedef enum
   GAMEPAD_BUTTON_TR     = TU_BIT(7),  ///< R1 button
   GAMEPAD_BUTTON_TL2    = TU_BIT(8),  ///< L2 button
   GAMEPAD_BUTTON_TR2    = TU_BIT(9),  ///< R2 button
- GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button
+  GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button
   GAMEPAD_BUTTON_START  = TU_BIT(11), ///< Start button
   GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button

From e393fb32a0830e9d371f3e335cc0cca92b75cbbb Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Tue, 8 Jun 2021 09:39:53 +0200
Subject: [PATCH 0028/2085] re-adding ifdef removed accidentally

---
 src/class/hid/hid_device.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 543bc3b3b..1d1213e3f 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -43,8 +43,9 @@
   #define CFG_TUD_HID_EP_BUFSIZE  CFG_TUD_HID_BUFSIZE
 #endif
 
-
-
+#ifndef CFG_TUD_HID_EP_BUFSIZE
+  #define CFG_TUD_HID_EP_BUFSIZE     64
+#endif
 
 //--------------------------------------------------------------------+
 // Application API (Multiple Instances)

From 2c0947ebb621e3e53933300cbfd1dce7e0f31338 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Jun 2021 10:30:13 +0700
Subject: [PATCH 0029/2085] update gamepad helper

---
 src/class/hid/hid.h        | 1 +
 src/class/hid/hid_device.c | 2 +-
 src/class/hid/hid_device.h | 6 +++---
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 782a1a552..b4e8a9c4c 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -222,6 +222,7 @@ typedef enum
   GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
   GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
+  // Note: Button number start from 1 on host OS
   GAMEPAD_BUTTON_16     = TU_BIT(15), ///< Button 16
   GAMEPAD_BUTTON_17     = TU_BIT(16), ///< Button 17
   GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 18
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 151a36225..e44f282c4 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -149,7 +149,7 @@ bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id,
 }
 
 bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
-                              int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint16_t buttons)
+                              int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons)
 {
   hid_gamepad_report_t report =
   {
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 1d1213e3f..19e9315f4 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -72,9 +72,9 @@ bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modi
 // use template layout report as defined by hid_mouse_report_t
 bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal);
 
-// Gamepad: convenient helper to send mouse report if application
+// Gamepad: convenient helper to send gamepad report if application
 // use template layout report TUD_HID_REPORT_DESC_GAMEPAD
-bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint16_t buttons);
+bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons);
 
 //--------------------------------------------------------------------+
 // Application API (Single Port)
@@ -85,7 +85,7 @@ static inline uint8_t tud_hid_get_protocol(void);
 static inline bool    tud_hid_report(uint8_t report_id, void const* report, uint8_t len);
 static inline bool    tud_hid_keyboard_report(uint8_t report_id, uint8_t modifier, uint8_t keycode[6]);
 static inline bool    tud_hid_mouse_report(uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal);
-static inline bool    tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint16_t buttons);
+static inline bool    tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons);
 
 //--------------------------------------------------------------------+
 // Callbacks (Weak is optional)

From dca9bc97d66fe2912d2643e4f36cb839d08a31da Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Jun 2021 10:45:37 +0700
Subject: [PATCH 0030/2085] miss a helper

---
 src/class/hid/hid_device.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 19e9315f4..e2c950dd1 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -152,7 +152,7 @@ static inline bool tud_hid_mouse_report(uint8_t report_id, uint8_t buttons, int8
   return tud_hid_n_mouse_report(0, report_id, buttons, x, y, vertical, horizontal);
 }
 
-static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint16_t buttons)
+static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons)
 {
   return tud_hid_n_gamepad_report(0, report_id, x, y, z, rz, rx, ry, hat, buttons);
 }

From d81a37d1bed3e9a905a1472eaafe2f750892eaac Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Jun 2021 12:10:44 +0700
Subject: [PATCH 0031/2085] fix enum overflow with msp430

---
 src/common/tusb_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 3350ed86c..889ad7b25 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -51,7 +51,7 @@
 #define U32_TO_U8S_BE(u32)    TU_U32_BYTE3(u32), TU_U32_BYTE2(u32), TU_U32_BYTE1(u32), TU_U32_BYTE0(u32)
 #define U32_TO_U8S_LE(u32)    TU_U32_BYTE0(u32), TU_U32_BYTE1(u32), TU_U32_BYTE2(u32), TU_U32_BYTE3(u32)
 
-#define TU_BIT(n)             (1U << (n))
+#define TU_BIT(n)             (1UL << (n))
 
 //--------------------------------------------------------------------+
 // Includes

From a8abbcc34df72ff5a63d5567d26276ce84e6d162 Mon Sep 17 00:00:00 2001
From: Marcelo Bezerra <23555060+mmosca@users.noreply.github.com>
Date: Wed, 9 Jun 2021 12:14:04 +0200
Subject: [PATCH 0032/2085] Change buttons to start from 0

---
 src/class/hid/hid.h | 35 +++++++++++++++++------------------
 1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index b4e8a9c4c..3c616d691 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -222,24 +222,23 @@ typedef enum
   GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
   GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
   GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
-  // Note: Button number start from 1 on host OS
-  GAMEPAD_BUTTON_16     = TU_BIT(15), ///< Button 16
-  GAMEPAD_BUTTON_17     = TU_BIT(16), ///< Button 17
-  GAMEPAD_BUTTON_18     = TU_BIT(17), ///< Button 18
-  GAMEPAD_BUTTON_19     = TU_BIT(18), ///< Button 19
-  GAMEPAD_BUTTON_20     = TU_BIT(19), ///< Button 20
-  GAMEPAD_BUTTON_21     = TU_BIT(20), ///< Button 21
-  GAMEPAD_BUTTON_22     = TU_BIT(21), ///< Button 22
-  GAMEPAD_BUTTON_23     = TU_BIT(22), ///< Button 23
-  GAMEPAD_BUTTON_24     = TU_BIT(23), ///< Button 24
-  GAMEPAD_BUTTON_25     = TU_BIT(24), ///< Button 25
-  GAMEPAD_BUTTON_26     = TU_BIT(25), ///< Button 26
-  GAMEPAD_BUTTON_27     = TU_BIT(26), ///< Button 27
-  GAMEPAD_BUTTON_28     = TU_BIT(27), ///< Button 28
-  GAMEPAD_BUTTON_29     = TU_BIT(28), ///< Button 29
-  GAMEPAD_BUTTON_30     = TU_BIT(29), ///< Button 30
-  GAMEPAD_BUTTON_31     = TU_BIT(30), ///< Button 31
-  GAMEPAD_BUTTON_32     = TU_BIT(31), ///< Button 32
+  GAMEPAD_BUTTON_15     = TU_BIT(15), ///< Button 15
+  GAMEPAD_BUTTON_16     = TU_BIT(16), ///< Button 16
+  GAMEPAD_BUTTON_17     = TU_BIT(17), ///< Button 17
+  GAMEPAD_BUTTON_18     = TU_BIT(18), ///< Button 18
+  GAMEPAD_BUTTON_19     = TU_BIT(19), ///< Button 19
+  GAMEPAD_BUTTON_20     = TU_BIT(20), ///< Button 20
+  GAMEPAD_BUTTON_21     = TU_BIT(21), ///< Button 21
+  GAMEPAD_BUTTON_22     = TU_BIT(22), ///< Button 22
+  GAMEPAD_BUTTON_23     = TU_BIT(23), ///< Button 23
+  GAMEPAD_BUTTON_24     = TU_BIT(24), ///< Button 24
+  GAMEPAD_BUTTON_25     = TU_BIT(25), ///< Button 25
+  GAMEPAD_BUTTON_26     = TU_BIT(26), ///< Button 26
+  GAMEPAD_BUTTON_27     = TU_BIT(27), ///< Button 27
+  GAMEPAD_BUTTON_28     = TU_BIT(28), ///< Button 28
+  GAMEPAD_BUTTON_29     = TU_BIT(29), ///< Button 29
+  GAMEPAD_BUTTON_30     = TU_BIT(30), ///< Button 30
+  GAMEPAD_BUTTON_31     = TU_BIT(31), ///< Button 31
 }hid_gamepad_button_bm_t;
 
 /// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes)

From cffa666bd1fd8f0ab45336b36eb79ab1a8f4663d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Jun 2021 17:45:14 +0700
Subject: [PATCH 0033/2085] use alias for button naming

---
 src/class/hid/hid.h | 93 +++++++++++++++++++++++++++++----------------
 1 file changed, 60 insertions(+), 33 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 3c616d691..ec14c9c7c 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -204,43 +204,70 @@ typedef struct TU_ATTR_PACKED
   uint32_t buttons;  ///< Buttons mask for currently pressed buttons
 }hid_gamepad_report_t;
 
-/// Standard Gamepad Buttons Bitmap (from Linux input event codes)
+/// Standard Gamepad Buttons Bitmap
 typedef enum
 {
-  GAMEPAD_BUTTON_A      = TU_BIT(0),  ///< A/South button
-  GAMEPAD_BUTTON_B      = TU_BIT(1),  ///< B/East button
-  GAMEPAD_BUTTON_C      = TU_BIT(2),  ///< C button
-  GAMEPAD_BUTTON_X      = TU_BIT(3),  ///< X/North button
-  GAMEPAD_BUTTON_Y      = TU_BIT(4),  ///< Y/West button
-  GAMEPAD_BUTTON_Z      = TU_BIT(5),  ///< Z button
-  GAMEPAD_BUTTON_TL     = TU_BIT(6),  ///< L1 button
-  GAMEPAD_BUTTON_TR     = TU_BIT(7),  ///< R1 button
-  GAMEPAD_BUTTON_TL2    = TU_BIT(8),  ///< L2 button
-  GAMEPAD_BUTTON_TR2    = TU_BIT(9),  ///< R2 button
-  GAMEPAD_BUTTON_SELECT = TU_BIT(10), ///< Select button
-  GAMEPAD_BUTTON_START  = TU_BIT(11), ///< Start button
-  GAMEPAD_BUTTON_MODE   = TU_BIT(12), ///< Mode button
-  GAMEPAD_BUTTON_THUMBL = TU_BIT(13), ///< L3 button
-  GAMEPAD_BUTTON_THUMBR = TU_BIT(14), ///< R3 button
-  GAMEPAD_BUTTON_15     = TU_BIT(15), ///< Button 15
-  GAMEPAD_BUTTON_16     = TU_BIT(16), ///< Button 16
-  GAMEPAD_BUTTON_17     = TU_BIT(17), ///< Button 17
-  GAMEPAD_BUTTON_18     = TU_BIT(18), ///< Button 18
-  GAMEPAD_BUTTON_19     = TU_BIT(19), ///< Button 19
-  GAMEPAD_BUTTON_20     = TU_BIT(20), ///< Button 20
-  GAMEPAD_BUTTON_21     = TU_BIT(21), ///< Button 21
-  GAMEPAD_BUTTON_22     = TU_BIT(22), ///< Button 22
-  GAMEPAD_BUTTON_23     = TU_BIT(23), ///< Button 23
-  GAMEPAD_BUTTON_24     = TU_BIT(24), ///< Button 24
-  GAMEPAD_BUTTON_25     = TU_BIT(25), ///< Button 25
-  GAMEPAD_BUTTON_26     = TU_BIT(26), ///< Button 26
-  GAMEPAD_BUTTON_27     = TU_BIT(27), ///< Button 27
-  GAMEPAD_BUTTON_28     = TU_BIT(28), ///< Button 28
-  GAMEPAD_BUTTON_29     = TU_BIT(29), ///< Button 29
-  GAMEPAD_BUTTON_30     = TU_BIT(30), ///< Button 30
-  GAMEPAD_BUTTON_31     = TU_BIT(31), ///< Button 31
+  GAMEPAD_BUTTON_0  = TU_BIT(0),
+  GAMEPAD_BUTTON_1  = TU_BIT(1),
+  GAMEPAD_BUTTON_2  = TU_BIT(2),
+  GAMEPAD_BUTTON_3  = TU_BIT(3),
+  GAMEPAD_BUTTON_4  = TU_BIT(4),
+  GAMEPAD_BUTTON_5  = TU_BIT(5),
+  GAMEPAD_BUTTON_6  = TU_BIT(6),
+  GAMEPAD_BUTTON_7  = TU_BIT(7),
+  GAMEPAD_BUTTON_8  = TU_BIT(8),
+  GAMEPAD_BUTTON_9  = TU_BIT(9),
+  GAMEPAD_BUTTON_10 = TU_BIT(10),
+  GAMEPAD_BUTTON_11 = TU_BIT(11),
+  GAMEPAD_BUTTON_12 = TU_BIT(12),
+  GAMEPAD_BUTTON_13 = TU_BIT(13),
+  GAMEPAD_BUTTON_14 = TU_BIT(14),
+  GAMEPAD_BUTTON_15 = TU_BIT(15),
+  GAMEPAD_BUTTON_16 = TU_BIT(16),
+  GAMEPAD_BUTTON_17 = TU_BIT(17),
+  GAMEPAD_BUTTON_18 = TU_BIT(18),
+  GAMEPAD_BUTTON_19 = TU_BIT(19),
+  GAMEPAD_BUTTON_20 = TU_BIT(20),
+  GAMEPAD_BUTTON_21 = TU_BIT(21),
+  GAMEPAD_BUTTON_22 = TU_BIT(22),
+  GAMEPAD_BUTTON_23 = TU_BIT(23),
+  GAMEPAD_BUTTON_24 = TU_BIT(24),
+  GAMEPAD_BUTTON_25 = TU_BIT(25),
+  GAMEPAD_BUTTON_26 = TU_BIT(26),
+  GAMEPAD_BUTTON_27 = TU_BIT(27),
+  GAMEPAD_BUTTON_28 = TU_BIT(28),
+  GAMEPAD_BUTTON_29 = TU_BIT(29),
+  GAMEPAD_BUTTON_30 = TU_BIT(30),
+  GAMEPAD_BUTTON_31 = TU_BIT(31),
 }hid_gamepad_button_bm_t;
 
+/// Standard Gamepad Buttons Naming from Linux input event codes
+/// https://github.com/torvalds/linux/blob/master/include/uapi/linux/input-event-codes.h
+#define GAMEPAD_BUTTON_A       GAMEPAD_BUTTON_0
+#define GAMEPAD_BUTTON_SOUTH   GAMEPAD_BUTTON_0
+
+#define GAMEPAD_BUTTON_B       GAMEPAD_BUTTON_1
+#define GAMEPAD_BUTTON_EAST    GAMEPAD_BUTTON_1
+
+#define GAMEPAD_BUTTON_C       GAMEPAD_BUTTON_2
+
+#define GAMEPAD_BUTTON_X       GAMEPAD_BUTTON_3
+#define GAMEPAD_BUTTON_NORTH   GAMEPAD_BUTTON_3
+
+#define GAMEPAD_BUTTON_Y       GAMEPAD_BUTTON_4
+#define GAMEPAD_BUTTON_WEST    GAMEPAD_BUTTON_4
+
+#define GAMEPAD_BUTTON_Z       GAMEPAD_BUTTON_5
+#define GAMEPAD_BUTTON_TL      GAMEPAD_BUTTON_6
+#define GAMEPAD_BUTTON_TR      GAMEPAD_BUTTON_7
+#define GAMEPAD_BUTTON_TL2     GAMEPAD_BUTTON_8
+#define GAMEPAD_BUTTON_TR2     GAMEPAD_BUTTON_9
+#define GAMEPAD_BUTTON_SELECT  GAMEPAD_BUTTON_10
+#define GAMEPAD_BUTTON_START   GAMEPAD_BUTTON_11
+#define GAMEPAD_BUTTON_MODE    GAMEPAD_BUTTON_12
+#define GAMEPAD_BUTTON_THUMBL  GAMEPAD_BUTTON_13
+#define GAMEPAD_BUTTON_THUMBR  GAMEPAD_BUTTON_14
+
 /// Standard Gamepad HAT/DPAD Buttons (from Linux input event codes)
 typedef enum
 {

From 14fc0987ac9d712fc933899572ed1dc02fd0ddcd Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Thu, 10 Jun 2021 11:03:58 +0700
Subject: [PATCH 0034/2085] Update bug_report.md

---
 .github/ISSUE_TEMPLATE/bug_report.md | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md
index 00d16bc2b..3beef45d0 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@@ -9,7 +9,7 @@ assignees: ''
 
 **Set Up**
 
-- **PC OS** e.g Ubuntu 20.04 / Windows 10/ macOS 10.15
+- **PC OS** e.g Ubuntu 20.04 / Windows 10 / macOS 10.15
 - **Board** e.g Feather nRF52840 Express (if custom specify your MCUs)
 - **TinyUSB version** relase version or git hash (preferrably running with master for lastest code) 
 - **Firmware** e.g examples/device/cdc_msc
@@ -31,6 +31,5 @@ If applicable, add screenshots, bus capture to help explain your problem.
 
 **Log**
 
-If applicable, provide the stack's log (uart/rtt/swo) where the issue occurred, best with comments to explain the actual events. If the log is too long, attach it as txt file instead.
-
+If applicable, provide the stack's log (uart/rtt/swo) where the issue occurred as attached txt file, best with comments to explain the actual events.
 Note: To enable logging, add `LOG=2` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=2` in your tusb_config.h. More information can be found at [example's readme](/docs/getting_started.md)

From 13cb0160421a6a66429e99ed103afba4f1c345ce Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Jun 2021 16:48:20 +0700
Subject: [PATCH 0035/2085] add usbh_classdriver.h

---
 src/class/cdc/cdc_host.c    |  2 +
 src/class/hid/hid_host.c    |  2 +
 src/class/msc/msc_host.c    |  2 +
 src/device/usbd_pvt.h       |  2 +-
 src/host/hub.c              |  1 +
 src/host/usbh.c             |  7 ++--
 src/host/usbh.h             | 43 +--------------------
 src/host/usbh_classdriver.h | 76 +++++++++++++++++++++++++++++++++++++
 src/host/usbh_hcd.h         |  6 ---
 9 files changed, 89 insertions(+), 52 deletions(-)
 create mode 100644 src/host/usbh_classdriver.h

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index facf86d56..dbe5341e9 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -29,6 +29,8 @@
 #if (TUSB_OPT_HOST_ENABLED && CFG_TUH_CDC)
 
 #include "host/usbh.h"
+#include "host/usbh_classdriver.h"
+
 #include "cdc_host.h"
 
 //--------------------------------------------------------------------+
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 83f3f3039..ec50f55f9 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -29,6 +29,8 @@
 #if (TUSB_OPT_HOST_ENABLED && CFG_TUH_HID)
 
 #include "host/usbh.h"
+#include "host/usbh_classdriver.h"
+
 #include "hid_host.h"
 
 //--------------------------------------------------------------------+
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 205f0fd2d..176403e86 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -29,6 +29,8 @@
 #if TUSB_OPT_HOST_ENABLED & CFG_TUH_MSC
 
 #include "host/usbh.h"
+#include "host/usbh_classdriver.h"
+
 #include "msc_host.h"
 
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 65fdadf51..b8d34d7b6 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -34,7 +34,7 @@
 #endif
 
 //--------------------------------------------------------------------+
-// Class Drivers
+// Class Driver API
 //--------------------------------------------------------------------+
 
 typedef struct
diff --git a/src/host/hub.c b/src/host/hub.c
index f921027c7..b2761184d 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -29,6 +29,7 @@
 #if (TUSB_OPT_HOST_ENABLED && CFG_TUH_HUB)
 
 #include "usbh.h"
+#include "usbh_classdriver.h"
 #include "hub.h"
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index ca0653409..ff66d5afd 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "common/tusb_common.h"
+#include "tusb_option.h"
 
 #if TUSB_OPT_HOST_ENABLED
 
@@ -32,10 +32,9 @@
 #define CFG_TUH_TASK_QUEUE_SZ   16
 #endif
 
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
 #include "tusb.h"
+#include "host/usbh.h"
+#include "host/usbh_classdriver.h"
 #include "hub.h"
 #include "usbh_hcd.h"
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index a9790b484..edc9e0808 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -40,27 +40,6 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-typedef enum tusb_interface_status_{
-  TUSB_INTERFACE_STATUS_READY = 0,
-  TUSB_INTERFACE_STATUS_BUSY,
-  TUSB_INTERFACE_STATUS_COMPLETE,
-  TUSB_INTERFACE_STATUS_ERROR,
-  TUSB_INTERFACE_STATUS_INVALID_PARA
-} tusb_interface_status_t;
-
-typedef struct {
-  #if CFG_TUSB_DEBUG >= 2
-  char const* name;
-  #endif
-
-  uint8_t class_code;
-
-  void (* const init       )(void);
-  bool (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t* outlen);
-  bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
-  bool (* const xfer_cb    )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-  void (* const close      )(uint8_t dev_addr);
-} usbh_class_driver_t;
 
 typedef bool (*tuh_control_complete_cb_t)(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 
@@ -101,30 +80,12 @@ bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
 //--------------------------------------------------------------------+
 //TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device);
 
-/** Callback invoked when device is mounted (configured) */
+// Invoked when device is mounted (configured)
 TU_ATTR_WEAK void tuh_mount_cb (uint8_t dev_addr);
 
-/** Callback invoked when device is unmounted (bus reset/unplugged) */
+/// Invoked when device is unmounted (bus reset/unplugged)
 TU_ATTR_WEAK void tuh_umount_cb(uint8_t dev_addr);
 
-//--------------------------------------------------------------------+
-// CLASS-USBH & INTERNAL API
-// TODO move to usbh_pvt.h
-//--------------------------------------------------------------------+
-
-bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
-bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
-
-// Claim an endpoint before submitting a transfer.
-// If caller does not make any transfer, it must release endpoint for others.
-bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
-
-void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num);
-
-uint8_t usbh_get_rhport(uint8_t dev_addr);
-
-uint8_t* usbh_get_enum_buf(void);
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
new file mode 100644
index 000000000..2b1523855
--- /dev/null
+++ b/src/host/usbh_classdriver.h
@@ -0,0 +1,76 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_USBH_CLASSDRIVER_H_
+#define _TUSB_USBH_CLASSDRIVER_H_
+
+#include "osal/osal.h"
+#include "common/tusb_fifo.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Class Driver API
+//--------------------------------------------------------------------+
+
+typedef struct {
+  #if CFG_TUSB_DEBUG >= 2
+  char const* name;
+  #endif
+
+  uint8_t class_code;
+
+  void (* const init       )(void);
+  bool (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t* outlen);
+  bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
+  bool (* const xfer_cb    )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+  void (* const close      )(uint8_t dev_addr);
+} usbh_class_driver_t;
+
+//--------------------------------------------------------------------+
+// USBH Endpoint API
+//--------------------------------------------------------------------+
+
+bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
+bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
+
+// Claim an endpoint before submitting a transfer.
+// If caller does not make any transfer, it must release endpoint for others.
+bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
+
+void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num);
+
+uint8_t usbh_get_rhport(uint8_t dev_addr);
+
+uint8_t* usbh_get_enum_buf(void);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/host/usbh_hcd.h b/src/host/usbh_hcd.h
index abc7fd250..b3856d6b7 100644
--- a/src/host/usbh_hcd.h
+++ b/src/host/usbh_hcd.h
@@ -97,12 +97,6 @@ typedef struct {
 
 extern usbh_device_t _usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1]; // including zero-address
 
-//--------------------------------------------------------------------+
-// callback from HCD ISR
-//--------------------------------------------------------------------+
-
-
-
 #ifdef __cplusplus
  }
 #endif

From 7e6cba7359dd362548026578dd48fe1f26312db3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Jun 2021 16:55:12 +0700
Subject: [PATCH 0036/2085] remove hcd_edpt_stalled()

---
 src/host/hcd.h                               | 1 -
 src/host/usbh.h                              | 7 +------
 src/portable/ehci/ehci.c                     | 6 ------
 src/portable/ohci/ohci.c                     | 6 ------
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 6 ------
 5 files changed, 1 insertion(+), 25 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 46209dc45..8cb5b3772 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -139,7 +139,6 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
 
 bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
-bool hcd_edpt_stalled(uint8_t dev_addr, uint8_t ep_addr);
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.h b/src/host/usbh.h
index edc9e0808..4de6e7ba6 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -24,9 +24,6 @@
  * This file is part of the TinyUSB stack.
  */
 
-/** \ingroup group_usbh USB Host Core (USBH)
- *  @{ */
-
 #ifndef _TUSB_USBH_H_
 #define _TUSB_USBH_H_
 
@@ -90,6 +87,4 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t dev_addr);
  }
 #endif
 
-#endif /* _TUSB_USBH_H_ */
-
-/** @} */
+#endif
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index bcba360bb..be3030676 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -446,12 +446,6 @@ bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
   return !p_qhd->qtd_overlay.halted && (p_qhd->p_qtd_list_head != NULL);
 }
 
-bool hcd_edpt_stalled(uint8_t dev_addr, uint8_t ep_addr)
-{
-  ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
-  return p_qhd->qtd_overlay.halted && !qhd_has_xact_error(p_qhd);
-}
-
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
   ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index dbd2cc793..cbb72c726 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -495,12 +495,6 @@ bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
   return tu_align16(p_ed->td_head.address) != tu_align16(p_ed->td_tail);
 }
 
-bool hcd_edpt_stalled(uint8_t dev_addr, uint8_t ep_addr)
-{
-  ohci_ed_t const * const p_ed = ed_from_addr(dev_addr, ep_addr);
-  return p_ed->td_head.halted && p_ed->is_stalled;
-}
-
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
   ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr);
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 3c62b5732..aeee93324 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -529,12 +529,6 @@ bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
     return busy;
 }
 
-bool hcd_edpt_stalled(uint8_t dev_addr, uint8_t ep_addr)
-{
-    panic("hcd_pipe_stalled");
-    return false;
-}
-
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
     panic("hcd_clear_stall");

From c7f51cde40afbefe3f1d57b9dbdaaca0abed424e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Jun 2021 17:19:21 +0700
Subject: [PATCH 0037/2085] implement usbh_edpt_busy (WIP), remove
 hcd_edpt_busy

---
 src/class/cdc/cdc_host.c                     | 10 ++---
 src/class/hid/hid_host.c                     |  2 +-
 src/class/msc/msc_host.c                     |  2 +-
 src/device/dcd.h                             |  2 +-
 src/device/usbd.c                            |  4 +-
 src/host/hcd.h                               |  2 -
 src/host/usbh.c                              | 46 ++++++++++++++++++--
 src/host/usbh_classdriver.h                  | 29 +++++++-----
 src/portable/ehci/ehci.c                     |  6 ---
 src/portable/ohci/ohci.c                     |  6 ---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 26 +++++------
 11 files changed, 84 insertions(+), 51 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index dbe5341e9..33f1a8ad3 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -73,13 +73,13 @@ bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid)
   switch (pipeid)
   {
     case CDC_PIPE_NOTIFICATION:
-      return hcd_edpt_busy(dev_addr, p_cdc->ep_notif );
+      return usbh_edpt_busy(dev_addr, p_cdc->ep_notif );
 
     case CDC_PIPE_DATA_IN:
-      return hcd_edpt_busy(dev_addr, p_cdc->ep_in );
+      return usbh_edpt_busy(dev_addr, p_cdc->ep_in );
 
     case CDC_PIPE_DATA_OUT:
-      return hcd_edpt_busy(dev_addr, p_cdc->ep_out );
+      return usbh_edpt_busy(dev_addr, p_cdc->ep_out );
 
     default:
       return false;
@@ -103,7 +103,7 @@ bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool i
   TU_VERIFY( p_data != NULL && length, TUSB_ERROR_INVALID_PARA);
 
   uint8_t const ep_out = cdch_data[dev_addr-1].ep_out;
-  if ( hcd_edpt_busy(dev_addr, ep_out) ) return false;
+  if ( usbh_edpt_busy(dev_addr, ep_out) ) return false;
 
   return usbh_edpt_xfer(dev_addr, ep_out, (void *) p_data, length);
 }
@@ -115,7 +115,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
   TU_VERIFY( p_buffer != NULL && length, TUSB_ERROR_INVALID_PARA);
 
   uint8_t const ep_in = cdch_data[dev_addr-1].ep_in;
-  if ( hcd_edpt_busy(dev_addr, ep_in) ) return false;
+  if ( usbh_edpt_busy(dev_addr, ep_in) ) return false;
 
   return usbh_edpt_xfer(dev_addr, ep_in, p_buffer, length);
 }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index ec50f55f9..cde5e23a5 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -201,7 +201,7 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
 //  TU_VERIFY(tuh_n_hid_n_mounted(dev_addr, instance));
 //
 //  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-//  return !hcd_edpt_busy(dev_addr, hid_itf->ep_in);
+//  return !usbh_edpt_busy(dev_addr, hid_itf->ep_in);
 //}
 
 //void tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len);
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 176403e86..7f98ef9b1 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -111,7 +111,7 @@ bool tuh_msc_mounted(uint8_t dev_addr)
 bool tuh_msc_ready(uint8_t dev_addr)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
-  return p_msc->mounted && !hcd_edpt_busy(dev_addr, p_msc->ep_in);
+  return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/device/dcd.h b/src/device/dcd.h
index e17c62d4e..63e97df96 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -122,7 +122,7 @@ void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK;
 void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) TU_ATTR_WEAK;
 
 // Configure endpoint's registers according to descriptor
-bool dcd_edpt_open            (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
+bool dcd_edpt_open            (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
 
 // Close an endpoint.
 // Since it is weak, caller must TU_ASSERT this function's existence before calling it.
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 71c5d4e6c..2935defd0 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1248,8 +1248,8 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
 
-  // Set busy first since the actual transfer can be complete before dcd_edpt_xfer() could return
-  // and usbd task can preempt and clear the busy
+  // Set busy first since the actual transfer can be complete before dcd_edpt_xfer()
+  // could return and USBD task can preempt and clear the busy
   _usbd_dev.ep_status[epnum][dir].busy = true;
 
   if ( dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes) )
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 8cb5b3772..7a9aadc73 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -137,8 +137,6 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
-
-bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index ff66d5afd..59246a663 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -314,8 +314,11 @@ uint8_t* usbh_get_enum_buf(void)
   return _usbh_ctrl_buf;
 }
 
-//------------- Endpoint API -------------//
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
 
+// TODO has some duplication code with device, refactor later
 bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
 {
   uint8_t const epnum = tu_edpt_number(ep_addr);
@@ -343,6 +346,7 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
   return ret;
 }
 
+// TODO has some duplication code with device, refactor later
 bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
 {
   uint8_t const epnum = tu_edpt_number(ep_addr);
@@ -368,11 +372,36 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
   return ret;
 }
 
+// TODO has some duplication code with device, refactor later
 bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
   usbh_device_t* dev = &_usbh_devices[dev_addr];
-  TU_LOG2("  Queue EP %02X with %u bytes ... OK\r\n", ep_addr, total_bytes);
-  return hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes);
+
+  TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
+
+  // Attempt to transfer on a busy endpoint, sound like an race condition !
+  TU_ASSERT(dev->ep_status[epnum][dir].busy == 0);
+
+  // Set busy first since the actual transfer can be complete before hcd_edpt_xfer()
+  // could return and USBH task can preempt and clear the busy
+  dev->ep_status[epnum][dir].busy = true;
+
+  if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
+  {
+    TU_LOG2("OK\r\n");
+    return true;
+  }else
+  {
+    // HCD error, mark endpoint as ready to allow next transfer
+    dev->ep_status[epnum][dir].busy = false;
+    dev->ep_status[epnum][dir].claimed = 0;
+    TU_LOG2("failed\r\n");
+    TU_BREAKPOINT();
+    return false;
+  }
 }
 
 bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
@@ -419,6 +448,17 @@ bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   return ret;
 }
 
+bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  usbh_device_t* dev = &_usbh_devices[dev_addr];
+
+  return dev->ep_status[epnum][dir].busy;
+}
+
+
 //--------------------------------------------------------------------+
 // HCD Event Handler
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index 2b1523855..07480fe8e 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -52,23 +52,30 @@ typedef struct {
   void (* const close      )(uint8_t dev_addr);
 } usbh_class_driver_t;
 
-//--------------------------------------------------------------------+
-// USBH Endpoint API
-//--------------------------------------------------------------------+
-
-bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
-bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
-
-// Claim an endpoint before submitting a transfer.
-// If caller does not make any transfer, it must release endpoint for others.
-bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
-
+// Call by class driver to tell USBH that it has complete the enumeration
 void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num);
 
 uint8_t usbh_get_rhport(uint8_t dev_addr);
 
 uint8_t* usbh_get_enum_buf(void);
 
+//--------------------------------------------------------------------+
+// USBH Endpoint API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
+
+// Submit a usb transfer
+bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
+
+// Claim an endpoint before submitting a transfer.
+// If caller does not make any transfer, it must release endpoint for others.
+bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
+
+// Check if endpoint transferring is complete
+bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index be3030676..48788ba06 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -440,12 +440,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   return true;
 }
 
-bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
-{
-  ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
-  return !p_qhd->qtd_overlay.halted && (p_qhd->p_qtd_list_head != NULL);
-}
-
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
   ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index cbb72c726..73489c764 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -489,12 +489,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   return true;
 }
 
-bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
-{
-  ohci_ed_t const * const p_ed = ed_from_addr(dev_addr, ep_addr);
-  return tu_align16(p_ed->td_head.address) != tu_align16(p_ed->td_tail);
-}
-
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
   ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr);
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index aeee93324..b575c6afc 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -515,19 +515,19 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
     return true;
 }
 
-bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
-{
-    // EPX is shared, so multiple device addresses and endpoint addresses share that
-    // so if any transfer is active on epx, we are busy. Interrupt endpoints have their own
-    // EPX so ep->active will only be busy if there is a pending transfer on that interrupt endpoint
-    // on that device
-    pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\n", dev_addr, ep_addr);
-    struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
-    assert(ep);
-    bool busy = ep->active;
-    pico_trace("busy == %d\n", busy);
-    return busy;
-}
+//bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
+//{
+//    // EPX is shared, so multiple device addresses and endpoint addresses share that
+//    // so if any transfer is active on epx, we are busy. Interrupt endpoints have their own
+//    // EPX so ep->active will only be busy if there is a pending transfer on that interrupt endpoint
+//    // on that device
+//    pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\n", dev_addr, ep_addr);
+//    struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
+//    assert(ep);
+//    bool busy = ep->active;
+//    pico_trace("busy == %d\n", busy);
+//    return busy;
+//}
 
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {

From c9d66dcd5f82b138865bbb02486fe19e4a843eb2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Jun 2021 17:24:36 +0700
Subject: [PATCH 0038/2085] remove BOARD from output name

---
 examples/make.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/make.mk b/examples/make.mk
index df8bfd617..9daf60e35 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -5,7 +5,7 @@
 # Build directory
 BUILD := _build/$(BOARD)
 
-PROJECT := $(BOARD)-$(notdir $(CURDIR))
+PROJECT := $(notdir $(CURDIR))
 BIN := $(TOP)/_bin/$(BOARD)/$(notdir $(CURDIR))
 
 # Handy check parameter function

From cf0a475a2e501f21638369eca6ceb090ef47bd51 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Jun 2021 22:00:59 +0700
Subject: [PATCH 0039/2085] clean up

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 101 ++++++++++---------
 1 file changed, 56 insertions(+), 45 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index b575c6afc..7042160ec 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -52,22 +52,23 @@
 static_assert(PICO_USB_HOST_INTERRUPT_ENDPOINTS <= USB_MAX_ENDPOINTS, "");
 
 // Host mode uses one shared endpoint register for non-interrupt endpoint
-struct hw_endpoint eps[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
-#define epx (eps[0])
+static struct hw_endpoint ep_pool[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
+#define epx (ep_pool[0])
 
-#define usb_hw_set hw_set_alias(usb_hw)
+#define usb_hw_set   hw_set_alias(usb_hw)
 #define usb_hw_clear hw_clear_alias(usb_hw)
 
-// Used for hcd pipe busy.
 // todo still a bit wasteful
 // top bit set if valid
 uint8_t dev_ep_map[CFG_TUSB_HOST_DEVICE_MAX][1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS][2];
 
 // Flags we set by default in sie_ctrl (we add other bits on top)
-static uint32_t sie_ctrl_base = USB_SIE_CTRL_SOF_EN_BITS | 
-                                USB_SIE_CTRL_KEEP_ALIVE_EN_BITS | 
-                                USB_SIE_CTRL_PULLDOWN_EN_BITS | 
-                                USB_SIE_CTRL_EP0_INT_1BUF_BITS;
+enum {
+  sie_ctrl_base = USB_SIE_CTRL_SOF_EN_BITS        |
+                  USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
+                  USB_SIE_CTRL_PULLDOWN_EN_BITS   |
+                  USB_SIE_CTRL_EP0_INT_1BUF_BITS
+};
 
 static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
 {
@@ -78,19 +79,22 @@ static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
     uint8_t in = (ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0;
     uint mapping = dev_ep_map[dev_addr-1][num][in];
     pico_trace("Get dev addr %d ep %d = %d\n", dev_addr, ep_addr, mapping);
-    return mapping >= 128 ? eps + (mapping & 0x7fu) : NULL;
+    return mapping >= 128 ? ep_pool + (mapping & 0x7fu) : NULL;
 }
 
 static void set_dev_ep(uint8_t dev_addr, uint8_t ep_addr, struct hw_endpoint *ep)
 {
     uint8_t num = tu_edpt_number(ep_addr);
-    uint8_t in = (ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0;
-    uint32_t index = ep - eps;
-    hard_assert(index < TU_ARRAY_SIZE(eps));
+    uint8_t in = (uint8_t) tu_edpt_dir(ep_addr);
+
+    uint32_t index = ep - ep_pool;
+    hard_assert(index < TU_ARRAY_SIZE(ep_pool));
+
     // todo revisit why dev_addr can be 0 here
     if (dev_addr) {
         dev_ep_map[dev_addr-1][num][in] = 128u | index;
     }
+
     pico_trace("Set dev addr %d ep %d = %d\n", dev_addr, ep_addr, index);
 }
 
@@ -153,7 +157,7 @@ static void hw_handle_buff_status(void)
         if (remaining_buffers & bit)
         {
             remaining_buffers &= ~bit;
-            _handle_buff_status_bit(bit, &eps[i]);
+            _handle_buff_status_bit(bit, &ep_pool[i]);
         }
     }
 
@@ -206,13 +210,15 @@ static void hcd_rp2040_irq(void)
     {
         handled |= USB_INTS_TRANS_COMPLETE_BITS;
         usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
+        TU_LOG(2, "Transfer complete\n");
         hw_trans_complete();
     }
 
     if (status & USB_INTS_BUFF_STATUS_BITS)
     {
         handled |= USB_INTS_BUFF_STATUS_BITS;
-        // print_bufctrl32(*epx.buffer_control);
+        TU_LOG(2, "Buffer complete\n");
+        print_bufctrl32(*epx.buffer_control);
         hw_handle_buff_status();
     }
 
@@ -234,7 +240,7 @@ static void hcd_rp2040_irq(void)
     if (status & USB_INTS_ERROR_DATA_SEQ_BITS)
     {
         usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
-        // print_bufctrl32(*epx.buffer_control);
+        print_bufctrl32(*epx.buffer_control);
         panic("Data Seq Error \n");
     }
 
@@ -247,9 +253,9 @@ static void hcd_rp2040_irq(void)
 static struct hw_endpoint *_next_free_interrupt_ep(void)
 {
     struct hw_endpoint *ep = NULL;
-    for (uint i = 1; i < TU_ARRAY_SIZE(eps); i++)
+    for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++)
     {
-        ep = &eps[i];
+        ep = &ep_pool[i];
         if (!ep->configured)
         {
             // Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
@@ -263,6 +269,7 @@ static struct hw_endpoint *_next_free_interrupt_ep(void)
 static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
 {
     struct hw_endpoint *ep = NULL;
+
     if (transfer_type == TUSB_XFER_INTERRUPT)
     {
         ep = _next_free_interrupt_ep();
@@ -283,6 +290,7 @@ static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
         ep->endpoint_control = &usbh_dpram->epx_ctrl;
         ep->hw_data_buf = &usbh_dpram->epx_data[0];
     }
+
     return ep;
 }
 
@@ -345,24 +353,9 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
 
         // If it's an interrupt endpoint we need to set up the buffer control
         // register
-
     }
 }
 
-static void hw_endpoint_init(uint8_t dev_addr, const tusb_desc_endpoint_t *ep_desc)
-{
-    // Allocated differently based on if it's an interrupt endpoint or not
-    struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
-    _hw_endpoint_init(ep,
-        dev_addr,
-        ep_desc->bEndpointAddress,
-        ep_desc->wMaxPacketSize.size,
-        ep_desc->bmAttributes.xfer,
-        ep_desc->bInterval);
-    // Map this struct to ep@device address
-    set_dev_ep(dev_addr, ep_desc->bEndpointAddress, ep);
-}
-
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
@@ -377,7 +370,7 @@ bool hcd_init(uint8_t rhport)
     irq_set_exclusive_handler(USBCTRL_IRQ, hcd_rp2040_irq);
 
     // clear epx and interrupt eps
-    memset(&eps, 0, sizeof(eps));
+    memset(&ep_pool, 0, sizeof(ep_pool));
 
     // Enable in host mode with SOF / Keep alive on
     usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS | USB_MAIN_CTRL_HOST_NDEVICE_BITS;
@@ -420,6 +413,7 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
             return TUSB_SPEED_FULL;
         default:
             panic("Invalid speed\n");
+            return TUSB_SPEED_INVALID;
     }
 }
 
@@ -444,7 +438,7 @@ void hcd_int_disable(uint8_t rhport)
 
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
-    pico_info("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
+    pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
     
     // Get appropriate ep. Either EPX or interrupt endpoint
     struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
@@ -452,13 +446,12 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
     if (ep_addr != ep->ep_addr)
     {
-        // Direction has flipped so re init it but with same properties
-        // TODO treat IN and OUT as invidual endpoints
+        // Direction has flipped on endpoint control so re init it but with same properties
         _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
     }
 
     // True indicates this is the start of the transfer
-    _hw_endpoint_xfer(ep, buffer, buflen, true);
+    _hw_endpoint_xfer_start(ep, buffer, buflen);
 
     // If a normal transfer (non-interrupt) then initiate using
     // sie ctrl registers. Otherwise interrupt ep registers should
@@ -479,27 +472,30 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
-    pico_info("hcd_setup_send dev_addr %d\n", dev_addr);
-    
     // Copy data into setup packet buffer
     memcpy((void*)&usbh_dpram->setup_packet[0], setup_packet, 8);
 
     // Configure EP0 struct with setup info for the trans complete
     struct hw_endpoint *ep = _hw_endpoint_allocate(0);
+
     // EP0 out
     _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
     assert(ep->configured);
-    ep->total_len = 8;
+
+    ep->total_len     = 8;
     ep->transfer_size = 8;
-    ep->active = true;
-    ep->sent_setup = true;
+    ep->active        = true;
+    ep->sent_setup    = true;
 
     // Set device address
     usb_hw->dev_addr_ctrl = dev_addr;
+
     // Set pre if we are a low speed device on full speed hub
-    uint32_t flags = sie_ctrl_base | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS;
-    flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
+    uint32_t const flags = sie_ctrl_base | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
+                           (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
+
     usb_hw->sie_ctrl = flags;
+
     return true;
 }
 
@@ -510,8 +506,23 @@ uint32_t hcd_frame_number(uint8_t rhport)
 
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
+    (void) rhport;
+
     pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
-    hw_endpoint_init(dev_addr, ep_desc);
+
+    // Allocated differently based on if it's an interrupt endpoint or not
+    struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
+
+    _hw_endpoint_init(ep,
+        dev_addr,
+        ep_desc->bEndpointAddress,
+        ep_desc->wMaxPacketSize.size,
+        ep_desc->bmAttributes.xfer,
+        ep_desc->bInterval);
+
+    // Map this struct to ep@device address
+    set_dev_ep(dev_addr, ep_desc->bEndpointAddress, ep);
+
     return true;
 }
 

From fd7b18a4f6417c214b2b8880b3a640c39f587019 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Thu, 10 Jun 2021 10:11:20 -0500
Subject: [PATCH 0040/2085] Make examples standalone buildable via CMake

---
 examples/device/CMakeLists.txt                |  2 +-
 .../device/audio_4_channel_mic/CMakeLists.txt |  2 +-
 examples/device/audio_test/CMakeLists.txt     |  2 +-
 examples/device/board_test/CMakeLists.txt     |  3 +-
 examples/device/cdc_dual_ports/CMakeLists.txt |  2 +-
 examples/device/cdc_msc/CMakeLists.txt        |  2 +-
 .../device/cdc_msc_freertos/CMakeLists.txt    | 19 +++--
 examples/device/dfu/CMakeLists.txt            |  2 +-
 examples/device/dfu_runtime/CMakeLists.txt    |  2 +-
 .../dynamic_configuration/CMakeLists.txt      |  2 +-
 examples/device/hid_composite/CMakeLists.txt  |  2 +-
 .../device/hid_generic_inout/CMakeLists.txt   |  2 +-
 .../hid_multiple_interface/CMakeLists.txt     |  2 +-
 examples/device/midi_test/CMakeLists.txt      |  2 +-
 examples/device/msc_dual_lun/CMakeLists.txt   |  2 +-
 .../device/net_lwip_webserver/CMakeLists.txt  |  2 +-
 examples/device/uac2_headset/CMakeLists.txt   |  2 +-
 examples/device/usbtmc/CMakeLists.txt         |  2 +-
 examples/device/webusb_serial/CMakeLists.txt  |  2 +-
 examples/host/CMakeLists.txt                  |  2 +-
 examples/host/cdc_msc_hid/CMakeLists.txt      |  2 +-
 hw/bsp/esp32s2/family.cmake                   |  3 -
 hw/bsp/esp32s3/family.cmake                   |  3 -
 hw/bsp/family_common.cmake                    | 57 ---------------
 hw/bsp/family_support.cmake                   | 71 +++++++++++++++++++
 hw/bsp/rp2040/family.cmake                    |  4 +-
 26 files changed, 101 insertions(+), 97 deletions(-)
 delete mode 100644 hw/bsp/family_common.cmake
 create mode 100644 hw/bsp/family_support.cmake

diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index 4ed693cde..a0e4600f6 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
 
 project(tinyusb_device_examples)
 family_initialize_project(tinyusb_device_examples ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/audio_4_channel_mic/CMakeLists.txt b/examples/device/audio_4_channel_mic/CMakeLists.txt
index b653fc91f..f6e10e2ea 100644
--- a/examples/device/audio_4_channel_mic/CMakeLists.txt
+++ b/examples/device/audio_4_channel_mic/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt
index fac0ca64f..cb321f9a8 100644
--- a/examples/device/audio_test/CMakeLists.txt
+++ b/examples/device/audio_test/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index 8cd5b9ea4..37113578e 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # Check for -DFAMILY=
 if(FAMILY MATCHES "^esp32s[2-3]")
@@ -12,7 +12,6 @@ if(FAMILY MATCHES "^esp32s[2-3]")
   set(TOP "../../..")
   get_filename_component(TOP "${TOP}" REALPATH)
 
-  include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
   project(${PROJECT})
 
 else()
diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt
index 18367a893..abc4d91da 100644
--- a/examples/device/cdc_dual_ports/CMakeLists.txt
+++ b/examples/device/cdc_dual_ports/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index 5da761a04..fa6e83b7e 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 1d04a8518..11f1c6135 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -1,20 +1,17 @@
 cmake_minimum_required(VERSION 3.5)
 
-# use BOARD-Directory name for project id
-get_filename_component(PROJECT ${CMAKE_CURRENT_SOURCE_DIR} NAME)
-set(PROJECT ${BOARD}-${PROJECT})
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
-# TOP is absolute path to root directory of TinyUSB git repo
-set(TOP "../../..")
-get_filename_component(TOP "${TOP}" REALPATH)
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
 # Check for -DFAMILY=
 if(FAMILY MATCHES "^esp32s[2-3]")
-  cmake_minimum_required(VERSION 3.5)
-
-  include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
-  project(${PROJECT})
-
 else()
   message(FATAL_ERROR "Invalid FAMILY specified: ${FAMILY}")
 endif()
diff --git a/examples/device/dfu/CMakeLists.txt b/examples/device/dfu/CMakeLists.txt
index 18367a893..abc4d91da 100644
--- a/examples/device/dfu/CMakeLists.txt
+++ b/examples/device/dfu/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt
index 18367a893..abc4d91da 100644
--- a/examples/device/dfu_runtime/CMakeLists.txt
+++ b/examples/device/dfu_runtime/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt
index 5da761a04..fa6e83b7e 100644
--- a/examples/device/dynamic_configuration/CMakeLists.txt
+++ b/examples/device/dynamic_configuration/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt
index 18367a893..abc4d91da 100644
--- a/examples/device/hid_composite/CMakeLists.txt
+++ b/examples/device/hid_composite/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt
index 18367a893..abc4d91da 100644
--- a/examples/device/hid_generic_inout/CMakeLists.txt
+++ b/examples/device/hid_generic_inout/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt
index 18367a893..abc4d91da 100644
--- a/examples/device/hid_multiple_interface/CMakeLists.txt
+++ b/examples/device/hid_multiple_interface/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt
index 18367a893..abc4d91da 100644
--- a/examples/device/midi_test/CMakeLists.txt
+++ b/examples/device/midi_test/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt
index f60be8eda..9e834ae21 100644
--- a/examples/device/msc_dual_lun/CMakeLists.txt
+++ b/examples/device/msc_dual_lun/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index f1f79b2d1..7500f6e9e 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -4,7 +4,7 @@ set(TOP "../../..")
 get_filename_component(TOP "${TOP}" REALPATH)
 
 if (EXISTS ${TOP}/lib/lwip/src)
-    include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
+    include(${TOP}/hw/bsp/family_support.cmake)
 
     # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
     family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt
index 18367a893..abc4d91da 100644
--- a/examples/device/uac2_headset/CMakeLists.txt
+++ b/examples/device/uac2_headset/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt
index 4306da8cb..c49603c26 100644
--- a/examples/device/usbtmc/CMakeLists.txt
+++ b/examples/device/usbtmc/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt
index 18367a893..abc4d91da 100644
--- a/examples/device/webusb_serial/CMakeLists.txt
+++ b/examples/device/webusb_serial/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt
index c70d11d5b..f185ac4f8 100644
--- a/examples/host/CMakeLists.txt
+++ b/examples/host/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
 
 project(tinyusb_host_examples)
 family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index ad0f412e2..0a99bc3a9 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/${FAMILY}/family.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
diff --git a/hw/bsp/esp32s2/family.cmake b/hw/bsp/esp32s2/family.cmake
index 9eb1627a1..f3d41d041 100644
--- a/hw/bsp/esp32s2/family.cmake
+++ b/hw/bsp/esp32s2/family.cmake
@@ -4,7 +4,4 @@ cmake_minimum_required(VERSION 3.5)
 set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2/boards" "${TOP}/hw/bsp/esp32s2/components")  
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 set(SUPPORTED_TARGETS esp32s2)
-
-# include basic family CMake functionality
 set(FAMILY_MCUS ESP32S2)
-include(${CMAKE_CURRENT_LIST_DIR}/../family_common.cmake)
diff --git a/hw/bsp/esp32s3/family.cmake b/hw/bsp/esp32s3/family.cmake
index c99c3728b..511dd58bb 100644
--- a/hw/bsp/esp32s3/family.cmake
+++ b/hw/bsp/esp32s3/family.cmake
@@ -4,7 +4,4 @@ cmake_minimum_required(VERSION 3.5)
 set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s3/boards" "${TOP}/hw/bsp/esp32s3/components")  
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 set(SUPPORTED_TARGETS esp32s3)
-
-# include basic family CMake functionality
 set(FAMILY_MCUS ESP32S3)
-include(${CMAKE_CURRENT_LIST_DIR}/../family_common.cmake)
diff --git a/hw/bsp/family_common.cmake b/hw/bsp/family_common.cmake
deleted file mode 100644
index 2544c58c6..000000000
--- a/hw/bsp/family_common.cmake
+++ /dev/null
@@ -1,57 +0,0 @@
-if (NOT FAMILY_MCUS)
-    set(FAMILY_MCUS ${FAMILY})
-endif()
-
-# save it in case of re-inclusion
-set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
-
-function(family_filter RESULT DIR)
-    get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
-    file(GLOB ONLYS "${DIR}/.only.MCU_*")
-    if (ONLYS)
-        foreach(MCU IN LISTS FAMILY_MCUS)
-            if (EXISTS ${DIR}/.only.MCU_${MCU})
-                set(${RESULT} 1 PARENT_SCOPE)
-                return()
-            endif()
-        endforeach()
-    else()
-        foreach(MCU IN LISTS FAMILY_MCUS)
-            if (EXISTS ${DIR}/.skip.MCU_${MCU})
-                set(${RESULT} 0 PARENT_SCOPE)
-                return()
-            endif()
-        endforeach()
-    endif()
-    set(${RESULT} 1 PARENT_SCOPE)
-endfunction()
-
-function(family_add_subdirectory DIR)
-    family_filter(SHOULD_ADD "${DIR}")
-    if (SHOULD_ADD)
-        add_subdirectory(${DIR})
-    endif()
-endfunction()
-
-function(family_get_project_name OUTPUT_NAME DIR)
-    get_filename_component(SHORT_NAME ${DIR} NAME)
-    set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
-endfunction()
-
-function(family_initialize_project PROJECT DIR)
-    family_filter(ALLOWED "${DIR}")
-    if (NOT ALLOWED)
-        get_filename_component(SHORT_NAME ${DIR} NAME)
-        message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
-    endif()
-endfunction()
-
-# configure an executable target to link to tinyusb in device mode, and add the board implementation
-function(family_configure_device_example TARGET)
-    # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
-endfunction()
-
-# configure an executable target to link to tinyusb in host mode, and add the board implementation
-function(family_configure_host_example TARGET)
-    # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
-endfunction()
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
new file mode 100644
index 000000000..af0e00b2d
--- /dev/null
+++ b/hw/bsp/family_support.cmake
@@ -0,0 +1,71 @@
+if (NOT TARGET _family_support_marker)
+    add_library(_family_support_marker INTERFACE)
+
+    if (NOT FAMILY)
+        message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the camke command line")
+    endif()
+
+    if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
+        message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
+    endif()
+
+    function(family_filter RESULT DIR)
+        get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
+        file(GLOB ONLYS "${DIR}/.only.MCU_*")
+        if (ONLYS)
+            foreach(MCU IN LISTS FAMILY_MCUS)
+                if (EXISTS ${DIR}/.only.MCU_${MCU})
+                    set(${RESULT} 1 PARENT_SCOPE)
+                    return()
+                endif()
+            endforeach()
+        else()
+            foreach(MCU IN LISTS FAMILY_MCUS)
+                if (EXISTS ${DIR}/.skip.MCU_${MCU})
+                    set(${RESULT} 0 PARENT_SCOPE)
+                    return()
+                endif()
+            endforeach()
+        endif()
+        set(${RESULT} 1 PARENT_SCOPE)
+    endfunction()
+
+    function(family_add_subdirectory DIR)
+        family_filter(SHOULD_ADD "${DIR}")
+        if (SHOULD_ADD)
+            add_subdirectory(${DIR})
+        endif()
+    endfunction()
+
+    function(family_get_project_name OUTPUT_NAME DIR)
+        get_filename_component(SHORT_NAME ${DIR} NAME)
+        set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
+    endfunction()
+
+    function(family_initialize_project PROJECT DIR)
+        family_filter(ALLOWED "${DIR}")
+        if (NOT ALLOWED)
+            get_filename_component(SHORT_NAME ${DIR} NAME)
+            message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
+        endif()
+    endfunction()
+
+    # configure an executable target to link to tinyusb in device mode, and add the board implementation
+    function(family_configure_device_example TARGET)
+        # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
+    endfunction()
+
+    # configure an executable target to link to tinyusb in host mode, and add the board implementation
+    function(family_configure_host_example TARGET)
+        # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
+    endfunction()
+
+    include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
+
+    if (NOT FAMILY_MCUS)
+        set(FAMILY_MCUS ${FAMILY})
+    endif()
+
+    # save it in case of re-inclusion
+    set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
+endif()
\ No newline at end of file
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 752eb0cab..41960b6cd 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -3,7 +3,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	add_library(_rp2040_family_inclusion_marker INTERFACE)
 
 	if (NOT BOARD)
-		message(FATAL_ERROR "BOARD must be specified")
+		message("BOARD not specified, defaulting to pico_sdk")
+		set(BOARD pico_sdk)
 	endif()
 
 	# add the SDK in case we are standalone tinyusb example (noop if already present)
@@ -11,7 +12,6 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 
 	# include basic family CMake functionality
 	set(FAMILY_MCUS RP2040)
-	include(${CMAKE_CURRENT_LIST_DIR}/../family_common.cmake)
 
 	include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 

From 43656dc0a7a613f8d5f6533d2c68ca9f5824a5f4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Jun 2021 23:29:02 +0700
Subject: [PATCH 0041/2085] more clean up

---
 src/host/usbh_control.c                      |  2 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 77 ++++++++++++--------
 2 files changed, 48 insertions(+), 31 deletions(-)

diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index 4dbf8592a..aa82f14ba 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -68,7 +68,7 @@ bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
   _ctrl_xfer.stage       = STAGE_SETUP;
   _ctrl_xfer.complete_cb = complete_cb;
 
-  TU_LOG2("Control Setup: ");
+  TU_LOG2("Send Setup to address %u: ", dev_addr);
   TU_LOG2_VAR(request);
   TU_LOG2("\r\n");
 
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 7042160ec..d6bcf5b82 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -420,9 +420,18 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 // Close all opened endpoint belong to this device
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 {
+    (void) rhport;
+    (void) dev_addr;
+
     pico_trace("hcd_device_close %d\n", dev_addr);
 }
 
+uint32_t hcd_frame_number(uint8_t rhport)
+{
+    (void) rhport;
+    return usb_hw->sof_rd;
+}
+
 void hcd_int_enable(uint8_t rhport)
 {
     assert(rhport == 0);
@@ -436,10 +445,37 @@ void hcd_int_disable(uint8_t rhport)
     irq_set_enabled(USBCTRL_IRQ, false);
 }
 
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
+{
+    (void) rhport;
+
+    pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
+
+    // Allocated differently based on if it's an interrupt endpoint or not
+    struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
+
+    _hw_endpoint_init(ep,
+        dev_addr,
+        ep_desc->bEndpointAddress,
+        ep_desc->wMaxPacketSize.size,
+        ep_desc->bmAttributes.xfer,
+        ep_desc->bInterval);
+
+    // Map this struct to ep@device address
+    set_dev_ep(dev_addr, ep_desc->bEndpointAddress, ep);
+
+    return true;
+}
+
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
+    (void) rhport;
+
     pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
     
+    uint8_t const ep_num = tu_edpt_number(ep_addr);
+    tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
+
     // Get appropriate ep. Either EPX or interrupt endpoint
     struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
     assert(ep);
@@ -450,7 +486,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
         _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
     }
 
-    // True indicates this is the start of the transfer
+    // Start the transfer
     _hw_endpoint_xfer_start(ep, buffer, buflen);
 
     // If a normal transfer (non-interrupt) then initiate using
@@ -459,11 +495,13 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     if (ep == &epx) {
         // That has set up buffer control, endpoint control etc
         // for host we have to initiate the transfer
-        usb_hw->dev_addr_ctrl = dev_addr | (tu_edpt_number(ep_addr) << USB_ADDR_ENDP_ENDPOINT_LSB);
-        uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | sie_ctrl_base;
-        flags |= ep->rx ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS;
+        usb_hw->dev_addr_ctrl = dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB);
+
+        uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | sie_ctrl_base |
+                         (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS);
         // Set pre if we are a low speed device on full speed hub
         flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
+
         usb_hw->sie_ctrl = flags;
     }
 
@@ -472,6 +510,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
+    (void) rhport;
+
     // Copy data into setup packet buffer
     memcpy((void*)&usbh_dpram->setup_packet[0], setup_packet, 8);
 
@@ -499,32 +539,6 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
     return true;
 }
 
-uint32_t hcd_frame_number(uint8_t rhport)
-{
-    return usb_hw->sof_rd;
-}
-
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
-{
-    (void) rhport;
-
-    pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
-
-    // Allocated differently based on if it's an interrupt endpoint or not
-    struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
-
-    _hw_endpoint_init(ep,
-        dev_addr,
-        ep_desc->bEndpointAddress,
-        ep_desc->wMaxPacketSize.size,
-        ep_desc->bmAttributes.xfer,
-        ep_desc->bInterval);
-
-    // Map this struct to ep@device address
-    set_dev_ep(dev_addr, ep_desc->bEndpointAddress, ep);
-
-    return true;
-}
 
 //bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
 //{
@@ -542,6 +556,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
+    (void) rhport;
+    (void) dev_addr;
+
     panic("hcd_clear_stall");
     return true;
 }

From a1a03c92f66e0c2cae5198341c322182302a1229 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Jun 2021 17:05:49 +0700
Subject: [PATCH 0042/2085] double buffered work with host

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c |  10 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 103 ++++++-
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 267 +++++++++----------
 src/portable/raspberrypi/rp2040/rp2040_usb.h |  15 +-
 4 files changed, 233 insertions(+), 162 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 0048270a6..ccdbb9c01 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -198,10 +198,10 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t b
     _hw_endpoint_init(ep, ep_addr, wMaxPacketSize, bmAttributes);
 }
 
-static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes, bool start)
+static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
     struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
-    _hw_endpoint_xfer(ep, buffer, total_bytes, start);
+    _hw_endpoint_xfer_start(ep, buffer, total_bytes);
 }
 
 static void hw_handle_buff_status(void)
@@ -251,7 +251,7 @@ static void ep0_0len_status(void)
 {
     // Send 0len complete response on EP0 IN
     reset_ep0();
-    hw_endpoint_xfer(0x80, NULL, 0, true);
+    hw_endpoint_xfer(0x80, NULL, 0);
 }
 
 static void _hw_endpoint_stall(struct hw_endpoint *ep)
@@ -477,7 +477,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
         request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
         request->bRequest == TUSB_REQ_SET_ADDRESS)
     {
-        pico_trace("Set HW address %d\n", assigned_address);
+        pico_trace("Set HW address %d\n", request->wValue);
         usb_hw->dev_addr_ctrl = (uint8_t) request->wValue;
     }
 
@@ -496,7 +496,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 {
     assert(rhport == 0);
     // True means start new xfer
-    hw_endpoint_xfer(ep_addr, buffer, total_bytes, true);
+    hw_endpoint_xfer(ep_addr, buffer, total_bytes);
     return true;
 }
 
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index d6bcf5b82..561656a10 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -115,9 +115,9 @@ static void hw_xfer_complete(struct hw_endpoint *ep, xfer_result_t xfer_result)
     // Mark transfer as done before we tell the tinyusb stack
     uint8_t dev_addr = ep->dev_addr;
     uint8_t ep_addr = ep->ep_addr;
-    uint total_len = ep->total_len;
+    uint xferred_len = ep->len;
     hw_endpoint_reset_transfer(ep);
-    hcd_event_xfer_complete(dev_addr, ep_addr, total_len, xfer_result, true);
+    hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
 }
 
 static void _handle_buff_status_bit(uint bit, struct hw_endpoint *ep)
@@ -141,6 +141,20 @@ static void hw_handle_buff_status(void)
     {
         remaining_buffers &= ~bit;
         struct hw_endpoint *ep = &epx;
+
+        uint32_t ep_ctrl = *ep->endpoint_control;
+        if (ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS)
+        {
+          TU_LOG(2, "Double Buffered ");
+        }else
+        {
+          TU_LOG(2, "Single Buffered ");
+        }
+
+        if (ep_ctrl & EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER) TU_LOG(2, "Interrupt per double ");
+        if (ep_ctrl & EP_CTRL_INTERRUPT_PER_BUFFER) TU_LOG(2, "Interrupt per single ");
+        TU_LOG_HEX(2, ep_ctrl);
+
         _handle_buff_status_bit(bit, ep);
     }
 
@@ -277,11 +291,11 @@ static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
         assert(ep);
         ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
         ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
-        // 0x180 for epx
-        // 0x1c0 for intep0
-        // 0x200 for intep1
+        // 0 for epx (double buffered): TODO increase to 1024 for ISO
+        // 2x64 for intep0
+        // 3x64 for intep1
         // etc
-        ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 1)];
+        ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)];
     }
     else
     {
@@ -311,7 +325,7 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
     ep->rx = (dir == TUSB_DIR_IN);
 
     // Response to a setup packet on EP0 starts with pid of 1
-    ep->next_pid = num == 0 ? 1u : 0u;
+    ep->next_pid = (num == 0 ? 1u : 0u);
     ep->wMaxPacketSize = wMaxPacketSize;
     ep->transfer_type = transfer_type;
 
@@ -340,6 +354,7 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
         // preamble
         uint32_t reg = dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB);
         // Assert the interrupt endpoint is IN_TO_HOST
+        // TODO Interrupt can also be OUT
         assert(dir == TUSB_DIR_IN);
 
         if (need_pre(dev_addr))
@@ -402,7 +417,6 @@ bool hcd_port_connect_status(uint8_t rhport)
 
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
-    pico_trace("hcd_port_speed_get\n");
     assert(rhport == 0);
     // TODO: Should enumval this register
     switch (dev_speed())
@@ -445,6 +459,10 @@ void hcd_int_disable(uint8_t rhport)
     irq_set_enabled(USBCTRL_IRQ, false);
 }
 
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
     (void) rhport;
@@ -467,6 +485,65 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
     return true;
 }
 
+// return true if double buffered
+static bool xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len)
+{
+  // Fill in info now that we're kicking off the hw
+  ep->total_len = total_len;
+  ep->len = 0;
+
+  // Limit by packet size
+  ep->user_buf = buffer;
+
+  // Buffer 0
+  ep->transfer_size = tu_min16(total_len, ep->wMaxPacketSize);
+  total_len -= ep->transfer_size;
+
+  // Buffer 1
+  ep->buf_1_len = tu_min16(total_len, ep->wMaxPacketSize);
+  total_len -= ep->buf_1_len;
+
+  ep->active = true;
+
+  // Write buffer control
+
+  // Buffer 0
+  uint32_t bufctrl = ep->transfer_size  | USB_BUF_CTRL_AVAIL;
+
+  // Copy data to DPB if tx
+  if (!ep->rx)
+  {
+    // Copy data from user buffer to hw buffer
+    memcpy(ep->hw_data_buf, ep->user_buf, ep->transfer_size + ep->buf_1_len);
+
+    // Mark as full
+    bufctrl |= USB_BUF_CTRL_FULL | (ep->buf_1_len ? (USB_BUF_CTRL_FULL << 16) : 0);
+  }
+
+  // PID
+  bufctrl |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
+  ep->next_pid ^= 1u;
+
+  if (ep->buf_1_len)
+  {
+    bufctrl |= (ep->buf_1_len | USB_BUF_CTRL_AVAIL) << 16;
+    bufctrl |= (ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID) << 16;
+    ep->next_pid ^= 1u;
+  }
+
+  // determine which buffer is last
+  if (total_len == 0)
+  {
+    bufctrl |= USB_BUF_CTRL_LAST << (ep->buf_1_len ? 16 : 0);
+  }
+
+  print_bufctrl32(bufctrl);
+
+  _hw_endpoint_buffer_control_set_value32(ep, bufctrl);
+
+  return ep->buf_1_len > 0;
+}
+
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
     (void) rhport;
@@ -486,13 +563,12 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
         _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
     }
 
-    // Start the transfer
-    _hw_endpoint_xfer_start(ep, buffer, buflen);
-
     // If a normal transfer (non-interrupt) then initiate using
     // sie ctrl registers. Otherwise interrupt ep registers should
     // already be configured
     if (ep == &epx) {
+        _hw_endpoint_xfer_start(ep, buffer, buflen);
+
         // That has set up buffer control, endpoint control etc
         // for host we have to initiate the transfer
         usb_hw->dev_addr_ctrl = dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB);
@@ -503,6 +579,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
         flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
 
         usb_hw->sie_ctrl = flags;
+    }else
+    {
+      _hw_endpoint_xfer_start(ep, buffer, buflen);
     }
 
     return true;
@@ -556,8 +635,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
-    (void) rhport;
     (void) dev_addr;
+    (void) ep_addr;
 
     panic("hcd_clear_stall");
     return true;
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 31381e6c2..5f61f90c5 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -61,11 +61,11 @@ void rp2040_usb_init(void)
     memset(usb_dpram, 0, sizeof(*usb_dpram));
 
     // Mux the controller to the onboard usb phy
-    usb_hw->muxing    = USB_USB_MUXING_TO_PHY_BITS    | USB_USB_MUXING_SOFTCON_BITS;
+    usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS    | USB_USB_MUXING_SOFTCON_BITS;
 
     // Force VBUS detect so the device thinks it is plugged into a host
     // TODO support VBUs detect
-    usb_hw->pwr       = USB_USB_PWR_VBUS_DETECT_BITS  | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
+    usb_hw->pwr    = USB_USB_PWR_VBUS_DETECT_BITS  | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
 }
 
 void hw_endpoint_reset_transfer(struct hw_endpoint *ep)
@@ -111,150 +111,157 @@ void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_m
     *ep->buffer_control = value;
 }
 
+// Prepare buffer control register value
 void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
 {
-    // Prepare buffer control register value
-    uint32_t val = ep->transfer_size | USB_BUF_CTRL_AVAIL;
+  uint16_t remaining = ep->total_len - ep->len;
+  uint32_t ep_ctrl = *ep->endpoint_control;
+  uint32_t buf_ctrl;
 
-    if (!ep->rx)
-    {
-        // Copy data from user buffer to hw buffer
-        memcpy(ep->hw_data_buf, &ep->user_buf[ep->len], ep->transfer_size);
-        // Mark as full
-        val |= USB_BUF_CTRL_FULL;
-    }
+  // Buffer 0
+  ep->transfer_size = tu_min16(remaining, ep->wMaxPacketSize);
+  remaining -= ep->transfer_size;
 
-    // PID
-    val |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
+  buf_ctrl = ep->transfer_size | USB_BUF_CTRL_AVAIL;
+  if ( !ep->rx )
+  {
+    // Copy data from user buffer to hw buffer
+    memcpy(ep->hw_data_buf, ep->user_buf+ep->len, ep->transfer_size);
 
-#if TUSB_OPT_DEVICE_ENABLED
+    // Mark as full
+    buf_ctrl |= USB_BUF_CTRL_FULL;
+  }
+
+  // PID
+  buf_ctrl |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
+  ep->next_pid ^= 1u;
+
+  // Buffer 1
+  ep->buf_1_len = tu_min16(remaining, ep->wMaxPacketSize);
+  remaining -= ep->buf_1_len;
+
+  if (ep->buf_1_len)
+  {
+    buf_ctrl |= (ep->buf_1_len | USB_BUF_CTRL_AVAIL) << 16;
+    buf_ctrl |= (ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID) << 16;
     ep->next_pid ^= 1u;
 
-#else
-    // For Host (also device but since we dictate the endpoint size, following scenario does not occur)
-    // Next PID depends on the number of packet in case wMaxPacketSize < 64 (e.g Interrupt Endpoint 8, or 12)
-    // Special case with control status stage where PID is always DATA1
-    if ( ep->transfer_size == 0 )
+    if ( !ep->rx )
     {
-      // ZLP also toggle data
-      ep->next_pid ^= 1u;
-    }else
-    {
-      uint32_t packet_count = 1 + ((ep->transfer_size - 1) / ep->wMaxPacketSize);
-
-      if ( packet_count & 0x01 )
-      {
-        ep->next_pid ^= 1u;
-      }
+      // Copy data from user buffer to hw buffer
+      memcpy(ep->hw_data_buf+64, ep->user_buf+ep->len+ep->transfer_size, ep->buf_1_len);
     }
-#endif
 
+    // Set endpoint control double buffered bit if needed
+    ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER;
+    ep_ctrl |= EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER;
+  }else
+  {
+    ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
+    ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
+  }
+
+  *ep->endpoint_control = ep_ctrl;
 
 #if TUSB_OPT_HOST_ENABLED
-    // Is this the last buffer? Only really matters for host mode. Will trigger
-    // the trans complete irq but also stop it polling. We only really care about
-    // trans complete for setup packets being sent
-    if (ep->last_buf)
-    {
-        pico_trace("Last buf (%d bytes left)\n", ep->transfer_size);
-        val |= USB_BUF_CTRL_LAST;
-    }
+  // Is this the last buffer? Only really matters for host mode. Will trigger
+  // the trans complete irq but also stop it polling. We only really care about
+  // trans complete for setup packets being sent
+  if (remaining == 0)
+  {
+    buf_ctrl |= USB_BUF_CTRL_LAST << (ep->buf_1_len ? 16 : 0);
+  }
 #endif
 
-    // Finally, write to buffer_control which will trigger the transfer
-    // the next time the controller polls this dpram address
-    _hw_endpoint_buffer_control_set_value32(ep, val);
-    pico_trace("buffer control (0x%p) <- 0x%x\n", ep->buffer_control, val);
-    //print_bufctrl16(val);
+  print_bufctrl32(buf_ctrl);
+
+  // Finally, write to buffer_control which will trigger the transfer
+  // the next time the controller polls this dpram address
+  _hw_endpoint_buffer_control_set_value32(ep, buf_ctrl);
 }
 
 
 void _hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len)
 {
-    _hw_endpoint_lock_update(ep, 1);
-    pico_trace("Start transfer of total len %d on ep %d %s\n", total_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
-    if (ep->active)
-    {
-        // TODO: Is this acceptable for interrupt packets?
-        pico_warn("WARN: starting new transfer on already active ep %d %s\n", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+  _hw_endpoint_lock_update(ep, 1);
+  pico_trace("Start transfer of total len %d on ep %d %s\n", total_len, tu_edpt_number(ep->ep_addr),
+             ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+  if ( ep->active )
+  {
+    // TODO: Is this acceptable for interrupt packets?
+    pico_warn("WARN: starting new transfer on already active ep %d %s\n", tu_edpt_number(ep->ep_addr),
+              ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
 
-        hw_endpoint_reset_transfer(ep);
-    }
+    hw_endpoint_reset_transfer(ep);
+  }
 
-    // Fill in info now that we're kicking off the hw
-    ep->total_len = total_len;
-    ep->len = 0;
+  // Fill in info now that we're kicking off the hw
+  ep->total_len = total_len;
+  ep->len       = 0;
+  ep->active    = true;
+  ep->user_buf  = buffer;
 
-    // Limit by packet size but not less 64 (i.e low speed 8 bytes EP0)
-    ep->transfer_size = tu_min16(total_len, tu_max16(64, ep->wMaxPacketSize));
-
-    ep->active = true;
-    ep->user_buf = buffer;
-#if TUSB_OPT_HOST_ENABLED
-    // Recalculate if this is the last buffer
-    _hw_endpoint_update_last_buf(ep);
-    ep->buf_sel = 0;
-#endif
-
-    _hw_endpoint_start_next_buffer(ep);
-    _hw_endpoint_lock_update(ep, -1);
+  _hw_endpoint_start_next_buffer(ep);
+  _hw_endpoint_lock_update(ep, -1);
 }
 
-void _hw_endpoint_xfer_sync(struct hw_endpoint *ep)
+void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
 {
-    // Update hw endpoint struct with info from hardware
-    // after a buff status interrupt
+  // Update hw endpoint struct with info from hardware
+  // after a buff status interrupt
 
-    uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
+  uint32_t const buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
+  print_bufctrl32(buf_ctrl);
 
-#if TUSB_OPT_HOST_ENABLED
-    // RP2040-E4
-    // tag::host_buf_sel_fix[]
-    // TODO need changes to support double buffering
-    if (ep->buf_sel == 1)
+  // Transferred bytes for each buffer
+  uint16_t xferred_bytes[2];
+
+  xferred_bytes[0] = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
+
+  // double buffered: take buffer1 into account as well
+  if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS )
+  {
+    xferred_bytes[1] = (buf_ctrl >> 16) & USB_BUF_CTRL_LEN_MASK;
+  }else
+  {
+    xferred_bytes[1] = 0;
+  }
+
+  TU_LOG_INT(2, xferred_bytes[0]);
+  TU_LOG_INT(2, xferred_bytes[1]);
+
+  // We are continuing a transfer here. If we are TX, we have successfully
+  // sent some data can increase the length we have sent
+  if ( !ep->rx )
+  {
+    assert(!(buf_ctrl & USB_BUF_CTRL_FULL));
+    ep->len += xferred_bytes[0] + xferred_bytes[1];
+  }
+  else
+  {
+    // If we are OUT we have recieved some data, so can increase the length
+    // we have recieved AFTER we have copied it to the user buffer at the appropriate offset
+    assert(buf_ctrl & USB_BUF_CTRL_FULL);
+
+    memcpy(&ep->user_buf[ep->len], ep->hw_data_buf, xferred_bytes[0]);
+    ep->len += xferred_bytes[0];
+
+    if (xferred_bytes[1])
     {
-        // Host can erroneously write status to top half of buf_ctrl register
-        buf_ctrl = buf_ctrl >> 16;
-
-        // update buf1 -> buf0 to prevent panic with "already available"
-        *ep->buffer_control = buf_ctrl;
+      memcpy(&ep->user_buf[ep->len], ep->hw_data_buf+64, xferred_bytes[1]);
+      ep->len += xferred_bytes[1];
     }
-    // Flip buf sel for host
-    ep->buf_sel ^= 1u;
-    // end::host_buf_sel_fix[]
-#endif
+  }
 
-    // Get tranferred bytes after adjusted buf sel
-    uint16_t const transferred_bytes = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
-
-    // We are continuing a transfer here. If we are TX, we have successfullly
-    // sent some data can increase the length we have sent
-    if (!ep->rx)
-    {
-        assert(!(buf_ctrl & USB_BUF_CTRL_FULL));
-        pico_trace("tx %d bytes (buf_ctrl 0x%08x)\n", transferred_bytes, buf_ctrl);
-        ep->len += transferred_bytes;
-    }
-    else
-    {
-        // If we are OUT we have recieved some data, so can increase the length
-        // we have recieved AFTER we have copied it to the user buffer at the appropriate
-        // offset
-        pico_trace("rx %d bytes (buf_ctrl 0x%08x)\n", transferred_bytes, buf_ctrl);
-        assert(buf_ctrl & USB_BUF_CTRL_FULL);
-        memcpy(&ep->user_buf[ep->len], ep->hw_data_buf, transferred_bytes);
-        ep->len += transferred_bytes;
-    }
-
-    // Sometimes the host will send less data than we expect...
-    // If this is a short out transfer update the total length of the transfer
-    // to be the current length
-    if ((ep->rx) && (transferred_bytes < ep->wMaxPacketSize))
-    {
-        pico_trace("Short rx transfer\n");
-        // Reduce total length as this is last packet
-        ep->total_len = ep->len;
-    }
+  // Sometimes the host will send less data than we expect...
+  // If this is a short out transfer update the total length of the transfer
+  // to be the current length
+  if ( (ep->rx) && ((xferred_bytes[0] < ep->wMaxPacketSize) || (xferred_bytes[1] && (xferred_bytes[1] < ep->wMaxPacketSize))) )
+  {
+    pico_trace("Short rx transfer\n");
+    // Reduce total length as this is last packet
+    ep->total_len = ep->len;
+  }
 }
 
 // Returns true if transfer is complete
@@ -271,12 +278,11 @@ bool _hw_endpoint_xfer_continue(struct hw_endpoint *ep)
     _hw_endpoint_xfer_sync(ep);
 
     // Now we have synced our state with the hardware. Is there more data to transfer?
-    // Limit by packet size but not less 64 (i.e low speed 8 bytes EP0)
+    // Limit by packet size
     uint16_t remaining_bytes = ep->total_len - ep->len;
-    ep->transfer_size = tu_min16(remaining_bytes, tu_max16(64, ep->wMaxPacketSize));
-#if TUSB_OPT_HOST_ENABLED
-    _hw_endpoint_update_last_buf(ep);
-#endif
+    ep->transfer_size = tu_min16(remaining_bytes, ep->wMaxPacketSize);
+
+    TU_LOG_INT(2, ep->transfer_size);
 
     // Can happen because of programmer error so check for it
     if (ep->len > ep->total_len)
@@ -303,23 +309,4 @@ bool _hw_endpoint_xfer_continue(struct hw_endpoint *ep)
     return false;
 }
 
-void _hw_endpoint_xfer(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len, bool start)
-{
-    // Trace
-    pico_trace("hw_endpoint_xfer ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
-    pico_trace(" total_len %d, start=%d\n", total_len, start);
-
-    assert(ep->configured);
-
-
-    if (start)
-    {
-        _hw_endpoint_xfer_start(ep, buffer, total_len);
-    }
-    else
-    {
-        _hw_endpoint_xfer_continue(ep);
-    }
-}
-
 #endif
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 33f3ecd41..d27f4157a 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -17,7 +17,7 @@
 #endif
 
 
-#if false && !defined(NDEBUG)
+#if true || false && !defined(NDEBUG)
 #define pico_trace(format,args...) printf(format, ## args)
 #else
 #define pico_trace(format,...) ((void)0)
@@ -50,6 +50,7 @@ struct hw_endpoint
 
     // Endpoint control register
     io_rw_32 *endpoint_control;
+
     // Buffer control register
     io_rw_32 *buffer_control;
 
@@ -63,8 +64,11 @@ struct hw_endpoint
     bool active;
     uint16_t total_len;
     uint16_t len;
+
     // Amount of data with the hardware
-    uint16_t transfer_size;
+    uint16_t transfer_size; // buf0_len;
+    uint16_t buf_1_len;
+
     // User buffer in main memory
     uint8_t *user_buf;
 
@@ -76,6 +80,7 @@ struct hw_endpoint
 #if TUSB_OPT_HOST_ENABLED
     // Only needed for host mode
     bool last_buf;
+
     // RP2040-E4: HOST BUG. Host will incorrect write status to top half of buffer
     // control register when doing transfers > 1 packet
     uint8_t buf_sel;
@@ -90,11 +95,11 @@ struct hw_endpoint
 void rp2040_usb_init(void);
 
 void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
-void _hw_endpoint_xfer(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len, bool start);
 void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
 void _hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len);
 void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
 bool _hw_endpoint_xfer_continue(struct hw_endpoint *ep);
+
 void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask);
 static inline uint32_t _hw_endpoint_buffer_control_get_value32(struct hw_endpoint *ep) {
     return *ep->buffer_control;
@@ -149,11 +154,11 @@ static inline void print_bufctrl32(uint32_t u32)
   uint16_t u16;
 
   u16 = u32 >> 16;
-  TU_LOG(2, "Buffer Control 1 0x%x: ", u16);
+  TU_LOG(2, "  Buffer Control 1 0x%x: ", u16);
   print_bufctrl16(u16);
 
   u16 = u32 & 0x0000ffff;
-  TU_LOG(2, "Buffer Control 0 0x%x: ", u16);
+  TU_LOG(2, "  Buffer Control 0 0x%x: ", u16);
   print_bufctrl16(u16);
 }
 

From 572d986a0260543ada22592e3f2216a152ac632d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Jun 2021 17:14:22 +0700
Subject: [PATCH 0043/2085] improve usbh

---
 examples/host/cdc_msc_hid/src/hid_app.c | 12 +++-
 src/class/hid/hid_host.c                | 10 ----
 src/common/tusb_common.h                |  4 +-
 src/host/usbh.c                         | 78 +++++++++++++------------
 src/host/usbh_control.c                 |  4 +-
 5 files changed, 56 insertions(+), 52 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index 23ab12404..817646dab 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -30,7 +30,8 @@
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
-// If your host terminal support ansi escape code, it can be use to simulate mouse cursor
+// If your host terminal support ansi escape code such as TeraTerm
+// it can be use to simulate mouse cursor movement within terminal
 #define USE_ANSI_ESCAPE   0
 
 #define MAX_REPORT  4
@@ -113,6 +114,13 @@ void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t cons
     return;
   }
 
+  // For complete list of Usage Page & Usage checkout src/class/hid/hid.h. For examples:
+  // - Keyboard                     : Desktop, Keyboard
+  // - Mouse                        : Desktop, Mouse
+  // - Gamepad                      : Desktop, Gamepad
+  // - Consumer Control (Media Key) : Consumer, Consumer Control
+  // - System Control (Power key)   : Desktop, System Control
+  // - Generic (vendor)             : 0xFFxx, xx
   if ( rpt_info->usage_page == HID_USAGE_PAGE_DESKTOP )
   {
     switch (rpt_info->usage)
@@ -164,7 +172,7 @@ static void process_kbd_report(hid_keyboard_report_t const *report)
       }else
       {
         // not existed in previous report means the current key is pressed
-        bool const is_shift =  report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
+        bool const is_shift = report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
         uint8_t ch = keycode2ascii[report->keycode[i]][is_shift ? 1 : 0];
         putchar(ch);
         if ( ch == '\r' ) putchar('\n'); // added new line for enter key
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index cde5e23a5..a227c2a86 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -37,16 +37,6 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-/*
- "KEYBOARD"               : in_len=8 , out_len=1, usage_page=0x01, usage=0x06   # Generic Desktop, Keyboard
- "MOUSE"                  : in_len=4 , out_len=0, usage_page=0x01, usage=0x02   # Generic Desktop, Mouse
- "CONSUMER"               : in_len=2 , out_len=0, usage_page=0x0C, usage=0x01   # Consumer, Consumer Control
- "SYS_CONTROL"            : in_len=1 , out_len=0, usage_page=0x01, usage=0x80   # Generic Desktop, Sys Control
- "GAMEPAD"                : in_len=6 , out_len=0, usage_page=0x01, usage=0x05   # Generic Desktop, Game Pad
- "DIGITIZER"              : in_len=5 , out_len=0, usage_page=0x0D, usage=0x02   # Digitizers, Pen
- "XAC_COMPATIBLE_GAMEPAD" : in_len=3 , out_len=0, usage_page=0x01, usage=0x05   # Generic Desktop, Game Pad
- "RAW"                    : in_len=64, out_len=0, usage_page=0xFFAF, usage=0xAF # Vendor 0xFFAF "Adafruit", 0xAF
- */
 typedef struct
 {
   uint8_t itf_num;
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 889ad7b25..fe5bf5f41 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -317,8 +317,8 @@ void tu_print_var(uint8_t const* buf, uint32_t bufsize)
 #define TU_LOG1               tu_printf
 #define TU_LOG1_MEM           tu_print_mem
 #define TU_LOG1_VAR(_x)       tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
-#define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\n", (uint32_t) (_x) )
-#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\n", (uint32_t) (_x) )
+#define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (uint32_t) (_x) )
+#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (uint32_t) (_x) )
 
 // Log Level 2: Warn
 #if CFG_TUSB_DEBUG >= 2
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 59246a663..81b9e84af 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -795,6 +795,8 @@ static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_r
     return false;
   }
 
+  TU_ASSERT(tu_desc_type(_usbh_ctrl_buf) == TUSB_DESC_DEVICE);
+
   // Reset device again before Set Address
   TU_LOG2("Port reset \r\n");
 
@@ -938,7 +940,7 @@ static bool enum_get_config_desc_complete(uint8_t dev_addr, tusb_control_request
 
   // Parse configuration & set up drivers
   // Driver open aren't allowed to make any usb transfer yet
-  parse_configuration_descriptor(dev_addr, (tusb_desc_configuration_t*) _usbh_ctrl_buf);
+  TU_ASSERT( parse_configuration_descriptor(dev_addr, (tusb_desc_configuration_t*) _usbh_ctrl_buf) );
 
   TU_LOG2("Set Configuration = %d\r\n", CONFIG_NUM);
   tusb_control_request_t const new_request =
@@ -988,49 +990,53 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
   // parse each interfaces
   while( p_desc < _usbh_ctrl_buf + desc_cfg->wTotalLength )
   {
-    // skip until we see interface descriptor
-    if ( TUSB_DESC_INTERFACE != tu_desc_type(p_desc) )
-    {
-      p_desc = tu_desc_next(p_desc); // skip the descriptor, increase by the descriptor's length
-    }else
-    {
-      tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
+    tusb_desc_interface_assoc_t const * desc_itf_assoc = NULL;
 
-      // Check if class is supported
-      uint8_t drv_id;
-      for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
-      {
-        if ( usbh_class_drivers[drv_id].class_code == desc_itf->bInterfaceClass ) break;
-      }
+    // Class will always starts with Interface Association (if any) and then Interface descriptor
+    if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
+    {
+      desc_itf_assoc = (tusb_desc_interface_assoc_t const *) p_desc;
+      p_desc = tu_desc_next(p_desc); // next to Interface
+    }
 
-      if( drv_id >= USBH_CLASS_DRIVER_COUNT )
+    TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
+
+    tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
+
+    // Check if class is supported
+    uint8_t drv_id;
+    for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+    {
+      if ( usbh_class_drivers[drv_id].class_code == desc_itf->bInterfaceClass ) break;
+    }
+
+    if( drv_id >= USBH_CLASS_DRIVER_COUNT )
+    {
+      // skip unsupported class
+      p_desc = tu_desc_next(p_desc);
+    }
+    else
+    {
+      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+
+      // Interface number must not be used already TODO alternate interface
+      TU_ASSERT( dev->itf2drv[desc_itf->bInterfaceNumber] == 0xff );
+      dev->itf2drv[desc_itf->bInterfaceNumber] = drv_id;
+
+      if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && dev->hub_addr != 0)
       {
-        // skip unsupported class
+        // TODO Attach hub to Hub is not currently supported
+        // skip this interface
         p_desc = tu_desc_next(p_desc);
       }
       else
       {
-        usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+        TU_LOG2("%s open\r\n", driver->name);
 
-        // Interface number must not be used already TODO alternate interface
-        TU_ASSERT( dev->itf2drv[desc_itf->bInterfaceNumber] == 0xff );
-        dev->itf2drv[desc_itf->bInterfaceNumber] = drv_id;
-
-        if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && dev->hub_addr != 0)
-        {
-          // TODO Attach hub to Hub is not currently supported
-          // skip this interface
-          p_desc = tu_desc_next(p_desc);
-        }
-        else
-        {
-          TU_LOG2("%s open\r\n", driver->name);
-
-          uint16_t itf_len = 0;
-          TU_ASSERT( driver->open(dev->rhport, dev_addr, desc_itf, &itf_len) );
-          TU_ASSERT( itf_len >= sizeof(tusb_desc_interface_t) );
-          p_desc += itf_len;
-        }
+        uint16_t itf_len = 0;
+        TU_ASSERT( driver->open(dev->rhport, dev_addr, desc_itf, &itf_len) );
+        TU_ASSERT( itf_len >= sizeof(tusb_desc_interface_t) );
+        p_desc += itf_len;
       }
     }
   }
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index aa82f14ba..91dbdfe99 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -68,7 +68,7 @@ bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
   _ctrl_xfer.stage       = STAGE_SETUP;
   _ctrl_xfer.complete_cb = complete_cb;
 
-  TU_LOG2("Send Setup to address %u: ", dev_addr);
+  TU_LOG2("Control Setup (addr = %u): ", dev_addr);
   TU_LOG2_VAR(request);
   TU_LOG2("\r\n");
 
@@ -119,7 +119,7 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
 
         if (request->wLength)
         {
-          TU_LOG2("Control data:\r\n");
+          TU_LOG2("Control data (addr = %u):\r\n", dev_addr);
           TU_LOG2_MEM(_ctrl_xfer.buffer, request->wLength, 2);
         }
 

From f8aa4b3ff3e3db71e752d9278bc248fb9e066f75 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Wed, 3 Mar 2021 10:14:41 +0100
Subject: [PATCH 0044/2085] Add sketchy SAME70 DCD driver.

---
 .../device/cdc_dual_ports/src/tusb_config.h   |   2 +-
 .../cdc_dual_ports/src/usb_descriptors.c      |  32 +-
 src/portable/microchip/same70/dcd_same70.c    | 564 ++++++++++++++++++
 3 files changed, 589 insertions(+), 9 deletions(-)
 create mode 100644 src/portable/microchip/same70/dcd_same70.c

diff --git a/examples/device/cdc_dual_ports/src/tusb_config.h b/examples/device/cdc_dual_ports/src/tusb_config.h
index c7e87bf67..45167da8e 100644
--- a/examples/device/cdc_dual_ports/src/tusb_config.h
+++ b/examples/device/cdc_dual_ports/src/tusb_config.h
@@ -48,7 +48,7 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAME70)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index 8e19678e5..e39c140cc 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -87,16 +87,32 @@ enum
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
   #define EPNUM_CDC_0_NOTIF   0x81
-  #define EPNUM_CDC_0_DATA    0x02
+  #define EPNUM_CDC_0_OUT     0x02
+  #define EPNUM_CDC_0_IN      0x82
 
   #define EPNUM_CDC_1_NOTIF   0x84
-  #define EPNUM_CDC_1_DATA    0x05
+  #define EPNUM_CDC_1_OUT     0x05
+  #define EPNUM_CDC_1_IN      0x85
+
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAME70
+  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_0_NOTIF   0x81
+  #define EPNUM_CDC_0_OUT     0x02
+  #define EPNUM_CDC_0_IN      0x83
+
+  #define EPNUM_CDC_1_NOTIF   0x84
+  #define EPNUM_CDC_1_OUT     0x05
+  #define EPNUM_CDC_1_IN      0x86
+
 #else
   #define EPNUM_CDC_0_NOTIF   0x81
-  #define EPNUM_CDC_0_DATA    0x02
+  #define EPNUM_CDC_0_OUT     0x02
+  #define EPNUM_CDC_0_IN      0x82
 
   #define EPNUM_CDC_1_NOTIF   0x83
-  #define EPNUM_CDC_1_DATA    0x04
+  #define EPNUM_CDC_1_OUT     0x04
+  #define EPNUM_CDC_1_IN      0x84
 #endif
 
 uint8_t const desc_fs_configuration[] =
@@ -105,10 +121,10 @@ uint8_t const desc_fs_configuration[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
   // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_DATA, 0x80 | EPNUM_CDC_0_DATA, 64),
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_OUT, EPNUM_CDC_0_IN, 64),
 
   // 2nd CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_1, 4, EPNUM_CDC_1_NOTIF, 8, EPNUM_CDC_1_DATA, 0x80 | EPNUM_CDC_1_DATA, 64),
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_1, 4, EPNUM_CDC_1_NOTIF, 8, EPNUM_CDC_1_OUT, EPNUM_CDC_1_IN, 64),
 };
 
 #if TUD_OPT_HIGH_SPEED
@@ -118,10 +134,10 @@ uint8_t const desc_hs_configuration[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
   // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_DATA, 0x80 | EPNUM_CDC_0_DATA, 512),
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_OUT, EPNUM_CDC_0_IN, 512),
 
   // 2nd CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_1, 4, EPNUM_CDC_1_NOTIF, 8, EPNUM_CDC_1_DATA, 0x80 | EPNUM_CDC_1_DATA, 512),
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_1, 4, EPNUM_CDC_1_NOTIF, 8, EPNUM_CDC_1_OUT, EPNUM_CDC_1_IN, 512),
 };
 #endif
 
diff --git a/src/portable/microchip/same70/dcd_same70.c b/src/portable/microchip/same70/dcd_same70.c
new file mode 100644
index 000000000..7fdc9dd08
--- /dev/null
+++ b/src/portable/microchip/same70/dcd_same70.c
@@ -0,0 +1,564 @@
+/* 
+* The MIT License (MIT)
+*
+* Copyright (c) 2018, hathach (tinyusb.org)
+* Copyright (c) 2020, HiFiPhile
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+* This file is part of the TinyUSB stack.
+*/
+
+
+
+#include "tusb_option.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_SAME70
+
+#include "device/dcd.h"
+
+#include "sam.h"
+
+#include "SEGGER_RTT.h"
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
+// We disable SOF for now until needed later on
+#ifndef USE_SOF
+#  define USE_SOF     0
+#endif
+
+#ifndef USBHS_RAM_ADDR
+#  define USBHS_RAM_ADDR        0xA0100000u
+#endif
+
+#define get_ep_fifo_ptr(ep, scale) (((volatile TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
+
+#define EP_MAX            10
+
+typedef struct {
+  uint8_t * buffer;
+  uint16_t total_len;
+  uint16_t queued_len;
+  uint16_t max_packet_size;
+  uint8_t interval;
+} xfer_ctl_t;
+
+xfer_ctl_t xfer_status[EP_MAX+1];
+
+static const tusb_desc_endpoint_t ep0_desc =
+{
+  .bLength          = sizeof(tusb_desc_endpoint_t),
+  .bDescriptorType  = TUSB_DESC_ENDPOINT,
+
+  .bEndpointAddress = 0x00,
+  .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
+  .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
+  .bInterval        = 0
+};
+
+static tusb_speed_t get_speed(void);
+static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
+//------------------------------------------------------------------
+// Device API
+//------------------------------------------------------------------
+
+// Initialize controller to device mode
+void dcd_init (uint8_t rhport)
+{
+    // Enable USBPLL
+    PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
+    // Wait until USB UTMI stabilize
+    while (!(PMC->PMC_SR & PMC_SR_LOCKU));
+    // Enable USB FS clk
+    PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
+    PMC->PMC_SCER = PMC_SCER_USBCLK;
+    dcd_connect(rhport);
+}
+
+// Enable device interrupt
+void dcd_int_enable (uint8_t rhport)
+{
+    (void) rhport;
+    NVIC_EnableIRQ((IRQn_Type) ID_USBHS);
+}
+
+// Disable device interrupt
+void dcd_int_disable (uint8_t rhport)
+{
+    (void) rhport;
+    NVIC_DisableIRQ((IRQn_Type) ID_USBHS);
+}
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
+{
+    (void) rhport;
+    // Set the address but keep it disabled for now. It should be enabled
+    // only after the ack to the host completes.
+    USBHS->USBHS_DEVCTRL &= ~(USBHS_DEVCTRL_UADD_Msk | USBHS_DEVCTRL_ADDEN);
+    USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(dev_addr);
+    
+    // Respond with status
+    dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+
+// Wake up host
+void dcd_remote_wakeup (uint8_t rhport)
+{
+    (void) rhport;
+    USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP;
+}
+
+// Connect by enabling internal pull-up resistor on D+/D-
+void dcd_connect(uint8_t rhport)
+{
+    uint32_t irq_state = __get_PRIMASK();
+    __disable_irq();
+    // Enable USB clock
+    PMC->PMC_PCER1 = 1 << (ID_USBHS - 32);
+    // Enable the USB controller in device mode
+    USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE;
+    // Wait to unfreeze clock
+    while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+    // Attach the device
+    USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH;
+    // Enable the End Of Reset, Suspend & Wakeup interrupts
+    USBHS->USBHS_DEVIER = (USBHS_DEVIER_EORSTES | USBHS_DEVIER_SUSPES | USBHS_DEVIER_WAKEUPES);
+#if USE_SOF
+    USBHS->USBHS_DEVIER = USBHS_DEVIER_SOFES;
+#endif
+    // Clear the End Of Reset, SOF & Wakeup interrupts
+    USBHS->USBHS_DEVICR = (USBHS_DEVICR_EORSTC | USBHS_DEVICR_SOFC | USBHS_DEVICR_WAKEUPC);
+    // Manually set the Suspend Interrupt
+    USBHS->USBHS_DEVIFR |= USBHS_DEVIFR_SUSPS;
+    // Ack the Wakeup Interrupt
+    USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
+    // Freeze USB clock
+    USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
+    __set_PRIMASK(irq_state);
+}
+
+// Disconnect by disabling internal pull-up resistor on D+/D-
+void dcd_disconnect(uint8_t rhport)
+{
+    (void) rhport;
+    uint32_t irq_state = __get_PRIMASK();
+    __disable_irq();
+    // Disable all endpoints
+    USBHS->USBHS_DEVEPT &= ~(0x3FF << USBHS_DEVEPT_EPEN0_Pos);
+    // Unfreeze USB clock
+    USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
+    // Wait to unfreeze clock
+    while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+    // Clear all the pending interrupts
+    USBHS->USBHS_DEVICR = USBHS_DEVICR_Msk;
+    // Disable all interrupts
+    USBHS->USBHS_DEVIDR = USBHS_DEVCTRL_UADD_Msk;
+    // Detach the device
+    USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH;
+    // Disable the device address
+    USBHS->USBHS_DEVCTRL &=~(USBHS_DEVCTRL_ADDEN | USBHS_DEVCTRL_UADD_Msk);
+     __set_PRIMASK(irq_state);
+}
+
+static tusb_speed_t get_speed(void)
+{
+  switch((USBHS->USBHS_SR & USBHS_SR_SPEED_Msk) >> USBHS_SR_SPEED_Pos)
+  {
+      case USBHS_SR_SPEED_FULL_SPEED_Val:
+      default:
+          return TUSB_SPEED_FULL;
+      case USBHS_SR_SPEED_HIGH_SPEED_Val:
+          return TUSB_SPEED_HIGH;
+      case USBHS_SR_SPEED_LOW_SPEED_Val:
+          return TUSB_SPEED_LOW;
+  }
+}
+
+static void dcd_ep_handler(uint8_t ep_ix)
+{
+    uint32_t int_status = USBHS->USBHS_DEVEPTISR[ep_ix] & USBHS->USBHS_DEVEPTIMR[ep_ix];
+    uint32_t dev_ctrl = USBHS->USBHS_DEVCTRL;
+    uint16_t count = (USBHS->USBHS_DEVEPTISR[ep_ix] &
+			  USBHS_DEVEPTISR_BYCT_Msk) >> USBHS_DEVEPTISR_BYCT_Pos;
+    SEGGER_RTT_printf(0, "ep: %u %u %u \r\n", ep_ix, count, int_status);
+    if(ep_ix == 0U)
+    {
+        if (int_status & USBHS_DEVEPTISR_CTRL_RXSTPI) {
+            
+            // Get 8-bit access to endpoint 0 FIFO from USB RAM address 
+            volatile uint8_t *ptr = get_ep_fifo_ptr(0,8);
+            SCB_InvalidateDCache_by_Addr((uint32_t *) ptr, 8);
+            dcd_event_setup_received(0, (uint8_t*)ptr, true);
+            
+            // Acknowledge the interrupt 
+            USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXSTPIC;
+        }
+        if (int_status & USBHS_DEVEPTISR_RXOUTI) {
+            // Disable the interrupt 
+            //USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_RXOUTEC;
+            
+            xfer_ctl_t *xfer = &xfer_status[0];
+            
+            if(count)
+            {
+                volatile uint8_t *ptr = get_ep_fifo_ptr(0,8);
+                for (int i = 0; i < count; i++) {
+                    xfer->buffer[xfer->queued_len + i] = ptr[i];
+                }
+                xfer->queued_len = (uint16_t)(xfer->queued_len + count);
+            }
+            
+            USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXOUTIC;
+            
+            if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
+            {
+                // RX COMPLETE 
+                dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+                xfer->queued_len = 0;
+                SEGGER_RTT_printf(0, "rx: %u \r\n", xfer->queued_len);
+                // Though the host could still send, we don't know.
+            }
+            
+            
+        }
+        if (int_status & USBHS_DEVEPTISR_TXINI) {
+            // Disable the interrupt 
+            USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
+            if (!(dev_ctrl & USBHS_DEVCTRL_ADDEN) &&
+                (dev_ctrl & USBHS_DEVCTRL_UADD_Msk) != 0U) {
+                    // Commit the pending address update.  This
+                    // must be done after the ack to the host
+                    // completes else the ack will get dropped.
+                    USBHS->USBHS_DEVCTRL = dev_ctrl | USBHS_DEVCTRL_ADDEN;
+                }
+            xfer_ctl_t * xfer = &xfer_status[EP_MAX];
+            if((xfer->total_len != xfer->queued_len)) // TX not complete 
+            {
+                dcd_transmit_packet(xfer, 0);
+            }
+            else // TX Complete 
+            {
+                dcd_event_xfer_complete(0, (uint8_t)(0x80 + 0), xfer->total_len, XFER_RESULT_SUCCESS, true);
+            }
+        }
+    }
+    else
+    {
+        if (int_status & USBHS_DEVEPTISR_RXOUTI) {
+            // Acknowledge the interrupt 
+            USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
+            
+            xfer_ctl_t *xfer = &xfer_status[ep_ix];
+            
+            if(count)
+            {
+                volatile uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
+                for (int i = 0; i < count; i++) {
+                    xfer->buffer[xfer->queued_len + i] = ptr[i];
+                }
+                xfer->queued_len = (uint16_t)(xfer->queued_len + count);
+            }
+            // Clear the FIFO control flag to receive more data.
+            USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
+            if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
+            {
+                // RX COMPLETE 
+                dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+                xfer->queued_len = 0;
+                // Though the host could still send, we don't know.
+            }
+        }
+        if (int_status & USBHS_DEVEPTISR_TXINI) {
+            // Acknowledge the interrupt 
+            USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
+            xfer_ctl_t * xfer = &xfer_status[ep_ix];;
+            if((xfer->total_len != xfer->queued_len)) // TX not complete 
+            {
+                dcd_transmit_packet(xfer, ep_ix);
+            }
+            else // TX Complete 
+            {
+                dcd_event_xfer_complete(0, (uint8_t)(0x80 + ep_ix), xfer->total_len, XFER_RESULT_SUCCESS, true);
+            }
+        }
+    }
+}
+
+void dcd_int_handler(uint8_t rhport)
+{
+    (void) rhport;
+    uint32_t int_status = USBHS->USBHS_DEVISR;
+    // End of reset interrupt 
+    if (int_status & USBHS_DEVISR_EORST) {
+        // Unfreeze USB clock 
+        USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
+        while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+        // Reset all endpoints
+        for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++)
+        {
+            // Disable endpoint interrupt 
+            USBHS->USBHS_DEVIDR = 1 << (USBHS_DEVIDR_PEP_0_Pos + ep_ix);
+            // Disable endpoint and SETUP, IN or OUT interrupts 
+            USBHS->USBHS_DEVEPT &= ~ (1 << (USBHS_DEVEPT_EPEN0_Pos + ep_ix));
+            // Free all endpoint memory 
+            USBHS->USBHS_DEVEPTCFG[ep_ix] &= ~USBHS_DEVEPTCFG_ALLOC;
+        }
+        dcd_edpt_open (0, &ep0_desc);
+        // Acknowledge the End of Reset interrupt 
+        USBHS->USBHS_DEVICR = USBHS_DEVICR_EORSTC;
+        // Acknowledge the Wakeup interrupt 
+        USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
+        // Acknowledge the suspend interrupt 
+        USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
+        // Enable Suspend Interrupt 
+        USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
+        
+        dcd_event_bus_reset(rhport, get_speed(), true);
+    }
+    // End of Wakeup interrupt 
+    if (int_status & USBHS_DEVISR_WAKEUP) {
+        // Unfreeze USB clock 
+        USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
+        // Wait to unfreeze clock 
+        while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+        // Acknowledge the Wakeup interrupt 
+        USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
+        // Disable Wakeup Interrupt 
+        USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC;
+        // Enable Suspend Interrupt 
+        USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
+        
+        dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+    }
+    // Suspend interrupt 
+    if (int_status & USBHS_DEVISR_SUSP) {
+        // Unfreeze USB clock 
+        USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
+         // Wait to unfreeze clock 
+        while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+        // Acknowledge the suspend interrupt 
+        USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
+        // Disable Suspend Interrupt 
+        USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC;
+        // Enable Wakeup Interrupt 
+        USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES;
+        // Freeze USB clock 
+        USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
+        
+        dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+    }
+#if USE_SOF
+    if(int_status & USBHS_DEVISR_SOF) {
+        USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC;
+        
+        dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+    }
+#endif 
+    // Endpoints interrupt 
+    for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
+        if (int_status & (1 << (USBHS_DEVISR_PEP_0_Pos + ep_ix))) {
+            dcd_ep_handler(ep_ix);
+        }
+    }
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+    (void) rhport;
+    uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
+    uint8_t const dir   = tu_edpt_dir(ep_desc->bEndpointAddress);
+    uint16_t const epMaxPktSize = ep_desc->wMaxPacketSize.size;
+    tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
+    uint8_t fifoSize = 0;                       // FIFO size 
+    uint16_t defaultEndpointSize = 8;           // Default size of Endpoint 
+    // Find upper 2 power number of epMaxPktSize 
+    if(epMaxPktSize)
+    {
+        while (defaultEndpointSize < epMaxPktSize)
+        {
+            fifoSize++;
+            defaultEndpointSize <<= 1;
+        }
+    }
+    xfer_status[epnum].max_packet_size = epMaxPktSize;
+    
+    if(epnum == 0)
+    {
+        xfer_status[EP_MAX].max_packet_size = epMaxPktSize;
+        // Enable the control endpoint - Endpoint 0 
+        USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
+        // Configure the Endpoint 0 configuration register 
+        USBHS->USBHS_DEVEPTCFG[0] =
+        (
+             USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
+             USBHS_DEVEPTCFG_EPTYPE(TUSB_XFER_CONTROL) |
+             USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
+             USBHS_DEVEPTCFG_ALLOC
+         );
+        USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RSTDTS;
+        USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_STALLRQC;
+        if(USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK))
+        {
+            // Endpoint configuration is successful 
+            USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RXSTPES  | USBHS_DEVEPTIER_RXOUTES;
+            // Enable Endpoint 0 Interrupts 
+            USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
+            return true;
+        }
+        else
+        {
+            // Endpoint configuration is not successful 
+            return false;
+        }
+    }
+    else
+    {
+        // Enable the endpoint 
+        USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
+        // Set up the maxpacket size, fifo start address fifosize
+        // and enable the interrupt. CLear the data toggle. 
+        USBHS->USBHS_DEVEPTCFG[epnum] =
+        (
+            USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
+            USBHS_DEVEPTCFG_EPTYPE(eptype) |
+            USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
+            USBHS_DEVEPTCFG_ALLOC |
+            ((dir & 0x01) << USBHS_DEVEPTCFG_EPDIR_Pos)
+        );
+        
+        if (eptype == TUSB_XFER_ISOCHRONOUS)
+        {
+            USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1); 
+        }
+        USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RSTDTS;
+        USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
+        if(USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK))
+        {
+            // Endpoint configuration is successful. Enable Endpoint Interrupts
+            if(dir == TUSB_DIR_OUT)
+            {
+                USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
+            }
+            else
+            {
+                USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_TXINIC;
+		USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_TXINES;
+            }
+            USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
+            return true;
+        }
+        else
+        {
+            // Endpoint configuration is not successful 
+            return false;
+        }
+    }
+}
+
+static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
+{
+    uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
+    
+    if(len > xfer->max_packet_size) // max packet size for FS transfer
+    {
+        len = xfer->max_packet_size;
+    }
+    
+    volatile uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
+    for (int i = 0; i < len; i++) {
+        ptr[i] = xfer->buffer[xfer->queued_len + i];
+    }
+
+    xfer->queued_len = (uint16_t)(xfer->queued_len + len);
+    
+    if (ep_ix == 0U) {
+        
+        // Control endpoint: clear the interrupt flag to send the data,
+        // and re-enable the interrupts to trigger an interrupt at the
+        // end of the transfer.
+        USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
+        USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_TXINES;
+    } else {
+        
+        // Other endpoint types: clear the FIFO control flag to send the data.
+        USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
+    }
+}
+
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+    (void) rhport;
+    
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    uint8_t const dir   = tu_edpt_dir(ep_addr);
+    
+    xfer_ctl_t * xfer = &xfer_status[epnum];
+    if(ep_addr == 0x80)
+        xfer = &xfer_status[EP_MAX];
+    
+    xfer->buffer = buffer;
+    xfer->total_len = total_bytes;
+    xfer->queued_len = 0;
+    
+    SEGGER_RTT_printf(0, "xfer: %u %u %u \r\n", epnum, dir, total_bytes);
+    
+    if ( dir == TUSB_DIR_OUT )
+    {
+        // Endpoint configuration is successful 
+        // Acknowledge the interrupt 
+        //USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_RXOUTIC;
+        
+        //USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
+    }
+    else // IN
+    {
+        dcd_transmit_packet(xfer,epnum);
+    }
+    return true;
+}
+
+// Stall endpoint
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
+{
+    (void) rhport;
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_STALLRQS;
+}
+
+// clear stall, data toggle is also reset to DATA0
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
+{
+    (void) rhport;
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
+    USBHS->USBHS_DEVEPTIER[epnum] = USBHS_HSTPIPIER_RSTDTS;
+}
+
+#endif

From e7bee80948bdb5132e815eaaf957b75f691cfaa3 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Wed, 3 Mar 2021 19:33:36 +0100
Subject: [PATCH 0045/2085] Add OPT_MCU_SAME70 option value.

---
 src/tusb_option.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 5cfcc08e2..fb86d7f9c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -61,6 +61,7 @@
 #define OPT_MCU_SAME5X            203 ///< MicroChip SAM E5x
 #define OPT_MCU_SAMD11            204 ///< MicroChip SAMD11
 #define OPT_MCU_SAML22            205 ///< MicroChip SAML22
+#define OPT_MCU_SAME70            206 ///< MicroChip SAME70 series
 
 // STM32
 #define OPT_MCU_STM32F0           300 ///< ST STM32F0

From 4f4a33b3784729ff4d7bc91224350291d2367ea3 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Wed, 3 Mar 2021 19:34:53 +0100
Subject: [PATCH 0046/2085] Seems like fixed ep0 issues, code format.

Signed-off-by: HiFiPhile <admin@hifiphile.com>
---
 src/portable/microchip/same70/dcd_same70.c | 747 ++++++++++-----------
 1 file changed, 349 insertions(+), 398 deletions(-)

diff --git a/src/portable/microchip/same70/dcd_same70.c b/src/portable/microchip/same70/dcd_same70.c
index 7fdc9dd08..98fe61360 100644
--- a/src/portable/microchip/same70/dcd_same70.c
+++ b/src/portable/microchip/same70/dcd_same70.c
@@ -2,7 +2,7 @@
 * The MIT License (MIT)
 *
 * Copyright (c) 2018, hathach (tinyusb.org)
-* Copyright (c) 2020, HiFiPhile
+* Copyright (c) 2021, HiFiPhile
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -35,7 +35,6 @@
 
 #include "sam.h"
 
-#include "SEGGER_RTT.h"
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
@@ -50,7 +49,7 @@
 #  define USBHS_RAM_ADDR        0xA0100000u
 #endif
 
-#define get_ep_fifo_ptr(ep, scale) (((volatile TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
+#define get_ep_fifo_ptr(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
 
 #define EP_MAX            10
 
@@ -66,13 +65,8 @@ xfer_ctl_t xfer_status[EP_MAX+1];
 
 static const tusb_desc_endpoint_t ep0_desc =
 {
-  .bLength          = sizeof(tusb_desc_endpoint_t),
-  .bDescriptorType  = TUSB_DESC_ENDPOINT,
-
   .bEndpointAddress = 0x00,
-  .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
   .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
-  .bInterval        = 0
 };
 
 static tusb_speed_t get_speed(void);
@@ -84,481 +78,438 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
 // Initialize controller to device mode
 void dcd_init (uint8_t rhport)
 {
-    // Enable USBPLL
-    PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
-    // Wait until USB UTMI stabilize
-    while (!(PMC->PMC_SR & PMC_SR_LOCKU));
-    // Enable USB FS clk
-    PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
-    PMC->PMC_SCER = PMC_SCER_USBCLK;
-    dcd_connect(rhport);
+  // Enable USBPLL
+  PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
+  // Wait until USB UTMI stabilize
+  while (!(PMC->PMC_SR & PMC_SR_LOCKU));
+  // Enable USB FS clk
+  PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
+  PMC->PMC_SCER = PMC_SCER_USBCLK;
+  dcd_connect(rhport);
 }
 
 // Enable device interrupt
 void dcd_int_enable (uint8_t rhport)
 {
-    (void) rhport;
-    NVIC_EnableIRQ((IRQn_Type) ID_USBHS);
+  (void) rhport;
+  NVIC_EnableIRQ((IRQn_Type) ID_USBHS);
 }
 
 // Disable device interrupt
 void dcd_int_disable (uint8_t rhport)
 {
-    (void) rhport;
-    NVIC_DisableIRQ((IRQn_Type) ID_USBHS);
+  (void) rhport;
+  NVIC_DisableIRQ((IRQn_Type) ID_USBHS);
 }
 
 // Receive Set Address request, mcu port must also include status IN response
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-    (void) rhport;
-    // Set the address but keep it disabled for now. It should be enabled
-    // only after the ack to the host completes.
-    USBHS->USBHS_DEVCTRL &= ~(USBHS_DEVCTRL_UADD_Msk | USBHS_DEVCTRL_ADDEN);
-    USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(dev_addr);
-    
-    // Respond with status
-    dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  // DCD can only set address after status for this request is complete
+  // do it at dcd_edpt0_status_complete()
+  
+  // Response with zlp status
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
 
 // Wake up host
 void dcd_remote_wakeup (uint8_t rhport)
 {
-    (void) rhport;
-    USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP;
+  (void) rhport;
+  USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP;
 }
 
 // Connect by enabling internal pull-up resistor on D+/D-
 void dcd_connect(uint8_t rhport)
 {
-    uint32_t irq_state = __get_PRIMASK();
-    __disable_irq();
-    // Enable USB clock
-    PMC->PMC_PCER1 = 1 << (ID_USBHS - 32);
-    // Enable the USB controller in device mode
-    USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE;
-    // Wait to unfreeze clock
-    while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
-    // Attach the device
-    USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH;
-    // Enable the End Of Reset, Suspend & Wakeup interrupts
-    USBHS->USBHS_DEVIER = (USBHS_DEVIER_EORSTES | USBHS_DEVIER_SUSPES | USBHS_DEVIER_WAKEUPES);
+  uint32_t irq_state = __get_PRIMASK();
+  __disable_irq();
+  // Enable USB clock
+  PMC->PMC_PCER1 = 1 << (ID_USBHS - 32);
+  // Enable the USB controller in device mode
+  USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE;
+  // Wait to unfreeze clock
+  while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+  // Attach the device
+  USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH;
+  // Enable the End Of Reset, Suspend & Wakeup interrupts
+  USBHS->USBHS_DEVIER = (USBHS_DEVIER_EORSTES | USBHS_DEVIER_SUSPES | USBHS_DEVIER_WAKEUPES);
 #if USE_SOF
-    USBHS->USBHS_DEVIER = USBHS_DEVIER_SOFES;
+  USBHS->USBHS_DEVIER = USBHS_DEVIER_SOFES;
 #endif
-    // Clear the End Of Reset, SOF & Wakeup interrupts
-    USBHS->USBHS_DEVICR = (USBHS_DEVICR_EORSTC | USBHS_DEVICR_SOFC | USBHS_DEVICR_WAKEUPC);
-    // Manually set the Suspend Interrupt
-    USBHS->USBHS_DEVIFR |= USBHS_DEVIFR_SUSPS;
-    // Ack the Wakeup Interrupt
-    USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
-    // Freeze USB clock
-    USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
-    __set_PRIMASK(irq_state);
+  // Clear the End Of Reset, SOF & Wakeup interrupts
+  USBHS->USBHS_DEVICR = (USBHS_DEVICR_EORSTC | USBHS_DEVICR_SOFC | USBHS_DEVICR_WAKEUPC);
+  // Manually set the Suspend Interrupt
+  USBHS->USBHS_DEVIFR |= USBHS_DEVIFR_SUSPS;
+  // Ack the Wakeup Interrupt
+  USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
+  // Freeze USB clock
+  USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
+  __set_PRIMASK(irq_state);
 }
 
 // Disconnect by disabling internal pull-up resistor on D+/D-
 void dcd_disconnect(uint8_t rhport)
 {
-    (void) rhport;
-    uint32_t irq_state = __get_PRIMASK();
-    __disable_irq();
-    // Disable all endpoints
-    USBHS->USBHS_DEVEPT &= ~(0x3FF << USBHS_DEVEPT_EPEN0_Pos);
-    // Unfreeze USB clock
-    USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-    // Wait to unfreeze clock
-    while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
-    // Clear all the pending interrupts
-    USBHS->USBHS_DEVICR = USBHS_DEVICR_Msk;
-    // Disable all interrupts
-    USBHS->USBHS_DEVIDR = USBHS_DEVCTRL_UADD_Msk;
-    // Detach the device
-    USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH;
-    // Disable the device address
-    USBHS->USBHS_DEVCTRL &=~(USBHS_DEVCTRL_ADDEN | USBHS_DEVCTRL_UADD_Msk);
-     __set_PRIMASK(irq_state);
+  (void) rhport;
+  uint32_t irq_state = __get_PRIMASK();
+  __disable_irq();
+  // Disable all endpoints
+  USBHS->USBHS_DEVEPT &= ~(0x3FF << USBHS_DEVEPT_EPEN0_Pos);
+  // Unfreeze USB clock
+  USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
+  // Wait to unfreeze clock
+  while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+  // Clear all the pending interrupts
+  USBHS->USBHS_DEVICR = USBHS_DEVICR_Msk;
+  // Disable all interrupts
+  USBHS->USBHS_DEVIDR = USBHS_DEVCTRL_UADD_Msk;
+  // Detach the device
+  USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH;
+  // Disable the device address
+  USBHS->USBHS_DEVCTRL &=~(USBHS_DEVCTRL_ADDEN | USBHS_DEVCTRL_UADD_Msk);
+  __set_PRIMASK(irq_state);
 }
 
 static tusb_speed_t get_speed(void)
 {
-  switch((USBHS->USBHS_SR & USBHS_SR_SPEED_Msk) >> USBHS_SR_SPEED_Pos)
-  {
-      case USBHS_SR_SPEED_FULL_SPEED_Val:
-      default:
-          return TUSB_SPEED_FULL;
-      case USBHS_SR_SPEED_HIGH_SPEED_Val:
-          return TUSB_SPEED_HIGH;
-      case USBHS_SR_SPEED_LOW_SPEED_Val:
-          return TUSB_SPEED_LOW;
+  switch ((USBHS->USBHS_SR & USBHS_SR_SPEED_Msk) >> USBHS_SR_SPEED_Pos) {
+  case USBHS_SR_SPEED_FULL_SPEED_Val:
+  default:
+    return TUSB_SPEED_FULL;
+  case USBHS_SR_SPEED_HIGH_SPEED_Val:
+    return TUSB_SPEED_HIGH;
+  case USBHS_SR_SPEED_LOW_SPEED_Val:
+    return TUSB_SPEED_LOW;
   }
 }
 
 static void dcd_ep_handler(uint8_t ep_ix)
 {
-    uint32_t int_status = USBHS->USBHS_DEVEPTISR[ep_ix] & USBHS->USBHS_DEVEPTIMR[ep_ix];
-    uint32_t dev_ctrl = USBHS->USBHS_DEVCTRL;
-    uint16_t count = (USBHS->USBHS_DEVEPTISR[ep_ix] &
-			  USBHS_DEVEPTISR_BYCT_Msk) >> USBHS_DEVEPTISR_BYCT_Pos;
-    SEGGER_RTT_printf(0, "ep: %u %u %u \r\n", ep_ix, count, int_status);
-    if(ep_ix == 0U)
-    {
-        if (int_status & USBHS_DEVEPTISR_CTRL_RXSTPI) {
-            
-            // Get 8-bit access to endpoint 0 FIFO from USB RAM address 
-            volatile uint8_t *ptr = get_ep_fifo_ptr(0,8);
-            SCB_InvalidateDCache_by_Addr((uint32_t *) ptr, 8);
-            dcd_event_setup_received(0, (uint8_t*)ptr, true);
-            
-            // Acknowledge the interrupt 
-            USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXSTPIC;
-        }
-        if (int_status & USBHS_DEVEPTISR_RXOUTI) {
-            // Disable the interrupt 
-            //USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_RXOUTEC;
-            
-            xfer_ctl_t *xfer = &xfer_status[0];
-            
-            if(count)
-            {
-                volatile uint8_t *ptr = get_ep_fifo_ptr(0,8);
-                for (int i = 0; i < count; i++) {
-                    xfer->buffer[xfer->queued_len + i] = ptr[i];
-                }
-                xfer->queued_len = (uint16_t)(xfer->queued_len + count);
-            }
-            
-            USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXOUTIC;
-            
-            if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
-            {
-                // RX COMPLETE 
-                dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-                xfer->queued_len = 0;
-                SEGGER_RTT_printf(0, "rx: %u \r\n", xfer->queued_len);
-                // Though the host could still send, we don't know.
-            }
-            
-            
-        }
-        if (int_status & USBHS_DEVEPTISR_TXINI) {
-            // Disable the interrupt 
-            USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
-            if (!(dev_ctrl & USBHS_DEVCTRL_ADDEN) &&
-                (dev_ctrl & USBHS_DEVCTRL_UADD_Msk) != 0U) {
-                    // Commit the pending address update.  This
-                    // must be done after the ack to the host
-                    // completes else the ack will get dropped.
-                    USBHS->USBHS_DEVCTRL = dev_ctrl | USBHS_DEVCTRL_ADDEN;
-                }
-            xfer_ctl_t * xfer = &xfer_status[EP_MAX];
-            if((xfer->total_len != xfer->queued_len)) // TX not complete 
-            {
-                dcd_transmit_packet(xfer, 0);
-            }
-            else // TX Complete 
-            {
-                dcd_event_xfer_complete(0, (uint8_t)(0x80 + 0), xfer->total_len, XFER_RESULT_SUCCESS, true);
-            }
-        }
+  uint32_t int_status = USBHS->USBHS_DEVEPTISR[ep_ix];
+  int_status &= USBHS->USBHS_DEVEPTIMR[ep_ix];
+  uint16_t count = (USBHS->USBHS_DEVEPTISR[ep_ix] &
+                    USBHS_DEVEPTISR_BYCT_Msk) >> USBHS_DEVEPTISR_BYCT_Pos;
+  if (ep_ix == 0U) {
+    if (int_status & USBHS_DEVEPTISR_CTRL_RXSTPI) {
+      // Setup packet should always be 8 bytes. If not, ignore it, and try again.
+      if (count == 8)
+      {
+        uint8_t *ptr = get_ep_fifo_ptr(0,8);
+        dcd_event_setup_received(0, ptr, true);
+      }
+      // Acknowledge the interrupt 
+      USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXSTPIC;
     }
-    else
-    {
-        if (int_status & USBHS_DEVEPTISR_RXOUTI) {
-            // Acknowledge the interrupt 
-            USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
-            
-            xfer_ctl_t *xfer = &xfer_status[ep_ix];
-            
-            if(count)
-            {
-                volatile uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
-                for (int i = 0; i < count; i++) {
-                    xfer->buffer[xfer->queued_len + i] = ptr[i];
-                }
-                xfer->queued_len = (uint16_t)(xfer->queued_len + count);
-            }
-            // Clear the FIFO control flag to receive more data.
-            USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
-            if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
-            {
-                // RX COMPLETE 
-                dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-                xfer->queued_len = 0;
-                // Though the host could still send, we don't know.
-            }
-        }
-        if (int_status & USBHS_DEVEPTISR_TXINI) {
-            // Acknowledge the interrupt 
-            USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
-            xfer_ctl_t * xfer = &xfer_status[ep_ix];;
-            if((xfer->total_len != xfer->queued_len)) // TX not complete 
-            {
-                dcd_transmit_packet(xfer, ep_ix);
-            }
-            else // TX Complete 
-            {
-                dcd_event_xfer_complete(0, (uint8_t)(0x80 + ep_ix), xfer->total_len, XFER_RESULT_SUCCESS, true);
-            }
+    if (int_status & USBHS_DEVEPTISR_RXOUTI) {
+      xfer_ctl_t *xfer = &xfer_status[0];
+      if (count) {
+        uint8_t *ptr = get_ep_fifo_ptr(0,8);
+        for (int i = 0; i < count; i++) {
+          xfer->buffer[xfer->queued_len + i] = ptr[i];
         }
+        xfer->queued_len = (uint16_t)(xfer->queued_len + count);
+      }
+      // Acknowledge the interrupt 
+      USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXOUTIC;
+      if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) {
+        // RX COMPLETE 
+        dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+        // Disable the interrupt 
+        USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
+        // Though the host could still send, we don't know.
+      }
     }
+    if (int_status & USBHS_DEVEPTISR_TXINI) {
+      // Disable the interrupt 
+      USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
+      xfer_ctl_t * xfer = &xfer_status[EP_MAX];
+      if ((xfer->total_len != xfer->queued_len)) {
+        // TX not complete 
+        dcd_transmit_packet(xfer, 0);
+      }
+      else {
+        // TX complete 
+        dcd_event_xfer_complete(0, (uint8_t)(0x80 + 0), xfer->total_len, XFER_RESULT_SUCCESS, true);
+      }
+    }
+  }
+  else {
+    if (int_status & USBHS_DEVEPTISR_RXOUTI) { 
+      xfer_ctl_t *xfer = &xfer_status[ep_ix];
+      if (count) {
+        uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
+        memcpy(xfer->buffer + xfer->queued_len, ptr, count);
+        xfer->queued_len = (uint16_t)(xfer->queued_len + count);
+      }
+      // Acknowledge the interrupt 
+      USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
+      // Clear the FIFO control flag to receive more data.
+      USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
+      if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) {
+        // RX COMPLETE 
+        dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+        // Disable the interrupt 
+        USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_RXOUTEC;
+        // Though the host could still send, we don't know.
+      }
+    }
+    if (int_status & USBHS_DEVEPTISR_TXINI) {
+      // Acknowledge the interrupt 
+      USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
+      xfer_ctl_t * xfer = &xfer_status[ep_ix];;
+      if ((xfer->total_len != xfer->queued_len)) {
+        // TX not complete 
+        dcd_transmit_packet(xfer, ep_ix);
+      }
+      else  {
+        // TX complete
+        dcd_event_xfer_complete(0, (uint8_t)(0x80 + ep_ix), xfer->total_len, XFER_RESULT_SUCCESS, true);
+      }
+    }
+  }
 }
 
 void dcd_int_handler(uint8_t rhport)
 {
-    (void) rhport;
-    uint32_t int_status = USBHS->USBHS_DEVISR;
-    // End of reset interrupt 
-    if (int_status & USBHS_DEVISR_EORST) {
-        // Unfreeze USB clock 
-        USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-        while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
-        // Reset all endpoints
-        for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++)
-        {
-            // Disable endpoint interrupt 
-            USBHS->USBHS_DEVIDR = 1 << (USBHS_DEVIDR_PEP_0_Pos + ep_ix);
-            // Disable endpoint and SETUP, IN or OUT interrupts 
-            USBHS->USBHS_DEVEPT &= ~ (1 << (USBHS_DEVEPT_EPEN0_Pos + ep_ix));
-            // Free all endpoint memory 
-            USBHS->USBHS_DEVEPTCFG[ep_ix] &= ~USBHS_DEVEPTCFG_ALLOC;
-        }
-        dcd_edpt_open (0, &ep0_desc);
-        // Acknowledge the End of Reset interrupt 
-        USBHS->USBHS_DEVICR = USBHS_DEVICR_EORSTC;
-        // Acknowledge the Wakeup interrupt 
-        USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
-        // Acknowledge the suspend interrupt 
-        USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
-        // Enable Suspend Interrupt 
-        USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
-        
-        dcd_event_bus_reset(rhport, get_speed(), true);
-    }
-    // End of Wakeup interrupt 
-    if (int_status & USBHS_DEVISR_WAKEUP) {
-        // Unfreeze USB clock 
-        USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-        // Wait to unfreeze clock 
-        while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
-        // Acknowledge the Wakeup interrupt 
-        USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
-        // Disable Wakeup Interrupt 
-        USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC;
-        // Enable Suspend Interrupt 
-        USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
-        
-        dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
-    }
-    // Suspend interrupt 
-    if (int_status & USBHS_DEVISR_SUSP) {
-        // Unfreeze USB clock 
-        USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-         // Wait to unfreeze clock 
-        while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
-        // Acknowledge the suspend interrupt 
-        USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
-        // Disable Suspend Interrupt 
-        USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC;
-        // Enable Wakeup Interrupt 
-        USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES;
-        // Freeze USB clock 
-        USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
-        
-        dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+  (void) rhport;
+  uint32_t int_status = USBHS->USBHS_DEVISR;
+  // End of reset interrupt 
+  if (int_status & USBHS_DEVISR_EORST) {
+    // Unfreeze USB clock 
+    USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
+    while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+    // Reset all endpoints
+    for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++) {
+      USBHS->USBHS_DEVEPT |= 1 << (USBHS_DEVEPT_EPRST0_Pos + ep_ix);
+      USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPRST0_Pos + ep_ix));
     }
+    dcd_edpt_open (0, &ep0_desc);
+    // Acknowledge the End of Reset interrupt 
+    USBHS->USBHS_DEVICR = USBHS_DEVICR_EORSTC;
+    // Acknowledge the Wakeup interrupt 
+    USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
+    // Acknowledge the suspend interrupt 
+    USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
+    // Enable Suspend Interrupt 
+    USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
+    
+    dcd_event_bus_reset(rhport, get_speed(), true);
+  }
+  // End of Wakeup interrupt 
+  if (int_status & USBHS_DEVISR_WAKEUP) {
+    // Unfreeze USB clock 
+    USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
+    // Wait to unfreeze clock 
+    while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+    // Acknowledge the Wakeup interrupt 
+    USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
+    // Disable Wakeup Interrupt 
+    USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC;
+    // Enable Suspend Interrupt 
+    USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
+    
+    dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+  }
+  // Suspend interrupt 
+  if (int_status & USBHS_DEVISR_SUSP) {
+    // Unfreeze USB clock 
+    USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
+    // Wait to unfreeze clock 
+    while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+    // Acknowledge the suspend interrupt 
+    USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
+    // Disable Suspend Interrupt 
+    USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC;
+    // Enable Wakeup Interrupt 
+    USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES;
+    // Freeze USB clock 
+    USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
+    
+    dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+  }
 #if USE_SOF
-    if(int_status & USBHS_DEVISR_SOF) {
-        USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC;
-        
-        dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
-    }
+  if(int_status & USBHS_DEVISR_SOF) {
+    USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC;
+    
+    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+  }
 #endif 
-    // Endpoints interrupt 
-    for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
-        if (int_status & (1 << (USBHS_DEVISR_PEP_0_Pos + ep_ix))) {
-            dcd_ep_handler(ep_ix);
-        }
+  // Endpoints interrupt 
+  for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
+    if (int_status & (1 << (USBHS_DEVISR_PEP_0_Pos + ep_ix))) {
+      dcd_ep_handler(ep_ix);
     }
+  }
 }
 
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  (void) rhport;
+
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS )
+  {
+    uint8_t const dev_addr = (uint8_t) request->wValue;
+    
+    USBHS->USBHS_DEVCTRL |= dev_addr | USBHS_DEVCTRL_ADDEN;
+  }
+}
 
 // Configure endpoint's registers according to descriptor
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 {
-    (void) rhport;
-    uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
-    uint8_t const dir   = tu_edpt_dir(ep_desc->bEndpointAddress);
-    uint16_t const epMaxPktSize = ep_desc->wMaxPacketSize.size;
-    tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
-    uint8_t fifoSize = 0;                       // FIFO size 
-    uint16_t defaultEndpointSize = 8;           // Default size of Endpoint 
-    // Find upper 2 power number of epMaxPktSize 
-    if(epMaxPktSize)
-    {
-        while (defaultEndpointSize < epMaxPktSize)
-        {
-            fifoSize++;
-            defaultEndpointSize <<= 1;
-        }
+  (void) rhport;
+  uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
+  uint8_t const dir   = tu_edpt_dir(ep_desc->bEndpointAddress);
+  uint16_t const epMaxPktSize = ep_desc->wMaxPacketSize.size;
+  tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
+  uint8_t fifoSize = 0;                       // FIFO size 
+  uint16_t defaultEndpointSize = 8;           // Default size of Endpoint 
+  // Find upper 2 power number of epMaxPktSize 
+  if (epMaxPktSize) {
+    while (defaultEndpointSize < epMaxPktSize) {
+      fifoSize++;
+      defaultEndpointSize <<= 1;
     }
-    xfer_status[epnum].max_packet_size = epMaxPktSize;
+  }
+  xfer_status[epnum].max_packet_size = epMaxPktSize;
+  
+  USBHS->USBHS_DEVEPT |= 1 << (USBHS_DEVEPT_EPRST0_Pos + epnum);
+  USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPRST0_Pos + epnum));
     
-    if(epnum == 0)
-    {
-        xfer_status[EP_MAX].max_packet_size = epMaxPktSize;
-        // Enable the control endpoint - Endpoint 0 
-        USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
-        // Configure the Endpoint 0 configuration register 
-        USBHS->USBHS_DEVEPTCFG[0] =
-        (
-             USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
-             USBHS_DEVEPTCFG_EPTYPE(TUSB_XFER_CONTROL) |
-             USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
-             USBHS_DEVEPTCFG_ALLOC
-         );
-        USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RSTDTS;
-        USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_STALLRQC;
-        if(USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK))
-        {
-            // Endpoint configuration is successful 
-            USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RXSTPES  | USBHS_DEVEPTIER_RXOUTES;
-            // Enable Endpoint 0 Interrupts 
-            USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
-            return true;
-        }
-        else
-        {
-            // Endpoint configuration is not successful 
-            return false;
-        }
+  if (epnum == 0) {
+    xfer_status[EP_MAX].max_packet_size = epMaxPktSize;
+    // Enable the control endpoint - Endpoint 0 
+    USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
+    // Configure the Endpoint 0 configuration register 
+    USBHS->USBHS_DEVEPTCFG[0] =
+      (
+       USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
+       USBHS_DEVEPTCFG_EPTYPE(TUSB_XFER_CONTROL) |
+       USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
+       USBHS_DEVEPTCFG_ALLOC
+      );
+    USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RSTDTS;
+    USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_STALLRQC;
+    if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK)) {
+      // Endpoint configuration is successful 
+      USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RXSTPES;
+      // Enable Endpoint 0 Interrupts 
+      USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
+      return true;
     }
-    else
-    {
-        // Enable the endpoint 
-        USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
-        // Set up the maxpacket size, fifo start address fifosize
-        // and enable the interrupt. CLear the data toggle. 
-        USBHS->USBHS_DEVEPTCFG[epnum] =
-        (
-            USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
-            USBHS_DEVEPTCFG_EPTYPE(eptype) |
-            USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
-            USBHS_DEVEPTCFG_ALLOC |
-            ((dir & 0x01) << USBHS_DEVEPTCFG_EPDIR_Pos)
-        );
-        
-        if (eptype == TUSB_XFER_ISOCHRONOUS)
-        {
-            USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1); 
-        }
-        USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RSTDTS;
-        USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
-        if(USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK))
-        {
-            // Endpoint configuration is successful. Enable Endpoint Interrupts
-            if(dir == TUSB_DIR_OUT)
-            {
-                USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
-            }
-            else
-            {
-                USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_TXINIC;
+    else {
+      // Endpoint configuration is not successful 
+      return false;
+    }
+  }
+  else {
+    // Enable the endpoint 
+    USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
+    // Set up the maxpacket size, fifo start address fifosize
+    // and enable the interrupt. CLear the data toggle. 
+    USBHS->USBHS_DEVEPTCFG[epnum] =
+      (
+       USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
+       USBHS_DEVEPTCFG_EPTYPE(eptype) |
+       USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
+       ((dir & 0x01) << USBHS_DEVEPTCFG_EPDIR_Pos)
+      );
+    
+    if (eptype == TUSB_XFER_ISOCHRONOUS){
+      USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1) | USBHS_DEVEPTCFG_EPBK_2_BANK; 
+    }
+    USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_ALLOC;
+    USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RSTDTS;
+    USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
+    if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK)) {
+      // Endpoint configuration is successful. Enable Endpoint Interrupts
+      if (dir == TUSB_DIR_IN) {
+        USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_TXINIC;
 		USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_TXINES;
-            }
-            USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
-            return true;
-        }
-        else
-        {
-            // Endpoint configuration is not successful 
-            return false;
-        }
+      }
+      USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
+      return true;
     }
+    else {
+      // Endpoint configuration is not successful 
+      return false;
+    }
+  }
 }
 
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
 {
-    uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
-    
-    if(len > xfer->max_packet_size) // max packet size for FS transfer
-    {
-        len = xfer->max_packet_size;
-    }
-    
-    volatile uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
-    for (int i = 0; i < len; i++) {
-        ptr[i] = xfer->buffer[xfer->queued_len + i];
-    }
-
-    xfer->queued_len = (uint16_t)(xfer->queued_len + len);
-    
-    if (ep_ix == 0U) {
-        
-        // Control endpoint: clear the interrupt flag to send the data,
-        // and re-enable the interrupts to trigger an interrupt at the
-        // end of the transfer.
-        USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
-        USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_TXINES;
-    } else {
-        
-        // Other endpoint types: clear the FIFO control flag to send the data.
-        USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
-    }
+  uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
+  
+  if (len > xfer->max_packet_size) {
+    len = xfer->max_packet_size;
+  }
+  
+  uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
+  memcpy(ptr, xfer->buffer + xfer->queued_len, len);
+  
+  xfer->queued_len = (uint16_t)(xfer->queued_len + len);
+  
+  if (ep_ix == 0U) {
+    // Control endpoint: clear the interrupt flag to send the data,
+    // and re-enable the interrupts to trigger an interrupt at the
+    // end of the transfer.
+    USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
+    USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_TXINES;
+  } else {
+    // Other endpoint types: clear the FIFO control flag to send the data.
+    USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
+  }
 }
 
-
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
-    (void) rhport;
-    
-    uint8_t const epnum = tu_edpt_number(ep_addr);
-    uint8_t const dir   = tu_edpt_dir(ep_addr);
-    
-    xfer_ctl_t * xfer = &xfer_status[epnum];
-    if(ep_addr == 0x80)
-        xfer = &xfer_status[EP_MAX];
-    
-    xfer->buffer = buffer;
-    xfer->total_len = total_bytes;
-    xfer->queued_len = 0;
-    
-    SEGGER_RTT_printf(0, "xfer: %u %u %u \r\n", epnum, dir, total_bytes);
-    
-    if ( dir == TUSB_DIR_OUT )
-    {
-        // Endpoint configuration is successful 
-        // Acknowledge the interrupt 
-        //USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_RXOUTIC;
-        
-        //USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
-    }
-    else // IN
-    {
-        dcd_transmit_packet(xfer,epnum);
-    }
-    return true;
+  (void) rhport;
+  
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  
+  xfer_ctl_t * xfer = &xfer_status[epnum];
+  if(ep_addr == 0x80)
+    xfer = &xfer_status[EP_MAX];
+  
+  xfer->buffer = buffer;
+  xfer->total_len = total_bytes;
+  xfer->queued_len = 0;
+  
+  if (dir == TUSB_DIR_OUT){
+    USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
+  }
+  else {
+    dcd_transmit_packet(xfer,epnum);
+  }
+  return true;
 }
 
 // Stall endpoint
 void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
-    (void) rhport;
-    uint8_t const epnum = tu_edpt_number(ep_addr);
-    USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_STALLRQS;
+  (void) rhport;
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_STALLRQS;
 }
 
 // clear stall, data toggle is also reset to DATA0
 void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
-    (void) rhport;
-    uint8_t const epnum = tu_edpt_number(ep_addr);
-    USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
-    USBHS->USBHS_DEVEPTIER[epnum] = USBHS_HSTPIPIER_RSTDTS;
+  (void) rhport;
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
+  USBHS->USBHS_DEVEPTIER[epnum] = USBHS_HSTPIPIER_RSTDTS;
 }
 
 #endif

From 1dafcd1132deb10c824a0587b333e646b102e8aa Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 5 Mar 2021 17:15:02 +0100
Subject: [PATCH 0047/2085] - Add Full Speed switch - Add DMA support - Add
 Dual bank support

Signed-off-by: HiFiPhile <admin@hifiphile.com>
---
 src/portable/microchip/same70/dcd_same70.c | 145 ++++++++++++++++-----
 1 file changed, 111 insertions(+), 34 deletions(-)

diff --git a/src/portable/microchip/same70/dcd_same70.c b/src/portable/microchip/same70/dcd_same70.c
index 98fe61360..89ef63660 100644
--- a/src/portable/microchip/same70/dcd_same70.c
+++ b/src/portable/microchip/same70/dcd_same70.c
@@ -34,7 +34,6 @@
 #include "device/dcd.h"
 
 #include "sam.h"
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
@@ -42,17 +41,29 @@
 // Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
 // We disable SOF for now until needed later on
 #ifndef USE_SOF
-#  define USE_SOF     0
+#  define USE_SOF         0
 #endif
 
-#ifndef USBHS_RAM_ADDR
-#  define USBHS_RAM_ADDR        0xA0100000u
+// Dual bank can imporve performance, but need 2 times bigger packet buffer
+// As SAME70 has only 4KB packet buffer, use with caution !
+// Enable in FS mode as packets are smaller
+#ifndef USE_DUAL_BANK
+#  if TUD_OPT_HIGH_SPEED
+#    define USE_DUAL_BANK   0
+#  else
+#    define USE_DUAL_BANK   1
+#  endif
 #endif
 
-#define get_ep_fifo_ptr(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
-
 #define EP_MAX            10
 
+#define USBHS_RAM_ADDR  0xA0100000u
+
+#define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
+
+// Errata: The DMA feature is not available for Pipe/Endpoint 7
+#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)
+
 typedef struct {
   uint8_t * buffer;
   uint16_t total_len;
@@ -82,9 +93,12 @@ void dcd_init (uint8_t rhport)
   PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
   // Wait until USB UTMI stabilize
   while (!(PMC->PMC_SR & PMC_SR_LOCKU));
+#if !TUD_OPT_HIGH_SPEED
   // Enable USB FS clk
+  PMC->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2;
   PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
   PMC->PMC_SCER = PMC_SCER_USBCLK;
+#endif
   dcd_connect(rhport);
 }
 
@@ -128,10 +142,12 @@ void dcd_connect(uint8_t rhport)
   PMC->PMC_PCER1 = 1 << (ID_USBHS - 32);
   // Enable the USB controller in device mode
   USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE;
-  // Wait to unfreeze clock
-  while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
-  // Attach the device
-  USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH;
+  while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+#if TUD_OPT_HIGH_SPEED
+  USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_SPDCONF_Msk;
+#else
+  USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_LOW_POWER;
+#endif
   // Enable the End Of Reset, Suspend & Wakeup interrupts
   USBHS->USBHS_DEVIER = (USBHS_DEVIER_EORSTES | USBHS_DEVIER_SUSPES | USBHS_DEVIER_WAKEUPES);
 #if USE_SOF
@@ -143,6 +159,8 @@ void dcd_connect(uint8_t rhport)
   USBHS->USBHS_DEVIFR |= USBHS_DEVIFR_SUSPS;
   // Ack the Wakeup Interrupt
   USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
+  // Attach the device
+  USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH;
   // Freeze USB clock
   USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
   __set_PRIMASK(irq_state);
@@ -158,7 +176,6 @@ void dcd_disconnect(uint8_t rhport)
   USBHS->USBHS_DEVEPT &= ~(0x3FF << USBHS_DEVEPT_EPEN0_Pos);
   // Unfreeze USB clock
   USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-  // Wait to unfreeze clock
   while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
   // Clear all the pending interrupts
   USBHS->USBHS_DEVICR = USBHS_DEVICR_Msk;
@@ -195,7 +212,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       // Setup packet should always be 8 bytes. If not, ignore it, and try again.
       if (count == 8)
       {
-        uint8_t *ptr = get_ep_fifo_ptr(0,8);
+        uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
         dcd_event_setup_received(0, ptr, true);
       }
       // Acknowledge the interrupt 
@@ -204,7 +221,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
     if (int_status & USBHS_DEVEPTISR_RXOUTI) {
       xfer_ctl_t *xfer = &xfer_status[0];
       if (count) {
-        uint8_t *ptr = get_ep_fifo_ptr(0,8);
+        uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
         for (int i = 0; i < count; i++) {
           xfer->buffer[xfer->queued_len + i] = ptr[i];
         }
@@ -230,7 +247,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       }
       else {
         // TX complete 
-        dcd_event_xfer_complete(0, (uint8_t)(0x80 + 0), xfer->total_len, XFER_RESULT_SUCCESS, true);
+        dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
       }
     }
   }
@@ -238,7 +255,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
     if (int_status & USBHS_DEVEPTISR_RXOUTI) { 
       xfer_ctl_t *xfer = &xfer_status[ep_ix];
       if (count) {
-        uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
+        uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
         memcpy(xfer->buffer + xfer->queued_len, ptr, count);
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
@@ -264,12 +281,34 @@ static void dcd_ep_handler(uint8_t ep_ix)
       }
       else  {
         // TX complete
-        dcd_event_xfer_complete(0, (uint8_t)(0x80 + ep_ix), xfer->total_len, XFER_RESULT_SUCCESS, true);
+        dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
+        USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_TXINEC;
       }
     }
   }
 }
 
+static void dcd_dma_handler(uint8_t ep_ix)
+{
+  uint32_t status = USBHS->UsbhsDevdma[ep_ix - 1].USBHS_DEVDMASTATUS;
+  if (status & USBHS_DEVDMASTATUS_CHANN_ENB) {
+    return; // Ignore EOT_STA interrupt
+  }
+  // Disable DMA interrupt
+  USBHS->USBHS_DEVIDR = USBHS_DEVIDR_DMA_1 << (ep_ix - 1);
+  
+  xfer_ctl_t *xfer = &xfer_status[ep_ix];
+  uint16_t count = xfer->total_len - ((status & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos);
+  if(USBHS->USBHS_DEVEPTCFG[ep_ix] & USBHS_DEVEPTCFG_EPDIR)
+  {
+    dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
+  }
+  else
+  {
+    dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
+  }
+}
+
 void dcd_int_handler(uint8_t rhport)
 {
   (void) rhport;
@@ -337,10 +376,18 @@ void dcd_int_handler(uint8_t rhport)
 #endif 
   // Endpoints interrupt 
   for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
-    if (int_status & (1 << (USBHS_DEVISR_PEP_0_Pos + ep_ix))) {
+    if (int_status & (USBHS_DEVISR_PEP_0 << ep_ix)) {
       dcd_ep_handler(ep_ix);
     }
   }
+  // Endpoints DMA interrupt 
+  for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
+    if (EP_DMA_SUPPORT(ep_ix)) {
+      if (int_status & (USBHS_DEVISR_DMA_1 << (ep_ix - 1))) {
+        dcd_dma_handler(ep_ix);
+      }
+    }
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -415,26 +462,27 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
     // Set up the maxpacket size, fifo start address fifosize
     // and enable the interrupt. CLear the data toggle. 
+    // AUTOSW is needed for DMA ack !
     USBHS->USBHS_DEVEPTCFG[epnum] =
       (
        USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
        USBHS_DEVEPTCFG_EPTYPE(eptype) |
        USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
+       USBHS_DEVEPTCFG_AUTOSW |
        ((dir & 0x01) << USBHS_DEVEPTCFG_EPDIR_Pos)
       );
-    
     if (eptype == TUSB_XFER_ISOCHRONOUS){
-      USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1) | USBHS_DEVEPTCFG_EPBK_2_BANK; 
+      USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1); 
     }
+#if USE_DUAL_BANK
+    if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK){
+      USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_EPBK_2_BANK; 
+    }
+#endif
     USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_ALLOC;
     USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RSTDTS;
     USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
     if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK)) {
-      // Endpoint configuration is successful. Enable Endpoint Interrupts
-      if (dir == TUSB_DIR_IN) {
-        USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_TXINIC;
-		USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_TXINES;
-      }
       USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
       return true;
     }
@@ -453,28 +501,26 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
     len = xfer->max_packet_size;
   }
   
-  uint8_t *ptr = get_ep_fifo_ptr(ep_ix,8);
+  uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
   memcpy(ptr, xfer->buffer + xfer->queued_len, len);
   
   xfer->queued_len = (uint16_t)(xfer->queued_len + len);
   
   if (ep_ix == 0U) {
-    // Control endpoint: clear the interrupt flag to send the data,
-    // and re-enable the interrupts to trigger an interrupt at the
-    // end of the transfer.
+    // Control endpoint: clear the interrupt flag to send the data
     USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
-    USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_TXINES;
+    
   } else {
-    // Other endpoint types: clear the FIFO control flag to send the data.
+    // Other endpoint types: clear the FIFO control flag to send the data
     USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
   }
+  USBHS->USBHS_DEVEPTIER[ep_ix] = USBHS_DEVEPTIER_TXINES;
 }
 
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
   (void) rhport;
-  
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
   
@@ -486,11 +532,42 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
   
-  if (dir == TUSB_DIR_OUT){
-    USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
+  if(EP_DMA_SUPPORT(epnum) && total_bytes != 0) {
+    uint32_t udd_dma_ctrl = 0;
+    udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
+    if (dir == TUSB_DIR_OUT){
+      udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_TR_IT | USBHS_DEVDMACONTROL_END_TR_EN;
+    }
+    else {
+      udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_B_EN;
+    }
+    // Start USB DMA to fill or read fifo of the selected endpoint
+		USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)buffer;
+		udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_BUFFIT | USBHS_DEVDMACONTROL_CHANN_ENB;
+    // Disable IRQs to have a short sequence
+		// between read of EOT_STA and DMA enable
+		uint32_t irq_state = __get_PRIMASK();
+    __disable_irq();
+		if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST)) {
+      USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMACONTROL = udd_dma_ctrl;
+			USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << (epnum - 1);
+			__set_PRIMASK(irq_state);
+			return true;
+		}
+		__set_PRIMASK(irq_state);
+
+		// Here a ZLP has been recieved
+		// and the DMA transfer must be not started.
+		// It is the end of transfer
+    return false;
   }
   else {
-    dcd_transmit_packet(xfer,epnum);
+    if (dir == TUSB_DIR_OUT){
+      USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
+    }
+    else {
+      dcd_transmit_packet(xfer,epnum);
+    }
   }
   return true;
 }

From 24de9d39af9c7f015dc00295a1d9f8c5bf428d34 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Thu, 11 Mar 2021 20:47:53 +0100
Subject: [PATCH 0048/2085] Format.

---
 src/portable/microchip/same70/dcd_same70.c | 155 +++++++++++++--------
 1 file changed, 95 insertions(+), 60 deletions(-)

diff --git a/src/portable/microchip/same70/dcd_same70.c b/src/portable/microchip/same70/dcd_same70.c
index 89ef63660..72d91e466 100644
--- a/src/portable/microchip/same70/dcd_same70.c
+++ b/src/portable/microchip/same70/dcd_same70.c
@@ -25,8 +25,6 @@
 * This file is part of the TinyUSB stack.
 */
 
-
-
 #include "tusb_option.h"
 
 #if CFG_TUSB_MCU == OPT_MCU_SAME70
@@ -207,8 +205,10 @@ static void dcd_ep_handler(uint8_t ep_ix)
   int_status &= USBHS->USBHS_DEVEPTIMR[ep_ix];
   uint16_t count = (USBHS->USBHS_DEVEPTISR[ep_ix] &
                     USBHS_DEVEPTISR_BYCT_Msk) >> USBHS_DEVEPTISR_BYCT_Pos;
-  if (ep_ix == 0U) {
-    if (int_status & USBHS_DEVEPTISR_CTRL_RXSTPI) {
+  if (ep_ix == 0U)
+  {
+    if (int_status & USBHS_DEVEPTISR_CTRL_RXSTPI)
+    {
       // Setup packet should always be 8 bytes. If not, ignore it, and try again.
       if (count == 8)
       {
@@ -218,18 +218,22 @@ static void dcd_ep_handler(uint8_t ep_ix)
       // Acknowledge the interrupt 
       USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXSTPIC;
     }
-    if (int_status & USBHS_DEVEPTISR_RXOUTI) {
+    if (int_status & USBHS_DEVEPTISR_RXOUTI)
+    {
       xfer_ctl_t *xfer = &xfer_status[0];
-      if (count) {
+      if (count)
+      {
         uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
-        for (int i = 0; i < count; i++) {
+        for (int i = 0; i < count; i++)
+        {
           xfer->buffer[xfer->queued_len + i] = ptr[i];
         }
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
       // Acknowledge the interrupt 
       USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXOUTIC;
-      if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) {
+      if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
+      {
         // RX COMPLETE 
         dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt 
@@ -237,24 +241,28 @@ static void dcd_ep_handler(uint8_t ep_ix)
         // Though the host could still send, we don't know.
       }
     }
-    if (int_status & USBHS_DEVEPTISR_TXINI) {
+    if (int_status & USBHS_DEVEPTISR_TXINI)
+    {
       // Disable the interrupt 
       USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
       xfer_ctl_t * xfer = &xfer_status[EP_MAX];
-      if ((xfer->total_len != xfer->queued_len)) {
+      if ((xfer->total_len != xfer->queued_len))
+      {
         // TX not complete 
         dcd_transmit_packet(xfer, 0);
-      }
-      else {
+      } else 
+      {
         // TX complete 
         dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
       }
     }
-  }
-  else {
-    if (int_status & USBHS_DEVEPTISR_RXOUTI) { 
+  } else
+  {
+    if (int_status & USBHS_DEVEPTISR_RXOUTI)
+    { 
       xfer_ctl_t *xfer = &xfer_status[ep_ix];
-      if (count) {
+      if (count)
+      {
         uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
         memcpy(xfer->buffer + xfer->queued_len, ptr, count);
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
@@ -263,7 +271,8 @@ static void dcd_ep_handler(uint8_t ep_ix)
       USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
       // Clear the FIFO control flag to receive more data.
       USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
-      if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) {
+      if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
+      {
         // RX COMPLETE 
         dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt 
@@ -271,15 +280,17 @@ static void dcd_ep_handler(uint8_t ep_ix)
         // Though the host could still send, we don't know.
       }
     }
-    if (int_status & USBHS_DEVEPTISR_TXINI) {
+    if (int_status & USBHS_DEVEPTISR_TXINI)
+    {
       // Acknowledge the interrupt 
       USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
       xfer_ctl_t * xfer = &xfer_status[ep_ix];;
-      if ((xfer->total_len != xfer->queued_len)) {
+      if ((xfer->total_len != xfer->queued_len))
+      {
         // TX not complete 
         dcd_transmit_packet(xfer, ep_ix);
-      }
-      else  {
+      } else
+      {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
         USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_TXINEC;
@@ -291,7 +302,8 @@ static void dcd_ep_handler(uint8_t ep_ix)
 static void dcd_dma_handler(uint8_t ep_ix)
 {
   uint32_t status = USBHS->UsbhsDevdma[ep_ix - 1].USBHS_DEVDMASTATUS;
-  if (status & USBHS_DEVDMASTATUS_CHANN_ENB) {
+  if (status & USBHS_DEVDMASTATUS_CHANN_ENB)
+  {
     return; // Ignore EOT_STA interrupt
   }
   // Disable DMA interrupt
@@ -302,8 +314,7 @@ static void dcd_dma_handler(uint8_t ep_ix)
   if(USBHS->USBHS_DEVEPTCFG[ep_ix] & USBHS_DEVEPTCFG_EPDIR)
   {
     dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
-  }
-  else
+  } else
   {
     dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
   }
@@ -314,12 +325,14 @@ void dcd_int_handler(uint8_t rhport)
   (void) rhport;
   uint32_t int_status = USBHS->USBHS_DEVISR;
   // End of reset interrupt 
-  if (int_status & USBHS_DEVISR_EORST) {
+  if (int_status & USBHS_DEVISR_EORST)
+  {
     // Unfreeze USB clock 
     USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
     while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
     // Reset all endpoints
-    for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++) {
+    for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++)
+    {
       USBHS->USBHS_DEVEPT |= 1 << (USBHS_DEVEPT_EPRST0_Pos + ep_ix);
       USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPRST0_Pos + ep_ix));
     }
@@ -336,7 +349,8 @@ void dcd_int_handler(uint8_t rhport)
     dcd_event_bus_reset(rhport, get_speed(), true);
   }
   // End of Wakeup interrupt 
-  if (int_status & USBHS_DEVISR_WAKEUP) {
+  if (int_status & USBHS_DEVISR_WAKEUP)
+  {
     // Unfreeze USB clock 
     USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
     // Wait to unfreeze clock 
@@ -351,7 +365,8 @@ void dcd_int_handler(uint8_t rhport)
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
   }
   // Suspend interrupt 
-  if (int_status & USBHS_DEVISR_SUSP) {
+  if (int_status & USBHS_DEVISR_SUSP)
+  {
     // Unfreeze USB clock 
     USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
     // Wait to unfreeze clock 
@@ -368,22 +383,28 @@ void dcd_int_handler(uint8_t rhport)
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 #if USE_SOF
-  if(int_status & USBHS_DEVISR_SOF) {
+  if(int_status & USBHS_DEVISR_SOF)
+  {
     USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC;
     
     dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
   }
 #endif 
   // Endpoints interrupt 
-  for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
-    if (int_status & (USBHS_DEVISR_PEP_0 << ep_ix)) {
+  for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
+  {
+    if (int_status & (USBHS_DEVISR_PEP_0 << ep_ix))
+    {
       dcd_ep_handler(ep_ix);
     }
   }
   // Endpoints DMA interrupt 
-  for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) {
-    if (EP_DMA_SUPPORT(ep_ix)) {
-      if (int_status & (USBHS_DEVISR_DMA_1 << (ep_ix - 1))) {
+  for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
+  {
+    if (EP_DMA_SUPPORT(ep_ix))
+    {
+      if (int_status & (USBHS_DEVISR_DMA_1 << (ep_ix - 1)))
+      {
         dcd_dma_handler(ep_ix);
       }
     }
@@ -420,8 +441,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   uint8_t fifoSize = 0;                       // FIFO size 
   uint16_t defaultEndpointSize = 8;           // Default size of Endpoint 
   // Find upper 2 power number of epMaxPktSize 
-  if (epMaxPktSize) {
-    while (defaultEndpointSize < epMaxPktSize) {
+  if (epMaxPktSize)
+  {
+    while (defaultEndpointSize < epMaxPktSize)
+    {
       fifoSize++;
       defaultEndpointSize <<= 1;
     }
@@ -431,7 +454,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   USBHS->USBHS_DEVEPT |= 1 << (USBHS_DEVEPT_EPRST0_Pos + epnum);
   USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPRST0_Pos + epnum));
     
-  if (epnum == 0) {
+  if (epnum == 0) 
+  {
     xfer_status[EP_MAX].max_packet_size = epMaxPktSize;
     // Enable the control endpoint - Endpoint 0 
     USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
@@ -445,19 +469,20 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
       );
     USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RSTDTS;
     USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_STALLRQC;
-    if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK)) {
+    if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK))
+    {
       // Endpoint configuration is successful 
       USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RXSTPES;
       // Enable Endpoint 0 Interrupts 
       USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
       return true;
-    }
-    else {
+    } else
+    {
       // Endpoint configuration is not successful 
       return false;
     }
-  }
-  else {
+  } else
+  {
     // Enable the endpoint 
     USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
     // Set up the maxpacket size, fifo start address fifosize
@@ -471,22 +496,25 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
        USBHS_DEVEPTCFG_AUTOSW |
        ((dir & 0x01) << USBHS_DEVEPTCFG_EPDIR_Pos)
       );
-    if (eptype == TUSB_XFER_ISOCHRONOUS){
+    if (eptype == TUSB_XFER_ISOCHRONOUS)
+    {
       USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1); 
     }
 #if USE_DUAL_BANK
-    if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK){
+    if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK)
+    {
       USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_EPBK_2_BANK; 
     }
 #endif
     USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_ALLOC;
     USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RSTDTS;
     USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
-    if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK)) {
+    if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK))
+    {
       USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
       return true;
-    }
-    else {
+    } else
+    {
       // Endpoint configuration is not successful 
       return false;
     }
@@ -497,7 +525,8 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
 {
   uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
   
-  if (len > xfer->max_packet_size) {
+  if (len > xfer->max_packet_size)
+  {
     len = xfer->max_packet_size;
   }
   
@@ -506,11 +535,13 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
   
   xfer->queued_len = (uint16_t)(xfer->queued_len + len);
   
-  if (ep_ix == 0U) {
+  if (ep_ix == 0U)
+  {
     // Control endpoint: clear the interrupt flag to send the data
     USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
     
-  } else {
+  } else 
+  {
     // Other endpoint types: clear the FIFO control flag to send the data
     USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
   }
@@ -532,13 +563,15 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
   
-  if(EP_DMA_SUPPORT(epnum) && total_bytes != 0) {
+  if(EP_DMA_SUPPORT(epnum) && total_bytes != 0)
+  {
     uint32_t udd_dma_ctrl = 0;
     udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
-    if (dir == TUSB_DIR_OUT){
+    if (dir == TUSB_DIR_OUT)
+    {
       udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_TR_IT | USBHS_DEVDMACONTROL_END_TR_EN;
-    }
-    else {
+    } else
+    {
       udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_B_EN;
     }
     // Start USB DMA to fill or read fifo of the selected endpoint
@@ -548,7 +581,8 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 		// between read of EOT_STA and DMA enable
 		uint32_t irq_state = __get_PRIMASK();
     __disable_irq();
-		if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST)) {
+		if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST))
+    {
       USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMACONTROL = udd_dma_ctrl;
 			USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << (epnum - 1);
 			__set_PRIMASK(irq_state);
@@ -560,12 +594,13 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 		// and the DMA transfer must be not started.
 		// It is the end of transfer
     return false;
-  }
-  else {
-    if (dir == TUSB_DIR_OUT){
+  } else
+  {
+    if (dir == TUSB_DIR_OUT)
+    {
       USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
-    }
-    else {
+    } else
+    {
       dcd_transmit_packet(xfer,epnum);
     }
   }

From c291deccfac7725a4e1f26357e133f32887e65aa Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 11 Jun 2021 12:14:14 +0200
Subject: [PATCH 0049/2085] Add fifo & DMA linked list mode support.

---
 examples/device/cdc_msc/src/tusb_config.h     |   2 +-
 examples/device/cdc_msc/src/usb_descriptors.c |   4 +-
 src/portable/microchip/same70/dcd_same70.c    | 177 +++++++++++++-----
 3 files changed, 132 insertions(+), 51 deletions(-)

diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index 9a0262d30..f9e98b0f7 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -48,7 +48,7 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAME70)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index fa4342165..46b57f7e2 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -94,8 +94,8 @@ enum
   #define EPNUM_MSC_OUT     0x05
   #define EPNUM_MSC_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG
-  // SAMG doesn't support a same endpoint number with different direction IN and OUT
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAME70
+  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_NOTIF   0x81
   #define EPNUM_CDC_OUT     0x02
diff --git a/src/portable/microchip/same70/dcd_same70.c b/src/portable/microchip/same70/dcd_same70.c
index 72d91e466..eb716182d 100644
--- a/src/portable/microchip/same70/dcd_same70.c
+++ b/src/portable/microchip/same70/dcd_same70.c
@@ -62,14 +62,33 @@
 // Errata: The DMA feature is not available for Pipe/Endpoint 7
 #define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)
 
+// DMA Channel Transfer Descriptor
+typedef struct {
+  volatile uint32_t next_desc;
+  volatile uint32_t buff_addr;
+  volatile uint32_t chnl_ctrl;
+  uint32_t padding;
+} dma_desc_t;
+
+// Transfer control context
 typedef struct {
   uint8_t * buffer;
   uint16_t total_len;
   uint16_t queued_len;
   uint16_t max_packet_size;
   uint8_t interval;
+  tu_fifo_t * fifo;
 } xfer_ctl_t;
 
+static tusb_speed_t get_speed(void);
+static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
+
+// DMA descriptors shouldn't be placed in ITCM
+#if defined(USB_DMA_DESC_SECTION)
+TU_ATTR_SECTION(TU_XSTRING(USB_DMA_DESC_SECTION))
+#endif
+dma_desc_t dma_desc[6];
+
 xfer_ctl_t xfer_status[EP_MAX+1];
 
 static const tusb_desc_endpoint_t ep0_desc =
@@ -78,8 +97,6 @@ static const tusb_desc_endpoint_t ep0_desc =
   .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
 };
 
-static tusb_speed_t get_speed(void);
-static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
 //------------------------------------------------------------------
 // Device API
 //------------------------------------------------------------------
@@ -224,9 +241,11 @@ static void dcd_ep_handler(uint8_t ep_ix)
       if (count)
       {
         uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
-        for (int i = 0; i < count; i++)
+        if (xfer->buffer)
         {
-          xfer->buffer[xfer->queued_len + i] = ptr[i];
+          memcpy(xfer->buffer + xfer->queued_len, ptr, count);
+        } else {
+          tu_fifo_write_n(xfer->fifo, ptr, count);
         }
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
@@ -250,21 +269,24 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX not complete 
         dcd_transmit_packet(xfer, 0);
-      } else 
-      {
+      } else {
         // TX complete 
         dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
       }
     }
-  } else
-  {
+  } else {
     if (int_status & USBHS_DEVEPTISR_RXOUTI)
     { 
       xfer_ctl_t *xfer = &xfer_status[ep_ix];
       if (count)
       {
         uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
-        memcpy(xfer->buffer + xfer->queued_len, ptr, count);
+        if (xfer->buffer)
+        {
+          memcpy(xfer->buffer + xfer->queued_len, ptr, count);
+        } else {
+          tu_fifo_write_n(xfer->fifo, ptr, count);
+        }
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
       // Acknowledge the interrupt 
@@ -289,8 +311,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX not complete 
         dcd_transmit_packet(xfer, ep_ix);
-      } else
-      {
+      } else {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
         USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_TXINEC;
@@ -314,8 +335,7 @@ static void dcd_dma_handler(uint8_t ep_ix)
   if(USBHS->USBHS_DEVEPTCFG[ep_ix] & USBHS_DEVEPTCFG_EPDIR)
   {
     dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
-  } else
-  {
+  } else {
     dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
   }
 }
@@ -337,13 +357,9 @@ void dcd_int_handler(uint8_t rhport)
       USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPRST0_Pos + ep_ix));
     }
     dcd_edpt_open (0, &ep0_desc);
-    // Acknowledge the End of Reset interrupt 
     USBHS->USBHS_DEVICR = USBHS_DEVICR_EORSTC;
-    // Acknowledge the Wakeup interrupt 
     USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
-    // Acknowledge the suspend interrupt 
     USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
-    // Enable Suspend Interrupt 
     USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
     
     dcd_event_bus_reset(rhport, get_speed(), true);
@@ -351,15 +367,10 @@ void dcd_int_handler(uint8_t rhport)
   // End of Wakeup interrupt 
   if (int_status & USBHS_DEVISR_WAKEUP)
   {
-    // Unfreeze USB clock 
     USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-    // Wait to unfreeze clock 
     while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
-    // Acknowledge the Wakeup interrupt 
     USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
-    // Disable Wakeup Interrupt 
     USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC;
-    // Enable Suspend Interrupt 
     USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
     
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
@@ -369,15 +380,10 @@ void dcd_int_handler(uint8_t rhport)
   {
     // Unfreeze USB clock 
     USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-    // Wait to unfreeze clock 
     while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
-    // Acknowledge the suspend interrupt 
     USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
-    // Disable Suspend Interrupt 
     USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC;
-    // Enable Wakeup Interrupt 
     USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES;
-    // Freeze USB clock 
     USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
     
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
@@ -476,13 +482,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
       // Enable Endpoint 0 Interrupts 
       USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
       return true;
-    } else
-    {
+    } else {
       // Endpoint configuration is not successful 
       return false;
     }
-  } else
-  {
+  } else {
     // Enable the endpoint 
     USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
     // Set up the maxpacket size, fifo start address fifosize
@@ -513,8 +517,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     {
       USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
       return true;
-    } else
-    {
+    } else {
       // Endpoint configuration is not successful 
       return false;
     }
@@ -524,24 +527,25 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
 {
   uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
-  
   if (len > xfer->max_packet_size)
   {
     len = xfer->max_packet_size;
   }
-  
   uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
-  memcpy(ptr, xfer->buffer + xfer->queued_len, len);
-  
+  if(xfer->buffer)
+  {
+    memcpy(ptr, xfer->buffer + xfer->queued_len, len);
+  }
+  else {
+    tu_fifo_read_n(xfer->fifo, ptr, len);
+  }
   xfer->queued_len = (uint16_t)(xfer->queued_len + len);
-  
   if (ep_ix == 0U)
   {
     // Control endpoint: clear the interrupt flag to send the data
     USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
     
-  } else 
-  {
+  } else {
     // Other endpoint types: clear the FIFO control flag to send the data
     USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
   }
@@ -562,19 +566,17 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->buffer = buffer;
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
+  xfer->fifo = NULL;
   
   if(EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {
-    uint32_t udd_dma_ctrl = 0;
-    udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
+    uint32_t udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
     if (dir == TUSB_DIR_OUT)
     {
       udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_TR_IT | USBHS_DEVDMACONTROL_END_TR_EN;
-    } else
-    {
+    } else {
       udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_B_EN;
     }
-    // Start USB DMA to fill or read fifo of the selected endpoint
 		USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)buffer;
 		udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_BUFFIT | USBHS_DEVDMACONTROL_CHANN_ENB;
     // Disable IRQs to have a short sequence
@@ -594,13 +596,92 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 		// and the DMA transfer must be not started.
 		// It is the end of transfer
     return false;
-  } else
-  {
+  } else {
     if (dir == TUSB_DIR_OUT)
     {
       USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
-    } else
+    } else {
+      dcd_transmit_packet(xfer,epnum);
+    }
+  }
+  return true;
+}
+
+// The number of bytes has to be given explicitly to allow more flexible control of how many
+// bytes should be written and second to keep the return value free to give back a boolean
+// success message. If total_bytes is too big, the FIFO will copy only what is available
+// into the USB buffer!
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  (void) rhport;
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  
+  xfer_ctl_t * xfer = &xfer_status[epnum];
+  if(epnum == 0x80)
+    xfer = &xfer_status[EP_MAX];
+  
+  xfer->buffer = NULL;
+  xfer->total_len = total_bytes;
+  xfer->queued_len = 0;
+  xfer->fifo = ff;
+  
+  if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
+  {
+    tu_fifo_buffer_info_t info;
+    uint32_t udd_dma_ctrl_lin = USBHS_DEVDMACONTROL_CHANN_ENB;
+    uint32_t udd_dma_ctrl_wrap = USBHS_DEVDMACONTROL_CHANN_ENB | USBHS_DEVDMACONTROL_END_BUFFIT;
+    if (dir == TUSB_DIR_OUT)
     {
+      tu_fifo_get_write_info(ff, &info);
+      udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_END_TR_IT | USBHS_DEVDMACONTROL_END_TR_EN;
+      udd_dma_ctrl_wrap |= USBHS_DEVDMACONTROL_END_TR_IT | USBHS_DEVDMACONTROL_END_TR_EN;
+    } else {
+      tu_fifo_get_read_info(ff, &info);
+      if(info.len_wrap == 0)
+      {
+        udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_END_B_EN;
+      }
+      udd_dma_ctrl_wrap |= USBHS_DEVDMACONTROL_END_B_EN;
+    }
+    
+    USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)info.ptr_lin;
+    if (info.len_wrap)
+    {
+      dma_desc[epnum - 1].next_desc = 0;
+      dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
+      dma_desc[epnum - 1].chnl_ctrl = 
+        udd_dma_ctrl_wrap | USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_wrap);
+      udd_dma_ctrl_lin |= USBHS_DEVDMASTATUS_DESC_LDST;
+      __DSB();
+      __ISB();
+      USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
+    } else {
+      udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_END_BUFFIT;
+    }
+		udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_lin);
+    // Disable IRQs to have a short sequence
+		// between read of EOT_STA and DMA enable
+		uint32_t irq_state = __get_PRIMASK();
+    __disable_irq();
+		if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST))
+    {
+      USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMACONTROL = udd_dma_ctrl_lin;
+			USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << (epnum - 1);
+			__set_PRIMASK(irq_state);
+			return true;
+		}
+		__set_PRIMASK(irq_state);
+
+		// Here a ZLP has been recieved
+		// and the DMA transfer must be not started.
+		// It is the end of transfer
+    return false;
+  } else {
+    if (dir == TUSB_DIR_OUT)
+    {
+      USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
+    } else {
       dcd_transmit_packet(xfer,epnum);
     }
   }

From 5d6e381ef640fce9f590abe0ce304bf4c9474605 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Jun 2021 17:34:51 +0700
Subject: [PATCH 0050/2085] refactor rp2040 usb

- make _hw_endpoint_xfer_sync and _hw_endpoint_start_next_buffer private
- drop prefix _ from _hw_endpoint_xfer_continue and
_hw_endpoint_reset_transfer
---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c |  4 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 65 +--------------
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 85 ++++++++++----------
 src/portable/raspberrypi/rp2040/rp2040_usb.h |  6 +-
 4 files changed, 48 insertions(+), 112 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index ccdbb9c01..c755c2e6f 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -201,7 +201,7 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t b
 static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
     struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
-    _hw_endpoint_xfer_start(ep, buffer, total_bytes);
+    hw_endpoint_xfer_start(ep, buffer, total_bytes);
 }
 
 static void hw_handle_buff_status(void)
@@ -221,7 +221,7 @@ static void hw_handle_buff_status(void)
             // IN transfer for even i, OUT transfer for odd i
             struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, !(i & 1u));
             // Continue xfer
-            bool done = _hw_endpoint_xfer_continue(ep);
+            bool done = hw_endpoint_xfer_continue(ep);
             if (done)
             {
                 // Notify
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 561656a10..1ba9725fe 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -123,7 +123,7 @@ static void hw_xfer_complete(struct hw_endpoint *ep, xfer_result_t xfer_result)
 static void _handle_buff_status_bit(uint bit, struct hw_endpoint *ep)
 {
     usb_hw_clear->buf_status = bit;
-    bool done = _hw_endpoint_xfer_continue(ep);
+    bool done = hw_endpoint_xfer_continue(ep);
     if (done)
     {
         hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
@@ -485,65 +485,6 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
     return true;
 }
 
-// return true if double buffered
-static bool xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len)
-{
-  // Fill in info now that we're kicking off the hw
-  ep->total_len = total_len;
-  ep->len = 0;
-
-  // Limit by packet size
-  ep->user_buf = buffer;
-
-  // Buffer 0
-  ep->transfer_size = tu_min16(total_len, ep->wMaxPacketSize);
-  total_len -= ep->transfer_size;
-
-  // Buffer 1
-  ep->buf_1_len = tu_min16(total_len, ep->wMaxPacketSize);
-  total_len -= ep->buf_1_len;
-
-  ep->active = true;
-
-  // Write buffer control
-
-  // Buffer 0
-  uint32_t bufctrl = ep->transfer_size  | USB_BUF_CTRL_AVAIL;
-
-  // Copy data to DPB if tx
-  if (!ep->rx)
-  {
-    // Copy data from user buffer to hw buffer
-    memcpy(ep->hw_data_buf, ep->user_buf, ep->transfer_size + ep->buf_1_len);
-
-    // Mark as full
-    bufctrl |= USB_BUF_CTRL_FULL | (ep->buf_1_len ? (USB_BUF_CTRL_FULL << 16) : 0);
-  }
-
-  // PID
-  bufctrl |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
-  ep->next_pid ^= 1u;
-
-  if (ep->buf_1_len)
-  {
-    bufctrl |= (ep->buf_1_len | USB_BUF_CTRL_AVAIL) << 16;
-    bufctrl |= (ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID) << 16;
-    ep->next_pid ^= 1u;
-  }
-
-  // determine which buffer is last
-  if (total_len == 0)
-  {
-    bufctrl |= USB_BUF_CTRL_LAST << (ep->buf_1_len ? 16 : 0);
-  }
-
-  print_bufctrl32(bufctrl);
-
-  _hw_endpoint_buffer_control_set_value32(ep, bufctrl);
-
-  return ep->buf_1_len > 0;
-}
-
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
     (void) rhport;
@@ -567,7 +508,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     // sie ctrl registers. Otherwise interrupt ep registers should
     // already be configured
     if (ep == &epx) {
-        _hw_endpoint_xfer_start(ep, buffer, buflen);
+        hw_endpoint_xfer_start(ep, buffer, buflen);
 
         // That has set up buffer control, endpoint control etc
         // for host we have to initiate the transfer
@@ -581,7 +522,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
         usb_hw->sie_ctrl = flags;
     }else
     {
-      _hw_endpoint_xfer_start(ep, buffer, buflen);
+      hw_endpoint_xfer_start(ep, buffer, buflen);
     }
 
     return true;
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 5f61f90c5..293325b8b 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -50,6 +50,13 @@ static inline void _hw_endpoint_update_last_buf(struct hw_endpoint *ep)
 }
 #endif
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
+void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
+
 void rp2040_usb_init(void)
 {
     // Reset usb controller
@@ -180,8 +187,7 @@ void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
   _hw_endpoint_buffer_control_set_value32(ep, buf_ctrl);
 }
 
-
-void _hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len)
+void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len)
 {
   _hw_endpoint_lock_update(ep, 1);
   pico_trace("Start transfer of total len %d on ep %d %s\n", total_len, tu_edpt_number(ep->ep_addr),
@@ -205,58 +211,34 @@ void _hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t t
   _hw_endpoint_lock_update(ep, -1);
 }
 
-void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
+static void ep_sync_buf(struct hw_endpoint *ep, uint8_t buf_id)
 {
-  // Update hw endpoint struct with info from hardware
-  // after a buff status interrupt
+  uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
+  if (buf_id)  buf_ctrl = buf_ctrl >> 16;
 
-  uint32_t const buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
-  print_bufctrl32(buf_ctrl);
+  uint16_t xferred_bytes = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
 
-  // Transferred bytes for each buffer
-  uint16_t xferred_bytes[2];
-
-  xferred_bytes[0] = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
-
-  // double buffered: take buffer1 into account as well
-  if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS )
-  {
-    xferred_bytes[1] = (buf_ctrl >> 16) & USB_BUF_CTRL_LEN_MASK;
-  }else
-  {
-    xferred_bytes[1] = 0;
-  }
-
-  TU_LOG_INT(2, xferred_bytes[0]);
-  TU_LOG_INT(2, xferred_bytes[1]);
-
-  // We are continuing a transfer here. If we are TX, we have successfully
-  // sent some data can increase the length we have sent
   if ( !ep->rx )
   {
+    // We are continuing a transfer here. If we are TX, we have successfully
+    // sent some data can increase the length we have sent
     assert(!(buf_ctrl & USB_BUF_CTRL_FULL));
-    ep->len += xferred_bytes[0] + xferred_bytes[1];
-  }
-  else
+
+    ep->len += xferred_bytes;
+  }else
   {
-    // If we are OUT we have recieved some data, so can increase the length
-    // we have recieved AFTER we have copied it to the user buffer at the appropriate offset
+    // If we have received some data, so can increase the length
+    // we have received AFTER we have copied it to the user buffer at the appropriate offset
     assert(buf_ctrl & USB_BUF_CTRL_FULL);
 
-    memcpy(&ep->user_buf[ep->len], ep->hw_data_buf, xferred_bytes[0]);
-    ep->len += xferred_bytes[0];
-
-    if (xferred_bytes[1])
-    {
-      memcpy(&ep->user_buf[ep->len], ep->hw_data_buf+64, xferred_bytes[1]);
-      ep->len += xferred_bytes[1];
-    }
+    memcpy(&ep->user_buf[ep->len], ep->hw_data_buf + buf_id*64, xferred_bytes);
+    ep->len += xferred_bytes;
   }
 
-  // Sometimes the host will send less data than we expect...
-  // If this is a short out transfer update the total length of the transfer
-  // to be the current length
-  if ( (ep->rx) && ((xferred_bytes[0] < ep->wMaxPacketSize) || (xferred_bytes[1] && (xferred_bytes[1] < ep->wMaxPacketSize))) )
+  // Short packet
+  // TODO what if we prepare double buffered but receive short packet on buffer 0 !!!
+  // would the buffer status  or trans complete interrupt is triggered
+  if (xferred_bytes < ep->wMaxPacketSize)
   {
     pico_trace("Short rx transfer\n");
     // Reduce total length as this is last packet
@@ -264,8 +246,23 @@ void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
   }
 }
 
+void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
+{
+  // Update hw endpoint struct with info from hardware
+  // after a buff status interrupt
+
+  // always sync buffer 0
+  ep_sync_buf(ep, 0);
+
+  // sync buffer 1 if double buffered
+  if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS )
+  {
+    ep_sync_buf(ep, 1);
+  }
+}
+
 // Returns true if transfer is complete
-bool _hw_endpoint_xfer_continue(struct hw_endpoint *ep)
+bool hw_endpoint_xfer_continue(struct hw_endpoint *ep)
 {
     _hw_endpoint_lock_update(ep, 1);
     // Part way through a transfer
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index d27f4157a..b3fcb9417 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -94,11 +94,9 @@ struct hw_endpoint
 
 void rp2040_usb_init(void);
 
+void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len);
+bool hw_endpoint_xfer_continue(struct hw_endpoint *ep);
 void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
-void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
-void _hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len);
-void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
-bool _hw_endpoint_xfer_continue(struct hw_endpoint *ep);
 
 void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask);
 static inline uint32_t _hw_endpoint_buffer_control_get_value32(struct hw_endpoint *ep) {

From 1d48320d8aa85ebeae617be35614cd80011c37f4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Jun 2021 17:58:29 +0700
Subject: [PATCH 0051/2085] rename hw endpoint

- total_len to remaining_len
- len to xferred_len
---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c |  2 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |  4 +-
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 78 +++++++++-----------
 src/portable/raspberrypi/rp2040/rp2040_usb.h |  6 +-
 4 files changed, 41 insertions(+), 49 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index c755c2e6f..3f2bf7810 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -225,7 +225,7 @@ static void hw_handle_buff_status(void)
             if (done)
             {
                 // Notify
-                dcd_event_xfer_complete(0, ep->ep_addr, ep->len, XFER_RESULT_SUCCESS, true);
+                dcd_event_xfer_complete(0, ep->ep_addr, ep->xferred_len, XFER_RESULT_SUCCESS, true);
                 hw_endpoint_reset_transfer(ep);
             }
             remaining_buffers &= ~bit;
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 1ba9725fe..6a1d7cff2 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -115,7 +115,7 @@ static void hw_xfer_complete(struct hw_endpoint *ep, xfer_result_t xfer_result)
     // Mark transfer as done before we tell the tinyusb stack
     uint8_t dev_addr = ep->dev_addr;
     uint8_t ep_addr = ep->ep_addr;
-    uint xferred_len = ep->len;
+    uint xferred_len = ep->xferred_len;
     hw_endpoint_reset_transfer(ep);
     hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
 }
@@ -542,7 +542,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
     _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
     assert(ep->configured);
 
-    ep->total_len     = 8;
+    ep->remaining_len = 8;
     ep->transfer_size = 8;
     ep->active        = true;
     ep->sent_setup    = true;
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 293325b8b..037b24247 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -43,20 +43,13 @@ static inline void _hw_endpoint_lock_update(struct hw_endpoint *ep, int delta) {
     //  sense to have worker and IRQ on same core, however I think using critsec is about equivalent.
 }
 
-#if TUSB_OPT_HOST_ENABLED
-static inline void _hw_endpoint_update_last_buf(struct hw_endpoint *ep)
-{
-    ep->last_buf = (ep->len + ep->transfer_size == ep->total_len);
-}
-#endif
+void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
+void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
-void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
-void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
-
 void rp2040_usb_init(void)
 {
     // Reset usb controller
@@ -82,8 +75,8 @@ void hw_endpoint_reset_transfer(struct hw_endpoint *ep)
 #if TUSB_OPT_HOST_ENABLED
     ep->sent_setup = false;
 #endif
-    ep->total_len = 0;
-    ep->len = 0;
+    ep->remaining_len = 0;
+    ep->xferred_len = 0;
     ep->transfer_size = 0;
     ep->user_buf = 0;
 }
@@ -118,22 +111,29 @@ void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_m
     *ep->buffer_control = value;
 }
 
+//static void prepare_ep_buf(struct hw_endpoint *ep, uint8_t buf_id)
+//{
+//  uint16_t buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
+//
+//
+//}
+
 // Prepare buffer control register value
 void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
 {
-  uint16_t remaining = ep->total_len - ep->len;
   uint32_t ep_ctrl = *ep->endpoint_control;
   uint32_t buf_ctrl;
 
   // Buffer 0
-  ep->transfer_size = tu_min16(remaining, ep->wMaxPacketSize);
-  remaining -= ep->transfer_size;
+  ep->transfer_size = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
+  ep->remaining_len -= ep->transfer_size;
 
   buf_ctrl = ep->transfer_size | USB_BUF_CTRL_AVAIL;
   if ( !ep->rx )
   {
     // Copy data from user buffer to hw buffer
-    memcpy(ep->hw_data_buf, ep->user_buf+ep->len, ep->transfer_size);
+    memcpy(ep->hw_data_buf, ep->user_buf, ep->transfer_size);
+    ep->user_buf += ep->transfer_size;
 
     // Mark as full
     buf_ctrl |= USB_BUF_CTRL_FULL;
@@ -144,8 +144,8 @@ void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
   ep->next_pid ^= 1u;
 
   // Buffer 1
-  ep->buf_1_len = tu_min16(remaining, ep->wMaxPacketSize);
-  remaining -= ep->buf_1_len;
+  ep->buf_1_len = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
+  ep->remaining_len -= ep->buf_1_len;
 
   if (ep->buf_1_len)
   {
@@ -156,7 +156,8 @@ void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
     if ( !ep->rx )
     {
       // Copy data from user buffer to hw buffer
-      memcpy(ep->hw_data_buf+64, ep->user_buf+ep->len+ep->transfer_size, ep->buf_1_len);
+      memcpy(ep->hw_data_buf+64, ep->user_buf, ep->buf_1_len);
+      ep->user_buf += ep->buf_1_len;
     }
 
     // Set endpoint control double buffered bit if needed
@@ -174,7 +175,7 @@ void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
   // Is this the last buffer? Only really matters for host mode. Will trigger
   // the trans complete irq but also stop it polling. We only really care about
   // trans complete for setup packets being sent
-  if (remaining == 0)
+  if (ep->remaining_len == 0)
   {
     buf_ctrl |= USB_BUF_CTRL_LAST << (ep->buf_1_len ? 16 : 0);
   }
@@ -202,16 +203,16 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
   }
 
   // Fill in info now that we're kicking off the hw
-  ep->total_len = total_len;
-  ep->len       = 0;
-  ep->active    = true;
-  ep->user_buf  = buffer;
+  ep->remaining_len = total_len;
+  ep->xferred_len           = 0;
+  ep->active        = true;
+  ep->user_buf      = buffer;
 
   _hw_endpoint_start_next_buffer(ep);
   _hw_endpoint_lock_update(ep, -1);
 }
 
-static void ep_sync_buf(struct hw_endpoint *ep, uint8_t buf_id)
+static void sync_ep_buf(struct hw_endpoint *ep, uint8_t buf_id)
 {
   uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
   if (buf_id)  buf_ctrl = buf_ctrl >> 16;
@@ -224,15 +225,16 @@ static void ep_sync_buf(struct hw_endpoint *ep, uint8_t buf_id)
     // sent some data can increase the length we have sent
     assert(!(buf_ctrl & USB_BUF_CTRL_FULL));
 
-    ep->len += xferred_bytes;
+    ep->xferred_len += xferred_bytes;
   }else
   {
     // If we have received some data, so can increase the length
     // we have received AFTER we have copied it to the user buffer at the appropriate offset
     assert(buf_ctrl & USB_BUF_CTRL_FULL);
 
-    memcpy(&ep->user_buf[ep->len], ep->hw_data_buf + buf_id*64, xferred_bytes);
-    ep->len += xferred_bytes;
+    memcpy(ep->user_buf, ep->hw_data_buf + buf_id*64, xferred_bytes);
+    ep->xferred_len += xferred_bytes;
+    ep->user_buf += xferred_bytes;
   }
 
   // Short packet
@@ -242,7 +244,7 @@ static void ep_sync_buf(struct hw_endpoint *ep, uint8_t buf_id)
   {
     pico_trace("Short rx transfer\n");
     // Reduce total length as this is last packet
-    ep->total_len = ep->len;
+    ep->remaining_len = 0;
   }
 }
 
@@ -252,12 +254,12 @@ void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
   // after a buff status interrupt
 
   // always sync buffer 0
-  ep_sync_buf(ep, 0);
+  sync_ep_buf(ep, 0);
 
   // sync buffer 1 if double buffered
   if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS )
   {
-    ep_sync_buf(ep, 1);
+    sync_ep_buf(ep, 1);
   }
 }
 
@@ -275,23 +277,11 @@ bool hw_endpoint_xfer_continue(struct hw_endpoint *ep)
     _hw_endpoint_xfer_sync(ep);
 
     // Now we have synced our state with the hardware. Is there more data to transfer?
-    // Limit by packet size
-    uint16_t remaining_bytes = ep->total_len - ep->len;
-    ep->transfer_size = tu_min16(remaining_bytes, ep->wMaxPacketSize);
-
-    TU_LOG_INT(2, ep->transfer_size);
-
-    // Can happen because of programmer error so check for it
-    if (ep->len > ep->total_len)
-    {
-        panic("Transferred more data than expected");
-    }
-
     // If we are done then notify tinyusb
-    if (ep->len == ep->total_len)
+    if (ep->remaining_len == 0)
     {
         pico_trace("Completed transfer of %d bytes on ep %d %s\n",
-                   ep->len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+                   ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
         // Notify caller we are done so it can notify the tinyusb stack
         _hw_endpoint_lock_update(ep, -1);
         return true;
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index b3fcb9417..d61a5a57f 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -62,10 +62,12 @@ struct hw_endpoint
 
     // Current transfer information
     bool active;
-    uint16_t total_len;
-    uint16_t len;
+    uint16_t remaining_len;
+    uint16_t xferred_len;
 
     // Amount of data with the hardware
+    uint16_t buflen[2];
+
     uint16_t transfer_size; // buf0_len;
     uint16_t buf_1_len;
 

From 93cb2ff4cf5c9b95ed423be6b8dae498868ab435 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Jun 2021 18:14:11 +0700
Subject: [PATCH 0052/2085] more refactor double buffered rp2040

---
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 179 +++++++++----------
 1 file changed, 86 insertions(+), 93 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 037b24247..38a59d83a 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -52,33 +52,33 @@ void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
 
 void rp2040_usb_init(void)
 {
-    // Reset usb controller
-    reset_block(RESETS_RESET_USBCTRL_BITS);
-    unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
+  // Reset usb controller
+  reset_block(RESETS_RESET_USBCTRL_BITS);
+  unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
 
-    // Clear any previous state just in case
-    memset(usb_hw, 0, sizeof(*usb_hw));
-    memset(usb_dpram, 0, sizeof(*usb_dpram));
+  // Clear any previous state just in case
+  memset(usb_hw, 0, sizeof(*usb_hw));
+  memset(usb_dpram, 0, sizeof(*usb_dpram));
 
-    // Mux the controller to the onboard usb phy
-    usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS    | USB_USB_MUXING_SOFTCON_BITS;
+  // Mux the controller to the onboard usb phy
+  usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS    | USB_USB_MUXING_SOFTCON_BITS;
 
-    // Force VBUS detect so the device thinks it is plugged into a host
-    // TODO support VBUs detect
-    usb_hw->pwr    = USB_USB_PWR_VBUS_DETECT_BITS  | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
+  // Force VBUS detect so the device thinks it is plugged into a host
+  // TODO support VBUs detect
+  usb_hw->pwr    = USB_USB_PWR_VBUS_DETECT_BITS  | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
 }
 
 void hw_endpoint_reset_transfer(struct hw_endpoint *ep)
 {
-    ep->stalled = false;
-    ep->active = false;
+  ep->stalled = false;
+  ep->active = false;
 #if TUSB_OPT_HOST_ENABLED
-    ep->sent_setup = false;
+  ep->sent_setup = false;
 #endif
-    ep->remaining_len = 0;
-    ep->xferred_len = 0;
-    ep->transfer_size = 0;
-    ep->user_buf = 0;
+  ep->remaining_len = 0;
+  ep->xferred_len = 0;
+  ep->transfer_size = 0;
+  ep->user_buf = 0;
 }
 
 void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
@@ -111,76 +111,69 @@ void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_m
     *ep->buffer_control = value;
 }
 
-//static void prepare_ep_buf(struct hw_endpoint *ep, uint8_t buf_id)
-//{
-//  uint16_t buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
-//
-//
-//}
-
-// Prepare buffer control register value
-void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
+static uint32_t compute_ep_buf(struct hw_endpoint *ep, uint8_t buf_id)
 {
-  uint32_t ep_ctrl = *ep->endpoint_control;
-  uint32_t buf_ctrl;
+  uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
+  ep->remaining_len -= buflen;
 
-  // Buffer 0
-  ep->transfer_size = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
-  ep->remaining_len -= ep->transfer_size;
-
-  buf_ctrl = ep->transfer_size | USB_BUF_CTRL_AVAIL;
-  if ( !ep->rx )
-  {
-    // Copy data from user buffer to hw buffer
-    memcpy(ep->hw_data_buf, ep->user_buf, ep->transfer_size);
-    ep->user_buf += ep->transfer_size;
-
-    // Mark as full
-    buf_ctrl |= USB_BUF_CTRL_FULL;
-  }
+  uint32_t buf_ctrl = buflen | USB_BUF_CTRL_AVAIL;
 
   // PID
   buf_ctrl |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
   ep->next_pid ^= 1u;
 
-  // Buffer 1
-  ep->buf_1_len = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
-  ep->remaining_len -= ep->buf_1_len;
-
-  if (ep->buf_1_len)
+  if ( !ep->rx )
   {
-    buf_ctrl |= (ep->buf_1_len | USB_BUF_CTRL_AVAIL) << 16;
-    buf_ctrl |= (ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID) << 16;
-    ep->next_pid ^= 1u;
+    // Copy data from user buffer to hw buffer
+    memcpy(ep->hw_data_buf, ep->user_buf, buflen);
+    ep->user_buf += buflen;
 
-    if ( !ep->rx )
-    {
-      // Copy data from user buffer to hw buffer
-      memcpy(ep->hw_data_buf+64, ep->user_buf, ep->buf_1_len);
-      ep->user_buf += ep->buf_1_len;
-    }
-
-    // Set endpoint control double buffered bit if needed
-    ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER;
-    ep_ctrl |= EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER;
-  }else
-  {
-    ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
-    ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
+    // Mark as full
+    buf_ctrl |= USB_BUF_CTRL_FULL;
   }
 
-  *ep->endpoint_control = ep_ctrl;
-
 #if TUSB_OPT_HOST_ENABLED
   // Is this the last buffer? Only really matters for host mode. Will trigger
   // the trans complete irq but also stop it polling. We only really care about
   // trans complete for setup packets being sent
   if (ep->remaining_len == 0)
   {
-    buf_ctrl |= USB_BUF_CTRL_LAST << (ep->buf_1_len ? 16 : 0);
+    buf_ctrl |= USB_BUF_CTRL_LAST;
   }
 #endif
 
+  if (buf_id) buf_ctrl = buf_ctrl << 16;
+
+  return buf_ctrl;
+}
+
+// Prepare buffer control register value
+void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
+{
+  uint32_t ep_ctrl = *ep->endpoint_control;
+
+  // always compute buffer 0
+  uint32_t buf_ctrl = compute_ep_buf(ep, 0);
+
+  if(ep->remaining_len)
+  {
+    // Use buffer 1 (double buffered) if there is still data
+    // TODO: Isochronous for buffer1 bit-field is different than CBI (control bulk, interrupt)
+
+    buf_ctrl |= compute_ep_buf(ep, 1);
+
+    // Set endpoint control double buffered bit if needed
+    ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER;
+    ep_ctrl |= EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER;
+  }else
+  {
+    // Single buffered since 1 is enough
+    ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
+    ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
+  }
+
+  *ep->endpoint_control = ep_ctrl;
+
   print_bufctrl32(buf_ctrl);
 
   // Finally, write to buffer_control which will trigger the transfer
@@ -266,34 +259,34 @@ void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
 // Returns true if transfer is complete
 bool hw_endpoint_xfer_continue(struct hw_endpoint *ep)
 {
-    _hw_endpoint_lock_update(ep, 1);
-    // Part way through a transfer
-    if (!ep->active)
-    {
-        panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string);
-    }
+  _hw_endpoint_lock_update(ep, 1);
+  // Part way through a transfer
+  if (!ep->active)
+  {
+    panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string);
+  }
 
-    // Update EP struct from hardware state
-    _hw_endpoint_xfer_sync(ep);
-
-    // Now we have synced our state with the hardware. Is there more data to transfer?
-    // If we are done then notify tinyusb
-    if (ep->remaining_len == 0)
-    {
-        pico_trace("Completed transfer of %d bytes on ep %d %s\n",
-                   ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
-        // Notify caller we are done so it can notify the tinyusb stack
-        _hw_endpoint_lock_update(ep, -1);
-        return true;
-    }
-    else
-    {
-        _hw_endpoint_start_next_buffer(ep);
-    }
+  // Update EP struct from hardware state
+  _hw_endpoint_xfer_sync(ep);
 
+  // Now we have synced our state with the hardware. Is there more data to transfer?
+  // If we are done then notify tinyusb
+  if (ep->remaining_len == 0)
+  {
+    pico_trace("Completed transfer of %d bytes on ep %d %s\n",
+               ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+    // Notify caller we are done so it can notify the tinyusb stack
     _hw_endpoint_lock_update(ep, -1);
-    // More work to do
-    return false;
+    return true;
+  }
+  else
+  {
+    _hw_endpoint_start_next_buffer(ep);
+  }
+
+  _hw_endpoint_lock_update(ep, -1);
+  // More work to do
+  return false;
 }
 
 #endif

From 66c8a13f137d54a2c140d04310cd4b7adba50401 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Jun 2021 18:26:41 +0700
Subject: [PATCH 0053/2085] remove unused variable in hw endpoint

last_buf, buf_sel, transfer_size
---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 18 ++++++++--------
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 22 ++++++++++----------
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 12 -----------
 3 files changed, 20 insertions(+), 32 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 6a1d7cff2..0bbd7e7c2 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Double Buffered
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -220,6 +221,14 @@ static void hcd_rp2040_irq(void)
         usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS;
     }
 
+    if (status & USB_INTS_BUFF_STATUS_BITS)
+    {
+        handled |= USB_INTS_BUFF_STATUS_BITS;
+        TU_LOG(2, "Buffer complete\n");
+        // print_bufctrl32(*epx.buffer_control);
+        hw_handle_buff_status();
+    }
+
     if (status & USB_INTS_TRANS_COMPLETE_BITS)
     {
         handled |= USB_INTS_TRANS_COMPLETE_BITS;
@@ -228,14 +237,6 @@ static void hcd_rp2040_irq(void)
         hw_trans_complete();
     }
 
-    if (status & USB_INTS_BUFF_STATUS_BITS)
-    {
-        handled |= USB_INTS_BUFF_STATUS_BITS;
-        TU_LOG(2, "Buffer complete\n");
-        print_bufctrl32(*epx.buffer_control);
-        hw_handle_buff_status();
-    }
-
     if (status & USB_INTS_STALL_BITS)
     {
         // We have rx'd a stall from the device
@@ -543,7 +544,6 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
     assert(ep->configured);
 
     ep->remaining_len = 8;
-    ep->transfer_size = 8;
     ep->active        = true;
     ep->sent_setup    = true;
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 38a59d83a..26c6e8b13 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Double Buffered
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -43,8 +44,8 @@ static inline void _hw_endpoint_lock_update(struct hw_endpoint *ep, int delta) {
     //  sense to have worker and IRQ on same core, however I think using critsec is about equivalent.
 }
 
-void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
-void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
+static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
+static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
 
 //--------------------------------------------------------------------+
 //
@@ -77,7 +78,6 @@ void hw_endpoint_reset_transfer(struct hw_endpoint *ep)
 #endif
   ep->remaining_len = 0;
   ep->xferred_len = 0;
-  ep->transfer_size = 0;
   ep->user_buf = 0;
 }
 
@@ -111,7 +111,7 @@ void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_m
     *ep->buffer_control = value;
 }
 
-static uint32_t compute_ep_buf(struct hw_endpoint *ep, uint8_t buf_id)
+static uint32_t compute_buffer_control(struct hw_endpoint *ep, uint8_t buf_id)
 {
   uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
   ep->remaining_len -= buflen;
@@ -148,19 +148,19 @@ static uint32_t compute_ep_buf(struct hw_endpoint *ep, uint8_t buf_id)
 }
 
 // Prepare buffer control register value
-void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
+static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
 {
   uint32_t ep_ctrl = *ep->endpoint_control;
 
   // always compute buffer 0
-  uint32_t buf_ctrl = compute_ep_buf(ep, 0);
+  uint32_t buf_ctrl = compute_buffer_control(ep, 0);
 
   if(ep->remaining_len)
   {
     // Use buffer 1 (double buffered) if there is still data
     // TODO: Isochronous for buffer1 bit-field is different than CBI (control bulk, interrupt)
 
-    buf_ctrl |= compute_ep_buf(ep, 1);
+    buf_ctrl |= compute_buffer_control(ep, 1);
 
     // Set endpoint control double buffered bit if needed
     ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER;
@@ -205,7 +205,7 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
   _hw_endpoint_lock_update(ep, -1);
 }
 
-static void sync_ep_buf(struct hw_endpoint *ep, uint8_t buf_id)
+static void sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
 {
   uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
   if (buf_id)  buf_ctrl = buf_ctrl >> 16;
@@ -241,18 +241,18 @@ static void sync_ep_buf(struct hw_endpoint *ep, uint8_t buf_id)
   }
 }
 
-void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
+static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
 {
   // Update hw endpoint struct with info from hardware
   // after a buff status interrupt
 
   // always sync buffer 0
-  sync_ep_buf(ep, 0);
+  sync_ep_buffer(ep, 0);
 
   // sync buffer 1 if double buffered
   if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS )
   {
-    sync_ep_buf(ep, 1);
+    sync_ep_buffer(ep, 1);
   }
 }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index d61a5a57f..ada1dd750 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -65,12 +65,6 @@ struct hw_endpoint
     uint16_t remaining_len;
     uint16_t xferred_len;
 
-    // Amount of data with the hardware
-    uint16_t buflen[2];
-
-    uint16_t transfer_size; // buf0_len;
-    uint16_t buf_1_len;
-
     // User buffer in main memory
     uint8_t *user_buf;
 
@@ -80,12 +74,6 @@ struct hw_endpoint
     uint8_t transfer_type;
     
 #if TUSB_OPT_HOST_ENABLED
-    // Only needed for host mode
-    bool last_buf;
-
-    // RP2040-E4: HOST BUG. Host will incorrect write status to top half of buffer
-    // control register when doing transfers > 1 packet
-    uint8_t buf_sel;
     // Only needed for host
     uint8_t dev_addr;
     bool sent_setup;

From a6d22f5a6879388e657987378cecea827794ad1e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Jun 2021 18:39:28 +0700
Subject: [PATCH 0054/2085] replace pico_warn by log level 1

---
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  2 +-
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 24 +++++++++++---------
 2 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 26c6e8b13..cb46ad1b9 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -189,7 +189,7 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
   if ( ep->active )
   {
     // TODO: Is this acceptable for interrupt packets?
-    pico_warn("WARN: starting new transfer on already active ep %d %s\n", tu_edpt_number(ep->ep_addr),
+    TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\n", tu_edpt_number(ep->ep_addr),
               ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
 
     hw_endpoint_reset_transfer(ep);
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index ada1dd750..278ba59ec 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -29,12 +29,6 @@
 #define pico_info(format,...) ((void)0)
 #endif
 
-#if false && !defined(NDEBUG)
-#define pico_warn(format,args...) printf(format, ## args)
-#else
-#define pico_warn(format,...) ((void)0)
-#endif
-
 // Hardware information per endpoint
 struct hw_endpoint
 {
@@ -127,13 +121,14 @@ typedef union TU_ATTR_PACKED
 
 TU_VERIFY_STATIC(sizeof(rp2040_buffer_control_t) == 2, "size is not correct");
 
-static inline void print_bufctrl16(uint32_t __unused u16)
+#if CFG_TUSB_DEBUG >= 3
+static inline void print_bufctrl16(uint32_t u16)
 {
-  rp2040_buffer_control_t __unused bufctrl = {
+  rp2040_buffer_control_t bufctrl = {
       .u16 = u16
   };
 
-  TU_LOG(2, "len = %u, available = %u, stall = %u, reset = %u, toggle = %u, last = %u, full = %u\r\n",
+  TU_LOG(3, "len = %u, available = %u, stall = %u, reset = %u, toggle = %u, last = %u, full = %u\r\n",
          bufctrl.xfer_len, bufctrl.available, bufctrl.stall, bufctrl.reset_bufsel, bufctrl.data_toggle, bufctrl.last_buf, bufctrl.full);
 }
 
@@ -142,12 +137,19 @@ static inline void print_bufctrl32(uint32_t u32)
   uint16_t u16;
 
   u16 = u32 >> 16;
-  TU_LOG(2, "  Buffer Control 1 0x%x: ", u16);
+  TU_LOG(3, "  Buffer Control 1 0x%x: ", u16);
   print_bufctrl16(u16);
 
   u16 = u32 & 0x0000ffff;
-  TU_LOG(2, "  Buffer Control 0 0x%x: ", u16);
+  TU_LOG(3, "  Buffer Control 0 0x%x: ", u16);
   print_bufctrl16(u16);
 }
 
+#else
+
+#define print_bufctrl16(u16)
+#define print_bufctrl32(u32)
+
+#endif
+
 #endif

From b39faa15effec35dceb95655b0db75c3fe564f3d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Jun 2021 18:44:08 +0700
Subject: [PATCH 0055/2085] map pico_info to log2, pico_trace to log3

---
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 278ba59ec..4c24b8dbe 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -17,17 +17,8 @@
 #endif
 
 
-#if true || false && !defined(NDEBUG)
-#define pico_trace(format,args...) printf(format, ## args)
-#else
-#define pico_trace(format,...) ((void)0)
-#endif
-
-#if false && !defined(NDEBUG)
-#define pico_info(format,args...) printf(format, ## args)
-#else
-#define pico_info(format,...) ((void)0)
-#endif
+#define pico_info(...)  TU_LOG(2, __VA_ARGS__)
+#define pico_trace(...) TU_LOG(3, __VA_ARGS__)
 
 // Hardware information per endpoint
 struct hw_endpoint

From dfe5a727c6b236c1b05b5447cdf0535545a6d32e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Jun 2021 18:53:56 +0700
Subject: [PATCH 0056/2085] log clean up

---
 src/class/hid/hid_host.c                     | 6 +++---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 8 +++-----
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index a227c2a86..7444c10fe 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -442,9 +442,9 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr,
 
     uint8_t const data8 = desc_report[0];
 
-    TU_LOG2("tag = %d, type = %d, size = %d, data = ", tag, type, size);
-    for(uint32_t i=0; i<size; i++) TU_LOG2("%02X ", desc_report[i]);
-    TU_LOG2("\r\n");
+    TU_LOG(3, "tag = %d, type = %d, size = %d, data = ", tag, type, size);
+    for(uint32_t i=0; i<size; i++) TU_LOG(3, "%02X ", desc_report[i]);
+    TU_LOG(3, "\r\n");
 
     switch(type)
     {
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 0bbd7e7c2..c145082f2 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -146,15 +146,13 @@ static void hw_handle_buff_status(void)
         uint32_t ep_ctrl = *ep->endpoint_control;
         if (ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS)
         {
-          TU_LOG(2, "Double Buffered ");
+          TU_LOG(3, "Double Buffered: ");
         }else
         {
-          TU_LOG(2, "Single Buffered ");
+          TU_LOG(3, "Single Buffered: ");
         }
 
-        if (ep_ctrl & EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER) TU_LOG(2, "Interrupt per double ");
-        if (ep_ctrl & EP_CTRL_INTERRUPT_PER_BUFFER) TU_LOG(2, "Interrupt per single ");
-        TU_LOG_HEX(2, ep_ctrl);
+        TU_LOG_HEX(3, ep_ctrl);
 
         _handle_buff_status_bit(bit, ep);
     }

From 910e11a8aba7328a3cb61ecf8ac5a10f8a525377 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Jun 2021 19:04:16 +0700
Subject: [PATCH 0057/2085] fix ci build

---
 src/host/usbh.c                              | 7 ++++---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 1 -
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 81b9e84af..203f9fd54 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -990,13 +990,14 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
   // parse each interfaces
   while( p_desc < _usbh_ctrl_buf + desc_cfg->wTotalLength )
   {
-    tusb_desc_interface_assoc_t const * desc_itf_assoc = NULL;
+    // TODO Do we need to use IAD
+    // tusb_desc_interface_assoc_t const * desc_itf_assoc = NULL;
 
     // Class will always starts with Interface Association (if any) and then Interface descriptor
     if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
     {
-      desc_itf_assoc = (tusb_desc_interface_assoc_t const *) p_desc;
-      p_desc = tu_desc_next(p_desc); // next to Interface
+      // desc_itf_assoc = (tusb_desc_interface_assoc_t const *) p_desc;
+      p_desc = tu_desc_next(p_desc);
     }
 
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index c145082f2..ab8639861 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -151,7 +151,6 @@ static void hw_handle_buff_status(void)
         {
           TU_LOG(3, "Single Buffered: ");
         }
-
         TU_LOG_HEX(3, ep_ctrl);
 
         _handle_buff_status_bit(bit, ep);

From 9a03ab9dfadb4f5a93df02b76a84c44edc6fc9f4 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Fri, 11 Jun 2021 20:52:22 +0100
Subject: [PATCH 0058/2085] dcd: same70: change cmsis deprecated macros

Signed-off-by: Rafael Silva <perigoso@riseup.net>
---
 src/portable/microchip/same70/dcd_same70.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/portable/microchip/same70/dcd_same70.c b/src/portable/microchip/same70/dcd_same70.c
index eb716182d..284010e53 100644
--- a/src/portable/microchip/same70/dcd_same70.c
+++ b/src/portable/microchip/same70/dcd_same70.c
@@ -233,7 +233,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         dcd_event_setup_received(0, ptr, true);
       }
       // Acknowledge the interrupt 
-      USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXSTPIC;
+      USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_CTRL_RXSTPIC;
     }
     if (int_status & USBHS_DEVEPTISR_RXOUTI)
     {
@@ -474,11 +474,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
        USBHS_DEVEPTCFG_ALLOC
       );
     USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RSTDTS;
-    USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_STALLRQC;
+    USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_CTRL_STALLRQC;
     if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK))
     {
       // Endpoint configuration is successful 
-      USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RXSTPES;
+      USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
       // Enable Endpoint 0 Interrupts 
       USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
       return true;
@@ -512,7 +512,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 #endif
     USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_ALLOC;
     USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RSTDTS;
-    USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
+    USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_CTRL_STALLRQC;
     if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK))
     {
       USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
@@ -693,7 +693,7 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_STALLRQS;
+  USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_CTRL_STALLRQS;
 }
 
 // clear stall, data toggle is also reset to DATA0
@@ -701,7 +701,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_STALLRQC;
+  USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_CTRL_STALLRQC;
   USBHS->USBHS_DEVEPTIER[epnum] = USBHS_HSTPIPIER_RSTDTS;
 }
 

From bcd3e31bd678053918898a29136cf787e72a534b Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Fri, 11 Jun 2021 20:59:48 +0100
Subject: [PATCH 0059/2085] dcd: same70: fix unused variable warning

Signed-off-by: Rafael Silva <perigoso@riseup.net>
---
 src/portable/microchip/same70/dcd_same70.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/portable/microchip/same70/dcd_same70.c b/src/portable/microchip/same70/dcd_same70.c
index 284010e53..d4430ce99 100644
--- a/src/portable/microchip/same70/dcd_same70.c
+++ b/src/portable/microchip/same70/dcd_same70.c
@@ -134,6 +134,7 @@ void dcd_int_disable (uint8_t rhport)
 // Receive Set Address request, mcu port must also include status IN response
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
+  (void) dev_addr;
   // DCD can only set address after status for this request is complete
   // do it at dcd_edpt0_status_complete()
   
@@ -151,6 +152,7 @@ void dcd_remote_wakeup (uint8_t rhport)
 // Connect by enabling internal pull-up resistor on D+/D-
 void dcd_connect(uint8_t rhport)
 {
+  (void) rhport;
   uint32_t irq_state = __get_PRIMASK();
   __disable_irq();
   // Enable USB clock

From 71aae2743c2e3704411c2c6cbab3cbcb0f8144d1 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Fri, 11 Jun 2021 21:01:12 +0100
Subject: [PATCH 0060/2085] bsp: same70_xplained: fix unused variable warning

Signed-off-by: Rafael Silva <perigoso@riseup.net>
---
 hw/bsp/same70_xplained/same70_xplained.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/bsp/same70_xplained/same70_xplained.c b/hw/bsp/same70_xplained/same70_xplained.c
index fb8855f52..e34b5d35d 100644
--- a/hw/bsp/same70_xplained/same70_xplained.c
+++ b/hw/bsp/same70_xplained/same70_xplained.c
@@ -52,6 +52,7 @@ static volatile bool uart_busy = false;
 
 static void tx_cb_EDBG_COM(const struct usart_async_descriptor *const io_descr)
 {
+  (void) io_descr;
   uart_busy = false;
 }
 

From 28875c431b783ba1a552a9a1cd3df077445c8435 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Fri, 11 Jun 2021 21:02:23 +0100
Subject: [PATCH 0061/2085] bsp: same70_xplained: replace template vars from
 make

Signed-off-by: Rafael Silva <perigoso@riseup.net>
---
 hw/bsp/same70_xplained/board.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index 90ffbb708..13c552f98 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -8,7 +8,7 @@ CFLAGS += \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
   -D__SAME70Q21B__ \
-  -DCFG_TUSB_MCU=OPT_MCU_NONE
+  -DCFG_TUSB_MCU=OPT_MCU_SAME70
 
 # suppress following warnings from mcu driver
 CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
@@ -19,7 +19,7 @@ ASF_DIR = hw/mcu/microchip/same70
 LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
 
 SRC_C += \
-	src/portable/template/dcd_template.c \
+	src/portable/microchip/same70/dcd_same70.c \
 	$(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \
 	$(ASF_DIR)/same70b/gcc/system_same70q21b.c \
 	$(ASF_DIR)/hpl/core/hpl_init.c \

From 2196991df31f27dcf2bf71cc4bf743774ea395e8 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Fri, 11 Jun 2021 21:03:36 +0100
Subject: [PATCH 0062/2085] dcd: same70: trim trailling spaces

Signed-off-by: Rafael Silva <perigoso@riseup.net>
---
 src/portable/microchip/same70/dcd_same70.c | 108 ++++++++++-----------
 1 file changed, 54 insertions(+), 54 deletions(-)

diff --git a/src/portable/microchip/same70/dcd_same70.c b/src/portable/microchip/same70/dcd_same70.c
index d4430ce99..0ad9ad625 100644
--- a/src/portable/microchip/same70/dcd_same70.c
+++ b/src/portable/microchip/same70/dcd_same70.c
@@ -1,4 +1,4 @@
-/* 
+/*
 * The MIT License (MIT)
 *
 * Copyright (c) 2018, hathach (tinyusb.org)
@@ -137,7 +137,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
   (void) dev_addr;
   // DCD can only set address after status for this request is complete
   // do it at dcd_edpt0_status_complete()
-  
+
   // Response with zlp status
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
@@ -234,7 +234,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
         dcd_event_setup_received(0, ptr, true);
       }
-      // Acknowledge the interrupt 
+      // Acknowledge the interrupt
       USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_CTRL_RXSTPIC;
     }
     if (int_status & USBHS_DEVEPTISR_RXOUTI)
@@ -251,34 +251,34 @@ static void dcd_ep_handler(uint8_t ep_ix)
         }
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
-      // Acknowledge the interrupt 
+      // Acknowledge the interrupt
       USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXOUTIC;
       if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
       {
-        // RX COMPLETE 
+        // RX COMPLETE
         dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-        // Disable the interrupt 
+        // Disable the interrupt
         USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
         // Though the host could still send, we don't know.
       }
     }
     if (int_status & USBHS_DEVEPTISR_TXINI)
     {
-      // Disable the interrupt 
+      // Disable the interrupt
       USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
       xfer_ctl_t * xfer = &xfer_status[EP_MAX];
       if ((xfer->total_len != xfer->queued_len))
       {
-        // TX not complete 
+        // TX not complete
         dcd_transmit_packet(xfer, 0);
       } else {
-        // TX complete 
+        // TX complete
         dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
       }
     }
   } else {
     if (int_status & USBHS_DEVEPTISR_RXOUTI)
-    { 
+    {
       xfer_ctl_t *xfer = &xfer_status[ep_ix];
       if (count)
       {
@@ -291,27 +291,27 @@ static void dcd_ep_handler(uint8_t ep_ix)
         }
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
-      // Acknowledge the interrupt 
+      // Acknowledge the interrupt
       USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
       // Clear the FIFO control flag to receive more data.
       USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
       if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
       {
-        // RX COMPLETE 
+        // RX COMPLETE
         dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-        // Disable the interrupt 
+        // Disable the interrupt
         USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_RXOUTEC;
         // Though the host could still send, we don't know.
       }
     }
     if (int_status & USBHS_DEVEPTISR_TXINI)
     {
-      // Acknowledge the interrupt 
+      // Acknowledge the interrupt
       USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
       xfer_ctl_t * xfer = &xfer_status[ep_ix];;
       if ((xfer->total_len != xfer->queued_len))
       {
-        // TX not complete 
+        // TX not complete
         dcd_transmit_packet(xfer, ep_ix);
       } else {
         // TX complete
@@ -331,7 +331,7 @@ static void dcd_dma_handler(uint8_t ep_ix)
   }
   // Disable DMA interrupt
   USBHS->USBHS_DEVIDR = USBHS_DEVIDR_DMA_1 << (ep_ix - 1);
-  
+
   xfer_ctl_t *xfer = &xfer_status[ep_ix];
   uint16_t count = xfer->total_len - ((status & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos);
   if(USBHS->USBHS_DEVEPTCFG[ep_ix] & USBHS_DEVEPTCFG_EPDIR)
@@ -346,10 +346,10 @@ void dcd_int_handler(uint8_t rhport)
 {
   (void) rhport;
   uint32_t int_status = USBHS->USBHS_DEVISR;
-  // End of reset interrupt 
+  // End of reset interrupt
   if (int_status & USBHS_DEVISR_EORST)
   {
-    // Unfreeze USB clock 
+    // Unfreeze USB clock
     USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
     while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
     // Reset all endpoints
@@ -363,10 +363,10 @@ void dcd_int_handler(uint8_t rhport)
     USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
     USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
     USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
-    
+
     dcd_event_bus_reset(rhport, get_speed(), true);
   }
-  // End of Wakeup interrupt 
+  // End of Wakeup interrupt
   if (int_status & USBHS_DEVISR_WAKEUP)
   {
     USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
@@ -374,31 +374,31 @@ void dcd_int_handler(uint8_t rhport)
     USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
     USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC;
     USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
-    
+
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
   }
-  // Suspend interrupt 
+  // Suspend interrupt
   if (int_status & USBHS_DEVISR_SUSP)
   {
-    // Unfreeze USB clock 
+    // Unfreeze USB clock
     USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
     while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
     USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
     USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC;
     USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES;
     USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
-    
+
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 #if USE_SOF
   if(int_status & USBHS_DEVISR_SOF)
   {
     USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC;
-    
+
     dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
   }
-#endif 
-  // Endpoints interrupt 
+#endif
+  // Endpoints interrupt
   for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
   {
     if (int_status & (USBHS_DEVISR_PEP_0 << ep_ix))
@@ -406,7 +406,7 @@ void dcd_int_handler(uint8_t rhport)
       dcd_ep_handler(ep_ix);
     }
   }
-  // Endpoints DMA interrupt 
+  // Endpoints DMA interrupt
   for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
   {
     if (EP_DMA_SUPPORT(ep_ix))
@@ -433,7 +433,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
       request->bRequest == TUSB_REQ_SET_ADDRESS )
   {
     uint8_t const dev_addr = (uint8_t) request->wValue;
-    
+
     USBHS->USBHS_DEVCTRL |= dev_addr | USBHS_DEVCTRL_ADDEN;
   }
 }
@@ -446,9 +446,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   uint8_t const dir   = tu_edpt_dir(ep_desc->bEndpointAddress);
   uint16_t const epMaxPktSize = ep_desc->wMaxPacketSize.size;
   tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
-  uint8_t fifoSize = 0;                       // FIFO size 
-  uint16_t defaultEndpointSize = 8;           // Default size of Endpoint 
-  // Find upper 2 power number of epMaxPktSize 
+  uint8_t fifoSize = 0;                       // FIFO size
+  uint16_t defaultEndpointSize = 8;           // Default size of Endpoint
+  // Find upper 2 power number of epMaxPktSize
   if (epMaxPktSize)
   {
     while (defaultEndpointSize < epMaxPktSize)
@@ -458,16 +458,16 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     }
   }
   xfer_status[epnum].max_packet_size = epMaxPktSize;
-  
+
   USBHS->USBHS_DEVEPT |= 1 << (USBHS_DEVEPT_EPRST0_Pos + epnum);
   USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPRST0_Pos + epnum));
-    
-  if (epnum == 0) 
+
+  if (epnum == 0)
   {
     xfer_status[EP_MAX].max_packet_size = epMaxPktSize;
-    // Enable the control endpoint - Endpoint 0 
+    // Enable the control endpoint - Endpoint 0
     USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
-    // Configure the Endpoint 0 configuration register 
+    // Configure the Endpoint 0 configuration register
     USBHS->USBHS_DEVEPTCFG[0] =
       (
        USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
@@ -479,20 +479,20 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_CTRL_STALLRQC;
     if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK))
     {
-      // Endpoint configuration is successful 
+      // Endpoint configuration is successful
       USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
-      // Enable Endpoint 0 Interrupts 
+      // Enable Endpoint 0 Interrupts
       USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
       return true;
     } else {
-      // Endpoint configuration is not successful 
+      // Endpoint configuration is not successful
       return false;
     }
   } else {
-    // Enable the endpoint 
+    // Enable the endpoint
     USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
     // Set up the maxpacket size, fifo start address fifosize
-    // and enable the interrupt. CLear the data toggle. 
+    // and enable the interrupt. CLear the data toggle.
     // AUTOSW is needed for DMA ack !
     USBHS->USBHS_DEVEPTCFG[epnum] =
       (
@@ -504,12 +504,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
       );
     if (eptype == TUSB_XFER_ISOCHRONOUS)
     {
-      USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1); 
+      USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1);
     }
 #if USE_DUAL_BANK
     if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK)
     {
-      USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_EPBK_2_BANK; 
+      USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_EPBK_2_BANK;
     }
 #endif
     USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_ALLOC;
@@ -520,7 +520,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
       USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
       return true;
     } else {
-      // Endpoint configuration is not successful 
+      // Endpoint configuration is not successful
       return false;
     }
   }
@@ -546,7 +546,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
   {
     // Control endpoint: clear the interrupt flag to send the data
     USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
-    
+
   } else {
     // Other endpoint types: clear the FIFO control flag to send the data
     USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
@@ -560,16 +560,16 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
-  
+
   xfer_ctl_t * xfer = &xfer_status[epnum];
   if(ep_addr == 0x80)
     xfer = &xfer_status[EP_MAX];
-  
+
   xfer->buffer = buffer;
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
   xfer->fifo = NULL;
-  
+
   if(EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {
     uint32_t udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
@@ -618,16 +618,16 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
-  
+
   xfer_ctl_t * xfer = &xfer_status[epnum];
   if(epnum == 0x80)
     xfer = &xfer_status[EP_MAX];
-  
+
   xfer->buffer = NULL;
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
   xfer->fifo = ff;
-  
+
   if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {
     tu_fifo_buffer_info_t info;
@@ -646,13 +646,13 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
       }
       udd_dma_ctrl_wrap |= USBHS_DEVDMACONTROL_END_B_EN;
     }
-    
+
     USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)info.ptr_lin;
     if (info.len_wrap)
     {
       dma_desc[epnum - 1].next_desc = 0;
       dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
-      dma_desc[epnum - 1].chnl_ctrl = 
+      dma_desc[epnum - 1].chnl_ctrl =
         udd_dma_ctrl_wrap | USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_wrap);
       udd_dma_ctrl_lin |= USBHS_DEVDMASTATUS_DESC_LDST;
       __DSB();

From 1c23462b43f47685cf0051568f4bfea5de37d563 Mon Sep 17 00:00:00 2001
From: Wini-Buh <info@winformatik.ch>
Date: Fri, 11 Jun 2021 22:25:36 +0200
Subject: [PATCH 0063/2085] weak atrribute work around removed from CCRX_Port

---
 src/class/cdc/cdc.h                  | 54 ++++++++++-------------
 src/class/cdc/cdc_device.c           | 23 +++-------
 src/class/cdc/cdc_device.h           | 57 ------------------------
 src/common/tusb_compiler.h           | 39 ----------------
 src/common/tusb_types.h              | 42 +++++-------------
 src/device/dcd.h                     | 30 -------------
 src/device/usbd.c                    | 61 ++++++++++---------------
 src/device/usbd.h                    | 66 ----------------------------
 src/device/usbd_control.c            |  6 +--
 src/device/usbd_pvt.h                | 12 -----
 src/portable/renesas/usba/dcd_usba.c | 33 +++++---------
 11 files changed, 74 insertions(+), 349 deletions(-)

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index e5af9fc0c..f59690835 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -215,8 +215,9 @@ typedef enum
 // Class Specific Functional Descriptor (Communication Interface)
 //--------------------------------------------------------------------+
 
+TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+
 /// Header Functional Descriptor (Communication Interface)
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
@@ -224,10 +225,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUNC_DESC_
   uint16_t bcdCDC            ; ///< CDC release number in Binary-Coded Decimal
 }cdc_desc_func_header_t;
-TU_PACK_STRUCT_END
 
 /// Union Functional Descriptor (Communication Interface)
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength                  ; ///< Size of this descriptor in bytes.
@@ -236,7 +235,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t bControlInterface        ; ///< Interface number of Communication Interface
   uint8_t bSubordinateInterface    ; ///< Array of Interface number of Data Interface
 }cdc_desc_func_union_t;
-TU_PACK_STRUCT_END
+
+TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 #define cdc_desc_func_union_n_t(no_slave)\
  TU_PACK_STRUCT_BEGIN                      \
@@ -249,8 +249,10 @@ TU_PACK_STRUCT_END
 }                                          \
 TU_PACK_STRUCT_END
 
+
+TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+
 /// Country Selection Functional Descriptor (Communication Interface)
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength             ; ///< Size of this descriptor in bytes.
@@ -259,7 +261,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t iCountryCodeRelDate ; ///< Index of a string giving the release date for the implemented ISO 3166 Country Codes.
   uint16_t wCountryCode       ; ///< Country code in the format as defined in [ISO3166], release date as specified inoffset 3 for the first supported country.
 }cdc_desc_func_country_selection_t;
-TU_PACK_STRUCT_END
+
+TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 #define cdc_desc_func_country_selection_n_t(no_country) \
   TU_PACK_STRUCT_BEGIN               \
@@ -276,29 +279,28 @@ TU_PACK_STRUCT_END
 // PUBLIC SWITCHED TELEPHONE NETWORK (PSTN) SUBCLASS
 //--------------------------------------------------------------------+
 
+TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+
 /// \brief Call Management Functional Descriptor
 /// \details This functional descriptor describes the processing of calls for the Communications Class interface.
-TU_PACK_STRUCT_BEGIN
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
   uint8_t bDescriptorType    ; ///< Descriptor Type, must be Class-Specific
   uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
 
-  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     uint8_t handle_call    : 1; ///< 0 - Device sends/receives call management information only over the Communications Class interface. 1 - Device can send/receive call management information over a Data Class interface.
     uint8_t send_recv_call : 1; ///< 0 - Device does not handle call management itself. 1 - Device handles call management itself.
     uint8_t TU_RESERVED    : 6;
   } bmCapabilities;
-  TU_BIT_FIELD_ORDER_END
 
   uint8_t bDataInterface;
 }cdc_desc_func_call_management_t;
-TU_PACK_STRUCT_END
+TU_BIT_FIELD_ORDER_END
 
 
-TU_PACK_STRUCT_BEGIN
 TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
@@ -309,13 +311,11 @@ typedef struct TU_ATTR_PACKED
   uint8_t TU_RESERVED                             : 4;
 }cdc_acm_capability_t;
 TU_BIT_FIELD_ORDER_END
-TU_PACK_STRUCT_END
 
 TU_VERIFY_STATIC(sizeof(cdc_acm_capability_t) == 1, "mostly problem with compiler");
 
 /// \brief Abstract Control Management Functional Descriptor
 /// \details This functional descriptor describes the commands supported by by the Communications Class interface with SubClass code of \ref CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength                  ; ///< Size of this descriptor in bytes.
@@ -323,31 +323,27 @@ typedef struct TU_ATTR_PACKED
   uint8_t bDescriptorSubType       ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
   cdc_acm_capability_t bmCapabilities ;
 }cdc_desc_func_acm_t;
-TU_PACK_STRUCT_END
 
 /// \brief Direct Line Management Functional Descriptor
 /// \details This functional descriptor describes the commands supported by the Communications Class interface with SubClass code of \ref CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT
-TU_PACK_STRUCT_BEGIN
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
   uint8_t bDescriptorType    ; ///< Descriptor Type, must be Class-Specific
   uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
-  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     uint8_t require_pulse_setup   : 1; ///< Device requires extra Pulse_Setup request during pulse dialing sequence to disengage holding circuit.
     uint8_t support_aux_request   : 1; ///< Device supports the request combination of Set_Aux_Line_State, Ring_Aux_Jack, and notification Aux_Jack_Hook_State.
     uint8_t support_pulse_request : 1; ///< Device supports the request combination of Pulse_Setup, Send_Pulse, and Set_Pulse_Time.
     uint8_t TU_RESERVED           : 5;
   } bmCapabilities;
-  TU_BIT_FIELD_ORDER_END
 }cdc_desc_func_direct_line_management_t;
-TU_PACK_STRUCT_END
+TU_BIT_FIELD_ORDER_END
 
 /// \brief Telephone Ringer Functional Descriptor
 /// \details The Telephone Ringer functional descriptor describes the ringer capabilities supported by the Communications Class interface,
 /// with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
@@ -356,38 +352,34 @@ typedef struct TU_ATTR_PACKED
   uint8_t bRingerVolSteps    ;
   uint8_t bNumRingerPatterns ;
 }cdc_desc_func_telephone_ringer_t;
-TU_PACK_STRUCT_END
 
 /// \brief Telephone Operational Modes Functional Descriptor
 /// \details The Telephone Operational Modes functional descriptor describes the operational modes supported by
 /// the Communications Class interface, with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL
-TU_PACK_STRUCT_BEGIN
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
   uint8_t bDescriptorType    ; ///< Descriptor Type, must be Class-Specific
   uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
-  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     uint8_t simple_mode           : 1;
     uint8_t standalone_mode       : 1;
     uint8_t computer_centric_mode : 1;
     uint8_t TU_RESERVED           : 5;
   } bmCapabilities;
-  TU_BIT_FIELD_ORDER_END
 }cdc_desc_func_telephone_operational_modes_t;
-TU_PACK_STRUCT_END
+TU_BIT_FIELD_ORDER_END
 
 /// \brief Telephone Call and Line State Reporting Capabilities Descriptor
 /// \details The Telephone Call and Line State Reporting Capabilities functional descriptor describes the abilities of a
 /// telephone device to report optional call and line states.
-TU_PACK_STRUCT_BEGIN
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
   uint8_t bDescriptorType    ; ///< Descriptor Type, must be Class-Specific
   uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
-  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     uint32_t interrupted_dialtone   : 1; ///< 0 : Reports only dialtone (does not differentiate between normal and interrupted dialtone). 1 : Reports interrupted dialtone in addition to normal dialtone
     uint32_t ringback_busy_fastbusy : 1; ///< 0 : Reports only dialing state. 1 : Reports ringback, busy, and fast busy states.
@@ -397,9 +389,8 @@ typedef struct TU_ATTR_PACKED
     uint32_t line_state_change      : 1; ///< 0 : Does not support line state change notification. 1 : Does support line state change notification
     uint32_t TU_RESERVED            : 26;
   } bmCapabilities;
-  TU_BIT_FIELD_ORDER_END
 }cdc_desc_func_telephone_call_state_reporting_capabilities_t;
-TU_PACK_STRUCT_END
+TU_BIT_FIELD_ORDER_END
 
 static inline uint8_t cdc_functional_desc_typeof(uint8_t const * p_desc)
 {
@@ -409,7 +400,6 @@ static inline uint8_t cdc_functional_desc_typeof(uint8_t const * p_desc)
 //--------------------------------------------------------------------+
 // Requests
 //--------------------------------------------------------------------+
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint32_t bit_rate;
@@ -417,11 +407,9 @@ typedef struct TU_ATTR_PACKED
   uint8_t  parity;    ///< 0: None - 1: Odd - 2: Even - 3: Mark - 4: Space
   uint8_t  data_bits; ///< can be 5, 6, 7, 8 or 16
 } cdc_line_coding_t;
-TU_PACK_STRUCT_END
 
 TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct");
 
-TU_PACK_STRUCT_BEGIN
 TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
@@ -430,7 +418,9 @@ typedef struct TU_ATTR_PACKED
   uint16_t : 14;
 } cdc_line_control_state_t;
 TU_BIT_FIELD_ORDER_END
-TU_PACK_STRUCT_END
+
+TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
+
 
 TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct");
 
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 57bb804a8..cac811c45 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -33,15 +33,6 @@
 
 #include "cdc_device.h"
 
-#if defined(TU_HAS_NO_ATTR_WEAK)
-static void (*const MAKE_WEAK_FUNC(tud_cdc_rx_cb))(uint8_t) = TUD_CDC_RX_CB;
-static void (*const MAKE_WEAK_FUNC(tud_cdc_rx_wanted_cb))(uint8_t, char) = TUD_CDC_RX_WANTED_CB;
-static void (*const MAKE_WEAK_FUNC(tud_cdc_tx_complete_cb))(uint8_t) = TUD_CDC_TX_COMPLETE_CB;
-static void (*const MAKE_WEAK_FUNC(tud_cdc_line_state_cb))(uint8_t, bool, bool) = TUD_CDC_LINE_STATE_CB;
-static void (*const MAKE_WEAK_FUNC(tud_cdc_line_coding_cb))(uint8_t, cdc_line_coding_t const*) = TUD_CDC_LINE_CODING_CB;
-static void (*const MAKE_WEAK_FUNC(tud_cdc_send_break_cb))(uint8_t, uint16_t) = TUD_CDC_SEND_BREAK_CB;
-#endif
-
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -370,7 +361,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
       }
       else if ( stage == CONTROL_STAGE_ACK)
       {
-        if ( MAKE_WEAK_FUNC(tud_cdc_line_coding_cb) ) MAKE_WEAK_FUNC(tud_cdc_line_coding_cb)(itf, &p_cdc->line_coding);
+        if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
       }
     break;
 
@@ -405,7 +396,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         TU_LOG2("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
 
         // Invoke callback
-        if ( MAKE_WEAK_FUNC(tud_cdc_line_state_cb) ) MAKE_WEAK_FUNC(tud_cdc_line_state_cb)(itf, dtr, rts);
+        if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
       }
     break;
     case CDC_REQUEST_SEND_BREAK:
@@ -416,7 +407,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
       else if (stage == CONTROL_STAGE_ACK)
       {
         TU_LOG2("  Send Break\r\n");
-        if ( MAKE_WEAK_FUNC(tud_cdc_send_break_cb) ) MAKE_WEAK_FUNC(tud_cdc_send_break_cb)(itf, request->wValue);
+        if ( tud_cdc_send_break_cb ) tud_cdc_send_break_cb(itf, request->wValue);
       }
     break;
 
@@ -447,19 +438,19 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
     tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, xferred_bytes);
     
     // Check for wanted char and invoke callback if needed
-    if ( MAKE_WEAK_FUNC(tud_cdc_rx_wanted_cb) && (((signed char) p_cdc->wanted_char) != -1) )
+    if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) )
     {
       for ( uint32_t i = 0; i < xferred_bytes; i++ )
       {
         if ( (p_cdc->wanted_char == p_cdc->epout_buf[i]) && !tu_fifo_empty(&p_cdc->rx_ff) )
         {
-          MAKE_WEAK_FUNC(tud_cdc_rx_wanted_cb)(itf, p_cdc->wanted_char);
+          tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char);
         }
       }
     }
     
     // invoke receive callback (if there is still data)
-    if (MAKE_WEAK_FUNC(tud_cdc_rx_cb) && !tu_fifo_empty(&p_cdc->rx_ff) ) MAKE_WEAK_FUNC(tud_cdc_rx_cb)(itf);
+    if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff) ) tud_cdc_rx_cb(itf);
     
     // prepare for OUT transaction
     _prep_out_transaction(p_cdc);
@@ -471,7 +462,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   if ( ep_addr == p_cdc->ep_in )
   {
     // invoke transmit callback to possibly refill tx fifo
-    if ( MAKE_WEAK_FUNC(tud_cdc_tx_complete_cb) ) MAKE_WEAK_FUNC(tud_cdc_tx_complete_cb)(itf);
+    if ( tud_cdc_tx_complete_cb ) tud_cdc_tx_complete_cb(itf);
 
     if ( 0 == tud_cdc_n_write_flush(itf) )
     {
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index 389516883..7ff757add 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -129,7 +129,6 @@ static inline bool     tud_cdc_write_clear     (void);
 // Application Callback API (weak is optional)
 //--------------------------------------------------------------------+
 
-#if !defined(TU_HAS_NO_ATTR_WEAK)
 // Invoked when received new data
 TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf);
 
@@ -148,62 +147,6 @@ TU_ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* p
 // Invoked when received send break
 TU_ATTR_WEAK void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms);
 
-#else
- #if  ADD_WEAK_FUNC_TUD_CDC_RX_CB
-  #define TUD_CDC_RX_CB  tud_cdc_rx_cb
- #endif
- #ifndef TUD_CDC_RX_CB
-  #define TUD_CDC_RX_CB    NULL
- #else
-  extern void TUD_CDC_RX_CB(uint8_t itf);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_CDC_RX_WANTED_CB
-  #define TUD_CDC_RX_WANTED_CB  tud_cdc_rx_wanted_cb
- #endif
- #ifndef TUD_CDC_RX_WANTED_CB
-  #define TUD_CDC_RX_WANTED_CB    NULL
- #else
-  extern void TUD_CDC_RX_WANTED_CB(uint8_t itf, char wanted_char);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_CDC_TX_COMPLETE_CB
-  #define TUD_CDC_TX_COMPLETE_CB  tud_cdc_tx_complete_cb
- #endif
- #ifndef TUD_CDC_TX_COMPLETE_CB
-  #define TUD_CDC_TX_COMPLETE_CB    NULL
- #else
-  extern void TUD_CDC_TX_COMPLETE_CB(uint8_t itf);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_CDC_LINE_STATE_CB
-  #define TUD_CDC_LINE_STATE_CB  tud_cdc_line_state_cb
- #endif
- #ifndef TUD_CDC_LINE_STATE_CB
-  #define TUD_CDC_LINE_STATE_CB    NULL
- #else
-  extern void TUD_CDC_LINE_STATE_CB(uint8_t itf, bool dtr, bool rts);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_CDC_LINE_CODING_CB
-  #define TUD_CDC_LINE_CODING_CB  tud_cdc_line_coding_cb
- #endif
- #ifndef TUD_CDC_LINE_CODING_CB
-  #define TUD_CDC_LINE_CODING_CB    NULL
- #else
-  extern void TUD_CDC_LINE_CODING_CB(uint8_t itf, cdc_line_coding_t const* p_line_coding);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_CDC_SEND_BREAK_CB
-  #define TUD_CDC_SEND_BREAK_CB  tud_cdc_send_break_cb
- #endif
- #ifndef TUD_CDC_SEND_BREAK_CB
-  #define TUD_CDC_SEND_BREAK_CB    NULL
- #else
-  extern void TUD_CDC_SEND_BREAK_CB(uint8_t itf, uint16_t duration_ms);
- #endif
-#endif
-
 //--------------------------------------------------------------------+
 // Inline Functions
 //--------------------------------------------------------------------+
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 508bb126e..f77cf94ee 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -64,9 +64,6 @@
 // Compiler porting with Attribute and Endian
 //--------------------------------------------------------------------+
 
-// define the standard definition of this macro to construct a "weak" function name
-#define MAKE_WEAK_FUNC(func_name)  func_name
-
 // TODO refactor since __attribute__ is supported across many compiler
 #if defined(__GNUC__)
   #define TU_ATTR_ALIGNED(Bytes)        __attribute__ ((aligned(Bytes)))
@@ -171,42 +168,6 @@
      the aligned attribute (or something similar yet) */
   #define TU_HAS_NO_ATTR_ALIGNED
 
-  /* activate the "weak" function emulation, because this toolchain does not
-     know the weak attribute (or something similar yet) */
-  #define TU_HAS_NO_ATTR_WEAK
-
-  // make sure to define away the standard definition of this macro
-  #undef MAKE_WEAK_FUNC
-  // Helper macro to construct a "weak" function name
-  #define MAKE_WEAK_FUNC(func_name)  weak_ ## func_name
-
-  #if defined(TU_HAS_NO_ATTR_WEAK)
-  // "Weak function" emulation defined in cdc_device.h
-  #define ADD_WEAK_FUNC_TUD_CDC_RX_CB           0
-  #define ADD_WEAK_FUNC_TUD_CDC_RX_WANTED_CB    0
-  #define ADD_WEAK_FUNC_TUD_CDC_TX_COMPLETE_CB  0
-  #define ADD_WEAK_FUNC_TUD_CDC_LINE_STATE_CB   0
-  #define ADD_WEAK_FUNC_TUD_CDC_LINE_CODING_CB  0
-  #define ADD_WEAK_FUNC_TUD_CDC_SEND_BREAK_CB   0
-
-  // "Weak function" emulation defined in usbd_pvt.h
-  #define ADD_WEAK_FUNC_USBD_APP_DRIVER_GET_CB  0
-
-  // "Weak function" emulation defined in usbd.h
-  #define ADD_WEAK_FUNC_TUD_DESCRIPTOR_BOS_CB               0
-  #define ADD_WEAK_FUNC_TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB  0
-  #define ADD_WEAK_FUNC_TUD_MOUNT_CB                        0
-  #define ADD_WEAK_FUNC_TUD_UMOUNT_CB                       0
-  #define ADD_WEAK_FUNC_TUD_SUSPEND_CB                      0
-  #define ADD_WEAK_FUNC_TUD_RESUME_CB                       0
-  #define ADD_WEAK_FUNC_TUD_VENDOR_CONTROL_XFER_CB          0
-
-  // "Weak function" emulation defined in dcd.h
-  #define ADD_WEAK_FUNC_DCD_EDPT0_STATUS_COMPLETE  0
-  #define ADD_WEAK_FUNC_DCD_EDPT_CLOSE             0
-  #define ADD_WEAK_FUNC_DCD_EDPT_XFER_FIFO         0
-  #endif
-
 #else 
   #error "Compiler attribute porting is required"
 #endif
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index b20ea2974..a8a4d21e5 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -262,8 +262,9 @@ enum
 // USB Descriptors
 //--------------------------------------------------------------------+
 
+TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+
 /// USB Device Descriptor
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes.
@@ -284,12 +285,10 @@ typedef struct TU_ATTR_PACKED
 
   uint8_t  bNumConfigurations ; ///< Number of possible configurations.
 } tusb_desc_device_t;
-TU_PACK_STRUCT_END
 
 TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct");
 
 // USB Binary Device Object Store (BOS) Descriptor
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
@@ -297,10 +296,8 @@ typedef struct TU_ATTR_PACKED
   uint16_t wTotalLength    ; ///< Total length of data returned for this descriptor
   uint8_t  bNumDeviceCaps  ; ///< Number of device capability descriptors in the BOS
 } tusb_desc_bos_t;
-TU_PACK_STRUCT_END
 
 /// USB Configuration Descriptor
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength             ; ///< Size of this descriptor in bytes
@@ -313,10 +310,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t  bmAttributes        ; ///< Configuration characteristics \n D7: Reserved (set to one)\n D6: Self-powered \n D5: Remote Wakeup \n D4...0: Reserved (reset to zero) \n D7 is reserved and must be set to one for historical reasons. \n A device configuration that uses power from the bus and a local source reports a non-zero value in bMaxPower to indicate the amount of bus power required and sets D6. The actual power source at runtime may be determined using the GetStatus(DEVICE) request (see USB 2.0 spec Section 9.4.5). \n If a device configuration supports remote wakeup, D5 is set to one.
   uint8_t  bMaxPower           ; ///< Maximum power consumption of the USB device from the bus in this specific configuration when the device is fully operational. Expressed in 2 mA units (i.e., 50 = 100 mA).
 } tusb_desc_configuration_t;
-TU_PACK_STRUCT_END
 
 /// USB Interface Descriptor
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength            ; ///< Size of this descriptor in bytes
@@ -330,10 +325,9 @@ typedef struct TU_ATTR_PACKED
   uint8_t  bInterfaceProtocol ; ///< Protocol code (assigned by the USB). \n These codes are qualified by the value of the bInterfaceClass and the bInterfaceSubClass fields. If an interface supports class-specific requests, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use a class-specific protocol on this interface. \li If this field is set to FFH, the device uses a vendor-specific protocol for this interface.
   uint8_t  iInterface         ; ///< Index of string descriptor describing this interface
 } tusb_desc_interface_t;
-TU_PACK_STRUCT_END
 
 /// USB Endpoint Descriptor
-TU_PACK_STRUCT_BEGIN
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength          ; ///< Size of this descriptor in bytes
@@ -341,14 +335,12 @@ typedef struct TU_ATTR_PACKED
 
   uint8_t  bEndpointAddress ; ///< The address of the endpoint on the USB device described by this descriptor. The address is encoded as follows: \n Bit 3...0: The endpoint number \n Bit 6...4: Reserved, reset to zero \n Bit 7: Direction, ignored for control endpoints 0 = OUT endpoint 1 = IN endpoint.
 
-  TU_BIT_FIELD_ORDER_BEGIN
   struct TU_ATTR_PACKED {
     uint8_t xfer  : 2;
     uint8_t sync  : 2;
     uint8_t usage : 2;
     uint8_t       : 2;
   } bmAttributes     ; ///< This field describes the endpoint's attributes when it is configured using the bConfigurationValue. \n Bits 1..0: Transfer Type \n- 00 = Control \n- 01 = Isochronous \n- 10 = Bulk \n- 11 = Interrupt \n If not an isochronous endpoint, bits 5..2 are reserved and must be set to zero. If isochronous, they are defined as follows: \n Bits 3..2: Synchronization Type \n- 00 = No Synchronization \n- 01 = Asynchronous \n- 10 = Adaptive \n- 11 = Synchronous \n Bits 5..4: Usage Type \n- 00 = Data endpoint \n- 01 = Feedback endpoint \n- 10 = Implicit feedback Data endpoint \n- 11 = Reserved \n Refer to Chapter 5 of USB 2.0 specification for more information. \n All other bits are reserved and must be reset to zero. Reserved bits must be ignored by the host.
-  TU_BIT_FIELD_ORDER_END
 
   struct TU_ATTR_PACKED {
 #if defined(__CCRX__)
@@ -363,10 +355,9 @@ typedef struct TU_ATTR_PACKED
 
   uint8_t  bInterval        ; ///< Interval for polling endpoint for data transfers. Expressed in frames or microframes depending on the device operating speed (i.e., either 1 millisecond or 125 us units). \n- For full-/high-speed isochronous endpoints, this value must be in the range from 1 to 16. The bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \n- For full-/low-speed interrupt endpoints, the value of this field may be from 1 to 255. \n- For high-speed interrupt endpoints, the bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value must be from 1 to 16. \n- For high-speed bulk/control OUT endpoints, the bInterval must specify the maximum NAK rate of the endpoint. A value of 0 indicates the endpoint never NAKs. Other values indicate at most 1 NAK each bInterval number of microframes. This value must be in the range from 0 to 255. \n Refer to Chapter 5 of USB 2.0 specification for more information.
 } tusb_desc_endpoint_t;
-TU_PACK_STRUCT_END
+TU_BIT_FIELD_ORDER_END
 
 /// USB Other Speed Configuration Descriptor
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength             ; ///< Size of descriptor
@@ -379,10 +370,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t  bmAttributes        ; ///< Same as Configuration descriptor
   uint8_t  bMaxPower           ; ///< Same as Configuration descriptor
 } tusb_desc_other_speed_t;
-TU_PACK_STRUCT_END
 
 /// USB Device Qualifier Descriptor
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength            ; ///< Size of descriptor
@@ -396,10 +385,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t  bNumConfigurations ; ///< Number of Other-speed Configurations
   uint8_t  bReserved          ; ///< Reserved for future use, must be zero
 } tusb_desc_device_qualifier_t;
-TU_PACK_STRUCT_END
 
 /// USB Interface Association Descriptor (IAD ECN)
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength           ; ///< Size of descriptor
@@ -414,20 +401,16 @@ typedef struct TU_ATTR_PACKED
 
   uint8_t iFunction         ; ///< Index of the string descriptor describing the interface association.
 } tusb_desc_interface_assoc_t;
-TU_PACK_STRUCT_END
 
 // USB String Descriptor
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength         ; ///< Size of this descriptor in bytes
   uint8_t  bDescriptorType ; ///< Descriptor Type
   uint16_t unicode_string[];
 } tusb_desc_string_t;
-TU_PACK_STRUCT_END
 
 // USB Binary Device Object Store (BOS)
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength;
@@ -437,10 +420,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t PlatformCapabilityUUID[16];
   uint8_t CapabilityData[];
 } tusb_desc_bos_platform_t;
-TU_PACK_STRUCT_END
 
 // USB WebuSB URL Descriptor
-TU_PACK_STRUCT_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength;
@@ -448,17 +429,15 @@ typedef struct TU_ATTR_PACKED
   uint8_t bScheme;
   char    url[];
 } tusb_desc_webusb_url_t;
-TU_PACK_STRUCT_END
 
 // DFU Functional Descriptor
-TU_PACK_STRUCT_BEGIN
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
 
   union {
-    TU_BIT_FIELD_ORDER_BEGIN
     struct TU_ATTR_PACKED {
       uint8_t bitCanDnload             : 1;
       uint8_t bitCanUpload             : 1;
@@ -466,7 +445,6 @@ typedef struct TU_ATTR_PACKED
       uint8_t bitWillDetach            : 1;
       uint8_t reserved                 : 4;
     } bmAttributes;
-    TU_BIT_FIELD_ORDER_END
 
     uint8_t bAttributes;
   };
@@ -475,21 +453,19 @@ typedef struct TU_ATTR_PACKED
   uint16_t wTransferSize;
   uint16_t bcdDFUVersion;
 } tusb_desc_dfu_functional_t;
-TU_PACK_STRUCT_END
+TU_BIT_FIELD_ORDER_END
 
 /*------------------------------------------------------------------*/
 /* Types
  *------------------------------------------------------------------*/
-TU_PACK_STRUCT_BEGIN
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED{
   union {
-    TU_BIT_FIELD_ORDER_BEGIN
     struct TU_ATTR_PACKED {
       uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.
       uint8_t type      :  2; ///< Request type tusb_request_type_t.
       uint8_t direction :  1; ///< Direction type. tusb_dir_t
     } bmRequestType_bit;
-    TU_BIT_FIELD_ORDER_END
 
     uint8_t bmRequestType;
   };
@@ -499,7 +475,9 @@ typedef struct TU_ATTR_PACKED{
   uint16_t wIndex;
   uint16_t wLength;
 } tusb_control_request_t;
-TU_PACK_STRUCT_END
+TU_BIT_FIELD_ORDER_END
+
+TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 
diff --git a/src/device/dcd.h b/src/device/dcd.h
index d68f9baa7..25cfafc4b 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -117,7 +117,6 @@ void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK;
 // Endpoint API
 //--------------------------------------------------------------------+
 
-#if !defined(TU_HAS_NO_ATTR_WEAK)
 // Invoked when a control transfer's status stage is complete.
 // May help DCD to prepare for next control transfer, this API is optional.
 void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) TU_ATTR_WEAK;
@@ -130,35 +129,6 @@ void dcd_edpt_close           (uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK;
 // This API is optional, may be useful for register-based for transferring data.
 bool dcd_edpt_xfer_fifo       (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) TU_ATTR_WEAK;
 
-#else
- #if ADD_WEAK_FUNC_DCD_EDPT0_STATUS_COMPLETE
-  #define DCD_EDPT0_STATUS_COMPLETE  dcd_edpt0_status_complete
- #endif
- #ifndef DCD_EDPT0_STATUS_COMPLETE
-  #define DCD_EDPT0_STATUS_COMPLETE    NULL
- #else
-  extern void DCD_EDPT0_STATUS_COMPLETE(uint8_t rhport, tusb_control_request_t const * request);
- #endif
-
- #if ADD_WEAK_FUNC_DCD_EDPT_CLOSE
-  #define DCD_EDPT_CLOSE  dcd_edpt_close
- #endif
- #ifndef DCD_EDPT_CLOSE
-  #define DCD_EDPT_CLOSE    NULL
- #else
-  extern void DCD_EDPT_CLOSE(uint8_t rhport, uint8_t ep_addr);
- #endif
-
- #if ADD_WEAK_FUNC_DCD_EDPT_XFER_FIFO
-  #define DCD_EDPT_XFER_FIFO  dcd_edpt_xfer_fifo
- #endif
- #ifndef DCD_EDPT_XFER_FIFO
-  #define DCD_EDPT_XFER_FIFO    NULL
- #else
-  extern void DCD_EDPT_XFER_FIFO(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes);
- #endif
-#endif
-
 // Configure endpoint's registers according to descriptor
 bool dcd_edpt_open            (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 389ba4a4e..49c9279bf 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -33,19 +33,6 @@
 #include "device/usbd_pvt.h"
 #include "device/dcd.h"
 
-#if defined(TU_HAS_NO_ATTR_WEAK)
-static uint8_t const* (*const MAKE_WEAK_FUNC(tud_descriptor_bos_cb))(void) = TUD_DESCRIPTOR_BOS_CB;
-static uint8_t const* (*const MAKE_WEAK_FUNC(tud_descriptor_device_qualifier_cb))(void) = TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB;
-static void (*const MAKE_WEAK_FUNC(tud_mount_cb))(void) = TUD_MOUNT_CB;
-static void (*const MAKE_WEAK_FUNC(tud_umount_cb))(void) = TUD_UMOUNT_CB;
-static void (*const MAKE_WEAK_FUNC(tud_suspend_cb))(_Bool) = TUD_SUSPEND_CB;
-static void (*const MAKE_WEAK_FUNC(tud_resume_cb))(void) = TUD_RESUME_CB;
-static _Bool (*const MAKE_WEAK_FUNC(tud_vendor_control_xfer_cb))(uint8_t, uint8_t, tusb_control_request_t const *) = TUD_RESUME_CB;
-static usbd_class_driver_t const* (*const MAKE_WEAK_FUNC(usbd_app_driver_get_cb))(uint8_t*) = USBD_APP_DRIVER_GET_CB;
-static bool (*const MAKE_WEAK_FUNC(dcd_edpt_xfer_fifo))(uint8_t, uint8_t, tu_fifo_t *, uint16_t) = DCD_EDPT_XFER_FIFO;
-static void (*const MAKE_WEAK_FUNC(dcd_edpt_close))(uint8_t, uint8_t) = DCD_EDPT_CLOSE;
-#endif
-
 #ifndef CFG_TUD_TASK_QUEUE_SZ
 #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
@@ -61,10 +48,11 @@ static void (*const MAKE_WEAK_FUNC(dcd_edpt_close))(uint8_t, uint8_t) = DCD_EDPT
 // Invalid driver ID in itf2drv[] ep2drv[][] mapping
 enum { DRVID_INVALID = 0xFFu };
 
+TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct
 {
-  TU_PACK_STRUCT_BEGIN
-  TU_BIT_FIELD_ORDER_BEGIN
   struct TU_ATTR_PACKED
   {
     volatile uint8_t connected    : 1;
@@ -75,8 +63,6 @@ typedef struct
     uint8_t remote_wakeup_support : 1; // configuration descriptor's attribute
     uint8_t self_powered          : 1; // configuration descriptor's attribute
   };
-  TU_BIT_FIELD_ORDER_END
-  TU_PACK_STRUCT_END
 
   volatile uint8_t cfg_num; // current active configuration (0x00 is not configured)
   uint8_t speed;
@@ -84,8 +70,6 @@ typedef struct
   uint8_t itf2drv[16];     // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUD_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid )
 
-  TU_PACK_STRUCT_BEGIN
-  TU_BIT_FIELD_ORDER_BEGIN
   struct TU_ATTR_PACKED
   {
     volatile bool busy    : 1;
@@ -94,10 +78,11 @@ typedef struct
 
     // TODO merge ep2drv here, 4-bit should be sufficient
   }ep_status[CFG_TUD_EP_MAX][2];
-  TU_BIT_FIELD_ORDER_END
-  TU_PACK_STRUCT_END
 
 }usbd_device_t;
+TU_BIT_FIELD_ORDER_END
+
+TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 static usbd_device_t _usbd_dev;
 
@@ -257,7 +242,7 @@ static uint8_t _app_driver_count = 0;
 static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 {
   // Application drivers
-  if ( MAKE_WEAK_FUNC(usbd_app_driver_get_cb) )
+  if ( usbd_app_driver_get_cb )
   {
     if ( drvid < _app_driver_count ) return &_app_driver[drvid];
     drvid -= _app_driver_count;
@@ -429,9 +414,9 @@ bool tud_init (uint8_t rhport)
   TU_ASSERT(_usbd_q);
 
   // Get application driver if available
-  if ( MAKE_WEAK_FUNC(usbd_app_driver_get_cb) )
+  if ( usbd_app_driver_get_cb )
   {
-    _app_driver = MAKE_WEAK_FUNC(usbd_app_driver_get_cb)(&_app_driver_count);
+    _app_driver = usbd_app_driver_get_cb(&_app_driver_count);
   }
 
   // Init class drivers
@@ -522,7 +507,7 @@ void tud_task (void)
         usbd_reset(event.rhport);
 
         // invoke callback
-        if (MAKE_WEAK_FUNC(tud_umount_cb)) MAKE_WEAK_FUNC(tud_umount_cb)();
+        if (tud_umount_cb) tud_umount_cb();
       break;
 
       case DCD_EVENT_SETUP_RECEIVED:
@@ -578,12 +563,12 @@ void tud_task (void)
 
       case DCD_EVENT_SUSPEND:
         TU_LOG2("\r\n");
-        if (MAKE_WEAK_FUNC(tud_suspend_cb)) MAKE_WEAK_FUNC(tud_suspend_cb)(_usbd_dev.remote_wakeup_en);
+        if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
       break;
 
       case DCD_EVENT_RESUME:
         TU_LOG2("\r\n");
-        if (MAKE_WEAK_FUNC(tud_resume_cb)) MAKE_WEAK_FUNC(tud_resume_cb)();
+        if (tud_resume_cb) tud_resume_cb();
       break;
 
       case DCD_EVENT_SOF:
@@ -630,10 +615,10 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
   // Vendor request
   if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR )
   {
-    TU_VERIFY(MAKE_WEAK_FUNC(tud_vendor_control_xfer_cb));
+    TU_VERIFY(tud_vendor_control_xfer_cb);
 
-    usbd_control_set_complete_callback(MAKE_WEAK_FUNC(tud_vendor_control_xfer_cb));
-    return MAKE_WEAK_FUNC(tud_vendor_control_xfer_cb)(rhport, CONTROL_STAGE_SETUP, p_request);
+    usbd_control_set_complete_callback(tud_vendor_control_xfer_cb);
+    return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request);
   }
 
 #if CFG_TUSB_DEBUG >= 2
@@ -913,7 +898,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
   }
 
   // invoke callback
-  if (MAKE_WEAK_FUNC(tud_mount_cb)) MAKE_WEAK_FUNC(tud_mount_cb)();
+  if (tud_mount_cb) tud_mount_cb();
 
   return true;
 }
@@ -970,9 +955,9 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       TU_LOG2(" BOS\r\n");
 
       // requested by host if USB > 2.0 ( i.e 2.1 or 3.x )
-      if (!MAKE_WEAK_FUNC(tud_descriptor_bos_cb)) return false;
+      if (!tud_descriptor_bos_cb) return false;
 
-      tusb_desc_bos_t const* desc_bos = (tusb_desc_bos_t const*)MAKE_WEAK_FUNC(tud_descriptor_bos_cb)();
+      tusb_desc_bos_t const* desc_bos = (tusb_desc_bos_t const*)tud_descriptor_bos_cb();
 
       uint16_t total_len;
       // Use offsetof to avoid pointer to the odd/misaligned address
@@ -1016,9 +1001,9 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       // Host sends this request to ask why our device with USB BCD from 2.0
       // but is running at Full/Low Speed. If not highspeed capable stall this request,
       // otherwise return the descriptor that could work in highspeed mode
-      if (MAKE_WEAK_FUNC(tud_descriptor_device_qualifier_cb))
+      if (tud_descriptor_device_qualifier_cb)
       {
-        uint8_t const* desc_qualifier = MAKE_WEAK_FUNC(tud_descriptor_device_qualifier_cb)();
+        uint8_t const* desc_qualifier = tud_descriptor_device_qualifier_cb();
         TU_ASSERT(desc_qualifier);
 
         // first byte of descriptor is its size
@@ -1306,7 +1291,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   // and usbd task can preempt and clear the busy
   _usbd_dev.ep_status[epnum][dir].busy = true;
 
-  if (MAKE_WEAK_FUNC(dcd_edpt_xfer_fifo)(rhport, ep_addr, ff, total_bytes))
+  if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes))
   {
     TU_LOG2("OK\r\n");
     return true;
@@ -1369,10 +1354,10 @@ bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
  */
 void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
-  TU_ASSERT(MAKE_WEAK_FUNC(dcd_edpt_close), /**/);
+  TU_ASSERT(dcd_edpt_close, /**/);
   TU_LOG2("  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
 
-  MAKE_WEAK_FUNC(dcd_edpt_close(rhport, ep_addr));
+  dcd_edpt_close(rhport, ep_addr);
 
   return;
 }
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 67f1e2913..57c80fed1 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -111,7 +111,6 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index);
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
 uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid);
 
-#if !defined(TU_HAS_NO_ATTR_WEAK)
 // Invoked when received GET BOS DESCRIPTOR request
 // Application return pointer to descriptor
 TU_ATTR_WEAK uint8_t const * tud_descriptor_bos_cb(void);
@@ -136,71 +135,6 @@ TU_ATTR_WEAK void tud_resume_cb(void);
 // Invoked when received control request with VENDOR TYPE
 TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 
-#else
- #if ADD_WEAK_FUNC_TUD_DESCRIPTOR_BOS_CB
-  #define TUD_DESCRIPTOR_BOS_CB  tud_descriptor_bos_cb
- #endif
- #ifndef TUD_DESCRIPTOR_BOS_CB
-  #define TUD_DESCRIPTOR_BOS_CB    NULL
- #else
-  extern uint8_t const* TUD_DESCRIPTOR_BOS_CB(void);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB
-  #define TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB  tud_descriptor_device_qualifier_cb
- #endif
- #ifndef TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB
-  #define TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB    NULL
- #else
-  extern uint8_t const* TUD_DESCRIPTOR_DEVICE_QUALIFIER_CB(void);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_MOUNT_CB
-  #define TUD_MOUNT_CB  tud_mount_cb
- #endif
- #ifndef TUD_MOUNT_CB
-  #define TUD_MOUNT_CB    NULL
- #else
-  extern void TUD_MOUNT_CB(void);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_UMOUNT_CB
-  #define TUD_UMOUNT_CB  tud_umount_cb
- #endif
- #ifndef TUD_UMOUNT_CB
-  #define TUD_UMOUNT_CB    NULL
- #else
-  extern void TUD_UMOUNT_CB(void);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_SUSPEND_CB
-  #define TUD_SUSPEND_CB  tud_suspend_cb
- #endif
- #ifndef TUD_SUSPEND_CB
-  #define TUD_SUSPEND_CB    NULL
- #else
-  extern void TUD_SUSPEND_CB(bool remote_wakeup_en);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_RESUME_CB
-  #define TUD_RESUME_CB  tud_resume_cb
- #endif
- #ifndef TUD_RESUME_CB
-  #define TUD_RESUME_CB    NULL
- #else
-  extern void TUD_RESUME_CB(void);
- #endif
-
- #if ADD_WEAK_FUNC_TUD_VENDOR_CONTROL_XFER_CB
-  #define TUD_VENDOR_CONTROL_XFER_CB  tud_vendor_control_xfer_cb
- #endif
- #ifndef TUD_VENDOR_CONTROL_XFER_CB
-  #define TUD_VENDOR_CONTROL_XFER_CB    NULL
- #else
-  extern bool TUD_VENDOR_CONTROL_XFER_CB(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
- #endif
-#endif
-
 //--------------------------------------------------------------------+
 // Binary Device Object Store (BOS) Descriptor Templates
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 76f999f86..b3bab2e32 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -36,10 +36,6 @@
 extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
 #endif
 
-#if defined(TU_HAS_NO_ATTR_WEAK)
-static void (*const MAKE_WEAK_FUNC(dcd_edpt0_status_complete))(uint8_t, tusb_control_request_t const *) = DCD_EDPT0_STATUS_COMPLETE;
-#endif
-
 enum
 {
   EDPT_CTRL_OUT = 0x00,
@@ -184,7 +180,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
     TU_ASSERT(0 == xferred_bytes);
 
     // invoke optional dcd hook if available
-    if (MAKE_WEAK_FUNC(dcd_edpt0_status_complete)) MAKE_WEAK_FUNC(dcd_edpt0_status_complete)(rhport, &_ctrl_xfer.request);
+    if (dcd_edpt0_status_complete) dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
 
     if (_ctrl_xfer.complete_cb)
     {
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index c814353ae..bb2267d40 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -51,22 +51,10 @@ typedef struct
   void     (* sof              ) (uint8_t rhport); /* optional */
 } usbd_class_driver_t;
 
-#if !defined(TU_HAS_NO_ATTR_WEAK)
 // Invoked when initializing device stack to get additional class drivers.
 // Can optionally implemented by application to extend/overwrite class driver support.
 // Note: The drivers array must be accessible at all time when stack is active
 usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
-#else
- #if ADD_WEAK_FUNC_USBD_APP_DRIVER_GET_CB
-  #define USBD_APP_DRIVER_GET_CB  usbd_app_driver_get_cb
- #endif
- #ifndef USBD_APP_DRIVER_GET_CB
-  #define USBD_APP_DRIVER_GET_CB    NULL
- #else
-  extern usbd_class_driver_t const* USBD_APP_DRIVER_GET_CB(uint8_t* driver_count);
- #endif
-#endif
-
 
 typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 0e7881383..13fc50ae5 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -90,45 +90,47 @@
 #define FIFO_REQ_CLR         (1u)
 #define FIFO_COMPLETE        (1u<<1)
 
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct {
   union {
-    TU_BIT_FIELD_ORDER_BEGIN
     struct {
       uint16_t      : 8;
       uint16_t TRCLR: 1;
       uint16_t TRENB: 1;
       uint16_t      : 0;
     };
-    TU_BIT_FIELD_ORDER_END
     uint16_t TRE;
   };
   uint16_t TRN;
 } reg_pipetre_t;
+TU_BIT_FIELD_ORDER_END
 
+TU_BIT_FIELD_ORDER_BEGIN
 typedef union {
-  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     volatile uint16_t u8: 8;
     volatile uint16_t   : 0;
   };
-  TU_BIT_FIELD_ORDER_END
   volatile uint16_t u16;
 } hw_fifo_t;
+TU_BIT_FIELD_ORDER_END
 
-TU_PACK_STRUCT_BEGIN
+TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+
+TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uintptr_t addr;      /* the start address of a transfer data buffer */
   uint16_t  length;    /* the number of bytes in the buffer */
   uint16_t  remaining; /* the number of bytes remaining in the buffer */
-  TU_BIT_FIELD_ORDER_BEGIN
   struct {
     uint32_t ep  : 8;  /* an assigned endpoint address */
     uint32_t     : 0;
   };
-  TU_BIT_FIELD_ORDER_END
 } pipe_state_t;
-TU_PACK_STRUCT_END
+TU_BIT_FIELD_ORDER_END
+
+TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 typedef struct
 {
@@ -259,12 +261,6 @@ static int fifo_write(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
 
   hw_fifo_t *reg = (hw_fifo_t*)fifo;
   uintptr_t addr = pipe->addr + pipe->length - rem;
-  if (addr & 1u) {
-    /* addr is not 2-byte aligned */
-    reg->u8 = *(const uint8_t *)addr;
-    ++addr;
-    --len;
-  }
   while (len >= 2) {
     reg->u16 = *(const uint16_t *)addr;
     addr += 2;
@@ -306,17 +302,10 @@ static void process_setup_packet(uint8_t rhport)
   uint16_t setup_packet[4];
   if (0 == (USB0.INTSTS0.WORD & USB_IS0_VALID)) return;
   USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
-  setup_packet[0] = USB0.USBREQ.WORD;
+  setup_packet[0] = tu_le16toh(USB0.USBREQ.WORD);
   setup_packet[1] = USB0.USBVAL;
   setup_packet[2] = USB0.USBINDX;
   setup_packet[3] = USB0.USBLENG;
-#if TU_BYTE_ORDER==TU_BIG_ENDIAN
- #if defined(__CCRX__)
-  setup_packet[0] = tu_le16toh(setup_packet[0]);
- #else
- //FIXME needs to implemented for other tool chains
- #endif
-#endif
   USB0.INTSTS0.WORD = ~USB_IS0_VALID;
   dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
 }

From 776a7709474a0736ed21218c2ff84208745c58cc Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Fri, 11 Jun 2021 22:50:00 +0100
Subject: [PATCH 0064/2085] dcd: sam7x: rename family dcd to include the whole
 family

Signed-off-by: Rafael Silva <perigoso@riseup.net>
---
 examples/device/cdc_dual_ports/src/tusb_config.h              | 2 +-
 examples/device/cdc_dual_ports/src/usb_descriptors.c          | 2 +-
 examples/device/cdc_msc/src/tusb_config.h                     | 2 +-
 examples/device/cdc_msc/src/usb_descriptors.c                 | 2 +-
 hw/bsp/same70_xplained/board.mk                               | 4 ++--
 .../microchip/{same70/dcd_same70.c => sam7x/dcd_sam7x.c}      | 4 ++--
 src/tusb_option.h                                             | 3 ++-
 7 files changed, 10 insertions(+), 9 deletions(-)
 rename src/portable/microchip/{same70/dcd_same70.c => sam7x/dcd_sam7x.c} (99%)

diff --git a/examples/device/cdc_dual_ports/src/tusb_config.h b/examples/device/cdc_dual_ports/src/tusb_config.h
index 45167da8e..19b6925bc 100644
--- a/examples/device/cdc_dual_ports/src/tusb_config.h
+++ b/examples/device/cdc_dual_ports/src/tusb_config.h
@@ -48,7 +48,7 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAME70)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAM7X)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index e39c140cc..f1f71a778 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -94,7 +94,7 @@ enum
   #define EPNUM_CDC_1_OUT     0x05
   #define EPNUM_CDC_1_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAME70
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAM7X
   // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_0_NOTIF   0x81
diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index f9e98b0f7..950f3c421 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -48,7 +48,7 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAME70)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAM7X)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 46b57f7e2..6ac34e859 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -94,7 +94,7 @@ enum
   #define EPNUM_MSC_OUT     0x05
   #define EPNUM_MSC_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAME70
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAM7X
   // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_NOTIF   0x81
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index 13c552f98..031b536b2 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -8,7 +8,7 @@ CFLAGS += \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
   -D__SAME70Q21B__ \
-  -DCFG_TUSB_MCU=OPT_MCU_SAME70
+  -DCFG_TUSB_MCU=OPT_MCU_SAM7X
 
 # suppress following warnings from mcu driver
 CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
@@ -19,7 +19,7 @@ ASF_DIR = hw/mcu/microchip/same70
 LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
 
 SRC_C += \
-	src/portable/microchip/same70/dcd_same70.c \
+	src/portable/microchip/sam7x/dcd_sam7x.c \
 	$(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \
 	$(ASF_DIR)/same70b/gcc/system_same70q21b.c \
 	$(ASF_DIR)/hpl/core/hpl_init.c \
diff --git a/src/portable/microchip/same70/dcd_same70.c b/src/portable/microchip/sam7x/dcd_sam7x.c
similarity index 99%
rename from src/portable/microchip/same70/dcd_same70.c
rename to src/portable/microchip/sam7x/dcd_sam7x.c
index 0ad9ad625..53ea796b4 100644
--- a/src/portable/microchip/same70/dcd_same70.c
+++ b/src/portable/microchip/sam7x/dcd_sam7x.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_SAME70
+#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAM7X
 
 #include "device/dcd.h"
 
@@ -43,7 +43,7 @@
 #endif
 
 // Dual bank can imporve performance, but need 2 times bigger packet buffer
-// As SAME70 has only 4KB packet buffer, use with caution !
+// As SAM7x has only 4KB packet buffer, use with caution !
 // Enable in FS mode as packets are smaller
 #ifndef USE_DUAL_BANK
 #  if TUD_OPT_HIGH_SPEED
diff --git a/src/tusb_option.h b/src/tusb_option.h
index fb86d7f9c..2e1678ccf 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -61,7 +61,8 @@
 #define OPT_MCU_SAME5X            203 ///< MicroChip SAM E5x
 #define OPT_MCU_SAMD11            204 ///< MicroChip SAMD11
 #define OPT_MCU_SAML22            205 ///< MicroChip SAML22
-#define OPT_MCU_SAME70            206 ///< MicroChip SAME70 series
+#define OPT_MCU_SAM7X             206 ///< MicroChip SAME70, S70, V70, V71 family
+
 
 // STM32
 #define OPT_MCU_STM32F0           300 ///< ST STM32F0

From 0066e2b3444e549e7bc7f6ea757548688d46ddc9 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Fri, 11 Jun 2021 23:31:38 +0100
Subject: [PATCH 0065/2085] examples: freertos: add skip for same70

Signed-off-by: Rafael Silva <perigoso@riseup.net>
---
 examples/device/cdc_msc_freertos/.skip.MCU_SAM7X       | 0
 examples/device/hid_composite_freertos/.skip.MCU_SAM7X | 0
 2 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_SAM7X
 create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_SAM7X

diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_SAM7X b/examples/device/cdc_msc_freertos/.skip.MCU_SAM7X
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_SAM7X b/examples/device/hid_composite_freertos/.skip.MCU_SAM7X
new file mode 100644
index 000000000..e69de29bb

From a4ad064e638679a7c8759a2c30ed555bd93e524b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 12 Jun 2021 14:20:09 +0700
Subject: [PATCH 0066/2085] increase example CFG_TUH_HID from 2 to 4

---
 examples/host/cdc_msc_hid/src/tusb_config.h | 2 +-
 src/common/tusb_verify.h                    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 8253964c0..531bb2c30 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -76,7 +76,7 @@
 
 #define CFG_TUH_HUB                 1
 #define CFG_TUH_CDC                 1
-#define CFG_TUH_HID                 2
+#define CFG_TUH_HID                 4
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
 
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 542809899..56ba8bcd1 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -75,7 +75,7 @@
 #if CFG_TUSB_DEBUG
   #include <stdio.h>
   #define _MESS_ERR(_err)   tu_printf("%s %d: failed, error = %s\r\n", __func__, __LINE__, tusb_strerr[_err])
-  #define _MESS_FAILED()    tu_printf("%s %d: assert failed\r\n", __func__, __LINE__)
+  #define _MESS_FAILED()    tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__)
 #else
   #define _MESS_ERR(_err) do {} while (0)
   #define _MESS_FAILED() do {} while (0)

From f039607afcf7473ea3869f2e2e7cd763d13f8de0 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 12 Jun 2021 11:19:08 +0200
Subject: [PATCH 0067/2085] Fix indent.

Signed-off-by: MasterPhi <admin@hifiphile.com>
---
 src/portable/microchip/sam7x/dcd_sam7x.c | 58 ++++++++++++------------
 1 file changed, 29 insertions(+), 29 deletions(-)

diff --git a/src/portable/microchip/sam7x/dcd_sam7x.c b/src/portable/microchip/sam7x/dcd_sam7x.c
index 53ea796b4..6463973bd 100644
--- a/src/portable/microchip/sam7x/dcd_sam7x.c
+++ b/src/portable/microchip/sam7x/dcd_sam7x.c
@@ -430,7 +430,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
 
   if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
       request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
-      request->bRequest == TUSB_REQ_SET_ADDRESS )
+        request->bRequest == TUSB_REQ_SET_ADDRESS )
   {
     uint8_t const dev_addr = (uint8_t) request->wValue;
 
@@ -474,7 +474,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
        USBHS_DEVEPTCFG_EPTYPE(TUSB_XFER_CONTROL) |
        USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
        USBHS_DEVEPTCFG_ALLOC
-      );
+       );
     USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RSTDTS;
     USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_CTRL_STALLRQC;
     if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK))
@@ -501,7 +501,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
        USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
        USBHS_DEVEPTCFG_AUTOSW |
        ((dir & 0x01) << USBHS_DEVEPTCFG_EPDIR_Pos)
-      );
+       );
     if (eptype == TUSB_XFER_ISOCHRONOUS)
     {
       USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1);
@@ -570,7 +570,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->queued_len = 0;
   xfer->fifo = NULL;
 
-  if(EP_DMA_SUPPORT(epnum) && total_bytes != 0)
+  if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {
     uint32_t udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
     if (dir == TUSB_DIR_OUT)
@@ -579,24 +579,24 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     } else {
       udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_B_EN;
     }
-		USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)buffer;
-		udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_BUFFIT | USBHS_DEVDMACONTROL_CHANN_ENB;
+    USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)buffer;
+    udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_BUFFIT | USBHS_DEVDMACONTROL_CHANN_ENB;
     // Disable IRQs to have a short sequence
-		// between read of EOT_STA and DMA enable
-		uint32_t irq_state = __get_PRIMASK();
+    // between read of EOT_STA and DMA enable
+    uint32_t irq_state = __get_PRIMASK();
     __disable_irq();
-		if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST))
+    if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST))
     {
       USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMACONTROL = udd_dma_ctrl;
-			USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << (epnum - 1);
-			__set_PRIMASK(irq_state);
-			return true;
-		}
-		__set_PRIMASK(irq_state);
+      USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << (epnum - 1);
+      __set_PRIMASK(irq_state);
+      return true;
+    }
+    __set_PRIMASK(irq_state);
 
-		// Here a ZLP has been recieved
-		// and the DMA transfer must be not started.
-		// It is the end of transfer
+    // Here a ZLP has been recieved
+    // and the DMA transfer must be not started.
+    // It is the end of transfer
     return false;
   } else {
     if (dir == TUSB_DIR_OUT)
@@ -661,23 +661,23 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
     } else {
       udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_END_BUFFIT;
     }
-		udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_lin);
+    udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_lin);
     // Disable IRQs to have a short sequence
-		// between read of EOT_STA and DMA enable
-		uint32_t irq_state = __get_PRIMASK();
+    // between read of EOT_STA and DMA enable
+    uint32_t irq_state = __get_PRIMASK();
     __disable_irq();
-		if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST))
+    if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST))
     {
       USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMACONTROL = udd_dma_ctrl_lin;
-			USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << (epnum - 1);
-			__set_PRIMASK(irq_state);
-			return true;
-		}
-		__set_PRIMASK(irq_state);
+      USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << (epnum - 1);
+      __set_PRIMASK(irq_state);
+      return true;
+    }
+    __set_PRIMASK(irq_state);
 
-		// Here a ZLP has been recieved
-		// and the DMA transfer must be not started.
-		// It is the end of transfer
+    // Here a ZLP has been recieved
+    // and the DMA transfer must be not started.
+    // It is the end of transfer
     return false;
   } else {
     if (dir == TUSB_DIR_OUT)

From 85fc42356977cac4d893c33eff80937e6ff9b45a Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 12 Jun 2021 12:28:28 +0200
Subject: [PATCH 0068/2085] Rename SAM7X to SAMX7X

Signed-off-by: MasterPhi <admin@hifiphile.com>
---
 examples/device/cdc_dual_ports/src/tusb_config.h              | 2 +-
 examples/device/cdc_dual_ports/src/usb_descriptors.c          | 2 +-
 examples/device/cdc_msc/src/msc_disk.c                        | 2 +-
 examples/device/cdc_msc/src/tusb_config.h                     | 2 +-
 examples/device/cdc_msc/src/usb_descriptors.c                 | 2 +-
 .../cdc_msc_freertos/{.skip.MCU_SAM7X => .skip.MCU_SAMX7X}    | 0
 .../{.skip.MCU_SAM7X => .skip.MCU_SAMX7X}                     | 0
 hw/bsp/same70_xplained/board.mk                               | 4 ++--
 .../microchip/{sam7x/dcd_sam7x.c => samx7x/dcd_samx7x.c}      | 2 +-
 src/tusb_option.h                                             | 2 +-
 10 files changed, 9 insertions(+), 9 deletions(-)
 rename examples/device/cdc_msc_freertos/{.skip.MCU_SAM7X => .skip.MCU_SAMX7X} (100%)
 rename examples/device/hid_composite_freertos/{.skip.MCU_SAM7X => .skip.MCU_SAMX7X} (100%)
 rename src/portable/microchip/{sam7x/dcd_sam7x.c => samx7x/dcd_samx7x.c} (99%)

diff --git a/examples/device/cdc_dual_ports/src/tusb_config.h b/examples/device/cdc_dual_ports/src/tusb_config.h
index 19b6925bc..ff8535d1a 100644
--- a/examples/device/cdc_dual_ports/src/tusb_config.h
+++ b/examples/device/cdc_dual_ports/src/tusb_config.h
@@ -48,7 +48,7 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAM7X)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index f1f71a778..b935b672f 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -94,7 +94,7 @@ enum
   #define EPNUM_CDC_1_OUT     0x05
   #define EPNUM_CDC_1_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAM7X
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
   // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_0_NOTIF   0x81
diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index 503baace9..3caf3fd42 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+//#include "bsp/board.h"
 #include "tusb.h"
 
 #if CFG_TUD_MSC
diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index 950f3c421..bf6af06bc 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -48,7 +48,7 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAM7X)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 6ac34e859..1a89ce561 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -94,7 +94,7 @@ enum
   #define EPNUM_MSC_OUT     0x05
   #define EPNUM_MSC_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAM7X
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
   // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_NOTIF   0x81
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_SAM7X b/examples/device/cdc_msc_freertos/.skip.MCU_SAMX7X
similarity index 100%
rename from examples/device/cdc_msc_freertos/.skip.MCU_SAM7X
rename to examples/device/cdc_msc_freertos/.skip.MCU_SAMX7X
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_SAM7X b/examples/device/hid_composite_freertos/.skip.MCU_SAMX7X
similarity index 100%
rename from examples/device/hid_composite_freertos/.skip.MCU_SAM7X
rename to examples/device/hid_composite_freertos/.skip.MCU_SAMX7X
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index 031b536b2..94b0bed98 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -8,7 +8,7 @@ CFLAGS += \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
   -D__SAME70Q21B__ \
-  -DCFG_TUSB_MCU=OPT_MCU_SAM7X
+  -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
 
 # suppress following warnings from mcu driver
 CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
@@ -19,7 +19,7 @@ ASF_DIR = hw/mcu/microchip/same70
 LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
 
 SRC_C += \
-	src/portable/microchip/sam7x/dcd_sam7x.c \
+	src/portable/microchip/samx7x/dcd_samx7x.c \
 	$(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \
 	$(ASF_DIR)/same70b/gcc/system_same70q21b.c \
 	$(ASF_DIR)/hpl/core/hpl_init.c \
diff --git a/src/portable/microchip/sam7x/dcd_sam7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
similarity index 99%
rename from src/portable/microchip/sam7x/dcd_sam7x.c
rename to src/portable/microchip/samx7x/dcd_samx7x.c
index 6463973bd..a864fda5b 100644
--- a/src/portable/microchip/sam7x/dcd_sam7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAM7X
+#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMX7X
 
 #include "device/dcd.h"
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 2e1678ccf..3f5710362 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -61,7 +61,7 @@
 #define OPT_MCU_SAME5X            203 ///< MicroChip SAM E5x
 #define OPT_MCU_SAMD11            204 ///< MicroChip SAMD11
 #define OPT_MCU_SAML22            205 ///< MicroChip SAML22
-#define OPT_MCU_SAM7X             206 ///< MicroChip SAME70, S70, V70, V71 family
+#define OPT_MCU_SAMX7X             206 ///< MicroChip SAME70, S70, V70, V71 family
 
 
 // STM32

From e4da606164c434f24d9aa157438170f6ef5fbe2f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 12 Jun 2021 23:02:41 +0700
Subject: [PATCH 0069/2085] set TOP to build with esp32sx

---
 examples/device/cdc_msc_freertos/CMakeLists.txt | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 11f1c6135..639dde99a 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -1,5 +1,10 @@
 cmake_minimum_required(VERSION 3.5)
 
+# TOP is absolute path to root directory of TinyUSB git repo
+# needed for esp32sx build. TOOD could be removed later on
+set(TOP "../../..")
+get_filename_component(TOP "${TOP}" REALPATH)
+
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)

From 289ccf3c938c8f2be0edf2a2c8a18c68e39880c0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 13 Jun 2021 13:18:32 +0700
Subject: [PATCH 0070/2085] remove dev_ep_map

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 49 ++++++--------------
 1 file changed, 13 insertions(+), 36 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index ab8639861..42d0839f6 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -59,44 +59,24 @@ static struct hw_endpoint ep_pool[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
 #define usb_hw_set   hw_set_alias(usb_hw)
 #define usb_hw_clear hw_clear_alias(usb_hw)
 
-// todo still a bit wasteful
-// top bit set if valid
-uint8_t dev_ep_map[CFG_TUSB_HOST_DEVICE_MAX][1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS][2];
-
 // Flags we set by default in sie_ctrl (we add other bits on top)
 enum {
-  sie_ctrl_base = USB_SIE_CTRL_SOF_EN_BITS        |
-                  USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
-                  USB_SIE_CTRL_PULLDOWN_EN_BITS   |
-                  USB_SIE_CTRL_EP0_INT_1BUF_BITS
+  SIE_CTRL_BASE = USB_SIE_CTRL_SOF_EN_BITS        | USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
+                  USB_SIE_CTRL_PULLDOWN_EN_BITS   | USB_SIE_CTRL_EP0_INT_1BUF_BITS
 };
 
 static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
 {
-    uint8_t num = tu_edpt_number(ep_addr);
-    if (num == 0) {
-        return &epx;
-    }
-    uint8_t in = (ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0;
-    uint mapping = dev_ep_map[dev_addr-1][num][in];
-    pico_trace("Get dev addr %d ep %d = %d\n", dev_addr, ep_addr, mapping);
-    return mapping >= 128 ? ep_pool + (mapping & 0x7fu) : NULL;
-}
+  uint8_t num = tu_edpt_number(ep_addr);
+  if ( num == 0 ) return &epx;
 
-static void set_dev_ep(uint8_t dev_addr, uint8_t ep_addr, struct hw_endpoint *ep)
-{
-    uint8_t num = tu_edpt_number(ep_addr);
-    uint8_t in = (uint8_t) tu_edpt_dir(ep_addr);
+  for ( uint32_t i = 1; i < TU_ARRAY_SIZE(ep_pool); i++ )
+  {
+    struct hw_endpoint *ep = &ep_pool[i];
+    if ( ep->configured && (ep->dev_addr == dev_addr) && (ep->ep_addr == ep_addr) ) return ep;
+  }
 
-    uint32_t index = ep - ep_pool;
-    hard_assert(index < TU_ARRAY_SIZE(ep_pool));
-
-    // todo revisit why dev_addr can be 0 here
-    if (dev_addr) {
-        dev_ep_map[dev_addr-1][num][in] = 128u | index;
-    }
-
-    pico_trace("Set dev addr %d ep %d = %d\n", dev_addr, ep_addr, index);
+  return NULL;
 }
 
 static inline uint8_t dev_speed(void)
@@ -387,7 +367,7 @@ bool hcd_init(uint8_t rhport)
 
     // Enable in host mode with SOF / Keep alive on
     usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS | USB_MAIN_CTRL_HOST_NDEVICE_BITS;
-    usb_hw->sie_ctrl = sie_ctrl_base;
+    usb_hw->sie_ctrl = SIE_CTRL_BASE;
     usb_hw->inte = USB_INTE_BUFF_STATUS_BITS      | 
                    USB_INTE_HOST_CONN_DIS_BITS    | 
                    USB_INTE_HOST_RESUME_BITS      | 
@@ -477,9 +457,6 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
         ep_desc->bmAttributes.xfer,
         ep_desc->bInterval);
 
-    // Map this struct to ep@device address
-    set_dev_ep(dev_addr, ep_desc->bEndpointAddress, ep);
-
     return true;
 }
 
@@ -512,7 +489,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
         // for host we have to initiate the transfer
         usb_hw->dev_addr_ctrl = dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB);
 
-        uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | sie_ctrl_base |
+        uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
                          (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS);
         // Set pre if we are a low speed device on full speed hub
         flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
@@ -548,7 +525,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
     usb_hw->dev_addr_ctrl = dev_addr;
 
     // Set pre if we are a low speed device on full speed hub
-    uint32_t const flags = sie_ctrl_base | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
+    uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
                            (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
 
     usb_hw->sie_ctrl = flags;

From 1af64f9729f743f4fc9d8686af239c65f689630f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 13 Jun 2021 15:27:20 +0700
Subject: [PATCH 0071/2085] remove sent_setup from hw endpoint

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 34 +++++++++++---------
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  3 --
 src/portable/raspberrypi/rp2040/rp2040_usb.h |  3 +-
 3 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 42d0839f6..40a0805c6 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -161,19 +161,19 @@ static void hw_handle_buff_status(void)
 
 static void hw_trans_complete(void)
 {
-    struct hw_endpoint *ep = &epx;
-    assert(ep->active);
+  struct hw_endpoint *ep = &epx;
+  assert(ep->active);
 
-    if (ep->sent_setup)
-    {
-        pico_trace("Sent setup packet\n");
-        hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
-    }
-    else
-    {
-        // Don't care. Will handle this in buff status
-        return;
-    }
+  if (usb_hw->sie_ctrl & USB_SIE_CTRL_SEND_SETUP_BITS)
+  {
+    pico_trace("Sent setup packet\n");
+    hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
+  }
+  else
+  {
+    // Don't care. Will handle this in buff status
+    return;
+  }
 }
 
 static void hcd_rp2040_irq(void)
@@ -473,10 +473,13 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
     assert(ep);
 
-    if (ep_addr != ep->ep_addr)
+    // Control endpoint can change direction 0x00 <-> 0x80
+    if ( ep_addr != ep->ep_addr )
     {
-        // Direction has flipped on endpoint control so re init it but with same properties
-        _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
+      assert(ep_num == 0);
+
+      // Direction has flipped on endpoint control so re init it but with same properties
+      _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
     }
 
     // If a normal transfer (non-interrupt) then initiate using
@@ -519,7 +522,6 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 
     ep->remaining_len = 8;
     ep->active        = true;
-    ep->sent_setup    = true;
 
     // Set device address
     usb_hw->dev_addr_ctrl = dev_addr;
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index cb46ad1b9..7430881e0 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -73,9 +73,6 @@ void hw_endpoint_reset_transfer(struct hw_endpoint *ep)
 {
   ep->stalled = false;
   ep->active = false;
-#if TUSB_OPT_HOST_ENABLED
-  ep->sent_setup = false;
-#endif
   ep->remaining_len = 0;
   ep->xferred_len = 0;
   ep->user_buf = 0;
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 4c24b8dbe..4c787f496 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -55,13 +55,14 @@ struct hw_endpoint
 
     // Data needed from EP descriptor
     uint16_t wMaxPacketSize;
+
     // Interrupt, bulk, etc
     uint8_t transfer_type;
     
 #if TUSB_OPT_HOST_ENABLED
     // Only needed for host
     uint8_t dev_addr;
-    bool sent_setup;
+
     // If interrupt endpoint
     uint8_t interrupt_num;
 #endif

From bd039c8d37d7df05da992eb8afdcb31f782e1f23 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 13 Jun 2021 16:16:25 +0700
Subject: [PATCH 0072/2085] fix build with log for device

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 35 +++++---------------
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  2 +-
 2 files changed, 10 insertions(+), 27 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 3f2bf7810..63e129e53 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -69,6 +69,7 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep)
     // Assumes single buffered for now
     ep->hw_data_buf = next_buffer_ptr;
     next_buffer_ptr += size;
+
     // Bits 0-5 are ignored by the controller so make sure these are 0
     if ((uintptr_t)next_buffer_ptr & 0b111111u)
     {
@@ -87,8 +88,8 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep)
                 size,
                 dpram_offset,
                 ep->hw_data_buf,
-                ep->num,
-                ep_dir_string[ep->in]);
+                tu_edpt_number(ep->ep_addr),
+                ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
 
     // Fill in endpoint control register with buffer offset
     uint32_t reg =  EP_CTRL_ENABLE_BITS
@@ -103,28 +104,15 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t ep_addr, uint16_t
 {
     const uint8_t num = tu_edpt_number(ep_addr);
     const tusb_dir_t dir = tu_edpt_dir(ep_addr);
+
     ep->ep_addr = ep_addr;
+
     // For device, IN is a tx transfer and OUT is an rx transfer
     ep->rx = (dir == TUSB_DIR_OUT);
+
     // Response to a setup packet on EP0 starts with pid of 1
     ep->next_pid = num == 0 ? 1u : 0u;
 
-    // Add some checks around the max packet size
-    if (transfer_type == TUSB_XFER_ISOCHRONOUS)
-    {
-        if (wMaxPacketSize > USB_MAX_ISO_PACKET_SIZE)
-        {
-            panic("Isochronous wMaxPacketSize %d too large", wMaxPacketSize);
-        }
-    }
-    else
-    {
-        if (wMaxPacketSize > USB_MAX_PACKET_SIZE)
-        {
-            panic("Isochronous wMaxPacketSize %d too large", wMaxPacketSize);
-        }
-    }
-
     ep->wMaxPacketSize = wMaxPacketSize;
     ep->transfer_type = transfer_type;
 
@@ -339,10 +327,7 @@ static void dcd_rp2040_irq(void)
 
 #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
         // Only run enumeration walk-around if pull up is enabled
-        if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS )
-        {
-          rp2040_usb_device_enumeration_fix();
-        }
+        if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix();
 #endif
     }
 
@@ -402,9 +387,9 @@ void dcd_init (uint8_t rhport)
 
     // EP0 always exists so init it now
     // EP0 OUT
-    hw_endpoint_init(0x0, 64, 0);
+    hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL);
     // EP0 IN
-    hw_endpoint_init(0x80, 64, 0);
+    hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL);
 
     // Initializes the USB peripheral for device mode and enables it.
     // Don't need to enable the pull up here. Force VBUS
@@ -495,7 +480,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
     assert(rhport == 0);
-    // True means start new xfer
     hw_endpoint_xfer(ep_addr, buffer, total_bytes);
     return true;
 }
@@ -519,7 +503,6 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
     // usbd.c says: In progress transfers on this EP may be delivered after this call
     pico_trace("dcd_edpt_close %d %02x\n", rhport, ep_addr);
-
 }
 
 void dcd_int_handler(uint8_t rhport)
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 7430881e0..de3a83be9 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -194,7 +194,7 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
 
   // Fill in info now that we're kicking off the hw
   ep->remaining_len = total_len;
-  ep->xferred_len           = 0;
+  ep->xferred_len   = 0;
   ep->active        = true;
   ep->user_buf      = buffer;
 

From f38c460433abc0c557f2035c7205b4f36bcbc677 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 13 Jun 2021 17:19:14 +0700
Subject: [PATCH 0073/2085] fix ep tx with double buffered

---
 src/common/tusb_common.h                     |  2 +-
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 48 ++++++++------------
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 11 ++---
 3 files changed, 25 insertions(+), 36 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index fe5bf5f41..8490daad7 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -123,7 +123,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { retur
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); }
 
 //------------- Mathematics -------------//
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_abs(int32_t value) { return (uint32_t)((value < 0) ? (-value) : value); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d -1)/d; }
 
 /// inclusive range checking TODO remove
 TU_ATTR_ALWAYS_INLINE static inline bool tu_within(uint32_t lower, uint32_t value, uint32_t upper)
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 63e129e53..4f70d60cc 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -64,40 +64,30 @@ static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
 
 static void _hw_endpoint_alloc(struct hw_endpoint *ep)
 {
-    uint16_t size = tu_min16(64, ep->wMaxPacketSize);
+  // size must be multiple of 64
+  uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
 
-    // Assumes single buffered for now
-    ep->hw_data_buf = next_buffer_ptr;
-    next_buffer_ptr += size;
+  // double buffered for non-ISO endpoint
+  if ( ep->transfer_type != TUSB_XFER_ISOCHRONOUS ) size *= 2u;
 
-    // Bits 0-5 are ignored by the controller so make sure these are 0
-    if ((uintptr_t)next_buffer_ptr & 0b111111u)
-    {
-        // Round up to the next 64
-        uint32_t fixptr = (uintptr_t)next_buffer_ptr;
-        fixptr &= ~0b111111u;
-        fixptr += 64;
-        pico_info("Rounding non 64 byte boundary buffer up from %x to %x\n", (uintptr_t)next_buffer_ptr, fixptr);
-        next_buffer_ptr = (uint8_t*)fixptr;
-    }
-    assert(((uintptr_t)next_buffer_ptr & 0b111111u) == 0);
-    uint dpram_offset = hw_data_offset(ep->hw_data_buf);
-    assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX);
+  ep->hw_data_buf = next_buffer_ptr;
+  next_buffer_ptr += size;
 
-    pico_info("Alloced %d bytes at offset 0x%x (0x%p) for ep %d %s\n",
-                size,
-                dpram_offset,
-                ep->hw_data_buf,
-                tu_edpt_number(ep->ep_addr),
-                ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+  assert(((uintptr_t )next_buffer_ptr & 0b111111u) == 0);
+  uint dpram_offset = hw_data_offset(ep->hw_data_buf);
+  assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX);
 
-    // Fill in endpoint control register with buffer offset
-    uint32_t reg =  EP_CTRL_ENABLE_BITS
-                  | EP_CTRL_INTERRUPT_PER_BUFFER
-                  | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
-                  | dpram_offset;
+  pico_info("Alloced %d bytes at offset 0x%x (0x%p) for ep %d %s\n",
+            size,
+            dpram_offset,
+            ep->hw_data_buf,
+            tu_edpt_number(ep->ep_addr),
+            ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
 
-    *ep->endpoint_control = reg;
+  // Fill in endpoint control register with buffer offset
+  uint32_t const reg = EP_CTRL_ENABLE_BITS | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
+
+  *ep->endpoint_control = reg;
 }
 
 static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type)
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index de3a83be9..f8d36e5eb 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -108,7 +108,8 @@ void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_m
     *ep->buffer_control = value;
 }
 
-static uint32_t compute_buffer_control(struct hw_endpoint *ep, uint8_t buf_id)
+// prepare buffer, return buffer control
+static uint32_t prepare_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
 {
   uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
   ep->remaining_len -= buflen;
@@ -122,14 +123,13 @@ static uint32_t compute_buffer_control(struct hw_endpoint *ep, uint8_t buf_id)
   if ( !ep->rx )
   {
     // Copy data from user buffer to hw buffer
-    memcpy(ep->hw_data_buf, ep->user_buf, buflen);
+    memcpy(ep->hw_data_buf + buf_id*64, ep->user_buf, buflen);
     ep->user_buf += buflen;
 
     // Mark as full
     buf_ctrl |= USB_BUF_CTRL_FULL;
   }
 
-#if TUSB_OPT_HOST_ENABLED
   // Is this the last buffer? Only really matters for host mode. Will trigger
   // the trans complete irq but also stop it polling. We only really care about
   // trans complete for setup packets being sent
@@ -137,7 +137,6 @@ static uint32_t compute_buffer_control(struct hw_endpoint *ep, uint8_t buf_id)
   {
     buf_ctrl |= USB_BUF_CTRL_LAST;
   }
-#endif
 
   if (buf_id) buf_ctrl = buf_ctrl << 16;
 
@@ -150,14 +149,14 @@ static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
   uint32_t ep_ctrl = *ep->endpoint_control;
 
   // always compute buffer 0
-  uint32_t buf_ctrl = compute_buffer_control(ep, 0);
+  uint32_t buf_ctrl = prepare_ep_buffer(ep, 0);
 
   if(ep->remaining_len)
   {
     // Use buffer 1 (double buffered) if there is still data
     // TODO: Isochronous for buffer1 bit-field is different than CBI (control bulk, interrupt)
 
-    buf_ctrl |= compute_buffer_control(ep, 1);
+    buf_ctrl |= prepare_ep_buffer(ep, 1);
 
     // Set endpoint control double buffered bit if needed
     ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER;

From 5c567129ea34ea78833cee2bf38e4e09cbdee389 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 13 Jun 2021 18:30:26 +0700
Subject: [PATCH 0074/2085] fix calculating xferred bytes with double buffer
 with short packet on buffer0

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 26 +++++++++++---------
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 22 +++++++++++------
 2 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 4f70d60cc..b87951421 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -67,8 +67,11 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep)
   // size must be multiple of 64
   uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
 
-  // double buffered for non-ISO endpoint
-  if ( ep->transfer_type != TUSB_XFER_ISOCHRONOUS ) size *= 2u;
+  // double buffered for Control and Bulk endpoint
+  if ( ep->transfer_type == TUSB_XFER_CONTROL || ep->transfer_type == TUSB_XFER_BULK)
+  {
+    size *= 2u;
+  }
 
   ep->hw_data_buf = next_buffer_ptr;
   next_buffer_ptr += size;
@@ -445,18 +448,17 @@ void dcd_connect(uint8_t rhport)
 
 void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
 {
-    pico_trace("dcd_edpt0_status_complete %d\n", rhport);
-    assert(rhport == 0);
+  (void) rhport;
 
-    if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
-        request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
-        request->bRequest == TUSB_REQ_SET_ADDRESS)
-    {
-        pico_trace("Set HW address %d\n", request->wValue);
-        usb_hw->dev_addr_ctrl = (uint8_t) request->wValue;
-    }
+  if ( request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+       request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+       request->bRequest == TUSB_REQ_SET_ADDRESS )
+  {
+    pico_trace("Set HW address %d\n", request->wValue);
+    usb_hw->dev_addr_ctrl = (uint8_t) request->wValue;
+  }
 
-    reset_ep0();
+  reset_ep0();
 }
 
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index f8d36e5eb..5b2a5f5a0 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -170,6 +170,7 @@ static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
 
   *ep->endpoint_control = ep_ctrl;
 
+  TU_LOG(3, "Prepare Buffer Control:\r\n");
   print_bufctrl32(buf_ctrl);
 
   // Finally, write to buffer_control which will trigger the transfer
@@ -201,7 +202,8 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
   _hw_endpoint_lock_update(ep, -1);
 }
 
-static void sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
+// sync endpoint buffer and return transferred bytes
+static uint16_t sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
 {
   uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
   if (buf_id)  buf_ctrl = buf_ctrl >> 16;
@@ -227,14 +229,14 @@ static void sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
   }
 
   // Short packet
-  // TODO what if we prepare double buffered but receive short packet on buffer 0 !!!
-  // would the buffer status  or trans complete interrupt is triggered
   if (xferred_bytes < ep->wMaxPacketSize)
   {
-    pico_trace("Short rx transfer\n");
+    pico_trace("Short rx transfer on buffer %d with %u bytes\n", buf_id, xferred_bytes);
     // Reduce total length as this is last packet
     ep->remaining_len = 0;
   }
+
+  return xferred_bytes;
 }
 
 static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
@@ -242,11 +244,15 @@ static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
   // Update hw endpoint struct with info from hardware
   // after a buff status interrupt
 
-  // always sync buffer 0
-  sync_ep_buffer(ep, 0);
+  uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
+  TU_LOG(3, "_hw_endpoint_xfer_sync:\r\n");
+  print_bufctrl32(buf_ctrl);
 
-  // sync buffer 1 if double buffered
-  if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS )
+  // always sync buffer 0
+  uint16_t buf0_bytes = sync_ep_buffer(ep, 0);
+
+  // sync buffer 1 if double buffered and buffer 0 is not short packet
+  if ( ((*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS) && (buf0_bytes == ep->wMaxPacketSize) )
   {
     sync_ep_buffer(ep, 1);
   }

From 7bed7d70f06e291bf4ba4f5d6cfcc238b11c563b Mon Sep 17 00:00:00 2001
From: sabas1080 <sabasjimenez@gmail.com>
Date: Tue, 15 Jun 2021 00:01:28 -0500
Subject: [PATCH 0075/2085] add support SAML21

---
 hw/bsp/board_mcu.h                            |   2 +-
 hw/bsp/saml21/boards/atsaml21_xpro/board.h    |  50 ++++++
 hw/bsp/saml21/boards/atsaml21_xpro/board.mk   |  10 ++
 .../boards/atsaml21_xpro/saml21j18b_flash.ld  | 152 ++++++++++++++++
 hw/bsp/saml21/family.c                        | 163 ++++++++++++++++++
 hw/bsp/saml21/family.mk                       |  50 ++++++
 src/portable/microchip/samd/dcd_samd.c        |   4 +-
 src/tusb_option.h                             |   1 +
 8 files changed, 429 insertions(+), 3 deletions(-)
 create mode 100644 hw/bsp/saml21/boards/atsaml21_xpro/board.h
 create mode 100644 hw/bsp/saml21/boards/atsaml21_xpro/board.mk
 create mode 100644 hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld
 create mode 100644 hw/bsp/saml21/family.c
 create mode 100644 hw/bsp/saml21/family.mk

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 1a659c410..f8e89ad04 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -54,7 +54,7 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
       CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
-      CFG_TUSB_MCU == OPT_MCU_SAML22
+      CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21
   #include "sam.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_SAMG
diff --git a/hw/bsp/saml21/boards/atsaml21_xpro/board.h b/hw/bsp/saml21/boards/atsaml21_xpro/board.h
new file mode 100644
index 000000000..a3e03997c
--- /dev/null
+++ b/hw/bsp/saml21/boards/atsaml21_xpro/board.h
@@ -0,0 +1,50 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PIN               (32 + 30) // PB30
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PIN            (0  + 15) // PA15
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_RX_PIN           4
+#define UART_TX_PIN           5
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/saml21/boards/atsaml21_xpro/board.mk b/hw/bsp/saml21/boards/atsaml21_xpro/board.mk
new file mode 100644
index 000000000..aa77d4a21
--- /dev/null
+++ b/hw/bsp/saml21/boards/atsaml21_xpro/board.mk
@@ -0,0 +1,10 @@
+CFLAGS += -D__SAML21J18B__
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/saml21j18b_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAML21J18
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld b/hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld
new file mode 100644
index 000000000..42f1de8d4
--- /dev/null
+++ b/hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld
@@ -0,0 +1,152 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAML21J18B
+ *
+ * Copyright (c) 2016 Atmel Corporation,
+ *                    a wholly owned subsidiary of Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+  lpram    (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    .lpram (NOLOAD):
+    {
+        . = ALIGN(8);
+        _slpram = .;
+        *(.lpram .lpram.*);
+        . = ALIGN(8);
+        _elpram = .;
+    } > lpram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hw/bsp/saml21/family.c b/hw/bsp/saml21/family.c
new file mode 100644
index 000000000..d2d25ecac
--- /dev/null
+++ b/hw/bsp/saml21/family.c
@@ -0,0 +1,163 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "sam.h"
+#include "bsp/board.h"
+#include "board.h"
+
+#include "hal/include/hal_gpio.h"
+#include "hal/include/hal_init.h"
+#include "hpl/gclk/hpl_gclk_base.h"
+#include "hpl_mclk_config.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_Handler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+/* Referenced GCLKs (out of 0~4), should be initialized firstly */
+#define _GCLK_INIT_1ST 0x00000000
+/* Not referenced GCLKs, initialized last */
+#define _GCLK_INIT_LAST 0x0000001F
+
+void board_init(void)
+{
+  // Clock init ( follow hpl_init.c )
+  hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
+
+  _set_performance_level(2);
+
+  _osc32kctrl_init_sources();
+  _oscctrl_init_sources();
+  _mclk_init();
+#if _GCLK_INIT_1ST
+  _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
+#endif
+  _oscctrl_init_referenced_generators();
+  _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
+
+#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
+  hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL);
+  hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL);
+#endif
+
+  // Update SystemCoreClock since it is hard coded with asf4 and not correct
+  // Init 1ms tick timer (samd SystemCoreClock may not correct)
+  SystemCoreClock = CONF_CPU_FREQUENCY;
+  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
+
+  // Led init
+  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(LED_PIN, !LED_STATE_ON);
+
+  // Button init
+  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP);
+
+#if CFG_TUSB_OS  == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  /* USB Clock init
+   * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
+   * for low speed and full speed operation. */
+  hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
+  hri_mclk_set_AHBMASK_USB_bit(MCLK);
+  hri_mclk_set_APBBMASK_USB_bit(MCLK);
+
+  // USB Pin Init
+  gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(PIN_PA24, false);
+  gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
+  gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(PIN_PA25, false);
+  gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
+
+  gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM);
+  gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
+
+  // Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed
+  hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
+  TCC0->PER.bit.PER = 48000000 / 1000;
+  TCC0->CC[3].bit.CC = 48000000 / 2000;
+  TCC0->CTRLA.bit.ENABLE = true;
+
+  gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3);
+  hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  gpio_set_pin_level(LED_PIN, state);
+}
+
+uint32_t board_button_read(void)
+{
+  // button is active low
+  return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+void _init(void)
+{
+
+}
\ No newline at end of file
diff --git a/hw/bsp/saml21/family.mk b/hw/bsp/saml21/family.mk
new file mode 100644
index 000000000..a6611d5f4
--- /dev/null
+++ b/hw/bsp/saml21/family.mk
@@ -0,0 +1,50 @@
+UF2_FAMILY_ID = 0x68ed2b88
+DEPS_SUBMODULES += hw/mcu/microchip
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0plus \
+  -nostdlib -nostartfiles \
+  -DCONF_OSC32K_CALIB_ENABLE=0 \
+  -DCFG_TUSB_MCU=OPT_MCU_SAML21
+
+SRC_C += \
+	src/portable/microchip/samd/dcd_samd.c \
+	hw/mcu/microchip/saml21/gcc/gcc/startup_saml21.c \
+	hw/mcu/microchip/saml21/gcc/system_saml21.c \
+	hw/mcu/microchip/saml21/hpl/gclk/hpl_gclk.c \
+	hw/mcu/microchip/saml21/hpl/mclk/hpl_mclk.c \
+	hw/mcu/microchip/saml21/hpl/pm/hpl_pm.c \
+	hw/mcu/microchip/saml21/hpl/osc32kctrl/hpl_osc32kctrl.c \
+	hw/mcu/microchip/saml21/hpl/oscctrl/hpl_oscctrl.c \
+	hw/mcu/microchip/saml21/hal/src/hal_atomic.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/hw/mcu/microchip/saml21/ \
+	$(TOP)/hw/mcu/microchip/saml21/config \
+	$(TOP)/hw/mcu/microchip/saml21/include \
+	$(TOP)/hw/mcu/microchip/saml21/hal/include \
+	$(TOP)/hw/mcu/microchip/saml21/hal/utils/include \
+	$(TOP)/hw/mcu/microchip/saml21/hpl/port \
+	$(TOP)/hw/mcu/microchip/saml21/hri \
+	$(TOP)/hw/mcu/microchip/saml21/CMSIS/Include
+
+# For TinyUSB port source 
+VENDOR = microchip
+CHIP_FAMILY = samd
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM0
+
+# flash using bossac at least version 1.8
+# can be found in arduino15/packages/arduino/tools/bossac/
+# Add it to your PATH or change BOSSAC variable to match your installation
+BOSSAC = bossac
+
+flash-bossac: $(BUILD)/$(PROJECT).bin
+	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
+	$(BOSSAC) --port=$(SERIAL) -U -i --offset=0x2000 -e -w $^ -R
diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index 13e56453d..577bd0e05 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -29,7 +29,7 @@
 #if TUSB_OPT_DEVICE_ENABLED && \
     (CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
      CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
-     CFG_TUSB_MCU == OPT_MCU_SAML22)
+     CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21)
 
 #include "sam.h"
 #include "device/dcd.h"
@@ -125,7 +125,7 @@ void dcd_int_disable(uint8_t rhport)
 }
 
 #elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
-      CFG_TUSB_MCU == OPT_MCU_SAML22
+      CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21
 
 void dcd_int_enable(uint8_t rhport)
 {
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 5cfcc08e2..d5776c029 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -61,6 +61,7 @@
 #define OPT_MCU_SAME5X            203 ///< MicroChip SAM E5x
 #define OPT_MCU_SAMD11            204 ///< MicroChip SAMD11
 #define OPT_MCU_SAML22            205 ///< MicroChip SAML22
+#define OPT_MCU_SAML21            206 ///< MicroChip SAML21
 
 // STM32
 #define OPT_MCU_STM32F0           300 ///< ST STM32F0

From ca8e8041ef05ba06d7d01bf1567106a76a793cab Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 15 Jun 2021 17:53:09 +0200
Subject: [PATCH 0076/2085] Fix resume, always init FS clock.

Signed-off-by: MasterPhi <admin@hifiphile.com>
---
 examples/device/hid_composite/src/tusb_config.h | 4 ++--
 src/portable/microchip/samx7x/dcd_samx7x.c      | 5 ++---
 src/tusb_option.h                               | 2 +-
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index 3e608ed37..31dea4ee9 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -48,7 +48,7 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
@@ -69,7 +69,7 @@
 #endif
 
 // CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#define CFG_TUSB_DEBUG           0
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index a864fda5b..f486e0eed 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -49,7 +49,7 @@
 #  if TUD_OPT_HIGH_SPEED
 #    define USE_DUAL_BANK   0
 #  else
-#    define USE_DUAL_BANK   1
+#    define USE_DUAL_BANK   0
 #  endif
 #endif
 
@@ -108,12 +108,10 @@ void dcd_init (uint8_t rhport)
   PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
   // Wait until USB UTMI stabilize
   while (!(PMC->PMC_SR & PMC_SR_LOCKU));
-#if !TUD_OPT_HIGH_SPEED
   // Enable USB FS clk
   PMC->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2;
   PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
   PMC->PMC_SCER = PMC_SCER_USBCLK;
-#endif
   dcd_connect(rhport);
 }
 
@@ -346,6 +344,7 @@ void dcd_int_handler(uint8_t rhport)
 {
   (void) rhport;
   uint32_t int_status = USBHS->USBHS_DEVISR;
+  int_status &= USBHS->USBHS_DEVIMR;
   // End of reset interrupt
   if (int_status & USBHS_DEVISR_EORST)
   {
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 3f5710362..69c5fb0bd 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -61,7 +61,7 @@
 #define OPT_MCU_SAME5X            203 ///< MicroChip SAM E5x
 #define OPT_MCU_SAMD11            204 ///< MicroChip SAMD11
 #define OPT_MCU_SAML22            205 ///< MicroChip SAML22
-#define OPT_MCU_SAMX7X             206 ///< MicroChip SAME70, S70, V70, V71 family
+#define OPT_MCU_SAMX7X            206 ///< MicroChip SAME70, S70, V70, V71 family
 
 
 // STM32

From 54dc694be4430e51d153405afa3b80d949479558 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 15 Jun 2021 19:11:53 +0200
Subject: [PATCH 0077/2085] Use byte copy.

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index f486e0eed..a46fa2cf1 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -243,7 +243,9 @@ static void dcd_ep_handler(uint8_t ep_ix)
         uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
         if (xfer->buffer)
         {
-          memcpy(xfer->buffer + xfer->queued_len, ptr, count);
+          //memcpy(xfer->buffer + xfer->queued_len, ptr, count);
+          for(int i = 0; i < count; i++)
+            xfer->buffer[i + xfer->queued_len] = ptr[i];
         } else {
           tu_fifo_write_n(xfer->fifo, ptr, count);
         }
@@ -283,7 +285,9 @@ static void dcd_ep_handler(uint8_t ep_ix)
         uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
         if (xfer->buffer)
         {
-          memcpy(xfer->buffer + xfer->queued_len, ptr, count);
+          //memcpy(xfer->buffer + xfer->queued_len, ptr, count);
+          for(int i = 0; i < count; i++)
+            xfer->buffer[i + xfer->queued_len] = ptr[i];
         } else {
           tu_fifo_write_n(xfer->fifo, ptr, count);
         }
@@ -535,7 +539,9 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
   uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
   if(xfer->buffer)
   {
-    memcpy(ptr, xfer->buffer + xfer->queued_len, len);
+    //memcpy(ptr, xfer->buffer + xfer->queued_len, len);
+    for(int i = 0; i < len; i++)
+      ptr[i] = xfer->buffer[i + xfer->queued_len];
   }
   else {
     tu_fifo_read_n(xfer->fifo, ptr, len);
@@ -569,6 +575,11 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->queued_len = 0;
   xfer->fifo = NULL;
 
+  TU_LOG3("Xfer: ");
+  for(int i = 0; i < total_bytes; i++)
+    TU_LOG3("%02X ", buffer[i]);
+  TU_LOG3("\r\n");
+  
   if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {
     uint32_t udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);

From 6cc702e9ece9bbf32ac9ad4283407b4937c671a9 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 15 Jun 2021 21:16:51 +0200
Subject: [PATCH 0078/2085] Prevent buffer overflow.

Signed-off-by: MasterPhi <admin@hifiphile.com>
---
 src/portable/microchip/samx7x/dcd_samx7x.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index a46fa2cf1..848febc66 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -238,8 +238,13 @@ static void dcd_ep_handler(uint8_t ep_ix)
     if (int_status & USBHS_DEVEPTISR_RXOUTI)
     {
       xfer_ctl_t *xfer = &xfer_status[0];
-      if (count)
+      if (count && xfer->total_len)
       {
+        uint16_t remain = xfer->total_len - xfer->queued_len;
+        if (count > remain)
+        {
+          count = remain;
+        }
         uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
         if (xfer->buffer)
         {
@@ -256,7 +261,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
       {
         // RX COMPLETE
-        dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+        dcd_event_xfer_complete(0, 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt
         USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
         // Though the host could still send, we don't know.
@@ -280,8 +285,13 @@ static void dcd_ep_handler(uint8_t ep_ix)
     if (int_status & USBHS_DEVEPTISR_RXOUTI)
     {
       xfer_ctl_t *xfer = &xfer_status[ep_ix];
-      if (count)
+      if (count && xfer->total_len)
       {
+        uint16_t remain = xfer->total_len - xfer->queued_len;
+        if (count > remain)
+        {
+          count = remain;
+        }
         uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
         if (xfer->buffer)
         {

From 67a6560ec9f379418cccc312ee09bb021e464716 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 15 Jun 2021 21:34:42 +0200
Subject: [PATCH 0079/2085] Default use dual bank for FS, use dcd irq switch.

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 848febc66..a9e125b7c 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -49,7 +49,7 @@
 #  if TUD_OPT_HIGH_SPEED
 #    define USE_DUAL_BANK   0
 #  else
-#    define USE_DUAL_BANK   0
+#    define USE_DUAL_BANK   1
 #  endif
 #endif
 
@@ -151,8 +151,7 @@ void dcd_remote_wakeup (uint8_t rhport)
 void dcd_connect(uint8_t rhport)
 {
   (void) rhport;
-  uint32_t irq_state = __get_PRIMASK();
-  __disable_irq();
+  dcd_int_disable(rhport);
   // Enable USB clock
   PMC->PMC_PCER1 = 1 << (ID_USBHS - 32);
   // Enable the USB controller in device mode
@@ -178,15 +177,13 @@ void dcd_connect(uint8_t rhport)
   USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH;
   // Freeze USB clock
   USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
-  __set_PRIMASK(irq_state);
 }
 
 // Disconnect by disabling internal pull-up resistor on D+/D-
 void dcd_disconnect(uint8_t rhport)
 {
   (void) rhport;
-  uint32_t irq_state = __get_PRIMASK();
-  __disable_irq();
+  dcd_int_disable(rhport);
   // Disable all endpoints
   USBHS->USBHS_DEVEPT &= ~(0x3FF << USBHS_DEVEPT_EPEN0_Pos);
   // Unfreeze USB clock
@@ -200,7 +197,6 @@ void dcd_disconnect(uint8_t rhport)
   USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH;
   // Disable the device address
   USBHS->USBHS_DEVCTRL &=~(USBHS_DEVCTRL_ADDEN | USBHS_DEVCTRL_UADD_Msk);
-  __set_PRIMASK(irq_state);
 }
 
 static tusb_speed_t get_speed(void)
@@ -584,11 +580,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
   xfer->fifo = NULL;
-
-  TU_LOG3("Xfer: ");
-  for(int i = 0; i < total_bytes; i++)
-    TU_LOG3("%02X ", buffer[i]);
-  TU_LOG3("\r\n");
   
   if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {

From 30fff56aa4b3e75dd14b95cf21484e7342088997 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 16 Jun 2021 00:18:38 +0200
Subject: [PATCH 0080/2085] Revert "Use byte copy.", add barrier after buffer
 write.

Signed-off-by: MasterPhi <admin@hifiphile.com>
---
 src/portable/microchip/samx7x/dcd_samx7x.c | 38 ++++++++++------------
 1 file changed, 18 insertions(+), 20 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index a9e125b7c..0299d12b9 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -244,9 +244,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
         if (xfer->buffer)
         {
-          //memcpy(xfer->buffer + xfer->queued_len, ptr, count);
-          for(int i = 0; i < count; i++)
-            xfer->buffer[i + xfer->queued_len] = ptr[i];
+          memcpy(xfer->buffer + xfer->queued_len, ptr, count);
         } else {
           tu_fifo_write_n(xfer->fifo, ptr, count);
         }
@@ -291,9 +289,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
         if (xfer->buffer)
         {
-          //memcpy(xfer->buffer + xfer->queued_len, ptr, count);
-          for(int i = 0; i < count; i++)
-            xfer->buffer[i + xfer->queued_len] = ptr[i];
+          memcpy(xfer->buffer + xfer->queued_len, ptr, count);
         } else {
           tu_fifo_write_n(xfer->fifo, ptr, count);
         }
@@ -538,26 +534,28 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
 {
   uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
-  if (len > xfer->max_packet_size)
+  if (len)
   {
-    len = xfer->max_packet_size;
+    if (len > xfer->max_packet_size)
+    {
+      len = xfer->max_packet_size;
+    }
+    uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
+    if(xfer->buffer)
+    {
+      memcpy(ptr, xfer->buffer + xfer->queued_len, len);
+    }
+    else {
+      tu_fifo_read_n(xfer->fifo, ptr, len);
+    }
+    __DSB();
+    __ISB();
+    xfer->queued_len = (uint16_t)(xfer->queued_len + len);
   }
-  uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix,8);
-  if(xfer->buffer)
-  {
-    //memcpy(ptr, xfer->buffer + xfer->queued_len, len);
-    for(int i = 0; i < len; i++)
-      ptr[i] = xfer->buffer[i + xfer->queued_len];
-  }
-  else {
-    tu_fifo_read_n(xfer->fifo, ptr, len);
-  }
-  xfer->queued_len = (uint16_t)(xfer->queued_len + len);
   if (ep_ix == 0U)
   {
     // Control endpoint: clear the interrupt flag to send the data
     USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
-
   } else {
     // Other endpoint types: clear the FIFO control flag to send the data
     USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;

From 832d22d7addf9b1e4b88556c544f60bd9fa32dd6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Jun 2021 01:55:35 +0700
Subject: [PATCH 0081/2085] force single buffered for device mode, out endpoint

---
 src/device/usbd.c                            |  3 +-
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 15 +++---
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 52 +++++++++++++++++---
 src/portable/raspberrypi/rp2040/rp2040_usb.h |  4 +-
 4 files changed, 55 insertions(+), 19 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 2935defd0..587d487dc 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1254,14 +1254,13 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 
   if ( dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes) )
   {
-    TU_LOG2("OK\r\n");
     return true;
   }else
   {
     // DCD error, mark endpoint as ready to allow next transfer
     _usbd_dev.ep_status[epnum][dir].busy = false;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
-    TU_LOG2("failed\r\n");
+    TU_LOG2("FAILED\r\n");
     TU_BREAKPOINT();
     return false;
   }
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index b87951421..f78a932f1 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -145,6 +145,7 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t ep_addr, uint16_t
 
         // Now if it hasn't already been done
         //alloc a buffer and fill in endpoint control register
+        // TODO device may change configuration (dynamic), should clear and reallocate
         if(!(ep->configured))
         {
             _hw_endpoint_alloc(ep);
@@ -194,9 +195,6 @@ static void hw_handle_buff_status(void)
     {
         if (remaining_buffers & bit)
         {
-            uint __unused which = (usb_hw->buf_cpu_should_handle & bit) ? 1 : 0;
-            // Should be single buffered
-            assert(which == 0);
             // clear this in advance
             usb_hw_clear->buf_status = bit;
             // IN transfer for even i, OUT transfer for odd i
@@ -463,7 +461,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
 
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
-    pico_info("dcd_edpt_open %d %02x\n", rhport, desc_edpt->bEndpointAddress);
+    pico_info("dcd_edpt_open %02x\n", desc_edpt->bEndpointAddress);
     assert(rhport == 0);
     hw_endpoint_init(desc_edpt->bEndpointAddress, desc_edpt->wMaxPacketSize.size, desc_edpt->bmAttributes.xfer);
     return true;
@@ -478,14 +476,14 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 
 void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
-    pico_trace("dcd_edpt_stall %d %02x\n", rhport, ep_addr);
+    pico_trace("dcd_edpt_stall %02x\n", ep_addr);
     assert(rhport == 0);
     hw_endpoint_stall(ep_addr);
 }
 
 void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
-    pico_trace("dcd_edpt_clear_stall %d %02x\n", rhport, ep_addr);
+    pico_trace("dcd_edpt_clear_stall %02x\n", ep_addr);
     assert(rhport == 0);
     hw_endpoint_clear_stall(ep_addr);
 }
@@ -493,8 +491,11 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
+    (void) rhport;
+    (void) ep_addr;
+
     // usbd.c says: In progress transfers on this EP may be delivered after this call
-    pico_trace("dcd_edpt_close %d %02x\n", rhport, ep_addr);
+    pico_trace("dcd_edpt_close %02x\n", ep_addr);
 }
 
 void dcd_int_handler(uint8_t rhport)
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 5b2a5f5a0..dc12e6d82 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -148,10 +148,15 @@ static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
 {
   uint32_t ep_ctrl = *ep->endpoint_control;
 
-  // always compute buffer 0
-  uint32_t buf_ctrl = prepare_ep_buffer(ep, 0);
+  // always compute and start with buffer 0
+  uint32_t buf_ctrl = prepare_ep_buffer(ep, 0) | USB_BUF_CTRL_SEL;
 
-  if(ep->remaining_len)
+  // For now: skip double buffered for Device mode, OUT endpoint since
+  // host could send < 64 bytes and cause short packet on buffer0
+  // NOTE this could happen to Host mode IN endpoint
+  bool const force_single = !(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr);
+
+  if(ep->remaining_len && !force_single)
   {
     // Use buffer 1 (double buffered) if there is still data
     // TODO: Isochronous for buffer1 bit-field is different than CBI (control bulk, interrupt)
@@ -181,8 +186,7 @@ static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
 void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len)
 {
   _hw_endpoint_lock_update(ep, 1);
-  pico_trace("Start transfer of total len %d on ep %d %s\n", total_len, tu_edpt_number(ep->ep_addr),
-             ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+
   if ( ep->active )
   {
     // TODO: Is this acceptable for interrupt packets?
@@ -251,10 +255,42 @@ static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
   // always sync buffer 0
   uint16_t buf0_bytes = sync_ep_buffer(ep, 0);
 
-  // sync buffer 1 if double buffered and buffer 0 is not short packet
-  if ( ((*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS) && (buf0_bytes == ep->wMaxPacketSize) )
+  // sync buffer 1 if double buffered
+  if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS )
   {
-    sync_ep_buffer(ep, 1);
+    if (buf0_bytes == ep->wMaxPacketSize)
+    {
+      // sync buffer 1 if not short packet
+      sync_ep_buffer(ep, 1);
+    }else
+    {
+      // short packet on buffer 0
+      // TODO couldn't figure out how to handle this case which happen with net_lwip_webserver example
+      // At this time (currently trigger per 2 buffer), the buffer1 is probably filled with data from
+      // the next transfer (not current one). For now we disable double buffered for device OUT
+      // NOTE this could happen to Host IN
+#if 0
+      uint8_t const ep_num = tu_edpt_number(ep->ep_addr);
+      uint8_t const dir =  (uint8_t) tu_edpt_dir(ep->ep_addr);
+      uint8_t const ep_id = 2*ep_num + (dir ? 0 : 1);
+
+      // abort queued transfer on buffer 1
+      usb_hw->abort |= TU_BIT(ep_id);
+
+      while ( !(usb_hw->abort_done & TU_BIT(ep_id)) ) {}
+
+      uint32_t ep_ctrl = *ep->endpoint_control;
+      ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
+      ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
+
+      _hw_endpoint_buffer_control_set_value32(ep, 0);
+
+      usb_hw->abort &= ~TU_BIT(ep_id);
+
+      TU_LOG(3, "----SHORT PACKET buffer0 on EP %02X:\r\n", ep->ep_addr);
+      print_bufctrl32(buf_ctrl);
+#endif
+    }
   }
 }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 4c787f496..514152cd9 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -120,8 +120,8 @@ static inline void print_bufctrl16(uint32_t u16)
       .u16 = u16
   };
 
-  TU_LOG(3, "len = %u, available = %u, stall = %u, reset = %u, toggle = %u, last = %u, full = %u\r\n",
-         bufctrl.xfer_len, bufctrl.available, bufctrl.stall, bufctrl.reset_bufsel, bufctrl.data_toggle, bufctrl.last_buf, bufctrl.full);
+  TU_LOG(3, "len = %u, available = %u, full = %u, last = %u, stall = %u, reset = %u, toggle = %u\r\n",
+         bufctrl.xfer_len, bufctrl.available, bufctrl.full, bufctrl.last_buf, bufctrl.stall, bufctrl.reset_bufsel, bufctrl.data_toggle);
 }
 
 static inline void print_bufctrl32(uint32_t u32)

From 3ba72b53d88a5eb08004c9c3c4edf7101066eb3f Mon Sep 17 00:00:00 2001
From: zhangslice <1304224508@qq.com>
Date: Wed, 2 Jun 2021 09:46:48 +0800
Subject: [PATCH 0082/2085] Add MM32 SDK and USB driver

Signed-off-by: zhangslice <1304224508@qq.com>
---
 .../CMSIS/IAR_Core/arm_common_tables.h        |  121 +
 .../CMSIS/IAR_Core/arm_const_structs.h        |   66 +
 .../mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h  | 7122 +++++++++++++++++
 .../mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h    |  796 ++
 .../mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h | 1735 ++++
 .../mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h |  231 +
 .../mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h | 1900 +++++
 .../mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h  | 1813 +++++
 .../mm32f327x/CMSIS/IAR_Core/core_armv8mml.h  | 2821 +++++++
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h  |  850 ++
 .../mm32f327x/CMSIS/IAR_Core/core_cm0plus.h   |  975 +++
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h | 1813 +++++
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h  | 1880 +++++
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h | 2821 +++++++
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h  | 2061 +++++
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h  | 2592 ++++++
 .../mm32f327x/CMSIS/IAR_Core/core_sc000.h     |  976 +++
 .../mm32f327x/CMSIS/IAR_Core/core_sc300.h     | 1851 +++++
 .../mm32f327x/CMSIS/IAR_Core/tz_context.h     |   69 +
 .../CMSIS/KEIL_Core/arm_common_tables.h       |  121 +
 .../CMSIS/KEIL_Core/arm_const_structs.h       |   66 +
 .../mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h | 7122 +++++++++++++++++
 .../mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h   |  796 ++
 .../CMSIS/KEIL_Core/cmsis_armclang.h          | 1735 ++++
 .../CMSIS/KEIL_Core/cmsis_compiler.h          |  231 +
 .../mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h     | 1900 +++++
 .../mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h | 1813 +++++
 .../mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h | 2821 +++++++
 .../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h |  850 ++
 .../mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h  |  975 +++
 .../mm32f327x/CMSIS/KEIL_Core/core_cm23.h     | 1813 +++++
 .../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h | 1880 +++++
 .../mm32f327x/CMSIS/KEIL_Core/core_cm33.h     | 2821 +++++++
 .../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h | 2061 +++++
 .../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h | 2592 ++++++
 .../mm32f327x/CMSIS/KEIL_Core/core_sc000.h    |  976 +++
 .../mm32f327x/CMSIS/KEIL_Core/core_sc300.h    | 1851 +++++
 .../mm32f327x/CMSIS/KEIL_Core/tz_context.h    |   69 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h   |   33 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h |  341 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h |  130 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h |  340 +
 .../MM32F327x/HAL_Lib/Inc/hal_comp.h          |  228 +
 .../MM32F327x/HAL_Lib/Inc/hal_conf.h          |   62 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h |   84 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h |   46 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h |  166 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h |   72 +
 .../MM32F327x/HAL_Lib/Inc/hal_device.h        |   41 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h |  306 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h |  729 ++
 .../MM32F327x/HAL_Lib/Inc/hal_eth_conf.h      |   68 +
 .../MM32F327x/HAL_Lib/Inc/hal_exti.h          |  181 +
 .../MM32F327x/HAL_Lib/Inc/hal_flash.h         |  230 +
 .../MM32F327x/HAL_Lib/Inc/hal_fsmc.h          |  147 +
 .../MM32F327x/HAL_Lib/Inc/hal_gpio.h          |  198 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h |  255 +
 .../MM32F327x/HAL_Lib/Inc/hal_iwdg.h          |  130 +
 .../MM32F327x/HAL_Lib/Inc/hal_misc.h          |  128 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h |  156 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h |  329 +
 .../MM32F327x/HAL_Lib/Inc/hal_redefine.h      |  102 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h |  114 +
 .../MM32F327x/HAL_Lib/Inc/hal_sdio.h          |  503 ++
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h |  351 +
 .../MM32F327x/HAL_Lib/Inc/hal_syscfg.h        |   83 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h |  755 ++
 .../MM32F327x/HAL_Lib/Inc/hal_uart.h          |  211 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h |   71 +
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h |   89 +
 .../MM32F327x/HAL_Lib/Inc/hal_wwdg.h          |   90 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c |  563 ++
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c |  231 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c |  696 ++
 .../MM32F327x/HAL_Lib/Src/hal_comp.c          |  226 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c |  108 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c |   43 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c |  184 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c |   53 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c |  319 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c |  836 ++
 .../MM32F327x/HAL_Lib/Src/hal_exti.c          |  222 +
 .../MM32F327x/HAL_Lib/Src/hal_flash.c         |  548 ++
 .../MM32F327x/HAL_Lib/Src/hal_fsmc.c          |  124 +
 .../MM32F327x/HAL_Lib/Src/hal_gpio.c          |  344 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c |  526 ++
 .../MM32F327x/HAL_Lib/Src/hal_iwdg.c          |  208 +
 .../MM32F327x/HAL_Lib/Src/hal_misc.c          |  147 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c |  215 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c |  995 +++
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c |  234 +
 .../MM32F327x/HAL_Lib/Src/hal_sdio.c          |  527 ++
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c |  648 ++
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c | 1875 +++++
 .../MM32F327x/HAL_Lib/Src/hal_uart.c          |  502 ++
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c |   55 +
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c |  131 +
 .../MM32F327x/HAL_Lib/Src/hal_wwdg.c          |  147 +
 .../mm32f327x/MM32F327x/Include/mm32_device.h |   23 +
 .../mm32f327x/MM32F327x/Include/mm32_reg.h    |   71 +
 .../MM32F327x/Include/mm32_reg_redefine_v1.h  | 1175 +++
 .../mm32f327x/MM32F327x/Include/reg_adc.h     |  953 +++
 .../mm32f327x/MM32F327x/Include/reg_bkp.h     |  147 +
 .../mm32f327x/MM32F327x/Include/reg_can.h     |  532 ++
 .../mm32f327x/MM32F327x/Include/reg_common.h  |  643 ++
 .../mm32f327x/MM32F327x/Include/reg_comp.h    |  228 +
 .../mm32f327x/MM32F327x/Include/reg_crc.h     |  102 +
 .../mm32f327x/MM32F327x/Include/reg_crs.h     |  152 +
 .../mm32f327x/MM32F327x/Include/reg_dac.h     |  247 +
 .../mm32f327x/MM32F327x/Include/reg_dbg.h     |  113 +
 .../mm32f327x/MM32F327x/Include/reg_dma.h     |  325 +
 .../mm32f327x/MM32F327x/Include/reg_eth.h     |  730 ++
 .../mm32f327x/MM32F327x/Include/reg_exti.h    |  544 ++
 .../mm32f327x/MM32F327x/Include/reg_flash.h   |  290 +
 .../mm32f327x/MM32F327x/Include/reg_fsmc.h    |  194 +
 .../mm32f327x/MM32F327x/Include/reg_gpio.h    |  706 ++
 .../mm32f327x/MM32F327x/Include/reg_i2c.h     |  635 ++
 .../mm32f327x/MM32F327x/Include/reg_iwdg.h    |  125 +
 .../mm32f327x/MM32F327x/Include/reg_pwm.h     |   72 +
 .../mm32f327x/MM32F327x/Include/reg_pwr.h     |  219 +
 .../mm32f327x/MM32F327x/Include/reg_rcc.h     |  654 ++
 .../mm32f327x/MM32F327x/Include/reg_rtc.h     |  203 +
 .../mm32f327x/MM32F327x/Include/reg_sdio.h    |  391 +
 .../mm32f327x/MM32F327x/Include/reg_spi.h     |  359 +
 .../mm32f327x/MM32F327x/Include/reg_syscfg.h  |  299 +
 .../mm32f327x/MM32F327x/Include/reg_tim.h     |  681 ++
 .../mm32f327x/MM32F327x/Include/reg_uart.h    |  362 +
 .../MM32F327x/Include/reg_usb_otg_fs.h        |  923 +++
 .../mm32f327x/MM32F327x/Include/reg_wwdg.h    |  133 +
 .../mm32/mm32f327x/MM32F327x/Include/types.h  |  105 +
 .../GCC_StartAsm/startup_mm32m3ux_u_gcc.S     |  440 +
 .../MM32F327x/Source/system_mm32f327x.c       |  866 ++
 src/portable/mm32/dcd_mm32f327x_otg.c         |  462 ++
 133 files changed, 96566 insertions(+)
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h
 create mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
 create mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c
 create mode 100644 src/portable/mm32/dcd_mm32f327x_otg.c

diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h
new file mode 100644
index 000000000..dfea7460e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_common_tables.h
+ * Description:  Extern declaration for common tables
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h
new file mode 100644
index 000000000..84ffe8b85
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_const_structs.h
+ * Description:  Constant structs that are initialized for user convenience.
+ *               For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h
new file mode 100644
index 000000000..9d678052b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h
@@ -0,0 +1,7122 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_math.h
+ * Description:  Public header file for CMSIS DSP Library
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+   * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
+   * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
+   * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
+   * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
+   * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+   * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
+   *
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - ARM_MATH_ARMV8MxL:
+   *
+   * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
+   * on ARMv8M Mainline target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+   *
+   * - __DSP_PRESENT:
+   *
+   * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+#include "core_cm7.h"
+#define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+#include "core_armv8mbl.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+#include "core_armv8mml.h"
+#if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+#define ARM_MATH_DSP
+#endif
+#else
+#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31          (0x100)
+#define DELTA_Q15          0x5
+#define INDEX_MASK         0x0000003F
+#ifndef PI
+#define PI               3.14159265358979f
+#endif
+
+/**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+/**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+/* 1.31(q31) Fixed value of 2/360 */
+/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING         0xB60B61
+
+/**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+#define ALIGN4
+#else
+#if defined  (__GNUC__)
+#define ALIGN4 __attribute__((aligned(4)))
+#else
+#define ALIGN4 __align(4)
+#endif
+#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @brief Error status returned by some functions in the library.
+ */
+
+typedef enum {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+} arm_status;
+
+/**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+typedef int8_t q7_t;
+
+/**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+typedef int16_t q15_t;
+
+/**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+typedef int32_t q31_t;
+
+/**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+typedef int64_t q63_t;
+
+/**
+ * @brief 32-bit floating-point type definition.
+ */
+typedef float float32_t;
+
+/**
+ * @brief 64-bit floating-point type definition.
+ */
+typedef double float64_t;
+
+/**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if   defined ( __CC_ARM )
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+#define __SIMD32_TYPE __unaligned int32_t
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+#define __SIMD64(addr)        (*(int64_t **) & (addr))
+
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+/**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
+                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
+                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+/**
+* @brief definition to pack four 8 bit values.
+*/
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+/**
+ * @brief Clips Q63 to Q31 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+    q63_t x)
+{
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+           ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+}
+
+/**
+ * @brief Clips Q63 to Q15 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+    q63_t x)
+{
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+           ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+}
+
+/**
+ * @brief Clips Q31 to Q7 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+    q31_t x)
+{
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+           ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+}
+
+/**
+ * @brief Clips Q31 to Q15 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+    q31_t x)
+{
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+           ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+}
+
+/**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+    q63_t x,
+    q31_t y)
+{
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+}
+
+/*
+  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+  #define __CLZ __clz
+  #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+    q31_t data);
+
+CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+    q31_t data)
+{
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while ((data & mask) == 0) {
+        count += 1u;
+        mask = mask >> 1u;
+    }
+
+    return (count);
+}
+#endif
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+    q31_t in,
+    q31_t* dst,
+    q31_t* pRecipTable)
+{
+    q31_t out;
+    uint32_t tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if (in > 0) {
+        signBits = ((uint32_t) (__CLZ( in) - 1));
+    }
+    else {
+        signBits = ((uint32_t) (__CLZ(-in) - 1));
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >> 24);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++) {
+        tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+        tempVal = 0x7FFFFFFFu - tempVal;
+        /*      1.31 with exp 1 */
+        /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+        out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+}
+
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+    q15_t in,
+    q15_t* dst,
+    q15_t* pRecipTable)
+{
+    q15_t out = 0;
+    uint32_t tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if (in > 0) {
+        signBits = ((uint32_t)(__CLZ( in) - 17));
+    }
+    else {
+        signBits = ((uint32_t)(__CLZ(-in) - 17));
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >>  8);
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++) {
+        tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+        tempVal = 0x7FFFu - tempVal;
+        /*      1.15 with exp 1 */
+        out = (q15_t) (((q31_t) out * tempVal) >> 14);
+        /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+}
+
+
+/*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
+    q31_t x,
+    uint32_t y)
+{
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++) {
+        posMax = posMax * 2;
+    }
+
+    if (x > 0) {
+        posMax = (posMax - 1);
+
+        if (x > posMax) {
+            x = posMax;
+        }
+    }
+    else {
+        negMin = -posMax;
+
+        if (x < negMin) {
+            x = negMin;
+        }
+    }
+    return (x);
+}
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+
+/*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+    uint32_t x,
+    uint32_t y)
+{
+    /*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
+    q31_t r = 0, s = 0;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+    uint32_t x,
+    uint32_t y)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+}
+
+/*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+    uint32_t x,
+    uint32_t y)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+}
+
+
+/*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+    int32_t x,
+    int32_t y)
+{
+    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+}
+
+
+/*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+    int32_t x,
+    int32_t y)
+{
+    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+}
+
+
+/*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+    uint32_t x,
+    uint32_t y,
+    uint32_t sum)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+}
+
+
+/*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+    uint32_t x,
+    uint32_t y,
+    uint32_t sum)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+}
+
+
+/*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+    uint32_t x,
+    uint32_t y,
+    uint32_t sum)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+}
+
+
+/*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+    uint32_t x,
+    uint32_t y,
+    uint64_t sum)
+{
+    /*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+}
+
+
+/*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+    uint32_t x,
+    uint32_t y,
+    uint64_t sum)
+{
+    /*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+}
+
+
+/*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+    uint32_t x,
+    uint32_t y)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+}
+
+
+/*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+    uint32_t x,
+    uint32_t y)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+}
+
+
+/*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+    uint32_t x)
+{
+    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
+}
+
+/*
+ * @brief C custom defined SMMLA for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+    int32_t x,
+    int32_t y,
+    int32_t sum)
+{
+    return (sum + (int32_t) (((int64_t) x * y) >> 32));
+}
+
+#if 0
+/*
+ * @brief C custom defined PKHBT for unavailable DSP extension
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
+    uint32_t x,
+    uint32_t y,
+    uint32_t leftshift)
+{
+    return ( ((x             ) & 0x0000FFFFUL) |
+             ((y << leftshift) & 0xFFFF0000UL)  );
+}
+
+/*
+ * @brief C custom defined PKHTB for unavailable DSP extension
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
+    uint32_t x,
+    uint32_t y,
+    uint32_t rightshift)
+{
+    return ( ((x              ) & 0xFFFF0000UL) |
+             ((y >> rightshift) & 0x0000FFFFUL)  );
+}
+#endif
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+/**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q7;
+
+/**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in]  S          points to an instance of the Q7 FIR filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_q7(
+    const arm_fir_instance_q7* S,
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q7 FIR filter.
+ * @param[in,out] S          points to an instance of the Q7 FIR structure.
+ * @param[in]     numTaps    Number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of samples that are processed.
+ */
+void arm_fir_init_q7(
+    arm_fir_instance_q7* S,
+    uint16_t numTaps,
+    q7_t* pCoeffs,
+    q7_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in]  S          points to an instance of the Q15 FIR structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_q15(
+    const arm_fir_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q15 FIR filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_fast_q15(
+    const arm_fir_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 FIR filter.
+ * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
+ * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+arm_status arm_fir_init_q15(
+    arm_fir_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in]  S          points to an instance of the Q31 FIR filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_q31(
+    const arm_fir_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q31 FIR structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_fast_q31(
+    const arm_fir_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 FIR filter.
+ * @param[in,out] S          points to an instance of the Q31 FIR structure.
+ * @param[in]     numTaps    Number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of samples that are processed at a time.
+ */
+void arm_fir_init_q31(
+    arm_fir_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in]  S          points to an instance of the floating-point FIR structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_f32(
+    const arm_fir_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point FIR filter.
+ * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
+ * @param[in]     numTaps    Number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of samples that are processed at a time.
+ */
+void arm_fir_init_f32(
+    arm_fir_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+typedef struct {
+    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t* pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t* pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
+} arm_biquad_casd_df1_inst_q15;
+
+/**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+typedef struct {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t* pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t* pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+} arm_biquad_casd_df1_inst_q31;
+
+/**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+typedef struct {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t* pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_casd_df1_inst_f32;
+
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df1_q15(
+    const arm_biquad_casd_df1_inst_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cascade_df1_init_q15(
+    arm_biquad_casd_df1_inst_q15* S,
+    uint8_t numStages,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    int8_t postShift);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df1_fast_q15(
+    const arm_biquad_casd_df1_inst_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df1_q31(
+    const arm_biquad_casd_df1_inst_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df1_fast_q31(
+    const arm_biquad_casd_df1_inst_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cascade_df1_init_q31(
+    arm_biquad_casd_df1_inst_q31* S,
+    uint8_t numStages,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    int8_t postShift);
+
+
+/**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df1_f32(
+    const arm_biquad_casd_df1_inst_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ */
+void arm_biquad_cascade_df1_init_f32(
+    arm_biquad_casd_df1_inst_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t* pData;     /**< points to the data of the matrix. */
+} arm_matrix_instance_f32;
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t* pData;     /**< points to the data of the matrix. */
+} arm_matrix_instance_f64;
+
+/**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t* pData;         /**< points to the data of the matrix. */
+} arm_matrix_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t* pData;         /**< points to the data of the matrix. */
+} arm_matrix_instance_q31;
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in]   pSrcA  points to the first input matrix structure
+ * @param[in]   pSrcB  points to the second input matrix structure
+ * @param[out]  pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15, complex,  matrix multiplication.
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pScratch);
+
+
+/**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in]  pSrc  points to the input matrix
+ * @param[out] pDst  points to the output matrix
+ * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f32(
+    const arm_matrix_instance_f32* pSrc,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix transpose.
+ * @param[in]  pSrc  points to the input matrix
+ * @param[out] pDst  points to the output matrix
+ * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q15(
+    const arm_matrix_instance_q15* pSrc,
+    arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix transpose.
+ * @param[in]  pSrc  points to the input matrix
+ * @param[out] pDst  points to the output matrix
+ * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q31(
+    const arm_matrix_instance_q31* pSrc,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix multiplication
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in]  pSrcA   points to the first input matrix structure
+ * @param[in]  pSrcB   points to the second input matrix structure
+ * @param[out] pDst    points to output matrix structure
+ * @param[in]  pState  points to the array for storing intermediate results
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pState);
+
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA   points to the first input matrix structure
+ * @param[in]  pSrcB   points to the second input matrix structure
+ * @param[out] pDst    points to output matrix structure
+ * @param[in]  pState  points to the array for storing intermediate results
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pState);
+
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix subtraction
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix subtraction
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in]  pSrc   points to the input matrix
+ * @param[in]  scale  scale factor
+ * @param[out] pDst   points to the output matrix
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f32(
+    const arm_matrix_instance_f32* pSrc,
+    float32_t scale,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in]  pSrc        points to input matrix
+ * @param[in]  scaleFract  fractional portion of the scale factor
+ * @param[in]  shift       number of bits to shift the result by
+ * @param[out] pDst        points to output matrix
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q15(
+    const arm_matrix_instance_q15* pSrc,
+    q15_t scaleFract,
+    int32_t shift,
+    arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in]  pSrc        points to input matrix
+ * @param[in]  scaleFract  fractional portion of the scale factor
+ * @param[in]  shift       number of bits to shift the result by
+ * @param[out] pDst        points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q31(
+    const arm_matrix_instance_q31* pSrc,
+    q31_t scaleFract,
+    int32_t shift,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief  Q31 matrix initialization.
+ * @param[in,out] S         points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows     number of rows in the matrix.
+ * @param[in]     nColumns  number of columns in the matrix.
+ * @param[in]     pData     points to the matrix data array.
+ */
+void arm_mat_init_q31(
+    arm_matrix_instance_q31* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    q31_t* pData);
+
+
+/**
+ * @brief  Q15 matrix initialization.
+ * @param[in,out] S         points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows     number of rows in the matrix.
+ * @param[in]     nColumns  number of columns in the matrix.
+ * @param[in]     pData     points to the matrix data array.
+ */
+void arm_mat_init_q15(
+    arm_matrix_instance_q15* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    q15_t* pData);
+
+
+/**
+ * @brief  Floating-point matrix initialization.
+ * @param[in,out] S         points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows     number of rows in the matrix.
+ * @param[in]     nColumns  number of columns in the matrix.
+ * @param[in]     pData     points to the matrix data array.
+ */
+void arm_mat_init_f32(
+    arm_matrix_instance_f32* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    float32_t* pData);
+
+
+
+/**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+typedef struct {
+    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];     /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+} arm_pid_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+typedef struct {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+} arm_pid_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+typedef struct {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;          /**< The proportional gain. */
+    float32_t Ki;          /**< The integral gain. */
+    float32_t Kd;          /**< The derivative gain. */
+} arm_pid_instance_f32;
+
+
+
+/**
+ * @brief  Initialization function for the floating-point PID Control.
+ * @param[in,out] S               points to an instance of the PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_f32(
+    arm_pid_instance_f32* S,
+    int32_t resetStateFlag);
+
+
+/**
+ * @brief  Reset function for the floating-point PID Control.
+ * @param[in,out] S  is an instance of the floating-point PID Control structure
+ */
+void arm_pid_reset_f32(
+    arm_pid_instance_f32* S);
+
+
+/**
+ * @brief  Initialization function for the Q31 PID Control.
+ * @param[in,out] S               points to an instance of the Q15 PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_q31(
+    arm_pid_instance_q31* S,
+    int32_t resetStateFlag);
+
+
+/**
+ * @brief  Reset function for the Q31 PID Control.
+ * @param[in,out] S   points to an instance of the Q31 PID Control structure
+ */
+
+void arm_pid_reset_q31(
+    arm_pid_instance_q31* S);
+
+
+/**
+ * @brief  Initialization function for the Q15 PID Control.
+ * @param[in,out] S               points to an instance of the Q15 PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_q15(
+    arm_pid_instance_q15* S,
+    int32_t resetStateFlag);
+
+
+/**
+ * @brief  Reset function for the Q15 PID Control.
+ * @param[in,out] S  points to an instance of the q15 PID Control structure
+ */
+void arm_pid_reset_q15(
+    arm_pid_instance_q15* S);
+
+
+/**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+typedef struct {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t* pYData;          /**< pointer to the table of Y values */
+} arm_linear_interp_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t* pData;   /**< points to the data table. */
+} arm_bilinear_interp_instance_f32;
+
+/**
+* @brief Instance structure for the Q31 bilinear interpolation function.
+*/
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t* pData;       /**< points to the data table. */
+} arm_bilinear_interp_instance_q31;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t* pData;       /**< points to the data table. */
+} arm_bilinear_interp_instance_q15;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t* pData;        /**< points to the data table. */
+} arm_bilinear_interp_instance_q7;
+
+
+/**
+ * @brief Q7 vector multiplication.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_mult_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector multiplication.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_mult_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_mult_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_mult_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t* pTwiddle;                 /**< points to the Sin twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q15(
+    arm_cfft_radix2_instance_q15* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q15(
+    const arm_cfft_radix2_instance_q15* S,
+    q15_t* pSrc);
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t* pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q15(
+    arm_cfft_radix4_instance_q15* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_q15(
+    const arm_cfft_radix4_instance_q15* S,
+    q15_t* pSrc);
+
+/**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t* pTwiddle;                 /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q31(
+    arm_cfft_radix2_instance_q31* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q31(
+    const arm_cfft_radix2_instance_q31* S,
+    q31_t* pSrc);
+
+/**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t* pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+void arm_cfft_radix4_q31(
+    const arm_cfft_radix4_instance_q31* S,
+    q31_t* pSrc);
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q31(
+    arm_cfft_radix4_instance_q31* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+} arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_f32(
+    arm_cfft_radix2_instance_f32* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_f32(
+    const arm_cfft_radix2_instance_f32* S,
+    float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+} arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_f32(
+    arm_cfft_radix4_instance_f32* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_f32(
+    const arm_cfft_radix4_instance_f32* S,
+    float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t* pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+} arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15* S,
+    q15_t* p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t* pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+} arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31* S,
+    q31_t* p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t* pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+} arm_cfft_instance_f32;
+
+void arm_cfft_f32(
+    const arm_cfft_instance_f32* S,
+    float32_t* p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+typedef struct {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t* pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t* pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15* pCfft;       /**< points to the complex FFT instance. */
+} arm_rfft_instance_q15;
+
+arm_status arm_rfft_init_q15(
+    arm_rfft_instance_q15* S,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_q15(
+    const arm_rfft_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst);
+
+/**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+typedef struct {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t* pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t* pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31* pCfft;         /**< points to the complex FFT instance. */
+} arm_rfft_instance_q31;
+
+arm_status arm_rfft_init_q31(
+    arm_rfft_instance_q31* S,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_q31(
+    const arm_rfft_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t* pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t* pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32* pCfft;        /**< points to the complex FFT instance. */
+} arm_rfft_instance_f32;
+
+arm_status arm_rfft_init_f32(
+    arm_rfft_instance_f32* S,
+    arm_cfft_radix4_instance_f32* S_CFFT,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_f32(
+    const arm_rfft_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;             /**< length of the real sequence */
+    float32_t* pTwiddleRFFT;         /**< Twiddle factors real stage  */
+} arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+    arm_rfft_fast_instance_f32* S,
+    uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+    arm_rfft_fast_instance_f32* S,
+    float32_t* p, float32_t* pOut,
+    uint8_t ifftFlag);
+
+/**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+typedef struct {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    float32_t normalize;                 /**< normalizing factor. */
+    float32_t* pTwiddle;                 /**< points to the twiddle factor table. */
+    float32_t* pCosFactor;               /**< points to the cosFactor table. */
+    arm_rfft_instance_f32* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_f32;
+
+
+/**
+ * @brief  Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+arm_status arm_dct4_init_f32(
+    arm_dct4_instance_f32* S,
+    arm_rfft_instance_f32* S_RFFT,
+    arm_cfft_radix4_instance_f32* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    float32_t normalize);
+
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in]     pState         points to state buffer.
+ * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+ */
+void arm_dct4_f32(
+    const arm_dct4_instance_f32* S,
+    float32_t* pState,
+    float32_t* pInlineBuffer);
+
+
+/**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+typedef struct {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q31_t normalize;                     /**< normalizing factor. */
+    q31_t* pTwiddle;                     /**< points to the twiddle factor table. */
+    q31_t* pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q31* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q31;
+
+
+/**
+ * @brief  Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+arm_status arm_dct4_init_q31(
+    arm_dct4_instance_q31* S,
+    arm_rfft_instance_q31* S_RFFT,
+    arm_cfft_radix4_instance_q31* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    q31_t normalize);
+
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in]     S              points to an instance of the Q31 DCT4 structure.
+ * @param[in]     pState         points to state buffer.
+ * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+ */
+void arm_dct4_q31(
+    const arm_dct4_instance_q31* S,
+    q31_t* pState,
+    q31_t* pInlineBuffer);
+
+
+/**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+typedef struct {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q15_t normalize;                     /**< normalizing factor. */
+    q15_t* pTwiddle;                     /**< points to the twiddle factor table. */
+    q15_t* pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q15* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q15;
+
+
+/**
+ * @brief  Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+arm_status arm_dct4_init_q15(
+    arm_dct4_instance_q15* S,
+    arm_rfft_instance_q15* S_RFFT,
+    arm_cfft_radix4_instance_q15* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    q15_t normalize);
+
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in]     S              points to an instance of the Q15 DCT4 structure.
+ * @param[in]     pState         points to state buffer.
+ * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+ */
+void arm_dct4_q15(
+    const arm_dct4_instance_q15* S,
+    q15_t* pState,
+    q15_t* pInlineBuffer);
+
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_add_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_add_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_add_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_add_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_sub_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_sub_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_sub_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_sub_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  scale      scale factor to be applied
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_scale_f32(
+    float32_t* pSrc,
+    float32_t scale,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in]  pSrc        points to the input vector
+ * @param[in]  scaleFract  fractional portion of the scale value
+ * @param[in]  shift       number of bits to shift the result by
+ * @param[out] pDst        points to the output vector
+ * @param[in]  blockSize   number of samples in the vector
+ */
+void arm_scale_q7(
+    q7_t* pSrc,
+    q7_t scaleFract,
+    int8_t shift,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in]  pSrc        points to the input vector
+ * @param[in]  scaleFract  fractional portion of the scale value
+ * @param[in]  shift       number of bits to shift the result by
+ * @param[out] pDst        points to the output vector
+ * @param[in]  blockSize   number of samples in the vector
+ */
+void arm_scale_q15(
+    q15_t* pSrc,
+    q15_t scaleFract,
+    int8_t shift,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in]  pSrc        points to the input vector
+ * @param[in]  scaleFract  fractional portion of the scale value
+ * @param[in]  shift       number of bits to shift the result by
+ * @param[out] pDst        points to the output vector
+ * @param[in]  blockSize   number of samples in the vector
+ */
+void arm_scale_q31(
+    q31_t* pSrc,
+    q31_t scaleFract,
+    int8_t shift,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[out] pDst       points to the output buffer
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_abs_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[out] pDst       points to the output buffer
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_abs_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[out] pDst       points to the output buffer
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_abs_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[out] pDst       points to the output buffer
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_abs_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[in]  blockSize  number of samples in each vector
+ * @param[out] result     output result returned here
+ */
+void arm_dot_prod_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    uint32_t blockSize,
+    float32_t* result);
+
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[in]  blockSize  number of samples in each vector
+ * @param[out] result     output result returned here
+ */
+void arm_dot_prod_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    uint32_t blockSize,
+    q31_t* result);
+
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[in]  blockSize  number of samples in each vector
+ * @param[out] result     output result returned here
+ */
+void arm_dot_prod_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    uint32_t blockSize,
+    q63_t* result);
+
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[in]  blockSize  number of samples in each vector
+ * @param[out] result     output result returned here
+ */
+void arm_dot_prod_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    uint32_t blockSize,
+    q63_t* result);
+
+
+/**
+ * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_shift_q7(
+    q7_t* pSrc,
+    int8_t shiftBits,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_shift_q15(
+    q15_t* pSrc,
+    int8_t shiftBits,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_shift_q31(
+    q31_t* pSrc,
+    int8_t shiftBits,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Adds a constant offset to a floating-point vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  offset     is the offset to be added
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_offset_f32(
+    float32_t* pSrc,
+    float32_t offset,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Adds a constant offset to a Q7 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  offset     is the offset to be added
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_offset_q7(
+    q7_t* pSrc,
+    q7_t offset,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Adds a constant offset to a Q15 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  offset     is the offset to be added
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_offset_q15(
+    q15_t* pSrc,
+    q15_t offset,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Adds a constant offset to a Q31 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  offset     is the offset to be added
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_offset_q31(
+    q31_t* pSrc,
+    q31_t offset,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Negates the elements of a floating-point vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_negate_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Negates the elements of a Q7 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_negate_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Negates the elements of a Q15 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_negate_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Negates the elements of a Q31 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_negate_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Copies the elements of a floating-point vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_copy_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Copies the elements of a Q7 vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_copy_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Copies the elements of a Q15 vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_copy_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Copies the elements of a Q31 vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_copy_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Fills a constant value into a floating-point vector.
+ * @param[in]  value      input value to be filled
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_fill_f32(
+    float32_t value,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Fills a constant value into a Q7 vector.
+ * @param[in]  value      input value to be filled
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_fill_q7(
+    q7_t value,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Fills a constant value into a Q15 vector.
+ * @param[in]  value      input value to be filled
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_fill_q15(
+    q15_t value,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Fills a constant value into a Q31 vector.
+ * @param[in]  value      input value to be filled
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_fill_q31(
+    q31_t value,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+void arm_conv_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA      points to the first input sequence.
+ * @param[in]  srcALen    length of the first input sequence.
+ * @param[in]  pSrcB      points to the second input sequence.
+ * @param[in]  srcBLen    length of the second input sequence.
+ * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+ * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void arm_conv_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+void arm_conv_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+ */
+void arm_conv_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA      points to the first input sequence.
+ * @param[in]  srcALen    length of the first input sequence.
+ * @param[in]  pSrcB      points to the second input sequence.
+ * @param[in]  srcBLen    length of the second input sequence.
+ * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+ * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void arm_conv_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+ */
+void arm_conv_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+/**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+ */
+void arm_conv_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+/**
+* @brief Convolution of Q7 sequences.
+* @param[in]  pSrcA      points to the first input sequence.
+* @param[in]  srcALen    length of the first input sequence.
+* @param[in]  pSrcB      points to the second input sequence.
+* @param[in]  srcBLen    length of the second input sequence.
+* @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+* @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+*/
+void arm_conv_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+ */
+void arm_conv_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst);
+
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+arm_status arm_conv_partial_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+typedef struct {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q15_t* pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t* pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+typedef struct {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t* pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t* pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+typedef struct {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    float32_t* pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t* pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_decimate_f32(
+    const arm_fir_decimate_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
+ * @param[in]     numTaps    number of coefficients in the filter.
+ * @param[in]     M          decimation factor.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+arm_status arm_fir_decimate_init_f32(
+    arm_fir_decimate_instance_f32* S,
+    uint16_t numTaps,
+    uint8_t M,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_decimate_q15(
+    const arm_fir_decimate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_decimate_fast_q15(
+    const arm_fir_decimate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
+ * @param[in]     numTaps    number of coefficients in the filter.
+ * @param[in]     M          decimation factor.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+arm_status arm_fir_decimate_init_q15(
+    arm_fir_decimate_instance_q15* S,
+    uint16_t numTaps,
+    uint8_t M,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
+ * @param[in]  pSrc  points to the block of input data.
+ * @param[out] pDst  points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_q31(
+    const arm_fir_decimate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_decimate_fast_q31(
+    arm_fir_decimate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
+ * @param[in]     numTaps    number of coefficients in the filter.
+ * @param[in]     M          decimation factor.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+arm_status arm_fir_decimate_init_q31(
+    arm_fir_decimate_instance_q31* S,
+    uint16_t numTaps,
+    uint8_t M,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+typedef struct {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t* pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t* pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+typedef struct {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t* pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t* pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+typedef struct {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t* pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t* pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+} arm_fir_interpolate_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_interpolate_q15(
+    const arm_fir_interpolate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
+ * @param[in]     L          upsample factor.
+ * @param[in]     numTaps    number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficient buffer.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+arm_status arm_fir_interpolate_init_q15(
+    arm_fir_interpolate_instance_q15* S,
+    uint8_t L,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_interpolate_q31(
+    const arm_fir_interpolate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
+ * @param[in]     L          upsample factor.
+ * @param[in]     numTaps    number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficient buffer.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+arm_status arm_fir_interpolate_init_q31(
+    arm_fir_interpolate_instance_q31* S,
+    uint8_t L,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_interpolate_f32(
+    const arm_fir_interpolate_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
+ * @param[in]     L          upsample factor.
+ * @param[in]     numTaps    number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficient buffer.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+arm_status arm_fir_interpolate_init_f32(
+    arm_fir_interpolate_instance_f32* S,
+    uint8_t L,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+typedef struct {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t* pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t* pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+} arm_biquad_cas_df1_32x64_ins_q31;
+
+
+/**
+ * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cas_df1_32x64_q31(
+    const arm_biquad_cas_df1_32x64_ins_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cas_df1_32x64_init_q31(
+    arm_biquad_cas_df1_32x64_ins_q31* S,
+    uint8_t numStages,
+    q31_t* pCoeffs,
+    q63_t* pState,
+    uint8_t postShift);
+
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_cascade_stereo_df2T_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f64;
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in]  S          points to an instance of the filter data structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df2T_f32(
+    const arm_biquad_cascade_df2T_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in]  S          points to an instance of the filter data structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_stereo_df2T_f32(
+    const arm_biquad_cascade_stereo_df2T_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in]  S          points to an instance of the filter data structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df2T_f64(
+    const arm_biquad_cascade_df2T_instance_f64* S,
+    float64_t* pSrc,
+    float64_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the filter data structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ */
+void arm_biquad_cascade_df2T_init_f32(
+    arm_biquad_cascade_df2T_instance_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the filter data structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ */
+void arm_biquad_cascade_stereo_df2T_init_f32(
+    arm_biquad_cascade_stereo_df2T_instance_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the filter data structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ */
+void arm_biquad_cascade_df2T_init_f64(
+    arm_biquad_cascade_df2T_instance_f64* S,
+    uint8_t numStages,
+    float64_t* pCoeffs,
+    float64_t* pState);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q15_t* pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q15_t* pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q31_t* pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q31_t* pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t* pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t* pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_f32;
+
+
+/**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S          points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+void arm_fir_lattice_init_q15(
+    arm_fir_lattice_instance_q15* S,
+    uint16_t numStages,
+    q15_t* pCoeffs,
+    q15_t* pState);
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_lattice_q15(
+    const arm_fir_lattice_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S          points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.   The array is of length numStages.
+ */
+void arm_fir_lattice_init_q31(
+    arm_fir_lattice_instance_q31* S,
+    uint16_t numStages,
+    q31_t* pCoeffs,
+    q31_t* pState);
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_lattice_q31(
+    const arm_fir_lattice_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+void arm_fir_lattice_init_f32(
+    arm_fir_lattice_instance_f32* S,
+    uint16_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_lattice_f32(
+    const arm_fir_lattice_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q15_t* pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t* pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t* pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q31_t* pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t* pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t* pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    float32_t* pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t* pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t* pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_iir_lattice_f32(
+    const arm_iir_lattice_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
+ * @param[in] blockSize  number of samples to process.
+ */
+void arm_iir_lattice_init_f32(
+    arm_iir_lattice_instance_f32* S,
+    uint16_t numStages,
+    float32_t* pkCoeffs,
+    float32_t* pvCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_iir_lattice_q31(
+    const arm_iir_lattice_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S          points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process.
+ */
+void arm_iir_lattice_init_q31(
+    arm_iir_lattice_instance_q31* S,
+    uint16_t numStages,
+    q31_t* pkCoeffs,
+    q31_t* pvCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_iir_lattice_q15(
+    const arm_iir_lattice_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process per call.
+ */
+void arm_iir_lattice_init_q15(
+    arm_iir_lattice_instance_q15* S,
+    uint16_t numStages,
+    q15_t* pkCoeffs,
+    q15_t* pvCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t* pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+} arm_lms_instance_f32;
+
+
+/**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in]  S          points to an instance of the floating-point LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_f32(
+    const arm_lms_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pRef,
+    float32_t* pOut,
+    float32_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S          points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to the coefficient buffer.
+ * @param[in] pState     points to state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ */
+void arm_lms_init_f32(
+    arm_lms_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    float32_t mu,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+} arm_lms_instance_q15;
+
+
+/**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S          points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to the coefficient buffer.
+ * @param[in] pState     points to the state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ * @param[in] postShift  bit shift applied to coefficients.
+ */
+void arm_lms_init_q15(
+    arm_lms_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    q15_t mu,
+    uint32_t blockSize,
+    uint32_t postShift);
+
+
+/**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_q15(
+    const arm_lms_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pRef,
+    q15_t* pOut,
+    q15_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+} arm_lms_instance_q31;
+
+
+/**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_q31(
+    const arm_lms_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pRef,
+    q31_t* pOut,
+    q31_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S          points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to coefficient buffer.
+ * @param[in] pState     points to state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ * @param[in] postShift  bit shift applied to coefficients.
+ */
+void arm_lms_init_q31(
+    arm_lms_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    q31_t mu,
+    uint32_t blockSize,
+    uint32_t postShift);
+
+
+/**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;         /**< step size that control filter coefficient updates. */
+    float32_t energy;     /**< saves previous frame energy. */
+    float32_t x0;         /**< saves previous input sample. */
+} arm_lms_norm_instance_f32;
+
+
+/**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_norm_f32(
+    arm_lms_norm_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pRef,
+    float32_t* pOut,
+    float32_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S          points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to coefficient buffer.
+ * @param[in] pState     points to state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ */
+void arm_lms_norm_init_f32(
+    arm_lms_norm_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    float32_t mu,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t* recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+} arm_lms_norm_instance_q31;
+
+
+/**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_norm_q31(
+    arm_lms_norm_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pRef,
+    q31_t* pOut,
+    q31_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to coefficient buffer.
+ * @param[in] pState     points to state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ * @param[in] postShift  bit shift applied to coefficients.
+ */
+void arm_lms_norm_init_q31(
+    arm_lms_norm_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    q31_t mu,
+    uint32_t blockSize,
+    uint8_t postShift);
+
+
+/**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< Number of coefficients in the filter. */
+    q15_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q15_t* recipTable;    /**< Points to the reciprocal initial value table. */
+    q15_t energy;         /**< saves previous frame energy. */
+    q15_t x0;             /**< saves previous input sample. */
+} arm_lms_norm_instance_q15;
+
+
+/**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_norm_q15(
+    arm_lms_norm_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pRef,
+    q15_t* pOut,
+    q15_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to coefficient buffer.
+ * @param[in] pState     points to state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ * @param[in] postShift  bit shift applied to coefficients.
+ */
+void arm_lms_norm_init_q15(
+    arm_lms_norm_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    q15_t mu,
+    uint32_t blockSize,
+    uint8_t postShift);
+
+
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst);
+
+
+/**
+* @brief Correlation of Q15 sequences
+* @param[in]  pSrcA     points to the first input sequence.
+* @param[in]  srcALen   length of the first input sequence.
+* @param[in]  pSrcB     points to the second input sequence.
+* @param[in]  srcBLen   length of the second input sequence.
+* @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+* @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void arm_correlate_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch);
+
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+void arm_correlate_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+void arm_correlate_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in]  pSrcA     points to the first input sequence.
+ * @param[in]  srcALen   length of the first input sequence.
+ * @param[in]  pSrcB     points to the second input sequence.
+ * @param[in]  srcBLen   length of the second input sequence.
+ * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void arm_correlate_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch);
+
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+/**
+  * @brief Correlation of Q7 sequences.
+  * @param[in]  pSrcA      points to the first input sequence.
+  * @param[in]  srcALen    length of the first input sequence.
+  * @param[in]  pSrcB      points to the second input sequence.
+  * @param[in]  srcBLen    length of the second input sequence.
+  * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+  * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+  * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+  */
+void arm_correlate_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst);
+
+
+/**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t* pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_f32;
+
+/**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q31;
+
+/**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q15;
+
+/**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t* pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t* pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q7;
+
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
+ * @param[in]  pSrc        points to the block of input data.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize   number of input samples to process per call.
+ */
+void arm_fir_sparse_f32(
+    arm_fir_sparse_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    float32_t* pScratchIn,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     pCoeffs    points to the array of filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     pTapDelay  points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_f32(
+    arm_fir_sparse_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
+ * @param[in]  pSrc        points to the block of input data.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize   number of input samples to process per call.
+ */
+void arm_fir_sparse_q31(
+    arm_fir_sparse_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    q31_t* pScratchIn,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     pCoeffs    points to the array of filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     pTapDelay  points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q31(
+    arm_fir_sparse_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
+ * @param[in]  pSrc         points to the block of input data.
+ * @param[out] pDst         points to the block of output data
+ * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+ * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize    number of input samples to process per call.
+ */
+void arm_fir_sparse_q15(
+    arm_fir_sparse_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    q15_t* pScratchIn,
+    q31_t* pScratchOut,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     pCoeffs    points to the array of filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     pTapDelay  points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q15(
+    arm_fir_sparse_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
+ * @param[in]  pSrc         points to the block of input data.
+ * @param[out] pDst         points to the block of output data
+ * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+ * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize    number of input samples to process per call.
+ */
+void arm_fir_sparse_q7(
+    arm_fir_sparse_instance_q7* S,
+    q7_t* pSrc,
+    q7_t* pDst,
+    q7_t* pScratchIn,
+    q31_t* pScratchOut,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     pCoeffs    points to the array of filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     pTapDelay  points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q7(
+    arm_fir_sparse_instance_q7* S,
+    uint16_t numTaps,
+    q7_t* pCoeffs,
+    q7_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Floating-point sin_cos function.
+ * @param[in]  theta   input value in degrees
+ * @param[out] pSinVal  points to the processed sine output.
+ * @param[out] pCosVal  points to the processed cos output.
+ */
+void arm_sin_cos_f32(
+    float32_t theta,
+    float32_t* pSinVal,
+    float32_t* pCosVal);
+
+
+/**
+ * @brief  Q31 sin_cos function.
+ * @param[in]  theta    scaled input value in degrees
+ * @param[out] pSinVal  points to the processed sine output.
+ * @param[out] pCosVal  points to the processed cosine output.
+ */
+void arm_sin_cos_q31(
+    q31_t theta,
+    q31_t* pSinVal,
+    q31_t* pCosVal);
+
+
+/**
+ * @brief  Floating-point complex conjugate.
+ * @param[in]  pSrc        points to the input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_conj_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex conjugate.
+ * @param[in]  pSrc        points to the input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_conj_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q15 complex conjugate.
+ * @param[in]  pSrc        points to the input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_conj_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Floating-point complex magnitude squared
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q31 complex magnitude squared
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q15 complex magnitude squared
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+  * @ingroup groupController
+  */
+
+/**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd  </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief  Process function for the floating-point PID Control.
+ * @param[in,out] S   is an instance of the floating-point PID Control structure
+ * @param[in]     in  input sample to process
+ * @return out processed output sample.
+ */
+CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+    arm_pid_instance_f32* S,
+    float32_t in)
+{
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+          (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+}
+
+/**
+ * @brief  Process function for the Q31 PID Control.
+ * @param[in,out] S  points to an instance of the Q31 PID Control structure
+ * @param[in]     in  input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+    arm_pid_instance_q31* S,
+    q31_t in)
+{
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+}
+
+
+/**
+ * @brief  Process function for the Q15 PID Control.
+ * @param[in,out] S   points to an instance of the Q15 PID Control structure
+ * @param[in]     in  input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+    arm_pid_instance_q15* S,
+    q15_t in)
+{
+    q63_t acc;
+    q15_t out;
+
+#if defined (ARM_MATH_DSP)
+    __SIMD32_TYPE* vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc);
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+}
+
+/**
+ * @} end of PID group
+ */
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in]  src   points to the instance of the input floating-point matrix structure.
+ * @param[out] dst   points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+arm_status arm_mat_inverse_f32(
+    const arm_matrix_instance_f32* src,
+    arm_matrix_instance_f32* dst);
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in]  src   points to the instance of the input floating-point matrix structure.
+ * @param[out] dst   points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+arm_status arm_mat_inverse_f64(
+    const arm_matrix_instance_f64* src,
+    arm_matrix_instance_f64* dst);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup clarke
+ * @{
+ */
+
+/**
+ *
+ * @brief  Floating-point Clarke transform
+ * @param[in]  Ia       input three-phase coordinate <code>a</code>
+ * @param[in]  Ib       input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+    float32_t Ia,
+    float32_t Ib,
+    float32_t* pIalpha,
+    float32_t* pIbeta)
+{
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+}
+
+
+/**
+ * @brief  Clarke transform for Q31 version
+ * @param[in]  Ia       input three-phase coordinate <code>a</code>
+ * @param[in]  Ib       input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+    q31_t Ia,
+    q31_t Ib,
+    q31_t* pIalpha,
+    q31_t* pIbeta)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+}
+
+/**
+ * @} end of clarke group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_q7_to_q31(
+    q7_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+/**
+* @brief  Floating-point Inverse Clarke transform
+* @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+* @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+* @param[out] pIa     points to output three-phase coordinate <code>a</code>
+* @param[out] pIb     points to output three-phase coordinate <code>b</code>
+*/
+CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+    float32_t Ialpha,
+    float32_t Ibeta,
+    float32_t* pIa,
+    float32_t* pIb)
+{
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+}
+
+
+/**
+ * @brief  Inverse Clarke transform for Q31 version
+ * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+ * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+ * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+    q31_t Ialpha,
+    q31_t Ibeta,
+    q31_t* pIa,
+    q31_t* pIb)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+}
+
+/**
+ * @} end of inv_clarke group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_q7_to_q15(
+    q7_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup park
+ * @{
+ */
+
+/**
+ * @brief Floating-point Park transform
+ * @param[in]  Ialpha  input two-phase vector coordinate alpha
+ * @param[in]  Ibeta   input two-phase vector coordinate beta
+ * @param[out] pId     points to output   rotor reference frame d
+ * @param[out] pIq     points to output   rotor reference frame q
+ * @param[in]  sinVal  sine value of rotation angle theta
+ * @param[in]  cosVal  cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+    float32_t Ialpha,
+    float32_t Ibeta,
+    float32_t* pId,
+    float32_t* pIq,
+    float32_t sinVal,
+    float32_t cosVal)
+{
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+}
+
+
+/**
+ * @brief  Park transform for Q31 version
+ * @param[in]  Ialpha  input two-phase vector coordinate alpha
+ * @param[in]  Ibeta   input two-phase vector coordinate beta
+ * @param[out] pId     points to output rotor reference frame d
+ * @param[out] pIq     points to output rotor reference frame q
+ * @param[in]  sinVal  sine value of rotation angle theta
+ * @param[in]  cosVal  cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+    q31_t Ialpha,
+    q31_t Ibeta,
+    q31_t* pId,
+    q31_t* pIq,
+    q31_t sinVal,
+    q31_t cosVal)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+}
+
+/**
+ * @} end of park group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q7_to_float(
+    q7_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_park
+ * @{
+ */
+
+/**
+* @brief  Floating-point Inverse Park transform
+* @param[in]  Id       input coordinate of rotor reference frame d
+* @param[in]  Iq       input coordinate of rotor reference frame q
+* @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+* @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+* @param[in]  sinVal   sine value of rotation angle theta
+* @param[in]  cosVal   cosine value of rotation angle theta
+*/
+CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+    float32_t Id,
+    float32_t Iq,
+    float32_t* pIalpha,
+    float32_t* pIbeta,
+    float32_t sinVal,
+    float32_t cosVal)
+{
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+}
+
+
+/**
+ * @brief  Inverse Park transform for   Q31 version
+ * @param[in]  Id       input coordinate of rotor reference frame d
+ * @param[in]  Iq       input coordinate of rotor reference frame q
+ * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+ * @param[in]  sinVal   sine value of rotation angle theta
+ * @param[in]  cosVal   cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+    q31_t Id,
+    q31_t Iq,
+    q31_t* pIalpha,
+    q31_t* pIbeta,
+    q31_t sinVal,
+    q31_t cosVal)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+}
+
+/**
+ * @} end of Inverse park group
+ */
+
+
+/**
+ * @brief  Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q31_to_float(
+    q31_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A  Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+/**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+/**
+ * @brief  Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
+ * @param[in]     x  input sample to process
+ * @return y processed output sample.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+    arm_linear_interp_instance_f32* S,
+    float32_t x)
+{
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t* pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if (i < 0) {
+        /* Iniatilize output for below specified range as least output value of table */
+        y = pYData[0];
+    }
+    else if ((uint32_t)i >= S->nValues) {
+        /* Iniatilize output for above specified range as last output value of table */
+        y = pYData[S->nValues - 1];
+    }
+    else {
+        /* Calculation of nearest input values */
+        x0 = S->x1 +  i      * xSpacing;
+        x1 = S->x1 + (i + 1) * xSpacing;
+
+        /* Read of nearest output values */
+        y0 = pYData[i];
+        y1 = pYData[i + 1];
+
+        /* Calculation of output */
+        y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+}
+
+
+/**
+*
+* @brief  Process function for the Q31 Linear Interpolation Function.
+* @param[in] pYData   pointer to Q31 Linear Interpolation table
+* @param[in] x        input sample to process
+* @param[in] nValues  number of table values
+* @return y processed output sample.
+*
+* \par
+* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+* This function can support maximum of table size 2^12.
+*
+*/
+CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+    q31_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (q31_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else if (index < 0) {
+        return (pYData[0]);
+    }
+    else {
+        /* 20 bits for the fractional part */
+        /* shift left by 11 to keep fract in 1.31 format */
+        fract = (x & 0x000FFFFF) << 11;
+
+        /* Read two nearest output values from the index in 1.31(q31) format */
+        y0 = pYData[index];
+        y1 = pYData[index + 1];
+
+        /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+        y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+        /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+        y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+        /* Convert y to 1.31 format */
+        return (y << 1u);
+    }
+}
+
+
+/**
+ *
+ * @brief  Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData   pointer to Q15 Linear Interpolation table
+ * @param[in] x        input sample to process
+ * @param[in] nValues  number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+    q15_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (int32_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else if (index < 0) {
+        return (pYData[0]);
+    }
+    else {
+        /* 20 bits for the fractional part */
+        /* fract is in 12.20 format */
+        fract = (x & 0x000FFFFF);
+
+        /* Read two nearest output values from the index */
+        y0 = pYData[index];
+        y1 = pYData[index + 1];
+
+        /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+        y = ((q63_t) y0 * (0xFFFFF - fract));
+
+        /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+        y += ((q63_t) y1 * (fract));
+
+        /* convert y to 1.15 format */
+        return (q15_t) (y >> 20);
+    }
+}
+
+
+/**
+ *
+ * @brief  Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData   pointer to Q7 Linear Interpolation table
+ * @param[in] x        input sample to process
+ * @param[in] nValues  number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+    q7_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0) {
+        return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+    if (index >= (nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else {
+        /* 20 bits for the fractional part */
+        /* fract is in 12.20 format */
+        fract = (x & 0x000FFFFF);
+
+        /* Read two nearest output values from the index and are in 1.7(q7) format */
+        y0 = pYData[index];
+        y1 = pYData[index + 1];
+
+        /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+        y = ((y0 * (0xFFFFF - fract)));
+
+        /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+        y += (y1 * fract);
+
+        /* convert y to 1.7(q7) format */
+        return (q7_t) (y >> 20);
+    }
+}
+
+/**
+ * @} end of LinearInterpolate group
+ */
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x  input value in radians.
+ * @return  sin(x).
+ */
+float32_t arm_sin_f32(
+    float32_t x);
+
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x  Scaled input value in radians.
+ * @return  sin(x).
+ */
+q31_t arm_sin_q31(
+    q31_t x);
+
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x  Scaled input value in radians.
+ * @return  sin(x).
+ */
+q15_t arm_sin_q15(
+    q15_t x);
+
+
+/**
+ * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x  input value in radians.
+ * @return  cos(x).
+ */
+float32_t arm_cos_f32(
+    float32_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x  Scaled input value in radians.
+ * @return  cos(x).
+ */
+q31_t arm_cos_q31(
+    q31_t x);
+
+
+/**
+ * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x  Scaled input value in radians.
+ * @return  cos(x).
+ */
+q15_t arm_cos_q15(
+    q15_t x);
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+
+/**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ *      x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ *     x0 = in/2                         [initial guess]
+ *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ * </pre>
+ */
+
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief  Floating-point square root function.
+ * @param[in]  in    input value.
+ * @param[out] pOut  square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+    float32_t in,
+    float32_t* pOut)
+{
+    if (in >= 0.0f) {
+
+#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
+        *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+        *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+        *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+        __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+        *pOut = sqrtf(in);
+#endif
+
+        return (ARM_MATH_SUCCESS);
+    }
+    else {
+        *pOut = 0.0f;
+        return (ARM_MATH_ARGUMENT_ERROR);
+    }
+}
+
+
+/**
+ * @brief Q31 square root function.
+ * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut  square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q31(
+    q31_t in,
+    q31_t* pOut);
+
+
+/**
+ * @brief  Q15 square root function.
+ * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut  square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q15(
+    q15_t in,
+    q15_t* pOut);
+
+/**
+ * @} end of SQRT group
+ */
+
+
+/**
+ * @brief floating-point Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+    int32_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const int32_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if (wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+}
+
+
+
+/**
+ * @brief floating-point Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+    int32_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    int32_t* dst,
+    int32_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if (dst == (int32_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update rOffset.  Watch out for positive and negative value  */
+        rOffset += bufferInc;
+
+        if (rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q15 Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+    q15_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const q15_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if (wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+}
+
+
+/**
+ * @brief Q15 Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+    q15_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    q15_t* dst,
+    q15_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if (dst == (q15_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        rOffset += bufferInc;
+
+        if (rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q7 Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+    q7_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const q7_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if (wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+}
+
+
+/**
+ * @brief Q7 Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+    q7_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    q7_t* dst,
+    q7_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if (dst == (q7_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update rOffset.  Watch out for positive and negative value */
+        rOffset += bufferInc;
+
+        if (rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+
+/**
+ * @brief  Sum of the squares of the elements of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_power_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q63_t* pResult);
+
+
+/**
+ * @brief  Sum of the squares of the elements of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_power_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+
+/**
+ * @brief  Sum of the squares of the elements of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_power_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q63_t* pResult);
+
+
+/**
+ * @brief  Sum of the squares of the elements of a Q7 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_power_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+
+/**
+ * @brief  Mean value of a Q7 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_mean_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* pResult);
+
+
+/**
+ * @brief  Mean value of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_mean_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+
+/**
+ * @brief  Mean value of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_mean_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+
+/**
+ * @brief  Mean value of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_mean_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+
+/**
+ * @brief  Variance of the elements of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_var_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+
+/**
+ * @brief  Variance of the elements of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_var_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+
+/**
+ * @brief  Variance of the elements of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_var_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+
+/**
+ * @brief  Root Mean Square of the elements of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_rms_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+
+/**
+ * @brief  Root Mean Square of the elements of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_rms_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+
+/**
+ * @brief  Root Mean Square of the elements of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_rms_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+
+/**
+ * @brief  Standard deviation of the elements of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_std_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+
+/**
+ * @brief  Standard deviation of the elements of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_std_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+
+/**
+ * @brief  Standard deviation of the elements of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_std_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+
+/**
+ * @brief  Floating-point complex magnitude
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q31 complex magnitude
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q15 complex magnitude
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q15 complex dot product
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ * @param[out] realResult  real part of the result returned here
+ * @param[out] imagResult  imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    uint32_t numSamples,
+    q31_t* realResult,
+    q31_t* imagResult);
+
+
+/**
+ * @brief  Q31 complex dot product
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ * @param[out] realResult  real part of the result returned here
+ * @param[out] imagResult  imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    uint32_t numSamples,
+    q63_t* realResult,
+    q63_t* imagResult);
+
+
+/**
+ * @brief  Floating-point complex dot product
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ * @param[out] realResult  real part of the result returned here
+ * @param[out] imagResult  imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    uint32_t numSamples,
+    float32_t* realResult,
+    float32_t* imagResult);
+
+
+/**
+ * @brief  Q15 complex-by-real multiplication
+ * @param[in]  pSrcCmplx   points to the complex input vector
+ * @param[in]  pSrcReal    points to the real input vector
+ * @param[out] pCmplxDst   points to the complex output vector
+ * @param[in]  numSamples  number of samples in each vector
+ */
+void arm_cmplx_mult_real_q15(
+    q15_t* pSrcCmplx,
+    q15_t* pSrcReal,
+    q15_t* pCmplxDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q31 complex-by-real multiplication
+ * @param[in]  pSrcCmplx   points to the complex input vector
+ * @param[in]  pSrcReal    points to the real input vector
+ * @param[out] pCmplxDst   points to the complex output vector
+ * @param[in]  numSamples  number of samples in each vector
+ */
+void arm_cmplx_mult_real_q31(
+    q31_t* pSrcCmplx,
+    q31_t* pSrcReal,
+    q31_t* pCmplxDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Floating-point complex-by-real multiplication
+ * @param[in]  pSrcCmplx   points to the complex input vector
+ * @param[in]  pSrcReal    points to the real input vector
+ * @param[out] pCmplxDst   points to the complex output vector
+ * @param[in]  numSamples  number of samples in each vector
+ */
+void arm_cmplx_mult_real_f32(
+    float32_t* pSrcCmplx,
+    float32_t* pSrcReal,
+    float32_t* pCmplxDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Minimum value of a Q7 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] result     is output pointer
+ * @param[in]  index      is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* result,
+    uint32_t* index);
+
+
+/**
+ * @brief  Minimum value of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output pointer
+ * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief  Minimum value of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output pointer
+ * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief  Minimum value of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output pointer
+ * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+ */
+void arm_min_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+void arm_max_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+void arm_max_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+void arm_max_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+void arm_max_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief  Q15 complex-by-complex multiplication
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q31 complex-by-complex multiplication
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Floating-point complex-by-complex multiplication
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in]  pSrc       points to the floating-point input vector
+ * @param[out] pDst       points to the Q31 output vector
+ * @param[in]  blockSize  length of the input vector
+ */
+void arm_float_to_q31(
+    float32_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in]  pSrc       points to the floating-point input vector
+ * @param[out] pDst       points to the Q15 output vector
+ * @param[in]  blockSize  length of the input vector
+ */
+void arm_float_to_q15(
+    float32_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in]  pSrc       points to the floating-point input vector
+ * @param[out] pDst       points to the Q7 output vector
+ * @param[in]  blockSize  length of the input vector
+ */
+void arm_float_to_q7(
+    float32_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q31_to_q15(
+    q31_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q31_to_q7(
+    q31_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q15_to_float(
+    q15_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q15_to_q31(
+    q15_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q15_to_q7(
+    q15_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+ * <pre>
+ *     XF = floor(x)
+ *     YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+/**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+/**
+*
+* @brief  Floating-point bilinear interpolation.
+* @param[in,out] S  points to an instance of the interpolation structure.
+* @param[in]     X  interpolation coordinate.
+* @param[in]     Y  interpolation coordinate.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+    const arm_bilinear_interp_instance_f32* S,
+    float32_t X,
+    float32_t Y)
+{
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t* pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+}
+
+
+/**
+*
+* @brief  Q31 bilinear interpolation.
+* @param[in,out] S  points to an instance of the interpolation structure.
+* @param[in]     X  interpolation coordinate in 12.20 format.
+* @param[in]     Y  interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+    arm_bilinear_interp_instance_q31* S,
+    q31_t X,
+    q31_t Y)
+{
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t* pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
+    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
+    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return ((q31_t)(acc << 2));
+}
+
+
+/**
+* @brief  Q15 bilinear interpolation.
+* @param[in,out] S  points to an instance of the interpolation structure.
+* @param[in]     X  interpolation coordinate in 12.20 format.
+* @param[in]     Y  interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+    arm_bilinear_interp_instance_q15* S,
+    q31_t X,
+    q31_t Y)
+{
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t* pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return ((q15_t)(acc >> 36));
+}
+
+
+/**
+* @brief  Q7 bilinear interpolation.
+* @param[in,out] S  points to an instance of the interpolation structure.
+* @param[in]     X  interpolation coordinate in 12.20 format.
+* @param[in]     Y  interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+    arm_bilinear_interp_instance_q7* S,
+    q31_t X,
+    q31_t Y)
+{
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t* pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return ((q7_t)(acc >> 40));
+}
+
+/**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if   defined ( __CC_ARM )
+/* Enter low optimization region - place directly above function definition */
+#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+#define LOW_OPTIMIZATION_ENTER \
+    _Pragma ("push")         \
+    _Pragma ("O1")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define LOW_OPTIMIZATION_EXIT \
+    _Pragma ("pop")
+#else
+#define LOW_OPTIMIZATION_EXIT
+#endif
+
+/* Enter low optimization region - place directly above function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+/* Exit low optimization region - place directly after end of function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+#define LOW_OPTIMIZATION_ENTER \
+    __attribute__(( optimize("-O1") ))
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+/* Enter low optimization region - place directly above function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define LOW_OPTIMIZATION_ENTER \
+    _Pragma ("optimize=low")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#define LOW_OPTIMIZATION_EXIT
+
+/* Enter low optimization region - place directly above function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+    _Pragma ("optimize=low")
+#else
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef   __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h
new file mode 100644
index 000000000..4617b1280
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h
@@ -0,0 +1,796 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
+ * @version  V5.0.1
+ * @date     03. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+#define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+#define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+#define __ARM_ARCH_7EM__          1
+#endif
+
+/* __ARM_ARCH_8M_BASE__  not applicable */
+/* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  __inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static __inline
+#endif
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __declspec(noreturn)
+#endif
+#ifndef   __USED
+#define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+#define __UNALIGNED_UINT32(x)     (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __ALIGNED
+#define __ALIGNED(x)              __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           __packed struct
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    register uint32_t __regControl         __ASM("control");
+    return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    register uint32_t __regControl         __ASM("control");
+    __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    register uint32_t __regIPSR          __ASM("ipsr");
+    return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+    register uint32_t __regAPSR          __ASM("apsr");
+    return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    register uint32_t __regXPSR          __ASM("xpsr");
+    return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    register uint32_t __regPriMask         __ASM("primask");
+    return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    register uint32_t __regPriMask         __ASM("primask");
+    __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+    register uint32_t __regBasePri         __ASM("basepri");
+    return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+    register uint32_t __regBasePri         __ASM("basepri");
+    __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+    register uint32_t __regBasePriMax      __ASM("basepri_max");
+    __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    register uint32_t __regfpscr         __ASM("fpscr");
+    return(__regfpscr);
+#else
+    return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    register uint32_t __regfpscr         __ASM("fpscr");
+    __regfpscr = (fpscr);
+#else
+    (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+        __schedule_barrier();\
+        __isb(0xF);\
+        __schedule_barrier();\
+    } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+        __schedule_barrier();\
+        __dsb(0xF);\
+        __schedule_barrier();\
+    } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+        __schedule_barrier();\
+        __dmb(0xF);\
+        __schedule_barrier();\
+    } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+    rev16 r0, r0
+    bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+    revsh r0, r0
+    bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+#define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+    result = value;                      /* r will be reversed bits of v; first get LSB of v */
+    for (value >>= 1U; value; value >>= 1U) {
+        result <<= 1U;
+        result |= value & 1U;
+        s--;
+    }
+    result <<= s;                        /* shift when v's highest bits are zero */
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+#define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+#define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+#define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+#define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+#define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+#define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+    rrx r0, r0
+    bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h
new file mode 100644
index 000000000..6b21a5bea
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h
@@ -0,0 +1,1735 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version  V5.0.1
+ * @date     02. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  __inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static __inline
+#endif
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __attribute__((noreturn))
+#endif
+#ifndef   __USED
+#define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wpacked"
+struct __attribute__((packed)) T_UINT32 {
+    uint32_t v;
+};
+#pragma clang diagnostic pop
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#define __ALIGNED(x)              __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           struct __attribute__((packed, aligned(1)))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, control" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+    __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+    __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msp" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+    __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, primask" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+    __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+    __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+    return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+    __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+    __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+    return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+    __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+    __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+/* #define __get_FPSCR      __builtin_arm_get_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    uint32_t result;
+
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    return(result);
+#else
+    return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+/* #define __set_FPSCR      __builtin_arm_set_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+    (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV          __builtin_bswap32
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16          __builtin_bswap16                /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+    int32_t result;
+
+    __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+    return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+    result = value;                      /* r will be reversed bits of v; first get LSB of v */
+    for (value >>= 1U; value; value >>= 1U) {
+        result <<= 1U;
+        result |= value & 1U;
+        s--;
+    }
+    result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+    return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
+{
+    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
+{
+    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
+{
+    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
+{
+    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
+{
+    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
+{
+    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+    ({                          \
+        int32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+#define __USAT16(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+    int32_t result;
+
+    __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+    int32_t result;
+
+    __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        if (ARG3 == 0) \
+            __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+        else \
+            __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+    int32_t result;
+
+    __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h
new file mode 100644
index 000000000..89cd69027
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h
@@ -0,0 +1,231 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.1
+ * @date     30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+#include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+#include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static inline
+#endif
+
+#include <cmsis_iar.h>
+
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __noreturn
+#endif
+#ifndef   __USED
+#define __USED                    __root
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __weak
+#endif
+#ifndef   __UNALIGNED_UINT32
+__packed struct T_UINT32 {
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __packed
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           __packed struct
+#endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+#include <cmsis_ccs.h>
+
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static inline
+#endif
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __attribute__((noreturn))
+#endif
+#ifndef   __USED
+#define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+struct __attribute__((packed)) T_UINT32 {
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#define __ALIGNED(x)              __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           struct __attribute__((packed))
+#endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static inline
+#endif
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __attribute__((noreturn))
+#endif
+#ifndef   __USED
+#define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+struct __packed__ T_UINT32 {
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#define __ALIGNED(x)              __align(x)
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __packed__
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           struct __packed__
+#endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+#include <cmsis_csm.h>
+
+#ifndef   __ASM
+#define __ASM                     _asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static inline
+#endif
+#ifndef   __NO_RETURN
+// NO RETURN is automatically detected hence no warning here
+#define __NO_RETURN
+#endif
+#ifndef   __USED
+#warning No compiler specific solution for __USED. __USED is ignored.
+#define __USED
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __weak
+#endif
+#ifndef   __UNALIGNED_UINT32
+@packed struct T_UINT32 {
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#ifndef   __PACKED
+#define __PACKED                  @packed
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           @packed struct
+#endif
+
+
+#else
+#error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h
new file mode 100644
index 000000000..919f26d15
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h
@@ -0,0 +1,1900 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.1
+ * @date     02. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static inline
+#endif
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __attribute__((noreturn))
+#endif
+#ifndef   __USED
+#define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+struct __attribute__((packed)) T_UINT32 {
+    uint32_t v;
+};
+#pragma GCC diagnostic pop
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#define __ALIGNED(x)              __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           struct __attribute__((packed, aligned(1)))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+    __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+    __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, control" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+    __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+    __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msp" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+    __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, primask" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+    __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+    __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+    __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+    __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+    return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+    __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+    __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+    return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+    __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+    __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    uint32_t result;
+
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    return(result);
+#else
+    return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#else
+    (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+//{
+//  __ASM volatile ("nop");
+//}
+#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+//{
+//  __ASM volatile ("wfi");
+//}
+#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+//{
+//  __ASM volatile ("wfe");
+//}
+#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+//{
+//  __ASM volatile ("sev");
+//}
+#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+    __ASM volatile ("isb 0xF"::: "memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+    __ASM volatile ("dsb 0xF"::: "memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+    __ASM volatile ("dmb 0xF"::: "memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+    return __builtin_bswap32(value);
+#else
+    uint32_t result;
+
+    __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    return (short)__builtin_bswap16(value);
+#else
+    int32_t result;
+
+    __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+    return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+    result = value;                      /* r will be reversed bits of v; first get LSB of v */
+    for (value >>= 1U; value; value >>= 1U) {
+        result <<= 1U;
+        result |= value & 1U;
+        s--;
+    }
+    result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+    return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+    return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+    return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+    __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+    ({                          \
+        int32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
+{
+    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
+{
+    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
+{
+    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
+{
+    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
+{
+    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
+{
+    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+    ({                          \
+        int32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+#define __USAT16(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+    int32_t result;
+
+    __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+    int32_t result;
+
+    __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        if (ARG3 == 0) \
+            __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+        else \
+            __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+    int32_t result;
+
+    __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h
new file mode 100644
index 000000000..4e65d1d95
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h
@@ -0,0 +1,1813 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS ARMv8MBL Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+/*  CMSIS cmGrebe definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                        __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __ARMv8MBL_REV
+#define __ARMv8MBL_REV               0x0000U
+#warning "__ARMv8MBL_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT       0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT            0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+
+#ifndef __ETM_PRESENT
+#define __ETM_PRESENT             0U
+#warning "__ETM_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MTB_PRESENT
+#define __MTB_PRESENT             0U
+#warning "__MTB_PRESENT not defined in device header file; using default!"
+#endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[16U];
+    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[16U];
+    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[16U];
+    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[16U];
+    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[16U];
+    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+    uint32_t RESERVED5[16U];
+    __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+    uint32_t RESERVED0;
+#endif
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED1;
+    __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    uint32_t RESERVED0[6U];
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    uint32_t RESERVED3[1U];
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    uint32_t RESERVED5[1U];
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED6[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    uint32_t RESERVED7[1U];
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+    uint32_t RESERVED9[1U];
+    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+    uint32_t RESERVED10[1U];
+    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+    uint32_t RESERVED11[1U];
+    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+    uint32_t RESERVED12[1U];
+    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+    uint32_t RESERVED13[1U];
+    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+    uint32_t RESERVED14[1U];
+    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+    uint32_t RESERVED15[1U];
+    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+    uint32_t RESERVED16[1U];
+    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+    uint32_t RESERVED17[1U];
+    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+    uint32_t RESERVED18[1U];
+    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+    uint32_t RESERVED19[1U];
+    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+    uint32_t RESERVED20[1U];
+    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+    uint32_t RESERVED21[1U];
+    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+    uint32_t RESERVED22[1U];
+    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+    uint32_t RESERVED23[1U];
+    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+    uint32_t RESERVED24[1U];
+    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+    uint32_t RESERVED25[1U];
+    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+    uint32_t RESERVED26[1U];
+    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+    uint32_t RESERVED27[1U];
+    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+    uint32_t RESERVED28[1U];
+    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+    uint32_t RESERVED29[1U];
+    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+    uint32_t RESERVED30[1U];
+    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+    uint32_t RESERVED31[1U];
+    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+    uint32_t RESERVED0[7U];
+    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+#endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for ARMv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for ARMv8-M Baseline */
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                         /* Reload value impossible */
+    }
+
+    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                        SysTick_CTRL_TICKINT_Msk   |
+                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h
new file mode 100644
index 000000000..273c3849c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h
@@ -0,0 +1,2821 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS ARMv8MML Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     07. December 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+/*  CMSIS ARMv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                        __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __ARMv8MML_REV
+#define __ARMv8MML_REV               0x0000U
+#warning "__ARMv8MML_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT       0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DSP_PRESENT
+#define __DSP_PRESENT             0U
+#warning "__DSP_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0) */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
+        uint32_t FPCA: 1;                    /*!< bit:      2  Floating-point context active */
+        uint32_t SFPA: 1;                    /*!< bit:      3  Secure floating-point active */
+        uint32_t _reserved1: 28;             /*!< bit:  4..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[16U];
+    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[16U];
+    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[16U];
+    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[16U];
+    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[16U];
+    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+    uint32_t RESERVED5[16U];
+    __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED6[580U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+    __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+    uint32_t RESERVED3[92U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+    uint32_t RESERVED4[15U];
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+    uint32_t RESERVED5[1U];
+    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+    uint32_t RESERVED6[1U];
+    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+    uint32_t RESERVED7[6U];
+    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+    __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[1U];
+    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+    uint32_t RESERVED6[4U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    uint32_t RESERVED3[1U];
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    uint32_t RESERVED5[1U];
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED6[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    uint32_t RESERVED7[1U];
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+    uint32_t RESERVED9[1U];
+    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+    uint32_t RESERVED10[1U];
+    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+    uint32_t RESERVED11[1U];
+    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+    uint32_t RESERVED12[1U];
+    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+    uint32_t RESERVED13[1U];
+    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+    uint32_t RESERVED14[1U];
+    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+    uint32_t RESERVED15[1U];
+    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+    uint32_t RESERVED16[1U];
+    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+    uint32_t RESERVED17[1U];
+    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+    uint32_t RESERVED18[1U];
+    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+    uint32_t RESERVED19[1U];
+    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+    uint32_t RESERVED20[1U];
+    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+    uint32_t RESERVED21[1U];
+    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+    uint32_t RESERVED22[1U];
+    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+    uint32_t RESERVED23[1U];
+    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+    uint32_t RESERVED24[1U];
+    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+    uint32_t RESERVED25[1U];
+    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+    uint32_t RESERVED26[1U];
+    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+    uint32_t RESERVED27[1U];
+    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+    uint32_t RESERVED28[1U];
+    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+    uint32_t RESERVED29[1U];
+    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+    uint32_t RESERVED30[1U];
+    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+    uint32_t RESERVED31[1U];
+    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+    uint32_t RESERVED32[934U];
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+    uint32_t RESERVED33[1U];
+    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+    __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+    __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+    __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+    uint32_t RESERVED0[1];
+    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+    uint32_t RESERVED0[3];
+#endif
+    __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+    __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+#endif
+
+#define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+#define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+    return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    uint32_t mvfr0;
+
+    mvfr0 = FPU->MVFR0;
+    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+        return 2U;           /* Double + Single precision FPU */
+    }
+    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+        return 1U;           /* Single precision FPU */
+    }
+    else {
+        return 0U;           /* No FPU */
+    }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                         /* Reload value impossible */
+    }
+
+    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                        SysTick_CTRL_TICKINT_Msk   |
+                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h
new file mode 100644
index 000000000..d06d984b7
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h
@@ -0,0 +1,850 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM0_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0_REV
+#define __CM0_REV               0x0000U
+#warning "__CM0_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 1;              /*!< bit:      0  Reserved */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[31U];
+    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[31U];
+    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[31U];
+    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[31U];
+    uint32_t RESERVED4[64U];
+    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    uint32_t RESERVED0;
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED1;
+    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)0x0U;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)0x0U;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h
new file mode 100644
index 000000000..ebc43f3a1
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h
@@ -0,0 +1,975 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                      __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0PLUS_REV
+#define __CM0PLUS_REV             0x0000U
+#warning "__CM0PLUS_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT            0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[31U];
+    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[31U];
+    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[31U];
+    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[31U];
+    uint32_t RESERVED4[64U];
+    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+    uint32_t RESERVED0;
+#endif
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED1;
+    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0+ */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0+ */
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h
new file mode 100644
index 000000000..513635a58
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h
@@ -0,0 +1,1813 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+/*  CMSIS cmGrebe definitions */
+#define __CM23_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM23_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                     (23U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM23_REV
+#define __CM23_REV                0x0000U
+#warning "__CM23_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT       0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT            0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+
+#ifndef __ETM_PRESENT
+#define __ETM_PRESENT             0U
+#warning "__ETM_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MTB_PRESENT
+#define __MTB_PRESENT             0U
+#warning "__MTB_PRESENT not defined in device header file; using default!"
+#endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[16U];
+    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[16U];
+    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[16U];
+    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[16U];
+    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[16U];
+    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+    uint32_t RESERVED5[16U];
+    __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+    uint32_t RESERVED0;
+#endif
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED1;
+    __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    uint32_t RESERVED0[6U];
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    uint32_t RESERVED3[1U];
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    uint32_t RESERVED5[1U];
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED6[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    uint32_t RESERVED7[1U];
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+    uint32_t RESERVED9[1U];
+    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+    uint32_t RESERVED10[1U];
+    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+    uint32_t RESERVED11[1U];
+    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+    uint32_t RESERVED12[1U];
+    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+    uint32_t RESERVED13[1U];
+    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+    uint32_t RESERVED14[1U];
+    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+    uint32_t RESERVED15[1U];
+    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+    uint32_t RESERVED16[1U];
+    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+    uint32_t RESERVED17[1U];
+    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+    uint32_t RESERVED18[1U];
+    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+    uint32_t RESERVED19[1U];
+    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+    uint32_t RESERVED20[1U];
+    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+    uint32_t RESERVED21[1U];
+    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+    uint32_t RESERVED22[1U];
+    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+    uint32_t RESERVED23[1U];
+    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+    uint32_t RESERVED24[1U];
+    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+    uint32_t RESERVED25[1U];
+    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+    uint32_t RESERVED26[1U];
+    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+    uint32_t RESERVED27[1U];
+    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+    uint32_t RESERVED28[1U];
+    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+    uint32_t RESERVED29[1U];
+    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+    uint32_t RESERVED30[1U];
+    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+    uint32_t RESERVED31[1U];
+    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+    uint32_t RESERVED0[7U];
+    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+#endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                         /* Reload value impossible */
+    }
+
+    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                        SysTick_CTRL_TICKINT_Msk   |
+                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h
new file mode 100644
index 000000000..8cbf329b8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h
@@ -0,0 +1,1880 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM3_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM3_REV
+#define __CM3_REV               0x0200U
+#warning "__CM3_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
+        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
+        uint32_t _reserved1: 8;              /*!< bit: 16..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
+        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24U];
+    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24U];
+    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24U];
+    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24U];
+    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56U];
+    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    uint32_t RESERVED0[5U];
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+    uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[6U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h
new file mode 100644
index 000000000..00de7795e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h
@@ -0,0 +1,2821 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     07. December 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM33_CMSIS_VERSION_SUB           )     /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM33_REV
+#define __CM33_REV                0x0000U
+#warning "__CM33_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT       0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DSP_PRESENT
+#define __DSP_PRESENT             0U
+#warning "__DSP_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0) */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
+        uint32_t FPCA: 1;                    /*!< bit:      2  Floating-point context active */
+        uint32_t SFPA: 1;                    /*!< bit:      3  Secure floating-point active */
+        uint32_t _reserved1: 28;             /*!< bit:  4..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[16U];
+    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[16U];
+    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[16U];
+    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[16U];
+    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[16U];
+    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+    uint32_t RESERVED5[16U];
+    __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED6[580U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+    __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+    uint32_t RESERVED3[92U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+    uint32_t RESERVED4[15U];
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+    uint32_t RESERVED5[1U];
+    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+    uint32_t RESERVED6[1U];
+    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+    uint32_t RESERVED7[6U];
+    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+    __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[1U];
+    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+    uint32_t RESERVED6[4U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    uint32_t RESERVED3[1U];
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    uint32_t RESERVED5[1U];
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED6[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    uint32_t RESERVED7[1U];
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+    uint32_t RESERVED9[1U];
+    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+    uint32_t RESERVED10[1U];
+    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+    uint32_t RESERVED11[1U];
+    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+    uint32_t RESERVED12[1U];
+    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+    uint32_t RESERVED13[1U];
+    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+    uint32_t RESERVED14[1U];
+    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+    uint32_t RESERVED15[1U];
+    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+    uint32_t RESERVED16[1U];
+    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+    uint32_t RESERVED17[1U];
+    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+    uint32_t RESERVED18[1U];
+    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+    uint32_t RESERVED19[1U];
+    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+    uint32_t RESERVED20[1U];
+    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+    uint32_t RESERVED21[1U];
+    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+    uint32_t RESERVED22[1U];
+    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+    uint32_t RESERVED23[1U];
+    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+    uint32_t RESERVED24[1U];
+    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+    uint32_t RESERVED25[1U];
+    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+    uint32_t RESERVED26[1U];
+    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+    uint32_t RESERVED27[1U];
+    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+    uint32_t RESERVED28[1U];
+    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+    uint32_t RESERVED29[1U];
+    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+    uint32_t RESERVED30[1U];
+    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+    uint32_t RESERVED31[1U];
+    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+    uint32_t RESERVED32[934U];
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+    uint32_t RESERVED33[1U];
+    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+    __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+    __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+    __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+    uint32_t RESERVED0[1];
+    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+    uint32_t RESERVED0[3];
+#endif
+    __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+    __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+#endif
+
+#define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+#define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+    return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    uint32_t mvfr0;
+
+    mvfr0 = FPU->MVFR0;
+    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+        return 2U;           /* Double + Single precision FPU */
+    }
+    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+        return 1U;           /* Single precision FPU */
+    }
+    else {
+        return 0U;           /* No FPU */
+    }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                         /* Reload value impossible */
+    }
+
+    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                        SysTick_CTRL_TICKINT_Msk   |
+                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h
new file mode 100644
index 000000000..f4c8011f8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h
@@ -0,0 +1,2061 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM4_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM4_REV
+#define __CM4_REV               0x0000U
+#warning "__CM4_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
+        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
+        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24U];
+    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24U];
+    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24U];
+    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24U];
+    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56U];
+    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    uint32_t RESERVED0[5U];
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[6U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    uint32_t mvfr0;
+
+    mvfr0 = FPU->MVFR0;
+    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+        return 1U;           /* Single precision FPU */
+    }
+    else {
+        return 0U;           /* No FPU */
+    }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h
new file mode 100644
index 000000000..c09acc824
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h
@@ -0,0 +1,2592 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM7_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM7_REV
+#define __CM7_REV               0x0000U
+#warning "__CM7_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          0U
+#warning "__ICACHE_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          0U
+#warning "__DCACHE_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DTCM_PRESENT
+#define __DTCM_PRESENT            0U
+#warning "__DTCM_PRESENT        not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
+        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
+        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24U];
+    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24U];
+    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24U];
+    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24U];
+    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56U];
+    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+    uint32_t RESERVED3[93U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+    uint32_t RESERVED4[15U];
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+    uint32_t RESERVED5[1U];
+    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+    uint32_t RESERVED6[1U];
+    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+    uint32_t RESERVED7[6U];
+    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[6U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+    uint32_t RESERVED3[981U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+    __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    uint32_t mvfr0;
+
+    mvfr0 = SCB->MVFR0;
+    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+        return 2U;           /* Double + Single precision FPU */
+    }
+    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+        return 1U;           /* Single precision FPU */
+    }
+    else {
+        return 0U;           /* No FPU */
+    }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+        do {
+            SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                          ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+#if defined ( __CC_ARM )
+            __schedule_barrier();
+#endif
+        } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    register uint32_t ccsidr;
+    register uint32_t sets;
+    register uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+        do {
+            SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                           ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+#if defined ( __CC_ARM )
+            __schedule_barrier();
+#endif
+        } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+        do {
+            SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                          ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+#if defined ( __CC_ARM )
+            __schedule_barrier();
+#endif
+        } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+        do {
+            SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                          ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+#if defined ( __CC_ARM )
+            __schedule_barrier();
+#endif
+        } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+        do {
+            SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                           ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+#if defined ( __CC_ARM )
+            __schedule_barrier();
+#endif
+        } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+        SCB->DCIMVAC = op_addr;
+        op_addr += (uint32_t)linesize;
+        op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+        SCB->DCCMVAC = op_addr;
+        op_addr += (uint32_t)linesize;
+        op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+        SCB->DCCIMVAC = op_addr;
+        op_addr += (uint32_t)linesize;
+        op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h
new file mode 100644
index 000000000..ed1063364
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                     __SC000_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC000_REV
+#define __SC000_REV             0x0000U
+#warning "__SC000_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 1;              /*!< bit:      0  Reserved */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[31U];
+    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[31U];
+    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[31U];
+    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[31U];
+    uint32_t RESERVED4[64U];
+    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    uint32_t RESERVED1[154U];
+    __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h
new file mode 100644
index 000000000..a1b17e1ce
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h
@@ -0,0 +1,1851 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                     __SC300_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC300_REV
+#define __SC300_REV               0x0000U
+#warning "__SC300_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
+        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
+        uint32_t _reserved1: 8;              /*!< bit: 16..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
+        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24U];
+    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24U];
+    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24U];
+    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24U];
+    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56U];
+    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    uint32_t RESERVED0[5U];
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+    uint32_t RESERVED1[129U];
+    __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+    uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[6U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h
new file mode 100644
index 000000000..cd6d8ab07
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date:        21. September 2016
+ * $Revision:    V1.0
+ *
+ * Project:      TrustZone for ARMv8-M
+ * Title:        Context Management for ARMv8-M TrustZone
+ *
+ * Version 1.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include <stdint.h>
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif  // TZ_CONTEXT_H
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h
new file mode 100644
index 000000000..dfea7460e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_common_tables.h
+ * Description:  Extern declaration for common tables
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h
new file mode 100644
index 000000000..84ffe8b85
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_const_structs.h
+ * Description:  Constant structs that are initialized for user convenience.
+ *               For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h
new file mode 100644
index 000000000..9d678052b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h
@@ -0,0 +1,7122 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_math.h
+ * Description:  Public header file for CMSIS DSP Library
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+   * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
+   * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
+   * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
+   * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
+   * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+   * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
+   *
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - ARM_MATH_ARMV8MxL:
+   *
+   * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
+   * on ARMv8M Mainline target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+   *
+   * - __DSP_PRESENT:
+   *
+   * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+#include "core_cm7.h"
+#define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+#include "core_armv8mbl.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+#include "core_armv8mml.h"
+#if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+#define ARM_MATH_DSP
+#endif
+#else
+#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31          (0x100)
+#define DELTA_Q15          0x5
+#define INDEX_MASK         0x0000003F
+#ifndef PI
+#define PI               3.14159265358979f
+#endif
+
+/**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+/**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+/* 1.31(q31) Fixed value of 2/360 */
+/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING         0xB60B61
+
+/**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+#define ALIGN4
+#else
+#if defined  (__GNUC__)
+#define ALIGN4 __attribute__((aligned(4)))
+#else
+#define ALIGN4 __align(4)
+#endif
+#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @brief Error status returned by some functions in the library.
+ */
+
+typedef enum {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+} arm_status;
+
+/**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+typedef int8_t q7_t;
+
+/**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+typedef int16_t q15_t;
+
+/**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+typedef int32_t q31_t;
+
+/**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+typedef int64_t q63_t;
+
+/**
+ * @brief 32-bit floating-point type definition.
+ */
+typedef float float32_t;
+
+/**
+ * @brief 64-bit floating-point type definition.
+ */
+typedef double float64_t;
+
+/**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if   defined ( __CC_ARM )
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+#define __SIMD32_TYPE __unaligned int32_t
+#define CMSIS_UNUSED
+#define CMSIS_INLINE
+
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+#define __SIMD64(addr)        (*(int64_t **) & (addr))
+
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+/**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
+                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
+                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+/**
+* @brief definition to pack four 8 bit values.
+*/
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+/**
+ * @brief Clips Q63 to Q31 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+    q63_t x)
+{
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+           ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+}
+
+/**
+ * @brief Clips Q63 to Q15 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+    q63_t x)
+{
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+           ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+}
+
+/**
+ * @brief Clips Q31 to Q7 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+    q31_t x)
+{
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+           ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+}
+
+/**
+ * @brief Clips Q31 to Q15 values.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+    q31_t x)
+{
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+           ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+}
+
+/**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+    q63_t x,
+    q31_t y)
+{
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+}
+
+/*
+  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+  #define __CLZ __clz
+  #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+    q31_t data);
+
+CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+    q31_t data)
+{
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while ((data & mask) == 0) {
+        count += 1u;
+        mask = mask >> 1u;
+    }
+
+    return (count);
+}
+#endif
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+    q31_t in,
+    q31_t* dst,
+    q31_t* pRecipTable)
+{
+    q31_t out;
+    uint32_t tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if (in > 0) {
+        signBits = ((uint32_t) (__CLZ( in) - 1));
+    }
+    else {
+        signBits = ((uint32_t) (__CLZ(-in) - 1));
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >> 24);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++) {
+        tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+        tempVal = 0x7FFFFFFFu - tempVal;
+        /*      1.31 with exp 1 */
+        /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+        out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+}
+
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+    q15_t in,
+    q15_t* dst,
+    q15_t* pRecipTable)
+{
+    q15_t out = 0;
+    uint32_t tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if (in > 0) {
+        signBits = ((uint32_t)(__CLZ( in) - 17));
+    }
+    else {
+        signBits = ((uint32_t)(__CLZ(-in) - 17));
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >>  8);
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++) {
+        tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+        tempVal = 0x7FFFu - tempVal;
+        /*      1.15 with exp 1 */
+        out = (q15_t) (((q31_t) out * tempVal) >> 14);
+        /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+}
+
+
+/*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
+    q31_t x,
+    uint32_t y)
+{
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++) {
+        posMax = posMax * 2;
+    }
+
+    if (x > 0) {
+        posMax = (posMax - 1);
+
+        if (x > posMax) {
+            x = posMax;
+        }
+    }
+    else {
+        negMin = -posMax;
+
+        if (x < negMin) {
+            x = negMin;
+        }
+    }
+    return (x);
+}
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+
+/*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+    uint32_t x,
+    uint32_t y)
+{
+    /*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
+    q31_t r = 0, s = 0;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+    uint32_t x,
+    uint32_t y)
+{
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+}
+
+
+/*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+    uint32_t x,
+    uint32_t y)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+}
+
+/*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+    uint32_t x,
+    uint32_t y)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+}
+
+
+/*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+    int32_t x,
+    int32_t y)
+{
+    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+}
+
+
+/*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+    int32_t x,
+    int32_t y)
+{
+    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+}
+
+
+/*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+    uint32_t x,
+    uint32_t y,
+    uint32_t sum)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+}
+
+
+/*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+    uint32_t x,
+    uint32_t y,
+    uint32_t sum)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+}
+
+
+/*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+    uint32_t x,
+    uint32_t y,
+    uint32_t sum)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+}
+
+
+/*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+    uint32_t x,
+    uint32_t y,
+    uint64_t sum)
+{
+    /*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+}
+
+
+/*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+    uint32_t x,
+    uint32_t y,
+    uint64_t sum)
+{
+    /*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+}
+
+
+/*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+    uint32_t x,
+    uint32_t y)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+}
+
+
+/*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+    uint32_t x,
+    uint32_t y)
+{
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+}
+
+
+/*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+    uint32_t x)
+{
+    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
+}
+
+/*
+ * @brief C custom defined SMMLA for M3 and M0 processors
+ */
+CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+    int32_t x,
+    int32_t y,
+    int32_t sum)
+{
+    return (sum + (int32_t) (((int64_t) x * y) >> 32));
+}
+
+#if 0
+/*
+ * @brief C custom defined PKHBT for unavailable DSP extension
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
+    uint32_t x,
+    uint32_t y,
+    uint32_t leftshift)
+{
+    return ( ((x             ) & 0x0000FFFFUL) |
+             ((y << leftshift) & 0xFFFF0000UL)  );
+}
+
+/*
+ * @brief C custom defined PKHTB for unavailable DSP extension
+ */
+CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
+    uint32_t x,
+    uint32_t y,
+    uint32_t rightshift)
+{
+    return ( ((x              ) & 0xFFFF0000UL) |
+             ((y >> rightshift) & 0x0000FFFFUL)  );
+}
+#endif
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+/**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q7;
+
+/**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in]  S          points to an instance of the Q7 FIR filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_q7(
+    const arm_fir_instance_q7* S,
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q7 FIR filter.
+ * @param[in,out] S          points to an instance of the Q7 FIR structure.
+ * @param[in]     numTaps    Number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of samples that are processed.
+ */
+void arm_fir_init_q7(
+    arm_fir_instance_q7* S,
+    uint16_t numTaps,
+    q7_t* pCoeffs,
+    q7_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in]  S          points to an instance of the Q15 FIR structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_q15(
+    const arm_fir_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q15 FIR filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_fast_q15(
+    const arm_fir_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 FIR filter.
+ * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
+ * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+arm_status arm_fir_init_q15(
+    arm_fir_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in]  S          points to an instance of the Q31 FIR filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_q31(
+    const arm_fir_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q31 FIR structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_fast_q31(
+    const arm_fir_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 FIR filter.
+ * @param[in,out] S          points to an instance of the Q31 FIR structure.
+ * @param[in]     numTaps    Number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of samples that are processed at a time.
+ */
+void arm_fir_init_q31(
+    arm_fir_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in]  S          points to an instance of the floating-point FIR structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_f32(
+    const arm_fir_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point FIR filter.
+ * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
+ * @param[in]     numTaps    Number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of samples that are processed at a time.
+ */
+void arm_fir_init_f32(
+    arm_fir_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+typedef struct {
+    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t* pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t* pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
+} arm_biquad_casd_df1_inst_q15;
+
+/**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+typedef struct {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t* pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t* pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+} arm_biquad_casd_df1_inst_q31;
+
+/**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+typedef struct {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t* pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_casd_df1_inst_f32;
+
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df1_q15(
+    const arm_biquad_casd_df1_inst_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cascade_df1_init_q15(
+    arm_biquad_casd_df1_inst_q15* S,
+    uint8_t numStages,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    int8_t postShift);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df1_fast_q15(
+    const arm_biquad_casd_df1_inst_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df1_q31(
+    const arm_biquad_casd_df1_inst_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df1_fast_q31(
+    const arm_biquad_casd_df1_inst_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cascade_df1_init_q31(
+    arm_biquad_casd_df1_inst_q31* S,
+    uint8_t numStages,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    int8_t postShift);
+
+
+/**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df1_f32(
+    const arm_biquad_casd_df1_inst_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ */
+void arm_biquad_cascade_df1_init_f32(
+    arm_biquad_casd_df1_inst_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t* pData;     /**< points to the data of the matrix. */
+} arm_matrix_instance_f32;
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t* pData;     /**< points to the data of the matrix. */
+} arm_matrix_instance_f64;
+
+/**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t* pData;         /**< points to the data of the matrix. */
+} arm_matrix_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t* pData;         /**< points to the data of the matrix. */
+} arm_matrix_instance_q31;
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in]   pSrcA  points to the first input matrix structure
+ * @param[in]   pSrcB  points to the second input matrix structure
+ * @param[out]  pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15, complex,  matrix multiplication.
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pScratch);
+
+
+/**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in]  pSrc  points to the input matrix
+ * @param[out] pDst  points to the output matrix
+ * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f32(
+    const arm_matrix_instance_f32* pSrc,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix transpose.
+ * @param[in]  pSrc  points to the input matrix
+ * @param[out] pDst  points to the output matrix
+ * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q15(
+    const arm_matrix_instance_q15* pSrc,
+    arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix transpose.
+ * @param[in]  pSrc  points to the input matrix
+ * @param[out] pDst  points to the output matrix
+ * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q31(
+    const arm_matrix_instance_q31* pSrc,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix multiplication
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in]  pSrcA   points to the first input matrix structure
+ * @param[in]  pSrcB   points to the second input matrix structure
+ * @param[out] pDst    points to output matrix structure
+ * @param[in]  pState  points to the array for storing intermediate results
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pState);
+
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA   points to the first input matrix structure
+ * @param[in]  pSrcB   points to the second input matrix structure
+ * @param[out] pDst    points to output matrix structure
+ * @param[in]  pState  points to the array for storing intermediate results
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pState);
+
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix subtraction
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix subtraction
+ * @param[in]  pSrcA  points to the first input matrix structure
+ * @param[in]  pSrcB  points to the second input matrix structure
+ * @param[out] pDst   points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in]  pSrc   points to the input matrix
+ * @param[in]  scale  scale factor
+ * @param[out] pDst   points to the output matrix
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f32(
+    const arm_matrix_instance_f32* pSrc,
+    float32_t scale,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in]  pSrc        points to input matrix
+ * @param[in]  scaleFract  fractional portion of the scale factor
+ * @param[in]  shift       number of bits to shift the result by
+ * @param[out] pDst        points to output matrix
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q15(
+    const arm_matrix_instance_q15* pSrc,
+    q15_t scaleFract,
+    int32_t shift,
+    arm_matrix_instance_q15* pDst);
+
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in]  pSrc        points to input matrix
+ * @param[in]  scaleFract  fractional portion of the scale factor
+ * @param[in]  shift       number of bits to shift the result by
+ * @param[out] pDst        points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q31(
+    const arm_matrix_instance_q31* pSrc,
+    q31_t scaleFract,
+    int32_t shift,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief  Q31 matrix initialization.
+ * @param[in,out] S         points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows     number of rows in the matrix.
+ * @param[in]     nColumns  number of columns in the matrix.
+ * @param[in]     pData     points to the matrix data array.
+ */
+void arm_mat_init_q31(
+    arm_matrix_instance_q31* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    q31_t* pData);
+
+
+/**
+ * @brief  Q15 matrix initialization.
+ * @param[in,out] S         points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows     number of rows in the matrix.
+ * @param[in]     nColumns  number of columns in the matrix.
+ * @param[in]     pData     points to the matrix data array.
+ */
+void arm_mat_init_q15(
+    arm_matrix_instance_q15* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    q15_t* pData);
+
+
+/**
+ * @brief  Floating-point matrix initialization.
+ * @param[in,out] S         points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows     number of rows in the matrix.
+ * @param[in]     nColumns  number of columns in the matrix.
+ * @param[in]     pData     points to the matrix data array.
+ */
+void arm_mat_init_f32(
+    arm_matrix_instance_f32* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    float32_t* pData);
+
+
+
+/**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+typedef struct {
+    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];     /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+} arm_pid_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+typedef struct {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+} arm_pid_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+typedef struct {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;          /**< The proportional gain. */
+    float32_t Ki;          /**< The integral gain. */
+    float32_t Kd;          /**< The derivative gain. */
+} arm_pid_instance_f32;
+
+
+
+/**
+ * @brief  Initialization function for the floating-point PID Control.
+ * @param[in,out] S               points to an instance of the PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_f32(
+    arm_pid_instance_f32* S,
+    int32_t resetStateFlag);
+
+
+/**
+ * @brief  Reset function for the floating-point PID Control.
+ * @param[in,out] S  is an instance of the floating-point PID Control structure
+ */
+void arm_pid_reset_f32(
+    arm_pid_instance_f32* S);
+
+
+/**
+ * @brief  Initialization function for the Q31 PID Control.
+ * @param[in,out] S               points to an instance of the Q15 PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_q31(
+    arm_pid_instance_q31* S,
+    int32_t resetStateFlag);
+
+
+/**
+ * @brief  Reset function for the Q31 PID Control.
+ * @param[in,out] S   points to an instance of the Q31 PID Control structure
+ */
+
+void arm_pid_reset_q31(
+    arm_pid_instance_q31* S);
+
+
+/**
+ * @brief  Initialization function for the Q15 PID Control.
+ * @param[in,out] S               points to an instance of the Q15 PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_q15(
+    arm_pid_instance_q15* S,
+    int32_t resetStateFlag);
+
+
+/**
+ * @brief  Reset function for the Q15 PID Control.
+ * @param[in,out] S  points to an instance of the q15 PID Control structure
+ */
+void arm_pid_reset_q15(
+    arm_pid_instance_q15* S);
+
+
+/**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+typedef struct {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t* pYData;          /**< pointer to the table of Y values */
+} arm_linear_interp_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t* pData;   /**< points to the data table. */
+} arm_bilinear_interp_instance_f32;
+
+/**
+* @brief Instance structure for the Q31 bilinear interpolation function.
+*/
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t* pData;       /**< points to the data table. */
+} arm_bilinear_interp_instance_q31;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t* pData;       /**< points to the data table. */
+} arm_bilinear_interp_instance_q15;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t* pData;        /**< points to the data table. */
+} arm_bilinear_interp_instance_q7;
+
+
+/**
+ * @brief Q7 vector multiplication.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_mult_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector multiplication.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_mult_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_mult_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_mult_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t* pTwiddle;                 /**< points to the Sin twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q15(
+    arm_cfft_radix2_instance_q15* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q15(
+    const arm_cfft_radix2_instance_q15* S,
+    q15_t* pSrc);
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t* pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q15(
+    arm_cfft_radix4_instance_q15* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_q15(
+    const arm_cfft_radix4_instance_q15* S,
+    q15_t* pSrc);
+
+/**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t* pTwiddle;                 /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q31(
+    arm_cfft_radix2_instance_q31* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q31(
+    const arm_cfft_radix2_instance_q31* S,
+    q31_t* pSrc);
+
+/**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t* pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+void arm_cfft_radix4_q31(
+    const arm_cfft_radix4_instance_q31* S,
+    q31_t* pSrc);
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q31(
+    arm_cfft_radix4_instance_q31* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+} arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_f32(
+    arm_cfft_radix2_instance_f32* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_f32(
+    const arm_cfft_radix2_instance_f32* S,
+    float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+} arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_f32(
+    arm_cfft_radix4_instance_f32* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_f32(
+    const arm_cfft_radix4_instance_f32* S,
+    float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t* pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+} arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15* S,
+    q15_t* p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t* pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+} arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31* S,
+    q31_t* p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t* pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+} arm_cfft_instance_f32;
+
+void arm_cfft_f32(
+    const arm_cfft_instance_f32* S,
+    float32_t* p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+typedef struct {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t* pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t* pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15* pCfft;       /**< points to the complex FFT instance. */
+} arm_rfft_instance_q15;
+
+arm_status arm_rfft_init_q15(
+    arm_rfft_instance_q15* S,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_q15(
+    const arm_rfft_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst);
+
+/**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+typedef struct {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t* pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t* pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31* pCfft;         /**< points to the complex FFT instance. */
+} arm_rfft_instance_q31;
+
+arm_status arm_rfft_init_q31(
+    arm_rfft_instance_q31* S,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_q31(
+    const arm_rfft_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t* pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t* pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32* pCfft;        /**< points to the complex FFT instance. */
+} arm_rfft_instance_f32;
+
+arm_status arm_rfft_init_f32(
+    arm_rfft_instance_f32* S,
+    arm_cfft_radix4_instance_f32* S_CFFT,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_f32(
+    const arm_rfft_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;             /**< length of the real sequence */
+    float32_t* pTwiddleRFFT;         /**< Twiddle factors real stage  */
+} arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+    arm_rfft_fast_instance_f32* S,
+    uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+    arm_rfft_fast_instance_f32* S,
+    float32_t* p, float32_t* pOut,
+    uint8_t ifftFlag);
+
+/**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+typedef struct {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    float32_t normalize;                 /**< normalizing factor. */
+    float32_t* pTwiddle;                 /**< points to the twiddle factor table. */
+    float32_t* pCosFactor;               /**< points to the cosFactor table. */
+    arm_rfft_instance_f32* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_f32;
+
+
+/**
+ * @brief  Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+arm_status arm_dct4_init_f32(
+    arm_dct4_instance_f32* S,
+    arm_rfft_instance_f32* S_RFFT,
+    arm_cfft_radix4_instance_f32* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    float32_t normalize);
+
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in]     pState         points to state buffer.
+ * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+ */
+void arm_dct4_f32(
+    const arm_dct4_instance_f32* S,
+    float32_t* pState,
+    float32_t* pInlineBuffer);
+
+
+/**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+typedef struct {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q31_t normalize;                     /**< normalizing factor. */
+    q31_t* pTwiddle;                     /**< points to the twiddle factor table. */
+    q31_t* pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q31* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q31;
+
+
+/**
+ * @brief  Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+arm_status arm_dct4_init_q31(
+    arm_dct4_instance_q31* S,
+    arm_rfft_instance_q31* S_RFFT,
+    arm_cfft_radix4_instance_q31* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    q31_t normalize);
+
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in]     S              points to an instance of the Q31 DCT4 structure.
+ * @param[in]     pState         points to state buffer.
+ * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+ */
+void arm_dct4_q31(
+    const arm_dct4_instance_q31* S,
+    q31_t* pState,
+    q31_t* pInlineBuffer);
+
+
+/**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+typedef struct {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q15_t normalize;                     /**< normalizing factor. */
+    q15_t* pTwiddle;                     /**< points to the twiddle factor table. */
+    q15_t* pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q15* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q15;
+
+
+/**
+ * @brief  Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+arm_status arm_dct4_init_q15(
+    arm_dct4_instance_q15* S,
+    arm_rfft_instance_q15* S_RFFT,
+    arm_cfft_radix4_instance_q15* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    q15_t normalize);
+
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in]     S              points to an instance of the Q15 DCT4 structure.
+ * @param[in]     pState         points to state buffer.
+ * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+ */
+void arm_dct4_q15(
+    const arm_dct4_instance_q15* S,
+    q15_t* pState,
+    q15_t* pInlineBuffer);
+
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_add_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_add_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_add_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_add_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_sub_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_sub_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_sub_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_sub_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  scale      scale factor to be applied
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_scale_f32(
+    float32_t* pSrc,
+    float32_t scale,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in]  pSrc        points to the input vector
+ * @param[in]  scaleFract  fractional portion of the scale value
+ * @param[in]  shift       number of bits to shift the result by
+ * @param[out] pDst        points to the output vector
+ * @param[in]  blockSize   number of samples in the vector
+ */
+void arm_scale_q7(
+    q7_t* pSrc,
+    q7_t scaleFract,
+    int8_t shift,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in]  pSrc        points to the input vector
+ * @param[in]  scaleFract  fractional portion of the scale value
+ * @param[in]  shift       number of bits to shift the result by
+ * @param[out] pDst        points to the output vector
+ * @param[in]  blockSize   number of samples in the vector
+ */
+void arm_scale_q15(
+    q15_t* pSrc,
+    q15_t scaleFract,
+    int8_t shift,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in]  pSrc        points to the input vector
+ * @param[in]  scaleFract  fractional portion of the scale value
+ * @param[in]  shift       number of bits to shift the result by
+ * @param[out] pDst        points to the output vector
+ * @param[in]  blockSize   number of samples in the vector
+ */
+void arm_scale_q31(
+    q31_t* pSrc,
+    q31_t scaleFract,
+    int8_t shift,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[out] pDst       points to the output buffer
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_abs_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[out] pDst       points to the output buffer
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_abs_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[out] pDst       points to the output buffer
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_abs_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[out] pDst       points to the output buffer
+ * @param[in]  blockSize  number of samples in each vector
+ */
+void arm_abs_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[in]  blockSize  number of samples in each vector
+ * @param[out] result     output result returned here
+ */
+void arm_dot_prod_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    uint32_t blockSize,
+    float32_t* result);
+
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[in]  blockSize  number of samples in each vector
+ * @param[out] result     output result returned here
+ */
+void arm_dot_prod_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    uint32_t blockSize,
+    q31_t* result);
+
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[in]  blockSize  number of samples in each vector
+ * @param[out] result     output result returned here
+ */
+void arm_dot_prod_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    uint32_t blockSize,
+    q63_t* result);
+
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in]  pSrcA      points to the first input vector
+ * @param[in]  pSrcB      points to the second input vector
+ * @param[in]  blockSize  number of samples in each vector
+ * @param[out] result     output result returned here
+ */
+void arm_dot_prod_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    uint32_t blockSize,
+    q63_t* result);
+
+
+/**
+ * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_shift_q7(
+    q7_t* pSrc,
+    int8_t shiftBits,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_shift_q15(
+    q15_t* pSrc,
+    int8_t shiftBits,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_shift_q31(
+    q31_t* pSrc,
+    int8_t shiftBits,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Adds a constant offset to a floating-point vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  offset     is the offset to be added
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_offset_f32(
+    float32_t* pSrc,
+    float32_t offset,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Adds a constant offset to a Q7 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  offset     is the offset to be added
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_offset_q7(
+    q7_t* pSrc,
+    q7_t offset,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Adds a constant offset to a Q15 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  offset     is the offset to be added
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_offset_q15(
+    q15_t* pSrc,
+    q15_t offset,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Adds a constant offset to a Q31 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[in]  offset     is the offset to be added
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_offset_q31(
+    q31_t* pSrc,
+    q31_t offset,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Negates the elements of a floating-point vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_negate_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Negates the elements of a Q7 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_negate_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Negates the elements of a Q15 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_negate_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Negates the elements of a Q31 vector.
+ * @param[in]  pSrc       points to the input vector
+ * @param[out] pDst       points to the output vector
+ * @param[in]  blockSize  number of samples in the vector
+ */
+void arm_negate_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Copies the elements of a floating-point vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_copy_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Copies the elements of a Q7 vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_copy_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Copies the elements of a Q15 vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_copy_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Copies the elements of a Q31 vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_copy_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Fills a constant value into a floating-point vector.
+ * @param[in]  value      input value to be filled
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_fill_f32(
+    float32_t value,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Fills a constant value into a Q7 vector.
+ * @param[in]  value      input value to be filled
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_fill_q7(
+    q7_t value,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Fills a constant value into a Q15 vector.
+ * @param[in]  value      input value to be filled
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_fill_q15(
+    q15_t value,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Fills a constant value into a Q31 vector.
+ * @param[in]  value      input value to be filled
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_fill_q31(
+    q31_t value,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+void arm_conv_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA      points to the first input sequence.
+ * @param[in]  srcALen    length of the first input sequence.
+ * @param[in]  pSrcB      points to the second input sequence.
+ * @param[in]  srcBLen    length of the second input sequence.
+ * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+ * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void arm_conv_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+void arm_conv_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+ */
+void arm_conv_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA      points to the first input sequence.
+ * @param[in]  srcALen    length of the first input sequence.
+ * @param[in]  pSrcB      points to the second input sequence.
+ * @param[in]  srcBLen    length of the second input sequence.
+ * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+ * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void arm_conv_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+ */
+void arm_conv_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+/**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+ */
+void arm_conv_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+/**
+* @brief Convolution of Q7 sequences.
+* @param[in]  pSrcA      points to the first input sequence.
+* @param[in]  srcALen    length of the first input sequence.
+* @param[in]  pSrcB      points to the second input sequence.
+* @param[in]  srcBLen    length of the second input sequence.
+* @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+* @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+*/
+void arm_conv_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+ */
+void arm_conv_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst);
+
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in]  pSrcA       points to the first input sequence.
+ * @param[in]  srcALen     length of the first input sequence.
+ * @param[in]  pSrcB       points to the second input sequence.
+ * @param[in]  srcBLen     length of the second input sequence.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  firstIndex  is the first output sample to start with.
+ * @param[in]  numPoints   is the number of output points to be computed.
+ * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+arm_status arm_conv_partial_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+typedef struct {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q15_t* pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t* pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+typedef struct {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t* pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t* pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+typedef struct {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    float32_t* pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t* pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_decimate_f32(
+    const arm_fir_decimate_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
+ * @param[in]     numTaps    number of coefficients in the filter.
+ * @param[in]     M          decimation factor.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+arm_status arm_fir_decimate_init_f32(
+    arm_fir_decimate_instance_f32* S,
+    uint16_t numTaps,
+    uint8_t M,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_decimate_q15(
+    const arm_fir_decimate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_decimate_fast_q15(
+    const arm_fir_decimate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
+ * @param[in]     numTaps    number of coefficients in the filter.
+ * @param[in]     M          decimation factor.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+arm_status arm_fir_decimate_init_q15(
+    arm_fir_decimate_instance_q15* S,
+    uint16_t numTaps,
+    uint8_t M,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
+ * @param[in]  pSrc  points to the block of input data.
+ * @param[out] pDst  points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_q31(
+    const arm_fir_decimate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_decimate_fast_q31(
+    arm_fir_decimate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
+ * @param[in]     numTaps    number of coefficients in the filter.
+ * @param[in]     M          decimation factor.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+arm_status arm_fir_decimate_init_q31(
+    arm_fir_decimate_instance_q31* S,
+    uint16_t numTaps,
+    uint8_t M,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+typedef struct {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t* pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t* pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+typedef struct {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t* pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t* pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+typedef struct {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t* pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t* pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+} arm_fir_interpolate_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_interpolate_q15(
+    const arm_fir_interpolate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
+ * @param[in]     L          upsample factor.
+ * @param[in]     numTaps    number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficient buffer.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+arm_status arm_fir_interpolate_init_q15(
+    arm_fir_interpolate_instance_q15* S,
+    uint8_t L,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_interpolate_q31(
+    const arm_fir_interpolate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
+ * @param[in]     L          upsample factor.
+ * @param[in]     numTaps    number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficient buffer.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+arm_status arm_fir_interpolate_init_q31(
+    arm_fir_interpolate_instance_q31* S,
+    uint8_t L,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of input samples to process per call.
+ */
+void arm_fir_interpolate_f32(
+    const arm_fir_interpolate_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
+ * @param[in]     L          upsample factor.
+ * @param[in]     numTaps    number of filter coefficients in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficient buffer.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     blockSize  number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+arm_status arm_fir_interpolate_init_f32(
+    arm_fir_interpolate_instance_f32* S,
+    uint8_t L,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+typedef struct {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t* pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t* pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+} arm_biquad_cas_df1_32x64_ins_q31;
+
+
+/**
+ * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cas_df1_32x64_q31(
+    const arm_biquad_cas_df1_32x64_ins_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cas_df1_32x64_init_q31(
+    arm_biquad_cas_df1_32x64_ins_q31* S,
+    uint8_t numStages,
+    q31_t* pCoeffs,
+    q63_t* pState,
+    uint8_t postShift);
+
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_cascade_stereo_df2T_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f64;
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in]  S          points to an instance of the filter data structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df2T_f32(
+    const arm_biquad_cascade_df2T_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in]  S          points to an instance of the filter data structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_stereo_df2T_f32(
+    const arm_biquad_cascade_stereo_df2T_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in]  S          points to an instance of the filter data structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_biquad_cascade_df2T_f64(
+    const arm_biquad_cascade_df2T_instance_f64* S,
+    float64_t* pSrc,
+    float64_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the filter data structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ */
+void arm_biquad_cascade_df2T_init_f32(
+    arm_biquad_cascade_df2T_instance_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the filter data structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ */
+void arm_biquad_cascade_stereo_df2T_init_f32(
+    arm_biquad_cascade_stereo_df2T_instance_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S          points to an instance of the filter data structure.
+ * @param[in]     numStages  number of 2nd order stages in the filter.
+ * @param[in]     pCoeffs    points to the filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ */
+void arm_biquad_cascade_df2T_init_f64(
+    arm_biquad_cascade_df2T_instance_f64* S,
+    uint8_t numStages,
+    float64_t* pCoeffs,
+    float64_t* pState);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q15_t* pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q15_t* pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q31_t* pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q31_t* pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t* pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t* pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_f32;
+
+
+/**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S          points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+void arm_fir_lattice_init_q15(
+    arm_fir_lattice_instance_q15* S,
+    uint16_t numStages,
+    q15_t* pCoeffs,
+    q15_t* pState);
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_lattice_q15(
+    const arm_fir_lattice_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S          points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.   The array is of length numStages.
+ */
+void arm_fir_lattice_init_q31(
+    arm_fir_lattice_instance_q31* S,
+    uint16_t numStages,
+    q31_t* pCoeffs,
+    q31_t* pState);
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_lattice_q31(
+    const arm_fir_lattice_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+void arm_fir_lattice_init_f32(
+    arm_fir_lattice_instance_f32* S,
+    uint16_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_fir_lattice_f32(
+    const arm_fir_lattice_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q15_t* pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t* pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t* pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q31_t* pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t* pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t* pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    float32_t* pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t* pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t* pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_iir_lattice_f32(
+    const arm_iir_lattice_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
+ * @param[in] blockSize  number of samples to process.
+ */
+void arm_iir_lattice_init_f32(
+    arm_iir_lattice_instance_f32* S,
+    uint16_t numStages,
+    float32_t* pkCoeffs,
+    float32_t* pvCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_iir_lattice_q31(
+    const arm_iir_lattice_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S          points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process.
+ */
+void arm_iir_lattice_init_q31(
+    arm_iir_lattice_instance_q31* S,
+    uint16_t numStages,
+    q31_t* pkCoeffs,
+    q31_t* pvCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[out] pDst       points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_iir_lattice_q15(
+    const arm_iir_lattice_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process per call.
+ */
+void arm_iir_lattice_init_q15(
+    arm_iir_lattice_instance_q15* S,
+    uint16_t numStages,
+    q15_t* pkCoeffs,
+    q15_t* pvCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t* pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+} arm_lms_instance_f32;
+
+
+/**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in]  S          points to an instance of the floating-point LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_f32(
+    const arm_lms_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pRef,
+    float32_t* pOut,
+    float32_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S          points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to the coefficient buffer.
+ * @param[in] pState     points to state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ */
+void arm_lms_init_f32(
+    arm_lms_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    float32_t mu,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+} arm_lms_instance_q15;
+
+
+/**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S          points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to the coefficient buffer.
+ * @param[in] pState     points to the state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ * @param[in] postShift  bit shift applied to coefficients.
+ */
+void arm_lms_init_q15(
+    arm_lms_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    q15_t mu,
+    uint32_t blockSize,
+    uint32_t postShift);
+
+
+/**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_q15(
+    const arm_lms_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pRef,
+    q15_t* pOut,
+    q15_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+} arm_lms_instance_q31;
+
+
+/**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_q31(
+    const arm_lms_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pRef,
+    q31_t* pOut,
+    q31_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S          points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to coefficient buffer.
+ * @param[in] pState     points to state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ * @param[in] postShift  bit shift applied to coefficients.
+ */
+void arm_lms_init_q31(
+    arm_lms_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    q31_t mu,
+    uint32_t blockSize,
+    uint32_t postShift);
+
+
+/**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;         /**< step size that control filter coefficient updates. */
+    float32_t energy;     /**< saves previous frame energy. */
+    float32_t x0;         /**< saves previous input sample. */
+} arm_lms_norm_instance_f32;
+
+
+/**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_norm_f32(
+    arm_lms_norm_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pRef,
+    float32_t* pOut,
+    float32_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S          points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to coefficient buffer.
+ * @param[in] pState     points to state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ */
+void arm_lms_norm_init_f32(
+    arm_lms_norm_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    float32_t mu,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t* recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+} arm_lms_norm_instance_q31;
+
+
+/**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_norm_q31(
+    arm_lms_norm_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pRef,
+    q31_t* pOut,
+    q31_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to coefficient buffer.
+ * @param[in] pState     points to state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ * @param[in] postShift  bit shift applied to coefficients.
+ */
+void arm_lms_norm_init_q31(
+    arm_lms_norm_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    q31_t mu,
+    uint32_t blockSize,
+    uint8_t postShift);
+
+
+/**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< Number of coefficients in the filter. */
+    q15_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q15_t* recipTable;    /**< Points to the reciprocal initial value table. */
+    q15_t energy;         /**< saves previous frame energy. */
+    q15_t x0;             /**< saves previous input sample. */
+} arm_lms_norm_instance_q15;
+
+
+/**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in]  pSrc       points to the block of input data.
+ * @param[in]  pRef       points to the block of reference data.
+ * @param[out] pOut       points to the block of output data.
+ * @param[out] pErr       points to the block of error data.
+ * @param[in]  blockSize  number of samples to process.
+ */
+void arm_lms_norm_q15(
+    arm_lms_norm_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pRef,
+    q15_t* pOut,
+    q15_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps    number of filter coefficients.
+ * @param[in] pCoeffs    points to coefficient buffer.
+ * @param[in] pState     points to state buffer.
+ * @param[in] mu         step size that controls filter coefficient updates.
+ * @param[in] blockSize  number of samples to process.
+ * @param[in] postShift  bit shift applied to coefficients.
+ */
+void arm_lms_norm_init_q15(
+    arm_lms_norm_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    q15_t mu,
+    uint32_t blockSize,
+    uint8_t postShift);
+
+
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst);
+
+
+/**
+* @brief Correlation of Q15 sequences
+* @param[in]  pSrcA     points to the first input sequence.
+* @param[in]  srcALen   length of the first input sequence.
+* @param[in]  pSrcB     points to the second input sequence.
+* @param[in]  srcBLen   length of the second input sequence.
+* @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+* @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void arm_correlate_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch);
+
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+void arm_correlate_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+void arm_correlate_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in]  pSrcA     points to the first input sequence.
+ * @param[in]  srcALen   length of the first input sequence.
+ * @param[in]  pSrcB     points to the second input sequence.
+ * @param[in]  srcBLen   length of the second input sequence.
+ * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void arm_correlate_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch);
+
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+/**
+  * @brief Correlation of Q7 sequences.
+  * @param[in]  pSrcA      points to the first input sequence.
+  * @param[in]  srcALen    length of the first input sequence.
+  * @param[in]  pSrcB      points to the second input sequence.
+  * @param[in]  srcBLen    length of the second input sequence.
+  * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+  * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+  * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+  */
+void arm_correlate_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst);
+
+
+/**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t* pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_f32;
+
+/**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q31;
+
+/**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q15;
+
+/**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t* pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t* pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q7;
+
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
+ * @param[in]  pSrc        points to the block of input data.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize   number of input samples to process per call.
+ */
+void arm_fir_sparse_f32(
+    arm_fir_sparse_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    float32_t* pScratchIn,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     pCoeffs    points to the array of filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     pTapDelay  points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_f32(
+    arm_fir_sparse_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
+ * @param[in]  pSrc        points to the block of input data.
+ * @param[out] pDst        points to the block of output data
+ * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize   number of input samples to process per call.
+ */
+void arm_fir_sparse_q31(
+    arm_fir_sparse_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    q31_t* pScratchIn,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     pCoeffs    points to the array of filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     pTapDelay  points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q31(
+    arm_fir_sparse_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
+ * @param[in]  pSrc         points to the block of input data.
+ * @param[out] pDst         points to the block of output data
+ * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+ * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize    number of input samples to process per call.
+ */
+void arm_fir_sparse_q15(
+    arm_fir_sparse_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    q15_t* pScratchIn,
+    q31_t* pScratchOut,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     pCoeffs    points to the array of filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     pTapDelay  points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q15(
+    arm_fir_sparse_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
+ * @param[in]  pSrc         points to the block of input data.
+ * @param[out] pDst         points to the block of output data
+ * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+ * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize    number of input samples to process per call.
+ */
+void arm_fir_sparse_q7(
+    arm_fir_sparse_instance_q7* S,
+    q7_t* pSrc,
+    q7_t* pDst,
+    q7_t* pScratchIn,
+    q31_t* pScratchOut,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     pCoeffs    points to the array of filter coefficients.
+ * @param[in]     pState     points to the state buffer.
+ * @param[in]     pTapDelay  points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q7(
+    arm_fir_sparse_instance_q7* S,
+    uint16_t numTaps,
+    q7_t* pCoeffs,
+    q7_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Floating-point sin_cos function.
+ * @param[in]  theta   input value in degrees
+ * @param[out] pSinVal  points to the processed sine output.
+ * @param[out] pCosVal  points to the processed cos output.
+ */
+void arm_sin_cos_f32(
+    float32_t theta,
+    float32_t* pSinVal,
+    float32_t* pCosVal);
+
+
+/**
+ * @brief  Q31 sin_cos function.
+ * @param[in]  theta    scaled input value in degrees
+ * @param[out] pSinVal  points to the processed sine output.
+ * @param[out] pCosVal  points to the processed cosine output.
+ */
+void arm_sin_cos_q31(
+    q31_t theta,
+    q31_t* pSinVal,
+    q31_t* pCosVal);
+
+
+/**
+ * @brief  Floating-point complex conjugate.
+ * @param[in]  pSrc        points to the input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_conj_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex conjugate.
+ * @param[in]  pSrc        points to the input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_conj_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q15 complex conjugate.
+ * @param[in]  pSrc        points to the input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_conj_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Floating-point complex magnitude squared
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q31 complex magnitude squared
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q15 complex magnitude squared
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+  * @ingroup groupController
+  */
+
+/**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd  </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief  Process function for the floating-point PID Control.
+ * @param[in,out] S   is an instance of the floating-point PID Control structure
+ * @param[in]     in  input sample to process
+ * @return out processed output sample.
+ */
+CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+    arm_pid_instance_f32* S,
+    float32_t in)
+{
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+          (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+}
+
+/**
+ * @brief  Process function for the Q31 PID Control.
+ * @param[in,out] S  points to an instance of the Q31 PID Control structure
+ * @param[in]     in  input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+    arm_pid_instance_q31* S,
+    q31_t in)
+{
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+}
+
+
+/**
+ * @brief  Process function for the Q15 PID Control.
+ * @param[in,out] S   points to an instance of the Q15 PID Control structure
+ * @param[in]     in  input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+    arm_pid_instance_q15* S,
+    q15_t in)
+{
+    q63_t acc;
+    q15_t out;
+
+#if defined (ARM_MATH_DSP)
+    __SIMD32_TYPE* vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc);
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+}
+
+/**
+ * @} end of PID group
+ */
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in]  src   points to the instance of the input floating-point matrix structure.
+ * @param[out] dst   points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+arm_status arm_mat_inverse_f32(
+    const arm_matrix_instance_f32* src,
+    arm_matrix_instance_f32* dst);
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in]  src   points to the instance of the input floating-point matrix structure.
+ * @param[out] dst   points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+arm_status arm_mat_inverse_f64(
+    const arm_matrix_instance_f64* src,
+    arm_matrix_instance_f64* dst);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup clarke
+ * @{
+ */
+
+/**
+ *
+ * @brief  Floating-point Clarke transform
+ * @param[in]  Ia       input three-phase coordinate <code>a</code>
+ * @param[in]  Ib       input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+    float32_t Ia,
+    float32_t Ib,
+    float32_t* pIalpha,
+    float32_t* pIbeta)
+{
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+}
+
+
+/**
+ * @brief  Clarke transform for Q31 version
+ * @param[in]  Ia       input three-phase coordinate <code>a</code>
+ * @param[in]  Ib       input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+    q31_t Ia,
+    q31_t Ib,
+    q31_t* pIalpha,
+    q31_t* pIbeta)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+}
+
+/**
+ * @} end of clarke group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_q7_to_q31(
+    q7_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+/**
+* @brief  Floating-point Inverse Clarke transform
+* @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+* @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+* @param[out] pIa     points to output three-phase coordinate <code>a</code>
+* @param[out] pIb     points to output three-phase coordinate <code>b</code>
+*/
+CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+    float32_t Ialpha,
+    float32_t Ibeta,
+    float32_t* pIa,
+    float32_t* pIb)
+{
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+}
+
+
+/**
+ * @brief  Inverse Clarke transform for Q31 version
+ * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+ * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+ * @param[out] pIa     points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb     points to output three-phase coordinate <code>b</code>
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+    q31_t Ialpha,
+    q31_t Ibeta,
+    q31_t* pIa,
+    q31_t* pIb)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+}
+
+/**
+ * @} end of inv_clarke group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in]  pSrc       input pointer
+ * @param[out] pDst       output pointer
+ * @param[in]  blockSize  number of samples to process
+ */
+void arm_q7_to_q15(
+    q7_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup park
+ * @{
+ */
+
+/**
+ * @brief Floating-point Park transform
+ * @param[in]  Ialpha  input two-phase vector coordinate alpha
+ * @param[in]  Ibeta   input two-phase vector coordinate beta
+ * @param[out] pId     points to output   rotor reference frame d
+ * @param[out] pIq     points to output   rotor reference frame q
+ * @param[in]  sinVal  sine value of rotation angle theta
+ * @param[in]  cosVal  cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+    float32_t Ialpha,
+    float32_t Ibeta,
+    float32_t* pId,
+    float32_t* pIq,
+    float32_t sinVal,
+    float32_t cosVal)
+{
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+}
+
+
+/**
+ * @brief  Park transform for Q31 version
+ * @param[in]  Ialpha  input two-phase vector coordinate alpha
+ * @param[in]  Ibeta   input two-phase vector coordinate beta
+ * @param[out] pId     points to output rotor reference frame d
+ * @param[out] pIq     points to output rotor reference frame q
+ * @param[in]  sinVal  sine value of rotation angle theta
+ * @param[in]  cosVal  cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+    q31_t Ialpha,
+    q31_t Ibeta,
+    q31_t* pId,
+    q31_t* pIq,
+    q31_t sinVal,
+    q31_t cosVal)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+}
+
+/**
+ * @} end of park group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q7_to_float(
+    q7_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_park
+ * @{
+ */
+
+/**
+* @brief  Floating-point Inverse Park transform
+* @param[in]  Id       input coordinate of rotor reference frame d
+* @param[in]  Iq       input coordinate of rotor reference frame q
+* @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+* @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+* @param[in]  sinVal   sine value of rotation angle theta
+* @param[in]  cosVal   cosine value of rotation angle theta
+*/
+CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+    float32_t Id,
+    float32_t Iq,
+    float32_t* pIalpha,
+    float32_t* pIbeta,
+    float32_t sinVal,
+    float32_t cosVal)
+{
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+}
+
+
+/**
+ * @brief  Inverse Park transform for   Q31 version
+ * @param[in]  Id       input coordinate of rotor reference frame d
+ * @param[in]  Iq       input coordinate of rotor reference frame q
+ * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+ * @param[in]  sinVal   sine value of rotation angle theta
+ * @param[in]  cosVal   cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+    q31_t Id,
+    q31_t Iq,
+    q31_t* pIalpha,
+    q31_t* pIbeta,
+    q31_t sinVal,
+    q31_t cosVal)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+}
+
+/**
+ * @} end of Inverse park group
+ */
+
+
+/**
+ * @brief  Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q31_to_float(
+    q31_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A  Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+/**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+/**
+ * @brief  Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
+ * @param[in]     x  input sample to process
+ * @return y processed output sample.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+    arm_linear_interp_instance_f32* S,
+    float32_t x)
+{
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t* pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if (i < 0) {
+        /* Iniatilize output for below specified range as least output value of table */
+        y = pYData[0];
+    }
+    else if ((uint32_t)i >= S->nValues) {
+        /* Iniatilize output for above specified range as last output value of table */
+        y = pYData[S->nValues - 1];
+    }
+    else {
+        /* Calculation of nearest input values */
+        x0 = S->x1 +  i      * xSpacing;
+        x1 = S->x1 + (i + 1) * xSpacing;
+
+        /* Read of nearest output values */
+        y0 = pYData[i];
+        y1 = pYData[i + 1];
+
+        /* Calculation of output */
+        y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+}
+
+
+/**
+*
+* @brief  Process function for the Q31 Linear Interpolation Function.
+* @param[in] pYData   pointer to Q31 Linear Interpolation table
+* @param[in] x        input sample to process
+* @param[in] nValues  number of table values
+* @return y processed output sample.
+*
+* \par
+* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+* This function can support maximum of table size 2^12.
+*
+*/
+CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+    q31_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (q31_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else if (index < 0) {
+        return (pYData[0]);
+    }
+    else {
+        /* 20 bits for the fractional part */
+        /* shift left by 11 to keep fract in 1.31 format */
+        fract = (x & 0x000FFFFF) << 11;
+
+        /* Read two nearest output values from the index in 1.31(q31) format */
+        y0 = pYData[index];
+        y1 = pYData[index + 1];
+
+        /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+        y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+        /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+        y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+        /* Convert y to 1.31 format */
+        return (y << 1u);
+    }
+}
+
+
+/**
+ *
+ * @brief  Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData   pointer to Q15 Linear Interpolation table
+ * @param[in] x        input sample to process
+ * @param[in] nValues  number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+    q15_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (int32_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else if (index < 0) {
+        return (pYData[0]);
+    }
+    else {
+        /* 20 bits for the fractional part */
+        /* fract is in 12.20 format */
+        fract = (x & 0x000FFFFF);
+
+        /* Read two nearest output values from the index */
+        y0 = pYData[index];
+        y1 = pYData[index + 1];
+
+        /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+        y = ((q63_t) y0 * (0xFFFFF - fract));
+
+        /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+        y += ((q63_t) y1 * (fract));
+
+        /* convert y to 1.15 format */
+        return (q15_t) (y >> 20);
+    }
+}
+
+
+/**
+ *
+ * @brief  Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData   pointer to Q7 Linear Interpolation table
+ * @param[in] x        input sample to process
+ * @param[in] nValues  number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+    q7_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0) {
+        return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+    if (index >= (nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else {
+        /* 20 bits for the fractional part */
+        /* fract is in 12.20 format */
+        fract = (x & 0x000FFFFF);
+
+        /* Read two nearest output values from the index and are in 1.7(q7) format */
+        y0 = pYData[index];
+        y1 = pYData[index + 1];
+
+        /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+        y = ((y0 * (0xFFFFF - fract)));
+
+        /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+        y += (y1 * fract);
+
+        /* convert y to 1.7(q7) format */
+        return (q7_t) (y >> 20);
+    }
+}
+
+/**
+ * @} end of LinearInterpolate group
+ */
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x  input value in radians.
+ * @return  sin(x).
+ */
+float32_t arm_sin_f32(
+    float32_t x);
+
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x  Scaled input value in radians.
+ * @return  sin(x).
+ */
+q31_t arm_sin_q31(
+    q31_t x);
+
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x  Scaled input value in radians.
+ * @return  sin(x).
+ */
+q15_t arm_sin_q15(
+    q15_t x);
+
+
+/**
+ * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x  input value in radians.
+ * @return  cos(x).
+ */
+float32_t arm_cos_f32(
+    float32_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x  Scaled input value in radians.
+ * @return  cos(x).
+ */
+q31_t arm_cos_q31(
+    q31_t x);
+
+
+/**
+ * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x  Scaled input value in radians.
+ * @return  cos(x).
+ */
+q15_t arm_cos_q15(
+    q15_t x);
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+
+/**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ *      x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ *     x0 = in/2                         [initial guess]
+ *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ * </pre>
+ */
+
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief  Floating-point square root function.
+ * @param[in]  in    input value.
+ * @param[out] pOut  square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+    float32_t in,
+    float32_t* pOut)
+{
+    if (in >= 0.0f) {
+
+#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
+        *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+        *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+        *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+        __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+        *pOut = sqrtf(in);
+#endif
+
+        return (ARM_MATH_SUCCESS);
+    }
+    else {
+        *pOut = 0.0f;
+        return (ARM_MATH_ARGUMENT_ERROR);
+    }
+}
+
+
+/**
+ * @brief Q31 square root function.
+ * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut  square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q31(
+    q31_t in,
+    q31_t* pOut);
+
+
+/**
+ * @brief  Q15 square root function.
+ * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut  square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q15(
+    q15_t in,
+    q15_t* pOut);
+
+/**
+ * @} end of SQRT group
+ */
+
+
+/**
+ * @brief floating-point Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+    int32_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const int32_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if (wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+}
+
+
+
+/**
+ * @brief floating-point Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+    int32_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    int32_t* dst,
+    int32_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if (dst == (int32_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update rOffset.  Watch out for positive and negative value  */
+        rOffset += bufferInc;
+
+        if (rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q15 Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+    q15_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const q15_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if (wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+}
+
+
+/**
+ * @brief Q15 Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+    q15_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    q15_t* dst,
+    q15_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if (dst == (q15_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        rOffset += bufferInc;
+
+        if (rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q7 Circular write function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+    q7_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const q7_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if (wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+}
+
+
+/**
+ * @brief Q7 Circular Read function.
+ */
+CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+    q7_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    q7_t* dst,
+    q7_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if (dst == (q7_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update rOffset.  Watch out for positive and negative value */
+        rOffset += bufferInc;
+
+        if (rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+
+/**
+ * @brief  Sum of the squares of the elements of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_power_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q63_t* pResult);
+
+
+/**
+ * @brief  Sum of the squares of the elements of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_power_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+
+/**
+ * @brief  Sum of the squares of the elements of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_power_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q63_t* pResult);
+
+
+/**
+ * @brief  Sum of the squares of the elements of a Q7 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_power_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+
+/**
+ * @brief  Mean value of a Q7 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_mean_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* pResult);
+
+
+/**
+ * @brief  Mean value of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_mean_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+
+/**
+ * @brief  Mean value of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_mean_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+
+/**
+ * @brief  Mean value of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_mean_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+
+/**
+ * @brief  Variance of the elements of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_var_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+
+/**
+ * @brief  Variance of the elements of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_var_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+
+/**
+ * @brief  Variance of the elements of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_var_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+
+/**
+ * @brief  Root Mean Square of the elements of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_rms_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+
+/**
+ * @brief  Root Mean Square of the elements of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_rms_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+
+/**
+ * @brief  Root Mean Square of the elements of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_rms_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+
+/**
+ * @brief  Standard deviation of the elements of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_std_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+
+/**
+ * @brief  Standard deviation of the elements of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_std_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+
+/**
+ * @brief  Standard deviation of the elements of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output value.
+ */
+void arm_std_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+
+/**
+ * @brief  Floating-point complex magnitude
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q31 complex magnitude
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q15 complex magnitude
+ * @param[in]  pSrc        points to the complex input vector
+ * @param[out] pDst        points to the real output vector
+ * @param[in]  numSamples  number of complex samples in the input vector
+ */
+void arm_cmplx_mag_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q15 complex dot product
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ * @param[out] realResult  real part of the result returned here
+ * @param[out] imagResult  imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    uint32_t numSamples,
+    q31_t* realResult,
+    q31_t* imagResult);
+
+
+/**
+ * @brief  Q31 complex dot product
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ * @param[out] realResult  real part of the result returned here
+ * @param[out] imagResult  imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    uint32_t numSamples,
+    q63_t* realResult,
+    q63_t* imagResult);
+
+
+/**
+ * @brief  Floating-point complex dot product
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ * @param[out] realResult  real part of the result returned here
+ * @param[out] imagResult  imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    uint32_t numSamples,
+    float32_t* realResult,
+    float32_t* imagResult);
+
+
+/**
+ * @brief  Q15 complex-by-real multiplication
+ * @param[in]  pSrcCmplx   points to the complex input vector
+ * @param[in]  pSrcReal    points to the real input vector
+ * @param[out] pCmplxDst   points to the complex output vector
+ * @param[in]  numSamples  number of samples in each vector
+ */
+void arm_cmplx_mult_real_q15(
+    q15_t* pSrcCmplx,
+    q15_t* pSrcReal,
+    q15_t* pCmplxDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q31 complex-by-real multiplication
+ * @param[in]  pSrcCmplx   points to the complex input vector
+ * @param[in]  pSrcReal    points to the real input vector
+ * @param[out] pCmplxDst   points to the complex output vector
+ * @param[in]  numSamples  number of samples in each vector
+ */
+void arm_cmplx_mult_real_q31(
+    q31_t* pSrcCmplx,
+    q31_t* pSrcReal,
+    q31_t* pCmplxDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Floating-point complex-by-real multiplication
+ * @param[in]  pSrcCmplx   points to the complex input vector
+ * @param[in]  pSrcReal    points to the real input vector
+ * @param[out] pCmplxDst   points to the complex output vector
+ * @param[in]  numSamples  number of samples in each vector
+ */
+void arm_cmplx_mult_real_f32(
+    float32_t* pSrcCmplx,
+    float32_t* pSrcReal,
+    float32_t* pCmplxDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Minimum value of a Q7 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] result     is output pointer
+ * @param[in]  index      is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* result,
+    uint32_t* index);
+
+
+/**
+ * @brief  Minimum value of a Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output pointer
+ * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief  Minimum value of a Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output pointer
+ * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief  Minimum value of a floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[in]  blockSize  is the number of samples to process
+ * @param[out] pResult    is output pointer
+ * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+ */
+void arm_min_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+void arm_max_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+void arm_max_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+void arm_max_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+void arm_max_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult,
+    uint32_t* pIndex);
+
+
+/**
+ * @brief  Q15 complex-by-complex multiplication
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Q31 complex-by-complex multiplication
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief  Floating-point complex-by-complex multiplication
+ * @param[in]  pSrcA       points to the first input vector
+ * @param[in]  pSrcB       points to the second input vector
+ * @param[out] pDst        points to the output vector
+ * @param[in]  numSamples  number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in]  pSrc       points to the floating-point input vector
+ * @param[out] pDst       points to the Q31 output vector
+ * @param[in]  blockSize  length of the input vector
+ */
+void arm_float_to_q31(
+    float32_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in]  pSrc       points to the floating-point input vector
+ * @param[out] pDst       points to the Q15 output vector
+ * @param[in]  blockSize  length of the input vector
+ */
+void arm_float_to_q15(
+    float32_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in]  pSrc       points to the floating-point input vector
+ * @param[out] pDst       points to the Q7 output vector
+ * @param[in]  blockSize  length of the input vector
+ */
+void arm_float_to_q7(
+    float32_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q31_to_q15(
+    q31_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q31_to_q7(
+    q31_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q15_to_float(
+    q15_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q15_to_q31(
+    q15_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in]  pSrc       is input pointer
+ * @param[out] pDst       is output pointer
+ * @param[in]  blockSize  is the number of samples to process
+ */
+void arm_q15_to_q7(
+    q15_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+ * <pre>
+ *     XF = floor(x)
+ *     YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+/**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+/**
+*
+* @brief  Floating-point bilinear interpolation.
+* @param[in,out] S  points to an instance of the interpolation structure.
+* @param[in]     X  interpolation coordinate.
+* @param[in]     Y  interpolation coordinate.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+    const arm_bilinear_interp_instance_f32* S,
+    float32_t X,
+    float32_t Y)
+{
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t* pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+}
+
+
+/**
+*
+* @brief  Q31 bilinear interpolation.
+* @param[in,out] S  points to an instance of the interpolation structure.
+* @param[in]     X  interpolation coordinate in 12.20 format.
+* @param[in]     Y  interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+    arm_bilinear_interp_instance_q31* S,
+    q31_t X,
+    q31_t Y)
+{
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t* pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
+    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
+    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return ((q31_t)(acc << 2));
+}
+
+
+/**
+* @brief  Q15 bilinear interpolation.
+* @param[in,out] S  points to an instance of the interpolation structure.
+* @param[in]     X  interpolation coordinate in 12.20 format.
+* @param[in]     Y  interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+    arm_bilinear_interp_instance_q15* S,
+    q31_t X,
+    q31_t Y)
+{
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t* pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return ((q15_t)(acc >> 36));
+}
+
+
+/**
+* @brief  Q7 bilinear interpolation.
+* @param[in,out] S  points to an instance of the interpolation structure.
+* @param[in]     X  interpolation coordinate in 12.20 format.
+* @param[in]     Y  interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+    arm_bilinear_interp_instance_q7* S,
+    q31_t X,
+    q31_t Y)
+{
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t* pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return ((q7_t)(acc >> 40));
+}
+
+/**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if   defined ( __CC_ARM )
+/* Enter low optimization region - place directly above function definition */
+#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+#define LOW_OPTIMIZATION_ENTER \
+    _Pragma ("push")         \
+    _Pragma ("O1")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define LOW_OPTIMIZATION_EXIT \
+    _Pragma ("pop")
+#else
+#define LOW_OPTIMIZATION_EXIT
+#endif
+
+/* Enter low optimization region - place directly above function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+/* Exit low optimization region - place directly after end of function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+#define LOW_OPTIMIZATION_ENTER \
+    __attribute__(( optimize("-O1") ))
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+/* Enter low optimization region - place directly above function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define LOW_OPTIMIZATION_ENTER \
+    _Pragma ("optimize=low")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#define LOW_OPTIMIZATION_EXIT
+
+/* Enter low optimization region - place directly above function definition */
+#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+    _Pragma ("optimize=low")
+#else
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef   __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h
new file mode 100644
index 000000000..4617b1280
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h
@@ -0,0 +1,796 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
+ * @version  V5.0.1
+ * @date     03. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+#define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+#define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+#define __ARM_ARCH_7EM__          1
+#endif
+
+/* __ARM_ARCH_8M_BASE__  not applicable */
+/* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  __inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static __inline
+#endif
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __declspec(noreturn)
+#endif
+#ifndef   __USED
+#define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+#define __UNALIGNED_UINT32(x)     (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __ALIGNED
+#define __ALIGNED(x)              __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           __packed struct
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    register uint32_t __regControl         __ASM("control");
+    return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    register uint32_t __regControl         __ASM("control");
+    __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    register uint32_t __regIPSR          __ASM("ipsr");
+    return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+    register uint32_t __regAPSR          __ASM("apsr");
+    return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    register uint32_t __regXPSR          __ASM("xpsr");
+    return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    register uint32_t __regPriMask         __ASM("primask");
+    return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    register uint32_t __regPriMask         __ASM("primask");
+    __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+    register uint32_t __regBasePri         __ASM("basepri");
+    return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+    register uint32_t __regBasePri         __ASM("basepri");
+    __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+    register uint32_t __regBasePriMax      __ASM("basepri_max");
+    __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    register uint32_t __regfpscr         __ASM("fpscr");
+    return(__regfpscr);
+#else
+    return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    register uint32_t __regfpscr         __ASM("fpscr");
+    __regfpscr = (fpscr);
+#else
+    (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+        __schedule_barrier();\
+        __isb(0xF);\
+        __schedule_barrier();\
+    } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+        __schedule_barrier();\
+        __dsb(0xF);\
+        __schedule_barrier();\
+    } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+        __schedule_barrier();\
+        __dmb(0xF);\
+        __schedule_barrier();\
+    } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+    rev16 r0, r0
+    bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+    revsh r0, r0
+    bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+#define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+    result = value;                      /* r will be reversed bits of v; first get LSB of v */
+    for (value >>= 1U; value; value >>= 1U) {
+        result <<= 1U;
+        result |= value & 1U;
+        s--;
+    }
+    result <<= s;                        /* shift when v's highest bits are zero */
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+#define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+#define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+#define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+#define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+#define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+#define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+    rrx r0, r0
+    bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h
new file mode 100644
index 000000000..6b21a5bea
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h
@@ -0,0 +1,1735 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version  V5.0.1
+ * @date     02. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  __inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static __inline
+#endif
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __attribute__((noreturn))
+#endif
+#ifndef   __USED
+#define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wpacked"
+struct __attribute__((packed)) T_UINT32 {
+    uint32_t v;
+};
+#pragma clang diagnostic pop
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#define __ALIGNED(x)              __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           struct __attribute__((packed, aligned(1)))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, control" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+    __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+    __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msp" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+    __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, primask" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+    __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+    __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+    return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+    __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+    __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+    return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+    __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+    __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+/* #define __get_FPSCR      __builtin_arm_get_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    uint32_t result;
+
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    return(result);
+#else
+    return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+/* #define __set_FPSCR      __builtin_arm_set_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+    (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV          __builtin_bswap32
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16          __builtin_bswap16                /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+    int32_t result;
+
+    __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+    return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+    result = value;                      /* r will be reversed bits of v; first get LSB of v */
+    for (value >>= 1U; value; value >>= 1U) {
+        result <<= 1U;
+        result |= value & 1U;
+        s--;
+    }
+    result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+    return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
+{
+    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
+{
+    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
+{
+    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
+{
+    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
+{
+    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
+{
+    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+    ({                          \
+        int32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+#define __USAT16(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+    int32_t result;
+
+    __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+    int32_t result;
+
+    __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        if (ARG3 == 0) \
+            __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+        else \
+            __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+    int32_t result;
+
+    __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h
new file mode 100644
index 000000000..89cd69027
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h
@@ -0,0 +1,231 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.1
+ * @date     30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+#include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+#include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static inline
+#endif
+
+#include <cmsis_iar.h>
+
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __noreturn
+#endif
+#ifndef   __USED
+#define __USED                    __root
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __weak
+#endif
+#ifndef   __UNALIGNED_UINT32
+__packed struct T_UINT32 {
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __packed
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           __packed struct
+#endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+#include <cmsis_ccs.h>
+
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static inline
+#endif
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __attribute__((noreturn))
+#endif
+#ifndef   __USED
+#define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+struct __attribute__((packed)) T_UINT32 {
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#define __ALIGNED(x)              __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           struct __attribute__((packed))
+#endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static inline
+#endif
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __attribute__((noreturn))
+#endif
+#ifndef   __USED
+#define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+struct __packed__ T_UINT32 {
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#define __ALIGNED(x)              __align(x)
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __packed__
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           struct __packed__
+#endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+#include <cmsis_csm.h>
+
+#ifndef   __ASM
+#define __ASM                     _asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static inline
+#endif
+#ifndef   __NO_RETURN
+// NO RETURN is automatically detected hence no warning here
+#define __NO_RETURN
+#endif
+#ifndef   __USED
+#warning No compiler specific solution for __USED. __USED is ignored.
+#define __USED
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __weak
+#endif
+#ifndef   __UNALIGNED_UINT32
+@packed struct T_UINT32 {
+    uint32_t v;
+};
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+#define __ALIGNED(x)
+#endif
+#ifndef   __PACKED
+#define __PACKED                  @packed
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           @packed struct
+#endif
+
+
+#else
+#error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h
new file mode 100644
index 000000000..919f26d15
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h
@@ -0,0 +1,1900 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.1
+ * @date     02. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+#define __ASM                     __asm
+#endif
+#ifndef   __INLINE
+#define __INLINE                  inline
+#endif
+#ifndef   __STATIC_INLINE
+#define __STATIC_INLINE           static inline
+#endif
+#ifndef   __NO_RETURN
+#define __NO_RETURN               __attribute__((noreturn))
+#endif
+#ifndef   __USED
+#define __USED                    __attribute__((used))
+#endif
+#ifndef   __WEAK
+#define __WEAK                    __attribute__((weak))
+#endif
+#ifndef   __UNALIGNED_UINT32
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpacked"
+#pragma GCC diagnostic ignored "-Wattributes"
+struct __attribute__((packed)) T_UINT32 {
+    uint32_t v;
+};
+#pragma GCC diagnostic pop
+#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __ALIGNED
+#define __ALIGNED(x)              __attribute__((aligned(x)))
+#endif
+#ifndef   __PACKED
+#define __PACKED                  __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+#define __PACKED_STRUCT           struct __attribute__((packed, aligned(1)))
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+    __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+    __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, control" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+    __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+    return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+    __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msp" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+    __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, primask" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+    __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+    __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+    __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+    __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+    return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+    __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+    return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+    __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+    __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+    return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+    return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+    __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+    __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    uint32_t result;
+
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    return(result);
+#else
+    return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#else
+    (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+//{
+//  __ASM volatile ("nop");
+//}
+#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+//{
+//  __ASM volatile ("wfi");
+//}
+#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+//{
+//  __ASM volatile ("wfe");
+//}
+#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+//{
+//  __ASM volatile ("sev");
+//}
+#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+    __ASM volatile ("isb 0xF"::: "memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+    __ASM volatile ("dsb 0xF"::: "memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+    __ASM volatile ("dmb 0xF"::: "memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+    return __builtin_bswap32(value);
+#else
+    uint32_t result;
+
+    __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    return (short)__builtin_bswap16(value);
+#else
+    int32_t result;
+
+    __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+    return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+    result = value;                      /* r will be reversed bits of v; first get LSB of v */
+    for (value >>= 1U; value; value >>= 1U) {
+        result <<= 1U;
+        result |= value & 1U;
+        s--;
+    }
+    result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+    return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+    return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+    return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+    __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+    ({                          \
+        int32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
+{
+    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
+{
+    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
+{
+    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
+{
+    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
+{
+    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
+{
+    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+    return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t* ptr)
+{
+    uint32_t result;
+
+    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+    ({                          \
+        int32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+#define __USAT16(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+    int32_t result;
+
+    __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+    int32_t result;
+
+    __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        if (ARG3 == 0) \
+            __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+        else \
+            __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+    int32_t result;
+
+    __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h
new file mode 100644
index 000000000..4e65d1d95
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h
@@ -0,0 +1,1813 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS ARMv8MBL Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+/*  CMSIS cmGrebe definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                        __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __ARMv8MBL_REV
+#define __ARMv8MBL_REV               0x0000U
+#warning "__ARMv8MBL_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT       0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT            0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+
+#ifndef __ETM_PRESENT
+#define __ETM_PRESENT             0U
+#warning "__ETM_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MTB_PRESENT
+#define __MTB_PRESENT             0U
+#warning "__MTB_PRESENT not defined in device header file; using default!"
+#endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[16U];
+    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[16U];
+    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[16U];
+    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[16U];
+    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[16U];
+    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+    uint32_t RESERVED5[16U];
+    __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+    uint32_t RESERVED0;
+#endif
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED1;
+    __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    uint32_t RESERVED0[6U];
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    uint32_t RESERVED3[1U];
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    uint32_t RESERVED5[1U];
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED6[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    uint32_t RESERVED7[1U];
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+    uint32_t RESERVED9[1U];
+    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+    uint32_t RESERVED10[1U];
+    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+    uint32_t RESERVED11[1U];
+    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+    uint32_t RESERVED12[1U];
+    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+    uint32_t RESERVED13[1U];
+    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+    uint32_t RESERVED14[1U];
+    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+    uint32_t RESERVED15[1U];
+    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+    uint32_t RESERVED16[1U];
+    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+    uint32_t RESERVED17[1U];
+    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+    uint32_t RESERVED18[1U];
+    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+    uint32_t RESERVED19[1U];
+    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+    uint32_t RESERVED20[1U];
+    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+    uint32_t RESERVED21[1U];
+    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+    uint32_t RESERVED22[1U];
+    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+    uint32_t RESERVED23[1U];
+    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+    uint32_t RESERVED24[1U];
+    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+    uint32_t RESERVED25[1U];
+    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+    uint32_t RESERVED26[1U];
+    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+    uint32_t RESERVED27[1U];
+    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+    uint32_t RESERVED28[1U];
+    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+    uint32_t RESERVED29[1U];
+    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+    uint32_t RESERVED30[1U];
+    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+    uint32_t RESERVED31[1U];
+    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+    uint32_t RESERVED0[7U];
+    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+#endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for ARMv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for ARMv8-M Baseline */
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                         /* Reload value impossible */
+    }
+
+    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                        SysTick_CTRL_TICKINT_Msk   |
+                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h
new file mode 100644
index 000000000..273c3849c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h
@@ -0,0 +1,2821 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS ARMv8MML Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     07. December 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+/*  CMSIS ARMv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                        __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __ARMv8MML_REV
+#define __ARMv8MML_REV               0x0000U
+#warning "__ARMv8MML_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT       0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DSP_PRESENT
+#define __DSP_PRESENT             0U
+#warning "__DSP_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0) */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
+        uint32_t FPCA: 1;                    /*!< bit:      2  Floating-point context active */
+        uint32_t SFPA: 1;                    /*!< bit:      3  Secure floating-point active */
+        uint32_t _reserved1: 28;             /*!< bit:  4..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[16U];
+    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[16U];
+    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[16U];
+    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[16U];
+    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[16U];
+    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+    uint32_t RESERVED5[16U];
+    __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED6[580U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+    __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+    uint32_t RESERVED3[92U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+    uint32_t RESERVED4[15U];
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+    uint32_t RESERVED5[1U];
+    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+    uint32_t RESERVED6[1U];
+    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+    uint32_t RESERVED7[6U];
+    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+    __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[1U];
+    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+    uint32_t RESERVED6[4U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    uint32_t RESERVED3[1U];
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    uint32_t RESERVED5[1U];
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED6[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    uint32_t RESERVED7[1U];
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+    uint32_t RESERVED9[1U];
+    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+    uint32_t RESERVED10[1U];
+    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+    uint32_t RESERVED11[1U];
+    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+    uint32_t RESERVED12[1U];
+    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+    uint32_t RESERVED13[1U];
+    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+    uint32_t RESERVED14[1U];
+    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+    uint32_t RESERVED15[1U];
+    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+    uint32_t RESERVED16[1U];
+    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+    uint32_t RESERVED17[1U];
+    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+    uint32_t RESERVED18[1U];
+    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+    uint32_t RESERVED19[1U];
+    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+    uint32_t RESERVED20[1U];
+    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+    uint32_t RESERVED21[1U];
+    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+    uint32_t RESERVED22[1U];
+    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+    uint32_t RESERVED23[1U];
+    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+    uint32_t RESERVED24[1U];
+    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+    uint32_t RESERVED25[1U];
+    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+    uint32_t RESERVED26[1U];
+    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+    uint32_t RESERVED27[1U];
+    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+    uint32_t RESERVED28[1U];
+    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+    uint32_t RESERVED29[1U];
+    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+    uint32_t RESERVED30[1U];
+    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+    uint32_t RESERVED31[1U];
+    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+    uint32_t RESERVED32[934U];
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+    uint32_t RESERVED33[1U];
+    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+    __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+    __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+    __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+    uint32_t RESERVED0[1];
+    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+    uint32_t RESERVED0[3];
+#endif
+    __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+    __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+#endif
+
+#define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+#define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+    return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    uint32_t mvfr0;
+
+    mvfr0 = FPU->MVFR0;
+    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+        return 2U;           /* Double + Single precision FPU */
+    }
+    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+        return 1U;           /* Single precision FPU */
+    }
+    else {
+        return 0U;           /* No FPU */
+    }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                         /* Reload value impossible */
+    }
+
+    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                        SysTick_CTRL_TICKINT_Msk   |
+                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h
new file mode 100644
index 000000000..d06d984b7
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h
@@ -0,0 +1,850 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM0_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0_REV
+#define __CM0_REV               0x0000U
+#warning "__CM0_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 1;              /*!< bit:      0  Reserved */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[31U];
+    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[31U];
+    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[31U];
+    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[31U];
+    uint32_t RESERVED4[64U];
+    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    uint32_t RESERVED0;
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED1;
+    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)0x0U;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)0x0U;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h
new file mode 100644
index 000000000..ebc43f3a1
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h
@@ -0,0 +1,975 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                      __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0PLUS_REV
+#define __CM0PLUS_REV             0x0000U
+#warning "__CM0PLUS_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT            0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[31U];
+    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[31U];
+    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[31U];
+    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[31U];
+    uint32_t RESERVED4[64U];
+    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+    uint32_t RESERVED0;
+#endif
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED1;
+    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0+ */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0+ */
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h
new file mode 100644
index 000000000..513635a58
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h
@@ -0,0 +1,1813 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+/*  CMSIS cmGrebe definitions */
+#define __CM23_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM23_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                     (23U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM23_REV
+#define __CM23_REV                0x0000U
+#warning "__CM23_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT       0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT            0U
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+
+#ifndef __ETM_PRESENT
+#define __ETM_PRESENT             0U
+#warning "__ETM_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MTB_PRESENT
+#define __MTB_PRESENT             0U
+#warning "__MTB_PRESENT not defined in device header file; using default!"
+#endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[16U];
+    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[16U];
+    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[16U];
+    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[16U];
+    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[16U];
+    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+    uint32_t RESERVED5[16U];
+    __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+    uint32_t RESERVED0;
+#endif
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED1;
+    __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    uint32_t RESERVED0[6U];
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    uint32_t RESERVED3[1U];
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    uint32_t RESERVED5[1U];
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED6[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    uint32_t RESERVED7[1U];
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+    uint32_t RESERVED9[1U];
+    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+    uint32_t RESERVED10[1U];
+    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+    uint32_t RESERVED11[1U];
+    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+    uint32_t RESERVED12[1U];
+    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+    uint32_t RESERVED13[1U];
+    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+    uint32_t RESERVED14[1U];
+    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+    uint32_t RESERVED15[1U];
+    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+    uint32_t RESERVED16[1U];
+    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+    uint32_t RESERVED17[1U];
+    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+    uint32_t RESERVED18[1U];
+    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+    uint32_t RESERVED19[1U];
+    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+    uint32_t RESERVED20[1U];
+    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+    uint32_t RESERVED21[1U];
+    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+    uint32_t RESERVED22[1U];
+    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+    uint32_t RESERVED23[1U];
+    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+    uint32_t RESERVED24[1U];
+    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+    uint32_t RESERVED25[1U];
+    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+    uint32_t RESERVED26[1U];
+    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+    uint32_t RESERVED27[1U];
+    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+    uint32_t RESERVED28[1U];
+    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+    uint32_t RESERVED29[1U];
+    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+    uint32_t RESERVED30[1U];
+    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+    uint32_t RESERVED31[1U];
+    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+    uint32_t RESERVED0[7U];
+    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+#endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+#else
+    uint32_t* vectors = (uint32_t*)0x0U;
+#endif
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                         /* Reload value impossible */
+    }
+
+    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                        SysTick_CTRL_TICKINT_Msk   |
+                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h
new file mode 100644
index 000000000..8cbf329b8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h
@@ -0,0 +1,1880 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM3_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM3_REV
+#define __CM3_REV               0x0200U
+#warning "__CM3_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
+        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
+        uint32_t _reserved1: 8;              /*!< bit: 16..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
+        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24U];
+    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24U];
+    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24U];
+    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24U];
+    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56U];
+    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    uint32_t RESERVED0[5U];
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+    uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[6U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h
new file mode 100644
index 000000000..00de7795e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h
@@ -0,0 +1,2821 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     07. December 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM33_CMSIS_VERSION_SUB           )     /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM33_REV
+#define __CM33_REV                0x0000U
+#warning "__CM33_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __SAUREGION_PRESENT
+#define __SAUREGION_PRESENT       0U
+#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DSP_PRESENT
+#define __DSP_PRESENT             0U
+#warning "__DSP_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0) */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
+        uint32_t FPCA: 1;                    /*!< bit:      2  Floating-point context active */
+        uint32_t SFPA: 1;                    /*!< bit:      3  Secure floating-point active */
+        uint32_t _reserved1: 28;             /*!< bit:  4..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[16U];
+    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[16U];
+    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[16U];
+    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[16U];
+    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[16U];
+    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+    uint32_t RESERVED5[16U];
+    __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED6[580U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+    __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+    uint32_t RESERVED3[92U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+    uint32_t RESERVED4[15U];
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+    uint32_t RESERVED5[1U];
+    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+    uint32_t RESERVED6[1U];
+    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+    uint32_t RESERVED7[6U];
+    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+    __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[1U];
+    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+    uint32_t RESERVED6[4U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    uint32_t RESERVED3[1U];
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    uint32_t RESERVED5[1U];
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED6[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    uint32_t RESERVED7[1U];
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+    uint32_t RESERVED9[1U];
+    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+    uint32_t RESERVED10[1U];
+    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+    uint32_t RESERVED11[1U];
+    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+    uint32_t RESERVED12[1U];
+    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+    uint32_t RESERVED13[1U];
+    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+    uint32_t RESERVED14[1U];
+    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+    uint32_t RESERVED15[1U];
+    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+    uint32_t RESERVED16[1U];
+    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+    uint32_t RESERVED17[1U];
+    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+    uint32_t RESERVED18[1U];
+    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+    uint32_t RESERVED19[1U];
+    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+    uint32_t RESERVED20[1U];
+    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+    uint32_t RESERVED21[1U];
+    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+    uint32_t RESERVED22[1U];
+    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+    uint32_t RESERVED23[1U];
+    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+    uint32_t RESERVED24[1U];
+    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+    uint32_t RESERVED25[1U];
+    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+    uint32_t RESERVED26[1U];
+    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+    uint32_t RESERVED27[1U];
+    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+    uint32_t RESERVED28[1U];
+    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+    uint32_t RESERVED29[1U];
+    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+    uint32_t RESERVED30[1U];
+    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+    uint32_t RESERVED31[1U];
+    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+    uint32_t RESERVED32[934U];
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+    uint32_t RESERVED33[1U];
+    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+    __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+    __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+    __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+    uint32_t RESERVED0[1];
+    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+    uint32_t RESERVED0[3];
+#endif
+    __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+    __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+    uint32_t RESERVED4[1U];
+    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+#define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+#endif
+
+#define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+#define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+    return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    uint32_t mvfr0;
+
+    mvfr0 = FPU->MVFR0;
+    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+        return 2U;           /* Double + Single precision FPU */
+    }
+    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+        return 1U;           /* Single precision FPU */
+    }
+    else {
+        return 0U;           /* No FPU */
+    }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                         /* Reload value impossible */
+    }
+
+    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                        SysTick_CTRL_TICKINT_Msk   |
+                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h
new file mode 100644
index 000000000..f4c8011f8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h
@@ -0,0 +1,2061 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     30. January 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM4_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM4_REV
+#define __CM4_REV               0x0000U
+#warning "__CM4_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
+        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
+        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24U];
+    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24U];
+    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24U];
+    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24U];
+    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56U];
+    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    uint32_t RESERVED0[5U];
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[6U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+#endif
+#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+#endif
+#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    uint32_t mvfr0;
+
+    mvfr0 = FPU->MVFR0;
+    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+        return 1U;           /* Single precision FPU */
+    }
+    else {
+        return 0U;           /* No FPU */
+    }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h
new file mode 100644
index 000000000..c09acc824
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h
@@ -0,0 +1,2592 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM7_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+#define __FPU_USED       1U
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0U
+#endif
+#else
+#define __FPU_USED         0U
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM7_REV
+#define __CM7_REV               0x0000U
+#warning "__CM7_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0U
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          0U
+#warning "__ICACHE_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          0U
+#warning "__DCACHE_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DTCM_PRESENT
+#define __DTCM_PRESENT            0U
+#warning "__DTCM_PRESENT        not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
+        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
+        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24U];
+    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24U];
+    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24U];
+    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24U];
+    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56U];
+    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+    uint32_t RESERVED3[93U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+    uint32_t RESERVED4[15U];
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
+    uint32_t RESERVED5[1U];
+    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+    uint32_t RESERVED6[1U];
+    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+    uint32_t RESERVED7[6U];
+    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+    uint32_t RESERVED8[1U];
+    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[6U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+    uint32_t RESERVED3[981U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+    __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    uint32_t mvfr0;
+
+    mvfr0 = SCB->MVFR0;
+    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
+        return 2U;           /* Double + Single precision FPU */
+    }
+    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
+        return 1U;           /* Single precision FPU */
+    }
+    else {
+        return 0U;           /* No FPU */
+    }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+        do {
+            SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                          ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+#if defined ( __CC_ARM )
+            __schedule_barrier();
+#endif
+        } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    register uint32_t ccsidr;
+    register uint32_t sets;
+    register uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+        do {
+            SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                           ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+#if defined ( __CC_ARM )
+            __schedule_barrier();
+#endif
+        } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+        do {
+            SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                          ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+#if defined ( __CC_ARM )
+            __schedule_barrier();
+#endif
+        } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+        do {
+            SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                          ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+#if defined ( __CC_ARM )
+            __schedule_barrier();
+#endif
+        } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+    /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+        do {
+            SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                           ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+#if defined ( __CC_ARM )
+            __schedule_barrier();
+#endif
+        } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+        SCB->DCIMVAC = op_addr;
+        op_addr += (uint32_t)linesize;
+        op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+        SCB->DCCMVAC = op_addr;
+        op_addr += (uint32_t)linesize;
+        op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+        SCB->DCCIMVAC = op_addr;
+        op_addr += (uint32_t)linesize;
+        op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h
new file mode 100644
index 000000000..ed1063364
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h
@@ -0,0 +1,976 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                     __SC000_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC000_REV
+#define __SC000_REV             0x0000U
+#warning "__SC000_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
+        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 1;              /*!< bit:      0  Reserved */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[31U];
+    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[31U];
+    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[31U];
+    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[31U];
+    uint32_t RESERVED4[64U];
+    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    uint32_t RESERVED1[154U];
+    __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+    else {
+        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h
new file mode 100644
index 000000000..a1b17e1ce
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h
@@ -0,0 +1,1851 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.1
+ * @date     25. November 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+#pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                     __SC300_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TI_ARM__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC300_REV
+#define __SC300_REV               0x0000U
+#warning "__SC300_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
+        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
+        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
+        uint32_t _reserved1: 8;              /*!< bit: 16..23  Reserved */
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
+        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
+        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
+    } b;                                   /*!< Structure used for bit  access */
+    uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+    uint32_t RESERVED0[24U];
+    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+    uint32_t RSERVED1[24U];
+    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+    uint32_t RESERVED2[24U];
+    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+    uint32_t RESERVED3[24U];
+    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+    uint32_t RESERVED4[56U];
+    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644U];
+    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+    uint32_t RESERVED0[5U];
+    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+    uint32_t RESERVED1[129U];
+    __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1U];
+    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+    uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __OM  union {
+        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+    uint32_t RESERVED0[864U];
+    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+    uint32_t RESERVED1[15U];
+    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+    uint32_t RESERVED2[15U];
+    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+    uint32_t RESERVED3[29U];
+    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+    uint32_t RESERVED4[43U];
+    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+    uint32_t RESERVED5[6U];
+    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+    uint32_t RESERVED0[1U];
+    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+    uint32_t RESERVED1[1U];
+    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+    uint32_t RESERVED2[1U];
+    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2U];
+    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55U];
+    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131U];
+    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759U];
+    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1U];
+    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39U];
+    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8U];
+    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifndef CMSIS_NVIC_VIRTUAL
+#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+#define NVIC_EnableIRQ              __NVIC_EnableIRQ
+#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+#define NVIC_DisableIRQ             __NVIC_DisableIRQ
+#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+#define NVIC_GetActive              __NVIC_GetActive
+#define NVIC_SetPriority            __NVIC_SetPriority
+#define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifndef CMSIS_VECTAB_VIRTUAL
+#define NVIC_SetVector              __NVIC_SetVector
+#define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+    reg_value  =  (reg_value                                   |
+                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+        __DSB();
+        __ISB();
+    }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+    }
+    else {
+        return(0U);
+    }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if ((int32_t)(IRQn) >= 0) {
+        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+    else {
+        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+    }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if ((int32_t)(IRQn) >= 0) {
+        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+    }
+    else {
+        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
+    }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    return (
+               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+           );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t* vectors = (uint32_t*)SCB->VTOR;
+    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+    __DSB();                                                          /* Ensure completion of memory access */
+
+    for(;;) {                                                         /* wait until reset */
+        __NOP();
+    }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+        return (1UL);                                                   /* Reload value impossible */
+    }
+
+    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+    return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0U].u32 == 0UL) {
+            __NOP();
+        }
+        ITM->PORT[0U].u8 = (uint8_t)ch;
+    }
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                              /* no character available */
+    }
+    else {
+        return (1);                              /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h
new file mode 100644
index 000000000..cd6d8ab07
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date:        21. September 2016
+ * $Revision:    V1.0
+ *
+ * Project:      TrustZone for ARMv8-M
+ * Title:        Context Management for ARMv8-M TrustZone
+ *
+ * Version 1.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include <stdint.h>
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif  // TZ_CONTEXT_H
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h
new file mode 100644
index 000000000..c77078936
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h
@@ -0,0 +1,33 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file:   dtype.h
+/// @author  AE TEAM
+/// @brief   Define the data types to be used in the project, including the function
+///          library and application code. Use the data types defined in this file.
+////////////////////////////////////////////////////////////////////////////////
+#ifndef __DTYPE_H
+#define __DTYPE_H     //This is done to avoid including the header file repeatedly in the same file
+
+
+//Defines the read and write characteristics of data, which is often used for storage limits of peripheral registers
+#ifndef __I
+#define     __I     volatile const    //only read
+#endif
+#ifndef __O
+#define     __O     volatile          //only write
+#endif
+#ifndef __IO
+#define     __IO    volatile          //read write
+#endif
+
+//Common data type definitions
+
+typedef unsigned char  int8u;         //haven't symbol8 bit integer variable
+typedef signed   char  int8s;         //have symbol8 bit integer variable
+typedef unsigned short int16u;        //haven't symbol16 bit integer variable
+typedef signed   short int16s;        //have symbol16 bit integer variable
+typedef unsigned int   int32u;        //haven't symbol32 bit integer variable
+typedef signed   int   int32s;        //have symbol32 bit integer variable
+typedef float          fp32;          //Single-precision floating-point number (32-bit length)
+typedef double         fp64;          //Double-precision floating-point number (64-bit length)
+
+#endif  //__DTYPE_H
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h
new file mode 100644
index 000000000..dc0aa3d67
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h
@@ -0,0 +1,341 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_adc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE ADC
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_ADC_H
+#define __HAL_ADC_H
+
+// Files includes
+#include "types.h"
+#include "reg_adc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ADC_HAL
+/// @brief ADC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ADC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Channels
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_Channel_0                       = 0x00,                   ///< ADC Channel 0
+    ADC_Channel_1                       = 0x01,                   ///< ADC Channel 1
+    ADC_Channel_2                       = 0x02,                   ///< ADC Channel 2
+    ADC_Channel_3                       = 0x03,                   ///< ADC Channel 3
+    ADC_Channel_4                       = 0x04,                   ///< ADC Channel 4
+    ADC_Channel_5                       = 0x05,                   ///< ADC Channel 5
+    ADC_Channel_6                       = 0x06,                   ///< ADC Channel 6
+    ADC_Channel_7                       = 0x07,                   ///< ADC Channel 7
+
+    ADC_Channel_8               = 0x08,     ///< ADC Channel 8
+    ADC_Channel_9               = 0x09,     ///< ADC Channel 9
+    ADC_Channel_10              = 0x0A,     ///< ADC Channel 10
+    ADC_Channel_11              = 0x0B,     ///< ADC Channel 11
+    ADC_Channel_12              = 0x0C,     ///< ADC Channel 12
+    ADC_Channel_13              = 0x0D,     ///< ADC Channel 13
+    ADC_Channel_14              = 0x0E,     ///< ADC Channel 14
+    ADC_Channel_15              = 0x0F,     ///< ADC Channel 15
+    ADC_Channel_TempSensor      = 0x0E,     ///< Temperature sensor channel(ADC1)
+    ADC_Channel_VoltReference   = 0x0F,     ///< Internal reference voltage channel(ADC1)
+    ADC_Channel_Vrefint         = 0x0F,     ///< Internal reference voltage channel(ADC1)
+
+} ADCCHANNEL_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Sampling_Times
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_Samctl_1_5   = ADC_SMPR1_SAMCTL0_2_5,   ///< ADC sample time select 1.5t
+    ADC_Samctl_2_5   = ADC_SMPR1_SAMCTL0_2_5,   ///< ADC sample time select 2.5t
+    ADC_Samctl_3_5   = ADC_SMPR1_SAMCTL0_3_5,   ///< ADC sample time select 3.5t
+    ADC_Samctl_4_5   = ADC_SMPR1_SAMCTL0_4_5,   ///< ADC sample time select 4.5t
+    ADC_Samctl_5_5   = ADC_SMPR1_SAMCTL0_5_5,   ///< ADC sample time select 5.5t
+    ADC_Samctl_6_5   = ADC_SMPR1_SAMCTL0_6_5,   ///< ADC sample time select 6.5t
+    ADC_Samctl_7_5   = ADC_SMPR1_SAMCTL0_7_5,   ///< ADC sample time select 7.5t
+    ADC_Samctl_8_5   = ADC_SMPR1_SAMCTL0_8_5,   ///< ADC sample time select 7.5t
+    ADC_Samctl_13_5  = ADC_SMPR1_SAMCTL0_14_5,  ///< ADC sample time select 13.5t
+    ADC_Samctl_14_5  = ADC_SMPR1_SAMCTL0_14_5,  ///< ADC sample time select 14.5t
+    ADC_Samctl_28_5  = ADC_SMPR1_SAMCTL0_29_5,  ///< ADC sample time select 28.5t
+    ADC_Samctl_29_5  = ADC_SMPR1_SAMCTL0_29_5,  ///< ADC sample time select 29.5t
+    ADC_Samctl_41_5  = ADC_SMPR1_SAMCTL0_42_5,  ///< ADC sample time select 41.5t
+    ADC_Samctl_42_5  = ADC_SMPR1_SAMCTL0_42_5,  ///< ADC sample time select 42.5t
+    ADC_Samctl_55_5  = ADC_SMPR1_SAMCTL0_56_5,  ///< ADC sample time select 55.5t
+    ADC_Samctl_56_5  = ADC_SMPR1_SAMCTL0_56_5,  ///< ADC sample time select 56.5t
+    ADC_Samctl_71_5  = ADC_SMPR1_SAMCTL0_72_5,  ///< ADC sample time select 71.5t
+    ADC_Samctl_72_5  = ADC_SMPR1_SAMCTL0_72_5,  ///< ADC sample time select 72.5t
+    ADC_Samctl_239_5 = ADC_SMPR1_SAMCTL0_240_5, ///< ADC sample time select 239.5t
+    ADC_Samctl_240_5 = ADC_SMPR1_SAMCTL0_240_5  ///< ADC sample time select 240.5t
+} ADCSAM_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Resolution
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_Resolution_12b = ADC_CFGR_RSLTCTL_12,  ///< ADC resolution select 12bit
+    ADC_Resolution_11b = ADC_CFGR_RSLTCTL_11,  ///< ADC resolution select 11bit
+    ADC_Resolution_10b = ADC_CFGR_RSLTCTL_10,  ///< ADC resolution select 10bit
+    ADC_Resolution_9b  = ADC_CFGR_RSLTCTL_9,   ///< ADC resolution select 9bit
+    ADC_Resolution_8b  = ADC_CFGR_RSLTCTL_8    ///< ADC resolution select 8bit
+} ADCRSL_TypeDef;
+/// @brief ADC_Prescare
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_PCLK2_PRESCARE_3  = ADC_CFGR_PRE_3,   ///< ADC preclk 3
+    ADC_PCLK2_PRESCARE_5  = ADC_CFGR_PRE_5,   ///< ADC preclk 5
+    ADC_PCLK2_PRESCARE_7  = ADC_CFGR_PRE_7,   ///< ADC preclk 7
+    ADC_PCLK2_PRESCARE_9  = ADC_CFGR_PRE_9,   ///< ADC preclk 9
+    ADC_PCLK2_PRESCARE_11 = ADC_CFGR_PRE_11,  ///< ADC preclk 11
+    ADC_PCLK2_PRESCARE_13 = ADC_CFGR_PRE_13,  ///< ADC preclk 13
+    ADC_PCLK2_PRESCARE_15 = ADC_CFGR_PRE_15,  ///< ADC preclk 15
+    ADC_PCLK2_PRESCARE_17 = ADC_CFGR_PRE_17,  ///< ADC preclk 17
+
+    ADC_PCLK2_PRESCARE_2  = ADC_CFGR_PRE_2,   ///< ADC preclk 2
+    ADC_PCLK2_PRESCARE_4  = ADC_CFGR_PRE_4,   ///< ADC preclk 4
+    ADC_PCLK2_PRESCARE_6  = ADC_CFGR_PRE_6,   ///< ADC preclk 6
+    ADC_PCLK2_PRESCARE_8  = ADC_CFGR_PRE_8,   ///< ADC preclk 8
+    ADC_PCLK2_PRESCARE_10 = ADC_CFGR_PRE_10,  ///< ADC preclk 10
+    ADC_PCLK2_PRESCARE_12 = ADC_CFGR_PRE_12,  ///< ADC preclk 12
+    ADC_PCLK2_PRESCARE_14 = ADC_CFGR_PRE_14,  ///< ADC preclk 14
+    ADC_PCLK2_PRESCARE_16 = ADC_CFGR_PRE_16   ///< ADC preclk 16
+} ADCPRE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Conversion_Mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_Mode_Imm        = ADC_CR_IMM,       ///< ADC single convert mode
+    ADC_Mode_Scan       = ADC_CR_SCAN,      ///< ADC single period convert mode
+    ADC_Mode_Continue   = ADC_CR_CONTINUE   ///< ADC continue scan convert mode
+} ADCMODE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC1_ExternalTrigConv_T1_CC1        = ADC_CR_T1_CC1,
+    ADC1_ExternalTrigConv_T1_CC2        = ADC_CR_T1_CC2,
+    ADC1_ExternalTrigConv_T1_CC3        = ADC_CR_T1_CC3,
+    ADC1_ExternalTrigConv_T2_CC2        = ADC_CR_T2_CC2,
+    ADC1_ExternalTrigConv_T3_TRIG       = ADC_CR_T3_TRIG,
+    ADC1_ExternalTrigConv_T3_CC1        = ADC_CR_T3_CC1,
+    ADC1_ExternalTrigConv_EXTI_11       = ADC_CR_EXTI_11,
+    ADC1_ExternalTrigConv_T1_CC4_CC5    = ADC_CR_T1_CC4_CC5,
+    ADC1_ExternalTrigConv_T1_TRIG       = ADC_CR_T1_TRIG,
+    ADC1_ExternalTrigConv_T8_CC4        = ADC_CR_T8_CC4,
+    ADC1_ExternalTrigConv_T8_CC4_CC5    = ADC_CR_T8_CC4_CC5,
+    ADC1_ExternalTrigConv_T2_CC1        = ADC_CR_T2_CC1,
+    ADC1_ExternalTrigConv_T3_CC4        = ADC_CR_T3_CC4,
+    ADC1_ExternalTrigConv_T2_TRIG       = ADC_CR_T2_TRIG,
+    ADC1_ExternalTrigConv_T8_CC5        = ADC_CR_T8_CC5,
+    ADC1_ExternalTrigConv_EXTI_15       = ADC_CR_EXTI_15,
+    ADC1_ExternalTrigConv_T1_CC4        = ADC_CR_TIM1_CC4,
+    ADC1_ExternalTrigConv_T1_CC5        = ADC_CR_TIM1_CC5
+} EXTERTRIG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Data_Align
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_DataAlign_Right = ADC_CR_RIGHT,     ///< ADC data left align
+    ADC_DataAlign_Left  = ADC_CR_LEFT       ///< ADC data right align
+} ADCDATAALI_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Flags_Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_IT_EOC = 1,                            ///< ADC conversion flag
+    ADC_FLAG_EOC = 1,
+    ADC_IT_AWD = 2,                            ///< ADC window comparator flag
+    ADC_FLAG_AWD = 2
+} ADCFLAG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Trig_Edge
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_ADC_Trig_Edge_Dual              = ADC_CR_TRG_EDGE_DUAL,                 ///< ADC trig edge dual mode down and up
+    ADC_ADC_Trig_Edge_Down              = ADC_CR_TRG_EDGE_DOWN,                 ///< ADC trig edge single mode down
+    ADC_ADC_Trig_Edge_Up                = ADC_CR_TRG_EDGE_UP,                   ///< ADC trig edge single mode up
+    ADC_ADC_Trig_Edge_Mask              = ADC_CR_TRG_EDGE_MASK                  ///< ADC trig edge is mask, not allowed
+} ADCTRIGEDGE_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Scan_Direct
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_Scan_Direct_Up                  = ADC_CR_SCANDIR,                       ///< ADC scan from low channel to high channel
+    ADC_Scan_Direct_Down                = 0                                     ///< ADC scan from High channel to low channel
+} ADCSCANDIRECT_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Trig_Shift
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_ADC_Trig_Shift_0                = ADC_CR_TRGSHIFT_0,                    ///< ADC trig shift bit is 0
+    ADC_ADC_Trig_Shift_4                = ADC_CR_TRGSHIFT_4,                    ///< ADC trig shift bit is 4
+    ADC_ADC_Trig_Shift_16               = ADC_CR_TRGSHIFT_16,                   ///< ADC trig shift bit is 16
+    ADC_ADC_Trig_Shift_32               = ADC_CR_TRGSHIFT_32,                   ///< ADC trig shift bit is 32
+    ADC_ADC_Trig_Shift_64               = ADC_CR_TRGSHIFT_64,                   ///< ADC trig shift bit is 64
+    ADC_ADC_Trig_Shift_128              = ADC_CR_TRGSHIFT_128,                  ///< ADC trig shift bit is 128
+    ADC_ADC_Trig_Shift_256              = ADC_CR_TRGSHIFT_256,                  ///< ADC trig shift bit is 256
+    ADC_ADC_Trig_Shift_512              = ADC_CR_TRGSHIFT_512,                  ///< ADC trig shift bit is 512
+} ADCTRIGSHIFT_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_Inject_Seqen_Len1               = 0,                                    ///< ADC Injected Seqence length is 1
+    ADC_Inject_Seqen_Len2               = 1,                                    ///< ADC Injected Seqence length is 2
+    ADC_Inject_Seqen_Len3               = 2,                                    ///< ADC Injected Seqence length is 3
+    ADC_Inject_Seqen_Len4               = 3,                                    ///< ADC Injected Seqence length is 4
+} ADC_INJ_SEQ_LEN_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC_InjectedChannel_1 = 0x00,
+    ADC_InjectedChannel_2 = 0x04,
+    ADC_InjectedChannel_3 = 0x08,
+    ADC_InjectedChannel_4 = 0x0c,
+} ADC_INJ_SEQ_Channel_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    ADC1_InjectExtTrigSrc_T1_TRGO       = ADC_ANY_CR_JTRGSEL_TIM1_TRGO,         ///< TIM1 TRGO
+    ADC1_InjectExtTrigSrc_T1_CC4        = ADC_ANY_CR_JTRGSEL_TIM1_CC4,          ///< TIM1 CC4
+    ADC1_InjectExtTrigSrc_T1_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5,      ///< TIM1 CC4 and CC5
+    ADC1_InjectExtTrigSrc_T2_CC1        = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1,      ///< TIM2 CC1
+    ADC1_InjectExtTrigSrc_T3_CC4        = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4,      ///< TIM3 CC4
+    ADC1_InjectExtTrigSrc_T8_CC4        = ADC_ANY_CR_JTRGSEL_TIM8_CC4,          ///< TIM8 CC4
+    ADC1_InjectExtTrigSrc_T8_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5,      ///< TIM8 CC4 and CC5
+    ADC1_InjectExtTrigSrc_EXTI_12       = ADC_ANY_CR_JTRGSEL_EXTI12,            ///< EXTI12
+
+    ADC2_InjectExtTrigSrc_T1_TRGO       = ADC_ANY_CR_JTRGSEL_TIM1_TRGO,         ///< TIM1 TRGO
+    ADC2_InjectExtTrigSrc_T1_CC4        = ADC_ANY_CR_JTRGSEL_TIM1_CC4,          ///< TIM1 CC4
+    ADC2_InjectExtTrigSrc_T1_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5,      ///< TIM1 CC4 and CC5
+    ADC2_InjectExtTrigSrc_T2_CC1        = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1,      ///< TIM2 CC1
+    ADC2_InjectExtTrigSrc_T3_CC4        = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4,      ///< TIM3 CC4
+    ADC2_InjectExtTrigSrc_T8_CC4        = ADC_ANY_CR_JTRGSEL_TIM8_CC4,          ///< TIM8 CC4
+    ADC2_InjectExtTrigSrc_T8_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5,      ///< TIM8 CC4 and CC5
+
+    ADC2_InjectExtTrigSrc_EXTI_12       = ADC_ANY_CR_JTRGSEL_EXTI12,            ///< EXTI12
+    ADC3_InjectExtTrigSrc_T1_TRGO       = ADC_ANY_CR_JTRGSEL_TIM1_TRGO,         ///< TIM1 TRGO
+    ADC3_InjectExtTrigSrc_T1_CC4        = ADC_ANY_CR_JTRGSEL_TIM1_CC4,          ///< TIM1 CC4
+    ADC3_InjectExtTrigSrc_T1_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5,      ///< TIM1 CC4 and CC5
+    ADC3_InjectExtTrigSrc_T4_CC1        = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1,      ///< TIM4 CC1
+    ADC3_InjectExtTrigSrc_T5_CC4        = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4,      ///< TIM5 CC4
+    ADC3_InjectExtTrigSrc_T8_CC4        = ADC_ANY_CR_JTRGSEL_TIM8_CC4,          ///< TIM8 CC4
+    ADC3_InjectExtTrigSrc_T8_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5,      ///< TIM8 CC4 and CC5
+    ADC3_InjectExtTrigSrc_EXTI_12       = ADC_ANY_CR_JTRGSEL_EXTI12,            ///< EXTI12
+} EXTER_INJ_TRIG_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC Init Structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u32                                 ADC_Resolution;                         ///< Convert data resolution
+    u32                                 ADC_PRESCARE;                           ///< Clock prescaler
+    u32                                 ADC_Mode;                               ///< ADC conversion mode
+    FunctionalState                     ADC_ContinuousConvMode;                 ///< Useless just for compatibility
+    u32                                 ADC_ExternalTrigConv;                   ///< External trigger source selection
+    u32                                 ADC_DataAlign;                          ///< Data alignmentn
+} ADC_InitTypeDef;
+
+/// @}
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ADC_Exported_Variables
+/// @{
+#ifdef _HAL_ADC_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ADC_Exported_Functions
+/// @{
+void ADC_DeInit(ADC_TypeDef* adc);
+void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct);
+void ADC_StructInit(ADC_InitTypeDef* init_struct);
+void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time);//ADCSAM_TypeDef
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source);
+#define ADC_ExternalTrigInjectedConvConfig ADC_ExternalTrigConvConfig
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel);
+void ADC_TempSensorVrefintCmd(FunctionalState state);
+void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt);
+void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag);
+
+u16 ADC_GetConversionValue(ADC_TypeDef* adc);
+
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag);
+ITStatus   ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt);
+void ADC_TempSensorCmd(FunctionalState state);
+void ADC_VrefintCmd(FunctionalState state);
+void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state);
+void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel);
+void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num);
+void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource);
+void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
+void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length);
+void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel);
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr);
+u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc);
+void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value);
+u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel);
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h
new file mode 100644
index 000000000..26a93d4a0
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h
@@ -0,0 +1,130 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_bkp.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE BKP
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_BKP_H
+#define __HAL_BKP_H
+
+// Files includes
+#include "types.h"
+#include "reg_bkp.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup BKP_HAL
+/// @brief BKP HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup BKP_Exported_Types
+/// @{
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Data_Backup_Register
+/// @anchor Data_Backup_Register
+
+typedef enum {
+    BKP_DR1  = 0x0010,
+    BKP_DR2  = 0x0014,
+    BKP_DR3  = 0x0018,
+    BKP_DR4  = 0x001C,
+    BKP_DR5  = 0x0020,
+    BKP_DR6  = 0x0024,
+    BKP_DR7  = 0x0028,
+    BKP_DR8  = 0x002C,
+    BKP_DR9  = 0x0030,
+    BKP_DR10 = 0x0034,
+    BKP_DR11 = 0x0038,
+    BKP_DR12 = 0x003C,
+    BKP_DR13 = 0x0040,
+    BKP_DR14 = 0x0044,
+    BKP_DR15 = 0x0048,
+    BKP_DR16 = 0x004C,
+    BKP_DR17 = 0x0050,
+    BKP_DR18 = 0x0054,
+    BKP_DR19 = 0x0058,
+    BKP_DR20 = 0x005C
+} BKPDR_Typedef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Tamper_Pin_active_level
+/// @anchor Tamper_Pin_active_level
+typedef enum {
+    BKP_TamperPinLevel_High,                                                    ///< Tamper pin active on high level
+    BKP_TamperPinLevel_Low = BKP_CR_TPAL,                                       ///< Tamper pin active on low level
+} BKPTPAL_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_output_source_to_output_on_the_Tamper_pin
+/// @anchor RTC_output_source_to_output_on_the_Tamper_pin
+typedef enum {
+    BKP_RTCOutputSource_None       = 0x0000,                                    ///< No RTC output on the Tamper pin
+    BKP_RTCOutputSource_CalibClock = 0x0080,                                    ///< Output the RTC clock with frequency divided by 64 on the Tamper pin
+    BKP_RTCOutputSource_Alarm      = 0x0100,                                    ///< Output the RTC Alarm pulse signal on the Tamper pin
+    BKP_RTCOutputSource_Second     = 0x0300                                     ///< Output the RTC Second pulse signal on the Tamper pin
+} BKPRTCOUTPUTSRC_Typedef;
+
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup BKP_Exported_Variables
+/// @{
+#ifdef _HAL_BKP_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup BKP_Exported_Functions
+/// @{
+
+void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data);
+u16  BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr);
+
+void BKP_DeInit(void);
+void BKP_ClearFlag(void);
+void BKP_ClearITPendingBit(void);
+void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level);
+void BKP_TamperPinCmd(FunctionalState state);
+void BKP_ITConfig(FunctionalState state);
+void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source);
+void BKP_SetRTCCalibrationValue(u8 calibration_value);
+
+ITStatus   BKP_GetITStatus(void);
+FlagStatus BKP_GetFlagStatus(void);
+void exBKP_Init(void);
+void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 data);
+u16  exBKP_ImmRead(BKPDR_Typedef bkp_dr);
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_BKP_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h
new file mode 100644
index 000000000..b7e1d4b42
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h
@@ -0,0 +1,340 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_can.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CAN
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_CAN_H
+#define __HAL_CAN_H
+
+// Files includes
+#include "types.h"
+#include "reg_can.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CAN_HAL
+/// @brief CAN HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CAN_Exported_Types
+/// @{
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Initialization
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    CANINITFAILED = 0x00000000,  ///< CAN initialization failed
+    CANINITOK     = 0x00000001   ///< CAN initialization ok
+} emCAN_INIT_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_sleep_constants
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    CANSLEEPFAILED = 0x00000000,  ///< CAN did not enter the sleep mode
+    CANSLEEPOK     = 0x00000001   ///< CAN entered the sleep mode
+} emCAN_SLEEP_conts_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_wake_up_constants
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    CANWAKEUPFAILED = 0x00000000,  ///< CAN did not leave the sleep mode
+    CANWAKEUPOK     = 0x00000001   ///< CAN leaved the sleep mode
+} emCAN_WAKE_conts_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    CAN_BASICMode         = 0x00000000,
+    CAN_PELIMode          = 0x00000080,
+    CAN_WorkMode          = 0x00000080,
+    CAN_ResetMode         = 0x00000001,
+    CAN_ListenOnlyMode    = 0x00000002,
+    CAN_SeftTestMode      = 0x00000004,
+    CAN_FilterMode_Singal = 0x00000008,
+    CAN_FilterMode_Double = 0x000000f7,
+    CAN_SleepMode         = 0x00000010
+} emCAN_CAN_Mode_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BASIC_CAN_interrupt
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    CAN_IT_RIE = CAN_CR_RIE,                                                    ///< Overflow interrupt enable
+    CAN_IT_TIE = CAN_CR_TIE,                                                    ///< Transmit interrupt enable
+    CAN_IT_EIE = CAN_CR_EIE,                                                    ///< Error interrupt enable
+    CAN_IT_OIE = CAN_CR_OIE                                                     ///< Receive interrupt enable
+} emCAN_BASIC_IntEn_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PELI_CAN_interrupt
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    CAN_IT_RI  = CAN_IR_RI,                                                     ///< Overflow interrupt enable
+    CAN_IT_TI  = CAN_IR_TI,                                                     ///< Transmit interrupt enable
+    CAN_IT_EI  = CAN_IR_EI,                                                     ///< Error interrupt enable
+    CAN_IT_DOI = CAN_IR_DOI,                                                    ///< Receive interrupt enable
+    CAN_IT_WUI = 0x00001010,                                                    ///< Receive interrupt enable
+    CAN_IT_EPI = CAN_IR_EPI,                                                    ///< Receive interrupt enable
+    CAN_IT_ALI = CAN_IR_ALI,                                                    ///< Receive interrupt enable
+    CAN_IT_BEI = CAN_IR_BEI,                                                    ///< Receive interrupt enable
+    CAN_IT_ALL = 0xFFFF                                                         ///< Receive interrupt enable
+
+} emCAN_PELI_IntEn_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Status
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    CAN_STATUS_RBS = CAN_SR_RBS,
+    CAN_STATUS_DOS = CAN_SR_DOS,
+    CAN_STATUS_TBS = CAN_SR_TBS,
+    CAN_STATUS_TCS = CAN_SR_TCS,
+    CAN_STATUS_RS  = CAN_SR_RS,
+    CAN_STATUS_TS  = CAN_SR_TS,
+    CAN_STATUS_ES  = CAN_SR_ES,
+    CAN_STATUS_BS  = CAN_SR_BS
+} emCAN_Status_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_Command_register
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    CAN_TR  = CAN_CMR_TR,  ///< Transmission request
+    CAN_AT  = CAN_CMR_AT,
+    CAN_RRB = CAN_CMR_RRB,
+    CAN_CDO = CAN_CMR_CDO
+} emCAN_Command_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  CAN_Peli transmit frame definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DataFrame   = 0,  ///< Data Frame
+    RemoteFrame = !DataFrame
+} TransFrame;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  CAN_Basic init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u8              SJW;
+    u8              BRP;
+    FlagStatus      SAM;
+    u8              TESG2;
+    u8              TESG1;
+    FunctionalState GTS;
+    u8              CDCLK;
+    u8              CLOSE_OPEN_CLK;
+    u8              RXINTEN;
+    u8              CBP;
+} CAN_Basic_InitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  CAN_Peli init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u8              SJW;
+    u8              BRP;
+    FlagStatus      SAM;
+    u8              TESG2;
+    u8              TESG1;
+    FunctionalState LOM;
+    FunctionalState STM;
+    FunctionalState SM;
+    FunctionalState SRR;
+    u32             EWLR;
+} CAN_Peli_InitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  CAN_Basic filter init structure definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+    u8 CAN_FilterId;      ///< Specifies the filter identification number. This parameter can be a value between 0x00 and 0xFF.
+    u8 CAN_FilterMaskId;  ///< Specifies the filter mask number or identification number, This parameter can be a value between
+    ///< 0x00 and 0xFF.
+} CAN_Basic_FilterInitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  CAN_Peli filter init structure definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+    u8 AFM;
+    u8 CAN_FilterId0;  ///< Specifies the filter identification number, This parameter can be a value between 0x00 and 0xFF
+    u8 CAN_FilterId1;
+    u8 CAN_FilterId2;
+    u8 CAN_FilterId3;
+    u8 CAN_FilterMaskId0;  ///< Specifies the filter mask number or identification number, This parameter can be a value between
+    ///< 0x00 and 0xFF
+    u8 CAN_FilterMaskId1;
+    u8 CAN_FilterMaskId2;
+    u8 CAN_FilterMaskId3;
+} CAN_Peli_FilterInitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  CAN_Basic Tx message structure definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+    u8 IDH;      ///< Specifies the standard high identifier. This parameter can be a value between 0 to 0xFF.
+    u8 IDL;      ///< Specifies the standard low identifier. This parameter can be a value between 0 to 0x7.
+    u8 RTR;      ///< Specifies the type of frame for the message that will be transmitted. This parameter can be @TransFrame.
+    u8 DLC;      ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8.
+    u8 Data[8];  ///< Contains the data to be transmitted. It ranges from 0 to 0xFF.
+} CanBasicTxMsg;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  CAN_Basic Rx message structure definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+    u16 ID;       ///< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF.
+    u8  RTR;      ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame
+    u8  DLC;      ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8
+    u8  Data[8];  ///< Contains the data to be received. It ranges from 0 to  0xFF.
+} CanBasicRxMsg;
+
+///////////////////////////////////////////////////////////////////////////////
+/// @brief  CAN_Peli_Tx message structure definition
+///////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+    u8 IDLL;  ///< Specifies the extended identifier.
+    ///< This parameter can be a value between 0 to 0xFF.
+    u8 IDLH;
+    u8 IDHL;
+    u8 IDHH;
+    u8 FF;   ///< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref
+    ///< CAN_identifier_type
+    u8 RTR;  ///< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref
+    ///< TransFrame.
+    u8 DLC;  ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8.
+    u8 Data[8];  ///< Contains the data to be transmitted. It ranges from 0 to 0xFF.
+} CanPeliTxMsg;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  CAN Rx message structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u32 ID;  ///< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF.
+    u8  FF;  ///< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref
+    ///< CAN_identifier_type.
+    u8 RTR;  ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame.
+    u8 DLC;  ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8.
+    u8 Data[8];  ///< Contains the data to be received. It ranges from 0 to0xFF.
+} CanPeliRxMsg;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup  CAN_Exported_Constants
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup  parasmeter_of_CAN_transmission_register
+/// @{
+#define CANTXFAILED (0x00U)   ///< CAN transmission failed
+#define CANTXOK (0x01U)       ///< CAN transmission succeeded
+#define CANTXPENDING (0x02U)  ///< CAN transmission pending
+#define CAN_NO_MB (0x04U)     ///< CAN cell did not provide an empty mailbox
+/// @}
+
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CAN_Exported_Variables
+/// @{
+#ifdef _HAL_CAN_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CAN_Exported_Functions
+/// @{
+
+// Basic and Peli Work all need function ---------------------------------------
+
+void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode);
+void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state);
+void CAN_ClearDataOverflow(CAN_TypeDef* can);
+void CAN_ClearITPendingBit(CAN_TypeDef* can);
+
+// Basic Work function ---------------------------------------------------------
+void CAN_DeInit(CAN_TypeDef* can);
+void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct);
+void CAN_StructInit(CAN_Basic_InitTypeDef* basic_init_struct);
+void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state);
+void CAN_CancelTransmit(CAN_TypeDef* can);
+void CAN_FIFORelease(CAN_TypeDef* can);
+void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message);
+
+u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message);
+u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* basic_init_struct);
+u8 CAN_Sleep(CAN_TypeDef* can);
+u8 CAN_WakeUp(CAN_TypeDef* can);
+
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag);
+ITStatus   CAN_GetITStatus(CAN_TypeDef* can, u32 it);
+
+// Peli Work function ----------------------------------------------------------
+void CAN_Peli_SleepMode_Cmd(FunctionalState state);
+void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct);
+void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* peli_init_struct);
+void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct);
+void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct);
+void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message);
+void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message);
+void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message);
+void CAN_Peli_ITConfig(u32 it, FunctionalState state);
+void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud);
+
+u32 CAN_Peli_GetRxFIFOInfo(void);
+u8  CAN_Peli_GetLastErrorCode(void);
+u8  CAN_Peli_GetReceiveErrorCounter(void);
+u8  CAN_Peli_GetLSBTransmitErrorCounter(void);
+
+ITStatus CAN_Peli_GetITStatus(u32 it);
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h
new file mode 100644
index 000000000..617318d53
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h
@@ -0,0 +1,228 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_comp.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE COMP
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_COMP_H
+#define __HAL_COMP_H
+
+
+// Files includes
+#include "reg_common.h"
+#include "reg_comp.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup COMP_HAL
+/// @brief COMP HAL modules
+/// @{
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup COMP_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_InvertingInput
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    COMP_InvertingInput_IO0           = COMP_CSR_INM_0,                       ///< INM0 as COMP inverting input
+    COMP_InvertingInput_IO1           = COMP_CSR_INM_1,                       ///< INM1 as COMP inverting input
+    COMP_InvertingInput_IO2           = COMP_CSR_INM_2,                       ///< INM2 as COMP inverting input
+    COMP_InvertingInput_CRV           = COMP_CSR_INM_3,                       ///< INM3 as COMP inverting input
+    COMP_InvertingInput_IO3           = COMP_CSR_INM_3,                       ///< INM3 as COMP inverting input
+} EM_COMP_InvertingInput;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_NonInvertingInput
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    COMP_NonInvertingInput_IO0        = COMP_CSR_INP_INP0,                    ///< INP0 as COMP non-inverting input
+    COMP_NonInvertingInput_IO1        = COMP_CSR_INP_INP1,                    ///< INP1 as COMP non-inverting input
+    COMP_NonInvertingInput_IO2        = COMP_CSR_INP_INP2,                    ///< INP2 as COMP non-inverting input
+    COMP_NonInvertingInput_IO3        = COMP_CSR_INP_INP3,                    ///< INP3 as COMP non-inverting input
+} EM_COMP_NonInvertingInput;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_Output
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    COMP_Output_None                  = 0x00000000,                             ///< No output
+    COMP_Output_TIM1BKIN              = COMP_CSR_OUT_TIM1_BRAKE,                ///< Timer1 brake input
+    COMP_Output_TIM1OCREFCLR          = COMP_CSR_OUT_TIM1_OCREFCLR,             ///< Timer1 ocrefclear input
+    COMP_Output_TIM1IC1               = COMP_CSR_OUT_TIM1_CAPTURE1,             ///< Timer1 input capture 1
+    COMP_Output_TIM2IC4               = COMP_CSR_OUT_TIM2_CAPTURE4,             ///< Timer2 input capture 4
+    COMP_Output_TIM2OCREFCLR          = COMP_CSR_OUT_TIM2_OCREFCLR,             ///< Timer2 ocrefclear input
+    COMP_Output_TIM3IC1               = COMP_CSR_OUT_TIM3_CAPTURE1,             ///< Timer3 input capture 1
+    COMP_Output_TIM3OCREFCLR          = COMP_CSR_OUT_TIM3_OCREFCLR              ///< Timer3 ocrefclear input
+} EM_COMP_Output;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_OutputPoloarity
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    COMP_NonInverted                  = 0x00000000,                             ///< COMP non-inverting output
+    COMP_OutputPol_NonInverted        = 0x00000000,
+    COMP_Inverted                     = 0x00008000,                             ///< COMP inverting output
+    COMP_OutputPol_Inverted           = 0x00008000
+} EM_COMP_OutputPol;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_Hysteresis
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    COMP_Hysteresis_No                = COMP_CSR_HYST_0,                      ///< Hysteresis Voltage: 0mV
+    COMP_Hysteresis_Low               = COMP_CSR_HYST_15,                     ///< Hysteresis Voltage: 15mV
+    COMP_Hysteresis_Medium            = COMP_CSR_HYST_30,                     ///< Hysteresis Voltage: 30mV
+    COMP_Hysteresis_High              = COMP_CSR_HYST_90                      ///< Hysteresis Voltage: 90mV
+} EM_COMP_Hysteresis;
+typedef enum {
+    COMP_Filter_0_Period                = COMP_CSR_OFLT_0,                      ///< filter is ((u32)0x00000000)
+    COMP_Filter_2_Period                = COMP_CSR_OFLT_1,                      ///< filter is ((u32)0x00040000)
+    COMP_Filter_4_Period                = COMP_CSR_OFLT_2,                      ///< filter is ((u32)0x00080000)
+    COMP_Filter_8_Period                = COMP_CSR_OFLT_3,                      ///< filter is ((u32)0x000C0000)
+    COMP_Filter_16_Period               = COMP_CSR_OFLT_4,                      ///< filter is ((u32)0x00100000)
+    COMP_Filter_32_Period               = COMP_CSR_OFLT_5,                      ///< filter is ((u32)0x00140000)
+    COMP_Filter_64_Period               = COMP_CSR_OFLT_6,                      ///< filter is ((u32)0x00180000)
+    COMP_Filter_128_Period              = COMP_CSR_OFLT_7,                      ///< filter is ((u32)0x001C0000)
+} EM_COMP_FILT;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_Mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    COMP_Mode_HighSpeed               = COMP_CSR_MODE_HIGHRATE,               ///< Comparator high rate mode
+    COMP_Mode_MediumSpeed             = COMP_CSR_MODE_MEDIUMRATE,             ///< Comparator medium rate mode
+    COMP_Mode_LowPower                = COMP_CSR_MODE_LOWPOWER,               ///< Comparator low power mode
+    COMP_Mode_UltraLowPower           = COMP_CSR_MODE_LOWESTPOWER             ///< Comparator lowest power mode
+} EM_COMP_Mode;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_OutputLevel
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    COMP_OutputLevel_High             = COMP_CSR_OUT,                         ///<  High output
+    COMP_OutputLevel_Low              = 0x00000000                            ///<  Low output
+} EM_COMP_OutputLevel;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  COMP Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    union {
+        u32 COMP_InvertingInput;
+        u32 Invert;                                                             ///< Selects the inverting input of the comparator.
+    };
+    union {
+        u32 COMP_NonInvertingInput;
+        u32 NonInvert;                                                          ///< Selects the non inverting input of the comparator.
+    };
+    union {
+        u32 COMP_Output;
+        u32 Output;                                                             ///< Selects the output redirection of the comparator.
+        u32 BlankingSrce;                                                       ///< Selects the output blanking source of the comparator.
+    };
+    union {
+        u32 COMP_OutputPol;
+        u32 OutputPol;                                                          ///< Selects the output polarity of the comparator.
+    };
+    union {
+        u32 COMP_Hysteresis;
+        u32 Hysteresis;                                                         ///< Selects the hysteresis voltage of the comparator.
+    };
+    union {
+        u32 COMP_Mode;
+        u32 Mode;                                                               ///< Selects the operating mode of the comparator and allows
+    };
+    union {
+        u32 COMP_Filter;
+        u32 OFLT;                                                               ///< to adjust the speed/consumption.
+    };
+} COMP_InitTypeDef;
+
+
+
+typedef struct {
+
+    FunctionalState COMP_Poll_En;                                                ///< Selects the inverting input of the comparator.
+
+    u32 COMP_Poll_Ch;                                                            ///< Selects the non inverting input of the comparator.
+    u32 COMP_Poll_Fixn;                                                          ///< Selects the output redirection of the comparator.
+    u32 COMP_Poll_Period;                                                        ///< Selects the output polarity of the comparator.
+    u32 COMP_Poll_Pout;                                                          ///< Selects the hysteresis voltage of the comparator.
+
+} COMP_POLL_InitTypeDef;
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup COMP_Exported_Constants
+/// @{
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  COMP Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    COMP1                       =   (0x00000C),                               ///< Select comparator 1
+    COMP2                       =   (0x000010),                               ///< Select comparator 2
+} COMP_Selection_TypeDef;
+
+#define COMP_BlankingSrce_None  ((u32)0x00000000)
+#define COMP_CSR_CLEAR_MASK     ((u32)0x00000003)
+
+#define COMP_CSR_COMPSW1        ((u32)0x00000002)
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+///@defgroup COMP_Exported_Variables
+/// @{
+#ifdef _HAL_COMP_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup COMP_Exported_Functions
+/// @{
+
+
+void COMP_DeInit(COMP_Selection_TypeDef selection);
+void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct);
+void COMP_StructInit(COMP_InitTypeDef* init_struct);
+void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state);
+void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state);
+void COMP_LockConfig(COMP_Selection_TypeDef selection);
+
+u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection);
+
+void COMP_SetCrv(u8 crv_select, u8 crv_level);
+#define  SET_COMP_CRV COMP_SetCrv
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_COMP_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h
new file mode 100644
index 000000000..758c7a618
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h
@@ -0,0 +1,62 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_conf.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GENERIC MICROCONTROLLER
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_CONF_H
+#define __HAL_CONF_H
+// Files includes
+#include "mm32_device.h"
+
+#include "hal_adc.h"
+#include "hal_bkp.h"
+#include "hal_can.h"
+#include "hal_comp.h"
+#include "hal_crc.h"
+#include "hal_crs.h"
+#include "hal_dac.h"
+#include "hal_dbg.h"
+#include "hal_dma.h"
+#include "hal_exti.h"
+#include "hal_flash.h"
+#include "hal_gpio.h"
+#include "hal_i2c.h"
+#include "hal_iwdg.h"
+#include "hal_misc.h"
+#include "hal_pwr.h"
+#include "hal_rcc.h"
+#include "hal_rtc.h"
+#include "hal_spi.h"
+#include "hal_syscfg.h"
+#include "hal_tim.h"
+#include "hal_uart.h"
+#include "hal_uid.h"
+#include "hal_wwdg.h"
+#include "hal_redefine.h"
+#include "hal_eth.h"
+#include "hal_eth_conf.h"
+#include "hal_fsmc.h"
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_CONF_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h
new file mode 100644
index 000000000..f5f3d6054
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h
@@ -0,0 +1,84 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_crc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRC
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_CRC_H
+#define __HAL_CRC_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_crc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRC_HAL
+/// @brief CRC HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRC_Exported_Types
+/// @{
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRC_Exported_Constants
+/// @{
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRC_Exported_Variables
+/// @{
+#ifdef _HAL_CRC_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRC_Exported_Functions
+/// @{
+void CRC_ResetDR(void);
+void CRC_SetIDRegister(u8 id_value);
+
+u32 CRC_CalcCRC(u32 data);
+u32 CRC_CalcBlockCRC(u32* buffer, u32 length);
+u32 CRC_GetCRC(void);
+
+u8 CRC_GetIDRegister(void);
+
+/// @}
+
+/// @}
+
+/// @}
+
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_CRC_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h
new file mode 100644
index 000000000..d3c2a6cc5
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h
@@ -0,0 +1,46 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_crs.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRS
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_CRS_H
+#define __HAL_CRS_H
+
+
+// Files includes
+#include "types.h"
+#include "reg_crs.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup CRS_HAL
+/// @brief CRS HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Types
+/// @{
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h
new file mode 100644
index 000000000..e538b20b7
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h
@@ -0,0 +1,166 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_dac.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DAC
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_DAC_H
+#define __HAL_DAC_H
+
+// Files includes
+#include "types.h"
+#include "reg_dac.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DAC_HAL
+/// @brief DAC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DAC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_Trigger_Selection
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DAC_Trigger_None     = 0x00000000,
+    DAC_Trigger_T1_TRIG  = (DAC_CR_TSEL1_TIM1_TRIG | DAC_CR_TEN1),
+    DAC_Trigger_T3_TRIG  = (DAC_CR_TSEL1_TIM3_TRIG | DAC_CR_TEN1),
+    DAC_Trigger_T2_TRIG  = (DAC_CR_TSEL1_TIM2_TRIG | DAC_CR_TEN1),
+    DAC_Trigger_T4_TRIG  = (DAC_CR_TSEL1_TIM4_TRIG | DAC_CR_TEN1),
+    DAC_Trigger_Ext_IT9  = (DAC_CR_TSEL1_EXTI9 | DAC_CR_TEN1),
+    DAC_Trigger_Software = (DAC_CR_TSEL1_SOFTWARE)
+} emDACTRIG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_Wave_Generation
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DAC_WaveGeneration_None     = DAC_CR_WAVE1_NONE,
+    DAC_WaveGeneration_Noise    = DAC_CR_WAVE1_NOISE,
+    DAC_WaveGeneration_Triangle = DAC_CR_WAVE1_TRIANGLE
+} emDACWAVE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_Mask_Amplitude
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DAC_TriangleAmplitude_1    = DAC_CR_MAMP1_1,
+    DAC_TriangleAmplitude_3    = DAC_CR_MAMP1_3,
+    DAC_TriangleAmplitude_7    = DAC_CR_MAMP1_7,
+    DAC_TriangleAmplitude_15   = DAC_CR_MAMP1_15,
+    DAC_TriangleAmplitude_31   = DAC_CR_MAMP1_31,
+    DAC_TriangleAmplitude_63   = DAC_CR_MAMP1_63,
+    DAC_TriangleAmplitude_127  = DAC_CR_MAMP1_127,
+    DAC_TriangleAmplitude_255  = DAC_CR_MAMP1_255,
+    DAC_TriangleAmplitude_511  = DAC_CR_MAMP1_511,
+    DAC_TriangleAmplitude_1023 = DAC_CR_MAMP1_1023,
+    DAC_TriangleAmplitude_2047 = DAC_CR_MAMP1_2047,
+    DAC_TriangleAmplitude_4095 = DAC_CR_MAMP1_4095
+} emDACAMP_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief channel
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DAC_Channel_1,                                                              ///< DAC channel 1
+    DAC_Channel_2 = (u32)0x00000010                                             ///< DAC Channel 2
+} emDACCH_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_Data_Alignement
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DAC_Align_12b_R = ((u32)0x00000000),
+    DAC_Align_12b_L = ((u32)0x00000004),
+    DAC_Align_8b_R  = ((u32)0x00000008)
+} emDACALIGN_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_Output_Buffer
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DAC_OutputBuffer_Enable  = 0x00000000,                                      ///< DAC output buffer enable
+    DAC_OutputBuffer_Disable = DAC_CR_BOFF1                                     ///< DAC output buffer disable
+} emDACBOFF_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  DAC Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    emDACTRIG_TypeDef DAC_Trigger;
+    emDACWAVE_TypeDef DAC_WaveGeneration;
+    emDACAMP_TypeDef  DAC_LFSRUnmask_TriangleAmplitude;
+    emDACBOFF_TypeDef DAC_OutputBuffer;
+} DAC_InitTypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DAC_Exported_Constants
+/// @{
+#define DHR12R1_Offset  ((u32)0x00000008)
+#define DHR12R2_Offset  ((u32)0x00000014)
+#define DHR12RD_Offset  ((u32)0x00000020)
+#define DOR_Offset      ((u32)0x0000002C)
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DAC_Exported_Variables
+/// @{
+#ifdef _HAL_DAC_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DAC_Exported_Functions
+/// @{
+void DAC_DeInit(void);
+void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct);
+void DAC_StructInit(DAC_InitTypeDef* init_struct);
+void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state);
+void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state);
+void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state);
+void DAC_DualSoftwareTriggerCmd(FunctionalState state);
+void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state);
+void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data);
+void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data);
+void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1);
+
+u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_DAC_H
+////////////////////////////////////////////////////////////////////////////////
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h
new file mode 100644
index 000000000..0e9b41d1e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h
@@ -0,0 +1,72 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_dbg.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DBG
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_DBG_H
+#define __HAL_DBG_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_dbg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DBG_HAL
+/// @brief DBG HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DBG_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DIV_Exported_Variables
+/// @{
+#ifdef _HAL_DBG_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DBG_Exported_Functions
+/// @{
+void DBGMCU_Configure(u32 periph, FunctionalState state);
+
+/// @}
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_DBG_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h
new file mode 100644
index 000000000..ff2133702
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h
@@ -0,0 +1,41 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_device.h
+/// @author   AE team
+/// @brief    CMSIS Cortex-M Peripheral Access Layer for MindMotion
+///           microcontroller devices
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_DEVICE_H
+#define __HAL_DEVICE_H
+
+
+
+
+
+#include "mm32_device.h"
+
+
+#endif // __HAL_device_H
+
+/// @}
+
+
+/// @}
+
+/// @}
+
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h
new file mode 100644
index 000000000..892e750b5
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h
@@ -0,0 +1,306 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_dma.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DMA
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_DMA_H
+#define __HAL_DMA_H
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_dma.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DMA_HAL
+/// @brief DMA HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DMA_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA data transfer direction Enumerate definition
+/// @anchor DMA_data_transfer_direction
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMA_DIR_PeripheralSRC = 0U,
+    DMA_DIR_PeripheralDST = DMA_CCR_DIR  // 0x00000010U
+} DMA_data_transfer_direction_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA peripheral incremented mode Enumerate definition
+/// @anchor DMA_peripheral_incremented_mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMA_PeripheralInc_Disable = 0U,
+    DMA_PeripheralInc_Enable  = DMA_CCR_PINC  // 0x00000040U
+} DMA_peripheral_incremented_mode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA memory incremented mode Enumerate definition
+/// @anchor DMA_memory_incremented_mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMA_MemoryInc_Disable = 0U,
+    DMA_MemoryInc_Enable  = DMA_CCR_MINC  // 0x00000080U
+} DMA_memory_incremented_mode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA peripheral data size Enumerate definition
+/// @anchor DMA_peripheral_data_size
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMA_PeripheralDataSize_Byte     = 0U,
+    DMA_PeripheralDataSize_HalfWord = DMA_CCR_PSIZE_HALFWORD,
+    DMA_PeripheralDataSize_Word     = DMA_CCR_PSIZE_WORD
+} DMA_peripheral_data_size_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA memory data size Enumerate definition
+/// @anchor DMA_memory_data_size
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMA_MemoryDataSize_Byte     = 0U,
+    DMA_MemoryDataSize_HalfWord = DMA_CCR_MSIZE_HALFWORD,                       // 0x00000400U
+    DMA_MemoryDataSize_Word     = DMA_CCR_MSIZE_WORD                            // 0x00000800U
+} DMA_memory_data_size_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA circular normal mode Enumerate definition
+/// @anchor DMA_circular_normal_mode
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMA_Mode_Normal   = 0U,
+    DMA_Mode_Circular = DMA_CCR_CIRC                                            // 0x00000020U
+} DMA_circular_normal_mode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA priority level Enumerate definition
+/// @anchor DMA_priority_level
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMA_Priority_Low      = 0U,
+    DMA_Priority_Medium   = DMA_CCR_PL_Medium,                                  // 0x00001000U
+    DMA_Priority_High     = DMA_CCR_PL_High,                                    // 0x00002000U
+    DMA_Priority_VeryHigh = DMA_CCR_PL_VeryHigh                                 // 0x00003000U
+} DMA_priority_level_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA memory to memory Enumerate definition
+/// @anchor DMA_memory_to_memory
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMA_M2M_Disable = 0U,
+    DMA_M2M_Enable  = DMA_CCR_M2M                                               // 0x00004000U
+} DMA_memory_to_memory_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA auto reload Enumerate definition
+/// @anchor DMA_auto_reload
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMA_Auto_Reload_Disable = 0U,  //
+    DMA_Auto_Reload_Enable  = DMA_CCR_ARE
+} DMA_auto_reload_TypeDef;
+/// @brief DMA Interrupt Setting Enumerate definition
+/// @anchor DMA_auto_reload
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMA_IT_TC                 = DMA_CCR_TCIE, //(0x00000002UL),
+    DMA_IT_HT                 = DMA_CCR_HTIE, //(0x00000004UL),
+    DMA_IT_TE                 = DMA_CCR_TEIE, //(0x00000008UL),
+} DMA_Interrupt_EN_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA interrupts Enumerate definition
+/// @anchor DMA_Flags
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    DMAx_IT_GLy               = (0x00000001UL),
+    DMAx_IT_TCy               = (0x00000002UL),
+    DMAx_IT_HTy               = (0x00000004UL),
+    DMAx_IT_TEy               = (0x00000008UL),
+    DMA1_IT_GL1               = (0x00000001UL),
+    DMA1_IT_TC1               = (0x00000002UL),
+    DMA1_IT_HT1               = (0x00000004UL),
+    DMA1_IT_TE1               = (0x00000008UL),
+    DMA1_IT_GL2               = (0x00000010UL),
+    DMA1_IT_TC2               = (0x00000020UL),
+    DMA1_IT_HT2               = (0x00000040UL),
+    DMA1_IT_TE2               = (0x00000080UL),
+    DMA1_IT_GL3               = (0x00000100UL),
+    DMA1_IT_TC3               = (0x00000200UL),
+    DMA1_IT_HT3               = (0x00000400UL),
+    DMA1_IT_TE3               = (0x00000800UL),
+    DMA1_IT_GL4               = (0x00001000UL),
+    DMA1_IT_TC4               = (0x00002000UL),
+    DMA1_IT_HT4               = (0x00004000UL),
+    DMA1_IT_TE4               = (0x00008000UL),
+    DMA1_IT_GL5               = (0x00010000UL),
+    DMA1_IT_TC5               = (0x00020000UL),
+    DMA1_IT_HT5               = (0x00040000UL),
+    DMA1_IT_TE5               = (0x00080000UL),
+    DMA1_IT_GL6               = (0x00100000UL),
+    DMA1_IT_TC6               = (0x00200000UL),
+    DMA1_IT_HT6               = (0x00400000UL),
+    DMA1_IT_TE6               = (0x00800000UL),
+    DMA1_IT_GL7               = (0x01000000UL),
+    DMA1_IT_TC7               = (0x02000000UL),
+    DMA1_IT_HT7               = (0x04000000UL),
+    DMA1_IT_TE7               = (0x08000000UL),
+    DMA2_IT_GL1               = (0x10000001UL),
+    DMA2_IT_TC1               = (0x10000002UL),
+    DMA2_IT_HT1               = (0x10000004UL),
+    DMA2_IT_TE1               = (0x10000008UL),
+    DMA2_IT_GL2               = (0x10000010UL),
+    DMA2_IT_TC2               = (0x10000020UL),
+    DMA2_IT_HT2               = (0x10000040UL),
+    DMA2_IT_TE2               = (0x10000080UL),
+    DMA2_IT_GL3               = (0x10000100UL),
+    DMA2_IT_TC3               = (0x10000200UL),
+    DMA2_IT_HT3               = (0x10000400UL),
+    DMA2_IT_TE3               = (0x10000800UL),
+    DMA2_IT_GL4               = (0x10001000UL),
+    DMA2_IT_TC4               = (0x10002000UL),
+    DMA2_IT_HT4               = (0x10004000UL),
+    DMA2_IT_TE4               = (0x10008000UL),
+    DMA2_IT_GL5               = (0x10010000UL),
+    DMA2_IT_TC5               = (0x10020000UL),
+    DMA2_IT_HT5               = (0x10040000UL),
+    DMA2_IT_TE5               = (0x10080000UL),
+} DMA_Interrupts_TypeDef;
+typedef enum {
+    DMAx_FLAG_GLy               = (0x00000001UL),
+    DMAx_FLAG_TCy               = (0x00000002UL),
+    DMAx_FLAG_HTy               = (0x00000004UL),
+    DMAx_FLAG_TEy               = (0x00000008UL),
+    DMA1_FLAG_GL1               = (0x00000001UL),
+    DMA1_FLAG_TC1               = (0x00000002UL),
+    DMA1_FLAG_HT1               = (0x00000004UL),
+    DMA1_FLAG_TE1               = (0x00000008UL),
+    DMA1_FLAG_GL2               = (0x00000010UL),
+    DMA1_FLAG_TC2               = (0x00000020UL),
+    DMA1_FLAG_HT2               = (0x00000040UL),
+    DMA1_FLAG_TE2               = (0x00000080UL),
+    DMA1_FLAG_GL3               = (0x00000100UL),
+    DMA1_FLAG_TC3               = (0x00000200UL),
+    DMA1_FLAG_HT3               = (0x00000400UL),
+    DMA1_FLAG_TE3               = (0x00000800UL),
+    DMA1_FLAG_GL4               = (0x00001000UL),
+    DMA1_FLAG_TC4               = (0x00002000UL),
+    DMA1_FLAG_HT4               = (0x00004000UL),
+    DMA1_FLAG_TE4               = (0x00008000UL),
+    DMA1_FLAG_GL5               = (0x00010000UL),
+    DMA1_FLAG_TC5               = (0x00020000UL),
+    DMA1_FLAG_HT5               = (0x00040000UL),
+    DMA1_FLAG_TE5               = (0x00080000UL),
+    DMA1_FLAG_GL6               = (0x00100000UL),
+    DMA1_FLAG_TC6               = (0x00200000UL),
+    DMA1_FLAG_HT6               = (0x00400000UL),
+    DMA1_FLAG_TE6               = (0x00800000UL),
+    DMA1_FLAG_GL7               = (0x01000000UL),
+    DMA1_FLAG_TC7               = (0x02000000UL),
+    DMA1_FLAG_HT7               = (0x04000000UL),
+    DMA1_FLAG_TE7               = (0x08000000UL),
+    DMA2_FLAG_GL1               = (0x10000001UL),
+    DMA2_FLAG_TC1               = (0x10000002UL),
+    DMA2_FLAG_HT1               = (0x10000004UL),
+    DMA2_FLAG_TE1               = (0x10000008UL),
+    DMA2_FLAG_GL2               = (0x10000010UL),
+    DMA2_FLAG_TC2               = (0x10000020UL),
+    DMA2_FLAG_HT2               = (0x10000040UL),
+    DMA2_FLAG_TE2               = (0x10000080UL),
+    DMA2_FLAG_GL3               = (0x10000100UL),
+    DMA2_FLAG_TC3               = (0x10000200UL),
+    DMA2_FLAG_HT3               = (0x10000400UL),
+    DMA2_FLAG_TE3               = (0x10000800UL),
+    DMA2_FLAG_GL4               = (0x10001000UL),
+    DMA2_FLAG_TC4               = (0x10002000UL),
+    DMA2_FLAG_HT4               = (0x10004000UL),
+    DMA2_FLAG_TE4               = (0x10008000UL),
+    DMA2_FLAG_GL5               = (0x10010000UL),
+    DMA2_FLAG_TC5               = (0x10020000UL),
+    DMA2_FLAG_HT5               = (0x10040000UL),
+    DMA2_FLAG_TE5               = (0x10080000UL),
+} DMA_Flags_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  DMA Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u32 DMA_PeripheralBaseAddr;                                 ///< the peripheral base address for DMA Channeln.
+    u32 DMA_MemoryBaseAddr;                                     ///< the memory base address for DMA Channeln.
+    DMA_data_transfer_direction_TypeDef DMA_DIR;                ///< the peripheral is the source or destination.
+    u32 DMA_BufferSize;                                         ///< Specifies the buffer size, in data unit, of the Buffer size
+    DMA_peripheral_incremented_mode_TypeDef DMA_PeripheralInc;  ///< Specifies whether the Peripheral address increment or not
+    DMA_memory_incremented_mode_TypeDef DMA_MemoryInc;          ///< Specifies whether the memory address register is increment or not
+    DMA_peripheral_data_size_TypeDef DMA_PeripheralDataSize;    ///< Specifies the Peripheral data width.
+    DMA_memory_data_size_TypeDef DMA_MemoryDataSize;            ///< Specifies the Memory data width.
+    DMA_circular_normal_mode_TypeDef DMA_Mode;                  ///< Specifies the operation mode of the DMA Channeln  circular or normal mode.
+    DMA_priority_level_TypeDef DMA_Priority;                    ///< Specifies the software priority for the DMA priority level
+    DMA_memory_to_memory_TypeDef DMA_M2M;                       ///< Specifies if the DMA Channeln will be used in  memory-to-memory transfer.
+    DMA_auto_reload_TypeDef DMA_Auto_reload;                     ///< Specifies if the DMA Channeln will auto reload the CNDTR register
+} DMA_InitTypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DMA_Exported_Variables
+/// @{
+#ifdef _HAL_DMA_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DMA_Exported_Functions
+/// @{
+
+void DMA_DeInit(DMA_Channel_TypeDef* channel);
+void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct);
+void DMA_StructInit(DMA_InitTypeDef* init_struct);
+void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state);
+void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state);
+void DMA_ClearFlag(DMA_Flags_TypeDef flag);
+void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it);
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length);
+u16        DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel);
+FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag);
+ITStatus   DMA_GetITStatus(DMA_Interrupts_TypeDef it);
+
+void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 addr);
+void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 len);
+void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 addr);
+
+/// @}
+
+/// @}
+
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_DMA_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h
new file mode 100644
index 000000000..4000bbaa5
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h
@@ -0,0 +1,729 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     HAL_eth.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE HAL_eth.h EXAMPLES.
+/// ////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT  MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __HAL_ETH_H
+#define __HAL_ETH_H
+
+// Files includes
+#include "types.h"
+#include "mm32_device.h"
+#include "HAL_eth_conf.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ETH_HAL
+/// @brief ETH HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ETH_Exported_Types
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// ETH     | Header | Extra | VLAN tag | Payload   | CRC |
+// Size    | 14     | 2     | 4        | 46 ~ 1500 | 4   |
+#define ETH_MAX_PACKET_SIZE     1524
+#define ETH_HEADER              14      ///< MAC Dest Addr 6 byte + MAC Src Addr 6 byte + Lenth/Type 2 byte
+#define ETH_EXTRA               2
+#define VLAN_TAG                4
+#define ETH_PAYLOAD_MIN         46
+#define ETH_PAYLOAD_MAX         1500
+#define JUMBO_FRAME_PAYLOAD     9000
+
+#ifndef ETH_RX_BUF_SIZE
+#define ETH_RX_BUF_SIZE     ETH_MAX_PACKET_SIZE
+#endif
+
+#ifndef ETH_RX_BUF_NUM
+#define ETH_RX_BUF_NUM      4
+#endif
+
+#ifndef ETH_TX_BUF_SIZE
+#define ETH_TX_BUF_SIZE     ETH_MAX_PACKET_SIZE
+#endif
+
+#ifndef ETH_TX_BUF_NUM
+#define ETH_TX_BUF_NUM      4
+#endif
+
+#define ETH_DMA_RDES_FL_Pos     16                                              ///< Ethernet DMA Received Frame Length Position
+
+#define ETH_WAKEUP_REGISTER_LENGTH                          8                   ///< ETHERNET Remote Wake-up frame register length
+
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT       17                  ///< ETHERNET Missed frames counter Shift
+
+#define ETH_DMA_TDES_COLLISION_COUNTSHIFT                   3                   ///< ETHERNET DMA Tx descriptors Collision Count Shift
+#define ETH_DMA_TDES_BUFFER2_SIZESHIFT                      11                  ///< ETHERNET DMA Tx descriptors Buffer2 Size Shift
+
+#define ETH_DMA_RDES_FRAME_LENGTHSHIFT                      16                  ///< ETHERNET DMA Rx descriptors Frame Length Shift
+#define ETH_DMA_RDES_BUFFER2_SIZESHIFT                      11                  ///< ETHERNET DMA Rx descriptors Buffer2 Size Shift
+
+///< ETHERNET errors
+#define  ETH_ERROR                                          ((u32)0)
+#define  ETH_SUCCESS                                        ((u32)1)
+
+
+#ifdef _HAL_ETH_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+#endif
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH Init Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32    ETH_AutoNegotiation;
+    __IO u32    ETH_Watchdog;
+    __IO u32    ETH_Jabber;
+    __IO u32    ETH_InterFrameGap;
+    __IO u32    ETH_CarrierSense;
+    __IO u32    ETH_Speed;
+    __IO u32    ETH_ReceiveOwn;
+    __IO u32    ETH_LoopbackMode;
+    __IO u32    ETH_Mode;
+    __IO u32    ETH_ChecksumOffload;
+    __IO u32    ETH_RetryTransmission;
+    __IO u32    ETH_AutomaticPadCRCStrip;
+    __IO u32    ETH_BackOffLimit;
+    __IO u32    ETH_DeferralCheck;
+    __IO u32    ETH_ReceiveAll;
+    __IO u32    ETH_SourceAddrFilter;
+    __IO u32    ETH_PassControlFrames;
+    __IO u32    ETH_BroadcastFramesReception;
+    __IO u32    ETH_DestinationAddrFilter;
+    __IO u32    ETH_PromiscuousMode;
+    __IO u32    ETH_MulticastFramesFilter;
+    __IO u32    ETH_UnicastFramesFilter;
+    __IO u32    ETH_HashTableHigh;
+    __IO u32    ETH_HashTableLow;
+    __IO u32    ETH_PauseTime;
+    __IO u32    ETH_ZeroQuantaPause;
+    __IO u32    ETH_PauseLowThreshold;
+    __IO u32    ETH_UnicastPauseFrameDetect;
+    __IO u32    ETH_ReceiveFlowControl;
+    __IO u32    ETH_TransmitFlowControl;
+    __IO u32    ETH_VLANTagComparison;
+    __IO u32    ETH_VLANTagIdentifier;
+    __IO u32    ETH_DropTCPIPChecksumErrorFrame;
+    __IO u32    ETH_ReceiveStoreForward;
+    __IO u32    ETH_FlushReceivedFrame;
+    __IO u32    ETH_TransmitStoreForward;
+    __IO u32    ETH_TransmitThresholdControl;
+    __IO u32    ETH_ForwardErrorFrames;
+    __IO u32    ETH_ForwardUndersizedGoodFrames;
+    __IO u32    ETH_ReceiveThresholdControl;
+    __IO u32    ETH_SecondFrameOperate;
+    __IO u32    ETH_AddressAlignedBeats;
+    __IO u32    ETH_FixedBurst;
+    __IO u32    ETH_RxDMABurstLength;
+    __IO u32    ETH_TxDMABurstLength;
+    __IO u32    ETH_DescriptorSkipLength;
+    __IO u32    ETH_DMAArbitration;
+} ETH_InitTypeDef;
+
+typedef struct {
+    __IO u32   CS;                                                              ///< Control and Status
+    __IO u32   BL;                                                              ///< Buffer1, Buffer2 lengths
+    __IO u32   BUF1ADDR;                                                        ///< Buffer1 address pointer
+    __IO u32   BUF2NDADDR;                                                      ///< Buffer2 or next descriptor address pointer
+
+#ifdef USE_ENHANCED_DMA_DESCRIPTORS                                             ///< Enhanced ETHERNET DMA PTP Descriptors
+    __IO u32        ExtendedStatus;                                             ///< Extended status for PTP receive descriptor
+    __IO u32        Reserved1;                                                  ///< Reserved
+    __IO u32        TimeStampLow;                                               ///< Time Stamp Low value for transmit and receive
+    __IO u32        TimeStampHigh;                                              ///< Time Stamp High value for transmit and receive
+#endif
+} ETH_DMADESCTypeDef;
+
+typedef struct {
+    __IO u32                         len;
+    __IO u32                         buf;
+    __IO ETH_DMADESCTypeDef*    ptrDesc;
+} FrameTypeDef;
+
+typedef struct  {
+    __IO ETH_DMADESCTypeDef*    ptrFS_Rx_Desc;                                  ///< First Segment Rx Desc
+    __IO ETH_DMADESCTypeDef*    ptrLS_Rx_Desc;                                  ///< Last Segment Rx Desc
+    __IO u32               cnt;                                            ///< Segment count
+} ETH_DMA_Rx_Frame_infos;
+
+
+
+#define ETH_DMA_TDES_OWN                     ((u32)0x80000000)             ///< OWN bit: descriptor is owned by DMA engine
+#define ETH_DMA_TDES_ES                      ((u32)0x00008000)             ///< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT
+#define ETH_DMA_TDES_JT                      ((u32)0x00004000)             ///< Jabber Timeout
+#define ETH_DMA_TDES_FF                      ((u32)0x00002000)             ///< Frame Flushed: DMA/MTL flushed the frame due to SW flush
+#define ETH_DMA_TDES_LCA                     ((u32)0x00000800)             ///< Loss of Carrier: carrier lost during transmission
+#define ETH_DMA_TDES_NC                      ((u32)0x00000400)             ///< No Carrier: no carrier signal from the transceiver
+#define ETH_DMA_TDES_LCO                     ((u32)0x00000200)             ///< Late Collision: transmission aborted due to collision
+#define ETH_DMA_TDES_EC                      ((u32)0x00000100)             ///< Excessive Collision: transmission aborted after 16 collisions
+#define ETH_DMA_TDES_VF                      ((u32)0x00000080)             ///< VLAN Frame
+#define ETH_DMA_TDES_CC                      ((u32)0x00000078)             ///< Collision Count
+#define ETH_DMA_TDES_ED                      ((u32)0x00000004)             ///< Excessive Deferral
+#define ETH_DMA_TDES_UF                      ((u32)0x00000002)             ///< Underflow Error: late data arrival from the memory
+#define ETH_DMA_TDES_DB                      ((u32)0x00000001)             ///< Deferred Bit
+
+#define ETH_DMA_TDES_IC                      ((u32)0x80000000)             ///< Interrupt on Completion
+#define ETH_DMA_TDES_LS                      ((u32)0x40000000)             ///< Last Segment
+#define ETH_DMA_TDES_FS                      ((u32)0x20000000)             ///< First Segment
+#define ETH_DMA_TDES_DC                      ((u32)0x04000000)             ///< Disable CRC
+#define ETH_DMA_TDES_TER                     ((u32)0x02000000)             ///< Transmit end of ring
+#define ETH_DMA_TDES_TCH                     ((u32)0x01000000)             ///< Second Address Chained
+#define ETH_DMA_TDES_DP                      ((u32)0x00800000)             ///< Disable Padding
+#define ETH_DMA_TDES_TBS2                    ((u32)0x003FF800)             ///< Transmit Buffer 2 Size
+#define ETH_DMA_TDES_TBS1                    ((u32)0x000007FF)             ///< Transmit Buffer 1 Size
+
+#define ETH_DMA_TDES_B1AP                    ((u32)0xFFFFFFFF)             ///< Buffer 1 Address Pointer
+
+#define ETH_DMA_TDES_B2AP                    ((u32)0xFFFFFFFF)             ///< Buffer 2 Address Pointer
+
+#if defined(USE_ENHANCED_DMA_DESCRIPTORS)
+#define ETH_DMA_PTP_TDES_TTSL                ((u32)0xFFFFFFFF)              ///< Transmit Time Stamp Low
+#define ETH_DMA_PTP_TDES_TTSH                ((u32)0xFFFFFFFF)              ///< Transmit Time Stamp High
+#endif
+
+#define ETH_DMA_RDES_OWN                     ((u32)0x80000000)             ///< OWN bit: descriptor is owned by DMA engine
+#define ETH_DMA_RDES_AFM                     ((u32)0x40000000)             ///< DA Filter Fail for the rx frame
+#define ETH_DMA_RDES_FL                      ((u32)0x3FFF0000)             ///< Receive descriptor frame length
+#define ETH_DMA_RDES_ES                      ((u32)0x00008000)             ///< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE
+#define ETH_DMA_RDES_DE                      ((u32)0x00004000)             ///< Descriptor error: no more descriptors for receive frame
+#define ETH_DMA_RDES_SAF                     ((u32)0x00002000)             ///< SA Filter Fail for the received frame
+#define ETH_DMA_RDES_LE                      ((u32)0x00001000)             ///< Frame size not matching with length field
+#define ETH_DMA_RDES_OE                      ((u32)0x00000800)             ///< Overflow Error: Frame was damaged due to buffer overflow
+#define ETH_DMA_RDES_VLAN                    ((u32)0x00000400)             ///< VLAN Tag: received frame is a VLAN frame
+#define ETH_DMA_RDES_FS                      ((u32)0x00000200)             ///< First descriptor of the frame
+#define ETH_DMA_RDES_LS                      ((u32)0x00000100)             ///< Last descriptor of the frame
+#define ETH_DMA_RDES_IPV4HCE                 ((u32)0x00000080)             ///< IPC Checksum Error: Rx Ipv4 header checksum error
+#define ETH_DMA_RDES_LC                      ((u32)0x00000040)             ///< Late collision occurred during reception
+#define ETH_DMA_RDES_FT                      ((u32)0x00000020)             ///< Frame type - Ethernet, otherwise 802.3
+#define ETH_DMA_RDES_RWT                     ((u32)0x00000010)             ///< Receive Watchdog Timeout: watchdog timer expired during reception
+#define ETH_DMA_RDES_RE                      ((u32)0x00000008)             ///< Receive error: error reported by MII interface
+#define ETH_DMA_RDES_DBE                     ((u32)0x00000004)             ///< Dribble bit error: frame contains non int multiple of 8 bits
+#define ETH_DMA_RDES_CE                      ((u32)0x00000002)             ///< CRC error
+#define ETH_DMA_RDES_MAMPCE                  ((u32)0x00000001)             ///< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
+
+#define ETH_DMA_RDES_DIC                     ((u32)0x80000000)             ///< Disable Interrupt on Completion
+#define ETH_DMA_RDES_RER                     ((u32)0x02000000)             ///< Receive End of Ring
+#define ETH_DMA_RDES_RCH                     ((u32)0x01000000)             ///< Second Address Chained
+#define ETH_DMA_RDES_RBS2                    ((u32)0x003FF800)             ///< Receive Buffer2 Size
+#define ETH_DMA_RDES_RBS1                    ((u32)0x000007FF)             ///< Receive Buffer1 Size
+
+#define ETH_DMA_RDES_B1AP                    ((u32)0xFFFFFFFF)             ///< Buffer 1 Address Pointer
+
+#define ETH_DMA_RDES_B2AP                    ((u32)0xFFFFFFFF)             ///< Buffer 2 Address Pointer
+
+
+#if defined(USE_ENHANCED_DMA_DESCRIPTORS)
+#define ETH_DMA_PTP_RDES_PTPV                            ((u32)0x00002000)  ///< PTP Version
+#define ETH_DMA_PTP_RDES_PTPFT                           ((u32)0x00001000)  ///< PTP Frame Type
+#define ETH_DMA_PTP_RDES_PTPMT                           ((u32)0x00000F00)  ///< PTP Message Type
+#define ETH_DMA_PTP_RDES_PTPMT_Sync                      ((u32)0x00000100)  ///< SYNC message (all clock types)
+#define ETH_DMA_PTP_RDES_PTPMT_FollowUp                  ((u32)0x00000200)  ///< FollowUp message (all clock types)
+#define ETH_DMA_PTP_RDES_PTPMT_DelayReq                  ((u32)0x00000300)  ///< DelayReq message (all clock types)
+#define ETH_DMA_PTP_RDES_PTPMT_DelayResp                 ((u32)0x00000400)  ///< DelayResp message (all clock types)
+#define ETH_DMA_PTP_RDES_PTPMT_PdelayReq_Announce        ((u32)0x00000500)  ///< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock)
+#define ETH_DMA_PTP_RDES_PTPMT_PdelayResp_Manag          ((u32)0x00000600)  ///< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)
+#define ETH_DMA_PTP_RDES_PTPMT_PdelayRespFollowUp_Signal ((u32)0x00000700)  ///< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock)
+#define ETH_DMA_PTP_RDES_IPV6PR                          ((u32)0x00000080)  ///< IPv6 Packet Received
+#define ETH_DMA_PTP_RDES_IPV4PR                          ((u32)0x00000040)  ///< IPv4 Packet Received
+#define ETH_DMA_PTP_RDES_IPCB                            ((u32)0x00000020)  ///< IP Checksum Bypassed
+#define ETH_DMA_PTP_RDES_IPPE                            ((u32)0x00000010)  ///< IP Payload Error
+#define ETH_DMA_PTP_RDES_IPHE                            ((u32)0x00000008)  ///< IP Header Error
+#define ETH_DMA_PTP_RDES_IPPT                            ((u32)0x00000007)  ///< IP Payload Type
+#define ETH_DMA_PTP_RDES_IPPT_UDP                        ((u32)0x00000001)  ///< UDP payload encapsulated in the IP datagram
+#define ETH_DMA_PTP_RDES_IPPT_TCP                        ((u32)0x00000002)  ///< TCP payload encapsulated in the IP datagram
+#define ETH_DMA_PTP_RDES_IPPT_ICMP                       ((u32)0x00000003)  ///< ICMP payload encapsulated in the IP datagram
+
+
+
+#define ETH_DMA_PTP_RDES_TTSL               ((u32)0xFFFFFFFF)              ///< Receive Time Stamp Low
+#define ETH_DMA_PTP_RDES_TTSH               ((u32)0xFFFFFFFF)              ///< Receive Time Stamp High
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+#define PHY_READ_TIMEOUT                    ((u32)0x0004FFFF)
+#define PHY_WRITE_TIMEOUT                   ((u32)0x0004FFFF)
+
+#define PHY_BCR                             0                                   ///< Transceiver Basic Control Register
+#define PHY_BSR                             1                                   ///< Transceiver Basic Status Register
+
+#define PHY_Reset                           ((u16)0x8000)                  ///< PHY Reset
+#define PHY_Loopback                        ((u16)0x4000)                  ///< Select loop-back mode
+#define PHY_FULLDUPLEX_100M                 ((u16)0x2100)                  ///< Set the full-duplex mode at 100 Mb/s
+#define PHY_HALFDUPLEX_100M                 ((u16)0x2000)                  ///< Set the half-duplex mode at 100 Mb/s
+#define PHY_FULLDUPLEX_10M                  ((u16)0x0100)                  ///< Set the full-duplex mode at 10 Mb/s
+#define PHY_HALFDUPLEX_10M                  ((u16)0x0000)                  ///< Set the half-duplex mode at 10 Mb/s
+#define PHY_AutoNegotiation                 ((u16)0x1000)                  ///< Enable auto-negotiation function
+#define PHY_Restart_AutoNegotiation         ((u16)0x0200)                  ///< Restart auto-negotiation function
+#define PHY_Powerdown                       ((u16)0x0800)                  ///< Select the power down mode
+#define PHY_Isolate                         ((u16)0x0400)                  ///< Isolate PHY from MII
+
+#define PHY_AutoNego_Complete               ((u16)0x0020)                  ///< Auto-Negotiation process completed
+#define PHY_Linked_Status                   ((u16)0x0004)                  ///< Valid link established
+#define PHY_Jabber_detection                ((u16)0x0002)                  ///< Jabber condition detected
+
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_AutoNegotiation_Enable          ((u32)0x00000001)
+#define ETH_AutoNegotiation_Disable         ((u32)0x00000000)
+
+#define ETH_Watchdog_Enable                 ((u32)0x00000000)
+#define ETH_Watchdog_Disable                ((u32)0x00800000)
+
+#define ETH_Jabber_Enable                   ((u32)0x00000000)
+#define ETH_Jabber_Disable                  ((u32)0x00400000)
+
+#define ETH_InterFrameGap_96Bit             ((u32)0x00000000)              ///< minimum IFG between frames during transmission is 96Bit
+#define ETH_InterFrameGap_88Bit             ((u32)0x00020000)              ///< minimum IFG between frames during transmission is 88Bit
+#define ETH_InterFrameGap_80Bit             ((u32)0x00040000)              ///< minimum IFG between frames during transmission is 80Bit
+#define ETH_InterFrameGap_72Bit             ((u32)0x00060000)              ///< minimum IFG between frames during transmission is 72Bit
+#define ETH_InterFrameGap_64Bit             ((u32)0x00080000)              ///< minimum IFG between frames during transmission is 64Bit
+#define ETH_InterFrameGap_56Bit             ((u32)0x000A0000)              ///< minimum IFG between frames during transmission is 56Bit
+#define ETH_InterFrameGap_48Bit             ((u32)0x000C0000)              ///< minimum IFG between frames during transmission is 48Bit
+#define ETH_InterFrameGap_40Bit             ((u32)0x000E0000)              ///< minimum IFG between frames during transmission is 40Bit
+
+#define ETH_CarrierSense_Enable             ((u32)0x00000000)
+#define ETH_CarrierSense_Disable            ((u32)0x00010000)
+
+#define ETH_Speed_10M                       ((u32)0x00000000)
+#define ETH_Speed_100M                      ((u32)0x00004000)
+
+#define ETH_ReceiveOwn_Enable               ((u32)0x00000000)
+#define ETH_ReceiveOwn_Disable              ((u32)0x00002000)
+
+#define ETH_LoopbackMode_Enable             ((u32)0x00001000)
+#define ETH_LoopbackMode_Disable            ((u32)0x00000000)
+
+#define ETH_Mode_FullDuplex                 ((u32)0x00000800)
+#define ETH_Mode_HalfDuplex                 ((u32)0x00000000)
+
+#define ETH_ChecksumOffload_Enable          ((u32)0x00000400)
+#define ETH_ChecksumOffload_Disable         ((u32)0x00000000)
+
+#define ETH_RetryTransmission_Enable        ((u32)0x00000000)
+#define ETH_RetryTransmission_Disable       ((u32)0x00000200)
+
+#define ETH_AutomaticPadCRCStrip_Enable     ((u32)0x00000080)
+#define ETH_AutomaticPadCRCStrip_Disable    ((u32)0x00000000)
+
+#define ETH_BackOffLimit_10                 ((u32)0x00000000)
+#define ETH_BackOffLimit_8                  ((u32)0x00000020)
+#define ETH_BackOffLimit_4                  ((u32)0x00000040)
+#define ETH_BackOffLimit_1                  ((u32)0x00000060)
+
+#define ETH_DeferralCheck_Enable            ((u32)0x00000010)
+#define ETH_DeferralCheck_Disable           ((u32)0x00000000)
+
+#define ETH_ReceiveAll_Enable               ((u32)0x80000000)
+#define ETH_ReceiveAll_Disable              ((u32)0x00000000)
+
+#define ETH_SourceAddrFilter_Normal_Enable  ((u32)0x00000200)
+#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300)
+#define ETH_SourceAddrFilter_Disable        ((u32)0x00000000)
+
+#define ETH_PassControlFrames_BlockAll                  ((u32)0x00000040)  ///< MAC filters all control frames from reaching the application
+#define ETH_PassControlFrames_ForwardAll                ((u32)0x00000080)  ///< MAC forwards all control frames to application even if they fail the Address Filter
+#define ETH_PassControlFrames_ForwardPassedAddrFilter   ((u32)0x000000C0)  ///< MAC forwards control frames that pass the Address Filter.
+
+#define ETH_BroadcastFramesReception_Enable             ((u32)0x00000000)
+#define ETH_BroadcastFramesReception_Disable            ((u32)0x00000020)
+
+#define ETH_DestinationAddrFilter_Normal                ((u32)0x00000000)
+#define ETH_DestinationAddrFilter_Inverse               ((u32)0x00000008)
+
+#define ETH_PromiscuousMode_Enable                      ((u32)0x00000001)
+#define ETH_PromiscuousMode_Disable                     ((u32)0x00000000)
+
+#define ETH_MulticastFramesFilter_PerfectHashTable      ((u32)0x00000404)
+#define ETH_MulticastFramesFilter_HashTable             ((u32)0x00000004)
+#define ETH_MulticastFramesFilter_Perfect               ((u32)0x00000000)
+#define ETH_MulticastFramesFilter_None                  ((u32)0x00000010)
+
+#define ETH_UnicastFramesFilter_PerfectHashTable        ((u32)0x00000402)
+#define ETH_UnicastFramesFilter_HashTable               ((u32)0x00000002)
+#define ETH_UnicastFramesFilter_Perfect                 ((u32)0x00000000)
+
+#define ETH_ZeroQuantaPause_Enable                      ((u32)0x00000000)
+#define ETH_ZeroQuantaPause_Disable                     ((u32)0x00000080)
+
+#define ETH_PauseLowThreshold_Minus4                    ((u32)0x00000000)              ///< Pause time minus 4 slot times
+#define ETH_PauseLowThreshold_Minus28                   ((u32)0x00000010)              ///< Pause time minus 28 slot times
+#define ETH_PauseLowThreshold_Minus144                  ((u32)0x00000020)              ///< Pause time minus 144 slot times
+#define ETH_PauseLowThreshold_Minus256                  ((u32)0x00000030)              ///< Pause time minus 256 slot times
+
+#define ETH_UnicastPauseFrameDetect_Enable              ((u32)0x00000008)
+#define ETH_UnicastPauseFrameDetect_Disable             ((u32)0x00000000)
+
+#define ETH_ReceiveFlowControl_Enable                   ((u32)0x00000004)
+#define ETH_ReceiveFlowControl_Disable                  ((u32)0x00000000)
+
+#define ETH_TransmitFlowControl_Enable                  ((u32)0x00000002)
+#define ETH_TransmitFlowControl_Disable                 ((u32)0x00000000)
+
+#define ETH_VLANTagComparison_12Bit                     ((u32)0x00010000)
+#define ETH_VLANTagComparison_16Bit                     ((u32)0x00000000)
+
+#define ETH_MAC_FLAG_TST                                ((u32)0x00000200)              ///< Time stamp trigger flag (on MAC)
+#define ETH_MAC_FLAG_MMCT                               ((u32)0x00000040)              ///< MMC transmit flag
+#define ETH_MAC_FLAG_MMCR                               ((u32)0x00000020)              ///< MMC receive flag
+#define ETH_MAC_FLAG_MMC                                ((u32)0x00000010)              ///< MMC flag (on MAC)
+#define ETH_MAC_FLAG_PMT                                ((u32)0x00000008)              ///< PMT flag (on MAC)
+
+#define ETH_MAC_IT_TST                                  ((u32)0x00000200)              ///< Time stamp trigger interrupt (on MAC)
+#define ETH_MAC_IT_MMCT                                 ((u32)0x00000040)              ///< MMC transmit interrupt
+#define ETH_MAC_IT_MMCR                                 ((u32)0x00000020)              ///< MMC receive interrupt
+#define ETH_MAC_IT_MMC                                  ((u32)0x00000010)              ///< MMC interrupt (on MAC)
+#define ETH_MAC_IT_PMT                                  ((u32)0x00000008)              ///< PMT interrupt (on MAC)
+
+#define ETH_MAC_Address0                                ((u32)0x00000000)
+#define ETH_MAC_Address1                                ((u32)0x00000008)
+#define ETH_MAC_Address2                                ((u32)0x00000010)
+#define ETH_MAC_Address3                                ((u32)0x00000018)
+
+#define ETH_MAC_AddressFilter_SA                        ((u32)0x00000000)
+#define ETH_MAC_AddressFilter_DA                        ((u32)0x00000008)
+
+#define ETH_MAC_AddressMask_Byte6                       ((u32)0x20000000)              ///< Mask MAC Address high reg bits [15:8]
+#define ETH_MAC_AddressMask_Byte5                       ((u32)0x10000000)              ///< Mask MAC Address high reg bits [7:0]
+#define ETH_MAC_AddressMask_Byte4                       ((u32)0x08000000)              ///< Mask MAC Address low reg bits [31:24]
+#define ETH_MAC_AddressMask_Byte3                       ((u32)0x04000000)              ///< Mask MAC Address low reg bits [23:16]
+#define ETH_MAC_AddressMask_Byte2                       ((u32)0x02000000)              ///< Mask MAC Address low reg bits [15:8]
+#define ETH_MAC_AddressMask_Byte1                       ((u32)0x01000000)              ///< Mask MAC Address low reg bits [70]
+
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMA_TDES_LastSegment                        ((u32)0x40000000)              ///< Last Segment
+#define ETH_DMA_TDES_FirstSegment                       ((u32)0x20000000)              ///< First Segment
+
+#define ETH_DMA_TDES_ChecksumByPass                     ((u32)0x00000000)      ///< Checksum engine bypass
+#define ETH_DMA_TDES_ChecksumIPV4Header                 ((u32)0x00400000)      ///< IPv4 header checksum insertion
+#define ETH_DMA_TDES_ChecksumTCPUDPICMPSegment          ((u32)0x00800000)      ///< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present
+#define ETH_DMA_TDES_ChecksumTCPUDPICMPFull             ((u32)0x00C00000)      ///< TCP/UDP/ICMP checksum fully in hardware including pseudo header
+
+#define ETH_DMA_RDES_Buffer1                            ((u32)0x00000000)              ///< DMA Rx Desc Buffer1
+#define ETH_DMA_RDES_Buffer2                            ((u32)0x00000001)              ///< DMA Rx Desc Buffer2
+
+#define ETH_DropTCPIPChecksumErrorFrame_Enable          ((u32)0x00000000)
+#define ETH_DropTCPIPChecksumErrorFrame_Disable         ((u32)0x04000000)
+
+#define ETH_ReceiveStoreForward_Enable                  ((u32)0x02000000)
+#define ETH_ReceiveStoreForward_Disable                 ((u32)0x00000000)
+
+#define ETH_FlushReceivedFrame_Enable                   ((u32)0x00000000)
+#define ETH_FlushReceivedFrame_Disable                  ((u32)0x01000000)
+
+#define ETH_TransmitStoreForward_Enable                 ((u32)0x00200000)
+#define ETH_TransmitStoreForward_Disable                ((u32)0x00000000)
+
+#define ETH_TransmitThresholdControl_64Bytes            ((u32)0x00000000)      ///< threshold level of the MTL Transmit FIFO is 64 Bytes
+#define ETH_TransmitThresholdControl_128Bytes           ((u32)0x00004000)      ///< threshold level of the MTL Transmit FIFO is 128 Bytes
+#define ETH_TransmitThresholdControl_192Bytes           ((u32)0x00008000)      ///< threshold level of the MTL Transmit FIFO is 192 Bytes
+#define ETH_TransmitThresholdControl_256Bytes           ((u32)0x0000C000)      ///< threshold level of the MTL Transmit FIFO is 256 Bytes
+#define ETH_TransmitThresholdControl_40Bytes            ((u32)0x00010000)      ///< threshold level of the MTL Transmit FIFO is 40 Bytes
+#define ETH_TransmitThresholdControl_32Bytes            ((u32)0x00014000)      ///< threshold level of the MTL Transmit FIFO is 32 Bytes
+#define ETH_TransmitThresholdControl_24Bytes            ((u32)0x00018000)      ///< threshold level of the MTL Transmit FIFO is 24 Bytes
+#define ETH_TransmitThresholdControl_16Bytes            ((u32)0x0001C000)      ///< threshold level of the MTL Transmit FIFO is 16 Bytes
+
+#define ETH_ForwardErrorFrames_Enable                   ((u32)0x00000080)
+#define ETH_ForwardErrorFrames_Disable                  ((u32)0x00000000)
+
+#define ETH_ForwardUndersizedGoodFrames_Enable          ((u32)0x00000040)
+#define ETH_ForwardUndersizedGoodFrames_Disable         ((u32)0x00000000)
+
+#define ETH_ReceiveThresholdControl_64Bytes             ((u32)0x00000000)      ///< threshold level of the MTL Receive FIFO is 64 Bytes
+#define ETH_ReceiveThresholdControl_32Bytes             ((u32)0x00000008)      ///< threshold level of the MTL Receive FIFO is 32 Bytes
+#define ETH_ReceiveThresholdControl_96Bytes             ((u32)0x00000010)      ///< threshold level of the MTL Receive FIFO is 96 Bytes
+#define ETH_ReceiveThresholdControl_128Bytes            ((u32)0x00000018)      ///< threshold level of the MTL Receive FIFO is 128 Bytes
+
+#define ETH_SecondFrameOperate_Enable       ((u32)0x00000004)
+#define ETH_SecondFrameOperate_Disable      ((u32)0x00000000)
+
+#define ETH_AddressAlignedBeats_Enable      ((u32)0x02000000)
+#define ETH_AddressAlignedBeats_Disable     ((u32)0x00000000)
+
+#define ETH_FixedBurst_Enable               ((u32)0x00010000)
+#define ETH_FixedBurst_Disable              ((u32)0x00000000)
+
+#define ETH_RxDMABurstLength_1Beat          ((u32)0x00020000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 1
+#define ETH_RxDMABurstLength_2Beat          ((u32)0x00040000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 2
+#define ETH_RxDMABurstLength_4Beat          ((u32)0x00080000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 4
+#define ETH_RxDMABurstLength_8Beat          ((u32)0x00100000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 8
+#define ETH_RxDMABurstLength_16Beat         ((u32)0x00200000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 16
+#define ETH_RxDMABurstLength_32Beat         ((u32)0x00400000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 32
+#define ETH_RxDMABurstLength_4xPBL_4Beat    ((u32)0x01020000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 4
+#define ETH_RxDMABurstLength_4xPBL_8Beat    ((u32)0x01040000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 8
+#define ETH_RxDMABurstLength_4xPBL_16Beat   ((u32)0x01080000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 16
+#define ETH_RxDMABurstLength_4xPBL_32Beat   ((u32)0x01100000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 32
+#define ETH_RxDMABurstLength_4xPBL_64Beat   ((u32)0x01200000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 64
+#define ETH_RxDMABurstLength_4xPBL_128Beat  ((u32)0x01400000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 128
+
+#define ETH_TxDMABurstLength_1Beat          ((u32)0x00000100)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1
+#define ETH_TxDMABurstLength_2Beat          ((u32)0x00000200)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2
+#define ETH_TxDMABurstLength_4Beat          ((u32)0x00000400)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
+#define ETH_TxDMABurstLength_8Beat          ((u32)0x00000800)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
+#define ETH_TxDMABurstLength_16Beat         ((u32)0x00001000)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
+#define ETH_TxDMABurstLength_32Beat         ((u32)0x00002000)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
+#define ETH_TxDMABurstLength_4xPBL_4Beat    ((u32)0x01000100)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
+#define ETH_TxDMABurstLength_4xPBL_8Beat    ((u32)0x01000200)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
+#define ETH_TxDMABurstLength_4xPBL_16Beat   ((u32)0x01000400)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
+#define ETH_TxDMABurstLength_4xPBL_32Beat   ((u32)0x01000800)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
+#define ETH_TxDMABurstLength_4xPBL_64Beat   ((u32)0x01001000)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64
+#define ETH_TxDMABurstLength_4xPBL_128Beat  ((u32)0x01002000)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128
+
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1      ((u32)0x00000000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1      ((u32)0x00004000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1      ((u32)0x00008000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1      ((u32)0x0000C000)
+#define ETH_DMAArbitration_RxPriorTx                ((u32)0x00000002)
+
+#define ETH_DMA_FLAG_TST                    ((u32)0x20000000)              ///< Time-stamp trigger interrupt (on DMA)
+#define ETH_DMA_FLAG_PMT                    ((u32)0x10000000)              ///< PMT interrupt (on DMA)
+#define ETH_DMA_FLAG_MMC                    ((u32)0x08000000)              ///< MMC interrupt (on DMA)
+#define ETH_DMA_FLAG_DataTransferError      ((u32)0x00800000)              ///< Error bits 0-Rx DMA, 1-Tx DMA
+#define ETH_DMA_FLAG_ReadWriteError         ((u32)0x01000000)              ///< Error bits 0-write trnsf, 1-read transfr
+#define ETH_DMA_FLAG_AccessError            ((u32)0x02000000)              ///< Error bits 0-data buffer, 1-desc. access
+#define ETH_DMA_FLAG_NIS                    ((u32)0x00010000)              ///< Normal interrupt summary flag
+#define ETH_DMA_FLAG_AIS                    ((u32)0x00008000)              ///< Abnormal interrupt summary flag
+#define ETH_DMA_FLAG_ER                     ((u32)0x00004000)              ///< Early receive flag
+#define ETH_DMA_FLAG_FBE                    ((u32)0x00002000)              ///< Fatal bus error flag
+#define ETH_DMA_FLAG_ET                     ((u32)0x00000400)              ///< Early transmit flag
+#define ETH_DMA_FLAG_RWT                    ((u32)0x00000200)              ///< Receive watchdog timeout flag
+#define ETH_DMA_FLAG_RPS                    ((u32)0x00000100)              ///< Receive process stopped flag
+#define ETH_DMA_FLAG_RBU                    ((u32)0x00000080)              ///< Receive buffer unavailable flag
+#define ETH_DMA_FLAG_R                      ((u32)0x00000040)              ///< Receive flag
+#define ETH_DMA_FLAG_TU                     ((u32)0x00000020)              ///< Underflow flag
+#define ETH_DMA_FLAG_RO                     ((u32)0x00000010)              ///< Overflow flag
+#define ETH_DMA_FLAG_TJT                    ((u32)0x00000008)              ///< Transmit jabber timeout flag
+#define ETH_DMA_FLAG_TBU                    ((u32)0x00000004)              ///< Transmit buffer unavailable flag
+#define ETH_DMA_FLAG_TPS                    ((u32)0x00000002)              ///< Transmit process stopped flag
+#define ETH_DMA_FLAG_T                      ((u32)0x00000001)              ///< Transmit flag
+
+#define ETH_DMA_IT_TST                      ((u32)0x20000000)              ///< Time-stamp trigger interrupt (on DMA)
+#define ETH_DMA_IT_PMT                      ((u32)0x10000000)              ///< PMT interrupt (on DMA)
+#define ETH_DMA_IT_MMC                      ((u32)0x08000000)              ///< MMC interrupt (on DMA)
+#define ETH_DMA_IT_NIS                      ((u32)0x00010000)              ///< Normal interrupt summary
+#define ETH_DMA_IT_AIS                      ((u32)0x00008000)              ///< Abnormal interrupt summary
+#define ETH_DMA_IT_ER                       ((u32)0x00004000)              ///< Early receive interrupt
+#define ETH_DMA_IT_FBE                      ((u32)0x00002000)              ///< Fatal bus error interrupt
+#define ETH_DMA_IT_ET                       ((u32)0x00000400)              ///< Early transmit interrupt
+#define ETH_DMA_IT_RWT                      ((u32)0x00000200)              ///< Receive watchdog timeout interrupt
+#define ETH_DMA_IT_RPS                      ((u32)0x00000100)              ///< Receive process stopped interrupt
+#define ETH_DMA_IT_RBU                      ((u32)0x00000080)              ///< Receive buffer unavailable interrupt
+#define ETH_DMA_IT_R                        ((u32)0x00000040)              ///< Receive interrupt
+#define ETH_DMA_IT_TU                       ((u32)0x00000020)              ///< Underflow interrupt
+#define ETH_DMA_IT_RO                       ((u32)0x00000010)              ///< Overflow interrupt
+#define ETH_DMA_IT_TJT                      ((u32)0x00000008)              ///< Transmit jabber timeout interrupt
+#define ETH_DMA_IT_TBU                      ((u32)0x00000004)              ///< Transmit buffer unavailable interrupt
+#define ETH_DMA_IT_TPS                      ((u32)0x00000002)              ///< Transmit process stopped interrupt
+#define ETH_DMA_IT_T                        ((u32)0x00000001)              ///< Transmit interrupt
+
+#define ETH_DMA_TransmitProcess_Stopped     ((u32)0x00000000)              ///< Stopped - Reset or Stop Tx Command issued
+#define ETH_DMA_TransmitProcess_Fetching    ((u32)0x00100000)              ///< Running - fetching the Tx descriptor
+#define ETH_DMA_TransmitProcess_Waiting     ((u32)0x00200000)              ///< Running - waiting for status
+#define ETH_DMA_TransmitProcess_Reading     ((u32)0x00300000)              ///< Running - reading the data from host memory
+#define ETH_DMA_TransmitProcess_Suspended   ((u32)0x00600000)              ///< Suspended - Tx Descriptor unavailable
+#define ETH_DMA_TransmitProcess_Closing     ((u32)0x00700000)              ///< Running - closing Rx descriptor
+
+#define ETH_DMA_ReceiveProcess_Stopped      ((u32)0x00000000)              ///< Stopped - Reset or Stop Rx Command issued
+#define ETH_DMA_ReceiveProcess_Fetching     ((u32)0x00020000)              ///< Running - fetching the Rx descriptor
+#define ETH_DMA_ReceiveProcess_Waiting      ((u32)0x00060000)              ///< Running - waiting for packet
+#define ETH_DMA_ReceiveProcess_Suspended    ((u32)0x00080000)              ///< Suspended - Rx Descriptor unavailable
+#define ETH_DMA_ReceiveProcess_Closing      ((u32)0x000A0000)              ///< Running - closing descriptor
+#define ETH_DMA_ReceiveProcess_Queuing      ((u32)0x000E0000)              ///< Running - queuing the receive frame into host memory
+
+#define ETH_DMA_Overflow_RxFIFOCounter      ((u32)0x10000000)              ///< Overflow bit for FIFO overflow counter
+#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000)              ///< Overflow bit for missed frame counter
+
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_PMT_FLAG_WUFFRPR                ((u32)0x80000000)              ///< Wake-Up Frame Filter Register Pointer Reset
+#define ETH_PMT_FLAG_WUFR                   ((u32)0x00000040)              ///< Wake-Up Frame Received
+#define ETH_PMT_FLAG_MPR                    ((u32)0x00000020)              ///< Magic Packet Received
+
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMC_IT_TGF                      ((u32)0x00200000)              ///< When Tx good frame counter reaches half the maximum value
+#define ETH_MMC_IT_TGFMSC                   ((u32)0x00008000)              ///< When Tx good multi col counter reaches half the maximum value
+#define ETH_MMC_IT_TGFSC                    ((u32)0x00004000)              ///< When Tx good single col counter reaches half the maximum value
+
+#define ETH_MMC_IT_RGUF                     ((u32)0x10020000)              ///< When Rx good unicast frames counter reaches half the maximum value
+#define ETH_MMC_IT_RFAE                     ((u32)0x10000040)              ///< When Rx alignment error counter reaches half the maximum value
+#define ETH_MMC_IT_RFCE                     ((u32)0x10000020)              ///< When Rx crc error counter reaches half the maximum value
+
+#define ETH_MMCCR                           ((u32)0x00000100)              ///< MMC CR register
+#define ETH_MMCRIR                          ((u32)0x00000104)              ///< MMC RIR register
+#define ETH_MMCTIR                          ((u32)0x00000108)              ///< MMC TIR register
+#define ETH_MMCRIMR                         ((u32)0x0000010C)              ///< MMC RIMR register
+#define ETH_MMCTIMR                         ((u32)0x00000110)              ///< MMC TIMR register
+#define ETH_MMCTGFSCCR                      ((u32)0x0000014C)              ///< MMC TGFSCCR register
+#define ETH_MMCTGFMSCCR                     ((u32)0x00000150)              ///< MMC TGFMSCCR register
+#define ETH_MMCTGFCR                        ((u32)0x00000168)              ///< MMC TGFCR register
+#define ETH_MMCRFCECR                       ((u32)0x00000194)              ///< MMC RFCECR register
+#define ETH_MMCRFAECR                       ((u32)0x00000198)              ///< MMC RFAECR register
+#define ETH_MMCRGUFCR                       ((u32)0x000001C4)              ///< MMC RGUFCR register
+
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_PTP_FineUpdate                  ((u32)0x00000001)              ///< Fine Update method
+#define ETH_PTP_CoarseUpdate                ((u32)0x00000000)              ///< Coarse Update method
+
+#define ETH_PTP_FLAG_TSARU                  ((u32)0x00000020)              ///< Addend Register Update
+#define ETH_PTP_FLAG_TSITE                  ((u32)0x00000010)              ///< Time Stamp Interrupt Trigger
+#define ETH_PTP_FLAG_TSSTU                  ((u32)0x00000008)              ///< Time Stamp Update
+#define ETH_PTP_FLAG_TSSTI                  ((u32)0x00000004)              ///< Time Stamp Initialize
+
+#define ETH_PTP_FLAG_TSTTR                  ((u32)0x10000002)              ///< Time stamp target time reached
+#define ETH_PTP_FLAG_TSSO                   ((u32)0x10000001)              ///< Time stamp seconds overflow
+
+#define ETH_PTP_PositiveTime                ((u32)0x00000000)              ///< Positive time value
+#define ETH_PTP_NegativeTime                ((u32)0x80000000)              ///< Negative time value
+
+#define ETH_PTPTSCR                         ((u32)0x00000700)              ///< PTP TSCR register
+#define ETH_PTPSSIR                         ((u32)0x00000704)              ///< PTP SSIR register
+#define ETH_PTPTSHR                         ((u32)0x00000708)              ///< PTP TSHR register
+#define ETH_PTPTSLR                         ((u32)0x0000070C)              ///< PTP TSLR register
+#define ETH_PTPTSHUR                        ((u32)0x00000710)              ///< PTP TSHUR register
+#define ETH_PTPTSLUR                        ((u32)0x00000714)              ///< PTP TSLUR register
+#define ETH_PTPTSAR                         ((u32)0x00000718)              ///< PTP TSAR register
+#define ETH_PTPTTHR                         ((u32)0x0000071C)              ///< PTP TTHR register
+#define ETH_PTPTTLR                         ((u32)0x00000720)              ///< PTP TTLR register
+
+#define ETH_PTPTSSR                         ((u32)0x00000728)              ///< PTP TSSR register
+
+#define ETH_PTP_OrdinaryClock               ((u32)0x00000000)              ///< Ordinary Clock
+#define ETH_PTP_BoundaryClock               ((u32)0x00010000)              ///< Boundary Clock
+#define ETH_PTP_EndToEndTransparentClock    ((u32)0x00020000)              ///< End To End Transparent Clock
+#define ETH_PTP_PeerToPeerTransparentClock  ((u32)0x00030000)              ///< Peer To Peer Transparent Clock
+
+#define ETH_PTP_SnapshotMasterMessage               ((u32)0x00008000)      ///< Time stamp snapshot for message relevant to master enable
+#define ETH_PTP_SnapshotEventMessage                ((u32)0x00004000)      ///< Time stamp snapshot for event message enable
+#define ETH_PTP_SnapshotIPV4Frames                  ((u32)0x00002000)      ///< Time stamp snapshot for IPv4 frames enable
+#define ETH_PTP_SnapshotIPV6Frames                  ((u32)0x00001000)      ///< Time stamp snapshot for IPv6 frames enable
+#define ETH_PTP_SnapshotPTPOverEthernetFrames       ((u32)0x00000800)      ///< Time stamp snapshot for PTP over ethernet frames enable
+#define ETH_PTP_SnapshotAllReceivedFrames           ((u32)0x00000100)      ///< Time stamp snapshot for all received frames enable
+
+#define ETH_MAC_ADDR_HBASE      (ETH_BASE + 0x40)                               ///< ETHERNET MAC address high offset
+#define ETH_MAC_ADDR_LBASE      (ETH_BASE + 0x44)                               ///< ETHERNET MAC address low offset
+
+#define MACMIIAR_CR_MASK    ((u32)0xFFFFFFE3)
+
+#define MACCR_CLEAR_MASK    ((u32)0xFF20810F)
+#define MACFCR_CLEAR_MASK   ((u32)0x0000FF41)
+#define DMAOMR_CLEAR_MASK   ((u32)0xF8DE3F23)
+
+
+
+GLOBAL __IO ETH_DMADESCTypeDef*  DMATxDescToSet;
+GLOBAL __IO ETH_DMADESCTypeDef*  DMARxDescToGet;
+
+GLOBAL ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor;
+GLOBAL __IO ETH_DMA_Rx_Frame_infos* DMA_RX_FRAME_infos;
+GLOBAL __IO u32 Frame_Rx_index;
+
+#undef GLOBAL
+
+void ETH_DeInit(void);
+void ETH_StructInit(ETH_InitTypeDef* ptr);
+u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr);
+void ETH_Start(void);
+void ETH_Stop(void);
+void ETH_MACTransmissionCmd(FunctionalState sta);
+void ETH_MACReceptionCmd(FunctionalState sta);
+FlagStatus ETH_GetFlowControlBusyStatus(void);
+void ETH_InitiatePauseControlFrame(void);
+void ETH_BackPressureActivationCmd(FunctionalState sta);
+void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr);
+void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr);
+void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta);
+void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta);
+void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte);
+FrameTypeDef ETH_Get_Received_Frame(void);
+FrameTypeDef ETH_Get_Received_Frame_interrupt(void);
+u32 ETH_Prepare_Transmit_Descriptors(u16 len);
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt);
+u32 ETH_CheckFrameReceived(void);
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt);
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag);
+u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc);
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc);
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val);
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val);
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size);
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag);
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc);
+u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc);
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
+u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf);
+u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc);
+void ETH_SoftwareReset(void);
+FlagStatus ETH_GetSoftwareResetStatus(void);
+FlagStatus ETH_GetDMAFlagStatus(u32 flag);
+void ETH_DMAClearFlag(u32 flag);
+void ETH_DMAITConfig(u32 it, FunctionalState sta);
+ITStatus ETH_GetDMAITStatus(u32 it);
+void ETH_DMAClearITPendingBit(u32 it);
+u32 ETH_GetTransmitProcessState(void);
+u32 ETH_GetReceiveProcessState(void);
+void ETH_FlushTransmitFIFO(void);
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
+void ETH_DMATransmissionCmd(FunctionalState sta);
+void ETH_DMAReceptionCmd(FunctionalState sta);
+FlagStatus ETH_GetDMAOverflowStatus(u32 val);
+u32 ETH_GetRxOverflowMissedFrameCounter(void);
+u32 ETH_GetBufferUnavailableMissedFrameCounter(void);
+u32 ETH_GetCurrentTxDescStartAddress(void);
+u32 ETH_GetCurrentRxDescStartAddress(void);
+u32 ETH_GetCurrentTxBufferAddress(void);
+u32 ETH_GetCurrentRxBufferAddress(void);
+void ETH_ResumeDMATransmission(void);
+void ETH_ResumeDMAReception(void);
+void ETH_SetReceiveWatchdogTimer(u8 val);
+u16 ETH_ReadPHYRegister(u16 addr, u16 reg);
+u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val);
+u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta);
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
+void ETH_SetWakeUpFrameFilterRegister(u32* buf);
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta);
+FlagStatus ETH_GetPMTFlagStatus(u32 flag);
+void ETH_WakeUpFrameDetectionCmd(FunctionalState sta);
+void ETH_MagicPacketDetectionCmd(FunctionalState sta);
+void ETH_PowerDownCmd(FunctionalState sta);
+void ETH_MMCCounterFullPreset(void);
+void ETH_MMCCounterHalfPreset(void);
+void ETH_MMCCounterFreezeCmd(FunctionalState sta);
+void ETH_MMCResetOnReadCmd(FunctionalState sta);
+void ETH_MMCCounterRolloverCmd(FunctionalState sta);
+void ETH_MMCCountersReset(void);
+void ETH_MMCITConfig(u32 it, FunctionalState sta);
+ITStatus ETH_GetMMCITStatus(u32 it);
+u32 ETH_GetMMCRegister(u32 reg);
+
+/// @}
+
+/// @}
+
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_ETH_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h
new file mode 100644
index 000000000..f00e17e63
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h
@@ -0,0 +1,68 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_eth_conf.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE hal_eth_conf.h EXAMPLES.
+/// ////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT  MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __HAL_ETH_CONF_H
+#define __HAL_ETH_CONF_H
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ETH_HAL
+/// @brief ETH HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup ETH_Exported_Types
+/// @{
+
+
+// #define USE_ENHANCED_DMA_DESCRIPTORS
+// #define CUSTOM_DRIVER_BUFFERS_CONFIG
+#define DP83848
+
+#ifdef CUSTOM_DRIVER_BUFFERS_CONFIG
+#define ETH_RX_BUF_SIZE     ETH_MAX_PACKET_SIZE
+#define ETH_TX_BUF_SIZE     ETH_MAX_PACKET_SIZE
+#define ETH_RX_BUF_NUM      4
+#define ETH_TX_BUF_NUM      4
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+#if defined(DP83848)
+#define PHY_SR                  ((u16)0x10)
+#define PHY_SR_LINKSTATUS       ((u16)0x0001)
+#define PHY_SPEED_STATUS        ((u16)0x0002)
+#define PHY_DUPLEX_STATUS       ((u16)0x0004)
+
+#define PHY_MICR                ((u16)0x11)
+#define PHY_MICR_INT_EN         ((u16)0x0002)
+#define PHY_MICR_INT_OE         ((u16)0x0001)
+
+#define PHY_MISR                ((u16)0x12)
+#define PHY_MISR_LINK_INT_EN    ((u16)0x0020)
+#define PHY_LINK_STATUS         ((u16)0x2000)
+#endif
+
+/// @}
+
+/// @}
+
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_ETH_CONF_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h
new file mode 100644
index 000000000..a90daff9c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h
@@ -0,0 +1,181 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_exti.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_EXTI_H
+#define __HAL_EXTI_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_exti.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup EXTI_HAL
+/// @brief EXTI HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup EXTI_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  EXTI mode enumeration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    EXTI_Mode_Interrupt = 0x00,                                                 ///< EXTI interrupt mode
+    EXTI_Mode_Event     = 0x04                                                  ///< EXTI event mode
+} EXTIMode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  EXTI Trigger enumeration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    EXTI_Trigger_Rising = 0x08,                                                 ///< EXTI rising edge triggering
+    EXTI_Trigger_Falling = 0x0C,                                                ///< EXTI falling edge triggering
+    EXTI_Trigger_Rising_Falling = 0x10                                          ///< EXTI rising and falling edge triggers
+} EXTITrigger_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  EXTI Init Structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u32 EXTI_Line;                                                              ///< Specifies the EXTI lines to be enabled or disabled.
+    ///< This parameter can be any combination of @ref EXTI_Lines
+    EXTIMode_TypeDef EXTI_Mode;                                                 ///< Specifies the mode for the EXTI lines.
+    ///< This parameter can be a value of @ref EXTIMode_TypeDef
+    EXTITrigger_TypeDef EXTI_Trigger;                                           ///< Specifies the trigger signal active edge for the EXTI lines.
+    ///< This parameter can be a value of @ref EXTIMode_TypeDef
+    FunctionalState EXTI_LineCmd;                                               ///< Specifies the new state of the selected EXTI lines.
+    ///< This parameter can be set either to ENABLE or DISABLE
+} EXTI_InitTypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup EXTI_Exported_Constants
+/// @{
+
+
+
+#define EXTI_LineNone   ((u32)0x0000000)                                        ///< No interrupt selected
+#define EXTI_Line0      ((u32)0x0000001)                                        ///< External interrupt line 0
+#define EXTI_Line1      ((u32)0x0000002)                                        ///< External interrupt line 1
+#define EXTI_Line2      ((u32)0x0000004)                                        ///< External interrupt line 2
+#define EXTI_Line3      ((u32)0x0000008)                                        ///< External interrupt line 3
+#define EXTI_Line4      ((u32)0x0000010)                                        ///< External interrupt line 4
+#define EXTI_Line5      ((u32)0x0000020)                                        ///< External interrupt line 5
+#define EXTI_Line6      ((u32)0x0000040)                                        ///< External interrupt line 6
+#define EXTI_Line7      ((u32)0x0000080)                                        ///< External interrupt line 7
+#define EXTI_Line8      ((u32)0x0000100)                                        ///< External interrupt line 8
+#define EXTI_Line9      ((u32)0x0000200)                                        ///< External interrupt line 9
+#define EXTI_Line10     ((u32)0x0000400)                                        ///< External interrupt line 10
+#define EXTI_Line11     ((u32)0x0000800)                                        ///< External interrupt line 11
+#define EXTI_Line12     ((u32)0x0001000)                                        ///< External interrupt line 12
+#define EXTI_Line13     ((u32)0x0002000)                                        ///< External interrupt line 13
+#define EXTI_Line14     ((u32)0x0004000)                                        ///< External interrupt line 14
+#define EXTI_Line15     ((u32)0x0008000)                                        ///< External interrupt line 15
+#define EXTI_Line16     ((u32)0x0010000)                                        ///< External interrupt line 16 Connected to the PVD Output
+#define EXTI_Line17     ((u32)0x0020000)                                        ///< External interrupt line 17 Connected to the RTC Alarm event
+#define EXTI_Line18     ((u32)0x0040000)                                        ///< External interrupt line 18 Connected to the USB Wakeup from suspend event
+#define EXTI_Line19     ((u32)0x0080000)                                        ///< External interrupt line 19
+#define EXTI_Line20     ((u32)0x0100000)                                        ///< External interrupt line 20
+#define EXTI_Line21     ((u32)0x0200000)                                        ///< External interrupt line 21
+#define EXTI_Line22     ((u32)0x0400000)                                        ///< External interrupt line 22
+#define EXTI_Line23     ((u32)0x0800000)                                        ///< External interrupt line 23
+#define EXTI_Line24     ((u32)0x1000000)                                        ///< External interrupt line 24
+
+#define EXTI_PortSourceGPIOA (0x00U)
+#define EXTI_PortSourceGPIOB (0x01U)
+#define EXTI_PortSourceGPIOC (0x02U)
+#define EXTI_PortSourceGPIOD (0x03U)
+#define EXTI_PortSourceGPIOE (0x04U)
+#define EXTI_PortSourceGPIOF (0x05U)
+
+#define EXTI_PinSource0     (0x00U)
+#define EXTI_PinSource1     (0x01U)
+#define EXTI_PinSource2     (0x02U)
+#define EXTI_PinSource3     (0x03U)
+#define EXTI_PinSource4     (0x04U)
+#define EXTI_PinSource5     (0x05U)
+#define EXTI_PinSource6     (0x06U)
+#define EXTI_PinSource7     (0x07U)
+#define EXTI_PinSource8     (0x08U)
+#define EXTI_PinSource9     (0x09U)
+#define EXTI_PinSource10    (0x0AU)
+#define EXTI_PinSource11    (0x0BU)
+#define EXTI_PinSource12    (0x0CU)
+#define EXTI_PinSource13    (0x0DU)
+#define EXTI_PinSource14    (0x0EU)
+#define EXTI_PinSource15    (0x0FU)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup EXTI_Exported_Variables
+/// @{
+
+#ifdef _HAL_EXTI_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup EXTI_Exported_Functions
+/// @{
+
+FlagStatus EXTI_GetFlagStatus(u32 line);
+ITStatus   EXTI_GetITStatus(u32 line);
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* init_struct);
+void EXTI_StructInit(EXTI_InitTypeDef* init_struct);
+void EXTI_GenerateSWInterrupt(u32 line);
+void EXTI_ClearFlag(u32 line);
+void EXTI_ClearITPendingBit(u32 line);
+void exEXTI_LineDisable(u32 line);
+u32  exEXTI_GetAllFlagStatus(void);
+
+
+void EXTI_MemoryRemapConfig(u32 memory_remap);
+void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source);
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_EXTI_H
+////////////////////////////////////////////////////////////////////////////////
+
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h
new file mode 100644
index 000000000..ee313dee7
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h
@@ -0,0 +1,230 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_flash.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE FLASH
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_FLASH_H
+#define __HAL_FLASH_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_flash.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FLASH_HAL
+/// @brief FLASH HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FLASH_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  FLASH Status
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    FLASH_BUSY = 1,                                                             ///< FLASH busy status
+    FLASH_ERROR_PG,                                                             ///< FLASH programming error status
+    FLASH_ERROR_WRP,                                                            ///< FLASH write protection error status
+    FLASH_COMPLETE,                                                             ///< FLASH end of operation status
+    FLASH_TIMEOUT                                                               ///< FLASH Last operation timed out status
+} FLASH_Status;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  FLASH Latency
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    FLASH_Latency_0 = FLASH_ACR_LATENCY_0,                                      ///< FLASH Zero Latency cycle
+    FLASH_Latency_1 = FLASH_ACR_LATENCY_1,                                      ///< FLASH One Latency cycle
+    FLASH_Latency_2 = FLASH_ACR_LATENCY_2,                                      ///< FLASH Two Latency cycles
+    FLASH_Latency_3 = FLASH_ACR_LATENCY_3                                       ///< FLASH Three Latency cycles
+} FLASH_Latency_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Half_Cycle_Enable_Disable
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    FLASH_HalfCycleAccess_Enable  = FLASH_ACR_HLFCYA,                           ///< FLASH Half Cycle Enable
+    FLASH_HalfCycleAccess_Disable = (s32)~FLASH_ACR_HLFCYA                              ///< FLASH Half Cycle Disable
+} FLASH_HalfCycleAccess_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Prefetch_Buffer_Enable_Disable
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    FLASH_PrefetchBuffer_Enable  = FLASH_ACR_PRFTBE,                            ///< FLASH Prefetch Buffer Enable
+    FLASH_PrefetchBuffer_Disable = (s32)~FLASH_ACR_PRFTBE                           ///< FLASH Prefetch Buffer Disable
+} FLASH_PrefetchBuffer_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Option_Bytes_IWatchdog
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    OB_IWDG_SW = 0x0001,                                                        ///< Software IWDG selected
+    OB_IWDG_HW = 0x0000                                                         ///< Hardware IWDG selected
+} OB_IWDG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Option_Bytes_nRST_STOP
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    OB_STOP_NoRST = 0x0002,                                                     ///< No reset generated when entering in STOP
+    OB_STOP_RST   = 0x0000                                                      ///< Reset generated when entering in STOP
+} OB_STOP_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Option_Bytes_nRST_STDBY
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    OB_STDBY_NoRST = 0x0004,                                                    ///< No reset generated when entering in STANDBY
+    OB_STDBY_RST   = 0x0000                                                     ///< Reset generated when entering in STANDBY
+} OB_STDBY_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  FLASH_Interrupts
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    FLASH_IT_ERROR = FLASH_CR_ERRIE,                                            ///< FPEC error interrupt source
+    FLASH_IT_EOP   = FLASH_CR_EOPIE                                             ///< End of FLASH Operation Interrupt source
+} FLASH_IT_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  FLASH_Flags
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    FLASH_FLAG_EOP      = FLASH_SR_EOP,                                         ///< FLASH End of Operation flag
+    FLASH_FLAG_PGERR    = FLASH_SR_PGERR,                                       ///< FLASH Program error flag
+    FLASH_FLAG_WRPRTERR = FLASH_SR_WRPRTERR,                                    ///< FLASH Write protected error flag
+    FLASH_FLAG_BSY      = FLASH_SR_BUSY,                                        ///< FLASH Busy flag
+    FLASH_FLAG_OPTERR   = FLASH_OBR_OPTERR                                      ///< FLASH Option Byte error flag
+} FLASH_FLAG_TypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FLASH_Exported_Constants
+/// @{
+
+
+#define RDP_Key ((u16)0x00A5)
+#define FLASH_KEY1 ((u32)0x45670123)
+#define FLASH_KEY2 ((u32)0xCDEF89AB)
+#define EraseTimeout ((u32)0x00000FFF)
+#define ProgramTimeout ((u32)0x0000000F)
+
+#define FLASH_WRProt_Pages0to3      ((u32)0x00000001)  ///< Write protection of page 0 to 3
+#define FLASH_WRProt_Pages4to7      ((u32)0x00000002)  ///< Write protection of page 4 to 7
+#define FLASH_WRProt_Pages8to11     ((u32)0x00000004)  ///< Write protection of page 8 to 11
+#define FLASH_WRProt_Pages12to15    ((u32)0x00000008)  ///< Write protection of page 12 to 15
+#define FLASH_WRProt_Pages16to19    ((u32)0x00000010)  ///< Write protection of page 16 to 19
+#define FLASH_WRProt_Pages20to23    ((u32)0x00000020)  ///< Write protection of page 20 to 23
+#define FLASH_WRProt_Pages24to27    ((u32)0x00000040)  ///< Write protection of page 24 to 27
+#define FLASH_WRProt_Pages28to31    ((u32)0x00000080)  ///< Write protection of page 28 to 31
+#define FLASH_WRProt_Pages32to35    ((u32)0x00000100)  ///< Write protection of page 32 to 35
+#define FLASH_WRProt_Pages36to39    ((u32)0x00000200)  ///< Write protection of page 36 to 39
+#define FLASH_WRProt_Pages40to43    ((u32)0x00000400)  ///< Write protection of page 40 to 43
+#define FLASH_WRProt_Pages44to47    ((u32)0x00000800)  ///< Write protection of page 44 to 47
+#define FLASH_WRProt_Pages48to51    ((u32)0x00001000)  ///< Write protection of page 48 to 51
+#define FLASH_WRProt_Pages52to55    ((u32)0x00002000)  ///< Write protection of page 52 to 55
+#define FLASH_WRProt_Pages56to59    ((u32)0x00004000)  ///< Write protection of page 56 to 59
+#define FLASH_WRProt_Pages60to63    ((u32)0x00008000)  ///< Write protection of page 60 to 63
+#define FLASH_WRProt_Pages64to67    ((u32)0x00010000)  ///< Write protection of page 64 to 67
+#define FLASH_WRProt_Pages68to71    ((u32)0x00020000)  ///< Write protection of page 68 to 71
+#define FLASH_WRProt_Pages72to75    ((u32)0x00040000)  ///< Write protection of page 72 to 75
+#define FLASH_WRProt_Pages76to79    ((u32)0x00080000)  ///< Write protection of page 76 to 79
+#define FLASH_WRProt_Pages80to83    ((u32)0x00100000)  ///< Write protection of page 80 to 83
+#define FLASH_WRProt_Pages84to87    ((u32)0x00200000)  ///< Write protection of page 84 to 87
+#define FLASH_WRProt_Pages88to91    ((u32)0x00400000)  ///< Write protection of page 88 to 91
+#define FLASH_WRProt_Pages92to95    ((u32)0x00800000)  ///< Write protection of page 92 to 95
+#define FLASH_WRProt_Pages96to99    ((u32)0x01000000)  ///< Write protection of page 96 to 99
+#define FLASH_WRProt_Pages100to103  ((u32)0x02000000)  ///< Write protection of page 100 to 103
+#define FLASH_WRProt_Pages104to107  ((u32)0x04000000)  ///< Write protection of page 104 to 107
+#define FLASH_WRProt_Pages108to111  ((u32)0x08000000)  ///< Write protection of page 108 to 111
+#define FLASH_WRProt_Pages112to115  ((u32)0x10000000)  ///< Write protection of page 112 to 115
+#define FLASH_WRProt_Pages116to119  ((u32)0x20000000)  ///< Write protection of page 115 to 119
+#define FLASH_WRProt_Pages120to123  ((u32)0x40000000)  ///< Write protection of page 120 to 123
+#define FLASH_WRProt_Pages124to127  ((u32)0x80000000)  ///< Write protection of page 124 to 127
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FLASH_Exported_Variables
+/// @{
+
+#ifdef _HAL_FLASH_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FLASH_Exported_Functions
+/// @{
+void  FLASH_SetLatency(FLASH_Latency_TypeDef latency);
+void  FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access);
+void  FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer);
+void  FLASH_Unlock(void);
+void  FLASH_Lock(void);
+void  FLASH_OPTB_Enable(void);
+void  FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state);
+void  FLASH_ClearFlag(u16 flag);
+void  exFLASH_EraseEE(u32 page_address);
+void  exFLASH_ProgramEE(u16* buf, u32 address, u16 len);
+void  exFLASH_WriteEE(u16* buf, u32 page_address, u16 len);
+void* exFLASH_Locate(u32 page_address, u16 len);
+void* exFLASH_ReadEE(u32 page_address, u16 len);
+
+u8  exFLASH_FindEmpty(u16* ptr, u16 len);
+u32 FLASH_GetUserOptionByte(void);
+u32 FLASH_GetWriteProtectionOptionByte(void);
+
+FLASH_Status FLASH_ErasePage(u32 page_address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_EraseProtect(void);
+FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data);
+FLASH_Status FLASH_ProgramWord(u32 address, u32 data);
+FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data);
+FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data);
+FLASH_Status FLASH_ProgramProtect(u32 address, u16 data);
+FLASH_Status FLASH_EnableWriteProtection(u32 page);
+FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef ob_standby);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(u32 time_out);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState state);
+FlagStatus   FLASH_GetPrefetchBufferStatus(void);
+FlagStatus   FLASH_GetFlagStatus(u16 flag);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_FLASH_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h
new file mode 100644
index 000000000..dbfe38166
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h
@@ -0,0 +1,147 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_fsmc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SDIO
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_FSMC_H
+#define __HAL_FSMC_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_fsmc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FSMC_HAL
+/// @brief FSMC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup FSMC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC_interrupts_define
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+
+// Timing parameter configuration register set selection register set0 register set1 register set2
+
+#define FSMC_TimingRegSelect_0    ((u32)0x00000000)
+#define FSMC_TimingRegSelect_1    ((u32)0x00000100)
+#define FSMC_TimingRegSelect_2    ((u32)0x00000200)
+
+// Capacity of external device
+#define FSMC_MemSize_None   ((u32)0x00000000)
+#define FSMC_MemSize_64KB   ((u32)0x00000001)
+#define FSMC_MemSize_128KB  ((u32)0x00000002)
+#define FSMC_MemSize_256KB  ((u32)0x00000002)
+#define FSMC_MemSize_512KB  ((u32)0x00000004)
+#define FSMC_MemSize_1MB    ((u32)0x00000005)
+#define FSMC_MemSize_2MB    ((u32)0x00000006)
+#define FSMC_MemSize_4MB    ((u32)0x00000007)
+#define FSMC_MemSize_8MB    ((u32)0x00000008)
+#define FSMC_MemSize_16MB   ((u32)0x00000009)
+#define FSMC_MemSize_32MB   ((u32)0x0000000A)
+#define FSMC_MemSize_64MB   ((u32)0x0000000B)
+#define FSMC_MemSize_128MB  ((u32)0x0000000C)
+#define FSMC_MemSize_256MB  ((u32)0x0000000D)
+#define FSMC_MemSize_512MB  ((u32)0x0000000E)
+#define FSMC_MemSize_1GB    ((u32)0x0000000F)
+#define FSMC_MemSize_2GB    ((u32)0x00000010)
+#define FSMC_MemSize_4GB    ((u32)0x00000011)
+
+
+// Memory data bus bit width setting
+typedef enum {
+    FSMC_DataWidth_16bits      = (0x0000), //16bits
+    FSMC_DataWidth_32bits      = (0x0001), //32bits
+    FSMC_DataWidth_64bits      = (0x0002), //64bits
+    FSMC_DataWidth_128bits     = (0x0003), //128bits
+    FSMC_DataWidth_8bits       = (0x0004), //8bits
+} FSMC_NORSRAM_DataWidth_TypeDef;
+
+typedef enum {
+    FSMC_NORSRAM_BANK0 = 0,
+    FSMC_NORSRAM_BANK1 = 1,
+    FSMC_NORSRAM_BANK2 = 2,
+} FSMC_NORSRAM_BANK_TypeDef;
+
+typedef struct {
+    u32 FSMC_SMReadPipe;                                                        //sm_read_pipe[1:0] The cycle of latching read data, that is, the cycle when ready_resp is pulled high
+
+    u32 FSMC_ReadyMode;                                                         //Select whether the hready_resp signal comes from the FSMC IP internal or external DEVICE, only for writing and reading external DEVICE operations.
+    //0: Internal FSMC 1: External DEVICE (ie from FSMC_NWAIT)
+    u32 FSMC_WritePeriod;                                                       //Write cycle
+
+    u32 FSMC_WriteHoldTime;                                                     //Address/data hold time during write operation
+
+    u32 FSMC_AddrSetTime;                                                       //Address establishment time
+
+    u32 FSMC_ReadPeriod;                                                        //Read cycle
+
+    FSMC_NORSRAM_DataWidth_TypeDef FSMC_DataWidth;
+
+} FSMC_NORSRAM_Bank_InitTypeDef;
+
+typedef struct {
+    u32 FSMC_Mode;
+    u32 FSMC_TimingRegSelect;
+    u32 FSMC_MemSize;
+    u32 FSMC_MemType;
+    u32 FSMC_AddrDataMode;
+} FSMC_InitTypeDef;
+
+
+#define FSMC_MemType_SDRAM          ((u32)0x0<<5)
+#define FSMC_MemType_NorSRAM        ((u32)0x1<<5)
+#define FSMC_MemType_FLASH          ((u32)0x2<<5)
+#define FSMC_MemType_RESERVED       ((u32)0x3<<5)
+//SYSCFG_CFGR1
+#define FSMC_Mode_6800              ((u32)0x40000000)
+#define FSMC_Mode_8080              ((u32)0x20000000)
+#define FSMC_Mode_NorFlash          ((u32)0x00000000)
+
+#define FSMC_AddrDataMUX            ((u32)0x00000000)
+#define FSMC_AddrDataDeMUX          ((u32)0x10000000)
+
+
+
+
+void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct);
+void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct);
+void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct);
+void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank);
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_FSMC_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h
new file mode 100644
index 000000000..b28afd839
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h
@@ -0,0 +1,198 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_gpio.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_GPIO_H
+#define __HAL_GPIO_H
+
+// Files includes
+#include "types.h"
+#include "reg_gpio.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_HAL
+/// @brief GPIO HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Output Maximum frequency selection
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    GPIO_Speed_50MHz = 1,  ///< Maximum speed is 50MHz
+    GPIO_Speed_20MHz,      ///< Maximum speed is 20MHz
+    GPIO_Speed_10MHz       ///< Maximum speed is 10MHz
+} GPIOSpeed_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configuration Mode enumeration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    GPIO_Mode_AIN       = 0x00,  ///< Analog input
+    GPIO_Mode_FLOATING  = 0x04,  ///< Floating input
+    GPIO_Mode_IPD       = 0x28,  ///< Pull down input
+    GPIO_Mode_IPU       = 0x48,  ///< Pull up input
+    GPIO_Mode_Out_OD    = 0x14,  ///< Universal open drain output
+    GPIO_Mode_Out_PP    = 0x10,  ///< Universal push-pull output
+    GPIO_Mode_AF_OD     = 0x1C,  ///< Multiplex open drain output
+    GPIO_Mode_AF_PP     = 0x18   ///< Multiplexed push-pull output
+} GPIOMode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Bit_SET and Bit_RESET enumeration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    Bit_RESET = 0,  ///< bit reset
+    Bit_SET         ///< bit set
+} BitAction;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  GPIO Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u16               GPIO_Pin;    ///< GPIO_Pin
+    GPIOSpeed_TypeDef GPIO_Speed;  ///< GPIO_Speed
+    GPIOMode_TypeDef  GPIO_Mode;   ///< GPIO_Mode
+} GPIO_InitTypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Constants
+/// @{
+
+#define GPIO_Speed_2MHz GPIO_Speed_20MHz
+
+#define GPIO_Pin_0                  (0x0001U)                                   ///< Pin 0 selected
+#define GPIO_Pin_1                  (0x0002U)                                   ///< Pin 1 selected
+#define GPIO_Pin_2                  (0x0004U)                                   ///< Pin 2 selected
+#define GPIO_Pin_3                  (0x0008U)                                   ///< Pin 3 selected
+#define GPIO_Pin_4                  (0x0010U)                                   ///< Pin 4 selected
+#define GPIO_Pin_5                  (0x0020U)                                   ///< Pin 5 selected
+#define GPIO_Pin_6                  (0x0040U)                                   ///< Pin 6 selected
+#define GPIO_Pin_7                  (0x0080U)                                   ///< Pin 7 selected
+#define GPIO_Pin_8                  (0x0100U)                                   ///< Pin 8 selected
+#define GPIO_Pin_9                  (0x0200U)                                   ///< Pin 9 selected
+#define GPIO_Pin_10                 (0x0400U)                                   ///< Pin 10 selected
+#define GPIO_Pin_11                 (0x0800U)                                   ///< Pin 11 selected
+#define GPIO_Pin_12                 (0x1000U)                                   ///< Pin 12 selected
+#define GPIO_Pin_13                 (0x2000U)                                   ///< Pin 13 selected
+#define GPIO_Pin_14                 (0x4000U)                                   ///< Pin 14 selected
+#define GPIO_Pin_15                 (0x8000U)                                   ///< Pin 15 selected
+#define GPIO_Pin_All                (0xFFFFU)                                   ///< All pins selected
+
+
+#define GPIO_AF_0                   (0x00U)                                     ///< Alternative function 0
+#define GPIO_AF_1                   (0x01U)                                     ///< Alternative function 1
+#define GPIO_AF_2                   (0x02U)                                     ///< Alternative function 2
+#define GPIO_AF_3                   (0x03U)                                     ///< Alternative function 3
+#define GPIO_AF_4                   (0x04U)                                     ///< Alternative function 4
+#define GPIO_AF_5                   (0x05U)                                     ///< Alternative function 5
+#define GPIO_AF_6                   (0x06U)                                     ///< Alternative function 6
+#define GPIO_AF_7                   (0x07U)                                     ///< Alternative function 7
+#define GPIO_AF_8                   (0x08U)                                     ///< Alternative function 8 
+#define GPIO_AF_9                   (0x09U)                                     ///< Alternative function 9 
+#define GPIO_AF_10                  (0x0AU)                                     ///< Alternative function 10
+#define GPIO_AF_11                  (0x0BU)                                     ///< Alternative function 11
+#define GPIO_AF_12                  (0x0CU)                                     ///< Alternative function 12
+#define GPIO_AF_13                  (0x0DU)                                     ///< Alternative function 13
+#define GPIO_AF_14                  (0x0EU)                                     ///< Alternative function 14
+#define GPIO_AF_15                  (0x0FU)                                     ///< Alternative function 15
+#define GPIO_PortSourceGPIOA        (0x00U)
+#define GPIO_PortSourceGPIOB        (0x01U)
+#define GPIO_PortSourceGPIOC        (0x02U)
+#define GPIO_PortSourceGPIOD        (0x03U)
+
+#define GPIO_PinSource0             (0x00U)
+#define GPIO_PinSource1             (0x01U)
+#define GPIO_PinSource2             (0x02U)
+#define GPIO_PinSource3             (0x03U)
+#define GPIO_PinSource4             (0x04U)
+#define GPIO_PinSource5             (0x05U)
+#define GPIO_PinSource6             (0x06U)
+#define GPIO_PinSource7             (0x07U)
+#define GPIO_PinSource8             (0x08U)
+#define GPIO_PinSource9             (0x09U)
+#define GPIO_PinSource10            (0x0AU)
+#define GPIO_PinSource11            (0x0BU)
+#define GPIO_PinSource12            (0x0CU)
+#define GPIO_PinSource13            (0x0DU)
+#define GPIO_PinSource14            (0x0EU)
+#define GPIO_PinSource15            (0x0FU)
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Variables
+/// @{
+
+#ifdef _HAL_GPIO_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Functions
+/// @{
+void GPIO_DeInit(GPIO_TypeDef* gpio);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct);
+void GPIO_StructInit(GPIO_InitTypeDef* init_struct);
+void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin);
+void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin);
+void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value);
+void GPIO_Write(GPIO_TypeDef* gpio, u16 value);
+void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state);
+void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin);
+bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin);
+bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin);
+
+u16 GPIO_ReadInputData(GPIO_TypeDef* gpio);
+u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio);
+
+
+void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function);
+
+void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function);
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_GPIO_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h
new file mode 100644
index 000000000..42a9ab55f
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h
@@ -0,0 +1,255 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_i2c.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE I2C
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_I2C_H
+#define __HAL_I2C_H
+
+// Files includes
+#include "types.h"
+#include "reg_i2c.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_HAL
+/// @brief I2C HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup DRV_Exported_Constants
+/// @{
+
+#define I2C_OWN_ADDRESS  0x20
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  I2C Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    union {
+        u16 Mode;        ///< Specifies the I2C mode. This parameter can be a value of I2C_mode.
+        u16 I2C_Mode;
+    };
+    union {
+        u16 Speed;       ///< Specifies the I2C speed. This parameter can be a value of I2C_speed.
+        u16 I2C_Speed;
+    };
+    union {
+        u16 OwnAddress;  ///< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.
+        u16 I2C_OwnAddress;
+    };
+
+    union {
+        u32 ClockSpeed;  ///< Specifies the clock speed.
+        u32 I2C_ClockSpeed;
+    };
+} I2C_InitTypeDef;
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Exported_Constants
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C DMA Direction
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RDMAE_SET = 1,  // 1 - DMA read
+    TDMAE_SET       // 2 - DMA transmit
+} I2C_DMA_Dir_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C Transfer Direction
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    I2C_Direction_Transmitter,  // I2C Transmitter
+    I2C_Direction_Receiver      // I2C Receiver
+} I2C_Trans_Dir_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C Acknowledged Address
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    I2C_AcknowledgedAddress_7bit  = 0x4000,  // 7-bit address
+    I2C_AcknowledgedAddress_10bit = 0xC000   // 10-bit address
+} I2C_ACKaddr_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Private_Defines
+/// @{
+#define INTR_MASK           ((u16)0xC000)
+#define FLAG_Mask           ((u32)0x00793FFF)
+#define IC_TAR_ENDUAL_Set   ((u16)0x1000)
+#define IC_TAR_ENDUAL_Reset ((u16)0xEFFF)
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_modes
+/// @{
+#define TX_EMPTY_CTRL       I2C_CR_EMPINT
+#define IC_SLAVE_DISABLE    I2C_CR_SLAVEDIS
+#define IC_RESTART_EN       I2C_CR_REPEN
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_interrupts_definition
+/// @{
+#define I2C_IT_RX_UNDER     ((u16)0x0001)
+#define I2C_IT_RX_OVER      ((u16)0x0002)
+#define I2C_IT_RX_FULL      ((u16)0x0004)
+#define I2C_IT_TX_OVER      ((u16)0x0008)
+#define I2C_IT_TX_EMPTY     ((u16)0x0010)
+#define I2C_IT_RD_REQ       ((u16)0x0020)
+#define I2C_IT_TX_ABRT      ((u16)0x0040)
+#define I2C_IT_RX_DONE      ((u16)0x0080)
+#define I2C_IT_ACTIVITY     ((u16)0x0100)
+#define I2C_IT_STOP_DET     ((u16)0x0200)
+#define I2C_IT_START_DET    ((u16)0x0400)
+#define I2C_IT_GEN_CALL     ((u16)0x0800)
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_flags_definition
+/// @{
+#define I2C_FLAG_RX_UNDER     ((u16)0x0001)
+#define I2C_FLAG_RX_OVER      ((u16)0x0002)
+#define I2C_FLAG_RX_FULL      ((u16)0x0004)
+#define I2C_FLAG_TX_OVER      ((u16)0x0008)
+#define I2C_FLAG_TX_EMPTY     ((u16)0x0010)
+#define I2C_FLAG_RD_REQ       ((u16)0x0020)
+#define I2C_FLAG_TX_ABRT      ((u16)0x0040)
+#define I2C_FLAG_RX_DONE      ((u16)0x0080)
+#define I2C_FLAG_ACTIVITY     ((u16)0x0100)
+#define I2C_FLAG_STOP_DET     ((u16)0x0200)
+#define I2C_FLAG_START_DET    ((u16)0x0400)
+#define I2C_FLAG_GEN_CALL     ((u16)0x0800)
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Events
+/// @{
+#define I2C_EVENT_RX_UNDER     ((u16)0x0001)
+#define I2C_EVENT_RX_OVER      ((u16)0x0002)
+#define I2C_EVENT_RX_FULL      ((u16)0x0004)
+#define I2C_EVENT_TX_OVER      ((u16)0x0008)
+#define I2C_EVENT_TX_EMPTY     ((u16)0x0010)
+#define I2C_EVENT_RD_REQ       ((u16)0x0020)
+#define I2C_EVENT_TX_ABRT      ((u16)0x0040)
+#define I2C_EVENT_RX_DONE      ((u16)0x0080)
+#define I2C_EVENT_ACTIVITY     ((u16)0x0100)
+#define I2C_EVENT_STOP_DET     ((u16)0x0200)
+#define I2C_EVENT_START_DET    ((u16)0x0400)
+#define I2C_EVENT_GEN_CALL     ((u16)0x0800)
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Statusflags_definition
+/// @{
+#define I2C_STATUS_FLAG_ACTIVITY    ((u16)0x8001)
+#define I2C_STATUS_FLAG_TFNF        ((u16)0x8002)
+#define I2C_STATUS_FLAG_TFE         ((u16)0x8004)
+#define I2C_STATUS_FLAG_RFNE        ((u16)0x8008)
+#define I2C_STATUS_FLAG_RFF         ((u16)0x8010)
+#define I2C_STATUS_FLAG_M_ACTIVITY  ((u16)0x8020)
+#define I2C_STATUS_FLAG_S_ACTIVITY  ((u16)0x8040)
+/// @}
+
+
+
+#define IC_SLAVE_ENABLE                 (0x0000<<6)
+#define IC_7BITADDR_MASTER              (0x0000<<4)
+#define IC_7BITADDR_SLAVE               (0x0000<<3)
+#define I2C_Speed_STANDARD              ((u16)0x0002)
+#define I2C_Speed_FAST                  ((u16)0x0004)
+#define I2C_Mode_MASTER                 ((u16)0x0001)
+#define I2C_Mode_SLAVE                  ((u16)0x0000)
+#define CMD_READ                        ((u16)0x0100)
+#define CMD_WRITE                       ((u16)0x0000)
+#define I2C_Mode_I2C                    ((u16)0x0000)
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Exported_Variables
+/// @{
+#ifdef _HAL_I2C_C_
+
+#define GLOBAL
+
+static u8 I2C_CMD_DIR = 0;
+u16       I2C_DMA_DIR = 0;
+
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Exported_Functions
+/// @{
+void I2C_DeInit(I2C_TypeDef* i2c);
+void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct);
+void I2C_StructInit(I2C_InitTypeDef* init_struct);
+void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr);
+void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state);
+void I2C_SendData(I2C_TypeDef* i2c, u8 dat);
+void I2C_ReadCmd(I2C_TypeDef* i2c);
+void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir);
+void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag);
+void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it);
+
+u8  I2C_ReceiveData(I2C_TypeDef* i2c);
+u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg);
+u32 I2C_GetLastEvent(I2C_TypeDef* i2c);
+
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event);
+FlagStatus  I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag);
+ITStatus    I2C_GetITStatus(I2C_TypeDef* i2c, u32 it);
+
+////////////////////////////////////////////////////////////////////////////////
+//          Extended function interface
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr);
+void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state);
+void I2C_DMAConfigure(I2C_TypeDef* i2c, u8 dir);
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_I2C_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h
new file mode 100644
index 000000000..e0b86d7b7
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h
@@ -0,0 +1,130 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_iwdg.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE IWDG
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_IWDG_H
+#define __HAL_IWDG_H
+
+// Files includes
+#include "types.h"
+#include "reg_iwdg.h"
+#include "reg_common.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup IWDG_HAL
+/// @brief IWDG HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup IWDG_Exported_Constants
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  IWDG prescaler
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    IWDG_Prescaler_4   = IWDG_PR_PRE_DIV4,
+    IWDG_Prescaler_8   = IWDG_PR_PRE_DIV8,
+    IWDG_Prescaler_16  = IWDG_PR_PRE_DIV16,
+    IWDG_Prescaler_32  = IWDG_PR_PRE_DIV32,
+    IWDG_Prescaler_64  = IWDG_PR_PRE_DIV64,
+    IWDG_Prescaler_128 = IWDG_PR_PRE_DIV128,
+    IWDG_Prescaler_256 = IWDG_PR_PRE_DIV256
+} IWDGPrescaler_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  IWDG flag
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    IWDG_FLAG_PVU = 0x0001,  // IWDG prescaler value update flag
+    IWDG_FLAG_RVU = 0x0002   // IWDG counter reload value update flag
+} IWDGFlag_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Write access to IWDG_PR and IWDG_RLR registers
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    IWDG_WriteAccess_Enable  = 0x5555,  // Enable write
+    IWDG_WriteAccess_Disable = 0x0000   // Disable write
+} IWDGWriteAccess_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  IWDG Key Reload
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    KR_KEY_Reload = 0xAAAA,  // Reload value
+    KR_KEY_Enable = 0xCCCC   // Start IWDG
+} IWDGKey_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  IWDG Overflow Configration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    IWDG_Overflow_Reset     = 0,               //
+    IWDG_Overflow_Interrupt = IWDG_CR_IRQSEL   //
+} IWDGOverflowConfig_TypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup IWDG_Exported_Variables
+/// @{
+#ifdef _HAL_IWDG_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+#endif
+
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup IWDG_Exported_Functions
+/// @{
+FlagStatus IWDG_GetFlagStatus(u16 flag);
+
+void IWDG_WriteAccessCmd(u16 write_access);
+void IWDG_SetPrescaler(u8 prescaler);
+void IWDG_SetReload(u16 reload);
+u32 IWDG_GetReload(void);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+void PVU_CheckStatus(void);
+void RVU_CheckStatus(void);
+
+void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config);
+void IWDG_ClearITPendingBit(void);
+void IWDG_EnableIT(void);
+void IWDG_Reset(void);
+void IWDG_ClearIT(void);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_IWDG_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h
new file mode 100644
index 000000000..0b7429963
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h
@@ -0,0 +1,128 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_misc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE NVIC
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_MISC_H
+#define __HAL_MISC_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup NVIC_HAL
+/// @brief NVIC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup NVIC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  NVIC Init Structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u8 NVIC_IRQChannel;
+    u8 NVIC_IRQChannelPreemptionPriority;
+    u8 NVIC_IRQChannelSubPriority;
+    FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  NVIC New Init Structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u8              NVIC_IRQChannel;
+    u8              NVIC_IRQChannelPreemptionPriority;                          // Cortex-M0 not used
+    u8              NVIC_IRQChannelSubPriority;
+    FunctionalState NVIC_IRQChannelCmd;
+} exNVIC_Init_TypeDef;
+
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup NVIC_Exported_Constants
+/// @{
+
+#define NVIC_VectTab_RAM        (0x20000000U)
+#define NVIC_VectTab_FLASH      (0x08000000U)
+
+#define NVIC_LP_SEVONPEND       (0x10U)
+#define NVIC_LP_SLEEPDEEP       (0x04U)
+#define NVIC_LP_SLEEPONEXIT     (0x02U)
+
+#define NVIC_PriorityGroup_0     (0x0700U) // 0 bits for pre-emption priority 4 bits for subpriority 
+#define NVIC_PriorityGroup_1     (0x0600U) // 1 bits for pre-emption priority 3 bits for subpriority 
+#define NVIC_PriorityGroup_2     (0x0500U) // 2 bits for pre-emption priority 2 bits for subpriority 
+#define NVIC_PriorityGroup_3     (0x0400U) // 3 bits for pre-emption priority 1 bits for subpriority 
+#define NVIC_PriorityGroup_4     (0x0300U) // 4 bits for pre-emption priority 0 bits for subpriority 
+
+#define AIRCR_VECTKEY_MASK (0x05FA0000U)
+
+#define SysTick_CLKSource_HCLK_Div8     (0xFFFFFFFBU)
+
+
+#define SysTick_CLKSource_EXTCLK        (0xFFFFFFFBU)
+#define SysTick_CLKSource_HCLK          (0x00000004U)
+/// @}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup NVIC_Exported_Variables
+/// @{
+
+#ifdef _HAL_NVIC_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup NVIC_Exported_Functions
+/// @{
+
+void NVIC_PriorityGroupConfig(u32 priority_group);
+void NVIC_SetVectorTable(u32 vect_tab, u32 offset);
+
+void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state);
+void NVIC_Init(NVIC_InitTypeDef* init_struct);
+
+void SysTick_CLKSourceConfig(u32 systick_clk_source);
+
+void exNVIC_Init(exNVIC_Init_TypeDef* init_struct);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_NVIC_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h
new file mode 100644
index 000000000..f7837ca8d
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h
@@ -0,0 +1,156 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_pwr.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE PWR
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_PWR_H
+#define __HAL_PWR_H
+
+// Files includes
+#include "types.h"
+#include "reg_pwr.h"
+#include "reg_syscfg.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup PWR_HAL
+/// @brief PWR HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup PWR_Exported_Types
+/// @{
+
+typedef enum {
+    emWUP_Pin1 = 0,
+    emWUP_Pin2 = 1,
+    emWUP_Pin3,
+    emWUP_Pin4,
+    emWUP_Pin5,
+    emWUP_Pin6,
+} emWUP_Pin_Typedef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PVD_detection_level
+
+typedef enum {
+    emPVD_LEVEL0  = SYSCFG_PDETCSR_PLS_1V7,
+    emPVD_LEVEL1  = SYSCFG_PDETCSR_PLS_2V0,
+    emPVD_LEVEL2  = SYSCFG_PDETCSR_PLS_2V3,
+    emPVD_LEVEL3  = SYSCFG_PDETCSR_PLS_2V6,
+    emPVD_LEVEL4  = SYSCFG_PDETCSR_PLS_2V9,
+    emPVD_LEVEL5  = SYSCFG_PDETCSR_PLS_3V2,
+    emPVD_LEVEL6  = SYSCFG_PDETCSR_PLS_3V5,
+    emPVD_LEVEL7  = SYSCFG_PDETCSR_PLS_3V8,
+    emPVD_LEVEL8  = SYSCFG_PDETCSR_PLS_4V1,
+    emPVD_LEVEL9  = SYSCFG_PDETCSR_PLS_4V4,
+    emPVD_LEVEL10 = SYSCFG_PDETCSR_PLS_4V7
+} emPVD_Level_Typedef;
+#define PWR_PVDLevel_1V7          SYSCFG_PDETCSR_PLS_1V7
+#define PWR_PVDLevel_2V0          SYSCFG_PDETCSR_PLS_2V0
+#define PWR_PVDLevel_2V3          SYSCFG_PDETCSR_PLS_2V3
+#define PWR_PVDLevel_2V6          SYSCFG_PDETCSR_PLS_2V6
+#define PWR_PVDLevel_2V9          SYSCFG_PDETCSR_PLS_2V9
+#define PWR_PVDLevel_3V2          SYSCFG_PDETCSR_PLS_3V2
+#define PWR_PVDLevel_3V5          SYSCFG_PDETCSR_PLS_3V5
+#define PWR_PVDLevel_3V8          SYSCFG_PDETCSR_PLS_3V8
+#define PWR_PVDLevel_4V1          SYSCFG_PDETCSR_PLS_4V1
+#define PWR_PVDLevel_4V4          SYSCFG_PDETCSR_PLS_4V4
+#define PWR_PVDLevel_4V7          SYSCFG_PDETCSR_PLS_4V7
+/// @brief Regulator_state_is_STOP_mode
+typedef enum {
+    PWR_Regulator_ON       = 0x00000000,
+    PWR_Regulator_LowPower = 0x00000001
+
+} emPWR_Reg_Stop_mode_Typedef;
+
+/// @brief STOP_mode_entry
+typedef enum {
+    PWR_STOPEntry_WFI = 0x00000001,
+    PWR_STOPEntry_WFE = 0x00000002
+
+} emPWR_STOP_ModeEn_Typedef;
+
+/// @brief Low Power Mode
+typedef enum {
+    LP_STOP_MODE    = 0,
+    LP_SLEEP_MODE   = 1,
+    LP_STANDBY_MODE = 2
+} emPWR_LP_Mode_Typedef;
+
+/// @brief Wait_for_mode
+typedef enum {
+    LP_WFI,
+    LP_WFE
+} emPWR_Wait_Mode_Typedef;
+//typedef enum {
+//    PWR_FLAG_WU   = PWR_CSR_WUF,
+//    PWR_FLAG_SB   = PWR_CSR_SBF,
+
+//    PWR_FLAG_PVDO = PWR_CSR_PVDO
+
+
+//} emPWR_PWR_Flag_Typedef;
+
+
+/// @}
+
+///////////////////////////////////////////////////////////////////////////////
+/// @defgroup PWR_Exported_Variables
+/// @{
+
+#ifdef _HAL_PWR_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup PWR_Exported_Functions
+/// @{
+
+void PWR_DeInit(void);
+
+void PWR_BackupAccessCmd(FunctionalState state);
+
+void PWR_PVDCmd(FunctionalState state);
+void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level);
+void PWR_WakeUpPinCmd(FunctionalState state);
+void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry);
+void PWR_EnterSTANDBYMode(void);
+
+
+void PWR_ClearFlag(u32 flag);
+FlagStatus PWR_GetFlagStatus(u32 flag);
+FlagStatus PWR_GetPVDOFlagStatus(u32 flag);
+void exPWR_EnterLowPowerMode(emPWR_LP_Mode_Typedef lp_mode, emPWR_Wait_Mode_Typedef wait_mode);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_PWR_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h
new file mode 100644
index 000000000..deb916d4c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h
@@ -0,0 +1,329 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_rcc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RCC
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_RCC_H
+#define __HAL_RCC_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "mm32_reg.h"
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_HAL
+/// @brief RCC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_Exported_Constants
+/// @{
+
+
+/// @}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_Exported_Enumeration
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief HSE configuration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_HSE_OFF    = 0,             // HSE OFF
+    RCC_HSE_ON     = RCC_CR_HSEON,  // HSE ON
+    RCC_HSE_Bypass = RCC_CR_HSEBYP  // HSE Bypass
+} RCCHSE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Used for flags
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    CR_REG_INDEX   = 1,     //
+    BDCR_REG_INDEX = 2,     //
+    CSR_REG_INDEX  = 3,     //
+    RCC_FLAG_MASK  = 0x1FU  //
+} RCC_RegisterFlag_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC Flag
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    // Flags in the CR register
+    RCC_FLAG_HSIRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)),         ///< Internal High Speed clock ready flag
+    RCC_FLAG_HSERDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)),         ///< External High Speed clock ready flag
+
+    RCC_FLAG_PLLRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)),         ///< PLL clock ready flag
+
+    // Flags in the CSR register
+    RCC_FLAG_LSIRDY  = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)),      ///< Internal Low Speed oscillator Ready
+    RCC_FLAG_PINRST  = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)),     ///< PIN reset flag
+    RCC_FLAG_PORRST  = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)),     ///< POR/PDR reset flag
+    RCC_FLAG_SFTRST  = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)),     ///< Software Reset flag
+    RCC_FLAG_IWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)),    ///< Independent Watchdog reset flag
+    RCC_FLAG_WWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)),    ///< Window watchdog reset flag
+
+    // Flags in the BDCR register
+    RCC_FLAG_LSERDY = ((u8)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos))      ///< External Low Speed oscillator Ready
+} RCC_FLAG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief System clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_HSI = 0,  // Set HSI as systemCLOCK
+    RCC_HSE = 1,  // Set HSE as systemCLOCK
+    RCC_PLL = 2,   // Set PLL as systemCLOCK
+    RCC_LSI = 3  // Set LSI as systemCLOCK
+} SYSCLK_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PLL entry clock source
+////////////////////////////////////////////////////////////////////////////////
+
+typedef enum {
+    RCC_HSI_Div4 = 0,
+    RCC_HSI_Div = 0,
+    RCC_HSE_Div1 = RCC_PLLCFGR_PLLSRC,
+    RCC_HSE_Div2 = (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC),
+} RCC_PLLSource_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PLL multiplication factor
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_PLLMul_2  = 0x00000000U,
+    RCC_PLLMul_3  = 0x00040000U,
+    RCC_PLLMul_4  = 0x00080000U,
+    RCC_PLLMul_5  = 0x000C0000U,
+    RCC_PLLMul_6  = 0x00100000U,
+    RCC_PLLMul_7  = 0x00140000U,
+    RCC_PLLMul_8  = 0x00180000U,
+    RCC_PLLMul_9  = 0x001C0000U,
+    RCC_PLLMul_10 = 0x00200000U,
+    RCC_PLLMul_11 = 0x00240000U,
+    RCC_PLLMul_12 = 0x00280000U,
+    RCC_PLLMul_13 = 0x002C0000U,
+    RCC_PLLMul_14 = 0x00300000U,
+    RCC_PLLMul_15 = 0x00340000U,
+    RCC_PLLMul_16 = 0x00380000U
+} RCC_PLLMul_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief AHB clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_SYSCLK_Div1   = RCC_CFGR_HPRE_DIV1,
+    RCC_SYSCLK_Div2   = RCC_CFGR_HPRE_DIV2,
+    RCC_SYSCLK_Div4   = RCC_CFGR_HPRE_DIV4,
+    RCC_SYSCLK_Div8   = RCC_CFGR_HPRE_DIV8,
+    RCC_SYSCLK_Div16  = RCC_CFGR_HPRE_DIV16,
+    RCC_SYSCLK_Div64  = RCC_CFGR_HPRE_DIV64,
+    RCC_SYSCLK_Div128 = RCC_CFGR_HPRE_DIV128,
+    RCC_SYSCLK_Div256 = RCC_CFGR_HPRE_DIV256,
+    RCC_SYSCLK_Div512 = RCC_CFGR_HPRE_DIV512
+} RCC_AHB_CLK_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief APB1 and APB2clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_HCLK_Div1  = RCC_CFGR_PPRE1_DIV1,
+    RCC_HCLK_Div2  = RCC_CFGR_PPRE1_DIV2,
+    RCC_HCLK_Div4  = RCC_CFGR_PPRE1_DIV4,
+    RCC_HCLK_Div8  = RCC_CFGR_PPRE1_DIV8,
+    RCC_HCLK_Div16 = RCC_CFGR_PPRE1_DIV16
+} RCC_APB1_APB2_CLK_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief USB Device clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_USBCLKSource_PLLCLK_Div1 = 0,
+    RCC_USBCLKSource_PLLCLK_Div2 = 1,
+    RCC_USBCLKSource_PLLCLK_Div3 = 2,
+    RCC_USBCLKSource_PLLCLK_Div4 = 3
+} RCC_USBCLKSOURCE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_PCLK2_Div2 = (0x00000000),
+    RCC_PCLK2_Div4 = (0x00004000),
+    RCC_PCLK2_Div6 = (0x00008000),
+    RCC_PCLK2_Div8 = (0x0000C000)
+} RCC_ADCCLKSOURCE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief LSE configuration
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_LSE_OFF    = 0,               // LSE OFF
+    RCC_LSE_ON     = RCC_BDCR_LSEON,  // LSE ON
+    RCC_LSE_Bypass = RCC_BDCR_LSEBYP  // LSE Bypass
+} RCC_LSE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC clock source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_RTCCLKSource_LSE        = RCC_BDCR_RTCSEL_LSE,
+    RCC_RTCCLKSource_LSI        = RCC_BDCR_RTCSEL_LSI,
+    RCC_RTCCLKSource_HSE_Div128 = RCC_BDCR_RTCSEL_HSE
+} RCC_RTCCLKSOURCE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Clock source to output on MCO pin
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_MCO_NoClock = RCC_CFGR_MCO_NOCLOCK,
+    RCC_MCO_LSI     = RCC_CFGR_MCO_LSI,
+    RCC_MCO_LSE = RCC_CFGR_MCO_LSE,
+    RCC_MCO_SYSCLK = RCC_CFGR_MCO_SYSCLK,
+    RCC_MCO_HSI    = RCC_CFGR_MCO_HSI,
+    RCC_MCO_HSE    = RCC_CFGR_MCO_HSE,
+    RCC_MCO_PLLCLK_Div2 = RCC_CFGR_MCO_PLL
+} RCC_MCO_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC Interrupt source
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RCC_IT_LSIRDY = RCC_CIR_LSIRDYF,
+    RCC_IT_LSERDY = RCC_CIR_LSERDYF,
+    RCC_IT_HSIRDY = RCC_CIR_HSIRDYF,
+    RCC_IT_HSERDY = RCC_CIR_HSERDYF,
+    RCC_IT_PLLRDY = RCC_CIR_PLLRDYF,
+    RCC_IT_CSS = RCC_CIR_CSSF
+} RCC_IT_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC clock frequency type definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u32 SYSCLK_Frequency;                                                       ///< returns SYSCLK clock frequency.
+    u32 HCLK_Frequency;                                                         ///< returns hclk clock frequency.
+    u32 PCLK1_Frequency;                                                        ///< returns PCLK1 clock frequency.
+    u32 PCLK2_Frequency;                                                        ///< returns PCLK2 clock frequency.
+    u32 ADCCLK_Frequency;                                                       ///< returns ADCCLK clock frequency.
+} RCC_ClocksTypeDef;
+/// @}
+
+/// @}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_Exported_Variables
+/// @{
+#ifdef _HAL_RCC_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RCC_Exported_Functions
+/// @{
+void RCC_DeInit(void);
+void RCC_HSEConfig(RCCHSE_TypeDef state);
+void RCC_HSICmd(FunctionalState state);
+void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_src);
+void RCC_PLLDMDNConfig(u32 plldn, u32 plldm);
+void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul);
+void RCC_PLLCmd(FunctionalState state);
+void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk);
+void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk);
+void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk);
+void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src);
+void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2);
+void RCC_LSICmd(FunctionalState state);
+
+void RCC_RTCCLKCmd(FunctionalState state);
+void RCC_LSEConfig(RCC_LSE_TypeDef state);
+void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src);
+void RCC_BackupResetCmd(FunctionalState state);
+
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk);
+void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state);
+void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state);
+void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state);
+void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state);
+void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state);
+void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state);
+void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state);
+void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state);
+void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state);
+void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state);
+
+void RCC_ClockSecuritySystemCmd(FunctionalState state);
+void RCC_MCOConfig(RCC_MCO_TypeDef mco_src);
+void RCC_ClearFlag(void);
+void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state);
+void RCC_ClearITPendingBit(u8 it);
+
+u8  RCC_GetSYSCLKSource(void);
+u32 RCC_GetSysClockFreq(void);
+u32 RCC_GetHCLKFreq(void);
+
+u32 RCC_GetPCLK1Freq(void);
+u32 RCC_GetPCLK2Freq(void);
+FlagStatus  RCC_GetFlagStatus(RCC_FLAG_TypeDef flag);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag);
+ITStatus    RCC_GetITStatus(RCC_IT_TypeDef it);
+
+////////////////////////////////////////////////////////////////////////////////
+//          Extended function interface
+////////////////////////////////////////////////////////////////////////////////
+//ErrorStatus exRCC_Init(RCCInitStruct_TypeDef* para);
+void exRCC_SystickDisable(void);
+void exRCC_SystickEnable(u32 sys_tick_period);
+void exRCC_APB1PeriphReset(u32 apb1_periph);
+void exRCC_APB2PeriphReset(u32 apb2_periph);
+void exRCC_BackupReset(void);
+void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state);
+void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state);
+/// @}
+
+/// @}
+
+/// @}
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_RCC_H 
+////////////////////////////////////////////////////////////////////////////////
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h
new file mode 100644
index 000000000..da5295c78
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h
@@ -0,0 +1,102 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_redefine.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE REDEFINE
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_REDEFINE_H
+#define __HAL_REDEFINE_H
+
+// Files includes
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+/////////////////////////////////////1///////////////////////////////////////////
+/// @defgroup REDEFINE_HAL
+/// @brief REDEFINE HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup REDEFINE_Exported_Types
+/// @{
+///
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup REDEFINE_Exported_Constants
+/// @{
+//Lib redefine
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief HAL_lib Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define TIM_TRGOSource_Reset          TIM_TRIGSource_Reset
+#define TIM_TRGOSource_Enable         TIM_TRIGSource_Enable
+#define TIM_TRGOSource_Update         TIM_TRIGSource_Update
+#define TIM_TRGOSource_OC1            TIM_TRIGSource_OC1
+#define TIM_TRGOSource_OC1Ref         TIM_TRIGSource_OC1Ref
+#define TIM_TRGOSource_OC2Ref         TIM_TRIGSource_OC2Ref
+#define TIM_TRGOSource_OC3Ref         TIM_TRIGSource_OC3Ref
+#define TIM_TRGOSource_OC4Ref         TIM_TRIGSource_OC4Ref
+///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
+///< The Counter Enable CEN is used as the trigger output (TRIG).
+///< The update event is used as the trigger output (TRIG).
+///< The trigger output sends a positive pulse when the CC1IF flag     ///< is to be set, as soon as a capture or compare match occurs (TRIG).
+///< OC1REF signal is used as the trigger output (TRIG).
+///< OC2REF signal is used as the trigger output (TRIG).
+///< OC3REF signal is used as the trigger output (TRIG).
+///< OC4REF signal is used as the trigger output (TRIG).
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup REDEFINE_Exported_Variables
+/// @{
+#ifdef _HAL_REDEFINE_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup REDEFINE_Exported_Functions
+/// @{
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_REDEFINE_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h
new file mode 100644
index 000000000..fcf48d569
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h
@@ -0,0 +1,114 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_rtc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RTC
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_RTC_H
+#define __HAL_RTC_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+#include "reg_rtc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RTC_HAL
+/// @brief RTC HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RTC_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_interrupts_define
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RTC_IT_OW  = RTC_CR_OWIE,   ///< Overflow interrupt
+    RTC_IT_ALR = RTC_CR_ALRIE,  ///< Alarm interrupt
+    RTC_IT_SEC = RTC_CR_SECIE   ///< Second interrupt
+} RTC_IT_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_interrupts_flags
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    RTC_FLAG_RTOFF = RTC_CSR_RTOFF,  ///< RTC Operation OFF flag
+    RTC_FLAG_RSF   = RTC_CSR_RSF,    ///< Registers Synchronized flag
+    RTC_FLAG_OW    = RTC_CSR_OWF,    ///< Overflow flag
+    RTC_FLAG_ALR   = RTC_CSR_ALRF,   ///< Alarm flag
+    RTC_FLAG_SEC   = RTC_CSR_SECF    ///< Second flag
+} RTC_FLAG_TypeDef;
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RTC_Exported_Constants
+/// @{
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RTC_Exported_Variables
+/// @{
+
+#ifdef _HAL_RTC_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+GLOBAL  bool accessRTC;
+
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup RTC_Exported_Functions
+/// @{
+void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state);
+void RTC_ClearFlag(RTC_FLAG_TypeDef flag);
+void RTC_ClearITPendingBit(RTC_IT_TypeDef it);
+void RTC_EnterConfigMode(void);
+void RTC_SetCounter(u32 count);
+void RTC_SetPrescaler(u32 prescaler);
+void RTC_SetAlarm(u32 alarm);
+void RTC_ExitConfigMode(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+
+u32 RTC_GetCounter(void);
+u32 RTC_GetDivider(void);
+
+FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag);
+ITStatus   RTC_GetITStatus(RTC_IT_TypeDef it);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_RTC_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h
new file mode 100644
index 000000000..199ccc4c6
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h
@@ -0,0 +1,503 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_gpio.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_SDIO_H
+#define __HAL_SDIO_H
+
+// Files includes
+#include "mm32_reg.h"
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_HAL
+/// @brief GPIO HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup GPIO_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Output Maximum frequency selection
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_FLAG_CCRCFAIL                  ((u32)0x00000001)
+#define SDIO_FLAG_DCRCFAIL                  ((u32)0x00000002)
+#define SDIO_FLAG_CTIMEOUT                  ((u32)0x00000004)
+#define SDIO_FLAG_DTIMEOUT                  ((u32)0x00000008)
+#define SDIO_FLAG_TXUNDERR                  ((u32)0x00000010)
+#define SDIO_FLAG_RXOVERR                   ((u32)0x00000020)
+#define SDIO_FLAG_CMDREND                   ((u32)0x00000040)
+#define SDIO_FLAG_CMDSENT                   ((u32)0x00000080)
+#define SDIO_FLAG_DATAEND                   ((u32)0x00000100)
+#define SDIO_FLAG_STBITERR                  ((u32)0x00000200)
+#define SDIO_FLAG_DBCKEND                   ((u32)0x00000400)
+#define SDIO_FLAG_CMDACT                    ((u32)0x00000800)
+#define SDIO_FLAG_TXACT                     ((u32)0x00001000)
+#define SDIO_FLAG_RXACT                     ((u32)0x00002000)
+#define SDIO_FLAG_TXFIFOHE                  ((u32)0x00004000)
+#define SDIO_FLAG_RXFIFOHF                  ((u32)0x00008000)
+#define SDIO_FLAG_TXFIFOF                   ((u32)0x00010000)
+#define SDIO_FLAG_RXFIFOF                   ((u32)0x00020000)
+#define SDIO_FLAG_TXFIFOE                   ((u32)0x00040000)
+#define SDIO_FLAG_RXFIFOE                   ((u32)0x00080000)
+#define SDIO_FLAG_TXDAVL                    ((u32)0x00100000)
+#define SDIO_FLAG_RXDAVL                    ((u32)0x00200000)
+#define SDIO_FLAG_SDIOIT                    ((u32)0x00400000)
+#define SDIO_FLAG_CEATAEND                  ((u32)0x00800000)
+
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+//SDIO working mode define ,SDIO working mode definition, set through the SD_SetDevice Mode function.
+#define SD_POLLING_MODE     0                                                                      /// Query mode. In this mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing.
+#define SD_DMA_MODE         1                                                                      /// In DMA mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing.   
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SDIO Various error enumeration definitions
+////////////////////////////////////////////////////////////////////////////////
+
+typedef enum {
+    SD_CMD_CRC_FAIL = 1,                                                                    ///< Command response received (but CRC check failed)
+    SD_DATA_CRC_FAIL,                                                                       ///< Data bock sent/received (CRC check Failed)
+    SD_CMD_RSP_TIMEOUT,                                                                     ///< Command response timeout
+    SD_DATA_TIMEOUT,                                                                        ///< Data time out
+    SD_TX_UNDERRUN,                                                                         ///< Transmit FIFO under-run
+    SD_RX_OVERRUN,                                                                          ///< Receive FIFO over-run
+    SD_START_BIT_ERR,                                                                       ///< Start bit not detected on all data signals in widE bus mode
+    SD_CMD_OUT_OF_RANGE,                                                                    ///< CMD's argument was out of range.
+    SD_ADDR_MISALIGNED,                                                                     ///< Misaligned address
+    SD_BLOCK_LEN_ERR,                                                                       ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length
+    SD_ERASE_SEQ_ERR,                                                                       ///< An error in the sequence of erase command occurs.
+    SD_BAD_ERASE_PARAM,                                                                     ///< An Invalid selection for erase groups
+    SD_WRITE_PROT_VIOLATION,                                                                ///< Attempt to program a write protect block
+    SD_LOCK_UNLOCK_FAILED,                                                                  ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card
+    SD_COM_CRC_FAILED,                                                                      ///< CRC check of the previous command failed
+    SD_ILLEGAL_CMD,                                                                         ///< Command is not legal for the card state
+    SD_CARD_ECC_FAILED,                                                                     ///< Card internal ECC was applied but failed to correct the data
+    SD_CC_ERROR,                                                                            ///< Internal card controller error
+    SD_GENERAL_UNKNOWN_ERROR,                                                               ///< General or Unknown error
+    SD_STREAM_READ_UNDERRUN,                                                                ///< The card could not sustain data transfer in stream read operation.
+    SD_STREAM_WRITE_OVERRUN,                                                                ///< The card could not sustain data programming in stream mode
+    SD_CID_CSD_OVERWRITE,                                                                   ///< CID/CSD overwrite error
+    SD_WP_ERASE_SKIP,                                                                       ///< only partial address space was erased
+    SD_CARD_ECC_DISABLED,                                                                   ///< Command has been executed without using internal ECC
+    SD_ERASE_RESET,                                                                         ///< Erase sequence was cleared before executing because an out of erase sequence command was received
+    SD_AKE_SEQ_ERROR,                                                                       ///< Error in sequence of authentication.
+    SD_INVALID_VOLTRANGE,                                                                   ///< SD invalid voltage range,
+    SD_ADDR_OUT_OF_RANGE,                                                                   ///< SD addresses are out of range,
+    SD_SWITCH_ERROR,                                                                        ///< SD switch error,
+    SD_SDIO_DISABLED,                                                                       ///< SD SDIO disability,
+    SD_SDIO_FUNCTION_BUSY,                                                                  ///< SD SDIO function busy,
+    SD_SDIO_FUNCTION_FAILED,                                                                ///< SD SDIO failed,
+    SD_SDIO_UNKNOWN_FUNCTION,                                                               ///< SDIO unknown function,
+    SD_INTERNAL_ERROR,                                                                      ///< SD internal error,
+    SD_NOT_CONFIGURED,                                                                      ///< SD is not configured,
+    SD_REQUEST_PENDING,                                                                     ///< The SD request waits,
+    SD_REQUEST_NOT_APPLICABLE,                                                              ///< The SD requirement does not apply,
+    SD_INVALID_PARAMETER,                                                                   ///< Invalid SD parameter,
+    SD_UNSUPPORTED_FEATURE,                                                                 ///< Features not supported by SD,
+    SD_UNSUPPORTED_HW,                                                                      ///< HW not supported by SD,
+    SD_ERROR,                                                                               ///< SD error
+    SD_OK = 0                                                                               ///< SD OK
+} SD_Error;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SD card CSD register data
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u8  CSDStruct;                                                                                ///< CSD structure
+    u8  SysSpecVersion;                                                                           ///< System specification version
+    u8  Reserved1;                                                                                ///< Reserved
+    u8  TAAC;                                                                                     ///< Data read access-time 1
+    u8  NSAC;                                                                                     ///< Data read access-time 2 in CLK cycles
+    u8  MaxBusClkFrec;                                                                            ///< Max. bus clock frequency
+    u16 CardComdClasses;                                                                          ///< Card command classes
+    u8  RdBlockLen;                                                                               ///< Max. read data block length
+    u8  PartBlockRead;                                                                            ///< Partial blocks for read allowed
+    u8  WrBlockMisalign;                                                                          ///< Write block misalignment
+    u8  RdBlockMisalign;                                                                          ///< Read block misalignment
+    u8  DSRImpl;                                                                                  ///< DSR implemented
+    u8  Reserved2;                                                                                ///< Reserved
+    u32 DeviceSize;                                                                               ///< Device Size
+    u8  MaxRdCurrentVDDMin;                                                                       ///< Max. read current @ VDD min
+    u8  MaxRdCurrentVDDMax;                                                                       ///< Max. read current @ VDD max
+    u8  MaxWrCurrentVDDMin;                                                                       ///< Max. write current @ VDD min
+    u8  MaxWrCurrentVDDMax;                                                                       ///< Max. write current @ VDD max
+    u8  DeviceSizeMul;                                                                            ///< Device size multiplier
+    u8  EraseGrSize;                                                                              ///< Erase group size
+    u8  EraseGrMul;                                                                               ///< Erase group size multiplier
+    u8  WrProtectGrSize;                                                                          ///< Write protect group size
+    u8  WrProtectGrEnable;                                                                        ///< Write protect group enable
+    u8  ManDeflECC;                                                                               ///< Manufacturer default ECC
+    u8  WrSpeedFact;                                                                              ///< Write speed factor
+    u8  MaxWrBlockLen;                                                                            ///< Max. write data block length
+    u8  WriteBlockPaPartial;                                                                      ///< Partial blocks for write allowed
+    u8  Reserved3;                                                                                ///< Reserded
+    u8  ContentProtectAppli;                                                                      ///< Content protection application
+    u8  FileFormatGrouop;                                                                         ///< File format group
+    u8  CopyFlag;                                                                                 ///< Copy flag (OTP)
+    u8  PermWrProtect;                                                                            ///< Permanent write protection
+    u8  TempWrProtect;                                                                            ///< Temporary write protection
+    u8  FileFormat;                                                                               ///< File Format
+    u8  ECC;                                                                                      ///< ECC code
+    u8  CSD_CRC;                                                                                  ///< CSD CRC
+    u8  Reserved4;                                                                                ///< always 1
+} SD_CSD;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SD card CID register data
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u8  ManufacturerID;                                                                           ///< ManufacturerID
+    u16 OEM_AppliID;                                                                              ///< OEM/Application ID
+    u32 ProdName1;                                                                                ///< Product Name part1
+    u8  ProdName2;                                                                                ///< Product Name part2
+    u8  ProdRev;                                                                                  ///< Product Revision
+    u32 ProdSN;                                                                                   ///< Product Serial Number
+    u8  Reserved1;                                                                                ///< Reserved1
+    u16 ManufactDate;                                                                             ///< Manufacturing Date
+    u8  CID_CRC;                                                                                  ///< CID CRC
+    u8  Reserved2;                                                                                ///< always 1
+} SD_CID;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SD state
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SD_CARD_READY                  = ((u32)0x00000001),
+    SD_CARD_IDENTIFICATION         = ((u32)0x00000002),
+    SD_CARD_STANDBY                = ((u32)0x00000003),
+    SD_CARD_TRANSFER               = ((u32)0x00000004),
+    SD_CARD_SENDING                = ((u32)0x00000005),
+    SD_CARD_RECEIVING              = ((u32)0x00000006),
+    SD_CARD_PROGRAMMING            = ((u32)0x00000007),
+    SD_CARD_DISCONNECTED           = ((u32)0x00000008),
+    SD_CARD_ERROR                  = ((u32)0x000000FF)
+} SDCardState;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SD message ,include CSD,CID data
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    SD_CSD SD_csd;
+    SD_CID SD_cid;
+    long long CardCapacity;
+    u32 CardBlockSize;
+    u16 RCA;
+    u8 CardType;
+} SD_CardInfo;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SDIO init
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u8 SDIO_MDEN;
+    u8 SDIO_DATWT;
+    u8 SDIO_SelPTSM;
+    u8 SDIO_CLKSP;
+    u8 SDIO_OUTM;
+    u8 SDIO_SelSM;
+    u8 SDIO_OPMSel;
+} SDIO_InitTypeDef;
+
+typedef struct {
+    u32 SDIO_Argument;  ///Specifies the SDIO command argument which is sent
+    ///to a card as part of a command message. If a command
+    ///contains an argument, it must be loaded into this register
+    ///before writing the command to the command register
+
+    u32 SDIO_CmdIndex;  ///Specifies the SDIO command index. It must be lower than 0x40.
+
+    u32 SDIO_Response;  ///Specifies the SDIO response type.
+    ///This parameter can be a value of @ref SDIO_Response_Type
+
+    u32 SDIO_Wait;      ///Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+    ///This parameter can be a value of @ref SDIO_Wait_Interrupt_State
+
+///    u32 SDIO_CPSM;      ///Specifies whether SDIO Command path state machine (CPSM)
+    ///is enabled or disabled.
+    ///This parameter can be a value of @ref SDIO_CPSM_State
+} SDIO_CmdInitTypeDef;
+typedef struct {
+    u32 SDIO_DataTimeOut;   // < Specifies the data timeout period in card bus clock periods.
+    //
+    u32 SDIO_DataLength;    // < Specifies the number of data bytes to be transferred.
+    //
+    u32 SDIO_DataBlockSize; // < Specifies the data block size for block transfer.
+    // This parameter can be a value of @ref SDIO_Data_Block_Size
+    //
+    u32 SDIO_TransferDir;   // < Specifies the data transfer direction, whether the transfer
+    // is a read or write.
+    // This parameter can be a value of @ref SDIO_Transfer_Direction
+    //
+//    u32 SDIO_TransferMode;  // < Specifies whether data transfer is in stream or block mode.
+//                                 // This parameter can be a value of @ref SDIO_Transfer_Type
+//                                 //
+//    u32 SDIO_DPSM;          // < Specifies whether SDIO Data path state machine (DPSM)
+//                                 //    is enabled or disabled.
+//                                 //    This parameter can be a value of @ref SDIO_DPSM_State
+} SDIO_DataInitTypeDef;
+
+
+
+extern SD_CardInfo SDCardInfo;
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SDIO Ö¸instruction set
+/// @{
+#define SD_CMD_GO_IDLE_STATE                       ((u8)0)
+#define SD_CMD_SEND_OP_COND                        ((u8)1)
+#define SD_CMD_ALL_SEND_CID                        ((u8)2)
+#define SD_CMD_SET_REL_ADDR                        ((u8)3)
+#define SD_CMD_SET_DSR                             ((u8)4)
+#define SD_CMD_SDIO_SEN_OP_COND                    ((u8)5)
+#define SD_CMD_HS_SWITCH                           ((u8)6)
+#define SD_CMD_SEL_DESEL_CARD                      ((u8)7)
+#define SD_CMD_HS_SEND_EXT_CSD                     ((u8)8)
+#define SD_CMD_SEND_CSD                            ((u8)9)
+#define SD_CMD_SEND_CID                            ((u8)10)
+#define SD_CMD_READ_DAT_UNTIL_STOP                 ((u8)11)
+#define SD_CMD_STOP_TRANSMISSION                   ((u8)12)
+#define SD_CMD_SEND_STATUS                         ((u8)13)
+#define SD_CMD_HS_BUSTEST_READ                     ((u8)14)
+#define SD_CMD_GO_INACTIVE_STATE                   ((u8)15)
+#define SD_CMD_SET_BLOCKLEN                        ((u8)16)
+#define SD_CMD_READ_SINGLE_BLOCK                   ((u8)17)
+#define SD_CMD_READ_MULT_BLOCK                     ((u8)18)
+#define SD_CMD_HS_BUSTEST_WRITE                    ((u8)19)
+#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((u8)20)
+#define SD_CMD_SET_BLOCK_COUNT                     ((u8)23)
+#define SD_CMD_WRITE_SINGLE_BLOCK                  ((u8)24)
+#define SD_CMD_WRITE_MULT_BLOCK                    ((u8)25)
+#define SD_CMD_PROG_CID                            ((u8)26)
+#define SD_CMD_PROG_CSD                            ((u8)27)
+#define SD_CMD_SET_WRITE_PROT                      ((u8)28)
+#define SD_CMD_CLR_WRITE_PROT                      ((u8)29)
+#define SD_CMD_SEND_WRITE_PROT                     ((u8)30)
+#define SD_CMD_SD_ERASE_GRP_START                  ((u8)32)
+#define SD_CMD_SD_ERASE_GRP_END                    ((u8)33)
+#define SD_CMD_ERASE_GRP_START                     ((u8)35)
+#define SD_CMD_ERASE_GRP_END                       ((u8)36)
+#define SD_CMD_ERASE                               ((u8)38)
+#define SD_CMD_FAST_IO                             ((u8)39)
+#define SD_CMD_GO_IRQ_STATE                        ((u8)40)
+#define SD_CMD_LOCK_UNLOCK                         ((u8)42)
+#define SD_CMD_APP_CMD                             ((u8)55)
+#define SD_CMD_GEN_CMD                             ((u8)56)
+#define SD_CMD_NO_CMD                              ((u8)64)
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup Following commands are SD Card Specific commands.
+/// @{
+#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((u8)6)
+#define SD_CMD_SD_APP_STAUS                        ((u8)13)
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((u8)22)
+#define SD_CMD_SD_APP_OP_COND                      ((u8)41)
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((u8)42)
+#define SD_CMD_SD_APP_SEND_SCR                     ((u8)51)
+#define SD_CMD_SDIO_RW_DIRECT                      ((u8)52)
+#define SD_CMD_SDIO_RW_EXTENDED                    ((u8)53)
+
+#define SD_CMD_SD_APP_GET_MKB                      ((u8)43)
+#define SD_CMD_SD_APP_GET_MID                      ((u8)44)
+#define SD_CMD_SD_APP_SET_CER_RN1                  ((u8)45)
+#define SD_CMD_SD_APP_GET_CER_RN2                  ((u8)46)
+#define SD_CMD_SD_APP_SET_CER_RES2                 ((u8)47)
+#define SD_CMD_SD_APP_GET_CER_RES1                 ((u8)48)
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((u8)18)
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((u8)25)
+#define SD_CMD_SD_APP_SECURE_ERASE                 ((u8)38)
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((u8)49)
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((u8)48)
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SD support define.
+/// @{
+#define SDIO_STD_CAPACITY_SD_CARD_V1_1             ((u32)0x00000000)
+#define SDIO_STD_CAPACITY_SD_CARD_V2_0             ((u32)0x00000001)
+#define SDIO_HIGH_CAPACITY_SD_CARD                 ((u32)0x00000002)
+#define SDIO_MULTIMEDIA_CARD                       ((u32)0x00000003)
+#define SDIO_SECURE_DIGITAL_IO_CARD                ((u32)0x00000004)
+#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD            ((u32)0x00000005)
+#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD          ((u32)0x00000006)
+#define SDIO_HIGH_CAPACITY_MMC_CARD                ((u32)0x00000007)
+/// @}
+
+#ifndef NULL
+#define NULL 0
+#endif
+#define SDIO_STATIC_FLAGS               ((u32)0x000005FF)
+#define SDIO_CMD0TIMEOUT                ((u32)0x00010000)
+#define SDIO_DATATIMEOUT                ((u32)0xFFFFFFFF)
+#define SDIO_FIFO_Address               ((u32)0x40018080)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup Mask for errors Card Status R1 (OCR Register)
+/// @{
+#define SD_OCR_ADDR_OUT_OF_RANGE        ((u32)0x80000000)
+#define SD_OCR_ADDR_MISALIGNED          ((u32)0x40000000)
+#define SD_OCR_BLOCK_LEN_ERR            ((u32)0x20000000)
+#define SD_OCR_ERASE_SEQ_ERR            ((u32)0x10000000)
+#define SD_OCR_BAD_ERASE_PARAM          ((u32)0x08000000)
+#define SD_OCR_WRITE_PROT_VIOLATION     ((u32)0x04000000)
+#define SD_OCR_LOCK_UNLOCK_FAILED       ((u32)0x01000000)
+#define SD_OCR_COM_CRC_FAILED           ((u32)0x00800000)
+#define SD_OCR_ILLEGAL_CMD              ((u32)0x00400000)
+#define SD_OCR_CARD_ECC_FAILED          ((u32)0x00200000)
+#define SD_OCR_CC_ERROR                 ((u32)0x00100000)
+#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((u32)0x00080000)
+#define SD_OCR_STREAM_READ_UNDERRUN     ((u32)0x00040000)
+#define SD_OCR_STREAM_WRITE_OVERRUN     ((u32)0x00020000)
+#define SD_OCR_CID_CSD_OVERWRIETE       ((u32)0x00010000)
+#define SD_OCR_WP_ERASE_SKIP            ((u32)0x00008000)
+#define SD_OCR_CARD_ECC_DISABLED        ((u32)0x00004000)
+#define SD_OCR_ERASE_RESET              ((u32)0x00002000)
+#define SD_OCR_AKE_SEQ_ERROR            ((u32)0x00000008)
+#define SD_OCR_ERRORBITS                ((u32)0xFDFFE008)
+/// @}
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup Masks for R6 Response
+/// @{
+#define SD_R6_GENERAL_UNKNOWN_ERROR     ((u32)0x00002000)
+#define SD_R6_ILLEGAL_CMD               ((u32)0x00004000)
+#define SD_R6_COM_CRC_FAILED            ((u32)0x00008000)
+/// @}
+#define SD_VOLTAGE_WINDOW_SD            ((u32)0x80100000)
+#define SD_HIGH_CAPACITY                ((u32)0x40000000)
+#define SD_STD_CAPACITY                 ((u32)0x00000000)
+#define SD_CHECK_PATTERN                ((u32)0x000001AA)
+#define SD_VOLTAGE_WINDOW_MMC           ((u32)0x80FF8000)
+
+#define SD_MAX_VOLT_TRIAL               ((u32)0x0000FFFF)
+#define SD_ALLZERO                      ((u32)0x00000000)
+
+#define SD_WIDE_BUS_SUPPORT             ((u32)0x00040000)
+#define SD_SINGLE_BUS_SUPPORT           ((u32)0x00010000)
+#define SD_CARD_LOCKED                  ((u32)0x02000000)
+#define SD_CARD_PROGRAMMING             ((u32)0x00000007)
+#define SD_CARD_RECEIVING               ((u32)0x00000006)
+#define SD_DATATIMEOUT                  ((u32)0xFFFFFFFF)
+#define SD_0TO7BITS                     ((u32)0x000000FF)
+#define SD_8TO15BITS                    ((u32)0x0000FF00)
+#define SD_16TO23BITS                   ((u32)0x00FF0000)
+#define SD_24TO31BITS                   ((u32)0xFF000000)
+#define SD_MAX_DATA_LENGTH              ((u32)0x01FFFFFF)
+
+#define SD_HALFFIFO                     ((u32)0x00000008)
+#define SD_HALFFIFOBYTES                ((u32)0x00000020)
+
+#define SD_CCCC_LOCK_UNLOCK             ((u32)0x00000080)
+#define SD_CCCC_WRITE_PROT              ((u32)0x00000040)
+#define SD_CCCC_ERASE                   ((u32)0x00000020)
+
+
+#define SDIO_SEND_IF_COND               ((u32)0x00000008)
+
+#define SDIO_Response_No                    ((u32)0x00)
+#define SDIO_Response_Short                 ((u32)0x01)
+#define SDIO_Response_Long                  ((u32)0x03)
+
+#define SDIO_DataBlockSize_1b               ((u32)0x00000000)
+#define SDIO_DataBlockSize_2b               ((u32)0x00000001)
+#define SDIO_DataBlockSize_4b               ((u32)0x00000002)
+#define SDIO_DataBlockSize_8b               ((u32)0x00000003)
+#define SDIO_DataBlockSize_16b              ((u32)0x00000004)
+#define SDIO_DataBlockSize_32b              ((u32)0x00000005)
+#define SDIO_DataBlockSize_64b              ((u32)0x00000006)
+#define SDIO_DataBlockSize_128b             ((u32)0x00000007)
+#define SDIO_DataBlockSize_256b             ((u32)0x00000008)
+#define SDIO_DataBlockSize_512b             ((u32)0x00000009)
+#define SDIO_DataBlockSize_1024b            ((u32)0x0000000A)
+#define SDIO_DataBlockSize_2048b            ((u32)0x0000000B)
+#define SDIO_DataBlockSize_4096b            ((u32)0x0000000C)
+#define SDIO_DataBlockSize_8192b            ((u32)0x0000000D)
+#define SDIO_DataBlockSize_16384b           ((u32)0x0000000E)
+//Define the data block length when the block data transfer mode is selected:
+//0000: (0 decimal) lock length  = 2^0 = 1 byte
+//0001: (1 decimal) lock length  = 2^1 = 2 bytes
+//0010: (2 decimal) lock length  = 2^2 = 4 bytes
+//0011: (3 decimal) lock length  = 2^3 = 8 bytes
+//0100: (4 decimal) lock length  = 2^4 = 16 bytes
+//0101: (5 decimal) lock length  = 2^5 = 32 bytes
+//0110: (6 decimal) lock length  = 2^6 = 64 bytes
+//0111: (7 decimal) lock length  = 2^7 = 128 bytes
+//1000: (8 decimal) lock length  = 2^8 = 256 bytes
+//1001: (9 decimal) lock length  = 2^9 = 512 bytes
+//1010: (10 decimal) lock length = 2^10 = 1024 bytes
+//1011: (11 decimal) lock length = 2^11 = 2048 bytes
+//1100: (12 decimal) lock length = 2^12 = 4096 bytes
+//1101: (13 decimal) lock length = 2^13 = 8192 bytes
+//1110: (14 decimal) lock length = 2^14 = 16384 bytes
+//1111: (15 decimal) reserved
+
+
+#define SDIO_TransferDir_ToCard             ((u32)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((u32)0x00000002)
+
+#define SDIO_Wait_No                        ((u32)0x00000000) // SDIO No Wait, TimeOut is enabled 
+#define SDIO_Wait_IT                        ((u32)0x00000100) //SDIO Wait Interrupt Request 
+#define SDIO_Wait_Pend                      ((u32)0x00000200) // SDIO Wait End of transfer 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup I2C_Exported_Functions
+/// @{
+void SDIO_DeInit(void);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockSet(u32 value);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state);
+void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state);
+void SDIO_Clock_Set(u8 clkdiv);
+void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg);
+SD_Error SD_PowerOFF(void);
+SD_Error CmdError(void);
+SD_Error CmdResp2Error(void);
+SD_Error CmdResp3Error(void);
+SD_Error CmdResp6Error(u8 cmd, u16* prca);
+SD_Error CmdResp7Error(void);
+SD_Error CmdResp1Error(u8 cmd);
+void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir);
+void SDIO_ClearITPendingBit(u32 SDIO_IT);
+FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);
+u32 SDIO_GetTimeOutCounter(void);
+u32 SDIO_ReadData(void);
+void SDIO_WriteData(u32 tempbuff);
+void SDIO_DMACmd(FunctionalState state);
+/// @}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h
new file mode 100644
index 000000000..db1a9aa30
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h
@@ -0,0 +1,351 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_spi.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SPI
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_SPI_H
+#define __HAL_SPI_H
+
+// Files includes
+#include "types.h"
+#include "reg_spi.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_HAL
+/// @brief SPI HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI mode enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_Mode_Slave  = 0x0000,        ///< SPI slave mode
+    SPI_Mode_Master = SPI_GCR_MODE   ///< SPI master mode
+} SPI_Mode_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI data size enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_DataSize_8b  = 0x0000,         ///< 8 bits valid data
+    SPI_DataSize_32b = SPI_GCR_DWSEL   ///< 32 bits valid data
+} SPI_DataSize_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI clock polarity enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_CPOL_Low  = 0x0000,                                                     ///< The clock is low in idle state.
+    SPI_CPOL_High = SPI_CCR_CPOL                                                ///< The clock is high in idle state.
+} SPI_CPOL_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI clock phase enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_CPHA_2Edge = 0x0000,                                                    ///< Data sampling starts from the second clock edge.
+    SPI_CPHA_1Edge = SPI_CCR_CPHA                                               ///< Data sampling starts from the first clock edge.
+} SPI_CPHA_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI nss control mode enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_NSS_Soft = 0x0000,
+    SPI_NSS_Hard = SPI_GCR_NSS
+} SPI_NSS_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI baud rate prescaler enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_BaudRatePrescaler_2   = 0x0002,                                         ///< SCK clock devide by 2
+    SPI_BaudRatePrescaler_4   = 0x0004,                                         ///< SCK clock devide by 4
+    SPI_BaudRatePrescaler_8   = 0x0008,                                         ///< SCK clock devide by 7
+    SPI_BaudRatePrescaler_16  = 0x0010,                                         ///< SCK clock devide by 16
+    SPI_BaudRatePrescaler_32  = 0x0020,                                         ///< SCK clock devide by 32
+    SPI_BaudRatePrescaler_64  = 0x0040,                                         ///< SCK clock devide by 64
+    SPI_BaudRatePrescaler_128 = 0x0080,                                         ///< SCK clock devide by 128
+    SPI_BaudRatePrescaler_256 = 0x0100                                          ///< SCK clock devide by 256
+} SPI_BaudRatePrescaler_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI first bit enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_FirstBit_MSB = 0x0000,                                                  ///< Data transfers start from MSB
+    SPI_FirstBit_LSB = SPI_CCR_LSBFE                                            ///< Data transfers start from LSB
+} SPI_FirstBit_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI FIFO trigger level enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_RXTLF = SPI_GCR_RXTLF_Half,                                             ///< RX FIFO trigger level
+    SPI_TXTLF = SPI_GCR_TXTLF_Half                                              ///< TX FIFO trigger level
+} SPI_TLF_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI bit derection enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_Direction_Rx,                                                           ///< Receive enable
+    SPI_Direction_Tx,                                                           ///< Transmit enable
+    SPI_Disable_Rx,                                                             ///< Receive disable
+    SPI_Disable_Tx                                                              ///< Transmit disable
+} SPI_Direction_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI flag enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_FLAG_RXAVL       = SPI_SR_RXAVL,                                        ///< Receive 1 byte available data flag
+    SPI_FLAG_TXEPT       = SPI_SR_TXEPT,                                        ///< Transmitter empty flag
+    SPI_FLAG_TXFULL      = SPI_SR_TXFULL,                                       ///< Transmitter FIFO full status flag
+    SPI_FLAG_RXAVL_4BYTE = SPI_SR_RXAVL_4BYTE                                   ///< Receive 4 bytes available data flag
+} SPI_FLAG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI slave mode data edge adjust enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_SlaveAdjust_LOW,                                                        ///< SPI slave mode data edge adjust in low speed mode
+    SPI_SlaveAdjust_FAST                                                        ///< SPI slave mode data edge adjust in fast speed mode
+} SPI_SlaveAdjust_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI data edge adjust enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_DataEdgeAdjust_LOW,                                                     ///< SPI data edge adjust in low speed mode
+    SPI_DataEdgeAdjust_FAST                                                     ///< SPI data edge adjust in fast speed mode
+} SPI_DataEdgeAdjust_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI interruput enum definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    SPI_IT_TXEPT    = 0x40,                                                     ///< Transmitter empty interrupt
+    SPI_IT_RXFULL   = 0x20,                                                     ///< RX FIFO full interrupt
+    SPI_IT_RXMATCH  = 0x10,                                                     ///< Receive data match the RXDNR number interrut
+    SPI_IT_RXOERR   = 0x08,                                                     ///< Receive overrun error interrupt
+    SPI_IT_UNDERRUN = 0x04,                                                     ///< Underrun interrupt
+    SPI_IT_RX       = 0x02,                                                     ///< Receive available data interrupt
+    SPI_IT_TX       = 0x01                                                      ///< Transmit FIFO available interrupt
+} SPI_IT_TypeDef;
+
+
+typedef enum {
+    I2S_Standard_Phillips               = 0x0000,
+    I2S_Standard_MSB                    = 0x0010,
+    I2S_Standard_LSB                    = 0x0020,
+    I2S_Standard_PCMShort               = 0x0030,
+    I2S_Standard_PCMLong                = 0x00B0,
+} SPI_I2S_STANDARD_TypeDef;
+
+
+typedef enum {
+    I2S_DataFormat_16b              = 0x0000,
+    I2S_DataFormat_16bextended      = 0x0001,
+    I2S_DataFormat_24b              = 0x0003,
+    I2S_DataFormat_32b              = 0x0005,
+} SPI_I2S_DATAFORMAT_TypeDef;
+typedef enum {
+    I2S_AudioFreq_192k               = (192000),
+    I2S_AudioFreq_96k                = (96000),
+    I2S_AudioFreq_48k                = (48000),
+    I2S_AudioFreq_44k                = (44100),
+    I2S_AudioFreq_32k                = (32000),
+    I2S_AudioFreq_24k                = (24000),
+    I2S_AudioFreq_22k                = (22050),
+    I2S_AudioFreq_16k                = (16000),
+    I2S_AudioFreq_11k                = (11025),
+    I2S_AudioFreq_12k                = (12000),
+    I2S_AudioFreq_8k                 = (8000),
+    I2S_AudioFreq_4k                 = (4000),
+    I2S_AudioFreq_Default            = (2),
+} SPI_I2S_AUDIO_FREQ_TypeDef;
+typedef enum {
+    I2S_Mode_SlaveTx                = 0x0000,
+    I2S_Mode_SlaveRx                = 0x0100,
+    I2S_Mode_MasterTx               = 0x0200,
+    I2S_Mode_MasterRx               = 0x0300,
+} SPI_I2S_TRANS_MODE_TypeDef;
+
+typedef enum {
+    I2S_MCLKOutput_Enable           = 0x0800,
+    I2S_MCLKOutput_Disable          = 0x0000,
+} SPI_I2S_MCLK_OUTPUT_TypeDef;
+
+typedef enum {
+    I2S_CPOL_Low  = 0x0000,                                                     ///< The clock is low in idle state.
+    I2S_CPOL_High = SPI_CCR_CPOL                                                ///< The clock is high in idle state.
+} SPI_I2S_CPOL_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    SPI_Mode_TypeDef                SPI_Mode;                                   ///< Specifies the SPI operating mode
+    SPI_DataSize_TypeDef            SPI_DataSize;                               ///< Specifies the SPI available data size
+    u8                              SPI_DataWidth;                              ///< SPI data length
+    SPI_CPOL_TypeDef                SPI_CPOL;                                   ///< Specifies the serial clock steady state
+    SPI_CPHA_TypeDef                SPI_CPHA;                                   ///< Specifies the clock active edge for the bit capture
+    SPI_NSS_TypeDef                 SPI_NSS;                                    ///< Specifies whether the NSS signal is managed by hardware or by software
+    SPI_BaudRatePrescaler_TypeDef   SPI_BaudRatePrescaler;                      ///< Specifies the Baud Rate prescaler value which will be
+    ///< used to configure the transmit and receive SCK clock
+    SPI_FirstBit_TypeDef            SPI_FirstBit;                               ///< Specifies whether data transfers start from MSB or LSB bit
+    //  u16     SPI_length;
+} SPI_InitTypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  I2S Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    SPI_I2S_TRANS_MODE_TypeDef      I2S_Mode;                                   ///< Specifies the I2S operating mode.
+    SPI_I2S_STANDARD_TypeDef        I2S_Standard;                               ///< Specifies the standard used for the I2S communication.
+    SPI_I2S_DATAFORMAT_TypeDef      I2S_DataFormat;                             ///< Specifies the data format for the I2S communication.
+    SPI_I2S_MCLK_OUTPUT_TypeDef     I2S_MCLKOutput;                             ///< Specifies whether the I2S MCLK output is enabled or not.
+    SPI_I2S_AUDIO_FREQ_TypeDef      I2S_AudioFreq;                              ///< Specifies the frequency selected for the I2S communication.
+    SPI_I2S_CPOL_TypeDef            I2S_CPOL;                                   ///< Specifies the idle state of the I2S clock.
+} I2S_InitTypeDef;
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_Exported_Constants
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_Register_Mask
+/// @{
+
+#define GCR_Mask ((u32)0x0FFF)
+#define CCR_Mask ((u32)0x003F)
+#define BRR_Mask ((u32)0xFFFF)
+#define ECR_Mask ((u32)0x001F)
+
+/// @}
+
+
+// SPI_7bit_8bit data width
+#define SPI_DataWidth_1b                  ((u16)0x0001)
+#define SPI_DataWidth_2b                  ((u16)0x0002)
+#define SPI_DataWidth_3b                  ((u16)0x0003)
+#define SPI_DataWidth_4b                  ((u16)0x0004)
+#define SPI_DataWidth_5b                  ((u16)0x0005)
+#define SPI_DataWidth_6b                  ((u16)0x0006)
+#define SPI_DataWidth_7b                  ((u16)0x0007)
+#define SPI_DataWidth_8b                  ((u16)0x0008)
+#define SPI_DataWidth_9b                  ((u16)0x0009)
+#define SPI_DataWidth_10b                 ((u16)0x000a)
+#define SPI_DataWidth_11b                 ((u16)0x000b)
+#define SPI_DataWidth_12b                 ((u16)0x000c)
+#define SPI_DataWidth_13b                 ((u16)0x000d)
+#define SPI_DataWidth_14b                 ((u16)0x000e)
+#define SPI_DataWidth_15b                 ((u16)0x000f)
+#define SPI_DataWidth_16b                 ((u16)0x0010)
+#define SPI_DataWidth_17b                 ((u16)0x0011)
+#define SPI_DataWidth_18b                 ((u16)0x0012)
+#define SPI_DataWidth_19b                 ((u16)0x0013)
+#define SPI_DataWidth_20b                 ((u16)0x0014)
+#define SPI_DataWidth_21b                 ((u16)0x0015)
+#define SPI_DataWidth_22b                 ((u16)0x0016)
+#define SPI_DataWidth_23b                 ((u16)0x0017)
+#define SPI_DataWidth_24b                 ((u16)0x0018)
+#define SPI_DataWidth_25b                 ((u16)0x0019)
+#define SPI_DataWidth_26b                 ((u16)0x001a)
+#define SPI_DataWidth_27b                 ((u16)0x001b)
+#define SPI_DataWidth_28b                 ((u16)0x001c)
+#define SPI_DataWidth_29b                 ((u16)0x001d)
+#define SPI_DataWidth_30b                 ((u16)0x001e)
+#define SPI_DataWidth_31b                 ((u16)0x001f)
+#define SPI_DataWidth_32b                 ((u16)0x0000)
+
+
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_Exported_Variables
+/// @{
+
+#ifdef _HAL_SPI_C_
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SPI_Exported_Functions
+/// @{
+
+void SPI_DeInit(SPI_TypeDef* spi);
+void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct);
+void SPI_StructInit(SPI_InitTypeDef* init_struct);
+void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state);
+void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state);
+void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
+void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state);
+void SPI_SendData(SPI_TypeDef* spi, u32 data);
+void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss);
+
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction);
+void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
+void SPI_RxBytes(SPI_TypeDef* spi, u16 number);
+void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value);
+
+bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size);
+void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize);
+u32 SPI_ReceiveData(SPI_TypeDef* spi);
+
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag);
+
+ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
+
+////////////////////////////////////////////////////////////////////////////////
+//          Extended function interface
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state);
+void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrput, FunctionalState state);
+void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
+void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
+void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value);
+void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state);
+void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct);
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_SPI_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h
new file mode 100644
index 000000000..e034f9626
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h
@@ -0,0 +1,83 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_syscfg.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_SYSCFG_H
+#define __HAL_SYSCFG_H
+
+// Files includes
+#include "types.h"
+#include "mm32_device.h"
+#include "hal_EXTI.H"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SYSCFG_HAL
+/// @brief SYSCFG HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup SYSCFG_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SYSCFG mode enumeration
+////////////////////////////////////////////////////////////////////////////////
+// @defgroup SYSCFG_Memory_Remap_Config
+#define SYSCFG_MemoryRemap_Flash                ((u8)0x00)
+#define SYSCFG_MemoryRemap_SystemMemory         ((u8)0x01)
+#define SYSCFG_MemoryRemap_SRAM                 ((u8)0x03)
+
+
+
+
+///
+/// @}
+///
+
+
+
+
+// Exported macro ------------------------------------------------------------
+// Exported functions -------------------------------------------------------
+
+//  Function used to set the SYSCFG configuration to the default reset state
+#define SYSCFG_DeInit                   EXTI_DeInit
+#define SYSCFG_MemoryRemapConfig        EXTI_MemoryRemapConfig
+#define SYSCFG_EXTILineConfig           EXTI_LineConfig
+u32 SYSCFG_GetPendingIT(u32 ITSourceLine);
+void SYSCFG_BreakConfig(u32 SYSCFG_Break);
+FlagStatus SYSCFG_GetFlagStatus(u32 SYSCFG_Flag);
+void SYSCFG_ClearFlag(u32 SYSCFG_Flag);
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__HAL_SYSCFG_H 
+////////////////////////////////////////////////////////////////////////////////
+
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h
new file mode 100644
index 000000000..4e57960dd
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h
@@ -0,0 +1,755 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_tim.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE TIM
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_TIM_H
+#define __HAL_TIM_H
+
+// Files includes
+#include "types.h"
+#include "reg_tim.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup TIM_HAL
+/// @brief TIM HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup TIM_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Channel
+/// @anchor TIM_Channel
+typedef enum {
+    TIM_Channel_1 = 0x0000,  ///< TIM Channel 1
+    TIM_Channel_2 = 0x0004,  ///< TIM Channel 2
+    TIM_Channel_3 = 0x0008,  ///< TIM Channel 3
+    TIM_Channel_4 = 0x000C,  ///< TIM Channel 4
+    TIM_Channel_5 = 0x0010   ///< TIM Channel 5
+} TIMCHx_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Counter_Mode
+/// @anchor TIM_Counter_Mode
+typedef enum {
+    TIM_CounterMode_Up             = 0x0000,                        ///< TIM Up Counting Mode
+    TIM_CounterMode_Down           = TIM_CR1_DIR,                   ///< TIM Down Counting Mode
+    TIM_CounterMode_CenterAligned1 = TIM_CR1_CMS_CENTERALIGNED1,    ///< TIM Center Aligned Mode1
+    TIM_CounterMode_CenterAligned2 = TIM_CR1_CMS_CENTERALIGNED2,    ///< TIM Center Aligned Mode2
+    TIM_CounterMode_CenterAligned3 = TIM_CR1_CMS_CENTERALIGNED3     ///< TIM Center Aligned Mode3
+} TIMCOUNTMODE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_and_PWM_modes_and_Forced_Action
+/// @anchor TIM_Output_Compare_and_PWM_modes_and_Forced_Action
+typedef enum {
+    TIM_OCMode_Timing         = 0x0000,                         ///< Output compare mode: Timing
+    TIM_OCMode_Active         = 0x0010,                         ///< Output compare mode: Active
+    TIM_OCMode_Inactive       = 0x0020,                         ///< Output compare mode: Inactive
+    TIM_OCMode_Toggle         = 0x0030,                         ///< Output compare mode: Toggle
+    TIM_OCMode_PWM1           = 0x0060,                         ///< Output compare mode: PWM1
+    TIM_OCMode_PWM2           = 0x0070,                         ///< Output compare mode: PWM2
+    TIM_ForcedAction_Active   = 0x0050,                         ///< Force active level on OCnREF
+    TIM_ForcedAction_InActive = 0x0040                          ///< Force inactive level on OCnREF
+} TIMOCMODE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Clock_Division_CKD
+/// @anchor TIM_Clock_Division_CKD
+typedef enum {
+    TIM_CKD_DIV1 = TIM_CR1_CKD_DIV1,                            ///< TDTS = Tck_tim
+    TIM_CKD_DIV2 = TIM_CR1_CKD_DIV2,                            ///< TDTS = 2 * Tck_tim
+    TIM_CKD_DIV4 = TIM_CR1_CKD_DIV4                             ///< TDTS = 4 * Tck_tim
+} TIMCKD_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Internal_Trigger_Selection
+/// @anchor TIM_Internal_Trigger_Selection
+typedef enum {
+    TIM_TS_ITR0    = TIM_SMCR_TS_ITR0,                          ///< Internal Trigger 0
+    TIM_TS_ITR1    = TIM_SMCR_TS_ITR1,                          ///< Internal Trigger 1
+    TIM_TS_ITR2    = TIM_SMCR_TS_ITR2,                          ///< Internal Trigger 2
+    TIM_TS_ITR3    = TIM_SMCR_TS_ITR3,                          ///< Internal Trigger 3
+    TIM_TS_TI1F_ED = TIM_SMCR_TS_TI1F_ED,                       ///< TI1 Edge Detector
+    TIM_TS_TI1FP1  = TIM_SMCR_TS_TI1FP1,                        ///< Filtered Timer Input 1
+    TIM_TS_TI2FP2  = TIM_SMCR_TS_TI2FP2,                        ///< Filtered Timer Input 2
+    TIM_TS_ETRF    = TIM_SMCR_TS_ETRF                           ///< TI1 Edge Detector
+} TIMTS_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Trigger_Output_Source
+/// @anchor TIM_Trigger_Output_Source
+typedef enum {
+    TIM_TRIGSource_Reset  = TIM_CR2_MMS_RESET,                  ///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
+    TIM_TRIGSource_Enable = TIM_CR2_MMS_ENABLE,                 ///< The Counter Enable CEN is used as the trigger output (TRIG).
+    TIM_TRIGSource_Update = TIM_CR2_MMS_UPDATE,                 ///< The update event is used as the trigger output (TRIG).
+    TIM_TRIGSource_OC1    = TIM_CR2_MMS_OC1,                    ///< The trigger output sends a positive pulse when the CC1IF flag
+    ///< is to be set, as soon as a capture or compare match occurs (TRIG).
+    TIM_TRIGSource_OC1Ref = TIM_CR2_MMS_OC1REF,                 ///< OC1REF signal is used as the trigger output (TRIG).
+    TIM_TRIGSource_OC2Ref = TIM_CR2_MMS_OC2REF,                 ///< OC2REF signal is used as the trigger output (TRIG).
+    TIM_TRIGSource_OC3Ref = TIM_CR2_MMS_OC3REF,                 ///< OC3REF signal is used as the trigger output (TRIG).
+    TIM_TRIGSource_OC4Ref = TIM_CR2_MMS_OC4REF                  ///< OC4REF signal is used as the trigger output (TRIG).
+} TIMMMS_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Slave_Mode
+/// @anchor TIM_Slave_Mode
+typedef enum {
+    TIM_SlaveMode_Reset = TIM_SMCR_SMS_RESET,                   ///< Rising edge of the selected trigger signal (TRGI) re-initializes
+    ///< the counter and triggers an update of the registers.
+    TIM_SlaveMode_Gated     = TIM_SMCR_SMS_GATED,               ///< The counter clock is enabled when the trigger signal (TRGI) is high.
+    TIM_SlaveMode_Trigger   = TIM_SMCR_SMS_TRIGGER,             ///< The counter starts at a rising edge of the trigger TRGI.
+    TIM_SlaveMode_External1 = TIM_SMCR_SMS_EXTERNAL1            ///< Rising edges of the selected trigger (TRGI) clock the counter.
+} TIMSMSMODE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Event_Source
+/// @anchor TIM_Event_Source
+typedef enum {
+    TIM_EventSource_Update  = TIM_EGR_UG,                       ///< Timer update Event source
+    TIM_EventSource_CC1     = TIM_EGR_CC1G,                     ///< Timer Capture Compare 1 Event source
+    TIM_EventSource_CC2     = TIM_EGR_CC2G,                     ///< Timer Capture Compare 2 Event source
+    TIM_EventSource_CC3     = TIM_EGR_CC3G,                     ///< Timer Capture Compare 3 Event source
+    TIM_EventSource_CC4     = TIM_EGR_CC4G,                     ///< Timer Capture Compare 4 Event source
+    TIM_EventSource_COM     = TIM_EGR_COMG,                     ///< Timer COM event source
+    TIM_EventSource_Trigger = TIM_EGR_TG,                       ///< Timer Trigger Event source
+    TIM_EventSource_Break   = TIM_EGR_BG,                       ///< Timer Break event source
+    TIM_EventSource_CC5     = (s32)0x00010000,                  ///< Timer Capture Compare 5 Event source
+} TIMEGR_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_External_Trigger_Prescaler
+/// @anchor TIM_External_Trigger_Prescaler
+typedef enum {
+    TIM_ExtTRGPSC_OFF  = TIM_SMCR_ETPS_OFF,                     ///< ETRP Prescaler OFF
+    TIM_ExtTRGPSC_DIV2 = TIM_SMCR_ETPS_DIV2,                    ///< ETRP frequency divided by 2
+    TIM_ExtTRGPSC_DIV4 = TIM_SMCR_ETPS_DIV4,                    ///< ETRP frequency divided by 4
+    TIM_ExtTRGPSC_DIV8 = TIM_SMCR_ETPS_DIV8                     ///< ETRP frequency divided by 8
+} TIMEXTTRGPSC_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_TIx_External_Clock_Source
+/// @anchor TIM_TIx_External_Clock_Source
+typedef enum {
+    TIM_TIxExternalCLK1Source_TI1   = TIM_SMCR_TS_TI1FP1,       ///< Filtered Timer Input 1
+    TIM_TIxExternalCLK1Source_TI2   = TIM_SMCR_TS_TI2FP2,       ///< Filtered Timer Input 2
+    TIM_TIxExternalCLK1Source_TI1ED = TIM_SMCR_TS_TI1F_ED       ///< TI1 Edge Detector
+} TIM_TIEXTCLKSRC_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Lock_level
+/// @anchor Lock_level
+typedef enum {
+    TIM_LOCKLevel_OFF = TIM_BDTR_LOCK_OFF,                      ///< No bit is write protected.
+    TIM_LOCKLevel_1   = TIM_BDTR_LOCK_1,                        ///< DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
+    ///< register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
+    TIM_LOCKLevel_2 = TIM_BDTR_LOCK_2,                          ///< LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
+    ///< register, as s32 as the related channel is configured in output through the CCxS
+    ///< bits) as well as OSSR and OSSI bits can no longer be written.
+    TIM_LOCKLevel_3 = TIM_BDTR_LOCK_3                           ///< LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers,
+                      ///< as s32 as the related channel is configured in output through the CCxS bits)
+                      ///< can no longer be written.
+} TIMLOCKLEVEL_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_One_Pulse_Mode
+/// @anchor TIM_One_Pulse_Mode
+typedef enum {
+    TIM_OPMode_Repetitive = 0,                                  ///< Counter is not stopped at update event
+    TIM_OPMode_Single     = TIM_CR1_OPM                         ///< Counter stops counting at the next update event (clearing the bit CEN)
+} TIMOPMODE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_Polarity
+/// @anchor TIM_Output_Compare_Polarity
+typedef enum {
+    TIM_OCPolarity_High,                                        ///< Output Compare active high
+    TIM_OCPolarity_Low = TIM_CCER_CC1P                          ///< Output Compare active low
+} TIMCCxP_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_N_Polarity
+/// @anchor TIM_Output_Compare_N_Polarity
+typedef enum {
+    TIM_OCNPolarity_High,                                       ///< Output Compare active high
+    TIM_OCNPolarity_Low = TIM_CCER_CC1NP                        ///< Output Compare active low
+} TIMCCxNP_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_state
+/// @anchor TIM_Output_Compare_state
+typedef enum {
+    TIM_OutputState_Disable = 0,                                ///< Output Compare Disable
+    TIM_OutputState_Enable  = TIM_CCER_CC1EN                     ///< Output Compare Enable
+} TIMOUTPUTSTATE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_N_state
+/// @anchor TIM_Output_Compare_N_state
+typedef enum {
+    TIM_OutputNState_Disable = 0,                               ///< Output Compare N Disable
+    TIM_OutputNState_Enable  = TIM_CCER_CC1NEN                   ///< Output Compare N Enable
+} TIMOUTPUTNSTATE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Capture_Compare_state
+/// @anchor TIM_Capture_Compare_state
+typedef enum {
+    TIM_CCx_Disable = 0,                                        ///< Capture/Compare Enable
+    TIM_CCx_Enable  = TIM_CCER_CC1EN                             ///< Capture/Compare Enable
+} TIMCCxE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Capture_Compare_N_state
+/// @anchor TIM_Capture_Compare_N_state
+typedef enum {
+    TIM_CCxN_Disable = 0,                                       ///< Capture/Compare N Enable
+    TIM_CCxN_Enable  = TIM_CCER_CC1NEN                           ///< Capture/Compare N Enable
+} TIMCCxNE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Break_Input_enable_disable
+/// @anchor Break_Input_enable_disable
+typedef enum {
+    TIM_Break_Disable = 0,                                      ///< Break inputs (BRK and CSS clock failure event) disabled
+    TIM_Break_Enable  = TIM_BDTR_BKEN                            ///< Break inputs (BRK and CSS clock failure event) enabled
+} TIMBKE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Break_Polarity
+/// @anchor Break_Polarity
+typedef enum {
+    TIM_BreakPolarity_Low  = 0,                                 ///< Break input BRK is active low
+    TIM_BreakPolarity_High = TIM_BDTR_BKP                       ///< Break input BRK is active high
+} TIMBKP_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_AOE_Bit_Set_Reset
+/// @anchor TIM_AOE_Bit_Set_Reset
+typedef enum {
+    TIM_AutomaticOutput_Disable = 0,                            ///< MOE can be set only by software.
+    TIM_AutomaticOutput_Enable  = TIM_BDTR_AOEN                  ///< MOE can be set by software or automatically at the next
+                                  ///< update event (if the break input is not be active).
+} TIMAOE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DOE_Bit_Set_Reset
+/// @anchor TIM_DOE_Bit_Set_Reset
+typedef enum {
+    TIM_DirectOutput_Disable = 0,                               ///< Direct output disable, output waiting for dead time
+    TIM_DirectOutput_Enable  = TIM_BDTR_DOEN                     ///< Direct output enable, no longer waiting for output after dead time
+} TIMDOE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OSSI_Off_State_Selection_for_Idle_mode_state
+/// @anchor OSSI_Off_State_Selection_for_Idle_mode_state
+typedef enum {
+    TIM_OSSIState_Disable = 0,                                  ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
+    TIM_OSSIState_Enable  = TIM_BDTR_OSSI                       ///< When inactive, OC/OCN outputs are forced first with their idle level
+                            ///< as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1).
+} TIMOSSI_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OSSR_Off_State_Selection_for_Run_mode_state
+/// @anchor OSSR_Off_State_Selection_for_Run_mode_state
+typedef enum {
+    TIM_OSSRState_Disable = 0,                                  ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
+    TIM_OSSRState_Enable  = TIM_BDTR_OSSR                       ///< When inactive, OC/OCN outputs are enabled with their inactive level
+                            ///< as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1.
+} TIMOSSR_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_Idle_State
+/// @anchor TIM_Output_Compare_Idle_State
+typedef enum {
+    TIM_OCIdleState_Reset = 0,                                  ///< OCn=0 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4)
+    TIM_OCIdleState_Set   = TIM_CR2_OIS1                        ///< OCn=1 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4)
+} TIMOIS_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_N_Idle_State
+/// @anchor TIM_Output_Compare_N_Idle_State
+typedef enum {
+    TIM_OCNIdleState_Reset = 0,                                 ///< OCnN=0 after a dead-time when MOE=0.(n= 0 : 4)
+    TIM_OCNIdleState_Set   = TIM_CR2_OIS1N                      ///< OCnN=1 after a dead-time when MOE=0.(n= 0 : 4)
+} TIMOISN_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Input_Capture_Selection
+/// @anchor TIM_Input_Capture_Selection
+typedef enum {
+    TIM_ICSelection_DirectTI   = TIM_CCMR1_CC1S_DIRECTTI,
+    TIM_ICSelection_IndirectTI = TIM_CCMR1_CC1S_INDIRECTTI,
+    TIM_ICSelection_TRC        = TIM_CCMR1_CC1S_TRC             ///< TIM Input is selected to be connected to TRC.
+} TIMICSEL_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Input_Capture_Prescaler
+/// @anchor TIM_Input_Capture_Prescaler
+typedef enum {
+    TIM_ICPSC_DIV1 = 0x0000,                                    ///< no prescaler
+    TIM_ICPSC_DIV2 = 0x0004,                                    ///< capture is done once every 2 events
+    TIM_ICPSC_DIV4 = 0x0008,                                    ///< capture is done once every 4 events
+    TIM_ICPSC_DIV8 = 0x000C                                     ///< capture is done once every 8 events
+} TIMICPSC_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Input_Capture_Polarity
+/// @anchor TIM_Input_Capture_Polarity
+typedef enum {
+    TIM_ICPolarity_Rising  = 0,                                 ///< IC Rising edge
+    TIM_ICPolarity_Falling = TIM_CCER_CC1P,                     ///< IC Falling edge
+    TIM_ICPolarity_BothEdge = TIM_CCER_CC1P | TIM_CCER_CC1NP
+} TIMICP_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_External_Trigger_Polarity
+/// @anchor TIM_External_Trigger_Polarity
+typedef enum {
+    TIM_ExtTRGPolarity_NonInverted = 0,                         ///< Active high or rising edge active
+    TIM_ExtTRGPolarity_Inverted    = TIM_SMCR_ETP               ///< Active low or falling edge active
+} TIMETP_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Prescaler_Reload_Mode
+/// @anchor TIM_Prescaler_Reload_Mode
+typedef enum {
+    TIM_PSCReloadMode_Update    = 0,                            ///< The Prescaler is loaded at the update event
+    TIM_PSCReloadMode_Immediate = TIM_EGR_UG                    ///< The Prescaler is loaded immediately
+} TIMUG_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Encoder_Mode
+/// @anchor TIM_Encoder_Mode
+typedef enum {
+    TIM_EncoderMode_TI1  = TIM_SMCR_SMS_ENCODER1,               ///< Counter counts on TI1FP1 edge depending on TI2FP2 level.
+    TIM_EncoderMode_TI2  = TIM_SMCR_SMS_ENCODER2,               ///< Counter counts on TI2FP2 edge depending on TI1FP1 level.
+    TIM_EncoderMode_TI12 = TIM_SMCR_SMS_ENCODER3                ///< Counter counts on both TI1FP1 and TI2FP2 edges depending
+                           ///< on the level of the other input.
+} TIMSMSENCODER_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Update_Source
+/// @anchor TIM_Update_Source
+typedef enum {
+    TIM_UpdateSource_Global  = 0,                               ///< Source of update is counter overflow/underflow.
+    TIM_UpdateSource_Regular = TIM_CR1_URS                      ///< Source of update is the counter overflow/underflow
+                               ///< or the setting of UG bit, or an update generation
+                               ///< through the slave mode controller.
+} TIMURS_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_Preload_State
+/// @anchor TIM_Output_Compare_Preload_State
+typedef enum {
+    TIM_OCPreload_Disable = 0,                                  ///< TIM output compare preload disable
+    TIM_OCPreload_Enable  = TIM_CCMR1_OC1PEN                     ///< TIM output compare preload enable
+} TIMOCPE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_Fast_State
+/// @anchor TIM_Output_Compare_Fast_State
+typedef enum {
+    TIM_OCFast_Disable = 0,                                     ///< TIM output compare fast disable
+    TIM_OCFast_Enable  = TIM_CCMR1_OC1FEN,                       ///< TIM output compare fast enable
+} TIMOCFE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Output_Compare_Clear_State
+/// @anchor TIM_Output_Compare_Clear_State
+typedef enum {
+    TIM_OCClear_Disable = 0,                                    ///< TIM Output clear disable
+    TIM_OCClear_Enable  = TIM_CCMR1_OC1CEN                       ///< TIM Output clear enable
+} TIMOCCE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Master_Slave_Mode
+/// @anchor TIM_Master_Slave_Mode
+typedef enum {
+    TIM_MasterSlaveMode_Disable = 0,                            ///< No action
+    TIM_MasterSlaveMode_Enable  = TIM_SMCR_MSM                  ///< synchronization between the current timer and its slaves (through TRIG)
+} TIMMSM_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_interrupt_sources
+/// @anchor TIM_Master_Slave_Mode
+typedef enum {
+    TIM_IT_Update  = TIM_DIER_UI,                               ///< TIM update Interrupt source
+    TIM_IT_CC1     = TIM_DIER_CC1I,                             ///< TIM Capture Compare 1 Interrupt source
+    TIM_IT_CC2     = TIM_DIER_CC2I,                             ///< TIM Capture Compare 2 Interrupt source
+    TIM_IT_CC3     = TIM_DIER_CC3I,                             ///< TIM Capture Compare 3 Interrupt source
+    TIM_IT_CC4     = TIM_DIER_CC4I,                             ///< TIM Capture Compare 4 Interrupt source
+    TIM_IT_COM     = TIM_DIER_COMI,                             ///< TIM Commutation Interrupt source
+    TIM_IT_Trigger = TIM_DIER_TI,                               ///< TIM Trigger Interrupt source
+    TIM_IT_Break   = TIM_DIER_BI                                ///< TIM Break Interrupt source
+    , TIM_IT_CC5     = TIM_DIER_CC5I                            ///< TIM Capture Compare 5 Interrupt source
+} TIMIT_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_Flags
+/// @anchor TIM_Flags
+typedef enum {
+    TIM_FLAG_Update  = TIM_SR_UI,                              ///< TIM update Flag
+    TIM_FLAG_CC1     = TIM_SR_CC1I,                            ///< TIM Capture Compare 1 Flag
+    TIM_FLAG_CC2     = TIM_SR_CC2I,                            ///< TIM Capture Compare 2 Flag
+    TIM_FLAG_CC3     = TIM_SR_CC3I,                            ///< TIM Capture Compare 3 Flag
+    TIM_FLAG_CC4     = TIM_SR_CC4I,                            ///< TIM Capture Compare 4 Flag
+    TIM_FLAG_COM     = TIM_SR_COMI,                            ///< TIM Commutation Flag
+    TIM_FLAG_Trigger = TIM_SR_TI,                              ///< TIM Trigger Flag
+    TIM_FLAG_Break   = TIM_SR_BI,                              ///< TIM Break Flag
+    TIM_FLAG_CC1OF   = TIM_SR_CC1O,                            ///< TIM Capture Compare 1 overcapture Flag
+    TIM_FLAG_CC2OF   = TIM_SR_CC2O,                            ///< TIM Capture Compare 2 overcapture Flag
+    TIM_FLAG_CC3OF   = TIM_SR_CC3O,                            ///< TIM Capture Compare 3 overcapture Flag
+    TIM_FLAG_CC4OF   = TIM_SR_CC4O                             ///< TIM Capture Compare 4 overcapture Flag
+    , TIM_FLAG_CC5    = TIM_SR_CC5I                            ///< TIM Capture Compare 5 Flag
+} TIMFLAG_Typedef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DMA_sources
+/// @anchor TIM_DMA_sources
+typedef enum {
+    TIM_DMA_Update  = TIM_DIER_UD,                              ///< TIM update Interrupt source
+    TIM_DMA_CC1     = TIM_DIER_CC1D,                            ///< TIM Capture Compare 1 DMA source
+    TIM_DMA_CC2     = TIM_DIER_CC2D,                            ///< TIM Capture Compare 2 DMA source
+    TIM_DMA_CC3     = TIM_DIER_CC3D,                            ///< TIM Capture Compare 3 DMA source
+    TIM_DMA_CC4     = TIM_DIER_CC4D,                            ///< TIM Capture Compare 4 DMA source
+    TIM_DMA_COM     = TIM_DIER_COMD,                            ///< TIM Commutation DMA source
+    TIM_DMA_Trigger = TIM_DIER_TD                               ///< TIM Trigger DMA source
+} TIMDMASRC_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DMA_Base_address
+/// @anchor TIM_DMA_Base_address
+typedef enum {
+    TIM_DMABase_CR1   = 0x0000,
+    TIM_DMABase_CR2   = 0x0001,
+    TIM_DMABase_SMCR  = 0x0002,
+    TIM_DMABase_DIER  = 0x0003,
+    TIM_DMABase_SR    = 0x0004,
+    TIM_DMABase_EGR   = 0x0005,
+    TIM_DMABase_CCMR1 = 0x0006,
+    TIM_DMABase_CCMR2 = 0x0007,
+    TIM_DMABase_CCER  = 0x0008,
+    TIM_DMABase_CNT   = 0x0009,
+    TIM_DMABase_PSC   = 0x000A,
+    TIM_DMABase_ARR   = 0x000B,
+    TIM_DMABase_RCR   = 0x000C,
+    TIM_DMABase_CCR1  = 0x000D,
+    TIM_DMABase_CCR2  = 0x000E,
+    TIM_DMABase_CCR3  = 0x000F,
+    TIM_DMABase_CCR4  = 0x0010,
+    TIM_DMABase_BDTR  = 0x0011,
+    TIM_DMABase_DCR   = 0x0012
+} TIMDMABASE_Typedef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DMA_Burst_Length
+/// @anchor TIM_DMA_Burst_Length
+typedef enum {
+    TIM_DMABurstLength_1Byte   = 0x0000,
+    TIM_DMABurstLength_2Bytes  = 0x0100,
+    TIM_DMABurstLength_3Bytes  = 0x0200,
+    TIM_DMABurstLength_4Bytes  = 0x0300,
+    TIM_DMABurstLength_5Bytes  = 0x0400,
+    TIM_DMABurstLength_6Bytes  = 0x0500,
+    TIM_DMABurstLength_7Bytes  = 0x0600,
+    TIM_DMABurstLength_8Bytes  = 0x0700,
+    TIM_DMABurstLength_9Bytes  = 0x0800,
+    TIM_DMABurstLength_10Bytes = 0x0900,
+    TIM_DMABurstLength_11Bytes = 0x0A00,
+    TIM_DMABurstLength_12Bytes = 0x0B00,
+    TIM_DMABurstLength_13Bytes = 0x0C00,
+    TIM_DMABurstLength_14Bytes = 0x0D00,
+    TIM_DMABurstLength_15Bytes = 0x0E00,
+    TIM_DMABurstLength_16Bytes = 0x0F00,
+    TIM_DMABurstLength_17Bytes = 0x1000,
+    TIM_DMABurstLength_18Bytes = 0x1100
+} TIMDMABURSTLENGTH_Typedef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  TIM Time Base Init structure definition
+/// @note   This structure is used with all tim.
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    u16 TIM_Prescaler;                                          ///< Specifies the prescaler value used to divide the TIM clock.
+    ///< This parameter can be a number between 0x0000 and 0xFFFF
+    TIMCOUNTMODE_Typedef TIM_CounterMode;                       ///< Specifies the counter mode.
+    ///< This parameter can be a value of @ref TIM_Counter_Mode
+    u32 TIM_Period;                                             ///< Specifies the period value to be loaded into the active
+    ///< Auto-Reload Register at the next update event.
+    ///< This parameter must be a number between 0x0000 and 0xFFFF/0xFFFFFFFF.
+    ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5.
+    TIMCKD_TypeDef TIM_ClockDivision;                           ///< Specifies the clock division.
+    ///< This parameter can be a value of @ref TIM_Clock_Division_CKD
+    u8 TIM_RepetitionCounter;                                   ///< Specifies the repetition counter value. Each time the RCR downcounter
+    ///< reaches zero, an update event is generated and counting restarts
+    ///< from the RCR value (N).
+    ///< This means in PWM mode that (N+1) corresponds to:
+    ///<    - the number of PWM periods in edge-aligned mode
+    ///<    - the number of half PWM period in center-aligned mode
+    ///< This parameter must be a number between 0x00 and 0xFF.
+    ///< @note This parameter is valid only for TIM1 and TIM8.
+} TIM_TimeBaseInitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  TIM Output Compare Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    TIMOCMODE_Typedef TIM_OCMode;                               ///< Specifies the TIM mode.
+    ///< This parameter can be a value of TIM_Output_Compare_and_PWM_modes
+    TIMOUTPUTSTATE_Typedef TIM_OutputState;                     ///< Specifies the TIM Output Compare state.
+    ///< This parameter can be a value of TIM_Output_Compare_state
+    TIMOUTPUTNSTATE_Typedef TIM_OutputNState;                   ///< Specifies the TIM complementary Output Compare state.
+    ///< This parameter can be a value of TIM_Output_Compare_N_state
+    ///< @note This parameter is valid only for TIM1 and TIM8.
+    u32 TIM_Pulse;                                              ///< Specifies the pulse value to be loaded into the Capture Compare Register.
+    ///< This parameter can be a number between 0x0000 and 0xFFFF/0xFFFFFFFF
+    ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5.
+    TIMCCxP_Typedef TIM_OCPolarity;                             ///< Specifies the output polarity.
+    ///< This parameter can be a value of @ref TIM_Output_Compare_Polarity
+    TIMCCxNP_Typedef TIM_OCNPolarity;                           ///< Specifies the complementary output polarity.
+    ///< This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+    ///< @note This parameter is valid only for TIM1 and TIM8.
+    TIMOIS_Typedef TIM_OCIdleState;                             ///< Specifies the TIM Output Compare pin state during Idle state.
+    ///< This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+    ///< @note This parameter is valid only for TIM1 and TIM8.
+    TIMOISN_Typedef TIM_OCNIdleState;                           ///< Specifies the TIM Output Compare pin state during Idle state.
+    ///< This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+    ///< @note This parameter is valid only for TIM1 and TIM8.
+} TIM_OCInitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  TIM Input Capture Init structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    TIMCHx_Typedef TIM_Channel;                                 ///< Specifies the TIM channel.
+    ///< This parameter can be a value of @ref TIM_Channel
+    TIMICP_Typedef TIM_ICPolarity;                              ///< Specifies the active edge of the input signal.
+    ///< This parameter can be a value of @ref TIM_Input_Capture_Polarity
+    TIMICSEL_Typedef TIM_ICSelection;                           ///< Specifies the input.
+    ///< This parameter can be a value of @ref TIM_Input_Capture_Selection
+    TIMICPSC_Typedef TIM_ICPrescaler;                           ///< Specifies the Input Capture Prescaler.
+    ///< This parameter can be a value of @ref TIM_Input_Capture_Prescaler
+    u16 TIM_ICFilter;                                           ///< Specifies the input capture filter.
+    ///< This parameter can be a number between 0x0 and 0xF
+} TIM_ICInitTypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  BDTR structure definition
+/// @note   This structure is used only with TIM1 and TIM8.
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    TIMOSSR_Typedef TIM_OSSRState;                              ///< Specifies the Off-State selection used in Run mode.
+    ///< This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state
+    TIMOSSI_Typedef TIM_OSSIState;                              ///< Specifies the Off-State used in Idle state.
+    ///< This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state
+    TIMLOCKLEVEL_Typedef TIM_LOCKLevel;                         ///< Specifies the LOCK level parameters.
+    ///< This parameter can be a value of @ref Lock_level
+    u16 TIM_DeadTime;                                           ///< Specifies the delay time between the switching-off and
+    ///< the switching-on of the outputs.
+    ///< This parameter can be a number between 0x00 and 0xFF
+    TIMBKE_Typedef TIM_Break;                                   ///< Specifies whether the TIM Break input is enabled or not.
+    ///< This parameter can be a value of @ref Break_Input_enable_disable
+    TIMBKP_Typedef TIM_BreakPolarity;                           ///< Specifies the TIM Break Input pin polarity.
+    ///< This parameter can be a value of @ref Break_Polarity
+    TIMAOE_Typedef TIM_AutomaticOutput;                         ///< Specifies whether the TIM Automatic Output feature is enabled or not.
+    ///< This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset
+} TIM_BDTRInitTypeDef;
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup TIM_Exported_Variables
+/// @{
+#ifdef _HAL_TIM_C_
+#define GLOBAL
+
+static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
+static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
+static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
+static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
+
+
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup TIM_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+//=================  TimeBase management  ======================================
+void TIM_DeInit(TIM_TypeDef* tim);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct);
+void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct);
+void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reload_mode);
+void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode);
+void TIM_SetCounter(TIM_TypeDef* tim, u32 counter);
+void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload);
+void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state);
+void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source);
+void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state);
+void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode);
+void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div);
+void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state);
+
+u32 TIM_GetCounter(TIM_TypeDef* tim);
+u16 TIM_GetPrescaler(TIM_TypeDef* tim);
+
+//=================  Advanced-control timers specific features  ================
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct);
+void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state);
+
+//=================  Output Compare management  ================================
+void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct);
+void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
+void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
+void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
+void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
+void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode);
+void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare);
+void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare);
+void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare);
+void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare);
+void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
+void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
+void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
+void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
+void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state);
+void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
+void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
+void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
+void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
+void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
+void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
+void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
+void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
+void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
+void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en);
+void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en);
+void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state);
+
+//=================  Input Capture management  =================================
+void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct);
+void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct);
+void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct);
+void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
+void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
+void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
+void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
+
+u32 TIM_GetCapture1(TIM_TypeDef* tim);
+u32 TIM_GetCapture2(TIM_TypeDef* tim);
+u32 TIM_GetCapture3(TIM_TypeDef* tim);
+u32 TIM_GetCapture4(TIM_TypeDef* tim);
+
+//=================  Interrupts, DMA and flags management  =====================
+void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);//TIMIT_TypeDef
+void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source);
+void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag);
+void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it);//TIMIT_TypeDef
+void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length);
+void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state);
+void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag);
+ITStatus   TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it);
+
+//=================  Clocks management  ========================================
+void TIM_InternalClockConfig(TIM_TypeDef* tim);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
+
+//=================  Synchronization management  ===============================
+void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source);
+void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source);
+void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode);
+void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
+
+//=================  Specific interface management  ============================
+void TIM_EncoderInterfaceConfig(TIM_TypeDef*          tim,
+                                TIMSMSENCODER_Typedef encoder_mode,
+                                TIMICP_Typedef        ic1_polarity,
+                                TIMICP_Typedef        iC2_polarity);
+void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state);
+
+//=================  extend Channel IC management  ==============================
+void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
+void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
+void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
+void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
+
+#define exTIM_SetIC1Plority                     TIM_SetIC1Plority
+#define exTIM_SetIC2Plority                     TIM_SetIC2Plority
+#define exTIM_SetIC3Plority                     TIM_SetIC3Plority
+#define exTIM_SetIC4Plority                     TIM_SetIC4Plority
+//=================  extend Channel 5 management  ==============================
+
+void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare);
+void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
+void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
+void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
+void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
+void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
+u32 TIM_GetCapture5(TIM_TypeDef* tim);
+
+#define exTIM_SetCompare5                       TIM_SetCompare5
+#define exTIM_OC5Init                           TIM_OC5Init
+#define exTIM_OC5PreloadConfig                  TIM_OC5PreloadConfig
+#define exTIM_OC5PolarityConfig                 TIM_OC5PolarityConfig
+#define exTIM_OC5FastConfig                     TIM_OC5FastConfig
+#define exTIM_ClearOC5Ref                       TIM_ClearOC5Ref
+#define exTIM_GetCapture5                       TIM_GetCapture5
+
+//============= extend Advanced-control timers specific features  ==============
+void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state);
+#define exTIM_DirectOutput TIM_DirectOutput
+void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);
+void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift);
+void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift);
+void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift);
+void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift);
+void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift);
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_TIM_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h
new file mode 100644
index 000000000..a46f234e0
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h
@@ -0,0 +1,211 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_uart.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_UART_H
+#define __HAL_UART_H
+
+// Files includes
+#include "reg_uart.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+/////////////////////////////////////1///////////////////////////////////////////
+/// @defgroup UART_HAL
+/// @brief UART HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Types
+/// @{
+///
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Word Length Enumerate definition
+/// @anchor UART_Word_Length
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    UART_WordLength_5b = 0U,
+    UART_WordLength_6b = 1U << UART_CCR_CHAR_Pos,
+    UART_WordLength_7b = 2U << UART_CCR_CHAR_Pos,
+    UART_WordLength_8b = 3U << UART_CCR_CHAR_Pos
+} UART_WordLength_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Stop Bits Enumerate definition
+/// @anchor UART_Stop_Bits
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    UART_StopBits_1 = 0U,
+    UART_StopBits_2 = UART_CCR_SPB,
+
+    UART_StopBits_0_5 = UART_CCR_SPB1,
+    UART_StopBits_1_5 = UART_CCR_SPB1 | UART_CCR_SPB0,
+} UART_Stop_Bits_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Parity Enumerate definition
+/// @anchor UART_Parity
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    UART_Parity_No   = 0U,
+    UART_Parity_Even = UART_CCR_PEN | UART_CCR_PSEL,
+    UART_Parity_Odd  = UART_CCR_PEN
+} UART_Parity_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Hardware Flow Control Enumerate definition
+/// @anchor UART_Hardware_Flow_Control
+////////////////////////////////////////////////////////////////////////////////
+typedef enum {
+    UART_HWFlowControl_None    = 0U,
+
+    //    UART_HWFlowControl_RTS     = UART_GCR_AUTOFLOW,
+    //    UART_HWFlowControl_CTS     = UART_GCR_AUTOFLOW,
+
+    UART_HWFlowControl_RTS_CTS = UART_GCR_AUTOFLOW
+} UART_HW_FLOWCONTROL_TypeDef;
+
+typedef enum {
+    UART_WakeUp_IdleLine    = 0U,  //
+    UART_WakeUp_AddressMark = UART_CCR_WAKE
+} UART_WakeUp_TypeDef;
+
+typedef enum {
+    UART_9bit_Polarity_Low  = 0U,  //
+    UART_9bit_Polarity_High = UART_CCR_B8POL
+} UART_9bit_Polarity_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Auto BaudRate definition
+////////////////////////////////////////////////////////////////////////////////
+typedef enum  {
+    Data_F8 = 0,
+    Data_FE,
+    ABRMODE_FALLING_TO_RISINGEDGE1BIT,
+    ABRMODE_FALLING_TO_RISINGEDGE2BIT,
+    ABRMODE_FALLING_TO_RISINGEDGE4BIT,
+    ABRMODE_FALLING_TO_RISINGEDGE8BIT,
+    ABRMODE_FALLING_TO_FALLINGEDGE2BIT,
+    ABRMODE_FALLING_TO_FALLINGEDGE4BIT,
+    ABRMODE_FALLING_TO_FALLINGEDGE8BIT,
+    ABRMODE_STARTBIT,
+    ABRMODE_VALUE0X55,
+    ABRMODE_VALUE0x7F,
+    ABRMODE_VALUE0X80,
+    ABRMODE_VALUE0XF7,
+    ABRMODE_VALUE0XF8 = Data_F8,
+    ABRMODE_VALUE0XFE = Data_FE,
+    ABRMODE_VALUE0XFF,
+} UART_AutoBaud_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Init Structure definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    union {
+        u32                         BaudRate;                           ///< This member configures the UART communication baud rate.
+        u32                         UART_BaudRate;
+    };
+    union {
+        UART_WordLength_TypeDef     WordLength;                         ///< Specifies the number of data bits transmitted or received in a frame.
+        u16                         UART_WordLength;
+    };
+    union {
+        UART_Stop_Bits_TypeDef      StopBits;                           ///< Specifies the number of stop bits transmitted.
+        u16                         UART_StopBits;
+    };
+    union {
+        UART_Parity_TypeDef         Parity;                             ///< Specifies the parity mode.
+        u16                         UART_Parity;
+    };
+    union {
+        u16                         Mode;                               ///< Specifies wether the Receive or Transmit mode is
+        u16                         UART_Mode;
+    };
+    union {
+        UART_HW_FLOWCONTROL_TypeDef HWFlowControl;                      ///< Specifies wether the hardware flow control mode is enabled or disabled.
+        u16                         UART_HardwareFlowControl;
+    };
+} UART_InitTypeDef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Constants
+/// @{
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Variables
+/// @{
+#ifdef _HAL_UART_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Functions
+/// @{
+void UART_DeInit(UART_TypeDef* uart);
+void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct);
+void UART_StructInit(UART_InitTypeDef* init_struct);
+void UART_Cmd(UART_TypeDef* uart, FunctionalState state);
+void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state);
+void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state);
+void UART_SendData(UART_TypeDef* uart, u16 Data);
+void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it);
+
+u16        UART_ReceiveData(UART_TypeDef* uart);
+FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag);
+
+ITStatus   UART_GetITStatus(UART_TypeDef* uart, u16 it);
+
+void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode);
+void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state);
+void UART_SetRXAddress(UART_TypeDef* uart, u8 address);
+void UART_SetRXMASK(UART_TypeDef* uart, u8 address);
+void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state);
+void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state);
+void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity);
+void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state);
+void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state);
+void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time);
+void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state);
+void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state);
+void UART_SendBreak(UART_TypeDef* uart);
+void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state);
+void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_UART_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h
new file mode 100644
index 000000000..2dba789d2
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h
@@ -0,0 +1,71 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_uid.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UID
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_UID_H
+#define __HAL_UID_H
+
+// Files includes
+#include "types.h"
+#include "reg_common.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UID_HAL
+/// @brief UID HAL modules
+/// @{
+
+
+/////////////////////////////////////1///////////////////////////////////////////
+/// @defgroup UID_Exported_Variables
+/// @{
+#ifdef _HAL_UID_C_
+#define GLOBAL
+
+#else
+#define GLOBAL extern
+
+
+#endif
+GLOBAL u8 device_id_data[12];
+
+#undef GLOBAL
+
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UID_Exported_Functions
+/// @{
+void GetChipUID(void);
+
+/// @}
+
+
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_UID_H 
+////////////////////////////////////////////////////////////////////////////////
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h
new file mode 100644
index 000000000..773af5631
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h
@@ -0,0 +1,89 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_ver.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_VER_H
+#define __HAL_VER_H
+
+// Files includes
+#include "reg_common.h"
+#include "reg_dbg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+/////////////////////////////////////1///////////////////////////////////////////
+/// @defgroup UART_HAL
+/// @brief UART HAL modules
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Types
+/// @{
+///
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Word Length Enumerate definition
+/// @anchor UART_Word_Length
+////////////////////////////////////////////////////////////////////////////////
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Constants
+/// @{
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Variables
+/// @{
+#ifdef _HAL_VER_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup UART_Exported_Functions
+/// @{
+
+u32            Get_MM32LibVersion(void);
+u32            Get_ChipsetREVID(void);
+u32            Get_ChipsetDEVID(void);
+u32            Get_ChipsetUIDw0(void);
+u32            Get_ChipsetUIDw1(void);
+u32            Get_ChipsetUIDw2(void);
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_VER_H 
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h
new file mode 100644
index 000000000..287ddd5c8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h
@@ -0,0 +1,90 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_wwdg.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE WWDG
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT O
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDER
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __HAL_WWDG_H
+#define __HAL_WWDG_H
+
+// Files includes
+#include "types.h"
+#include "reg_wwdg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup WWDG_HAL
+/// @brief WWDG HAL modules
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup WWDG_Exported_Types
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  WWDG_Prescaler
+/// @anchor WWDG_Prescaler
+
+typedef enum {
+    WWDG_Prescaler_1 = WWDG_CFGR_WDGTB_1,
+    WWDG_Prescaler_2 = WWDG_CFGR_WDGTB_2,
+    WWDG_Prescaler_4 = WWDG_CFGR_WDGTB_4,
+    WWDG_Prescaler_8 = WWDG_CFGR_WDGTB_8
+} WWDG_Prescaler_Typedef;
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup WWDG_Exported_Variables
+/// @{
+
+#ifdef _HAL_WWDG_C_
+
+#define GLOBAL
+#else
+#define GLOBAL extern
+#endif
+
+#undef GLOBAL
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup WWDG_Exported_Functions
+/// @{
+
+void       WWDG_DeInit(void);
+void       WWDG_SetPrescaler(u32 prescaler);
+void       WWDG_SetWindowValue(u8 window_value);
+void       WWDG_EnableIT(void);
+void       WWDG_SetCounter(u8 count);
+u32        WWDG_GetCounter(void);
+void       WWDG_Enable(u8 count);
+FlagStatus WWDG_GetFlagStatus(void);
+void       WWDG_ClearFlag(void);
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __HAL_WWDG_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c
new file mode 100644
index 000000000..503e91a67
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c
@@ -0,0 +1,563 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_adc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE ADC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_ADC_C_
+
+// Files includes
+#include "hal_adc.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup ADC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup ADC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the adc peripheral registers to their default
+///         reset values.
+/// @param  adc: select the ADC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_DeInit(ADC_TypeDef* adc)
+{
+
+    switch (*(vu32*)&adc) {
+
+        case ADC1_BASE:
+            exRCC_APB2PeriphReset(RCC_APB2ENR_ADC1);
+            break;
+        case ADC2_BASE:
+            exRCC_APB2PeriphReset(RCC_APB2ENR_ADC2);
+            break;
+        case ADC3_BASE:
+            exRCC_APB2PeriphReset(RCC_APB2ENR_ADC3);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the adc peripheral according to the specified parameters
+///         in the init_struct, Please use this function if you want to be
+///         compatible with older versions of the library.
+/// @param  adc: select the ADC peripheral.
+/// @param  init_struct: pointer to an ADC_InitTypeDef structure that contains
+///         the configuration information for the specified ADC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct)
+{
+    adc->ADCFG &= ~(ADC_CFGR_PRE | ADC_CFGR_RSLTCTL);
+    adc->ADCFG |= (u32)(init_struct->ADC_PRESCARE) | init_struct->ADC_Resolution;
+
+    adc->ADCR &= ~(ADC_CR_ALIGN | ADC_CR_MODE | ADC_CR_TRGSEL);
+    adc->ADCR |= ((u32)init_struct->ADC_DataAlign) | init_struct->ADC_ExternalTrigConv | ((u32)init_struct->ADC_Mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct : pointer to an ADC_InitTypeDef structure which will be
+///         initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_StructInit(ADC_InitTypeDef* init_struct)
+{
+    init_struct->ADC_Resolution         = ADC_Resolution_12b;
+    init_struct->ADC_PRESCARE           = ADC_PCLK2_PRESCARE_2;
+    init_struct->ADC_Mode               = ADC_CR_IMM;                           //ADC_Mode_Single;
+    init_struct->ADC_ContinuousConvMode = DISABLE;                              // useless
+    init_struct->ADC_ExternalTrigConv   = ADC1_ExternalTrigConv_T1_CC1;
+    init_struct->ADC_DataAlign          = ADC_DataAlign_Right;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified ADC peripheral.
+/// @param  adc:select the ADC peripheral.
+/// @param  state: new state of the adc peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ADCFG |= ADC_CFGR_ADEN) : (adc->ADCFG &= ~ADC_CFGR_ADEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified ADC DMA request.
+/// @param  adc: select the ADC peripheral.
+/// @param  state: New state of the selected ADC DMA transfer.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ADCR |= ADC_CR_DMAEN) : (adc->ADCR &= ~ADC_CR_DMAEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified ADC interrupts.
+/// @param  adc: select the ADC peripheral.
+/// @param  adc_interrupt: specifies the ADC interrupt sources to be enabled or disabled.
+/// @param  state: New state of the specified ADC interrupts.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state)
+{
+    if (adc_interrupt == ADC_IT_EOC)
+        (state) ? (adc->ADCR |= ADC_CR_ADIE) : (adc->ADCR &= ~ADC_CR_ADIE);
+    else
+        (state) ? (adc->ADCR |= ADC_CR_ADWIE) : (adc->ADCR &= ~ADC_CR_ADWIE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected ADC software start conversion .
+/// @param  adc:  select the ADC peripheral.
+/// @param  state: New state of the selected ADC software start conversion.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ADCR |= ADC_CR_ADST) : (adc->ADCR &= ~ADC_CR_ADST);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the selected ADC Software start conversion Status.
+/// @param  adc: select the ADC peripheral.
+/// @retval  The new state of ADC software start conversion (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc)
+{
+    return (((adc->ADCR & ADC_CR_ADST) != (u32)RESET) ? SET : RESET);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable the selected ADC channel and configure its sample time. Please
+///         use this function if you want to be compatible with older versions
+///         of the library.
+/// @param  adc:  select the ADC peripheral.
+/// @param  channel: the ADC channel to configure.
+/// @param  sample_time: the ADC Channel n Sample time to configure.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time)    //ADCSAM_TypeDef
+{
+
+    u32 tempchan;
+    sample_time = sample_time & 0xF;
+    tempchan = channel;
+    if(tempchan > 8) {
+        tempchan = tempchan & 0xF;
+        tempchan = tempchan - 8;
+        adc->SMPR2 &= ~(0xF << tempchan);
+        adc->SMPR2 |= (sample_time << tempchan);
+    }
+    else {
+        adc->SMPR1 &= ~(0xF << tempchan);
+        adc->SMPR1 |= (sample_time << tempchan);
+    }
+    adc->ADCHS &= ~(1 << channel);
+    adc->ADCHS |=  (1 << channel);
+
+    if (channel & ADC_CHSR_CHT)
+        ADC_TempSensorVrefintCmd(ENABLE);
+    else if (channel & ADC_CHSR_CHV)
+        ADC_TempSensorVrefintCmd(ENABLE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the adc conversion through external trigger.
+/// @param  adc: select the ADC peripheral.
+/// @param  state: New state of the selected ADC external trigger.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ADCR |= ADC_CR_TRGEN) : (adc->ADCR &= ~ADC_CR_TRGEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the adc external trigger for injected channels conversion.
+/// @param  adc:  select the ADC peripheral.
+/// @param  adc_external_trig_source: Configuring the external trigger source
+///         for the ADC.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source)
+{
+    adc->ADCR &= ~ADC_CR_TRGSEL;
+    adc->ADCR |=  adc_external_trig_source;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the last adc conversion result data for regular channel.
+/// @param  adc: select the ADC peripheral.
+/// @retval The data conversion value.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetConversionValue(ADC_TypeDef* adc)
+{
+    return (u16)adc->ADDATA;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the last ADC conversion result data in dual mode.
+/// @param  None
+/// @retval The Data conversion value.
+////////////////////////////////////////////////////////////////////////////////
+u32 ADC_GetDualModeConversionValue()
+{
+    return (*(vu32*)ADC1_BASE);
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the analog watchdog.
+/// @param  adc:  to select the ADC peripheral.
+/// @param  state: New state of the selected ADC analog watchdog.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ADCFG |= ADC_CFGR_ADWEN) : (adc->ADCFG &= ~ADC_CFGR_ADWEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the high and low thresholds of the analog watchdog.
+/// @param  adc:  select the ADC peripheral.
+/// @param  high_threshold: the ADC analog watchdog High threshold value.
+///         This parameter must be a 12bit value.
+/// @param  low_threshold: the ADC analog watchdog Low threshold value.
+///         This parameter must be a 12bit value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold)
+{
+    u32 tempThreshold;
+    tempThreshold = high_threshold;
+    adc->ADCMPR    = (tempThreshold << 16) | low_threshold;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the analog watchdog guarded single channel
+/// @param  adc: select the ADC peripheral.
+/// @param  channel: the ADC channel to configure for the analog watchdog.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel)
+{
+    adc->ADCR &= ~ADC_CR_CMPCH;
+    adc->ADCR |= (channel << ADC_CR_CMPCH_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the temperature sensor and Vrefint channel.
+/// @param  state: New state of the temperature sensor.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_TempSensorVrefintCmd(FunctionalState state)
+{
+    (state) ? (ADC1->ADCFG |=  (ADC_CFGR_TEN | ADC_CFGR_VEN))
+    : (ADC1->ADCFG &= ~(ADC_CFGR_TEN | ADC_CFGR_VEN));
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the temperature sensor .
+/// @param  state: New state of the temperature sensor.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_TempSensorCmd(FunctionalState state)
+{
+    ADC_TempSensorVrefintCmd(state);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Vrefint channel.
+/// @param  state: New state of the Vrefint channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_VrefintCmd(FunctionalState state)
+{
+    ADC_TempSensorVrefintCmd(state);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the temperature sensor and Vrefint channel.
+/// @param  chs: temperature sensor bit & Vrefint bit.
+/// @param  state: New state of the temperature sensor.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state)
+{
+    if (chs & ADC_CHSR_CHT) {
+        (state) ? (ADC1->ADCFG |=  ADC_CFGR_TEN)
+        : (ADC1->ADCFG &= ~ADC_CFGR_TEN);
+    }
+    else if (chs & ADC_CHSR_CHV) {
+        (state) ? (ADC1->ADCFG |=  ADC_CFGR_VEN)
+        : (ADC1->ADCFG &= ~ADC_CFGR_VEN);
+    }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified ADC flag is set or not.
+/// @param  adc: select the ADC peripheral.
+/// @param  adc_flag: specifies the flag to check.
+/// @retval The New state of adc_flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag)
+{
+    return (adc_flag == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the adc's pending flags.
+/// @param  adc: select the ADC peripheral.
+/// @param  adc_flag: specifies the flag to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag)
+{
+    (adc_flag == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified adc's interrupt has occurred or not.
+/// @param  adc: select the ADC peripheral.
+/// @param  adc_interrupt: specifies the ADC interrupt source to check.
+/// @retval The new state of adc_interrupt (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt)
+{
+    return (adc_interrupt == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the adc's interrupt pending bits.
+/// @param  adc: select the ADC peripheral.
+/// @param  adc_interrupt: specifies the ADC interrupt pending bit to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt)
+{
+    (adc_interrupt == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the adc any channels conversion rank and channel.
+/// @param  adc: select the ADC peripheral.
+/// @param  rank: rank can be 0x0~0xf for the convert sequence.
+/// @param  adc_channel: Configuring the target channel to be converted.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel)
+{
+    rank = rank & 0xF;
+    if(rank < 8) {
+        adc->CHANY0 &= ~(0x0F << (4 * rank));
+        adc->CHANY0 |= (adc_channel << (4 * rank));
+    }
+    else {
+        adc->CHANY1 &= ~(0x0F << (4 * (rank - 8)));
+        adc->CHANY1 |= (adc_channel << (4 * (rank - 8)));
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the adc any channels conversion Max rank number
+/// @param  adc: select the ADC peripheral.
+/// @param  num: Configuring the max rank number for the ADC.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num)
+{
+    if(num > 15) num = 15;                                                      //15 ? 16 need to be confirmed
+    adc->ANYCFG = num;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the ANY channel converter.
+/// @param  state: enable or disable the ANY channel converter mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ANYCR |= ADC1_CHANY_CR_MDEN) : (adc->ANYCR &= ~ADC1_CHANY_CR_MDEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected ADC automatic injected group
+///         conversion after regular one.
+/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param  state: new state of the selected ADC auto injected conversion
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ANYCR |= ADC_ANY_CR_JAUTO) : (adc->ANYCR &= ~ADC_ANY_CR_JAUTO);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the adc external trigger for injected channels conversion.
+/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param  ADC_ExtInjTrigSource: specifies the ADC trigger to start injected conversion.
+
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource)
+{
+    u32 tmpreg = 0;
+    // Get the old register value
+    tmpreg = adc->ANYCR;
+    // Clear the old external event selection for injected group
+    tmpreg &= ADC_ANY_CR_JTRGSEL;
+    // Set the external event selection for injected group
+    tmpreg |= ADC_ExtInjTrigSource;
+    // Store the new register value
+    adc->ANYCR = tmpreg;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the adc injected channels conversion through
+///         external trigger
+/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param  state: new state of the selected ADC external trigger start of
+///         injected conversion.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ANYCR |= ADC_ANY_CR_JTRGEN) : (adc->ANYCR &= ~ADC_ANY_CR_JTRGEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected ADC start of the injected
+///         channels conversion.
+/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param  state: new state of the selected ADC software start injected conversion.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ANYCR |= ADC_ANY_CR_JCEN) : (adc->ANYCR &= ~ADC_ANY_CR_JCEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected ADC start of the injected
+///         channels conversion.
+/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
+/// @param  NewState: new state of the selected ADC software start injected conversion.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None
+////////////////////////////////////////////////////////////////////////////////
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
+{
+    (state) ? (adc->ANYCR |= ADC_ANY_CR_JADST) : (adc->ANYCR &= ~ADC_ANY_CR_JADST);
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable the selected ADC channel and configure its sample time. Please
+///         use this function if you want to be compatible with older versions
+///         of the library.
+/// @param  adc:  select the ADC peripheral.
+/// @param  event: the ADC external event to configure.
+/// @param  sample_time: the ADC Channel n Sample time to configure.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time)
+{
+    adc->ANYCR &= ~(ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | ADC_ANY_CR_JTRGSEL_EXTI12 \
+                    | ADC_ANY_CR_JTRGSHIFT_512 | ADC_ANY_CR_JTRGEN);
+    adc->ANYCR |= (ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | sample_time | event | ADC_ANY_CR_JTRGEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Injection channel length configuration.
+/// @param  adc:  select the ADC peripheral.
+/// @param  Length: Injection channel length.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length)
+{
+    adc->JSQR &= ~(0x03 << ADC_JSQR_JL_Pos);
+    adc->JSQR |= Length << ADC_JSQR_JL_Pos;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Injection channel  configuration.
+/// @param  adc  :   select the ADC peripheral.
+/// @param  off_addr :   Injection channel offset address.
+/// @param  channel: The sampling channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel)
+{
+    adc->JSQR &= ~(0x1F << (off_addr >> 2) * 5);
+    adc->JSQR |= (channel <<  (off_addr >> 2) * 5);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Injection channel  converted value.
+/// @param  adc  :   select the ADC peripheral.
+/// @param  off_addr :   Injection channel offset address.
+/// @retval value.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr)
+{
+    u32 value;
+    value = (*(vu32*)(*(vu32*)&adc + 0xB0 + off_addr)) - (*(vu32*)(*(vu32*)&adc + 0x7C + off_addr));
+
+    return (u16)value;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Injection current converted value.
+/// @param  adc  :   select the ADC peripheral.
+/// @retval value. Returns the last adc conversion result data for injected channel.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc)
+{
+    return (u16)adc->JDATA;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Injection channel compensation configuration.
+/// @param  adc         : select the ADC peripheral.
+/// @param  off_addr    : Injection channel.
+/// @param  value       : compensation value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value)
+{
+    *(vu32*)(*(vu32*)&adc + 0x7C + off_addr) = value;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Get channel convertion result.
+/// @param  adc  :   select the ADC peripheral.
+/// @param  channel :   Converted channel.
+/// @retval The Data conversion value.
+////////////////////////////////////////////////////////////////////////////////
+u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel)
+{
+    return (u16)(*(vu32*) ((u32)adc + 0x18 + ((u32)channel << 2)));
+}
+
+/// @}
+
+/// @}
+
+/// @}
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c
new file mode 100644
index 000000000..323971dd3
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c
@@ -0,0 +1,231 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_bkp.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE BKP FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_BKP_C_
+
+// Files includes
+#include "types.h"
+#include "hal_pwr.h"
+#include "hal_rcc.h"
+#include "hal_bkp.h"
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup BKP_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup BKP_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the BKP peripheral registers to their default reset
+///         values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_DeInit(void)
+{
+    RCC_BackupResetCmd(ENABLE);
+    RCC_BackupResetCmd(DISABLE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the Tamper Pin active level.
+/// @param  tamper_pin_level: specifies the Tamper Pin active level.
+///         This parameter can be one of the following values:
+/// @arg    BKP_TamperPinLevel_High: Tamper pin active on high level
+/// @arg    BKP_TamperPinLevel_Low: Tamper pin active on low level
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level)
+{
+    BKP->CR = tamper_pin_level;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Tamper Pin activation.
+/// @param  state: new state of the Tamper Pin activation.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_TamperPinCmd(FunctionalState state)
+{
+    (state) ? SET_BIT(BKP->CR, BKP_CR_TPE) : CLEAR_BIT(BKP->CR, BKP_CR_TPE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Tamper Pin Interrupt.
+/// @param  state: new state of the Tamper Pin Interrupt.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_ITConfig(FunctionalState state)
+{
+    (state) ? SET_BIT(BKP->CSR, BKP_CSR_TPIE) : CLEAR_BIT(BKP->CSR, BKP_CSR_TPIE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select the RTC output source to output on the Tamper pin.
+/// @param  rtc_output_source: specifies the RTC output source.
+///         This parameter can be one of the following values:
+/// @arg    BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
+/// @arg    BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
+///                                          divided by 64 on the Tamper pin.
+/// @arg    BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
+///                                     the Tamper pin.
+/// @arg    BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
+///                                      the Tamper pin.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source)
+{
+    MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS, rtc_output_source);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets RTC Clock Calibration value.
+/// @param  calibration_value: specifies the RTC Clock Calibration value.
+///         This parameter must be a number between 0 and 0x7F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_SetRTCCalibrationValue(u8 calibration_value)
+{
+    MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, calibration_value);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the Tamper Pin Event flag is set or not.
+/// @param  None.
+/// @retval State: The new state of the Tamper Pin Event flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus BKP_GetFlagStatus(void)
+{
+    return ((BKP->CSR & BKP_CSR_TEF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears Tamper Pin Event pending flag.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_ClearFlag(void)
+{
+    SET_BIT(BKP->CSR, BKP_CSR_CTE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
+/// @param  None.
+/// @retval State: The new state of the Tamper Pin Interrupt (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus BKP_GetITStatus(void)
+{
+    return ((BKP->CSR & BKP_CSR_TIF) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears Tamper Pin Interrupt pending bit.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_ClearITPendingBit(void)
+{
+    SET_BIT(BKP->CSR, BKP_CSR_CTI);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Writes user data to the specified data Backup Register.
+/// @param  bkp_dr: specifies the data Backup Register.
+///         This parameter can be BKP_DRx where x:[1, 10]
+/// @param  data: data to write
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data)
+{
+    *(vu16*)(BKP_BASE + bkp_dr) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads data from the specified data Backup Register.
+/// @param  bkp_dr: specifies the data Backup Register.
+///         This parameter can be BKP_DRx where x:[1, 10]
+/// @retval data: The content of the specified data Backup Register
+////////////////////////////////////////////////////////////////////////////////
+u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr)
+{
+    return (*(vu16*)(BKP_BASE + bkp_dr));
+}
+////////////////////////////////////////////////////////////////////////////////
+//          Extended function interface
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the BKP peripheral, enable access to the backup
+///         registers.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exBKP_Init(void)
+{
+    RCC_APB1PeriphClockCmd(RCC_APB1ENR_PWR, ENABLE);
+    //COMMON_EnableIpClock(emCLOCK_PWR);
+    RCC_APB1PeriphClockCmd(RCC_APB1ENR_BKP, ENABLE);
+    //COMMON_EnableIpClock(emCLOCK_BKP);
+
+    RCC->BDCR |= RCC_BDCR_DBP;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Writes user data to the specified data Backup Register immediately.
+/// @param  bkp_dr: specifies the data Backup Register.
+///         This parameter can be BKP_DRx where x:[1, 10]
+/// @param  data: data to write
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 dat)
+{
+    RCC->BDCR |= RCC_BDCR_DBP;
+    *(vu16*)(BKP_BASE + bkp_dr) = dat;
+    RCC->BDCR &= ~RCC_BDCR_DBP;
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads data from the specified data Backup Register immediately.
+/// @param  bkp_dr: specifies the data Backup Register.
+///         This parameter can be BKP_DRx where x:[1, 10]
+/// @retval data: The content of the specified data Backup Register
+////////////////////////////////////////////////////////////////////////////////
+u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr)
+{
+    u16 dat;
+    RCC->BDCR |= RCC_BDCR_DBP;
+    dat = (*(vu16*)(BKP_BASE + bkp_dr));
+    RCC->BDCR &= ~RCC_BDCR_DBP;
+    return dat;
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c
new file mode 100644
index 000000000..9dd85df29
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c
@@ -0,0 +1,696 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_can.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE CAN FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define __HAL_CAN_C
+
+// Files includes
+#include "hal_can.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CAN_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CAN_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the CAN peripheral registers to their default reset
+/// values.
+/// @param  can: select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_DeInit(CAN_TypeDef* can)
+{
+    exRCC_APB1PeriphReset(RCC_APB1ENR_CAN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief   Initializes the CAN peripheral according to the specified
+///          parameters in the CAN_InitStruct.
+/// @param   can: select the CAN peripheral.
+/// @param   CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+///          contains the configuration information for the CAN peripheral.
+/// @retval  Constant indicates initialization succeed which will be
+///          CANINITFAILED or CANINITOK.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* init_struct)
+{
+    u8 InitStatus = CANINITFAILED;
+
+    can->BTR0 = ((u32)(init_struct->SJW) << 6) | ((u32)(init_struct->BRP));
+    can->BTR1 = ((u32)(init_struct->SAM) << 7) | ((u32)(init_struct->TESG2) << 4) | ((u32)(init_struct->TESG1));
+
+    if (init_struct->GTS == ENABLE) {
+        can->CMR |= (u32)CAN_SleepMode;
+        InitStatus = CANINITFAILED;
+    }
+    else {
+        can->CMR &= ~(u32)CAN_SleepMode;
+        InitStatus = CANINITOK;
+    }
+
+    (init_struct->GTS == ENABLE) ? (can->CMR |= (u32)CAN_SleepMode) : (can->CMR &= ~(u32)CAN_SleepMode);
+
+    can->CDR |=
+        ((init_struct->CBP) << 6) | ((init_struct->RXINTEN) << 5) | ((init_struct->CLOSE_OPEN_CLK) << 3) | (init_struct->CDCLK);
+
+    return InitStatus;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the CAN_Basic reception filter according to the specified
+///         parameters in the basic_filter_init_struct.
+/// @param  basic_filter_init_struct: pointer to a CAN_Basic_FilterInitTypeDef
+///         structure that contains the configuration information.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct)
+{
+    // Filter Mode
+    CAN1->ACR = basic_filter_init_struct->CAN_FilterId;
+    CAN1->AMR = basic_filter_init_struct->CAN_FilterMaskId;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct : pointer to a CAN_Basic_InitTypeDef structure which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_StructInit(CAN_Basic_InitTypeDef* init_struct)
+{
+    // Reset CAN_Basic init structure parameters values
+
+    // initialize the BRP member(where can be set with (0..63))
+    init_struct->BRP = 0x0;
+    // initialize the SJW member(where can be set with (0..3))
+    init_struct->SJW = 0x0;
+    // Initialize the TESG1 member(where can be set with (0..15))
+    init_struct->TESG1 = 0x0;
+    // Initialize the TESG2 member(where can be set with(0..7))
+    init_struct->TESG2 = 0x0;
+    // Initialize the SAM member(where can be set (SET or RESET))
+    init_struct->SAM = RESET;
+    // Initialize the GTS member to Sleep Mode(where can be set (ENABLE or
+    // DISABLE))
+    init_struct->GTS = DISABLE;
+    // Initialize the external pin CLKOUT frequence
+    init_struct->CDCLK = 0x0;
+    // Initialize the external clk is open or close
+    init_struct->CLOSE_OPEN_CLK = 0x0;
+    // Initialize the TX1 pin work as rx interrupt output
+    init_struct->RXINTEN = 0x0;
+    // Initialize the CBP of CDR register
+    init_struct->CBP = 0x0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified CAN interrupts.
+/// @param  can:  select the CAN peripheral.
+/// @param  it: specifies the CAN interrupt sources to be enabled or
+///         disabled.
+///         This parameter can be: CAN_IT_OIE, CAN_IT_EIE, CAN_IT_TIE,
+///         CAN_IT_RIE.
+/// @param  state: new state of the CAN interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state)
+{
+    (state) ? (can->CR |= it) : (can->CR &= ~it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initiates and transmits a CAN frame message.
+/// @param  can:select the CAN peripheral.
+/// @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
+///         CAN data.
+/// @retval CANTXOK if the CAN driver transmits the message
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message)
+{
+    can->TXID0 = (basic_transmit_message->IDH);
+    can->TXID1 = (basic_transmit_message->IDL << 5) | (basic_transmit_message->RTR << 4) | (basic_transmit_message->DLC);
+    if ((FunctionalState)(basic_transmit_message->RTR) != ENABLE) {
+        can->TXDR0 = basic_transmit_message->Data[0];
+        can->TXDR1 = basic_transmit_message->Data[1];
+        can->TXDR2 = basic_transmit_message->Data[2];
+        can->TXDR3 = basic_transmit_message->Data[3];
+        can->TXDR4 = basic_transmit_message->Data[4];
+        can->TXDR5 = basic_transmit_message->Data[5];
+        can->TXDR6 = basic_transmit_message->Data[6];
+        can->TXDR7 = basic_transmit_message->Data[7];
+    }
+
+    can->CMR = CAN_CMR_TR;
+
+    return (can->SR & 0x01);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Cancels a transmit request.
+/// @param  can: select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_CancelTransmit(CAN_TypeDef* can)
+{
+    // abort transmission
+    can->CMR = CAN_AT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Releases the specified receive FIFO.
+/// @param  can: select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_FIFORelease(CAN_TypeDef* can)
+{
+    // Release FIFO
+    can->CMR |= (u32)CAN_RRB;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Receives a correct CAN frame.
+/// @param  can: select the CAN peripheral.
+/// @param  RxMessage: pointer to a structure receive frame which contains CAN
+///         Id,CAN DLC, CAN data and FMI number.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message)
+{
+    u16 tempid;
+
+    basic_receive_message->RTR = (u8)((can->RXID1) >> 4) & 0x1;
+    basic_receive_message->DLC = (u8)((can->RXID1) & 0xf);
+    tempid              = (u16)(((can->RXID1) & 0xe0) >> 5);
+    tempid |= (u16)(can->RXID0 << 3);
+    basic_receive_message->ID      = tempid;
+    basic_receive_message->Data[0] = CAN1->RXDR0;
+    basic_receive_message->Data[1] = CAN1->RXDR1;
+    basic_receive_message->Data[2] = CAN1->RXDR2;
+    basic_receive_message->Data[3] = CAN1->RXDR3;
+    basic_receive_message->Data[4] = CAN1->RXDR4;
+    basic_receive_message->Data[5] = CAN1->RXDR5;
+    basic_receive_message->Data[6] = CAN1->RXDR6;
+    basic_receive_message->Data[7] = CAN1->RXDR7;
+    CAN_FIFORelease(can);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select the Sleep mode or not in Basic workmode
+/// @param  state to go into the Sleep mode or go out
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Sleep(CAN_TypeDef* can)
+{
+    can->CMR |= CAN_SleepMode;
+    // At this step, sleep mode status
+    return (u8)((can->CMR & 0x10) == CAN_SleepMode) ? CANSLEEPOK : CANSLEEPFAILED;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Wakes the CAN up.
+/// @param  can: where x can be 1 to select the CAN peripheral.
+/// @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_WakeUp(CAN_TypeDef* can)
+{
+    // Wake up request
+    can->CMR &= ~CAN_SleepMode;
+    return (u8)((can->CMR & 0x01) == 0) ? CANWAKEUPOK : CANWAKEUPFAILED;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified CAN flag is set or not.
+/// @param  can: select the CAN peripheral.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+///            @arg CAN_STATUS_RBS: Receive buffer status
+///            @arg CAN_STATUS_DOS: Data overflow status
+///            @arg CAN_STATUS_TBS: Transmit buffer status
+///            @arg CAN_STATUS_TCS: Transmit complete status
+///            @arg CAN_STATUS_RS: Receiving status
+///            @arg CAN_STATUS_TS: Transmiting status
+///            @arg CAN_STATUS_ES: Error status
+///            @arg CAN_STATUS_BS: bus status, close or open
+/// @retval The new state of CAN_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag)
+{
+    return (FlagStatus)(((can->SR & flag) == flag) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified CAN interrupt has occurred or not.
+/// @param  can: where x can be 1 to select the CAN peripheral.
+/// @param  it: specifies the CAN interrupt source to check.
+///         This parameter can be one of the following values:
+///            @arg CAN_IT_RI: Receive FIFO not empty Interrupt
+///            @arg CAN_IT_TI: Transmit Interrupt
+///            @arg CAN_IT_EI: ERROR Interrupt
+///            @arg CAN_IT_DOI: Data voerflow Interrupt
+///            @arg CAN_IT_WUI: Wakeup Interrupt
+///            @arg CAN_IT_ALL: use it can enble all Interrupt
+/// @retval The current state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it)
+{
+    return (ITStatus)((can->IR & it) != it) ? RESET : SET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select the can work as peli mode or basic mode
+/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @param  CAN_MODE: specifies the work mode:CAN_BASICMode,CAN_PELIMode
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode)
+{
+    can->CDR |= mode;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select the Reset mode or not
+/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @param  state to go into the Reset mode or go out
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state)
+{
+    (state == ENABLE) ? (can->CR |= CAN_ResetMode) : (can->CR &= ~CAN_ResetMode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clear the data overflow.
+/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ClearDataOverflow(CAN_TypeDef* can)
+{
+    can->CMR |= (u32)CAN_CDO;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the CAN's IT pending.
+/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_ClearITPendingBit(CAN_TypeDef* can)
+{
+    u32 temp = 0;
+    temp     = temp;
+    temp     = can->IR;  // read this register clear all interrupt
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select the Sleep mode or not in Peli workmode
+/// @param  state to go into the Sleep mode or go out
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_SleepMode_Cmd(FunctionalState state)
+{
+    (state == ENABLE) ? (CAN1_PELI->MOD |= CAN_SleepMode) : (CAN1_PELI->MOD &= ~CAN_SleepMode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each CAN1_PELI_InitStruct member with its default value.
+/// @param  init_struct : pointer to a CAN_Peli_InitTypeDef structure
+///         which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* init_struct)
+{
+    //--------------- Reset CAN_Peli init structure parameters values
+    //---------------
+    init_struct->BRP   = 0x0;      // initialize the BRP member(where can be set with (0..63))
+    init_struct->SJW   = 0x0;      // initialize the SJW member(where can be set with (0..3))
+    init_struct->TESG1 = 0x0;      // Initialize the TESG1 member(where can be set with (0..15))
+    init_struct->TESG2 = 0x0;      // Initialize the TESG2 member(where can be set with(0..7))
+    init_struct->SAM   = RESET;    // Initialize the SAM member(where can be set (SET or RESET))
+    init_struct->LOM   = DISABLE;  // Initialize the LOM member
+    init_struct->STM   = DISABLE;  // Initialize the STM member
+    init_struct->SM    = DISABLE;  // Initialize the SM member
+    init_struct->SRR   = DISABLE;
+    init_struct->EWLR  = 0x96;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the CAN_Peli peripheral according to the specified
+///         parameters in the init_struct.
+/// @param  init_struct: pointer to a CAN_Peli_InitTypeDef structure that
+///         contains the configuration information for the CAN peripheral in the peli workmode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct)
+{
+    CAN1_PELI->BTR0 = ((u32)init_struct->SJW << 6) | ((u32)init_struct->BRP);
+    CAN1_PELI->BTR1 = ((u32)init_struct->SAM << 7) | ((u32)init_struct->TESG2 << 4) | ((u32)init_struct->TESG1);
+    if (init_struct->LOM == ENABLE)
+        CAN1_PELI->MOD |= (u32)CAN_ListenOnlyMode;
+    else
+        CAN1_PELI->MOD &= ~(u32)CAN_ListenOnlyMode;
+    if (init_struct->STM == ENABLE)
+        CAN1_PELI->MOD |= (u32)CAN_SeftTestMode;
+    else
+        CAN1_PELI->MOD &= ~(u32)CAN_SeftTestMode;
+    if (init_struct->SM == ENABLE)
+        CAN1_PELI->MOD |= (u32)CAN_SleepMode;
+    else
+        CAN1_PELI->MOD &= ~(u32)CAN_SleepMode;
+    CAN1_PELI->EWLR = (u32)init_struct->EWLR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the CAN_Peli reception filter according to the specified
+///         parameters in the peli_filter_init_struct.
+/// @param  peli_filter_init_struct: pointer to a CAN_Peli_FilterInitTypeDef
+///         structure that contains the configuration information.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct)
+{
+    (peli_filter_init_struct->AFM == CAN_FilterMode_Singal) ? (CAN1_PELI->MOD |= (u32)CAN_FilterMode_Singal)
+    : (CAN1_PELI->MOD &= (u32)CAN_FilterMode_Double);
+
+    CAN1_PELI->FF    = peli_filter_init_struct->CAN_FilterId0;
+    CAN1_PELI->ID0   = peli_filter_init_struct->CAN_FilterId1;
+    CAN1_PELI->ID1   = peli_filter_init_struct->CAN_FilterId2;
+    CAN1_PELI->DATA0 = peli_filter_init_struct->CAN_FilterId3;
+
+    CAN1_PELI->DATA1 = peli_filter_init_struct->CAN_FilterMaskId0;
+    CAN1_PELI->DATA2 = peli_filter_init_struct->CAN_FilterMaskId1;
+    CAN1_PELI->DATA3 = peli_filter_init_struct->CAN_FilterMaskId2;
+    CAN1_PELI->DATA4 = peli_filter_init_struct->CAN_FilterMaskId3;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each peli_filter_init_struct member with its default value.
+/// @param  peli_filter_init_struct: pointer to a CAN_InitTypeDef structure
+///         which ill be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct)
+{
+    peli_filter_init_struct->CAN_FilterId0 = 0;
+    peli_filter_init_struct->CAN_FilterId1 = 0;
+    peli_filter_init_struct->CAN_FilterId2 = 0;
+    peli_filter_init_struct->CAN_FilterId3 = 0;
+
+    peli_filter_init_struct->CAN_FilterMaskId0 = 0;
+    peli_filter_init_struct->CAN_FilterMaskId1 = 0;
+    peli_filter_init_struct->CAN_FilterMaskId2 = 0;
+    peli_filter_init_struct->CAN_FilterMaskId3 = 0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initiates and transmits a CAN frame message.
+/// @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
+///         CAN data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message)
+{
+    CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC);
+    if (((FunctionalState)peli_transmit_message->FF) != ENABLE) {
+        CAN1_PELI->ID0 = (peli_transmit_message->IDHH);
+
+        CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0);
+        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+            CAN1_PELI->DATA0 = peli_transmit_message->Data[0];
+            CAN1_PELI->DATA1 = peli_transmit_message->Data[1];
+            CAN1_PELI->DATA2 = peli_transmit_message->Data[2];
+            CAN1_PELI->DATA3 = peli_transmit_message->Data[3];
+            CAN1_PELI->DATA4 = peli_transmit_message->Data[4];
+            CAN1_PELI->DATA5 = peli_transmit_message->Data[5];
+            CAN1_PELI->DATA6 = peli_transmit_message->Data[6];
+            CAN1_PELI->DATA7 = peli_transmit_message->Data[7];
+        }
+    }
+    else {
+        CAN1_PELI->ID0   = peli_transmit_message->IDHH;
+        CAN1_PELI->ID1   = peli_transmit_message->IDHL;
+        CAN1_PELI->DATA0 = peli_transmit_message->IDLH;
+        CAN1_PELI->DATA1 = peli_transmit_message->IDLL;
+        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+            CAN1_PELI->DATA2 = peli_transmit_message->Data[0];
+            CAN1_PELI->DATA3 = peli_transmit_message->Data[1];
+            CAN1_PELI->DATA4 = peli_transmit_message->Data[2];
+            CAN1_PELI->DATA5 = peli_transmit_message->Data[3];
+            CAN1_PELI->DATA6 = peli_transmit_message->Data[4];
+            CAN1_PELI->DATA7 = peli_transmit_message->Data[5];
+            CAN1_PELI->DATA8 = peli_transmit_message->Data[6];
+            CAN1_PELI->DATA9 = peli_transmit_message->Data[7];
+        }
+    }
+
+    (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR | CAN_CMR_AT);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initiates and transmits a CAN frame message.
+/// @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
+///         CAN data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message)
+{
+    CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC);
+    if (((FunctionalState)peli_transmit_message->FF) != ENABLE) {
+        CAN1_PELI->ID0 = (peli_transmit_message->IDHH);
+
+        CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0);
+        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+            CAN1_PELI->DATA0 = peli_transmit_message->Data[0];
+            CAN1_PELI->DATA1 = peli_transmit_message->Data[1];
+            CAN1_PELI->DATA2 = peli_transmit_message->Data[2];
+            CAN1_PELI->DATA3 = peli_transmit_message->Data[3];
+            CAN1_PELI->DATA4 = peli_transmit_message->Data[4];
+            CAN1_PELI->DATA5 = peli_transmit_message->Data[5];
+            CAN1_PELI->DATA6 = peli_transmit_message->Data[6];
+            CAN1_PELI->DATA7 = peli_transmit_message->Data[7];
+        }
+    }
+    else {
+        CAN1_PELI->ID0   = peli_transmit_message->IDHH;
+        CAN1_PELI->ID1   = peli_transmit_message->IDHL;
+        CAN1_PELI->DATA0 = peli_transmit_message->IDLH;
+        CAN1_PELI->DATA1 = peli_transmit_message->IDLL;
+        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
+            CAN1_PELI->DATA2 = peli_transmit_message->Data[0];
+            CAN1_PELI->DATA3 = peli_transmit_message->Data[1];
+            CAN1_PELI->DATA4 = peli_transmit_message->Data[2];
+            CAN1_PELI->DATA5 = peli_transmit_message->Data[3];
+            CAN1_PELI->DATA6 = peli_transmit_message->Data[4];
+            CAN1_PELI->DATA7 = peli_transmit_message->Data[5];
+            CAN1_PELI->DATA8 = peli_transmit_message->Data[6];
+            CAN1_PELI->DATA9 = peli_transmit_message->Data[7];
+        }
+    }
+
+    (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Receives a correct CAN frame.
+/// @param  RxMessage: pointer to a structure receive frame which contains CAN
+///         Id,CAN DLC, CAN data and FMI number.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message)
+{
+    u32 tempid;
+    peli_receive_message->FF  = (CAN1_PELI->FF) >> 7;
+    peli_receive_message->RTR = ((CAN1_PELI->FF) >> 6) & 0x1;
+    peli_receive_message->DLC = (CAN1_PELI->FF) & 0xf;
+
+    if (((FunctionalState)peli_receive_message->FF) != ENABLE) {
+        tempid = (u32)(CAN1_PELI->ID1 >> 5);
+        tempid |= (u32)(CAN1_PELI->ID0 << 3);
+        peli_receive_message->ID      = tempid;
+        peli_receive_message->Data[0] = CAN1_PELI->DATA0;
+        peli_receive_message->Data[1] = CAN1_PELI->DATA1;
+        peli_receive_message->Data[2] = CAN1_PELI->DATA2;
+        peli_receive_message->Data[3] = CAN1_PELI->DATA3;
+        peli_receive_message->Data[4] = CAN1_PELI->DATA4;
+        peli_receive_message->Data[5] = CAN1_PELI->DATA5;
+        peli_receive_message->Data[6] = CAN1_PELI->DATA6;
+        peli_receive_message->Data[7] = CAN1_PELI->DATA7;
+    }
+    else {
+        tempid = (u32)((CAN1_PELI->DATA1 & 0xf8) >> 3);
+        tempid |= (u32)(CAN1_PELI->DATA0 << 5);
+        tempid |= (u32)(CAN1_PELI->ID1 << 13);
+        tempid |= (u32)(CAN1_PELI->ID0 << 21);
+        peli_receive_message->ID      = tempid;
+        peli_receive_message->Data[0] = CAN1_PELI->DATA2;
+        peli_receive_message->Data[1] = CAN1_PELI->DATA3;
+        peli_receive_message->Data[2] = CAN1_PELI->DATA4;
+        peli_receive_message->Data[3] = CAN1_PELI->DATA5;
+        peli_receive_message->Data[4] = CAN1_PELI->DATA6;
+        peli_receive_message->Data[5] = CAN1_PELI->DATA7;
+        peli_receive_message->Data[6] = CAN1_PELI->DATA8;
+        peli_receive_message->Data[7] = CAN1_PELI->DATA9;
+    }
+    CAN_FIFORelease(CAN1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Get available current informatoin in receive FIFO only in Peli
+///         workmode.
+/// @retval The value in reg RMC
+////////////////////////////////////////////////////////////////////////////////
+u32 CAN_Peli_GetRxFIFOInfo(void)
+{
+    return CAN1_PELI->RMC;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the CAN's last error code (LEC).
+/// @retval Error code:
+///          - CAN_ERRORCODE_NoErr: No Error
+///          - CAN_ERRORCODE_StuffErr: Stuff Error
+///          - CAN_ERRORCODE_FormErr: Form Error
+///          - CAN_ERRORCODE_ACKErr : Acknowledgment Error
+///          - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
+///          - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
+///          - CAN_ERRORCODE_CRCErr: CRC Error
+///          - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Peli_GetLastErrorCode(void)
+{
+    // Return the error code
+    return (u8)CAN1_PELI->ECC;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the CAN Receive Error Counter (REC).
+/// @note   In case of an error during reception, this counter is incremented
+///         by 1 or by 8 depending on the error condition as defined by the CAN
+///         standard. After every successful reception, the counter is
+///         decremented by 1 or reset to 120 if its value was higher than 128.
+///         When the counter value exceeds 127, the CAN controller enters the
+///         error passive state.
+/// @retval CAN Receive Error Counter.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Peli_GetReceiveErrorCounter(void)
+{
+    // Return the Receive Error Counter
+    return (u8)(CAN1_PELI->RXERR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the LSB of the 9-bit can Transmit Error Counter(TEC).
+/// @retval LSB of the 8-bit CAN Transmit Error Counter.
+////////////////////////////////////////////////////////////////////////////////
+u8 CAN_Peli_GetLSBTransmitErrorCounter(void)
+{
+    // Return the LSB of the 8-bit CAN Transmit Error Counter(TEC)
+    return (u8)(CAN1_PELI->TXERR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified CAN interrupts in peli workmode.
+/// @param  it: specifies the CAN interrupt sources to be enabled or
+///         disabled.
+///         This parameter can be:
+/// @arg    CAN_IT_RI: Receive FIFO not empty Interrupt
+/// @arg    CAN_IT_TI: Transmit Interrupt
+/// @arg    CAN_IT_EI: ERROR Interrupt
+/// @arg    CAN_IT_DOI: Data voerflow Interrupt
+/// @arg    CAN_IT_WUI: Wakeup Interrupt
+/// @arg    CAN_IT_EPI(only Peli): passive error Interrupt
+/// @arg    CAN_IT_ALI(only Peli): arbiter lose Interrupt
+/// @arg    CAN_IT_BEI(only Peli): bus error Interrupt
+/// @arg    CAN_IT_ALL: use it can enble all Interrupt
+/// @param  state: new state of the CAN interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CAN_Peli_ITConfig(u32 it, FunctionalState state)
+{
+    (state) ? (CAN1_PELI->IER |= it) : (CAN1_PELI->IER &= ~it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified CAN interrupt has occurred or not.
+/// @param  it: specifies the CAN interrupt source to check.
+///         This parameter can be one of the following values:
+/// @arg    CAN_IT_RI: Receive FIFO not empty Interrupt
+/// @arg    CAN_IT_TI: Transmit Interrupt
+/// @arg    CAN_IT_EI: ERROR Interrupt
+/// @arg    CAN_IT_DOI: Data voerflow Interrupt
+/// @arg    CAN_IT_WUI: Wakeup Interrupt
+/// @arg    CAN_IT_EPI(only Peli): passive error Interrupt
+/// @arg    CAN_IT_ALI(only Peli): arbiter lose Interrupt
+/// @arg    CAN_IT_BEI(only Peli): bus error Interrupt
+/// @arg    CAN_IT_ALL: use it can enble all Interrupt
+/// @retval The current state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus CAN_Peli_GetITStatus(u32 it)
+{
+    return (ITStatus)(((CAN1_PELI->IR & it) != it) ? RESET : SET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Config CAN_Peli_InitTypeDef baud parameter.
+/// @param  CAN_Peli_InitTypeDef: CAN struct.
+/// @param  src_clk: CAN module clock.
+/// @param  baud: specified baud.
+/// @retval The current state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud)
+{
+    u32 i, value = baud, record = 1;
+    u32 remain = 0, sumPrescaler = 0;
+    while ((baud == 0) || (src_clk == 0))
+        ;
+    sumPrescaler = src_clk / baud;
+    sumPrescaler = sumPrescaler / 2;
+    for (i = 25; i > 3; i--) {
+        remain = sumPrescaler - ((sumPrescaler / i) * i);
+        if (remain == 0) {
+            record = i;
+            break;
+        }
+        else {
+            if (remain < value) {
+                value  = remain;
+                record = i;
+            }
+        }
+    }
+    init_struct->SJW   = 0;
+    init_struct->BRP   = (sumPrescaler / record) - 1;
+    init_struct->TESG2 = (record - 3) / 3;
+    init_struct->TESG1 = (record - 3) - init_struct->TESG2;
+}
+
+/// @}
+
+/// @}
+
+/// @}
+
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c
new file mode 100644
index 000000000..b55558263
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c
@@ -0,0 +1,226 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_comp.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE COMP FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_COMP_C_
+
+// Files includes
+#include "hal_comp.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup COMP_HAL
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup COMP_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes COMP peripheral registers to their default reset
+///         values.
+/// @param  selection: the selected comparator.
+///         select the COMP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_DeInit(COMP_Selection_TypeDef selection)
+{
+    *(vu32*)(COMP_BASE + selection) = 0;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the COMP peripheral according to the specified
+/// @param  selection: the selected comparator.
+///         select the COMP peripheral.
+/// @param  init_struct: pointer to an COMP_InitTypeDef structure that
+///         contains the configuration information for the specified COMP
+///         peripheral.
+///         - COMP_InvertingInput specifies the inverting input of COMP
+///         - COMP_NonInvertingInput specifies the non inverting input of COMP
+///         - COMP_Output connect COMP output to selected timer
+///           input (Input capture / Output Compare Reference Clear / Break
+///           Input)
+///         - COMP_BlankingSrce specifies the blanking source of COMP
+///         - COMP_OutputPol select output polarity
+///         - COMP_Hysteresis configures COMP hysteresis value
+///         - COMP_Mode configures COMP power mode
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct)
+{
+    *(vu32*)(COMP_BASE + selection) =    init_struct->Invert     |
+                                         init_struct->NonInvert  |
+                                         init_struct->Output     |
+                                         init_struct->OutputPol  |
+                                         init_struct->BlankingSrce   |
+                                         init_struct->Hysteresis |
+                                         init_struct->Mode       |
+                                         init_struct->OFLT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct: pointer to an COMP_InitTypeDef structure which will
+///         be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_StructInit(COMP_InitTypeDef* init_struct)
+{
+
+    init_struct->Invert         = COMP_InvertingInput_IO1;
+    init_struct->NonInvert      = COMP_NonInvertingInput_IO1;
+    init_struct->Output         = COMP_Output_None;
+    init_struct->BlankingSrce   = COMP_BlankingSrce_None;
+    init_struct->OutputPol      = COMP_NonInverted;
+    init_struct->Hysteresis     = COMP_Hysteresis_No;
+    init_struct->Mode           = COMP_Mode_UltraLowPower;
+    init_struct->OFLT           = COMP_Filter_4_Period;                                                               ///< to adjust the speed/consumption.
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable or disable the COMP peripheral.
+/// @param  selection: the selected comparator.
+///         select the COMP peripheral.
+/// @param  NewState: new state of the COMP peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+///         When enabled, the comparator compares the non inverting input with
+///         the inverting input and the comparison result is available on
+///         comparator output.
+///         When disabled, the comparator doesn't perform comparison and the
+///         output level is low.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state)
+{
+    (state) ? (*(vu32*)(COMP_BASE + selection) |=  COMP_CSR_EN) :
+    (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_EN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select CRV param.
+/// @param  crv_select: Select source for CRV.
+/// @param  crv_level: Set level for CRV.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_SetCrv(u8 crv_select, u8 crv_level)
+{
+    u32 temreg = 0;
+    temreg = COMP->CRV;
+    temreg &= ~COMP_CRV_MASK;
+    // Load config to CRV and enable
+    temreg |= crv_select | crv_level | (1 << 4);
+    COMP->CRV = temreg;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Close or Open the SW1 switch.
+/// @param  selection: the selected comparator.
+///         select the COMP peripheral.
+/// @param  state: new state of the COMP peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+///         When enabled, the comparator compares the non inverting input with
+///         the inverting input and the comparison result is available on
+///         comparator output.
+///         When disabled, the comparator doesn't perform comparison and the
+///         output level is low.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state)
+{
+    (state) ?
+    (*(vu32*)(COMP_BASE + selection) |=  COMP_CSR_COMPSW1) :
+    (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_COMPSW1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Return the output level (high or low) of the selected comparator.
+///         The output level depends on the selected polarity.
+///         If the polarity is not inverted:
+///           - Comparator output is low when the non-inverting input is at a
+///           lower voltage than the inverting input
+///           - Comparator output is high when the non-inverting input is at a
+///           higher voltage than the inverting input
+///         If the polarity is inverted:
+///           - Comparator output is high when the non-inverting input is at a
+///           lower voltage than the inverting input
+///           - Comparator output is low when the non-inverting input is at a
+///           higher voltage than the inverting input
+/// @param  comp: the selected comparator.
+///         select the COMP peripheral.
+/// @retval  The selected comparator output level: low or high.
+////////////////////////////////////////////////////////////////////////////////
+u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection)
+{
+    return (((*(vu32*)(COMP_BASE + selection) & COMP_CSR_STA) != 0) ?
+            COMP_OutputLevel_High :
+            COMP_OutputLevel_Low );
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Lock the selected comparator (COMP1/COMP2) configuration.
+/// @param  selection: the selected comparator.
+///         select the COMP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void COMP_LockConfig(COMP_Selection_TypeDef selection)
+{
+    *(vu32*)(COMP_BASE + selection) |= COMP_CSR_LOCK;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable or disable the COMP register.
+/// @param  state: new state of the COMP peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exCOMP_CrvCmd(FunctionalState state)
+{
+    (state) ? (COMP->CRV |= COMP_CRV_EN_ENABLE) : (COMP->CRV &= ~COMP_CRV_EN_ENABLE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select comparator external reference voltage.
+/// @param  selection: the selected external reference voltage.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exCOMP_SwitchCrv(u32 crv)
+{
+    COMP->CRV |= crv;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Select comparator external reference voltage source.
+/// @param  selection: the selected external reference voltage source.
+///         This parameter can be: COMP_CRV_SRC_AVDD or COMP_CRV_SRC_VREF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exCOMP_CrvSrc(u32 src)
+{
+    COMP->CRV |= src;
+}
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c
new file mode 100644
index 000000000..817698bf5
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c
@@ -0,0 +1,108 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_crc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE CRC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_CRC_C_
+
+// Files includes
+#include "hal_crc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Resets the CRC Data register (DR).
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CRC_ResetDR()
+{
+    CRC->CR = CRC_CR_RESET;
+}
+//#pragma optimize(0)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Computes the 32-bit CRC of a given data word(32-bit).
+/// @param  Data: data word(32-bit) to compute its CRC
+/// @retval 32-bit CRC
+////////////////////////////////////////////////////////////////////////////////
+u32 CRC_CalcCRC(u32 data)
+{
+    CRC->DR = data;
+    return (CRC->DR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+/// @param  buffer: pointer to the buffer containing the data to be computed
+/// @param  length: length of the buffer to be computed
+/// @retval 32-bit CRC
+////////////////////////////////////////////////////////////////////////////////
+u32 CRC_CalcBlockCRC(u32* buffer, u32 length)
+{
+    u32 i;
+    for (i = 0; i < length; i++) {
+        CRC->DR = buffer[i];
+    }
+    return (CRC->DR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the current CRC value.
+/// @param  None.
+/// @retval 32-bit CRC
+////////////////////////////////////////////////////////////////////////////////
+u32 CRC_GetCRC(void)
+{
+    return (CRC->DR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Stores a 8-bit data in the Independent Data(ID) register.
+/// @param  id_value: 8-bit value to be stored in the ID register
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void CRC_SetIDRegister(u8 id_value)
+{
+    CRC->IDR = id_value;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+/// @param  None.
+/// @retval 8-bit value of the ID register
+////////////////////////////////////////////////////////////////////////////////
+u8 CRC_GetIDRegister()
+{
+    return (CRC->IDR);
+}
+
+/// @}
+
+/// @}
+
+/// @}
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c
new file mode 100644
index 000000000..10b26d353
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c
@@ -0,0 +1,43 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_crs.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE CRS FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_CRS_C_
+
+// Files includes
+#include "hal_rcc.h"
+#include "hal_crs.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRS_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup CRS_Exported_Functions
+/// @{
+
+/// @}
+
+/// @}
+
+/// @}
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c
new file mode 100644
index 000000000..b3583f155
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c
@@ -0,0 +1,184 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_dac.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE DAC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_DAC_C_
+
+// Files includes
+#include "hal_dac.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DAC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DAC_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the DAC peripheral registers to their default reset values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_DeInit(void)
+{
+    exRCC_APB1PeriphReset(RCC_APB1ENR_DAC);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
+/// @param channel: the selected DAC channel.
+/// @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified
+/// DAC channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct)
+{
+    DAC->CR &= ~((DAC_CR_BOFF1 | DAC_CR_TEN1 | DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_MAMP1) << channel);
+    DAC->CR |= (((u32)(init_struct->DAC_Trigger) | (u32)(init_struct->DAC_WaveGeneration) |
+                 (u32)(init_struct->DAC_LFSRUnmask_TriangleAmplitude) | (u32)(init_struct->DAC_OutputBuffer))
+                << channel);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each DAC_InitStruct member with its default value.
+/// @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_StructInit(DAC_InitTypeDef* init_struct)
+{
+    init_struct->DAC_Trigger                      = DAC_Trigger_None;
+    init_struct->DAC_WaveGeneration               = DAC_WaveGeneration_None;
+    init_struct->DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1;
+    init_struct->DAC_OutputBuffer                 = DAC_OutputBuffer_Enable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DAC channel.
+/// @param channel: the selected DAC channel.
+/// @param state: new state of the DAC channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state)
+{
+    (state) ? (DAC->CR |= DAC_CR_EN1 << channel) : (DAC->CR &= ~(DAC_CR_EN1 << channel));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DAC channel DMA request.
+/// @param channel: the selected DAC channel.
+/// @param state: new state of the selected DAC channel DMA request.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state)
+{
+    (state) ? (DAC->CR |= DAC_CR_DMAEN1 << channel) : (DAC->CR &= ~(DAC_CR_DMAEN1 << channel));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected DAC channel software trigger.
+/// @param channel: the selected DAC channel.
+/// @param state: new state of the selected DAC channel software trigger.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state)
+{
+    (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 << (channel >> 4)))
+    : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 << (channel >> 4)));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables simultaneously the two DAC channels software triggers.
+/// @param state: new state of the DAC channels software triggers.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_DualSoftwareTriggerCmd(FunctionalState state)
+{
+    (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2))
+    : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the selected DAC channel wave generation.
+/// @param channel: the selected DAC channel.
+/// @param wave: Specifies the wave type to enable or disable.
+/// @param state: new state of the selected DAC channel wave generation.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state)
+{
+    (state) ? (DAC->CR |= wave << channel) : (DAC->CR &= ~(wave << channel));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the specified data holding register value for DAC channel1.
+/// @param alignement: Specifies the data alignement for DAC channel1.
+/// @param data : data to be loaded in the selected data holding register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data)
+{
+    *((u32*)(DAC_BASE + DHR12R1_Offset + alignement)) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the specified data holding register value for DAC channel2.
+/// @param alignement: Specifies the data alignement for DAC channel2.
+/// @param data : data to be loaded in the selected data holding
+///   register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data)
+{
+    *((u32*)(DAC_BASE + DHR12R2_Offset + alignement)) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the specified data holding register value for dual channel DAC.
+/// @param alignement: Specifies the data alignement for dual channel DAC.
+/// @param data2: data for DAC Channel2 to be loaded in the selected data holding register.
+/// @param data1: data for DAC Channel1 to be loaded in the selected data holding register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1)
+{
+    u32 data = ((alignement == DAC_Align_8b_R) ? ((data2 << 8) | data1) : ((data2 << 16) | data1));
+    *((u32*)(DAC_BASE + DHR12RD_Offset + alignement)) = data;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the last data output value of the selected DAC cahnnel.
+/// @param channel: the selected DAC channel.
+/// @retval  The selected DAC channel data output value.
+////////////////////////////////////////////////////////////////////////////////
+u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel)
+{
+    return (*(vu32*)(DAC_BASE + DOR_Offset + (channel >> 2)));
+}
+/// @}
+
+/// @}
+
+/// @}
+
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c
new file mode 100644
index 000000000..b51d13214
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c
@@ -0,0 +1,53 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_dbg.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE DBG FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_DBG_C
+
+// Files includes
+#include "types.h"
+#include "hal_dbg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DBG_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DBG_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DBG peripheral.
+/// @param  periph: DBG peripheral.
+/// @param  state: new state of the specified DBG peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DBGMCU_Configure(u32 periph, FunctionalState state)
+{
+    (state) ? (DBGMCU->CR |= periph) : (DBGMCU->CR &= ~periph);
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c
new file mode 100644
index 000000000..5ec0dc95a
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c
@@ -0,0 +1,319 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_dma.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE DMA FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+
+
+// Define to prevent recursive inclusion
+#define _HAL_DMA_C_
+
+// Files includes
+#include "types.h"
+#include "hal_dma.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DMA_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup DMA_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the DMA Channeln registers to their default reset
+///         values.
+/// @param   select the DMA Channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_DeInit(DMA_Channel_TypeDef* channel)
+{
+    channel->CCR &= ~DMA_CCR_EN;
+    channel->CCR   = 0;
+    channel->CNDTR = 0;
+    channel->CPAR  = 0;
+    channel->CMAR  = 0;
+    if((*(vu32*)&channel) >= (*(vu32*)DMA2_Channel1_BASE)) {
+        DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+    }
+    else {
+        DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the DMA Channeln according to the specified
+///         parameters in the init_struct.
+/// @param  select the DMA Channel.
+/// @param  init_struct: pointer to a DMA_InitTypeDef structure that
+///         contains the configuration information for the specified DMA
+///         Channel.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct)
+{
+    MODIFY_REG(
+        channel->CCR,
+        (DMA_CCR_DIR | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL | DMA_CCR_M2M),
+        ((u32)init_struct->DMA_DIR | (u32)init_struct->DMA_Mode | (u32)init_struct->DMA_PeripheralInc |
+         (u32)init_struct->DMA_MemoryInc | (u32)init_struct->DMA_PeripheralDataSize | (u32)init_struct->DMA_MemoryDataSize |
+         (u32)init_struct->DMA_Priority | (u32)init_struct->DMA_M2M));
+
+    MODIFY_REG(channel->CCR, DMA_CCR_ARE, init_struct->DMA_Auto_reload);
+    channel->CNDTR = init_struct->DMA_BufferSize;
+    channel->CPAR  = init_struct->DMA_PeripheralBaseAddr;
+    channel->CMAR  = init_struct->DMA_MemoryBaseAddr;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct : pointer to a DMA_InitTypeDef structure which will
+///         be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_StructInit(DMA_InitTypeDef* init_struct)
+{
+    init_struct->DMA_PeripheralBaseAddr = 0;
+    init_struct->DMA_MemoryBaseAddr     = 0;
+    init_struct->DMA_DIR                = DMA_DIR_PeripheralSRC;
+    init_struct->DMA_BufferSize         = 0;
+    init_struct->DMA_PeripheralInc      = DMA_PeripheralInc_Disable;
+    init_struct->DMA_MemoryInc          = DMA_MemoryInc_Disable;
+    init_struct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    init_struct->DMA_MemoryDataSize     = DMA_MemoryDataSize_Byte;
+    init_struct->DMA_Mode               = DMA_Mode_Normal;
+    init_struct->DMA_Priority           = DMA_Priority_Low;
+    init_struct->DMA_M2M                = DMA_M2M_Disable;
+
+    init_struct->DMA_Auto_reload         = DMA_Auto_Reload_Disable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DMA Channeln.
+/// @param  channel: select the DMA Channel.
+/// @param  state: new state of the DMA Channeln.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state)
+{
+    MODIFY_REG(channel->CCR, DMA_CCR_EN, state << DMA_CCR_EN_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DMA Channeln interrupts.
+/// @param  channel: select the DMA Channel.
+/// @param  it: specifies the DMA interrupts sources to be enabled
+///         or disabled.
+///         This parameter can be any combination of the following values:
+///    @arg DMA_IT_TC:  Transfer complete interrupt mask
+///    @arg DMA_IT_HT:  Half transfer interrupt mask
+///    @arg DMA_IT_TE:  Transfer error interrupt mask
+/// @param  state: new state of the specified DMA interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state)
+{
+    (state) ? (channel->CCR |= it) : (channel->CCR &= ~it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the number of data units in the select the DMA Channel .
+/// @param  channel: select the DMA Channel
+/// @param  DataNumber: The number of data units in the current DMAy Channelx
+///         transfer.
+/// @note   This function can only be used when the DMAy_Channelx is disabled.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length)
+{
+    channel->CNDTR = length;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the number of remaining data units in the current
+///         DMA Channeln transfer.
+/// @param  channel: select the DMA Channel.
+/// @retval The number of remaining data units in the current DMA Channeln
+///         transfer.
+////////////////////////////////////////////////////////////////////////////////
+u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel)
+{
+    return channel->CNDTR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified DMA Channeln flag is set or not.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+///    @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
+///    @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
+///    @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
+///    @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
+///    @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
+///    @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+///    @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+///    @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval The new state of DMAy_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag)
+{
+    if(flag >= DMA2_FLAG_GL1 ) {
+        return (DMA2->ISR & flag) ? SET : RESET;
+    }
+    return (DMA1->ISR & flag) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the DMA Channeln's pending flags.
+/// @param  flag: specifies the flag to clear.
+///         This parameter can be any combination (for the same DMA) of the
+///         following values:
+///    @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
+///    @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
+///    @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
+///    @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
+///    @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
+///    @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+///    @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+///    @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_ClearFlag(DMA_Flags_TypeDef flag)
+{
+    if(flag >= DMA2_FLAG_GL1 ) {
+        DMA2->IFCR = flag;
+        return ;
+    }
+    DMA1->IFCR = flag;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified DMA Channeln interrupt has occurred or
+/// not.
+/// @param  it: specifies the DMA interrupt source to check.
+///         This parameter can be one of the following values:
+///    @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
+///    @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
+///    @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
+///    @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
+///    @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
+///    @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+///    @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+///    @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval  The new state of DMAy_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it)
+{
+    if(it >= DMA2_IT_GL1 ) {
+        return (DMA2->ISR & it) ? SET : RESET;
+    }
+    return (DMA1->ISR & it) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the DMA Channeln's interrupt pending bits.
+/// @param  it: specifies the DMA interrupt pending bit to clear.
+///         This parameter can be any combination (for the same DMA) of the
+///         following values:
+///    @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
+///    @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
+///    @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
+///    @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
+///    @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
+///    @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+///    @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+///    @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it)
+{
+    if(it >= DMA2_IT_GL1 ) {
+        DMA2->IFCR = it;
+        return ;
+    }
+    DMA1->IFCR = it;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the DMA Channeln's Peripheral address.
+/// @param  channel : where n can be 1 to 7 for DMA1 to select the DMA Channel.
+/// @param  address : DMA Peripheral address.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 address)
+{
+    channel->CPAR = address;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the DMA Channeln's Peripheral address.
+/// @param  channel : select the DMA Channel.
+/// @param  length : Transmit lengths.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 length)
+{
+    channel->CNDTR = length;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the DMA Channeln's Peripheral address.
+/// @param  channel :select the DMA Channel.
+/// @param  address : DMA memery address.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 address)
+{
+    channel->CMAR = address;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the DMA Channeln's interrupt pending bits.
+/// @param  it: specifies the DMA interrupt pending bit to clear.
+///         This parameter can be any combination (for the same DMA) of the
+///         following values:
+///    @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
+///    @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
+///    @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
+///    @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
+///    @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
+///    @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
+///    @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
+///    @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exDMA_ClearITPendingBit(DMA_Channel_TypeDef* channel, u32 it)
+{
+    if(it >= DMA2_IT_GL1 ) {
+        DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+        DMA2->IFCR = it;
+        return ;
+    }
+    DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
+    DMA1->IFCR = it;
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c
new file mode 100644
index 000000000..ca662e978
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c
@@ -0,0 +1,836 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_eth.c
+/// @author   AE TEM
+/// @brief    THIS FILE PROVIDES ALL THE HAL_eth.c EXAMPLE.
+/// ////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT  MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+#define _HAL_ETH_C_
+#include "hal_rcc.h"
+#include "hal_eth.h"
+#include "reg_eth.h"
+
+
+void ETH_DeInit(void)
+{
+    RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, DISABLE);
+}
+
+void ETH_StructInit(ETH_InitTypeDef* ptr)
+{
+    ptr->ETH_AutoNegotiation         = ETH_AutoNegotiation_Enable;              ///< PHY Auto-negotiation enabled
+    ptr->ETH_Watchdog                = ETH_Watchdog_Enable;                     ///< MAC watchdog enabled: cuts off long frame
+    ptr->ETH_Jabber                  = ETH_Jabber_Enable;                       ///< MAC Jabber enabled in Half-duplex mode
+    ptr->ETH_InterFrameGap           = ETH_InterFrameGap_96Bit;                 ///< Ethernet interframe gap set to 96 bits
+    ptr->ETH_CarrierSense            = ETH_CarrierSense_Enable;                 ///< Carrier Sense Enabled in Half-Duplex mode
+    ptr->ETH_Speed                   = ETH_Speed_100M;                          ///< PHY speed configured to 100Mbit/s
+    ptr->ETH_ReceiveOwn              = ETH_ReceiveOwn_Enable;                   ///< Receive own Frames in Half-Duplex mode enabled
+    ptr->ETH_LoopbackMode            = ETH_LoopbackMode_Disable;                ///< MAC MII loopback disabled
+    ptr->ETH_Mode                    = ETH_Mode_FullDuplex;                     ///< Full-Duplex mode selected
+    ptr->ETH_ChecksumOffload         = ETH_ChecksumOffload_Disable;             ///< IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled
+    ptr->ETH_RetryTransmission       = ETH_RetryTransmission_Enable;            ///< Retry Transmission enabled for half-duplex mode
+    ptr->ETH_AutomaticPadCRCStrip    = ETH_AutomaticPadCRCStrip_Disable;        ///< Automatic PAD/CRC strip disable
+    ptr->ETH_BackOffLimit            = ETH_BackOffLimit_10;                     ///< half-duplex mode retransmission Backoff time_limit = 10 slot time
+    ptr->ETH_DeferralCheck           = ETH_DeferralCheck_Disable;               ///< half-duplex mode Deferral check disabled
+    ptr->ETH_ReceiveAll              = ETH_ReceiveAll_Disable;                  ///< Receive all frames disabled
+    ptr->ETH_SourceAddrFilter        = ETH_SourceAddrFilter_Disable;            ///< Source address filtering (on the optional MAC addresses) disabled
+    ptr->ETH_PassControlFrames       = ETH_PassControlFrames_BlockAll;          ///< Do not forward control frames that do not pass the address filtering
+    ptr->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;   ///< Disable reception of Broadcast frames
+    ptr->ETH_DestinationAddrFilter   = ETH_DestinationAddrFilter_Normal;        ///< Normal Destination address filtering (not reverse addressing)
+    ptr->ETH_PromiscuousMode         = ETH_PromiscuousMode_Disable;             ///< Promiscuous address filtering mode disabled
+    ptr->ETH_MulticastFramesFilter   = ETH_MulticastFramesFilter_Perfect;       ///< Perfect address filtering for multicast addresses
+    ptr->ETH_UnicastFramesFilter     = ETH_UnicastFramesFilter_Perfect;         ///< Perfect address filtering for unicast addresses
+    ptr->ETH_HashTableHigh           = 0x0;                                     ///< Initialize hash table high and low regs
+    ptr->ETH_HashTableLow            = 0x0;
+    ptr->ETH_PauseTime               = 0x0;                                     ///< Flow control config (flow control disabled)
+    ptr->ETH_ZeroQuantaPause         = ETH_ZeroQuantaPause_Enable;
+    ptr->ETH_PauseLowThreshold       = ETH_PauseLowThreshold_Minus4;
+    ptr->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
+    ptr->ETH_ReceiveFlowControl      = ETH_ReceiveFlowControl_Disable;
+    ptr->ETH_TransmitFlowControl     = ETH_TransmitFlowControl_Disable;
+    ptr->ETH_VLANTagComparison       = ETH_VLANTagComparison_16Bit;             ///< VLANtag config (VLAN field not checked)
+    ptr->ETH_VLANTagIdentifier       = 0x0;
+
+    ptr->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; ///< Drops frames with with TCP/IP checksum errors
+    ptr->ETH_ReceiveStoreForward     = ETH_ReceiveStoreForward_Enable;          ///< Store and forward mode enabled for receive
+    ptr->ETH_FlushReceivedFrame      = ETH_FlushReceivedFrame_Enable;           ///< Flush received frame that created FIFO overflow
+    ptr->ETH_TransmitStoreForward    = ETH_TransmitStoreForward_Enable;         ///< Store and forward mode enabled for transmit
+    ptr->ETH_TransmitThresholdControl = ETH_ReceiveThresholdControl_64Bytes;    ///< Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled)
+    ptr->ETH_ForwardErrorFrames      = ETH_ForwardErrorFrames_Disable;          ///< Disable forwarding frames with errors (short frames, CRC,...)
+    ptr->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; ///< Disable undersized good frames
+    ptr->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;     ///< Threshold RXFIFO level set to 64 bytes (used when Cut through mode is enabled)
+    ptr->ETH_SecondFrameOperate      = ETH_SecondFrameOperate_Disable;          ///< Disable Operate on second frame (transmit a second frame to FIFO without waiting status of previous frame
+    ptr->ETH_AddressAlignedBeats     = ETH_AddressAlignedBeats_Enable;          ///< DMA works on 32-bit aligned start source and destinations addresses
+    ptr->ETH_FixedBurst              = ETH_FixedBurst_Enable;                   ///< Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions
+    ptr->ETH_RxDMABurstLength        = ETH_RxDMABurstLength_32Beat;             ///< DMA transfer max burst length = 32 beats = 32 x 32bits
+    ptr->ETH_TxDMABurstLength        = ETH_TxDMABurstLength_32Beat;
+    ptr->ETH_DescriptorSkipLength    = 0x0;                                     ///< DMA Ring mode skip length = 0
+    ptr->ETH_DMAArbitration          = ETH_DMAArbitration_RoundRobin_RxTx_1_1;  ///< Equal priority (round-robin) between transmit and receive DMA engines
+}
+
+u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr)
+{
+    u32 hclk = RCC_GetHCLKFreq();
+    u32 reg = ETH->MACMIIAR & MACMIIAR_CR_MASK;
+    u32 temp_val = 0;
+    hclk = 100000000;
+    ////////////////////////////////////////////////////////////////////////////
+    if (hclk >= 20000000 && hclk < 35000000) {
+        reg |= ETH_MACMIIAR_CR_Div16;                                           ///< HCLK 20 ~ 35 MHz, /16
+    }
+    else if (hclk >= 35000000 && hclk < 60000000) {
+        reg |= ETH_MACMIIAR_CR_Div26;                                           ///< HCLK 35 ~ 60 MHz, /26
+    }
+    else if (hclk >= 60000000 && hclk < 100000000) {
+        reg |= ETH_MACMIIAR_CR_Div42;                                           ///< HCLK 60 ~ 100 MHz, /42
+    }
+    else if (hclk >= 100000000 && hclk < 150000000) {
+        reg |= ETH_MACMIIAR_CR_Div62;                                           ///< HCLK 100 ~ 150 MHz, /62
+    }
+    else {
+        reg |= ETH_MACMIIAR_CR_Div102;                                          ///< HCLK 150 ~ 168 MHz, /102
+    }
+
+    ETH->MACMIIAR = reg;
+
+    ////////////////////////////////////////////////////////////////////////////
+    ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_Reset);
+    if (ptr->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) {
+        // Wait for linked status
+        while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_Linked_Status));
+        ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AutoNegotiation);
+        // Enable Auto-Negitation
+        while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_AutoNego_Complete)) {
+
+        }
+        // Read the result of the Auto-Negitation
+        temp_val = ETH_ReadPHYRegister(phy_addr, 31);
+
+        if ((temp_val & 0x1C) == 0x4) {
+            ptr->ETH_Speed = ETH_Speed_10M;
+            ptr->ETH_Mode = ETH_Mode_HalfDuplex;
+            SYSCFG->CFGR2 &= ~(1 << 21);
+        }
+        else if((temp_val & 0x1C) == 0x14) {
+            ptr->ETH_Speed = ETH_Speed_10M;
+            ptr->ETH_Mode = ETH_Mode_FullDuplex;
+            SYSCFG->CFGR2 |= 1 << 21;
+        }
+        else if((temp_val & 0x1C) == 0x8) {
+            ptr->ETH_Speed = ETH_Speed_100M;
+            ptr->ETH_Mode = ETH_Mode_HalfDuplex;
+            SYSCFG->CFGR2 &= ~(1 << 21);
+        }
+        else if((temp_val & 0x1C) == 0x18) {
+            ptr->ETH_Speed = ETH_Speed_100M;
+            ptr->ETH_Mode = ETH_Mode_FullDuplex;
+            SYSCFG->CFGR2 |= 1 << 21;
+        }
+    }
+    else {
+        ETH_WritePHYRegister(phy_addr, PHY_BCR, ((u16)(ptr->ETH_Mode >> 3) |
+                             (u16)(ptr->ETH_Speed >> 1)));
+        if(ptr->ETH_Speed == ETH_Speed_10M) {
+            SYSCFG->CFGR2 &= ~(1 << 21);
+        }
+        else {
+            SYSCFG->CFGR2 |= 1 << 21;
+        }
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    ETH->MACCR = ETH->MACCR & MACCR_CLEAR_MASK |   (ptr->ETH_Watchdog |
+                 ptr->ETH_Jabber |
+                 ptr->ETH_InterFrameGap |
+                 ptr->ETH_CarrierSense |
+                 ptr->ETH_Speed |
+                 ptr->ETH_ReceiveOwn |
+                 ptr->ETH_LoopbackMode |
+                 ptr->ETH_Mode |
+                 ptr->ETH_ChecksumOffload |
+                 ptr->ETH_RetryTransmission |
+                 ptr->ETH_AutomaticPadCRCStrip |
+                 ptr->ETH_DeferralCheck);
+
+    ETH->MACFFR =   ptr->ETH_ReceiveAll |
+                    ptr->ETH_SourceAddrFilter |
+                    ptr->ETH_PassControlFrames |
+                    ptr->ETH_BroadcastFramesReception |
+                    ptr->ETH_DestinationAddrFilter |
+                    ptr->ETH_PromiscuousMode |
+                    ptr->ETH_MulticastFramesFilter |
+                    ptr->ETH_UnicastFramesFilter;
+
+    ETH->MACHTHR = ptr->ETH_HashTableHigh;
+    ETH->MACHTLR = ptr->ETH_HashTableLow;
+
+    ETH->MACFCR = ETH->MACFCR & MACFCR_CLEAR_MASK | ((ptr->ETH_PauseTime << ETH_MACFCR_PT_Pos) |
+                  ptr->ETH_ZeroQuantaPause |
+                  ptr->ETH_PauseLowThreshold |
+                  ptr->ETH_UnicastPauseFrameDetect |
+                  ptr->ETH_ReceiveFlowControl |
+                  ptr->ETH_TransmitFlowControl);
+
+    ETH->MACVLANTR = ptr->ETH_VLANTagComparison | ptr->ETH_VLANTagIdentifier;
+
+    ETH->DMAOMR = 0x00200004;
+    ETH->DMAIER = 0x0001A040;
+    ETH->DMABMR = ( ptr->ETH_AddressAlignedBeats |
+                    ptr->ETH_FixedBurst |
+                    ptr->ETH_RxDMABurstLength |                                 // !! if 4xPBL is selected for Tx or Rx it is applied for the other
+                    ptr->ETH_TxDMABurstLength |
+                    ptr->ETH_DescriptorSkipLength << 2 |
+                    ptr->ETH_DMAArbitration);// |
+//                    ETH_DMABMR_USP);                                            // Enable use of separate PBL for Rx and Tx
+
+    return ETH_SUCCESS;
+}
+
+void ETH_Start(void)
+{
+    ETH_MACTransmissionCmd(ENABLE);
+    ETH_MACReceptionCmd(ENABLE);
+    ETH_FlushTransmitFIFO();
+    ETH_DMATransmissionCmd(ENABLE);
+    ETH_DMAReceptionCmd(ENABLE);
+}
+
+void ETH_Stop(void)
+{
+    ETH_DMATransmissionCmd(DISABLE);
+    ETH_DMAReceptionCmd(DISABLE);
+    ETH_MACReceptionCmd(DISABLE);
+    ETH_FlushTransmitFIFO();
+    ETH_MACTransmissionCmd(DISABLE);
+}
+
+void ETH_MACTransmissionCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACCR |= ETH_MACCR_TE) : (ETH->MACCR &= ~ETH_MACCR_TE);
+}
+
+void ETH_MACReceptionCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACCR |= ETH_MACCR_RE) : (ETH->MACCR &= ~ETH_MACCR_RE);
+}
+
+FlagStatus ETH_GetFlowControlBusyStatus(void)
+{
+    return (FlagStatus)(ETH->MACFCR & ETH_MACFCR_FCBBPA);
+}
+
+void ETH_InitiatePauseControlFrame(void)
+{
+    ETH->MACFCR |= ETH_MACFCR_FCBBPA;
+}
+
+void ETH_BackPressureActivationCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACFCR |= ETH_MACFCR_FCBBPA) : (ETH->MACFCR &= ~ETH_MACFCR_FCBBPA);
+}
+
+void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr)
+{
+    *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) =
+        (u32)mac_addr[5] << 8 |
+        (u32)mac_addr[4];
+
+    *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) =
+        (u32)mac_addr[3] << 24 |
+        (u32)mac_addr[2] << 16 |
+        (u32)mac_addr[1] << 8 |
+        (u32)mac_addr[0];
+}
+
+void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr)
+{
+    mac_addr[5] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) >> 8 & 0xFF;
+    mac_addr[4] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) & 0xFF;
+    mac_addr[3] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 24 & 0xFF;
+    mac_addr[2] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 16 & 0xFF;
+    mac_addr[1] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 8 & 0xFF;
+    mac_addr[0] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) & 0xFF;
+}
+
+void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta)
+{
+    sta ?   ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_AE) :
+    ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_AE);
+}
+
+void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta)
+{
+    sta ?   ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA) :
+    ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA);
+}
+
+void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte)
+{
+    (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_MBC;
+
+    (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= mask_byte;
+}
+
+FrameTypeDef ETH_Get_Received_Frame(void)
+{
+    FrameTypeDef frame;
+
+    frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4;
+    frame.buf = (DMA_RX_FRAME_infos->ptrFS_Rx_Desc)->BUF1ADDR;
+    frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc;
+
+
+    DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+
+    return frame;
+}
+
+FrameTypeDef ETH_Get_Received_Frame_interrupt(void)
+{
+    FrameTypeDef frame = {0};
+    __IO u32 desc_cnt = 0;
+
+    while(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && desc_cnt < ETH_RX_BUF_NUM) {
+        desc_cnt++;
+
+        if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) &&
+                !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
+            DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+            DMA_RX_FRAME_infos->cnt = 1;
+            DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+
+        }
+        else if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) &&
+                  (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
+            DMA_RX_FRAME_infos->cnt++;
+            DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+        }
+        else {
+            DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet;
+            DMA_RX_FRAME_infos->cnt++;
+
+            if (DMA_RX_FRAME_infos->cnt == 1)
+                DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+
+            frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4;
+
+            frame.buf = (DMA_RX_FRAME_infos->cnt > 1) ?
+                        (DMA_RX_FRAME_infos->ptrFS_Rx_Desc->BUF1ADDR) :
+                        (DMARxDescToGet->BUF1ADDR);
+
+            frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc;
+
+            DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+
+            return frame;
+        }
+    }
+
+    return frame;
+}
+
+u32 ETH_Prepare_Transmit_Descriptors(u16 len)
+{
+    u32 cnt = 0, i = 0;
+    __IO ETH_DMADESCTypeDef* temp_desc = DMATxDescToSet;
+
+    if (DMATxDescToSet->CS & ETH_DMA_TDES_OWN)
+        return ETH_ERROR;
+
+    if(len > ETH_TX_BUF_SIZE) {
+        cnt = len / ETH_TX_BUF_SIZE;
+
+        if (len % ETH_TX_BUF_SIZE)
+            cnt++;
+    }
+    else {
+        cnt = 1;
+    }
+
+    if (cnt == 1) {
+        temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS | ETH_DMA_TDES_TBS1);
+
+        temp_desc->BL |=    ETH_DMA_TDES_FS |
+                            ETH_DMA_TDES_LS |
+                            (len & ETH_DMA_TDES_TBS1);
+
+        temp_desc->CS |= ETH_DMA_TDES_OWN;
+        temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR);
+    }
+    else {
+        for (i = 0; i < cnt; i++) {
+            temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS);
+
+            if (i == 0)
+                temp_desc->BL |= ETH_DMA_TDES_FS;
+
+            temp_desc->BL = ETH_TX_BUF_SIZE & ETH_DMA_TDES_TBS1;
+
+            if (i == (cnt - 1)) {
+                temp_desc->BL &= ~ETH_DMA_TDES_TBS1;
+                temp_desc->BL |=    ETH_DMA_TDES_LS |
+                                    ((len - (cnt - 1) * ETH_TX_BUF_SIZE) & ETH_DMA_TDES_TBS1);
+            }
+
+            temp_desc->CS |= ETH_DMA_TDES_OWN;
+            temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR);
+        }
+    }
+
+    DMATxDescToSet = temp_desc;
+
+    if (ETH->DMASR & ETH_DMASR_TBUS) {
+        ETH->DMASR = ETH_DMASR_TBUS;
+        ETH->DMATPDR = 0;
+    }
+
+    return ETH_SUCCESS;
+}
+
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt)
+{
+    u32 i = 0;
+    ETH_DMADESCTypeDef* temp_desc;
+
+    DMARxDescToGet = ptr_desc;
+
+    for (i = 0; i < cnt; i++) {
+        temp_desc = ptr_desc + i;
+        temp_desc->CS = ETH_DMA_RDES_OWN;
+        temp_desc->BL = ETH_DMA_RDES_RCH | ETH_RX_BUF_SIZE;
+        temp_desc->BUF1ADDR = (u32)&buf[i * ETH_RX_BUF_SIZE];
+
+        if (i < cnt - 1) {
+            temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1);
+        }
+        else {
+            temp_desc->BUF2NDADDR = (u32)(ptr_desc);
+        }
+    }
+
+    ETH->DMARDLAR = (u32)ptr_desc;
+
+    DMA_RX_FRAME_infos = &RX_Frame_Descriptor;
+}
+
+u32 ETH_CheckFrameReceived(void)
+{
+    if(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
+            (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
+
+        DMA_RX_FRAME_infos->cnt++;
+
+        if (DMA_RX_FRAME_infos->cnt == 1) {
+            DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+        }
+        DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet;
+        return 1;
+    }
+    else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
+              !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)  &&
+              (DMARxDescToGet->CS & ETH_DMA_RDES_FS)) {
+        DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
+        DMA_RX_FRAME_infos->ptrLS_Rx_Desc = (void*)0;
+        DMA_RX_FRAME_infos->cnt = 1;
+    }
+    else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
+              !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)  &&
+              !(DMARxDescToGet->CS & ETH_DMA_RDES_FS)) {
+        DMA_RX_FRAME_infos->cnt++;
+        DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
+    }
+
+    return 0;
+}
+
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt)
+{
+    u32 i = 0;
+    ETH_DMADESCTypeDef* temp_desc;
+
+    DMATxDescToSet = ptr_desc;
+
+    for (i = 0; i < cnt; i++) {
+        temp_desc = ptr_desc + i;
+        temp_desc->BL = ETH_DMA_TDES_TCH;
+        temp_desc->BUF1ADDR = (u32)(&buf[i * ETH_TX_BUF_SIZE]);
+
+        if (i < cnt - 1) {
+            temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1);
+        }
+        else {
+            temp_desc->BUF2NDADDR = (u32)(ptr_desc);
+        }
+    }
+
+    ETH->DMATDLAR = (u32)ptr_desc;
+}
+
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag)
+{
+    return (FlagStatus)(ptr_desc->CS & flag);
+}
+
+u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc)
+{
+    return (ptr_desc->CS & ETH_DMA_TDES_CC) >> ETH_DMA_TDES_COLLISION_COUNTSHIFT;
+}
+
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc)
+{
+    ptr_desc->CS |= ETH_DMA_TDES_OWN;
+}
+
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+    sta ? (ptr_desc->BL |= ETH_DMA_TDES_IC) : (ptr_desc->BL &= ~ETH_DMA_TDES_IC);
+}
+
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val)
+{
+    ptr_desc->CS |= val;
+}
+
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val)
+{
+    ptr_desc->CS |= val;
+}
+
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+    sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DC) : (ptr_desc->BL |= ETH_DMA_TDES_DC);
+}
+
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+    sta ? (ptr_desc->BL |= ETH_DMA_TDES_TCH) : (ptr_desc->BL &= ~ETH_DMA_TDES_TCH);
+}
+
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+    sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DP) : (ptr_desc->BL |= ETH_DMA_TDES_DP);
+}
+
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size)
+{
+    ptr_desc->BL |= buf1_size | (buf2_size << ETH_DMA_TDES_BUFFER2_SIZESHIFT);
+}
+
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag)
+{
+    return (FlagStatus)(ptr_desc->CS & flag);
+}
+
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc)
+{
+    ptr_desc->CS |= ETH_DMA_RDES_OWN;
+}
+
+u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc)
+{
+    return (ptr_desc->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FRAME_LENGTHSHIFT;
+}
+
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
+{
+    sta ? (ptr_desc->CS &= ~ETH_DMA_RDES_DIC) : (ptr_desc->CS |= ETH_DMA_RDES_DIC);
+}
+
+u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf)
+{
+    return (buf != ETH_DMA_RDES_Buffer1 ?
+            ((ptr_desc->BL & ETH_DMA_RDES_RBS2) >> ETH_DMA_RDES_BUFFER2_SIZESHIFT) :
+            (ptr_desc->BL & ETH_DMA_RDES_RBS1));
+}
+
+u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc)
+{
+    u32 len = 0;
+
+    if (    !(ptr_desc->CS & ETH_DMA_RDES_OWN) &&
+            !(ptr_desc->CS & ETH_DMA_RDES_ES) &&
+            (ptr_desc->CS & ETH_DMA_RDES_LS)) {
+        len = ETH_GetDMARxDescFrameLength(ptr_desc);
+    }
+
+    return len;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+void ETH_SoftwareReset(void)
+{
+    ETH->DMABMR |= ETH_DMABMR_SR;
+}
+
+FlagStatus ETH_GetSoftwareResetStatus(void)
+{
+    return (FlagStatus)(ETH->DMABMR & ETH_DMABMR_SR);
+}
+
+FlagStatus ETH_GetDMAFlagStatus(u32 flag)
+{
+    return (FlagStatus)(ETH->DMASR & flag);
+}
+
+void ETH_DMAClearFlag(u32 flag)
+{
+    ETH->DMASR = flag;
+}
+
+void ETH_DMAITConfig(u32 it, FunctionalState sta)
+{
+    sta ? (ETH->DMAIER |= it) : (ETH->DMAIER &= ~it);
+}
+
+ITStatus ETH_GetDMAITStatus(u32 it)
+{
+    return (ITStatus)(ETH->DMASR & it);
+}
+
+void ETH_DMAClearITPendingBit(u32 it)
+{
+    ETH->DMASR = it;
+}
+
+u32 ETH_GetTransmitProcessState(void)
+{
+    return ETH->DMASR & ETH_DMASR_TS;
+}
+
+u32 ETH_GetReceiveProcessState(void)
+{
+    return ETH->DMASR & ETH_DMASR_RS;
+}
+
+void ETH_FlushTransmitFIFO(void)
+{
+    ETH->DMAOMR |= ETH_DMAOMR_FTF;
+}
+
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
+{
+    return (FlagStatus)(ETH->DMAOMR & ETH_DMAOMR_FTF);
+}
+
+void ETH_DMATransmissionCmd(FunctionalState sta)
+{
+    sta ? (ETH->DMAOMR |= ETH_DMAOMR_ST) : (ETH->DMAOMR &= ~ETH_DMAOMR_ST);
+}
+
+void ETH_DMAReceptionCmd(FunctionalState sta)
+{
+    sta ? (ETH->DMAOMR |= ETH_DMAOMR_SR) : (ETH->DMAOMR &= ~ETH_DMAOMR_SR);
+}
+
+FlagStatus ETH_GetDMAOverflowStatus(u32 val)
+{
+    return (FlagStatus)(ETH->DMAMFBOCR & val);
+}
+
+u32 ETH_GetRxOverflowMissedFrameCounter(void)
+{
+    return (ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >>
+           ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT;
+}
+
+u32 ETH_GetBufferUnavailableMissedFrameCounter(void)
+{
+    return ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFC;
+}
+
+u32 ETH_GetCurrentTxDescStartAddress(void)
+{
+    return ETH->DMACHTDR;
+}
+
+u32 ETH_GetCurrentRxDescStartAddress(void)
+{
+    return ETH->DMACHRDR;
+}
+
+u32 ETH_GetCurrentTxBufferAddress(void)
+{
+    return ETH->DMACHTBAR;
+}
+
+u32 ETH_GetCurrentRxBufferAddress(void)
+{
+    return ETH->DMACHRBAR;
+}
+
+void ETH_ResumeDMATransmission(void)
+{
+    ETH->DMATPDR = 0;
+}
+
+void ETH_ResumeDMAReception(void)
+{
+    ETH->DMARPDR = 0;
+}
+
+void ETH_SetReceiveWatchdogTimer(u8 val)
+{
+    ETH->DMARSWTR = val;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+u16 ETH_ReadPHYRegister(u16 addr, u16 reg)
+{
+    u32 dat;
+    // Set phy address and reg address, clear write flag
+    ETH->MACMIIAR = (((ETH->MACMIIAR & ~MACMIIAR_CR_MASK) |
+                      (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) |
+                      (reg  << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR)) &
+                     (~ETH_MACMIIAR_MW)) | ETH_MACMIIAR_MB;
+
+    // Check busy flag
+    while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
+    dat = (u16)ETH->MACMIIDR;
+    if(dat == 0xFFFF) {
+        dat = 0;
+    }
+    return dat;
+}
+
+u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val)
+{
+    // Load data
+    ETH->MACMIIDR = val;
+
+    // Set phy address, reg address and write flag
+    ETH->MACMIIAR = (ETH->MACMIIAR & ~MACMIIAR_CR_MASK) |
+                    (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) |
+                    (reg  << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR) |
+                    ETH_MACMIIAR_MW |
+                    ETH_MACMIIAR_MB;
+
+    // Check busy flag
+    while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
+
+    return ETH->MACMIIDR;
+}
+
+u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta)
+{
+    u16 temp_val = ETH_ReadPHYRegister(addr, PHY_BCR);
+
+    sta ? (temp_val |= PHY_Loopback) : (temp_val &= ~PHY_Loopback);
+
+    if(ETH_WritePHYRegister(addr, PHY_BCR, temp_val))
+        return ETH_SUCCESS;
+
+    return ETH_ERROR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
+{
+    ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
+}
+
+void ETH_SetWakeUpFrameFilterRegister(u32* buf)
+{
+    u32 i = 0;
+
+    for (i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) {
+        ETH->MACRWUFFR = buf[i];
+    }
+}
+
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta)
+{
+    sta ?   (ETH->MACPMTCSR |= ETH_MACPMTCSR_GU) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU);
+}
+
+FlagStatus ETH_GetPMTFlagStatus(u32 flag)
+{
+    return (FlagStatus)(ETH->MACPMTCSR & flag);
+}
+
+void ETH_WakeUpFrameDetectionCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE);
+}
+
+void ETH_MagicPacketDetectionCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE);
+}
+
+void ETH_PowerDownCmd(FunctionalState sta)
+{
+    sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_PD) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+
+void ETH_MMCCounterFullPreset(void)
+{
+    ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP;
+}
+
+void ETH_MMCCounterHalfPreset(void)
+{
+    ETH->MMCCR &= ~ETH_MMCCR_MCFHP;
+
+    ETH->MMCCR |= ETH_MMCCR_MCP;
+}
+
+void ETH_MMCCounterFreezeCmd(FunctionalState sta)
+{
+    sta ? (ETH->MMCCR |= ETH_MMCCR_MCF) : (ETH->MMCCR &= ~ETH_MMCCR_MCF);
+}
+
+void ETH_MMCResetOnReadCmd(FunctionalState sta)
+{
+    sta ? (ETH->MMCCR |= ETH_MMCCR_ROR) : (ETH->MMCCR &= ~ETH_MMCCR_ROR);
+}
+
+void ETH_MMCCounterRolloverCmd(FunctionalState sta)
+{
+    sta ? (ETH->MMCCR &= ~ETH_MMCCR_CSR) : (ETH->MMCCR |= ETH_MMCCR_CSR);
+}
+
+void ETH_MMCCountersReset(void)
+{
+    ETH->MMCCR |= ETH_MMCCR_CR;
+}
+
+void ETH_MMCITConfig(u32 it, FunctionalState sta)
+{
+    if (it & 0x10000000) {
+        it &= 0xEFFFFFFF;
+
+        sta ? (ETH->MMCRIMR &= ~it) : (ETH->MMCRIMR |= it);
+    }
+    else {
+        sta ? (ETH->MMCTIMR &= ~it) : (ETH->MMCTIMR |= it);
+    }
+}
+
+ITStatus ETH_GetMMCITStatus(u32 it)
+{
+    if (it & 0x10000000) {
+        return (ITStatus)((ETH->MMCRIR & it) && !(ETH->MMCRIMR & it));
+    }
+    else {
+        return (ITStatus)((ETH->MMCTIR & it) && !(ETH->MMCTIMR & it));
+    }
+}
+
+u32 ETH_GetMMCRegister(u32 reg)
+{
+    return *(vu32*)(ETH_BASE + reg);
+}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c
new file mode 100644
index 000000000..409d84d80
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c
@@ -0,0 +1,222 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_exti.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE EXTI FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_EXTI_C_
+
+// Files includes
+#include "hal_exti.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup EXTI_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup EXTI_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the EXTI peripheral registers to their default reset
+///         values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the EXTI registers to their default reset values.
+/// @param  None.
+/// @retval None.
+/// @note   MEM_MODE bits are not affected by APB reset.
+/// @note   MEM_MODE bits took the value from the user option bytes.
+/// @note   CFGR2 register is not affected by APB reset.
+/// @note   CLABBB configuration bits are locked when set.
+/// @note   To unlock the configuration, perform a system reset.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_DeInit(void)
+{
+    u16 i;
+    // Clear all
+    exEXTI_LineDisable(~0x00000000);
+
+    // rc_w1
+    EXTI->PR = EXTI->PR;
+
+    // Set EXTI_CFGR1 register to reset value without affecting MEM_MODE bits
+    EXTI->CFGR &= EXTI_CFGR_MEMMODE;
+
+    // Set EXTICRx registers to reset value
+    for (i = 0; i < 4; i++) {
+        EXTI->CR[i] = 0;
+    }
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the GPIO pin used as EXTI Line.
+/// @param  port_source_gpio: selects the GPIO port to be used as source for EXTI lines .
+/// @param  pin_source: specifies the EXTI line to be configured.
+/// @note   This parameter can be pin_source where x can be:
+///         For MCU: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOD.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source)
+{
+    EXTI->CR[pin_source >> 0x02] &= ~(0x0F << (0x04 * (pin_source & 0x03)));
+    EXTI->CR[pin_source >> 0x02] |= ((port_source_gpio) << (0x04 * (pin_source & 0x03)));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the EXTI peripheral according to the specified
+///         parameters in the init_struct.
+/// @param  init_struct: pointer to a EXTI_InitTypeDef structure that
+///         contains the configuration information for the EXTI peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_Init(EXTI_InitTypeDef* init_struct)
+{
+    if (init_struct->EXTI_LineCmd != DISABLE) {
+        EXTI->IMR  &= ~init_struct->EXTI_Line;
+        EXTI->EMR  &= ~init_struct->EXTI_Line;
+        if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) {
+            EXTI->IMR |= init_struct->EXTI_Line;
+        }
+        else {
+            EXTI->EMR |= init_struct->EXTI_Line;
+        }
+        EXTI->RTSR &= ~init_struct->EXTI_Line;
+        EXTI->FTSR &= ~init_struct->EXTI_Line;
+        if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) {
+            EXTI->RTSR |= init_struct->EXTI_Line;
+            EXTI->FTSR |= init_struct->EXTI_Line;                               // Rising and Faling    afio
+        }
+        else if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising) {
+            EXTI->RTSR |= init_struct->EXTI_Line;
+        }
+        else {
+            EXTI->FTSR |= init_struct->EXTI_Line;
+        }
+    }
+    else {
+        if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) {
+            EXTI->IMR &= ~init_struct->EXTI_Line;
+        }
+        else {
+            EXTI->EMR &= ~init_struct->EXTI_Line;
+        }
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its reset value.
+/// @param  init_struct: pointer to a EXTI_InitTypeDef structure which will
+///         be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_StructInit(EXTI_InitTypeDef* init_struct)
+{
+    init_struct->EXTI_Line    = EXTI_LineNone;
+    init_struct->EXTI_Mode    = EXTI_Mode_Interrupt;
+    init_struct->EXTI_Trigger = EXTI_Trigger_Falling;
+    init_struct->EXTI_LineCmd = DISABLE;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Generates a Software interrupt on selected EXTI line.
+/// @param  line: specifies the EXTI line on which the software interrupt
+///         will be generated.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_GenerateSWInterrupt(u32 line)
+{
+    EXTI->SWIER |= line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified EXTI line flag is set or not.
+/// @param  line: specifies the EXTI line flag to check.
+/// @retval The new state of line (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus EXTI_GetFlagStatus(u32 line)
+{
+    return (EXTI->PR & line) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the EXTI's line pending flags.
+/// @param  line: specifies the EXTI lines flags to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_ClearFlag(u32 line)
+{
+    EXTI->PR = line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified EXTI line is asserted or not.
+/// @param  line: specifies the EXTI line to check.
+/// @retval The new state of line (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus EXTI_GetITStatus(u32 line)
+{
+    return ((EXTI->PR & line) && (EXTI->IMR & line)) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the EXTI's line pending bits.
+/// @param  line: specifies the EXTI lines to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void EXTI_ClearITPendingBit(u32 line)
+{
+    EXTI->PR = line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  EXTI Line Disable
+/// @param  line: specifies the EXTI lines to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exEXTI_LineDisable(u32 line)
+{
+    EXTI->IMR  &= ~line;
+    EXTI->EMR  &= ~line;
+    EXTI->RTSR &= ~line;
+    EXTI->FTSR &= ~line;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the EXTI's line all pending bits.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+u32 exEXTI_GetAllFlagStatus(void)
+{
+    return EXTI->PR;
+}
+
+/// @}
+
+/// @}
+
+/// @}
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c
new file mode 100644
index 000000000..ecdc8be3a
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c
@@ -0,0 +1,548 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_flash.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE FLASH FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_FLASH_C_
+
+// Files includes
+#include "hal_flash.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FLASH_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FLASH_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the code latency value.
+/// @note   This function can be used for all MM32 devices.
+/// @param  latency: specifies the FLASH Latency value.
+///         This parameter can be one of the following values:
+/// @arg    FLASH_Latency_0: FLASH Zero Latency cycle
+/// @arg    FLASH_Latency_1: FLASH One Latency cycle
+/// @arg    FLASH_Latency_2: FLASH Two Latency cycles
+/// @arg    FLASH_Latency_3: FLASH Three Latency cycles
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_SetLatency(FLASH_Latency_TypeDef latency)
+{
+    FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | latency;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Half cycle flash access.
+/// @note   This function can be used for all MM32 devices.
+/// @param  half_cycle_access: specifies the FLASH Half cycle Access mode.
+///         This parameter can be one of the following values:
+/// @arg    FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+/// @arg    FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access)
+{
+    FLASH->ACR &= ~FLASH_ACR_HLFCYA;
+    FLASH->ACR |= half_cycle_access;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Prefetch Buffer.
+/// @note   This function can be used for all MM32 devices.
+/// @param  prefetch_buffer: specifies the Prefetch buffer status.
+///         This parameter can be one of the following values:
+/// @arg    FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
+/// @arg    FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer)
+{
+    FLASH->ACR &= ~FLASH_ACR_PRFTBE;
+    FLASH->ACR |= prefetch_buffer;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Locks the FLASH Program Erase Controller.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_Lock(void)
+{
+    FLASH->CR |= FLASH_CR_LOCK;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Unlocks the FLASH Program Erase Controller.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_Unlock()
+{
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable to program the FLASH Option Byte.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_OPTB_Enable(void)
+{
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Erases a specified FLASH page.
+/// @note   This function can be used for all MM32 devices.
+/// @param  page_address: The page address to be erased.
+/// @retval FLASH Status: The returned value can be: FLASH_BUSY,
+///         FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ErasePage(u32 page_address)
+{
+    FLASH->CR |= FLASH_CR_PER;
+    FLASH->AR = page_address;
+    FLASH->CR |= FLASH_CR_STRT;
+    return FLASH_WaitForLastOperation(EraseTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Erases all FLASH pages.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_EraseAllPages()
+{
+    FLASH->AR = FLASH_BASE;
+    FLASH->CR |= (FLASH_CR_MER | FLASH_CR_STRT);
+    return FLASH_WaitForLastOperation(EraseTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Erases the FLASH option bytes.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_EraseOptionBytes()
+{
+    FLASH_OPTB_Enable();
+    FLASH->AR = OB_BASE;
+    FLASH->CR |= (FLASH_CR_OPTER | FLASH_CR_STRT);
+    return FLASH_WaitForLastOperation(EraseTimeout);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a half word at a specified address.
+/// @note   This function can be used for all MM32 devices.
+/// @param  address: specifies the address to be programmed.
+/// @param  data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data)
+{
+    FLASH->CR |= FLASH_CR_PG;
+
+    *(vu16*)address = data;
+
+
+    return FLASH_WaitForLastOperation(ProgramTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a word at a specified address.
+/// @note   This function can be used for all MM32 devices.
+/// @param  address: specifies the address to be programmed.
+/// @param  data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramWord(u32 address, u32 data)
+{
+    FLASH_Status ret = FLASH_ProgramHalfWord(address, data);
+    if (ret == FLASH_COMPLETE) {
+        ret = FLASH_ProgramHalfWord(address + 2, data >> 16);
+    }
+    return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a byte at a specified Option Byte Data address.
+/// @note   This function can be used for all MM32 devices.
+/// @param  address: specifies the address to be programmed.
+///         This parameter can be 0x1FFFF804 or 0x1FFFF806.
+/// @param  data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data)
+{
+    FLASH_Status ret;
+    __IO u16 temp;
+    FLASH_OPTB_Enable();
+    FLASH->CR |= FLASH_CR_OPTPG;
+    temp = (u16)(~data);
+    temp = (temp << 8) & 0xFF00;
+    temp = temp | (u16)data;
+    address = address & (~0x1);
+    *(vu16*)address = temp;
+    ret = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a half word at a specified Option Byte Data address.
+/// @note   This function can be used for all MM32 devices.
+/// @param  address: specifies the address to be programmed.
+///         This parameter can be 0x1FFFF804 or 0x1FFFF806.
+/// @param  data: specifies the data to be programmed.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data)
+{
+    FLASH_Status ret;
+    FLASH_OPTB_Enable();
+    FLASH->CR |= FLASH_CR_OPTPG;
+    *(vu16*)address = data;
+    ret = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Read protection for the specified address
+/// @note   This function can be used for all MM32 devices.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_ProgramProtect(u32 address, u16 data)
+{
+    return FLASH_ProgramOptionHalfWord(address, data);
+
+//    FLASH_Status ret;
+//  ret = FLASH_ProgramOptionHalfWord(address, 0x7F80);
+//
+//  if (ret == FLASH_COMPLETE) {
+//      ret = FLASH_ProgramOptionHalfWord(address + 2, 0xFF00);
+//    }
+//    return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Write protection for the specified address
+/// @note   This function can be used for all MM32 devices.
+/// @param  page: specifies the address of the pages to be write
+///         protected.
+///         This parameter is (0x01 << ((Absolute address - 0x08000000)/0x1000))
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_EnableWriteProtection(u32 page)
+{
+    FLASH_Status ret;
+    u8           i;
+    for (i = 0; i < 4; i++) {
+        ret = FLASH_ProgramOptionHalfWord((OB_BASE + 8 + i * 2), ~(page >> (i * 8)));
+        if (ret != FLASH_COMPLETE) {
+            break;
+        }
+    }
+    return ret;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+/// @note   This function can be used for all MM32 devices.
+/// @param  ob_iwdg: Selects the IWDG mode
+/// @param  ob_stop: Reset event when entering STOP mode.
+/// @param  standby: Reset event when entering Standby mode.
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef standby)
+{
+    FLASH_OPTB_Enable();
+    FLASH->CR |= FLASH_CR_OPTPG;
+    OB->USER = ob_iwdg;
+    OB->USER |= ob_stop;
+    OB->USER |= standby;
+    OB->USER |= 0xF8;
+    //    OB->USER = iwdg | stop | stdby | 0xF8;
+    return FLASH_WaitForLastOperation(ProgramTimeout);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the FLASH User Option Bytes values.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+///         and RST_STDBY(Bit2).
+////////////////////////////////////////////////////////////////////////////////
+u32 FLASH_GetUserOptionByte()
+{
+    return (FLASH->OBR >> 2);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the FLASH Write Protection Option Bytes Register value.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval The FLASH Write Protection  Option Bytes Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 FLASH_GetWriteProtectionOptionByte()
+{
+    return (FLASH->WRPR);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval FLASH Prefetch Buffer Status (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+    return (FLASH->ACR & FLASH_ACR_PRFTBS) ? SET : RESET;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified FLASH interrupts.
+/// @note   This function can be used for all MM32 devices.
+/// @param  interrupt: specifies the FLASH interrupt sources to be enabled or
+///         disabled.
+/// @param  state: new state of the specified Flash interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state)
+{
+    (state) ? (FLASH->CR |= interrupt) : (FLASH->CR &= ~interrupt);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified FLASH flag is set or not.
+/// @note   This function can be used for all MM32 devices.
+/// @param  flag: specifies the FLASH flags to clear.
+///         This parameter can be one of the following values:
+/// @arg    FLASH_FLAG_BSY: FLASH Busy flag
+/// @arg    FLASH_FLAG_PGERR: FLASH Program error flag
+/// @arg    FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+/// @arg    FLASH_FLAG_EOP: FLASH End of Operation flag
+/// @arg    FLASH_FLAG_OPTERR:  FLASH Option Byte error flag
+/// @retval The new state of FLASH_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus FLASH_GetFlagStatus(u16 flag)
+{
+    return ((flag == FLASH_FLAG_OPTERR) ? (FLASH->OBR & FLASH_FLAG_OPTERR) : (FLASH->SR & flag)) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the FLASH's pending flags.
+/// @note   This function can be used for all MM32 devices.
+/// @param  flag: specifies the FLASH flags to clear.
+///         This parameter can be any combination of the following values:
+/// @arg    FLASH_FLAG_PGERR: FLASH Program error flag
+/// @arg    FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+/// @arg    FLASH_FLAG_EOP: FLASH End of Operation flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FLASH_ClearFlag(u16 flag)
+{
+    FLASH->SR = flag;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the FLASH Status.
+/// @note   This function can be used for all MM32 devices.
+/// @param  None.
+/// @retval FLASH Status: The returned value can be: FLASH_BUSY,
+///         FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_GetStatus()
+{
+    return (FLASH_Status)((FLASH->SR & FLASH_FLAG_BSY))
+           ? FLASH_BUSY
+           : ((FLASH->SR & FLASH_FLAG_PGERR) ? FLASH_ERROR_PG
+              : ((FLASH->SR & FLASH_FLAG_WRPRTERR) ? FLASH_ERROR_WRP : FLASH_COMPLETE));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Waits for a Flash operation to complete or a TIMEOUT to occur.
+/// @note   This function can be used for all MM32 devices
+/// @param  time_out: FLASH programming time_out
+/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+////////////////////////////////////////////////////////////////////////////////
+FLASH_Status FLASH_WaitForLastOperation(u32 time_out)
+{
+    u32          i;
+    FLASH_Status ret;
+    do {
+        ret = FLASH_GetStatus();
+        time_out--;
+        for (i = 0xFF; i != 0; i--)
+            ;
+    } while ((ret == FLASH_BUSY) && (time_out != 0x00));
+
+    FLASH->CR = 0;
+    FLASH->SR = FLASH_SR_EOP | FLASH_SR_WRPRTERR | FLASH_SR_PGERR;
+    return (FLASH_Status)((time_out == 0x00) ? FLASH_TIMEOUT : ret);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Erases a specified FLASH page.
+/// @note   This function can be used for all MM32 devices.
+/// @param  Page_Address: The page address to be erased.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exFLASH_EraseEE(u32 page_address)
+{
+    FLASH_Unlock();
+    FLASH_ErasePage(page_address);
+    FLASH_Lock();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a buffer at a specified address.
+/// @note   This function can be used for all MM32 devices.
+/// @param *buf: the pointer of the buffer to be programmed.
+/// @param  addr: specifies the address to be programmed.
+/// @param  len: the number of bytes in the buffer.
+///         This parameter can only be even.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exFLASH_ProgramEE(u16* buf, u32 addr, u16 len)
+{
+    u16 i;
+    FLASH_Unlock();
+    for (i = 0; i < len / 2; i++) {
+        FLASH_ProgramHalfWord(addr, *buf);
+        addr += 2;
+        buf++;
+    }
+    FLASH_Lock();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Determine if the data that at the ptr address with the length is len
+///         is empty.
+/// @note   This function can be used for all MM32 devices.
+/// @param *ptr: the pointer of the starting address.
+/// @param  len: the number of bytes.
+///         This parameter can only be even.
+/// @retval 1 presents the data is empty,
+///         0 presents the data has been written.
+////////////////////////////////////////////////////////////////////////////////
+u8 exFLASH_FindEmpty(u16* ptr, u16 len)
+{
+    u16 i;
+    for (i = 0; i < (len / 2); i++) {
+        if (*(ptr + i) != 0xffff)
+            return 0;
+    }
+    return 1;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Locate the writable area on the specified address.
+/// @note   This function can be used for all MM32 devices.
+/// @param  page_address: specifies the beginning of the EEprom.
+///         The EEprom can be some continuously pages in the flash.
+/// @param  len: the number of bytes to be written.
+///         This parameter can only be even.
+/// @retval the pointer of the starting address.
+////////////////////////////////////////////////////////////////////////////////
+void* exFLASH_Locate(u32 page_address, u16 len)
+{
+    u16 i;
+    u16* ptr = (u16*)page_address;
+    for (i = 0; i < (0x0800 / len); i++) {
+        if (exFLASH_FindEmpty(ptr, len)) {
+            if (i == 0)
+                return 0;
+            break;
+        }
+        ptr += len / 2;
+    }
+    return ptr;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Programs a buffer at a specified address.
+/// @note   This function can be used for all MM32 devices.
+/// @param *buf: the pointer of the buffer to be programmed.
+/// @param  page_address: specifies the beginning of the EEprom.
+///         The EEprom can be some continuously pages in the flash.
+/// @param  len: the number of bytes in the buffer.
+///         This parameter can only be even.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len)
+{
+    u16* ptr = exFLASH_Locate(page_address, len);
+    if (ptr == 0) {
+        exFLASH_EraseEE(page_address + 0x000);
+        exFLASH_EraseEE(page_address + 0x400);
+        exFLASH_ProgramEE(buf, page_address, len);
+    }
+    else {
+        if (ptr == (u16*)(page_address + ((0x0400 / len) - 1) * len)) {
+            exFLASH_EraseEE(page_address + 0x400);
+            exFLASH_ProgramEE(buf, (u32)ptr, len);
+        }
+        else if (ptr == (u16*)(page_address + 0x0800)) {
+            exFLASH_EraseEE(page_address + 0x000);
+            exFLASH_ProgramEE(buf, (u32)page_address, len);
+        }
+        else {
+            exFLASH_ProgramEE(buf, (u32)ptr, len);
+        }
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Read the beginning address of the last written data.
+/// @note   This function can be used for all MM32 devices.
+/// @param  page_address: specifies the beginning of the EEprom.
+///         The EEprom can be some continuously pages in the flash.
+/// @param  len: the number of bytes have been written.
+///         This parameter can only be even.
+/// @retval the beginning address of the last written data.
+///         0 presents that this is the first time to use this as EEprom.
+////////////////////////////////////////////////////////////////////////////////
+void* exFLASH_ReadEE(u32 page_address, u16 len)
+{
+    u16* ptr = exFLASH_Locate(page_address, len);
+    return (ptr == 0) ? 0 : (ptr - len / 2);
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c
new file mode 100644
index 000000000..b4b665a0b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c
@@ -0,0 +1,124 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_fsmc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE FSMC FIRMWARE FUNCTIONS.
+///                Interface with SRAM, PSRAM, NOR memories
+///                Interrupts and flags management
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_FSMC_C_
+
+// Files includes
+#include "reg_rcc.h"
+#include "reg_syscfg.h"
+#include "hal_fsmc.h"
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FSMC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup FSMC_Exported_Functions
+/// @{
+
+
+void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct)
+{
+    init_struct->FSMC_Mode = FSMC_Mode_NorFlash;
+    init_struct->FSMC_AddrDataMode = FSMC_AddrDataDeMUX;
+
+    init_struct->FSMC_TimingRegSelect = FSMC_TimingRegSelect_0;
+    init_struct->FSMC_MemSize = FSMC_MemSize_64MB;
+    init_struct->FSMC_MemType = FSMC_MemType_NorSRAM;
+}
+void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct)
+{
+
+    init_struct->FSMC_SMReadPipe    = 0;
+    init_struct->FSMC_ReadyMode     = 0;
+    init_struct->FSMC_WritePeriod   = 0x2;
+    init_struct->FSMC_WriteHoldTime = 1;
+    init_struct->FSMC_AddrSetTime   = 3;
+    init_struct->FSMC_ReadPeriod    = 0x1;
+    init_struct->FSMC_DataWidth     = FSMC_DataWidth_16bits;
+}
+void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct)
+{
+    SYSCFG->CFGR &= ~(SYSCFG_CFGR_FSMC_MODE | SYSCFG_CFGR_FSMC_AF_ADDR | SYSCFG_CFGR_FSMC_SYNC_EN);
+    SYSCFG->CFGR |= (u32)init_struct->FSMC_Mode | \
+                    (u32)init_struct->FSMC_AddrDataMode;
+
+    FSMC->SMSKR = (u32)init_struct->FSMC_TimingRegSelect | \
+                  (u32)init_struct->FSMC_MemSize | \
+                  (u32)init_struct->FSMC_MemType;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initialize the FSMC_NORSRAM Timing according to the specified
+///         parameters in the FSMC_NORSRAM_TimingTypeDef
+/// @param  FSMC_Bank_InitStruct: Timing Pointer to NORSRAM Timing structure
+/// @param  Bank: NORSRAM bank number
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank)
+{
+    // Set FSMC_NORSRAM device timing parameters
+    if(bank == FSMC_NORSRAM_BANK0) {
+        FSMC->SMTMGR_SET0 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos)     | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos)   | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos)  | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
+        FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET0;
+        FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos;
+    }
+    else if(bank == FSMC_NORSRAM_BANK1) {
+        FSMC->SMTMGR_SET1 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos)     | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos)   | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos)  | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
+        FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET1;
+        FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos;
+    }
+    else if(bank == FSMC_NORSRAM_BANK2) {
+        FSMC->SMTMGR_SET2 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos)     | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos)   | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos)  | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos)    | \
+                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
+        FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET2;
+        FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos;
+    }
+}
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c
new file mode 100644
index 000000000..4363338f3
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c
@@ -0,0 +1,344 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_gpio.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE GPIO FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_GPIO_C_
+
+// Files includes
+#include "reg_exti.h"
+#include "hal_rcc.h"
+#include "hal_gpio.h"
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup GPIO_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup GPIO_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the gpio peripheral registers to their default reset
+///         values.
+/// @param  gpio: select the GPIO peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_DeInit(GPIO_TypeDef* gpio)
+{
+    switch (*(vu32*)&gpio) {
+        case (u32)GPIOA:
+            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, DISABLE);
+            break;
+        case (u32)GPIOB:
+            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOB, DISABLE);
+            break;
+        case (u32)GPIOC:
+            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOC, DISABLE);
+            break;
+        case (u32)GPIOD:
+            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOD, DISABLE);
+            break;
+        case (u32)GPIOE:
+            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOE, DISABLE);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the Alternate Functions (remap, event control
+///         and EXTI configuration) registers to their default reset values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_AFIODeInit()
+{
+    GPIOA->AFRL = 0xFFFFFFFF;
+    GPIOA->AFRH = 0xF00FFFFF;       //  PA14:SWCLK, PA13:PSWDIO
+    GPIOB->AFRL = 0xFFFFFFFF;
+    GPIOB->AFRH = 0xFFFFFFFF;
+    GPIOC->AFRL = 0xFFFFFFFF;
+    GPIOC->AFRH = 0xFFFFFFFF;
+    GPIOD->AFRL = 0xFFFFFFFF;
+    GPIOD->AFRH = 0xFFFFFFFF;
+    GPIOE->AFRL = 0xFFFFFFFF;
+    GPIOE->AFRH = 0xFFFFFFFF;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the gpio peripheral according to the specified
+///         parameters in the init_struct.
+/// @param  gpio: select the GPIO peripheral.
+/// @param  init_struct: pointer to a GPIO_InitTypeDef structure that
+///         contains the configuration information for the specified GPIO
+///         peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct)
+{
+    u8   idx;
+    u8 i;
+    u32 tmp;
+    __IO u32* reg ;
+
+    // 1x
+    u32 dat = init_struct->GPIO_Mode & 0x0F;
+    if (init_struct->GPIO_Mode & 0x10)
+        dat |= init_struct->GPIO_Speed;
+
+    // 0x
+    reg  = &gpio->CRL;
+    for (i = 0; i < 8; i++) {
+        idx = i * 4;
+        if ((init_struct->GPIO_Pin) & (1 << i)) {
+            *reg  = (*reg  & ~(0xF << idx)) | (dat << idx);
+        }
+    }
+
+    reg     = &gpio->CRH;
+    tmp = init_struct->GPIO_Pin >> 8;
+    for (i = 0; i < 8; i++) {
+        idx = i * 4;
+        if (tmp & (1 << i)) {
+            *reg  = (*reg  & ~(0xF << idx)) | (dat << idx);
+        }
+    }
+
+    // 2x,4x
+    if (init_struct->GPIO_Mode == GPIO_Mode_IPD)
+        gpio->BRR |= init_struct->GPIO_Pin;
+    else if (init_struct->GPIO_Mode == GPIO_Mode_IPU)
+        gpio->BSRR |= init_struct->GPIO_Pin;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param init_struct : pointer to a GPIO_InitTypeDef structure
+///   which will be initialized.
+/// @retval : None
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_StructInit(GPIO_InitTypeDef* init_struct)
+{
+    // Reset GPIO init structure parameters values
+    init_struct->GPIO_Pin  = GPIO_Pin_All;
+    init_struct->GPIO_Speed = GPIO_Speed_2MHz;
+    init_struct->GPIO_Mode = GPIO_Mode_FLOATING;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads the input data of specified GPIO port pin.
+/// @param  gpio:  select the GPIO peripheral.
+/// @param  pin:  specifies the port pin to be read.
+///         This parameter can be GPIO_Pin_x where x can be (0..15).
+/// @retval The input port pin value.
+////////////////////////////////////////////////////////////////////////////////
+bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin)
+{
+    return ((gpio->IDR & pin)) ? Bit_SET : Bit_RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads all GPIO port pins input data.
+/// @param  gpio: select the GPIO peripheral.
+/// @retval GPIO port input data value.
+////////////////////////////////////////////////////////////////////////////////
+u16 GPIO_ReadInputData(GPIO_TypeDef* gpio)
+{
+    return gpio->IDR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads the output data of specified GPIO port pin.
+/// @param  gpio: select the GPIO peripheral.
+/// @param  pin:  specifies the port bit to be read.
+///         This parameter can be GPIO_Pin_x where x can be (0..15).
+/// @retval The output port pin value.
+////////////////////////////////////////////////////////////////////////////////
+bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin)
+{
+    return (gpio->ODR & pin) ? Bit_SET : Bit_RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads all GPIO port pins output data.
+/// @param  gpio: select the GPIO peripheral.
+/// @retval GPIO port output data value.
+////////////////////////////////////////////////////////////////////////////////
+u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio)
+{
+    return gpio->ODR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the selected GPIO port pin.
+/// @param  gpio: where x can be (A..D) to select the GPIO peripheral.
+/// @param  pin: specifies the port pins to be written.
+///         This parameter can be any combination of GPIO_Pin_x where x can be
+///         (0..15).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin)
+{
+    gpio->BSRR = pin;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the selected GPIO port bit.
+/// @param  gpio: where x can be (A..D) to select the GPIO peripheral.
+/// @param  pin: specifies the port pins to be written.
+///         This parameter can be any combination of GPIO_Pin_x where x can be
+///         (0..15).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin)
+{
+    gpio->BRR = pin;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets or clears the selected GPIO port pin.
+/// @param  gpio: select the GPIO peripheral.
+/// @param  pin: specifies the port bit to be written.
+///         This parameter can be one of GPIO_Pin_x where x can be (0..15).
+/// @param  value: specifies the value to be written to the selected bit.
+///         This parameter can be one of the BitAction enum values:
+/// @arg    Bit_RESET: to clear the port pin
+/// @arg    Bit_SET: to set the port pin
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value)
+{
+    (value) ? (gpio->BSRR = pin) : (gpio->BRR = pin);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Writes data to all GPIO port pins.
+/// @param  gpio: where x can be (A..D) to select the GPIO peripheral.
+/// @param  value: specifies the value to be written to the port output data
+///         register.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_Write(GPIO_TypeDef* gpio, u16 value)
+{
+    gpio->ODR = value;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Locks GPIO Pins configuration.
+/// @param  gpio: to select the GPIO peripheral.
+/// @param  pin: specifies the port bit to be written.
+///         This parameter can be any combination of GPIO_Pin_x where x can be
+///         (0..15).
+/// @param  state: new lock state of the port pin.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state)
+{
+    (state) ? (gpio->LCKR |= pin) : (gpio->LCKR &= ~pin);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Locks GPIO Pins configuration registers until next system reset.
+/// @param  gpio: to select the GPIO peripheral.
+/// @param  pin: specifies the port bit to be written.
+///         This parameter can be any combination of GPIO_Pin_x where x can be
+///         (0..15).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin)
+{
+    gpio->LCKR = GPIO_LCKR_LCKK | pin;
+    gpio->LCKR = pin;
+    gpio->LCKR = GPIO_LCKR_LCKK | pin;
+    gpio->LCKR;
+    gpio->LCKR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the port pin remapping.
+/// @param  remap: selects the pin to remap.
+/// @param  mask: the corresponding remapping mask of the remapping pin.
+/// @param  state: new state of the port pin remapping.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Writes data to the specified GPIO data port.
+/// @param  gpio: select the GPIO peripheral.
+/// @param  pin: specifies the pin for the Alternate function.
+///         This parameter can be GPIO_PinSourcex where x can be (0..15) for
+///         GPIOA, GPIOB, GPIOD and (0..12) for GPIOC .
+/// @param  alternate_function: selects the pin to used as Alternate function.
+///         This parameter can be the GPIO_AF_x where x can be (0..7).
+/// @note   The pin should be used for Digital IP.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function)
+{
+    u8 shift = (pin & 0x07) * 4;
+    u32* ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH;
+    *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the remap function and AF function of the GPIO pin.
+/// @param  gpio:select the GPIO peripheral.
+/// @param  pin: specifies the pin for the Alternate function.
+///         This parameter can be GPIO_Pin_x where x can be (0..15) for
+///         GPIOA, GPIOB, GPIOD and (0..12) for GPIOC .
+/// @param  remap: selects the pin to remap.
+/// @param  alternate_function: selects the pin to used as Alternate function.
+///         This parameter can be the GPIO_AF_x where x can be (0..7).
+/// @note   The pin should be used for Digital IP.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function)
+{
+    u8 i;
+    u8 shift;
+    u32* ptr;
+
+    if (alternate_function >= 0) {
+        for (i = 0; i < 32; i++) {
+            if (pin & 0x01) {
+                pin = i;
+                break;
+            }
+            pin >>= 1;
+        }
+
+        shift = (pin & 0x07) * 4;
+        ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH;
+        *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift);
+    }
+}
+
+
+/// @}
+
+/// @}
+
+/// @}
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c
new file mode 100644
index 000000000..855236a63
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c
@@ -0,0 +1,526 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_i2c.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE I2C FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_I2C_C_
+
+// Files includes
+#include "hal_i2c.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup I2C_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup I2C_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the i2c peripheral registers to their default
+///         reset values.
+/// @param  i2c: where n can be 1 or 2 to select the I2C peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_DeInit(I2C_TypeDef* i2c)
+{
+    switch (*(vu32*)&i2c) {
+        case (u32)I2C1:  // I2C1_BASE:
+            exRCC_APB1PeriphReset(RCC_APB1ENR_I2C1);
+            break;
+        case (u32)I2C2:  // I2C2_BASE:
+            exRCC_APB1PeriphReset(RCC_APB1ENR_I2C2);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the i2c peripheral according to the specified
+///         parameters in the init_struct.
+/// @param  i2c: select the I2C peripheral.
+/// @param  init_struct: pointer to a I2C_InitTypeDef structure that
+///         contains the configuration information for the specified
+///         I2C peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct)
+{
+    u32 pclk1         = HSI_VALUE;
+    u32 minSclLowTime = 0;
+    u32 i2cPeriod     = 0;
+    u32 pclk1Period   = 0;
+
+
+    i2c->IC_ENABLE &= ~I2C_ENR_ENABLE;
+
+
+    pclk1       = RCC_GetPCLK1Freq();
+    pclk1Period = 1000000000 / pclk1;
+    i2cPeriod   = 1000000000 / init_struct->I2C_ClockSpeed;
+
+    minSclLowTime = pclk1 / init_struct->I2C_ClockSpeed ;
+    i2cPeriod = 82 / pclk1Period;
+
+    if (init_struct->I2C_ClockSpeed <= 100000) {
+        i2c->IC_SS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod) / 2;
+        i2c->IC_SS_SCL_HCNT = (minSclLowTime - 13 - i2cPeriod - i2c->IC_SS_SCL_LCNT);
+    }
+    else {
+        i2c->IC_FS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod ) / 2 + 4;
+        i2c->IC_FS_SCL_HCNT = (minSclLowTime - 13 - i2c->IC_FS_SCL_LCNT - i2cPeriod);
+    }
+
+    i2c->IC_CON &= ~(I2C_CR_EMPINT     |   \
+                     I2C_CR_SLAVEDIS   |   \
+                     I2C_CR_REPEN      |   \
+                     I2C_CR_MASTER10   |   \
+                     I2C_CR_SLAVE10    |   \
+                     I2C_CR_FAST       |   \
+                     I2C_CR_MASTER);
+
+    i2c->IC_CON =  I2C_CR_EMPINT       |   \
+                   I2C_CR_REPEN        |   \
+                   ((init_struct->I2C_Speed == I2C_CR_FAST) ? I2C_CR_FAST : I2C_CR_STD) | \
+                   ((init_struct->I2C_Mode)  ? I2C_CR_MASTER : 0x00);
+    i2c->IC_INTR_MASK &= INTR_MASK;
+
+    i2c->IC_RX_TL = 0x00;
+    i2c->IC_TX_TL = 0x00;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct: pointer to an I2C_InitTypeDef structure
+///         which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_StructInit(I2C_InitTypeDef* init_struct)
+{
+    init_struct->I2C_Mode       = I2C_CR_MASTER;
+    init_struct->I2C_OwnAddress = I2C_OWN_ADDRESS;
+    init_struct->I2C_Speed      = I2C_CR_STD;
+    init_struct->I2C_ClockSpeed = 100000;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified I2C peripheral.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the i2c peripheral. This parameter
+///         can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+    (state) ? (i2c->IC_ENABLE |= I2C_ENR_ENABLE) : (i2c->IC_ENABLE &= ~I2C_ENR_ENABLE);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified I2C DMA requests.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the I2C DMA transfer.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+    if (state) {
+        if (I2C_DMA_DIR == TDMAE_SET)
+            i2c->IC_DMA_CR |= TDMAE_SET;
+
+        else
+            i2c->IC_DMA_CR |= RDMAE_SET;
+    }
+    else
+        i2c->IC_DMA_CR &= ~(I2C_DMA_RXEN | I2C_DMA_TXEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Generates i2c communication START condition.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the I2C START condition generation.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state)
+{
+    (state) ? (i2c->IC_CON |= I2C_CR_REPEN) : (i2c->IC_CON &= ~I2C_CR_REPEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Generates i2c communication STOP condition.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the I2C STOP condition generation.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state)
+{
+    u16 overTime = 3000;
+
+    i2c->IC_ENABLE |= I2C_ENR_ABORT;
+
+    while (i2c->IC_ENABLE & I2C_ENR_ABORT) {
+        if (overTime-- == 0)
+            break;
+    }
+    i2c->IC_CLR_TX_ABRT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the specified I2C own address2.
+/// @param  i2c: select the I2C peripheral.
+/// @param  addr: specifies the 7bit I2C own address2.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr)
+{
+    MODIFY_REG(i2c->IC_TAR, (u16)I2C_TAR_ADDR, (u16)(addr >> 1));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified I2C dual addressing mode.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the I2C dual addressing mode.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+    (state) ? (i2c->IC_TAR |= IC_TAR_ENDUAL_Set) : (i2c->IC_TAR &= IC_TAR_ENDUAL_Reset);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified I2C general call feature.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the I2C General call.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state)
+{
+    (state) ? (i2c->IC_TAR |= I2C_TAR_SPECIAL) : (i2c->IC_TAR &= ~I2C_TAR_SPECIAL);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified I2C interrupts.
+/// @param  i2c: select the I2C peripheral.
+/// @param  it: specifies the I2C interrupts sources to be enabled
+///         or disabled.
+///         This parameter can be any combination of the following values:
+/// @arg    I2C_IT_RX_UNDER   : Rx Buffer is empty interrupt mask
+/// @arg    I2C_IT_RX_OVER    : RX  Buffer Overrun interrupt mask
+/// @arg    I2C_IT_RX_FULL    : Rx buffer full interrupt mask
+/// @arg    I2C_IT_TX_OVER    : TX  Buffer Overrun interrupt mask
+/// @arg    I2C_IT_TX_EMPTY   : TX_FIFO empty interrupt mask
+/// @arg    I2C_IT_RD_REQ     : I2C work as slave or master interrupt mask
+/// @arg    I2C_IT_TX_ABRT    : TX error interrupt  mask(Master mode)
+/// @arg    I2C_IT_RX_DONE    : Master not ack interrupt mask(slave mode)
+/// @arg    I2C_IT_ACTIVITY   : I2C activity interrupt mask
+/// @arg    I2C_IT_STOP_DET   : stop condition  interrupt mask
+/// @arg    I2C_IT_START_DET  : start condition  interrupt mask
+/// @arg    I2C_IT_GEN_CALL   : a general call address and ack interrupt mask
+/// @param  state: new state of the specified I2C interrupts.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state)
+{
+    if (it == I2C_IT_RX_FULL)
+        I2C_ReadCmd(i2c);
+    (state) ? SET_BIT(i2c->IC_INTR_MASK, it) : CLEAR_BIT(i2c->IC_INTR_MASK, (u16)it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sends a data byte through the i2c peripheral.
+/// @param  i2c: select the I2C peripheral.
+/// @param  dat: Byte to be transmitted..
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SendData(I2C_TypeDef* i2c, u8 dat)
+{
+    i2c->IC_DATA_CMD = dat;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the most recent received data by the i2c peripheral.
+/// @param  i2c: select the I2C peripheral.
+/// @retval The value of the received data.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ReadCmd(I2C_TypeDef* i2c)
+{
+    i2c->IC_DATA_CMD = I2C_DR_CMD;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the most recent received data by the i2c peripheral.
+/// @param  i2c: select the I2C peripheral.
+/// @retval The value of the received data.
+////////////////////////////////////////////////////////////////////////////////
+u8 I2C_ReceiveData(I2C_TypeDef* i2c)
+{
+    I2C_CMD_DIR = 0;
+    return (u8)i2c->IC_DATA_CMD;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Transmits the address byte to select the slave device.
+/// @param  i2c: select the I2C peripheral.
+/// @param  addr: specifies the slave address which will be transmitted
+/// @param  dir: specifies whether the I2C device will be a
+///   Transmitter or a Receiver.
+///   This parameter can be one of the following values
+/// @arg  I2C_Direction_Transmitter: Transmitter mode
+/// @arg  I2C_Direction_Receiver: Receiver mode
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir)
+{
+    i2c->IC_TAR = addr >> 1;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads the specified I2C register and returns its value.
+/// @param  i2c: select the I2C peripheral.
+/// @param  reg: specifies the register to read.
+///         This parameter can be one of the following values:
+/// @retval The value of the read register.
+////////////////////////////////////////////////////////////////////////////////
+u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg)
+{
+    return (*(vu16*)(*((u32*)&i2c) + reg));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the last i2c Event.
+/// @param  i2c: select the I2C peripheral.
+/// @retval The last event
+////////////////////////////////////////////////////////////////////////////////
+u32 I2C_GetLastEvent(I2C_TypeDef* i2c)
+{
+    return (u32)i2c->IC_RAW_INTR_STAT & FLAG_Mask;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the last i2c Event is equal to the one passed
+///   as parameter.
+/// @param  i2c: select the I2C peripheral.
+/// @param  event: specifies the event to be checked.
+///   This parameter can be one of the following values:
+/// @arg  I2C_EVENT_RX_UNDER : Rx Buffer is empty event
+/// @arg  I2C_EVENT_RX_OVER  : RX  Buffer Overrun event
+/// @arg  I2C_EVENTT_RX_FULL : Rx buffer full event
+/// @arg  I2C_EVENT_TX_OVER  : TX  Buffer Overrun event
+/// @arg  I2C_EVENT_TX_EMPTY : TX_FIFO empty event
+/// @arg  I2C_EVENT_RD_REQ   : I2C work as slave or master event
+/// @arg  I2C_EVENT_TX_ABRT  : TX error event(Master mode)
+/// @arg  I2C_EVENT_RX_DONE  : Master not ack event(slave mode)
+/// @arg  I2C_EVENT_ACTIVITY : I2C activity event
+/// @arg  I2C_EVENT_STOP_DET : stop condition  event
+/// @arg  I2C_EVENT_START_DET: start condition  event
+/// @arg  I2C_EVENT_GEN_CALL : a general call address and ack event
+/// - SUCCESS: Last event is equal to the I2C_EVENT
+/// - ERROR: Last event is different from the I2C_EVENT
+////////////////////////////////////////////////////////////////////////////////
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event)
+{
+    if ((event == I2C_EVENT_RX_FULL) && (I2C_CMD_DIR == 0)) {
+        i2c->IC_DATA_CMD = I2C_DR_CMD;
+        I2C_CMD_DIR       = 1;
+    }
+
+    return (ErrorStatus)((i2c->IC_RAW_INTR_STAT & event) == event);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified I2C flag is set or not.
+/// @param  i2c: select the I2C peripheral.
+/// @param  flag: specifies the flag to check.
+///   This parameter can be one of the following values:
+/// @arg  I2C_FLAG_RX_UNDER : Rx Buffer is empty flag
+/// @arg  I2C_FLAG_RX_OVER  : RX  Buffer Overrun flag
+/// @arg  I2C_FLAG_RX_FULL  : Rx buffer full flag
+/// @arg  I2C_FLAG_TX_OVER  : TX  Buffer Overrun flag
+/// @arg  I2C_FLAG_TX_EMPTY : TX_FIFO empty flag
+/// @arg  I2C_FLAG_RD_REQ   : I2C work as slave or master flag
+/// @arg  I2C_FLAG_TX_ABRT  : TX error flag(Master mode)
+/// @arg  I2C_FLAG_RX_DONE  : Master not ack flag(slave mode)
+/// @arg  I2C_FLAG_ACTIVITY : I2C activity flag
+/// @arg  I2C_FLAG_STOP_DET : stop condition  flag
+/// @arg  I2C_FLAG_START_DET: start condition  flag
+/// @arg  I2C_FLAG_GEN_CALL : a general call address and ack flag
+/// @retval The new state of I2C_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag)
+{
+    if (flag & 0x8000)
+        return ((i2c->IC_STATUS & flag) ? SET : RESET);
+
+    if ((flag == I2C_FLAG_RX_FULL) && (I2C_CMD_DIR == 0)) {
+        i2c->IC_DATA_CMD = I2C_DR_CMD;
+        I2C_CMD_DIR       = 1;
+    }
+    return (((i2c->IC_RAW_INTR_STAT & flag)) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the i2c's pending flags.
+/// @param  i2c: select the I2C peripheral.
+/// @param  flag: specifies the flag to clear.
+///   This parameter can be any combination of the following values:
+/// @arg  I2C_FLAG_RX_UNDER : Rx Buffer is empty flag
+/// @arg  I2C_FLAG_RX_OVER  : RX  Buffer Overrun flag
+/// @arg  I2C_FLAG_RX_FULL  : Rx buffer full flag
+/// @arg  I2C_FLAG_TX_OVER  : TX  Buffer Overrun flag
+/// @arg  I2C_FLAG_TX_EMPTY : TX_FIFO empty flag
+/// @arg  I2C_FLAG_RD_REQ   : I2C work as slave or master flag
+/// @arg  I2C_FLAG_TX_ABRT  : TX error flag(Master mode)
+/// @arg  I2C_FLAG_RX_DONE  : Master not ack flag(slave mode)
+/// @arg  I2C_FLAG_ACTIVITY : I2C activity flag
+/// @arg  I2C_FLAG_STOP_DET : stop condition  flag
+/// @arg  I2C_FLAG_START_DET: start condition  flag
+/// @arg  I2C_FLAG_GEN_CALL : a general call address and ack flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag)
+{
+    if ((flag & I2C_FLAG_RX_UNDER) == I2C_FLAG_RX_UNDER)
+        i2c->IC_CLR_RX_UNDER;
+    if ((flag & I2C_FLAG_RX_OVER) == I2C_FLAG_RX_OVER)
+        i2c->IC_CLR_RX_OVER;
+    if ((flag & I2C_FLAG_TX_OVER) == I2C_FLAG_TX_OVER)
+        i2c->IC_CLR_TX_OVER;
+    if ((flag & I2C_FLAG_RD_REQ) == I2C_FLAG_RD_REQ)
+        i2c->IC_CLR_RD_REQ;
+    if ((flag & I2C_FLAG_TX_ABRT) == I2C_FLAG_TX_ABRT)
+        i2c->IC_CLR_TX_ABRT;
+    if ((flag & I2C_FLAG_RX_DONE) == I2C_FLAG_RX_DONE)
+        i2c->IC_CLR_RX_DONE;
+    if ((flag & I2C_FLAG_ACTIVITY) == I2C_FLAG_ACTIVITY)
+        i2c->IC_CLR_ACTIVITY;
+    if ((flag & I2C_FLAG_STOP_DET) == I2C_FLAG_STOP_DET)
+        i2c->IC_CLR_STOP_DET;
+    if ((flag & I2C_FLAG_START_DET) == I2C_FLAG_START_DET)
+        i2c->IC_CLR_START_DET;
+    if ((flag & I2C_FLAG_GEN_CALL) == I2C_FLAG_GEN_CALL)
+        i2c->IC_CLR_GEN_CALL;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified I2C interrupt has occurred or not.
+/// @param  i2c: select the I2C peripheral.
+/// @param  it: specifies the interrupt source to check.
+///   This parameter can be one of the following values:
+/// @arg  I2C_IT_RX_UNDER : Rx Buffer is empty interrupt
+/// @arg  I2C_IT_RX_OVER  : RX  Buffer Overrun interrupt
+/// @arg  I2C_IT_RX_FULL  : Rx buffer full interrupt
+/// @arg  I2C_IT_TX_OVER  : TX  Buffer Overrun interrupt
+/// @arg  I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
+/// @arg  I2C_IT_RD_REQ   : I2C work as slave or master interrupt
+/// @arg  I2C_IT_TX_ABRT  : TX error interrupt  (Master mode)
+/// @arg  I2C_IT_RX_DONE  : Master not ack interrupt (slave mode)
+/// @arg  I2C_IT_ACTIVITY : I2C activity interrupt
+/// @arg  I2C_IT_STOP_DET : stop condition  interrupt
+/// @arg  I2C_IT_START_DET: start condition  interrupt
+/// @arg  I2C_IT_GEN_CALL : a general call address and ack interrupt
+/// @retval The new state of I2C_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it)
+{
+    return ((i2c->IC_RAW_INTR_STAT & it) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the i2c interrupt pending bits.
+/// @param  i2c: select the I2C peripheral.
+/// @param  it: specifies the interrupt pending bit to clear.
+///   This parameter can be any combination of the following values:
+/// @arg  I2C_IT_RX_UNDER : Rx Buffer is empty interrupt
+/// @arg  I2C_IT_RX_OVER  : RX  Buffer Overrun interrupt
+/// @arg  I2C_IT_RX_FULL  : Rx buffer full interrupt
+/// @arg  I2C_IT_TX_OVER  : TX  Buffer Overrun interrupt
+/// @arg  I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
+/// @arg  I2C_IT_RD_REQ   : I2C work as slave or master interrupt
+/// @arg  I2C_IT_TX_ABRT  : TX error interrupt  (Master mode)
+/// @arg  I2C_IT_RX_DONE  : Master not ack interrupt (slave mode)
+/// @arg  I2C_IT_ACTIVITY : I2C activity interrupt
+/// @arg  I2C_IT_STOP_DET : stop condition  interrupt
+/// @arg  I2C_IT_START_DET: start condition  interrupt
+/// @arg  I2C_IT_GEN_CALL : a general call address and ack interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it)
+{
+    if ((it & I2C_IT_RX_UNDER) == I2C_FLAG_RX_UNDER)
+        i2c->IC_CLR_RX_UNDER;
+    if ((it & I2C_IT_RX_OVER) == I2C_FLAG_RX_OVER)
+        i2c->IC_CLR_RX_OVER;
+    if ((it & I2C_IT_TX_OVER) == I2C_FLAG_TX_OVER)
+        i2c->IC_CLR_TX_OVER;
+    if ((it & I2C_IT_RD_REQ) == I2C_FLAG_RD_REQ)
+        i2c->IC_CLR_RD_REQ;
+    if ((it & I2C_IT_TX_ABRT) == I2C_FLAG_TX_ABRT)
+        i2c->IC_CLR_TX_ABRT;
+    if ((it & I2C_IT_RX_DONE) == I2C_FLAG_RX_DONE)
+        i2c->IC_CLR_RX_DONE;
+    if ((it & I2C_IT_ACTIVITY) == I2C_FLAG_ACTIVITY)
+        i2c->IC_CLR_ACTIVITY;
+    if ((it & I2C_IT_STOP_DET) == I2C_FLAG_STOP_DET)
+        i2c->IC_CLR_STOP_DET;
+    if ((it & I2C_IT_START_DET) == I2C_FLAG_START_DET)
+        i2c->IC_CLR_START_DET;
+    if ((it & I2C_IT_GEN_CALL) == I2C_FLAG_GEN_CALL)
+        i2c->IC_CLR_GEN_CALL;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//
+//  New Function Interface
+//
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures slave address.
+/// @param  i2c: select the I2C peripheral.
+/// @param  addr: specifies the slave address which will be transmitted
+///   This parameter can be one of the following values
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr)
+{
+    WRITE_REG(i2c->IC_SAR, addr >> 1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the I2C slave mode.
+/// @param  i2c: select the I2C peripheral.
+/// @param  state: new state of the specified I2C interrupts.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state)
+{
+    (state) ? CLEAR_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS) : SET_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS);
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c
new file mode 100644
index 000000000..06b49fb24
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c
@@ -0,0 +1,208 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_iwdg.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE IWDG FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_IWDG_C_
+
+// Files includes
+#include "hal_iwdg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup IWDG_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup IWDG_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables write access to IWDG_PR and IWDG_RLR
+///   registers.
+/// @param  write_access: new state of write access to IWDG_PR and
+///   IWDG_RLR registers.
+///   This parameter can be one of the following values:
+/// @arg IWDG_WriteAccess_Enable: Enable write access to
+///   IWDG_PR and IWDG_RLR registers
+/// @arg IWDG_WriteAccess_Disable: Disable write access to
+///   IWDG_PR and IWDG_RLR registers
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_WriteAccessCmd(u16 write_access)
+{
+    IWDG->KR = write_access;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets IWDG Prescaler value.
+/// @param  prescaler: specifies the IWDG Prescaler value.
+///         This parameter can be one of the following values:
+/// @arg    IWDG_Prescaler_4: IWDG prescaler set to 4
+/// @arg    IWDG_Prescaler_8: IWDG prescaler set to 8
+/// @arg    IWDG_Prescaler_16: IWDG prescaler set to 16
+/// @arg    IWDG_Prescaler_32: IWDG prescaler set to 32
+/// @arg    IWDG_Prescaler_64: IWDG prescaler set to 64
+/// @arg    IWDG_Prescaler_128: IWDG prescaler set to 128
+/// @arg    IWDG_Prescaler_256: IWDG prescaler set to 256
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_SetPrescaler(u8 prescaler)
+{
+    IWDG->PR = prescaler;
+    PVU_CheckStatus();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set IWDG reload value.
+/// @param  reload: specifies the IWDG reload value.
+///         This parameter must be a number between 0 and 0x0FFF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_SetReload(u16 reload)
+{
+    IWDG->RLR = reload;
+    RVU_CheckStatus();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Get IWDG reload value.
+/// @param  None.
+/// @retval reload: specifies the IWDG reload value.
+////////////////////////////////////////////////////////////////////////////////
+u32 IWDG_GetReload(void)
+{
+    return IWDG->RLR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reloads IWDG counter with value defined in the reload register
+///   (write access to IWDG_PR and IWDG_RLR registers disabled).
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_ReloadCounter(void)
+{
+    IWDG->KR = KR_KEY_Reload;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
+///         disabled).
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_Enable(void)
+{
+    IWDG->KR = KR_KEY_Enable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified IWDG flag is set or not.
+/// @param  flag: specifies the flag to check.
+///   This parameter can be one of the following values:
+/// @arg    IWDG_FLAG_PVU: Prescaler Value Update on going
+/// @arg    IWDG_FLAG_RVU: reload Value Update on going
+/// @retval The new state of flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus IWDG_GetFlagStatus(u16 flag)
+{
+    return ((IWDG->SR & flag) != (u32)RESET) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks prescaler value has been updated.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PVU_CheckStatus(void)
+{
+    while (IWDG_GetFlagStatus(IWDG_FLAG_PVU) == SET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks count relead value has been updated.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RVU_CheckStatus(void)
+{
+    while (IWDG_GetFlagStatus(IWDG_FLAG_RVU) == SET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  IWDG overflow configuration.
+/// @param  overflow_config
+/// @arg    IWDG_Overflow_Interrupt: Interrupt after overflow.
+/// @arg    IWDG_Overflow_Reset:     Reset after overflow.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config)
+{
+    IWDG->CR &= ~IWDG_CR_IRQSEL;
+    IWDG->CR |= overflow_config;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clear interrupt flag
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_ClearITPendingBit(void)
+{
+    IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clear interrupt flag
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_ClearIT(void)
+{
+    IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable IWDG interrupt function
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_EnableIT(void)
+{
+    IWDG->CR |= IWDG_CR_IRQSEL;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Disable IWDG interrupt function
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void IWDG_Reset(void)
+{
+    IWDG->CR &= ~IWDG_CR_IRQSEL;
+}
+
+
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c
new file mode 100644
index 000000000..598d6d07e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c
@@ -0,0 +1,147 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_misc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE MSIC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_MISC_C_
+
+// Files includes
+#include "hal_misc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MSIC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MISC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the NVIC interrupt vector table.
+/// @param  vect_tab
+///         This parameter can be any combination of the following values:
+///    @arg NVIC_VectTab_RAM
+///    @arg NVIC_VectTab_FLASH
+/// @param  offset
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_SetVectorTable(u32 vect_tab, u32 offset)
+{
+    SCB->VTOR = vect_tab | (offset & (u32)0x1FFFFF80);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the NVIC interrupt priority group.
+/// @param  priority_group
+///         This parameter can be any combination of the following values:
+///    @arg NVIC_PriorityGroup_0
+///    @arg NVIC_PriorityGroup_1
+///    @arg NVIC_PriorityGroup_2
+///    @arg NVIC_PriorityGroup_3
+///    @arg NVIC_PriorityGroup_4
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_PriorityGroupConfig(u32 priority_group)
+{
+    SCB->AIRCR = AIRCR_VECTKEY_MASK | priority_group;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  NVIC initialization.
+/// @param  init_struct
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_Init(NVIC_InitTypeDef* init_struct)
+{
+    if (init_struct->NVIC_IRQChannelCmd != DISABLE) {
+        u32 pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos;
+
+        pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) |
+               (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri)))
+              << 0x04;
+
+        NVIC->IP[init_struct->NVIC_IRQChannel]           = pri;
+        NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+    }
+    else {
+        NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+    }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  NVIC initialized extension function.
+/// @param  init_struct
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exNVIC_Init(exNVIC_Init_TypeDef* init_struct)
+{
+    u32 pri;
+
+    if (init_struct->NVIC_IRQChannelCmd != DISABLE) {
+        pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos;
+
+        pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) |
+               (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri))) << 0x04;
+
+        NVIC->IP[init_struct->NVIC_IRQChannel] = pri;
+        NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+    }
+    else {
+        NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
+    }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  System low power mode configuration.
+/// @param  low_power_mode
+///         This parameter can be any combination of the following values:
+///    @arg NVIC_LP_SEVONPEND
+///    @arg NVIC_LP_SLEEPDEEP
+///    @arg NVIC_LP_SLEEPONEXIT
+/// @param  state: new state of the low power mode.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state)
+{
+    (state) ? (SCB->SCR |= low_power_mode) : (SCB->SCR &= ~(u32)low_power_mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SysTick clock source configuration.
+/// @param  systick_clk_source
+///         This parameter can be any combination of the following values:
+///    @arg SysTick_CLKSource_EXTCLK
+///    @arg SysTick_CLKSource_HCLK
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SysTick_CLKSourceConfig(u32 systick_clk_source)
+{
+    (systick_clk_source == SysTick_CLKSource_HCLK) ? (SysTick->CTRL |= SysTick_CLKSource_HCLK) \
+    : (SysTick->CTRL &= ~SysTick_CLKSource_HCLK);
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c
new file mode 100644
index 000000000..e39bf3f31
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c
@@ -0,0 +1,215 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_pwr.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE PWR FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define __HAL_PWR_C_
+
+// Files includes
+#include "hal_pwr.h"
+#include "hal_rcc.h"
+#include "hal_syscfg.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup PWR_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup PWR_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the PWR peripheral registers to their default reset
+/// values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_DeInit(void)
+{
+    exRCC_APB1PeriphReset(RCC_APB1ENR_PWR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables access to the RTC and backup registers.
+/// @param  state: new state of the access to the RTC and backup
+///         registers. This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_BackupAccessCmd(FunctionalState state)
+{
+    (state) ? (RCC->BDCR |= RCC_BDCR_DBP) : (RCC->BDCR &= ~RCC_BDCR_DBP);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Power Voltage Detector(PVD).
+/// @param  state: new state of the PVD.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_PVDCmd(FunctionalState state)
+{
+    (state) ? (SYSCFG->PDETCSR |= SYSCFG_PDETCSR_PVDE) : (SYSCFG->PDETCSR &= ~SYSCFG_PDETCSR_PVDE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the voltage threshold detected by the Power Voltage
+///         Detector(PVD).
+/// @param  pvd_level: specifies the PVD detection level
+///         This parameter can be one of the following values:
+/// @arg    emPVD_LEVEL0 : PVD detection level set to 1.7V
+/// @arg    emPVD_LEVEL1 : PVD detection level set to 2.0V
+/// @arg    emPVD_LEVEL2 : PVD detection level set to 2.3V
+/// @arg    emPVD_LEVEL3 : PVD detection level set to 2.6V
+/// @arg    emPVD_LEVEL4 : PVD detection level set to 2.9V
+/// @arg    emPVD_LEVEL5 : PVD detection level set to 3.2V
+/// @arg    emPVD_LEVEL6 : PVD detection level set to 3.5V
+/// @arg    emPVD_LEVEL7 : PVD detection level set to 3.8V
+/// @arg    emPVD_LEVEL8 : PVD detection level set to 4.1V
+/// @arg    emPVD_LEVEL9 : PVD detection level set to 4.4V
+/// @arg    emPVD_LEVEL10: PVD detection level set to 4.7V
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level)
+{
+    SYSCFG->PDETCSR = (SYSCFG->PDETCSR & (~SYSCFG_PDETCSR_PLS)) | pvd_level;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the WakeUp Pin functionality.
+/// @param  state: new state of the WakeUp Pin functionality.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_WakeUpPinCmd(FunctionalState state)
+{
+    (state != DISABLE) ? (PWR->CR2 |= PWR_CR2_EWUP1) : (PWR->CSR &= ~PWR_CR2_EWUP1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the WakeUp Pin functionality.
+/// @param  state: new state of the WakeUp Pin functionality.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_WakeUpPinXCmd(emWUP_Pin_Typedef pin, FunctionalState state)
+{
+    (state != DISABLE) ? (PWR->CR2 |= (PWR_CR2_EWUP1 << pin)) : (PWR->CSR &= ~(PWR_CR2_EWUP1 << pin));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enters STOP mode.
+/// @param  regulator: specifies the regulator state in STOP mode.
+///         This parameter can be one of the following values:
+/// @arg    PWR_Regulator_ON: STOP mode with regulator ON
+/// @arg    PWR_Regulator_LowPower: STOP mode with regulator in low power mode.
+/// @param  stop_entry: specifies if STOP mode in entered with WFI or  WFE
+///         instruction.
+///         This parameter can be one of the following values:
+/// @arg    PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+/// @arg    PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry)
+{
+
+    MODIFY_REG(PWR->CR, PWR_CR_LDPS, regulator);
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    if(stop_entry == PWR_STOPEntry_WFI) {
+        __WFI();
+    }
+    else {
+        __WFE();
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enters STANDBY mode.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_EnterSTANDBYMode(void)
+{
+    PWR->CR |= PWR_CR_PDDS;
+    PWR->SCR |= PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5 | PWR_SCR_CWUF6;
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+#if defined(__CC_ARM)
+    __force_stores();
+#endif
+    __WFI();
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified PWR flag is set or not.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+/// @arg    PWR_FLAG_WU: Wake Up flag
+/// @arg    PWR_FLAG_SB: StandBy flag
+/// @arg    PWR_FLAG_PVDO: PVD Output
+/// @retval The new state of PWR_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus PWR_GetPVDOFlagStatus(u32 flag)
+{
+    return (FlagStatus)(SYSCFG->PDETCSR & flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the PWR's pending flags.
+/// @param  flag: specifies the flag to clear.
+///         This parameter can be one of the following values:
+/// @arg    PWR_FLAG_WU: Wake Up flag
+/// @arg    PWR_FLAG_SB: StandBy flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_ClearPVDOFlag(u32 flag)
+{
+    PWR->CR |= flag << 2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified PWR flag is set or not.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+/// @arg    PWR_FLAG_WU: Wake Up flag
+/// @arg    PWR_FLAG_SB: StandBy flag
+/// @arg    PWR_FLAG_PVDO: PVD Output
+/// @retval The new state of PWR_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus PWR_GetFlagStatus(u32 flag)
+{
+    return (FlagStatus)(PWR->CSR & flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the PWR's pending flags.
+/// @param  flag: specifies the flag to clear.
+///         This parameter can be one of the following values:
+/// @arg    PWR_FLAG_WU: Wake Up flag
+/// @arg    PWR_FLAG_SB: StandBy flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void PWR_ClearFlag(u32 flag)
+{
+    PWR->CR |= flag << 2;
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c
new file mode 100644
index 000000000..5e2bd1a85
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c
@@ -0,0 +1,995 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_rcc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE RCC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_RCC_C_
+
+// Files includes
+#include "mm32_reg.h"
+#include "hal_rcc.h"
+
+
+
+u8 tbPresc[] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RCC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RCC_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Resets the RCC clock configuration to default state.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_DeInit()
+{
+    SET_BIT(RCC->CR, RCC_CR_HSION);
+    CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
+    CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON );
+    CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP);
+    CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+    CLEAR_REG(RCC->CFGR);
+    CLEAR_REG(RCC->CIR);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the External High Speed oscillator (HSE).
+/// @param  state: specifies the new state of HSE.
+///         This parameter can be one of the following values:
+/// @arg    RCC_HSE_OFF: HSE oscillator OFF
+/// @arg    RCC_HSE_ON: HSE oscillator ON
+/// @arg    RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_HSEConfig(RCCHSE_TypeDef state)
+{
+    RCC->CR &= ~(RCC_CR_HSEBYP | RCC_CR_HSEON);
+    switch (state) {
+        case RCC_HSE_Bypass:
+            RCC->CR |= RCC_CR_HSEBYP;
+            RCC->CR |= RCC_CR_HSEON;
+            break;
+        case RCC_HSE_ON:
+            RCC->CR |= RCC_CR_HSEON;
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified RCC flag is set or not.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+/// @arg    RCC_FLAG_HSIRDY: HSI oscillator clock ready
+/// @arg    RCC_FLAG_HSERDY: HSE oscillator clock ready
+/// @arg    RCC_FLAG_PLLRDY: PLL clock ready
+/// @arg    RCC_FLAG_LSERDY: LSE oscillator clock ready
+/// @arg    RCC_FLAG_LSIRDY: LSI oscillator clock ready
+/// @arg    RCC_FLAG_PINRST: Pin reset
+/// @arg    RCC_FLAG_PORRST: POR/PDR reset
+/// @arg    RCC_FLAG_SFTRST: Software reset
+/// @arg    RCC_FLAG_IWDGRST: Independent Watchdog reset
+/// @arg    RCC_FLAG_WWDGRST: Window Watchdog reset
+/// @arg    RCC_FLAG_LPWRRST: Low Power reset
+/// @retval The new state of flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag)
+{
+    return ((((flag >> 5) == CR_REG_INDEX) ? RCC->CR : (((flag >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) &
+            (1 << (flag & 0x1F)))
+           ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Waits for HSE start-up.
+/// @param  None.
+/// @retval An ErrorStatus enumuration value:
+///         - SUCCESS: HSE oscillator is stable and ready to use
+///         - ERROR: HSE oscillator not yet ready
+////////////////////////////////////////////////////////////////////////////////
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+    u32 StartUpCounter = 0;
+
+    FlagStatus HSEStatus;
+
+    do {
+        HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+        StartUpCounter++;
+    } while ((HSEStatus == RESET) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    return (ErrorStatus)(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) ? SUCCESS : ERROR;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Waits for flag start-up.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+/// @arg    RCC_FLAG_HSIRDY: HSI oscillator clock ready
+/// @arg    RCC_FLAG_HSERDY: HSE oscillator clock ready
+/// @arg    RCC_FLAG_PLLRDY: PLL clock ready
+/// @arg    RCC_FLAG_LSERDY: LSE oscillator clock ready
+/// @arg    RCC_FLAG_LSIRDY: LSI oscillator clock ready
+/// @arg    RCC_FLAG_PINRST: Pin reset
+/// @arg    RCC_FLAG_PORRST: POR/PDR reset
+/// @arg    RCC_FLAG_SFTRST: Software reset
+/// @arg    RCC_FLAG_IWDGRST: Independent Watchdog reset
+/// @arg    RCC_FLAG_WWDGRST: Window Watchdog reset
+/// @retval An ErrorStatus enumuration value:
+///         - SUCCESS: HSE oscillator is stable and ready to use
+///         - ERROR: HSE oscillator not yet ready
+////////////////////////////////////////////////////////////////////////////////
+ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag)
+{
+    u32 StartUpCounter = 0;
+
+    while (RCC_GetFlagStatus(flag) == RESET) {
+        if (StartUpCounter++ > HSE_STARTUP_TIMEOUT) {
+            return ERROR;
+        }
+    }
+    return SUCCESS;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Internal High Speed oscillator (HSI).
+/// @param  state: new state of the HSI.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_HSICmd(FunctionalState state)
+{
+    MODIFY_REG(RCC->CR, RCC_CR_HSION, (state << RCC_CR_HSION_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the system clock (SYSCLK).
+/// @param  sys_clk_source: specifies the clock source used as system
+///         clock. This parameter can be one of the following values:
+/// @arg    RCC_HSI: specifies HSI as system clock
+/// @arg    RCC_HSE: specifies HSE as system clock
+/// @arg    RCC_PLL: specifies PLL as system clock
+/// @arg    RCC_LSI: specifies LSI as system clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_source)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (sys_clk_source << RCC_CFGR_SW_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the PLL clock source and DM DN factor.
+///         This function must be used only when the PLL is disabled.
+/// @param  plldn: specifies the PLL multiplication factor.
+///         This parameter can be RCC_PLLMul_x where x:[31:26]
+/// @param  plldm: specifies the PLL Divsior factor.
+///         This parameter can be RCC_Divsior_x where x:[22:20]
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PLLDMDNConfig(u32 plldn, u32 plldm)
+{
+    MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP), ((plldn << RCC_PLLCFGR_PLL_DN_Pos) | (plldm << RCC_PLLCFGR_PLL_DP_Pos)));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the PLL.
+///   The PLL can not be disabled if it is used as system clock.
+/// @param  state: new state of the PLL.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PLLCmd(FunctionalState state)
+{
+    MODIFY_REG(RCC->CR, RCC_CR_PLLON, (state << RCC_CR_PLLON_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the PLL clock source and multiplication factor.
+///         This function must be used only when the PLL is disabled.
+/// @param  pll_src: specifies the PLL entry clock source.
+///         This parameter can be one of the following values:
+/// @arg    RCC_HSI_Div4: HSI oscillator clock divided
+///         by 4 selected as PLL clock entry
+/// @arg    RCC_HSE_Div1: HSE oscillator clock selected
+///         as PLL clock entry
+/// @arg    RCC_HSE_Div2: HSE oscillator clock divided
+///         by 2 selected as PLL clock entry
+/// @param  pll_mul: specifies the PLL multiplication factor.
+///         This parameter can be RCC_PLLMul_x where x:[31:26][22:20]
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul)
+{
+    const u8 DNDM_Item[] = {0x07, 0x03, 0x05, 0x01, 0x07, 0x01, 0x09, 0x01,  // Frclk*8/4 ; Frclk*6/2 ; Frclk*8/2 ; Frclk*10/2;
+                            0x0B, 0x01, 0x0D, 0x01, 0x0F, 0x01, 0x11, 0x01,  // Frclk*12/2; Frclk*14/2; Frclk*16/2; Frclk*18/2;
+                            0x13, 0x01, 0x15, 0x01, 0x17, 0x01, 0x19, 0x01,  // Frclk*20/2; Frclk*22/2; Frclk*24/2; Frclk*26/2;
+                            0x1B, 0x01, 0x1D, 0x01, 0x1F, 0x01
+                           };             // Frclk*28/2; Frclk*30/2;    // Frclk*32/2;
+    MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC), pll_src);
+    RCC_PLLDMDNConfig((u32)DNDM_Item[pll_mul >> 17], (u32)DNDM_Item[(pll_mul >> 17) + 1]);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the USB clock (USBCLK).
+/// @param  usb_clk_src: specifies the USB clock source.
+///         This clock is derived from the PLL output.
+///         This parameter can be one of the following values:
+/// @arg    RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+/// @arg    RCC_USBCLKSource_PLLCLK_Div2: PLL clock divided by 2 selected as USB
+///         clock source
+/// @arg    RCC_USBCLKSource_PLLCLK_Div3: PLL clock divided by 3 selected as USB
+///         clock source
+/// @arg    RCC_USBCLKSource_PLLCLK_Div4: PLL clock divided by 4 selected as USB
+///         clock source
+/// @arg    RCC_USBCLKSource_PLLCLK_Div5: PLL clock divided by 5 selected as USB
+///         clock source
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (usb_clk_src << RCC_CFGR_USBPRE_Pos));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the clock source used as system clock.
+/// @param  None.
+/// @retval The clock source used as system clock. The returned value can
+///         be one of the following:
+///         - 0x00: HSI/6 used as system clock
+///         - 0x04: HSE used as system clock
+///         - 0x08: PLL used as system clock
+////////////////////////////////////////////////////////////////////////////////
+u8 RCC_GetSYSCLKSource(void)
+{
+    return ((u8)READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the AHB clock (hclk).
+/// @param  sys_clk: defines the AHB clock divider. This clock is derived
+///                    from the system clock (SYSCLK).
+///         This parameter can be one of the following values:
+/// @arg    RCC_SYSCLK_Div1: AHB clock = SYSCLK
+/// @arg    RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+/// @arg    RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+/// @arg    RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+/// @arg    RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+/// @arg    RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+/// @arg    RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+/// @arg    RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+/// @arg    RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, sys_clk);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the Low Speed APB clock (pclk1).
+/// @param  hclk: defines the APB1 clock divider. This clock is derived from
+///                  the AHB clock (hclk).
+///         This parameter can be one of the following values:
+/// @arg    RCC_HCLK_Div1: APB1 clock = hclk
+/// @arg    RCC_HCLK_Div2: APB1 clock = hclk/2
+/// @arg    RCC_HCLK_Div4: APB1 clock = hclk/4
+/// @arg    RCC_HCLK_Div8: APB1 clock = hclk/8
+/// @arg    RCC_HCLK_Div16: APB1 clock = hclk/16
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, hclk);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the High Speed APB clock (pclk2).
+/// @param  hclk: defines the APB2 clock divider. This clock is derived from
+///                  the AHB clock (hclk).
+///         This parameter can be one of the following values:
+/// @arg    RCC_HCLK_Div1: APB2 clock = hclk
+/// @arg    RCC_HCLK_Div2: APB2 clock = hclk/2
+/// @arg    RCC_HCLK_Div4: APB2 clock = hclk/4
+/// @arg    RCC_HCLK_Div8: APB2 clock = hclk/8
+/// @arg    RCC_HCLK_Div16: APB2 clock = hclk/16
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (hclk << 3));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the ADC clock (ADCCLK).
+/// @param  pclk2: defines the ADC clock divider. This clock is derived from
+///                   the APB2 clock (pclk2).
+///         This parameter can be one of the following values:
+/// @arg    RCC_PCLK2_Div2: ADC clock = pclk2/2
+/// @arg    RCC_PCLK2_Div4: ADC clock = pclk2/4
+/// @arg    RCC_PCLK2_Div6: ADC clock = pclk2/6
+/// @arg    RCC_PCLK2_Div8: ADC clock = pclk2/8
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2)
+{
+    MODIFY_REG(RCC->CFGR, ADC_CFGR_PRE, pclk2);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the External Low Speed oscillator (LSE).
+/// @param  state: specifies the new state of the LSE.
+///         This parameter can be one of the following values:
+/// @arg    RCC_LSE_OFF: LSE oscillator OFF
+/// @arg    RCC_LSE_ON: LSE oscillator ON
+/// @arg    RCC_LSE_Bypass: LSE oscillator bypassed with external
+///         clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_LSEConfig(RCC_LSE_TypeDef state)
+{
+    RCC->BDCR &= ~(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON);
+
+    switch (state) {
+        case RCC_LSE_Bypass:
+            RCC->BDCR |= RCC_BDCR_LSEBYP;
+            RCC->BDCR |= RCC_BDCR_LSEON;
+            break;
+        case RCC_LSE_ON:
+            RCC->BDCR |= RCC_BDCR_LSEON;
+            break;
+        default:
+            break;
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the RTC clock (RTCCLK).
+///         Once the RTC clock is selected it can be changed unless the
+///         Backup domain is reset.
+/// @param  rtc_clk_src: specifies the RTC clock source.
+///         This parameter can be one of the following values:
+/// @arg    RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+/// @arg    RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+/// @arg    RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
+///         selected as RTC clock
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src)
+{
+    MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, rtc_clk_src);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the RTC clock.
+///         This function must be used only after the RTC clock was
+///         selected using the RCC_RTCCLKConfig function.
+/// @param  state: new state of the RTC clock.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_RTCCLKCmd(FunctionalState state)
+{
+    MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCEN, (state << RCC_BDCR_RTCEN_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+///         LSI can not be disabled if the IWDG is running.
+/// @param  state: new state of the LSI.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_LSICmd(FunctionalState state)
+{
+//    u32 j;
+    MODIFY_REG(RCC->CSR, RCC_CSR_LSION | RCC_CSR_LSIOENLV, RCC_CSR_LSIOENLV | (state << RCC_CSR_LSION_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the clock frequency of different on chip clocks.
+/// @param  None.
+/// @retval sys_clk : System clock frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetSysClockFreq(void)
+{
+    u32 result;
+    u32 clock, mul, div;
+    switch (RCC->CFGR & RCC_CFGR_SWS) {
+        case RCC_CFGR_SWS_LSI:
+            result = LSI_VALUE;
+            break;
+
+        case RCC_CFGR_SWS_HSE:
+            result = HSE_VALUE;
+            break;
+
+        case RCC_CFGR_SWS_PLL:
+            clock = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) ? (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLXTPRE) ? (HSE_VALUE >> 1) : HSE_VALUE)
+                    : HSI_VALUE_PLL_ON;
+            mul = ((RCC->PLLCFGR & (u32)RCC_PLLCFGR_PLL_DN) >> RCC_PLLCFGR_PLL_DN_Pos) + 1;
+            div = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL_DP) >> RCC_PLLCFGR_PLL_DP_Pos) + 1;
+
+            result = clock * mul / div;
+            break;
+        default:
+            result =  HSI_VALUE;
+            break;
+    }
+    return result;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the hclk frequency of different on chip clocks.
+/// @param  None.
+/// @retval hclk frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetHCLKFreq(void)
+{
+    return (RCC_GetSysClockFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the pclk1 frequency of different on chip clocks.
+/// @param  None.
+/// @retval pclk1 frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetPCLK1Freq(void)
+{
+    return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the pclk2 frequency of different on chip clocks.
+/// @param  None.
+/// @retval pclk2 frequency
+////////////////////////////////////////////////////////////////////////////////
+u32 RCC_GetPCLK2Freq(void)
+{
+    return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the frequency of different on chip clocks.
+/// @param  clk: pointer to a RCC_ClocksTypeDef structure which
+///   will hold the clocks frequency.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk)
+{
+    u8 tbADCPresc[] = {2, 4, 6, 8};
+
+    clk->SYSCLK_Frequency = RCC_GetSysClockFreq();
+    clk->HCLK_Frequency   = RCC_GetHCLKFreq();
+    clk->PCLK1_Frequency  = RCC_GetPCLK1Freq();
+    clk->PCLK2_Frequency  = RCC_GetPCLK2Freq();
+
+    clk->ADCCLK_Frequency = clk->PCLK2_Frequency / tbADCPresc[(RCC->CFGR & ADC_CFGR_PRE) >> ADC_CFGR_PRE_Pos];
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the AHB peripheral clock.
+/// @param  ahb_periph: specifies the AHB peripheral to gates its clock.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph);
+}
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHB2ENR |= ahb_periph) : (RCC->AHB2ENR &= ~ahb_periph);
+}
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHB3ENR |= ahb_periph) : (RCC->AHB3ENR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
+/// @param  apb2_periph: specifies the APB2 peripheral to gates its
+///   clock.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state)
+{
+    (state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
+/// @param  apb1_periph: specifies the APB1 peripheral to gates its
+///   clock.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state)
+{
+    (state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+/// @param  apb2_periph: specifies the APB2 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral reset.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state)
+{
+    (state) ? (RCC->APB2RSTR |= apb2_periph) : (RCC->APB2RSTR &= ~apb2_periph);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+/// @param  apb1_periph: specifies the APB1 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state)
+{
+    (state) ? (RCC->APB1RSTR |= apb1_periph) : (RCC->APB1RSTR &= ~apb1_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed AHB peripheral reset.
+/// @param  ahb_periph: specifies the AHB peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHBRSTR |= ahb_periph) : (RCC->AHBRSTR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed AHB2 peripheral reset.
+/// @param  ahb_periph: specifies the AHB peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHB2RSTR |= ahb_periph) : (RCC->AHB2RSTR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed AHB2 peripheral reset.
+/// @param  ahb_periph: specifies the AHB peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @param  state: new state of the specified peripheral clock.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state)
+{
+    (state) ? (RCC->AHB3RSTR |= ahb_periph) : (RCC->AHB3RSTR &= ~ahb_periph);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases the Backup domain reset.
+/// @param  state: new state of the Backup domain reset.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_BackupResetCmd(FunctionalState state)
+{
+    MODIFY_REG(RCC->BDCR, RCC_BDCR_BDRST, (state << RCC_BDCR_BDRST_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the Clock Security System.
+/// @param  state: new state of the Clock Security System..
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ClockSecuritySystemCmd(FunctionalState state)
+{
+    MODIFY_REG(RCC->CR, RCC_CR_CSSON, (state << RCC_CR_CSSON_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the clock source to output on MCO pin.
+/// @param  mco_src: specifies the clock source to output.
+///   This parameter can be one of the following values:
+/// @arg RCC_MCO_NoClock: No clock selected
+/// @arg RCC_MCO_LSI: LSI oscillator clock selected
+/// @arg RCC_MCO_LSE: LSE oscillator clock selected
+/// @arg RCC_MCO_SYSCLK: System clock selected
+/// @arg RCC_MCO_HSI: HSI oscillator clock selected
+/// @arg RCC_MCO_HSE: HSE oscillator clock selected
+/// @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_MCOConfig(RCC_MCO_TypeDef mco_src)
+{
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, mco_src);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the RCC reset flags.
+///   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+///   RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
+///   RCC_FLAG_LPWRRST
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ClearFlag(void)
+{
+    SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified RCC interrupts.
+/// @param  it: specifies the RCC interrupt sources to be enabled or
+/// disabled.
+///   This parameter can be any combination of the following values:
+/// @arg RCC_IT_LSIRDY: LSI ready interrupt
+/// @arg RCC_IT_LSERDY: LSE ready interrupt
+/// @arg RCC_IT_HSIRDY: HSI ready interrupt
+/// @arg RCC_IT_HSERDY: HSE ready interrupt
+/// @arg RCC_IT_PLLRDY: PLL ready interrupt
+/// @param  state: new state of the specified RCC interrupts.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state)
+{
+    (state) ? SET_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos) : CLEAR_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified RCC interrupt has occurred or not.
+/// @param  it: specifies the RCC interrupt source to check.
+///   This parameter can be one of the following values:
+/// @arg RCC_IT_LSIRDY: LSI ready interrupt
+/// @arg RCC_IT_LSERDY: LSE ready interrupt
+/// @arg RCC_IT_HSIRDY: HSI ready interrupt
+/// @arg RCC_IT_HSERDY: HSE ready interrupt
+/// @arg RCC_IT_PLLRDY: PLL ready interrupt
+/// @arg RCC_IT_CSS: Clock Security System interrupt
+/// @retval The new state of it (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus RCC_GetITStatus(RCC_IT_TypeDef it)
+{
+    return (ITStatus)READ_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYF_Pos));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the RCC�?interrupt pending bits.
+/// @param  it: specifies the interrupt pending bit to clear.
+///   This parameter can be any combination of the following values:
+/// @arg RCC_IT_LSIRDY: LSI ready interrupt
+/// @arg RCC_IT_LSERDY: LSE ready interrupt
+/// @arg RCC_IT_HSIRDY: HSI ready interrupt
+/// @arg RCC_IT_HSERDY: HSE ready interrupt
+/// @arg RCC_IT_PLLRDY: PLL ready interrupt
+/// @arg RCC_IT_CSS: Clock Security System interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ClearITPendingBit(u8 it)
+{
+    SET_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYC_Pos));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+/// @param  apb1_periph: specifies the APB1 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB1PeriphReset(u32 apb1_periph)
+{
+    RCC->APB1RSTR |= apb1_periph;
+    RCC->APB1RSTR &= ~apb1_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed APB (APB2) peripheral reset.
+/// @param  apb2_periph: specifies the APB2 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_APB2PeriphReset(u32 apb2_periph)
+{
+    RCC->APB2RSTR |= apb2_periph;
+    RCC->APB2RSTR &= ~apb2_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases High Speed AHB (AHB1) peripheral reset.
+/// @param  ahb1_periph: specifies the AHB1 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_AHBPeriphReset(u32 ahb1_periph)
+{
+    RCC->AHBRSTR |= ahb1_periph;
+    RCC->AHBRSTR &= ~ahb1_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+//
+//  New Function Interface
+//
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+/// @param  apb1_periph: specifies the APB1 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_APB1PeriphReset(u32 apb1_periph)
+{
+    RCC->APB1RSTR |= apb1_periph;
+    RCC->APB1RSTR &= ~apb1_periph;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief
+/// @param
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_BackupReset()
+{
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+/// @param  apb2_periph: specifies the APB2 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_APB2PeriphReset(u32 apb2_periph)
+{
+    RCC->APB2RSTR |= apb2_periph;
+    RCC->APB2RSTR &= ~apb2_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces or releases High Speed AHB (AHB1) peripheral reset.
+/// @param  ahb1_periph: specifies the AHB1 peripheral to reset.
+///   This parameter can be any combination of the following values:
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_AHBPeriphReset(u32 ahb1_periph)
+{
+    RCC->AHBRSTR |= ahb1_periph;
+    RCC->AHBRSTR &= ~ahb1_periph;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Disable systick
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_SystickDisable()
+{
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable systick
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exRCC_SystickEnable(u32 sys_tick_period)
+{
+    SysTick_Config(RCC_GetHCLKFreq() / 1000000 * sys_tick_period);
+}
+
+/*
+(state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph);
+(state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph);
+(state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph);
+*/
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified ADC peripheral Clock.
+/// @param  peripheral:select the ADC peripheral.
+/// @param  state: new state of the ADC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state)
+{
+    switch (*(vu32*)&peripheral) {
+
+        case ADC1_BASE:
+            (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC1) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC1);
+            break;
+        case ADC2_BASE:
+            (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC2) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC2);
+            break;
+        case ADC3_BASE:
+            (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC3) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC3);
+            break;
+        default:
+            break;
+    }
+
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified BKP peripheral Clock.
+/// @param  peripheral:select the BKP peripheral.
+/// @param  state: new state of the BKP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_BKP_ClockCmd(BKP_TypeDef* peripheral, FunctionalState state)
+{
+    if(BKP == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_BKP) : (RCC->APB1ENR &= ~RCC_APB1ENR_BKP);
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_PWR) : (RCC->APB1ENR &= ~RCC_APB1ENR_PWR);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified CAN peripheral Clock.
+/// @param  peripheral:select the CAN peripheral.
+/// @param  state: new state of the CAN peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_CAN_ClockCmd(CAN_TypeDef* peripheral, FunctionalState state)
+{
+    if(CAN1 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_CAN) : (RCC->APB1ENR &= ~RCC_APB1ENR_CAN);
+    }
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified COMP peripheral Clock.
+/// @param  peripheral:select the COMP peripheral.
+/// @param  state: new state of the COMP peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_COMP_ClockCmd(COMP_TypeDef* peripheral, FunctionalState state)
+{
+    if(COMP == peripheral) {
+        (state) ? (RCC->APB2ENR |= RCC_APB2ENR_COMP) : (RCC->APB2ENR &= ~RCC_APB2ENR_COMP);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified CRC peripheral Clock.
+/// @param  peripheral:select the CRC peripheral.
+/// @param  state: new state of the CRC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_CRC_ClockCmd(CRC_TypeDef* peripheral, FunctionalState state)
+{
+    if(CRC == peripheral) {
+        (state) ? (RCC->AHBENR |= RCC_AHBENR_CRC) : (RCC->AHBENR &= ~RCC_AHBENR_CRC);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DAC peripheral Clock.
+/// @param  peripheral:select the DAC peripheral.
+/// @param  state: new state of the DAC peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_DAC_ClockCmd(DAC_TypeDef* peripheral, FunctionalState state)
+{
+    if(DAC == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_DAC) : (RCC->APB1ENR &= ~RCC_APB1ENR_DAC);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified DMA peripheral Clock.
+/// @param  peripheral:select the DMA peripheral.
+/// @param  state: new state of the DMA peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_DMA_ClockCmd(DMA_TypeDef* peripheral, FunctionalState state)
+{
+    if(DMA1 == peripheral) {
+        (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA1) : (RCC->AHBENR &= ~RCC_AHBENR_DMA1);
+    }
+    if(DMA2 == peripheral) {
+        (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA2) : (RCC->AHBENR &= ~RCC_AHBENR_DMA2);
+    }
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified GPIO peripheral Clock.
+/// @param  peripheral:select the GPIO peripheral.
+/// @param  state: new state of the GPIO peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state)
+{
+    switch (*(vu32*)&peripheral) {
+        case (u32)GPIOA:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOA) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOA);
+            break;
+        case (u32)GPIOB:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOB) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOB);
+            break;
+        case (u32)GPIOC:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOC) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOC);
+            break;
+        case (u32)GPIOD:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOD) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOD);
+            break;
+        case (u32)GPIOE:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOE) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOE);
+            break;
+        case (u32)GPIOF:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOF) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOF);
+            break;
+        case (u32)GPIOG:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOG) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOG);
+            break;
+        case (u32)GPIOH:
+            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOH) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOH);
+            break;
+        default:
+            break;
+    }
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the uart peripheral registers to their
+///         default reset values.
+/// @param  peripheral: Select the UART or the UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RCC_UART_ClockCmd(UART_TypeDef* peripheral, FunctionalState state)
+{
+    if(UART2 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART2) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART2);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART2);
+    }
+    if(UART1 == peripheral) {
+        (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART1) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART1);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART1);
+    }
+    if(UART3 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART3) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART3);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART3);
+    }
+    if(UART4 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART4) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART4);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART4);
+    }
+    if(UART5 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART5) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART5);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART5);
+    }
+    if(UART6 == peripheral) {
+        (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART6) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART6);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART6);
+    }
+    if(UART7 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART7) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART7);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART7);
+    }
+    if(UART8 == peripheral) {
+        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART8) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART8);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART8);
+    }
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c
new file mode 100644
index 000000000..b02c6750b
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c
@@ -0,0 +1,234 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_rtc.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE RTC FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_RTC_C_
+
+// Files includes
+#include "hal_rtc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RTC_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup RTC_Exported_Functions
+/// @{
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified RTC interrupts.
+/// @param  it: specifies the RTC interrupts sources to be enabled or
+///         disabled.
+///         This parameter can be any combination of the following values:
+/// @arg    RTC_IT_OW: Overflow interrupt
+/// @arg    RTC_IT_ALR: Alarm interrupt
+/// @arg    RTC_IT_SEC: Second interrupt
+/// @param  state: new state of the specified RTC interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state)
+{
+    (state == ENABLE) ? (RTC->CR |= it) : (RTC->CR &= (u16)~it);
+//    RTC_WaitForLastTask();
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enters the RTC configuration mode.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_EnterConfigMode(void)
+{
+//    PWR->CR |= PWR_CR_DBP;
+    RTC->CSR |= RTC_CSR_CNF;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Exits from the RTC configuration mode.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ExitConfigMode(void)
+{
+    RTC->CSR &= ~RTC_CSR_CNF;
+    while (!(RTC->CSR & RTC_CSR_RTOFF));
+//    PWR->CR  &= ~PWR_CR_DBP;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the RTC counter value.
+/// @param  None.
+/// @retval RTC counter value.
+////////////////////////////////////////////////////////////////////////////////
+u32 RTC_GetCounter(void)
+{
+    u32 dat = RTC->CNTH << 16;
+    return (RTC->CNTL | dat);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the RTC counter value.
+/// @param  count: RTC counter new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_SetCounter(u32 count)
+{
+    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+    RTC->CNTH = count >> 16;
+    RTC->CNTL = count;
+    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+//    while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the RTC prescaler value.
+/// @param  prescaler: RTC prescaler new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_SetPrescaler(u32 prescaler)
+{
+    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+    RTC->PRLH = prescaler >> 16;
+    RTC->PRLL = prescaler;
+    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+//    while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the RTC alarm value.
+/// @param  alarm: RTC alarm new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_SetAlarm(u32 alarm)
+{
+    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+    RTC->ALRH = alarm >> 16;
+    RTC->ALRL = alarm;
+    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+//    while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the RTC divider value.
+/// @param  None.
+/// @retval RTC Divider value.
+////////////////////////////////////////////////////////////////////////////////
+u32 RTC_GetDivider(void)
+{
+    u32 dat = ((u32)(RTC->DIVH & RTC_DIVH_DIV) << 16);
+    return (RTC->DIVL | dat);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Waits until last write operation on RTC registers has finished.
+/// @note   This function must be called before any write to RTC registers.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_WaitForLastTask(void)
+{
+    while (!(RTC->CSR & RTC_CSR_RTOFF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+///         are synchronized with RTC APB clock.
+/// @note   This function must be called before any read operation after an APB
+///         reset or an APB clock stop.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_WaitForSynchro(void)
+{
+    RTC->CSR &= ~RTC_CSR_RSF;
+    while (!(RTC->CSR & RTC_CSR_RSF));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified RTC flag is set or not.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one the following values:
+/// @arg    RTC_FLAG_RTOFF: RTC Operation OFF flag
+/// @arg    RTC_FLAG_RSF: Registers Synchronized flag
+/// @arg    RTC_FLAG_OW: Overflow flag
+/// @arg    RTC_FLAG_ALR: Alarm flag
+/// @arg    RTC_FLAG_SEC: Second flag
+/// @retval The state of RTC_FLAG (SET or RESET).
+/////////////////////////////////////////////////////////////////////////////////
+FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag)
+{
+    return  (FlagStatus)(RTC->CSR & flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the RTC's pending flags.
+/// @param  flag: specifies the flag to clear.
+///         This parameter can be any combination of the following values:
+/// @arg    RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only
+///         after an APB reset or an APB Clock stop.
+/// @arg    RTC_FLAG_OW: Overflow flag
+/// @arg    RTC_FLAG_ALR: Alarm flag
+/// @arg    RTC_FLAG_SEC: Second flag
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ClearFlag(RTC_FLAG_TypeDef flag)
+{
+    RTC->CSR &= ~flag;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified RTC interrupt has occurred or not.
+/// @param  it: specifies the RTC interrupts sources to check.
+///         This parameter can be one of the following values:
+/// @arg    RTC_IT_OW: Overflow interrupt
+/// @arg    RTC_IT_ALR: Alarm interrupt
+/// @arg    RTC_IT_SEC: Second interrupt
+/// @retval The state of the RTC_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus RTC_GetITStatus(RTC_IT_TypeDef it)
+{
+    return  (ITStatus)(RTC->CSR & it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the RTC's interrupt pending bits.
+/// @param  it: specifies the interrupt pending bit to clear.
+///         This parameter can be any combination of the following values:
+/// @arg    RTC_IT_OW: Overflow interrupt
+/// @arg    RTC_IT_ALR: Alarm interrupt
+/// @arg    RTC_IT_SEC: Second interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void RTC_ClearITPendingBit(RTC_IT_TypeDef it)
+{
+//    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
+    RTC->CSR &= ~it;
+//    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
+}
+
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c
new file mode 100644
index 000000000..4b1bd70ee
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c
@@ -0,0 +1,527 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_sdio.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE SDIO FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_SDIO_C_
+#include "reg_sdio.h"
+#include "hal_sdio.h"
+#include "hal_rcc.h"
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup SDIO_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup SDIO_Exported_Functions
+/// @{
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the SDIO peripheral registers to their default reset
+///         values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_DeInit(void)
+{
+    RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, ENABLE);
+    RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, DISABLE);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each SDIO_InitStruct member with its default value.
+/// @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
+///         will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+    // SDIO_InitStruct members default value
+    SDIO_InitStruct->SDIO_MDEN = 0;
+    SDIO_InitStruct->SDIO_DATWT = 0;
+    SDIO_InitStruct->SDIO_SelPTSM = 0;
+    SDIO_InitStruct->SDIO_CLKSP = 0;
+    SDIO_InitStruct->SDIO_OUTM = 0;
+    SDIO_InitStruct->SDIO_SelSM = 0;
+    SDIO_InitStruct->SDIO_OPMSel = 0;
+}
+
+
+///
+/// @brief  Fills each SDIO_DataInitStruct member with its default value.
+/// @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
+///         will be initialized.
+/// @retval None
+///
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+    /* SDIO_DataInitStruct members default value */
+    SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+    SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+    SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+    SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+//    SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
+//    SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+///
+/// @brief  Initializes the SDIO data path according to the specified
+///   parameters in the SDIO_DataInitStruct.
+/// @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
+///   contains the configuration information for the SDIO command.
+/// @retval None
+///
+//void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+//{
+//    u32 tmpreg = 0;
+
+//    /*---------------------------- SDIO DTIMER Configuration ---------------------*/
+//    /* Set the SDIO Data TimeOut value */
+//    SDIO->MMC_TIMEOUTCNT = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+//    /*---------------------------- SDIO DLEN Configuration -----------------------*/
+//    /* Set the SDIO DataLength value */
+//    SDIO->MMC_BYTECNTL = SDIO_DataInitStruct->SDIO_DataLength;
+
+//    /*---------------------------- SDIO DCTRL Configuration ----------------------*/
+//    /* Get the SDIO DCTRL value */
+//    tmpreg = SDIO->DCTRL;
+//    /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+//    tmpreg &= DCTRL_CLEAR_MASK;
+//    /* Set DEN bit according to SDIO_DPSM value */
+//    /* Set DTMODE bit according to SDIO_TransferMode value */
+//    /* Set DTDIR bit according to SDIO_TransferDir value */
+//    /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+//    tmpreg |= (u32)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir;//
+//              //| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+//    /* Write to SDIO DCTRL */
+//    SDIO->DCTRL = tmpreg;
+//}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  The frequency division factor is configured to generate the SDIO clock.
+/// @param  value : 1MHz = Fhclk/((mmc_cardsel[5 : 0] + 1) × 2)
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ClockSet(u32 value)
+{
+//    SDIO->MMC_CARDSEL &= ~SDIO_MMC_CARDSEL_MASK;
+    SDIO->MMC_CARDSEL = (SDIO_MMC_CARDSEL_CTREN | SDIO_MMC_CARDSEL_ENPCLK | (value & 0x3F));
+//    SDIO->MMC_CARDSEL = 0xC0+0x2F;//0xdf;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the SDIO peripheral according to the specified
+///         parameters in the SDIO_InitStruct.
+/// @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
+///         that contains the configuration information for the SDIO peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+    SDIO->MMC_CTRL &= 0x700;
+    SDIO->MMC_CTRL |= (SDIO_InitStruct->SDIO_OPMSel | SDIO_InitStruct->SDIO_SelSM |
+                       SDIO_InitStruct->SDIO_OUTM | SDIO_InitStruct->SDIO_CLKSP |
+                       SDIO_InitStruct->SDIO_SelPTSM | SDIO_InitStruct->SDIO_DATWT |
+                       SDIO_InitStruct->SDIO_MDEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the SDIO interrupts.
+/// @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
+///         state  : new state of the specified SDIO interrupts.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state)
+{
+    (state) ?  (SDIO->MMC_INT_MASK |= SDIO_IT) : (SDIO->MMC_INT_MASK &= ~SDIO_IT);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the SDIO CRC.
+/// @param  SDIO_CRC: specifies the SDIO CRC sources to be enabled or disabled.
+///         state   : new state of the specified SDIO CRC.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state)
+{
+    (state) ?  (SDIO->MMC_CRCCTL |= SDIO_CRC) : (SDIO->MMC_CRCCTL &= ~SDIO_CRC);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Port transfer speed mode.
+/// @param  clkdiv : High/low speed.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Clock_Set(u8 clkdiv)
+{
+    SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM;
+    (clkdiv) ? (SDIO->MMC_CTRL |= SDIO_MMC_CTRL_SelPTSM) : (SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Turn off the SDIO switch.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error SD_PowerOFF(void)
+{
+    SDIO->MMC_CARDSEL &= ~(SDIO_MMC_CARDSEL_ENPCLK | SDIO_MMC_CARDSEL_CTREN);
+    return SD_OK;
+}
+///
+/// @brief  Fills each SDIO_CmdInitStruct member with its default value.
+/// @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
+///         structure which will be initialized.
+/// @retval None
+///
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+    /* SDIO_CmdInitStruct members default value */
+    SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+    SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+    SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+    SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+//    SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SDIO sends command functions.
+/// @param  cmdindex : Type the command.
+///         waitrsp  : Expected correspondence.
+///         arg      : parameter.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg)
+{
+    SDIO->CMD_BUF0 = (arg >> 0) & 0xFF;
+    SDIO->CMD_BUF1 = (arg >> 8) & 0xFF;
+    SDIO->CMD_BUF2 = (arg >> 16) & 0xFF;
+    SDIO->CMD_BUF3 = (arg >> 24) & 0xFF;
+    SDIO->CMD_BUF4 = 0x40 | cmdindex;
+    SDIO->CLR_MMC_INT |= 0;
+    SDIO->MMC_IO = SDIO_MMC_IO_AUTOTR;
+    while(1) {
+        if(SDIO->CLR_MMC_INT & SDIO_CLR_MMC_INT_CMDDMC) {
+            SDIO->CLR_MMC_INT |= SDIO_CLR_MMC_INT_CMDDMC;
+            break;
+        }
+    }
+    if(waitrsp == SDIO_Response_Short) {
+        SDIO->MMC_IO =  SDIO_MMC_IO_AUTOCLKG | \
+                        SDIO_MMC_IO_AUTOTR | \
+                        SDIO_MMC_IO_RESPCMDSEL;
+    }
+    else if(waitrsp == SDIO_Response_Long) {
+        SDIO->MMC_IO =  SDIO_MMC_IO_AUTOCLKG | \
+                        SDIO_MMC_IO_AUTOTR | \
+                        SDIO_MMC_IO_RESPCMDSEL | \
+                        SDIO_MMC_IO_CID_CSDRD;
+    }
+    else {
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the execution status of CMD0.
+/// @param  None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdError(void)
+{
+    SD_Error errorstatus = SD_OK;
+    u32 timeout = SDIO_CMD0TIMEOUT;
+    while (timeout--) {
+        if(((SDIO->MMC_IO & SDIO_MMC_IO_RESPCMDSEL) == 0) && ((SDIO->MMC_IO & SDIO_MMC_IO_AUTOTR) == 0))
+            break;
+    }
+    if (timeout == 0)
+        return SD_CMD_RSP_TIMEOUT;
+    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+    return errorstatus;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the error status of the R1 response.
+/// @param  cmd : Current command.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp1Error(u8 cmd)
+{
+    u32 status;
+    u32 response;
+    while(1) {
+        status = SDIO->CLR_MMC_INT ;
+        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+            break;
+    }
+    if(status & SDIO_CLR_MMC_INT_CRNTMC) {
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+        return SD_CMD_RSP_TIMEOUT;
+    }
+    if(status & (SDIO_CLR_MMC_INT_CRCEMC)) {
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
+        return SD_CMD_CRC_FAIL;
+    }
+    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+
+    if((SDIO->CMD_BUF4 & 0x3F) != cmd) {
+        return SD_ILLEGAL_CMD;
+    }
+    response = SDIO->CMD_BUF3 << 24  | SDIO->CMD_BUF2 << 16  | SDIO->CMD_BUF1 << 8  | SDIO->CMD_BUF0;
+    return (SD_Error)(response & SD_OCR_ERRORBITS);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the execution status of CMD2.
+/// @param  None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp2Error(void)
+{
+    SD_Error errorstatus = SD_OK;
+    u32 status;
+    u32 timeout = SDIO_CMD0TIMEOUT;
+    while(timeout--) {
+        status = SDIO->CLR_MMC_INT ;
+        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+            break;
+    }
+    if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) {
+        errorstatus = SD_CMD_RSP_TIMEOUT;
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+        return errorstatus;
+    }
+    if(status & SDIO_CLR_MMC_INT_CRCEMC) {
+        errorstatus = SD_CMD_CRC_FAIL;
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
+    }
+    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+    return errorstatus;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the execution status of CMD3.
+/// @param  None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp3Error(void)
+{
+    u32 status;
+    while(1) {
+        status = SDIO->CLR_MMC_INT ;
+        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+            break;
+    }
+    if(status & SDIO_CLR_MMC_INT_CRNTMC) {
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+        return SD_CMD_RSP_TIMEOUT;
+    }
+    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+    return SD_OK;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the execution status of CMD6.
+/// @param  None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp6Error(u8 cmd, u16* prca)
+{
+    SD_Error errorstatus = SD_OK;
+    u32 status;
+    u32 rspr1;
+    while(1) {
+        status = SDIO->CLR_MMC_INT ;
+        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+            break;
+    }
+    if(status & SDIO_CLR_MMC_INT_CRNTMC) {
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+        return SD_CMD_RSP_TIMEOUT;
+    }
+    if(status & SDIO_CLR_MMC_INT_CRCEMC) {
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
+        return SD_CMD_CRC_FAIL;
+    }
+    if((SDIO->CMD_BUF4 & 0x3F) != cmd) {
+        return SD_ILLEGAL_CMD;
+    }
+    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
+    rspr1 = SDIO->CMD_BUF3 << 24  | SDIO->CMD_BUF2 << 16  | SDIO->CMD_BUF1 << 8  | SDIO->CMD_BUF0;
+    if(SD_ALLZERO == (rspr1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) {
+        *prca = (u16)(rspr1 >> 16);
+        return errorstatus;
+    }
+    if(rspr1 & SD_R6_GENERAL_UNKNOWN_ERROR) {
+        return SD_GENERAL_UNKNOWN_ERROR;
+    }
+    if(rspr1 & SD_R6_ILLEGAL_CMD) {
+        return SD_ILLEGAL_CMD;
+    }
+    if(rspr1 & SD_R6_COM_CRC_FAILED) {
+        return SD_COM_CRC_FAILED;
+    }
+    return errorstatus;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Check the execution status of CMD7.
+/// @param  None.
+/// @retval card error code.
+////////////////////////////////////////////////////////////////////////////////
+SD_Error CmdResp7Error(void)
+{
+    SD_Error errorstatus = SD_OK;
+    u32 status;
+    u32 timeout = SDIO_CMD0TIMEOUT;
+    while(timeout--) {
+        status = SDIO->CLR_MMC_INT ;
+        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
+            break;
+    }
+    if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) { //timeout
+        errorstatus = SD_CMD_RSP_TIMEOUT;
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
+        return errorstatus;
+    }
+    if(status & SDIO_CLR_MMC_INT_CMDDMC) {
+        errorstatus = SD_OK;
+        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CMDDMC;
+    }
+    return errorstatus;
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Write data direction block size configuration.
+/// @param  datatimeout : maximum latency.
+///         datalen     : data len
+///         blksize     : block count.
+///         dir         :  direction
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir)
+{
+    u32 tmpreg, tmpreg1, tmpreg2 = 0;
+    tmpreg = SDIO->MMC_IO_MBCTL;
+    tmpreg1 = SDIO->MMC_IO;
+    tmpreg &= ~(SDIO_MMC_IO_MBCTL_BTSSel | SDIO_MMC_IO_MBCTL_SPMBDTR | SDIO_MMC_IO_MBCTL_SMBDTD);
+    if (datatimeout < 100) {
+        SDIO->MMC_TIMEOUTCNT = datatimeout;
+    }
+    else if (datatimeout < 10000) {
+        SDIO->MMC_TIMEOUTCNT = datatimeout / 100;
+        tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel;
+    }
+    else if (datatimeout < 1000000) {
+        SDIO->MMC_TIMEOUTCNT = datatimeout / 10000;
+        tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel_2;
+    }
+    else {
+        SDIO->MMC_TIMEOUTCNT = datatimeout / 1000000;
+        tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel;
+    }
+    SDIO->MMC_BYTECNTL = datalen & 0x1FFFFFF; ;
+    SDIO->MMC_BLOCKCNT = blksize;
+    if (dir == 0) {
+        tmpreg |= SDIO_MMC_IO_MBCTL_SMBDTD;
+        tmpreg1 |= SDIO_MMC_IO_TRANSFDIR;
+        tmpreg2 |= SDIO_BUF_CTLL_SBAD;
+    }
+    else {
+        tmpreg &= ~(SDIO_MMC_IO_MBCTL_SMBDTD);
+        tmpreg1 &= ~(SDIO_MMC_IO_TRANSFDIR);
+        tmpreg2 &= ~(SDIO_BUF_CTLL_SBAD);
+    }
+    SDIO->MMC_IO_MBCTL = tmpreg;
+    SDIO->MMC_IO = tmpreg1;
+    SDIO->BUF_CTL = tmpreg2;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the SDIO's Flag pending bits.
+/// @param  SDIO_IT: specifies the flag pending bit to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ClearFlag(u32 SDIO_FLAG)
+{
+    SDIO->CLR_MMC_INT |= SDIO_FLAG;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the SDIO's interrupt pending bits.
+/// @param  SDIO_IT: specifies the interrupt pending bit to clear.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_ClearITPendingBit(u32 SDIO_IT)
+{
+    SDIO->CLR_MMC_INT |= SDIO_IT;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified SDIO flag is set or not.
+/// @param  SDIO_FLAG: specifies the flag to check.
+/// @retval The new state of SDIO_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG)
+{
+    return ((SDIO->CLR_MMC_INT & SDIO_FLAG) ? SET : RESET);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Reads the value of the data transfer timeout count
+/// @param  None.
+/// @retval timeout count.
+////////////////////////////////////////////////////////////////////////////////
+u32 SDIO_GetTimeOutCounter(void)
+{
+    return (SDIO->MMC_TIMEOUTCNT & 0xFF);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Read one data word from FIFO.
+/// @param  None.
+/// @retval Data received.
+////////////////////////////////////////////////////////////////////////////////
+u32 SDIO_ReadData(void)
+{
+    return SDIO->FIFO;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Write one data word to FIFO.
+/// @param  tempbuff : Write data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_WriteData(u32 tempbuff)
+{
+    SDIO->FIFO = tempbuff;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns number of remaining data bytes to be transferred.
+/// @param  None
+/// @retval Number of remaining data bytes to be transferred
+////////////////////////////////////////////////////////////////////////////////
+u32 SDIO_GetDataCounter(void)
+{
+    return SDIO->MMC_BYTECNTL;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable or Dsiable DMA .
+/// @param  tempbuff : Write data.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SDIO_DMACmd(FunctionalState state)
+{
+    (state) ?  ((SDIO->BUF_CTL |= SDIO_BUF_CTLL_DMAHEN), SDIO->BUF_CTL &= (~(SDIO_BUF_CTLL_DRM))) : (SDIO->BUF_CTL &= ~SDIO_BUF_CTLL_DMAHEN);
+}
+
+
+/// @}
+
+/// @}
+
+/// @}
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c
new file mode 100644
index 000000000..3d8c286a3
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c
@@ -0,0 +1,648 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_spi.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE SPI FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_SPI_C_
+#include <math.h>
+// Files includes
+#include "hal_spi.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup SPI_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup SPI_Exported_Functions
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the spi peripheral registers to their
+///         default reset values.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_DeInit(SPI_TypeDef* spi)
+{
+    switch (*(vu32*)&spi) {
+        case (u32)SPI2:  // SPI2_BASE:
+            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, DISABLE);
+            break;
+        case (u32)SPI3:  // SPI3_BASE:
+            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, DISABLE);
+            break;
+        case (u32)SPI1:  // SPI1_BASE:
+            RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, ENABLE);
+            RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, DISABLE);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the spi peripheral according to the specified
+///         parameters in the init_struct .
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  init_struct: pointer to a SPI_InitTypeDef structure
+///         that contains the configuration information for the
+///         specified SPI peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct)
+{
+    if (init_struct->SPI_DataSize == SPI_DataSize_32b) {
+        SET_BIT(spi->GCR, SPI_GCR_DWSEL);
+    }
+    else {
+        CLEAR_BIT(spi->GCR, SPI_GCR_DWSEL);
+    }
+    MODIFY_REG(spi->GCR, SPI_GCR_NSS, init_struct->SPI_NSS);
+    MODIFY_REG(spi->GCR, SPI_GCR_MODE, init_struct->SPI_Mode);
+    MODIFY_REG(spi->CCR, SPI_CCR_LSBFE, init_struct->SPI_FirstBit);
+    MODIFY_REG(spi->CCR, SPI_CCR_CPOL, init_struct->SPI_CPOL);
+    MODIFY_REG(spi->CCR, SPI_CCR_CPHA, init_struct->SPI_CPHA);
+
+    SET_BIT(spi->CCR, SPI_CCR_SPILEN);
+
+    MODIFY_REG(spi->BRR, BRR_Mask, init_struct->SPI_BaudRatePrescaler);
+
+    if (init_struct->SPI_DataWidth >= 32) {
+        MODIFY_REG(spi->ECR, ECR_Mask, 0);
+    }
+    else {
+        MODIFY_REG(spi->ECR, ECR_Mask, init_struct->SPI_DataWidth);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct: pointer to a SPI_InitTypeDef structure
+///         which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_StructInit(SPI_InitTypeDef* init_struct)
+{
+    init_struct->SPI_Mode              = SPI_Mode_Slave;
+    init_struct->SPI_DataSize          = SPI_DataSize_8b;
+    init_struct->SPI_DataWidth         = 8;
+    init_struct->SPI_CPOL              = SPI_CPOL_Low;
+    init_struct->SPI_CPHA              = SPI_CPHA_1Edge;
+    init_struct->SPI_NSS               = SPI_NSS_Soft;
+    init_struct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+    init_struct->SPI_FirstBit          = SPI_FirstBit_MSB;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified SPI peripheral.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of the spi peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->GCR, SPI_GCR_SPIEN) : CLEAR_BIT(spi->GCR, SPI_GCR_SPIEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified SPI interrupts.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:SPI1, SPI2.
+/// @param  interrupt: specifies the SPI interrupt sources to be
+///         enabled or disabled.
+///         This parameter can be one of the following values:
+/// @arg    SPI_IT_TXEPT: Transmitter empty interrupt
+/// @arg    SPI_IT_RXFULL: RX FIFO full interrupt
+/// @arg    SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt
+/// @arg    SPI_IT_RXOERR: Receive overrun error interrupt
+/// @arg    SPI_IT_UNDERRUN: underrun interrupt
+/// @arg    SPI_IT_RX: Receive data available interrupt
+/// @arg    SPI_IT_TX: Transmit FIFO available interrupt
+/// @param  state: new state of the specified spi interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state)
+{
+    if (state) {
+        SET_BIT(spi->GCR, (u32)SPI_GCR_IEN);
+        SET_BIT(spi->IER, (u32)interrupt);
+    }
+    else {
+        CLEAR_BIT(spi->IER, interrupt);
+        CLEAR_BIT(spi->GCR, SPI_GCR_IEN);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the SPI DMA interface.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of the DMA Request sources.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  configure tn Fifo trigger level bit.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  fifo_trigger_value: specifies the Fifo trigger level
+///         This parameter can be any combination of the following values:
+///         SPI_TXTLF : SPI TX FIFO Trigger value set
+///         SPI_RXTLF : SPI RX FIFO Trigger value set
+/// @param  state: new state of the selected SPI transfer request.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->GCR, (u32)fifo_trigger_value) : CLEAR_BIT(spi->GCR, (u32)fifo_trigger_value);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Transmits a Data through the spi peripheral.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  data : Data to be transmitted.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_SendData(SPI_TypeDef* spi, u32 data)
+{
+    u16 templen;
+    __asm volatile("cpsid i");
+
+    WRITE_REG(spi->TDR, data);
+
+    templen = READ_REG(spi->ECR);
+    if(templen  == 0)
+        templen = 32;
+    if (templen > 8)
+        WRITE_REG(spi->TDR, data >> 8);
+    if (templen > 16)
+        WRITE_REG(spi->TDR, data >> 16);
+    if (templen > 24)
+        WRITE_REG(spi->TDR, data >> 24);
+    __asm volatile("cpsie i");
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the most recent received data by the spi peripheral.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @retval The value of the received data.
+////////////////////////////////////////////////////////////////////////////////
+u32 SPI_ReceiveData(SPI_TypeDef* spi)
+{
+    u32 temp;
+    u8 templen;
+    __asm volatile("cpsid i");
+
+    temp = READ_REG(spi->RDR);
+
+    templen = READ_REG(spi->ECR);
+    if(templen  == 0)
+        templen = 32;
+    if (templen > 8)
+        temp |= (u32)(READ_REG(spi->RDR) << 8);
+    if (templen > 16)
+        temp |= (u32)(READ_REG(spi->RDR) << 16);
+    if (templen > 24)
+        temp |= (u32)(READ_REG(spi->RDR) << 24);
+
+    __asm volatile("cpsie i");
+
+    return temp;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Slave chip csn single by selected
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of the selected SPI CS pin
+///         request.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS);  // illogical
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the NSS pin control mode for the selected SPI.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  nss: specifies the SPI NSS internal state.
+///         This parameter can be one of the following values:
+/// @arg    SPI_NSS_Soft: NSS pin control by software
+/// @arg    SPI_NSS_Hard: NSS pin control by hardware
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss)
+{
+    (nss != SPI_NSS_Soft) ? SET_BIT(spi->GCR, SPI_NSS_Hard) : CLEAR_BIT(spi->GCR, SPI_NSS_Hard);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the data size for the selected SPI.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  data_size: specifies the SPI data size.
+///         This parameter can be one of the following values:
+///         0 to 31, 0 = 32b, 1 = 1b, 2 = 2b
+/// @arg    DataSize : 0 to 31
+/// @retval None.
+/// @retval None.
+bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size)
+{
+    if (data_size > 32)
+        return false;
+    data_size &= 0x1F;
+    WRITE_REG(spi->ECR, data_size);
+    return true;
+}
+
+//////////////////////////////////////////////////////////////////////////////////
+void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize)
+{
+    CLEAR_BIT(spi->GCR, (u32)SPI_DataSize_32b);
+    SET_BIT(spi->GCR, (u32)SPI_DataSize);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the data transfer direction in bi-directional mode
+///         for the specified SPI.
+/// @param spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param direction: specifies the data transfer direction in
+///         bi-directional mode.
+///         This parameter can be one of the following values:
+/// @arg    SPI_Direction_Tx: Selects Tx transmission direction
+/// @arg    SPI_Direction_Rx: Selects Rx receive direction
+/// @arg    SPI_Disable_Tx: Selects Rx receive direction
+/// @arg    SPI_Disable_Rx: Selects Rx receive direction
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction)
+{
+    switch (direction) {
+        case SPI_Direction_Rx:
+            SET_BIT(spi->GCR, SPI_GCR_RXEN);
+            break;
+        case SPI_Direction_Tx:
+            SET_BIT(spi->GCR, SPI_GCR_TXEN);
+            break;
+        case SPI_Disable_Rx:
+            CLEAR_BIT(spi->GCR, SPI_GCR_RXEN);
+            break;
+        case SPI_Disable_Tx:
+            CLEAR_BIT(spi->GCR, SPI_GCR_TXEN);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified SPI flag is set or not.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  flag: specifies the SPI flag to check.
+///         This parameter can be one of the following values:
+/// @arg    SPI_FLAG_RXAVL: Rx buffer has bytes flag
+/// @arg    SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag
+/// @arg    SPI_FLAG_TXFULL: Tx buffer full flag
+/// @arg    SPI_FLAG_RXAVL_4BYTE: Receive available 4 byte data message flag.
+/// @retval The new state of SPI_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag)
+{
+//    u8 number;
+    return (spi->SR & flag) ? SET : RESET;
+//  if (spi->ECR == 8 || spi->ECR == 0)
+//      return (spi->SR & SPI_FLAG) ? SET : RESET;
+//  else {
+//      if ((spi->ECR > 0) && (spi->ECR <= 8))
+//          number = 1;
+//      else if ((spi->ECR) <= 16)
+//          number = 2;
+//      else if ((spi->ECR) <= 24)
+//          number = 3;
+//      else if (((spi->ECR) <= 31) || (spi->ECR == 0))
+//          number = 4;
+//      return (((spi->SR & 0xf00) >> 8) >= number) ? SET : RESET;
+//  }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified SPI interrupt has occurred or not.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  interrupt: specifies the SPI interrupt source to check.
+///         This parameter can be one of the following values:
+/// @arg    SPI_IT_TX: Tx buffer empty interrupt
+/// @arg    SPI_IT_RX: Rx buffer  interrupt
+/// @arg    SPI_IT_UNDERRUN: under Error interrupt in slave mode
+/// @arg    SPI_IT_RXOVER: RX OVER Error interrupt
+/// @arg    SPI_IT_RXMATCH: spectials rx data numbers  interrupt
+/// @arg    SPI_IT_RXFULL: Rx buffer full interrupt
+/// @arg    SPI_IT_TXEPT: Tx buffer  and tx shifter empty interrupt
+/// @retval The new state of SPI_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt)
+{
+    return (spi->ISR & interrupt) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the spi  interrupt pending bit.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  interrupt: specifies the SPI interrupt pending bit to clear.
+/// @arg    SPI_IT_TX: Tx buffer empty interrupt
+/// @arg    SPI_IT_RX: Rx buffer  interrupt
+/// @arg    SPI_IT_UNDERRUN: under Error interrupt in slave mode
+/// @arg    SPI_IT_RXOVER: RX OVER Error interrupt
+/// @arg    SPI_IT_RXMATCH: spectials rx data numbers  interrupt
+/// @arg    SPI_IT_RXFULL: Rx buffer full interrupt
+/// @arg    SPI_IT_TXEPT: Tx buffer  and tx shifter empty interrupt
+///         This function clears only ERR intetrrupt pending bit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt)
+{
+    SET_BIT(spi->ICR, interrupt);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  SPI Hole a count Received bytes in next receive process.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  number: specifies the SPI receive Number.
+///         This parament can be 1-65535.
+///         This function can use only in SPI master single receive mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_RxBytes(SPI_TypeDef* spi, u16 number)
+{
+    WRITE_REG(spi->RDNR, number);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  slave mode tx data transmit phase adjust set.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  adjust_value: slave mode tx data transmit phase adjust enum.
+///         This parament can be :
+///         SPI_SlaveAdjust_FAST:  fast speed use
+///         SPI_SlaveAdjust_LOW:   low speed use
+///         This function can use only in SPI master single receive mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value)
+{
+    (adjust_value) ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables all SPI interrupts.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of all spi interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->IER, (u32)SPI_GCR_IEN) : CLEAR_BIT(spi->IER, (u32)SPI_GCR_IEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified SPI interrupts.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  interrupt: specifies the SPI interrupt sources to be enabled or disabled.
+///         This parameter can be one of the following values:
+/// @arg    SPI_IT_TXEPT: Transmitter empty interrupt
+/// @arg    SPI_IT_RXFULL: RX FIFO full interrupt
+/// @arg    SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt
+/// @arg    SPI_IT_RXOERR: Receive overrun error interrupt
+/// @arg    SPI_IT_UNDERRUN: underrun interrupt
+/// @arg    SPI_IT_RX: Receive data available interrupt
+/// @arg    SPI_IT_TX: Transmit FIFO available interrupt
+/// @param  state: new state of the specified spi interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->IER, (u32)interrupt) : CLEAR_BIT(spi->IER, (u32)interrupt);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the SPI DMA request.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of the DMA Request.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set or reset Slave chip csn signal output
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  state: new state of Slave chip csn signal output.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS);  // illogical
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  tx data and rx data phase adjust.
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2.
+/// @param  adjust_value: choose adjust mode.
+///         This parament can be :
+///         SPI_DataEdgeAdjust_LOW,
+///         SPI_DataEdgeAdjust_FAST
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value)
+{
+    // master mode
+    if (spi->GCR & SPI_GCR_MODE) {
+        adjust_value ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE);
+    }
+    // slave mode
+    else {
+        adjust_value ? SET_BIT(spi->CCR, SPI_CCR_TXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_TXEDGE);
+    }
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set or reset i2s
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2, SPI3.
+/// @param  state: new state of Slave chip csn signal output.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state)
+{
+    (state) ? SET_BIT(spi->CFGR, I2S_CFGR_SPI_I2S) : CLEAR_BIT(spi->CFGR, I2S_CFGR_SPI_I2S);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  i2s Config
+/// @param  spi: Select the SPI peripheral.
+///         This parameter can be one of the following values:
+///         SPI1, SPI2, SPI3.
+/// @param  state: new state of Slave chip csn signal output.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct)
+{
+    u32 i2sdiv = 2;
+    u32 tmpreg = 0;
+    u32 packetlength = 1;
+    u32 result = 0, yushu = 0;
+    u32 sourceclock = 0;
+    RCC_ClocksTypeDef RCC_Clocks;
+
+    if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) {
+        i2sdiv = 2;
+    }
+    else {
+        if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) {
+            packetlength = 1;
+        }
+        else {
+            packetlength = 2;
+        }
+        RCC_GetClocksFreq(&RCC_Clocks);
+
+        if((SPI2 == spi) || (SPI3 == spi))  {
+            sourceclock = RCC_Clocks.PCLK1_Frequency;
+        }
+        else {
+            sourceclock = RCC_Clocks.PCLK2_Frequency;
+        }
+        if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) {
+            result = (sourceclock) / (256 * (I2S_InitStruct->I2S_AudioFreq));
+            yushu = (sourceclock) % (256 * (I2S_InitStruct->I2S_AudioFreq));
+            if(yushu > (128 * (I2S_InitStruct->I2S_AudioFreq))) {
+                result = result + 1;
+            }
+            i2sdiv = result;
+            if ((i2sdiv < 2) || (i2sdiv > 0x1FF)) {
+                i2sdiv = 2;
+            }
+        }
+        else {
+            result = (sourceclock) / (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq));
+            yushu = (sourceclock) % (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq));
+            if(yushu > ((16 * packetlength * (I2S_InitStruct->I2S_AudioFreq)))) {
+                result = result + 1;
+            }
+            if ((i2sdiv < 1) || (i2sdiv > 0x1FF)) {
+                i2sdiv = 1;
+            }
+        }
+    }
+    if(I2S_CPOL_High  == I2S_InitStruct->I2S_CPOL) {
+        spi->CCTL |= SPI_CCR_CPOL;
+    }
+    else {
+        spi->CCTL &= ~SPI_CCR_CPOL;
+    }
+
+    spi->CFGR = 0x2 << I2S_CFGR_I2SDIV_Pos;
+
+    if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx)) {
+        spi->GCTL |= SPI_GCR_MODE;
+    }
+    else {
+        spi->GCTL &= ~SPI_GCR_MODE;
+    }
+    if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) {
+        spi->GCTL |= SPI_GCR_TXEN;
+        spi->GCTL &= ~SPI_GCR_RXEN;
+    }
+    else {
+        spi->GCTL &= ~SPI_GCR_TXEN;
+        spi->GCTL |= SPI_GCR_RXEN;
+    }
+//    tmpreg = spi->GCTL;
+//    tmpreg &= ~(1 << 2);
+//    tmpreg |= (u16)(I2S_InitStruct->I2S_Mode);
+//    spi->GCTL = tmpreg;
+//
+    tmpreg = 0;
+    tmpreg |= (i2sdiv << I2S_CFGR_I2SDIV_Pos) | \
+              (I2S_InitStruct->I2S_MCLKOutput) | \
+              (I2S_CFGR_SPI_I2S) | \
+              (I2S_InitStruct->I2S_Standard) | \
+              (I2S_InitStruct->I2S_DataFormat);
+    spi->CFGR &= ~I2S_CFGR_I2SDIV;
+    spi->CFGR |= tmpreg;
+
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c
new file mode 100644
index 000000000..e798bc46a
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c
@@ -0,0 +1,1875 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_tim.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE TIM FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_TIM_C_
+
+// Files includes
+#include "hal_rcc.h"
+#include "hal_tim.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup TIM_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup TIM_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the tim peripheral registers to their default reset values.
+/// @param  tim:  select the TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_DeInit(TIM_TypeDef* tim)
+{
+    switch (*(vu32*)&tim) {
+        case (u32)TIM1:
+            exRCC_APB2PeriphReset(RCC_APB2ENR_TIM1);
+            break;
+        case (u32)TIM2:
+            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM2);
+            break;
+        case (u32)TIM3:
+            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM3);
+            break;
+        case (u32)TIM4:
+            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM4);
+            break;
+
+        case (u32)TIM5:
+            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM5);
+            break;
+        case (u32)TIM6:
+            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM6);
+            break;
+        case (u32)TIM7:
+            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM7);
+            break;
+
+        case (u32)TIM8:
+            exRCC_APB2PeriphReset(RCC_APB2ENR_TIM8);
+            break;
+
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the tim Time Base Unit peripheral according to
+///         the specified parameters in the init_struct.
+/// @param  tim: select the TIM peripheral.
+/// @param  init_struct: pointer to a TIM_TimeBaseInitTypeDef
+///         structure that contains the configuration information for the
+///         specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct)
+{
+    MODIFY_REG(tim->CR1, TIM_CR1_CKD, init_struct->TIM_ClockDivision);
+
+    if ((tim == TIM1) || (tim == TIM2) || (tim == TIM3) || (tim == TIM4) || (tim == TIM5) || (tim == TIM8))
+        MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, init_struct->TIM_CounterMode);
+
+    if ((tim == TIM1) || (tim == TIM8) )
+
+        MODIFY_REG(tim->RCR, TIM_RCR_REP, init_struct->TIM_RepetitionCounter);
+
+    WRITE_REG(tim->ARR, init_struct->TIM_Period);
+    WRITE_REG(tim->PSC, init_struct->TIM_Prescaler);
+    WRITE_REG(tim->EGR, TIM_PSCReloadMode_Immediate);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the tim Channel1 according to the specified
+///         parameters in the init_struct.
+/// @param  tim:  select the TIM peripheral.
+/// @param  init_struct: pointer to a TIM_OCInitTypeDef structure that
+///         contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, init_struct->TIM_OCMode);
+    MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC1EN, \
+               ((u32)init_struct->TIM_OCPolarity) | ((u32)init_struct->TIM_OutputState));
+    WRITE_REG(tim->CCR1, init_struct->TIM_Pulse);
+
+    if ((tim == TIM1) || (tim == TIM8)) {
+        MODIFY_REG(tim->CCER, TIM_CCER_CC1NP | TIM_CCER_CC1NEN, \
+                   ((u32)init_struct->TIM_OCNPolarity) | ((u32)init_struct->TIM_OutputNState));
+        MODIFY_REG(tim->CR2, TIM_CR2_OIS1 | TIM_CR2_OIS1N, \
+                   ((u32)init_struct->TIM_OCIdleState) | ((u32)init_struct->TIM_OCNIdleState));
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the tim Channel2 according to the specified
+///         parameters in the init_struct.
+/// @param  tim: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+/// @param  init_struct: pointer to a TIM_OCInitTypeDef structure that
+///         contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, init_struct->TIM_OCMode << 8);
+    MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, \
+               (init_struct->TIM_OCPolarity << 4) | (init_struct->TIM_OutputState << 4));
+    WRITE_REG(tim->CCR2, init_struct->TIM_Pulse);
+
+    if ((tim == TIM1) || (tim == TIM8)) {
+        MODIFY_REG(tim->CCER, TIM_CCER_CC2NP | TIM_CCER_CC2NEN, \
+                   (init_struct->TIM_OCNPolarity << 4) | (init_struct->TIM_OutputNState << 4));
+        MODIFY_REG(tim->CR2, TIM_CR2_OIS2 | TIM_CR2_OIS2N, \
+                   (init_struct->TIM_OCIdleState << 2) | (init_struct->TIM_OCNIdleState << 2));
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the tim Channel3 according to the specified
+///         parameters in the init_struct.
+/// @param  tim: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+/// @param  init_struct: pointer to a TIM_OCInitTypeDef structure that
+///         contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, init_struct->TIM_OCMode);
+    MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, \
+               (init_struct->TIM_OCPolarity << 8) | (init_struct->TIM_OutputState << 8));
+    WRITE_REG(tim->CCR3, init_struct->TIM_Pulse);
+
+    if ((tim == TIM1) || (tim == TIM8)) {
+        MODIFY_REG(tim->CCER, TIM_CCER_CC3NP | TIM_CCER_CC3NEN, \
+                   (init_struct->TIM_OCNPolarity << 8) | (init_struct->TIM_OutputNState << 8));
+        MODIFY_REG(tim->CR2, TIM_CR2_OIS3 | TIM_CR2_OIS3N, \
+                   (init_struct->TIM_OCIdleState << 4) | (init_struct->TIM_OCNIdleState << 4));
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the tim Channel4 according to the specified
+///         parameters in the init_struct.
+/// @param  tim:select the TIM peripheral.
+/// @param  init_struct: pointer to a TIM_OCInitTypeDef structure that
+///         contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, (init_struct->TIM_OCMode) << 8);
+    MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, \
+               (init_struct->TIM_OCPolarity << 12) | (init_struct->TIM_OutputState << 12));
+    WRITE_REG(tim->CCR4, init_struct->TIM_Pulse);
+
+    if ((tim == TIM1) || (tim == TIM8))
+        MODIFY_REG(tim->CR2, TIM_CR2_OIS4, init_struct->TIM_OCIdleState << 6);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the TIM peripheral according to the specified
+///         parameters in the init_struct.
+/// @param  tim:  select the TIM peripheral.
+/// @param  init_struct: pointer to a TIM_ICInitTypeDef structure that
+///         contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct)
+{
+    switch (init_struct->TIM_Channel) {
+        case TIM_Channel_1:
+            TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+            TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
+            break;
+        case TIM_Channel_2:
+            TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+            TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
+            break;
+        case TIM_Channel_3:
+            TI3_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+            TIM_SetIC3Prescaler(tim, init_struct->TIM_ICPrescaler);
+            break;
+        case TIM_Channel_4:
+            TI4_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+            TIM_SetIC4Prescaler(tim, init_struct->TIM_ICPrescaler);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the TIM peripheral according to the specified
+///         parameters in the init_struct to measure an external PWM signal.
+/// @param  tim: select the TIM peripheral.
+/// @param  init_struct: pointer to a TIM_ICInitTypeDef structure that
+///         contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct)
+{
+    u16 icoppositepolarity  = TIM_ICPolarity_Rising;
+    u16 icoppositeselection = TIM_ICSelection_DirectTI;
+    icoppositepolarity = (init_struct->TIM_ICPolarity == TIM_ICPolarity_Rising) ? TIM_ICPolarity_Falling : TIM_ICPolarity_Rising;
+    icoppositeselection =
+        (init_struct->TIM_ICSelection == TIM_ICSelection_DirectTI) ? TIM_ICSelection_IndirectTI : TIM_ICSelection_DirectTI;
+    if (init_struct->TIM_Channel == TIM_Channel_1) {
+        TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
+        TI2_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
+    }
+    else {
+        TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
+        TI1_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
+///         the OSSR State and the AOE(automatic output enable).
+/// @param  tim: select the TIM
+/// @param  init_struct: pointer to a TIM_BDTRInitTypeDef structure that
+///         contains the BDTR Register configuration  information for the TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct)
+{
+    tim->BDTR = (u32)init_struct->TIM_OSSRState | init_struct->TIM_OSSIState | init_struct->TIM_LOCKLevel |
+                init_struct->TIM_DeadTime | init_struct->TIM_Break | init_struct->TIM_BreakPolarity |
+                init_struct->TIM_AutomaticOutput;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct : pointer to a TIM_TimeBaseInitTypeDef
+///         structure which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct)
+{
+    init_struct->TIM_Period            = 0xFFFFFFFF;
+    init_struct->TIM_Prescaler         = 0x0000;
+    init_struct->TIM_ClockDivision     = TIM_CKD_DIV1;
+    init_struct->TIM_CounterMode       = TIM_CounterMode_Up;
+    init_struct->TIM_RepetitionCounter = 0x00;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct : pointer to a TIM_OCInitTypeDef structure which will
+///         be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct)
+{
+    init_struct->TIM_OCMode       = TIM_OCMode_Timing;
+    init_struct->TIM_OutputState  = TIM_OutputState_Disable;
+    init_struct->TIM_OutputNState = TIM_OutputNState_Disable;
+    init_struct->TIM_Pulse        = 0x00000000;
+    init_struct->TIM_OCPolarity   = TIM_OCPolarity_High;
+    init_struct->TIM_OCNPolarity  = TIM_OCNPolarity_High;
+    init_struct->TIM_OCIdleState  = TIM_OCIdleState_Reset;
+    init_struct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct: pointer to a TIM_ICInitTypeDef structure which will
+///         be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct)
+{
+    init_struct->TIM_Channel     = TIM_Channel_1;
+    init_struct->TIM_ICPolarity  = TIM_ICPolarity_Rising;
+    init_struct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+    init_struct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+    init_struct->TIM_ICFilter    = 0x00;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each init_struct member with its default value.
+/// @param  init_struct: pointer to a TIM_BDTRInitTypeDef structure which
+///         will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct)
+{
+    init_struct->TIM_OSSRState       = TIM_OSSRState_Disable;
+    init_struct->TIM_OSSIState       = TIM_OSSIState_Disable;
+    init_struct->TIM_LOCKLevel       = TIM_LOCKLevel_OFF;
+    init_struct->TIM_DeadTime        = 0x00;
+    init_struct->TIM_Break           = TIM_Break_Disable;
+    init_struct->TIM_BreakPolarity   = TIM_BreakPolarity_Low;
+    init_struct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified TIM peripheral.
+/// @param  tim: where x can be 1 to 17 to select the tim peripheral.
+/// @param  state: new state of the tim peripheral.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state)
+{
+    (state) ? SET_BIT(tim->CR1, TIM_CR1_CEN) : CLEAR_BIT(tim->CR1, TIM_CR1_CEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the TIM peripheral Main Outputs.
+/// @param  tim: where x can be 1, 8, 16 or 17 to select the tim peripheral.
+/// @param  state: new state of the TIM peripheral Main Outputs.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state)
+{
+    (state) ? SET_BIT(tim->BDTR, TIM_BDTR_MOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_MOEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified TIM interrupts.
+/// @param  tim:  select the tim peripheral.
+/// @param  it: specifies the TIM interrupts sources to be enabled or disabled.
+///   This parameter can be any combination of the following values:
+///     @arg TIM_IT_Update: TIM update Interrupt source
+///     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+///     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+///     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+///     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+///     @arg TIM_IT_COM: TIM Commutation Interrupt source
+///     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+///     @arg TIM_IT_Break: TIM Break Interrupt source
+/// @note
+///   - Partial timer can have TIM_IT_Update or TIM_IT_CC1.
+///   - TIM_IT_Break is used only with partial timer.
+///   - TIM_IT_COM is used only with partial timer.
+/// @param  state: new state of the TIM interrupts.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state)    //TIMIT_TypeDef
+{
+    (state) ? SET_BIT(tim->DIER, it) : CLEAR_BIT(tim->DIER, it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim event to be generate by software.
+/// @param  tim:  select the TIM peripheral.
+/// @param  source: specifies the event source.
+///   This parameter can be one or more of the following values:
+///     @arg TIM_EventSource_Update: Timer update Event source
+///     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+///     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+///     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+///     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+///     @arg TIM_EventSource_COM: Timer COM event source
+///     @arg TIM_EventSource_Trigger: Timer Trigger Event source
+///     @arg TIM_EventSource_Break: Timer Break event source
+/// @note
+///   - TIM_EventSource_COM and TIM_EventSource_Break are used only with partial timer.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source)
+{
+    WRITE_REG(tim->EGR, source);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim's DMA interface.
+/// @param  tim: select the TIM peripheral.
+/// @param  dma_base: DMA Base address.
+///   This parameter can be one of the following values:
+///     @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+///          TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
+///          TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+///          TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+///          TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
+///          TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
+///          TIM_DMABase_DCR.
+/// @param  length: DMA Burst length.
+///   This parameter can be one value between:
+///   TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length)
+{
+    WRITE_REG(tim->DCR, ((u32)dma_base) | ((u32)length));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the tim's DMA Requests.
+/// @param  tim: select the TIM peripheral.
+/// @param  source: specifies the DMA Request sources.
+///   This parameter can be any combination of the following values:
+///     @arg TIM_DMA_Update: TIM update Interrupt source
+///     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+///     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+///     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+///     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+///     @arg TIM_DMA_COM: TIM Commutation DMA source
+///     @arg TIM_DMA_Trigger: TIM Trigger DMA source
+/// @param  state: new state of the DMA Request sources.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state)
+{
+    (state) ? SET_BIT(tim->DIER, source) : CLEAR_BIT(tim->DIER, source);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim internal Clock
+/// @param  tim: select the TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_InternalClockConfig(TIM_TypeDef* tim)
+{
+    CLEAR_BIT(tim->SMCR, TIM_SMCR_SMS);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Internal Trigger as External Clock
+/// @param  tim: select the TIM peripheral.
+/// @param  source: Trigger source.
+///   This parameter can be one of the following values:
+///    @arg TIM_TS_ITR0: Internal Trigger 0
+///    @arg TIM_TS_ITR1: Internal Trigger 1
+///    @arg TIM_TS_ITR2: Internal Trigger 2
+///    @arg TIM_TS_ITR3: Internal Trigger 3
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source)
+{
+    TIM_SelectInputTrigger(tim, source);
+    SET_BIT(tim->SMCR, TIM_SlaveMode_External1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Trigger as External Clock
+/// @param  tim: select the TIM peripheral.
+/// @param  source: Trigger source.
+///   This parameter can be one of the following values:
+///     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+///     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+///     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+/// @param  polarity: specifies the TIx Polarity.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Rising
+///     @arg TIM_ICPolarity_Falling
+/// @param  filter : specifies the filter value.
+///   This parameter must be a value between 0x0 and 0xF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter)
+{
+    (source == TIM_TIxExternalCLK1Source_TI2) ? (TI2_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter))
+    : (TI1_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter));
+    TIM_SelectInputTrigger(tim, (TIMTS_TypeDef)source);
+    SET_BIT(tim->SMCR, TIM_SlaveMode_External1);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim External Trigger (ETR).
+/// @param  tim: select the TIM peripheral.
+/// @param  psc: The external Trigger Prescaler.
+///   This parameter can be one of the following values:
+///     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+///     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+///     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+///     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+/// @param  polarity: The external Trigger Polarity.
+///   This parameter can be one of the following values:
+///     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+///     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+/// @param  filter: External Trigger Filter.
+///   This parameter must be a value between 0x00 and 0x0F
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
+{
+    CLEAR_BIT(tim->SMCR, TIM_SMCR_ECEN);
+    MODIFY_REG(tim->SMCR, TIM_SMCR_ETP, polarity);
+    MODIFY_REG(tim->SMCR, TIM_SMCR_ETPS, psc);
+    MODIFY_REG(tim->SMCR, TIM_SMCR_ETF, filter << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the External clock Mode1
+/// @param  tim: select the TIM peripheral.
+/// @param  psc: The external Trigger Prescaler.
+///   This parameter can be one of the following values:
+///     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+///     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+///     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+///     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+/// @param  polarity: The external Trigger Polarity.
+///   This parameter can be one of the following values:
+///     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+///     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+/// @param  filter: External Trigger Filter.
+///   This parameter must be a value between 0x00 and 0x0F
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
+{
+    TIM_ETRConfig(tim, psc, polarity, filter);
+    MODIFY_REG(tim->SMCR, TIM_SMCR_TS | TIM_SMCR_SMS, ((u32)TIM_TS_ETRF) | ((u32)TIM_SlaveMode_External1));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the External clock Mode2
+/// @param  tim:  select the TIM peripheral.
+/// @param  psc: The external Trigger Prescaler.
+///   This parameter can be one of the following values:
+///     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+///     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+///     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+///     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+/// @param  polarity: The external Trigger Polarity.
+///   This parameter can be one of the following values:
+///     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+///     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+/// @param  filter: External Trigger Filter.
+///   This parameter must be a value between 0x00 and 0x0F
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
+{
+    TIM_ETRConfig(tim, psc, polarity, filter);
+    SET_BIT(tim->SMCR, TIM_SMCR_ECEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Prescaler.
+/// @param  tim:  select the TIM peripheral.
+/// @param  prescaler: specifies the Prescaler Register value
+/// @param  reloadMode: specifies the TIM Prescaler Reload mode
+///   This parameter can be one of the following values:
+///     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+///     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reloadMode)
+{
+    WRITE_REG(tim->PSC, prescaler);
+    WRITE_REG(tim->EGR, reloadMode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Specifies the tim Counter Mode to be used.
+/// @param  tim:select the TIM peripheral.
+/// @param  counter_mode: specifies the Counter Mode to be used
+///   This parameter can be one of the following values:
+///     @arg TIM_CounterMode_Up: TIM Up Counting Mode
+///     @arg TIM_CounterMode_Down: TIM Down Counting Mode
+///     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+///     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+///     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode)
+{
+    MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, counter_mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the Input Trigger source
+/// @param  tim: select the TIM peripheral.
+/// @param  source: The Input Trigger source.
+///   This parameter can be one of the following values:
+///     @arg TIM_TS_ITR0: Internal Trigger 0
+///     @arg TIM_TS_ITR1: Internal Trigger 1
+///     @arg TIM_TS_ITR2: Internal Trigger 2
+///     @arg TIM_TS_ITR3: Internal Trigger 3
+///     @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+///     @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+///     @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+///     @arg TIM_TS_ETRF: External Trigger input
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source)
+{
+    MODIFY_REG(tim->SMCR, TIM_SMCR_TS, source);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Encoder Interface.
+/// @param  tim: select the TIM peripheral.
+/// @param  encoder_mode: specifies the tim Encoder Mode.
+///   This parameter can be one of the following values:
+///     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+///     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+///     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+///                                on the level of the other input.
+/// @param  ic1_polarity: specifies the IC1 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Falling: IC Falling edge.
+///     @arg TIM_ICPolarity_Rising: IC Rising edge.
+/// @param  ic2_polarity: specifies the IC2 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Falling: IC Falling edge.
+///     @arg TIM_ICPolarity_Rising: IC Rising edge.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_EncoderInterfaceConfig(TIM_TypeDef*          tim,
+                                TIMSMSENCODER_Typedef encoder_mode,
+                                TIMICP_Typedef        ic1_polarity,
+                                TIMICP_Typedef        ic2_polarity)
+{
+    MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, encoder_mode);
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_CC2S, TIM_CCMR1_CC1S_DIRECTTI | TIM_CCMR1_CC2S_DIRECTTI);
+    MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC2P, ic1_polarity | (ic2_polarity << 4));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces the tim output 1 waveform to active or inactive level.
+/// @param  tim:  select the TIM peripheral.
+/// @param  forced_action: specifies the forced Action to be set to the output waveform.
+///   This parameter can be one of the following values:
+///     @arg TIM_ForcedAction_Active: Force active level on OC1REF
+///     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, forced_action);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces the tim output 2 waveform to active or inactive level.
+/// @param  tim: select the TIM peripheral.
+/// @param  forced_action: specifies the forced Action to be set to the output waveform.
+///   This parameter can be one of the following values:
+///     @arg TIM_ForcedAction_Active: Force active level on OC2REF
+///     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, forced_action << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces the tim output 3 waveform to active or inactive level.
+/// @param  tim: select the TIM peripheral.
+/// @param  forced_action: specifies the forced Action to be set to the output waveform.
+///   This parameter can be one of the following values:
+///     @arg TIM_ForcedAction_Active: Force active level on OC3REF
+///     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, forced_action);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Forces the tim output 4 waveform to active or inactive level.
+/// @param  tim: select the TIM peripheral.
+/// @param  forced_action: specifies the forced Action to be set to the output waveform.
+///   This parameter can be one of the following values:
+///     @arg TIM_ForcedAction_Active: Force active level on OC4REF
+///     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, forced_action << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables tim peripheral Preload register on ARR.
+/// @param  tim:  select the TIM peripheral.
+/// @param  state: new state of the tim peripheral Preload register
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state)
+{
+    (state) ? SET_BIT(tim->CR1, TIM_CR1_ARPEN) : CLEAR_BIT(tim->CR1, TIM_CR1_ARPEN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the TIM peripheral Commutation event.
+/// @param  tim: select the tim peripheral.
+/// @param  state: new state of the Commutation event.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state)
+{
+    (state) ? SET_BIT(tim->CR2, TIM_CR2_CCUS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCUS);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the tim peripheral Capture Compare DMA source.
+/// @param  tim: select the TIM peripheral.
+/// @param  state: new state of the Capture Compare DMA source
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state)
+{
+    (state) ? SET_BIT(tim->CR2, TIM_CR2_CCDS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCDS);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+/// @param  tim: select the tim peripheral.
+/// @param  state: new state of the Capture Compare Preload Control bit
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state)
+{
+    (state) ? SET_BIT(tim->CR2, TIM_CR2_CCPC) : CLEAR_BIT(tim->CR2, TIM_CR2_CCPC);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the tim peripheral Preload register on CCR1.
+/// @param  tim:  select the TIM peripheral.
+/// @param  preload: new state of the tim peripheral Preload register
+///   This parameter can be one of the following values:
+///     @arg TIM_OCPreload_Enable
+///     @arg TIM_OCPreload_Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1PEN, preload);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the tim peripheral Preload register on CCR2.
+/// @param  tim: select the TIM peripheral.
+/// @param  preload: new state of the tim peripheral Preload register
+///   This parameter can be one of the following values:
+///     @arg TIM_OCPreload_Enable
+///     @arg TIM_OCPreload_Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2PEN, preload << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the tim peripheral Preload register on CCR3.
+/// @param  tim: select the TIM peripheral.
+/// @param  preload: new state of the tim peripheral Preload register
+///   This parameter can be one of the following values:
+///     @arg TIM_OCPreload_Enable
+///     @arg TIM_OCPreload_Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3PEN, preload);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the tim peripheral Preload register on CCR4.
+/// @param  tim: select the TIM peripheral.
+/// @param  preload: new state of the tim peripheral Preload register
+///   This parameter can be one of the following values:
+///     @arg TIM_OCPreload_Enable
+///     @arg TIM_OCPreload_Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4PEN, preload << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Output Compare 1 Fast feature.
+/// @param  tim: select the TIM peripheral.
+/// @param  fast: new state of the Output Compare Fast Enable Bit.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCFast_Enable: TIM output compare fast enable
+///     @arg TIM_OCFast_Disable: TIM output compare fast disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1FEN, fast);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Output Compare 2 Fast feature.
+/// @param  tim: select the TIM peripheral.
+/// @param  fast: new state of the Output Compare Fast Enable Bit.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCFast_Enable: TIM output compare fast enable
+///     @arg TIM_OCFast_Disable: TIM output compare fast disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2FEN, fast << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Output Compare 3 Fast feature.
+/// @param  tim: select the TIM peripheral.
+/// @param  fast: new state of the Output Compare Fast Enable Bit.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCFast_Enable: TIM output compare fast enable
+///     @arg TIM_OCFast_Disable: TIM output compare fast disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3FEN, fast);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Output Compare 4 Fast feature.
+/// @param  tim: select the TIM peripheral.
+/// @param  fast: new state of the Output Compare Fast Enable Bit.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCFast_Enable: TIM output compare fast enable
+///     @arg TIM_OCFast_Disable: TIM output compare fast disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4FEN, fast << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears or safeguards the OCREF1 signal on an external event
+/// @param  tim:  select the TIM peripheral.
+/// @param  clear: new state of the Output Compare Clear Enable Bit.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCClear_Enable: TIM Output clear enable
+///     @arg TIM_OCClear_Disable: TIM Output clear disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1CEN, clear);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears or safeguards the OCREF2 signal on an external event
+/// @param  tim: select the TIM peripheral.
+/// @param  clear: new state of the Output Compare Clear Enable Bit.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCClear_Enable: TIM Output clear enable
+///     @arg TIM_OCClear_Disable: TIM Output clear disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2CEN, clear << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears or safeguards the OCREF3 signal on an external event
+/// @param  tim: select the TIM peripheral.
+/// @param  clear: new state of the Output Compare Clear Enable Bit.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCClear_Enable: TIM Output clear enable
+///     @arg TIM_OCClear_Disable: TIM Output clear disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3CEN, clear);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears or safeguards the OCREF4 signal on an external event
+/// @param  tim: select the TIM peripheral.
+/// @param  clear: new state of the Output Compare Clear Enable Bit.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCClear_Enable: TIM Output clear enable
+///     @arg TIM_OCClear_Disable: TIM Output clear disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4CEN, clear << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim channel 1 polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the OC1 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_OCPolarity_High: Output Compare active high
+///     @arg TIM_OCPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
+{
+    MODIFY_REG(tim->CCER, TIM_CCER_CC1P, polarity);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Channel 1N polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the OC1N Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_OCNPolarity_High: Output Compare active high
+///     @arg TIM_OCNPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
+{
+    MODIFY_REG(tim->CCER, TIM_CCER_CC1NP, polarity);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim channel 2 polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the OC2 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_OCPolarity_High: Output Compare active high
+///     @arg TIM_OCPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
+{
+    MODIFY_REG(tim->CCER, TIM_CCER_CC2P, polarity << 4);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Channel 2N polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the OC2N Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_OCNPolarity_High: Output Compare active high
+///     @arg TIM_OCNPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
+{
+    MODIFY_REG(tim->CCER, TIM_CCER_CC2NP, polarity << 4);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim channel 3 polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the OC3 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_OCPolarity_High: Output Compare active high
+///     @arg TIM_OCPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
+{
+    MODIFY_REG(tim->CCER, TIM_CCER_CC3P, polarity << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Channel 3N polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the OC3N Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_OCNPolarity_High: Output Compare active high
+///     @arg TIM_OCNPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
+{
+    MODIFY_REG(tim->CCER, TIM_CCER_CC3NP, polarity << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim channel 4 polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the OC4 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_OCPolarity_High: Output Compare active high
+///     @arg TIM_OCPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
+{
+    MODIFY_REG(tim->CCER, TIM_CCER_CC4P, polarity << 12);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the TIM Capture Compare Channel x.
+/// @param  tim:  select the TIM peripheral.
+/// @param  channel: specifies the TIM Channel
+///   This parameter can be one of the following values:
+///     @arg TIM_Channel_1: TIM Channel 1
+///     @arg TIM_Channel_2: TIM Channel 2
+///     @arg TIM_Channel_3: TIM Channel 3
+///     @arg TIM_Channel_4: TIM Channel 4
+///     @arg TIM_Channel_5: TIM Channel 5(Only for some MM32 TIM1/8)
+/// @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
+///   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en)
+{
+    MODIFY_REG(tim->CCER, TIM_CCER_CC1EN << channel, ccx_en << channel);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the TIM Capture Compare Channel xN.
+/// @param  tim: select the TIM peripheral.
+/// @param  channel: specifies the TIM Channel
+///   This parameter can be one of the following values:
+///     @arg TIM_Channel_1: TIM Channel 1
+///     @arg TIM_Channel_2: TIM Channel 2
+///     @arg TIM_Channel_3: TIM Channel 3
+/// @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+///   This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en)
+{
+    if (channel != TIM_Channel_4)
+        MODIFY_REG(tim->CCER, TIM_CCER_CC1NEN << channel, ccxn_en << channel);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the TIM Output Compare Mode.
+/// @note   This function disables the selected channel before changing the Output
+///         Compare Mode.
+///         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
+/// @param  tim:  select the TIM peripheral.
+/// @param  channel: specifies the TIM Channel
+///   This parameter can be one of the following values:
+///     @arg TIM_Channel_1: TIM Channel 1
+///     @arg TIM_Channel_2: TIM Channel 2
+///     @arg TIM_Channel_3: TIM Channel 3
+///     @arg TIM_Channel_4: TIM Channel 4
+/// @param  mode: specifies the TIM Output Compare Mode.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCMode_Timing
+///     @arg TIM_OCMode_Active
+///     @arg TIM_OCMode_Toggle
+///     @arg TIM_OCMode_PWM1
+///     @arg TIM_OCMode_PWM2
+///     @arg TIM_ForcedAction_Active
+///     @arg TIM_ForcedAction_InActive
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode)
+{
+    CLEAR_BIT(tim->CCER, TIM_CCER_CC1EN << channel);
+    switch (channel) {
+        case TIM_Channel_1:
+            MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, mode);
+            break;
+        case TIM_Channel_2:
+            MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, mode << 8);
+            break;
+        case TIM_Channel_3:
+            MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, mode);
+            break;
+        case TIM_Channel_4:
+            MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, mode << 8);
+            break;
+        default:
+            break;
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or Disables the tim Update event.
+/// @param  tim:  select the TIM peripheral.
+/// @param  state: new state of the tim UDIS bit
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state)
+{
+    (state) ? SET_BIT(tim->CR1, TIM_CR1_UDIS) : CLEAR_BIT(tim->CR1, TIM_CR1_UDIS);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Update Request Interrupt source.
+/// @param  tim:  select the TIM peripheral.
+/// @param  source: specifies the Update source.
+///   This parameter can be one of the following values:
+///     @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
+///                                    or the setting of UG bit, or an update generation
+///                                    through the slave mode controller.
+///     @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source)
+{
+    MODIFY_REG(tim->CR1, TIM_CR1_URS, source);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the tim's Hall sensor interface.
+/// @param  tim: select the TIM peripheral.
+/// @param  state: new state of the tim Hall sensor interface.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state)
+{
+    (state) ? SET_BIT(tim->CR2, TIM_CR2_TI1S) : CLEAR_BIT(tim->CR2, TIM_CR2_TI1S);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the tim's One Pulse Mode.
+/// @param  tim:  select the TIM peripheral.
+/// @param  mode: specifies the OPM Mode to be used.
+///   This parameter can be one of the following values:
+///     @arg TIM_OPMode_Single
+///     @arg TIM_OPMode_Repetitive
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode)
+{
+    MODIFY_REG(tim->CR1, TIM_CR1_OPM, mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the tim Trigger Output Mode.
+/// @param  tim:select the TIM peripheral.
+/// @param  source: specifies the Trigger Output source.
+///   This paramter can be one of the following values:
+///  - For all tim
+///     @arg TIM_TRIGSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
+///     @arg TIM_TRIGSource_Enable: The Counter Enable CEN is used as the trigger output (TRIG).
+///     @arg TIM_TRIGSource_Update: The update event is selected as the trigger output (TRIG).
+///     @arg TIM_TRIGSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+///                              is to be set, as soon as a capture or compare match occurs (TRIG).
+///     @arg TIM_TRIGSource_OC1Ref: OC1REF signal is used as the trigger output (TRIG).
+///     @arg TIM_TRIGSource_OC2Ref: OC2REF signal is used as the trigger output (TRIG).
+///     @arg TIM_TRIGSource_OC3Ref: OC3REF signal is used as the trigger output (TRIG).
+///     @arg TIM_TRIGSource_OC4Ref: OC4REF signal is used as the trigger output (TRIG).
+///
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source)
+{
+    MODIFY_REG(tim->CR2, TIM_CR2_MMS, source);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the tim Slave Mode.
+/// @param  tim: select the TIM peripheral.
+/// @param  mode: specifies the Timer Slave Mode.
+///   This parameter can be one of the following values:
+///     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
+///                               the counter and triggers an update of the registers.
+///     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
+///     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
+///     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode)
+{
+    MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets or Resets the tim Master/Slave Mode.
+/// @param  tim: select the TIM peripheral.
+/// @param  mode: specifies the Timer Master Slave Mode.
+///   This parameter can be one of the following values:
+///     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+///                                      and its slaves (through TRIG).
+///     @arg TIM_MasterSlaveMode_Disable: No action
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode)
+{
+    MODIFY_REG(tim->SMCR, TIM_SMCR_MSM, mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Counter Register value
+/// @param  tim:  select the TIM peripheral.
+/// @param  auto_reload: specifies the Counter register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload)
+{
+    WRITE_REG(tim->ARR, auto_reload);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Input Capture 1 prescaler.
+/// @param  tim:  select the TIM peripheral.
+/// @param  psc: specifies the Input Capture1 prescaler new value.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPSC_DIV1: no prescaler
+///     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+///     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+///     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC1PSC, psc);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Input Capture 2 prescaler.
+/// @param  tim: select the TIM peripheral.
+/// @param  psc: specifies the Input Capture2 prescaler new value.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPSC_DIV1: no prescaler
+///     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+///     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+///     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC2PSC, psc << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Input Capture 3 prescaler.
+/// @param  tim: select the TIM peripheral.
+/// @param  psc: specifies the Input Capture3 prescaler new value.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPSC_DIV1: no prescaler
+///     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+///     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+///     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC3PSC, psc);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Input Capture 4 prescaler.
+/// @param  tim: select the TIM peripheral.
+/// @param  psc: specifies the Input Capture4 prescaler new value.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPSC_DIV1: no prescaler
+///     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+///     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+///     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC4PSC, psc << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Clock Division value.
+/// @param  tim:  select
+///   the TIM peripheral.
+/// @param  clock_div: specifies the clock division value.
+///   This parameter can be one of the following value:
+///     @arg TIM_CKD_DIV1: TDTS = Tck_tim
+///     @arg TIM_CKD_DIV2: TDTS = 2 * Tck_tim
+///     @arg TIM_CKD_DIV4: TDTS = 4 * Tck_tim
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div)
+{
+    MODIFY_REG(tim->CR1, TIM_CR1_CKD, clock_div);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Counter Register value
+/// @param  tim:  select the TIM peripheral.
+/// @param  counter: specifies the Counter register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCounter(TIM_TypeDef* tim, u32 counter)
+{
+    if ((tim == TIM2) || (tim == TIM5))
+        WRITE_REG(tim->CNT, (u32)counter);
+    else
+        WRITE_REG(tim->CNT, (u16)counter);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Capture Compare1 Register value
+/// @param  tim:  select the TIM peripheral.
+/// @param  compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare)
+{
+    if ((tim == TIM2) || (tim == TIM5))
+        WRITE_REG(tim->CCR1, (u32)compare);
+    else
+        WRITE_REG(tim->CCR1, (u16)compare);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Capture Compare2 Register value
+/// @param  tim: select the TIM peripheral.
+/// @param  compare: specifies the Capture Compare2 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare)
+{
+    if ((tim == TIM2) || (tim == TIM5))
+        WRITE_REG(tim->CCR2, (u32)compare);
+    else
+        WRITE_REG(tim->CCR2, (u16)compare);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Capture Compare3 Register value
+/// @param  tim: select the TIM peripheral.
+/// @param  compare: specifies the Capture Compare3 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare)
+{
+    if ((tim == TIM2) || (tim == TIM5))
+        WRITE_REG(tim->CCR3, (u32)compare);
+    else
+        WRITE_REG(tim->CCR3, (u16)compare);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Capture Compare4 Register value
+/// @param  tim:  select the TIM peripheral.
+/// @param  compare: specifies the Capture Compare4 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare)
+{
+    if ((tim == TIM2) || (tim == TIM5))
+        WRITE_REG(tim->CCR4, (u32)compare);
+    else
+        WRITE_REG(tim->CCR4, (u16)compare);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the tim Input Capture 1 value.
+/// @param  tim:  select the TIM peripheral.
+/// @retval Value: Capture Compare 1 Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCapture1(TIM_TypeDef* tim)
+{
+    return tim->CCR1;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the tim Input Capture 2 value.
+/// @param  tim: select the TIM peripheral.
+/// @retval Value: Capture Compare 2 Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCapture2(TIM_TypeDef* tim)
+{
+    return tim->CCR2;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the tim Input Capture 3 value.
+/// @param  tim: select the TIM peripheral.
+/// @retval Value: Capture Compare 3 Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCapture3(TIM_TypeDef* tim)
+{
+    return tim->CCR3;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the tim Input Capture 4 value.
+/// @param  tim: select the TIM peripheral.
+/// @retval Value: Capture Compare 4 Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCapture4(TIM_TypeDef* tim)
+{
+    return tim->CCR4;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the tim Counter value.
+/// @param  tim:  select the TIM peripheral.
+/// @retval Value: Counter Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCounter(TIM_TypeDef* tim)
+{
+    return tim->CNT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the tim Prescaler value.
+/// @param  tim:  select the TIM peripheral.
+/// @retval Value: Prescaler Register value.
+////////////////////////////////////////////////////////////////////////////////
+u16 TIM_GetPrescaler(TIM_TypeDef* tim)
+{
+    return tim->PSC;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified TIM flag is set or not.
+/// @param  tim:  select the TIM peripheral.
+/// @param  flag: specifies the flag to check.
+///   This parameter can be one of the following values:
+///     @arg TIM_FLAG_Update: TIM update Flag
+///     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+///     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+///     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+///     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+///     @arg TIM_FLAG_COM: TIM Commutation Flag
+///     @arg TIM_FLAG_Trigger: TIM Trigger Flag
+///     @arg TIM_FLAG_Break: TIM Break Flag
+///     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+///     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+///     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+///     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+/// @note
+///   - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
+///   - TIM_FLAG_Break is used only with TIM1 and TIM8.
+///   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17.
+/// @retval State: The new state of TIM_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag)
+{
+    return ((tim->SR & flag) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the tim's pending flags.
+/// @param  tim:  select the TIM peripheral.
+/// @param  flag: specifies the flag bit to clear.
+///   This parameter can be any combination of the following values:
+///     @arg TIM_FLAG_Update: TIM update Flag
+///     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+///     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+///     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+///     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+///     @arg TIM_FLAG_COM: TIM Commutation Flag
+///     @arg TIM_FLAG_Trigger: TIM Trigger Flag
+///     @arg TIM_FLAG_Break: TIM Break Flag
+///     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+///     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+///     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+///     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+/// @note
+///   - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
+///   - TIM_FLAG_Break is used only with TIM1 and TIM8.
+///   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag)
+{
+    CLEAR_BIT(tim->SR, flag);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the TIM interrupt has occurred or not.
+/// @param  tim:  select the TIM peripheral.
+/// @param  it: specifies the TIM interrupt source to check.
+///   This parameter can be one of the following values:
+///     @arg TIM_IT_Update: TIM update Interrupt source
+///     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+///     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+///     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+///     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+///     @arg TIM_IT_COM: TIM Commutation Interrupt source
+///     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+///     @arg TIM_IT_Break: TIM Break Interrupt source
+/// @note
+///   - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
+///   - TIM_IT_Break is used only with TIM1 and TIM8.
+///   - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17.
+/// @retval State: The new state of the TIM_IT(SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it)
+{
+    return (((tim->SR & it) && (tim->DIER & it)) ? SET : RESET);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the tim's interrupt pending bits.
+/// @param  tim:  select the TIM peripheral.
+/// @param  it: specifies the pending bit to clear.
+///   This parameter can be any combination of the following values:
+///     @arg TIM_IT_Update: TIM1 update Interrupt source
+///     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+///     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+///     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+///     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+///     @arg TIM_IT_COM: TIM Commutation Interrupt source
+///     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+///     @arg TIM_IT_Break: TIM Break Interrupt source
+/// @note
+///   - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
+///   - TIM_IT_Break is used only with TIM1 and TIM8.
+///   - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearITPendingBit(TIM_TypeDef* tim,  u32 it)    //TIMIT_TypeDef
+{
+    CLEAR_BIT(tim->SR, it);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim channel 1 polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the IC1 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Rising
+///     @arg TIM_ICPolarity_Falling
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
+{
+    (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC1P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC1P);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim channel 2 polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the IC2 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Rising
+///     @arg TIM_ICPolarity_Falling
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
+{
+    (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC2P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC2P);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim channel 3 polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the IC3 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Rising
+///     @arg TIM_ICPolarity_Falling
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
+{
+    (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC3P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC3P);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim channel 4 polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the IC4 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Rising
+///     @arg TIM_ICPolarity_Falling
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
+{
+    (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC4P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC4P);
+}
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim Capture Compare 5 Register value
+/// @param  tim: select the TIM peripheral.
+/// @param  compare: specifies the Capture Compare5 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare)
+{
+    WRITE_REG(tim->CCR5, (u16)compare);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Gets the tim Input Capture 5 value.
+/// @param  tim: select the TIM peripheral.
+/// @retval Value: Capture Compare 5 Register value.
+////////////////////////////////////////////////////////////////////////////////
+u32 TIM_GetCapture5(TIM_TypeDef* tim)
+{
+    return tim->CCR5;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the tim Channel5 according to the specified
+///         parameters in the init_struct.
+/// @param  tim: select the TIM peripheral.
+/// @param  init_struct: pointer to a TIM_OCInitTypeDef structure that
+///         contains the configuration information for the specified TIM peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
+{
+    MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5M, (init_struct->TIM_OCMode) << 4);
+    MODIFY_REG(tim->CCER, TIM_CCER_CC5EN | TIM_CCER_CC5P,
+               (init_struct->TIM_OCPolarity << 16) | (init_struct->TIM_OutputState << 16));
+    WRITE_REG(tim->CCR4, init_struct->TIM_Pulse);
+
+    if ((tim == TIM1) || (tim == TIM8))
+        MODIFY_REG(tim->CR2, TIM_CR2_OIS5, init_struct->TIM_OCIdleState << 8);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the tim peripheral Preload register on CCR5.
+/// @param  tim: select the TIM peripheral.
+/// @param  preload: new state of the tim peripheral Preload register
+///   This parameter can be one of the following values:
+///     @arg TIM_OCPreload_Enable
+///     @arg TIM_OCPreload_Disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
+{
+    MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5PEN, preload);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim channel 5 polarity.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity: specifies the OC5 Polarity
+///   This parameter can be one of the following values:
+///     @arg TIM_OCPolarity_High: Output Compare active high
+///     @arg TIM_OCPolarity_Low: Output Compare active low
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
+{
+    MODIFY_REG(tim->CCER, TIM_CCER_CC5P, polarity << 16);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configures the tim Output Compare 5 Fast feature.
+/// @param  tim: select the TIM peripheral.
+/// @param  fast: new state of the Output Compare Fast Enable Bit.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCFast_Enable: TIM output compare fast enable
+///     @arg TIM_OCFast_Disable: TIM output compare fast disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
+{
+    MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5FEN, fast);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears or safeguards the OCREF4 signal on an external event
+/// @param  tim: select the TIM peripheral.
+/// @param  clear: new state of the Output Compare Clear Enable Bit.
+///   This parameter can be one of the following values:
+///     @arg TIM_OCClear_Enable: TIM Output clear enable
+///     @arg TIM_OCClear_Disable: TIM Output clear disable
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
+{
+    MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5CEN, clear);
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the tim complementary PWM output Status after Break.
+/// @param  tim: select the TIM peripheral.
+/// @param  state: new state of the tim complementary PWM output.
+///   This parameter can be: ENABLE or DISABLE.
+///     @arg ENABLE: Direct output enable, no longer waiting for output after dead time.
+///     @arg DISABLE: Direct output disable, output waiting for dead time.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state)
+{
+    (state) ? SET_BIT(tim->BDTR, TIM_BDTR_DOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_DOEN);
+}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup TIM_Private_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configure the TI1 as Input.
+/// @param  tim:  select the TIM peripheral.
+/// @param  polarity : The Input Polarity.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Rising
+///     @arg TIM_ICPolarity_Falling
+/// @param  selection: specifies the input to be used.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+///     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+///     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+/// @param  filter: Specifies the Input Capture Filter.
+///   This parameter must be a value between 0x00 and 0x0F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_IC1F, (filter << 4) | selection);
+    MODIFY_REG(tim->CCER, TIM_CCER_CC1EN | TIM_CCER_CC1P, polarity | TIM_CCER_CC1EN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configure the TI2 as Input.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity : The Input Polarity.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Rising
+///     @arg TIM_ICPolarity_Falling
+/// @param  selection: specifies the input to be used.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+///     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+///     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+/// @param  filter: Specifies the Input Capture Filter.
+///   This parameter must be a value between 0x00 and 0x0F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
+{
+    MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC2S | TIM_CCMR1_IC2F, (filter << 12) | (selection << 8));
+    MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, (polarity << 4) | TIM_CCER_CC2EN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configure the TI3 as Input.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity : The Input Polarity.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Rising
+///     @arg TIM_ICPolarity_Falling
+/// @param  selection: specifies the input to be used.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+///     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+///     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+/// @param  filter: Specifies the Input Capture Filter.
+///   This parameter must be a value between 0x00 and 0x0F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC3S | TIM_CCMR2_IC3F, (filter << 4) | selection);
+    MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, (polarity << 8) | TIM_CCER_CC3EN);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Configure the TI4 as Input.
+/// @param  tim: select the TIM peripheral.
+/// @param  polarity : The Input Polarity.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICPolarity_Rising
+///     @arg TIM_ICPolarity_Falling
+/// @param  selection: specifies the input to be used.
+///   This parameter can be one of the following values:
+///     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+///     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+///     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+/// @param  filter: Specifies the Input Capture Filter.
+///   This parameter must be a value between 0x00 and 0x0F.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
+{
+    MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC4S | TIM_CCMR2_IC4F, (filter << 12) | (selection << 8));
+    MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, (polarity << 12) | TIM_CCER_CC4EN);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified TIM PWM shift /DMA reqeat.
+/// @param  tim: select the tim peripheral.
+/// @param  it: Specifies the TIM PWM shift channel to enable or disable.
+///   This parameter can be any combination of the following values:
+///     @arg TIM_PDER_CCDREPE: TIM DMA reqeat enable bit
+///     @arg TIM_PDER_CCR1SHIFTEN: TIM Channel 1 output PWM phase shift enable bit
+///     @arg TIM_PDER_CCR2SHIFTEN: TIM Channel 2 output PWM phase shift enable bit
+///     @arg TIM_PDER_CCR3SHIFTEN: TIM Channel 3 output PWM phase shift enable bit
+///     @arg TIM_PDER_CCR4SHIFTEN: TIM Channel 4 output PWM phase shift enable bit
+///     @arg TIM_PDER_CCR5SHIFTEN: TIM Channel 5 output PWM phase shift enable bit
+/// @param  state: new state of the TIM interrupts.
+///   This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state)//TIMIT_TypeDef
+{
+    (state) ? SET_BIT(tim->PDER, it) : CLEAR_BIT(tim->PDER, it);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim CCR1 shift Register value
+/// @param  tim:  select the TIM peripheral.
+/// @param  compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift)
+{
+    if (tim == TIM1)
+        WRITE_REG(tim->CCR1FALL, (u32)shift);
+
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim CCR2 shift Register value
+/// @param  tim:  select the TIM peripheral.
+/// @param  compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift)
+{
+    if (tim == TIM1)
+        WRITE_REG(tim->CCR2FALL, (u32)shift);
+
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim CCR3 shift Register value
+/// @param  tim:  select the TIM peripheral.
+/// @param  compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift)
+{
+    if (tim == TIM1)
+        WRITE_REG(tim->CCR3FALL, (u32)shift);
+
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim CCR4 shift Register value
+/// @param  tim:  select the TIM peripheral.
+/// @param  compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift)
+{
+    if (tim == TIM1)
+        WRITE_REG(tim->CCR4FALL, (u32)shift);
+
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the tim CCR5 shift Register value
+/// @param  tim:  select the TIM peripheral.
+/// @param  compare: specifies the Capture Compare1 register new value.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift)
+{
+    if (tim == TIM1)
+        WRITE_REG(tim->CCR5FALL, (u32)shift);
+
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c
new file mode 100644
index 000000000..2a0578f91
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c
@@ -0,0 +1,502 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_uart.c
+/// @file     hal_uart.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE UART FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_UART_C_
+
+// Files includes
+#include "hal_rcc.h"
+#include "hal_uart.h"
+#include "hal_gpio.h"
+#include "hal_dma.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup UART_HAL
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup UART_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the uart peripheral registers to their
+///         default reset values.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_DeInit(UART_TypeDef* uart)
+{
+
+
+    if(UART2 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART2);
+    }
+    if(UART1 == uart) {
+        exRCC_APB2PeriphReset(RCC_APB2ENR_UART1);
+    }
+    if(UART3 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART3);
+    }
+    if(UART4 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART4);
+    }
+    if(UART5 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART5);
+    }
+    if(UART6 == uart) {
+        exRCC_APB2PeriphReset(RCC_APB2ENR_UART6);
+    }
+    if(UART7 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART7);
+    }
+    if(UART8 == uart) {
+        exRCC_APB1PeriphReset(RCC_APB1ENR_UART8);
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Initializes the uart peripheral according to the specified
+///         parameters in the UART_InitStruct .
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  init_struct: pointer to a UART_InitTypeDef structure
+///         that contains the configuration information for the
+///         specified UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct)
+{
+    u32 apbclock = 0x00;
+    // UART CCR Configuration
+    MODIFY_REG(uart->CCR, UART_CCR_CHAR, init_struct->WordLength);
+
+
+    MODIFY_REG(uart->CCR, (UART_CCR_SPB0 | UART_CCR_SPB1), init_struct->StopBits);
+
+    MODIFY_REG(uart->CCR, (UART_CCR_PEN | UART_CCR_PSEL), init_struct->Parity);
+
+    // UART GCR Configuration
+    MODIFY_REG(uart->GCR, (UART_GCR_TX | UART_GCR_RX), init_struct->Mode);
+    MODIFY_REG(uart->GCR, UART_GCR_AUTOFLOW, init_struct->HWFlowControl);
+
+    //UART BRR Configuration
+    //Configure the UART Baud Rate
+    if (uart == UART1) {
+
+        apbclock = RCC_GetPCLK2Freq();
+    }
+    else {
+        apbclock = RCC_GetPCLK1Freq();
+    }
+    // Determine the UART_baud
+    uart->BRR = (apbclock / init_struct->BaudRate) / 16;
+    uart->FRA = (apbclock / init_struct->BaudRate) % 16;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Fills each UART_InitStruct member with its default value.
+/// @param  init_struct: pointer to a UART_InitTypeDef structure
+///         which will be initialized.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_StructInit(UART_InitTypeDef* init_struct)
+{
+    // UART_InitStruct members default value
+    init_struct->BaudRate       = 9600;
+    init_struct->WordLength     = UART_WordLength_8b;
+    init_struct->StopBits       = UART_StopBits_1;
+    init_struct->Parity         = UART_Parity_No;
+    init_struct->Mode           = UART_GCR_RX | UART_GCR_TX;
+    init_struct->HWFlowControl  = UART_HWFlowControl_None;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified UART peripheral.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the uart peripheral.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Cmd(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->GCR, UART_GCR_UART, state << UART_GCR_UART_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the specified UART interrupts.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  it: specifies the UART interrupt sources to be
+///         enabled or disabled.
+///         This parameter can be one of the following values:
+/// @arg    UART_IT_ERR:  Error interrupt(Frame error,)
+/// @arg    UART_IT_PE:   Parity Error interrupt
+/// @arg    UART_OVER_ERR:  overrun Error interrupt
+/// @arg    UART_IT_RXIEN: Receive Data register interrupt
+/// @arg    UART_IT_TXIEN:  Tansmit Data Register empty interrupt
+///
+/// @param  state: new state of the specified uart interrupts.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state)
+{
+    (state) ? (uart->IER |= it) : (uart->IER &= ~it);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the UART DMA interface.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  dma_request: specifies the DMA request.
+///         This parameter can be any combination of the following values:
+/// @arg    UART_DMAReq_EN: UART DMA transmit request
+///
+/// @param  state: new state of the DMA Request sources.
+///         This parameter can be: ENABLE or DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state)
+{
+    MODIFY_REG(uart->GCR, UART_GCR_DMA, state << UART_GCR_DMA_Pos);
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Transmits single data through the uart peripheral.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  Data: the data to transmit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SendData(UART_TypeDef* uart, u16 value)
+{
+    // Transmit Data
+    WRITE_REG(uart->TDR, (value & 0xFFU));
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the most recent received data by the uart peripheral.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @retval  The received data.
+////////////////////////////////////////////////////////////////////////////////
+u16 UART_ReceiveData(UART_TypeDef* uart)
+{
+    // Receive Data
+    return (u16)(uart->RDR & 0xFFU);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified UART flag is set or not.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  flag: specifies the flag to check.
+///         This parameter can be one of the following values:
+/// @arg    UART_FLAG_TXEMPTY: Transmit data register empty flag
+/// @arg    UART_FLAG_TXFULL: Transmit data buffer full
+/// @arg    UART_FLAG_RXAVL: RX Buffer has a byte flag
+/// @arg    UART_FLAG_TXEPT: tx and shifter are emptys flag
+/// @retval  The new state of UART_FLAG (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag)
+{
+    return (uart->CSR & flag) ? SET : RESET;
+}
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the specified UART interrupt has occurred or not.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  it: specifies the UART interrupt source to check.
+///         This parameter can be one of the following values:
+/// @arg    UART_IT_ERR:  Error interrupt(Frame error,)
+/// @arg    UART_IT_PE:   Parity Error interrupt
+/// @arg    UART_OVER_ERR:  overrun Error interrupt
+/// @arg    UART_IT_RXIEN: Receive Data register interrupt
+/// @arg    UART_IT_TXIEN:  Tansmit Data Register empty interrupt
+/// @retval  The new state of UART_IT (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it)
+{
+    return (uart->ISR & it) ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears the uart interrupt pending bits.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  it: specifies the interrupt pending bit to clear.
+///         This parameter can be one of the following values:
+/// @arg    UART_IT_ERR:  Error interrupt(Frame error,)
+/// @arg    UART_IT_PE:   Parity Error interrupt
+/// @arg    UART_OVER_ERR:  overrun Error interrupt
+/// @arg    UART_IT_RXIEN: Receive Data register interrupt
+/// @arg    UART_IT_TXIEN:  Tansmit Data Register empty interrupt
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it)
+{
+    //clear UART_IT pendings bit
+    uart->ICR = it;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Selects the UART WakeUp method.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  mode: specifies the UART wakeup method.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_WAKE, mode);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Determines if the UART is in mute mode or not.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART mute mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_RWU, state << UART_CCR_RWU_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the address of the UART Rx Address.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  address: Indicates the address of the UART Rx Address.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SetRXAddress(UART_TypeDef* uart, u8 address)
+{
+    MODIFY_REG(uart->RXAR, UART_RXAR_ADDR, address);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the address of the UART Rx MASK.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  address: Indicates the address of the UART Rx MASK.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SetRXMASK(UART_TypeDef* uart, u8 address)
+{
+    MODIFY_REG(uart->RXMR, UART_RXMR_MASK, address);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  ENBALE or DISABLE the UART's 9bit.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART 9 bit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_B8EN, state << UART_CCR_B8EN_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the UART's 9bit Level.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART 9 bit.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_B8TXD, state << UART_CCR_B8TXD_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the UART's 9bit Polarity.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  polarity: new state of the UART 9 bit Polarity.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_B8POL, polarity);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Set the UART's 9bit Automatic Toggle.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART 9 bit Automatic Toggle.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->CCR, UART_CCR_B8TOG, state << UART_CCR_B8TOG_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the UART Half Duplex communication.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART Communication.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->SCR, UART_SCR_HDSEL, state << UART_SCR_HDSEL_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the specified UART guard time.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  guard_time: specifies the guard time.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time)
+{
+    MODIFY_REG(uart->SCR, UART_SCR_SCFCNT, guard_time << UART_SCR_SCFCNT_Pos);
+    // Clear the UART Guard time
+    // uart->SCR &= SCR_SCFCNT_Mask;
+    // Set the UART guard time
+    // uart->SCR |= (u16)((u16)guard_time << 0x04);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables the UART's Smart Card mode.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the Smart Card mode.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->SCR, UART_SCR_SCEN, state << UART_SCR_SCEN_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables or disables NACK transmission.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the NACK transmission.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state)
+{
+    MODIFY_REG(uart->SCR, UART_SCR_SCARB, state << UART_SCR_SCARB_Pos);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Transmits break characters.
+/// @param  uart: Select the UART or the UART peripheral.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_SendBreak(UART_TypeDef* uart)
+{
+    SET_BIT(uart->CCR, UART_CCR_BRK);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enable or Disable Auto Baud-Rate Detection
+/// @param  uart: Select the UART or the UART peripheral.
+/// @param  state: new state of the UART AutoBaudRate Detection.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state)
+{
+    state ? SET_BIT(uart->ABRCR, UART_ABRCR_ABREN) : CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN) ;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  AutoBaudRate.
+/// @param  uart: Select the UART or the UART peripheral.
+///         value: special character.
+///         state: ENABLE/DISABLE.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state)
+{
+    CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN);
+    //This bit field can only be written when ABREN = 0 or the UART is disabled (UARTEN=0).
+
+    if ((value == ABRMODE_FALLING_TO_RISINGEDGE1BIT) || (value == ABRMODE_STARTBIT) || (value == ABRMODE_VALUE0XFF)) {
+        //UART measures the duration of the start bit (falling edge) to first rising edge
+        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = one bit
+        //___   _               _______
+        //   |_|1 x x x x x x x|        = Bxxxx xxx1  F to U = 1 start bit
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE0 );
+    }
+    else if((value == ABRMODE_FALLING_TO_RISINGEDGE2BIT) || (value == Data_FE))  {
+        //UART measures the duration of the start bit (falling edge) to first rising edge
+        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = two bit
+        //___     _             _______
+        //   |_ _|1 x x x x x x|        = Bxxxx xx10  F to U = 2
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE1);
+    }
+    else if((value == ABRMODE_FALLING_TO_RISINGEDGE4BIT) || (value == Data_F8)) {
+        //UART measures the duration of the start bit (falling edge) to first rising edge
+        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = four bit
+        //___         _         _______
+        //   |_ _ _ _|1 x x x x|        = Bxxxx 1000  F to U = 4
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE2);
+    }
+    else if((value == ABRMODE_FALLING_TO_RISINGEDGE8BIT) || (value == ABRMODE_VALUE0X80))  {
+        //UART measures the duration of the start bit (falling edge) to first rising edge
+        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = eight bit
+        //___                 _ ______
+        //   |_ _ _ _ _ _ _ _|1         = B1000 0000  F to U = 8
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE3);
+    }
+    else if((value == ABRMODE_FALLING_TO_FALLINGEDGE2BIT) || (value == ABRMODE_VALUE0X55)) {
+        //UART measures the duration of the start bit (falling edge) to next falling edge
+        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = two bit
+        //___   _               ______
+        //   |_|1|_|x x x x x x|        = Bxxxx xx01  F to F = 2 0x55 and Falling to Falling
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_BITCNT_MODE1);
+    }
+    else if((value == ABRMODE_FALLING_TO_FALLINGEDGE4BIT) || (value == ABRMODE_VALUE0XF7))  {
+        //UART measures the duration of the start bit (falling edge) to next falling edge
+        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = four bit
+        //___   _ _ _           ______
+        //   |_|1 1 1|_|x x x x|        = Bxxxx 0111  F to F = 4
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_BITCNT_MODE2);
+    }
+    else if((value == ABRMODE_FALLING_TO_FALLINGEDGE8BIT) || (value == ABRMODE_VALUE0x7F)) {
+        //UART measures the duration of the start bit (falling edge) to next falling edge
+        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = eight bit
+        //___   _ _ _ _ _ _ _   ______
+        //   |_|1 1 1 1 1 1 1|_|        = B0111 1111  F to F = 8 0x7F
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_BITCNT_MODE3);
+    }
+
+    else {
+        //UART measures the duration of the start bit (falling edge) to next falling edge
+        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = eight bit
+        //___   _ _ _ _ _ _ _   ______
+        //   |_|1 1 1 1 1 1 1|_|        = B0111 1111  F to F = 8 0x7F
+        //
+        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
+                   UART_ABRCR_BITCNT_MODE3);
+    }
+    if(state == ENABLE) {
+        SET_BIT(uart->ABRCR, UART_ABRCR_ABREN);
+    }
+}
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c
new file mode 100644
index 000000000..e51bfcade
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c
@@ -0,0 +1,55 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_uid.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE UID FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_UID_C_
+
+// Files includes
+#include "hal_uid.h"
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup UID_HAL
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup UID_Exported_Functions
+/// @{
+
+u8 device_id_data[12] = {0};
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Get device ID.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void GetChipUID(void)
+{
+    u8 i;
+
+    for (i = 0; i < 12; i++) {
+        device_id_data[i] = *((vu8*)(UID_BASE + i));
+    }
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c
new file mode 100644
index 000000000..9d771396c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c
@@ -0,0 +1,131 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_ver.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE LIB AND THE CHIPSET INFORMATION.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_VER_C_
+
+// Files includes
+#include "hal_ver.h"
+
+
+// MM32 Library version is 0.90
+
+#define __MM32_LIB_VERSION_MAIN         (0x0U)                                  //!< [31:24] main version 
+#define __MM32_LIB_VERSION_SUB1         (0x9U)                                  //!< [23:16] sub1 version
+#define __MM32_LIB_VERSION_SUB2         (0x0U)                                  //!< [15:8]  sub2 version
+#define __MM32_LIB_VERSION_RC           (0x00U)                                 //!< [7:0]  release candidate
+#define __MM32_LIB_VERSION              ((__MM32_LIB_VERSION_MAIN << 24U)\
+                                         |(__MM32_LIB_VERSION_SUB1 << 16U)\
+                                         |(__MM32_LIB_VERSION_SUB2 << 8U )\
+                                         |(__MM32_LIB_VERSION_RC))
+
+// MM32 Library release date is 2021-05-10 (YYYY-MM-DD)
+#define __MM32_LIB_RELESE_YEARH         (0x20U)                                  //!< [31:24] release year high 
+#define __MM32_LIB_RELESE_YEARL         (0x21U)                                  //!< [23:16] release year low
+#define __MM32_LIB_RELESE_MONTH         (0x05U)                                  //!< [15:8]  release month
+#define __MM32_LIB_RELESE_DAY           (0x10U)                                //!< [7:0]   release day
+#define __MM32_LIB_RELESE_DATE          ((__MM32_LIB_RELESE_YEARH << 24U)\
+                                         |(__MM32_LIB_RELESE_YEARL << 16U)\
+                                         |(__MM32_LIB_RELESE_MONTH << 8U )\
+                                         |(__MM32_LIB_RELESE_DAY))
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+///@addtogroup VER_HAL
+///@{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup Lib and chipset_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  This method returns the Lib revision.
+/// @param  None.
+/// @retval return the Lib version.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_MM32LibVersion(void)
+{
+    return __MM32_LIB_VERSION;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  This method returns the Lib release date.
+/// @param  None.
+/// @retval return the Lib release date.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_MM32LibReleaseDate(void)
+{
+    return __MM32_LIB_RELESE_DATE;
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the device revision identifier.
+/// @param  None.
+/// @retval return the device revision identifier.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetREVID(void)
+{
+    return((DBGMCU->IDCODE) & 0xF );
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns the device identifier..
+/// @param  None.
+/// @retval return the device Device identifier.
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetDEVID(void)
+{
+    return((DBGMCU->IDCODE) );
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+/// @param  None.
+/// @retval Device identifier
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetUIDw0(void)
+{
+    return(READ_REG(*((vu32*)UID_BASE)));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+/// @param  None.
+/// @retval Device identifier
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetUIDw1(void)
+{
+    return(READ_REG(*((vu32*)(UID_BASE + 4U))));
+}
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+/// @param  None.
+/// @retval Device identifier
+////////////////////////////////////////////////////////////////////////////////
+u32 Get_ChipsetUIDw2(void)
+{
+    return(READ_REG(*((vu32*)(UID_BASE + 8U))));
+}
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c
new file mode 100644
index 000000000..05d74b596
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c
@@ -0,0 +1,147 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     hal_wwdg.c
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE WWDG FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _HAL_WWDG_C_
+
+// Files includes
+#include "hal_wwdg.h"
+#include "hal_rcc.h"
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup MM32_Hardware_Abstract_Layer
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup WWDG_HAL
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @addtogroup WWDG_Exported_Functions
+/// @{
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Deinitializes the WWDG peripheral registers to their default reset
+/// values.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_DeInit()
+{
+    exRCC_APB1PeriphReset(RCC_APB1RSTR_WWDG);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the WWDG Prescaler.
+/// @param  WWDG_Prescaler: specifies the WWDG Prescaler.
+///         This parameter can be one of the following values:
+///             @arg WWDG_Prescaler_1: WWDG counter clock = APB1CLK / 4096 / 1
+///             @arg WWDG_Prescaler_2: WWDG counter clock = APB1CLK / 4096 / 2
+///             @arg WWDG_Prescaler_4: WWDG counter clock = APB1CLK / 4096 / 4
+///             @arg WWDG_Prescaler_8: WWDG counter clock = APB1CLK / 4096 / 8
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_SetPrescaler(u32 prescaler)
+{
+    WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WDGTB) | prescaler;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the WWDG window value.
+/// @param  WindowValue: specifies the window value to be compared to the
+/// downcounter.
+///          This parameter value must be lower than 0x80.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_SetWindowValue(u8 window_value)
+{
+    WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WINDOW) | (window_value & WWDG_CFGR_WINDOW);
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+/// @note   Once enabled this interrupt cannot be disabled except by a system
+/// reset.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_EnableIT()
+{
+    WWDG->CFGR |= WWDG_CFGR_EWI;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Sets the WWDG counter value.
+/// @param  Counter: specifies the watchdog counter value.
+///         This parameter must be a number between 0x40 and 0x7F (to prevent
+///         generating an immediate reset).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_SetCounter(u8 count)
+{
+    WWDG->CR = count & WWDG_CFGR_WINDOW;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables WWDG and load the counter value.
+/// @param  Counter: specifies the watchdog counter value.
+///         This parameter must be a number between 0x40 and 0x7F (to prevent
+///         generating an immediate reset).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+u32 WWDG_GetCounter()
+{
+    return WWDG->CR & WWDG_CR_CNT;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Enables WWDG and load the counter value.
+/// @param  Counter: specifies the watchdog counter value.
+///         This parameter must be a number between 0x40 and 0x7F (to prevent
+///         generating an immediate reset).
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_Enable(u8 count)
+{
+    WWDG->CR = WWDG_CR_WDGA | count;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+/// @param  None.
+/// @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
+////////////////////////////////////////////////////////////////////////////////
+FlagStatus WWDG_GetFlagStatus()
+{
+    return WWDG->SR ? SET : RESET;
+}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  Clears Early Wakeup interrupt flag.
+/// @param  None.
+/// @retval None.
+////////////////////////////////////////////////////////////////////////////////
+void WWDG_ClearFlag()
+{
+    WWDG->SR &= ~WWDG_SR_EWIF;
+}
+
+/// @}
+
+/// @}
+
+/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h
new file mode 100644
index 000000000..1a85c131a
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h
@@ -0,0 +1,23 @@
+///-----------------------------------------------------------------------------
+/// @file mm32_device.h
+/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion
+///        microcontroller devices
+///
+/// This is a convenience header file for defining the part number on the
+/// build command line, instead of specifying the part specific header file.
+///
+/// Example: Add MM32 series to your build options, to define part
+///          Add "#include "mm32_device.h" to your source files
+///
+///
+///
+///
+///-----------------------------------------------------------------------------
+
+#ifndef __MM32_DEVICE_H
+#define __MM32_DEVICE_H
+
+#include "mm32_reg.h"
+
+#endif // __MM32_DEVICE_H 
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h
new file mode 100644
index 000000000..dfba84215
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h
@@ -0,0 +1,71 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     mm32_reg.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+////////////////////////////////////////////////////////////////////////////////
+#ifndef __MM32_REG_H
+#define __MM32_REG_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#include "reg_common.h"
+#include "reg_adc.h"
+#include "reg_bkp.h"
+#include "reg_can.h"
+#include "reg_comp.h"
+#include "reg_crc.h"
+#include "reg_crs.h"
+#include "reg_dac.h"
+#include "reg_dbg.h"
+#include "reg_dma.h"
+#include "reg_exti.h"
+#include "reg_eth.h"
+#include "reg_flash.h"
+#include "reg_gpio.h"
+#include "reg_i2c.h"
+#include "reg_iwdg.h"
+#include "reg_pwm.h"
+#include "reg_pwr.h"
+#include "reg_rcc.h"
+#include "reg_rtc.h"
+#include "reg_sdio.h"
+#include "reg_spi.h"
+#include "reg_syscfg.h"
+#include "reg_tim.h"
+#include "reg_uart.h"
+#include "reg_usb_otg_fs.h"
+#include "reg_wwdg.h"
+
+////////////////////////////////////////////////////////////////////////////////
+#include "mm32_reg_redefine_v1.h"
+////////////////////////////////////////////////////////////////////////////////
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif // __MM32_REG_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h
new file mode 100644
index 000000000..6cdd79ead
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h
@@ -0,0 +1,1175 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     mm32_reg_define_v1.H
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE define for version compatibility define
+///           FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __MM32_REG_DEFINE_V1_H
+#define __MM32_REG_DEFINE_V1_H
+
+// Files includes
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief redefine for register
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+/// @brief redefine for ADC of MCU register
+////////////////////////////////////////////////////////////////////////////////
+
+#define ADC_COMP_IRQHandler             ADC1_COMP_IRQHandler
+
+#define ADDATA_DATA                     ADC_DR_DATA
+
+#define ADDATA_CHANNELSEL               ADC_DR_CH
+#define ADDATA_CHANNELSEL_0             ADC_DR_CH0
+#define ADDATA_CHANNELSEL_1             ADC_DR_CH1
+#define ADDATA_CHANNELSEL_2             ADC_DR_CH2
+#define ADDATA_CHANNELSEL_3             ADC_DR_CH3
+#define ADDATA_CHANNELSEL_4             ADC_DR_CH4
+#define ADDATA_CHANNELSEL_5             ADC_DR_CH5
+#define ADDATA_CHANNELSEL_6             ADC_DR_CH6
+#define ADDATA_CHANNELSEL_7             ADC_DR_CH7
+
+
+
+
+#define ADDATA_CHANNELSEL_CH8           ADC_DR_CH8
+#define ADDATA_CHANNELSEL_CH9           ADC_DR_CH9
+#define ADDATA_CHANNELSEL_CH10          ADC_DR_CH10
+#define ADDATA_CHANNELSEL_CH11          ADC_DR_CH11
+#define ADDATA_CHANNELSEL_CH12          ADC_DR_CH12
+#define ADDATA_CHANNELSEL_CH13          ADC_DR_CH13
+#define ADDATA_CHANNELSEL_CH14          ADC_DR_CH14
+#define ADDATA_CHANNELSEL_CH15          ADC_DR_CH15
+#define ADDATA_CHANNELSEL_TempSensor    ADC_DR_TempSensor
+#define ADDATA_CHANNELSEL_VolSensor     ADC_DR_VoltRef
+
+
+#define ADDATA_OVERRUN                  ADC_DR_OVERRUN
+#define ADDATA_VALID                    ADC_DR_VALID
+
+#define ADCFG_ADEN                      ADC_CFGR_ADEN
+#define ADCFG_ADWEN                     ADC_CFGR_ADWEN
+
+#define ADCFG_RSLTCTL                   ADC_CFGR_RSLTCTL
+#define ADCFG_RSLTCTL_12                ADC_CFGR_RSLTCTL_12
+#define ADCFG_RSLTCTL_11                ADC_CFGR_RSLTCTL_11
+#define ADCFG_RSLTCTL_10                ADC_CFGR_RSLTCTL_10
+#define ADCFG_RSLTCTL_9                 ADC_CFGR_RSLTCTL_9
+#define ADCFG_RSLTCTL_8                 ADC_CFGR_RSLTCTL_8
+
+
+#define ADCFG_TSEN                      ADC_CFGR_TEN
+#define ADCFG_VSEN                      ADC_CFGR_VEN
+
+#define ADCFG_ADCPRE                    ADC_CFGR_PRE
+#define ADCFG_ADCPRE_2                  ADC_CFGR_PRE_2
+#define ADCFG_ADCPRE_4                  ADC_CFGR_PRE_4
+#define ADCFG_ADCPRE_6                  ADC_CFGR_PRE_6
+#define ADCFG_ADCPRE_8                  ADC_CFGR_PRE_8
+#define ADCFG_ADCPRE_10                 ADC_CFGR_PRE_10
+#define ADCFG_ADCPRE_12                 ADC_CFGR_PRE_12
+#define ADCFG_ADCPRE_14                 ADC_CFGR_PRE_14
+#define ADCFG_ADCPRE_16                 ADC_CFGR_PRE_16
+#define ADCFG_SAMCTL                    ADC_CFGR_SAMCTL
+#define ADCFG_SAMCTL_1_5                ADC_CFGR_SAMCTL_1_5
+#define ADCFG_SAMCTL_7_5                ADC_CFGR_SAMCTL_7_5
+#define ADCFG_SAMCTL_13_5               ADC_CFGR_SAMCTL_13_5
+#define ADCFG_SAMCTL_28_5               ADC_CFGR_SAMCTL_28_5
+#define ADCFG_SAMCTL_41_5               ADC_CFGR_SAMCTL_41_5
+#define ADCFG_SAMCTL_55_5               ADC_CFGR_SAMCTL_55_5
+#define ADCFG_SAMCTL_71_5               ADC_CFGR_SAMCTL_71_5
+#define ADCFG_SAMCTL_239_5              ADC_CFGR_SAMCTL_239_5
+
+
+#define ADCFG_ADCPRE_3                  ADC_CFGR_PRE_3
+#define ADCFG_ADCPRE_5                  ADC_CFGR_PRE_5
+#define ADCFG_ADCPRE_7                  ADC_CFGR_PRE_7
+#define ADCFG_ADCPRE_9                  ADC_CFGR_PRE_9
+#define ADCFG_ADCPRE_11                 ADC_CFGR_PRE_11
+#define ADCFG_ADCPRE_13                 ADC_CFGR_PRE_13
+#define ADCFG_ADCPRE_15                 ADC_CFGR_PRE_15
+#define ADCFG_ADCPRE_17                 ADC_CFGR_PRE_17
+#define ADCFG_SAMCTL_2_5                ADC_CFGR_SAMCTL_2_5
+#define ADCFG_SAMCTL_3_5                ADC_CFGR_SAMCTL_3_5
+#define ADCFG_SAMCTL_4_5                ADC_CFGR_SAMCTL_4_5
+#define ADCFG_SAMCTL_5_5                ADC_CFGR_SAMCTL_5_5
+#define ADCFG_SAMCTL_6_5                ADC_CFGR_SAMCTL_6_5
+
+#define ADCR_ADIE                       ADC_CR_ADIE
+#define ADCR_ADWIE                      ADC_CR_ADWIE
+#define ADCR_TRGEN                      ADC_CR_TRGEN
+#define ADCR_DMAEN                      ADC_CR_DMAEN
+#define ADCR_ADST                       ADC_CR_ADST
+#define ADCR_ADMD                       ADC_CR_MODE
+#define ADCR_ADMD_SINGLE                ADC_CR_IMM
+#define ADCR_ADMD_PERIOD                ADC_CR_SCAN
+#define ADCR_ADMD_CONTINUE              ADC_CR_CONTINUE
+#define ADC_Mode_Single                 ADC_CR_IMM
+#define ADC_Mode_Single_Period          ADC_CR_SCAN
+#define ADC_Mode_Continuous_Scan        ADC_CR_CONTINUE
+
+
+#define ADCR_ALIGN                      ADC_CR_ALIGN
+#define ADCR_ALIGN_LEFT                 ADC_CR_LEFT
+#define ADCR_ALIGN_RIGHT                ADC_CR_RIGHT
+#define ADCR_CMPCH_Pos                  ADC_CR_CMPCH_Pos
+#define ADCR_CMPCH                      ADC_CR_CMPCH
+#define ADCR_CMPCH_0                    ADC_CR_CMPCH_0
+#define ADCR_CMPCH_1                    ADC_CR_CMPCH_1
+#define ADCR_CMPCH_2                    ADC_CR_CMPCH_2
+#define ADCR_CMPCH_4                    ADC_CR_CMPCH_4
+#define ADCR_CMPCH_5                    ADC_CR_CMPCH_5
+#define ADCR_CMPCH_6                    ADC_CR_CMPCH_6
+#define ADCR_CMPCH_7                    ADC_CR_CMPCH_7
+#define ADCR_CMPCH_8                    ADC_CR_CMPCH_8
+#define ADCR_CMPCH_9                    ADC_CR_CMPCH_9
+#define ADCR_CMPCH_10                   ADC_CR_CMPCH_10
+#define ADCR_CMPCH_11                   ADC_CR_CMPCH_11
+#define ADCR_CMPCH_13                   ADC_CR_CMPCH_13
+#define ADCR_CMPCH_14                   ADC_CR_CMPCH_14
+#define ADCR_CMPCH_ALL                  ADC_CR_CMPCH_ALL
+
+
+#define ADCR_TRGSEL                     ADC_CR_TRGSEL
+#define ADCR_TRGSEL_T1_CC1              ADC_CR_T1_CC1
+#define ADCR_TRGSEL_T1_CC2              ADC_CR_T1_CC2
+#define ADCR_TRGSEL_T1_CC3              ADC_CR_T1_CC3
+#define ADCR_TRGSEL_T2_CC2              ADC_CR_T2_CC2
+#define ADCR_TRGSEL_T3_TRGO             ADC_CR_T3_TRIG
+#define ADCR_TRGSEL_EXTI_11             ADC_CR_EXTI_11
+
+
+
+#define ADCR_TRGSEL_T1_CC4_CC5          ADC_CR_T1_CC4_CC5
+#define ADCR_TRGSEL_T3_CC1              ADC_CR_T3_CC1
+#define ADCR_TRGSEL_T1_TRGO             ADC_CR_T1_TRIG
+#define ADCR_TRGSEL_T8_CC4              ADC_CR_T8_CC4
+#define ADCR_TRGSEL_T8_CC4_CC5          ADC_CR_T8_CC4_CC5
+#define ADCR_TRGSEL_T2_CC1              ADC_CR_T2_CC1
+#define ADCR_TRGSEL_T3_CC4              ADC_CR_T3_CC4
+#define ADCR_TRGSEL_T2_TRGO             ADC_CR_T2_TRIG
+#define ADCR_TRGSEL_T8_CC5              ADC_CR_T8_CC5
+#define ADCR_TRGSEL_EXTI_15             ADC_CR_EXTI_15
+#define ADCR_TRGSEL_TIM1_CC4            ADC_CR_TIM1_CC4
+#define ADCR_TRGSEL_TIM1_CC5            ADC_CR_TIM1_CC5
+#define ADCR_SCANDIR                    ADC_CR_SCANDIR
+#define ADCR_TRGSHIFT                   ADC_CR_TRGSHIFT
+#define ADCR_TRGSHIFT_0                 ADC_CR_TRGSHIFT_0
+#define ADCR_TRGSHIFT_4                 ADC_CR_TRGSHIFT_4
+#define ADCR_TRGSHIFT_16                ADC_CR_TRGSHIFT_16
+#define ADCR_TRGSHIFT_32                ADC_CR_TRGSHIFT_32
+#define ADCR_TRGSHIFT_64                ADC_CR_TRGSHIFT_64
+#define ADCR_TRGSHIFT_128               ADC_CR_TRGSHIFT_128
+#define ADCR_TRGSHIFT_256               ADC_CR_TRGSHIFT_256
+#define ADCR_TRGSHIFT_512               ADC_CR_TRGSHIFT_512
+#define ADCR_CALIBEN                    ADC_CR_CALIBEN
+#define ADCR_CALIBSEL                   ADC_CR_CALIBSEL
+
+#define ADCHS_CHEN0                     ADC_CHSR_CH0
+#define ADCHS_CHEN1                     ADC_CHSR_CH1
+#define ADCHS_CHEN2                     ADC_CHSR_CH2
+#define ADCHS_CHEN3                     ADC_CHSR_CH3
+#define ADCHS_CHEN4                     ADC_CHSR_CH4
+#define ADCHS_CHEN5                     ADC_CHSR_CH5
+#define ADCHS_CHEN6                     ADC_CHSR_CH6
+#define ADCHS_CHEN7                     ADC_CHSR_CH7
+#define ADCHS_ALL                       ADC_CHSR_CHALL
+
+
+#define ADCHS_CHEN8                     ADC_CHSR_CH8
+#define ADCHS_CHEN9                     ADC_CHSR_CH9
+#define ADCHS_CHENTS                    ADC_CHSR_CHT
+#define ADCHS_CHENVS                    ADC_CHSR_CHV
+#define ADCHS_CHEN8                     ADC_CHSR_CH8
+#define ADCHS_CHEN9                     ADC_CHSR_CH9
+#define ADCHS_CHEN10                    ADC_CHSR_CH10
+#define ADCHS_CHEN11                    ADC_CHSR_CH11
+#define ADCHS_CHEN12                    ADC_CHSR_CH12
+#define ADCHS_CHEN13                    ADC_CHSR_CH13
+#define ADCHS_CHEN14                    ADC_CHSR_CH14
+#define ADCHS_CHEN15                    ADC_CHSR_CH15
+#define ADCHS_CHENTS                    ADC_CHSR_CHT
+#define ADCHS_CHENVS                    ADC_CHSR_CHV
+
+
+#define ADCMPR_CMPLDATA                 ADC_CMPR_CMPLDATA
+#define ADCMPR_CMPHDATA                 ADC_CMPR_CMPHDATA
+
+#define ADSTA_ADIF                      ADC_SR_ADIF
+#define ADSTA_ADWIF                     ADC_SR_ADWIF
+#define ADSTA_BUSY                      ADC_SR_BUSY
+#define ADSTA_CHANNEL                   ADC_SR_CH
+#define ADSTA_CHANNEL_CH0               ADC_SR_CH0
+#define ADSTA_CHANNEL_CH1               ADC_SR_CH1
+#define ADSTA_CHANNEL_CH2               ADC_SR_CH2
+#define ADSTA_CHANNEL_CH3               ADC_SR_CH3
+#define ADSTA_CHANNEL_CH4               ADC_SR_CH4
+#define ADSTA_CHANNEL_CH5               ADC_SR_CH5
+#define ADSTA_CHANNEL_CH6               ADC_SR_CH6
+#define ADSTA_CHANNEL_CH7               ADC_SR_CH7
+#define ADSTA_CHANNEL_CH8               ADC_SR_CH8
+#define ADSTA_CHANNEL_CH9               ADC_SR_CH9
+#define ADSTA_CHANNEL_CH10              ADC_SR_CH10
+#define ADSTA_CHANNEL_CH11              ADC_SR_CH11
+#define ADSTA_CHANNEL_CH13              ADC_SR_CH13
+#define ADSTA_CHANNEL_CH14              ADC_SR_CH14
+#define ADSTA_CHANNEL_CH15              ADC_SR_CH15
+#define ADSTA_VALID                     ADC_SR_VALID
+#define ADSTA_OVERRUN                   ADC_SR_OVERRUN
+
+#define ADDR_OVERRUN                    ADC_CHDR_OVERRUN
+#define ADDR_VALID                      ADC_CHDR_VALID
+#define ADDR_DATA                       ADC_CHDR_DATA
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief redefine for HAL library
+////////////////////////////////////////////////////////////////////////////////
+
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+/// @brief redefine for ADC of HAL library
+////////////////////////////////////////////////////////////////////////////////
+
+
+#define ADC_ExternalTrigConv_T1_CC1     ADC1_ExternalTrigConv_T1_CC1
+#define ADC_ExternalTrigConv_T1_CC2     ADC1_ExternalTrigConv_T1_CC2
+#define ADC_ExternalTrigConv_T1_CC3     ADC1_ExternalTrigConv_T1_CC3
+#define ADC_ExternalTrigConv_T2_CC2     ADC1_ExternalTrigConv_T2_CC2
+#define ADC_ExternalTrigConv_T3_TRIG    ADC1_ExternalTrigConv_T3_TRIG
+#define ADC_ExternalTrigConv_T3_CC1     ADC1_ExternalTrigConv_T3_CC1
+#define ADC_ExternalTrigConv_EXTI_11    ADC1_ExternalTrigConv_EXTI_11
+#define ADC_ExternalTrigConv_T1_CC4_CC5  ADC1_ExternalTrigConv_T1_CC4_CC5
+#define ADC_ExternalTrigConv_T1_TRIG     ADC1_ExternalTrigConv_T1_TRIG
+#define ADC_ExternalTrigConv_T8_CC4      ADC1_ExternalTrigConv_T8_CC4
+#define ADC_ExternalTrigConv_T8_CC4_CC5  ADC1_ExternalTrigConv_T8_CC4_CC5
+#define ADC_ExternalTrigConv_T2_CC1      ADC1_ExternalTrigConv_T2_CC1
+#define ADC_ExternalTrigConv_T3_CC4      ADC1_ExternalTrigConv_T3_CC4
+#define ADC_ExternalTrigConv_T2_TRIG     ADC1_ExternalTrigConv_T2_TRIG
+#define ADC_ExternalTrigConv_T8_CC5      ADC1_ExternalTrigConv_T8_CC5
+#define ADC_ExternalTrigConv_EXTI_15     ADC1_ExternalTrigConv_EXTI_15
+#define ADC_ExternalTrigConv_T1_CC4      ADC1_ExternalTrigConv_T1_CC4
+#define ADC_ExternalTrigConv_T1_CC5      ADC1_ExternalTrigConv_T1_CC5
+
+
+
+#define ADC_SampleTime_1_5Cycles         ADC_Samctl_1_5
+#define ADC_SampleTime_7_5Cycles         ADC_Samctl_7_5
+#define ADC_SampleTime_13_5Cycles        ADC_Samctl_13_5
+#define ADC_SampleTime_28_5Cycles        ADC_Samctl_28_5
+#define ADC_SampleTime_41_5Cycles        ADC_Samctl_41_5
+#define ADC_SampleTime_55_5Cycles        ADC_Samctl_55_5
+#define ADC_SampleTime_71_5Cycles        ADC_Samctl_71_5
+#define ADC_SampleTime_239_5Cycles       ADC_Samctl_239_5
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+#define AES_KEYR0                       AES_KEYRn                               ///< AES Key Register 0
+#define AES_KEYR1                       AES_KEYRn                               ///< AES Key Register 1
+#define AES_KEYR2                       AES_KEYRn                               ///< AES Key Register 2
+#define AES_KEYR3                       AES_KEYRn                               ///< AES Key Register 3
+#define AES_KEYR4                       AES_KEYRn                               ///< AES Key Register 4
+#define AES_KEYR5                       AES_KEYRn                               ///< AES Key Register 5
+#define AES_KEYR6                       AES_KEYRn                               ///< AES Key Register 6
+#define AES_KEYR7                       AES_KEYRn                               ///< AES Key Register 7
+
+#define AES_IVR0                        AES_IVRn                                ///< AES Initialization Vector Register 0
+#define AES_IVR1                        AES_IVRn                                ///< AES Initialization Vector Register 1
+#define AES_IVR2                        AES_IVRn                                ///< AES Initialization Vector Register 2
+#define AES_IVR3                        AES_IVRn                                ///< AES Initialization Vector Register 3
+
+
+#define CRC_DR_DR                       CRC_DR_DATA
+#define CRC_IDR_IDR                     CRC_IDR_DATA
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_CR_SYNCOKIE                 CRS_CR_OKIE
+#define CRS_CR_SYNCWARNIE               CRS_CR_WARNIE
+#define CRS_CR_ESYNCIE                  CRS_CR_EXPTIE
+#define CRS_CR_CEN                      CRS_CR_CNTEN
+#define CRS_CFGR_SYNCDIV                CRS_CFGR_DIV
+#define CRS_CFGR_SYNCSRC                CRS_CFGR_SRC
+#define CRS_CFGR_SYNCPOL                CRS_CFGR_POL
+#define CRS_ISR_SYNCOKF                 CRS_ISR_OKIF
+#define CRS_ISR_SYNCWARNF               CRS_ISR_WARNIF
+#define CRS_ISR_ERRF                    CRS_ISR_ERRIF
+#define CRS_ISR_ESYNCF                  CRS_ISR_EXPTIF
+#define CRS_ISR_SYNCERR                 CRS_ISR_ERR
+#define CRS_ISR_SYNCMISS                CRS_ISR_MISS
+#define CRS_ISR_TRIMOVF                 CRS_ISR_OVERFLOW
+#define CRS_ICR_SYNCOKC                 CRS_ICR_OK
+#define CRS_ICR_SYNCWARNC               CRS_ICR_WARN
+#define CRS_ICR_ERRC                    CRS_ICR_ERR
+#define CRS_ICR_ESYNCC                  CRS_ICR_EXPT
+
+#define CRS_IT_SYNCOK                   CRS_ISR_SYNCOKF                         ///< SYNC event OK
+#define CRS_IT_SYNCWARN                 CRS_ISR_SYNCWARNF                       ///< SYNC warning
+#define CRS_IT_ERR                      CRS_CR_ERRIE                            ///< error
+#define CRS_IT_ESYNC                    CRS_ISR_ESYNCF                          ///< Expected SYNC
+#define CRS_IT_TRIMOVF                  CRS_ISR_TRIMOVF                         ///< Trimming overflow or underflow
+#define CRS_IT_SYNCERR                  CRS_ISR_SYNCERR                         ///< SYNC error
+#define CRS_IT_SYNCMISS                 CRS_ISR_SYNCMISS                        ///< SYNC missed
+
+#define CRS_FLAG_SYNCOK                 CRS_ISR_SYNCOKF                         ///< SYNC event OK
+#define CRS_FLAG_SYNCWARN               CRS_ISR_SYNCWARNF                       ///< SYNC warning
+#define CRS_FLAG_ERR                    CRS_ISR_ERRF                            ///< error
+#define CRS_FLAG_ESYNC                  CRS_ISR_ESYNCF                          ///< Expected SYNC
+#define CRS_FLAG_TRIMOVF                CRS_ISR_TRIMOVF                         ///< Trimming overflow or underflow
+#define CRS_FLAG_SYNCERR                CRS_ISR_SYNCERR                         ///< SYNC error
+#define CRS_FLAG_SYNCMISS               CRS_ISR_SYNCMISS                        ///< SYNC missed
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+#define  DIV_UNSIGN                     DIV_CR_USIGN                            ///< Unsigned enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+#define DMA_CCR_MEM2MEM                 DMA_CCR_M2M
+
+#define DMA_CCR1_EN                     DMA_CCR_EN
+#define DMA_CCR1_DIR                    DMA_CCR_DIR
+#define DMA_CCR1_CIRC                   DMA_CCR_CIRC
+#define DMA_CCR1_PINC                   DMA_CCR_PINC
+#define DMA_CCR1_MINC                   DMA_CCR_MINC
+#define DMA_CCR1_PSIZE_0                DMA_CCR_PSIZE_0
+#define DMA_CCR1_MSIZE_0                DMA_CCR_MSIZE_0
+#define DMA_CCR1_PL_0                   DMA_CCR_PL_0
+#define DMA_CCR1_PSIZE_1                DMA_CCR_PSIZE_1
+#define DMA_CCR1_MSIZE_1                DMA_CCR_MSIZE_1
+#define DMA_CCR1_PL_1                   DMA_CCR_PL_1
+#define DMA_CCR1_MEM2MEM                DMA_CCR_M2M
+#define DMA_CCR1_TCIE                   DMA_CCR_TCIE
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_IMR_MR0                    EXTI_IMR_0
+#define EXTI_IMR_MR1                    EXTI_IMR_1
+#define EXTI_IMR_MR2                    EXTI_IMR_2
+#define EXTI_IMR_MR3                    EXTI_IMR_3
+#define EXTI_IMR_MR4                    EXTI_IMR_4
+#define EXTI_IMR_MR5                    EXTI_IMR_5
+#define EXTI_IMR_MR6                    EXTI_IMR_6
+#define EXTI_IMR_MR7                    EXTI_IMR_7
+#define EXTI_IMR_MR8                    EXTI_IMR_8
+#define EXTI_IMR_MR9                    EXTI_IMR_9
+#define EXTI_IMR_MR10                   EXTI_IMR_10
+#define EXTI_IMR_MR11                   EXTI_IMR_11
+#define EXTI_IMR_MR12                   EXTI_IMR_12
+#define EXTI_IMR_MR13                   EXTI_IMR_13
+#define EXTI_IMR_MR14                   EXTI_IMR_14
+#define EXTI_IMR_MR15                   EXTI_IMR_15
+#define EXTI_IMR_MR16                   EXTI_IMR_16
+
+#define EXTI_EMR_MR0                    EXTI_EMR_0
+#define EXTI_EMR_MR1                    EXTI_EMR_1
+#define EXTI_EMR_MR2                    EXTI_EMR_2
+#define EXTI_EMR_MR3                    EXTI_EMR_3
+#define EXTI_EMR_MR4                    EXTI_EMR_4
+#define EXTI_EMR_MR5                    EXTI_EMR_5
+#define EXTI_EMR_MR6                    EXTI_EMR_6
+#define EXTI_EMR_MR7                    EXTI_EMR_7
+#define EXTI_EMR_MR8                    EXTI_EMR_8
+#define EXTI_EMR_MR9                    EXTI_EMR_9
+#define EXTI_EMR_MR10                   EXTI_EMR_10
+#define EXTI_EMR_MR11                   EXTI_EMR_11
+#define EXTI_EMR_MR12                   EXTI_EMR_12
+#define EXTI_EMR_MR13                   EXTI_EMR_13
+#define EXTI_EMR_MR14                   EXTI_EMR_14
+#define EXTI_EMR_MR15                   EXTI_EMR_15
+#define EXTI_EMR_MR16                   EXTI_EMR_16
+
+#define EXTI_RTSR_TR0                   EXTI_RTSR_0
+#define EXTI_RTSR_TR1                   EXTI_RTSR_1
+#define EXTI_RTSR_TR2                   EXTI_RTSR_2
+#define EXTI_RTSR_TR3                   EXTI_RTSR_3
+#define EXTI_RTSR_TR4                   EXTI_RTSR_4
+#define EXTI_RTSR_TR5                   EXTI_RTSR_5
+#define EXTI_RTSR_TR6                   EXTI_RTSR_6
+#define EXTI_RTSR_TR7                   EXTI_RTSR_7
+#define EXTI_RTSR_TR8                   EXTI_RTSR_8
+#define EXTI_RTSR_TR9                   EXTI_RTSR_9
+#define EXTI_RTSR_TR10                  EXTI_RTSR_10
+#define EXTI_RTSR_TR11                  EXTI_RTSR_11
+#define EXTI_RTSR_TR12                  EXTI_RTSR_12
+#define EXTI_RTSR_TR13                  EXTI_RTSR_13
+#define EXTI_RTSR_TR14                  EXTI_RTSR_14
+#define EXTI_RTSR_TR15                  EXTI_RTSR_15
+#define EXTI_RTSR_TR16                  EXTI_RTSR_16
+
+#define EXTI_FTSR_TR0                   EXTI_FTSR_0
+#define EXTI_FTSR_TR1                   EXTI_FTSR_1
+#define EXTI_FTSR_TR2                   EXTI_FTSR_2
+#define EXTI_FTSR_TR3                   EXTI_FTSR_3
+#define EXTI_FTSR_TR4                   EXTI_FTSR_4
+#define EXTI_FTSR_TR5                   EXTI_FTSR_5
+#define EXTI_FTSR_TR6                   EXTI_FTSR_6
+#define EXTI_FTSR_TR7                   EXTI_FTSR_7
+#define EXTI_FTSR_TR8                   EXTI_FTSR_8
+#define EXTI_FTSR_TR9                   EXTI_FTSR_9
+#define EXTI_FTSR_TR10                  EXTI_FTSR_10
+#define EXTI_FTSR_TR11                  EXTI_FTSR_11
+#define EXTI_FTSR_TR12                  EXTI_FTSR_12
+#define EXTI_FTSR_TR13                  EXTI_FTSR_13
+#define EXTI_FTSR_TR14                  EXTI_FTSR_14
+#define EXTI_FTSR_TR15                  EXTI_FTSR_15
+#define EXTI_FTSR_TR16                  EXTI_FTSR_16
+
+#define EXTI_SWIER_SWIER0               EXTI_SWIER_0
+#define EXTI_SWIER_SWIER1               EXTI_SWIER_1
+#define EXTI_SWIER_SWIER2               EXTI_SWIER_2
+#define EXTI_SWIER_SWIER3               EXTI_SWIER_3
+#define EXTI_SWIER_SWIER4               EXTI_SWIER_4
+#define EXTI_SWIER_SWIER5               EXTI_SWIER_5
+#define EXTI_SWIER_SWIER6               EXTI_SWIER_6
+#define EXTI_SWIER_SWIER7               EXTI_SWIER_7
+#define EXTI_SWIER_SWIER8               EXTI_SWIER_8
+#define EXTI_SWIER_SWIER9               EXTI_SWIER_9
+#define EXTI_SWIER_SWIER10              EXTI_SWIER_10
+#define EXTI_SWIER_SWIER11              EXTI_SWIER_11
+#define EXTI_SWIER_SWIER12              EXTI_SWIER_12
+#define EXTI_SWIER_SWIER13              EXTI_SWIER_13
+#define EXTI_SWIER_SWIER14              EXTI_SWIER_14
+#define EXTI_SWIER_SWIER15              EXTI_SWIER_15
+#define EXTI_SWIER_SWIER16              EXTI_SWIER_16
+
+#define EXTI_PR_PR0                     EXTI_PR_0
+#define EXTI_PR_PR1                     EXTI_PR_1
+#define EXTI_PR_PR2                     EXTI_PR_2
+#define EXTI_PR_PR3                     EXTI_PR_3
+#define EXTI_PR_PR4                     EXTI_PR_4
+#define EXTI_PR_PR5                     EXTI_PR_5
+#define EXTI_PR_PR6                     EXTI_PR_6
+#define EXTI_PR_PR7                     EXTI_PR_7
+#define EXTI_PR_PR8                     EXTI_PR_8
+#define EXTI_PR_PR9                     EXTI_PR_9
+#define EXTI_PR_PR10                    EXTI_PR_10
+#define EXTI_PR_PR11                    EXTI_PR_11
+#define EXTI_PR_PR12                    EXTI_PR_12
+#define EXTI_PR_PR13                    EXTI_PR_13
+#define EXTI_PR_PR14                    EXTI_PR_14
+#define EXTI_PR_PR15                    EXTI_PR_15
+#define EXTI_PR_PR16                    EXTI_PR_16
+
+#define EXTI_IMR_MR17                   EXTI_IMR_17
+
+#define EXTI_IMR_MR18                   EXTI_IMR_18
+
+#define EXTI_IMR_MR19                   EXTI_IMR_19
+
+#define EXTI_IMR_MR20                   EXTI_IMR_20
+
+#define EXTI_IMR_MR21                   EXTI_IMR_21
+
+
+#define EXTI_IMR_MR24                   EXTI_IMR_24
+
+#define EXTI_EMR_MR17                   EXTI_EMR_17
+
+#define EXTI_EMR_MR18                   EXTI_EMR_18
+
+#define EXTI_EMR_MR19                   EXTI_EMR_19
+
+#define EXTI_EMR_MR20                   EXTI_EMR_20
+
+#define EXTI_EMR_MR21                   EXTI_EMR_21
+
+
+#define EXTI_EMR_MR24                   EXTI_EMR_24
+
+#define EXTI_RTSR_MR17                  EXTI_RTSR_17
+
+#define EXTI_RTSR_MR18                  EXTI_RTSR_18
+
+#define EXTI_RTSR_MR19                  EXTI_RTSR_19
+
+#define EXTI_RTSR_MR20                  EXTI_RTSR_20
+
+#define EXTI_RTSR_MR21                  EXTI_RTSR_21
+
+
+#define EXTI_RTSR_MR24                  EXTI_RTSR_24
+
+#define EXTI_FTSR_MR17                  EXTI_FTSR_18
+
+#define EXTI_FTSR_MR18                  EXTI_FTSR_18
+
+#define EXTI_FTSR_MR19                  EXTI_FTSR_19
+
+#define EXTI_FTSR_MR20                  EXTI_FTSR_20
+
+#define EXTI_FTSR_MR21                  EXTI_FTSR_21
+
+
+#define EXTI_FTSR_MR24                  EXTI_FTSR_24
+
+#define EXTI_SWIER_MR17                 EXTI_SWIER_17
+
+#define EXTI_SWIER_MR18                 EXTI_SWIER_18
+
+#define EXTI_SWIER_MR19                 EXTI_SWIER_19
+
+#define EXTI_SWIER_MR20                 EXTI_SWIER_20
+
+#define EXTI_SWIER_MR21                 EXTI_SWIER_21
+
+
+#define EXTI_SWIER_MR24                 EXTI_SWIER_24
+
+#define EXTI_PR_MR17                    EXTI_PR_17
+
+#define EXTI_PR_MR18                    EXTI_PR_18
+
+#define EXTI_PR_MR19                    EXTI_PR_19
+
+#define EXTI_PR_MR20                    EXTI_PR_20
+
+#define EXTI_PR_MR21                    EXTI_PR_21
+
+
+#define EXTI_PR_MR24                    EXTI_PR_24
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define GPIO_Mode_IN_FLOATING           GPIO_Mode_FLOATING
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+//Bit
+#define I2C_CON_MASTER_MODE             I2C_CR_MASTER
+#define I2C_CON_SPEED                   I2C_CR_SPEED
+#define I2C_CON_SPEED_STANDARD          I2C_CR_STD
+#define I2C_CON_SPEED_FAST              I2C_CR_FAST
+#define I2C_CON_10BITADDR_SLAVE         I2C_CR_SLAVE10
+#define I2C_CON_10BITADDR_MASTER        I2C_CR_MASTER10
+#define I2C_CON_RESTART_EN              I2C_CR_REPEN
+#define I2C_CON_SLAVE_DISABLE           I2C_CR_SLAVEDIS
+#define I2C_CON_STOP_DET_IFADDRESSED    I2C_CR_STOPINT
+#define I2C_CON_EMPTY_CTRL              I2C_CR_EMPINT
+#define I2C_CON_STOP                    I2C_CR_STOP
+#define I2C_CON_RESTART                 I2C_CR_RESTART
+
+#define I2C_TAR_TAR                     I2C_TAR_ADDR
+#define I2C_TAR_GC_OR_START             I2C_TAR_GC
+#define I2C_SAR_SAR                     I2C_SAR_ADDR
+#define I2C_DATA_CMD_DAT                I2C_DR_DAT
+#define I2C_DATA_CMD_CMD                I2C_DR_CMD
+#define I2C_DATA_CMD_STOP               I2C_DR_STOP
+#define I2C_DATA_CMD_RESTART            I2C_DR_RESTART
+
+#define I2C_SS_SCL_HCNT                 I2C_SSHR_CNT
+#define I2C_SS_SCL_LCNT                 I2C_SSLR_CNT
+#define I2C_FS_SCL_HCNT                 I2C_FSHR_CNT
+#define I2C_FS_SCL_LCNT                 I2C_FSLR_CNT
+
+#define I2C_INTR_STAT_RX_UNDER          I2C_ISR_RX_UNDER
+#define I2C_INTR_STAT_RX_OVER           I2C_ISR_RX_OVER
+#define I2C_INTR_STAT_RX_FULL           I2C_ISR_RX_FULL
+#define I2C_INTR_STAT_TX_OVER           I2C_ISR_TX_OVER
+#define I2C_INTR_STAT_TX_EMPTY          I2C_ISR_TX_EMPTY
+#define I2C_INTR_STAT_RX_REQ            I2C_ISR_RX_REQ
+#define I2C_INTR_STAT_TX_ABRT           I2C_ISR_TX_ABRT
+#define I2C_INTR_STAT_RX_DONE           I2C_ISR_RX_DONE
+#define I2C_INTR_STAT_ACTIVITY          I2C_ISR_ACTIV
+#define I2C_INTR_STAT_STOP_DET          I2C_ISR_STOP
+#define I2C_INTR_STAT_START_DET         I2C_ISR_START
+#define I2C_INTR_STAT_GEN_CALL          I2C_ISR_GC
+#define I2C_INTR_STAT_RESTART_DET       I2C_ISR_RESTART
+#define I2C_INTR_STAT_MST_ON_HOLD       I2C_ISR_HOLD
+
+#define I2C_INTR_MASK_RX_UNDER          I2C_IMR_RX_UNDER
+#define I2C_INTR_MASK_RX_OVER           I2C_IMR_RX_OVER
+#define I2C_INTR_MASK_RX_FULL           I2C_IMR_RX_FULL
+#define I2C_INTR_MASK_TX_OVER           I2C_IMR_TX_OVER
+#define I2C_INTR_MASK_TX_EMPTY          I2C_IMR_TX_EMPTY
+#define I2C_INTR_MASK_RX_REQ            I2C_IMR_RX_REQ
+#define I2C_INTR_MASK_TX_ABRT           I2C_IMR_TX_ABRT
+#define I2C_INTR_MASK_RX_DONE           I2C_IMR_RX_DONE
+#define I2C_INTR_MASK_ACTIVITY          I2C_IMR_ACTIV
+#define I2C_INTR_MASK_STOP_DET          I2C_IMR_STOP
+#define I2C_INTR_MASK_START_DET         I2C_IMR_START
+#define I2C_INTR_MASK_GEN_CALL          I2C_IMR_GC
+#define I2C_INTR_MASK_RESTART_DET       I2C_IMR_RESTART
+#define I2C_INTR_MASK_MST_ON_HOLD       I2C_IMR_HOLD
+
+#define I2C_RAW_INTR_MASK_RX_UNDER      I2C_RAWISR_RX_UNDER
+#define I2C_RAW_INTR_MASK_RX_OVER       I2C_RAWISR_RX_OVER
+#define I2C_RAW_INTR_MASK_RX_FULL       I2C_RAWISR_RX_FULL
+#define I2C_RAW_INTR_MASK_TX_OVER       I2C_RAWISR_TX_OVER
+#define I2C_RAW_INTR_MASK_TX_EMPTY      I2C_RAWISR_TX_EMPTY
+#define I2C_RAW_INTR_MASK_RX_REQ        I2C_RAWISR_RX_REQ
+#define I2C_RAW_INTR_MASK_TX_ABRT       I2C_RAWISR_TX_ABRT
+#define I2C_RAW_INTR_MASK_RX_DONE       I2C_RAWISR_RX_DONE
+#define I2C_RAW_INTR_MASK_ACTIVITY      I2C_RAWISR_ACTIV
+#define I2C_RAW_INTR_MASK_STOP_DET      I2C_RAWISR_STOP
+#define I2C_RAW_INTR_MASK_START_DET     I2C_RAWISR_START
+#define I2C_RAW_INTR_MASK_GEN_CALL      I2C_RAWISR_GC
+#define I2C_RAW_INTR_MASK_RESTART_DET   I2C_RAWISR_RESTART
+#define I2C_RAW_INTR_MASK_MST_ON_HOLD   I2C_RAWISR_HOLD
+
+#define I2C_RX_TL                       I2C_RXTLR_TL
+#define I2C_TX_TL                       I2C_TXTLR_TL
+
+#define I2C_CLR_INTR                    I2C_ICR
+#define I2C_CLR_RX_UNDER                I2C_RX_UNDER
+#define I2C_CLR_RX_OVER                 I2C_RX_OVER
+#define I2C_CLR_TX_OVER                 I2C_TX_OVER
+#define I2C_RX_REQ                      I2C_RD_REQ
+#define I2C_CLR_RX_REQ                  I2C_RD_REQ
+#define I2C_CLR_TX_ABRT                 I2C_TX_ABRT
+#define I2C_CLR_RX_DONE                 I2C_RX_DONE
+#define I2C_CLR_ACTIVITY                I2C_ACTIV
+#define I2C_CLR_STOP_DET                I2C_STOP
+#define I2C_CLR_START_DET               I2C_START
+#define I2C_CLR_GEN_CALL                I2C_GC
+
+#define I2C_ENABLE_ENABLE               I2C_ENR_ENABLE
+#define I2C_ENABLE_ABORT                I2C_ENR_ABORT
+
+#define I2C_STATUS_ACTIVITY             I2C_SR_ACTIV
+#define I2C_STATUS_TFNF                 I2C_SR_TFNF
+#define I2C_STATUS_TFE                  I2C_SR_TFE
+#define I2C_STATUS_RFNE                 I2C_SR_RFNE
+#define I2C_STATUS_RFF                  I2C_SR_RFF
+#define I2C_STATUS_MST_ACTIVITY         I2C_SR_MST_ACTIV
+#define I2C_STATUS_SLV_ACTIVITY         I2C_SR_SLV_ACTIV
+
+#define I2C_TXFLR                       I2C_TXFLR_CNT
+#define I2C_RXFLR                       I2C_RXFLR_CNT
+
+#define I2C_SDA_TX_HOLD                 I2C_HOLD_TXCNT
+#define I2C_SDA_RX_HOLD                 I2C_HOLD_RXCNT
+#define I2C_DMA_CR_RDMAE                I2C_DMA_RXEN
+#define I2C_DMA_CR_TDMAE                I2C_DMA_TXEN
+#define I2C_SDA_SET_UP                  I2C_SETUP_CNT
+#define I2C_ACK_GENERAL_CALL            I2C_GCR_GC
+
+
+#define IWDG_PR_PR                      IWDG_PR_PRE
+#define IWDG_PR_PR_DIV4                 IWDG_PR_PRE_DIV4
+#define IWDG_PR_PR_DIV8                 IWDG_PR_PRE_DIV8
+#define IWDG_PR_PR_DIV16                IWDG_PR_PRE_DIV16
+#define IWDG_PR_PR_DIV32                IWDG_PR_PRE_DIV32
+#define IWDG_PR_PR_DIV64                IWDG_PR_PRE_DIV64
+#define IWDG_PR_PR_DIV128               IWDG_PR_PRE_DIV128
+#define IWDG_PR_PR_DIV256               IWDG_PR_PRE_DIV256
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHBENR_DMAEN                RCC_AHBENR_DMA1
+#define RCC_AHBENR_DMA1EN               RCC_AHBENR_DMA1
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup AHB_peripheral
+/// @{
+#define RCC_AHBPeriph_DMA1              RCC_AHBENR_DMA1
+#define RCC_AHBPeriph_SRAM              RCC_AHBENR_SRAM
+#define RCC_AHBPeriph_FLITF             RCC_AHBENR_FLITF
+#define RCC_AHBPeriph_CRC               RCC_AHBENR_CRC
+#define RCC_AHBPeriph_AES               RCC_AHBENR_AES
+#define RCC_AHBPeriph_GPIOA             RCC_AHBENR_GPIOA
+#define RCC_AHBPeriph_GPIOB             RCC_AHBENR_GPIOB
+#define RCC_AHBPeriph_GPIOC             RCC_AHBENR_GPIOC
+#define RCC_AHBPeriph_GPIOD             RCC_AHBENR_GPIOD
+
+
+#define RCC_AHBPeriph_GPIOE             RCC_AHBENR_GPIOE
+#define RCC_AHBPeriph_HIV               RCC_AHBENR_HWDIV
+#define RCC_AHBPeriph_HWDIV             RCC_AHBENR_HWDIV
+
+
+
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup APB2_peripheral
+/// @{
+#define RCC_APB2Periph_ADC1             RCC_APB2ENR_ADC1
+#define RCC_APB2Periph_TIM1             RCC_APB2ENR_TIM1
+#define RCC_APB2Periph_SPI1             RCC_APB2ENR_SPI1
+#define RCC_APB2Periph_UART1            RCC_APB2ENR_UART1
+#define RCC_APB2Periph_COMP             RCC_APB2ENR_COMP
+#define RCC_APB2Periph_DBGMCU           RCC_APB2ENR_DBGMCU
+
+#define RCC_APB2ENR_ADC1EN              RCC_APB2ENR_ADC1
+#define RCC_APB2ENR_TIM1EN              RCC_APB2ENR_TIM1
+#define RCC_APB2RSTR_ADC1RST            RCC_APB2RSTR_ADC1
+
+#define RCC_APB2Periph_ADC2             RCC_APB2ENR_ADC2
+#define RCC_APB2Periph_ADC3             RCC_APB2ENR_ADC3
+#define RCC_APB2Periph_SYSCFG           RCC_APB2ENR_SYSCFG
+#define RCC_APB2Periph_EXTI             RCC_APB2ENR_EXTI
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+/// @defgroup APB1_peripheral
+/// @{
+#define RCC_APB1Periph_TIM2             RCC_APB1ENR_TIM2
+#define RCC_APB1Periph_TIM3             RCC_APB1ENR_TIM3
+#define RCC_APB1Periph_TIM4             RCC_APB1ENR_TIM4
+#define RCC_APB1Periph_UART3            RCC_APB1ENR_UART3
+#define RCC_APB1Periph_BKP              RCC_APB1ENR_BKP
+#define RCC_APB1Periph_DAC              RCC_APB1ENR_DAC
+#define RCC_APB1Periph_I2C2             RCC_APB1ENR_I2C2
+#define RCC_APB1Periph_ALL              0x3AE64807
+#define RCC_APB1Periph_CAN1             RCC_APB1ENR_CAN
+#define RCC_APB1Periph_CRS              RCC_APB1ENR_CRS
+#define RCC_APB1Periph_UART2            RCC_APB1ENR_UART2
+#define RCC_APB1Periph_I2C1             RCC_APB1ENR_I2C1
+#define RCC_APB1Periph_SPI2             RCC_APB1ENR_SPI2
+#define RCC_APB1Periph_WWDG             RCC_APB1ENR_WWDG
+#define RCC_APB1Periph_PWR              RCC_APB1ENR_PWR
+
+#define RCC_APB1ENR_PWREN               RCC_APB1ENR_PWR
+#define RCC_APB1ENR_TIM2EN              RCC_APB1ENR_TIM2
+#define RCC_APB1ENR_TIM3EN              RCC_APB1ENR_TIM3
+#define RCC_APB1ENR_SYSCFG              RCC_APB1ENR_EXTI
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CRH_SECIE_Pos               RTC_CR_SECIE_Pos
+#define RTC_CRH_SECIE                   RTC_CR_SECIE                  ///< Second Interrupt Enable
+#define RTC_CRH_ALRIE_Pos               RTC_CR_ALRIE_Pos
+#define RTC_CRH_ALRIE                   RTC_CR_ALRIE                  ///< Alarm Interrupt Enable
+#define RTC_CRH_OWIE_Pos                RTC_CR_OWIE_Pos
+#define RTC_CRH_OWIE                    RTC_CR_OWIE                   ///< OverfloW Interrupt Enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CRL_SECF_Pos                RTC_CSR_SECF_Pos
+#define RTC_CRL_SECF                    RTC_CSR_SECF                   ///< Second Flag
+#define RTC_CRL_ALRF_Pos                RTC_CSR_ALRF_Pos
+#define RTC_CRL_ALRF                    RTC_CSR_ALRF                   ///< Alarm Flag
+#define RTC_CRL_OWF_Pos                 RTC_CSR_OWF_Pos
+#define RTC_CRL_OWF                     RTC_CSR_OWF                    ///< OverfloW Flag
+#define RTC_CRL_RSF_Pos                 RTC_CSR_RSF_Pos
+#define RTC_CRL_RSF                     RTC_CSR_RSF                    ///< Registers Synchronized Flag
+#define RTC_CRL_CNF_Pos                 RTC_CSR_CNF_Pos
+#define RTC_CRL_CNF                     RTC_CSR_CNF                    ///< Configuration Flag
+#define RTC_CRL_RTOFF_Pos               RTC_CSR_RTOFF_Pos
+#define RTC_CRL_RTOFF                   RTC_CSR_RTOFF                  ///< RTC operation OFF
+#define RTC_CRL_ALPEN_Pos               RTC_CSR_ALPEN_Pos
+#define RTC_CRL_ALPEN                   RTC_CSR_ALPEN                  ///< RTC Alarm Loop Enable
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Version compatibility definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_TXREG_TXREG                 SPI_TDR_TXREG
+#define SPI_RXREG_RXREG                 SPI_RDR_RXREG
+
+#define SPI_CSTAT_TXEPT                 SPI_SR_TXEPT
+#define SPI_CSTAT_RXAVL                 SPI_SR_RXAVL
+#define SPI_CSTAT_TXFULL                SPI_SR_TXFULL
+#define SPI_CSTAT_RXAVL_4BYTE           SPI_SR_RXAVL_4BYTE
+#define SPI_CSTAT_TXFADDR               SPI_SR_TXFADDR
+#define SPI_CSTAT_RXFADDR               SPI_SR_RXFADDR
+
+#define SPI_INTSTAT_TX_INTF             SPI_ISR_TX_INTF
+#define SPI_INTSTAT_RX_INTF             SPI_ISR_RX_INTF
+#define SPI_INTSTAT_UNDERRUN_INTF       SPI_ISR_UNDERRUN_INTF
+#define SPI_INTSTAT_RXOERR_INTF         SPI_ISR_RXOERR_INTF
+#define SPI_INTSTAT_RXMATCH_INTF        SPI_ISR_RXMATCH_INTF
+#define SPI_INTSTAT_RXFULL_INTF         SPI_ISR_RXFULL_INTF
+#define SPI_INTSTAT_TXEPT_INTF          SPI_ISR_TXEPT_INTF
+
+#define SPI_INTEN_TX_IEN                SPI_IER_TX_IEN
+#define SPI_INTEN_RX_IEN                SPI_IER_RX_IEN
+#define SPI_INTEN_UNDERRUN_IEN          SPI_IER_UNDERRUN_IEN
+#define SPI_INTEN_RXOERR_IEN            SPI_IER_RXOERR_IEN
+#define SPI_INTEN_RXMATCH_IEN           SPI_IER_RXMATCH_IEN
+#define SPI_INTEN_RXFULL_IEN            SPI_IER_RXFULL_IEN
+#define SPI_INTEN_TXEPT_IEN             SPI_IER_TXEPT_IEN
+
+#define SPI_INTCLR_TX_ICLR              SPI_ICR_TX_ICLR
+#define SPI_INTCLR_RX_ICLR              SPI_ICR_RX_ICLR
+#define SPI_INTCLR_UNDERRUN_ICLR        SPI_ICR_UNDERRUN_ICLR
+#define SPI_INTCLR_RXOERR_ICLR          SPI_ICR_RXOERR_ICLR
+#define SPI_INTCLR_RXMATCH_ICLR         SPI_ICR_RXMATCH_ICLR
+#define SPI_INTCLR_RXFULL_ICLR          SPI_ICR_RXFULL_ICLR
+#define SPI_INTCLR_TXEPT_ICLR           SPI_ICR_TXEPT_ICLR
+
+#define SPI_GCTL_SPIEN                  SPI_GCR_SPIEN
+#define SPI_GCTL_INT_EN                 SPI_GCR_IEN
+#define SPI_GCTL_MM                     SPI_GCR_MODE
+#define SPI_GCTL_TXEN                   SPI_GCR_TXEN
+#define SPI_GCTL_RXEN                   SPI_GCR_RXEN
+
+#define SPI_GCTL_RXTLF                  SPI_GCR_RXTLF
+#define SPI_GCTL_RXTLF_One              SPI_GCR_RXTLF_One
+#define SPI_GCTL_RXTLF_Half             SPI_GCR_RXTLF_Half
+
+#define SPI_GCTL_TXTLF_Pos              SPI_GCR_TXTLF_Pos
+#define SPI_GCTL_TXTLF                  SPI_GCR_TXTLF
+#define SPI_GCTL_TXTLF_One              SPI_GCR_TXTLF_One
+#define SPI_GCTL_TXTLF_Half             SPI_GCR_TXTLF_Half
+#define SPI_GCTL_DMAEN                  SPI_GCR_DMAEN
+#define SPI_GCTL_NSS_SEL                SPI_GCR_NSS
+#define SPI_GCTL_DATA_SEL               SPI_GCR_DWSEL
+
+#define SPI_GCTL_NSSTOG                 SPI_GCR_NSSTOG
+
+#define SPI_CCTL_CPHA                   SPI_CCR_CPHA
+#define SPI_CCTL_CPOL                   SPI_CCR_CPOL
+#define SPI_CCTL_LSBFE                  SPI_CCR_LSBFE
+#define SPI_CCTL_SPILEN                 SPI_CCR_SPILEN
+#define SPI_CCTL_RXEDGE                 SPI_CCR_RXEDGE
+#define SPI_CCTL_TXEDGE                 SPI_CCR_TXEDGE
+
+#define SPI_CCTL_CPHASEL                SPI_CCR_CPHASEL
+
+#define SPI_CCTL_HISPD                  SPI_CCR_HISPD
+
+#define SPI_SPBRG_SPBRG                 SPI_BRR_DIVF
+
+#define SPI_RXDNR_RXDNR                 SPI_RDNR_RDN
+
+#define SPI_EXTCTL_EXTLEN               SPI_ECR_EXTLEN
+#define TIM_CR1_ARPE                    TIM_CR1_ARPEN
+
+#define TIM_SMCR_ECE                    TIM_SMCR_ECEN
+
+#define TIM_DIER_UIE                    TIM_DIER_UI
+#define TIM_DIER_CC1IE                  TIM_DIER_CC1I
+#define TIM_DIER_CC2IE                  TIM_DIER_CC2I
+#define TIM_DIER_CC3IE                  TIM_DIER_CC3I
+#define TIM_DIER_CC4IE                  TIM_DIER_CC4I
+#define TIM_DIER_COMIE                  TIM_DIER_COMI
+#define TIM_DIER_TIE                    TIM_DIER_TI
+#define TIM_DIER_BIE                    TIM_DIER_BI
+#define TIM_DIER_UDE                    TIM_DIER_UD
+#define TIM_DIER_CC1DE                  TIM_DIER_CC1D
+#define TIM_DIER_CC2DE                  TIM_DIER_CC2D
+#define TIM_DIER_CC3DE                  TIM_DIER_CC3D
+#define TIM_DIER_CC4DE                  TIM_DIER_CC4D
+#define TIM_DIER_COMDE                  TIM_DIER_COMD
+#define TIM_DIER_TDE                    TIM_DIER_TD
+
+#define TIM_DIER_UIEN                   TIM_DIER_UI
+#define TIM_DIER_CC1IEN                 TIM_DIER_CC1I
+#define TIM_DIER_CC2IEN                 TIM_DIER_CC2I
+#define TIM_DIER_CC3IEN                 TIM_DIER_CC3I
+#define TIM_DIER_CC4IEN                 TIM_DIER_CC4I
+#define TIM_DIER_COMIEN                 TIM_DIER_COMI
+#define TIM_DIER_TIEN                   TIM_DIER_TI
+#define TIM_DIER_BIEN                   TIM_DIER_BI
+#define TIM_DIER_UDEN                   TIM_DIER_UD
+#define TIM_DIER_CC1DEN                 TIM_DIER_CC1D
+#define TIM_DIER_CC2DEN                 TIM_DIER_CC2D
+#define TIM_DIER_CC3DEN                 TIM_DIER_CC3D
+#define TIM_DIER_CC4DEN                 TIM_DIER_CC4D
+#define TIM_DIER_COMDEN                 TIM_DIER_COMD
+#define TIM_DIER_TDEN                   TIM_DIER_TD
+
+#define TIM_DIER_CC5IE                  TIM_DIER_CC5I
+#define TIM_DIER_CC5DE                  TIM_DIER_CC5D
+
+#define TIM_SR_UIF                      TIM_SR_UI
+#define TIM_SR_CC1IF                    TIM_SR_CC1I
+#define TIM_SR_CC2IF                    TIM_SR_CC2I
+#define TIM_SR_CC3IF                    TIM_SR_CC3I
+#define TIM_SR_CC4IF                    TIM_SR_CC4I
+#define TIM_SR_COMIF                    TIM_SR_COMI
+#define TIM_SR_TIF                      TIM_SR_TI
+#define TIM_SR_BIF                      TIM_SR_BI
+#define TIM_SR_CC1OF                    TIM_SR_CC1O
+#define TIM_SR_CC2OF                    TIM_SR_CC2O
+#define TIM_SR_CC3OF                    TIM_SR_CC3O
+#define TIM_SR_CC4OF                    TIM_SR_CC4O
+
+#define TIM_SR_CC5IF                    TIM_SR_CC5I
+
+#define TIM_CCMR1_OC1FE                 TIM_CCMR1_OC1FEN
+#define TIM_CCMR1_OC1PE                 TIM_CCMR1_OC1PEN
+#define TIM_CCMR1_OC1CE                 TIM_CCMR1_OC1CEN
+#define TIM_CCMR1_OC2FE                 TIM_CCMR1_OC2FEN
+#define TIM_CCMR1_OC2PE                 TIM_CCMR1_OC2PEN
+#define TIM_CCMR1_OC2CE                 TIM_CCMR1_OC2CEN
+
+#define TIM_CCMR2_OC3FE                 TIM_CCMR2_OC3FEN
+#define TIM_CCMR2_OC3PE                 TIM_CCMR2_OC3PEN
+#define TIM_CCMR2_OC3CE                 TIM_CCMR2_OC3CEN
+#define TIM_CCMR2_OC4FE                 TIM_CCMR2_OC4FEN
+#define TIM_CCMR2_OC4PE                 TIM_CCMR2_OC4PEN
+#define TIM_CCMR2_OC4CE                 TIM_CCMR2_OC4CEN
+
+#define TIM_CCER_CC1E                   TIM_CCER_CC1EN
+#define TIM_CCER_CC1NE                  TIM_CCER_CC1NEN
+#define TIM_CCER_CC2E                   TIM_CCER_CC2EN
+#define TIM_CCER_CC2NE                  TIM_CCER_CC2NEN
+#define TIM_CCER_CC3E                   TIM_CCER_CC3EN
+#define TIM_CCER_CC3NE                  TIM_CCER_CC3NEN
+#define TIM_CCER_CC4E                   TIM_CCER_CC4EN
+
+#define TIM_CCER_CC5E                   TIM_CCER_CC5EN
+
+#define TIM_BDTR_BKE                    TIM_BDTR_BKEN
+#define TIM_BDTR_AOE                    TIM_BDTR_AOEN
+#define TIM_BDTR_MOE                    TIM_BDTR_MOEN
+
+#define TIM_BDTR_DOE                    TIM_BDTR_DOEN
+
+#define TIM_CCMR3_OC5FE                 TIM_CCMR3_OC5FEN
+#define TIM_CCMR3_OC5PE                 TIM_CCMR3_OC5PEN
+#define TIM_CCMR3_OC5CE                 TIM_CCMR3_OC5CEN
+#define UART_TDR_TXREG                  UART_TDR_DATA
+#define UART_RDR_RXREG                  UART_RDR_DATA
+
+#define UART_ISR_TX_INTF                UART_ISR_TX
+#define UART_ISR_RX_INTF                UART_ISR_RX
+#define UART_ISR_RXOERR_INTF            UART_ISR_RXOERR
+#define UART_ISR_RXPERR_INTF            UART_ISR_RXPERR
+#define UART_ISR_RXFERR_INTF            UART_ISR_RXFERR
+#define UART_ISR_RXBRK_INTF             UART_ISR_RXBRK
+
+#define UART_IER_TXIEN                  UART_IER_TX
+#define UART_IER_RXIEN                  UART_IER_RXI
+#define UART_IER_RXOERREN               UART_IER_RXOERR
+#define UART_IER_RXPERREN               UART_IER_RXPERR
+#define UART_IER_RXFERREN               UART_IER_RXFERR
+#define UART_IER_RXBRKEN                UART_IER_RXBRK
+
+#define UART_ICR_TXICLR                 UART_ICR_TX
+#define UART_ICR_RXICLR                 UART_ICR_RX
+#define UART_ICR_RXOERRCLR              UART_ICR_RXOERR
+#define UART_ICR_RXPERRCLR              UART_ICR_RXPERR
+#define UART_ICR_RXFERRCLR              UART_ICR_RXFERR
+#define UART_ICR_RXBRKCLR               UART_ICR_RXBRK
+
+#define UART_Mode_Rx                    UART_GCR_RX
+#define UART_Mode_Tx                    UART_GCR_TX
+#define UART_EN                         UART_GCR_UART
+#define UART_IT_RXBRK                   UART_IER_RXBRK
+#define UART_IT_ERR                     UART_IER_RXFERR
+#define UART_IT_PE                      UART_IER_RXPERR
+#define UART_OVER_ERR                   UART_IER_RXOERR
+#define UART_IT_RXIEN                   UART_IER_RX
+#define UART_IT_TXIEN                   UART_IER_TX
+
+#define UART_HardwareFlowControl_None   UART_HWFlowControl_None
+
+#define UART_BRR_DIV_MANTISSA           UART_BRR_MANTISSA
+#define UART_BRR_DIV_FRACTION           UART_BRR_FRACTION
+
+#define UART_ISR_TXC_INTF               UART_ISR_TXC
+#define UART_ISR_TXBRK_INTF             UART_ISR_TXBRK
+#define UART_ISR_RXB8_INTF              UART_ISR_RXB8
+
+#define UART_IT_RXB8                    UART_IER_RXB8
+#define UART_IT_TXBRK                   UART_IER_TXBRK
+#define UART_IT_TXCIEN                  UART_IER_TXC
+#define UART_ICR_TXCCLR                 UART_ICR_TXC
+#define UART_ICR_TXBRKCLR               UART_ICR_TXBRK
+#define UART_ICR_RXB8CLR                UART_ICR_RXB8
+#define UART_SCR_SCAEN                  UART_SCR_SCARB
+#define UART_DMAReq_EN                  UART_GCR_DMA
+#define UART_FLAG_TXEMPTY               UART_CSR_TXEPT
+#define UART_FLAG_TXFULL                UART_CSR_TXFULL
+#define UART_FLAG_RXAVL                 UART_CSR_RXAVL
+#define UART_FLAG_TXEPT                 UART_CSR_TXC
+#define WWDG_CR_T                       WWDG_CR_CNT
+
+
+#if defined(ENABLEIP_USB_OTG)
+//USB
+
+///-------------------  Bit definition for SETUP0 register  --------------------
+
+//#define SETUP0 ((u16)0x00FF)
+
+///-------------------  Bit definition for SETUP1 register  --------------------
+//#define SETUP1 ((u16)0x00FF)
+
+///-------------------  Bit definition for SETUP2 register  --------------------
+//#define SETUP2 ((u16)0x00FF)
+
+///-------------------  Bit definition for SETUP3 register  --------------------
+//#define SETUP3 ((u16)0x00FF)
+
+///-------------------  Bit definition for SETUP4 register  --------------------
+//#define SETUP4 ((u16)0x00FF)
+
+///-------------------  Bit definition for SETUP5 register  --------------------
+//#define SETUP5 ((u16)0x00FF)
+
+///-------------------  Bit definition for SETUP6 register  --------------------
+//#define SETUP6 ((u16)0x00FF)
+
+///-------------------  Bit definition for SETUP7 register  --------------------
+//#define SETUP7 ((u16)0x00FF)
+
+
+
+#define USB_TOP_STATE_0                             ((u16)0x0020)
+#define USB_TOP_STATE_1                             ((u16)0x0040)
+
+///-------------------  Bit definition for EP1_INT_STATE register  --------------------
+#define  EP1_INT_STATE_END                          ((u16)0x0002)
+#define  EP1_INT_STATE_INNACK                       ((u16)0x0004)
+#define  EP1_INT_STATE_INACK                        ((u16)0x0008)
+#define  EP1_INT_STATE_INSTALL                      ((u16)0x0010)
+#define  EP1_INT_STATE_OUTNACK                      ((u16)0x0020)
+#define  EP1_INT_STATE_OUTACK                       ((u16)0x0040)
+#define  EP1_INT_STATE_OUTSTALL                     ((u16)0x0080)
+
+///-------------------  Bit definition for EP2_INT_STATE register  --------------------
+#define  EP2_INT_STATE_END                          ((u16)0x0002)
+#define  EP2_INT_STATE_INNACK                       ((u16)0x0004)
+#define  EP2_INT_STATE_INACK                        ((u16)0x0008)
+#define  EP2_INT_STATE_INSTALL                      ((u16)0x0010)
+#define  EP2_INT_STATE_OUTNACK                      ((u16)0x0020)
+#define  EP2_INT_STATE_OUTACK                       ((u16)0x0040)
+#define  EP2_INT_STATE_OUTSTALL                     ((u16)0x0080)
+
+///-------------------  Bit definition for EP3_INT_STATE register  --------------------
+#define  EP3_INT_STATE_END                          ((u16)0x0002)
+#define  EP3_INT_STATE_INNACK                       ((u16)0x0004)
+#define  EP3_INT_STATE_INACK                        ((u16)0x0008)
+#define  EP3_INT_STATE_INSTALL                      ((u16)0x0010)
+#define  EP3_INT_STATE_OUTNACK                      ((u16)0x0020)
+#define  EP3_INT_STATE_OUTACK                       ((u16)0x0040)
+#define  EP3_INT_STATE_OUTSTALL                     ((u16)0x0080)
+
+///-------------------  Bit definition for EP4_INT_STATE register  --------------------
+#define  EP4_INT_STATE_END                          ((u16)0x0002)
+#define  EP4_INT_STATE_INNACK                       ((u16)0x0004)
+#define  EP4_INT_STATE_INACK                        ((u16)0x0008)
+#define  EP4_INT_STATE_INSTALL                      ((u16)0x0010)
+#define  EP4_INT_STATE_OUTNACK                      ((u16)0x0020)
+#define  EP4_INT_STATE_OUTACK                       ((u16)0x0040)
+#define  EP4_INT_STATE_OUTSTALL                     ((u16)0x0080)
+
+
+///-------------------  Bit definition for EP0_AVIL register  --------------------
+#define EP0_AVIL_EPXAVIL                            ((u16)0x00FF)
+
+///-------------------  Bit definition for EP1_AVIL register  --------------------
+#define EP1_AVIL_EPXAVIL                            ((u16)0x00FF)
+
+///-------------------  Bit definition for EP2_AVIL register  --------------------
+#define EP2_AVIL_EPXAVIL                            ((u16)0x00FF)
+
+///-------------------  Bit definition for EP3_AVIL register  --------------------
+#define EP3_AVIL_EPXAVIL                            ((u16)0x00FF)
+
+///-------------------  Bit definition for EP4_AVIL register  --------------------
+#define EP4_AVIL_EPXAVIL                            ((u16)0x00FF)
+
+///-------------------  Bit definition for EP0_CTRL register  --------------------
+#define EP0_CTRL_TRANEN                             ((u16)0x0080)
+
+#define EP0_CTRL_TRANCOUNT                          ((u16)0x007F)
+#define EP0_CTRL_TRANCOUNT_0                        ((u16)0x0001)
+#define EP0_CTRL_TRANCOUNT_1                        ((u16)0x0002)
+#define EP0_CTRL_TRANCOUNT_2                        ((u16)0x0004)
+#define EP0_CTRL_TRANCOUNT_3                        ((u16)0x0008)
+#define EP0_CTRL_TRANCOUNT_4                        ((u16)0x0010)
+#define EP0_CTRL_TRANCOUNT_5                        ((u16)0x0020)
+#define EP0_CTRL_TRANCOUNT_6                        ((u16)0x0040)
+
+///-------------------  Bit definition for EP1_CTRL register  --------------------
+#define EP1_CTRL_TRANEN                             ((u16)0x0080)
+
+#define EP1_CTRL_TRANCOUNT                         ((u16)0x007F)
+#define EP1_CTRL_TRANCOUNT_0                       ((u16)0x0001)
+#define EP1_CTRL_TRANCOUNT_1                       ((u16)0x0002)
+#define EP1_CTRL_TRANCOUNT_2                       ((u16)0x0004)
+#define EP1_CTRL_TRANCOUNT_3                       ((u16)0x0008)
+#define EP1_CTRL_TRANCOUNT_4                       ((u16)0x0010)
+#define EP1_CTRL_TRANCOUNT_5                       ((u16)0x0020)
+#define EP1_CTRL_TRANCOUNT_6                       ((u16)0x0040)
+
+///-------------------  Bit definition for EP2_CTRL register  --------------------
+#define EP2_CTRL_TRANEN                             ((u16)0x0080)
+
+#define EP2_CTRL_TRANCOUNT                          ((u16)0x007F)
+#define EP2_CTRL_TRANCOUNT_0                        ((u16)0x0001)
+#define EP2_CTRL_TRANCOUNT_1                        ((u16)0x0002)
+#define EP2_CTRL_TRANCOUNT_2                        ((u16)0x0004)
+#define EP2_CTRL_TRANCOUNT_3                        ((u16)0x0008)
+#define EP2_CTRL_TRANCOUNT_4                        ((u16)0x0010)
+#define EP2_CTRL_TRANCOUNT_5                        ((u16)0x0020)
+#define EP2_CTRL_TRANCOUNT_6                        ((u16)0x0040)
+
+///-------------------  Bit definition for EP3_CTRL register  --------------------
+#define EP3_CTRL_TRANEN                             ((u16)0x0080)
+
+#define EP3_CTRL_TRANCOUNT                          ((u16)0x007F)
+#define EP3_CTRL_TRANCOUNT_0                        ((u16)0x0001)
+#define EP3_CTRL_TRANCOUNT_1                        ((u16)0x0002)
+#define EP3_CTRL_TRANCOUNT_2                        ((u16)0x0004)
+#define EP3_CTRL_TRANCOUNT_3                        ((u16)0x0008)
+#define EP3_CTRL_TRANCOUNT_4                        ((u16)0x0010)
+#define EP3_CTRL_TRANCOUNT_5                        ((u16)0x0020)
+#define EP3_CTRL_TRANCOUNT_6                        ((u16)0x0040)
+
+///-------------------  Bit definition for EP4_CTRL register  --------------------
+#define EP4_CTRL_TRANEN                             ((u16)0x0080)
+
+#define EP4_CTRL_TRANCOUNT                          ((u16)0x007F)
+#define EP4_CTRL_TRANCOUNT_0                        ((u16)0x0001)
+#define EP4_CTRL_TRANCOUNT_1                        ((u16)0x0002)
+#define EP4_CTRL_TRANCOUNT_2                        ((u16)0x0004)
+#define EP4_CTRL_TRANCOUNT_3                        ((u16)0x0008)
+#define EP4_CTRL_TRANCOUNT_4                        ((u16)0x0010)
+#define EP4_CTRL_TRANCOUNT_5                        ((u16)0x0020)
+#define EP4_CTRL_TRANCOUNT_6                        ((u16)0x0040)
+
+
+#endif
+#endif //__MM32_REG_DEFINE_V1_H
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h
new file mode 100644
index 000000000..1aab3ef16
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h
@@ -0,0 +1,953 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_adc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_ADC_H
+#define __REG_ADC_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1_BASE                       (APB2PERIPH_BASE + 0x2400)              ///< Base Address: 0x40012400
+#define ADC2_BASE                       (APB2PERIPH_BASE + 0x2800)              ///< Base Address: 0x40012800
+#define ADC3_BASE                       (APB2PERIPH_BASE + 0x4C00)              ///< Base Address: 0x40014C00
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Analog-to-Digital Converter register
+////////////////////////////////////////////////////////////////////////////////
+#define USENCOMBINEREGISTER
+#ifdef USENCOMBINEREGISTER
+
+typedef struct {
+    union {
+        __IO u32 DR;                                                            ///< ADC data register,                             offset: 0x00
+        __IO u32 ADDATA;
+    };
+    union {
+        __IO u32 CFGR;                                                          ///< ADC configuration register,                    offset: 0x04
+        __IO u32 ADCFG;
+    };
+    union {
+        __IO u32 CR;                                                            ///< ADC control register,                          offset: 0x08
+        __IO u32 ADCR;
+    };
+    union {
+        __IO u32 CHSR;                                                          ///< ADC channel selection register,                offset: 0x0C
+        __IO u32 ADCHS;
+    };
+    union {
+        __IO u32 CMPR;                                                          ///< ADC window compare register,                   offset: 0x10
+        __IO u32 ADCMPR;
+    };
+    union {
+        __IO u32 SR;                                                            ///< ADC status register,                           offset: 0x14
+        __IO u32 ADSTA;
+    };
+    union {
+        __IO u32 CH0DR;                                                         ///< ADC channel0 data register,                    offset: 0x18
+        __IO u32 ADDR0;
+    };
+    union {
+        __IO u32 CH1DR;                                                         ///< ADC channel1 data register,                    offset: 0x1C
+        __IO u32 ADDR1;
+    };
+    union {
+        __IO u32 CH2DR;                                                         ///< ADC channel2 data register,                    offset: 0x20
+        __IO u32 ADDR2;
+    };
+    union {
+        __IO u32 CH3DR;                                                         ///< ADC channel3 data register,                    offset: 0x24
+        __IO u32 ADDR3;
+    };
+    union {
+        __IO u32 CH4DR;                                                         ///< ADC channel4 data register,                    offset: 0x28
+        __IO u32 ADDR4;
+    };
+    union {
+        __IO u32 CH5DR;                                                         ///< ADC channel5 data register,                    offset: 0x2C
+        __IO u32 ADDR5;
+    };
+    union {
+        __IO u32 CH6DR;                                                         ///< ADC channel6 data register,                    offset: 0x30
+        __IO u32 ADDR6;
+    };
+    union {
+        __IO u32 CH7DR;                                                         ///< ADC channel7 data register,                    offset: 0x34
+        __IO u32 ADDR7;
+    };
+    union {
+        __IO u32 CH8DR;                                                         ///< ADC channel8 data register,                    offset: 0x38
+        __IO u32 ADDR8;
+    };
+    union {
+        __IO u32 CH9DR;                                                         ///< ADC channel9 data register,                    offset: 0x3C
+        __IO u32 ADDR9;
+    };
+    __IO u32 ADDR10;                                                            ///<                                                offset: 0x40
+    __IO u32 ADDR11;                                                            ///<                                                offset: 0x44
+    __IO u32 ADDR12;                                                            ///<                                                offset: 0x48
+    __IO u32 ADDR13;                                                            ///<                                                offset: 0x4C
+    union {
+        __IO u32 CH14DR;                                                        ///< ADC channel14 data register,                   offset: 0x50
+        __IO u32 ADDR14;
+    };
+    union {
+        __IO u32 CH15DR;                                                        ///< ADC channel15 data register,                   offset: 0x54
+        __IO u32 ADDR15;
+    };
+    __IO u32 SREXT;                                                             ///< ADC Extended Status Register,                  offset: 0x58
+    __IO u32 CHANY0;                                                            ///< ADC any Chan Select Register 0,                offset: 0x5C
+    __IO u32 CHANY1;                                                            ///< ADC any Chan Select Register 1,                offset: 0x60
+    __IO u32 ANYCFG;                                                            ///< ADC any Chan config Register,                  offset: 0x64
+    __IO u32 ANYCR;                                                             ///< ADC any Chan control Register,                 offset: 0x68
+    __IO u32 RESERVED0;                                                         ///<                                                offset 0x6C
+    __IO u32 SMPR1;                                                             ///< Sampling configuration register 1              offset 0x70
+    __IO u32 SMPR2;                                                             ///< Sampling configuration register 2              offset 0x74
+    __IO u32 RESERVED1;                                                         ///<                                                offset 0x78
+    __IO u32 JOFR0;                                                             ///< Injection channel data compensation register 0 offset 0x7C
+    __IO u32 JOFR1;                                                             ///< Injection channel data compensation register 1 offset 0x80
+    __IO u32 JOFR2;                                                             ///< Injection channel data compensation register 2 offset 0x84
+    __IO u32 JOFR3;                                                             ///< Injection channel data compensation register 3 offset 0x88
+    __IO u32 JSQR;                                                              ///< Injection sequence register                    offset 0x8C
+    __IO u32 JDATA;                                                             ///< Inject data register                           offset 0x90
+    __IO u32 RESERVED2;                                                         ///<                                                offset 0x94
+    __IO u32 RESERVED3;                                                         ///<                                                offset 0x98
+    __IO u32 RESERVED4;                                                         ///<                                                offset 0x9C
+    __IO u32 RESERVED5;                                                         ///<                                                offset 0xA0
+    __IO u32 RESERVED6;                                                         ///<                                                offset 0xA4
+    __IO u32 RESERVED7;                                                         ///<                                                offset 0xA8
+    __IO u32 RESERVED8;                                                         ///<                                                offset 0xAC
+    __IO u32 JDR0;                                                              ///< Injection channel data register 0              offset 0xB0
+    __IO u32 JDR1;                                                              ///< Injection channel data register 1              offset 0xB4
+    __IO u32 JDR2;                                                              ///< Injection channel data register 2              offset 0xB8
+    __IO u32 JDR3;                                                              ///< Injection channel data register 3              offset 0xBC
+} ADC_TypeDef;
+
+#endif
+#ifdef USENNEWREGISTER
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Analog-to-Digital Converter register
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 DR;                                                                ///< ADC data register,                             offset: 0x00
+    __IO u32 CFGR;                                                              ///< ADC configuration register,                    offset: 0x04
+    __IO u32 CR;                                                                ///< ADC control register,                          offset: 0x08
+    __IO u32 CHSR;                                                              ///< ADC channel selection register,                offset: 0x0C
+    __IO u32 CMPR;                                                              ///< ADC window compare register,                   offset: 0x10
+    __IO u32 SR;                                                                ///< ADC status register,                           offset: 0x14
+    __IO u32 CH0DR;                                                             ///< ADC channel0 data register,                    offset: 0x18
+    __IO u32 CH1DR;                                                             ///< ADC channel1 data register,                    offset: 0x1C
+    __IO u32 CH2DR;                                                             ///< ADC channel2 data register,                    offset: 0x20
+    __IO u32 CH3DR;                                                             ///< ADC channel3 data register,                    offset: 0x24
+    __IO u32 CH4DR;                                                             ///< ADC channel4 data register,                    offset: 0x28
+    __IO u32 CH5DR;                                                             ///< ADC channel5 data register,                    offset: 0x2C
+    __IO u32 CH6DR;                                                             ///< ADC channel6 data register,                    offset: 0x30
+    __IO u32 CH7DR;                                                             ///< ADC channel7 data register,                    offset: 0x34
+    __IO u32 CH8DR;                                                             ///< ADC channel8 data register,                    offset: 0x38
+} ADC_TypeDef;
+#endif
+#ifdef USENOLDREGISTER
+typedef struct {
+    __IO u32 ADDATA;                                                            ///< ADC data register,                             offset: 0x00
+    __IO u32 ADCFG;                                                             ///< ADC configuration register,                    offset: 0x04
+    __IO u32 ADCR;                                                              ///< ADC control register,                          offset: 0x08
+    __IO u32 ADCHS;                                                             ///< ADC channel selection register,                offset: 0x0C
+    __IO u32 ADCMPR;                                                            ///< ADC window compare register,                   offset: 0x10
+    __IO u32 ADSTA;                                                             ///< ADC status register,                           offset: 0x14
+    __IO u32 ADDR0;                                                             ///< ADC channel0 data register,                    offset: 0x18
+    __IO u32 ADDR1;                                                             ///< ADC channel1 data register,                    offset: 0x1C
+    __IO u32 ADDR2;                                                             ///< ADC channel2 data register,                    offset: 0x20
+    __IO u32 ADDR3;                                                             ///< ADC channel3 data register,                    offset: 0x24
+    __IO u32 ADDR4;                                                             ///< ADC channel4 data register,                    offset: 0x28
+    __IO u32 ADDR5;                                                             ///< ADC channel5 data register,                    offset: 0x2C
+    __IO u32 ADDR6;                                                             ///< ADC channel6 data register,                    offset: 0x30
+    __IO u32 ADDR7;                                                             ///< ADC channel7 data register,                    offset: 0x34
+    __IO u32 ADDR8;                                                             ///< ADC channel8 data register,                    offset: 0x38
+} ADC_TypeDef;
+#endif
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1                            ((ADC_TypeDef*) ADC1_BASE)
+#define ADC2                            ((ADC_TypeDef*) ADC2_BASE)
+#define ADC3                            ((ADC_TypeDef*) ADC3_BASE)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_DR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_DR_DATA_Pos                (0)
+#define ADC_DR_DATA                    (0xFFFFU << ADC_DR_DATA_Pos)            ///< ADC 12bit convert data
+
+#define ADC_DR_CH_Pos                  (16)
+#define ADC_DR_CH                      (0x0FU <<  ADC_DR_CH_Pos)               ///< CHANNELSEL[19:16] (ADC current channel convert data)
+
+#define ADC_DR_CH0                     (0x00U << ADC_DR_CH_Pos)                ///< ADC Channel select  0
+#define ADC_DR_CH1                     (0x01U << ADC_DR_CH_Pos)                ///< ADC Channel select  1
+#define ADC_DR_CH2                     (0x02U << ADC_DR_CH_Pos)                ///< ADC Channel select  2
+#define ADC_DR_CH3                     (0x03U << ADC_DR_CH_Pos)                ///< ADC Channel select  3
+#define ADC_DR_CH4                     (0x04U << ADC_DR_CH_Pos)                ///< ADC Channel select  4
+#define ADC_DR_CH5                     (0x05U << ADC_DR_CH_Pos)                ///< ADC Channel select  5
+#define ADC_DR_CH6                     (0x06U << ADC_DR_CH_Pos)                ///< ADC Channel select  6
+#define ADC_DR_CH7                     (0x07U << ADC_DR_CH_Pos)                ///< ADC Channel select  7
+
+#define ADC_DR_CH8                     (0x08U << ADC_DR_CH_Pos)                ///< ADC Channel select  8
+
+#define ADC_DR_CH10                    (0x0AU << ADC_DR_CH_Pos)                ///< ADC Channel select  10
+#define ADC_DR_CH11                    (0x0BU << ADC_DR_CH_Pos)                ///< ADC Channel select  11
+#define ADC_DR_CH13                    (0x0CU << ADC_DR_CH_Pos)                ///< ADC Channel select  13
+
+#define ADC_DR_CH9                     (0x09U << ADC_DR_CH_Pos)                ///< ADC Channel select  9
+#define ADC_DR_CH14                    (0x0EU << ADC_DR_CH_Pos)                ///< ADC Channel select  14
+#define ADC_DR_CH15                    (0x0FU << ADC_DR_CH_Pos)                ///< ADC Channel select  15
+#define ADC_DR_OVERRUN_Pos             (20)
+#define ADC_DR_OVERRUN                 (0x01U << ADC_DR_OVERRUN_Pos)           ///< ADC data will be cover
+#define ADC_DR_VALID_Pos               (21)
+#define ADC_DR_VALID                   (0x01U << ADC_DR_VALID_Pos)             ///< ADC data[11:0] is valid
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_CFGR_ADEN_Pos              (0)
+#define ADC_CFGR_ADEN                  (0x01U << ADC_CFGR_ADEN_Pos)            ///< Enable ADC convert
+#define ADC_CFGR_ADWEN_Pos             (1)
+#define ADC_CFGR_ADWEN                 (0x01U << ADC_CFGR_ADWEN_Pos)           ///< Enable ADC window compare
+
+
+#define ADC_CFGR_RSLTCTL_Pos           (7)
+#define ADC_CFGR_RSLTCTL               (0x07U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select
+#define ADC_CFGR_RSLTCTL_12            (0x00U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select 12bit
+#define ADC_CFGR_RSLTCTL_11            (0x01U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select 11bit
+#define ADC_CFGR_RSLTCTL_10            (0x02U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select 10bit
+#define ADC_CFGR_RSLTCTL_9             (0x03U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select 9bit
+#define ADC_CFGR_RSLTCTL_8             (0x04U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select 8bit
+
+#define ADC_CFGR_TEN_Pos               (2)
+#define ADC_CFGR_TEN                   (0x01U << ADC_CFGR_TEN_Pos)                 ///< Enable ADC temperature sensor
+#define ADC_CFGR_VEN_Pos               (3)
+#define ADC_CFGR_VEN                   (0x01U << ADC_CFGR_VEN_Pos)                 ///< Enable ADC voltage reference
+
+
+
+
+
+#define ADC_CFGR_PRE_Pos                (4)
+#define ADC_CFGR_PREL_Pos               (14)
+#define ADC_CFGR_PRE                    ((0x07U << ADC_CFGR_PRE_Pos) + (0x01U << ADC_CFGR_PREL_Pos))
+#define ADC_CFGR_PRE_2                  (0x00U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 2
+#define ADC_CFGR_PRE_4                  (0x01U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 4
+#define ADC_CFGR_PRE_6                  (0x02U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 6
+#define ADC_CFGR_PRE_8                  (0x03U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 8
+#define ADC_CFGR_PRE_10                 (0x04U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 10
+#define ADC_CFGR_PRE_12                 (0x05U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 12
+#define ADC_CFGR_PRE_14                 (0x06U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 14
+#define ADC_CFGR_PRE_16                 (0x07U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 16
+#define ADC_CFGR_PRE_3                  ((0x01U << ADC_CFGR_PREL_Pos) + (0x00U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 3
+#define ADC_CFGR_PRE_5                  ((0x01U << ADC_CFGR_PREL_Pos) + (0x01U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 5
+#define ADC_CFGR_PRE_7                  ((0x01U << ADC_CFGR_PREL_Pos) + (0x02U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 7
+#define ADC_CFGR_PRE_9                  ((0x01U << ADC_CFGR_PREL_Pos) + (0x03U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 9
+#define ADC_CFGR_PRE_11                 ((0x01U << ADC_CFGR_PREL_Pos) + (0x04U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 11
+#define ADC_CFGR_PRE_13                 ((0x01U << ADC_CFGR_PREL_Pos) + (0x05U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 13
+#define ADC_CFGR_PRE_15                 ((0x01U << ADC_CFGR_PREL_Pos) + (0x06U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 15
+#define ADC_CFGR_PRE_17                 ((0x01U << ADC_CFGR_PREL_Pos) + (0x07U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 17
+
+#define ADC_CFGR_JADWEN_Pos             (16)
+#define ADC_CFGR_JADWEN                 (0x01U << ADC_CFGR_JADWEN_Pos)              ///< Inject ADC conversion window comparison enable
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_CR_ADIE_Pos                (0)
+#define ADC_CR_ADIE                    (0x01U << ADC_CR_ADIE_Pos)              ///< ADC interrupt enable
+#define ADC_CR_ADWIE_Pos               (1)
+#define ADC_CR_ADWIE                   (0x01U << ADC_CR_ADWIE_Pos)             ///< ADC window compare interrupt enable
+#define ADC_CR_TRGEN_Pos               (2)
+#define ADC_CR_TRGEN                   (0x01U << ADC_CR_TRGEN_Pos)             ///< extranal trigger single start AD convert
+#define ADC_CR_DMAEN_Pos               (3)
+#define ADC_CR_DMAEN                   (0x01U << ADC_CR_DMAEN_Pos)             ///< ADC DMA enable
+
+#define ADC_CR_ADST_Pos                (8)
+#define ADC_CR_ADST                    (0x01U << ADC_CR_ADST_Pos)              ///< ADC start convert data
+#define ADC_CR_MODE_Pos                (9)
+#define ADC_CR_MODE                    (0x03U << ADC_CR_MODE_Pos)              ///< ADC convert mode
+#define ADC_CR_IMM                     (0x00U << ADC_CR_MODE_Pos)              ///< ADC imm convert mode
+#define ADC_CR_SCAN                    (0x01U << ADC_CR_MODE_Pos)              ///< ADC scan convert mode
+#define ADC_CR_CONTINUE                (0x02U << ADC_CR_MODE_Pos)              ///< ADC continue scan convert mode
+#define ADC_CR_ALIGN_Pos               (11)
+#define ADC_CR_ALIGN                   (0x01U << ADC_CR_ALIGN_Pos)             ///< ADC data align
+#define ADC_CR_LEFT                    (0x01U << ADC_CR_ALIGN_Pos)             ///< ADC data left align
+#define ADC_CR_RIGHT                   (0x00U << ADC_CR_ALIGN_Pos)             ///< ADC data right align
+#define ADC_CR_CMPCH_Pos               (12)
+#define ADC_CR_CMPCH                   (0x0FU << ADC_CR_CMPCH_Pos)             ///< CMPCH[15:12] ADC window compare channel0 convert data
+#define ADC_CR_CMPCH_0                 (0x00U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 0 Conversion Results
+#define ADC_CR_CMPCH_1                 (0x01U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 1 Conversion Results
+#define ADC_CR_CMPCH_2                 (0x02U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 2 Conversion Results
+#define ADC_CR_CMPCH_4                 (0x04U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 4 Conversion Results
+#define ADC_CR_CMPCH_5                 (0x05U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 5 Conversion Results
+#define ADC_CR_CMPCH_6                 (0x06U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 6 Conversion Results
+#define ADC_CR_CMPCH_7                 (0x07U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 7 Conversion Results
+#define ADC_CR_CMPCH_8                 (0x08U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 8 Conversion Results
+#define ADC_CR_CMPCH_9                 (0x09U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 9 Conversion Results
+#define ADC_CR_CMPCH_10                (0x0AU << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 10 Conversion Results
+#define ADC_CR_CMPCH_11                (0x0BU << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 11 Conversion Results
+#define ADC_CR_CMPCH_13                (0x0DU << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 13 Conversion Results
+#define ADC_CR_CMPCH_14                (0x0EU << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 14 Conversion Results
+#define ADC_CR_CMPCH_ALL               (0x0FU << ADC_CR_CMPCH_Pos)             ///< Select Compare ALL Channel Conversion Results
+
+
+
+#define ADC_CR_SCANDIR_Pos              (16)
+#define ADC_CR_SCANDIR                  (0x01U << ADC_CR_SCANDIR_Pos)           ///< ADC scan direction
+#define ADC_CR_TRGSEL_H_Pos             (17)
+#define ADC_CR_TRGSEL_L_Pos             (4)
+#define ADC_CR_TRGSEL                   ((0x03U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos))   ///< TRGSEL[6:4][18:17] ADC external trigger source select
+#define ADC_CR_T1_CC1                   (0x00U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T1_CC1
+#define ADC_CR_T1_CC2                   (0x01U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T1_CC2
+#define ADC_CR_T1_CC3                   (0x02U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T1_CC3
+#define ADC_CR_T2_CC2                   (0x03U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T2_CC2
+#define ADC_CR_T3_TRIG                  (0x04U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T3_TRIG
+#define ADC_CR_T1_CC4_CC5               (0x05U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T1_CC4_CC5
+#define ADC_CR_T3_CC1                   (0x06U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T3_CC1
+#define ADC_CR_EXTI_11                  (0x07U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is EXTI_11
+#define ADC_CR_T1_TRIG                  ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T1_TRIG
+#define ADC_CR_T8_CC4               ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T8_CC4
+#define ADC_CR_T8_CC4_CC5           ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x02U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T8_CC4_CC5
+#define ADC_CR_T2_CC1                   ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x03U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T2_CC1
+#define ADC_CR_T3_CC4                   ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x04U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T3_CC4
+#define ADC_CR_T2_TRIG                  ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x05U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T2_TRIG
+#define ADC_CR_T8_CC5                   ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x06U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T8_CC5
+#define ADC_CR_EXTI_15                  ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is EXTI_15
+#define ADC_CR_TIM1_CC4                 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is TIM1_CC4
+#define ADC_CR_TIM1_CC5                 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is TIM1_CC5
+
+#define ADC_CR_TRGSHIFT_Pos             (19)
+#define ADC_CR_TRGSHIFT                 (0x07U << ADC_CR_TRGSHIFT_Pos)          ///< External trigger shift sample
+#define ADC_CR_TRGSHIFT_0               (0x00U << ADC_CR_TRGSHIFT_Pos)          ///< No shift
+#define ADC_CR_TRGSHIFT_4               (0x01U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 4 period
+#define ADC_CR_TRGSHIFT_16              (0x02U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 16 period
+#define ADC_CR_TRGSHIFT_32              (0x03U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 32 period
+#define ADC_CR_TRGSHIFT_64              (0x04U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 64 period
+#define ADC_CR_TRGSHIFT_128             (0x05U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 128 period
+#define ADC_CR_TRGSHIFT_256             (0x06U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 256 period
+#define ADC_CR_TRGSHIFT_512             (0x07U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 512 period
+#define ADC_CR_CALIBEN_Pos              (22)
+#define ADC_CR_CALIBEN                  (0x01U << ADC_CR_CALIBEN_Pos)           ///< Self-calibration enable
+#define ADC_CR_CALIBSEL_Pos             (23)
+#define ADC_CR_CALIBSEL                 (0x01U << ADC_CR_CALIBSEL_Pos)          ///< Self-calibration voltage selection
+#define ADC_CR_TRG_EDGE_Pos            (24)
+#define ADC_CR_TRG_EDGE                (0x03U << ADC_CR_TRG_EDGE_Pos)          ///< ADC trig edge config
+#define ADC_CR_TRG_EDGE_DUAL           (0x00U << ADC_CR_TRG_EDGE_Pos)          ///< ADC dual edge trig mode
+#define ADC_CR_TRG_EDGE_DOWN           (0x01U << ADC_CR_TRG_EDGE_Pos)          ///< ADC down edge trig mode
+#define ADC_CR_TRG_EDGE_UP             (0x02U << ADC_CR_TRG_EDGE_Pos)          ///< ADC up   edge trig mode
+#define ADC_CR_TRG_EDGE_MASK           (0x03U << ADC_CR_TRG_EDGE_Pos)          ///< ADC mask edge trig mode
+
+#define ADC_CR_EOSMPIE_Pos              (26)
+#define ADC_CR_EOSMPIE                  (0X01U << ADC_CR_EOSMPIE_Pos)            ///< ADC end sampling flag interrupt enable
+#define ADC_CR_EOCIE_Pos                (27)
+#define ADC_CR_EOCIE                    (0X01U << ADC_CR_EOCIE_Pos)            ///< ADC end of conversion interrupt enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_CHSR_CH0_Pos               (0)
+#define ADC_CHSR_CH0                   (0x01U << ADC_CHSR_CH0_Pos)             ///< Enable ADC channel 0
+#define ADC_CHSR_CH1_Pos               (1)
+#define ADC_CHSR_CH1                   (0x01U << ADC_CHSR_CH1_Pos)             ///< Enable ADC channel 1
+#define ADC_CHSR_CH2_Pos               (2)
+#define ADC_CHSR_CH2                   (0x01U << ADC_CHSR_CH2_Pos)             ///< Enable ADC channel 2
+#define ADC_CHSR_CH3_Pos               (3)
+#define ADC_CHSR_CH3                   (0x01U << ADC_CHSR_CH3_Pos)             ///< Enable ADC channel 3
+#define ADC_CHSR_CH4_Pos               (4)
+#define ADC_CHSR_CH4                   (0x01U << ADC_CHSR_CH4_Pos)             ///< Enable ADC channel 4
+#define ADC_CHSR_CH5_Pos               (5)
+#define ADC_CHSR_CH5                   (0x01U << ADC_CHSR_CH5_Pos)             ///< Enable ADC channel 5
+#define ADC_CHSR_CH6_Pos               (6)
+#define ADC_CHSR_CH6                   (0x01U << ADC_CHSR_CH6_Pos)             ///< Enable ADC channel 6
+#define ADC_CHSR_CH7_Pos               (7)
+#define ADC_CHSR_CH7                   (0x01U << ADC_CHSR_CH7_Pos)             ///< Enable ADC channel 7
+
+#define ADC_CHSR_CH8_Pos               (8)
+#define ADC_CHSR_CH8                   (0x01U << ADC_CHSR_CH8_Pos)             ///< Enable ADC channel 8
+#define ADC_CHSR_CH9_Pos               (9)
+#define ADC_CHSR_CH9                   (0x01U << ADC_CHSR_CH9_Pos)             ///< Enable ADC channel 9
+#define ADC_CHSR_CHT_Pos               (14)
+#define ADC_CHSR_CHT                   (0x01U << ADC_CHSR_CHT_Pos)             ///< Enable Temperature Sensor
+#define ADC_CHSR_CHV_Pos               (15)
+#define ADC_CHSR_CHV                   (0x01U << ADC_CHSR_CHV_Pos)             ///< Enable Voltage Sensor
+
+
+#define ADC_CHSR_CH10_Pos              (10)
+#define ADC_CHSR_CH10                  (0x01U << ADC_CHSR_CH10_Pos)            ///< Enable ADC channel 10
+#define ADC_CHSR_CH11_Pos              (11)
+#define ADC_CHSR_CH11                  (0x01U << ADC_CHSR_CH11_Pos)            ///< Enable ADC channel 11
+#define ADC_CHSR_CH12_Pos              (12)
+#define ADC_CHSR_CH12                  (0x01U << ADC_CHSR_CH12_Pos)            ///< Enable ADC channel 12
+#define ADC_CHSR_CH13_Pos              (13)
+#define ADC_CHSR_CH13                  (0x01U << ADC_CHSR_CH13_Pos)            ///< Enable ADC channel 13
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CMPR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_CMPR_CMPLDATA_Pos          (0)
+#define ADC_CMPR_CMPLDATA              (0x0FFFU << ADC_CMPR_CMPLDATA_Pos)      ///< ADC 12bit window compare DOWN LEVEL DATA
+#define ADC_CMPR_CMPHDATA_Pos          (16)
+#define ADC_CMPR_CMPHDATA              (0x0FFFU << ADC_CMPR_CMPHDATA_Pos)      ///< ADC 12bit window compare UP LEVEL DATA
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_SR_ADIF_Pos                (0)
+#define ADC_SR_ADIF                    (0x01U << ADC_SR_ADIF_Pos)              ///< ADC convert complete flag
+#define ADC_SR_ADWIF_Pos               (1)
+#define ADC_SR_ADWIF                   (0x01U << ADC_SR_ADWIF_Pos)             ///< ADC compare flag
+#define ADC_SR_BUSY_Pos                (2)
+#define ADC_SR_BUSY                    (0x01U << ADC_SR_BUSY_Pos)              ///< ADC busy flag
+#define ADC_SR_CH_Pos                  (4)
+#define ADC_SR_CH                      (0x0FU << ADC_SR_CH_Pos)                ///< CHANNEL[7:4] ADC current channel
+#define ADC_SR_CH0                     (0x00U << ADC_SR_CH_Pos)                ///< Channel 0 is the current conversion channel
+#define ADC_SR_CH1                     (0x01U << ADC_SR_CH_Pos)                ///< Channel 1 is the current conversion channel
+#define ADC_SR_CH2                     (0x02U << ADC_SR_CH_Pos)                ///< Channel 2 is the current conversion channel
+#define ADC_SR_CH3                     (0x03U << ADC_SR_CH_Pos)                ///< Channel 3 is the current conversion channel
+#define ADC_SR_CH4                     (0x04U << ADC_SR_CH_Pos)                ///< Channel 4 is the current conversion channel
+#define ADC_SR_CH5                     (0x05U << ADC_SR_CH_Pos)                ///< Channel 5 is the current conversion channel
+#define ADC_SR_CH6                     (0x06U << ADC_SR_CH_Pos)                ///< Channel 6 is the current conversion channel
+#define ADC_SR_CH7                     (0x07U << ADC_SR_CH_Pos)                ///< Channel 7 is the current conversion channel
+#define ADC_SR_CH8                     (0x08U << ADC_SR_CH_Pos)                ///< Channel 8 is the current conversion channel
+#define ADC_SR_CH9                     (0x09U << ADC_SR_CH_Pos)                ///< Channel 9 is the current conversion channel
+#define ADC_SR_CH10                    (0x0AU << ADC_SR_CH_Pos)                ///< Channel 10 is the current conversion channel
+#define ADC_SR_CH11                    (0x0BU << ADC_SR_CH_Pos)                ///< Channel 11 is the current conversion channel
+#define ADC_SR_CH13                    (0x0DU << ADC_SR_CH_Pos)                ///< Channel 13 is the current conversion channel
+#define ADC_SR_CH14                    (0x0EU << ADC_SR_CH_Pos)                ///< Channel 14 is the current conversion channel
+#define ADC_SR_CH15                    (0x0FU << ADC_SR_CH_Pos)                ///< Channel 15 is the current conversion channel
+
+
+#define ADC_SR_VALID_Pos               (8)
+#define ADC_SR_VALID                   (0x0FFFU << ADC_SR_VALID_Pos)           ///< VALID[19:8] ADC channel 0..11 valid flag
+#define ADC_SR_OVERRUN_Pos             (20)
+#define ADC_SR_OVERRUN                 (0x0FFFU << ADC_SR_OVERRUN_Pos)         ///< OVERRUN[31:20] ADC channel 0..11 data covered flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHnDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_CHDR_DATA_Pos          (0)
+#define ADC_CHDR_DATA              (0xFFFFU << ADC_CHDR_DATA_Pos)          ///< ADC channel convert data
+#define ADC_CHDR_OVERRUN_Pos       (20)
+#define ADC_CHDR_OVERRUN           (0x01U << ADC_CHDR_OVERRUN_Pos)         ///< ADC data covered flag
+#define ADC_CHDR_VALID_Pos         (21)
+#define ADC_CHDR_VALID             (0x01U << ADC_CHDR_VALID_Pos)           ///< ADC data valid flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_SREXT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_SREXT_VALID_Pos             (0)
+#define ADC_SREXT_VALID                 (0x0FU << ADC_SREXT_VALID_Pos)          ///< VALID[3:0] ADC channel 12,14..15 valid flag
+#define ADC_SREXT_OVERRUN_Pos           (4)
+#define ADC_SREXT_OVERRUN               (0x0FU << ADC_SREXT_OVERRUN_Pos)        ///< OVERRUN[7:4] ADC channel 12,14..15 data covered flag
+
+
+#define ADC_SREXT_EOSMPIF_Pos       (16)
+#define ADC_SREXT_EOSMPIF           (0x01U << ADC_SREXT_EOSMPIF_Pos)       ///< End of sampling interrupt flag
+#define ADC_SREXT_EOCIF_Pos         (17)
+#define ADC_SREXT_EOCIF             (0x01U << ADC_SREXT_EOCIF_Pos)         ///< End of conversion interrupt flag
+#define ADC_SREXT_JEOSMPIF_Pos      (18)
+#define ADC_SREXT_JEOSMPIF          (0x01U << ADC_SREXT_JEOSMPIF_Pos)      /// Injected channel end of sampling interrupt flag
+#define ADC_SREXT_JEOCIF_Pos        (19)
+#define ADC_SREXT_JEOCIF            (0x03U << ADC_SREXT_JEOCIF_Pos)        ///< Injected channel end of conversion interrupt flag
+#define ADC_SREXT_JEOSIF_Pos        (20)
+#define ADC_SREXT_JEOSIF            (0x03U << ADC_SREXT_JEOSIF_Pos)        ///< Injected channel end of sequential conversion interrupt flag
+#define ADC_SREXT_JBUSY_Pos         (21)
+#define ADC_SREXT_JBUSY             (0x01U << ADC_SREXT_JBUSY_Pos)         ///< Injection mode busy/idle
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHANY0 select Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1_CHANY0_SEL0_Pos            (0)                                     ///< CHANY_SEL0 (Bit 0)
+#define ADC1_CHANY0_SEL0                (0x0FU << ADC1_CHANY0_SEL0_Pos)         ///< CHANY_SEL0 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL1_Pos            (4)                                     ///< CHANY_SEL1 (Bit 4)
+#define ADC1_CHANY0_SEL1                (0x0FU << ADC1_CHANY0_SEL1_Pos)         ///< CHANY_SEL1 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL2_Pos            (8)                                     ///< CHANY_SEL2 (Bit 8)
+#define ADC1_CHANY0_SEL2                (0x0FU << ADC1_CHANY0_SEL2_Pos)         ///< CHANY_SEL2 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL3_Pos            (12)                                    ///< CHANY_SEL3 (Bit 12)
+#define ADC1_CHANY0_SEL3                (0x0FU << ADC1_CHANY0_SEL3_Pos)         ///< CHANY_SEL3 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL4_Pos            (16)                                    ///< CHANY_SEL4 (Bit 16)
+#define ADC1_CHANY0_SEL4                (0x0FU << ADC1_CHANY0_SEL4_Pos)         ///< CHANY_SEL4 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL5_Pos            (20)                                    ///< CHANY_SEL5 (Bit 20)
+#define ADC1_CHANY0_SEL5                (0x0FU << ADC1_CHANY0_SEL5_Pos)         ///< CHANY_SEL5 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL6_Pos            (24)                                    ///< CHANY_SEL6 (Bit 24)
+#define ADC1_CHANY0_SEL6                (0x0FU << ADC1_CHANY0_SEL6_Pos)         ///< CHANY_SEL6 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY0_SEL7_Pos            (28)                                    ///< CHANY_SEL7 (Bit 28)
+#define ADC1_CHANY0_SEL7                (0x0FU << ADC1_CHANY0_SEL7_Pos)         ///< CHANY_SEL7 (Bitfield-Mask: 0x0f)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHANY1 select Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1_CHANY1_SEL8_Pos            (0)                                     ///< CHANY_SEL8 (Bit 0)
+#define ADC1_CHANY1_SEL8                (0x0FU << ADC1_CHANY1_SEL8_Pos)         ///< CHANY_SEL8 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL9_Pos            (4)                                     ///< CHANY_SEL9 (Bit 4)
+#define ADC1_CHANY1_SEL9                (0x0FU << ADC1_CHANY1_SEL9_Pos)         ///< CHANY_SEL9 (Bitfield-Mask: 0x0f)
+
+#define ADC1_CHANY1_SEL14_Pos           (24)                                    ///< CHANY_SEL14 (Bit 24)
+#define ADC1_CHANY1_SEL14               (0x0FU << ADC1_CHANY1_SEL14_Pos)        ///< CHANY_SEL14 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL15_Pos           (28)                                    ///< CHANY_SEL15 (Bit 28)
+#define ADC1_CHANY1_SEL15               (0x0FU << ADC1_CHANY1_SEL15_Pos)        ///< CHANY_SEL15 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL10_Pos           (8)                                     ///< CHANY_SEL10 (Bit 8)
+#define ADC1_CHANY1_SEL10               (0x0FU << ADC1_CHANY1_SEL10_Pos)        ///< CHANY_SEL10 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL11_Pos           (12)                                    ///< CHANY_SEL11 (Bit 12)
+#define ADC1_CHANY1_SEL11               (0x0FU << ADC1_CHANY1_SEL11_Pos)        ///< CHANY_SEL11 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL12_Pos           (16)                                    ///< CHANY_SEL12 (Bit 16)
+#define ADC1_CHANY1_SEL12               (0x0FU << ADC1_CHANY1_SEL12_Pos)        ///< CHANY_SEL12 (Bitfield-Mask: 0x0f)
+#define ADC1_CHANY1_SEL13_Pos           (20)                                    ///< CHANY_SEL13 (Bit 20)
+#define ADC1_CHANY1_SEL13               (0x0FU << ADC1_CHANY1_SEL13_Pos)        ///< CHANY_SEL13 (Bitfield-Mask: 0x0f)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHANY config number Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1_CHANY_CFG_NUM_Max          (16)                                    ///< CHANY_CFG_NUM Max Value is 16
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_CHANY mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC1_CHANY_CR_MDEN_Pos          (0)                                     ///< CHANY_MDEN (Bit 0)
+#define ADC1_CHANY_CR_MDEN              (0x01U << ADC1_CHANY_CR_MDEN_Pos)       ///< CHANY_MDEN (Bitfield-Mask: 0x01)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_ANY_CR mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_ANY_CR_JTRGEDGE_Pos         (16)                                    ///< Injection mode triggers edge selection
+#define ADC_ANY_CR_JTRGEDGE_R_F         (0x00U << ADC_ANY_CR_JTRGEDGE_Pos)      ///< Triggered along both rising and falling edges
+#define ADC_ANY_CR_JTRGEDGE_F           (0x01U << ADC_ANY_CR_JTRGEDGE_Pos)      ///< Drop edge trigger
+#define ADC_ANY_CR_JTRGEDGE_R           (0x02U << ADC_ANY_CR_JTRGEDGE_Pos)      ///< Rising edge trigger
+#define ADC_ANY_CR_JTRGEDGE_S           (0x03U << ADC_ANY_CR_JTRGEDGE_Pos)      ///< Shield trigger
+
+#define ADC_ANY_CR_JTRGSHIFT_Pos        (13)                                    ///< Injection mode external trigger delay sampling
+#define ADC_ANY_CR_JTRGSHIFT_0          (0x00U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 0   cycle
+#define ADC_ANY_CR_JTRGSHIFT_4          (0x01U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 4   cycle
+#define ADC_ANY_CR_JTRGSHIFT_16         (0x02U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 16  cycle
+#define ADC_ANY_CR_JTRGSHIFT_32         (0x03U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 32  cycle
+#define ADC_ANY_CR_JTRGSHIFT_64         (0x04U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 64  cycle
+#define ADC_ANY_CR_JTRGSHIFT_128        (0x05U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 128 cycle
+#define ADC_ANY_CR_JTRGSHIFT_256        (0x06U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 256 cycle
+#define ADC_ANY_CR_JTRGSHIFT_512        (0x07U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 512 cycle
+
+#define ADC_ANY_CR_JTRGSEL_Pos          (8)                                     ///< External event select for injected group
+#define ADC_ANY_CR_JTRGSEL              (0x07U << ADC_ANY_CR_JTRGSEL_Pos)
+#define ADC_ANY_CR_JTRGSEL_TIM1_TRGO    (0x00U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM1 TRGO     
+#define ADC_ANY_CR_JTRGSEL_TIM1_CC4     (0x01U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM1 CC4      
+#define ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5 (0x02U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM1 CC4 and CC5  
+#define ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1 (0x03U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM2 CC1 and TIM4 CC1
+#define ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4 (0x04U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM3 CC4 and TIM5 CC4
+#define ADC_ANY_CR_JTRGSEL_TIM8_CC4     (0x05U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM8 CC4      
+#define ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5 (0x06U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM8 CC4 and CC5  
+#define ADC_ANY_CR_JTRGSEL_EXTI12       (0x07U << ADC_ANY_CR_JTRGSEL_Pos)       ///< EXTI12        
+
+#define ADC_ANY_CR_JTRGEN_Pos           (7)
+#define ADC_ANY_CR_JTRGEN               (0x01U << ADC_ANY_CR_JTRGEN_Pos)        ///< External trigger conversion mode for injected channels
+#define ADC_ANY_CR_JADST_Pos            (6)
+#define ADC_ANY_CR_JADST                (0x01U << ADC_ANY_CR_JADST_Pos)         ///< Start conversion of injected channels
+#define ADC_ANY_CR_JAUTO_Pos            (5)
+#define ADC_ANY_CR_JAUTO                (0x01U << ADC_ANY_CR_JAUTO_Pos)         ///<Automatic Injected group conversion
+#define ADC_ANY_CR_JEOSIE_Pos           (4)
+#define ADC_ANY_CR_JEOSIE               (0x01U << ADC_ANY_CR_JEOSIE_Pos)        ///< Interrupt enable the end of sequence conversion for injected channel
+#define ADC_ANY_CR_JEOCIE_Pos           (3)
+#define ADC_ANY_CR_JEOCIE               (0x01U << ADC_ANY_CR_JEOCIE_Pos)        ///< Interrupt enable the end of conversion for injected channel
+#define ADC_ANY_CR_JEOSMPIE_Pos         (2)
+#define ADC_ANY_CR_JEOSMPIE             (0x01U << ADC_ANY_CR_JEOSMPIE_Pos)      ///< Interrupt enable the end of sequence conversion for injected channel
+#define ADC_ANY_CR_JCEN_Pos             (1)
+#define ADC_ANY_CR_JCEN                 (0x01U << ADC_ANY_CR_JCEN_Pos)          ///< Injected channel enable
+
+#define ADC_ANY_CR_CHANY_MDEN_Pos       (0)
+#define ADC_ANY_CR_CHANY_MDEN           (0x01U << ADC_ANY_CR_CHANY_MDEN_Pos)    ///< Enable bits for any channel configuration mode:
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_SMPR1 mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_SMPR_SAMCTL_Pos             (0)                                     ///< Injection mode external trigger delay sampling off_set Position
+#define ADC_SMPR_SAMCTL_Msk             (0x0FU << ADC_SMPR_SAMCTL_Pos)          ///< Injection mode external trigger delay sampling mask for Value
+#define ADC_SMPR_SAMCTL_2_5             (0x00U << ADC_SMPR_SAMCTL_Pos)          ///< 2.5    cycle
+#define ADC_SMPR_SAMCTL_8_5             (0x01U << ADC_SMPR_SAMCTL_Pos)          ///< 8.5    cycle
+#define ADC_SMPR_SAMCTL_14_5            (0x02U << ADC_SMPR_SAMCTL_Pos)          ///< 14.5   cycle
+#define ADC_SMPR_SAMCTL_29_5            (0x03U << ADC_SMPR_SAMCTL_Pos)          ///< 29.5   cycle
+#define ADC_SMPR_SAMCTL_42_5            (0x04U << ADC_SMPR_SAMCTL_Pos)          ///< 42.5   cycle
+#define ADC_SMPR_SAMCTL_56_5            (0x05U << ADC_SMPR_SAMCTL_Pos)          ///< 56.5   cycle
+#define ADC_SMPR_SAMCTL_72_5            (0x06U << ADC_SMPR_SAMCTL_Pos)          ///< 72.5   cycle
+#define ADC_SMPR_SAMCTL_240_5           (0x07U << ADC_SMPR_SAMCTL_Pos)          ///< 240.5  cycle
+#define ADC_SMPR_SAMCTL_3_5             (0x08U << ADC_SMPR_SAMCTL_Pos)          ///< 3.5    cycle
+#define ADC_SMPR_SAMCTL_4_5             (0x09U << ADC_SMPR_SAMCTL_Pos)          ///< 4.5    cycle
+#define ADC_SMPR_SAMCTL_5_5             (0x0AU << ADC_SMPR_SAMCTL_Pos)          ///< 5.5    cycle
+#define ADC_SMPR_SAMCTL_6_5             (0x0BU << ADC_SMPR_SAMCTL_Pos)          ///< 6.5    cycle
+#define ADC_SMPR_SAMCTL_7_5             (0x0CU << ADC_SMPR_SAMCTL_Pos)          ///< 7.5    cycle
+
+
+#define ADC_SMPR1_SAMCTL7_Pos           (28)                                    ///< Injection mode external trigger delay sampling
+#define ADC_SMPR1_SAMCTL7_Msk           (0x0FU << ADC_SMPR1_SAMCTL7_Pos)        ///< Injection mode external trigger delay sampling mask for Value
+#define ADC_SMPR1_SAMCTL7_2_5           (0x00U << ADC_SMPR1_SAMCTL7_Pos)        ///< 2.5    cycle
+#define ADC_SMPR1_SAMCTL7_8_5           (0x01U << ADC_SMPR1_SAMCTL7_Pos)        ///< 8.5    cycle
+#define ADC_SMPR1_SAMCTL7_14_5          (0x02U << ADC_SMPR1_SAMCTL7_Pos)        ///< 14.5   cycle
+#define ADC_SMPR1_SAMCTL7_29_5          (0x03U << ADC_SMPR1_SAMCTL7_Pos)        ///< 29.5   cycle
+#define ADC_SMPR1_SAMCTL7_42_5          (0x04U << ADC_SMPR1_SAMCTL7_Pos)        ///< 42.5   cycle
+#define ADC_SMPR1_SAMCTL7_56_5          (0x05U << ADC_SMPR1_SAMCTL7_Pos)        ///< 56.5   cycle
+#define ADC_SMPR1_SAMCTL7_72_5          (0x06U << ADC_SMPR1_SAMCTL7_Pos)        ///< 72.5   cycle
+#define ADC_SMPR1_SAMCTL7_240_5         (0x07U << ADC_SMPR1_SAMCTL7_Pos)        ///< 240.5  cycle
+#define ADC_SMPR1_SAMCTL7_3_5           (0x08U << ADC_SMPR1_SAMCTL7_Pos)        ///< 3.5    cycle
+#define ADC_SMPR1_SAMCTL7_4_5           (0x09U << ADC_SMPR1_SAMCTL7_Pos)        ///< 4.5    cycle
+#define ADC_SMPR1_SAMCTL7_5_5           (0x0AU << ADC_SMPR1_SAMCTL7_Pos)        ///< 5.5    cycle
+#define ADC_SMPR1_SAMCTL7_6_5           (0x0BU << ADC_SMPR1_SAMCTL7_Pos)        ///< 6.5    cycle
+#define ADC_SMPR1_SAMCTL7_7_5           (0x0CU << ADC_SMPR1_SAMCTL7_Pos)        ///< 7.5    cycle
+#define ADC_SMPR1_SAMCTL6_Pos           (24)                                    ///< Injection mode external trigger delay sampling
+#define ADC_SMPR1_SAMCTL6_2_5           (0x00U << ADC_SMPR1_SAMCTL6_Pos)        ///< 2.5    cycle
+#define ADC_SMPR1_SAMCTL6_8_5           (0x01U << ADC_SMPR1_SAMCTL6_Pos)        ///< 8.5    cycle
+#define ADC_SMPR1_SAMCTL6_14_5          (0x02U << ADC_SMPR1_SAMCTL6_Pos)        ///< 14.5   cycle
+#define ADC_SMPR1_SAMCTL6_29_5          (0x03U << ADC_SMPR1_SAMCTL6_Pos)        ///< 29.5   cycle
+#define ADC_SMPR1_SAMCTL6_42_5          (0x04U << ADC_SMPR1_SAMCTL6_Pos)        ///< 42.5   cycle
+#define ADC_SMPR1_SAMCTL6_56_5          (0x05U << ADC_SMPR1_SAMCTL6_Pos)        ///< 56.5   cycle
+#define ADC_SMPR1_SAMCTL6_72_5          (0x06U << ADC_SMPR1_SAMCTL6_Pos)        ///< 72.5   cycle
+#define ADC_SMPR1_SAMCTL6_240_5         (0x07U << ADC_SMPR1_SAMCTL6_Pos)        ///< 240.5  cycle
+#define ADC_SMPR1_SAMCTL6_3_5           (0x08U << ADC_SMPR1_SAMCTL6_Pos)        ///< 3.5    cycle
+#define ADC_SMPR1_SAMCTL6_4_5           (0x09U << ADC_SMPR1_SAMCTL6_Pos)        ///< 4.5    cycle
+#define ADC_SMPR1_SAMCTL6_5_5           (0x0AU << ADC_SMPR1_SAMCTL6_Pos)        ///< 5.5    cycle
+#define ADC_SMPR1_SAMCTL6_6_5           (0x0BU << ADC_SMPR1_SAMCTL6_Pos)        ///< 6.5    cycle
+#define ADC_SMPR1_SAMCTL6_7_5           (0x0CU << ADC_SMPR1_SAMCTL6_Pos)        ///< 7.5    cycle
+#define ADC_SMPR1_SAMCTL5_Pos           (20)                                    ///< Injection mode external trigger delay sampling
+#define ADC_SMPR1_SAMCTL5_2_5           (0x00U << ADC_SMPR1_SAMCTL5_Pos)        ///< 2.5    cycle
+#define ADC_SMPR1_SAMCTL5_8_5           (0x01U << ADC_SMPR1_SAMCTL5_Pos)        ///< 8.5    cycle
+#define ADC_SMPR1_SAMCTL5_14_5          (0x02U << ADC_SMPR1_SAMCTL5_Pos)        ///< 14.5   cycle
+#define ADC_SMPR1_SAMCTL5_29_5          (0x03U << ADC_SMPR1_SAMCTL5_Pos)        ///< 29.5   cycle
+#define ADC_SMPR1_SAMCTL5_42_5          (0x04U << ADC_SMPR1_SAMCTL5_Pos)        ///< 42.5   cycle
+#define ADC_SMPR1_SAMCTL5_56_5          (0x05U << ADC_SMPR1_SAMCTL5_Pos)        ///< 56.5   cycle
+#define ADC_SMPR1_SAMCTL5_72_5          (0x06U << ADC_SMPR1_SAMCTL5_Pos)        ///< 72.5   cycle
+#define ADC_SMPR1_SAMCTL5_240_5         (0x07U << ADC_SMPR1_SAMCTL5_Pos)        ///< 240.5  cycle
+#define ADC_SMPR1_SAMCTL5_3_5           (0x08U << ADC_SMPR1_SAMCTL5_Pos)        ///< 3.5    cycle
+#define ADC_SMPR1_SAMCTL5_4_5           (0x09U << ADC_SMPR1_SAMCTL5_Pos)        ///< 4.5    cycle
+#define ADC_SMPR1_SAMCTL5_5_5           (0x0AU << ADC_SMPR1_SAMCTL5_Pos)        ///< 5.5    cycle
+#define ADC_SMPR1_SAMCTL5_6_5           (0x0BU << ADC_SMPR1_SAMCTL5_Pos)        ///< 6.5    cycle
+#define ADC_SMPR1_SAMCTL5_7_5           (0x0CU << ADC_SMPR1_SAMCTL5_Pos)        ///< 7.5    cycle
+#define ADC_SMPR1_SAMCTL4_Pos           (16)                                    ///< Injection mode external trigger delay sampling
+#define ADC_SMPR1_SAMCTL4_2_5           (0x00U << ADC_SMPR1_SAMCTL4_Pos)        ///< 2.5    cycle
+#define ADC_SMPR1_SAMCTL4_8_5           (0x01U << ADC_SMPR1_SAMCTL4_Pos)        ///< 8.5    cycle
+#define ADC_SMPR1_SAMCTL4_14_5          (0x02U << ADC_SMPR1_SAMCTL4_Pos)        ///< 14.5   cycle
+#define ADC_SMPR1_SAMCTL4_29_5          (0x03U << ADC_SMPR1_SAMCTL4_Pos)        ///< 29.5   cycle
+#define ADC_SMPR1_SAMCTL4_42_5          (0x04U << ADC_SMPR1_SAMCTL4_Pos)        ///< 42.5   cycle
+#define ADC_SMPR1_SAMCTL4_56_5          (0x05U << ADC_SMPR1_SAMCTL4_Pos)        ///< 56.5   cycle
+#define ADC_SMPR1_SAMCTL4_72_5          (0x06U << ADC_SMPR1_SAMCTL4_Pos)        ///< 72.5   cycle
+#define ADC_SMPR1_SAMCTL4_240_5         (0x07U << ADC_SMPR1_SAMCTL4_Pos)        ///< 240.5  cycle
+#define ADC_SMPR1_SAMCTL4_3_5           (0x08U << ADC_SMPR1_SAMCTL4_Pos)        ///< 3.5    cycle
+#define ADC_SMPR1_SAMCTL4_4_5           (0x09U << ADC_SMPR1_SAMCTL4_Pos)        ///< 4.5    cycle
+#define ADC_SMPR1_SAMCTL4_5_5           (0x0AU << ADC_SMPR1_SAMCTL4_Pos)        ///< 5.5    cycle
+#define ADC_SMPR1_SAMCTL4_6_5           (0x0BU << ADC_SMPR1_SAMCTL4_Pos)        ///< 6.5    cycle
+#define ADC_SMPR1_SAMCTL4_7_5           (0x0CU << ADC_SMPR1_SAMCTL4_Pos)        ///< 7.5    cycle
+#define ADC_SMPR1_SAMCTL3_Pos           (12)                                    ///< Injection mode external trigger delay sampling
+#define ADC_SMPR1_SAMCTL3_2_5           (0x00U << ADC_SMPR1_SAMCTL3_Pos)        ///< 2.5    cycle
+#define ADC_SMPR1_SAMCTL3_8_5           (0x01U << ADC_SMPR1_SAMCTL3_Pos)        ///< 8.5    cycle
+#define ADC_SMPR1_SAMCTL3_14_5          (0x02U << ADC_SMPR1_SAMCTL3_Pos)        ///< 14.5   cycle
+#define ADC_SMPR1_SAMCTL3_29_5          (0x03U << ADC_SMPR1_SAMCTL3_Pos)        ///< 29.5   cycle
+#define ADC_SMPR1_SAMCTL3_42_5          (0x04U << ADC_SMPR1_SAMCTL3_Pos)        ///< 42.5   cycle
+#define ADC_SMPR1_SAMCTL3_56_5          (0x05U << ADC_SMPR1_SAMCTL3_Pos)        ///< 56.5   cycle
+#define ADC_SMPR1_SAMCTL3_72_5          (0x06U << ADC_SMPR1_SAMCTL3_Pos)        ///< 72.5   cycle
+#define ADC_SMPR1_SAMCTL3_240_5         (0x07U << ADC_SMPR1_SAMCTL3_Pos)        ///< 240.5  cycle
+#define ADC_SMPR1_SAMCTL3_3_5           (0x08U << ADC_SMPR1_SAMCTL3_Pos)        ///< 3.5    cycle
+#define ADC_SMPR1_SAMCTL3_4_5           (0x09U << ADC_SMPR1_SAMCTL3_Pos)        ///< 4.5    cycle
+#define ADC_SMPR1_SAMCTL3_5_5           (0x0AU << ADC_SMPR1_SAMCTL3_Pos)        ///< 5.5    cycle
+#define ADC_SMPR1_SAMCTL3_6_5           (0x0BU << ADC_SMPR1_SAMCTL3_Pos)        ///< 6.5    cycle
+#define ADC_SMPR1_SAMCTL3_7_5           (0x0CU << ADC_SMPR1_SAMCTL3_Pos)        ///< 7.5    cycle
+#define ADC_SMPR1_SAMCTL2_Pos           (8)                                     ///< Injection mode external trigger delay sampling
+#define ADC_SMPR1_SAMCTL2_2_5           (0x00U << ADC_SMPR1_SAMCTL2_Pos)        ///< 2.5    cycle
+#define ADC_SMPR1_SAMCTL2_8_5           (0x01U << ADC_SMPR1_SAMCTL2_Pos)        ///< 8.5    cycle
+#define ADC_SMPR1_SAMCTL2_14_5          (0x02U << ADC_SMPR1_SAMCTL2_Pos)        ///< 14.5   cycle
+#define ADC_SMPR1_SAMCTL2_29_5          (0x03U << ADC_SMPR1_SAMCTL2_Pos)        ///< 29.5   cycle
+#define ADC_SMPR1_SAMCTL2_42_5          (0x04U << ADC_SMPR1_SAMCTL2_Pos)        ///< 42.5   cycle
+#define ADC_SMPR1_SAMCTL2_56_5          (0x05U << ADC_SMPR1_SAMCTL2_Pos)        ///< 56.5   cycle
+#define ADC_SMPR1_SAMCTL2_72_5          (0x06U << ADC_SMPR1_SAMCTL2_Pos)        ///< 72.5   cycle
+#define ADC_SMPR1_SAMCTL2_240_5         (0x07U << ADC_SMPR1_SAMCTL2_Pos)        ///< 240.5  cycle
+#define ADC_SMPR1_SAMCTL2_3_5           (0x08U << ADC_SMPR1_SAMCTL2_Pos)        ///< 3.5    cycle
+#define ADC_SMPR1_SAMCTL2_4_5           (0x09U << ADC_SMPR1_SAMCTL2_Pos)        ///< 4.5    cycle
+#define ADC_SMPR1_SAMCTL2_5_5           (0x0AU << ADC_SMPR1_SAMCTL2_Pos)        ///< 5.5    cycle
+#define ADC_SMPR1_SAMCTL2_6_5           (0x0BU << ADC_SMPR1_SAMCTL2_Pos)        ///< 6.5    cycle
+#define ADC_SMPR1_SAMCTL2_7_5           (0x0CU << ADC_SMPR1_SAMCTL2_Pos)        ///< 7.5    cycle
+#define ADC_SMPR1_SAMCTL1_Pos           (4)                                     ///< Injection mode external trigger delay sampling
+#define ADC_SMPR1_SAMCTL1_2_5           (0x00U << ADC_SMPR1_SAMCTL1_Pos)        ///< 2.5    cycle
+#define ADC_SMPR1_SAMCTL1_8_5           (0x01U << ADC_SMPR1_SAMCTL1_Pos)        ///< 8.5    cycle
+#define ADC_SMPR1_SAMCTL1_14_5          (0x02U << ADC_SMPR1_SAMCTL1_Pos)        ///< 14.5   cycle
+#define ADC_SMPR1_SAMCTL1_29_5          (0x03U << ADC_SMPR1_SAMCTL1_Pos)        ///< 29.5   cycle
+#define ADC_SMPR1_SAMCTL1_42_5          (0x04U << ADC_SMPR1_SAMCTL1_Pos)        ///< 42.5   cycle
+#define ADC_SMPR1_SAMCTL1_56_5          (0x05U << ADC_SMPR1_SAMCTL1_Pos)        ///< 56.5   cycle
+#define ADC_SMPR1_SAMCTL1_72_5          (0x06U << ADC_SMPR1_SAMCTL1_Pos)        ///< 72.5   cycle
+#define ADC_SMPR1_SAMCTL1_240_5         (0x07U << ADC_SMPR1_SAMCTL1_Pos)        ///< 240.5  cycle
+#define ADC_SMPR1_SAMCTL1_3_5           (0x08U << ADC_SMPR1_SAMCTL1_Pos)        ///< 3.5    cycle
+#define ADC_SMPR1_SAMCTL1_4_5           (0x09U << ADC_SMPR1_SAMCTL1_Pos)        ///< 4.5    cycle
+#define ADC_SMPR1_SAMCTL1_5_5           (0x0AU << ADC_SMPR1_SAMCTL1_Pos)        ///< 5.5    cycle
+#define ADC_SMPR1_SAMCTL1_6_5           (0x0BU << ADC_SMPR1_SAMCTL1_Pos)        ///< 6.5    cycle
+#define ADC_SMPR1_SAMCTL1_7_5           (0x0CU << ADC_SMPR1_SAMCTL1_Pos)        ///< 7.5    cycle
+#define ADC_SMPR1_SAMCTL0_Pos           (0)                                     ///< Injection mode external trigger delay sampling
+#define ADC_SMPR1_SAMCTL0_2_5           (0x00U << ADC_SMPR1_SAMCTL0_Pos)        ///< 2.5    cycle
+#define ADC_SMPR1_SAMCTL0_8_5           (0x01U << ADC_SMPR1_SAMCTL0_Pos)        ///< 8.5    cycle
+#define ADC_SMPR1_SAMCTL0_14_5          (0x02U << ADC_SMPR1_SAMCTL0_Pos)        ///< 14.5   cycle
+#define ADC_SMPR1_SAMCTL0_29_5          (0x03U << ADC_SMPR1_SAMCTL0_Pos)        ///< 29.5   cycle
+#define ADC_SMPR1_SAMCTL0_42_5          (0x04U << ADC_SMPR1_SAMCTL0_Pos)        ///< 42.5   cycle
+#define ADC_SMPR1_SAMCTL0_56_5          (0x05U << ADC_SMPR1_SAMCTL0_Pos)        ///< 56.5   cycle
+#define ADC_SMPR1_SAMCTL0_72_5          (0x06U << ADC_SMPR1_SAMCTL0_Pos)        ///< 72.5   cycle
+#define ADC_SMPR1_SAMCTL0_240_5         (0x07U << ADC_SMPR1_SAMCTL0_Pos)        ///< 240.5  cycle
+#define ADC_SMPR1_SAMCTL0_3_5           (0x08U << ADC_SMPR1_SAMCTL0_Pos)        ///< 3.5    cycle
+#define ADC_SMPR1_SAMCTL0_4_5           (0x09U << ADC_SMPR1_SAMCTL0_Pos)        ///< 4.5    cycle
+#define ADC_SMPR1_SAMCTL0_5_5           (0x0AU << ADC_SMPR1_SAMCTL0_Pos)        ///< 5.5    cycle
+#define ADC_SMPR1_SAMCTL0_6_5           (0x0BU << ADC_SMPR1_SAMCTL0_Pos)        ///< 6.5    cycle
+#define ADC_SMPR1_SAMCTL0_7_5           (0x0CU << ADC_SMPR1_SAMCTL0_Pos)        ///< 7.5    cycle
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_SMPR2 mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_SMPR2_SAMCTL15_Pos          (28)                                     ///< Injection mode external trigger delay sampling
+#define ADC_SMPR2_SAMCTL15_2_5          (0x00U << ADC_SMPR2_SAMCTL15_Pos)        ///< 2.5    cycle
+#define ADC_SMPR2_SAMCTL15_8_5          (0x01U << ADC_SMPR2_SAMCTL15_Pos)        ///< 8.5    cycle
+#define ADC_SMPR2_SAMCTL15_14_5         (0x02U << ADC_SMPR2_SAMCTL15_Pos)        ///< 14.5   cycle
+#define ADC_SMPR2_SAMCTL15_29_5         (0x03U << ADC_SMPR2_SAMCTL15_Pos)        ///< 29.5   cycle
+#define ADC_SMPR2_SAMCTL15_42_5         (0x04U << ADC_SMPR2_SAMCTL15_Pos)        ///< 42.5   cycle
+#define ADC_SMPR2_SAMCTL15_56_5         (0x05U << ADC_SMPR2_SAMCTL15_Pos)        ///< 56.5   cycle
+#define ADC_SMPR2_SAMCTL15_72_5         (0x06U << ADC_SMPR2_SAMCTL15_Pos)        ///< 72.5   cycle
+#define ADC_SMPR2_SAMCTL15_240_5        (0x07U << ADC_SMPR2_SAMCTL15_Pos)        ///< 240.5  cycle
+#define ADC_SMPR2_SAMCTL15_3_5          (0x08U << ADC_SMPR2_SAMCTL15_Pos)        ///< 3.5    cycle
+#define ADC_SMPR2_SAMCTL15_4_5          (0x09U << ADC_SMPR2_SAMCTL15_Pos)        ///< 4.5    cycle
+#define ADC_SMPR2_SAMCTL15_5_5          (0x0AU << ADC_SMPR2_SAMCTL15_Pos)        ///< 5.5    cycle
+#define ADC_SMPR2_SAMCTL15_6_5          (0x0BU << ADC_SMPR2_SAMCTL15_Pos)        ///< 6.5    cycle
+#define ADC_SMPR2_SAMCTL15_7_5          (0x0CU << ADC_SMPR2_SAMCTL15_Pos)        ///< 7.5    cycle
+#define ADC_SMPR2_SAMCTL14_Pos          (24)                                    ///< Injection mode external trigger delay sampling
+#define ADC_SMPR2_SAMCTL14_2_5          (0x00U << ADC_SMPR2_SAMCTL14_Pos)        ///< 2.5    cycle
+#define ADC_SMPR2_SAMCTL14_8_5          (0x01U << ADC_SMPR2_SAMCTL14_Pos)        ///< 8.5    cycle
+#define ADC_SMPR2_SAMCTL14_14_5         (0x02U << ADC_SMPR2_SAMCTL14_Pos)        ///< 14.5   cycle
+#define ADC_SMPR2_SAMCTL14_29_5         (0x03U << ADC_SMPR2_SAMCTL14_Pos)        ///< 29.5   cycle
+#define ADC_SMPR2_SAMCTL14_42_5         (0x04U << ADC_SMPR2_SAMCTL14_Pos)        ///< 42.5   cycle
+#define ADC_SMPR2_SAMCTL14_56_5         (0x05U << ADC_SMPR2_SAMCTL14_Pos)        ///< 56.5   cycle
+#define ADC_SMPR2_SAMCTL14_72_5         (0x06U << ADC_SMPR2_SAMCTL14_Pos)        ///< 72.5   cycle
+#define ADC_SMPR2_SAMCTL14_240_5        (0x07U << ADC_SMPR2_SAMCTL14_Pos)        ///< 240.5  cycle
+#define ADC_SMPR2_SAMCTL14_3_5          (0x08U << ADC_SMPR2_SAMCTL14_Pos)        ///< 3.5    cycle
+#define ADC_SMPR2_SAMCTL14_4_5          (0x09U << ADC_SMPR2_SAMCTL14_Pos)        ///< 4.5    cycle
+#define ADC_SMPR2_SAMCTL14_5_5          (0x0AU << ADC_SMPR2_SAMCTL14_Pos)        ///< 5.5    cycle
+#define ADC_SMPR2_SAMCTL14_6_5          (0x0BU << ADC_SMPR2_SAMCTL14_Pos)        ///< 6.5    cycle
+#define ADC_SMPR2_SAMCTL14_7_5          (0x0CU << ADC_SMPR2_SAMCTL14_Pos)        ///< 7.5    cycle
+#define ADC_SMPR2_SAMCTL13_Pos          (20)                                    ///< Injection mode external trigger delay sampling
+#define ADC_SMPR2_SAMCTL13_2_5          (0x00U << ADC_SMPR2_SAMCTL13_Pos)        ///< 2.5    cycle
+#define ADC_SMPR2_SAMCTL13_8_5          (0x01U << ADC_SMPR2_SAMCTL13_Pos)        ///< 8.5    cycle
+#define ADC_SMPR2_SAMCTL13_14_5         (0x02U << ADC_SMPR2_SAMCTL13_Pos)        ///< 14.5   cycle
+#define ADC_SMPR2_SAMCTL13_29_5         (0x03U << ADC_SMPR2_SAMCTL13_Pos)        ///< 29.5   cycle
+#define ADC_SMPR2_SAMCTL13_42_5         (0x04U << ADC_SMPR2_SAMCTL13_Pos)        ///< 42.5   cycle
+#define ADC_SMPR2_SAMCTL13_56_5         (0x05U << ADC_SMPR2_SAMCTL13_Pos)        ///< 56.5   cycle
+#define ADC_SMPR2_SAMCTL13_72_5         (0x06U << ADC_SMPR2_SAMCTL13_Pos)        ///< 72.5   cycle
+#define ADC_SMPR2_SAMCTL13_240_5        (0x07U << ADC_SMPR2_SAMCTL13_Pos)        ///< 240.5  cycle
+#define ADC_SMPR2_SAMCTL13_3_5          (0x08U << ADC_SMPR2_SAMCTL13_Pos)        ///< 3.5    cycle
+#define ADC_SMPR2_SAMCTL13_4_5          (0x09U << ADC_SMPR2_SAMCTL13_Pos)        ///< 4.5    cycle
+#define ADC_SMPR2_SAMCTL13_5_5          (0x0AU << ADC_SMPR2_SAMCTL13_Pos)        ///< 5.5    cycle
+#define ADC_SMPR2_SAMCTL13_6_5          (0x0BU << ADC_SMPR2_SAMCTL13_Pos)        ///< 6.5    cycle
+#define ADC_SMPR2_SAMCTL13_7_5          (0x0CU << ADC_SMPR2_SAMCTL13_Pos)        ///< 7.5    cycle
+#define ADC_SMPR2_SAMCTL12_Pos          (16)                                    ///< Injection mode external trigger delay sampling
+#define ADC_SMPR2_SAMCTL12_2_5          (0x00U << ADC_SMPR2_SAMCTL12_Pos)        ///< 2.5    cycle
+#define ADC_SMPR2_SAMCTL12_8_5          (0x01U << ADC_SMPR2_SAMCTL12_Pos)        ///< 8.5    cycle
+#define ADC_SMPR2_SAMCTL12_14_5         (0x02U << ADC_SMPR2_SAMCTL12_Pos)        ///< 14.5   cycle
+#define ADC_SMPR2_SAMCTL12_29_5         (0x03U << ADC_SMPR2_SAMCTL12_Pos)        ///< 29.5   cycle
+#define ADC_SMPR2_SAMCTL12_42_5         (0x04U << ADC_SMPR2_SAMCTL12_Pos)        ///< 42.5   cycle
+#define ADC_SMPR2_SAMCTL12_56_5         (0x05U << ADC_SMPR2_SAMCTL12_Pos)        ///< 56.5   cycle
+#define ADC_SMPR2_SAMCTL12_72_5         (0x06U << ADC_SMPR2_SAMCTL12_Pos)        ///< 72.5   cycle
+#define ADC_SMPR2_SAMCTL12_240_5        (0x07U << ADC_SMPR2_SAMCTL12_Pos)        ///< 240.5  cycle
+#define ADC_SMPR2_SAMCTL12_3_5          (0x08U << ADC_SMPR2_SAMCTL12_Pos)        ///< 3.5    cycle
+#define ADC_SMPR2_SAMCTL12_4_5          (0x09U << ADC_SMPR2_SAMCTL12_Pos)        ///< 4.5    cycle
+#define ADC_SMPR2_SAMCTL12_5_5          (0x0AU << ADC_SMPR2_SAMCTL12_Pos)        ///< 5.5    cycle
+#define ADC_SMPR2_SAMCTL12_6_5          (0x0BU << ADC_SMPR2_SAMCTL12_Pos)        ///< 6.5    cycle
+#define ADC_SMPR2_SAMCTL12_7_5          (0x0CU << ADC_SMPR2_SAMCTL12_Pos)        ///< 7.5    cycle
+#define ADC_SMPR2_SAMCTL11_Pos          (12)                                    ///< Injection mode external trigger delay sampling
+#define ADC_SMPR2_SAMCTL11_2_5          (0x00U << ADC_SMPR2_SAMCTL11_Pos)        ///< 2.5    cycle
+#define ADC_SMPR2_SAMCTL11_8_5          (0x01U << ADC_SMPR2_SAMCTL11_Pos)        ///< 8.5    cycle
+#define ADC_SMPR2_SAMCTL11_14_5         (0x02U << ADC_SMPR2_SAMCTL11_Pos)        ///< 14.5   cycle
+#define ADC_SMPR2_SAMCTL11_29_5         (0x03U << ADC_SMPR2_SAMCTL11_Pos)        ///< 29.5   cycle
+#define ADC_SMPR2_SAMCTL11_42_5         (0x04U << ADC_SMPR2_SAMCTL11_Pos)        ///< 42.5   cycle
+#define ADC_SMPR2_SAMCTL11_56_5         (0x05U << ADC_SMPR2_SAMCTL11_Pos)        ///< 56.5   cycle
+#define ADC_SMPR2_SAMCTL11_72_5         (0x06U << ADC_SMPR2_SAMCTL11_Pos)        ///< 72.5   cycle
+#define ADC_SMPR2_SAMCTL11_240_5        (0x07U << ADC_SMPR2_SAMCTL11_Pos)        ///< 240.5  cycle
+#define ADC_SMPR2_SAMCTL11_3_5          (0x08U << ADC_SMPR2_SAMCTL11_Pos)        ///< 3.5    cycle
+#define ADC_SMPR2_SAMCTL11_4_5          (0x09U << ADC_SMPR2_SAMCTL11_Pos)        ///< 4.5    cycle
+#define ADC_SMPR2_SAMCTL11_5_5          (0x0AU << ADC_SMPR2_SAMCTL11_Pos)        ///< 5.5    cycle
+#define ADC_SMPR2_SAMCTL11_6_5          (0x0BU << ADC_SMPR2_SAMCTL11_Pos)        ///< 6.5    cycle
+#define ADC_SMPR2_SAMCTL11_7_5          (0x0CU << ADC_SMPR2_SAMCTL11_Pos)        ///< 7.5    cycle
+#define ADC_SMPR2_SAMCTL10_Pos          (8)                                     ///< Injection mode external trigger delay sampling
+#define ADC_SMPR2_SAMCTL10_2_5          (0x00U << ADC_SMPR2_SAMCTL10_Pos)        ///< 2.5    cycle
+#define ADC_SMPR2_SAMCTL10_8_5          (0x01U << ADC_SMPR2_SAMCTL10_Pos)        ///< 8.5    cycle
+#define ADC_SMPR2_SAMCTL10_14_5         (0x02U << ADC_SMPR2_SAMCTL10_Pos)        ///< 14.5   cycle
+#define ADC_SMPR2_SAMCTL10_29_5         (0x03U << ADC_SMPR2_SAMCTL10_Pos)        ///< 29.5   cycle
+#define ADC_SMPR2_SAMCTL10_42_5         (0x04U << ADC_SMPR2_SAMCTL10_Pos)        ///< 42.5   cycle
+#define ADC_SMPR2_SAMCTL10_56_5         (0x05U << ADC_SMPR2_SAMCTL10_Pos)        ///< 56.5   cycle
+#define ADC_SMPR2_SAMCTL10_72_5         (0x06U << ADC_SMPR2_SAMCTL10_Pos)        ///< 72.5   cycle
+#define ADC_SMPR2_SAMCTL10_240_5        (0x07U << ADC_SMPR2_SAMCTL10_Pos)        ///< 240.5  cycle
+#define ADC_SMPR2_SAMCTL10_3_5          (0x08U << ADC_SMPR2_SAMCTL10_Pos)        ///< 3.5    cycle
+#define ADC_SMPR2_SAMCTL10_4_5          (0x09U << ADC_SMPR2_SAMCTL10_Pos)        ///< 4.5    cycle
+#define ADC_SMPR2_SAMCTL10_5_5          (0x0AU << ADC_SMPR2_SAMCTL10_Pos)        ///< 5.5    cycle
+#define ADC_SMPR2_SAMCTL10_6_5          (0x0BU << ADC_SMPR2_SAMCTL10_Pos)        ///< 6.5    cycle
+#define ADC_SMPR2_SAMCTL10_7_5          (0x0CU << ADC_SMPR2_SAMCTL10_Pos)        ///< 7.5    cycle
+#define ADC_SMPR2_SAMCTL9_Pos           (4)                                     ///< Injection mode external trigger delay sampling
+#define ADC_SMPR2_SAMCTL9_2_5           (0x00U << ADC_SMPR2_SAMCTL9_Pos)        ///< 2.5    cycle
+#define ADC_SMPR2_SAMCTL9_8_5           (0x01U << ADC_SMPR2_SAMCTL9_Pos)        ///< 8.5    cycle
+#define ADC_SMPR2_SAMCTL9_14_5          (0x02U << ADC_SMPR2_SAMCTL9_Pos)        ///< 14.5   cycle
+#define ADC_SMPR2_SAMCTL9_29_5          (0x03U << ADC_SMPR2_SAMCTL9_Pos)        ///< 29.5   cycle
+#define ADC_SMPR2_SAMCTL9_42_5          (0x04U << ADC_SMPR2_SAMCTL9_Pos)        ///< 42.5   cycle
+#define ADC_SMPR2_SAMCTL9_56_5          (0x05U << ADC_SMPR2_SAMCTL9_Pos)        ///< 56.5   cycle
+#define ADC_SMPR2_SAMCTL9_72_5          (0x06U << ADC_SMPR2_SAMCTL9_Pos)        ///< 72.5   cycle
+#define ADC_SMPR2_SAMCTL9_240_5         (0x07U << ADC_SMPR2_SAMCTL9_Pos)        ///< 240.5  cycle
+#define ADC_SMPR2_SAMCTL9_3_5           (0x08U << ADC_SMPR2_SAMCTL9_Pos)        ///< 3.5    cycle
+#define ADC_SMPR2_SAMCTL9_4_5           (0x09U << ADC_SMPR2_SAMCTL9_Pos)        ///< 4.5    cycle
+#define ADC_SMPR2_SAMCTL9_5_5           (0x0AU << ADC_SMPR2_SAMCTL9_Pos)        ///< 5.5    cycle
+#define ADC_SMPR2_SAMCTL9_6_5           (0x0BU << ADC_SMPR2_SAMCTL9_Pos)        ///< 6.5    cycle
+#define ADC_SMPR2_SAMCTL9_7_5           (0x0CU << ADC_SMPR2_SAMCTL9_Pos)        ///< 7.5    cycle
+#define ADC_SMPR2_SAMCTL8_Pos           (0)                                     ///< Injection mode external trigger delay sampling
+#define ADC_SMPR2_SAMCTL8_2_5           (0x00U << ADC_SMPR2_SAMCTL8_Pos)        ///< 2.5    cycle
+#define ADC_SMPR2_SAMCTL8_8_5           (0x01U << ADC_SMPR2_SAMCTL8_Pos)        ///< 8.5    cycle
+#define ADC_SMPR2_SAMCTL8_14_5          (0x02U << ADC_SMPR2_SAMCTL8_Pos)        ///< 14.5   cycle
+#define ADC_SMPR2_SAMCTL8_29_5          (0x03U << ADC_SMPR2_SAMCTL8_Pos)        ///< 29.5   cycle
+#define ADC_SMPR2_SAMCTL8_42_5          (0x04U << ADC_SMPR2_SAMCTL8_Pos)        ///< 42.5   cycle
+#define ADC_SMPR2_SAMCTL8_56_5          (0x05U << ADC_SMPR2_SAMCTL8_Pos)        ///< 56.5   cycle
+#define ADC_SMPR2_SAMCTL8_72_5          (0x06U << ADC_SMPR2_SAMCTL8_Pos)        ///< 72.5   cycle
+#define ADC_SMPR2_SAMCTL8_240_5         (0x07U << ADC_SMPR2_SAMCTL8_Pos)        ///< 240.5  cycle
+#define ADC_SMPR2_SAMCTL8_3_5           (0x08U << ADC_SMPR2_SAMCTL8_Pos)        ///< 3.5    cycle
+#define ADC_SMPR2_SAMCTL8_4_5           (0x09U << ADC_SMPR2_SAMCTL8_Pos)        ///< 4.5    cycle
+#define ADC_SMPR2_SAMCTL8_5_5           (0x0AU << ADC_SMPR2_SAMCTL8_Pos)        ///< 5.5    cycle
+#define ADC_SMPR2_SAMCTL8_6_5           (0x0BU << ADC_SMPR2_SAMCTL8_Pos)        ///< 6.5    cycle
+#define ADC_SMPR2_SAMCTL8_7_5           (0x0CU << ADC_SMPR2_SAMCTL8_Pos)        ///< 7.5    cycle
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_JOFR0 mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_JOFR0_JOFR                  (0xFFFU)                                ///< Compensates for the A/D conversion results of the injected channel 0
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_JOFR1 mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_JOFR1_JOFR                  (0xFFFU)                                ///< Compensates for the A/D conversion results of the injected channel 1
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_JOFR2 mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_JOFR2_JOFR                  (0xFFFU)                                ///< Compensates for the A/D conversion results of the injected channel 2
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_JOFR3 mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_JOFR3_JOFR                  (0xFFFU)                                ///< Compensates for the A/D conversion results of the injected channel 3
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_JSQR mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_JSQR_JSQ0_Pos            (0)                                          ///< 1st conversion in injected sequence
+#define ADC_JSQR_JSQ0_0             (0x01U << ADC_JSQR_JSQ0_Pos)                  ///< Bit 0
+#define ADC_JSQR_JSQ0_1             (0x02U << ADC_JSQR_JSQ0_Pos)                  ///< Bit 1
+#define ADC_JSQR_JSQ0_2             (0x04U << ADC_JSQR_JSQ0_Pos)                  ///< Bit 2
+#define ADC_JSQR_JSQ0_3             (0x08U << ADC_JSQR_JSQ0_Pos)                  ///< Bit 3
+#define ADC_JSQR_JSQ0_4             (0x10U << ADC_JSQR_JSQ0_Pos)                  ///< Bit 4
+#define ADC_JSQR_JSQ1_Pos           (5 )                                          ///< 2st conversion in injected sequence
+#define ADC_JSQR_JSQ1_0             (0x01U << ADC_JSQR_JSQ1_Pos)                  ///< Bit 0
+#define ADC_JSQR_JSQ1_1             (0x02U << ADC_JSQR_JSQ1_Pos)                  ///< Bit 1
+#define ADC_JSQR_JSQ1_2             (0x04U << ADC_JSQR_JSQ1_Pos)                  ///< Bit 2
+#define ADC_JSQR_JSQ1_3             (0x08U << ADC_JSQR_JSQ1_Pos)                  ///< Bit 3
+#define ADC_JSQR_JSQ1_4             (0x10U << ADC_JSQR_JSQ1_Pos)                  ///< Bit 4
+#define ADC_JSQR_JSQ2_Pos           (10)                                          ///< 3st conversion in injected sequence
+#define ADC_JSQR_JSQ2_0             (0x01U << ADC_JSQR_JSQ2_Pos)                  ///< Bit 0
+#define ADC_JSQR_JSQ2_1             (0x02U << ADC_JSQR_JSQ2_Pos)                  ///< Bit 1
+#define ADC_JSQR_JSQ2_2             (0x04U << ADC_JSQR_JSQ2_Pos)                  ///< Bit 2
+#define ADC_JSQR_JSQ2_3             (0x08U << ADC_JSQR_JSQ2_Pos)                  ///< Bit 3
+#define ADC_JSQR_JSQ2_4             (0x10U << ADC_JSQR_JSQ2_Pos)                  ///< Bit 4
+#define ADC_JSQR_JSQ3_Pos           (15)                                          ///< 4st conversion in injected sequence
+#define ADC_JSQR_JSQ3_0             (0x01U << ADC_JSQR_JSQ3_Pos)                  ///< Bit 0
+#define ADC_JSQR_JSQ3_1             (0x02U << ADC_JSQR_JSQ3_Pos)                  ///< Bit 1
+#define ADC_JSQR_JSQ3_2             (0x04U << ADC_JSQR_JSQ3_Pos)                  ///< Bit 2
+#define ADC_JSQR_JSQ3_3             (0x08U << ADC_JSQR_JSQ3_Pos)                  ///< Bit 3
+#define ADC_JSQR_JSQ3_4             (0x10U << ADC_JSQR_JSQ3_Pos)                  ///< Bit 4
+
+#define ADC_JSQR_JL_Pos             (20)                                          ///< Injected Sequence length
+#define ADC_JSQR_JL_0               (0x01U << ADC_JSQR_JL_Pos)                    ///< Bit 0
+#define ADC_JSQR_JL_1               (0x02U << ADC_JSQR_JL_Pos)                    ///< Bit 1
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_JDATA mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_JDATA_JVALID_Pos          (22)
+#define ADC_JDATA_JVALID              (0x01U << ADC_JDATA_JVALID_Pos)               ///< Valid flag
+#define ADC_JDATA_JOVERRUN_Pos        (21)
+#define ADC_JDATA_JOVERRUN            (0x01U << ADC_JDATA_JOVERRUN_Pos)             ///< Overrun flag
+#define ADC_JDATA_JCHANNELSEL_Pos     (16)
+#define ADC_JDATA_JCHANNELSEL         (0xFFU << ADC_JDATA_JCHANNELSEL_Pos)          ///< Channel selection
+#define ADC_JDATA_JDATA_Pos           (0)
+#define ADC_JDATA_JDATA               (0xFFFFU << ADC_JSQR_JSQ0_Pos)                ///< Transfer data
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_JDR0 mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_JDR0_JVALID_Pos          (22)
+#define ADC_JDR0_JVALID              (0x01U << ADC_JDATA_JVALID_Pos)               ///< Valid flag
+#define ADC_JDR0_JOVERRUN_Pos        (21)
+#define ADC_JDR0_JOVERRUN            (0x01U << ADC_JDATA_JOVERRUN_Pos)             ///< Overrun flag
+#define ADC_JDR0_JDATA_Pos           (0)
+#define ADC_JDR0_JDATA               (0xFFFFU << ADC_JSQR_JSQ0_Pos)                ///< Transfer data
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_JDR1 mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_JDR1_JVALID_Pos          (22)
+#define ADC_JDR1_JVALID              (0x01U << ADC_JDATA_JVALID_Pos)               ///< Valid flag
+#define ADC_JDR1_JOVERRUN_Pos        (21)
+#define ADC_JDR1_JOVERRUN            (0x01U << ADC_JDATA_JOVERRUN_Pos)             ///< Overrun flag
+#define ADC_JDR1_JDATA_Pos           (0)
+#define ADC_JDR1_JDATA               (0xFFFFU << ADC_JSQR_JSQ0_Pos)                ///< Transfer data
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_JDR2 mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_JDR2_JVALID_Pos          (22)
+#define ADC_JDR2_JVALID              (0x01U << ADC_JDATA_JVALID_Pos)               ///< Valid flag
+#define ADC_JDR2_JOVERRUN_Pos        (21)
+#define ADC_JDR2_JOVERRUN            (0x01U << ADC_JDATA_JOVERRUN_Pos)             ///< Overrun flag
+#define ADC_JDR2_JDATA_Pos           (0)
+#define ADC_JDR2_JDATA               (0xFFFFU << ADC_JSQR_JSQ0_Pos)                ///< Transfer data
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ADC_JDR3 mode enable Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ADC_JDR3_JVALID_Pos          (22)
+#define ADC_JDR3_JVALID              (0x01U << ADC_JDATA_JVALID_Pos)               ///< Valid flag
+#define ADC_JDR3_JOVERRUN_Pos        (21)
+#define ADC_JDR3_JOVERRUN            (0x01U << ADC_JDATA_JOVERRUN_Pos)             ///< Overrun flag
+#define ADC_JDR3_JDATA_Pos           (0)
+#define ADC_JDR3_JDATA               (0xFFFFU << ADC_JSQR_JSQ0_Pos)                ///< Transfer data
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h
new file mode 100644
index 000000000..d4bd55188
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h
@@ -0,0 +1,147 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_bkp.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_BKP_H
+#define __REG_BKP_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+#define BKP_BASE                        (APB1PERIPH_BASE + 0x2840)              ///< Base Address: 0x40002840
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+#define BKP_NUMBER  20
+
+typedef struct {
+    __IO u32 RTCCR;                                                             ///< RTC clock calibration register,                offset: 0x00
+    __IO u32 CR;                                                                ///< BKP control register,                          offset: 0x04
+    __IO u32 CSR;                                                               ///< BKP control/status register,                   offset: 0x08
+    __IO u32 RESERVED0;                                                         ///< Reserved,                                      offset: 0x0C
+    __IO u32 DR1;                                                               ///< BKP data register 1,                           offset: 0x10
+    __IO u32 DR2;                                                               ///< BKP data register 2,                           offset: 0x14
+    __IO u32 DR3;                                                               ///< BKP data register 3,                           offset: 0x18
+    __IO u32 DR4;                                                               ///< BKP data register 4,                           offset: 0x1C
+    __IO u32 DR5;                                                               ///< BKP data register 5,                           offset: 0x20
+    __IO u32 DR6;                                                               ///< BKP data register 6,                           offset: 0x24
+    __IO u32 DR7;                                                               ///< BKP data register 7,                           offset: 0x28
+    __IO u32 DR8;                                                               ///< BKP data register 8,                           offset: 0x2C
+    __IO u32 DR9;                                                               ///< BKP data register 9,                           offset: 0x30
+    __IO u32 DR10;                                                              ///< BKP data register 10                           offset: 0x34
+    __IO u32 DR11;                                                              ///< BKP data register 11,                          offset: 0x38
+    __IO u32 DR12;                                                              ///< BKP data register 12,                          offset: 0x3C
+    __IO u32 DR13;                                                              ///< BKP data register 13,                          offset: 0x40
+    __IO u32 DR14;                                                              ///< BKP data register 14,                          offset: 0x44
+    __IO u32 DR15;                                                              ///< BKP data register 15,                          offset: 0x48
+    __IO u32 DR16;                                                              ///< BKP data register 16,                          offset: 0x4C
+    __IO u32 DR17;                                                              ///< BKP data register 17,                          offset: 0x50
+    __IO u32 DR18;                                                              ///< BKP data register 18,                          offset: 0x54
+    __IO u32 DR19;                                                              ///< BKP data register 19,                          offset: 0x58
+    __IO u32 DR20;                                                              ///< BKP data register 20,                          offset: 0x5C
+} BKP_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define BKP                          ((BKP_TypeDef*) BKP_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP_DRn Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define BKP_DR_DATA_Pos              (0)
+#define BKP_DR_DATA                  (0xFFFFU << BKP_DR_DATA)                ///< Backup data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP_RTCCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define BKP_RTCCR_CAL_Pos           (0)
+#define BKP_RTCCR_CAL               (0x7FU << BKP_RTCCR_CAL_Pos)            ///< Calibration value
+#define BKP_RTCCR_CCO_Pos           (7)
+#define BKP_RTCCR_CCO               (0x01U << BKP_RTCCR_CCO_Pos)            ///< Calibration Clock Output
+#define BKP_RTCCR_ASOE_Pos          (8)
+#define BKP_RTCCR_ASOE              (0x01U << BKP_RTCCR_ASOE_Pos)           ///< Alarm or Second Output Enable
+#define BKP_RTCCR_ASOS_Pos          (9)
+#define BKP_RTCCR_ASOS              (0x01U << BKP_RTCCR_ASOS_Pos)           ///< Alarm or Second Output Selection
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define BKP_CR_TPE_Pos              (0)
+#define BKP_CR_TPE                  (0x01U << BKP_CR_TPE_Pos)               ///< TAMPER pin enable
+#define BKP_CR_TPAL_Pos             (1)
+#define BKP_CR_TPAL                 (0x01U << BKP_CR_TPAL_Pos)              ///< TAMPER pin active level
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief BKP_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define BKP_CSR_CTE_Pos             (0)
+#define BKP_CSR_CTE                 (0x01U << BKP_CSR_CTE_Pos)              ///< Clear Tamper event
+#define BKP_CSR_CTI_Pos             (1)
+#define BKP_CSR_CTI                 (0x01U << BKP_CSR_CTI_Pos)              ///< Clear Tamper Interrupt
+#define BKP_CSR_TPIE_Pos            (2)
+#define BKP_CSR_TPIE                (0x01U << BKP_CSR_TPIE_Pos)             ///< TAMPER Pin interrupt enable
+#define BKP_CSR_TEF_Pos             (8)
+#define BKP_CSR_TEF                 (0x01U << BKP_CSR_TEF_Pos)              ///< Tamper Event Flag
+#define BKP_CSR_TIF_Pos             (9)
+#define BKP_CSR_TIF                 (0x01U << BKP_CSR_TIF_Pos)              ///< Tamper Interrupt Flag
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h
new file mode 100644
index 000000000..5f66bb681
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h
@@ -0,0 +1,532 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_can.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_CAN_H
+#define __REG_CAN_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN1_BASE                       (APB1PERIPH_BASE + 0x6400)              ///< Base Address: 0x40006400
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN basic
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 CR;                                                                ///< Control register,                              offset: 0x00
+    __IO u32 CMR;                                                               ///< Command register,                              offset: 0x04
+    __IO u32 SR;                                                                ///< <Status register,                              offset: 0x08
+    __IO u32 IR;                                                                ///< Interrupt register,                            offset: 0x0c
+    __IO u32 ACR;                                                               ///< Acceptance Code register,                      offset: 0x10
+    __IO u32 AMR;                                                               ///< Acceptance Mask register,                      offset: 0x14
+    __IO u32 BTR0;                                                              ///< Bus Timing register 0,                         offset: 0x18
+    __IO u32 BTR1;                                                              ///< Bus Timing register 1,                         offset: 0x1C
+    __IO u32 RESERVED0;
+    __IO u32 RESERVED1;
+    __IO u32 TXID0;                                                             ///< Send ID register 0,                            offset: 0x28
+    __IO u32 TXID1;                                                             ///< Send ID register 1,                            offset: 0x2c
+    __IO u32 TXDR0;                                                             ///< Send Data register 0,                          offset: 0x30
+    __IO u32 TXDR1;                                                             ///< Send Data register 1,                          offset: 0x34
+    __IO u32 TXDR2;                                                             ///< Send Data register 2,                          offset: 0x38
+    __IO u32 TXDR3;                                                             ///< Send Data register 3,                          offset: 0x3c
+    __IO u32 TXDR4;                                                             ///< Send Data register 4,                          offset: 0x40
+    __IO u32 TXDR5;                                                             ///< Send Data register 5,                          offset: 0x44
+    __IO u32 TXDR6;                                                             ///< Send Data register 6,                          offset: 0x48
+    __IO u32 TXDR7;                                                             ///< Send Data register 7,                          offset: 0x4c
+    __IO u32 RXID0;                                                             ///< Mode register,                                 offset: 0x50
+    __IO u32 RXID1;                                                             ///< Mode register,                                 offset: 0x54
+    __IO u32 RXDR0;                                                             ///< Mode register,                                 offset: 0x58
+    __IO u32 RXDR1;                                                             ///< Mode register,                                 offset: 0x5C
+    __IO u32 RXDR2;                                                             ///< Mode register,                                 offset: 0x60
+    __IO u32 RXDR3;                                                             ///< Mode register,                                 offset: 0x64
+    __IO u32 RXDR4;                                                             ///< Mode register,                                 offset: 0x68
+    __IO u32 RXDR5;                                                             ///< Mode register,                                 offset: 0x6c
+    __IO u32 RXDR6;                                                             ///< Mode register,                                 offset: 0x70
+    __IO u32 RXDR7;                                                             ///< Mode register,                                 offset: 0x74
+    __IO u32 RESERVED2;
+    __IO u32 CDR;                                                               ///< Clock Divider register,                        offset: 0x7c
+} CAN_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN Peli
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 MOD;                                                               ///< Mode register,                                 offset: 0x00
+    __IO u32 CMR;                                                               ///< Command register,                              offset: 0x04
+    __IO u32 SR;                                                                ///< Status register,                               offset: 0x08
+    __IO u32 IR;                                                                ///< Interrupt Enable register,                     offset: 0x0c
+    __IO u32 IER;                                                               ///< Mode register,                                 offset: 0x10
+    __IO u32 RESERVED0;
+    __IO u32 BTR0;                                                              ///< Bus Timing register 0,                         offset: 0x18
+    __IO u32 BTR1;                                                              ///< Bus Timing register 1,                         offset: 0x1C
+    __IO u32 RESERVED1;
+    __IO u32 RESERVED2;
+    __IO u32 RESERVED3;
+    __IO u32 ALC;                                                               ///< Arbitration Lost Capture register,             offset: 0x2c
+    __IO u32 ECC;                                                               ///< Error Code Capture register,                   offset: 0x30
+    __IO u32 EWLR;                                                              ///< Error Warning Limit register,                  offset: 0x34
+    __IO u32 RXERR;                                                             ///< RX Error Counter register,                     offset: 0x38
+    __IO u32 TXERR;                                                             ///< TX Error Counter register,                     offset: 0x3c
+    __IO u32 FF;                                                                ///< Frame Format register,                         offset: 0x40
+    __IO u32 ID0;                                                               ///< ID register 0,                                 offset: 0x44
+    __IO u32 ID1;                                                               ///< ID register 1,                                 offset: 0x48
+    __IO u32 DATA0;                                                             ///< Data register 0,                               offset: 0x4c
+    __IO u32 DATA1;                                                             ///< Data register 1,                               offset: 0x50
+    __IO u32 DATA2;                                                             ///< Data register 2,                               offset: 0x54
+    __IO u32 DATA3;                                                             ///< Data register 3,                               offset: 0x58
+    __IO u32 DATA4;                                                             ///< Data register 4,                               offset: 0x5c
+    __IO u32 DATA5;                                                             ///< Data register 5,                               offset: 0x60
+    __IO u32 DATA6;                                                             ///< Data register 6,                               offset: 0x64
+    __IO u32 DATA7;                                                             ///< Data register 7,                               offset: 0x68
+    __IO u32 DATA8;                                                             ///< Data register 8,                               offset: 0x6c
+    __IO u32 DATA9;                                                             ///< Data register 9,                               offset: 0x70
+    __IO u32 RMC;                                                               ///< RMC register,                                  offset: 0x74
+    __IO u32 RBSA;                                                              ///< RBSA register,                                 offset: 0x78
+    __IO u32 CDR;                                                               ///< Clock Divider register                         offset: 0x7c
+} CAN_Peli_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 ACR0;
+    __IO u32 ACR1;
+    __IO u32 ACR2;
+    __IO u32 ACR3;
+    __IO u32 AMR0;
+    __IO u32 AMR1;
+    __IO u32 AMR2;
+    __IO u32 AMR3;
+} CAN_FLT_GROUP;
+
+typedef struct {
+    CAN_FLT_GROUP GROUP0;                                                        //Address offset: 0x40
+    u32      RESERVED[8];                                                        //Address offset: 0x60
+    __IO u32 AFM0;                                                               //Address offset: 0x80
+    __IO u32 AFM1;                                                               //Address offset: 0x84
+    __IO u32 AFM2;                                                               //Address offset: 0x88
+    __IO u32 FGA0;                                                               //Address offset: 0x8C
+    __IO u32 FGA1;                                                               //Address offset: 0x90
+    __IO u32 FGA2;                                                               //Address offset: 0x94
+    CAN_FLT_GROUP GROUP1;                                                        //Address offset: 0x98
+    CAN_FLT_GROUP GROUP2;                                                        //Address offset: 0xB8
+    CAN_FLT_GROUP GROUP3;                                                        //Address offset: 0xD8
+    CAN_FLT_GROUP GROUP4;                                                        //Address offset: 0xF8
+    CAN_FLT_GROUP GROUP5;                                                        //Address offset: 0x118
+    CAN_FLT_GROUP GROUP6;                                                        //Address offset: 0x138
+    CAN_FLT_GROUP GROUP7;                                                        //Address offset: 0x158
+    CAN_FLT_GROUP GROUP8;                                                        //Address offset: 0x178
+    CAN_FLT_GROUP GROUP9;                                                        //Address offset: 0x198
+    CAN_FLT_GROUP GROUP10;                                                       //Address offset: 0x1B8
+    CAN_FLT_GROUP GROUP11;                                                       //Address offset: 0x1D8
+    CAN_FLT_GROUP GROUP12;                                                       //Address offset: 0x1F8
+    CAN_FLT_GROUP GROUP13;                                                       //Address offset: 0x218
+    CAN_FLT_GROUP GROUP14;                                                       //Address offset: 0x238
+    CAN_FLT_GROUP GROUP15;                                                       //Address offset: 0x258
+    CAN_FLT_GROUP GROUP16;                                                       //Address offset: 0x278
+    CAN_FLT_GROUP GROUP17;                                                       //Address offset: 0x298
+    CAN_FLT_GROUP GROUP18;                                                       //Address offset: 0x2B8
+    CAN_FLT_GROUP GROUP19;                                                       //Address offset: 0x2D8
+} CAN_Peli_FLT_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN1                        ((CAN_TypeDef*) CAN1_BASE)
+#define CAN1_PELI                   ((CAN_Peli_TypeDef*) CAN1_BASE)
+#define CAN_Peli_FLT                ((CAN_Peli_FLT_TypeDef*)(CAN1_BASE + 0x40))
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN basic
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_CR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_CR_RR_Pos               (0)
+#define CAN_CR_RR                   (0x01U << CAN_CR_RR_Pos)                ///< CAN reset request
+#define CAN_CR_RIE_Pos              (1)
+#define CAN_CR_RIE                  (0x01U << CAN_CR_RIE_Pos)               ///< CAN receive interrupt enable
+#define CAN_CR_TIE_Pos              (2)
+#define CAN_CR_TIE                  (0x01U << CAN_CR_TIE_Pos)               ///< CAN transmit interrupt enable
+#define CAN_CR_EIE_Pos              (3)
+#define CAN_CR_EIE                  (0x01U << CAN_CR_EIE_Pos)               ///< CAN error interrupt enable
+#define CAN_CR_OIE_Pos              (4)
+#define CAN_CR_OIE                  (0x01U << CAN_CR_OIE_Pos)               ///< CAN overflow interrupt enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_CMR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_CMR_TR_Pos              (0)
+#define CAN_CMR_TR                  (0x01U << CAN_CMR_TR_Pos )              ///< CAN transmission request
+#define CAN_CMR_AT_Pos              (1)
+#define CAN_CMR_AT                  (0x01U << CAN_CMR_AT_Pos )              ///< CAN abort transmission
+#define CAN_CMR_RRB_Pos             (2)
+#define CAN_CMR_RRB                 (0x01U << CAN_CMR_RRB_Pos)              ///< CAN release receive buffer
+#define CAN_CMR_CDO_Pos             (3)
+#define CAN_CMR_CDO                 (0x01U << CAN_CMR_CDO_Pos)              ///< CAN clear data overrun
+#define CAN_CMR_GTS_Pos             (4)
+#define CAN_CMR_GTS                 (0x01U << CAN_CMR_GTS_Pos)              ///< CAN go to sleep
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_SR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_SR_RBS_Pos              (0)
+#define CAN_SR_RBS                  (0x01U << CAN_SR_RBS_Pos)               ///< CAN receive buffer status
+#define CAN_SR_DOS_Pos              (1)
+#define CAN_SR_DOS                  (0x01U << CAN_SR_DOS_Pos)               ///< CAN data overrun status
+#define CAN_SR_TBS_Pos              (2)
+#define CAN_SR_TBS                  (0x01U << CAN_SR_TBS_Pos)               ///< CAN transmit buffer status
+#define CAN_SR_TCS_Pos              (3)
+#define CAN_SR_TCS                  (0x01U << CAN_SR_TCS_Pos)               ///< CAN transmission complete status
+#define CAN_SR_RS_Pos               (4)
+#define CAN_SR_RS                   (0x01U << CAN_SR_RS_Pos)                ///< CAN receive status
+#define CAN_SR_TS_Pos               (5)
+#define CAN_SR_TS                   (0x01U << CAN_SR_TS_Pos)                ///< CAN transmit status
+#define CAN_SR_ES_Pos               (6)
+#define CAN_SR_ES                   (0x01U << CAN_SR_ES_Pos)                ///< CAN error status
+#define CAN_SR_BS_Pos               (7)
+#define CAN_SR_BS                   (0x01U << CAN_SR_BS_Pos)                ///< CAN bus status
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_ACR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_ACR_AC                  (0xFFU << 0)                            ///< CAN acceptance code
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_AMR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_AMR_AM_Pos              (0)
+#define CAN_AMR_AM                  (0xFFU << CAN_AMR_AM_Pos)               ///< CAN acceptance mask
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_BTR0 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_BTR0_BRP_Pos            (0)
+#define CAN_BTR0_BRP                (0x003FU << CAN_BTR0_BRP_Pos)           ///< CAN baud rate prescaler
+#define CAN_BTR0_SJW_Pos            (6)
+#define CAN_BTR0_SJW                (0x03U << CAN_BTR0_SJW_Pos)             ///< CAN synchronization jump width
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_BTR1 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_BTR1_TESG1_Pos          (0)
+#define CAN_BTR1_TESG1              (0x000FU << CAN_BTR1_TESG1_Pos)         ///< CAN Time segment 1
+#define CAN_BTR1_TESG2_Pos          (4)
+#define CAN_BTR1_TESG2              (0x07U << CAN_BTR1_TESG2_Pos)           ///< CAN Time segment 2
+#define CAN_BTR1_SAM_Pos            (7)
+#define CAN_BTR1_SAM                (0x01U << CAN_BTR1_SAM_Pos)             ///< CAN sampling
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_TXID0 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_TXID0_ID_3_Pos          (0)
+#define CAN_TXID0_ID_3              (0x01U << CAN_TXID0_ID_3_Pos)           ///< CAN identifier byte 3
+#define CAN_TXID0_ID_4_Pos          (1)
+#define CAN_TXID0_ID_4              (0x01U << CAN_TXID0_ID_4_Pos)           ///< CAN identifier byte 4
+#define CAN_TXID0_ID_5_Pos          (2)
+#define CAN_TXID0_ID_5              (0x01U << CAN_TXID0_ID_5_Pos)           ///< CAN identifier byte 5
+#define CAN_TXID0_ID_6_Pos          (3)
+#define CAN_TXID0_ID_6              (0x01U << CAN_TXID0_ID_6_Pos)           ///< CAN identifier byte 6
+#define CAN_TXID0_ID_7_Pos          (4)
+#define CAN_TXID0_ID_7              (0x01U << CAN_TXID0_ID_7_Pos)           ///< CAN identifier byte 7
+#define CAN_TXID0_ID_8_Pos          (5)
+#define CAN_TXID0_ID_8              (0x01U << CAN_TXID0_ID_8_Pos)           ///< CAN identifier byte 8
+#define CAN_TXID0_ID_9_Pos          (6)
+#define CAN_TXID0_ID_9              (0x01U << CAN_TXID0_ID_9_Pos)           ///< CAN identifier byte 9
+#define CAN_TXID0_ID_10_Pos         (7)
+#define CAN_TXID0_ID_10             (0x01U << CAN_TXID0_ID_10_Pos)          ///< CAN identifier byte 10
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_TXID1 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_TXID1_DLC0_Pos          (0)
+#define CAN_TXID1_DLC0              (0x01U << CAN_TXID1_DLC0_Pos)           ///< CAN data length code 0 ~ 8
+#define CAN_TXID1_DLC1_Pos          (1)
+#define CAN_TXID1_DLC1              (0x01U << CAN_TXID1_DLC1_Pos)           ///< CAN data length code 0 ~ 8
+#define CAN_TXID1_DLC2_Pos          (2)
+#define CAN_TXID1_DLC2              (0x01U << CAN_TXID1_DLC2_Pos)           ///< CAN data length code 0 ~ 8
+#define CAN_TXID1_DLC3_Pos          (3)
+#define CAN_TXID1_DLC3              (0x01U << CAN_TXID1_DLC3_Pos)           ///< CAN data length code 0 ~ 8
+#define CAN_TXID1_RTR_Pos           (4)
+#define CAN_TXID1_RTR               (0x01U << CAN_TXID1_RTR_Pos )           ///< CAN remote transmission request
+#define CAN_TXID1_ID_0_Pos          (5)
+#define CAN_TXID1_ID_0              (0x01U << CAN_TXID1_ID_0_Pos)           ///< CAN identifier byte 0
+#define CAN_TXID1_ID_1_Pos          (6)
+#define CAN_TXID1_ID_1              (0x01U << CAN_TXID1_ID_1_Pos)           ///< CAN identifier byte 1
+#define CAN_TXID1_ID_2_Pos          (7)
+#define CAN_TXID1_ID_2              (0x01U << CAN_TXID1_ID_2_Pos)           ///< CAN identifier byte 2
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_TXDRn register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_TXDRn                   (0x00FFU)                               // (n = 0..7)        ///< CAN send data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_CDR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_CDR_MODE_Pos            (7)
+#define CAN_CDR_MODE                (0x01U << CAN_CDR_MODE_Pos)             ///< CAN mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN Peli
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_MOD register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_MOD_RM_Pos              (0)
+#define CAN_MOD_RM                  (0x01U << CAN_MOD_RM_Pos)               ///< CAN reset mode
+#define CAN_MOD_LOM_Pos             (1)
+#define CAN_MOD_LOM                 (0x01U << CAN_MOD_LOM_Pos)              ///< CAN listen only mode
+#define CAN_MOD_STM_Pos             (2)
+#define CAN_MOD_STM                 (0x01U << CAN_MOD_STM_Pos)              ///< CAN self test mode
+#define CAN_MOD_AFM_Pos             (3)
+#define CAN_MOD_AFM                 (0x01U << CAN_MOD_AFM_Pos)              ///< CAN acceptance filter mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_CMR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_CMR_TR_Pos              (0)
+#define CAN_CMR_TR                  (0x01U << CAN_CMR_TR_Pos )              ///< CAN transmission request
+#define CAN_CMR_AT_Pos              (1)
+#define CAN_CMR_AT                  (0x01U << CAN_CMR_AT_Pos )              ///< CAN abort transmission
+#define CAN_CMR_RRB_Pos             (2)
+#define CAN_CMR_RRB                 (0x01U << CAN_CMR_RRB_Pos)              ///< CAN release receive buffer
+#define CAN_CMR_CDO_Pos             (3)
+#define CAN_CMR_CDO                 (0x01U << CAN_CMR_CDO_Pos)              ///< CAN clear data overrun
+#define CAN_CMR_SRR_Pos             (4)
+#define CAN_CMR_SRR                 (0x01U << CAN_CMR_SRR_Pos)              ///< CAN self reset request
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_SR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_SR_RBS_Pos              (0)
+#define CAN_SR_RBS                  (0x01U << CAN_SR_RBS_Pos)               ///< CAN receive buffer status
+#define CAN_SR_DOS_Pos              (1)
+#define CAN_SR_DOS                  (0x01U << CAN_SR_DOS_Pos)               ///< CAN data overrun status
+#define CAN_SR_TBS_Pos              (2)
+#define CAN_SR_TBS                  (0x01U << CAN_SR_TBS_Pos)               ///< CAN transmit buffer status
+#define CAN_SR_TCS_Pos              (3)
+#define CAN_SR_TCS                  (0x01U << CAN_SR_TCS_Pos)               ///< CAN transmission complete status
+#define CAN_SR_RS_Pos               (4)
+#define CAN_SR_RS                   (0x01U << CAN_SR_RS_Pos)                ///< CAN receive status
+#define CAN_SR_TS_Pos               (5)
+#define CAN_SR_TS                   (0x01U << CAN_SR_TS_Pos)                ///< CAN transmit status
+#define CAN_SR_ES_Pos               (6)
+#define CAN_SR_ES                   (0x01U << CAN_SR_ES_Pos)                ///< CAN error status
+#define CAN_SR_BS_Pos               (7)
+#define CAN_SR_BS                   (0x01U << CAN_SR_BS_Pos)                ///< CAN bus status
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_IR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_IR_RI_Pos               (0)
+#define CAN_IR_RI                   (0x01U << CAN_IR_RI_Pos)                ///< CAN receive interrupt
+#define CAN_IR_TI_Pos               (1)
+#define CAN_IR_TI                   (0x01U << CAN_IR_TI_Pos)                ///< CAN transmit interrupt
+#define CAN_IR_EI_Pos               (2)
+#define CAN_IR_EI                   (0x01U << CAN_IR_EI_Pos)                ///< CAN error interrupt
+#define CAN_IR_DOI_Pos              (3)
+#define CAN_IR_DOI                  (0x01U << CAN_IR_DOI_Pos)               ///< CAN data overrun interrupt
+#define CAN_IR_EPI_Pos              (5)
+#define CAN_IR_EPI                  (0x01U << CAN_IR_EPI_Pos)               ///< CAN error passive interrupt
+#define CAN_IR_ALI_Pos              (6)
+#define CAN_IR_ALI                  (0x01U << CAN_IR_ALI_Pos)               ///< CAN arbitration lost interrupt
+#define CAN_IR_BEI_Pos              (7)
+#define CAN_IR_BEI                  (0x01U << CAN_IR_BEI_Pos)               ///< CAN bus error interrupt
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_IR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_IER_RIE_Pos             (0)
+#define CAN_IER_RIE                 (0x01U << CAN_IER_RIE_Pos)              ///< CAN receive interrupt enable
+#define CAN_IER_TIE_Pos             (1)
+#define CAN_IER_TIE                 (0x01U << CAN_IER_TIE_Pos)              ///< CAN transmit interrupt enable
+#define CAN_IER_EIE_Pos             (2)
+#define CAN_IER_EIE                 (0x01U << CAN_IER_EIE_Pos)              ///< CAN error interrupt enable
+#define CAN_IER_DOIE_Pos            (3)
+#define CAN_IER_DOIE                (0x01U << CAN_IER_DOIE_Pos)             ///< CAN data overrun interrupt enable
+#define CAN_IER_EPIE_Pos            (5)
+#define CAN_IER_EPIE                (0x01U << CAN_IER_EPI_Pos)              ///< CAN error passive interrupt enable
+#define CAN_IER_ALIE_Pos            (6)
+#define CAN_IER_ALIE                (0x01U << CAN_IER_ALIE_Pos)             ///< CAN arbitration lost interrupt enable
+#define CAN_IER_BEIE_Pos            (7)
+#define CAN_IER_BEIE                (0x01U << CAN_IER_BEIE_Pos)             ///< CAN bus error interrupt enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_ACRn register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_ACRn_AC_Pos             (0)
+#define CAN_ACRn_AC                 (0xFFU << CAN_ACRn_AC_Pos)              ///< CAN acceptance code
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_AMRn register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_AMRn_AM_Pos             (0)
+#define CAN_AMRn_AM                 (0xFFU << CAN_AMRn_AM_Pos)              ///< CAN acceptance mask
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_BTR0 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_BTR0_BRP_Pos            (0)
+#define CAN_BTR0_BRP                (0x003FU << CAN_BTR0_BRP_Pos)           ///< CAN baud rate prescaler
+#define CAN_BTR0_SJW_Pos            (6)
+#define CAN_BTR0_SJW                (0x03U << CAN_BTR0_SJW_Pos)             ///< CAN synchronization jump width
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_ALC register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_ALC_BITNO_Pos           (0)
+#define CAN_ALC_BITNO               (0x001FU << CAN_ALC_BITNO_Pos)          ///< CAN bit number
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_ECC register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_ECC_SEG_Pos             (0)
+#define CAN_ECC_SEG                 (0x001FU <<CAN_ECC_SEG_Pos)             ///< CAN error code capture
+#define CAN_ECC_DIR_Pos             (5)
+#define CAN_ECC_DIR                 (0x01U << CAN_ECC_DIR_Pos)              ///< CAN direction
+#define CAN_ECC_ERRC_Pos            (6)
+#define CAN_ECC_ERRC                (0x03U << CAN_ECC_ERRC_Pos)             ///< CAN error code
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_EWLR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_EWLR_EWL_Pos            (0)
+#define CAN_EWLR_EWL                (0x00FFU << CAN_EWLR_EWL_Pos)           ///< CAN programmable error warning limit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_RXERR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_RXERR_RXERR_Pos         (0)
+#define CAN_RXERR_RXERR             (0x00FFU << CAN_RXERR_RXERR_Pos)        ///< CAN RX error counter register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_TXERR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_TXERR_TXERR_Pos         (0)
+#define CAN_TXERR_TXERR             (0x00FFU << CAN_TXERR_TXERR_Pos)        ///< CAN TX error counter register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_FF register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_FF_DLC_0_Pos            (0)
+#define CAN_FF_DLC_0                (0x01U << CAN_FF_DLC_0_Pos)             ///< CAN data length code bit
+#define CAN_FF_DLC_1_Pos            (1)
+#define CAN_FF_DLC_1                (0x01U << CAN_FF_DLC_1_Pos)             ///< CAN data length code bit
+#define CAN_FF_DLC_2_Pos            (2)
+#define CAN_FF_DLC_2                (0x01U << CAN_FF_DLC_2_Pos)             ///< CAN data length code bit
+#define CAN_FF_DLC_3_Pos            (3)
+#define CAN_FF_DLC_3                (0x01U << CAN_FF_DLC_3_Pos)             ///< CAN data length code bit
+#define CAN_FF_RTR_Pos              (6)
+#define CAN_FF_RTR                  (0x01U << CAN_FF_RTR_Pos)               ///< CAN remote transmission request
+#define CAN_FF_FF_Pos               (7)
+#define CAN_FF_FF                   (0x01U << CAN_FF_FF_Pos)                ///< CAN frame format
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_TXID0 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_TXID0_ID_21_Pos         (0)
+#define CAN_TXID0_ID_21             (0x01U << CAN_TXID0_ID_21_Pos)          ///< CAN identifier bit 21
+#define CAN_TXID0_ID_22_Pos         (1)
+#define CAN_TXID0_ID_22             (0x01U << CAN_TXID0_ID_22_Pos)          ///< CAN identifier bit 22
+#define CAN_TXID0_ID_23_Pos         (2)
+#define CAN_TXID0_ID_23             (0x01U << CAN_TXID0_ID_23_Pos)          ///< CAN identifier bit 23
+#define CAN_TXID0_ID_24_Pos         (3)
+#define CAN_TXID0_ID_24             (0x01U << CAN_TXID0_ID_24_Pos)          ///< CAN identifier bit 24
+#define CAN_TXID0_ID_25_Pos         (4)
+#define CAN_TXID0_ID_25             (0x01U << CAN_TXID0_ID_25_Pos)          ///< CAN identifier bit 25
+#define CAN_TXID0_ID_26_Pos         (5)
+#define CAN_TXID0_ID_26             (0x01U << CAN_TXID0_ID_26_Pos)          ///< CAN identifier bit 26
+#define CAN_TXID0_ID_27_Pos         (6)
+#define CAN_TXID0_ID_27             (0x01U << CAN_TXID0_ID_27_Pos)          ///< CAN identifier bit 27
+#define CAN_TXID0_ID_28_Pos         (7)
+#define CAN_TXID0_ID_28             (0x01U << CAN_TXID0_ID_28_Pos)          ///< CAN identifier bit 28
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_TXID1 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_TXID1_ID_13_Pos         (0)
+#define CAN_TXID1_ID_13             (0x01U << CAN_TXID1_ID_13_Pos)          ///< CAN identifier bit 13
+#define CAN_TXID1_ID_14_Pos         (1)
+#define CAN_TXID1_ID_14             (0x01U << CAN_TXID1_ID_14_Pos)          ///< CAN identifier bit 14
+#define CAN_TXID1_ID_15_Pos         (2)
+#define CAN_TXID1_ID_15             (0x01U << CAN_TXID1_ID_15_Pos)          ///< CAN identifier bit 15
+#define CAN_TXID1_ID_16_Pos         (3)
+#define CAN_TXID1_ID_16             (0x01U << CAN_TXID1_ID_16_Pos)          ///< CAN identifier bit 16
+#define CAN_TXID1_ID_17_Pos         (4)
+#define CAN_TXID1_ID_17             (0x01U << CAN_TXID1_ID_17_Pos)          ///< CAN identifier bit 17
+#define CAN_TXID1_ID_18_Pos         (5)
+#define CAN_TXID1_ID_18             (0x01U << CAN_TXID1_ID_18_Pos)          ///< CAN identifier bit 18
+#define CAN_TXID1_ID_19_Pos         (6)
+#define CAN_TXID1_ID_19             (0x01U << CAN_TXID1_ID_19_Pos)          ///< CAN identifier bit 19
+#define CAN_TXID1_ID_20_Pos         (7)
+#define CAN_TXID1_ID_20             (0x01U << CAN_TXID1_ID_20_Pos)          ///< CAN identifier bit 20
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_TXDATAn register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_TXDATAn_Pos             (0)
+#define CAN_TXDATAn                 (0x00FFU << CAN_TXDATAn_Pos)            ///< CAN transmit data n
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CAN_CDR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define CAN_CDR_MODE_Pos            (7)
+#define CAN_CDR_MODE                (0x01U << CAN_CDR_MODE_Pos)             ///< CAN mode
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h
new file mode 100644
index 000000000..6a955cc61
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h
@@ -0,0 +1,643 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_common.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_COMMON_H
+#define __REG_COMMON_H
+
+// Files includes
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+#ifndef HSE_STARTUP_TIMEOUT
+#define HSE_STARTUP_TIMEOUT     (0x0500U)                                       ///< Time out for HSE start up.
+#endif
+#ifdef  CUSTOM_HSE_VAL
+#ifndef HSE_VALUE
+#define HSE_VALUE               (12000000U)                                     ///< Value of the External oscillator in Hz.
+#endif
+#else
+#ifndef HSE_VALUE
+#define HSE_VALUE               (8000000U)                                      ///< Value of the External oscillator in Hz.
+#endif
+#endif
+
+
+
+#define HSI_VALUE_PLL_ON        (8000000U)                                      ///< Value of the Internal oscillator in Hz.
+#define HSI_DIV6                (8000000U)                                      ///< Value of the Internal oscillator in Hz.
+// Value of the Internal oscillator in Hz.
+
+
+#define LSI_VALUE               (40000U)                                        ///< Value of the Internal oscillator in Hz.
+
+
+
+
+
+#ifndef HSI_VALUE
+
+#define HSI_VALUE               (8000000U)                                      ///< Value of the Internal oscillator in Hz.
+
+#endif
+
+
+
+
+
+
+
+
+#define __MPU_PRESENT               (0)                                     ///< Cortex-M3 does not provide a MPU present or not
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS            (4)                                     ///< Cortex-M3 uses 4 Bits for the Priority Levels
+//#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#define __Vendor_SysTickConfig      (0)                                     ///< Set to 1 if different SysTick Config is used
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  MM32 MCU Interrupt Handle
+////////////////////////////////////////////////////////////////////////////////
+typedef enum IRQn {
+    NonMaskableInt_IRQn             = -14,                                  ///< 2 Non Maskable Interrupt
+    MemoryManagement_IRQn           = -12,                                  ///< 4 Cortex-M3 Memory Management Interrupt
+    BusFault_IRQn                   = -11,                                  ///< 5 Cortex-M3 Bus Fault Interrupt
+    UsageFault_IRQn                 = -10,                                  ///< 6 Cortex-M3 Usage Fault Interrupt
+    SVCall_IRQn                     = -5,                                   ///< 11 Cortex-M3 SV Call Interrupt
+    DebugMonitor_IRQn               = -4,                                   ///< 12 Cortex-M3 Debug Monitor Interrupt
+    PendSV_IRQn                     = -2,                                   ///< 14 Cortex-M3 Pend SV Interrupt
+    SysTick_IRQn                    = -1,                                   ///< 15 Cortex-M3 System Tick Interrupt
+
+    WWDG_IWDG_IRQn                      = 0,                                     ///< Watchdog interrupt
+    WWDG_IRQn                           = 0,                                     ///< Watchdog interrupt
+    PVD_IRQn                            = 1,                                     ///< (PVD) Interrupt
+    TAMPER_IRQn                         = 2,                                     ///< Intrusion detection interrupted
+    RTC_IRQn                            = 3,                                     ///< Real-time clock (RTC) global interrupt
+    FLASH_IRQn                          = 4,                                     ///< Flash global interrupt
+    RCC_CRS_IRQn                        = 5,                                     ///< RCC and CRS global interrupt
+    EXTI0_IRQn                          = 6,                                     ///< EXTI line 0 interrupt
+    EXTI1_IRQn                          = 7,                                     ///< EXTI line 1 interrupt
+    EXTI2_IRQn                          = 8,                                     ///< EXTI line 2 interrupt
+    EXTI3_IRQn                          = 9,                                     ///< EXTI line 3 interrupted
+    EXTI4_IRQn                          = 10,                                    ///< EXTI line 4 interrupt
+    DMA1_Channel1_IRQn                  = 11,                                    ///< DMA1 channel 1 global interrupt
+    DMA1_Channel2_IRQn                  = 12,                                    ///< DMA1 channel 2 global interrupt
+    DMA1_Channel3_IRQn                  = 13,                                    ///< DMA1 channel 3 global interrupt
+    DMA1_Channel4_IRQn                  = 14,                                    ///< DMA1 channel 4 global interrupt
+    DMA1_Channel5_IRQn                  = 15,                                    ///< DMA1 channel 5 global interrupt
+    DMA1_Channel6_IRQn                  = 16,                                    ///< DMA1 channel 6 global interrupt
+    DMA1_Channel7_IRQn                  = 17,                                    ///< DMA1 channel 7 global interrupt
+    ADC1_IRQn                           = 18,                                    ///< ADC1 global interrupt
+    ADC1_2_IRQn                         = 18,                                    ///< ADC1&ADC2 global interrupt
+    ADC2_IRQn                           = 18,                                    ///< ADC2 global interrupt
+    FlashCache_IRQn                     = 19,                                    ///< FlashCache outage
+    CAN1_RX_IRQn                        = 21,                                    ///< CAN1 receive interrupt
+    CAN_IRQn                            = 21,                                    ///< CAN interrupt
+    EXTI9_5_IRQn                        = 23,                                    ///< EXTI line [9: 5] interrupted
+    TIM1_BRK_IRQn                       = 24,                                    ///< TIM1 disconnect interrupt
+    TIM1_UP_IRQn                        = 25,                                    ///< TIM1 update interrupt
+    IM1_TRG_COM_IRQn                    = 26,                                    ///< TIM1 trigger and communication interrupt
+    TIM1_CC_IRQn                        = 27,                                    ///< TIM1 capture compare interrupt
+    TIM2_IRQn                           = 28,                                    ///< TIM2 global interrupt
+    TIM3_IRQn                           = 29,                                    ///< TIM3 global interrupt
+    TIM4_IRQn                           = 30,                                    ///< TIM4 global interrupt
+    I2C1_IRQn                           = 31,                                    ///< I2C1 global interrupt
+    I2C2_IRQn                           = 33,                                    ///< I2C2 global interrupt
+    SPI1_IRQn                           = 35,                                    ///< SPI1 global interrupt
+    SPI2_IRQn                           = 36,                                    ///< SPI2 global interrupt
+    UART1_IRQn                          = 37,                                    ///< UART1 global interrupt
+    UART2_IRQn                          = 38,                                    ///< UART2 global interrupt
+    UART3_IRQn                          = 39,                                    ///< UART3 global interrupt
+    EXTI15_10_IRQn                      = 40,                                    ///< EXTI line [15: 10] interrupted
+    RTCAlarm_IRQn                       = 41,                                    ///< RTC alarm connected to EXTI interrupted
+    USB_WKUP_IRQn                       = 42,                                    ///< Wake-up interrupt from USB connected to EXTI
+    TIM8_BRK_IRQn                       = 43,                                    ///< TIM8 brake interruption
+    TIM8_UP_IRQn                        = 44,                                    ///< TIM8 update interrupt
+    TIM8_TRG_COM_IRQn                   = 45,                                    ///< TIM8 trigger, communication interrupt
+    TIM8_CC_IRQn                        = 46,                                    ///< TIM8 capture compare interrupt
+    ADC3_IRQn                           = 47,                                    ///< ADC3 global interrupt
+    SDIO_IRQn                           = 49,                                    ///< SDIO global interrupt
+    TIM5_IRQn                           = 50,                                    ///< TIM5 global interrupt
+    SPI3_IRQn                           = 51,                                    ///< SPI3 global interrupt
+    UART4_IRQn                          = 52,                                    ///< UART4 global interrupt
+    UART5_IRQn                          = 53,                                    ///< UART5 global interrupt
+    TIM6_IRQn                           = 54,                                    ///< TIM6 global interrupt
+    TIM7_IRQn                           = 55,                                    ///< TIM7 global interrupt
+    DMA2_Channel1_IRQn                  = 56,                                    ///< DMA2 channel 1 global interrupt
+    DMA2_Channel2_IRQn                  = 57,                                    ///< DMA2 channel 2 global interrupt
+    DMA2_Channel3_IRQn                  = 58,                                    ///< DMA2 channel 3 global interrupt
+    DMA2_Channel4_IRQn                  = 59,                                    ///< DMA2 channel 4 global interrupt
+    DMA2_Channel5_IRQn                  = 60,                                    ///< DMA2 channel 5 global interrupt
+    ETHERNET_MAC_IRQn                   = 61,                                    ///< ETHERNET global interrupt
+    COMP1_2_IRQn                        = 64,                                  ///< Comparator 1/2 interrupt connected to EXTI
+    USB_FS_IRQn                         = 67,                                  ///< USB FS global interrupt
+    UART6_IRQn                          = 71,                                  ///< UART6 global interrupt
+    UART7_IRQn                          = 82,                                  ///< UART7 global interrupt
+    UART8_IRQn                          = 83,                                  ///< UART8 global interrupt
+} IRQn_Type;
+
+
+
+
+#include <core_cm3.h>
+
+
+
+#define PERIPH_BASE                     (0x40000000U)                           ///< Peripheral base address in the alias region
+
+#define EEPROM_BASE                     (0x08100000U)                           ///< EEPROM base address in the alias region
+
+
+#define SRAM_BITBAND_BASE               (0x22000000U)                           ///< Peripheral base address in the bit-band region
+#define PERIPH_BITBAND_BASE             (0x42000000U)                           ///< SRAM base address in the bit-band region
+
+#define APB1PERIPH_BASE                 (PERIPH_BASE + 0x00000000)
+#define APB2PERIPH_BASE                 (PERIPH_BASE + 0x00010000)
+#define AHBPERIPH_BASE                  (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE                 (PERIPH_BASE + 0x10000000)
+#define AHB3PERIPH_BASE                 (PERIPH_BASE + 0x20000000)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UID type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UID_BASE                        (0x1FFFF7E0U)                           ///< Unique device ID register base address
+
+
+
+
+
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// @brief Nested Vectored Interrupt Controller
+///////////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_ISER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_ISER_SETENA                (0xFFFFFFFFU)                           ///< Interrupt set enable bits
+#define NVIC_ISER_SETENA_0              (0x00000001U)                           ///< bit 0
+#define NVIC_ISER_SETENA_1              (0x00000002U)                           ///< bit 1
+#define NVIC_ISER_SETENA_2              (0x00000004U)                           ///< bit 2
+#define NVIC_ISER_SETENA_3              (0x00000008U)                           ///< bit 3
+#define NVIC_ISER_SETENA_4              (0x00000010U)                           ///< bit 4
+#define NVIC_ISER_SETENA_5              (0x00000020U)                           ///< bit 5
+#define NVIC_ISER_SETENA_6              (0x00000040U)                           ///< bit 6
+#define NVIC_ISER_SETENA_7              (0x00000080U)                           ///< bit 7
+#define NVIC_ISER_SETENA_8              (0x00000100U)                           ///< bit 8
+#define NVIC_ISER_SETENA_9              (0x00000200U)                           ///< bit 9
+#define NVIC_ISER_SETENA_10             (0x00000400U)                           ///< bit 10
+#define NVIC_ISER_SETENA_11             (0x00000800U)                           ///< bit 11
+#define NVIC_ISER_SETENA_12             (0x00001000U)                           ///< bit 12
+#define NVIC_ISER_SETENA_13             (0x00002000U)                           ///< bit 13
+#define NVIC_ISER_SETENA_14             (0x00004000U)                           ///< bit 14
+#define NVIC_ISER_SETENA_15             (0x00008000U)                           ///< bit 15
+#define NVIC_ISER_SETENA_16             (0x00010000U)                           ///< bit 16
+#define NVIC_ISER_SETENA_17             (0x00020000U)                           ///< bit 17
+#define NVIC_ISER_SETENA_18             (0x00040000U)                           ///< bit 18
+#define NVIC_ISER_SETENA_19             (0x00080000U)                           ///< bit 19
+#define NVIC_ISER_SETENA_20             (0x00100000U)                           ///< bit 20
+#define NVIC_ISER_SETENA_21             (0x00200000U)                           ///< bit 21
+#define NVIC_ISER_SETENA_22             (0x00400000U)                           ///< bit 22
+#define NVIC_ISER_SETENA_23             (0x00800000U)                           ///< bit 23
+#define NVIC_ISER_SETENA_24             (0x01000000U)                           ///< bit 24
+#define NVIC_ISER_SETENA_25             (0x02000000U)                           ///< bit 25
+#define NVIC_ISER_SETENA_26             (0x04000000U)                           ///< bit 26
+#define NVIC_ISER_SETENA_27             (0x08000000U)                           ///< bit 27
+#define NVIC_ISER_SETENA_28             (0x10000000U)                           ///< bit 28
+#define NVIC_ISER_SETENA_29             (0x20000000U)                           ///< bit 29
+#define NVIC_ISER_SETENA_30             (0x40000000U)                           ///< bit 30
+#define NVIC_ISER_SETENA_31             (0x80000000U)                           ///< bit 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_ICER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_ICER_CLRENA                (0xFFFFFFFFU)                           ///< Interrupt clear-enable bits
+#define NVIC_ICER_CLRENA_0              (0x00000001U)                           ///< bit 0
+#define NVIC_ICER_CLRENA_1              (0x00000002U)                           ///< bit 1
+#define NVIC_ICER_CLRENA_2              (0x00000004U)                           ///< bit 2
+#define NVIC_ICER_CLRENA_3              (0x00000008U)                           ///< bit 3
+#define NVIC_ICER_CLRENA_4              (0x00000010U)                           ///< bit 4
+#define NVIC_ICER_CLRENA_5              (0x00000020U)                           ///< bit 5
+#define NVIC_ICER_CLRENA_6              (0x00000040U)                           ///< bit 6
+#define NVIC_ICER_CLRENA_7              (0x00000080U)                           ///< bit 7
+#define NVIC_ICER_CLRENA_8              (0x00000100U)                           ///< bit 8
+#define NVIC_ICER_CLRENA_9              (0x00000200U)                           ///< bit 9
+#define NVIC_ICER_CLRENA_10             (0x00000400U)                           ///< bit 10
+#define NVIC_ICER_CLRENA_11             (0x00000800U)                           ///< bit 11
+#define NVIC_ICER_CLRENA_12             (0x00001000U)                           ///< bit 12
+#define NVIC_ICER_CLRENA_13             (0x00002000U)                           ///< bit 13
+#define NVIC_ICER_CLRENA_14             (0x00004000U)                           ///< bit 14
+#define NVIC_ICER_CLRENA_15             (0x00008000U)                           ///< bit 15
+#define NVIC_ICER_CLRENA_16             (0x00010000U)                           ///< bit 16
+#define NVIC_ICER_CLRENA_17             (0x00020000U)                           ///< bit 17
+#define NVIC_ICER_CLRENA_18             (0x00040000U)                           ///< bit 18
+#define NVIC_ICER_CLRENA_19             (0x00080000U)                           ///< bit 19
+#define NVIC_ICER_CLRENA_20             (0x00100000U)                           ///< bit 20
+#define NVIC_ICER_CLRENA_21             (0x00200000U)                           ///< bit 21
+#define NVIC_ICER_CLRENA_22             (0x00400000U)                           ///< bit 22
+#define NVIC_ICER_CLRENA_23             (0x00800000U)                           ///< bit 23
+#define NVIC_ICER_CLRENA_24             (0x01000000U)                           ///< bit 24
+#define NVIC_ICER_CLRENA_25             (0x02000000U)                           ///< bit 25
+#define NVIC_ICER_CLRENA_26             (0x04000000U)                           ///< bit 26
+#define NVIC_ICER_CLRENA_27             (0x08000000U)                           ///< bit 27
+#define NVIC_ICER_CLRENA_28             (0x10000000U)                           ///< bit 28
+#define NVIC_ICER_CLRENA_29             (0x20000000U)                           ///< bit 29
+#define NVIC_ICER_CLRENA_30             (0x40000000U)                           ///< bit 30
+#define NVIC_ICER_CLRENA_31             (0x80000000U)                           ///< bit 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_ISPR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_ISPR_SETPEND               (0xFFFFFFFFU)                           ///< Interrupt set-pending bits
+#define NVIC_ISPR_SETPEND_0             (0x00000001U)                           ///< bit 0
+#define NVIC_ISPR_SETPEND_1             (0x00000002U)                           ///< bit 1
+#define NVIC_ISPR_SETPEND_2             (0x00000004U)                           ///< bit 2
+#define NVIC_ISPR_SETPEND_3             (0x00000008U)                           ///< bit 3
+#define NVIC_ISPR_SETPEND_4             (0x00000010U)                           ///< bit 4
+#define NVIC_ISPR_SETPEND_5             (0x00000020U)                           ///< bit 5
+#define NVIC_ISPR_SETPEND_6             (0x00000040U)                           ///< bit 6
+#define NVIC_ISPR_SETPEND_7             (0x00000080U)                           ///< bit 7
+#define NVIC_ISPR_SETPEND_8             (0x00000100U)                           ///< bit 8
+#define NVIC_ISPR_SETPEND_9             (0x00000200U)                           ///< bit 9
+#define NVIC_ISPR_SETPEND_10            (0x00000400U)                           ///< bit 10
+#define NVIC_ISPR_SETPEND_11            (0x00000800U)                           ///< bit 11
+#define NVIC_ISPR_SETPEND_12            (0x00001000U)                           ///< bit 12
+#define NVIC_ISPR_SETPEND_13            (0x00002000U)                           ///< bit 13
+#define NVIC_ISPR_SETPEND_14            (0x00004000U)                           ///< bit 14
+#define NVIC_ISPR_SETPEND_15            (0x00008000U)                           ///< bit 15
+#define NVIC_ISPR_SETPEND_16            (0x00010000U)                           ///< bit 16
+#define NVIC_ISPR_SETPEND_17            (0x00020000U)                           ///< bit 17
+#define NVIC_ISPR_SETPEND_18            (0x00040000U)                           ///< bit 18
+#define NVIC_ISPR_SETPEND_19            (0x00080000U)                           ///< bit 19
+#define NVIC_ISPR_SETPEND_20            (0x00100000U)                           ///< bit 20
+#define NVIC_ISPR_SETPEND_21            (0x00200000U)                           ///< bit 21
+#define NVIC_ISPR_SETPEND_22            (0x00400000U)                           ///< bit 22
+#define NVIC_ISPR_SETPEND_23            (0x00800000U)                           ///< bit 23
+#define NVIC_ISPR_SETPEND_24            (0x01000000U)                           ///< bit 24
+#define NVIC_ISPR_SETPEND_25            (0x02000000U)                           ///< bit 25
+#define NVIC_ISPR_SETPEND_26            (0x04000000U)                           ///< bit 26
+#define NVIC_ISPR_SETPEND_27            (0x08000000U)                           ///< bit 27
+#define NVIC_ISPR_SETPEND_28            (0x10000000U)                           ///< bit 28
+#define NVIC_ISPR_SETPEND_29            (0x20000000U)                           ///< bit 29
+#define NVIC_ISPR_SETPEND_30            (0x40000000U)                           ///< bit 30
+#define NVIC_ISPR_SETPEND_31            (0x80000000U)                           ///< bit 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_ICPR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_ICPR_CLRPEND               (0xFFFFFFFFU)                           ///< Interrupt clear-pending bits
+#define NVIC_ICPR_CLRPEND_0             (0x00000001U)                           ///< bit 0
+#define NVIC_ICPR_CLRPEND_1             (0x00000002U)                           ///< bit 1
+#define NVIC_ICPR_CLRPEND_2             (0x00000004U)                           ///< bit 2
+#define NVIC_ICPR_CLRPEND_3             (0x00000008U)                           ///< bit 3
+#define NVIC_ICPR_CLRPEND_4             (0x00000010U)                           ///< bit 4
+#define NVIC_ICPR_CLRPEND_5             (0x00000020U)                           ///< bit 5
+#define NVIC_ICPR_CLRPEND_6             (0x00000040U)                           ///< bit 6
+#define NVIC_ICPR_CLRPEND_7             (0x00000080U)                           ///< bit 7
+#define NVIC_ICPR_CLRPEND_8             (0x00000100U)                           ///< bit 8
+#define NVIC_ICPR_CLRPEND_9             (0x00000200U)                           ///< bit 9
+#define NVIC_ICPR_CLRPEND_10            (0x00000400U)                           ///< bit 10
+#define NVIC_ICPR_CLRPEND_11            (0x00000800U)                           ///< bit 11
+#define NVIC_ICPR_CLRPEND_12            (0x00001000U)                           ///< bit 12
+#define NVIC_ICPR_CLRPEND_13            (0x00002000U)                           ///< bit 13
+#define NVIC_ICPR_CLRPEND_14            (0x00004000U)                           ///< bit 14
+#define NVIC_ICPR_CLRPEND_15            (0x00008000U)                           ///< bit 15
+#define NVIC_ICPR_CLRPEND_16            (0x00010000U)                           ///< bit 16
+#define NVIC_ICPR_CLRPEND_17            (0x00020000U)                           ///< bit 17
+#define NVIC_ICPR_CLRPEND_18            (0x00040000U)                           ///< bit 18
+#define NVIC_ICPR_CLRPEND_19            (0x00080000U)                           ///< bit 19
+#define NVIC_ICPR_CLRPEND_20            (0x00100000U)                           ///< bit 20
+#define NVIC_ICPR_CLRPEND_21            (0x00200000U)                           ///< bit 21
+#define NVIC_ICPR_CLRPEND_22            (0x00400000U)                           ///< bit 22
+#define NVIC_ICPR_CLRPEND_23            (0x00800000U)                           ///< bit 23
+#define NVIC_ICPR_CLRPEND_24            (0x01000000U)                           ///< bit 24
+#define NVIC_ICPR_CLRPEND_25            (0x02000000U)                           ///< bit 25
+#define NVIC_ICPR_CLRPEND_26            (0x04000000U)                           ///< bit 26
+#define NVIC_ICPR_CLRPEND_27            (0x08000000U)                           ///< bit 27
+#define NVIC_ICPR_CLRPEND_28            (0x10000000U)                           ///< bit 28
+#define NVIC_ICPR_CLRPEND_29            (0x20000000U)                           ///< bit 29
+#define NVIC_ICPR_CLRPEND_30            (0x40000000U)                           ///< bit 30
+#define NVIC_ICPR_CLRPEND_31            (0x80000000U)                           ///< bit 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_IABR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IABR_ACTIVE                (0xFFFFFFFFU)                           ///< Interrupt active flags
+#define NVIC_IABR_ACTIVE_0              (0x00000001U)                           ///< bit 0
+#define NVIC_IABR_ACTIVE_1              (0x00000002U)                           ///< bit 1
+#define NVIC_IABR_ACTIVE_2              (0x00000004U)                           ///< bit 2
+#define NVIC_IABR_ACTIVE_3              (0x00000008U)                           ///< bit 3
+#define NVIC_IABR_ACTIVE_4              (0x00000010U)                           ///< bit 4
+#define NVIC_IABR_ACTIVE_5              (0x00000020U)                           ///< bit 5
+#define NVIC_IABR_ACTIVE_6              (0x00000040U)                           ///< bit 6
+#define NVIC_IABR_ACTIVE_7              (0x00000080U)                           ///< bit 7
+#define NVIC_IABR_ACTIVE_8              (0x00000100U)                           ///< bit 8
+#define NVIC_IABR_ACTIVE_9              (0x00000200U)                           ///< bit 9
+#define NVIC_IABR_ACTIVE_10             (0x00000400U)                           ///< bit 10
+#define NVIC_IABR_ACTIVE_11             (0x00000800U)                           ///< bit 11
+#define NVIC_IABR_ACTIVE_12             (0x00001000U)                           ///< bit 12
+#define NVIC_IABR_ACTIVE_13             (0x00002000U)                           ///< bit 13
+#define NVIC_IABR_ACTIVE_14             (0x00004000U)                           ///< bit 14
+#define NVIC_IABR_ACTIVE_15             (0x00008000U)                           ///< bit 15
+#define NVIC_IABR_ACTIVE_16             (0x00010000U)                           ///< bit 16
+#define NVIC_IABR_ACTIVE_17             (0x00020000U)                           ///< bit 17
+#define NVIC_IABR_ACTIVE_18             (0x00040000U)                           ///< bit 18
+#define NVIC_IABR_ACTIVE_19             (0x00080000U)                           ///< bit 19
+#define NVIC_IABR_ACTIVE_20             (0x00100000U)                           ///< bit 20
+#define NVIC_IABR_ACTIVE_21             (0x00200000U)                           ///< bit 21
+#define NVIC_IABR_ACTIVE_22             (0x00400000U)                           ///< bit 22
+#define NVIC_IABR_ACTIVE_23             (0x00800000U)                           ///< bit 23
+#define NVIC_IABR_ACTIVE_24             (0x01000000U)                           ///< bit 24
+#define NVIC_IABR_ACTIVE_25             (0x02000000U)                           ///< bit 25
+#define NVIC_IABR_ACTIVE_26             (0x04000000U)                           ///< bit 26
+#define NVIC_IABR_ACTIVE_27             (0x08000000U)                           ///< bit 27
+#define NVIC_IABR_ACTIVE_28             (0x10000000U)                           ///< bit 28
+#define NVIC_IABR_ACTIVE_29             (0x20000000U)                           ///< bit 29
+#define NVIC_IABR_ACTIVE_30             (0x40000000U)                           ///< bit 30
+#define NVIC_IABR_ACTIVE_31             (0x80000000U)                           ///< bit 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI0 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR0_PRI_0                 (0x000000FFU)                           ///< Priority of interrupt 0
+#define NVIC_IPR0_PRI_1                 (0x0000FF00U)                           ///< Priority of interrupt 1
+#define NVIC_IPR0_PRI_2                 (0x00FF0000U)                           ///< Priority of interrupt 2
+#define NVIC_IPR0_PRI_3                 (0xFF000000U)                           ///< Priority of interrupt 3
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR1_PRI_4                 (0x000000FFU)                           ///< Priority of interrupt 4
+#define NVIC_IPR1_PRI_5                 (0x0000FF00U)                           ///< Priority of interrupt 5
+#define NVIC_IPR1_PRI_6                 (0x00FF0000U)                           ///< Priority of interrupt 6
+#define NVIC_IPR1_PRI_7                 (0xFF000000U)                           ///< Priority of interrupt 7
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR2_PRI_8                 (0x000000FFU)                           ///< Priority of interrupt 8
+#define NVIC_IPR2_PRI_9                 (0x0000FF00U)                           ///< Priority of interrupt 9
+#define NVIC_IPR2_PRI_10                (0x00FF0000U)                           ///< Priority of interrupt 10
+#define NVIC_IPR2_PRI_11                (0xFF000000U)                           ///< Priority of interrupt 11
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI3 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR3_PRI_12                (0x000000FFU)                           ///< Priority of interrupt 12
+#define NVIC_IPR3_PRI_13                (0x0000FF00U)                           ///< Priority of interrupt 13
+#define NVIC_IPR3_PRI_14                (0x00FF0000U)                           ///< Priority of interrupt 14
+#define NVIC_IPR3_PRI_15                (0xFF000000U)                           ///< Priority of interrupt 15
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI4 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR4_PRI_16                (0x000000FFU)                           ///< Priority of interrupt 16
+#define NVIC_IPR4_PRI_17                (0x0000FF00U)                           ///< Priority of interrupt 17
+#define NVIC_IPR4_PRI_18                (0x00FF0000U)                           ///< Priority of interrupt 18
+#define NVIC_IPR4_PRI_19                (0xFF000000U)                           ///< Priority of interrupt 19
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI5 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR5_PRI_20                (0x000000FFU)                           ///< Priority of interrupt 20
+#define NVIC_IPR5_PRI_21                (0x0000FF00U)                           ///< Priority of interrupt 21
+#define NVIC_IPR5_PRI_22                (0x00FF0000U)                           ///< Priority of interrupt 22
+#define NVIC_IPR5_PRI_23                (0xFF000000U)                           ///< Priority of interrupt 23
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI6 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR6_PRI_24                (0x000000FFU)                           ///< Priority of interrupt 24
+#define NVIC_IPR6_PRI_25                (0x0000FF00U)                           ///< Priority of interrupt 25
+#define NVIC_IPR6_PRI_26                (0x00FF0000U)                           ///< Priority of interrupt 26
+#define NVIC_IPR6_PRI_27                (0xFF000000U)                           ///< Priority of interrupt 27
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI7 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR7_PRI_28                (0x000000FFU)                           ///< Priority of interrupt 28
+#define NVIC_IPR7_PRI_29                (0x0000FF00U)                           ///< Priority of interrupt 29
+#define NVIC_IPR7_PRI_30                (0x00FF0000U)                           ///< Priority of interrupt 30
+#define NVIC_IPR7_PRI_31                (0xFF000000U)                           ///< Priority of interrupt 31
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI8 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR7_PRI_32                (0x000000FFU)                           ///< Priority of interrupt 32
+#define NVIC_IPR7_PRI_33                (0x0000FF00U)                           ///< Priority of interrupt 33
+#define NVIC_IPR7_PRI_34                (0x00FF0000U)                           ///< Priority of interrupt 34
+#define NVIC_IPR7_PRI_35                (0xFF000000U)                           ///< Priority of interrupt 35
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI9 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR7_PRI_36                (0x000000FFU)                           ///< Priority of interrupt 36
+#define NVIC_IPR7_PRI_37                (0x0000FF00U)                           ///< Priority of interrupt 37
+#define NVIC_IPR7_PRI_38                (0x00FF0000U)                           ///< Priority of interrupt 38
+#define NVIC_IPR7_PRI_39                (0xFF000000U)                           ///< Priority of interrupt 39
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI10 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR7_PRI_40                (0x000000FFU)                           ///< Priority of interrupt 40
+#define NVIC_IPR7_PRI_41                (0x0000FF00U)                           ///< Priority of interrupt 41
+#define NVIC_IPR7_PRI_42                (0x00FF0000U)                           ///< Priority of interrupt 42
+#define NVIC_IPR7_PRI_43                (0xFF000000U)                           ///< Priority of interrupt 43
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief NVIC_PRI11 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define NVIC_IPR7_PRI_44                (0x000000FFU)                           ///< Priority of interrupt 44
+#define NVIC_IPR7_PRI_45                (0x0000FF00U)                           ///< Priority of interrupt 45
+#define NVIC_IPR7_PRI_46                (0x00FF0000U)                           ///< Priority of interrupt 46
+#define NVIC_IPR7_PRI_47                (0xFF000000U)                           ///< Priority of interrupt 47
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_CPUID Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_CPUID_REVISION              (0x0000000FU)                           ///< Implementation defined revision number
+#define SCB_CPUID_PARTNO                (0x0000FFF0U)                           ///< Number of processor within family
+#define SCB_CPUID_Constant              (0x000F0000U)                           ///< Reads as 0x0F
+#define SCB_CPUID_VARIANT               (0x00F00000U)                           ///< Implementation defined variant number
+#define SCB_CPUID_IMPLEMENTER           (0xFF000000U)                           ///< Implementer code. ARM is 0x41
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_ICSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_ICSR_VECTACTIVE             (0x000001FFU)                           ///< Active ISR number field
+#define SCB_ICSR_RETTOBASE              (0x00000800U)                           ///< All active exceptions minus the IPSR_current_exception yields the empty set
+#define SCB_ICSR_VECTPENDING            (0x003FF000U)                           ///< Pending ISR number field
+#define SCB_ICSR_ISRPENDING             (0x00400000U)                           ///< Interrupt pending flag
+#define SCB_ICSR_ISRPREEMPT             (0x00800000U)                           ///< It indicates that a pending interrupt becomes active in the next running cycle
+#define SCB_ICSR_PENDSTCLR              (0x02000000U)                           ///< Clear pending SysTick bit
+#define SCB_ICSR_PENDSTSET              (0x04000000U)                           ///< Set pending SysTick bit
+#define SCB_ICSR_PENDSVCLR              (0x08000000U)                           ///< Clear pending pendSV bit
+#define SCB_ICSR_PENDSVSET              (0x10000000U)                           ///< Set pending pendSV bit
+#define SCB_ICSR_NMIPENDSET             (0x80000000U)                           ///< Set pending NMI bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_VTOR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_VTOR_TBLOFF                 (0x1FFFFF80U)                           ///< Vector table base offset field
+#define SCB_VTOR_TBLBASE                (0x20000000U)                           ///< Table base in code(0) or RAM(1)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_AIRCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_AIRCR_VECTRESET             (0x00000001U)                           ///< System Reset bit
+#define SCB_AIRCR_VECTCLRACTIVE         (0x00000002U)                           ///< Clear active vector bit
+#define SCB_AIRCR_SYSRESETREQ           (0x00000004U)                           ///< Requests chip control logic to generate a reset
+#define SCB_AIRCR_PRIGROUP              (0x00000700U)                           ///< PRIGROUP[2:0] bits (Priority group)
+#define SCB_AIRCR_PRIGROUP_0            (0x00000100U)                           ///< Bit 0
+#define SCB_AIRCR_PRIGROUP_1            (0x00000200U)                           ///< Bit 1
+#define SCB_AIRCR_PRIGROUP_2            (0x00000400U)                           ///< Bit 2
+
+#define SCB_AIRCR_PRIGROUP0             (0x00000000U)                           ///< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)
+#define SCB_AIRCR_PRIGROUP1             (0x00000100U)                           ///< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP2             (0x00000200U)                           ///< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP3             (0x00000300U)                           ///< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP4             (0x00000400U)                           ///< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP5             (0x00000500U)                           ///< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP6             (0x00000600U)                           ///< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)
+#define SCB_AIRCR_PRIGROUP7             (0x00000700U)                           ///< Priority group=7 (no pre-emption priority, 8 bits of subpriority)
+
+#define SCB_AIRCR_ENDIANESS             (0x00008000U)                           ///< Data endianness bit
+#define SCB_AIRCR_VECTKEY               (0xFFFF0000U)                           ///< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_SCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_SCR_SLEEPONEXIT             (0x02U)                                 ///< Sleep on exit bit
+#define SCB_SCR_SLEEPDEEP               (0x04U)                                 ///< Sleep deep bit
+#define SCB_SCR_SEVONPEND               (0x10U)                                 ///< Wake up from WFE
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_CCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_CCR_NONBASETHRDENA          (0x0001U)                               ///< Thread mode can be entered from any level in Handler mode by controlled return value
+#define SCB_CCR_USERSETMPEND            (0x0002U)                               ///< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception
+#define SCB_CCR_UNALIGN_TRP             (0x0008U)                               ///< Trap for unaligned access
+#define SCB_CCR_DIV_0_TRP               (0x0010U)                               ///< Trap on Divide by 0
+#define SCB_CCR_BFHFNMIGN               (0x0100U)                               ///< Handlers running at priority -1 and -2
+#define SCB_CCR_STKALIGN                (0x0200U)                               ///< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_SHPR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_SHPR_PRI_N                  (0x000000FFU)                           ///< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor
+#define SCB_SHPR_PRI_N1                 (0x0000FF00U)                           ///< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved
+#define SCB_SHPR_PRI_N2                 (0x00FF0000U)                           ///< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV
+#define SCB_SHPR_PRI_N3                 (0xFF000000U)                           ///< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_SHCSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_SHCSR_MEMFAULTACT           (0x00000001U)                           ///< MemManage is active
+#define SCB_SHCSR_BUSFAULTACT           (0x00000002U)                           ///< BusFault is active
+#define SCB_SHCSR_USGFAULTACT           (0x00000008U)                           ///< UsageFault is active
+#define SCB_SHCSR_SVCALLACT             (0x00000080U)                           ///< SVCall is active
+#define SCB_SHCSR_MONITORACT            (0x00000100U)                           ///< Monitor is active
+#define SCB_SHCSR_PENDSVACT             (0x00000400U)                           ///< PendSV is active
+#define SCB_SHCSR_SYSTICKACT            (0x00000800U)                           ///< SysTick is active
+#define SCB_SHCSR_USGFAULTPENDED        (0x00001000U)                           ///< Usage Fault is pended
+#define SCB_SHCSR_MEMFAULTPENDED        (0x00002000U)                           ///< MemManage is pended
+#define SCB_SHCSR_BUSFAULTPENDED        (0x00004000U)                           ///< Bus Fault is pended
+#define SCB_SHCSR_SVCALLPENDED          (0x00008000U)                           ///< SVCall is pended
+#define SCB_SHCSR_MEMFAULTENA           (0x00010000U)                           ///< MemManage enable
+#define SCB_SHCSR_BUSFAULTENA           (0x00020000U)                           ///< Bus Fault enable
+#define SCB_SHCSR_USGFAULTENA           (0x00040000U)                           ///< UsageFault enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_CFSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+///< MFSR
+#define SCB_CFSR_IACCVIOL               (0x00000001U)                           ///< Instruction access violation
+#define SCB_CFSR_DACCVIOL               (0x00000002U)                           ///< Data access violation
+#define SCB_CFSR_MUNSTKERR              (0x00000008U)                           ///< Unstacking error
+#define SCB_CFSR_MSTKERR                (0x00000010U)                           ///< Stacking error
+#define SCB_CFSR_MMARVALID              (0x00000080U)                           ///< Memory Manage Address Register address valid flag
+///< BFSR
+#define SCB_CFSR_IBUSERR                (0x00000100U)                           ///< Instruction bus error flag
+#define SCB_CFSR_PRECISERR              (0x00000200U)                           ///< Precise data bus error
+#define SCB_CFSR_IMPRECISERR            (0x00000400U)                           ///< Imprecise data bus error
+#define SCB_CFSR_UNSTKERR               (0x00000800U)                           ///< Unstacking error
+#define SCB_CFSR_STKERR                 (0x00001000U)                           ///< Stacking error
+#define SCB_CFSR_BFARVALID              (0x00008000U)                           ///< Bus Fault Address Register address valid flag
+///< UFSR
+#define SCB_CFSR_UNDEFINSTR             (0x00010000U)                           ///< The processor attempt to excecute an undefined instruction
+#define SCB_CFSR_INVSTATE               (0x00020000U)                           ///< Invalid combination of EPSR and instruction
+#define SCB_CFSR_INVPC                  (0x00040000U)                           ///< Attempt to load EXC_RETURN into pc illegally
+#define SCB_CFSR_NOCP                   (0x00080000U)                           ///< Attempt to use a coprocessor instruction
+#define SCB_CFSR_UNALIGNED              (0x01000000U)                           ///< Fault occurs when there is an attempt to make an unaligned memory access
+#define SCB_CFSR_DIVBYZERO              (0x02000000U)                           ///< Fault occurs when SDIV or DIV instruction is used with a divisor of 0
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_HFSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_HFSR_VECTTBL                (0x00000002U)                           ///< Fault occures because of vector table read on exception processing
+#define SCB_HFSR_FORCED                 (0x40000000U)                           ///< Hard Fault activated when a configurable Fault was received and cannot activate
+#define SCB_HFSR_DEBUGEVT               (0x80000000U)                           ///< Fault related to debug
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_DFSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_DFSR_HALTED                 (0x01U)                                 ///< Halt request flag
+#define SCB_DFSR_BKPT                   (0x02U)                                 ///< BKPT flag
+#define SCB_DFSR_DWTTRAP                (0x04U)                                 ///< Data Watchpoint and Trace (DWT) flag
+#define SCB_DFSR_VCATCH                 (0x08U)                                 ///< Vector catch flag
+#define SCB_DFSR_EXTERNAL               (0x10U)                                 ///< External debug request flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_MMFAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_MMFAR_ADDRESS               (0xFFFFFFFFU)                           ///< Mem Manage fault address field
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_BFAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_BFAR_ADDRESS                (0xFFFFFFFFU)                           ///< Bus fault address field
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SCB_AFSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SCB_AFSR_IMPDEF                 (0xFFFFFFFFU)                           ///< Implementation defined
+
+
+
+#endif
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h
new file mode 100644
index 000000000..71297819c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h
@@ -0,0 +1,228 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_comp.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_COMP_H
+#define __REG_COMP_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define COMP_BASE                       (APB2PERIPH_BASE + 0x4000)              ///< Base Address: 0x40014000
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Comparators Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+
+
+
+    __IO u32 RESERVED1;                                                         ///<                                                offset: 0x00
+    __IO u32 RESERVED2;                                                         ///<                                                offset: 0x04
+    __IO u32 RESERVED3;                                                         ///<                                                offset: 0x08
+    union {
+        __IO u32 CSR1;                                                          ///< COMP1 Control Status Register                  offset: 0x0C
+        __IO u32 COMP1_CSR;
+    };
+    union {
+        __IO u32 CSR2;                                                          ///< COMP2 Control Status Register                  offset: 0x10
+        __IO u32 COMP2_CSR;
+    };
+    __IO u32 RESERVED4;                                                         ///<                                                offset: 0x14
+    union {
+        __IO u32 CRV;                                                           ///< COMP external reference voltage register       offset: 0x18
+        __IO u32 COMP_CRV;
+    };
+    union {
+        __IO u32 POLL1;                                                         ///< COMP1 polling register                         offset: 0x1C
+        __IO u32 COMP1_POLL;
+    };
+    union {
+        __IO u32 POLL2;                                                         ///< COMP2 polling register                         offset: 0x20
+        __IO u32 COMP2_POLL;
+    };
+} COMP_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define COMP                            ((COMP_TypeDef*) COMP_BASE)
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define COMP_CSR_EN_Pos             (0)
+#define COMP_CSR_EN                 (0x01U << COMP_CSR_EN_Pos)              ///< Comparator enable
+#define COMP_CSR_MODE_Pos           (2)
+#define COMP_CSR_MODE               (0x03U << COMP_CSR_MODE_Pos)            ///< Comparator mode
+#define COMP_CSR_MODE_LOWESTPOWER   (0x00U << COMP_CSR_MODE_Pos)            ///< Comparator lowest power mode
+#define COMP_CSR_MODE_LOWPOWER      (0x01U << COMP_CSR_MODE_Pos)            ///< Comparator low power mode
+#define COMP_CSR_MODE_MEDIUMRATE    (0x02U << COMP_CSR_MODE_Pos)            ///< Comparator medium rate mode
+#define COMP_CSR_MODE_HIGHRATE      (0x03U << COMP_CSR_MODE_Pos)            ///< Comparator high rate mode
+
+#define COMP_CSR_INM_Pos            (4)
+#define COMP_CSR_INM                (0x03U << COMP_CSR_INM_Pos)             ///< Comparator inverting input selection
+#define COMP_CSR_INM_0              (0x00U << COMP_CSR_INM_Pos)             ///< INM0 as COMP inverting input
+#define COMP_CSR_INM_1              (0x01U << COMP_CSR_INM_Pos)             ///< INM1 as COMP inverting input
+#define COMP_CSR_INM_2              (0x02U << COMP_CSR_INM_Pos)             ///< INM2 as COMP inverting input
+#define COMP_CSR_INM_3              (0x03U << COMP_CSR_INM_Pos)             ///< INM3 as COMP inverting input
+
+#define COMP_CSR_INP_Pos            (7)
+#define COMP_CSR_INP                (0x03U << COMP_CSR_INP_Pos)             ///< Comparator non-inverting input selection
+#define COMP_CSR_INP_INP0           (0x00U << COMP_CSR_INP_Pos)             ///< INP0 as COMP non-inverting input
+#define COMP_CSR_INP_INP1           (0x01U << COMP_CSR_INP_Pos)             ///< INP1 as COMP non-inverting input
+#define COMP_CSR_INP_INP2           (0x02U << COMP_CSR_INP_Pos)             ///< INP2 as COMP non-inverting input
+#define COMP_CSR_INP_INP3           (0x03U << COMP_CSR_INP_Pos)             ///< INP3 as COMP non-inverting input
+
+#define COMP_CSR_OUT_Pos            (10)
+#define COMP_CSR_OUT                (0x0FU << COMP_CSR_OUT_Pos)             ///< Comparator output selection
+#define COMP_CSR_OUT_TIM1_BRAKE     (0x02U << COMP_CSR_OUT_Pos)             ///< Timer1 brake input
+#define COMP_CSR_OUT_TIM8_BRAKE     (0x03U << COMP_CSR_OUT_Pos)             ///< Timer8 brake input
+#define COMP_CSR_OUT_TIM1_OCREFCLR  (0x06U << COMP_CSR_OUT_Pos)             ///< Timer1 ocrefclear input
+#define COMP_CSR_OUT_TIM1_CAPTURE1  (0x07U << COMP_CSR_OUT_Pos)             ///< Timer1 input capture 1
+#define COMP_CSR_OUT_TIM2_CAPTURE4  (0x08U << COMP_CSR_OUT_Pos)             ///< Timer2 input capture 4
+#define COMP_CSR_OUT_TIM2_OCREFCLR  (0x09U << COMP_CSR_OUT_Pos)             ///< Timer2 ocrefclear input
+#define COMP_CSR_OUT_TIM3_CAPTURE1  (0x0AU << COMP_CSR_OUT_Pos)             ///< Timer3 input capture 1
+#define COMP_CSR_OUT_TIM3_OCREFCLR  (0x0BU << COMP_CSR_OUT_Pos)             ///< Timer3 ocrefclear input
+#define COMP_CSR_OUT_TIM8_OCREFCLR  (0x0FU << COMP_CSR_OUT_Pos)             ///< Timer8 ocrefclear input
+
+#define COMP_CSR_POL_Pos            (15)
+#define COMP_CSR_POL                (0x01U << COMP_CSR_POL_Pos)             ///< Comparator output polarity
+#define COMP_CSR_HYST_Pos           (16)
+#define COMP_CSR_HYST               (0x03U << COMP_CSR_HYST_Pos)            ///< Comparator hysteresis
+#define COMP_CSR_HYST_0             (0x00U << COMP_CSR_HYST_Pos)            ///< Hysteresis Voltage: 0mV
+#define COMP_CSR_HYST_15            (0x01U << COMP_CSR_HYST_Pos)            ///< Hysteresis Voltage: 15mV
+#define COMP_CSR_HYST_30            (0x02U << COMP_CSR_HYST_Pos)            ///< Hysteresis Voltage: 30mV
+#define COMP_CSR_HYST_90            (0x03U << COMP_CSR_HYST_Pos)            ///< Hysteresis Voltage: 90mV
+
+#define COMP_CSR_OFLT_Pos           (18)
+#define COMP_CSR_OFLT               (0x07U << COMP_CSR_OFLT_Pos)            ///< Comparator output filter
+#define COMP_CSR_OFLT_0             (0x00U << COMP_CSR_OFLT_Pos)            ///< 0 clock cycle
+#define COMP_CSR_OFLT_1             (0x01U << COMP_CSR_OFLT_Pos)            ///< 2 clock cycle
+#define COMP_CSR_OFLT_2             (0x02U << COMP_CSR_OFLT_Pos)            ///< 4 clock cycle
+#define COMP_CSR_OFLT_3             (0x03U << COMP_CSR_OFLT_Pos)            ///< 8 clock cycle
+#define COMP_CSR_OFLT_4             (0x04U << COMP_CSR_OFLT_Pos)            ///< 16 clock cycle
+#define COMP_CSR_OFLT_5             (0x05U << COMP_CSR_OFLT_Pos)            ///< 32 clock cycle
+#define COMP_CSR_OFLT_6             (0x06U << COMP_CSR_OFLT_Pos)            ///< 64 clock cycle
+#define COMP_CSR_OFLT_7             (0x07U << COMP_CSR_OFLT_Pos)            ///< 128 clock cycle
+
+#define COMP_CSR_STA_Pos            (30)
+#define COMP_CSR_STA                (0x01U << COMP_CSR_STA_Pos)             ///< Comparator output status
+#define COMP_CSR_LOCK_Pos           (31)
+#define COMP_CSR_LOCK               (0x01U << COMP_CSR_LOCK_Pos)            ///< Comparator lock
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_CRV Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define COMP_CRV_Pos                (0)
+#define COMP_CRV_MASK               (0x0FU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_1_20               (0x00U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_2_20               (0x01U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_3_20               (0x02U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_4_20               (0x03U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_5_20               (0x04U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_6_20               (0x05U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_7_20               (0x06U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_8_20               (0x07U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_9_20               (0x08U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_10_20              (0x09U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_11_20              (0x0AU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_12_20              (0x0BU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_13_20              (0x0CU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_14_20              (0x0DU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_15_20              (0x0EU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+#define COMP_CRV_16_20              (0x0FU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
+
+#define COMP_CRV_EN_Pos             (4)
+#define COMP_CRV_EN                 (0x01U << COMP_CRV_EN_Pos)              ///< Comparator external reference voltage enable
+#define COMP_CRV_EN_DISABLE         (0x00U << COMP_CRV_EN_Pos)              ///< Disable comparator external reference voltage
+#define COMP_CRV_EN_ENABLE          (0x01U << COMP_CRV_EN_Pos)              ///< Enable comparator external reference voltage
+#define COMP_CRV_SRC_Pos            (5)
+#define COMP_CRV_SRC                (0x01U << COMP_CRV_SRC_Pos)             ///< Comparator external reference voltage source select
+#define COMP_CRV_SRC_VREF           (0x00U << COMP_CRV_SRC_Pos)             ///< Select VREF
+#define COMP_CRV_SRC_AVDD           (0x01U << COMP_CRV_SRC_Pos)             ///< Select AVDD
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief COMP_POL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define COMP_POLL_EN_Pos            (0)
+#define COMP_POLL_EN                (0x01U << COMP_POLL_EN_Pos)              ///< Comparator polling enable
+#define COMP_POLL_EN_DISABLE        (0x00U << COMP_POLL_EN_Pos)              ///< Disable comparator polling mode
+#define COMP_POLL_EN_ENABLE         (0x01U << COMP_POLL_EN_Pos)              ///< Enable comparator polling mode
+#define COMP_POLL_CH_Pos            (1)
+#define COMP_POLL_CH                (0x01U << COMP_POLL_CH_Pos)              ///< Comparator polling channel
+#define COMP_POLL_CH_1_2            (0x00U << COMP_POLL_CH_Pos)              ///< Polling channel 1/2
+#define COMP_POLL_CH_1_2_3          (0x01U << COMP_POLL_CH_Pos)              ///< Polling channel 1/2/3
+#define COMP_POLL_FIXN_Pos          (2)
+#define COMP_POLL_FIXN              (0x01U << COMP_POLL_FIXN_Pos)            ///< Polling inverting input fix
+#define COMP_POLL_FIXN_NOTFIXED     (0x00U << COMP_POLL_FIXN_Pos)            ///< Polling channel inverting input is not fixed
+#define COMP_POLL_FIXN_FIXED        (0x01U << COMP_POLL_FIXN_Pos)            ///< Polling channel inverting input fixed
+#define COMP_POLL_PERIOD_Pos        (4)
+#define COMP_POLL_PERIOD            (0x07U << COMP_POLL_PERIOD_Pos)          ///< polling wait cycle
+#define COMP_POLL_PERIOD_1          (0x00U << COMP_POLL_PERIOD_Pos)          ///< 1 clock cycle
+#define COMP_POLL_PERIOD_2          (0x01U << COMP_POLL_PERIOD_Pos)          ///< 2 clock cycle
+#define COMP_POLL_PERIOD_4          (0x02U << COMP_POLL_PERIOD_Pos)          ///< 4 clock cycle
+#define COMP_POLL_PERIOD_8          (0x03U << COMP_POLL_PERIOD_Pos)          ///< 8 clock cycle
+#define COMP_POLL_PERIOD_16         (0x04U << COMP_POLL_PERIOD_Pos)          ///< 16 clock cycle
+#define COMP_POLL_PERIOD_32         (0x05U << COMP_POLL_PERIOD_Pos)          ///< 32 clock cycle
+#define COMP_POLL_PERIOD_64         (0x06U << COMP_POLL_PERIOD_Pos)          ///< 64 clock cycle
+#define COMP_POLL_PERIOD_128        (0x07U << COMP_POLL_PERIOD_Pos)          ///< 128 clock cycle
+#define COMP_POLL_POUT_Pos          (8)
+#define COMP_POLL_POUT              (0x07U << COMP_POLL_POUT_Pos)            ///< Polling output
+#define COMP_POLL_POUT_Low          (0x00U << COMP_POLL_POUT_Pos)            ///< Non-inverting input is lower than inverting input
+#define COMP_POLL_POUT_High         (0x01U << COMP_POLL_POUT_Pos)            ///< Non-inverting input is higher than inverting input
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h
new file mode 100644
index 000000000..9bb28e56f
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h
@@ -0,0 +1,102 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_crc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_CRC_H
+#define __REG_CRC_H
+
+// Files includes
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC_BASE                        (AHBPERIPH_BASE + 0x3000)               ///< Base Address: 0x40023000
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32   DR;                                                              ///< CRC data register,                             offset: 0x00
+    __IO u32   IDR;                                                             ///< CRC independent data register,                 offset: 0x04
+    __IO u32   CR;                                                              ///< CRC control register,                          offset: 0x08
+    __IO u32   MIR;                                                              ///< Middle data register,                          offset: 0x08
+} CRC_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC                             ((CRC_TypeDef*) CRC_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC_DR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC_DR_DATA_Pos                 (0)
+#define CRC_DR_DATA                     (0xFFFFFFFFU << CRC_DR_DATA_Pos)        ///< Data register bits
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC_IDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC_IDR_DATA_Pos                (0)
+#define CRC_IDR_DATA                    (0xFFU << CRC_IDR_DATA_Pos)             ///< General-purpose 8-bit data register bits
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC_CTRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC_CR_RESET_Pos                (0)
+#define CRC_CR_RESET                    (0x01U << CRC_CR_RESET_Pos)             ///< RESET bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRC_MIR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRC_MIR_Pos                 (0)
+#define CRC_MIR                     (0xFFFFFFFFU << CRC_MIR_Pos)        ///< Middle data register
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h
new file mode 100644
index 000000000..a8beece98
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h
@@ -0,0 +1,152 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_crs.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_CRS_H
+#define __REG_CRS_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_BASE                        (APB1PERIPH_BASE + 0x6C00)              ///< Base Address: 0x40006C00
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 CR;                                                                ///< Control Register                    offset: 0x00
+    __IO u32 CFGR;                                                              ///< Configuration Register              offset: 0x04
+    __IO u32 ISR;                                                               ///< Interrupt and Status Register       offset: 0x08
+    __IO u32 ICR;                                                               ///< Interrupt Flag Clear Register       offset: 0x0C
+} CRS_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS                         ((CRS_TypeDef*) CRS_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_CR_OKIE_Pos             (0)
+#define CRS_CR_OKIE                 (0x01U << CRS_CR_OKIE_Pos)              ///< SYNC event OK interrupt enable
+#define CRS_CR_WARNIE_Pos           (1)
+#define CRS_CR_WARNIE               (0x01U << CRS_CR_WARNIE_Pos)            ///< SYNC warning interrupt enable
+#define CRS_CR_ERRIE_Pos            (2)
+#define CRS_CR_ERRIE                (0x01U << CRS_CR_ERRIE_Pos)             ///< Synchronization or trimming error interrupt enable
+#define CRS_CR_EXPTIE_Pos           (3)
+#define CRS_CR_EXPTIE               (0x01U << CRS_CR_EXPTIE_Pos)            ///< Expected SYNC interrupt enable
+#define CRS_CR_CNTEN_Pos            (5)
+#define CRS_CR_CNTEN                (0x01U << CRS_CR_CNTEN_Pos)             ///< Frequency error counter enable
+#define CRS_CR_AUTOTRIMEN_Pos       (6)
+#define CRS_CR_AUTOTRIMEN           (0x01U << CRS_CR_AUTOTRIMEN_Pos)        ///< Automatic trimming enable
+#define CRS_CR_SWSYNC_Pos           (7)
+#define CRS_CR_SWSYNC               (0x01U << CRS_CR_SWSYNC_Pos)            ///< Generate software SYNC event
+#define CRS_CR_TRIM_Pos             (8)
+#define CRS_CR_TRIM                 (0x3FFU << CRS_CR_TRIM_Pos)              ///< HSI 48 oscillator smooth trimming
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS_CFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_CFGR_RELOAD_Pos         (0)
+#define CRS_CFGR_RELOAD             (0xFFFFU << CRS_CFGR_RELOAD_Pos)        ///< Counter reload value
+#define CRS_CFGR_FELIM_Pos          (16)
+#define CRS_CFGR_FELIM              (0xFFU << CRS_CFGR_FELIM_Pos)           ///< Frequency error limit
+#define CRS_CFGR_DIV_Pos            (24)
+#define CRS_CFGR_DIV                (0x07U << CRS_CFGR_DIV_Pos)             ///< SYNC divider
+#define CRS_CFGR_SRC_Pos            (28)
+#define CRS_CFGR_SRC                (0x03U << CRS_CFGR_SRC_Pos)             ///< SYNC signal source selection
+#define CRS_CFGR_SRC_MCO            (0x00U << CRS_CFGR_SRC_Pos)
+#define CRS_CFGR_SRC_USBSOF         (0x02U << CRS_CFGR_SRC_Pos)
+#define CRS_CFGR_POL_Pos            (31)
+#define CRS_CFGR_POL                (0x01U << CRS_CFGR_POL_Pos)             ///< SYNC polarity selection
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_ISR_OKIF_Pos            (0)
+#define CRS_ISR_OKIF                (0x01U << CRS_ISR_OKIF_Pos)             ///< SYNC event OK flag
+#define CRS_ISR_WARNIF_Pos          (1)
+#define CRS_ISR_WARNIF              (0x01U << CRS_ISR_WARNIF_Pos)           ///< SYNC warning flag
+#define CRS_ISR_ERRIF_Pos           (2)
+#define CRS_ISR_ERRIF               (0x01U << CRS_ISR_ERRIF_Pos)            ///< Error flag
+#define CRS_ISR_EXPTIF_Pos          (3)
+#define CRS_ISR_EXPTIF              (0x01U << CRS_ISR_EXPTIF_Pos)           ///< Expected SYNC flag
+#define CRS_ISR_ERR_Pos             (8)
+#define CRS_ISR_ERR                 (0x01U << CRS_ISR_ERR_Pos)              ///< SYNC error
+#define CRS_ISR_MISS_Pos            (9)
+#define CRS_ISR_MISS                (0x01U << CRS_ISR_MISS_Pos)             ///< SYNC missed
+#define CRS_ISR_OVERFLOW_Pos        (10)
+#define CRS_ISR_OVERFLOW            (0x01U << CRS_ISR_OVERFLOW_Pos)         ///< Trimming overflow or underflow
+#define CRS_ISR_FEDIR_Pos           (15)
+#define CRS_ISR_FEDIR               (0x01U << CRS_ISR_FEDIR_Pos)            ///< Frequency error direction
+#define CRS_ISR_FECAP_Pos           (16)
+#define CRS_ISR_FECAP               (0xFFFFU << CRS_ISR_FECAP_Pos)          ///< Frequency error capture
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CRS_ICR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CRS_ICR_OK_Pos              (0)
+#define CRS_ICR_OK                  (0x01U << CRS_ICR_OK_Pos)               ///< SYNC event OK clear flag
+#define CRS_ICR_WARN_Pos            (1)
+#define CRS_ICR_WARN                (0x01U << CRS_ICR_WARN_Pos)             ///< SYNC warning clear flag
+#define CRS_ICR_ERR_Pos             (2)
+#define CRS_ICR_ERR                 (0x01U << CRS_ICR_ERR_Pos)              ///< Error clear flag
+#define CRS_ICR_EXPT_Pos            (3)
+#define CRS_ICR_EXPT                (0x01U << CRS_ICR_EXPT_Pos)             ///< Expected SYNC clear flag
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h
new file mode 100644
index 000000000..2e8d1883d
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h
@@ -0,0 +1,247 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_dac.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_DAC_H
+#define __REG_DAC_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_BASE                        (APB1PERIPH_BASE + 0x7400)              ///< Base Address: 0x40007400
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Digital to analog converter register
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 CR;                                                                ///<  DAC control register,                         offset: 0x00
+    __IO u32 SWTRIGR;                                                           ///<  DAC software trigger register,                offset: 0x04
+    __IO u32 DHR12R1;                                                           ///<  Channel 1 12-bit right align data register,   offset: 0x08
+    __IO u32 DHR12L1;                                                           ///<  Channel 1 12-bit left align data register,    offset: 0x0C
+    __IO u32 DHR8R1;                                                            ///<  Channel 1 8-bit right align data register,    offset: 0x10
+    __IO u32 DHR12R2;                                                           ///<  Channel 2 12-bit right align data register,   offset: 0x14
+    __IO u32 DHR12L2;                                                           ///<  Channel 2 12-bit left align data register,    offset: 0x18
+    __IO u32 DHR8R2;                                                            ///<  Channel 2 8-bit right align data register,    offset: 0x1C
+    __IO u32 DHR12RD;                                                           ///<  Dual channel 12-bit right align data register,offset: 0x20
+    __IO u32 DHR12LD;                                                           ///<  Dual channel 12-bit left align data register, offset: 0x24
+    __IO u32 DHR8RD;                                                            ///<  Dual channel 8-bit right align data register, offset: 0x28
+    __IO u32 DOR1;                                                              ///<  Channel 1 output register,                    offset: 0x2C
+    __IO u32 DOR2;                                                              ///<  Channel 2 output register,                    offset: 0x30
+} DAC_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC                         ((DAC_TypeDef*) DAC_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_CR_EN1_Pos              (0)
+#define DAC_CR_EN1                  (0x01U << DAC_CR_EN1_Pos)               ///< DAC channel1 enable
+#define DAC_CR_BOFF1_Pos            (1)
+#define DAC_CR_BOFF1                (0x01U << DAC_CR_BOFF1_Pos)             ///< DAC channel1 output buffer disable
+#define DAC_CR_TEN1_Pos             (2)
+#define DAC_CR_TEN1                 (0x01U << DAC_CR_TEN1_Pos)              ///< DAC channel1 Trigger enable
+#define DAC_CR_TSEL1_Pos            (3)
+#define DAC_CR_TSEL1                (0x07U << DAC_CR_TSEL1_Pos)             ///< TSEL1[2:0] (DAC channel1 Trigger selection)
+#define DAC_CR_TSEL1_TIM1_TRIG      (0x00U << DAC_CR_TSEL1_Pos)             ///< TIM1_TRIG trigger
+#define DAC_CR_TSEL1_TIM3_TRIG      (0x01U << DAC_CR_TSEL1_Pos)             ///< TIM3_TRIG trigger
+#define DAC_CR_TSEL1_TIM2_TRIG      (0x04U << DAC_CR_TSEL1_Pos)             ///< TIM2_TRIG trigger
+#define DAC_CR_TSEL1_TIM4_TRIG      (0x05U << DAC_CR_TSEL1_Pos)             ///< TIM4_TRIG trigger
+#define DAC_CR_TSEL1_EXTI9          (0x06U << DAC_CR_TSEL1_Pos)             ///< External interrupt line 9 trigger
+#define DAC_CR_TSEL1_SOFTWARE       (0x07U << DAC_CR_TSEL1_Pos)             ///< Software trigger
+#define DAC_CR_WAVE1_Pos            (6)
+#define DAC_CR_WAVE1                (0x03U << DAC_CR_WAVE1_Pos)             ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
+#define DAC_CR_WAVE1_NONE           (0x00U << DAC_CR_WAVE1_Pos)             ///< Turn off waveform generation
+#define DAC_CR_WAVE1_NOISE          (0x01U << DAC_CR_WAVE1_Pos)             ///< Noise waveform generation
+#define DAC_CR_WAVE1_TRIANGLE       (0x02U << DAC_CR_WAVE1_Pos)             ///< Triangle wave generation
+#define DAC_CR_MAMP1_Pos            (8)
+#define DAC_CR_MAMP1                (0x0FU << DAC_CR_MAMP1_Pos)             ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
+#define DAC_CR_MAMP1_1              (0x00U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 1
+#define DAC_CR_MAMP1_3              (0x01U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 3
+#define DAC_CR_MAMP1_7              (0x02U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 7
+#define DAC_CR_MAMP1_15             (0x03U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 15
+#define DAC_CR_MAMP1_31             (0x04U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 31
+#define DAC_CR_MAMP1_63             (0x05U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 63
+#define DAC_CR_MAMP1_127            (0x06U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 127
+#define DAC_CR_MAMP1_255            (0x07U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 255
+#define DAC_CR_MAMP1_511            (0x08U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 511
+#define DAC_CR_MAMP1_1023           (0x09U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 1023
+#define DAC_CR_MAMP1_2047           (0x0AU << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 2047
+#define DAC_CR_MAMP1_4095           (0x0BU << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 4095
+#define DAC_CR_DMAEN1_Pos           (12)
+#define DAC_CR_DMAEN1               (0x01U << DAC_CR_DMAEN1_Pos)            ///< DAC channel1 DMA enable
+#define DAC_CR_EN2_Pos              (16)
+#define DAC_CR_EN2                  (0x01U << DAC_CR_EN2_Pos)               ///< DAC channel2 enable
+#define DAC_CR_BOFF2_Pos            (17)
+#define DAC_CR_BOFF2                (0x01U << DAC_CR_BOFF2_Pos)             ///< DAC channel2 output buffer disable
+#define DAC_CR_TEN2_Pos             (18)
+#define DAC_CR_TEN2                 (0x01U << DAC_CR_TEN2_Pos)              ///< DAC channel2 Trigger enable
+#define DAC_CR_TSEL2_Pos            (19)
+#define DAC_CR_TSEL2                (0x07U << DAC_CR_TSEL2_Pos)             ///< TSEL1[2:0] (DAC channel1 Trigger selection)
+#define DAC_CR_TSEL2_TIM1_TRIG      (0x00U << DAC_CR_TSEL2_Pos)             ///< TIM1_TRIG trigger
+#define DAC_CR_TSEL2_TIM3_TRIG      (0x01U << DAC_CR_TSEL2_Pos)             ///< TIM3_TRIG trigger
+#define DAC_CR_TSEL2_TIM2_TRIG      (0x04U << DAC_CR_TSEL2_Pos)             ///< TIM2_TRIG trigger
+#define DAC_CR_TSEL2_TIM4_TRIG      (0x05U << DAC_CR_TSEL2_Pos)             ///< TIM4_TRIG trigger
+#define DAC_CR_TSEL2_EXTI9          (0x06U << DAC_CR_TSEL2_Pos)             ///< External interrupt line 9 trigger
+#define DAC_CR_TSEL2_SOFTWARE       (0x07U << DAC_CR_TSEL2_Pos)             ///< Software trigger
+#define DAC_CR_WAVE2_Pos            (22)
+#define DAC_CR_WAVE2                (0x03U << DAC_CR_WAVE2_Pos)             ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
+#define DAC_CR_WAVE2_NONE           (0x00U << DAC_CR_WAVE2_Pos)             ///< Turn off waveform generation
+#define DAC_CR_WAVE2_NOISE          (0x01U << DAC_CR_WAVE2_Pos)             ///< Noise waveform generation
+#define DAC_CR_WAVE2_TRIANGLE       (0x02U << DAC_CR_WAVE2_Pos)             ///< Triangle wave generation
+#define DAC_CR_MAMP2_Pos            (24)
+#define DAC_CR_MAMP2                (0x0FU << DAC_CR_MAMP2_Pos)             ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
+#define DAC_CR_MAMP2_1              (0x00U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 1
+#define DAC_CR_MAMP2_3              (0x01U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 3
+#define DAC_CR_MAMP2_7              (0x02U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 7
+#define DAC_CR_MAMP2_15             (0x03U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 15
+#define DAC_CR_MAMP2_31             (0x04U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 31
+#define DAC_CR_MAMP2_63             (0x05U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 63
+#define DAC_CR_MAMP2_127            (0x06U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 127
+#define DAC_CR_MAMP2_255            (0x07U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 255
+#define DAC_CR_MAMP2_511            (0x08U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 511
+#define DAC_CR_MAMP2_1023           (0x09U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 1023
+#define DAC_CR_MAMP2_2047           (0x0AU << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 2047
+#define DAC_CR_MAMP2_4095           (0x0BU << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 4095
+#define DAC_CR_DMAEN2_Pos           (28)
+#define DAC_CR_DMAEN2               (0x01U << DAC_CR_DMAEN2_Pos)            ///< DAC channel2 DMA enabled
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_SWTRIGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0)
+#define DAC_SWTRIGR_SWTRIG1         (0x01U << DAC_SWTRIGR_SWTRIG1_Pos)      ///< DAC channel1 software trigger
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1)
+#define DAC_SWTRIGR_SWTRIG2         (0x01U << DAC_SWTRIGR_SWTRIG2_Pos)      ///< DAC channel2 software trigger
+#define DAC_SWTRIGR_DACPRE_Pos      (8)
+#define DAC_SWTRIGR_DACPRE          (0x7FU << DAC_SWTRIGR_DACPRE_Pos)       ///< DAC prescale
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12R1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12R1_DACC1DHR_Pos    (0)
+#define DAC_DHR12R1_DACC1DHR        (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)    ///< DAC channel1 12-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12L1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12L1_DACC1DHR_Pos    (4)
+#define DAC_DHR12L1_DACC1DHR        (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)    ///< DAC channel1 12-bit Left align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR8R1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR8R1_DACC1DHR_Pos     (0)
+#define DAC_DHR8R1_DACC1DHR         (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)      ///< DAC channel1 8-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12R2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12R2_DACC2DHR_Pos    (0)
+#define DAC_DHR12R2_DACC2DHR        (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)    ///< DAC channel2 12-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12L2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12L2_DACC2DHR_Pos    (4)
+#define DAC_DHR12L2_DACC2DHR        (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)    ///< DAC channel2 12-bit Left align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR8R2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR8R2_DACC2DHR_Pos     (0)
+#define DAC_DHR8R2_DACC2DHR         (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)      ///< DAC channel2 8-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12RD Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12RD_DACC1DHR_Pos    (0)
+#define DAC_DHR12RD_DACC1DHR        (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)    ///< DAC channel1 12-bit Right align data
+#define DAC_DHR12RD_DACC2DHR_Pos    (16)
+#define DAC_DHR12RD_DACC2DHR        (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)    ///< DAC channel2 12-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR12LD Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR12LD_DACC1DHR_Pos    (4)
+#define DAC_DHR12LD_DACC1DHR        (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)    ///< DAC channel1 12-bit Right align data
+#define DAC_DHR12LD_DACC2DHR_Pos    (20)
+#define DAC_DHR12LD_DACC2DHR        (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)    ///< DAC channel2 12-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DHR8RD Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DHR8RD_DACC1DHR_Pos     (0)
+#define DAC_DHR8RD_DACC1DHR         (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)      ///< DAC channel1 8-bit Right align data
+#define DAC_DHR8RD_DACC2DHR_Pos     (8)
+#define DAC_DHR8RD_DACC2DHR         (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)      ///< DAC channel2 8-bit Right align data
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DOR1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DOR1_DACC1DOR_Pos       (0)
+#define DAC_DOR1_DACC1DOR           (0xFFFU << DAC_DOR1_DACC1DOR_Pos)       ///< DAC channel1 data output
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DAC_DOR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DAC_DOR2_DACC2DOR_Pos       (0)
+#define DAC_DOR2_DACC2DOR           (0xFFFU << DAC_DOR2_DACC2DOR_Pos)       ///< DAC channel2 data output #endif
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h
new file mode 100644
index 000000000..5e378753e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h
@@ -0,0 +1,113 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_dbg.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_DBG_H
+#define __REG_DBG_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DBG Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define DBG_BASE                        (0x40007080UL)                         ///< Base Address: 0x40007080
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DEBUG Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 IDCODE;                                                            ///< Code ID                                        offset: 0x00
+    __IO u32 CR;                                                                ///< Control Register                               offset: 0x04
+} DBGMCU_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DBGMCU type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DBGMCU                          ((DBGMCU_TypeDef*) DBG_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DBGMCU_IDCODE Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DBGMCU_IDCODE_DEV_ID_Pos        (0)
+#define DBGMCU_IDCODE_DEV_ID            (0xFFFFFFFFU << DBGMCU_IDCODE_DEV_ID_Pos)   ///< Device identifier
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DBGMCU_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DBGMCU_CR_SLEEP_Pos             (0)
+#define DBGMCU_CR_SLEEP                 (0x01U << DBGMCU_CR_SLEEP_Pos)          ///< Debug Sleep mode
+#define DBGMCU_CR_STOP_Pos              (1)
+#define DBGMCU_CR_STOP                  (0x01U << DBGMCU_CR_STOP_Pos)           ///< Debug Stop mode
+#define DBGMCU_CR_STANDBY_Pos           (2)
+#define DBGMCU_CR_STANDBY               (0x01U << DBGMCU_CR_STANDBY_Pos)        ///< Debug Standby mode
+#define DBGMCU_CR_TRACE_IOEN_Pos        (5)
+#define DBGMCU_CR_TRACE_IOEN            (0x01U << DBGMCU_CR_TRACE_IOEN_Pos)     ///< Trace pin assignment
+#define DBGMCU_CR_TRACE_MODE_Pos        (6)
+#define DBGMCU_CR_TRACE_MODE_Msk        (0x03U << DBGMCU_CR_TRACE_MODE_Pos)     ///< TRACE_MODE[1:0] bits (Trace Pin Assignment Control)
+#define DBGMCU_CR_TRACE_MODE_0          (0x01U << DBGMCU_CR_TRACE_MODE_Pos)     ///< Bit 0
+#define DBGMCU_CR_TRACE_MODE_1          (0x02U << DBGMCU_CR_TRACE_MODE_Pos)     ///< Bit 1
+#define DBGMCU_CR_TRACE_MODE_ASYNC      (0x00U << DBGMCU_CR_TRACE_MODE_Pos)     ///< Tracking pin uses asynchronous mode
+#define DBGMCU_CR_TRACE_MODE_SYNC1      (0x01U << DBGMCU_CR_TRACE_MODE_Pos)     ///< The trace pin uses synchronous mode, and the data length is 1
+#define DBGMCU_CR_TRACE_MODE_SYNC2      (0x02U << DBGMCU_CR_TRACE_MODE_Pos)     ///< The trace pin uses synchronous mode, and the data length is 2
+
+#define DBGMCU_CR_IWDG_STOP_Pos         (8)
+#define DBGMCU_CR_IWDG_STOP             (0x01U << DBGMCU_CR_IWDG_STOP_Pos)      ///< Debug independent watchdog stopped when core is halted
+#define DBGMCU_CR_WWDG_STOP_Pos         (9)
+#define DBGMCU_CR_WWDG_STOP             (0x01U << DBGMCU_CR_WWDG_STOP_Pos)      ///< Debug window watchdog stopped when core is halted
+#define DBGMCU_CR_TIM_STOP_Pos          (10)
+#define DBGMCU_CR_TIM1_STOP             (0x01U << DBGMCU_CR_TIM_STOP_Pos)       ///< TIM1 counter stopped when core is halted
+#define DBGMCU_CR_TIM2_STOP             (0x02U << DBGMCU_CR_TIM_STOP_Pos)       ///< TIM2 counter stopped when core is halted
+#define DBGMCU_CR_TIM3_STOP             (0x04U << DBGMCU_CR_TIM_STOP_Pos)       ///< TIM3 counter stopped when core is halted
+#define DBGMCU_CR_TIM4_STOP             (0x08U << DBGMCU_CR_TIM_STOP_Pos)       ///< TIM4 counter stopped when core is halted
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h
new file mode 100644
index 000000000..ffcba5654
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h
@@ -0,0 +1,325 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_dma.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_DMA_H
+#define __REG_DMA_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA1_BASE                       (AHBPERIPH_BASE + 0x0000)               ///< Base Address: 0x40020000
+#define DMA1_Channel1_BASE              (AHBPERIPH_BASE + 0x0008)               ///< Base Address: 0x40020008
+#define DMA1_Channel2_BASE              (AHBPERIPH_BASE + 0x001C)               ///< Base Address: 0x4002001C
+#define DMA1_Channel3_BASE              (AHBPERIPH_BASE + 0x0030)               ///< Base Address: 0x40020030
+#define DMA1_Channel4_BASE              (AHBPERIPH_BASE + 0x0044)               ///< Base Address: 0x40020044
+#define DMA1_Channel5_BASE              (AHBPERIPH_BASE + 0x0058)               ///< Base Address: 0x40020058
+
+#define DMA1_Channel6_BASE              (AHBPERIPH_BASE + 0x006C)               ///< Base Address: 0x4002006C
+#define DMA1_Channel7_BASE              (AHBPERIPH_BASE + 0x0080)               ///< Base Address: 0x40020080
+#define DMA2_BASE                       (AHBPERIPH_BASE + 0x0400)               ///< Base Address: 0x40020400
+#define DMA2_Channel1_BASE              (AHBPERIPH_BASE + 0x0408)               ///< Base Address: 0x40020408
+#define DMA2_Channel2_BASE              (AHBPERIPH_BASE + 0x041C)               ///< Base Address: 0x4002041C
+#define DMA2_Channel3_BASE              (AHBPERIPH_BASE + 0x0430)               ///< Base Address: 0x40020430
+#define DMA2_Channel4_BASE              (AHBPERIPH_BASE + 0x0444)               ///< Base Address: 0x40020444
+#define DMA2_Channel5_BASE              (AHBPERIPH_BASE + 0x0458)               ///< Base Address: 0x40020458
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 CCR;                                                               ///< DMA channel x configuration register           offset: 0x00
+    __IO u32 CNDTR;                                                             ///< DMA channel x number of data register          offset: 0x04
+    __IO u32 CPAR;                                                              ///< DMA channel x peripheral address register      offset: 0x08
+    __IO u32 CMAR;                                                              ///< DMA channel x memory address register          offset: 0x0C
+} DMA_Channel_TypeDef;
+
+typedef struct {
+    __IO u32 ISR;                                                               ///< Interrupt Status Register                      offset: 0x00
+    __IO u32 IFCR;                                                              ///< Interrupt Flag Clear Register                  offset: 0x04
+    __IO u32 CCRx;                                                              ///< Channel X configures registers                 offset: 0x08
+    __IO u32 CNDTRx;                                                            ///< Channel X transfer quantity register           offset: 0x0C
+    __IO u32 CPARx;                                                             ///< Channel X peripheral address register          offset: 0x10
+    __IO u32 CMARx;                                                             ///< Channel X memory address register              offset: 0x14
+} DMA_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA1                            ((DMA_TypeDef*) DMA1_BASE)
+#define DMA1_ch1                        ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE)
+#define DMA1_ch2                        ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE)
+#define DMA1_ch3                        ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE)
+#define DMA1_ch4                        ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE)
+#define DMA1_ch5                        ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE)
+
+#define DMA1_Channel1                   ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE)
+#define DMA1_Channel2                   ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE)
+#define DMA1_Channel3                   ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE)
+#define DMA1_Channel4                   ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE)
+#define DMA1_Channel5                   ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE)
+
+
+#define DMA1_ch6                        ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE)
+#define DMA1_ch7                        ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE)
+
+#define DMA1_Channel6                   ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE)
+#define DMA1_Channel7                   ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE)
+
+#define DMA2                            ((DMA_TypeDef*) DMA2_BASE)
+#define DMA2_ch1                        ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE)
+#define DMA2_ch2                        ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE)
+#define DMA2_ch3                        ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE)
+#define DMA2_ch4                        ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE)
+#define DMA2_ch5                        ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE)
+#define DMA2_Channel1                   ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE)
+#define DMA2_Channel2                   ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE)
+#define DMA2_Channel3                   ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE)
+#define DMA2_Channel4                   ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE)
+#define DMA2_Channel5                   ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_ISR_GIF1_Pos                (0)
+#define DMA_ISR_GIF1                    (0x01U << DMA_ISR_GIF1_Pos)             ///< Channel 1 Global interrupt flag
+#define DMA_ISR_TCIF1_Pos               (1)
+#define DMA_ISR_TCIF1                   (0x01U << DMA_ISR_TCIF1_Pos)            ///< Channel 1 Transfer Complete flag
+#define DMA_ISR_HTIF1_Pos               (2)
+#define DMA_ISR_HTIF1                   (0x01U << DMA_ISR_HTIF1_Pos)            ///< Channel 1 Half Transfer flag
+#define DMA_ISR_TEIF1_Pos               (3)
+#define DMA_ISR_TEIF1                   (0x01U << DMA_ISR_TEIF1_Pos)            ///< Channel 1 Transfer Error flag
+#define DMA_ISR_GIF2_Pos                (4)
+#define DMA_ISR_GIF2                    (0x01U << DMA_ISR_GIF2_Pos)             ///< Channel 2 Global interrupt flag
+#define DMA_ISR_TCIF2_Pos               (5)
+#define DMA_ISR_TCIF2                   (0x01U << DMA_ISR_TCIF2_Pos)            ///< Channel 2 Transfer Complete flag
+#define DMA_ISR_HTIF2_Pos               (6)
+#define DMA_ISR_HTIF2                   (0x01U << DMA_ISR_HTIF2_Pos)            ///< Channel 2 Half Transfer flag
+#define DMA_ISR_TEIF2_Pos               (7)
+#define DMA_ISR_TEIF2                   (0x01U << DMA_ISR_TEIF2_Pos)            ///< Channel 2 Transfer Error flag
+#define DMA_ISR_GIF3_Pos                (8)
+#define DMA_ISR_GIF3                    (0x01U << DMA_ISR_GIF3_Pos)             ///< Channel 3 Global interrupt flag
+#define DMA_ISR_TCIF3_Pos               (9)
+#define DMA_ISR_TCIF3                   (0x01U << DMA_ISR_TCIF3_Pos)            ///< Channel 3 Transfer Complete flag
+#define DMA_ISR_HTIF3_Pos               (10)
+#define DMA_ISR_HTIF3                   (0x01U << DMA_ISR_HTIF3_Pos)            ///< Channel 3 Half Transfer flag
+#define DMA_ISR_TEIF3_Pos               (11)
+#define DMA_ISR_TEIF3                   (0x01U << DMA_ISR_TEIF3_Pos)            ///< Channel 3 Transfer Error flag
+#define DMA_ISR_GIF4_Pos                (12)
+#define DMA_ISR_GIF4                    (0x01U << DMA_ISR_GIF4_Pos)             ///< Channel 4 Global interrupt flag
+#define DMA_ISR_TCIF4_Pos               (13)
+#define DMA_ISR_TCIF4                   (0x01U << DMA_ISR_TCIF4_Pos)            ///< Channel 4 Transfer Complete flag
+#define DMA_ISR_HTIF4_Pos               (14)
+#define DMA_ISR_HTIF4                   (0x01U << DMA_ISR_HTIF4_Pos)            ///< Channel 4 Half Transfer flag
+#define DMA_ISR_TEIF4_Pos               (15)
+#define DMA_ISR_TEIF4                   (0x01U << DMA_ISR_TEIF4_Pos)            ///< Channel 4 Transfer Error flag
+#define DMA_ISR_GIF5_Pos                (16)
+#define DMA_ISR_GIF5                    (0x01U << DMA_ISR_GIF5_Pos)             ///< Channel 5 Global interrupt flag
+#define DMA_ISR_TCIF5_Pos               (17)
+#define DMA_ISR_TCIF5                   (0x01U << DMA_ISR_TCIF5_Pos)            ///< Channel 5 Transfer Complete flag
+#define DMA_ISR_HTIF5_Pos               (18)
+#define DMA_ISR_HTIF5                   (0x01U << DMA_ISR_HTIF5_Pos)            ///< Channel 5 Half Transfer flag
+#define DMA_ISR_TEIF5_Pos               (19)
+#define DMA_ISR_TEIF5                   (0x01U << DMA_ISR_TEIF5_Pos)            ///< Channel 5 Transfer Error flag
+
+#define DMA_ISR_GIF6_Pos                (20)
+#define DMA_ISR_GIF6                    (0x01U << DMA_ISR_GIF6_Pos)             ///< Channel 6 Global interrupt flag
+#define DMA_ISR_TCIF6_Pos               (21)
+#define DMA_ISR_TCIF6                   (0x01U << DMA_ISR_TCIF6_Pos)            ///< Channel 6 Transfer Complete flag
+#define DMA_ISR_HTIF6_Pos               (22)
+#define DMA_ISR_HTIF6                   (0x01U << DMA_ISR_HTIF6_Pos)            ///< Channel 6 Half Transfer flag
+#define DMA_ISR_TEIF6_Pos               (23)
+#define DMA_ISR_TEIF6                   (0x01U << DMA_ISR_TEIF6_Pos)            ///< Channel 6 Transfer Error flag
+#define DMA_ISR_GIF7_Pos                (24)
+#define DMA_ISR_GIF7                    (0x01U << DMA_ISR_GIF7_Pos)             ///< Channel 7 Global interrupt flag
+#define DMA_ISR_TCIF7_Pos               (25)
+#define DMA_ISR_TCIF7                   (0x01U << DMA_ISR_TCIF7_Pos)            ///< Channel 7 Transfer Complete flag
+#define DMA_ISR_HTIF7_Pos               (26)
+#define DMA_ISR_HTIF7                   (0x01U << DMA_ISR_HTIF7_Pos)            ///< Channel 7 Half Transfer flag
+#define DMA_ISR_TEIF7_Pos               (27)
+#define DMA_ISR_TEIF7                   (0x01U << DMA_ISR_TEIF7_Pos)            ///< Channel 7 Transfer Error flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_IFCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_IFCR_CGIF1_Pos              (0)
+#define DMA_IFCR_CGIF1                  (0x01U << DMA_IFCR_CGIF1_Pos)           ///< Channel 1 Global interrupt clearr
+#define DMA_IFCR_CTCIF1_Pos             (1)
+#define DMA_IFCR_CTCIF1                 (0x01U << DMA_IFCR_CTCIF1_Pos)          ///< Channel 1 Transfer Complete clear
+#define DMA_IFCR_CHTIF1_Pos             (2)
+#define DMA_IFCR_CHTIF1                 (0x01U << DMA_IFCR_CHTIF1_Pos)          ///< Channel 1 Half Transfer clear
+#define DMA_IFCR_CTEIF1_Pos             (3)
+#define DMA_IFCR_CTEIF1                 (0x01U << DMA_IFCR_CTEIF1_Pos)          ///< Channel 1 Transfer Error clear
+#define DMA_IFCR_CGIF2_Pos              (4)
+#define DMA_IFCR_CGIF2                  (0x01U << DMA_IFCR_CGIF2_Pos)           ///< Channel 2 Global interrupt clear
+#define DMA_IFCR_CTCIF2_Pos             (5)
+#define DMA_IFCR_CTCIF2                 (0x01U << DMA_IFCR_CTCIF2_Pos)          ///< Channel 2 Transfer Complete clear
+#define DMA_IFCR_CHTIF2_Pos             (6)
+#define DMA_IFCR_CHTIF2                 (0x01U << DMA_IFCR_CHTIF2_Pos)          ///< Channel 2 Half Transfer clear
+#define DMA_IFCR_CTEIF2_Pos             (7)
+#define DMA_IFCR_CTEIF2                 (0x01U << DMA_IFCR_CTEIF2_Pos)          ///< Channel 2 Transfer Error clear
+#define DMA_IFCR_CGIF3_Pos              (8)
+#define DMA_IFCR_CGIF3                  (0x01U << DMA_IFCR_CGIF3_Pos)           ///< Channel 3 Global interrupt clear
+#define DMA_IFCR_CTCIF3_Pos             (9)
+#define DMA_IFCR_CTCIF3                 (0x01U << DMA_IFCR_CTCIF3_Pos)          ///< Channel 3 Transfer Complete clear
+#define DMA_IFCR_CHTIF3_Pos             (10)
+#define DMA_IFCR_CHTIF3                 (0x01U << DMA_IFCR_CHTIF3_Pos)          ///< Channel 3 Half Transfer clear
+#define DMA_IFCR_CTEIF3_Pos             (11)
+#define DMA_IFCR_CTEIF3                 (0x01U << DMA_IFCR_CTEIF3_Pos)          ///< Channel 3 Transfer Error clear
+#define DMA_IFCR_CGIF4_Pos              (12)
+#define DMA_IFCR_CGIF4                  (0x01U << DMA_IFCR_CGIF4_Pos)           ///< Channel 4 Global interrupt clear
+#define DMA_IFCR_CTCIF4_Pos             (13)
+#define DMA_IFCR_CTCIF4                 (0x01U << DMA_IFCR_CTCIF4_Pos)          ///< Channel 4 Transfer Complete clear
+#define DMA_IFCR_CHTIF4_Pos             (14)
+#define DMA_IFCR_CHTIF4                 (0x01U << DMA_IFCR_CHTIF4_Pos)          ///< Channel 4 Half Transfer clear
+#define DMA_IFCR_CTEIF4_Pos             (15)
+#define DMA_IFCR_CTEIF4                 (0x01U << DMA_IFCR_CTEIF4_Pos)          ///< Channel 4 Transfer Error clear
+#define DMA_IFCR_CGIF5_Pos              (16)
+#define DMA_IFCR_CGIF5                  (0x01U << DMA_IFCR_CGIF5_Pos)           ///< Channel 5 Global interrupt clear
+#define DMA_IFCR_CTCIF5_Pos             (17)
+#define DMA_IFCR_CTCIF5                 (0x01U << DMA_IFCR_CTCIF5_Pos)          ///< Channel 5 Transfer Complete clear
+#define DMA_IFCR_CHTIF5_Pos             (18)
+#define DMA_IFCR_CHTIF5                 (0x01U << DMA_IFCR_CHTIF5_Pos)          ///< Channel 5 Half Transfer clear
+#define DMA_IFCR_CTEIF5_Pos             (19)
+#define DMA_IFCR_CTEIF5                 (0x01U << DMA_IFCR_CTEIF5_Pos)          ///< Channel 5 Transfer Error clear
+
+#define DMA_IFCR_CGIF6_Pos              (20)
+#define DMA_IFCR_CGIF6                  (0x01U << DMA_IFCR_CGIF6_Pos)           ///< Channel 6 Global interrupt clear
+#define DMA_IFCR_CTCIF6_Pos             (21)
+#define DMA_IFCR_CTCIF6                 (0x01U << DMA_IFCR_CTCIF6_Pos)          ///< Channel 6 Transfer Complete clear
+#define DMA_IFCR_CHTIF6_Pos             (22)
+#define DMA_IFCR_CHTIF6                 (0x01U << DMA_IFCR_CHTIF6_Pos)          ///< Channel 6 Half Transfer clear
+#define DMA_IFCR_CTEIF6_Pos             (23)
+#define DMA_IFCR_CTEIF6                 (0x01U << DMA_IFCR_CTEIF6_Pos)          ///< Channel 6 Transfer Error clear
+#define DMA_IFCR_CGIF7_Pos              (24)
+#define DMA_IFCR_CGIF7                  (0x01U << DMA_IFCR_CGIF7_Pos)           ///< Channel 7 Global interrupt clear
+#define DMA_IFCR_CTCIF7_Pos             (25)
+#define DMA_IFCR_CTCIF7                 (0x01U << DMA_IFCR_CTCIF7_Pos)          ///< Channel 7 Transfer Complete clear
+#define DMA_IFCR_CHTIF7_Pos             (26)
+#define DMA_IFCR_CHTIF7                 (0x01U << DMA_IFCR_CHTIF7_Pos)          ///< Channel 7 Half Transfer clear
+#define DMA_IFCR_CTEIF7_Pos             (27)
+#define DMA_IFCR_CTEIF7                 (0x01U << DMA_IFCR_CTEIF7_Pos)          ///< Channel 7 Transfer Error clear
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_CCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_CCR_EN_Pos                  (0)
+#define DMA_CCR_EN                      (0x01U << DMA_CCR_EN_Pos)               ///< Channel enabl
+#define DMA_CCR_TCIE_Pos                (1)
+#define DMA_CCR_TCIE                    (0x01U << DMA_CCR_TCIE_Pos)             ///< Transfer complete interrupt enable
+#define DMA_CCR_HTIE_Pos                (2)
+#define DMA_CCR_HTIE                    (0x01U << DMA_CCR_HTIE_Pos)             ///< Half Transfer interrupt enable
+#define DMA_CCR_TEIE_Pos                (3)
+#define DMA_CCR_TEIE                    (0x01U << DMA_CCR_TEIE_Pos)             ///< Transfer error interrupt enable
+#define DMA_CCR_DIR_Pos                 (4)
+#define DMA_CCR_DIR                     (0x01U << DMA_CCR_DIR_Pos)              ///< Data transfer direction
+#define DMA_CCR_CIRC_Pos                (5)
+#define DMA_CCR_CIRC                    (0x01U << DMA_CCR_CIRC_Pos)             ///< Circular mode
+#define DMA_CCR_PINC_Pos                (6)
+#define DMA_CCR_PINC                    (0x01U << DMA_CCR_PINC_Pos)             ///< Peripheral increment mode
+#define DMA_CCR_MINC_Pos                (7)
+#define DMA_CCR_MINC                    (0x01U << DMA_CCR_MINC_Pos)             ///< Memory increment mode
+
+#define DMA_CCR_PSIZE_Pos               (8)
+#define DMA_CCR_PSIZE                   (0x03U << DMA_CCR_PSIZE_Pos)            ///< PSIZE[1:0] bits (Peripheral size)
+#define DMA_CCR_PSIZE_0                 (0x01U << DMA_CCR_PSIZE_Pos)            ///< Bit0
+#define DMA_CCR_PSIZE_1                 (0x02U << DMA_CCR_PSIZE_Pos)            ///< Bit1
+
+#define DMA_CCR_PSIZE_BYTE              (0x00U << DMA_CCR_PSIZE_Pos)            ///< DMA Peripheral Data Size Byte
+#define DMA_CCR_PSIZE_HALFWORD          (0x01U << DMA_CCR_PSIZE_Pos)            ///< DMA Peripheral Data Size HalfWord
+#define DMA_CCR_PSIZE_WORD              (0x02U << DMA_CCR_PSIZE_Pos)            ///< DMA Peripheral Data Size Word
+
+#define DMA_CCR_MSIZE_Pos               (10)
+#define DMA_CCR_MSIZE                   (0x03U << DMA_CCR_MSIZE_Pos)            ///< MSIZE[1:0] bits (Memory size)
+#define DMA_CCR_MSIZE_0                 (0x01U << DMA_CCR_MSIZE_Pos)            ///< Bit0
+#define DMA_CCR_MSIZE_1                 (0x02U << DMA_CCR_MSIZE_Pos)            ///< Bit1
+
+#define DMA_CCR_MSIZE_BYTE              (0x00U << DMA_CCR_MSIZE_Pos)            ///< DMA Memory Data Size Byte
+#define DMA_CCR_MSIZE_HALFWORD          (0x01U << DMA_CCR_MSIZE_Pos)            ///< DMA Memory Data Size HalfWord
+#define DMA_CCR_MSIZE_WORD              (0x02U << DMA_CCR_MSIZE_Pos)            ///< DMA Memory Data Size Word
+
+#define DMA_CCR_PL_Pos                  (12)
+#define DMA_CCR_PL                      (0x03U << DMA_CCR_PL_Pos)               ///< PL[1:0] bits(Channel Priority level)
+#define DMA_CCR_PL_0                    (0x01U << DMA_CCR_PL_Pos)               ///< Bit0
+#define DMA_CCR_PL_1                    (0x02U << DMA_CCR_PL_Pos)               ///< Bit1
+
+#define DMA_CCR_PL_Low                  (0x00U << DMA_CCR_PL_Pos)               ///< DMA Priority Low
+#define DMA_CCR_PL_Medium               (0x01U << DMA_CCR_PL_Pos)               ///< DMA Priority Medium
+#define DMA_CCR_PL_High                 (0x02U << DMA_CCR_PL_Pos)               ///< DMA Priority High
+#define DMA_CCR_PL_VeryHigh             (0x03U << DMA_CCR_PL_Pos)               ///< DMA Priority VeryHigh
+#define DMA_CCR_M2M_Pos                 (14)
+#define DMA_CCR_M2M                     (0x01U << DMA_CCR_M2M_Pos)              ///< Memory to memory mode
+
+#define DMA_CCR_ARE_Pos                 (15)
+#define DMA_CCR_ARE                     (0x01U << DMA_CCR_ARE_Pos)              ///< Auto-Reload Enable bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_CNDTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_CNDTR_NDT_Pos               (0)
+#define DMA_CNDTR_NDT                   (0xFFFFU << DMA_CNDTR_NDT_Pos)          ///< Number of data to Transfer
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_CPAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_CPAR_PA_Pos                 (0)
+#define DMA_CPAR_PA                     (0xFFFFFFFFU << DMA_CPAR_PA_Pos)        ///< Peripheral Address
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief DMA_CMAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define DMA_CMAR_MA_Pos                 (0)
+#define DMA_CMAR_MA                     (0xFFFFFFFFU << DMA_CMAR_MA_Pos)        ///< Peripheral Address
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h
new file mode 100644
index 000000000..61a0d25c2
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h
@@ -0,0 +1,730 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_iwdg.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_ETH_H
+#define __REG_ETH_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+#include "reg_common.h"
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_BASE                       (AHBPERIPH_BASE + 0x8000)              ///< Base Address: 0x40028000
+
+
+#define ETH                             ((ETH_TypeDef*) ETH_BASE)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 MACCR;                                                        ///< configuration register                         offset 0x0000
+    __IO u32 MACFFR;                                                       ///< frame filter register                          offset 0x0004
+    __IO u32 MACHTHR;                                                      ///< Hash list high register                        offset 0x0008
+    __IO u32 MACHTLR;                                                      ///< Hash list low register                         offset 0x000C
+    __IO u32 MACMIIAR;                                                     ///< MII address register                           offset 0x0010
+    __IO u32 MACMIIDR;                                                     ///< MII data register                              offset 0x0014
+    __IO u32 MACFCR;                                                       ///< flow control register                          offset 0x0018
+    __IO u32 MACVLANTR;                                                    ///< VLAN label register                            offset 0x001C
+    __IO u32 RESERVEDX0020[2];                                             /// 0x0020 ~ 0x0024
+    __IO u32 MACRWUFFR;                                                    /// 0x0028
+    __IO u32 MACPMTCSR;                                                    /// 0x002C
+    __IO u32 RESERVEDX0030[4];                                             /// 0x0030 ~ 0x003C
+    __IO u32 MACA0HR;                                                      ///< address 0 high register                        offset 0x0040
+    __IO u32 MACA0LR;                                                      ///< address 0 low register                         offset 0x0044
+    __IO u32 MACA1HR;                                                      ///< address 1 high register                        offset 0x0048
+    __IO u32 MACA1LR;                                                      ///< address 1 low register                         offset 0x004C
+    __IO u32 MACA2HR;                                                      ///< address 2 high register                        offset 0x0050
+    __IO u32 MACA2LR;                                                      ///< address 2 low register                         offset 0x0054
+    __IO u32 MACA3HR;                                                      ///< address 3 high register                        offset 0x0058
+    __IO u32 MACA3LR;                                                      ///< address 3 low register                         offset 0x005C
+    __IO u32 MACA4HR;                                                      ///< address 4 high register                        offset 0x0060
+    __IO u32 MACA4LR;                                                      ///< address 4 low register                         offset 0x0064
+    __IO u32 MACA5HR;                                                      ///< address 5 high register                        offset 0x0068
+    __IO u32 MACA5LR;                                                      ///< address 5 low register                         offset 0x006C
+    __IO u32 MACA6HR;                                                      ///< address 6 high register                        offset 0x0070
+    __IO u32 MACA6LR;                                                      ///< address 6 low register                         offset 0x0074
+    __IO u32 MACA7HR;                                                      ///< address 7 high register                        offset 0x0078
+    __IO u32 MACA7LR;                                                      ///< address 7 low register                         offset 0x007C
+    __IO u32 MACA8HR;                                                      ///< address 8 high register                        offset 0x0080
+    __IO u32 MACA8LR;                                                      ///< address 8 low register                         offset 0x0084
+    __IO u32 MACA9HR;                                                      ///< address 9 high register                        offset 0x0088
+    __IO u32 MACA9LR;                                                      ///< address 9 low register                         offset 0x008C
+    __IO u32 MACA10HR;                                                     ///< address 10 high register                        offset 0x0090
+    __IO u32 MACA10LR;                                                     ///< address 10 low register                         offset 0x0094
+    __IO u32 MACA11HR;                                                     ///< address 11 high register                        offset 0x0098
+    __IO u32 MACA11LR;                                                     ///< address 11 low register                         offset 0x009C
+    __IO u32 MACA12HR;                                                     ///< address 12 high register                        offset 0x00A0
+    __IO u32 MACA12LR;                                                     ///< address 12 low register                         offset 0x00A4
+    __IO u32 MACA13HR;                                                     ///< address 13 high register                        offset 0x00A8
+    __IO u32 MACA13LR;                                                     ///< address 13 low register                         offset 0x00AC
+    __IO u32 MACA14HR;                                                     ///< address 14 high register                        offset 0x00B0
+    __IO u32 MACA14LR;                                                     ///< address 14 low register                         offset 0x00B4
+    __IO u32 MACA15HR;                                                     ///< address 15 high register                        offset 0x00B8
+    __IO u32 MACA15LR;                                                     ///< address 15 low register                         offset 0x00BC
+    __IO u32 MACANCR;                                                      ///< Automatic negotiation control register           offset 0x00C0
+    __IO u32 MACANSR;                                                      ///< Automatic negotiation of the status register     offset 0x00C4
+    __IO u32 MACANAR;                                                      ///< Automatic negotiation of broadcast registers     offset 0x00C8
+    __IO u32 MACANLPAR;                                                    ///< Automatic negotiation of link partner capability register  offset 0x00CC
+    __IO u32 MACANER;                                                      ///< Automatic negotiation of extension registers     offset 0x00D0
+    __IO u32 MACTBIER;                                                     ///< Ten - place interface extension register         offset 0x00D4
+    __IO u32 MACMIISR;                                                     ///< MII status register                              offset 0x00D8
+    __IO u32 RESERVEDX00DC[9];                                             ///<                                                  offset 0x00DC ~ 0x00FC
+    __IO u32 MMCCR;                                                        ///< MMC controls registers  offset 0x0100
+    __IO u32 MMCRIR;                                                       ///< The MMC receives the interrupt register  offset 0x0104
+    __IO u32 MMCTIR;                                                       ///< The MMC sends the interrupt register  offset 0x0108
+    __IO u32 MMCRIMR;                                                      ///< The MMC receives the interrupt mask register  offset 0x010C
+    __IO u32 MMCTIMR;                                                      ///< MMC sends interrupt masking registers  offset 0x0110
+    __IO u32 RESERVEDX0114[14];                                            ///<   offset 0x0114 ~ 0x0148
+    __IO u32 MMCTGFSCCR;                                                   ///< A good frame counter register that MMC sends after a single conflict  offset 0x014C
+    __IO u32 MMCTGFMSCCR;                                                  ///< A good frame counter register that MMC sends after multiple collisions  offset 0x0150
+    __IO u32 RESERVEDX0154[5];                                             ///<   offset 0x0154 ~ 0x0164
+    __IO u32 MMCTGFCR;                                                     ///< Good frame counter register sent by MMC  offset 0x0168
+    __IO u32 RESERVEDX016C[10];                                            ///<   offset 0x016C ~ 0x0190
+    __IO u32 MMCRFCECR;                                                    ///< Ethernet MMC with CRC error counter register receives frame register  offset 0x0194
+    __IO u32 MMCRFAECR;                                                    ///< Ethernet MMC receives frames with alignment error counter registers  offset 0x0198
+    __IO u32 RESERVEDX019C[10];                                            ///<   offset 0x019C ~ 0x01C0
+    __IO u32 MMCRGUFCR;                                                    ///< Good unicast frame counter register received by MMC  offset 0x01C4
+    __IO u32 RESERVEDx01C8[910];                                           ///<   offset 0x01C8 ~ 0x0FFC
+    __IO u32 DMABMR;                                                       ///< Bus mode register                               offset 0x1000
+    __IO u32 DMATPDR;                                                      ///< DMA sends the polling request register          offset 0x1004
+    __IO u32 DMARPDR;                                                      ///< DMA receives the polling request register       offset 0x1008
+    __IO u32 DMARDLAR;                                                     ///< DMA receives a list of descriptor addresses     offset 0x100C
+    __IO u32 DMATDLAR;                                                     ///< DMA sends the descriptor list address           offset 0x1010
+    __IO u32 DMASR;                                                        ///< DMA status register                             offset 0x1014
+    __IO u32 DMAOMR;                                                       ///< DMA working mode register                       offset 0x1018
+    __IO u32 DMAIER;                                                       ///< DMA interrupt enablement register               offset 0x101C
+    __IO u32 DMAMFBOCR;                                                    ///< DMA lost frames and cache overflow counter registers offset 0x1020
+    __IO u32 DMARSWTR;                                                     /// 0x1024
+    __IO u32 RESERVEDX1028[8];                                             /// 0x1028 ~ 0x1044
+    __IO u32 DMACHTDR;                                                     /// 0x1048
+    __IO u32 DMACHRDR;                                                     /// 0x104C
+    __IO u32 DMACHTBAR;                                                    ///< DMA is currently sending the cache address register  offset 0x1050
+    __IO u32 DMACHRBAR;                                                    ///< DMA currently receives the cache address register    offset 0x1054
+} ETH_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACCR_WD_Pos                (23)
+#define ETH_MACCR_WD                    (0x01U << ETH_MACCR_WD_Pos)                  ///< Watchdog disable
+#define ETH_MACCR_JD_Pos                (22)
+#define ETH_MACCR_JD                    (0x01U << ETH_MACCR_JD_Pos)                  ///< Jabber disable
+#define ETH_MACCR_FBE_Pos               (21)
+#define ETH_MACCR_FBE                   (0x01U << ETH_MACCR_FBE_Pos)                 ///< Frame Burst Enable
+#define ETH_MACCR_JE_Pos                (20)
+#define ETH_MACCR_JE                    (0x01U << ETH_MACCR_JE_Pos)                  ///< Jumbo Frame Enable
+#define ETH_MACCR_IFG_Pos               (17)                                         ///< Inter-frame gap
+#define ETH_MACCR_IFG_96Bit             (0x00U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 96Bit
+#define ETH_MACCR_IFG_88Bit             (0x01U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 88Bit
+#define ETH_MACCR_IFG_80Bit             (0x02U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 80Bit
+#define ETH_MACCR_IFG_72Bit             (0x03U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 72Bit
+#define ETH_MACCR_IFG_64Bit             (0x04U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 64Bit
+#define ETH_MACCR_IFG_56Bit             (0x05U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 56Bit
+#define ETH_MACCR_IFG_48Bit             (0x06U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 48Bit
+#define ETH_MACCR_IFG_40Bit             (0x07U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 40Bit
+#define ETH_MACCR_FES_Pos               (14)
+#define ETH_MACCR_FES                   (0x01U << ETH_MACCR_FES_Pos)                  ///< Fast ethernet speed
+#define ETH_MACCR_ROD_Pos               (13)
+#define ETH_MACCR_ROD                   (0x01U << ETH_MACCR_ROD_Pos)                  ///< Receive own disable
+#define ETH_MACCR_LM_Pos                (12)
+#define ETH_MACCR_LM                    (0x01U << ETH_MACCR_LM_Pos)                   ///< loopback mode
+#define ETH_MACCR_DM_Pos                (11)
+#define ETH_MACCR_DM                    (0x01U << ETH_MACCR_DM_Pos)                   ///< Duplex mode
+#define ETH_MACCR_IPCO_Pos              (10)
+#define ETH_MACCR_IPCO                  (0x01U << ETH_MACCR_IPCO_Pos)                 ///< IP Checksum offload
+#define ETH_MACCR_RD_Pos                (9)
+#define ETH_MACCR_RD                    (0x01U << ETH_MACCR_RD_Pos)                   ///< Retry disable
+#define ETH_MACCR_APCS_Pos              (8)
+#define ETH_MACCR_APCS                  (0x01U << ETH_MACCR_APCS_Pos)                 ///< Automatic Pad/CRC stripping
+#define ETH_MACCR_BL_Pos                (5)                                           ///< Back-off limit: random integer number (r) of slot time delays before rescheduling a transmission attempt during retries after a collision: 0 =< r <2^k
+#define ETH_MACCR_BL_10                 (0x00U << ETH_MACCR_BL_Pos)                   ///< k = min (n, 10)
+#define ETH_MACCR_BL_8                  (0x01U << ETH_MACCR_BL_Pos)                   ///< k = min (n, 8)
+#define ETH_MACCR_BL_4                  (0x02U << ETH_MACCR_BL_Pos)                   ///< k = min (n, 4)
+#define ETH_MACCR_BL_1                  (0x03U << ETH_MACCR_BL_Pos)                   ///< k = min (n, 1)
+#define ETH_MACCR_DC_Pos                (4)
+#define ETH_MACCR_DC                    (0x01U << ETH_MACCR_DC_Pos)                  ///< Defferal check
+#define ETH_MACCR_TE_Pos                (3)
+#define ETH_MACCR_TE                    (0x01U << ETH_MACCR_TE_Pos)                  ///< Transmitter enable
+#define ETH_MACCR_RE_Pos                (2)
+#define ETH_MACCR_RE                    (0x01U << ETH_MACCR_RE_Pos)                  ///< Receiver enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACFFR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACFFR_RA_Pos               (31)
+#define ETH_MACFFR_RA                   (0x01U << ETH_MACFFR_RA_Pos)                  ///< Receive all 
+
+#define ETH_MACFFR_SAF_Pos              (9)
+#define ETH_MACFFR_SAF                  (0x01U << ETH_MACFFR_SAF_Pos)                  ///< Source address filter enable 
+#define ETH_MACFFR_SAIF_Pos             (8)
+#define ETH_MACFFR_SAIF                 (0x01U << ETH_MACFFR_SAIF_Pos)                 ///< SA inverse filtering 
+#define ETH_MACFFR_PCF_Pos              (6)
+#define ETH_MACFFR_PCF                  (0x03U << ETH_MACFFR_PCF_Pos)                  ///< Pass control frames: 3 cases 
+#define ETH_MACFFR_PCF_BlockAll         (0x01U << ETH_MACFFR_PCF_Pos)                  ///< MAC filters all control frames from reaching the application 
+#define ETH_MACFFR_PCF_ForwardAll       (0x02U << ETH_MACFFR_PCF_Pos)                  ///< MAC forwards all control frames to application even if they fail the Address Filter 
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter (0x03U << ETH_MACFFR_PCF_Pos)           ///< MAC forwards control frames that pass the Address Filter. 
+#define ETH_MACFFR_BFD_Pos              (5)
+#define ETH_MACFFR_BFD                  (0x01U << ETH_MACFFR_BFD_Pos)                  ///< Broadcast frame disable 
+#define ETH_MACFFR_PAM_Pos              (4)
+#define ETH_MACFFR_PAM                  (0x01U << ETH_MACFFR_PAM_Pos)                  ///< Pass all mutlicast 
+#define ETH_MACFFR_DAIF_Pos             (3)
+#define ETH_MACFFR_DAIF                 (0x01U << ETH_MACFFR_DAIF_Pos)                 ///< DA Inverse filtering 
+#define ETH_MACFFR_HM_Pos               (2)
+#define ETH_MACFFR_HM                   (0x01U << ETH_MACFFR_HM_Pos)                  ///< Hash multicast 
+#define ETH_MACFFR_HU_Pos               (1)
+#define ETH_MACFFR_HU                   (0x01U << ETH_MACFFR_HU_Pos)                  ///< Hash unicast 
+#define ETH_MACFFR_PM_Pos               (0)
+#define ETH_MACFFR_PM                   (0x01U << ETH_MACFFR_PM_Pos)                  ///< Promiscuous mode 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACHTHR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACHTHR_HTH                 (0xFFFFFFFFU)                                 ///< Hash table high
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACHTLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACHTLR_HTL                 (0xFFFFFFFFU)                                ///< Hash table low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACMIIAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACMIIAR_PA_Pos             (11)
+#define ETH_MACMIIAR_PA                 (0x1FU << ETH_MACMIIAR_PA_Pos)              ///< Physical layer address
+#define ETH_MACMIIAR_MR_Pos             (6)
+#define ETH_MACMIIAR_MR                 (0x1FU << ETH_MACMIIAR_MR_Pos)              ///< MII register in the selected PHY
+#define ETH_MACMIIAR_CR_Pos             (2)
+#define ETH_MACMIIAR_CR                 (0x07U << ETH_MACMIIAR_CR_Pos)              ///< CR clock range: 6 cases
+#define ETH_MACMIIAR_CR_Div42           (0x00U << ETH_MACMIIAR_CR_Pos)              ///< HCLK:60-100 MHz; MDC clock= HCLK/42
+#define ETH_MACMIIAR_CR_Div62           (0x01U << ETH_MACMIIAR_CR_Pos)              ///< HCLK:100-150 MHz; MDC clock= HCLK/62
+#define ETH_MACMIIAR_CR_Div16           (0x02U << ETH_MACMIIAR_CR_Pos)              ///< HCLK:20-35 MHz; MDC clock= HCLK/16
+#define ETH_MACMIIAR_CR_Div26           (0x03U << ETH_MACMIIAR_CR_Pos)              ///< HCLK:35-60 MHz; MDC clock= HCLK/26
+#define ETH_MACMIIAR_CR_Div102          (0x04U << ETH_MACMIIAR_CR_Pos)              ///< HCLK:150-168 MHz; MDC clock= HCLK/102
+#define ETH_MACMIIAR_MW_Pos             (1)
+#define ETH_MACMIIAR_MW                 (0x01U << ETH_MACMIIAR_MW_Pos)              ///< MII write
+#define ETH_MACMIIAR_MB_Pos             (0)
+#define ETH_MACMIIAR_MB                 (0x01U << ETH_MACMIIAR_MB_Pos)              ///< MII busy
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACMIIDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACMIIDR_MD                 (0x0000FFFFU)                               ///< MII data: read/write data from/to PHY 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACFCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACFCR_PT_Pos               (16)
+#define ETH_MACFCR_PT                   ((u32)0xFFFF << ETH_MACFCR_PT_Pos) ///< Pause time
+#define ETH_MACFCR_PLT_Pos              (4)
+#define ETH_MACFCR_PLT                  (0x03U << ETH_MACFCR_PLT_Pos)                  ///< Pause low threshold: 4 cases 
+#define ETH_MACFCR_PLT_Minus4           (0x00U << ETH_MACFCR_PLT_Pos)                  ///< Pause time minus 4 slot times 
+#define ETH_MACFCR_PLT_Minus28          (0x01U << ETH_MACFCR_PLT_Pos)                  ///< Pause time minus 28 slot times 
+#define ETH_MACFCR_PLT_Minus144         (0x02U << ETH_MACFCR_PLT_Pos)                  ///< Pause time minus 144 slot times 
+#define ETH_MACFCR_PLT_Minus256         (0x03U << ETH_MACFCR_PLT_Pos)                  ///< Pause time minus 256 slot times 
+#define ETH_MACFCR_UPFD_Pos             (3)
+#define ETH_MACFCR_UPFD                 (0x01U << ETH_MACFCR_UPFD_Pos)                  ///< Unicast pause frame detect 
+#define ETH_MACFCR_RFCE_Pos             (2)
+#define ETH_MACFCR_RFCE                 (0x01U << ETH_MACFCR_RFCE_Pos)                  ///< Receive flow control enable 
+#define ETH_MACFCR_TFCE_Pos             (1)
+#define ETH_MACFCR_TFCE                 (0x01U << ETH_MACFCR_TFCE_Pos)                  ///< Transmit flow control enable 
+#define ETH_MACFCR_FCBBPA_Pos           (0)
+#define ETH_MACFCR_FCBBPA               (0x01U << ETH_MACFCR_FCBBPA_Pos)                ///< Flow control busy/backpressure activate 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACVLANTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACVLANTR_VLANTI            (0x0000FFFFU)                                  ///< VLAN tag identifier (for receive frames) 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACRWUFFR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACRWUFFR_D                 (0xFFFFFFFFU)                                  ///< Wake-up frame filter register data 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACPMTCSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACPMTCSR_WFFRPR_Pos        (31)                                     ///< Wake-Up Frame Filter Register Pointer Reset
+#define ETH_MACPMTCSR_WFFRPR            (0x01U << ETH_MACPMTCSR_WFFRPR_Pos)                  ///< Wake-Up Frame Filter Register Pointer Reset
+#define ETH_MACPMTCSR_GU_Pos            (9)
+#define ETH_MACPMTCSR_GU                (0x01U << ETH_MACPMTCSR_GU_Pos)                   ///< Global Unicast 
+#define ETH_MACPMTCSR_WFR_Pos           (6)
+#define ETH_MACPMTCSR_WFR               (0x01U << ETH_MACPMTCSR_WFR_Pos)                  ///< Wake-Up Frame Received 
+#define ETH_MACPMTCSR_MPR_Pos           (5)
+#define ETH_MACPMTCSR_MPR               (0x01U << ETH_MACPMTCSR_MPR_Pos)                  ///< Magic Packet Received 
+#define ETH_MACPMTCSR_WFE_Pos           (2)
+#define ETH_MACPMTCSR_WFE               (0x01U << ETH_MACPMTCSR_WFE_Pos)                  ///< Wake-Up Frame Enable 
+#define ETH_MACPMTCSR_MPE_Pos           (1)
+#define ETH_MACPMTCSR_MPE               (0x01U << ETH_MACPMTCSR_MPE_Pos)                  ///< Magic Packet Enable 
+#define ETH_MACPMTCSR_PD_Pos            (0)
+#define ETH_MACPMTCSR_PD                (0x01U << ETH_MACPMTCSR_PD_Pos)                  ///< Power Down 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA0HR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA0HR_MACA0H              ((u32)0x0000FFFF)                  ///< MAC address0 high 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA0LR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA0LR_MACA0L              ((u32)0xFFFFFFFF)                  ///< MAC address0 low 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA1HR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA1HR_AE_Pos              (31)
+#define ETH_MACA1HR_AE                  (0x01U << ETH_MACA1HR_AE_Pos)                  ///< Address enable 
+#define ETH_MACA1HR_SA_Pos              (30)
+#define ETH_MACA1HR_SA                  (0x01U << ETH_MACA1HR_SA_Pos)                  ///< Source address 
+#define ETH_MACA1HR_MBC_Pos             (24)
+#define ETH_MACA1HR_MBC                 (0x3FU << ETH_MACA1HR_MBC_Pos)                  ///< Mask byte control: bits to mask for comparison of the MAC Address bytes 
+#define ETH_MACA1HR_MBC_HBits15_8       (0x20U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address high reg bits [15:8] 
+#define ETH_MACA1HR_MBC_HBits7_0        (0x10U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address high reg bits [7:0] 
+#define ETH_MACA1HR_MBC_LBits31_24      (0x08U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [31:24] 
+#define ETH_MACA1HR_MBC_LBits23_16      (0x04U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [23:16] 
+#define ETH_MACA1HR_MBC_LBits15_8       (0x02U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [15:8] 
+#define ETH_MACA1HR_MBC_LBits7_0        (0x00U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [7:0] 
+#define ETH_MACA1HR_MACA1H_Pos          (0)
+#define ETH_MACA1HR_MACA1H              (0x0000FFFFU << ETH_MACA1HR_MACA1H_Pos)         ///< MAC address1 high 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA1LR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA1LR_MACA1L              (0xFFFFFFFFU)                                  ///< MAC address1 low 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA2HR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA2HR_AE_Pos              (31)
+#define ETH_MACA2HR_AE                  (0x01U << ETH_MACA2HR_AE_Pos)                  ///< Address enable 
+#define ETH_MACA2HR_SA_Pos              (30)
+#define ETH_MACA2HR_SA                  (0x01U << ETH_MACA2HR_SA_Pos)                  ///< Source address 
+#define ETH_MACA2HR_MBC_Pos             (24)
+#define ETH_MACA2HR_MBC                 (0x3FU << ETH_MACA2HR_MBC_Pos)                  ///< Mask byte control: bits to mask for comparison of the MAC Address bytes 
+#define ETH_MACA2HR_MBC_HBits15_8       (0x20U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address high reg bits [15:8] 
+#define ETH_MACA2HR_MBC_HBits7_0        (0x10U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address high reg bits [7:0] 
+#define ETH_MACA2HR_MBC_LBits31_24      (0x08U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [31:24] 
+#define ETH_MACA2HR_MBC_LBits23_16      (0x04U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [23:16] 
+#define ETH_MACA2HR_MBC_LBits15_8       (0x02U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [15:8] 
+#define ETH_MACA2HR_MBC_LBits7_0        (0x00U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [7:0] 
+#define ETH_MACA2HR_MACA2H_Pos          (0)
+#define ETH_MACA2HR_MACA2H              (0x0000FFFFU << ETH_MACA2HR_MACA2H_Pos)         ///< MAC address2 high 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACA2LR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACA2LR_MACA2L              (0xFFFFFFFFU)                                  ///< MAC address2 low 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACANCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACANCR_LR_Pos              (17)
+#define ETH_MACANCR_LR                  (0x01U << ETH_MACANCR_LR_Pos)                   ///< Lock to Reference
+#define ETH_MACANCR_ECD_Pos             (16)
+#define ETH_MACANCR_ECD                 (0x01U << ETH_MACANCR_ECD_Pos)                  ///< Enable Comma Detect 
+#define ETH_MACANCR_ELE_Pos             (14)
+#define ETH_MACANCR_ELE                 (0x01U << ETH_MACANCR_ELE_Pos)                  ///< External Loopback Enable
+#define ETH_MACANCR_ANE_Pos             (12)
+#define ETH_MACANCR_ANE                 (0x01U << ETH_MACANCR_ANE_Pos)                  ///< Auto-Negotiation Enable 
+#define ETH_MACANCR_RAN_Pos             (9)
+#define ETH_MACANCR_RAN                 (0x01U << ETH_MACANCR_RAN_Pos)                  ///< Restart Auto-Negotiation 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACANSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACANSR_ES_Pos              (8)
+#define ETH_MACANSR_ES                  (0x01U << ETH_MACANSR_ES_Pos)                   ///< Extended Status
+#define ETH_MACANSR_ANC_Pos             (5)
+#define ETH_MACANSR_ANC                 (0x01U << ETH_MACANSR_ANC_Pos)                  ///< Auto-Negotiation Complete 
+#define ETH_MACANSR_ANA_Pos             (3)
+#define ETH_MACANSR_ANA                 (0x01U << ETH_MACANSR_ANA_Pos)                  ///< Auto-Negotiation Ability
+#define ETH_MACANSR_LS_Pos              (2)
+#define ETH_MACANSR_LS                  (0x01U << ETH_MACANSR_LS_Pos)                  ///< Link Status 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACANAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACANAR_NP_Pos              (15)
+#define ETH_MACANAR_NP                  (0x01U << ETH_MACANAR_NP_Pos)                   ///< Next Page Support
+#define ETH_MACANAR_RFE_Pos             (12)
+#define ETH_MACANAR_RFE                 (0x01U << ETH_MACANAR_RFE_Pos)                  ///< Remote Fault Encoding
+#define ETH_MACANAR_PSE_Pos             (7)
+#define ETH_MACANAR_PSE                 (0x01U << ETH_MACANAR_PSE_Pos)                  ///< Pause Encoding
+#define ETH_MACANAR_HD_Pos              (6)
+#define ETH_MACANAR_HD                  (0x01U << ETH_MACANAR_HD_Pos)                  ///< support Half-Duplex 
+#define ETH_MACANAR_FD_Pos              (5)
+#define ETH_MACANAR_FD                  (0x01U << ETH_MACANAR_FD_Pos)                  ///< support Full-Durplex 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACANLPAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACANLPAR_NP_Pos              (15)
+#define ETH_MACANLPAR_NP                  (0x01U << ETH_MACANLPAR_NP_Pos)                   ///< Next Page Support
+#define ETH_MACANLPAR_ACK_Pos             (14)
+#define ETH_MACANLPAR_ACK                 (0x01U << ETH_MACANLPAR_ACK_Pos)                ///< Acknowledge
+#define ETH_MACANLPAR_RFE_Pos             (12)
+#define ETH_MACANLPAR_RFE                 (0x01U << ETH_MACANLPAR_RFE_Pos)                  ///< Remote Fault Encoding
+#define ETH_MACANLPAR_PSE_Pos             (7)
+#define ETH_MACANLPAR_PSE                 (0x01U << ETH_MACANLPAR_PSE_Pos)                  ///< Pause Encoding
+#define ETH_MACANLPAR_HD_Pos              (6)
+#define ETH_MACANLPAR_HD                  (0x01U << ETH_MACANLPAR_HD_Pos)                  ///< support Half-Duplex 
+#define ETH_MACANLPAR_FD_Pos              (5)
+#define ETH_MACANLPAR_FD                  (0x01U << ETH_MACANLPAR_FD_Pos)                  ///< support Full-Durplex 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACANER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACANER_NPA_Pos              (2)
+#define ETH_MACANER_NPA                  (0x01U << ETH_MACANER_NPA_Pos)                   ///< Next Page Ability
+#define ETH_MACANER_NPR_Pos              (1)
+#define ETH_MACANER_NPR                  (0x01U << ETH_MACANER_NPR_Pos)                   ///< New Page Received
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACTBIER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACTBIER_GFD_Pos              (15)
+#define ETH_MACTBIER_GFD                  (0x01U << ETH_MACTBIER_GFD_Pos)                   ///< 1000BASE-X Full-Duplex Capable
+#define ETH_MACTBIER_GHD_Pos              (14)
+#define ETH_MACTBIER_GHD                  (0x01U << ETH_MACTBIER_GHD_Pos)                   ///< 1000BASE-X Half-Duplex Capable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MACMIISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MACMIISR_LS_Pos               (3)
+#define ETH_MACMIISR_LS                   (0x01U << ETH_MACMIISR_LS_Pos)                   ///< Link Status
+#define ETH_MACMIISR_LSP_Pos              (1)
+#define ETH_MACMIISR_LSP_2_5              (0x00U << ETH_MACMIISR_LSP_Pos)                   ///< Link Speed 2.5 MHz
+#define ETH_MACMIISR_LSP_25               (0x01U << ETH_MACMIISR_LSP_Pos)                   ///< Link Speed 25  MHz
+#define ETH_MACMIISR_LSP_125              (0x02U << ETH_MACMIISR_LSP_Pos)                   ///< Link Speed 125 MHz
+#define ETH_MACMIISR_LM_Pos               (0)
+#define ETH_MACMIISR_LM                   (0x01U << ETH_MACMIISR_LM_Pos)                   ///< Link Mode : Full-Duplex Capable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCCR_MCFHP                 ((u32)0x00000020)                  ///< MMC counter Full-Half preset
+#define ETH_MMCCR_MCP                   ((u32)0x00000010)                  ///< MMC counter preset
+#define ETH_MMCCR_MCF                   ((u32)0x00000008)                  ///< MMC Counter Freeze
+#define ETH_MMCCR_ROR_Pos               (2)
+#define ETH_MMCCR_ROR                   (0x01U << ETH_MMCCR_ROR_Pos)                  ///< Reset on Read 
+#define ETH_MMCCR_CSR_Pos               (1)
+#define ETH_MMCCR_CSR                   (0x01U << ETH_MMCCR_CSR_Pos)                  ///< Counter Stop Rollover 
+#define ETH_MMCCR_CR_Pos                (0)
+#define ETH_MMCCR_CR                    (0x01U << ETH_MMCCR_CR_Pos)                  ///< Counters Reset 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCRIR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCRIR_RGUF_Pos             (17)
+#define ETH_MMCRIR_RGUFS                (0x01U << ETH_MMCRIR_RGUF_Pos)                  ///< Set when Rx good unicast frames counter reaches half the maximum value 
+#define ETH_MMCRIR_RFAES_Pos            (6)
+#define ETH_MMCRIR_RFAES                (0x01U << ETH_MMCRIR_RFAES_Pos)                 ///< Set when Rx alignment error counter reaches half the maximum value 
+#define ETH_MMCRIR_RFCES_Pos            (5)
+#define ETH_MMCRIR_RFCES                (0x01U << ETH_MMCRIR_RFCES_Pos)                 ///< Set when Rx crc error counter reaches half the maximum value 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCTIR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCTIR_TGFS_Pos             (21)
+#define ETH_MMCTIR_TGFS                 (0x01U << ETH_MMCTIR_TGFS_Pos)                  ///< Set when Tx good frame count counter reaches half the maximum value 
+#define ETH_MMCTIR_TGFMSCS_Pos          (15)
+#define ETH_MMCTIR_TGFMSCS              (0x01U << ETH_MMCTIR_TGFMSCS_Pos)               ///< Set when Tx good multi col counter reaches half the maximum value 
+#define ETH_MMCTIR_TGFSCS_Pos           (14)
+#define ETH_MMCTIR_TGFSCS               (0x01U << ETH_MMCTIR_TGFSCS_Pos)                ///< Set when Tx good single col counter reaches half the maximum value 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCRIMR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCRIMR_RGUFM_Pos            (17)
+#define ETH_MMCRIMR_RGUFM                (0x01U << ETH_MMCRIMR_RGUFM_Pos)                ///< Mask the interrupt when Rx good unicast frames counter reaches half the maximum value 
+#define ETH_MMCRIMR_RFAEM_Pos            (6)
+#define ETH_MMCRIMR_RFAEM                (0x01U << ETH_MMCRIMR_RFAEM_Pos)                ///< Mask the interrupt when when Rx alignment error counter reaches half the maximum value 
+#define ETH_MMCRIMR_RFCEM_Pos            (5)
+#define ETH_MMCRIMR_RFCEM                (0x01U << ETH_MMCRIMR_RFCEM_Pos)                ///< Mask the interrupt when Rx crc error counter reaches half the maximum value 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCTIMR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCTIMR_TGFM_Pos             (21)
+#define ETH_MMCTIMR_TGFM                 (0x01U << ETH_MMCTIMR_TGFM_Pos)                  ///< Mask the interrupt when Tx good frame count counter reaches half the maximum value 
+#define ETH_MMCTIMR_TGFMSCM_Pos          (15)
+#define ETH_MMCTIMR_TGFMSCM              (0x01U << ETH_MMCTIMR_TGFMSCM_Pos)               ///< Mask the interrupt when Tx good multi col counter reaches half the maximum value 
+#define ETH_MMCTIMR_TGFSCM_Pos           (14)
+#define ETH_MMCTIMR_TGFSCM               (0x01U << ETH_MMCTIMR_TGFSCM_Pos)                ///< Mask the interrupt when Tx good single col counter reaches half the maximum value 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCTGFSCCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCTGFSCCR_TGFSCC           (0xFFFFFFFFU)                                     ///< Number of successfully transmitted frames after a single collision in Half-duplex mode. 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCTGFMSCCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCTGFMSCCR_TGFMSCC         (0xFFFFFFFFU)                                    ///< Number of successfully transmitted frames after more than a single collision in Half-duplex mode. 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCTGFCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCTGFCR_TGFC               (0xFFFFFFFFU)                                    ///< Number of good frames transmitted. 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCRFCECR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCRFCECR_RFCEC             (0xFFFFFFFFU)                                    ///< Number of frames received with CRC error. 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCRFAECR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCRFAECR_RFAEC             (0xFFFFFFFFU)                                   ///< Number of frames received with alignment (dribble) error 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_MMCRGUFCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_MMCRGUFCR_RGUFC             (0xFFFFFFFFU)                                  ///< Number of good unicast frames received. 
+/// @brief ETH_DMABMR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMABMR_FB_Pos               (16)
+#define ETH_DMABMR_FB                   (0x01U << ETH_DMABMR_FB_Pos)            ///< Fixed Burst 
+#define ETH_DMABMR_RTPR_Pos             (14)
+#define ETH_DMABMR_RTPR                 (0x03U << ETH_DMABMR_RTPR_Pos)          ///< Rx Tx priority ratio 
+#define ETH_DMABMR_RTPR_1_1             (0x00U << ETH_DMABMR_RTPR_Pos)          ///< Rx Tx priority ratio 
+#define ETH_DMABMR_RTPR_2_1             (0x01U << ETH_DMABMR_RTPR_Pos)          ///< Rx Tx priority ratio 
+#define ETH_DMABMR_RTPR_3_1             (0x02U << ETH_DMABMR_RTPR_Pos)          ///< Rx Tx priority ratio 
+#define ETH_DMABMR_RTPR_4_1             (0x03U << ETH_DMABMR_RTPR_Pos)          ///< Rx Tx priority ratio 
+#define ETH_DMABMR_PBL_Pos              (8)
+#define ETH_DMABMR_PBL                  (0x3FU<< ETH_DMABMR_PBL_Pos)            //< Programmable burst length 
+#define ETH_DMABMR_PBL_1Beat            (0x01U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 
+#define ETH_DMABMR_PBL_2Beat            (0x02U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 
+#define ETH_DMABMR_PBL_4Beat            (0x04U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 
+#define ETH_DMABMR_PBL_8Beat            (0x08U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 
+#define ETH_DMABMR_PBL_16Beat           (0x10U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 
+#define ETH_DMABMR_PBL_32Beat           (0x20U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 
+#define ETH_DMABMR_PBL_4xPBL_4Beat      (0x10001U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 
+#define ETH_DMABMR_PBL_4xPBL_8Beat      (0x10002U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 
+#define ETH_DMABMR_PBL_4xPBL_16Beat     (0x10004U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 
+#define ETH_DMABMR_PBL_4xPBL_32Beat     (0x10008U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 
+#define ETH_DMABMR_PBL_4xPBL_64Beat     (0x10010U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 
+#define ETH_DMABMR_PBL_4xPBL_128Beat    (0x10020U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 
+
+#define ETH_DMABMR_DSL_Pos              (2)
+#define ETH_DMABMR_DSL                  (0x01U << ETH_DMABMR_DSL_Pos)            ///< Descriptor Skip Length 
+#define ETH_DMABMR_DA_Pos               (1)
+#define ETH_DMABMR_DA                   (0x1FU << ETH_DMABMR_DA_Pos)             ///< DMA arbitration scheme 
+#define ETH_DMABMR_SR_Pos               (0)
+#define ETH_DMABMR_SR                   (0x01U << ETH_DMABMR_SR_Pos)             ///< Software reset 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMATPDR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMATPDR_TPD                 (0xFFFFFFFFU)                            ///< Transmit poll demand 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMARPDR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMARPDR_RPD                 (0xFFFFFFFFU)                            ///< Receive poll demand  
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMARDLAR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMARDLAR_SRL                (0xFFFFFFFFU)                            ///< Start of receive list 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMATDLAR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMATDLAR_STL                (0xFFFFFFFFU)                            ///< Start of transmit list 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMASR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMASR_PMTS_Pos              (28)
+#define ETH_DMASR_PMTS                  (0x01U << ETH_DMASR_PMTS_Pos)                ///< PMT status 
+#define ETH_DMASR_MMCS_Pos              (27)
+#define ETH_DMASR_MMCS                  (0x01U << ETH_DMASR_MMCS_Pos)                ///< MMC status 
+#define ETH_DMASR_LIS_Pos               (26)
+#define ETH_DMASR_LIS                   (0x01U << ETH_DMASR_LIS_Pos)                ///< GMAC Line interface Status 
+
+#define ETH_DMASR_EBS_Pos               (23)
+#define ETH_DMASR_EBS                   (0x07U << ETH_DMASR_EBS_Pos)                ///< Error bits status 
+#define ETH_DMASR_EBS_DescAccess        (0x04U << ETH_DMASR_EBS_Pos)                ///< Error bits 0-data buffer, 1-desc. access 
+#define ETH_DMASR_EBS_ReadTransf        (0x02U << ETH_DMASR_EBS_Pos)                ///< Error bits 0-write trnsf, 1-read transfr 
+#define ETH_DMASR_EBS_DataTransfTx      (0x01U << ETH_DMASR_EBS_Pos)                ///< Error bits 0-Rx DMA, 1-Tx DMA 
+#define ETH_DMASR_TPS_Pos               (20)
+#define ETH_DMASR_TPS                   (0x007U << ETH_DMASR_TPS_Pos)                  ///< Transmit process state 
+#define ETH_DMASR_TPS_Stopped           (0x000U << ETH_DMASR_TPS_Pos)                  ///< Stopped - Reset or Stop Tx Command issued  
+#define ETH_DMASR_TPS_Fetching          (0x001U << ETH_DMASR_TPS_Pos)                  ///< Running - fetching the Tx descriptor 
+#define ETH_DMASR_TPS_Waiting           (0x002U << ETH_DMASR_TPS_Pos)                  ///< Running - waiting for status 
+#define ETH_DMASR_TPS_Reading           (0x003U << ETH_DMASR_TPS_Pos)                  ///< Running - reading the data from host memory 
+#define ETH_DMASR_TPS_Suspended         (0x006U << ETH_DMASR_TPS_Pos)                  ///< Suspended - Tx Descriptor unavailabe 
+#define ETH_DMASR_TPS_Closing           (0x007U << ETH_DMASR_TPS_Pos)                  ///< Running - closing Rx descriptor 
+#define ETH_DMASR_RPS_Pos               (17)
+#define ETH_DMASR_RPS                   (0x07U << ETH_DMASR_RPS_Pos)                  ///< Receive process state 
+#define ETH_DMASR_RPS_Stopped           (0x00U << ETH_DMASR_RPS_Pos)                  ///< Stopped - Reset or Stop Rx Command issued 
+#define ETH_DMASR_RPS_Fetching          (0x01U << ETH_DMASR_RPS_Pos)                  ///< Running - fetching the Rx descriptor 
+#define ETH_DMASR_RPS_Waiting           (0x03U << ETH_DMASR_RPS_Pos)                  ///< Running - waiting for packet 
+#define ETH_DMASR_RPS_Suspended         (0x04U << ETH_DMASR_RPS_Pos)                  ///< Suspended - Rx Descriptor unavailable 
+#define ETH_DMASR_RPS_Closing           (0x05U << ETH_DMASR_RPS_Pos)                  ///< Running - closing descriptor 
+#define ETH_DMASR_RPS_Queuing           (0x07U << ETH_DMASR_RPS_Pos)                  ///< Running - queuing the recieve frame into host memory 
+#define ETH_DMASR_NIS_Pos               (16)
+#define ETH_DMASR_NIS                   (0x01U << ETH_DMASR_NIS_Pos )                  ///< Normal interrupt summary 
+#define ETH_DMASR_AIS_Pos               (15)
+#define ETH_DMASR_AIS                   (0x01U << ETH_DMASR_AIS_Pos )                  ///< Abnormal interrupt summary 
+#define ETH_DMASR_ERS_Pos               (14)
+#define ETH_DMASR_ERS                   (0x01U << ETH_DMASR_ERS_Pos )                  ///< Early receive status 
+#define ETH_DMASR_FBES_Pos              (13)
+#define ETH_DMASR_FBES                  (0x01U << ETH_DMASR_FBES_Pos)                  ///< Fatal bus error status 
+#define ETH_DMASR_ETS_Pos               (10)
+#define ETH_DMASR_ETS                   (0x01U << ETH_DMASR_ETS_Pos )                  ///< Early transmit status 
+#define ETH_DMASR_RWTS_Pos              (9)
+#define ETH_DMASR_RWTS                  (0x01U << ETH_DMASR_RWTS_Pos)                  ///< Receive watchdog timeout status 
+#define ETH_DMASR_RPSS_Pos              (8)
+#define ETH_DMASR_RPSS                  (0x01U << ETH_DMASR_RPSS_Pos)                  ///< Receive process stopped status 
+#define ETH_DMASR_RBUS_Pos              (7)
+#define ETH_DMASR_RBUS                  (0x01U << ETH_DMASR_RBUS_Pos)                  ///< Receive buffer unavailable status 
+#define ETH_DMASR_RS_Pos                (6)
+#define ETH_DMASR_RS                    (0x01U << ETH_DMASR_RS_Pos  )                  ///< Receive status 
+#define ETH_DMASR_TUS_Pos               (5)
+#define ETH_DMASR_TUS                   (0x01U << ETH_DMASR_TUS_Pos )                  ///< Transmit underflow status 
+#define ETH_DMASR_ROS_Pos               (4)
+#define ETH_DMASR_ROS                   (0x01U << ETH_DMASR_ROS_Pos )                  ///< Receive overflow status 
+#define ETH_DMASR_TJTS_Pos              (3)
+#define ETH_DMASR_TJTS                  (0x01U << ETH_DMASR_TJTS_Pos)                  ///< Transmit jabber timeout status 
+#define ETH_DMASR_TBUS_Pos              (2)
+#define ETH_DMASR_TBUS                  (0x01U << ETH_DMASR_TBUS_Pos)                  ///< Transmit buffer unavailable status 
+#define ETH_DMASR_TPSS_Pos              (1)
+#define ETH_DMASR_TPSS                  (0x01U << ETH_DMASR_TPSS_Pos)                  ///< Transmit process stopped status 
+#define ETH_DMASR_TS_Pos                (0)
+#define ETH_DMASR_TS                    (0x01U << ETH_DMASR_TS_Pos  )                  ///< Transmit status 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMAOMR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define ETH_DMAOMR_TSF_Pos              (21)
+#define ETH_DMAOMR_TSF                  (0x01U << ETH_DMAOMR_TSF_Pos)                  ///< Transmit store and forward 
+#define ETH_DMAOMR_FTF_Pos              (20)
+#define ETH_DMAOMR_FTF                  (0x01U << ETH_DMAOMR_FTF_Pos)                  ///< Flush transmit FIFO 
+#define ETH_DMAOMR_TTC_Pos              (14)
+#define ETH_DMAOMR_TTC                  (0x07U << ETH_DMAOMR_TTC_Pos)                  ///< Transmit threshold control 
+#define ETH_DMAOMR_TTC_64Bytes          (0x00U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 64 Bytes 
+#define ETH_DMAOMR_TTC_128Bytes         (0x01U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 128 Bytes 
+#define ETH_DMAOMR_TTC_192Bytes         (0x02U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 192 Bytes 
+#define ETH_DMAOMR_TTC_256Bytes         (0x03U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 256 Bytes 
+#define ETH_DMAOMR_TTC_40Bytes          (0x04U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 40 Bytes 
+#define ETH_DMAOMR_TTC_32Bytes          (0x05U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 32 Bytes 
+#define ETH_DMAOMR_TTC_24Bytes          (0x06U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 24 Bytes 
+#define ETH_DMAOMR_TTC_16Bytes          (0x07U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 16 Bytes 
+#define ETH_DMAOMR_ST_Pos               (13)
+#define ETH_DMAOMR_ST                   (0x01U << ETH_DMAOMR_ST_Pos  )                  ///< Start/stop transmission command 
+#define ETH_DMAOMR_RFD_Pos              (11)
+#define ETH_DMAOMR_RFD1                 (0x00U << ETH_DMAOMR_RFD_Pos  )                 ///< Threshold for failure flow control 1 byte
+#define ETH_DMAOMR_RFD2                 (0x01U << ETH_DMAOMR_RFD_Pos  )                 ///< Threshold for failure flow control 2 byte
+#define ETH_DMAOMR_RFD3                 (0x02U << ETH_DMAOMR_RFD_Pos  )                 ///< Threshold for failure flow control 3 byte
+#define ETH_DMAOMR_RFD4                 (0x03U << ETH_DMAOMR_RFD_Pos  )                 ///< Threshold for failure flow control 4 byte
+#define ETH_DMAOMR_RFA_Pos              (9)
+#define ETH_DMAOMR_RFA1                 (0x00U << ETH_DMAOMR_RFA_Pos  )                 ///< Activate the threshold for flow control 1 byte
+#define ETH_DMAOMR_RFA2                 (0x01U << ETH_DMAOMR_RFA_Pos  )                 ///< Activate the threshold for flow control 2 byte
+#define ETH_DMAOMR_RFA3                 (0x02U << ETH_DMAOMR_RFA_Pos  )                 ///< Activate the threshold for flow control 3 byte
+#define ETH_DMAOMR_RFA4                 (0x03U << ETH_DMAOMR_RFA_Pos  )                 ///< Activate the threshold for flow control 4 byte
+
+#define ETH_DMAOMR_EFC_Pos              (8)
+#define ETH_DMAOMR_EFC                  (0x01U << ETH_DMAOMR_EFC_Pos )                  ///< Enable HW Flow Control 
+#define ETH_DMAOMR_FEF_Pos              (7)
+#define ETH_DMAOMR_FEF                  (0x01U << ETH_DMAOMR_FEF_Pos )                  ///< Forward error frames 
+#define ETH_DMAOMR_FUGF_Pos             (6)
+#define ETH_DMAOMR_FUGF                 (0x01U << ETH_DMAOMR_FUGF_Pos)                  ///< Forward undersized good frames 
+#define ETH_DMAOMR_RTC_Pos              (3)
+#define ETH_DMAOMR_RTC                  (0x03U << ETH_DMAOMR_RTC_Pos)                  ///< receive threshold control 
+#define ETH_DMAOMR_RTC_64Bytes          (0x00U << ETH_DMAOMR_RTC_Pos)                  ///< threshold level of the MTL Receive FIFO is 64 Bytes 
+#define ETH_DMAOMR_RTC_32Bytes          (0x01U << ETH_DMAOMR_RTC_Pos)                  ///< threshold level of the MTL Receive FIFO is 32 Bytes 
+#define ETH_DMAOMR_RTC_96Bytes          (0x02U << ETH_DMAOMR_RTC_Pos)                  ///< threshold level of the MTL Receive FIFO is 96 Bytes 
+#define ETH_DMAOMR_RTC_128Bytes         (0x03U << ETH_DMAOMR_RTC_Pos)                  ///< threshold level of the MTL Receive FIFO is 128 Bytes 
+#define ETH_DMAOMR_OSF_Pos              (2)
+#define ETH_DMAOMR_OSF                  (0x01U << ETH_DMAOMR_OSF_Pos)                  ///< operate on second frame 
+#define ETH_DMAOMR_SR_Pos               (1)
+#define ETH_DMAOMR_SR                   (0x01U << ETH_DMAOMR_SR_Pos )                  ///< Start/stop receive 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMAIER Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMAIER_NISE_Pos             (16)
+#define ETH_DMAIER_NISE                 (0x01U << ETH_DMAIER_NISE_Pos )                  ///< Normal interrupt summary enable 
+#define ETH_DMAIER_AISE_Pos             (15)
+#define ETH_DMAIER_AISE                 (0x01U << ETH_DMAIER_AISE_Pos )                  ///< Abnormal interrupt summary enable 
+#define ETH_DMAIER_ERIE_Pos             (14)
+#define ETH_DMAIER_ERIE                 (0x01U << ETH_DMAIER_ERIE_Pos )                  ///< Early receive interrupt enable 
+#define ETH_DMAIER_FBEIE_Pos            (13)
+#define ETH_DMAIER_FBEIE                (0x01U << ETH_DMAIER_FBEIE_Pos)                  ///< Fatal bus error interrupt enable 
+#define ETH_DMAIER_ETIE_Pos             (10)
+#define ETH_DMAIER_ETIE                 (0x01U << ETH_DMAIER_ETIE_Pos )                  ///< Early transmit interrupt enable 
+#define ETH_DMAIER_RWTIE_Pos            (9)
+#define ETH_DMAIER_RWTIE                (0x01U << ETH_DMAIER_RWTIE_Pos)                  ///< Receive watchdog timeout interrupt enable 
+#define ETH_DMAIER_RPSIE_Pos            (8)
+#define ETH_DMAIER_RPSIE                (0x01U << ETH_DMAIER_RPSIE_Pos)                  ///< Receive process stopped interrupt enable 
+#define ETH_DMAIER_RBUIE_Pos            (7)
+#define ETH_DMAIER_RBUIE                (0x01U << ETH_DMAIER_RBUIE_Pos)                  ///< Receive buffer unavailable interrupt enable 
+#define ETH_DMAIER_RIE_Pos              (6)
+#define ETH_DMAIER_RIE                  (0x01U << ETH_DMAIER_RIE_Pos  )                  ///< Receive interrupt enable 
+#define ETH_DMAIER_TUIE_Pos             (5)
+#define ETH_DMAIER_TUIE                 (0x01U << ETH_DMAIER_TUIE_Pos )                  ///< Transmit Underflow interrupt enable 
+#define ETH_DMAIER_ROIE_Pos             (4)
+#define ETH_DMAIER_ROIE                 (0x01U << ETH_DMAIER_ROIE_Pos )                  ///< Receive Overflow interrupt enable 
+#define ETH_DMAIER_TJTIE_Pos            (3)
+#define ETH_DMAIER_TJTIE                (0x01U << ETH_DMAIER_TJTIE_Pos)                  ///< Transmit jabber timeout interrupt enable 
+#define ETH_DMAIER_TBUIE_Pos            (2)
+#define ETH_DMAIER_TBUIE                (0x01U << ETH_DMAIER_TBUIE_Pos)                  ///< Transmit buffer unavailable interrupt enable 
+#define ETH_DMAIER_TPSIE_Pos            (1)
+#define ETH_DMAIER_TPSIE                (0x01U << ETH_DMAIER_TPSIE_Pos)                  ///< Transmit process stopped interrupt enable 
+#define ETH_DMAIER_TIE_Pos              (0)
+#define ETH_DMAIER_TIE                  (0x01U << ETH_DMAIER_TIE_Pos  )                  ///< Transmit interrupt enable 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMAMFBOCR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMAMFBOCR_OFOC_Pos          (28)
+#define ETH_DMAMFBOCR_OFOC              (0x01U << ETH_DMAMFBOCR_OFOC_Pos)                  ///< Overflow bit for FIFO overflow counter 
+
+#define ETH_DMAMFBOCR_MFA_Pos           (17)
+#define ETH_DMAMFBOCR_MFA               (0x7FFU << ETH_DMAMFBOCR_MFA_Pos )                 ///< Number of frames missed by the application 
+
+#define ETH_DMAMFBOCR_OMFC_Pos          (16)
+#define ETH_DMAMFBOCR_OMFC              (0x01U << ETH_DMAMFBOCR_OMFC_Pos)                  ///< Overflow bit for missed frame counter 
+
+#define ETH_DMAMFBOCR_MFC_Pos           (0)
+#define ETH_DMAMFBOCR_MFC               (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos )                ///< Number of frames missed by the controller 
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMACHTDR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMACHTDR_HTDAP              (0xFFFFFFFFU)                                      ///< Host transmit descriptor address pointer 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMACHRDR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMACHRDR_HRDAP              (0xFFFFFFFFU)                                      ///< Host receive descriptor address pointer 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMACHTBAR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMACHTBAR_HTBAP             (0xFFFFFFFFU)                                      ///< Host transmit buffer address pointer 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief ETH_DMACHRBAR Registers bits definition
+////////////////////////////////////////////////////////////////////////////////
+#define ETH_DMACHRBAR_HRBAP             (0xFFFFFFFFU)                                     ///< Host receive buffer address pointer 
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h
new file mode 100644
index 000000000..608c12bc2
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h
@@ -0,0 +1,544 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_exti.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_EXTI_H
+#define __REG_EXTI_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_BASE                       (APB2PERIPH_BASE + 0x0000)              ///< Base Address: 0x40010000
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 CFGR;                                                              ///< configuration register,                        offset: 0x00
+    u32 Reserved;                                                               ///< Reserved                                       offset: 0x04
+    __IO u32 CR[4];                                                             ///< External interrupt configuration register,     offset: 0x08 - 0x14
+    __IO u32 CFGR2;                                                             ///< configuration register                        offset: 0x18
+    __IO u32 PDETCSR;                                                           ///< Power detection configuration status register offset: 0x1C
+    __IO u32 VOSDLY;                                                            ///< VOS delay time                                offset: 0x20
+    u32 Reserved1[0x100 - 0x09];                                                ///< Reserved space
+    __IO u32 IMR;                                                               ///< Interrupt Mask Register                        offset: 0x00 + 0x400
+    __IO u32 EMR;                                                               ///< Event Mask Register                            offset: 0x04 + 0x400
+    __IO u32 RTSR;                                                              ///< Rising Trigger Status Register                 offset: 0x08 + 0x400
+    __IO u32 FTSR;                                                              ///< Falling Trigger Status Register                offset: 0x0C + 0x400
+    __IO u32 SWIER;                                                             ///< Software Interrupt Enable Register             offset: 0x10 + 0x400
+    __IO u32 PR;                                                                ///< Pending Register                               offset: 0x14 + 0x400
+} EXTI_TypeDef;
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI                        ((EXTI_TypeDef*) EXTI_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CFGR_MEMMODE_Pos       (0)
+#define EXTI_CFGR_MEMMODE           (0x03U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config
+#define EXTI_CFGR_MEMMODE_0         (0x01U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config Bit 0
+#define EXTI_CFGR_MEMMODE_1         (0x02U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config Bit 1
+#define EXTI_CFGR_FLASH_MEMORY      (0x00U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config Mode 0
+#define EXTI_CFGR_SYSTEM_MEMORY     (0x01U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config Mode 1
+#define EXTI_CFGR_SRAM_MEMORY       (0x03U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config Mode 3
+
+
+#define EXTI_CFGR_FC_SYNCEN_Pos     (27)
+#define EXTI_CFGR_FC_SYNCEN         (0x01U << EXTI_CFGR_FC_SYNCEN_Pos)      ///< FSMC synchronization enable
+#define EXTI_CFGR_FC_ODATAEN_Pos    (28)
+#define EXTI_CFGR_FC_ODATAEN        (0x01U << EXTI_CFGR_FC_ODATAEN_Pos)     ///< FSMC Only used as data pin
+#define EXTI_CFGR_MODESEL_Pos       (29)                                    ///< FSMC mode selection
+#define EXTI_CFGR_MODESEL0          (0x00U << EXTI_CFGR_MODESEL0_Pos)       ///< Compatible with 8080 protocol interface
+#define EXTI_CFGR_MODESEL1          (0x01U << EXTI_CFGR_MODESEL1_Pos)       ///< Compatible with NOR FLASH protocol interface
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CR1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CR1_EXTI0_Pos          (0)
+#define EXTI_CR1_EXTI0              (0x0FU << EXTI_CR1_EXTI0_Pos)           ///< EXTI 0 configuration
+#define EXTI_CR1_EXTI0_PA           (0x00U << EXTI_CR1_EXTI0_Pos)           ///< PA[0] pin
+#define EXTI_CR1_EXTI0_PB           (0x01U << EXTI_CR1_EXTI0_Pos)           ///< PB[0] pin
+#define EXTI_CR1_EXTI0_PC           (0x02U << EXTI_CR1_EXTI0_Pos)           ///< PC[0] pin
+#define EXTI_CR1_EXTI0_PD           (0x03U << EXTI_CR1_EXTI0_Pos)           ///< PD[0] pin
+
+#define EXTI_CR1_EXTI1_Pos          (4)
+#define EXTI_CR1_EXTI1              (0x0FU << EXTI_CR1_EXTI1_Pos)           ///< EXTI 1 configuration
+#define EXTI_CR1_EXTI1_PA           (0x00U << EXTI_CR1_EXTI1_Pos)           ///< PA[1] pin
+#define EXTI_CR1_EXTI1_PB           (0x01U << EXTI_CR1_EXTI1_Pos)           ///< PB[1] pin
+#define EXTI_CR1_EXTI1_PC           (0x02U << EXTI_CR1_EXTI1_Pos)           ///< PC[1] pin
+#define EXTI_CR1_EXTI1_PD           (0x03U << EXTI_CR1_EXTI1_Pos)           ///< PD[1] pin
+
+#define EXTI_CR1_EXTI2_Pos          (8)
+#define EXTI_CR1_EXTI2              (0x0FU << EXTI_CR1_EXTI2_Pos)           ///< EXTI 2 configuration
+#define EXTI_CR1_EXTI2_PA           (0x00U << EXTI_CR1_EXTI2_Pos)           ///< PA[2] pin
+#define EXTI_CR1_EXTI2_PB           (0x01U << EXTI_CR1_EXTI2_Pos)           ///< PB[2] pin
+#define EXTI_CR1_EXTI2_PC           (0x02U << EXTI_CR1_EXTI2_Pos)           ///< PC[2] pin
+#define EXTI_CR1_EXTI2_PD           (0x03U << EXTI_CR1_EXTI2_Pos)           ///< PD[2] pin
+
+#define EXTI_CR1_EXTI3_Pos          (12)
+#define EXTI_CR1_EXTI3              (0x0FU << EXTI_CR1_EXTI3_Pos)           ///< EXTI 3 configuration
+#define EXTI_CR1_EXTI3_PA           (0x00U << EXTI_CR1_EXTI3_Pos)           ///< PA[3] pin
+#define EXTI_CR1_EXTI3_PB           (0x01U << EXTI_CR1_EXTI3_Pos)           ///< PB[3] pin
+#define EXTI_CR1_EXTI3_PC           (0x02U << EXTI_CR1_EXTI3_Pos)           ///< PC[3] pin
+#define EXTI_CR1_EXTI3_PD           (0x03U << EXTI_CR1_EXTI3_Pos)           ///< PD[3] pin
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CR2_EXTI4_Pos          (0)
+#define EXTI_CR2_EXTI4              (0x0FU << EXTI_CR2_EXTI4_Pos)           ///< EXTI 4 configuration
+#define EXTI_CR2_EXTI4_PA           (0x00U << EXTI_CR2_EXTI4_Pos)           ///< PA[4] pin
+#define EXTI_CR2_EXTI4_PB           (0x01U << EXTI_CR2_EXTI4_Pos)           ///< PB[4] pin
+#define EXTI_CR2_EXTI4_PC           (0x02U << EXTI_CR2_EXTI4_Pos)           ///< PC[4] pin
+#define EXTI_CR2_EXTI4_PD           (0x03U << EXTI_CR2_EXTI4_Pos)           ///< PD[4] pin
+
+#define EXTI_CR2_EXTI5_Pos          (4)
+#define EXTI_CR2_EXTI5              (0x0FU << EXTI_CR2_EXTI5_Pos)           ///< EXTI 5 configuration
+#define EXTI_CR2_EXTI5_PA           (0x00U << EXTI_CR2_EXTI5_Pos)           ///< PA[5] pin
+#define EXTI_CR2_EXTI5_PB           (0x01U << EXTI_CR2_EXTI5_Pos)           ///< PB[5] pin
+#define EXTI_CR2_EXTI5_PC           (0x02U << EXTI_CR2_EXTI5_Pos)           ///< PC[5] pin
+#define EXTI_CR2_EXTI5_PD           (0x03U << EXTI_CR2_EXTI5_Pos)           ///< PD[5] pin
+
+#define EXTI_CR2_EXTI6_Pos          (8)
+#define EXTI_CR2_EXTI6              (0x0FU << EXTI_CR2_EXTI6_Pos)           ///< EXTI 6 configuration
+#define EXTI_CR2_EXTI6_PA           (0x00U << EXTI_CR2_EXTI6_Pos)           ///< PA[6] pin
+#define EXTI_CR2_EXTI6_PB           (0x01U << EXTI_CR2_EXTI6_Pos)           ///< PB[6] pin
+#define EXTI_CR2_EXTI6_PC           (0x02U << EXTI_CR2_EXTI6_Pos)           ///< PC[6] pin
+#define EXTI_CR2_EXTI6_PD           (0x03U << EXTI_CR2_EXTI6_Pos)           ///< PD[6] pin
+
+#define EXTI_CR2_EXTI7_Pos          (12)
+#define EXTI_CR2_EXTI7              (0x0FU << EXTI_CR2_EXTI7_Pos)           ///< EXTI 7 configuration
+#define EXTI_CR2_EXTI7_PA           (0x00U << EXTI_CR2_EXTI7_Pos)           ///< PA[7] pin
+#define EXTI_CR2_EXTI7_PB           (0x01U << EXTI_CR2_EXTI7_Pos)           ///< PB[7] pin
+#define EXTI_CR2_EXTI7_PC           (0x02U << EXTI_CR2_EXTI7_Pos)           ///< PC[7] pin
+#define EXTI_CR2_EXTI7_PD           (0x03U << EXTI_CR2_EXTI7_Pos)           ///< PD[7] pin
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CR3 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CR3_EXTI8_Pos          (0)
+#define EXTI_CR3_EXTI8              (0x0FU << EXTI_CR3_EXTI8_Pos)           ///< EXTI 8 configuration
+#define EXTI_CR3_EXTI8_PA           (0x00U << EXTI_CR3_EXTI8_Pos)           ///< PA[8] pin
+#define EXTI_CR3_EXTI8_PB           (0x01U << EXTI_CR3_EXTI8_Pos)           ///< PB[8] pin
+#define EXTI_CR3_EXTI8_PC           (0x02U << EXTI_CR3_EXTI8_Pos)           ///< PC[8] pin
+#define EXTI_CR3_EXTI8_PD           (0x03U << EXTI_CR3_EXTI8_Pos)           ///< PD[8] pin
+
+#define EXTI_CR3_EXTI9_Pos          (4)
+#define EXTI_CR3_EXTI9              (0x0FU << EXTI_CR3_EXTI9_Pos)           ///< EXTI 9 configuration
+#define EXTI_CR3_EXTI9_PA           (0x00U << EXTI_CR3_EXTI9_Pos)           ///< PA[9] pin
+#define EXTI_CR3_EXTI9_PB           (0x01U << EXTI_CR3_EXTI9_Pos)           ///< PB[9] pin
+#define EXTI_CR3_EXTI9_PC           (0x02U << EXTI_CR3_EXTI9_Pos)           ///< PC[9] pin
+#define EXTI_CR3_EXTI9_PD           (0x03U << EXTI_CR3_EXTI9_Pos)           ///< PD[9] pin
+
+#define EXTI_CR3_EXTI10_Pos         (8)
+#define EXTI_CR3_EXTI10             (0x0FU << EXTI_CR3_EXTI10_Pos)          ///< EXTI 10 configuration
+#define EXTI_CR3_EXTI10_PA          (0x00U << EXTI_CR3_EXTI10_Pos)          ///< PA[10] pin
+#define EXTI_CR3_EXTI10_PB          (0x01U << EXTI_CR3_EXTI10_Pos)          ///< PB[10] pin
+#define EXTI_CR3_EXTI10_PC          (0x02U << EXTI_CR3_EXTI10_Pos)          ///< PC[10] pin
+#define EXTI_CR3_EXTI10_PD          (0x03U << EXTI_CR3_EXTI10_Pos)          ///< PD[10] pin
+
+#define EXTI_CR3_EXTI11_Pos         (12)
+#define EXTI_CR3_EXTI11             (0x0FU << EXTI_CR3_EXTI11_Pos)          ///< EXTI 11 configuration
+#define EXTI_CR3_EXTI11_PA          (0x00U << EXTI_CR3_EXTI11_Pos)          ///< PA[11] pin
+#define EXTI_CR3_EXTI11_PB          (0x01U << EXTI_CR3_EXTI11_Pos)          ///< PB[11] pin
+#define EXTI_CR3_EXTI11_PC          (0x02U << EXTI_CR3_EXTI11_Pos)          ///< PC[11] pin
+#define EXTI_CR3_EXTI11_PD          (0x03U << EXTI_CR3_EXTI11_Pos)          ///< PD[11] pin
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CR4 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CR4_EXTI12_Pos         (0)
+#define EXTI_CR4_EXTI12             (0x0FU << EXTI_CR4_EXTI12_Pos)          ///< EXTI 12 configuration
+#define EXTI_CR4_EXTI12_PA          (0x00U << EXTI_CR4_EXTI12_Pos)          ///< PA[12] pin
+#define EXTI_CR4_EXTI12_PB          (0x01U << EXTI_CR4_EXTI12_Pos)          ///< PB[12] pin
+#define EXTI_CR4_EXTI12_PC          (0x02U << EXTI_CR4_EXTI12_Pos)          ///< PC[12] pin
+#define EXTI_CR4_EXTI12_PD          (0x03U << EXTI_CR4_EXTI12_Pos)          ///< PD[12] pin
+
+#define EXTI_CR4_EXTI13_Pos         (4)
+#define EXTI_CR4_EXTI13             (0x0FU << EXTI_CR4_EXTI13_Pos)          ///< EXTI 13 configuration
+#define EXTI_CR4_EXTI13_PA          (0x00U << EXTI_CR4_EXTI13_Pos)          ///< PA[13] pin
+#define EXTI_CR4_EXTI13_PB          (0x01U << EXTI_CR4_EXTI13_Pos)          ///< PB[13] pin
+#define EXTI_CR4_EXTI13_PC          (0x02U << EXTI_CR4_EXTI13_Pos)          ///< PC[13] pin
+#define EXTI_CR4_EXTI13_PD          (0x03U << EXTI_CR4_EXTI13_Pos)          ///< PD[13] pin
+
+#define EXTI_CR4_EXTI14_Pos         (8)
+#define EXTI_CR4_EXTI14             (0x0FU << EXTI_CR4_EXTI14_Pos)          ///< EXTI 14 configuration
+#define EXTI_CR4_EXTI14_PA          (0x00U << EXTI_CR4_EXTI14_Pos)          ///< PA[14] pin
+#define EXTI_CR4_EXTI14_PB          (0x01U << EXTI_CR4_EXTI14_Pos)          ///< PB[14] pin
+#define EXTI_CR4_EXTI14_PC          (0x02U << EXTI_CR4_EXTI14_Pos)          ///< PC[14] pin
+#define EXTI_CR4_EXTI14_PD          (0x03U << EXTI_CR4_EXTI14_Pos)          ///< PD[14] pin
+
+#define EXTI_CR4_EXTI15_Pos         (12)
+#define EXTI_CR4_EXTI15             (0x0FU << EXTI_CR4_EXTI15_Pos)          ///< EXTI 15 configuration
+#define EXTI_CR4_EXTI15_PA          (0x00U << EXTI_CR4_EXTI15_Pos)          ///< PA[15] pin
+#define EXTI_CR4_EXTI15_PB          (0x01U << EXTI_CR4_EXTI15_Pos)          ///< PB[15] pin
+#define EXTI_CR4_EXTI15_PC          (0x02U << EXTI_CR4_EXTI15_Pos)          ///< PC[15] pin
+#define EXTI_CR4_EXTI15_PD          (0x03U << EXTI_CR4_EXTI15_Pos)          ///< PD[15] pin
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_CFGR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_CFGR2_I2C1_Pos         (16)
+#define EXTI_CFGR2_I2C1_OD          (0x00U << EXTI_CFGR2_I2C1_Pos)          ///< Select open drain mode    
+#define EXTI_CFGR2_I2C1_PP          (0x01U << EXTI_CFGR2_I2C1_Pos)          ///< Select Push-pull mode    
+#define EXTI_CFGR2_I2C2_Pos         (17)
+#define EXTI_CFGR2_I2C2_OD          (0x00U << EXTI_CFGR2_I2C2_Pos)          ///< Select open drain mode    
+#define EXTI_CFGR2_I2C2_PP          (0x01U << EXTI_CFGR2_I2C2_Pos)          ///< Select Push-pull mode    
+#define EXTI_CFGR2_ETPHY_Pos        (20)
+#define EXTI_CFGR2_ETPHY_MII        (0x00U << EXTI_CFGR2_ETPHY_Pos)          ///< Select MII port      
+#define EXTI_CFGR2_ETPHY_RMII       (0x01U << EXTI_CFGR2_ETPHY_Pos)          ///< Select RMII port   
+#define EXTI_CFGR2_MAC_SPD_Pos      (20)
+#define EXTI_CFGR2_MAC_SPD_10       (0x00U << EXTI_CFGR2_ETPHY_Pos)          ///< Select MAC_SPD 10 Mbps     
+#define EXTI_CFGR2_MAC_SPD_100      (0x01U << EXTI_CFGR2_ETPHY_Pos)          ///< Select MAC_SPD 100 Mbps   
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_PDETCSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_PDETCSR_PVDE_Pos       (0)
+#define EXTI_PDETCSR_PVDE           (0x01U << EXTI_PDETCSR_PVDE_Pos)        ///< PVD Enable 
+#define EXTI_PDETCSR_PLS_Pos        (1)
+#define EXTI_PDETCSR_PLS_1_7        (0x00U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 1.7mV 
+#define EXTI_PDETCSR_PLS_2_0        (0x01U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 2.0mV 
+#define EXTI_PDETCSR_PLS_2_3        (0x02U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 2.3mV 
+#define EXTI_PDETCSR_PLS_2_6        (0x03U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 2.6mV 
+#define EXTI_PDETCSR_PLS_2_9        (0x04U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 2.9mV 
+#define EXTI_PDETCSR_PLS_3_2        (0x05U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 3.2mV 
+#define EXTI_PDETCSR_PLS_3_5        (0x06U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 3.5mV 
+#define EXTI_PDETCSR_PLS_3_8        (0x07U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 3.8mV 
+#define EXTI_PDETCSR_PLS_4_1        (0x08U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 4.1mV 
+#define EXTI_PDETCSR_PLS_4_4        (0x09U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 4.4mV 
+#define EXTI_PDETCSR_PLS_4_7        (0x0AU << EXTI_PDETCSR_PLS_Pos)        ///< PVD 4.7mV 
+#define EXTI_PDETCSR_PVDO_Pos       (5)
+#define EXTI_PDETCSR_PVDO           (0x01U << EXTI_PDETCSR_PVDO_Pos)        ///< PVD Output state 
+#define EXTI_PDETCSR_VDTO_Pos       (6)
+#define EXTI_PDETCSR_VDTO           (0x01U << EXTI_PDETCSR_VDTO_Pos)        ///< VDTO Output state 
+#define EXTI_PDETCSR_VDTE_Pos       (8)
+#define EXTI_PDETCSR_VDTE           (0x01U << EXTI_PDETCSR_VDTE_Pos)        ///< VDT Enable 
+#define EXTI_PDETCSR_VDTLS_Pos      (9)
+#define EXTI_PDETCSR_VDTLS0         (0x00U << EXTI_PDETCSR_VDTLS_Pos)       ///< select VDT  0.9V
+#define EXTI_PDETCSR_VDTLS1         (0x01U << EXTI_PDETCSR_VDTLS_Pos)       ///< select VDT  1.0V
+#define EXTI_PDETCSR_VDTLS2         (0x02U << EXTI_PDETCSR_VDTLS_Pos)       ///< select VDT  1.1V
+#define EXTI_PDETCSR_VDTLS3         (0x03U << EXTI_PDETCSR_VDTLS_Pos)       ///< select VDT  1.2V
+#define EXTI_PDETCSR_VBATDIV3_Pos   (11)
+#define EXTI_PDETCSR_VBATDIV3       (0x01U << EXTI_PDETCSR_VBATDIV3_Pos)    ///< PVD Enable 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_VOSDLY Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_EXTI_VOSDLY            (0x3FFU)                               ///< VOS delay time
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_IMR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_IMR_0_Pos              (0)
+#define EXTI_IMR_0                  (0x01U << EXTI_IMR_0_Pos)               ///< Interrupt Mask on line 0
+#define EXTI_IMR_1_Pos              (1)
+#define EXTI_IMR_1                  (0x01U << EXTI_IMR_1_Pos)               ///< Interrupt Mask on line 1
+#define EXTI_IMR_2_Pos              (2)
+#define EXTI_IMR_2                  (0x01U << EXTI_IMR_2_Pos)               ///< Interrupt Mask on line 2
+#define EXTI_IMR_3_Pos              (3)
+#define EXTI_IMR_3                  (0x01U << EXTI_IMR_3_Pos)               ///< Interrupt Mask on line 3
+#define EXTI_IMR_4_Pos              (4)
+#define EXTI_IMR_4                  (0x01U << EXTI_IMR_4_Pos)               ///< Interrupt Mask on line 4
+#define EXTI_IMR_5_Pos              (5)
+#define EXTI_IMR_5                  (0x01U << EXTI_IMR_5_Pos)               ///< Interrupt Mask on line 5
+#define EXTI_IMR_6_Pos              (6)
+#define EXTI_IMR_6                  (0x01U << EXTI_IMR_6_Pos)               ///< Interrupt Mask on line 6
+#define EXTI_IMR_7_Pos              (7)
+#define EXTI_IMR_7                  (0x01U << EXTI_IMR_7_Pos)               ///< Interrupt Mask on line 7
+#define EXTI_IMR_8_Pos              (8)
+#define EXTI_IMR_8                  (0x01U << EXTI_IMR_8_Pos)               ///< Interrupt Mask on line 8
+#define EXTI_IMR_9_Pos              (9)
+#define EXTI_IMR_9                  (0x01U << EXTI_IMR_9_Pos)               ///< Interrupt Mask on line 9
+#define EXTI_IMR_10_Pos             (10)
+#define EXTI_IMR_10                 (0x01U << EXTI_IMR_10_Pos)              ///< Interrupt Mask on line 10
+#define EXTI_IMR_11_Pos             (11)
+#define EXTI_IMR_11                 (0x01U << EXTI_IMR_11_Pos)              ///< Interrupt Mask on line 11
+#define EXTI_IMR_12_Pos             (12)
+#define EXTI_IMR_12                 (0x01U << EXTI_IMR_12_Pos)              ///< Interrupt Mask on line 12
+#define EXTI_IMR_13_Pos             (13)
+#define EXTI_IMR_13                 (0x01U << EXTI_IMR_13_Pos)              ///< Interrupt Mask on line 13
+#define EXTI_IMR_14_Pos             (14)
+#define EXTI_IMR_14                 (0x01U << EXTI_IMR_14_Pos)              ///< Interrupt Mask on line 14
+#define EXTI_IMR_15_Pos             (15)
+#define EXTI_IMR_15                 (0x01U << EXTI_IMR_15_Pos)              ///< Interrupt Mask on line 15
+#define EXTI_IMR_16_Pos             (16)
+#define EXTI_IMR_16                 (0x01U << EXTI_IMR_16_Pos)              ///< Interrupt Mask on line 16
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_EMR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_EMR_0_Pos              (0)
+#define EXTI_EMR_0                  (0x01U << EXTI_EMR_0_Pos)               ///< Event Mask on line 0
+#define EXTI_EMR_1_Pos              (1)
+#define EXTI_EMR_1                  (0x01U << EXTI_EMR_1_Pos)               ///< Event Mask on line 1
+#define EXTI_EMR_2_Pos              (2)
+#define EXTI_EMR_2                  (0x01U << EXTI_EMR_2_Pos)               ///< Event Mask on line 2
+#define EXTI_EMR_3_Pos              (3)
+#define EXTI_EMR_3                  (0x01U << EXTI_EMR_3_Pos)               ///< Event Mask on line 3
+#define EXTI_EMR_4_Pos              (4)
+#define EXTI_EMR_4                  (0x01U << EXTI_EMR_4_Pos)               ///< Event Mask on line 4
+#define EXTI_EMR_5_Pos              (5)
+#define EXTI_EMR_5                  (0x01U << EXTI_EMR_5_Pos)               ///< Event Mask on line 5
+#define EXTI_EMR_6_Pos              (6)
+#define EXTI_EMR_6                  (0x01U << EXTI_EMR_6_Pos)               ///< Event Mask on line 6
+#define EXTI_EMR_7_Pos              (7)
+#define EXTI_EMR_7                  (0x01U << EXTI_EMR_7_Pos)               ///< Event Mask on line 7
+#define EXTI_EMR_8_Pos              (8)
+#define EXTI_EMR_8                  (0x01U << EXTI_EMR_8_Pos)               ///< Event Mask on line 8
+#define EXTI_EMR_9_Pos              (9)
+#define EXTI_EMR_9                  (0x01U << EXTI_EMR_9_Pos)               ///< Event Mask on line 9
+#define EXTI_EMR_10_Pos             (10)
+#define EXTI_EMR_10                 (0x01U << EXTI_EMR_10_Pos)              ///< Event Mask on line 10
+#define EXTI_EMR_11_Pos             (11)
+#define EXTI_EMR_11                 (0x01U << EXTI_EMR_11_Pos)              ///< Event Mask on line 11
+#define EXTI_EMR_12_Pos             (12)
+#define EXTI_EMR_12                 (0x01U << EXTI_EMR_12_Pos)              ///< Event Mask on line 12
+#define EXTI_EMR_13_Pos             (13)
+#define EXTI_EMR_13                 (0x01U << EXTI_EMR_13_Pos)              ///< Event Mask on line 13
+#define EXTI_EMR_14_Pos             (14)
+#define EXTI_EMR_14                 (0x01U << EXTI_EMR_14_Pos)              ///< Event Mask on line 14
+#define EXTI_EMR_15_Pos             (15)
+#define EXTI_EMR_15                 (0x01U << EXTI_EMR_15_Pos)              ///< Event Mask on line 15
+#define EXTI_EMR_16_Pos             (16)
+#define EXTI_EMR_16                 (0x01U << EXTI_EMR_16_Pos)              ///< Event Mask on line 16
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_RTSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_RTSR_0_Pos             (0)
+#define EXTI_RTSR_0                 (0x01U << EXTI_RTSR_0_Pos)              ///< Rising trigger event configuration bit of line 0
+#define EXTI_RTSR_1_Pos             (1)
+#define EXTI_RTSR_1                 (0x01U << EXTI_RTSR_1_Pos)              ///< Rising trigger event configuration bit of line 1
+#define EXTI_RTSR_2_Pos             (2)
+#define EXTI_RTSR_2                 (0x01U << EXTI_RTSR_2_Pos)              ///< Rising trigger event configuration bit of line 2
+#define EXTI_RTSR_3_Pos             (3)
+#define EXTI_RTSR_3                 (0x01U << EXTI_RTSR_3_Pos)              ///< Rising trigger event configuration bit of line 3
+#define EXTI_RTSR_4_Pos             (4)
+#define EXTI_RTSR_4                 (0x01U << EXTI_RTSR_4_Pos)              ///< Rising trigger event configuration bit of line 4
+#define EXTI_RTSR_5_Pos             (5)
+#define EXTI_RTSR_5                 (0x01U << EXTI_RTSR_5_Pos)              ///< Rising trigger event configuration bit of line 5
+#define EXTI_RTSR_6_Pos             (6)
+#define EXTI_RTSR_6                 (0x01U << EXTI_RTSR_6_Pos)              ///< Rising trigger event configuration bit of line 6
+#define EXTI_RTSR_7_Pos             (7)
+#define EXTI_RTSR_7                 (0x01U << EXTI_RTSR_7_Pos)              ///< Rising trigger event configuration bit of line 7
+#define EXTI_RTSR_8_Pos             (8)
+#define EXTI_RTSR_8                 (0x01U << EXTI_RTSR_8_Pos)              ///< Rising trigger event configuration bit of line 8
+#define EXTI_RTSR_9_Pos             (9)
+#define EXTI_RTSR_9                 (0x01U << EXTI_RTSR_9_Pos)              ///< Rising trigger event configuration bit of line 9
+#define EXTI_RTSR_10_Pos            (10)
+#define EXTI_RTSR_10                (0x01U << EXTI_RTSR_10_Pos)             ///< Rising trigger event configuration bit of line 10
+#define EXTI_RTSR_11_Pos            (11)
+#define EXTI_RTSR_11                (0x01U << EXTI_RTSR_11_Pos)             ///< Rising trigger event configuration bit of line 11
+#define EXTI_RTSR_12_Pos            (12)
+#define EXTI_RTSR_12                (0x01U << EXTI_RTSR_12_Pos)             ///< Rising trigger event configuration bit of line 12
+#define EXTI_RTSR_13_Pos            (13)
+#define EXTI_RTSR_13                (0x01U << EXTI_RTSR_13_Pos)             ///< Rising trigger event configuration bit of line 13
+#define EXTI_RTSR_14_Pos            (14)
+#define EXTI_RTSR_14                (0x01U << EXTI_RTSR_14_Pos)             ///< Rising trigger event configuration bit of line 14
+#define EXTI_RTSR_15_Pos            (15)
+#define EXTI_RTSR_15                (0x01U << EXTI_RTSR_15_Pos)             ///< Rising trigger event configuration bit of line 15
+#define EXTI_RTSR_16_Pos            (16)
+#define EXTI_RTSR_16                (0x01U << EXTI_RTSR_16_Pos)             ///< Rising trigger event configuration bit of line 16
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_FTSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_FTSR_0_Pos             (0)
+#define EXTI_FTSR_0                 (0x01U << EXTI_FTSR_0_Pos)              ///< Falling trigger event configuration bit of line 0
+#define EXTI_FTSR_1_Pos             (1)
+#define EXTI_FTSR_1                 (0x01U << EXTI_FTSR_1_Pos)              ///< Falling trigger event configuration bit of line 1
+#define EXTI_FTSR_2_Pos             (2)
+#define EXTI_FTSR_2                 (0x01U << EXTI_FTSR_2_Pos)              ///< Falling trigger event configuration bit of line 2
+#define EXTI_FTSR_3_Pos             (3)
+#define EXTI_FTSR_3                 (0x01U << EXTI_FTSR_3_Pos)              ///< Falling trigger event configuration bit of line 3
+#define EXTI_FTSR_4_Pos             (4)
+#define EXTI_FTSR_4                 (0x01U << EXTI_FTSR_4_Pos)              ///< Falling trigger event configuration bit of line 4
+#define EXTI_FTSR_5_Pos             (5)
+#define EXTI_FTSR_5                 (0x01U << EXTI_FTSR_5_Pos)              ///< Falling trigger event configuration bit of line 5
+#define EXTI_FTSR_6_Pos             (6)
+#define EXTI_FTSR_6                 (0x01U << EXTI_FTSR_6_Pos)              ///< Falling trigger event configuration bit of line 6
+#define EXTI_FTSR_7_Pos             (7)
+#define EXTI_FTSR_7                 (0x01U << EXTI_FTSR_7_Pos)              ///< Falling trigger event configuration bit of line 7
+#define EXTI_FTSR_8_Pos             (8)
+#define EXTI_FTSR_8                 (0x01U << EXTI_FTSR_8_Pos)              ///< Falling trigger event configuration bit of line 8
+#define EXTI_FTSR_9_Pos             (9)
+#define EXTI_FTSR_9                 (0x01U << EXTI_FTSR_9_Pos)              ///< Falling trigger event configuration bit of line 9
+#define EXTI_FTSR_10_Pos            (10)
+#define EXTI_FTSR_10                (0x01U << EXTI_FTSR_10_Pos)             ///< Falling trigger event configuration bit of line 10
+#define EXTI_FTSR_11_Pos            (11)
+#define EXTI_FTSR_11                (0x01U << EXTI_FTSR_11_Pos)             ///< Falling trigger event configuration bit of line 11
+#define EXTI_FTSR_12_Pos            (12)
+#define EXTI_FTSR_12                (0x01U << EXTI_FTSR_12_Pos)             ///< Falling trigger event configuration bit of line 12
+#define EXTI_FTSR_13_Pos            (13)
+#define EXTI_FTSR_13                (0x01U << EXTI_FTSR_13_Pos)             ///< Falling trigger event configuration bit of line 13
+#define EXTI_FTSR_14_Pos            (14)
+#define EXTI_FTSR_14                (0x01U << EXTI_FTSR_14_Pos)             ///< Falling trigger event configuration bit of line 14
+#define EXTI_FTSR_15_Pos            (15)
+#define EXTI_FTSR_15                (0x01U << EXTI_FTSR_15_Pos)             ///< Falling trigger event configuration bit of line 15
+#define EXTI_FTSR_16_Pos            (16)
+#define EXTI_FTSR_16                (0x01U << EXTI_FTSR_16_Pos)             ///< Falling trigger event configuration bit of line 16
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_SWIER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_SWIER_0_Pos            (0)
+#define EXTI_SWIER_0                (0x01U << EXTI_SWIER_0_Pos)             ///< Software Interrupt on line  0
+#define EXTI_SWIER_1_Pos            (1)
+#define EXTI_SWIER_1                (0x01U << EXTI_SWIER_1_Pos)             ///< Software Interrupt on line  1
+#define EXTI_SWIER_2_Pos            (2)
+#define EXTI_SWIER_2                (0x01U << EXTI_SWIER_2_Pos)             ///< Software Interrupt on line  2
+#define EXTI_SWIER_3_Pos            (3)
+#define EXTI_SWIER_3                (0x01U << EXTI_SWIER_3_Pos)             ///< Software Interrupt on line  3
+#define EXTI_SWIER_4_Pos            (4)
+#define EXTI_SWIER_4                (0x01U << EXTI_SWIER_4_Pos)             ///< Software Interrupt on line  4
+#define EXTI_SWIER_5_Pos            (5)
+#define EXTI_SWIER_5                (0x01U << EXTI_SWIER_5_Pos)             ///< Software Interrupt on line  5
+#define EXTI_SWIER_6_Pos            (6)
+#define EXTI_SWIER_6                (0x01U << EXTI_SWIER_6_Pos)             ///< Software Interrupt on line  6
+#define EXTI_SWIER_7_Pos            (7)
+#define EXTI_SWIER_7                (0x01U << EXTI_SWIER_7_Pos)             ///< Software Interrupt on line  7
+#define EXTI_SWIER_8_Pos            (8)
+#define EXTI_SWIER_8                (0x01U << EXTI_SWIER_8_Pos)             ///< Software Interrupt on line  8
+#define EXTI_SWIER_9_Pos            (9)
+#define EXTI_SWIER_9                (0x01U << EXTI_SWIER_9_Pos)             ///< Software Interrupt on line  9
+#define EXTI_SWIER_10_Pos           (10)
+#define EXTI_SWIER_10               (0x01U << EXTI_SWIER_10_Pos)            ///< Software Interrupt on line  10
+#define EXTI_SWIER_11_Pos           (11)
+#define EXTI_SWIER_11               (0x01U << EXTI_SWIER_11_Pos)            ///< Software Interrupt on line  11
+#define EXTI_SWIER_12_Pos           (12)
+#define EXTI_SWIER_12               (0x01U << EXTI_SWIER_12_Pos)            ///< Software Interrupt on line  12
+#define EXTI_SWIER_13_Pos           (13)
+#define EXTI_SWIER_13               (0x01U << EXTI_SWIER_13_Pos)            ///< Software Interrupt on line  13
+#define EXTI_SWIER_14_Pos           (14)
+#define EXTI_SWIER_14               (0x01U << EXTI_SWIER_14_Pos)            ///< Software Interrupt on line  14
+#define EXTI_SWIER_15_Pos           (15)
+#define EXTI_SWIER_15               (0x01U << EXTI_SWIER_15_Pos)            ///< Software Interrupt on line  15
+#define EXTI_SWIER_16_Pos           (16)
+#define EXTI_SWIER_16               (0x01U << EXTI_SWIER_16_Pos)            ///< Software Interrupt on line  16
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief EXTI_PR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define EXTI_PR_0_Pos               (0)
+#define EXTI_PR_0                   (0x01U << EXTI_PR_0_Pos)                ///< Pending bit 0
+#define EXTI_PR_1_Pos               (1)
+#define EXTI_PR_1                   (0x01U << EXTI_PR_1_Pos)                ///< Pending bit 1
+#define EXTI_PR_2_Pos               (2)
+#define EXTI_PR_2                   (0x01U << EXTI_PR_2_Pos)                ///< Pending bit 2
+#define EXTI_PR_3_Pos               (3)
+#define EXTI_PR_3                   (0x01U << EXTI_PR_3_Pos)                ///< Pending bit 3
+#define EXTI_PR_4_Pos               (4)
+#define EXTI_PR_4                   (0x01U << EXTI_PR_4_Pos)                ///< Pending bit 4
+#define EXTI_PR_5_Pos               (5)
+#define EXTI_PR_5                   (0x01U << EXTI_PR_5_Pos)                ///< Pending bit 5
+#define EXTI_PR_6_Pos               (6)
+#define EXTI_PR_6                   (0x01U << EXTI_PR_6_Pos)                ///< Pending bit 6
+#define EXTI_PR_7_Pos               (7)
+#define EXTI_PR_7                   (0x01U << EXTI_PR_7_Pos)                ///< Pending bit 7
+#define EXTI_PR_8_Pos               (8)
+#define EXTI_PR_8                   (0x01U << EXTI_PR_8_Pos)                ///< Pending bit 8
+#define EXTI_PR_9_Pos               (9)
+#define EXTI_PR_9                   (0x01U << EXTI_PR_9_Pos)                ///< Pending bit 9
+#define EXTI_PR_10_Pos              (10)
+#define EXTI_PR_10                  (0x01U << EXTI_PR_10_Pos)               ///< Pending bit 10
+#define EXTI_PR_11_Pos              (11)
+#define EXTI_PR_11                  (0x01U << EXTI_PR_11_Pos)               ///< Pending bit 11
+#define EXTI_PR_12_Pos              (12)
+#define EXTI_PR_12                  (0x01U << EXTI_PR_12_Pos)               ///< Pending bit 12
+#define EXTI_PR_13_Pos              (13)
+#define EXTI_PR_13                  (0x01U << EXTI_PR_13_Pos)               ///< Pending bit 13
+#define EXTI_PR_14_Pos              (14)
+#define EXTI_PR_14                  (0x01U << EXTI_PR_14_Pos)               ///< Pending bit 14
+#define EXTI_PR_15_Pos              (15)
+#define EXTI_PR_15                  (0x01U << EXTI_PR_15_Pos)               ///< Pending bit 15
+#define EXTI_PR_16_Pos              (16)
+#define EXTI_PR_16                  (0x01U << EXTI_PR_16_Pos)               ///< Pending bit 16
+
+
+
+
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h
new file mode 100644
index 000000000..b95acef60
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h
@@ -0,0 +1,290 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_flash.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_FLASH_H
+#define __REG_FLASH_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  MM32 MCU Memory/Peripherals mapping
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_BASE                      (0x08000000U)                           ///< FLASH base address in the alias region
+#define SRAM_BASE                       (0x20000000U)                           ///< SRAM base address in the alias region
+
+#define CACHE_BASE                      (APB2PERIPH_BASE + 0x6000)              ///< Base Address: 0x40016000       
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_REG_BASE                  (AHBPERIPH_BASE + 0x2000)               ///< Base Address: 0x40022000
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OPTB Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OB_BASE                         (0x1FFFF800U)                           ///< Flash Option Bytes base address
+#define PROTECT_BASE                    (0x1FFE0000U)                           ///< Flash Protect Bytes base address
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 ACR;                                                               ///< Access control Register                        offset: 0x00
+    __IO u32 KEYR;                                                              ///< Key Register                                   offset: 0x04
+    __IO u32 OPTKEYR;                                                           ///< Option byte key Register                       offset: 0x08
+    __IO u32 SR;                                                                ///< State Register                                 offset: 0x0C
+    __IO u32 CR;                                                                ///< Control Register                               offset: 0x10
+    __IO u32 AR;                                                                ///< Address Register                               offset: 0x14
+    __IO u32 RESERVED;
+    __IO u32 OBR;                                                               ///< Option bytes Register                          offset: 0x1C
+    __IO u32 WRPR;                                                              ///< Write protect Register                         offset: 0x20
+} FLASH_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  OPT Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u16 RDP;                                                               ///< Read Protect,                                  offset: 0x00
+    __IO u16 USER;                                                              ///< User option byte,                              offset: 0x02
+    __IO u16 Data0;                                                             ///< User data 0,                                   offset: 0x04
+    __IO u16 Data1;                                                             ///< User data 1,                                   offset: 0x06
+    __IO u16 WRP0;                                                              ///< Flash write protection option byte 0,          offset: 0x08
+    __IO u16 WRP1;                                                              ///< Flash write protection option byte 1,          offset: 0x0A
+    __IO u16 WRP2;                                                              ///< Flash write protection option byte 2,          offset: 0x0C
+    __IO u16 WRP3;                                                              ///< Flash write protection option byte 3,          offset: 0x0E
+} OB_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  PROTECT BYTES Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u16 PROTECT_LEN0;                                                      ///< The length of Protect byte 0,                  offset: 0x00
+    __IO u16 PROTECT_ADDR0;                                                     ///< Data of Protect byte 0,                        offset: 0x02
+    __IO u16 PROTECT_LEN1;                                                      ///< The length of Protect byte 1,                  offset: 0x04
+    __IO u16 PROTECT_ADDR1;                                                     ///< Data of Protect byte 1,                        offset: 0x06
+    __IO u16 PROTECT_LEN2;                                                      ///< The length of Protect byte 2,                  offset: 0x08
+    __IO u16 PROTECT_ADDR2;                                                     ///< Data of Protect byte 2,                        offset: 0x0A
+    __IO u16 PROTECT_LEN3;                                                      ///< The length of Protect byte 3,                  offset: 0x0C
+    __IO u16 PROTECT_ADDR3;                                                     ///< Data of Protect byte 3,                        offset: 0x0E
+} PROTECT_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief  CACHE BYTES Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+    __IO u32 CCR;                                                               ///< Configuration and control register              offset: 0x00
+    __IO u32 SR;                                                                ///< Status register                                 offset: 0x04
+    __IO u32 IMR;                                                               ///< Interrupt mask register                         offset: 0x08
+    __IO u32 ISR;                                                               ///< Interrupt status register                       offset: 0x0C
+    __IO u32 RESERVED0;                                                         ///<                                                 offset: 0x10
+    __IO u32 CSHR;                                                              ///< Hit Statistics Register                         offset: 0x14
+    __IO u32 CSMR;                                                              ///< Lost Statistics Register                        offset: 0x18
+} CACHE_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH                           ((FLASH_TypeDef*) FLASH_REG_BASE)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OPTB type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OB                              ((OB_TypeDef*) OB_BASE)
+#define PROTECT                         ((PROTECT_TypeDef*) PROTECT_BASE)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE                           ((CACHE_TypeDef*) CACHE_BASE)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_ACR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_ACR_LATENCY_Pos           (0)
+#define FLASH_ACR_LATENCY               (0x07U << FLASH_ACR_LATENCY_Pos)        ///< LATENCY[2:0] bits (Latency)
+#define FLASH_ACR_LATENCY_0             (0x00U << FLASH_ACR_LATENCY_Pos)        ///< 0 waiting state
+#define FLASH_ACR_LATENCY_1             (0x01U << FLASH_ACR_LATENCY_Pos)        ///< 1 waiting state   
+#define FLASH_ACR_LATENCY_2             (0x02U << FLASH_ACR_LATENCY_Pos)        ///< 2 waiting state
+#define FLASH_ACR_LATENCY_3             (0x03U << FLASH_ACR_LATENCY_Pos)        ///< 3 waiting state
+#define FLASH_ACR_HLFCYA_Pos            (3)
+#define FLASH_ACR_HLFCYA                (0x01U << FLASH_ACR_HLFCYA_Pos)         ///< Flash Half Cycle Access Enable
+#define FLASH_ACR_PRFTBE_Pos            (4)
+#define FLASH_ACR_PRFTBE                (0x01U << FLASH_ACR_PRFTBE_Pos)         ///< Prefetch Buffer Enable
+#define FLASH_ACR_PRFTBS_Pos            (5)
+#define FLASH_ACR_PRFTBS                (0x01U << FLASH_ACR_PRFTBS_Pos)         ///< Prefetch Buffer Status
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_KEYR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_KEYR_FKEY_Pos             (0)
+#define FLASH_KEYR_FKEY                 (0xFFFFFFFFU << FLASH_KEYR_FKEY_Pos)    ///< FLASH Key
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_OPTKEYR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_OPTKEYR_OPTKEY_Pos        (0)
+#define FLASH_OPTKEYR_OPTKEY            (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEY_Pos)   ///< Option Byte Key
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_SR_BUSY_Pos               (0)
+#define FLASH_SR_BUSY                   (0x01U << FLASH_SR_BUSY_Pos)            ///< Busy
+#define FLASH_SR_PGERR_Pos              (2)
+#define FLASH_SR_PGERR                  (0x01U << FLASH_SR_PGERR_Pos)           ///< Programming Error
+#define FLASH_SR_WRPRTERR_Pos           (4)
+#define FLASH_SR_WRPRTERR               (0x01U << FLASH_SR_WRPRTERR_Pos)        ///< Write Protection Error
+#define FLASH_SR_EOP_Pos                (5)
+#define FLASH_SR_EOP                    (0x01U << FLASH_SR_EOP_Pos)             ///< End of operation
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_CR_PG_Pos                 (0)
+#define FLASH_CR_PG                     (0x01U << FLASH_CR_PG_Pos)              ///< Programming
+#define FLASH_CR_PER_Pos                (1)
+#define FLASH_CR_PER                    (0x01U << FLASH_CR_PER_Pos)             ///< Page Erase
+#define FLASH_CR_MER_Pos                (2)
+#define FLASH_CR_MER                    (0x01U << FLASH_CR_MER_Pos)             ///< Mass Erase
+#define FLASH_CR_OPTPG_Pos              (4)
+#define FLASH_CR_OPTPG                  (0x01U << FLASH_CR_OPTPG_Pos)           ///< Option Byte Programming
+#define FLASH_CR_OPTER_Pos              (5)
+#define FLASH_CR_OPTER                  (0x01U << FLASH_CR_OPTER_Pos)           ///< Option Byte Erase
+#define FLASH_CR_STRT_Pos               (6)
+#define FLASH_CR_STRT                   (0x01U << FLASH_CR_STRT_Pos)            ///< Start
+#define FLASH_CR_LOCK_Pos               (7)
+#define FLASH_CR_LOCK                   (0x01U << FLASH_CR_LOCK_Pos)            ///< Lock
+#define FLASH_CR_OPTWRE_Pos             (9)
+#define FLASH_CR_OPTWRE                 (0x01U << FLASH_CR_OPTWRE_Pos)          ///< Option Bytes Write Enable
+#define FLASH_CR_ERRIE_Pos              (10)
+#define FLASH_CR_ERRIE                  (0x01U << FLASH_CR_ERRIE_Pos)           ///< Error Interrupt Enable
+#define FLASH_CR_EOPIE_Pos              (12)
+#define FLASH_CR_EOPIE                  (0x01U << FLASH_CR_EOPIE_Pos)           ///< End of operation interrupt enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_AR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_AR_FAR_Pos                (0)
+#define FLASH_AR_FAR                    (0xFFFFFFFFU << FLASH_AR_FAR_Pos)       ///< Flash Address
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_OBR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_OBR_OPTERR_Pos            (0)
+#define FLASH_OBR_OPTERR                (0x01U << FLASH_OBR_OPTERR_Pos)         ///< Option Byte Error
+#define FLASH_OBR_RDPRT_Pos             (1)
+#define FLASH_OBR_RDPRT                 (0x01U << FLASH_OBR_RDPRT_Pos)         ///< Read protection level status
+#define FLASH_OBR_USER_Pos              (2)
+#define FLASH_OBR_USER                  (0xFFU << FLASH_OBR_USER_Pos)           ///< User Option Bytes
+
+#define FLASH_OBR_WDG_SW                (0x01U << FLASH_OBR_USER_Pos)           ///< WDG_SW
+#define FLASH_OBR_RST_STOP              (0x02U << FLASH_OBR_USER_Pos)           ///< nRST_STOP
+#define FLASH_OBR_RST_STDBY             (0x04U << FLASH_OBR_USER_Pos)           ///< nRST_STDBY
+
+
+#define FLASH_OBR_Data0_Pos             (10)
+#define FLASH_OBR_Data0                 (0xFFU << FLASH_OBR_Data0_Pos)          ///< User data storage option byte
+#define FLASH_OBR_Data1_Pos             (18)
+#define FLASH_OBR_Data1                 (0xFFU << FLASH_OBR_Data1_Pos)          ///< User data storage option byte
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH_WRPR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FLASH_WRPR_WRP_Pos              (0)
+#define FLASH_WRPR_WRP                  (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos)     ///< Write Protect
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_CCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_CCR_EN_Pos               (0)
+#define CACHE_CCR_EN                   (0x01U << CACHE_CCR_EN_Pos)              ///< Cache Enable
+#define CACHE_CCR_INV_Pos              (1)
+#define CACHE_CCR_INV                  (0x01U << CACHE_CCR_INV_REQ_Pos)         ///< Manually invalidate the request
+#define CACHE_CCR_POW_Pos              (2)
+#define CACHE_CCR_POW                  (0x01U << CACHE_CCR_POW_REQ_Pos)         ///< Manual SRAM power request
+#define CACHE_CCR_MAN_POW_Pos          (3)
+#define CACHE_CCR_MAN_POW              (0x01U << CACHE_CCR_MAN_POW_Pos)         ///< Set manual or automatic SRAM power request
+#define CACHE_CCR_MAN_INV_Pos          (4)
+#define CACHE_CCR_MAN_INV              (0x01U << CACHE_CCR_MAN_INV_Pos)         ///< Manually or automatically disable it
+#define CACHE_CCR_PREFETCH_Pos         (5)
+#define CACHE_CCR_PREFETCH             (0x01U << CACHE_CCR_PREFETCH_Pos)        ///< Prefetch function
+#define CACHE_CCR_STATISTIC_Pos        (6)
+#define CACHE_CCR_STATISTIC            (0x01U << CACHE_CCR_STATISTIC_Pos)       ///< Statistics enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_SR_CS_Pos               (0)
+#define CACHE_SR_CS0                  (0x00U << CACHE_CCR_CS_Pos)              ///< Cache is disabled
+#define CACHE_SR_CS1                  (0x01U << CACHE_CCR_CS_Pos)              ///< Cache is being enabled
+#define CACHE_SR_CS2                  (0x02U << CACHE_CCR_CS_Pos)              ///< Cache is enabled
+#define CACHE_SR_CS3                  (0x03U << CACHE_CCR_CS_Pos)              ///< Cache is being disabled
+#define CACHE_SR_INV_Pos              (2)
+#define CACHE_SR_INV                  (0x01U << CACHE_CCR_INV_REQ_Pos)         ///< Invalidation status
+#define CACHE_SR_POW_Pos              (4)
+#define CACHE_SR_POW                  (0x01U << CACHE_CCR_POW_REQ_Pos)         ///< SRAM power response
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_IMR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_IMR_MAN_INV_Pos          (0)
+#define CACHE_IMR_MAN_INV              (0x01U << CACHE_IMR_MAN_INV_Pos)        ///< Mask the interrupt request of manual invalidation error
+#define CACHE_IMR_POW_Pos              (1)
+#define CACHE_IMR_POW                  (0x01U << CACHE_IMR_POW_Pos)            ///< Mask the interrupt request of power supply error 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_ISR_MAN_INV_Pos          (0)
+#define CACHE_ISR_MAN_INV              (0x01U << CACHE_ISR_MAN_INV_Pos)        ///< Manual invalidation of error flags
+#define CACHE_ISR_POW_Pos              (1)
+#define CACHE_ISR_POW                  (0x01U << CACHE_ISR_POW_Pos)            ///< SRAM power error flags 
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_CSHR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_CSHR                     (0xFFFFU )                              ///< Cache  Hits
+////////////////////////////////////////////////////////////////////////////////
+/// @brief CACHE_CSHR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define CACHE_CSMR                     (0xFFFFU )                              ///< Cache  Lost times
+
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h
new file mode 100644
index 000000000..77870dd1e
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h
@@ -0,0 +1,194 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_fsmc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_FSMC_H
+#define __REG_FSMC_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FLASH Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define FSMC_BANK1_ADDR       (0x60000000UL )
+#define FSMC_BANK2_ADDR       (0x60000000UL + 0x4000000 )
+#define FSMC_BANK3_ADDR       (0x60000000UL + 0x8000000 )
+#define FSMC_BANK4_ADDR       (0x60000000UL + 0xc000000 )
+#define FSMC_BASE             (0x60000000UL + 0x40000000)                      ///< Base Address: 0xA0000000
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+    __IO u32 Reservedoffset0x00;                                                ///< Reserved Register                              offset: 0x00
+    __IO u32 Reservedoffset0x04;                                                ///< Reserved Register                              offset: 0x04
+    __IO u32 Reservedoffset0x08;                                                ///< Reserved Register                              offset: 0x08
+    __IO u32 Reservedoffset0x0c;                                                ///< Reserved Register                              offset: 0x0c
+    __IO u32 Reservedoffset0x10;                                                ///< Reserved Register                              offset: 0x10
+    __IO u32 Reservedoffset0x14;                                                ///< Reserved Register                              offset: 0x14
+    __IO u32 Reservedoffset0x18;                                                ///< Reserved Register                              offset: 0x18
+    __IO u32 Reservedoffset0x1c;                                                ///< Reserved Register                              offset: 0x1c
+    __IO u32 Reservedoffset0x20;                                                ///< Reserved Register                              offset: 0x20
+    __IO u32 Reservedoffset0x24;                                                ///< Reserved Register                              offset: 0x24
+    __IO u32 Reservedoffset0x28;                                                ///< Reserved Register                              offset: 0x28
+    __IO u32 Reservedoffset0x2c;                                                ///< Reserved Register                              offset: 0x2c
+    __IO u32 Reservedoffset0x30;                                                ///< Reserved Register                              offset: 0x30
+    __IO u32 Reservedoffset0x34;                                                ///< Reserved Register                              offset: 0x34
+    __IO u32 Reservedoffset0x38;                                                ///< Reserved Register                              offset: 0x38
+    __IO u32 Reservedoffset0x3c;                                                ///< Reserved Register                              offset: 0x3c
+    __IO u32 Reservedoffset0x40;                                                ///< Reserved Register                              offset: 0x40
+    __IO u32 Reservedoffset0x44;                                                ///< Reserved Register                              offset: 0x44
+    __IO u32 Reservedoffset0x48;                                                ///< Reserved Register                              offset: 0x48
+    __IO u32 Reservedoffset0x4c;                                                ///< Reserved Register                              offset: 0x4c
+    __IO u32 Reservedoffset0x50;                                                ///< Reserved Register                              offset: 0x50
+    __IO u32 SMSKR;                                                             ///< SMSKR control Register                         offset: 0x54
+    __IO u32 Reservedoffset0x58;                                                ///< Reserved Register                              offset: 0x58
+    __IO u32 Reservedoffset0x5c;                                                ///< Reserved Register                              offset: 0x5c
+    __IO u32 Reservedoffset0x60;                                                ///< Reserved Register                              offset: 0x60
+    __IO u32 Reservedoffset0x64;                                                ///< Reserved Register                              offset: 0x64
+    __IO u32 Reservedoffset0x68;                                                ///< Reserved Register                              offset: 0x68
+    __IO u32 Reservedoffset0x6c;                                                ///< Reserved Register                              offset: 0x6c
+    __IO u32 Reservedoffset0x70;                                                ///< Reserved Register                              offset: 0x70
+    __IO u32 Reservedoffset0x74;                                                ///< Reserved Register                              offset: 0x74
+    __IO u32 Reservedoffset0x78;                                                ///< Reserved Register                              offset: 0x78
+    __IO u32 Reservedoffset0x7c;                                                ///< Reserved Register                              offset: 0x7c
+    __IO u32 Reservedoffset0x80;                                                ///< Reserved Register                              offset: 0x80
+    __IO u32 Reservedoffset0x84;                                                ///< Reserved Register                              offset: 0x84
+    __IO u32 Reservedoffset0x88;                                                ///< Reserved Register                              offset: 0x88
+    __IO u32 Reservedoffset0x8c;                                                ///< Reserved Register                              offset: 0x8c
+    __IO u32 Reservedoffset0x90;                                                ///< Reserved Register                              offset: 0x90
+    __IO u32 SMTMGR_SET0;                                                       ///< SMTMGR_SET Register 0                          offset: 0x94
+    __IO u32 SMTMGR_SET1;                                                       ///< SMTMGR_SET Register 1                          offset: 0x98
+    __IO u32 SMTMGR_SET2;                                                       ///< SMTMGR_SET Register 2                          offset: 0x9c
+    __IO u32 Reservedoffset0xA0;                                                ///< Reserved Register                              offset: 0xa0
+    __IO u32 SMCTLR;                                                            ///< Reserved Register                              offset: 0xa4
+    __IO u32 Reservedoffset0xA8;                                                ///< Reserved Register                              offset: 0xa8
+    __IO u32 Reservedoffset0xAC;                                                ///< Reserved Register                              offset: 0xac
+} FSMC_TypeDef;
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC  type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FSMC                            ((FSMC_TypeDef*) FSMC_BASE)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC_SMSKR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FSMC_SMSKR_REG_SELECT_Pos          (8)
+#define FSMC_SMSKR_REG_SELECT0             (0x00U << FSMC_SMSKR_REG_SELECT_Pos)        ///< timing parameter configures the register group 0
+#define FSMC_SMSKR_REG_SELECT1             (0x01U << FSMC_SMSKR_REG_SELECT_Pos)        ///< timing parameter configures the register group 1
+#define FSMC_SMSKR_REG_SELECT2             (0x02U << FSMC_SMSKR_REG_SELECT_Pos)        ///< timing parameter configures the register group 2
+#define FSMC_SMSKR_MEM_TYPE_Pos            (5)
+#define FSMC_SMSKR_MEM_TYPE0               (0x00U << FSMC_SMSKR_MEM_TYPE_Pos)        ///< SDRAM
+#define FSMC_SMSKR_MEM_TYPE1               (0x01U << FSMC_SMSKR_MEM_TYPE_Pos)        ///< SRAM
+#define FSMC_SMSKR_MEM_TYPE2               (0x02U << FSMC_SMSKR_MEM_TYPE_Pos)        ///< FLASH
+#define FSMC_SMSKR_MEM_SIZE_Pos            (0)
+#define FSMC_SMSKR_MEM_SIZE_64K            (0x01U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 64KB
+#define FSMC_SMSKR_MEM_SIZE_128K           (0x02U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 128KB
+#define FSMC_SMSKR_MEM_SIZE_256K           (0x03U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 256KB
+#define FSMC_SMSKR_MEM_SIZE_512K           (0x04U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 512KB
+#define FSMC_SMSKR_MEM_SIZE_1M             (0x05U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 1MB
+#define FSMC_SMSKR_MEM_SIZE_2M             (0x06U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 2MB
+#define FSMC_SMSKR_MEM_SIZE_4M             (0x07U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 4MB
+#define FSMC_SMSKR_MEM_SIZE_8M             (0x08U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 8MB
+#define FSMC_SMSKR_MEM_SIZE_16M            (0x09U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 16MB
+#define FSMC_SMSKR_MEM_SIZE_32M            (0x10U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 32MB
+#define FSMC_SMSKR_MEM_SIZE_64M            (0x11U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 64MB
+#define FSMC_SMSKR_MEM_SIZE_128M           (0x12U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 128MB
+#define FSMC_SMSKR_MEM_SIZE_256M           (0x13U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 256MB
+#define FSMC_SMSKR_MEM_SIZE_512M           (0x14U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 512MB
+#define FSMC_SMSKR_MEM_SIZE_1G             (0x15U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 1GB
+#define FSMC_SMSKR_MEM_SIZE_2G             (0x16U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 2GB
+#define FSMC_SMSKR_MEM_SIZE_4G             (0x17U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 4GB
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC_SMTMGR_SET0/1/2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FSMC_SMTMGR_SET_SM_READ_PIPE_Pos          (28)
+#define FSMC_SMTMGR_SET_SM_READ_PIPE              (0x03U << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)          ///< The period of the latched read data 
+#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos  (27)
+#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE      (0x01U << FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos)  ///< Access low frequency synchronization devices
+#define FSMC_SMTMGR_SET_READ_MODE_Pos             (26)
+#define FSMC_SMTMGR_SET_READ_MODE                 (0x01U << FSMC_SMTMGR_SET_READ_MODE_Pos)             ///< The Hready_RESP signal is from an external DEVICE
+#define FSMC_SMTMGR_SET_T_WP_Pos                  (10)
+#define FSMC_SMTMGR_SET_T_WP                      (0x3FU << FSMC_SMTMGR_SET_T_WP_Pos)                  ///< Write pulse width 64 clock cycles
+#define FSMC_SMTMGR_SET_T_WR_Pos                  (8)
+#define FSMC_SMTMGR_SET_T_WR                      (0x03U << FSMC_SMTMGR_SET_T_WR_Pos)                  ///< Address/data retention time for write operations is 3 clock cycles
+#define FSMC_SMTMGR_SET_T_AS_Pos                  (6)
+#define FSMC_SMTMGR_SET_T_AS                      (0x03U << FSMC_SMTMGR_SET_T_AS_Pos)                  ///< The address establishment time of write operation is 3 clock cycles
+#define FSMC_SMTMGR_SET_T_RC_Pos                  (0)
+#define FSMC_SMTMGR_SET_T_RC                      (0x3FU << FSMC_SMTMGR_SET_T_RC_Pos)                  ///< Read operation cycle 64 clock cycles
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief FSMC_SMCTLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos          (13)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2              (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_16           (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)          ///< Memory data bus bit width 16  bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_32           (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)          ///< Memory data bus bit width 32  bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_64           (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)          ///< Memory data bus bit width 64  bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_128          (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)          ///< Memory data bus bit width 128 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_8            (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)          ///< Memory data bus bit width 8   bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos          (10)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1              (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_16           (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)          ///< Memory data bus bit width 16  bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_32           (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)          ///< Memory data bus bit width 32  bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_64           (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)          ///< Memory data bus bit width 64  bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_128          (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)          ///< Memory data bus bit width 128 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_8            (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)          ///< Memory data bus bit width 8   bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos          (7)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0              (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_16           (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)          ///< Memory data bus bit width 16  bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_32           (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)          ///< Memory data bus bit width 32  bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_64           (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)          ///< Memory data bus bit width 64  bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_128          (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)          ///< Memory data bus bit width 128 bits
+#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_8            (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)          ///< Memory data bus bit width 8   bits
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__REG_FSMC_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h
new file mode 100644
index 000000000..44e043bac
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h
@@ -0,0 +1,706 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_gpio.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_GPIO_H
+#define __REG_GPIO_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define GPIOA_BASE                  (AHBPERIPH_BASE + 0x0020000)                ///< Base Address: 0x40040000
+#define GPIOB_BASE                  (AHBPERIPH_BASE + 0x0020400)                ///< Base Address: 0x40040400
+#define GPIOC_BASE                  (AHBPERIPH_BASE + 0x0020800)                ///< Base Address: 0x40040800
+#define GPIOD_BASE                  (AHBPERIPH_BASE + 0x0020C00)                ///< Base Address: 0x40040C00
+#define GPIOE_BASE                  (AHBPERIPH_BASE + 0x0021000)                ///< Base Address: 0x40041000
+#define GPIOF_BASE                  (AHBPERIPH_BASE + 0x0021400)                ///< Base Address: 0x40041400
+#define GPIOG_BASE                  (AHBPERIPH_BASE + 0x0021800)                ///< Base Address: 0x40041800
+#define GPIOH_BASE                  (AHBPERIPH_BASE + 0x0021C00)                ///< Base Address: 0x40041C00
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 CRL;                                                               ///< Control Register Low,                          offset: 0x00
+    __IO u32 CRH;                                                               ///< Control Register High,                         offset: 0x04
+    __IO u32 IDR;                                                               ///< Input Data Register,                           offset: 0x08
+    __IO u32 ODR;                                                               ///< Output Data Register,                          offset: 0x0C
+    __IO u32 BSRR;                                                              ///< Bit Set or Reset Register,                     offset: 0x10
+    __IO u32 BRR;                                                               ///< Bit Reset Register,                            offset: 0x14
+    __IO u32 LCKR;                                                              ///< Lock Register,                                 offset: 0x18
+    __IO u32 DCR;                                                               ///< Pin Output Open Drain Config Register,         offset: 0x1C
+    __IO u32 AFRL;                                                              ///< Port Multiplexing Function Low Register,       offset: 0x20
+    __IO u32 AFRH;                                                              ///< Port Multiplexing Function High Register,      offset: 0x24
+} GPIO_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIOA                           ((GPIO_TypeDef*) GPIOA_BASE)
+#define GPIOB                           ((GPIO_TypeDef*) GPIOB_BASE)
+#define GPIOC                           ((GPIO_TypeDef*) GPIOC_BASE)
+#define GPIOD                           ((GPIO_TypeDef*) GPIOD_BASE)
+#define GPIOE                           ((GPIO_TypeDef*) GPIOE_BASE)
+#define GPIOF                           ((GPIO_TypeDef*) GPIOF_BASE)
+#define GPIOG                           ((GPIO_TypeDef*) GPIOG_BASE)
+#define GPIOH                           ((GPIO_TypeDef*) GPIOH_BASE)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO Common Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+#define GPIO_CNF_MODE_AIN             0x00UL //0b0000,                                ///< Analog input
+#define GPIO_CNF_MODE_FLOATING        0x04UL //0b0100,                                ///< Floating input
+#define GPIO_CNF_MODE_INPUPD          0x08UL //0b1000,                                ///< Pull up and down input
+#define GPIO_CNF_MODE_INRESEVED       0x0CUL //0b1100,                                ///< Reseved input mode
+#define GPIO_CNF_MODE_OUT_PP          0x01UL //0b0001,                                ///< Universal push-pull  output default
+#define GPIO_CNF_MODE_OUT_OD          0x05UL //0b0101,                                ///< Universal open drain output default
+#define GPIO_CNF_MODE_AF_PP           0x09UL //0b1001,                                ///< Multiplex push-pull  output default
+#define GPIO_CNF_MODE_AF_OD           0x0DUL //0b1101                                 ///< Multiplex open drain output default
+#define GPIO_CNF_MODE_50MHZ_OUT_PP    0x01UL //0b0001,                                ///< Universal push-pull  output 50MHZ
+#define GPIO_CNF_MODE_50MHZ_OUT_OD    0x05UL //0b0101,                                ///< Universal open drain output 50MHZ
+#define GPIO_CNF_MODE_50MHZ_AF_PP     0x09UL //0b1001,                                ///< Multiplex push-pull  output 50MHZ
+#define GPIO_CNF_MODE_50MHZ_AF_OD     0x0DUL //0b1101                                 ///< Multiplex open drain output 50MHZ
+#define GPIO_CNF_MODE_20MHZ_OUT_PP    0x02UL //0b0010,                                ///< Universal push-pull  output 20MHZ
+#define GPIO_CNF_MODE_20MHZ_OUT_OD    0x06UL //0b0110,                                ///< Universal open drain output 20MHZ
+#define GPIO_CNF_MODE_20MHZ_AF_PP     0x0AUL //0b1010,                                ///< Multiplex push-pull  output 20MHZ
+#define GPIO_CNF_MODE_20MHZ_AF_OD     0x0EUL //0b1110                                 ///< Multiplex open drain output 20MHZ
+#define GPIO_CNF_MODE_10MHZ_OUT_PP    0x03UL //0b0011,                                ///< Universal push-pull  output 10MHZ
+#define GPIO_CNF_MODE_10MHZ_OUT_OD    0x07UL //0b0111,                                ///< Universal open drain output 10MHZ
+#define GPIO_CNF_MODE_10MHZ_AF_PP     0x0BUL //0b1011,                                ///< Multiplex push-pull  output 10MHZ
+#define GPIO_CNF_MODE_10MHZ_AF_OD     0x0FUL //0b1111                                 ///< Multiplex open drain output 10MHZ
+#define GPIO_CNF_MODE_MASK            0x0FUL //0b1111
+
+#define GPIO_CRL_CNF_MODE_0_Pos       (0)  //                                       ///< Analog input
+#define GPIO_CRL_CNF_MODE_1_Pos       (4)  //                                       ///< Floating input
+#define GPIO_CRL_CNF_MODE_2_Pos       (8)  //                                       ///< Pull up and down input
+#define GPIO_CRL_CNF_MODE_3_Pos       (12) //                                       ///< Reseved input mode
+#define GPIO_CRL_CNF_MODE_4_Pos       (16) //                                       ///< Universal push-pull  output default
+#define GPIO_CRL_CNF_MODE_5_Pos       (20) //                                       ///< Universal open drain output default
+#define GPIO_CRL_CNF_MODE_6_Pos       (24) //                                       ///< Multiplex push-pull  output default
+#define GPIO_CRL_CNF_MODE_7_Pos       (28) //                                       ///< Multiplex open drain output default
+#define GPIO_CRH_CNF_MODE_8_Pos       (0)  //                                       ///< Universal push-pull  output 50MHZ
+#define GPIO_CRH_CNF_MODE_9_Pos       (4)  //                                       ///< Universal open drain output 50MHZ
+#define GPIO_CRH_CNF_MODE_10_Pos      (8)  //                                       ///< Multiplex push-pull  output 50MHZ
+#define GPIO_CRH_CNF_MODE_11_Pos      (12) //                                       ///< Multiplex open drain output 50MHZ
+#define GPIO_CRH_CNF_MODE_12_Pos      (16) //                                       ///< Universal push-pull  output 20MHZ
+#define GPIO_CRH_CNF_MODE_13_Pos      (20) //                                       ///< Universal open drain output 20MHZ
+#define GPIO_CRH_CNF_MODE_14_Pos      (24) //                                       ///< Multiplex push-pull  output 20MHZ
+#define GPIO_CRH_CNF_MODE_15_Pos      (28) //                                       ///< Multiplex open drain output 20MHZ
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_CRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_CRL_MODE                   ((u32)0x33333333)                       ///< Port x mode bits
+
+#define GPIO_CRL_MODE0_Pos              (0)
+#define GPIO_CRL_MODE0                  (0x03U << GPIO_CRL_MODE0_Pos)           ///< MODE0[1:0] bits (portx mode bits, pin 0)
+#define GPIO_CRL_MODE0_0                (0x01U << GPIO_CRL_MODE0_Pos)           ///< Bit 0
+#define GPIO_CRL_MODE0_1                (0x02U << GPIO_CRL_MODE0_Pos)           ///< Bit 1
+
+#define GPIO_CRL_CNF0_Pos               (2)
+#define GPIO_CRL_CNF0                   (0x03U << GPIO_CRL_CNF0_Pos)            ///< CNF0[1:0] bits (portx configuration bits, pin 0)
+#define GPIO_CRL_CNF0_0                 (0x01U << GPIO_CRL_CNF0_Pos)            ///< Bit 0
+#define GPIO_CRL_CNF0_1                 (0x02U << GPIO_CRL_CNF0_Pos)            ///< Bit 1
+
+#define GPIO_CRL_MODE1_Pos              (4)
+#define GPIO_CRL_MODE1                  (0x03U << GPIO_CRL_MODE1_Pos)           ///< MODE1[1:0] bits (portx mode bits, pin 1)
+#define GPIO_CRL_MODE1_0                (0x01U << GPIO_CRL_MODE1_Pos)           ///< Bit 0
+#define GPIO_CRL_MODE1_1                (0x02U << GPIO_CRL_MODE1_Pos)           ///< Bit 1
+
+#define GPIO_CRL_CNF1_Pos               (6)
+#define GPIO_CRL_CNF1                   (0x03U << GPIO_CRL_CNF1_Pos)            ///< CNF1[1:0] bits (portx configuration bits, pin 1)
+#define GPIO_CRL_CNF1_0                 (0x01U << GPIO_CRL_CNF1_Pos)            ///< Bit 0
+#define GPIO_CRL_CNF1_1                 (0x02U << GPIO_CRL_CNF1_Pos)            ///< Bit 1
+
+#define GPIO_CRL_MODE2_Pos              (8)
+#define GPIO_CRL_MODE2                  (0x03U << GPIO_CRL_MODE2_Pos)           ///< MODE2[1:0] bits (portx mode bits, pin 2)
+#define GPIO_CRL_MODE2_0                (0x01U << GPIO_CRL_MODE2_Pos)           ///< Bit 0
+#define GPIO_CRL_MODE2_1                (0x02U << GPIO_CRL_MODE2_Pos)           ///< Bit 1
+
+#define GPIO_CRL_CNF2_Pos               (10)
+#define GPIO_CRL_CNF2                   (0x03U << GPIO_CRL_CNF2_Pos)            ///< CNF2[1:0] bits (portx configuration bits, pin 2)
+#define GPIO_CRL_CNF2_0                 (0x01U << GPIO_CRL_CNF2_Pos)            ///< Bit 0
+#define GPIO_CRL_CNF2_1                 (0x02U << GPIO_CRL_CNF2_Pos)            ///< Bit 1
+
+#define GPIO_CRL_MODE3_Pos              (12)
+#define GPIO_CRL_MODE3                  (0x03U << GPIO_CRL_MODE3_Pos)           ///< MODE3[1:0] bits (portx mode bits, pin 3)
+#define GPIO_CRL_MODE3_0                (0x01U << GPIO_CRL_MODE3_Pos)           ///< Bit 0
+#define GPIO_CRL_MODE3_1                (0x02U << GPIO_CRL_MODE3_Pos)           ///< Bit 1
+
+#define GPIO_CRL_CNF3_Pos               (14)
+#define GPIO_CRL_CNF3                   (0x03U << GPIO_CRL_CNF3_Pos)            ///< CNF3[1:0] bits (portx configuration bits, pin 3)
+#define GPIO_CRL_CNF3_0                 (0x01U << GPIO_CRL_CNF3_Pos)            ///< Bit 0
+#define GPIO_CRL_CNF3_1                 (0x02U << GPIO_CRL_CNF3_Pos)            ///< Bit 1
+
+
+#define GPIO_CRL_MODE4_Pos              (16)
+#define GPIO_CRL_MODE4                  (0x03U << GPIO_CRL_MODE4_Pos)           ///< MODE4[1:0] bits (portx mode bits, pin 4)
+#define GPIO_CRL_MODE4_0                (0x01U << GPIO_CRL_MODE4_Pos)           ///< Bit 0
+#define GPIO_CRL_MODE4_1                (0x02U << GPIO_CRL_MODE4_Pos)           ///< Bit 1
+
+#define GPIO_CRL_CNF4_Pos               (18)
+#define GPIO_CRL_CNF4                   (0x03U << GPIO_CRL_CNF4_Pos)            ///< CNF4[1:0] bits (portx configuration bits, pin 4)
+#define GPIO_CRL_CNF4_0                 (0x01U << GPIO_CRL_CNF4_Pos)            ///< Bit 0
+#define GPIO_CRL_CNF4_1                 (0x02U << GPIO_CRL_CNF4_Pos)            ///< Bit 1
+
+#define GPIO_CRL_MODE5_Pos              (20)
+#define GPIO_CRL_MODE5                  (0x03U << GPIO_CRL_MODE5_Pos)           ///< MODE5[1:0] bits (portx mode bits, pin 5)
+#define GPIO_CRL_MODE5_0                (0x01U << GPIO_CRL_MODE5_Pos)           ///< Bit 0
+#define GPIO_CRL_MODE5_1                (0x02U << GPIO_CRL_MODE5_Pos)           ///< Bit 1
+
+#define GPIO_CRL_CNF5_Pos               (22)
+#define GPIO_CRL_CNF5                   (0x03U << GPIO_CRL_CNF5_Pos)            ///< CNF5[1:0] bits (portx configuration bits, pin 5)
+#define GPIO_CRL_CNF5_0                 (0x01U << GPIO_CRL_CNF5_Pos)            ///< Bit 0
+#define GPIO_CRL_CNF5_1                 (0x02U << GPIO_CRL_CNF5_Pos)            ///< Bit 1
+
+#define GPIO_CRL_MODE6_Pos              (24)
+#define GPIO_CRL_MODE6                  (0x03U << GPIO_CRL_MODE6_Pos)           ///< MODE6[1:0] bits (portx mode bits, pin 6)
+#define GPIO_CRL_MODE6_0                (0x01U << GPIO_CRL_MODE6_Pos)           ///< Bit 0
+#define GPIO_CRL_MODE6_1                (0x02U << GPIO_CRL_MODE6_Pos)           ///< Bit 1
+
+#define GPIO_CRL_CNF6_Pos               (26)
+#define GPIO_CRL_CNF6                   (0x03U << GPIO_CRL_CNF6_Pos)            ///< CNF6[1:0] bits (portx configuration bits, pin 6)
+#define GPIO_CRL_CNF6_0                 (0x01U << GPIO_CRL_CNF6_Pos)            ///< Bit 0
+#define GPIO_CRL_CNF6_1                 (0x02U << GPIO_CRL_CNF6_Pos)            ///< Bit 1
+
+#define GPIO_CRL_MODE7_Pos              (28)
+#define GPIO_CRL_MODE7                  (0x03U << GPIO_CRL_MODE7_Pos)           ///< MODE7[1:0] bits (portx mode bits, pin 7)
+#define GPIO_CRL_MODE7_0                (0x01U << GPIO_CRL_MODE7_Pos)           ///< Bit 0
+#define GPIO_CRL_MODE7_1                (0x02U << GPIO_CRL_MODE7_Pos)           ///< Bit 1
+
+#define GPIO_CRL_CNF7_Pos               (30)
+#define GPIO_CRL_CNF7                   (0x03U << GPIO_CRL_CNF7_Pos)            ///< CNF7[1:0] bits (portx configuration bits, pin 7)
+#define GPIO_CRL_CNF7_0                 (0x01U << GPIO_CRL_CNF7_Pos)            ///< Bit 0
+#define GPIO_CRL_CNF7_1                 (0x02U << GPIO_CRL_CNF7_Pos)            ///< Bit 1
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_CRH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_CRH_MODE                   ((u32)0x33333333)                       ///< Port x mode bits
+
+#define GPIO_CRH_MODE8_Pos              (0)
+#define GPIO_CRH_MODE8                  (0x03U << GPIO_CRH_MODE8_Pos)           ///< MODE8[1:0] bits (portx mode bits, pin 0)
+#define GPIO_CRH_MODE8_0                (0x01U << GPIO_CRH_MODE8_Pos)           ///< Bit 0
+#define GPIO_CRH_MODE8_1                (0x02U << GPIO_CRH_MODE8_Pos)           ///< Bit 1
+#define GPIO_CRH_CNF8_Pos               (2)
+#define GPIO_CRH_CNF8                   (0x03U << GPIO_CRH_CNF8_Pos)            ///< CNF8[1:0] bits (portx configuration bits, pin 0)
+#define GPIO_CRH_CNF8_0                 (0x01U << GPIO_CRH_CNF8_Pos)            ///< Bit 0
+#define GPIO_CRH_CNF8_1                 (0x02U << GPIO_CRH_CNF8_Pos)            ///< Bit 1
+#define GPIO_CRH_MODE9_Pos              (4)
+#define GPIO_CRH_MODE9                  (0x03U << GPIO_CRH_MODE9_Pos)           ///< MODE9[1:0] bits (portx mode bits, pin 1)
+#define GPIO_CRH_MODE9_0                (0x01U << GPIO_CRH_MODE9_Pos)           ///< Bit 0
+#define GPIO_CRH_MODE9_1                (0x02U << GPIO_CRH_MODE9_Pos)           ///< Bit 1
+#define GPIO_CRH_CNF9_Pos               (6)
+#define GPIO_CRH_CNF9                   (0x03U << GPIO_CRH_CNF9_Pos)            ///< CNF9[1:0] bits (portx configuration bits, pin 1)
+#define GPIO_CRH_CNF9_0                 (0x01U << GPIO_CRH_CNF9_Pos)            ///< Bit 0
+#define GPIO_CRH_CNF9_1                 (0x02U << GPIO_CRH_CNF9_Pos)            ///< Bit 1
+#define GPIO_CRH_MODE10_Pos             (8)
+#define GPIO_CRH_MODE10                 (0x03U << GPIO_CRH_MODE10_Pos)          ///< MODE10[1:0] bits (portx mode bits, pin 2)
+#define GPIO_CRH_MODE10_0               (0x01U << GPIO_CRH_MODE10_Pos)          ///< Bit 0
+#define GPIO_CRH_MODE10_1               (0x02U << GPIO_CRH_MODE10_Pos)          ///< Bit 1
+#define GPIO_CRH_CNF10_Pos              (10)
+#define GPIO_CRH_CNF10                  (0x03U << GPIO_CRH_CNF10_Pos)           ///< CNF10[1:0] bits (portx configuration bits, pin 2)
+#define GPIO_CRH_CNF10_0                (0x01U << GPIO_CRH_CNF10_Pos)           ///< Bit 0
+#define GPIO_CRH_CNF10_1                (0x02U << GPIO_CRH_CNF10_Pos)           ///< Bit 1
+#define GPIO_CRH_MODE11_Pos             (12)
+#define GPIO_CRH_MODE11                 (0x03U << GPIO_CRH_MODE11_Pos)          ///< MODE11[1:0] bits (portx mode bits, pin 3)
+#define GPIO_CRH_MODE11_0               (0x01U << GPIO_CRH_MODE11_Pos)          ///< Bit 0
+#define GPIO_CRH_MODE11_1               (0x02U << GPIO_CRH_MODE11_Pos)          ///< Bit 1
+#define GPIO_CRH_CNF11_Pos              (14)
+#define GPIO_CRH_CNF11                  (0x03U << GPIO_CRH_CNF11_Pos)           ///< CNF11[1:0] bits (portx configuration bits, pin 3)
+#define GPIO_CRH_CNF11_0                (0x01U << GPIO_CRH_CNF11_Pos)           ///< Bit 0
+#define GPIO_CRH_CNF11_1                (0x02U << GPIO_CRH_CNF11_Pos)           ///< Bit 1
+#define GPIO_CRH_MODE12_Pos             (16)
+#define GPIO_CRH_MODE12                 (0x03U << GPIO_CRH_MODE12_Pos)          ///< MODE12[1:0] bits (portx mode bits, pin 4)
+#define GPIO_CRH_MODE12_0               (0x01U << GPIO_CRH_MODE12_Pos)          ///< Bit 0
+#define GPIO_CRH_MODE12_1               (0x02U << GPIO_CRH_MODE12_Pos)          ///< Bit 1
+#define GPIO_CRH_CNF12_Pos              (18)
+#define GPIO_CRH_CNF12                  (0x03U << GPIO_CRH_CNF12_Pos)           ///< CNF12[1:0] bits (portx configuration bits, pin 4)
+#define GPIO_CRH_CNF12_0                (0x01U << GPIO_CRH_CNF12_Pos)           ///< Bit 0
+#define GPIO_CRH_CNF12_1                (0x02U << GPIO_CRH_CNF12_Pos)           ///< Bit 1
+#define GPIO_CRH_MODE13_Pos             (20)
+#define GPIO_CRH_MODE13                 (0x03U << GPIO_CRH_MODE13_Pos)          ///< MODE13[1:0] bits (portx mode bits, pin 5)
+#define GPIO_CRH_MODE13_0               (0x01U << GPIO_CRH_MODE13_Pos)          ///< Bit 0
+#define GPIO_CRH_MODE13_1               (0x02U << GPIO_CRH_MODE13_Pos)          ///< Bit 1
+#define GPIO_CRH_CNF13_Pos              (22)
+#define GPIO_CRH_CNF13                  (0x03U << GPIO_CRH_CNF13_Pos)           ///< CNF13[1:0] bits (portx configuration bits, pin 5)
+#define GPIO_CRH_CNF13_0                (0x01U << GPIO_CRH_CNF13_Pos)           ///< Bit 0
+#define GPIO_CRH_CNF13_1                (0x02U << GPIO_CRH_CNF13_Pos)           ///< Bit 1
+#define GPIO_CRH_MODE14_Pos             (24)
+#define GPIO_CRH_MODE14                 (0x03U << GPIO_CRH_MODE14_Pos)          ///< MODE14[1:0] bits (portx mode bits, pin 6)
+#define GPIO_CRH_MODE14_0               (0x01U << GPIO_CRH_MODE14_Pos)          ///< Bit 0
+#define GPIO_CRH_MODE14_1               (0x02U << GPIO_CRH_MODE14_Pos)          ///< Bit 1
+#define GPIO_CRH_CNF14_Pos              (26)
+#define GPIO_CRH_CNF14                  (0x03U << GPIO_CRH_CNF14_Pos)           ///< CNF14[1:0] bits (portx configuration bits, pin 6)
+#define GPIO_CRH_CNF14_0                (0x01U << GPIO_CRH_CNF14_Pos)           ///< Bit 0
+#define GPIO_CRH_CNF14_1                (0x02U << GPIO_CRH_CNF14_Pos)           ///< Bit 1
+#define GPIO_CRH_MODE15_Pos             (28)
+#define GPIO_CRH_MODE15                 (0x03U << GPIO_CRH_MODE15_Pos)          ///< MODE15[1:0] bits (portx mode bits, pin 7)
+#define GPIO_CRH_MODE15_0               (0x01U << GPIO_CRH_MODE15_Pos)          ///< Bit 0
+#define GPIO_CRH_MODE15_1               (0x02U << GPIO_CRH_MODE15_Pos)          ///< Bit 1
+#define GPIO_CRH_CNF15_Pos              (30)
+#define GPIO_CRH_CNF15                  (0x03U << GPIO_CRH_CNF15_Pos)           ///< CNF15[1:0] bits (portx configuration bits, pin 7)
+#define GPIO_CRH_CNF15_0                (0x01U << GPIO_CRH_CNF15_Pos)           ///< Bit 0
+#define GPIO_CRH_CNF15_1                (0x02U << GPIO_CRH_CNF15_Pos)           ///< Bit 1
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_IDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_IDR_DATA_Pos               (0)
+#define GPIO_IDR_DATA                   (0xFFFFU << GPIO_IDR_DATA_Pos)          ///< Port input data
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_IDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_IDR_IDR0_Pos               (0)
+#define GPIO_IDR_IDR0                   (0x01U << GPIO_IDR_IDR0_Pos)            ///< Portx Set bit 0
+#define GPIO_IDR_IDR1_Pos               (1)
+#define GPIO_IDR_IDR1                   (0x01U << GPIO_IDR_IDR1_Pos)            ///< Portx Set bit 1
+#define GPIO_IDR_IDR2_Pos               (2)
+#define GPIO_IDR_IDR2                   (0x01U << GPIO_IDR_IDR2_Pos)            ///< Portx Set bit 2
+#define GPIO_IDR_IDR3_Pos               (3)
+#define GPIO_IDR_IDR3                   (0x01U << GPIO_IDR_IDR3_Pos)            ///< Portx Set bit 3
+#define GPIO_IDR_IDR4_Pos               (4)
+#define GPIO_IDR_IDR4                   (0x01U << GPIO_IDR_IDR4_Pos)            ///< Portx Set bit 4
+#define GPIO_IDR_IDR5_Pos               (5)
+#define GPIO_IDR_IDR5                   (0x01U << GPIO_IDR_IDR5_Pos)            ///< Portx Set bit 5
+#define GPIO_IDR_IDR6_Pos               (6)
+#define GPIO_IDR_IDR6                   (0x01U << GPIO_IDR_IDR6_Pos)            ///< Portx Set bit 6
+#define GPIO_IDR_IDR7_Pos               (7)
+#define GPIO_IDR_IDR7                   (0x01U << GPIO_IDR_IDR7_Pos)            ///< Portx Set bit 7
+#define GPIO_IDR_IDR8_Pos               (8)
+#define GPIO_IDR_IDR8                   (0x01U << GPIO_IDR_IDR8_Pos)            ///< Portx Set bit 8
+#define GPIO_IDR_IDR9_Pos               (9)
+#define GPIO_IDR_IDR9                   (0x01U << GPIO_IDR_IDR9_Pos)            ///< Portx Set bit 9
+#define GPIO_IDR_IDR10_Pos              (10)
+#define GPIO_IDR_IDR10                  (0x01U << GPIO_IDR_IDR10_Pos)           ///< Portx Set bit 10
+#define GPIO_IDR_IDR11_Pos              (11)
+#define GPIO_IDR_IDR11                  (0x01U << GPIO_IDR_IDR11_Pos)           ///< Portx Set bit 11
+#define GPIO_IDR_IDR12_Pos              (12)
+#define GPIO_IDR_IDR12                  (0x01U << GPIO_IDR_IDR12_Pos)           ///< Portx Set bit 12
+#define GPIO_IDR_IDR13_Pos              (13)
+#define GPIO_IDR_IDR13                  (0x01U << GPIO_IDR_IDR13_Pos)           ///< Portx Set bit 13
+#define GPIO_IDR_IDR14_Pos              (14)
+#define GPIO_IDR_IDR14                  (0x01U << GPIO_IDR_IDR14_Pos)           ///< Portx Set bit 14
+#define GPIO_IDR_IDR15_Pos              (15)
+#define GPIO_IDR_IDR15                  (0x01U << GPIO_IDR_IDR15_Pos)           ///< Portx Set bit 15
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_ODR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_ODR_DATA_Pos               (0)
+#define GPIO_ODR_DATA                   (0xFFFF << GPIO_ODR_DATA_Pos)           ///< Port output data
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_ODR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_ODR_ODR0_Pos               (0)
+#define GPIO_ODR_ODR0                   (0x01U << GPIO_ODR_ODR0_Pos)            ///< Portx Set bit 0
+#define GPIO_ODR_ODR1_Pos               (1)
+#define GPIO_ODR_ODR1                   (0x01U << GPIO_ODR_ODR1_Pos)            ///< Portx Set bit 1
+#define GPIO_ODR_ODR2_Pos               (2)
+#define GPIO_ODR_ODR2                   (0x01U << GPIO_ODR_ODR2_Pos)            ///< Portx Set bit 2
+#define GPIO_ODR_ODR3_Pos               (3)
+#define GPIO_ODR_ODR3                   (0x01U << GPIO_ODR_ODR3_Pos)            ///< Portx Set bit 3
+#define GPIO_ODR_ODR4_Pos               (4)
+#define GPIO_ODR_ODR4                   (0x01U << GPIO_ODR_ODR4_Pos)            ///< Portx Set bit 4
+#define GPIO_ODR_ODR5_Pos               (5)
+#define GPIO_ODR_ODR5                   (0x01U << GPIO_ODR_ODR5_Pos)            ///< Portx Set bit 5
+#define GPIO_ODR_ODR6_Pos               (6)
+#define GPIO_ODR_ODR6                   (0x01U << GPIO_ODR_ODR6_Pos)            ///< Portx Set bit 6
+#define GPIO_ODR_ODR7_Pos               (7)
+#define GPIO_ODR_ODR7                   (0x01U << GPIO_ODR_ODR7_Pos)            ///< Portx Set bit 7
+#define GPIO_ODR_ODR8_Pos               (8)
+#define GPIO_ODR_ODR8                   (0x01U << GPIO_ODR_ODR8_Pos)            ///< Portx Set bit 8
+#define GPIO_ODR_ODR9_Pos               (9)
+#define GPIO_ODR_ODR9                   (0x01U << GPIO_ODR_ODR9_Pos)            ///< Portx Set bit 9
+#define GPIO_ODR_ODR10_Pos              (10)
+#define GPIO_ODR_ODR10                  (0x01U << GPIO_ODR_ODR10_Pos)           ///< Portx Set bit 10
+#define GPIO_ODR_ODR11_Pos              (11)
+#define GPIO_ODR_ODR11                  (0x01U << GPIO_ODR_ODR11_Pos)           ///< Portx Set bit 11
+#define GPIO_ODR_ODR12_Pos              (12)
+#define GPIO_ODR_ODR12                  (0x01U << GPIO_ODR_ODR12_Pos)           ///< Portx Set bit 12
+#define GPIO_ODR_ODR13_Pos              (13)
+#define GPIO_ODR_ODR13                  (0x01U << GPIO_ODR_ODR13_Pos)           ///< Portx Set bit 13
+#define GPIO_ODR_ODR14_Pos              (14)
+#define GPIO_ODR_ODR14                  (0x01U << GPIO_ODR_ODR14_Pos)           ///< Portx Set bit 14
+#define GPIO_ODR_ODR15_Pos              (15)
+#define GPIO_ODR_ODR15                  (0x01U << GPIO_ODR_ODR15_Pos)           ///< Portx Set bit 15
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_BRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_BSRR_BS_Pos                (0)
+#define GPIO_BSRR_BS                    (0xFFFFU << GPIO_BSRR_BS_Pos)            ///< Portx Reset
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_BSRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_BSRR_BS0_Pos               (0)
+#define GPIO_BSRR_BS0                   (0x01U << GPIO_BSRR_BS0_Pos)            ///< Portx Set bit 0
+#define GPIO_BSRR_BS1_Pos               (1)
+#define GPIO_BSRR_BS1                   (0x01U << GPIO_BSRR_BS1_Pos)            ///< Portx Set bit 1
+#define GPIO_BSRR_BS2_Pos               (2)
+#define GPIO_BSRR_BS2                   (0x01U << GPIO_BSRR_BS2_Pos)            ///< Portx Set bit 2
+#define GPIO_BSRR_BS3_Pos               (3)
+#define GPIO_BSRR_BS3                   (0x01U << GPIO_BSRR_BS3_Pos)            ///< Portx Set bit 3
+#define GPIO_BSRR_BS4_Pos               (4)
+#define GPIO_BSRR_BS4                   (0x01U << GPIO_BSRR_BS4_Pos)            ///< Portx Set bit 4
+#define GPIO_BSRR_BS5_Pos               (5)
+#define GPIO_BSRR_BS5                   (0x01U << GPIO_BSRR_BS5_Pos)            ///< Portx Set bit 5
+#define GPIO_BSRR_BS6_Pos               (6)
+#define GPIO_BSRR_BS6                   (0x01U << GPIO_BSRR_BS6_Pos)            ///< Portx Set bit 6
+#define GPIO_BSRR_BS7_Pos               (7)
+#define GPIO_BSRR_BS7                   (0x01U << GPIO_BSRR_BS7_Pos)            ///< Portx Set bit 7
+#define GPIO_BSRR_BS8_Pos               (8)
+#define GPIO_BSRR_BS8                   (0x01U << GPIO_BSRR_BS8_Pos)            ///< Portx Set bit 8
+#define GPIO_BSRR_BS9_Pos               (9)
+#define GPIO_BSRR_BS9                   (0x01U << GPIO_BSRR_BS9_Pos)            ///< Portx Set bit 9
+#define GPIO_BSRR_BS10_Pos              (10)
+#define GPIO_BSRR_BS10                  (0x01U << GPIO_BSRR_BS10_Pos)           ///< Portx Set bit 10
+#define GPIO_BSRR_BS11_Pos              (11)
+#define GPIO_BSRR_BS11                  (0x01U << GPIO_BSRR_BS11_Pos)           ///< Portx Set bit 11
+#define GPIO_BSRR_BS12_Pos              (12)
+#define GPIO_BSRR_BS12                  (0x01U << GPIO_BSRR_BS12_Pos)           ///< Portx Set bit 12
+#define GPIO_BSRR_BS13_Pos              (13)
+#define GPIO_BSRR_BS13                  (0x01U << GPIO_BSRR_BS13_Pos)           ///< Portx Set bit 13
+#define GPIO_BSRR_BS14_Pos              (14)
+#define GPIO_BSRR_BS14                  (0x01U << GPIO_BSRR_BS14_Pos)           ///< Portx Set bit 14
+#define GPIO_BSRR_BS15_Pos              (15)
+#define GPIO_BSRR_BS15                  (0x01U << GPIO_BSRR_BS15_Pos)           ///< Portx Set bit 15
+
+#define GPIO_BSRR_BR0_Pos               (16)
+#define GPIO_BSRR_BR0                   (0x01U << GPIO_BSRR_BR0_Pos)            ///< Portx Reset bit 0
+#define GPIO_BSRR_BR1_Pos               (17)
+#define GPIO_BSRR_BR1                   (0x01U << GPIO_BSRR_BR1_Pos)            ///< Portx Reset bit 1
+#define GPIO_BSRR_BR2_Pos               (18)
+#define GPIO_BSRR_BR2                   (0x01U << GPIO_BSRR_BR2_Pos)            ///< Portx Reset bit 2
+#define GPIO_BSRR_BR3_Pos               (19)
+#define GPIO_BSRR_BR3                   (0x01U << GPIO_BSRR_BR3_Pos)            ///< Portx Reset bit 3
+#define GPIO_BSRR_BR4_Pos               (20)
+#define GPIO_BSRR_BR4                   (0x01U << GPIO_BSRR_BR4_Pos)            ///< Portx Reset bit 4
+#define GPIO_BSRR_BR5_Pos               (21)
+#define GPIO_BSRR_BR5                   (0x01U << GPIO_BSRR_BR5_Pos)            ///< Portx Reset bit 5
+#define GPIO_BSRR_BR6_Pos               (22)
+#define GPIO_BSRR_BR6                   (0x01U << GPIO_BSRR_BR6_Pos)            ///< Portx Reset bit 6
+#define GPIO_BSRR_BR7_Pos               (23)
+#define GPIO_BSRR_BR7                   (0x01U << GPIO_BSRR_BR7_Pos)            ///< Portx Reset bit 7
+#define GPIO_BSRR_BR8_Pos               (24)
+#define GPIO_BSRR_BR8                   (0x01U << GPIO_BSRR_BR8_Pos)            ///< Portx Reset bit 8
+#define GPIO_BSRR_BR9_Pos               (25)
+#define GPIO_BSRR_BR9                   (0x01U << GPIO_BSRR_BR9_Pos)            ///< Portx Reset bit 9
+#define GPIO_BSRR_BR10_Pos              (26)
+#define GPIO_BSRR_BR10                  (0x01U << GPIO_BSRR_BR10_Pos)           ///< Portx Reset bit 10
+#define GPIO_BSRR_BR11_Pos              (27)
+#define GPIO_BSRR_BR11                  (0x01U << GPIO_BSRR_BR11_Pos)           ///< Portx Reset bit 11
+#define GPIO_BSRR_BR12_Pos              (28)
+#define GPIO_BSRR_BR12                  (0x01U << GPIO_BSRR_BR12_Pos)           ///< Portx Reset bit 12
+#define GPIO_BSRR_BR13_Pos              (29)
+#define GPIO_BSRR_BR13                  (0x01U << GPIO_BSRR_BR13_Pos)           ///< Portx Reset bit 13
+#define GPIO_BSRR_BR14_Pos              (30)
+#define GPIO_BSRR_BR14                  (0x01U << GPIO_BSRR_BR14_Pos)           ///< Portx Reset bit 14
+#define GPIO_BSRR_BR15_Pos              (31)
+#define GPIO_BSRR_BR15                  (0x01U << GPIO_BSRR_BR15_Pos)           ///< Portx Reset bit 15
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_BRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_BRR_BR_Pos                 (0)
+#define GPIO_BRR_BR                     (0xFFFFU << GPIO_BRR_BR_Pos)            ///< Portx Reset
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_BRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_BRR_BR0_Pos               (0)
+#define GPIO_BRR_BR0                   (0x01U << GPIO_BRR_BR0_Pos)            ///< Portx Set bit 0
+#define GPIO_BRR_BR1_Pos               (1)
+#define GPIO_BRR_BR1                   (0x01U << GPIO_BRR_BR1_Pos)            ///< Portx Set bit 1
+#define GPIO_BRR_BR2_Pos               (2)
+#define GPIO_BRR_BR2                   (0x01U << GPIO_BRR_BR2_Pos)            ///< Portx Set bit 2
+#define GPIO_BRR_BR3_Pos               (3)
+#define GPIO_BRR_BR3                   (0x01U << GPIO_BRR_BR3_Pos)            ///< Portx Set bit 3
+#define GPIO_BRR_BR4_Pos               (4)
+#define GPIO_BRR_BR4                   (0x01U << GPIO_BRR_BR4_Pos)            ///< Portx Set bit 4
+#define GPIO_BRR_BR5_Pos               (5)
+#define GPIO_BRR_BR5                   (0x01U << GPIO_BRR_BR5_Pos)            ///< Portx Set bit 5
+#define GPIO_BRR_BR6_Pos               (6)
+#define GPIO_BRR_BR6                   (0x01U << GPIO_BRR_BR6_Pos)            ///< Portx Set bit 6
+#define GPIO_BRR_BR7_Pos               (7)
+#define GPIO_BRR_BR7                   (0x01U << GPIO_BRR_BR7_Pos)            ///< Portx Set bit 7
+#define GPIO_BRR_BR8_Pos               (8)
+#define GPIO_BRR_BR8                   (0x01U << GPIO_BRR_BR8_Pos)            ///< Portx Set bit 8
+#define GPIO_BRR_BR9_Pos               (9)
+#define GPIO_BRR_BR9                   (0x01U << GPIO_BRR_BR9_Pos)            ///< Portx Set bit 9
+#define GPIO_BRR_BR10_Pos              (10)
+#define GPIO_BRR_BR10                  (0x01U << GPIO_BRR_BR10_Pos)           ///< Portx Set bit 10
+#define GPIO_BRR_BR11_Pos              (11)
+#define GPIO_BRR_BR11                  (0x01U << GPIO_BRR_BR11_Pos)           ///< Portx Set bit 11
+#define GPIO_BRR_BR12_Pos              (12)
+#define GPIO_BRR_BR12                  (0x01U << GPIO_BRR_BR12_Pos)           ///< Portx Set bit 12
+#define GPIO_BRR_BR13_Pos              (13)
+#define GPIO_BRR_BR13                  (0x01U << GPIO_BRR_BR13_Pos)           ///< Portx Set bit 13
+#define GPIO_BRR_BR14_Pos              (14)
+#define GPIO_BRR_BR14                  (0x01U << GPIO_BRR_BR14_Pos)           ///< Portx Set bit 14
+#define GPIO_BRR_BR15_Pos              (15)
+#define GPIO_BRR_BR15                  (0x01U << GPIO_BRR_BR15_Pos)           ///< Portx Set bit 15
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_LCKR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_LCKR_LCK_Pos               (0)
+#define GPIO_LCKR_LCK                   (0xFFFFU << GPIO_LCKR_LCK_Pos)          ///< Portx Lock
+#define GPIO_LCKR_LCKK_Pos              (16)
+#define GPIO_LCKR_LCKK                  (0x01U << GPIO_LCKR_LCKK_Pos)           ///< Lock key
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_LCKR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_LCKR_LCK0_Pos               (0)
+#define GPIO_LCKR_LCK0                   (0x01U << GPIO_LCKR_LCK0_Pos)          ///< Portx Set bit 0
+#define GPIO_LCKR_LCK1_Pos               (1)
+#define GPIO_LCKR_LCK1                   (0x01U << GPIO_LCKR_LCK1_Pos)          ///< Portx Set bit 1
+#define GPIO_LCKR_LCK2_Pos               (2)
+#define GPIO_LCKR_LCK2                   (0x01U << GPIO_LCKR_LCK2_Pos)          ///< Portx Set bit 2
+#define GPIO_LCKR_LCK3_Pos               (3)
+#define GPIO_LCKR_LCK3                   (0x01U << GPIO_LCKR_LCK3_Pos)          ///< Portx Set bit 3
+#define GPIO_LCKR_LCK4_Pos               (4)
+#define GPIO_LCKR_LCK4                   (0x01U << GPIO_LCKR_LCK4_Pos)          ///< Portx Set bit 4
+#define GPIO_LCKR_LCK5_Pos               (5)
+#define GPIO_LCKR_LCK5                   (0x01U << GPIO_LCKR_LCK5_Pos)          ///< Portx Set bit 5
+#define GPIO_LCKR_LCK6_Pos               (6)
+#define GPIO_LCKR_LCK6                   (0x01U << GPIO_LCKR_LCK6_Pos)          ///< Portx Set bit 6
+#define GPIO_LCKR_LCK7_Pos               (7)
+#define GPIO_LCKR_LCK7                   (0x01U << GPIO_LCKR_LCK7_Pos)          ///< Portx Set bit 7
+#define GPIO_LCKR_LCK8_Pos               (8)
+#define GPIO_LCKR_LCK8                   (0x01U << GPIO_LCKR_LCK8_Pos)          ///< Portx Set bit 8
+#define GPIO_LCKR_LCK9_Pos               (9)
+#define GPIO_LCKR_LCK9                   (0x01U << GPIO_LCKR_LCK9_Pos)          ///< Portx Set bit 9
+#define GPIO_LCKR_LCK10_Pos              (10)
+#define GPIO_LCKR_LCK10                  (0x01U << GPIO_LCKR_LCK10_Pos)         ///< Portx Set bit 10
+#define GPIO_LCKR_LCK11_Pos              (11)
+#define GPIO_LCKR_LCK11                  (0x01U << GPIO_LCKR_LCK11_Pos)         ///< Portx Set bit 11
+#define GPIO_LCKR_LCK12_Pos              (12)
+#define GPIO_LCKR_LCK12                  (0x01U << GPIO_LCKR_LCK12_Pos)         ///< Portx Set bit 12
+#define GPIO_LCKR_LCK13_Pos              (13)
+#define GPIO_LCKR_LCK13                  (0x01U << GPIO_LCKR_LCK13_Pos)         ///< Portx Set bit 13
+#define GPIO_LCKR_LCK14_Pos              (14)
+#define GPIO_LCKR_LCK14                  (0x01U << GPIO_LCKR_LCK14_Pos)         ///< Portx Set bit 14
+#define GPIO_LCKR_LCK15_Pos              (15)
+#define GPIO_LCKR_LCK15                  (0x01U << GPIO_LCKR_LCK15_Pos)         ///< Portx Set bit 15
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_DCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_DCR_PX0_Pos                (0)
+#define GPIO_DCR_PX0                    (0x03U << GPIO_DCR_PX0_Pos)                  ///< PX0[1:0] bits (pinx configuration bits, pin 0)
+#define GPIO_DCR_PX0_MODE0              (0x00U << GPIO_DCR_PX0_Pos)                  ///< Mode = 0
+#define GPIO_DCR_PX0_MODE1              (0x01U << GPIO_DCR_PX0_Pos)                  ///< Mode = 1
+#define GPIO_DCR_PX0_MODE2              (0x02U << GPIO_DCR_PX0_Pos)                  ///< Mode = 2
+#define GPIO_DCR_PX0_MODE3              (0x03U << GPIO_DCR_PX0_Pos)                  ///< Mode = 3
+#define GPIO_DCR_PX1_Pos                (2)
+#define GPIO_DCR_PX1                    (0x03U << GPIO_DCR_PX1_Pos)                  ///< PX1[1:0] bits (pinx configuration bits, pin 1)
+#define GPIO_DCR_PX1_MODE0              (0x00U << GPIO_DCR_PX1_Pos)                  ///< Mode = 0
+#define GPIO_DCR_PX1_MODE1              (0x01U << GPIO_DCR_PX1_Pos)                  ///< Mode = 1
+#define GPIO_DCR_PX1_MODE2              (0x02U << GPIO_DCR_PX1_Pos)                  ///< Mode = 2
+#define GPIO_DCR_PX1_MODE3              (0x03U << GPIO_DCR_PX1_Pos)                  ///< Mode = 3
+#define GPIO_DCR_PX2_Pos                (4)
+#define GPIO_DCR_PX2                    (0x03U << GPIO_DCR_PX2_Pos)                  ///< PX2[1:0] bits (pinx configuration bits, pin 2)
+#define GPIO_DCR_PX2_MODE0              (0x00U << GPIO_DCR_PX2_Pos)                  ///< Mode = 0
+#define GPIO_DCR_PX2_MODE1              (0x01U << GPIO_DCR_PX2_Pos)                  ///< Mode = 1
+#define GPIO_DCR_PX2_MODE2              (0x02U << GPIO_DCR_PX2_Pos)                  ///< Mode = 2
+#define GPIO_DCR_PX2_MODE3              (0x03U << GPIO_DCR_PX2_Pos)                  ///< Mode = 3
+#define GPIO_DCR_PX3_Pos                (6)
+#define GPIO_DCR_PX3                    (0x03U << GPIO_DCR_PX3_Pos)                  ///< PX3[1:0] bits (pinx configuration bits, pin 3)
+#define GPIO_DCR_PX3_MODE0              (0x00U << GPIO_DCR_PX3_Pos)                  ///< Mode = 0
+#define GPIO_DCR_PX3_MODE1              (0x01U << GPIO_DCR_PX3_Pos)                  ///< Mode = 1
+#define GPIO_DCR_PX3_MODE2              (0x02U << GPIO_DCR_PX3_Pos)                  ///< Mode = 2
+#define GPIO_DCR_PX3_MODE3              (0x03U << GPIO_DCR_PX3_Pos)                  ///< Mode = 3
+
+#define GPIO_DCR_PX4_Pos                (8)
+#define GPIO_DCR_PX4                    (0x03U << GPIO_DCR_PX4_Pos)                  ///< PX4[1:0] bits (pinx configuration bits, pin 4)
+#define GPIO_DCR_PX4_MODE0              (0x00U << GPIO_DCR_PX4_Pos)                  ///< Mode = 0
+#define GPIO_DCR_PX4_MODE1              (0x01U << GPIO_DCR_PX4_Pos)                  ///< Mode = 1
+#define GPIO_DCR_PX4_MODE2              (0x02U << GPIO_DCR_PX4_Pos)                  ///< Mode = 2
+#define GPIO_DCR_PX4_MODE3              (0x03U << GPIO_DCR_PX4_Pos)                  ///< Mode = 3
+
+#define GPIO_DCR_PX5_Pos                (10)
+#define GPIO_DCR_PX5                    (0x03U << GPIO_DCR_PX5_Pos)                  ///< PX5[1:0] bits (pinx configuration bits, pin 5)
+#define GPIO_DCR_PX5_MODE0              (0x00U << GPIO_DCR_PX5_Pos)                  ///< Mode = 0
+#define GPIO_DCR_PX5_MODE1              (0x01U << GPIO_DCR_PX5_Pos)                  ///< Mode = 1
+#define GPIO_DCR_PX5_MODE2              (0x02U << GPIO_DCR_PX5_Pos)                  ///< Mode = 2
+#define GPIO_DCR_PX5_MODE3              (0x03U << GPIO_DCR_PX5_Pos)                  ///< Mode = 3
+
+#define GPIO_DCR_PX6_Pos                (12)
+#define GPIO_DCR_PX6                    (0x03U << GPIO_DCR_PX6_Pos)                  ///< PX6[1:0] bits (pinx configuration bits, pin 6)
+#define GPIO_DCR_PX6_MODE0              (0x00U << GPIO_DCR_PX6_Pos)                  ///< Mode = 0
+#define GPIO_DCR_PX6_MODE1              (0x01U << GPIO_DCR_PX6_Pos)                  ///< Mode = 1
+#define GPIO_DCR_PX6_MODE2              (0x02U << GPIO_DCR_PX6_Pos)                  ///< Mode = 2
+#define GPIO_DCR_PX6_MODE3              (0x03U << GPIO_DCR_PX6_Pos)                  ///< Mode = 3
+
+#define GPIO_DCR_PX7_Pos                (14)
+#define GPIO_DCR_PX7                    (0x03U << GPIO_DCR_PX7_Pos)                  ///< PX7[1:0] bits (pinx configuration bits, pin 7)
+#define GPIO_DCR_PX7_MODE0              (0x00U << GPIO_DCR_PX7_Pos)                  ///< Mode = 0
+#define GPIO_DCR_PX7_MODE1              (0x01U << GPIO_DCR_PX7_Pos)                  ///< Mode = 1
+#define GPIO_DCR_PX7_MODE2              (0x02U << GPIO_DCR_PX7_Pos)                  ///< Mode = 2
+#define GPIO_DCR_PX7_MODE3              (0x03U << GPIO_DCR_PX7_Pos)                  ///< Mode = 3
+
+#define GPIO_DCR_PX8_Pos                (16)
+#define GPIO_DCR_PX8                    (0x03U << GPIO_DCR_PX8_Pos)                  ///< PX8[1:0] bits (pinx configuration bits, pin 8)
+#define GPIO_DCR_PX8_MODE0              (0x00U << GPIO_DCR_PX8_Pos)                  ///< Mode = 0
+#define GPIO_DCR_PX8_MODE1              (0x01U << GPIO_DCR_PX8_Pos)                  ///< Mode = 1
+#define GPIO_DCR_PX8_MODE2              (0x02U << GPIO_DCR_PX8_Pos)                  ///< Mode = 2
+#define GPIO_DCR_PX8_MODE3              (0x03U << GPIO_DCR_PX8_Pos)                  ///< Mode = 3
+
+#define GPIO_DCR_PX9_Pos                (18)
+#define GPIO_DCR_PX9                    (0x03U << GPIO_DCR_PX9_Pos)                  ///< PX9[1:0] bits (pinx configuration bits, pin 9)
+#define GPIO_DCR_PX9_MODE0              (0x00U << GPIO_DCR_PX9_Pos)                  ///< Mode = 0
+#define GPIO_DCR_PX9_MODE1              (0x01U << GPIO_DCR_PX9_Pos)                  ///< Mode = 1
+#define GPIO_DCR_PX9_MODE2              (0x02U << GPIO_DCR_PX9_Pos)                  ///< Mode = 2
+#define GPIO_DCR_PX9_MODE3              (0x03U << GPIO_DCR_PX9_Pos)                  ///< Mode = 3
+
+#define GPIO_DCR_PX10_Pos               (20)
+#define GPIO_DCR_PX10                   (0x03U << GPIO_DCR_PX10_Pos)                 ///< PX10[1:0] bits (pinx configuration bits, pin 10)
+#define GPIO_DCR_PX10_MODE0             (0x00U << GPIO_DCR_PX10_Pos)                 ///< Mode = 0
+#define GPIO_DCR_PX10_MODE1             (0x01U << GPIO_DCR_PX10_Pos)                 ///< Mode = 1
+#define GPIO_DCR_PX10_MODE2             (0x02U << GPIO_DCR_PX10_Pos)                 ///< Mode = 2
+#define GPIO_DCR_PX10_MODE3             (0x03U << GPIO_DCR_PX10_Pos)                 ///< Mode = 3
+
+#define GPIO_DCR_PX11_Pos               (22)
+#define GPIO_DCR_PX11                   (0x03U << GPIO_DCR_PX11_Pos)                 ///< PX11[1:0] bits (pinx configuration bits, pin 11)
+#define GPIO_DCR_PX11_MODE0             (0x00U << GPIO_DCR_PX11_Pos)                 ///< Mode = 0
+#define GPIO_DCR_PX11_MODE1             (0x01U << GPIO_DCR_PX11_Pos)                 ///< Mode = 1
+#define GPIO_DCR_PX11_MODE2             (0x02U << GPIO_DCR_PX11_Pos)                 ///< Mode = 2
+#define GPIO_DCR_PX11_MODE3             (0x03U << GPIO_DCR_PX11_Pos)                 ///< Mode = 3
+#define GPIO_DCR_PX12_Pos               (24)
+#define GPIO_DCR_PX12                   (0x03U << GPIO_DCR_PX12_Pos)                 ///< PX12[1:0] bits (pinx configuration bits, pin 12)
+#define GPIO_DCR_PX12_MODE0             (0x00U << GPIO_DCR_PX12_Pos)                 ///< Mode = 0
+#define GPIO_DCR_PX12_MODE1             (0x01U << GPIO_DCR_PX12_Pos)                 ///< Mode = 1
+#define GPIO_DCR_PX12_MODE2             (0x02U << GPIO_DCR_PX12_Pos)                 ///< Mode = 2
+#define GPIO_DCR_PX12_MODE3             (0x03U << GPIO_DCR_PX12_Pos)                 ///< Mode = 3
+#define GPIO_DCR_PX13_Pos               (26)
+#define GPIO_DCR_PX13                   (0x03U << GPIO_DCR_PX13_Pos)                 ///< PX13[1:0] bits (pinx configuration bits, pin 13)
+#define GPIO_DCR_PX13_MODE0             (0x00U << GPIO_DCR_PX13_Pos)                 ///< Mode = 0
+#define GPIO_DCR_PX13_MODE1             (0x01U << GPIO_DCR_PX13_Pos)                 ///< Mode = 1
+#define GPIO_DCR_PX13_MODE2             (0x02U << GPIO_DCR_PX13_Pos)                 ///< Mode = 2
+#define GPIO_DCR_PX13_MODE3             (0x03U << GPIO_DCR_PX13_Pos)                 ///< Mode = 3
+
+#define GPIO_DCR_PX14_Pos               (28)
+#define GPIO_DCR_PX14                   (0x03U << GPIO_DCR_PX14_Pos)                 ///< PX14[1:0] bits (pinx configuration bits, pin 14)
+#define GPIO_DCR_PX14_MODE0             (0x00U << GPIO_DCR_PX14_Pos)                 ///< Mode = 0
+#define GPIO_DCR_PX14_MODE1             (0x01U << GPIO_DCR_PX14_Pos)                 ///< Mode = 1
+#define GPIO_DCR_PX14_MODE2             (0x02U << GPIO_DCR_PX14_Pos)                 ///< Mode = 2
+#define GPIO_DCR_PX14_MODE3             (0x03U << GPIO_DCR_PX14_Pos)                 ///< Mode = 3
+#define GPIO_DCR_PX15_Pos               (30)
+#define GPIO_DCR_PX15                   (0x03U << GPIO_DCR_PX15_Pos)                 ///< PX15[1:0] bits (pinx configuration bits, pin 15)
+#define GPIO_DCR_PX15_MODE0             (0x00U << GPIO_DCR_PX15_Pos)                 ///< Mode = 0
+#define GPIO_DCR_PX15_MODE1             (0x01U << GPIO_DCR_PX15_Pos)                 ///< Mode = 1
+#define GPIO_DCR_PX15_MODE2             (0x02U << GPIO_DCR_PX15_Pos)                 ///< Mode = 2
+#define GPIO_DCR_PX15_MODE3             (0x03U << GPIO_DCR_PX15_Pos)                 ///< Mode = 3
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_AFRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_AFRL_AFR0_Pos              (0)
+#define GPIO_AFRL_AFR0                  (0x0FU << GPIO_AFRL_AFR0_Pos)           ///< Multiplexing function selection for bit 0 of portx
+#define GPIO_AFRL_AFR1_Pos              (4)
+#define GPIO_AFRL_AFR1                  (0x0FU << GPIO_AFRL_AFR1_Pos)           ///< Multiplexing function selection for bit 1 of portx
+#define GPIO_AFRL_AFR2_Pos              (8)
+#define GPIO_AFRL_AFR2                  (0x0FU << GPIO_AFRL_AFR2_Pos)           ///< Multiplexing function selection for bit 2 of portx
+#define GPIO_AFRL_AFR3_Pos              (12)
+#define GPIO_AFRL_AFR3                  (0x0FU << GPIO_AFRL_AFR3_Pos)           ///< Multiplexing function selection for bit 3 of portx
+#define GPIO_AFRL_AFR4_Pos              (16)
+#define GPIO_AFRL_AFR4                  (0x0FU << GPIO_AFRL_AFR4_Pos)           ///< Multiplexing function selection for bit 4 of portx
+#define GPIO_AFRL_AFR5_Pos              (20)
+#define GPIO_AFRL_AFR5                  (0x0FU << GPIO_AFRL_AFR5_Pos)           ///< Multiplexing function selection for bit 5 of portx
+#define GPIO_AFRL_AFR6_Pos              (24)
+#define GPIO_AFRL_AFR6                  (0x0FU << GPIO_AFRL_AFR6_Pos)           ///< Multiplexing function selection for bit 6 of portx
+#define GPIO_AFRL_AFR7_Pos              (28)
+#define GPIO_AFRL_AFR7                  (0x0FU << GPIO_AFRL_AFR7_Pos)           ///< Multiplexing function selection for bit 7 of portx
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief GPIO_AFRH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define GPIO_AFRH_AFR8_Pos              (0)
+#define GPIO_AFRH_AFR8                  (0x0FU << GPIO_AFRH_AFR8_Pos)           ///< Multiplexing function selection for bit 8 of portx
+#define GPIO_AFRH_AFR9_Pos              (4)
+#define GPIO_AFRH_AFR9                  (0x0FU << GPIO_AFRH_AFR9_Pos)           ///< Multiplexing function selection for bit 9 of portx
+#define GPIO_AFRH_AFR10_Pos             (8)
+#define GPIO_AFRH_AFR10                 (0x0FU << GPIO_AFRH_AFR10_Pos)          ///< Multiplexing function selection for bit 10 of portx
+#define GPIO_AFRH_AFR11_Pos             (12)
+#define GPIO_AFRH_AFR11                 (0x0FU << GPIO_AFRH_AFR11_Pos)          ///< Multiplexing function selection for bit 11 of portx
+#define GPIO_AFRH_AFR12_Pos             (16)
+#define GPIO_AFRH_AFR12                 (0x0FU << GPIO_AFRH_AFR12_Pos)          ///< Multiplexing function selection for bit 12 of portx
+#define GPIO_AFRH_AFR13_Pos             (20)
+#define GPIO_AFRH_AFR13                 (0x0FU << GPIO_AFRH_AFR13_Pos)          ///< Multiplexing function selection for bit 13 of portx
+#define GPIO_AFRH_AFR14_Pos             (24)
+#define GPIO_AFRH_AFR14                 (0x0FU << GPIO_AFRH_AFR14_Pos)          ///< Multiplexing function selection for bit 14 of portx
+#define GPIO_AFRH_AFR15_Pos             (28)
+#define GPIO_AFRH_AFR15                 (0x0FU << GPIO_AFRH_AFR15_Pos)          ///< Multiplexing function selection for bit 15 of portx
+#define GPIO_AF_MODEMASK                (0x0FU)                                 ///< Mode = 0
+#define GPIO_AF_MODE0                   (0x00U)                                 ///< Mode = 0
+#define GPIO_AF_MODE1                   (0x01U)                                 ///< Mode = 1
+#define GPIO_AF_MODE2                   (0x02U)                                 ///< Mode = 2
+#define GPIO_AF_MODE3                   (0x03U)                                 ///< Mode = 3
+#define GPIO_AF_MODE4                   (0x04U)                                 ///< Mode = 4
+#define GPIO_AF_MODE5                   (0x05U)                                 ///< Mode = 5
+#define GPIO_AF_MODE6                   (0x06U)                                 ///< Mode = 6
+#define GPIO_AF_MODE7                   (0x07U)                                 ///< Mode = 7
+#define GPIO_AF_MODE8                   (0x08U)                                 ///< Mode = 8 
+#define GPIO_AF_MODE9                   (0x09U)                                 ///< Mode = 9 
+#define GPIO_AF_MODE10                  (0x0AU)                                 ///< Mode = 10
+#define GPIO_AF_MODE11                  (0x0BU)                                 ///< Mode = 11
+#define GPIO_AF_MODE12                  (0x0CU)                                 ///< Mode = 12
+#define GPIO_AF_MODE13                  (0x0DU)                                 ///< Mode = 13
+#define GPIO_AF_MODE14                  (0x0EU)                                 ///< Mode = 14
+#define GPIO_AF_MODE15                  (0x0FU)                                 ///< Mode = 15
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h
new file mode 100644
index 000000000..e12f107e3
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h
@@ -0,0 +1,635 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_i2c.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_I2C_H
+#define __REG_I2C_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C1_BASE                       (APB1PERIPH_BASE + 0x5400)              ///< Base Address: 0x40005400
+#define I2C2_BASE                       (APB1PERIPH_BASE + 0x5800)              ///< Base Address: 0x40005800
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+#undef USENCOMBINEREGISTER
+#undef USENNEWREGISTER
+#undef USENOLDREGISTER
+#define USENCOMBINEREGISTER
+#ifdef USENCOMBINEREGISTER
+typedef struct {
+    union {
+        __IO u32 CR;                                                           ///< Control Register                               offset: 0x00
+        __IO u32 IC_CON;
+    };
+    union {
+        __IO u32 TAR;                                                          ///< Target Address Register                        offset: 0x04
+        __IO u32 IC_TAR;
+    };
+    union {
+        __IO u32 SAR;                                                          ///< Slave Address Register                         offset: 0x08
+        __IO u32 IC_SAR;
+    };
+    __IO u32 IC_HS_MADDR_RESERVED;                                             ///< Reserved Register                              offset: 0x0C
+    union {
+        __IO u32 DR;                                                           ///< Data Command Register                          offset: 0x10
+        __IO u32 IC_DATA_CMD;
+    };
+    union {
+        __IO u32 SSHR;                                                         ///< SCL High Period Count for Std. Speed Register  offset: 0x14
+        __IO u32 IC_SS_SCL_HCNT;
+    };
+    union {
+        __IO u32 SSLR;                                                         ///< SCL Low Period Count for Std. Speed Register   offset: 0x18
+        __IO u32 IC_SS_SCL_LCNT;
+    };
+    union {
+        __IO u32 FSHR;                                                         ///< SCL High Period Count for Fast Speed Register  offset: 0x1C
+        __IO u32 IC_FS_SCL_HCNT;
+    };
+    union {
+        __IO u32 FSLR;                                                         ///< SCL Low Period Count for Fast Speed Register   offset: 0x20
+        __IO u32 IC_FS_SCL_LCNT;
+    };
+    __IO u32 IC_HS_SCL_HCNT_RESERVED;                                          ///< Reserved Register                              offset: 0x24
+    __IO u32 IC_HS_SCL_LCNT_RESERVED;                                          ///< Reserved Register                              offset: 0x28
+    union {
+        __IO u32 ISR;                                                          ///< Interrupt Status Register                      offset: 0x2C
+        __IO u32 IC_INTR_STAT;
+    };
+    union {
+        __IO u32 IMR;                                                          ///< Interrupt Mask Register                        offset: 0x30
+        __IO u32 IC_INTR_MASK;
+    };
+    union {
+        __IO u32 RAWISR;                                                       ///< RAW Interrupt Status Register                  offset: 0x34
+        __IO u32 IC_RAW_INTR_STAT;
+    };
+    union {
+        __IO u32 RXTLR;                                                        ///< Receive FIFO Threshold Level Register          offset: 0x38
+        __IO u32 IC_RX_TL;
+    };
+    union {
+        __IO u32 TXTLR;                                                        ///< Transmit FIFO Threshold Level Register         offset: 0x3C
+        __IO u32 IC_TX_TL;
+    };
+    union {
+        __IO u32 ICR;                                                          ///< Clear All Interrupt Register                   offset: 0x40
+        __IO u32 IC_CLR_INTR;
+    };
+    union {
+        __IO u32 RX_UNDER;                                                     ///< Clear RX_UNDER Interrupt Register              offset: 0x44
+        __IO u32 IC_CLR_RX_UNDER;
+    };
+    union {
+        __IO u32 RX_OVER;                                                      ///< Clear RX_OVER Interrupt Register               offset: 0x48
+        __IO u32 IC_CLR_RX_OVER;
+    };
+    union {
+        __IO u32 TX_OVER;                                                      ///< Clear TX_OVER Interrupt Register               offset: 0x4C
+        __IO u32 IC_CLR_TX_OVER;
+    };
+    union {
+        __IO u32 RD_REQ;                                                       ///< Clear RD_REQ Interrupt Register                offset: 0x50
+        __IO u32 IC_CLR_RD_REQ;
+    };
+    union {
+        __IO u32 TX_ABRT;                                                      ///< Clear TX_ABRT Interrupt Register               offset: 0x54
+        __IO u32 IC_CLR_TX_ABRT;
+    };
+    union {
+        __IO u32 RX_DONE;                                                      ///< Clear RX_DONE Interrupt Register               offset: 0x58
+        __IO u32 IC_CLR_RX_DONE;
+    };
+    union {
+        __IO u32 ACTIV;                                                        ///< Clear ACTIVITY Interrupt Register              offset: 0x5C
+        __IO u32 IC_CLR_ACTIVITY;
+    };
+    union {
+        __IO u32 STOP;                                                         ///< Clear STOP_DET Interrupt Register              offset: 0x60
+        __IO u32 IC_CLR_STOP_DET;
+    };
+    union {
+        __IO u32 START;                                                        ///< Clear START_DET Interrupt Register             offset: 0x64
+        __IO u32 IC_CLR_START_DET;
+    };
+    union {
+        __IO u32 GC;                                                           ///< Clear GEN_CALL Interrupt Register              offset: 0x68
+        __IO u32 IC_CLR_GEN_CALL;
+    };
+    union {
+        __IO u32 ENR;                                                          ///< Enable Register                                offset: 0x6C
+        __IO u32 IC_ENABLE;
+    };
+    union {
+        __IO u32 SR;                                                           ///< Status Register                                offset: 0x70
+        __IO u32 IC_STATUS;
+    };
+    union {
+        __IO u32 TXFLR;                                                        ///< Transmit FIFO Level Register                   offset: 0x74
+        __IO u32 IC_TXFLR;
+    };
+    union {
+        __IO u32 RXFLR;                                                        ///< Receive FIFO Level Register                    offset: 0x78
+        __IO u32 IC_RXFLR;
+    };
+    union {
+        __IO u32 HOLD;                                                         ///< SDA Hold Time Register                         offset: 0x7C
+        __IO u32 IC_SDA_HOLD;
+    };
+    __IO u32 RESERVED28;                                                       ///IC_TX_ABRT_SOURCE_RESERVED;
+    __IO u32 RESERVED29;                                                       ///IC_SLV_DATA_NACK_ONLY_RESERVED;
+
+    union {
+        __IO u32 DMA;                                                          ///< DMA Control Register                           offset: 0x88
+        __IO u32 IC_DMA_CR;
+    };
+    __IO u32 RESERVED30;                                                       ///IC_DMA_TDLR_RESERVED;
+    __IO u32 RESERVED31;                                                       ///IC_DMA_RDLR_RESERVED;
+    union {
+        __IO u32 SETUP;                                                        ///< SDA Setup Time Register                        offset: 0x94
+        __IO u32 IC_SDA_SETUP;
+    };
+    union {
+        __IO u32 GCR;                                                          ///< ACK General Call Register                      offset: 0x98
+        __IO u32 IC_ACK_GENERAL_CALL;
+    };
+    __IO u32 RESERVED32a;                                                       ///_RESERVED;                                     offset: 0x9C
+    __IO u32 RESERVED33;                                                        ///_RESERVED;                                     offset: 0xA0
+    __IO u32 RESERVED34;                                                        ///_RESERVED;                                     offset: 0xA4
+    __IO u32 RESERVED35;                                                        ///_RESERVED;                                     offset: 0xA8
+    __IO u32 RESERVED36;                                                        ///_RESERVED;                                     offset: 0xAC    
+    __IO u32 SLVMASK;                                                           ///<I2C Slave Mode Mask Register                  offset: 0xB0
+    __IO u32 SLVRCVADDR;                                                        ///<I2C Slave Mode Address Register               offset: 0xB4
+
+} I2C_TypeDef;
+#endif
+#ifdef USENNEWREGISTER
+typedef struct {
+    __IO u32 CR;                                                                ///< Control Register                               offset: 0x00
+    __IO u32 TAR;                                                               ///< Target Address Register                        offset: 0x04
+    __IO u32 SAR;                                                               ///< Slave Address Register                         offset: 0x08
+    __IO u32 RESERVED3;
+    __IO u32 DR;                                                                ///< Data Command Register                          offset: 0x10
+    __IO u32 SSHR;                                                              ///< SCL High Period Count for Std. Speed Register  offset: 0x14
+    __IO u32 SSLR;                                                              ///< SCL Low Period Count for Std. Speed Register   offset: 0x18
+    __IO u32 FSHR;                                                              ///< SCL High Period Count for Fast Speed Register  offset: 0x1C
+    __IO u32 FSLR;                                                              ///< SCL Low Period Count for Fast Speed Register   offset: 0x20
+    __IO u32 RESERVED9;
+    __IO u32 RESERVED10;
+    __IO u32 ISR;                                                               ///< Interrupt Status Register                      offset: 0x2C
+    __IO u32 IMR;                                                               ///< Interrupt Mask Register                        offset: 0x30
+    __IO u32 RAWISR;                                                            ///< RAW Interrupt Status Register                  offset: 0x34
+    __IO u32 RXTLR;                                                             ///< Receive FIFO Threshold Level Register          offset: 0x38
+    __IO u32 TXTLR;                                                             ///< Transmit FIFO Threshold Level Register         offset: 0x3C
+    __IO u32 ICR;                                                               ///< Clear All Interrupt Register                   offset: 0x40
+    __IO u32 RX_UNDER;                                                          ///< Clear RX_UNDER Interrupt Register              offset: 0x44
+    __IO u32 RX_OVER;                                                           ///< Clear RX_OVER Interrupt Register               offset: 0x48
+    __IO u32 TX_OVER;                                                           ///< Clear TX_OVER Interrupt Register               offset: 0x4C
+    __IO u32 RD_REQ;                                                            ///< Clear RD_REQ Interrupt Register                offset: 0x50
+    __IO u32 TX_ABRT;                                                           ///< Clear TX_ABRT Interrupt Register               offset: 0x54
+    __IO u32 RX_DONE;                                                           ///< Clear RX_DONE Interrupt Register               offset: 0x58
+    __IO u32 ACTIV;                                                             ///< Clear ACTIVITY Interrupt Register              offset: 0x5C
+    __IO u32 STOP;                                                              ///< Clear STOP_DET Interrupt Register              offset: 0x60
+    __IO u32 START;                                                             ///< Clear START_DET Interrupt Register             offset: 0x64
+    __IO u32 GC;                                                                ///< Clear GEN_CALL Interrupt Register              offset: 0x68
+    __IO u32 ENR;                                                               ///< Enable Register                                offset: 0x6C
+    __IO u32 SR;                                                                ///< Status Register                                offset: 0x70
+    __IO u32 TXFLR;                                                             ///< Transmit FIFO Level Register                   offset: 0x74
+    __IO u32 RXFLR;                                                             ///< Receive FIFO Level Register                    offset: 0x78
+    __IO u32 HOLD;                                                              ///< SDA Hold Time Register                         offset: 0x7C
+    __IO u32 RESERVED28;
+    __IO u32 RESERVED29;
+    __IO u32 RESERVED30;
+    __IO u32 RESERVED30a;
+    __IO u32 SETUP;                                                             ///< SDA Setup Time Register                        offset: 0x94
+    __IO u32 GCR;                                                               ///< ACK General Call Register                      offset: 0x98
+} I2C_TypeDef;
+#endif
+#ifdef USENOLDREGISTER
+typedef struct {
+    __IO u32 IC_CON;
+    __IO u32 IC_TAR;
+    __IO u32 IC_SAR;
+    __IO u32 IC_HS_MADDR_RESERVED;
+    __IO u32 IC_DATA_CMD;
+    __IO u32 IC_SS_SCL_HCNT;
+    __IO u32 IC_SS_SCL_LCNT;
+    __IO u32 IC_FS_SCL_HCNT;
+    __IO u32 IC_FS_SCL_LCNT;
+    __IO u32 IC_HS_SCL_HCNT_RESERVED;
+    __IO u32 IC_HS_SCL_LCNT_RESERVED;
+    __IO u32 IC_INTR_STAT;
+    __IO u32 IC_INTR_MASK;
+    __IO u32 IC_RAW_INTR_STAT;
+    __IO u32 IC_RX_TL;
+    __IO u32 IC_TX_TL;
+    __IO u32 IC_CLR_INTR;
+    __IO u32 IC_CLR_RX_UNDER;
+    __IO u32 IC_CLR_RX_OVER;
+    __IO u32 IC_CLR_TX_OVER;
+    __IO u32 IC_CLR_RD_REQ;
+    __IO u32 IC_CLR_TX_ABRT;
+    __IO u32 IC_CLR_RX_DONE;
+    __IO u32 IC_CLR_ACTIVITY;
+    __IO u32 IC_CLR_STOP_DET;
+    __IO u32 IC_CLR_START_DET;
+    __IO u32 IC_CLR_GEN_CALL;
+    __IO u32 IC_ENABLE;
+    __IO u32 IC_STATUS;
+    __IO u32 IC_TXFLR;
+    __IO u32 IC_RXFLR;
+    __IO u32 IC_SDA_HOLD;
+    __IO u32 IC_TX_ABRT_SOURCE_RESERVED;
+    __IO u32 IC_SLV_DATA_NACK_ONLY_RESERVED;
+    __IO u32 IC_DMA_CR;
+    __IO u32 IC_DMA_TDLR_RESERVED;
+    __IO u32 IC_DMA_RDLR_RESERVED;
+    __IO u32 IC_SDA_SETUP;
+    __IO u32 IC_ACK_GENERAL_CALL;
+} I2C_TypeDef;
+#endif
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C1                            ((I2C_TypeDef*)I2C1_BASE)
+#define I2C2                            ((I2C_TypeDef*)I2C2_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_CR_MASTER_Pos               (0)
+#define I2C_CR_MASTER                   (0x01U << I2C_CR_MASTER_Pos)            ///< I2C master mode enable
+#define I2C_CR_SPEED_Pos                (1)
+#define I2C_CR_SPEED                    (0x03U << I2C_CR_SPEED_Pos)             ///< I2C speed mode
+#define I2C_CR_STD                      (0x01U << I2C_CR_SPEED_Pos)             ///< I2C standard speed mode
+#define I2C_CR_FAST                     (0x02U << I2C_CR_SPEED_Pos)             ///< I2C fast speed mode
+#define I2C_CR_SLAVE10_Pos              (3)
+#define I2C_CR_SLAVE10                  (0x01U << I2C_CR_SLAVE10_Pos)           ///< I2C slave mode responds to 10-bit address
+#define I2C_CR_MASTER10_Pos             (4)
+#define I2C_CR_MASTER10                 (0x01U << I2C_CR_MASTER10_Pos)          ///< I2C master mode responds to 10-bit address
+#define I2C_CR_REPEN_Pos                (5)
+#define I2C_CR_REPEN                    (0x01U << I2C_CR_REPEN_Pos)             ///< Enable send RESTART
+#define I2C_CR_SLAVEDIS_Pos             (6)
+#define I2C_CR_SLAVEDIS                 (0x01U << I2C_CR_SLAVEDIS_Pos)          ///< I2C slave mode disable
+#define I2C_CR_STOPINT_Pos              (7)
+#define I2C_CR_STOPINT                  (0x01U << I2C_CR_STOPINT_Pos)           ///< Generate STOP interrupt in slave mode
+#define I2C_CR_EMPINT_Pos               (8)
+#define I2C_CR_EMPINT                   (0x01U << I2C_CR_EMPINT_Pos)            ///< I2C TX_EMPTY interrupt
+
+#define I2C_CR_STOP_Pos             (9)
+#define I2C_CR_STOP                 (0x01U << I2C_CR_STOP_Pos)                  ///< STOP signal enable
+#define I2C_CR_RESTART_Pos          (10)
+#define I2C_CR_RESTART              (0x01U << I2C_CR_RESTART_Pos)               ///< RESTART signal enable
+#define I2C_CR_SLV_TX_ABRT_DIS_Pos  (11)
+#define I2C_CR_SLV_TX_ABRT_DIS      (0x01U << I2C_CR_SLV_TX_ABRT_DIS_Pos)       ///< I2C as a slave
+#define I2C_CR_PADSEL_Pos           (12)
+#define I2C_CR_PADSEL               (0x01U << I2C_CR_PADSEL_Pos)               ///< PAD mode select
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_TAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_TAR_ADDR_Pos                (0)
+#define I2C_TAR_ADDR                    (0x03FFU << I2C_TAR_ADDR_Pos)           ///< Target address for master mode
+#define I2C_TAR_GC_Pos                  (10)
+#define I2C_TAR_GC                      (0x01U << I2C_TAR_GC_Pos)               ///< General Call or START byte
+#define I2C_TAR_SPECIAL_Pos             (11)
+#define I2C_TAR_SPECIAL                 (0x01U << I2C_TAR_SPECIAL_Pos)          ///< Special command enable like General Call or START byte
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_SAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_SAR_ADDR_Pos                (0)
+#define I2C_SAR_ADDR                    (0x03FFU << I2C_SAR_ADDR_Pos)           ///< Slave address
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_DR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_DR_DAT_Pos                  (0)
+#define I2C_DR_DAT                      (0xFFU << I2C_DR_DAT_Pos)               ///< The data to be transmitted or received
+#define I2C_DR_CMD_Pos                  (8)
+#define I2C_DR_CMD                      (0x01U << I2C_DR_CMD_Pos)               ///< Read or write command
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_SSHR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_SSHR_CNT_Pos                (0)
+#define I2C_SSHR_CNT                    (0xFFFFU << I2C_SSHR_CNT_Pos)           ///< SCL clock high period count for standard speed
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_SSLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_SSLR_CNT_Pos                (0)
+#define I2C_SSLR_CNT                    (0xFFFFU << I2C_SSLR_CNT_Pos)           ///< SCL clock low period count for standard speed
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_FSHR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_FSHR_CNT_Pos                (0)
+#define I2C_FSHR_CNT                    (0xFFFFU << I2C_FSHR_CNT_Pos)           ///< SCL clock high period count for fast speed
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_FSLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_FSLR_CNT_Pos                (0)
+#define I2C_FSLR_CNT                    (0xFFFFU << I2C_FSLR_CNT_Pos)           ///< SCL clock low period count for fast speed
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_ISR_RX_UNDER_Pos            (0)
+#define I2C_ISR_RX_UNDER                (0x01U << I2C_ISR_RX_UNDER_Pos)         ///< RX_UNDER interrupt status
+#define I2C_ISR_RX_OVER_Pos             (1)
+#define I2C_ISR_RX_OVER                 (0x01U << I2C_ISR_RX_OVER_Pos)          ///< RX_OVER interrupt status
+#define I2C_ISR_RX_FULL_Pos             (2)
+#define I2C_ISR_RX_FULL                 (0x01U << I2C_ISR_RX_FULL_Pos)          ///< RX_FULL interrupt status
+#define I2C_ISR_TX_OVER_Pos             (3)
+#define I2C_ISR_TX_OVER                 (0x01U << I2C_ISR_TX_OVER_Pos)          ///< TX_OVER interrupt status
+#define I2C_ISR_TX_EMPTY_Pos            (4)
+#define I2C_ISR_TX_EMPTY                (0x01U << I2C_ISR_TX_EMPTY_Pos)         ///< TX_EMPTY interrupt status
+#define I2C_ISR_RX_REQ_Pos              (5)
+#define I2C_ISR_RX_REQ                  (0x01U << I2C_ISR_RX_REQ_Pos)           ///< RX_REQ interrupt status
+#define I2C_ISR_TX_ABRT_Pos             (6)
+#define I2C_ISR_TX_ABRT                 (0x01U << I2C_ISR_TX_ABRT_Pos)          ///< TX_ABRT interrupt status
+#define I2C_ISR_RX_DONE_Pos             (7)
+#define I2C_ISR_RX_DONE                 (0x01U << I2C_ISR_RX_DONE_Pos)          ///< RX_DONE interrupt status
+#define I2C_ISR_ACTIV_Pos               (8)
+#define I2C_ISR_ACTIV                   (0x01U << I2C_ISR_ACTIV_Pos)            ///< ACTIVITY interrupt status
+#define I2C_ISR_STOP_Pos                (9)
+#define I2C_ISR_STOP                    (0x01U << I2C_ISR_STOP_Pos)             ///< STOP_DET interrupt status
+#define I2C_ISR_START_Pos               (10)
+#define I2C_ISR_START                   (0x01U << I2C_ISR_START_Pos)            ///< START_DET interrupt status
+#define I2C_ISR_GC_Pos                  (11)
+#define I2C_ISR_GC                      (0x01U << I2C_ISR_GC_Pos)               ///< GEN_CALL interrupt status
+#define I2C_ISR_RESTART_Pos             (12)
+#define I2C_ISR_RESTART                 (0x01U << I2C_ISR_RESTART_Pos)          ///< RESTART_DET interrupt status
+#define I2C_ISR_HOLD_Pos                (13)
+#define I2C_ISR_HOLD                    (0x01U << I2C_ISR_HOLD_Pos)             ///< MST_ON_HOLD interrupt status
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_IMR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_IMR_RX_UNDER_Pos            (0)
+#define I2C_IMR_RX_UNDER                (0x01U << I2C_IMR_RX_UNDER_Pos)         ///< RX_UNDER interrupt mask
+#define I2C_IMR_RX_OVER_Pos             (1)
+#define I2C_IMR_RX_OVER                 (0x01U << I2C_IMR_RX_OVER_Pos)          ///< RX_OVER interrupt mask
+#define I2C_IMR_RX_FULL_Pos             (2)
+#define I2C_IMR_RX_FULL                 (0x01U << I2C_IMR_RX_FULL_Pos)          ///< RX_FULL interrupt mask
+#define I2C_IMR_TX_OVER_Pos             (3)
+#define I2C_IMR_TX_OVER                 (0x01U << I2C_IMR_TX_OVER_Pos)          ///< TX_OVER interrupt mask
+#define I2C_IMR_TX_EMPTY_Pos            (4)
+#define I2C_IMR_TX_EMPTY                (0x01U << I2C_IMR_TX_EMPTY_Pos)         ///< TX_EMPTY interrupt mask
+#define I2C_IMR_RX_REQ_Pos              (5)
+#define I2C_IMR_RX_REQ                  (0x01U << I2C_IMR_RX_REQ_Pos)           ///< RX_REQ interrupt mask
+#define I2C_IMR_TX_ABRT_Pos             (6)
+#define I2C_IMR_TX_ABRT                 (0x01U << I2C_IMR_TX_ABRT_Pos)          ///< TX_ABRT interrupt mask
+#define I2C_IMR_RX_DONE_Pos             (7)
+#define I2C_IMR_RX_DONE                 (0x01U << I2C_IMR_RX_DONE_Pos)          ///< RX_DONE interrupt mask
+
+#define I2C_IMR_ACTIV_Pos               (8)
+#define I2C_IMR_ACTIV                   (0x01U << I2C_IMR_ACTIV_Pos)            ///< ACTIVITY interrupt status
+#define I2C_IMR_STOP_Pos                (9)
+#define I2C_IMR_STOP                    (0x01U << I2C_IMR_STOP_Pos)             ///< STOP_DET interrupt status
+#define I2C_IMR_START_Pos               (10)
+#define I2C_IMR_START                   (0x01U << I2C_IMR_START_Pos)            ///< START_DET interrupt status
+#define I2C_IMR_GC_Pos                  (11)
+#define I2C_IMR_GC                      (0x01U << I2C_IMR_GC_Pos)               ///< GEN_CALL interrupt status
+#define I2C_IMR_RESTART_Pos             (12)
+#define I2C_IMR_RESTART                 (0x01U << I2C_IMR_RESTART_Pos)          ///< RESTART_DET interrupt status
+#define I2C_IMR_HOLD_Pos                (13)
+#define I2C_IMR_HOLD                    (0x01U << I2C_IMR_HOLD_Pos)             ///< MST_ON_HOLD interrupt status
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_RAWISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_RAWISR_RX_UNDER_Pos         (0)
+#define I2C_RAWISR_RX_UNDER             (0x01U << I2C_RAWISR_RX_UNDER_Pos)      ///< RX_UNDER raw interrupt status
+#define I2C_RAWISR_RX_OVER_Pos          (1)
+#define I2C_RAWISR_RX_OVER              (0x01U << I2C_RAWISR_RX_OVER_Pos)       ///< RX_OVER raw interrupt status
+#define I2C_RAWISR_RX_FULL_Pos          (2)
+#define I2C_RAWISR_RX_FULL              (0x01U << I2C_RAWISR_RX_FULL_Pos)       ///< RX_FULL raw interrupt status
+#define I2C_RAWISR_TX_OVER_Pos          (3)
+#define I2C_RAWISR_TX_OVER              (0x01U << I2C_RAWISR_TX_OVER_Pos)       ///< TX_OVER raw interrupt status
+#define I2C_RAWISR_TX_EMPTY_Pos         (4)
+#define I2C_RAWISR_TX_EMPTY             (0x01U << I2C_RAWISR_TX_EMPTY_Pos)      ///< TX_EMPTY raw interrupt status
+#define I2C_RAWISR_RX_REQ_Pos           (5)
+#define I2C_RAWISR_RX_REQ               (0x01U << I2C_RAWISR_RX_REQ_Pos)        ///< RX_REQ raw interrupt status
+#define I2C_RAWISR_TX_ABRT_Pos          (6)
+#define I2C_RAWISR_TX_ABRT              (0x01U << I2C_RAWISR_TX_ABRT_Pos)       ///< TX_ABRT raw interrupt status
+#define I2C_RAWISR_RX_DONE_Pos          (7)
+#define I2C_RAWISR_RX_DONE              (0x01U << I2C_RAWISR_RX_DONE_Pos)       ///< RX_DONE raw interrupt status
+
+#define I2C_RAWISR_ACTIV_Pos            (8)
+#define I2C_RAWISR_ACTIV                (0x01U << I2C_RAWISR_ACTIV_Pos)         ///< ACTIVITY interrupt status
+#define I2C_RAWISR_STOP_Pos             (9)
+#define I2C_RAWISR_STOP                 (0x01U << I2C_RAWISR_STOP_Pos)          ///< STOP_DET interrupt status
+#define I2C_RAWISR_START_Pos            (10)
+#define I2C_RAWISR_START                (0x01U << I2C_RAWISR_START_Pos)         ///< START_DET interrupt status
+#define I2C_RAWISR_GC_Pos               (11)
+#define I2C_RAWISR_GC                   (0x01U << I2C_RAWISR_GC_Pos)            ///< GEN_CALL interrupt status
+#define I2C_RAWISR_RESTART_Pos          (12)
+#define I2C_RAWISR_RESTART              (0x01U << I2C_RAWISR_RESTART_Pos)       ///< RESTART_DET interrupt status
+#define I2C_RAWISR_HOLD_Pos             (13)
+#define I2C_RAWISR_HOLD                 (0x01U << I2C_RAWISR_HOLD_Pos)          ///< MST_ON_HOLD interrupt status
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_RXTLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_RXTLR_Pos                   (0)
+#define I2C_RXTLR_TL                    (0xFFU << I2C_RXTLR_Pos)                ///< Receive FIFO threshold level
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_TXTLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_TXTLR_Pos                   (0)
+#define I2C_TXTLR_TL                    (0xFFU << I2C_TXTLR_Pos)                ///< Transmit FIFO threshold level
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_ICR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_ICR_Pos                     (0)
+#define I2C_ICR                         (0x01U << I2C_ICR_Pos)                  ///< Read this register to clear the combined interrupt, all individual interrupts
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_RX_UNDER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_RX_UNDER_Pos                (0)
+#define I2C_RX_UNDER                    (0x01U << I2C_RX_UNDER_Pos)             ///< Read this register to clear the RX_UNDER interrupt of the I2C_RAW_INTR_STAT register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_RX_OVER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_RX_OVER_Pos                 (0)
+#define I2C_RX_OVER                     (0x01U << I2C_RX_OVER_Pos)              ///< Read this register to clear the RX_OVER interrupt of the I2C_RAW_INTR_STAT register
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_TX_OVER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_TX_OVER_Pos                 (0)
+#define I2C_TX_OVER                     (0x01U << I2C_TX_OVER_Pos)              ///< Read this register to clear the TX_OVER interrupt of the I2C_RAW_INTR_STAT register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_RD_REQ Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_RD_REQ_Pos                  (0)
+#define I2C_RD_REQ                      (0x01U << I2C_RD_REQ_Pos)               ///< Read this register to clear the RD_REQ interrupt of the I2C_RAW_INTR_STAT register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_TX_ABRT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_TX_ABRT_Pos                 (0)
+#define I2C_TX_ABRT                     (0x01U << I2C_TX_ABRT_Pos)              ///< Read this register to clear the TX_ABRT interrupt of the I2C_RAW_INTR_STAT register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_RX_DONE Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_RX_DONE_Pos                 (0)
+#define I2C_RX_DONE                     (0x01U << I2C_RX_DONE_Pos)              ///< Read this register to clear the RX_DONE interrupt of the I2C_RAW_INTR_STAT register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_ACTIV Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_ACTIV_Pos                   (0)
+#define I2C_ACTIV                       (0x01U << I2C_ACTIV_Pos)                ///< Read this register to clear the ACTIVITY interrupt of the I2C_RAW_INTR_STAT register
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_STOP Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_STOP_Pos                    (0)
+#define I2C_STOP                        (0x01U << I2C_STOP_Pos)                 ///< Read this register to clear the STOP_DET interrupt of the I2C_RAW_INTR_STAT register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_START Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_START_Pos                   (0)
+#define I2C_START                       (0x01U << I2C_START_Pos)                ///< Read this register to clear the START_DET interrupt of the I2C_RAW_INTR_STAT register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_GC Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_GC_Pos                      (0)
+#define I2C_GC                          (0x01U << I2C_GC_Pos)                   ///< Read this register to clear the GEN_CALL interrupt of the I2C_RAW_INTR_STAT register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_ENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_ENR_ENABLE_Pos              (0)
+#define I2C_ENR_ENABLE                  (0x01U << I2C_ENR_ENABLE_Pos)           ///< I2C mode enable
+#define I2C_ENR_ABORT_Pos               (1)
+#define I2C_ENR_ABORT                   (0x01U << I2C_ENR_ABORT_Pos)            ///< I2C transfer abort
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_SR_ACTIV_Pos                (0)
+#define I2C_SR_ACTIV                    (0x01U << I2C_SR_ACTIV_Pos)             ///< I2C activity status
+#define I2C_SR_TFNF_Pos                 (1)
+#define I2C_SR_TFNF                     (0x01U << I2C_SR_TFNF_Pos)              ///< Transmit FIFO not full
+#define I2C_SR_TFE_Pos                  (2)
+#define I2C_SR_TFE                      (0x01U << I2C_SR_TFE_Pos)               ///< Transmit FIFO completely empty
+#define I2C_SR_RFNE_Pos                 (3)
+#define I2C_SR_RFNE                     (0x01U << I2C_SR_RFNE_Pos)              ///< Receive FIFO not empty
+#define I2C_SR_RFF_Pos                  (4)
+#define I2C_SR_RFF                      (0x01U << I2C_SR_RFF_Pos)               ///< Receive FIFO completely full
+#define I2C_SR_MST_ACTIV_Pos            (5)
+#define I2C_SR_MST_ACTIV                (0x01U << I2C_SR_MST_ACTIV_Pos)         ///< Master FSM activity status
+#define I2C_SR_SLV_ACTIV_Pos            (6)
+#define I2C_SR_SLV_ACTIV                (0x01U << I2C_SR_SLV_ACTIV_Pos)         ///< Slave FSM activity status
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_TXFLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_TXFLR_CNT_Pos               (0)
+#define I2C_TXFLR_CNT                   (0x03U << I2C_TXFLR_CNT_Pos)            ///< Number of valid data in the transmit FIFO
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_RXFLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_RXFLR_CNT_Pos               (0)
+#define I2C_RXFLR_CNT                   (0x03U << I2C_RXFLR_CNT_Pos)            ///< Number of valid data in the receive FIFO
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_HOLD Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_HOLD_TXCNT_Pos              (0)
+#define I2C_HOLD_TXCNT                  (0xFFFFU << I2C_HOLD_TXCNT_Pos)         ///< SDA hold time when I2C acts as a transmit
+#define I2C_HOLD_RXCNT_Pos              (16)
+#define I2C_HOLD_RXCNT                  (0xFFU << I2C_HOLD_RXCNT_Pos)           ///< SDA hold time when I2C acts as a receiver
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_DMA Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_DMA_RXEN_Pos                (0)
+#define I2C_DMA_RXEN                    (0x01U << I2C_DMA_RXEN_Pos)             ///< Receive DMA enable
+#define I2C_DMA_TXEN_Pos                (1)
+#define I2C_DMA_TXEN                    (0x01U << I2C_DMA_TXEN_Pos)             ///< Transmit DMA enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_SETUP Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_SETUP_CNT_Pos               (0)
+#define I2C_SETUP_CNT                   (0xFFU << I2C_SETUP_CNT_Pos)            ///< SDA setup
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2C_GCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define I2C_GCR_GC_Pos                  (0)
+#define I2C_GCR_GC                      (0x01U << I2C_GCR_GC_Pos)               ///< ACK general call
+
+
+#define I2C_SLVMASK_Pos                (0)
+#define I2C_SLVMASK                    (0x3FFU <<I2C_SLVMASK_Pos)
+
+#define I2C_SLVRCVADDR_Pos             (0)
+#define I2C_SLVRCVADDR                 (0x3FFU <<I2C_SLVRCVADDR_Pos)
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h
new file mode 100644
index 000000000..5c77b857c
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h
@@ -0,0 +1,125 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_iwdg.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_IWDG_H
+#define __REG_IWDG_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_BASE                       (APB1PERIPH_BASE + 0x3000)              ///< Base Address: 0x40003000
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 KR;                                                                ///< Key Register                                   offset: 0x00
+    __IO u32 PR;                                                                ///< Prescaler Register                             offset: 0x04
+    __IO u32 RLR;                                                               ///< Reload Register                                offset: 0x08
+    __IO u32 SR;                                                                ///< Status Register                                offset: 0x0C
+    __IO u32 CR;                                                                ///< Control Register                               offset: 0x10
+    __IO u32  IGEN;                                                              ///< Interrupt Generator Register                   offset: 0x14
+    __IO u32  CNT;                                                              ///< Interrupt Generator count Register              offset: 0x18
+    __IO u32  PS;                                                              ///< Prescaler count Register              offset: 0x1C
+} IWDG_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG                            ((IWDG_TypeDef*) IWDG_BASE)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_KR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_KEYR_KEY_Pos               (0)
+#define IWDG_KEYR_KEY                   (0xFFFFU << IWDG_KEYR_KEY_Pos)          ///< Key Value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_PR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_PR_PRE_Pos                 (0)
+#define IWDG_PR_PRE                     (0x07U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 4
+#define IWDG_PR_PRE_DIV4                (0x00U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 4
+#define IWDG_PR_PRE_DIV8                (0x01U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 8
+#define IWDG_PR_PRE_DIV16               (0x02U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 16
+#define IWDG_PR_PRE_DIV32               (0x03U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 32
+#define IWDG_PR_PRE_DIV64               (0x04U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 64
+#define IWDG_PR_PRE_DIV128              (0x05U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 128
+#define IWDG_PR_PRE_DIV256              (0x06U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 256
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_RLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_RLR_RL_Pos                 (0)
+#define IWDG_RLR_RL                     (0x0FFFU << IWDG_RLR_RL_Pos)            ///< Watchdog counter reload value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_SR_PVU_Pos                 (0)
+#define IWDG_SR_PVU                     (0x01U << IWDG_SR_PVU_Pos)              ///< Watchdog prescaler value update
+#define IWDG_SR_RVU_Pos                 (1)
+#define IWDG_SR_RVU                     (0x01U << IWDG_SR_RVU_Pos)              ///< Watchdog counter reload value update
+
+#define IWDG_SR_IVU_Pos                 (2)
+#define IWDG_SR_IVU                     (0x01U << IWDG_SR_IVU_Pos)
+
+#define IWDG_SR_UPDATE_Pos                 (3)
+#define IWDG_SR_UPDATE                     (0x01U << IWDG_SR_UPDATE_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_CR_IRQSEL_Pos          (0)
+#define IWDG_CR_IRQSEL              (0x01U << IWDG_CR_IRQSEL_Pos)           ///< IWDG overflow operation selection
+#define IWDG_CR_IRQCLR_Pos          (1)
+#define IWDG_CR_IRQCLR              (0x01U << IWDG_CR_IRQCLR_Pos)           ///< IWDG interrupt clear
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief IWDG_IGRN Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define IWDG_IGEN_IGEN_Pos          (0)
+#define IWDG_IGEN_IGEN              (0xFFFU << IWDG_CR_IRQSEL_Pos)          ///< IWDG Interrupt Generate value
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h
new file mode 100644
index 000000000..aa3605524
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h
@@ -0,0 +1,72 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_pwm.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_PWM_H
+#define __REG_PWM_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWM Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWM Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h
new file mode 100644
index 000000000..99f523225
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h
@@ -0,0 +1,219 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_pwr.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_PWR_H
+#define __REG_PWR_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_BASE                        (APB1PERIPH_BASE + 0x7000)              ///< Base Address: 0x40007000
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    union {
+        __IO u32 CR;                                                            ///< Control register,                             offset: 0x00
+        __IO u32 CR1;
+    };
+    union {
+        __IO u32 CSR;                                                               ///< Control Status register                        offset: 0x04
+        __IO u32 CSR1;
+    };
+    __IO u32 CR2;                                                               ///< Control register  2                            offset: 0x08
+    __IO u32 CR3;                                                               ///< Control register  3                            offset: 0x0C
+    __IO u32 CR4;                                                               ///< Control register  4                            offset: 0x10
+    __IO u32 CR5;                                                               ///< Control register  5                            offset: 0x14
+    __IO u32 CR6;                                                               ///< Control register  6                            offset: 0x18
+    __IO u32 SR;                                                                ///< Status  register                               offset: 0x1C
+    __IO u32 SCR;                                                               ///< clear status register                          offset: 0x20
+    __IO u32 CFGR;                                                              ///< Configuration register                         offset: 0x24
+} PWR_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR                             ((PWR_TypeDef*) PWR_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR_LDPS_Pos                 (0)
+#define PWR_CR_LDPS                     (0x01U  << PWR_CR_LDPS_Pos)             ///< Domain Write Protction
+
+#define PWR_CR_PDDS_Pos                 (1)
+#define PWR_CR_PDDS                     (0x01U  << PWR_CR_PDDS_Pos)             ///< Power Down Deepsleep
+#define PWR_CR_CSBF_Pos                 (3)
+#define PWR_CR_CSBF                     (0x01U  << PWR_CR_CSBF_Pos)             ///< Clear Standby Flag
+#define PWR_CR_LPR_Pos                  (13)
+#define PWR_CR_LPR                      (0x01U  << PWR_CR_LPR_Pos)              ///< Low power run
+#define PWR_CR_VOS_Pos                  (14)
+#define PWR_CR_VOS0                     (0x00U  << PWR_CR_VOS_Pos)              ///< Modulator Voltage Output Select 1.80V
+#define PWR_CR_VOS1                     (0x01U  << PWR_CR_VOS_Pos)              ///< Modulator Voltage Output Select 1.70V
+#define PWR_CR_VOS2                     (0x02U  << PWR_CR_VOS_Pos)              ///< Modulator Voltage Output Select 1.60V
+#define PWR_CR_VOS3                     (0x03U  << PWR_CR_VOS_Pos)              ///< Modulator Voltage Output Select 1.55V
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CSR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CSR_SBF_Pos                 (1)
+#define PWR_CSR_SBF                     (0x01U  << PWR_CSR_SBF_Pos)             ///< Standby Flag
+#define PWR_CSR_VOSRDY_Pos              (14)
+#define PWR_CSR_VOSRDY                  (0x01U  << PWR_CR_VOSRDY_Pos)           ///< Voltage Modulator Output Selection Ready
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR2 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR2_EWUP1_Pos                (0)
+#define PWR_CR2_EWUP1                    (0x01U << PWR_CR2_EWUP1_Pos)           ///< Enable WKUP1 wake-up pin
+#define PWR_CR2_EWUP2_Pos                (1)
+#define PWR_CR2_EWUP2                    (0x01U << PWR_CR2_EWUP2_Pos)           ///< Enable WKUP2 wake-up pin
+#define PWR_CR2_EWUP3_Pos                (2)
+#define PWR_CR2_EWUP3                    (0x01U << PWR_CR2_EWUP3_Pos)           ///< Enable WKUP3 wake-up pin
+#define PWR_CR2_EWUP4_Pos                (3)
+#define PWR_CR2_EWUP4                    (0x01U << PWR_CR2_EWUP4_Pos)           ///< Enable WKUP4 wake-up pin
+#define PWR_CR2_EWUP5_Pos                (4)
+#define PWR_CR2_EWUP5                    (0x01U << PWR_CR2_EWUP5_Pos)           ///< Enable WKUP5 wake-up pin
+#define PWR_CR2_EWUP6_Pos                (5)
+#define PWR_CR2_EWUP6                    (0x01U << PWR_CR2_EWUP6_Pos)           ///< Enable WKUP6 wake-up pin
+#define PWR_CR2_ENWU_Pos                 (15)
+#define PWR_CR2_ENWU                     (0x01U << PWR_CR2_ENWU_Pos)            ///< Enable wakeup module
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR3 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR3_WP1_Pos                (0)
+#define PWR_CR3_WP1                    (0x01U << PWR_CR3_WP1_Pos)               ///<  WKUP1 used for event polarity detection
+#define PWR_CR3_WP2_Pos                (1)
+#define PWR_CR3_WP2                    (0x01U << PWR_CR3_WP2_Pos)               ///<  WKUP2 used for event polarity detection
+#define PWR_CR3_WP3_Pos                (2)
+#define PWR_CR3_WP3                    (0x01U << PWR_CR3_WP3_Pos)               ///<  WKUP3 used for event polarity detection
+#define PWR_CR3_WP4_Pos                (3)
+#define PWR_CR3_WP4                    (0x01U << PWR_CR3_WP4_Pos)               ///<  WKUP4 used for event polarity detection
+#define PWR_CR3_WP5_Pos                (4)
+#define PWR_CR3_WP5                    (0x01U << PWR_CR3_WP5_Pos)               ///<  WKUP5 used for event polarity detection
+#define PWR_CR3_WP6_Pos                (5)
+#define PWR_CR3_WP6                    (0x01U << PWR_CR3_WP6_Pos)               ///<  WKUP6 used for event polarity detection
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR4 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR4_FILTSEL0_Pos           (0)
+#define PWR_CR4_FILTSEL0               (0x01U << PWR_CR4_FILTSEL0_Pos)          ///<  selection wake-up source
+#define PWR_CR4_FILTE0_Pos             (2)
+#define PWR_CR4_FILTE0                 (0x01U << PWR_CR4_FILTE0_Pos)            ///<  enable Filter 0
+#define PWR_CR4_FILTF0_Pos             (4)
+#define PWR_CR4_FILTF0                 (0x01U << PWR_CR4_FILTF0_Pos)            ///<  Whether the wake source passes through filter 0
+#define PWR_CR4_FILTCNT0_Pos           (8)
+#define PWR_CR4_FILTCNT0               (0xFFU << PWR_CR4_FILTCNT0_Pos)          ///<  Filter 0 counter
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR5 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR5_FILTSEL1_Pos           (0)
+#define PWR_CR5_FILTSEL1               (0x01U << PWR_CR5_FILTSEL1_Pos)          ///<  selection wake-up source
+#define PWR_CR5_FILTE1_Pos             (2)
+#define PWR_CR5_FILTE1                 (0x01U << PWR_CR5_FILTE1_Pos)            ///<  enable Filter 1
+#define PWR_CR5_FILTF1_Pos             (4)
+#define PWR_CR5_FILTF1                 (0x01U << PWR_CR5_FILTF1_Pos)            ///<  Whether the wake source passes through filter 1
+#define PWR_CR5_FILTCNT1_Pos           (8)
+#define PWR_CR5_FILTCNT1               (0xFFU << PWR_CR5_FILTCNT1_Pos)          ///<  Filter 1 counter
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CR6 register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CR6_STDBY_FS_W_Pos          (0)
+#define PWR_CR6_STDBY_FS_W1             (0x00U << PWR_CR6_STDBY_FS_W_Pos)       ///<  1 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W2             (0x01U << PWR_CR6_STDBY_FS_W_Pos)       ///<  2 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W3             (0x02U << PWR_CR6_STDBY_FS_W_Pos)       ///<  3 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W4             (0x03U << PWR_CR6_STDBY_FS_W_Pos)       ///<  4 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W5             (0x04U << PWR_CR6_STDBY_FS_W_Pos)       ///<  5 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W6             (0x05U << PWR_CR6_STDBY_FS_W_Pos)       ///<  6 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W7             (0x06U << PWR_CR6_STDBY_FS_W_Pos)       ///<  7 LSI cycle wake
+#define PWR_CR6_STDBY_FS_W8             (0x07U << PWR_CR6_STDBY_FS_W_Pos)       ///<  8 LSI cycle wake
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_SR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_SR_WUF1_Pos                (0)
+#define PWR_SR_WUF1                    (0x01U << PWR_SR_WUF1_Pos)               ///<  wake-up flag 1
+#define PWR_SR_WUF2_Pos                (1)
+#define PWR_SR_WUF2                    (0x01U << PWR_SR_WUF2_Pos)               ///<  wake-up flag 2
+#define PWR_SR_WUF3_Pos                (2)
+#define PWR_SR_WUF3                    (0x01U << PWR_SR_WUF3_Pos)               ///<  wake-up flag 3
+#define PWR_SR_WUF4_Pos                (3)
+#define PWR_SR_WUF4                    (0x01U << PWR_SR_WUF4_Pos)               ///<  wake-up flag 4
+#define PWR_SR_WUF5_Pos                (4)
+#define PWR_SR_WUF5                    (0x01U << PWR_SR_WUF5_Pos)               ///<  wake-up flag 5
+#define PWR_SR_WUF6_Pos                (5)
+#define PWR_SR_WUF6                    (0x01U << PWR_SR_WUF6_Pos)               ///<  wake-up flag 6
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_SCR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_SCR_CWUF1_Pos              (0)
+#define PWR_SCR_CWUF1                  (0x01U << PWR_SCR_CWUF1_Pos)             ///< clear wake-up flag 1 
+#define PWR_SCR_CWUF2_Pos              (1)
+#define PWR_SCR_CWUF2                  (0x01U << PWR_SCR_CWUF2_Pos)             ///< clear wake-up flag 2
+#define PWR_SCR_CWUF3_Pos              (2)
+#define PWR_SCR_CWUF3                  (0x01U << PWR_SCR_CWUF3_Pos)             ///< clear wake-up flag 3
+#define PWR_SCR_CWUF4_Pos              (3)
+#define PWR_SCR_CWUF4                  (0x01U << PWR_SCR_CWUF4_Pos)             ///< clear wake-up flag 4
+#define PWR_SCR_CWUF5_Pos              (4)
+#define PWR_SCR_CWUF5                  (0x01U << PWR_SCR_CWUF5_Pos)             ///< clear wake-up flag 5
+#define PWR_SCR_CWUF6_Pos              (5)
+#define PWR_SCR_CWUF6                  (0x01U << PWR_SCR_CWUF6_Pos)             ///< clear wake-up flag 6
+////////////////////////////////////////////////////////////////////////////////
+/// @brief PWR_CFGR register Bit definition
+////////////////////////////////////////////////////////////////////////////////
+#define PWR_CFGR_LSICALSEL_Pos         (0)
+#define PWR_CFGR_LSICALSEL             (0x1FU << PWR_CFGR_LSICALSEL_Pos)        ///< Enable internal clock calibration 
+#define PWR_CFGR_LSICAL_Pos            (5)
+#define PWR_CFGR_LSICAL                (0x1FU << PWR_CFGR_LSICAL_Pos)           ///< Internal high-speed clock calibration
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h
new file mode 100644
index 000000000..d378371fc
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h
@@ -0,0 +1,654 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_rcc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_RCC_H
+#define __REG_RCC_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_BASE                        (AHBPERIPH_BASE + 0x1000)               ///< Base Address: 0x40021000
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 CR;                                                                ///< Control Register                               offset: 0x00
+    __IO u32 CFGR;                                                              ///< Configuration Register                         offset: 0x04
+    __IO u32 CIR;                                                               ///< Clock Interrupt Register                       offset: 0x08
+    __IO u32 AHB3RSTR;                                                          ///< Advanced High Performance Bus 3 Reset Register offset: 0x0C
+    __IO u32 AHB2RSTR;                                                          ///< Advanced High Performance Bus 2 Reset Register offset: 0x10
+    __IO u32 AHBRSTR;                                                           ///<  Advanced High Performance Bus 1 Reset Register  offset: 0x14
+    __IO u32 APB2RSTR;                                                          ///< Advanced Peripheral Bus 2 Reset Register      offset: 0x18
+    __IO u32 APB1RSTR;                                                          ///< Advanced Peripheral Bus 1 Reset Register      offset: 0x1C
+    __IO u32 AHB3ENR;                                                           ///< Advanced High Performance Bus 3 Enable Register  offset: 0x20
+    __IO u32 AHB2ENR;                                                           ///< Advanced High Performance Bus 2 Enable Register  offset: 0x24
+    union {
+        __IO u32 AHBENR;                                                        ///< Advanced High Performance Bus 1 Enable Register  offset: 0x28
+        __IO u32 AHB1ENR;
+    };
+
+    __IO u32 APB2ENR;                                                           ///< Advanced Peripheral Bus 2 Enable Register      offset: 0x2C
+    __IO u32 APB1ENR;                                                           ///< Advanced Peripheral Bus 1 Enable Register      offset: 0x30
+
+
+    __IO u32 BDCR;                                                              ///< Backup Domain Control Register                  offset: 0x34
+    __IO u32 CSR;                                                               ///< Control Status Register                         offset: 0x38
+    __IO u32 SYSCFGR;                                                           ///< System Configuration Register                   offset: 0x3C
+    __IO u32 CFGR2;                                                             ///< System Configuration Register                  offset: 0x40
+    __IO u32 ICSCR;                                                             ///< Internal clock source calibration register     offset: 0x44
+    __IO u32 PLLCFGR;                                                           ///< PLL configures registers                       offset: 0x48
+    u32 Reserved1[13];                                                          ///< Reserved space
+    __IO u32 HSIDLY;                                                            ///< HSI delay register                             offset: 0x80
+    __IO u32 HSEDLY;                                                            ///< HSE delay register                             offset: 0x84
+    __IO u32 PLLDLY;                                                            ///< PLL delay register                             offset: 0x88
+} RCC_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC                             ((RCC_TypeDef*) RCC_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_CR_HSION_Pos                (0)
+#define RCC_CR_HSION                    (0x01U << RCC_CR_HSION_Pos)             ///< Internal High Speed clock enable
+
+#define RCC_CR_HSIRDY_Pos               (1)
+#define RCC_CR_HSIRDY                   (0x01U << RCC_CR_HSIRDY_Pos)            ///< Internal High Speed clock ready flag
+
+
+
+#define  RCC_CR_HSIDIV_Pos              (11)
+#define  RCC_CR_HSIDIV_0                (0x00U << RCC_CR_HSIDIV_Pos)            ///< HSI regardless of frequency
+#define  RCC_CR_HSIDIV_2                (0x01U << RCC_CR_HSIDIV_Pos)            ///< HSI 2 frequency division
+#define  RCC_CR_HSIDIV_4                (0x02U << RCC_CR_HSIDIV_Pos)            ///< HSI 4 frequency division
+#define  RCC_CR_HSIDIV_8                (0x03U << RCC_CR_HSIDIV_Pos)            ///< HSI eight points and frequency
+#define  RCC_CR_HSIDIV_16               (0x04U << RCC_CR_HSIDIV_Pos)            ///< HSI 16 points and frequency
+#define  RCC_CR_HSIDIV_32               (0x05U << RCC_CR_HSIDIV_Pos)            ///< HSI 32 points and frequency
+#define  RCC_CR_HSIDIV_64               (0x06U << RCC_CR_HSIDIV_Pos)            ///< HSI 64 frequency division
+#define  RCC_CR_HSIDIV_128              (0x07U << RCC_CR_HSIDIV_Pos)            ///< HSI 128 frequency division
+#define  RCC_CR_HSEON_Pos               (16)
+#define  RCC_CR_HSEON                   (0x01U << RCC_CR_HSEON_Pos)             ///< External High Speed clock enable
+#define  RCC_CR_HSERDY_Pos              (17)
+#define  RCC_CR_HSERDY                  (0x01U << RCC_CR_HSERDY_Pos)            ///< External High Speed clock ready flag
+#define  RCC_CR_HSEBYP_Pos              (18)
+#define  RCC_CR_HSEBYP                  (0x01U << RCC_CR_HSEBYP_Pos)            ///< External High Speed clock Bypass
+#define  RCC_CR_CSSON_Pos               (19)
+#define  RCC_CR_CSSON                   (0x01U << RCC_CR_CSSON_Pos)             ///< Clock Security System enable
+
+
+#define  RCC_CR_PLLON_Pos               (24)
+#define  RCC_CR_PLLON                   (0x01U << RCC_CR_PLLON_Pos)             ///< PLL enable
+#define  RCC_CR_PLLRDY_Pos              (25)
+#define  RCC_CR_PLLRDY                  (0x01U << RCC_CR_PLLRDY_Pos)            ///< PLL clock ready flag
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_CFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_CFGR_SW_Pos                 (0)
+#define RCC_CFGR_SW                     (0x03U << RCC_CFGR_SW_Pos)              ///< SW[1:0] bits (System clock Switch)
+#define RCC_CFGR_SW_HSI_DIV6            (0x00U << RCC_CFGR_SW_Pos)              ///< HSI/6 selected as system clock
+#define RCC_CFGR_SW_HSE                 (0x01U << RCC_CFGR_SW_Pos)              ///< HSE selected as system clock
+#define RCC_CFGR_SW_PLL                 (0x02U << RCC_CFGR_SW_Pos)              ///< PLL selected as system clock
+#define RCC_CFGR_SW_LSI                 (0x03U << RCC_CFGR_SW_Pos)              ///< LSI selected as system clock
+
+#define RCC_CFGR_SWS_Pos                (2)
+#define RCC_CFGR_SWS                    (0x03U << RCC_CFGR_SWS_Pos)             ///< SWS[1:0] bits (System Clock Switch Status)
+#define RCC_CFGR_SWS_HSI_DIV6           (0x00U << RCC_CFGR_SWS_Pos)             ///< HSI/6 oscillator used as system clock
+#define RCC_CFGR_SWS_HSE                (0x01U << RCC_CFGR_SWS_Pos)             ///< HSE oscillator used as system clock
+#define RCC_CFGR_SWS_PLL                (0x02U << RCC_CFGR_SWS_Pos)             ///< PLL used as system clock
+#define RCC_CFGR_SWS_LSI                (0x03U << RCC_CFGR_SWS_Pos)             ///< LSI used as system clock
+
+#define RCC_CFGR_HPRE_Pos               (4)
+#define RCC_CFGR_HPRE                   (0x0FU << RCC_CFGR_HPRE_Pos)            ///< HPRE[3:0] bits (AHB prescaler)
+#define RCC_CFGR_PPRE_0                 (0x01U << RCC_CFGR_HPRE_Pos)            ///< Bit 0
+#define RCC_CFGR_PPRE_1                 (0x02U << RCC_CFGR_HPRE_Pos)            ///< Bit 1
+#define RCC_CFGR_PPRE_2                 (0x04U << RCC_CFGR_HPRE_Pos)            ///< Bit 2
+#define RCC_CFGR_PPRE_3                 (0x08U << RCC_CFGR_HPRE_Pos)            ///< Bit 3
+
+#define RCC_CFGR_HPRE_DIV1              (0x00U << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK not divided
+#define RCC_CFGR_HPRE_DIV2              (0x08U << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 2
+#define RCC_CFGR_HPRE_DIV4              (0x09U << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 4
+#define RCC_CFGR_HPRE_DIV8              (0x0AU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 8
+#define RCC_CFGR_HPRE_DIV16             (0x0BU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 16
+#define RCC_CFGR_HPRE_DIV64             (0x0CU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 64
+#define RCC_CFGR_HPRE_DIV128            (0x0DU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 128
+#define RCC_CFGR_HPRE_DIV256            (0x0EU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 256
+#define RCC_CFGR_HPRE_DIV512            (0x0FU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 512
+
+#define RCC_CFGR_PPRE1_Pos              (8)
+#define RCC_CFGR_PPRE1                  (0x07U << RCC_CFGR_PPRE1_Pos)           ///< PRE1[2:0] bits (APB1 prescaler)
+#define RCC_CFGR_PPRE1_0                (0x01U << RCC_CFGR_PPRE1_Pos)           ///< Bit 0
+#define RCC_CFGR_PPRE1_1                (0x02U << RCC_CFGR_PPRE1_Pos)           ///< Bit 1
+#define RCC_CFGR_PPRE1_2                (0x04U << RCC_CFGR_PPRE1_Pos)           ///< Bit 2
+
+#define RCC_CFGR_PPRE1_DIV1             (0x00U << RCC_CFGR_PPRE1_Pos)           ///< APB1 = HCLK not divided
+#define RCC_CFGR_PPRE1_DIV2             (0x04U << RCC_CFGR_PPRE1_Pos)           ///< APB1 = HCLK divided by 2
+#define RCC_CFGR_PPRE1_DIV4             (0x05U << RCC_CFGR_PPRE1_Pos)           ///< APB1 = HCLK divided by 4
+#define RCC_CFGR_PPRE1_DIV8             (0x06U << RCC_CFGR_PPRE1_Pos)           ///< APB1 = HCLK divided by 8
+#define RCC_CFGR_PPRE1_DIV16            (0x07U << RCC_CFGR_PPRE1_Pos)           ///< APB1 = HCLK divided by 16
+
+#define RCC_CFGR_PPRE2_Pos              (11)
+#define RCC_CFGR_PPRE2                  (0x07U << RCC_CFGR_PPRE2_Pos)           ///< PRE2[2:0] bits (APB2 prescaler)
+#define RCC_CFGR_PPRE2_0                (0x01U << RCC_CFGR_PPRE2_Pos)           ///< Bit 0
+#define RCC_CFGR_PPRE2_1                (0x02U << RCC_CFGR_PPRE2_Pos)           ///< Bit 1
+#define RCC_CFGR_PPRE2_2                (0x04U << RCC_CFGR_PPRE2_Pos)           ///< Bit 2
+
+#define RCC_CFGR_PPRE2_DIV1             (0x00U << RCC_CFGR_PPRE2_Pos)           ///< APB2 = HCLK not divided
+#define RCC_CFGR_PPRE2_DIV2             (0x04U << RCC_CFGR_PPRE2_Pos)           ///< APB2 = HCLK divided by 2
+#define RCC_CFGR_PPRE2_DIV4             (0x05U << RCC_CFGR_PPRE2_Pos)           ///< APB2 = HCLK divided by 4
+#define RCC_CFGR_PPRE2_DIV8             (0x06U << RCC_CFGR_PPRE2_Pos)           ///< APB2 = HCLK divided by 8
+#define RCC_CFGR_PPRE2_DIV16            (0x07U << RCC_CFGR_PPRE2_Pos)           ///< APB2 = HCLK divided by 16
+
+
+#define RCC_CFGR_USBPRE_Pos             (22)
+#define RCC_CFGR_USBPRE                 (0x03U << RCC_CFGR_USBPRE_Pos)          ///< USB prescaler BIT[1:0]
+
+#define RCC_CFGR_MCO_Pos                (24)
+#define RCC_CFGR_MCO                    (0x07U << RCC_CFGR_MCO_Pos)             ///< MCO[2:0] bits (Microcontroller Clock Output)
+#define RCC_CFGR_MCO_NOCLOCK            (0x00U << RCC_CFGR_MCO_Pos)             ///< No clock
+#define RCC_CFGR_MCO_LSI                (0x02U << RCC_CFGR_MCO_Pos)             ///< LSI clock
+#define RCC_CFGR_MCO_LSE                (0x03U << RCC_CFGR_MCO_Pos)             ///< LSE clock
+#define RCC_CFGR_MCO_SYSCLK             (0x04U << RCC_CFGR_MCO_Pos)             ///< System clock selected
+#define RCC_CFGR_MCO_HSI                (0x05U << RCC_CFGR_MCO_Pos)             ///< Internal 48 MHz RC oscillator clock selected
+#define RCC_CFGR_MCO_HSE                (0x06U << RCC_CFGR_MCO_Pos)             ///< External 1-25 MHz oscillator clock selected
+#define RCC_CFGR_MCO_PLL                (0x07U << RCC_CFGR_MCO_Pos)             ///< PLL clock divided by 2 selected
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_CIR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_CIR_LSIRDYF_Pos             (0)
+#define RCC_CIR_LSIRDYF                 (0x01U << RCC_CIR_LSIRDYF_Pos)          ///< LSI Ready Interrupt flag
+
+#define RCC_CIR_LSERDYF_Pos             (1)
+#define RCC_CIR_LSERDYF                 (0x01U << RCC_CIR_LSERDYF_Pos)          ///< LSE Ready Interrupt flag
+
+#define RCC_CIR_HSIRDYF_Pos             (2)
+#define RCC_CIR_HSIRDYF                 (0x01U << RCC_CIR_HSIRDYF_Pos)          ///< HSI Ready Interrupt flag
+#define RCC_CIR_HSERDYF_Pos             (3)
+#define RCC_CIR_HSERDYF                 (0x01U << RCC_CIR_HSERDYF_Pos)          ///< HSE Ready Interrupt flag
+
+#define RCC_CIR_PLLRDYF_Pos             (4)
+#define RCC_CIR_PLLRDYF                 (0x01U << RCC_CIR_PLLRDYF_Pos)          ///< PLL Ready Interrupt flag
+
+#define RCC_CIR_CSSF_Pos                (7)
+#define RCC_CIR_CSSF                    (0x01U << RCC_CIR_CSSF_Pos)             ///< Clock Security System Interrupt flag
+#define RCC_CIR_LSIRDYIE_Pos            (8)
+#define RCC_CIR_LSIRDYIE                (0x01U << RCC_CIR_LSIRDYIE_Pos)         ///< LSI Ready Interrupt Enable
+
+#define RCC_CIR_LSERDYIE_Pos            (9)
+#define RCC_CIR_LSERDYIE                (0x01U << RCC_CIR_LSERDYIE_Pos)         ///< LSE Ready Interrupt Enable
+
+#define RCC_CIR_HSIRDYIE_Pos            (10)
+#define RCC_CIR_HSIRDYIE                (0x01U << RCC_CIR_HSIRDYIE_Pos)         ///< HSI Ready Interrupt Enable
+#define RCC_CIR_HSERDYIE_Pos            (11)
+#define RCC_CIR_HSERDYIE                (0x01U << RCC_CIR_HSIRDYIE_Pos)         ///< HSE Ready Interrupt Enable
+
+#define RCC_CIR_PLLRDYIE_Pos            (12)
+#define RCC_CIR_PLLRDYIE                (0x01U << RCC_CIR_PLLRDYIE_Pos)         ///< PLL Ready Interrupt Enable
+
+#define RCC_CIR_LSIRDYC_Pos             (16)
+#define RCC_CIR_LSIRDYC                 (0x01U << RCC_CIR_LSIRDYC_Pos)          ///< LSI Ready Interrupt Clear
+
+#define RCC_CIR_LSERDYC_Pos             (17)
+#define RCC_CIR_LSERDYC                 (0x01U << RCC_CIR_LSERDYC_Pos)          ///< LSE Ready Interrupt Clear
+
+#define RCC_CIR_HSIRDYC_Pos             (18)
+#define RCC_CIR_HSIRDYC                 (0x01U << RCC_CIR_HSIRDYC_Pos)          ///< HSI Ready Interrupt Clear
+#define RCC_CIR_HSERDYC_Pos             (19)
+#define RCC_CIR_HSERDYC                 (0x01U << RCC_CIR_HSERDYC_Pos)          ///< HSE Ready Interrupt Clear
+
+#define RCC_CIR_PLLRDYC_Pos             (20)
+#define RCC_CIR_PLLRDYC                 (0x01U << RCC_CIR_PLLRDYC_Pos)          ///< PLL Ready Interrupt Clear
+
+#define RCC_CIR_CSSC_Pos                (23)
+#define RCC_CIR_CSSC                    (0x01U << RCC_CIR_CSSC_Pos)             ///< Clock Security System Interrupt Clear
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_APB2RSTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_APB2RSTR_TIM1_Pos           (0)
+#define RCC_APB2RSTR_TIM1               (0x01U << RCC_APB2RSTR_TIM1_Pos)        ///< TIM1 reset
+#define RCC_APB2RSTR_TIM8_Pos           (1)
+#define RCC_APB2RSTR_TIM8               (0x01U << RCC_APB2RSTR_TIM8_Pos)        ///< TIM8 reset
+#define RCC_APB2RSTR_UART1_Pos          (4)
+#define RCC_APB2RSTR_UART1              (0x01U << RCC_APB2RSTR_UART1_Pos)       ///< UART1 reset
+#define RCC_APB2RSTR_UART6_Pos          (5)
+#define RCC_APB2RSTR_UART6              (0x01U << RCC_APB2RSTR_UART6_Pos)       ///< UART6 reset
+#define RCC_APB2RSTR_ADC1_Pos           (8)
+#define RCC_APB2RSTR_ADC1               (0x01U << RCC_APB2RSTR_ADC1_Pos)        ///< ADC1 reset
+#define RCC_APB2RSTR_ADC2_Pos           (9)
+#define RCC_APB2RSTR_ADC2               (0x01U << RCC_APB2RSTR_ADC2_Pos)        ///< ADC2 reset
+#define RCC_APB2RSTR_ADC3_Pos           (10)
+#define RCC_APB2RSTR_ADC3               (0x01U << RCC_APB2RSTR_ADC3_Pos)        ///< ADC3 reset
+#define RCC_APB2RSTR_SPI1_Pos           (12)
+#define RCC_APB2RSTR_SPI1               (0x01U << RCC_APB2RSTR_SPI1_Pos)        ///< SPI1 reset
+#define RCC_APB2RSTR_SYSCFG_Pos         (14)
+#define RCC_APB2RSTR_SYSCFG             (0x01U << RCC_APB2RSTR_SYSCFG_Pos)      ///< SYSCFG reset
+#define RCC_APB2RSTR_COMP_Pos           (15)
+#define RCC_APB2RSTR_COMP               (0x01U << RCC_APB2RSTR_COMP_Pos)        ///< COMP reset
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHB3RSTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHB3RSTR_FSMC_Pos           (0)
+#define RCC_AHB3RSTR_FSMC               (0x01U << RCC_AHB3RSTR_FSMC_Pos)        ///< FSMC reset
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_APB1RSTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_APB1RSTR_TIM2_Pos           (0)
+#define RCC_APB1RSTR_TIM2               (0x01U << RCC_APB1RSTR_TIM2_Pos)        ///< Timer 2 reset
+#define RCC_APB1RSTR_TIM3_Pos           (1)
+#define RCC_APB1RSTR_TIM3               (0x01U << RCC_APB1RSTR_TIM3_Pos)        ///< Timer 3 reset
+
+#define RCC_APB1RSTR_TIM4_Pos           (2)
+#define RCC_APB1RSTR_TIM4               (0x01U << RCC_APB1RSTR_TIM4_Pos)        ///< Timer 4 reset
+#define RCC_APB1RSTR_TIM5_Pos           (3)
+#define RCC_APB1RSTR_TIM5               (0x01U << RCC_APB1RSTR_TIM5_Pos)        ///< Timer 5 reset
+#define RCC_APB1RSTR_TIM6_Pos           (4)
+#define RCC_APB1RSTR_TIM6               (0x01U << RCC_APB1RSTR_TIM6_Pos)        ///< Timer 6 reset
+#define RCC_APB1RSTR_TIM7_Pos           (5)
+#define RCC_APB1RSTR_TIM7               (0x01U << RCC_APB1RSTR_TIM7_Pos)        ///< Timer 7 reset
+
+#define RCC_APB1RSTR_WWDG_Pos           (11)
+#define RCC_APB1RSTR_WWDG               (0x01U << RCC_APB1RSTR_WWDG_Pos)        ///< Window Watchdog reset
+#define RCC_APB1RSTR_SPI2_Pos           (14)
+#define RCC_APB1RSTR_SPI2               (0x01U << RCC_APB1RSTR_SPI2_Pos)        ///< SPI 2 reset
+#define RCC_APB1RSTR_SPI3_Pos           (15)
+#define RCC_APB1RSTR_SPI3               (0x01U << RCC_APB1RSTR_SPI3_Pos)        ///< SPI 3 reset
+
+#define RCC_APB1RSTR_UART2_Pos          (17)
+#define RCC_APB1RSTR_UART2              (0x01U << RCC_APB1RSTR_UART2_Pos)       ///< UART 2 reset
+#define RCC_APB1RSTR_UART3_Pos          (18)
+#define RCC_APB1RSTR_UART3              (0x01U << RCC_APB1RSTR_UART3_Pos)       ///< UART 3 reset
+#define RCC_APB1RSTR_UART4_Pos          (19)
+#define RCC_APB1RSTR_UART4              (0x01U << RCC_APB1RSTR_UART4_Pos)       ///< UART 4 reset
+#define RCC_APB1RSTR_UART5_Pos          (20)
+#define RCC_APB1RSTR_UART5              (0x01U << RCC_APB1RSTR_UART5_Pos)       ///< UART 5 reset
+#define RCC_APB1RSTR_I2C1_Pos           (21)
+#define RCC_APB1RSTR_I2C1               (0x01U << RCC_APB1RSTR_I2C1_Pos)        ///< I2C 1 reset
+#define RCC_APB1RSTR_I2C2_Pos           (22)
+#define RCC_APB1RSTR_I2C2               (0x01U << RCC_APB1RSTR_I2C2_Pos)        ///< I2C 2 reset
+
+#define RCC_APB1RSTR_CRS_Pos            (24)
+#define RCC_APB1RSTR_CRS                (0x01U << RCC_APB1RSTR_CRS_Pos)         ///< CRS reset
+#define RCC_APB1RSTR_CAN_Pos            (25)
+#define RCC_APB1RSTR_CAN                (0x01U << RCC_APB1RSTR_CAN_Pos)         ///< CAN reset
+
+#define RCC_APB1RSTR_BKP_Pos            (27)
+#define RCC_APB1RSTR_BKP                (0x01U << RCC_APB1RSTR_BKP_Pos)         ///< Backup interface reset
+
+#define RCC_APB1RSTR_PWR_Pos            (28)
+#define RCC_APB1RSTR_PWR                (0x01U << RCC_APB1RSTR_PWR_Pos)         ///< Power interface reset
+#define RCC_APB1RSTR_DAC_Pos            (29)
+#define RCC_APB1RSTR_DAC                (0x01U << RCC_APB1RSTR_DAC_Pos)         ///< DAC interface reset
+
+
+#define RCC_APB1RSTR_UART7_Pos          (30)
+#define RCC_APB1RSTR_UART7              (0x01U << RCC_APB1RSTR_UART7_Pos)        ///< UART7 reset
+#define RCC_APB1RSTR_UART8_Pos          (31)
+#define RCC_APB1RSTR_UART8              (0x01U << RCC_APB1RSTR_UART8_Pos)        ///< UART8 reset
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHB2RSTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHB2RSTR_USBFS_Pos          (7)
+#define RCC_AHB2RSTR_USBFS              (0x01U << RCC_AHB2RSTR_USBFS_Pos)       ///< USBFS reset
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHB3ENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHB3ENR_FSMC_Pos            (0)
+#define RCC_AHB3ENR_FSMC                (0x01U << RCC_AHB3ENR_FSMC_Pos)       ///< FSMC reset
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHB2ENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHB2ENR_USBFS_Pos           (7)
+#define RCC_AHB2ENR_USBFS               (0x01U << RCC_AHB2ENR_USBFS_Pos)       ///< USBFS reset
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHBENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+
+
+#define RCC_AHBENR_GPIOA_Pos             (0)
+#define RCC_AHBENR_GPIOA                 (0x01U << RCC_AHBENR_GPIOA_Pos)          ///< GPIOA clock enable
+#define RCC_AHBENR_GPIOB_Pos             (1)
+#define RCC_AHBENR_GPIOB                 (0x01U << RCC_AHBENR_GPIOB_Pos)          ///< GPIOB clock enable
+#define RCC_AHBENR_GPIOC_Pos             (2)
+#define RCC_AHBENR_GPIOC                 (0x01U << RCC_AHBENR_GPIOC_Pos)          ///< GPIOC clock enable
+#define RCC_AHBENR_GPIOD_Pos             (3)
+#define RCC_AHBENR_GPIOD                 (0x01U << RCC_AHBENR_GPIOD_Pos)          ///< GPIOD clock enable
+#define RCC_AHBENR_GPIOE_Pos             (4)
+#define RCC_AHBENR_GPIOE                 (0x01U << RCC_AHBENR_GPIOE_Pos)          ///< GPIOE clock enable
+#define RCC_AHBENR_GPIOF_Pos             (5)
+#define RCC_AHBENR_GPIOF                 (0x01U << RCC_AHBENR_GPIOF_Pos)          ///< GPIOF clock enable
+#define RCC_AHBENR_GPIOG_Pos             (6)
+#define RCC_AHBENR_GPIOG                 (0x01U << RCC_AHBENR_GPIOG_Pos)          ///< GPIOG clock enable
+#define RCC_AHBENR_GPIOH_Pos             (7)
+#define RCC_AHBENR_GPIOH                 (0x01U << RCC_AHBENR_GPIOH_Pos)          ///< GPIOH clock enable
+#define RCC_AHBENR_SDIO_Pos             (10)
+#define RCC_AHBENR_SDIO                 (0x01U << RCC_AHBENR_SDIO_Pos)          ///< SDIO clock enable
+#define RCC_AHBENR_CRC_Pos              (12)
+#define RCC_AHBENR_CRC                  (0x01U << RCC_AHBENR_CRC_Pos)          ///< CRC clock enable
+#define RCC_AHBENR_FLASH_Pos            (13)
+#define RCC_AHBENR_FLASH                (0x01U << RCC_AHBENR_FLASH_Pos)          ///< FLASH clock enable
+#define RCC_AHBENR_SRAM_Pos             (14)
+#define RCC_AHBENR_SRAM                 (0x01U << RCC_AHBENR_SRAM_Pos)          ///< SRAM clock enable
+#define RCC_AHBENR_DMA1_Pos             (21)
+#define RCC_AHBENR_DMA1                 (0x01U << RCC_AHBENR_DMA1_Pos)          ///< DMA1 clock enable
+#define RCC_AHBENR_DMA2_Pos             (22)
+#define RCC_AHBENR_DMA2                 (0x01U << RCC_AHBENR_DMA2_Pos)          ///< DMA2 clock enable
+#define RCC_AHBENR_ETHMAC_Pos           (25)
+#define RCC_AHBENR_ETHMAC               (0x01U << RCC_AHBENR_ETHMAC_Pos)        ///< ETHMAC clock enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_APB2ENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_APB2ENR_TIM1_Pos         (0)
+#define RCC_APB2ENR_TIM1             (0x01U << RCC_APB2ENR_TIM1_Pos)          ///< TIM1 enable
+#define RCC_APB2ENR_TIM8_Pos         (1)
+#define RCC_APB2ENR_TIM8             (0x01U << RCC_APB2ENR_TIM8_Pos)          ///< TIM8 enable
+#define RCC_APB2ENR_UART1_Pos        (4)
+#define RCC_APB2ENR_UART1            (0x01U << RCC_APB2ENR_UART1_Pos)         ///< UART1 enable
+#define RCC_APB2ENR_UART6_Pos        (5)
+#define RCC_APB2ENR_UART6            (0x01U << RCC_APB2ENR_UART6_Pos)         ///< UART6 enable
+#define RCC_APB2ENR_ADC1_Pos         (8)
+#define RCC_APB2ENR_ADC1             (0x01U << RCC_APB2ENR_ADC1_Pos)          ///< ADC1 enable
+#define RCC_APB2ENR_ADC2_Pos         (9)
+#define RCC_APB2ENR_ADC2             (0x01U << RCC_APB2ENR_ADC2_Pos)          ///< ADC2 enable
+#define RCC_APB2ENR_ADC3_Pos         (10)
+#define RCC_APB2ENR_ADC3             (0x01U << RCC_APB2ENR_ADC3_Pos)          ///< ADC3 enable
+#define RCC_APB2ENR_SPI1_Pos         (12)
+#define RCC_APB2ENR_SPI1             (0x01U << RCC_APB2ENR_SPI1_Pos)          ///< SPI1 enable
+#define RCC_APB2ENR_EXTI_Pos         (14)
+#define RCC_APB2ENR_EXTI             (0x01U << RCC_APB2ENR_EXTI_Pos)          ///< EXTI Block enable
+#define RCC_APB2ENR_SYSCFG_Pos       (14)
+#define RCC_APB2ENR_SYSCFG           (0x01U << RCC_APB2ENR_SYSCFG_Pos)        ///< SYSCFG enable
+#define RCC_APB2ENR_COMP_Pos         (15)
+#define RCC_APB2ENR_COMP             (0x01U << RCC_APB2ENR_COMP_Pos)          ///< COMP enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_APB1ENR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_APB1ENR_TIM2_Pos            (0)
+#define RCC_APB1ENR_TIM2                (0x01U << RCC_APB1ENR_TIM2_Pos)         ///< Timer 2 clock enable
+
+#define RCC_APB1ENR_TIM3_Pos            (1)
+#define RCC_APB1ENR_TIM3                (0x01U << RCC_APB1ENR_TIM3_Pos)         ///< Timer 3 clock enabled
+
+#define RCC_APB1ENR_TIM4_Pos            (2)
+#define RCC_APB1ENR_TIM4                (0x01U << RCC_APB1ENR_TIM4_Pos)         ///< Timer 4 clock enable
+
+
+#define RCC_APB1ENR_TIM5_Pos            (3)
+#define RCC_APB1ENR_TIM5                (0x01U << RCC_APB1ENR_TIM5_Pos)        ///< TIM5 Timer clock enable
+#define RCC_APB1ENR_TIM6_Pos            (4)
+#define RCC_APB1ENR_TIM6                (0x01U << RCC_APB1ENR_TIM6_Pos)        ///< TIM6 Timer clock enable
+#define RCC_APB1ENR_TIM7_Pos            (5)
+#define RCC_APB1ENR_TIM7                (0x01U << RCC_APB1ENR_TIM7_Pos)        ///< TIM7 Timer clock enable
+
+#define RCC_APB1ENR_WWDG_Pos            (11)
+#define RCC_APB1ENR_WWDG                (0x01U << RCC_APB1ENR_WWDG_Pos)         ///< Window Watchdog clock enable
+
+
+#define RCC_APB1ENR_SPI2_Pos            (14)
+#define RCC_APB1ENR_SPI2                (0x01U << RCC_APB1ENR_SPI2_Pos)         ///< SPI 2 clock enable
+#define RCC_APB1ENR_SPI3_Pos            (15)
+#define RCC_APB1ENR_SPI3                (0x01U << RCC_APB1ENR_SPI3_Pos)         ///< SPI 3 clock enable
+
+#define RCC_APB1ENR_UART2_Pos           (17)
+#define RCC_APB1ENR_UART2               (0x01U << RCC_APB1ENR_UART2_Pos)        ///< UART 2 clock enable
+#define RCC_APB1ENR_UART3_Pos           (18)
+#define RCC_APB1ENR_UART3               (0x01U << RCC_APB1ENR_UART3_Pos)        ///< UART 3 clock enable
+#define RCC_APB1ENR_UART4_Pos           (19)
+#define RCC_APB1ENR_UART4               (0x01U << RCC_APB1ENR_UART4_Pos)        ///< UART 4 clock enable
+#define RCC_APB1ENR_UART5_Pos           (20)
+#define RCC_APB1ENR_UART5               (0x01U << RCC_APB1ENR_UART5_Pos)        ///< UART 5 clock enable
+#define RCC_APB1ENR_I2C1_Pos            (21)
+#define RCC_APB1ENR_I2C1                (0x01U << RCC_APB1ENR_I2C1_Pos)         ///< I2C 1 clock enable
+#define RCC_APB1ENR_I2C2_Pos            (22)
+#define RCC_APB1ENR_I2C2                (0x01U << RCC_APB1ENR_I2C2_Pos)         ///< I2C 2 clock enable
+#define RCC_APB1ENR_CRS_Pos             (24)
+#define RCC_APB1ENR_CRS                 (0x01U << RCC_APB1ENR_CRS_Pos)         ///< CRS 4 clock enable
+#define RCC_APB1ENR_CAN_Pos             (25)
+#define RCC_APB1ENR_CAN                 (0x01U << RCC_APB1ENR_CAN_Pos)         ///< CAN 5 clock enable
+
+
+
+#define RCC_APB1ENR_BKP_Pos             (27)
+#define RCC_APB1ENR_BKP                 (0x01U << RCC_APB1ENR_BKP_Pos)          ///< Backup interface clock enable
+
+#define RCC_APB1ENR_PWR_Pos             (28)
+#define RCC_APB1ENR_PWR                 (0x01U << RCC_APB1ENR_PWR_Pos)          ///< Power interface clock enable
+
+#define RCC_APB1ENR_DBGMCU_Pos          (28)
+#define RCC_APB1ENR_DBGMCU              (0x01U << RCC_APB1ENR_DBGMCU_Pos)       ///< DBGMCU clock enable
+
+
+#define RCC_APB1ENR_DAC_Pos             (29)
+#define RCC_APB1ENR_DAC                 (0x01U << RCC_APB1ENR_DAC_Pos)          ///< DAC interface clock enable
+#define RCC_APB1ENR_UART7_Pos            (30)
+#define RCC_APB1ENR_UART7                (0x01U << RCC_APB1ENR_UART7_Pos)       ///< UART7 interface clock enable
+#define RCC_APB1ENR_UART8_Pos            (31)
+#define RCC_APB1ENR_UART8                (0x01U << RCC_APB1ENR_UART8_Pos)       ///< UART8 interface clock enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_BDCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_BDCR_LSEON_Pos              (0)
+#define RCC_BDCR_LSEON                  (0x01U << RCC_BDCR_LSEON_Pos)           ///< External Low Speed oscillator enable
+#define RCC_BDCR_LSERDY_Pos             (1)
+#define RCC_BDCR_LSERDY                 (0x01U << RCC_BDCR_LSERDY_Pos)          ///< External Low Speed oscillator Ready
+#define RCC_BDCR_LSEBYP_Pos             (2)
+#define RCC_BDCR_LSEBYP                 (0x01U << RCC_BDCR_LSEBYP_Pos)          ///< External Low Speed oscillator Bypass
+
+#define RCC_BDCR_RTCSEL_Pos             (8)
+#define RCC_BDCR_RTCSEL                 (0x03U << RCC_BDCR_RTCSEL_Pos)          ///< RTCSEL[1:0] bits (RTC clock source selection)
+#define RCC_BDCR_RTCSEL_LSE             (0x01U << RCC_BDCR_RTCSEL_Pos)          ///< LSE oscillator clock used as RTC clock
+#define RCC_BDCR_RTCSEL_LSI             (0x02U << RCC_BDCR_RTCSEL_Pos)          ///< LSI oscillator clock used as RTC clock
+#define RCC_BDCR_RTCSEL_HSE             (0x03U << RCC_BDCR_RTCSEL_Pos)          ///< HSE oscillator clock divided by 128 used as RTC clock
+
+#define RCC_BDCR_RTCEN_Pos              (15)
+#define RCC_BDCR_RTCEN                  (0x01U << RCC_BDCR_RTCEN_Pos)           ///< RTC clock enable
+#define RCC_BDCR_BDRST_Pos              (16)
+#define RCC_BDCR_BDRST                  (0x01U << RCC_BDCR_BDRST_Pos)           ///< Backup domain software reset
+#define RCC_BDCR_DBP_Pos                (24)
+#define RCC_BDCR_DBP                    (0x01U << RCC_BDCR_DBP_Pos)             ///< DBP clock enable
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_CSR_LSION_Pos               (0)
+#define RCC_CSR_LSION                   (0x01U << RCC_CSR_LSION_Pos)            ///< Internal Low Speed oscillator enable
+#define RCC_CSR_LSIRDY_Pos              (1)
+#define RCC_CSR_LSIRDY                  (0x01U << RCC_CSR_LSIRDY_Pos)           ///< Internal Low Speed oscillator Ready
+#define RCC_CSR_LSIOENLV_Pos            (5)
+#define RCC_CSR_LSIOENLV                (0x01U << RCC_CSR_LSIOENLV_Pos)         ///< LSI output enable lower voltage
+#define RCC_CSR_PVDRSTEN_Pos            (6)
+#define RCC_CSR_PVDRSTEN                (0x01U << RCC_CSR_PVDRSTEN_Pos)         ///< PVD reset enable
+#define RCC_CSR_LOCKUPEN_Pos            (7)
+#define RCC_CSR_LOCKUPEN                (0x01U << RCC_CSR_LOCKUPEN_Pos)         ///< CPU lockup reset enable
+#define RCC_CSR_VDTRSTNEN_Pos           (8)
+#define RCC_CSR_VDTRSTNEN               (0x01U << RCC_CSR_VDTRSTNEN_Pos)        ///< Voltage detect reset enable
+#define RCC_CSR_VDTRSTF_Pos             (21)
+#define RCC_CSR_VDTRSTF                 (0x01U << RCC_CSR_VDTRSTF_Pos)           ///< Voltage detect reset flag
+#define RCC_CSR_PVDRSTF_Pos             (22)
+#define RCC_CSR_PVDRSTF                 (0x01U << RCC_CSR_PVDRSTF_Pos)           ///< PVD reset flag
+#define RCC_CSR_LOCKUPF_Pos             (23)
+#define RCC_CSR_LOCKUPF                 (0x01U << RCC_CSR_LOCKUPF_Pos)           ///< CPU lockup reset flag
+
+#define RCC_CSR_RMVF_Pos                (24)
+#define RCC_CSR_RMVF                    (0x01U << RCC_CSR_RMVF_Pos)             ///< Remove reset flag
+#define RCC_CSR_PINRSTF_Pos             (26)
+#define RCC_CSR_PINRSTF                 (0x01U << RCC_CSR_PINRSTF_Pos)          ///< PIN reset flag
+
+#define RCC_CSR_PORRSTF_Pos             (27)
+#define RCC_CSR_PORRSTF                 (0x01U << RCC_CSR_PORRSTF_Pos)          ///< POR/PDR reset flag
+
+#define RCC_CSR_SFTRSTF_Pos             (28)
+#define RCC_CSR_SFTRSTF                 (0x01U << RCC_CSR_SFTRSTF_Pos)          ///< Software Reset flag
+
+#define RCC_CSR_IWDGRSTF_Pos            (29)
+#define RCC_CSR_IWDGRSTF                (0x01U << RCC_CSR_IWDGRSTF_Pos)         ///< Independent Watchdog reset flag
+
+#define RCC_CSR_WWDGRSTF_Pos            (30)
+#define RCC_CSR_WWDGRSTF                (0x01U << RCC_CSR_WWDGRSTF_Pos)         ///< Window watchdog reset flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_AHBRSTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_AHBRSTR_GPIOA_Pos       (0)
+#define RCC_AHBRSTR_GPIOA           (0x01U << RCC_AHBRSTR_GPIOA_Pos)        ///< GPIOA clock reset
+#define RCC_AHBRSTR_GPIOB_Pos       (1)
+#define RCC_AHBRSTR_GPIOB           (0x01U << RCC_AHBRSTR_GPIOB_Pos)        ///< GPIOB clock reset
+#define RCC_AHBRSTR_GPIOC_Pos       (2)
+#define RCC_AHBRSTR_GPIOC           (0x01U << RCC_AHBRSTR_GPIOC_Pos)        ///< GPIOC clock reset
+#define RCC_AHBRSTR_GPIOD_Pos       (3)
+#define RCC_AHBRSTR_GPIOD           (0x01U << RCC_AHBRSTR_GPIOD_Pos)        ///< GPIOD clock reset
+#define RCC_AHBRSTR_GPIOE_Pos       (4)
+#define RCC_AHBRSTR_GPIOE           (0x01U << RCC_AHBRSTR_GPIOE_Pos)        ///< GPIOE clock reset
+#define RCC_AHBRSTR_GPIOF_Pos       (5)
+#define RCC_AHBRSTR_GPIOF           (0x01U << RCC_AHBRSTR_GPIOF_Pos)        ///< GPIOF clock reset
+#define RCC_AHBRSTR_GPIOG_Pos       (6)
+#define RCC_AHBRSTR_GPIOG           (0x01U << RCC_AHBRSTR_GPIOG_Pos)        ///< GPIOG clock reset
+#define RCC_AHBRSTR_GPIOH_Pos       (7)
+#define RCC_AHBRSTR_GPIOH           (0x01U << RCC_AHBRSTR_GPIOH_Pos)        ///< GPIOH clock reset
+#define RCC_AHBRSTR_SDIO_Pos       (10)
+#define RCC_AHBRSTR_SDIO           (0x01U << RCC_AHBRSTR_SDIO_Pos)          ///< SDIO clock reset
+#define RCC_AHBRSTR_CRC_Pos        (12)
+#define RCC_AHBRSTR_CRC            (0x01U << RCC_AHBRSTR_CRC_Pos)           ///< CRC clock reset
+#define RCC_AHBRSTR_DMA1_Pos       (21)
+#define RCC_AHBRSTR_DMA1           (0x01U << RCC_AHBRSTR_DMA1_Pos)          ///< DMA1 clock reset
+#define RCC_AHBRSTR_DMA2_Pos       (22)
+#define RCC_AHBRSTR_DMA2           (0x01U << RCC_AHBRSTR_DMA2_Pos)          ///< DMA2 clock reset
+#define RCC_AHBRSTR_ETHMAC_Pos     (25)
+#define RCC_AHBRSTR_ETHMAC         (0x01U << RCC_AHBRSTR_ETHMAC_Pos)        ///< ETHMAC clock reset
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_SYSCFG Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define RCC_SYSCFG_PROGCHECKEN_Pos       (0)
+#define RCC_SYSCFG_PROGCHECKEN           (0x01U << RCC_SYSCFG_PROGCHECKEN_Pos)  ///< Whether to check the number in Flash when writing to Flash
+#define RCC_SYSCFG_SECTOR1KCFG_Pos       (1)
+#define RCC_SYSCFG_SECTOR1KCFG           (0x01U << RCC_SYSCFG_SECTOR1KCFG_Pos)  ///< The size of the Flash page when erased.
+#define RCC_SYSCFG_DATAPREFETCH_Pos      (2)
+#define RCC_SYSCFG_DATAPREFETCH          (0x01U << RCC_SYSCFG_DATAPREFETCH_Pos) ///< DATA prefetch module enable bit
+#define RCC_SYSCFG_PAD_OSC_TRIM_Pos      (8)
+#define RCC_SYSCFG_PAD_OSC_TRIM          (0x1FU << RCC_SYSCFG_PAD_OSC_TRIM_Pos) ///< Calibration value of external crystal vibration
+#define RCC_SYSCFG_OSC_LPFEN_Pos         (14)
+#define RCC_SYSCFG_OSC_LPFEN             (0x01U << RCC_SYSCFG_OSC_LPFEN_Pos)    ///< External crystal oscillator low pass filtering enables  
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_CFGR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_CFGR2_TIMADVCKSEL_Pos         (1)
+#define RCC_CFGR2_TIMADVCKSEL             (0x01U << RCC_CFGR2_TIMADVCKSEL_Pos)    ///< TIMADV_CKSEL
+#define RCC_CFGR2_TIMADV_PRE_Pos          (1)    ///< 
+#define RCC_CFGR2_TIMADV_PRE              (0x07U << RCC_CFGR2_TIMADV_PRE_Pos)     ///< SYSCLK's advance points are controlled by the software Frequency coefficient
+#define RCC_CFGR2_FSMC_PRE_Pos            (8)
+#define RCC_CFGR2_FSMC_PRE                (0x1FU << RCC_CFGR2_FSMC_PRE_Pos)       ///< FSMC Output clock frequency division factor
+#define RCC_CFGR2_APB1_CLK_HV_PRE_Pos     (16)
+#define RCC_CFGR2_APB1_CLK_HV_PRE         (0x0FU << RCC_CFGR2_APB1_CLK_HV_PRE_Pos) ///< APB1 Output clock frequency division factor
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_ICSCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_ICSCR_TIME_CRS_SEL_Pos         (0)
+#define RCC_ICSCR_TIME_CRS_SEL             (0x01U << RCC_ICSCR_TIME_CRS_SEL_Pos) ///< Whether to use the CRS module as source
+#define RCC_ICSCR_HSI_CAL_SEL_Pos          (11)    ///< 
+#define RCC_ICSCR_HSI_CAL_SEL              (0x1FU << RCC_ICSCR_HSI_CAL_SEL_Pos)  ///< Select the internal high speed clock calibration value
+#define RCC_ICSCR_HSI_CAL_SFT_Pos          (16)
+#define RCC_ICSCR_HSI_CAL_SFT              (0x3FU << RCC_ICSCR_HSI_CAL_SFT_Pos)  ///< Internal high-speed clock calibration
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_PLLCFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_PLLCFGR_PLLSRC_Pos             (0)
+#define RCC_PLLCFGR_PLLSRC                 (0x01U << RCC_PLLCFGR_PLLSRC_Pos)     ///< PLL entry clock source
+#define RCC_PLLCFGR_PLLXTPRE_Pos           (1)    ///< 
+#define RCC_PLLCFGR_PLLXTPRE               (0x01U << RCC_PLLCFGR_PLLXTPRE_Pos)   ///< HSE divider for PLL entry
+#define RCC_PLLCFGR_PLL_ICTRL_Pos          (2)
+#define RCC_PLLCFGR_PLL_ICTRL              (0x03U << RCC_PLLCFGR_PLL_ICTRL_Pos)  ///< PLL CP current control signals
+#define RCC_PLLCFGR_PLL_LDS_Pos            (4)
+#define RCC_PLLCFGR_PLL_LDS                (0x03U << RCC_PLLCFGR_PLL_LDS_Pos)    ///< PLL lock detector accuracy select
+#define RCC_PLLCFGR_PLL_DP_Pos             (8)    ///< 
+#define RCC_PLLCFGR_PLL_DP                 (0x07U << RCC_PLLCFGR_PLL_DP_Pos)     ///< PLL divider factor DP
+#define RCC_PLLCFGR_PLL_DN_Pos             (16)
+#define RCC_PLLCFGR_PLL_DN                 (0x7FU << RCC_PLLCFGR_PLL_DN_Pos)     ///< PLL divider factor DN
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_HSIDLY Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_HSIDLY_HSI_EQU_CNT             (0xFFU)                               ///< HSI delay time
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_HSEDLY Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_HSEDLY_HSI_EQU_CNT             (0xFFFFU)                               ///< HSE delay time
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RCC_PLLDLY Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RCC_PLLDLY_HSI_EQU_CNT             (0xFFU)                               ///< PLL delay time
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h
new file mode 100644
index 000000000..7f8acab01
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h
@@ -0,0 +1,203 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_rtc.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_RTC_H
+#define __REG_RTC_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_BASE                    (APB1PERIPH_BASE + 0x2800)              ///< Base Address: 0x40002800
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC Registers Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    union {
+        __IO u32 CR;                                                                ///< Control Register,                      offset: 0x00
+        __IO u32 CRH;
+    };
+    union {
+        __IO u32 CSR;                                                               ///< Control & Status Register,             offset: 0x04
+        __IO u32 CRL;
+    };
+    __IO u32 PRLH;                                                              ///< Prescaler Reload Value High,           offset: 0x08
+    __IO u32 PRLL;                                                              ///< Prescaler Reload Value Low,            offset: 0x0C
+    __IO u32 DIVH;                                                              ///< Clock Divider High,                    offset: 0x10
+    __IO u32 DIVL;                                                              ///< Clock Divider Low,                     offset: 0x14
+    __IO u32 CNTH;                                                              ///< Counter High,                          offset: 0x18
+    __IO u32 CNTL;                                                              ///< Counter Low,                           offset: 0x1C
+    __IO u32 ALRH;                                                              ///< Alarm High,                            offset: 0x20
+    __IO u32 ALRL;                                                              ///< Alarm Low,                             offset: 0x24
+    __IO u32 MSRH;                                                              ///< Millisecond alarm high register        offset: 0x28
+    __IO u32 MSRL;                                                              ///< Millisecond alarm low register         offset: 0x2C
+    __IO u32 RESERVED0;                                                         ///< Reserved                               offset: 0x30
+    __IO u32 RESERVED1;                                                         ///< Reserved                               offset: 0x34
+    __IO u32 RESERVED2;                                                         ///< Reserved                               offset: 0x38
+    __IO u32 LSE_CFG;                                                           ///< LSE configure register                 offset: 0x3C
+} RTC_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC                         ((RTC_TypeDef*)RTC_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CR_SECIE_Pos            (0)
+#define RTC_CR_SECIE                (0x01U << RTC_CR_SECIE_Pos)             ///< Second Interrupt Enable
+#define RTC_CR_ALRIE_Pos            (1)
+#define RTC_CR_ALRIE                (0x01U << RTC_CR_ALRIE_Pos)             ///< Alarm Interrupt Enable
+#define RTC_CR_OWIE_Pos             (2)
+#define RTC_CR_OWIE                 (0x01U << RTC_CR_OWIE_Pos)              ///< OverfloW Interrupt Enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CSR_SECF_Pos            (0)
+#define RTC_CSR_SECF                (0x01 << RTC_CSR_SECF_Pos)              ///< Second Flag
+#define RTC_CSR_ALRF_Pos            (1)
+#define RTC_CSR_ALRF                (0x01 << RTC_CSR_ALRF_Pos)              ///< Alarm Flag
+#define RTC_CSR_OWF_Pos             (2)
+#define RTC_CSR_OWF                 (0x01 << RTC_CSR_OWF_Pos)               ///< OverfloW Flag
+#define RTC_CSR_RSF_Pos             (3)
+#define RTC_CSR_RSF                 (0x01 << RTC_CSR_RSF_Pos)               ///< Registers Synchronized Flag
+#define RTC_CSR_CNF_Pos             (4)
+#define RTC_CSR_CNF                 (0x01 << RTC_CSR_CNF_Pos)               ///< Configuration Flag
+#define RTC_CSR_RTOFF_Pos           (5)
+#define RTC_CSR_RTOFF               (0x01 << RTC_CSR_RTOFF_Pos)             ///< RTC operation OFF
+#define RTC_CSR_ALPEN_Pos           (6)
+#define RTC_CSR_ALPEN               (0x01 << RTC_CSR_ALPEN_Pos)             ///< RTC Alarm Loop Enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_PRLH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_PRLH_PRL_Pos            (0)
+#define RTC_PRLH_PRL                (0x0F << RTC_PRLH_PRL_Pos)              ///< RTC Prescaler Reload Value High
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_PRLL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_PRLL_PRL_Pos            (0)
+#define RTC_PRLL_PRL                (0xFFFFU << RTC_PRLL_PRL_Pos)           ///< RTC Prescaler Reload Value Low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_DIVH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_DIVH_DIV_Pos            (0)
+#define RTC_DIVH_DIV                (0x0F << RTC_DIVH_DIV_Pos)              ///< RTC Clock Divider High
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_DIVL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_DIVL_DIV_Pos            (0)
+#define RTC_DIVL_DIV                (0xFFFFU << RTC_DIVL_DIV_Pos)           ///< RTC Clock Divider Low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CNTH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CNTH_CNT_Pos            (0)
+#define RTC_CNTH_CNT                (0xFFFFU << RTC_CNTH_CNT_Pos)           ///< RTC Counter High
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_CNTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_CNTL_CNT_Pos            (0)
+#define RTC_CNTL_CNT                (0xFFFFU << RTC_CNTL_CNT_Pos)           ///< RTC Counter Low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_ALRH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_ALRH_ALR_Pos            (0)
+#define RTC_ALRH_ALR                (0xFFFFU << RTC_ALRH_ALR_Pos)           ///< RTC Alarm High
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_ALRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_ALRL_ALR_Pos            (0)
+#define RTC_ALRL_ALR                (0xFFFFU << RTC_ALRL_ALR_Pos)           ///< RTC Alarm Low
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_MSRH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_MSRH_MSR_Pos            (0)
+#define RTC_MSRH_MSR                (0xFFFFU << RTC_MSRH_MSR_Pos)          ///< RTC MS Alarm Register High
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_MSRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define RTC_MSRL_MSR_Pos            (0)
+#define RTC_MSRL_MSR                (0xFFFFU << RTC_MSRL_MSR_Pos)           ///< RTC MS Alarm Register Low
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief RTC_LSE_CFG Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define RTC_LSE_CFG_TEST_Pos        (0)
+#define RTC_LSE_CFG_TEST            (0x0FU << RTC_LSE_CFG_TEST_Pos)              ///< Test control signal
+#define RTC_LSE_CFG_DR_Pos          (4)
+#define RTC_LSE_CFG_DR              (0x03U << RTC_LSE_CFG_DR_Pos)                ///< Drive capability selection
+#define RTC_LSE_CFG_RFB_SEL_Pos     (6)
+#define RTC_LSE_CFG_RFB_SEL_3       (0x03U << RTC_LSE_CFG_RFB_SEL_Pos)           ///< Feedback resistance selection 3M  
+#define RTC_LSE_CFG_RFB_SEL_6       (0x02U << RTC_LSE_CFG_RFB_SEL_Pos)           ///< Feedback resistance selection 6M 
+#define RTC_LSE_CFG_RFB_SEL_10      (0x01U << RTC_LSE_CFG_RFB_SEL_Pos)           ///< Feedback resistance selection 10M
+#define RTC_LSE_CFG_RFB_SEL_12      (0x00U << RTC_LSE_CFG_RFB_SEL_Pos)           ///< Feedback resistance selection 12M
+#define RTC_LSE_CFG_IB_Pos          (8)
+#define RTC_LSE_CFG_IB              (0x01U << RTC_MSRL_MSR_Pos)                  ///< Bias current regulation
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h
new file mode 100644
index 000000000..9c5d0cb60
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h
@@ -0,0 +1,391 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_sdio.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_SDIO_H
+#define __REG_SDIO_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+//#include "types.h"
+#include "mm32_reg.h"
+
+//#if defined ( __CC_ARM )
+//#pragma anon_unions
+//#endif
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_BASE                        (0x40018000U)                            ///< Base Address: 0x40018000
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+    __IO u32 MMC_CTRL;                                                          ///< SDIO transmit data register,                    offset: 0x00
+    __IO u32 MMC_IO;                                                            ///< SDIO receive data register,                     offset: 0x04
+    __IO u32 MMC_BYTECNTL;                                                      ///< SDIO current state register,                    offset: 0x08
+    __IO u32 MMC_TR_BLOCKCNT;                                                   ///< SDIO interruput state register,                 offset: 0x0C
+    __IO u32 MMC_CRCCTL;                                                        ///< SDIO interruput enable register,                offset: 0x10
+    __IO u32 CMD_CRC;                                                           ///< SDIO interruput control register,               offset: 0x14
+    __IO u32 DAT_CRCL;                                                          ///< SDIO global control register,                   offset: 0x18
+    __IO u32 DAT_CRCH;                                                          ///< SDIO common control register,                   offset: 0x1C
+    __IO u32 MMC_PORT;                                                          ///< SDIO baud rate control register,                offset: 0x20
+    __IO u32 MMC_INT_MASK;                                                      ///< SDIO receive data number register,              offset: 0x24
+    __IO u32 CLR_MMC_INT;                                                       ///< SDIO chip select register,                      offset: 0x28
+    __IO u32 MMC_CARDSEL;                                                       ///< SDIO extand control register,                   offset: 0x2C
+    __IO u32 MMC_SIG;                                                           ///<                                                 0ffset: 0x30
+    __IO u32 MMC_IO_MBCTL;                                                      ///<                                                 0ffset: 0x34
+    __IO u32 MMC_BLOCKCNT;                                                      ///<                                                 0ffset: 0x38
+    __IO u32 MMC_TIMEOUTCNT;                                                    ///<                                                 0ffset: 0x3C
+    __IO u32 CMD_BUF0;                                                          ///<                                                 0ffset: 0x40
+    __IO u32 CMD_BUF1;                                                          ///<                                                 0ffset: 0x44
+    __IO u32 CMD_BUF2;                                                          ///<                                                 0ffset: 0x48
+    __IO u32 CMD_BUF3;                                                          ///<                                                 0ffset: 0x4C
+    __IO u32 CMD_BUF4;                                                          ///<                                                 0ffset: 0x50
+    __IO u32 CMD_BUF5;                                                          ///<                                                 0ffset: 0x54
+    __IO u32 CMD_BUF6;                                                          ///<                                                 0ffset: 0x58
+    __IO u32 CMD_BUF7;                                                          ///<                                                 0ffset: 0x5C
+    __IO u32 CMD_BUF8;                                                          ///<                                                 0ffset: 0x60
+    __IO u32 CMD_BUF9;                                                          ///<                                                 0ffset: 0x64
+    __IO u32 CMD_BUF10;                                                         ///<                                                 0ffset: 0x68
+    __IO u32 CMD_BUF11;                                                         ///<                                                 0ffset: 0x6C
+    __IO u32 CMD_BUF12;                                                         ///<                                                 0ffset: 0x70
+    __IO u32 CMD_BUF13;                                                         ///<                                                 0ffset: 0x74
+    __IO u32 CMD_BUF14;                                                         ///<                                                 0ffset: 0x78
+    __IO u32 CMD_BUF15;                                                         ///<                                                 0ffset: 0x7C
+    __IO u32 BUF_CTL;                                                           ///<                                                 0ffset: 0x80
+
+    __IO u32 RESERVED[31];                                                      ///<                                                 0ffset: 0x84
+    union {
+        __IO u32 DATA_BUF0;                                                         ///<                                                 0ffset: 0x100
+        __IO u32 FIFO;
+    };
+    __IO u32 DATA_BUF1;                                                         ///<                                                 0ffset: 0x104
+    __IO u32 DATA_BUF2;                                                         ///<                                                 0ffset: 0x108
+    __IO u32 DATA_BUF3;                                                         ///<                                                 0ffset: 0x10C
+    __IO u32 DATA_BUF4;                                                         ///<                                                 0ffset: 0x110
+} SDIO_TypeDef;
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO                            ((SDIO_TypeDef*) SDIO_BASE)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_CTRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_CTRL_OPMSel_Pos               (0)
+#define SDIO_MMC_CTRL_OPMSel                   (0x01U << SDIO_MMC_CTRL_OPMSel_Pos)      ///< SD/MMC/SDIO port operation mode select
+#define SDIO_MMC_CTRL_SelSM_Pos                (1)
+#define SDIO_MMC_CTRL_SelSM                    (0x01U << SDIO_MMC_CTRL_SelSM_Pos)      ///< Select automatic mode
+#define SDIO_MMC_CTRL_OUTM_Pos                 (2)
+#define SDIO_MMC_CTRL_OUTM                     (0x01U << SDIO_MMC_CTRL_OUTM_Pos)      ///< SD/MMC/SDIO port CMD line output driver mode selection Open drain
+#define SDIO_MMC_CTRL_CLKSP_Pos                (3)
+#define SDIO_MMC_CTRL_CLKSP2                   (0x00U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/2  baseclock
+#define SDIO_MMC_CTRL_CLKSP4                   (0x01U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/4  baseclock
+#define SDIO_MMC_CTRL_CLKSP6                   (0x02U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/6  baseclock
+#define SDIO_MMC_CTRL_CLKSP8                   (0x03U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/8  baseclock
+#define SDIO_MMC_CTRL_CLKSP10                  (0x04U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/10 baseclock
+#define SDIO_MMC_CTRL_CLKSP12                  (0x05U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/12 baseclock
+#define SDIO_MMC_CTRL_CLKSP14                  (0x06U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/14 baseclock
+#define SDIO_MMC_CTRL_CLKSP16                  (0x07U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/16 baseclock
+#define SDIO_MMC_CTRL_SelPTSM_Pos              (6)
+#define SDIO_MMC_CTRL_SelPTSM                  (0x01U << SDIO_MMC_CTRL_SelPTSM_Pos)    ///< SelectSD/MMC/SDIO port transfer high speed mode
+#define SDIO_MMC_CTRL_DATWT_Pos                (7)
+#define SDIO_MMC_CTRL_DATWT                    (0x01U << SDIO_MMC_CTRL_DATWT_Pos)      ///< Definethe bus width of SD/MMC/SDIO port DAT line
+#define SDIO_MMC_CTRL_MDEN_Pos                 (8)
+#define SDIO_MMC_CTRL_MDEN                     (0x01U << SDIO_MMC_CTRL_MDEN_Pos)       ///< SDIO mode enable
+#define SDIO_MMC_CTRL_INTEN_Pos                (9)
+#define SDIO_MMC_CTRL_INTEN                    (0x01U << SDIO_MMC_CTRL_INTEN_Pos)      ///< SDIO interrupt enale signal
+#define SDIO_MMC_CTRL_RDWTEN_Pos               (10)
+#define SDIO_MMC_CTRL_RDWTEN                   (0x01U << SDIO_MMC_CTRL_RDWTEN_Pos)     ///< SDIO read wait enable signal
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_IO Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_IO_AUTODATTR_Pos               (0)
+#define SDIO_MMC_IO_AUTODATTR                   (0x01U << SDIO_MMC_IO_AUTODATTR_Pos)      ///< Set up automatic data transfer
+#define SDIO_MMC_IO_TRANSFDIR_Pos               (1)
+#define SDIO_MMC_IO_TRANSFDIR                   (0x01U << SDIO_MMC_IO_TRANSFDIR_Pos)      ///< Set the direction of data transfer
+#define SDIO_MMC_IO_AUTOTR_Pos                  (2)
+#define SDIO_MMC_IO_AUTOTR                      (0x01U << SDIO_MMC_IO_AUTOTR_Pos)        ///< Set up automatic 8-bit/command/response transmission.
+#define SDIO_MMC_IO_RESPCMDSEL_Pos              (3)
+#define SDIO_MMC_IO_RESPCMDSEL                  (0x01U << SDIO_MMC_IO_RESPCMDSEL_Pos)    ///< Receive response
+#define SDIO_MMC_IO_CID_CSDRD_Pos               (4)
+#define SDIO_MMC_IO_CID_CSDRD                   (0x01U << SDIO_MMC_IO_CID_CSDRD_Pos)     ///< CID and CSD reads
+#define SDIO_MMC_IO_PCLKG_Pos                   (5)
+#define SDIO_MMC_IO_PCLKG                       (0x01U << SDIO_MMC_IO_PCLKG_Pos)         ///< SD/MMC/SDIO port CLK line 8 empty clock generated
+#define SDIO_MMC_IO_ENRRESP_Pos                 (6)
+#define SDIO_MMC_IO_ENRRESP                     (0x01U << SDIO_MMC_IO_ENRRESP_Pos)       ///< Enable automatic receiving of responses after a command
+#define SDIO_MMC_IO_AUTOCLKG_Pos                (7)
+#define SDIO_MMC_IO_AUTOCLKG                    (0x01U << SDIO_MMC_IO_AUTOCLKG_Pos)      ///< Enable automatic conversion of the 8 empty clock after a response/command or a single block of data
+#define SDIO_MMC_IO_CMDCH_Pos                   (8)
+#define SDIO_MMC_IO_CMDCH                       (0x01U << SDIO_MMC_IO_CMDCH_Pos)         ///< SDIO mode enable
+#define SDIO_MMC_IO_CMDAF_Pos                   (9)
+#define SDIO_MMC_IO_CMDAF                       (0x01U << SDIO_MMC_IO_CMDAF_Pos)        ///< SDIO CMD12 / IO abort flag
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_BYTECNTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_BYTECNTL_CNT                    (0xFFFFU)                              ///< Data transfer byte count register
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_TR_BLOCKCNT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_TR_BLOCKCNT_CNT                 (0xFFFFU)                              ///< The value of the counter that completes the transfer when multiple blocks are transferred.
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_CRCCTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_CRCCTL_DAT_CRCE_Pos             (0)
+#define SDIO_MMC_CRCCTL_DAT_CRCE                 (0x01U << SDIO_MMC_CRCCTL_DAT_CRCE_Pos)      ///< DAT CRC error
+#define SDIO_MMC_CRCCTL_CMD_CRCE_Pos             (1)
+#define SDIO_MMC_CRCCTL_CMD_CRCE                 (0x01U << SDIO_MMC_CRCCTL_CMD_CRCE_Pos)      ///< CMD CRC error
+#define SDIO_MMC_CRCCTL_DAT_CRCS_Pos             (2)
+#define SDIO_MMC_CRCCTL_DAT_CRCS                 (0x03U << SDIO_MMC_CRCCTL_DAT_CRCS_Pos)      ///< DAT CRC selection
+#define SDIO_MMC_CRCCTL_ENRDMB_Pos               (4)
+#define SDIO_MMC_CRCCTL_ENRDMB                   (0x01U << SDIO_MMC_CRCCTL_ENRDMB_Pos)        ///< Enable reading multiple blocks of data before responding
+#define SDIO_MMC_CRCCTL_ENCHK_Pos                (5)
+#define SDIO_MMC_CRCCTL_ENCHK                    (0x01U << SDIO_MMC_CRCCTL_ENCHK_Pos)         ///< Enable automatic checking 
+#define SDIO_MMC_CRCCTL_DAT_CRCEN_Pos            (6)
+#define SDIO_MMC_CRCCTL_DAT_CRCEN                (0x01U << SDIO_MMC_CRCCTL_DAT_CRCEN_Pos)     ///< SD/MMC/SDIO PORT DAT line CRC circuit enablement
+#define SDIO_MMC_CRCCTL_CMD_CRCEN_Pos            (7)
+#define SDIO_MMC_CRCCTL_CMD_CRCEN                (0x01U << SDIO_MMC_CRCCTL_CMD_CRCEN_Pos)     ///< SD/MMC/SDIO port CMD line CRC circuit enablement
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_CRC Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_CRC_CMD_CRCV                    (0x7FU)                                 ///< CMD_CRCV register value
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_DAT_CRCL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_DAT_CRCL_DAT_CRCLV                  (0xFFU)                                 ///< CMD_CRCV low  register value
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_DAT_CRCH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_DAT_CRCL_DAT_CRCHV                  (0xFFU)                                 ///< CMD_CRCV high register value
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_PORT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_PORT_NTCR_Pos                   (0)
+#define SDIO_MMC_PORT_NTCR                       (0x0FU << SDIO_MMC_PORT_NTCR_Pos)      ///< Ncr timeout count register
+#define SDIO_MMC_PORT_AUTONTEN_Pos               (4)
+#define SDIO_MMC_PORT_AUTONTEN                   (0x01U << SDIO_MMC_PORT_AUTONTEN_Pos)  ///< Automatic Ncr timer output enablement
+#define SDIO_MMC_PORT_PDATS_Pos                  (5)
+#define SDIO_MMC_PORT_PDATS                      (0x01U << SDIO_MMC_PORT_PDATS_Pos)     ///< SD/MMC/SDIO port DAT line signal
+#define SDIO_MMC_PORT_PCMDS_Pos                  (6)
+#define SDIO_MMC_PORT_PCMDS                      (0x01U << SDIO_MMC_PORT_PCMDS_Pos)     ///< SD/MMC/SDIO port CMD line signal
+#define SDIO_MMC_PORT_PCLKS_Pos                  (7)
+#define SDIO_MMC_PORT_PCLKS                      (0x01U << SDIO_MMC_PORT_PCLKS_Pos)     ///< SD/MMC/SDIO port CLK line signal
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_INT_MASK Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_INT_MASK_CMDDINT_Pos             (0)
+#define SDIO_MMC_INT_MASK_CMDDINT                 (0x01U << SDIO_MMC_INT_MASK_CMDDINT_Pos)      ///<CMD completes interrupt shielding
+#define SDIO_MMC_INT_MASK_DATDINT_Pos             (1)
+#define SDIO_MMC_INT_MASK_DATDINT                 (0x01U << SDIO_MMC_INT_MASK_DATDINT_Pos)      ///< DAT completes interrupt shielding
+#define SDIO_MMC_INT_MASK_DATEINT_Pos             (2)
+#define SDIO_MMC_INT_MASK_DATEINT                 (0x01U << SDIO_MMC_INT_MASK_DATEINT_Pos)      ///< DAT CRC error interrupt masking
+#define SDIO_MMC_INT_MASK_CMDEINT_Pos             (3)
+#define SDIO_MMC_INT_MASK_CMDEINT                 (0x01U << SDIO_MMC_INT_MASK_CMDEINT_Pos)     ///< CMD CRC error interrupt masking
+#define SDIO_MMC_INT_MASK_MBDINTM_Pos             (4)
+#define SDIO_MMC_INT_MASK_MBDINTM                 (0x01U << SDIO_MMC_INT_MASK_MBDINTM_Pos)     ///< Multiple blocks complete interrupt shielding 
+#define SDIO_MMC_INT_MASK_MBTINTM_Pos             (5)
+#define SDIO_MMC_INT_MASK_MBTINTM                 (0x01U << SDIO_MMC_INT_MASK_MBTINTM_Pos)     ///< Multiblock timeout interrupt shielding
+#define SDIO_MMC_INT_MASK_CRTINTM_Pos             (6)
+#define SDIO_MMC_INT_MASK_CRTINTM                 (0x01U << SDIO_MMC_INT_MASK_CRTINTM_Pos)     ///< Cmd and Resp Ncr timeout interrupt shielding
+#define SDIO_MMC_INT_MASK_CRCINTM_Pos             (7)
+#define SDIO_MMC_INT_MASK_CRCINTM                 (0x01U << SDIO_MMC_INT_MASK_CRCINTM_Pos)     ///< CRC status token error interrupt masking
+#define SDIO_MMC_INT_MASK_D1INTM_Pos              (8)
+#define SDIO_MMC_INT_MASK_D1INTM                  (0x01U << SDIO_MMC_INT_MASK_D1INTM_Pos)     ///< SDIO Data 1 Line Interrupt Mask
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CLR_MMC_INT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CLR_MMC_INT_CMDDMC_Pos             (0)
+#define SDIO_CLR_MMC_INT_CMDDMC                 (0x01U << SDIO_CLR_MMC_INT_CMDDMC_Pos)      ///< CMD completes interrupt mask bit
+#define SDIO_CLR_MMC_INT_DATDMC_Pos             (1)
+#define SDIO_CLR_MMC_INT_DATDMC                 (0x01U << SDIO_CLR_MMC_INT_DATDMC_Pos)      ///< DAT completes interrupt mask bit
+#define SDIO_CLR_MMC_INT_DATEMC_Pos             (2)
+#define SDIO_CLR_MMC_INT_DATEMC                 (0x01U << SDIO_CLR_MMC_INT_DATEMC_Pos)      ///< DAT CRC error interrupt mask bit
+#define SDIO_CLR_MMC_INT_CMDEMC_Pos             (3)
+#define SDIO_CLR_MMC_INT_CMDEMC                 (0x01U << SDIO_CLR_MMC_INT_CMDEMC_Pos)     ///< CMD CRC error interrupt mask bit
+#define SDIO_CLR_MMC_INT_MBDMC_Pos              (4)
+#define SDIO_CLR_MMC_INT_MBDMC                  (0x01U << SDIO_CLR_MMC_INT_MBDMC_Pos)      ///< Multi - block transmission completion interrupt mask bit 
+#define SDIO_CLR_MMC_INT_MBTMC_Pos              (5)
+#define SDIO_CLR_MMC_INT_MBTMC                  (0x01U << SDIO_CLR_MMC_INT_MBTMC_Pos)      ///< Multiblock transmission timeout interrupt mask bit
+#define SDIO_CLR_MMC_INT_CRNTMC_Pos             (6)
+#define SDIO_CLR_MMC_INT_CRNTMC                 (0x01U << SDIO_CLR_MMC_INT_CRNTMC_Pos)     ///< Command and response Ncr timeout interrupt mask bit
+#define SDIO_CLR_MMC_INT_CRCEMC_Pos             (7)
+#define SDIO_CLR_MMC_INT_CRCEMC                 (0x01U << SDIO_CLR_MMC_INT_CRCEMC_Pos)     ///< CRC status error marks the interrupt mask bit
+#define SDIO_CLR_MMC_INT_D1MC_Pos               (8)
+#define SDIO_CLR_MMC_INT_D1MC                   (0x01U << SDIO_CLR_MMC_INT_D1MC_Pos)       ///< SDIO DatA1 line interrupt flag/clear bit
+#define SDIO_CLR_MMC_INT_MASK                   (0XFFU)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_CARDSEL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_CARDSEL_TSCALE_Pos             (0)
+#define SDIO_MMC_CARDSEL_TSCALE                 (0x01U << SDIO_MMC_CARDSEL_TSCALE_Pos)      ///< SD/MMC/SDIO clock frequency division factor (based on 1MHz
+#define SDIO_MMC_CARDSEL_ENPCLK_Pos             (6)
+#define SDIO_MMC_CARDSEL_ENPCLK                 (0x01U << SDIO_MMC_CARDSEL_ENPCLK_Pos)      ///< Enabling card's SD/MMC/SDIO port CLK clock
+#define SDIO_MMC_CARDSEL_CTREN_Pos              (7)
+#define SDIO_MMC_CARDSEL_CTREN                  (0x01U << SDIO_MMC_CARDSEL_CTREN_Pos)      ///< SD/MMC/SDIO controller enablement bit
+#define SDIO_MMC_CARDSEL_MASK                   (0XFFU)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_SIQ Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_SIQ_PDAT0S_Pos                 (0)
+#define SDIO_MMC_SIQ_PDAT0S                     (0x01U << SDIO_MMC_SIQ_PDAT0S_Pos)         ///< SD/MMC/SDIO port DAT0 line signal
+#define SDIO_MMC_SIQ_PDAT1S_Pos                 (1)
+#define SDIO_MMC_SIQ_PDAT1S                     (0x01U << SDIO_MMC_SIQ_PDAT1S_Pos)         ///< SD/MMC/SDIO port DAT1 line signal
+#define SDIO_MMC_SIQ_PDAT2S_Pos                 (2)
+#define SDIO_MMC_SIQ_PDAT2S                     (0x01U << SDIO_MMC_SIQ_PDAT2S_Pos)         ///< SD/MMC/SDIO port DAT2 line signal
+#define SDIO_MMC_SIQ_PDAT3S_Pos                 (3)
+#define SDIO_MMC_SIQ_PDAT3S                     (0x01U << SDIO_MMC_SIQ_PDAT3S_Pos)         ///< SD/MMC/SDIO port DAT3 line signal
+#define SDIO_MMC_SIQ_CRC_status_Pos             (4)
+#define SDIO_MMC_SIQ_CRC_status                 (0x07U << SDIO_MMC_SIQ_CRC_status_Pos)     ///< CRC state
+#define SDIO_MMC_SIQ_PCMDS_Pos                  (7)
+#define SDIO_MMC_SIQ_PCMDS                      (0x01U << SDIO_MMC_SIQ_PCMDS_Pos)          ///< SD/MMC/SDIO port CMD line signal
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_IO_MBCTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_IO_MBCTL_SPMBDTR_Pos           (0)
+#define SDIO_MMC_IO_MBCTL_SPMBDTR               (0x01U << SDIO_MMC_IO_MBCTL_SPMBDTR_Pos)   ///< Set the SD/MMC/SDIO port to automatically multiblock data transfer bit
+#define SDIO_MMC_IO_MBCTL_SMBDTD_Pos            (1)
+#define SDIO_MMC_IO_MBCTL_SMBDTD                (0x01U << SDIO_MMC_IO_MBCTL_SMBDTD_Pos)    //< Multi - block data transfer direction selection bit
+#define SDIO_MMC_IO_MBCTL_PAUTOTR_Pos           (2)
+#define SDIO_MMC_IO_MBCTL_PAUTOTR               (0x01U << SDIO_MMC_IO_MBCTL_PAUTOTR_Pos)   ///< Set up SD/MMC/SDIO port automatic command and multi - block data transfer
+#define SDIO_MMC_IO_MBCTL_PCLKP_Pos             (3)
+#define SDIO_MMC_IO_MBCTL_PCLKP                 (0x01U << SDIO_MMC_IO_MBCTL_PCLKP_Pos)     ///< SD/MMC/SDIO port CLK line polarity selection bit
+#define SDIO_MMC_IO_MBCTL_BTSSel_Pos            (4)
+#define SDIO_MMC_IO_MBCTL_BTSSel                (0x03U << SDIO_MMC_SIQ_CRC_status_Pos)     ///< SD/MMC/SDIO BUSY Timeout level selects bits
+#define SDIO_MMC_IO_MBCTL_BTSSel_2              (0x02U << SDIO_MMC_SIQ_CRC_status_Pos)     ///< SD/MMC/SDIO BUSY Timeout level selects bits
+#define SDIO_MMC_IO_MBCTL_NTSSel_Pos            (6)
+#define SDIO_MMC_IO_MBCTL_NTSSel                (0x03U << SDIO_MMC_IO_MBCTL_NTSSel_Pos)    ///< SD/MMC/SDIO NAC timeout level selection bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_BLOCKCNT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_BLOCKCNT_EN                    (0xFFFFU)                                 ///< Block count register
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_MMC_TIMEOUTCNT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_MMC_TIMEOUTCNT_DTCNT                (0xFFU)                                 ///< Data transfer timeout count register
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF0 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF0_DAT                        (0xFFU)                                 ///< Cmd_buf0 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF1_DAT                        (0xFFU)                                 ///< Cmd_buf1 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF2_DAT                        (0xFFU)                                 ///< Cmd_buf2 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF3 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF3_DAT                        (0xFFU)                                 ///< Cmd_buf3 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF4 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF4_DAT                        (0xFFU)                                 ///< Cmd_buf4 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF5 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF5_DAT                        (0xFFU)                                 ///< Cmd_buf5 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF6 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF6_DAT                        (0xFFU)                                 ///< Cmd_buf6 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF7 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF7_DAT                        (0xFFU)                                 ///< Cmd_buf7 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF8 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF8_DAT                        (0xFFU)                                 ///< Cmd_buf8 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF9 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF9_DAT                        (0xFFU)                                 ///< Cmd_buf9 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF10 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF10_DAT                        (0xFFU)                                 ///< Cmd_buf10 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF11 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF11_DAT                        (0xFFU)                                 ///< Cmd_buf11 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF12 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF12_DAT                        (0xFFU)                                 ///< Cmd_buf12 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF13 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF13_DAT                        (0xFFU)                                 ///< Cmd_buf13 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF14 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF14_DAT                        (0xFFU)                                 ///< Cmd_buf14 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_CMD_BUF15 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_CMD_BUF15_DAT                        (0xFFU)                                 ///< Cmd_buf15 byte mapping bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_BUF_CTLL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_BUF_CTLL_DBF_Pos                     (0)
+#define SDIO_BUF_CTLL_DBF                         (0x01U << SDIO_BUF_CTLL_DBF_Pos)        ///< The data cache is full
+#define SDIO_BUF_CTLL_DBE_Pos                     (1)
+#define SDIO_BUF_CTLL_DBE                         (0x01U << SDIO_BUF_CTLL_DBE_Pos)        ///< Data buff is null
+#define SDIO_BUF_CTLL_DBML_Pos                    (2)
+#define SDIO_BUF_CTLL_DBML                        (0xFFU << SDIO_BUF_CTLL_DBML_Pos)       ////< Data buff tags
+#define SDIO_BUF_CTLL_DMAHEN_Pos                  (10)
+#define SDIO_BUF_CTLL_DMAHEN                      (0x01U << SDIO_BUF_CTLL_DMAHEN_Pos)     ///< DMA hardware interface enablement
+#define SDIO_BUF_CTLL_SBAD_Pos                    (11)
+#define SDIO_BUF_CTLL_SBAD                        (0x01U << SDIO_BUF_CTLL_SBAD_Pos)       ///< Sets the access direction of the buff
+#define SDIO_BUF_CTLL_DFIFOSM_Pos                 (12)
+#define SDIO_BUF_CTLL_DFIFOSM                     (0x01U << SDIO_BUF_CTLL_DFIFOSM_Pos)    ///< Data FIFO status signal shielding bit
+#define SDIO_BUF_CTLL_DRM_Pos                     (14)
+#define SDIO_BUF_CTLL_DRM                         (0x01U << SDIO_BUF_CTLL_DRM_Pos)        ///< DMA request masking
+#define SDIO_BUF_CTLL_DBFEN_Pos                   (15)
+#define SDIO_BUF_CTLL_DBFEN                       (0x01U << SDIO_BUF_CTLL_DBFEN_Pos)      ///< Data Buf empty enable bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SDIO_DATA_BUF Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SDIO_DATA_BUF_DB                         (0xFFFFFFFFU)                            ///< Data buffer
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h
new file mode 100644
index 000000000..c02b0fae0
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h
@@ -0,0 +1,359 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_spi.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_SPI_H
+#define __REG_SPI_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI2_BASE                       (APB1PERIPH_BASE + 0x3800)              ///< Base Address: 0x40003800
+#define SPI1_BASE                       (APB2PERIPH_BASE + 0x3000)              ///< Base Address: 0x400013000
+#define SPI3_BASE                       (APB1PERIPH_BASE + 0x3C00)             ///< Base Address: 0x40003C000
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+#undef USENCOMBINEREGISTER
+#undef USENNEWREGISTER
+#undef USENOLDREGISTER
+#define USENCOMBINEREGISTER
+#ifdef USENCOMBINEREGISTER
+typedef struct {
+    union {
+        __IO u32 TDR;                                                               ///< SPI transmit data register,                    offset: 0x00
+        __IO u32 TXREG;
+    };
+    union {
+        __IO u32 RDR;                                                               ///< SPI receive data register,                     offset: 0x04
+        __IO u32 RXREG;
+    };
+    union {
+        __IO u32 SR;                                                                ///< SPI current state register,                    offset: 0x08
+        __IO u32 CSTAT;
+    };
+    union {
+        __IO u32 ISR;                                                               ///< SPI interruput state register,                 offset: 0x0C
+        __IO u32 INTSTAT;
+    };
+    union {
+        __IO u32 IER;                                                               ///< SPI interruput enable register,                offset: 0x10
+        __IO u32 INTEN;
+    };
+    union {
+        __IO u32 ICR;                                                               ///< SPI interruput control register,               offset: 0x14
+        __IO u32 INTCLR;
+    };
+    union {
+        __IO u32 GCR;                                                               ///< SPI global control register,                   offset: 0x18
+        __IO u32 GCTL;
+    };
+    union {
+        __IO u32 CCR;                                                               ///< SPI common control register,                   offset: 0x1C
+        __IO u32 CCTL;
+    };
+    union {
+        __IO u32 BRR;                                                               ///< SPI baud rate control register,                offset: 0x20
+        __IO u32 SPBRG;
+    };
+    union {
+        __IO u32 RDNR;                                                              ///< SPI receive data number register,              offset: 0x24
+        __IO u32 RXDNR;
+    };
+    union {
+        __IO u32 NSSR;                                                              ///< SPI chip select register,                      offset: 0x28
+        __IO u32 SCSR;
+    };
+    union {
+        __IO u32 ECR;                                                               ///< SPI extand control register,                   offset: 0x2C
+        __IO u32 EXTCTL;
+    };
+    __IO u32 CFGR;                                                              ///< I2S configuration register,                   offset: 0x30
+} SPI_TypeDef;
+#endif
+#ifdef USENNEWREGISTER
+typedef struct {
+    __IO u32 TDR;                                                               ///< SPI transmit data register,                    offset: 0x00
+    __IO u32 RDR;                                                               ///< SPI receive data register,                     offset: 0x04
+    __IO u32 SR;                                                                ///< SPI current state register,                    offset: 0x08
+    __IO u32 ISR;                                                               ///< SPI interruput state register,                 offset: 0x0C
+    __IO u32 IER;                                                               ///< SPI interruput enable register,                offset: 0x10
+    __IO u32 ICR;                                                               ///< SPI interruput control register,               offset: 0x14
+    __IO u32 GCR;                                                               ///< SPI global control register,                   offset: 0x18
+    __IO u32 CCR;                                                               ///< SPI common control register,                   offset: 0x1C
+    __IO u32 BRR;                                                               ///< SPI baud rate control register,                offset: 0x20
+    __IO u32 RDNR;                                                              ///< SPI receive data number register,              offset: 0x24
+    __IO u32 NSSR;                                                              ///< SPI chip select register,                      offset: 0x28
+    __IO u32 ECR;                                                               ///< SPI extand control register,                   offset: 0x2C
+} SPI_TypeDef;
+#endif
+#ifdef USENOLDREGISTER
+typedef struct {
+    __IO u32 TXREG;                                                             ///< SPI transmit data register,                    offset: 0x00
+    __IO u32 RXREG;                                                             ///< SPI receive data register,                     offset: 0x04
+    __IO u32 CSTAT;                                                             ///< SPI current state register,                    offset: 0x08
+    __IO u32 INTSTAT;                                                           ///< SPI interruput state register,                 offset: 0x0C
+    __IO u32 INTEN;                                                             ///< SPI interruput enable register,                offset: 0x10
+    __IO u32 INTCLR;                                                            ///< SPI interruput control register,               offset: 0x14
+    __IO u32 GCTL;                                                              ///< SPI global control register,                   offset: 0x18
+    __IO u32 CCTL;                                                              ///< SPI common control register,                   offset: 0x1C
+    __IO u32 SPBRG;                                                             ///< SPI baud rate control register,                offset: 0x20
+    __IO u32 RXDNR;                                                             ///< SPI receive data number register,              offset: 0x24
+    __IO u32 NSSR;                                                              ///< SPI chip select register,                      offset: 0x28
+    __IO u32 EXTCTL;                                                            ///< SPI extand control register,                   offset: 0x2C
+} SPI_TypeDef;
+#endif
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI2                            ((SPI_TypeDef*) SPI2_BASE)
+#define SPI1                            ((SPI_TypeDef*) SPI1_BASE)
+#define SPI3                            ((SPI_TypeDef*) SPI3_BASE)
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_TDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_TDR_TXREG_Pos               (0)
+#define SPI_TDR_TXREG                   (0xFFFFFFFFU << SPI_TDR_TXREG_Pos)      ///< Transmit data register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_RDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_RDR_RXREG_Pos               (0)
+#define SPI_RDR_RXREG                   (0xFFFFFFFFU << SPI_RDR_RXREG_Pos)      ///< Receive data register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_SR_TXEPT_Pos                (0)
+#define SPI_SR_TXEPT                    (0x01U << SPI_SR_TXEPT_Pos)             ///< Transmitter empty bit
+#define SPI_SR_RXAVL_Pos                (1)
+#define SPI_SR_RXAVL                    (0x01U << SPI_SR_RXAVL_Pos)             ///< Receive available byte data message
+#define SPI_SR_TXFULL_Pos               (2)
+#define SPI_SR_TXFULL                   (0x01U << SPI_SR_TXFULL_Pos)            ///< Transmitter FIFO full status bit
+#define SPI_SR_RXAVL_4BYTE_Pos          (3)
+#define SPI_SR_RXAVL_4BYTE              (0x01U << SPI_SR_RXAVL_4BYTE_Pos)       ///< Receive available 4 byte data message
+#define SPI_SR_TXFADDR_Pos              (4)
+#define SPI_SR_TXFADDR                  (0x0FU << SPI_SR_TXFADDR_Pos)           ///< Transmit FIFO address
+#define SPI_SR_RXFADDR_Pos              (8)
+#define SPI_SR_RXFADDR                  (0x0FU << SPI_SR_RXFADDR_Pos)           ///< Receive FIFO address
+#define SPI_SR_BUSY_Pos                 (12)
+#define SPI_SR_BUSY                     (0x01U << SPI_SR_BUSY_Pos)              ///< Data transfer flag
+#define SPI_SR_CHSIDE_Pos               (13)
+#define SPI_SR_CHSIDE                   (0x01U << SPI_SR_CHSIDE_Pos)            ///< transmission channel     
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_ISR_TX_INTF_Pos             (0)
+#define SPI_ISR_TX_INTF                 (0x01U << SPI_ISR_TX_INTF_Pos)          ///<  Transmit FIFO available interrupt flag bit
+#define SPI_ISR_RX_INTF_Pos             (1)
+#define SPI_ISR_RX_INTF                 (0x01U << SPI_ISR_RX_INTF_Pos)          ///<  Receive data available interrupt flag bit
+#define SPI_ISR_UNDERRUN_INTF_Pos       (2)
+#define SPI_ISR_UNDERRUN_INTF           (0x01U << SPI_ISR_UNDERRUN_INTF_Pos)    ///<  SPI underrun interrupt flag bit
+#define SPI_ISR_RXOERR_INTF_Pos         (3)
+#define SPI_ISR_RXOERR_INTF             (0x01U << SPI_ISR_RXOERR_INTF_Pos)      ///<  Receive overrun error interrupt flag bit
+#define SPI_ISR_RXMATCH_INTF_Pos        (4)
+#define SPI_ISR_RXMATCH_INTF            (0x01U << SPI_ISR_RXMATCH_INTF_Pos)     ///<  Receive data match the RXDNR number, the receive process will be completed and generate the interrupt
+#define SPI_ISR_RXFULL_INTF_Pos         (5)
+#define SPI_ISR_RXFULL_INTF             (0x01U << SPI_ISR_RXFULL_INTF_Pos)      ///<  RX FIFO full interrupt flag bit
+#define SPI_ISR_TXEPT_INTF_Pos          (6)
+#define SPI_ISR_TXEPT_INTF              (0x01U << SPI_ISR_TXEPT_INTF_Pos)       ///<  Transmitter empty interrupt flag bit
+#define SPI_ISR_FRE_INTF_Pos            (7)
+#define SPI_ISR_FRE_INTF                (0x01U << SPI_ISR_FRE_INTF_Pos)         ///< I2S frame transmission error flag bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_IER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_IER_TX_IEN_Pos              (0)
+#define SPI_IER_TX_IEN                  (0x01U << SPI_IER_TX_IEN_Pos)           ///<  Transmit FIFO empty interrupt enable bit
+#define SPI_IER_RX_IEN_Pos              (1)
+#define SPI_IER_RX_IEN                  (0x01U << SPI_IER_RX_IEN_Pos)           ///<  Receive FIFO interrupt enable bit
+#define SPI_IER_UNDERRUN_IEN_Pos        (2)
+#define SPI_IER_UNDERRUN_IEN            (0x01U << SPI_IER_UNDERRUN_IEN_Pos)     ///<  Transmitter underrun interrupt enable bit
+#define SPI_IER_RXOERR_IEN_Pos          (3)
+#define SPI_IER_RXOERR_IEN              (0x01U << SPI_IER_RXOERR_IEN_Pos)       ///<  Overrun error interrupt enable bit
+#define SPI_IER_RXMATCH_IEN_Pos         (4)
+#define SPI_IER_RXMATCH_IEN             (0x01U << SPI_IER_RXMATCH_IEN_Pos)      ///<  Receive data complete interrupt enable bit
+#define SPI_IER_RXFULL_IEN_Pos          (5)
+#define SPI_IER_RXFULL_IEN              (0x01U << SPI_IER_RXFULL_IEN_Pos)       ///<  Receive FIFO full interrupt enable bit
+#define SPI_IER_TXEPT_IEN_Pos           (6)
+#define SPI_IER_TXEPT_IEN               (0x01U << SPI_IER_TXEPT_IEN_Pos)        ///<  Transmit empty interrupt enable bit
+#define SPI_IER_FRE_IEN_Pos            (7)
+#define SPI_IER_FRE_IEN                (0x01U << SPI_IER_FRE_IEN_Pos)           ///< I2S frame transmission interrupt enable bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_ICR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_ICR_TX_ICLR_Pos             (0)
+#define SPI_ICR_TX_ICLR                 (0x01U << SPI_ICR_TX_ICLR_Pos)          ///<  Transmitter FIFO empty interrupt clear bit
+#define SPI_ICR_RX_ICLR_Pos             (1)
+#define SPI_ICR_RX_ICLR                 (0x01U << SPI_ICR_RX_ICLR_Pos)          ///<  Receive interrupt clear bit
+#define SPI_ICR_UNDERRUN_ICLR_Pos       (2)
+#define SPI_ICR_UNDERRUN_ICLR           (0x01U << SPI_ICR_UNDERRUN_ICLR_Pos)    ///<  Transmitter underrun interrupt clear bit
+#define SPI_ICR_RXOERR_ICLR_Pos         (3)
+#define SPI_ICR_RXOERR_ICLR             (0x01U << SPI_ICR_RXOERR_ICLR_Pos)      ///<  Overrun error interrupt clear bit
+#define SPI_ICR_RXMATCH_ICLR_Pos        (4)
+#define SPI_ICR_RXMATCH_ICLR            (0x01U << SPI_ICR_RXMATCH_ICLR_Pos)     ///<  Receive completed interrupt clear bit
+#define SPI_ICR_RXFULL_ICLR_Pos         (5)
+#define SPI_ICR_RXFULL_ICLR             (0x01U << SPI_ICR_RXFULL_ICLR_Pos)      ///<  Receiver buffer full interrupt clear bit
+#define SPI_ICR_TXEPT_ICLR_Pos          (6)
+#define SPI_ICR_TXEPT_ICLR              (0x01U << SPI_ICR_TXEPT_ICLR_Pos)       ///<  Transmitter empty interrupt clear bit
+#define SPI_ICR_FRE_ICLR_Pos            (7)
+#define SPI_ICR_FRE_ICLR                (0x01U << SPI_ICR_FRE_ICLR_Pos)         ///< I2S frame transmission interrupt clear bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_GCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_GCR_SPIEN_Pos               (0)
+#define SPI_GCR_SPIEN                   (0x01U << SPI_GCR_SPIEN_Pos)            ///<  SPI select bit
+#define SPI_GCR_IEN_Pos                 (1)
+#define SPI_GCR_IEN                     (0x01U << SPI_GCR_IEN_Pos)              ///<  SPI interrupt enable bit
+#define SPI_GCR_MODE_Pos                (2)
+#define SPI_GCR_MODE                    (0x01U << SPI_GCR_MODE_Pos)             ///<  Master mode bit
+#define SPI_GCR_TXEN_Pos                (3)
+#define SPI_GCR_TXEN                    (0x01U << SPI_GCR_TXEN_Pos)             ///<  Transmit enable bit
+#define SPI_GCR_RXEN_Pos                (4)
+#define SPI_GCR_RXEN                    (0x01U << SPI_GCR_RXEN_Pos)             ///<  Receive enable bit
+
+#define SPI_GCR_RXTLF_Pos               (5)
+#define SPI_GCR_RXTLF                   (0x03U << SPI_GCR_RXTLF_Pos)            ///<  RX FIFO trigger level bit
+#define SPI_GCR_RXTLF_One               (0x00U << SPI_GCR_RXTLF_Pos)            ///<
+#define SPI_GCR_RXTLF_Half              (0x01U << SPI_GCR_RXTLF_Pos)            ///<
+
+#define SPI_GCR_TXTLF_Pos               (7)
+#define SPI_GCR_TXTLF                   (0x03U << SPI_GCR_TXTLF_Pos)            ///<  TX FIFO trigger level bit
+#define SPI_GCR_TXTLF_One               (0x00U << SPI_GCR_TXTLF_Pos)            ///<
+#define SPI_GCR_TXTLF_Half              (0x01U << SPI_GCR_TXTLF_Pos)            ///<
+#define SPI_GCR_DMAEN_Pos               (9)
+#define SPI_GCR_DMAEN                   (0x01U << SPI_GCR_DMAEN_Pos)            ///<  DMA access mode enable
+#define SPI_GCR_NSS_Pos                 (10)
+#define SPI_GCR_NSS                     (0x01U << SPI_GCR_NSS_Pos)              ///<  NSS select signal that from software or hardware
+#define SPI_GCR_DWSEL_Pos               (11)
+#define SPI_GCR_DWSEL                   (0x01U << SPI_GCR_DWSEL_Pos)            ///<  Valid byte or double-word data select signal
+
+#define SPI_GCR_NSSTOG_Pos              (12)
+#define SPI_GCR_NSSTOG                  (0x01U << SPI_GCR_NSSTOG_Pos)           ///<  Slave select toggle
+#define SPI_GCR_PAD_SEL_Pos             (13)
+#define SPI_GCR_PAD_SEL                 (0x1FU << SPI_GCR_PAD_SEL_Pos)          ///< Bus mapping transformation
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_CCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_CCR_CPHA_Pos                (0)
+#define SPI_CCR_CPHA                    (0x01U << SPI_CCR_CPHA_Pos)             ///<  Clock phase select bit
+#define SPI_CCR_CPOL_Pos                (1)
+#define SPI_CCR_CPOL                    (0x01U << SPI_CCR_CPOL_Pos)             ///<  Clock polarity select bit
+#define SPI_CCR_LSBFE_Pos               (2)
+#define SPI_CCR_LSBFE                   (0x01U << SPI_CCR_LSBFE_Pos)            ///<  LSI first enable bit
+#define SPI_CCR_SPILEN_Pos              (3)
+#define SPI_CCR_SPILEN                  (0x01U << SPI_CCR_SPILEN_Pos)           ///<  SPI character length bit
+#define SPI_CCR_RXEDGE_Pos              (4)
+#define SPI_CCR_RXEDGE                  (0x01U << SPI_CCR_RXEDGE_Pos)           ///<  Receive data edge select
+#define SPI_CCR_TXEDGE_Pos              (5)
+#define SPI_CCR_TXEDGE                  (0x01U << SPI_CCR_TXEDGE_Pos)           ///<  Transmit data edge select
+
+#define SPI_CCR_CPHASEL_Pos             (6)
+#define SPI_CCR_CPHASEL                 (0x01U << SPI_CCR_CPHASEL)              ///<  CPHA polarity select
+
+#define SPI_CCR_HISPD_Pos               (7)
+#define SPI_CCR_HISPD                   (0x01U << SPI_CCR_HISPD)                ///<  High speed slave mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_BRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_BRR_DIVF_Pos                (0)
+#define SPI_BRR_DIVF                    (0xFFFFU << SPI_BRR_DIVF_Pos)       ///<  SPI baud rate control register for baud rate
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_RDNR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_RDNR_RDN_Pos                (0)
+#define SPI_RDNR_RDN                    (0xFFFFU << SPI_RDNR_RDN_Pos)       ///<  The register is used to hold a count of to be received bytes in next receive process
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_NSSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_NSSR_NSS_Pos                (0)
+#define SPI_NSSR_NSS                    (0xFFU << SPI_NSSR_NSS_Pos)             ///<  Chip select output signal in Master mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SPI_ECR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define SPI_ECR_EXTLEN_Pos              (0)
+#define SPI_ECR_EXTLEN                  (0x1FU << SPI_ECR_EXTLEN_Pos)           ///<  control SPI data length
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief I2S_CFGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define I2SCFGR_CLEAR_Mask              ((u32)0xFE00F388)
+#define I2S_CFGR_CHLEN_Pos              (0)
+#define I2S_CFGR_CHLEN                  (0x01U << I2S_CFGR_CHLEN_Pos)             ///<  Vocal tract length
+#define I2S_CFGR_DATLEN_Pos             (1)
+#define I2S_CFGR_DATLEN_16              (0x00U << I2S_CFGR_DATLEN_Pos)            ///<  Audio data width 16 
+#define I2S_CFGR_DATLEN_24              (0x01U << I2S_CFGR_DATLEN_Pos)            ///<  Audio data width 24 
+#define I2S_CFGR_DATLEN_32              (0x02U << I2S_CFGR_DATLEN_Pos)            ///<  Audio data width 32 
+
+#define I2S_CFGR_I2SSTD_Pos             (4)
+#define I2S_CFGR_I2SSTD_PCM             (0x00U << I2S_CFGR_I2SSTD_Pos)            ///<  I2S selection PCM standard
+#define I2S_CFGR_I2SSTD_MSB_R           (0x01U << I2S_CFGR_I2SSTD_Pos)            ///<  I2S selection Right alignment (MSB) standard
+#define I2S_CFGR_I2SSTD_MSB_L           (0x02U << I2S_CFGR_I2SSTD_Pos)            ///<  I2S selection Left aligned (MSB) standard
+#define I2S_CFGR_I2SSTD_Philips         (0x03U << I2S_CFGR_I2SSTD_Pos)            ///<  I2S selection Philips standard
+
+#define I2S_CFGR_PCMSYNC_Pos            (6)
+#define I2S_CFGR_PCMSYNC                (0x01U << I2S_CFGR_PCMSYNC_Pos)           ///<  PCM frame synchronization mode
+#define I2S_CFGR_SPI_I2S_Pos            (10)
+#define I2S_CFGR_SPI_I2S                (0x01U << I2S_CFGR_SPI_I2S_Pos)           ///<  SPI/I2S module function selection
+#define I2S_CFGR_MCKOE_Pos              (11)
+#define I2S_CFGR_MCKOE                  (0x01U << I2S_CFGR_MCKOE_Pos)             ///<  I2S master clock output enable
+#define I2S_CFGR_I2SDIV_Pos             (16)
+#define I2S_CFGR_I2SDIV                 (0x1FFU << I2S_CFGR_I2SDIV_Pos)           ///<  The frequency division
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h
new file mode 100644
index 000000000..677250dc8
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h
@@ -0,0 +1,299 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_syscfg.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_SYSCFG_H
+#define __REG_SYSCFG_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+#define SYSCFG_BASE                     (APB2PERIPH_BASE + 0x0000)              ///< Base Address: 0x40010000
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief SysTem Configuration Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    union {
+        __IO u32 CFGR;                                                          ///< SYSCFG configuration register                  offset: 0x00
+        __IO u32 CFGR1;
+    };
+    __IO u32 RESERVED0x04;                                                      ///< RESERVED register                              offset: 0x04
+    __IO u32 EXTICR[4];                                                         ///< SYSCFG configuration register                  offset: 0x08-0x14
+    __IO u32 CFGR2;                                                             ///< SYSCFG configuration2 register                 offset: 0x18
+    __IO u32 PDETCSR;                                                           ///< SYSCFG Power Detect configuration stautus reg  offset: 0x1C
+    __IO u32 VOSDLY;                                                            ///< SYSCFG VOSDLY Counter register                 offset: 0x20
+} SYSCFG_TypeDef;
+
+
+#define SYSCFG                             ((SYSCFG_TypeDef *) SYSCFG_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+///@brief System Configuration (SYSCFG)
+////////////////////////////////////////////////////////////////////////////////
+
+/// @brief SYSCFG_CFGR Register Bit definition
+#define SYSCFG_CFGR_MEM_MODE_Pos           (0)
+#define SYSCFG_CFGR_MEM_MODE               ((u32)0x00000003)               ///< SYSCFG_Memory Remap Config
+#define SYSCFG_CFGR_MEM_MODE_0             ((u32)0x00000001)               ///< SYSCFG_Memory Remap Config Bit 0
+#define SYSCFG_CFGR_MEM_MODE_1             ((u32)0x00000002)               ///< SYSCFG_Memory Remap Config Bit 1
+///
+
+#define SYSCFG_CFGR_FSMC_SYNC_EN_Pos    (27)
+#define SYSCFG_CFGR_FSMC_SYNC_EN        (0x01U  << SYSCFG_CFGR_FSMC_SYNC_EN_Pos)///< FSMC SYNC Enable
+#define SYSCFG_CFGR_FSMC_AF_ADDR_Pos    (28)
+#define SYSCFG_CFGR_FSMC_AF_ADDR        (0x01U  << SYSCFG_CFGR_FSMC_AF_ADDR_Pos)///< FSMC Databus AF Address
+#define SYSCFG_CFGR_FSMC_MODE_Pos       (29)
+#define SYSCFG_CFGR_FSMC_MODE           ((u32)0x03<<SYSCFG_CFGR_FSMC_MODE_Pos)  ///< FSMC Interface Mode Config
+#define SYSCFG_CFGR_FSMC_MODE0          ((u32)0x00<<SYSCFG_CFGR_FSMC_MODE_Pos)  ///< FSMC Mode Config Mode 0
+#define SYSCFG_CFGR_FSMC_MODE1          ((u32)0x01<<SYSCFG_CFGR_FSMC_MODE_Pos)  ///< FSMC Mode Config Mode 1
+
+
+/// @brief SYSCFG_EXTICR1 Register Bit definition
+#define SYSCFG_EXTICR1_EXTI0               ((u16)0x000F)                   ///< EXTI 0 configuration
+#define SYSCFG_EXTICR1_EXTI1               ((u16)0x00F0)                   ///< EXTI 1 configuration
+#define SYSCFG_EXTICR1_EXTI2               ((u16)0x0F00)                   ///< EXTI 2 configuration
+#define SYSCFG_EXTICR1_EXTI3               ((u16)0xF000)                   ///< EXTI 3 configuration
+
+///  @brief  EXTI0 configuration
+#define SYSCFG_EXTICR1_EXTI0_PA            ((u16)0x0000)                   ///< PA[0] pin
+#define SYSCFG_EXTICR1_EXTI0_PB            ((u16)0x0001)                   ///< PB[0] pin
+#define SYSCFG_EXTICR1_EXTI0_PC            ((u16)0x0002)                   ///< PC[0] pin
+#define SYSCFG_EXTICR1_EXTI0_PD            ((u16)0x0003)                   ///< PD[0] pin
+
+///  @brief  EXTI1 configuration
+#define SYSCFG_EXTICR1_EXTI1_PA            ((u16)0x0000)                   ///< PA[1] pin
+#define SYSCFG_EXTICR1_EXTI1_PB            ((u16)0x0010)                   ///< PB[1] pin
+#define SYSCFG_EXTICR1_EXTI1_PC            ((u16)0x0020)                   ///< PC[1] pin
+#define SYSCFG_EXTICR1_EXTI1_PD            ((u16)0x0030)                   ///< PD[1] pin
+
+///  @brief  EXTI2 configuration
+#define SYSCFG_EXTICR1_EXTI2_PA            ((u16)0x0000)                   ///< PA[2] pin
+#define SYSCFG_EXTICR1_EXTI2_PB            ((u16)0x0100)                   ///< PB[2] pin
+#define SYSCFG_EXTICR1_EXTI2_PC            ((u16)0x0200)                   ///< PC[2] pin
+#define SYSCFG_EXTICR1_EXTI2_PD            ((u16)0x0300)                   ///< PD[2] pin
+
+
+///  @brief  EXTI3 configuration
+#define SYSCFG_EXTICR1_EXTI3_PA            ((u16)0x0000)                   ///< PA[3] pin
+#define SYSCFG_EXTICR1_EXTI3_PB            ((u16)0x1000)                   ///< PB[3] pin
+#define SYSCFG_EXTICR1_EXTI3_PC            ((u16)0x2000)                   ///< PC[3] pin
+#define SYSCFG_EXTICR1_EXTI3_PD            ((u16)0x3000)                   ///< PD[3] pin
+
+
+/// @brief SYSCFG_EXTICR2 Register Bit definition
+#define SYSCFG_EXTICR2_EXTI4               ((u16)0x000F)                   ///< EXTI 4 configuration
+#define SYSCFG_EXTICR2_EXTI5               ((u16)0x00F0)                   ///< EXTI 5 configuration
+#define SYSCFG_EXTICR2_EXTI6               ((u16)0x0F00)                   ///< EXTI 6 configuration
+#define SYSCFG_EXTICR2_EXTI7               ((u16)0xF000)                   ///< EXTI 7 configuration
+
+/// @brief  EXTI4 configuration
+#define SYSCFG_EXTICR2_EXTI4_PA            ((u16)0x0000)                   ///< PA[4] pin
+#define SYSCFG_EXTICR2_EXTI4_PB            ((u16)0x0001)                   ///< PB[4] pin
+#define SYSCFG_EXTICR2_EXTI4_PC            ((u16)0x0002)                   ///< PC[4] pin
+#define SYSCFG_EXTICR2_EXTI4_PD            ((u16)0x0003)                   ///< PD[4] pin
+
+
+/// @brief  EXTI5 configuration
+#define SYSCFG_EXTICR2_EXTI5_PA            ((u16)0x0000)                   ///< PA[5] pin
+#define SYSCFG_EXTICR2_EXTI5_PB            ((u16)0x0010)                   ///< PB[5] pin
+#define SYSCFG_EXTICR2_EXTI5_PC            ((u16)0x0020)                   ///< PC[5] pin
+#define SYSCFG_EXTICR2_EXTI5_PD            ((u16)0x0030)                   ///< PD[5] pin
+
+/// @brief  EXTI6 configuration
+
+#define SYSCFG_EXTICR2_EXTI6_PA            ((u16)0x0000)                   ///< PA[6] pin
+#define SYSCFG_EXTICR2_EXTI6_PB            ((u16)0x0100)                   ///< PB[6] pin
+#define SYSCFG_EXTICR2_EXTI6_PC            ((u16)0x0200)                   ///< PC[6] pin
+#define SYSCFG_EXTICR2_EXTI6_PD            ((u16)0x0300)                   ///< PD[6] pin
+
+
+/// @brief  EXTI7 configuration
+#define SYSCFG_EXTICR2_EXTI7_PA            ((u16)0x0000)                   ///< PA[7] pin
+#define SYSCFG_EXTICR2_EXTI7_PB            ((u16)0x1000)                   ///< PB[7] pin
+#define SYSCFG_EXTICR2_EXTI7_PC            ((u16)0x2000)                   ///< PC[7] pin
+#define SYSCFG_EXTICR2_EXTI7_PD            ((u16)0x3000)                   ///< PD[7] pin
+
+/// @brief SYSCFG_EXTICR3 Register Bit definition
+#define SYSCFG_EXTICR3_EXTI8               ((u16)0x000F)                   ///< EXTI 8 configuration
+#define SYSCFG_EXTICR3_EXTI9               ((u16)0x00F0)                   ///< EXTI 9 configuration
+#define SYSCFG_EXTICR3_EXTI10              ((u16)0x0F00)                   ///< EXTI 10 configuration
+#define SYSCFG_EXTICR3_EXTI11              ((u16)0xF000)                   ///< EXTI 11 configuration
+
+///  @brief  EXTI8 configuration
+#define SYSCFG_EXTICR3_EXTI8_PA            ((u16)0x0000)                   ///< PA[8] pin
+#define SYSCFG_EXTICR3_EXTI8_PB            ((u16)0x0001)                   ///< PB[8] pin
+#define SYSCFG_EXTICR3_EXTI8_PC            ((u16)0x0002)                   ///< PC[8] pin
+#define SYSCFG_EXTICR3_EXTI8_PD            ((u16)0x0003)                   ///< PD[8] pin
+
+
+///  @brief  EXTI9 configuration
+
+#define SYSCFG_EXTICR3_EXTI9_PA            ((u16)0x0000)                   ///< PA[9] pin
+#define SYSCFG_EXTICR3_EXTI9_PB            ((u16)0x0010)                   ///< PB[9] pin
+#define SYSCFG_EXTICR3_EXTI9_PC            ((u16)0x0020)                   ///< PC[9] pin
+#define SYSCFG_EXTICR3_EXTI9_PD            ((u16)0x0030)                   ///< PD[9] pin
+
+///  @brief  EXTI10 configuration
+#define SYSCFG_EXTICR3_EXTI10_PA           ((u16)0x0000)                   ///< PA[10] pin
+#define SYSCFG_EXTICR3_EXTI10_PB           ((u16)0x0100)                   ///< PB[10] pin
+#define SYSCFG_EXTICR3_EXTI10_PC           ((u16)0x0200)                   ///< PC[10] pin
+#define SYSCFG_EXTICR3_EXTI10_PD           ((u16)0x0300)                   ///< PE[10] pin
+
+///  @brief  EXTI11 configuration
+#define SYSCFG_EXTICR3_EXTI11_PA           ((u16)0x0000)                   ///< PA[11] pin
+#define SYSCFG_EXTICR3_EXTI11_PB           ((u16)0x1000)                   ///< PB[11] pin
+#define SYSCFG_EXTICR3_EXTI11_PC           ((u16)0x2000)                   ///< PC[11] pin
+#define SYSCFG_EXTICR3_EXTI11_PD           ((u16)0x3000)                   ///< PD[11] pin
+
+
+/// @brief SYSCFG_EXTICR4 Register Bit definition
+#define SYSCFG_EXTICR4_EXTI12               ((u16)0x000F)                  ///< EXTI 12 configuration
+#define SYSCFG_EXTICR4_EXTI13               ((u16)0x00F0)                  ///< EXTI 13 configuration
+#define SYSCFG_EXTICR4_EXTI14               ((u16)0x0F00)                  ///< EXTI 14 configuration
+#define SYSCFG_EXTICR4_EXTI15               ((u16)0xF000)                  ///< EXTI 15 configuration
+
+#define SYSCFG_EXTICR4_EXTI12_PA            ((u16)0x0000)                  ///< PA[12] pin for EXTI12
+#define SYSCFG_EXTICR4_EXTI12_PB            ((u16)0x0001)                  ///< PB[12] pin for EXTI12
+#define SYSCFG_EXTICR4_EXTI12_PC            ((u16)0x0002)                  ///< PC[12] pin for EXTI12
+#define SYSCFG_EXTICR4_EXTI12_PD            ((u16)0x0003)                  ///< PD[12] pin for EXTI12
+
+#define SYSCFG_EXTICR4_EXTI13_PA            ((u16)0x0000)                  ///< PA[13] pin for EXTI13
+#define SYSCFG_EXTICR4_EXTI13_PB            ((u16)0x0010)                  ///< PB[13] pin for EXTI13
+#define SYSCFG_EXTICR4_EXTI13_PC            ((u16)0x0020)                  ///< PC[13] pin for EXTI13
+#define SYSCFG_EXTICR4_EXTI13_PD            ((u16)0x0030)                  ///< PD[13] pin for EXTI13
+
+#define SYSCFG_EXTICR4_EXTI14_PA            ((u16)0x0000)                  ///< PA[14] pin for EXTI14
+#define SYSCFG_EXTICR4_EXTI14_PB            ((u16)0x0100)                  ///< PB[14] pin for EXTI14
+#define SYSCFG_EXTICR4_EXTI14_PC            ((u16)0x0200)                  ///< PC[14] pin for EXTI14
+#define SYSCFG_EXTICR4_EXTI14_PD            ((u16)0x0300)                  ///< PD[14] pin for EXTI14
+
+#define SYSCFG_EXTICR4_EXTI15_PA            ((u16)0x0000)                  ///< PA[15] pin for EXTI15
+#define SYSCFG_EXTICR4_EXTI15_PB            ((u16)0x1000)                  ///< PB[15] pin for EXTI15
+#define SYSCFG_EXTICR4_EXTI15_PC            ((u16)0x2000)                  ///< PC[15] pin for EXTI15
+#define SYSCFG_EXTICR4_EXTI15_PD            ((u16)0x3000)                  ///< PD[15] pin for EXTI15
+
+
+
+
+#define SYSCFG_CFGR2_I2C1_MODE_SEL_Pos             (16)
+#define SYSCFG_CFGR2_I2C1_MODE_SEL                 (0x01U  << SYSCFG_CFGR2_I2C1_MODE_SEL_Pos)                   ///< I2C1 Enable PushPull mode
+#define SYSCFG_CFGR2_I2C2_MODE_SEL_Pos             (17)
+#define SYSCFG_CFGR2_I2C2_MODE_SEL                 (0x01U  << SYSCFG_CFGR2_I2C2_MODE_SEL_Pos)                   ///< I2C2 Enable PushPull mode
+
+#define SYSCFG_CFGR2_MII_RMII_MODE_SEL_Pos         (20)
+#define SYSCFG_CFGR2_MII_RMII_MODE_SEL             (0x01U  << SYSCFG_CFGR2_MII_RMII_MODE_SEL_Pos)               ///< MII_RMII mode
+#define SYSCFG_CFGR2_MAC_SPEED_SEL_Pos             (21)
+#define SYSCFG_CFGR2_MAC_SPEED_SEL                 (0x01U  << SYSCFG_CFGR2_MAC_SPEED_SEL_Pos)                   ///< MAC_SPEED mode
+
+
+#define SYSCFG_PDETCSR_PVDE_Pos             (0)
+#define SYSCFG_PDETCSR_PVDE                 (0x01U  << SYSCFG_PDETCSR_PVDE_Pos)                     ///< Power Voltage Detector Enable
+
+#define SYSCFG_PDETCSR_PLS_Pos              (1)
+#define SYSCFG_PDETCSR_PLS                  (0x0FU  << SYSCFG_PDETCSR_PLS_Pos)
+
+#define SYSCFG_PDETCSR_PLS_1V7              (0x00U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 1.7V
+#define SYSCFG_PDETCSR_PLS_2V0              (0x01U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 2.0V
+#define SYSCFG_PDETCSR_PLS_2V3              (0x02U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 2.3V
+#define SYSCFG_PDETCSR_PLS_2V6              (0x03U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 2.6V
+#define SYSCFG_PDETCSR_PLS_2V9              (0x04U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 2.9V
+#define SYSCFG_PDETCSR_PLS_3V2              (0x05U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 3.2V
+#define SYSCFG_PDETCSR_PLS_3V5              (0x06U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 3.5V
+#define SYSCFG_PDETCSR_PLS_3V8              (0x07U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 3.8V
+#define SYSCFG_PDETCSR_PLS_4V1              (0x08U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 4.1V
+#define SYSCFG_PDETCSR_PLS_4V4              (0x09U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 4.4V
+#define SYSCFG_PDETCSR_PLS_4V7              (0x0AU  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 4.7V
+
+// #define PWR_CR_PLS_Pos                      SYSCFG_PDETCSR_PLS_Pos
+// #define PWR_CR_PLS                          SYSCFG_PDETCSR_PLS
+// #define PWR_CR_PLS_1V8                      SYSCFG_PDETCSR_PLS_1V7                          ///< PVD level 1.8V
+// #define PWR_CR_PLS_2V1                      SYSCFG_PDETCSR_PLS_2V0                          ///< PVD level 2.1V
+// #define PWR_CR_PLS_2V4                      SYSCFG_PDETCSR_PLS_2V3                          ///< PVD level 2.4V
+// #define PWR_CR_PLS_2V7                      SYSCFG_PDETCSR_PLS_2V6                          ///< PVD level 2.7V
+// #define PWR_CR_PLS_3V0                      SYSCFG_PDETCSR_PLS_2V9                          ///< PVD level 3.0V
+// #define PWR_CR_PLS_3V3                      SYSCFG_PDETCSR_PLS_3V2                          ///< PVD level 3.3V
+// #define PWR_CR_PLS_3V6                      SYSCFG_PDETCSR_PLS_3V5                          ///< PVD level 3.6V
+// #define PWR_CR_PLS_3V9                      SYSCFG_PDETCSR_PLS_3V8                          ///< PVD level 3.9V
+// #define PWR_CR_PLS_4V2                      SYSCFG_PDETCSR_PLS_4V1                          ///< PVD level 4.2V
+// #define PWR_CR_PLS_4V5                      SYSCFG_PDETCSR_PLS_4V4                          ///< PVD level 4.5V
+// #define PWR_CR_PLS_4V8                      SYSCFG_PDETCSR_PLS_4V7                          ///< PVD level 4.8V
+
+#define SYSCFG_PDETCSR_PVDO_Pos             (5)
+#define SYSCFG_PDETCSR_PVDO                 (0x01U  << SYSCFG_PDETCSR_PVDO_Pos)             ///< PVD Output
+// #define PWR_CSR_PVDO_Pos                    SYSCFG_PDETCSR_PVDO_Pos
+// #define PWR_CSR_PVDO                        SYSCFG_PDETCSR_PVDO                             ///< PVD Output
+
+#define SYSCFG_PDETCSR_VDTO_Pos             (6)
+#define SYSCFG_PDETCSR_VDTO                 (0x01U  << SYSCFG_PDETCSR_VDTO_Pos)             ///< VDT Output Enable
+
+#define SYSCFG_PDETCSR_VDTE_Pos             (8)
+#define SYSCFG_PDETCSR_VDTE                 (0x01U  << SYSCFG_PDETCSR_VDTE_Pos)             ///< VDT Output
+
+#define SYSCFG_PDETCSR_VDTLS_Pos            (9)
+#define SYSCFG_PDETCSR_VDTLS                (0x0FU  << SYSCFG_PDETCSR_VDTLS_Pos)
+#define SYSCFG_PDETCSR_VDTLS_0V9            (0x00U  << SYSCFG_PDETCSR_VDTLS_Pos)            ///< VDT level 0.9V
+#define SYSCFG_PDETCSR_VDTLS_1V0            (0x01U  << SYSCFG_PDETCSR_VDTLS_Pos)            ///< VDT level 1.0V
+#define SYSCFG_PDETCSR_VDTLS_1V1            (0x02U  << SYSCFG_PDETCSR_VDTLS_Pos)            ///< VDT level 1.1V
+#define SYSCFG_PDETCSR_VDTLS_1V2            (0x03U  << SYSCFG_PDETCSR_VDTLS_Pos)            ///< VDT level 1.2V
+
+#define SYSCFG_PDETCSR_VBATDIV3EN_Pos       (11)
+#define SYSCFG_PDETCSR_VBATDIV3EN           (0x01U  << SYSCFG_PDETCSR_VBATDIV3EN_Pos)       ///< VBATDIV3 Enable
+
+#define SYSCFG_VOSDLY_CNT_Pos               (0)
+#define SYSCFG_VOSDLY_CNT                   (0x03FFU << SYSCFG_VOSDLY_CNT_Pos)              ///< SYSCFG VOSDLY CNT
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h
new file mode 100644
index 000000000..b9022e2ff
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h
@@ -0,0 +1,681 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_tim.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_TIM_H
+#define __REG_TIM_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM1_BASE                       (APB2PERIPH_BASE + 0x2C00)              ///< Base Address: 0x40012C00
+#define TIM2_BASE                       (APB1PERIPH_BASE + 0x0000)              ///< Base Address: 0x40000000
+#define TIM3_BASE                       (APB1PERIPH_BASE + 0x0400)              ///< Base Address: 0x40000400
+#define TIM4_BASE                       (APB1PERIPH_BASE + 0x0800)              ///< Base Address: 0x40000800
+
+#define TIM5_BASE                       (APB1PERIPH_BASE + 0x0C00)              ///< Base Address: 0x40000C00
+#define TIM6_BASE                       (APB1PERIPH_BASE + 0x1000)              ///< Base Address: 0x40001000
+#define TIM7_BASE                       (APB1PERIPH_BASE + 0x1400)              ///< Base Address: 0x40001400
+#define TIM8_BASE                       (APB2PERIPH_BASE + 0x3400)              ///< Base Address: 0x40013400
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief Timer Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 CR1;                                                               ///< TIM control register 1,                        offset: 0x00
+    __IO u32 CR2;                                                               ///< TIM control register 2,                        offset: 0x04
+    __IO u32 SMCR;                                                              ///< TIM slave Mode Control register,               offset: 0x08
+    __IO u32 DIER;                                                              ///< TIM DMA/interrupt enable register,             offset: 0x0C
+    __IO u32 SR;                                                                ///< TIM status register,                           offset: 0x10
+    __IO u32 EGR;                                                               ///< TIM event generation register,                 offset: 0x14
+    __IO u32 CCMR1;                                                             ///< TIM capture/compare mode register 1,           offset: 0x18
+    __IO u32 CCMR2;                                                             ///< TIM capture/compare mode register 2,           offset: 0x1C
+    __IO u32 CCER;                                                              ///< TIM capture/compare enable register,           offset: 0x20
+    __IO u32 CNT;                                                               ///< TIM counter register,                          offset: 0x24
+    __IO u32 PSC;                                                               ///< TIM prescaler register,                        offset: 0x28
+    __IO u32 ARR;                                                               ///< TIM auto-reload register,                      offset: 0x2C
+    __IO u32 RCR;                                                               ///< TIM repetition counter register,               offset: 0x30
+    __IO u32 CCR1;                                                              ///< TIM capture/compare register 1,                offset: 0x34
+    __IO u32 CCR2;                                                              ///< TIM capture/compare register 2,                offset: 0x38
+    __IO u32 CCR3;                                                              ///< TIM capture/compare register 3,                offset: 0x3C
+    __IO u32 CCR4;                                                              ///< TIM capture/compare register 4,                offset: 0x40
+    __IO u32 BDTR;                                                              ///< TIM break and dead-time register,              offset: 0x44
+    __IO u32 DCR;                                                               ///< TIM DMA control register,                      offset: 0x48
+    __IO u32 DMAR;                                                              ///< TIM DMA address for full transfer register,    offset: 0x4C
+    __IO u32 OR;                                                                ///< Option register,                               offset: 0x50
+    __IO u32 CCMR3;                                                             ///< TIM capture/compare mode register 3,           offset: 0x54
+    __IO u32 CCR5;                                                              ///< TIM capture/compare register 5,                offset: 0x58
+    __IO u32 PDER;                                                              ///< PWM Shift repeat enable register,                offset: 0x5C
+    __IO u32 CCR1FALL;                                                          ///< PWM shift count CCR1 register,                 offset: 0x60
+    __IO u32 CCR2FALL;                                                          ///< PWM shift count CCR2 register,                 offset: 0x64
+    __IO u32 CCR3FALL;                                                          ///< PWM shift count CCR3 register,                 offset: 0x68
+    __IO u32 CCR4FALL;                                                          ///< PWM shift count CCR4 register,                 offset: 0x6c
+    __IO u32 CCR5FALL;                                                          ///< PWM shift count CCR5 register,                 offset: 0x70
+} TIM_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM1                            ((TIM_TypeDef*) TIM1_BASE)
+#define TIM2                            ((TIM_TypeDef*) TIM2_BASE)
+#define TIM3                            ((TIM_TypeDef*) TIM3_BASE)
+#define TIM4                            ((TIM_TypeDef*) TIM4_BASE)
+
+#define TIM5                            ((TIM_TypeDef*) TIM5_BASE)
+#define TIM6                            ((TIM_TypeDef*) TIM6_BASE)
+#define TIM7                            ((TIM_TypeDef*) TIM7_BASE)
+
+#define TIM8                            ((TIM_TypeDef*) TIM8_BASE)
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CR1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CR1_CEN_Pos                 (0)
+#define TIM_CR1_CEN                     (0x01U << TIM_CR1_CEN_Pos)              ///< Counter enable
+#define TIM_CR1_UDIS_Pos                (1)
+#define TIM_CR1_UDIS                    (0x01U << TIM_CR1_UDIS_Pos)             ///< Update disable
+#define TIM_CR1_URS_Pos                 (2)
+#define TIM_CR1_URS                     (0x01U << TIM_CR1_URS_Pos)              ///< Update request source
+#define TIM_CR1_OPM_Pos                 (3)
+#define TIM_CR1_OPM                     (0x01U << TIM_CR1_OPM_Pos)              ///< One pulse mode
+#define TIM_CR1_DIR_Pos                 (4)
+#define TIM_CR1_DIR                     (0x01U << TIM_CR1_DIR_Pos)              ///< Direction
+#define TIM_CR1_CMS_Pos                 (5)
+#define TIM_CR1_CMS                     (0x03U << TIM_CR1_CMS_Pos)              ///< CMS[1:0] bits (Center-aligned mode selection)
+#define TIM_CR1_CMS_EDGEALIGNED         (0x00U << TIM_CR1_CMS_Pos)              ///< Edge-aligned mode
+#define TIM_CR1_CMS_CENTERALIGNED1      (0x01U << TIM_CR1_CMS_Pos)              ///< Center-aligned mode 1
+#define TIM_CR1_CMS_CENTERALIGNED2      (0x02U << TIM_CR1_CMS_Pos)              ///< Center-aligned mode 2
+#define TIM_CR1_CMS_CENTERALIGNED3      (0x03U << TIM_CR1_CMS_Pos)              ///< Center-aligned mode 3
+#define TIM_CR1_ARPEN_Pos               (7)
+#define TIM_CR1_ARPEN                   (0x01U << TIM_CR1_ARPEN_Pos)            ///< Auto-reload preload enable
+#define TIM_CR1_CKD_Pos                 (8)
+#define TIM_CR1_CKD                     (0x03U << TIM_CR1_CKD_Pos)              ///< CKD[1:0] bits (clock division)
+#define TIM_CR1_CKD_DIV1                (0x00U << TIM_CR1_CKD_Pos)              ///< Divided by 1
+#define TIM_CR1_CKD_DIV2                (0x01U << TIM_CR1_CKD_Pos)              ///< Divided by 2
+#define TIM_CR1_CKD_DIV4                (0x02U << TIM_CR1_CKD_Pos)              ///< Divided by 4
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CR2_CCPC_Pos                (0)
+#define TIM_CR2_CCPC                    (0x01U << TIM_CR2_CCPC_Pos)             ///< Capture/Compare Preloaded Control
+#define TIM_CR2_CCUS_Pos                (2)
+#define TIM_CR2_CCUS                    (0x01U << TIM_CR2_CCUS_Pos)             ///< Capture/Compare Control Update Selection
+#define TIM_CR2_CCDS_Pos                (3)
+#define TIM_CR2_CCDS                    (0x01U << TIM_CR2_CCDS_Pos)             ///< Capture/Compare DMA Selection
+#define TIM_CR2_MMS_Pos                 (4)
+#define TIM_CR2_MMS                     (0x07U << TIM_CR2_MMS_Pos)              ///< MMS[2:0] bits (Master Mode Selection)
+#define TIM_CR2_MMS_RESET               (0x00U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: Reset
+#define TIM_CR2_MMS_ENABLE              (0x01U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: Enable
+#define TIM_CR2_MMS_UPDATE              (0x02U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: Update
+#define TIM_CR2_MMS_OC1                 (0x03U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: OC1
+#define TIM_CR2_MMS_OC1REF              (0x04U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: OC1Ref
+#define TIM_CR2_MMS_OC2REF              (0x05U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: OC2Ref
+#define TIM_CR2_MMS_OC3REF              (0x06U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: OC3Ref
+#define TIM_CR2_MMS_OC4REF              (0x07U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: OC4Ref
+#define TIM_CR2_TI1S_Pos                (7)
+#define TIM_CR2_TI1S                    (0x01U << TIM_CR2_TI1S_Pos)             ///< TI1 Selection
+#define TIM_CR2_OIS1_Pos                (8)
+#define TIM_CR2_OIS1                    (0x01U << TIM_CR2_OIS1_Pos)             ///< Output Idle state 1 (OC1 output)
+#define TIM_CR2_OIS1N_Pos               (9)
+#define TIM_CR2_OIS1N                   (0x01U << TIM_CR2_OIS1N_Pos)            ///< Output Idle state 1 (OC1N output)
+#define TIM_CR2_OIS2_Pos                (10)
+#define TIM_CR2_OIS2                    (0x01U << TIM_CR2_OIS2_Pos)             ///< Output Idle state 2 (OC2 output)
+#define TIM_CR2_OIS2N_Pos               (11)
+#define TIM_CR2_OIS2N                   (0x01U << TIM_CR2_OIS2N_Pos)            ///< Output Idle state 2 (OC2N output)
+#define TIM_CR2_OIS3_Pos                (12)
+#define TIM_CR2_OIS3                    (0x01U << TIM_CR2_OIS3_Pos)             ///< Output Idle state 3 (OC3 output)
+#define TIM_CR2_OIS3N_Pos               (13)
+#define TIM_CR2_OIS3N                   (0x01U << TIM_CR2_OIS3N_Pos)            ///< Output Idle state 3 (OC3N output)
+#define TIM_CR2_OIS4_Pos                (14)
+#define TIM_CR2_OIS4                    (0x01U << TIM_CR2_OIS4_Pos)             ///< Output Idle state 4 (OC4 output)
+
+
+#define TIM_CR2_OIS5_Pos                (16)
+#define TIM_CR2_OIS5                    (0x01U << TIM_CR2_OIS5_Pos)             ///< Output Idle state 5 (OC5 output)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_SMCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_SMCR_SMS_Pos                (0)
+#define TIM_SMCR_SMS                    (0x07U << TIM_SMCR_SMS_Pos)             ///< SMS[2:0] bits (Slave mode selection)
+#define TIM_SMCR_SMS_OFF                (0x00U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: OFF
+#define TIM_SMCR_SMS_ENCODER1           (0x01U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Encoder1
+#define TIM_SMCR_SMS_ENCODER2           (0x02U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Encoder2
+#define TIM_SMCR_SMS_ENCODER3           (0x03U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Encoder3
+#define TIM_SMCR_SMS_RESET              (0x04U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Reset
+#define TIM_SMCR_SMS_GATED              (0x05U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Gated
+#define TIM_SMCR_SMS_TRIGGER            (0x06U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Trigger
+#define TIM_SMCR_SMS_EXTERNAL1          (0x07U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: External1
+
+#define TIM_SMCR_OCCS_Pos               (3)
+#define TIM_SMCR_OCCS                   (0x01U << TIM_SMCR_OCCS_Pos)            ///< Output compare clear selection
+
+#define TIM_SMCR_TS_Pos                 (4)
+#define TIM_SMCR_TS                     (0x07U << TIM_SMCR_TS_Pos)              ///< TS[2:0] bits (Trigger selection)
+#define TIM_SMCR_TS_ITR0                (0x00U << TIM_SMCR_TS_Pos)              ///< Internal Trigger 0 (ITR0)
+#define TIM_SMCR_TS_ITR1                (0x01U << TIM_SMCR_TS_Pos)              ///< Internal Trigger 1 (ITR1)
+#define TIM_SMCR_TS_ITR2                (0x02U << TIM_SMCR_TS_Pos)              ///< Internal Trigger 2 (ITR2)
+#define TIM_SMCR_TS_ITR3                (0x03U << TIM_SMCR_TS_Pos)              ///< Internal Trigger 3 (ITR3)
+#define TIM_SMCR_TS_TI1F_ED             (0x04U << TIM_SMCR_TS_Pos)              ///< TI1 Edge Detector (TI1F_ED)
+#define TIM_SMCR_TS_TI1FP1              (0x05U << TIM_SMCR_TS_Pos)              ///< Filtered Timer Input 1 (TI1FP1)
+#define TIM_SMCR_TS_TI2FP2              (0x06U << TIM_SMCR_TS_Pos)              ///< Filtered Timer Input 2 (TI2FP2)
+#define TIM_SMCR_TS_ETRF                (0x07U << TIM_SMCR_TS_Pos)              ///< External Trigger input (ETRF)
+#define TIM_SMCR_MSM_Pos                (7)
+#define TIM_SMCR_MSM                    (0x01U << TIM_SMCR_MSM_Pos)             ///< Master/slave mode
+#define TIM_SMCR_ETF_Pos                (8)
+#define TIM_SMCR_ETF                    (0x0FU << TIM_SMCR_ETF_Pos)             ///< ETF[3:0] bits (External trigger filter)
+#define TIM_SMCR_ETF_0                  (0x01U << TIM_SMCR_ETF_Pos)             ///< Bit 0
+#define TIM_SMCR_ETF_1                  (0x02U << TIM_SMCR_ETF_Pos)             ///< Bit 1
+#define TIM_SMCR_ETF_2                  (0x04U << TIM_SMCR_ETF_Pos)             ///< Bit 2
+#define TIM_SMCR_ETF_3                  (0x08U << TIM_SMCR_ETF_Pos)             ///< Bit 3
+#define TIM_SMCR_ETPS_Pos               (12)
+#define TIM_SMCR_ETPS                   (0x03U << TIM_SMCR_ETPS_Pos)            ///< ETPS[1:0] bits (External trigger prescaler)
+#define TIM_SMCR_ETPS_OFF               (0x00U << TIM_SMCR_ETPS_Pos)            ///< Prescaler OFF
+#define TIM_SMCR_ETPS_DIV2              (0x01U << TIM_SMCR_ETPS_Pos)            ///< ETRP frequency divided by 2
+#define TIM_SMCR_ETPS_DIV4              (0x02U << TIM_SMCR_ETPS_Pos)            ///< ETRP frequency divided by 4
+#define TIM_SMCR_ETPS_DIV8              (0x03U << TIM_SMCR_ETPS_Pos)            ///< ETRP frequency divided by 8
+#define TIM_SMCR_ECEN_Pos               (14)
+#define TIM_SMCR_ECEN                   (0x01U << TIM_SMCR_ECEN_Pos)            ///< External clock enable
+#define TIM_SMCR_ETP_Pos                (15)
+#define TIM_SMCR_ETP                    (0x01U << TIM_SMCR_ETP_Pos)             ///< External trigger polarity
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DIER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_DIER_UI_Pos                 (0)
+#define TIM_DIER_UI                     (0x01U << TIM_DIER_UI_Pos)              ///< Update interrupt enable
+#define TIM_DIER_CC1I_Pos               (1)
+#define TIM_DIER_CC1I                   (0x01U << TIM_DIER_CC1I_Pos)            ///< Capture/Compare 1 interrupt enable
+#define TIM_DIER_CC2I_Pos               (2)
+#define TIM_DIER_CC2I                   (0x01U << TIM_DIER_CC2I_Pos)            ///< Capture/Compare 2 interrupt enable
+#define TIM_DIER_CC3I_Pos               (3)
+#define TIM_DIER_CC3I                   (0x01U << TIM_DIER_CC3I_Pos)            ///< Capture/Compare 3 interrupt enable
+#define TIM_DIER_CC4I_Pos               (4)
+#define TIM_DIER_CC4I                   (0x01U << TIM_DIER_CC4I_Pos)            ///< Capture/Compare 4 interrupt enable
+#define TIM_DIER_COMI_Pos               (5)
+#define TIM_DIER_COMI                   (0x01U << TIM_DIER_COMI_Pos)            ///< COM interrupt enable
+#define TIM_DIER_TI_Pos                 (6)
+#define TIM_DIER_TI                     (0x01U << TIM_DIER_TI_Pos)              ///< Trigger interrupt enable
+#define TIM_DIER_BI_Pos                 (7)
+#define TIM_DIER_BI                     (0x01U << TIM_DIER_BI_Pos)              ///< Break interrupt enable
+#define TIM_DIER_UD_Pos                 (8)
+#define TIM_DIER_UD                     (0x01U << TIM_DIER_UD_Pos)              ///< Update DMA request enable
+#define TIM_DIER_CC1D_Pos               (9)
+#define TIM_DIER_CC1D                   (0x01U << TIM_DIER_CC1D_Pos)            ///< Capture/Compare 1 DMA request enable
+#define TIM_DIER_CC2D_Pos               (10)
+#define TIM_DIER_CC2D                   (0x01U << TIM_DIER_CC2D_Pos)            ///< Capture/Compare 2 DMA request enable
+#define TIM_DIER_CC3D_Pos               (11)
+#define TIM_DIER_CC3D                   (0x01U << TIM_DIER_CC3D_Pos)            ///< Capture/Compare 3 DMA request enable
+#define TIM_DIER_CC4D_Pos               (12)
+#define TIM_DIER_CC4D                   (0x01U << TIM_DIER_CC4D_Pos)            ///< Capture/Compare 4 DMA request enable
+#define TIM_DIER_COMD_Pos               (13)
+#define TIM_DIER_COMD                   (0x01U << TIM_DIER_COMD_Pos)            ///< COM DMA request enable
+#define TIM_DIER_TD_Pos                 (14)
+#define TIM_DIER_TD                     (0x01U << TIM_DIER_TD_Pos)              ///< Trigger DMA request enable
+#define TIM_DIER_CC5I_Pos               (16)
+#define TIM_DIER_CC5I                   (0x01U << TIM_DIER_CC5I_Pos)            ///< Capture/Compare 5 interrupt enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_SR_UI_Pos                   (0)
+#define TIM_SR_UI                       (0x01U << TIM_SR_UI_Pos)                ///< Update interrupt Flag
+#define TIM_SR_CC1I_Pos                 (1)
+#define TIM_SR_CC1I                     (0x01U << TIM_SR_CC1I_Pos)              ///< Capture/Compare 1 interrupt Flag
+#define TIM_SR_CC2I_Pos                 (2)
+#define TIM_SR_CC2I                     (0x01U << TIM_SR_CC2I_Pos)              ///< Capture/Compare 2 interrupt Flag
+#define TIM_SR_CC3I_Pos                 (3)
+#define TIM_SR_CC3I                     (0x01U << TIM_SR_CC3I_Pos)              ///< Capture/Compare 3 interrupt Flag
+#define TIM_SR_CC4I_Pos                 (4)
+#define TIM_SR_CC4I                     (0x01U << TIM_SR_CC4I_Pos)              ///< Capture/Compare 4 interrupt Flag
+#define TIM_SR_COMI_Pos                 (5)
+#define TIM_SR_COMI                     (0x01U << TIM_SR_COMI_Pos)              ///< COM interrupt Flag
+#define TIM_SR_TI_Pos                   (6)
+#define TIM_SR_TI                       (0x01U << TIM_SR_TI_Pos)                ///< Trigger interrupt Flag
+#define TIM_SR_BI_Pos                   (7)
+#define TIM_SR_BI                       (0x01U << TIM_SR_BI_Pos)                ///< Break interrupt Flag
+#define TIM_SR_CC1O_Pos                 (9)
+#define TIM_SR_CC1O                     (0x01U << TIM_SR_CC1O_Pos)              ///< Capture/Compare 1 Overcapture Flag
+#define TIM_SR_CC2O_Pos                 (10)
+#define TIM_SR_CC2O                     (0x01U << TIM_SR_CC2O_Pos)              ///< Capture/Compare 2 Overcapture Flag
+#define TIM_SR_CC3O_Pos                 (11)
+#define TIM_SR_CC3O                     (0x01U << TIM_SR_CC3O_Pos)              ///< Capture/Compare 3 Overcapture Flag
+#define TIM_SR_CC4O_Pos                 (12)
+#define TIM_SR_CC4O                     (0x01U << TIM_SR_CC4O_Pos)              ///< Capture/Compare 4 Overcapture Flag
+
+#define TIM_SR_CC5I_Pos                 (16)
+#define TIM_SR_CC5I                     (0x01U << TIM_SR_CC5I_Pos)              ///< Capture/Compare 5 interrupt Flag
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_EGR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_EGR_UG_Pos                  (0)
+#define TIM_EGR_UG                      (0x01U << TIM_EGR_UG_Pos)               ///< Update Generation
+#define TIM_EGR_CC1G_Pos                (1)
+#define TIM_EGR_CC1G                    (0x01U << TIM_EGR_CC1G_Pos)             ///< Capture/Compare 1 Generation
+#define TIM_EGR_CC2G_Pos                (2)
+#define TIM_EGR_CC2G                    (0x01U << TIM_EGR_CC2G_Pos)             ///< Capture/Compare 2 Generation
+#define TIM_EGR_CC3G_Pos                (3)
+#define TIM_EGR_CC3G                    (0x01U << TIM_EGR_CC3G_Pos)             ///< Capture/Compare 3 Generation
+#define TIM_EGR_CC4G_Pos                (4)
+#define TIM_EGR_CC4G                    (0x01U << TIM_EGR_CC4G_Pos)             ///< Capture/Compare 4 Generation
+#define TIM_EGR_COMG_Pos                (5)
+#define TIM_EGR_COMG                    (0x01U << TIM_EGR_COMG_Pos)             ///< Capture/Compare Control Update Generation
+#define TIM_EGR_TG_Pos                  (6)
+#define TIM_EGR_TG                      (0x01U << TIM_EGR_TG_Pos)               ///< Trigger Generation
+#define TIM_EGR_BG_Pos                  (7)
+#define TIM_EGR_BG                      (0x01U << TIM_EGR_BG_Pos)               ///< Break Generation
+
+#define TIM_EGR_CC5G_Pos                (16)
+#define TIM_EGR_CC5G                    (0x01U << TIM_EGR_CC5G_Pos)             ///< Capture/Compare 5 Generation
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCMR1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCMR1_CC1S_Pos              (0)
+#define TIM_CCMR1_CC1S                  (0x03U << TIM_CCMR1_CC1S_Pos)           ///< CC1S[1:0] bits (Capture/Compare 1 Selection)
+#define TIM_CCMR1_CC1S_OC               (0x00U << TIM_CCMR1_CC1S_Pos)           ///< Channel is configured as output
+#define TIM_CCMR1_CC1S_DIRECTTI         (0x01U << TIM_CCMR1_CC1S_Pos)           ///< Channel is configured as input, IC1 is mapped on TI1
+#define TIM_CCMR1_CC1S_INDIRECTTI       (0x02U << TIM_CCMR1_CC1S_Pos)           ///< Channel is configured as input, IC1 is mapped on TI2
+#define TIM_CCMR1_CC1S_TRC              (0x03U << TIM_CCMR1_CC1S_Pos)           ///< Channel is configured as input, IC1 is mapped on TRC
+#define TIM_CCMR1_OC1FEN_Pos            (2)
+#define TIM_CCMR1_OC1FEN                (0x01U << TIM_CCMR1_OC1FEN_Pos)         ///< Output Compare 1 Fast enable
+
+#define TIM_CCMR1_OC1PEN_Pos            (3)
+#define TIM_CCMR1_OC1PEN                (0x01U << TIM_CCMR1_OC1PEN_Pos)         ///< Output Compare 1 Preload enable
+#define TIM_CCMR1_OC1M_Pos              (4)
+#define TIM_CCMR1_OC1M                  (0x07U << TIM_CCMR1_OC1M_Pos)           ///< OC1M[2:0] bits (Output Compare 1 Mode)
+#define TIM_CCMR1_OC1M_TIMING           (0x00U << TIM_CCMR1_OC1M_Pos)           ///< Timing
+#define TIM_CCMR1_OC1M_ACTIVE           (0x01U << TIM_CCMR1_OC1M_Pos)           ///< Active
+#define TIM_CCMR1_OC1M_INACTIVE         (0x02U << TIM_CCMR1_OC1M_Pos)           ///< Inactive
+#define TIM_CCMR1_OC1M_TOGGLE           (0x03U << TIM_CCMR1_OC1M_Pos)           ///< Toggle
+#define TIM_CCMR1_OC1M_FORCEINACTIVE    (0x04U << TIM_CCMR1_OC1M_Pos)           ///< Forceinactive
+#define TIM_CCMR1_OC1M_FORCEACTIVE      (0x05U << TIM_CCMR1_OC1M_Pos)           ///< Forceactive
+#define TIM_CCMR1_OC1M_PWM1             (0x06U << TIM_CCMR1_OC1M_Pos)           ///< PWM1
+#define TIM_CCMR1_OC1M_PWM2             (0x07U << TIM_CCMR1_OC1M_Pos)           ///< PWM2
+
+#define TIM_CCMR1_OC1CEN_Pos            (7)
+#define TIM_CCMR1_OC1CEN                (0x01U << TIM_CCMR1_OC1CEN_Pos)         ///< Output Compare 1Clear Enable
+#define TIM_CCMR1_CC2S_Pos              (8)
+#define TIM_CCMR1_CC2S                  (0x03U << TIM_CCMR1_CC2S_Pos)           ///< CC2S[1:0] bits (Capture/Compare 2 Selection)
+#define TIM_CCMR1_CC2S_OC               (0x00U << TIM_CCMR1_CC2S_Pos)           ///< Channel is configured as output
+#define TIM_CCMR1_CC2S_DIRECTTI         (0x01U << TIM_CCMR1_CC2S_Pos)           ///< Channel is configured as input, IC2 is mapped on TI2
+#define TIM_CCMR1_CC2S_INDIRECTTI       (0x02U << TIM_CCMR1_CC2S_Pos)           ///< Channel is configured as input, IC2 is mapped on TI1
+#define TIM_CCMR1_CC2S_TRC              (0x03U << TIM_CCMR1_CC2S_Pos)           ///< Channel is configured as input, IC2 is mapped on TRC
+#define TIM_CCMR1_OC2FEN_Pos            (10)
+#define TIM_CCMR1_OC2FEN                (0x01U << TIM_CCMR1_OC2FEN_Pos)         ///< Output Compare 2 Fast enable
+#define TIM_CCMR1_OC2PEN_Pos            (11)
+#define TIM_CCMR1_OC2PEN                (0x01U << TIM_CCMR1_OC2PEN_Pos)         ///< Output Compare 2 Preload enable
+#define TIM_CCMR1_OC2M_Pos              (12)
+#define TIM_CCMR1_OC2M                  (0x07U << TIM_CCMR1_OC2M_Pos)           ///< OC2M[2:0] bits (Output Compare 2 Mode)
+#define TIM_CCMR1_OC2M_TIMING           (0x00U << TIM_CCMR1_OC2M_Pos)           ///< Timing
+#define TIM_CCMR1_OC2M_ACTIVE           (0x01U << TIM_CCMR1_OC2M_Pos)           ///< Active
+#define TIM_CCMR1_OC2M_INACTIVE         (0x02U << TIM_CCMR1_OC2M_Pos)           ///< Inactive
+#define TIM_CCMR1_OC2M_TOGGLE           (0x03U << TIM_CCMR1_OC2M_Pos)           ///< Toggle
+#define TIM_CCMR1_OC2M_FORCEINACTIVE    (0x04U << TIM_CCMR1_OC2M_Pos)           ///< Forceinactive
+#define TIM_CCMR1_OC2M_FORCEACTIVE      (0x05U << TIM_CCMR1_OC2M_Pos)           ///< Forceactive
+#define TIM_CCMR1_OC2M_PWM1             (0x06U << TIM_CCMR1_OC2M_Pos)           ///< PWM1
+#define TIM_CCMR1_OC2M_PWM2             (0x07U << TIM_CCMR1_OC2M_Pos)           ///< PWM2
+#define TIM_CCMR1_OC2CEN_Pos            (15)
+#define TIM_CCMR1_OC2CEN                (0x01U << TIM_CCMR1_OC2CEN_Pos)         ///< Output Compare 2 Clear Enable
+
+#define TIM_CCMR1_IC1PSC_Pos            (2)
+#define TIM_CCMR1_IC1PSC                (0x03U << TIM_CCMR1_IC1PSC_Pos)         ///< IC1PSC[1:0] bits (Input Capture 1 Prescaler)
+#define TIM_CCMR1_IC1PSC_DIV1           (0x00U << TIM_CCMR1_IC1PSC_Pos)         ///< No Prescaler
+#define TIM_CCMR1_IC1PSC_DIV2           (0x01U << TIM_CCMR1_IC1PSC_Pos)         ///< Capture is done once every 2 events
+#define TIM_CCMR1_IC1PSC_DIV4           (0x02U << TIM_CCMR1_IC1PSC_Pos)         ///< Capture is done once every 4 events
+#define TIM_CCMR1_IC1PSC_DIV8           (0x03U << TIM_CCMR1_IC1PSC_Pos)         ///< Capture is done once every 8 events
+#define TIM_CCMR1_IC1F_Pos              (4)
+#define TIM_CCMR1_IC1F                  (0x0FU << TIM_CCMR1_IC1F_Pos)           ///< IC1F[3:0] bits (Input Capture 1 Filter)
+#define TIM_CCMR1_IC1F_0                (0x01U << TIM_CCMR1_IC1F_Pos)           ///< Bit 0
+#define TIM_CCMR1_IC1F_1                (0x02U << TIM_CCMR1_IC1F_Pos)           ///< Bit 1
+#define TIM_CCMR1_IC1F_2                (0x04U << TIM_CCMR1_IC1F_Pos)           ///< Bit 2
+#define TIM_CCMR1_IC1F_3                (0x08U << TIM_CCMR1_IC1F_Pos)           ///< Bit 3
+
+#define TIM_CCMR1_IC2PSC_Pos            (10)
+#define TIM_CCMR1_IC2PSC                (0x03U << TIM_CCMR1_IC2PSC_Pos)         ///< IC2PSC[1:0] bits (Input Capture 2 Prescaler)
+#define TIM_CCMR1_IC2PSC_DIV1           (0x00U << TIM_CCMR1_IC2PSC_Pos)         ///< No Prescaler
+#define TIM_CCMR1_IC2PSC_DIV2           (0x01U << TIM_CCMR1_IC2PSC_Pos)         ///< Capture is done once every 2 events
+#define TIM_CCMR1_IC2PSC_DIV4           (0x02U << TIM_CCMR1_IC2PSC_Pos)         ///< Capture is done once every 4 events
+#define TIM_CCMR1_IC2PSC_DIV8           (0x03U << TIM_CCMR1_IC2PSC_Pos)         ///< Capture is done once every 8 events
+#define TIM_CCMR1_IC2F_Pos              (12)
+#define TIM_CCMR1_IC2F                  (0x0FU << TIM_CCMR1_IC2F_Pos)           ///< IC2F[3:0] bits (Input Capture 2 Filter)
+#define TIM_CCMR1_IC2F_0                (0x01U << TIM_CCMR1_IC2F_Pos)           ///< Bit 0
+#define TIM_CCMR1_IC2F_1                (0x02U << TIM_CCMR1_IC2F_Pos)           ///< Bit 1
+#define TIM_CCMR1_IC2F_2                (0x04U << TIM_CCMR1_IC2F_Pos)           ///< Bit 2
+#define TIM_CCMR1_IC2F_3                (0x08U << TIM_CCMR1_IC2F_Pos)           ///< Bit 3
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCMR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCMR2_CC3S_Pos              (0)
+#define TIM_CCMR2_CC3S                  (0x03U << TIM_CCMR2_CC3S_Pos)           ///< CC3S[1:0] bits (Capture/Compare 3 Selection)
+#define TIM_CCMR2_CC3S_OC               (0x00U << TIM_CCMR2_CC3S_Pos)           ///< Channel is configured as output
+#define TIM_CCMR2_CC3S_DIRECTTI         (0x01U << TIM_CCMR2_CC3S_Pos)           ///< Channel is configured as input, IC3 is mapped on TI3
+#define TIM_CCMR2_CC3S_INDIRECTTI       (0x02U << TIM_CCMR2_CC3S_Pos)           ///< Channel is configured as input, IC3 is mapped on TI4
+#define TIM_CCMR2_CC3S_TRC              (0x03U << TIM_CCMR2_CC3S_Pos)           ///< Channel is configured as input, IC3 is mapped on TRC
+#define TIM_CCMR2_OC3FEN_Pos            (2)
+#define TIM_CCMR2_OC3FEN                (0x01U << TIM_CCMR2_OC3FEN_Pos)         ///< Output Compare 3 Fast enable
+#define TIM_CCMR2_IC3PSC_Pos            (2)
+#define TIM_CCMR2_IC3PSC                (0x03U << TIM_CCMR2_IC3PSC_Pos)         ///< IC3PSC[1:0] bits (Input Capture 3 Prescaler)
+#define TIM_CCMR2_IC3PSC_DIV1           (0x00U << TIM_CCMR2_IC3PSC_Pos)         ///< No Prescaler
+#define TIM_CCMR2_IC3PSC_DIV2           (0x01U << TIM_CCMR2_IC3PSC_Pos)         ///< Capture is done once every 2 events
+#define TIM_CCMR2_IC3PSC_DIV4           (0x02U << TIM_CCMR2_IC3PSC_Pos)         ///< Capture is done once every 4 events
+#define TIM_CCMR2_IC3PSC_DIV8           (0x03U << TIM_CCMR2_IC3PSC_Pos)         ///< Capture is done once every 8 events
+#define TIM_CCMR2_OC3PEN_Pos            (3)
+#define TIM_CCMR2_OC3PEN                (0x01U << TIM_CCMR2_OC3PEN_Pos)         ///< Output Compare 3 Preload enable
+#define TIM_CCMR2_OC3M_Pos              (4)
+#define TIM_CCMR2_OC3M                  (0x07U << TIM_CCMR2_OC3M_Pos)           ///< OC3M[2:0] bits (Output Compare 3 Mode)
+#define TIM_CCMR2_OC3M_TIMING           (0x00U << TIM_CCMR2_OC3M_Pos)           ///< Timing
+#define TIM_CCMR2_OC3M_ACTIVE           (0x01U << TIM_CCMR2_OC3M_Pos)           ///< Active
+#define TIM_CCMR2_OC3M_INACTIVE         (0x02U << TIM_CCMR2_OC3M_Pos)           ///< Inactive
+#define TIM_CCMR2_OC3M_TOGGLE           (0x03U << TIM_CCMR2_OC3M_Pos)           ///< Toggle
+#define TIM_CCMR2_OC3M_FORCEINACTIVE    (0x04U << TIM_CCMR2_OC3M_Pos)           ///< Forceinactive
+#define TIM_CCMR2_OC3M_FORCEACTIVE      (0x05U << TIM_CCMR2_OC3M_Pos)           ///< Forceactive
+#define TIM_CCMR2_OC3M_PWM1             (0x06U << TIM_CCMR2_OC3M_Pos)           ///< PWM1
+#define TIM_CCMR2_OC3M_PWM2             (0x07U << TIM_CCMR2_OC3M_Pos)           ///< PWM2
+#define TIM_CCMR2_IC3F_Pos              (4)
+#define TIM_CCMR2_IC3F                  (0x0FU << TIM_CCMR2_IC3F_Pos)           ///< IC3F[3:0] bits (Input Capture 3 Filter)
+#define TIM_CCMR2_IC3F_0                (0x01U << TIM_CCMR2_IC3F_Pos)           ///< Bit 0
+#define TIM_CCMR2_IC3F_1                (0x02U << TIM_CCMR2_IC3F_Pos)           ///< Bit 1
+#define TIM_CCMR2_IC3F_2                (0x04U << TIM_CCMR2_IC3F_Pos)           ///< Bit 2
+#define TIM_CCMR2_IC3F_3                (0x08U << TIM_CCMR2_IC3F_Pos)           ///< Bit 3
+#define TIM_CCMR2_OC3CEN_Pos            (7)
+#define TIM_CCMR2_OC3CEN                (0x01U << TIM_CCMR2_OC3CEN_Pos)         ///< Output Compare 3 Clear Enable
+#define TIM_CCMR2_CC4S_Pos              (8)
+#define TIM_CCMR2_CC4S                  (0x03U << TIM_CCMR2_CC4S_Pos)           ///< CC4S[1:0] bits (Capture/Compare 4 Selection)
+#define TIM_CCMR2_CC4S_OC               (0x00U << TIM_CCMR2_CC4S_Pos)           ///< Channel is configured as output
+#define TIM_CCMR2_CC4S_DIRECTTI         (0x01U << TIM_CCMR2_CC4S_Pos)           ///< Channel is configured as input, IC4 is mapped on TI4
+#define TIM_CCMR2_CC4S_INDIRECTTI       (0x02U << TIM_CCMR2_CC4S_Pos)           ///< Channel is configured as input, IC4 is mapped on TI3
+#define TIM_CCMR2_CC4S_TRC              (0x03U << TIM_CCMR2_CC4S_Pos)           ///< Channel is configured as input, IC4 is mapped on TRC
+#define TIM_CCMR2_OC4FEN_Pos            (10)
+#define TIM_CCMR2_OC4FEN                (0x01U << TIM_CCMR2_OC4FEN_Pos)         ///< Output Compare 4 Fast enable
+#define TIM_CCMR2_OC4PEN_Pos            (11)
+#define TIM_CCMR2_OC4PEN                (0x01U << TIM_CCMR2_OC4PEN_Pos)         ///< Output Compare 4 Preload enable
+#define TIM_CCMR2_OC4M_Pos              (12)
+#define TIM_CCMR2_OC4M                  (0x07U << TIM_CCMR2_OC4M_Pos)           ///< OC4M[2:0] bits (Output Compare 4 Mode)
+#define TIM_CCMR2_OC4M_TIMING           (0x00U << TIM_CCMR2_OC4M_Pos)           ///< Timing
+#define TIM_CCMR2_OC4M_ACTIVE           (0x01U << TIM_CCMR2_OC4M_Pos)           ///< Active
+#define TIM_CCMR2_OC4M_INACTIVE         (0x02U << TIM_CCMR2_OC4M_Pos)           ///< Inactive
+#define TIM_CCMR2_OC4M_TOGGLE           (0x03U << TIM_CCMR2_OC4M_Pos)           ///< Toggle
+#define TIM_CCMR2_OC4M_FORCEINACTIVE    (0x04U << TIM_CCMR2_OC4M_Pos)           ///< Forceinactive
+#define TIM_CCMR2_OC4M_FORCEACTIVE      (0x05U << TIM_CCMR2_OC4M_Pos)           ///< Forceactive
+#define TIM_CCMR2_OC4M_PWM1             (0x06U << TIM_CCMR2_OC4M_Pos)           ///< PWM1
+#define TIM_CCMR2_OC4M_PWM2             (0x07U << TIM_CCMR2_OC4M_Pos)           ///< PWM2
+#define TIM_CCMR2_OC4CEN_Pos            (15)
+#define TIM_CCMR2_OC4CEN                (0x01U << TIM_CCMR2_OC4CEN_Pos)         ///< Output Compare 4 Clear Enable
+#define TIM_CCMR2_IC4PSC_Pos            (10)
+#define TIM_CCMR2_IC4PSC                (0x03U << TIM_CCMR2_IC4PSC_Pos)         ///< IC4PSC[1:0] bits (Input Capture 4 Prescaler)
+#define TIM_CCMR2_IC4PSC_DIV1           (0x00U << TIM_CCMR2_IC4PSC_Pos)         ///< No Prescaler
+#define TIM_CCMR2_IC4PSC_DIV2           (0x01U << TIM_CCMR2_IC4PSC_Pos)         ///< Capture is done once every 2 events
+#define TIM_CCMR2_IC4PSC_DIV4           (0x02U << TIM_CCMR2_IC4PSC_Pos)         ///< Capture is done once every 4 events
+#define TIM_CCMR2_IC4PSC_DIV8           (0x03U << TIM_CCMR2_IC4PSC_Pos)         ///< Capture is done once every 8 events
+#define TIM_CCMR2_IC4F_Pos              (12)
+#define TIM_CCMR2_IC4F                  (0x0FU << TIM_CCMR2_IC4F_Pos)           ///< IC4F[3:0] bits (Input Capture 4 Filter)
+#define TIM_CCMR2_IC4F_0                (0x01U << TIM_CCMR2_IC4F_Pos)           ///< Bit 0
+#define TIM_CCMR2_IC4F_1                (0x02U << TIM_CCMR2_IC4F_Pos)           ///< Bit 1
+#define TIM_CCMR2_IC4F_2                (0x04U << TIM_CCMR2_IC4F_Pos)           ///< Bit 2
+#define TIM_CCMR2_IC4F_3                (0x08U << TIM_CCMR2_IC4F_Pos)           ///< Bit 3
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCER_CC1EN_Pos              (0)
+#define TIM_CCER_CC1EN                  (0x01U << TIM_CCER_CC1EN_Pos)           ///< Capture/Compare 1 output enable
+#define TIM_CCER_CC1P_Pos               (1)
+#define TIM_CCER_CC1P                   (0x01U << TIM_CCER_CC1P_Pos)            ///< Capture/Compare 1 output Polarity
+#define TIM_CCER_CC1NEN_Pos             (2)
+#define TIM_CCER_CC1NEN                 (0x01U << TIM_CCER_CC1NEN_Pos)          ///< Capture/Compare 1 Complementary output enable
+#define TIM_CCER_CC1NP_Pos              (3)
+#define TIM_CCER_CC1NP                  (0x01U << TIM_CCER_CC1NP_Pos)           ///< Capture/Compare 1 Complementary output Polarity
+#define TIM_CCER_CC2EN_Pos              (4)
+#define TIM_CCER_CC2EN                  (0x01U << TIM_CCER_CC2EN_Pos)           ///< Capture/Compare 2 output enable
+#define TIM_CCER_CC2P_Pos               (5)
+#define TIM_CCER_CC2P                   (0x01U << TIM_CCER_CC2P_Pos)            ///< Capture/Compare 2 output Polarity
+#define TIM_CCER_CC2NEN_Pos             (6)
+#define TIM_CCER_CC2NEN                 (0x01U << TIM_CCER_CC2NEN_Pos)          ///< Capture/Compare 2 Complementary output enable
+#define TIM_CCER_CC2NP_Pos              (7)
+#define TIM_CCER_CC2NP                  (0x01U << TIM_CCER_CC2NP_Pos)           ///< Capture/Compare 2 Complementary output Polarity
+#define TIM_CCER_CC3EN_Pos              (8)
+#define TIM_CCER_CC3EN                  (0x01U << TIM_CCER_CC3EN_Pos)           ///< Capture/Compare 3 output enable
+#define TIM_CCER_CC3P_Pos               (9)
+#define TIM_CCER_CC3P                   (0x01U << TIM_CCER_CC3P_Pos)            ///< Capture/Compare 3 output Polarity
+#define TIM_CCER_CC3NEN_Pos             (10)
+#define TIM_CCER_CC3NEN                 (0x01U << TIM_CCER_CC3NEN_Pos)          ///< Capture/Compare 3 Complementary output enable
+#define TIM_CCER_CC3NP_Pos              (11)
+#define TIM_CCER_CC3NP                  (0x01U << TIM_CCER_CC3NP_Pos)           ///< Capture/Compare 3 Complementary output Polarity
+#define TIM_CCER_CC4EN_Pos              (12)
+#define TIM_CCER_CC4EN                  (0x01U << TIM_CCER_CC4EN_Pos)           ///< Capture/Compare 4 output enable
+#define TIM_CCER_CC4P_Pos               (13)
+#define TIM_CCER_CC4P                   (0x01U << TIM_CCER_CC4P_Pos)            ///< Capture/Compare 4 output Polarity
+#define TIM_CCER_CC4NP_Pos              (15)
+#define TIM_CCER_CC4NP                  (0x01U << TIM_CCER_CC4NP_Pos)           ///< Capture/Compare 4 complementary output polarity
+
+#define TIM_CCER_CC5EN_Pos              (16)
+#define TIM_CCER_CC5EN                  (0x01U << TIM_CCER_CC5EN_Pos)           ///< Capture/Compare 5 output enable
+#define TIM_CCER_CC5P_Pos               (17)
+#define TIM_CCER_CC5P                   (0x01U << TIM_CCER_CC5P_Pos)            ///< Capture/Compare 5 output Polarity
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CNT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CNT_CNT                     (0xFFFFU)                               ///< Counter Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_PSC Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_PSC_PSC                     (0xFFFFU)                               ///< Prescaler Value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_ARR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_ARR_ARR                     (0xFFFFU)                               ///< actual auto-reload Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_RCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_RCR_REP                     (0xFFU)                                 ///< Repetition Counter Value
+
+#define TIM_RCR_REP_CNT_Pos             (8)
+#define TIM_RCR_REP_CNT                 (0xFFU << TIM_RCR_REP_CNT_Pos)          ///< Repetition counter value of real-time writing
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR1 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR1_CCR1                  (0xFFFFU)                               ///< Capture/Compare 1 Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR2 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR2_CCR2                  (0xFFFFU)                               ///< Capture/Compare 2 Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR3 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR3_CCR3                  (0xFFFFU)                               ///< Capture/Compare 3 Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR4 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR4_CCR4                  (0xFFFFU)                               ///< Capture/Compare 4 Value
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_BDTR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_BDTR_DTG_Pos                (0)
+#define TIM_BDTR_DTG                    (0xFFU << TIM_BDTR_DTG_Pos)             ///< DTG[0:7] bits (Dead-Time Generator set-up)
+#define TIM_BDTR_DTG_0                  (0x01U << TIM_BDTR_DTG_Pos)             ///< Bit 0
+#define TIM_BDTR_DTG_1                  (0x02U << TIM_BDTR_DTG_Pos)             ///< Bit 1
+#define TIM_BDTR_DTG_2                  (0x04U << TIM_BDTR_DTG_Pos)             ///< Bit 2
+#define TIM_BDTR_DTG_3                  (0x08U << TIM_BDTR_DTG_Pos)             ///< Bit 3
+#define TIM_BDTR_DTG_4                  (0x10U << TIM_BDTR_DTG_Pos)             ///< Bit 4
+#define TIM_BDTR_DTG_5                  (0x20U << TIM_BDTR_DTG_Pos)             ///< Bit 5
+#define TIM_BDTR_DTG_6                  (0x40U << TIM_BDTR_DTG_Pos)             ///< Bit 6
+#define TIM_BDTR_DTG_7                  (0x80U << TIM_BDTR_DTG_Pos)             ///< Bit 7
+#define TIM_BDTR_LOCK_Pos               (8)
+#define TIM_BDTR_LOCK                   (0x03U << TIM_BDTR_LOCK_Pos)            ///< LOCK[1:0] bits (Lock Configuration)
+#define TIM_BDTR_LOCK_OFF               (0x00U << TIM_BDTR_LOCK_Pos)            ///< Lock Off
+#define TIM_BDTR_LOCK_1                 (0x01U << TIM_BDTR_LOCK_Pos)            ///< Lock Level 1
+#define TIM_BDTR_LOCK_2                 (0x02U << TIM_BDTR_LOCK_Pos)            ///< Lock Level 2
+#define TIM_BDTR_LOCK_3                 (0x03U << TIM_BDTR_LOCK_Pos)            ///< Lock Level 3
+#define TIM_BDTR_OSSI_Pos               (10)
+#define TIM_BDTR_OSSI                   (0x01U << TIM_BDTR_OSSI_Pos)            ///< Off-State Selection for Idle mode
+#define TIM_BDTR_OSSR_Pos               (11)
+#define TIM_BDTR_OSSR                   (0x01U << TIM_BDTR_OSSR_Pos)            ///< Off-State Selection for Run mode
+#define TIM_BDTR_BKEN_Pos               (12)
+#define TIM_BDTR_BKEN                   (0x01U << TIM_BDTR_BKEN_Pos)            ///< Break enable
+#define TIM_BDTR_BKP_Pos                (13)
+#define TIM_BDTR_BKP                    (0x01U << TIM_BDTR_BKP_Pos)             ///< Break Polarity
+#define TIM_BDTR_AOEN_Pos               (14)
+#define TIM_BDTR_AOEN                   (0x01U << TIM_BDTR_AOEN_Pos)            ///< Automatic Output enable
+#define TIM_BDTR_MOEN_Pos               (15)
+#define TIM_BDTR_MOEN                   (0x01U << TIM_BDTR_MOEN_Pos)            ///< Main Output enable
+
+#define TIM_BDTR_DOEN_Pos               (16)
+#define TIM_BDTR_DOEN                   (0x01U << TIM_BDTR_DOEN_Pos)            ///< Direct Output enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_DCR_DBA_Pos                 (0)
+#define TIM_DCR_DBA                     (0x1FU << TIM_DCR_DBA_Pos)              ///< DBA[4:0] bits (DMA Base Address)
+#define TIM_DCR_DBA_0                   (0x01U << TIM_DCR_DBA_Pos)              ///< Bit 0
+#define TIM_DCR_DBA_1                   (0x02U << TIM_DCR_DBA_Pos)              ///< Bit 1
+#define TIM_DCR_DBA_2                   (0x04U << TIM_DCR_DBA_Pos)              ///< Bit 2
+#define TIM_DCR_DBA_3                   (0x08U << TIM_DCR_DBA_Pos)              ///< Bit 3
+#define TIM_DCR_DBA_4                   (0x10U << TIM_DCR_DBA_Pos)              ///< Bit 4
+#define TIM_DCR_DBL_Pos                 (8)
+#define TIM_DCR_DBL                     (0x1FU << TIM_DCR_DBL_Pos)              ///< DBL[4:0] bits (DMA Burst Length)
+#define TIM_DCR_DBL_0                   (0x01U << TIM_DCR_DBL_Pos)              ///< Bit 0
+#define TIM_DCR_DBL_1                   (0x02U << TIM_DCR_DBL_Pos)              ///< Bit 1
+#define TIM_DCR_DBL_2                   (0x04U << TIM_DCR_DBL_Pos)              ///< Bit 2
+#define TIM_DCR_DBL_3                   (0x08U << TIM_DCR_DBL_Pos)              ///< Bit 3
+#define TIM_DCR_DBL_4                   (0x10U << TIM_DCR_DBL_Pos)              ///< Bit 4
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_DMAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_DMAR_DMAB                   (0xFFFFU)                               ///< DMA register for burst accesses
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCMR3 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCMR3_OC5FEN_Pos        (2)
+#define TIM_CCMR3_OC5FEN            (0x01U << TIM_CCMR3_OC5FEN_Pos)         ///< Output Compare 5 Fast enable
+#define TIM_CCMR3_OC5PEN_Pos        (3)
+#define TIM_CCMR3_OC5PEN            (0x01U << TIM_CCMR3_OC5PEN_Pos)         ///< Output Compare 5 Preload enable
+#define TIM_CCMR3_OC5M_Pos          (4)
+#define TIM_CCMR3_OC5M              (0x07U << TIM_CCMR3_OC5M_Pos)           ///< OC5M[2:0] bits (Output Compare 5 Mode)
+
+#define TIM_CCMR3_OC5CEN_Pos        (7)
+#define TIM_CCMR3_OC5CEN            (0x01U << TIM_CCMR3_OC5CEN_Pos)         ///< Output Compare 5 Clear Enable
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR5 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR5_CCR5               (0xFFFF)                                ///< Capture/Compare 5 Value
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_PDER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_PDER_CCDREPE_Pos        (0)
+#define TIM_PDER_CCDREPE            (0x01U << TIM_PDER_CCDREPE_Pos)         ///< DMA request flow enable
+#define TIM_PDER_CCR1SHIFTEN_Pos    (1)
+#define TIM_PDER_CCR1SHIFTEN        (0x01U << TIM_PDER_CCR1SHIFTEN_Pos)     ///< CCR1 pwm shift enable
+#define TIM_PDER_CCR2SHIFTEN_Pos    (2)
+#define TIM_PDER_CCR2SHIFTEN        (0x01U << TIM_PDER_CCR2SHIFTEN_Pos)     ///< CCR2 pwm shift enable
+#define TIM_PDER_CCR3SHIFTEN_Pos    (3)
+#define TIM_PDER_CCR3SHIFTEN        (0x01U << TIM_PDER_CCR3SHIFTEN_Pos)     ///< CCR3 pwm shift enable
+#define TIM_PDER_CCR4SHIFTEN_Pos    (4)
+#define TIM_PDER_CCR4SHIFTEN        (0x01U << TIM_PDER_CCR4SHIFTEN_Pos)     ///< CCR4 pwm shift enable
+#define TIM_PDER_CCR5SHIFTEN_Pos    (5)
+#define TIM_PDER_CCR5SHIFTEN        (0x01U << TIM_PDER_CCR5SHIFTEN_Pos)     ///< CCR5 pwm shift enable
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR1FALL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR1FALL_CCR1FALL       (0xFFFFU)                               ///< Capture/compare value for ch1 when counting down in PWM center-aligned mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR2FALL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR2FALL_CCR2FALL       (0xFFFFU)                               ///< Capture/compare value for ch2 when counting down in PWM center-aligned mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR3FALL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR3FALL_CCR3FALL       (0xFFFFU)                               ///< Capture/compare value for ch3 when counting down in PWM center-aligned mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR4FALL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR4FALL_CCR4FALL       (0xFFFFU)                               ///< Capture/compare value for ch4 when counting down in PWM center-aligned mode
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief TIM_CCR5FALL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define TIM_CCR5FALL_CCR5FALL       (0xFFFFU)                               ///< Capture/compare value for ch5 when counting down in PWM center-aligned mode
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h
new file mode 100644
index 000000000..069ff2cf9
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h
@@ -0,0 +1,362 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_uart.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_UART_H
+#define __REG_UART_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART1_BASE                      (APB2PERIPH_BASE + 0x3800)              ///< Base Address: 0x40013800
+#define UART2_BASE                      (APB1PERIPH_BASE + 0x4400)              ///< Base Address: 0x40004400
+#define UART3_BASE                      (APB1PERIPH_BASE + 0x4800)              ///< Base Address: 0x40004800
+#define UART4_BASE                      (APB1PERIPH_BASE + 0x4C00)              ///< Base Address: 0x40004C00
+#define UART5_BASE                      (APB1PERIPH_BASE + 0x5000)              ///< Base Address: 0x40005000
+#define UART6_BASE                      (APB2PERIPH_BASE + 0x3C00)              ///< Base Address: 0x40013C00
+#define UART7_BASE                      (APB1PERIPH_BASE + 0x7800)              ///< Base Address: 0x40007800
+#define UART8_BASE                      (APB1PERIPH_BASE + 0x7C00)              ///< Base Address: 0x40007C00
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+typedef struct {
+    __IO u32 TDR;                                                               ///< Transmit Data Register,                        offset: 0x00
+    __IO u32 RDR;                                                               ///< Receive Data Register,                         offset: 0x04
+    __IO u32 CSR;                                                               ///< Current Status Register,                       offset: 0x08
+    __IO u32 ISR;                                                               ///< Interrupt Status Register,                     offset: 0x0C
+    __IO u32 IER;                                                               ///< Interrupt Enable Register,                     offset: 0x10
+    __IO u32 ICR;                                                               ///< Interrupt Clear Register,                      offset: 0x14
+    __IO u32 GCR;                                                               ///< Global Control Register,                       offset: 0x18
+    __IO u32 CCR;                                                               ///< Config Control Register,                       offset: 0x1C
+    __IO u32 BRR;                                                               ///< Baud Rate Register,                            offset: 0x20
+    __IO u32 FRA;                                                               ///< Fraction Register,                             offset: 0x24
+
+    __IO u32 RXAR;                                                              ///< Receive Address Register,                      offset: 0x28
+    __IO u32 RXMR;                                                              ///< Receive Address Mask Register,                 offset: 0x2C
+    __IO u32 SCR;                                                               ///< Smart Card Register,                           offset: 0x30
+
+    __IO u32 IDLR;                                                              ///< Data length register                          offset: 0x34
+    __IO u32 ABRCR;                                                             ///< automatic Baud rate control delivery          offset: 0x38
+    __IO u32 IRDA;                                                              ///< Infrared function control register,           offset: 0x3C
+} UART_TypeDef;
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART1                           ((UART_TypeDef*) UART1_BASE)
+#define UART2                           ((UART_TypeDef*) UART2_BASE)
+
+#define UART3                           ((UART_TypeDef*) UART3_BASE)
+#define UART4                           ((UART_TypeDef*) UART4_BASE)
+#define UART5                           ((UART_TypeDef*) UART5_BASE)
+#define UART6                           ((UART_TypeDef*) UART6_BASE)
+#define UART7                           ((UART_TypeDef*) UART7_BASE)
+#define UART8                           ((UART_TypeDef*) UART8_BASE)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_TDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_TDR_DATA_Pos               (0)
+#define UART_TDR_DATA                   (0xFFU << UART_TDR_DATA_Pos)            ///< Transmit data register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_RDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_RDR_DATA_Pos               (0)
+#define UART_RDR_DATA                   (0xFFU << UART_RDR_DATA_Pos)            ///< Receive data register
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_CSR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_CSR_TXC_Pos                (0)
+#define UART_CSR_TXC                    (0x01U << UART_CSR_TXC_Pos)             ///< Transmit complete flag bit
+#define UART_CSR_RXAVL_Pos              (1)
+#define UART_CSR_RXAVL                  (0x01U << UART_CSR_RXAVL_Pos)           ///< Receive valid data flag bit
+#define UART_CSR_TXFULL_Pos             (2)
+#define UART_CSR_TXFULL                 (0x01U << UART_CSR_TXFULL_Pos)          ///< Transmit buffer full flag bit
+#define UART_CSR_TXEPT_Pos              (3)
+#define UART_CSR_TXEPT                  (0x01U << UART_CSR_TXEPT_Pos)           ///< Transmit buffer empty flag bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_ISR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_ISR_TX_Pos                 (0)
+#define UART_ISR_TX                     (0x01U << UART_ISR_TX_Pos)              ///< Transmit buffer empty interrupt flag bit
+#define UART_ISR_RX_Pos                 (1)
+#define UART_ISR_RX                     (0x01U << UART_ISR_RX_Pos)              ///< Receive valid data interrupt flag bit
+
+#define UART_ISR_TXC_Pos                (2)
+#define UART_ISR_TXC                    (0x01U << UART_ISR_TXC_Pos)             ///< Transmit complete interrupt flag bit
+
+#define UART_ISR_RXOERR_Pos             (3)
+#define UART_ISR_RXOERR                 (0x01U << UART_ISR_RXOERR_Pos)          ///< Receive overflow error interrupt flag bit
+#define UART_ISR_RXPERR_Pos             (4)
+#define UART_ISR_RXPERR                 (0x01U << UART_ISR_RXPERR_Pos)          ///< Parity error interrupt flag bit
+#define UART_ISR_RXFERR_Pos             (5)
+#define UART_ISR_RXFERR                 (0x01U << UART_ISR_RXFERR_Pos)          ///< Frame error interrupt flag bit
+#define UART_ISR_RXBRK_Pos              (6)
+#define UART_ISR_RXBRK                  (0x01U << UART_ISR_RXBRK_Pos)           ///< Receive frame break interrupt flag bit
+
+#define UART_ISR_TXBRK_Pos              (7)
+#define UART_ISR_TXBRK                  (0x01U << UART_ISR_TXBRK_Pos)           ///< Transmit Break Frame Interrupt Flag Bit
+#define UART_ISR_RXB8_Pos               (8)
+#define UART_ISR_RXB8                   (0x01U << UART_ISR_RXB8_Pos)            ///< Receive Bit 8 Interrupt Flag Bit
+
+#define UART_ISR_RXIDLE_Pos             (9)
+#define UART_ISR_RXIDLE                 (0x01U << UART_ISR_RXIDLE_Pos)          ///< Receive Bit 8 Interrupt clear Bit
+#define UART_ISR_ABREND_INTF_Pos         (10)
+#define UART_ISR_ABREND_INTF             (0x01U << UART_ISR_ABREND_INTF_Pos)          ///< Auto baud rate end interrupt flag bit
+#define UART_ISR_ABRERR_INTF_Pos         (11)
+#define UART_ISR_ABRERR_INTF             (0x01U << UART_ISR_ABRERR_INTF_Pos)          ///< Auto baud rate error interrupt flag bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_IER Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_IER_TX_Pos                 (0)
+#define UART_IER_TX                     (0x01U << UART_IER_TX_Pos)              ///< Transmit buffer empty interrupt enable bit
+#define UART_IER_RX_Pos                 (1)
+#define UART_IER_RX                     (0x01U << UART_IER_RX_Pos)              ///< Receive buffer interrupt enable bit
+
+#define UART_IER_TXC_Pos                (2)
+#define UART_IER_TXC                    (0x01U << UART_IER_TXC_Pos)             ///< Transmit complete interrupt enable bit
+
+#define UART_IER_RXOERR_Pos             (3)
+#define UART_IER_RXOERR                 (0x01U << UART_IER_RXOERR_Pos)          ///< Receive overflow error interrupt enable bit
+#define UART_IER_RXPERR_Pos             (4)
+#define UART_IER_RXPERR                 (0x01U << UART_IER_RXPERR_Pos)          ///< Parity error interrupt enable bit
+#define UART_IER_RXFERR_Pos             (5)
+#define UART_IER_RXFERR                 (0x01U << UART_IER_RXFERR_Pos)          ///< Frame error interrupt enable bit
+#define UART_IER_RXBRK_Pos              (6)
+#define UART_IER_RXBRK                  (0x01U << UART_IER_RXBRK_Pos)           ///< Receive frame break interrupt enable bit
+
+#define UART_IER_TXBRK_Pos              (7)
+#define UART_IER_TXBRK                  (0x01U << UART_IER_TXBRK_Pos)           ///< Transmit Break Frame Interrupt Enable Bit
+#define UART_IER_RXB8_Pos               (8)
+#define UART_IER_RXB8                   (0x01U << UART_IER_RXB8_Pos)            ///< Receive Bit 8 Interrupt Enable Bit
+
+#define UART_IER_RXIDLE_Pos             (9)
+#define UART_IER_RXIDLE                 (0x01U << UART_IER_RXIDLE_Pos)          ///< Receive Bit 8 Interrupt clear Bit
+#define UART_IER_ABREND_IEN_Pos         (10)
+#define UART_IER_ABREND_IEN             (0x01U << UART_IER_ABREND_IEN_Pos)          ///< Auto baud rate end enable bit
+#define UART_IER_ABRERR_IEN_Pos         (11)
+#define UART_IER_ABRERR_IEN             (0x01U << UART_IER_ABRERR_IEN_Pos)          ///< Auto baud rate error enable bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_ICR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define UART_ICR_TX_Pos                 (0)
+#define UART_ICR_TX                     (0x01U << UART_ICR_TX_Pos)              ///< Transmit buffer empty interrupt clear bit
+#define UART_ICR_RX_Pos                 (1)
+#define UART_ICR_RX                     (0x01U << UART_ICR_RX_Pos)              ///< Receive interrupt clear bit
+
+#define UART_ICR_TXC_Pos                (2)
+#define UART_ICR_TXC                    (0x01U << UART_ICR_TXC_Pos)             ///< Transmit complete interrupt clear bit
+
+#define UART_ICR_RXOERR_Pos             (3)
+#define UART_ICR_RXOERR                 (0x01U << UART_ICR_RXOERR_Pos)          ///< Receive overflow error interrupt clear bit
+#define UART_ICR_RXPERR_Pos             (4)
+#define UART_ICR_RXPERR                 (0x01U << UART_ICR_RXPERR_Pos)          ///< Parity error interrupt clear bit
+
+#define UART_ICR_RXFERR_Pos             (5)
+#define UART_ICR_RXFERR                 (0x01U << UART_ICR_RXFERR_Pos)          ///< Frame error interrupt clear bit
+#define UART_ICR_RXBRK_Pos              (6)
+#define UART_ICR_RXBRK                  (0x01U << UART_ICR_RXBRK_Pos)           ///< Receive frame break interrupt clear bit
+
+#define UART_ICR_TXBRK_Pos              (7)
+#define UART_ICR_TXBRK                  (0x01U << UART_ICR_TXBRK_Pos)           ///< Transmit Break Frame Interrupt clear Bit
+#define UART_ICR_RXB8_Pos               (8)
+#define UART_ICR_RXB8                   (0x01U << UART_ICR_RXB8_Pos)            ///< Receive Bit 8 Interrupt clear Bit
+
+#define UART_ICR_RXIDLE_Pos             (9)
+#define UART_ICR_RXIDLE                 (0x01U << UART_ICR_RXIDLE_Pos)          ///< Receive Bit 8 Interrupt clear Bit
+#define UART_ICR_ABRENDCLR_Pos         (10)
+#define UART_ICR_ABRENDCLR             (0x01U << UART_ICR_ABRENDCLR_Pos)          ///< Auto baud rate end clear bit
+#define UART_ICR_ABRERRCLR_Pos         (11)
+#define UART_ICR_ABRERRCLR             (0x01U << UART_ICR_ABRERRCLR_Pos)          ///< Auto baud rate error clear bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_GCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_GCR_UART_Pos               (0)
+#define UART_GCR_UART                   (0x01U << UART_GCR_UART_Pos)            ///< UART mode selection bit
+#define UART_GCR_DMA_Pos                (1)
+#define UART_GCR_DMA                    (0x01U << UART_GCR_DMA_Pos)             ///< DMA mode selection bit
+#define UART_GCR_AUTOFLOW_Pos           (2)
+#define UART_GCR_AUTOFLOW               (0x01U << UART_GCR_AUTOFLOW_Pos)        ///< Automatic flow control enable bit
+#define UART_GCR_RX_Pos                 (3)
+#define UART_GCR_RX                     (0x01U << UART_GCR_RX_Pos)              ///< Enable receive
+#define UART_GCR_TX_Pos                 (4)
+#define UART_GCR_TX                     (0x01U << UART_GCR_TX_Pos)              ///< Enable transmit
+
+#define UART_GCR_SELB8_Pos              (7)
+#define UART_GCR_SELB8                  (0x01U << UART_GCR_SELB8_Pos)           ///< UART mode selection bit
+#define UART_GCR_SWAP_Pos               (8)
+#define UART_GCR_SWAP                   (0x01U << UART_GCR_SWAP_Pos)            ///< DMA mode selection bit
+#define UART_GCR_RXTOG_Pos              (9)
+#define UART_GCR_RXTOG                  (0x01U << UART_GCR_RXTOG_Pos)           ///< Automatic flow control enable bit
+#define UART_GCR_TXTOG_Pos              (10)
+#define UART_GCR_TXTOG                  (0x01U << UART_GCR_TXTOG_Pos)           ///< Enable receive
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_CCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_CCR_PEN_Pos                (0)
+#define UART_CCR_PEN                    (0x01U << UART_CCR_PEN_Pos)             ///< Parity enable bit
+#define UART_CCR_PSEL_Pos               (1)
+#define UART_CCR_PSEL                   (0x01U << UART_CCR_PSEL_Pos)            ///< Parity selection bit
+
+#define UART_CCR_SPB_Pos                (2)
+#define UART_CCR_SPB                    (0x01U << UART_CCR_SPB_Pos)             ///< Stop bit selection
+
+
+
+#define UART_CCR_SPB0_Pos               UART_CCR_SPB_Pos
+#define UART_CCR_SPB0                   UART_CCR_SPB                            ///< Stop bit 0 selection
+
+#define UART_CCR_BRK_Pos                (3)
+#define UART_CCR_BRK                    (0x01U << UART_CCR_BRK_Pos)             ///< UART transmit frame break
+#define UART_CCR_CHAR_Pos               (4)
+#define UART_CCR_CHAR                   (0x03U << UART_CCR_CHAR_Pos)            ///< UART width bit
+#define UART_CCR_CHAR_5b                (0x00U << UART_CCR_CHAR_Pos)            ///< UART Word Length 5b
+#define UART_CCR_CHAR_6b                (0x01U << UART_CCR_CHAR_Pos)            ///< UART Word Length 6b
+#define UART_CCR_CHAR_7b                (0x02U << UART_CCR_CHAR_Pos)            ///< UART Word Length 7b
+#define UART_CCR_CHAR_8b                (0x03U << UART_CCR_CHAR_Pos)            ///< UART Word Length 8b
+
+#define UART_CCR_SPB1_Pos               (6)
+#define UART_CCR_SPB1                   (0x01U << UART_CCR_SPB1_Pos)            ///< Stop bit 1 selection
+#define UART_CCR_B8RXD_Pos              (7)
+#define UART_CCR_B8RXD                  (0x01U << UART_CCR_B8RXD_Pos)           ///< Synchronous frame receive
+#define UART_CCR_B8TXD_Pos              (8)
+#define UART_CCR_B8TXD                  (0x01U << UART_CCR_B8TXD_Pos)           ///< Synchronous frame transmit
+#define UART_CCR_B8POL_Pos              (9)
+#define UART_CCR_B8POL                  (0x01U << UART_CCR_B8POL_Pos)           ///< Synchronous frame polarity control bit
+#define UART_CCR_B8TOG_Pos              (10)
+#define UART_CCR_B8TOG                  (0x01U << UART_CCR_B8TOG_Pos)           ///< Synchronous frame auto toggle bit
+#define UART_CCR_B8EN_Pos               (11)
+#define UART_CCR_B8EN                   (0x01U << UART_CCR_B8EN_Pos)            ///< Synchronous frame enable bit
+#define UART_CCR_RWU_Pos                (12)
+#define UART_CCR_RWU                    (0x01U << UART_CCR_RWU_Pos)             ///< Receive wake up method
+#define UART_CCR_WAKE_Pos               (13)
+#define UART_CCR_WAKE                   (0x01U << UART_CCR_WAKE_Pos)            ///< Wake up method
+
+#define UART_CCR_LIN_Pos            (14)
+#define UART_CCR_LIN                (0x01U << UART_CCR_LIN_Pos)             ///< Wake up method
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_BRR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_BRR_MANTISSA_Pos        (0)
+#define UART_BRR_MANTISSA            (0xFFFFU << UART_BRR_MANTISSA_Pos)      ///< UART DIV MANTISSA
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_FRA Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_BRR_FRACTION_Pos        (0)
+#define UART_BRR_FRACTION            (0x0FU << UART_BRR_FRACTION_Pos)        ///< UART DIV FRACTION
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_RXAR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_RXAR_ADDR_Pos          (0)
+#define UART_RXAR_ADDR              (0xFFU << UART_RXAR_ADDR_Pos)           ///< Synchronous frame match address
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_RXMR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_RXMR_MASK_Pos          (0)
+#define UART_RXMR_MASK              (0xFFU << UART_RXMR_MASK_Pos)           ///< Synchronous frame match address mask
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_SCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_SCR_SCEN_Pos           (0)
+#define UART_SCR_SCEN               (0x01U << UART_SCR_SCEN_Pos)            ///< ISO7816 enable bit
+#define UART_SCR_SCARB_Pos          (1)
+#define UART_SCR_SCARB              (0x01U << UART_SCR_SCARB_Pos)           ///< ISO7816 check auto answer bit
+#define UART_SCR_NACK_Pos           (2)
+#define UART_SCR_NACK               (0x01U << UART_SCR_NACK_Pos)            ///< Master receive frame answer bit
+#define UART_SCR_SCFCNT_Pos         (4)
+#define UART_SCR_SCFCNT             (0xFFU << UART_SCR_SCFCNT_Pos)          ///< ISO7816 protection counter bit
+#define UART_SCR_HDSEL_Pos          (12)
+#define UART_SCR_HDSEL              (0x01U << UART_SCR_HDSEL_Pos)           ///< Single-line half-duplex mode selection bit
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_ABRCR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_ABRCR_ABREN_Pos        (0)
+#define UART_ABRCR_ABREN            (0x01U<<UART_ABRCR_ABREN_Pos)
+#define UART_ABRCR_BITCNT_Pos       (1)
+#define UART_ABRCR_BITCNT           (0x03U<<UART_ABRCR_BITCNT_Pos)
+#define UART_ABRCR_BITCNT_MODE0     (0x00U<<UART_ABRCR_BITCNT_Pos)
+#define UART_ABRCR_BITCNT_MODE1     (0x01U<<UART_ABRCR_BITCNT_Pos)
+#define UART_ABRCR_BITCNT_MODE2     (0x02U<<UART_ABRCR_BITCNT_Pos)
+#define UART_ABRCR_BITCNT_MODE3     (0x03U<<UART_ABRCR_BITCNT_Pos)
+#define UART_ABRCR_FORMER_Pos       (3)
+#define UART_ABRCR_FORMER           (0x01U<<UART_ABRCR_FORMER_Pos)
+#define UART_ABRCR_LATTER_Pos       (4)
+#define UART_ABRCR_LATTER           (0x01U<<UART_ABRCR_LATTER_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief UART_IDLR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define UART_IDLR_IDLR_Pos          (0)
+#define UART_IDLR_IDLR              (0xFFFFU << UART_IDLR_IDLR_Pos)         ///< ISO7816 enable bit
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h
new file mode 100644
index 000000000..9d8c6bf42
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h
@@ -0,0 +1,923 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_usb_otg_fs.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_USB_OTG_FS_H
+#define __REG_USB_OTG_FS_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief USB Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define USB_OTG_FS_BASE                        (AHB2PERIPH_BASE + 0x0000)              ///< Base Address: 0x50000000
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief USB Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+
+typedef struct {
+    __IO u32 PER_ID;                                                             ///< Peripheral ID register                         offset: 0x00
+    __IO u32 ID_COMP;                                                            ///< Peripheral ID complement register              offset: 0x04
+    __IO u32 REV;                                                                ///< Peripheral revision register                   offset: 0x08
+    __IO u32 ADD_INFO;                                                           ///< Peripheral additional info register            offset: 0x0C
+    __IO u32 OTG_ISTAT;                                                          ///< OTG Interrupt Status Register                  offset: 0x10
+    __IO u32 OTG_ICTRL;                                                          ///< OTG Interrupt Control Register                 offset: 0x14
+    __IO u32 OTG_STAT;                                                           ///< OTG Status Register                            offset: 0x18
+    __IO u32 OTG_CTRL;                                                           ///< OTG Control register                           offset: 0x1C
+    __IO u32 RESERVED0[24];                                                      ///< Reserved                                       offset: 0x20
+    __IO u32 INT_STAT;                                                           ///< Interrupt status register                      offset: 0x80
+    __IO u32 INT_ENB;                                                            ///< Interrupt enable register                      offset: 0x84
+    __IO u32 ERR_STAT;                                                           ///< Error interrupt status register                offset: 0x88
+    __IO u32 ERR_ENB;                                                            ///< Error interrupt enable register                offset: 0x8C
+    __IO u32 STAT;                                                               ///< Status register                                offset: 0x90
+    __IO u32 CTL;                                                                ///< Control register                               offset: 0x94
+    __IO u32 ADDR;                                                               ///< Address register                               offset: 0x98
+    __IO u32 BDT_PAGE_01;                                                        ///< BDT page register 1                            offset: 0x9C
+    __IO u32 FRM_NUML;                                                           ///< Frame number register                          offset: 0xA0
+    __IO u32 FRM_NUMH;                                                           ///< Frame number register                          offset: 0xA4
+    __IO u32 TOKEN;                                                              ///< Token register                                 offset: 0xA8
+    __IO u32 SOF_THLD;                                                           ///< SOF threshold register                         offset: 0xAC
+    __IO u32 BDT_PAGE_02;                                                        ///< BDT page register 2                            offset: 0xB0
+    __IO u32 BDT_PAGE_03;                                                        ///< BDT page register 3                            offset: 0xB4
+    __IO u32 RESERVED1;                                                          ///< Reserved                                       offset: 0xB8
+    __IO u32 RESERVED2;                                                          ///< Reserved                                       offset: 0xBC
+    __IO u32 EP_CTL[16];                                                         ///< Endpoint control register                      offset: 0xC0
+} USB_OTG_FS_TypeDef;
+////////////////////////////////////////////////////////////////////////////////
+/// @brief USBD type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define USB_OTG_FS                             ((USB_OTG_FS_TypeDef*) USB_OTG_FS_BASE )
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_PER_ID Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_PER_ID_ID_Pos                    (0)
+#define OTG_FS_PER_ID_ID                        (0x3FU << OTG_FS_PER_ID_ID_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_ID_COMP Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_ID_COMP_NID_Pos                  (0)
+#define OTG_FS_ID_COMP_NID                      (0x3FU << OTG_FS_ID_COMP_NID_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_REV Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_REV_REV_Pos                      (0)
+#define OTG_FS_REV_REV                          (0xFFU << OTG_FS_REV_REV_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_ADD_INFO Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_ADD_INFO_HOST_Pos                (0)
+#define OTG_FS_ADD_INFO_HOST                    (0x01U << OTG_FS_ADD_INFO_HOST_Pos)
+#define OTG_FS_ADD_INFO_IRQ_NUM_Pos             (3)
+#define OTG_FS_ADD_INFO_IRQ_NUM                 (0x1FU << OTG_FS_ADD_INFO_IRQ_NUM_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_OTG_ISTAT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos     (0)
+#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG         (0x01U << OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos)
+#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos     (2)
+#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG         (0x01U << OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos)
+#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos       (3)
+#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG           (0x01U << OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos)
+#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos     (5)
+#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG         (0x01U << OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos)
+#define OTG_FS_OTG_ISTAT_1_MSEC_Pos             (6)
+#define OTG_FS_OTG_ISTAT_1_MSEC                 (0x01U << OTG_FS_OTG_ISTAT_1_MSEC_Pos)
+#define OTG_FS_OTG_ISTAT_ID_CHG_Pos             (7)
+#define OTG_FS_OTG_ISTAT_ID_CHG                 (0x01U << OTG_FS_OTG_ISTAT_ID_CHG_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_OTG_ICTRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos      (0)
+#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN          (0x01U << OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos)
+#define OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos      (2)
+#define OTG_FS_OTG_ICTRL_B_SESS_END_EN          (0x01U << OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos)
+#define OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos        (3)
+#define OTG_FS_OTG_ICTRL_SESS_VLD_EN            (0x01U << OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos)
+#define OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos      (5)
+#define OTG_FS_OTG_ICTRL_LINE_STATE_EN          (0x01U << OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos)
+#define OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos          (6)
+#define OTG_FS_OTG_ICTRL_1_MSEC_EN              (0x01U << OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos)
+#define OTG_FS_OTG_ICTRL_ID_EN_Pos              (7)
+#define OTG_FS_OTG_ICTRL_ID_EN                  (0x01U << OTG_FS_OTG_ICTRL_ID_EN_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_OTG_STAT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_OTG_STAT_A_VBUS_VLD_Pos          (0)
+#define OTG_FS_OTG_STAT_A_VBUS_VLD              (0x01U << OTG_FS_OTG_STAT_A_VBUS_VLD_Pos)
+#define OTG_FS_OTG_STAT_B_SESS_END_Pos          (2)
+#define OTG_FS_OTG_STAT_B_SESS_END              (0x01U << OTG_FS_OTG_STAT_B_SESS_END_Pos)
+#define OTG_FS_OTG_STAT_SESS_VLD_Pos            (3)
+#define OTG_FS_OTG_STAT_SESS_VLD                (0x01U << OTG_FS_OTG_STAT_SESS_VLD_Pos)
+#define OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos   (5)
+#define OTG_FS_OTG_STAT_LINE_STATE_STABLE       (0x01U << OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos)
+#define OTG_FS_OTG_STAT_1_MSEC_Pos              (6)
+#define OTG_FS_OTG_STAT_1_MSEC                  (0x01U << OTG_FS_OTG_STAT_1_MSEC_Pos)
+#define OTG_FS_OTG_STAT_ID_Pos                  (7)
+#define OTG_FS_OTG_STAT_ID                      (0x01U << OTG_FS_OTG_STAT_ID_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_OTG_CTRL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos          (0)
+#define OTG_FS_OTG_CTRL_VBUS_DSCHG              (0x01U << OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos)
+#define OTG_FS_OTG_CTRL_VBUS_CHG_Pos            (1)
+#define OTG_FS_OTG_CTRL_VBUS_CHG                (0x01U << OTG_FS_OTG_CTRL_VBUS_CHG_Pos)
+#define OTG_FS_OTG_CTRL_OTG_EN_Pos              (2)
+#define OTG_FS_OTG_CTRL_OTG_EN                  (0x01U << OTG_FS_OTG_CTRL_OTG_EN_Pos)
+#define OTG_FS_OTG_CTRL_VBUS_ON_Pos             (3)
+#define OTG_FS_OTG_CTRL_VBUS_ON                 (0x01U << OTG_FS_OTG_CTRL_VBUS_ON_Pos)
+#define OTG_FS_OTG_CTRL_DM_LOW_Pos              (4)
+#define OTG_FS_OTG_CTRL_DM_LOW                  (0x01U << OTG_FS_OTG_CTRL_DM_LOW_Pos)
+#define OTG_FS_OTG_CTRL_DP_LOW_Pos              (5)
+#define OTG_FS_OTG_CTRL_DP_LOW                  (0x01U << OTG_FS_OTG_CTRL_DP_LOW_Pos)
+#define OTG_FS_OTG_CTRL_DM_HIGH_Pos             (6)
+#define OTG_FS_OTG_CTRL_DM_HIGH                 (0x01U << OTG_FS_OTG_CTRL_DM_HIGH_Pos)
+#define OTG_FS_OTG_CTRL_DP_HIGH_Pos             (7)
+#define OTG_FS_OTG_CTRL_DP_HIGH                 (0x01U << OTG_FS_OTG_CTRL_DP_HIGH_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_INT_STAT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_INT_STAT_USB_RST_Pos             (0)
+#define OTG_FS_INT_STAT_USB_RST                 (0x01U << OTG_FS_INT_STAT_USB_RST_Pos)
+#define OTG_FS_INT_STAT_ERROR_Pos               (1)
+#define OTG_FS_INT_STAT_ERROR                   (0x01U << OTG_FS_INT_STAT_ERROR_Pos)
+#define OTG_FS_INT_STAT_SOF_TOK_Pos             (2)
+#define OTG_FS_INT_STAT_SOF_TOK                 (0x01U << OTG_FS_INT_STAT_SOF_TOK_Pos)
+#define OTG_FS_INT_STAT_TOK_DNE_Pos             (3)
+#define OTG_FS_INT_STAT_TOK_DNE                 (0x01U << OTG_FS_INT_STAT_TOK_DNE_Pos)
+#define OTG_FS_INT_STAT_SLEEP_Pos               (4)
+#define OTG_FS_INT_STAT_SLEEP                   (0x01U << OTG_FS_INT_STAT_SLEEP_Pos)
+#define OTG_FS_INT_STAT_RESUME_Pos              (5)
+#define OTG_FS_INT_STAT_RESUME                  (0x01U << OTG_FS_INT_STAT_RESUME_Pos)
+#define OTG_FS_INT_STAT_ATTACH_Pos              (6)
+#define OTG_FS_INT_STAT_ATTACH                  (0x01U << OTG_FS_INT_STAT_ATTACH_Pos)
+#define OTG_FS_INT_STAT_STALL_Pos               (7)
+#define OTG_FS_INT_STAT_STALL                   (0x01U << OTG_FS_INT_STAT_STALL_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_INT_ENB Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_INT_ENB_USB_RST_EN_Pos           (0)
+#define OTG_FS_INT_ENB_USB_RST_EN               (0x01U << OTG_FS_INT_ENB_USB_RST_EN_Pos)
+#define OTG_FS_INT_ENB_ERROR_EN_Pos             (1)
+#define OTG_FS_INT_ENB_ERROR_EN                 (0x01U << OTG_FS_INT_ENB_ERROR_EN_Pos)
+#define OTG_FS_INT_ENB_SOF_TOK_EN_Pos           (2)
+#define OTG_FS_INT_ENB_SOF_TOK_EN               (0x01U << OTG_FS_INT_ENB_SOF_TOK_EN_Pos)
+#define OTG_FS_INT_ENB_TOK_DNE_EN_Pos           (3)
+#define OTG_FS_INT_ENB_TOK_DNE_EN               (0x01U << OTG_FS_INT_ENB_TOK_DNE_EN_Pos)
+#define OTG_FS_INT_ENB_SLEEP_EN_Pos             (4)
+#define OTG_FS_INT_ENB_SLEEP_EN                 (0x01U << OTG_FS_INT_ENB_SLEEP_EN_Pos)
+#define OTG_FS_INT_ENB_RESUME_EN_Pos            (5)
+#define OTG_FS_INT_ENB_RESUME_EN                (0x01U << OTG_FS_INT_ENB_RESUME_EN_Pos)
+#define OTG_FS_INT_ENB_ATTACH_EN_Pos            (6)
+#define OTG_FS_INT_ENB_ATTACH_EN                (0x01U << OTG_FS_INT_ENB_ATTACH_EN_Pos)
+#define OTG_FS_INT_ENB_STALL_EN_Pos             (7)
+#define OTG_FS_INT_ENB_STALL_EN                 (0x01U << OTG_FS_INT_ENB_STALL_EN_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_ERR_STAT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_ERR_STAT_PID_ERR_Pos             (0)
+#define OTG_FS_ERR_STAT_PID_ERR                 (0x01U << OTG_FS_ERR_STAT_PID_ERR_Pos)
+#define OTG_FS_ERR_STAT_CRC5_EOF_Pos            (1)
+#define OTG_FS_ERR_STAT_CRC5_EOF                (0x01U << OTG_FS_ERR_STAT_CRC5_EOF_Pos)
+#define OTG_FS_ERR_STAT_CRC16_Pos               (2)
+#define OTG_FS_ERR_STAT_CRC16                   (0x01U << OTG_FS_ERR_STAT_CRC16_Pos)
+#define OTG_FS_ERR_STAT_DFN8_Pos                (3)
+#define OTG_FS_ERR_STAT_DFN8                    (0x01U << OTG_FS_ERR_STAT_DFN8_Pos)
+#define OTG_FS_ERR_STAT_BTO_ERR_Pos             (4)
+#define OTG_FS_ERR_STAT_BTO_ERR                 (0x01U << OTG_FS_ERR_STAT_BTO_ERR_Pos)
+#define OTG_FS_ERR_STAT_DMA_ERR_Pos             (5)
+#define OTG_FS_ERR_STAT_DMA_ERR                 (0x01U << OTG_FS_ERR_STAT_DMA_ERR_Pos)
+#define OTG_FS_ERR_STAT_BTS_ERR_Pos             (7)
+#define OTG_FS_ERR_STAT_BTS_ERR                 (0x01U << OTG_FS_ERR_STAT_BTS_ERR_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_ERR_ENB Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_ERR_ENB_PID_ERR_EN_Pos           (0)
+#define OTG_FS_ERR_ENB_PID_ERR_EN               (0x01U << OTG_FS_ERR_ENB_PID_ERR_EN_Pos)
+#define OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos          (1)
+#define OTG_FS_ERR_ENB_CRC5_EOF_EN              (0x01U << OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos)
+#define OTG_FS_ERR_ENB_CRC16_EN_Pos             (2)
+#define OTG_FS_ERR_ENB_CRC16_EN                 (0x01U << OTG_FS_ERR_ENB_CRC16_EN_Pos)
+#define OTG_FS_ERR_ENB_DFN8_EN_Pos              (3)
+#define OTG_FS_ERR_ENB_DFN8_EN                  (0x01U << OTG_FS_ERR_ENB_DFN8_EN_Pos)
+#define OTG_FS_ERR_ENB_BTO_ERR_EN_Pos           (4)
+#define OTG_FS_ERR_ENB_BTO_ERR_EN               (0x01U << OTG_FS_ERR_ENB_BTO_ERR_EN_Pos)
+#define OTG_FS_ERR_ENB_DMA_ERR_EN_Pos           (5)
+#define OTG_FS_ERR_ENB_DMA_ERR_EN               (0x01U << OTG_FS_ERR_ENB_DMA_ERR_EN_Pos)
+#define OTG_FS_ERR_ENB_BTS_ERR_EN_Pos           (7)
+#define OTG_FS_ERR_ENB_BTS_ERR_EN               (0x01U << OTG_FS_ERR_ENB_BTS_ERR_EN_Pos)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_STAT Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_STAT_ODD_Pos                     (2)
+#define OTG_FS_STAT_ODD                         (0x01U << OTG_FS_STAT_ODD_Pos)
+#define OTG_FS_STAT_TX_Pos                      (3)
+#define OTG_FS_STAT_TX                          (0x01U << OTG_FS_STAT_TX_Pos)
+#define OTG_FS_STAT_ENDP_Pos                    (4)
+#define OTG_FS_STAT_ENDP                        (0x0FU << OTG_FS_STAT_ENDP_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_CTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_CTL_USB_EN_SOF_EN_Pos            (0)
+#define OTG_FS_CTL_USB_EN_SOF_EN                (0x01U << OTG_FS_CTL_USB_EN_SOF_EN_Pos)
+#define OTG_FS_CTL_ODD_RST_Pos                  (1)
+#define OTG_FS_CTL_ODD_RST                      (0x01U << OTG_FS_CTL_ODD_RST_Pos)
+#define OTG_FS_CTL_RESUME_Pos                   (2)
+#define OTG_FS_CTL_RESUME                       (0x01U << OTG_FS_CTL_RESUME_Pos)
+#define OTG_FS_CTL_HOST_MODE_EN_Pos             (3)
+#define OTG_FS_CTL_HOST_MODE_EN                 (0x01U << OTG_FS_CTL_HOST_MODE_EN_Pos)
+#define OTG_FS_CTL_RESET_Pos                    (4)
+#define OTG_FS_CTL_RESET                        (0x01U << OTG_FS_CTL_RESET_Pos)
+#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos     (5)
+#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY         (0x01U << OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos)
+#define OTG_FS_CTL_SE0_Pos                      (6)
+#define OTG_FS_CTL_SE0                          (0x01U << OTG_FS_CTL_SE0_Pos)
+#define OTG_FS_CTL_JSTATE_Pos                   (7)
+#define OTG_FS_CTL_JSTATE                       (0x01U << OTG_FS_CTL_JSTATE_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_ADDR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_ADDR_ADDR_Pos                    (0)
+#define OTG_FS_ADDR_ADDR                        (0x7FU << OTG_FS_ADDR_ADDR_Pos)
+#define OTG_FS_ADDR_LS_EN_Pos                   (7)
+#define OTG_FS_ADDR_LS_EN                       (0x01U << OTG_FS_ADDR_LS_EN_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_BDT_PAGE_01 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos      (1)
+#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9          (0x7FU << OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_FRM_NUML Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_FRM_NUML_FRM_Pos                 (0)
+#define OTG_FS_FRM_NUML_FRM                     (0xFFU << OTG_FS_FRM_NUML_FRM_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_FRM_NUMH Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_FRM_NUMH_FRM_Pos                 (0)
+#define OTG_FS_FRM_NUMH_FRM                     (0x07U << OTG_FS_FRM_NUMH_FRM_Pos)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_TOKEN Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_TOKEN_TOKEN_ENDPT_Pos            (0)
+#define OTG_FS_TOKEN_TOKEN_ENDPT                (0x0FU << OTG_FS_TOKEN_TOKEN_ENDPT_Pos)
+#define OTG_FS_TOKEN_TOKEN_PID_Pos              (4)
+#define OTG_FS_TOKEN_TOKEN_PID                  (0x0FU << OTG_FS_TOKEN_TOKEN_PID_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_SOF_THLD Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_SOF_THLD_CNT_Pos                 (0)
+#define OTG_FS_SOF_THLD_CNT                     (0xFFU << OTG_FS_SOF_THLD_CNT_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_BDT_PAGE_02 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos     (0)
+#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16         (0xFFU << OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_BDT_PAGE_03 Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos     (0)
+#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24         (0xFFU << OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos)
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS_EP_CTL Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define OTG_FS_EP_CTL_EP_HSHK_Pos               (0)
+#define OTG_FS_EP_CTL_EP_HSHK                   (0x01U << OTG_FS_EP_CTL_EP_HSHK_Pos)
+#define OTG_FS_EP_CTL_EP_STALL_Pos              (1)
+#define OTG_FS_EP_CTL_EP_STALL                  (0x01U << OTG_FS_EP_CTL_EP_STALL_Pos)
+#define OTG_FS_EP_CTL_EP_TX_EN_Pos              (2)
+#define OTG_FS_EP_CTL_EP_TX_EN                  (0x01U << OTG_FS_EP_CTL_EP_TX_EN_Pos)
+#define OTG_FS_EP_CTL_EP_RX_EN_Pos              (3)
+#define OTG_FS_EP_CTL_EP_RX_EN                  (0x01U << OTG_FS_EP_CTL_EP_RX_EN_Pos)
+#define OTG_FS_EP_CTL_EP_CTL_DIS_Pos            (4)
+#define OTG_FS_EP_CTL_EP_CTL_DIS                (0x01U << OTG_FS_EP_CTL_EP_CTL_DIS_Pos)
+#define OTG_FS_EP_CTL_RETRY_DIS_Pos             (6)
+#define OTG_FS_EP_CTL_RETRY_DIS                 (0x01U << OTG_FS_EP_CTL_RETRY_DIS_Pos)
+#define OTG_FS_EP_CTL_HOST_WO_HUB_Pos           (7)
+#define OTG_FS_EP_CTL_HOST_WO_HUB               (0x01U << OTG_FS_EP_CTL_HOST_WO_HUB_Pos)
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief OTG_FS Buffer Descriptor Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+
+#define OTG_FS_BD_TOK_PID_Pos                   (2)
+#define OTG_FS_BD_TOK_PID                       (0x0FU << OTG_FS_BD_TOK_PID_Pos)
+#define OTG_FS_BD_DATA01_Pos                    (6)
+#define OTG_FS_BD_DATA01                        (0x01U << OTG_FS_BD_DATA01_Pos)
+#define OTG_FS_BD_OWN_Pos                       (7)
+#define OTG_FS_BD_OWN                           (0x01U << OTG_FS_BD_OWN_Pos)
+#define OTG_FS_BD_BC_Pos                        (16)
+#define OTG_FS_BD_BC                            (0x3FFU << OTG_FS_BD_BC_Pos)
+#define OTG_FS_BD_ADDRESS_Pos                   (0)
+#define OTG_FS_BD_ADDRESS                       (0xFFFFFFFFU << OTG_FS_BD_ADDRESS_Pos)
+
+
+
+/**
+* @}
+*/
+//#define OTG_FS_INT_STAT_RST         ((uint32_t)0x01)
+//#define OTG_FS_INT_STAT_ERROR       ((uint32_t)0x02)
+//#define OTG_FS_INT_STAT_SOF         ((uint32_t)0x04)
+//#define OTG_FS_INT_STAT_DNE         ((uint32_t)0x08)
+//#define OTG_FS_INT_STAT_SLEEP       ((uint32_t)0x10)
+//#define OTG_FS_INT_STAT_RESUME      ((uint32_t)0x20)
+//#define OTG_FS_INT_STAT_ATTACH      ((uint32_t)0x40)
+//#define OTG_FS_INT_STAT_STALL       ((uint32_t)0x80)
+
+//TEMP
+#define  USB_INT_STAT_RST       0x01
+#define  USB_INT_STAT_ERROR     0x02
+#define  USB_INT_STAT_SOF_TOK   0x04
+#define  USB_INT_STAT_TOK_DNE   0x08
+#define  USB_INT_STAT_SLEEP     0x10
+#define  USB_INT_STAT_RESUME    0x20
+#define  USB_INT_STAT_ATTACH    0x40
+#define  USB_INT_STAT_STALL     0x80
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+/*! @name PERID - Peripheral ID register */
+#define USB_PERID_ID_MASK                        (0x3FU)
+#define USB_PERID_ID_SHIFT                       (0U)
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USB_IDCOMP_NID_MASK                      (0x3FU)
+#define USB_IDCOMP_NID_SHIFT                     (0U)
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USB_REV_REV_MASK                         (0xFFU)
+#define USB_REV_REV_SHIFT                        (0U)
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USB_ADDINFO_IEHOST_MASK                  (0x1U)
+#define USB_ADDINFO_IEHOST_SHIFT                 (0U)
+#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         (0x20U)
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        (5U)
+#define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USB_OTGISTAT_ONEMSEC_MASK                (0x40U)
+#define USB_OTGISTAT_ONEMSEC_SHIFT               (6U)
+#define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control register */
+#define USB_OTGICR_LINESTATEEN_MASK              (0x20U)
+#define USB_OTGICR_LINESTATEEN_SHIFT             (5U)
+#define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
+#define USB_OTGICR_ONEMSECEN_MASK                (0x40U)
+#define USB_OTGICR_ONEMSECEN_SHIFT               (6U)
+#define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         (0x20U)
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        (5U)
+#define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
+#define USB_OTGSTAT_ONEMSECEN_MASK               (0x40U)
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              (6U)
+#define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
+
+/*! @name OTGCTL - OTG Control register */
+#define USB_OTGCTL_OTGEN_MASK                    (0x4U)
+#define USB_OTGCTL_OTGEN_SHIFT                   (2U)
+#define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
+#define USB_OTGCTL_DMLOW_MASK                    (0x10U)
+#define USB_OTGCTL_DMLOW_SHIFT                   (4U)
+#define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
+#define USB_OTGCTL_DPLOW_MASK                    (0x20U)
+#define USB_OTGCTL_DPLOW_SHIFT                   (5U)
+#define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
+#define USB_OTGCTL_DPHIGH_MASK                   (0x80U)
+#define USB_OTGCTL_DPHIGH_SHIFT                  (7U)
+#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USB_ISTAT_USBRST_MASK                    (0x1U)
+#define USB_ISTAT_USBRST_SHIFT                   (0U)
+#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
+#define USB_ISTAT_ERROR_MASK                     (0x2U)
+#define USB_ISTAT_ERROR_SHIFT                    (1U)
+#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
+#define USB_ISTAT_SOFTOK_MASK                    (0x4U)
+#define USB_ISTAT_SOFTOK_SHIFT                   (2U)
+#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
+#define USB_ISTAT_TOKDNE_MASK                    (0x8U)
+#define USB_ISTAT_TOKDNE_SHIFT                   (3U)
+#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
+#define USB_ISTAT_SLEEP_MASK                     (0x10U)
+#define USB_ISTAT_SLEEP_SHIFT                    (4U)
+#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
+#define USB_ISTAT_RESUME_MASK                    (0x20U)
+#define USB_ISTAT_RESUME_SHIFT                   (5U)
+#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
+#define USB_ISTAT_ATTACH_MASK                    (0x40U)
+#define USB_ISTAT_ATTACH_SHIFT                   (6U)
+#define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
+#define USB_ISTAT_STALL_MASK                     (0x80U)
+#define USB_ISTAT_STALL_SHIFT                    (7U)
+#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
+
+/*! @name INTEN - Interrupt Enable register */
+#define USB_INTEN_USBRSTEN_MASK                  (0x1U)
+#define USB_INTEN_USBRSTEN_SHIFT                 (0U)
+#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
+#define USB_INTEN_ERROREN_MASK                   (0x2U)
+#define USB_INTEN_ERROREN_SHIFT                  (1U)
+#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
+#define USB_INTEN_SOFTOKEN_MASK                  (0x4U)
+#define USB_INTEN_SOFTOKEN_SHIFT                 (2U)
+#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
+#define USB_INTEN_TOKDNEEN_MASK                  (0x8U)
+#define USB_INTEN_TOKDNEEN_SHIFT                 (3U)
+#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
+#define USB_INTEN_SLEEPEN_MASK                   (0x10U)
+#define USB_INTEN_SLEEPEN_SHIFT                  (4U)
+#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
+#define USB_INTEN_RESUMEEN_MASK                  (0x20U)
+#define USB_INTEN_RESUMEEN_SHIFT                 (5U)
+#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
+#define USB_INTEN_ATTACHEN_MASK                  (0x40U)
+#define USB_INTEN_ATTACHEN_SHIFT                 (6U)
+#define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
+#define USB_INTEN_STALLEN_MASK                   (0x80U)
+#define USB_INTEN_STALLEN_SHIFT                  (7U)
+#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USB_ERRSTAT_PIDERR_MASK                  (0x1U)
+#define USB_ERRSTAT_PIDERR_SHIFT                 (0U)
+#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
+#define USB_ERRSTAT_CRC5EOF_MASK                 (0x2U)
+#define USB_ERRSTAT_CRC5EOF_SHIFT                (1U)
+#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
+#define USB_ERRSTAT_CRC16_MASK                   (0x4U)
+#define USB_ERRSTAT_CRC16_SHIFT                  (2U)
+#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
+#define USB_ERRSTAT_DFN8_MASK                    (0x8U)
+#define USB_ERRSTAT_DFN8_SHIFT                   (3U)
+#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
+#define USB_ERRSTAT_BTOERR_MASK                  (0x10U)
+#define USB_ERRSTAT_BTOERR_SHIFT                 (4U)
+#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
+#define USB_ERRSTAT_DMAERR_MASK                  (0x20U)
+#define USB_ERRSTAT_DMAERR_SHIFT                 (5U)
+#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
+#define USB_ERRSTAT_OWNERR_MASK                  (0x40U)
+#define USB_ERRSTAT_OWNERR_SHIFT                 (6U)
+#define USB_ERRSTAT_OWNERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
+#define USB_ERRSTAT_BTSERR_MASK                  (0x80U)
+#define USB_ERRSTAT_BTSERR_SHIFT                 (7U)
+#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USB_ERREN_PIDERREN_MASK                  (0x1U)
+#define USB_ERREN_PIDERREN_SHIFT                 (0U)
+#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
+#define USB_ERREN_CRC5EOFEN_MASK                 (0x2U)
+#define USB_ERREN_CRC5EOFEN_SHIFT                (1U)
+#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
+#define USB_ERREN_CRC16EN_MASK                   (0x4U)
+#define USB_ERREN_CRC16EN_SHIFT                  (2U)
+#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
+#define USB_ERREN_DFN8EN_MASK                    (0x8U)
+#define USB_ERREN_DFN8EN_SHIFT                   (3U)
+#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
+#define USB_ERREN_BTOERREN_MASK                  (0x10U)
+#define USB_ERREN_BTOERREN_SHIFT                 (4U)
+#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
+#define USB_ERREN_DMAERREN_MASK                  (0x20U)
+#define USB_ERREN_DMAERREN_SHIFT                 (5U)
+#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
+#define USB_ERREN_OWNERREN_MASK                  (0x40U)
+#define USB_ERREN_OWNERREN_SHIFT                 (6U)
+#define USB_ERREN_OWNERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
+#define USB_ERREN_BTSERREN_MASK                  (0x80U)
+#define USB_ERREN_BTSERREN_SHIFT                 (7U)
+#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status register */
+#define USB_STAT_ODD_MASK                        (0x4U)
+#define USB_STAT_ODD_SHIFT                       (2U)
+#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
+#define USB_STAT_TX_MASK                         (0x8U)
+#define USB_STAT_TX_SHIFT                        (3U)
+#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
+#define USB_STAT_ENDP_MASK                       (0xF0U)
+#define USB_STAT_ENDP_SHIFT                      (4U)
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USB_CTL_USBENSOFEN_MASK                  (0x1U)
+#define USB_CTL_USBENSOFEN_SHIFT                 (0U)
+#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
+#define USB_CTL_ODDRST_MASK                      (0x2U)
+#define USB_CTL_ODDRST_SHIFT                     (1U)
+#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
+#define USB_CTL_RESUME_MASK                      (0x4U)
+#define USB_CTL_RESUME_SHIFT                     (2U)
+#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
+#define USB_CTL_HOSTMODEEN_MASK                  (0x8U)
+#define USB_CTL_HOSTMODEEN_SHIFT                 (3U)
+#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
+#define USB_CTL_RESET_MASK                       (0x10U)
+#define USB_CTL_RESET_SHIFT                      (4U)
+#define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          (0x20U)
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         (5U)
+#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USB_CTL_SE0_MASK                         (0x40U)
+#define USB_CTL_SE0_SHIFT                        (6U)
+#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
+#define USB_CTL_JSTATE_MASK                      (0x80U)
+#define USB_CTL_JSTATE_SHIFT                     (7U)
+#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address register */
+#define USB_ADDR_ADDR_MASK                       (0x7FU)
+#define USB_ADDR_ADDR_SHIFT                      (0U)
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       (0x80U)
+#define USB_ADDR_LSEN_SHIFT                      (7U)
+#define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK                  (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT                 (1U)
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number register Low */
+#define USB_FRMNUML_FRM_MASK                     (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT                    (0U)
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number register High */
+#define USB_FRMNUMH_FRM_MASK                     (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT                    (0U)
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USB_TOKEN_TOKENENDPT_MASK                (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT               (0U)
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT                 (4U)
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold register */
+#define USB_SOFTHLD_CNT_MASK                     (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT                    (0U)
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USB_ENDPT_EPHSHK_MASK                    (0x1U)
+#define USB_ENDPT_EPHSHK_SHIFT                   (0U)
+#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
+#define USB_ENDPT_EPSTALL_MASK                   (0x2U)
+#define USB_ENDPT_EPSTALL_SHIFT                  (1U)
+#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
+#define USB_ENDPT_EPTXEN_MASK                    (0x4U)
+#define USB_ENDPT_EPTXEN_SHIFT                   (2U)
+#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
+#define USB_ENDPT_EPRXEN_MASK                    (0x8U)
+#define USB_ENDPT_EPRXEN_SHIFT                   (3U)
+#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
+#define USB_ENDPT_EPCTLDIS_MASK                  (0x10U)
+#define USB_ENDPT_EPCTLDIS_SHIFT                 (4U)
+#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
+#define USB_ENDPT_RETRYDIS_MASK                  (0x40U)
+#define USB_ENDPT_RETRYDIS_SHIFT                 (6U)
+#define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
+#define USB_ENDPT_HOSTWOHUB_MASK                 (0x80U)
+#define USB_ENDPT_HOSTWOHUB_SHIFT                (7U)
+#define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT                          (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USB_USBCTRL_UARTSEL_MASK                 (0x10U)
+#define USB_USBCTRL_UARTSEL_SHIFT                (4U)
+#define USB_USBCTRL_UARTSEL(x)                   (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
+#define USB_USBCTRL_UARTCHLS_MASK                (0x20U)
+#define USB_USBCTRL_UARTCHLS_SHIFT               (5U)
+#define USB_USBCTRL_UARTCHLS(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
+#define USB_USBCTRL_PDE_MASK                     (0x40U)
+#define USB_USBCTRL_PDE_SHIFT                    (6U)
+#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
+#define USB_USBCTRL_SUSP_MASK                    (0x80U)
+#define USB_USBCTRL_SUSP_SHIFT                   (7U)
+#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USB_OBSERVE_DMPD_MASK                    (0x10U)
+#define USB_OBSERVE_DMPD_SHIFT                   (4U)
+#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
+#define USB_OBSERVE_DPPD_MASK                    (0x40U)
+#define USB_OBSERVE_DPPD_SHIFT                   (6U)
+#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
+#define USB_OBSERVE_DPPU_MASK                    (0x80U)
+#define USB_OBSERVE_DPPU_SHIFT                   (7U)
+#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          (0x10U)
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         (4U)
+#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          (0x1U)
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         (0U)
+#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
+#define USB_USBTRC0_SYNC_DET_MASK                (0x2U)
+#define USB_USBTRC0_SYNC_DET_SHIFT               (1U)
+#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    (0x4U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   (2U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
+#define USB_USBTRC0_VREDG_DET_MASK               (0x8U)
+#define USB_USBTRC0_VREDG_DET_SHIFT              (3U)
+#define USB_USBTRC0_VREDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
+#define USB_USBTRC0_VFEDG_DET_MASK               (0x10U)
+#define USB_USBTRC0_VFEDG_DET_SHIFT              (4U)
+#define USB_USBTRC0_VFEDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
+#define USB_USBTRC0_USBRESMEN_MASK               (0x20U)
+#define USB_USBTRC0_USBRESMEN_SHIFT              (5U)
+#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
+#define USB_USBTRC0_USBRESET_MASK                (0x80U)
+#define USB_USBTRC0_USBRESET_SHIFT               (7U)
+#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK                (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT               (0U)
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
+/*! @name MISCCTRL - Miscellaneous Control register */
+#define USB_MISCCTRL_SOFDYNTHLD_MASK             (0x1U)
+#define USB_MISCCTRL_SOFDYNTHLD_SHIFT            (0U)
+#define USB_MISCCTRL_SOFDYNTHLD(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
+#define USB_MISCCTRL_SOFBUSSET_MASK              (0x2U)
+#define USB_MISCCTRL_SOFBUSSET_SHIFT             (1U)
+#define USB_MISCCTRL_SOFBUSSET(x)                (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
+#define USB_MISCCTRL_OWNERRISODIS_MASK           (0x4U)
+#define USB_MISCCTRL_OWNERRISODIS_SHIFT          (2U)
+#define USB_MISCCTRL_OWNERRISODIS(x)             (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
+#define USB_MISCCTRL_VREDG_EN_MASK               (0x8U)
+#define USB_MISCCTRL_VREDG_EN_SHIFT              (3U)
+#define USB_MISCCTRL_VREDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
+#define USB_MISCCTRL_VFEDG_EN_MASK               (0x10U)
+#define USB_MISCCTRL_VFEDG_EN_SHIFT              (4U)
+#define USB_MISCCTRL_VFEDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
+#define USB_MISCCTRL_STL_ADJ_EN_MASK             (0x80U)
+#define USB_MISCCTRL_STL_ADJ_EN_SHIFT            (7U)
+#define USB_MISCCTRL_STL_ADJ_EN(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK)
+
+/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */
+#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK       (0x1U)
+#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT      (0U)
+#define USB_STALL_IL_DIS_STALL_I_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK       (0x2U)
+#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT      (1U)
+#define USB_STALL_IL_DIS_STALL_I_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK       (0x4U)
+#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT      (2U)
+#define USB_STALL_IL_DIS_STALL_I_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK       (0x8U)
+#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT      (3U)
+#define USB_STALL_IL_DIS_STALL_I_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK       (0x10U)
+#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT      (4U)
+#define USB_STALL_IL_DIS_STALL_I_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK       (0x20U)
+#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT      (5U)
+#define USB_STALL_IL_DIS_STALL_I_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK       (0x40U)
+#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT      (6U)
+#define USB_STALL_IL_DIS_STALL_I_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
+#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK       (0x80U)
+#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT      (7U)
+#define USB_STALL_IL_DIS_STALL_I_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
+
+/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */
+#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK       (0x1U)
+#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT      (0U)
+#define USB_STALL_IH_DIS_STALL_I_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK       (0x2U)
+#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT      (1U)
+#define USB_STALL_IH_DIS_STALL_I_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK      (0x4U)
+#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT     (2U)
+#define USB_STALL_IH_DIS_STALL_I_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK      (0x8U)
+#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT     (3U)
+#define USB_STALL_IH_DIS_STALL_I_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK      (0x10U)
+#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT     (4U)
+#define USB_STALL_IH_DIS_STALL_I_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK      (0x20U)
+#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT     (5U)
+#define USB_STALL_IH_DIS_STALL_I_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK      (0x40U)
+#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT     (6U)
+#define USB_STALL_IH_DIS_STALL_I_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
+#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK      (0x80U)
+#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT     (7U)
+#define USB_STALL_IH_DIS_STALL_I_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
+
+/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */
+#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK       (0x1U)
+#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT      (0U)
+#define USB_STALL_OL_DIS_STALL_O_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK       (0x2U)
+#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT      (1U)
+#define USB_STALL_OL_DIS_STALL_O_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK       (0x4U)
+#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT      (2U)
+#define USB_STALL_OL_DIS_STALL_O_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK       (0x8U)
+#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT      (3U)
+#define USB_STALL_OL_DIS_STALL_O_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK       (0x10U)
+#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT      (4U)
+#define USB_STALL_OL_DIS_STALL_O_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK       (0x20U)
+#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT      (5U)
+#define USB_STALL_OL_DIS_STALL_O_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK       (0x40U)
+#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT      (6U)
+#define USB_STALL_OL_DIS_STALL_O_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
+#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK       (0x80U)
+#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT      (7U)
+#define USB_STALL_OL_DIS_STALL_O_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
+
+/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */
+#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK       (0x1U)
+#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT      (0U)
+#define USB_STALL_OH_DIS_STALL_O_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK       (0x2U)
+#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT      (1U)
+#define USB_STALL_OH_DIS_STALL_O_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK      (0x4U)
+#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT     (2U)
+#define USB_STALL_OH_DIS_STALL_O_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK      (0x8U)
+#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT     (3U)
+#define USB_STALL_OH_DIS_STALL_O_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK      (0x10U)
+#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT     (4U)
+#define USB_STALL_OH_DIS_STALL_O_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK      (0x20U)
+#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT     (5U)
+#define USB_STALL_OH_DIS_STALL_O_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK      (0x40U)
+#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT     (6U)
+#define USB_STALL_OH_DIS_STALL_O_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
+#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK      (0x80U)
+#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT     (7U)
+#define USB_STALL_OH_DIS_STALL_O_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       (0x1U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      (0U)
+#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       (0x2U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      (1U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+
+/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)   (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+#define USB0_BASE                                ((0x50000000))
+
+#define USB_BASE_ADDRS                           { USB0_BASE }
+
+
+
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif //__REG_USB_OTG_FS_H
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h
new file mode 100644
index 000000000..a802bbab6
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h
@@ -0,0 +1,133 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     reg_wwdg.h
+/// @author   AE TEAM
+/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
+///           MM32 FIRMWARE LIBRARY.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+
+#ifndef __REG_WWDG_H
+#define __REG_WWDG_H
+
+// Files includes
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "types.h"
+
+
+
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+
+
+
+
+
+
+
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG Base Address Definition
+////////////////////////////////////////////////////////////////////////////////
+#define WWDG_BASE                       (APB1PERIPH_BASE + 0x2C00)              ///< Base Address: 0x40002C00
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG Register Structure Definition
+////////////////////////////////////////////////////////////////////////////////
+#undef USENCOMBINEREGISTER
+#undef USENNEWREGISTER
+#undef USENOLDREGISTER
+#define USENCOMBINEREGISTER
+#ifdef USENCOMBINEREGISTER
+typedef struct {
+    __IO u32 CR;                                                                ///< Control register                               offset: 0x00
+    union {
+        __IO u32 CFGR;                                                          ///< Configuration register                         offset: 0x04
+        __IO u32 CFR;
+    };
+    __IO u32 SR;                                                                ///< Status register                                offset: 0x08
+} WWDG_TypeDef;
+#endif
+#ifdef USENNEWREGISTER
+typedef struct {
+    __IO u32 CR;                                                                ///< Control register                               offset: 0x00
+    __IO u32 CFGR;                                                              ///< Configuration register                         offset: 0x04
+    __IO u32 SR;                                                                ///< Status register                                offset: 0x08
+} WWDG_TypeDef;
+#endif
+#ifdef USENOLDREGISTER
+typedef struct {
+    __IO u32 CR;
+    __IO u32 CFR;
+    __IO u32 SR;
+} WWDG_TypeDef;
+#endif
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG type pointer Definition
+////////////////////////////////////////////////////////////////////////////////
+#define WWDG                            ((WWDG_TypeDef*) WWDG_BASE)
+
+
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG_CR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define WWDG_CR_CNT_Pos                 (0)
+#define WWDG_CR_CNT                     (0x7FU << WWDG_CR_CNT_Pos)              ///< T[6:0] bits (7-Bit counter (MSB to LSB))
+#define WWDG_CR_WDGA_Pos                (7)
+#define WWDG_CR_WDGA                    (0x01U << WWDG_CR_WDGA_Pos)             ///< Activation bit
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG_CFR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define WWDG_CFGR_WINDOW_Pos            (0)
+#define WWDG_CFGR_WINDOW                (0x7FU << WWDG_CFGR_WINDOW_Pos)         ///< W[6:0] bits (7-bit window value)
+#define WWDG_CFGR_WDGTB_Pos             (7)
+#define WWDG_CFGR_WDGTB                 (0x03U << WWDG_CFGR_WDGTB_Pos)          ///< WDGTB[1:0] bits (Timer Base)
+#define WWDG_CFGR_WDGTB_1               (0x00U << WWDG_CFGR_WDGTB_Pos)          ///< WDGTB[1:0] bits (Timer Base /1)
+#define WWDG_CFGR_WDGTB_2               (0x01U << WWDG_CFGR_WDGTB_Pos)          ///< WDGTB[1:0] bits (Timer Base /2)
+#define WWDG_CFGR_WDGTB_4               (0x02U << WWDG_CFGR_WDGTB_Pos)          ///< WDGTB[1:0] bits (Timer Base /4)
+#define WWDG_CFGR_WDGTB_8               (0x03U << WWDG_CFGR_WDGTB_Pos)          ///< WDGTB[1:0] bits (Timer Base /8)
+#define WWDG_CFGR_EWI_Pos               (9)
+#define WWDG_CFGR_EWI                   (0x01U << WWDG_CFGR_EWI_Pos)            ///< Early Wakeup Interrupt
+
+////////////////////////////////////////////////////////////////////////////////
+/// @brief WWDG_SR Register Bit Definition
+////////////////////////////////////////////////////////////////////////////////
+#define WWDG_SR_EWIF_Pos                (0)
+#define WWDG_SR_EWIF                    (0x01U << WWDG_SR_EWIF_Pos)             ///< Early Wakeup Interrupt Flag
+
+
+
+
+/// @}
+
+/// @}
+
+/// @}
+
+////////////////////////////////////////////////////////////////////////////////
+#endif
+////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h
new file mode 100644
index 000000000..baceddd05
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h
@@ -0,0 +1,105 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     types.h
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE TYPE FIRMWARE FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#ifndef __TYPES_H
+#define __TYPES_H
+
+// Files includes
+#include <stdint.h>
+#include <stdbool.h>
+
+
+
+#ifdef __cplusplus
+#define     __I     volatile                        ///< Defines 'read only' permissions
+#else
+#define     __I     volatile const                  ///< Defines 'read only' permissions
+#endif
+#define     __O     volatile                        ///< Defines 'write only' permissions
+#define     __IO    volatile                        ///< Defines 'read / write' permissions
+
+typedef long long    s64;                           ///< used for signed 64bit
+
+typedef signed int   s32;
+typedef signed short s16;
+typedef signed char  s8;
+
+typedef signed int  const  sc32;                    ///< Read Only
+typedef signed short const sc16;                    ///< Read Only
+typedef signed char  const sc8;                     ///< Read Only
+
+typedef volatile signed int   vs32;
+typedef volatile signed short vs16;
+typedef volatile signed char  vs8;
+
+typedef volatile signed int  const  vsc32;          ///< Read Only
+typedef volatile signed short const vsc16;          ///< Read Only
+typedef volatile signed char  const vsc8;           ///< Read Only
+
+typedef unsigned int   u32;
+typedef unsigned short u16;
+typedef unsigned char  u8;
+
+typedef unsigned int  const  uc32;                  ///< Read Only
+typedef unsigned short const uc16;                  ///< Read Only
+typedef unsigned char  const uc8;                   ///< Read Only
+
+typedef volatile unsigned int   vu32;
+typedef volatile unsigned short vu16;
+typedef volatile unsigned char  vu8;
+
+typedef volatile unsigned int  const  vuc32;        ///< Read Only
+typedef volatile unsigned short const vuc16;        ///< Read Only
+typedef volatile unsigned char  const vuc8;         ///< Read Only
+typedef bool    BOOL;
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+#define U8_MAX     ((u8)255)
+#define S8_MAX     ((s8)127)
+#define S8_MIN     ((s8)-128)
+#define U16_MAX    ((u16)65535u)
+#define S16_MAX    ((s16)32767)
+#define S16_MIN    ((s16)-32768)
+#define U32_MAX    ((u32)4294967295uL)
+#define S32_MAX    ((s32)2147483647)
+#define S32_MIN    ((s32)-2147483648uL)
+
+#define MAX(a,b)((a)>(b)?(a):(b))
+#define MIN(a,b)((a)<(b)?(a):(b))
+
+#define SET_BIT(reg, bit)     ((reg) |= (bit))
+#define CLEAR_BIT(reg, bit)   ((reg) &= ~(bit))
+#define READ_BIT(reg, bit)    ((reg) & (bit))
+#define CLEAR_REG(reg)        ((reg) = (0x0))
+#define WRITE_REG(reg, value)   ((reg) = (value))
+#define READ_REG(reg)         ((reg))
+#define MODIFY_REG(reg, CLEARMASK, SETMASK)  WRITE_REG((reg), (((READ_REG(reg)) & (~(CLEARMASK))) | (SETMASK)))
+#define POSITION_VAL(value)     (__CLZ(__RBIT(value)))
+
+#define LEFT_SHIFT_BIT(x)   (1 << x)
+
+
+#endif
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
new file mode 100644
index 000000000..920aefcba
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
@@ -0,0 +1,440 @@
+/**
+  ******************************************************************************
+  * @file      startup_mm32m3ux_u_gcc.s
+  * @author    AE Team
+  * @brief     MM32 devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  */
+
+                .syntax     unified
+                .cpu        cortex-m3
+                .fpu        softvfp
+                .thumb
+
+                .global     g_pfnVectors
+                .global     Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+                .word       _sidata
+/* start address for the .data section. defined in linker script */
+                .word       _sdata
+/* end address for the .data section. defined in linker script */
+                .word       _edata
+/* start address for the .bss section. defined in linker script */
+                .word       _sbss
+/* end address for the .bss section. defined in linker script */
+                .word       _ebss
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+                .section    .text.Reset_Handler
+                .weak       Reset_Handler
+                .type       Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */  
+                movs        r1, #0
+                b           LoopCopyDataInit
+
+CopyDataInit:
+                ldr         r3, =_sidata
+                ldr         r3, [r3, r1]
+                str         r3, [r0, r1]
+                adds        r1, r1, #4
+    
+LoopCopyDataInit:
+                ldr         r0, =_sdata
+                ldr         r3, =_edata
+                adds        r2, r0, r1
+                cmp         r2, r3
+                bcc         CopyDataInit
+                ldr         r2, =_sbss
+                b           LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+                movs        r3, #0
+                str         r3, [r2], #4
+    
+LoopFillZerobss:
+                ldr         r3, = _ebss
+                cmp         r2, r3
+                bcc         FillZerobss
+
+/* Call the clock system intitialization function.*/
+                bl          SystemInit
+/* Call static constructors */
+                bl          __libc_init_array
+/* Call the application's entry point.*/
+                bl          main
+                bx          lr    
+                .size       Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+                .section    .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+                b           Infinite_Loop
+                .size       Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+                .section    .isr_vector,"a",%progbits
+                .type       g_pfnVectors, %object
+                .size       g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:                                                                   
+                .word       _estack                                             /*        Top of Stack                         */
+                .word       Reset_Handler                                       /*        Reset Handler                        */
+                .word       NMI_Handler                                         /*-14     NMI Handler                          */
+                .word       HardFault_Handler                                   /*-13     Hard Fault Handler                   */
+                .word       MemManage_Handler                                   /*-12     MPU Fault Handler                    */
+                .word       BusFault_Handler                                    /*-11     Bus Fault Handler                    */
+                .word       UsageFault_Handler                                  /*-10     Usage Fault Handler                  */
+                .word       0                                                   /*-9      Reserved                             */
+                .word       0                                                   /*-8      Reserved                             */
+                .word       0                                                   /*-7      Reserved                             */
+                .word       0                                                   /*-6      Reserved                             */
+                .word       SVC_Handler                                         /*-5      SVCall Handler                       */
+                .word       DebugMon_Handler                                    /*-4      Debug Monitor Handler                */
+                .word       0                                                   /*-3      Reserved                             */
+                .word       PendSV_Handler                                      /*-2      PendSV Handler                       */
+                .word       SysTick_Handler                                     /*-1      SysTick Handler                      */
+                                                                                
+                /* External Interrupts */
+                .word       WWDG_IRQHandler                                     /*0       Window Watchdog                      */
+                .word       PVD_IRQHandler                                      /*1       PVD through EXTI Line detect         */
+                .word       TAMPER_IRQHandler                                   /*2       Tamper                               */
+                .word       RTC_IRQHandler                                      /*3       RTC                                  */
+                .word       FLASH_IRQHandler                                    /*4       Flash                                */
+                .word       RCC_CRS_IRQHandler                                  /*5       RCC                                  */
+                .word       EXTI0_IRQHandler                                    /*6       EXTI Line 0                          */
+                .word       EXTI1_IRQHandler                                    /*7       EXTI Line 1                          */
+                .word       EXTI2_IRQHandler                                    /*8       EXTI Line 2                          */
+                .word       EXTI3_IRQHandler                                    /*9       EXTI Line 3                          */
+                .word       EXTI4_IRQHandler                                    /*10      EXTI Line 4                          */
+                .word       DMA1_Channel1_IRQHandler                            /*11      DMA1 Channel 1                       */
+                .word       DMA1_Channel2_IRQHandler                            /*12      DMA1 Channel 2                       */
+                .word       DMA1_Channel3_IRQHandler                            /*13      DMA1 Channel 3                       */
+                .word       DMA1_Channel4_IRQHandler                            /*14      DMA1 Channel 4                       */
+                .word       DMA1_Channel5_IRQHandler                            /*15      DMA1 Channel 5                       */
+                .word       DMA1_Channel6_IRQHandler                            /*16      DMA1 Channel 6                       */
+                .word       DMA1_Channel7_IRQHandler                            /*17      DMA1 Channel 7                       */
+                .word       ADC1_2_IRQHandler                                   /*18      ADC1 and ADC2                        */
+                .word       FlashCache_IRQHandler                               /*19      FlashCache outage                    */
+                .word       0                                                   /*20      Reserved                             */
+                .word       CAN1_RX_IRQHandler                                  /*21      CAN1_RX                              */
+                .word       0                                                   /*22      Reserved                             */
+                .word       EXTI9_5_IRQHandler                                  /*23      EXTI Line 9..5                       */
+                .word       TIM1_BRK_IRQHandler                                 /*24      TIM1 Break                           */
+                .word       TIM1_UP_IRQHandler                                  /*25      TIM1 Update                          */
+                .word       TIM1_TRG_COM_IRQHandler                             /*26      TIM1 Trigger and Commutation         */
+                .word       TIM1_CC_IRQHandler                                  /*27      TIM1 Capture Compare                 */
+                .word       TIM2_IRQHandler                                     /*28      TIM2                                 */
+                .word       TIM3_IRQHandler                                     /*29      TIM3                                 */
+                .word       TIM4_IRQHandler                                     /*30      TIM4                                 */
+                .word       I2C1_IRQHandler                                     /*31      I2C1 Event                           */
+                .word       0                                                   /*32      Reserved                             */
+                .word       I2C2_IRQHandler                                     /*33      I2C2 Event                           */
+                .word       0                                                   /*34      Reserved                             */
+                .word       SPI1_IRQHandler                                     /*35      SPI1                                 */
+                .word       SPI2_IRQHandler                                     /*36      SPI2                                 */
+                .word       UART1_IRQHandler                                    /*37      UART1                                */
+                .word       UART2_IRQHandler                                    /*38      UART2                                */
+                .word       UART3_IRQHandler                                    /*39      UART3                                */
+                .word       EXTI15_10_IRQHandler                                /*40      EXTI Line 15..10                     */
+                .word       RTCAlarm_IRQHandler                                 /*41      RTC Alarm through EXTI Line 17       */
+                .word       OTG_FS_WKUP_IRQHandler                              /*42      USB OTG FS Wakeup through EXTI line  */
+                .word       TIM8_BRK_IRQHandler                                 /*43      TIM8 Break                           */
+                .word       TIM8_UP_IRQHandler                                  /*44      TIM8 Update                          */
+                .word       TIM8_TRG_COM_IRQHandler                             /*45      TIM8 Trigger and Commutation         */
+                .word       TIM8_CC_IRQHandler                                  /*46      TIM8 Capture Compare                 */
+                .word       ADC3_IRQHandler                                     /*47      ADC3                                 */
+                .word       0                                                   /*48      Reserved                             */
+                .word       SDIO_IRQHandler                                     /*49      SDIO                                 */
+                .word       TIM5_IRQHandler                                     /*50      TIM5                                 */
+                .word       SPI3_IRQHandler                                     /*51      SPI3                                 */
+                .word       UART4_IRQHandler                                    /*52      UART4                                */
+                .word       UART5_IRQHandler                                    /*53      UART5                                */
+                .word       TIM6_IRQHandler                                     /*54      TIM6                                 */
+                .word       TIM7_IRQHandler                                     /*55      TIM7                                 */
+                .word       DMA2_Channel1_IRQHandler                            /*56      DMA2 Channel 1                       */
+                .word       DMA2_Channel2_IRQHandler                            /*57      DMA2 Channel 2                       */
+                .word       DMA2_Channel3_IRQHandler                            /*58      DMA2 Channel 3                       */
+                .word       DMA2_Channel4_IRQHandler                            /*59      DMA2 Channel 4                       */
+                .word       DMA2_Channel5_IRQHandler                            /*60      DMA2 Channel 5                       */
+                .word       ETH_IRQHandler                                      /*61      Ethernet                             */
+                .word       0                                                   /*62      Reserved                             */
+                .word       0                                                   /*63      Reserved                             */
+                .word       COMP1_2_IRQHandler                                  /*64      COMP1,COMP2                          */
+                .word       0                                                   /*65      Reserved                             */
+                .word       0                                                   /*66      Reserved                             */
+                .word       OTG_FS_IRQHandler                                   /*67      USB OTG_FullSpeed                    */
+                .word       0                                                   /*68      Reserved                             */
+                .word       0                                                   /*69      Reserved                             */
+                .word       0                                                   /*70      Reserved                             */
+                .word       UART6_IRQHandler                                    /*71      UART6                                */
+                .word       0                                                   /*72      Reserved                             */
+                .word       0                                                   /*73      Reserved                             */
+                .word       0                                                   /*74      Reserved                             */
+                .word       0                                                   /*75      Reserved                             */
+                .word       0                                                   /*76      Reserved                             */
+                .word       0                                                   /*77      Reserved                             */
+                .word       0                                                   /*78      Reserved                             */
+                .word       0                                                   /*79      Reserved                             */
+                .word       0                                                   /*80      Reserved                             */
+                .word       0                                                   /*81      Reserved                             */
+                .word       UART7_IRQHandler                                    /*82      UART7                                */
+                .word       UART8_IRQHandler                                    /*83      UART8                                */
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+                .weak       NMI_Handler
+                .thumb_set  NMI_Handler                 ,Default_Handler
+
+                .weak       HardFault_Handler
+                .thumb_set  HardFault_Handler           ,Default_Handler
+
+                .weak       MemManage_Handler
+                .thumb_set  MemManage_Handler           ,Default_Handler
+
+                .weak       BusFault_Handler
+                .thumb_set  BusFault_Handler            ,Default_Handler
+
+                .weak       UsageFault_Handler
+                .thumb_set  UsageFault_Handler          ,Default_Handler
+
+                .weak       SVC_Handler
+                .thumb_set  SVC_Handler                 ,Default_Handler
+
+                .weak       DebugMon_Handler
+                .thumb_set  DebugMon_Handler            ,Default_Handler
+
+                .weak       PendSV_Handler
+                .thumb_set  PendSV_Handler              ,Default_Handler
+
+                .weak       SysTick_Handler
+                .thumb_set  SysTick_Handler             ,Default_Handler              
+
+
+                .weak       WWDG_IRQHandler             
+                .thumb_set  WWDG_IRQHandler             ,Default_Handler
+                                                        
+                .weak       PVD_IRQHandler              
+                .thumb_set  PVD_IRQHandler              ,Default_Handler
+                                                        
+                .weak       TAMPER_IRQHandler           
+                .thumb_set  TAMPER_IRQHandler           ,Default_Handler
+                                                        
+                .weak       RTC_IRQHandler              
+                .thumb_set  RTC_IRQHandler              ,Default_Handler
+                                                        
+                .weak       FLASH_IRQHandler            
+                .thumb_set  FLASH_IRQHandler            ,Default_Handler
+                                                        
+                .weak       RCC_CRS_IRQHandler          
+                .thumb_set  RCC_CRS_IRQHandler          ,Default_Handler
+                                                        
+                .weak       EXTI0_IRQHandler            
+                .thumb_set  EXTI0_IRQHandler            ,Default_Handler
+                                                        
+                .weak       EXTI1_IRQHandler            
+                .thumb_set  EXTI1_IRQHandler            ,Default_Handler
+                                                        
+                .weak       EXTI2_IRQHandler            
+                .thumb_set  EXTI2_IRQHandler            ,Default_Handler
+                                                        
+                .weak       EXTI3_IRQHandler            
+                .thumb_set  EXTI3_IRQHandler            ,Default_Handler
+                                                        
+                .weak       EXTI4_IRQHandler            
+                .thumb_set  EXTI4_IRQHandler            ,Default_Handler
+                                                        
+                .weak       DMA1_Channel1_IRQHandler    
+                .thumb_set  DMA1_Channel1_IRQHandler    ,Default_Handler
+                                                        
+                .weak       DMA1_Channel2_IRQHandler    
+                .thumb_set  DMA1_Channel2_IRQHandler    ,Default_Handler
+                                                        
+                .weak       DMA1_Channel3_IRQHandler    
+                .thumb_set  DMA1_Channel3_IRQHandler    ,Default_Handler
+                                                        
+                .weak       DMA1_Channel4_IRQHandler    
+                .thumb_set  DMA1_Channel4_IRQHandler    ,Default_Handler
+                                                        
+                .weak       DMA1_Channel5_IRQHandler    
+                .thumb_set  DMA1_Channel5_IRQHandler    ,Default_Handler
+                                                        
+                .weak       DMA1_Channel6_IRQHandler    
+                .thumb_set  DMA1_Channel6_IRQHandler    ,Default_Handler
+                                                        
+                .weak       DMA1_Channel7_IRQHandler    
+                .thumb_set  DMA1_Channel7_IRQHandler    ,Default_Handler
+                                                        
+                .weak       ADC1_2_IRQHandler           
+                .thumb_set  ADC1_2_IRQHandler           ,Default_Handler
+                                                        
+                .weak       FlashCache_IRQHandler       
+                .thumb_set  FlashCache_IRQHandler       ,Default_Handler
+                                                        
+                .weak       CAN1_RX_IRQHandler          
+                .thumb_set  CAN1_RX_IRQHandler          ,Default_Handler
+                                                        
+                .weak       EXTI9_5_IRQHandler          
+                .thumb_set  EXTI9_5_IRQHandler          ,Default_Handler
+                                                        
+                .weak       TIM1_BRK_IRQHandler         
+                .thumb_set  TIM1_BRK_IRQHandler         ,Default_Handler
+                                                        
+                .weak       TIM1_UP_IRQHandler          
+                .thumb_set  TIM1_UP_IRQHandler          ,Default_Handler
+                                                        
+                .weak       TIM1_TRG_COM_IRQHandler     
+                .thumb_set  TIM1_TRG_COM_IRQHandler     ,Default_Handler
+                                                        
+                .weak       TIM1_CC_IRQHandler          
+                .thumb_set  TIM1_CC_IRQHandler          ,Default_Handler
+                                                        
+                .weak       TIM2_IRQHandler             
+                .thumb_set  TIM2_IRQHandler             ,Default_Handler
+                                                        
+                .weak       TIM3_IRQHandler             
+                .thumb_set  TIM3_IRQHandler             ,Default_Handler
+                                                        
+                .weak       TIM4_IRQHandler             
+                .thumb_set  TIM4_IRQHandler             ,Default_Handler
+                                                        
+                .weak       I2C1_IRQHandler             
+                .thumb_set  I2C1_IRQHandler             ,Default_Handler
+                                                        
+                .weak       I2C2_IRQHandler             
+                .thumb_set  I2C2_IRQHandler             ,Default_Handler
+                                                        
+                .weak       SPI1_IRQHandler             
+                .thumb_set  SPI1_IRQHandler             ,Default_Handler
+                                                        
+                .weak       SPI2_IRQHandler             
+                .thumb_set  SPI2_IRQHandler             ,Default_Handler
+                                                        
+                .weak       UART1_IRQHandler            
+                .thumb_set  UART1_IRQHandler            ,Default_Handler
+                                                        
+                .weak       UART2_IRQHandler            
+                .thumb_set  UART2_IRQHandler            ,Default_Handler
+                                                        
+                .weak       UART3_IRQHandler            
+                .thumb_set  UART3_IRQHandler            ,Default_Handler
+                                                        
+                .weak       EXTI15_10_IRQHandler        
+                .thumb_set  EXTI15_10_IRQHandler        ,Default_Handler
+                                                        
+                .weak       RTCAlarm_IRQHandler         
+                .thumb_set  RTCAlarm_IRQHandler         ,Default_Handler
+                                                        
+                .weak       OTG_FS_WKUP_IRQHandler      
+                .thumb_set  OTG_FS_WKUP_IRQHandler      ,Default_Handler
+                                                        
+                .weak       TIM8_BRK_IRQHandler         
+                .thumb_set  TIM8_BRK_IRQHandler         ,Default_Handler
+                                                        
+                .weak       TIM8_UP_IRQHandler          
+                .thumb_set  TIM8_UP_IRQHandler          ,Default_Handler
+                                                        
+                .weak       TIM8_TRG_COM_IRQHandler     
+                .thumb_set  TIM8_TRG_COM_IRQHandler     ,Default_Handler
+                                                        
+                .weak       TIM8_CC_IRQHandler          
+                .thumb_set  TIM8_CC_IRQHandler          ,Default_Handler
+                                                        
+                .weak       ADC3_IRQHandler             
+                .thumb_set  ADC3_IRQHandler             ,Default_Handler
+                                                        
+                .weak       SDIO_IRQHandler             
+                .thumb_set  SDIO_IRQHandler             ,Default_Handler
+                                                        
+                .weak       TIM5_IRQHandler             
+                .thumb_set  TIM5_IRQHandler             ,Default_Handler
+                                                        
+                .weak       SPI3_IRQHandler             
+                .thumb_set  SPI3_IRQHandler             ,Default_Handler
+                                                        
+                .weak       UART4_IRQHandler            
+                .thumb_set  UART4_IRQHandler            ,Default_Handler
+                                                        
+                .weak       UART5_IRQHandler            
+                .thumb_set  UART5_IRQHandler            ,Default_Handler
+                                                        
+                .weak       TIM6_IRQHandler             
+                .thumb_set  TIM6_IRQHandler             ,Default_Handler
+                                                        
+                .weak       TIM7_IRQHandler             
+                .thumb_set  TIM7_IRQHandler             ,Default_Handler
+                                                        
+                .weak       DMA2_Channel1_IRQHandler    
+                .thumb_set  DMA2_Channel1_IRQHandler    ,Default_Handler
+                                                        
+                .weak       DMA2_Channel2_IRQHandler    
+                .thumb_set  DMA2_Channel2_IRQHandler    ,Default_Handler
+                                                        
+                .weak       DMA2_Channel3_IRQHandler    
+                .thumb_set  DMA2_Channel3_IRQHandler    ,Default_Handler
+                                                        
+                .weak       DMA2_Channel4_IRQHandler    
+                .thumb_set  DMA2_Channel4_IRQHandler    ,Default_Handler
+                                                        
+                .weak       DMA2_Channel5_IRQHandler    
+                .thumb_set  DMA2_Channel5_IRQHandler    ,Default_Handler
+                                                        
+                .weak       ETH_IRQHandler              
+                .thumb_set  ETH_IRQHandler              ,Default_Handler
+                                                        
+                .weak       COMP1_2_IRQHandler          
+                .thumb_set  COMP1_2_IRQHandler          ,Default_Handler
+                                                        
+                .weak       OTG_FS_IRQHandler           
+                .thumb_set  OTG_FS_IRQHandler           ,Default_Handler
+                                                        
+                .weak       UART6_IRQHandler            
+                .thumb_set  UART6_IRQHandler            ,Default_Handler
+                                                        
+                .weak       UART7_IRQHandler            
+                .thumb_set  UART7_IRQHandler            ,Default_Handler
+                                                        
+                .weak       UART8_IRQHandler            
+                .thumb_set  UART8_IRQHandler            ,Default_Handler
+
+
+
+
+/****END OF FILE****/
+
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c
new file mode 100644
index 000000000..cdfa8e801
--- /dev/null
+++ b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c
@@ -0,0 +1,866 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     SYSTEM_MM32.C
+/// @author   AE TEAM
+/// @brief    THIS FILE PROVIDES ALL THE SYSTEM FUNCTIONS.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+// Define to prevent recursive inclusion
+#define _SYSTEM_MM32_C_
+
+// Files includes
+
+/// @addtogroup CMSIS
+/// @{
+
+#include "mm32_device.h"
+
+
+/// @}
+
+
+
+/// @}
+
+
+/// Uncomment the line corresponding to the desired System clock (SYSCLK)
+/// frequency (after reset the HSI is used as SYSCLK source)
+///
+/// IMPORTANT NOTE:
+/// ==============
+/// 1. After each device reset the HSI is used as System clock source.
+///
+/// 2. Please make sure that the selected System clock doesn't exceed your device's
+/// maximum frequency.
+///
+/// 3. If none of the define below is enabled, the HSI is used as System clock
+/// source.
+///
+/// 4. The System clock configuration functions provided within this file assume that:
+/// - For Low, Medium and High density Value line devices an external 8MHz
+/// crystal is used to drive the System clock.
+/// - For Low, Medium and High density devices an external 8MHz crystal is
+/// used to drive the System clock.
+/// - For Connectivity line devices an external 25MHz crystal is used to drive
+/// the System clock.
+/// If you are using different crystal you have to adapt those functions accordingly.
+
+//#define SYSCLK_FREQ_HSE    HSE_VALUE          //HSE_VALUE is define in reg_common.h
+//#define SYSCLK_FREQ_24MHz  (HSE_VALUE*3)      //24000000 based HSE_VALUE = 8000000
+//#define SYSCLK_FREQ_36MHz  (HSE_VALUE*9/2)    //36000000 based HSE_VALUE = 8000000
+//#define SYSCLK_FREQ_48MHz  (HSE_VALUE*6)      //48000000 based HSE_VALUE = 8000000
+//#define SYSCLK_FREQ_XXMHz  (HSE_VALUE*6)      //48000000 based HSE_VALUE = 8000000
+//#define SYSCLK_FREQ_XXMHz  (HSE_VALUE*9)      //72000000 based HSE_VALUE = 8000000
+//#define SYSCLK_FREQ_XXMHz  (HSE_VALUE*12)      //96000000 based HSE_VALUE = 8000000
+#define SYSCLK_FREQ_XXMHz (HSE_VALUE*12)       //120000000 based HSE_VALUE = 8000000
+
+#if defined(SYSCLK_FREQ_HSE) || defined(SYSCLK_FREQ_24MHz) || defined(SYSCLK_FREQ_36MHz) || defined(SYSCLK_FREQ_48MHz) || defined(SYSCLK_FREQ_XXMHz)
+
+#if defined(HSE_VALUE) && (!(HSE_VALUE == 8000000))
+#warning redefine HSE_VALUE in reg_common.h Line 48 and ignore this warning
+#endif
+
+#endif
+
+
+//#define SYSCLK_HSI_24MHz  24000000
+//#define SYSCLK_HSI_36MHz  36000000
+//#define SYSCLK_HSI_48MHz  48000000
+//#define SYSCLK_HSI_XXMHz  48000000
+//#define SYSCLK_HSI_XXMHz  72000000
+//#define SYSCLK_HSI_XXMHz  96000000
+#define SYSCLK_HSI_XXMHz  120000000
+/// Uncomment the following line if you need to relocate your vector Table in
+/// Internal SRAM.
+///#define VECT_TAB_SRAM
+#define VECT_TAB_OFFSET  0x0
+/// Vector Table base offset field.
+/// This value must be a multiple of 0x200.
+
+
+/// @}
+
+
+
+
+///////////////////////////////////////////////////////////////
+///Clock Definitions
+///////////////////////////////////////////////////////////////
+#if defined SYSCLK_FREQ_HSE
+u32 SystemCoreClock         = SYSCLK_FREQ_HSE;
+#elif defined SYSCLK_FREQ_24MHz
+u32 SystemCoreClock         = SYSCLK_FREQ_24MHz;
+#elif defined SYSCLK_FREQ_36MHz
+u32 SystemCoreClock         = SYSCLK_FREQ_36MHz;
+#elif defined SYSCLK_FREQ_48MHz
+u32 SystemCoreClock         = SYSCLK_FREQ_48MHz;
+#elif defined SYSCLK_FREQ_XXMHz
+u32 SystemCoreClock         = SYSCLK_FREQ_XXMHz;
+
+
+#elif defined SYSCLK_HSI_24MHz
+u32 SystemCoreClock         = SYSCLK_HSI_24MHz;
+#elif defined SYSCLK_HSI_36MHz
+u32 SystemCoreClock         = SYSCLK_HSI_36MHz;
+#elif defined SYSCLK_HSI_48MHz
+u32 SystemCoreClock         = SYSCLK_HSI_48MHz;
+#elif defined SYSCLK_HSI_XXMHz
+u32 SystemCoreClock         = SYSCLK_HSI_XXMHz;
+#else //HSI Selected as System Clock source 
+u32 SystemCoreClock         = HSI_VALUE;
+#endif
+
+__I u8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/// @}
+
+
+static void SetSysClock(void);
+
+#if defined SYSCLK_FREQ_HSE
+static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_XXMHz
+static void SetSysClockToXX(void);
+
+#elif defined SYSCLK_HSI_24MHz
+static void SetSysClockTo24_HSI(void);
+#elif defined SYSCLK_HSI_36MHz
+static void SetSysClockTo36_HSI(void);
+#elif defined SYSCLK_HSI_48MHz
+static void SetSysClockTo48_HSI(void);
+#elif defined SYSCLK_HSI_XXMHz
+static void SetSysClockToXX_HSI(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+static void SystemInit_ExtMemCtl(void);
+#endif //DATA_IN_ExtSRAM 
+
+
+/// @}
+
+
+
+/// @brief  Setup the microcontroller system
+///         Initialize the Embedded Flash Interface, the PLL and update the
+///         SystemCoreClock variable.
+/// @note   This function should be used only after reset.
+/// @param  None
+/// @retval None
+
+void SystemInit (void)
+{
+    //Reset the RCC clock configuration to the default reset state(for debug purpose)
+    //Set HSION bit
+    RCC->CR |= (u32)0x00000001;
+
+    //Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits
+    RCC->CFGR &= (u32)0xF8FFC00C;
+
+    //Reset HSEON, CSSON and PLLON bits
+    RCC->CR &= (u32)0xFEF6FFFF;
+
+    //Reset HSEBYP bit
+    RCC->CR &= (u32)0xFFFBFFFF;
+
+    //Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits
+    RCC->CFGR &= (u32)0xFF3CFFFF;
+    RCC->CR &= (u32)0x008FFFFF;
+
+    //Disable all interrupts and clear pending bits
+    RCC->CIR = 0x009F0000;
+    //Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers
+    //Configure the Flash Latency cycles and enable prefetch buffer
+    SetSysClock();
+}
+
+
+/// @brief  use to return the pllm&plln.
+/// @param  pllclkSourceFrq : PLL source clock frquency;
+///         pllclkFrq : Target PLL clock frquency;
+///         plln : PLL factor PLLN
+///         pllm : PLL factor PLLM
+/// @retval amount of error
+u32 AutoCalPllFactor(u32 pllclkSourceFrq, u32 pllclkFrq, u8* plln, u8* pllm)
+{
+    u32 n, m;
+    u32 tempFrq;
+    u32 minDiff = pllclkFrq;
+    u8  flag = 0;
+    for(m = 0; m < 4 ; m++) {
+        for(n = 0; n < 64 ; n++) {
+            tempFrq =  pllclkSourceFrq * (n + 1) / (m + 1);
+            tempFrq = (tempFrq >  pllclkFrq) ? (tempFrq - pllclkFrq) : (pllclkFrq - tempFrq) ;
+
+            if(minDiff > tempFrq) {
+                minDiff =  tempFrq;
+                *plln = n;
+                *pllm = m;
+            }
+            if(minDiff == 0) {
+                flag = 1;
+                break;
+            }
+        }
+        if(flag != 0) {
+            break;
+        }
+    }
+    return  minDiff;
+}
+static void DELAY_xUs(u32 count)
+{
+    u32 temp;
+    SysTick->CTRL = 0x0;                                                        //disable systick function
+    SysTick->LOAD = count * 8;                                                    //time count for 1us with HSI as SYSCLK
+    SysTick->VAL = 0x00;                                                        //clear counter
+    SysTick->CTRL = 0x5;                                                        //start discrease with Polling
+    do {
+        temp = SysTick->CTRL;
+    } while((temp & 0x01) && !(temp & (1 << 16)));                              //wait time count done
+    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;                                  //Close Counter
+    SysTick->VAL = 0X00;                                                        //clear counter
+}
+/// @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+/// @param  None
+/// @retval None
+
+static void SetSysClock(void)
+{
+    CACHE->CCR &= ~(0x3 << 3);
+    CACHE->CCR |= 1;
+    while((CACHE->SR & 0x3) != 2);
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+    SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+    SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+    SetSysClockTo48();
+#elif defined SYSCLK_FREQ_XXMHz
+    SetSysClockToXX();
+
+#elif defined SYSCLK_HSI_24MHz
+    SetSysClockTo24_HSI();
+#elif defined SYSCLK_HSI_36MHz
+    SetSysClockTo36_HSI();
+#elif defined SYSCLK_HSI_48MHz
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_HSI_XXMHz
+    SetSysClockToXX_HSI();
+#endif
+
+    //If none of the define above is enabled, the HSI is used as System clock
+    //source (default after reset)
+}
+
+#ifdef SYSCLK_FREQ_HSE
+
+/// @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+///         and PCLK1 prescalers.
+/// @note   This function should be used only after reset.
+/// @param  None
+/// @retval None
+
+static void SetSysClockToHSE(void)
+{
+    __IO u32 StartUpCounter = 0, HSEStatus = 0;
+    s32 i;
+
+    //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
+    //Enable HSE
+    RCC->CR |= ((u32)RCC_CR_HSEON);
+
+    //Wait till HSE is ready and if Time out is reached exit
+    do {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
+        HSEStatus = (u32)0x01;
+        i = 2000;
+        while(i--);
+    }
+    else {
+        HSEStatus = (u32)0x00;
+    }
+
+    if (HSEStatus == (u32)0x01) {
+        //Enable Prefetch Buffer
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+        //Flash 0 wait state ,bit0~2
+        FLASH->ACR &= ~0x07;
+        //HCLK = SYSCLK
+        RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
+
+        //PCLK2 = HCLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+        //PCLK1 = HCLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
+
+        //Select HSE as system clock source
+        RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+        RCC->CFGR |= (u32)RCC_CFGR_SW_HSE;
+
+        //Wait till HSE is used as system clock source
+        while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x04) {
+        }
+    }
+    else {
+        //If HSE fails to start-up, the application will have wrong clock
+        //configuration. User can add here some code to deal with this error
+    }
+}
+#elif defined SYSCLK_FREQ_24MHz
+
+/// @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
+///         and PCLK1 prescalers.
+/// @note   This function should be used only after reset.
+/// @param  None
+/// @retval None
+
+static void SetSysClockTo24(void)
+{
+    __IO u32 StartUpCounter = 0, HSEStatus = 0;
+    s32 i;
+
+    //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
+    //Enable HSE
+    RCC->CR |= ((u32)RCC_CR_HSEON);
+
+    //Wait till HSE is ready and if Time out is reached exit
+    do {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
+        HSEStatus = (u32)0x01;
+        i = 2000;
+        while(i--);
+    }
+    else {
+        HSEStatus = (u32)0x00;
+    }
+
+    if (HSEStatus == (u32)0x01) {
+        //Enable Prefetch Buffer
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+        //Flash 0 wait state ,bit0~2
+        FLASH->ACR &= ~0x07;
+        FLASH->ACR |= 0x01;
+        //HCLK = SYSCLK
+        RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
+
+        //PCLK2 = HCLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+        //PCLK1 = HCLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
+
+        // PLL configuration:  = (HSE ) * (2+1) = 24 MHz
+        RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+        RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
+
+        RCC->APB1ENR |= RCC_APB1ENR_PWR;
+        RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+        RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos));
+        //Enable PLL
+        RCC->CR |= RCC_CR_PLLON;
+
+        //Wait till PLL is ready
+        while((RCC->CR & RCC_CR_PLLRDY) == 0) {
+        }
+
+        //Select PLL as system clock source
+        RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+        RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
+
+        //Wait till PLL is used as system clock source
+        while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
+        }
+    }
+    else {
+        //If HSE fails to start-up, the application will have wrong clock
+        //configuration. User can add here some code to deal with this error
+    }
+}
+#elif defined SYSCLK_FREQ_36MHz
+
+/// @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
+///         and PCLK1 prescalers.
+/// @note   This function should be used only after reset.
+/// @param  None
+/// @retval None
+
+static void SetSysClockTo36(void)
+{
+    s32 i;
+    __IO u32 StartUpCounter = 0, HSEStatus = 0;
+
+    //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
+    //Enable HSE
+    RCC->CR |= ((u32)RCC_CR_HSEON);
+
+    //Wait till HSE is ready and if Time out is reached exit
+    do {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
+        HSEStatus = (u32)0x01;
+        i = 2000;
+        while(i--);
+    }
+    else {
+        HSEStatus = (u32)0x00;
+    }
+
+    if (HSEStatus == (u32)0x01) {
+        //Enable Prefetch Buffer
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+        //Flash 0 wait state ,bit0~2
+        FLASH->ACR &= ~0x07;
+        FLASH->ACR |= 0x01;
+        //HCLK = SYSCLK
+        RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
+
+        //PCLK2 = HCLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+        //PCLK1 = HCLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
+        RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+        RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
+
+        RCC->APB1ENR |= RCC_APB1ENR_PWR;
+        RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+        RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos));
+        //Enable PLL
+        RCC->CR |= RCC_CR_PLLON;
+
+        //Wait till PLL is ready
+        while((RCC->CR & RCC_CR_PLLRDY) == 0) {
+        }
+
+        //Select PLL as system clock source
+        RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+        RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
+
+        //Wait till PLL is used as system clock source
+        while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
+        }
+    }
+    else {
+        //If HSE fails to start-up, the application will have wrong clock
+        //configuration. User can add here some code to deal with this error
+    }
+}
+#elif defined SYSCLK_FREQ_48MHz
+
+/// @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
+///         and PCLK1 prescalers.
+/// @note   This function should be used only after reset.
+/// @param  None
+/// @retval None
+
+static void SetSysClockTo48(void)
+{
+    __IO u32 StartUpCounter = 0, HSEStatus = 0;
+    s32 i;
+    //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
+    //Enable HSE
+    RCC->CR |= ((u32)RCC_CR_HSEON);
+
+    //Wait till HSE is ready and if Time out is reached exit
+    do {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
+        HSEStatus = (u32)0x01;
+        i = 2000;
+        while(i--);
+    }
+    else {
+        HSEStatus = (u32)0x00;
+    }
+
+    if (HSEStatus == (u32)0x01) {
+        //Enable Prefetch Buffer
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+        //Flash 0 wait state ,bit0~2
+        FLASH->ACR &= ~0x07;
+        FLASH->ACR |= 0x02;
+        //HCLK = SYSCLK
+        RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
+
+        //PCLK2 = HCLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+        //PCLK1 = HCLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
+
+        // PLL configuration:  = (HSE ) * (5+1) = 48MHz
+        RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+        RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
+
+        RCC->APB1ENR |= RCC_APB1ENR_PWR;
+        RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+        RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos));
+        //Enable PLL
+        RCC->CR |= RCC_CR_PLLON;
+
+        //Wait till PLL is ready
+        while((RCC->CR & RCC_CR_PLLRDY) == 0) {
+        }
+
+        //Select PLL as system clock source
+        RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+        RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
+
+        //Wait till PLL is used as system clock source
+        while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
+        }
+    }
+    else {
+        //If HSE fails to start-up, the application will have wrong clock
+        //configuration. User can add here some code to deal with this error
+    }
+}
+#elif defined SYSCLK_FREQ_XXMHz
+
+/// @brief  Sets System clock frequency to XXMHz and configure HCLK, PCLK2
+///         and PCLK1 prescalers.
+/// @note   This function should be used only after reset.
+/// @param  None
+/// @retval None
+
+static void SetSysClockToXX(void)
+{
+    __IO u32 temp, tn, tm;//j,
+    __IO u32 StartUpCounter = 0, HSEStatus = 0;
+
+    u8 plln, pllm;
+
+    RCC->CR |= RCC_CR_HSION;
+    while(!(RCC->CR & RCC_CR_HSIRDY));
+    //PLL SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
+    //Enable HSE
+    RCC->CR |= ((u32)RCC_CR_HSEON);
+
+    DELAY_xUs(5);
+
+    if(SystemCoreClock > 96000000) {
+        RCC->APB1ENR |= RCC_APB1ENR_PWR;
+        PWR->CR &= ~(3 << 14);
+        PWR->CR |= 3 << 14;
+    }
+    //Wait till HSE is ready and if Time out is reached exit
+    while(1) {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        if(HSEStatus != 0)
+            break;
+        StartUpCounter++;
+        if(StartUpCounter >= (10 * HSE_STARTUP_TIMEOUT))
+            return;
+    }
+
+    if ((RCC->CR & RCC_CR_HSERDY) == RESET) {
+        //If HSE fails to start-up, the application will have wrong clock
+        //configuration. User can add here some code to deal with this error
+        HSEStatus = (u32)0x00;
+        return;
+    }
+
+    HSEStatus = (u32)0x01;
+    DELAY_xUs(5);
+
+    SystemCoreClock         = SYSCLK_FREQ_XXMHz;
+    //Enable Prefetch Buffer
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+    //Flash 0 wait state ,bit0~2
+    FLASH->ACR &= ~FLASH_ACR_LATENCY;
+    temp = (SystemCoreClock - 1) / 24000000;
+    FLASH->ACR |= (temp & FLASH_ACR_LATENCY);
+    RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2);
+
+    //HCLK = AHB = FCLK = SYSCLK divided by 4
+    RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4;
+
+    //PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK
+    RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+    if(SystemCoreClock > 72000000) {
+        //PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4;
+    }
+    else if(SystemCoreClock > 36000000) {
+        //PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
+    }
+
+    AutoCalPllFactor(HSE_VALUE, SystemCoreClock, &plln, &pllm);
+
+    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+    RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
+
+    tm = (((u32)pllm) & 0x07);
+    tn = (((u32)plln) & 0x7F);
+
+    RCC->APB1ENR |= RCC_APB1ENR_PWR;
+    RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+    RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos));
+    //Enable PLL
+    RCC->CR |= RCC_CR_PLLON;
+    //Wait till PLL is ready
+    while((RCC->CR & RCC_CR_PLLRDY) == 0) {
+        __ASM ("nop") ;//__NOP();
+    }
+    //Select PLL as system clock source
+    RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+    RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
+
+    //Wait till PLL is used as system clock source
+    while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) {
+        __ASM ("nop") ;//__NOP();
+    }
+
+    DELAY_xUs(1);
+    // set HCLK = AHB = FCLK = SYSCLK divided by 2
+    RCC->CFGR &= (~(RCC_CFGR_PPRE_0));
+    DELAY_xUs(1);
+
+    // set HCLK = AHB = FCLK = SYSCLK divided by 1
+    RCC->CFGR &= (~(RCC_CFGR_PPRE_3));
+
+    DELAY_xUs(1);
+
+}
+#elif defined SYSCLK_HSI_24MHz
+void SetSysClockTo24_HSI(void)
+{
+    u8 temp = 0;
+
+    RCC->CR |= RCC_CR_HSION;
+
+    while(!(RCC->CR & RCC_CR_HSIRDY));
+    FLASH->ACR = FLASH_ACR_PRFTBE;
+
+    RCC->CFGR = RCC_CFGR_PPRE1_2;
+    // PLL configuration:  = (HSI = 8M ) * (2+1)/(0+1) = 24 MHz
+    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+    RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
+
+    RCC->APB1ENR |= RCC_APB1ENR_PWR;
+    RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+    RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos));
+
+
+    RCC->CR |= RCC_CR_PLLON;
+
+    while(!(RCC->CR & RCC_CR_PLLRDY));
+
+    RCC->CFGR &= ~RCC_CFGR_SW;
+
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    while(temp != 0x02) {
+        temp = RCC->CFGR >> 2;
+        temp &= 0x03;
+    }
+}
+
+#elif defined SYSCLK_HSI_36MHz
+void SetSysClockTo36_HSI(void)
+{
+    u8 temp = 0;
+
+    RCC->CR |= RCC_CR_HSION;
+
+    while(!(RCC->CR & RCC_CR_HSIRDY));
+    FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE;
+    RCC->CFGR = RCC_CFGR_PPRE1_2;
+    // PLL configuration:  = (HSI = 8M ) * (8+1)/(1+1) = 36 MHz
+    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+    RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
+
+    RCC->APB1ENR |= RCC_APB1ENR_PWR;
+    RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+    RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos));
+
+    RCC->CR |= RCC_CR_PLLON;
+
+    while(!(RCC->CR & RCC_CR_PLLRDY));
+
+    RCC->CFGR &= ~ RCC_CFGR_SW;
+
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    while(temp != 0x02) {
+        temp = RCC->CFGR >> 2;
+        temp &= 0x03;
+    }
+}
+
+#elif defined SYSCLK_HSI_48MHz
+void SetSysClockTo48_HSI(void)
+{
+    u8 temp = 0;
+
+    RCC->CR |= RCC_CR_HSION;
+
+    while(!(RCC->CR & RCC_CR_HSIRDY));
+    FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE;
+    RCC->CFGR = RCC_CFGR_PPRE1_2;
+
+
+
+
+
+    // PLL configuration:  = (HSI = 8M ) * (5+1)/(0+1) = 36 MHz
+    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+    RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
+
+    RCC->APB1ENR |= RCC_APB1ENR_PWR;
+    RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+    RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos));
+
+    RCC->CR |= RCC_CR_PLLON;
+
+    while(!(RCC->CR & RCC_CR_PLLRDY));
+
+    RCC->CFGR &= ~RCC_CFGR_SW;
+
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    while(temp != 0x02) {
+        temp = RCC->CFGR >> 2;
+        temp &= 0x03;
+    }
+}
+#elif defined SYSCLK_HSI_XXMHz
+
+
+static void SetSysClockToXX_HSI(void)
+{
+    __IO u32 temp, tn, tm;
+    u8 plln, pllm;
+
+    RCC->CR |= RCC_CR_HSION;
+    while(!(RCC->CR & RCC_CR_HSIRDY));
+
+    if(SystemCoreClock > 96000000) {
+        RCC->APB1ENR |= RCC_APB1ENR_PWR;
+        PWR->CR &= ~(3 << 14);
+        PWR->CR |= 3 << 14;
+    }
+
+
+
+    SystemCoreClock         = SYSCLK_HSI_XXMHz;
+    //Enable Prefetch Buffer
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+    //Flash 0 wait state ,bit0~2
+    FLASH->ACR &= ~FLASH_ACR_LATENCY;
+
+    temp = (SystemCoreClock - 1) / 24000000;
+
+    FLASH->ACR |= (temp & FLASH_ACR_LATENCY);
+
+
+    RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2);
+    //HCLK = AHB = FCLK = SYSCLK divided by 4
+    RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4;
+
+    //PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK
+    RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
+
+    if(SystemCoreClock > 72000000) {
+        //PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4;
+    }
+    else if(SystemCoreClock > 36000000) {
+        //PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK
+        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
+    }
+
+
+
+    AutoCalPllFactor(HSI_VALUE_PLL_ON, SystemCoreClock, &plln, &pllm);
+
+    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
+    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC);
+
+    tm = (((u32)pllm) & 0x07);
+    tn = (((u32)plln) & 0x7F);
+
+    RCC->APB1ENR |= RCC_APB1ENR_PWR;
+    RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
+    RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos));
+    //Enable PLL
+    RCC->CR |= RCC_CR_PLLON;
+    //Wait till PLL is ready
+    while((RCC->CR & RCC_CR_PLLRDY) == 0) {
+        __ASM ("nop") ;//__NOP();
+    }
+    //Select PLL as system clock source
+    RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
+    RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
+
+    //Wait till PLL is used as system clock source
+    while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) {
+        __ASM ("nop") ;//__NOP();
+    }
+
+    DELAY_xUs(1);
+    // set HCLK = AHB = FCLK = SYSCLK divided by 2
+    RCC->CFGR &= (~(RCC_CFGR_PPRE_0));
+    DELAY_xUs(1);
+
+    // set HCLK = AHB = FCLK = SYSCLK divided by 1
+    RCC->CFGR &= (~(RCC_CFGR_PPRE_3));
+
+    DELAY_xUs(1);
+
+}
+
+#endif
+
+
+
+/// @}
+
+
+
+/// @}
+
+
+
+/// @}
+
+
+
diff --git a/src/portable/mm32/dcd_mm32f327x_otg.c b/src/portable/mm32/dcd_mm32f327x_otg.c
new file mode 100644
index 000000000..914bbb38c
--- /dev/null
+++ b/src/portable/mm32/dcd_mm32f327x_otg.c
@@ -0,0 +1,462 @@
+////////////////////////////////////////////////////////////////////////////////
+/// @file     dcd_mm32f327x_otg.c
+/// @author   SE TEAM
+/// @brief    tinyusb driver.
+////////////////////////////////////////////////////////////////////////////////
+/// @attention
+///
+/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
+/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
+/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
+/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
+/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
+/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
+///
+/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
+////////////////////////////////////////////////////////////////////////////////
+
+#include "tusb_option.h"
+#include "reg_usb_otg_fs.h"
+#include "mm32_device.h"
+#include "hal_conf.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MM32F327X )
+
+#include "device/dcd.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+enum {
+  TOK_PID_OUT   = 0x1u,
+  TOK_PID_IN    = 0x9u,
+  TOK_PID_SETUP = 0xDu,
+};
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t head;
+    struct {
+      union {
+        struct {
+          uint16_t          :  2;
+          uint16_t tok_pid  :  4;
+          uint16_t data     :  1;
+          uint16_t own      :  1;
+          uint16_t          :  8;
+        };
+        struct {
+          uint16_t          :  2;
+          uint16_t bdt_stall:  1;
+          uint16_t dts      :  1;
+          uint16_t ninc     :  1;
+          uint16_t keep     :  1;
+          uint16_t          : 10;
+        };
+      };
+      uint16_t bc          : 10;
+      uint16_t             :  6;
+    };
+  };
+  uint8_t *addr;
+}buffer_descriptor_t;
+
+TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t state;
+    struct {
+      uint32_t max_packet_size :11;
+      uint32_t                 : 5;
+      uint32_t odd             : 1;
+      uint32_t                 :15;
+    };
+  };
+  uint16_t length;
+  uint16_t remaining;
+}endpoint_state_t;
+
+TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
+
+typedef struct
+{
+  union {
+    /* [#EP][OUT,IN][EVEN,ODD] */
+    buffer_descriptor_t bdt[16][2][2];
+    uint16_t            bda[512];
+  };
+  TU_ATTR_ALIGNED(4) union {
+    endpoint_state_t endpoint[16][2];
+    endpoint_state_t endpoint_unified[16 * 2];
+  };
+  uint8_t setup_packet[8];
+  uint8_t addr;
+}dcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+// BDT(Buffer Descriptor Table) must be 256-byte aligned
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
+
+TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
+
+static void prepare_next_setup_packet(uint8_t rhport)
+{
+  const unsigned out_odd = _dcd.endpoint[0][0].odd;
+  const unsigned in_odd  = _dcd.endpoint[0][1].odd;
+  if (_dcd.bdt[0][0][out_odd].own) {
+    TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd);
+    return;
+  }
+  _dcd.bdt[0][0][out_odd].data     = 0;
+  _dcd.bdt[0][0][out_odd ^ 1].data = 1;
+  _dcd.bdt[0][1][in_odd].data      = 1;
+  _dcd.bdt[0][1][in_odd ^ 1].data  = 0;
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
+                _dcd.setup_packet, sizeof(_dcd.setup_packet));
+}
+
+static void process_stall(uint8_t rhport)
+{
+  if (USB_OTG_FS->EP_CTL[0] & USB_ENDPT_EPSTALL_MASK) {
+    /* clear stall condition of the control pipe */
+    prepare_next_setup_packet(rhport);
+    USB_OTG_FS->EP_CTL[0] &= ~USB_ENDPT_EPSTALL_MASK;
+  }
+}
+
+static void process_tokdne(uint8_t rhport)
+{
+  const unsigned s = USB_OTG_FS->STAT;
+  USB_OTG_FS->INT_STAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
+  buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
+  endpoint_state_t    *ep = &_dcd.endpoint_unified[s >> 3];
+  unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0;
+
+  /* fetch pid before discarded by the next steps */
+  const unsigned pid = bd->tok_pid;
+  /* reset values for a next transfer */
+  bd->bdt_stall = 0;
+  bd->dts       = 1;
+  bd->ninc      = 0;
+  bd->keep      = 0;
+  /* update the odd variable to prepare for the next transfer */
+  ep->odd       = odd ^ 1;
+  if (pid == TOK_PID_SETUP) {
+    dcd_event_setup_received(rhport, bd->addr, true);
+    USB_OTG_FS->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+    return;
+  }
+  if (s >> 4) {
+    TU_LOG1("TKDNE %x\r\n", s);
+  }
+
+  const unsigned bc = bd->bc;
+  const unsigned remaining = ep->remaining - bc;
+  if (remaining && bc == ep->max_packet_size) {
+    /* continue the transferring consecutive data */
+    ep->remaining = remaining;
+    const int next_remaining = remaining - ep->max_packet_size;
+    if (next_remaining > 0) {
+      /* prepare to the after next transfer */
+      bd->addr += ep->max_packet_size * 2;
+      bd->bc    = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
+      __DSB();
+      bd->own   = 1; /* the own bit must set after addr */
+    }
+    return;
+  }
+  const unsigned length = ep->length;
+  dcd_event_xfer_complete(rhport,
+                          ((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT),
+                          length - remaining, XFER_RESULT_SUCCESS, true);
+  if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) {
+    /* After completion a ZLP of control transfer,
+     * it prepares for the next steup transfer. */
+    if (_dcd.addr) {
+      /* When the transfer was the SetAddress,
+       * the device address should be updated here. */
+      USB_OTG_FS->ADDR = _dcd.addr;
+      _dcd.addr  = 0;
+    }
+    prepare_next_setup_packet(rhport);
+  }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+  USB_OTG_FS->CTL     |= USB_CTL_ODDRST_MASK;
+  USB_OTG_FS->ADDR     = 0;
+  USB_OTG_FS->INT_ENB    = (USB_OTG_FS->INT_ENB & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
+
+  USB_OTG_FS->EP_CTL[0] = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
+  for (unsigned i = 1; i < 16; ++i) {
+    USB_OTG_FS->EP_CTL[i] = 0;
+  }
+  buffer_descriptor_t *bd = _dcd.bdt[0][0];
+  for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
+    bd->head = 0;
+  }
+  const endpoint_state_t ep0 = {
+    .max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
+    .odd             = 0,
+    .length          = 0,
+    .remaining       = 0,
+  };
+  _dcd.endpoint[0][0] = ep0;
+  _dcd.endpoint[0][1] = ep0;
+  tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
+  _dcd.addr = 0;
+  prepare_next_setup_packet(rhport);
+  USB_OTG_FS->CTL &= ~USB_CTL_ODDRST_MASK;
+  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+}
+
+static void process_bus_inactive(uint8_t rhport)
+{
+  (void) rhport;
+  const unsigned inten = USB_OTG_FS->INT_ENB;
+  USB_OTG_FS->INT_ENB    = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
+  dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+}
+
+static void process_bus_active(uint8_t rhport)
+{
+  (void) rhport;
+  const unsigned inten = USB_OTG_FS->INT_ENB;
+  USB_OTG_FS->INT_ENB    = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
+  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+void dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  tu_memclr(&_dcd, sizeof(_dcd));
+  USB_OTG_FS->BDT_PAGE_01 = (uint8_t)((uintptr_t)_dcd.bdt >>  8);
+  USB_OTG_FS->BDT_PAGE_02 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
+  USB_OTG_FS->BDT_PAGE_03 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
+
+  dcd_connect(rhport);
+  NVIC_ClearPendingIRQ(USB_FS_IRQn);
+}
+#define USB_DEVICE_INTERRUPT_PRIORITY (3U)
+void dcd_int_enable(uint8_t rhport)
+{
+  uint8_t irqNumber;
+  irqNumber = USB_FS_IRQn;
+  (void) rhport;
+  USB_OTG_FS->INT_ENB = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK |
+    USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
+  NVIC_SetPriority((IRQn_Type)irqNumber, USB_DEVICE_INTERRUPT_PRIORITY);
+  NVIC_EnableIRQ(USB_FS_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB_FS_IRQn);
+  USB_OTG_FS->INT_ENB = 0;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+  _dcd.addr = dev_addr & 0x7F;
+  /* Response with status first before changing device address */
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+extern u32 SystemCoreClock ;
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+  unsigned cnt = SystemCoreClock / 100;
+  USB_OTG_FS->CTL |= USB_CTL_RESUME_MASK;
+  while (cnt--) __NOP();
+  USB_OTG_FS->CTL &= ~USB_CTL_RESUME_MASK;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  USB_OTG_FS->CTL     |= USB_CTL_USBENSOFEN_MASK;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  (void) rhport;
+  USB_OTG_FS->CTL      = 0;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+
+  const unsigned ep_addr  = ep_desc->bEndpointAddress;
+  const unsigned epn      = ep_addr & 0xFu;
+  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned xfer     = ep_desc->bmAttributes.xfer;
+  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
+  const unsigned odd      = ep->odd;
+  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
+
+  /* No support for control transfer */
+  TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
+
+  ep->max_packet_size = ep_desc->wMaxPacketSize.size;
+  unsigned val = USB_ENDPT_EPCTLDIS_MASK;
+  val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
+  val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+  USB_OTG_FS->EP_CTL[epn] |= val;
+
+  if (xfer != TUSB_XFER_ISOCHRONOUS) {
+    bd[odd].dts      = 1;
+    bd[odd].data     = 0;
+    bd[odd ^ 1].dts  = 1;
+    bd[odd ^ 1].data = 1;
+  }
+
+  return true;
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  const unsigned epn      = ep_addr & 0xFu;
+  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
+  const unsigned msk      = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+  USB_OTG_FS->EP_CTL[epn] &= ~msk;
+  ep->max_packet_size = 0;
+  ep->length          = 0;
+  ep->remaining       = 0;
+  bd->head            = 0;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB_FS_IRQn);
+  const unsigned epn = ep_addr & 0xFu;
+  const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
+
+  if (bd->own) {
+    TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head);
+    return false; /* The last transfer has not completed */
+  }
+  ep->length    = total_bytes;
+  ep->remaining = total_bytes;
+
+  const unsigned mps = ep->max_packet_size;
+  if (total_bytes > mps) {
+    buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
+    /* When total_bytes is greater than the max packet size,
+     * it prepares to the next transfer to avoid NAK in advance. */
+    next->bc   = total_bytes >= 2 * mps ? mps: total_bytes - mps;
+    next->addr = buffer + mps;
+    next->own  = 1;
+  }
+  bd->bc        = total_bytes >= mps ? mps: total_bytes;
+  bd->addr      = buffer;
+  __DSB();
+  bd->own  = 1; /* the own bit must set after addr */
+  NVIC_EnableIRQ(USB_FS_IRQn);
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  const unsigned epn = ep_addr & 0xFu;
+  if (0 == epn) {
+    USB_OTG_FS->EP_CTL[epn] |=  USB_ENDPT_EPSTALL_MASK;
+  } else {
+    const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+    buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+    bd[0].bdt_stall = 1;
+    bd[1].bdt_stall = 1;
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  const unsigned epn      = ep_addr & 0xFu;
+  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned odd      = _dcd.endpoint[epn][dir].odd;
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+
+  bd[odd ^ 1].own       = 0;
+  bd[odd ^ 1].data      = 1;
+  bd[odd ^ 1].bdt_stall = 0;
+  bd[odd].own           = 0;
+  bd[odd].data          = 0;
+  bd[odd].bdt_stall     = 0;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_int_handler(uint8_t rhport)
+{
+  (void) rhport;
+
+  uint32_t is  = USB_OTG_FS->INT_STAT;
+  uint32_t msk = USB_OTG_FS->INT_ENB;
+  USB_OTG_FS->INT_STAT = is & ~msk;
+  is &= msk;
+  if (is & USB_ISTAT_ERROR_MASK) {
+    /* TODO: */
+    uint32_t es = USB_OTG_FS->ERR_STAT;
+    USB_OTG_FS->ERR_STAT = es;
+    USB_OTG_FS->INT_STAT   = is; /* discard any pending events */
+    return;
+  }
+
+  if (is & USB_ISTAT_USBRST_MASK) {
+    USB_OTG_FS->INT_STAT = is; /* discard any pending events */
+    process_bus_reset(rhport);
+    return;
+  }
+  if (is & USB_ISTAT_SLEEP_MASK) {
+    USB_OTG_FS->INT_STAT = USB_ISTAT_SLEEP_MASK;
+    process_bus_inactive(rhport);
+    return;
+  }
+  if (is & USB_ISTAT_RESUME_MASK) {
+    USB_OTG_FS->INT_STAT = USB_ISTAT_RESUME_MASK;
+    process_bus_active(rhport);
+    return;
+  }
+  if (is & USB_ISTAT_SOFTOK_MASK) {
+    USB_OTG_FS->INT_STAT = USB_ISTAT_SOFTOK_MASK;
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+    return;
+  }
+  if (is & USB_ISTAT_STALL_MASK) {
+    USB_OTG_FS->INT_STAT = USB_ISTAT_STALL_MASK;
+    process_stall(rhport);
+    return;
+  }
+  if (is & USB_ISTAT_TOKDNE_MASK) {
+    process_tokdne(rhport);
+    return;
+  }
+}
+
+#endif

From 373b977cc3b0bbb0144429d52d4ad6132b8319e2 Mon Sep 17 00:00:00 2001
From: zhangslice <1304224508@qq.com>
Date: Wed, 2 Jun 2021 09:54:21 +0800
Subject: [PATCH 0083/2085] add keil projrct Signed-off-by: zhangslice
 <1304224508@qq.com>

---
 tinyusb_keil.zip | Bin 0 -> 1001190 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 tinyusb_keil.zip

diff --git a/tinyusb_keil.zip b/tinyusb_keil.zip
new file mode 100644
index 0000000000000000000000000000000000000000..6b178fcfc3c8d45f0b6515d2311d571bce2ccb69
GIT binary patch
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HcmV?d00001


From b8ac5f12872a97ccb1fa81fdc028ab91947fb217 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Jun 2021 13:32:00 +0700
Subject: [PATCH 0084/2085] add mindmotion mm32sdk as submodule

remove the local copy of mm32
---
 .../CMSIS/IAR_Core/arm_common_tables.h        |  121 -
 .../CMSIS/IAR_Core/arm_const_structs.h        |   66 -
 .../mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h  | 7122 -----------------
 .../mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h    |  796 --
 .../mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h | 1735 ----
 .../mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h |  231 -
 .../mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h | 1900 -----
 .../mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h  | 1813 -----
 .../mm32f327x/CMSIS/IAR_Core/core_armv8mml.h  | 2821 -------
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h  |  850 --
 .../mm32f327x/CMSIS/IAR_Core/core_cm0plus.h   |  975 ---
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h | 1813 -----
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h  | 1880 -----
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h | 2821 -------
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h  | 2061 -----
 .../mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h  | 2592 ------
 .../mm32f327x/CMSIS/IAR_Core/core_sc000.h     |  976 ---
 .../mm32f327x/CMSIS/IAR_Core/core_sc300.h     | 1851 -----
 .../mm32f327x/CMSIS/IAR_Core/tz_context.h     |   69 -
 .../CMSIS/KEIL_Core/arm_common_tables.h       |  121 -
 .../CMSIS/KEIL_Core/arm_const_structs.h       |   66 -
 .../mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h | 7122 -----------------
 .../mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h   |  796 --
 .../CMSIS/KEIL_Core/cmsis_armclang.h          | 1735 ----
 .../CMSIS/KEIL_Core/cmsis_compiler.h          |  231 -
 .../mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h     | 1900 -----
 .../mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h | 1813 -----
 .../mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h | 2821 -------
 .../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h |  850 --
 .../mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h  |  975 ---
 .../mm32f327x/CMSIS/KEIL_Core/core_cm23.h     | 1813 -----
 .../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h | 1880 -----
 .../mm32f327x/CMSIS/KEIL_Core/core_cm33.h     | 2821 -------
 .../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h | 2061 -----
 .../mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h | 2592 ------
 .../mm32f327x/CMSIS/KEIL_Core/core_sc000.h    |  976 ---
 .../mm32f327x/CMSIS/KEIL_Core/core_sc300.h    | 1851 -----
 .../mm32f327x/CMSIS/KEIL_Core/tz_context.h    |   69 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h   |   33 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h |  341 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h |  130 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h |  340 -
 .../MM32F327x/HAL_Lib/Inc/hal_comp.h          |  228 -
 .../MM32F327x/HAL_Lib/Inc/hal_conf.h          |   62 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h |   84 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h |   46 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h |  166 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h |   72 -
 .../MM32F327x/HAL_Lib/Inc/hal_device.h        |   41 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h |  306 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h |  729 --
 .../MM32F327x/HAL_Lib/Inc/hal_eth_conf.h      |   68 -
 .../MM32F327x/HAL_Lib/Inc/hal_exti.h          |  181 -
 .../MM32F327x/HAL_Lib/Inc/hal_flash.h         |  230 -
 .../MM32F327x/HAL_Lib/Inc/hal_fsmc.h          |  147 -
 .../MM32F327x/HAL_Lib/Inc/hal_gpio.h          |  198 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h |  255 -
 .../MM32F327x/HAL_Lib/Inc/hal_iwdg.h          |  130 -
 .../MM32F327x/HAL_Lib/Inc/hal_misc.h          |  128 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h |  156 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h |  329 -
 .../MM32F327x/HAL_Lib/Inc/hal_redefine.h      |  102 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h |  114 -
 .../MM32F327x/HAL_Lib/Inc/hal_sdio.h          |  503 --
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h |  351 -
 .../MM32F327x/HAL_Lib/Inc/hal_syscfg.h        |   83 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h |  755 --
 .../MM32F327x/HAL_Lib/Inc/hal_uart.h          |  211 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h |   71 -
 .../mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h |   89 -
 .../MM32F327x/HAL_Lib/Inc/hal_wwdg.h          |   90 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c |  563 --
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c |  231 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c |  696 --
 .../MM32F327x/HAL_Lib/Src/hal_comp.c          |  226 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c |  108 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c |   43 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c |  184 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c |   53 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c |  319 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c |  836 --
 .../MM32F327x/HAL_Lib/Src/hal_exti.c          |  222 -
 .../MM32F327x/HAL_Lib/Src/hal_flash.c         |  548 --
 .../MM32F327x/HAL_Lib/Src/hal_fsmc.c          |  124 -
 .../MM32F327x/HAL_Lib/Src/hal_gpio.c          |  344 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c |  526 --
 .../MM32F327x/HAL_Lib/Src/hal_iwdg.c          |  208 -
 .../MM32F327x/HAL_Lib/Src/hal_misc.c          |  147 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c |  215 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c |  995 ---
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c |  234 -
 .../MM32F327x/HAL_Lib/Src/hal_sdio.c          |  527 --
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c |  648 --
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c | 1875 -----
 .../MM32F327x/HAL_Lib/Src/hal_uart.c          |  502 --
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c |   55 -
 .../mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c |  131 -
 .../MM32F327x/HAL_Lib/Src/hal_wwdg.c          |  147 -
 .../mm32f327x/MM32F327x/Include/mm32_device.h |   23 -
 .../mm32f327x/MM32F327x/Include/mm32_reg.h    |   71 -
 .../MM32F327x/Include/mm32_reg_redefine_v1.h  | 1175 ---
 .../mm32f327x/MM32F327x/Include/reg_adc.h     |  953 ---
 .../mm32f327x/MM32F327x/Include/reg_bkp.h     |  147 -
 .../mm32f327x/MM32F327x/Include/reg_can.h     |  532 --
 .../mm32f327x/MM32F327x/Include/reg_common.h  |  643 --
 .../mm32f327x/MM32F327x/Include/reg_comp.h    |  228 -
 .../mm32f327x/MM32F327x/Include/reg_crc.h     |  102 -
 .../mm32f327x/MM32F327x/Include/reg_crs.h     |  152 -
 .../mm32f327x/MM32F327x/Include/reg_dac.h     |  247 -
 .../mm32f327x/MM32F327x/Include/reg_dbg.h     |  113 -
 .../mm32f327x/MM32F327x/Include/reg_dma.h     |  325 -
 .../mm32f327x/MM32F327x/Include/reg_eth.h     |  730 --
 .../mm32f327x/MM32F327x/Include/reg_exti.h    |  544 --
 .../mm32f327x/MM32F327x/Include/reg_flash.h   |  290 -
 .../mm32f327x/MM32F327x/Include/reg_fsmc.h    |  194 -
 .../mm32f327x/MM32F327x/Include/reg_gpio.h    |  706 --
 .../mm32f327x/MM32F327x/Include/reg_i2c.h     |  635 --
 .../mm32f327x/MM32F327x/Include/reg_iwdg.h    |  125 -
 .../mm32f327x/MM32F327x/Include/reg_pwm.h     |   72 -
 .../mm32f327x/MM32F327x/Include/reg_pwr.h     |  219 -
 .../mm32f327x/MM32F327x/Include/reg_rcc.h     |  654 --
 .../mm32f327x/MM32F327x/Include/reg_rtc.h     |  203 -
 .../mm32f327x/MM32F327x/Include/reg_sdio.h    |  391 -
 .../mm32f327x/MM32F327x/Include/reg_spi.h     |  359 -
 .../mm32f327x/MM32F327x/Include/reg_syscfg.h  |  299 -
 .../mm32f327x/MM32F327x/Include/reg_tim.h     |  681 --
 .../mm32f327x/MM32F327x/Include/reg_uart.h    |  362 -
 .../MM32F327x/Include/reg_usb_otg_fs.h        |  923 ---
 .../mm32f327x/MM32F327x/Include/reg_wwdg.h    |  133 -
 .../mm32/mm32f327x/MM32F327x/Include/types.h  |  105 -
 .../GCC_StartAsm/startup_mm32m3ux_u_gcc.S     |  440 -
 .../MM32F327x/Source/system_mm32f327x.c       |  866 --
 132 files changed, 96104 deletions(-)
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h
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 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
 delete mode 100644 hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c

diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h
deleted file mode 100644
index dfea7460e..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_common_tables.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_common_tables.h
- * Description:  Extern declaration for common tables
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
-#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
-#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
-#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
-#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
-#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
-#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
-#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /*  ARM_COMMON_TABLES_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h
deleted file mode 100644
index 84ffe8b85..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_const_structs.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_const_structs.h
- * Description:  Constant structs that are initialized for user convenience.
- *               For example, some can be given as arguments to the arm_cfft_f32() function.
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h
deleted file mode 100644
index 9d678052b..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/arm_math.h
+++ /dev/null
@@ -1,7122 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_math.h
- * Description:  Public header file for CMSIS DSP Library
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * Introduction
-   * ------------
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * Using the Library
-   * ------------
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
-   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
-   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
-   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
-   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
-   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
-   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
-   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
-   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
-   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
-   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
-   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
-   * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
-   * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
-   * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
-   * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
-   * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
-   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
-   * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
-   * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
-   *
-   *
-   * Examples
-   * --------
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * Toolchain Support
-   * ------------
-   *
-   * The library has been developed and tested with MDK-ARM version 5.14.0.0
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * Building the Library
-   * ------------
-   *
-   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
-   * - arm_cortexM_math.uvprojx
-   *
-   *
-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
-   *
-   * Pre-processor Macros
-   * ------------
-   *
-   * Each library project have differant pre-processor macros.
-   *
-   * - UNALIGNED_SUPPORT_DISABLE:
-   *
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_CMx:
-   *
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
-   * ARM_MATH_CM7 for building the library on cortex-M7.
-   *
-   * - ARM_MATH_ARMV8MxL:
-   *
-   * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
-   * on ARMv8M Mainline target.
-   *
-   * - __FPU_PRESENT:
-   *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
-   *
-   * - __DSP_PRESENT:
-   *
-   * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
-   *
-   * <hr>
-   * CMSIS-DSP in ARM::CMSIS Pack
-   * -----------------------------
-   *
-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
-   * |File/Folder                   |Content                                                                 |
-   * |------------------------------|------------------------------------------------------------------------|
-   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
-   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
-   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
-   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
-   *
-   * <hr>
-   * Revision History of CMSIS-DSP
-   * ------------
-   * Please refer to \ref ChangeLog_pg.
-   *
-   * Copyright Notice
-   * ------------
-   *
-   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* ignore some GCC warnings */
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-#endif
-
-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
-#include "core_cm7.h"
-#define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM4)
-#include "core_cm4.h"
-#define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM3)
-#include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-#include "core_cm0.h"
-#define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
-#include "core_cm0plus.h"
-#define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MBL)
-#include "core_armv8mbl.h"
-#define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MML)
-#include "core_armv8mml.h"
-#if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
-#define ARM_MATH_DSP
-#endif
-#else
-#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
-#endif
-
-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-
-/**
- * @brief Macros required for reciprocal calculation in Normalized LMS
- */
-
-#define DELTA_Q31          (0x100)
-#define DELTA_Q15          0x5
-#define INDEX_MASK         0x0000003F
-#ifndef PI
-#define PI               3.14159265358979f
-#endif
-
-/**
- * @brief Macros required for SINE and COSINE Fast math approximations
- */
-
-#define FAST_MATH_TABLE_SIZE  512
-#define FAST_MATH_Q31_SHIFT   (32 - 10)
-#define FAST_MATH_Q15_SHIFT   (16 - 10)
-#define CONTROLLER_Q31_SHIFT  (32 - 9)
-#define TABLE_SPACING_Q31     0x400000
-#define TABLE_SPACING_Q15     0x80
-
-/**
- * @brief Macros required for SINE and COSINE Controller functions
- */
-/* 1.31(q31) Fixed value of 2/360 */
-/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING         0xB60B61
-
-/**
- * @brief Macro for Unaligned Support
- */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-#define ALIGN4
-#else
-#if defined  (__GNUC__)
-#define ALIGN4 __attribute__((aligned(4)))
-#else
-#define ALIGN4 __align(4)
-#endif
-#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-/**
- * @brief Error status returned by some functions in the library.
- */
-
-typedef enum {
-    ARM_MATH_SUCCESS = 0,                /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
-} arm_status;
-
-/**
- * @brief 8-bit fractional data type in 1.7 format.
- */
-typedef int8_t q7_t;
-
-/**
- * @brief 16-bit fractional data type in 1.15 format.
- */
-typedef int16_t q15_t;
-
-/**
- * @brief 32-bit fractional data type in 1.31 format.
- */
-typedef int32_t q31_t;
-
-/**
- * @brief 64-bit fractional data type in 1.63 format.
- */
-typedef int64_t q63_t;
-
-/**
- * @brief 32-bit floating-point type definition.
- */
-typedef float float32_t;
-
-/**
- * @brief 64-bit floating-point type definition.
- */
-typedef double float64_t;
-
-/**
- * @brief definition to read/write two 16 bit values.
- */
-#if   defined ( __CC_ARM )
-#define __SIMD32_TYPE int32_t __packed
-#define CMSIS_UNUSED __attribute__((unused))
-#define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED __attribute__((unused))
-#define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __GNUC__ )
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED __attribute__((unused))
-#define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ICCARM__ )
-#define __SIMD32_TYPE int32_t __packed
-#define CMSIS_UNUSED
-#define CMSIS_INLINE
-
-#elif defined ( __TI_ARM__ )
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED __attribute__((unused))
-#define CMSIS_INLINE
-
-#elif defined ( __CSMC__ )
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED
-#define CMSIS_INLINE
-
-#elif defined ( __TASKING__ )
-#define __SIMD32_TYPE __unaligned int32_t
-#define CMSIS_UNUSED
-#define CMSIS_INLINE
-
-#else
-#error Unknown compiler
-#endif
-
-#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
-#define __SIMD64(addr)        (*(int64_t **) & (addr))
-
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
-/**
- * @brief definition to pack two 16 bit values.
- */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
-                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
-                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
-/**
-* @brief definition to pack four 8 bit values.
-*/
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-
-#endif
-
-
-/**
- * @brief Clips Q63 to Q31 values.
- */
-CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
-    q63_t x)
-{
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-           ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-}
-
-/**
- * @brief Clips Q63 to Q15 values.
- */
-CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
-    q63_t x)
-{
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-           ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-}
-
-/**
- * @brief Clips Q31 to Q7 values.
- */
-CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
-    q31_t x)
-{
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-           ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-}
-
-/**
- * @brief Clips Q31 to Q15 values.
- */
-CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
-    q31_t x)
-{
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-           ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-}
-
-/**
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
- */
-
-CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
-    q63_t x,
-    q31_t y)
-{
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-}
-
-/*
-  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
-  #define __CLZ __clz
-  #endif
- */
-/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
-CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
-    q31_t data);
-
-CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
-    q31_t data)
-{
-    uint32_t count = 0;
-    uint32_t mask = 0x80000000;
-
-    while ((data & mask) == 0) {
-        count += 1u;
-        mask = mask >> 1u;
-    }
-
-    return (count);
-}
-#endif
-
-/**
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
- */
-
-CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
-    q31_t in,
-    q31_t* dst,
-    q31_t* pRecipTable)
-{
-    q31_t out;
-    uint32_t tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if (in > 0) {
-        signBits = ((uint32_t) (__CLZ( in) - 1));
-    }
-    else {
-        signBits = ((uint32_t) (__CLZ(-in) - 1));
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >> 24);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++) {
-        tempVal = (uint32_t) (((q63_t) in * out) >> 31);
-        tempVal = 0x7FFFFFFFu - tempVal;
-        /*      1.31 with exp 1 */
-        /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
-        out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1u);
-}
-
-
-/**
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
-    q15_t in,
-    q15_t* dst,
-    q15_t* pRecipTable)
-{
-    q15_t out = 0;
-    uint32_t tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if (in > 0) {
-        signBits = ((uint32_t)(__CLZ( in) - 17));
-    }
-    else {
-        signBits = ((uint32_t)(__CLZ(-in) - 17));
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >>  8);
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++) {
-        tempVal = (uint32_t) (((q31_t) in * out) >> 15);
-        tempVal = 0x7FFFu - tempVal;
-        /*      1.15 with exp 1 */
-        out = (q15_t) (((q31_t) out * tempVal) >> 14);
-        /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-}
-
-
-/*
- * @brief C custom defined intrinisic function for only M0 processors
- */
-#if defined(ARM_MATH_CM0_FAMILY)
-CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
-    q31_t x,
-    uint32_t y)
-{
-    int32_t posMax, negMin;
-    uint32_t i;
-
-    posMax = 1;
-    for (i = 0; i < (y - 1); i++) {
-        posMax = posMax * 2;
-    }
-
-    if (x > 0) {
-        posMax = (posMax - 1);
-
-        if (x > posMax) {
-            x = posMax;
-        }
-    }
-    else {
-        negMin = -posMax;
-
-        if (x < negMin) {
-            x = negMin;
-        }
-    }
-    return (x);
-}
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
-/*
- * @brief C custom defined intrinsic function for M3 and M0 processors
- */
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
-
-/*
- * @brief C custom defined QADD8 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-}
-
-
-/*
- * @brief C custom defined QSUB8 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-}
-
-
-/*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
-    uint32_t x,
-    uint32_t y)
-{
-    /*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
-    q31_t r = 0, s = 0;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined SHADD16 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined QSUB16 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined SHSUB16 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined QASX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined SHASX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined QSAX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined SHSAX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined SMUSDX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
-    uint32_t x,
-    uint32_t y)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-}
-
-/*
- * @brief C custom defined SMUADX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
-    uint32_t x,
-    uint32_t y)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-}
-
-
-/*
- * @brief C custom defined QADD for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
-    int32_t x,
-    int32_t y)
-{
-    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
-}
-
-
-/*
- * @brief C custom defined QSUB for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
-    int32_t x,
-    int32_t y)
-{
-    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
-}
-
-
-/*
- * @brief C custom defined SMLAD for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
-    uint32_t x,
-    uint32_t y,
-    uint32_t sum)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-}
-
-
-/*
- * @brief C custom defined SMLADX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
-    uint32_t x,
-    uint32_t y,
-    uint32_t sum)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-}
-
-
-/*
- * @brief C custom defined SMLSDX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
-    uint32_t x,
-    uint32_t y,
-    uint32_t sum)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-}
-
-
-/*
- * @brief C custom defined SMLALD for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
-    uint32_t x,
-    uint32_t y,
-    uint64_t sum)
-{
-    /*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-}
-
-
-/*
- * @brief C custom defined SMLALDX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
-    uint32_t x,
-    uint32_t y,
-    uint64_t sum)
-{
-    /*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-}
-
-
-/*
- * @brief C custom defined SMUAD for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
-    uint32_t x,
-    uint32_t y)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-}
-
-
-/*
- * @brief C custom defined SMUSD for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
-    uint32_t x,
-    uint32_t y)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-}
-
-
-/*
- * @brief C custom defined SXTB16 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
-    uint32_t x)
-{
-    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
-                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
-}
-
-/*
- * @brief C custom defined SMMLA for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
-    int32_t x,
-    int32_t y,
-    int32_t sum)
-{
-    return (sum + (int32_t) (((int64_t) x * y) >> 32));
-}
-
-#if 0
-/*
- * @brief C custom defined PKHBT for unavailable DSP extension
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
-    uint32_t x,
-    uint32_t y,
-    uint32_t leftshift)
-{
-    return ( ((x             ) & 0x0000FFFFUL) |
-             ((y << leftshift) & 0xFFFF0000UL)  );
-}
-
-/*
- * @brief C custom defined PKHTB for unavailable DSP extension
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
-    uint32_t x,
-    uint32_t y,
-    uint32_t rightshift)
-{
-    return ( ((x              ) & 0xFFFF0000UL) |
-             ((y >> rightshift) & 0x0000FFFFUL)  );
-}
-#endif
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
-
-/**
- * @brief Instance structure for the Q7 FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-} arm_fir_instance_q7;
-
-/**
- * @brief Instance structure for the Q15 FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-} arm_fir_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-} arm_fir_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-} arm_fir_instance_f32;
-
-
-/**
- * @brief Processing function for the Q7 FIR filter.
- * @param[in]  S          points to an instance of the Q7 FIR filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_q7(
-    const arm_fir_instance_q7* S,
-    q7_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q7 FIR filter.
- * @param[in,out] S          points to an instance of the Q7 FIR structure.
- * @param[in]     numTaps    Number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of samples that are processed.
- */
-void arm_fir_init_q7(
-    arm_fir_instance_q7* S,
-    uint16_t numTaps,
-    q7_t* pCoeffs,
-    q7_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q15 FIR filter.
- * @param[in]  S          points to an instance of the Q15 FIR structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_q15(
-    const arm_fir_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q15 FIR filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_fast_q15(
-    const arm_fir_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q15 FIR filter.
- * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
- * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of samples that are processed at a time.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
- * <code>numTaps</code> is not a supported value.
- */
-arm_status arm_fir_init_q15(
-    arm_fir_instance_q15* S,
-    uint16_t numTaps,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 FIR filter.
- * @param[in]  S          points to an instance of the Q31 FIR filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_q31(
-    const arm_fir_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q31 FIR structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_fast_q31(
-    const arm_fir_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q31 FIR filter.
- * @param[in,out] S          points to an instance of the Q31 FIR structure.
- * @param[in]     numTaps    Number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of samples that are processed at a time.
- */
-void arm_fir_init_q31(
-    arm_fir_instance_q31* S,
-    uint16_t numTaps,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the floating-point FIR filter.
- * @param[in]  S          points to an instance of the floating-point FIR structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_f32(
-    const arm_fir_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point FIR filter.
- * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
- * @param[in]     numTaps    Number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of samples that are processed at a time.
- */
-void arm_fir_init_f32(
-    arm_fir_instance_f32* S,
-    uint16_t numTaps,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q15 Biquad cascade filter.
- */
-typedef struct {
-    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t* pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t* pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
-} arm_biquad_casd_df1_inst_q15;
-
-/**
- * @brief Instance structure for the Q31 Biquad cascade filter.
- */
-typedef struct {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t* pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t* pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-} arm_biquad_casd_df1_inst_q31;
-
-/**
- * @brief Instance structure for the floating-point Biquad cascade filter.
- */
-typedef struct {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t* pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t* pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-} arm_biquad_casd_df1_inst_f32;
-
-
-/**
- * @brief Processing function for the Q15 Biquad cascade filter.
- * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df1_q15(
-    const arm_biquad_casd_df1_inst_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q15 Biquad cascade filter.
- * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
- */
-void arm_biquad_cascade_df1_init_q15(
-    arm_biquad_casd_df1_inst_q15* S,
-    uint8_t numStages,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    int8_t postShift);
-
-
-/**
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df1_fast_q15(
-    const arm_biquad_casd_df1_inst_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 Biquad cascade filter
- * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df1_q31(
-    const arm_biquad_casd_df1_inst_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df1_fast_q31(
-    const arm_biquad_casd_df1_inst_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q31 Biquad cascade filter.
- * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
- */
-void arm_biquad_cascade_df1_init_q31(
-    arm_biquad_casd_df1_inst_q31* S,
-    uint8_t numStages,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    int8_t postShift);
-
-
-/**
- * @brief Processing function for the floating-point Biquad cascade filter.
- * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df1_f32(
-    const arm_biquad_casd_df1_inst_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point Biquad cascade filter.
- * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- */
-void arm_biquad_cascade_df1_init_f32(
-    arm_biquad_casd_df1_inst_f32* S,
-    uint8_t numStages,
-    float32_t* pCoeffs,
-    float32_t* pState);
-
-
-/**
- * @brief Instance structure for the floating-point matrix structure.
- */
-typedef struct {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t* pData;     /**< points to the data of the matrix. */
-} arm_matrix_instance_f32;
-
-
-/**
- * @brief Instance structure for the floating-point matrix structure.
- */
-typedef struct {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float64_t* pData;     /**< points to the data of the matrix. */
-} arm_matrix_instance_f64;
-
-/**
- * @brief Instance structure for the Q15 matrix structure.
- */
-typedef struct {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t* pData;         /**< points to the data of the matrix. */
-} arm_matrix_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 matrix structure.
- */
-typedef struct {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t* pData;         /**< points to the data of the matrix. */
-} arm_matrix_instance_q31;
-
-
-/**
- * @brief Floating-point matrix addition.
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_add_f32(
-    const arm_matrix_instance_f32* pSrcA,
-    const arm_matrix_instance_f32* pSrcB,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15 matrix addition.
- * @param[in]   pSrcA  points to the first input matrix structure
- * @param[in]   pSrcB  points to the second input matrix structure
- * @param[out]  pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_add_q15(
-    const arm_matrix_instance_q15* pSrcA,
-    const arm_matrix_instance_q15* pSrcB,
-    arm_matrix_instance_q15* pDst);
-
-
-/**
- * @brief Q31 matrix addition.
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_add_q31(
-    const arm_matrix_instance_q31* pSrcA,
-    const arm_matrix_instance_q31* pSrcB,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Floating-point, complex, matrix multiplication.
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_cmplx_mult_f32(
-    const arm_matrix_instance_f32* pSrcA,
-    const arm_matrix_instance_f32* pSrcB,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15, complex,  matrix multiplication.
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_cmplx_mult_q15(
-    const arm_matrix_instance_q15* pSrcA,
-    const arm_matrix_instance_q15* pSrcB,
-    arm_matrix_instance_q15* pDst,
-    q15_t* pScratch);
-
-
-/**
- * @brief Q31, complex, matrix multiplication.
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_cmplx_mult_q31(
-    const arm_matrix_instance_q31* pSrcA,
-    const arm_matrix_instance_q31* pSrcB,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Floating-point matrix transpose.
- * @param[in]  pSrc  points to the input matrix
- * @param[out] pDst  points to the output matrix
- * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_trans_f32(
-    const arm_matrix_instance_f32* pSrc,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15 matrix transpose.
- * @param[in]  pSrc  points to the input matrix
- * @param[out] pDst  points to the output matrix
- * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_trans_q15(
-    const arm_matrix_instance_q15* pSrc,
-    arm_matrix_instance_q15* pDst);
-
-
-/**
- * @brief Q31 matrix transpose.
- * @param[in]  pSrc  points to the input matrix
- * @param[out] pDst  points to the output matrix
- * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_trans_q31(
-    const arm_matrix_instance_q31* pSrc,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Floating-point matrix multiplication
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_mult_f32(
-    const arm_matrix_instance_f32* pSrcA,
-    const arm_matrix_instance_f32* pSrcB,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15 matrix multiplication
- * @param[in]  pSrcA   points to the first input matrix structure
- * @param[in]  pSrcB   points to the second input matrix structure
- * @param[out] pDst    points to output matrix structure
- * @param[in]  pState  points to the array for storing intermediate results
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_mult_q15(
-    const arm_matrix_instance_q15* pSrcA,
-    const arm_matrix_instance_q15* pSrcB,
-    arm_matrix_instance_q15* pDst,
-    q15_t* pState);
-
-
-/**
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA   points to the first input matrix structure
- * @param[in]  pSrcB   points to the second input matrix structure
- * @param[out] pDst    points to output matrix structure
- * @param[in]  pState  points to the array for storing intermediate results
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_mult_fast_q15(
-    const arm_matrix_instance_q15* pSrcA,
-    const arm_matrix_instance_q15* pSrcB,
-    arm_matrix_instance_q15* pDst,
-    q15_t* pState);
-
-
-/**
- * @brief Q31 matrix multiplication
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_mult_q31(
-    const arm_matrix_instance_q31* pSrcA,
-    const arm_matrix_instance_q31* pSrcB,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_mult_fast_q31(
-    const arm_matrix_instance_q31* pSrcA,
-    const arm_matrix_instance_q31* pSrcB,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Floating-point matrix subtraction
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_sub_f32(
-    const arm_matrix_instance_f32* pSrcA,
-    const arm_matrix_instance_f32* pSrcB,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15 matrix subtraction
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_sub_q15(
-    const arm_matrix_instance_q15* pSrcA,
-    const arm_matrix_instance_q15* pSrcB,
-    arm_matrix_instance_q15* pDst);
-
-
-/**
- * @brief Q31 matrix subtraction
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_sub_q31(
-    const arm_matrix_instance_q31* pSrcA,
-    const arm_matrix_instance_q31* pSrcB,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Floating-point matrix scaling.
- * @param[in]  pSrc   points to the input matrix
- * @param[in]  scale  scale factor
- * @param[out] pDst   points to the output matrix
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_scale_f32(
-    const arm_matrix_instance_f32* pSrc,
-    float32_t scale,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15 matrix scaling.
- * @param[in]  pSrc        points to input matrix
- * @param[in]  scaleFract  fractional portion of the scale factor
- * @param[in]  shift       number of bits to shift the result by
- * @param[out] pDst        points to output matrix
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_scale_q15(
-    const arm_matrix_instance_q15* pSrc,
-    q15_t scaleFract,
-    int32_t shift,
-    arm_matrix_instance_q15* pDst);
-
-
-/**
- * @brief Q31 matrix scaling.
- * @param[in]  pSrc        points to input matrix
- * @param[in]  scaleFract  fractional portion of the scale factor
- * @param[in]  shift       number of bits to shift the result by
- * @param[out] pDst        points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_scale_q31(
-    const arm_matrix_instance_q31* pSrc,
-    q31_t scaleFract,
-    int32_t shift,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief  Q31 matrix initialization.
- * @param[in,out] S         points to an instance of the floating-point matrix structure.
- * @param[in]     nRows     number of rows in the matrix.
- * @param[in]     nColumns  number of columns in the matrix.
- * @param[in]     pData     points to the matrix data array.
- */
-void arm_mat_init_q31(
-    arm_matrix_instance_q31* S,
-    uint16_t nRows,
-    uint16_t nColumns,
-    q31_t* pData);
-
-
-/**
- * @brief  Q15 matrix initialization.
- * @param[in,out] S         points to an instance of the floating-point matrix structure.
- * @param[in]     nRows     number of rows in the matrix.
- * @param[in]     nColumns  number of columns in the matrix.
- * @param[in]     pData     points to the matrix data array.
- */
-void arm_mat_init_q15(
-    arm_matrix_instance_q15* S,
-    uint16_t nRows,
-    uint16_t nColumns,
-    q15_t* pData);
-
-
-/**
- * @brief  Floating-point matrix initialization.
- * @param[in,out] S         points to an instance of the floating-point matrix structure.
- * @param[in]     nRows     number of rows in the matrix.
- * @param[in]     nColumns  number of columns in the matrix.
- * @param[in]     pData     points to the matrix data array.
- */
-void arm_mat_init_f32(
-    arm_matrix_instance_f32* S,
-    uint16_t nRows,
-    uint16_t nColumns,
-    float32_t* pData);
-
-
-
-/**
- * @brief Instance structure for the Q15 PID Control.
- */
-typedef struct {
-    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
-#if !defined (ARM_MATH_DSP)
-    q15_t A1;
-    q15_t A2;
-#else
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-    q15_t state[3];     /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-} arm_pid_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 PID Control.
- */
-typedef struct {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-} arm_pid_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point PID Control.
- */
-typedef struct {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;          /**< The proportional gain. */
-    float32_t Ki;          /**< The integral gain. */
-    float32_t Kd;          /**< The derivative gain. */
-} arm_pid_instance_f32;
-
-
-
-/**
- * @brief  Initialization function for the floating-point PID Control.
- * @param[in,out] S               points to an instance of the PID structure.
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
- */
-void arm_pid_init_f32(
-    arm_pid_instance_f32* S,
-    int32_t resetStateFlag);
-
-
-/**
- * @brief  Reset function for the floating-point PID Control.
- * @param[in,out] S  is an instance of the floating-point PID Control structure
- */
-void arm_pid_reset_f32(
-    arm_pid_instance_f32* S);
-
-
-/**
- * @brief  Initialization function for the Q31 PID Control.
- * @param[in,out] S               points to an instance of the Q15 PID structure.
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
- */
-void arm_pid_init_q31(
-    arm_pid_instance_q31* S,
-    int32_t resetStateFlag);
-
-
-/**
- * @brief  Reset function for the Q31 PID Control.
- * @param[in,out] S   points to an instance of the Q31 PID Control structure
- */
-
-void arm_pid_reset_q31(
-    arm_pid_instance_q31* S);
-
-
-/**
- * @brief  Initialization function for the Q15 PID Control.
- * @param[in,out] S               points to an instance of the Q15 PID structure.
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
- */
-void arm_pid_init_q15(
-    arm_pid_instance_q15* S,
-    int32_t resetStateFlag);
-
-
-/**
- * @brief  Reset function for the Q15 PID Control.
- * @param[in,out] S  points to an instance of the q15 PID Control structure
- */
-void arm_pid_reset_q15(
-    arm_pid_instance_q15* S);
-
-
-/**
- * @brief Instance structure for the floating-point Linear Interpolate function.
- */
-typedef struct {
-    uint32_t nValues;           /**< nValues */
-    float32_t x1;               /**< x1 */
-    float32_t xSpacing;         /**< xSpacing */
-    float32_t* pYData;          /**< pointer to the table of Y values */
-} arm_linear_interp_instance_f32;
-
-/**
- * @brief Instance structure for the floating-point bilinear interpolation function.
- */
-typedef struct {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    float32_t* pData;   /**< points to the data table. */
-} arm_bilinear_interp_instance_f32;
-
-/**
-* @brief Instance structure for the Q31 bilinear interpolation function.
-*/
-typedef struct {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q31_t* pData;       /**< points to the data table. */
-} arm_bilinear_interp_instance_q31;
-
-/**
-* @brief Instance structure for the Q15 bilinear interpolation function.
-*/
-typedef struct {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q15_t* pData;       /**< points to the data table. */
-} arm_bilinear_interp_instance_q15;
-
-/**
-* @brief Instance structure for the Q15 bilinear interpolation function.
-*/
-typedef struct {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q7_t* pData;        /**< points to the data table. */
-} arm_bilinear_interp_instance_q7;
-
-
-/**
- * @brief Q7 vector multiplication.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_mult_q7(
-    q7_t* pSrcA,
-    q7_t* pSrcB,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q15 vector multiplication.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_mult_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q31 vector multiplication.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_mult_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Floating-point vector multiplication.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_mult_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t* pTwiddle;                 /**< points to the Sin twiddle factor table. */
-    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-} arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
-arm_status arm_cfft_radix2_init_q15(
-    arm_cfft_radix2_instance_q15* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/* Deprecated */
-void arm_cfft_radix2_q15(
-    const arm_cfft_radix2_instance_q15* S,
-    q15_t* pSrc);
-
-
-/**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t* pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-} arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
-arm_status arm_cfft_radix4_init_q15(
-    arm_cfft_radix4_instance_q15* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/* Deprecated */
-void arm_cfft_radix4_q15(
-    const arm_cfft_radix4_instance_q15* S,
-    q15_t* pSrc);
-
-/**
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t* pTwiddle;                 /**< points to the Twiddle factor table. */
-    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-} arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
-arm_status arm_cfft_radix2_init_q31(
-    arm_cfft_radix2_instance_q31* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/* Deprecated */
-void arm_cfft_radix2_q31(
-    const arm_cfft_radix2_instance_q31* S,
-    q31_t* pSrc);
-
-/**
- * @brief Instance structure for the Q31 CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t* pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-} arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
-void arm_cfft_radix4_q31(
-    const arm_cfft_radix4_instance_q31* S,
-    q31_t* pSrc);
-
-/* Deprecated */
-arm_status arm_cfft_radix4_init_q31(
-    arm_cfft_radix4_instance_q31* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-} arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
-arm_status arm_cfft_radix2_init_f32(
-    arm_cfft_radix2_instance_f32* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/* Deprecated */
-void arm_cfft_radix2_f32(
-    const arm_cfft_radix2_instance_f32* S,
-    float32_t* pSrc);
-
-/**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-} arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
-arm_status arm_cfft_radix4_init_f32(
-    arm_cfft_radix4_instance_f32* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/* Deprecated */
-void arm_cfft_radix4_f32(
-    const arm_cfft_radix4_instance_f32* S,
-    float32_t* pSrc);
-
-/**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q15_t* pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-} arm_cfft_instance_q15;
-
-void arm_cfft_q15(
-    const arm_cfft_instance_q15* S,
-    q15_t* p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q31_t* pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-} arm_cfft_instance_q31;
-
-void arm_cfft_q31(
-    const arm_cfft_instance_q31* S,
-    q31_t* p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const float32_t* pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-} arm_cfft_instance_f32;
-
-void arm_cfft_f32(
-    const arm_cfft_instance_f32* S,
-    float32_t* p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/**
- * @brief Instance structure for the Q15 RFFT/RIFFT function.
- */
-typedef struct {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q15_t* pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    q15_t* pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q15* pCfft;       /**< points to the complex FFT instance. */
-} arm_rfft_instance_q15;
-
-arm_status arm_rfft_init_q15(
-    arm_rfft_instance_q15* S,
-    uint32_t fftLenReal,
-    uint32_t ifftFlagR,
-    uint32_t bitReverseFlag);
-
-void arm_rfft_q15(
-    const arm_rfft_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst);
-
-/**
- * @brief Instance structure for the Q31 RFFT/RIFFT function.
- */
-typedef struct {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t* pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    q31_t* pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q31* pCfft;         /**< points to the complex FFT instance. */
-} arm_rfft_instance_q31;
-
-arm_status arm_rfft_init_q31(
-    arm_rfft_instance_q31* S,
-    uint32_t fftLenReal,
-    uint32_t ifftFlagR,
-    uint32_t bitReverseFlag);
-
-void arm_rfft_q31(
-    const arm_rfft_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst);
-
-/**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-typedef struct {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t* pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t* pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32* pCfft;        /**< points to the complex FFT instance. */
-} arm_rfft_instance_f32;
-
-arm_status arm_rfft_init_f32(
-    arm_rfft_instance_f32* S,
-    arm_cfft_radix4_instance_f32* S_CFFT,
-    uint32_t fftLenReal,
-    uint32_t ifftFlagR,
-    uint32_t bitReverseFlag);
-
-void arm_rfft_f32(
-    const arm_rfft_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst);
-
-/**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-typedef struct {
-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
-    uint16_t fftLenRFFT;             /**< length of the real sequence */
-    float32_t* pTwiddleRFFT;         /**< Twiddle factors real stage  */
-} arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
-    arm_rfft_fast_instance_f32* S,
-    uint16_t fftLen);
-
-void arm_rfft_fast_f32(
-    arm_rfft_fast_instance_f32* S,
-    float32_t* p, float32_t* pOut,
-    uint8_t ifftFlag);
-
-/**
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.
- */
-typedef struct {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    float32_t normalize;                 /**< normalizing factor. */
-    float32_t* pTwiddle;                 /**< points to the twiddle factor table. */
-    float32_t* pCosFactor;               /**< points to the cosFactor table. */
-    arm_rfft_instance_f32* pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */
-} arm_dct4_instance_f32;
-
-
-/**
- * @brief  Initialization function for the floating-point DCT4/IDCT4.
- * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
- * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
- * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
- * @param[in]     N          length of the DCT4.
- * @param[in]     Nby2       half of the length of the DCT4.
- * @param[in]     normalize  normalizing factor.
- * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
- */
-arm_status arm_dct4_init_f32(
-    arm_dct4_instance_f32* S,
-    arm_rfft_instance_f32* S_RFFT,
-    arm_cfft_radix4_instance_f32* S_CFFT,
-    uint16_t N,
-    uint16_t Nby2,
-    float32_t normalize);
-
-
-/**
- * @brief Processing function for the floating-point DCT4/IDCT4.
- * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
- * @param[in]     pState         points to state buffer.
- * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
- */
-void arm_dct4_f32(
-    const arm_dct4_instance_f32* S,
-    float32_t* pState,
-    float32_t* pInlineBuffer);
-
-
-/**
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.
- */
-typedef struct {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q31_t normalize;                     /**< normalizing factor. */
-    q31_t* pTwiddle;                     /**< points to the twiddle factor table. */
-    q31_t* pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q31* pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */
-} arm_dct4_instance_q31;
-
-
-/**
- * @brief  Initialization function for the Q31 DCT4/IDCT4.
- * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
- * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
- * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
- * @param[in]     N          length of the DCT4.
- * @param[in]     Nby2       half of the length of the DCT4.
- * @param[in]     normalize  normalizing factor.
- * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
-arm_status arm_dct4_init_q31(
-    arm_dct4_instance_q31* S,
-    arm_rfft_instance_q31* S_RFFT,
-    arm_cfft_radix4_instance_q31* S_CFFT,
-    uint16_t N,
-    uint16_t Nby2,
-    q31_t normalize);
-
-
-/**
- * @brief Processing function for the Q31 DCT4/IDCT4.
- * @param[in]     S              points to an instance of the Q31 DCT4 structure.
- * @param[in]     pState         points to state buffer.
- * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
- */
-void arm_dct4_q31(
-    const arm_dct4_instance_q31* S,
-    q31_t* pState,
-    q31_t* pInlineBuffer);
-
-
-/**
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.
- */
-typedef struct {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q15_t normalize;                     /**< normalizing factor. */
-    q15_t* pTwiddle;                     /**< points to the twiddle factor table. */
-    q15_t* pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q15* pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */
-} arm_dct4_instance_q15;
-
-
-/**
- * @brief  Initialization function for the Q15 DCT4/IDCT4.
- * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
- * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
- * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
- * @param[in]     N          length of the DCT4.
- * @param[in]     Nby2       half of the length of the DCT4.
- * @param[in]     normalize  normalizing factor.
- * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
-arm_status arm_dct4_init_q15(
-    arm_dct4_instance_q15* S,
-    arm_rfft_instance_q15* S_RFFT,
-    arm_cfft_radix4_instance_q15* S_CFFT,
-    uint16_t N,
-    uint16_t Nby2,
-    q15_t normalize);
-
-
-/**
- * @brief Processing function for the Q15 DCT4/IDCT4.
- * @param[in]     S              points to an instance of the Q15 DCT4 structure.
- * @param[in]     pState         points to state buffer.
- * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
- */
-void arm_dct4_q15(
-    const arm_dct4_instance_q15* S,
-    q15_t* pState,
-    q15_t* pInlineBuffer);
-
-
-/**
- * @brief Floating-point vector addition.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_add_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q7 vector addition.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_add_q7(
-    q7_t* pSrcA,
-    q7_t* pSrcB,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q15 vector addition.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_add_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q31 vector addition.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_add_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Floating-point vector subtraction.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_sub_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q7 vector subtraction.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_sub_q7(
-    q7_t* pSrcA,
-    q7_t* pSrcB,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q15 vector subtraction.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_sub_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q31 vector subtraction.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_sub_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Multiplies a floating-point vector by a scalar.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  scale      scale factor to be applied
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_scale_f32(
-    float32_t* pSrc,
-    float32_t scale,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Multiplies a Q7 vector by a scalar.
- * @param[in]  pSrc        points to the input vector
- * @param[in]  scaleFract  fractional portion of the scale value
- * @param[in]  shift       number of bits to shift the result by
- * @param[out] pDst        points to the output vector
- * @param[in]  blockSize   number of samples in the vector
- */
-void arm_scale_q7(
-    q7_t* pSrc,
-    q7_t scaleFract,
-    int8_t shift,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Multiplies a Q15 vector by a scalar.
- * @param[in]  pSrc        points to the input vector
- * @param[in]  scaleFract  fractional portion of the scale value
- * @param[in]  shift       number of bits to shift the result by
- * @param[out] pDst        points to the output vector
- * @param[in]  blockSize   number of samples in the vector
- */
-void arm_scale_q15(
-    q15_t* pSrc,
-    q15_t scaleFract,
-    int8_t shift,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Multiplies a Q31 vector by a scalar.
- * @param[in]  pSrc        points to the input vector
- * @param[in]  scaleFract  fractional portion of the scale value
- * @param[in]  shift       number of bits to shift the result by
- * @param[out] pDst        points to the output vector
- * @param[in]  blockSize   number of samples in the vector
- */
-void arm_scale_q31(
-    q31_t* pSrc,
-    q31_t scaleFract,
-    int8_t shift,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q7 vector absolute value.
- * @param[in]  pSrc       points to the input buffer
- * @param[out] pDst       points to the output buffer
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_abs_q7(
-    q7_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Floating-point vector absolute value.
- * @param[in]  pSrc       points to the input buffer
- * @param[out] pDst       points to the output buffer
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_abs_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q15 vector absolute value.
- * @param[in]  pSrc       points to the input buffer
- * @param[out] pDst       points to the output buffer
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_abs_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q31 vector absolute value.
- * @param[in]  pSrc       points to the input buffer
- * @param[out] pDst       points to the output buffer
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_abs_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Dot product of floating-point vectors.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[in]  blockSize  number of samples in each vector
- * @param[out] result     output result returned here
- */
-void arm_dot_prod_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    uint32_t blockSize,
-    float32_t* result);
-
-
-/**
- * @brief Dot product of Q7 vectors.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[in]  blockSize  number of samples in each vector
- * @param[out] result     output result returned here
- */
-void arm_dot_prod_q7(
-    q7_t* pSrcA,
-    q7_t* pSrcB,
-    uint32_t blockSize,
-    q31_t* result);
-
-
-/**
- * @brief Dot product of Q15 vectors.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[in]  blockSize  number of samples in each vector
- * @param[out] result     output result returned here
- */
-void arm_dot_prod_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    uint32_t blockSize,
-    q63_t* result);
-
-
-/**
- * @brief Dot product of Q31 vectors.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[in]  blockSize  number of samples in each vector
- * @param[out] result     output result returned here
- */
-void arm_dot_prod_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    uint32_t blockSize,
-    q63_t* result);
-
-
-/**
- * @brief  Shifts the elements of a Q7 vector a specified number of bits.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_shift_q7(
-    q7_t* pSrc,
-    int8_t shiftBits,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Shifts the elements of a Q15 vector a specified number of bits.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_shift_q15(
-    q15_t* pSrc,
-    int8_t shiftBits,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Shifts the elements of a Q31 vector a specified number of bits.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_shift_q31(
-    q31_t* pSrc,
-    int8_t shiftBits,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Adds a constant offset to a floating-point vector.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  offset     is the offset to be added
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_offset_f32(
-    float32_t* pSrc,
-    float32_t offset,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Adds a constant offset to a Q7 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  offset     is the offset to be added
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_offset_q7(
-    q7_t* pSrc,
-    q7_t offset,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Adds a constant offset to a Q15 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  offset     is the offset to be added
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_offset_q15(
-    q15_t* pSrc,
-    q15_t offset,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Adds a constant offset to a Q31 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  offset     is the offset to be added
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_offset_q31(
-    q31_t* pSrc,
-    q31_t offset,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Negates the elements of a floating-point vector.
- * @param[in]  pSrc       points to the input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_negate_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Negates the elements of a Q7 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_negate_q7(
-    q7_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Negates the elements of a Q15 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_negate_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Negates the elements of a Q31 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_negate_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Copies the elements of a floating-point vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_copy_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Copies the elements of a Q7 vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_copy_q7(
-    q7_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Copies the elements of a Q15 vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_copy_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Copies the elements of a Q31 vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_copy_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Fills a constant value into a floating-point vector.
- * @param[in]  value      input value to be filled
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_fill_f32(
-    float32_t value,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Fills a constant value into a Q7 vector.
- * @param[in]  value      input value to be filled
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_fill_q7(
-    q7_t value,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Fills a constant value into a Q15 vector.
- * @param[in]  value      input value to be filled
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_fill_q15(
-    q15_t value,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Fills a constant value into a Q31 vector.
- * @param[in]  value      input value to be filled
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_fill_q31(
-    q31_t value,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-void arm_conv_f32(
-    float32_t* pSrcA,
-    uint32_t srcALen,
-    float32_t* pSrcB,
-    uint32_t srcBLen,
-    float32_t* pDst);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in]  pSrcA      points to the first input sequence.
- * @param[in]  srcALen    length of the first input sequence.
- * @param[in]  pSrcB      points to the second input sequence.
- * @param[in]  srcBLen    length of the second input sequence.
- * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
- * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
- */
-void arm_conv_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-void arm_conv_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst);
-
-
-/**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
- */
-void arm_conv_fast_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst);
-
-
-/**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA      points to the first input sequence.
- * @param[in]  srcALen    length of the first input sequence.
- * @param[in]  pSrcB      points to the second input sequence.
- * @param[in]  srcBLen    length of the second input sequence.
- * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
- * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
- */
-void arm_conv_fast_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Convolution of Q31 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
- */
-void arm_conv_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst);
-
-
-/**
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
- */
-void arm_conv_fast_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst);
-
-
-/**
-* @brief Convolution of Q7 sequences.
-* @param[in]  pSrcA      points to the first input sequence.
-* @param[in]  srcALen    length of the first input sequence.
-* @param[in]  pSrcB      points to the second input sequence.
-* @param[in]  srcBLen    length of the second input sequence.
-* @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-* @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-* @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-*/
-void arm_conv_opt_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Convolution of Q7 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
- */
-void arm_conv_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst);
-
-
-/**
- * @brief Partial convolution of floating-point sequences.
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_f32(
-    float32_t* pSrcA,
-    uint32_t srcALen,
-    float32_t* pSrcB,
-    uint32_t srcBLen,
-    float32_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Partial convolution of Q15 sequences.
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Partial convolution of Q15 sequences.
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_fast_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_fast_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Partial convolution of Q31 sequences.
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_fast_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Partial convolution of Q7 sequences
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_opt_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-arm_status arm_conv_partial_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Instance structure for the Q15 FIR decimator.
- */
-typedef struct {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q15_t* pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t* pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-} arm_fir_decimate_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 FIR decimator.
- */
-typedef struct {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t* pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t* pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-} arm_fir_decimate_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point FIR decimator.
- */
-typedef struct {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    float32_t* pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t* pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-} arm_fir_decimate_instance_f32;
-
-
-/**
- * @brief Processing function for the floating-point FIR decimator.
- * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_decimate_f32(
-    const arm_fir_decimate_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point FIR decimator.
- * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
- * @param[in]     numTaps    number of coefficients in the filter.
- * @param[in]     M          decimation factor.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-arm_status arm_fir_decimate_init_f32(
-    arm_fir_decimate_instance_f32* S,
-    uint16_t numTaps,
-    uint8_t M,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q15 FIR decimator.
- * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_decimate_q15(
-    const arm_fir_decimate_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_decimate_fast_q15(
-    const arm_fir_decimate_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q15 FIR decimator.
- * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
- * @param[in]     numTaps    number of coefficients in the filter.
- * @param[in]     M          decimation factor.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-arm_status arm_fir_decimate_init_q15(
-    arm_fir_decimate_instance_q15* S,
-    uint16_t numTaps,
-    uint8_t M,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 FIR decimator.
- * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
- * @param[in]  pSrc  points to the block of input data.
- * @param[out] pDst  points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
-void arm_fir_decimate_q31(
-    const arm_fir_decimate_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-/**
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_decimate_fast_q31(
-    arm_fir_decimate_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q31 FIR decimator.
- * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
- * @param[in]     numTaps    number of coefficients in the filter.
- * @param[in]     M          decimation factor.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-arm_status arm_fir_decimate_init_q31(
-    arm_fir_decimate_instance_q31* S,
-    uint16_t numTaps,
-    uint8_t M,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q15 FIR interpolator.
- */
-typedef struct {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t* pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t* pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-} arm_fir_interpolate_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 FIR interpolator.
- */
-typedef struct {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t* pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t* pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-} arm_fir_interpolate_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point FIR interpolator.
- */
-typedef struct {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t* pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t* pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-} arm_fir_interpolate_instance_f32;
-
-
-/**
- * @brief Processing function for the Q15 FIR interpolator.
- * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_interpolate_q15(
-    const arm_fir_interpolate_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q15 FIR interpolator.
- * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
- * @param[in]     L          upsample factor.
- * @param[in]     numTaps    number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficient buffer.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-arm_status arm_fir_interpolate_init_q15(
-    arm_fir_interpolate_instance_q15* S,
-    uint8_t L,
-    uint16_t numTaps,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 FIR interpolator.
- * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_interpolate_q31(
-    const arm_fir_interpolate_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q31 FIR interpolator.
- * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
- * @param[in]     L          upsample factor.
- * @param[in]     numTaps    number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficient buffer.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-arm_status arm_fir_interpolate_init_q31(
-    arm_fir_interpolate_instance_q31* S,
-    uint8_t L,
-    uint16_t numTaps,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the floating-point FIR interpolator.
- * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_interpolate_f32(
-    const arm_fir_interpolate_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point FIR interpolator.
- * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
- * @param[in]     L          upsample factor.
- * @param[in]     numTaps    number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficient buffer.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-arm_status arm_fir_interpolate_init_f32(
-    arm_fir_interpolate_instance_f32* S,
-    uint8_t L,
-    uint16_t numTaps,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.
- */
-typedef struct {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t* pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t* pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-} arm_biquad_cas_df1_32x64_ins_q31;
-
-
-/**
- * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cas_df1_32x64_q31(
-    const arm_biquad_cas_df1_32x64_ins_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
- */
-void arm_biquad_cas_df1_32x64_init_q31(
-    arm_biquad_cas_df1_32x64_ins_q31* S,
-    uint8_t numStages,
-    q31_t* pCoeffs,
-    q63_t* pState,
-    uint8_t postShift);
-
-
-/**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-typedef struct {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-} arm_biquad_cascade_df2T_instance_f32;
-
-/**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-typedef struct {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-} arm_biquad_cascade_stereo_df2T_instance_f32;
-
-/**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-typedef struct {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float64_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float64_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-} arm_biquad_cascade_df2T_instance_f64;
-
-
-/**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in]  S          points to an instance of the filter data structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df2T_f32(
-    const arm_biquad_cascade_df2T_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
- * @param[in]  S          points to an instance of the filter data structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_stereo_df2T_f32(
-    const arm_biquad_cascade_stereo_df2T_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in]  S          points to an instance of the filter data structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df2T_f64(
-    const arm_biquad_cascade_df2T_instance_f64* S,
-    float64_t* pSrc,
-    float64_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S          points to an instance of the filter data structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- */
-void arm_biquad_cascade_df2T_init_f32(
-    arm_biquad_cascade_df2T_instance_f32* S,
-    uint8_t numStages,
-    float32_t* pCoeffs,
-    float32_t* pState);
-
-
-/**
- * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S          points to an instance of the filter data structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- */
-void arm_biquad_cascade_stereo_df2T_init_f32(
-    arm_biquad_cascade_stereo_df2T_instance_f32* S,
-    uint8_t numStages,
-    float32_t* pCoeffs,
-    float32_t* pState);
-
-
-/**
- * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S          points to an instance of the filter data structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- */
-void arm_biquad_cascade_df2T_init_f64(
-    arm_biquad_cascade_df2T_instance_f64* S,
-    uint8_t numStages,
-    float64_t* pCoeffs,
-    float64_t* pState);
-
-
-/**
- * @brief Instance structure for the Q15 FIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q15_t* pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q15_t* pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-} arm_fir_lattice_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 FIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q31_t* pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q31_t* pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-} arm_fir_lattice_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point FIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t* pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t* pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-} arm_fir_lattice_instance_f32;
-
-
-/**
- * @brief Initialization function for the Q15 FIR lattice filter.
- * @param[in] S          points to an instance of the Q15 FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.  The array is of length numStages.
- */
-void arm_fir_lattice_init_q15(
-    arm_fir_lattice_instance_q15* S,
-    uint16_t numStages,
-    q15_t* pCoeffs,
-    q15_t* pState);
-
-
-/**
- * @brief Processing function for the Q15 FIR lattice filter.
- * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_lattice_q15(
-    const arm_fir_lattice_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q31 FIR lattice filter.
- * @param[in] S          points to an instance of the Q31 FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.   The array is of length numStages.
- */
-void arm_fir_lattice_init_q31(
-    arm_fir_lattice_instance_q31* S,
-    uint16_t numStages,
-    q31_t* pCoeffs,
-    q31_t* pState);
-
-
-/**
- * @brief Processing function for the Q31 FIR lattice filter.
- * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_lattice_q31(
-    const arm_fir_lattice_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S          points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.  The array is of length numStages.
- */
-void arm_fir_lattice_init_f32(
-    arm_fir_lattice_instance_f32* S,
-    uint16_t numStages,
-    float32_t* pCoeffs,
-    float32_t* pState);
-
-
-/**
- * @brief Processing function for the floating-point FIR lattice filter.
- * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_lattice_f32(
-    const arm_fir_lattice_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q15 IIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q15_t* pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t* pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t* pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-} arm_iir_lattice_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 IIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q31_t* pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t* pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t* pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-} arm_iir_lattice_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point IIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    float32_t* pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t* pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t* pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
-} arm_iir_lattice_instance_f32;
-
-
-/**
- * @brief Processing function for the floating-point IIR lattice filter.
- * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_iir_lattice_f32(
-    const arm_iir_lattice_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point IIR lattice filter.
- * @param[in] S          points to an instance of the floating-point IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
- * @param[in] blockSize  number of samples to process.
- */
-void arm_iir_lattice_init_f32(
-    arm_iir_lattice_instance_f32* S,
-    uint16_t numStages,
-    float32_t* pkCoeffs,
-    float32_t* pvCoeffs,
-    float32_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 IIR lattice filter.
- * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_iir_lattice_q31(
-    const arm_iir_lattice_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q31 IIR lattice filter.
- * @param[in] S          points to an instance of the Q31 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize  number of samples to process.
- */
-void arm_iir_lattice_init_q31(
-    arm_iir_lattice_instance_q31* S,
-    uint16_t numStages,
-    q31_t* pkCoeffs,
-    q31_t* pvCoeffs,
-    q31_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q15 IIR lattice filter.
- * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_iir_lattice_q15(
-    const arm_iir_lattice_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize  number of samples to process per call.
- */
-void arm_iir_lattice_init_q15(
-    arm_iir_lattice_instance_q15* S,
-    uint16_t numStages,
-    q15_t* pkCoeffs,
-    q15_t* pvCoeffs,
-    q15_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the floating-point LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t* pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t* pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-} arm_lms_instance_f32;
-
-
-/**
- * @brief Processing function for floating-point LMS filter.
- * @param[in]  S          points to an instance of the floating-point LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_f32(
-    const arm_lms_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pRef,
-    float32_t* pOut,
-    float32_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for floating-point LMS filter.
- * @param[in] S          points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to the coefficient buffer.
- * @param[in] pState     points to state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- */
-void arm_lms_init_f32(
-    arm_lms_instance_f32* S,
-    uint16_t numTaps,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    float32_t mu,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q15 LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-} arm_lms_instance_q15;
-
-
-/**
- * @brief Initialization function for the Q15 LMS filter.
- * @param[in] S          points to an instance of the Q15 LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to the coefficient buffer.
- * @param[in] pState     points to the state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- * @param[in] postShift  bit shift applied to coefficients.
- */
-void arm_lms_init_q15(
-    arm_lms_instance_q15* S,
-    uint16_t numTaps,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    q15_t mu,
-    uint32_t blockSize,
-    uint32_t postShift);
-
-
-/**
- * @brief Processing function for Q15 LMS filter.
- * @param[in]  S          points to an instance of the Q15 LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_q15(
-    const arm_lms_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pRef,
-    q15_t* pOut,
-    q15_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q31 LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-} arm_lms_instance_q31;
-
-
-/**
- * @brief Processing function for Q31 LMS filter.
- * @param[in]  S          points to an instance of the Q15 LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_q31(
-    const arm_lms_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pRef,
-    q31_t* pOut,
-    q31_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for Q31 LMS filter.
- * @param[in] S          points to an instance of the Q31 LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to coefficient buffer.
- * @param[in] pState     points to state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- * @param[in] postShift  bit shift applied to coefficients.
- */
-void arm_lms_init_q31(
-    arm_lms_instance_q31* S,
-    uint16_t numTaps,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    q31_t mu,
-    uint32_t blockSize,
-    uint32_t postShift);
-
-
-/**
- * @brief Instance structure for the floating-point normalized LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;         /**< step size that control filter coefficient updates. */
-    float32_t energy;     /**< saves previous frame energy. */
-    float32_t x0;         /**< saves previous input sample. */
-} arm_lms_norm_instance_f32;
-
-
-/**
- * @brief Processing function for floating-point normalized LMS filter.
- * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_norm_f32(
-    arm_lms_norm_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pRef,
-    float32_t* pOut,
-    float32_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for floating-point normalized LMS filter.
- * @param[in] S          points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to coefficient buffer.
- * @param[in] pState     points to state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- */
-void arm_lms_norm_init_f32(
-    arm_lms_norm_instance_f32* S,
-    uint16_t numTaps,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    float32_t mu,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q31 normalized LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t* recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-} arm_lms_norm_instance_q31;
-
-
-/**
- * @brief Processing function for Q31 normalized LMS filter.
- * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_norm_q31(
-    arm_lms_norm_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pRef,
-    q31_t* pOut,
-    q31_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for Q31 normalized LMS filter.
- * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to coefficient buffer.
- * @param[in] pState     points to state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- * @param[in] postShift  bit shift applied to coefficients.
- */
-void arm_lms_norm_init_q31(
-    arm_lms_norm_instance_q31* S,
-    uint16_t numTaps,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    q31_t mu,
-    uint32_t blockSize,
-    uint8_t postShift);
-
-
-/**
- * @brief Instance structure for the Q15 normalized LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;     /**< Number of coefficients in the filter. */
-    q15_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q15_t* recipTable;    /**< Points to the reciprocal initial value table. */
-    q15_t energy;         /**< saves previous frame energy. */
-    q15_t x0;             /**< saves previous input sample. */
-} arm_lms_norm_instance_q15;
-
-
-/**
- * @brief Processing function for Q15 normalized LMS filter.
- * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_norm_q15(
-    arm_lms_norm_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pRef,
-    q15_t* pOut,
-    q15_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for Q15 normalized LMS filter.
- * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to coefficient buffer.
- * @param[in] pState     points to state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- * @param[in] postShift  bit shift applied to coefficients.
- */
-void arm_lms_norm_init_q15(
-    arm_lms_norm_instance_q15* S,
-    uint16_t numTaps,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    q15_t mu,
-    uint32_t blockSize,
-    uint8_t postShift);
-
-
-/**
- * @brief Correlation of floating-point sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-void arm_correlate_f32(
-    float32_t* pSrcA,
-    uint32_t srcALen,
-    float32_t* pSrcB,
-    uint32_t srcBLen,
-    float32_t* pDst);
-
-
-/**
-* @brief Correlation of Q15 sequences
-* @param[in]  pSrcA     points to the first input sequence.
-* @param[in]  srcALen   length of the first input sequence.
-* @param[in]  pSrcB     points to the second input sequence.
-* @param[in]  srcBLen   length of the second input sequence.
-* @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-* @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-*/
-void arm_correlate_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    q15_t* pScratch);
-
-
-/**
- * @brief Correlation of Q15 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-
-void arm_correlate_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst);
-
-
-/**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-
-void arm_correlate_fast_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst);
-
-
-/**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in]  pSrcA     points to the first input sequence.
- * @param[in]  srcALen   length of the first input sequence.
- * @param[in]  pSrcB     points to the second input sequence.
- * @param[in]  srcBLen   length of the second input sequence.
- * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- */
-void arm_correlate_fast_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    q15_t* pScratch);
-
-
-/**
- * @brief Correlation of Q31 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-void arm_correlate_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst);
-
-
-/**
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-void arm_correlate_fast_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst);
-
-
-/**
-  * @brief Correlation of Q7 sequences.
-  * @param[in]  pSrcA      points to the first input sequence.
-  * @param[in]  srcALen    length of the first input sequence.
-  * @param[in]  pSrcB      points to the second input sequence.
-  * @param[in]  srcBLen    length of the second input sequence.
-  * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-  * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-  * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-  */
-void arm_correlate_opt_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Correlation of Q7 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-void arm_correlate_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst);
-
-
-/**
- * @brief Instance structure for the floating-point sparse FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t* pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-} arm_fir_sparse_instance_f32;
-
-/**
- * @brief Instance structure for the Q31 sparse FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-} arm_fir_sparse_instance_q31;
-
-/**
- * @brief Instance structure for the Q15 sparse FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-} arm_fir_sparse_instance_q15;
-
-/**
- * @brief Instance structure for the Q7 sparse FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t* pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t* pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-} arm_fir_sparse_instance_q7;
-
-
-/**
- * @brief Processing function for the floating-point sparse FIR filter.
- * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
- * @param[in]  pSrc        points to the block of input data.
- * @param[out] pDst        points to the block of output data
- * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
- * @param[in]  blockSize   number of input samples to process per call.
- */
-void arm_fir_sparse_f32(
-    arm_fir_sparse_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    float32_t* pScratchIn,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point sparse FIR filter.
- * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
- * @param[in]     numTaps    number of nonzero coefficients in the filter.
- * @param[in]     pCoeffs    points to the array of filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     pTapDelay  points to the array of offset times.
- * @param[in]     maxDelay   maximum offset time supported.
- * @param[in]     blockSize  number of samples that will be processed per block.
- */
-void arm_fir_sparse_init_f32(
-    arm_fir_sparse_instance_f32* S,
-    uint16_t numTaps,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    int32_t* pTapDelay,
-    uint16_t maxDelay,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 sparse FIR filter.
- * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
- * @param[in]  pSrc        points to the block of input data.
- * @param[out] pDst        points to the block of output data
- * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
- * @param[in]  blockSize   number of input samples to process per call.
- */
-void arm_fir_sparse_q31(
-    arm_fir_sparse_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    q31_t* pScratchIn,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q31 sparse FIR filter.
- * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
- * @param[in]     numTaps    number of nonzero coefficients in the filter.
- * @param[in]     pCoeffs    points to the array of filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     pTapDelay  points to the array of offset times.
- * @param[in]     maxDelay   maximum offset time supported.
- * @param[in]     blockSize  number of samples that will be processed per block.
- */
-void arm_fir_sparse_init_q31(
-    arm_fir_sparse_instance_q31* S,
-    uint16_t numTaps,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    int32_t* pTapDelay,
-    uint16_t maxDelay,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q15 sparse FIR filter.
- * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
- * @param[in]  pSrc         points to the block of input data.
- * @param[out] pDst         points to the block of output data
- * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
- * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
- * @param[in]  blockSize    number of input samples to process per call.
- */
-void arm_fir_sparse_q15(
-    arm_fir_sparse_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    q15_t* pScratchIn,
-    q31_t* pScratchOut,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q15 sparse FIR filter.
- * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
- * @param[in]     numTaps    number of nonzero coefficients in the filter.
- * @param[in]     pCoeffs    points to the array of filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     pTapDelay  points to the array of offset times.
- * @param[in]     maxDelay   maximum offset time supported.
- * @param[in]     blockSize  number of samples that will be processed per block.
- */
-void arm_fir_sparse_init_q15(
-    arm_fir_sparse_instance_q15* S,
-    uint16_t numTaps,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    int32_t* pTapDelay,
-    uint16_t maxDelay,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q7 sparse FIR filter.
- * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
- * @param[in]  pSrc         points to the block of input data.
- * @param[out] pDst         points to the block of output data
- * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
- * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
- * @param[in]  blockSize    number of input samples to process per call.
- */
-void arm_fir_sparse_q7(
-    arm_fir_sparse_instance_q7* S,
-    q7_t* pSrc,
-    q7_t* pDst,
-    q7_t* pScratchIn,
-    q31_t* pScratchOut,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q7 sparse FIR filter.
- * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
- * @param[in]     numTaps    number of nonzero coefficients in the filter.
- * @param[in]     pCoeffs    points to the array of filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     pTapDelay  points to the array of offset times.
- * @param[in]     maxDelay   maximum offset time supported.
- * @param[in]     blockSize  number of samples that will be processed per block.
- */
-void arm_fir_sparse_init_q7(
-    arm_fir_sparse_instance_q7* S,
-    uint16_t numTaps,
-    q7_t* pCoeffs,
-    q7_t* pState,
-    int32_t* pTapDelay,
-    uint16_t maxDelay,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Floating-point sin_cos function.
- * @param[in]  theta   input value in degrees
- * @param[out] pSinVal  points to the processed sine output.
- * @param[out] pCosVal  points to the processed cos output.
- */
-void arm_sin_cos_f32(
-    float32_t theta,
-    float32_t* pSinVal,
-    float32_t* pCosVal);
-
-
-/**
- * @brief  Q31 sin_cos function.
- * @param[in]  theta    scaled input value in degrees
- * @param[out] pSinVal  points to the processed sine output.
- * @param[out] pCosVal  points to the processed cosine output.
- */
-void arm_sin_cos_q31(
-    q31_t theta,
-    q31_t* pSinVal,
-    q31_t* pCosVal);
-
-
-/**
- * @brief  Floating-point complex conjugate.
- * @param[in]  pSrc        points to the input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_conj_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t numSamples);
-
-/**
- * @brief  Q31 complex conjugate.
- * @param[in]  pSrc        points to the input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_conj_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q15 complex conjugate.
- * @param[in]  pSrc        points to the input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_conj_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Floating-point complex magnitude squared
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_squared_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q31 complex magnitude squared
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_squared_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q15 complex magnitude squared
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_squared_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t numSamples);
-
-
-/**
-  * @ingroup groupController
-  */
-
-/**
- * @defgroup PID PID Motor Control
- *
- * A Proportional Integral Derivative (PID) controller is a generic feedback control
- * loop mechanism widely used in industrial control systems.
- * A PID controller is the most commonly used type of feedback controller.
- *
- * This set of functions implements (PID) controllers
- * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
- * of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
- * is the input sample value. The functions return the output value.
- *
- * \par Algorithm:
- * <pre>
- *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- *    A0 = Kp + Ki + Kd
- *    A1 = (-Kp ) - (2 * Kd )
- *    A2 = Kd  </pre>
- *
- * \par
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
- *
- * \par
- * \image html PID.gif "Proportional Integral Derivative Controller"
- *
- * \par
- * The PID controller calculates an "error" value as the difference between
- * the measured output and the reference input.
- * The controller attempts to minimize the error by adjusting the process control inputs.
- * The proportional value determines the reaction to the current error,
- * the integral value determines the reaction based on the sum of recent errors,
- * and the derivative value determines the reaction based on the rate at which the error has been changing.
- *
- * \par Instance Structure
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
- * A separate instance structure must be defined for each PID Controller.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Reset Functions
- * There is also an associated reset function for each data type which clears the state array.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
- * - Zeros out the values in the state buffer.
- *
- * \par
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the PID Controller functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup PID
- * @{
- */
-
-/**
- * @brief  Process function for the floating-point PID Control.
- * @param[in,out] S   is an instance of the floating-point PID Control structure
- * @param[in]     in  input sample to process
- * @return out processed output sample.
- */
-CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
-    arm_pid_instance_f32* S,
-    float32_t in)
-{
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-          (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-}
-
-/**
- * @brief  Process function for the Q31 PID Control.
- * @param[in,out] S  points to an instance of the Q31 PID Control structure
- * @param[in]     in  input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
-CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
-    arm_pid_instance_q31* S,
-    q31_t in)
-{
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31u);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-}
-
-
-/**
- * @brief  Process function for the Q15 PID Control.
- * @param[in,out] S   points to an instance of the Q15 PID Control structure
- * @param[in]     in  input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
-CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
-    arm_pid_instance_q15* S,
-    q15_t in)
-{
-    q63_t acc;
-    q15_t out;
-
-#if defined (ARM_MATH_DSP)
-    __SIMD32_TYPE* vstate;
-
-    /* Implementation of PID controller */
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    vstate = __SIMD32_CONST(S->state);
-    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc);
-#else
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-}
-
-/**
- * @} end of PID group
- */
-
-
-/**
- * @brief Floating-point matrix inverse.
- * @param[in]  src   points to the instance of the input floating-point matrix structure.
- * @param[out] dst   points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
-arm_status arm_mat_inverse_f32(
-    const arm_matrix_instance_f32* src,
-    arm_matrix_instance_f32* dst);
-
-
-/**
- * @brief Floating-point matrix inverse.
- * @param[in]  src   points to the instance of the input floating-point matrix structure.
- * @param[out] dst   points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
-arm_status arm_mat_inverse_f64(
-    const arm_matrix_instance_f64* src,
-    arm_matrix_instance_f64* dst);
-
-
-
-/**
- * @ingroup groupController
- */
-
-/**
- * @defgroup clarke Vector Clarke Transform
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
- * \image html clarke.gif Stator current space vector and its components in (a,b).
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeFormula.gif
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup clarke
- * @{
- */
-
-/**
- *
- * @brief  Floating-point Clarke transform
- * @param[in]  Ia       input three-phase coordinate <code>a</code>
- * @param[in]  Ib       input three-phase coordinate <code>b</code>
- * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
- */
-CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
-    float32_t Ia,
-    float32_t Ib,
-    float32_t* pIalpha,
-    float32_t* pIbeta)
-{
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-}
-
-
-/**
- * @brief  Clarke transform for Q31 version
- * @param[in]  Ia       input three-phase coordinate <code>a</code>
- * @param[in]  Ib       input three-phase coordinate <code>b</code>
- * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
-    q31_t Ia,
-    q31_t Ib,
-    q31_t* pIalpha,
-    q31_t* pIbeta)
-{
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-}
-
-/**
- * @} end of clarke group
- */
-
-/**
- * @brief  Converts the elements of the Q7 vector to Q31 vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_q7_to_q31(
-    q7_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-
-/**
- * @ingroup groupController
- */
-
-/**
- * @defgroup inv_clarke Vector Inverse Clarke Transform
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeInvFormula.gif
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup inv_clarke
- * @{
- */
-
-/**
-* @brief  Floating-point Inverse Clarke transform
-* @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-* @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-* @param[out] pIa     points to output three-phase coordinate <code>a</code>
-* @param[out] pIb     points to output three-phase coordinate <code>b</code>
-*/
-CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
-    float32_t Ialpha,
-    float32_t Ibeta,
-    float32_t* pIa,
-    float32_t* pIb)
-{
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
-}
-
-
-/**
- * @brief  Inverse Clarke transform for Q31 version
- * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
- * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
- * @param[out] pIa     points to output three-phase coordinate <code>a</code>
- * @param[out] pIb     points to output three-phase coordinate <code>b</code>
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the subtraction, hence there is no risk of overflow.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
-    q31_t Ialpha,
-    q31_t Ibeta,
-    q31_t* pIa,
-    q31_t* pIb)
-{
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-}
-
-/**
- * @} end of inv_clarke group
- */
-
-/**
- * @brief  Converts the elements of the Q7 vector to Q15 vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_q7_to_q15(
-    q7_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-
-/**
- * @ingroup groupController
- */
-
-/**
- * @defgroup park Vector Park Transform
- *
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
- * from the stationary to the moving reference frame and control the spatial relationship between
- * the stator vector current and rotor flux vector.
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the
- * current vector and the relationship from the two reference frames:
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkFormula.gif
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup park
- * @{
- */
-
-/**
- * @brief Floating-point Park transform
- * @param[in]  Ialpha  input two-phase vector coordinate alpha
- * @param[in]  Ibeta   input two-phase vector coordinate beta
- * @param[out] pId     points to output   rotor reference frame d
- * @param[out] pIq     points to output   rotor reference frame q
- * @param[in]  sinVal  sine value of rotation angle theta
- * @param[in]  cosVal  cosine value of rotation angle theta
- *
- * The function implements the forward Park transform.
- *
- */
-CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
-    float32_t Ialpha,
-    float32_t Ibeta,
-    float32_t* pId,
-    float32_t* pIq,
-    float32_t sinVal,
-    float32_t cosVal)
-{
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-}
-
-
-/**
- * @brief  Park transform for Q31 version
- * @param[in]  Ialpha  input two-phase vector coordinate alpha
- * @param[in]  Ibeta   input two-phase vector coordinate beta
- * @param[out] pId     points to output rotor reference frame d
- * @param[out] pIq     points to output rotor reference frame q
- * @param[in]  sinVal  sine value of rotation angle theta
- * @param[in]  cosVal  cosine value of rotation angle theta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
-    q31_t Ialpha,
-    q31_t Ibeta,
-    q31_t* pId,
-    q31_t* pIq,
-    q31_t sinVal,
-    q31_t cosVal)
-{
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-}
-
-/**
- * @} end of park group
- */
-
-/**
- * @brief  Converts the elements of the Q7 vector to floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q7_to_float(
-    q7_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @ingroup groupController
- */
-
-/**
- * @defgroup inv_park Vector Inverse Park transform
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkInvFormula.gif
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup inv_park
- * @{
- */
-
-/**
-* @brief  Floating-point Inverse Park transform
-* @param[in]  Id       input coordinate of rotor reference frame d
-* @param[in]  Iq       input coordinate of rotor reference frame q
-* @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-* @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-* @param[in]  sinVal   sine value of rotation angle theta
-* @param[in]  cosVal   cosine value of rotation angle theta
-*/
-CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
-    float32_t Id,
-    float32_t Iq,
-    float32_t* pIalpha,
-    float32_t* pIbeta,
-    float32_t sinVal,
-    float32_t cosVal)
-{
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-}
-
-
-/**
- * @brief  Inverse Park transform for   Q31 version
- * @param[in]  Id       input coordinate of rotor reference frame d
- * @param[in]  Iq       input coordinate of rotor reference frame q
- * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
- * @param[in]  sinVal   sine value of rotation angle theta
- * @param[in]  cosVal   cosine value of rotation angle theta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
-    q31_t Id,
-    q31_t Iq,
-    q31_t* pIalpha,
-    q31_t* pIbeta,
-    q31_t sinVal,
-    q31_t cosVal)
-{
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-}
-
-/**
- * @} end of Inverse park group
- */
-
-
-/**
- * @brief  Converts the elements of the Q31 vector to floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q31_to_float(
-    q31_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-/**
- * @ingroup groupInterpolation
- */
-
-/**
- * @defgroup LinearInterpolate Linear Interpolation
- *
- * Linear interpolation is a method of curve fitting using linear polynomials.
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
- *
- * \par
- * \image html LinearInterp.gif "Linear interpolation"
- *
- * \par
- * A  Linear Interpolate function calculates an output value(y), for the input(x)
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
- *
- * \par Algorithm:
- * <pre>
- *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- *       where x0, x1 are nearest values of input x
- *             y0, y1 are nearest values to output y
- * </pre>
- *
- * \par
- * This set of functions implements Linear interpolation process
- * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
- * sample of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.
- * <code>x</code> is the input sample value. The functions returns the output value.
- *
- * \par
- * if x is outside of the table boundary, Linear interpolation returns first value of the table
- * if x is below input range and returns last value of table if x is above range.
- */
-
-/**
- * @addtogroup LinearInterpolate
- * @{
- */
-
-/**
- * @brief  Process function for the floating-point Linear Interpolation Function.
- * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
- * @param[in]     x  input sample to process
- * @return y processed output sample.
- *
- */
-CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
-    arm_linear_interp_instance_f32* S,
-    float32_t x)
-{
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t* pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (int32_t) ((x - S->x1) / xSpacing);
-
-    if (i < 0) {
-        /* Iniatilize output for below specified range as least output value of table */
-        y = pYData[0];
-    }
-    else if ((uint32_t)i >= S->nValues) {
-        /* Iniatilize output for above specified range as last output value of table */
-        y = pYData[S->nValues - 1];
-    }
-    else {
-        /* Calculation of nearest input values */
-        x0 = S->x1 +  i      * xSpacing;
-        x1 = S->x1 + (i + 1) * xSpacing;
-
-        /* Read of nearest output values */
-        y0 = pYData[i];
-        y1 = pYData[i + 1];
-
-        /* Calculation of output */
-        y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-}
-
-
-/**
-*
-* @brief  Process function for the Q31 Linear Interpolation Function.
-* @param[in] pYData   pointer to Q31 Linear Interpolation table
-* @param[in] x        input sample to process
-* @param[in] nValues  number of table values
-* @return y processed output sample.
-*
-* \par
-* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-* This function can support maximum of table size 2^12.
-*
-*/
-CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
-    q31_t* pYData,
-    q31_t x,
-    uint32_t nValues)
-{
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (q31_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1)) {
-        return (pYData[nValues - 1]);
-    }
-    else if (index < 0) {
-        return (pYData[0]);
-    }
-    else {
-        /* 20 bits for the fractional part */
-        /* shift left by 11 to keep fract in 1.31 format */
-        fract = (x & 0x000FFFFF) << 11;
-
-        /* Read two nearest output values from the index in 1.31(q31) format */
-        y0 = pYData[index];
-        y1 = pYData[index + 1];
-
-        /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-        y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-        /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-        y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-        /* Convert y to 1.31 format */
-        return (y << 1u);
-    }
-}
-
-
-/**
- *
- * @brief  Process function for the Q15 Linear Interpolation Function.
- * @param[in] pYData   pointer to Q15 Linear Interpolation table
- * @param[in] x        input sample to process
- * @param[in] nValues  number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
-CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
-    q15_t* pYData,
-    q31_t x,
-    uint32_t nValues)
-{
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (int32_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1)) {
-        return (pYData[nValues - 1]);
-    }
-    else if (index < 0) {
-        return (pYData[0]);
-    }
-    else {
-        /* 20 bits for the fractional part */
-        /* fract is in 12.20 format */
-        fract = (x & 0x000FFFFF);
-
-        /* Read two nearest output values from the index */
-        y0 = pYData[index];
-        y1 = pYData[index + 1];
-
-        /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-        y = ((q63_t) y0 * (0xFFFFF - fract));
-
-        /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-        y += ((q63_t) y1 * (fract));
-
-        /* convert y to 1.15 format */
-        return (q15_t) (y >> 20);
-    }
-}
-
-
-/**
- *
- * @brief  Process function for the Q7 Linear Interpolation Function.
- * @param[in] pYData   pointer to Q7 Linear Interpolation table
- * @param[in] x        input sample to process
- * @param[in] nValues  number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- */
-CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
-    q7_t* pYData,
-    q31_t x,
-    uint32_t nValues)
-{
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    uint32_t index;                              /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    if (x < 0) {
-        return (pYData[0]);
-    }
-    index = (x >> 20) & 0xfff;
-
-    if (index >= (nValues - 1)) {
-        return (pYData[nValues - 1]);
-    }
-    else {
-        /* 20 bits for the fractional part */
-        /* fract is in 12.20 format */
-        fract = (x & 0x000FFFFF);
-
-        /* Read two nearest output values from the index and are in 1.7(q7) format */
-        y0 = pYData[index];
-        y1 = pYData[index + 1];
-
-        /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-        y = ((y0 * (0xFFFFF - fract)));
-
-        /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-        y += (y1 * fract);
-
-        /* convert y to 1.7(q7) format */
-        return (q7_t) (y >> 20);
-    }
-}
-
-/**
- * @} end of LinearInterpolate group
- */
-
-/**
- * @brief  Fast approximation to the trigonometric sine function for floating-point data.
- * @param[in] x  input value in radians.
- * @return  sin(x).
- */
-float32_t arm_sin_f32(
-    float32_t x);
-
-
-/**
- * @brief  Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x  Scaled input value in radians.
- * @return  sin(x).
- */
-q31_t arm_sin_q31(
-    q31_t x);
-
-
-/**
- * @brief  Fast approximation to the trigonometric sine function for Q15 data.
- * @param[in] x  Scaled input value in radians.
- * @return  sin(x).
- */
-q15_t arm_sin_q15(
-    q15_t x);
-
-
-/**
- * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
- * @param[in] x  input value in radians.
- * @return  cos(x).
- */
-float32_t arm_cos_f32(
-    float32_t x);
-
-
-/**
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.
- * @param[in] x  Scaled input value in radians.
- * @return  cos(x).
- */
-q31_t arm_cos_q31(
-    q31_t x);
-
-
-/**
- * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
- * @param[in] x  Scaled input value in radians.
- * @return  cos(x).
- */
-q15_t arm_cos_q15(
-    q15_t x);
-
-
-/**
- * @ingroup groupFastMath
- */
-
-
-/**
- * @defgroup SQRT Square Root
- *
- * Computes the square root of a number.
- * There are separate functions for Q15, Q31, and floating-point data types.
- * The square root function is computed using the Newton-Raphson algorithm.
- * This is an iterative algorithm of the form:
- * <pre>
- *      x1 = x0 - f(x0)/f'(x0)
- * </pre>
- * where <code>x1</code> is the current estimate,
- * <code>x0</code> is the previous estimate, and
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
- * For the square root function, the algorithm reduces to:
- * <pre>
- *     x0 = in/2                         [initial guess]
- *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
- * </pre>
- */
-
-
-/**
- * @addtogroup SQRT
- * @{
- */
-
-/**
- * @brief  Floating-point square root function.
- * @param[in]  in    input value.
- * @param[out] pOut  square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
-CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
-    float32_t in,
-    float32_t* pOut)
-{
-    if (in >= 0.0f) {
-
-#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
-        *pOut = __sqrtf(in);
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-        *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined(__GNUC__)
-        *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
-        __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
-#else
-        *pOut = sqrtf(in);
-#endif
-
-        return (ARM_MATH_SUCCESS);
-    }
-    else {
-        *pOut = 0.0f;
-        return (ARM_MATH_ARGUMENT_ERROR);
-    }
-}
-
-
-/**
- * @brief Q31 square root function.
- * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
- * @param[out] pOut  square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
-arm_status arm_sqrt_q31(
-    q31_t in,
-    q31_t* pOut);
-
-
-/**
- * @brief  Q15 square root function.
- * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
- * @param[out] pOut  square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
-arm_status arm_sqrt_q15(
-    q15_t in,
-    q15_t* pOut);
-
-/**
- * @} end of SQRT group
- */
-
-
-/**
- * @brief floating-point Circular write function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
-    int32_t* circBuffer,
-    int32_t L,
-    uint16_t* writeOffset,
-    int32_t bufferInc,
-    const int32_t* src,
-    int32_t srcInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the input sample to the circular buffer */
-        circBuffer[wOffset] = *src;
-
-        /* Update the input pointer */
-        src += srcInc;
-
-        /* Circularly update wOffset.  Watch out for positive and negative value */
-        wOffset += bufferInc;
-        if (wOffset >= L)
-            wOffset -= L;
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-}
-
-
-
-/**
- * @brief floating-point Circular Read function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
-    int32_t* circBuffer,
-    int32_t L,
-    int32_t* readOffset,
-    int32_t bufferInc,
-    int32_t* dst,
-    int32_t* dst_base,
-    int32_t dst_length,
-    int32_t dstInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0u;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the sample from the circular buffer to the destination buffer */
-        *dst = circBuffer[rOffset];
-
-        /* Update the input pointer */
-        dst += dstInc;
-
-        if (dst == (int32_t*) dst_end) {
-            dst = dst_base;
-        }
-
-        /* Circularly update rOffset.  Watch out for positive and negative value  */
-        rOffset += bufferInc;
-
-        if (rOffset >= L) {
-            rOffset -= L;
-        }
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-}
-
-
-/**
- * @brief Q15 Circular write function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
-    q15_t* circBuffer,
-    int32_t L,
-    uint16_t* writeOffset,
-    int32_t bufferInc,
-    const q15_t* src,
-    int32_t srcInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the input sample to the circular buffer */
-        circBuffer[wOffset] = *src;
-
-        /* Update the input pointer */
-        src += srcInc;
-
-        /* Circularly update wOffset.  Watch out for positive and negative value */
-        wOffset += bufferInc;
-        if (wOffset >= L)
-            wOffset -= L;
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-}
-
-
-/**
- * @brief Q15 Circular Read function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
-    q15_t* circBuffer,
-    int32_t L,
-    int32_t* readOffset,
-    int32_t bufferInc,
-    q15_t* dst,
-    q15_t* dst_base,
-    int32_t dst_length,
-    int32_t dstInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the sample from the circular buffer to the destination buffer */
-        *dst = circBuffer[rOffset];
-
-        /* Update the input pointer */
-        dst += dstInc;
-
-        if (dst == (q15_t*) dst_end) {
-            dst = dst_base;
-        }
-
-        /* Circularly update wOffset.  Watch out for positive and negative value */
-        rOffset += bufferInc;
-
-        if (rOffset >= L) {
-            rOffset -= L;
-        }
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-}
-
-
-/**
- * @brief Q7 Circular write function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
-    q7_t* circBuffer,
-    int32_t L,
-    uint16_t* writeOffset,
-    int32_t bufferInc,
-    const q7_t* src,
-    int32_t srcInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the input sample to the circular buffer */
-        circBuffer[wOffset] = *src;
-
-        /* Update the input pointer */
-        src += srcInc;
-
-        /* Circularly update wOffset.  Watch out for positive and negative value */
-        wOffset += bufferInc;
-        if (wOffset >= L)
-            wOffset -= L;
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-}
-
-
-/**
- * @brief Q7 Circular Read function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
-    q7_t* circBuffer,
-    int32_t L,
-    int32_t* readOffset,
-    int32_t bufferInc,
-    q7_t* dst,
-    q7_t* dst_base,
-    int32_t dst_length,
-    int32_t dstInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the sample from the circular buffer to the destination buffer */
-        *dst = circBuffer[rOffset];
-
-        /* Update the input pointer */
-        dst += dstInc;
-
-        if (dst == (q7_t*) dst_end) {
-            dst = dst_base;
-        }
-
-        /* Circularly update rOffset.  Watch out for positive and negative value */
-        rOffset += bufferInc;
-
-        if (rOffset >= L) {
-            rOffset -= L;
-        }
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-}
-
-
-/**
- * @brief  Sum of the squares of the elements of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_power_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q63_t* pResult);
-
-
-/**
- * @brief  Sum of the squares of the elements of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_power_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult);
-
-
-/**
- * @brief  Sum of the squares of the elements of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_power_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q63_t* pResult);
-
-
-/**
- * @brief  Sum of the squares of the elements of a Q7 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_power_q7(
-    q7_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult);
-
-
-/**
- * @brief  Mean value of a Q7 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_mean_q7(
-    q7_t* pSrc,
-    uint32_t blockSize,
-    q7_t* pResult);
-
-
-/**
- * @brief  Mean value of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_mean_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult);
-
-
-/**
- * @brief  Mean value of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_mean_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult);
-
-
-/**
- * @brief  Mean value of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_mean_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult);
-
-
-/**
- * @brief  Variance of the elements of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_var_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult);
-
-
-/**
- * @brief  Variance of the elements of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_var_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult);
-
-
-/**
- * @brief  Variance of the elements of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_var_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult);
-
-
-/**
- * @brief  Root Mean Square of the elements of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_rms_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult);
-
-
-/**
- * @brief  Root Mean Square of the elements of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_rms_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult);
-
-
-/**
- * @brief  Root Mean Square of the elements of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_rms_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult);
-
-
-/**
- * @brief  Standard deviation of the elements of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_std_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult);
-
-
-/**
- * @brief  Standard deviation of the elements of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_std_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult);
-
-
-/**
- * @brief  Standard deviation of the elements of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_std_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult);
-
-
-/**
- * @brief  Floating-point complex magnitude
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q31 complex magnitude
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q15 complex magnitude
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q15 complex dot product
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[in]  numSamples  number of complex samples in each vector
- * @param[out] realResult  real part of the result returned here
- * @param[out] imagResult  imaginary part of the result returned here
- */
-void arm_cmplx_dot_prod_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    uint32_t numSamples,
-    q31_t* realResult,
-    q31_t* imagResult);
-
-
-/**
- * @brief  Q31 complex dot product
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[in]  numSamples  number of complex samples in each vector
- * @param[out] realResult  real part of the result returned here
- * @param[out] imagResult  imaginary part of the result returned here
- */
-void arm_cmplx_dot_prod_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    uint32_t numSamples,
-    q63_t* realResult,
-    q63_t* imagResult);
-
-
-/**
- * @brief  Floating-point complex dot product
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[in]  numSamples  number of complex samples in each vector
- * @param[out] realResult  real part of the result returned here
- * @param[out] imagResult  imaginary part of the result returned here
- */
-void arm_cmplx_dot_prod_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    uint32_t numSamples,
-    float32_t* realResult,
-    float32_t* imagResult);
-
-
-/**
- * @brief  Q15 complex-by-real multiplication
- * @param[in]  pSrcCmplx   points to the complex input vector
- * @param[in]  pSrcReal    points to the real input vector
- * @param[out] pCmplxDst   points to the complex output vector
- * @param[in]  numSamples  number of samples in each vector
- */
-void arm_cmplx_mult_real_q15(
-    q15_t* pSrcCmplx,
-    q15_t* pSrcReal,
-    q15_t* pCmplxDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q31 complex-by-real multiplication
- * @param[in]  pSrcCmplx   points to the complex input vector
- * @param[in]  pSrcReal    points to the real input vector
- * @param[out] pCmplxDst   points to the complex output vector
- * @param[in]  numSamples  number of samples in each vector
- */
-void arm_cmplx_mult_real_q31(
-    q31_t* pSrcCmplx,
-    q31_t* pSrcReal,
-    q31_t* pCmplxDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Floating-point complex-by-real multiplication
- * @param[in]  pSrcCmplx   points to the complex input vector
- * @param[in]  pSrcReal    points to the real input vector
- * @param[out] pCmplxDst   points to the complex output vector
- * @param[in]  numSamples  number of samples in each vector
- */
-void arm_cmplx_mult_real_f32(
-    float32_t* pSrcCmplx,
-    float32_t* pSrcReal,
-    float32_t* pCmplxDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Minimum value of a Q7 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] result     is output pointer
- * @param[in]  index      is the array index of the minimum value in the input buffer.
- */
-void arm_min_q7(
-    q7_t* pSrc,
-    uint32_t blockSize,
-    q7_t* result,
-    uint32_t* index);
-
-
-/**
- * @brief  Minimum value of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output pointer
- * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
- */
-void arm_min_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief  Minimum value of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output pointer
- * @param[out] pIndex     is the array index of the minimum value in the input buffer.
- */
-void arm_min_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief  Minimum value of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output pointer
- * @param[out] pIndex     is the array index of the minimum value in the input buffer.
- */
-void arm_min_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-void arm_max_q7(
-    q7_t* pSrc,
-    uint32_t blockSize,
-    q7_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-void arm_max_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-void arm_max_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-void arm_max_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief  Q15 complex-by-complex multiplication
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_mult_cmplx_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    q15_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q31 complex-by-complex multiplication
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_mult_cmplx_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    q31_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Floating-point complex-by-complex multiplication
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_mult_cmplx_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    float32_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief Converts the elements of the floating-point vector to Q31 vector.
- * @param[in]  pSrc       points to the floating-point input vector
- * @param[out] pDst       points to the Q31 output vector
- * @param[in]  blockSize  length of the input vector
- */
-void arm_float_to_q31(
-    float32_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Converts the elements of the floating-point vector to Q15 vector.
- * @param[in]  pSrc       points to the floating-point input vector
- * @param[out] pDst       points to the Q15 output vector
- * @param[in]  blockSize  length of the input vector
- */
-void arm_float_to_q15(
-    float32_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Converts the elements of the floating-point vector to Q7 vector.
- * @param[in]  pSrc       points to the floating-point input vector
- * @param[out] pDst       points to the Q7 output vector
- * @param[in]  blockSize  length of the input vector
- */
-void arm_float_to_q7(
-    float32_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Converts the elements of the Q31 vector to Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q31_to_q15(
-    q31_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Converts the elements of the Q31 vector to Q7 vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q31_to_q7(
-    q31_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Converts the elements of the Q15 vector to floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q15_to_float(
-    q15_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Converts the elements of the Q15 vector to Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q15_to_q31(
-    q15_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Converts the elements of the Q15 vector to Q7 vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q15_to_q7(
-    q15_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @ingroup groupInterpolation
- */
-
-/**
- * @defgroup BilinearInterpolate Bilinear Interpolation
- *
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
- * determines values between the grid points.
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
- * Bilinear interpolation is often used in image processing to rescale images.
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
- *
- * <b>Algorithm</b>
- * \par
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
- * For floating-point, the instance structure is defined as:
- * <pre>
- *   typedef struct
- *   {
- *     uint16_t numRows;
- *     uint16_t numCols;
- *     float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- * </pre>
- *
- * \par
- * where <code>numRows</code> specifies the number of rows in the table;
- * <code>numCols</code> specifies the number of columns in the table;
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
- *
- * \par
- * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
- * <pre>
- *     XF = floor(x)
- *     YF = floor(y)
- * </pre>
- * \par
- * The interpolated output point is computed as:
- * <pre>
- *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
- * </pre>
- * Note that the coordinates (x, y) contain integer and fractional components.
- * The integer components specify which portion of the table to use while the
- * fractional components control the interpolation processor.
- *
- * \par
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
- */
-
-/**
- * @addtogroup BilinearInterpolate
- * @{
- */
-
-
-/**
-*
-* @brief  Floating-point bilinear interpolation.
-* @param[in,out] S  points to an instance of the interpolation structure.
-* @param[in]     X  interpolation coordinate.
-* @param[in]     Y  interpolation coordinate.
-* @return out interpolated value.
-*/
-CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
-    const arm_bilinear_interp_instance_f32* S,
-    float32_t X,
-    float32_t Y)
-{
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t* pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) {
-        return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-}
-
-
-/**
-*
-* @brief  Q31 bilinear interpolation.
-* @param[in,out] S  points to an instance of the interpolation structure.
-* @param[in]     X  interpolation coordinate in 12.20 format.
-* @param[in]     Y  interpolation coordinate in 12.20 format.
-* @return out interpolated value.
-*/
-CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
-    arm_bilinear_interp_instance_q31* S,
-    q31_t X,
-    q31_t Y)
-{
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t* pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
-        return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
-    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
-    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return ((q31_t)(acc << 2));
-}
-
-
-/**
-* @brief  Q15 bilinear interpolation.
-* @param[in,out] S  points to an instance of the interpolation structure.
-* @param[in]     X  interpolation coordinate in 12.20 format.
-* @param[in]     Y  interpolation coordinate in 12.20 format.
-* @return out interpolated value.
-*/
-CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
-    arm_bilinear_interp_instance_q15* S,
-    q31_t X,
-    q31_t Y)
-{
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t* pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
-        return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return ((q15_t)(acc >> 36));
-}
-
-
-/**
-* @brief  Q7 bilinear interpolation.
-* @param[in,out] S  points to an instance of the interpolation structure.
-* @param[in]     X  interpolation coordinate in 12.20 format.
-* @param[in]     Y  interpolation coordinate in 12.20 format.
-* @return out interpolated value.
-*/
-CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
-    arm_bilinear_interp_instance_q7* S,
-    q31_t X,
-    q31_t Y)
-{
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t* pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
-        return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return ((q7_t)(acc >> 40));
-}
-
-/**
- * @} end of BilinearInterpolate group
- */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
-    a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
-    a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
-    a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if   defined ( __CC_ARM )
-/* Enter low optimization region - place directly above function definition */
-#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
-#define LOW_OPTIMIZATION_ENTER \
-    _Pragma ("push")         \
-    _Pragma ("O1")
-#else
-#define LOW_OPTIMIZATION_ENTER
-#endif
-
-/* Exit low optimization region - place directly after end of function definition */
-#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-#define LOW_OPTIMIZATION_EXIT \
-    _Pragma ("pop")
-#else
-#define LOW_OPTIMIZATION_EXIT
-#endif
-
-/* Enter low optimization region - place directly above function definition */
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-/* Exit low optimization region - place directly after end of function definition */
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
-#define LOW_OPTIMIZATION_ENTER \
-    __attribute__(( optimize("-O1") ))
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
-/* Enter low optimization region - place directly above function definition */
-#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-#define LOW_OPTIMIZATION_ENTER \
-    _Pragma ("optimize=low")
-#else
-#define LOW_OPTIMIZATION_ENTER
-#endif
-
-/* Exit low optimization region - place directly after end of function definition */
-#define LOW_OPTIMIZATION_EXIT
-
-/* Enter low optimization region - place directly above function definition */
-#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-    _Pragma ("optimize=low")
-#else
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#endif
-
-/* Exit low optimization region - place directly after end of function definition */
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#endif
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h
deleted file mode 100644
index 4617b1280..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armcc.h
+++ /dev/null
@@ -1,796 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_armcc.h
- * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
- * @version  V5.0.1
- * @date     03. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCC_H
-#define __CMSIS_ARMCC_H
-
-
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* CMSIS compiler control architecture macros */
-#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
-     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
-#define __ARM_ARCH_6M__           1
-#endif
-
-#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
-#define __ARM_ARCH_7M__           1
-#endif
-
-#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
-#define __ARM_ARCH_7EM__          1
-#endif
-
-/* __ARM_ARCH_8M_BASE__  not applicable */
-/* __ARM_ARCH_8M_MAIN__  not applicable */
-
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  __inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static __inline
-#endif
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __declspec(noreturn)
-#endif
-#ifndef   __USED
-#define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-#define __UNALIGNED_UINT32(x)     (*((__packed uint32_t *)(x)))
-#endif
-#ifndef   __ALIGNED
-#define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __attribute__((packed))
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           __packed struct
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();     */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();    */
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-    register uint32_t __regControl         __ASM("control");
-    return(__regControl);
-}
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-    register uint32_t __regControl         __ASM("control");
-    __regControl = control;
-}
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-    register uint32_t __regIPSR          __ASM("ipsr");
-    return(__regIPSR);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-    register uint32_t __regAPSR          __ASM("apsr");
-    return(__regAPSR);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-    register uint32_t __regXPSR          __ASM("xpsr");
-    return(__regXPSR);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-    register uint32_t __regProcessStackPointer  __ASM("psp");
-    return(__regProcessStackPointer);
-}
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-    register uint32_t __regProcessStackPointer  __ASM("psp");
-    __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-    register uint32_t __regMainStackPointer     __ASM("msp");
-    return(__regMainStackPointer);
-}
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-    register uint32_t __regMainStackPointer     __ASM("msp");
-    __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-    register uint32_t __regPriMask         __ASM("primask");
-    return(__regPriMask);
-}
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-    register uint32_t __regPriMask         __ASM("primask");
-    __regPriMask = (priMask);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-    register uint32_t __regBasePri         __ASM("basepri");
-    return(__regBasePri);
-}
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-    register uint32_t __regBasePri         __ASM("basepri");
-    __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-    register uint32_t __regBasePriMax      __ASM("basepri_max");
-    __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-    register uint32_t __regFaultMask       __ASM("faultmask");
-    return(__regFaultMask);
-}
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-    register uint32_t __regFaultMask       __ASM("faultmask");
-    __regFaultMask = (faultMask & (uint32_t)1U);
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    register uint32_t __regfpscr         __ASM("fpscr");
-    return(__regfpscr);
-#else
-    return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    register uint32_t __regfpscr         __ASM("fpscr");
-    __regfpscr = (fpscr);
-#else
-    (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB() do {\
-        __schedule_barrier();\
-        __isb(0xF);\
-        __schedule_barrier();\
-    } while (0U)
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
-        __schedule_barrier();\
-        __dsb(0xF);\
-        __schedule_barrier();\
-    } while (0U)
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
-        __schedule_barrier();\
-        __dmb(0xF);\
-        __schedule_barrier();\
-    } while (0U)
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-    rev16 r0, r0
-    bx lr
-}
-#endif
-
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-    revsh r0, r0
-    bx lr
-}
-#endif
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-#define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-    uint32_t result;
-    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
-    result = value;                      /* r will be reversed bits of v; first get LSB of v */
-    for (value >>= 1U; value; value >>= 1U) {
-        result <<= 1U;
-        result |= value & 1U;
-        s--;
-    }
-    result <<= s;                        /* shift when v's highest bits are zero */
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
-#else
-#define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
-#else
-#define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
-#else
-#define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __STREXB(value, ptr)                                                 __strex(value, ptr)
-#else
-#define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __STREXH(value, ptr)                                                 __strex(value, ptr)
-#else
-#define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __STREXW(value, ptr)                                                 __strex(value, ptr)
-#else
-#define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX                           __clrex
-
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-    rrx r0, r0
-    bx lr
-}
-#endif
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h
deleted file mode 100644
index 6b21a5bea..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_armclang.h
+++ /dev/null
@@ -1,1735 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_armclang.h
- * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
- * @version  V5.0.1
- * @date     02. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCLANG_H
-#define __CMSIS_ARMCLANG_H
-
-#ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  __inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static __inline
-#endif
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __attribute__((noreturn))
-#endif
-#ifndef   __USED
-#define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-#pragma clang diagnostic push
-#pragma clang diagnostic ignored "-Wpacked"
-struct __attribute__((packed)) T_UINT32 {
-    uint32_t v;
-};
-#pragma clang diagnostic pop
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           struct __attribute__((packed, aligned(1)))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, control" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-    __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-    __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-    __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-    __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msp" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-    __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-    __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, primask" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-    __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-    __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-    __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-    __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-    return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-    __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-    __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
-    return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-    __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-    __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-/* #define __get_FPSCR      __builtin_arm_get_fpscr */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    uint32_t result;
-
-    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-    return(result);
-#else
-    return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-/* #define __set_FPSCR      __builtin_arm_set_fpscr */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
-#else
-    (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP          __builtin_arm_nop
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI          __builtin_arm_wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE          __builtin_arm_wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV          __builtin_arm_sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB()        __builtin_arm_isb(0xF);
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()        __builtin_arm_dsb(0xF);
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB()        __builtin_arm_dmb(0xF);
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV          __builtin_bswap32
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV16          __builtin_bswap16                /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
-#if 0
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-    uint32_t result;
-
-    __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-    int32_t result;
-
-    __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-    return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-    uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
-    result = value;                      /* r will be reversed bits of v; first get LSB of v */
-    for (value >>= 1U; value; value >>= 1U) {
-        result <<= 1U;
-        result |= value & 1U;
-        s--;
-    }
-    result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-    return(result);
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB        (uint8_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH        (uint16_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW        (uint32_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXB        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXH        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXW        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX             __builtin_arm_clrex
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT             __builtin_arm_ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT             __builtin_arm_usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-    uint32_t result;
-
-    __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
-{
-    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
-{
-    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
-{
-    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
-{
-    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
-{
-    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
-{
-    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEX                  (uint32_t)__builtin_arm_stlex
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-    ({                          \
-        int32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-#define __USAT16(ARG1,ARG2) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-    uint32_t result;
-
-    __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-    uint32_t result;
-
-    __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-    int32_t result;
-
-    __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-    int32_t result;
-
-    __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-        __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-        __RES; \
-    })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-        if (ARG3 == 0) \
-            __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-        else \
-            __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-        __RES; \
-    })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
-    int32_t result;
-
-    __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCLANG_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h
deleted file mode 100644
index 89cd69027..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_compiler.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_compiler.h
- * @brief    CMSIS compiler generic header file
- * @version  V5.0.1
- * @date     30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_COMPILER_H
-#define __CMSIS_COMPILER_H
-
-#include <stdint.h>
-
-/*
- * ARM Compiler 4/5
- */
-#if   defined ( __CC_ARM )
-#include "cmsis_armcc.h"
-
-
-/*
- * ARM Compiler 6 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#include "cmsis_armclang.h"
-
-
-/*
- * GNU Compiler
- */
-#elif defined ( __GNUC__ )
-#include "cmsis_gcc.h"
-
-
-/*
- * IAR Compiler
- */
-#elif defined ( __ICCARM__ )
-
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static inline
-#endif
-
-#include <cmsis_iar.h>
-
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __noreturn
-#endif
-#ifndef   __USED
-#define __USED                    __root
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __weak
-#endif
-#ifndef   __UNALIGNED_UINT32
-__packed struct T_UINT32 {
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-#define __ALIGNED(x)
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __packed
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           __packed struct
-#endif
-
-
-/*
- * TI ARM Compiler
- */
-#elif defined ( __TI_ARM__ )
-#include <cmsis_ccs.h>
-
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static inline
-#endif
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __attribute__((noreturn))
-#endif
-#ifndef   __USED
-#define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-struct __attribute__((packed)) T_UINT32 {
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __attribute__((packed))
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           struct __attribute__((packed))
-#endif
-
-
-/*
- * TASKING Compiler
- */
-#elif defined ( __TASKING__ )
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static inline
-#endif
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __attribute__((noreturn))
-#endif
-#ifndef   __USED
-#define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-struct __packed__ T_UINT32 {
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#define __ALIGNED(x)              __align(x)
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __packed__
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           struct __packed__
-#endif
-
-
-/*
- * COSMIC Compiler
- */
-#elif defined ( __CSMC__ )
-#include <cmsis_csm.h>
-
-#ifndef   __ASM
-#define __ASM                     _asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static inline
-#endif
-#ifndef   __NO_RETURN
-// NO RETURN is automatically detected hence no warning here
-#define __NO_RETURN
-#endif
-#ifndef   __USED
-#warning No compiler specific solution for __USED. __USED is ignored.
-#define __USED
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __weak
-#endif
-#ifndef   __UNALIGNED_UINT32
-@packed struct T_UINT32 {
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-#define __ALIGNED(x)
-#endif
-#ifndef   __PACKED
-#define __PACKED                  @packed
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           @packed struct
-#endif
-
-
-#else
-#error Unknown compiler.
-#endif
-
-
-#endif /* __CMSIS_COMPILER_H */
-
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h
deleted file mode 100644
index 919f26d15..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/cmsis_gcc.h
+++ /dev/null
@@ -1,1900 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_gcc.h
- * @brief    CMSIS compiler GCC header file
- * @version  V5.0.1
- * @date     02. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static inline
-#endif
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __attribute__((noreturn))
-#endif
-#ifndef   __USED
-#define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpacked"
-#pragma GCC diagnostic ignored "-Wattributes"
-struct __attribute__((packed)) T_UINT32 {
-    uint32_t v;
-};
-#pragma GCC diagnostic pop
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           struct __attribute__((packed, aligned(1)))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
-{
-    __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
-{
-    __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, control" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-    __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-    __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-    __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-    __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msp" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-    __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-    __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, primask" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-    __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-    __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
-{
-    __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
-{
-    __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-    __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-    __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-    return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-    __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-    __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
-    return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-    __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-    __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    uint32_t result;
-
-    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-    return(result);
-#else
-    return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#else
-    (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-//{
-//  __ASM volatile ("nop");
-//}
-#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-//{
-//  __ASM volatile ("wfi");
-//}
-#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-//{
-//  __ASM volatile ("wfe");
-//}
-#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-//{
-//  __ASM volatile ("sev");
-//}
-#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
-    __ASM volatile ("isb 0xF"::: "memory");
-}
-
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
-    __ASM volatile ("dsb 0xF"::: "memory");
-}
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
-    __ASM volatile ("dmb 0xF"::: "memory");
-}
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-    return __builtin_bswap32(value);
-#else
-    uint32_t result;
-
-    __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-#endif
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-    uint32_t result;
-
-    __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-}
-
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    return (short)__builtin_bswap16(value);
-#else
-    int32_t result;
-
-    __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-#endif
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-    return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-    uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
-    result = value;                      /* r will be reversed bits of v; first get LSB of v */
-    for (value >>= 1U; value; value >>= 1U) {
-        result <<= 1U;
-        result |= value & 1U;
-        s--;
-    }
-    result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-    return(result);
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-    return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-    return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-    return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr)
-{
-    uint32_t result;
-
-    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-    return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr)
-{
-    uint32_t result;
-
-    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-    return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr)
-{
-    uint32_t result;
-
-    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-    return(result);
-}
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
-    __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-    ({                          \
-        int32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-    uint32_t result;
-
-    __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-    return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-    return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
-{
-    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
-{
-    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
-{
-    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
-{
-    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
-{
-    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
-{
-    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-    return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-    return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-    return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-    ({                          \
-        int32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-#define __USAT16(ARG1,ARG2) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-    uint32_t result;
-
-    __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-    uint32_t result;
-
-    __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-    int32_t result;
-
-    __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-    int32_t result;
-
-    __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-        __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-        __RES; \
-    })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-        if (ARG3 == 0) \
-            __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-        else \
-            __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-        __RES; \
-    })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
-    int32_t result;
-
-    __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h
deleted file mode 100644
index 4e65d1d95..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mbl.h
+++ /dev/null
@@ -1,1813 +0,0 @@
-/**************************************************************************//**
- * @file     core_armv8mbl.h
- * @brief    CMSIS ARMv8MBL Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MBL_H_GENERIC
-#define __CORE_ARMV8MBL_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_ARMv8MBL
-  @{
- */
-
-/*  CMSIS cmGrebe definitions */
-#define __ARMv8MBL_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
-#define __ARMv8MBL_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
-                                        __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MBL_H_DEPENDANT
-#define __CORE_ARMV8MBL_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __ARMv8MBL_REV
-#define __ARMv8MBL_REV               0x0000U
-#warning "__ARMv8MBL_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __SAUREGION_PRESENT
-#define __SAUREGION_PRESENT       0U
-#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __VTOR_PRESENT
-#define __VTOR_PRESENT            0U
-#warning "__VTOR_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          2U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-
-#ifndef __ETM_PRESENT
-#define __ETM_PRESENT             0U
-#warning "__ETM_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MTB_PRESENT
-#define __MTB_PRESENT             0U
-#warning "__MTB_PRESENT not defined in device header file; using default!"
-#endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MBL */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[16U];
-    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[16U];
-    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[16U];
-    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[16U];
-    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[16U];
-    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-    uint32_t RESERVED5[16U];
-    __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-    uint32_t RESERVED0;
-#endif
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    uint32_t RESERVED1;
-    __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    uint32_t RESERVED0[6U];
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    uint32_t RESERVED3[1U];
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    uint32_t RESERVED5[1U];
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED6[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    uint32_t RESERVED7[1U];
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-    uint32_t RESERVED9[1U];
-    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-    uint32_t RESERVED10[1U];
-    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-    uint32_t RESERVED11[1U];
-    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-    uint32_t RESERVED12[1U];
-    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-    uint32_t RESERVED13[1U];
-    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-    uint32_t RESERVED14[1U];
-    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-    uint32_t RESERVED15[1U];
-    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-    uint32_t RESERVED16[1U];
-    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-    uint32_t RESERVED17[1U];
-    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-    uint32_t RESERVED18[1U];
-    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-    uint32_t RESERVED19[1U];
-    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-    uint32_t RESERVED20[1U];
-    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-    uint32_t RESERVED21[1U];
-    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-    uint32_t RESERVED22[1U];
-    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-    uint32_t RESERVED23[1U];
-    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-    uint32_t RESERVED24[1U];
-    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-    uint32_t RESERVED25[1U];
-    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-    uint32_t RESERVED26[1U];
-    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-    uint32_t RESERVED27[1U];
-    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-    uint32_t RESERVED28[1U];
-    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-    uint32_t RESERVED29[1U];
-    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-    uint32_t RESERVED30[1U];
-    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-    uint32_t RESERVED31[1U];
-    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-    uint32_t RESERVED0[7U];
-    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-#endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for ARMv8-M Baseline */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for ARMv8-M Baseline */
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   SCB_AIRCR_SYSRESETREQ_Msk);
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                         /* Reload value impossible */
-    }
-
-    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk   |
-                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h
deleted file mode 100644
index 273c3849c..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_armv8mml.h
+++ /dev/null
@@ -1,2821 +0,0 @@
-/**************************************************************************//**
- * @file     core_armv8mml.h
- * @brief    CMSIS ARMv8MML Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     07. December 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MML_H_GENERIC
-#define __CORE_ARMV8MML_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_ARMv8MML
-  @{
- */
-
-/*  CMSIS ARMv8MML definitions */
-#define __ARMv8MML_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
-#define __ARMv8MML_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
-                                        __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MML_H_DEPENDANT
-#define __CORE_ARMV8MML_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __ARMv8MML_REV
-#define __ARMv8MML_REV               0x0000U
-#warning "__ARMv8MML_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __SAUREGION_PRESENT
-#define __SAUREGION_PRESENT       0U
-#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __DSP_PRESENT
-#define __DSP_PRESENT             0U
-#warning "__DSP_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MML */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0) */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
-        uint32_t FPCA: 1;                    /*!< bit:      2  Floating-point context active */
-        uint32_t SFPA: 1;                    /*!< bit:      3  Secure floating-point active */
-        uint32_t _reserved1: 28;             /*!< bit:  4..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[16U];
-    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[16U];
-    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[16U];
-    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[16U];
-    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[16U];
-    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-    uint32_t RESERVED5[16U];
-    __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED6[580U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-    __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-    uint32_t RESERVED3[92U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-    uint32_t RESERVED4[15U];
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
-    uint32_t RESERVED5[1U];
-    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-    uint32_t RESERVED6[1U];
-    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-    uint32_t RESERVED7[6U];
-    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-    __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[1U];
-    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
-    uint32_t RESERVED6[4U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    uint32_t RESERVED3[1U];
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    uint32_t RESERVED5[1U];
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED6[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    uint32_t RESERVED7[1U];
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-    uint32_t RESERVED9[1U];
-    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-    uint32_t RESERVED10[1U];
-    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-    uint32_t RESERVED11[1U];
-    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-    uint32_t RESERVED12[1U];
-    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-    uint32_t RESERVED13[1U];
-    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-    uint32_t RESERVED14[1U];
-    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-    uint32_t RESERVED15[1U];
-    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-    uint32_t RESERVED16[1U];
-    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-    uint32_t RESERVED17[1U];
-    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-    uint32_t RESERVED18[1U];
-    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-    uint32_t RESERVED19[1U];
-    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-    uint32_t RESERVED20[1U];
-    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-    uint32_t RESERVED21[1U];
-    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-    uint32_t RESERVED22[1U];
-    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-    uint32_t RESERVED23[1U];
-    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-    uint32_t RESERVED24[1U];
-    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-    uint32_t RESERVED25[1U];
-    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-    uint32_t RESERVED26[1U];
-    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-    uint32_t RESERVED27[1U];
-    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-    uint32_t RESERVED28[1U];
-    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-    uint32_t RESERVED29[1U];
-    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-    uint32_t RESERVED30[1U];
-    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-    uint32_t RESERVED31[1U];
-    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-    uint32_t RESERVED32[934U];
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-    uint32_t RESERVED33[1U];
-    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
-    __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
-    __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
-    __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
-    uint32_t RESERVED0[1];
-    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#else
-    uint32_t RESERVED0[3];
-#endif
-    __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
-    __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-#define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
-#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-#endif
-
-#define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
-#define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Set Priority Grouping (non-secure)
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB_NS->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping (non-secure)
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
-    return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    uint32_t mvfr0;
-
-    mvfr0 = FPU->MVFR0;
-    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
-        return 2U;           /* Double + Single precision FPU */
-    }
-    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
-        return 1U;           /* Single precision FPU */
-    }
-    else {
-        return 0U;           /* No FPU */
-    }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                         /* Reload value impossible */
-    }
-
-    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk   |
-                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h
deleted file mode 100644
index d06d984b7..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0.h
+++ /dev/null
@@ -1,850 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM0_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM0_REV
-#define __CM0_REV               0x0000U
-#warning "__CM0_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          2U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 1;              /*!< bit:      0  Reserved */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[31U];
-    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[31U];
-    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[31U];
-    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[31U];
-    uint32_t RESERVED4[64U];
-    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    uint32_t RESERVED0;
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    uint32_t RESERVED1;
-    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           Address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)0x0U;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)0x0U;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   SCB_AIRCR_SYSRESETREQ_Msk);
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h
deleted file mode 100644
index ebc43f3a1..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm0plus.h
+++ /dev/null
@@ -1,975 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0+ definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB  ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
-                                      __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM0PLUS_REV
-#define __CM0PLUS_REV             0x0000U
-#warning "__CM0PLUS_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __VTOR_PRESENT
-#define __VTOR_PRESENT            0U
-#warning "__VTOR_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          2U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[31U];
-    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[31U];
-    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[31U];
-    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[31U];
-    uint32_t RESERVED4[64U];
-    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-    uint32_t RESERVED0;
-#endif
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    uint32_t RESERVED1;
-    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0+ header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0+ */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0+ */
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   SCB_AIRCR_SYSRESETREQ_Msk);
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h
deleted file mode 100644
index 513635a58..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm23.h
+++ /dev/null
@@ -1,1813 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm23.h
- * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM23_H_GENERIC
-#define __CORE_CM23_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M23
-  @{
- */
-
-/*  CMSIS cmGrebe definitions */
-#define __CM23_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM23_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM23_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                     (23U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM23_H_DEPENDANT
-#define __CORE_CM23_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM23_REV
-#define __CM23_REV                0x0000U
-#warning "__CM23_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __SAUREGION_PRESENT
-#define __SAUREGION_PRESENT       0U
-#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __VTOR_PRESENT
-#define __VTOR_PRESENT            0U
-#warning "__VTOR_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          2U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-
-#ifndef __ETM_PRESENT
-#define __ETM_PRESENT             0U
-#warning "__ETM_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MTB_PRESENT
-#define __MTB_PRESENT             0U
-#warning "__MTB_PRESENT not defined in device header file; using default!"
-#endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M23 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[16U];
-    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[16U];
-    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[16U];
-    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[16U];
-    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[16U];
-    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-    uint32_t RESERVED5[16U];
-    __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-    uint32_t RESERVED0;
-#endif
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    uint32_t RESERVED1;
-    __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    uint32_t RESERVED0[6U];
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    uint32_t RESERVED3[1U];
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    uint32_t RESERVED5[1U];
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED6[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    uint32_t RESERVED7[1U];
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-    uint32_t RESERVED9[1U];
-    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-    uint32_t RESERVED10[1U];
-    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-    uint32_t RESERVED11[1U];
-    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-    uint32_t RESERVED12[1U];
-    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-    uint32_t RESERVED13[1U];
-    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-    uint32_t RESERVED14[1U];
-    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-    uint32_t RESERVED15[1U];
-    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-    uint32_t RESERVED16[1U];
-    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-    uint32_t RESERVED17[1U];
-    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-    uint32_t RESERVED18[1U];
-    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-    uint32_t RESERVED19[1U];
-    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-    uint32_t RESERVED20[1U];
-    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-    uint32_t RESERVED21[1U];
-    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-    uint32_t RESERVED22[1U];
-    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-    uint32_t RESERVED23[1U];
-    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-    uint32_t RESERVED24[1U];
-    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-    uint32_t RESERVED25[1U];
-    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-    uint32_t RESERVED26[1U];
-    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-    uint32_t RESERVED27[1U];
-    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-    uint32_t RESERVED28[1U];
-    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-    uint32_t RESERVED29[1U];
-    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-    uint32_t RESERVED30[1U];
-    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-    uint32_t RESERVED31[1U];
-    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-    uint32_t RESERVED0[7U];
-    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-#endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   SCB_AIRCR_SYSRESETREQ_Msk);
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                         /* Reload value impossible */
-    }
-
-    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk   |
-                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h
deleted file mode 100644
index 8cbf329b8..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm3.h
+++ /dev/null
@@ -1,1880 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M3
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM3_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM3_REV
-#define __CM3_REV               0x0200U
-#warning "__CM3_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
-        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
-        uint32_t _reserved1: 8;              /*!< bit: 16..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
-        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[24U];
-    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[24U];
-    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[24U];
-    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[24U];
-    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[56U];
-    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED5[644U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    uint32_t RESERVED0[5U];
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-#else
-    uint32_t RESERVED1[1U];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[6U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-#endif
-#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-#endif
-#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h
deleted file mode 100644
index 00de7795e..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm33.h
+++ /dev/null
@@ -1,2821 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm33.h
- * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     07. December 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM33_H_GENERIC
-#define __CORE_CM33_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M33
-  @{
- */
-
-/*  CMSIS CM33 definitions */
-#define __CM33_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM33_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM33_CMSIS_VERSION_SUB           )     /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM33_H_DEPENDANT
-#define __CORE_CM33_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM33_REV
-#define __CM33_REV                0x0000U
-#warning "__CM33_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __SAUREGION_PRESENT
-#define __SAUREGION_PRESENT       0U
-#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __DSP_PRESENT
-#define __DSP_PRESENT             0U
-#warning "__DSP_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M33 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0) */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
-        uint32_t FPCA: 1;                    /*!< bit:      2  Floating-point context active */
-        uint32_t SFPA: 1;                    /*!< bit:      3  Secure floating-point active */
-        uint32_t _reserved1: 28;             /*!< bit:  4..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[16U];
-    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[16U];
-    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[16U];
-    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[16U];
-    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[16U];
-    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-    uint32_t RESERVED5[16U];
-    __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED6[580U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-    __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-    uint32_t RESERVED3[92U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-    uint32_t RESERVED4[15U];
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
-    uint32_t RESERVED5[1U];
-    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-    uint32_t RESERVED6[1U];
-    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-    uint32_t RESERVED7[6U];
-    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-    __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[1U];
-    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
-    uint32_t RESERVED6[4U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    uint32_t RESERVED3[1U];
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    uint32_t RESERVED5[1U];
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED6[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    uint32_t RESERVED7[1U];
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-    uint32_t RESERVED9[1U];
-    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-    uint32_t RESERVED10[1U];
-    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-    uint32_t RESERVED11[1U];
-    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-    uint32_t RESERVED12[1U];
-    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-    uint32_t RESERVED13[1U];
-    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-    uint32_t RESERVED14[1U];
-    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-    uint32_t RESERVED15[1U];
-    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-    uint32_t RESERVED16[1U];
-    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-    uint32_t RESERVED17[1U];
-    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-    uint32_t RESERVED18[1U];
-    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-    uint32_t RESERVED19[1U];
-    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-    uint32_t RESERVED20[1U];
-    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-    uint32_t RESERVED21[1U];
-    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-    uint32_t RESERVED22[1U];
-    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-    uint32_t RESERVED23[1U];
-    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-    uint32_t RESERVED24[1U];
-    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-    uint32_t RESERVED25[1U];
-    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-    uint32_t RESERVED26[1U];
-    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-    uint32_t RESERVED27[1U];
-    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-    uint32_t RESERVED28[1U];
-    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-    uint32_t RESERVED29[1U];
-    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-    uint32_t RESERVED30[1U];
-    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-    uint32_t RESERVED31[1U];
-    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-    uint32_t RESERVED32[934U];
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-    uint32_t RESERVED33[1U];
-    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
-    __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
-    __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
-    __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
-    uint32_t RESERVED0[1];
-    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#else
-    uint32_t RESERVED0[3];
-#endif
-    __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
-    __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-#define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
-#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-#endif
-
-#define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
-#define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Set Priority Grouping (non-secure)
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB_NS->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping (non-secure)
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
-    return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    uint32_t mvfr0;
-
-    mvfr0 = FPU->MVFR0;
-    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
-        return 2U;           /* Double + Single precision FPU */
-    }
-    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
-        return 1U;           /* Single precision FPU */
-    }
-    else {
-        return 0U;           /* No FPU */
-    }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                         /* Reload value impossible */
-    }
-
-    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk   |
-                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h
deleted file mode 100644
index f4c8011f8..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm4.h
+++ /dev/null
@@ -1,2061 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM4_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM4_REV
-#define __CM4_REV               0x0000U
-#warning "__CM4_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
-        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
-        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag */
-        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[24U];
-    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[24U];
-    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[24U];
-    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[24U];
-    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[56U];
-    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED5[644U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    uint32_t RESERVED0[5U];
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[6U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-#endif
-#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-#endif
-#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    uint32_t mvfr0;
-
-    mvfr0 = FPU->MVFR0;
-    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
-        return 1U;           /* Single precision FPU */
-    }
-    else {
-        return 0U;           /* No FPU */
-    }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h
deleted file mode 100644
index c09acc824..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_cm7.h
+++ /dev/null
@@ -1,2592 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm7.h
- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M7
-  @{
- */
-
-/*  CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM7_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM7_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM7_REV
-#define __CM7_REV               0x0000U
-#warning "__CM7_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __ICACHE_PRESENT
-#define __ICACHE_PRESENT          0U
-#warning "__ICACHE_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __DCACHE_PRESENT
-#define __DCACHE_PRESENT          0U
-#warning "__DCACHE_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __DTCM_PRESENT
-#define __DTCM_PRESENT            0U
-#warning "__DTCM_PRESENT        not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
-        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
-        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag */
-        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[24U];
-    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[24U];
-    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[24U];
-    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[24U];
-    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[56U];
-    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED5[644U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-    uint32_t RESERVED3[93U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-    uint32_t RESERVED4[15U];
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
-    uint32_t RESERVED5[1U];
-    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-    uint32_t RESERVED6[1U];
-    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-    uint32_t RESERVED7[6U];
-    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[6U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-    uint32_t RESERVED3[981U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-    __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 Definitions */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    uint32_t mvfr0;
-
-    mvfr0 = SCB->MVFR0;
-    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
-        return 2U;           /* Double + Single precision FPU */
-    }
-    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
-        return 1U;           /* Single precision FPU */
-    }
-    else {
-        return 0U;           /* No FPU */
-    }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################  Cache functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_CacheFunctions Cache Functions
-  \brief    Functions that configure Instruction and Data cache.
-  @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
-
-
-/**
-  \brief   Enable I-Cache
-  \details Turns on I-Cache
-  */
-__STATIC_INLINE void SCB_EnableICache (void)
-{
-#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
-    __DSB();
-    __ISB();
-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Disable I-Cache
-  \details Turns off I-Cache
-  */
-__STATIC_INLINE void SCB_DisableICache (void)
-{
-#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Invalidate I-Cache
-  \details Invalidates I-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateICache (void)
-{
-#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Enable D-Cache
-  \details Turns on D-Cache
-  */
-__STATIC_INLINE void SCB_EnableDCache (void)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    /* invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-        do {
-            SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
-                          ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
-#if defined ( __CC_ARM )
-            __schedule_barrier();
-#endif
-        } while (ways-- != 0U);
-    } while(sets-- != 0U);
-    __DSB();
-
-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Disable D-Cache
-  \details Turns off D-Cache
-  */
-__STATIC_INLINE void SCB_DisableDCache (void)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    register uint32_t ccsidr;
-    register uint32_t sets;
-    register uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    /* clean & invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-        do {
-            SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
-                           ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
-#if defined ( __CC_ARM )
-            __schedule_barrier();
-#endif
-        } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Invalidate D-Cache
-  \details Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    /* invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-        do {
-            SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
-                          ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
-#if defined ( __CC_ARM )
-            __schedule_barrier();
-#endif
-        } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Clean D-Cache
-  \details Cleans D-Cache
-  */
-__STATIC_INLINE void SCB_CleanDCache (void)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    /* clean D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-        do {
-            SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
-                          ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
-#if defined ( __CC_ARM )
-            __schedule_barrier();
-#endif
-        } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Clean & Invalidate D-Cache
-  \details Cleans and Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    /* clean & invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-        do {
-            SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
-                           ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
-#if defined ( __CC_ARM )
-            __schedule_barrier();
-#endif
-        } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   D-Cache Invalidate by address
-  \details Invalidates D-Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t)addr;
-    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-        SCB->DCIMVAC = op_addr;
-        op_addr += (uint32_t)linesize;
-        op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   D-Cache Clean by address
-  \details Cleans D-Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t* addr, int32_t dsize)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-        SCB->DCCMVAC = op_addr;
-        op_addr += (uint32_t)linesize;
-        op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   D-Cache Clean and Invalidate by address
-  \details Cleans and invalidates D_Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-        SCB->DCCIMVAC = op_addr;
-        op_addr += (uint32_t)linesize;
-        op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h
deleted file mode 100644
index ed1063364..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc000.h
+++ /dev/null
@@ -1,976 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc000.h
- * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup SC000
-  @{
- */
-
-/*  CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
-                                     __SC000_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __SC000_REV
-#define __SC000_REV             0x0000U
-#warning "__SC000_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          2U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 1;              /*!< bit:      0  Reserved */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[31U];
-    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[31U];
-    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[31U];
-    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[31U];
-    uint32_t RESERVED4[64U];
-    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    uint32_t RESERVED1[154U];
-    __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the SC000 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   SCB_AIRCR_SYSRESETREQ_Msk);
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h
deleted file mode 100644
index a1b17e1ce..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/core_sc300.h
+++ /dev/null
@@ -1,1851 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc300.h
- * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup SC3000
-  @{
- */
-
-/*  CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
-                                     __SC300_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC300_H_DEPENDANT
-#define __CORE_SC300_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __SC300_REV
-#define __SC300_REV               0x0000U
-#warning "__SC300_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC300 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
-        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
-        uint32_t _reserved1: 8;              /*!< bit: 16..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
-        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[24U];
-    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[24U];
-    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[24U];
-    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[24U];
-    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[56U];
-    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED5[644U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    uint32_t RESERVED0[5U];
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-    uint32_t RESERVED1[129U];
-    __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-    uint32_t RESERVED1[1U];
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[6U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h b/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h
deleted file mode 100644
index cd6d8ab07..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/IAR_Core/tz_context.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * ----------------------------------------------------------------------------
- *
- * $Date:        21. September 2016
- * $Revision:    V1.0
- *
- * Project:      TrustZone for ARMv8-M
- * Title:        Context Management for ARMv8-M TrustZone
- *
- * Version 1.0
- *    Initial Release
- *---------------------------------------------------------------------------*/
-
-#ifndef TZ_CONTEXT_H
-#define TZ_CONTEXT_H
-
-#include <stdint.h>
-
-#ifndef TZ_MODULEID_T
-#define TZ_MODULEID_T
-/// \details Data type that identifies secure software modules called by a process.
-typedef uint32_t TZ_ModuleId_t;
-#endif
-
-/// \details TZ Memory ID identifies an allocated memory slot.
-typedef uint32_t TZ_MemoryId_t;
-
-/// Initialize secure context memory system
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_InitContextSystem_S (void);
-
-/// Allocate context memory for calling secure software modules in TrustZone
-/// \param[in]  module   identifies software modules called from non-secure mode
-/// \return value != 0 id TrustZone memory slot identifier
-/// \return value 0    no memory available or internal error
-TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
-
-/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
-
-/// Load secure context (called on RTOS thread context switch)
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
-
-/// Store secure context (called on RTOS thread context switch)
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
-
-#endif  // TZ_CONTEXT_H
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h
deleted file mode 100644
index dfea7460e..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_common_tables.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_common_tables.h
- * Description:  Extern declaration for common tables
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
-#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
-#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
-#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
-#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
-#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
-#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
-#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /*  ARM_COMMON_TABLES_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h
deleted file mode 100644
index 84ffe8b85..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_const_structs.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_const_structs.h
- * Description:  Constant structs that are initialized for user convenience.
- *               For example, some can be given as arguments to the arm_cfft_f32() function.
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h
deleted file mode 100644
index 9d678052b..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/arm_math.h
+++ /dev/null
@@ -1,7122 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_math.h
- * Description:  Public header file for CMSIS DSP Library
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * Introduction
-   * ------------
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * Using the Library
-   * ------------
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
-   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
-   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
-   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
-   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
-   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
-   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
-   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
-   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
-   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
-   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
-   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
-   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
-   * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
-   * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
-   * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
-   * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
-   * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
-   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
-   * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
-   * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
-   *
-   *
-   * Examples
-   * --------
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * Toolchain Support
-   * ------------
-   *
-   * The library has been developed and tested with MDK-ARM version 5.14.0.0
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * Building the Library
-   * ------------
-   *
-   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
-   * - arm_cortexM_math.uvprojx
-   *
-   *
-   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
-   *
-   * Pre-processor Macros
-   * ------------
-   *
-   * Each library project have differant pre-processor macros.
-   *
-   * - UNALIGNED_SUPPORT_DISABLE:
-   *
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_CMx:
-   *
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
-   * ARM_MATH_CM7 for building the library on cortex-M7.
-   *
-   * - ARM_MATH_ARMV8MxL:
-   *
-   * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
-   * on ARMv8M Mainline target.
-   *
-   * - __FPU_PRESENT:
-   *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
-   *
-   * - __DSP_PRESENT:
-   *
-   * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
-   *
-   * <hr>
-   * CMSIS-DSP in ARM::CMSIS Pack
-   * -----------------------------
-   *
-   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
-   * |File/Folder                   |Content                                                                 |
-   * |------------------------------|------------------------------------------------------------------------|
-   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
-   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
-   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
-   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
-   *
-   * <hr>
-   * Revision History of CMSIS-DSP
-   * ------------
-   * Please refer to \ref ChangeLog_pg.
-   *
-   * Copyright Notice
-   * ------------
-   *
-   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* ignore some GCC warnings */
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-#endif
-
-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
-#include "core_cm7.h"
-#define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM4)
-#include "core_cm4.h"
-#define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM3)
-#include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-#include "core_cm0.h"
-#define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
-#include "core_cm0plus.h"
-#define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MBL)
-#include "core_armv8mbl.h"
-#define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MML)
-#include "core_armv8mml.h"
-#if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
-#define ARM_MATH_DSP
-#endif
-#else
-#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
-#endif
-
-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef   __cplusplus
-extern "C"
-{
-#endif
-
-
-/**
- * @brief Macros required for reciprocal calculation in Normalized LMS
- */
-
-#define DELTA_Q31          (0x100)
-#define DELTA_Q15          0x5
-#define INDEX_MASK         0x0000003F
-#ifndef PI
-#define PI               3.14159265358979f
-#endif
-
-/**
- * @brief Macros required for SINE and COSINE Fast math approximations
- */
-
-#define FAST_MATH_TABLE_SIZE  512
-#define FAST_MATH_Q31_SHIFT   (32 - 10)
-#define FAST_MATH_Q15_SHIFT   (16 - 10)
-#define CONTROLLER_Q31_SHIFT  (32 - 9)
-#define TABLE_SPACING_Q31     0x400000
-#define TABLE_SPACING_Q15     0x80
-
-/**
- * @brief Macros required for SINE and COSINE Controller functions
- */
-/* 1.31(q31) Fixed value of 2/360 */
-/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING         0xB60B61
-
-/**
- * @brief Macro for Unaligned Support
- */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-#define ALIGN4
-#else
-#if defined  (__GNUC__)
-#define ALIGN4 __attribute__((aligned(4)))
-#else
-#define ALIGN4 __align(4)
-#endif
-#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-/**
- * @brief Error status returned by some functions in the library.
- */
-
-typedef enum {
-    ARM_MATH_SUCCESS = 0,                /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
-} arm_status;
-
-/**
- * @brief 8-bit fractional data type in 1.7 format.
- */
-typedef int8_t q7_t;
-
-/**
- * @brief 16-bit fractional data type in 1.15 format.
- */
-typedef int16_t q15_t;
-
-/**
- * @brief 32-bit fractional data type in 1.31 format.
- */
-typedef int32_t q31_t;
-
-/**
- * @brief 64-bit fractional data type in 1.63 format.
- */
-typedef int64_t q63_t;
-
-/**
- * @brief 32-bit floating-point type definition.
- */
-typedef float float32_t;
-
-/**
- * @brief 64-bit floating-point type definition.
- */
-typedef double float64_t;
-
-/**
- * @brief definition to read/write two 16 bit values.
- */
-#if   defined ( __CC_ARM )
-#define __SIMD32_TYPE int32_t __packed
-#define CMSIS_UNUSED __attribute__((unused))
-#define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED __attribute__((unused))
-#define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __GNUC__ )
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED __attribute__((unused))
-#define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ICCARM__ )
-#define __SIMD32_TYPE int32_t __packed
-#define CMSIS_UNUSED
-#define CMSIS_INLINE
-
-#elif defined ( __TI_ARM__ )
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED __attribute__((unused))
-#define CMSIS_INLINE
-
-#elif defined ( __CSMC__ )
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED
-#define CMSIS_INLINE
-
-#elif defined ( __TASKING__ )
-#define __SIMD32_TYPE __unaligned int32_t
-#define CMSIS_UNUSED
-#define CMSIS_INLINE
-
-#else
-#error Unknown compiler
-#endif
-
-#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
-#define __SIMD64(addr)        (*(int64_t **) & (addr))
-
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
-/**
- * @brief definition to pack two 16 bit values.
- */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
-                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
-                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
-/**
-* @brief definition to pack four 8 bit values.
-*/
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
-                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
-                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-
-#endif
-
-
-/**
- * @brief Clips Q63 to Q31 values.
- */
-CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
-    q63_t x)
-{
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-           ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-}
-
-/**
- * @brief Clips Q63 to Q15 values.
- */
-CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
-    q63_t x)
-{
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-           ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-}
-
-/**
- * @brief Clips Q31 to Q7 values.
- */
-CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
-    q31_t x)
-{
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-           ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-}
-
-/**
- * @brief Clips Q31 to Q15 values.
- */
-CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
-    q31_t x)
-{
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-           ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-}
-
-/**
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
- */
-
-CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
-    q63_t x,
-    q31_t y)
-{
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-}
-
-/*
-  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
-  #define __CLZ __clz
-  #endif
- */
-/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
-CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
-    q31_t data);
-
-CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
-    q31_t data)
-{
-    uint32_t count = 0;
-    uint32_t mask = 0x80000000;
-
-    while ((data & mask) == 0) {
-        count += 1u;
-        mask = mask >> 1u;
-    }
-
-    return (count);
-}
-#endif
-
-/**
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
- */
-
-CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
-    q31_t in,
-    q31_t* dst,
-    q31_t* pRecipTable)
-{
-    q31_t out;
-    uint32_t tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if (in > 0) {
-        signBits = ((uint32_t) (__CLZ( in) - 1));
-    }
-    else {
-        signBits = ((uint32_t) (__CLZ(-in) - 1));
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >> 24);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++) {
-        tempVal = (uint32_t) (((q63_t) in * out) >> 31);
-        tempVal = 0x7FFFFFFFu - tempVal;
-        /*      1.31 with exp 1 */
-        /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
-        out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1u);
-}
-
-
-/**
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
-    q15_t in,
-    q15_t* dst,
-    q15_t* pRecipTable)
-{
-    q15_t out = 0;
-    uint32_t tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if (in > 0) {
-        signBits = ((uint32_t)(__CLZ( in) - 17));
-    }
-    else {
-        signBits = ((uint32_t)(__CLZ(-in) - 17));
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = (in << signBits);
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t)(in >>  8);
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++) {
-        tempVal = (uint32_t) (((q31_t) in * out) >> 15);
-        tempVal = 0x7FFFu - tempVal;
-        /*      1.15 with exp 1 */
-        out = (q15_t) (((q31_t) out * tempVal) >> 14);
-        /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-}
-
-
-/*
- * @brief C custom defined intrinisic function for only M0 processors
- */
-#if defined(ARM_MATH_CM0_FAMILY)
-CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
-    q31_t x,
-    uint32_t y)
-{
-    int32_t posMax, negMin;
-    uint32_t i;
-
-    posMax = 1;
-    for (i = 0; i < (y - 1); i++) {
-        posMax = posMax * 2;
-    }
-
-    if (x > 0) {
-        posMax = (posMax - 1);
-
-        if (x > posMax) {
-            x = posMax;
-        }
-    }
-    else {
-        negMin = -posMax;
-
-        if (x < negMin) {
-            x = negMin;
-        }
-    }
-    return (x);
-}
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
-/*
- * @brief C custom defined intrinsic function for M3 and M0 processors
- */
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
-
-/*
- * @brief C custom defined QADD8 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-}
-
-
-/*
- * @brief C custom defined QSUB8 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s, t, u;
-
-    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
-    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
-    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
-    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
-
-    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
-}
-
-
-/*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
-    uint32_t x,
-    uint32_t y)
-{
-    /*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
-    q31_t r = 0, s = 0;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined SHADD16 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined QSUB16 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined SHSUB16 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined QASX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined SHASX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined QSAX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
-    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined SHSAX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
-    uint32_t x,
-    uint32_t y)
-{
-    q31_t r, s;
-
-    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
-    return ((uint32_t)((s << 16) | (r      )));
-}
-
-
-/*
- * @brief C custom defined SMUSDX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
-    uint32_t x,
-    uint32_t y)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-}
-
-/*
- * @brief C custom defined SMUADX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
-    uint32_t x,
-    uint32_t y)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
-}
-
-
-/*
- * @brief C custom defined QADD for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
-    int32_t x,
-    int32_t y)
-{
-    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
-}
-
-
-/*
- * @brief C custom defined QSUB for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
-    int32_t x,
-    int32_t y)
-{
-    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
-}
-
-
-/*
- * @brief C custom defined SMLAD for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
-    uint32_t x,
-    uint32_t y,
-    uint32_t sum)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-}
-
-
-/*
- * @brief C custom defined SMLADX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
-    uint32_t x,
-    uint32_t y,
-    uint32_t sum)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-}
-
-
-/*
- * @brief C custom defined SMLSDX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
-    uint32_t x,
-    uint32_t y,
-    uint32_t sum)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q31_t)sum    )                                  )   ));
-}
-
-
-/*
- * @brief C custom defined SMLALD for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
-    uint32_t x,
-    uint32_t y,
-    uint64_t sum)
-{
-    /*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-}
-
-
-/*
- * @brief C custom defined SMLALDX for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
-    uint32_t x,
-    uint32_t y,
-    uint64_t sum)
-{
-    /*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
-    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ( ((q63_t)sum    )                                  )   ));
-}
-
-
-/*
- * @brief C custom defined SMUAD for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
-    uint32_t x,
-    uint32_t y)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-}
-
-
-/*
- * @brief C custom defined SMUSD for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
-    uint32_t x,
-    uint32_t y)
-{
-    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
-                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
-}
-
-
-/*
- * @brief C custom defined SXTB16 for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
-    uint32_t x)
-{
-    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
-                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
-}
-
-/*
- * @brief C custom defined SMMLA for M3 and M0 processors
- */
-CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
-    int32_t x,
-    int32_t y,
-    int32_t sum)
-{
-    return (sum + (int32_t) (((int64_t) x * y) >> 32));
-}
-
-#if 0
-/*
- * @brief C custom defined PKHBT for unavailable DSP extension
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
-    uint32_t x,
-    uint32_t y,
-    uint32_t leftshift)
-{
-    return ( ((x             ) & 0x0000FFFFUL) |
-             ((y << leftshift) & 0xFFFF0000UL)  );
-}
-
-/*
- * @brief C custom defined PKHTB for unavailable DSP extension
- */
-CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
-    uint32_t x,
-    uint32_t y,
-    uint32_t rightshift)
-{
-    return ( ((x              ) & 0xFFFF0000UL) |
-             ((y >> rightshift) & 0x0000FFFFUL)  );
-}
-#endif
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
-
-/**
- * @brief Instance structure for the Q7 FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-} arm_fir_instance_q7;
-
-/**
- * @brief Instance structure for the Q15 FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-} arm_fir_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-} arm_fir_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-} arm_fir_instance_f32;
-
-
-/**
- * @brief Processing function for the Q7 FIR filter.
- * @param[in]  S          points to an instance of the Q7 FIR filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_q7(
-    const arm_fir_instance_q7* S,
-    q7_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q7 FIR filter.
- * @param[in,out] S          points to an instance of the Q7 FIR structure.
- * @param[in]     numTaps    Number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of samples that are processed.
- */
-void arm_fir_init_q7(
-    arm_fir_instance_q7* S,
-    uint16_t numTaps,
-    q7_t* pCoeffs,
-    q7_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q15 FIR filter.
- * @param[in]  S          points to an instance of the Q15 FIR structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_q15(
-    const arm_fir_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q15 FIR filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_fast_q15(
-    const arm_fir_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q15 FIR filter.
- * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
- * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of samples that are processed at a time.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
- * <code>numTaps</code> is not a supported value.
- */
-arm_status arm_fir_init_q15(
-    arm_fir_instance_q15* S,
-    uint16_t numTaps,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 FIR filter.
- * @param[in]  S          points to an instance of the Q31 FIR filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_q31(
-    const arm_fir_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q31 FIR structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_fast_q31(
-    const arm_fir_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q31 FIR filter.
- * @param[in,out] S          points to an instance of the Q31 FIR structure.
- * @param[in]     numTaps    Number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of samples that are processed at a time.
- */
-void arm_fir_init_q31(
-    arm_fir_instance_q31* S,
-    uint16_t numTaps,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the floating-point FIR filter.
- * @param[in]  S          points to an instance of the floating-point FIR structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_f32(
-    const arm_fir_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point FIR filter.
- * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
- * @param[in]     numTaps    Number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of samples that are processed at a time.
- */
-void arm_fir_init_f32(
-    arm_fir_instance_f32* S,
-    uint16_t numTaps,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q15 Biquad cascade filter.
- */
-typedef struct {
-    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t* pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t* pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
-} arm_biquad_casd_df1_inst_q15;
-
-/**
- * @brief Instance structure for the Q31 Biquad cascade filter.
- */
-typedef struct {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t* pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t* pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-} arm_biquad_casd_df1_inst_q31;
-
-/**
- * @brief Instance structure for the floating-point Biquad cascade filter.
- */
-typedef struct {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t* pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t* pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-} arm_biquad_casd_df1_inst_f32;
-
-
-/**
- * @brief Processing function for the Q15 Biquad cascade filter.
- * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df1_q15(
-    const arm_biquad_casd_df1_inst_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q15 Biquad cascade filter.
- * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
- */
-void arm_biquad_cascade_df1_init_q15(
-    arm_biquad_casd_df1_inst_q15* S,
-    uint8_t numStages,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    int8_t postShift);
-
-
-/**
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df1_fast_q15(
-    const arm_biquad_casd_df1_inst_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 Biquad cascade filter
- * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df1_q31(
-    const arm_biquad_casd_df1_inst_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df1_fast_q31(
-    const arm_biquad_casd_df1_inst_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q31 Biquad cascade filter.
- * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
- */
-void arm_biquad_cascade_df1_init_q31(
-    arm_biquad_casd_df1_inst_q31* S,
-    uint8_t numStages,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    int8_t postShift);
-
-
-/**
- * @brief Processing function for the floating-point Biquad cascade filter.
- * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df1_f32(
-    const arm_biquad_casd_df1_inst_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point Biquad cascade filter.
- * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- */
-void arm_biquad_cascade_df1_init_f32(
-    arm_biquad_casd_df1_inst_f32* S,
-    uint8_t numStages,
-    float32_t* pCoeffs,
-    float32_t* pState);
-
-
-/**
- * @brief Instance structure for the floating-point matrix structure.
- */
-typedef struct {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t* pData;     /**< points to the data of the matrix. */
-} arm_matrix_instance_f32;
-
-
-/**
- * @brief Instance structure for the floating-point matrix structure.
- */
-typedef struct {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float64_t* pData;     /**< points to the data of the matrix. */
-} arm_matrix_instance_f64;
-
-/**
- * @brief Instance structure for the Q15 matrix structure.
- */
-typedef struct {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t* pData;         /**< points to the data of the matrix. */
-} arm_matrix_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 matrix structure.
- */
-typedef struct {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t* pData;         /**< points to the data of the matrix. */
-} arm_matrix_instance_q31;
-
-
-/**
- * @brief Floating-point matrix addition.
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_add_f32(
-    const arm_matrix_instance_f32* pSrcA,
-    const arm_matrix_instance_f32* pSrcB,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15 matrix addition.
- * @param[in]   pSrcA  points to the first input matrix structure
- * @param[in]   pSrcB  points to the second input matrix structure
- * @param[out]  pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_add_q15(
-    const arm_matrix_instance_q15* pSrcA,
-    const arm_matrix_instance_q15* pSrcB,
-    arm_matrix_instance_q15* pDst);
-
-
-/**
- * @brief Q31 matrix addition.
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_add_q31(
-    const arm_matrix_instance_q31* pSrcA,
-    const arm_matrix_instance_q31* pSrcB,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Floating-point, complex, matrix multiplication.
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_cmplx_mult_f32(
-    const arm_matrix_instance_f32* pSrcA,
-    const arm_matrix_instance_f32* pSrcB,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15, complex,  matrix multiplication.
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_cmplx_mult_q15(
-    const arm_matrix_instance_q15* pSrcA,
-    const arm_matrix_instance_q15* pSrcB,
-    arm_matrix_instance_q15* pDst,
-    q15_t* pScratch);
-
-
-/**
- * @brief Q31, complex, matrix multiplication.
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_cmplx_mult_q31(
-    const arm_matrix_instance_q31* pSrcA,
-    const arm_matrix_instance_q31* pSrcB,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Floating-point matrix transpose.
- * @param[in]  pSrc  points to the input matrix
- * @param[out] pDst  points to the output matrix
- * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_trans_f32(
-    const arm_matrix_instance_f32* pSrc,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15 matrix transpose.
- * @param[in]  pSrc  points to the input matrix
- * @param[out] pDst  points to the output matrix
- * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_trans_q15(
-    const arm_matrix_instance_q15* pSrc,
-    arm_matrix_instance_q15* pDst);
-
-
-/**
- * @brief Q31 matrix transpose.
- * @param[in]  pSrc  points to the input matrix
- * @param[out] pDst  points to the output matrix
- * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_trans_q31(
-    const arm_matrix_instance_q31* pSrc,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Floating-point matrix multiplication
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_mult_f32(
-    const arm_matrix_instance_f32* pSrcA,
-    const arm_matrix_instance_f32* pSrcB,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15 matrix multiplication
- * @param[in]  pSrcA   points to the first input matrix structure
- * @param[in]  pSrcB   points to the second input matrix structure
- * @param[out] pDst    points to output matrix structure
- * @param[in]  pState  points to the array for storing intermediate results
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_mult_q15(
-    const arm_matrix_instance_q15* pSrcA,
-    const arm_matrix_instance_q15* pSrcB,
-    arm_matrix_instance_q15* pDst,
-    q15_t* pState);
-
-
-/**
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA   points to the first input matrix structure
- * @param[in]  pSrcB   points to the second input matrix structure
- * @param[out] pDst    points to output matrix structure
- * @param[in]  pState  points to the array for storing intermediate results
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_mult_fast_q15(
-    const arm_matrix_instance_q15* pSrcA,
-    const arm_matrix_instance_q15* pSrcB,
-    arm_matrix_instance_q15* pDst,
-    q15_t* pState);
-
-
-/**
- * @brief Q31 matrix multiplication
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_mult_q31(
-    const arm_matrix_instance_q31* pSrcA,
-    const arm_matrix_instance_q31* pSrcB,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_mult_fast_q31(
-    const arm_matrix_instance_q31* pSrcA,
-    const arm_matrix_instance_q31* pSrcB,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Floating-point matrix subtraction
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_sub_f32(
-    const arm_matrix_instance_f32* pSrcA,
-    const arm_matrix_instance_f32* pSrcB,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15 matrix subtraction
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_sub_q15(
-    const arm_matrix_instance_q15* pSrcA,
-    const arm_matrix_instance_q15* pSrcB,
-    arm_matrix_instance_q15* pDst);
-
-
-/**
- * @brief Q31 matrix subtraction
- * @param[in]  pSrcA  points to the first input matrix structure
- * @param[in]  pSrcB  points to the second input matrix structure
- * @param[out] pDst   points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_sub_q31(
-    const arm_matrix_instance_q31* pSrcA,
-    const arm_matrix_instance_q31* pSrcB,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief Floating-point matrix scaling.
- * @param[in]  pSrc   points to the input matrix
- * @param[in]  scale  scale factor
- * @param[out] pDst   points to the output matrix
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_scale_f32(
-    const arm_matrix_instance_f32* pSrc,
-    float32_t scale,
-    arm_matrix_instance_f32* pDst);
-
-
-/**
- * @brief Q15 matrix scaling.
- * @param[in]  pSrc        points to input matrix
- * @param[in]  scaleFract  fractional portion of the scale factor
- * @param[in]  shift       number of bits to shift the result by
- * @param[out] pDst        points to output matrix
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_scale_q15(
-    const arm_matrix_instance_q15* pSrc,
-    q15_t scaleFract,
-    int32_t shift,
-    arm_matrix_instance_q15* pDst);
-
-
-/**
- * @brief Q31 matrix scaling.
- * @param[in]  pSrc        points to input matrix
- * @param[in]  scaleFract  fractional portion of the scale factor
- * @param[in]  shift       number of bits to shift the result by
- * @param[out] pDst        points to output matrix structure
- * @return     The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-arm_status arm_mat_scale_q31(
-    const arm_matrix_instance_q31* pSrc,
-    q31_t scaleFract,
-    int32_t shift,
-    arm_matrix_instance_q31* pDst);
-
-
-/**
- * @brief  Q31 matrix initialization.
- * @param[in,out] S         points to an instance of the floating-point matrix structure.
- * @param[in]     nRows     number of rows in the matrix.
- * @param[in]     nColumns  number of columns in the matrix.
- * @param[in]     pData     points to the matrix data array.
- */
-void arm_mat_init_q31(
-    arm_matrix_instance_q31* S,
-    uint16_t nRows,
-    uint16_t nColumns,
-    q31_t* pData);
-
-
-/**
- * @brief  Q15 matrix initialization.
- * @param[in,out] S         points to an instance of the floating-point matrix structure.
- * @param[in]     nRows     number of rows in the matrix.
- * @param[in]     nColumns  number of columns in the matrix.
- * @param[in]     pData     points to the matrix data array.
- */
-void arm_mat_init_q15(
-    arm_matrix_instance_q15* S,
-    uint16_t nRows,
-    uint16_t nColumns,
-    q15_t* pData);
-
-
-/**
- * @brief  Floating-point matrix initialization.
- * @param[in,out] S         points to an instance of the floating-point matrix structure.
- * @param[in]     nRows     number of rows in the matrix.
- * @param[in]     nColumns  number of columns in the matrix.
- * @param[in]     pData     points to the matrix data array.
- */
-void arm_mat_init_f32(
-    arm_matrix_instance_f32* S,
-    uint16_t nRows,
-    uint16_t nColumns,
-    float32_t* pData);
-
-
-
-/**
- * @brief Instance structure for the Q15 PID Control.
- */
-typedef struct {
-    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
-#if !defined (ARM_MATH_DSP)
-    q15_t A1;
-    q15_t A2;
-#else
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-    q15_t state[3];     /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-} arm_pid_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 PID Control.
- */
-typedef struct {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-} arm_pid_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point PID Control.
- */
-typedef struct {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;          /**< The proportional gain. */
-    float32_t Ki;          /**< The integral gain. */
-    float32_t Kd;          /**< The derivative gain. */
-} arm_pid_instance_f32;
-
-
-
-/**
- * @brief  Initialization function for the floating-point PID Control.
- * @param[in,out] S               points to an instance of the PID structure.
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
- */
-void arm_pid_init_f32(
-    arm_pid_instance_f32* S,
-    int32_t resetStateFlag);
-
-
-/**
- * @brief  Reset function for the floating-point PID Control.
- * @param[in,out] S  is an instance of the floating-point PID Control structure
- */
-void arm_pid_reset_f32(
-    arm_pid_instance_f32* S);
-
-
-/**
- * @brief  Initialization function for the Q31 PID Control.
- * @param[in,out] S               points to an instance of the Q15 PID structure.
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
- */
-void arm_pid_init_q31(
-    arm_pid_instance_q31* S,
-    int32_t resetStateFlag);
-
-
-/**
- * @brief  Reset function for the Q31 PID Control.
- * @param[in,out] S   points to an instance of the Q31 PID Control structure
- */
-
-void arm_pid_reset_q31(
-    arm_pid_instance_q31* S);
-
-
-/**
- * @brief  Initialization function for the Q15 PID Control.
- * @param[in,out] S               points to an instance of the Q15 PID structure.
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
- */
-void arm_pid_init_q15(
-    arm_pid_instance_q15* S,
-    int32_t resetStateFlag);
-
-
-/**
- * @brief  Reset function for the Q15 PID Control.
- * @param[in,out] S  points to an instance of the q15 PID Control structure
- */
-void arm_pid_reset_q15(
-    arm_pid_instance_q15* S);
-
-
-/**
- * @brief Instance structure for the floating-point Linear Interpolate function.
- */
-typedef struct {
-    uint32_t nValues;           /**< nValues */
-    float32_t x1;               /**< x1 */
-    float32_t xSpacing;         /**< xSpacing */
-    float32_t* pYData;          /**< pointer to the table of Y values */
-} arm_linear_interp_instance_f32;
-
-/**
- * @brief Instance structure for the floating-point bilinear interpolation function.
- */
-typedef struct {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    float32_t* pData;   /**< points to the data table. */
-} arm_bilinear_interp_instance_f32;
-
-/**
-* @brief Instance structure for the Q31 bilinear interpolation function.
-*/
-typedef struct {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q31_t* pData;       /**< points to the data table. */
-} arm_bilinear_interp_instance_q31;
-
-/**
-* @brief Instance structure for the Q15 bilinear interpolation function.
-*/
-typedef struct {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q15_t* pData;       /**< points to the data table. */
-} arm_bilinear_interp_instance_q15;
-
-/**
-* @brief Instance structure for the Q15 bilinear interpolation function.
-*/
-typedef struct {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q7_t* pData;        /**< points to the data table. */
-} arm_bilinear_interp_instance_q7;
-
-
-/**
- * @brief Q7 vector multiplication.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_mult_q7(
-    q7_t* pSrcA,
-    q7_t* pSrcB,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q15 vector multiplication.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_mult_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q31 vector multiplication.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_mult_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Floating-point vector multiplication.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_mult_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t* pTwiddle;                 /**< points to the Sin twiddle factor table. */
-    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-} arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
-arm_status arm_cfft_radix2_init_q15(
-    arm_cfft_radix2_instance_q15* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/* Deprecated */
-void arm_cfft_radix2_q15(
-    const arm_cfft_radix2_instance_q15* S,
-    q15_t* pSrc);
-
-
-/**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t* pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-} arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
-arm_status arm_cfft_radix4_init_q15(
-    arm_cfft_radix4_instance_q15* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/* Deprecated */
-void arm_cfft_radix4_q15(
-    const arm_cfft_radix4_instance_q15* S,
-    q15_t* pSrc);
-
-/**
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t* pTwiddle;                 /**< points to the Twiddle factor table. */
-    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-} arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
-arm_status arm_cfft_radix2_init_q31(
-    arm_cfft_radix2_instance_q31* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/* Deprecated */
-void arm_cfft_radix2_q31(
-    const arm_cfft_radix2_instance_q31* S,
-    q31_t* pSrc);
-
-/**
- * @brief Instance structure for the Q31 CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t* pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-} arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
-void arm_cfft_radix4_q31(
-    const arm_cfft_radix4_instance_q31* S,
-    q31_t* pSrc);
-
-/* Deprecated */
-arm_status arm_cfft_radix4_init_q31(
-    arm_cfft_radix4_instance_q31* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-} arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
-arm_status arm_cfft_radix2_init_f32(
-    arm_cfft_radix2_instance_f32* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/* Deprecated */
-void arm_cfft_radix2_f32(
-    const arm_cfft_radix2_instance_f32* S,
-    float32_t* pSrc);
-
-/**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;             /**< value of 1/fftLen. */
-} arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
-arm_status arm_cfft_radix4_init_f32(
-    arm_cfft_radix4_instance_f32* S,
-    uint16_t fftLen,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/* Deprecated */
-void arm_cfft_radix4_f32(
-    const arm_cfft_radix4_instance_f32* S,
-    float32_t* pSrc);
-
-/**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q15_t* pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-} arm_cfft_instance_q15;
-
-void arm_cfft_q15(
-    const arm_cfft_instance_q15* S,
-    q15_t* p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const q31_t* pTwiddle;             /**< points to the Twiddle factor table. */
-    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-} arm_cfft_instance_q31;
-
-void arm_cfft_q31(
-    const arm_cfft_instance_q31* S,
-    q31_t* p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-typedef struct {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const float32_t* pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-} arm_cfft_instance_f32;
-
-void arm_cfft_f32(
-    const arm_cfft_instance_f32* S,
-    float32_t* p1,
-    uint8_t ifftFlag,
-    uint8_t bitReverseFlag);
-
-/**
- * @brief Instance structure for the Q15 RFFT/RIFFT function.
- */
-typedef struct {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q15_t* pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    q15_t* pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q15* pCfft;       /**< points to the complex FFT instance. */
-} arm_rfft_instance_q15;
-
-arm_status arm_rfft_init_q15(
-    arm_rfft_instance_q15* S,
-    uint32_t fftLenReal,
-    uint32_t ifftFlagR,
-    uint32_t bitReverseFlag);
-
-void arm_rfft_q15(
-    const arm_rfft_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst);
-
-/**
- * @brief Instance structure for the Q31 RFFT/RIFFT function.
- */
-typedef struct {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t* pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    q31_t* pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-    const arm_cfft_instance_q31* pCfft;         /**< points to the complex FFT instance. */
-} arm_rfft_instance_q31;
-
-arm_status arm_rfft_init_q31(
-    arm_rfft_instance_q31* S,
-    uint32_t fftLenReal,
-    uint32_t ifftFlagR,
-    uint32_t bitReverseFlag);
-
-void arm_rfft_q31(
-    const arm_rfft_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst);
-
-/**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-typedef struct {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t* pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t* pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32* pCfft;        /**< points to the complex FFT instance. */
-} arm_rfft_instance_f32;
-
-arm_status arm_rfft_init_f32(
-    arm_rfft_instance_f32* S,
-    arm_cfft_radix4_instance_f32* S_CFFT,
-    uint32_t fftLenReal,
-    uint32_t ifftFlagR,
-    uint32_t bitReverseFlag);
-
-void arm_rfft_f32(
-    const arm_rfft_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst);
-
-/**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-typedef struct {
-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
-    uint16_t fftLenRFFT;             /**< length of the real sequence */
-    float32_t* pTwiddleRFFT;         /**< Twiddle factors real stage  */
-} arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
-    arm_rfft_fast_instance_f32* S,
-    uint16_t fftLen);
-
-void arm_rfft_fast_f32(
-    arm_rfft_fast_instance_f32* S,
-    float32_t* p, float32_t* pOut,
-    uint8_t ifftFlag);
-
-/**
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.
- */
-typedef struct {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    float32_t normalize;                 /**< normalizing factor. */
-    float32_t* pTwiddle;                 /**< points to the twiddle factor table. */
-    float32_t* pCosFactor;               /**< points to the cosFactor table. */
-    arm_rfft_instance_f32* pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */
-} arm_dct4_instance_f32;
-
-
-/**
- * @brief  Initialization function for the floating-point DCT4/IDCT4.
- * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
- * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
- * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
- * @param[in]     N          length of the DCT4.
- * @param[in]     Nby2       half of the length of the DCT4.
- * @param[in]     normalize  normalizing factor.
- * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
- */
-arm_status arm_dct4_init_f32(
-    arm_dct4_instance_f32* S,
-    arm_rfft_instance_f32* S_RFFT,
-    arm_cfft_radix4_instance_f32* S_CFFT,
-    uint16_t N,
-    uint16_t Nby2,
-    float32_t normalize);
-
-
-/**
- * @brief Processing function for the floating-point DCT4/IDCT4.
- * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
- * @param[in]     pState         points to state buffer.
- * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
- */
-void arm_dct4_f32(
-    const arm_dct4_instance_f32* S,
-    float32_t* pState,
-    float32_t* pInlineBuffer);
-
-
-/**
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.
- */
-typedef struct {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q31_t normalize;                     /**< normalizing factor. */
-    q31_t* pTwiddle;                     /**< points to the twiddle factor table. */
-    q31_t* pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q31* pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */
-} arm_dct4_instance_q31;
-
-
-/**
- * @brief  Initialization function for the Q31 DCT4/IDCT4.
- * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
- * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
- * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
- * @param[in]     N          length of the DCT4.
- * @param[in]     Nby2       half of the length of the DCT4.
- * @param[in]     normalize  normalizing factor.
- * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
-arm_status arm_dct4_init_q31(
-    arm_dct4_instance_q31* S,
-    arm_rfft_instance_q31* S_RFFT,
-    arm_cfft_radix4_instance_q31* S_CFFT,
-    uint16_t N,
-    uint16_t Nby2,
-    q31_t normalize);
-
-
-/**
- * @brief Processing function for the Q31 DCT4/IDCT4.
- * @param[in]     S              points to an instance of the Q31 DCT4 structure.
- * @param[in]     pState         points to state buffer.
- * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
- */
-void arm_dct4_q31(
-    const arm_dct4_instance_q31* S,
-    q31_t* pState,
-    q31_t* pInlineBuffer);
-
-
-/**
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.
- */
-typedef struct {
-    uint16_t N;                          /**< length of the DCT4. */
-    uint16_t Nby2;                       /**< half of the length of the DCT4. */
-    q15_t normalize;                     /**< normalizing factor. */
-    q15_t* pTwiddle;                     /**< points to the twiddle factor table. */
-    q15_t* pCosFactor;                   /**< points to the cosFactor table. */
-    arm_rfft_instance_q15* pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */
-} arm_dct4_instance_q15;
-
-
-/**
- * @brief  Initialization function for the Q15 DCT4/IDCT4.
- * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
- * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
- * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
- * @param[in]     N          length of the DCT4.
- * @param[in]     Nby2       half of the length of the DCT4.
- * @param[in]     normalize  normalizing factor.
- * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
-arm_status arm_dct4_init_q15(
-    arm_dct4_instance_q15* S,
-    arm_rfft_instance_q15* S_RFFT,
-    arm_cfft_radix4_instance_q15* S_CFFT,
-    uint16_t N,
-    uint16_t Nby2,
-    q15_t normalize);
-
-
-/**
- * @brief Processing function for the Q15 DCT4/IDCT4.
- * @param[in]     S              points to an instance of the Q15 DCT4 structure.
- * @param[in]     pState         points to state buffer.
- * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
- */
-void arm_dct4_q15(
-    const arm_dct4_instance_q15* S,
-    q15_t* pState,
-    q15_t* pInlineBuffer);
-
-
-/**
- * @brief Floating-point vector addition.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_add_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q7 vector addition.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_add_q7(
-    q7_t* pSrcA,
-    q7_t* pSrcB,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q15 vector addition.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_add_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q31 vector addition.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_add_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Floating-point vector subtraction.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_sub_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q7 vector subtraction.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_sub_q7(
-    q7_t* pSrcA,
-    q7_t* pSrcB,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q15 vector subtraction.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_sub_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q31 vector subtraction.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_sub_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Multiplies a floating-point vector by a scalar.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  scale      scale factor to be applied
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_scale_f32(
-    float32_t* pSrc,
-    float32_t scale,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Multiplies a Q7 vector by a scalar.
- * @param[in]  pSrc        points to the input vector
- * @param[in]  scaleFract  fractional portion of the scale value
- * @param[in]  shift       number of bits to shift the result by
- * @param[out] pDst        points to the output vector
- * @param[in]  blockSize   number of samples in the vector
- */
-void arm_scale_q7(
-    q7_t* pSrc,
-    q7_t scaleFract,
-    int8_t shift,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Multiplies a Q15 vector by a scalar.
- * @param[in]  pSrc        points to the input vector
- * @param[in]  scaleFract  fractional portion of the scale value
- * @param[in]  shift       number of bits to shift the result by
- * @param[out] pDst        points to the output vector
- * @param[in]  blockSize   number of samples in the vector
- */
-void arm_scale_q15(
-    q15_t* pSrc,
-    q15_t scaleFract,
-    int8_t shift,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Multiplies a Q31 vector by a scalar.
- * @param[in]  pSrc        points to the input vector
- * @param[in]  scaleFract  fractional portion of the scale value
- * @param[in]  shift       number of bits to shift the result by
- * @param[out] pDst        points to the output vector
- * @param[in]  blockSize   number of samples in the vector
- */
-void arm_scale_q31(
-    q31_t* pSrc,
-    q31_t scaleFract,
-    int8_t shift,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q7 vector absolute value.
- * @param[in]  pSrc       points to the input buffer
- * @param[out] pDst       points to the output buffer
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_abs_q7(
-    q7_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Floating-point vector absolute value.
- * @param[in]  pSrc       points to the input buffer
- * @param[out] pDst       points to the output buffer
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_abs_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q15 vector absolute value.
- * @param[in]  pSrc       points to the input buffer
- * @param[out] pDst       points to the output buffer
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_abs_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Q31 vector absolute value.
- * @param[in]  pSrc       points to the input buffer
- * @param[out] pDst       points to the output buffer
- * @param[in]  blockSize  number of samples in each vector
- */
-void arm_abs_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Dot product of floating-point vectors.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[in]  blockSize  number of samples in each vector
- * @param[out] result     output result returned here
- */
-void arm_dot_prod_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    uint32_t blockSize,
-    float32_t* result);
-
-
-/**
- * @brief Dot product of Q7 vectors.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[in]  blockSize  number of samples in each vector
- * @param[out] result     output result returned here
- */
-void arm_dot_prod_q7(
-    q7_t* pSrcA,
-    q7_t* pSrcB,
-    uint32_t blockSize,
-    q31_t* result);
-
-
-/**
- * @brief Dot product of Q15 vectors.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[in]  blockSize  number of samples in each vector
- * @param[out] result     output result returned here
- */
-void arm_dot_prod_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    uint32_t blockSize,
-    q63_t* result);
-
-
-/**
- * @brief Dot product of Q31 vectors.
- * @param[in]  pSrcA      points to the first input vector
- * @param[in]  pSrcB      points to the second input vector
- * @param[in]  blockSize  number of samples in each vector
- * @param[out] result     output result returned here
- */
-void arm_dot_prod_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    uint32_t blockSize,
-    q63_t* result);
-
-
-/**
- * @brief  Shifts the elements of a Q7 vector a specified number of bits.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_shift_q7(
-    q7_t* pSrc,
-    int8_t shiftBits,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Shifts the elements of a Q15 vector a specified number of bits.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_shift_q15(
-    q15_t* pSrc,
-    int8_t shiftBits,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Shifts the elements of a Q31 vector a specified number of bits.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_shift_q31(
-    q31_t* pSrc,
-    int8_t shiftBits,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Adds a constant offset to a floating-point vector.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  offset     is the offset to be added
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_offset_f32(
-    float32_t* pSrc,
-    float32_t offset,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Adds a constant offset to a Q7 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  offset     is the offset to be added
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_offset_q7(
-    q7_t* pSrc,
-    q7_t offset,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Adds a constant offset to a Q15 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  offset     is the offset to be added
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_offset_q15(
-    q15_t* pSrc,
-    q15_t offset,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Adds a constant offset to a Q31 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[in]  offset     is the offset to be added
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_offset_q31(
-    q31_t* pSrc,
-    q31_t offset,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Negates the elements of a floating-point vector.
- * @param[in]  pSrc       points to the input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_negate_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Negates the elements of a Q7 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_negate_q7(
-    q7_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Negates the elements of a Q15 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_negate_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Negates the elements of a Q31 vector.
- * @param[in]  pSrc       points to the input vector
- * @param[out] pDst       points to the output vector
- * @param[in]  blockSize  number of samples in the vector
- */
-void arm_negate_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Copies the elements of a floating-point vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_copy_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Copies the elements of a Q7 vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_copy_q7(
-    q7_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Copies the elements of a Q15 vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_copy_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Copies the elements of a Q31 vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_copy_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Fills a constant value into a floating-point vector.
- * @param[in]  value      input value to be filled
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_fill_f32(
-    float32_t value,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Fills a constant value into a Q7 vector.
- * @param[in]  value      input value to be filled
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_fill_q7(
-    q7_t value,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Fills a constant value into a Q15 vector.
- * @param[in]  value      input value to be filled
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_fill_q15(
-    q15_t value,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Fills a constant value into a Q31 vector.
- * @param[in]  value      input value to be filled
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_fill_q31(
-    q31_t value,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-void arm_conv_f32(
-    float32_t* pSrcA,
-    uint32_t srcALen,
-    float32_t* pSrcB,
-    uint32_t srcBLen,
-    float32_t* pDst);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in]  pSrcA      points to the first input sequence.
- * @param[in]  srcALen    length of the first input sequence.
- * @param[in]  pSrcB      points to the second input sequence.
- * @param[in]  srcBLen    length of the second input sequence.
- * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
- * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
- */
-void arm_conv_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
- */
-void arm_conv_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst);
-
-
-/**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
- */
-void arm_conv_fast_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst);
-
-
-/**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA      points to the first input sequence.
- * @param[in]  srcALen    length of the first input sequence.
- * @param[in]  pSrcB      points to the second input sequence.
- * @param[in]  srcBLen    length of the second input sequence.
- * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
- * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
- */
-void arm_conv_fast_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Convolution of Q31 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
- */
-void arm_conv_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst);
-
-
-/**
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
- */
-void arm_conv_fast_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst);
-
-
-/**
-* @brief Convolution of Q7 sequences.
-* @param[in]  pSrcA      points to the first input sequence.
-* @param[in]  srcALen    length of the first input sequence.
-* @param[in]  pSrcB      points to the second input sequence.
-* @param[in]  srcBLen    length of the second input sequence.
-* @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
-* @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-* @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-*/
-void arm_conv_opt_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Convolution of Q7 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
- */
-void arm_conv_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst);
-
-
-/**
- * @brief Partial convolution of floating-point sequences.
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_f32(
-    float32_t* pSrcA,
-    uint32_t srcALen,
-    float32_t* pSrcB,
-    uint32_t srcBLen,
-    float32_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Partial convolution of Q15 sequences.
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Partial convolution of Q15 sequences.
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_fast_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_fast_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Partial convolution of Q31 sequences.
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_fast_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Partial convolution of Q7 sequences
- * @param[in]  pSrcA       points to the first input sequence.
- * @param[in]  srcALen     length of the first input sequence.
- * @param[in]  pSrcB       points to the second input sequence.
- * @param[in]  srcBLen     length of the second input sequence.
- * @param[out] pDst        points to the block of output data
- * @param[in]  firstIndex  is the first output sample to start with.
- * @param[in]  numPoints   is the number of output points to be computed.
- * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-arm_status arm_conv_partial_opt_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]  pSrcA       points to the first input sequence.
-   * @param[in]  srcALen     length of the first input sequence.
-   * @param[in]  pSrcB       points to the second input sequence.
-   * @param[in]  srcBLen     length of the second input sequence.
-   * @param[out] pDst        points to the block of output data
-   * @param[in]  firstIndex  is the first output sample to start with.
-   * @param[in]  numPoints   is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-arm_status arm_conv_partial_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst,
-    uint32_t firstIndex,
-    uint32_t numPoints);
-
-
-/**
- * @brief Instance structure for the Q15 FIR decimator.
- */
-typedef struct {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q15_t* pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t* pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-} arm_fir_decimate_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 FIR decimator.
- */
-typedef struct {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t* pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t* pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-} arm_fir_decimate_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point FIR decimator.
- */
-typedef struct {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    float32_t* pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t* pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-} arm_fir_decimate_instance_f32;
-
-
-/**
- * @brief Processing function for the floating-point FIR decimator.
- * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_decimate_f32(
-    const arm_fir_decimate_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point FIR decimator.
- * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
- * @param[in]     numTaps    number of coefficients in the filter.
- * @param[in]     M          decimation factor.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-arm_status arm_fir_decimate_init_f32(
-    arm_fir_decimate_instance_f32* S,
-    uint16_t numTaps,
-    uint8_t M,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q15 FIR decimator.
- * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_decimate_q15(
-    const arm_fir_decimate_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_decimate_fast_q15(
-    const arm_fir_decimate_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q15 FIR decimator.
- * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
- * @param[in]     numTaps    number of coefficients in the filter.
- * @param[in]     M          decimation factor.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-arm_status arm_fir_decimate_init_q15(
-    arm_fir_decimate_instance_q15* S,
-    uint16_t numTaps,
-    uint8_t M,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 FIR decimator.
- * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
- * @param[in]  pSrc  points to the block of input data.
- * @param[out] pDst  points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
-void arm_fir_decimate_q31(
-    const arm_fir_decimate_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-/**
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_decimate_fast_q31(
-    arm_fir_decimate_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q31 FIR decimator.
- * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
- * @param[in]     numTaps    number of coefficients in the filter.
- * @param[in]     M          decimation factor.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-arm_status arm_fir_decimate_init_q31(
-    arm_fir_decimate_instance_q31* S,
-    uint16_t numTaps,
-    uint8_t M,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q15 FIR interpolator.
- */
-typedef struct {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t* pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t* pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-} arm_fir_interpolate_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 FIR interpolator.
- */
-typedef struct {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t* pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t* pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-} arm_fir_interpolate_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point FIR interpolator.
- */
-typedef struct {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t* pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t* pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-} arm_fir_interpolate_instance_f32;
-
-
-/**
- * @brief Processing function for the Q15 FIR interpolator.
- * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_interpolate_q15(
-    const arm_fir_interpolate_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q15 FIR interpolator.
- * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
- * @param[in]     L          upsample factor.
- * @param[in]     numTaps    number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficient buffer.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-arm_status arm_fir_interpolate_init_q15(
-    arm_fir_interpolate_instance_q15* S,
-    uint8_t L,
-    uint16_t numTaps,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 FIR interpolator.
- * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_interpolate_q31(
-    const arm_fir_interpolate_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q31 FIR interpolator.
- * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
- * @param[in]     L          upsample factor.
- * @param[in]     numTaps    number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficient buffer.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-arm_status arm_fir_interpolate_init_q31(
-    arm_fir_interpolate_instance_q31* S,
-    uint8_t L,
-    uint16_t numTaps,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the floating-point FIR interpolator.
- * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of input samples to process per call.
- */
-void arm_fir_interpolate_f32(
-    const arm_fir_interpolate_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point FIR interpolator.
- * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
- * @param[in]     L          upsample factor.
- * @param[in]     numTaps    number of filter coefficients in the filter.
- * @param[in]     pCoeffs    points to the filter coefficient buffer.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     blockSize  number of input samples to process per call.
- * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-arm_status arm_fir_interpolate_init_f32(
-    arm_fir_interpolate_instance_f32* S,
-    uint8_t L,
-    uint16_t numTaps,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.
- */
-typedef struct {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t* pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t* pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-} arm_biquad_cas_df1_32x64_ins_q31;
-
-
-/**
- * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cas_df1_32x64_q31(
-    const arm_biquad_cas_df1_32x64_ins_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
- */
-void arm_biquad_cas_df1_32x64_init_q31(
-    arm_biquad_cas_df1_32x64_ins_q31* S,
-    uint8_t numStages,
-    q31_t* pCoeffs,
-    q63_t* pState,
-    uint8_t postShift);
-
-
-/**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-typedef struct {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-} arm_biquad_cascade_df2T_instance_f32;
-
-/**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-typedef struct {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-} arm_biquad_cascade_stereo_df2T_instance_f32;
-
-/**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-typedef struct {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float64_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float64_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-} arm_biquad_cascade_df2T_instance_f64;
-
-
-/**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in]  S          points to an instance of the filter data structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df2T_f32(
-    const arm_biquad_cascade_df2T_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
- * @param[in]  S          points to an instance of the filter data structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_stereo_df2T_f32(
-    const arm_biquad_cascade_stereo_df2T_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in]  S          points to an instance of the filter data structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_biquad_cascade_df2T_f64(
-    const arm_biquad_cascade_df2T_instance_f64* S,
-    float64_t* pSrc,
-    float64_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S          points to an instance of the filter data structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- */
-void arm_biquad_cascade_df2T_init_f32(
-    arm_biquad_cascade_df2T_instance_f32* S,
-    uint8_t numStages,
-    float32_t* pCoeffs,
-    float32_t* pState);
-
-
-/**
- * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S          points to an instance of the filter data structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- */
-void arm_biquad_cascade_stereo_df2T_init_f32(
-    arm_biquad_cascade_stereo_df2T_instance_f32* S,
-    uint8_t numStages,
-    float32_t* pCoeffs,
-    float32_t* pState);
-
-
-/**
- * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S          points to an instance of the filter data structure.
- * @param[in]     numStages  number of 2nd order stages in the filter.
- * @param[in]     pCoeffs    points to the filter coefficients.
- * @param[in]     pState     points to the state buffer.
- */
-void arm_biquad_cascade_df2T_init_f64(
-    arm_biquad_cascade_df2T_instance_f64* S,
-    uint8_t numStages,
-    float64_t* pCoeffs,
-    float64_t* pState);
-
-
-/**
- * @brief Instance structure for the Q15 FIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q15_t* pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q15_t* pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-} arm_fir_lattice_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 FIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of filter stages. */
-    q31_t* pState;                       /**< points to the state variable array. The array is of length numStages. */
-    q31_t* pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
-} arm_fir_lattice_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point FIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t* pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t* pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-} arm_fir_lattice_instance_f32;
-
-
-/**
- * @brief Initialization function for the Q15 FIR lattice filter.
- * @param[in] S          points to an instance of the Q15 FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.  The array is of length numStages.
- */
-void arm_fir_lattice_init_q15(
-    arm_fir_lattice_instance_q15* S,
-    uint16_t numStages,
-    q15_t* pCoeffs,
-    q15_t* pState);
-
-
-/**
- * @brief Processing function for the Q15 FIR lattice filter.
- * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_lattice_q15(
-    const arm_fir_lattice_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q31 FIR lattice filter.
- * @param[in] S          points to an instance of the Q31 FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.   The array is of length numStages.
- */
-void arm_fir_lattice_init_q31(
-    arm_fir_lattice_instance_q31* S,
-    uint16_t numStages,
-    q31_t* pCoeffs,
-    q31_t* pState);
-
-
-/**
- * @brief Processing function for the Q31 FIR lattice filter.
- * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_lattice_q31(
-    const arm_fir_lattice_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S          points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
- * @param[in] pState     points to the state buffer.  The array is of length numStages.
- */
-void arm_fir_lattice_init_f32(
-    arm_fir_lattice_instance_f32* S,
-    uint16_t numStages,
-    float32_t* pCoeffs,
-    float32_t* pState);
-
-
-/**
- * @brief Processing function for the floating-point FIR lattice filter.
- * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_fir_lattice_f32(
-    const arm_fir_lattice_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q15 IIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q15_t* pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t* pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t* pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-} arm_iir_lattice_instance_q15;
-
-/**
- * @brief Instance structure for the Q31 IIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    q31_t* pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t* pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t* pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
-} arm_iir_lattice_instance_q31;
-
-/**
- * @brief Instance structure for the floating-point IIR lattice filter.
- */
-typedef struct {
-    uint16_t numStages;                  /**< number of stages in the filter. */
-    float32_t* pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t* pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t* pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
-} arm_iir_lattice_instance_f32;
-
-
-/**
- * @brief Processing function for the floating-point IIR lattice filter.
- * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_iir_lattice_f32(
-    const arm_iir_lattice_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point IIR lattice filter.
- * @param[in] S          points to an instance of the floating-point IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
- * @param[in] blockSize  number of samples to process.
- */
-void arm_iir_lattice_init_f32(
-    arm_iir_lattice_instance_f32* S,
-    uint16_t numStages,
-    float32_t* pkCoeffs,
-    float32_t* pvCoeffs,
-    float32_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 IIR lattice filter.
- * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_iir_lattice_q31(
-    const arm_iir_lattice_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q31 IIR lattice filter.
- * @param[in] S          points to an instance of the Q31 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize  number of samples to process.
- */
-void arm_iir_lattice_init_q31(
-    arm_iir_lattice_instance_q31* S,
-    uint16_t numStages,
-    q31_t* pkCoeffs,
-    q31_t* pvCoeffs,
-    q31_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q15 IIR lattice filter.
- * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[out] pDst       points to the block of output data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_iir_lattice_q15(
-    const arm_iir_lattice_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize  number of samples to process per call.
- */
-void arm_iir_lattice_init_q15(
-    arm_iir_lattice_instance_q15* S,
-    uint16_t numStages,
-    q15_t* pkCoeffs,
-    q15_t* pvCoeffs,
-    q15_t* pState,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the floating-point LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t* pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t* pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-} arm_lms_instance_f32;
-
-
-/**
- * @brief Processing function for floating-point LMS filter.
- * @param[in]  S          points to an instance of the floating-point LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_f32(
-    const arm_lms_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pRef,
-    float32_t* pOut,
-    float32_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for floating-point LMS filter.
- * @param[in] S          points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to the coefficient buffer.
- * @param[in] pState     points to state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- */
-void arm_lms_init_f32(
-    arm_lms_instance_f32* S,
-    uint16_t numTaps,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    float32_t mu,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q15 LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-} arm_lms_instance_q15;
-
-
-/**
- * @brief Initialization function for the Q15 LMS filter.
- * @param[in] S          points to an instance of the Q15 LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to the coefficient buffer.
- * @param[in] pState     points to the state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- * @param[in] postShift  bit shift applied to coefficients.
- */
-void arm_lms_init_q15(
-    arm_lms_instance_q15* S,
-    uint16_t numTaps,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    q15_t mu,
-    uint32_t blockSize,
-    uint32_t postShift);
-
-
-/**
- * @brief Processing function for Q15 LMS filter.
- * @param[in]  S          points to an instance of the Q15 LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_q15(
-    const arm_lms_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pRef,
-    q15_t* pOut,
-    q15_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q31 LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-} arm_lms_instance_q31;
-
-
-/**
- * @brief Processing function for Q31 LMS filter.
- * @param[in]  S          points to an instance of the Q15 LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_q31(
-    const arm_lms_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pRef,
-    q31_t* pOut,
-    q31_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for Q31 LMS filter.
- * @param[in] S          points to an instance of the Q31 LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to coefficient buffer.
- * @param[in] pState     points to state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- * @param[in] postShift  bit shift applied to coefficients.
- */
-void arm_lms_init_q31(
-    arm_lms_instance_q31* S,
-    uint16_t numTaps,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    q31_t mu,
-    uint32_t blockSize,
-    uint32_t postShift);
-
-
-/**
- * @brief Instance structure for the floating-point normalized LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;         /**< step size that control filter coefficient updates. */
-    float32_t energy;     /**< saves previous frame energy. */
-    float32_t x0;         /**< saves previous input sample. */
-} arm_lms_norm_instance_f32;
-
-
-/**
- * @brief Processing function for floating-point normalized LMS filter.
- * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_norm_f32(
-    arm_lms_norm_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pRef,
-    float32_t* pOut,
-    float32_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for floating-point normalized LMS filter.
- * @param[in] S          points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to coefficient buffer.
- * @param[in] pState     points to state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- */
-void arm_lms_norm_init_f32(
-    arm_lms_norm_instance_f32* S,
-    uint16_t numTaps,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    float32_t mu,
-    uint32_t blockSize);
-
-
-/**
- * @brief Instance structure for the Q31 normalized LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t* recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-} arm_lms_norm_instance_q31;
-
-
-/**
- * @brief Processing function for Q31 normalized LMS filter.
- * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_norm_q31(
-    arm_lms_norm_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pRef,
-    q31_t* pOut,
-    q31_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for Q31 normalized LMS filter.
- * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to coefficient buffer.
- * @param[in] pState     points to state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- * @param[in] postShift  bit shift applied to coefficients.
- */
-void arm_lms_norm_init_q31(
-    arm_lms_norm_instance_q31* S,
-    uint16_t numTaps,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    q31_t mu,
-    uint32_t blockSize,
-    uint8_t postShift);
-
-
-/**
- * @brief Instance structure for the Q15 normalized LMS filter.
- */
-typedef struct {
-    uint16_t numTaps;     /**< Number of coefficients in the filter. */
-    q15_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q15_t* recipTable;    /**< Points to the reciprocal initial value table. */
-    q15_t energy;         /**< saves previous frame energy. */
-    q15_t x0;             /**< saves previous input sample. */
-} arm_lms_norm_instance_q15;
-
-
-/**
- * @brief Processing function for Q15 normalized LMS filter.
- * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
- * @param[in]  pSrc       points to the block of input data.
- * @param[in]  pRef       points to the block of reference data.
- * @param[out] pOut       points to the block of output data.
- * @param[out] pErr       points to the block of error data.
- * @param[in]  blockSize  number of samples to process.
- */
-void arm_lms_norm_q15(
-    arm_lms_norm_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pRef,
-    q15_t* pOut,
-    q15_t* pErr,
-    uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for Q15 normalized LMS filter.
- * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] numTaps    number of filter coefficients.
- * @param[in] pCoeffs    points to coefficient buffer.
- * @param[in] pState     points to state buffer.
- * @param[in] mu         step size that controls filter coefficient updates.
- * @param[in] blockSize  number of samples to process.
- * @param[in] postShift  bit shift applied to coefficients.
- */
-void arm_lms_norm_init_q15(
-    arm_lms_norm_instance_q15* S,
-    uint16_t numTaps,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    q15_t mu,
-    uint32_t blockSize,
-    uint8_t postShift);
-
-
-/**
- * @brief Correlation of floating-point sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-void arm_correlate_f32(
-    float32_t* pSrcA,
-    uint32_t srcALen,
-    float32_t* pSrcB,
-    uint32_t srcBLen,
-    float32_t* pDst);
-
-
-/**
-* @brief Correlation of Q15 sequences
-* @param[in]  pSrcA     points to the first input sequence.
-* @param[in]  srcALen   length of the first input sequence.
-* @param[in]  pSrcB     points to the second input sequence.
-* @param[in]  srcBLen   length of the second input sequence.
-* @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-* @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-*/
-void arm_correlate_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    q15_t* pScratch);
-
-
-/**
- * @brief Correlation of Q15 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-
-void arm_correlate_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst);
-
-
-/**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-
-void arm_correlate_fast_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst);
-
-
-/**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in]  pSrcA     points to the first input sequence.
- * @param[in]  srcALen   length of the first input sequence.
- * @param[in]  pSrcB     points to the second input sequence.
- * @param[in]  srcBLen   length of the second input sequence.
- * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- */
-void arm_correlate_fast_opt_q15(
-    q15_t* pSrcA,
-    uint32_t srcALen,
-    q15_t* pSrcB,
-    uint32_t srcBLen,
-    q15_t* pDst,
-    q15_t* pScratch);
-
-
-/**
- * @brief Correlation of Q31 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-void arm_correlate_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst);
-
-
-/**
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-void arm_correlate_fast_q31(
-    q31_t* pSrcA,
-    uint32_t srcALen,
-    q31_t* pSrcB,
-    uint32_t srcBLen,
-    q31_t* pDst);
-
-
-/**
-  * @brief Correlation of Q7 sequences.
-  * @param[in]  pSrcA      points to the first input sequence.
-  * @param[in]  srcALen    length of the first input sequence.
-  * @param[in]  pSrcB      points to the second input sequence.
-  * @param[in]  srcBLen    length of the second input sequence.
-  * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-  * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-  * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-  */
-void arm_correlate_opt_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst,
-    q15_t* pScratch1,
-    q15_t* pScratch2);
-
-
-/**
- * @brief Correlation of Q7 sequences.
- * @param[in]  pSrcA    points to the first input sequence.
- * @param[in]  srcALen  length of the first input sequence.
- * @param[in]  pSrcB    points to the second input sequence.
- * @param[in]  srcBLen  length of the second input sequence.
- * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
- */
-void arm_correlate_q7(
-    q7_t* pSrcA,
-    uint32_t srcALen,
-    q7_t* pSrcB,
-    uint32_t srcBLen,
-    q7_t* pDst);
-
-
-/**
- * @brief Instance structure for the floating-point sparse FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t* pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-} arm_fir_sparse_instance_f32;
-
-/**
- * @brief Instance structure for the Q31 sparse FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-} arm_fir_sparse_instance_q31;
-
-/**
- * @brief Instance structure for the Q15 sparse FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-} arm_fir_sparse_instance_q15;
-
-/**
- * @brief Instance structure for the Q7 sparse FIR filter.
- */
-typedef struct {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t* pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t* pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-} arm_fir_sparse_instance_q7;
-
-
-/**
- * @brief Processing function for the floating-point sparse FIR filter.
- * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
- * @param[in]  pSrc        points to the block of input data.
- * @param[out] pDst        points to the block of output data
- * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
- * @param[in]  blockSize   number of input samples to process per call.
- */
-void arm_fir_sparse_f32(
-    arm_fir_sparse_instance_f32* S,
-    float32_t* pSrc,
-    float32_t* pDst,
-    float32_t* pScratchIn,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the floating-point sparse FIR filter.
- * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
- * @param[in]     numTaps    number of nonzero coefficients in the filter.
- * @param[in]     pCoeffs    points to the array of filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     pTapDelay  points to the array of offset times.
- * @param[in]     maxDelay   maximum offset time supported.
- * @param[in]     blockSize  number of samples that will be processed per block.
- */
-void arm_fir_sparse_init_f32(
-    arm_fir_sparse_instance_f32* S,
-    uint16_t numTaps,
-    float32_t* pCoeffs,
-    float32_t* pState,
-    int32_t* pTapDelay,
-    uint16_t maxDelay,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q31 sparse FIR filter.
- * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
- * @param[in]  pSrc        points to the block of input data.
- * @param[out] pDst        points to the block of output data
- * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
- * @param[in]  blockSize   number of input samples to process per call.
- */
-void arm_fir_sparse_q31(
-    arm_fir_sparse_instance_q31* S,
-    q31_t* pSrc,
-    q31_t* pDst,
-    q31_t* pScratchIn,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q31 sparse FIR filter.
- * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
- * @param[in]     numTaps    number of nonzero coefficients in the filter.
- * @param[in]     pCoeffs    points to the array of filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     pTapDelay  points to the array of offset times.
- * @param[in]     maxDelay   maximum offset time supported.
- * @param[in]     blockSize  number of samples that will be processed per block.
- */
-void arm_fir_sparse_init_q31(
-    arm_fir_sparse_instance_q31* S,
-    uint16_t numTaps,
-    q31_t* pCoeffs,
-    q31_t* pState,
-    int32_t* pTapDelay,
-    uint16_t maxDelay,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q15 sparse FIR filter.
- * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
- * @param[in]  pSrc         points to the block of input data.
- * @param[out] pDst         points to the block of output data
- * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
- * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
- * @param[in]  blockSize    number of input samples to process per call.
- */
-void arm_fir_sparse_q15(
-    arm_fir_sparse_instance_q15* S,
-    q15_t* pSrc,
-    q15_t* pDst,
-    q15_t* pScratchIn,
-    q31_t* pScratchOut,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q15 sparse FIR filter.
- * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
- * @param[in]     numTaps    number of nonzero coefficients in the filter.
- * @param[in]     pCoeffs    points to the array of filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     pTapDelay  points to the array of offset times.
- * @param[in]     maxDelay   maximum offset time supported.
- * @param[in]     blockSize  number of samples that will be processed per block.
- */
-void arm_fir_sparse_init_q15(
-    arm_fir_sparse_instance_q15* S,
-    uint16_t numTaps,
-    q15_t* pCoeffs,
-    q15_t* pState,
-    int32_t* pTapDelay,
-    uint16_t maxDelay,
-    uint32_t blockSize);
-
-
-/**
- * @brief Processing function for the Q7 sparse FIR filter.
- * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
- * @param[in]  pSrc         points to the block of input data.
- * @param[out] pDst         points to the block of output data
- * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
- * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
- * @param[in]  blockSize    number of input samples to process per call.
- */
-void arm_fir_sparse_q7(
-    arm_fir_sparse_instance_q7* S,
-    q7_t* pSrc,
-    q7_t* pDst,
-    q7_t* pScratchIn,
-    q31_t* pScratchOut,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Initialization function for the Q7 sparse FIR filter.
- * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
- * @param[in]     numTaps    number of nonzero coefficients in the filter.
- * @param[in]     pCoeffs    points to the array of filter coefficients.
- * @param[in]     pState     points to the state buffer.
- * @param[in]     pTapDelay  points to the array of offset times.
- * @param[in]     maxDelay   maximum offset time supported.
- * @param[in]     blockSize  number of samples that will be processed per block.
- */
-void arm_fir_sparse_init_q7(
-    arm_fir_sparse_instance_q7* S,
-    uint16_t numTaps,
-    q7_t* pCoeffs,
-    q7_t* pState,
-    int32_t* pTapDelay,
-    uint16_t maxDelay,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Floating-point sin_cos function.
- * @param[in]  theta   input value in degrees
- * @param[out] pSinVal  points to the processed sine output.
- * @param[out] pCosVal  points to the processed cos output.
- */
-void arm_sin_cos_f32(
-    float32_t theta,
-    float32_t* pSinVal,
-    float32_t* pCosVal);
-
-
-/**
- * @brief  Q31 sin_cos function.
- * @param[in]  theta    scaled input value in degrees
- * @param[out] pSinVal  points to the processed sine output.
- * @param[out] pCosVal  points to the processed cosine output.
- */
-void arm_sin_cos_q31(
-    q31_t theta,
-    q31_t* pSinVal,
-    q31_t* pCosVal);
-
-
-/**
- * @brief  Floating-point complex conjugate.
- * @param[in]  pSrc        points to the input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_conj_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t numSamples);
-
-/**
- * @brief  Q31 complex conjugate.
- * @param[in]  pSrc        points to the input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_conj_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q15 complex conjugate.
- * @param[in]  pSrc        points to the input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_conj_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Floating-point complex magnitude squared
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_squared_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q31 complex magnitude squared
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_squared_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q15 complex magnitude squared
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_squared_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t numSamples);
-
-
-/**
-  * @ingroup groupController
-  */
-
-/**
- * @defgroup PID PID Motor Control
- *
- * A Proportional Integral Derivative (PID) controller is a generic feedback control
- * loop mechanism widely used in industrial control systems.
- * A PID controller is the most commonly used type of feedback controller.
- *
- * This set of functions implements (PID) controllers
- * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
- * of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
- * is the input sample value. The functions return the output value.
- *
- * \par Algorithm:
- * <pre>
- *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- *    A0 = Kp + Ki + Kd
- *    A1 = (-Kp ) - (2 * Kd )
- *    A2 = Kd  </pre>
- *
- * \par
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
- *
- * \par
- * \image html PID.gif "Proportional Integral Derivative Controller"
- *
- * \par
- * The PID controller calculates an "error" value as the difference between
- * the measured output and the reference input.
- * The controller attempts to minimize the error by adjusting the process control inputs.
- * The proportional value determines the reaction to the current error,
- * the integral value determines the reaction based on the sum of recent errors,
- * and the derivative value determines the reaction based on the rate at which the error has been changing.
- *
- * \par Instance Structure
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
- * A separate instance structure must be defined for each PID Controller.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Reset Functions
- * There is also an associated reset function for each data type which clears the state array.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
- * - Zeros out the values in the state buffer.
- *
- * \par
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the PID Controller functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup PID
- * @{
- */
-
-/**
- * @brief  Process function for the floating-point PID Control.
- * @param[in,out] S   is an instance of the floating-point PID Control structure
- * @param[in]     in  input sample to process
- * @return out processed output sample.
- */
-CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
-    arm_pid_instance_f32* S,
-    float32_t in)
-{
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-          (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-}
-
-/**
- * @brief  Process function for the Q31 PID Control.
- * @param[in,out] S  points to an instance of the Q31 PID Control structure
- * @param[in]     in  input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
-CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
-    arm_pid_instance_q31* S,
-    q31_t in)
-{
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31u);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-}
-
-
-/**
- * @brief  Process function for the Q15 PID Control.
- * @param[in,out] S   points to an instance of the Q15 PID Control structure
- * @param[in]     in  input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
-CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
-    arm_pid_instance_q15* S,
-    q15_t in)
-{
-    q63_t acc;
-    q15_t out;
-
-#if defined (ARM_MATH_DSP)
-    __SIMD32_TYPE* vstate;
-
-    /* Implementation of PID controller */
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    vstate = __SIMD32_CONST(S->state);
-    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t) * vstate, (uint64_t)acc);
-#else
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-}
-
-/**
- * @} end of PID group
- */
-
-
-/**
- * @brief Floating-point matrix inverse.
- * @param[in]  src   points to the instance of the input floating-point matrix structure.
- * @param[out] dst   points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
-arm_status arm_mat_inverse_f32(
-    const arm_matrix_instance_f32* src,
-    arm_matrix_instance_f32* dst);
-
-
-/**
- * @brief Floating-point matrix inverse.
- * @param[in]  src   points to the instance of the input floating-point matrix structure.
- * @param[out] dst   points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
-arm_status arm_mat_inverse_f64(
-    const arm_matrix_instance_f64* src,
-    arm_matrix_instance_f64* dst);
-
-
-
-/**
- * @ingroup groupController
- */
-
-/**
- * @defgroup clarke Vector Clarke Transform
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
- * \image html clarke.gif Stator current space vector and its components in (a,b).
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeFormula.gif
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup clarke
- * @{
- */
-
-/**
- *
- * @brief  Floating-point Clarke transform
- * @param[in]  Ia       input three-phase coordinate <code>a</code>
- * @param[in]  Ib       input three-phase coordinate <code>b</code>
- * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
- */
-CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
-    float32_t Ia,
-    float32_t Ib,
-    float32_t* pIalpha,
-    float32_t* pIbeta)
-{
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-}
-
-
-/**
- * @brief  Clarke transform for Q31 version
- * @param[in]  Ia       input three-phase coordinate <code>a</code>
- * @param[in]  Ib       input three-phase coordinate <code>b</code>
- * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
-    q31_t Ia,
-    q31_t Ib,
-    q31_t* pIalpha,
-    q31_t* pIbeta)
-{
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-}
-
-/**
- * @} end of clarke group
- */
-
-/**
- * @brief  Converts the elements of the Q7 vector to Q31 vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_q7_to_q31(
-    q7_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-
-/**
- * @ingroup groupController
- */
-
-/**
- * @defgroup inv_clarke Vector Inverse Clarke Transform
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeInvFormula.gif
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup inv_clarke
- * @{
- */
-
-/**
-* @brief  Floating-point Inverse Clarke transform
-* @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
-* @param[in]  Ibeta   input two-phase orthogonal vector axis beta
-* @param[out] pIa     points to output three-phase coordinate <code>a</code>
-* @param[out] pIb     points to output three-phase coordinate <code>b</code>
-*/
-CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
-    float32_t Ialpha,
-    float32_t Ibeta,
-    float32_t* pIa,
-    float32_t* pIb)
-{
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
-}
-
-
-/**
- * @brief  Inverse Clarke transform for Q31 version
- * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
- * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
- * @param[out] pIa     points to output three-phase coordinate <code>a</code>
- * @param[out] pIb     points to output three-phase coordinate <code>b</code>
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the subtraction, hence there is no risk of overflow.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
-    q31_t Ialpha,
-    q31_t Ibeta,
-    q31_t* pIa,
-    q31_t* pIb)
-{
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-}
-
-/**
- * @} end of inv_clarke group
- */
-
-/**
- * @brief  Converts the elements of the Q7 vector to Q15 vector.
- * @param[in]  pSrc       input pointer
- * @param[out] pDst       output pointer
- * @param[in]  blockSize  number of samples to process
- */
-void arm_q7_to_q15(
-    q7_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-
-/**
- * @ingroup groupController
- */
-
-/**
- * @defgroup park Vector Park Transform
- *
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
- * from the stationary to the moving reference frame and control the spatial relationship between
- * the stator vector current and rotor flux vector.
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the
- * current vector and the relationship from the two reference frames:
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkFormula.gif
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup park
- * @{
- */
-
-/**
- * @brief Floating-point Park transform
- * @param[in]  Ialpha  input two-phase vector coordinate alpha
- * @param[in]  Ibeta   input two-phase vector coordinate beta
- * @param[out] pId     points to output   rotor reference frame d
- * @param[out] pIq     points to output   rotor reference frame q
- * @param[in]  sinVal  sine value of rotation angle theta
- * @param[in]  cosVal  cosine value of rotation angle theta
- *
- * The function implements the forward Park transform.
- *
- */
-CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
-    float32_t Ialpha,
-    float32_t Ibeta,
-    float32_t* pId,
-    float32_t* pIq,
-    float32_t sinVal,
-    float32_t cosVal)
-{
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-}
-
-
-/**
- * @brief  Park transform for Q31 version
- * @param[in]  Ialpha  input two-phase vector coordinate alpha
- * @param[in]  Ibeta   input two-phase vector coordinate beta
- * @param[out] pId     points to output rotor reference frame d
- * @param[out] pIq     points to output rotor reference frame q
- * @param[in]  sinVal  sine value of rotation angle theta
- * @param[in]  cosVal  cosine value of rotation angle theta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
-    q31_t Ialpha,
-    q31_t Ibeta,
-    q31_t* pId,
-    q31_t* pIq,
-    q31_t sinVal,
-    q31_t cosVal)
-{
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-}
-
-/**
- * @} end of park group
- */
-
-/**
- * @brief  Converts the elements of the Q7 vector to floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q7_to_float(
-    q7_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @ingroup groupController
- */
-
-/**
- * @defgroup inv_park Vector Inverse Park transform
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkInvFormula.gif
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
-/**
- * @addtogroup inv_park
- * @{
- */
-
-/**
-* @brief  Floating-point Inverse Park transform
-* @param[in]  Id       input coordinate of rotor reference frame d
-* @param[in]  Iq       input coordinate of rotor reference frame q
-* @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
-* @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
-* @param[in]  sinVal   sine value of rotation angle theta
-* @param[in]  cosVal   cosine value of rotation angle theta
-*/
-CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
-    float32_t Id,
-    float32_t Iq,
-    float32_t* pIalpha,
-    float32_t* pIbeta,
-    float32_t sinVal,
-    float32_t cosVal)
-{
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-}
-
-
-/**
- * @brief  Inverse Park transform for   Q31 version
- * @param[in]  Id       input coordinate of rotor reference frame d
- * @param[in]  Iq       input coordinate of rotor reference frame q
- * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
- * @param[in]  sinVal   sine value of rotation angle theta
- * @param[in]  cosVal   cosine value of rotation angle theta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
-    q31_t Id,
-    q31_t Iq,
-    q31_t* pIalpha,
-    q31_t* pIbeta,
-    q31_t sinVal,
-    q31_t cosVal)
-{
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-}
-
-/**
- * @} end of Inverse park group
- */
-
-
-/**
- * @brief  Converts the elements of the Q31 vector to floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q31_to_float(
-    q31_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-/**
- * @ingroup groupInterpolation
- */
-
-/**
- * @defgroup LinearInterpolate Linear Interpolation
- *
- * Linear interpolation is a method of curve fitting using linear polynomials.
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
- *
- * \par
- * \image html LinearInterp.gif "Linear interpolation"
- *
- * \par
- * A  Linear Interpolate function calculates an output value(y), for the input(x)
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
- *
- * \par Algorithm:
- * <pre>
- *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- *       where x0, x1 are nearest values of input x
- *             y0, y1 are nearest values to output y
- * </pre>
- *
- * \par
- * This set of functions implements Linear interpolation process
- * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
- * sample of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.
- * <code>x</code> is the input sample value. The functions returns the output value.
- *
- * \par
- * if x is outside of the table boundary, Linear interpolation returns first value of the table
- * if x is below input range and returns last value of table if x is above range.
- */
-
-/**
- * @addtogroup LinearInterpolate
- * @{
- */
-
-/**
- * @brief  Process function for the floating-point Linear Interpolation Function.
- * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
- * @param[in]     x  input sample to process
- * @return y processed output sample.
- *
- */
-CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
-    arm_linear_interp_instance_f32* S,
-    float32_t x)
-{
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t* pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (int32_t) ((x - S->x1) / xSpacing);
-
-    if (i < 0) {
-        /* Iniatilize output for below specified range as least output value of table */
-        y = pYData[0];
-    }
-    else if ((uint32_t)i >= S->nValues) {
-        /* Iniatilize output for above specified range as last output value of table */
-        y = pYData[S->nValues - 1];
-    }
-    else {
-        /* Calculation of nearest input values */
-        x0 = S->x1 +  i      * xSpacing;
-        x1 = S->x1 + (i + 1) * xSpacing;
-
-        /* Read of nearest output values */
-        y0 = pYData[i];
-        y1 = pYData[i + 1];
-
-        /* Calculation of output */
-        y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-}
-
-
-/**
-*
-* @brief  Process function for the Q31 Linear Interpolation Function.
-* @param[in] pYData   pointer to Q31 Linear Interpolation table
-* @param[in] x        input sample to process
-* @param[in] nValues  number of table values
-* @return y processed output sample.
-*
-* \par
-* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-* This function can support maximum of table size 2^12.
-*
-*/
-CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
-    q31_t* pYData,
-    q31_t x,
-    uint32_t nValues)
-{
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (q31_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1)) {
-        return (pYData[nValues - 1]);
-    }
-    else if (index < 0) {
-        return (pYData[0]);
-    }
-    else {
-        /* 20 bits for the fractional part */
-        /* shift left by 11 to keep fract in 1.31 format */
-        fract = (x & 0x000FFFFF) << 11;
-
-        /* Read two nearest output values from the index in 1.31(q31) format */
-        y0 = pYData[index];
-        y1 = pYData[index + 1];
-
-        /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-        y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-        /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-        y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-        /* Convert y to 1.31 format */
-        return (y << 1u);
-    }
-}
-
-
-/**
- *
- * @brief  Process function for the Q15 Linear Interpolation Function.
- * @param[in] pYData   pointer to Q15 Linear Interpolation table
- * @param[in] x        input sample to process
- * @param[in] nValues  number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
-CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
-    q15_t* pYData,
-    q31_t x,
-    uint32_t nValues)
-{
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & (int32_t)0xFFF00000) >> 20);
-
-    if (index >= (int32_t)(nValues - 1)) {
-        return (pYData[nValues - 1]);
-    }
-    else if (index < 0) {
-        return (pYData[0]);
-    }
-    else {
-        /* 20 bits for the fractional part */
-        /* fract is in 12.20 format */
-        fract = (x & 0x000FFFFF);
-
-        /* Read two nearest output values from the index */
-        y0 = pYData[index];
-        y1 = pYData[index + 1];
-
-        /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-        y = ((q63_t) y0 * (0xFFFFF - fract));
-
-        /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-        y += ((q63_t) y1 * (fract));
-
-        /* convert y to 1.15 format */
-        return (q15_t) (y >> 20);
-    }
-}
-
-
-/**
- *
- * @brief  Process function for the Q7 Linear Interpolation Function.
- * @param[in] pYData   pointer to Q7 Linear Interpolation table
- * @param[in] x        input sample to process
- * @param[in] nValues  number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- */
-CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
-    q7_t* pYData,
-    q31_t x,
-    uint32_t nValues)
-{
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    uint32_t index;                              /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    if (x < 0) {
-        return (pYData[0]);
-    }
-    index = (x >> 20) & 0xfff;
-
-    if (index >= (nValues - 1)) {
-        return (pYData[nValues - 1]);
-    }
-    else {
-        /* 20 bits for the fractional part */
-        /* fract is in 12.20 format */
-        fract = (x & 0x000FFFFF);
-
-        /* Read two nearest output values from the index and are in 1.7(q7) format */
-        y0 = pYData[index];
-        y1 = pYData[index + 1];
-
-        /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-        y = ((y0 * (0xFFFFF - fract)));
-
-        /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-        y += (y1 * fract);
-
-        /* convert y to 1.7(q7) format */
-        return (q7_t) (y >> 20);
-    }
-}
-
-/**
- * @} end of LinearInterpolate group
- */
-
-/**
- * @brief  Fast approximation to the trigonometric sine function for floating-point data.
- * @param[in] x  input value in radians.
- * @return  sin(x).
- */
-float32_t arm_sin_f32(
-    float32_t x);
-
-
-/**
- * @brief  Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x  Scaled input value in radians.
- * @return  sin(x).
- */
-q31_t arm_sin_q31(
-    q31_t x);
-
-
-/**
- * @brief  Fast approximation to the trigonometric sine function for Q15 data.
- * @param[in] x  Scaled input value in radians.
- * @return  sin(x).
- */
-q15_t arm_sin_q15(
-    q15_t x);
-
-
-/**
- * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
- * @param[in] x  input value in radians.
- * @return  cos(x).
- */
-float32_t arm_cos_f32(
-    float32_t x);
-
-
-/**
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.
- * @param[in] x  Scaled input value in radians.
- * @return  cos(x).
- */
-q31_t arm_cos_q31(
-    q31_t x);
-
-
-/**
- * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
- * @param[in] x  Scaled input value in radians.
- * @return  cos(x).
- */
-q15_t arm_cos_q15(
-    q15_t x);
-
-
-/**
- * @ingroup groupFastMath
- */
-
-
-/**
- * @defgroup SQRT Square Root
- *
- * Computes the square root of a number.
- * There are separate functions for Q15, Q31, and floating-point data types.
- * The square root function is computed using the Newton-Raphson algorithm.
- * This is an iterative algorithm of the form:
- * <pre>
- *      x1 = x0 - f(x0)/f'(x0)
- * </pre>
- * where <code>x1</code> is the current estimate,
- * <code>x0</code> is the previous estimate, and
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
- * For the square root function, the algorithm reduces to:
- * <pre>
- *     x0 = in/2                         [initial guess]
- *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
- * </pre>
- */
-
-
-/**
- * @addtogroup SQRT
- * @{
- */
-
-/**
- * @brief  Floating-point square root function.
- * @param[in]  in    input value.
- * @param[out] pOut  square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
-CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
-    float32_t in,
-    float32_t* pOut)
-{
-    if (in >= 0.0f) {
-
-#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
-        *pOut = __sqrtf(in);
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-        *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined(__GNUC__)
-        *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
-        __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
-#else
-        *pOut = sqrtf(in);
-#endif
-
-        return (ARM_MATH_SUCCESS);
-    }
-    else {
-        *pOut = 0.0f;
-        return (ARM_MATH_ARGUMENT_ERROR);
-    }
-}
-
-
-/**
- * @brief Q31 square root function.
- * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
- * @param[out] pOut  square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
-arm_status arm_sqrt_q31(
-    q31_t in,
-    q31_t* pOut);
-
-
-/**
- * @brief  Q15 square root function.
- * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
- * @param[out] pOut  square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
-arm_status arm_sqrt_q15(
-    q15_t in,
-    q15_t* pOut);
-
-/**
- * @} end of SQRT group
- */
-
-
-/**
- * @brief floating-point Circular write function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
-    int32_t* circBuffer,
-    int32_t L,
-    uint16_t* writeOffset,
-    int32_t bufferInc,
-    const int32_t* src,
-    int32_t srcInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the input sample to the circular buffer */
-        circBuffer[wOffset] = *src;
-
-        /* Update the input pointer */
-        src += srcInc;
-
-        /* Circularly update wOffset.  Watch out for positive and negative value */
-        wOffset += bufferInc;
-        if (wOffset >= L)
-            wOffset -= L;
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-}
-
-
-
-/**
- * @brief floating-point Circular Read function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
-    int32_t* circBuffer,
-    int32_t L,
-    int32_t* readOffset,
-    int32_t bufferInc,
-    int32_t* dst,
-    int32_t* dst_base,
-    int32_t dst_length,
-    int32_t dstInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0u;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the sample from the circular buffer to the destination buffer */
-        *dst = circBuffer[rOffset];
-
-        /* Update the input pointer */
-        dst += dstInc;
-
-        if (dst == (int32_t*) dst_end) {
-            dst = dst_base;
-        }
-
-        /* Circularly update rOffset.  Watch out for positive and negative value  */
-        rOffset += bufferInc;
-
-        if (rOffset >= L) {
-            rOffset -= L;
-        }
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-}
-
-
-/**
- * @brief Q15 Circular write function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
-    q15_t* circBuffer,
-    int32_t L,
-    uint16_t* writeOffset,
-    int32_t bufferInc,
-    const q15_t* src,
-    int32_t srcInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the input sample to the circular buffer */
-        circBuffer[wOffset] = *src;
-
-        /* Update the input pointer */
-        src += srcInc;
-
-        /* Circularly update wOffset.  Watch out for positive and negative value */
-        wOffset += bufferInc;
-        if (wOffset >= L)
-            wOffset -= L;
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-}
-
-
-/**
- * @brief Q15 Circular Read function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
-    q15_t* circBuffer,
-    int32_t L,
-    int32_t* readOffset,
-    int32_t bufferInc,
-    q15_t* dst,
-    q15_t* dst_base,
-    int32_t dst_length,
-    int32_t dstInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the sample from the circular buffer to the destination buffer */
-        *dst = circBuffer[rOffset];
-
-        /* Update the input pointer */
-        dst += dstInc;
-
-        if (dst == (q15_t*) dst_end) {
-            dst = dst_base;
-        }
-
-        /* Circularly update wOffset.  Watch out for positive and negative value */
-        rOffset += bufferInc;
-
-        if (rOffset >= L) {
-            rOffset -= L;
-        }
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-}
-
-
-/**
- * @brief Q7 Circular write function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
-    q7_t* circBuffer,
-    int32_t L,
-    uint16_t* writeOffset,
-    int32_t bufferInc,
-    const q7_t* src,
-    int32_t srcInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the input sample to the circular buffer */
-        circBuffer[wOffset] = *src;
-
-        /* Update the input pointer */
-        src += srcInc;
-
-        /* Circularly update wOffset.  Watch out for positive and negative value */
-        wOffset += bufferInc;
-        if (wOffset >= L)
-            wOffset -= L;
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = (uint16_t)wOffset;
-}
-
-
-/**
- * @brief Q7 Circular Read function.
- */
-CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
-    q7_t* circBuffer,
-    int32_t L,
-    int32_t* readOffset,
-    int32_t bufferInc,
-    q7_t* dst,
-    q7_t* dst_base,
-    int32_t dst_length,
-    int32_t dstInc,
-    uint32_t blockSize)
-{
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while (i > 0u) {
-        /* copy the sample from the circular buffer to the destination buffer */
-        *dst = circBuffer[rOffset];
-
-        /* Update the input pointer */
-        dst += dstInc;
-
-        if (dst == (q7_t*) dst_end) {
-            dst = dst_base;
-        }
-
-        /* Circularly update rOffset.  Watch out for positive and negative value */
-        rOffset += bufferInc;
-
-        if (rOffset >= L) {
-            rOffset -= L;
-        }
-
-        /* Decrement the loop counter */
-        i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-}
-
-
-/**
- * @brief  Sum of the squares of the elements of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_power_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q63_t* pResult);
-
-
-/**
- * @brief  Sum of the squares of the elements of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_power_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult);
-
-
-/**
- * @brief  Sum of the squares of the elements of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_power_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q63_t* pResult);
-
-
-/**
- * @brief  Sum of the squares of the elements of a Q7 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_power_q7(
-    q7_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult);
-
-
-/**
- * @brief  Mean value of a Q7 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_mean_q7(
-    q7_t* pSrc,
-    uint32_t blockSize,
-    q7_t* pResult);
-
-
-/**
- * @brief  Mean value of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_mean_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult);
-
-
-/**
- * @brief  Mean value of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_mean_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult);
-
-
-/**
- * @brief  Mean value of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_mean_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult);
-
-
-/**
- * @brief  Variance of the elements of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_var_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult);
-
-
-/**
- * @brief  Variance of the elements of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_var_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult);
-
-
-/**
- * @brief  Variance of the elements of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_var_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult);
-
-
-/**
- * @brief  Root Mean Square of the elements of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_rms_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult);
-
-
-/**
- * @brief  Root Mean Square of the elements of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_rms_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult);
-
-
-/**
- * @brief  Root Mean Square of the elements of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_rms_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult);
-
-
-/**
- * @brief  Standard deviation of the elements of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_std_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult);
-
-
-/**
- * @brief  Standard deviation of the elements of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_std_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult);
-
-
-/**
- * @brief  Standard deviation of the elements of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output value.
- */
-void arm_std_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult);
-
-
-/**
- * @brief  Floating-point complex magnitude
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_f32(
-    float32_t* pSrc,
-    float32_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q31 complex magnitude
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_q31(
-    q31_t* pSrc,
-    q31_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q15 complex magnitude
- * @param[in]  pSrc        points to the complex input vector
- * @param[out] pDst        points to the real output vector
- * @param[in]  numSamples  number of complex samples in the input vector
- */
-void arm_cmplx_mag_q15(
-    q15_t* pSrc,
-    q15_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q15 complex dot product
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[in]  numSamples  number of complex samples in each vector
- * @param[out] realResult  real part of the result returned here
- * @param[out] imagResult  imaginary part of the result returned here
- */
-void arm_cmplx_dot_prod_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    uint32_t numSamples,
-    q31_t* realResult,
-    q31_t* imagResult);
-
-
-/**
- * @brief  Q31 complex dot product
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[in]  numSamples  number of complex samples in each vector
- * @param[out] realResult  real part of the result returned here
- * @param[out] imagResult  imaginary part of the result returned here
- */
-void arm_cmplx_dot_prod_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    uint32_t numSamples,
-    q63_t* realResult,
-    q63_t* imagResult);
-
-
-/**
- * @brief  Floating-point complex dot product
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[in]  numSamples  number of complex samples in each vector
- * @param[out] realResult  real part of the result returned here
- * @param[out] imagResult  imaginary part of the result returned here
- */
-void arm_cmplx_dot_prod_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    uint32_t numSamples,
-    float32_t* realResult,
-    float32_t* imagResult);
-
-
-/**
- * @brief  Q15 complex-by-real multiplication
- * @param[in]  pSrcCmplx   points to the complex input vector
- * @param[in]  pSrcReal    points to the real input vector
- * @param[out] pCmplxDst   points to the complex output vector
- * @param[in]  numSamples  number of samples in each vector
- */
-void arm_cmplx_mult_real_q15(
-    q15_t* pSrcCmplx,
-    q15_t* pSrcReal,
-    q15_t* pCmplxDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q31 complex-by-real multiplication
- * @param[in]  pSrcCmplx   points to the complex input vector
- * @param[in]  pSrcReal    points to the real input vector
- * @param[out] pCmplxDst   points to the complex output vector
- * @param[in]  numSamples  number of samples in each vector
- */
-void arm_cmplx_mult_real_q31(
-    q31_t* pSrcCmplx,
-    q31_t* pSrcReal,
-    q31_t* pCmplxDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Floating-point complex-by-real multiplication
- * @param[in]  pSrcCmplx   points to the complex input vector
- * @param[in]  pSrcReal    points to the real input vector
- * @param[out] pCmplxDst   points to the complex output vector
- * @param[in]  numSamples  number of samples in each vector
- */
-void arm_cmplx_mult_real_f32(
-    float32_t* pSrcCmplx,
-    float32_t* pSrcReal,
-    float32_t* pCmplxDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Minimum value of a Q7 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] result     is output pointer
- * @param[in]  index      is the array index of the minimum value in the input buffer.
- */
-void arm_min_q7(
-    q7_t* pSrc,
-    uint32_t blockSize,
-    q7_t* result,
-    uint32_t* index);
-
-
-/**
- * @brief  Minimum value of a Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output pointer
- * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
- */
-void arm_min_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief  Minimum value of a Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output pointer
- * @param[out] pIndex     is the array index of the minimum value in the input buffer.
- */
-void arm_min_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief  Minimum value of a floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[in]  blockSize  is the number of samples to process
- * @param[out] pResult    is output pointer
- * @param[out] pIndex     is the array index of the minimum value in the input buffer.
- */
-void arm_min_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-void arm_max_q7(
-    q7_t* pSrc,
-    uint32_t blockSize,
-    q7_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-void arm_max_q15(
-    q15_t* pSrc,
-    uint32_t blockSize,
-    q15_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-void arm_max_q31(
-    q31_t* pSrc,
-    uint32_t blockSize,
-    q31_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]  pSrc       points to the input buffer
- * @param[in]  blockSize  length of the input vector
- * @param[out] pResult    maximum value returned here
- * @param[out] pIndex     index of maximum value returned here
- */
-void arm_max_f32(
-    float32_t* pSrc,
-    uint32_t blockSize,
-    float32_t* pResult,
-    uint32_t* pIndex);
-
-
-/**
- * @brief  Q15 complex-by-complex multiplication
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_mult_cmplx_q15(
-    q15_t* pSrcA,
-    q15_t* pSrcB,
-    q15_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Q31 complex-by-complex multiplication
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_mult_cmplx_q31(
-    q31_t* pSrcA,
-    q31_t* pSrcB,
-    q31_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief  Floating-point complex-by-complex multiplication
- * @param[in]  pSrcA       points to the first input vector
- * @param[in]  pSrcB       points to the second input vector
- * @param[out] pDst        points to the output vector
- * @param[in]  numSamples  number of complex samples in each vector
- */
-void arm_cmplx_mult_cmplx_f32(
-    float32_t* pSrcA,
-    float32_t* pSrcB,
-    float32_t* pDst,
-    uint32_t numSamples);
-
-
-/**
- * @brief Converts the elements of the floating-point vector to Q31 vector.
- * @param[in]  pSrc       points to the floating-point input vector
- * @param[out] pDst       points to the Q31 output vector
- * @param[in]  blockSize  length of the input vector
- */
-void arm_float_to_q31(
-    float32_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Converts the elements of the floating-point vector to Q15 vector.
- * @param[in]  pSrc       points to the floating-point input vector
- * @param[out] pDst       points to the Q15 output vector
- * @param[in]  blockSize  length of the input vector
- */
-void arm_float_to_q15(
-    float32_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief Converts the elements of the floating-point vector to Q7 vector.
- * @param[in]  pSrc       points to the floating-point input vector
- * @param[out] pDst       points to the Q7 output vector
- * @param[in]  blockSize  length of the input vector
- */
-void arm_float_to_q7(
-    float32_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Converts the elements of the Q31 vector to Q15 vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q31_to_q15(
-    q31_t* pSrc,
-    q15_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Converts the elements of the Q31 vector to Q7 vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q31_to_q7(
-    q31_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Converts the elements of the Q15 vector to floating-point vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q15_to_float(
-    q15_t* pSrc,
-    float32_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Converts the elements of the Q15 vector to Q31 vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q15_to_q31(
-    q15_t* pSrc,
-    q31_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @brief  Converts the elements of the Q15 vector to Q7 vector.
- * @param[in]  pSrc       is input pointer
- * @param[out] pDst       is output pointer
- * @param[in]  blockSize  is the number of samples to process
- */
-void arm_q15_to_q7(
-    q15_t* pSrc,
-    q7_t* pDst,
-    uint32_t blockSize);
-
-
-/**
- * @ingroup groupInterpolation
- */
-
-/**
- * @defgroup BilinearInterpolate Bilinear Interpolation
- *
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
- * determines values between the grid points.
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
- * Bilinear interpolation is often used in image processing to rescale images.
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
- *
- * <b>Algorithm</b>
- * \par
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
- * For floating-point, the instance structure is defined as:
- * <pre>
- *   typedef struct
- *   {
- *     uint16_t numRows;
- *     uint16_t numCols;
- *     float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- * </pre>
- *
- * \par
- * where <code>numRows</code> specifies the number of rows in the table;
- * <code>numCols</code> specifies the number of columns in the table;
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
- *
- * \par
- * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
- * <pre>
- *     XF = floor(x)
- *     YF = floor(y)
- * </pre>
- * \par
- * The interpolated output point is computed as:
- * <pre>
- *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
- * </pre>
- * Note that the coordinates (x, y) contain integer and fractional components.
- * The integer components specify which portion of the table to use while the
- * fractional components control the interpolation processor.
- *
- * \par
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
- */
-
-/**
- * @addtogroup BilinearInterpolate
- * @{
- */
-
-
-/**
-*
-* @brief  Floating-point bilinear interpolation.
-* @param[in,out] S  points to an instance of the interpolation structure.
-* @param[in]     X  interpolation coordinate.
-* @param[in]     Y  interpolation coordinate.
-* @return out interpolated value.
-*/
-CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
-    const arm_bilinear_interp_instance_f32* S,
-    float32_t X,
-    float32_t Y)
-{
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t* pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) {
-        return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-}
-
-
-/**
-*
-* @brief  Q31 bilinear interpolation.
-* @param[in,out] S  points to an instance of the interpolation structure.
-* @param[in]     X  interpolation coordinate in 12.20 format.
-* @param[in]     Y  interpolation coordinate in 12.20 format.
-* @return out interpolated value.
-*/
-CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
-    arm_bilinear_interp_instance_q31* S,
-    q31_t X,
-    q31_t Y)
-{
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t* pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
-        return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
-    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
-    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return ((q31_t)(acc << 2));
-}
-
-
-/**
-* @brief  Q15 bilinear interpolation.
-* @param[in,out] S  points to an instance of the interpolation structure.
-* @param[in]     X  interpolation coordinate in 12.20 format.
-* @param[in]     Y  interpolation coordinate in 12.20 format.
-* @return out interpolated value.
-*/
-CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
-    arm_bilinear_interp_instance_q15* S,
-    q31_t X,
-    q31_t Y)
-{
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t* pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
-        return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return ((q15_t)(acc >> 36));
-}
-
-
-/**
-* @brief  Q7 bilinear interpolation.
-* @param[in,out] S  points to an instance of the interpolation structure.
-* @param[in]     X  interpolation coordinate in 12.20 format.
-* @param[in]     Y  interpolation coordinate in 12.20 format.
-* @return out interpolated value.
-*/
-CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
-    arm_bilinear_interp_instance_q7* S,
-    q31_t X,
-    q31_t Y)
-{
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t* pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & (q31_t)0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
-        return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
-    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & (q31_t)0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
-    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return ((q7_t)(acc >> 40));
-}
-
-/**
- * @} end of BilinearInterpolate group
- */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
-    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
-    a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
-    a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
-    a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if   defined ( __CC_ARM )
-/* Enter low optimization region - place directly above function definition */
-#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
-#define LOW_OPTIMIZATION_ENTER \
-    _Pragma ("push")         \
-    _Pragma ("O1")
-#else
-#define LOW_OPTIMIZATION_ENTER
-#endif
-
-/* Exit low optimization region - place directly after end of function definition */
-#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-#define LOW_OPTIMIZATION_EXIT \
-    _Pragma ("pop")
-#else
-#define LOW_OPTIMIZATION_EXIT
-#endif
-
-/* Enter low optimization region - place directly above function definition */
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-/* Exit low optimization region - place directly after end of function definition */
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
-#define LOW_OPTIMIZATION_ENTER \
-    __attribute__(( optimize("-O1") ))
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
-/* Enter low optimization region - place directly above function definition */
-#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-#define LOW_OPTIMIZATION_ENTER \
-    _Pragma ("optimize=low")
-#else
-#define LOW_OPTIMIZATION_ENTER
-#endif
-
-/* Exit low optimization region - place directly after end of function definition */
-#define LOW_OPTIMIZATION_EXIT
-
-/* Enter low optimization region - place directly above function definition */
-#if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-    _Pragma ("optimize=low")
-#else
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#endif
-
-/* Exit low optimization region - place directly after end of function definition */
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef   __cplusplus
-}
-#endif
-
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#endif
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h
deleted file mode 100644
index 4617b1280..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armcc.h
+++ /dev/null
@@ -1,796 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_armcc.h
- * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
- * @version  V5.0.1
- * @date     03. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCC_H
-#define __CMSIS_ARMCC_H
-
-
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* CMSIS compiler control architecture macros */
-#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
-     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
-#define __ARM_ARCH_6M__           1
-#endif
-
-#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
-#define __ARM_ARCH_7M__           1
-#endif
-
-#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
-#define __ARM_ARCH_7EM__          1
-#endif
-
-/* __ARM_ARCH_8M_BASE__  not applicable */
-/* __ARM_ARCH_8M_MAIN__  not applicable */
-
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  __inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static __inline
-#endif
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __declspec(noreturn)
-#endif
-#ifndef   __USED
-#define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-#define __UNALIGNED_UINT32(x)     (*((__packed uint32_t *)(x)))
-#endif
-#ifndef   __ALIGNED
-#define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __attribute__((packed))
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           __packed struct
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();     */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();    */
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-    register uint32_t __regControl         __ASM("control");
-    return(__regControl);
-}
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-    register uint32_t __regControl         __ASM("control");
-    __regControl = control;
-}
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-    register uint32_t __regIPSR          __ASM("ipsr");
-    return(__regIPSR);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-    register uint32_t __regAPSR          __ASM("apsr");
-    return(__regAPSR);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-    register uint32_t __regXPSR          __ASM("xpsr");
-    return(__regXPSR);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-    register uint32_t __regProcessStackPointer  __ASM("psp");
-    return(__regProcessStackPointer);
-}
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-    register uint32_t __regProcessStackPointer  __ASM("psp");
-    __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-    register uint32_t __regMainStackPointer     __ASM("msp");
-    return(__regMainStackPointer);
-}
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-    register uint32_t __regMainStackPointer     __ASM("msp");
-    __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-    register uint32_t __regPriMask         __ASM("primask");
-    return(__regPriMask);
-}
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-    register uint32_t __regPriMask         __ASM("primask");
-    __regPriMask = (priMask);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-    register uint32_t __regBasePri         __ASM("basepri");
-    return(__regBasePri);
-}
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-    register uint32_t __regBasePri         __ASM("basepri");
-    __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-    register uint32_t __regBasePriMax      __ASM("basepri_max");
-    __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-    register uint32_t __regFaultMask       __ASM("faultmask");
-    return(__regFaultMask);
-}
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-    register uint32_t __regFaultMask       __ASM("faultmask");
-    __regFaultMask = (faultMask & (uint32_t)1U);
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    register uint32_t __regfpscr         __ASM("fpscr");
-    return(__regfpscr);
-#else
-    return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    register uint32_t __regfpscr         __ASM("fpscr");
-    __regfpscr = (fpscr);
-#else
-    (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB() do {\
-        __schedule_barrier();\
-        __isb(0xF);\
-        __schedule_barrier();\
-    } while (0U)
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
-        __schedule_barrier();\
-        __dsb(0xF);\
-        __schedule_barrier();\
-    } while (0U)
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
-        __schedule_barrier();\
-        __dmb(0xF);\
-        __schedule_barrier();\
-    } while (0U)
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-    rev16 r0, r0
-    bx lr
-}
-#endif
-
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-    revsh r0, r0
-    bx lr
-}
-#endif
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-#define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-    uint32_t result;
-    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
-    result = value;                      /* r will be reversed bits of v; first get LSB of v */
-    for (value >>= 1U; value; value >>= 1U) {
-        result <<= 1U;
-        result |= value & 1U;
-        s--;
-    }
-    result <<= s;                        /* shift when v's highest bits are zero */
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
-#else
-#define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
-#else
-#define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
-#else
-#define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __STREXB(value, ptr)                                                 __strex(value, ptr)
-#else
-#define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __STREXH(value, ptr)                                                 __strex(value, ptr)
-#else
-#define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-#define __STREXW(value, ptr)                                                 __strex(value, ptr)
-#else
-#define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX                           __clrex
-
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-    rrx r0, r0
-    bx lr
-}
-#endif
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h
deleted file mode 100644
index 6b21a5bea..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_armclang.h
+++ /dev/null
@@ -1,1735 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_armclang.h
- * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
- * @version  V5.0.1
- * @date     02. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCLANG_H
-#define __CMSIS_ARMCLANG_H
-
-#ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  __inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static __inline
-#endif
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __attribute__((noreturn))
-#endif
-#ifndef   __USED
-#define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-#pragma clang diagnostic push
-#pragma clang diagnostic ignored "-Wpacked"
-struct __attribute__((packed)) T_UINT32 {
-    uint32_t v;
-};
-#pragma clang diagnostic pop
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           struct __attribute__((packed, aligned(1)))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, control" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-    __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-    __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-    __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-    __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msp" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-    __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-    __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, primask" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-    __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-    __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-    __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-    __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-    return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-    __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-    __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
-    return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-    __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-    __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-/* #define __get_FPSCR      __builtin_arm_get_fpscr */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    uint32_t result;
-
-    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-    return(result);
-#else
-    return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-/* #define __set_FPSCR      __builtin_arm_set_fpscr */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
-#else
-    (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP          __builtin_arm_nop
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI          __builtin_arm_wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE          __builtin_arm_wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV          __builtin_arm_sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB()        __builtin_arm_isb(0xF);
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()        __builtin_arm_dsb(0xF);
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB()        __builtin_arm_dmb(0xF);
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV          __builtin_bswap32
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV16          __builtin_bswap16                /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
-#if 0
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-    uint32_t result;
-
-    __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-/* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-    int32_t result;
-
-    __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-    return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-/* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-    uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
-    result = value;                      /* r will be reversed bits of v; first get LSB of v */
-    for (value >>= 1U; value; value >>= 1U) {
-        result <<= 1U;
-        result |= value & 1U;
-        s--;
-    }
-    result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-    return(result);
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB        (uint8_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH        (uint16_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW        (uint32_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXB        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXH        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXW        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX             __builtin_arm_clrex
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT             __builtin_arm_ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT             __builtin_arm_usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-    uint32_t result;
-
-    __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
-{
-    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
-{
-    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
-{
-    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
-{
-    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
-{
-    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
-{
-    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEX                  (uint32_t)__builtin_arm_stlex
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-    ({                          \
-        int32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-#define __USAT16(ARG1,ARG2) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-    uint32_t result;
-
-    __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-    uint32_t result;
-
-    __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-    int32_t result;
-
-    __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-    int32_t result;
-
-    __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-        __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-        __RES; \
-    })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-        if (ARG3 == 0) \
-            __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-        else \
-            __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-        __RES; \
-    })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
-    int32_t result;
-
-    __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCLANG_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h
deleted file mode 100644
index 89cd69027..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_compiler.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_compiler.h
- * @brief    CMSIS compiler generic header file
- * @version  V5.0.1
- * @date     30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_COMPILER_H
-#define __CMSIS_COMPILER_H
-
-#include <stdint.h>
-
-/*
- * ARM Compiler 4/5
- */
-#if   defined ( __CC_ARM )
-#include "cmsis_armcc.h"
-
-
-/*
- * ARM Compiler 6 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#include "cmsis_armclang.h"
-
-
-/*
- * GNU Compiler
- */
-#elif defined ( __GNUC__ )
-#include "cmsis_gcc.h"
-
-
-/*
- * IAR Compiler
- */
-#elif defined ( __ICCARM__ )
-
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static inline
-#endif
-
-#include <cmsis_iar.h>
-
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __noreturn
-#endif
-#ifndef   __USED
-#define __USED                    __root
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __weak
-#endif
-#ifndef   __UNALIGNED_UINT32
-__packed struct T_UINT32 {
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-#define __ALIGNED(x)
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __packed
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           __packed struct
-#endif
-
-
-/*
- * TI ARM Compiler
- */
-#elif defined ( __TI_ARM__ )
-#include <cmsis_ccs.h>
-
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static inline
-#endif
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __attribute__((noreturn))
-#endif
-#ifndef   __USED
-#define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-struct __attribute__((packed)) T_UINT32 {
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __attribute__((packed))
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           struct __attribute__((packed))
-#endif
-
-
-/*
- * TASKING Compiler
- */
-#elif defined ( __TASKING__ )
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static inline
-#endif
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __attribute__((noreturn))
-#endif
-#ifndef   __USED
-#define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-struct __packed__ T_UINT32 {
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#define __ALIGNED(x)              __align(x)
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __packed__
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           struct __packed__
-#endif
-
-
-/*
- * COSMIC Compiler
- */
-#elif defined ( __CSMC__ )
-#include <cmsis_csm.h>
-
-#ifndef   __ASM
-#define __ASM                     _asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static inline
-#endif
-#ifndef   __NO_RETURN
-// NO RETURN is automatically detected hence no warning here
-#define __NO_RETURN
-#endif
-#ifndef   __USED
-#warning No compiler specific solution for __USED. __USED is ignored.
-#define __USED
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __weak
-#endif
-#ifndef   __UNALIGNED_UINT32
-@packed struct T_UINT32 {
-    uint32_t v;
-};
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-#define __ALIGNED(x)
-#endif
-#ifndef   __PACKED
-#define __PACKED                  @packed
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           @packed struct
-#endif
-
-
-#else
-#error Unknown compiler.
-#endif
-
-
-#endif /* __CMSIS_COMPILER_H */
-
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h
deleted file mode 100644
index 919f26d15..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/cmsis_gcc.h
+++ /dev/null
@@ -1,1900 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_gcc.h
- * @brief    CMSIS compiler GCC header file
- * @version  V5.0.1
- * @date     02. February 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-#define __ASM                     __asm
-#endif
-#ifndef   __INLINE
-#define __INLINE                  inline
-#endif
-#ifndef   __STATIC_INLINE
-#define __STATIC_INLINE           static inline
-#endif
-#ifndef   __NO_RETURN
-#define __NO_RETURN               __attribute__((noreturn))
-#endif
-#ifndef   __USED
-#define __USED                    __attribute__((used))
-#endif
-#ifndef   __WEAK
-#define __WEAK                    __attribute__((weak))
-#endif
-#ifndef   __UNALIGNED_UINT32
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpacked"
-#pragma GCC diagnostic ignored "-Wattributes"
-struct __attribute__((packed)) T_UINT32 {
-    uint32_t v;
-};
-#pragma GCC diagnostic pop
-#define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __ALIGNED
-#define __ALIGNED(x)              __attribute__((aligned(x)))
-#endif
-#ifndef   __PACKED
-#define __PACKED                  __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-#define __PACKED_STRUCT           struct __attribute__((packed, aligned(1)))
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
-{
-    __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
-{
-    __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, control" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-    __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-    __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-    return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-    __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-    __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msp" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-    __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-    __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, primask" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-    __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-    __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
-{
-    __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
-{
-    __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-    __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-    return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-    uint32_t result;
-
-    __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-    __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-    __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-    return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-    __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-    __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
-    return(result);
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-    register uint32_t result;
-
-    __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-    return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-    __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
-     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-    __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    uint32_t result;
-
-    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-    return(result);
-#else
-    return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#else
-    (void)fpscr;
-#endif
-}
-
-#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-//{
-//  __ASM volatile ("nop");
-//}
-#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-//{
-//  __ASM volatile ("wfi");
-//}
-#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-//{
-//  __ASM volatile ("wfe");
-//}
-#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-//{
-//  __ASM volatile ("sev");
-//}
-#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
-    __ASM volatile ("isb 0xF"::: "memory");
-}
-
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
-    __ASM volatile ("dsb 0xF"::: "memory");
-}
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
-    __ASM volatile ("dmb 0xF"::: "memory");
-}
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in integer value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-    return __builtin_bswap32(value);
-#else
-    uint32_t result;
-
-    __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-#endif
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in two unsigned short values.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-    uint32_t result;
-
-    __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-}
-
-
-/**
-  \brief   Reverse byte order in signed short value
-  \details Reverses the byte order in a signed short value with sign extension to integer.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    return (short)__builtin_bswap16(value);
-#else
-    int32_t result;
-
-    __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-#endif
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-    return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-    uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-    int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
-
-    result = value;                      /* r will be reversed bits of v; first get LSB of v */
-    for (value >>= 1U; value; value >>= 1U) {
-        result <<= 1U;
-        result |= value & 1U;
-        s--;
-    }
-    result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-    return(result);
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ             __builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-    return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-    return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-    return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr)
-{
-    uint32_t result;
-
-    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-    return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr)
-{
-    uint32_t result;
-
-    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-    return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr)
-{
-    uint32_t result;
-
-    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-    return(result);
-}
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
-    __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-    ({                          \
-        int32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-    uint32_t result;
-
-    __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-    return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-    return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-    return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* ptr)
-{
-    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* ptr)
-{
-    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* ptr)
-{
-    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t* ptr)
-{
-    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t* ptr)
-{
-    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t* ptr)
-{
-    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
-    return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-    return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-    return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t* ptr)
-{
-    uint32_t result;
-
-    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-    return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-    ({                          \
-        int32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-#define __USAT16(ARG1,ARG2) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1); \
-        __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-        __RES; \
-    })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-    uint32_t result;
-
-    __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-    uint32_t result;
-
-    __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-    uint32_t result;
-
-    __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-    union llreg_u {
-        uint32_t w32[2];
-        uint64_t w64;
-    } llr;
-    llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-    return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-    uint32_t result;
-
-    __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-    int32_t result;
-
-    __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-    int32_t result;
-
-    __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-    return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-        __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-        __RES; \
-    })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-    ({                          \
-        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-        if (ARG3 == 0) \
-            __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-        else \
-            __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-        __RES; \
-    })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
-    int32_t result;
-
-    __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-    return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h
deleted file mode 100644
index 4e65d1d95..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mbl.h
+++ /dev/null
@@ -1,1813 +0,0 @@
-/**************************************************************************//**
- * @file     core_armv8mbl.h
- * @brief    CMSIS ARMv8MBL Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MBL_H_GENERIC
-#define __CORE_ARMV8MBL_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_ARMv8MBL
-  @{
- */
-
-/*  CMSIS cmGrebe definitions */
-#define __ARMv8MBL_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
-#define __ARMv8MBL_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
-                                        __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MBL_H_DEPENDANT
-#define __CORE_ARMV8MBL_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __ARMv8MBL_REV
-#define __ARMv8MBL_REV               0x0000U
-#warning "__ARMv8MBL_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __SAUREGION_PRESENT
-#define __SAUREGION_PRESENT       0U
-#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __VTOR_PRESENT
-#define __VTOR_PRESENT            0U
-#warning "__VTOR_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          2U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-
-#ifndef __ETM_PRESENT
-#define __ETM_PRESENT             0U
-#warning "__ETM_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MTB_PRESENT
-#define __MTB_PRESENT             0U
-#warning "__MTB_PRESENT not defined in device header file; using default!"
-#endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MBL */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[16U];
-    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[16U];
-    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[16U];
-    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[16U];
-    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[16U];
-    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-    uint32_t RESERVED5[16U];
-    __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-    uint32_t RESERVED0;
-#endif
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    uint32_t RESERVED1;
-    __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    uint32_t RESERVED0[6U];
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    uint32_t RESERVED3[1U];
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    uint32_t RESERVED5[1U];
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED6[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    uint32_t RESERVED7[1U];
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-    uint32_t RESERVED9[1U];
-    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-    uint32_t RESERVED10[1U];
-    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-    uint32_t RESERVED11[1U];
-    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-    uint32_t RESERVED12[1U];
-    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-    uint32_t RESERVED13[1U];
-    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-    uint32_t RESERVED14[1U];
-    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-    uint32_t RESERVED15[1U];
-    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-    uint32_t RESERVED16[1U];
-    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-    uint32_t RESERVED17[1U];
-    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-    uint32_t RESERVED18[1U];
-    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-    uint32_t RESERVED19[1U];
-    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-    uint32_t RESERVED20[1U];
-    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-    uint32_t RESERVED21[1U];
-    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-    uint32_t RESERVED22[1U];
-    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-    uint32_t RESERVED23[1U];
-    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-    uint32_t RESERVED24[1U];
-    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-    uint32_t RESERVED25[1U];
-    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-    uint32_t RESERVED26[1U];
-    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-    uint32_t RESERVED27[1U];
-    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-    uint32_t RESERVED28[1U];
-    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-    uint32_t RESERVED29[1U];
-    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-    uint32_t RESERVED30[1U];
-    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-    uint32_t RESERVED31[1U];
-    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-    uint32_t RESERVED0[7U];
-    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-#endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for ARMv8-M Baseline */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for ARMv8-M Baseline */
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   SCB_AIRCR_SYSRESETREQ_Msk);
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                         /* Reload value impossible */
-    }
-
-    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk   |
-                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h
deleted file mode 100644
index 273c3849c..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_armv8mml.h
+++ /dev/null
@@ -1,2821 +0,0 @@
-/**************************************************************************//**
- * @file     core_armv8mml.h
- * @brief    CMSIS ARMv8MML Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     07. December 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MML_H_GENERIC
-#define __CORE_ARMV8MML_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_ARMv8MML
-  @{
- */
-
-/*  CMSIS ARMv8MML definitions */
-#define __ARMv8MML_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
-#define __ARMv8MML_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
-                                        __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MML_H_DEPENDANT
-#define __CORE_ARMV8MML_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __ARMv8MML_REV
-#define __ARMv8MML_REV               0x0000U
-#warning "__ARMv8MML_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __SAUREGION_PRESENT
-#define __SAUREGION_PRESENT       0U
-#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __DSP_PRESENT
-#define __DSP_PRESENT             0U
-#warning "__DSP_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MML */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0) */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
-        uint32_t FPCA: 1;                    /*!< bit:      2  Floating-point context active */
-        uint32_t SFPA: 1;                    /*!< bit:      3  Secure floating-point active */
-        uint32_t _reserved1: 28;             /*!< bit:  4..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[16U];
-    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[16U];
-    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[16U];
-    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[16U];
-    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[16U];
-    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-    uint32_t RESERVED5[16U];
-    __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED6[580U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-    __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-    uint32_t RESERVED3[92U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-    uint32_t RESERVED4[15U];
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
-    uint32_t RESERVED5[1U];
-    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-    uint32_t RESERVED6[1U];
-    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-    uint32_t RESERVED7[6U];
-    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-    __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[1U];
-    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
-    uint32_t RESERVED6[4U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    uint32_t RESERVED3[1U];
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    uint32_t RESERVED5[1U];
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED6[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    uint32_t RESERVED7[1U];
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-    uint32_t RESERVED9[1U];
-    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-    uint32_t RESERVED10[1U];
-    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-    uint32_t RESERVED11[1U];
-    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-    uint32_t RESERVED12[1U];
-    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-    uint32_t RESERVED13[1U];
-    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-    uint32_t RESERVED14[1U];
-    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-    uint32_t RESERVED15[1U];
-    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-    uint32_t RESERVED16[1U];
-    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-    uint32_t RESERVED17[1U];
-    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-    uint32_t RESERVED18[1U];
-    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-    uint32_t RESERVED19[1U];
-    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-    uint32_t RESERVED20[1U];
-    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-    uint32_t RESERVED21[1U];
-    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-    uint32_t RESERVED22[1U];
-    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-    uint32_t RESERVED23[1U];
-    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-    uint32_t RESERVED24[1U];
-    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-    uint32_t RESERVED25[1U];
-    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-    uint32_t RESERVED26[1U];
-    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-    uint32_t RESERVED27[1U];
-    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-    uint32_t RESERVED28[1U];
-    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-    uint32_t RESERVED29[1U];
-    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-    uint32_t RESERVED30[1U];
-    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-    uint32_t RESERVED31[1U];
-    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-    uint32_t RESERVED32[934U];
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-    uint32_t RESERVED33[1U];
-    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
-    __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
-    __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
-    __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
-    uint32_t RESERVED0[1];
-    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#else
-    uint32_t RESERVED0[3];
-#endif
-    __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
-    __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-#define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
-#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-#endif
-
-#define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
-#define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Set Priority Grouping (non-secure)
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB_NS->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping (non-secure)
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
-    return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    uint32_t mvfr0;
-
-    mvfr0 = FPU->MVFR0;
-    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
-        return 2U;           /* Double + Single precision FPU */
-    }
-    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
-        return 1U;           /* Single precision FPU */
-    }
-    else {
-        return 0U;           /* No FPU */
-    }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                         /* Reload value impossible */
-    }
-
-    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk   |
-                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h
deleted file mode 100644
index d06d984b7..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0.h
+++ /dev/null
@@ -1,850 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM0_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM0_REV
-#define __CM0_REV               0x0000U
-#warning "__CM0_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          2U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 1;              /*!< bit:      0  Reserved */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[31U];
-    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[31U];
-    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[31U];
-    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[31U];
-    uint32_t RESERVED4[64U];
-    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    uint32_t RESERVED0;
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    uint32_t RESERVED1;
-    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           Address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)0x0U;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)0x0U;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   SCB_AIRCR_SYSRESETREQ_Msk);
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h
deleted file mode 100644
index ebc43f3a1..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm0plus.h
+++ /dev/null
@@ -1,975 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0+ definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB  ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
-                                      __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM0PLUS_REV
-#define __CM0PLUS_REV             0x0000U
-#warning "__CM0PLUS_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __VTOR_PRESENT
-#define __VTOR_PRESENT            0U
-#warning "__VTOR_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          2U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[31U];
-    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[31U];
-    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[31U];
-    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[31U];
-    uint32_t RESERVED4[64U];
-    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-    uint32_t RESERVED0;
-#endif
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    uint32_t RESERVED1;
-    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0+ header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0+ */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0+ */
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   SCB_AIRCR_SYSRESETREQ_Msk);
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h
deleted file mode 100644
index 513635a58..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm23.h
+++ /dev/null
@@ -1,1813 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm23.h
- * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM23_H_GENERIC
-#define __CORE_CM23_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M23
-  @{
- */
-
-/*  CMSIS cmGrebe definitions */
-#define __CM23_CMSIS_VERSION_MAIN  ( 5U)                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM23_CMSIS_VERSION_SUB   ( 0U)                                       /*!< [15:0]  CMSIS HAL sub version */
-#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM23_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                     (23U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM23_H_DEPENDANT
-#define __CORE_CM23_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM23_REV
-#define __CM23_REV                0x0000U
-#warning "__CM23_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __SAUREGION_PRESENT
-#define __SAUREGION_PRESENT       0U
-#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __VTOR_PRESENT
-#define __VTOR_PRESENT            0U
-#warning "__VTOR_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          2U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-
-#ifndef __ETM_PRESENT
-#define __ETM_PRESENT             0U
-#warning "__ETM_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MTB_PRESENT
-#define __MTB_PRESENT             0U
-#warning "__MTB_PRESENT not defined in device header file; using default!"
-#endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M23 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[16U];
-    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[16U];
-    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[16U];
-    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[16U];
-    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[16U];
-    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-    uint32_t RESERVED5[16U];
-    __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-    uint32_t RESERVED0;
-#endif
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    uint32_t RESERVED1;
-    __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    uint32_t RESERVED0[6U];
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    uint32_t RESERVED3[1U];
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    uint32_t RESERVED5[1U];
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED6[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    uint32_t RESERVED7[1U];
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-    uint32_t RESERVED9[1U];
-    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-    uint32_t RESERVED10[1U];
-    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-    uint32_t RESERVED11[1U];
-    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-    uint32_t RESERVED12[1U];
-    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-    uint32_t RESERVED13[1U];
-    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-    uint32_t RESERVED14[1U];
-    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-    uint32_t RESERVED15[1U];
-    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-    uint32_t RESERVED16[1U];
-    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-    uint32_t RESERVED17[1U];
-    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-    uint32_t RESERVED18[1U];
-    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-    uint32_t RESERVED19[1U];
-    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-    uint32_t RESERVED20[1U];
-    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-    uint32_t RESERVED21[1U];
-    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-    uint32_t RESERVED22[1U];
-    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-    uint32_t RESERVED23[1U];
-    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-    uint32_t RESERVED24[1U];
-    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-    uint32_t RESERVED25[1U];
-    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-    uint32_t RESERVED26[1U];
-    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-    uint32_t RESERVED27[1U];
-    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-    uint32_t RESERVED28[1U];
-    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-    uint32_t RESERVED29[1U];
-    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-    uint32_t RESERVED30[1U];
-    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-    uint32_t RESERVED31[1U];
-    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-    uint32_t RESERVED0[7U];
-    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-#endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                     (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-#else
-    uint32_t* vectors = (uint32_t*)0x0U;
-#endif
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   SCB_AIRCR_SYSRESETREQ_Msk);
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                         /* Reload value impossible */
-    }
-
-    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk   |
-                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h
deleted file mode 100644
index 8cbf329b8..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm3.h
+++ /dev/null
@@ -1,1880 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M3
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM3_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM3_REV
-#define __CM3_REV               0x0200U
-#warning "__CM3_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
-        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
-        uint32_t _reserved1: 8;              /*!< bit: 16..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
-        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[24U];
-    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[24U];
-    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[24U];
-    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[24U];
-    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[56U];
-    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED5[644U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    uint32_t RESERVED0[5U];
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-#else
-    uint32_t RESERVED1[1U];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[6U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-#endif
-#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-#endif
-#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h
deleted file mode 100644
index 00de7795e..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm33.h
+++ /dev/null
@@ -1,2821 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm33.h
- * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version  V5.0.2
- * @date     07. December 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM33_H_GENERIC
-#define __CORE_CM33_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M33
-  @{
- */
-
-/*  CMSIS CM33 definitions */
-#define __CM33_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM33_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM33_CMSIS_VERSION_SUB           )     /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM33_H_DEPENDANT
-#define __CORE_CM33_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM33_REV
-#define __CM33_REV                0x0000U
-#warning "__CM33_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __SAUREGION_PRESENT
-#define __SAUREGION_PRESENT       0U
-#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __DSP_PRESENT
-#define __DSP_PRESENT             0U
-#warning "__DSP_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M33 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0) */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack-pointer select */
-        uint32_t FPCA: 1;                    /*!< bit:      2  Floating-point context active */
-        uint32_t SFPA: 1;                    /*!< bit:      3  Secure floating-point active */
-        uint32_t _reserved1: 28;             /*!< bit:  4..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[16U];
-    __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[16U];
-    __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[16U];
-    __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[16U];
-    __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[16U];
-    __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-    uint32_t RESERVED5[16U];
-    __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED6[580U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-    __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-    uint32_t RESERVED3[92U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-    uint32_t RESERVED4[15U];
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
-    uint32_t RESERVED5[1U];
-    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-    uint32_t RESERVED6[1U];
-    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-    uint32_t RESERVED7[6U];
-    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-    __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[1U];
-    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
-    uint32_t RESERVED6[4U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    uint32_t RESERVED3[1U];
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    uint32_t RESERVED5[1U];
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED6[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    uint32_t RESERVED7[1U];
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-    uint32_t RESERVED9[1U];
-    __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-    uint32_t RESERVED10[1U];
-    __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-    uint32_t RESERVED11[1U];
-    __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-    uint32_t RESERVED12[1U];
-    __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-    uint32_t RESERVED13[1U];
-    __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-    uint32_t RESERVED14[1U];
-    __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-    uint32_t RESERVED15[1U];
-    __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-    uint32_t RESERVED16[1U];
-    __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-    uint32_t RESERVED17[1U];
-    __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-    uint32_t RESERVED18[1U];
-    __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-    uint32_t RESERVED19[1U];
-    __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-    uint32_t RESERVED20[1U];
-    __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-    uint32_t RESERVED21[1U];
-    __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-    uint32_t RESERVED22[1U];
-    __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-    uint32_t RESERVED23[1U];
-    __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-    uint32_t RESERVED24[1U];
-    __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-    uint32_t RESERVED25[1U];
-    __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-    uint32_t RESERVED26[1U];
-    __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-    uint32_t RESERVED27[1U];
-    __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-    uint32_t RESERVED28[1U];
-    __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-    uint32_t RESERVED29[1U];
-    __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-    uint32_t RESERVED30[1U];
-    __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-    uint32_t RESERVED31[1U];
-    __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-    uint32_t RESERVED32[934U];
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-    uint32_t RESERVED33[1U];
-    __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
-    __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
-    __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
-    __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
-    uint32_t RESERVED0[1];
-    __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-    __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-    __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#else
-    uint32_t RESERVED0[3];
-#endif
-    __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
-    __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-    uint32_t RESERVED4[1U];
-    __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-    __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-#endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-#define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-#define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-#define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-#define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-#define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-#define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-#define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
-#define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-#define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-#define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-#define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-#define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-#endif
-
-#define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
-#define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
-        return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Set Priority Grouping (non-secure)
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB_NS->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping (non-secure)
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
-    return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    uint32_t mvfr0;
-
-    mvfr0 = FPU->MVFR0;
-    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
-        return 2U;           /* Double + Single precision FPU */
-    }
-    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
-        return 1U;           /* Single precision FPU */
-    }
-    else {
-        return 0U;           /* No FPU */
-    }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                         /* Reload value impossible */
-    }
-
-    SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-    TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-    SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                        SysTick_CTRL_TICKINT_Msk   |
-                        SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h
deleted file mode 100644
index f4c8011f8..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm4.h
+++ /dev/null
@@ -1,2061 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     30. January 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM4_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM4_REV
-#define __CM4_REV               0x0000U
-#warning "__CM4_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
-        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
-        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag */
-        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[24U];
-    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[24U];
-    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[24U];
-    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[24U];
-    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[56U];
-    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED5[644U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    uint32_t RESERVED0[5U];
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[6U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-#endif
-#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-#endif
-#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void __NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    uint32_t mvfr0;
-
-    mvfr0 = FPU->MVFR0;
-    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
-        return 1U;           /* Single precision FPU */
-    }
-    else {
-        return 0U;           /* No FPU */
-    }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h
deleted file mode 100644
index c09acc824..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_cm7.h
+++ /dev/null
@@ -1,2592 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm7.h
- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M7
-  @{
- */
-
-/*  CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS HAL main version */
-#define __CM7_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS HAL sub version */
-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM7_CMSIS_VERSION_SUB           )      /*!< CMSIS HAL version number */
-
-#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-#define __FPU_USED       1U
-#else
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#define __FPU_USED       0U
-#endif
-#else
-#define __FPU_USED         0U
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __CM7_REV
-#define __CM7_REV               0x0000U
-#warning "__CM7_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT             0U
-#warning "__FPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __ICACHE_PRESENT
-#define __ICACHE_PRESENT          0U
-#warning "__ICACHE_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __DCACHE_PRESENT
-#define __DCACHE_PRESENT          0U
-#warning "__DCACHE_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __DTCM_PRESENT
-#define __DTCM_PRESENT            0U
-#warning "__DTCM_PRESENT        not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
-        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
-        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags */
-        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
-        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag */
-        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[24U];
-    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[24U];
-    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[24U];
-    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[24U];
-    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[56U];
-    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED5[644U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-    __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-    __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-    __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-    uint32_t RESERVED3[93U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-    uint32_t RESERVED4[15U];
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-    __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1 */
-    uint32_t RESERVED5[1U];
-    __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-    uint32_t RESERVED6[1U];
-    __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-    __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-    __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-    __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-    __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-    __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-    __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-    __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-    uint32_t RESERVED7[6U];
-    __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-    __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-    __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-    __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-    __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-    uint32_t RESERVED8[1U];
-    __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[6U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-    uint32_t RESERVED3[981U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-    __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-    __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-    __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-    __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-    __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 Definitions */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    uint32_t mvfr0;
-
-    mvfr0 = SCB->MVFR0;
-    if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) {
-        return 2U;           /* Double + Single precision FPU */
-    }
-    else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
-        return 1U;           /* Single precision FPU */
-    }
-    else {
-        return 0U;           /* No FPU */
-    }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################  Cache functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_CacheFunctions Cache Functions
-  \brief    Functions that configure Instruction and Data cache.
-  @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
-
-
-/**
-  \brief   Enable I-Cache
-  \details Turns on I-Cache
-  */
-__STATIC_INLINE void SCB_EnableICache (void)
-{
-#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
-    __DSB();
-    __ISB();
-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Disable I-Cache
-  \details Turns off I-Cache
-  */
-__STATIC_INLINE void SCB_DisableICache (void)
-{
-#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Invalidate I-Cache
-  \details Invalidates I-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateICache (void)
-{
-#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Enable D-Cache
-  \details Turns on D-Cache
-  */
-__STATIC_INLINE void SCB_EnableDCache (void)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    /* invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-        do {
-            SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
-                          ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
-#if defined ( __CC_ARM )
-            __schedule_barrier();
-#endif
-        } while (ways-- != 0U);
-    } while(sets-- != 0U);
-    __DSB();
-
-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Disable D-Cache
-  \details Turns off D-Cache
-  */
-__STATIC_INLINE void SCB_DisableDCache (void)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    register uint32_t ccsidr;
-    register uint32_t sets;
-    register uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    /* clean & invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-        do {
-            SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
-                           ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
-#if defined ( __CC_ARM )
-            __schedule_barrier();
-#endif
-        } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Invalidate D-Cache
-  \details Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    /* invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-        do {
-            SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
-                          ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
-#if defined ( __CC_ARM )
-            __schedule_barrier();
-#endif
-        } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Clean D-Cache
-  \details Cleans D-Cache
-  */
-__STATIC_INLINE void SCB_CleanDCache (void)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    /* clean D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-        do {
-            SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
-                          ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
-#if defined ( __CC_ARM )
-            __schedule_barrier();
-#endif
-        } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   Clean & Invalidate D-Cache
-  \details Cleans and Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-    /* clean & invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-        ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-        do {
-            SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
-                           ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
-#if defined ( __CC_ARM )
-            __schedule_barrier();
-#endif
-        } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   D-Cache Invalidate by address
-  \details Invalidates D-Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t)addr;
-    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-        SCB->DCIMVAC = op_addr;
-        op_addr += (uint32_t)linesize;
-        op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   D-Cache Clean by address
-  \details Cleans D-Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t* addr, int32_t dsize)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-        SCB->DCCMVAC = op_addr;
-        op_addr += (uint32_t)linesize;
-        op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/**
-  \brief   D-Cache Clean and Invalidate by address
-  \details Cleans and invalidates D_Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t* addr, int32_t dsize)
-{
-#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-    int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-        SCB->DCCIMVAC = op_addr;
-        op_addr += (uint32_t)linesize;
-        op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-#endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h
deleted file mode 100644
index ed1063364..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc000.h
+++ /dev/null
@@ -1,976 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc000.h
- * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup SC000
-  @{
- */
-
-/*  CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
-                                     __SC000_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __SC000_REV
-#define __SC000_REV             0x0000U
-#warning "__SC000_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          2U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 28;             /*!< bit:  0..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0) */
-        uint32_t _reserved1: 3;              /*!< bit: 25..27  Reserved */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 1;              /*!< bit:      0  Reserved */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[31U];
-    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[31U];
-    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[31U];
-    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[31U];
-    uint32_t RESERVED4[64U];
-    __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    uint32_t RESERVED1[154U];
-    __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the SC000 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-    else {
-        SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-                                    (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   SCB_AIRCR_SYSRESETREQ_Msk);
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h
deleted file mode 100644
index a1b17e1ce..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/core_sc300.h
+++ /dev/null
@@ -1,1851 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc300.h
- * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
- * @version  V5.0.1
- * @date     25. November 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-#pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup SC3000
-  @{
- */
-
-/*  CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
-                                     __SC300_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-#if defined __TARGET_FPU_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-#if defined __ARM_PCS_VFP
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __GNUC__ )
-#if defined (__VFP_FP__) && !defined(__SOFTFP__)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __ICCARM__ )
-#if defined __ARMVFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TI_ARM__ )
-#if defined __TI_VFP_SUPPORT__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __TASKING__ )
-#if defined __FPU_VFP__
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#elif defined ( __CSMC__ )
-#if ( __CSMC__ & 0x400U)
-#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-#endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC300_H_DEPENDANT
-#define __CORE_SC300_H_DEPENDANT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-#ifndef __SC300_REV
-#define __SC300_REV               0x0000U
-#warning "__SC300_REV not defined in device header file; using default!"
-#endif
-
-#ifndef __MPU_PRESENT
-#define __MPU_PRESENT             0U
-#warning "__MPU_PRESENT not defined in device header file; using default!"
-#endif
-
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS          3U
-#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#ifndef __Vendor_SysTickConfig
-#define __Vendor_SysTickConfig    0U
-#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-#endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-#define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-#define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC300 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union {
-    struct {
-        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union {
-    struct {
-        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number */
-        uint32_t _reserved0: 1;              /*!< bit:      9  Reserved */
-        uint32_t ICI_IT_1: 6;                /*!< bit: 10..15  ICI/IT part 1 */
-        uint32_t _reserved1: 8;              /*!< bit: 16..23  Reserved */
-        uint32_t T: 1;                       /*!< bit:     24  Thumb bit */
-        uint32_t ICI_IT_2: 2;                /*!< bit: 25..26  ICI/IT part 2 */
-        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag */
-        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag */
-        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag */
-        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag */
-        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union {
-    struct {
-        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
-        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used */
-        uint32_t _reserved1: 30;             /*!< bit:  2..31  Reserved */
-    } b;                                   /*!< Structure used for bit  access */
-    uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct {
-    __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-    uint32_t RESERVED0[24U];
-    __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-    uint32_t RSERVED1[24U];
-    __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-    uint32_t RESERVED2[24U];
-    __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-    uint32_t RESERVED3[24U];
-    __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-    uint32_t RESERVED4[56U];
-    __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-    uint32_t RESERVED5[644U];
-    __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct {
-    __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-    __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-    __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-    __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-    __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-    __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-    __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-    __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-    __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-    __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-    __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-    __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-    __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-    __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-    __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-    __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-    __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-    __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-    __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-    uint32_t RESERVED0[5U];
-    __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-    uint32_t RESERVED1[129U];
-    __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct {
-    uint32_t RESERVED0[1U];
-    __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-    uint32_t RESERVED1[1U];
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct {
-    __OM  union {
-        __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-        __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-        __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-    }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-    uint32_t RESERVED0[864U];
-    __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-    uint32_t RESERVED1[15U];
-    __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-    uint32_t RESERVED2[15U];
-    __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-    uint32_t RESERVED3[29U];
-    __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-    __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-    __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-    uint32_t RESERVED4[43U];
-    __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-    __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-    uint32_t RESERVED5[6U];
-    __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-    __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-    __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-    __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-    __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-    __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-    __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-    __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-    __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-    __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-    __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-    __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-    __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-    __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-    __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-    __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-    __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-    __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-    __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-    __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-    __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-    __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-    uint32_t RESERVED0[1U];
-    __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-    __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-    __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-    uint32_t RESERVED1[1U];
-    __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-    __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-    __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-    uint32_t RESERVED2[1U];
-    __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-    __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-    __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct {
-    __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-    __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-    uint32_t RESERVED0[2U];
-    __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-    uint32_t RESERVED1[55U];
-    __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-    uint32_t RESERVED2[131U];
-    __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-    __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-    __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-    uint32_t RESERVED3[759U];
-    __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-    __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-    __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-    uint32_t RESERVED4[1U];
-    __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-    __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-    __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-    uint32_t RESERVED5[39U];
-    __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-    __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-    uint32_t RESERVED7[8U];
-    __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-    __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct {
-    __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-    __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-    __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-    __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-    __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-    __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-    __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-    __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct {
-    __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-    __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-    __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-    __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifndef CMSIS_NVIC_VIRTUAL
-#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-#define NVIC_EnableIRQ              __NVIC_EnableIRQ
-#define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-#define NVIC_DisableIRQ             __NVIC_DisableIRQ
-#define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-#define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-#define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-#define NVIC_GetActive              __NVIC_GetActive
-#define NVIC_SetPriority            __NVIC_SetPriority
-#define NVIC_GetPriority            __NVIC_GetPriority
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifndef CMSIS_VECTAB_VIRTUAL
-#define NVIC_SetVector              __NVIC_SetVector
-#define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-    uint32_t reg_value;
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-    reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-    reg_value  =  (reg_value                                   |
-                   ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                   (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-    SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-    return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-        __DSB();
-        __ISB();
-    }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-    }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-    }
-    else {
-        return(0U);
-    }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    if ((int32_t)(IRQn) >= 0) {
-        NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-    else {
-        SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-    }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-    if ((int32_t)(IRQn) >= 0) {
-        return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-    }
-    else {
-        return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
-    }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    return (
-               ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-               ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-           );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-    uint32_t PreemptPriorityBits;
-    uint32_t SubPriorityBits;
-
-    PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-    SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-    *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-    *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-    uint32_t* vectors = (uint32_t*)SCB->VTOR;
-    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-    __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-    SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                             (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-    __DSB();                                                          /* Ensure completion of memory access */
-
-    for(;;) {                                                         /* wait until reset */
-        __NOP();
-    }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-    if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
-        return (1UL);                                                   /* Reload value impossible */
-    }
-
-    SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-    NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-    SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                     SysTick_CTRL_TICKINT_Msk   |
-                     SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-    return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-            ((ITM->TER & 1UL               ) != 0UL)   ) {   /* ITM Port #0 enabled */
-        while (ITM->PORT[0U].u32 == 0UL) {
-            __NOP();
-        }
-        ITM->PORT[0U].u8 = (uint8_t)ch;
-    }
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-    int32_t ch = -1;                           /* no character available */
-
-    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-        ch = ITM_RxBuffer;
-        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-    }
-
-    return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-        return (0);                              /* no character available */
-    }
-    else {
-        return (1);                              /*    character available */
-    }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h b/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h
deleted file mode 100644
index cd6d8ab07..000000000
--- a/hw/mcu/mm32/mm32f327x/CMSIS/KEIL_Core/tz_context.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * ----------------------------------------------------------------------------
- *
- * $Date:        21. September 2016
- * $Revision:    V1.0
- *
- * Project:      TrustZone for ARMv8-M
- * Title:        Context Management for ARMv8-M TrustZone
- *
- * Version 1.0
- *    Initial Release
- *---------------------------------------------------------------------------*/
-
-#ifndef TZ_CONTEXT_H
-#define TZ_CONTEXT_H
-
-#include <stdint.h>
-
-#ifndef TZ_MODULEID_T
-#define TZ_MODULEID_T
-/// \details Data type that identifies secure software modules called by a process.
-typedef uint32_t TZ_ModuleId_t;
-#endif
-
-/// \details TZ Memory ID identifies an allocated memory slot.
-typedef uint32_t TZ_MemoryId_t;
-
-/// Initialize secure context memory system
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_InitContextSystem_S (void);
-
-/// Allocate context memory for calling secure software modules in TrustZone
-/// \param[in]  module   identifies software modules called from non-secure mode
-/// \return value != 0 id TrustZone memory slot identifier
-/// \return value 0    no memory available or internal error
-TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
-
-/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
-
-/// Load secure context (called on RTOS thread context switch)
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
-
-/// Store secure context (called on RTOS thread context switch)
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
-
-#endif  // TZ_CONTEXT_H
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h
deleted file mode 100644
index c77078936..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/dtype.h
+++ /dev/null
@@ -1,33 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file:   dtype.h
-/// @author  AE TEAM
-/// @brief   Define the data types to be used in the project, including the function
-///          library and application code. Use the data types defined in this file.
-////////////////////////////////////////////////////////////////////////////////
-#ifndef __DTYPE_H
-#define __DTYPE_H     //This is done to avoid including the header file repeatedly in the same file
-
-
-//Defines the read and write characteristics of data, which is often used for storage limits of peripheral registers
-#ifndef __I
-#define     __I     volatile const    //only read
-#endif
-#ifndef __O
-#define     __O     volatile          //only write
-#endif
-#ifndef __IO
-#define     __IO    volatile          //read write
-#endif
-
-//Common data type definitions
-
-typedef unsigned char  int8u;         //haven't symbol8 bit integer variable
-typedef signed   char  int8s;         //have symbol8 bit integer variable
-typedef unsigned short int16u;        //haven't symbol16 bit integer variable
-typedef signed   short int16s;        //have symbol16 bit integer variable
-typedef unsigned int   int32u;        //haven't symbol32 bit integer variable
-typedef signed   int   int32s;        //have symbol32 bit integer variable
-typedef float          fp32;          //Single-precision floating-point number (32-bit length)
-typedef double         fp64;          //Double-precision floating-point number (64-bit length)
-
-#endif  //__DTYPE_H
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h
deleted file mode 100644
index dc0aa3d67..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_adc.h
+++ /dev/null
@@ -1,341 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_adc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE ADC
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_ADC_H
-#define __HAL_ADC_H
-
-// Files includes
-#include "types.h"
-#include "reg_adc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup ADC_HAL
-/// @brief ADC HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup ADC_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Channels
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_Channel_0                       = 0x00,                   ///< ADC Channel 0
-    ADC_Channel_1                       = 0x01,                   ///< ADC Channel 1
-    ADC_Channel_2                       = 0x02,                   ///< ADC Channel 2
-    ADC_Channel_3                       = 0x03,                   ///< ADC Channel 3
-    ADC_Channel_4                       = 0x04,                   ///< ADC Channel 4
-    ADC_Channel_5                       = 0x05,                   ///< ADC Channel 5
-    ADC_Channel_6                       = 0x06,                   ///< ADC Channel 6
-    ADC_Channel_7                       = 0x07,                   ///< ADC Channel 7
-
-    ADC_Channel_8               = 0x08,     ///< ADC Channel 8
-    ADC_Channel_9               = 0x09,     ///< ADC Channel 9
-    ADC_Channel_10              = 0x0A,     ///< ADC Channel 10
-    ADC_Channel_11              = 0x0B,     ///< ADC Channel 11
-    ADC_Channel_12              = 0x0C,     ///< ADC Channel 12
-    ADC_Channel_13              = 0x0D,     ///< ADC Channel 13
-    ADC_Channel_14              = 0x0E,     ///< ADC Channel 14
-    ADC_Channel_15              = 0x0F,     ///< ADC Channel 15
-    ADC_Channel_TempSensor      = 0x0E,     ///< Temperature sensor channel(ADC1)
-    ADC_Channel_VoltReference   = 0x0F,     ///< Internal reference voltage channel(ADC1)
-    ADC_Channel_Vrefint         = 0x0F,     ///< Internal reference voltage channel(ADC1)
-
-} ADCCHANNEL_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Sampling_Times
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_Samctl_1_5   = ADC_SMPR1_SAMCTL0_2_5,   ///< ADC sample time select 1.5t
-    ADC_Samctl_2_5   = ADC_SMPR1_SAMCTL0_2_5,   ///< ADC sample time select 2.5t
-    ADC_Samctl_3_5   = ADC_SMPR1_SAMCTL0_3_5,   ///< ADC sample time select 3.5t
-    ADC_Samctl_4_5   = ADC_SMPR1_SAMCTL0_4_5,   ///< ADC sample time select 4.5t
-    ADC_Samctl_5_5   = ADC_SMPR1_SAMCTL0_5_5,   ///< ADC sample time select 5.5t
-    ADC_Samctl_6_5   = ADC_SMPR1_SAMCTL0_6_5,   ///< ADC sample time select 6.5t
-    ADC_Samctl_7_5   = ADC_SMPR1_SAMCTL0_7_5,   ///< ADC sample time select 7.5t
-    ADC_Samctl_8_5   = ADC_SMPR1_SAMCTL0_8_5,   ///< ADC sample time select 7.5t
-    ADC_Samctl_13_5  = ADC_SMPR1_SAMCTL0_14_5,  ///< ADC sample time select 13.5t
-    ADC_Samctl_14_5  = ADC_SMPR1_SAMCTL0_14_5,  ///< ADC sample time select 14.5t
-    ADC_Samctl_28_5  = ADC_SMPR1_SAMCTL0_29_5,  ///< ADC sample time select 28.5t
-    ADC_Samctl_29_5  = ADC_SMPR1_SAMCTL0_29_5,  ///< ADC sample time select 29.5t
-    ADC_Samctl_41_5  = ADC_SMPR1_SAMCTL0_42_5,  ///< ADC sample time select 41.5t
-    ADC_Samctl_42_5  = ADC_SMPR1_SAMCTL0_42_5,  ///< ADC sample time select 42.5t
-    ADC_Samctl_55_5  = ADC_SMPR1_SAMCTL0_56_5,  ///< ADC sample time select 55.5t
-    ADC_Samctl_56_5  = ADC_SMPR1_SAMCTL0_56_5,  ///< ADC sample time select 56.5t
-    ADC_Samctl_71_5  = ADC_SMPR1_SAMCTL0_72_5,  ///< ADC sample time select 71.5t
-    ADC_Samctl_72_5  = ADC_SMPR1_SAMCTL0_72_5,  ///< ADC sample time select 72.5t
-    ADC_Samctl_239_5 = ADC_SMPR1_SAMCTL0_240_5, ///< ADC sample time select 239.5t
-    ADC_Samctl_240_5 = ADC_SMPR1_SAMCTL0_240_5  ///< ADC sample time select 240.5t
-} ADCSAM_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Resolution
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_Resolution_12b = ADC_CFGR_RSLTCTL_12,  ///< ADC resolution select 12bit
-    ADC_Resolution_11b = ADC_CFGR_RSLTCTL_11,  ///< ADC resolution select 11bit
-    ADC_Resolution_10b = ADC_CFGR_RSLTCTL_10,  ///< ADC resolution select 10bit
-    ADC_Resolution_9b  = ADC_CFGR_RSLTCTL_9,   ///< ADC resolution select 9bit
-    ADC_Resolution_8b  = ADC_CFGR_RSLTCTL_8    ///< ADC resolution select 8bit
-} ADCRSL_TypeDef;
-/// @brief ADC_Prescare
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_PCLK2_PRESCARE_3  = ADC_CFGR_PRE_3,   ///< ADC preclk 3
-    ADC_PCLK2_PRESCARE_5  = ADC_CFGR_PRE_5,   ///< ADC preclk 5
-    ADC_PCLK2_PRESCARE_7  = ADC_CFGR_PRE_7,   ///< ADC preclk 7
-    ADC_PCLK2_PRESCARE_9  = ADC_CFGR_PRE_9,   ///< ADC preclk 9
-    ADC_PCLK2_PRESCARE_11 = ADC_CFGR_PRE_11,  ///< ADC preclk 11
-    ADC_PCLK2_PRESCARE_13 = ADC_CFGR_PRE_13,  ///< ADC preclk 13
-    ADC_PCLK2_PRESCARE_15 = ADC_CFGR_PRE_15,  ///< ADC preclk 15
-    ADC_PCLK2_PRESCARE_17 = ADC_CFGR_PRE_17,  ///< ADC preclk 17
-
-    ADC_PCLK2_PRESCARE_2  = ADC_CFGR_PRE_2,   ///< ADC preclk 2
-    ADC_PCLK2_PRESCARE_4  = ADC_CFGR_PRE_4,   ///< ADC preclk 4
-    ADC_PCLK2_PRESCARE_6  = ADC_CFGR_PRE_6,   ///< ADC preclk 6
-    ADC_PCLK2_PRESCARE_8  = ADC_CFGR_PRE_8,   ///< ADC preclk 8
-    ADC_PCLK2_PRESCARE_10 = ADC_CFGR_PRE_10,  ///< ADC preclk 10
-    ADC_PCLK2_PRESCARE_12 = ADC_CFGR_PRE_12,  ///< ADC preclk 12
-    ADC_PCLK2_PRESCARE_14 = ADC_CFGR_PRE_14,  ///< ADC preclk 14
-    ADC_PCLK2_PRESCARE_16 = ADC_CFGR_PRE_16   ///< ADC preclk 16
-} ADCPRE_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Conversion_Mode
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_Mode_Imm        = ADC_CR_IMM,       ///< ADC single convert mode
-    ADC_Mode_Scan       = ADC_CR_SCAN,      ///< ADC single period convert mode
-    ADC_Mode_Continue   = ADC_CR_CONTINUE   ///< ADC continue scan convert mode
-} ADCMODE_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC1_ExternalTrigConv_T1_CC1        = ADC_CR_T1_CC1,
-    ADC1_ExternalTrigConv_T1_CC2        = ADC_CR_T1_CC2,
-    ADC1_ExternalTrigConv_T1_CC3        = ADC_CR_T1_CC3,
-    ADC1_ExternalTrigConv_T2_CC2        = ADC_CR_T2_CC2,
-    ADC1_ExternalTrigConv_T3_TRIG       = ADC_CR_T3_TRIG,
-    ADC1_ExternalTrigConv_T3_CC1        = ADC_CR_T3_CC1,
-    ADC1_ExternalTrigConv_EXTI_11       = ADC_CR_EXTI_11,
-    ADC1_ExternalTrigConv_T1_CC4_CC5    = ADC_CR_T1_CC4_CC5,
-    ADC1_ExternalTrigConv_T1_TRIG       = ADC_CR_T1_TRIG,
-    ADC1_ExternalTrigConv_T8_CC4        = ADC_CR_T8_CC4,
-    ADC1_ExternalTrigConv_T8_CC4_CC5    = ADC_CR_T8_CC4_CC5,
-    ADC1_ExternalTrigConv_T2_CC1        = ADC_CR_T2_CC1,
-    ADC1_ExternalTrigConv_T3_CC4        = ADC_CR_T3_CC4,
-    ADC1_ExternalTrigConv_T2_TRIG       = ADC_CR_T2_TRIG,
-    ADC1_ExternalTrigConv_T8_CC5        = ADC_CR_T8_CC5,
-    ADC1_ExternalTrigConv_EXTI_15       = ADC_CR_EXTI_15,
-    ADC1_ExternalTrigConv_T1_CC4        = ADC_CR_TIM1_CC4,
-    ADC1_ExternalTrigConv_T1_CC5        = ADC_CR_TIM1_CC5
-} EXTERTRIG_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Data_Align
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_DataAlign_Right = ADC_CR_RIGHT,     ///< ADC data left align
-    ADC_DataAlign_Left  = ADC_CR_LEFT       ///< ADC data right align
-} ADCDATAALI_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Flags_Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_IT_EOC = 1,                            ///< ADC conversion flag
-    ADC_FLAG_EOC = 1,
-    ADC_IT_AWD = 2,                            ///< ADC window comparator flag
-    ADC_FLAG_AWD = 2
-} ADCFLAG_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Trig_Edge
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_ADC_Trig_Edge_Dual              = ADC_CR_TRG_EDGE_DUAL,                 ///< ADC trig edge dual mode down and up
-    ADC_ADC_Trig_Edge_Down              = ADC_CR_TRG_EDGE_DOWN,                 ///< ADC trig edge single mode down
-    ADC_ADC_Trig_Edge_Up                = ADC_CR_TRG_EDGE_UP,                   ///< ADC trig edge single mode up
-    ADC_ADC_Trig_Edge_Mask              = ADC_CR_TRG_EDGE_MASK                  ///< ADC trig edge is mask, not allowed
-} ADCTRIGEDGE_TypeDef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Scan_Direct
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_Scan_Direct_Up                  = ADC_CR_SCANDIR,                       ///< ADC scan from low channel to high channel
-    ADC_Scan_Direct_Down                = 0                                     ///< ADC scan from High channel to low channel
-} ADCSCANDIRECT_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Trig_Shift
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_ADC_Trig_Shift_0                = ADC_CR_TRGSHIFT_0,                    ///< ADC trig shift bit is 0
-    ADC_ADC_Trig_Shift_4                = ADC_CR_TRGSHIFT_4,                    ///< ADC trig shift bit is 4
-    ADC_ADC_Trig_Shift_16               = ADC_CR_TRGSHIFT_16,                   ///< ADC trig shift bit is 16
-    ADC_ADC_Trig_Shift_32               = ADC_CR_TRGSHIFT_32,                   ///< ADC trig shift bit is 32
-    ADC_ADC_Trig_Shift_64               = ADC_CR_TRGSHIFT_64,                   ///< ADC trig shift bit is 64
-    ADC_ADC_Trig_Shift_128              = ADC_CR_TRGSHIFT_128,                  ///< ADC trig shift bit is 128
-    ADC_ADC_Trig_Shift_256              = ADC_CR_TRGSHIFT_256,                  ///< ADC trig shift bit is 256
-    ADC_ADC_Trig_Shift_512              = ADC_CR_TRGSHIFT_512,                  ///< ADC trig shift bit is 512
-} ADCTRIGSHIFT_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_Inject_Seqen_Len1               = 0,                                    ///< ADC Injected Seqence length is 1
-    ADC_Inject_Seqen_Len2               = 1,                                    ///< ADC Injected Seqence length is 2
-    ADC_Inject_Seqen_Len3               = 2,                                    ///< ADC Injected Seqence length is 3
-    ADC_Inject_Seqen_Len4               = 3,                                    ///< ADC Injected Seqence length is 4
-} ADC_INJ_SEQ_LEN_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Inject_Sequence_Length the sequencer length for injected channels
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC_InjectedChannel_1 = 0x00,
-    ADC_InjectedChannel_2 = 0x04,
-    ADC_InjectedChannel_3 = 0x08,
-    ADC_InjectedChannel_4 = 0x0c,
-} ADC_INJ_SEQ_Channel_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_Extrenal_Trigger_Sources_For_Regular_Channels_Conversion
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    ADC1_InjectExtTrigSrc_T1_TRGO       = ADC_ANY_CR_JTRGSEL_TIM1_TRGO,         ///< TIM1 TRGO
-    ADC1_InjectExtTrigSrc_T1_CC4        = ADC_ANY_CR_JTRGSEL_TIM1_CC4,          ///< TIM1 CC4
-    ADC1_InjectExtTrigSrc_T1_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5,      ///< TIM1 CC4 and CC5
-    ADC1_InjectExtTrigSrc_T2_CC1        = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1,      ///< TIM2 CC1
-    ADC1_InjectExtTrigSrc_T3_CC4        = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4,      ///< TIM3 CC4
-    ADC1_InjectExtTrigSrc_T8_CC4        = ADC_ANY_CR_JTRGSEL_TIM8_CC4,          ///< TIM8 CC4
-    ADC1_InjectExtTrigSrc_T8_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5,      ///< TIM8 CC4 and CC5
-    ADC1_InjectExtTrigSrc_EXTI_12       = ADC_ANY_CR_JTRGSEL_EXTI12,            ///< EXTI12
-
-    ADC2_InjectExtTrigSrc_T1_TRGO       = ADC_ANY_CR_JTRGSEL_TIM1_TRGO,         ///< TIM1 TRGO
-    ADC2_InjectExtTrigSrc_T1_CC4        = ADC_ANY_CR_JTRGSEL_TIM1_CC4,          ///< TIM1 CC4
-    ADC2_InjectExtTrigSrc_T1_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5,      ///< TIM1 CC4 and CC5
-    ADC2_InjectExtTrigSrc_T2_CC1        = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1,      ///< TIM2 CC1
-    ADC2_InjectExtTrigSrc_T3_CC4        = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4,      ///< TIM3 CC4
-    ADC2_InjectExtTrigSrc_T8_CC4        = ADC_ANY_CR_JTRGSEL_TIM8_CC4,          ///< TIM8 CC4
-    ADC2_InjectExtTrigSrc_T8_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5,      ///< TIM8 CC4 and CC5
-
-    ADC2_InjectExtTrigSrc_EXTI_12       = ADC_ANY_CR_JTRGSEL_EXTI12,            ///< EXTI12
-    ADC3_InjectExtTrigSrc_T1_TRGO       = ADC_ANY_CR_JTRGSEL_TIM1_TRGO,         ///< TIM1 TRGO
-    ADC3_InjectExtTrigSrc_T1_CC4        = ADC_ANY_CR_JTRGSEL_TIM1_CC4,          ///< TIM1 CC4
-    ADC3_InjectExtTrigSrc_T1_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5,      ///< TIM1 CC4 and CC5
-    ADC3_InjectExtTrigSrc_T4_CC1        = ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1,      ///< TIM4 CC1
-    ADC3_InjectExtTrigSrc_T5_CC4        = ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4,      ///< TIM5 CC4
-    ADC3_InjectExtTrigSrc_T8_CC4        = ADC_ANY_CR_JTRGSEL_TIM8_CC4,          ///< TIM8 CC4
-    ADC3_InjectExtTrigSrc_T8_CC4_CC5    = ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5,      ///< TIM8 CC4 and CC5
-    ADC3_InjectExtTrigSrc_EXTI_12       = ADC_ANY_CR_JTRGSEL_EXTI12,            ///< EXTI12
-} EXTER_INJ_TRIG_TypeDef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC Init Structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u32                                 ADC_Resolution;                         ///< Convert data resolution
-    u32                                 ADC_PRESCARE;                           ///< Clock prescaler
-    u32                                 ADC_Mode;                               ///< ADC conversion mode
-    FunctionalState                     ADC_ContinuousConvMode;                 ///< Useless just for compatibility
-    u32                                 ADC_ExternalTrigConv;                   ///< External trigger source selection
-    u32                                 ADC_DataAlign;                          ///< Data alignmentn
-} ADC_InitTypeDef;
-
-/// @}
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup ADC_Exported_Variables
-/// @{
-#ifdef _HAL_ADC_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup ADC_Exported_Functions
-/// @{
-void ADC_DeInit(ADC_TypeDef* adc);
-void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct);
-void ADC_StructInit(ADC_InitTypeDef* init_struct);
-void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state);
-void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state);
-void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state);
-void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state);
-void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time);//ADCSAM_TypeDef
-void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state);
-void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source);
-#define ADC_ExternalTrigInjectedConvConfig ADC_ExternalTrigConvConfig
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel);
-void ADC_TempSensorVrefintCmd(FunctionalState state);
-void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt);
-void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag);
-
-u16 ADC_GetConversionValue(ADC_TypeDef* adc);
-
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag);
-ITStatus   ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt);
-void ADC_TempSensorCmd(FunctionalState state);
-void ADC_VrefintCmd(FunctionalState state);
-void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state);
-void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel);
-void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num);
-void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state);
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
-void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource);
-void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
-void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state);
-void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time);
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length);
-void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel);
-u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr);
-u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc);
-void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value);
-u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel);
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h
deleted file mode 100644
index 26a93d4a0..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_bkp.h
+++ /dev/null
@@ -1,130 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_bkp.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE BKP
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_BKP_H
-#define __HAL_BKP_H
-
-// Files includes
-#include "types.h"
-#include "reg_bkp.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup BKP_HAL
-/// @brief BKP HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup BKP_Exported_Types
-/// @{
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Data_Backup_Register
-/// @anchor Data_Backup_Register
-
-typedef enum {
-    BKP_DR1  = 0x0010,
-    BKP_DR2  = 0x0014,
-    BKP_DR3  = 0x0018,
-    BKP_DR4  = 0x001C,
-    BKP_DR5  = 0x0020,
-    BKP_DR6  = 0x0024,
-    BKP_DR7  = 0x0028,
-    BKP_DR8  = 0x002C,
-    BKP_DR9  = 0x0030,
-    BKP_DR10 = 0x0034,
-    BKP_DR11 = 0x0038,
-    BKP_DR12 = 0x003C,
-    BKP_DR13 = 0x0040,
-    BKP_DR14 = 0x0044,
-    BKP_DR15 = 0x0048,
-    BKP_DR16 = 0x004C,
-    BKP_DR17 = 0x0050,
-    BKP_DR18 = 0x0054,
-    BKP_DR19 = 0x0058,
-    BKP_DR20 = 0x005C
-} BKPDR_Typedef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Tamper_Pin_active_level
-/// @anchor Tamper_Pin_active_level
-typedef enum {
-    BKP_TamperPinLevel_High,                                                    ///< Tamper pin active on high level
-    BKP_TamperPinLevel_Low = BKP_CR_TPAL,                                       ///< Tamper pin active on low level
-} BKPTPAL_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_output_source_to_output_on_the_Tamper_pin
-/// @anchor RTC_output_source_to_output_on_the_Tamper_pin
-typedef enum {
-    BKP_RTCOutputSource_None       = 0x0000,                                    ///< No RTC output on the Tamper pin
-    BKP_RTCOutputSource_CalibClock = 0x0080,                                    ///< Output the RTC clock with frequency divided by 64 on the Tamper pin
-    BKP_RTCOutputSource_Alarm      = 0x0100,                                    ///< Output the RTC Alarm pulse signal on the Tamper pin
-    BKP_RTCOutputSource_Second     = 0x0300                                     ///< Output the RTC Second pulse signal on the Tamper pin
-} BKPRTCOUTPUTSRC_Typedef;
-
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup BKP_Exported_Variables
-/// @{
-#ifdef _HAL_BKP_C_
-#define GLOBAL
-
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup BKP_Exported_Functions
-/// @{
-
-void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data);
-u16  BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr);
-
-void BKP_DeInit(void);
-void BKP_ClearFlag(void);
-void BKP_ClearITPendingBit(void);
-void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level);
-void BKP_TamperPinCmd(FunctionalState state);
-void BKP_ITConfig(FunctionalState state);
-void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source);
-void BKP_SetRTCCalibrationValue(u8 calibration_value);
-
-ITStatus   BKP_GetITStatus(void);
-FlagStatus BKP_GetFlagStatus(void);
-void exBKP_Init(void);
-void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 data);
-u16  exBKP_ImmRead(BKPDR_Typedef bkp_dr);
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_BKP_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h
deleted file mode 100644
index b7e1d4b42..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_can.h
+++ /dev/null
@@ -1,340 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_can.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CAN
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_CAN_H
-#define __HAL_CAN_H
-
-// Files includes
-#include "types.h"
-#include "reg_can.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup CAN_HAL
-/// @brief CAN HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup CAN_Exported_Types
-/// @{
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_Initialization
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    CANINITFAILED = 0x00000000,  ///< CAN initialization failed
-    CANINITOK     = 0x00000001   ///< CAN initialization ok
-} emCAN_INIT_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_sleep_constants
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    CANSLEEPFAILED = 0x00000000,  ///< CAN did not enter the sleep mode
-    CANSLEEPOK     = 0x00000001   ///< CAN entered the sleep mode
-} emCAN_SLEEP_conts_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_wake_up_constants
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    CANWAKEUPFAILED = 0x00000000,  ///< CAN did not leave the sleep mode
-    CANWAKEUPOK     = 0x00000001   ///< CAN leaved the sleep mode
-} emCAN_WAKE_conts_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_Mode
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    CAN_BASICMode         = 0x00000000,
-    CAN_PELIMode          = 0x00000080,
-    CAN_WorkMode          = 0x00000080,
-    CAN_ResetMode         = 0x00000001,
-    CAN_ListenOnlyMode    = 0x00000002,
-    CAN_SeftTestMode      = 0x00000004,
-    CAN_FilterMode_Singal = 0x00000008,
-    CAN_FilterMode_Double = 0x000000f7,
-    CAN_SleepMode         = 0x00000010
-} emCAN_CAN_Mode_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief BASIC_CAN_interrupt
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    CAN_IT_RIE = CAN_CR_RIE,                                                    ///< Overflow interrupt enable
-    CAN_IT_TIE = CAN_CR_TIE,                                                    ///< Transmit interrupt enable
-    CAN_IT_EIE = CAN_CR_EIE,                                                    ///< Error interrupt enable
-    CAN_IT_OIE = CAN_CR_OIE                                                     ///< Receive interrupt enable
-} emCAN_BASIC_IntEn_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PELI_CAN_interrupt
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    CAN_IT_RI  = CAN_IR_RI,                                                     ///< Overflow interrupt enable
-    CAN_IT_TI  = CAN_IR_TI,                                                     ///< Transmit interrupt enable
-    CAN_IT_EI  = CAN_IR_EI,                                                     ///< Error interrupt enable
-    CAN_IT_DOI = CAN_IR_DOI,                                                    ///< Receive interrupt enable
-    CAN_IT_WUI = 0x00001010,                                                    ///< Receive interrupt enable
-    CAN_IT_EPI = CAN_IR_EPI,                                                    ///< Receive interrupt enable
-    CAN_IT_ALI = CAN_IR_ALI,                                                    ///< Receive interrupt enable
-    CAN_IT_BEI = CAN_IR_BEI,                                                    ///< Receive interrupt enable
-    CAN_IT_ALL = 0xFFFF                                                         ///< Receive interrupt enable
-
-} emCAN_PELI_IntEn_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_Status
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    CAN_STATUS_RBS = CAN_SR_RBS,
-    CAN_STATUS_DOS = CAN_SR_DOS,
-    CAN_STATUS_TBS = CAN_SR_TBS,
-    CAN_STATUS_TCS = CAN_SR_TCS,
-    CAN_STATUS_RS  = CAN_SR_RS,
-    CAN_STATUS_TS  = CAN_SR_TS,
-    CAN_STATUS_ES  = CAN_SR_ES,
-    CAN_STATUS_BS  = CAN_SR_BS
-} emCAN_Status_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_Command_register
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    CAN_TR  = CAN_CMR_TR,  ///< Transmission request
-    CAN_AT  = CAN_CMR_AT,
-    CAN_RRB = CAN_CMR_RRB,
-    CAN_CDO = CAN_CMR_CDO
-} emCAN_Command_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  CAN_Peli transmit frame definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DataFrame   = 0,  ///< Data Frame
-    RemoteFrame = !DataFrame
-} TransFrame;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  CAN_Basic init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u8              SJW;
-    u8              BRP;
-    FlagStatus      SAM;
-    u8              TESG2;
-    u8              TESG1;
-    FunctionalState GTS;
-    u8              CDCLK;
-    u8              CLOSE_OPEN_CLK;
-    u8              RXINTEN;
-    u8              CBP;
-} CAN_Basic_InitTypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  CAN_Peli init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u8              SJW;
-    u8              BRP;
-    FlagStatus      SAM;
-    u8              TESG2;
-    u8              TESG1;
-    FunctionalState LOM;
-    FunctionalState STM;
-    FunctionalState SM;
-    FunctionalState SRR;
-    u32             EWLR;
-} CAN_Peli_InitTypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  CAN_Basic filter init structure definition
-////////////////////////////////////////////////////////////////////////////////
-
-typedef struct {
-    u8 CAN_FilterId;      ///< Specifies the filter identification number. This parameter can be a value between 0x00 and 0xFF.
-    u8 CAN_FilterMaskId;  ///< Specifies the filter mask number or identification number, This parameter can be a value between
-    ///< 0x00 and 0xFF.
-} CAN_Basic_FilterInitTypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  CAN_Peli filter init structure definition
-////////////////////////////////////////////////////////////////////////////////
-
-typedef struct {
-    u8 AFM;
-    u8 CAN_FilterId0;  ///< Specifies the filter identification number, This parameter can be a value between 0x00 and 0xFF
-    u8 CAN_FilterId1;
-    u8 CAN_FilterId2;
-    u8 CAN_FilterId3;
-    u8 CAN_FilterMaskId0;  ///< Specifies the filter mask number or identification number, This parameter can be a value between
-    ///< 0x00 and 0xFF
-    u8 CAN_FilterMaskId1;
-    u8 CAN_FilterMaskId2;
-    u8 CAN_FilterMaskId3;
-} CAN_Peli_FilterInitTypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  CAN_Basic Tx message structure definition
-////////////////////////////////////////////////////////////////////////////////
-
-typedef struct {
-    u8 IDH;      ///< Specifies the standard high identifier. This parameter can be a value between 0 to 0xFF.
-    u8 IDL;      ///< Specifies the standard low identifier. This parameter can be a value between 0 to 0x7.
-    u8 RTR;      ///< Specifies the type of frame for the message that will be transmitted. This parameter can be @TransFrame.
-    u8 DLC;      ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8.
-    u8 Data[8];  ///< Contains the data to be transmitted. It ranges from 0 to 0xFF.
-} CanBasicTxMsg;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  CAN_Basic Rx message structure definition
-////////////////////////////////////////////////////////////////////////////////
-
-typedef struct {
-    u16 ID;       ///< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF.
-    u8  RTR;      ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame
-    u8  DLC;      ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8
-    u8  Data[8];  ///< Contains the data to be received. It ranges from 0 to  0xFF.
-} CanBasicRxMsg;
-
-///////////////////////////////////////////////////////////////////////////////
-/// @brief  CAN_Peli_Tx message structure definition
-///////////////////////////////////////////////////////////////////////////////
-
-typedef struct {
-    u8 IDLL;  ///< Specifies the extended identifier.
-    ///< This parameter can be a value between 0 to 0xFF.
-    u8 IDLH;
-    u8 IDHL;
-    u8 IDHH;
-    u8 FF;   ///< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref
-    ///< CAN_identifier_type
-    u8 RTR;  ///< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref
-    ///< TransFrame.
-    u8 DLC;  ///< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8.
-    u8 Data[8];  ///< Contains the data to be transmitted. It ranges from 0 to 0xFF.
-} CanPeliTxMsg;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  CAN Rx message structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u32 ID;  ///< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF.
-    u8  FF;  ///< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref
-    ///< CAN_identifier_type.
-    u8 RTR;  ///< Specifies the type of frame for the received message. This parameter can be a value of @ref TransFrame.
-    u8 DLC;  ///< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8.
-    u8 Data[8];  ///< Contains the data to be received. It ranges from 0 to0xFF.
-} CanPeliRxMsg;
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup  CAN_Exported_Constants
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup  parasmeter_of_CAN_transmission_register
-/// @{
-#define CANTXFAILED (0x00U)   ///< CAN transmission failed
-#define CANTXOK (0x01U)       ///< CAN transmission succeeded
-#define CANTXPENDING (0x02U)  ///< CAN transmission pending
-#define CAN_NO_MB (0x04U)     ///< CAN cell did not provide an empty mailbox
-/// @}
-
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup CAN_Exported_Variables
-/// @{
-#ifdef _HAL_CAN_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup CAN_Exported_Functions
-/// @{
-
-// Basic and Peli Work all need function ---------------------------------------
-
-void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode);
-void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state);
-void CAN_ClearDataOverflow(CAN_TypeDef* can);
-void CAN_ClearITPendingBit(CAN_TypeDef* can);
-
-// Basic Work function ---------------------------------------------------------
-void CAN_DeInit(CAN_TypeDef* can);
-void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct);
-void CAN_StructInit(CAN_Basic_InitTypeDef* basic_init_struct);
-void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state);
-void CAN_CancelTransmit(CAN_TypeDef* can);
-void CAN_FIFORelease(CAN_TypeDef* can);
-void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message);
-
-u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message);
-u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* basic_init_struct);
-u8 CAN_Sleep(CAN_TypeDef* can);
-u8 CAN_WakeUp(CAN_TypeDef* can);
-
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag);
-ITStatus   CAN_GetITStatus(CAN_TypeDef* can, u32 it);
-
-// Peli Work function ----------------------------------------------------------
-void CAN_Peli_SleepMode_Cmd(FunctionalState state);
-void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct);
-void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* peli_init_struct);
-void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct);
-void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct);
-void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message);
-void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message);
-void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message);
-void CAN_Peli_ITConfig(u32 it, FunctionalState state);
-void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud);
-
-u32 CAN_Peli_GetRxFIFOInfo(void);
-u8  CAN_Peli_GetLastErrorCode(void);
-u8  CAN_Peli_GetReceiveErrorCounter(void);
-u8  CAN_Peli_GetLSBTransmitErrorCounter(void);
-
-ITStatus CAN_Peli_GetITStatus(u32 it);
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h
deleted file mode 100644
index 617318d53..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_comp.h
+++ /dev/null
@@ -1,228 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_comp.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE COMP
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_COMP_H
-#define __HAL_COMP_H
-
-
-// Files includes
-#include "reg_common.h"
-#include "reg_comp.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup COMP_HAL
-/// @brief COMP HAL modules
-/// @{
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup COMP_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP_InvertingInput
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    COMP_InvertingInput_IO0           = COMP_CSR_INM_0,                       ///< INM0 as COMP inverting input
-    COMP_InvertingInput_IO1           = COMP_CSR_INM_1,                       ///< INM1 as COMP inverting input
-    COMP_InvertingInput_IO2           = COMP_CSR_INM_2,                       ///< INM2 as COMP inverting input
-    COMP_InvertingInput_CRV           = COMP_CSR_INM_3,                       ///< INM3 as COMP inverting input
-    COMP_InvertingInput_IO3           = COMP_CSR_INM_3,                       ///< INM3 as COMP inverting input
-} EM_COMP_InvertingInput;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP_NonInvertingInput
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    COMP_NonInvertingInput_IO0        = COMP_CSR_INP_INP0,                    ///< INP0 as COMP non-inverting input
-    COMP_NonInvertingInput_IO1        = COMP_CSR_INP_INP1,                    ///< INP1 as COMP non-inverting input
-    COMP_NonInvertingInput_IO2        = COMP_CSR_INP_INP2,                    ///< INP2 as COMP non-inverting input
-    COMP_NonInvertingInput_IO3        = COMP_CSR_INP_INP3,                    ///< INP3 as COMP non-inverting input
-} EM_COMP_NonInvertingInput;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP_Output
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    COMP_Output_None                  = 0x00000000,                             ///< No output
-    COMP_Output_TIM1BKIN              = COMP_CSR_OUT_TIM1_BRAKE,                ///< Timer1 brake input
-    COMP_Output_TIM1OCREFCLR          = COMP_CSR_OUT_TIM1_OCREFCLR,             ///< Timer1 ocrefclear input
-    COMP_Output_TIM1IC1               = COMP_CSR_OUT_TIM1_CAPTURE1,             ///< Timer1 input capture 1
-    COMP_Output_TIM2IC4               = COMP_CSR_OUT_TIM2_CAPTURE4,             ///< Timer2 input capture 4
-    COMP_Output_TIM2OCREFCLR          = COMP_CSR_OUT_TIM2_OCREFCLR,             ///< Timer2 ocrefclear input
-    COMP_Output_TIM3IC1               = COMP_CSR_OUT_TIM3_CAPTURE1,             ///< Timer3 input capture 1
-    COMP_Output_TIM3OCREFCLR          = COMP_CSR_OUT_TIM3_OCREFCLR              ///< Timer3 ocrefclear input
-} EM_COMP_Output;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP_OutputPoloarity
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    COMP_NonInverted                  = 0x00000000,                             ///< COMP non-inverting output
-    COMP_OutputPol_NonInverted        = 0x00000000,
-    COMP_Inverted                     = 0x00008000,                             ///< COMP inverting output
-    COMP_OutputPol_Inverted           = 0x00008000
-} EM_COMP_OutputPol;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP_Hysteresis
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    COMP_Hysteresis_No                = COMP_CSR_HYST_0,                      ///< Hysteresis Voltage: 0mV
-    COMP_Hysteresis_Low               = COMP_CSR_HYST_15,                     ///< Hysteresis Voltage: 15mV
-    COMP_Hysteresis_Medium            = COMP_CSR_HYST_30,                     ///< Hysteresis Voltage: 30mV
-    COMP_Hysteresis_High              = COMP_CSR_HYST_90                      ///< Hysteresis Voltage: 90mV
-} EM_COMP_Hysteresis;
-typedef enum {
-    COMP_Filter_0_Period                = COMP_CSR_OFLT_0,                      ///< filter is ((u32)0x00000000)
-    COMP_Filter_2_Period                = COMP_CSR_OFLT_1,                      ///< filter is ((u32)0x00040000)
-    COMP_Filter_4_Period                = COMP_CSR_OFLT_2,                      ///< filter is ((u32)0x00080000)
-    COMP_Filter_8_Period                = COMP_CSR_OFLT_3,                      ///< filter is ((u32)0x000C0000)
-    COMP_Filter_16_Period               = COMP_CSR_OFLT_4,                      ///< filter is ((u32)0x00100000)
-    COMP_Filter_32_Period               = COMP_CSR_OFLT_5,                      ///< filter is ((u32)0x00140000)
-    COMP_Filter_64_Period               = COMP_CSR_OFLT_6,                      ///< filter is ((u32)0x00180000)
-    COMP_Filter_128_Period              = COMP_CSR_OFLT_7,                      ///< filter is ((u32)0x001C0000)
-} EM_COMP_FILT;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP_Mode
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    COMP_Mode_HighSpeed               = COMP_CSR_MODE_HIGHRATE,               ///< Comparator high rate mode
-    COMP_Mode_MediumSpeed             = COMP_CSR_MODE_MEDIUMRATE,             ///< Comparator medium rate mode
-    COMP_Mode_LowPower                = COMP_CSR_MODE_LOWPOWER,               ///< Comparator low power mode
-    COMP_Mode_UltraLowPower           = COMP_CSR_MODE_LOWESTPOWER             ///< Comparator lowest power mode
-} EM_COMP_Mode;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP_OutputLevel
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    COMP_OutputLevel_High             = COMP_CSR_OUT,                         ///<  High output
-    COMP_OutputLevel_Low              = 0x00000000                            ///<  Low output
-} EM_COMP_OutputLevel;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  COMP Init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    union {
-        u32 COMP_InvertingInput;
-        u32 Invert;                                                             ///< Selects the inverting input of the comparator.
-    };
-    union {
-        u32 COMP_NonInvertingInput;
-        u32 NonInvert;                                                          ///< Selects the non inverting input of the comparator.
-    };
-    union {
-        u32 COMP_Output;
-        u32 Output;                                                             ///< Selects the output redirection of the comparator.
-        u32 BlankingSrce;                                                       ///< Selects the output blanking source of the comparator.
-    };
-    union {
-        u32 COMP_OutputPol;
-        u32 OutputPol;                                                          ///< Selects the output polarity of the comparator.
-    };
-    union {
-        u32 COMP_Hysteresis;
-        u32 Hysteresis;                                                         ///< Selects the hysteresis voltage of the comparator.
-    };
-    union {
-        u32 COMP_Mode;
-        u32 Mode;                                                               ///< Selects the operating mode of the comparator and allows
-    };
-    union {
-        u32 COMP_Filter;
-        u32 OFLT;                                                               ///< to adjust the speed/consumption.
-    };
-} COMP_InitTypeDef;
-
-
-
-typedef struct {
-
-    FunctionalState COMP_Poll_En;                                                ///< Selects the inverting input of the comparator.
-
-    u32 COMP_Poll_Ch;                                                            ///< Selects the non inverting input of the comparator.
-    u32 COMP_Poll_Fixn;                                                          ///< Selects the output redirection of the comparator.
-    u32 COMP_Poll_Period;                                                        ///< Selects the output polarity of the comparator.
-    u32 COMP_Poll_Pout;                                                          ///< Selects the hysteresis voltage of the comparator.
-
-} COMP_POLL_InitTypeDef;
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup COMP_Exported_Constants
-/// @{
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  COMP Init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    COMP1                       =   (0x00000C),                               ///< Select comparator 1
-    COMP2                       =   (0x000010),                               ///< Select comparator 2
-} COMP_Selection_TypeDef;
-
-#define COMP_BlankingSrce_None  ((u32)0x00000000)
-#define COMP_CSR_CLEAR_MASK     ((u32)0x00000003)
-
-#define COMP_CSR_COMPSW1        ((u32)0x00000002)
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-///@defgroup COMP_Exported_Variables
-/// @{
-#ifdef _HAL_COMP_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup COMP_Exported_Functions
-/// @{
-
-
-void COMP_DeInit(COMP_Selection_TypeDef selection);
-void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct);
-void COMP_StructInit(COMP_InitTypeDef* init_struct);
-void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state);
-void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state);
-void COMP_LockConfig(COMP_Selection_TypeDef selection);
-
-u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection);
-
-void COMP_SetCrv(u8 crv_select, u8 crv_level);
-#define  SET_COMP_CRV COMP_SetCrv
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif //__HAL_COMP_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h
deleted file mode 100644
index 758c7a618..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_conf.h
+++ /dev/null
@@ -1,62 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_conf.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GENERIC MICROCONTROLLER
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_CONF_H
-#define __HAL_CONF_H
-// Files includes
-#include "mm32_device.h"
-
-#include "hal_adc.h"
-#include "hal_bkp.h"
-#include "hal_can.h"
-#include "hal_comp.h"
-#include "hal_crc.h"
-#include "hal_crs.h"
-#include "hal_dac.h"
-#include "hal_dbg.h"
-#include "hal_dma.h"
-#include "hal_exti.h"
-#include "hal_flash.h"
-#include "hal_gpio.h"
-#include "hal_i2c.h"
-#include "hal_iwdg.h"
-#include "hal_misc.h"
-#include "hal_pwr.h"
-#include "hal_rcc.h"
-#include "hal_rtc.h"
-#include "hal_spi.h"
-#include "hal_syscfg.h"
-#include "hal_tim.h"
-#include "hal_uart.h"
-#include "hal_uid.h"
-#include "hal_wwdg.h"
-#include "hal_redefine.h"
-#include "hal_eth.h"
-#include "hal_eth_conf.h"
-#include "hal_fsmc.h"
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif //__HAL_CONF_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h
deleted file mode 100644
index f5f3d6054..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crc.h
+++ /dev/null
@@ -1,84 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_crc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRC
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_CRC_H
-#define __HAL_CRC_H
-
-// Files includes
-#include "types.h"
-#include "reg_common.h"
-#include "reg_crc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup CRC_HAL
-/// @brief CRC HAL modules
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup CRC_Exported_Types
-/// @{
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup CRC_Exported_Constants
-/// @{
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup CRC_Exported_Variables
-/// @{
-#ifdef _HAL_CRC_C_
-#define GLOBAL
-
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup CRC_Exported_Functions
-/// @{
-void CRC_ResetDR(void);
-void CRC_SetIDRegister(u8 id_value);
-
-u32 CRC_CalcCRC(u32 data);
-u32 CRC_CalcBlockCRC(u32* buffer, u32 length);
-u32 CRC_GetCRC(void);
-
-u8 CRC_GetIDRegister(void);
-
-/// @}
-
-/// @}
-
-/// @}
-
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_CRC_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h
deleted file mode 100644
index d3c2a6cc5..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_crs.h
+++ /dev/null
@@ -1,46 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_crs.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE CRS
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_CRS_H
-#define __HAL_CRS_H
-
-
-// Files includes
-#include "types.h"
-#include "reg_crs.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup CRS_HAL
-/// @brief CRS HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup GPIO_Exported_Types
-/// @{
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h
deleted file mode 100644
index e538b20b7..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dac.h
+++ /dev/null
@@ -1,166 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_dac.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DAC
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_DAC_H
-#define __HAL_DAC_H
-
-// Files includes
-#include "types.h"
-#include "reg_dac.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DAC_HAL
-/// @brief DAC HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DAC_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_Trigger_Selection
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DAC_Trigger_None     = 0x00000000,
-    DAC_Trigger_T1_TRIG  = (DAC_CR_TSEL1_TIM1_TRIG | DAC_CR_TEN1),
-    DAC_Trigger_T3_TRIG  = (DAC_CR_TSEL1_TIM3_TRIG | DAC_CR_TEN1),
-    DAC_Trigger_T2_TRIG  = (DAC_CR_TSEL1_TIM2_TRIG | DAC_CR_TEN1),
-    DAC_Trigger_T4_TRIG  = (DAC_CR_TSEL1_TIM4_TRIG | DAC_CR_TEN1),
-    DAC_Trigger_Ext_IT9  = (DAC_CR_TSEL1_EXTI9 | DAC_CR_TEN1),
-    DAC_Trigger_Software = (DAC_CR_TSEL1_SOFTWARE)
-} emDACTRIG_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_Wave_Generation
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DAC_WaveGeneration_None     = DAC_CR_WAVE1_NONE,
-    DAC_WaveGeneration_Noise    = DAC_CR_WAVE1_NOISE,
-    DAC_WaveGeneration_Triangle = DAC_CR_WAVE1_TRIANGLE
-} emDACWAVE_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_Mask_Amplitude
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DAC_TriangleAmplitude_1    = DAC_CR_MAMP1_1,
-    DAC_TriangleAmplitude_3    = DAC_CR_MAMP1_3,
-    DAC_TriangleAmplitude_7    = DAC_CR_MAMP1_7,
-    DAC_TriangleAmplitude_15   = DAC_CR_MAMP1_15,
-    DAC_TriangleAmplitude_31   = DAC_CR_MAMP1_31,
-    DAC_TriangleAmplitude_63   = DAC_CR_MAMP1_63,
-    DAC_TriangleAmplitude_127  = DAC_CR_MAMP1_127,
-    DAC_TriangleAmplitude_255  = DAC_CR_MAMP1_255,
-    DAC_TriangleAmplitude_511  = DAC_CR_MAMP1_511,
-    DAC_TriangleAmplitude_1023 = DAC_CR_MAMP1_1023,
-    DAC_TriangleAmplitude_2047 = DAC_CR_MAMP1_2047,
-    DAC_TriangleAmplitude_4095 = DAC_CR_MAMP1_4095
-} emDACAMP_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief channel
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DAC_Channel_1,                                                              ///< DAC channel 1
-    DAC_Channel_2 = (u32)0x00000010                                             ///< DAC Channel 2
-} emDACCH_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_Data_Alignement
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DAC_Align_12b_R = ((u32)0x00000000),
-    DAC_Align_12b_L = ((u32)0x00000004),
-    DAC_Align_8b_R  = ((u32)0x00000008)
-} emDACALIGN_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_Output_Buffer
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DAC_OutputBuffer_Enable  = 0x00000000,                                      ///< DAC output buffer enable
-    DAC_OutputBuffer_Disable = DAC_CR_BOFF1                                     ///< DAC output buffer disable
-} emDACBOFF_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  DAC Init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    emDACTRIG_TypeDef DAC_Trigger;
-    emDACWAVE_TypeDef DAC_WaveGeneration;
-    emDACAMP_TypeDef  DAC_LFSRUnmask_TriangleAmplitude;
-    emDACBOFF_TypeDef DAC_OutputBuffer;
-} DAC_InitTypeDef;
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DAC_Exported_Constants
-/// @{
-#define DHR12R1_Offset  ((u32)0x00000008)
-#define DHR12R2_Offset  ((u32)0x00000014)
-#define DHR12RD_Offset  ((u32)0x00000020)
-#define DOR_Offset      ((u32)0x0000002C)
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DAC_Exported_Variables
-/// @{
-#ifdef _HAL_DAC_C_
-#define GLOBAL
-
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DAC_Exported_Functions
-/// @{
-void DAC_DeInit(void);
-void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct);
-void DAC_StructInit(DAC_InitTypeDef* init_struct);
-void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state);
-void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state);
-void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state);
-void DAC_DualSoftwareTriggerCmd(FunctionalState state);
-void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state);
-void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data);
-void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data);
-void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1);
-
-u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel);
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_DAC_H
-////////////////////////////////////////////////////////////////////////////////
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h
deleted file mode 100644
index 0e9b41d1e..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dbg.h
+++ /dev/null
@@ -1,72 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_dbg.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DBG
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_DBG_H
-#define __HAL_DBG_H
-
-// Files includes
-#include "types.h"
-#include "reg_common.h"
-#include "reg_dbg.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DBG_HAL
-/// @brief DBG HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DBG_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DIV_Exported_Variables
-/// @{
-#ifdef _HAL_DBG_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DBG_Exported_Functions
-/// @{
-void DBGMCU_Configure(u32 periph, FunctionalState state);
-
-/// @}
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_DBG_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h
deleted file mode 100644
index ff2133702..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_device.h
+++ /dev/null
@@ -1,41 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_device.h
-/// @author   AE team
-/// @brief    CMSIS Cortex-M Peripheral Access Layer for MindMotion
-///           microcontroller devices
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_DEVICE_H
-#define __HAL_DEVICE_H
-
-
-
-
-
-#include "mm32_device.h"
-
-
-#endif // __HAL_device_H
-
-/// @}
-
-
-/// @}
-
-/// @}
-
-
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h
deleted file mode 100644
index 892e750b5..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_dma.h
+++ /dev/null
@@ -1,306 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_dma.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DMA
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_DMA_H
-#define __HAL_DMA_H
-// Files includes
-#include "types.h"
-#include "reg_common.h"
-#include "reg_dma.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DMA_HAL
-/// @brief DMA HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DMA_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA data transfer direction Enumerate definition
-/// @anchor DMA_data_transfer_direction
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMA_DIR_PeripheralSRC = 0U,
-    DMA_DIR_PeripheralDST = DMA_CCR_DIR  // 0x00000010U
-} DMA_data_transfer_direction_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA peripheral incremented mode Enumerate definition
-/// @anchor DMA_peripheral_incremented_mode
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMA_PeripheralInc_Disable = 0U,
-    DMA_PeripheralInc_Enable  = DMA_CCR_PINC  // 0x00000040U
-} DMA_peripheral_incremented_mode_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA memory incremented mode Enumerate definition
-/// @anchor DMA_memory_incremented_mode
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMA_MemoryInc_Disable = 0U,
-    DMA_MemoryInc_Enable  = DMA_CCR_MINC  // 0x00000080U
-} DMA_memory_incremented_mode_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA peripheral data size Enumerate definition
-/// @anchor DMA_peripheral_data_size
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMA_PeripheralDataSize_Byte     = 0U,
-    DMA_PeripheralDataSize_HalfWord = DMA_CCR_PSIZE_HALFWORD,
-    DMA_PeripheralDataSize_Word     = DMA_CCR_PSIZE_WORD
-} DMA_peripheral_data_size_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA memory data size Enumerate definition
-/// @anchor DMA_memory_data_size
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMA_MemoryDataSize_Byte     = 0U,
-    DMA_MemoryDataSize_HalfWord = DMA_CCR_MSIZE_HALFWORD,                       // 0x00000400U
-    DMA_MemoryDataSize_Word     = DMA_CCR_MSIZE_WORD                            // 0x00000800U
-} DMA_memory_data_size_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA circular normal mode Enumerate definition
-/// @anchor DMA_circular_normal_mode
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMA_Mode_Normal   = 0U,
-    DMA_Mode_Circular = DMA_CCR_CIRC                                            // 0x00000020U
-} DMA_circular_normal_mode_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA priority level Enumerate definition
-/// @anchor DMA_priority_level
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMA_Priority_Low      = 0U,
-    DMA_Priority_Medium   = DMA_CCR_PL_Medium,                                  // 0x00001000U
-    DMA_Priority_High     = DMA_CCR_PL_High,                                    // 0x00002000U
-    DMA_Priority_VeryHigh = DMA_CCR_PL_VeryHigh                                 // 0x00003000U
-} DMA_priority_level_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA memory to memory Enumerate definition
-/// @anchor DMA_memory_to_memory
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMA_M2M_Disable = 0U,
-    DMA_M2M_Enable  = DMA_CCR_M2M                                               // 0x00004000U
-} DMA_memory_to_memory_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA auto reload Enumerate definition
-/// @anchor DMA_auto_reload
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMA_Auto_Reload_Disable = 0U,  //
-    DMA_Auto_Reload_Enable  = DMA_CCR_ARE
-} DMA_auto_reload_TypeDef;
-/// @brief DMA Interrupt Setting Enumerate definition
-/// @anchor DMA_auto_reload
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMA_IT_TC                 = DMA_CCR_TCIE, //(0x00000002UL),
-    DMA_IT_HT                 = DMA_CCR_HTIE, //(0x00000004UL),
-    DMA_IT_TE                 = DMA_CCR_TEIE, //(0x00000008UL),
-} DMA_Interrupt_EN_TypeDef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA interrupts Enumerate definition
-/// @anchor DMA_Flags
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    DMAx_IT_GLy               = (0x00000001UL),
-    DMAx_IT_TCy               = (0x00000002UL),
-    DMAx_IT_HTy               = (0x00000004UL),
-    DMAx_IT_TEy               = (0x00000008UL),
-    DMA1_IT_GL1               = (0x00000001UL),
-    DMA1_IT_TC1               = (0x00000002UL),
-    DMA1_IT_HT1               = (0x00000004UL),
-    DMA1_IT_TE1               = (0x00000008UL),
-    DMA1_IT_GL2               = (0x00000010UL),
-    DMA1_IT_TC2               = (0x00000020UL),
-    DMA1_IT_HT2               = (0x00000040UL),
-    DMA1_IT_TE2               = (0x00000080UL),
-    DMA1_IT_GL3               = (0x00000100UL),
-    DMA1_IT_TC3               = (0x00000200UL),
-    DMA1_IT_HT3               = (0x00000400UL),
-    DMA1_IT_TE3               = (0x00000800UL),
-    DMA1_IT_GL4               = (0x00001000UL),
-    DMA1_IT_TC4               = (0x00002000UL),
-    DMA1_IT_HT4               = (0x00004000UL),
-    DMA1_IT_TE4               = (0x00008000UL),
-    DMA1_IT_GL5               = (0x00010000UL),
-    DMA1_IT_TC5               = (0x00020000UL),
-    DMA1_IT_HT5               = (0x00040000UL),
-    DMA1_IT_TE5               = (0x00080000UL),
-    DMA1_IT_GL6               = (0x00100000UL),
-    DMA1_IT_TC6               = (0x00200000UL),
-    DMA1_IT_HT6               = (0x00400000UL),
-    DMA1_IT_TE6               = (0x00800000UL),
-    DMA1_IT_GL7               = (0x01000000UL),
-    DMA1_IT_TC7               = (0x02000000UL),
-    DMA1_IT_HT7               = (0x04000000UL),
-    DMA1_IT_TE7               = (0x08000000UL),
-    DMA2_IT_GL1               = (0x10000001UL),
-    DMA2_IT_TC1               = (0x10000002UL),
-    DMA2_IT_HT1               = (0x10000004UL),
-    DMA2_IT_TE1               = (0x10000008UL),
-    DMA2_IT_GL2               = (0x10000010UL),
-    DMA2_IT_TC2               = (0x10000020UL),
-    DMA2_IT_HT2               = (0x10000040UL),
-    DMA2_IT_TE2               = (0x10000080UL),
-    DMA2_IT_GL3               = (0x10000100UL),
-    DMA2_IT_TC3               = (0x10000200UL),
-    DMA2_IT_HT3               = (0x10000400UL),
-    DMA2_IT_TE3               = (0x10000800UL),
-    DMA2_IT_GL4               = (0x10001000UL),
-    DMA2_IT_TC4               = (0x10002000UL),
-    DMA2_IT_HT4               = (0x10004000UL),
-    DMA2_IT_TE4               = (0x10008000UL),
-    DMA2_IT_GL5               = (0x10010000UL),
-    DMA2_IT_TC5               = (0x10020000UL),
-    DMA2_IT_HT5               = (0x10040000UL),
-    DMA2_IT_TE5               = (0x10080000UL),
-} DMA_Interrupts_TypeDef;
-typedef enum {
-    DMAx_FLAG_GLy               = (0x00000001UL),
-    DMAx_FLAG_TCy               = (0x00000002UL),
-    DMAx_FLAG_HTy               = (0x00000004UL),
-    DMAx_FLAG_TEy               = (0x00000008UL),
-    DMA1_FLAG_GL1               = (0x00000001UL),
-    DMA1_FLAG_TC1               = (0x00000002UL),
-    DMA1_FLAG_HT1               = (0x00000004UL),
-    DMA1_FLAG_TE1               = (0x00000008UL),
-    DMA1_FLAG_GL2               = (0x00000010UL),
-    DMA1_FLAG_TC2               = (0x00000020UL),
-    DMA1_FLAG_HT2               = (0x00000040UL),
-    DMA1_FLAG_TE2               = (0x00000080UL),
-    DMA1_FLAG_GL3               = (0x00000100UL),
-    DMA1_FLAG_TC3               = (0x00000200UL),
-    DMA1_FLAG_HT3               = (0x00000400UL),
-    DMA1_FLAG_TE3               = (0x00000800UL),
-    DMA1_FLAG_GL4               = (0x00001000UL),
-    DMA1_FLAG_TC4               = (0x00002000UL),
-    DMA1_FLAG_HT4               = (0x00004000UL),
-    DMA1_FLAG_TE4               = (0x00008000UL),
-    DMA1_FLAG_GL5               = (0x00010000UL),
-    DMA1_FLAG_TC5               = (0x00020000UL),
-    DMA1_FLAG_HT5               = (0x00040000UL),
-    DMA1_FLAG_TE5               = (0x00080000UL),
-    DMA1_FLAG_GL6               = (0x00100000UL),
-    DMA1_FLAG_TC6               = (0x00200000UL),
-    DMA1_FLAG_HT6               = (0x00400000UL),
-    DMA1_FLAG_TE6               = (0x00800000UL),
-    DMA1_FLAG_GL7               = (0x01000000UL),
-    DMA1_FLAG_TC7               = (0x02000000UL),
-    DMA1_FLAG_HT7               = (0x04000000UL),
-    DMA1_FLAG_TE7               = (0x08000000UL),
-    DMA2_FLAG_GL1               = (0x10000001UL),
-    DMA2_FLAG_TC1               = (0x10000002UL),
-    DMA2_FLAG_HT1               = (0x10000004UL),
-    DMA2_FLAG_TE1               = (0x10000008UL),
-    DMA2_FLAG_GL2               = (0x10000010UL),
-    DMA2_FLAG_TC2               = (0x10000020UL),
-    DMA2_FLAG_HT2               = (0x10000040UL),
-    DMA2_FLAG_TE2               = (0x10000080UL),
-    DMA2_FLAG_GL3               = (0x10000100UL),
-    DMA2_FLAG_TC3               = (0x10000200UL),
-    DMA2_FLAG_HT3               = (0x10000400UL),
-    DMA2_FLAG_TE3               = (0x10000800UL),
-    DMA2_FLAG_GL4               = (0x10001000UL),
-    DMA2_FLAG_TC4               = (0x10002000UL),
-    DMA2_FLAG_HT4               = (0x10004000UL),
-    DMA2_FLAG_TE4               = (0x10008000UL),
-    DMA2_FLAG_GL5               = (0x10010000UL),
-    DMA2_FLAG_TC5               = (0x10020000UL),
-    DMA2_FLAG_HT5               = (0x10040000UL),
-    DMA2_FLAG_TE5               = (0x10080000UL),
-} DMA_Flags_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  DMA Init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u32 DMA_PeripheralBaseAddr;                                 ///< the peripheral base address for DMA Channeln.
-    u32 DMA_MemoryBaseAddr;                                     ///< the memory base address for DMA Channeln.
-    DMA_data_transfer_direction_TypeDef DMA_DIR;                ///< the peripheral is the source or destination.
-    u32 DMA_BufferSize;                                         ///< Specifies the buffer size, in data unit, of the Buffer size
-    DMA_peripheral_incremented_mode_TypeDef DMA_PeripheralInc;  ///< Specifies whether the Peripheral address increment or not
-    DMA_memory_incremented_mode_TypeDef DMA_MemoryInc;          ///< Specifies whether the memory address register is increment or not
-    DMA_peripheral_data_size_TypeDef DMA_PeripheralDataSize;    ///< Specifies the Peripheral data width.
-    DMA_memory_data_size_TypeDef DMA_MemoryDataSize;            ///< Specifies the Memory data width.
-    DMA_circular_normal_mode_TypeDef DMA_Mode;                  ///< Specifies the operation mode of the DMA Channeln  circular or normal mode.
-    DMA_priority_level_TypeDef DMA_Priority;                    ///< Specifies the software priority for the DMA priority level
-    DMA_memory_to_memory_TypeDef DMA_M2M;                       ///< Specifies if the DMA Channeln will be used in  memory-to-memory transfer.
-    DMA_auto_reload_TypeDef DMA_Auto_reload;                     ///< Specifies if the DMA Channeln will auto reload the CNDTR register
-} DMA_InitTypeDef;
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DMA_Exported_Variables
-/// @{
-#ifdef _HAL_DMA_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DMA_Exported_Functions
-/// @{
-
-void DMA_DeInit(DMA_Channel_TypeDef* channel);
-void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct);
-void DMA_StructInit(DMA_InitTypeDef* init_struct);
-void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state);
-void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state);
-void DMA_ClearFlag(DMA_Flags_TypeDef flag);
-void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it);
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length);
-u16        DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel);
-FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag);
-ITStatus   DMA_GetITStatus(DMA_Interrupts_TypeDef it);
-
-void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 addr);
-void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 len);
-void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 addr);
-
-/// @}
-
-/// @}
-
-/// @}
-////////////////////////////////////////////////////////////////////////////////
-#endif //__HAL_DMA_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h
deleted file mode 100644
index 4000bbaa5..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth.h
+++ /dev/null
@@ -1,729 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     HAL_eth.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE HAL_eth.h EXAMPLES.
-/// ////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT  MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-#ifndef __HAL_ETH_H
-#define __HAL_ETH_H
-
-// Files includes
-#include "types.h"
-#include "mm32_device.h"
-#include "HAL_eth_conf.h"
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup ETH_HAL
-/// @brief ETH HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup ETH_Exported_Types
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-// ETH     | Header | Extra | VLAN tag | Payload   | CRC |
-// Size    | 14     | 2     | 4        | 46 ~ 1500 | 4   |
-#define ETH_MAX_PACKET_SIZE     1524
-#define ETH_HEADER              14      ///< MAC Dest Addr 6 byte + MAC Src Addr 6 byte + Lenth/Type 2 byte
-#define ETH_EXTRA               2
-#define VLAN_TAG                4
-#define ETH_PAYLOAD_MIN         46
-#define ETH_PAYLOAD_MAX         1500
-#define JUMBO_FRAME_PAYLOAD     9000
-
-#ifndef ETH_RX_BUF_SIZE
-#define ETH_RX_BUF_SIZE     ETH_MAX_PACKET_SIZE
-#endif
-
-#ifndef ETH_RX_BUF_NUM
-#define ETH_RX_BUF_NUM      4
-#endif
-
-#ifndef ETH_TX_BUF_SIZE
-#define ETH_TX_BUF_SIZE     ETH_MAX_PACKET_SIZE
-#endif
-
-#ifndef ETH_TX_BUF_NUM
-#define ETH_TX_BUF_NUM      4
-#endif
-
-#define ETH_DMA_RDES_FL_Pos     16                                              ///< Ethernet DMA Received Frame Length Position
-
-#define ETH_WAKEUP_REGISTER_LENGTH                          8                   ///< ETHERNET Remote Wake-up frame register length
-
-#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT       17                  ///< ETHERNET Missed frames counter Shift
-
-#define ETH_DMA_TDES_COLLISION_COUNTSHIFT                   3                   ///< ETHERNET DMA Tx descriptors Collision Count Shift
-#define ETH_DMA_TDES_BUFFER2_SIZESHIFT                      11                  ///< ETHERNET DMA Tx descriptors Buffer2 Size Shift
-
-#define ETH_DMA_RDES_FRAME_LENGTHSHIFT                      16                  ///< ETHERNET DMA Rx descriptors Frame Length Shift
-#define ETH_DMA_RDES_BUFFER2_SIZESHIFT                      11                  ///< ETHERNET DMA Rx descriptors Buffer2 Size Shift
-
-///< ETHERNET errors
-#define  ETH_ERROR                                          ((u32)0)
-#define  ETH_SUCCESS                                        ((u32)1)
-
-
-#ifdef _HAL_ETH_C_
-#define GLOBAL
-
-#else
-#define GLOBAL extern
-#endif
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH Init Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32    ETH_AutoNegotiation;
-    __IO u32    ETH_Watchdog;
-    __IO u32    ETH_Jabber;
-    __IO u32    ETH_InterFrameGap;
-    __IO u32    ETH_CarrierSense;
-    __IO u32    ETH_Speed;
-    __IO u32    ETH_ReceiveOwn;
-    __IO u32    ETH_LoopbackMode;
-    __IO u32    ETH_Mode;
-    __IO u32    ETH_ChecksumOffload;
-    __IO u32    ETH_RetryTransmission;
-    __IO u32    ETH_AutomaticPadCRCStrip;
-    __IO u32    ETH_BackOffLimit;
-    __IO u32    ETH_DeferralCheck;
-    __IO u32    ETH_ReceiveAll;
-    __IO u32    ETH_SourceAddrFilter;
-    __IO u32    ETH_PassControlFrames;
-    __IO u32    ETH_BroadcastFramesReception;
-    __IO u32    ETH_DestinationAddrFilter;
-    __IO u32    ETH_PromiscuousMode;
-    __IO u32    ETH_MulticastFramesFilter;
-    __IO u32    ETH_UnicastFramesFilter;
-    __IO u32    ETH_HashTableHigh;
-    __IO u32    ETH_HashTableLow;
-    __IO u32    ETH_PauseTime;
-    __IO u32    ETH_ZeroQuantaPause;
-    __IO u32    ETH_PauseLowThreshold;
-    __IO u32    ETH_UnicastPauseFrameDetect;
-    __IO u32    ETH_ReceiveFlowControl;
-    __IO u32    ETH_TransmitFlowControl;
-    __IO u32    ETH_VLANTagComparison;
-    __IO u32    ETH_VLANTagIdentifier;
-    __IO u32    ETH_DropTCPIPChecksumErrorFrame;
-    __IO u32    ETH_ReceiveStoreForward;
-    __IO u32    ETH_FlushReceivedFrame;
-    __IO u32    ETH_TransmitStoreForward;
-    __IO u32    ETH_TransmitThresholdControl;
-    __IO u32    ETH_ForwardErrorFrames;
-    __IO u32    ETH_ForwardUndersizedGoodFrames;
-    __IO u32    ETH_ReceiveThresholdControl;
-    __IO u32    ETH_SecondFrameOperate;
-    __IO u32    ETH_AddressAlignedBeats;
-    __IO u32    ETH_FixedBurst;
-    __IO u32    ETH_RxDMABurstLength;
-    __IO u32    ETH_TxDMABurstLength;
-    __IO u32    ETH_DescriptorSkipLength;
-    __IO u32    ETH_DMAArbitration;
-} ETH_InitTypeDef;
-
-typedef struct {
-    __IO u32   CS;                                                              ///< Control and Status
-    __IO u32   BL;                                                              ///< Buffer1, Buffer2 lengths
-    __IO u32   BUF1ADDR;                                                        ///< Buffer1 address pointer
-    __IO u32   BUF2NDADDR;                                                      ///< Buffer2 or next descriptor address pointer
-
-#ifdef USE_ENHANCED_DMA_DESCRIPTORS                                             ///< Enhanced ETHERNET DMA PTP Descriptors
-    __IO u32        ExtendedStatus;                                             ///< Extended status for PTP receive descriptor
-    __IO u32        Reserved1;                                                  ///< Reserved
-    __IO u32        TimeStampLow;                                               ///< Time Stamp Low value for transmit and receive
-    __IO u32        TimeStampHigh;                                              ///< Time Stamp High value for transmit and receive
-#endif
-} ETH_DMADESCTypeDef;
-
-typedef struct {
-    __IO u32                         len;
-    __IO u32                         buf;
-    __IO ETH_DMADESCTypeDef*    ptrDesc;
-} FrameTypeDef;
-
-typedef struct  {
-    __IO ETH_DMADESCTypeDef*    ptrFS_Rx_Desc;                                  ///< First Segment Rx Desc
-    __IO ETH_DMADESCTypeDef*    ptrLS_Rx_Desc;                                  ///< Last Segment Rx Desc
-    __IO u32               cnt;                                            ///< Segment count
-} ETH_DMA_Rx_Frame_infos;
-
-
-
-#define ETH_DMA_TDES_OWN                     ((u32)0x80000000)             ///< OWN bit: descriptor is owned by DMA engine
-#define ETH_DMA_TDES_ES                      ((u32)0x00008000)             ///< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT
-#define ETH_DMA_TDES_JT                      ((u32)0x00004000)             ///< Jabber Timeout
-#define ETH_DMA_TDES_FF                      ((u32)0x00002000)             ///< Frame Flushed: DMA/MTL flushed the frame due to SW flush
-#define ETH_DMA_TDES_LCA                     ((u32)0x00000800)             ///< Loss of Carrier: carrier lost during transmission
-#define ETH_DMA_TDES_NC                      ((u32)0x00000400)             ///< No Carrier: no carrier signal from the transceiver
-#define ETH_DMA_TDES_LCO                     ((u32)0x00000200)             ///< Late Collision: transmission aborted due to collision
-#define ETH_DMA_TDES_EC                      ((u32)0x00000100)             ///< Excessive Collision: transmission aborted after 16 collisions
-#define ETH_DMA_TDES_VF                      ((u32)0x00000080)             ///< VLAN Frame
-#define ETH_DMA_TDES_CC                      ((u32)0x00000078)             ///< Collision Count
-#define ETH_DMA_TDES_ED                      ((u32)0x00000004)             ///< Excessive Deferral
-#define ETH_DMA_TDES_UF                      ((u32)0x00000002)             ///< Underflow Error: late data arrival from the memory
-#define ETH_DMA_TDES_DB                      ((u32)0x00000001)             ///< Deferred Bit
-
-#define ETH_DMA_TDES_IC                      ((u32)0x80000000)             ///< Interrupt on Completion
-#define ETH_DMA_TDES_LS                      ((u32)0x40000000)             ///< Last Segment
-#define ETH_DMA_TDES_FS                      ((u32)0x20000000)             ///< First Segment
-#define ETH_DMA_TDES_DC                      ((u32)0x04000000)             ///< Disable CRC
-#define ETH_DMA_TDES_TER                     ((u32)0x02000000)             ///< Transmit end of ring
-#define ETH_DMA_TDES_TCH                     ((u32)0x01000000)             ///< Second Address Chained
-#define ETH_DMA_TDES_DP                      ((u32)0x00800000)             ///< Disable Padding
-#define ETH_DMA_TDES_TBS2                    ((u32)0x003FF800)             ///< Transmit Buffer 2 Size
-#define ETH_DMA_TDES_TBS1                    ((u32)0x000007FF)             ///< Transmit Buffer 1 Size
-
-#define ETH_DMA_TDES_B1AP                    ((u32)0xFFFFFFFF)             ///< Buffer 1 Address Pointer
-
-#define ETH_DMA_TDES_B2AP                    ((u32)0xFFFFFFFF)             ///< Buffer 2 Address Pointer
-
-#if defined(USE_ENHANCED_DMA_DESCRIPTORS)
-#define ETH_DMA_PTP_TDES_TTSL                ((u32)0xFFFFFFFF)              ///< Transmit Time Stamp Low
-#define ETH_DMA_PTP_TDES_TTSH                ((u32)0xFFFFFFFF)              ///< Transmit Time Stamp High
-#endif
-
-#define ETH_DMA_RDES_OWN                     ((u32)0x80000000)             ///< OWN bit: descriptor is owned by DMA engine
-#define ETH_DMA_RDES_AFM                     ((u32)0x40000000)             ///< DA Filter Fail for the rx frame
-#define ETH_DMA_RDES_FL                      ((u32)0x3FFF0000)             ///< Receive descriptor frame length
-#define ETH_DMA_RDES_ES                      ((u32)0x00008000)             ///< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE
-#define ETH_DMA_RDES_DE                      ((u32)0x00004000)             ///< Descriptor error: no more descriptors for receive frame
-#define ETH_DMA_RDES_SAF                     ((u32)0x00002000)             ///< SA Filter Fail for the received frame
-#define ETH_DMA_RDES_LE                      ((u32)0x00001000)             ///< Frame size not matching with length field
-#define ETH_DMA_RDES_OE                      ((u32)0x00000800)             ///< Overflow Error: Frame was damaged due to buffer overflow
-#define ETH_DMA_RDES_VLAN                    ((u32)0x00000400)             ///< VLAN Tag: received frame is a VLAN frame
-#define ETH_DMA_RDES_FS                      ((u32)0x00000200)             ///< First descriptor of the frame
-#define ETH_DMA_RDES_LS                      ((u32)0x00000100)             ///< Last descriptor of the frame
-#define ETH_DMA_RDES_IPV4HCE                 ((u32)0x00000080)             ///< IPC Checksum Error: Rx Ipv4 header checksum error
-#define ETH_DMA_RDES_LC                      ((u32)0x00000040)             ///< Late collision occurred during reception
-#define ETH_DMA_RDES_FT                      ((u32)0x00000020)             ///< Frame type - Ethernet, otherwise 802.3
-#define ETH_DMA_RDES_RWT                     ((u32)0x00000010)             ///< Receive Watchdog Timeout: watchdog timer expired during reception
-#define ETH_DMA_RDES_RE                      ((u32)0x00000008)             ///< Receive error: error reported by MII interface
-#define ETH_DMA_RDES_DBE                     ((u32)0x00000004)             ///< Dribble bit error: frame contains non int multiple of 8 bits
-#define ETH_DMA_RDES_CE                      ((u32)0x00000002)             ///< CRC error
-#define ETH_DMA_RDES_MAMPCE                  ((u32)0x00000001)             ///< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
-
-#define ETH_DMA_RDES_DIC                     ((u32)0x80000000)             ///< Disable Interrupt on Completion
-#define ETH_DMA_RDES_RER                     ((u32)0x02000000)             ///< Receive End of Ring
-#define ETH_DMA_RDES_RCH                     ((u32)0x01000000)             ///< Second Address Chained
-#define ETH_DMA_RDES_RBS2                    ((u32)0x003FF800)             ///< Receive Buffer2 Size
-#define ETH_DMA_RDES_RBS1                    ((u32)0x000007FF)             ///< Receive Buffer1 Size
-
-#define ETH_DMA_RDES_B1AP                    ((u32)0xFFFFFFFF)             ///< Buffer 1 Address Pointer
-
-#define ETH_DMA_RDES_B2AP                    ((u32)0xFFFFFFFF)             ///< Buffer 2 Address Pointer
-
-
-#if defined(USE_ENHANCED_DMA_DESCRIPTORS)
-#define ETH_DMA_PTP_RDES_PTPV                            ((u32)0x00002000)  ///< PTP Version
-#define ETH_DMA_PTP_RDES_PTPFT                           ((u32)0x00001000)  ///< PTP Frame Type
-#define ETH_DMA_PTP_RDES_PTPMT                           ((u32)0x00000F00)  ///< PTP Message Type
-#define ETH_DMA_PTP_RDES_PTPMT_Sync                      ((u32)0x00000100)  ///< SYNC message (all clock types)
-#define ETH_DMA_PTP_RDES_PTPMT_FollowUp                  ((u32)0x00000200)  ///< FollowUp message (all clock types)
-#define ETH_DMA_PTP_RDES_PTPMT_DelayReq                  ((u32)0x00000300)  ///< DelayReq message (all clock types)
-#define ETH_DMA_PTP_RDES_PTPMT_DelayResp                 ((u32)0x00000400)  ///< DelayResp message (all clock types)
-#define ETH_DMA_PTP_RDES_PTPMT_PdelayReq_Announce        ((u32)0x00000500)  ///< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock)
-#define ETH_DMA_PTP_RDES_PTPMT_PdelayResp_Manag          ((u32)0x00000600)  ///< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)
-#define ETH_DMA_PTP_RDES_PTPMT_PdelayRespFollowUp_Signal ((u32)0x00000700)  ///< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock)
-#define ETH_DMA_PTP_RDES_IPV6PR                          ((u32)0x00000080)  ///< IPv6 Packet Received
-#define ETH_DMA_PTP_RDES_IPV4PR                          ((u32)0x00000040)  ///< IPv4 Packet Received
-#define ETH_DMA_PTP_RDES_IPCB                            ((u32)0x00000020)  ///< IP Checksum Bypassed
-#define ETH_DMA_PTP_RDES_IPPE                            ((u32)0x00000010)  ///< IP Payload Error
-#define ETH_DMA_PTP_RDES_IPHE                            ((u32)0x00000008)  ///< IP Header Error
-#define ETH_DMA_PTP_RDES_IPPT                            ((u32)0x00000007)  ///< IP Payload Type
-#define ETH_DMA_PTP_RDES_IPPT_UDP                        ((u32)0x00000001)  ///< UDP payload encapsulated in the IP datagram
-#define ETH_DMA_PTP_RDES_IPPT_TCP                        ((u32)0x00000002)  ///< TCP payload encapsulated in the IP datagram
-#define ETH_DMA_PTP_RDES_IPPT_ICMP                       ((u32)0x00000003)  ///< ICMP payload encapsulated in the IP datagram
-
-
-
-#define ETH_DMA_PTP_RDES_TTSL               ((u32)0xFFFFFFFF)              ///< Receive Time Stamp Low
-#define ETH_DMA_PTP_RDES_TTSH               ((u32)0xFFFFFFFF)              ///< Receive Time Stamp High
-#endif
-
-////////////////////////////////////////////////////////////////////////////////
-#define PHY_READ_TIMEOUT                    ((u32)0x0004FFFF)
-#define PHY_WRITE_TIMEOUT                   ((u32)0x0004FFFF)
-
-#define PHY_BCR                             0                                   ///< Transceiver Basic Control Register
-#define PHY_BSR                             1                                   ///< Transceiver Basic Status Register
-
-#define PHY_Reset                           ((u16)0x8000)                  ///< PHY Reset
-#define PHY_Loopback                        ((u16)0x4000)                  ///< Select loop-back mode
-#define PHY_FULLDUPLEX_100M                 ((u16)0x2100)                  ///< Set the full-duplex mode at 100 Mb/s
-#define PHY_HALFDUPLEX_100M                 ((u16)0x2000)                  ///< Set the half-duplex mode at 100 Mb/s
-#define PHY_FULLDUPLEX_10M                  ((u16)0x0100)                  ///< Set the full-duplex mode at 10 Mb/s
-#define PHY_HALFDUPLEX_10M                  ((u16)0x0000)                  ///< Set the half-duplex mode at 10 Mb/s
-#define PHY_AutoNegotiation                 ((u16)0x1000)                  ///< Enable auto-negotiation function
-#define PHY_Restart_AutoNegotiation         ((u16)0x0200)                  ///< Restart auto-negotiation function
-#define PHY_Powerdown                       ((u16)0x0800)                  ///< Select the power down mode
-#define PHY_Isolate                         ((u16)0x0400)                  ///< Isolate PHY from MII
-
-#define PHY_AutoNego_Complete               ((u16)0x0020)                  ///< Auto-Negotiation process completed
-#define PHY_Linked_Status                   ((u16)0x0004)                  ///< Valid link established
-#define PHY_Jabber_detection                ((u16)0x0002)                  ///< Jabber condition detected
-
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_AutoNegotiation_Enable          ((u32)0x00000001)
-#define ETH_AutoNegotiation_Disable         ((u32)0x00000000)
-
-#define ETH_Watchdog_Enable                 ((u32)0x00000000)
-#define ETH_Watchdog_Disable                ((u32)0x00800000)
-
-#define ETH_Jabber_Enable                   ((u32)0x00000000)
-#define ETH_Jabber_Disable                  ((u32)0x00400000)
-
-#define ETH_InterFrameGap_96Bit             ((u32)0x00000000)              ///< minimum IFG between frames during transmission is 96Bit
-#define ETH_InterFrameGap_88Bit             ((u32)0x00020000)              ///< minimum IFG between frames during transmission is 88Bit
-#define ETH_InterFrameGap_80Bit             ((u32)0x00040000)              ///< minimum IFG between frames during transmission is 80Bit
-#define ETH_InterFrameGap_72Bit             ((u32)0x00060000)              ///< minimum IFG between frames during transmission is 72Bit
-#define ETH_InterFrameGap_64Bit             ((u32)0x00080000)              ///< minimum IFG between frames during transmission is 64Bit
-#define ETH_InterFrameGap_56Bit             ((u32)0x000A0000)              ///< minimum IFG between frames during transmission is 56Bit
-#define ETH_InterFrameGap_48Bit             ((u32)0x000C0000)              ///< minimum IFG between frames during transmission is 48Bit
-#define ETH_InterFrameGap_40Bit             ((u32)0x000E0000)              ///< minimum IFG between frames during transmission is 40Bit
-
-#define ETH_CarrierSense_Enable             ((u32)0x00000000)
-#define ETH_CarrierSense_Disable            ((u32)0x00010000)
-
-#define ETH_Speed_10M                       ((u32)0x00000000)
-#define ETH_Speed_100M                      ((u32)0x00004000)
-
-#define ETH_ReceiveOwn_Enable               ((u32)0x00000000)
-#define ETH_ReceiveOwn_Disable              ((u32)0x00002000)
-
-#define ETH_LoopbackMode_Enable             ((u32)0x00001000)
-#define ETH_LoopbackMode_Disable            ((u32)0x00000000)
-
-#define ETH_Mode_FullDuplex                 ((u32)0x00000800)
-#define ETH_Mode_HalfDuplex                 ((u32)0x00000000)
-
-#define ETH_ChecksumOffload_Enable          ((u32)0x00000400)
-#define ETH_ChecksumOffload_Disable         ((u32)0x00000000)
-
-#define ETH_RetryTransmission_Enable        ((u32)0x00000000)
-#define ETH_RetryTransmission_Disable       ((u32)0x00000200)
-
-#define ETH_AutomaticPadCRCStrip_Enable     ((u32)0x00000080)
-#define ETH_AutomaticPadCRCStrip_Disable    ((u32)0x00000000)
-
-#define ETH_BackOffLimit_10                 ((u32)0x00000000)
-#define ETH_BackOffLimit_8                  ((u32)0x00000020)
-#define ETH_BackOffLimit_4                  ((u32)0x00000040)
-#define ETH_BackOffLimit_1                  ((u32)0x00000060)
-
-#define ETH_DeferralCheck_Enable            ((u32)0x00000010)
-#define ETH_DeferralCheck_Disable           ((u32)0x00000000)
-
-#define ETH_ReceiveAll_Enable               ((u32)0x80000000)
-#define ETH_ReceiveAll_Disable              ((u32)0x00000000)
-
-#define ETH_SourceAddrFilter_Normal_Enable  ((u32)0x00000200)
-#define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300)
-#define ETH_SourceAddrFilter_Disable        ((u32)0x00000000)
-
-#define ETH_PassControlFrames_BlockAll                  ((u32)0x00000040)  ///< MAC filters all control frames from reaching the application
-#define ETH_PassControlFrames_ForwardAll                ((u32)0x00000080)  ///< MAC forwards all control frames to application even if they fail the Address Filter
-#define ETH_PassControlFrames_ForwardPassedAddrFilter   ((u32)0x000000C0)  ///< MAC forwards control frames that pass the Address Filter.
-
-#define ETH_BroadcastFramesReception_Enable             ((u32)0x00000000)
-#define ETH_BroadcastFramesReception_Disable            ((u32)0x00000020)
-
-#define ETH_DestinationAddrFilter_Normal                ((u32)0x00000000)
-#define ETH_DestinationAddrFilter_Inverse               ((u32)0x00000008)
-
-#define ETH_PromiscuousMode_Enable                      ((u32)0x00000001)
-#define ETH_PromiscuousMode_Disable                     ((u32)0x00000000)
-
-#define ETH_MulticastFramesFilter_PerfectHashTable      ((u32)0x00000404)
-#define ETH_MulticastFramesFilter_HashTable             ((u32)0x00000004)
-#define ETH_MulticastFramesFilter_Perfect               ((u32)0x00000000)
-#define ETH_MulticastFramesFilter_None                  ((u32)0x00000010)
-
-#define ETH_UnicastFramesFilter_PerfectHashTable        ((u32)0x00000402)
-#define ETH_UnicastFramesFilter_HashTable               ((u32)0x00000002)
-#define ETH_UnicastFramesFilter_Perfect                 ((u32)0x00000000)
-
-#define ETH_ZeroQuantaPause_Enable                      ((u32)0x00000000)
-#define ETH_ZeroQuantaPause_Disable                     ((u32)0x00000080)
-
-#define ETH_PauseLowThreshold_Minus4                    ((u32)0x00000000)              ///< Pause time minus 4 slot times
-#define ETH_PauseLowThreshold_Minus28                   ((u32)0x00000010)              ///< Pause time minus 28 slot times
-#define ETH_PauseLowThreshold_Minus144                  ((u32)0x00000020)              ///< Pause time minus 144 slot times
-#define ETH_PauseLowThreshold_Minus256                  ((u32)0x00000030)              ///< Pause time minus 256 slot times
-
-#define ETH_UnicastPauseFrameDetect_Enable              ((u32)0x00000008)
-#define ETH_UnicastPauseFrameDetect_Disable             ((u32)0x00000000)
-
-#define ETH_ReceiveFlowControl_Enable                   ((u32)0x00000004)
-#define ETH_ReceiveFlowControl_Disable                  ((u32)0x00000000)
-
-#define ETH_TransmitFlowControl_Enable                  ((u32)0x00000002)
-#define ETH_TransmitFlowControl_Disable                 ((u32)0x00000000)
-
-#define ETH_VLANTagComparison_12Bit                     ((u32)0x00010000)
-#define ETH_VLANTagComparison_16Bit                     ((u32)0x00000000)
-
-#define ETH_MAC_FLAG_TST                                ((u32)0x00000200)              ///< Time stamp trigger flag (on MAC)
-#define ETH_MAC_FLAG_MMCT                               ((u32)0x00000040)              ///< MMC transmit flag
-#define ETH_MAC_FLAG_MMCR                               ((u32)0x00000020)              ///< MMC receive flag
-#define ETH_MAC_FLAG_MMC                                ((u32)0x00000010)              ///< MMC flag (on MAC)
-#define ETH_MAC_FLAG_PMT                                ((u32)0x00000008)              ///< PMT flag (on MAC)
-
-#define ETH_MAC_IT_TST                                  ((u32)0x00000200)              ///< Time stamp trigger interrupt (on MAC)
-#define ETH_MAC_IT_MMCT                                 ((u32)0x00000040)              ///< MMC transmit interrupt
-#define ETH_MAC_IT_MMCR                                 ((u32)0x00000020)              ///< MMC receive interrupt
-#define ETH_MAC_IT_MMC                                  ((u32)0x00000010)              ///< MMC interrupt (on MAC)
-#define ETH_MAC_IT_PMT                                  ((u32)0x00000008)              ///< PMT interrupt (on MAC)
-
-#define ETH_MAC_Address0                                ((u32)0x00000000)
-#define ETH_MAC_Address1                                ((u32)0x00000008)
-#define ETH_MAC_Address2                                ((u32)0x00000010)
-#define ETH_MAC_Address3                                ((u32)0x00000018)
-
-#define ETH_MAC_AddressFilter_SA                        ((u32)0x00000000)
-#define ETH_MAC_AddressFilter_DA                        ((u32)0x00000008)
-
-#define ETH_MAC_AddressMask_Byte6                       ((u32)0x20000000)              ///< Mask MAC Address high reg bits [15:8]
-#define ETH_MAC_AddressMask_Byte5                       ((u32)0x10000000)              ///< Mask MAC Address high reg bits [7:0]
-#define ETH_MAC_AddressMask_Byte4                       ((u32)0x08000000)              ///< Mask MAC Address low reg bits [31:24]
-#define ETH_MAC_AddressMask_Byte3                       ((u32)0x04000000)              ///< Mask MAC Address low reg bits [23:16]
-#define ETH_MAC_AddressMask_Byte2                       ((u32)0x02000000)              ///< Mask MAC Address low reg bits [15:8]
-#define ETH_MAC_AddressMask_Byte1                       ((u32)0x01000000)              ///< Mask MAC Address low reg bits [70]
-
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMA_TDES_LastSegment                        ((u32)0x40000000)              ///< Last Segment
-#define ETH_DMA_TDES_FirstSegment                       ((u32)0x20000000)              ///< First Segment
-
-#define ETH_DMA_TDES_ChecksumByPass                     ((u32)0x00000000)      ///< Checksum engine bypass
-#define ETH_DMA_TDES_ChecksumIPV4Header                 ((u32)0x00400000)      ///< IPv4 header checksum insertion
-#define ETH_DMA_TDES_ChecksumTCPUDPICMPSegment          ((u32)0x00800000)      ///< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present
-#define ETH_DMA_TDES_ChecksumTCPUDPICMPFull             ((u32)0x00C00000)      ///< TCP/UDP/ICMP checksum fully in hardware including pseudo header
-
-#define ETH_DMA_RDES_Buffer1                            ((u32)0x00000000)              ///< DMA Rx Desc Buffer1
-#define ETH_DMA_RDES_Buffer2                            ((u32)0x00000001)              ///< DMA Rx Desc Buffer2
-
-#define ETH_DropTCPIPChecksumErrorFrame_Enable          ((u32)0x00000000)
-#define ETH_DropTCPIPChecksumErrorFrame_Disable         ((u32)0x04000000)
-
-#define ETH_ReceiveStoreForward_Enable                  ((u32)0x02000000)
-#define ETH_ReceiveStoreForward_Disable                 ((u32)0x00000000)
-
-#define ETH_FlushReceivedFrame_Enable                   ((u32)0x00000000)
-#define ETH_FlushReceivedFrame_Disable                  ((u32)0x01000000)
-
-#define ETH_TransmitStoreForward_Enable                 ((u32)0x00200000)
-#define ETH_TransmitStoreForward_Disable                ((u32)0x00000000)
-
-#define ETH_TransmitThresholdControl_64Bytes            ((u32)0x00000000)      ///< threshold level of the MTL Transmit FIFO is 64 Bytes
-#define ETH_TransmitThresholdControl_128Bytes           ((u32)0x00004000)      ///< threshold level of the MTL Transmit FIFO is 128 Bytes
-#define ETH_TransmitThresholdControl_192Bytes           ((u32)0x00008000)      ///< threshold level of the MTL Transmit FIFO is 192 Bytes
-#define ETH_TransmitThresholdControl_256Bytes           ((u32)0x0000C000)      ///< threshold level of the MTL Transmit FIFO is 256 Bytes
-#define ETH_TransmitThresholdControl_40Bytes            ((u32)0x00010000)      ///< threshold level of the MTL Transmit FIFO is 40 Bytes
-#define ETH_TransmitThresholdControl_32Bytes            ((u32)0x00014000)      ///< threshold level of the MTL Transmit FIFO is 32 Bytes
-#define ETH_TransmitThresholdControl_24Bytes            ((u32)0x00018000)      ///< threshold level of the MTL Transmit FIFO is 24 Bytes
-#define ETH_TransmitThresholdControl_16Bytes            ((u32)0x0001C000)      ///< threshold level of the MTL Transmit FIFO is 16 Bytes
-
-#define ETH_ForwardErrorFrames_Enable                   ((u32)0x00000080)
-#define ETH_ForwardErrorFrames_Disable                  ((u32)0x00000000)
-
-#define ETH_ForwardUndersizedGoodFrames_Enable          ((u32)0x00000040)
-#define ETH_ForwardUndersizedGoodFrames_Disable         ((u32)0x00000000)
-
-#define ETH_ReceiveThresholdControl_64Bytes             ((u32)0x00000000)      ///< threshold level of the MTL Receive FIFO is 64 Bytes
-#define ETH_ReceiveThresholdControl_32Bytes             ((u32)0x00000008)      ///< threshold level of the MTL Receive FIFO is 32 Bytes
-#define ETH_ReceiveThresholdControl_96Bytes             ((u32)0x00000010)      ///< threshold level of the MTL Receive FIFO is 96 Bytes
-#define ETH_ReceiveThresholdControl_128Bytes            ((u32)0x00000018)      ///< threshold level of the MTL Receive FIFO is 128 Bytes
-
-#define ETH_SecondFrameOperate_Enable       ((u32)0x00000004)
-#define ETH_SecondFrameOperate_Disable      ((u32)0x00000000)
-
-#define ETH_AddressAlignedBeats_Enable      ((u32)0x02000000)
-#define ETH_AddressAlignedBeats_Disable     ((u32)0x00000000)
-
-#define ETH_FixedBurst_Enable               ((u32)0x00010000)
-#define ETH_FixedBurst_Disable              ((u32)0x00000000)
-
-#define ETH_RxDMABurstLength_1Beat          ((u32)0x00020000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 1
-#define ETH_RxDMABurstLength_2Beat          ((u32)0x00040000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 2
-#define ETH_RxDMABurstLength_4Beat          ((u32)0x00080000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 4
-#define ETH_RxDMABurstLength_8Beat          ((u32)0x00100000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 8
-#define ETH_RxDMABurstLength_16Beat         ((u32)0x00200000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 16
-#define ETH_RxDMABurstLength_32Beat         ((u32)0x00400000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 32
-#define ETH_RxDMABurstLength_4xPBL_4Beat    ((u32)0x01020000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 4
-#define ETH_RxDMABurstLength_4xPBL_8Beat    ((u32)0x01040000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 8
-#define ETH_RxDMABurstLength_4xPBL_16Beat   ((u32)0x01080000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 16
-#define ETH_RxDMABurstLength_4xPBL_32Beat   ((u32)0x01100000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 32
-#define ETH_RxDMABurstLength_4xPBL_64Beat   ((u32)0x01200000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 64
-#define ETH_RxDMABurstLength_4xPBL_128Beat  ((u32)0x01400000)              ///< maximum number of beats to be transferred in one RxDMA transaction is 128
-
-#define ETH_TxDMABurstLength_1Beat          ((u32)0x00000100)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1
-#define ETH_TxDMABurstLength_2Beat          ((u32)0x00000200)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2
-#define ETH_TxDMABurstLength_4Beat          ((u32)0x00000400)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
-#define ETH_TxDMABurstLength_8Beat          ((u32)0x00000800)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
-#define ETH_TxDMABurstLength_16Beat         ((u32)0x00001000)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
-#define ETH_TxDMABurstLength_32Beat         ((u32)0x00002000)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
-#define ETH_TxDMABurstLength_4xPBL_4Beat    ((u32)0x01000100)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4
-#define ETH_TxDMABurstLength_4xPBL_8Beat    ((u32)0x01000200)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8
-#define ETH_TxDMABurstLength_4xPBL_16Beat   ((u32)0x01000400)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16
-#define ETH_TxDMABurstLength_4xPBL_32Beat   ((u32)0x01000800)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32
-#define ETH_TxDMABurstLength_4xPBL_64Beat   ((u32)0x01001000)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64
-#define ETH_TxDMABurstLength_4xPBL_128Beat  ((u32)0x01002000)              ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128
-
-#define ETH_DMAArbitration_RoundRobin_RxTx_1_1      ((u32)0x00000000)
-#define ETH_DMAArbitration_RoundRobin_RxTx_2_1      ((u32)0x00004000)
-#define ETH_DMAArbitration_RoundRobin_RxTx_3_1      ((u32)0x00008000)
-#define ETH_DMAArbitration_RoundRobin_RxTx_4_1      ((u32)0x0000C000)
-#define ETH_DMAArbitration_RxPriorTx                ((u32)0x00000002)
-
-#define ETH_DMA_FLAG_TST                    ((u32)0x20000000)              ///< Time-stamp trigger interrupt (on DMA)
-#define ETH_DMA_FLAG_PMT                    ((u32)0x10000000)              ///< PMT interrupt (on DMA)
-#define ETH_DMA_FLAG_MMC                    ((u32)0x08000000)              ///< MMC interrupt (on DMA)
-#define ETH_DMA_FLAG_DataTransferError      ((u32)0x00800000)              ///< Error bits 0-Rx DMA, 1-Tx DMA
-#define ETH_DMA_FLAG_ReadWriteError         ((u32)0x01000000)              ///< Error bits 0-write trnsf, 1-read transfr
-#define ETH_DMA_FLAG_AccessError            ((u32)0x02000000)              ///< Error bits 0-data buffer, 1-desc. access
-#define ETH_DMA_FLAG_NIS                    ((u32)0x00010000)              ///< Normal interrupt summary flag
-#define ETH_DMA_FLAG_AIS                    ((u32)0x00008000)              ///< Abnormal interrupt summary flag
-#define ETH_DMA_FLAG_ER                     ((u32)0x00004000)              ///< Early receive flag
-#define ETH_DMA_FLAG_FBE                    ((u32)0x00002000)              ///< Fatal bus error flag
-#define ETH_DMA_FLAG_ET                     ((u32)0x00000400)              ///< Early transmit flag
-#define ETH_DMA_FLAG_RWT                    ((u32)0x00000200)              ///< Receive watchdog timeout flag
-#define ETH_DMA_FLAG_RPS                    ((u32)0x00000100)              ///< Receive process stopped flag
-#define ETH_DMA_FLAG_RBU                    ((u32)0x00000080)              ///< Receive buffer unavailable flag
-#define ETH_DMA_FLAG_R                      ((u32)0x00000040)              ///< Receive flag
-#define ETH_DMA_FLAG_TU                     ((u32)0x00000020)              ///< Underflow flag
-#define ETH_DMA_FLAG_RO                     ((u32)0x00000010)              ///< Overflow flag
-#define ETH_DMA_FLAG_TJT                    ((u32)0x00000008)              ///< Transmit jabber timeout flag
-#define ETH_DMA_FLAG_TBU                    ((u32)0x00000004)              ///< Transmit buffer unavailable flag
-#define ETH_DMA_FLAG_TPS                    ((u32)0x00000002)              ///< Transmit process stopped flag
-#define ETH_DMA_FLAG_T                      ((u32)0x00000001)              ///< Transmit flag
-
-#define ETH_DMA_IT_TST                      ((u32)0x20000000)              ///< Time-stamp trigger interrupt (on DMA)
-#define ETH_DMA_IT_PMT                      ((u32)0x10000000)              ///< PMT interrupt (on DMA)
-#define ETH_DMA_IT_MMC                      ((u32)0x08000000)              ///< MMC interrupt (on DMA)
-#define ETH_DMA_IT_NIS                      ((u32)0x00010000)              ///< Normal interrupt summary
-#define ETH_DMA_IT_AIS                      ((u32)0x00008000)              ///< Abnormal interrupt summary
-#define ETH_DMA_IT_ER                       ((u32)0x00004000)              ///< Early receive interrupt
-#define ETH_DMA_IT_FBE                      ((u32)0x00002000)              ///< Fatal bus error interrupt
-#define ETH_DMA_IT_ET                       ((u32)0x00000400)              ///< Early transmit interrupt
-#define ETH_DMA_IT_RWT                      ((u32)0x00000200)              ///< Receive watchdog timeout interrupt
-#define ETH_DMA_IT_RPS                      ((u32)0x00000100)              ///< Receive process stopped interrupt
-#define ETH_DMA_IT_RBU                      ((u32)0x00000080)              ///< Receive buffer unavailable interrupt
-#define ETH_DMA_IT_R                        ((u32)0x00000040)              ///< Receive interrupt
-#define ETH_DMA_IT_TU                       ((u32)0x00000020)              ///< Underflow interrupt
-#define ETH_DMA_IT_RO                       ((u32)0x00000010)              ///< Overflow interrupt
-#define ETH_DMA_IT_TJT                      ((u32)0x00000008)              ///< Transmit jabber timeout interrupt
-#define ETH_DMA_IT_TBU                      ((u32)0x00000004)              ///< Transmit buffer unavailable interrupt
-#define ETH_DMA_IT_TPS                      ((u32)0x00000002)              ///< Transmit process stopped interrupt
-#define ETH_DMA_IT_T                        ((u32)0x00000001)              ///< Transmit interrupt
-
-#define ETH_DMA_TransmitProcess_Stopped     ((u32)0x00000000)              ///< Stopped - Reset or Stop Tx Command issued
-#define ETH_DMA_TransmitProcess_Fetching    ((u32)0x00100000)              ///< Running - fetching the Tx descriptor
-#define ETH_DMA_TransmitProcess_Waiting     ((u32)0x00200000)              ///< Running - waiting for status
-#define ETH_DMA_TransmitProcess_Reading     ((u32)0x00300000)              ///< Running - reading the data from host memory
-#define ETH_DMA_TransmitProcess_Suspended   ((u32)0x00600000)              ///< Suspended - Tx Descriptor unavailable
-#define ETH_DMA_TransmitProcess_Closing     ((u32)0x00700000)              ///< Running - closing Rx descriptor
-
-#define ETH_DMA_ReceiveProcess_Stopped      ((u32)0x00000000)              ///< Stopped - Reset or Stop Rx Command issued
-#define ETH_DMA_ReceiveProcess_Fetching     ((u32)0x00020000)              ///< Running - fetching the Rx descriptor
-#define ETH_DMA_ReceiveProcess_Waiting      ((u32)0x00060000)              ///< Running - waiting for packet
-#define ETH_DMA_ReceiveProcess_Suspended    ((u32)0x00080000)              ///< Suspended - Rx Descriptor unavailable
-#define ETH_DMA_ReceiveProcess_Closing      ((u32)0x000A0000)              ///< Running - closing descriptor
-#define ETH_DMA_ReceiveProcess_Queuing      ((u32)0x000E0000)              ///< Running - queuing the receive frame into host memory
-
-#define ETH_DMA_Overflow_RxFIFOCounter      ((u32)0x10000000)              ///< Overflow bit for FIFO overflow counter
-#define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000)              ///< Overflow bit for missed frame counter
-
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_PMT_FLAG_WUFFRPR                ((u32)0x80000000)              ///< Wake-Up Frame Filter Register Pointer Reset
-#define ETH_PMT_FLAG_WUFR                   ((u32)0x00000040)              ///< Wake-Up Frame Received
-#define ETH_PMT_FLAG_MPR                    ((u32)0x00000020)              ///< Magic Packet Received
-
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMC_IT_TGF                      ((u32)0x00200000)              ///< When Tx good frame counter reaches half the maximum value
-#define ETH_MMC_IT_TGFMSC                   ((u32)0x00008000)              ///< When Tx good multi col counter reaches half the maximum value
-#define ETH_MMC_IT_TGFSC                    ((u32)0x00004000)              ///< When Tx good single col counter reaches half the maximum value
-
-#define ETH_MMC_IT_RGUF                     ((u32)0x10020000)              ///< When Rx good unicast frames counter reaches half the maximum value
-#define ETH_MMC_IT_RFAE                     ((u32)0x10000040)              ///< When Rx alignment error counter reaches half the maximum value
-#define ETH_MMC_IT_RFCE                     ((u32)0x10000020)              ///< When Rx crc error counter reaches half the maximum value
-
-#define ETH_MMCCR                           ((u32)0x00000100)              ///< MMC CR register
-#define ETH_MMCRIR                          ((u32)0x00000104)              ///< MMC RIR register
-#define ETH_MMCTIR                          ((u32)0x00000108)              ///< MMC TIR register
-#define ETH_MMCRIMR                         ((u32)0x0000010C)              ///< MMC RIMR register
-#define ETH_MMCTIMR                         ((u32)0x00000110)              ///< MMC TIMR register
-#define ETH_MMCTGFSCCR                      ((u32)0x0000014C)              ///< MMC TGFSCCR register
-#define ETH_MMCTGFMSCCR                     ((u32)0x00000150)              ///< MMC TGFMSCCR register
-#define ETH_MMCTGFCR                        ((u32)0x00000168)              ///< MMC TGFCR register
-#define ETH_MMCRFCECR                       ((u32)0x00000194)              ///< MMC RFCECR register
-#define ETH_MMCRFAECR                       ((u32)0x00000198)              ///< MMC RFAECR register
-#define ETH_MMCRGUFCR                       ((u32)0x000001C4)              ///< MMC RGUFCR register
-
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_PTP_FineUpdate                  ((u32)0x00000001)              ///< Fine Update method
-#define ETH_PTP_CoarseUpdate                ((u32)0x00000000)              ///< Coarse Update method
-
-#define ETH_PTP_FLAG_TSARU                  ((u32)0x00000020)              ///< Addend Register Update
-#define ETH_PTP_FLAG_TSITE                  ((u32)0x00000010)              ///< Time Stamp Interrupt Trigger
-#define ETH_PTP_FLAG_TSSTU                  ((u32)0x00000008)              ///< Time Stamp Update
-#define ETH_PTP_FLAG_TSSTI                  ((u32)0x00000004)              ///< Time Stamp Initialize
-
-#define ETH_PTP_FLAG_TSTTR                  ((u32)0x10000002)              ///< Time stamp target time reached
-#define ETH_PTP_FLAG_TSSO                   ((u32)0x10000001)              ///< Time stamp seconds overflow
-
-#define ETH_PTP_PositiveTime                ((u32)0x00000000)              ///< Positive time value
-#define ETH_PTP_NegativeTime                ((u32)0x80000000)              ///< Negative time value
-
-#define ETH_PTPTSCR                         ((u32)0x00000700)              ///< PTP TSCR register
-#define ETH_PTPSSIR                         ((u32)0x00000704)              ///< PTP SSIR register
-#define ETH_PTPTSHR                         ((u32)0x00000708)              ///< PTP TSHR register
-#define ETH_PTPTSLR                         ((u32)0x0000070C)              ///< PTP TSLR register
-#define ETH_PTPTSHUR                        ((u32)0x00000710)              ///< PTP TSHUR register
-#define ETH_PTPTSLUR                        ((u32)0x00000714)              ///< PTP TSLUR register
-#define ETH_PTPTSAR                         ((u32)0x00000718)              ///< PTP TSAR register
-#define ETH_PTPTTHR                         ((u32)0x0000071C)              ///< PTP TTHR register
-#define ETH_PTPTTLR                         ((u32)0x00000720)              ///< PTP TTLR register
-
-#define ETH_PTPTSSR                         ((u32)0x00000728)              ///< PTP TSSR register
-
-#define ETH_PTP_OrdinaryClock               ((u32)0x00000000)              ///< Ordinary Clock
-#define ETH_PTP_BoundaryClock               ((u32)0x00010000)              ///< Boundary Clock
-#define ETH_PTP_EndToEndTransparentClock    ((u32)0x00020000)              ///< End To End Transparent Clock
-#define ETH_PTP_PeerToPeerTransparentClock  ((u32)0x00030000)              ///< Peer To Peer Transparent Clock
-
-#define ETH_PTP_SnapshotMasterMessage               ((u32)0x00008000)      ///< Time stamp snapshot for message relevant to master enable
-#define ETH_PTP_SnapshotEventMessage                ((u32)0x00004000)      ///< Time stamp snapshot for event message enable
-#define ETH_PTP_SnapshotIPV4Frames                  ((u32)0x00002000)      ///< Time stamp snapshot for IPv4 frames enable
-#define ETH_PTP_SnapshotIPV6Frames                  ((u32)0x00001000)      ///< Time stamp snapshot for IPv6 frames enable
-#define ETH_PTP_SnapshotPTPOverEthernetFrames       ((u32)0x00000800)      ///< Time stamp snapshot for PTP over ethernet frames enable
-#define ETH_PTP_SnapshotAllReceivedFrames           ((u32)0x00000100)      ///< Time stamp snapshot for all received frames enable
-
-#define ETH_MAC_ADDR_HBASE      (ETH_BASE + 0x40)                               ///< ETHERNET MAC address high offset
-#define ETH_MAC_ADDR_LBASE      (ETH_BASE + 0x44)                               ///< ETHERNET MAC address low offset
-
-#define MACMIIAR_CR_MASK    ((u32)0xFFFFFFE3)
-
-#define MACCR_CLEAR_MASK    ((u32)0xFF20810F)
-#define MACFCR_CLEAR_MASK   ((u32)0x0000FF41)
-#define DMAOMR_CLEAR_MASK   ((u32)0xF8DE3F23)
-
-
-
-GLOBAL __IO ETH_DMADESCTypeDef*  DMATxDescToSet;
-GLOBAL __IO ETH_DMADESCTypeDef*  DMARxDescToGet;
-
-GLOBAL ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor;
-GLOBAL __IO ETH_DMA_Rx_Frame_infos* DMA_RX_FRAME_infos;
-GLOBAL __IO u32 Frame_Rx_index;
-
-#undef GLOBAL
-
-void ETH_DeInit(void);
-void ETH_StructInit(ETH_InitTypeDef* ptr);
-u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr);
-void ETH_Start(void);
-void ETH_Stop(void);
-void ETH_MACTransmissionCmd(FunctionalState sta);
-void ETH_MACReceptionCmd(FunctionalState sta);
-FlagStatus ETH_GetFlowControlBusyStatus(void);
-void ETH_InitiatePauseControlFrame(void);
-void ETH_BackPressureActivationCmd(FunctionalState sta);
-void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr);
-void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr);
-void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta);
-void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta);
-void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte);
-FrameTypeDef ETH_Get_Received_Frame(void);
-FrameTypeDef ETH_Get_Received_Frame_interrupt(void);
-u32 ETH_Prepare_Transmit_Descriptors(u16 len);
-void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt);
-u32 ETH_CheckFrameReceived(void);
-void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt);
-FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag);
-u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc);
-void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc);
-void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
-void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val);
-void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val);
-void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
-void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
-void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
-void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size);
-FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag);
-void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc);
-u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc);
-void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta);
-u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf);
-u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc);
-void ETH_SoftwareReset(void);
-FlagStatus ETH_GetSoftwareResetStatus(void);
-FlagStatus ETH_GetDMAFlagStatus(u32 flag);
-void ETH_DMAClearFlag(u32 flag);
-void ETH_DMAITConfig(u32 it, FunctionalState sta);
-ITStatus ETH_GetDMAITStatus(u32 it);
-void ETH_DMAClearITPendingBit(u32 it);
-u32 ETH_GetTransmitProcessState(void);
-u32 ETH_GetReceiveProcessState(void);
-void ETH_FlushTransmitFIFO(void);
-FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
-void ETH_DMATransmissionCmd(FunctionalState sta);
-void ETH_DMAReceptionCmd(FunctionalState sta);
-FlagStatus ETH_GetDMAOverflowStatus(u32 val);
-u32 ETH_GetRxOverflowMissedFrameCounter(void);
-u32 ETH_GetBufferUnavailableMissedFrameCounter(void);
-u32 ETH_GetCurrentTxDescStartAddress(void);
-u32 ETH_GetCurrentRxDescStartAddress(void);
-u32 ETH_GetCurrentTxBufferAddress(void);
-u32 ETH_GetCurrentRxBufferAddress(void);
-void ETH_ResumeDMATransmission(void);
-void ETH_ResumeDMAReception(void);
-void ETH_SetReceiveWatchdogTimer(u8 val);
-u16 ETH_ReadPHYRegister(u16 addr, u16 reg);
-u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val);
-u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta);
-void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
-void ETH_SetWakeUpFrameFilterRegister(u32* buf);
-void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta);
-FlagStatus ETH_GetPMTFlagStatus(u32 flag);
-void ETH_WakeUpFrameDetectionCmd(FunctionalState sta);
-void ETH_MagicPacketDetectionCmd(FunctionalState sta);
-void ETH_PowerDownCmd(FunctionalState sta);
-void ETH_MMCCounterFullPreset(void);
-void ETH_MMCCounterHalfPreset(void);
-void ETH_MMCCounterFreezeCmd(FunctionalState sta);
-void ETH_MMCResetOnReadCmd(FunctionalState sta);
-void ETH_MMCCounterRolloverCmd(FunctionalState sta);
-void ETH_MMCCountersReset(void);
-void ETH_MMCITConfig(u32 it, FunctionalState sta);
-ITStatus ETH_GetMMCITStatus(u32 it);
-u32 ETH_GetMMCRegister(u32 reg);
-
-/// @}
-
-/// @}
-
-/// @}
-////////////////////////////////////////////////////////////////////////////////
-#endif //__HAL_ETH_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h
deleted file mode 100644
index f00e17e63..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_eth_conf.h
+++ /dev/null
@@ -1,68 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_eth_conf.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE hal_eth_conf.h EXAMPLES.
-/// ////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT  MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-#ifndef __HAL_ETH_CONF_H
-#define __HAL_ETH_CONF_H
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup ETH_HAL
-/// @brief ETH HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup ETH_Exported_Types
-/// @{
-
-
-// #define USE_ENHANCED_DMA_DESCRIPTORS
-// #define CUSTOM_DRIVER_BUFFERS_CONFIG
-#define DP83848
-
-#ifdef CUSTOM_DRIVER_BUFFERS_CONFIG
-#define ETH_RX_BUF_SIZE     ETH_MAX_PACKET_SIZE
-#define ETH_TX_BUF_SIZE     ETH_MAX_PACKET_SIZE
-#define ETH_RX_BUF_NUM      4
-#define ETH_TX_BUF_NUM      4
-#endif
-
-////////////////////////////////////////////////////////////////////////////////
-#if defined(DP83848)
-#define PHY_SR                  ((u16)0x10)
-#define PHY_SR_LINKSTATUS       ((u16)0x0001)
-#define PHY_SPEED_STATUS        ((u16)0x0002)
-#define PHY_DUPLEX_STATUS       ((u16)0x0004)
-
-#define PHY_MICR                ((u16)0x11)
-#define PHY_MICR_INT_EN         ((u16)0x0002)
-#define PHY_MICR_INT_OE         ((u16)0x0001)
-
-#define PHY_MISR                ((u16)0x12)
-#define PHY_MISR_LINK_INT_EN    ((u16)0x0020)
-#define PHY_LINK_STATUS         ((u16)0x2000)
-#endif
-
-/// @}
-
-/// @}
-
-/// @}
-////////////////////////////////////////////////////////////////////////////////
-#endif //__HAL_ETH_CONF_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h
deleted file mode 100644
index a90daff9c..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_exti.h
+++ /dev/null
@@ -1,181 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_exti.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_EXTI_H
-#define __HAL_EXTI_H
-
-// Files includes
-#include "types.h"
-#include "reg_common.h"
-#include "reg_exti.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup EXTI_HAL
-/// @brief EXTI HAL modules
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup EXTI_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  EXTI mode enumeration
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    EXTI_Mode_Interrupt = 0x00,                                                 ///< EXTI interrupt mode
-    EXTI_Mode_Event     = 0x04                                                  ///< EXTI event mode
-} EXTIMode_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  EXTI Trigger enumeration
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    EXTI_Trigger_Rising = 0x08,                                                 ///< EXTI rising edge triggering
-    EXTI_Trigger_Falling = 0x0C,                                                ///< EXTI falling edge triggering
-    EXTI_Trigger_Rising_Falling = 0x10                                          ///< EXTI rising and falling edge triggers
-} EXTITrigger_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  EXTI Init Structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u32 EXTI_Line;                                                              ///< Specifies the EXTI lines to be enabled or disabled.
-    ///< This parameter can be any combination of @ref EXTI_Lines
-    EXTIMode_TypeDef EXTI_Mode;                                                 ///< Specifies the mode for the EXTI lines.
-    ///< This parameter can be a value of @ref EXTIMode_TypeDef
-    EXTITrigger_TypeDef EXTI_Trigger;                                           ///< Specifies the trigger signal active edge for the EXTI lines.
-    ///< This parameter can be a value of @ref EXTIMode_TypeDef
-    FunctionalState EXTI_LineCmd;                                               ///< Specifies the new state of the selected EXTI lines.
-    ///< This parameter can be set either to ENABLE or DISABLE
-} EXTI_InitTypeDef;
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup EXTI_Exported_Constants
-/// @{
-
-
-
-#define EXTI_LineNone   ((u32)0x0000000)                                        ///< No interrupt selected
-#define EXTI_Line0      ((u32)0x0000001)                                        ///< External interrupt line 0
-#define EXTI_Line1      ((u32)0x0000002)                                        ///< External interrupt line 1
-#define EXTI_Line2      ((u32)0x0000004)                                        ///< External interrupt line 2
-#define EXTI_Line3      ((u32)0x0000008)                                        ///< External interrupt line 3
-#define EXTI_Line4      ((u32)0x0000010)                                        ///< External interrupt line 4
-#define EXTI_Line5      ((u32)0x0000020)                                        ///< External interrupt line 5
-#define EXTI_Line6      ((u32)0x0000040)                                        ///< External interrupt line 6
-#define EXTI_Line7      ((u32)0x0000080)                                        ///< External interrupt line 7
-#define EXTI_Line8      ((u32)0x0000100)                                        ///< External interrupt line 8
-#define EXTI_Line9      ((u32)0x0000200)                                        ///< External interrupt line 9
-#define EXTI_Line10     ((u32)0x0000400)                                        ///< External interrupt line 10
-#define EXTI_Line11     ((u32)0x0000800)                                        ///< External interrupt line 11
-#define EXTI_Line12     ((u32)0x0001000)                                        ///< External interrupt line 12
-#define EXTI_Line13     ((u32)0x0002000)                                        ///< External interrupt line 13
-#define EXTI_Line14     ((u32)0x0004000)                                        ///< External interrupt line 14
-#define EXTI_Line15     ((u32)0x0008000)                                        ///< External interrupt line 15
-#define EXTI_Line16     ((u32)0x0010000)                                        ///< External interrupt line 16 Connected to the PVD Output
-#define EXTI_Line17     ((u32)0x0020000)                                        ///< External interrupt line 17 Connected to the RTC Alarm event
-#define EXTI_Line18     ((u32)0x0040000)                                        ///< External interrupt line 18 Connected to the USB Wakeup from suspend event
-#define EXTI_Line19     ((u32)0x0080000)                                        ///< External interrupt line 19
-#define EXTI_Line20     ((u32)0x0100000)                                        ///< External interrupt line 20
-#define EXTI_Line21     ((u32)0x0200000)                                        ///< External interrupt line 21
-#define EXTI_Line22     ((u32)0x0400000)                                        ///< External interrupt line 22
-#define EXTI_Line23     ((u32)0x0800000)                                        ///< External interrupt line 23
-#define EXTI_Line24     ((u32)0x1000000)                                        ///< External interrupt line 24
-
-#define EXTI_PortSourceGPIOA (0x00U)
-#define EXTI_PortSourceGPIOB (0x01U)
-#define EXTI_PortSourceGPIOC (0x02U)
-#define EXTI_PortSourceGPIOD (0x03U)
-#define EXTI_PortSourceGPIOE (0x04U)
-#define EXTI_PortSourceGPIOF (0x05U)
-
-#define EXTI_PinSource0     (0x00U)
-#define EXTI_PinSource1     (0x01U)
-#define EXTI_PinSource2     (0x02U)
-#define EXTI_PinSource3     (0x03U)
-#define EXTI_PinSource4     (0x04U)
-#define EXTI_PinSource5     (0x05U)
-#define EXTI_PinSource6     (0x06U)
-#define EXTI_PinSource7     (0x07U)
-#define EXTI_PinSource8     (0x08U)
-#define EXTI_PinSource9     (0x09U)
-#define EXTI_PinSource10    (0x0AU)
-#define EXTI_PinSource11    (0x0BU)
-#define EXTI_PinSource12    (0x0CU)
-#define EXTI_PinSource13    (0x0DU)
-#define EXTI_PinSource14    (0x0EU)
-#define EXTI_PinSource15    (0x0FU)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup EXTI_Exported_Variables
-/// @{
-
-#ifdef _HAL_EXTI_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup EXTI_Exported_Functions
-/// @{
-
-FlagStatus EXTI_GetFlagStatus(u32 line);
-ITStatus   EXTI_GetITStatus(u32 line);
-
-void EXTI_DeInit(void);
-void EXTI_Init(EXTI_InitTypeDef* init_struct);
-void EXTI_StructInit(EXTI_InitTypeDef* init_struct);
-void EXTI_GenerateSWInterrupt(u32 line);
-void EXTI_ClearFlag(u32 line);
-void EXTI_ClearITPendingBit(u32 line);
-void exEXTI_LineDisable(u32 line);
-u32  exEXTI_GetAllFlagStatus(void);
-
-
-void EXTI_MemoryRemapConfig(u32 memory_remap);
-void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source);
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_EXTI_H
-////////////////////////////////////////////////////////////////////////////////
-
-
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h
deleted file mode 100644
index ee313dee7..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_flash.h
+++ /dev/null
@@ -1,230 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_flash.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE FLASH
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_FLASH_H
-#define __HAL_FLASH_H
-
-// Files includes
-#include "types.h"
-#include "reg_common.h"
-#include "reg_flash.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup FLASH_HAL
-/// @brief FLASH HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup FLASH_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  FLASH Status
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    FLASH_BUSY = 1,                                                             ///< FLASH busy status
-    FLASH_ERROR_PG,                                                             ///< FLASH programming error status
-    FLASH_ERROR_WRP,                                                            ///< FLASH write protection error status
-    FLASH_COMPLETE,                                                             ///< FLASH end of operation status
-    FLASH_TIMEOUT                                                               ///< FLASH Last operation timed out status
-} FLASH_Status;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  FLASH Latency
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    FLASH_Latency_0 = FLASH_ACR_LATENCY_0,                                      ///< FLASH Zero Latency cycle
-    FLASH_Latency_1 = FLASH_ACR_LATENCY_1,                                      ///< FLASH One Latency cycle
-    FLASH_Latency_2 = FLASH_ACR_LATENCY_2,                                      ///< FLASH Two Latency cycles
-    FLASH_Latency_3 = FLASH_ACR_LATENCY_3                                       ///< FLASH Three Latency cycles
-} FLASH_Latency_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Half_Cycle_Enable_Disable
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    FLASH_HalfCycleAccess_Enable  = FLASH_ACR_HLFCYA,                           ///< FLASH Half Cycle Enable
-    FLASH_HalfCycleAccess_Disable = (s32)~FLASH_ACR_HLFCYA                              ///< FLASH Half Cycle Disable
-} FLASH_HalfCycleAccess_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Prefetch_Buffer_Enable_Disable
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    FLASH_PrefetchBuffer_Enable  = FLASH_ACR_PRFTBE,                            ///< FLASH Prefetch Buffer Enable
-    FLASH_PrefetchBuffer_Disable = (s32)~FLASH_ACR_PRFTBE                           ///< FLASH Prefetch Buffer Disable
-} FLASH_PrefetchBuffer_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Option_Bytes_IWatchdog
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    OB_IWDG_SW = 0x0001,                                                        ///< Software IWDG selected
-    OB_IWDG_HW = 0x0000                                                         ///< Hardware IWDG selected
-} OB_IWDG_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Option_Bytes_nRST_STOP
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    OB_STOP_NoRST = 0x0002,                                                     ///< No reset generated when entering in STOP
-    OB_STOP_RST   = 0x0000                                                      ///< Reset generated when entering in STOP
-} OB_STOP_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Option_Bytes_nRST_STDBY
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    OB_STDBY_NoRST = 0x0004,                                                    ///< No reset generated when entering in STANDBY
-    OB_STDBY_RST   = 0x0000                                                     ///< Reset generated when entering in STANDBY
-} OB_STDBY_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  FLASH_Interrupts
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    FLASH_IT_ERROR = FLASH_CR_ERRIE,                                            ///< FPEC error interrupt source
-    FLASH_IT_EOP   = FLASH_CR_EOPIE                                             ///< End of FLASH Operation Interrupt source
-} FLASH_IT_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  FLASH_Flags
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    FLASH_FLAG_EOP      = FLASH_SR_EOP,                                         ///< FLASH End of Operation flag
-    FLASH_FLAG_PGERR    = FLASH_SR_PGERR,                                       ///< FLASH Program error flag
-    FLASH_FLAG_WRPRTERR = FLASH_SR_WRPRTERR,                                    ///< FLASH Write protected error flag
-    FLASH_FLAG_BSY      = FLASH_SR_BUSY,                                        ///< FLASH Busy flag
-    FLASH_FLAG_OPTERR   = FLASH_OBR_OPTERR                                      ///< FLASH Option Byte error flag
-} FLASH_FLAG_TypeDef;
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup FLASH_Exported_Constants
-/// @{
-
-
-#define RDP_Key ((u16)0x00A5)
-#define FLASH_KEY1 ((u32)0x45670123)
-#define FLASH_KEY2 ((u32)0xCDEF89AB)
-#define EraseTimeout ((u32)0x00000FFF)
-#define ProgramTimeout ((u32)0x0000000F)
-
-#define FLASH_WRProt_Pages0to3      ((u32)0x00000001)  ///< Write protection of page 0 to 3
-#define FLASH_WRProt_Pages4to7      ((u32)0x00000002)  ///< Write protection of page 4 to 7
-#define FLASH_WRProt_Pages8to11     ((u32)0x00000004)  ///< Write protection of page 8 to 11
-#define FLASH_WRProt_Pages12to15    ((u32)0x00000008)  ///< Write protection of page 12 to 15
-#define FLASH_WRProt_Pages16to19    ((u32)0x00000010)  ///< Write protection of page 16 to 19
-#define FLASH_WRProt_Pages20to23    ((u32)0x00000020)  ///< Write protection of page 20 to 23
-#define FLASH_WRProt_Pages24to27    ((u32)0x00000040)  ///< Write protection of page 24 to 27
-#define FLASH_WRProt_Pages28to31    ((u32)0x00000080)  ///< Write protection of page 28 to 31
-#define FLASH_WRProt_Pages32to35    ((u32)0x00000100)  ///< Write protection of page 32 to 35
-#define FLASH_WRProt_Pages36to39    ((u32)0x00000200)  ///< Write protection of page 36 to 39
-#define FLASH_WRProt_Pages40to43    ((u32)0x00000400)  ///< Write protection of page 40 to 43
-#define FLASH_WRProt_Pages44to47    ((u32)0x00000800)  ///< Write protection of page 44 to 47
-#define FLASH_WRProt_Pages48to51    ((u32)0x00001000)  ///< Write protection of page 48 to 51
-#define FLASH_WRProt_Pages52to55    ((u32)0x00002000)  ///< Write protection of page 52 to 55
-#define FLASH_WRProt_Pages56to59    ((u32)0x00004000)  ///< Write protection of page 56 to 59
-#define FLASH_WRProt_Pages60to63    ((u32)0x00008000)  ///< Write protection of page 60 to 63
-#define FLASH_WRProt_Pages64to67    ((u32)0x00010000)  ///< Write protection of page 64 to 67
-#define FLASH_WRProt_Pages68to71    ((u32)0x00020000)  ///< Write protection of page 68 to 71
-#define FLASH_WRProt_Pages72to75    ((u32)0x00040000)  ///< Write protection of page 72 to 75
-#define FLASH_WRProt_Pages76to79    ((u32)0x00080000)  ///< Write protection of page 76 to 79
-#define FLASH_WRProt_Pages80to83    ((u32)0x00100000)  ///< Write protection of page 80 to 83
-#define FLASH_WRProt_Pages84to87    ((u32)0x00200000)  ///< Write protection of page 84 to 87
-#define FLASH_WRProt_Pages88to91    ((u32)0x00400000)  ///< Write protection of page 88 to 91
-#define FLASH_WRProt_Pages92to95    ((u32)0x00800000)  ///< Write protection of page 92 to 95
-#define FLASH_WRProt_Pages96to99    ((u32)0x01000000)  ///< Write protection of page 96 to 99
-#define FLASH_WRProt_Pages100to103  ((u32)0x02000000)  ///< Write protection of page 100 to 103
-#define FLASH_WRProt_Pages104to107  ((u32)0x04000000)  ///< Write protection of page 104 to 107
-#define FLASH_WRProt_Pages108to111  ((u32)0x08000000)  ///< Write protection of page 108 to 111
-#define FLASH_WRProt_Pages112to115  ((u32)0x10000000)  ///< Write protection of page 112 to 115
-#define FLASH_WRProt_Pages116to119  ((u32)0x20000000)  ///< Write protection of page 115 to 119
-#define FLASH_WRProt_Pages120to123  ((u32)0x40000000)  ///< Write protection of page 120 to 123
-#define FLASH_WRProt_Pages124to127  ((u32)0x80000000)  ///< Write protection of page 124 to 127
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup FLASH_Exported_Variables
-/// @{
-
-#ifdef _HAL_FLASH_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup FLASH_Exported_Functions
-/// @{
-void  FLASH_SetLatency(FLASH_Latency_TypeDef latency);
-void  FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access);
-void  FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer);
-void  FLASH_Unlock(void);
-void  FLASH_Lock(void);
-void  FLASH_OPTB_Enable(void);
-void  FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state);
-void  FLASH_ClearFlag(u16 flag);
-void  exFLASH_EraseEE(u32 page_address);
-void  exFLASH_ProgramEE(u16* buf, u32 address, u16 len);
-void  exFLASH_WriteEE(u16* buf, u32 page_address, u16 len);
-void* exFLASH_Locate(u32 page_address, u16 len);
-void* exFLASH_ReadEE(u32 page_address, u16 len);
-
-u8  exFLASH_FindEmpty(u16* ptr, u16 len);
-u32 FLASH_GetUserOptionByte(void);
-u32 FLASH_GetWriteProtectionOptionByte(void);
-
-FLASH_Status FLASH_ErasePage(u32 page_address);
-FLASH_Status FLASH_EraseAllPages(void);
-FLASH_Status FLASH_EraseOptionBytes(void);
-FLASH_Status FLASH_EraseProtect(void);
-FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data);
-FLASH_Status FLASH_ProgramWord(u32 address, u32 data);
-FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data);
-FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data);
-FLASH_Status FLASH_ProgramProtect(u32 address, u16 data);
-FLASH_Status FLASH_EnableWriteProtection(u32 page);
-FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef ob_standby);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(u32 time_out);
-FLASH_Status FLASH_ReadOutProtection(FunctionalState state);
-FlagStatus   FLASH_GetPrefetchBufferStatus(void);
-FlagStatus   FLASH_GetFlagStatus(u16 flag);
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif //__HAL_FLASH_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h
deleted file mode 100644
index dbfe38166..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_fsmc.h
+++ /dev/null
@@ -1,147 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_fsmc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SDIO
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_FSMC_H
-#define __HAL_FSMC_H
-
-// Files includes
-#include "types.h"
-#include "reg_common.h"
-#include "reg_fsmc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup FSMC_HAL
-/// @brief FSMC HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup FSMC_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FSMC_interrupts_define
-////////////////////////////////////////////////////////////////////////////////
-
-
-
-
-
-// Timing parameter configuration register set selection register set0 register set1 register set2
-
-#define FSMC_TimingRegSelect_0    ((u32)0x00000000)
-#define FSMC_TimingRegSelect_1    ((u32)0x00000100)
-#define FSMC_TimingRegSelect_2    ((u32)0x00000200)
-
-// Capacity of external device
-#define FSMC_MemSize_None   ((u32)0x00000000)
-#define FSMC_MemSize_64KB   ((u32)0x00000001)
-#define FSMC_MemSize_128KB  ((u32)0x00000002)
-#define FSMC_MemSize_256KB  ((u32)0x00000002)
-#define FSMC_MemSize_512KB  ((u32)0x00000004)
-#define FSMC_MemSize_1MB    ((u32)0x00000005)
-#define FSMC_MemSize_2MB    ((u32)0x00000006)
-#define FSMC_MemSize_4MB    ((u32)0x00000007)
-#define FSMC_MemSize_8MB    ((u32)0x00000008)
-#define FSMC_MemSize_16MB   ((u32)0x00000009)
-#define FSMC_MemSize_32MB   ((u32)0x0000000A)
-#define FSMC_MemSize_64MB   ((u32)0x0000000B)
-#define FSMC_MemSize_128MB  ((u32)0x0000000C)
-#define FSMC_MemSize_256MB  ((u32)0x0000000D)
-#define FSMC_MemSize_512MB  ((u32)0x0000000E)
-#define FSMC_MemSize_1GB    ((u32)0x0000000F)
-#define FSMC_MemSize_2GB    ((u32)0x00000010)
-#define FSMC_MemSize_4GB    ((u32)0x00000011)
-
-
-// Memory data bus bit width setting
-typedef enum {
-    FSMC_DataWidth_16bits      = (0x0000), //16bits
-    FSMC_DataWidth_32bits      = (0x0001), //32bits
-    FSMC_DataWidth_64bits      = (0x0002), //64bits
-    FSMC_DataWidth_128bits     = (0x0003), //128bits
-    FSMC_DataWidth_8bits       = (0x0004), //8bits
-} FSMC_NORSRAM_DataWidth_TypeDef;
-
-typedef enum {
-    FSMC_NORSRAM_BANK0 = 0,
-    FSMC_NORSRAM_BANK1 = 1,
-    FSMC_NORSRAM_BANK2 = 2,
-} FSMC_NORSRAM_BANK_TypeDef;
-
-typedef struct {
-    u32 FSMC_SMReadPipe;                                                        //sm_read_pipe[1:0] The cycle of latching read data, that is, the cycle when ready_resp is pulled high
-
-    u32 FSMC_ReadyMode;                                                         //Select whether the hready_resp signal comes from the FSMC IP internal or external DEVICE, only for writing and reading external DEVICE operations.
-    //0: Internal FSMC 1: External DEVICE (ie from FSMC_NWAIT)
-    u32 FSMC_WritePeriod;                                                       //Write cycle
-
-    u32 FSMC_WriteHoldTime;                                                     //Address/data hold time during write operation
-
-    u32 FSMC_AddrSetTime;                                                       //Address establishment time
-
-    u32 FSMC_ReadPeriod;                                                        //Read cycle
-
-    FSMC_NORSRAM_DataWidth_TypeDef FSMC_DataWidth;
-
-} FSMC_NORSRAM_Bank_InitTypeDef;
-
-typedef struct {
-    u32 FSMC_Mode;
-    u32 FSMC_TimingRegSelect;
-    u32 FSMC_MemSize;
-    u32 FSMC_MemType;
-    u32 FSMC_AddrDataMode;
-} FSMC_InitTypeDef;
-
-
-#define FSMC_MemType_SDRAM          ((u32)0x0<<5)
-#define FSMC_MemType_NorSRAM        ((u32)0x1<<5)
-#define FSMC_MemType_FLASH          ((u32)0x2<<5)
-#define FSMC_MemType_RESERVED       ((u32)0x3<<5)
-//SYSCFG_CFGR1
-#define FSMC_Mode_6800              ((u32)0x40000000)
-#define FSMC_Mode_8080              ((u32)0x20000000)
-#define FSMC_Mode_NorFlash          ((u32)0x00000000)
-
-#define FSMC_AddrDataMUX            ((u32)0x00000000)
-#define FSMC_AddrDataDeMUX          ((u32)0x10000000)
-
-
-
-
-void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct);
-void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct);
-void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct);
-void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank);
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_FSMC_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h
deleted file mode 100644
index b28afd839..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_gpio.h
+++ /dev/null
@@ -1,198 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_gpio.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_GPIO_H
-#define __HAL_GPIO_H
-
-// Files includes
-#include "types.h"
-#include "reg_gpio.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup GPIO_HAL
-/// @brief GPIO HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup GPIO_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Output Maximum frequency selection
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    GPIO_Speed_50MHz = 1,  ///< Maximum speed is 50MHz
-    GPIO_Speed_20MHz,      ///< Maximum speed is 20MHz
-    GPIO_Speed_10MHz       ///< Maximum speed is 10MHz
-} GPIOSpeed_TypeDef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configuration Mode enumeration
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    GPIO_Mode_AIN       = 0x00,  ///< Analog input
-    GPIO_Mode_FLOATING  = 0x04,  ///< Floating input
-    GPIO_Mode_IPD       = 0x28,  ///< Pull down input
-    GPIO_Mode_IPU       = 0x48,  ///< Pull up input
-    GPIO_Mode_Out_OD    = 0x14,  ///< Universal open drain output
-    GPIO_Mode_Out_PP    = 0x10,  ///< Universal push-pull output
-    GPIO_Mode_AF_OD     = 0x1C,  ///< Multiplex open drain output
-    GPIO_Mode_AF_PP     = 0x18   ///< Multiplexed push-pull output
-} GPIOMode_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Bit_SET and Bit_RESET enumeration
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    Bit_RESET = 0,  ///< bit reset
-    Bit_SET         ///< bit set
-} BitAction;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  GPIO Init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u16               GPIO_Pin;    ///< GPIO_Pin
-    GPIOSpeed_TypeDef GPIO_Speed;  ///< GPIO_Speed
-    GPIOMode_TypeDef  GPIO_Mode;   ///< GPIO_Mode
-} GPIO_InitTypeDef;
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup GPIO_Exported_Constants
-/// @{
-
-#define GPIO_Speed_2MHz GPIO_Speed_20MHz
-
-#define GPIO_Pin_0                  (0x0001U)                                   ///< Pin 0 selected
-#define GPIO_Pin_1                  (0x0002U)                                   ///< Pin 1 selected
-#define GPIO_Pin_2                  (0x0004U)                                   ///< Pin 2 selected
-#define GPIO_Pin_3                  (0x0008U)                                   ///< Pin 3 selected
-#define GPIO_Pin_4                  (0x0010U)                                   ///< Pin 4 selected
-#define GPIO_Pin_5                  (0x0020U)                                   ///< Pin 5 selected
-#define GPIO_Pin_6                  (0x0040U)                                   ///< Pin 6 selected
-#define GPIO_Pin_7                  (0x0080U)                                   ///< Pin 7 selected
-#define GPIO_Pin_8                  (0x0100U)                                   ///< Pin 8 selected
-#define GPIO_Pin_9                  (0x0200U)                                   ///< Pin 9 selected
-#define GPIO_Pin_10                 (0x0400U)                                   ///< Pin 10 selected
-#define GPIO_Pin_11                 (0x0800U)                                   ///< Pin 11 selected
-#define GPIO_Pin_12                 (0x1000U)                                   ///< Pin 12 selected
-#define GPIO_Pin_13                 (0x2000U)                                   ///< Pin 13 selected
-#define GPIO_Pin_14                 (0x4000U)                                   ///< Pin 14 selected
-#define GPIO_Pin_15                 (0x8000U)                                   ///< Pin 15 selected
-#define GPIO_Pin_All                (0xFFFFU)                                   ///< All pins selected
-
-
-#define GPIO_AF_0                   (0x00U)                                     ///< Alternative function 0
-#define GPIO_AF_1                   (0x01U)                                     ///< Alternative function 1
-#define GPIO_AF_2                   (0x02U)                                     ///< Alternative function 2
-#define GPIO_AF_3                   (0x03U)                                     ///< Alternative function 3
-#define GPIO_AF_4                   (0x04U)                                     ///< Alternative function 4
-#define GPIO_AF_5                   (0x05U)                                     ///< Alternative function 5
-#define GPIO_AF_6                   (0x06U)                                     ///< Alternative function 6
-#define GPIO_AF_7                   (0x07U)                                     ///< Alternative function 7
-#define GPIO_AF_8                   (0x08U)                                     ///< Alternative function 8 
-#define GPIO_AF_9                   (0x09U)                                     ///< Alternative function 9 
-#define GPIO_AF_10                  (0x0AU)                                     ///< Alternative function 10
-#define GPIO_AF_11                  (0x0BU)                                     ///< Alternative function 11
-#define GPIO_AF_12                  (0x0CU)                                     ///< Alternative function 12
-#define GPIO_AF_13                  (0x0DU)                                     ///< Alternative function 13
-#define GPIO_AF_14                  (0x0EU)                                     ///< Alternative function 14
-#define GPIO_AF_15                  (0x0FU)                                     ///< Alternative function 15
-#define GPIO_PortSourceGPIOA        (0x00U)
-#define GPIO_PortSourceGPIOB        (0x01U)
-#define GPIO_PortSourceGPIOC        (0x02U)
-#define GPIO_PortSourceGPIOD        (0x03U)
-
-#define GPIO_PinSource0             (0x00U)
-#define GPIO_PinSource1             (0x01U)
-#define GPIO_PinSource2             (0x02U)
-#define GPIO_PinSource3             (0x03U)
-#define GPIO_PinSource4             (0x04U)
-#define GPIO_PinSource5             (0x05U)
-#define GPIO_PinSource6             (0x06U)
-#define GPIO_PinSource7             (0x07U)
-#define GPIO_PinSource8             (0x08U)
-#define GPIO_PinSource9             (0x09U)
-#define GPIO_PinSource10            (0x0AU)
-#define GPIO_PinSource11            (0x0BU)
-#define GPIO_PinSource12            (0x0CU)
-#define GPIO_PinSource13            (0x0DU)
-#define GPIO_PinSource14            (0x0EU)
-#define GPIO_PinSource15            (0x0FU)
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup GPIO_Exported_Variables
-/// @{
-
-#ifdef _HAL_GPIO_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-
-
-#undef GLOBAL
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup GPIO_Exported_Functions
-/// @{
-void GPIO_DeInit(GPIO_TypeDef* gpio);
-void GPIO_AFIODeInit(void);
-void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct);
-void GPIO_StructInit(GPIO_InitTypeDef* init_struct);
-void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin);
-void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin);
-void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value);
-void GPIO_Write(GPIO_TypeDef* gpio, u16 value);
-void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state);
-void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin);
-bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin);
-bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin);
-
-u16 GPIO_ReadInputData(GPIO_TypeDef* gpio);
-u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio);
-
-
-void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function);
-
-void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function);
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_GPIO_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h
deleted file mode 100644
index 42a9ab55f..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_i2c.h
+++ /dev/null
@@ -1,255 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_i2c.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE I2C
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_I2C_H
-#define __HAL_I2C_H
-
-// Files includes
-#include "types.h"
-#include "reg_i2c.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_HAL
-/// @brief I2C HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup DRV_Exported_Constants
-/// @{
-
-#define I2C_OWN_ADDRESS  0x20
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  I2C Init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    union {
-        u16 Mode;        ///< Specifies the I2C mode. This parameter can be a value of I2C_mode.
-        u16 I2C_Mode;
-    };
-    union {
-        u16 Speed;       ///< Specifies the I2C speed. This parameter can be a value of I2C_speed.
-        u16 I2C_Speed;
-    };
-    union {
-        u16 OwnAddress;  ///< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address.
-        u16 I2C_OwnAddress;
-    };
-
-    union {
-        u32 ClockSpeed;  ///< Specifies the clock speed.
-        u32 I2C_ClockSpeed;
-    };
-} I2C_InitTypeDef;
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_Exported_Constants
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C DMA Direction
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RDMAE_SET = 1,  // 1 - DMA read
-    TDMAE_SET       // 2 - DMA transmit
-} I2C_DMA_Dir_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C Transfer Direction
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    I2C_Direction_Transmitter,  // I2C Transmitter
-    I2C_Direction_Receiver      // I2C Receiver
-} I2C_Trans_Dir_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C Acknowledged Address
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    I2C_AcknowledgedAddress_7bit  = 0x4000,  // 7-bit address
-    I2C_AcknowledgedAddress_10bit = 0xC000   // 10-bit address
-} I2C_ACKaddr_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_Private_Defines
-/// @{
-#define INTR_MASK           ((u16)0xC000)
-#define FLAG_Mask           ((u32)0x00793FFF)
-#define IC_TAR_ENDUAL_Set   ((u16)0x1000)
-#define IC_TAR_ENDUAL_Reset ((u16)0xEFFF)
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_modes
-/// @{
-#define TX_EMPTY_CTRL       I2C_CR_EMPINT
-#define IC_SLAVE_DISABLE    I2C_CR_SLAVEDIS
-#define IC_RESTART_EN       I2C_CR_REPEN
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_interrupts_definition
-/// @{
-#define I2C_IT_RX_UNDER     ((u16)0x0001)
-#define I2C_IT_RX_OVER      ((u16)0x0002)
-#define I2C_IT_RX_FULL      ((u16)0x0004)
-#define I2C_IT_TX_OVER      ((u16)0x0008)
-#define I2C_IT_TX_EMPTY     ((u16)0x0010)
-#define I2C_IT_RD_REQ       ((u16)0x0020)
-#define I2C_IT_TX_ABRT      ((u16)0x0040)
-#define I2C_IT_RX_DONE      ((u16)0x0080)
-#define I2C_IT_ACTIVITY     ((u16)0x0100)
-#define I2C_IT_STOP_DET     ((u16)0x0200)
-#define I2C_IT_START_DET    ((u16)0x0400)
-#define I2C_IT_GEN_CALL     ((u16)0x0800)
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_flags_definition
-/// @{
-#define I2C_FLAG_RX_UNDER     ((u16)0x0001)
-#define I2C_FLAG_RX_OVER      ((u16)0x0002)
-#define I2C_FLAG_RX_FULL      ((u16)0x0004)
-#define I2C_FLAG_TX_OVER      ((u16)0x0008)
-#define I2C_FLAG_TX_EMPTY     ((u16)0x0010)
-#define I2C_FLAG_RD_REQ       ((u16)0x0020)
-#define I2C_FLAG_TX_ABRT      ((u16)0x0040)
-#define I2C_FLAG_RX_DONE      ((u16)0x0080)
-#define I2C_FLAG_ACTIVITY     ((u16)0x0100)
-#define I2C_FLAG_STOP_DET     ((u16)0x0200)
-#define I2C_FLAG_START_DET    ((u16)0x0400)
-#define I2C_FLAG_GEN_CALL     ((u16)0x0800)
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_Events
-/// @{
-#define I2C_EVENT_RX_UNDER     ((u16)0x0001)
-#define I2C_EVENT_RX_OVER      ((u16)0x0002)
-#define I2C_EVENT_RX_FULL      ((u16)0x0004)
-#define I2C_EVENT_TX_OVER      ((u16)0x0008)
-#define I2C_EVENT_TX_EMPTY     ((u16)0x0010)
-#define I2C_EVENT_RD_REQ       ((u16)0x0020)
-#define I2C_EVENT_TX_ABRT      ((u16)0x0040)
-#define I2C_EVENT_RX_DONE      ((u16)0x0080)
-#define I2C_EVENT_ACTIVITY     ((u16)0x0100)
-#define I2C_EVENT_STOP_DET     ((u16)0x0200)
-#define I2C_EVENT_START_DET    ((u16)0x0400)
-#define I2C_EVENT_GEN_CALL     ((u16)0x0800)
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_Statusflags_definition
-/// @{
-#define I2C_STATUS_FLAG_ACTIVITY    ((u16)0x8001)
-#define I2C_STATUS_FLAG_TFNF        ((u16)0x8002)
-#define I2C_STATUS_FLAG_TFE         ((u16)0x8004)
-#define I2C_STATUS_FLAG_RFNE        ((u16)0x8008)
-#define I2C_STATUS_FLAG_RFF         ((u16)0x8010)
-#define I2C_STATUS_FLAG_M_ACTIVITY  ((u16)0x8020)
-#define I2C_STATUS_FLAG_S_ACTIVITY  ((u16)0x8040)
-/// @}
-
-
-
-#define IC_SLAVE_ENABLE                 (0x0000<<6)
-#define IC_7BITADDR_MASTER              (0x0000<<4)
-#define IC_7BITADDR_SLAVE               (0x0000<<3)
-#define I2C_Speed_STANDARD              ((u16)0x0002)
-#define I2C_Speed_FAST                  ((u16)0x0004)
-#define I2C_Mode_MASTER                 ((u16)0x0001)
-#define I2C_Mode_SLAVE                  ((u16)0x0000)
-#define CMD_READ                        ((u16)0x0100)
-#define CMD_WRITE                       ((u16)0x0000)
-#define I2C_Mode_I2C                    ((u16)0x0000)
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_Exported_Variables
-/// @{
-#ifdef _HAL_I2C_C_
-
-#define GLOBAL
-
-static u8 I2C_CMD_DIR = 0;
-u16       I2C_DMA_DIR = 0;
-
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_Exported_Functions
-/// @{
-void I2C_DeInit(I2C_TypeDef* i2c);
-void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct);
-void I2C_StructInit(I2C_InitTypeDef* init_struct);
-void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state);
-void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state);
-void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state);
-void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state);
-void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr);
-void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state);
-void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state);
-void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state);
-void I2C_SendData(I2C_TypeDef* i2c, u8 dat);
-void I2C_ReadCmd(I2C_TypeDef* i2c);
-void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir);
-void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag);
-void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it);
-
-u8  I2C_ReceiveData(I2C_TypeDef* i2c);
-u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg);
-u32 I2C_GetLastEvent(I2C_TypeDef* i2c);
-
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event);
-FlagStatus  I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag);
-ITStatus    I2C_GetITStatus(I2C_TypeDef* i2c, u32 it);
-
-////////////////////////////////////////////////////////////////////////////////
-//          Extended function interface
-////////////////////////////////////////////////////////////////////////////////
-void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr);
-void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state);
-void I2C_DMAConfigure(I2C_TypeDef* i2c, u8 dir);
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif //__HAL_I2C_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h
deleted file mode 100644
index e0b86d7b7..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_iwdg.h
+++ /dev/null
@@ -1,130 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_iwdg.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE IWDG
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_IWDG_H
-#define __HAL_IWDG_H
-
-// Files includes
-#include "types.h"
-#include "reg_iwdg.h"
-#include "reg_common.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup IWDG_HAL
-/// @brief IWDG HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup IWDG_Exported_Constants
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  IWDG prescaler
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    IWDG_Prescaler_4   = IWDG_PR_PRE_DIV4,
-    IWDG_Prescaler_8   = IWDG_PR_PRE_DIV8,
-    IWDG_Prescaler_16  = IWDG_PR_PRE_DIV16,
-    IWDG_Prescaler_32  = IWDG_PR_PRE_DIV32,
-    IWDG_Prescaler_64  = IWDG_PR_PRE_DIV64,
-    IWDG_Prescaler_128 = IWDG_PR_PRE_DIV128,
-    IWDG_Prescaler_256 = IWDG_PR_PRE_DIV256
-} IWDGPrescaler_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  IWDG flag
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    IWDG_FLAG_PVU = 0x0001,  // IWDG prescaler value update flag
-    IWDG_FLAG_RVU = 0x0002   // IWDG counter reload value update flag
-} IWDGFlag_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Write access to IWDG_PR and IWDG_RLR registers
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    IWDG_WriteAccess_Enable  = 0x5555,  // Enable write
-    IWDG_WriteAccess_Disable = 0x0000   // Disable write
-} IWDGWriteAccess_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  IWDG Key Reload
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    KR_KEY_Reload = 0xAAAA,  // Reload value
-    KR_KEY_Enable = 0xCCCC   // Start IWDG
-} IWDGKey_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  IWDG Overflow Configration
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    IWDG_Overflow_Reset     = 0,               //
-    IWDG_Overflow_Interrupt = IWDG_CR_IRQSEL   //
-} IWDGOverflowConfig_TypeDef;
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup IWDG_Exported_Variables
-/// @{
-#ifdef _HAL_IWDG_C_
-#define GLOBAL
-
-#else
-#define GLOBAL extern
-#endif
-
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup IWDG_Exported_Functions
-/// @{
-FlagStatus IWDG_GetFlagStatus(u16 flag);
-
-void IWDG_WriteAccessCmd(u16 write_access);
-void IWDG_SetPrescaler(u8 prescaler);
-void IWDG_SetReload(u16 reload);
-u32 IWDG_GetReload(void);
-void IWDG_ReloadCounter(void);
-void IWDG_Enable(void);
-void PVU_CheckStatus(void);
-void RVU_CheckStatus(void);
-
-void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config);
-void IWDG_ClearITPendingBit(void);
-void IWDG_EnableIT(void);
-void IWDG_Reset(void);
-void IWDG_ClearIT(void);
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_IWDG_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h
deleted file mode 100644
index 0b7429963..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_misc.h
+++ /dev/null
@@ -1,128 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_misc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE NVIC
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_MISC_H
-#define __HAL_MISC_H
-
-// Files includes
-#include "types.h"
-#include "reg_common.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup NVIC_HAL
-/// @brief NVIC HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup NVIC_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  NVIC Init Structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u8 NVIC_IRQChannel;
-    u8 NVIC_IRQChannelPreemptionPriority;
-    u8 NVIC_IRQChannelSubPriority;
-    FunctionalState NVIC_IRQChannelCmd;
-} NVIC_InitTypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  NVIC New Init Structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u8              NVIC_IRQChannel;
-    u8              NVIC_IRQChannelPreemptionPriority;                          // Cortex-M0 not used
-    u8              NVIC_IRQChannelSubPriority;
-    FunctionalState NVIC_IRQChannelCmd;
-} exNVIC_Init_TypeDef;
-
-/// @}
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup NVIC_Exported_Constants
-/// @{
-
-#define NVIC_VectTab_RAM        (0x20000000U)
-#define NVIC_VectTab_FLASH      (0x08000000U)
-
-#define NVIC_LP_SEVONPEND       (0x10U)
-#define NVIC_LP_SLEEPDEEP       (0x04U)
-#define NVIC_LP_SLEEPONEXIT     (0x02U)
-
-#define NVIC_PriorityGroup_0     (0x0700U) // 0 bits for pre-emption priority 4 bits for subpriority 
-#define NVIC_PriorityGroup_1     (0x0600U) // 1 bits for pre-emption priority 3 bits for subpriority 
-#define NVIC_PriorityGroup_2     (0x0500U) // 2 bits for pre-emption priority 2 bits for subpriority 
-#define NVIC_PriorityGroup_3     (0x0400U) // 3 bits for pre-emption priority 1 bits for subpriority 
-#define NVIC_PriorityGroup_4     (0x0300U) // 4 bits for pre-emption priority 0 bits for subpriority 
-
-#define AIRCR_VECTKEY_MASK (0x05FA0000U)
-
-#define SysTick_CLKSource_HCLK_Div8     (0xFFFFFFFBU)
-
-
-#define SysTick_CLKSource_EXTCLK        (0xFFFFFFFBU)
-#define SysTick_CLKSource_HCLK          (0x00000004U)
-/// @}
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup NVIC_Exported_Variables
-/// @{
-
-#ifdef _HAL_NVIC_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup NVIC_Exported_Functions
-/// @{
-
-void NVIC_PriorityGroupConfig(u32 priority_group);
-void NVIC_SetVectorTable(u32 vect_tab, u32 offset);
-
-void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state);
-void NVIC_Init(NVIC_InitTypeDef* init_struct);
-
-void SysTick_CLKSourceConfig(u32 systick_clk_source);
-
-void exNVIC_Init(exNVIC_Init_TypeDef* init_struct);
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_NVIC_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h
deleted file mode 100644
index f7837ca8d..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_pwr.h
+++ /dev/null
@@ -1,156 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_pwr.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE PWR
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_PWR_H
-#define __HAL_PWR_H
-
-// Files includes
-#include "types.h"
-#include "reg_pwr.h"
-#include "reg_syscfg.h"
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup PWR_HAL
-/// @brief PWR HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup PWR_Exported_Types
-/// @{
-
-typedef enum {
-    emWUP_Pin1 = 0,
-    emWUP_Pin2 = 1,
-    emWUP_Pin3,
-    emWUP_Pin4,
-    emWUP_Pin5,
-    emWUP_Pin6,
-} emWUP_Pin_Typedef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PVD_detection_level
-
-typedef enum {
-    emPVD_LEVEL0  = SYSCFG_PDETCSR_PLS_1V7,
-    emPVD_LEVEL1  = SYSCFG_PDETCSR_PLS_2V0,
-    emPVD_LEVEL2  = SYSCFG_PDETCSR_PLS_2V3,
-    emPVD_LEVEL3  = SYSCFG_PDETCSR_PLS_2V6,
-    emPVD_LEVEL4  = SYSCFG_PDETCSR_PLS_2V9,
-    emPVD_LEVEL5  = SYSCFG_PDETCSR_PLS_3V2,
-    emPVD_LEVEL6  = SYSCFG_PDETCSR_PLS_3V5,
-    emPVD_LEVEL7  = SYSCFG_PDETCSR_PLS_3V8,
-    emPVD_LEVEL8  = SYSCFG_PDETCSR_PLS_4V1,
-    emPVD_LEVEL9  = SYSCFG_PDETCSR_PLS_4V4,
-    emPVD_LEVEL10 = SYSCFG_PDETCSR_PLS_4V7
-} emPVD_Level_Typedef;
-#define PWR_PVDLevel_1V7          SYSCFG_PDETCSR_PLS_1V7
-#define PWR_PVDLevel_2V0          SYSCFG_PDETCSR_PLS_2V0
-#define PWR_PVDLevel_2V3          SYSCFG_PDETCSR_PLS_2V3
-#define PWR_PVDLevel_2V6          SYSCFG_PDETCSR_PLS_2V6
-#define PWR_PVDLevel_2V9          SYSCFG_PDETCSR_PLS_2V9
-#define PWR_PVDLevel_3V2          SYSCFG_PDETCSR_PLS_3V2
-#define PWR_PVDLevel_3V5          SYSCFG_PDETCSR_PLS_3V5
-#define PWR_PVDLevel_3V8          SYSCFG_PDETCSR_PLS_3V8
-#define PWR_PVDLevel_4V1          SYSCFG_PDETCSR_PLS_4V1
-#define PWR_PVDLevel_4V4          SYSCFG_PDETCSR_PLS_4V4
-#define PWR_PVDLevel_4V7          SYSCFG_PDETCSR_PLS_4V7
-/// @brief Regulator_state_is_STOP_mode
-typedef enum {
-    PWR_Regulator_ON       = 0x00000000,
-    PWR_Regulator_LowPower = 0x00000001
-
-} emPWR_Reg_Stop_mode_Typedef;
-
-/// @brief STOP_mode_entry
-typedef enum {
-    PWR_STOPEntry_WFI = 0x00000001,
-    PWR_STOPEntry_WFE = 0x00000002
-
-} emPWR_STOP_ModeEn_Typedef;
-
-/// @brief Low Power Mode
-typedef enum {
-    LP_STOP_MODE    = 0,
-    LP_SLEEP_MODE   = 1,
-    LP_STANDBY_MODE = 2
-} emPWR_LP_Mode_Typedef;
-
-/// @brief Wait_for_mode
-typedef enum {
-    LP_WFI,
-    LP_WFE
-} emPWR_Wait_Mode_Typedef;
-//typedef enum {
-//    PWR_FLAG_WU   = PWR_CSR_WUF,
-//    PWR_FLAG_SB   = PWR_CSR_SBF,
-
-//    PWR_FLAG_PVDO = PWR_CSR_PVDO
-
-
-//} emPWR_PWR_Flag_Typedef;
-
-
-/// @}
-
-///////////////////////////////////////////////////////////////////////////////
-/// @defgroup PWR_Exported_Variables
-/// @{
-
-#ifdef _HAL_PWR_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup PWR_Exported_Functions
-/// @{
-
-void PWR_DeInit(void);
-
-void PWR_BackupAccessCmd(FunctionalState state);
-
-void PWR_PVDCmd(FunctionalState state);
-void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level);
-void PWR_WakeUpPinCmd(FunctionalState state);
-void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry);
-void PWR_EnterSTANDBYMode(void);
-
-
-void PWR_ClearFlag(u32 flag);
-FlagStatus PWR_GetFlagStatus(u32 flag);
-FlagStatus PWR_GetPVDOFlagStatus(u32 flag);
-void exPWR_EnterLowPowerMode(emPWR_LP_Mode_Typedef lp_mode, emPWR_Wait_Mode_Typedef wait_mode);
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_PWR_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h
deleted file mode 100644
index deb916d4c..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rcc.h
+++ /dev/null
@@ -1,329 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_rcc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RCC
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_RCC_H
-#define __HAL_RCC_H
-
-// Files includes
-#include "types.h"
-#include "reg_common.h"
-#include "mm32_reg.h"
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RCC_HAL
-/// @brief RCC HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RCC_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RCC_Exported_Constants
-/// @{
-
-
-/// @}
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RCC_Exported_Enumeration
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief HSE configuration
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_HSE_OFF    = 0,             // HSE OFF
-    RCC_HSE_ON     = RCC_CR_HSEON,  // HSE ON
-    RCC_HSE_Bypass = RCC_CR_HSEBYP  // HSE Bypass
-} RCCHSE_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Used for flags
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    CR_REG_INDEX   = 1,     //
-    BDCR_REG_INDEX = 2,     //
-    CSR_REG_INDEX  = 3,     //
-    RCC_FLAG_MASK  = 0x1FU  //
-} RCC_RegisterFlag_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC Flag
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    // Flags in the CR register
-    RCC_FLAG_HSIRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)),         ///< Internal High Speed clock ready flag
-    RCC_FLAG_HSERDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)),         ///< External High Speed clock ready flag
-
-    RCC_FLAG_PLLRDY = ((u8)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)),         ///< PLL clock ready flag
-
-    // Flags in the CSR register
-    RCC_FLAG_LSIRDY  = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)),      ///< Internal Low Speed oscillator Ready
-    RCC_FLAG_PINRST  = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)),     ///< PIN reset flag
-    RCC_FLAG_PORRST  = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)),     ///< POR/PDR reset flag
-    RCC_FLAG_SFTRST  = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)),     ///< Software Reset flag
-    RCC_FLAG_IWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)),    ///< Independent Watchdog reset flag
-    RCC_FLAG_WWDGRST = ((u8)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)),    ///< Window watchdog reset flag
-
-    // Flags in the BDCR register
-    RCC_FLAG_LSERDY = ((u8)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos))      ///< External Low Speed oscillator Ready
-} RCC_FLAG_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief System clock source
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_HSI = 0,  // Set HSI as systemCLOCK
-    RCC_HSE = 1,  // Set HSE as systemCLOCK
-    RCC_PLL = 2,   // Set PLL as systemCLOCK
-    RCC_LSI = 3  // Set LSI as systemCLOCK
-} SYSCLK_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PLL entry clock source
-////////////////////////////////////////////////////////////////////////////////
-
-typedef enum {
-    RCC_HSI_Div4 = 0,
-    RCC_HSI_Div = 0,
-    RCC_HSE_Div1 = RCC_PLLCFGR_PLLSRC,
-    RCC_HSE_Div2 = (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC),
-} RCC_PLLSource_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PLL multiplication factor
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_PLLMul_2  = 0x00000000U,
-    RCC_PLLMul_3  = 0x00040000U,
-    RCC_PLLMul_4  = 0x00080000U,
-    RCC_PLLMul_5  = 0x000C0000U,
-    RCC_PLLMul_6  = 0x00100000U,
-    RCC_PLLMul_7  = 0x00140000U,
-    RCC_PLLMul_8  = 0x00180000U,
-    RCC_PLLMul_9  = 0x001C0000U,
-    RCC_PLLMul_10 = 0x00200000U,
-    RCC_PLLMul_11 = 0x00240000U,
-    RCC_PLLMul_12 = 0x00280000U,
-    RCC_PLLMul_13 = 0x002C0000U,
-    RCC_PLLMul_14 = 0x00300000U,
-    RCC_PLLMul_15 = 0x00340000U,
-    RCC_PLLMul_16 = 0x00380000U
-} RCC_PLLMul_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief AHB clock source
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_SYSCLK_Div1   = RCC_CFGR_HPRE_DIV1,
-    RCC_SYSCLK_Div2   = RCC_CFGR_HPRE_DIV2,
-    RCC_SYSCLK_Div4   = RCC_CFGR_HPRE_DIV4,
-    RCC_SYSCLK_Div8   = RCC_CFGR_HPRE_DIV8,
-    RCC_SYSCLK_Div16  = RCC_CFGR_HPRE_DIV16,
-    RCC_SYSCLK_Div64  = RCC_CFGR_HPRE_DIV64,
-    RCC_SYSCLK_Div128 = RCC_CFGR_HPRE_DIV128,
-    RCC_SYSCLK_Div256 = RCC_CFGR_HPRE_DIV256,
-    RCC_SYSCLK_Div512 = RCC_CFGR_HPRE_DIV512
-} RCC_AHB_CLK_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief APB1 and APB2clock source
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_HCLK_Div1  = RCC_CFGR_PPRE1_DIV1,
-    RCC_HCLK_Div2  = RCC_CFGR_PPRE1_DIV2,
-    RCC_HCLK_Div4  = RCC_CFGR_PPRE1_DIV4,
-    RCC_HCLK_Div8  = RCC_CFGR_PPRE1_DIV8,
-    RCC_HCLK_Div16 = RCC_CFGR_PPRE1_DIV16
-} RCC_APB1_APB2_CLK_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief USB Device clock source
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_USBCLKSource_PLLCLK_Div1 = 0,
-    RCC_USBCLKSource_PLLCLK_Div2 = 1,
-    RCC_USBCLKSource_PLLCLK_Div3 = 2,
-    RCC_USBCLKSource_PLLCLK_Div4 = 3
-} RCC_USBCLKSOURCE_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC clock source
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_PCLK2_Div2 = (0x00000000),
-    RCC_PCLK2_Div4 = (0x00004000),
-    RCC_PCLK2_Div6 = (0x00008000),
-    RCC_PCLK2_Div8 = (0x0000C000)
-} RCC_ADCCLKSOURCE_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief LSE configuration
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_LSE_OFF    = 0,               // LSE OFF
-    RCC_LSE_ON     = RCC_BDCR_LSEON,  // LSE ON
-    RCC_LSE_Bypass = RCC_BDCR_LSEBYP  // LSE Bypass
-} RCC_LSE_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC clock source
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_RTCCLKSource_LSE        = RCC_BDCR_RTCSEL_LSE,
-    RCC_RTCCLKSource_LSI        = RCC_BDCR_RTCSEL_LSI,
-    RCC_RTCCLKSource_HSE_Div128 = RCC_BDCR_RTCSEL_HSE
-} RCC_RTCCLKSOURCE_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Clock source to output on MCO pin
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_MCO_NoClock = RCC_CFGR_MCO_NOCLOCK,
-    RCC_MCO_LSI     = RCC_CFGR_MCO_LSI,
-    RCC_MCO_LSE = RCC_CFGR_MCO_LSE,
-    RCC_MCO_SYSCLK = RCC_CFGR_MCO_SYSCLK,
-    RCC_MCO_HSI    = RCC_CFGR_MCO_HSI,
-    RCC_MCO_HSE    = RCC_CFGR_MCO_HSE,
-    RCC_MCO_PLLCLK_Div2 = RCC_CFGR_MCO_PLL
-} RCC_MCO_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC Interrupt source
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RCC_IT_LSIRDY = RCC_CIR_LSIRDYF,
-    RCC_IT_LSERDY = RCC_CIR_LSERDYF,
-    RCC_IT_HSIRDY = RCC_CIR_HSIRDYF,
-    RCC_IT_HSERDY = RCC_CIR_HSERDYF,
-    RCC_IT_PLLRDY = RCC_CIR_PLLRDYF,
-    RCC_IT_CSS = RCC_CIR_CSSF
-} RCC_IT_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC clock frequency type definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u32 SYSCLK_Frequency;                                                       ///< returns SYSCLK clock frequency.
-    u32 HCLK_Frequency;                                                         ///< returns hclk clock frequency.
-    u32 PCLK1_Frequency;                                                        ///< returns PCLK1 clock frequency.
-    u32 PCLK2_Frequency;                                                        ///< returns PCLK2 clock frequency.
-    u32 ADCCLK_Frequency;                                                       ///< returns ADCCLK clock frequency.
-} RCC_ClocksTypeDef;
-/// @}
-
-/// @}
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RCC_Exported_Variables
-/// @{
-#ifdef _HAL_RCC_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RCC_Exported_Functions
-/// @{
-void RCC_DeInit(void);
-void RCC_HSEConfig(RCCHSE_TypeDef state);
-void RCC_HSICmd(FunctionalState state);
-void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_src);
-void RCC_PLLDMDNConfig(u32 plldn, u32 plldm);
-void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul);
-void RCC_PLLCmd(FunctionalState state);
-void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk);
-void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk);
-void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk);
-void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src);
-void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2);
-void RCC_LSICmd(FunctionalState state);
-
-void RCC_RTCCLKCmd(FunctionalState state);
-void RCC_LSEConfig(RCC_LSE_TypeDef state);
-void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src);
-void RCC_BackupResetCmd(FunctionalState state);
-
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk);
-void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state);
-void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state);
-void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state);
-void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state);
-void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state);
-void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state);
-void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state);
-void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state);
-void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state);
-void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state);
-
-void RCC_ClockSecuritySystemCmd(FunctionalState state);
-void RCC_MCOConfig(RCC_MCO_TypeDef mco_src);
-void RCC_ClearFlag(void);
-void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state);
-void RCC_ClearITPendingBit(u8 it);
-
-u8  RCC_GetSYSCLKSource(void);
-u32 RCC_GetSysClockFreq(void);
-u32 RCC_GetHCLKFreq(void);
-
-u32 RCC_GetPCLK1Freq(void);
-u32 RCC_GetPCLK2Freq(void);
-FlagStatus  RCC_GetFlagStatus(RCC_FLAG_TypeDef flag);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag);
-ITStatus    RCC_GetITStatus(RCC_IT_TypeDef it);
-
-////////////////////////////////////////////////////////////////////////////////
-//          Extended function interface
-////////////////////////////////////////////////////////////////////////////////
-//ErrorStatus exRCC_Init(RCCInitStruct_TypeDef* para);
-void exRCC_SystickDisable(void);
-void exRCC_SystickEnable(u32 sys_tick_period);
-void exRCC_APB1PeriphReset(u32 apb1_periph);
-void exRCC_APB2PeriphReset(u32 apb2_periph);
-void exRCC_BackupReset(void);
-void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state);
-void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state);
-/// @}
-
-/// @}
-
-/// @}
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_RCC_H 
-////////////////////////////////////////////////////////////////////////////////
-
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h
deleted file mode 100644
index da5295c78..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_redefine.h
+++ /dev/null
@@ -1,102 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_redefine.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE REDEFINE
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_REDEFINE_H
-#define __HAL_REDEFINE_H
-
-// Files includes
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-/////////////////////////////////////1///////////////////////////////////////////
-/// @defgroup REDEFINE_HAL
-/// @brief REDEFINE HAL modules
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup REDEFINE_Exported_Types
-/// @{
-///
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup REDEFINE_Exported_Constants
-/// @{
-//Lib redefine
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief HAL_lib Version compatibility definition
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM compatibility definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define TIM_TRGOSource_Reset          TIM_TRIGSource_Reset
-#define TIM_TRGOSource_Enable         TIM_TRIGSource_Enable
-#define TIM_TRGOSource_Update         TIM_TRIGSource_Update
-#define TIM_TRGOSource_OC1            TIM_TRIGSource_OC1
-#define TIM_TRGOSource_OC1Ref         TIM_TRIGSource_OC1Ref
-#define TIM_TRGOSource_OC2Ref         TIM_TRIGSource_OC2Ref
-#define TIM_TRGOSource_OC3Ref         TIM_TRIGSource_OC3Ref
-#define TIM_TRGOSource_OC4Ref         TIM_TRIGSource_OC4Ref
-///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
-///< The Counter Enable CEN is used as the trigger output (TRIG).
-///< The update event is used as the trigger output (TRIG).
-///< The trigger output sends a positive pulse when the CC1IF flag     ///< is to be set, as soon as a capture or compare match occurs (TRIG).
-///< OC1REF signal is used as the trigger output (TRIG).
-///< OC2REF signal is used as the trigger output (TRIG).
-///< OC3REF signal is used as the trigger output (TRIG).
-///< OC4REF signal is used as the trigger output (TRIG).
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup REDEFINE_Exported_Variables
-/// @{
-#ifdef _HAL_REDEFINE_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup REDEFINE_Exported_Functions
-/// @{
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_REDEFINE_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h
deleted file mode 100644
index fcf48d569..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_rtc.h
+++ /dev/null
@@ -1,114 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_rtc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE RTC
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_RTC_H
-#define __HAL_RTC_H
-
-// Files includes
-#include "types.h"
-#include "reg_common.h"
-#include "reg_rtc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RTC_HAL
-/// @brief RTC HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RTC_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_interrupts_define
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RTC_IT_OW  = RTC_CR_OWIE,   ///< Overflow interrupt
-    RTC_IT_ALR = RTC_CR_ALRIE,  ///< Alarm interrupt
-    RTC_IT_SEC = RTC_CR_SECIE   ///< Second interrupt
-} RTC_IT_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_interrupts_flags
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    RTC_FLAG_RTOFF = RTC_CSR_RTOFF,  ///< RTC Operation OFF flag
-    RTC_FLAG_RSF   = RTC_CSR_RSF,    ///< Registers Synchronized flag
-    RTC_FLAG_OW    = RTC_CSR_OWF,    ///< Overflow flag
-    RTC_FLAG_ALR   = RTC_CSR_ALRF,   ///< Alarm flag
-    RTC_FLAG_SEC   = RTC_CSR_SECF    ///< Second flag
-} RTC_FLAG_TypeDef;
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RTC_Exported_Constants
-/// @{
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RTC_Exported_Variables
-/// @{
-
-#ifdef _HAL_RTC_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-GLOBAL  bool accessRTC;
-
-
-#undef GLOBAL
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup RTC_Exported_Functions
-/// @{
-void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state);
-void RTC_ClearFlag(RTC_FLAG_TypeDef flag);
-void RTC_ClearITPendingBit(RTC_IT_TypeDef it);
-void RTC_EnterConfigMode(void);
-void RTC_SetCounter(u32 count);
-void RTC_SetPrescaler(u32 prescaler);
-void RTC_SetAlarm(u32 alarm);
-void RTC_ExitConfigMode(void);
-void RTC_WaitForLastTask(void);
-void RTC_WaitForSynchro(void);
-
-u32 RTC_GetCounter(void);
-u32 RTC_GetDivider(void);
-
-FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag);
-ITStatus   RTC_GetITStatus(RTC_IT_TypeDef it);
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_RTC_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h
deleted file mode 100644
index 199ccc4c6..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_sdio.h
+++ /dev/null
@@ -1,503 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_gpio.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE GPIO
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_SDIO_H
-#define __HAL_SDIO_H
-
-// Files includes
-#include "mm32_reg.h"
-
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup GPIO_HAL
-/// @brief GPIO HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup GPIO_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Output Maximum frequency selection
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_FLAG_CCRCFAIL                  ((u32)0x00000001)
-#define SDIO_FLAG_DCRCFAIL                  ((u32)0x00000002)
-#define SDIO_FLAG_CTIMEOUT                  ((u32)0x00000004)
-#define SDIO_FLAG_DTIMEOUT                  ((u32)0x00000008)
-#define SDIO_FLAG_TXUNDERR                  ((u32)0x00000010)
-#define SDIO_FLAG_RXOVERR                   ((u32)0x00000020)
-#define SDIO_FLAG_CMDREND                   ((u32)0x00000040)
-#define SDIO_FLAG_CMDSENT                   ((u32)0x00000080)
-#define SDIO_FLAG_DATAEND                   ((u32)0x00000100)
-#define SDIO_FLAG_STBITERR                  ((u32)0x00000200)
-#define SDIO_FLAG_DBCKEND                   ((u32)0x00000400)
-#define SDIO_FLAG_CMDACT                    ((u32)0x00000800)
-#define SDIO_FLAG_TXACT                     ((u32)0x00001000)
-#define SDIO_FLAG_RXACT                     ((u32)0x00002000)
-#define SDIO_FLAG_TXFIFOHE                  ((u32)0x00004000)
-#define SDIO_FLAG_RXFIFOHF                  ((u32)0x00008000)
-#define SDIO_FLAG_TXFIFOF                   ((u32)0x00010000)
-#define SDIO_FLAG_RXFIFOF                   ((u32)0x00020000)
-#define SDIO_FLAG_TXFIFOE                   ((u32)0x00040000)
-#define SDIO_FLAG_RXFIFOE                   ((u32)0x00080000)
-#define SDIO_FLAG_TXDAVL                    ((u32)0x00100000)
-#define SDIO_FLAG_RXDAVL                    ((u32)0x00200000)
-#define SDIO_FLAG_SDIOIT                    ((u32)0x00400000)
-#define SDIO_FLAG_CEATAEND                  ((u32)0x00800000)
-
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-//SDIO working mode define ,SDIO working mode definition, set through the SD_SetDevice Mode function.
-#define SD_POLLING_MODE     0                                                                      /// Query mode. In this mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing.
-#define SD_DMA_MODE         1                                                                      /// In DMA mode, it is recommended to increase the setting of SDIO_TRANSFER_CLK_DIV if there are problems with reading and writing.   
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SDIO Various error enumeration definitions
-////////////////////////////////////////////////////////////////////////////////
-
-typedef enum {
-    SD_CMD_CRC_FAIL = 1,                                                                    ///< Command response received (but CRC check failed)
-    SD_DATA_CRC_FAIL,                                                                       ///< Data bock sent/received (CRC check Failed)
-    SD_CMD_RSP_TIMEOUT,                                                                     ///< Command response timeout
-    SD_DATA_TIMEOUT,                                                                        ///< Data time out
-    SD_TX_UNDERRUN,                                                                         ///< Transmit FIFO under-run
-    SD_RX_OVERRUN,                                                                          ///< Receive FIFO over-run
-    SD_START_BIT_ERR,                                                                       ///< Start bit not detected on all data signals in widE bus mode
-    SD_CMD_OUT_OF_RANGE,                                                                    ///< CMD's argument was out of range.
-    SD_ADDR_MISALIGNED,                                                                     ///< Misaligned address
-    SD_BLOCK_LEN_ERR,                                                                       ///< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length
-    SD_ERASE_SEQ_ERR,                                                                       ///< An error in the sequence of erase command occurs.
-    SD_BAD_ERASE_PARAM,                                                                     ///< An Invalid selection for erase groups
-    SD_WRITE_PROT_VIOLATION,                                                                ///< Attempt to program a write protect block
-    SD_LOCK_UNLOCK_FAILED,                                                                  ///< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card
-    SD_COM_CRC_FAILED,                                                                      ///< CRC check of the previous command failed
-    SD_ILLEGAL_CMD,                                                                         ///< Command is not legal for the card state
-    SD_CARD_ECC_FAILED,                                                                     ///< Card internal ECC was applied but failed to correct the data
-    SD_CC_ERROR,                                                                            ///< Internal card controller error
-    SD_GENERAL_UNKNOWN_ERROR,                                                               ///< General or Unknown error
-    SD_STREAM_READ_UNDERRUN,                                                                ///< The card could not sustain data transfer in stream read operation.
-    SD_STREAM_WRITE_OVERRUN,                                                                ///< The card could not sustain data programming in stream mode
-    SD_CID_CSD_OVERWRITE,                                                                   ///< CID/CSD overwrite error
-    SD_WP_ERASE_SKIP,                                                                       ///< only partial address space was erased
-    SD_CARD_ECC_DISABLED,                                                                   ///< Command has been executed without using internal ECC
-    SD_ERASE_RESET,                                                                         ///< Erase sequence was cleared before executing because an out of erase sequence command was received
-    SD_AKE_SEQ_ERROR,                                                                       ///< Error in sequence of authentication.
-    SD_INVALID_VOLTRANGE,                                                                   ///< SD invalid voltage range,
-    SD_ADDR_OUT_OF_RANGE,                                                                   ///< SD addresses are out of range,
-    SD_SWITCH_ERROR,                                                                        ///< SD switch error,
-    SD_SDIO_DISABLED,                                                                       ///< SD SDIO disability,
-    SD_SDIO_FUNCTION_BUSY,                                                                  ///< SD SDIO function busy,
-    SD_SDIO_FUNCTION_FAILED,                                                                ///< SD SDIO failed,
-    SD_SDIO_UNKNOWN_FUNCTION,                                                               ///< SDIO unknown function,
-    SD_INTERNAL_ERROR,                                                                      ///< SD internal error,
-    SD_NOT_CONFIGURED,                                                                      ///< SD is not configured,
-    SD_REQUEST_PENDING,                                                                     ///< The SD request waits,
-    SD_REQUEST_NOT_APPLICABLE,                                                              ///< The SD requirement does not apply,
-    SD_INVALID_PARAMETER,                                                                   ///< Invalid SD parameter,
-    SD_UNSUPPORTED_FEATURE,                                                                 ///< Features not supported by SD,
-    SD_UNSUPPORTED_HW,                                                                      ///< HW not supported by SD,
-    SD_ERROR,                                                                               ///< SD error
-    SD_OK = 0                                                                               ///< SD OK
-} SD_Error;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SD card CSD register data
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u8  CSDStruct;                                                                                ///< CSD structure
-    u8  SysSpecVersion;                                                                           ///< System specification version
-    u8  Reserved1;                                                                                ///< Reserved
-    u8  TAAC;                                                                                     ///< Data read access-time 1
-    u8  NSAC;                                                                                     ///< Data read access-time 2 in CLK cycles
-    u8  MaxBusClkFrec;                                                                            ///< Max. bus clock frequency
-    u16 CardComdClasses;                                                                          ///< Card command classes
-    u8  RdBlockLen;                                                                               ///< Max. read data block length
-    u8  PartBlockRead;                                                                            ///< Partial blocks for read allowed
-    u8  WrBlockMisalign;                                                                          ///< Write block misalignment
-    u8  RdBlockMisalign;                                                                          ///< Read block misalignment
-    u8  DSRImpl;                                                                                  ///< DSR implemented
-    u8  Reserved2;                                                                                ///< Reserved
-    u32 DeviceSize;                                                                               ///< Device Size
-    u8  MaxRdCurrentVDDMin;                                                                       ///< Max. read current @ VDD min
-    u8  MaxRdCurrentVDDMax;                                                                       ///< Max. read current @ VDD max
-    u8  MaxWrCurrentVDDMin;                                                                       ///< Max. write current @ VDD min
-    u8  MaxWrCurrentVDDMax;                                                                       ///< Max. write current @ VDD max
-    u8  DeviceSizeMul;                                                                            ///< Device size multiplier
-    u8  EraseGrSize;                                                                              ///< Erase group size
-    u8  EraseGrMul;                                                                               ///< Erase group size multiplier
-    u8  WrProtectGrSize;                                                                          ///< Write protect group size
-    u8  WrProtectGrEnable;                                                                        ///< Write protect group enable
-    u8  ManDeflECC;                                                                               ///< Manufacturer default ECC
-    u8  WrSpeedFact;                                                                              ///< Write speed factor
-    u8  MaxWrBlockLen;                                                                            ///< Max. write data block length
-    u8  WriteBlockPaPartial;                                                                      ///< Partial blocks for write allowed
-    u8  Reserved3;                                                                                ///< Reserded
-    u8  ContentProtectAppli;                                                                      ///< Content protection application
-    u8  FileFormatGrouop;                                                                         ///< File format group
-    u8  CopyFlag;                                                                                 ///< Copy flag (OTP)
-    u8  PermWrProtect;                                                                            ///< Permanent write protection
-    u8  TempWrProtect;                                                                            ///< Temporary write protection
-    u8  FileFormat;                                                                               ///< File Format
-    u8  ECC;                                                                                      ///< ECC code
-    u8  CSD_CRC;                                                                                  ///< CSD CRC
-    u8  Reserved4;                                                                                ///< always 1
-} SD_CSD;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SD card CID register data
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u8  ManufacturerID;                                                                           ///< ManufacturerID
-    u16 OEM_AppliID;                                                                              ///< OEM/Application ID
-    u32 ProdName1;                                                                                ///< Product Name part1
-    u8  ProdName2;                                                                                ///< Product Name part2
-    u8  ProdRev;                                                                                  ///< Product Revision
-    u32 ProdSN;                                                                                   ///< Product Serial Number
-    u8  Reserved1;                                                                                ///< Reserved1
-    u16 ManufactDate;                                                                             ///< Manufacturing Date
-    u8  CID_CRC;                                                                                  ///< CID CRC
-    u8  Reserved2;                                                                                ///< always 1
-} SD_CID;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SD state
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SD_CARD_READY                  = ((u32)0x00000001),
-    SD_CARD_IDENTIFICATION         = ((u32)0x00000002),
-    SD_CARD_STANDBY                = ((u32)0x00000003),
-    SD_CARD_TRANSFER               = ((u32)0x00000004),
-    SD_CARD_SENDING                = ((u32)0x00000005),
-    SD_CARD_RECEIVING              = ((u32)0x00000006),
-    SD_CARD_PROGRAMMING            = ((u32)0x00000007),
-    SD_CARD_DISCONNECTED           = ((u32)0x00000008),
-    SD_CARD_ERROR                  = ((u32)0x000000FF)
-} SDCardState;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SD message ,include CSD,CID data
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    SD_CSD SD_csd;
-    SD_CID SD_cid;
-    long long CardCapacity;
-    u32 CardBlockSize;
-    u16 RCA;
-    u8 CardType;
-} SD_CardInfo;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SDIO init
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u8 SDIO_MDEN;
-    u8 SDIO_DATWT;
-    u8 SDIO_SelPTSM;
-    u8 SDIO_CLKSP;
-    u8 SDIO_OUTM;
-    u8 SDIO_SelSM;
-    u8 SDIO_OPMSel;
-} SDIO_InitTypeDef;
-
-typedef struct {
-    u32 SDIO_Argument;  ///Specifies the SDIO command argument which is sent
-    ///to a card as part of a command message. If a command
-    ///contains an argument, it must be loaded into this register
-    ///before writing the command to the command register
-
-    u32 SDIO_CmdIndex;  ///Specifies the SDIO command index. It must be lower than 0x40.
-
-    u32 SDIO_Response;  ///Specifies the SDIO response type.
-    ///This parameter can be a value of @ref SDIO_Response_Type
-
-    u32 SDIO_Wait;      ///Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
-    ///This parameter can be a value of @ref SDIO_Wait_Interrupt_State
-
-///    u32 SDIO_CPSM;      ///Specifies whether SDIO Command path state machine (CPSM)
-    ///is enabled or disabled.
-    ///This parameter can be a value of @ref SDIO_CPSM_State
-} SDIO_CmdInitTypeDef;
-typedef struct {
-    u32 SDIO_DataTimeOut;   // < Specifies the data timeout period in card bus clock periods.
-    //
-    u32 SDIO_DataLength;    // < Specifies the number of data bytes to be transferred.
-    //
-    u32 SDIO_DataBlockSize; // < Specifies the data block size for block transfer.
-    // This parameter can be a value of @ref SDIO_Data_Block_Size
-    //
-    u32 SDIO_TransferDir;   // < Specifies the data transfer direction, whether the transfer
-    // is a read or write.
-    // This parameter can be a value of @ref SDIO_Transfer_Direction
-    //
-//    u32 SDIO_TransferMode;  // < Specifies whether data transfer is in stream or block mode.
-//                                 // This parameter can be a value of @ref SDIO_Transfer_Type
-//                                 //
-//    u32 SDIO_DPSM;          // < Specifies whether SDIO Data path state machine (DPSM)
-//                                 //    is enabled or disabled.
-//                                 //    This parameter can be a value of @ref SDIO_DPSM_State
-} SDIO_DataInitTypeDef;
-
-
-
-extern SD_CardInfo SDCardInfo;
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup SDIO Ö¸instruction set
-/// @{
-#define SD_CMD_GO_IDLE_STATE                       ((u8)0)
-#define SD_CMD_SEND_OP_COND                        ((u8)1)
-#define SD_CMD_ALL_SEND_CID                        ((u8)2)
-#define SD_CMD_SET_REL_ADDR                        ((u8)3)
-#define SD_CMD_SET_DSR                             ((u8)4)
-#define SD_CMD_SDIO_SEN_OP_COND                    ((u8)5)
-#define SD_CMD_HS_SWITCH                           ((u8)6)
-#define SD_CMD_SEL_DESEL_CARD                      ((u8)7)
-#define SD_CMD_HS_SEND_EXT_CSD                     ((u8)8)
-#define SD_CMD_SEND_CSD                            ((u8)9)
-#define SD_CMD_SEND_CID                            ((u8)10)
-#define SD_CMD_READ_DAT_UNTIL_STOP                 ((u8)11)
-#define SD_CMD_STOP_TRANSMISSION                   ((u8)12)
-#define SD_CMD_SEND_STATUS                         ((u8)13)
-#define SD_CMD_HS_BUSTEST_READ                     ((u8)14)
-#define SD_CMD_GO_INACTIVE_STATE                   ((u8)15)
-#define SD_CMD_SET_BLOCKLEN                        ((u8)16)
-#define SD_CMD_READ_SINGLE_BLOCK                   ((u8)17)
-#define SD_CMD_READ_MULT_BLOCK                     ((u8)18)
-#define SD_CMD_HS_BUSTEST_WRITE                    ((u8)19)
-#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((u8)20)
-#define SD_CMD_SET_BLOCK_COUNT                     ((u8)23)
-#define SD_CMD_WRITE_SINGLE_BLOCK                  ((u8)24)
-#define SD_CMD_WRITE_MULT_BLOCK                    ((u8)25)
-#define SD_CMD_PROG_CID                            ((u8)26)
-#define SD_CMD_PROG_CSD                            ((u8)27)
-#define SD_CMD_SET_WRITE_PROT                      ((u8)28)
-#define SD_CMD_CLR_WRITE_PROT                      ((u8)29)
-#define SD_CMD_SEND_WRITE_PROT                     ((u8)30)
-#define SD_CMD_SD_ERASE_GRP_START                  ((u8)32)
-#define SD_CMD_SD_ERASE_GRP_END                    ((u8)33)
-#define SD_CMD_ERASE_GRP_START                     ((u8)35)
-#define SD_CMD_ERASE_GRP_END                       ((u8)36)
-#define SD_CMD_ERASE                               ((u8)38)
-#define SD_CMD_FAST_IO                             ((u8)39)
-#define SD_CMD_GO_IRQ_STATE                        ((u8)40)
-#define SD_CMD_LOCK_UNLOCK                         ((u8)42)
-#define SD_CMD_APP_CMD                             ((u8)55)
-#define SD_CMD_GEN_CMD                             ((u8)56)
-#define SD_CMD_NO_CMD                              ((u8)64)
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup Following commands are SD Card Specific commands.
-/// @{
-#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((u8)6)
-#define SD_CMD_SD_APP_STAUS                        ((u8)13)
-#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((u8)22)
-#define SD_CMD_SD_APP_OP_COND                      ((u8)41)
-#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((u8)42)
-#define SD_CMD_SD_APP_SEND_SCR                     ((u8)51)
-#define SD_CMD_SDIO_RW_DIRECT                      ((u8)52)
-#define SD_CMD_SDIO_RW_EXTENDED                    ((u8)53)
-
-#define SD_CMD_SD_APP_GET_MKB                      ((u8)43)
-#define SD_CMD_SD_APP_GET_MID                      ((u8)44)
-#define SD_CMD_SD_APP_SET_CER_RN1                  ((u8)45)
-#define SD_CMD_SD_APP_GET_CER_RN2                  ((u8)46)
-#define SD_CMD_SD_APP_SET_CER_RES2                 ((u8)47)
-#define SD_CMD_SD_APP_GET_CER_RES1                 ((u8)48)
-#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((u8)18)
-#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((u8)25)
-#define SD_CMD_SD_APP_SECURE_ERASE                 ((u8)38)
-#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((u8)49)
-#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((u8)48)
-/// @}
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup SD support define.
-/// @{
-#define SDIO_STD_CAPACITY_SD_CARD_V1_1             ((u32)0x00000000)
-#define SDIO_STD_CAPACITY_SD_CARD_V2_0             ((u32)0x00000001)
-#define SDIO_HIGH_CAPACITY_SD_CARD                 ((u32)0x00000002)
-#define SDIO_MULTIMEDIA_CARD                       ((u32)0x00000003)
-#define SDIO_SECURE_DIGITAL_IO_CARD                ((u32)0x00000004)
-#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD            ((u32)0x00000005)
-#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD          ((u32)0x00000006)
-#define SDIO_HIGH_CAPACITY_MMC_CARD                ((u32)0x00000007)
-/// @}
-
-#ifndef NULL
-#define NULL 0
-#endif
-#define SDIO_STATIC_FLAGS               ((u32)0x000005FF)
-#define SDIO_CMD0TIMEOUT                ((u32)0x00010000)
-#define SDIO_DATATIMEOUT                ((u32)0xFFFFFFFF)
-#define SDIO_FIFO_Address               ((u32)0x40018080)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup Mask for errors Card Status R1 (OCR Register)
-/// @{
-#define SD_OCR_ADDR_OUT_OF_RANGE        ((u32)0x80000000)
-#define SD_OCR_ADDR_MISALIGNED          ((u32)0x40000000)
-#define SD_OCR_BLOCK_LEN_ERR            ((u32)0x20000000)
-#define SD_OCR_ERASE_SEQ_ERR            ((u32)0x10000000)
-#define SD_OCR_BAD_ERASE_PARAM          ((u32)0x08000000)
-#define SD_OCR_WRITE_PROT_VIOLATION     ((u32)0x04000000)
-#define SD_OCR_LOCK_UNLOCK_FAILED       ((u32)0x01000000)
-#define SD_OCR_COM_CRC_FAILED           ((u32)0x00800000)
-#define SD_OCR_ILLEGAL_CMD              ((u32)0x00400000)
-#define SD_OCR_CARD_ECC_FAILED          ((u32)0x00200000)
-#define SD_OCR_CC_ERROR                 ((u32)0x00100000)
-#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((u32)0x00080000)
-#define SD_OCR_STREAM_READ_UNDERRUN     ((u32)0x00040000)
-#define SD_OCR_STREAM_WRITE_OVERRUN     ((u32)0x00020000)
-#define SD_OCR_CID_CSD_OVERWRIETE       ((u32)0x00010000)
-#define SD_OCR_WP_ERASE_SKIP            ((u32)0x00008000)
-#define SD_OCR_CARD_ECC_DISABLED        ((u32)0x00004000)
-#define SD_OCR_ERASE_RESET              ((u32)0x00002000)
-#define SD_OCR_AKE_SEQ_ERROR            ((u32)0x00000008)
-#define SD_OCR_ERRORBITS                ((u32)0xFDFFE008)
-/// @}
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup Masks for R6 Response
-/// @{
-#define SD_R6_GENERAL_UNKNOWN_ERROR     ((u32)0x00002000)
-#define SD_R6_ILLEGAL_CMD               ((u32)0x00004000)
-#define SD_R6_COM_CRC_FAILED            ((u32)0x00008000)
-/// @}
-#define SD_VOLTAGE_WINDOW_SD            ((u32)0x80100000)
-#define SD_HIGH_CAPACITY                ((u32)0x40000000)
-#define SD_STD_CAPACITY                 ((u32)0x00000000)
-#define SD_CHECK_PATTERN                ((u32)0x000001AA)
-#define SD_VOLTAGE_WINDOW_MMC           ((u32)0x80FF8000)
-
-#define SD_MAX_VOLT_TRIAL               ((u32)0x0000FFFF)
-#define SD_ALLZERO                      ((u32)0x00000000)
-
-#define SD_WIDE_BUS_SUPPORT             ((u32)0x00040000)
-#define SD_SINGLE_BUS_SUPPORT           ((u32)0x00010000)
-#define SD_CARD_LOCKED                  ((u32)0x02000000)
-#define SD_CARD_PROGRAMMING             ((u32)0x00000007)
-#define SD_CARD_RECEIVING               ((u32)0x00000006)
-#define SD_DATATIMEOUT                  ((u32)0xFFFFFFFF)
-#define SD_0TO7BITS                     ((u32)0x000000FF)
-#define SD_8TO15BITS                    ((u32)0x0000FF00)
-#define SD_16TO23BITS                   ((u32)0x00FF0000)
-#define SD_24TO31BITS                   ((u32)0xFF000000)
-#define SD_MAX_DATA_LENGTH              ((u32)0x01FFFFFF)
-
-#define SD_HALFFIFO                     ((u32)0x00000008)
-#define SD_HALFFIFOBYTES                ((u32)0x00000020)
-
-#define SD_CCCC_LOCK_UNLOCK             ((u32)0x00000080)
-#define SD_CCCC_WRITE_PROT              ((u32)0x00000040)
-#define SD_CCCC_ERASE                   ((u32)0x00000020)
-
-
-#define SDIO_SEND_IF_COND               ((u32)0x00000008)
-
-#define SDIO_Response_No                    ((u32)0x00)
-#define SDIO_Response_Short                 ((u32)0x01)
-#define SDIO_Response_Long                  ((u32)0x03)
-
-#define SDIO_DataBlockSize_1b               ((u32)0x00000000)
-#define SDIO_DataBlockSize_2b               ((u32)0x00000001)
-#define SDIO_DataBlockSize_4b               ((u32)0x00000002)
-#define SDIO_DataBlockSize_8b               ((u32)0x00000003)
-#define SDIO_DataBlockSize_16b              ((u32)0x00000004)
-#define SDIO_DataBlockSize_32b              ((u32)0x00000005)
-#define SDIO_DataBlockSize_64b              ((u32)0x00000006)
-#define SDIO_DataBlockSize_128b             ((u32)0x00000007)
-#define SDIO_DataBlockSize_256b             ((u32)0x00000008)
-#define SDIO_DataBlockSize_512b             ((u32)0x00000009)
-#define SDIO_DataBlockSize_1024b            ((u32)0x0000000A)
-#define SDIO_DataBlockSize_2048b            ((u32)0x0000000B)
-#define SDIO_DataBlockSize_4096b            ((u32)0x0000000C)
-#define SDIO_DataBlockSize_8192b            ((u32)0x0000000D)
-#define SDIO_DataBlockSize_16384b           ((u32)0x0000000E)
-//Define the data block length when the block data transfer mode is selected:
-//0000: (0 decimal) lock length  = 2^0 = 1 byte
-//0001: (1 decimal) lock length  = 2^1 = 2 bytes
-//0010: (2 decimal) lock length  = 2^2 = 4 bytes
-//0011: (3 decimal) lock length  = 2^3 = 8 bytes
-//0100: (4 decimal) lock length  = 2^4 = 16 bytes
-//0101: (5 decimal) lock length  = 2^5 = 32 bytes
-//0110: (6 decimal) lock length  = 2^6 = 64 bytes
-//0111: (7 decimal) lock length  = 2^7 = 128 bytes
-//1000: (8 decimal) lock length  = 2^8 = 256 bytes
-//1001: (9 decimal) lock length  = 2^9 = 512 bytes
-//1010: (10 decimal) lock length = 2^10 = 1024 bytes
-//1011: (11 decimal) lock length = 2^11 = 2048 bytes
-//1100: (12 decimal) lock length = 2^12 = 4096 bytes
-//1101: (13 decimal) lock length = 2^13 = 8192 bytes
-//1110: (14 decimal) lock length = 2^14 = 16384 bytes
-//1111: (15 decimal) reserved
-
-
-#define SDIO_TransferDir_ToCard             ((u32)0x00000000)
-#define SDIO_TransferDir_ToSDIO             ((u32)0x00000002)
-
-#define SDIO_Wait_No                        ((u32)0x00000000) // SDIO No Wait, TimeOut is enabled 
-#define SDIO_Wait_IT                        ((u32)0x00000100) //SDIO Wait Interrupt Request 
-#define SDIO_Wait_Pend                      ((u32)0x00000200) // SDIO Wait End of transfer 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup I2C_Exported_Functions
-/// @{
-void SDIO_DeInit(void);
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
-void SDIO_ClockSet(u32 value);
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
-void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state);
-void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state);
-void SDIO_Clock_Set(u8 clkdiv);
-void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg);
-SD_Error SD_PowerOFF(void);
-SD_Error CmdError(void);
-SD_Error CmdResp2Error(void);
-SD_Error CmdResp3Error(void);
-SD_Error CmdResp6Error(u8 cmd, u16* prca);
-SD_Error CmdResp7Error(void);
-SD_Error CmdResp1Error(u8 cmd);
-void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir);
-void SDIO_ClearITPendingBit(u32 SDIO_IT);
-FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG);
-u32 SDIO_GetTimeOutCounter(void);
-u32 SDIO_ReadData(void);
-void SDIO_WriteData(u32 tempbuff);
-void SDIO_DMACmd(FunctionalState state);
-/// @}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h
deleted file mode 100644
index db1a9aa30..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_spi.h
+++ /dev/null
@@ -1,351 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_spi.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SPI
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_SPI_H
-#define __HAL_SPI_H
-
-// Files includes
-#include "types.h"
-#include "reg_spi.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup SPI_HAL
-/// @brief SPI HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup SPI_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI mode enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_Mode_Slave  = 0x0000,        ///< SPI slave mode
-    SPI_Mode_Master = SPI_GCR_MODE   ///< SPI master mode
-} SPI_Mode_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI data size enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_DataSize_8b  = 0x0000,         ///< 8 bits valid data
-    SPI_DataSize_32b = SPI_GCR_DWSEL   ///< 32 bits valid data
-} SPI_DataSize_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI clock polarity enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_CPOL_Low  = 0x0000,                                                     ///< The clock is low in idle state.
-    SPI_CPOL_High = SPI_CCR_CPOL                                                ///< The clock is high in idle state.
-} SPI_CPOL_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI clock phase enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_CPHA_2Edge = 0x0000,                                                    ///< Data sampling starts from the second clock edge.
-    SPI_CPHA_1Edge = SPI_CCR_CPHA                                               ///< Data sampling starts from the first clock edge.
-} SPI_CPHA_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI nss control mode enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_NSS_Soft = 0x0000,
-    SPI_NSS_Hard = SPI_GCR_NSS
-} SPI_NSS_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI baud rate prescaler enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_BaudRatePrescaler_2   = 0x0002,                                         ///< SCK clock devide by 2
-    SPI_BaudRatePrescaler_4   = 0x0004,                                         ///< SCK clock devide by 4
-    SPI_BaudRatePrescaler_8   = 0x0008,                                         ///< SCK clock devide by 7
-    SPI_BaudRatePrescaler_16  = 0x0010,                                         ///< SCK clock devide by 16
-    SPI_BaudRatePrescaler_32  = 0x0020,                                         ///< SCK clock devide by 32
-    SPI_BaudRatePrescaler_64  = 0x0040,                                         ///< SCK clock devide by 64
-    SPI_BaudRatePrescaler_128 = 0x0080,                                         ///< SCK clock devide by 128
-    SPI_BaudRatePrescaler_256 = 0x0100                                          ///< SCK clock devide by 256
-} SPI_BaudRatePrescaler_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI first bit enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_FirstBit_MSB = 0x0000,                                                  ///< Data transfers start from MSB
-    SPI_FirstBit_LSB = SPI_CCR_LSBFE                                            ///< Data transfers start from LSB
-} SPI_FirstBit_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI FIFO trigger level enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_RXTLF = SPI_GCR_RXTLF_Half,                                             ///< RX FIFO trigger level
-    SPI_TXTLF = SPI_GCR_TXTLF_Half                                              ///< TX FIFO trigger level
-} SPI_TLF_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI bit derection enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_Direction_Rx,                                                           ///< Receive enable
-    SPI_Direction_Tx,                                                           ///< Transmit enable
-    SPI_Disable_Rx,                                                             ///< Receive disable
-    SPI_Disable_Tx                                                              ///< Transmit disable
-} SPI_Direction_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI flag enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_FLAG_RXAVL       = SPI_SR_RXAVL,                                        ///< Receive 1 byte available data flag
-    SPI_FLAG_TXEPT       = SPI_SR_TXEPT,                                        ///< Transmitter empty flag
-    SPI_FLAG_TXFULL      = SPI_SR_TXFULL,                                       ///< Transmitter FIFO full status flag
-    SPI_FLAG_RXAVL_4BYTE = SPI_SR_RXAVL_4BYTE                                   ///< Receive 4 bytes available data flag
-} SPI_FLAG_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI slave mode data edge adjust enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_SlaveAdjust_LOW,                                                        ///< SPI slave mode data edge adjust in low speed mode
-    SPI_SlaveAdjust_FAST                                                        ///< SPI slave mode data edge adjust in fast speed mode
-} SPI_SlaveAdjust_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI data edge adjust enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_DataEdgeAdjust_LOW,                                                     ///< SPI data edge adjust in low speed mode
-    SPI_DataEdgeAdjust_FAST                                                     ///< SPI data edge adjust in fast speed mode
-} SPI_DataEdgeAdjust_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI interruput enum definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    SPI_IT_TXEPT    = 0x40,                                                     ///< Transmitter empty interrupt
-    SPI_IT_RXFULL   = 0x20,                                                     ///< RX FIFO full interrupt
-    SPI_IT_RXMATCH  = 0x10,                                                     ///< Receive data match the RXDNR number interrut
-    SPI_IT_RXOERR   = 0x08,                                                     ///< Receive overrun error interrupt
-    SPI_IT_UNDERRUN = 0x04,                                                     ///< Underrun interrupt
-    SPI_IT_RX       = 0x02,                                                     ///< Receive available data interrupt
-    SPI_IT_TX       = 0x01                                                      ///< Transmit FIFO available interrupt
-} SPI_IT_TypeDef;
-
-
-typedef enum {
-    I2S_Standard_Phillips               = 0x0000,
-    I2S_Standard_MSB                    = 0x0010,
-    I2S_Standard_LSB                    = 0x0020,
-    I2S_Standard_PCMShort               = 0x0030,
-    I2S_Standard_PCMLong                = 0x00B0,
-} SPI_I2S_STANDARD_TypeDef;
-
-
-typedef enum {
-    I2S_DataFormat_16b              = 0x0000,
-    I2S_DataFormat_16bextended      = 0x0001,
-    I2S_DataFormat_24b              = 0x0003,
-    I2S_DataFormat_32b              = 0x0005,
-} SPI_I2S_DATAFORMAT_TypeDef;
-typedef enum {
-    I2S_AudioFreq_192k               = (192000),
-    I2S_AudioFreq_96k                = (96000),
-    I2S_AudioFreq_48k                = (48000),
-    I2S_AudioFreq_44k                = (44100),
-    I2S_AudioFreq_32k                = (32000),
-    I2S_AudioFreq_24k                = (24000),
-    I2S_AudioFreq_22k                = (22050),
-    I2S_AudioFreq_16k                = (16000),
-    I2S_AudioFreq_11k                = (11025),
-    I2S_AudioFreq_12k                = (12000),
-    I2S_AudioFreq_8k                 = (8000),
-    I2S_AudioFreq_4k                 = (4000),
-    I2S_AudioFreq_Default            = (2),
-} SPI_I2S_AUDIO_FREQ_TypeDef;
-typedef enum {
-    I2S_Mode_SlaveTx                = 0x0000,
-    I2S_Mode_SlaveRx                = 0x0100,
-    I2S_Mode_MasterTx               = 0x0200,
-    I2S_Mode_MasterRx               = 0x0300,
-} SPI_I2S_TRANS_MODE_TypeDef;
-
-typedef enum {
-    I2S_MCLKOutput_Enable           = 0x0800,
-    I2S_MCLKOutput_Disable          = 0x0000,
-} SPI_I2S_MCLK_OUTPUT_TypeDef;
-
-typedef enum {
-    I2S_CPOL_Low  = 0x0000,                                                     ///< The clock is low in idle state.
-    I2S_CPOL_High = SPI_CCR_CPOL                                                ///< The clock is high in idle state.
-} SPI_I2S_CPOL_TypeDef;
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI Init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    SPI_Mode_TypeDef                SPI_Mode;                                   ///< Specifies the SPI operating mode
-    SPI_DataSize_TypeDef            SPI_DataSize;                               ///< Specifies the SPI available data size
-    u8                              SPI_DataWidth;                              ///< SPI data length
-    SPI_CPOL_TypeDef                SPI_CPOL;                                   ///< Specifies the serial clock steady state
-    SPI_CPHA_TypeDef                SPI_CPHA;                                   ///< Specifies the clock active edge for the bit capture
-    SPI_NSS_TypeDef                 SPI_NSS;                                    ///< Specifies whether the NSS signal is managed by hardware or by software
-    SPI_BaudRatePrescaler_TypeDef   SPI_BaudRatePrescaler;                      ///< Specifies the Baud Rate prescaler value which will be
-    ///< used to configure the transmit and receive SCK clock
-    SPI_FirstBit_TypeDef            SPI_FirstBit;                               ///< Specifies whether data transfers start from MSB or LSB bit
-    //  u16     SPI_length;
-} SPI_InitTypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  I2S Init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    SPI_I2S_TRANS_MODE_TypeDef      I2S_Mode;                                   ///< Specifies the I2S operating mode.
-    SPI_I2S_STANDARD_TypeDef        I2S_Standard;                               ///< Specifies the standard used for the I2S communication.
-    SPI_I2S_DATAFORMAT_TypeDef      I2S_DataFormat;                             ///< Specifies the data format for the I2S communication.
-    SPI_I2S_MCLK_OUTPUT_TypeDef     I2S_MCLKOutput;                             ///< Specifies whether the I2S MCLK output is enabled or not.
-    SPI_I2S_AUDIO_FREQ_TypeDef      I2S_AudioFreq;                              ///< Specifies the frequency selected for the I2S communication.
-    SPI_I2S_CPOL_TypeDef            I2S_CPOL;                                   ///< Specifies the idle state of the I2S clock.
-} I2S_InitTypeDef;
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup SPI_Exported_Constants
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup SPI_Register_Mask
-/// @{
-
-#define GCR_Mask ((u32)0x0FFF)
-#define CCR_Mask ((u32)0x003F)
-#define BRR_Mask ((u32)0xFFFF)
-#define ECR_Mask ((u32)0x001F)
-
-/// @}
-
-
-// SPI_7bit_8bit data width
-#define SPI_DataWidth_1b                  ((u16)0x0001)
-#define SPI_DataWidth_2b                  ((u16)0x0002)
-#define SPI_DataWidth_3b                  ((u16)0x0003)
-#define SPI_DataWidth_4b                  ((u16)0x0004)
-#define SPI_DataWidth_5b                  ((u16)0x0005)
-#define SPI_DataWidth_6b                  ((u16)0x0006)
-#define SPI_DataWidth_7b                  ((u16)0x0007)
-#define SPI_DataWidth_8b                  ((u16)0x0008)
-#define SPI_DataWidth_9b                  ((u16)0x0009)
-#define SPI_DataWidth_10b                 ((u16)0x000a)
-#define SPI_DataWidth_11b                 ((u16)0x000b)
-#define SPI_DataWidth_12b                 ((u16)0x000c)
-#define SPI_DataWidth_13b                 ((u16)0x000d)
-#define SPI_DataWidth_14b                 ((u16)0x000e)
-#define SPI_DataWidth_15b                 ((u16)0x000f)
-#define SPI_DataWidth_16b                 ((u16)0x0010)
-#define SPI_DataWidth_17b                 ((u16)0x0011)
-#define SPI_DataWidth_18b                 ((u16)0x0012)
-#define SPI_DataWidth_19b                 ((u16)0x0013)
-#define SPI_DataWidth_20b                 ((u16)0x0014)
-#define SPI_DataWidth_21b                 ((u16)0x0015)
-#define SPI_DataWidth_22b                 ((u16)0x0016)
-#define SPI_DataWidth_23b                 ((u16)0x0017)
-#define SPI_DataWidth_24b                 ((u16)0x0018)
-#define SPI_DataWidth_25b                 ((u16)0x0019)
-#define SPI_DataWidth_26b                 ((u16)0x001a)
-#define SPI_DataWidth_27b                 ((u16)0x001b)
-#define SPI_DataWidth_28b                 ((u16)0x001c)
-#define SPI_DataWidth_29b                 ((u16)0x001d)
-#define SPI_DataWidth_30b                 ((u16)0x001e)
-#define SPI_DataWidth_31b                 ((u16)0x001f)
-#define SPI_DataWidth_32b                 ((u16)0x0000)
-
-
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup SPI_Exported_Variables
-/// @{
-
-#ifdef _HAL_SPI_C_
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup SPI_Exported_Functions
-/// @{
-
-void SPI_DeInit(SPI_TypeDef* spi);
-void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct);
-void SPI_StructInit(SPI_InitTypeDef* init_struct);
-void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state);
-void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state);
-void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
-void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state);
-void SPI_SendData(SPI_TypeDef* spi, u32 data);
-void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss);
-
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction);
-void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
-void SPI_RxBytes(SPI_TypeDef* spi, u16 number);
-void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value);
-
-bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size);
-void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize);
-u32 SPI_ReceiveData(SPI_TypeDef* spi);
-
-FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag);
-
-ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt);
-
-////////////////////////////////////////////////////////////////////////////////
-//          Extended function interface
-////////////////////////////////////////////////////////////////////////////////
-void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state);
-void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrput, FunctionalState state);
-void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state);
-void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state);
-void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value);
-void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state);
-void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct);
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif //__HAL_SPI_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h
deleted file mode 100644
index e034f9626..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_syscfg.h
+++ /dev/null
@@ -1,83 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_syscfg.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE EXTI
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_SYSCFG_H
-#define __HAL_SYSCFG_H
-
-// Files includes
-#include "types.h"
-#include "mm32_device.h"
-#include "hal_EXTI.H"
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup SYSCFG_HAL
-/// @brief SYSCFG HAL modules
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup SYSCFG_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SYSCFG mode enumeration
-////////////////////////////////////////////////////////////////////////////////
-// @defgroup SYSCFG_Memory_Remap_Config
-#define SYSCFG_MemoryRemap_Flash                ((u8)0x00)
-#define SYSCFG_MemoryRemap_SystemMemory         ((u8)0x01)
-#define SYSCFG_MemoryRemap_SRAM                 ((u8)0x03)
-
-
-
-
-///
-/// @}
-///
-
-
-
-
-// Exported macro ------------------------------------------------------------
-// Exported functions -------------------------------------------------------
-
-//  Function used to set the SYSCFG configuration to the default reset state
-#define SYSCFG_DeInit                   EXTI_DeInit
-#define SYSCFG_MemoryRemapConfig        EXTI_MemoryRemapConfig
-#define SYSCFG_EXTILineConfig           EXTI_LineConfig
-u32 SYSCFG_GetPendingIT(u32 ITSourceLine);
-void SYSCFG_BreakConfig(u32 SYSCFG_Break);
-FlagStatus SYSCFG_GetFlagStatus(u32 SYSCFG_Flag);
-void SYSCFG_ClearFlag(u32 SYSCFG_Flag);
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif //__HAL_SYSCFG_H 
-////////////////////////////////////////////////////////////////////////////////
-
-
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h
deleted file mode 100644
index 4e57960dd..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_tim.h
+++ /dev/null
@@ -1,755 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_tim.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE TIM
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_TIM_H
-#define __HAL_TIM_H
-
-// Files includes
-#include "types.h"
-#include "reg_tim.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup TIM_HAL
-/// @brief TIM HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup TIM_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Channel
-/// @anchor TIM_Channel
-typedef enum {
-    TIM_Channel_1 = 0x0000,  ///< TIM Channel 1
-    TIM_Channel_2 = 0x0004,  ///< TIM Channel 2
-    TIM_Channel_3 = 0x0008,  ///< TIM Channel 3
-    TIM_Channel_4 = 0x000C,  ///< TIM Channel 4
-    TIM_Channel_5 = 0x0010   ///< TIM Channel 5
-} TIMCHx_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Counter_Mode
-/// @anchor TIM_Counter_Mode
-typedef enum {
-    TIM_CounterMode_Up             = 0x0000,                        ///< TIM Up Counting Mode
-    TIM_CounterMode_Down           = TIM_CR1_DIR,                   ///< TIM Down Counting Mode
-    TIM_CounterMode_CenterAligned1 = TIM_CR1_CMS_CENTERALIGNED1,    ///< TIM Center Aligned Mode1
-    TIM_CounterMode_CenterAligned2 = TIM_CR1_CMS_CENTERALIGNED2,    ///< TIM Center Aligned Mode2
-    TIM_CounterMode_CenterAligned3 = TIM_CR1_CMS_CENTERALIGNED3     ///< TIM Center Aligned Mode3
-} TIMCOUNTMODE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Output_Compare_and_PWM_modes_and_Forced_Action
-/// @anchor TIM_Output_Compare_and_PWM_modes_and_Forced_Action
-typedef enum {
-    TIM_OCMode_Timing         = 0x0000,                         ///< Output compare mode: Timing
-    TIM_OCMode_Active         = 0x0010,                         ///< Output compare mode: Active
-    TIM_OCMode_Inactive       = 0x0020,                         ///< Output compare mode: Inactive
-    TIM_OCMode_Toggle         = 0x0030,                         ///< Output compare mode: Toggle
-    TIM_OCMode_PWM1           = 0x0060,                         ///< Output compare mode: PWM1
-    TIM_OCMode_PWM2           = 0x0070,                         ///< Output compare mode: PWM2
-    TIM_ForcedAction_Active   = 0x0050,                         ///< Force active level on OCnREF
-    TIM_ForcedAction_InActive = 0x0040                          ///< Force inactive level on OCnREF
-} TIMOCMODE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Clock_Division_CKD
-/// @anchor TIM_Clock_Division_CKD
-typedef enum {
-    TIM_CKD_DIV1 = TIM_CR1_CKD_DIV1,                            ///< TDTS = Tck_tim
-    TIM_CKD_DIV2 = TIM_CR1_CKD_DIV2,                            ///< TDTS = 2 * Tck_tim
-    TIM_CKD_DIV4 = TIM_CR1_CKD_DIV4                             ///< TDTS = 4 * Tck_tim
-} TIMCKD_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Internal_Trigger_Selection
-/// @anchor TIM_Internal_Trigger_Selection
-typedef enum {
-    TIM_TS_ITR0    = TIM_SMCR_TS_ITR0,                          ///< Internal Trigger 0
-    TIM_TS_ITR1    = TIM_SMCR_TS_ITR1,                          ///< Internal Trigger 1
-    TIM_TS_ITR2    = TIM_SMCR_TS_ITR2,                          ///< Internal Trigger 2
-    TIM_TS_ITR3    = TIM_SMCR_TS_ITR3,                          ///< Internal Trigger 3
-    TIM_TS_TI1F_ED = TIM_SMCR_TS_TI1F_ED,                       ///< TI1 Edge Detector
-    TIM_TS_TI1FP1  = TIM_SMCR_TS_TI1FP1,                        ///< Filtered Timer Input 1
-    TIM_TS_TI2FP2  = TIM_SMCR_TS_TI2FP2,                        ///< Filtered Timer Input 2
-    TIM_TS_ETRF    = TIM_SMCR_TS_ETRF                           ///< TI1 Edge Detector
-} TIMTS_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Trigger_Output_Source
-/// @anchor TIM_Trigger_Output_Source
-typedef enum {
-    TIM_TRIGSource_Reset  = TIM_CR2_MMS_RESET,                  ///< The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
-    TIM_TRIGSource_Enable = TIM_CR2_MMS_ENABLE,                 ///< The Counter Enable CEN is used as the trigger output (TRIG).
-    TIM_TRIGSource_Update = TIM_CR2_MMS_UPDATE,                 ///< The update event is used as the trigger output (TRIG).
-    TIM_TRIGSource_OC1    = TIM_CR2_MMS_OC1,                    ///< The trigger output sends a positive pulse when the CC1IF flag
-    ///< is to be set, as soon as a capture or compare match occurs (TRIG).
-    TIM_TRIGSource_OC1Ref = TIM_CR2_MMS_OC1REF,                 ///< OC1REF signal is used as the trigger output (TRIG).
-    TIM_TRIGSource_OC2Ref = TIM_CR2_MMS_OC2REF,                 ///< OC2REF signal is used as the trigger output (TRIG).
-    TIM_TRIGSource_OC3Ref = TIM_CR2_MMS_OC3REF,                 ///< OC3REF signal is used as the trigger output (TRIG).
-    TIM_TRIGSource_OC4Ref = TIM_CR2_MMS_OC4REF                  ///< OC4REF signal is used as the trigger output (TRIG).
-} TIMMMS_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Slave_Mode
-/// @anchor TIM_Slave_Mode
-typedef enum {
-    TIM_SlaveMode_Reset = TIM_SMCR_SMS_RESET,                   ///< Rising edge of the selected trigger signal (TRGI) re-initializes
-    ///< the counter and triggers an update of the registers.
-    TIM_SlaveMode_Gated     = TIM_SMCR_SMS_GATED,               ///< The counter clock is enabled when the trigger signal (TRGI) is high.
-    TIM_SlaveMode_Trigger   = TIM_SMCR_SMS_TRIGGER,             ///< The counter starts at a rising edge of the trigger TRGI.
-    TIM_SlaveMode_External1 = TIM_SMCR_SMS_EXTERNAL1            ///< Rising edges of the selected trigger (TRGI) clock the counter.
-} TIMSMSMODE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Event_Source
-/// @anchor TIM_Event_Source
-typedef enum {
-    TIM_EventSource_Update  = TIM_EGR_UG,                       ///< Timer update Event source
-    TIM_EventSource_CC1     = TIM_EGR_CC1G,                     ///< Timer Capture Compare 1 Event source
-    TIM_EventSource_CC2     = TIM_EGR_CC2G,                     ///< Timer Capture Compare 2 Event source
-    TIM_EventSource_CC3     = TIM_EGR_CC3G,                     ///< Timer Capture Compare 3 Event source
-    TIM_EventSource_CC4     = TIM_EGR_CC4G,                     ///< Timer Capture Compare 4 Event source
-    TIM_EventSource_COM     = TIM_EGR_COMG,                     ///< Timer COM event source
-    TIM_EventSource_Trigger = TIM_EGR_TG,                       ///< Timer Trigger Event source
-    TIM_EventSource_Break   = TIM_EGR_BG,                       ///< Timer Break event source
-    TIM_EventSource_CC5     = (s32)0x00010000,                  ///< Timer Capture Compare 5 Event source
-} TIMEGR_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_External_Trigger_Prescaler
-/// @anchor TIM_External_Trigger_Prescaler
-typedef enum {
-    TIM_ExtTRGPSC_OFF  = TIM_SMCR_ETPS_OFF,                     ///< ETRP Prescaler OFF
-    TIM_ExtTRGPSC_DIV2 = TIM_SMCR_ETPS_DIV2,                    ///< ETRP frequency divided by 2
-    TIM_ExtTRGPSC_DIV4 = TIM_SMCR_ETPS_DIV4,                    ///< ETRP frequency divided by 4
-    TIM_ExtTRGPSC_DIV8 = TIM_SMCR_ETPS_DIV8                     ///< ETRP frequency divided by 8
-} TIMEXTTRGPSC_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_TIx_External_Clock_Source
-/// @anchor TIM_TIx_External_Clock_Source
-typedef enum {
-    TIM_TIxExternalCLK1Source_TI1   = TIM_SMCR_TS_TI1FP1,       ///< Filtered Timer Input 1
-    TIM_TIxExternalCLK1Source_TI2   = TIM_SMCR_TS_TI2FP2,       ///< Filtered Timer Input 2
-    TIM_TIxExternalCLK1Source_TI1ED = TIM_SMCR_TS_TI1F_ED       ///< TI1 Edge Detector
-} TIM_TIEXTCLKSRC_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Lock_level
-/// @anchor Lock_level
-typedef enum {
-    TIM_LOCKLevel_OFF = TIM_BDTR_LOCK_OFF,                      ///< No bit is write protected.
-    TIM_LOCKLevel_1   = TIM_BDTR_LOCK_1,                        ///< DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
-    ///< register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
-    TIM_LOCKLevel_2 = TIM_BDTR_LOCK_2,                          ///< LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
-    ///< register, as s32 as the related channel is configured in output through the CCxS
-    ///< bits) as well as OSSR and OSSI bits can no longer be written.
-    TIM_LOCKLevel_3 = TIM_BDTR_LOCK_3                           ///< LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers,
-                      ///< as s32 as the related channel is configured in output through the CCxS bits)
-                      ///< can no longer be written.
-} TIMLOCKLEVEL_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_One_Pulse_Mode
-/// @anchor TIM_One_Pulse_Mode
-typedef enum {
-    TIM_OPMode_Repetitive = 0,                                  ///< Counter is not stopped at update event
-    TIM_OPMode_Single     = TIM_CR1_OPM                         ///< Counter stops counting at the next update event (clearing the bit CEN)
-} TIMOPMODE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Output_Compare_Polarity
-/// @anchor TIM_Output_Compare_Polarity
-typedef enum {
-    TIM_OCPolarity_High,                                        ///< Output Compare active high
-    TIM_OCPolarity_Low = TIM_CCER_CC1P                          ///< Output Compare active low
-} TIMCCxP_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Output_Compare_N_Polarity
-/// @anchor TIM_Output_Compare_N_Polarity
-typedef enum {
-    TIM_OCNPolarity_High,                                       ///< Output Compare active high
-    TIM_OCNPolarity_Low = TIM_CCER_CC1NP                        ///< Output Compare active low
-} TIMCCxNP_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Output_Compare_state
-/// @anchor TIM_Output_Compare_state
-typedef enum {
-    TIM_OutputState_Disable = 0,                                ///< Output Compare Disable
-    TIM_OutputState_Enable  = TIM_CCER_CC1EN                     ///< Output Compare Enable
-} TIMOUTPUTSTATE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Output_Compare_N_state
-/// @anchor TIM_Output_Compare_N_state
-typedef enum {
-    TIM_OutputNState_Disable = 0,                               ///< Output Compare N Disable
-    TIM_OutputNState_Enable  = TIM_CCER_CC1NEN                   ///< Output Compare N Enable
-} TIMOUTPUTNSTATE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Capture_Compare_state
-/// @anchor TIM_Capture_Compare_state
-typedef enum {
-    TIM_CCx_Disable = 0,                                        ///< Capture/Compare Enable
-    TIM_CCx_Enable  = TIM_CCER_CC1EN                             ///< Capture/Compare Enable
-} TIMCCxE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Capture_Compare_N_state
-/// @anchor TIM_Capture_Compare_N_state
-typedef enum {
-    TIM_CCxN_Disable = 0,                                       ///< Capture/Compare N Enable
-    TIM_CCxN_Enable  = TIM_CCER_CC1NEN                           ///< Capture/Compare N Enable
-} TIMCCxNE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Break_Input_enable_disable
-/// @anchor Break_Input_enable_disable
-typedef enum {
-    TIM_Break_Disable = 0,                                      ///< Break inputs (BRK and CSS clock failure event) disabled
-    TIM_Break_Enable  = TIM_BDTR_BKEN                            ///< Break inputs (BRK and CSS clock failure event) enabled
-} TIMBKE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Break_Polarity
-/// @anchor Break_Polarity
-typedef enum {
-    TIM_BreakPolarity_Low  = 0,                                 ///< Break input BRK is active low
-    TIM_BreakPolarity_High = TIM_BDTR_BKP                       ///< Break input BRK is active high
-} TIMBKP_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_AOE_Bit_Set_Reset
-/// @anchor TIM_AOE_Bit_Set_Reset
-typedef enum {
-    TIM_AutomaticOutput_Disable = 0,                            ///< MOE can be set only by software.
-    TIM_AutomaticOutput_Enable  = TIM_BDTR_AOEN                  ///< MOE can be set by software or automatically at the next
-                                  ///< update event (if the break input is not be active).
-} TIMAOE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_DOE_Bit_Set_Reset
-/// @anchor TIM_DOE_Bit_Set_Reset
-typedef enum {
-    TIM_DirectOutput_Disable = 0,                               ///< Direct output disable, output waiting for dead time
-    TIM_DirectOutput_Enable  = TIM_BDTR_DOEN                     ///< Direct output enable, no longer waiting for output after dead time
-} TIMDOE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OSSI_Off_State_Selection_for_Idle_mode_state
-/// @anchor OSSI_Off_State_Selection_for_Idle_mode_state
-typedef enum {
-    TIM_OSSIState_Disable = 0,                                  ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
-    TIM_OSSIState_Enable  = TIM_BDTR_OSSI                       ///< When inactive, OC/OCN outputs are forced first with their idle level
-                            ///< as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1).
-} TIMOSSI_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OSSR_Off_State_Selection_for_Run_mode_state
-/// @anchor OSSR_Off_State_Selection_for_Run_mode_state
-typedef enum {
-    TIM_OSSRState_Disable = 0,                                  ///< When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
-    TIM_OSSRState_Enable  = TIM_BDTR_OSSR                       ///< When inactive, OC/OCN outputs are enabled with their inactive level
-                            ///< as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1.
-} TIMOSSR_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Output_Compare_Idle_State
-/// @anchor TIM_Output_Compare_Idle_State
-typedef enum {
-    TIM_OCIdleState_Reset = 0,                                  ///< OCn=0 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4)
-    TIM_OCIdleState_Set   = TIM_CR2_OIS1                        ///< OCn=1 (after a dead-time if OCnN is implemented) when MOE=0.(n= 0 : 4)
-} TIMOIS_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Output_Compare_N_Idle_State
-/// @anchor TIM_Output_Compare_N_Idle_State
-typedef enum {
-    TIM_OCNIdleState_Reset = 0,                                 ///< OCnN=0 after a dead-time when MOE=0.(n= 0 : 4)
-    TIM_OCNIdleState_Set   = TIM_CR2_OIS1N                      ///< OCnN=1 after a dead-time when MOE=0.(n= 0 : 4)
-} TIMOISN_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Input_Capture_Selection
-/// @anchor TIM_Input_Capture_Selection
-typedef enum {
-    TIM_ICSelection_DirectTI   = TIM_CCMR1_CC1S_DIRECTTI,
-    TIM_ICSelection_IndirectTI = TIM_CCMR1_CC1S_INDIRECTTI,
-    TIM_ICSelection_TRC        = TIM_CCMR1_CC1S_TRC             ///< TIM Input is selected to be connected to TRC.
-} TIMICSEL_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Input_Capture_Prescaler
-/// @anchor TIM_Input_Capture_Prescaler
-typedef enum {
-    TIM_ICPSC_DIV1 = 0x0000,                                    ///< no prescaler
-    TIM_ICPSC_DIV2 = 0x0004,                                    ///< capture is done once every 2 events
-    TIM_ICPSC_DIV4 = 0x0008,                                    ///< capture is done once every 4 events
-    TIM_ICPSC_DIV8 = 0x000C                                     ///< capture is done once every 8 events
-} TIMICPSC_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Input_Capture_Polarity
-/// @anchor TIM_Input_Capture_Polarity
-typedef enum {
-    TIM_ICPolarity_Rising  = 0,                                 ///< IC Rising edge
-    TIM_ICPolarity_Falling = TIM_CCER_CC1P,                     ///< IC Falling edge
-    TIM_ICPolarity_BothEdge = TIM_CCER_CC1P | TIM_CCER_CC1NP
-} TIMICP_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_External_Trigger_Polarity
-/// @anchor TIM_External_Trigger_Polarity
-typedef enum {
-    TIM_ExtTRGPolarity_NonInverted = 0,                         ///< Active high or rising edge active
-    TIM_ExtTRGPolarity_Inverted    = TIM_SMCR_ETP               ///< Active low or falling edge active
-} TIMETP_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Prescaler_Reload_Mode
-/// @anchor TIM_Prescaler_Reload_Mode
-typedef enum {
-    TIM_PSCReloadMode_Update    = 0,                            ///< The Prescaler is loaded at the update event
-    TIM_PSCReloadMode_Immediate = TIM_EGR_UG                    ///< The Prescaler is loaded immediately
-} TIMUG_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Encoder_Mode
-/// @anchor TIM_Encoder_Mode
-typedef enum {
-    TIM_EncoderMode_TI1  = TIM_SMCR_SMS_ENCODER1,               ///< Counter counts on TI1FP1 edge depending on TI2FP2 level.
-    TIM_EncoderMode_TI2  = TIM_SMCR_SMS_ENCODER2,               ///< Counter counts on TI2FP2 edge depending on TI1FP1 level.
-    TIM_EncoderMode_TI12 = TIM_SMCR_SMS_ENCODER3                ///< Counter counts on both TI1FP1 and TI2FP2 edges depending
-                           ///< on the level of the other input.
-} TIMSMSENCODER_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Update_Source
-/// @anchor TIM_Update_Source
-typedef enum {
-    TIM_UpdateSource_Global  = 0,                               ///< Source of update is counter overflow/underflow.
-    TIM_UpdateSource_Regular = TIM_CR1_URS                      ///< Source of update is the counter overflow/underflow
-                               ///< or the setting of UG bit, or an update generation
-                               ///< through the slave mode controller.
-} TIMURS_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Output_Compare_Preload_State
-/// @anchor TIM_Output_Compare_Preload_State
-typedef enum {
-    TIM_OCPreload_Disable = 0,                                  ///< TIM output compare preload disable
-    TIM_OCPreload_Enable  = TIM_CCMR1_OC1PEN                     ///< TIM output compare preload enable
-} TIMOCPE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Output_Compare_Fast_State
-/// @anchor TIM_Output_Compare_Fast_State
-typedef enum {
-    TIM_OCFast_Disable = 0,                                     ///< TIM output compare fast disable
-    TIM_OCFast_Enable  = TIM_CCMR1_OC1FEN,                       ///< TIM output compare fast enable
-} TIMOCFE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Output_Compare_Clear_State
-/// @anchor TIM_Output_Compare_Clear_State
-typedef enum {
-    TIM_OCClear_Disable = 0,                                    ///< TIM Output clear disable
-    TIM_OCClear_Enable  = TIM_CCMR1_OC1CEN                       ///< TIM Output clear enable
-} TIMOCCE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Master_Slave_Mode
-/// @anchor TIM_Master_Slave_Mode
-typedef enum {
-    TIM_MasterSlaveMode_Disable = 0,                            ///< No action
-    TIM_MasterSlaveMode_Enable  = TIM_SMCR_MSM                  ///< synchronization between the current timer and its slaves (through TRIG)
-} TIMMSM_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_interrupt_sources
-/// @anchor TIM_Master_Slave_Mode
-typedef enum {
-    TIM_IT_Update  = TIM_DIER_UI,                               ///< TIM update Interrupt source
-    TIM_IT_CC1     = TIM_DIER_CC1I,                             ///< TIM Capture Compare 1 Interrupt source
-    TIM_IT_CC2     = TIM_DIER_CC2I,                             ///< TIM Capture Compare 2 Interrupt source
-    TIM_IT_CC3     = TIM_DIER_CC3I,                             ///< TIM Capture Compare 3 Interrupt source
-    TIM_IT_CC4     = TIM_DIER_CC4I,                             ///< TIM Capture Compare 4 Interrupt source
-    TIM_IT_COM     = TIM_DIER_COMI,                             ///< TIM Commutation Interrupt source
-    TIM_IT_Trigger = TIM_DIER_TI,                               ///< TIM Trigger Interrupt source
-    TIM_IT_Break   = TIM_DIER_BI                                ///< TIM Break Interrupt source
-    , TIM_IT_CC5     = TIM_DIER_CC5I                            ///< TIM Capture Compare 5 Interrupt source
-} TIMIT_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_Flags
-/// @anchor TIM_Flags
-typedef enum {
-    TIM_FLAG_Update  = TIM_SR_UI,                              ///< TIM update Flag
-    TIM_FLAG_CC1     = TIM_SR_CC1I,                            ///< TIM Capture Compare 1 Flag
-    TIM_FLAG_CC2     = TIM_SR_CC2I,                            ///< TIM Capture Compare 2 Flag
-    TIM_FLAG_CC3     = TIM_SR_CC3I,                            ///< TIM Capture Compare 3 Flag
-    TIM_FLAG_CC4     = TIM_SR_CC4I,                            ///< TIM Capture Compare 4 Flag
-    TIM_FLAG_COM     = TIM_SR_COMI,                            ///< TIM Commutation Flag
-    TIM_FLAG_Trigger = TIM_SR_TI,                              ///< TIM Trigger Flag
-    TIM_FLAG_Break   = TIM_SR_BI,                              ///< TIM Break Flag
-    TIM_FLAG_CC1OF   = TIM_SR_CC1O,                            ///< TIM Capture Compare 1 overcapture Flag
-    TIM_FLAG_CC2OF   = TIM_SR_CC2O,                            ///< TIM Capture Compare 2 overcapture Flag
-    TIM_FLAG_CC3OF   = TIM_SR_CC3O,                            ///< TIM Capture Compare 3 overcapture Flag
-    TIM_FLAG_CC4OF   = TIM_SR_CC4O                             ///< TIM Capture Compare 4 overcapture Flag
-    , TIM_FLAG_CC5    = TIM_SR_CC5I                            ///< TIM Capture Compare 5 Flag
-} TIMFLAG_Typedef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_DMA_sources
-/// @anchor TIM_DMA_sources
-typedef enum {
-    TIM_DMA_Update  = TIM_DIER_UD,                              ///< TIM update Interrupt source
-    TIM_DMA_CC1     = TIM_DIER_CC1D,                            ///< TIM Capture Compare 1 DMA source
-    TIM_DMA_CC2     = TIM_DIER_CC2D,                            ///< TIM Capture Compare 2 DMA source
-    TIM_DMA_CC3     = TIM_DIER_CC3D,                            ///< TIM Capture Compare 3 DMA source
-    TIM_DMA_CC4     = TIM_DIER_CC4D,                            ///< TIM Capture Compare 4 DMA source
-    TIM_DMA_COM     = TIM_DIER_COMD,                            ///< TIM Commutation DMA source
-    TIM_DMA_Trigger = TIM_DIER_TD                               ///< TIM Trigger DMA source
-} TIMDMASRC_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_DMA_Base_address
-/// @anchor TIM_DMA_Base_address
-typedef enum {
-    TIM_DMABase_CR1   = 0x0000,
-    TIM_DMABase_CR2   = 0x0001,
-    TIM_DMABase_SMCR  = 0x0002,
-    TIM_DMABase_DIER  = 0x0003,
-    TIM_DMABase_SR    = 0x0004,
-    TIM_DMABase_EGR   = 0x0005,
-    TIM_DMABase_CCMR1 = 0x0006,
-    TIM_DMABase_CCMR2 = 0x0007,
-    TIM_DMABase_CCER  = 0x0008,
-    TIM_DMABase_CNT   = 0x0009,
-    TIM_DMABase_PSC   = 0x000A,
-    TIM_DMABase_ARR   = 0x000B,
-    TIM_DMABase_RCR   = 0x000C,
-    TIM_DMABase_CCR1  = 0x000D,
-    TIM_DMABase_CCR2  = 0x000E,
-    TIM_DMABase_CCR3  = 0x000F,
-    TIM_DMABase_CCR4  = 0x0010,
-    TIM_DMABase_BDTR  = 0x0011,
-    TIM_DMABase_DCR   = 0x0012
-} TIMDMABASE_Typedef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_DMA_Burst_Length
-/// @anchor TIM_DMA_Burst_Length
-typedef enum {
-    TIM_DMABurstLength_1Byte   = 0x0000,
-    TIM_DMABurstLength_2Bytes  = 0x0100,
-    TIM_DMABurstLength_3Bytes  = 0x0200,
-    TIM_DMABurstLength_4Bytes  = 0x0300,
-    TIM_DMABurstLength_5Bytes  = 0x0400,
-    TIM_DMABurstLength_6Bytes  = 0x0500,
-    TIM_DMABurstLength_7Bytes  = 0x0600,
-    TIM_DMABurstLength_8Bytes  = 0x0700,
-    TIM_DMABurstLength_9Bytes  = 0x0800,
-    TIM_DMABurstLength_10Bytes = 0x0900,
-    TIM_DMABurstLength_11Bytes = 0x0A00,
-    TIM_DMABurstLength_12Bytes = 0x0B00,
-    TIM_DMABurstLength_13Bytes = 0x0C00,
-    TIM_DMABurstLength_14Bytes = 0x0D00,
-    TIM_DMABurstLength_15Bytes = 0x0E00,
-    TIM_DMABurstLength_16Bytes = 0x0F00,
-    TIM_DMABurstLength_17Bytes = 0x1000,
-    TIM_DMABurstLength_18Bytes = 0x1100
-} TIMDMABURSTLENGTH_Typedef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  TIM Time Base Init structure definition
-/// @note   This structure is used with all tim.
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    u16 TIM_Prescaler;                                          ///< Specifies the prescaler value used to divide the TIM clock.
-    ///< This parameter can be a number between 0x0000 and 0xFFFF
-    TIMCOUNTMODE_Typedef TIM_CounterMode;                       ///< Specifies the counter mode.
-    ///< This parameter can be a value of @ref TIM_Counter_Mode
-    u32 TIM_Period;                                             ///< Specifies the period value to be loaded into the active
-    ///< Auto-Reload Register at the next update event.
-    ///< This parameter must be a number between 0x0000 and 0xFFFF/0xFFFFFFFF.
-    ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5.
-    TIMCKD_TypeDef TIM_ClockDivision;                           ///< Specifies the clock division.
-    ///< This parameter can be a value of @ref TIM_Clock_Division_CKD
-    u8 TIM_RepetitionCounter;                                   ///< Specifies the repetition counter value. Each time the RCR downcounter
-    ///< reaches zero, an update event is generated and counting restarts
-    ///< from the RCR value (N).
-    ///< This means in PWM mode that (N+1) corresponds to:
-    ///<    - the number of PWM periods in edge-aligned mode
-    ///<    - the number of half PWM period in center-aligned mode
-    ///< This parameter must be a number between 0x00 and 0xFF.
-    ///< @note This parameter is valid only for TIM1 and TIM8.
-} TIM_TimeBaseInitTypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  TIM Output Compare Init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    TIMOCMODE_Typedef TIM_OCMode;                               ///< Specifies the TIM mode.
-    ///< This parameter can be a value of TIM_Output_Compare_and_PWM_modes
-    TIMOUTPUTSTATE_Typedef TIM_OutputState;                     ///< Specifies the TIM Output Compare state.
-    ///< This parameter can be a value of TIM_Output_Compare_state
-    TIMOUTPUTNSTATE_Typedef TIM_OutputNState;                   ///< Specifies the TIM complementary Output Compare state.
-    ///< This parameter can be a value of TIM_Output_Compare_N_state
-    ///< @note This parameter is valid only for TIM1 and TIM8.
-    u32 TIM_Pulse;                                              ///< Specifies the pulse value to be loaded into the Capture Compare Register.
-    ///< This parameter can be a number between 0x0000 and 0xFFFF/0xFFFFFFFF
-    ///< @note 0xFFFFFFFF is valid only for MM32 32bit Timers: eg.TIM2 or TIM5.
-    TIMCCxP_Typedef TIM_OCPolarity;                             ///< Specifies the output polarity.
-    ///< This parameter can be a value of @ref TIM_Output_Compare_Polarity
-    TIMCCxNP_Typedef TIM_OCNPolarity;                           ///< Specifies the complementary output polarity.
-    ///< This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-    ///< @note This parameter is valid only for TIM1 and TIM8.
-    TIMOIS_Typedef TIM_OCIdleState;                             ///< Specifies the TIM Output Compare pin state during Idle state.
-    ///< This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-    ///< @note This parameter is valid only for TIM1 and TIM8.
-    TIMOISN_Typedef TIM_OCNIdleState;                           ///< Specifies the TIM Output Compare pin state during Idle state.
-    ///< This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-    ///< @note This parameter is valid only for TIM1 and TIM8.
-} TIM_OCInitTypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  TIM Input Capture Init structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    TIMCHx_Typedef TIM_Channel;                                 ///< Specifies the TIM channel.
-    ///< This parameter can be a value of @ref TIM_Channel
-    TIMICP_Typedef TIM_ICPolarity;                              ///< Specifies the active edge of the input signal.
-    ///< This parameter can be a value of @ref TIM_Input_Capture_Polarity
-    TIMICSEL_Typedef TIM_ICSelection;                           ///< Specifies the input.
-    ///< This parameter can be a value of @ref TIM_Input_Capture_Selection
-    TIMICPSC_Typedef TIM_ICPrescaler;                           ///< Specifies the Input Capture Prescaler.
-    ///< This parameter can be a value of @ref TIM_Input_Capture_Prescaler
-    u16 TIM_ICFilter;                                           ///< Specifies the input capture filter.
-    ///< This parameter can be a number between 0x0 and 0xF
-} TIM_ICInitTypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  BDTR structure definition
-/// @note   This structure is used only with TIM1 and TIM8.
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    TIMOSSR_Typedef TIM_OSSRState;                              ///< Specifies the Off-State selection used in Run mode.
-    ///< This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state
-    TIMOSSI_Typedef TIM_OSSIState;                              ///< Specifies the Off-State used in Idle state.
-    ///< This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state
-    TIMLOCKLEVEL_Typedef TIM_LOCKLevel;                         ///< Specifies the LOCK level parameters.
-    ///< This parameter can be a value of @ref Lock_level
-    u16 TIM_DeadTime;                                           ///< Specifies the delay time between the switching-off and
-    ///< the switching-on of the outputs.
-    ///< This parameter can be a number between 0x00 and 0xFF
-    TIMBKE_Typedef TIM_Break;                                   ///< Specifies whether the TIM Break input is enabled or not.
-    ///< This parameter can be a value of @ref Break_Input_enable_disable
-    TIMBKP_Typedef TIM_BreakPolarity;                           ///< Specifies the TIM Break Input pin polarity.
-    ///< This parameter can be a value of @ref Break_Polarity
-    TIMAOE_Typedef TIM_AutomaticOutput;                         ///< Specifies whether the TIM Automatic Output feature is enabled or not.
-    ///< This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset
-} TIM_BDTRInitTypeDef;
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup TIM_Exported_Variables
-/// @{
-#ifdef _HAL_TIM_C_
-#define GLOBAL
-
-static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
-static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
-static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
-static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter);
-
-
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup TIM_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-//=================  TimeBase management  ======================================
-void TIM_DeInit(TIM_TypeDef* tim);
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct);
-void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct);
-void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reload_mode);
-void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode);
-void TIM_SetCounter(TIM_TypeDef* tim, u32 counter);
-void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload);
-void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state);
-void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source);
-void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state);
-void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode);
-void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div);
-void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state);
-
-u32 TIM_GetCounter(TIM_TypeDef* tim);
-u16 TIM_GetPrescaler(TIM_TypeDef* tim);
-
-//=================  Advanced-control timers specific features  ================
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct);
-void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct);
-void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state);
-
-//=================  Output Compare management  ================================
-void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct);
-void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
-void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
-void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
-void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
-void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode);
-void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare);
-void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare);
-void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare);
-void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare);
-void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
-void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
-void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
-void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action);
-void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state);
-void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
-void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
-void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
-void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
-void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
-void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
-void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
-void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
-void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
-void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
-void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
-void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
-void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en);
-void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en);
-void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state);
-
-//=================  Input Capture management  =================================
-void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct);
-void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct);
-void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct);
-void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
-void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
-void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
-void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc);
-
-u32 TIM_GetCapture1(TIM_TypeDef* tim);
-u32 TIM_GetCapture2(TIM_TypeDef* tim);
-u32 TIM_GetCapture3(TIM_TypeDef* tim);
-u32 TIM_GetCapture4(TIM_TypeDef* tim);
-
-//=================  Interrupts, DMA and flags management  =====================
-void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);//TIMIT_TypeDef
-void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source);
-void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag);
-void TIM_ClearITPendingBit(TIM_TypeDef* tim, u32 it);//TIMIT_TypeDef
-void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length);
-void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state);
-void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag);
-ITStatus   TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it);
-
-//=================  Clocks management  ========================================
-void TIM_InternalClockConfig(TIM_TypeDef* tim);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
-
-//=================  Synchronization management  ===============================
-void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source);
-void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source);
-void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode);
-void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter);
-
-//=================  Specific interface management  ============================
-void TIM_EncoderInterfaceConfig(TIM_TypeDef*          tim,
-                                TIMSMSENCODER_Typedef encoder_mode,
-                                TIMICP_Typedef        ic1_polarity,
-                                TIMICP_Typedef        iC2_polarity);
-void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state);
-
-//=================  extend Channel IC management  ==============================
-void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
-void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
-void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
-void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol);
-
-#define exTIM_SetIC1Plority                     TIM_SetIC1Plority
-#define exTIM_SetIC2Plority                     TIM_SetIC2Plority
-#define exTIM_SetIC3Plority                     TIM_SetIC3Plority
-#define exTIM_SetIC4Plority                     TIM_SetIC4Plority
-//=================  extend Channel 5 management  ==============================
-
-void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare);
-void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct);
-void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload);
-void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity);
-void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast);
-void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear);
-u32 TIM_GetCapture5(TIM_TypeDef* tim);
-
-#define exTIM_SetCompare5                       TIM_SetCompare5
-#define exTIM_OC5Init                           TIM_OC5Init
-#define exTIM_OC5PreloadConfig                  TIM_OC5PreloadConfig
-#define exTIM_OC5PolarityConfig                 TIM_OC5PolarityConfig
-#define exTIM_OC5FastConfig                     TIM_OC5FastConfig
-#define exTIM_ClearOC5Ref                       TIM_ClearOC5Ref
-#define exTIM_GetCapture5                       TIM_GetCapture5
-
-//============= extend Advanced-control timers specific features  ==============
-void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state);
-#define exTIM_DirectOutput TIM_DirectOutput
-void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state);
-void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift);
-void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift);
-void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift);
-void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift);
-void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift);
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_TIM_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h
deleted file mode 100644
index a46f234e0..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uart.h
+++ /dev/null
@@ -1,211 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_uart.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_UART_H
-#define __HAL_UART_H
-
-// Files includes
-#include "reg_uart.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-/////////////////////////////////////1///////////////////////////////////////////
-/// @defgroup UART_HAL
-/// @brief UART HAL modules
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup UART_Exported_Types
-/// @{
-///
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART Word Length Enumerate definition
-/// @anchor UART_Word_Length
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    UART_WordLength_5b = 0U,
-    UART_WordLength_6b = 1U << UART_CCR_CHAR_Pos,
-    UART_WordLength_7b = 2U << UART_CCR_CHAR_Pos,
-    UART_WordLength_8b = 3U << UART_CCR_CHAR_Pos
-} UART_WordLength_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART Stop Bits Enumerate definition
-/// @anchor UART_Stop_Bits
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    UART_StopBits_1 = 0U,
-    UART_StopBits_2 = UART_CCR_SPB,
-
-    UART_StopBits_0_5 = UART_CCR_SPB1,
-    UART_StopBits_1_5 = UART_CCR_SPB1 | UART_CCR_SPB0,
-} UART_Stop_Bits_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART Parity Enumerate definition
-/// @anchor UART_Parity
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    UART_Parity_No   = 0U,
-    UART_Parity_Even = UART_CCR_PEN | UART_CCR_PSEL,
-    UART_Parity_Odd  = UART_CCR_PEN
-} UART_Parity_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART Hardware Flow Control Enumerate definition
-/// @anchor UART_Hardware_Flow_Control
-////////////////////////////////////////////////////////////////////////////////
-typedef enum {
-    UART_HWFlowControl_None    = 0U,
-
-    //    UART_HWFlowControl_RTS     = UART_GCR_AUTOFLOW,
-    //    UART_HWFlowControl_CTS     = UART_GCR_AUTOFLOW,
-
-    UART_HWFlowControl_RTS_CTS = UART_GCR_AUTOFLOW
-} UART_HW_FLOWCONTROL_TypeDef;
-
-typedef enum {
-    UART_WakeUp_IdleLine    = 0U,  //
-    UART_WakeUp_AddressMark = UART_CCR_WAKE
-} UART_WakeUp_TypeDef;
-
-typedef enum {
-    UART_9bit_Polarity_Low  = 0U,  //
-    UART_9bit_Polarity_High = UART_CCR_B8POL
-} UART_9bit_Polarity_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART Auto BaudRate definition
-////////////////////////////////////////////////////////////////////////////////
-typedef enum  {
-    Data_F8 = 0,
-    Data_FE,
-    ABRMODE_FALLING_TO_RISINGEDGE1BIT,
-    ABRMODE_FALLING_TO_RISINGEDGE2BIT,
-    ABRMODE_FALLING_TO_RISINGEDGE4BIT,
-    ABRMODE_FALLING_TO_RISINGEDGE8BIT,
-    ABRMODE_FALLING_TO_FALLINGEDGE2BIT,
-    ABRMODE_FALLING_TO_FALLINGEDGE4BIT,
-    ABRMODE_FALLING_TO_FALLINGEDGE8BIT,
-    ABRMODE_STARTBIT,
-    ABRMODE_VALUE0X55,
-    ABRMODE_VALUE0x7F,
-    ABRMODE_VALUE0X80,
-    ABRMODE_VALUE0XF7,
-    ABRMODE_VALUE0XF8 = Data_F8,
-    ABRMODE_VALUE0XFE = Data_FE,
-    ABRMODE_VALUE0XFF,
-} UART_AutoBaud_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART Init Structure definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    union {
-        u32                         BaudRate;                           ///< This member configures the UART communication baud rate.
-        u32                         UART_BaudRate;
-    };
-    union {
-        UART_WordLength_TypeDef     WordLength;                         ///< Specifies the number of data bits transmitted or received in a frame.
-        u16                         UART_WordLength;
-    };
-    union {
-        UART_Stop_Bits_TypeDef      StopBits;                           ///< Specifies the number of stop bits transmitted.
-        u16                         UART_StopBits;
-    };
-    union {
-        UART_Parity_TypeDef         Parity;                             ///< Specifies the parity mode.
-        u16                         UART_Parity;
-    };
-    union {
-        u16                         Mode;                               ///< Specifies wether the Receive or Transmit mode is
-        u16                         UART_Mode;
-    };
-    union {
-        UART_HW_FLOWCONTROL_TypeDef HWFlowControl;                      ///< Specifies wether the hardware flow control mode is enabled or disabled.
-        u16                         UART_HardwareFlowControl;
-    };
-} UART_InitTypeDef;
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup UART_Exported_Constants
-/// @{
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup UART_Exported_Variables
-/// @{
-#ifdef _HAL_UART_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup UART_Exported_Functions
-/// @{
-void UART_DeInit(UART_TypeDef* uart);
-void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct);
-void UART_StructInit(UART_InitTypeDef* init_struct);
-void UART_Cmd(UART_TypeDef* uart, FunctionalState state);
-void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state);
-void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state);
-void UART_SendData(UART_TypeDef* uart, u16 Data);
-void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it);
-
-u16        UART_ReceiveData(UART_TypeDef* uart);
-FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag);
-
-ITStatus   UART_GetITStatus(UART_TypeDef* uart, u16 it);
-
-void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode);
-void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state);
-void UART_SetRXAddress(UART_TypeDef* uart, u8 address);
-void UART_SetRXMASK(UART_TypeDef* uart, u8 address);
-void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state);
-void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state);
-void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity);
-void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state);
-void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state);
-void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time);
-void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state);
-void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state);
-void UART_SendBreak(UART_TypeDef* uart);
-void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state);
-void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state);
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_UART_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h
deleted file mode 100644
index 2dba789d2..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_uid.h
+++ /dev/null
@@ -1,71 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_uid.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UID
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_UID_H
-#define __HAL_UID_H
-
-// Files includes
-#include "types.h"
-#include "reg_common.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup UID_HAL
-/// @brief UID HAL modules
-/// @{
-
-
-/////////////////////////////////////1///////////////////////////////////////////
-/// @defgroup UID_Exported_Variables
-/// @{
-#ifdef _HAL_UID_C_
-#define GLOBAL
-
-#else
-#define GLOBAL extern
-
-
-#endif
-GLOBAL u8 device_id_data[12];
-
-#undef GLOBAL
-
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup UID_Exported_Functions
-/// @{
-void GetChipUID(void);
-
-/// @}
-
-
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_UID_H 
-////////////////////////////////////////////////////////////////////////////////
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h
deleted file mode 100644
index 773af5631..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_ver.h
+++ /dev/null
@@ -1,89 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_ver.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE UART
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_VER_H
-#define __HAL_VER_H
-
-// Files includes
-#include "reg_common.h"
-#include "reg_dbg.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-/////////////////////////////////////1///////////////////////////////////////////
-/// @defgroup UART_HAL
-/// @brief UART HAL modules
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup UART_Exported_Types
-/// @{
-///
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART Word Length Enumerate definition
-/// @anchor UART_Word_Length
-////////////////////////////////////////////////////////////////////////////////
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup UART_Exported_Constants
-/// @{
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup UART_Exported_Variables
-/// @{
-#ifdef _HAL_VER_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup UART_Exported_Functions
-/// @{
-
-u32            Get_MM32LibVersion(void);
-u32            Get_ChipsetREVID(void);
-u32            Get_ChipsetDEVID(void);
-u32            Get_ChipsetUIDw0(void);
-u32            Get_ChipsetUIDw1(void);
-u32            Get_ChipsetUIDw2(void);
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_VER_H 
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h
deleted file mode 100644
index 287ddd5c8..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Inc/hal_wwdg.h
+++ /dev/null
@@ -1,90 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_wwdg.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE WWDG
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT O
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDER
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __HAL_WWDG_H
-#define __HAL_WWDG_H
-
-// Files includes
-#include "types.h"
-#include "reg_wwdg.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup WWDG_HAL
-/// @brief WWDG HAL modules
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup WWDG_Exported_Types
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  WWDG_Prescaler
-/// @anchor WWDG_Prescaler
-
-typedef enum {
-    WWDG_Prescaler_1 = WWDG_CFGR_WDGTB_1,
-    WWDG_Prescaler_2 = WWDG_CFGR_WDGTB_2,
-    WWDG_Prescaler_4 = WWDG_CFGR_WDGTB_4,
-    WWDG_Prescaler_8 = WWDG_CFGR_WDGTB_8
-} WWDG_Prescaler_Typedef;
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup WWDG_Exported_Variables
-/// @{
-
-#ifdef _HAL_WWDG_C_
-
-#define GLOBAL
-#else
-#define GLOBAL extern
-#endif
-
-#undef GLOBAL
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup WWDG_Exported_Functions
-/// @{
-
-void       WWDG_DeInit(void);
-void       WWDG_SetPrescaler(u32 prescaler);
-void       WWDG_SetWindowValue(u8 window_value);
-void       WWDG_EnableIT(void);
-void       WWDG_SetCounter(u8 count);
-u32        WWDG_GetCounter(void);
-void       WWDG_Enable(u8 count);
-FlagStatus WWDG_GetFlagStatus(void);
-void       WWDG_ClearFlag(void);
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __HAL_WWDG_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c
deleted file mode 100644
index 503e91a67..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_adc.c
+++ /dev/null
@@ -1,563 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_adc.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE ADC FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_ADC_C_
-
-// Files includes
-#include "hal_adc.h"
-#include "hal_rcc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup ADC_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup ADC_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the adc peripheral registers to their default
-///         reset values.
-/// @param  adc: select the ADC peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_DeInit(ADC_TypeDef* adc)
-{
-
-    switch (*(vu32*)&adc) {
-
-        case ADC1_BASE:
-            exRCC_APB2PeriphReset(RCC_APB2ENR_ADC1);
-            break;
-        case ADC2_BASE:
-            exRCC_APB2PeriphReset(RCC_APB2ENR_ADC2);
-            break;
-        case ADC3_BASE:
-            exRCC_APB2PeriphReset(RCC_APB2ENR_ADC3);
-            break;
-        default:
-            break;
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the adc peripheral according to the specified parameters
-///         in the init_struct, Please use this function if you want to be
-///         compatible with older versions of the library.
-/// @param  adc: select the ADC peripheral.
-/// @param  init_struct: pointer to an ADC_InitTypeDef structure that contains
-///         the configuration information for the specified ADC peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_Init(ADC_TypeDef* adc, ADC_InitTypeDef* init_struct)
-{
-    adc->ADCFG &= ~(ADC_CFGR_PRE | ADC_CFGR_RSLTCTL);
-    adc->ADCFG |= (u32)(init_struct->ADC_PRESCARE) | init_struct->ADC_Resolution;
-
-    adc->ADCR &= ~(ADC_CR_ALIGN | ADC_CR_MODE | ADC_CR_TRGSEL);
-    adc->ADCR |= ((u32)init_struct->ADC_DataAlign) | init_struct->ADC_ExternalTrigConv | ((u32)init_struct->ADC_Mode);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param  init_struct : pointer to an ADC_InitTypeDef structure which will be
-///         initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_StructInit(ADC_InitTypeDef* init_struct)
-{
-    init_struct->ADC_Resolution         = ADC_Resolution_12b;
-    init_struct->ADC_PRESCARE           = ADC_PCLK2_PRESCARE_2;
-    init_struct->ADC_Mode               = ADC_CR_IMM;                           //ADC_Mode_Single;
-    init_struct->ADC_ContinuousConvMode = DISABLE;                              // useless
-    init_struct->ADC_ExternalTrigConv   = ADC1_ExternalTrigConv_T1_CC1;
-    init_struct->ADC_DataAlign          = ADC_DataAlign_Right;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified ADC peripheral.
-/// @param  adc:select the ADC peripheral.
-/// @param  state: new state of the adc peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_Cmd(ADC_TypeDef* adc, FunctionalState state)
-{
-    (state) ? (adc->ADCFG |= ADC_CFGR_ADEN) : (adc->ADCFG &= ~ADC_CFGR_ADEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified ADC DMA request.
-/// @param  adc: select the ADC peripheral.
-/// @param  state: New state of the selected ADC DMA transfer.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_DMACmd(ADC_TypeDef* adc, FunctionalState state)
-{
-    (state) ? (adc->ADCR |= ADC_CR_DMAEN) : (adc->ADCR &= ~ADC_CR_DMAEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified ADC interrupts.
-/// @param  adc: select the ADC peripheral.
-/// @param  adc_interrupt: specifies the ADC interrupt sources to be enabled or disabled.
-/// @param  state: New state of the specified ADC interrupts.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_ITConfig(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt, FunctionalState state)
-{
-    if (adc_interrupt == ADC_IT_EOC)
-        (state) ? (adc->ADCR |= ADC_CR_ADIE) : (adc->ADCR &= ~ADC_CR_ADIE);
-    else
-        (state) ? (adc->ADCR |= ADC_CR_ADWIE) : (adc->ADCR &= ~ADC_CR_ADWIE);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the selected ADC software start conversion .
-/// @param  adc:  select the ADC peripheral.
-/// @param  state: New state of the selected ADC software start conversion.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_SoftwareStartConvCmd(ADC_TypeDef* adc, FunctionalState state)
-{
-    (state) ? (adc->ADCR |= ADC_CR_ADST) : (adc->ADCR &= ~ADC_CR_ADST);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Gets the selected ADC Software start conversion Status.
-/// @param  adc: select the ADC peripheral.
-/// @retval  The new state of ADC software start conversion (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* adc)
-{
-    return (((adc->ADCR & ADC_CR_ADST) != (u32)RESET) ? SET : RESET);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enable the selected ADC channel and configure its sample time. Please
-///         use this function if you want to be compatible with older versions
-///         of the library.
-/// @param  adc:  select the ADC peripheral.
-/// @param  channel: the ADC channel to configure.
-/// @param  sample_time: the ADC Channel n Sample time to configure.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_RegularChannelConfig(ADC_TypeDef* adc, u32 channel, u8 rank, u32 sample_time)    //ADCSAM_TypeDef
-{
-
-    u32 tempchan;
-    sample_time = sample_time & 0xF;
-    tempchan = channel;
-    if(tempchan > 8) {
-        tempchan = tempchan & 0xF;
-        tempchan = tempchan - 8;
-        adc->SMPR2 &= ~(0xF << tempchan);
-        adc->SMPR2 |= (sample_time << tempchan);
-    }
-    else {
-        adc->SMPR1 &= ~(0xF << tempchan);
-        adc->SMPR1 |= (sample_time << tempchan);
-    }
-    adc->ADCHS &= ~(1 << channel);
-    adc->ADCHS |=  (1 << channel);
-
-    if (channel & ADC_CHSR_CHT)
-        ADC_TempSensorVrefintCmd(ENABLE);
-    else if (channel & ADC_CHSR_CHV)
-        ADC_TempSensorVrefintCmd(ENABLE);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the adc conversion through external trigger.
-/// @param  adc: select the ADC peripheral.
-/// @param  state: New state of the selected ADC external trigger.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_ExternalTrigConvCmd(ADC_TypeDef* adc, FunctionalState state)
-{
-    (state) ? (adc->ADCR |= ADC_CR_TRGEN) : (adc->ADCR &= ~ADC_CR_TRGEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the adc external trigger for injected channels conversion.
-/// @param  adc:  select the ADC peripheral.
-/// @param  adc_external_trig_source: Configuring the external trigger source
-///         for the ADC.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_ExternalTrigConvConfig(ADC_TypeDef* adc, EXTERTRIG_TypeDef adc_external_trig_source)
-{
-    adc->ADCR &= ~ADC_CR_TRGSEL;
-    adc->ADCR |=  adc_external_trig_source;
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the last adc conversion result data for regular channel.
-/// @param  adc: select the ADC peripheral.
-/// @retval The data conversion value.
-////////////////////////////////////////////////////////////////////////////////
-u16 ADC_GetConversionValue(ADC_TypeDef* adc)
-{
-    return (u16)adc->ADDATA;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the last ADC conversion result data in dual mode.
-/// @param  None
-/// @retval The Data conversion value.
-////////////////////////////////////////////////////////////////////////////////
-u32 ADC_GetDualModeConversionValue()
-{
-    return (*(vu32*)ADC1_BASE);
-}
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the analog watchdog.
-/// @param  adc:  to select the ADC peripheral.
-/// @param  state: New state of the selected ADC analog watchdog.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* adc, FunctionalState state)
-{
-    (state) ? (adc->ADCFG |= ADC_CFGR_ADWEN) : (adc->ADCFG &= ~ADC_CFGR_ADWEN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the high and low thresholds of the analog watchdog.
-/// @param  adc:  select the ADC peripheral.
-/// @param  high_threshold: the ADC analog watchdog High threshold value.
-///         This parameter must be a 12bit value.
-/// @param  low_threshold: the ADC analog watchdog Low threshold value.
-///         This parameter must be a 12bit value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* adc, u16 high_threshold, u16 low_threshold)
-{
-    u32 tempThreshold;
-    tempThreshold = high_threshold;
-    adc->ADCMPR    = (tempThreshold << 16) | low_threshold;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the analog watchdog guarded single channel
-/// @param  adc: select the ADC peripheral.
-/// @param  channel: the ADC channel to configure for the analog watchdog.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel)
-{
-    adc->ADCR &= ~ADC_CR_CMPCH;
-    adc->ADCR |= (channel << ADC_CR_CMPCH_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the temperature sensor and Vrefint channel.
-/// @param  state: New state of the temperature sensor.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_TempSensorVrefintCmd(FunctionalState state)
-{
-    (state) ? (ADC1->ADCFG |=  (ADC_CFGR_TEN | ADC_CFGR_VEN))
-    : (ADC1->ADCFG &= ~(ADC_CFGR_TEN | ADC_CFGR_VEN));
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the temperature sensor .
-/// @param  state: New state of the temperature sensor.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_TempSensorCmd(FunctionalState state)
-{
-    ADC_TempSensorVrefintCmd(state);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the Vrefint channel.
-/// @param  state: New state of the Vrefint channel.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_VrefintCmd(FunctionalState state)
-{
-    ADC_TempSensorVrefintCmd(state);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the temperature sensor and Vrefint channel.
-/// @param  chs: temperature sensor bit & Vrefint bit.
-/// @param  state: New state of the temperature sensor.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exADC_TempSensorVrefintCmd(u32 chs, FunctionalState state)
-{
-    if (chs & ADC_CHSR_CHT) {
-        (state) ? (ADC1->ADCFG |=  ADC_CFGR_TEN)
-        : (ADC1->ADCFG &= ~ADC_CFGR_TEN);
-    }
-    else if (chs & ADC_CHSR_CHV) {
-        (state) ? (ADC1->ADCFG |=  ADC_CFGR_VEN)
-        : (ADC1->ADCFG &= ~ADC_CFGR_VEN);
-    }
-
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified ADC flag is set or not.
-/// @param  adc: select the ADC peripheral.
-/// @param  adc_flag: specifies the flag to check.
-/// @retval The New state of adc_flag (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag)
-{
-    return (adc_flag == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the adc's pending flags.
-/// @param  adc: select the ADC peripheral.
-/// @param  adc_flag: specifies the flag to clear.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_ClearFlag(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_flag)
-{
-    (adc_flag == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified adc's interrupt has occurred or not.
-/// @param  adc: select the ADC peripheral.
-/// @param  adc_interrupt: specifies the ADC interrupt source to check.
-/// @retval The new state of adc_interrupt (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus ADC_GetITStatus(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt)
-{
-    return (adc_interrupt == ADC_IT_EOC) ? ((adc->ADSTA & ADC_SR_ADIF) ? SET : RESET) : ((adc->ADSTA & ADC_SR_ADWIF) ? SET : RESET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the adc's interrupt pending bits.
-/// @param  adc: select the ADC peripheral.
-/// @param  adc_interrupt: specifies the ADC interrupt pending bit to clear.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_ClearITPendingBit(ADC_TypeDef* adc, ADCFLAG_TypeDef adc_interrupt)
-{
-    (adc_interrupt == ADC_IT_EOC) ? (adc->ADSTA |= ADC_SR_ADIF) : (adc->ADSTA |= ADC_SR_ADWIF);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the adc any channels conversion rank and channel.
-/// @param  adc: select the ADC peripheral.
-/// @param  rank: rank can be 0x0~0xf for the convert sequence.
-/// @param  adc_channel: Configuring the target channel to be converted.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_ANY_CH_Config(ADC_TypeDef* adc, u8 rank, ADCCHANNEL_TypeDef adc_channel)
-{
-    rank = rank & 0xF;
-    if(rank < 8) {
-        adc->CHANY0 &= ~(0x0F << (4 * rank));
-        adc->CHANY0 |= (adc_channel << (4 * rank));
-    }
-    else {
-        adc->CHANY1 &= ~(0x0F << (4 * (rank - 8)));
-        adc->CHANY1 |= (adc_channel << (4 * (rank - 8)));
-    }
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the adc any channels conversion Max rank number
-/// @param  adc: select the ADC peripheral.
-/// @param  num: Configuring the max rank number for the ADC.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_ANY_NUM_Config(ADC_TypeDef* adc, u8 num)
-{
-    if(num > 15) num = 15;                                                      //15 ? 16 need to be confirmed
-    adc->ANYCFG = num;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the ANY channel converter.
-/// @param  state: enable or disable the ANY channel converter mode.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_ANY_Cmd(ADC_TypeDef* adc, FunctionalState state)
-{
-    (state) ? (adc->ANYCR |= ADC1_CHANY_CR_MDEN) : (adc->ANYCR &= ~ADC1_CHANY_CR_MDEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the selected ADC automatic injected group
-///         conversion after regular one.
-/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
-/// @param  state: new state of the selected ADC auto injected conversion
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None
-////////////////////////////////////////////////////////////////////////////////
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
-{
-    (state) ? (adc->ANYCR |= ADC_ANY_CR_JAUTO) : (adc->ANYCR &= ~ADC_ANY_CR_JAUTO);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the adc external trigger for injected channels conversion.
-/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
-/// @param  ADC_ExtInjTrigSource: specifies the ADC trigger to start injected conversion.
-
-/// @retval None
-////////////////////////////////////////////////////////////////////////////////
-void ADC_ExternalTrigInjectedConvertConfig(ADC_TypeDef* adc, EXTER_INJ_TRIG_TypeDef ADC_ExtInjTrigSource)
-{
-    u32 tmpreg = 0;
-    // Get the old register value
-    tmpreg = adc->ANYCR;
-    // Clear the old external event selection for injected group
-    tmpreg &= ADC_ANY_CR_JTRGSEL;
-    // Set the external event selection for injected group
-    tmpreg |= ADC_ExtInjTrigSource;
-    // Store the new register value
-    adc->ANYCR = tmpreg;
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the adc injected channels conversion through
-///         external trigger
-/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
-/// @param  state: new state of the selected ADC external trigger start of
-///         injected conversion.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None
-////////////////////////////////////////////////////////////////////////////////
-void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
-{
-    (state) ? (adc->ANYCR |= ADC_ANY_CR_JTRGEN) : (adc->ANYCR &= ~ADC_ANY_CR_JTRGEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the selected ADC start of the injected
-///         channels conversion.
-/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
-/// @param  state: new state of the selected ADC software start injected conversion.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None
-////////////////////////////////////////////////////////////////////////////////
-void ADC_InjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
-{
-    (state) ? (adc->ANYCR |= ADC_ANY_CR_JCEN) : (adc->ANYCR &= ~ADC_ANY_CR_JCEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the selected ADC start of the injected
-///         channels conversion.
-/// @param  adc: where x can be 1, 2 or 3 to select the ADC peripheral.
-/// @param  NewState: new state of the selected ADC software start injected conversion.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None
-////////////////////////////////////////////////////////////////////////////////
-void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* adc, FunctionalState state)
-{
-    (state) ? (adc->ANYCR |= ADC_ANY_CR_JADST) : (adc->ANYCR &= ~ADC_ANY_CR_JADST);
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enable the selected ADC channel and configure its sample time. Please
-///         use this function if you want to be compatible with older versions
-///         of the library.
-/// @param  adc:  select the ADC peripheral.
-/// @param  event: the ADC external event to configure.
-/// @param  sample_time: the ADC Channel n Sample time to configure.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_InjectedSequencerConfig(ADC_TypeDef* adc, u32 event, u32 sample_time)
-{
-    adc->ANYCR &= ~(ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | ADC_ANY_CR_JTRGSEL_EXTI12 \
-                    | ADC_ANY_CR_JTRGSHIFT_512 | ADC_ANY_CR_JTRGEN);
-    adc->ANYCR |= (ADC_ANY_CR_JCEN | ADC_ANY_CR_CHANY_MDEN | sample_time | event | ADC_ANY_CR_JTRGEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Injection channel length configuration.
-/// @param  adc:  select the ADC peripheral.
-/// @param  Length: Injection channel length.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_LEN_TypeDef Length)
-{
-    adc->JSQR &= ~(0x03 << ADC_JSQR_JL_Pos);
-    adc->JSQR |= Length << ADC_JSQR_JL_Pos;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Injection channel  configuration.
-/// @param  adc  :   select the ADC peripheral.
-/// @param  off_addr :   Injection channel offset address.
-/// @param  channel: The sampling channel.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_InjectedSequencerChannelConfig(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, ADCCHANNEL_TypeDef channel)
-{
-    adc->JSQR &= ~(0x1F << (off_addr >> 2) * 5);
-    adc->JSQR |= (channel <<  (off_addr >> 2) * 5);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Injection channel  converted value.
-/// @param  adc  :   select the ADC peripheral.
-/// @param  off_addr :   Injection channel offset address.
-/// @retval value.
-////////////////////////////////////////////////////////////////////////////////
-u16 ADC_GetInjectedConversionValue(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr)
-{
-    u32 value;
-    value = (*(vu32*)(*(vu32*)&adc + 0xB0 + off_addr)) - (*(vu32*)(*(vu32*)&adc + 0x7C + off_addr));
-
-    return (u16)value;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Injection current converted value.
-/// @param  adc  :   select the ADC peripheral.
-/// @retval value. Returns the last adc conversion result data for injected channel.
-////////////////////////////////////////////////////////////////////////////////
-u16 ADC_GetInjectedCurrentConvertedValue(ADC_TypeDef* adc)
-{
-    return (u16)adc->JDATA;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Injection channel compensation configuration.
-/// @param  adc         : select the ADC peripheral.
-/// @param  off_addr    : Injection channel.
-/// @param  value       : compensation value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void ADC_SetInjectedOffset(ADC_TypeDef* adc, ADC_INJ_SEQ_Channel_TypeDef off_addr, u16 value)
-{
-    *(vu32*)(*(vu32*)&adc + 0x7C + off_addr) = value;
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Get channel convertion result.
-/// @param  adc  :   select the ADC peripheral.
-/// @param  channel :   Converted channel.
-/// @retval The Data conversion value.
-////////////////////////////////////////////////////////////////////////////////
-u16 ADC_GetChannelConvertedValue(ADC_TypeDef* adc, ADCCHANNEL_TypeDef channel)
-{
-    return (u16)(*(vu32*) ((u32)adc + 0x18 + ((u32)channel << 2)));
-}
-
-/// @}
-
-/// @}
-
-/// @}
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c
deleted file mode 100644
index 323971dd3..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_bkp.c
+++ /dev/null
@@ -1,231 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_bkp.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE BKP FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_BKP_C_
-
-// Files includes
-#include "types.h"
-#include "hal_pwr.h"
-#include "hal_rcc.h"
-#include "hal_bkp.h"
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup BKP_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup BKP_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the BKP peripheral registers to their default reset
-///         values.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void BKP_DeInit(void)
-{
-    RCC_BackupResetCmd(ENABLE);
-    RCC_BackupResetCmd(DISABLE);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the Tamper Pin active level.
-/// @param  tamper_pin_level: specifies the Tamper Pin active level.
-///         This parameter can be one of the following values:
-/// @arg    BKP_TamperPinLevel_High: Tamper pin active on high level
-/// @arg    BKP_TamperPinLevel_Low: Tamper pin active on low level
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void BKP_TamperPinLevelConfig(BKPTPAL_Typedef tamper_pin_level)
-{
-    BKP->CR = tamper_pin_level;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the Tamper Pin activation.
-/// @param  state: new state of the Tamper Pin activation.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void BKP_TamperPinCmd(FunctionalState state)
-{
-    (state) ? SET_BIT(BKP->CR, BKP_CR_TPE) : CLEAR_BIT(BKP->CR, BKP_CR_TPE);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the Tamper Pin Interrupt.
-/// @param  state: new state of the Tamper Pin Interrupt.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void BKP_ITConfig(FunctionalState state)
-{
-    (state) ? SET_BIT(BKP->CSR, BKP_CSR_TPIE) : CLEAR_BIT(BKP->CSR, BKP_CSR_TPIE);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Select the RTC output source to output on the Tamper pin.
-/// @param  rtc_output_source: specifies the RTC output source.
-///         This parameter can be one of the following values:
-/// @arg    BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
-/// @arg    BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
-///                                          divided by 64 on the Tamper pin.
-/// @arg    BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
-///                                     the Tamper pin.
-/// @arg    BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
-///                                      the Tamper pin.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void BKP_RTCOutputConfig(BKPRTCOUTPUTSRC_Typedef rtc_output_source)
-{
-    MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS, rtc_output_source);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets RTC Clock Calibration value.
-/// @param  calibration_value: specifies the RTC Clock Calibration value.
-///         This parameter must be a number between 0 and 0x7F.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void BKP_SetRTCCalibrationValue(u8 calibration_value)
-{
-    MODIFY_REG(BKP->RTCCR, BKP_RTCCR_CAL, calibration_value);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the Tamper Pin Event flag is set or not.
-/// @param  None.
-/// @retval State: The new state of the Tamper Pin Event flag (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus BKP_GetFlagStatus(void)
-{
-    return ((BKP->CSR & BKP_CSR_TEF) ? SET : RESET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears Tamper Pin Event pending flag.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void BKP_ClearFlag(void)
-{
-    SET_BIT(BKP->CSR, BKP_CSR_CTE);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
-/// @param  None.
-/// @retval State: The new state of the Tamper Pin Interrupt (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus BKP_GetITStatus(void)
-{
-    return ((BKP->CSR & BKP_CSR_TIF) ? SET : RESET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears Tamper Pin Interrupt pending bit.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void BKP_ClearITPendingBit(void)
-{
-    SET_BIT(BKP->CSR, BKP_CSR_CTI);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Writes user data to the specified data Backup Register.
-/// @param  bkp_dr: specifies the data Backup Register.
-///         This parameter can be BKP_DRx where x:[1, 10]
-/// @param  data: data to write
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void BKP_WriteBackupRegister(BKPDR_Typedef bkp_dr, u16 data)
-{
-    *(vu16*)(BKP_BASE + bkp_dr) = data;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Reads data from the specified data Backup Register.
-/// @param  bkp_dr: specifies the data Backup Register.
-///         This parameter can be BKP_DRx where x:[1, 10]
-/// @retval data: The content of the specified data Backup Register
-////////////////////////////////////////////////////////////////////////////////
-u16 BKP_ReadBackupRegister(BKPDR_Typedef bkp_dr)
-{
-    return (*(vu16*)(BKP_BASE + bkp_dr));
-}
-////////////////////////////////////////////////////////////////////////////////
-//          Extended function interface
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the BKP peripheral, enable access to the backup
-///         registers.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exBKP_Init(void)
-{
-    RCC_APB1PeriphClockCmd(RCC_APB1ENR_PWR, ENABLE);
-    //COMMON_EnableIpClock(emCLOCK_PWR);
-    RCC_APB1PeriphClockCmd(RCC_APB1ENR_BKP, ENABLE);
-    //COMMON_EnableIpClock(emCLOCK_BKP);
-
-    RCC->BDCR |= RCC_BDCR_DBP;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Writes user data to the specified data Backup Register immediately.
-/// @param  bkp_dr: specifies the data Backup Register.
-///         This parameter can be BKP_DRx where x:[1, 10]
-/// @param  data: data to write
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exBKP_ImmWrite(BKPDR_Typedef bkp_dr, u16 dat)
-{
-    RCC->BDCR |= RCC_BDCR_DBP;
-    *(vu16*)(BKP_BASE + bkp_dr) = dat;
-    RCC->BDCR &= ~RCC_BDCR_DBP;
-
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Reads data from the specified data Backup Register immediately.
-/// @param  bkp_dr: specifies the data Backup Register.
-///         This parameter can be BKP_DRx where x:[1, 10]
-/// @retval data: The content of the specified data Backup Register
-////////////////////////////////////////////////////////////////////////////////
-u16 exBKP_ImmRead(BKPDR_Typedef bkp_dr)
-{
-    u16 dat;
-    RCC->BDCR |= RCC_BDCR_DBP;
-    dat = (*(vu16*)(BKP_BASE + bkp_dr));
-    RCC->BDCR &= ~RCC_BDCR_DBP;
-    return dat;
-}
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c
deleted file mode 100644
index 9dd85df29..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_can.c
+++ /dev/null
@@ -1,696 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_can.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE CAN FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define __HAL_CAN_C
-
-// Files includes
-#include "hal_can.h"
-#include "hal_rcc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup CAN_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup CAN_Exported_Functions
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the CAN peripheral registers to their default reset
-/// values.
-/// @param  can: select the CAN peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_DeInit(CAN_TypeDef* can)
-{
-    exRCC_APB1PeriphReset(RCC_APB1ENR_CAN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief   Initializes the CAN peripheral according to the specified
-///          parameters in the CAN_InitStruct.
-/// @param   can: select the CAN peripheral.
-/// @param   CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
-///          contains the configuration information for the CAN peripheral.
-/// @retval  Constant indicates initialization succeed which will be
-///          CANINITFAILED or CANINITOK.
-////////////////////////////////////////////////////////////////////////////////
-u8 CAN_Init(CAN_TypeDef* can, CAN_Basic_InitTypeDef* init_struct)
-{
-    u8 InitStatus = CANINITFAILED;
-
-    can->BTR0 = ((u32)(init_struct->SJW) << 6) | ((u32)(init_struct->BRP));
-    can->BTR1 = ((u32)(init_struct->SAM) << 7) | ((u32)(init_struct->TESG2) << 4) | ((u32)(init_struct->TESG1));
-
-    if (init_struct->GTS == ENABLE) {
-        can->CMR |= (u32)CAN_SleepMode;
-        InitStatus = CANINITFAILED;
-    }
-    else {
-        can->CMR &= ~(u32)CAN_SleepMode;
-        InitStatus = CANINITOK;
-    }
-
-    (init_struct->GTS == ENABLE) ? (can->CMR |= (u32)CAN_SleepMode) : (can->CMR &= ~(u32)CAN_SleepMode);
-
-    can->CDR |=
-        ((init_struct->CBP) << 6) | ((init_struct->RXINTEN) << 5) | ((init_struct->CLOSE_OPEN_CLK) << 3) | (init_struct->CDCLK);
-
-    return InitStatus;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the CAN_Basic reception filter according to the specified
-///         parameters in the basic_filter_init_struct.
-/// @param  basic_filter_init_struct: pointer to a CAN_Basic_FilterInitTypeDef
-///         structure that contains the configuration information.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* basic_filter_init_struct)
-{
-    // Filter Mode
-    CAN1->ACR = basic_filter_init_struct->CAN_FilterId;
-    CAN1->AMR = basic_filter_init_struct->CAN_FilterMaskId;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param  init_struct : pointer to a CAN_Basic_InitTypeDef structure which will be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_StructInit(CAN_Basic_InitTypeDef* init_struct)
-{
-    // Reset CAN_Basic init structure parameters values
-
-    // initialize the BRP member(where can be set with (0..63))
-    init_struct->BRP = 0x0;
-    // initialize the SJW member(where can be set with (0..3))
-    init_struct->SJW = 0x0;
-    // Initialize the TESG1 member(where can be set with (0..15))
-    init_struct->TESG1 = 0x0;
-    // Initialize the TESG2 member(where can be set with(0..7))
-    init_struct->TESG2 = 0x0;
-    // Initialize the SAM member(where can be set (SET or RESET))
-    init_struct->SAM = RESET;
-    // Initialize the GTS member to Sleep Mode(where can be set (ENABLE or
-    // DISABLE))
-    init_struct->GTS = DISABLE;
-    // Initialize the external pin CLKOUT frequence
-    init_struct->CDCLK = 0x0;
-    // Initialize the external clk is open or close
-    init_struct->CLOSE_OPEN_CLK = 0x0;
-    // Initialize the TX1 pin work as rx interrupt output
-    init_struct->RXINTEN = 0x0;
-    // Initialize the CBP of CDR register
-    init_struct->CBP = 0x0;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified CAN interrupts.
-/// @param  can:  select the CAN peripheral.
-/// @param  it: specifies the CAN interrupt sources to be enabled or
-///         disabled.
-///         This parameter can be: CAN_IT_OIE, CAN_IT_EIE, CAN_IT_TIE,
-///         CAN_IT_RIE.
-/// @param  state: new state of the CAN interrupts.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_ITConfig(CAN_TypeDef* can, u32 it, FunctionalState state)
-{
-    (state) ? (can->CR |= it) : (can->CR &= ~it);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initiates and transmits a CAN frame message.
-/// @param  can:select the CAN peripheral.
-/// @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
-///         CAN data.
-/// @retval CANTXOK if the CAN driver transmits the message
-////////////////////////////////////////////////////////////////////////////////
-u8 CAN_Transmit(CAN_TypeDef* can, CanBasicTxMsg* basic_transmit_message)
-{
-    can->TXID0 = (basic_transmit_message->IDH);
-    can->TXID1 = (basic_transmit_message->IDL << 5) | (basic_transmit_message->RTR << 4) | (basic_transmit_message->DLC);
-    if ((FunctionalState)(basic_transmit_message->RTR) != ENABLE) {
-        can->TXDR0 = basic_transmit_message->Data[0];
-        can->TXDR1 = basic_transmit_message->Data[1];
-        can->TXDR2 = basic_transmit_message->Data[2];
-        can->TXDR3 = basic_transmit_message->Data[3];
-        can->TXDR4 = basic_transmit_message->Data[4];
-        can->TXDR5 = basic_transmit_message->Data[5];
-        can->TXDR6 = basic_transmit_message->Data[6];
-        can->TXDR7 = basic_transmit_message->Data[7];
-    }
-
-    can->CMR = CAN_CMR_TR;
-
-    return (can->SR & 0x01);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Cancels a transmit request.
-/// @param  can: select the CAN peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_CancelTransmit(CAN_TypeDef* can)
-{
-    // abort transmission
-    can->CMR = CAN_AT;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Releases the specified receive FIFO.
-/// @param  can: select the CAN peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_FIFORelease(CAN_TypeDef* can)
-{
-    // Release FIFO
-    can->CMR |= (u32)CAN_RRB;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Receives a correct CAN frame.
-/// @param  can: select the CAN peripheral.
-/// @param  RxMessage: pointer to a structure receive frame which contains CAN
-///         Id,CAN DLC, CAN data and FMI number.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Receive(CAN_TypeDef* can, CanBasicRxMsg* basic_receive_message)
-{
-    u16 tempid;
-
-    basic_receive_message->RTR = (u8)((can->RXID1) >> 4) & 0x1;
-    basic_receive_message->DLC = (u8)((can->RXID1) & 0xf);
-    tempid              = (u16)(((can->RXID1) & 0xe0) >> 5);
-    tempid |= (u16)(can->RXID0 << 3);
-    basic_receive_message->ID      = tempid;
-    basic_receive_message->Data[0] = CAN1->RXDR0;
-    basic_receive_message->Data[1] = CAN1->RXDR1;
-    basic_receive_message->Data[2] = CAN1->RXDR2;
-    basic_receive_message->Data[3] = CAN1->RXDR3;
-    basic_receive_message->Data[4] = CAN1->RXDR4;
-    basic_receive_message->Data[5] = CAN1->RXDR5;
-    basic_receive_message->Data[6] = CAN1->RXDR6;
-    basic_receive_message->Data[7] = CAN1->RXDR7;
-    CAN_FIFORelease(can);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Select the Sleep mode or not in Basic workmode
-/// @param  state to go into the Sleep mode or go out
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-u8 CAN_Sleep(CAN_TypeDef* can)
-{
-    can->CMR |= CAN_SleepMode;
-    // At this step, sleep mode status
-    return (u8)((can->CMR & 0x10) == CAN_SleepMode) ? CANSLEEPOK : CANSLEEPFAILED;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Wakes the CAN up.
-/// @param  can: where x can be 1 to select the CAN peripheral.
-/// @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.
-////////////////////////////////////////////////////////////////////////////////
-u8 CAN_WakeUp(CAN_TypeDef* can)
-{
-    // Wake up request
-    can->CMR &= ~CAN_SleepMode;
-    return (u8)((can->CMR & 0x01) == 0) ? CANWAKEUPOK : CANWAKEUPFAILED;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified CAN flag is set or not.
-/// @param  can: select the CAN peripheral.
-/// @param  flag: specifies the flag to check.
-///         This parameter can be one of the following values:
-///            @arg CAN_STATUS_RBS: Receive buffer status
-///            @arg CAN_STATUS_DOS: Data overflow status
-///            @arg CAN_STATUS_TBS: Transmit buffer status
-///            @arg CAN_STATUS_TCS: Transmit complete status
-///            @arg CAN_STATUS_RS: Receiving status
-///            @arg CAN_STATUS_TS: Transmiting status
-///            @arg CAN_STATUS_ES: Error status
-///            @arg CAN_STATUS_BS: bus status, close or open
-/// @retval The new state of CAN_FLAG (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* can, u32 flag)
-{
-    return (FlagStatus)(((can->SR & flag) == flag) ? SET : RESET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified CAN interrupt has occurred or not.
-/// @param  can: where x can be 1 to select the CAN peripheral.
-/// @param  it: specifies the CAN interrupt source to check.
-///         This parameter can be one of the following values:
-///            @arg CAN_IT_RI: Receive FIFO not empty Interrupt
-///            @arg CAN_IT_TI: Transmit Interrupt
-///            @arg CAN_IT_EI: ERROR Interrupt
-///            @arg CAN_IT_DOI: Data voerflow Interrupt
-///            @arg CAN_IT_WUI: Wakeup Interrupt
-///            @arg CAN_IT_ALL: use it can enble all Interrupt
-/// @retval The current state of it (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus CAN_GetITStatus(CAN_TypeDef* can, u32 it)
-{
-    return (ITStatus)((can->IR & it) != it) ? RESET : SET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Select the can work as peli mode or basic mode
-/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
-/// @param  CAN_MODE: specifies the work mode:CAN_BASICMode,CAN_PELIMode
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Mode_Cmd(CAN_TypeDef* can, u32 mode)
-{
-    can->CDR |= mode;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Select the Reset mode or not
-/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
-/// @param  state to go into the Reset mode or go out
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_ResetMode_Cmd(CAN_TypeDef* can, FunctionalState state)
-{
-    (state == ENABLE) ? (can->CR |= CAN_ResetMode) : (can->CR &= ~CAN_ResetMode);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clear the data overflow.
-/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_ClearDataOverflow(CAN_TypeDef* can)
-{
-    can->CMR |= (u32)CAN_CDO;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the CAN's IT pending.
-/// @param  can: where x can be 1 or 2 to to select the CAN peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_ClearITPendingBit(CAN_TypeDef* can)
-{
-    u32 temp = 0;
-    temp     = temp;
-    temp     = can->IR;  // read this register clear all interrupt
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Select the Sleep mode or not in Peli workmode
-/// @param  state to go into the Sleep mode or go out
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Peli_SleepMode_Cmd(FunctionalState state)
-{
-    (state == ENABLE) ? (CAN1_PELI->MOD |= CAN_SleepMode) : (CAN1_PELI->MOD &= ~CAN_SleepMode);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each CAN1_PELI_InitStruct member with its default value.
-/// @param  init_struct : pointer to a CAN_Peli_InitTypeDef structure
-///         which will be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* init_struct)
-{
-    //--------------- Reset CAN_Peli init structure parameters values
-    //---------------
-    init_struct->BRP   = 0x0;      // initialize the BRP member(where can be set with (0..63))
-    init_struct->SJW   = 0x0;      // initialize the SJW member(where can be set with (0..3))
-    init_struct->TESG1 = 0x0;      // Initialize the TESG1 member(where can be set with (0..15))
-    init_struct->TESG2 = 0x0;      // Initialize the TESG2 member(where can be set with(0..7))
-    init_struct->SAM   = RESET;    // Initialize the SAM member(where can be set (SET or RESET))
-    init_struct->LOM   = DISABLE;  // Initialize the LOM member
-    init_struct->STM   = DISABLE;  // Initialize the STM member
-    init_struct->SM    = DISABLE;  // Initialize the SM member
-    init_struct->SRR   = DISABLE;
-    init_struct->EWLR  = 0x96;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the CAN_Peli peripheral according to the specified
-///         parameters in the init_struct.
-/// @param  init_struct: pointer to a CAN_Peli_InitTypeDef structure that
-///         contains the configuration information for the CAN peripheral in the peli workmode.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Peli_Init(CAN_Peli_InitTypeDef* init_struct)
-{
-    CAN1_PELI->BTR0 = ((u32)init_struct->SJW << 6) | ((u32)init_struct->BRP);
-    CAN1_PELI->BTR1 = ((u32)init_struct->SAM << 7) | ((u32)init_struct->TESG2 << 4) | ((u32)init_struct->TESG1);
-    if (init_struct->LOM == ENABLE)
-        CAN1_PELI->MOD |= (u32)CAN_ListenOnlyMode;
-    else
-        CAN1_PELI->MOD &= ~(u32)CAN_ListenOnlyMode;
-    if (init_struct->STM == ENABLE)
-        CAN1_PELI->MOD |= (u32)CAN_SeftTestMode;
-    else
-        CAN1_PELI->MOD &= ~(u32)CAN_SeftTestMode;
-    if (init_struct->SM == ENABLE)
-        CAN1_PELI->MOD |= (u32)CAN_SleepMode;
-    else
-        CAN1_PELI->MOD &= ~(u32)CAN_SleepMode;
-    CAN1_PELI->EWLR = (u32)init_struct->EWLR;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the CAN_Peli reception filter according to the specified
-///         parameters in the peli_filter_init_struct.
-/// @param  peli_filter_init_struct: pointer to a CAN_Peli_FilterInitTypeDef
-///         structure that contains the configuration information.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct)
-{
-    (peli_filter_init_struct->AFM == CAN_FilterMode_Singal) ? (CAN1_PELI->MOD |= (u32)CAN_FilterMode_Singal)
-    : (CAN1_PELI->MOD &= (u32)CAN_FilterMode_Double);
-
-    CAN1_PELI->FF    = peli_filter_init_struct->CAN_FilterId0;
-    CAN1_PELI->ID0   = peli_filter_init_struct->CAN_FilterId1;
-    CAN1_PELI->ID1   = peli_filter_init_struct->CAN_FilterId2;
-    CAN1_PELI->DATA0 = peli_filter_init_struct->CAN_FilterId3;
-
-    CAN1_PELI->DATA1 = peli_filter_init_struct->CAN_FilterMaskId0;
-    CAN1_PELI->DATA2 = peli_filter_init_struct->CAN_FilterMaskId1;
-    CAN1_PELI->DATA3 = peli_filter_init_struct->CAN_FilterMaskId2;
-    CAN1_PELI->DATA4 = peli_filter_init_struct->CAN_FilterMaskId3;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each peli_filter_init_struct member with its default value.
-/// @param  peli_filter_init_struct: pointer to a CAN_InitTypeDef structure
-///         which ill be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* peli_filter_init_struct)
-{
-    peli_filter_init_struct->CAN_FilterId0 = 0;
-    peli_filter_init_struct->CAN_FilterId1 = 0;
-    peli_filter_init_struct->CAN_FilterId2 = 0;
-    peli_filter_init_struct->CAN_FilterId3 = 0;
-
-    peli_filter_init_struct->CAN_FilterMaskId0 = 0;
-    peli_filter_init_struct->CAN_FilterMaskId1 = 0;
-    peli_filter_init_struct->CAN_FilterMaskId2 = 0;
-    peli_filter_init_struct->CAN_FilterMaskId3 = 0;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initiates and transmits a CAN frame message.
-/// @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
-///         CAN data.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Peli_Transmit(CanPeliTxMsg* peli_transmit_message)
-{
-    CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC);
-    if (((FunctionalState)peli_transmit_message->FF) != ENABLE) {
-        CAN1_PELI->ID0 = (peli_transmit_message->IDHH);
-
-        CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0);
-        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
-            CAN1_PELI->DATA0 = peli_transmit_message->Data[0];
-            CAN1_PELI->DATA1 = peli_transmit_message->Data[1];
-            CAN1_PELI->DATA2 = peli_transmit_message->Data[2];
-            CAN1_PELI->DATA3 = peli_transmit_message->Data[3];
-            CAN1_PELI->DATA4 = peli_transmit_message->Data[4];
-            CAN1_PELI->DATA5 = peli_transmit_message->Data[5];
-            CAN1_PELI->DATA6 = peli_transmit_message->Data[6];
-            CAN1_PELI->DATA7 = peli_transmit_message->Data[7];
-        }
-    }
-    else {
-        CAN1_PELI->ID0   = peli_transmit_message->IDHH;
-        CAN1_PELI->ID1   = peli_transmit_message->IDHL;
-        CAN1_PELI->DATA0 = peli_transmit_message->IDLH;
-        CAN1_PELI->DATA1 = peli_transmit_message->IDLL;
-        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
-            CAN1_PELI->DATA2 = peli_transmit_message->Data[0];
-            CAN1_PELI->DATA3 = peli_transmit_message->Data[1];
-            CAN1_PELI->DATA4 = peli_transmit_message->Data[2];
-            CAN1_PELI->DATA5 = peli_transmit_message->Data[3];
-            CAN1_PELI->DATA6 = peli_transmit_message->Data[4];
-            CAN1_PELI->DATA7 = peli_transmit_message->Data[5];
-            CAN1_PELI->DATA8 = peli_transmit_message->Data[6];
-            CAN1_PELI->DATA9 = peli_transmit_message->Data[7];
-        }
-    }
-
-    (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR | CAN_CMR_AT);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initiates and transmits a CAN frame message.
-/// @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and
-///         CAN data.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Peli_TransmitRepeat(CanPeliTxMsg* peli_transmit_message)
-{
-    CAN1_PELI->FF = (peli_transmit_message->FF << 7) | (peli_transmit_message->RTR << 6) | (peli_transmit_message->DLC);
-    if (((FunctionalState)peli_transmit_message->FF) != ENABLE) {
-        CAN1_PELI->ID0 = (peli_transmit_message->IDHH);
-
-        CAN1_PELI->ID1 = (peli_transmit_message->IDHL & 0xE0);
-        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
-            CAN1_PELI->DATA0 = peli_transmit_message->Data[0];
-            CAN1_PELI->DATA1 = peli_transmit_message->Data[1];
-            CAN1_PELI->DATA2 = peli_transmit_message->Data[2];
-            CAN1_PELI->DATA3 = peli_transmit_message->Data[3];
-            CAN1_PELI->DATA4 = peli_transmit_message->Data[4];
-            CAN1_PELI->DATA5 = peli_transmit_message->Data[5];
-            CAN1_PELI->DATA6 = peli_transmit_message->Data[6];
-            CAN1_PELI->DATA7 = peli_transmit_message->Data[7];
-        }
-    }
-    else {
-        CAN1_PELI->ID0   = peli_transmit_message->IDHH;
-        CAN1_PELI->ID1   = peli_transmit_message->IDHL;
-        CAN1_PELI->DATA0 = peli_transmit_message->IDLH;
-        CAN1_PELI->DATA1 = peli_transmit_message->IDLL;
-        if ((FunctionalState)(peli_transmit_message->RTR) != ENABLE) {
-            CAN1_PELI->DATA2 = peli_transmit_message->Data[0];
-            CAN1_PELI->DATA3 = peli_transmit_message->Data[1];
-            CAN1_PELI->DATA4 = peli_transmit_message->Data[2];
-            CAN1_PELI->DATA5 = peli_transmit_message->Data[3];
-            CAN1_PELI->DATA6 = peli_transmit_message->Data[4];
-            CAN1_PELI->DATA7 = peli_transmit_message->Data[5];
-            CAN1_PELI->DATA8 = peli_transmit_message->Data[6];
-            CAN1_PELI->DATA9 = peli_transmit_message->Data[7];
-        }
-    }
-
-    (CAN1_PELI->MOD & CAN_MOD_STM) ? (CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT) : (CAN1->CMR = CAN_CMR_TR);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Receives a correct CAN frame.
-/// @param  RxMessage: pointer to a structure receive frame which contains CAN
-///         Id,CAN DLC, CAN data and FMI number.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Peli_Receive(CanPeliRxMsg* peli_receive_message)
-{
-    u32 tempid;
-    peli_receive_message->FF  = (CAN1_PELI->FF) >> 7;
-    peli_receive_message->RTR = ((CAN1_PELI->FF) >> 6) & 0x1;
-    peli_receive_message->DLC = (CAN1_PELI->FF) & 0xf;
-
-    if (((FunctionalState)peli_receive_message->FF) != ENABLE) {
-        tempid = (u32)(CAN1_PELI->ID1 >> 5);
-        tempid |= (u32)(CAN1_PELI->ID0 << 3);
-        peli_receive_message->ID      = tempid;
-        peli_receive_message->Data[0] = CAN1_PELI->DATA0;
-        peli_receive_message->Data[1] = CAN1_PELI->DATA1;
-        peli_receive_message->Data[2] = CAN1_PELI->DATA2;
-        peli_receive_message->Data[3] = CAN1_PELI->DATA3;
-        peli_receive_message->Data[4] = CAN1_PELI->DATA4;
-        peli_receive_message->Data[5] = CAN1_PELI->DATA5;
-        peli_receive_message->Data[6] = CAN1_PELI->DATA6;
-        peli_receive_message->Data[7] = CAN1_PELI->DATA7;
-    }
-    else {
-        tempid = (u32)((CAN1_PELI->DATA1 & 0xf8) >> 3);
-        tempid |= (u32)(CAN1_PELI->DATA0 << 5);
-        tempid |= (u32)(CAN1_PELI->ID1 << 13);
-        tempid |= (u32)(CAN1_PELI->ID0 << 21);
-        peli_receive_message->ID      = tempid;
-        peli_receive_message->Data[0] = CAN1_PELI->DATA2;
-        peli_receive_message->Data[1] = CAN1_PELI->DATA3;
-        peli_receive_message->Data[2] = CAN1_PELI->DATA4;
-        peli_receive_message->Data[3] = CAN1_PELI->DATA5;
-        peli_receive_message->Data[4] = CAN1_PELI->DATA6;
-        peli_receive_message->Data[5] = CAN1_PELI->DATA7;
-        peli_receive_message->Data[6] = CAN1_PELI->DATA8;
-        peli_receive_message->Data[7] = CAN1_PELI->DATA9;
-    }
-    CAN_FIFORelease(CAN1);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Get available current informatoin in receive FIFO only in Peli
-///         workmode.
-/// @retval The value in reg RMC
-////////////////////////////////////////////////////////////////////////////////
-u32 CAN_Peli_GetRxFIFOInfo(void)
-{
-    return CAN1_PELI->RMC;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the CAN's last error code (LEC).
-/// @retval Error code:
-///          - CAN_ERRORCODE_NoErr: No Error
-///          - CAN_ERRORCODE_StuffErr: Stuff Error
-///          - CAN_ERRORCODE_FormErr: Form Error
-///          - CAN_ERRORCODE_ACKErr : Acknowledgment Error
-///          - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
-///          - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
-///          - CAN_ERRORCODE_CRCErr: CRC Error
-///          - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
-////////////////////////////////////////////////////////////////////////////////
-u8 CAN_Peli_GetLastErrorCode(void)
-{
-    // Return the error code
-    return (u8)CAN1_PELI->ECC;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the CAN Receive Error Counter (REC).
-/// @note   In case of an error during reception, this counter is incremented
-///         by 1 or by 8 depending on the error condition as defined by the CAN
-///         standard. After every successful reception, the counter is
-///         decremented by 1 or reset to 120 if its value was higher than 128.
-///         When the counter value exceeds 127, the CAN controller enters the
-///         error passive state.
-/// @retval CAN Receive Error Counter.
-////////////////////////////////////////////////////////////////////////////////
-u8 CAN_Peli_GetReceiveErrorCounter(void)
-{
-    // Return the Receive Error Counter
-    return (u8)(CAN1_PELI->RXERR);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the LSB of the 9-bit can Transmit Error Counter(TEC).
-/// @retval LSB of the 8-bit CAN Transmit Error Counter.
-////////////////////////////////////////////////////////////////////////////////
-u8 CAN_Peli_GetLSBTransmitErrorCounter(void)
-{
-    // Return the LSB of the 8-bit CAN Transmit Error Counter(TEC)
-    return (u8)(CAN1_PELI->TXERR);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified CAN interrupts in peli workmode.
-/// @param  it: specifies the CAN interrupt sources to be enabled or
-///         disabled.
-///         This parameter can be:
-/// @arg    CAN_IT_RI: Receive FIFO not empty Interrupt
-/// @arg    CAN_IT_TI: Transmit Interrupt
-/// @arg    CAN_IT_EI: ERROR Interrupt
-/// @arg    CAN_IT_DOI: Data voerflow Interrupt
-/// @arg    CAN_IT_WUI: Wakeup Interrupt
-/// @arg    CAN_IT_EPI(only Peli): passive error Interrupt
-/// @arg    CAN_IT_ALI(only Peli): arbiter lose Interrupt
-/// @arg    CAN_IT_BEI(only Peli): bus error Interrupt
-/// @arg    CAN_IT_ALL: use it can enble all Interrupt
-/// @param  state: new state of the CAN interrupts.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CAN_Peli_ITConfig(u32 it, FunctionalState state)
-{
-    (state) ? (CAN1_PELI->IER |= it) : (CAN1_PELI->IER &= ~it);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified CAN interrupt has occurred or not.
-/// @param  it: specifies the CAN interrupt source to check.
-///         This parameter can be one of the following values:
-/// @arg    CAN_IT_RI: Receive FIFO not empty Interrupt
-/// @arg    CAN_IT_TI: Transmit Interrupt
-/// @arg    CAN_IT_EI: ERROR Interrupt
-/// @arg    CAN_IT_DOI: Data voerflow Interrupt
-/// @arg    CAN_IT_WUI: Wakeup Interrupt
-/// @arg    CAN_IT_EPI(only Peli): passive error Interrupt
-/// @arg    CAN_IT_ALI(only Peli): arbiter lose Interrupt
-/// @arg    CAN_IT_BEI(only Peli): bus error Interrupt
-/// @arg    CAN_IT_ALL: use it can enble all Interrupt
-/// @retval The current state of it (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus CAN_Peli_GetITStatus(u32 it)
-{
-    return (ITStatus)(((CAN1_PELI->IR & it) != it) ? RESET : SET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Config CAN_Peli_InitTypeDef baud parameter.
-/// @param  CAN_Peli_InitTypeDef: CAN struct.
-/// @param  src_clk: CAN module clock.
-/// @param  baud: specified baud.
-/// @retval The current state of it (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef* init_struct, u32 src_clk, u32 baud)
-{
-    u32 i, value = baud, record = 1;
-    u32 remain = 0, sumPrescaler = 0;
-    while ((baud == 0) || (src_clk == 0))
-        ;
-    sumPrescaler = src_clk / baud;
-    sumPrescaler = sumPrescaler / 2;
-    for (i = 25; i > 3; i--) {
-        remain = sumPrescaler - ((sumPrescaler / i) * i);
-        if (remain == 0) {
-            record = i;
-            break;
-        }
-        else {
-            if (remain < value) {
-                value  = remain;
-                record = i;
-            }
-        }
-    }
-    init_struct->SJW   = 0;
-    init_struct->BRP   = (sumPrescaler / record) - 1;
-    init_struct->TESG2 = (record - 3) / 3;
-    init_struct->TESG1 = (record - 3) - init_struct->TESG2;
-}
-
-/// @}
-
-/// @}
-
-/// @}
-
-
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c
deleted file mode 100644
index b55558263..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_comp.c
+++ /dev/null
@@ -1,226 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_comp.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE COMP FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_COMP_C_
-
-// Files includes
-#include "hal_comp.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup COMP_HAL
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup COMP_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes COMP peripheral registers to their default reset
-///         values.
-/// @param  selection: the selected comparator.
-///         select the COMP peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void COMP_DeInit(COMP_Selection_TypeDef selection)
-{
-    *(vu32*)(COMP_BASE + selection) = 0;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the COMP peripheral according to the specified
-/// @param  selection: the selected comparator.
-///         select the COMP peripheral.
-/// @param  init_struct: pointer to an COMP_InitTypeDef structure that
-///         contains the configuration information for the specified COMP
-///         peripheral.
-///         - COMP_InvertingInput specifies the inverting input of COMP
-///         - COMP_NonInvertingInput specifies the non inverting input of COMP
-///         - COMP_Output connect COMP output to selected timer
-///           input (Input capture / Output Compare Reference Clear / Break
-///           Input)
-///         - COMP_BlankingSrce specifies the blanking source of COMP
-///         - COMP_OutputPol select output polarity
-///         - COMP_Hysteresis configures COMP hysteresis value
-///         - COMP_Mode configures COMP power mode
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void COMP_Init(COMP_Selection_TypeDef selection, COMP_InitTypeDef* init_struct)
-{
-    *(vu32*)(COMP_BASE + selection) =    init_struct->Invert     |
-                                         init_struct->NonInvert  |
-                                         init_struct->Output     |
-                                         init_struct->OutputPol  |
-                                         init_struct->BlankingSrce   |
-                                         init_struct->Hysteresis |
-                                         init_struct->Mode       |
-                                         init_struct->OFLT;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param  init_struct: pointer to an COMP_InitTypeDef structure which will
-///         be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void COMP_StructInit(COMP_InitTypeDef* init_struct)
-{
-
-    init_struct->Invert         = COMP_InvertingInput_IO1;
-    init_struct->NonInvert      = COMP_NonInvertingInput_IO1;
-    init_struct->Output         = COMP_Output_None;
-    init_struct->BlankingSrce   = COMP_BlankingSrce_None;
-    init_struct->OutputPol      = COMP_NonInverted;
-    init_struct->Hysteresis     = COMP_Hysteresis_No;
-    init_struct->Mode           = COMP_Mode_UltraLowPower;
-    init_struct->OFLT           = COMP_Filter_4_Period;                                                               ///< to adjust the speed/consumption.
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enable or disable the COMP peripheral.
-/// @param  selection: the selected comparator.
-///         select the COMP peripheral.
-/// @param  NewState: new state of the COMP peripheral.
-///         This parameter can be: ENABLE or DISABLE.
-///         When enabled, the comparator compares the non inverting input with
-///         the inverting input and the comparison result is available on
-///         comparator output.
-///         When disabled, the comparator doesn't perform comparison and the
-///         output level is low.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void COMP_Cmd(COMP_Selection_TypeDef selection, FunctionalState state)
-{
-    (state) ? (*(vu32*)(COMP_BASE + selection) |=  COMP_CSR_EN) :
-    (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_EN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Select CRV param.
-/// @param  crv_select: Select source for CRV.
-/// @param  crv_level: Set level for CRV.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void COMP_SetCrv(u8 crv_select, u8 crv_level)
-{
-    u32 temreg = 0;
-    temreg = COMP->CRV;
-    temreg &= ~COMP_CRV_MASK;
-    // Load config to CRV and enable
-    temreg |= crv_select | crv_level | (1 << 4);
-    COMP->CRV = temreg;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Close or Open the SW1 switch.
-/// @param  selection: the selected comparator.
-///         select the COMP peripheral.
-/// @param  state: new state of the COMP peripheral.
-///         This parameter can be: ENABLE or DISABLE.
-///         When enabled, the comparator compares the non inverting input with
-///         the inverting input and the comparison result is available on
-///         comparator output.
-///         When disabled, the comparator doesn't perform comparison and the
-///         output level is low.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void COMP_SwitchCmd(COMP_Selection_TypeDef selection, FunctionalState state)
-{
-    (state) ?
-    (*(vu32*)(COMP_BASE + selection) |=  COMP_CSR_COMPSW1) :
-    (*(vu32*)(COMP_BASE + selection) &= ~COMP_CSR_COMPSW1);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Return the output level (high or low) of the selected comparator.
-///         The output level depends on the selected polarity.
-///         If the polarity is not inverted:
-///           - Comparator output is low when the non-inverting input is at a
-///           lower voltage than the inverting input
-///           - Comparator output is high when the non-inverting input is at a
-///           higher voltage than the inverting input
-///         If the polarity is inverted:
-///           - Comparator output is high when the non-inverting input is at a
-///           lower voltage than the inverting input
-///           - Comparator output is low when the non-inverting input is at a
-///           higher voltage than the inverting input
-/// @param  comp: the selected comparator.
-///         select the COMP peripheral.
-/// @retval  The selected comparator output level: low or high.
-////////////////////////////////////////////////////////////////////////////////
-u32 COMP_GetOutputLevel(COMP_Selection_TypeDef selection)
-{
-    return (((*(vu32*)(COMP_BASE + selection) & COMP_CSR_STA) != 0) ?
-            COMP_OutputLevel_High :
-            COMP_OutputLevel_Low );
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Lock the selected comparator (COMP1/COMP2) configuration.
-/// @param  selection: the selected comparator.
-///         select the COMP peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void COMP_LockConfig(COMP_Selection_TypeDef selection)
-{
-    *(vu32*)(COMP_BASE + selection) |= COMP_CSR_LOCK;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enable or disable the COMP register.
-/// @param  state: new state of the COMP peripheral.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exCOMP_CrvCmd(FunctionalState state)
-{
-    (state) ? (COMP->CRV |= COMP_CRV_EN_ENABLE) : (COMP->CRV &= ~COMP_CRV_EN_ENABLE);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Select comparator external reference voltage.
-/// @param  selection: the selected external reference voltage.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exCOMP_SwitchCrv(u32 crv)
-{
-    COMP->CRV |= crv;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Select comparator external reference voltage source.
-/// @param  selection: the selected external reference voltage source.
-///         This parameter can be: COMP_CRV_SRC_AVDD or COMP_CRV_SRC_VREF.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exCOMP_CrvSrc(u32 src)
-{
-    COMP->CRV |= src;
-}
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c
deleted file mode 100644
index 817698bf5..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crc.c
+++ /dev/null
@@ -1,108 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_crc.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE CRC FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_CRC_C_
-
-// Files includes
-#include "hal_crc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup CRC_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup CRC_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Resets the CRC Data register (DR).
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CRC_ResetDR()
-{
-    CRC->CR = CRC_CR_RESET;
-}
-//#pragma optimize(0)
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Computes the 32-bit CRC of a given data word(32-bit).
-/// @param  Data: data word(32-bit) to compute its CRC
-/// @retval 32-bit CRC
-////////////////////////////////////////////////////////////////////////////////
-u32 CRC_CalcCRC(u32 data)
-{
-    CRC->DR = data;
-    return (CRC->DR);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
-/// @param  buffer: pointer to the buffer containing the data to be computed
-/// @param  length: length of the buffer to be computed
-/// @retval 32-bit CRC
-////////////////////////////////////////////////////////////////////////////////
-u32 CRC_CalcBlockCRC(u32* buffer, u32 length)
-{
-    u32 i;
-    for (i = 0; i < length; i++) {
-        CRC->DR = buffer[i];
-    }
-    return (CRC->DR);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the current CRC value.
-/// @param  None.
-/// @retval 32-bit CRC
-////////////////////////////////////////////////////////////////////////////////
-u32 CRC_GetCRC(void)
-{
-    return (CRC->DR);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Stores a 8-bit data in the Independent Data(ID) register.
-/// @param  id_value: 8-bit value to be stored in the ID register
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void CRC_SetIDRegister(u8 id_value)
-{
-    CRC->IDR = id_value;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the 8-bit data stored in the Independent Data(ID) register
-/// @param  None.
-/// @retval 8-bit value of the ID register
-////////////////////////////////////////////////////////////////////////////////
-u8 CRC_GetIDRegister()
-{
-    return (CRC->IDR);
-}
-
-/// @}
-
-/// @}
-
-/// @}
-
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c
deleted file mode 100644
index 10b26d353..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_crs.c
+++ /dev/null
@@ -1,43 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_crs.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE CRS FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_CRS_C_
-
-// Files includes
-#include "hal_rcc.h"
-#include "hal_crs.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup CRS_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup CRS_Exported_Functions
-/// @{
-
-/// @}
-
-/// @}
-
-/// @}
-
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c
deleted file mode 100644
index b3583f155..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dac.c
+++ /dev/null
@@ -1,184 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_dac.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE DAC FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_DAC_C_
-
-// Files includes
-#include "hal_dac.h"
-#include "hal_rcc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup DAC_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup DAC_Exported_Functions
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the DAC peripheral registers to their default reset values.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_DeInit(void)
-{
-    exRCC_APB1PeriphReset(RCC_APB1ENR_DAC);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the DAC peripheral according to the specified parameters in the DAC_InitStruct.
-/// @param channel: the selected DAC channel.
-/// @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains the configuration information for the specified
-/// DAC channel.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_Init(emDACCH_TypeDef channel, DAC_InitTypeDef* init_struct)
-{
-    DAC->CR &= ~((DAC_CR_BOFF1 | DAC_CR_TEN1 | DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_MAMP1) << channel);
-    DAC->CR |= (((u32)(init_struct->DAC_Trigger) | (u32)(init_struct->DAC_WaveGeneration) |
-                 (u32)(init_struct->DAC_LFSRUnmask_TriangleAmplitude) | (u32)(init_struct->DAC_OutputBuffer))
-                << channel);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each DAC_InitStruct member with its default value.
-/// @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_StructInit(DAC_InitTypeDef* init_struct)
-{
-    init_struct->DAC_Trigger                      = DAC_Trigger_None;
-    init_struct->DAC_WaveGeneration               = DAC_WaveGeneration_None;
-    init_struct->DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1;
-    init_struct->DAC_OutputBuffer                 = DAC_OutputBuffer_Enable;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified DAC channel.
-/// @param channel: the selected DAC channel.
-/// @param state: new state of the DAC channel.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_Cmd(emDACCH_TypeDef channel, FunctionalState state)
-{
-    (state) ? (DAC->CR |= DAC_CR_EN1 << channel) : (DAC->CR &= ~(DAC_CR_EN1 << channel));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified DAC channel DMA request.
-/// @param channel: the selected DAC channel.
-/// @param state: new state of the selected DAC channel DMA request.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_DMACmd(emDACCH_TypeDef channel, FunctionalState state)
-{
-    (state) ? (DAC->CR |= DAC_CR_DMAEN1 << channel) : (DAC->CR &= ~(DAC_CR_DMAEN1 << channel));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the selected DAC channel software trigger.
-/// @param channel: the selected DAC channel.
-/// @param state: new state of the selected DAC channel software trigger.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_SoftwareTriggerCmd(emDACCH_TypeDef channel, FunctionalState state)
-{
-    (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 << (channel >> 4)))
-    : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 << (channel >> 4)));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables simultaneously the two DAC channels software triggers.
-/// @param state: new state of the DAC channels software triggers.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_DualSoftwareTriggerCmd(FunctionalState state)
-{
-    (state) ? (DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2))
-    : (DAC->SWTRIGR &= ~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the selected DAC channel wave generation.
-/// @param channel: the selected DAC channel.
-/// @param wave: Specifies the wave type to enable or disable.
-/// @param state: new state of the selected DAC channel wave generation.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_WaveGenerationCmd(emDACCH_TypeDef channel, emDACWAVE_TypeDef wave, FunctionalState state)
-{
-    (state) ? (DAC->CR |= wave << channel) : (DAC->CR &= ~(wave << channel));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the specified data holding register value for DAC channel1.
-/// @param alignement: Specifies the data alignement for DAC channel1.
-/// @param data : data to be loaded in the selected data holding register.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_SetChannel1Data(emDACALIGN_TypeDef alignement, u16 data)
-{
-    *((u32*)(DAC_BASE + DHR12R1_Offset + alignement)) = data;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the specified data holding register value for DAC channel2.
-/// @param alignement: Specifies the data alignement for DAC channel2.
-/// @param data : data to be loaded in the selected data holding
-///   register.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_SetChannel2Data(emDACALIGN_TypeDef alignement, u16 data)
-{
-    *((u32*)(DAC_BASE + DHR12R2_Offset + alignement)) = data;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the specified data holding register value for dual channel DAC.
-/// @param alignement: Specifies the data alignement for dual channel DAC.
-/// @param data2: data for DAC Channel2 to be loaded in the selected data holding register.
-/// @param data1: data for DAC Channel1 to be loaded in the selected data holding register.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DAC_SetDualChannelData(emDACALIGN_TypeDef alignement, u16 data2, u16 data1)
-{
-    u32 data = ((alignement == DAC_Align_8b_R) ? ((data2 << 8) | data1) : ((data2 << 16) | data1));
-    *((u32*)(DAC_BASE + DHR12RD_Offset + alignement)) = data;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the last data output value of the selected DAC cahnnel.
-/// @param channel: the selected DAC channel.
-/// @retval  The selected DAC channel data output value.
-////////////////////////////////////////////////////////////////////////////////
-u16 DAC_GetDataOutputValue(emDACCH_TypeDef channel)
-{
-    return (*(vu32*)(DAC_BASE + DOR_Offset + (channel >> 2)));
-}
-/// @}
-
-/// @}
-
-/// @}
-
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c
deleted file mode 100644
index b51d13214..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dbg.c
+++ /dev/null
@@ -1,53 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_dbg.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE DBG FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_DBG_C
-
-// Files includes
-#include "types.h"
-#include "hal_dbg.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup DBG_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup DBG_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified DBG peripheral.
-/// @param  periph: DBG peripheral.
-/// @param  state: new state of the specified DBG peripheral.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DBGMCU_Configure(u32 periph, FunctionalState state)
-{
-    (state) ? (DBGMCU->CR |= periph) : (DBGMCU->CR &= ~periph);
-}
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c
deleted file mode 100644
index 5ec0dc95a..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_dma.c
+++ /dev/null
@@ -1,319 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_dma.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE DMA FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-
-
-
-
-
-// Define to prevent recursive inclusion
-#define _HAL_DMA_C_
-
-// Files includes
-#include "types.h"
-#include "hal_dma.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup DMA_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup DMA_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the DMA Channeln registers to their default reset
-///         values.
-/// @param   select the DMA Channel.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DMA_DeInit(DMA_Channel_TypeDef* channel)
-{
-    channel->CCR &= ~DMA_CCR_EN;
-    channel->CCR   = 0;
-    channel->CNDTR = 0;
-    channel->CPAR  = 0;
-    channel->CMAR  = 0;
-    if((*(vu32*)&channel) >= (*(vu32*)DMA2_Channel1_BASE)) {
-        DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
-    }
-    else {
-        DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the DMA Channeln according to the specified
-///         parameters in the init_struct.
-/// @param  select the DMA Channel.
-/// @param  init_struct: pointer to a DMA_InitTypeDef structure that
-///         contains the configuration information for the specified DMA
-///         Channel.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct)
-{
-    MODIFY_REG(
-        channel->CCR,
-        (DMA_CCR_DIR | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL | DMA_CCR_M2M),
-        ((u32)init_struct->DMA_DIR | (u32)init_struct->DMA_Mode | (u32)init_struct->DMA_PeripheralInc |
-         (u32)init_struct->DMA_MemoryInc | (u32)init_struct->DMA_PeripheralDataSize | (u32)init_struct->DMA_MemoryDataSize |
-         (u32)init_struct->DMA_Priority | (u32)init_struct->DMA_M2M));
-
-    MODIFY_REG(channel->CCR, DMA_CCR_ARE, init_struct->DMA_Auto_reload);
-    channel->CNDTR = init_struct->DMA_BufferSize;
-    channel->CPAR  = init_struct->DMA_PeripheralBaseAddr;
-    channel->CMAR  = init_struct->DMA_MemoryBaseAddr;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param  init_struct : pointer to a DMA_InitTypeDef structure which will
-///         be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DMA_StructInit(DMA_InitTypeDef* init_struct)
-{
-    init_struct->DMA_PeripheralBaseAddr = 0;
-    init_struct->DMA_MemoryBaseAddr     = 0;
-    init_struct->DMA_DIR                = DMA_DIR_PeripheralSRC;
-    init_struct->DMA_BufferSize         = 0;
-    init_struct->DMA_PeripheralInc      = DMA_PeripheralInc_Disable;
-    init_struct->DMA_MemoryInc          = DMA_MemoryInc_Disable;
-    init_struct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-    init_struct->DMA_MemoryDataSize     = DMA_MemoryDataSize_Byte;
-    init_struct->DMA_Mode               = DMA_Mode_Normal;
-    init_struct->DMA_Priority           = DMA_Priority_Low;
-    init_struct->DMA_M2M                = DMA_M2M_Disable;
-
-    init_struct->DMA_Auto_reload         = DMA_Auto_Reload_Disable;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified DMA Channeln.
-/// @param  channel: select the DMA Channel.
-/// @param  state: new state of the DMA Channeln.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state)
-{
-    MODIFY_REG(channel->CCR, DMA_CCR_EN, state << DMA_CCR_EN_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified DMA Channeln interrupts.
-/// @param  channel: select the DMA Channel.
-/// @param  it: specifies the DMA interrupts sources to be enabled
-///         or disabled.
-///         This parameter can be any combination of the following values:
-///    @arg DMA_IT_TC:  Transfer complete interrupt mask
-///    @arg DMA_IT_HT:  Half transfer interrupt mask
-///    @arg DMA_IT_TE:  Transfer error interrupt mask
-/// @param  state: new state of the specified DMA interrupts.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state)
-{
-    (state) ? (channel->CCR |= it) : (channel->CCR &= ~it);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the number of data units in the select the DMA Channel .
-/// @param  channel: select the DMA Channel
-/// @param  DataNumber: The number of data units in the current DMAy Channelx
-///         transfer.
-/// @note   This function can only be used when the DMAy_Channelx is disabled.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length)
-{
-    channel->CNDTR = length;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the number of remaining data units in the current
-///         DMA Channeln transfer.
-/// @param  channel: select the DMA Channel.
-/// @retval The number of remaining data units in the current DMA Channeln
-///         transfer.
-////////////////////////////////////////////////////////////////////////////////
-u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel)
-{
-    return channel->CNDTR;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified DMA Channeln flag is set or not.
-/// @param  flag: specifies the flag to check.
-///         This parameter can be one of the following values:
-///    @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
-///    @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
-///    @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
-///    @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
-///    @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
-///    @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
-///    @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
-///    @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
-/// @retval The new state of DMAy_FLAG (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag)
-{
-    if(flag >= DMA2_FLAG_GL1 ) {
-        return (DMA2->ISR & flag) ? SET : RESET;
-    }
-    return (DMA1->ISR & flag) ? SET : RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the DMA Channeln's pending flags.
-/// @param  flag: specifies the flag to clear.
-///         This parameter can be any combination (for the same DMA) of the
-///         following values:
-///    @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
-///    @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
-///    @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
-///    @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
-///    @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
-///    @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
-///    @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
-///    @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DMA_ClearFlag(DMA_Flags_TypeDef flag)
-{
-    if(flag >= DMA2_FLAG_GL1 ) {
-        DMA2->IFCR = flag;
-        return ;
-    }
-    DMA1->IFCR = flag;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified DMA Channeln interrupt has occurred or
-/// not.
-/// @param  it: specifies the DMA interrupt source to check.
-///         This parameter can be one of the following values:
-///    @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
-///    @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
-///    @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
-///    @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
-///    @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
-///    @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
-///    @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
-///    @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
-/// @retval  The new state of DMAy_IT (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it)
-{
-    if(it >= DMA2_IT_GL1 ) {
-        return (DMA2->ISR & it) ? SET : RESET;
-    }
-    return (DMA1->ISR & it) ? SET : RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the DMA Channeln's interrupt pending bits.
-/// @param  it: specifies the DMA interrupt pending bit to clear.
-///         This parameter can be any combination (for the same DMA) of the
-///         following values:
-///    @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
-///    @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
-///    @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
-///    @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
-///    @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
-///    @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
-///    @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
-///    @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it)
-{
-    if(it >= DMA2_IT_GL1 ) {
-        DMA2->IFCR = it;
-        return ;
-    }
-    DMA1->IFCR = it;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the DMA Channeln's Peripheral address.
-/// @param  channel : where n can be 1 to 7 for DMA1 to select the DMA Channel.
-/// @param  address : DMA Peripheral address.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 address)
-{
-    channel->CPAR = address;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the DMA Channeln's Peripheral address.
-/// @param  channel : select the DMA Channel.
-/// @param  length : Transmit lengths.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 length)
-{
-    channel->CNDTR = length;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the DMA Channeln's Peripheral address.
-/// @param  channel :select the DMA Channel.
-/// @param  address : DMA memery address.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 address)
-{
-    channel->CMAR = address;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the DMA Channeln's interrupt pending bits.
-/// @param  it: specifies the DMA interrupt pending bit to clear.
-///         This parameter can be any combination (for the same DMA) of the
-///         following values:
-///    @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
-///    @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
-///    @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
-///    @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
-///    @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
-///    @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
-///    @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
-///    @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exDMA_ClearITPendingBit(DMA_Channel_TypeDef* channel, u32 it)
-{
-    if(it >= DMA2_IT_GL1 ) {
-        DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
-        DMA2->IFCR = it;
-        return ;
-    }
-    DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
-    DMA1->IFCR = it;
-}
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c
deleted file mode 100644
index ca662e978..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_eth.c
+++ /dev/null
@@ -1,836 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_eth.c
-/// @author   AE TEM
-/// @brief    THIS FILE PROVIDES ALL THE HAL_eth.c EXAMPLE.
-/// ////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT  MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-#define _HAL_ETH_C_
-#include "hal_rcc.h"
-#include "hal_eth.h"
-#include "reg_eth.h"
-
-
-void ETH_DeInit(void)
-{
-    RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, ENABLE);
-    RCC_AHBPeriphResetCmd(RCC_AHBENR_ETHMAC, DISABLE);
-}
-
-void ETH_StructInit(ETH_InitTypeDef* ptr)
-{
-    ptr->ETH_AutoNegotiation         = ETH_AutoNegotiation_Enable;              ///< PHY Auto-negotiation enabled
-    ptr->ETH_Watchdog                = ETH_Watchdog_Enable;                     ///< MAC watchdog enabled: cuts off long frame
-    ptr->ETH_Jabber                  = ETH_Jabber_Enable;                       ///< MAC Jabber enabled in Half-duplex mode
-    ptr->ETH_InterFrameGap           = ETH_InterFrameGap_96Bit;                 ///< Ethernet interframe gap set to 96 bits
-    ptr->ETH_CarrierSense            = ETH_CarrierSense_Enable;                 ///< Carrier Sense Enabled in Half-Duplex mode
-    ptr->ETH_Speed                   = ETH_Speed_100M;                          ///< PHY speed configured to 100Mbit/s
-    ptr->ETH_ReceiveOwn              = ETH_ReceiveOwn_Enable;                   ///< Receive own Frames in Half-Duplex mode enabled
-    ptr->ETH_LoopbackMode            = ETH_LoopbackMode_Disable;                ///< MAC MII loopback disabled
-    ptr->ETH_Mode                    = ETH_Mode_FullDuplex;                     ///< Full-Duplex mode selected
-    ptr->ETH_ChecksumOffload         = ETH_ChecksumOffload_Disable;             ///< IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled
-    ptr->ETH_RetryTransmission       = ETH_RetryTransmission_Enable;            ///< Retry Transmission enabled for half-duplex mode
-    ptr->ETH_AutomaticPadCRCStrip    = ETH_AutomaticPadCRCStrip_Disable;        ///< Automatic PAD/CRC strip disable
-    ptr->ETH_BackOffLimit            = ETH_BackOffLimit_10;                     ///< half-duplex mode retransmission Backoff time_limit = 10 slot time
-    ptr->ETH_DeferralCheck           = ETH_DeferralCheck_Disable;               ///< half-duplex mode Deferral check disabled
-    ptr->ETH_ReceiveAll              = ETH_ReceiveAll_Disable;                  ///< Receive all frames disabled
-    ptr->ETH_SourceAddrFilter        = ETH_SourceAddrFilter_Disable;            ///< Source address filtering (on the optional MAC addresses) disabled
-    ptr->ETH_PassControlFrames       = ETH_PassControlFrames_BlockAll;          ///< Do not forward control frames that do not pass the address filtering
-    ptr->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;   ///< Disable reception of Broadcast frames
-    ptr->ETH_DestinationAddrFilter   = ETH_DestinationAddrFilter_Normal;        ///< Normal Destination address filtering (not reverse addressing)
-    ptr->ETH_PromiscuousMode         = ETH_PromiscuousMode_Disable;             ///< Promiscuous address filtering mode disabled
-    ptr->ETH_MulticastFramesFilter   = ETH_MulticastFramesFilter_Perfect;       ///< Perfect address filtering for multicast addresses
-    ptr->ETH_UnicastFramesFilter     = ETH_UnicastFramesFilter_Perfect;         ///< Perfect address filtering for unicast addresses
-    ptr->ETH_HashTableHigh           = 0x0;                                     ///< Initialize hash table high and low regs
-    ptr->ETH_HashTableLow            = 0x0;
-    ptr->ETH_PauseTime               = 0x0;                                     ///< Flow control config (flow control disabled)
-    ptr->ETH_ZeroQuantaPause         = ETH_ZeroQuantaPause_Enable;
-    ptr->ETH_PauseLowThreshold       = ETH_PauseLowThreshold_Minus4;
-    ptr->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
-    ptr->ETH_ReceiveFlowControl      = ETH_ReceiveFlowControl_Disable;
-    ptr->ETH_TransmitFlowControl     = ETH_TransmitFlowControl_Disable;
-    ptr->ETH_VLANTagComparison       = ETH_VLANTagComparison_16Bit;             ///< VLANtag config (VLAN field not checked)
-    ptr->ETH_VLANTagIdentifier       = 0x0;
-
-    ptr->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; ///< Drops frames with with TCP/IP checksum errors
-    ptr->ETH_ReceiveStoreForward     = ETH_ReceiveStoreForward_Enable;          ///< Store and forward mode enabled for receive
-    ptr->ETH_FlushReceivedFrame      = ETH_FlushReceivedFrame_Enable;           ///< Flush received frame that created FIFO overflow
-    ptr->ETH_TransmitStoreForward    = ETH_TransmitStoreForward_Enable;         ///< Store and forward mode enabled for transmit
-    ptr->ETH_TransmitThresholdControl = ETH_ReceiveThresholdControl_64Bytes;    ///< Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled)
-    ptr->ETH_ForwardErrorFrames      = ETH_ForwardErrorFrames_Disable;          ///< Disable forwarding frames with errors (short frames, CRC,...)
-    ptr->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; ///< Disable undersized good frames
-    ptr->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;     ///< Threshold RXFIFO level set to 64 bytes (used when Cut through mode is enabled)
-    ptr->ETH_SecondFrameOperate      = ETH_SecondFrameOperate_Disable;          ///< Disable Operate on second frame (transmit a second frame to FIFO without waiting status of previous frame
-    ptr->ETH_AddressAlignedBeats     = ETH_AddressAlignedBeats_Enable;          ///< DMA works on 32-bit aligned start source and destinations addresses
-    ptr->ETH_FixedBurst              = ETH_FixedBurst_Enable;                   ///< Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions
-    ptr->ETH_RxDMABurstLength        = ETH_RxDMABurstLength_32Beat;             ///< DMA transfer max burst length = 32 beats = 32 x 32bits
-    ptr->ETH_TxDMABurstLength        = ETH_TxDMABurstLength_32Beat;
-    ptr->ETH_DescriptorSkipLength    = 0x0;                                     ///< DMA Ring mode skip length = 0
-    ptr->ETH_DMAArbitration          = ETH_DMAArbitration_RoundRobin_RxTx_1_1;  ///< Equal priority (round-robin) between transmit and receive DMA engines
-}
-
-u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr)
-{
-    u32 hclk = RCC_GetHCLKFreq();
-    u32 reg = ETH->MACMIIAR & MACMIIAR_CR_MASK;
-    u32 temp_val = 0;
-    hclk = 100000000;
-    ////////////////////////////////////////////////////////////////////////////
-    if (hclk >= 20000000 && hclk < 35000000) {
-        reg |= ETH_MACMIIAR_CR_Div16;                                           ///< HCLK 20 ~ 35 MHz, /16
-    }
-    else if (hclk >= 35000000 && hclk < 60000000) {
-        reg |= ETH_MACMIIAR_CR_Div26;                                           ///< HCLK 35 ~ 60 MHz, /26
-    }
-    else if (hclk >= 60000000 && hclk < 100000000) {
-        reg |= ETH_MACMIIAR_CR_Div42;                                           ///< HCLK 60 ~ 100 MHz, /42
-    }
-    else if (hclk >= 100000000 && hclk < 150000000) {
-        reg |= ETH_MACMIIAR_CR_Div62;                                           ///< HCLK 100 ~ 150 MHz, /62
-    }
-    else {
-        reg |= ETH_MACMIIAR_CR_Div102;                                          ///< HCLK 150 ~ 168 MHz, /102
-    }
-
-    ETH->MACMIIAR = reg;
-
-    ////////////////////////////////////////////////////////////////////////////
-    ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_Reset);
-    if (ptr->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable) {
-        // Wait for linked status
-        while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_Linked_Status));
-        ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AutoNegotiation);
-        // Enable Auto-Negitation
-        while (!(ETH_ReadPHYRegister(phy_addr, PHY_BSR) & PHY_AutoNego_Complete)) {
-
-        }
-        // Read the result of the Auto-Negitation
-        temp_val = ETH_ReadPHYRegister(phy_addr, 31);
-
-        if ((temp_val & 0x1C) == 0x4) {
-            ptr->ETH_Speed = ETH_Speed_10M;
-            ptr->ETH_Mode = ETH_Mode_HalfDuplex;
-            SYSCFG->CFGR2 &= ~(1 << 21);
-        }
-        else if((temp_val & 0x1C) == 0x14) {
-            ptr->ETH_Speed = ETH_Speed_10M;
-            ptr->ETH_Mode = ETH_Mode_FullDuplex;
-            SYSCFG->CFGR2 |= 1 << 21;
-        }
-        else if((temp_val & 0x1C) == 0x8) {
-            ptr->ETH_Speed = ETH_Speed_100M;
-            ptr->ETH_Mode = ETH_Mode_HalfDuplex;
-            SYSCFG->CFGR2 &= ~(1 << 21);
-        }
-        else if((temp_val & 0x1C) == 0x18) {
-            ptr->ETH_Speed = ETH_Speed_100M;
-            ptr->ETH_Mode = ETH_Mode_FullDuplex;
-            SYSCFG->CFGR2 |= 1 << 21;
-        }
-    }
-    else {
-        ETH_WritePHYRegister(phy_addr, PHY_BCR, ((u16)(ptr->ETH_Mode >> 3) |
-                             (u16)(ptr->ETH_Speed >> 1)));
-        if(ptr->ETH_Speed == ETH_Speed_10M) {
-            SYSCFG->CFGR2 &= ~(1 << 21);
-        }
-        else {
-            SYSCFG->CFGR2 |= 1 << 21;
-        }
-    }
-
-    ////////////////////////////////////////////////////////////////////////////
-    ETH->MACCR = ETH->MACCR & MACCR_CLEAR_MASK |   (ptr->ETH_Watchdog |
-                 ptr->ETH_Jabber |
-                 ptr->ETH_InterFrameGap |
-                 ptr->ETH_CarrierSense |
-                 ptr->ETH_Speed |
-                 ptr->ETH_ReceiveOwn |
-                 ptr->ETH_LoopbackMode |
-                 ptr->ETH_Mode |
-                 ptr->ETH_ChecksumOffload |
-                 ptr->ETH_RetryTransmission |
-                 ptr->ETH_AutomaticPadCRCStrip |
-                 ptr->ETH_DeferralCheck);
-
-    ETH->MACFFR =   ptr->ETH_ReceiveAll |
-                    ptr->ETH_SourceAddrFilter |
-                    ptr->ETH_PassControlFrames |
-                    ptr->ETH_BroadcastFramesReception |
-                    ptr->ETH_DestinationAddrFilter |
-                    ptr->ETH_PromiscuousMode |
-                    ptr->ETH_MulticastFramesFilter |
-                    ptr->ETH_UnicastFramesFilter;
-
-    ETH->MACHTHR = ptr->ETH_HashTableHigh;
-    ETH->MACHTLR = ptr->ETH_HashTableLow;
-
-    ETH->MACFCR = ETH->MACFCR & MACFCR_CLEAR_MASK | ((ptr->ETH_PauseTime << ETH_MACFCR_PT_Pos) |
-                  ptr->ETH_ZeroQuantaPause |
-                  ptr->ETH_PauseLowThreshold |
-                  ptr->ETH_UnicastPauseFrameDetect |
-                  ptr->ETH_ReceiveFlowControl |
-                  ptr->ETH_TransmitFlowControl);
-
-    ETH->MACVLANTR = ptr->ETH_VLANTagComparison | ptr->ETH_VLANTagIdentifier;
-
-    ETH->DMAOMR = 0x00200004;
-    ETH->DMAIER = 0x0001A040;
-    ETH->DMABMR = ( ptr->ETH_AddressAlignedBeats |
-                    ptr->ETH_FixedBurst |
-                    ptr->ETH_RxDMABurstLength |                                 // !! if 4xPBL is selected for Tx or Rx it is applied for the other
-                    ptr->ETH_TxDMABurstLength |
-                    ptr->ETH_DescriptorSkipLength << 2 |
-                    ptr->ETH_DMAArbitration);// |
-//                    ETH_DMABMR_USP);                                            // Enable use of separate PBL for Rx and Tx
-
-    return ETH_SUCCESS;
-}
-
-void ETH_Start(void)
-{
-    ETH_MACTransmissionCmd(ENABLE);
-    ETH_MACReceptionCmd(ENABLE);
-    ETH_FlushTransmitFIFO();
-    ETH_DMATransmissionCmd(ENABLE);
-    ETH_DMAReceptionCmd(ENABLE);
-}
-
-void ETH_Stop(void)
-{
-    ETH_DMATransmissionCmd(DISABLE);
-    ETH_DMAReceptionCmd(DISABLE);
-    ETH_MACReceptionCmd(DISABLE);
-    ETH_FlushTransmitFIFO();
-    ETH_MACTransmissionCmd(DISABLE);
-}
-
-void ETH_MACTransmissionCmd(FunctionalState sta)
-{
-    sta ? (ETH->MACCR |= ETH_MACCR_TE) : (ETH->MACCR &= ~ETH_MACCR_TE);
-}
-
-void ETH_MACReceptionCmd(FunctionalState sta)
-{
-    sta ? (ETH->MACCR |= ETH_MACCR_RE) : (ETH->MACCR &= ~ETH_MACCR_RE);
-}
-
-FlagStatus ETH_GetFlowControlBusyStatus(void)
-{
-    return (FlagStatus)(ETH->MACFCR & ETH_MACFCR_FCBBPA);
-}
-
-void ETH_InitiatePauseControlFrame(void)
-{
-    ETH->MACFCR |= ETH_MACFCR_FCBBPA;
-}
-
-void ETH_BackPressureActivationCmd(FunctionalState sta)
-{
-    sta ? (ETH->MACFCR |= ETH_MACFCR_FCBBPA) : (ETH->MACFCR &= ~ETH_MACFCR_FCBBPA);
-}
-
-void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr)
-{
-    *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) =
-        (u32)mac_addr[5] << 8 |
-        (u32)mac_addr[4];
-
-    *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) =
-        (u32)mac_addr[3] << 24 |
-        (u32)mac_addr[2] << 16 |
-        (u32)mac_addr[1] << 8 |
-        (u32)mac_addr[0];
-}
-
-void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr)
-{
-    mac_addr[5] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) >> 8 & 0xFF;
-    mac_addr[4] = *(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr) & 0xFF;
-    mac_addr[3] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 24 & 0xFF;
-    mac_addr[2] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 16 & 0xFF;
-    mac_addr[1] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) >> 8 & 0xFF;
-    mac_addr[0] = *(__IO u32*)(ETH_MAC_ADDR_LBASE + reg_addr) & 0xFF;
-}
-
-void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta)
-{
-    sta ?   ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_AE) :
-    ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_AE);
-}
-
-void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta)
-{
-    sta ?   ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA) :
-    ((*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= ETH_MACA1HR_SA);
-}
-
-void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte)
-{
-    (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) &= ~ETH_MACA1HR_MBC;
-
-    (*(__IO u32*)(ETH_MAC_ADDR_HBASE + reg_addr)) |= mask_byte;
-}
-
-FrameTypeDef ETH_Get_Received_Frame(void)
-{
-    FrameTypeDef frame;
-
-    frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4;
-    frame.buf = (DMA_RX_FRAME_infos->ptrFS_Rx_Desc)->BUF1ADDR;
-    frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc;
-
-
-    DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
-
-    return frame;
-}
-
-FrameTypeDef ETH_Get_Received_Frame_interrupt(void)
-{
-    FrameTypeDef frame = {0};
-    __IO u32 desc_cnt = 0;
-
-    while(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) && desc_cnt < ETH_RX_BUF_NUM) {
-        desc_cnt++;
-
-        if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) &&
-                !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
-            DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
-            DMA_RX_FRAME_infos->cnt = 1;
-            DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
-
-        }
-        else if ( (DMARxDescToGet->CS & ETH_DMA_RDES_FS) &&
-                  (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
-            DMA_RX_FRAME_infos->cnt++;
-            DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
-        }
-        else {
-            DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet;
-            DMA_RX_FRAME_infos->cnt++;
-
-            if (DMA_RX_FRAME_infos->cnt == 1)
-                DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
-
-            frame.len = ((DMARxDescToGet->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FL_Pos) - 4;
-
-            frame.buf = (DMA_RX_FRAME_infos->cnt > 1) ?
-                        (DMA_RX_FRAME_infos->ptrFS_Rx_Desc->BUF1ADDR) :
-                        (DMARxDescToGet->BUF1ADDR);
-
-            frame.ptrDesc = DMA_RX_FRAME_infos->ptrFS_Rx_Desc;
-
-            DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
-
-            return frame;
-        }
-    }
-
-    return frame;
-}
-
-u32 ETH_Prepare_Transmit_Descriptors(u16 len)
-{
-    u32 cnt = 0, i = 0;
-    __IO ETH_DMADESCTypeDef* temp_desc = DMATxDescToSet;
-
-    if (DMATxDescToSet->CS & ETH_DMA_TDES_OWN)
-        return ETH_ERROR;
-
-    if(len > ETH_TX_BUF_SIZE) {
-        cnt = len / ETH_TX_BUF_SIZE;
-
-        if (len % ETH_TX_BUF_SIZE)
-            cnt++;
-    }
-    else {
-        cnt = 1;
-    }
-
-    if (cnt == 1) {
-        temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS | ETH_DMA_TDES_TBS1);
-
-        temp_desc->BL |=    ETH_DMA_TDES_FS |
-                            ETH_DMA_TDES_LS |
-                            (len & ETH_DMA_TDES_TBS1);
-
-        temp_desc->CS |= ETH_DMA_TDES_OWN;
-        temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR);
-    }
-    else {
-        for (i = 0; i < cnt; i++) {
-            temp_desc->BL &= ~(ETH_DMA_TDES_FS | ETH_DMA_TDES_LS);
-
-            if (i == 0)
-                temp_desc->BL |= ETH_DMA_TDES_FS;
-
-            temp_desc->BL = ETH_TX_BUF_SIZE & ETH_DMA_TDES_TBS1;
-
-            if (i == (cnt - 1)) {
-                temp_desc->BL &= ~ETH_DMA_TDES_TBS1;
-                temp_desc->BL |=    ETH_DMA_TDES_LS |
-                                    ((len - (cnt - 1) * ETH_TX_BUF_SIZE) & ETH_DMA_TDES_TBS1);
-            }
-
-            temp_desc->CS |= ETH_DMA_TDES_OWN;
-            temp_desc = (ETH_DMADESCTypeDef*)(temp_desc->BUF2NDADDR);
-        }
-    }
-
-    DMATxDescToSet = temp_desc;
-
-    if (ETH->DMASR & ETH_DMASR_TBUS) {
-        ETH->DMASR = ETH_DMASR_TBUS;
-        ETH->DMATPDR = 0;
-    }
-
-    return ETH_SUCCESS;
-}
-
-void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt)
-{
-    u32 i = 0;
-    ETH_DMADESCTypeDef* temp_desc;
-
-    DMARxDescToGet = ptr_desc;
-
-    for (i = 0; i < cnt; i++) {
-        temp_desc = ptr_desc + i;
-        temp_desc->CS = ETH_DMA_RDES_OWN;
-        temp_desc->BL = ETH_DMA_RDES_RCH | ETH_RX_BUF_SIZE;
-        temp_desc->BUF1ADDR = (u32)&buf[i * ETH_RX_BUF_SIZE];
-
-        if (i < cnt - 1) {
-            temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1);
-        }
-        else {
-            temp_desc->BUF2NDADDR = (u32)(ptr_desc);
-        }
-    }
-
-    ETH->DMARDLAR = (u32)ptr_desc;
-
-    DMA_RX_FRAME_infos = &RX_Frame_Descriptor;
-}
-
-u32 ETH_CheckFrameReceived(void)
-{
-    if(!(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
-            (DMARxDescToGet->CS & ETH_DMA_RDES_LS)) {
-
-        DMA_RX_FRAME_infos->cnt++;
-
-        if (DMA_RX_FRAME_infos->cnt == 1) {
-            DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
-        }
-        DMA_RX_FRAME_infos->ptrLS_Rx_Desc = DMARxDescToGet;
-        return 1;
-    }
-    else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
-              !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)  &&
-              (DMARxDescToGet->CS & ETH_DMA_RDES_FS)) {
-        DMA_RX_FRAME_infos->ptrFS_Rx_Desc = DMARxDescToGet;
-        DMA_RX_FRAME_infos->ptrLS_Rx_Desc = (void*)0;
-        DMA_RX_FRAME_infos->cnt = 1;
-    }
-    else if ( !(DMARxDescToGet->CS & ETH_DMA_RDES_OWN) &&
-              !(DMARxDescToGet->CS & ETH_DMA_RDES_LS)  &&
-              !(DMARxDescToGet->CS & ETH_DMA_RDES_FS)) {
-        DMA_RX_FRAME_infos->cnt++;
-        DMARxDescToGet = (ETH_DMADESCTypeDef*)(DMARxDescToGet->BUF2NDADDR);
-    }
-
-    return 0;
-}
-
-void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt)
-{
-    u32 i = 0;
-    ETH_DMADESCTypeDef* temp_desc;
-
-    DMATxDescToSet = ptr_desc;
-
-    for (i = 0; i < cnt; i++) {
-        temp_desc = ptr_desc + i;
-        temp_desc->BL = ETH_DMA_TDES_TCH;
-        temp_desc->BUF1ADDR = (u32)(&buf[i * ETH_TX_BUF_SIZE]);
-
-        if (i < cnt - 1) {
-            temp_desc->BUF2NDADDR = (u32)(ptr_desc + i + 1);
-        }
-        else {
-            temp_desc->BUF2NDADDR = (u32)(ptr_desc);
-        }
-    }
-
-    ETH->DMATDLAR = (u32)ptr_desc;
-}
-
-FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag)
-{
-    return (FlagStatus)(ptr_desc->CS & flag);
-}
-
-u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc)
-{
-    return (ptr_desc->CS & ETH_DMA_TDES_CC) >> ETH_DMA_TDES_COLLISION_COUNTSHIFT;
-}
-
-void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc)
-{
-    ptr_desc->CS |= ETH_DMA_TDES_OWN;
-}
-
-void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
-{
-    sta ? (ptr_desc->BL |= ETH_DMA_TDES_IC) : (ptr_desc->BL &= ~ETH_DMA_TDES_IC);
-}
-
-void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val)
-{
-    ptr_desc->CS |= val;
-}
-
-void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val)
-{
-    ptr_desc->CS |= val;
-}
-
-void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
-{
-    sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DC) : (ptr_desc->BL |= ETH_DMA_TDES_DC);
-}
-
-void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
-{
-    sta ? (ptr_desc->BL |= ETH_DMA_TDES_TCH) : (ptr_desc->BL &= ~ETH_DMA_TDES_TCH);
-}
-
-void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
-{
-    sta ? (ptr_desc->BL &= ~ETH_DMA_TDES_DP) : (ptr_desc->BL |= ETH_DMA_TDES_DP);
-}
-
-void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size)
-{
-    ptr_desc->BL |= buf1_size | (buf2_size << ETH_DMA_TDES_BUFFER2_SIZESHIFT);
-}
-
-FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag)
-{
-    return (FlagStatus)(ptr_desc->CS & flag);
-}
-
-void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc)
-{
-    ptr_desc->CS |= ETH_DMA_RDES_OWN;
-}
-
-u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc)
-{
-    return (ptr_desc->CS & ETH_DMA_RDES_FL) >> ETH_DMA_RDES_FRAME_LENGTHSHIFT;
-}
-
-void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta)
-{
-    sta ? (ptr_desc->CS &= ~ETH_DMA_RDES_DIC) : (ptr_desc->CS |= ETH_DMA_RDES_DIC);
-}
-
-u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf)
-{
-    return (buf != ETH_DMA_RDES_Buffer1 ?
-            ((ptr_desc->BL & ETH_DMA_RDES_RBS2) >> ETH_DMA_RDES_BUFFER2_SIZESHIFT) :
-            (ptr_desc->BL & ETH_DMA_RDES_RBS1));
-}
-
-u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc)
-{
-    u32 len = 0;
-
-    if (    !(ptr_desc->CS & ETH_DMA_RDES_OWN) &&
-            !(ptr_desc->CS & ETH_DMA_RDES_ES) &&
-            (ptr_desc->CS & ETH_DMA_RDES_LS)) {
-        len = ETH_GetDMARxDescFrameLength(ptr_desc);
-    }
-
-    return len;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-void ETH_SoftwareReset(void)
-{
-    ETH->DMABMR |= ETH_DMABMR_SR;
-}
-
-FlagStatus ETH_GetSoftwareResetStatus(void)
-{
-    return (FlagStatus)(ETH->DMABMR & ETH_DMABMR_SR);
-}
-
-FlagStatus ETH_GetDMAFlagStatus(u32 flag)
-{
-    return (FlagStatus)(ETH->DMASR & flag);
-}
-
-void ETH_DMAClearFlag(u32 flag)
-{
-    ETH->DMASR = flag;
-}
-
-void ETH_DMAITConfig(u32 it, FunctionalState sta)
-{
-    sta ? (ETH->DMAIER |= it) : (ETH->DMAIER &= ~it);
-}
-
-ITStatus ETH_GetDMAITStatus(u32 it)
-{
-    return (ITStatus)(ETH->DMASR & it);
-}
-
-void ETH_DMAClearITPendingBit(u32 it)
-{
-    ETH->DMASR = it;
-}
-
-u32 ETH_GetTransmitProcessState(void)
-{
-    return ETH->DMASR & ETH_DMASR_TS;
-}
-
-u32 ETH_GetReceiveProcessState(void)
-{
-    return ETH->DMASR & ETH_DMASR_RS;
-}
-
-void ETH_FlushTransmitFIFO(void)
-{
-    ETH->DMAOMR |= ETH_DMAOMR_FTF;
-}
-
-FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
-{
-    return (FlagStatus)(ETH->DMAOMR & ETH_DMAOMR_FTF);
-}
-
-void ETH_DMATransmissionCmd(FunctionalState sta)
-{
-    sta ? (ETH->DMAOMR |= ETH_DMAOMR_ST) : (ETH->DMAOMR &= ~ETH_DMAOMR_ST);
-}
-
-void ETH_DMAReceptionCmd(FunctionalState sta)
-{
-    sta ? (ETH->DMAOMR |= ETH_DMAOMR_SR) : (ETH->DMAOMR &= ~ETH_DMAOMR_SR);
-}
-
-FlagStatus ETH_GetDMAOverflowStatus(u32 val)
-{
-    return (FlagStatus)(ETH->DMAMFBOCR & val);
-}
-
-u32 ETH_GetRxOverflowMissedFrameCounter(void)
-{
-    return (ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >>
-           ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT;
-}
-
-u32 ETH_GetBufferUnavailableMissedFrameCounter(void)
-{
-    return ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFC;
-}
-
-u32 ETH_GetCurrentTxDescStartAddress(void)
-{
-    return ETH->DMACHTDR;
-}
-
-u32 ETH_GetCurrentRxDescStartAddress(void)
-{
-    return ETH->DMACHRDR;
-}
-
-u32 ETH_GetCurrentTxBufferAddress(void)
-{
-    return ETH->DMACHTBAR;
-}
-
-u32 ETH_GetCurrentRxBufferAddress(void)
-{
-    return ETH->DMACHRBAR;
-}
-
-void ETH_ResumeDMATransmission(void)
-{
-    ETH->DMATPDR = 0;
-}
-
-void ETH_ResumeDMAReception(void)
-{
-    ETH->DMARPDR = 0;
-}
-
-void ETH_SetReceiveWatchdogTimer(u8 val)
-{
-    ETH->DMARSWTR = val;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-u16 ETH_ReadPHYRegister(u16 addr, u16 reg)
-{
-    u32 dat;
-    // Set phy address and reg address, clear write flag
-    ETH->MACMIIAR = (((ETH->MACMIIAR & ~MACMIIAR_CR_MASK) |
-                      (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) |
-                      (reg  << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR)) &
-                     (~ETH_MACMIIAR_MW)) | ETH_MACMIIAR_MB;
-
-    // Check busy flag
-    while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
-    dat = (u16)ETH->MACMIIDR;
-    if(dat == 0xFFFF) {
-        dat = 0;
-    }
-    return dat;
-}
-
-u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val)
-{
-    // Load data
-    ETH->MACMIIDR = val;
-
-    // Set phy address, reg address and write flag
-    ETH->MACMIIAR = (ETH->MACMIIAR & ~MACMIIAR_CR_MASK) |
-                    (addr << ETH_MACMIIAR_PA_Pos & ETH_MACMIIAR_PA) |
-                    (reg  << ETH_MACMIIAR_MR_Pos & ETH_MACMIIAR_MR) |
-                    ETH_MACMIIAR_MW |
-                    ETH_MACMIIAR_MB;
-
-    // Check busy flag
-    while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
-
-    return ETH->MACMIIDR;
-}
-
-u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta)
-{
-    u16 temp_val = ETH_ReadPHYRegister(addr, PHY_BCR);
-
-    sta ? (temp_val |= PHY_Loopback) : (temp_val &= ~PHY_Loopback);
-
-    if(ETH_WritePHYRegister(addr, PHY_BCR, temp_val))
-        return ETH_SUCCESS;
-
-    return ETH_ERROR;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-
-void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
-{
-    ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
-}
-
-void ETH_SetWakeUpFrameFilterRegister(u32* buf)
-{
-    u32 i = 0;
-
-    for (i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) {
-        ETH->MACRWUFFR = buf[i];
-    }
-}
-
-void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta)
-{
-    sta ?   (ETH->MACPMTCSR |= ETH_MACPMTCSR_GU) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU);
-}
-
-FlagStatus ETH_GetPMTFlagStatus(u32 flag)
-{
-    return (FlagStatus)(ETH->MACPMTCSR & flag);
-}
-
-void ETH_WakeUpFrameDetectionCmd(FunctionalState sta)
-{
-    sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE);
-}
-
-void ETH_MagicPacketDetectionCmd(FunctionalState sta)
-{
-    sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE);
-}
-
-void ETH_PowerDownCmd(FunctionalState sta)
-{
-    sta ? (ETH->MACPMTCSR |= ETH_MACPMTCSR_PD) : (ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-
-void ETH_MMCCounterFullPreset(void)
-{
-    ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP;
-}
-
-void ETH_MMCCounterHalfPreset(void)
-{
-    ETH->MMCCR &= ~ETH_MMCCR_MCFHP;
-
-    ETH->MMCCR |= ETH_MMCCR_MCP;
-}
-
-void ETH_MMCCounterFreezeCmd(FunctionalState sta)
-{
-    sta ? (ETH->MMCCR |= ETH_MMCCR_MCF) : (ETH->MMCCR &= ~ETH_MMCCR_MCF);
-}
-
-void ETH_MMCResetOnReadCmd(FunctionalState sta)
-{
-    sta ? (ETH->MMCCR |= ETH_MMCCR_ROR) : (ETH->MMCCR &= ~ETH_MMCCR_ROR);
-}
-
-void ETH_MMCCounterRolloverCmd(FunctionalState sta)
-{
-    sta ? (ETH->MMCCR &= ~ETH_MMCCR_CSR) : (ETH->MMCCR |= ETH_MMCCR_CSR);
-}
-
-void ETH_MMCCountersReset(void)
-{
-    ETH->MMCCR |= ETH_MMCCR_CR;
-}
-
-void ETH_MMCITConfig(u32 it, FunctionalState sta)
-{
-    if (it & 0x10000000) {
-        it &= 0xEFFFFFFF;
-
-        sta ? (ETH->MMCRIMR &= ~it) : (ETH->MMCRIMR |= it);
-    }
-    else {
-        sta ? (ETH->MMCTIMR &= ~it) : (ETH->MMCTIMR |= it);
-    }
-}
-
-ITStatus ETH_GetMMCITStatus(u32 it)
-{
-    if (it & 0x10000000) {
-        return (ITStatus)((ETH->MMCRIR & it) && !(ETH->MMCRIMR & it));
-    }
-    else {
-        return (ITStatus)((ETH->MMCTIR & it) && !(ETH->MMCTIMR & it));
-    }
-}
-
-u32 ETH_GetMMCRegister(u32 reg)
-{
-    return *(vu32*)(ETH_BASE + reg);
-}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c
deleted file mode 100644
index 409d84d80..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_exti.c
+++ /dev/null
@@ -1,222 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_exti.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE EXTI FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_EXTI_C_
-
-// Files includes
-#include "hal_exti.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup EXTI_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup EXTI_Exported_Functions
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the EXTI peripheral registers to their default reset
-///         values.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the EXTI registers to their default reset values.
-/// @param  None.
-/// @retval None.
-/// @note   MEM_MODE bits are not affected by APB reset.
-/// @note   MEM_MODE bits took the value from the user option bytes.
-/// @note   CFGR2 register is not affected by APB reset.
-/// @note   CLABBB configuration bits are locked when set.
-/// @note   To unlock the configuration, perform a system reset.
-////////////////////////////////////////////////////////////////////////////////
-void EXTI_DeInit(void)
-{
-    u16 i;
-    // Clear all
-    exEXTI_LineDisable(~0x00000000);
-
-    // rc_w1
-    EXTI->PR = EXTI->PR;
-
-    // Set EXTI_CFGR1 register to reset value without affecting MEM_MODE bits
-    EXTI->CFGR &= EXTI_CFGR_MEMMODE;
-
-    // Set EXTICRx registers to reset value
-    for (i = 0; i < 4; i++) {
-        EXTI->CR[i] = 0;
-    }
-}
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the GPIO pin used as EXTI Line.
-/// @param  port_source_gpio: selects the GPIO port to be used as source for EXTI lines .
-/// @param  pin_source: specifies the EXTI line to be configured.
-/// @note   This parameter can be pin_source where x can be:
-///         For MCU: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOD.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void EXTI_LineConfig(u8 port_source_gpio, u8 pin_source)
-{
-    EXTI->CR[pin_source >> 0x02] &= ~(0x0F << (0x04 * (pin_source & 0x03)));
-    EXTI->CR[pin_source >> 0x02] |= ((port_source_gpio) << (0x04 * (pin_source & 0x03)));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the EXTI peripheral according to the specified
-///         parameters in the init_struct.
-/// @param  init_struct: pointer to a EXTI_InitTypeDef structure that
-///         contains the configuration information for the EXTI peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void EXTI_Init(EXTI_InitTypeDef* init_struct)
-{
-    if (init_struct->EXTI_LineCmd != DISABLE) {
-        EXTI->IMR  &= ~init_struct->EXTI_Line;
-        EXTI->EMR  &= ~init_struct->EXTI_Line;
-        if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) {
-            EXTI->IMR |= init_struct->EXTI_Line;
-        }
-        else {
-            EXTI->EMR |= init_struct->EXTI_Line;
-        }
-        EXTI->RTSR &= ~init_struct->EXTI_Line;
-        EXTI->FTSR &= ~init_struct->EXTI_Line;
-        if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) {
-            EXTI->RTSR |= init_struct->EXTI_Line;
-            EXTI->FTSR |= init_struct->EXTI_Line;                               // Rising and Faling    afio
-        }
-        else if (init_struct->EXTI_Trigger == EXTI_Trigger_Rising) {
-            EXTI->RTSR |= init_struct->EXTI_Line;
-        }
-        else {
-            EXTI->FTSR |= init_struct->EXTI_Line;
-        }
-    }
-    else {
-        if (init_struct->EXTI_Mode == EXTI_Mode_Interrupt) {
-            EXTI->IMR &= ~init_struct->EXTI_Line;
-        }
-        else {
-            EXTI->EMR &= ~init_struct->EXTI_Line;
-        }
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its reset value.
-/// @param  init_struct: pointer to a EXTI_InitTypeDef structure which will
-///         be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void EXTI_StructInit(EXTI_InitTypeDef* init_struct)
-{
-    init_struct->EXTI_Line    = EXTI_LineNone;
-    init_struct->EXTI_Mode    = EXTI_Mode_Interrupt;
-    init_struct->EXTI_Trigger = EXTI_Trigger_Falling;
-    init_struct->EXTI_LineCmd = DISABLE;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Generates a Software interrupt on selected EXTI line.
-/// @param  line: specifies the EXTI line on which the software interrupt
-///         will be generated.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void EXTI_GenerateSWInterrupt(u32 line)
-{
-    EXTI->SWIER |= line;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified EXTI line flag is set or not.
-/// @param  line: specifies the EXTI line flag to check.
-/// @retval The new state of line (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus EXTI_GetFlagStatus(u32 line)
-{
-    return (EXTI->PR & line) ? SET : RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the EXTI's line pending flags.
-/// @param  line: specifies the EXTI lines flags to clear.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void EXTI_ClearFlag(u32 line)
-{
-    EXTI->PR = line;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified EXTI line is asserted or not.
-/// @param  line: specifies the EXTI line to check.
-/// @retval The new state of line (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus EXTI_GetITStatus(u32 line)
-{
-    return ((EXTI->PR & line) && (EXTI->IMR & line)) ? SET : RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the EXTI's line pending bits.
-/// @param  line: specifies the EXTI lines to clear.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void EXTI_ClearITPendingBit(u32 line)
-{
-    EXTI->PR = line;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  EXTI Line Disable
-/// @param  line: specifies the EXTI lines to clear.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exEXTI_LineDisable(u32 line)
-{
-    EXTI->IMR  &= ~line;
-    EXTI->EMR  &= ~line;
-    EXTI->RTSR &= ~line;
-    EXTI->FTSR &= ~line;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the EXTI's line all pending bits.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-u32 exEXTI_GetAllFlagStatus(void)
-{
-    return EXTI->PR;
-}
-
-/// @}
-
-/// @}
-
-/// @}
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c
deleted file mode 100644
index ecdc8be3a..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_flash.c
+++ /dev/null
@@ -1,548 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_flash.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE FLASH FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_FLASH_C_
-
-// Files includes
-#include "hal_flash.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup FLASH_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup FLASH_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the code latency value.
-/// @note   This function can be used for all MM32 devices.
-/// @param  latency: specifies the FLASH Latency value.
-///         This parameter can be one of the following values:
-/// @arg    FLASH_Latency_0: FLASH Zero Latency cycle
-/// @arg    FLASH_Latency_1: FLASH One Latency cycle
-/// @arg    FLASH_Latency_2: FLASH Two Latency cycles
-/// @arg    FLASH_Latency_3: FLASH Three Latency cycles
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void FLASH_SetLatency(FLASH_Latency_TypeDef latency)
-{
-    FLASH->ACR = (FLASH->ACR & (~FLASH_ACR_LATENCY)) | latency;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the Half cycle flash access.
-/// @note   This function can be used for all MM32 devices.
-/// @param  half_cycle_access: specifies the FLASH Half cycle Access mode.
-///         This parameter can be one of the following values:
-/// @arg    FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
-/// @arg    FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void FLASH_HalfCycleAccessCmd(FLASH_HalfCycleAccess_TypeDef half_cycle_access)
-{
-    FLASH->ACR &= ~FLASH_ACR_HLFCYA;
-    FLASH->ACR |= half_cycle_access;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the Prefetch Buffer.
-/// @note   This function can be used for all MM32 devices.
-/// @param  prefetch_buffer: specifies the Prefetch buffer status.
-///         This parameter can be one of the following values:
-/// @arg    FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
-/// @arg    FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_TypeDef prefetch_buffer)
-{
-    FLASH->ACR &= ~FLASH_ACR_PRFTBE;
-    FLASH->ACR |= prefetch_buffer;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Locks the FLASH Program Erase Controller.
-/// @note   This function can be used for all MM32 devices.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void FLASH_Lock(void)
-{
-    FLASH->CR |= FLASH_CR_LOCK;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Unlocks the FLASH Program Erase Controller.
-/// @note   This function can be used for all MM32 devices.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void FLASH_Unlock()
-{
-    FLASH->KEYR = FLASH_KEY1;
-    FLASH->KEYR = FLASH_KEY2;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enable to program the FLASH Option Byte.
-/// @note   This function can be used for all MM32 devices.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void FLASH_OPTB_Enable(void)
-{
-    FLASH->OPTKEYR = FLASH_KEY1;
-    FLASH->OPTKEYR = FLASH_KEY2;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Erases a specified FLASH page.
-/// @note   This function can be used for all MM32 devices.
-/// @param  page_address: The page address to be erased.
-/// @retval FLASH Status: The returned value can be: FLASH_BUSY,
-///         FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_ErasePage(u32 page_address)
-{
-    FLASH->CR |= FLASH_CR_PER;
-    FLASH->AR = page_address;
-    FLASH->CR |= FLASH_CR_STRT;
-    return FLASH_WaitForLastOperation(EraseTimeout);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Erases all FLASH pages.
-/// @note   This function can be used for all MM32 devices.
-/// @param  None.
-/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_EraseAllPages()
-{
-    FLASH->AR = FLASH_BASE;
-    FLASH->CR |= (FLASH_CR_MER | FLASH_CR_STRT);
-    return FLASH_WaitForLastOperation(EraseTimeout);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Erases the FLASH option bytes.
-/// @note   This function can be used for all MM32 devices.
-/// @param  None.
-/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_EraseOptionBytes()
-{
-    FLASH_OPTB_Enable();
-    FLASH->AR = OB_BASE;
-    FLASH->CR |= (FLASH_CR_OPTER | FLASH_CR_STRT);
-    return FLASH_WaitForLastOperation(EraseTimeout);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Programs a half word at a specified address.
-/// @note   This function can be used for all MM32 devices.
-/// @param  address: specifies the address to be programmed.
-/// @param  data: specifies the data to be programmed.
-/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_ProgramHalfWord(u32 address, u16 data)
-{
-    FLASH->CR |= FLASH_CR_PG;
-
-    *(vu16*)address = data;
-
-
-    return FLASH_WaitForLastOperation(ProgramTimeout);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Programs a word at a specified address.
-/// @note   This function can be used for all MM32 devices.
-/// @param  address: specifies the address to be programmed.
-/// @param  data: specifies the data to be programmed.
-/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_ProgramWord(u32 address, u32 data)
-{
-    FLASH_Status ret = FLASH_ProgramHalfWord(address, data);
-    if (ret == FLASH_COMPLETE) {
-        ret = FLASH_ProgramHalfWord(address + 2, data >> 16);
-    }
-    return ret;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Programs a byte at a specified Option Byte Data address.
-/// @note   This function can be used for all MM32 devices.
-/// @param  address: specifies the address to be programmed.
-///         This parameter can be 0x1FFFF804 or 0x1FFFF806.
-/// @param  data: specifies the data to be programmed.
-/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_ProgramOptionByteData(u32 address, u8 data)
-{
-    FLASH_Status ret;
-    __IO u16 temp;
-    FLASH_OPTB_Enable();
-    FLASH->CR |= FLASH_CR_OPTPG;
-    temp = (u16)(~data);
-    temp = (temp << 8) & 0xFF00;
-    temp = temp | (u16)data;
-    address = address & (~0x1);
-    *(vu16*)address = temp;
-    ret = FLASH_WaitForLastOperation(ProgramTimeout);
-
-    return ret;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Programs a half word at a specified Option Byte Data address.
-/// @note   This function can be used for all MM32 devices.
-/// @param  address: specifies the address to be programmed.
-///         This parameter can be 0x1FFFF804 or 0x1FFFF806.
-/// @param  data: specifies the data to be programmed.
-/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_ProgramOptionHalfWord(u32 address, u16 data)
-{
-    FLASH_Status ret;
-    FLASH_OPTB_Enable();
-    FLASH->CR |= FLASH_CR_OPTPG;
-    *(vu16*)address = data;
-    ret = FLASH_WaitForLastOperation(ProgramTimeout);
-
-    return ret;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Read protection for the specified address
-/// @note   This function can be used for all MM32 devices.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_ProgramProtect(u32 address, u16 data)
-{
-    return FLASH_ProgramOptionHalfWord(address, data);
-
-//    FLASH_Status ret;
-//  ret = FLASH_ProgramOptionHalfWord(address, 0x7F80);
-//
-//  if (ret == FLASH_COMPLETE) {
-//      ret = FLASH_ProgramOptionHalfWord(address + 2, 0xFF00);
-//    }
-//    return ret;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Write protection for the specified address
-/// @note   This function can be used for all MM32 devices.
-/// @param  page: specifies the address of the pages to be write
-///         protected.
-///         This parameter is (0x01 << ((Absolute address - 0x08000000)/0x1000))
-/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_EnableWriteProtection(u32 page)
-{
-    FLASH_Status ret;
-    u8           i;
-    for (i = 0; i < 4; i++) {
-        ret = FLASH_ProgramOptionHalfWord((OB_BASE + 8 + i * 2), ~(page >> (i * 8)));
-        if (ret != FLASH_COMPLETE) {
-            break;
-        }
-    }
-    return ret;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-/// @note   This function can be used for all MM32 devices.
-/// @param  ob_iwdg: Selects the IWDG mode
-/// @param  ob_stop: Reset event when entering STOP mode.
-/// @param  standby: Reset event when entering Standby mode.
-/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_UserOptionByteConfig(OB_IWDG_TypeDef ob_iwdg, OB_STOP_TypeDef ob_stop, OB_STDBY_TypeDef standby)
-{
-    FLASH_OPTB_Enable();
-    FLASH->CR |= FLASH_CR_OPTPG;
-    OB->USER = ob_iwdg;
-    OB->USER |= ob_stop;
-    OB->USER |= standby;
-    OB->USER |= 0xF8;
-    //    OB->USER = iwdg | stop | stdby | 0xF8;
-    return FLASH_WaitForLastOperation(ProgramTimeout);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the FLASH User Option Bytes values.
-/// @note   This function can be used for all MM32 devices.
-/// @param  None.
-/// @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
-///         and RST_STDBY(Bit2).
-////////////////////////////////////////////////////////////////////////////////
-u32 FLASH_GetUserOptionByte()
-{
-    return (FLASH->OBR >> 2);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the FLASH Write Protection Option Bytes Register value.
-/// @note   This function can be used for all MM32 devices.
-/// @param  None.
-/// @retval The FLASH Write Protection  Option Bytes Register value.
-////////////////////////////////////////////////////////////////////////////////
-u32 FLASH_GetWriteProtectionOptionByte()
-{
-    return (FLASH->WRPR);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
-/// @note   This function can be used for all MM32 devices.
-/// @param  None.
-/// @retval FLASH Prefetch Buffer Status (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus FLASH_GetPrefetchBufferStatus(void)
-{
-    return (FLASH->ACR & FLASH_ACR_PRFTBS) ? SET : RESET;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified FLASH interrupts.
-/// @note   This function can be used for all MM32 devices.
-/// @param  interrupt: specifies the FLASH interrupt sources to be enabled or
-///         disabled.
-/// @param  state: new state of the specified Flash interrupts.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void FLASH_ITConfig(FLASH_IT_TypeDef interrupt, FunctionalState state)
-{
-    (state) ? (FLASH->CR |= interrupt) : (FLASH->CR &= ~interrupt);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified FLASH flag is set or not.
-/// @note   This function can be used for all MM32 devices.
-/// @param  flag: specifies the FLASH flags to clear.
-///         This parameter can be one of the following values:
-/// @arg    FLASH_FLAG_BSY: FLASH Busy flag
-/// @arg    FLASH_FLAG_PGERR: FLASH Program error flag
-/// @arg    FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
-/// @arg    FLASH_FLAG_EOP: FLASH End of Operation flag
-/// @arg    FLASH_FLAG_OPTERR:  FLASH Option Byte error flag
-/// @retval The new state of FLASH_FLAG (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus FLASH_GetFlagStatus(u16 flag)
-{
-    return ((flag == FLASH_FLAG_OPTERR) ? (FLASH->OBR & FLASH_FLAG_OPTERR) : (FLASH->SR & flag)) ? SET : RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the FLASH's pending flags.
-/// @note   This function can be used for all MM32 devices.
-/// @param  flag: specifies the FLASH flags to clear.
-///         This parameter can be any combination of the following values:
-/// @arg    FLASH_FLAG_PGERR: FLASH Program error flag
-/// @arg    FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
-/// @arg    FLASH_FLAG_EOP: FLASH End of Operation flag
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void FLASH_ClearFlag(u16 flag)
-{
-    FLASH->SR = flag;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the FLASH Status.
-/// @note   This function can be used for all MM32 devices.
-/// @param  None.
-/// @retval FLASH Status: The returned value can be: FLASH_BUSY,
-///         FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_GetStatus()
-{
-    return (FLASH_Status)((FLASH->SR & FLASH_FLAG_BSY))
-           ? FLASH_BUSY
-           : ((FLASH->SR & FLASH_FLAG_PGERR) ? FLASH_ERROR_PG
-              : ((FLASH->SR & FLASH_FLAG_WRPRTERR) ? FLASH_ERROR_WRP : FLASH_COMPLETE));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Waits for a Flash operation to complete or a TIMEOUT to occur.
-/// @note   This function can be used for all MM32 devices
-/// @param  time_out: FLASH programming time_out
-/// @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-///         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-////////////////////////////////////////////////////////////////////////////////
-FLASH_Status FLASH_WaitForLastOperation(u32 time_out)
-{
-    u32          i;
-    FLASH_Status ret;
-    do {
-        ret = FLASH_GetStatus();
-        time_out--;
-        for (i = 0xFF; i != 0; i--)
-            ;
-    } while ((ret == FLASH_BUSY) && (time_out != 0x00));
-
-    FLASH->CR = 0;
-    FLASH->SR = FLASH_SR_EOP | FLASH_SR_WRPRTERR | FLASH_SR_PGERR;
-    return (FLASH_Status)((time_out == 0x00) ? FLASH_TIMEOUT : ret);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Erases a specified FLASH page.
-/// @note   This function can be used for all MM32 devices.
-/// @param  Page_Address: The page address to be erased.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exFLASH_EraseEE(u32 page_address)
-{
-    FLASH_Unlock();
-    FLASH_ErasePage(page_address);
-    FLASH_Lock();
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Programs a buffer at a specified address.
-/// @note   This function can be used for all MM32 devices.
-/// @param *buf: the pointer of the buffer to be programmed.
-/// @param  addr: specifies the address to be programmed.
-/// @param  len: the number of bytes in the buffer.
-///         This parameter can only be even.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exFLASH_ProgramEE(u16* buf, u32 addr, u16 len)
-{
-    u16 i;
-    FLASH_Unlock();
-    for (i = 0; i < len / 2; i++) {
-        FLASH_ProgramHalfWord(addr, *buf);
-        addr += 2;
-        buf++;
-    }
-    FLASH_Lock();
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Determine if the data that at the ptr address with the length is len
-///         is empty.
-/// @note   This function can be used for all MM32 devices.
-/// @param *ptr: the pointer of the starting address.
-/// @param  len: the number of bytes.
-///         This parameter can only be even.
-/// @retval 1 presents the data is empty,
-///         0 presents the data has been written.
-////////////////////////////////////////////////////////////////////////////////
-u8 exFLASH_FindEmpty(u16* ptr, u16 len)
-{
-    u16 i;
-    for (i = 0; i < (len / 2); i++) {
-        if (*(ptr + i) != 0xffff)
-            return 0;
-    }
-    return 1;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Locate the writable area on the specified address.
-/// @note   This function can be used for all MM32 devices.
-/// @param  page_address: specifies the beginning of the EEprom.
-///         The EEprom can be some continuously pages in the flash.
-/// @param  len: the number of bytes to be written.
-///         This parameter can only be even.
-/// @retval the pointer of the starting address.
-////////////////////////////////////////////////////////////////////////////////
-void* exFLASH_Locate(u32 page_address, u16 len)
-{
-    u16 i;
-    u16* ptr = (u16*)page_address;
-    for (i = 0; i < (0x0800 / len); i++) {
-        if (exFLASH_FindEmpty(ptr, len)) {
-            if (i == 0)
-                return 0;
-            break;
-        }
-        ptr += len / 2;
-    }
-    return ptr;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Programs a buffer at a specified address.
-/// @note   This function can be used for all MM32 devices.
-/// @param *buf: the pointer of the buffer to be programmed.
-/// @param  page_address: specifies the beginning of the EEprom.
-///         The EEprom can be some continuously pages in the flash.
-/// @param  len: the number of bytes in the buffer.
-///         This parameter can only be even.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exFLASH_WriteEE(u16* buf, u32 page_address, u16 len)
-{
-    u16* ptr = exFLASH_Locate(page_address, len);
-    if (ptr == 0) {
-        exFLASH_EraseEE(page_address + 0x000);
-        exFLASH_EraseEE(page_address + 0x400);
-        exFLASH_ProgramEE(buf, page_address, len);
-    }
-    else {
-        if (ptr == (u16*)(page_address + ((0x0400 / len) - 1) * len)) {
-            exFLASH_EraseEE(page_address + 0x400);
-            exFLASH_ProgramEE(buf, (u32)ptr, len);
-        }
-        else if (ptr == (u16*)(page_address + 0x0800)) {
-            exFLASH_EraseEE(page_address + 0x000);
-            exFLASH_ProgramEE(buf, (u32)page_address, len);
-        }
-        else {
-            exFLASH_ProgramEE(buf, (u32)ptr, len);
-        }
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Read the beginning address of the last written data.
-/// @note   This function can be used for all MM32 devices.
-/// @param  page_address: specifies the beginning of the EEprom.
-///         The EEprom can be some continuously pages in the flash.
-/// @param  len: the number of bytes have been written.
-///         This parameter can only be even.
-/// @retval the beginning address of the last written data.
-///         0 presents that this is the first time to use this as EEprom.
-////////////////////////////////////////////////////////////////////////////////
-void* exFLASH_ReadEE(u32 page_address, u16 len)
-{
-    u16* ptr = exFLASH_Locate(page_address, len);
-    return (ptr == 0) ? 0 : (ptr - len / 2);
-}
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c
deleted file mode 100644
index b4b665a0b..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_fsmc.c
+++ /dev/null
@@ -1,124 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_fsmc.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE FSMC FIRMWARE FUNCTIONS.
-///                Interface with SRAM, PSRAM, NOR memories
-///                Interrupts and flags management
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_FSMC_C_
-
-// Files includes
-#include "reg_rcc.h"
-#include "reg_syscfg.h"
-#include "hal_fsmc.h"
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup FSMC_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup FSMC_Exported_Functions
-/// @{
-
-
-void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct)
-{
-    init_struct->FSMC_Mode = FSMC_Mode_NorFlash;
-    init_struct->FSMC_AddrDataMode = FSMC_AddrDataDeMUX;
-
-    init_struct->FSMC_TimingRegSelect = FSMC_TimingRegSelect_0;
-    init_struct->FSMC_MemSize = FSMC_MemSize_64MB;
-    init_struct->FSMC_MemType = FSMC_MemType_NorSRAM;
-}
-void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct)
-{
-
-    init_struct->FSMC_SMReadPipe    = 0;
-    init_struct->FSMC_ReadyMode     = 0;
-    init_struct->FSMC_WritePeriod   = 0x2;
-    init_struct->FSMC_WriteHoldTime = 1;
-    init_struct->FSMC_AddrSetTime   = 3;
-    init_struct->FSMC_ReadPeriod    = 0x1;
-    init_struct->FSMC_DataWidth     = FSMC_DataWidth_16bits;
-}
-void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct)
-{
-    SYSCFG->CFGR &= ~(SYSCFG_CFGR_FSMC_MODE | SYSCFG_CFGR_FSMC_AF_ADDR | SYSCFG_CFGR_FSMC_SYNC_EN);
-    SYSCFG->CFGR |= (u32)init_struct->FSMC_Mode | \
-                    (u32)init_struct->FSMC_AddrDataMode;
-
-    FSMC->SMSKR = (u32)init_struct->FSMC_TimingRegSelect | \
-                  (u32)init_struct->FSMC_MemSize | \
-                  (u32)init_struct->FSMC_MemType;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initialize the FSMC_NORSRAM Timing according to the specified
-///         parameters in the FSMC_NORSRAM_TimingTypeDef
-/// @param  FSMC_Bank_InitStruct: Timing Pointer to NORSRAM Timing structure
-/// @param  Bank: NORSRAM bank number
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank)
-{
-    // Set FSMC_NORSRAM device timing parameters
-    if(bank == FSMC_NORSRAM_BANK0) {
-        FSMC->SMTMGR_SET0 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)    | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos)     | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos)   | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos)  | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos)    | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
-        FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET0;
-        FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos;
-    }
-    else if(bank == FSMC_NORSRAM_BANK1) {
-        FSMC->SMTMGR_SET1 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)    | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos)     | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos)   | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos)  | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos)    | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
-        FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET1;
-        FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos;
-    }
-    else if(bank == FSMC_NORSRAM_BANK2) {
-        FSMC->SMTMGR_SET2 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)    | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos)     | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos)   | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos)  | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos)    | \
-                            (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ;
-        FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET2;
-        FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos;
-    }
-}
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c
deleted file mode 100644
index 4363338f3..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c
+++ /dev/null
@@ -1,344 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_gpio.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE GPIO FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_GPIO_C_
-
-// Files includes
-#include "reg_exti.h"
-#include "hal_rcc.h"
-#include "hal_gpio.h"
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup GPIO_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup GPIO_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the gpio peripheral registers to their default reset
-///         values.
-/// @param  gpio: select the GPIO peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_DeInit(GPIO_TypeDef* gpio)
-{
-    switch (*(vu32*)&gpio) {
-        case (u32)GPIOA:
-            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, DISABLE);
-            break;
-        case (u32)GPIOB:
-            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOB, DISABLE);
-            break;
-        case (u32)GPIOC:
-            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOC, DISABLE);
-            break;
-        case (u32)GPIOD:
-            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOD, DISABLE);
-            break;
-        case (u32)GPIOE:
-            RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOE, DISABLE);
-            break;
-        default:
-            break;
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the Alternate Functions (remap, event control
-///         and EXTI configuration) registers to their default reset values.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_AFIODeInit()
-{
-    GPIOA->AFRL = 0xFFFFFFFF;
-    GPIOA->AFRH = 0xF00FFFFF;       //  PA14:SWCLK, PA13:PSWDIO
-    GPIOB->AFRL = 0xFFFFFFFF;
-    GPIOB->AFRH = 0xFFFFFFFF;
-    GPIOC->AFRL = 0xFFFFFFFF;
-    GPIOC->AFRH = 0xFFFFFFFF;
-    GPIOD->AFRL = 0xFFFFFFFF;
-    GPIOD->AFRH = 0xFFFFFFFF;
-    GPIOE->AFRL = 0xFFFFFFFF;
-    GPIOE->AFRH = 0xFFFFFFFF;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the gpio peripheral according to the specified
-///         parameters in the init_struct.
-/// @param  gpio: select the GPIO peripheral.
-/// @param  init_struct: pointer to a GPIO_InitTypeDef structure that
-///         contains the configuration information for the specified GPIO
-///         peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_Init(GPIO_TypeDef* gpio, GPIO_InitTypeDef* init_struct)
-{
-    u8   idx;
-    u8 i;
-    u32 tmp;
-    __IO u32* reg ;
-
-    // 1x
-    u32 dat = init_struct->GPIO_Mode & 0x0F;
-    if (init_struct->GPIO_Mode & 0x10)
-        dat |= init_struct->GPIO_Speed;
-
-    // 0x
-    reg  = &gpio->CRL;
-    for (i = 0; i < 8; i++) {
-        idx = i * 4;
-        if ((init_struct->GPIO_Pin) & (1 << i)) {
-            *reg  = (*reg  & ~(0xF << idx)) | (dat << idx);
-        }
-    }
-
-    reg     = &gpio->CRH;
-    tmp = init_struct->GPIO_Pin >> 8;
-    for (i = 0; i < 8; i++) {
-        idx = i * 4;
-        if (tmp & (1 << i)) {
-            *reg  = (*reg  & ~(0xF << idx)) | (dat << idx);
-        }
-    }
-
-    // 2x,4x
-    if (init_struct->GPIO_Mode == GPIO_Mode_IPD)
-        gpio->BRR |= init_struct->GPIO_Pin;
-    else if (init_struct->GPIO_Mode == GPIO_Mode_IPU)
-        gpio->BSRR |= init_struct->GPIO_Pin;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param init_struct : pointer to a GPIO_InitTypeDef structure
-///   which will be initialized.
-/// @retval : None
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_StructInit(GPIO_InitTypeDef* init_struct)
-{
-    // Reset GPIO init structure parameters values
-    init_struct->GPIO_Pin  = GPIO_Pin_All;
-    init_struct->GPIO_Speed = GPIO_Speed_2MHz;
-    init_struct->GPIO_Mode = GPIO_Mode_FLOATING;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Reads the input data of specified GPIO port pin.
-/// @param  gpio:  select the GPIO peripheral.
-/// @param  pin:  specifies the port pin to be read.
-///         This parameter can be GPIO_Pin_x where x can be (0..15).
-/// @retval The input port pin value.
-////////////////////////////////////////////////////////////////////////////////
-bool GPIO_ReadInputDataBit(GPIO_TypeDef* gpio, u16 pin)
-{
-    return ((gpio->IDR & pin)) ? Bit_SET : Bit_RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Reads all GPIO port pins input data.
-/// @param  gpio: select the GPIO peripheral.
-/// @retval GPIO port input data value.
-////////////////////////////////////////////////////////////////////////////////
-u16 GPIO_ReadInputData(GPIO_TypeDef* gpio)
-{
-    return gpio->IDR;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Reads the output data of specified GPIO port pin.
-/// @param  gpio: select the GPIO peripheral.
-/// @param  pin:  specifies the port bit to be read.
-///         This parameter can be GPIO_Pin_x where x can be (0..15).
-/// @retval The output port pin value.
-////////////////////////////////////////////////////////////////////////////////
-bool GPIO_ReadOutputDataBit(GPIO_TypeDef* gpio, u16 pin)
-{
-    return (gpio->ODR & pin) ? Bit_SET : Bit_RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Reads all GPIO port pins output data.
-/// @param  gpio: select the GPIO peripheral.
-/// @retval GPIO port output data value.
-////////////////////////////////////////////////////////////////////////////////
-u16 GPIO_ReadOutputData(GPIO_TypeDef* gpio)
-{
-    return gpio->ODR;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the selected GPIO port pin.
-/// @param  gpio: where x can be (A..D) to select the GPIO peripheral.
-/// @param  pin: specifies the port pins to be written.
-///         This parameter can be any combination of GPIO_Pin_x where x can be
-///         (0..15).
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_SetBits(GPIO_TypeDef* gpio, u16 pin)
-{
-    gpio->BSRR = pin;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the selected GPIO port bit.
-/// @param  gpio: where x can be (A..D) to select the GPIO peripheral.
-/// @param  pin: specifies the port pins to be written.
-///         This parameter can be any combination of GPIO_Pin_x where x can be
-///         (0..15).
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_ResetBits(GPIO_TypeDef* gpio, u16 pin)
-{
-    gpio->BRR = pin;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets or clears the selected GPIO port pin.
-/// @param  gpio: select the GPIO peripheral.
-/// @param  pin: specifies the port bit to be written.
-///         This parameter can be one of GPIO_Pin_x where x can be (0..15).
-/// @param  value: specifies the value to be written to the selected bit.
-///         This parameter can be one of the BitAction enum values:
-/// @arg    Bit_RESET: to clear the port pin
-/// @arg    Bit_SET: to set the port pin
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_WriteBit(GPIO_TypeDef* gpio, u16 pin, BitAction value)
-{
-    (value) ? (gpio->BSRR = pin) : (gpio->BRR = pin);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Writes data to all GPIO port pins.
-/// @param  gpio: where x can be (A..D) to select the GPIO peripheral.
-/// @param  value: specifies the value to be written to the port output data
-///         register.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_Write(GPIO_TypeDef* gpio, u16 value)
-{
-    gpio->ODR = value;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Locks GPIO Pins configuration.
-/// @param  gpio: to select the GPIO peripheral.
-/// @param  pin: specifies the port bit to be written.
-///         This parameter can be any combination of GPIO_Pin_x where x can be
-///         (0..15).
-/// @param  state: new lock state of the port pin.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_PinLock(GPIO_TypeDef* gpio, u16 pin, FunctionalState state)
-{
-    (state) ? (gpio->LCKR |= pin) : (gpio->LCKR &= ~pin);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Locks GPIO Pins configuration registers until next system reset.
-/// @param  gpio: to select the GPIO peripheral.
-/// @param  pin: specifies the port bit to be written.
-///         This parameter can be any combination of GPIO_Pin_x where x can be
-///         (0..15).
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_PinLockConfig(GPIO_TypeDef* gpio, u16 pin)
-{
-    gpio->LCKR = GPIO_LCKR_LCKK | pin;
-    gpio->LCKR = pin;
-    gpio->LCKR = GPIO_LCKR_LCKK | pin;
-    gpio->LCKR;
-    gpio->LCKR;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the port pin remapping.
-/// @param  remap: selects the pin to remap.
-/// @param  mask: the corresponding remapping mask of the remapping pin.
-/// @param  state: new state of the port pin remapping.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Writes data to the specified GPIO data port.
-/// @param  gpio: select the GPIO peripheral.
-/// @param  pin: specifies the pin for the Alternate function.
-///         This parameter can be GPIO_PinSourcex where x can be (0..15) for
-///         GPIOA, GPIOB, GPIOD and (0..12) for GPIOC .
-/// @param  alternate_function: selects the pin to used as Alternate function.
-///         This parameter can be the GPIO_AF_x where x can be (0..7).
-/// @note   The pin should be used for Digital IP.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GPIO_PinAFConfig(GPIO_TypeDef* gpio, u8 pin, u8 alternate_function)
-{
-    u8 shift = (pin & 0x07) * 4;
-    u32* ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH;
-    *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the remap function and AF function of the GPIO pin.
-/// @param  gpio:select the GPIO peripheral.
-/// @param  pin: specifies the pin for the Alternate function.
-///         This parameter can be GPIO_Pin_x where x can be (0..15) for
-///         GPIOA, GPIOB, GPIOD and (0..12) for GPIOC .
-/// @param  remap: selects the pin to remap.
-/// @param  alternate_function: selects the pin to used as Alternate function.
-///         This parameter can be the GPIO_AF_x where x can be (0..7).
-/// @note   The pin should be used for Digital IP.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exGPIO_PinAFConfig(GPIO_TypeDef* gpio, u16 pin, s32 remap, s8 alternate_function)
-{
-    u8 i;
-    u8 shift;
-    u32* ptr;
-
-    if (alternate_function >= 0) {
-        for (i = 0; i < 32; i++) {
-            if (pin & 0x01) {
-                pin = i;
-                break;
-            }
-            pin >>= 1;
-        }
-
-        shift = (pin & 0x07) * 4;
-        ptr = (pin < 8) ? (u32*)&gpio->AFRL : (u32*)&gpio->AFRH;
-        *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift);
-    }
-}
-
-
-/// @}
-
-/// @}
-
-/// @}
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c
deleted file mode 100644
index 855236a63..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_i2c.c
+++ /dev/null
@@ -1,526 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_i2c.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE I2C FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_I2C_C_
-
-// Files includes
-#include "hal_i2c.h"
-#include "hal_rcc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup I2C_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup I2C_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the i2c peripheral registers to their default
-///         reset values.
-/// @param  i2c: where n can be 1 or 2 to select the I2C peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_DeInit(I2C_TypeDef* i2c)
-{
-    switch (*(vu32*)&i2c) {
-        case (u32)I2C1:  // I2C1_BASE:
-            exRCC_APB1PeriphReset(RCC_APB1ENR_I2C1);
-            break;
-        case (u32)I2C2:  // I2C2_BASE:
-            exRCC_APB1PeriphReset(RCC_APB1ENR_I2C2);
-            break;
-        default:
-            break;
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the i2c peripheral according to the specified
-///         parameters in the init_struct.
-/// @param  i2c: select the I2C peripheral.
-/// @param  init_struct: pointer to a I2C_InitTypeDef structure that
-///         contains the configuration information for the specified
-///         I2C peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_Init(I2C_TypeDef* i2c, I2C_InitTypeDef* init_struct)
-{
-    u32 pclk1         = HSI_VALUE;
-    u32 minSclLowTime = 0;
-    u32 i2cPeriod     = 0;
-    u32 pclk1Period   = 0;
-
-
-    i2c->IC_ENABLE &= ~I2C_ENR_ENABLE;
-
-
-    pclk1       = RCC_GetPCLK1Freq();
-    pclk1Period = 1000000000 / pclk1;
-    i2cPeriod   = 1000000000 / init_struct->I2C_ClockSpeed;
-
-    minSclLowTime = pclk1 / init_struct->I2C_ClockSpeed ;
-    i2cPeriod = 82 / pclk1Period;
-
-    if (init_struct->I2C_ClockSpeed <= 100000) {
-        i2c->IC_SS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod) / 2;
-        i2c->IC_SS_SCL_HCNT = (minSclLowTime - 13 - i2cPeriod - i2c->IC_SS_SCL_LCNT);
-    }
-    else {
-        i2c->IC_FS_SCL_LCNT = (minSclLowTime - 13 - i2cPeriod ) / 2 + 4;
-        i2c->IC_FS_SCL_HCNT = (minSclLowTime - 13 - i2c->IC_FS_SCL_LCNT - i2cPeriod);
-    }
-
-    i2c->IC_CON &= ~(I2C_CR_EMPINT     |   \
-                     I2C_CR_SLAVEDIS   |   \
-                     I2C_CR_REPEN      |   \
-                     I2C_CR_MASTER10   |   \
-                     I2C_CR_SLAVE10    |   \
-                     I2C_CR_FAST       |   \
-                     I2C_CR_MASTER);
-
-    i2c->IC_CON =  I2C_CR_EMPINT       |   \
-                   I2C_CR_REPEN        |   \
-                   ((init_struct->I2C_Speed == I2C_CR_FAST) ? I2C_CR_FAST : I2C_CR_STD) | \
-                   ((init_struct->I2C_Mode)  ? I2C_CR_MASTER : 0x00);
-    i2c->IC_INTR_MASK &= INTR_MASK;
-
-    i2c->IC_RX_TL = 0x00;
-    i2c->IC_TX_TL = 0x00;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param  init_struct: pointer to an I2C_InitTypeDef structure
-///         which will be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_StructInit(I2C_InitTypeDef* init_struct)
-{
-    init_struct->I2C_Mode       = I2C_CR_MASTER;
-    init_struct->I2C_OwnAddress = I2C_OWN_ADDRESS;
-    init_struct->I2C_Speed      = I2C_CR_STD;
-    init_struct->I2C_ClockSpeed = 100000;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified I2C peripheral.
-/// @param  i2c: select the I2C peripheral.
-/// @param  state: new state of the i2c peripheral. This parameter
-///         can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_Cmd(I2C_TypeDef* i2c, FunctionalState state)
-{
-    (state) ? (i2c->IC_ENABLE |= I2C_ENR_ENABLE) : (i2c->IC_ENABLE &= ~I2C_ENR_ENABLE);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified I2C DMA requests.
-/// @param  i2c: select the I2C peripheral.
-/// @param  state: new state of the I2C DMA transfer.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_DMACmd(I2C_TypeDef* i2c, FunctionalState state)
-{
-    if (state) {
-        if (I2C_DMA_DIR == TDMAE_SET)
-            i2c->IC_DMA_CR |= TDMAE_SET;
-
-        else
-            i2c->IC_DMA_CR |= RDMAE_SET;
-    }
-    else
-        i2c->IC_DMA_CR &= ~(I2C_DMA_RXEN | I2C_DMA_TXEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Generates i2c communication START condition.
-/// @param  i2c: select the I2C peripheral.
-/// @param  state: new state of the I2C START condition generation.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_GenerateSTART(I2C_TypeDef* i2c, FunctionalState state)
-{
-    (state) ? (i2c->IC_CON |= I2C_CR_REPEN) : (i2c->IC_CON &= ~I2C_CR_REPEN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Generates i2c communication STOP condition.
-/// @param  i2c: select the I2C peripheral.
-/// @param  state: new state of the I2C STOP condition generation.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_GenerateSTOP(I2C_TypeDef* i2c, FunctionalState state)
-{
-    u16 overTime = 3000;
-
-    i2c->IC_ENABLE |= I2C_ENR_ABORT;
-
-    while (i2c->IC_ENABLE & I2C_ENR_ABORT) {
-        if (overTime-- == 0)
-            break;
-    }
-    i2c->IC_CLR_TX_ABRT;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the specified I2C own address2.
-/// @param  i2c: select the I2C peripheral.
-/// @param  addr: specifies the 7bit I2C own address2.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_OwnAddress2Config(I2C_TypeDef* i2c, u8 addr)
-{
-    MODIFY_REG(i2c->IC_TAR, (u16)I2C_TAR_ADDR, (u16)(addr >> 1));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified I2C dual addressing mode.
-/// @param  i2c: select the I2C peripheral.
-/// @param  state: new state of the I2C dual addressing mode.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_DualAddressCmd(I2C_TypeDef* i2c, FunctionalState state)
-{
-    (state) ? (i2c->IC_TAR |= IC_TAR_ENDUAL_Set) : (i2c->IC_TAR &= IC_TAR_ENDUAL_Reset);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified I2C general call feature.
-/// @param  i2c: select the I2C peripheral.
-/// @param  state: new state of the I2C General call.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_GeneralCallCmd(I2C_TypeDef* i2c, FunctionalState state)
-{
-    (state) ? (i2c->IC_TAR |= I2C_TAR_SPECIAL) : (i2c->IC_TAR &= ~I2C_TAR_SPECIAL);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified I2C interrupts.
-/// @param  i2c: select the I2C peripheral.
-/// @param  it: specifies the I2C interrupts sources to be enabled
-///         or disabled.
-///         This parameter can be any combination of the following values:
-/// @arg    I2C_IT_RX_UNDER   : Rx Buffer is empty interrupt mask
-/// @arg    I2C_IT_RX_OVER    : RX  Buffer Overrun interrupt mask
-/// @arg    I2C_IT_RX_FULL    : Rx buffer full interrupt mask
-/// @arg    I2C_IT_TX_OVER    : TX  Buffer Overrun interrupt mask
-/// @arg    I2C_IT_TX_EMPTY   : TX_FIFO empty interrupt mask
-/// @arg    I2C_IT_RD_REQ     : I2C work as slave or master interrupt mask
-/// @arg    I2C_IT_TX_ABRT    : TX error interrupt  mask(Master mode)
-/// @arg    I2C_IT_RX_DONE    : Master not ack interrupt mask(slave mode)
-/// @arg    I2C_IT_ACTIVITY   : I2C activity interrupt mask
-/// @arg    I2C_IT_STOP_DET   : stop condition  interrupt mask
-/// @arg    I2C_IT_START_DET  : start condition  interrupt mask
-/// @arg    I2C_IT_GEN_CALL   : a general call address and ack interrupt mask
-/// @param  state: new state of the specified I2C interrupts.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_ITConfig(I2C_TypeDef* i2c, u16 it, FunctionalState state)
-{
-    if (it == I2C_IT_RX_FULL)
-        I2C_ReadCmd(i2c);
-    (state) ? SET_BIT(i2c->IC_INTR_MASK, it) : CLEAR_BIT(i2c->IC_INTR_MASK, (u16)it);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sends a data byte through the i2c peripheral.
-/// @param  i2c: select the I2C peripheral.
-/// @param  dat: Byte to be transmitted..
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_SendData(I2C_TypeDef* i2c, u8 dat)
-{
-    i2c->IC_DATA_CMD = dat;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the most recent received data by the i2c peripheral.
-/// @param  i2c: select the I2C peripheral.
-/// @retval The value of the received data.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_ReadCmd(I2C_TypeDef* i2c)
-{
-    i2c->IC_DATA_CMD = I2C_DR_CMD;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the most recent received data by the i2c peripheral.
-/// @param  i2c: select the I2C peripheral.
-/// @retval The value of the received data.
-////////////////////////////////////////////////////////////////////////////////
-u8 I2C_ReceiveData(I2C_TypeDef* i2c)
-{
-    I2C_CMD_DIR = 0;
-    return (u8)i2c->IC_DATA_CMD;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Transmits the address byte to select the slave device.
-/// @param  i2c: select the I2C peripheral.
-/// @param  addr: specifies the slave address which will be transmitted
-/// @param  dir: specifies whether the I2C device will be a
-///   Transmitter or a Receiver.
-///   This parameter can be one of the following values
-/// @arg  I2C_Direction_Transmitter: Transmitter mode
-/// @arg  I2C_Direction_Receiver: Receiver mode
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_Send7bitAddress(I2C_TypeDef* i2c, u8 addr, u8 dir)
-{
-    i2c->IC_TAR = addr >> 1;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Reads the specified I2C register and returns its value.
-/// @param  i2c: select the I2C peripheral.
-/// @param  reg: specifies the register to read.
-///         This parameter can be one of the following values:
-/// @retval The value of the read register.
-////////////////////////////////////////////////////////////////////////////////
-u16 I2C_ReadRegister(I2C_TypeDef* i2c, u8 reg)
-{
-    return (*(vu16*)(*((u32*)&i2c) + reg));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the last i2c Event.
-/// @param  i2c: select the I2C peripheral.
-/// @retval The last event
-////////////////////////////////////////////////////////////////////////////////
-u32 I2C_GetLastEvent(I2C_TypeDef* i2c)
-{
-    return (u32)i2c->IC_RAW_INTR_STAT & FLAG_Mask;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the last i2c Event is equal to the one passed
-///   as parameter.
-/// @param  i2c: select the I2C peripheral.
-/// @param  event: specifies the event to be checked.
-///   This parameter can be one of the following values:
-/// @arg  I2C_EVENT_RX_UNDER : Rx Buffer is empty event
-/// @arg  I2C_EVENT_RX_OVER  : RX  Buffer Overrun event
-/// @arg  I2C_EVENTT_RX_FULL : Rx buffer full event
-/// @arg  I2C_EVENT_TX_OVER  : TX  Buffer Overrun event
-/// @arg  I2C_EVENT_TX_EMPTY : TX_FIFO empty event
-/// @arg  I2C_EVENT_RD_REQ   : I2C work as slave or master event
-/// @arg  I2C_EVENT_TX_ABRT  : TX error event(Master mode)
-/// @arg  I2C_EVENT_RX_DONE  : Master not ack event(slave mode)
-/// @arg  I2C_EVENT_ACTIVITY : I2C activity event
-/// @arg  I2C_EVENT_STOP_DET : stop condition  event
-/// @arg  I2C_EVENT_START_DET: start condition  event
-/// @arg  I2C_EVENT_GEN_CALL : a general call address and ack event
-/// - SUCCESS: Last event is equal to the I2C_EVENT
-/// - ERROR: Last event is different from the I2C_EVENT
-////////////////////////////////////////////////////////////////////////////////
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* i2c, u32 event)
-{
-    if ((event == I2C_EVENT_RX_FULL) && (I2C_CMD_DIR == 0)) {
-        i2c->IC_DATA_CMD = I2C_DR_CMD;
-        I2C_CMD_DIR       = 1;
-    }
-
-    return (ErrorStatus)((i2c->IC_RAW_INTR_STAT & event) == event);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified I2C flag is set or not.
-/// @param  i2c: select the I2C peripheral.
-/// @param  flag: specifies the flag to check.
-///   This parameter can be one of the following values:
-/// @arg  I2C_FLAG_RX_UNDER : Rx Buffer is empty flag
-/// @arg  I2C_FLAG_RX_OVER  : RX  Buffer Overrun flag
-/// @arg  I2C_FLAG_RX_FULL  : Rx buffer full flag
-/// @arg  I2C_FLAG_TX_OVER  : TX  Buffer Overrun flag
-/// @arg  I2C_FLAG_TX_EMPTY : TX_FIFO empty flag
-/// @arg  I2C_FLAG_RD_REQ   : I2C work as slave or master flag
-/// @arg  I2C_FLAG_TX_ABRT  : TX error flag(Master mode)
-/// @arg  I2C_FLAG_RX_DONE  : Master not ack flag(slave mode)
-/// @arg  I2C_FLAG_ACTIVITY : I2C activity flag
-/// @arg  I2C_FLAG_STOP_DET : stop condition  flag
-/// @arg  I2C_FLAG_START_DET: start condition  flag
-/// @arg  I2C_FLAG_GEN_CALL : a general call address and ack flag
-/// @retval The new state of I2C_FLAG (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* i2c, u32 flag)
-{
-    if (flag & 0x8000)
-        return ((i2c->IC_STATUS & flag) ? SET : RESET);
-
-    if ((flag == I2C_FLAG_RX_FULL) && (I2C_CMD_DIR == 0)) {
-        i2c->IC_DATA_CMD = I2C_DR_CMD;
-        I2C_CMD_DIR       = 1;
-    }
-    return (((i2c->IC_RAW_INTR_STAT & flag)) ? SET : RESET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the i2c's pending flags.
-/// @param  i2c: select the I2C peripheral.
-/// @param  flag: specifies the flag to clear.
-///   This parameter can be any combination of the following values:
-/// @arg  I2C_FLAG_RX_UNDER : Rx Buffer is empty flag
-/// @arg  I2C_FLAG_RX_OVER  : RX  Buffer Overrun flag
-/// @arg  I2C_FLAG_RX_FULL  : Rx buffer full flag
-/// @arg  I2C_FLAG_TX_OVER  : TX  Buffer Overrun flag
-/// @arg  I2C_FLAG_TX_EMPTY : TX_FIFO empty flag
-/// @arg  I2C_FLAG_RD_REQ   : I2C work as slave or master flag
-/// @arg  I2C_FLAG_TX_ABRT  : TX error flag(Master mode)
-/// @arg  I2C_FLAG_RX_DONE  : Master not ack flag(slave mode)
-/// @arg  I2C_FLAG_ACTIVITY : I2C activity flag
-/// @arg  I2C_FLAG_STOP_DET : stop condition  flag
-/// @arg  I2C_FLAG_START_DET: start condition  flag
-/// @arg  I2C_FLAG_GEN_CALL : a general call address and ack flag
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_ClearFlag(I2C_TypeDef* i2c, u32 flag)
-{
-    if ((flag & I2C_FLAG_RX_UNDER) == I2C_FLAG_RX_UNDER)
-        i2c->IC_CLR_RX_UNDER;
-    if ((flag & I2C_FLAG_RX_OVER) == I2C_FLAG_RX_OVER)
-        i2c->IC_CLR_RX_OVER;
-    if ((flag & I2C_FLAG_TX_OVER) == I2C_FLAG_TX_OVER)
-        i2c->IC_CLR_TX_OVER;
-    if ((flag & I2C_FLAG_RD_REQ) == I2C_FLAG_RD_REQ)
-        i2c->IC_CLR_RD_REQ;
-    if ((flag & I2C_FLAG_TX_ABRT) == I2C_FLAG_TX_ABRT)
-        i2c->IC_CLR_TX_ABRT;
-    if ((flag & I2C_FLAG_RX_DONE) == I2C_FLAG_RX_DONE)
-        i2c->IC_CLR_RX_DONE;
-    if ((flag & I2C_FLAG_ACTIVITY) == I2C_FLAG_ACTIVITY)
-        i2c->IC_CLR_ACTIVITY;
-    if ((flag & I2C_FLAG_STOP_DET) == I2C_FLAG_STOP_DET)
-        i2c->IC_CLR_STOP_DET;
-    if ((flag & I2C_FLAG_START_DET) == I2C_FLAG_START_DET)
-        i2c->IC_CLR_START_DET;
-    if ((flag & I2C_FLAG_GEN_CALL) == I2C_FLAG_GEN_CALL)
-        i2c->IC_CLR_GEN_CALL;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified I2C interrupt has occurred or not.
-/// @param  i2c: select the I2C peripheral.
-/// @param  it: specifies the interrupt source to check.
-///   This parameter can be one of the following values:
-/// @arg  I2C_IT_RX_UNDER : Rx Buffer is empty interrupt
-/// @arg  I2C_IT_RX_OVER  : RX  Buffer Overrun interrupt
-/// @arg  I2C_IT_RX_FULL  : Rx buffer full interrupt
-/// @arg  I2C_IT_TX_OVER  : TX  Buffer Overrun interrupt
-/// @arg  I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
-/// @arg  I2C_IT_RD_REQ   : I2C work as slave or master interrupt
-/// @arg  I2C_IT_TX_ABRT  : TX error interrupt  (Master mode)
-/// @arg  I2C_IT_RX_DONE  : Master not ack interrupt (slave mode)
-/// @arg  I2C_IT_ACTIVITY : I2C activity interrupt
-/// @arg  I2C_IT_STOP_DET : stop condition  interrupt
-/// @arg  I2C_IT_START_DET: start condition  interrupt
-/// @arg  I2C_IT_GEN_CALL : a general call address and ack interrupt
-/// @retval The new state of I2C_IT (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus I2C_GetITStatus(I2C_TypeDef* i2c, u32 it)
-{
-    return ((i2c->IC_RAW_INTR_STAT & it) ? SET : RESET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the i2c interrupt pending bits.
-/// @param  i2c: select the I2C peripheral.
-/// @param  it: specifies the interrupt pending bit to clear.
-///   This parameter can be any combination of the following values:
-/// @arg  I2C_IT_RX_UNDER : Rx Buffer is empty interrupt
-/// @arg  I2C_IT_RX_OVER  : RX  Buffer Overrun interrupt
-/// @arg  I2C_IT_RX_FULL  : Rx buffer full interrupt
-/// @arg  I2C_IT_TX_OVER  : TX  Buffer Overrun interrupt
-/// @arg  I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
-/// @arg  I2C_IT_RD_REQ   : I2C work as slave or master interrupt
-/// @arg  I2C_IT_TX_ABRT  : TX error interrupt  (Master mode)
-/// @arg  I2C_IT_RX_DONE  : Master not ack interrupt (slave mode)
-/// @arg  I2C_IT_ACTIVITY : I2C activity interrupt
-/// @arg  I2C_IT_STOP_DET : stop condition  interrupt
-/// @arg  I2C_IT_START_DET: start condition  interrupt
-/// @arg  I2C_IT_GEN_CALL : a general call address and ack interrupt
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_ClearITPendingBit(I2C_TypeDef* i2c, u32 it)
-{
-    if ((it & I2C_IT_RX_UNDER) == I2C_FLAG_RX_UNDER)
-        i2c->IC_CLR_RX_UNDER;
-    if ((it & I2C_IT_RX_OVER) == I2C_FLAG_RX_OVER)
-        i2c->IC_CLR_RX_OVER;
-    if ((it & I2C_IT_TX_OVER) == I2C_FLAG_TX_OVER)
-        i2c->IC_CLR_TX_OVER;
-    if ((it & I2C_IT_RD_REQ) == I2C_FLAG_RD_REQ)
-        i2c->IC_CLR_RD_REQ;
-    if ((it & I2C_IT_TX_ABRT) == I2C_FLAG_TX_ABRT)
-        i2c->IC_CLR_TX_ABRT;
-    if ((it & I2C_IT_RX_DONE) == I2C_FLAG_RX_DONE)
-        i2c->IC_CLR_RX_DONE;
-    if ((it & I2C_IT_ACTIVITY) == I2C_FLAG_ACTIVITY)
-        i2c->IC_CLR_ACTIVITY;
-    if ((it & I2C_IT_STOP_DET) == I2C_FLAG_STOP_DET)
-        i2c->IC_CLR_STOP_DET;
-    if ((it & I2C_IT_START_DET) == I2C_FLAG_START_DET)
-        i2c->IC_CLR_START_DET;
-    if ((it & I2C_IT_GEN_CALL) == I2C_FLAG_GEN_CALL)
-        i2c->IC_CLR_GEN_CALL;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-//
-//  New Function Interface
-//
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures slave address.
-/// @param  i2c: select the I2C peripheral.
-/// @param  addr: specifies the slave address which will be transmitted
-///   This parameter can be one of the following values
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_SendSlaveAddress(I2C_TypeDef* i2c, u8 addr)
-{
-    WRITE_REG(i2c->IC_SAR, addr >> 1);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the I2C slave mode.
-/// @param  i2c: select the I2C peripheral.
-/// @param  state: new state of the specified I2C interrupts.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2C_SlaveConfigure(I2C_TypeDef* i2c, FunctionalState state)
-{
-    (state) ? CLEAR_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS) : SET_BIT(i2c->IC_CON, I2C_CR_SLAVEDIS);
-}
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c
deleted file mode 100644
index 06b49fb24..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_iwdg.c
+++ /dev/null
@@ -1,208 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_iwdg.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE IWDG FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_IWDG_C_
-
-// Files includes
-#include "hal_iwdg.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup IWDG_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup IWDG_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables write access to IWDG_PR and IWDG_RLR
-///   registers.
-/// @param  write_access: new state of write access to IWDG_PR and
-///   IWDG_RLR registers.
-///   This parameter can be one of the following values:
-/// @arg IWDG_WriteAccess_Enable: Enable write access to
-///   IWDG_PR and IWDG_RLR registers
-/// @arg IWDG_WriteAccess_Disable: Disable write access to
-///   IWDG_PR and IWDG_RLR registers
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void IWDG_WriteAccessCmd(u16 write_access)
-{
-    IWDG->KR = write_access;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets IWDG Prescaler value.
-/// @param  prescaler: specifies the IWDG Prescaler value.
-///         This parameter can be one of the following values:
-/// @arg    IWDG_Prescaler_4: IWDG prescaler set to 4
-/// @arg    IWDG_Prescaler_8: IWDG prescaler set to 8
-/// @arg    IWDG_Prescaler_16: IWDG prescaler set to 16
-/// @arg    IWDG_Prescaler_32: IWDG prescaler set to 32
-/// @arg    IWDG_Prescaler_64: IWDG prescaler set to 64
-/// @arg    IWDG_Prescaler_128: IWDG prescaler set to 128
-/// @arg    IWDG_Prescaler_256: IWDG prescaler set to 256
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void IWDG_SetPrescaler(u8 prescaler)
-{
-    IWDG->PR = prescaler;
-    PVU_CheckStatus();
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set IWDG reload value.
-/// @param  reload: specifies the IWDG reload value.
-///         This parameter must be a number between 0 and 0x0FFF.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void IWDG_SetReload(u16 reload)
-{
-    IWDG->RLR = reload;
-    RVU_CheckStatus();
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Get IWDG reload value.
-/// @param  None.
-/// @retval reload: specifies the IWDG reload value.
-////////////////////////////////////////////////////////////////////////////////
-u32 IWDG_GetReload(void)
-{
-    return IWDG->RLR;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Reloads IWDG counter with value defined in the reload register
-///   (write access to IWDG_PR and IWDG_RLR registers disabled).
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void IWDG_ReloadCounter(void)
-{
-    IWDG->KR = KR_KEY_Reload;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
-///         disabled).
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void IWDG_Enable(void)
-{
-    IWDG->KR = KR_KEY_Enable;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified IWDG flag is set or not.
-/// @param  flag: specifies the flag to check.
-///   This parameter can be one of the following values:
-/// @arg    IWDG_FLAG_PVU: Prescaler Value Update on going
-/// @arg    IWDG_FLAG_RVU: reload Value Update on going
-/// @retval The new state of flag (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus IWDG_GetFlagStatus(u16 flag)
-{
-    return ((IWDG->SR & flag) != (u32)RESET) ? SET : RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks prescaler value has been updated.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PVU_CheckStatus(void)
-{
-    while (IWDG_GetFlagStatus(IWDG_FLAG_PVU) == SET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks count relead value has been updated.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RVU_CheckStatus(void)
-{
-    while (IWDG_GetFlagStatus(IWDG_FLAG_RVU) == SET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  IWDG overflow configuration.
-/// @param  overflow_config
-/// @arg    IWDG_Overflow_Interrupt: Interrupt after overflow.
-/// @arg    IWDG_Overflow_Reset:     Reset after overflow.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void IWDG_OverflowConfig(IWDGOverflowConfig_TypeDef overflow_config)
-{
-    IWDG->CR &= ~IWDG_CR_IRQSEL;
-    IWDG->CR |= overflow_config;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clear interrupt flag
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void IWDG_ClearITPendingBit(void)
-{
-    IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clear interrupt flag
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void IWDG_ClearIT(void)
-{
-    IWDG->CR |= IWDG_CR_IRQCLR;//write 1 clear interrupt Flag
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enable IWDG interrupt function
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void IWDG_EnableIT(void)
-{
-    IWDG->CR |= IWDG_CR_IRQSEL;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Disable IWDG interrupt function
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void IWDG_Reset(void)
-{
-    IWDG->CR &= ~IWDG_CR_IRQSEL;
-}
-
-
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c
deleted file mode 100644
index 598d6d07e..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_misc.c
+++ /dev/null
@@ -1,147 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_misc.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE MSIC FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_MISC_C_
-
-// Files includes
-#include "hal_misc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MSIC_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MISC_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the NVIC interrupt vector table.
-/// @param  vect_tab
-///         This parameter can be any combination of the following values:
-///    @arg NVIC_VectTab_RAM
-///    @arg NVIC_VectTab_FLASH
-/// @param  offset
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void NVIC_SetVectorTable(u32 vect_tab, u32 offset)
-{
-    SCB->VTOR = vect_tab | (offset & (u32)0x1FFFFF80);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the NVIC interrupt priority group.
-/// @param  priority_group
-///         This parameter can be any combination of the following values:
-///    @arg NVIC_PriorityGroup_0
-///    @arg NVIC_PriorityGroup_1
-///    @arg NVIC_PriorityGroup_2
-///    @arg NVIC_PriorityGroup_3
-///    @arg NVIC_PriorityGroup_4
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void NVIC_PriorityGroupConfig(u32 priority_group)
-{
-    SCB->AIRCR = AIRCR_VECTKEY_MASK | priority_group;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  NVIC initialization.
-/// @param  init_struct
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void NVIC_Init(NVIC_InitTypeDef* init_struct)
-{
-    if (init_struct->NVIC_IRQChannelCmd != DISABLE) {
-        u32 pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos;
-
-        pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) |
-               (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri)))
-              << 0x04;
-
-        NVIC->IP[init_struct->NVIC_IRQChannel]           = pri;
-        NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
-    }
-    else {
-        NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
-    }
-
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  NVIC initialized extension function.
-/// @param  init_struct
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exNVIC_Init(exNVIC_Init_TypeDef* init_struct)
-{
-    u32 pri;
-
-    if (init_struct->NVIC_IRQChannelCmd != DISABLE) {
-        pri = (SCB_AIRCR_PRIGROUP & ~(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk)) >> SCB_AIRCR_PRIGROUP_Pos;
-
-        pri = (((u32)init_struct->NVIC_IRQChannelPreemptionPriority << (0x4 - pri)) |
-               (init_struct->NVIC_IRQChannelSubPriority & (0x0F >> pri))) << 0x04;
-
-        NVIC->IP[init_struct->NVIC_IRQChannel] = pri;
-        NVIC->ISER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
-    }
-    else {
-        NVIC->ICER[init_struct->NVIC_IRQChannel >> 0x05] = 0x01 << (init_struct->NVIC_IRQChannel & 0x1F);
-    }
-
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  System low power mode configuration.
-/// @param  low_power_mode
-///         This parameter can be any combination of the following values:
-///    @arg NVIC_LP_SEVONPEND
-///    @arg NVIC_LP_SLEEPDEEP
-///    @arg NVIC_LP_SLEEPONEXIT
-/// @param  state: new state of the low power mode.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void NVIC_SystemLPConfig(u8 low_power_mode, FunctionalState state)
-{
-    (state) ? (SCB->SCR |= low_power_mode) : (SCB->SCR &= ~(u32)low_power_mode);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SysTick clock source configuration.
-/// @param  systick_clk_source
-///         This parameter can be any combination of the following values:
-///    @arg SysTick_CLKSource_EXTCLK
-///    @arg SysTick_CLKSource_HCLK
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SysTick_CLKSourceConfig(u32 systick_clk_source)
-{
-    (systick_clk_source == SysTick_CLKSource_HCLK) ? (SysTick->CTRL |= SysTick_CLKSource_HCLK) \
-    : (SysTick->CTRL &= ~SysTick_CLKSource_HCLK);
-}
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c
deleted file mode 100644
index e39bf3f31..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_pwr.c
+++ /dev/null
@@ -1,215 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_pwr.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE PWR FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define __HAL_PWR_C_
-
-// Files includes
-#include "hal_pwr.h"
-#include "hal_rcc.h"
-#include "hal_syscfg.h"
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup PWR_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup PWR_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the PWR peripheral registers to their default reset
-/// values.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PWR_DeInit(void)
-{
-    exRCC_APB1PeriphReset(RCC_APB1ENR_PWR);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables access to the RTC and backup registers.
-/// @param  state: new state of the access to the RTC and backup
-///         registers. This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PWR_BackupAccessCmd(FunctionalState state)
-{
-    (state) ? (RCC->BDCR |= RCC_BDCR_DBP) : (RCC->BDCR &= ~RCC_BDCR_DBP);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the Power Voltage Detector(PVD).
-/// @param  state: new state of the PVD.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PWR_PVDCmd(FunctionalState state)
-{
-    (state) ? (SYSCFG->PDETCSR |= SYSCFG_PDETCSR_PVDE) : (SYSCFG->PDETCSR &= ~SYSCFG_PDETCSR_PVDE);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the voltage threshold detected by the Power Voltage
-///         Detector(PVD).
-/// @param  pvd_level: specifies the PVD detection level
-///         This parameter can be one of the following values:
-/// @arg    emPVD_LEVEL0 : PVD detection level set to 1.7V
-/// @arg    emPVD_LEVEL1 : PVD detection level set to 2.0V
-/// @arg    emPVD_LEVEL2 : PVD detection level set to 2.3V
-/// @arg    emPVD_LEVEL3 : PVD detection level set to 2.6V
-/// @arg    emPVD_LEVEL4 : PVD detection level set to 2.9V
-/// @arg    emPVD_LEVEL5 : PVD detection level set to 3.2V
-/// @arg    emPVD_LEVEL6 : PVD detection level set to 3.5V
-/// @arg    emPVD_LEVEL7 : PVD detection level set to 3.8V
-/// @arg    emPVD_LEVEL8 : PVD detection level set to 4.1V
-/// @arg    emPVD_LEVEL9 : PVD detection level set to 4.4V
-/// @arg    emPVD_LEVEL10: PVD detection level set to 4.7V
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PWR_PVDLevelConfig(emPVD_Level_Typedef pvd_level)
-{
-    SYSCFG->PDETCSR = (SYSCFG->PDETCSR & (~SYSCFG_PDETCSR_PLS)) | pvd_level;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the WakeUp Pin functionality.
-/// @param  state: new state of the WakeUp Pin functionality.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PWR_WakeUpPinCmd(FunctionalState state)
-{
-    (state != DISABLE) ? (PWR->CR2 |= PWR_CR2_EWUP1) : (PWR->CSR &= ~PWR_CR2_EWUP1);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the WakeUp Pin functionality.
-/// @param  state: new state of the WakeUp Pin functionality.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PWR_WakeUpPinXCmd(emWUP_Pin_Typedef pin, FunctionalState state)
-{
-    (state != DISABLE) ? (PWR->CR2 |= (PWR_CR2_EWUP1 << pin)) : (PWR->CSR &= ~(PWR_CR2_EWUP1 << pin));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enters STOP mode.
-/// @param  regulator: specifies the regulator state in STOP mode.
-///         This parameter can be one of the following values:
-/// @arg    PWR_Regulator_ON: STOP mode with regulator ON
-/// @arg    PWR_Regulator_LowPower: STOP mode with regulator in low power mode.
-/// @param  stop_entry: specifies if STOP mode in entered with WFI or  WFE
-///         instruction.
-///         This parameter can be one of the following values:
-/// @arg    PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
-/// @arg    PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PWR_EnterSTOPMode(emPWR_Reg_Stop_mode_Typedef regulator, emPWR_STOP_ModeEn_Typedef stop_entry)
-{
-
-    MODIFY_REG(PWR->CR, PWR_CR_LDPS, regulator);
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-    if(stop_entry == PWR_STOPEntry_WFI) {
-        __WFI();
-    }
-    else {
-        __WFE();
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enters STANDBY mode.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PWR_EnterSTANDBYMode(void)
-{
-    PWR->CR |= PWR_CR_PDDS;
-    PWR->SCR |= PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5 | PWR_SCR_CWUF6;
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-#if defined(__CC_ARM)
-    __force_stores();
-#endif
-    __WFI();
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified PWR flag is set or not.
-/// @param  flag: specifies the flag to check.
-///         This parameter can be one of the following values:
-/// @arg    PWR_FLAG_WU: Wake Up flag
-/// @arg    PWR_FLAG_SB: StandBy flag
-/// @arg    PWR_FLAG_PVDO: PVD Output
-/// @retval The new state of PWR_FLAG (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus PWR_GetPVDOFlagStatus(u32 flag)
-{
-    return (FlagStatus)(SYSCFG->PDETCSR & flag);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the PWR's pending flags.
-/// @param  flag: specifies the flag to clear.
-///         This parameter can be one of the following values:
-/// @arg    PWR_FLAG_WU: Wake Up flag
-/// @arg    PWR_FLAG_SB: StandBy flag
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PWR_ClearPVDOFlag(u32 flag)
-{
-    PWR->CR |= flag << 2;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified PWR flag is set or not.
-/// @param  flag: specifies the flag to check.
-///         This parameter can be one of the following values:
-/// @arg    PWR_FLAG_WU: Wake Up flag
-/// @arg    PWR_FLAG_SB: StandBy flag
-/// @arg    PWR_FLAG_PVDO: PVD Output
-/// @retval The new state of PWR_FLAG (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus PWR_GetFlagStatus(u32 flag)
-{
-    return (FlagStatus)(PWR->CSR & flag);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the PWR's pending flags.
-/// @param  flag: specifies the flag to clear.
-///         This parameter can be one of the following values:
-/// @arg    PWR_FLAG_WU: Wake Up flag
-/// @arg    PWR_FLAG_SB: StandBy flag
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void PWR_ClearFlag(u32 flag)
-{
-    PWR->CR |= flag << 2;
-}
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c
deleted file mode 100644
index 5e2bd1a85..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c
+++ /dev/null
@@ -1,995 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_rcc.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE RCC FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_RCC_C_
-
-// Files includes
-#include "mm32_reg.h"
-#include "hal_rcc.h"
-
-
-
-u8 tbPresc[] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup RCC_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup RCC_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Resets the RCC clock configuration to default state.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_DeInit()
-{
-    SET_BIT(RCC->CR, RCC_CR_HSION);
-    CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
-    CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON );
-    CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP);
-    CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-    CLEAR_REG(RCC->CFGR);
-    CLEAR_REG(RCC->CIR);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the External High Speed oscillator (HSE).
-/// @param  state: specifies the new state of HSE.
-///         This parameter can be one of the following values:
-/// @arg    RCC_HSE_OFF: HSE oscillator OFF
-/// @arg    RCC_HSE_ON: HSE oscillator ON
-/// @arg    RCC_HSE_Bypass: HSE oscillator bypassed with external clock
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_HSEConfig(RCCHSE_TypeDef state)
-{
-    RCC->CR &= ~(RCC_CR_HSEBYP | RCC_CR_HSEON);
-    switch (state) {
-        case RCC_HSE_Bypass:
-            RCC->CR |= RCC_CR_HSEBYP;
-            RCC->CR |= RCC_CR_HSEON;
-            break;
-        case RCC_HSE_ON:
-            RCC->CR |= RCC_CR_HSEON;
-            break;
-        default:
-            break;
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified RCC flag is set or not.
-/// @param  flag: specifies the flag to check.
-///         This parameter can be one of the following values:
-/// @arg    RCC_FLAG_HSIRDY: HSI oscillator clock ready
-/// @arg    RCC_FLAG_HSERDY: HSE oscillator clock ready
-/// @arg    RCC_FLAG_PLLRDY: PLL clock ready
-/// @arg    RCC_FLAG_LSERDY: LSE oscillator clock ready
-/// @arg    RCC_FLAG_LSIRDY: LSI oscillator clock ready
-/// @arg    RCC_FLAG_PINRST: Pin reset
-/// @arg    RCC_FLAG_PORRST: POR/PDR reset
-/// @arg    RCC_FLAG_SFTRST: Software reset
-/// @arg    RCC_FLAG_IWDGRST: Independent Watchdog reset
-/// @arg    RCC_FLAG_WWDGRST: Window Watchdog reset
-/// @arg    RCC_FLAG_LPWRRST: Low Power reset
-/// @retval The new state of flag (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus RCC_GetFlagStatus(RCC_FLAG_TypeDef flag)
-{
-    return ((((flag >> 5) == CR_REG_INDEX) ? RCC->CR : (((flag >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : RCC->CSR)) &
-            (1 << (flag & 0x1F)))
-           ? SET : RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Waits for HSE start-up.
-/// @param  None.
-/// @retval An ErrorStatus enumuration value:
-///         - SUCCESS: HSE oscillator is stable and ready to use
-///         - ERROR: HSE oscillator not yet ready
-////////////////////////////////////////////////////////////////////////////////
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
-    u32 StartUpCounter = 0;
-
-    FlagStatus HSEStatus;
-
-    do {
-        HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
-        StartUpCounter++;
-    } while ((HSEStatus == RESET) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    return (ErrorStatus)(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) ? SUCCESS : ERROR;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Waits for flag start-up.
-/// @param  flag: specifies the flag to check.
-///         This parameter can be one of the following values:
-/// @arg    RCC_FLAG_HSIRDY: HSI oscillator clock ready
-/// @arg    RCC_FLAG_HSERDY: HSE oscillator clock ready
-/// @arg    RCC_FLAG_PLLRDY: PLL clock ready
-/// @arg    RCC_FLAG_LSERDY: LSE oscillator clock ready
-/// @arg    RCC_FLAG_LSIRDY: LSI oscillator clock ready
-/// @arg    RCC_FLAG_PINRST: Pin reset
-/// @arg    RCC_FLAG_PORRST: POR/PDR reset
-/// @arg    RCC_FLAG_SFTRST: Software reset
-/// @arg    RCC_FLAG_IWDGRST: Independent Watchdog reset
-/// @arg    RCC_FLAG_WWDGRST: Window Watchdog reset
-/// @retval An ErrorStatus enumuration value:
-///         - SUCCESS: HSE oscillator is stable and ready to use
-///         - ERROR: HSE oscillator not yet ready
-////////////////////////////////////////////////////////////////////////////////
-ErrorStatus RCC_WaitForFlagStartUp(RCC_FLAG_TypeDef flag)
-{
-    u32 StartUpCounter = 0;
-
-    while (RCC_GetFlagStatus(flag) == RESET) {
-        if (StartUpCounter++ > HSE_STARTUP_TIMEOUT) {
-            return ERROR;
-        }
-    }
-    return SUCCESS;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the Internal High Speed oscillator (HSI).
-/// @param  state: new state of the HSI.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_HSICmd(FunctionalState state)
-{
-    MODIFY_REG(RCC->CR, RCC_CR_HSION, (state << RCC_CR_HSION_Pos));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the system clock (SYSCLK).
-/// @param  sys_clk_source: specifies the clock source used as system
-///         clock. This parameter can be one of the following values:
-/// @arg    RCC_HSI: specifies HSI as system clock
-/// @arg    RCC_HSE: specifies HSE as system clock
-/// @arg    RCC_PLL: specifies PLL as system clock
-/// @arg    RCC_LSI: specifies LSI as system clock
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_SYSCLKConfig(SYSCLK_TypeDef sys_clk_source)
-{
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (sys_clk_source << RCC_CFGR_SW_Pos));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the PLL clock source and DM DN factor.
-///         This function must be used only when the PLL is disabled.
-/// @param  plldn: specifies the PLL multiplication factor.
-///         This parameter can be RCC_PLLMul_x where x:[31:26]
-/// @param  plldm: specifies the PLL Divsior factor.
-///         This parameter can be RCC_Divsior_x where x:[22:20]
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_PLLDMDNConfig(u32 plldn, u32 plldm)
-{
-    MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLL_DN | RCC_PLLCFGR_PLL_DP), ((plldn << RCC_PLLCFGR_PLL_DN_Pos) | (plldm << RCC_PLLCFGR_PLL_DP_Pos)));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the PLL.
-///   The PLL can not be disabled if it is used as system clock.
-/// @param  state: new state of the PLL.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_PLLCmd(FunctionalState state)
-{
-    MODIFY_REG(RCC->CR, RCC_CR_PLLON, (state << RCC_CR_PLLON_Pos));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the PLL clock source and multiplication factor.
-///         This function must be used only when the PLL is disabled.
-/// @param  pll_src: specifies the PLL entry clock source.
-///         This parameter can be one of the following values:
-/// @arg    RCC_HSI_Div4: HSI oscillator clock divided
-///         by 4 selected as PLL clock entry
-/// @arg    RCC_HSE_Div1: HSE oscillator clock selected
-///         as PLL clock entry
-/// @arg    RCC_HSE_Div2: HSE oscillator clock divided
-///         by 2 selected as PLL clock entry
-/// @param  pll_mul: specifies the PLL multiplication factor.
-///         This parameter can be RCC_PLLMul_x where x:[31:26][22:20]
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_PLLConfig(RCC_PLLSource_TypeDef pll_src, RCC_PLLMul_TypeDef pll_mul)
-{
-    const u8 DNDM_Item[] = {0x07, 0x03, 0x05, 0x01, 0x07, 0x01, 0x09, 0x01,  // Frclk*8/4 ; Frclk*6/2 ; Frclk*8/2 ; Frclk*10/2;
-                            0x0B, 0x01, 0x0D, 0x01, 0x0F, 0x01, 0x11, 0x01,  // Frclk*12/2; Frclk*14/2; Frclk*16/2; Frclk*18/2;
-                            0x13, 0x01, 0x15, 0x01, 0x17, 0x01, 0x19, 0x01,  // Frclk*20/2; Frclk*22/2; Frclk*24/2; Frclk*26/2;
-                            0x1B, 0x01, 0x1D, 0x01, 0x1F, 0x01
-                           };             // Frclk*28/2; Frclk*30/2;    // Frclk*32/2;
-    MODIFY_REG(RCC->PLLCFGR, (RCC_PLLCFGR_PLLXTPRE | RCC_PLLCFGR_PLLSRC), pll_src);
-    RCC_PLLDMDNConfig((u32)DNDM_Item[pll_mul >> 17], (u32)DNDM_Item[(pll_mul >> 17) + 1]);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the USB clock (USBCLK).
-/// @param  usb_clk_src: specifies the USB clock source.
-///         This clock is derived from the PLL output.
-///         This parameter can be one of the following values:
-/// @arg    RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
-/// @arg    RCC_USBCLKSource_PLLCLK_Div2: PLL clock divided by 2 selected as USB
-///         clock source
-/// @arg    RCC_USBCLKSource_PLLCLK_Div3: PLL clock divided by 3 selected as USB
-///         clock source
-/// @arg    RCC_USBCLKSource_PLLCLK_Div4: PLL clock divided by 4 selected as USB
-///         clock source
-/// @arg    RCC_USBCLKSource_PLLCLK_Div5: PLL clock divided by 5 selected as USB
-///         clock source
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_USBCLKConfig(RCC_USBCLKSOURCE_TypeDef usb_clk_src)
-{
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (usb_clk_src << RCC_CFGR_USBPRE_Pos));
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the clock source used as system clock.
-/// @param  None.
-/// @retval The clock source used as system clock. The returned value can
-///         be one of the following:
-///         - 0x00: HSI/6 used as system clock
-///         - 0x04: HSE used as system clock
-///         - 0x08: PLL used as system clock
-////////////////////////////////////////////////////////////////////////////////
-u8 RCC_GetSYSCLKSource(void)
-{
-    return ((u8)READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the AHB clock (hclk).
-/// @param  sys_clk: defines the AHB clock divider. This clock is derived
-///                    from the system clock (SYSCLK).
-///         This parameter can be one of the following values:
-/// @arg    RCC_SYSCLK_Div1: AHB clock = SYSCLK
-/// @arg    RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
-/// @arg    RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
-/// @arg    RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
-/// @arg    RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
-/// @arg    RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
-/// @arg    RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
-/// @arg    RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
-/// @arg    RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_HCLKConfig(RCC_AHB_CLK_TypeDef sys_clk)
-{
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, sys_clk);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the Low Speed APB clock (pclk1).
-/// @param  hclk: defines the APB1 clock divider. This clock is derived from
-///                  the AHB clock (hclk).
-///         This parameter can be one of the following values:
-/// @arg    RCC_HCLK_Div1: APB1 clock = hclk
-/// @arg    RCC_HCLK_Div2: APB1 clock = hclk/2
-/// @arg    RCC_HCLK_Div4: APB1 clock = hclk/4
-/// @arg    RCC_HCLK_Div8: APB1 clock = hclk/8
-/// @arg    RCC_HCLK_Div16: APB1 clock = hclk/16
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_PCLK1Config(RCC_APB1_APB2_CLK_TypeDef hclk)
-{
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, hclk);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the High Speed APB clock (pclk2).
-/// @param  hclk: defines the APB2 clock divider. This clock is derived from
-///                  the AHB clock (hclk).
-///         This parameter can be one of the following values:
-/// @arg    RCC_HCLK_Div1: APB2 clock = hclk
-/// @arg    RCC_HCLK_Div2: APB2 clock = hclk/2
-/// @arg    RCC_HCLK_Div4: APB2 clock = hclk/4
-/// @arg    RCC_HCLK_Div8: APB2 clock = hclk/8
-/// @arg    RCC_HCLK_Div16: APB2 clock = hclk/16
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_PCLK2Config(RCC_APB1_APB2_CLK_TypeDef hclk)
-{
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (hclk << 3));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the ADC clock (ADCCLK).
-/// @param  pclk2: defines the ADC clock divider. This clock is derived from
-///                   the APB2 clock (pclk2).
-///         This parameter can be one of the following values:
-/// @arg    RCC_PCLK2_Div2: ADC clock = pclk2/2
-/// @arg    RCC_PCLK2_Div4: ADC clock = pclk2/4
-/// @arg    RCC_PCLK2_Div6: ADC clock = pclk2/6
-/// @arg    RCC_PCLK2_Div8: ADC clock = pclk2/8
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_ADCCLKConfig(RCC_ADCCLKSOURCE_TypeDef pclk2)
-{
-    MODIFY_REG(RCC->CFGR, ADC_CFGR_PRE, pclk2);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the External Low Speed oscillator (LSE).
-/// @param  state: specifies the new state of the LSE.
-///         This parameter can be one of the following values:
-/// @arg    RCC_LSE_OFF: LSE oscillator OFF
-/// @arg    RCC_LSE_ON: LSE oscillator ON
-/// @arg    RCC_LSE_Bypass: LSE oscillator bypassed with external
-///         clock
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_LSEConfig(RCC_LSE_TypeDef state)
-{
-    RCC->BDCR &= ~(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON);
-
-    switch (state) {
-        case RCC_LSE_Bypass:
-            RCC->BDCR |= RCC_BDCR_LSEBYP;
-            RCC->BDCR |= RCC_BDCR_LSEON;
-            break;
-        case RCC_LSE_ON:
-            RCC->BDCR |= RCC_BDCR_LSEON;
-            break;
-        default:
-            break;
-    }
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the RTC clock (RTCCLK).
-///         Once the RTC clock is selected it can be changed unless the
-///         Backup domain is reset.
-/// @param  rtc_clk_src: specifies the RTC clock source.
-///         This parameter can be one of the following values:
-/// @arg    RCC_RTCCLKSource_LSE: LSE selected as RTC clock
-/// @arg    RCC_RTCCLKSource_LSI: LSI selected as RTC clock
-/// @arg    RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
-///         selected as RTC clock
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_RTCCLKConfig(RCC_RTCCLKSOURCE_TypeDef rtc_clk_src)
-{
-    MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, rtc_clk_src);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the RTC clock.
-///         This function must be used only after the RTC clock was
-///         selected using the RCC_RTCCLKConfig function.
-/// @param  state: new state of the RTC clock.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_RTCCLKCmd(FunctionalState state)
-{
-    MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCEN, (state << RCC_BDCR_RTCEN_Pos));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the Internal Low Speed oscillator (LSI).
-///         LSI can not be disabled if the IWDG is running.
-/// @param  state: new state of the LSI.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_LSICmd(FunctionalState state)
-{
-//    u32 j;
-    MODIFY_REG(RCC->CSR, RCC_CSR_LSION | RCC_CSR_LSIOENLV, RCC_CSR_LSIOENLV | (state << RCC_CSR_LSION_Pos));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the clock frequency of different on chip clocks.
-/// @param  None.
-/// @retval sys_clk : System clock frequency
-////////////////////////////////////////////////////////////////////////////////
-u32 RCC_GetSysClockFreq(void)
-{
-    u32 result;
-    u32 clock, mul, div;
-    switch (RCC->CFGR & RCC_CFGR_SWS) {
-        case RCC_CFGR_SWS_LSI:
-            result = LSI_VALUE;
-            break;
-
-        case RCC_CFGR_SWS_HSE:
-            result = HSE_VALUE;
-            break;
-
-        case RCC_CFGR_SWS_PLL:
-            clock = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) ? (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLXTPRE) ? (HSE_VALUE >> 1) : HSE_VALUE)
-                    : HSI_VALUE_PLL_ON;
-            mul = ((RCC->PLLCFGR & (u32)RCC_PLLCFGR_PLL_DN) >> RCC_PLLCFGR_PLL_DN_Pos) + 1;
-            div = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL_DP) >> RCC_PLLCFGR_PLL_DP_Pos) + 1;
-
-            result = clock * mul / div;
-            break;
-        default:
-            result =  HSI_VALUE;
-            break;
-    }
-    return result;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the hclk frequency of different on chip clocks.
-/// @param  None.
-/// @retval hclk frequency
-////////////////////////////////////////////////////////////////////////////////
-u32 RCC_GetHCLKFreq(void)
-{
-    return (RCC_GetSysClockFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the pclk1 frequency of different on chip clocks.
-/// @param  None.
-/// @retval pclk1 frequency
-////////////////////////////////////////////////////////////////////////////////
-u32 RCC_GetPCLK1Freq(void)
-{
-    return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the pclk2 frequency of different on chip clocks.
-/// @param  None.
-/// @retval pclk2 frequency
-////////////////////////////////////////////////////////////////////////////////
-u32 RCC_GetPCLK2Freq(void)
-{
-    return (RCC_GetHCLKFreq() >> tbPresc[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the frequency of different on chip clocks.
-/// @param  clk: pointer to a RCC_ClocksTypeDef structure which
-///   will hold the clocks frequency.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* clk)
-{
-    u8 tbADCPresc[] = {2, 4, 6, 8};
-
-    clk->SYSCLK_Frequency = RCC_GetSysClockFreq();
-    clk->HCLK_Frequency   = RCC_GetHCLKFreq();
-    clk->PCLK1_Frequency  = RCC_GetPCLK1Freq();
-    clk->PCLK2_Frequency  = RCC_GetPCLK2Freq();
-
-    clk->ADCCLK_Frequency = clk->PCLK2_Frequency / tbADCPresc[(RCC->CFGR & ADC_CFGR_PRE) >> ADC_CFGR_PRE_Pos];
-
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the AHB peripheral clock.
-/// @param  ahb_periph: specifies the AHB peripheral to gates its clock.
-///   This parameter can be any combination of the following values:
-/// @param  state: new state of the specified peripheral clock.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_AHBPeriphClockCmd(u32 ahb_periph, FunctionalState state)
-{
-    (state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph);
-}
-/// @param  state: new state of the specified peripheral clock.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_AHB2PeriphClockCmd(u32 ahb_periph, FunctionalState state)
-{
-    (state) ? (RCC->AHB2ENR |= ahb_periph) : (RCC->AHB2ENR &= ~ahb_periph);
-}
-/// @param  state: new state of the specified peripheral clock.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_AHB3PeriphClockCmd(u32 ahb_periph, FunctionalState state)
-{
-    (state) ? (RCC->AHB3ENR |= ahb_periph) : (RCC->AHB3ENR &= ~ahb_periph);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
-/// @param  apb2_periph: specifies the APB2 peripheral to gates its
-///   clock.
-///   This parameter can be any combination of the following values:
-/// @param  state: new state of the specified peripheral clock.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_APB2PeriphClockCmd(u32 apb2_periph, FunctionalState state)
-{
-    (state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
-/// @param  apb1_periph: specifies the APB1 peripheral to gates its
-///   clock.
-///   This parameter can be any combination of the following values:
-/// @param  state: new state of the specified peripheral clock.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_APB1PeriphClockCmd(u32 apb1_periph, FunctionalState state)
-{
-    (state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases High Speed APB (APB2) peripheral reset.
-/// @param  apb2_periph: specifies the APB2 peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @param  state: new state of the specified peripheral reset.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_APB2PeriphResetCmd(u32 apb2_periph, FunctionalState state)
-{
-    (state) ? (RCC->APB2RSTR |= apb2_periph) : (RCC->APB2RSTR &= ~apb2_periph);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
-/// @param  apb1_periph: specifies the APB1 peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @param  state: new state of the specified peripheral clock.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_APB1PeriphResetCmd(u32 apb1_periph, FunctionalState state)
-{
-    (state) ? (RCC->APB1RSTR |= apb1_periph) : (RCC->APB1RSTR &= ~apb1_periph);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases Low Speed AHB peripheral reset.
-/// @param  ahb_periph: specifies the AHB peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @param  state: new state of the specified peripheral clock.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_AHBPeriphResetCmd(u32 ahb_periph, FunctionalState state)
-{
-    (state) ? (RCC->AHBRSTR |= ahb_periph) : (RCC->AHBRSTR &= ~ahb_periph);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases Low Speed AHB2 peripheral reset.
-/// @param  ahb_periph: specifies the AHB peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @param  state: new state of the specified peripheral clock.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_AHB2PeriphResetCmd(u32 ahb_periph, FunctionalState state)
-{
-    (state) ? (RCC->AHB2RSTR |= ahb_periph) : (RCC->AHB2RSTR &= ~ahb_periph);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases Low Speed AHB2 peripheral reset.
-/// @param  ahb_periph: specifies the AHB peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @param  state: new state of the specified peripheral clock.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_AHB3PeriphResetCmd(u32 ahb_periph, FunctionalState state)
-{
-    (state) ? (RCC->AHB3RSTR |= ahb_periph) : (RCC->AHB3RSTR &= ~ahb_periph);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases the Backup domain reset.
-/// @param  state: new state of the Backup domain reset.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_BackupResetCmd(FunctionalState state)
-{
-    MODIFY_REG(RCC->BDCR, RCC_BDCR_BDRST, (state << RCC_BDCR_BDRST_Pos));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the Clock Security System.
-/// @param  state: new state of the Clock Security System..
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_ClockSecuritySystemCmd(FunctionalState state)
-{
-    MODIFY_REG(RCC->CR, RCC_CR_CSSON, (state << RCC_CR_CSSON_Pos));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the clock source to output on MCO pin.
-/// @param  mco_src: specifies the clock source to output.
-///   This parameter can be one of the following values:
-/// @arg RCC_MCO_NoClock: No clock selected
-/// @arg RCC_MCO_LSI: LSI oscillator clock selected
-/// @arg RCC_MCO_LSE: LSE oscillator clock selected
-/// @arg RCC_MCO_SYSCLK: System clock selected
-/// @arg RCC_MCO_HSI: HSI oscillator clock selected
-/// @arg RCC_MCO_HSE: HSE oscillator clock selected
-/// @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_MCOConfig(RCC_MCO_TypeDef mco_src)
-{
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, mco_src);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the RCC reset flags.
-///   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
-///   RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
-///   RCC_FLAG_LPWRRST
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_ClearFlag(void)
-{
-    SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified RCC interrupts.
-/// @param  it: specifies the RCC interrupt sources to be enabled or
-/// disabled.
-///   This parameter can be any combination of the following values:
-/// @arg RCC_IT_LSIRDY: LSI ready interrupt
-/// @arg RCC_IT_LSERDY: LSE ready interrupt
-/// @arg RCC_IT_HSIRDY: HSI ready interrupt
-/// @arg RCC_IT_HSERDY: HSE ready interrupt
-/// @arg RCC_IT_PLLRDY: PLL ready interrupt
-/// @param  state: new state of the specified RCC interrupts.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_ITConfig(RCC_IT_TypeDef it, FunctionalState state)
-{
-    (state) ? SET_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos) : CLEAR_BIT(RCC->CIR, it << RCC_CIR_LSIRDYIE_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified RCC interrupt has occurred or not.
-/// @param  it: specifies the RCC interrupt source to check.
-///   This parameter can be one of the following values:
-/// @arg RCC_IT_LSIRDY: LSI ready interrupt
-/// @arg RCC_IT_LSERDY: LSE ready interrupt
-/// @arg RCC_IT_HSIRDY: HSI ready interrupt
-/// @arg RCC_IT_HSERDY: HSE ready interrupt
-/// @arg RCC_IT_PLLRDY: PLL ready interrupt
-/// @arg RCC_IT_CSS: Clock Security System interrupt
-/// @retval The new state of it (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus RCC_GetITStatus(RCC_IT_TypeDef it)
-{
-    return (ITStatus)READ_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYF_Pos));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the RCC�?interrupt pending bits.
-/// @param  it: specifies the interrupt pending bit to clear.
-///   This parameter can be any combination of the following values:
-/// @arg RCC_IT_LSIRDY: LSI ready interrupt
-/// @arg RCC_IT_LSERDY: LSE ready interrupt
-/// @arg RCC_IT_HSIRDY: HSI ready interrupt
-/// @arg RCC_IT_HSERDY: HSE ready interrupt
-/// @arg RCC_IT_PLLRDY: PLL ready interrupt
-/// @arg RCC_IT_CSS: Clock Security System interrupt
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_ClearITPendingBit(u8 it)
-{
-    SET_BIT(RCC->CIR, (it << RCC_CIR_LSIRDYC_Pos));
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
-/// @param  apb1_periph: specifies the APB1 peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_APB1PeriphReset(u32 apb1_periph)
-{
-    RCC->APB1RSTR |= apb1_periph;
-    RCC->APB1RSTR &= ~apb1_periph;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases Low Speed APB (APB2) peripheral reset.
-/// @param  apb2_periph: specifies the APB2 peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_APB2PeriphReset(u32 apb2_periph)
-{
-    RCC->APB2RSTR |= apb2_periph;
-    RCC->APB2RSTR &= ~apb2_periph;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases High Speed AHB (AHB1) peripheral reset.
-/// @param  ahb1_periph: specifies the AHB1 peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_AHBPeriphReset(u32 ahb1_periph)
-{
-    RCC->AHBRSTR |= ahb1_periph;
-    RCC->AHBRSTR &= ~ahb1_periph;
-}
-////////////////////////////////////////////////////////////////////////////////
-//
-//  New Function Interface
-//
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
-/// @param  apb1_periph: specifies the APB1 peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exRCC_APB1PeriphReset(u32 apb1_periph)
-{
-    RCC->APB1RSTR |= apb1_periph;
-    RCC->APB1RSTR &= ~apb1_periph;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief
-/// @param
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exRCC_BackupReset()
-{
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases High Speed APB (APB2) peripheral reset.
-/// @param  apb2_periph: specifies the APB2 peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exRCC_APB2PeriphReset(u32 apb2_periph)
-{
-    RCC->APB2RSTR |= apb2_periph;
-    RCC->APB2RSTR &= ~apb2_periph;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces or releases High Speed AHB (AHB1) peripheral reset.
-/// @param  ahb1_periph: specifies the AHB1 peripheral to reset.
-///   This parameter can be any combination of the following values:
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exRCC_AHBPeriphReset(u32 ahb1_periph)
-{
-    RCC->AHBRSTR |= ahb1_periph;
-    RCC->AHBRSTR &= ~ahb1_periph;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Disable systick
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exRCC_SystickDisable()
-{
-    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enable systick
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exRCC_SystickEnable(u32 sys_tick_period)
-{
-    SysTick_Config(RCC_GetHCLKFreq() / 1000000 * sys_tick_period);
-}
-
-/*
-(state) ? (RCC->AHBENR |= ahb_periph) : (RCC->AHBENR &= ~ahb_periph);
-(state) ? (RCC->APB1ENR |= apb1_periph) : (RCC->APB1ENR &= ~apb1_periph);
-(state) ? (RCC->APB2ENR |= apb2_periph) : (RCC->APB2ENR &= ~apb2_periph);
-*/
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified ADC peripheral Clock.
-/// @param  peripheral:select the ADC peripheral.
-/// @param  state: new state of the ADC peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_ADC_ClockCmd(ADC_TypeDef* peripheral, FunctionalState state)
-{
-    switch (*(vu32*)&peripheral) {
-
-        case ADC1_BASE:
-            (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC1) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC1);
-            break;
-        case ADC2_BASE:
-            (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC2) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC2);
-            break;
-        case ADC3_BASE:
-            (state) ? (RCC->APB2ENR |= RCC_APB2ENR_ADC3) : (RCC->APB2ENR &= ~RCC_APB2ENR_ADC3);
-            break;
-        default:
-            break;
-    }
-
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified BKP peripheral Clock.
-/// @param  peripheral:select the BKP peripheral.
-/// @param  state: new state of the BKP peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_BKP_ClockCmd(BKP_TypeDef* peripheral, FunctionalState state)
-{
-    if(BKP == peripheral) {
-        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_BKP) : (RCC->APB1ENR &= ~RCC_APB1ENR_BKP);
-        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_PWR) : (RCC->APB1ENR &= ~RCC_APB1ENR_PWR);
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified CAN peripheral Clock.
-/// @param  peripheral:select the CAN peripheral.
-/// @param  state: new state of the CAN peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_CAN_ClockCmd(CAN_TypeDef* peripheral, FunctionalState state)
-{
-    if(CAN1 == peripheral) {
-        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_CAN) : (RCC->APB1ENR &= ~RCC_APB1ENR_CAN);
-    }
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified COMP peripheral Clock.
-/// @param  peripheral:select the COMP peripheral.
-/// @param  state: new state of the COMP peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_COMP_ClockCmd(COMP_TypeDef* peripheral, FunctionalState state)
-{
-    if(COMP == peripheral) {
-        (state) ? (RCC->APB2ENR |= RCC_APB2ENR_COMP) : (RCC->APB2ENR &= ~RCC_APB2ENR_COMP);
-    }
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified CRC peripheral Clock.
-/// @param  peripheral:select the CRC peripheral.
-/// @param  state: new state of the CRC peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_CRC_ClockCmd(CRC_TypeDef* peripheral, FunctionalState state)
-{
-    if(CRC == peripheral) {
-        (state) ? (RCC->AHBENR |= RCC_AHBENR_CRC) : (RCC->AHBENR &= ~RCC_AHBENR_CRC);
-    }
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified DAC peripheral Clock.
-/// @param  peripheral:select the DAC peripheral.
-/// @param  state: new state of the DAC peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_DAC_ClockCmd(DAC_TypeDef* peripheral, FunctionalState state)
-{
-    if(DAC == peripheral) {
-        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_DAC) : (RCC->APB1ENR &= ~RCC_APB1ENR_DAC);
-    }
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified DMA peripheral Clock.
-/// @param  peripheral:select the DMA peripheral.
-/// @param  state: new state of the DMA peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_DMA_ClockCmd(DMA_TypeDef* peripheral, FunctionalState state)
-{
-    if(DMA1 == peripheral) {
-        (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA1) : (RCC->AHBENR &= ~RCC_AHBENR_DMA1);
-    }
-    if(DMA2 == peripheral) {
-        (state) ? (RCC->AHBENR |= RCC_AHBENR_DMA2) : (RCC->AHBENR &= ~RCC_AHBENR_DMA2);
-    }
-}
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified GPIO peripheral Clock.
-/// @param  peripheral:select the GPIO peripheral.
-/// @param  state: new state of the GPIO peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_GPIO_ClockCmd(GPIO_TypeDef* peripheral, FunctionalState state)
-{
-    switch (*(vu32*)&peripheral) {
-        case (u32)GPIOA:
-            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOA) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOA);
-            break;
-        case (u32)GPIOB:
-            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOB) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOB);
-            break;
-        case (u32)GPIOC:
-            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOC) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOC);
-            break;
-        case (u32)GPIOD:
-            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOD) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOD);
-            break;
-        case (u32)GPIOE:
-            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOE) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOE);
-            break;
-        case (u32)GPIOF:
-            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOF) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOF);
-            break;
-        case (u32)GPIOG:
-            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOG) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOG);
-            break;
-        case (u32)GPIOH:
-            (state) ? (RCC->AHBENR |= RCC_AHBENR_GPIOH) : (RCC->AHBENR &= ~RCC_AHBENR_GPIOH);
-            break;
-        default:
-            break;
-    }
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the uart peripheral registers to their
-///         default reset values.
-/// @param  peripheral: Select the UART or the UART peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RCC_UART_ClockCmd(UART_TypeDef* peripheral, FunctionalState state)
-{
-    if(UART2 == peripheral) {
-        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART2) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART2);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART2);
-    }
-    if(UART1 == peripheral) {
-        (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART1) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART1);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART1);
-    }
-    if(UART3 == peripheral) {
-        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART3) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART3);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART3);
-    }
-    if(UART4 == peripheral) {
-        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART4) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART4);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART4);
-    }
-    if(UART5 == peripheral) {
-        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART5) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART5);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART5);
-    }
-    if(UART6 == peripheral) {
-        (state) ? (RCC->APB2ENR |= RCC_APB2ENR_UART6) : (RCC->APB2ENR &= ~RCC_APB2ENR_UART6);//exRCC_APB2PeriphReset(RCC_APB2ENR_UART6);
-    }
-    if(UART7 == peripheral) {
-        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART7) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART7);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART7);
-    }
-    if(UART8 == peripheral) {
-        (state) ? (RCC->APB1ENR |= RCC_APB1ENR_UART8) : (RCC->APB1ENR &= ~RCC_APB1ENR_UART8);//exRCC_APB1PeriphReset(RCC_APB1ENR_UART8);
-    }
-}
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c
deleted file mode 100644
index b02c6750b..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rtc.c
+++ /dev/null
@@ -1,234 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_rtc.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE RTC FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_RTC_C_
-
-// Files includes
-#include "hal_rtc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup RTC_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup RTC_Exported_Functions
-/// @{
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified RTC interrupts.
-/// @param  it: specifies the RTC interrupts sources to be enabled or
-///         disabled.
-///         This parameter can be any combination of the following values:
-/// @arg    RTC_IT_OW: Overflow interrupt
-/// @arg    RTC_IT_ALR: Alarm interrupt
-/// @arg    RTC_IT_SEC: Second interrupt
-/// @param  state: new state of the specified RTC interrupts.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RTC_ITConfig(RTC_IT_TypeDef it, FunctionalState state)
-{
-    (state == ENABLE) ? (RTC->CR |= it) : (RTC->CR &= (u16)~it);
-//    RTC_WaitForLastTask();
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enters the RTC configuration mode.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RTC_EnterConfigMode(void)
-{
-//    PWR->CR |= PWR_CR_DBP;
-    RTC->CSR |= RTC_CSR_CNF;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Exits from the RTC configuration mode.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RTC_ExitConfigMode(void)
-{
-    RTC->CSR &= ~RTC_CSR_CNF;
-    while (!(RTC->CSR & RTC_CSR_RTOFF));
-//    PWR->CR  &= ~PWR_CR_DBP;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Gets the RTC counter value.
-/// @param  None.
-/// @retval RTC counter value.
-////////////////////////////////////////////////////////////////////////////////
-u32 RTC_GetCounter(void)
-{
-    u32 dat = RTC->CNTH << 16;
-    return (RTC->CNTL | dat);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the RTC counter value.
-/// @param  count: RTC counter new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RTC_SetCounter(u32 count)
-{
-    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
-    RTC->CNTH = count >> 16;
-    RTC->CNTL = count;
-    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
-//    while (!(RTC->CSR & RTC_CSR_RTOFF));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the RTC prescaler value.
-/// @param  prescaler: RTC prescaler new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RTC_SetPrescaler(u32 prescaler)
-{
-    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
-    RTC->PRLH = prescaler >> 16;
-    RTC->PRLL = prescaler;
-    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
-//    while (!(RTC->CSR & RTC_CSR_RTOFF));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the RTC alarm value.
-/// @param  alarm: RTC alarm new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RTC_SetAlarm(u32 alarm)
-{
-    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
-    RTC->ALRH = alarm >> 16;
-    RTC->ALRL = alarm;
-    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
-//    while (!(RTC->CSR & RTC_CSR_RTOFF));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Gets the RTC divider value.
-/// @param  None.
-/// @retval RTC Divider value.
-////////////////////////////////////////////////////////////////////////////////
-u32 RTC_GetDivider(void)
-{
-    u32 dat = ((u32)(RTC->DIVH & RTC_DIVH_DIV) << 16);
-    return (RTC->DIVL | dat);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Waits until last write operation on RTC registers has finished.
-/// @note   This function must be called before any write to RTC registers.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RTC_WaitForLastTask(void)
-{
-    while (!(RTC->CSR & RTC_CSR_RTOFF));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
-///         are synchronized with RTC APB clock.
-/// @note   This function must be called before any read operation after an APB
-///         reset or an APB clock stop.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RTC_WaitForSynchro(void)
-{
-    RTC->CSR &= ~RTC_CSR_RSF;
-    while (!(RTC->CSR & RTC_CSR_RSF));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified RTC flag is set or not.
-/// @param  flag: specifies the flag to check.
-///         This parameter can be one the following values:
-/// @arg    RTC_FLAG_RTOFF: RTC Operation OFF flag
-/// @arg    RTC_FLAG_RSF: Registers Synchronized flag
-/// @arg    RTC_FLAG_OW: Overflow flag
-/// @arg    RTC_FLAG_ALR: Alarm flag
-/// @arg    RTC_FLAG_SEC: Second flag
-/// @retval The state of RTC_FLAG (SET or RESET).
-/////////////////////////////////////////////////////////////////////////////////
-FlagStatus RTC_GetFlagStatus(RTC_FLAG_TypeDef flag)
-{
-    return  (FlagStatus)(RTC->CSR & flag);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the RTC's pending flags.
-/// @param  flag: specifies the flag to clear.
-///         This parameter can be any combination of the following values:
-/// @arg    RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only
-///         after an APB reset or an APB Clock stop.
-/// @arg    RTC_FLAG_OW: Overflow flag
-/// @arg    RTC_FLAG_ALR: Alarm flag
-/// @arg    RTC_FLAG_SEC: Second flag
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RTC_ClearFlag(RTC_FLAG_TypeDef flag)
-{
-    RTC->CSR &= ~flag;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified RTC interrupt has occurred or not.
-/// @param  it: specifies the RTC interrupts sources to check.
-///         This parameter can be one of the following values:
-/// @arg    RTC_IT_OW: Overflow interrupt
-/// @arg    RTC_IT_ALR: Alarm interrupt
-/// @arg    RTC_IT_SEC: Second interrupt
-/// @retval The state of the RTC_IT (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus RTC_GetITStatus(RTC_IT_TypeDef it)
-{
-    return  (ITStatus)(RTC->CSR & it);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the RTC's interrupt pending bits.
-/// @param  it: specifies the interrupt pending bit to clear.
-///         This parameter can be any combination of the following values:
-/// @arg    RTC_IT_OW: Overflow interrupt
-/// @arg    RTC_IT_ALR: Alarm interrupt
-/// @arg    RTC_IT_SEC: Second interrupt
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void RTC_ClearITPendingBit(RTC_IT_TypeDef it)
-{
-//    RTC_EnterConfigMode();//RTC->CSR |= RTC_CSR_CNF;
-    RTC->CSR &= ~it;
-//    RTC_ExitConfigMode();//RTC->CSR &= ~RTC_CSR_CNF;
-}
-
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c
deleted file mode 100644
index 4b1bd70ee..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_sdio.c
+++ /dev/null
@@ -1,527 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_sdio.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE SDIO FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_SDIO_C_
-#include "reg_sdio.h"
-#include "hal_sdio.h"
-#include "hal_rcc.h"
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup SDIO_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup SDIO_Exported_Functions
-/// @{
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the SDIO peripheral registers to their default reset
-///         values.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_DeInit(void)
-{
-    RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, ENABLE);
-    RCC_AHBPeriphResetCmd(RCC_AHBRSTR_SDIO, DISABLE);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each SDIO_InitStruct member with its default value.
-/// @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
-///         will be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
-{
-    // SDIO_InitStruct members default value
-    SDIO_InitStruct->SDIO_MDEN = 0;
-    SDIO_InitStruct->SDIO_DATWT = 0;
-    SDIO_InitStruct->SDIO_SelPTSM = 0;
-    SDIO_InitStruct->SDIO_CLKSP = 0;
-    SDIO_InitStruct->SDIO_OUTM = 0;
-    SDIO_InitStruct->SDIO_SelSM = 0;
-    SDIO_InitStruct->SDIO_OPMSel = 0;
-}
-
-
-///
-/// @brief  Fills each SDIO_DataInitStruct member with its default value.
-/// @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
-///         will be initialized.
-/// @retval None
-///
-void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
-    /* SDIO_DataInitStruct members default value */
-    SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
-    SDIO_DataInitStruct->SDIO_DataLength = 0x00;
-    SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
-    SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
-//    SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
-//    SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
-}
-
-///
-/// @brief  Initializes the SDIO data path according to the specified
-///   parameters in the SDIO_DataInitStruct.
-/// @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
-///   contains the configuration information for the SDIO command.
-/// @retval None
-///
-//void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-//{
-//    u32 tmpreg = 0;
-
-//    /*---------------------------- SDIO DTIMER Configuration ---------------------*/
-//    /* Set the SDIO Data TimeOut value */
-//    SDIO->MMC_TIMEOUTCNT = SDIO_DataInitStruct->SDIO_DataTimeOut;
-
-//    /*---------------------------- SDIO DLEN Configuration -----------------------*/
-//    /* Set the SDIO DataLength value */
-//    SDIO->MMC_BYTECNTL = SDIO_DataInitStruct->SDIO_DataLength;
-
-//    /*---------------------------- SDIO DCTRL Configuration ----------------------*/
-//    /* Get the SDIO DCTRL value */
-//    tmpreg = SDIO->DCTRL;
-//    /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
-//    tmpreg &= DCTRL_CLEAR_MASK;
-//    /* Set DEN bit according to SDIO_DPSM value */
-//    /* Set DTMODE bit according to SDIO_TransferMode value */
-//    /* Set DTDIR bit according to SDIO_TransferDir value */
-//    /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
-//    tmpreg |= (u32)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir;//
-//              //| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
-
-//    /* Write to SDIO DCTRL */
-//    SDIO->DCTRL = tmpreg;
-//}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  The frequency division factor is configured to generate the SDIO clock.
-/// @param  value : 1MHz = Fhclk/((mmc_cardsel[5 : 0] + 1) × 2)
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_ClockSet(u32 value)
-{
-//    SDIO->MMC_CARDSEL &= ~SDIO_MMC_CARDSEL_MASK;
-    SDIO->MMC_CARDSEL = (SDIO_MMC_CARDSEL_CTREN | SDIO_MMC_CARDSEL_ENPCLK | (value & 0x3F));
-//    SDIO->MMC_CARDSEL = 0xC0+0x2F;//0xdf;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the SDIO peripheral according to the specified
-///         parameters in the SDIO_InitStruct.
-/// @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
-///         that contains the configuration information for the SDIO peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
-{
-    SDIO->MMC_CTRL &= 0x700;
-    SDIO->MMC_CTRL |= (SDIO_InitStruct->SDIO_OPMSel | SDIO_InitStruct->SDIO_SelSM |
-                       SDIO_InitStruct->SDIO_OUTM | SDIO_InitStruct->SDIO_CLKSP |
-                       SDIO_InitStruct->SDIO_SelPTSM | SDIO_InitStruct->SDIO_DATWT |
-                       SDIO_InitStruct->SDIO_MDEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the SDIO interrupts.
-/// @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
-///         state  : new state of the specified SDIO interrupts.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_ITConfig(u32 SDIO_IT, FunctionalState state)
-{
-    (state) ?  (SDIO->MMC_INT_MASK |= SDIO_IT) : (SDIO->MMC_INT_MASK &= ~SDIO_IT);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the SDIO CRC.
-/// @param  SDIO_CRC: specifies the SDIO CRC sources to be enabled or disabled.
-///         state   : new state of the specified SDIO CRC.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_CRCConfig(u32 SDIO_CRC, FunctionalState state)
-{
-    (state) ?  (SDIO->MMC_CRCCTL |= SDIO_CRC) : (SDIO->MMC_CRCCTL &= ~SDIO_CRC);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Port transfer speed mode.
-/// @param  clkdiv : High/low speed.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_Clock_Set(u8 clkdiv)
-{
-    SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM;
-    (clkdiv) ? (SDIO->MMC_CTRL |= SDIO_MMC_CTRL_SelPTSM) : (SDIO->MMC_CTRL &= ~SDIO_MMC_CTRL_SelPTSM);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Turn off the SDIO switch.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-SD_Error SD_PowerOFF(void)
-{
-    SDIO->MMC_CARDSEL &= ~(SDIO_MMC_CARDSEL_ENPCLK | SDIO_MMC_CARDSEL_CTREN);
-    return SD_OK;
-}
-///
-/// @brief  Fills each SDIO_CmdInitStruct member with its default value.
-/// @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
-///         structure which will be initialized.
-/// @retval None
-///
-void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
-{
-    /* SDIO_CmdInitStruct members default value */
-    SDIO_CmdInitStruct->SDIO_Argument = 0x00;
-    SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
-    SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
-    SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
-//    SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SDIO sends command functions.
-/// @param  cmdindex : Type the command.
-///         waitrsp  : Expected correspondence.
-///         arg      : parameter.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_Send_Cmd(u8 cmdindex, u8 waitrsp, u32 arg)
-{
-    SDIO->CMD_BUF0 = (arg >> 0) & 0xFF;
-    SDIO->CMD_BUF1 = (arg >> 8) & 0xFF;
-    SDIO->CMD_BUF2 = (arg >> 16) & 0xFF;
-    SDIO->CMD_BUF3 = (arg >> 24) & 0xFF;
-    SDIO->CMD_BUF4 = 0x40 | cmdindex;
-    SDIO->CLR_MMC_INT |= 0;
-    SDIO->MMC_IO = SDIO_MMC_IO_AUTOTR;
-    while(1) {
-        if(SDIO->CLR_MMC_INT & SDIO_CLR_MMC_INT_CMDDMC) {
-            SDIO->CLR_MMC_INT |= SDIO_CLR_MMC_INT_CMDDMC;
-            break;
-        }
-    }
-    if(waitrsp == SDIO_Response_Short) {
-        SDIO->MMC_IO =  SDIO_MMC_IO_AUTOCLKG | \
-                        SDIO_MMC_IO_AUTOTR | \
-                        SDIO_MMC_IO_RESPCMDSEL;
-    }
-    else if(waitrsp == SDIO_Response_Long) {
-        SDIO->MMC_IO =  SDIO_MMC_IO_AUTOCLKG | \
-                        SDIO_MMC_IO_AUTOTR | \
-                        SDIO_MMC_IO_RESPCMDSEL | \
-                        SDIO_MMC_IO_CID_CSDRD;
-    }
-    else {
-    }
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Check the execution status of CMD0.
-/// @param  None.
-/// @retval card error code.
-////////////////////////////////////////////////////////////////////////////////
-SD_Error CmdError(void)
-{
-    SD_Error errorstatus = SD_OK;
-    u32 timeout = SDIO_CMD0TIMEOUT;
-    while (timeout--) {
-        if(((SDIO->MMC_IO & SDIO_MMC_IO_RESPCMDSEL) == 0) && ((SDIO->MMC_IO & SDIO_MMC_IO_AUTOTR) == 0))
-            break;
-    }
-    if (timeout == 0)
-        return SD_CMD_RSP_TIMEOUT;
-    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
-    return errorstatus;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Check the error status of the R1 response.
-/// @param  cmd : Current command.
-/// @retval card error code.
-////////////////////////////////////////////////////////////////////////////////
-SD_Error CmdResp1Error(u8 cmd)
-{
-    u32 status;
-    u32 response;
-    while(1) {
-        status = SDIO->CLR_MMC_INT ;
-        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
-            break;
-    }
-    if(status & SDIO_CLR_MMC_INT_CRNTMC) {
-        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
-        return SD_CMD_RSP_TIMEOUT;
-    }
-    if(status & (SDIO_CLR_MMC_INT_CRCEMC)) {
-        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
-        return SD_CMD_CRC_FAIL;
-    }
-    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
-
-    if((SDIO->CMD_BUF4 & 0x3F) != cmd) {
-        return SD_ILLEGAL_CMD;
-    }
-    response = SDIO->CMD_BUF3 << 24  | SDIO->CMD_BUF2 << 16  | SDIO->CMD_BUF1 << 8  | SDIO->CMD_BUF0;
-    return (SD_Error)(response & SD_OCR_ERRORBITS);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Check the execution status of CMD2.
-/// @param  None.
-/// @retval card error code.
-////////////////////////////////////////////////////////////////////////////////
-SD_Error CmdResp2Error(void)
-{
-    SD_Error errorstatus = SD_OK;
-    u32 status;
-    u32 timeout = SDIO_CMD0TIMEOUT;
-    while(timeout--) {
-        status = SDIO->CLR_MMC_INT ;
-        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
-            break;
-    }
-    if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) {
-        errorstatus = SD_CMD_RSP_TIMEOUT;
-        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
-        return errorstatus;
-    }
-    if(status & SDIO_CLR_MMC_INT_CRCEMC) {
-        errorstatus = SD_CMD_CRC_FAIL;
-        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
-    }
-    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
-    return errorstatus;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Check the execution status of CMD3.
-/// @param  None.
-/// @retval card error code.
-////////////////////////////////////////////////////////////////////////////////
-SD_Error CmdResp3Error(void)
-{
-    u32 status;
-    while(1) {
-        status = SDIO->CLR_MMC_INT ;
-        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
-            break;
-    }
-    if(status & SDIO_CLR_MMC_INT_CRNTMC) {
-        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
-        return SD_CMD_RSP_TIMEOUT;
-    }
-    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
-    return SD_OK;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Check the execution status of CMD6.
-/// @param  None.
-/// @retval card error code.
-////////////////////////////////////////////////////////////////////////////////
-SD_Error CmdResp6Error(u8 cmd, u16* prca)
-{
-    SD_Error errorstatus = SD_OK;
-    u32 status;
-    u32 rspr1;
-    while(1) {
-        status = SDIO->CLR_MMC_INT ;
-        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
-            break;
-    }
-    if(status & SDIO_CLR_MMC_INT_CRNTMC) {
-        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
-        return SD_CMD_RSP_TIMEOUT;
-    }
-    if(status & SDIO_CLR_MMC_INT_CRCEMC) {
-        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRCEMC;
-        return SD_CMD_CRC_FAIL;
-    }
-    if((SDIO->CMD_BUF4 & 0x3F) != cmd) {
-        return SD_ILLEGAL_CMD;
-    }
-    SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_MASK;
-    rspr1 = SDIO->CMD_BUF3 << 24  | SDIO->CMD_BUF2 << 16  | SDIO->CMD_BUF1 << 8  | SDIO->CMD_BUF0;
-    if(SD_ALLZERO == (rspr1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED))) {
-        *prca = (u16)(rspr1 >> 16);
-        return errorstatus;
-    }
-    if(rspr1 & SD_R6_GENERAL_UNKNOWN_ERROR) {
-        return SD_GENERAL_UNKNOWN_ERROR;
-    }
-    if(rspr1 & SD_R6_ILLEGAL_CMD) {
-        return SD_ILLEGAL_CMD;
-    }
-    if(rspr1 & SD_R6_COM_CRC_FAILED) {
-        return SD_COM_CRC_FAILED;
-    }
-    return errorstatus;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Check the execution status of CMD7.
-/// @param  None.
-/// @retval card error code.
-////////////////////////////////////////////////////////////////////////////////
-SD_Error CmdResp7Error(void)
-{
-    SD_Error errorstatus = SD_OK;
-    u32 status;
-    u32 timeout = SDIO_CMD0TIMEOUT;
-    while(timeout--) {
-        status = SDIO->CLR_MMC_INT ;
-        if(status & (SDIO_CLR_MMC_INT_CRCEMC | SDIO_CLR_MMC_INT_CRNTMC | SDIO_CLR_MMC_INT_CMDDMC))
-            break;
-    }
-    if((timeout == 0) || (status & SDIO_CLR_MMC_INT_CRNTMC)) { //timeout
-        errorstatus = SD_CMD_RSP_TIMEOUT;
-        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CRNTMC;
-        return errorstatus;
-    }
-    if(status & SDIO_CLR_MMC_INT_CMDDMC) {
-        errorstatus = SD_OK;
-        SDIO->CLR_MMC_INT = SDIO_CLR_MMC_INT_CMDDMC;
-    }
-    return errorstatus;
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Write data direction block size configuration.
-/// @param  datatimeout : maximum latency.
-///         datalen     : data len
-///         blksize     : block count.
-///         dir         :  direction
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_Send_Data_Cfg(u32 datatimeout, u32 datalen, u8 blksize, u8 dir)
-{
-    u32 tmpreg, tmpreg1, tmpreg2 = 0;
-    tmpreg = SDIO->MMC_IO_MBCTL;
-    tmpreg1 = SDIO->MMC_IO;
-    tmpreg &= ~(SDIO_MMC_IO_MBCTL_BTSSel | SDIO_MMC_IO_MBCTL_SPMBDTR | SDIO_MMC_IO_MBCTL_SMBDTD);
-    if (datatimeout < 100) {
-        SDIO->MMC_TIMEOUTCNT = datatimeout;
-    }
-    else if (datatimeout < 10000) {
-        SDIO->MMC_TIMEOUTCNT = datatimeout / 100;
-        tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel;
-    }
-    else if (datatimeout < 1000000) {
-        SDIO->MMC_TIMEOUTCNT = datatimeout / 10000;
-        tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel_2;
-    }
-    else {
-        SDIO->MMC_TIMEOUTCNT = datatimeout / 1000000;
-        tmpreg |= SDIO_MMC_IO_MBCTL_BTSSel;
-    }
-    SDIO->MMC_BYTECNTL = datalen & 0x1FFFFFF; ;
-    SDIO->MMC_BLOCKCNT = blksize;
-    if (dir == 0) {
-        tmpreg |= SDIO_MMC_IO_MBCTL_SMBDTD;
-        tmpreg1 |= SDIO_MMC_IO_TRANSFDIR;
-        tmpreg2 |= SDIO_BUF_CTLL_SBAD;
-    }
-    else {
-        tmpreg &= ~(SDIO_MMC_IO_MBCTL_SMBDTD);
-        tmpreg1 &= ~(SDIO_MMC_IO_TRANSFDIR);
-        tmpreg2 &= ~(SDIO_BUF_CTLL_SBAD);
-    }
-    SDIO->MMC_IO_MBCTL = tmpreg;
-    SDIO->MMC_IO = tmpreg1;
-    SDIO->BUF_CTL = tmpreg2;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the SDIO's Flag pending bits.
-/// @param  SDIO_IT: specifies the flag pending bit to clear.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_ClearFlag(u32 SDIO_FLAG)
-{
-    SDIO->CLR_MMC_INT |= SDIO_FLAG;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the SDIO's interrupt pending bits.
-/// @param  SDIO_IT: specifies the interrupt pending bit to clear.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_ClearITPendingBit(u32 SDIO_IT)
-{
-    SDIO->CLR_MMC_INT |= SDIO_IT;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified SDIO flag is set or not.
-/// @param  SDIO_FLAG: specifies the flag to check.
-/// @retval The new state of SDIO_FLAG (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus SDIO_GetFlagStatus(u32 SDIO_FLAG)
-{
-    return ((SDIO->CLR_MMC_INT & SDIO_FLAG) ? SET : RESET);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Reads the value of the data transfer timeout count
-/// @param  None.
-/// @retval timeout count.
-////////////////////////////////////////////////////////////////////////////////
-u32 SDIO_GetTimeOutCounter(void)
-{
-    return (SDIO->MMC_TIMEOUTCNT & 0xFF);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Read one data word from FIFO.
-/// @param  None.
-/// @retval Data received.
-////////////////////////////////////////////////////////////////////////////////
-u32 SDIO_ReadData(void)
-{
-    return SDIO->FIFO;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Write one data word to FIFO.
-/// @param  tempbuff : Write data.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_WriteData(u32 tempbuff)
-{
-    SDIO->FIFO = tempbuff;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns number of remaining data bytes to be transferred.
-/// @param  None
-/// @retval Number of remaining data bytes to be transferred
-////////////////////////////////////////////////////////////////////////////////
-u32 SDIO_GetDataCounter(void)
-{
-    return SDIO->MMC_BYTECNTL;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enable or Dsiable DMA .
-/// @param  tempbuff : Write data.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SDIO_DMACmd(FunctionalState state)
-{
-    (state) ?  ((SDIO->BUF_CTL |= SDIO_BUF_CTLL_DMAHEN), SDIO->BUF_CTL &= (~(SDIO_BUF_CTLL_DRM))) : (SDIO->BUF_CTL &= ~SDIO_BUF_CTLL_DMAHEN);
-}
-
-
-/// @}
-
-/// @}
-
-/// @}
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c
deleted file mode 100644
index 3d8c286a3..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_spi.c
+++ /dev/null
@@ -1,648 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_spi.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE SPI FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_SPI_C_
-#include <math.h>
-// Files includes
-#include "hal_spi.h"
-#include "hal_rcc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup SPI_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-///@addtogroup SPI_Exported_Functions
-///@{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the spi peripheral registers to their
-///         default reset values.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_DeInit(SPI_TypeDef* spi)
-{
-    switch (*(vu32*)&spi) {
-        case (u32)SPI2:  // SPI2_BASE:
-            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, ENABLE);
-            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI2, DISABLE);
-            break;
-        case (u32)SPI3:  // SPI3_BASE:
-            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, ENABLE);
-            RCC_APB1PeriphResetCmd(RCC_APB1ENR_SPI3, DISABLE);
-            break;
-        case (u32)SPI1:  // SPI1_BASE:
-            RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, ENABLE);
-            RCC_APB2PeriphResetCmd(RCC_APB2ENR_SPI1, DISABLE);
-            break;
-        default:
-            break;
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the spi peripheral according to the specified
-///         parameters in the init_struct .
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  init_struct: pointer to a SPI_InitTypeDef structure
-///         that contains the configuration information for the
-///         specified SPI peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_Init(SPI_TypeDef* spi, SPI_InitTypeDef* init_struct)
-{
-    if (init_struct->SPI_DataSize == SPI_DataSize_32b) {
-        SET_BIT(spi->GCR, SPI_GCR_DWSEL);
-    }
-    else {
-        CLEAR_BIT(spi->GCR, SPI_GCR_DWSEL);
-    }
-    MODIFY_REG(spi->GCR, SPI_GCR_NSS, init_struct->SPI_NSS);
-    MODIFY_REG(spi->GCR, SPI_GCR_MODE, init_struct->SPI_Mode);
-    MODIFY_REG(spi->CCR, SPI_CCR_LSBFE, init_struct->SPI_FirstBit);
-    MODIFY_REG(spi->CCR, SPI_CCR_CPOL, init_struct->SPI_CPOL);
-    MODIFY_REG(spi->CCR, SPI_CCR_CPHA, init_struct->SPI_CPHA);
-
-    SET_BIT(spi->CCR, SPI_CCR_SPILEN);
-
-    MODIFY_REG(spi->BRR, BRR_Mask, init_struct->SPI_BaudRatePrescaler);
-
-    if (init_struct->SPI_DataWidth >= 32) {
-        MODIFY_REG(spi->ECR, ECR_Mask, 0);
-    }
-    else {
-        MODIFY_REG(spi->ECR, ECR_Mask, init_struct->SPI_DataWidth);
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param  init_struct: pointer to a SPI_InitTypeDef structure
-///         which will be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_StructInit(SPI_InitTypeDef* init_struct)
-{
-    init_struct->SPI_Mode              = SPI_Mode_Slave;
-    init_struct->SPI_DataSize          = SPI_DataSize_8b;
-    init_struct->SPI_DataWidth         = 8;
-    init_struct->SPI_CPOL              = SPI_CPOL_Low;
-    init_struct->SPI_CPHA              = SPI_CPHA_1Edge;
-    init_struct->SPI_NSS               = SPI_NSS_Soft;
-    init_struct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-    init_struct->SPI_FirstBit          = SPI_FirstBit_MSB;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified SPI peripheral.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  state: new state of the spi peripheral.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_Cmd(SPI_TypeDef* spi, FunctionalState state)
-{
-    (state) ? SET_BIT(spi->GCR, SPI_GCR_SPIEN) : CLEAR_BIT(spi->GCR, SPI_GCR_SPIEN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified SPI interrupts.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:SPI1, SPI2.
-/// @param  interrupt: specifies the SPI interrupt sources to be
-///         enabled or disabled.
-///         This parameter can be one of the following values:
-/// @arg    SPI_IT_TXEPT: Transmitter empty interrupt
-/// @arg    SPI_IT_RXFULL: RX FIFO full interrupt
-/// @arg    SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt
-/// @arg    SPI_IT_RXOERR: Receive overrun error interrupt
-/// @arg    SPI_IT_UNDERRUN: underrun interrupt
-/// @arg    SPI_IT_RX: Receive data available interrupt
-/// @arg    SPI_IT_TX: Transmit FIFO available interrupt
-/// @param  state: new state of the specified spi interrupts.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_ITConfig(SPI_TypeDef* spi, u8 interrupt, FunctionalState state)
-{
-    if (state) {
-        SET_BIT(spi->GCR, (u32)SPI_GCR_IEN);
-        SET_BIT(spi->IER, (u32)interrupt);
-    }
-    else {
-        CLEAR_BIT(spi->IER, interrupt);
-        CLEAR_BIT(spi->GCR, SPI_GCR_IEN);
-    }
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the SPI DMA interface.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  state: new state of the DMA Request sources.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_DMACmd(SPI_TypeDef* spi, FunctionalState state)
-{
-    (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  configure tn Fifo trigger level bit.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  fifo_trigger_value: specifies the Fifo trigger level
-///         This parameter can be any combination of the following values:
-///         SPI_TXTLF : SPI TX FIFO Trigger value set
-///         SPI_RXTLF : SPI RX FIFO Trigger value set
-/// @param  state: new state of the selected SPI transfer request.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_FifoTrigger(SPI_TypeDef* spi, SPI_TLF_TypeDef fifo_trigger_value, FunctionalState state)
-{
-    (state) ? SET_BIT(spi->GCR, (u32)fifo_trigger_value) : CLEAR_BIT(spi->GCR, (u32)fifo_trigger_value);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Transmits a Data through the spi peripheral.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  data : Data to be transmitted.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_SendData(SPI_TypeDef* spi, u32 data)
-{
-    u16 templen;
-    __asm volatile("cpsid i");
-
-    WRITE_REG(spi->TDR, data);
-
-    templen = READ_REG(spi->ECR);
-    if(templen  == 0)
-        templen = 32;
-    if (templen > 8)
-        WRITE_REG(spi->TDR, data >> 8);
-    if (templen > 16)
-        WRITE_REG(spi->TDR, data >> 16);
-    if (templen > 24)
-        WRITE_REG(spi->TDR, data >> 24);
-    __asm volatile("cpsie i");
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the most recent received data by the spi peripheral.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @retval The value of the received data.
-////////////////////////////////////////////////////////////////////////////////
-u32 SPI_ReceiveData(SPI_TypeDef* spi)
-{
-    u32 temp;
-    u8 templen;
-    __asm volatile("cpsid i");
-
-    temp = READ_REG(spi->RDR);
-
-    templen = READ_REG(spi->ECR);
-    if(templen  == 0)
-        templen = 32;
-    if (templen > 8)
-        temp |= (u32)(READ_REG(spi->RDR) << 8);
-    if (templen > 16)
-        temp |= (u32)(READ_REG(spi->RDR) << 16);
-    if (templen > 24)
-        temp |= (u32)(READ_REG(spi->RDR) << 24);
-
-    __asm volatile("cpsie i");
-
-    return temp;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Slave chip csn single by selected
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  state: new state of the selected SPI CS pin
-///         request.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state)
-{
-    (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS);  // illogical
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the NSS pin control mode for the selected SPI.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  nss: specifies the SPI NSS internal state.
-///         This parameter can be one of the following values:
-/// @arg    SPI_NSS_Soft: NSS pin control by software
-/// @arg    SPI_NSS_Hard: NSS pin control by hardware
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* spi, SPI_NSS_TypeDef nss)
-{
-    (nss != SPI_NSS_Soft) ? SET_BIT(spi->GCR, SPI_NSS_Hard) : CLEAR_BIT(spi->GCR, SPI_NSS_Hard);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the data size for the selected SPI.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  data_size: specifies the SPI data size.
-///         This parameter can be one of the following values:
-///         0 to 31, 0 = 32b, 1 = 1b, 2 = 2b
-/// @arg    DataSize : 0 to 31
-/// @retval None.
-/// @retval None.
-bool SPI_DataSizeConfig(SPI_TypeDef* spi, u8 data_size)
-{
-    if (data_size > 32)
-        return false;
-    data_size &= 0x1F;
-    WRITE_REG(spi->ECR, data_size);
-    return true;
-}
-
-//////////////////////////////////////////////////////////////////////////////////
-void SPI_DataSizeTypeConfig(SPI_TypeDef* spi, SPI_DataSize_TypeDef SPI_DataSize)
-{
-    CLEAR_BIT(spi->GCR, (u32)SPI_DataSize_32b);
-    SET_BIT(spi->GCR, (u32)SPI_DataSize);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the data transfer direction in bi-directional mode
-///         for the specified SPI.
-/// @param spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param direction: specifies the data transfer direction in
-///         bi-directional mode.
-///         This parameter can be one of the following values:
-/// @arg    SPI_Direction_Tx: Selects Tx transmission direction
-/// @arg    SPI_Direction_Rx: Selects Rx receive direction
-/// @arg    SPI_Disable_Tx: Selects Rx receive direction
-/// @arg    SPI_Disable_Rx: Selects Rx receive direction
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* spi, SPI_Direction_TypeDef direction)
-{
-    switch (direction) {
-        case SPI_Direction_Rx:
-            SET_BIT(spi->GCR, SPI_GCR_RXEN);
-            break;
-        case SPI_Direction_Tx:
-            SET_BIT(spi->GCR, SPI_GCR_TXEN);
-            break;
-        case SPI_Disable_Rx:
-            CLEAR_BIT(spi->GCR, SPI_GCR_RXEN);
-            break;
-        case SPI_Disable_Tx:
-            CLEAR_BIT(spi->GCR, SPI_GCR_TXEN);
-            break;
-        default:
-            break;
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified SPI flag is set or not.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  flag: specifies the SPI flag to check.
-///         This parameter can be one of the following values:
-/// @arg    SPI_FLAG_RXAVL: Rx buffer has bytes flag
-/// @arg    SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag
-/// @arg    SPI_FLAG_TXFULL: Tx buffer full flag
-/// @arg    SPI_FLAG_RXAVL_4BYTE: Receive available 4 byte data message flag.
-/// @retval The new state of SPI_FLAG (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus SPI_GetFlagStatus(SPI_TypeDef* spi, SPI_FLAG_TypeDef flag)
-{
-//    u8 number;
-    return (spi->SR & flag) ? SET : RESET;
-//  if (spi->ECR == 8 || spi->ECR == 0)
-//      return (spi->SR & SPI_FLAG) ? SET : RESET;
-//  else {
-//      if ((spi->ECR > 0) && (spi->ECR <= 8))
-//          number = 1;
-//      else if ((spi->ECR) <= 16)
-//          number = 2;
-//      else if ((spi->ECR) <= 24)
-//          number = 3;
-//      else if (((spi->ECR) <= 31) || (spi->ECR == 0))
-//          number = 4;
-//      return (((spi->SR & 0xf00) >> 8) >= number) ? SET : RESET;
-//  }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified SPI interrupt has occurred or not.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  interrupt: specifies the SPI interrupt source to check.
-///         This parameter can be one of the following values:
-/// @arg    SPI_IT_TX: Tx buffer empty interrupt
-/// @arg    SPI_IT_RX: Rx buffer  interrupt
-/// @arg    SPI_IT_UNDERRUN: under Error interrupt in slave mode
-/// @arg    SPI_IT_RXOVER: RX OVER Error interrupt
-/// @arg    SPI_IT_RXMATCH: spectials rx data numbers  interrupt
-/// @arg    SPI_IT_RXFULL: Rx buffer full interrupt
-/// @arg    SPI_IT_TXEPT: Tx buffer  and tx shifter empty interrupt
-/// @retval The new state of SPI_IT (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus SPI_GetITStatus(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt)
-{
-    return (spi->ISR & interrupt) ? SET : RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the spi  interrupt pending bit.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  interrupt: specifies the SPI interrupt pending bit to clear.
-/// @arg    SPI_IT_TX: Tx buffer empty interrupt
-/// @arg    SPI_IT_RX: Rx buffer  interrupt
-/// @arg    SPI_IT_UNDERRUN: under Error interrupt in slave mode
-/// @arg    SPI_IT_RXOVER: RX OVER Error interrupt
-/// @arg    SPI_IT_RXMATCH: spectials rx data numbers  interrupt
-/// @arg    SPI_IT_RXFULL: Rx buffer full interrupt
-/// @arg    SPI_IT_TXEPT: Tx buffer  and tx shifter empty interrupt
-///         This function clears only ERR intetrrupt pending bit.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_ClearITPendingBit(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt)
-{
-    SET_BIT(spi->ICR, interrupt);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  SPI Hole a count Received bytes in next receive process.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  number: specifies the SPI receive Number.
-///         This parament can be 1-65535.
-///         This function can use only in SPI master single receive mode.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_RxBytes(SPI_TypeDef* spi, u16 number)
-{
-    WRITE_REG(spi->RDNR, number);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  slave mode tx data transmit phase adjust set.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  adjust_value: slave mode tx data transmit phase adjust enum.
-///         This parament can be :
-///         SPI_SlaveAdjust_FAST:  fast speed use
-///         SPI_SlaveAdjust_LOW:   low speed use
-///         This function can use only in SPI master single receive mode.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void SPI_SlaveAdjust(SPI_TypeDef* spi, SPI_SlaveAdjust_TypeDef adjust_value)
-{
-    (adjust_value) ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables all SPI interrupts.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  state: new state of all spi interrupts.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exSPI_ITCmd(SPI_TypeDef* spi, FunctionalState state)
-{
-    (state) ? SET_BIT(spi->IER, (u32)SPI_GCR_IEN) : CLEAR_BIT(spi->IER, (u32)SPI_GCR_IEN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified SPI interrupts.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  interrupt: specifies the SPI interrupt sources to be enabled or disabled.
-///         This parameter can be one of the following values:
-/// @arg    SPI_IT_TXEPT: Transmitter empty interrupt
-/// @arg    SPI_IT_RXFULL: RX FIFO full interrupt
-/// @arg    SPI_IT_RXMATCH: Receive data match the RXDNR number interrupt
-/// @arg    SPI_IT_RXOERR: Receive overrun error interrupt
-/// @arg    SPI_IT_UNDERRUN: underrun interrupt
-/// @arg    SPI_IT_RX: Receive data available interrupt
-/// @arg    SPI_IT_TX: Transmit FIFO available interrupt
-/// @param  state: new state of the specified spi interrupts.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exSPI_ITConfig(SPI_TypeDef* spi, SPI_IT_TypeDef interrupt, FunctionalState state)
-{
-    (state) ? SET_BIT(spi->IER, (u32)interrupt) : CLEAR_BIT(spi->IER, (u32)interrupt);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the SPI DMA request.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  state: new state of the DMA Request.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exSPI_DMACmd(SPI_TypeDef* spi, FunctionalState state)
-{
-    (state) ? SET_BIT(spi->GCR, SPI_GCR_DMAEN) : CLEAR_BIT(spi->GCR, SPI_GCR_DMAEN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set or reset Slave chip csn signal output
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  state: new state of Slave chip csn signal output.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exSPI_CSInternalSelected(SPI_TypeDef* spi, FunctionalState state)
-{
-    (state) ? CLEAR_BIT(spi->NSSR, SPI_NSSR_NSS) : SET_BIT(spi->NSSR, SPI_NSSR_NSS);  // illogical
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  tx data and rx data phase adjust.
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2.
-/// @param  adjust_value: choose adjust mode.
-///         This parament can be :
-///         SPI_DataEdgeAdjust_LOW,
-///         SPI_DataEdgeAdjust_FAST
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void exSPI_DataEdgeAdjust(SPI_TypeDef* spi, SPI_DataEdgeAdjust_TypeDef adjust_value)
-{
-    // master mode
-    if (spi->GCR & SPI_GCR_MODE) {
-        adjust_value ? SET_BIT(spi->CCR, SPI_CCR_RXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_RXEDGE);
-    }
-    // slave mode
-    else {
-        adjust_value ? SET_BIT(spi->CCR, SPI_CCR_TXEDGE) : CLEAR_BIT(spi->CCR, SPI_CCR_TXEDGE);
-    }
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set or reset i2s
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2, SPI3.
-/// @param  state: new state of Slave chip csn signal output.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2S_Cmd(SPI_TypeDef* spi, FunctionalState state)
-{
-    (state) ? SET_BIT(spi->CFGR, I2S_CFGR_SPI_I2S) : CLEAR_BIT(spi->CFGR, I2S_CFGR_SPI_I2S);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  i2s Config
-/// @param  spi: Select the SPI peripheral.
-///         This parameter can be one of the following values:
-///         SPI1, SPI2, SPI3.
-/// @param  state: new state of Slave chip csn signal output.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void I2S_Init(SPI_TypeDef* spi, I2S_InitTypeDef* I2S_InitStruct)
-{
-    u32 i2sdiv = 2;
-    u32 tmpreg = 0;
-    u32 packetlength = 1;
-    u32 result = 0, yushu = 0;
-    u32 sourceclock = 0;
-    RCC_ClocksTypeDef RCC_Clocks;
-
-    if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) {
-        i2sdiv = 2;
-    }
-    else {
-        if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) {
-            packetlength = 1;
-        }
-        else {
-            packetlength = 2;
-        }
-        RCC_GetClocksFreq(&RCC_Clocks);
-
-        if((SPI2 == spi) || (SPI3 == spi))  {
-            sourceclock = RCC_Clocks.PCLK1_Frequency;
-        }
-        else {
-            sourceclock = RCC_Clocks.PCLK2_Frequency;
-        }
-        if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) {
-            result = (sourceclock) / (256 * (I2S_InitStruct->I2S_AudioFreq));
-            yushu = (sourceclock) % (256 * (I2S_InitStruct->I2S_AudioFreq));
-            if(yushu > (128 * (I2S_InitStruct->I2S_AudioFreq))) {
-                result = result + 1;
-            }
-            i2sdiv = result;
-            if ((i2sdiv < 2) || (i2sdiv > 0x1FF)) {
-                i2sdiv = 2;
-            }
-        }
-        else {
-            result = (sourceclock) / (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq));
-            yushu = (sourceclock) % (16 * 2 * packetlength * (I2S_InitStruct->I2S_AudioFreq));
-            if(yushu > ((16 * packetlength * (I2S_InitStruct->I2S_AudioFreq)))) {
-                result = result + 1;
-            }
-            if ((i2sdiv < 1) || (i2sdiv > 0x1FF)) {
-                i2sdiv = 1;
-            }
-        }
-    }
-    if(I2S_CPOL_High  == I2S_InitStruct->I2S_CPOL) {
-        spi->CCTL |= SPI_CCR_CPOL;
-    }
-    else {
-        spi->CCTL &= ~SPI_CCR_CPOL;
-    }
-
-    spi->CFGR = 0x2 << I2S_CFGR_I2SDIV_Pos;
-
-    if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx)) {
-        spi->GCTL |= SPI_GCR_MODE;
-    }
-    else {
-        spi->GCTL &= ~SPI_GCR_MODE;
-    }
-    if((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) {
-        spi->GCTL |= SPI_GCR_TXEN;
-        spi->GCTL &= ~SPI_GCR_RXEN;
-    }
-    else {
-        spi->GCTL &= ~SPI_GCR_TXEN;
-        spi->GCTL |= SPI_GCR_RXEN;
-    }
-//    tmpreg = spi->GCTL;
-//    tmpreg &= ~(1 << 2);
-//    tmpreg |= (u16)(I2S_InitStruct->I2S_Mode);
-//    spi->GCTL = tmpreg;
-//
-    tmpreg = 0;
-    tmpreg |= (i2sdiv << I2S_CFGR_I2SDIV_Pos) | \
-              (I2S_InitStruct->I2S_MCLKOutput) | \
-              (I2S_CFGR_SPI_I2S) | \
-              (I2S_InitStruct->I2S_Standard) | \
-              (I2S_InitStruct->I2S_DataFormat);
-    spi->CFGR &= ~I2S_CFGR_I2SDIV;
-    spi->CFGR |= tmpreg;
-
-}
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c
deleted file mode 100644
index e798bc46a..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_tim.c
+++ /dev/null
@@ -1,1875 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_tim.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE TIM FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_TIM_C_
-
-// Files includes
-#include "hal_rcc.h"
-#include "hal_tim.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup TIM_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup TIM_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the tim peripheral registers to their default reset values.
-/// @param  tim:  select the TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_DeInit(TIM_TypeDef* tim)
-{
-    switch (*(vu32*)&tim) {
-        case (u32)TIM1:
-            exRCC_APB2PeriphReset(RCC_APB2ENR_TIM1);
-            break;
-        case (u32)TIM2:
-            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM2);
-            break;
-        case (u32)TIM3:
-            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM3);
-            break;
-        case (u32)TIM4:
-            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM4);
-            break;
-
-        case (u32)TIM5:
-            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM5);
-            break;
-        case (u32)TIM6:
-            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM6);
-            break;
-        case (u32)TIM7:
-            exRCC_APB1PeriphReset(RCC_APB1ENR_TIM7);
-            break;
-
-        case (u32)TIM8:
-            exRCC_APB2PeriphReset(RCC_APB2ENR_TIM8);
-            break;
-
-        default:
-            break;
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the tim Time Base Unit peripheral according to
-///         the specified parameters in the init_struct.
-/// @param  tim: select the TIM peripheral.
-/// @param  init_struct: pointer to a TIM_TimeBaseInitTypeDef
-///         structure that contains the configuration information for the
-///         specified TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_TimeBaseInit(TIM_TypeDef* tim, TIM_TimeBaseInitTypeDef* init_struct)
-{
-    MODIFY_REG(tim->CR1, TIM_CR1_CKD, init_struct->TIM_ClockDivision);
-
-    if ((tim == TIM1) || (tim == TIM2) || (tim == TIM3) || (tim == TIM4) || (tim == TIM5) || (tim == TIM8))
-        MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, init_struct->TIM_CounterMode);
-
-    if ((tim == TIM1) || (tim == TIM8) )
-
-        MODIFY_REG(tim->RCR, TIM_RCR_REP, init_struct->TIM_RepetitionCounter);
-
-    WRITE_REG(tim->ARR, init_struct->TIM_Period);
-    WRITE_REG(tim->PSC, init_struct->TIM_Prescaler);
-    WRITE_REG(tim->EGR, TIM_PSCReloadMode_Immediate);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the tim Channel1 according to the specified
-///         parameters in the init_struct.
-/// @param  tim:  select the TIM peripheral.
-/// @param  init_struct: pointer to a TIM_OCInitTypeDef structure that
-///         contains the configuration information for the specified TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC1Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, init_struct->TIM_OCMode);
-    MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC1EN, \
-               ((u32)init_struct->TIM_OCPolarity) | ((u32)init_struct->TIM_OutputState));
-    WRITE_REG(tim->CCR1, init_struct->TIM_Pulse);
-
-    if ((tim == TIM1) || (tim == TIM8)) {
-        MODIFY_REG(tim->CCER, TIM_CCER_CC1NP | TIM_CCER_CC1NEN, \
-                   ((u32)init_struct->TIM_OCNPolarity) | ((u32)init_struct->TIM_OutputNState));
-        MODIFY_REG(tim->CR2, TIM_CR2_OIS1 | TIM_CR2_OIS1N, \
-                   ((u32)init_struct->TIM_OCIdleState) | ((u32)init_struct->TIM_OCNIdleState));
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the tim Channel2 according to the specified
-///         parameters in the init_struct.
-/// @param  tim: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-/// @param  init_struct: pointer to a TIM_OCInitTypeDef structure that
-///         contains the configuration information for the specified TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC2Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, init_struct->TIM_OCMode << 8);
-    MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, \
-               (init_struct->TIM_OCPolarity << 4) | (init_struct->TIM_OutputState << 4));
-    WRITE_REG(tim->CCR2, init_struct->TIM_Pulse);
-
-    if ((tim == TIM1) || (tim == TIM8)) {
-        MODIFY_REG(tim->CCER, TIM_CCER_CC2NP | TIM_CCER_CC2NEN, \
-                   (init_struct->TIM_OCNPolarity << 4) | (init_struct->TIM_OutputNState << 4));
-        MODIFY_REG(tim->CR2, TIM_CR2_OIS2 | TIM_CR2_OIS2N, \
-                   (init_struct->TIM_OCIdleState << 2) | (init_struct->TIM_OCNIdleState << 2));
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the tim Channel3 according to the specified
-///         parameters in the init_struct.
-/// @param  tim: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
-/// @param  init_struct: pointer to a TIM_OCInitTypeDef structure that
-///         contains the configuration information for the specified TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC3Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, init_struct->TIM_OCMode);
-    MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, \
-               (init_struct->TIM_OCPolarity << 8) | (init_struct->TIM_OutputState << 8));
-    WRITE_REG(tim->CCR3, init_struct->TIM_Pulse);
-
-    if ((tim == TIM1) || (tim == TIM8)) {
-        MODIFY_REG(tim->CCER, TIM_CCER_CC3NP | TIM_CCER_CC3NEN, \
-                   (init_struct->TIM_OCNPolarity << 8) | (init_struct->TIM_OutputNState << 8));
-        MODIFY_REG(tim->CR2, TIM_CR2_OIS3 | TIM_CR2_OIS3N, \
-                   (init_struct->TIM_OCIdleState << 4) | (init_struct->TIM_OCNIdleState << 4));
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the tim Channel4 according to the specified
-///         parameters in the init_struct.
-/// @param  tim:select the TIM peripheral.
-/// @param  init_struct: pointer to a TIM_OCInitTypeDef structure that
-///         contains the configuration information for the specified TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC4Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, (init_struct->TIM_OCMode) << 8);
-    MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, \
-               (init_struct->TIM_OCPolarity << 12) | (init_struct->TIM_OutputState << 12));
-    WRITE_REG(tim->CCR4, init_struct->TIM_Pulse);
-
-    if ((tim == TIM1) || (tim == TIM8))
-        MODIFY_REG(tim->CR2, TIM_CR2_OIS4, init_struct->TIM_OCIdleState << 6);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the TIM peripheral according to the specified
-///         parameters in the init_struct.
-/// @param  tim:  select the TIM peripheral.
-/// @param  init_struct: pointer to a TIM_ICInitTypeDef structure that
-///         contains the configuration information for the specified TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ICInit(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct)
-{
-    switch (init_struct->TIM_Channel) {
-        case TIM_Channel_1:
-            TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
-            TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
-            break;
-        case TIM_Channel_2:
-            TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
-            TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
-            break;
-        case TIM_Channel_3:
-            TI3_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
-            TIM_SetIC3Prescaler(tim, init_struct->TIM_ICPrescaler);
-            break;
-        case TIM_Channel_4:
-            TI4_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
-            TIM_SetIC4Prescaler(tim, init_struct->TIM_ICPrescaler);
-            break;
-        default:
-            break;
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the TIM peripheral according to the specified
-///         parameters in the init_struct to measure an external PWM signal.
-/// @param  tim: select the TIM peripheral.
-/// @param  init_struct: pointer to a TIM_ICInitTypeDef structure that
-///         contains the configuration information for the specified TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_PWMIConfig(TIM_TypeDef* tim, TIM_ICInitTypeDef* init_struct)
-{
-    u16 icoppositepolarity  = TIM_ICPolarity_Rising;
-    u16 icoppositeselection = TIM_ICSelection_DirectTI;
-    icoppositepolarity = (init_struct->TIM_ICPolarity == TIM_ICPolarity_Rising) ? TIM_ICPolarity_Falling : TIM_ICPolarity_Rising;
-    icoppositeselection =
-        (init_struct->TIM_ICSelection == TIM_ICSelection_DirectTI) ? TIM_ICSelection_IndirectTI : TIM_ICSelection_DirectTI;
-    if (init_struct->TIM_Channel == TIM_Channel_1) {
-        TI1_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
-        TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
-        TI2_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter);
-        TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
-    }
-    else {
-        TI2_Configure(tim, init_struct->TIM_ICPolarity, init_struct->TIM_ICSelection, init_struct->TIM_ICFilter);
-        TIM_SetIC2Prescaler(tim, init_struct->TIM_ICPrescaler);
-        TI1_Configure(tim, icoppositepolarity, icoppositeselection, init_struct->TIM_ICFilter);
-        TIM_SetIC1Prescaler(tim, init_struct->TIM_ICPrescaler);
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
-///         the OSSR State and the AOE(automatic output enable).
-/// @param  tim: select the TIM
-/// @param  init_struct: pointer to a TIM_BDTRInitTypeDef structure that
-///         contains the BDTR Register configuration  information for the TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_BDTRConfig(TIM_TypeDef* tim, TIM_BDTRInitTypeDef* init_struct)
-{
-    tim->BDTR = (u32)init_struct->TIM_OSSRState | init_struct->TIM_OSSIState | init_struct->TIM_LOCKLevel |
-                init_struct->TIM_DeadTime | init_struct->TIM_Break | init_struct->TIM_BreakPolarity |
-                init_struct->TIM_AutomaticOutput;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param  init_struct : pointer to a TIM_TimeBaseInitTypeDef
-///         structure which will be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* init_struct)
-{
-    init_struct->TIM_Period            = 0xFFFFFFFF;
-    init_struct->TIM_Prescaler         = 0x0000;
-    init_struct->TIM_ClockDivision     = TIM_CKD_DIV1;
-    init_struct->TIM_CounterMode       = TIM_CounterMode_Up;
-    init_struct->TIM_RepetitionCounter = 0x00;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param  init_struct : pointer to a TIM_OCInitTypeDef structure which will
-///         be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OCStructInit(TIM_OCInitTypeDef* init_struct)
-{
-    init_struct->TIM_OCMode       = TIM_OCMode_Timing;
-    init_struct->TIM_OutputState  = TIM_OutputState_Disable;
-    init_struct->TIM_OutputNState = TIM_OutputNState_Disable;
-    init_struct->TIM_Pulse        = 0x00000000;
-    init_struct->TIM_OCPolarity   = TIM_OCPolarity_High;
-    init_struct->TIM_OCNPolarity  = TIM_OCNPolarity_High;
-    init_struct->TIM_OCIdleState  = TIM_OCIdleState_Reset;
-    init_struct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param  init_struct: pointer to a TIM_ICInitTypeDef structure which will
-///         be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ICStructInit(TIM_ICInitTypeDef* init_struct)
-{
-    init_struct->TIM_Channel     = TIM_Channel_1;
-    init_struct->TIM_ICPolarity  = TIM_ICPolarity_Rising;
-    init_struct->TIM_ICSelection = TIM_ICSelection_DirectTI;
-    init_struct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
-    init_struct->TIM_ICFilter    = 0x00;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each init_struct member with its default value.
-/// @param  init_struct: pointer to a TIM_BDTRInitTypeDef structure which
-///         will be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* init_struct)
-{
-    init_struct->TIM_OSSRState       = TIM_OSSRState_Disable;
-    init_struct->TIM_OSSIState       = TIM_OSSIState_Disable;
-    init_struct->TIM_LOCKLevel       = TIM_LOCKLevel_OFF;
-    init_struct->TIM_DeadTime        = 0x00;
-    init_struct->TIM_Break           = TIM_Break_Disable;
-    init_struct->TIM_BreakPolarity   = TIM_BreakPolarity_Low;
-    init_struct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified TIM peripheral.
-/// @param  tim: where x can be 1 to 17 to select the tim peripheral.
-/// @param  state: new state of the tim peripheral.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_Cmd(TIM_TypeDef* tim, FunctionalState state)
-{
-    (state) ? SET_BIT(tim->CR1, TIM_CR1_CEN) : CLEAR_BIT(tim->CR1, TIM_CR1_CEN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the TIM peripheral Main Outputs.
-/// @param  tim: where x can be 1, 8, 16 or 17 to select the tim peripheral.
-/// @param  state: new state of the TIM peripheral Main Outputs.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_CtrlPWMOutputs(TIM_TypeDef* tim, FunctionalState state)
-{
-    (state) ? SET_BIT(tim->BDTR, TIM_BDTR_MOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_MOEN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified TIM interrupts.
-/// @param  tim:  select the tim peripheral.
-/// @param  it: specifies the TIM interrupts sources to be enabled or disabled.
-///   This parameter can be any combination of the following values:
-///     @arg TIM_IT_Update: TIM update Interrupt source
-///     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-///     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-///     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-///     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-///     @arg TIM_IT_COM: TIM Commutation Interrupt source
-///     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-///     @arg TIM_IT_Break: TIM Break Interrupt source
-/// @note
-///   - Partial timer can have TIM_IT_Update or TIM_IT_CC1.
-///   - TIM_IT_Break is used only with partial timer.
-///   - TIM_IT_COM is used only with partial timer.
-/// @param  state: new state of the TIM interrupts.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ITConfig(TIM_TypeDef* tim, u32 it, FunctionalState state)    //TIMIT_TypeDef
-{
-    (state) ? SET_BIT(tim->DIER, it) : CLEAR_BIT(tim->DIER, it);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim event to be generate by software.
-/// @param  tim:  select the TIM peripheral.
-/// @param  source: specifies the event source.
-///   This parameter can be one or more of the following values:
-///     @arg TIM_EventSource_Update: Timer update Event source
-///     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
-///     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
-///     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
-///     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
-///     @arg TIM_EventSource_COM: Timer COM event source
-///     @arg TIM_EventSource_Trigger: Timer Trigger Event source
-///     @arg TIM_EventSource_Break: Timer Break event source
-/// @note
-///   - TIM_EventSource_COM and TIM_EventSource_Break are used only with partial timer.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_GenerateEvent(TIM_TypeDef* tim, TIMEGR_Typedef source)
-{
-    WRITE_REG(tim->EGR, source);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim's DMA interface.
-/// @param  tim: select the TIM peripheral.
-/// @param  dma_base: DMA Base address.
-///   This parameter can be one of the following values:
-///     @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
-///          TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
-///          TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
-///          TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
-///          TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
-///          TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
-///          TIM_DMABase_DCR.
-/// @param  length: DMA Burst length.
-///   This parameter can be one value between:
-///   TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_DMAConfig(TIM_TypeDef* tim, TIMDMABASE_Typedef dma_base, TIMDMABURSTLENGTH_Typedef length)
-{
-    WRITE_REG(tim->DCR, ((u32)dma_base) | ((u32)length));
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the tim's DMA Requests.
-/// @param  tim: select the TIM peripheral.
-/// @param  source: specifies the DMA Request sources.
-///   This parameter can be any combination of the following values:
-///     @arg TIM_DMA_Update: TIM update Interrupt source
-///     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-///     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-///     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-///     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-///     @arg TIM_DMA_COM: TIM Commutation DMA source
-///     @arg TIM_DMA_Trigger: TIM Trigger DMA source
-/// @param  state: new state of the DMA Request sources.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_DMACmd(TIM_TypeDef* tim, TIMDMASRC_Typedef source, FunctionalState state)
-{
-    (state) ? SET_BIT(tim->DIER, source) : CLEAR_BIT(tim->DIER, source);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim internal Clock
-/// @param  tim: select the TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_InternalClockConfig(TIM_TypeDef* tim)
-{
-    CLEAR_BIT(tim->SMCR, TIM_SMCR_SMS);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Internal Trigger as External Clock
-/// @param  tim: select the TIM peripheral.
-/// @param  source: Trigger source.
-///   This parameter can be one of the following values:
-///    @arg TIM_TS_ITR0: Internal Trigger 0
-///    @arg TIM_TS_ITR1: Internal Trigger 1
-///    @arg TIM_TS_ITR2: Internal Trigger 2
-///    @arg TIM_TS_ITR3: Internal Trigger 3
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* tim, TIMTS_TypeDef source)
-{
-    TIM_SelectInputTrigger(tim, source);
-    SET_BIT(tim->SMCR, TIM_SlaveMode_External1);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Trigger as External Clock
-/// @param  tim: select the TIM peripheral.
-/// @param  source: Trigger source.
-///   This parameter can be one of the following values:
-///     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
-///     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
-///     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
-/// @param  polarity: specifies the TIx Polarity.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Rising
-///     @arg TIM_ICPolarity_Falling
-/// @param  filter : specifies the filter value.
-///   This parameter must be a value between 0x0 and 0xF.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_TIxExternalClockConfig(TIM_TypeDef* tim, TIM_TIEXTCLKSRC_Typedef source, TIMICP_Typedef polarity, u16 filter)
-{
-    (source == TIM_TIxExternalCLK1Source_TI2) ? (TI2_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter))
-    : (TI1_Configure(tim, polarity, TIM_ICSelection_DirectTI, filter));
-    TIM_SelectInputTrigger(tim, (TIMTS_TypeDef)source);
-    SET_BIT(tim->SMCR, TIM_SlaveMode_External1);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim External Trigger (ETR).
-/// @param  tim: select the TIM peripheral.
-/// @param  psc: The external Trigger Prescaler.
-///   This parameter can be one of the following values:
-///     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-///     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-///     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-///     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-/// @param  polarity: The external Trigger Polarity.
-///   This parameter can be one of the following values:
-///     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-///     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-/// @param  filter: External Trigger Filter.
-///   This parameter must be a value between 0x00 and 0x0F
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ETRConfig(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
-{
-    CLEAR_BIT(tim->SMCR, TIM_SMCR_ECEN);
-    MODIFY_REG(tim->SMCR, TIM_SMCR_ETP, polarity);
-    MODIFY_REG(tim->SMCR, TIM_SMCR_ETPS, psc);
-    MODIFY_REG(tim->SMCR, TIM_SMCR_ETF, filter << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the External clock Mode1
-/// @param  tim: select the TIM peripheral.
-/// @param  psc: The external Trigger Prescaler.
-///   This parameter can be one of the following values:
-///     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-///     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-///     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-///     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-/// @param  polarity: The external Trigger Polarity.
-///   This parameter can be one of the following values:
-///     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-///     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-/// @param  filter: External Trigger Filter.
-///   This parameter must be a value between 0x00 and 0x0F
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ETRClockMode1Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
-{
-    TIM_ETRConfig(tim, psc, polarity, filter);
-    MODIFY_REG(tim->SMCR, TIM_SMCR_TS | TIM_SMCR_SMS, ((u32)TIM_TS_ETRF) | ((u32)TIM_SlaveMode_External1));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the External clock Mode2
-/// @param  tim:  select the TIM peripheral.
-/// @param  psc: The external Trigger Prescaler.
-///   This parameter can be one of the following values:
-///     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-///     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-///     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-///     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-/// @param  polarity: The external Trigger Polarity.
-///   This parameter can be one of the following values:
-///     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-///     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-/// @param  filter: External Trigger Filter.
-///   This parameter must be a value between 0x00 and 0x0F
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ETRClockMode2Config(TIM_TypeDef* tim, TIMEXTTRGPSC_Typedef psc, TIMETP_Typedef polarity, u16 filter)
-{
-    TIM_ETRConfig(tim, psc, polarity, filter);
-    SET_BIT(tim->SMCR, TIM_SMCR_ECEN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Prescaler.
-/// @param  tim:  select the TIM peripheral.
-/// @param  prescaler: specifies the Prescaler Register value
-/// @param  reloadMode: specifies the TIM Prescaler Reload mode
-///   This parameter can be one of the following values:
-///     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
-///     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_PrescalerConfig(TIM_TypeDef* tim, u16 prescaler, TIMUG_Typedef reloadMode)
-{
-    WRITE_REG(tim->PSC, prescaler);
-    WRITE_REG(tim->EGR, reloadMode);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Specifies the tim Counter Mode to be used.
-/// @param  tim:select the TIM peripheral.
-/// @param  counter_mode: specifies the Counter Mode to be used
-///   This parameter can be one of the following values:
-///     @arg TIM_CounterMode_Up: TIM Up Counting Mode
-///     @arg TIM_CounterMode_Down: TIM Down Counting Mode
-///     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
-///     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
-///     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_CounterModeConfig(TIM_TypeDef* tim, TIMCOUNTMODE_Typedef counter_mode)
-{
-    MODIFY_REG(tim->CR1, TIM_CR1_CMS | TIM_CR1_DIR, counter_mode);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the Input Trigger source
-/// @param  tim: select the TIM peripheral.
-/// @param  source: The Input Trigger source.
-///   This parameter can be one of the following values:
-///     @arg TIM_TS_ITR0: Internal Trigger 0
-///     @arg TIM_TS_ITR1: Internal Trigger 1
-///     @arg TIM_TS_ITR2: Internal Trigger 2
-///     @arg TIM_TS_ITR3: Internal Trigger 3
-///     @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-///     @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-///     @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-///     @arg TIM_TS_ETRF: External Trigger input
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SelectInputTrigger(TIM_TypeDef* tim, TIMTS_TypeDef source)
-{
-    MODIFY_REG(tim->SMCR, TIM_SMCR_TS, source);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Encoder Interface.
-/// @param  tim: select the TIM peripheral.
-/// @param  encoder_mode: specifies the tim Encoder Mode.
-///   This parameter can be one of the following values:
-///     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
-///     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
-///     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
-///                                on the level of the other input.
-/// @param  ic1_polarity: specifies the IC1 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Falling: IC Falling edge.
-///     @arg TIM_ICPolarity_Rising: IC Rising edge.
-/// @param  ic2_polarity: specifies the IC2 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Falling: IC Falling edge.
-///     @arg TIM_ICPolarity_Rising: IC Rising edge.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_EncoderInterfaceConfig(TIM_TypeDef*          tim,
-                                TIMSMSENCODER_Typedef encoder_mode,
-                                TIMICP_Typedef        ic1_polarity,
-                                TIMICP_Typedef        ic2_polarity)
-{
-    MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, encoder_mode);
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_CC2S, TIM_CCMR1_CC1S_DIRECTTI | TIM_CCMR1_CC2S_DIRECTTI);
-    MODIFY_REG(tim->CCER, TIM_CCER_CC1P | TIM_CCER_CC2P, ic1_polarity | (ic2_polarity << 4));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces the tim output 1 waveform to active or inactive level.
-/// @param  tim:  select the TIM peripheral.
-/// @param  forced_action: specifies the forced Action to be set to the output waveform.
-///   This parameter can be one of the following values:
-///     @arg TIM_ForcedAction_Active: Force active level on OC1REF
-///     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ForcedOC1Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, forced_action);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces the tim output 2 waveform to active or inactive level.
-/// @param  tim: select the TIM peripheral.
-/// @param  forced_action: specifies the forced Action to be set to the output waveform.
-///   This parameter can be one of the following values:
-///     @arg TIM_ForcedAction_Active: Force active level on OC2REF
-///     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ForcedOC2Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, forced_action << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces the tim output 3 waveform to active or inactive level.
-/// @param  tim: select the TIM peripheral.
-/// @param  forced_action: specifies the forced Action to be set to the output waveform.
-///   This parameter can be one of the following values:
-///     @arg TIM_ForcedAction_Active: Force active level on OC3REF
-///     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ForcedOC3Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, forced_action);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Forces the tim output 4 waveform to active or inactive level.
-/// @param  tim: select the TIM peripheral.
-/// @param  forced_action: specifies the forced Action to be set to the output waveform.
-///   This parameter can be one of the following values:
-///     @arg TIM_ForcedAction_Active: Force active level on OC4REF
-///     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ForcedOC4Config(TIM_TypeDef* tim, TIMOCMODE_Typedef forced_action)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, forced_action << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables tim peripheral Preload register on ARR.
-/// @param  tim:  select the TIM peripheral.
-/// @param  state: new state of the tim peripheral Preload register
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ARRPreloadConfig(TIM_TypeDef* tim, FunctionalState state)
-{
-    (state) ? SET_BIT(tim->CR1, TIM_CR1_ARPEN) : CLEAR_BIT(tim->CR1, TIM_CR1_ARPEN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the TIM peripheral Commutation event.
-/// @param  tim: select the tim peripheral.
-/// @param  state: new state of the Commutation event.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SelectCOM(TIM_TypeDef* tim, FunctionalState state)
-{
-    (state) ? SET_BIT(tim->CR2, TIM_CR2_CCUS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCUS);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the tim peripheral Capture Compare DMA source.
-/// @param  tim: select the TIM peripheral.
-/// @param  state: new state of the Capture Compare DMA source
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SelectCCDMA(TIM_TypeDef* tim, FunctionalState state)
-{
-    (state) ? SET_BIT(tim->CR2, TIM_CR2_CCDS) : CLEAR_BIT(tim->CR2, TIM_CR2_CCDS);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
-/// @param  tim: select the tim peripheral.
-/// @param  state: new state of the Capture Compare Preload Control bit
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_CCPreloadControl(TIM_TypeDef* tim, FunctionalState state)
-{
-    (state) ? SET_BIT(tim->CR2, TIM_CR2_CCPC) : CLEAR_BIT(tim->CR2, TIM_CR2_CCPC);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the tim peripheral Preload register on CCR1.
-/// @param  tim:  select the TIM peripheral.
-/// @param  preload: new state of the tim peripheral Preload register
-///   This parameter can be one of the following values:
-///     @arg TIM_OCPreload_Enable
-///     @arg TIM_OCPreload_Disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC1PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1PEN, preload);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the tim peripheral Preload register on CCR2.
-/// @param  tim: select the TIM peripheral.
-/// @param  preload: new state of the tim peripheral Preload register
-///   This parameter can be one of the following values:
-///     @arg TIM_OCPreload_Enable
-///     @arg TIM_OCPreload_Disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC2PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2PEN, preload << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the tim peripheral Preload register on CCR3.
-/// @param  tim: select the TIM peripheral.
-/// @param  preload: new state of the tim peripheral Preload register
-///   This parameter can be one of the following values:
-///     @arg TIM_OCPreload_Enable
-///     @arg TIM_OCPreload_Disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC3PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3PEN, preload);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the tim peripheral Preload register on CCR4.
-/// @param  tim: select the TIM peripheral.
-/// @param  preload: new state of the tim peripheral Preload register
-///   This parameter can be one of the following values:
-///     @arg TIM_OCPreload_Enable
-///     @arg TIM_OCPreload_Disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC4PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4PEN, preload << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Output Compare 1 Fast feature.
-/// @param  tim: select the TIM peripheral.
-/// @param  fast: new state of the Output Compare Fast Enable Bit.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCFast_Enable: TIM output compare fast enable
-///     @arg TIM_OCFast_Disable: TIM output compare fast disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC1FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1FEN, fast);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Output Compare 2 Fast feature.
-/// @param  tim: select the TIM peripheral.
-/// @param  fast: new state of the Output Compare Fast Enable Bit.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCFast_Enable: TIM output compare fast enable
-///     @arg TIM_OCFast_Disable: TIM output compare fast disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC2FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2FEN, fast << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Output Compare 3 Fast feature.
-/// @param  tim: select the TIM peripheral.
-/// @param  fast: new state of the Output Compare Fast Enable Bit.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCFast_Enable: TIM output compare fast enable
-///     @arg TIM_OCFast_Disable: TIM output compare fast disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC3FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3FEN, fast);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Output Compare 4 Fast feature.
-/// @param  tim: select the TIM peripheral.
-/// @param  fast: new state of the Output Compare Fast Enable Bit.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCFast_Enable: TIM output compare fast enable
-///     @arg TIM_OCFast_Disable: TIM output compare fast disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC4FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4FEN, fast << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears or safeguards the OCREF1 signal on an external event
-/// @param  tim:  select the TIM peripheral.
-/// @param  clear: new state of the Output Compare Clear Enable Bit.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCClear_Enable: TIM Output clear enable
-///     @arg TIM_OCClear_Disable: TIM Output clear disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ClearOC1Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1CEN, clear);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears or safeguards the OCREF2 signal on an external event
-/// @param  tim: select the TIM peripheral.
-/// @param  clear: new state of the Output Compare Clear Enable Bit.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCClear_Enable: TIM Output clear enable
-///     @arg TIM_OCClear_Disable: TIM Output clear disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ClearOC2Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2CEN, clear << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears or safeguards the OCREF3 signal on an external event
-/// @param  tim: select the TIM peripheral.
-/// @param  clear: new state of the Output Compare Clear Enable Bit.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCClear_Enable: TIM Output clear enable
-///     @arg TIM_OCClear_Disable: TIM Output clear disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ClearOC3Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3CEN, clear);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears or safeguards the OCREF4 signal on an external event
-/// @param  tim: select the TIM peripheral.
-/// @param  clear: new state of the Output Compare Clear Enable Bit.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCClear_Enable: TIM Output clear enable
-///     @arg TIM_OCClear_Disable: TIM Output clear disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ClearOC4Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4CEN, clear << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim channel 1 polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the OC1 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_OCPolarity_High: Output Compare active high
-///     @arg TIM_OCPolarity_Low: Output Compare active low
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC1PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
-{
-    MODIFY_REG(tim->CCER, TIM_CCER_CC1P, polarity);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Channel 1N polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the OC1N Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_OCNPolarity_High: Output Compare active high
-///     @arg TIM_OCNPolarity_Low: Output Compare active low
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC1NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
-{
-    MODIFY_REG(tim->CCER, TIM_CCER_CC1NP, polarity);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim channel 2 polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the OC2 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_OCPolarity_High: Output Compare active high
-///     @arg TIM_OCPolarity_Low: Output Compare active low
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC2PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
-{
-    MODIFY_REG(tim->CCER, TIM_CCER_CC2P, polarity << 4);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Channel 2N polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the OC2N Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_OCNPolarity_High: Output Compare active high
-///     @arg TIM_OCNPolarity_Low: Output Compare active low
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC2NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
-{
-    MODIFY_REG(tim->CCER, TIM_CCER_CC2NP, polarity << 4);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim channel 3 polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the OC3 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_OCPolarity_High: Output Compare active high
-///     @arg TIM_OCPolarity_Low: Output Compare active low
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC3PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
-{
-    MODIFY_REG(tim->CCER, TIM_CCER_CC3P, polarity << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Channel 3N polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the OC3N Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_OCNPolarity_High: Output Compare active high
-///     @arg TIM_OCNPolarity_Low: Output Compare active low
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC3NPolarityConfig(TIM_TypeDef* tim, TIMCCxNP_Typedef polarity)
-{
-    MODIFY_REG(tim->CCER, TIM_CCER_CC3NP, polarity << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim channel 4 polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the OC4 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_OCPolarity_High: Output Compare active high
-///     @arg TIM_OCPolarity_Low: Output Compare active low
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC4PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
-{
-    MODIFY_REG(tim->CCER, TIM_CCER_CC4P, polarity << 12);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the TIM Capture Compare Channel x.
-/// @param  tim:  select the TIM peripheral.
-/// @param  channel: specifies the TIM Channel
-///   This parameter can be one of the following values:
-///     @arg TIM_Channel_1: TIM Channel 1
-///     @arg TIM_Channel_2: TIM Channel 2
-///     @arg TIM_Channel_3: TIM Channel 3
-///     @arg TIM_Channel_4: TIM Channel 4
-///     @arg TIM_Channel_5: TIM Channel 5(Only for some MM32 TIM1/8)
-/// @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
-///   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_CCxCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxE_Typedef ccx_en)
-{
-    MODIFY_REG(tim->CCER, TIM_CCER_CC1EN << channel, ccx_en << channel);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the TIM Capture Compare Channel xN.
-/// @param  tim: select the TIM peripheral.
-/// @param  channel: specifies the TIM Channel
-///   This parameter can be one of the following values:
-///     @arg TIM_Channel_1: TIM Channel 1
-///     @arg TIM_Channel_2: TIM Channel 2
-///     @arg TIM_Channel_3: TIM Channel 3
-/// @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
-///   This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_CCxNCmd(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMCCxNE_Typedef ccxn_en)
-{
-    if (channel != TIM_Channel_4)
-        MODIFY_REG(tim->CCER, TIM_CCER_CC1NEN << channel, ccxn_en << channel);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the TIM Output Compare Mode.
-/// @note   This function disables the selected channel before changing the Output
-///         Compare Mode.
-///         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
-/// @param  tim:  select the TIM peripheral.
-/// @param  channel: specifies the TIM Channel
-///   This parameter can be one of the following values:
-///     @arg TIM_Channel_1: TIM Channel 1
-///     @arg TIM_Channel_2: TIM Channel 2
-///     @arg TIM_Channel_3: TIM Channel 3
-///     @arg TIM_Channel_4: TIM Channel 4
-/// @param  mode: specifies the TIM Output Compare Mode.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCMode_Timing
-///     @arg TIM_OCMode_Active
-///     @arg TIM_OCMode_Toggle
-///     @arg TIM_OCMode_PWM1
-///     @arg TIM_OCMode_PWM2
-///     @arg TIM_ForcedAction_Active
-///     @arg TIM_ForcedAction_InActive
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SelectOCxM(TIM_TypeDef* tim, TIMCHx_Typedef channel, TIMOCMODE_Typedef mode)
-{
-    CLEAR_BIT(tim->CCER, TIM_CCER_CC1EN << channel);
-    switch (channel) {
-        case TIM_Channel_1:
-            MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC1M, mode);
-            break;
-        case TIM_Channel_2:
-            MODIFY_REG(tim->CCMR1, TIM_CCMR1_OC2M, mode << 8);
-            break;
-        case TIM_Channel_3:
-            MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC3M, mode);
-            break;
-        case TIM_Channel_4:
-            MODIFY_REG(tim->CCMR2, TIM_CCMR2_OC4M, mode << 8);
-            break;
-        default:
-            break;
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or Disables the tim Update event.
-/// @param  tim:  select the TIM peripheral.
-/// @param  state: new state of the tim UDIS bit
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_UpdateDisableConfig(TIM_TypeDef* tim, FunctionalState state)
-{
-    (state) ? SET_BIT(tim->CR1, TIM_CR1_UDIS) : CLEAR_BIT(tim->CR1, TIM_CR1_UDIS);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Update Request Interrupt source.
-/// @param  tim:  select the TIM peripheral.
-/// @param  source: specifies the Update source.
-///   This parameter can be one of the following values:
-///     @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
-///                                    or the setting of UG bit, or an update generation
-///                                    through the slave mode controller.
-///     @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_UpdateRequestConfig(TIM_TypeDef* tim, TIMURS_Typedef source)
-{
-    MODIFY_REG(tim->CR1, TIM_CR1_URS, source);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the tim's Hall sensor interface.
-/// @param  tim: select the TIM peripheral.
-/// @param  state: new state of the tim Hall sensor interface.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SelectHallSensor(TIM_TypeDef* tim, FunctionalState state)
-{
-    (state) ? SET_BIT(tim->CR2, TIM_CR2_TI1S) : CLEAR_BIT(tim->CR2, TIM_CR2_TI1S);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the tim's One Pulse Mode.
-/// @param  tim:  select the TIM peripheral.
-/// @param  mode: specifies the OPM Mode to be used.
-///   This parameter can be one of the following values:
-///     @arg TIM_OPMode_Single
-///     @arg TIM_OPMode_Repetitive
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SelectOnePulseMode(TIM_TypeDef* tim, TIMOPMODE_Typedef mode)
-{
-    MODIFY_REG(tim->CR1, TIM_CR1_OPM, mode);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the tim Trigger Output Mode.
-/// @param  tim:select the TIM peripheral.
-/// @param  source: specifies the Trigger Output source.
-///   This paramter can be one of the following values:
-///  - For all tim
-///     @arg TIM_TRIGSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRIG).
-///     @arg TIM_TRIGSource_Enable: The Counter Enable CEN is used as the trigger output (TRIG).
-///     @arg TIM_TRIGSource_Update: The update event is selected as the trigger output (TRIG).
-///     @arg TIM_TRIGSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
-///                              is to be set, as soon as a capture or compare match occurs (TRIG).
-///     @arg TIM_TRIGSource_OC1Ref: OC1REF signal is used as the trigger output (TRIG).
-///     @arg TIM_TRIGSource_OC2Ref: OC2REF signal is used as the trigger output (TRIG).
-///     @arg TIM_TRIGSource_OC3Ref: OC3REF signal is used as the trigger output (TRIG).
-///     @arg TIM_TRIGSource_OC4Ref: OC4REF signal is used as the trigger output (TRIG).
-///
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SelectOutputTrigger(TIM_TypeDef* tim, TIMMMS_Typedef source)
-{
-    MODIFY_REG(tim->CR2, TIM_CR2_MMS, source);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the tim Slave Mode.
-/// @param  tim: select the TIM peripheral.
-/// @param  mode: specifies the Timer Slave Mode.
-///   This parameter can be one of the following values:
-///     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
-///                               the counter and triggers an update of the registers.
-///     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
-///     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
-///     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SelectSlaveMode(TIM_TypeDef* tim, TIMSMSMODE_Typedef mode)
-{
-    MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, mode);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets or Resets the tim Master/Slave Mode.
-/// @param  tim: select the TIM peripheral.
-/// @param  mode: specifies the Timer Master Slave Mode.
-///   This parameter can be one of the following values:
-///     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
-///                                      and its slaves (through TRIG).
-///     @arg TIM_MasterSlaveMode_Disable: No action
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* tim, TIMMSM_Typedef mode)
-{
-    MODIFY_REG(tim->SMCR, TIM_SMCR_MSM, mode);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Counter Register value
-/// @param  tim:  select the TIM peripheral.
-/// @param  auto_reload: specifies the Counter register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetAutoreload(TIM_TypeDef* tim, u16 auto_reload)
-{
-    WRITE_REG(tim->ARR, auto_reload);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Input Capture 1 prescaler.
-/// @param  tim:  select the TIM peripheral.
-/// @param  psc: specifies the Input Capture1 prescaler new value.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPSC_DIV1: no prescaler
-///     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-///     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-///     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetIC1Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC1PSC, psc);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Input Capture 2 prescaler.
-/// @param  tim: select the TIM peripheral.
-/// @param  psc: specifies the Input Capture2 prescaler new value.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPSC_DIV1: no prescaler
-///     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-///     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-///     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetIC2Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC2PSC, psc << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Input Capture 3 prescaler.
-/// @param  tim: select the TIM peripheral.
-/// @param  psc: specifies the Input Capture3 prescaler new value.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPSC_DIV1: no prescaler
-///     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-///     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-///     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetIC3Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC3PSC, psc);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Input Capture 4 prescaler.
-/// @param  tim: select the TIM peripheral.
-/// @param  psc: specifies the Input Capture4 prescaler new value.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPSC_DIV1: no prescaler
-///     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-///     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-///     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetIC4Prescaler(TIM_TypeDef* tim, TIMICPSC_Typedef psc)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC4PSC, psc << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Clock Division value.
-/// @param  tim:  select
-///   the TIM peripheral.
-/// @param  clock_div: specifies the clock division value.
-///   This parameter can be one of the following value:
-///     @arg TIM_CKD_DIV1: TDTS = Tck_tim
-///     @arg TIM_CKD_DIV2: TDTS = 2 * Tck_tim
-///     @arg TIM_CKD_DIV4: TDTS = 4 * Tck_tim
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetClockDivision(TIM_TypeDef* tim, TIMCKD_TypeDef clock_div)
-{
-    MODIFY_REG(tim->CR1, TIM_CR1_CKD, clock_div);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Counter Register value
-/// @param  tim:  select the TIM peripheral.
-/// @param  counter: specifies the Counter register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCounter(TIM_TypeDef* tim, u32 counter)
-{
-    if ((tim == TIM2) || (tim == TIM5))
-        WRITE_REG(tim->CNT, (u32)counter);
-    else
-        WRITE_REG(tim->CNT, (u16)counter);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Capture Compare1 Register value
-/// @param  tim:  select the TIM peripheral.
-/// @param  compare: specifies the Capture Compare1 register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCompare1(TIM_TypeDef* tim, u32 compare)
-{
-    if ((tim == TIM2) || (tim == TIM5))
-        WRITE_REG(tim->CCR1, (u32)compare);
-    else
-        WRITE_REG(tim->CCR1, (u16)compare);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Capture Compare2 Register value
-/// @param  tim: select the TIM peripheral.
-/// @param  compare: specifies the Capture Compare2 register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCompare2(TIM_TypeDef* tim, u32 compare)
-{
-    if ((tim == TIM2) || (tim == TIM5))
-        WRITE_REG(tim->CCR2, (u32)compare);
-    else
-        WRITE_REG(tim->CCR2, (u16)compare);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Capture Compare3 Register value
-/// @param  tim: select the TIM peripheral.
-/// @param  compare: specifies the Capture Compare3 register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCompare3(TIM_TypeDef* tim, u32 compare)
-{
-    if ((tim == TIM2) || (tim == TIM5))
-        WRITE_REG(tim->CCR3, (u32)compare);
-    else
-        WRITE_REG(tim->CCR3, (u16)compare);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Capture Compare4 Register value
-/// @param  tim:  select the TIM peripheral.
-/// @param  compare: specifies the Capture Compare4 register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCompare4(TIM_TypeDef* tim, u32 compare)
-{
-    if ((tim == TIM2) || (tim == TIM5))
-        WRITE_REG(tim->CCR4, (u32)compare);
-    else
-        WRITE_REG(tim->CCR4, (u16)compare);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Gets the tim Input Capture 1 value.
-/// @param  tim:  select the TIM peripheral.
-/// @retval Value: Capture Compare 1 Register value.
-////////////////////////////////////////////////////////////////////////////////
-u32 TIM_GetCapture1(TIM_TypeDef* tim)
-{
-    return tim->CCR1;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Gets the tim Input Capture 2 value.
-/// @param  tim: select the TIM peripheral.
-/// @retval Value: Capture Compare 2 Register value.
-////////////////////////////////////////////////////////////////////////////////
-u32 TIM_GetCapture2(TIM_TypeDef* tim)
-{
-    return tim->CCR2;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Gets the tim Input Capture 3 value.
-/// @param  tim: select the TIM peripheral.
-/// @retval Value: Capture Compare 3 Register value.
-////////////////////////////////////////////////////////////////////////////////
-u32 TIM_GetCapture3(TIM_TypeDef* tim)
-{
-    return tim->CCR3;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Gets the tim Input Capture 4 value.
-/// @param  tim: select the TIM peripheral.
-/// @retval Value: Capture Compare 4 Register value.
-////////////////////////////////////////////////////////////////////////////////
-u32 TIM_GetCapture4(TIM_TypeDef* tim)
-{
-    return tim->CCR4;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Gets the tim Counter value.
-/// @param  tim:  select the TIM peripheral.
-/// @retval Value: Counter Register value.
-////////////////////////////////////////////////////////////////////////////////
-u32 TIM_GetCounter(TIM_TypeDef* tim)
-{
-    return tim->CNT;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Gets the tim Prescaler value.
-/// @param  tim:  select the TIM peripheral.
-/// @retval Value: Prescaler Register value.
-////////////////////////////////////////////////////////////////////////////////
-u16 TIM_GetPrescaler(TIM_TypeDef* tim)
-{
-    return tim->PSC;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified TIM flag is set or not.
-/// @param  tim:  select the TIM peripheral.
-/// @param  flag: specifies the flag to check.
-///   This parameter can be one of the following values:
-///     @arg TIM_FLAG_Update: TIM update Flag
-///     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
-///     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
-///     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
-///     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
-///     @arg TIM_FLAG_COM: TIM Commutation Flag
-///     @arg TIM_FLAG_Trigger: TIM Trigger Flag
-///     @arg TIM_FLAG_Break: TIM Break Flag
-///     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
-///     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
-///     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
-///     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
-/// @note
-///   - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
-///   - TIM_FLAG_Break is used only with TIM1 and TIM8.
-///   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17.
-/// @retval State: The new state of TIM_FLAG (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* tim, TIMFLAG_Typedef flag)
-{
-    return ((tim->SR & flag) ? SET : RESET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the tim's pending flags.
-/// @param  tim:  select the TIM peripheral.
-/// @param  flag: specifies the flag bit to clear.
-///   This parameter can be any combination of the following values:
-///     @arg TIM_FLAG_Update: TIM update Flag
-///     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
-///     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
-///     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
-///     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
-///     @arg TIM_FLAG_COM: TIM Commutation Flag
-///     @arg TIM_FLAG_Trigger: TIM Trigger Flag
-///     @arg TIM_FLAG_Break: TIM Break Flag
-///     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
-///     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
-///     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
-///     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
-/// @note
-///   - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
-///   - TIM_FLAG_Break is used only with TIM1 and TIM8.
-///   - TIM_FLAG_COM is used only with TIM1, TIM8, TIM16 and TIM17.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ClearFlag(TIM_TypeDef* tim, TIMFLAG_Typedef flag)
-{
-    CLEAR_BIT(tim->SR, flag);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the TIM interrupt has occurred or not.
-/// @param  tim:  select the TIM peripheral.
-/// @param  it: specifies the TIM interrupt source to check.
-///   This parameter can be one of the following values:
-///     @arg TIM_IT_Update: TIM update Interrupt source
-///     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-///     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-///     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-///     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-///     @arg TIM_IT_COM: TIM Commutation Interrupt source
-///     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-///     @arg TIM_IT_Break: TIM Break Interrupt source
-/// @note
-///   - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
-///   - TIM_IT_Break is used only with TIM1 and TIM8.
-///   - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17.
-/// @retval State: The new state of the TIM_IT(SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus TIM_GetITStatus(TIM_TypeDef* tim, TIMIT_TypeDef it)
-{
-    return (((tim->SR & it) && (tim->DIER & it)) ? SET : RESET);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the tim's interrupt pending bits.
-/// @param  tim:  select the TIM peripheral.
-/// @param  it: specifies the pending bit to clear.
-///   This parameter can be any combination of the following values:
-///     @arg TIM_IT_Update: TIM1 update Interrupt source
-///     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-///     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-///     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-///     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-///     @arg TIM_IT_COM: TIM Commutation Interrupt source
-///     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-///     @arg TIM_IT_Break: TIM Break Interrupt source
-/// @note
-///   - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
-///   - TIM_IT_Break is used only with TIM1 and TIM8.
-///   - TIM_IT_COM is used only with TIM1, TIM8, TIM16 and TIM17.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ClearITPendingBit(TIM_TypeDef* tim,  u32 it)    //TIMIT_TypeDef
-{
-    CLEAR_BIT(tim->SR, it);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim channel 1 polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the IC1 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Rising
-///     @arg TIM_ICPolarity_Falling
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetIC1Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
-{
-    (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC1P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC1P);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim channel 2 polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the IC2 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Rising
-///     @arg TIM_ICPolarity_Falling
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetIC2Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
-{
-    (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC2P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC2P);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim channel 3 polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the IC3 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Rising
-///     @arg TIM_ICPolarity_Falling
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetIC3Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
-{
-    (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC3P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC3P);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim channel 4 polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the IC4 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Rising
-///     @arg TIM_ICPolarity_Falling
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetIC4Plority(TIM_TypeDef* tim, TIMICP_Typedef pol)
-{
-    (pol) ? SET_BIT(tim->CCER, TIM_CCER_CC4P) : CLEAR_BIT(tim->CCER, TIM_CCER_CC4P);
-}
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim Capture Compare 5 Register value
-/// @param  tim: select the TIM peripheral.
-/// @param  compare: specifies the Capture Compare5 register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCompare5(TIM_TypeDef* tim, u32 compare)
-{
-    WRITE_REG(tim->CCR5, (u16)compare);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Gets the tim Input Capture 5 value.
-/// @param  tim: select the TIM peripheral.
-/// @retval Value: Capture Compare 5 Register value.
-////////////////////////////////////////////////////////////////////////////////
-u32 TIM_GetCapture5(TIM_TypeDef* tim)
-{
-    return tim->CCR5;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the tim Channel5 according to the specified
-///         parameters in the init_struct.
-/// @param  tim: select the TIM peripheral.
-/// @param  init_struct: pointer to a TIM_OCInitTypeDef structure that
-///         contains the configuration information for the specified TIM peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC5Init(TIM_TypeDef* tim, TIM_OCInitTypeDef* init_struct)
-{
-    MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5M, (init_struct->TIM_OCMode) << 4);
-    MODIFY_REG(tim->CCER, TIM_CCER_CC5EN | TIM_CCER_CC5P,
-               (init_struct->TIM_OCPolarity << 16) | (init_struct->TIM_OutputState << 16));
-    WRITE_REG(tim->CCR4, init_struct->TIM_Pulse);
-
-    if ((tim == TIM1) || (tim == TIM8))
-        MODIFY_REG(tim->CR2, TIM_CR2_OIS5, init_struct->TIM_OCIdleState << 8);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the tim peripheral Preload register on CCR5.
-/// @param  tim: select the TIM peripheral.
-/// @param  preload: new state of the tim peripheral Preload register
-///   This parameter can be one of the following values:
-///     @arg TIM_OCPreload_Enable
-///     @arg TIM_OCPreload_Disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC5PreloadConfig(TIM_TypeDef* tim, TIMOCPE_Typedef preload)
-{
-    MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5PEN, preload);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim channel 5 polarity.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity: specifies the OC5 Polarity
-///   This parameter can be one of the following values:
-///     @arg TIM_OCPolarity_High: Output Compare active high
-///     @arg TIM_OCPolarity_Low: Output Compare active low
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC5PolarityConfig(TIM_TypeDef* tim, TIMCCxP_Typedef polarity)
-{
-    MODIFY_REG(tim->CCER, TIM_CCER_CC5P, polarity << 16);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configures the tim Output Compare 5 Fast feature.
-/// @param  tim: select the TIM peripheral.
-/// @param  fast: new state of the Output Compare Fast Enable Bit.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCFast_Enable: TIM output compare fast enable
-///     @arg TIM_OCFast_Disable: TIM output compare fast disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_OC5FastConfig(TIM_TypeDef* tim, TIMOCFE_Typedef fast)
-{
-    MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5FEN, fast);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears or safeguards the OCREF4 signal on an external event
-/// @param  tim: select the TIM peripheral.
-/// @param  clear: new state of the Output Compare Clear Enable Bit.
-///   This parameter can be one of the following values:
-///     @arg TIM_OCClear_Enable: TIM Output clear enable
-///     @arg TIM_OCClear_Disable: TIM Output clear disable
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_ClearOC5Ref(TIM_TypeDef* tim, TIMOCCE_Typedef clear)
-{
-    MODIFY_REG(tim->CCMR3, TIM_CCMR3_OC5CEN, clear);
-}
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the tim complementary PWM output Status after Break.
-/// @param  tim: select the TIM peripheral.
-/// @param  state: new state of the tim complementary PWM output.
-///   This parameter can be: ENABLE or DISABLE.
-///     @arg ENABLE: Direct output enable, no longer waiting for output after dead time.
-///     @arg DISABLE: Direct output disable, output waiting for dead time.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_DirectOutput(TIM_TypeDef* tim, FunctionalState state)
-{
-    (state) ? SET_BIT(tim->BDTR, TIM_BDTR_DOEN) : CLEAR_BIT(tim->BDTR, TIM_BDTR_DOEN);
-}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup TIM_Private_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configure the TI1 as Input.
-/// @param  tim:  select the TIM peripheral.
-/// @param  polarity : The Input Polarity.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Rising
-///     @arg TIM_ICPolarity_Falling
-/// @param  selection: specifies the input to be used.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
-///     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
-///     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
-/// @param  filter: Specifies the Input Capture Filter.
-///   This parameter must be a value between 0x00 and 0x0F.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-static void TI1_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC1S | TIM_CCMR1_IC1F, (filter << 4) | selection);
-    MODIFY_REG(tim->CCER, TIM_CCER_CC1EN | TIM_CCER_CC1P, polarity | TIM_CCER_CC1EN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configure the TI2 as Input.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity : The Input Polarity.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Rising
-///     @arg TIM_ICPolarity_Falling
-/// @param  selection: specifies the input to be used.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
-///     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
-///     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
-/// @param  filter: Specifies the Input Capture Filter.
-///   This parameter must be a value between 0x00 and 0x0F.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-static void TI2_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
-{
-    MODIFY_REG(tim->CCMR1, TIM_CCMR1_CC2S | TIM_CCMR1_IC2F, (filter << 12) | (selection << 8));
-    MODIFY_REG(tim->CCER, TIM_CCER_CC2EN | TIM_CCER_CC2P, (polarity << 4) | TIM_CCER_CC2EN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configure the TI3 as Input.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity : The Input Polarity.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Rising
-///     @arg TIM_ICPolarity_Falling
-/// @param  selection: specifies the input to be used.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
-///     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
-///     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
-/// @param  filter: Specifies the Input Capture Filter.
-///   This parameter must be a value between 0x00 and 0x0F.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-static void TI3_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC3S | TIM_CCMR2_IC3F, (filter << 4) | selection);
-    MODIFY_REG(tim->CCER, TIM_CCER_CC3EN | TIM_CCER_CC3P, (polarity << 8) | TIM_CCER_CC3EN);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Configure the TI4 as Input.
-/// @param  tim: select the TIM peripheral.
-/// @param  polarity : The Input Polarity.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICPolarity_Rising
-///     @arg TIM_ICPolarity_Falling
-/// @param  selection: specifies the input to be used.
-///   This parameter can be one of the following values:
-///     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
-///     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
-///     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
-/// @param  filter: Specifies the Input Capture Filter.
-///   This parameter must be a value between 0x00 and 0x0F.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-static void TI4_Configure(TIM_TypeDef* tim, u16 polarity, u16 selection, u16 filter)
-{
-    MODIFY_REG(tim->CCMR2, TIM_CCMR2_CC4S | TIM_CCMR2_IC4F, (filter << 12) | (selection << 8));
-    MODIFY_REG(tim->CCER, TIM_CCER_CC4EN | TIM_CCER_CC4P, (polarity << 12) | TIM_CCER_CC4EN);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified TIM PWM shift /DMA reqeat.
-/// @param  tim: select the tim peripheral.
-/// @param  it: Specifies the TIM PWM shift channel to enable or disable.
-///   This parameter can be any combination of the following values:
-///     @arg TIM_PDER_CCDREPE: TIM DMA reqeat enable bit
-///     @arg TIM_PDER_CCR1SHIFTEN: TIM Channel 1 output PWM phase shift enable bit
-///     @arg TIM_PDER_CCR2SHIFTEN: TIM Channel 2 output PWM phase shift enable bit
-///     @arg TIM_PDER_CCR3SHIFTEN: TIM Channel 3 output PWM phase shift enable bit
-///     @arg TIM_PDER_CCR4SHIFTEN: TIM Channel 4 output PWM phase shift enable bit
-///     @arg TIM_PDER_CCR5SHIFTEN: TIM Channel 5 output PWM phase shift enable bit
-/// @param  state: new state of the TIM interrupts.
-///   This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_PWMShiftConfig(TIM_TypeDef* tim, u32 it, FunctionalState state)//TIMIT_TypeDef
-{
-    (state) ? SET_BIT(tim->PDER, it) : CLEAR_BIT(tim->PDER, it);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim CCR1 shift Register value
-/// @param  tim:  select the TIM peripheral.
-/// @param  compare: specifies the Capture Compare1 register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCCR1FALL(TIM_TypeDef* tim, u32 shift)
-{
-    if (tim == TIM1)
-        WRITE_REG(tim->CCR1FALL, (u32)shift);
-
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim CCR2 shift Register value
-/// @param  tim:  select the TIM peripheral.
-/// @param  compare: specifies the Capture Compare1 register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCCR2FALL(TIM_TypeDef* tim, u32 shift)
-{
-    if (tim == TIM1)
-        WRITE_REG(tim->CCR2FALL, (u32)shift);
-
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim CCR3 shift Register value
-/// @param  tim:  select the TIM peripheral.
-/// @param  compare: specifies the Capture Compare1 register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCCR3FALL(TIM_TypeDef* tim, u32 shift)
-{
-    if (tim == TIM1)
-        WRITE_REG(tim->CCR3FALL, (u32)shift);
-
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim CCR4 shift Register value
-/// @param  tim:  select the TIM peripheral.
-/// @param  compare: specifies the Capture Compare1 register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCCR4FALL(TIM_TypeDef* tim, u32 shift)
-{
-    if (tim == TIM1)
-        WRITE_REG(tim->CCR4FALL, (u32)shift);
-
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the tim CCR5 shift Register value
-/// @param  tim:  select the TIM peripheral.
-/// @param  compare: specifies the Capture Compare1 register new value.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void TIM_SetCCR5FALL(TIM_TypeDef* tim, u32 shift)
-{
-    if (tim == TIM1)
-        WRITE_REG(tim->CCR5FALL, (u32)shift);
-
-}
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c
deleted file mode 100644
index 2a0578f91..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c
+++ /dev/null
@@ -1,502 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_uart.c
-/// @file     hal_uart.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE UART FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_UART_C_
-
-// Files includes
-#include "hal_rcc.h"
-#include "hal_uart.h"
-#include "hal_gpio.h"
-#include "hal_dma.h"
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-///@addtogroup UART_HAL
-///@{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup UART_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the uart peripheral registers to their
-///         default reset values.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_DeInit(UART_TypeDef* uart)
-{
-
-
-    if(UART2 == uart) {
-        exRCC_APB1PeriphReset(RCC_APB1ENR_UART2);
-    }
-    if(UART1 == uart) {
-        exRCC_APB2PeriphReset(RCC_APB2ENR_UART1);
-    }
-    if(UART3 == uart) {
-        exRCC_APB1PeriphReset(RCC_APB1ENR_UART3);
-    }
-    if(UART4 == uart) {
-        exRCC_APB1PeriphReset(RCC_APB1ENR_UART4);
-    }
-    if(UART5 == uart) {
-        exRCC_APB1PeriphReset(RCC_APB1ENR_UART5);
-    }
-    if(UART6 == uart) {
-        exRCC_APB2PeriphReset(RCC_APB2ENR_UART6);
-    }
-    if(UART7 == uart) {
-        exRCC_APB1PeriphReset(RCC_APB1ENR_UART7);
-    }
-    if(UART8 == uart) {
-        exRCC_APB1PeriphReset(RCC_APB1ENR_UART8);
-    }
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Initializes the uart peripheral according to the specified
-///         parameters in the UART_InitStruct .
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  init_struct: pointer to a UART_InitTypeDef structure
-///         that contains the configuration information for the
-///         specified UART peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_Init(UART_TypeDef* uart, UART_InitTypeDef* init_struct)
-{
-    u32 apbclock = 0x00;
-    // UART CCR Configuration
-    MODIFY_REG(uart->CCR, UART_CCR_CHAR, init_struct->WordLength);
-
-
-    MODIFY_REG(uart->CCR, (UART_CCR_SPB0 | UART_CCR_SPB1), init_struct->StopBits);
-
-    MODIFY_REG(uart->CCR, (UART_CCR_PEN | UART_CCR_PSEL), init_struct->Parity);
-
-    // UART GCR Configuration
-    MODIFY_REG(uart->GCR, (UART_GCR_TX | UART_GCR_RX), init_struct->Mode);
-    MODIFY_REG(uart->GCR, UART_GCR_AUTOFLOW, init_struct->HWFlowControl);
-
-    //UART BRR Configuration
-    //Configure the UART Baud Rate
-    if (uart == UART1) {
-
-        apbclock = RCC_GetPCLK2Freq();
-    }
-    else {
-        apbclock = RCC_GetPCLK1Freq();
-    }
-    // Determine the UART_baud
-    uart->BRR = (apbclock / init_struct->BaudRate) / 16;
-    uart->FRA = (apbclock / init_struct->BaudRate) % 16;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Fills each UART_InitStruct member with its default value.
-/// @param  init_struct: pointer to a UART_InitTypeDef structure
-///         which will be initialized.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_StructInit(UART_InitTypeDef* init_struct)
-{
-    // UART_InitStruct members default value
-    init_struct->BaudRate       = 9600;
-    init_struct->WordLength     = UART_WordLength_8b;
-    init_struct->StopBits       = UART_StopBits_1;
-    init_struct->Parity         = UART_Parity_No;
-    init_struct->Mode           = UART_GCR_RX | UART_GCR_TX;
-    init_struct->HWFlowControl  = UART_HWFlowControl_None;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified UART peripheral.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  state: new state of the uart peripheral.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_Cmd(UART_TypeDef* uart, FunctionalState state)
-{
-    MODIFY_REG(uart->GCR, UART_GCR_UART, state << UART_GCR_UART_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the specified UART interrupts.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  it: specifies the UART interrupt sources to be
-///         enabled or disabled.
-///         This parameter can be one of the following values:
-/// @arg    UART_IT_ERR:  Error interrupt(Frame error,)
-/// @arg    UART_IT_PE:   Parity Error interrupt
-/// @arg    UART_OVER_ERR:  overrun Error interrupt
-/// @arg    UART_IT_RXIEN: Receive Data register interrupt
-/// @arg    UART_IT_TXIEN:  Tansmit Data Register empty interrupt
-///
-/// @param  state: new state of the specified uart interrupts.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_ITConfig(UART_TypeDef* uart, u16 it, FunctionalState state)
-{
-    (state) ? (uart->IER |= it) : (uart->IER &= ~it);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the UART DMA interface.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  dma_request: specifies the DMA request.
-///         This parameter can be any combination of the following values:
-/// @arg    UART_DMAReq_EN: UART DMA transmit request
-///
-/// @param  state: new state of the DMA Request sources.
-///         This parameter can be: ENABLE or DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_DMACmd(UART_TypeDef* uart, u16 dma_request, FunctionalState state)
-{
-    MODIFY_REG(uart->GCR, UART_GCR_DMA, state << UART_GCR_DMA_Pos);
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Transmits single data through the uart peripheral.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  Data: the data to transmit.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_SendData(UART_TypeDef* uart, u16 value)
-{
-    // Transmit Data
-    WRITE_REG(uart->TDR, (value & 0xFFU));
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the most recent received data by the uart peripheral.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @retval  The received data.
-////////////////////////////////////////////////////////////////////////////////
-u16 UART_ReceiveData(UART_TypeDef* uart)
-{
-    // Receive Data
-    return (u16)(uart->RDR & 0xFFU);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified UART flag is set or not.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  flag: specifies the flag to check.
-///         This parameter can be one of the following values:
-/// @arg    UART_FLAG_TXEMPTY: Transmit data register empty flag
-/// @arg    UART_FLAG_TXFULL: Transmit data buffer full
-/// @arg    UART_FLAG_RXAVL: RX Buffer has a byte flag
-/// @arg    UART_FLAG_TXEPT: tx and shifter are emptys flag
-/// @retval  The new state of UART_FLAG (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus UART_GetFlagStatus(UART_TypeDef* uart, u16 flag)
-{
-    return (uart->CSR & flag) ? SET : RESET;
-}
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the specified UART interrupt has occurred or not.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  it: specifies the UART interrupt source to check.
-///         This parameter can be one of the following values:
-/// @arg    UART_IT_ERR:  Error interrupt(Frame error,)
-/// @arg    UART_IT_PE:   Parity Error interrupt
-/// @arg    UART_OVER_ERR:  overrun Error interrupt
-/// @arg    UART_IT_RXIEN: Receive Data register interrupt
-/// @arg    UART_IT_TXIEN:  Tansmit Data Register empty interrupt
-/// @retval  The new state of UART_IT (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-ITStatus UART_GetITStatus(UART_TypeDef* uart, u16 it)
-{
-    return (uart->ISR & it) ? SET : RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears the uart interrupt pending bits.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  it: specifies the interrupt pending bit to clear.
-///         This parameter can be one of the following values:
-/// @arg    UART_IT_ERR:  Error interrupt(Frame error,)
-/// @arg    UART_IT_PE:   Parity Error interrupt
-/// @arg    UART_OVER_ERR:  overrun Error interrupt
-/// @arg    UART_IT_RXIEN: Receive Data register interrupt
-/// @arg    UART_IT_TXIEN:  Tansmit Data Register empty interrupt
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_ClearITPendingBit(UART_TypeDef* uart, u16 it)
-{
-    //clear UART_IT pendings bit
-    uart->ICR = it;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Selects the UART WakeUp method.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  mode: specifies the UART wakeup method.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_WakeUpConfig(UART_TypeDef* uart, UART_WakeUp_TypeDef mode)
-{
-    MODIFY_REG(uart->CCR, UART_CCR_WAKE, mode);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Determines if the UART is in mute mode or not.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  state: new state of the UART mute mode.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_ReceiverWakeUpCmd(UART_TypeDef* uart, FunctionalState state)
-{
-    MODIFY_REG(uart->CCR, UART_CCR_RWU, state << UART_CCR_RWU_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the address of the UART Rx Address.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  address: Indicates the address of the UART Rx Address.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_SetRXAddress(UART_TypeDef* uart, u8 address)
-{
-    MODIFY_REG(uart->RXAR, UART_RXAR_ADDR, address);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the address of the UART Rx MASK.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  address: Indicates the address of the UART Rx MASK.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_SetRXMASK(UART_TypeDef* uart, u8 address)
-{
-    MODIFY_REG(uart->RXMR, UART_RXMR_MASK, address);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  ENBALE or DISABLE the UART's 9bit.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  state: new state of the UART 9 bit.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_Enable9bit(UART_TypeDef* uart, FunctionalState state)
-{
-    MODIFY_REG(uart->CCR, UART_CCR_B8EN, state << UART_CCR_B8EN_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the UART's 9bit Level.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  state: new state of the UART 9 bit.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_Set9bitLevel(UART_TypeDef* uart, FunctionalState state)
-{
-    MODIFY_REG(uart->CCR, UART_CCR_B8TXD, state << UART_CCR_B8TXD_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the UART's 9bit Polarity.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  polarity: new state of the UART 9 bit Polarity.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_Set9bitPolarity(UART_TypeDef* uart, UART_9bit_Polarity_TypeDef polarity)
-{
-    MODIFY_REG(uart->CCR, UART_CCR_B8POL, polarity);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Set the UART's 9bit Automatic Toggle.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  state: new state of the UART 9 bit Automatic Toggle.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_Set9bitAutomaticToggle(UART_TypeDef* uart, FunctionalState state)
-{
-    MODIFY_REG(uart->CCR, UART_CCR_B8TOG, state << UART_CCR_B8TOG_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the UART Half Duplex communication.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  state: new state of the UART Communication.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_HalfDuplexCmd(UART_TypeDef* uart, FunctionalState state)
-{
-    MODIFY_REG(uart->SCR, UART_SCR_HDSEL, state << UART_SCR_HDSEL_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the specified UART guard time.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  guard_time: specifies the guard time.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_SetGuardTime(UART_TypeDef* uart, u8 guard_time)
-{
-    MODIFY_REG(uart->SCR, UART_SCR_SCFCNT, guard_time << UART_SCR_SCFCNT_Pos);
-    // Clear the UART Guard time
-    // uart->SCR &= SCR_SCFCNT_Mask;
-    // Set the UART guard time
-    // uart->SCR |= (u16)((u16)guard_time << 0x04);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables the UART's Smart Card mode.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  state: new state of the Smart Card mode.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_SmartCardCmd(UART_TypeDef* uart, FunctionalState state)
-{
-    MODIFY_REG(uart->SCR, UART_SCR_SCEN, state << UART_SCR_SCEN_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables or disables NACK transmission.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  state: new state of the NACK transmission.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_SmartCardNACKCmd(UART_TypeDef* uart, FunctionalState state)
-{
-    MODIFY_REG(uart->SCR, UART_SCR_SCARB, state << UART_SCR_SCARB_Pos);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Transmits break characters.
-/// @param  uart: Select the UART or the UART peripheral.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_SendBreak(UART_TypeDef* uart)
-{
-    SET_BIT(uart->CCR, UART_CCR_BRK);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enable or Disable Auto Baud-Rate Detection
-/// @param  uart: Select the UART or the UART peripheral.
-/// @param  state: new state of the UART AutoBaudRate Detection.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_AutoBaudRateCmd(UART_TypeDef* uart, FunctionalState state)
-{
-    state ? SET_BIT(uart->ABRCR, UART_ABRCR_ABREN) : CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN) ;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  AutoBaudRate.
-/// @param  uart: Select the UART or the UART peripheral.
-///         value: special character.
-///         state: ENABLE/DISABLE.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void UART_AutoBaudRateSet(UART_TypeDef* uart, UART_AutoBaud_TypeDef value, FunctionalState state)
-{
-    CLEAR_BIT(uart->ABRCR, UART_ABRCR_ABREN);
-    //This bit field can only be written when ABREN = 0 or the UART is disabled (UARTEN=0).
-
-    if ((value == ABRMODE_FALLING_TO_RISINGEDGE1BIT) || (value == ABRMODE_STARTBIT) || (value == ABRMODE_VALUE0XFF)) {
-        //UART measures the duration of the start bit (falling edge) to first rising edge
-        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = one bit
-        //___   _               _______
-        //   |_|1 x x x x x x x|        = Bxxxx xxx1  F to U = 1 start bit
-        //
-        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
-                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE0 );
-    }
-    else if((value == ABRMODE_FALLING_TO_RISINGEDGE2BIT) || (value == Data_FE))  {
-        //UART measures the duration of the start bit (falling edge) to first rising edge
-        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = two bit
-        //___     _             _______
-        //   |_ _|1 x x x x x x|        = Bxxxx xx10  F to U = 2
-        //
-        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
-                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE1);
-    }
-    else if((value == ABRMODE_FALLING_TO_RISINGEDGE4BIT) || (value == Data_F8)) {
-        //UART measures the duration of the start bit (falling edge) to first rising edge
-        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = four bit
-        //___         _         _______
-        //   |_ _ _ _|1 x x x x|        = Bxxxx 1000  F to U = 4
-        //
-        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
-                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE2);
-    }
-    else if((value == ABRMODE_FALLING_TO_RISINGEDGE8BIT) || (value == ABRMODE_VALUE0X80))  {
-        //UART measures the duration of the start bit (falling edge) to first rising edge
-        //FORMER edge = 0  LATTER edge= 1, from fist falling edge to rising edge = eight bit
-        //___                 _ ______
-        //   |_ _ _ _ _ _ _ _|1         = B1000 0000  F to U = 8
-        //
-        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
-                   UART_ABRCR_LATTER | UART_ABRCR_BITCNT_MODE3);
-    }
-    else if((value == ABRMODE_FALLING_TO_FALLINGEDGE2BIT) || (value == ABRMODE_VALUE0X55)) {
-        //UART measures the duration of the start bit (falling edge) to next falling edge
-        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = two bit
-        //___   _               ______
-        //   |_|1|_|x x x x x x|        = Bxxxx xx01  F to F = 2 0x55 and Falling to Falling
-        //
-        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
-                   UART_ABRCR_BITCNT_MODE1);
-    }
-    else if((value == ABRMODE_FALLING_TO_FALLINGEDGE4BIT) || (value == ABRMODE_VALUE0XF7))  {
-        //UART measures the duration of the start bit (falling edge) to next falling edge
-        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = four bit
-        //___   _ _ _           ______
-        //   |_|1 1 1|_|x x x x|        = Bxxxx 0111  F to F = 4
-        //
-        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
-                   UART_ABRCR_BITCNT_MODE2);
-    }
-    else if((value == ABRMODE_FALLING_TO_FALLINGEDGE8BIT) || (value == ABRMODE_VALUE0x7F)) {
-        //UART measures the duration of the start bit (falling edge) to next falling edge
-        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = eight bit
-        //___   _ _ _ _ _ _ _   ______
-        //   |_|1 1 1 1 1 1 1|_|        = B0111 1111  F to F = 8 0x7F
-        //
-        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
-                   UART_ABRCR_BITCNT_MODE3);
-    }
-
-    else {
-        //UART measures the duration of the start bit (falling edge) to next falling edge
-        //FORMER edge = 0  LATTER edge= 0, from fist falling edge to next falling edge = eight bit
-        //___   _ _ _ _ _ _ _   ______
-        //   |_|1 1 1 1 1 1 1|_|        = B0111 1111  F to F = 8 0x7F
-        //
-        MODIFY_REG(uart->ABRCR, UART_ABRCR_LATTER | UART_ABRCR_FORMER | UART_ABRCR_BITCNT, \
-                   UART_ABRCR_BITCNT_MODE3);
-    }
-    if(state == ENABLE) {
-        SET_BIT(uart->ABRCR, UART_ABRCR_ABREN);
-    }
-}
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c
deleted file mode 100644
index e51bfcade..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uid.c
+++ /dev/null
@@ -1,55 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_uid.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE UID FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_UID_C_
-
-// Files includes
-#include "hal_uid.h"
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-///@addtogroup UID_HAL
-///@{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup UID_Exported_Functions
-/// @{
-
-u8 device_id_data[12] = {0};
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Get device ID.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void GetChipUID(void)
-{
-    u8 i;
-
-    for (i = 0; i < 12; i++) {
-        device_id_data[i] = *((vu8*)(UID_BASE + i));
-    }
-}
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c
deleted file mode 100644
index 9d771396c..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_ver.c
+++ /dev/null
@@ -1,131 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_ver.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE LIB AND THE CHIPSET INFORMATION.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_VER_C_
-
-// Files includes
-#include "hal_ver.h"
-
-
-// MM32 Library version is 0.90
-
-#define __MM32_LIB_VERSION_MAIN         (0x0U)                                  //!< [31:24] main version 
-#define __MM32_LIB_VERSION_SUB1         (0x9U)                                  //!< [23:16] sub1 version
-#define __MM32_LIB_VERSION_SUB2         (0x0U)                                  //!< [15:8]  sub2 version
-#define __MM32_LIB_VERSION_RC           (0x00U)                                 //!< [7:0]  release candidate
-#define __MM32_LIB_VERSION              ((__MM32_LIB_VERSION_MAIN << 24U)\
-                                         |(__MM32_LIB_VERSION_SUB1 << 16U)\
-                                         |(__MM32_LIB_VERSION_SUB2 << 8U )\
-                                         |(__MM32_LIB_VERSION_RC))
-
-// MM32 Library release date is 2021-05-10 (YYYY-MM-DD)
-#define __MM32_LIB_RELESE_YEARH         (0x20U)                                  //!< [31:24] release year high 
-#define __MM32_LIB_RELESE_YEARL         (0x21U)                                  //!< [23:16] release year low
-#define __MM32_LIB_RELESE_MONTH         (0x05U)                                  //!< [15:8]  release month
-#define __MM32_LIB_RELESE_DAY           (0x10U)                                //!< [7:0]   release day
-#define __MM32_LIB_RELESE_DATE          ((__MM32_LIB_RELESE_YEARH << 24U)\
-                                         |(__MM32_LIB_RELESE_YEARL << 16U)\
-                                         |(__MM32_LIB_RELESE_MONTH << 8U )\
-                                         |(__MM32_LIB_RELESE_DAY))
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-///@addtogroup VER_HAL
-///@{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup Lib and chipset_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  This method returns the Lib revision.
-/// @param  None.
-/// @retval return the Lib version.
-////////////////////////////////////////////////////////////////////////////////
-u32 Get_MM32LibVersion(void)
-{
-    return __MM32_LIB_VERSION;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  This method returns the Lib release date.
-/// @param  None.
-/// @retval return the Lib release date.
-////////////////////////////////////////////////////////////////////////////////
-u32 Get_MM32LibReleaseDate(void)
-{
-    return __MM32_LIB_RELESE_DATE;
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the device revision identifier.
-/// @param  None.
-/// @retval return the device revision identifier.
-////////////////////////////////////////////////////////////////////////////////
-u32 Get_ChipsetREVID(void)
-{
-    return((DBGMCU->IDCODE) & 0xF );
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns the device identifier..
-/// @param  None.
-/// @retval return the device Device identifier.
-////////////////////////////////////////////////////////////////////////////////
-u32 Get_ChipsetDEVID(void)
-{
-    return((DBGMCU->IDCODE) );
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns first word of the unique device identifier (UID based on 96 bits)
-/// @param  None.
-/// @retval Device identifier
-////////////////////////////////////////////////////////////////////////////////
-u32 Get_ChipsetUIDw0(void)
-{
-    return(READ_REG(*((vu32*)UID_BASE)));
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns second word of the unique device identifier (UID based on 96 bits)
-/// @param  None.
-/// @retval Device identifier
-////////////////////////////////////////////////////////////////////////////////
-u32 Get_ChipsetUIDw1(void)
-{
-    return(READ_REG(*((vu32*)(UID_BASE + 4U))));
-}
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Returns third word of the unique device identifier (UID based on 96 bits)
-/// @param  None.
-/// @retval Device identifier
-////////////////////////////////////////////////////////////////////////////////
-u32 Get_ChipsetUIDw2(void)
-{
-    return(READ_REG(*((vu32*)(UID_BASE + 8U))));
-}
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c b/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c
deleted file mode 100644
index 05d74b596..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/HAL_Lib/Src/hal_wwdg.c
+++ /dev/null
@@ -1,147 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     hal_wwdg.c
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE WWDG FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _HAL_WWDG_C_
-
-// Files includes
-#include "hal_wwdg.h"
-#include "hal_rcc.h"
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup MM32_Hardware_Abstract_Layer
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup WWDG_HAL
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @addtogroup WWDG_Exported_Functions
-/// @{
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Deinitializes the WWDG peripheral registers to their default reset
-/// values.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void WWDG_DeInit()
-{
-    exRCC_APB1PeriphReset(RCC_APB1RSTR_WWDG);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the WWDG Prescaler.
-/// @param  WWDG_Prescaler: specifies the WWDG Prescaler.
-///         This parameter can be one of the following values:
-///             @arg WWDG_Prescaler_1: WWDG counter clock = APB1CLK / 4096 / 1
-///             @arg WWDG_Prescaler_2: WWDG counter clock = APB1CLK / 4096 / 2
-///             @arg WWDG_Prescaler_4: WWDG counter clock = APB1CLK / 4096 / 4
-///             @arg WWDG_Prescaler_8: WWDG counter clock = APB1CLK / 4096 / 8
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void WWDG_SetPrescaler(u32 prescaler)
-{
-    WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WDGTB) | prescaler;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the WWDG window value.
-/// @param  WindowValue: specifies the window value to be compared to the
-/// downcounter.
-///          This parameter value must be lower than 0x80.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void WWDG_SetWindowValue(u8 window_value)
-{
-    WWDG->CFGR = (WWDG->CFGR & ~WWDG_CFGR_WINDOW) | (window_value & WWDG_CFGR_WINDOW);
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables the WWDG Early Wakeup interrupt(EWI).
-/// @note   Once enabled this interrupt cannot be disabled except by a system
-/// reset.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void WWDG_EnableIT()
-{
-    WWDG->CFGR |= WWDG_CFGR_EWI;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Sets the WWDG counter value.
-/// @param  Counter: specifies the watchdog counter value.
-///         This parameter must be a number between 0x40 and 0x7F (to prevent
-///         generating an immediate reset).
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void WWDG_SetCounter(u8 count)
-{
-    WWDG->CR = count & WWDG_CFGR_WINDOW;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables WWDG and load the counter value.
-/// @param  Counter: specifies the watchdog counter value.
-///         This parameter must be a number between 0x40 and 0x7F (to prevent
-///         generating an immediate reset).
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-u32 WWDG_GetCounter()
-{
-    return WWDG->CR & WWDG_CR_CNT;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Enables WWDG and load the counter value.
-/// @param  Counter: specifies the watchdog counter value.
-///         This parameter must be a number between 0x40 and 0x7F (to prevent
-///         generating an immediate reset).
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void WWDG_Enable(u8 count)
-{
-    WWDG->CR = WWDG_CR_WDGA | count;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Checks whether the Early Wakeup interrupt flag is set or not.
-/// @param  None.
-/// @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
-////////////////////////////////////////////////////////////////////////////////
-FlagStatus WWDG_GetFlagStatus()
-{
-    return WWDG->SR ? SET : RESET;
-}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  Clears Early Wakeup interrupt flag.
-/// @param  None.
-/// @retval None.
-////////////////////////////////////////////////////////////////////////////////
-void WWDG_ClearFlag()
-{
-    WWDG->SR &= ~WWDG_SR_EWIF;
-}
-
-/// @}
-
-/// @}
-
-/// @}
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h
deleted file mode 100644
index 1a85c131a..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_device.h
+++ /dev/null
@@ -1,23 +0,0 @@
-///-----------------------------------------------------------------------------
-/// @file mm32_device.h
-/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion
-///        microcontroller devices
-///
-/// This is a convenience header file for defining the part number on the
-/// build command line, instead of specifying the part specific header file.
-///
-/// Example: Add MM32 series to your build options, to define part
-///          Add "#include "mm32_device.h" to your source files
-///
-///
-///
-///
-///-----------------------------------------------------------------------------
-
-#ifndef __MM32_DEVICE_H
-#define __MM32_DEVICE_H
-
-#include "mm32_reg.h"
-
-#endif // __MM32_DEVICE_H 
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h
deleted file mode 100644
index dfba84215..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg.h
+++ /dev/null
@@ -1,71 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     mm32_reg.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-////////////////////////////////////////////////////////////////////////////////
-#ifndef __MM32_REG_H
-#define __MM32_REG_H
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#include "reg_common.h"
-#include "reg_adc.h"
-#include "reg_bkp.h"
-#include "reg_can.h"
-#include "reg_comp.h"
-#include "reg_crc.h"
-#include "reg_crs.h"
-#include "reg_dac.h"
-#include "reg_dbg.h"
-#include "reg_dma.h"
-#include "reg_exti.h"
-#include "reg_eth.h"
-#include "reg_flash.h"
-#include "reg_gpio.h"
-#include "reg_i2c.h"
-#include "reg_iwdg.h"
-#include "reg_pwm.h"
-#include "reg_pwr.h"
-#include "reg_rcc.h"
-#include "reg_rtc.h"
-#include "reg_sdio.h"
-#include "reg_spi.h"
-#include "reg_syscfg.h"
-#include "reg_tim.h"
-#include "reg_uart.h"
-#include "reg_usb_otg_fs.h"
-#include "reg_wwdg.h"
-
-////////////////////////////////////////////////////////////////////////////////
-#include "mm32_reg_redefine_v1.h"
-////////////////////////////////////////////////////////////////////////////////
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif // __MM32_REG_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h
deleted file mode 100644
index 6cdd79ead..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/mm32_reg_redefine_v1.h
+++ /dev/null
@@ -1,1175 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     mm32_reg_define_v1.H
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE define for version compatibility define
-///           FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __MM32_REG_DEFINE_V1_H
-#define __MM32_REG_DEFINE_V1_H
-
-// Files includes
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Version compatibility definition
-////////////////////////////////////////////////////////////////////////////////
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief redefine for register
-////////////////////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-/// @brief redefine for ADC of MCU register
-////////////////////////////////////////////////////////////////////////////////
-
-#define ADC_COMP_IRQHandler             ADC1_COMP_IRQHandler
-
-#define ADDATA_DATA                     ADC_DR_DATA
-
-#define ADDATA_CHANNELSEL               ADC_DR_CH
-#define ADDATA_CHANNELSEL_0             ADC_DR_CH0
-#define ADDATA_CHANNELSEL_1             ADC_DR_CH1
-#define ADDATA_CHANNELSEL_2             ADC_DR_CH2
-#define ADDATA_CHANNELSEL_3             ADC_DR_CH3
-#define ADDATA_CHANNELSEL_4             ADC_DR_CH4
-#define ADDATA_CHANNELSEL_5             ADC_DR_CH5
-#define ADDATA_CHANNELSEL_6             ADC_DR_CH6
-#define ADDATA_CHANNELSEL_7             ADC_DR_CH7
-
-
-
-
-#define ADDATA_CHANNELSEL_CH8           ADC_DR_CH8
-#define ADDATA_CHANNELSEL_CH9           ADC_DR_CH9
-#define ADDATA_CHANNELSEL_CH10          ADC_DR_CH10
-#define ADDATA_CHANNELSEL_CH11          ADC_DR_CH11
-#define ADDATA_CHANNELSEL_CH12          ADC_DR_CH12
-#define ADDATA_CHANNELSEL_CH13          ADC_DR_CH13
-#define ADDATA_CHANNELSEL_CH14          ADC_DR_CH14
-#define ADDATA_CHANNELSEL_CH15          ADC_DR_CH15
-#define ADDATA_CHANNELSEL_TempSensor    ADC_DR_TempSensor
-#define ADDATA_CHANNELSEL_VolSensor     ADC_DR_VoltRef
-
-
-#define ADDATA_OVERRUN                  ADC_DR_OVERRUN
-#define ADDATA_VALID                    ADC_DR_VALID
-
-#define ADCFG_ADEN                      ADC_CFGR_ADEN
-#define ADCFG_ADWEN                     ADC_CFGR_ADWEN
-
-#define ADCFG_RSLTCTL                   ADC_CFGR_RSLTCTL
-#define ADCFG_RSLTCTL_12                ADC_CFGR_RSLTCTL_12
-#define ADCFG_RSLTCTL_11                ADC_CFGR_RSLTCTL_11
-#define ADCFG_RSLTCTL_10                ADC_CFGR_RSLTCTL_10
-#define ADCFG_RSLTCTL_9                 ADC_CFGR_RSLTCTL_9
-#define ADCFG_RSLTCTL_8                 ADC_CFGR_RSLTCTL_8
-
-
-#define ADCFG_TSEN                      ADC_CFGR_TEN
-#define ADCFG_VSEN                      ADC_CFGR_VEN
-
-#define ADCFG_ADCPRE                    ADC_CFGR_PRE
-#define ADCFG_ADCPRE_2                  ADC_CFGR_PRE_2
-#define ADCFG_ADCPRE_4                  ADC_CFGR_PRE_4
-#define ADCFG_ADCPRE_6                  ADC_CFGR_PRE_6
-#define ADCFG_ADCPRE_8                  ADC_CFGR_PRE_8
-#define ADCFG_ADCPRE_10                 ADC_CFGR_PRE_10
-#define ADCFG_ADCPRE_12                 ADC_CFGR_PRE_12
-#define ADCFG_ADCPRE_14                 ADC_CFGR_PRE_14
-#define ADCFG_ADCPRE_16                 ADC_CFGR_PRE_16
-#define ADCFG_SAMCTL                    ADC_CFGR_SAMCTL
-#define ADCFG_SAMCTL_1_5                ADC_CFGR_SAMCTL_1_5
-#define ADCFG_SAMCTL_7_5                ADC_CFGR_SAMCTL_7_5
-#define ADCFG_SAMCTL_13_5               ADC_CFGR_SAMCTL_13_5
-#define ADCFG_SAMCTL_28_5               ADC_CFGR_SAMCTL_28_5
-#define ADCFG_SAMCTL_41_5               ADC_CFGR_SAMCTL_41_5
-#define ADCFG_SAMCTL_55_5               ADC_CFGR_SAMCTL_55_5
-#define ADCFG_SAMCTL_71_5               ADC_CFGR_SAMCTL_71_5
-#define ADCFG_SAMCTL_239_5              ADC_CFGR_SAMCTL_239_5
-
-
-#define ADCFG_ADCPRE_3                  ADC_CFGR_PRE_3
-#define ADCFG_ADCPRE_5                  ADC_CFGR_PRE_5
-#define ADCFG_ADCPRE_7                  ADC_CFGR_PRE_7
-#define ADCFG_ADCPRE_9                  ADC_CFGR_PRE_9
-#define ADCFG_ADCPRE_11                 ADC_CFGR_PRE_11
-#define ADCFG_ADCPRE_13                 ADC_CFGR_PRE_13
-#define ADCFG_ADCPRE_15                 ADC_CFGR_PRE_15
-#define ADCFG_ADCPRE_17                 ADC_CFGR_PRE_17
-#define ADCFG_SAMCTL_2_5                ADC_CFGR_SAMCTL_2_5
-#define ADCFG_SAMCTL_3_5                ADC_CFGR_SAMCTL_3_5
-#define ADCFG_SAMCTL_4_5                ADC_CFGR_SAMCTL_4_5
-#define ADCFG_SAMCTL_5_5                ADC_CFGR_SAMCTL_5_5
-#define ADCFG_SAMCTL_6_5                ADC_CFGR_SAMCTL_6_5
-
-#define ADCR_ADIE                       ADC_CR_ADIE
-#define ADCR_ADWIE                      ADC_CR_ADWIE
-#define ADCR_TRGEN                      ADC_CR_TRGEN
-#define ADCR_DMAEN                      ADC_CR_DMAEN
-#define ADCR_ADST                       ADC_CR_ADST
-#define ADCR_ADMD                       ADC_CR_MODE
-#define ADCR_ADMD_SINGLE                ADC_CR_IMM
-#define ADCR_ADMD_PERIOD                ADC_CR_SCAN
-#define ADCR_ADMD_CONTINUE              ADC_CR_CONTINUE
-#define ADC_Mode_Single                 ADC_CR_IMM
-#define ADC_Mode_Single_Period          ADC_CR_SCAN
-#define ADC_Mode_Continuous_Scan        ADC_CR_CONTINUE
-
-
-#define ADCR_ALIGN                      ADC_CR_ALIGN
-#define ADCR_ALIGN_LEFT                 ADC_CR_LEFT
-#define ADCR_ALIGN_RIGHT                ADC_CR_RIGHT
-#define ADCR_CMPCH_Pos                  ADC_CR_CMPCH_Pos
-#define ADCR_CMPCH                      ADC_CR_CMPCH
-#define ADCR_CMPCH_0                    ADC_CR_CMPCH_0
-#define ADCR_CMPCH_1                    ADC_CR_CMPCH_1
-#define ADCR_CMPCH_2                    ADC_CR_CMPCH_2
-#define ADCR_CMPCH_4                    ADC_CR_CMPCH_4
-#define ADCR_CMPCH_5                    ADC_CR_CMPCH_5
-#define ADCR_CMPCH_6                    ADC_CR_CMPCH_6
-#define ADCR_CMPCH_7                    ADC_CR_CMPCH_7
-#define ADCR_CMPCH_8                    ADC_CR_CMPCH_8
-#define ADCR_CMPCH_9                    ADC_CR_CMPCH_9
-#define ADCR_CMPCH_10                   ADC_CR_CMPCH_10
-#define ADCR_CMPCH_11                   ADC_CR_CMPCH_11
-#define ADCR_CMPCH_13                   ADC_CR_CMPCH_13
-#define ADCR_CMPCH_14                   ADC_CR_CMPCH_14
-#define ADCR_CMPCH_ALL                  ADC_CR_CMPCH_ALL
-
-
-#define ADCR_TRGSEL                     ADC_CR_TRGSEL
-#define ADCR_TRGSEL_T1_CC1              ADC_CR_T1_CC1
-#define ADCR_TRGSEL_T1_CC2              ADC_CR_T1_CC2
-#define ADCR_TRGSEL_T1_CC3              ADC_CR_T1_CC3
-#define ADCR_TRGSEL_T2_CC2              ADC_CR_T2_CC2
-#define ADCR_TRGSEL_T3_TRGO             ADC_CR_T3_TRIG
-#define ADCR_TRGSEL_EXTI_11             ADC_CR_EXTI_11
-
-
-
-#define ADCR_TRGSEL_T1_CC4_CC5          ADC_CR_T1_CC4_CC5
-#define ADCR_TRGSEL_T3_CC1              ADC_CR_T3_CC1
-#define ADCR_TRGSEL_T1_TRGO             ADC_CR_T1_TRIG
-#define ADCR_TRGSEL_T8_CC4              ADC_CR_T8_CC4
-#define ADCR_TRGSEL_T8_CC4_CC5          ADC_CR_T8_CC4_CC5
-#define ADCR_TRGSEL_T2_CC1              ADC_CR_T2_CC1
-#define ADCR_TRGSEL_T3_CC4              ADC_CR_T3_CC4
-#define ADCR_TRGSEL_T2_TRGO             ADC_CR_T2_TRIG
-#define ADCR_TRGSEL_T8_CC5              ADC_CR_T8_CC5
-#define ADCR_TRGSEL_EXTI_15             ADC_CR_EXTI_15
-#define ADCR_TRGSEL_TIM1_CC4            ADC_CR_TIM1_CC4
-#define ADCR_TRGSEL_TIM1_CC5            ADC_CR_TIM1_CC5
-#define ADCR_SCANDIR                    ADC_CR_SCANDIR
-#define ADCR_TRGSHIFT                   ADC_CR_TRGSHIFT
-#define ADCR_TRGSHIFT_0                 ADC_CR_TRGSHIFT_0
-#define ADCR_TRGSHIFT_4                 ADC_CR_TRGSHIFT_4
-#define ADCR_TRGSHIFT_16                ADC_CR_TRGSHIFT_16
-#define ADCR_TRGSHIFT_32                ADC_CR_TRGSHIFT_32
-#define ADCR_TRGSHIFT_64                ADC_CR_TRGSHIFT_64
-#define ADCR_TRGSHIFT_128               ADC_CR_TRGSHIFT_128
-#define ADCR_TRGSHIFT_256               ADC_CR_TRGSHIFT_256
-#define ADCR_TRGSHIFT_512               ADC_CR_TRGSHIFT_512
-#define ADCR_CALIBEN                    ADC_CR_CALIBEN
-#define ADCR_CALIBSEL                   ADC_CR_CALIBSEL
-
-#define ADCHS_CHEN0                     ADC_CHSR_CH0
-#define ADCHS_CHEN1                     ADC_CHSR_CH1
-#define ADCHS_CHEN2                     ADC_CHSR_CH2
-#define ADCHS_CHEN3                     ADC_CHSR_CH3
-#define ADCHS_CHEN4                     ADC_CHSR_CH4
-#define ADCHS_CHEN5                     ADC_CHSR_CH5
-#define ADCHS_CHEN6                     ADC_CHSR_CH6
-#define ADCHS_CHEN7                     ADC_CHSR_CH7
-#define ADCHS_ALL                       ADC_CHSR_CHALL
-
-
-#define ADCHS_CHEN8                     ADC_CHSR_CH8
-#define ADCHS_CHEN9                     ADC_CHSR_CH9
-#define ADCHS_CHENTS                    ADC_CHSR_CHT
-#define ADCHS_CHENVS                    ADC_CHSR_CHV
-#define ADCHS_CHEN8                     ADC_CHSR_CH8
-#define ADCHS_CHEN9                     ADC_CHSR_CH9
-#define ADCHS_CHEN10                    ADC_CHSR_CH10
-#define ADCHS_CHEN11                    ADC_CHSR_CH11
-#define ADCHS_CHEN12                    ADC_CHSR_CH12
-#define ADCHS_CHEN13                    ADC_CHSR_CH13
-#define ADCHS_CHEN14                    ADC_CHSR_CH14
-#define ADCHS_CHEN15                    ADC_CHSR_CH15
-#define ADCHS_CHENTS                    ADC_CHSR_CHT
-#define ADCHS_CHENVS                    ADC_CHSR_CHV
-
-
-#define ADCMPR_CMPLDATA                 ADC_CMPR_CMPLDATA
-#define ADCMPR_CMPHDATA                 ADC_CMPR_CMPHDATA
-
-#define ADSTA_ADIF                      ADC_SR_ADIF
-#define ADSTA_ADWIF                     ADC_SR_ADWIF
-#define ADSTA_BUSY                      ADC_SR_BUSY
-#define ADSTA_CHANNEL                   ADC_SR_CH
-#define ADSTA_CHANNEL_CH0               ADC_SR_CH0
-#define ADSTA_CHANNEL_CH1               ADC_SR_CH1
-#define ADSTA_CHANNEL_CH2               ADC_SR_CH2
-#define ADSTA_CHANNEL_CH3               ADC_SR_CH3
-#define ADSTA_CHANNEL_CH4               ADC_SR_CH4
-#define ADSTA_CHANNEL_CH5               ADC_SR_CH5
-#define ADSTA_CHANNEL_CH6               ADC_SR_CH6
-#define ADSTA_CHANNEL_CH7               ADC_SR_CH7
-#define ADSTA_CHANNEL_CH8               ADC_SR_CH8
-#define ADSTA_CHANNEL_CH9               ADC_SR_CH9
-#define ADSTA_CHANNEL_CH10              ADC_SR_CH10
-#define ADSTA_CHANNEL_CH11              ADC_SR_CH11
-#define ADSTA_CHANNEL_CH13              ADC_SR_CH13
-#define ADSTA_CHANNEL_CH14              ADC_SR_CH14
-#define ADSTA_CHANNEL_CH15              ADC_SR_CH15
-#define ADSTA_VALID                     ADC_SR_VALID
-#define ADSTA_OVERRUN                   ADC_SR_OVERRUN
-
-#define ADDR_OVERRUN                    ADC_CHDR_OVERRUN
-#define ADDR_VALID                      ADC_CHDR_VALID
-#define ADDR_DATA                       ADC_CHDR_DATA
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief redefine for HAL library
-////////////////////////////////////////////////////////////////////////////////
-
-
-////////////////////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-/// @brief redefine for ADC of HAL library
-////////////////////////////////////////////////////////////////////////////////
-
-
-#define ADC_ExternalTrigConv_T1_CC1     ADC1_ExternalTrigConv_T1_CC1
-#define ADC_ExternalTrigConv_T1_CC2     ADC1_ExternalTrigConv_T1_CC2
-#define ADC_ExternalTrigConv_T1_CC3     ADC1_ExternalTrigConv_T1_CC3
-#define ADC_ExternalTrigConv_T2_CC2     ADC1_ExternalTrigConv_T2_CC2
-#define ADC_ExternalTrigConv_T3_TRIG    ADC1_ExternalTrigConv_T3_TRIG
-#define ADC_ExternalTrigConv_T3_CC1     ADC1_ExternalTrigConv_T3_CC1
-#define ADC_ExternalTrigConv_EXTI_11    ADC1_ExternalTrigConv_EXTI_11
-#define ADC_ExternalTrigConv_T1_CC4_CC5  ADC1_ExternalTrigConv_T1_CC4_CC5
-#define ADC_ExternalTrigConv_T1_TRIG     ADC1_ExternalTrigConv_T1_TRIG
-#define ADC_ExternalTrigConv_T8_CC4      ADC1_ExternalTrigConv_T8_CC4
-#define ADC_ExternalTrigConv_T8_CC4_CC5  ADC1_ExternalTrigConv_T8_CC4_CC5
-#define ADC_ExternalTrigConv_T2_CC1      ADC1_ExternalTrigConv_T2_CC1
-#define ADC_ExternalTrigConv_T3_CC4      ADC1_ExternalTrigConv_T3_CC4
-#define ADC_ExternalTrigConv_T2_TRIG     ADC1_ExternalTrigConv_T2_TRIG
-#define ADC_ExternalTrigConv_T8_CC5      ADC1_ExternalTrigConv_T8_CC5
-#define ADC_ExternalTrigConv_EXTI_15     ADC1_ExternalTrigConv_EXTI_15
-#define ADC_ExternalTrigConv_T1_CC4      ADC1_ExternalTrigConv_T1_CC4
-#define ADC_ExternalTrigConv_T1_CC5      ADC1_ExternalTrigConv_T1_CC5
-
-
-
-#define ADC_SampleTime_1_5Cycles         ADC_Samctl_1_5
-#define ADC_SampleTime_7_5Cycles         ADC_Samctl_7_5
-#define ADC_SampleTime_13_5Cycles        ADC_Samctl_13_5
-#define ADC_SampleTime_28_5Cycles        ADC_Samctl_28_5
-#define ADC_SampleTime_41_5Cycles        ADC_Samctl_41_5
-#define ADC_SampleTime_55_5Cycles        ADC_Samctl_55_5
-#define ADC_SampleTime_71_5Cycles        ADC_Samctl_71_5
-#define ADC_SampleTime_239_5Cycles       ADC_Samctl_239_5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Version compatibility definition
-////////////////////////////////////////////////////////////////////////////////
-#define AES_KEYR0                       AES_KEYRn                               ///< AES Key Register 0
-#define AES_KEYR1                       AES_KEYRn                               ///< AES Key Register 1
-#define AES_KEYR2                       AES_KEYRn                               ///< AES Key Register 2
-#define AES_KEYR3                       AES_KEYRn                               ///< AES Key Register 3
-#define AES_KEYR4                       AES_KEYRn                               ///< AES Key Register 4
-#define AES_KEYR5                       AES_KEYRn                               ///< AES Key Register 5
-#define AES_KEYR6                       AES_KEYRn                               ///< AES Key Register 6
-#define AES_KEYR7                       AES_KEYRn                               ///< AES Key Register 7
-
-#define AES_IVR0                        AES_IVRn                                ///< AES Initialization Vector Register 0
-#define AES_IVR1                        AES_IVRn                                ///< AES Initialization Vector Register 1
-#define AES_IVR2                        AES_IVRn                                ///< AES Initialization Vector Register 2
-#define AES_IVR3                        AES_IVRn                                ///< AES Initialization Vector Register 3
-
-
-#define CRC_DR_DR                       CRC_DR_DATA
-#define CRC_IDR_IDR                     CRC_IDR_DATA
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Version compatibility definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRS_CR_SYNCOKIE                 CRS_CR_OKIE
-#define CRS_CR_SYNCWARNIE               CRS_CR_WARNIE
-#define CRS_CR_ESYNCIE                  CRS_CR_EXPTIE
-#define CRS_CR_CEN                      CRS_CR_CNTEN
-#define CRS_CFGR_SYNCDIV                CRS_CFGR_DIV
-#define CRS_CFGR_SYNCSRC                CRS_CFGR_SRC
-#define CRS_CFGR_SYNCPOL                CRS_CFGR_POL
-#define CRS_ISR_SYNCOKF                 CRS_ISR_OKIF
-#define CRS_ISR_SYNCWARNF               CRS_ISR_WARNIF
-#define CRS_ISR_ERRF                    CRS_ISR_ERRIF
-#define CRS_ISR_ESYNCF                  CRS_ISR_EXPTIF
-#define CRS_ISR_SYNCERR                 CRS_ISR_ERR
-#define CRS_ISR_SYNCMISS                CRS_ISR_MISS
-#define CRS_ISR_TRIMOVF                 CRS_ISR_OVERFLOW
-#define CRS_ICR_SYNCOKC                 CRS_ICR_OK
-#define CRS_ICR_SYNCWARNC               CRS_ICR_WARN
-#define CRS_ICR_ERRC                    CRS_ICR_ERR
-#define CRS_ICR_ESYNCC                  CRS_ICR_EXPT
-
-#define CRS_IT_SYNCOK                   CRS_ISR_SYNCOKF                         ///< SYNC event OK
-#define CRS_IT_SYNCWARN                 CRS_ISR_SYNCWARNF                       ///< SYNC warning
-#define CRS_IT_ERR                      CRS_CR_ERRIE                            ///< error
-#define CRS_IT_ESYNC                    CRS_ISR_ESYNCF                          ///< Expected SYNC
-#define CRS_IT_TRIMOVF                  CRS_ISR_TRIMOVF                         ///< Trimming overflow or underflow
-#define CRS_IT_SYNCERR                  CRS_ISR_SYNCERR                         ///< SYNC error
-#define CRS_IT_SYNCMISS                 CRS_ISR_SYNCMISS                        ///< SYNC missed
-
-#define CRS_FLAG_SYNCOK                 CRS_ISR_SYNCOKF                         ///< SYNC event OK
-#define CRS_FLAG_SYNCWARN               CRS_ISR_SYNCWARNF                       ///< SYNC warning
-#define CRS_FLAG_ERR                    CRS_ISR_ERRF                            ///< error
-#define CRS_FLAG_ESYNC                  CRS_ISR_ESYNCF                          ///< Expected SYNC
-#define CRS_FLAG_TRIMOVF                CRS_ISR_TRIMOVF                         ///< Trimming overflow or underflow
-#define CRS_FLAG_SYNCERR                CRS_ISR_SYNCERR                         ///< SYNC error
-#define CRS_FLAG_SYNCMISS               CRS_ISR_SYNCMISS                        ///< SYNC missed
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Version compatibility definition
-////////////////////////////////////////////////////////////////////////////////
-#define  DIV_UNSIGN                     DIV_CR_USIGN                            ///< Unsigned enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-
-
-#define DMA_CCR_MEM2MEM                 DMA_CCR_M2M
-
-#define DMA_CCR1_EN                     DMA_CCR_EN
-#define DMA_CCR1_DIR                    DMA_CCR_DIR
-#define DMA_CCR1_CIRC                   DMA_CCR_CIRC
-#define DMA_CCR1_PINC                   DMA_CCR_PINC
-#define DMA_CCR1_MINC                   DMA_CCR_MINC
-#define DMA_CCR1_PSIZE_0                DMA_CCR_PSIZE_0
-#define DMA_CCR1_MSIZE_0                DMA_CCR_MSIZE_0
-#define DMA_CCR1_PL_0                   DMA_CCR_PL_0
-#define DMA_CCR1_PSIZE_1                DMA_CCR_PSIZE_1
-#define DMA_CCR1_MSIZE_1                DMA_CCR_MSIZE_1
-#define DMA_CCR1_PL_1                   DMA_CCR_PL_1
-#define DMA_CCR1_MEM2MEM                DMA_CCR_M2M
-#define DMA_CCR1_TCIE                   DMA_CCR_TCIE
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_IMR_MR0                    EXTI_IMR_0
-#define EXTI_IMR_MR1                    EXTI_IMR_1
-#define EXTI_IMR_MR2                    EXTI_IMR_2
-#define EXTI_IMR_MR3                    EXTI_IMR_3
-#define EXTI_IMR_MR4                    EXTI_IMR_4
-#define EXTI_IMR_MR5                    EXTI_IMR_5
-#define EXTI_IMR_MR6                    EXTI_IMR_6
-#define EXTI_IMR_MR7                    EXTI_IMR_7
-#define EXTI_IMR_MR8                    EXTI_IMR_8
-#define EXTI_IMR_MR9                    EXTI_IMR_9
-#define EXTI_IMR_MR10                   EXTI_IMR_10
-#define EXTI_IMR_MR11                   EXTI_IMR_11
-#define EXTI_IMR_MR12                   EXTI_IMR_12
-#define EXTI_IMR_MR13                   EXTI_IMR_13
-#define EXTI_IMR_MR14                   EXTI_IMR_14
-#define EXTI_IMR_MR15                   EXTI_IMR_15
-#define EXTI_IMR_MR16                   EXTI_IMR_16
-
-#define EXTI_EMR_MR0                    EXTI_EMR_0
-#define EXTI_EMR_MR1                    EXTI_EMR_1
-#define EXTI_EMR_MR2                    EXTI_EMR_2
-#define EXTI_EMR_MR3                    EXTI_EMR_3
-#define EXTI_EMR_MR4                    EXTI_EMR_4
-#define EXTI_EMR_MR5                    EXTI_EMR_5
-#define EXTI_EMR_MR6                    EXTI_EMR_6
-#define EXTI_EMR_MR7                    EXTI_EMR_7
-#define EXTI_EMR_MR8                    EXTI_EMR_8
-#define EXTI_EMR_MR9                    EXTI_EMR_9
-#define EXTI_EMR_MR10                   EXTI_EMR_10
-#define EXTI_EMR_MR11                   EXTI_EMR_11
-#define EXTI_EMR_MR12                   EXTI_EMR_12
-#define EXTI_EMR_MR13                   EXTI_EMR_13
-#define EXTI_EMR_MR14                   EXTI_EMR_14
-#define EXTI_EMR_MR15                   EXTI_EMR_15
-#define EXTI_EMR_MR16                   EXTI_EMR_16
-
-#define EXTI_RTSR_TR0                   EXTI_RTSR_0
-#define EXTI_RTSR_TR1                   EXTI_RTSR_1
-#define EXTI_RTSR_TR2                   EXTI_RTSR_2
-#define EXTI_RTSR_TR3                   EXTI_RTSR_3
-#define EXTI_RTSR_TR4                   EXTI_RTSR_4
-#define EXTI_RTSR_TR5                   EXTI_RTSR_5
-#define EXTI_RTSR_TR6                   EXTI_RTSR_6
-#define EXTI_RTSR_TR7                   EXTI_RTSR_7
-#define EXTI_RTSR_TR8                   EXTI_RTSR_8
-#define EXTI_RTSR_TR9                   EXTI_RTSR_9
-#define EXTI_RTSR_TR10                  EXTI_RTSR_10
-#define EXTI_RTSR_TR11                  EXTI_RTSR_11
-#define EXTI_RTSR_TR12                  EXTI_RTSR_12
-#define EXTI_RTSR_TR13                  EXTI_RTSR_13
-#define EXTI_RTSR_TR14                  EXTI_RTSR_14
-#define EXTI_RTSR_TR15                  EXTI_RTSR_15
-#define EXTI_RTSR_TR16                  EXTI_RTSR_16
-
-#define EXTI_FTSR_TR0                   EXTI_FTSR_0
-#define EXTI_FTSR_TR1                   EXTI_FTSR_1
-#define EXTI_FTSR_TR2                   EXTI_FTSR_2
-#define EXTI_FTSR_TR3                   EXTI_FTSR_3
-#define EXTI_FTSR_TR4                   EXTI_FTSR_4
-#define EXTI_FTSR_TR5                   EXTI_FTSR_5
-#define EXTI_FTSR_TR6                   EXTI_FTSR_6
-#define EXTI_FTSR_TR7                   EXTI_FTSR_7
-#define EXTI_FTSR_TR8                   EXTI_FTSR_8
-#define EXTI_FTSR_TR9                   EXTI_FTSR_9
-#define EXTI_FTSR_TR10                  EXTI_FTSR_10
-#define EXTI_FTSR_TR11                  EXTI_FTSR_11
-#define EXTI_FTSR_TR12                  EXTI_FTSR_12
-#define EXTI_FTSR_TR13                  EXTI_FTSR_13
-#define EXTI_FTSR_TR14                  EXTI_FTSR_14
-#define EXTI_FTSR_TR15                  EXTI_FTSR_15
-#define EXTI_FTSR_TR16                  EXTI_FTSR_16
-
-#define EXTI_SWIER_SWIER0               EXTI_SWIER_0
-#define EXTI_SWIER_SWIER1               EXTI_SWIER_1
-#define EXTI_SWIER_SWIER2               EXTI_SWIER_2
-#define EXTI_SWIER_SWIER3               EXTI_SWIER_3
-#define EXTI_SWIER_SWIER4               EXTI_SWIER_4
-#define EXTI_SWIER_SWIER5               EXTI_SWIER_5
-#define EXTI_SWIER_SWIER6               EXTI_SWIER_6
-#define EXTI_SWIER_SWIER7               EXTI_SWIER_7
-#define EXTI_SWIER_SWIER8               EXTI_SWIER_8
-#define EXTI_SWIER_SWIER9               EXTI_SWIER_9
-#define EXTI_SWIER_SWIER10              EXTI_SWIER_10
-#define EXTI_SWIER_SWIER11              EXTI_SWIER_11
-#define EXTI_SWIER_SWIER12              EXTI_SWIER_12
-#define EXTI_SWIER_SWIER13              EXTI_SWIER_13
-#define EXTI_SWIER_SWIER14              EXTI_SWIER_14
-#define EXTI_SWIER_SWIER15              EXTI_SWIER_15
-#define EXTI_SWIER_SWIER16              EXTI_SWIER_16
-
-#define EXTI_PR_PR0                     EXTI_PR_0
-#define EXTI_PR_PR1                     EXTI_PR_1
-#define EXTI_PR_PR2                     EXTI_PR_2
-#define EXTI_PR_PR3                     EXTI_PR_3
-#define EXTI_PR_PR4                     EXTI_PR_4
-#define EXTI_PR_PR5                     EXTI_PR_5
-#define EXTI_PR_PR6                     EXTI_PR_6
-#define EXTI_PR_PR7                     EXTI_PR_7
-#define EXTI_PR_PR8                     EXTI_PR_8
-#define EXTI_PR_PR9                     EXTI_PR_9
-#define EXTI_PR_PR10                    EXTI_PR_10
-#define EXTI_PR_PR11                    EXTI_PR_11
-#define EXTI_PR_PR12                    EXTI_PR_12
-#define EXTI_PR_PR13                    EXTI_PR_13
-#define EXTI_PR_PR14                    EXTI_PR_14
-#define EXTI_PR_PR15                    EXTI_PR_15
-#define EXTI_PR_PR16                    EXTI_PR_16
-
-#define EXTI_IMR_MR17                   EXTI_IMR_17
-
-#define EXTI_IMR_MR18                   EXTI_IMR_18
-
-#define EXTI_IMR_MR19                   EXTI_IMR_19
-
-#define EXTI_IMR_MR20                   EXTI_IMR_20
-
-#define EXTI_IMR_MR21                   EXTI_IMR_21
-
-
-#define EXTI_IMR_MR24                   EXTI_IMR_24
-
-#define EXTI_EMR_MR17                   EXTI_EMR_17
-
-#define EXTI_EMR_MR18                   EXTI_EMR_18
-
-#define EXTI_EMR_MR19                   EXTI_EMR_19
-
-#define EXTI_EMR_MR20                   EXTI_EMR_20
-
-#define EXTI_EMR_MR21                   EXTI_EMR_21
-
-
-#define EXTI_EMR_MR24                   EXTI_EMR_24
-
-#define EXTI_RTSR_MR17                  EXTI_RTSR_17
-
-#define EXTI_RTSR_MR18                  EXTI_RTSR_18
-
-#define EXTI_RTSR_MR19                  EXTI_RTSR_19
-
-#define EXTI_RTSR_MR20                  EXTI_RTSR_20
-
-#define EXTI_RTSR_MR21                  EXTI_RTSR_21
-
-
-#define EXTI_RTSR_MR24                  EXTI_RTSR_24
-
-#define EXTI_FTSR_MR17                  EXTI_FTSR_18
-
-#define EXTI_FTSR_MR18                  EXTI_FTSR_18
-
-#define EXTI_FTSR_MR19                  EXTI_FTSR_19
-
-#define EXTI_FTSR_MR20                  EXTI_FTSR_20
-
-#define EXTI_FTSR_MR21                  EXTI_FTSR_21
-
-
-#define EXTI_FTSR_MR24                  EXTI_FTSR_24
-
-#define EXTI_SWIER_MR17                 EXTI_SWIER_17
-
-#define EXTI_SWIER_MR18                 EXTI_SWIER_18
-
-#define EXTI_SWIER_MR19                 EXTI_SWIER_19
-
-#define EXTI_SWIER_MR20                 EXTI_SWIER_20
-
-#define EXTI_SWIER_MR21                 EXTI_SWIER_21
-
-
-#define EXTI_SWIER_MR24                 EXTI_SWIER_24
-
-#define EXTI_PR_MR17                    EXTI_PR_17
-
-#define EXTI_PR_MR18                    EXTI_PR_18
-
-#define EXTI_PR_MR19                    EXTI_PR_19
-
-#define EXTI_PR_MR20                    EXTI_PR_20
-
-#define EXTI_PR_MR21                    EXTI_PR_21
-
-
-#define EXTI_PR_MR24                    EXTI_PR_24
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Version compatibility definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define GPIO_Mode_IN_FLOATING           GPIO_Mode_FLOATING
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Version compatibility definition
-////////////////////////////////////////////////////////////////////////////////
-//Bit
-#define I2C_CON_MASTER_MODE             I2C_CR_MASTER
-#define I2C_CON_SPEED                   I2C_CR_SPEED
-#define I2C_CON_SPEED_STANDARD          I2C_CR_STD
-#define I2C_CON_SPEED_FAST              I2C_CR_FAST
-#define I2C_CON_10BITADDR_SLAVE         I2C_CR_SLAVE10
-#define I2C_CON_10BITADDR_MASTER        I2C_CR_MASTER10
-#define I2C_CON_RESTART_EN              I2C_CR_REPEN
-#define I2C_CON_SLAVE_DISABLE           I2C_CR_SLAVEDIS
-#define I2C_CON_STOP_DET_IFADDRESSED    I2C_CR_STOPINT
-#define I2C_CON_EMPTY_CTRL              I2C_CR_EMPINT
-#define I2C_CON_STOP                    I2C_CR_STOP
-#define I2C_CON_RESTART                 I2C_CR_RESTART
-
-#define I2C_TAR_TAR                     I2C_TAR_ADDR
-#define I2C_TAR_GC_OR_START             I2C_TAR_GC
-#define I2C_SAR_SAR                     I2C_SAR_ADDR
-#define I2C_DATA_CMD_DAT                I2C_DR_DAT
-#define I2C_DATA_CMD_CMD                I2C_DR_CMD
-#define I2C_DATA_CMD_STOP               I2C_DR_STOP
-#define I2C_DATA_CMD_RESTART            I2C_DR_RESTART
-
-#define I2C_SS_SCL_HCNT                 I2C_SSHR_CNT
-#define I2C_SS_SCL_LCNT                 I2C_SSLR_CNT
-#define I2C_FS_SCL_HCNT                 I2C_FSHR_CNT
-#define I2C_FS_SCL_LCNT                 I2C_FSLR_CNT
-
-#define I2C_INTR_STAT_RX_UNDER          I2C_ISR_RX_UNDER
-#define I2C_INTR_STAT_RX_OVER           I2C_ISR_RX_OVER
-#define I2C_INTR_STAT_RX_FULL           I2C_ISR_RX_FULL
-#define I2C_INTR_STAT_TX_OVER           I2C_ISR_TX_OVER
-#define I2C_INTR_STAT_TX_EMPTY          I2C_ISR_TX_EMPTY
-#define I2C_INTR_STAT_RX_REQ            I2C_ISR_RX_REQ
-#define I2C_INTR_STAT_TX_ABRT           I2C_ISR_TX_ABRT
-#define I2C_INTR_STAT_RX_DONE           I2C_ISR_RX_DONE
-#define I2C_INTR_STAT_ACTIVITY          I2C_ISR_ACTIV
-#define I2C_INTR_STAT_STOP_DET          I2C_ISR_STOP
-#define I2C_INTR_STAT_START_DET         I2C_ISR_START
-#define I2C_INTR_STAT_GEN_CALL          I2C_ISR_GC
-#define I2C_INTR_STAT_RESTART_DET       I2C_ISR_RESTART
-#define I2C_INTR_STAT_MST_ON_HOLD       I2C_ISR_HOLD
-
-#define I2C_INTR_MASK_RX_UNDER          I2C_IMR_RX_UNDER
-#define I2C_INTR_MASK_RX_OVER           I2C_IMR_RX_OVER
-#define I2C_INTR_MASK_RX_FULL           I2C_IMR_RX_FULL
-#define I2C_INTR_MASK_TX_OVER           I2C_IMR_TX_OVER
-#define I2C_INTR_MASK_TX_EMPTY          I2C_IMR_TX_EMPTY
-#define I2C_INTR_MASK_RX_REQ            I2C_IMR_RX_REQ
-#define I2C_INTR_MASK_TX_ABRT           I2C_IMR_TX_ABRT
-#define I2C_INTR_MASK_RX_DONE           I2C_IMR_RX_DONE
-#define I2C_INTR_MASK_ACTIVITY          I2C_IMR_ACTIV
-#define I2C_INTR_MASK_STOP_DET          I2C_IMR_STOP
-#define I2C_INTR_MASK_START_DET         I2C_IMR_START
-#define I2C_INTR_MASK_GEN_CALL          I2C_IMR_GC
-#define I2C_INTR_MASK_RESTART_DET       I2C_IMR_RESTART
-#define I2C_INTR_MASK_MST_ON_HOLD       I2C_IMR_HOLD
-
-#define I2C_RAW_INTR_MASK_RX_UNDER      I2C_RAWISR_RX_UNDER
-#define I2C_RAW_INTR_MASK_RX_OVER       I2C_RAWISR_RX_OVER
-#define I2C_RAW_INTR_MASK_RX_FULL       I2C_RAWISR_RX_FULL
-#define I2C_RAW_INTR_MASK_TX_OVER       I2C_RAWISR_TX_OVER
-#define I2C_RAW_INTR_MASK_TX_EMPTY      I2C_RAWISR_TX_EMPTY
-#define I2C_RAW_INTR_MASK_RX_REQ        I2C_RAWISR_RX_REQ
-#define I2C_RAW_INTR_MASK_TX_ABRT       I2C_RAWISR_TX_ABRT
-#define I2C_RAW_INTR_MASK_RX_DONE       I2C_RAWISR_RX_DONE
-#define I2C_RAW_INTR_MASK_ACTIVITY      I2C_RAWISR_ACTIV
-#define I2C_RAW_INTR_MASK_STOP_DET      I2C_RAWISR_STOP
-#define I2C_RAW_INTR_MASK_START_DET     I2C_RAWISR_START
-#define I2C_RAW_INTR_MASK_GEN_CALL      I2C_RAWISR_GC
-#define I2C_RAW_INTR_MASK_RESTART_DET   I2C_RAWISR_RESTART
-#define I2C_RAW_INTR_MASK_MST_ON_HOLD   I2C_RAWISR_HOLD
-
-#define I2C_RX_TL                       I2C_RXTLR_TL
-#define I2C_TX_TL                       I2C_TXTLR_TL
-
-#define I2C_CLR_INTR                    I2C_ICR
-#define I2C_CLR_RX_UNDER                I2C_RX_UNDER
-#define I2C_CLR_RX_OVER                 I2C_RX_OVER
-#define I2C_CLR_TX_OVER                 I2C_TX_OVER
-#define I2C_RX_REQ                      I2C_RD_REQ
-#define I2C_CLR_RX_REQ                  I2C_RD_REQ
-#define I2C_CLR_TX_ABRT                 I2C_TX_ABRT
-#define I2C_CLR_RX_DONE                 I2C_RX_DONE
-#define I2C_CLR_ACTIVITY                I2C_ACTIV
-#define I2C_CLR_STOP_DET                I2C_STOP
-#define I2C_CLR_START_DET               I2C_START
-#define I2C_CLR_GEN_CALL                I2C_GC
-
-#define I2C_ENABLE_ENABLE               I2C_ENR_ENABLE
-#define I2C_ENABLE_ABORT                I2C_ENR_ABORT
-
-#define I2C_STATUS_ACTIVITY             I2C_SR_ACTIV
-#define I2C_STATUS_TFNF                 I2C_SR_TFNF
-#define I2C_STATUS_TFE                  I2C_SR_TFE
-#define I2C_STATUS_RFNE                 I2C_SR_RFNE
-#define I2C_STATUS_RFF                  I2C_SR_RFF
-#define I2C_STATUS_MST_ACTIVITY         I2C_SR_MST_ACTIV
-#define I2C_STATUS_SLV_ACTIVITY         I2C_SR_SLV_ACTIV
-
-#define I2C_TXFLR                       I2C_TXFLR_CNT
-#define I2C_RXFLR                       I2C_RXFLR_CNT
-
-#define I2C_SDA_TX_HOLD                 I2C_HOLD_TXCNT
-#define I2C_SDA_RX_HOLD                 I2C_HOLD_RXCNT
-#define I2C_DMA_CR_RDMAE                I2C_DMA_RXEN
-#define I2C_DMA_CR_TDMAE                I2C_DMA_TXEN
-#define I2C_SDA_SET_UP                  I2C_SETUP_CNT
-#define I2C_ACK_GENERAL_CALL            I2C_GCR_GC
-
-
-#define IWDG_PR_PR                      IWDG_PR_PRE
-#define IWDG_PR_PR_DIV4                 IWDG_PR_PRE_DIV4
-#define IWDG_PR_PR_DIV8                 IWDG_PR_PRE_DIV8
-#define IWDG_PR_PR_DIV16                IWDG_PR_PRE_DIV16
-#define IWDG_PR_PR_DIV32                IWDG_PR_PRE_DIV32
-#define IWDG_PR_PR_DIV64                IWDG_PR_PRE_DIV64
-#define IWDG_PR_PR_DIV128               IWDG_PR_PRE_DIV128
-#define IWDG_PR_PR_DIV256               IWDG_PR_PRE_DIV256
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Version compatibility definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_AHBENR_DMAEN                RCC_AHBENR_DMA1
-#define RCC_AHBENR_DMA1EN               RCC_AHBENR_DMA1
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup AHB_peripheral
-/// @{
-#define RCC_AHBPeriph_DMA1              RCC_AHBENR_DMA1
-#define RCC_AHBPeriph_SRAM              RCC_AHBENR_SRAM
-#define RCC_AHBPeriph_FLITF             RCC_AHBENR_FLITF
-#define RCC_AHBPeriph_CRC               RCC_AHBENR_CRC
-#define RCC_AHBPeriph_AES               RCC_AHBENR_AES
-#define RCC_AHBPeriph_GPIOA             RCC_AHBENR_GPIOA
-#define RCC_AHBPeriph_GPIOB             RCC_AHBENR_GPIOB
-#define RCC_AHBPeriph_GPIOC             RCC_AHBENR_GPIOC
-#define RCC_AHBPeriph_GPIOD             RCC_AHBENR_GPIOD
-
-
-#define RCC_AHBPeriph_GPIOE             RCC_AHBENR_GPIOE
-#define RCC_AHBPeriph_HIV               RCC_AHBENR_HWDIV
-#define RCC_AHBPeriph_HWDIV             RCC_AHBENR_HWDIV
-
-
-
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup APB2_peripheral
-/// @{
-#define RCC_APB2Periph_ADC1             RCC_APB2ENR_ADC1
-#define RCC_APB2Periph_TIM1             RCC_APB2ENR_TIM1
-#define RCC_APB2Periph_SPI1             RCC_APB2ENR_SPI1
-#define RCC_APB2Periph_UART1            RCC_APB2ENR_UART1
-#define RCC_APB2Periph_COMP             RCC_APB2ENR_COMP
-#define RCC_APB2Periph_DBGMCU           RCC_APB2ENR_DBGMCU
-
-#define RCC_APB2ENR_ADC1EN              RCC_APB2ENR_ADC1
-#define RCC_APB2ENR_TIM1EN              RCC_APB2ENR_TIM1
-#define RCC_APB2RSTR_ADC1RST            RCC_APB2RSTR_ADC1
-
-#define RCC_APB2Periph_ADC2             RCC_APB2ENR_ADC2
-#define RCC_APB2Periph_ADC3             RCC_APB2ENR_ADC3
-#define RCC_APB2Periph_SYSCFG           RCC_APB2ENR_SYSCFG
-#define RCC_APB2Periph_EXTI             RCC_APB2ENR_EXTI
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-/// @defgroup APB1_peripheral
-/// @{
-#define RCC_APB1Periph_TIM2             RCC_APB1ENR_TIM2
-#define RCC_APB1Periph_TIM3             RCC_APB1ENR_TIM3
-#define RCC_APB1Periph_TIM4             RCC_APB1ENR_TIM4
-#define RCC_APB1Periph_UART3            RCC_APB1ENR_UART3
-#define RCC_APB1Periph_BKP              RCC_APB1ENR_BKP
-#define RCC_APB1Periph_DAC              RCC_APB1ENR_DAC
-#define RCC_APB1Periph_I2C2             RCC_APB1ENR_I2C2
-#define RCC_APB1Periph_ALL              0x3AE64807
-#define RCC_APB1Periph_CAN1             RCC_APB1ENR_CAN
-#define RCC_APB1Periph_CRS              RCC_APB1ENR_CRS
-#define RCC_APB1Periph_UART2            RCC_APB1ENR_UART2
-#define RCC_APB1Periph_I2C1             RCC_APB1ENR_I2C1
-#define RCC_APB1Periph_SPI2             RCC_APB1ENR_SPI2
-#define RCC_APB1Periph_WWDG             RCC_APB1ENR_WWDG
-#define RCC_APB1Periph_PWR              RCC_APB1ENR_PWR
-
-#define RCC_APB1ENR_PWREN               RCC_APB1ENR_PWR
-#define RCC_APB1ENR_TIM2EN              RCC_APB1ENR_TIM2
-#define RCC_APB1ENR_TIM3EN              RCC_APB1ENR_TIM3
-#define RCC_APB1ENR_SYSCFG              RCC_APB1ENR_EXTI
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_CRH_SECIE_Pos               RTC_CR_SECIE_Pos
-#define RTC_CRH_SECIE                   RTC_CR_SECIE                  ///< Second Interrupt Enable
-#define RTC_CRH_ALRIE_Pos               RTC_CR_ALRIE_Pos
-#define RTC_CRH_ALRIE                   RTC_CR_ALRIE                  ///< Alarm Interrupt Enable
-#define RTC_CRH_OWIE_Pos                RTC_CR_OWIE_Pos
-#define RTC_CRH_OWIE                    RTC_CR_OWIE                   ///< OverfloW Interrupt Enable
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_CSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_CRL_SECF_Pos                RTC_CSR_SECF_Pos
-#define RTC_CRL_SECF                    RTC_CSR_SECF                   ///< Second Flag
-#define RTC_CRL_ALRF_Pos                RTC_CSR_ALRF_Pos
-#define RTC_CRL_ALRF                    RTC_CSR_ALRF                   ///< Alarm Flag
-#define RTC_CRL_OWF_Pos                 RTC_CSR_OWF_Pos
-#define RTC_CRL_OWF                     RTC_CSR_OWF                    ///< OverfloW Flag
-#define RTC_CRL_RSF_Pos                 RTC_CSR_RSF_Pos
-#define RTC_CRL_RSF                     RTC_CSR_RSF                    ///< Registers Synchronized Flag
-#define RTC_CRL_CNF_Pos                 RTC_CSR_CNF_Pos
-#define RTC_CRL_CNF                     RTC_CSR_CNF                    ///< Configuration Flag
-#define RTC_CRL_RTOFF_Pos               RTC_CSR_RTOFF_Pos
-#define RTC_CRL_RTOFF                   RTC_CSR_RTOFF                  ///< RTC operation OFF
-#define RTC_CRL_ALPEN_Pos               RTC_CSR_ALPEN_Pos
-#define RTC_CRL_ALPEN                   RTC_CSR_ALPEN                  ///< RTC Alarm Loop Enable
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Version compatibility definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_TXREG_TXREG                 SPI_TDR_TXREG
-#define SPI_RXREG_RXREG                 SPI_RDR_RXREG
-
-#define SPI_CSTAT_TXEPT                 SPI_SR_TXEPT
-#define SPI_CSTAT_RXAVL                 SPI_SR_RXAVL
-#define SPI_CSTAT_TXFULL                SPI_SR_TXFULL
-#define SPI_CSTAT_RXAVL_4BYTE           SPI_SR_RXAVL_4BYTE
-#define SPI_CSTAT_TXFADDR               SPI_SR_TXFADDR
-#define SPI_CSTAT_RXFADDR               SPI_SR_RXFADDR
-
-#define SPI_INTSTAT_TX_INTF             SPI_ISR_TX_INTF
-#define SPI_INTSTAT_RX_INTF             SPI_ISR_RX_INTF
-#define SPI_INTSTAT_UNDERRUN_INTF       SPI_ISR_UNDERRUN_INTF
-#define SPI_INTSTAT_RXOERR_INTF         SPI_ISR_RXOERR_INTF
-#define SPI_INTSTAT_RXMATCH_INTF        SPI_ISR_RXMATCH_INTF
-#define SPI_INTSTAT_RXFULL_INTF         SPI_ISR_RXFULL_INTF
-#define SPI_INTSTAT_TXEPT_INTF          SPI_ISR_TXEPT_INTF
-
-#define SPI_INTEN_TX_IEN                SPI_IER_TX_IEN
-#define SPI_INTEN_RX_IEN                SPI_IER_RX_IEN
-#define SPI_INTEN_UNDERRUN_IEN          SPI_IER_UNDERRUN_IEN
-#define SPI_INTEN_RXOERR_IEN            SPI_IER_RXOERR_IEN
-#define SPI_INTEN_RXMATCH_IEN           SPI_IER_RXMATCH_IEN
-#define SPI_INTEN_RXFULL_IEN            SPI_IER_RXFULL_IEN
-#define SPI_INTEN_TXEPT_IEN             SPI_IER_TXEPT_IEN
-
-#define SPI_INTCLR_TX_ICLR              SPI_ICR_TX_ICLR
-#define SPI_INTCLR_RX_ICLR              SPI_ICR_RX_ICLR
-#define SPI_INTCLR_UNDERRUN_ICLR        SPI_ICR_UNDERRUN_ICLR
-#define SPI_INTCLR_RXOERR_ICLR          SPI_ICR_RXOERR_ICLR
-#define SPI_INTCLR_RXMATCH_ICLR         SPI_ICR_RXMATCH_ICLR
-#define SPI_INTCLR_RXFULL_ICLR          SPI_ICR_RXFULL_ICLR
-#define SPI_INTCLR_TXEPT_ICLR           SPI_ICR_TXEPT_ICLR
-
-#define SPI_GCTL_SPIEN                  SPI_GCR_SPIEN
-#define SPI_GCTL_INT_EN                 SPI_GCR_IEN
-#define SPI_GCTL_MM                     SPI_GCR_MODE
-#define SPI_GCTL_TXEN                   SPI_GCR_TXEN
-#define SPI_GCTL_RXEN                   SPI_GCR_RXEN
-
-#define SPI_GCTL_RXTLF                  SPI_GCR_RXTLF
-#define SPI_GCTL_RXTLF_One              SPI_GCR_RXTLF_One
-#define SPI_GCTL_RXTLF_Half             SPI_GCR_RXTLF_Half
-
-#define SPI_GCTL_TXTLF_Pos              SPI_GCR_TXTLF_Pos
-#define SPI_GCTL_TXTLF                  SPI_GCR_TXTLF
-#define SPI_GCTL_TXTLF_One              SPI_GCR_TXTLF_One
-#define SPI_GCTL_TXTLF_Half             SPI_GCR_TXTLF_Half
-#define SPI_GCTL_DMAEN                  SPI_GCR_DMAEN
-#define SPI_GCTL_NSS_SEL                SPI_GCR_NSS
-#define SPI_GCTL_DATA_SEL               SPI_GCR_DWSEL
-
-#define SPI_GCTL_NSSTOG                 SPI_GCR_NSSTOG
-
-#define SPI_CCTL_CPHA                   SPI_CCR_CPHA
-#define SPI_CCTL_CPOL                   SPI_CCR_CPOL
-#define SPI_CCTL_LSBFE                  SPI_CCR_LSBFE
-#define SPI_CCTL_SPILEN                 SPI_CCR_SPILEN
-#define SPI_CCTL_RXEDGE                 SPI_CCR_RXEDGE
-#define SPI_CCTL_TXEDGE                 SPI_CCR_TXEDGE
-
-#define SPI_CCTL_CPHASEL                SPI_CCR_CPHASEL
-
-#define SPI_CCTL_HISPD                  SPI_CCR_HISPD
-
-#define SPI_SPBRG_SPBRG                 SPI_BRR_DIVF
-
-#define SPI_RXDNR_RXDNR                 SPI_RDNR_RDN
-
-#define SPI_EXTCTL_EXTLEN               SPI_ECR_EXTLEN
-#define TIM_CR1_ARPE                    TIM_CR1_ARPEN
-
-#define TIM_SMCR_ECE                    TIM_SMCR_ECEN
-
-#define TIM_DIER_UIE                    TIM_DIER_UI
-#define TIM_DIER_CC1IE                  TIM_DIER_CC1I
-#define TIM_DIER_CC2IE                  TIM_DIER_CC2I
-#define TIM_DIER_CC3IE                  TIM_DIER_CC3I
-#define TIM_DIER_CC4IE                  TIM_DIER_CC4I
-#define TIM_DIER_COMIE                  TIM_DIER_COMI
-#define TIM_DIER_TIE                    TIM_DIER_TI
-#define TIM_DIER_BIE                    TIM_DIER_BI
-#define TIM_DIER_UDE                    TIM_DIER_UD
-#define TIM_DIER_CC1DE                  TIM_DIER_CC1D
-#define TIM_DIER_CC2DE                  TIM_DIER_CC2D
-#define TIM_DIER_CC3DE                  TIM_DIER_CC3D
-#define TIM_DIER_CC4DE                  TIM_DIER_CC4D
-#define TIM_DIER_COMDE                  TIM_DIER_COMD
-#define TIM_DIER_TDE                    TIM_DIER_TD
-
-#define TIM_DIER_UIEN                   TIM_DIER_UI
-#define TIM_DIER_CC1IEN                 TIM_DIER_CC1I
-#define TIM_DIER_CC2IEN                 TIM_DIER_CC2I
-#define TIM_DIER_CC3IEN                 TIM_DIER_CC3I
-#define TIM_DIER_CC4IEN                 TIM_DIER_CC4I
-#define TIM_DIER_COMIEN                 TIM_DIER_COMI
-#define TIM_DIER_TIEN                   TIM_DIER_TI
-#define TIM_DIER_BIEN                   TIM_DIER_BI
-#define TIM_DIER_UDEN                   TIM_DIER_UD
-#define TIM_DIER_CC1DEN                 TIM_DIER_CC1D
-#define TIM_DIER_CC2DEN                 TIM_DIER_CC2D
-#define TIM_DIER_CC3DEN                 TIM_DIER_CC3D
-#define TIM_DIER_CC4DEN                 TIM_DIER_CC4D
-#define TIM_DIER_COMDEN                 TIM_DIER_COMD
-#define TIM_DIER_TDEN                   TIM_DIER_TD
-
-#define TIM_DIER_CC5IE                  TIM_DIER_CC5I
-#define TIM_DIER_CC5DE                  TIM_DIER_CC5D
-
-#define TIM_SR_UIF                      TIM_SR_UI
-#define TIM_SR_CC1IF                    TIM_SR_CC1I
-#define TIM_SR_CC2IF                    TIM_SR_CC2I
-#define TIM_SR_CC3IF                    TIM_SR_CC3I
-#define TIM_SR_CC4IF                    TIM_SR_CC4I
-#define TIM_SR_COMIF                    TIM_SR_COMI
-#define TIM_SR_TIF                      TIM_SR_TI
-#define TIM_SR_BIF                      TIM_SR_BI
-#define TIM_SR_CC1OF                    TIM_SR_CC1O
-#define TIM_SR_CC2OF                    TIM_SR_CC2O
-#define TIM_SR_CC3OF                    TIM_SR_CC3O
-#define TIM_SR_CC4OF                    TIM_SR_CC4O
-
-#define TIM_SR_CC5IF                    TIM_SR_CC5I
-
-#define TIM_CCMR1_OC1FE                 TIM_CCMR1_OC1FEN
-#define TIM_CCMR1_OC1PE                 TIM_CCMR1_OC1PEN
-#define TIM_CCMR1_OC1CE                 TIM_CCMR1_OC1CEN
-#define TIM_CCMR1_OC2FE                 TIM_CCMR1_OC2FEN
-#define TIM_CCMR1_OC2PE                 TIM_CCMR1_OC2PEN
-#define TIM_CCMR1_OC2CE                 TIM_CCMR1_OC2CEN
-
-#define TIM_CCMR2_OC3FE                 TIM_CCMR2_OC3FEN
-#define TIM_CCMR2_OC3PE                 TIM_CCMR2_OC3PEN
-#define TIM_CCMR2_OC3CE                 TIM_CCMR2_OC3CEN
-#define TIM_CCMR2_OC4FE                 TIM_CCMR2_OC4FEN
-#define TIM_CCMR2_OC4PE                 TIM_CCMR2_OC4PEN
-#define TIM_CCMR2_OC4CE                 TIM_CCMR2_OC4CEN
-
-#define TIM_CCER_CC1E                   TIM_CCER_CC1EN
-#define TIM_CCER_CC1NE                  TIM_CCER_CC1NEN
-#define TIM_CCER_CC2E                   TIM_CCER_CC2EN
-#define TIM_CCER_CC2NE                  TIM_CCER_CC2NEN
-#define TIM_CCER_CC3E                   TIM_CCER_CC3EN
-#define TIM_CCER_CC3NE                  TIM_CCER_CC3NEN
-#define TIM_CCER_CC4E                   TIM_CCER_CC4EN
-
-#define TIM_CCER_CC5E                   TIM_CCER_CC5EN
-
-#define TIM_BDTR_BKE                    TIM_BDTR_BKEN
-#define TIM_BDTR_AOE                    TIM_BDTR_AOEN
-#define TIM_BDTR_MOE                    TIM_BDTR_MOEN
-
-#define TIM_BDTR_DOE                    TIM_BDTR_DOEN
-
-#define TIM_CCMR3_OC5FE                 TIM_CCMR3_OC5FEN
-#define TIM_CCMR3_OC5PE                 TIM_CCMR3_OC5PEN
-#define TIM_CCMR3_OC5CE                 TIM_CCMR3_OC5CEN
-#define UART_TDR_TXREG                  UART_TDR_DATA
-#define UART_RDR_RXREG                  UART_RDR_DATA
-
-#define UART_ISR_TX_INTF                UART_ISR_TX
-#define UART_ISR_RX_INTF                UART_ISR_RX
-#define UART_ISR_RXOERR_INTF            UART_ISR_RXOERR
-#define UART_ISR_RXPERR_INTF            UART_ISR_RXPERR
-#define UART_ISR_RXFERR_INTF            UART_ISR_RXFERR
-#define UART_ISR_RXBRK_INTF             UART_ISR_RXBRK
-
-#define UART_IER_TXIEN                  UART_IER_TX
-#define UART_IER_RXIEN                  UART_IER_RXI
-#define UART_IER_RXOERREN               UART_IER_RXOERR
-#define UART_IER_RXPERREN               UART_IER_RXPERR
-#define UART_IER_RXFERREN               UART_IER_RXFERR
-#define UART_IER_RXBRKEN                UART_IER_RXBRK
-
-#define UART_ICR_TXICLR                 UART_ICR_TX
-#define UART_ICR_RXICLR                 UART_ICR_RX
-#define UART_ICR_RXOERRCLR              UART_ICR_RXOERR
-#define UART_ICR_RXPERRCLR              UART_ICR_RXPERR
-#define UART_ICR_RXFERRCLR              UART_ICR_RXFERR
-#define UART_ICR_RXBRKCLR               UART_ICR_RXBRK
-
-#define UART_Mode_Rx                    UART_GCR_RX
-#define UART_Mode_Tx                    UART_GCR_TX
-#define UART_EN                         UART_GCR_UART
-#define UART_IT_RXBRK                   UART_IER_RXBRK
-#define UART_IT_ERR                     UART_IER_RXFERR
-#define UART_IT_PE                      UART_IER_RXPERR
-#define UART_OVER_ERR                   UART_IER_RXOERR
-#define UART_IT_RXIEN                   UART_IER_RX
-#define UART_IT_TXIEN                   UART_IER_TX
-
-#define UART_HardwareFlowControl_None   UART_HWFlowControl_None
-
-#define UART_BRR_DIV_MANTISSA           UART_BRR_MANTISSA
-#define UART_BRR_DIV_FRACTION           UART_BRR_FRACTION
-
-#define UART_ISR_TXC_INTF               UART_ISR_TXC
-#define UART_ISR_TXBRK_INTF             UART_ISR_TXBRK
-#define UART_ISR_RXB8_INTF              UART_ISR_RXB8
-
-#define UART_IT_RXB8                    UART_IER_RXB8
-#define UART_IT_TXBRK                   UART_IER_TXBRK
-#define UART_IT_TXCIEN                  UART_IER_TXC
-#define UART_ICR_TXCCLR                 UART_ICR_TXC
-#define UART_ICR_TXBRKCLR               UART_ICR_TXBRK
-#define UART_ICR_RXB8CLR                UART_ICR_RXB8
-#define UART_SCR_SCAEN                  UART_SCR_SCARB
-#define UART_DMAReq_EN                  UART_GCR_DMA
-#define UART_FLAG_TXEMPTY               UART_CSR_TXEPT
-#define UART_FLAG_TXFULL                UART_CSR_TXFULL
-#define UART_FLAG_RXAVL                 UART_CSR_RXAVL
-#define UART_FLAG_TXEPT                 UART_CSR_TXC
-#define WWDG_CR_T                       WWDG_CR_CNT
-
-
-#if defined(ENABLEIP_USB_OTG)
-//USB
-
-///-------------------  Bit definition for SETUP0 register  --------------------
-
-//#define SETUP0 ((u16)0x00FF)
-
-///-------------------  Bit definition for SETUP1 register  --------------------
-//#define SETUP1 ((u16)0x00FF)
-
-///-------------------  Bit definition for SETUP2 register  --------------------
-//#define SETUP2 ((u16)0x00FF)
-
-///-------------------  Bit definition for SETUP3 register  --------------------
-//#define SETUP3 ((u16)0x00FF)
-
-///-------------------  Bit definition for SETUP4 register  --------------------
-//#define SETUP4 ((u16)0x00FF)
-
-///-------------------  Bit definition for SETUP5 register  --------------------
-//#define SETUP5 ((u16)0x00FF)
-
-///-------------------  Bit definition for SETUP6 register  --------------------
-//#define SETUP6 ((u16)0x00FF)
-
-///-------------------  Bit definition for SETUP7 register  --------------------
-//#define SETUP7 ((u16)0x00FF)
-
-
-
-#define USB_TOP_STATE_0                             ((u16)0x0020)
-#define USB_TOP_STATE_1                             ((u16)0x0040)
-
-///-------------------  Bit definition for EP1_INT_STATE register  --------------------
-#define  EP1_INT_STATE_END                          ((u16)0x0002)
-#define  EP1_INT_STATE_INNACK                       ((u16)0x0004)
-#define  EP1_INT_STATE_INACK                        ((u16)0x0008)
-#define  EP1_INT_STATE_INSTALL                      ((u16)0x0010)
-#define  EP1_INT_STATE_OUTNACK                      ((u16)0x0020)
-#define  EP1_INT_STATE_OUTACK                       ((u16)0x0040)
-#define  EP1_INT_STATE_OUTSTALL                     ((u16)0x0080)
-
-///-------------------  Bit definition for EP2_INT_STATE register  --------------------
-#define  EP2_INT_STATE_END                          ((u16)0x0002)
-#define  EP2_INT_STATE_INNACK                       ((u16)0x0004)
-#define  EP2_INT_STATE_INACK                        ((u16)0x0008)
-#define  EP2_INT_STATE_INSTALL                      ((u16)0x0010)
-#define  EP2_INT_STATE_OUTNACK                      ((u16)0x0020)
-#define  EP2_INT_STATE_OUTACK                       ((u16)0x0040)
-#define  EP2_INT_STATE_OUTSTALL                     ((u16)0x0080)
-
-///-------------------  Bit definition for EP3_INT_STATE register  --------------------
-#define  EP3_INT_STATE_END                          ((u16)0x0002)
-#define  EP3_INT_STATE_INNACK                       ((u16)0x0004)
-#define  EP3_INT_STATE_INACK                        ((u16)0x0008)
-#define  EP3_INT_STATE_INSTALL                      ((u16)0x0010)
-#define  EP3_INT_STATE_OUTNACK                      ((u16)0x0020)
-#define  EP3_INT_STATE_OUTACK                       ((u16)0x0040)
-#define  EP3_INT_STATE_OUTSTALL                     ((u16)0x0080)
-
-///-------------------  Bit definition for EP4_INT_STATE register  --------------------
-#define  EP4_INT_STATE_END                          ((u16)0x0002)
-#define  EP4_INT_STATE_INNACK                       ((u16)0x0004)
-#define  EP4_INT_STATE_INACK                        ((u16)0x0008)
-#define  EP4_INT_STATE_INSTALL                      ((u16)0x0010)
-#define  EP4_INT_STATE_OUTNACK                      ((u16)0x0020)
-#define  EP4_INT_STATE_OUTACK                       ((u16)0x0040)
-#define  EP4_INT_STATE_OUTSTALL                     ((u16)0x0080)
-
-
-///-------------------  Bit definition for EP0_AVIL register  --------------------
-#define EP0_AVIL_EPXAVIL                            ((u16)0x00FF)
-
-///-------------------  Bit definition for EP1_AVIL register  --------------------
-#define EP1_AVIL_EPXAVIL                            ((u16)0x00FF)
-
-///-------------------  Bit definition for EP2_AVIL register  --------------------
-#define EP2_AVIL_EPXAVIL                            ((u16)0x00FF)
-
-///-------------------  Bit definition for EP3_AVIL register  --------------------
-#define EP3_AVIL_EPXAVIL                            ((u16)0x00FF)
-
-///-------------------  Bit definition for EP4_AVIL register  --------------------
-#define EP4_AVIL_EPXAVIL                            ((u16)0x00FF)
-
-///-------------------  Bit definition for EP0_CTRL register  --------------------
-#define EP0_CTRL_TRANEN                             ((u16)0x0080)
-
-#define EP0_CTRL_TRANCOUNT                          ((u16)0x007F)
-#define EP0_CTRL_TRANCOUNT_0                        ((u16)0x0001)
-#define EP0_CTRL_TRANCOUNT_1                        ((u16)0x0002)
-#define EP0_CTRL_TRANCOUNT_2                        ((u16)0x0004)
-#define EP0_CTRL_TRANCOUNT_3                        ((u16)0x0008)
-#define EP0_CTRL_TRANCOUNT_4                        ((u16)0x0010)
-#define EP0_CTRL_TRANCOUNT_5                        ((u16)0x0020)
-#define EP0_CTRL_TRANCOUNT_6                        ((u16)0x0040)
-
-///-------------------  Bit definition for EP1_CTRL register  --------------------
-#define EP1_CTRL_TRANEN                             ((u16)0x0080)
-
-#define EP1_CTRL_TRANCOUNT                         ((u16)0x007F)
-#define EP1_CTRL_TRANCOUNT_0                       ((u16)0x0001)
-#define EP1_CTRL_TRANCOUNT_1                       ((u16)0x0002)
-#define EP1_CTRL_TRANCOUNT_2                       ((u16)0x0004)
-#define EP1_CTRL_TRANCOUNT_3                       ((u16)0x0008)
-#define EP1_CTRL_TRANCOUNT_4                       ((u16)0x0010)
-#define EP1_CTRL_TRANCOUNT_5                       ((u16)0x0020)
-#define EP1_CTRL_TRANCOUNT_6                       ((u16)0x0040)
-
-///-------------------  Bit definition for EP2_CTRL register  --------------------
-#define EP2_CTRL_TRANEN                             ((u16)0x0080)
-
-#define EP2_CTRL_TRANCOUNT                          ((u16)0x007F)
-#define EP2_CTRL_TRANCOUNT_0                        ((u16)0x0001)
-#define EP2_CTRL_TRANCOUNT_1                        ((u16)0x0002)
-#define EP2_CTRL_TRANCOUNT_2                        ((u16)0x0004)
-#define EP2_CTRL_TRANCOUNT_3                        ((u16)0x0008)
-#define EP2_CTRL_TRANCOUNT_4                        ((u16)0x0010)
-#define EP2_CTRL_TRANCOUNT_5                        ((u16)0x0020)
-#define EP2_CTRL_TRANCOUNT_6                        ((u16)0x0040)
-
-///-------------------  Bit definition for EP3_CTRL register  --------------------
-#define EP3_CTRL_TRANEN                             ((u16)0x0080)
-
-#define EP3_CTRL_TRANCOUNT                          ((u16)0x007F)
-#define EP3_CTRL_TRANCOUNT_0                        ((u16)0x0001)
-#define EP3_CTRL_TRANCOUNT_1                        ((u16)0x0002)
-#define EP3_CTRL_TRANCOUNT_2                        ((u16)0x0004)
-#define EP3_CTRL_TRANCOUNT_3                        ((u16)0x0008)
-#define EP3_CTRL_TRANCOUNT_4                        ((u16)0x0010)
-#define EP3_CTRL_TRANCOUNT_5                        ((u16)0x0020)
-#define EP3_CTRL_TRANCOUNT_6                        ((u16)0x0040)
-
-///-------------------  Bit definition for EP4_CTRL register  --------------------
-#define EP4_CTRL_TRANEN                             ((u16)0x0080)
-
-#define EP4_CTRL_TRANCOUNT                          ((u16)0x007F)
-#define EP4_CTRL_TRANCOUNT_0                        ((u16)0x0001)
-#define EP4_CTRL_TRANCOUNT_1                        ((u16)0x0002)
-#define EP4_CTRL_TRANCOUNT_2                        ((u16)0x0004)
-#define EP4_CTRL_TRANCOUNT_3                        ((u16)0x0008)
-#define EP4_CTRL_TRANCOUNT_4                        ((u16)0x0010)
-#define EP4_CTRL_TRANCOUNT_5                        ((u16)0x0020)
-#define EP4_CTRL_TRANCOUNT_6                        ((u16)0x0040)
-
-
-#endif
-#endif //__MM32_REG_DEFINE_V1_H
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h
deleted file mode 100644
index 1aab3ef16..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_adc.h
+++ /dev/null
@@ -1,953 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_adc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_ADC_H
-#define __REG_ADC_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC1_BASE                       (APB2PERIPH_BASE + 0x2400)              ///< Base Address: 0x40012400
-#define ADC2_BASE                       (APB2PERIPH_BASE + 0x2800)              ///< Base Address: 0x40012800
-#define ADC3_BASE                       (APB2PERIPH_BASE + 0x4C00)              ///< Base Address: 0x40014C00
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Analog-to-Digital Converter register
-////////////////////////////////////////////////////////////////////////////////
-#define USENCOMBINEREGISTER
-#ifdef USENCOMBINEREGISTER
-
-typedef struct {
-    union {
-        __IO u32 DR;                                                            ///< ADC data register,                             offset: 0x00
-        __IO u32 ADDATA;
-    };
-    union {
-        __IO u32 CFGR;                                                          ///< ADC configuration register,                    offset: 0x04
-        __IO u32 ADCFG;
-    };
-    union {
-        __IO u32 CR;                                                            ///< ADC control register,                          offset: 0x08
-        __IO u32 ADCR;
-    };
-    union {
-        __IO u32 CHSR;                                                          ///< ADC channel selection register,                offset: 0x0C
-        __IO u32 ADCHS;
-    };
-    union {
-        __IO u32 CMPR;                                                          ///< ADC window compare register,                   offset: 0x10
-        __IO u32 ADCMPR;
-    };
-    union {
-        __IO u32 SR;                                                            ///< ADC status register,                           offset: 0x14
-        __IO u32 ADSTA;
-    };
-    union {
-        __IO u32 CH0DR;                                                         ///< ADC channel0 data register,                    offset: 0x18
-        __IO u32 ADDR0;
-    };
-    union {
-        __IO u32 CH1DR;                                                         ///< ADC channel1 data register,                    offset: 0x1C
-        __IO u32 ADDR1;
-    };
-    union {
-        __IO u32 CH2DR;                                                         ///< ADC channel2 data register,                    offset: 0x20
-        __IO u32 ADDR2;
-    };
-    union {
-        __IO u32 CH3DR;                                                         ///< ADC channel3 data register,                    offset: 0x24
-        __IO u32 ADDR3;
-    };
-    union {
-        __IO u32 CH4DR;                                                         ///< ADC channel4 data register,                    offset: 0x28
-        __IO u32 ADDR4;
-    };
-    union {
-        __IO u32 CH5DR;                                                         ///< ADC channel5 data register,                    offset: 0x2C
-        __IO u32 ADDR5;
-    };
-    union {
-        __IO u32 CH6DR;                                                         ///< ADC channel6 data register,                    offset: 0x30
-        __IO u32 ADDR6;
-    };
-    union {
-        __IO u32 CH7DR;                                                         ///< ADC channel7 data register,                    offset: 0x34
-        __IO u32 ADDR7;
-    };
-    union {
-        __IO u32 CH8DR;                                                         ///< ADC channel8 data register,                    offset: 0x38
-        __IO u32 ADDR8;
-    };
-    union {
-        __IO u32 CH9DR;                                                         ///< ADC channel9 data register,                    offset: 0x3C
-        __IO u32 ADDR9;
-    };
-    __IO u32 ADDR10;                                                            ///<                                                offset: 0x40
-    __IO u32 ADDR11;                                                            ///<                                                offset: 0x44
-    __IO u32 ADDR12;                                                            ///<                                                offset: 0x48
-    __IO u32 ADDR13;                                                            ///<                                                offset: 0x4C
-    union {
-        __IO u32 CH14DR;                                                        ///< ADC channel14 data register,                   offset: 0x50
-        __IO u32 ADDR14;
-    };
-    union {
-        __IO u32 CH15DR;                                                        ///< ADC channel15 data register,                   offset: 0x54
-        __IO u32 ADDR15;
-    };
-    __IO u32 SREXT;                                                             ///< ADC Extended Status Register,                  offset: 0x58
-    __IO u32 CHANY0;                                                            ///< ADC any Chan Select Register 0,                offset: 0x5C
-    __IO u32 CHANY1;                                                            ///< ADC any Chan Select Register 1,                offset: 0x60
-    __IO u32 ANYCFG;                                                            ///< ADC any Chan config Register,                  offset: 0x64
-    __IO u32 ANYCR;                                                             ///< ADC any Chan control Register,                 offset: 0x68
-    __IO u32 RESERVED0;                                                         ///<                                                offset 0x6C
-    __IO u32 SMPR1;                                                             ///< Sampling configuration register 1              offset 0x70
-    __IO u32 SMPR2;                                                             ///< Sampling configuration register 2              offset 0x74
-    __IO u32 RESERVED1;                                                         ///<                                                offset 0x78
-    __IO u32 JOFR0;                                                             ///< Injection channel data compensation register 0 offset 0x7C
-    __IO u32 JOFR1;                                                             ///< Injection channel data compensation register 1 offset 0x80
-    __IO u32 JOFR2;                                                             ///< Injection channel data compensation register 2 offset 0x84
-    __IO u32 JOFR3;                                                             ///< Injection channel data compensation register 3 offset 0x88
-    __IO u32 JSQR;                                                              ///< Injection sequence register                    offset 0x8C
-    __IO u32 JDATA;                                                             ///< Inject data register                           offset 0x90
-    __IO u32 RESERVED2;                                                         ///<                                                offset 0x94
-    __IO u32 RESERVED3;                                                         ///<                                                offset 0x98
-    __IO u32 RESERVED4;                                                         ///<                                                offset 0x9C
-    __IO u32 RESERVED5;                                                         ///<                                                offset 0xA0
-    __IO u32 RESERVED6;                                                         ///<                                                offset 0xA4
-    __IO u32 RESERVED7;                                                         ///<                                                offset 0xA8
-    __IO u32 RESERVED8;                                                         ///<                                                offset 0xAC
-    __IO u32 JDR0;                                                              ///< Injection channel data register 0              offset 0xB0
-    __IO u32 JDR1;                                                              ///< Injection channel data register 1              offset 0xB4
-    __IO u32 JDR2;                                                              ///< Injection channel data register 2              offset 0xB8
-    __IO u32 JDR3;                                                              ///< Injection channel data register 3              offset 0xBC
-} ADC_TypeDef;
-
-#endif
-#ifdef USENNEWREGISTER
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Analog-to-Digital Converter register
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 DR;                                                                ///< ADC data register,                             offset: 0x00
-    __IO u32 CFGR;                                                              ///< ADC configuration register,                    offset: 0x04
-    __IO u32 CR;                                                                ///< ADC control register,                          offset: 0x08
-    __IO u32 CHSR;                                                              ///< ADC channel selection register,                offset: 0x0C
-    __IO u32 CMPR;                                                              ///< ADC window compare register,                   offset: 0x10
-    __IO u32 SR;                                                                ///< ADC status register,                           offset: 0x14
-    __IO u32 CH0DR;                                                             ///< ADC channel0 data register,                    offset: 0x18
-    __IO u32 CH1DR;                                                             ///< ADC channel1 data register,                    offset: 0x1C
-    __IO u32 CH2DR;                                                             ///< ADC channel2 data register,                    offset: 0x20
-    __IO u32 CH3DR;                                                             ///< ADC channel3 data register,                    offset: 0x24
-    __IO u32 CH4DR;                                                             ///< ADC channel4 data register,                    offset: 0x28
-    __IO u32 CH5DR;                                                             ///< ADC channel5 data register,                    offset: 0x2C
-    __IO u32 CH6DR;                                                             ///< ADC channel6 data register,                    offset: 0x30
-    __IO u32 CH7DR;                                                             ///< ADC channel7 data register,                    offset: 0x34
-    __IO u32 CH8DR;                                                             ///< ADC channel8 data register,                    offset: 0x38
-} ADC_TypeDef;
-#endif
-#ifdef USENOLDREGISTER
-typedef struct {
-    __IO u32 ADDATA;                                                            ///< ADC data register,                             offset: 0x00
-    __IO u32 ADCFG;                                                             ///< ADC configuration register,                    offset: 0x04
-    __IO u32 ADCR;                                                              ///< ADC control register,                          offset: 0x08
-    __IO u32 ADCHS;                                                             ///< ADC channel selection register,                offset: 0x0C
-    __IO u32 ADCMPR;                                                            ///< ADC window compare register,                   offset: 0x10
-    __IO u32 ADSTA;                                                             ///< ADC status register,                           offset: 0x14
-    __IO u32 ADDR0;                                                             ///< ADC channel0 data register,                    offset: 0x18
-    __IO u32 ADDR1;                                                             ///< ADC channel1 data register,                    offset: 0x1C
-    __IO u32 ADDR2;                                                             ///< ADC channel2 data register,                    offset: 0x20
-    __IO u32 ADDR3;                                                             ///< ADC channel3 data register,                    offset: 0x24
-    __IO u32 ADDR4;                                                             ///< ADC channel4 data register,                    offset: 0x28
-    __IO u32 ADDR5;                                                             ///< ADC channel5 data register,                    offset: 0x2C
-    __IO u32 ADDR6;                                                             ///< ADC channel6 data register,                    offset: 0x30
-    __IO u32 ADDR7;                                                             ///< ADC channel7 data register,                    offset: 0x34
-    __IO u32 ADDR8;                                                             ///< ADC channel8 data register,                    offset: 0x38
-} ADC_TypeDef;
-#endif
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC1                            ((ADC_TypeDef*) ADC1_BASE)
-#define ADC2                            ((ADC_TypeDef*) ADC2_BASE)
-#define ADC3                            ((ADC_TypeDef*) ADC3_BASE)
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_DR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_DR_DATA_Pos                (0)
-#define ADC_DR_DATA                    (0xFFFFU << ADC_DR_DATA_Pos)            ///< ADC 12bit convert data
-
-#define ADC_DR_CH_Pos                  (16)
-#define ADC_DR_CH                      (0x0FU <<  ADC_DR_CH_Pos)               ///< CHANNELSEL[19:16] (ADC current channel convert data)
-
-#define ADC_DR_CH0                     (0x00U << ADC_DR_CH_Pos)                ///< ADC Channel select  0
-#define ADC_DR_CH1                     (0x01U << ADC_DR_CH_Pos)                ///< ADC Channel select  1
-#define ADC_DR_CH2                     (0x02U << ADC_DR_CH_Pos)                ///< ADC Channel select  2
-#define ADC_DR_CH3                     (0x03U << ADC_DR_CH_Pos)                ///< ADC Channel select  3
-#define ADC_DR_CH4                     (0x04U << ADC_DR_CH_Pos)                ///< ADC Channel select  4
-#define ADC_DR_CH5                     (0x05U << ADC_DR_CH_Pos)                ///< ADC Channel select  5
-#define ADC_DR_CH6                     (0x06U << ADC_DR_CH_Pos)                ///< ADC Channel select  6
-#define ADC_DR_CH7                     (0x07U << ADC_DR_CH_Pos)                ///< ADC Channel select  7
-
-#define ADC_DR_CH8                     (0x08U << ADC_DR_CH_Pos)                ///< ADC Channel select  8
-
-#define ADC_DR_CH10                    (0x0AU << ADC_DR_CH_Pos)                ///< ADC Channel select  10
-#define ADC_DR_CH11                    (0x0BU << ADC_DR_CH_Pos)                ///< ADC Channel select  11
-#define ADC_DR_CH13                    (0x0CU << ADC_DR_CH_Pos)                ///< ADC Channel select  13
-
-#define ADC_DR_CH9                     (0x09U << ADC_DR_CH_Pos)                ///< ADC Channel select  9
-#define ADC_DR_CH14                    (0x0EU << ADC_DR_CH_Pos)                ///< ADC Channel select  14
-#define ADC_DR_CH15                    (0x0FU << ADC_DR_CH_Pos)                ///< ADC Channel select  15
-#define ADC_DR_OVERRUN_Pos             (20)
-#define ADC_DR_OVERRUN                 (0x01U << ADC_DR_OVERRUN_Pos)           ///< ADC data will be cover
-#define ADC_DR_VALID_Pos               (21)
-#define ADC_DR_VALID                   (0x01U << ADC_DR_VALID_Pos)             ///< ADC data[11:0] is valid
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_CFGR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_CFGR_ADEN_Pos              (0)
-#define ADC_CFGR_ADEN                  (0x01U << ADC_CFGR_ADEN_Pos)            ///< Enable ADC convert
-#define ADC_CFGR_ADWEN_Pos             (1)
-#define ADC_CFGR_ADWEN                 (0x01U << ADC_CFGR_ADWEN_Pos)           ///< Enable ADC window compare
-
-
-#define ADC_CFGR_RSLTCTL_Pos           (7)
-#define ADC_CFGR_RSLTCTL               (0x07U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select
-#define ADC_CFGR_RSLTCTL_12            (0x00U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select 12bit
-#define ADC_CFGR_RSLTCTL_11            (0x01U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select 11bit
-#define ADC_CFGR_RSLTCTL_10            (0x02U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select 10bit
-#define ADC_CFGR_RSLTCTL_9             (0x03U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select 9bit
-#define ADC_CFGR_RSLTCTL_8             (0x04U << ADC_CFGR_RSLTCTL_Pos)         ///< ADC resolution select 8bit
-
-#define ADC_CFGR_TEN_Pos               (2)
-#define ADC_CFGR_TEN                   (0x01U << ADC_CFGR_TEN_Pos)                 ///< Enable ADC temperature sensor
-#define ADC_CFGR_VEN_Pos               (3)
-#define ADC_CFGR_VEN                   (0x01U << ADC_CFGR_VEN_Pos)                 ///< Enable ADC voltage reference
-
-
-
-
-
-#define ADC_CFGR_PRE_Pos                (4)
-#define ADC_CFGR_PREL_Pos               (14)
-#define ADC_CFGR_PRE                    ((0x07U << ADC_CFGR_PRE_Pos) + (0x01U << ADC_CFGR_PREL_Pos))
-#define ADC_CFGR_PRE_2                  (0x00U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 2
-#define ADC_CFGR_PRE_4                  (0x01U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 4
-#define ADC_CFGR_PRE_6                  (0x02U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 6
-#define ADC_CFGR_PRE_8                  (0x03U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 8
-#define ADC_CFGR_PRE_10                 (0x04U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 10
-#define ADC_CFGR_PRE_12                 (0x05U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 12
-#define ADC_CFGR_PRE_14                 (0x06U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 14
-#define ADC_CFGR_PRE_16                 (0x07U  << ADC_CFGR_PRE_Pos)            ///< ADC preclk 16
-#define ADC_CFGR_PRE_3                  ((0x01U << ADC_CFGR_PREL_Pos) + (0x00U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 3
-#define ADC_CFGR_PRE_5                  ((0x01U << ADC_CFGR_PREL_Pos) + (0x01U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 5
-#define ADC_CFGR_PRE_7                  ((0x01U << ADC_CFGR_PREL_Pos) + (0x02U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 7
-#define ADC_CFGR_PRE_9                  ((0x01U << ADC_CFGR_PREL_Pos) + (0x03U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 9
-#define ADC_CFGR_PRE_11                 ((0x01U << ADC_CFGR_PREL_Pos) + (0x04U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 11
-#define ADC_CFGR_PRE_13                 ((0x01U << ADC_CFGR_PREL_Pos) + (0x05U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 13
-#define ADC_CFGR_PRE_15                 ((0x01U << ADC_CFGR_PREL_Pos) + (0x06U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 15
-#define ADC_CFGR_PRE_17                 ((0x01U << ADC_CFGR_PREL_Pos) + (0x07U << ADC_CFGR_PRE_Pos))    ///< ADC preclk 17
-
-#define ADC_CFGR_JADWEN_Pos             (16)
-#define ADC_CFGR_JADWEN                 (0x01U << ADC_CFGR_JADWEN_Pos)              ///< Inject ADC conversion window comparison enable
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_CR_ADIE_Pos                (0)
-#define ADC_CR_ADIE                    (0x01U << ADC_CR_ADIE_Pos)              ///< ADC interrupt enable
-#define ADC_CR_ADWIE_Pos               (1)
-#define ADC_CR_ADWIE                   (0x01U << ADC_CR_ADWIE_Pos)             ///< ADC window compare interrupt enable
-#define ADC_CR_TRGEN_Pos               (2)
-#define ADC_CR_TRGEN                   (0x01U << ADC_CR_TRGEN_Pos)             ///< extranal trigger single start AD convert
-#define ADC_CR_DMAEN_Pos               (3)
-#define ADC_CR_DMAEN                   (0x01U << ADC_CR_DMAEN_Pos)             ///< ADC DMA enable
-
-#define ADC_CR_ADST_Pos                (8)
-#define ADC_CR_ADST                    (0x01U << ADC_CR_ADST_Pos)              ///< ADC start convert data
-#define ADC_CR_MODE_Pos                (9)
-#define ADC_CR_MODE                    (0x03U << ADC_CR_MODE_Pos)              ///< ADC convert mode
-#define ADC_CR_IMM                     (0x00U << ADC_CR_MODE_Pos)              ///< ADC imm convert mode
-#define ADC_CR_SCAN                    (0x01U << ADC_CR_MODE_Pos)              ///< ADC scan convert mode
-#define ADC_CR_CONTINUE                (0x02U << ADC_CR_MODE_Pos)              ///< ADC continue scan convert mode
-#define ADC_CR_ALIGN_Pos               (11)
-#define ADC_CR_ALIGN                   (0x01U << ADC_CR_ALIGN_Pos)             ///< ADC data align
-#define ADC_CR_LEFT                    (0x01U << ADC_CR_ALIGN_Pos)             ///< ADC data left align
-#define ADC_CR_RIGHT                   (0x00U << ADC_CR_ALIGN_Pos)             ///< ADC data right align
-#define ADC_CR_CMPCH_Pos               (12)
-#define ADC_CR_CMPCH                   (0x0FU << ADC_CR_CMPCH_Pos)             ///< CMPCH[15:12] ADC window compare channel0 convert data
-#define ADC_CR_CMPCH_0                 (0x00U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 0 Conversion Results
-#define ADC_CR_CMPCH_1                 (0x01U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 1 Conversion Results
-#define ADC_CR_CMPCH_2                 (0x02U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 2 Conversion Results
-#define ADC_CR_CMPCH_4                 (0x04U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 4 Conversion Results
-#define ADC_CR_CMPCH_5                 (0x05U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 5 Conversion Results
-#define ADC_CR_CMPCH_6                 (0x06U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 6 Conversion Results
-#define ADC_CR_CMPCH_7                 (0x07U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 7 Conversion Results
-#define ADC_CR_CMPCH_8                 (0x08U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 8 Conversion Results
-#define ADC_CR_CMPCH_9                 (0x09U << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 9 Conversion Results
-#define ADC_CR_CMPCH_10                (0x0AU << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 10 Conversion Results
-#define ADC_CR_CMPCH_11                (0x0BU << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 11 Conversion Results
-#define ADC_CR_CMPCH_13                (0x0DU << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 13 Conversion Results
-#define ADC_CR_CMPCH_14                (0x0EU << ADC_CR_CMPCH_Pos)             ///< Select Compare Channel 14 Conversion Results
-#define ADC_CR_CMPCH_ALL               (0x0FU << ADC_CR_CMPCH_Pos)             ///< Select Compare ALL Channel Conversion Results
-
-
-
-#define ADC_CR_SCANDIR_Pos              (16)
-#define ADC_CR_SCANDIR                  (0x01U << ADC_CR_SCANDIR_Pos)           ///< ADC scan direction
-#define ADC_CR_TRGSEL_H_Pos             (17)
-#define ADC_CR_TRGSEL_L_Pos             (4)
-#define ADC_CR_TRGSEL                   ((0x03U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos))   ///< TRGSEL[6:4][18:17] ADC external trigger source select
-#define ADC_CR_T1_CC1                   (0x00U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T1_CC1
-#define ADC_CR_T1_CC2                   (0x01U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T1_CC2
-#define ADC_CR_T1_CC3                   (0x02U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T1_CC3
-#define ADC_CR_T2_CC2                   (0x03U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T2_CC2
-#define ADC_CR_T3_TRIG                  (0x04U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T3_TRIG
-#define ADC_CR_T1_CC4_CC5               (0x05U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T1_CC4_CC5
-#define ADC_CR_T3_CC1                   (0x06U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is T3_CC1
-#define ADC_CR_EXTI_11                  (0x07U << ADC_CR_TRGSEL_L_Pos)          ///< The external trigger source of the ADC is EXTI_11
-#define ADC_CR_T1_TRIG                  ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T1_TRIG
-#define ADC_CR_T8_CC4               ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T8_CC4
-#define ADC_CR_T8_CC4_CC5           ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x02U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T8_CC4_CC5
-#define ADC_CR_T2_CC1                   ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x03U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T2_CC1
-#define ADC_CR_T3_CC4                   ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x04U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T3_CC4
-#define ADC_CR_T2_TRIG                  ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x05U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T2_TRIG
-#define ADC_CR_T8_CC5                   ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x06U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is T8_CC5
-#define ADC_CR_EXTI_15                  ((0x01U << ADC_CR_TRGSEL_H_Pos) + (0x07U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is EXTI_15
-#define ADC_CR_TIM1_CC4                 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x00U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is TIM1_CC4
-#define ADC_CR_TIM1_CC5                 ((0x02U << ADC_CR_TRGSEL_H_Pos) + (0x01U << ADC_CR_TRGSEL_L_Pos))   ///< The external trigger source of the ADC is TIM1_CC5
-
-#define ADC_CR_TRGSHIFT_Pos             (19)
-#define ADC_CR_TRGSHIFT                 (0x07U << ADC_CR_TRGSHIFT_Pos)          ///< External trigger shift sample
-#define ADC_CR_TRGSHIFT_0               (0x00U << ADC_CR_TRGSHIFT_Pos)          ///< No shift
-#define ADC_CR_TRGSHIFT_4               (0x01U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 4 period
-#define ADC_CR_TRGSHIFT_16              (0x02U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 16 period
-#define ADC_CR_TRGSHIFT_32              (0x03U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 32 period
-#define ADC_CR_TRGSHIFT_64              (0x04U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 64 period
-#define ADC_CR_TRGSHIFT_128             (0x05U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 128 period
-#define ADC_CR_TRGSHIFT_256             (0x06U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 256 period
-#define ADC_CR_TRGSHIFT_512             (0x07U << ADC_CR_TRGSHIFT_Pos)          ///< Shift 512 period
-#define ADC_CR_CALIBEN_Pos              (22)
-#define ADC_CR_CALIBEN                  (0x01U << ADC_CR_CALIBEN_Pos)           ///< Self-calibration enable
-#define ADC_CR_CALIBSEL_Pos             (23)
-#define ADC_CR_CALIBSEL                 (0x01U << ADC_CR_CALIBSEL_Pos)          ///< Self-calibration voltage selection
-#define ADC_CR_TRG_EDGE_Pos            (24)
-#define ADC_CR_TRG_EDGE                (0x03U << ADC_CR_TRG_EDGE_Pos)          ///< ADC trig edge config
-#define ADC_CR_TRG_EDGE_DUAL           (0x00U << ADC_CR_TRG_EDGE_Pos)          ///< ADC dual edge trig mode
-#define ADC_CR_TRG_EDGE_DOWN           (0x01U << ADC_CR_TRG_EDGE_Pos)          ///< ADC down edge trig mode
-#define ADC_CR_TRG_EDGE_UP             (0x02U << ADC_CR_TRG_EDGE_Pos)          ///< ADC up   edge trig mode
-#define ADC_CR_TRG_EDGE_MASK           (0x03U << ADC_CR_TRG_EDGE_Pos)          ///< ADC mask edge trig mode
-
-#define ADC_CR_EOSMPIE_Pos              (26)
-#define ADC_CR_EOSMPIE                  (0X01U << ADC_CR_EOSMPIE_Pos)            ///< ADC end sampling flag interrupt enable
-#define ADC_CR_EOCIE_Pos                (27)
-#define ADC_CR_EOCIE                    (0X01U << ADC_CR_EOCIE_Pos)            ///< ADC end of conversion interrupt enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_CHSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_CHSR_CH0_Pos               (0)
-#define ADC_CHSR_CH0                   (0x01U << ADC_CHSR_CH0_Pos)             ///< Enable ADC channel 0
-#define ADC_CHSR_CH1_Pos               (1)
-#define ADC_CHSR_CH1                   (0x01U << ADC_CHSR_CH1_Pos)             ///< Enable ADC channel 1
-#define ADC_CHSR_CH2_Pos               (2)
-#define ADC_CHSR_CH2                   (0x01U << ADC_CHSR_CH2_Pos)             ///< Enable ADC channel 2
-#define ADC_CHSR_CH3_Pos               (3)
-#define ADC_CHSR_CH3                   (0x01U << ADC_CHSR_CH3_Pos)             ///< Enable ADC channel 3
-#define ADC_CHSR_CH4_Pos               (4)
-#define ADC_CHSR_CH4                   (0x01U << ADC_CHSR_CH4_Pos)             ///< Enable ADC channel 4
-#define ADC_CHSR_CH5_Pos               (5)
-#define ADC_CHSR_CH5                   (0x01U << ADC_CHSR_CH5_Pos)             ///< Enable ADC channel 5
-#define ADC_CHSR_CH6_Pos               (6)
-#define ADC_CHSR_CH6                   (0x01U << ADC_CHSR_CH6_Pos)             ///< Enable ADC channel 6
-#define ADC_CHSR_CH7_Pos               (7)
-#define ADC_CHSR_CH7                   (0x01U << ADC_CHSR_CH7_Pos)             ///< Enable ADC channel 7
-
-#define ADC_CHSR_CH8_Pos               (8)
-#define ADC_CHSR_CH8                   (0x01U << ADC_CHSR_CH8_Pos)             ///< Enable ADC channel 8
-#define ADC_CHSR_CH9_Pos               (9)
-#define ADC_CHSR_CH9                   (0x01U << ADC_CHSR_CH9_Pos)             ///< Enable ADC channel 9
-#define ADC_CHSR_CHT_Pos               (14)
-#define ADC_CHSR_CHT                   (0x01U << ADC_CHSR_CHT_Pos)             ///< Enable Temperature Sensor
-#define ADC_CHSR_CHV_Pos               (15)
-#define ADC_CHSR_CHV                   (0x01U << ADC_CHSR_CHV_Pos)             ///< Enable Voltage Sensor
-
-
-#define ADC_CHSR_CH10_Pos              (10)
-#define ADC_CHSR_CH10                  (0x01U << ADC_CHSR_CH10_Pos)            ///< Enable ADC channel 10
-#define ADC_CHSR_CH11_Pos              (11)
-#define ADC_CHSR_CH11                  (0x01U << ADC_CHSR_CH11_Pos)            ///< Enable ADC channel 11
-#define ADC_CHSR_CH12_Pos              (12)
-#define ADC_CHSR_CH12                  (0x01U << ADC_CHSR_CH12_Pos)            ///< Enable ADC channel 12
-#define ADC_CHSR_CH13_Pos              (13)
-#define ADC_CHSR_CH13                  (0x01U << ADC_CHSR_CH13_Pos)            ///< Enable ADC channel 13
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_CMPR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_CMPR_CMPLDATA_Pos          (0)
-#define ADC_CMPR_CMPLDATA              (0x0FFFU << ADC_CMPR_CMPLDATA_Pos)      ///< ADC 12bit window compare DOWN LEVEL DATA
-#define ADC_CMPR_CMPHDATA_Pos          (16)
-#define ADC_CMPR_CMPHDATA              (0x0FFFU << ADC_CMPR_CMPHDATA_Pos)      ///< ADC 12bit window compare UP LEVEL DATA
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_SR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_SR_ADIF_Pos                (0)
-#define ADC_SR_ADIF                    (0x01U << ADC_SR_ADIF_Pos)              ///< ADC convert complete flag
-#define ADC_SR_ADWIF_Pos               (1)
-#define ADC_SR_ADWIF                   (0x01U << ADC_SR_ADWIF_Pos)             ///< ADC compare flag
-#define ADC_SR_BUSY_Pos                (2)
-#define ADC_SR_BUSY                    (0x01U << ADC_SR_BUSY_Pos)              ///< ADC busy flag
-#define ADC_SR_CH_Pos                  (4)
-#define ADC_SR_CH                      (0x0FU << ADC_SR_CH_Pos)                ///< CHANNEL[7:4] ADC current channel
-#define ADC_SR_CH0                     (0x00U << ADC_SR_CH_Pos)                ///< Channel 0 is the current conversion channel
-#define ADC_SR_CH1                     (0x01U << ADC_SR_CH_Pos)                ///< Channel 1 is the current conversion channel
-#define ADC_SR_CH2                     (0x02U << ADC_SR_CH_Pos)                ///< Channel 2 is the current conversion channel
-#define ADC_SR_CH3                     (0x03U << ADC_SR_CH_Pos)                ///< Channel 3 is the current conversion channel
-#define ADC_SR_CH4                     (0x04U << ADC_SR_CH_Pos)                ///< Channel 4 is the current conversion channel
-#define ADC_SR_CH5                     (0x05U << ADC_SR_CH_Pos)                ///< Channel 5 is the current conversion channel
-#define ADC_SR_CH6                     (0x06U << ADC_SR_CH_Pos)                ///< Channel 6 is the current conversion channel
-#define ADC_SR_CH7                     (0x07U << ADC_SR_CH_Pos)                ///< Channel 7 is the current conversion channel
-#define ADC_SR_CH8                     (0x08U << ADC_SR_CH_Pos)                ///< Channel 8 is the current conversion channel
-#define ADC_SR_CH9                     (0x09U << ADC_SR_CH_Pos)                ///< Channel 9 is the current conversion channel
-#define ADC_SR_CH10                    (0x0AU << ADC_SR_CH_Pos)                ///< Channel 10 is the current conversion channel
-#define ADC_SR_CH11                    (0x0BU << ADC_SR_CH_Pos)                ///< Channel 11 is the current conversion channel
-#define ADC_SR_CH13                    (0x0DU << ADC_SR_CH_Pos)                ///< Channel 13 is the current conversion channel
-#define ADC_SR_CH14                    (0x0EU << ADC_SR_CH_Pos)                ///< Channel 14 is the current conversion channel
-#define ADC_SR_CH15                    (0x0FU << ADC_SR_CH_Pos)                ///< Channel 15 is the current conversion channel
-
-
-#define ADC_SR_VALID_Pos               (8)
-#define ADC_SR_VALID                   (0x0FFFU << ADC_SR_VALID_Pos)           ///< VALID[19:8] ADC channel 0..11 valid flag
-#define ADC_SR_OVERRUN_Pos             (20)
-#define ADC_SR_OVERRUN                 (0x0FFFU << ADC_SR_OVERRUN_Pos)         ///< OVERRUN[31:20] ADC channel 0..11 data covered flag
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_CHnDR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_CHDR_DATA_Pos          (0)
-#define ADC_CHDR_DATA              (0xFFFFU << ADC_CHDR_DATA_Pos)          ///< ADC channel convert data
-#define ADC_CHDR_OVERRUN_Pos       (20)
-#define ADC_CHDR_OVERRUN           (0x01U << ADC_CHDR_OVERRUN_Pos)         ///< ADC data covered flag
-#define ADC_CHDR_VALID_Pos         (21)
-#define ADC_CHDR_VALID             (0x01U << ADC_CHDR_VALID_Pos)           ///< ADC data valid flag
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_SREXT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_SREXT_VALID_Pos             (0)
-#define ADC_SREXT_VALID                 (0x0FU << ADC_SREXT_VALID_Pos)          ///< VALID[3:0] ADC channel 12,14..15 valid flag
-#define ADC_SREXT_OVERRUN_Pos           (4)
-#define ADC_SREXT_OVERRUN               (0x0FU << ADC_SREXT_OVERRUN_Pos)        ///< OVERRUN[7:4] ADC channel 12,14..15 data covered flag
-
-
-#define ADC_SREXT_EOSMPIF_Pos       (16)
-#define ADC_SREXT_EOSMPIF           (0x01U << ADC_SREXT_EOSMPIF_Pos)       ///< End of sampling interrupt flag
-#define ADC_SREXT_EOCIF_Pos         (17)
-#define ADC_SREXT_EOCIF             (0x01U << ADC_SREXT_EOCIF_Pos)         ///< End of conversion interrupt flag
-#define ADC_SREXT_JEOSMPIF_Pos      (18)
-#define ADC_SREXT_JEOSMPIF          (0x01U << ADC_SREXT_JEOSMPIF_Pos)      /// Injected channel end of sampling interrupt flag
-#define ADC_SREXT_JEOCIF_Pos        (19)
-#define ADC_SREXT_JEOCIF            (0x03U << ADC_SREXT_JEOCIF_Pos)        ///< Injected channel end of conversion interrupt flag
-#define ADC_SREXT_JEOSIF_Pos        (20)
-#define ADC_SREXT_JEOSIF            (0x03U << ADC_SREXT_JEOSIF_Pos)        ///< Injected channel end of sequential conversion interrupt flag
-#define ADC_SREXT_JBUSY_Pos         (21)
-#define ADC_SREXT_JBUSY             (0x01U << ADC_SREXT_JBUSY_Pos)         ///< Injection mode busy/idle
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_CHANY0 select Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC1_CHANY0_SEL0_Pos            (0)                                     ///< CHANY_SEL0 (Bit 0)
-#define ADC1_CHANY0_SEL0                (0x0FU << ADC1_CHANY0_SEL0_Pos)         ///< CHANY_SEL0 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY0_SEL1_Pos            (4)                                     ///< CHANY_SEL1 (Bit 4)
-#define ADC1_CHANY0_SEL1                (0x0FU << ADC1_CHANY0_SEL1_Pos)         ///< CHANY_SEL1 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY0_SEL2_Pos            (8)                                     ///< CHANY_SEL2 (Bit 8)
-#define ADC1_CHANY0_SEL2                (0x0FU << ADC1_CHANY0_SEL2_Pos)         ///< CHANY_SEL2 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY0_SEL3_Pos            (12)                                    ///< CHANY_SEL3 (Bit 12)
-#define ADC1_CHANY0_SEL3                (0x0FU << ADC1_CHANY0_SEL3_Pos)         ///< CHANY_SEL3 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY0_SEL4_Pos            (16)                                    ///< CHANY_SEL4 (Bit 16)
-#define ADC1_CHANY0_SEL4                (0x0FU << ADC1_CHANY0_SEL4_Pos)         ///< CHANY_SEL4 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY0_SEL5_Pos            (20)                                    ///< CHANY_SEL5 (Bit 20)
-#define ADC1_CHANY0_SEL5                (0x0FU << ADC1_CHANY0_SEL5_Pos)         ///< CHANY_SEL5 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY0_SEL6_Pos            (24)                                    ///< CHANY_SEL6 (Bit 24)
-#define ADC1_CHANY0_SEL6                (0x0FU << ADC1_CHANY0_SEL6_Pos)         ///< CHANY_SEL6 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY0_SEL7_Pos            (28)                                    ///< CHANY_SEL7 (Bit 28)
-#define ADC1_CHANY0_SEL7                (0x0FU << ADC1_CHANY0_SEL7_Pos)         ///< CHANY_SEL7 (Bitfield-Mask: 0x0f)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_CHANY1 select Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC1_CHANY1_SEL8_Pos            (0)                                     ///< CHANY_SEL8 (Bit 0)
-#define ADC1_CHANY1_SEL8                (0x0FU << ADC1_CHANY1_SEL8_Pos)         ///< CHANY_SEL8 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY1_SEL9_Pos            (4)                                     ///< CHANY_SEL9 (Bit 4)
-#define ADC1_CHANY1_SEL9                (0x0FU << ADC1_CHANY1_SEL9_Pos)         ///< CHANY_SEL9 (Bitfield-Mask: 0x0f)
-
-#define ADC1_CHANY1_SEL14_Pos           (24)                                    ///< CHANY_SEL14 (Bit 24)
-#define ADC1_CHANY1_SEL14               (0x0FU << ADC1_CHANY1_SEL14_Pos)        ///< CHANY_SEL14 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY1_SEL15_Pos           (28)                                    ///< CHANY_SEL15 (Bit 28)
-#define ADC1_CHANY1_SEL15               (0x0FU << ADC1_CHANY1_SEL15_Pos)        ///< CHANY_SEL15 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY1_SEL10_Pos           (8)                                     ///< CHANY_SEL10 (Bit 8)
-#define ADC1_CHANY1_SEL10               (0x0FU << ADC1_CHANY1_SEL10_Pos)        ///< CHANY_SEL10 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY1_SEL11_Pos           (12)                                    ///< CHANY_SEL11 (Bit 12)
-#define ADC1_CHANY1_SEL11               (0x0FU << ADC1_CHANY1_SEL11_Pos)        ///< CHANY_SEL11 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY1_SEL12_Pos           (16)                                    ///< CHANY_SEL12 (Bit 16)
-#define ADC1_CHANY1_SEL12               (0x0FU << ADC1_CHANY1_SEL12_Pos)        ///< CHANY_SEL12 (Bitfield-Mask: 0x0f)
-#define ADC1_CHANY1_SEL13_Pos           (20)                                    ///< CHANY_SEL13 (Bit 20)
-#define ADC1_CHANY1_SEL13               (0x0FU << ADC1_CHANY1_SEL13_Pos)        ///< CHANY_SEL13 (Bitfield-Mask: 0x0f)
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_CHANY config number Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC1_CHANY_CFG_NUM_Max          (16)                                    ///< CHANY_CFG_NUM Max Value is 16
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_CHANY mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC1_CHANY_CR_MDEN_Pos          (0)                                     ///< CHANY_MDEN (Bit 0)
-#define ADC1_CHANY_CR_MDEN              (0x01U << ADC1_CHANY_CR_MDEN_Pos)       ///< CHANY_MDEN (Bitfield-Mask: 0x01)
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_ANY_CR mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_ANY_CR_JTRGEDGE_Pos         (16)                                    ///< Injection mode triggers edge selection
-#define ADC_ANY_CR_JTRGEDGE_R_F         (0x00U << ADC_ANY_CR_JTRGEDGE_Pos)      ///< Triggered along both rising and falling edges
-#define ADC_ANY_CR_JTRGEDGE_F           (0x01U << ADC_ANY_CR_JTRGEDGE_Pos)      ///< Drop edge trigger
-#define ADC_ANY_CR_JTRGEDGE_R           (0x02U << ADC_ANY_CR_JTRGEDGE_Pos)      ///< Rising edge trigger
-#define ADC_ANY_CR_JTRGEDGE_S           (0x03U << ADC_ANY_CR_JTRGEDGE_Pos)      ///< Shield trigger
-
-#define ADC_ANY_CR_JTRGSHIFT_Pos        (13)                                    ///< Injection mode external trigger delay sampling
-#define ADC_ANY_CR_JTRGSHIFT_0          (0x00U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 0   cycle
-#define ADC_ANY_CR_JTRGSHIFT_4          (0x01U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 4   cycle
-#define ADC_ANY_CR_JTRGSHIFT_16         (0x02U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 16  cycle
-#define ADC_ANY_CR_JTRGSHIFT_32         (0x03U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 32  cycle
-#define ADC_ANY_CR_JTRGSHIFT_64         (0x04U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 64  cycle
-#define ADC_ANY_CR_JTRGSHIFT_128        (0x05U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 128 cycle
-#define ADC_ANY_CR_JTRGSHIFT_256        (0x06U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 256 cycle
-#define ADC_ANY_CR_JTRGSHIFT_512        (0x07U << ADC_ANY_CR_JTRGSHIFT_Pos)     ///< 512 cycle
-
-#define ADC_ANY_CR_JTRGSEL_Pos          (8)                                     ///< External event select for injected group
-#define ADC_ANY_CR_JTRGSEL              (0x07U << ADC_ANY_CR_JTRGSEL_Pos)
-#define ADC_ANY_CR_JTRGSEL_TIM1_TRGO    (0x00U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM1 TRGO     
-#define ADC_ANY_CR_JTRGSEL_TIM1_CC4     (0x01U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM1 CC4      
-#define ADC_ANY_CR_JTRGSEL_TIM1_CC4_CC5 (0x02U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM1 CC4 and CC5  
-#define ADC_ANY_CR_JTRGSEL_TIM2_TIM4CC1 (0x03U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM2 CC1 and TIM4 CC1
-#define ADC_ANY_CR_JTRGSEL_TIM3_TIM5CC4 (0x04U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM3 CC4 and TIM5 CC4
-#define ADC_ANY_CR_JTRGSEL_TIM8_CC4     (0x05U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM8 CC4      
-#define ADC_ANY_CR_JTRGSEL_TIM8_CC4_CC5 (0x06U << ADC_ANY_CR_JTRGSEL_Pos)       ///< TIM8 CC4 and CC5  
-#define ADC_ANY_CR_JTRGSEL_EXTI12       (0x07U << ADC_ANY_CR_JTRGSEL_Pos)       ///< EXTI12        
-
-#define ADC_ANY_CR_JTRGEN_Pos           (7)
-#define ADC_ANY_CR_JTRGEN               (0x01U << ADC_ANY_CR_JTRGEN_Pos)        ///< External trigger conversion mode for injected channels
-#define ADC_ANY_CR_JADST_Pos            (6)
-#define ADC_ANY_CR_JADST                (0x01U << ADC_ANY_CR_JADST_Pos)         ///< Start conversion of injected channels
-#define ADC_ANY_CR_JAUTO_Pos            (5)
-#define ADC_ANY_CR_JAUTO                (0x01U << ADC_ANY_CR_JAUTO_Pos)         ///<Automatic Injected group conversion
-#define ADC_ANY_CR_JEOSIE_Pos           (4)
-#define ADC_ANY_CR_JEOSIE               (0x01U << ADC_ANY_CR_JEOSIE_Pos)        ///< Interrupt enable the end of sequence conversion for injected channel
-#define ADC_ANY_CR_JEOCIE_Pos           (3)
-#define ADC_ANY_CR_JEOCIE               (0x01U << ADC_ANY_CR_JEOCIE_Pos)        ///< Interrupt enable the end of conversion for injected channel
-#define ADC_ANY_CR_JEOSMPIE_Pos         (2)
-#define ADC_ANY_CR_JEOSMPIE             (0x01U << ADC_ANY_CR_JEOSMPIE_Pos)      ///< Interrupt enable the end of sequence conversion for injected channel
-#define ADC_ANY_CR_JCEN_Pos             (1)
-#define ADC_ANY_CR_JCEN                 (0x01U << ADC_ANY_CR_JCEN_Pos)          ///< Injected channel enable
-
-#define ADC_ANY_CR_CHANY_MDEN_Pos       (0)
-#define ADC_ANY_CR_CHANY_MDEN           (0x01U << ADC_ANY_CR_CHANY_MDEN_Pos)    ///< Enable bits for any channel configuration mode:
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_SMPR1 mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_SMPR_SAMCTL_Pos             (0)                                     ///< Injection mode external trigger delay sampling off_set Position
-#define ADC_SMPR_SAMCTL_Msk             (0x0FU << ADC_SMPR_SAMCTL_Pos)          ///< Injection mode external trigger delay sampling mask for Value
-#define ADC_SMPR_SAMCTL_2_5             (0x00U << ADC_SMPR_SAMCTL_Pos)          ///< 2.5    cycle
-#define ADC_SMPR_SAMCTL_8_5             (0x01U << ADC_SMPR_SAMCTL_Pos)          ///< 8.5    cycle
-#define ADC_SMPR_SAMCTL_14_5            (0x02U << ADC_SMPR_SAMCTL_Pos)          ///< 14.5   cycle
-#define ADC_SMPR_SAMCTL_29_5            (0x03U << ADC_SMPR_SAMCTL_Pos)          ///< 29.5   cycle
-#define ADC_SMPR_SAMCTL_42_5            (0x04U << ADC_SMPR_SAMCTL_Pos)          ///< 42.5   cycle
-#define ADC_SMPR_SAMCTL_56_5            (0x05U << ADC_SMPR_SAMCTL_Pos)          ///< 56.5   cycle
-#define ADC_SMPR_SAMCTL_72_5            (0x06U << ADC_SMPR_SAMCTL_Pos)          ///< 72.5   cycle
-#define ADC_SMPR_SAMCTL_240_5           (0x07U << ADC_SMPR_SAMCTL_Pos)          ///< 240.5  cycle
-#define ADC_SMPR_SAMCTL_3_5             (0x08U << ADC_SMPR_SAMCTL_Pos)          ///< 3.5    cycle
-#define ADC_SMPR_SAMCTL_4_5             (0x09U << ADC_SMPR_SAMCTL_Pos)          ///< 4.5    cycle
-#define ADC_SMPR_SAMCTL_5_5             (0x0AU << ADC_SMPR_SAMCTL_Pos)          ///< 5.5    cycle
-#define ADC_SMPR_SAMCTL_6_5             (0x0BU << ADC_SMPR_SAMCTL_Pos)          ///< 6.5    cycle
-#define ADC_SMPR_SAMCTL_7_5             (0x0CU << ADC_SMPR_SAMCTL_Pos)          ///< 7.5    cycle
-
-
-#define ADC_SMPR1_SAMCTL7_Pos           (28)                                    ///< Injection mode external trigger delay sampling
-#define ADC_SMPR1_SAMCTL7_Msk           (0x0FU << ADC_SMPR1_SAMCTL7_Pos)        ///< Injection mode external trigger delay sampling mask for Value
-#define ADC_SMPR1_SAMCTL7_2_5           (0x00U << ADC_SMPR1_SAMCTL7_Pos)        ///< 2.5    cycle
-#define ADC_SMPR1_SAMCTL7_8_5           (0x01U << ADC_SMPR1_SAMCTL7_Pos)        ///< 8.5    cycle
-#define ADC_SMPR1_SAMCTL7_14_5          (0x02U << ADC_SMPR1_SAMCTL7_Pos)        ///< 14.5   cycle
-#define ADC_SMPR1_SAMCTL7_29_5          (0x03U << ADC_SMPR1_SAMCTL7_Pos)        ///< 29.5   cycle
-#define ADC_SMPR1_SAMCTL7_42_5          (0x04U << ADC_SMPR1_SAMCTL7_Pos)        ///< 42.5   cycle
-#define ADC_SMPR1_SAMCTL7_56_5          (0x05U << ADC_SMPR1_SAMCTL7_Pos)        ///< 56.5   cycle
-#define ADC_SMPR1_SAMCTL7_72_5          (0x06U << ADC_SMPR1_SAMCTL7_Pos)        ///< 72.5   cycle
-#define ADC_SMPR1_SAMCTL7_240_5         (0x07U << ADC_SMPR1_SAMCTL7_Pos)        ///< 240.5  cycle
-#define ADC_SMPR1_SAMCTL7_3_5           (0x08U << ADC_SMPR1_SAMCTL7_Pos)        ///< 3.5    cycle
-#define ADC_SMPR1_SAMCTL7_4_5           (0x09U << ADC_SMPR1_SAMCTL7_Pos)        ///< 4.5    cycle
-#define ADC_SMPR1_SAMCTL7_5_5           (0x0AU << ADC_SMPR1_SAMCTL7_Pos)        ///< 5.5    cycle
-#define ADC_SMPR1_SAMCTL7_6_5           (0x0BU << ADC_SMPR1_SAMCTL7_Pos)        ///< 6.5    cycle
-#define ADC_SMPR1_SAMCTL7_7_5           (0x0CU << ADC_SMPR1_SAMCTL7_Pos)        ///< 7.5    cycle
-#define ADC_SMPR1_SAMCTL6_Pos           (24)                                    ///< Injection mode external trigger delay sampling
-#define ADC_SMPR1_SAMCTL6_2_5           (0x00U << ADC_SMPR1_SAMCTL6_Pos)        ///< 2.5    cycle
-#define ADC_SMPR1_SAMCTL6_8_5           (0x01U << ADC_SMPR1_SAMCTL6_Pos)        ///< 8.5    cycle
-#define ADC_SMPR1_SAMCTL6_14_5          (0x02U << ADC_SMPR1_SAMCTL6_Pos)        ///< 14.5   cycle
-#define ADC_SMPR1_SAMCTL6_29_5          (0x03U << ADC_SMPR1_SAMCTL6_Pos)        ///< 29.5   cycle
-#define ADC_SMPR1_SAMCTL6_42_5          (0x04U << ADC_SMPR1_SAMCTL6_Pos)        ///< 42.5   cycle
-#define ADC_SMPR1_SAMCTL6_56_5          (0x05U << ADC_SMPR1_SAMCTL6_Pos)        ///< 56.5   cycle
-#define ADC_SMPR1_SAMCTL6_72_5          (0x06U << ADC_SMPR1_SAMCTL6_Pos)        ///< 72.5   cycle
-#define ADC_SMPR1_SAMCTL6_240_5         (0x07U << ADC_SMPR1_SAMCTL6_Pos)        ///< 240.5  cycle
-#define ADC_SMPR1_SAMCTL6_3_5           (0x08U << ADC_SMPR1_SAMCTL6_Pos)        ///< 3.5    cycle
-#define ADC_SMPR1_SAMCTL6_4_5           (0x09U << ADC_SMPR1_SAMCTL6_Pos)        ///< 4.5    cycle
-#define ADC_SMPR1_SAMCTL6_5_5           (0x0AU << ADC_SMPR1_SAMCTL6_Pos)        ///< 5.5    cycle
-#define ADC_SMPR1_SAMCTL6_6_5           (0x0BU << ADC_SMPR1_SAMCTL6_Pos)        ///< 6.5    cycle
-#define ADC_SMPR1_SAMCTL6_7_5           (0x0CU << ADC_SMPR1_SAMCTL6_Pos)        ///< 7.5    cycle
-#define ADC_SMPR1_SAMCTL5_Pos           (20)                                    ///< Injection mode external trigger delay sampling
-#define ADC_SMPR1_SAMCTL5_2_5           (0x00U << ADC_SMPR1_SAMCTL5_Pos)        ///< 2.5    cycle
-#define ADC_SMPR1_SAMCTL5_8_5           (0x01U << ADC_SMPR1_SAMCTL5_Pos)        ///< 8.5    cycle
-#define ADC_SMPR1_SAMCTL5_14_5          (0x02U << ADC_SMPR1_SAMCTL5_Pos)        ///< 14.5   cycle
-#define ADC_SMPR1_SAMCTL5_29_5          (0x03U << ADC_SMPR1_SAMCTL5_Pos)        ///< 29.5   cycle
-#define ADC_SMPR1_SAMCTL5_42_5          (0x04U << ADC_SMPR1_SAMCTL5_Pos)        ///< 42.5   cycle
-#define ADC_SMPR1_SAMCTL5_56_5          (0x05U << ADC_SMPR1_SAMCTL5_Pos)        ///< 56.5   cycle
-#define ADC_SMPR1_SAMCTL5_72_5          (0x06U << ADC_SMPR1_SAMCTL5_Pos)        ///< 72.5   cycle
-#define ADC_SMPR1_SAMCTL5_240_5         (0x07U << ADC_SMPR1_SAMCTL5_Pos)        ///< 240.5  cycle
-#define ADC_SMPR1_SAMCTL5_3_5           (0x08U << ADC_SMPR1_SAMCTL5_Pos)        ///< 3.5    cycle
-#define ADC_SMPR1_SAMCTL5_4_5           (0x09U << ADC_SMPR1_SAMCTL5_Pos)        ///< 4.5    cycle
-#define ADC_SMPR1_SAMCTL5_5_5           (0x0AU << ADC_SMPR1_SAMCTL5_Pos)        ///< 5.5    cycle
-#define ADC_SMPR1_SAMCTL5_6_5           (0x0BU << ADC_SMPR1_SAMCTL5_Pos)        ///< 6.5    cycle
-#define ADC_SMPR1_SAMCTL5_7_5           (0x0CU << ADC_SMPR1_SAMCTL5_Pos)        ///< 7.5    cycle
-#define ADC_SMPR1_SAMCTL4_Pos           (16)                                    ///< Injection mode external trigger delay sampling
-#define ADC_SMPR1_SAMCTL4_2_5           (0x00U << ADC_SMPR1_SAMCTL4_Pos)        ///< 2.5    cycle
-#define ADC_SMPR1_SAMCTL4_8_5           (0x01U << ADC_SMPR1_SAMCTL4_Pos)        ///< 8.5    cycle
-#define ADC_SMPR1_SAMCTL4_14_5          (0x02U << ADC_SMPR1_SAMCTL4_Pos)        ///< 14.5   cycle
-#define ADC_SMPR1_SAMCTL4_29_5          (0x03U << ADC_SMPR1_SAMCTL4_Pos)        ///< 29.5   cycle
-#define ADC_SMPR1_SAMCTL4_42_5          (0x04U << ADC_SMPR1_SAMCTL4_Pos)        ///< 42.5   cycle
-#define ADC_SMPR1_SAMCTL4_56_5          (0x05U << ADC_SMPR1_SAMCTL4_Pos)        ///< 56.5   cycle
-#define ADC_SMPR1_SAMCTL4_72_5          (0x06U << ADC_SMPR1_SAMCTL4_Pos)        ///< 72.5   cycle
-#define ADC_SMPR1_SAMCTL4_240_5         (0x07U << ADC_SMPR1_SAMCTL4_Pos)        ///< 240.5  cycle
-#define ADC_SMPR1_SAMCTL4_3_5           (0x08U << ADC_SMPR1_SAMCTL4_Pos)        ///< 3.5    cycle
-#define ADC_SMPR1_SAMCTL4_4_5           (0x09U << ADC_SMPR1_SAMCTL4_Pos)        ///< 4.5    cycle
-#define ADC_SMPR1_SAMCTL4_5_5           (0x0AU << ADC_SMPR1_SAMCTL4_Pos)        ///< 5.5    cycle
-#define ADC_SMPR1_SAMCTL4_6_5           (0x0BU << ADC_SMPR1_SAMCTL4_Pos)        ///< 6.5    cycle
-#define ADC_SMPR1_SAMCTL4_7_5           (0x0CU << ADC_SMPR1_SAMCTL4_Pos)        ///< 7.5    cycle
-#define ADC_SMPR1_SAMCTL3_Pos           (12)                                    ///< Injection mode external trigger delay sampling
-#define ADC_SMPR1_SAMCTL3_2_5           (0x00U << ADC_SMPR1_SAMCTL3_Pos)        ///< 2.5    cycle
-#define ADC_SMPR1_SAMCTL3_8_5           (0x01U << ADC_SMPR1_SAMCTL3_Pos)        ///< 8.5    cycle
-#define ADC_SMPR1_SAMCTL3_14_5          (0x02U << ADC_SMPR1_SAMCTL3_Pos)        ///< 14.5   cycle
-#define ADC_SMPR1_SAMCTL3_29_5          (0x03U << ADC_SMPR1_SAMCTL3_Pos)        ///< 29.5   cycle
-#define ADC_SMPR1_SAMCTL3_42_5          (0x04U << ADC_SMPR1_SAMCTL3_Pos)        ///< 42.5   cycle
-#define ADC_SMPR1_SAMCTL3_56_5          (0x05U << ADC_SMPR1_SAMCTL3_Pos)        ///< 56.5   cycle
-#define ADC_SMPR1_SAMCTL3_72_5          (0x06U << ADC_SMPR1_SAMCTL3_Pos)        ///< 72.5   cycle
-#define ADC_SMPR1_SAMCTL3_240_5         (0x07U << ADC_SMPR1_SAMCTL3_Pos)        ///< 240.5  cycle
-#define ADC_SMPR1_SAMCTL3_3_5           (0x08U << ADC_SMPR1_SAMCTL3_Pos)        ///< 3.5    cycle
-#define ADC_SMPR1_SAMCTL3_4_5           (0x09U << ADC_SMPR1_SAMCTL3_Pos)        ///< 4.5    cycle
-#define ADC_SMPR1_SAMCTL3_5_5           (0x0AU << ADC_SMPR1_SAMCTL3_Pos)        ///< 5.5    cycle
-#define ADC_SMPR1_SAMCTL3_6_5           (0x0BU << ADC_SMPR1_SAMCTL3_Pos)        ///< 6.5    cycle
-#define ADC_SMPR1_SAMCTL3_7_5           (0x0CU << ADC_SMPR1_SAMCTL3_Pos)        ///< 7.5    cycle
-#define ADC_SMPR1_SAMCTL2_Pos           (8)                                     ///< Injection mode external trigger delay sampling
-#define ADC_SMPR1_SAMCTL2_2_5           (0x00U << ADC_SMPR1_SAMCTL2_Pos)        ///< 2.5    cycle
-#define ADC_SMPR1_SAMCTL2_8_5           (0x01U << ADC_SMPR1_SAMCTL2_Pos)        ///< 8.5    cycle
-#define ADC_SMPR1_SAMCTL2_14_5          (0x02U << ADC_SMPR1_SAMCTL2_Pos)        ///< 14.5   cycle
-#define ADC_SMPR1_SAMCTL2_29_5          (0x03U << ADC_SMPR1_SAMCTL2_Pos)        ///< 29.5   cycle
-#define ADC_SMPR1_SAMCTL2_42_5          (0x04U << ADC_SMPR1_SAMCTL2_Pos)        ///< 42.5   cycle
-#define ADC_SMPR1_SAMCTL2_56_5          (0x05U << ADC_SMPR1_SAMCTL2_Pos)        ///< 56.5   cycle
-#define ADC_SMPR1_SAMCTL2_72_5          (0x06U << ADC_SMPR1_SAMCTL2_Pos)        ///< 72.5   cycle
-#define ADC_SMPR1_SAMCTL2_240_5         (0x07U << ADC_SMPR1_SAMCTL2_Pos)        ///< 240.5  cycle
-#define ADC_SMPR1_SAMCTL2_3_5           (0x08U << ADC_SMPR1_SAMCTL2_Pos)        ///< 3.5    cycle
-#define ADC_SMPR1_SAMCTL2_4_5           (0x09U << ADC_SMPR1_SAMCTL2_Pos)        ///< 4.5    cycle
-#define ADC_SMPR1_SAMCTL2_5_5           (0x0AU << ADC_SMPR1_SAMCTL2_Pos)        ///< 5.5    cycle
-#define ADC_SMPR1_SAMCTL2_6_5           (0x0BU << ADC_SMPR1_SAMCTL2_Pos)        ///< 6.5    cycle
-#define ADC_SMPR1_SAMCTL2_7_5           (0x0CU << ADC_SMPR1_SAMCTL2_Pos)        ///< 7.5    cycle
-#define ADC_SMPR1_SAMCTL1_Pos           (4)                                     ///< Injection mode external trigger delay sampling
-#define ADC_SMPR1_SAMCTL1_2_5           (0x00U << ADC_SMPR1_SAMCTL1_Pos)        ///< 2.5    cycle
-#define ADC_SMPR1_SAMCTL1_8_5           (0x01U << ADC_SMPR1_SAMCTL1_Pos)        ///< 8.5    cycle
-#define ADC_SMPR1_SAMCTL1_14_5          (0x02U << ADC_SMPR1_SAMCTL1_Pos)        ///< 14.5   cycle
-#define ADC_SMPR1_SAMCTL1_29_5          (0x03U << ADC_SMPR1_SAMCTL1_Pos)        ///< 29.5   cycle
-#define ADC_SMPR1_SAMCTL1_42_5          (0x04U << ADC_SMPR1_SAMCTL1_Pos)        ///< 42.5   cycle
-#define ADC_SMPR1_SAMCTL1_56_5          (0x05U << ADC_SMPR1_SAMCTL1_Pos)        ///< 56.5   cycle
-#define ADC_SMPR1_SAMCTL1_72_5          (0x06U << ADC_SMPR1_SAMCTL1_Pos)        ///< 72.5   cycle
-#define ADC_SMPR1_SAMCTL1_240_5         (0x07U << ADC_SMPR1_SAMCTL1_Pos)        ///< 240.5  cycle
-#define ADC_SMPR1_SAMCTL1_3_5           (0x08U << ADC_SMPR1_SAMCTL1_Pos)        ///< 3.5    cycle
-#define ADC_SMPR1_SAMCTL1_4_5           (0x09U << ADC_SMPR1_SAMCTL1_Pos)        ///< 4.5    cycle
-#define ADC_SMPR1_SAMCTL1_5_5           (0x0AU << ADC_SMPR1_SAMCTL1_Pos)        ///< 5.5    cycle
-#define ADC_SMPR1_SAMCTL1_6_5           (0x0BU << ADC_SMPR1_SAMCTL1_Pos)        ///< 6.5    cycle
-#define ADC_SMPR1_SAMCTL1_7_5           (0x0CU << ADC_SMPR1_SAMCTL1_Pos)        ///< 7.5    cycle
-#define ADC_SMPR1_SAMCTL0_Pos           (0)                                     ///< Injection mode external trigger delay sampling
-#define ADC_SMPR1_SAMCTL0_2_5           (0x00U << ADC_SMPR1_SAMCTL0_Pos)        ///< 2.5    cycle
-#define ADC_SMPR1_SAMCTL0_8_5           (0x01U << ADC_SMPR1_SAMCTL0_Pos)        ///< 8.5    cycle
-#define ADC_SMPR1_SAMCTL0_14_5          (0x02U << ADC_SMPR1_SAMCTL0_Pos)        ///< 14.5   cycle
-#define ADC_SMPR1_SAMCTL0_29_5          (0x03U << ADC_SMPR1_SAMCTL0_Pos)        ///< 29.5   cycle
-#define ADC_SMPR1_SAMCTL0_42_5          (0x04U << ADC_SMPR1_SAMCTL0_Pos)        ///< 42.5   cycle
-#define ADC_SMPR1_SAMCTL0_56_5          (0x05U << ADC_SMPR1_SAMCTL0_Pos)        ///< 56.5   cycle
-#define ADC_SMPR1_SAMCTL0_72_5          (0x06U << ADC_SMPR1_SAMCTL0_Pos)        ///< 72.5   cycle
-#define ADC_SMPR1_SAMCTL0_240_5         (0x07U << ADC_SMPR1_SAMCTL0_Pos)        ///< 240.5  cycle
-#define ADC_SMPR1_SAMCTL0_3_5           (0x08U << ADC_SMPR1_SAMCTL0_Pos)        ///< 3.5    cycle
-#define ADC_SMPR1_SAMCTL0_4_5           (0x09U << ADC_SMPR1_SAMCTL0_Pos)        ///< 4.5    cycle
-#define ADC_SMPR1_SAMCTL0_5_5           (0x0AU << ADC_SMPR1_SAMCTL0_Pos)        ///< 5.5    cycle
-#define ADC_SMPR1_SAMCTL0_6_5           (0x0BU << ADC_SMPR1_SAMCTL0_Pos)        ///< 6.5    cycle
-#define ADC_SMPR1_SAMCTL0_7_5           (0x0CU << ADC_SMPR1_SAMCTL0_Pos)        ///< 7.5    cycle
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_SMPR2 mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_SMPR2_SAMCTL15_Pos          (28)                                     ///< Injection mode external trigger delay sampling
-#define ADC_SMPR2_SAMCTL15_2_5          (0x00U << ADC_SMPR2_SAMCTL15_Pos)        ///< 2.5    cycle
-#define ADC_SMPR2_SAMCTL15_8_5          (0x01U << ADC_SMPR2_SAMCTL15_Pos)        ///< 8.5    cycle
-#define ADC_SMPR2_SAMCTL15_14_5         (0x02U << ADC_SMPR2_SAMCTL15_Pos)        ///< 14.5   cycle
-#define ADC_SMPR2_SAMCTL15_29_5         (0x03U << ADC_SMPR2_SAMCTL15_Pos)        ///< 29.5   cycle
-#define ADC_SMPR2_SAMCTL15_42_5         (0x04U << ADC_SMPR2_SAMCTL15_Pos)        ///< 42.5   cycle
-#define ADC_SMPR2_SAMCTL15_56_5         (0x05U << ADC_SMPR2_SAMCTL15_Pos)        ///< 56.5   cycle
-#define ADC_SMPR2_SAMCTL15_72_5         (0x06U << ADC_SMPR2_SAMCTL15_Pos)        ///< 72.5   cycle
-#define ADC_SMPR2_SAMCTL15_240_5        (0x07U << ADC_SMPR2_SAMCTL15_Pos)        ///< 240.5  cycle
-#define ADC_SMPR2_SAMCTL15_3_5          (0x08U << ADC_SMPR2_SAMCTL15_Pos)        ///< 3.5    cycle
-#define ADC_SMPR2_SAMCTL15_4_5          (0x09U << ADC_SMPR2_SAMCTL15_Pos)        ///< 4.5    cycle
-#define ADC_SMPR2_SAMCTL15_5_5          (0x0AU << ADC_SMPR2_SAMCTL15_Pos)        ///< 5.5    cycle
-#define ADC_SMPR2_SAMCTL15_6_5          (0x0BU << ADC_SMPR2_SAMCTL15_Pos)        ///< 6.5    cycle
-#define ADC_SMPR2_SAMCTL15_7_5          (0x0CU << ADC_SMPR2_SAMCTL15_Pos)        ///< 7.5    cycle
-#define ADC_SMPR2_SAMCTL14_Pos          (24)                                    ///< Injection mode external trigger delay sampling
-#define ADC_SMPR2_SAMCTL14_2_5          (0x00U << ADC_SMPR2_SAMCTL14_Pos)        ///< 2.5    cycle
-#define ADC_SMPR2_SAMCTL14_8_5          (0x01U << ADC_SMPR2_SAMCTL14_Pos)        ///< 8.5    cycle
-#define ADC_SMPR2_SAMCTL14_14_5         (0x02U << ADC_SMPR2_SAMCTL14_Pos)        ///< 14.5   cycle
-#define ADC_SMPR2_SAMCTL14_29_5         (0x03U << ADC_SMPR2_SAMCTL14_Pos)        ///< 29.5   cycle
-#define ADC_SMPR2_SAMCTL14_42_5         (0x04U << ADC_SMPR2_SAMCTL14_Pos)        ///< 42.5   cycle
-#define ADC_SMPR2_SAMCTL14_56_5         (0x05U << ADC_SMPR2_SAMCTL14_Pos)        ///< 56.5   cycle
-#define ADC_SMPR2_SAMCTL14_72_5         (0x06U << ADC_SMPR2_SAMCTL14_Pos)        ///< 72.5   cycle
-#define ADC_SMPR2_SAMCTL14_240_5        (0x07U << ADC_SMPR2_SAMCTL14_Pos)        ///< 240.5  cycle
-#define ADC_SMPR2_SAMCTL14_3_5          (0x08U << ADC_SMPR2_SAMCTL14_Pos)        ///< 3.5    cycle
-#define ADC_SMPR2_SAMCTL14_4_5          (0x09U << ADC_SMPR2_SAMCTL14_Pos)        ///< 4.5    cycle
-#define ADC_SMPR2_SAMCTL14_5_5          (0x0AU << ADC_SMPR2_SAMCTL14_Pos)        ///< 5.5    cycle
-#define ADC_SMPR2_SAMCTL14_6_5          (0x0BU << ADC_SMPR2_SAMCTL14_Pos)        ///< 6.5    cycle
-#define ADC_SMPR2_SAMCTL14_7_5          (0x0CU << ADC_SMPR2_SAMCTL14_Pos)        ///< 7.5    cycle
-#define ADC_SMPR2_SAMCTL13_Pos          (20)                                    ///< Injection mode external trigger delay sampling
-#define ADC_SMPR2_SAMCTL13_2_5          (0x00U << ADC_SMPR2_SAMCTL13_Pos)        ///< 2.5    cycle
-#define ADC_SMPR2_SAMCTL13_8_5          (0x01U << ADC_SMPR2_SAMCTL13_Pos)        ///< 8.5    cycle
-#define ADC_SMPR2_SAMCTL13_14_5         (0x02U << ADC_SMPR2_SAMCTL13_Pos)        ///< 14.5   cycle
-#define ADC_SMPR2_SAMCTL13_29_5         (0x03U << ADC_SMPR2_SAMCTL13_Pos)        ///< 29.5   cycle
-#define ADC_SMPR2_SAMCTL13_42_5         (0x04U << ADC_SMPR2_SAMCTL13_Pos)        ///< 42.5   cycle
-#define ADC_SMPR2_SAMCTL13_56_5         (0x05U << ADC_SMPR2_SAMCTL13_Pos)        ///< 56.5   cycle
-#define ADC_SMPR2_SAMCTL13_72_5         (0x06U << ADC_SMPR2_SAMCTL13_Pos)        ///< 72.5   cycle
-#define ADC_SMPR2_SAMCTL13_240_5        (0x07U << ADC_SMPR2_SAMCTL13_Pos)        ///< 240.5  cycle
-#define ADC_SMPR2_SAMCTL13_3_5          (0x08U << ADC_SMPR2_SAMCTL13_Pos)        ///< 3.5    cycle
-#define ADC_SMPR2_SAMCTL13_4_5          (0x09U << ADC_SMPR2_SAMCTL13_Pos)        ///< 4.5    cycle
-#define ADC_SMPR2_SAMCTL13_5_5          (0x0AU << ADC_SMPR2_SAMCTL13_Pos)        ///< 5.5    cycle
-#define ADC_SMPR2_SAMCTL13_6_5          (0x0BU << ADC_SMPR2_SAMCTL13_Pos)        ///< 6.5    cycle
-#define ADC_SMPR2_SAMCTL13_7_5          (0x0CU << ADC_SMPR2_SAMCTL13_Pos)        ///< 7.5    cycle
-#define ADC_SMPR2_SAMCTL12_Pos          (16)                                    ///< Injection mode external trigger delay sampling
-#define ADC_SMPR2_SAMCTL12_2_5          (0x00U << ADC_SMPR2_SAMCTL12_Pos)        ///< 2.5    cycle
-#define ADC_SMPR2_SAMCTL12_8_5          (0x01U << ADC_SMPR2_SAMCTL12_Pos)        ///< 8.5    cycle
-#define ADC_SMPR2_SAMCTL12_14_5         (0x02U << ADC_SMPR2_SAMCTL12_Pos)        ///< 14.5   cycle
-#define ADC_SMPR2_SAMCTL12_29_5         (0x03U << ADC_SMPR2_SAMCTL12_Pos)        ///< 29.5   cycle
-#define ADC_SMPR2_SAMCTL12_42_5         (0x04U << ADC_SMPR2_SAMCTL12_Pos)        ///< 42.5   cycle
-#define ADC_SMPR2_SAMCTL12_56_5         (0x05U << ADC_SMPR2_SAMCTL12_Pos)        ///< 56.5   cycle
-#define ADC_SMPR2_SAMCTL12_72_5         (0x06U << ADC_SMPR2_SAMCTL12_Pos)        ///< 72.5   cycle
-#define ADC_SMPR2_SAMCTL12_240_5        (0x07U << ADC_SMPR2_SAMCTL12_Pos)        ///< 240.5  cycle
-#define ADC_SMPR2_SAMCTL12_3_5          (0x08U << ADC_SMPR2_SAMCTL12_Pos)        ///< 3.5    cycle
-#define ADC_SMPR2_SAMCTL12_4_5          (0x09U << ADC_SMPR2_SAMCTL12_Pos)        ///< 4.5    cycle
-#define ADC_SMPR2_SAMCTL12_5_5          (0x0AU << ADC_SMPR2_SAMCTL12_Pos)        ///< 5.5    cycle
-#define ADC_SMPR2_SAMCTL12_6_5          (0x0BU << ADC_SMPR2_SAMCTL12_Pos)        ///< 6.5    cycle
-#define ADC_SMPR2_SAMCTL12_7_5          (0x0CU << ADC_SMPR2_SAMCTL12_Pos)        ///< 7.5    cycle
-#define ADC_SMPR2_SAMCTL11_Pos          (12)                                    ///< Injection mode external trigger delay sampling
-#define ADC_SMPR2_SAMCTL11_2_5          (0x00U << ADC_SMPR2_SAMCTL11_Pos)        ///< 2.5    cycle
-#define ADC_SMPR2_SAMCTL11_8_5          (0x01U << ADC_SMPR2_SAMCTL11_Pos)        ///< 8.5    cycle
-#define ADC_SMPR2_SAMCTL11_14_5         (0x02U << ADC_SMPR2_SAMCTL11_Pos)        ///< 14.5   cycle
-#define ADC_SMPR2_SAMCTL11_29_5         (0x03U << ADC_SMPR2_SAMCTL11_Pos)        ///< 29.5   cycle
-#define ADC_SMPR2_SAMCTL11_42_5         (0x04U << ADC_SMPR2_SAMCTL11_Pos)        ///< 42.5   cycle
-#define ADC_SMPR2_SAMCTL11_56_5         (0x05U << ADC_SMPR2_SAMCTL11_Pos)        ///< 56.5   cycle
-#define ADC_SMPR2_SAMCTL11_72_5         (0x06U << ADC_SMPR2_SAMCTL11_Pos)        ///< 72.5   cycle
-#define ADC_SMPR2_SAMCTL11_240_5        (0x07U << ADC_SMPR2_SAMCTL11_Pos)        ///< 240.5  cycle
-#define ADC_SMPR2_SAMCTL11_3_5          (0x08U << ADC_SMPR2_SAMCTL11_Pos)        ///< 3.5    cycle
-#define ADC_SMPR2_SAMCTL11_4_5          (0x09U << ADC_SMPR2_SAMCTL11_Pos)        ///< 4.5    cycle
-#define ADC_SMPR2_SAMCTL11_5_5          (0x0AU << ADC_SMPR2_SAMCTL11_Pos)        ///< 5.5    cycle
-#define ADC_SMPR2_SAMCTL11_6_5          (0x0BU << ADC_SMPR2_SAMCTL11_Pos)        ///< 6.5    cycle
-#define ADC_SMPR2_SAMCTL11_7_5          (0x0CU << ADC_SMPR2_SAMCTL11_Pos)        ///< 7.5    cycle
-#define ADC_SMPR2_SAMCTL10_Pos          (8)                                     ///< Injection mode external trigger delay sampling
-#define ADC_SMPR2_SAMCTL10_2_5          (0x00U << ADC_SMPR2_SAMCTL10_Pos)        ///< 2.5    cycle
-#define ADC_SMPR2_SAMCTL10_8_5          (0x01U << ADC_SMPR2_SAMCTL10_Pos)        ///< 8.5    cycle
-#define ADC_SMPR2_SAMCTL10_14_5         (0x02U << ADC_SMPR2_SAMCTL10_Pos)        ///< 14.5   cycle
-#define ADC_SMPR2_SAMCTL10_29_5         (0x03U << ADC_SMPR2_SAMCTL10_Pos)        ///< 29.5   cycle
-#define ADC_SMPR2_SAMCTL10_42_5         (0x04U << ADC_SMPR2_SAMCTL10_Pos)        ///< 42.5   cycle
-#define ADC_SMPR2_SAMCTL10_56_5         (0x05U << ADC_SMPR2_SAMCTL10_Pos)        ///< 56.5   cycle
-#define ADC_SMPR2_SAMCTL10_72_5         (0x06U << ADC_SMPR2_SAMCTL10_Pos)        ///< 72.5   cycle
-#define ADC_SMPR2_SAMCTL10_240_5        (0x07U << ADC_SMPR2_SAMCTL10_Pos)        ///< 240.5  cycle
-#define ADC_SMPR2_SAMCTL10_3_5          (0x08U << ADC_SMPR2_SAMCTL10_Pos)        ///< 3.5    cycle
-#define ADC_SMPR2_SAMCTL10_4_5          (0x09U << ADC_SMPR2_SAMCTL10_Pos)        ///< 4.5    cycle
-#define ADC_SMPR2_SAMCTL10_5_5          (0x0AU << ADC_SMPR2_SAMCTL10_Pos)        ///< 5.5    cycle
-#define ADC_SMPR2_SAMCTL10_6_5          (0x0BU << ADC_SMPR2_SAMCTL10_Pos)        ///< 6.5    cycle
-#define ADC_SMPR2_SAMCTL10_7_5          (0x0CU << ADC_SMPR2_SAMCTL10_Pos)        ///< 7.5    cycle
-#define ADC_SMPR2_SAMCTL9_Pos           (4)                                     ///< Injection mode external trigger delay sampling
-#define ADC_SMPR2_SAMCTL9_2_5           (0x00U << ADC_SMPR2_SAMCTL9_Pos)        ///< 2.5    cycle
-#define ADC_SMPR2_SAMCTL9_8_5           (0x01U << ADC_SMPR2_SAMCTL9_Pos)        ///< 8.5    cycle
-#define ADC_SMPR2_SAMCTL9_14_5          (0x02U << ADC_SMPR2_SAMCTL9_Pos)        ///< 14.5   cycle
-#define ADC_SMPR2_SAMCTL9_29_5          (0x03U << ADC_SMPR2_SAMCTL9_Pos)        ///< 29.5   cycle
-#define ADC_SMPR2_SAMCTL9_42_5          (0x04U << ADC_SMPR2_SAMCTL9_Pos)        ///< 42.5   cycle
-#define ADC_SMPR2_SAMCTL9_56_5          (0x05U << ADC_SMPR2_SAMCTL9_Pos)        ///< 56.5   cycle
-#define ADC_SMPR2_SAMCTL9_72_5          (0x06U << ADC_SMPR2_SAMCTL9_Pos)        ///< 72.5   cycle
-#define ADC_SMPR2_SAMCTL9_240_5         (0x07U << ADC_SMPR2_SAMCTL9_Pos)        ///< 240.5  cycle
-#define ADC_SMPR2_SAMCTL9_3_5           (0x08U << ADC_SMPR2_SAMCTL9_Pos)        ///< 3.5    cycle
-#define ADC_SMPR2_SAMCTL9_4_5           (0x09U << ADC_SMPR2_SAMCTL9_Pos)        ///< 4.5    cycle
-#define ADC_SMPR2_SAMCTL9_5_5           (0x0AU << ADC_SMPR2_SAMCTL9_Pos)        ///< 5.5    cycle
-#define ADC_SMPR2_SAMCTL9_6_5           (0x0BU << ADC_SMPR2_SAMCTL9_Pos)        ///< 6.5    cycle
-#define ADC_SMPR2_SAMCTL9_7_5           (0x0CU << ADC_SMPR2_SAMCTL9_Pos)        ///< 7.5    cycle
-#define ADC_SMPR2_SAMCTL8_Pos           (0)                                     ///< Injection mode external trigger delay sampling
-#define ADC_SMPR2_SAMCTL8_2_5           (0x00U << ADC_SMPR2_SAMCTL8_Pos)        ///< 2.5    cycle
-#define ADC_SMPR2_SAMCTL8_8_5           (0x01U << ADC_SMPR2_SAMCTL8_Pos)        ///< 8.5    cycle
-#define ADC_SMPR2_SAMCTL8_14_5          (0x02U << ADC_SMPR2_SAMCTL8_Pos)        ///< 14.5   cycle
-#define ADC_SMPR2_SAMCTL8_29_5          (0x03U << ADC_SMPR2_SAMCTL8_Pos)        ///< 29.5   cycle
-#define ADC_SMPR2_SAMCTL8_42_5          (0x04U << ADC_SMPR2_SAMCTL8_Pos)        ///< 42.5   cycle
-#define ADC_SMPR2_SAMCTL8_56_5          (0x05U << ADC_SMPR2_SAMCTL8_Pos)        ///< 56.5   cycle
-#define ADC_SMPR2_SAMCTL8_72_5          (0x06U << ADC_SMPR2_SAMCTL8_Pos)        ///< 72.5   cycle
-#define ADC_SMPR2_SAMCTL8_240_5         (0x07U << ADC_SMPR2_SAMCTL8_Pos)        ///< 240.5  cycle
-#define ADC_SMPR2_SAMCTL8_3_5           (0x08U << ADC_SMPR2_SAMCTL8_Pos)        ///< 3.5    cycle
-#define ADC_SMPR2_SAMCTL8_4_5           (0x09U << ADC_SMPR2_SAMCTL8_Pos)        ///< 4.5    cycle
-#define ADC_SMPR2_SAMCTL8_5_5           (0x0AU << ADC_SMPR2_SAMCTL8_Pos)        ///< 5.5    cycle
-#define ADC_SMPR2_SAMCTL8_6_5           (0x0BU << ADC_SMPR2_SAMCTL8_Pos)        ///< 6.5    cycle
-#define ADC_SMPR2_SAMCTL8_7_5           (0x0CU << ADC_SMPR2_SAMCTL8_Pos)        ///< 7.5    cycle
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_JOFR0 mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_JOFR0_JOFR                  (0xFFFU)                                ///< Compensates for the A/D conversion results of the injected channel 0
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_JOFR1 mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_JOFR1_JOFR                  (0xFFFU)                                ///< Compensates for the A/D conversion results of the injected channel 1
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_JOFR2 mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_JOFR2_JOFR                  (0xFFFU)                                ///< Compensates for the A/D conversion results of the injected channel 2
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_JOFR3 mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_JOFR3_JOFR                  (0xFFFU)                                ///< Compensates for the A/D conversion results of the injected channel 3
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_JSQR mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_JSQR_JSQ0_Pos            (0)                                          ///< 1st conversion in injected sequence
-#define ADC_JSQR_JSQ0_0             (0x01U << ADC_JSQR_JSQ0_Pos)                  ///< Bit 0
-#define ADC_JSQR_JSQ0_1             (0x02U << ADC_JSQR_JSQ0_Pos)                  ///< Bit 1
-#define ADC_JSQR_JSQ0_2             (0x04U << ADC_JSQR_JSQ0_Pos)                  ///< Bit 2
-#define ADC_JSQR_JSQ0_3             (0x08U << ADC_JSQR_JSQ0_Pos)                  ///< Bit 3
-#define ADC_JSQR_JSQ0_4             (0x10U << ADC_JSQR_JSQ0_Pos)                  ///< Bit 4
-#define ADC_JSQR_JSQ1_Pos           (5 )                                          ///< 2st conversion in injected sequence
-#define ADC_JSQR_JSQ1_0             (0x01U << ADC_JSQR_JSQ1_Pos)                  ///< Bit 0
-#define ADC_JSQR_JSQ1_1             (0x02U << ADC_JSQR_JSQ1_Pos)                  ///< Bit 1
-#define ADC_JSQR_JSQ1_2             (0x04U << ADC_JSQR_JSQ1_Pos)                  ///< Bit 2
-#define ADC_JSQR_JSQ1_3             (0x08U << ADC_JSQR_JSQ1_Pos)                  ///< Bit 3
-#define ADC_JSQR_JSQ1_4             (0x10U << ADC_JSQR_JSQ1_Pos)                  ///< Bit 4
-#define ADC_JSQR_JSQ2_Pos           (10)                                          ///< 3st conversion in injected sequence
-#define ADC_JSQR_JSQ2_0             (0x01U << ADC_JSQR_JSQ2_Pos)                  ///< Bit 0
-#define ADC_JSQR_JSQ2_1             (0x02U << ADC_JSQR_JSQ2_Pos)                  ///< Bit 1
-#define ADC_JSQR_JSQ2_2             (0x04U << ADC_JSQR_JSQ2_Pos)                  ///< Bit 2
-#define ADC_JSQR_JSQ2_3             (0x08U << ADC_JSQR_JSQ2_Pos)                  ///< Bit 3
-#define ADC_JSQR_JSQ2_4             (0x10U << ADC_JSQR_JSQ2_Pos)                  ///< Bit 4
-#define ADC_JSQR_JSQ3_Pos           (15)                                          ///< 4st conversion in injected sequence
-#define ADC_JSQR_JSQ3_0             (0x01U << ADC_JSQR_JSQ3_Pos)                  ///< Bit 0
-#define ADC_JSQR_JSQ3_1             (0x02U << ADC_JSQR_JSQ3_Pos)                  ///< Bit 1
-#define ADC_JSQR_JSQ3_2             (0x04U << ADC_JSQR_JSQ3_Pos)                  ///< Bit 2
-#define ADC_JSQR_JSQ3_3             (0x08U << ADC_JSQR_JSQ3_Pos)                  ///< Bit 3
-#define ADC_JSQR_JSQ3_4             (0x10U << ADC_JSQR_JSQ3_Pos)                  ///< Bit 4
-
-#define ADC_JSQR_JL_Pos             (20)                                          ///< Injected Sequence length
-#define ADC_JSQR_JL_0               (0x01U << ADC_JSQR_JL_Pos)                    ///< Bit 0
-#define ADC_JSQR_JL_1               (0x02U << ADC_JSQR_JL_Pos)                    ///< Bit 1
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_JDATA mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_JDATA_JVALID_Pos          (22)
-#define ADC_JDATA_JVALID              (0x01U << ADC_JDATA_JVALID_Pos)               ///< Valid flag
-#define ADC_JDATA_JOVERRUN_Pos        (21)
-#define ADC_JDATA_JOVERRUN            (0x01U << ADC_JDATA_JOVERRUN_Pos)             ///< Overrun flag
-#define ADC_JDATA_JCHANNELSEL_Pos     (16)
-#define ADC_JDATA_JCHANNELSEL         (0xFFU << ADC_JDATA_JCHANNELSEL_Pos)          ///< Channel selection
-#define ADC_JDATA_JDATA_Pos           (0)
-#define ADC_JDATA_JDATA               (0xFFFFU << ADC_JSQR_JSQ0_Pos)                ///< Transfer data
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_JDR0 mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_JDR0_JVALID_Pos          (22)
-#define ADC_JDR0_JVALID              (0x01U << ADC_JDATA_JVALID_Pos)               ///< Valid flag
-#define ADC_JDR0_JOVERRUN_Pos        (21)
-#define ADC_JDR0_JOVERRUN            (0x01U << ADC_JDATA_JOVERRUN_Pos)             ///< Overrun flag
-#define ADC_JDR0_JDATA_Pos           (0)
-#define ADC_JDR0_JDATA               (0xFFFFU << ADC_JSQR_JSQ0_Pos)                ///< Transfer data
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_JDR1 mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_JDR1_JVALID_Pos          (22)
-#define ADC_JDR1_JVALID              (0x01U << ADC_JDATA_JVALID_Pos)               ///< Valid flag
-#define ADC_JDR1_JOVERRUN_Pos        (21)
-#define ADC_JDR1_JOVERRUN            (0x01U << ADC_JDATA_JOVERRUN_Pos)             ///< Overrun flag
-#define ADC_JDR1_JDATA_Pos           (0)
-#define ADC_JDR1_JDATA               (0xFFFFU << ADC_JSQR_JSQ0_Pos)                ///< Transfer data
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_JDR2 mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_JDR2_JVALID_Pos          (22)
-#define ADC_JDR2_JVALID              (0x01U << ADC_JDATA_JVALID_Pos)               ///< Valid flag
-#define ADC_JDR2_JOVERRUN_Pos        (21)
-#define ADC_JDR2_JOVERRUN            (0x01U << ADC_JDATA_JOVERRUN_Pos)             ///< Overrun flag
-#define ADC_JDR2_JDATA_Pos           (0)
-#define ADC_JDR2_JDATA               (0xFFFFU << ADC_JSQR_JSQ0_Pos)                ///< Transfer data
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ADC_JDR3 mode enable Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ADC_JDR3_JVALID_Pos          (22)
-#define ADC_JDR3_JVALID              (0x01U << ADC_JDATA_JVALID_Pos)               ///< Valid flag
-#define ADC_JDR3_JOVERRUN_Pos        (21)
-#define ADC_JDR3_JOVERRUN            (0x01U << ADC_JDATA_JOVERRUN_Pos)             ///< Overrun flag
-#define ADC_JDR3_JDATA_Pos           (0)
-#define ADC_JDR3_JDATA               (0xFFFFU << ADC_JSQR_JSQ0_Pos)                ///< Transfer data
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h
deleted file mode 100644
index d4bd55188..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_bkp.h
+++ /dev/null
@@ -1,147 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_bkp.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_BKP_H
-#define __REG_BKP_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief BKP Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-
-
-#define BKP_BASE                        (APB1PERIPH_BASE + 0x2840)              ///< Base Address: 0x40002840
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief BKP Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-
-
-
-#define BKP_NUMBER  20
-
-typedef struct {
-    __IO u32 RTCCR;                                                             ///< RTC clock calibration register,                offset: 0x00
-    __IO u32 CR;                                                                ///< BKP control register,                          offset: 0x04
-    __IO u32 CSR;                                                               ///< BKP control/status register,                   offset: 0x08
-    __IO u32 RESERVED0;                                                         ///< Reserved,                                      offset: 0x0C
-    __IO u32 DR1;                                                               ///< BKP data register 1,                           offset: 0x10
-    __IO u32 DR2;                                                               ///< BKP data register 2,                           offset: 0x14
-    __IO u32 DR3;                                                               ///< BKP data register 3,                           offset: 0x18
-    __IO u32 DR4;                                                               ///< BKP data register 4,                           offset: 0x1C
-    __IO u32 DR5;                                                               ///< BKP data register 5,                           offset: 0x20
-    __IO u32 DR6;                                                               ///< BKP data register 6,                           offset: 0x24
-    __IO u32 DR7;                                                               ///< BKP data register 7,                           offset: 0x28
-    __IO u32 DR8;                                                               ///< BKP data register 8,                           offset: 0x2C
-    __IO u32 DR9;                                                               ///< BKP data register 9,                           offset: 0x30
-    __IO u32 DR10;                                                              ///< BKP data register 10                           offset: 0x34
-    __IO u32 DR11;                                                              ///< BKP data register 11,                          offset: 0x38
-    __IO u32 DR12;                                                              ///< BKP data register 12,                          offset: 0x3C
-    __IO u32 DR13;                                                              ///< BKP data register 13,                          offset: 0x40
-    __IO u32 DR14;                                                              ///< BKP data register 14,                          offset: 0x44
-    __IO u32 DR15;                                                              ///< BKP data register 15,                          offset: 0x48
-    __IO u32 DR16;                                                              ///< BKP data register 16,                          offset: 0x4C
-    __IO u32 DR17;                                                              ///< BKP data register 17,                          offset: 0x50
-    __IO u32 DR18;                                                              ///< BKP data register 18,                          offset: 0x54
-    __IO u32 DR19;                                                              ///< BKP data register 19,                          offset: 0x58
-    __IO u32 DR20;                                                              ///< BKP data register 20,                          offset: 0x5C
-} BKP_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief BKP type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define BKP                          ((BKP_TypeDef*) BKP_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief BKP_DRn Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define BKP_DR_DATA_Pos              (0)
-#define BKP_DR_DATA                  (0xFFFFU << BKP_DR_DATA)                ///< Backup data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief BKP_RTCCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define BKP_RTCCR_CAL_Pos           (0)
-#define BKP_RTCCR_CAL               (0x7FU << BKP_RTCCR_CAL_Pos)            ///< Calibration value
-#define BKP_RTCCR_CCO_Pos           (7)
-#define BKP_RTCCR_CCO               (0x01U << BKP_RTCCR_CCO_Pos)            ///< Calibration Clock Output
-#define BKP_RTCCR_ASOE_Pos          (8)
-#define BKP_RTCCR_ASOE              (0x01U << BKP_RTCCR_ASOE_Pos)           ///< Alarm or Second Output Enable
-#define BKP_RTCCR_ASOS_Pos          (9)
-#define BKP_RTCCR_ASOS              (0x01U << BKP_RTCCR_ASOS_Pos)           ///< Alarm or Second Output Selection
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief BKP_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define BKP_CR_TPE_Pos              (0)
-#define BKP_CR_TPE                  (0x01U << BKP_CR_TPE_Pos)               ///< TAMPER pin enable
-#define BKP_CR_TPAL_Pos             (1)
-#define BKP_CR_TPAL                 (0x01U << BKP_CR_TPAL_Pos)              ///< TAMPER pin active level
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief BKP_CSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define BKP_CSR_CTE_Pos             (0)
-#define BKP_CSR_CTE                 (0x01U << BKP_CSR_CTE_Pos)              ///< Clear Tamper event
-#define BKP_CSR_CTI_Pos             (1)
-#define BKP_CSR_CTI                 (0x01U << BKP_CSR_CTI_Pos)              ///< Clear Tamper Interrupt
-#define BKP_CSR_TPIE_Pos            (2)
-#define BKP_CSR_TPIE                (0x01U << BKP_CSR_TPIE_Pos)             ///< TAMPER Pin interrupt enable
-#define BKP_CSR_TEF_Pos             (8)
-#define BKP_CSR_TEF                 (0x01U << BKP_CSR_TEF_Pos)              ///< Tamper Event Flag
-#define BKP_CSR_TIF_Pos             (9)
-#define BKP_CSR_TIF                 (0x01U << BKP_CSR_TIF_Pos)              ///< Tamper Interrupt Flag
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h
deleted file mode 100644
index 5f66bb681..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_can.h
+++ /dev/null
@@ -1,532 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_can.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_CAN_H
-#define __REG_CAN_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN1_BASE                       (APB1PERIPH_BASE + 0x6400)              ///< Base Address: 0x40006400
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN basic
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 CR;                                                                ///< Control register,                              offset: 0x00
-    __IO u32 CMR;                                                               ///< Command register,                              offset: 0x04
-    __IO u32 SR;                                                                ///< <Status register,                              offset: 0x08
-    __IO u32 IR;                                                                ///< Interrupt register,                            offset: 0x0c
-    __IO u32 ACR;                                                               ///< Acceptance Code register,                      offset: 0x10
-    __IO u32 AMR;                                                               ///< Acceptance Mask register,                      offset: 0x14
-    __IO u32 BTR0;                                                              ///< Bus Timing register 0,                         offset: 0x18
-    __IO u32 BTR1;                                                              ///< Bus Timing register 1,                         offset: 0x1C
-    __IO u32 RESERVED0;
-    __IO u32 RESERVED1;
-    __IO u32 TXID0;                                                             ///< Send ID register 0,                            offset: 0x28
-    __IO u32 TXID1;                                                             ///< Send ID register 1,                            offset: 0x2c
-    __IO u32 TXDR0;                                                             ///< Send Data register 0,                          offset: 0x30
-    __IO u32 TXDR1;                                                             ///< Send Data register 1,                          offset: 0x34
-    __IO u32 TXDR2;                                                             ///< Send Data register 2,                          offset: 0x38
-    __IO u32 TXDR3;                                                             ///< Send Data register 3,                          offset: 0x3c
-    __IO u32 TXDR4;                                                             ///< Send Data register 4,                          offset: 0x40
-    __IO u32 TXDR5;                                                             ///< Send Data register 5,                          offset: 0x44
-    __IO u32 TXDR6;                                                             ///< Send Data register 6,                          offset: 0x48
-    __IO u32 TXDR7;                                                             ///< Send Data register 7,                          offset: 0x4c
-    __IO u32 RXID0;                                                             ///< Mode register,                                 offset: 0x50
-    __IO u32 RXID1;                                                             ///< Mode register,                                 offset: 0x54
-    __IO u32 RXDR0;                                                             ///< Mode register,                                 offset: 0x58
-    __IO u32 RXDR1;                                                             ///< Mode register,                                 offset: 0x5C
-    __IO u32 RXDR2;                                                             ///< Mode register,                                 offset: 0x60
-    __IO u32 RXDR3;                                                             ///< Mode register,                                 offset: 0x64
-    __IO u32 RXDR4;                                                             ///< Mode register,                                 offset: 0x68
-    __IO u32 RXDR5;                                                             ///< Mode register,                                 offset: 0x6c
-    __IO u32 RXDR6;                                                             ///< Mode register,                                 offset: 0x70
-    __IO u32 RXDR7;                                                             ///< Mode register,                                 offset: 0x74
-    __IO u32 RESERVED2;
-    __IO u32 CDR;                                                               ///< Clock Divider register,                        offset: 0x7c
-} CAN_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN Peli
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 MOD;                                                               ///< Mode register,                                 offset: 0x00
-    __IO u32 CMR;                                                               ///< Command register,                              offset: 0x04
-    __IO u32 SR;                                                                ///< Status register,                               offset: 0x08
-    __IO u32 IR;                                                                ///< Interrupt Enable register,                     offset: 0x0c
-    __IO u32 IER;                                                               ///< Mode register,                                 offset: 0x10
-    __IO u32 RESERVED0;
-    __IO u32 BTR0;                                                              ///< Bus Timing register 0,                         offset: 0x18
-    __IO u32 BTR1;                                                              ///< Bus Timing register 1,                         offset: 0x1C
-    __IO u32 RESERVED1;
-    __IO u32 RESERVED2;
-    __IO u32 RESERVED3;
-    __IO u32 ALC;                                                               ///< Arbitration Lost Capture register,             offset: 0x2c
-    __IO u32 ECC;                                                               ///< Error Code Capture register,                   offset: 0x30
-    __IO u32 EWLR;                                                              ///< Error Warning Limit register,                  offset: 0x34
-    __IO u32 RXERR;                                                             ///< RX Error Counter register,                     offset: 0x38
-    __IO u32 TXERR;                                                             ///< TX Error Counter register,                     offset: 0x3c
-    __IO u32 FF;                                                                ///< Frame Format register,                         offset: 0x40
-    __IO u32 ID0;                                                               ///< ID register 0,                                 offset: 0x44
-    __IO u32 ID1;                                                               ///< ID register 1,                                 offset: 0x48
-    __IO u32 DATA0;                                                             ///< Data register 0,                               offset: 0x4c
-    __IO u32 DATA1;                                                             ///< Data register 1,                               offset: 0x50
-    __IO u32 DATA2;                                                             ///< Data register 2,                               offset: 0x54
-    __IO u32 DATA3;                                                             ///< Data register 3,                               offset: 0x58
-    __IO u32 DATA4;                                                             ///< Data register 4,                               offset: 0x5c
-    __IO u32 DATA5;                                                             ///< Data register 5,                               offset: 0x60
-    __IO u32 DATA6;                                                             ///< Data register 6,                               offset: 0x64
-    __IO u32 DATA7;                                                             ///< Data register 7,                               offset: 0x68
-    __IO u32 DATA8;                                                             ///< Data register 8,                               offset: 0x6c
-    __IO u32 DATA9;                                                             ///< Data register 9,                               offset: 0x70
-    __IO u32 RMC;                                                               ///< RMC register,                                  offset: 0x74
-    __IO u32 RBSA;                                                              ///< RBSA register,                                 offset: 0x78
-    __IO u32 CDR;                                                               ///< Clock Divider register                         offset: 0x7c
-} CAN_Peli_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 ACR0;
-    __IO u32 ACR1;
-    __IO u32 ACR2;
-    __IO u32 ACR3;
-    __IO u32 AMR0;
-    __IO u32 AMR1;
-    __IO u32 AMR2;
-    __IO u32 AMR3;
-} CAN_FLT_GROUP;
-
-typedef struct {
-    CAN_FLT_GROUP GROUP0;                                                        //Address offset: 0x40
-    u32      RESERVED[8];                                                        //Address offset: 0x60
-    __IO u32 AFM0;                                                               //Address offset: 0x80
-    __IO u32 AFM1;                                                               //Address offset: 0x84
-    __IO u32 AFM2;                                                               //Address offset: 0x88
-    __IO u32 FGA0;                                                               //Address offset: 0x8C
-    __IO u32 FGA1;                                                               //Address offset: 0x90
-    __IO u32 FGA2;                                                               //Address offset: 0x94
-    CAN_FLT_GROUP GROUP1;                                                        //Address offset: 0x98
-    CAN_FLT_GROUP GROUP2;                                                        //Address offset: 0xB8
-    CAN_FLT_GROUP GROUP3;                                                        //Address offset: 0xD8
-    CAN_FLT_GROUP GROUP4;                                                        //Address offset: 0xF8
-    CAN_FLT_GROUP GROUP5;                                                        //Address offset: 0x118
-    CAN_FLT_GROUP GROUP6;                                                        //Address offset: 0x138
-    CAN_FLT_GROUP GROUP7;                                                        //Address offset: 0x158
-    CAN_FLT_GROUP GROUP8;                                                        //Address offset: 0x178
-    CAN_FLT_GROUP GROUP9;                                                        //Address offset: 0x198
-    CAN_FLT_GROUP GROUP10;                                                       //Address offset: 0x1B8
-    CAN_FLT_GROUP GROUP11;                                                       //Address offset: 0x1D8
-    CAN_FLT_GROUP GROUP12;                                                       //Address offset: 0x1F8
-    CAN_FLT_GROUP GROUP13;                                                       //Address offset: 0x218
-    CAN_FLT_GROUP GROUP14;                                                       //Address offset: 0x238
-    CAN_FLT_GROUP GROUP15;                                                       //Address offset: 0x258
-    CAN_FLT_GROUP GROUP16;                                                       //Address offset: 0x278
-    CAN_FLT_GROUP GROUP17;                                                       //Address offset: 0x298
-    CAN_FLT_GROUP GROUP18;                                                       //Address offset: 0x2B8
-    CAN_FLT_GROUP GROUP19;                                                       //Address offset: 0x2D8
-} CAN_Peli_FLT_TypeDef;
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN1                        ((CAN_TypeDef*) CAN1_BASE)
-#define CAN1_PELI                   ((CAN_Peli_TypeDef*) CAN1_BASE)
-#define CAN_Peli_FLT                ((CAN_Peli_FLT_TypeDef*)(CAN1_BASE + 0x40))
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN basic
-////////////////////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_CR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_CR_RR_Pos               (0)
-#define CAN_CR_RR                   (0x01U << CAN_CR_RR_Pos)                ///< CAN reset request
-#define CAN_CR_RIE_Pos              (1)
-#define CAN_CR_RIE                  (0x01U << CAN_CR_RIE_Pos)               ///< CAN receive interrupt enable
-#define CAN_CR_TIE_Pos              (2)
-#define CAN_CR_TIE                  (0x01U << CAN_CR_TIE_Pos)               ///< CAN transmit interrupt enable
-#define CAN_CR_EIE_Pos              (3)
-#define CAN_CR_EIE                  (0x01U << CAN_CR_EIE_Pos)               ///< CAN error interrupt enable
-#define CAN_CR_OIE_Pos              (4)
-#define CAN_CR_OIE                  (0x01U << CAN_CR_OIE_Pos)               ///< CAN overflow interrupt enable
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_CMR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_CMR_TR_Pos              (0)
-#define CAN_CMR_TR                  (0x01U << CAN_CMR_TR_Pos )              ///< CAN transmission request
-#define CAN_CMR_AT_Pos              (1)
-#define CAN_CMR_AT                  (0x01U << CAN_CMR_AT_Pos )              ///< CAN abort transmission
-#define CAN_CMR_RRB_Pos             (2)
-#define CAN_CMR_RRB                 (0x01U << CAN_CMR_RRB_Pos)              ///< CAN release receive buffer
-#define CAN_CMR_CDO_Pos             (3)
-#define CAN_CMR_CDO                 (0x01U << CAN_CMR_CDO_Pos)              ///< CAN clear data overrun
-#define CAN_CMR_GTS_Pos             (4)
-#define CAN_CMR_GTS                 (0x01U << CAN_CMR_GTS_Pos)              ///< CAN go to sleep
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_SR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_SR_RBS_Pos              (0)
-#define CAN_SR_RBS                  (0x01U << CAN_SR_RBS_Pos)               ///< CAN receive buffer status
-#define CAN_SR_DOS_Pos              (1)
-#define CAN_SR_DOS                  (0x01U << CAN_SR_DOS_Pos)               ///< CAN data overrun status
-#define CAN_SR_TBS_Pos              (2)
-#define CAN_SR_TBS                  (0x01U << CAN_SR_TBS_Pos)               ///< CAN transmit buffer status
-#define CAN_SR_TCS_Pos              (3)
-#define CAN_SR_TCS                  (0x01U << CAN_SR_TCS_Pos)               ///< CAN transmission complete status
-#define CAN_SR_RS_Pos               (4)
-#define CAN_SR_RS                   (0x01U << CAN_SR_RS_Pos)                ///< CAN receive status
-#define CAN_SR_TS_Pos               (5)
-#define CAN_SR_TS                   (0x01U << CAN_SR_TS_Pos)                ///< CAN transmit status
-#define CAN_SR_ES_Pos               (6)
-#define CAN_SR_ES                   (0x01U << CAN_SR_ES_Pos)                ///< CAN error status
-#define CAN_SR_BS_Pos               (7)
-#define CAN_SR_BS                   (0x01U << CAN_SR_BS_Pos)                ///< CAN bus status
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_ACR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_ACR_AC                  (0xFFU << 0)                            ///< CAN acceptance code
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_AMR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_AMR_AM_Pos              (0)
-#define CAN_AMR_AM                  (0xFFU << CAN_AMR_AM_Pos)               ///< CAN acceptance mask
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_BTR0 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_BTR0_BRP_Pos            (0)
-#define CAN_BTR0_BRP                (0x003FU << CAN_BTR0_BRP_Pos)           ///< CAN baud rate prescaler
-#define CAN_BTR0_SJW_Pos            (6)
-#define CAN_BTR0_SJW                (0x03U << CAN_BTR0_SJW_Pos)             ///< CAN synchronization jump width
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_BTR1 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_BTR1_TESG1_Pos          (0)
-#define CAN_BTR1_TESG1              (0x000FU << CAN_BTR1_TESG1_Pos)         ///< CAN Time segment 1
-#define CAN_BTR1_TESG2_Pos          (4)
-#define CAN_BTR1_TESG2              (0x07U << CAN_BTR1_TESG2_Pos)           ///< CAN Time segment 2
-#define CAN_BTR1_SAM_Pos            (7)
-#define CAN_BTR1_SAM                (0x01U << CAN_BTR1_SAM_Pos)             ///< CAN sampling
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_TXID0 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_TXID0_ID_3_Pos          (0)
-#define CAN_TXID0_ID_3              (0x01U << CAN_TXID0_ID_3_Pos)           ///< CAN identifier byte 3
-#define CAN_TXID0_ID_4_Pos          (1)
-#define CAN_TXID0_ID_4              (0x01U << CAN_TXID0_ID_4_Pos)           ///< CAN identifier byte 4
-#define CAN_TXID0_ID_5_Pos          (2)
-#define CAN_TXID0_ID_5              (0x01U << CAN_TXID0_ID_5_Pos)           ///< CAN identifier byte 5
-#define CAN_TXID0_ID_6_Pos          (3)
-#define CAN_TXID0_ID_6              (0x01U << CAN_TXID0_ID_6_Pos)           ///< CAN identifier byte 6
-#define CAN_TXID0_ID_7_Pos          (4)
-#define CAN_TXID0_ID_7              (0x01U << CAN_TXID0_ID_7_Pos)           ///< CAN identifier byte 7
-#define CAN_TXID0_ID_8_Pos          (5)
-#define CAN_TXID0_ID_8              (0x01U << CAN_TXID0_ID_8_Pos)           ///< CAN identifier byte 8
-#define CAN_TXID0_ID_9_Pos          (6)
-#define CAN_TXID0_ID_9              (0x01U << CAN_TXID0_ID_9_Pos)           ///< CAN identifier byte 9
-#define CAN_TXID0_ID_10_Pos         (7)
-#define CAN_TXID0_ID_10             (0x01U << CAN_TXID0_ID_10_Pos)          ///< CAN identifier byte 10
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_TXID1 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_TXID1_DLC0_Pos          (0)
-#define CAN_TXID1_DLC0              (0x01U << CAN_TXID1_DLC0_Pos)           ///< CAN data length code 0 ~ 8
-#define CAN_TXID1_DLC1_Pos          (1)
-#define CAN_TXID1_DLC1              (0x01U << CAN_TXID1_DLC1_Pos)           ///< CAN data length code 0 ~ 8
-#define CAN_TXID1_DLC2_Pos          (2)
-#define CAN_TXID1_DLC2              (0x01U << CAN_TXID1_DLC2_Pos)           ///< CAN data length code 0 ~ 8
-#define CAN_TXID1_DLC3_Pos          (3)
-#define CAN_TXID1_DLC3              (0x01U << CAN_TXID1_DLC3_Pos)           ///< CAN data length code 0 ~ 8
-#define CAN_TXID1_RTR_Pos           (4)
-#define CAN_TXID1_RTR               (0x01U << CAN_TXID1_RTR_Pos )           ///< CAN remote transmission request
-#define CAN_TXID1_ID_0_Pos          (5)
-#define CAN_TXID1_ID_0              (0x01U << CAN_TXID1_ID_0_Pos)           ///< CAN identifier byte 0
-#define CAN_TXID1_ID_1_Pos          (6)
-#define CAN_TXID1_ID_1              (0x01U << CAN_TXID1_ID_1_Pos)           ///< CAN identifier byte 1
-#define CAN_TXID1_ID_2_Pos          (7)
-#define CAN_TXID1_ID_2              (0x01U << CAN_TXID1_ID_2_Pos)           ///< CAN identifier byte 2
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_TXDRn register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_TXDRn                   (0x00FFU)                               // (n = 0..7)        ///< CAN send data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_CDR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_CDR_MODE_Pos            (7)
-#define CAN_CDR_MODE                (0x01U << CAN_CDR_MODE_Pos)             ///< CAN mode
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN Peli
-////////////////////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_MOD register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_MOD_RM_Pos              (0)
-#define CAN_MOD_RM                  (0x01U << CAN_MOD_RM_Pos)               ///< CAN reset mode
-#define CAN_MOD_LOM_Pos             (1)
-#define CAN_MOD_LOM                 (0x01U << CAN_MOD_LOM_Pos)              ///< CAN listen only mode
-#define CAN_MOD_STM_Pos             (2)
-#define CAN_MOD_STM                 (0x01U << CAN_MOD_STM_Pos)              ///< CAN self test mode
-#define CAN_MOD_AFM_Pos             (3)
-#define CAN_MOD_AFM                 (0x01U << CAN_MOD_AFM_Pos)              ///< CAN acceptance filter mode
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_CMR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_CMR_TR_Pos              (0)
-#define CAN_CMR_TR                  (0x01U << CAN_CMR_TR_Pos )              ///< CAN transmission request
-#define CAN_CMR_AT_Pos              (1)
-#define CAN_CMR_AT                  (0x01U << CAN_CMR_AT_Pos )              ///< CAN abort transmission
-#define CAN_CMR_RRB_Pos             (2)
-#define CAN_CMR_RRB                 (0x01U << CAN_CMR_RRB_Pos)              ///< CAN release receive buffer
-#define CAN_CMR_CDO_Pos             (3)
-#define CAN_CMR_CDO                 (0x01U << CAN_CMR_CDO_Pos)              ///< CAN clear data overrun
-#define CAN_CMR_SRR_Pos             (4)
-#define CAN_CMR_SRR                 (0x01U << CAN_CMR_SRR_Pos)              ///< CAN self reset request
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_SR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_SR_RBS_Pos              (0)
-#define CAN_SR_RBS                  (0x01U << CAN_SR_RBS_Pos)               ///< CAN receive buffer status
-#define CAN_SR_DOS_Pos              (1)
-#define CAN_SR_DOS                  (0x01U << CAN_SR_DOS_Pos)               ///< CAN data overrun status
-#define CAN_SR_TBS_Pos              (2)
-#define CAN_SR_TBS                  (0x01U << CAN_SR_TBS_Pos)               ///< CAN transmit buffer status
-#define CAN_SR_TCS_Pos              (3)
-#define CAN_SR_TCS                  (0x01U << CAN_SR_TCS_Pos)               ///< CAN transmission complete status
-#define CAN_SR_RS_Pos               (4)
-#define CAN_SR_RS                   (0x01U << CAN_SR_RS_Pos)                ///< CAN receive status
-#define CAN_SR_TS_Pos               (5)
-#define CAN_SR_TS                   (0x01U << CAN_SR_TS_Pos)                ///< CAN transmit status
-#define CAN_SR_ES_Pos               (6)
-#define CAN_SR_ES                   (0x01U << CAN_SR_ES_Pos)                ///< CAN error status
-#define CAN_SR_BS_Pos               (7)
-#define CAN_SR_BS                   (0x01U << CAN_SR_BS_Pos)                ///< CAN bus status
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_IR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_IR_RI_Pos               (0)
-#define CAN_IR_RI                   (0x01U << CAN_IR_RI_Pos)                ///< CAN receive interrupt
-#define CAN_IR_TI_Pos               (1)
-#define CAN_IR_TI                   (0x01U << CAN_IR_TI_Pos)                ///< CAN transmit interrupt
-#define CAN_IR_EI_Pos               (2)
-#define CAN_IR_EI                   (0x01U << CAN_IR_EI_Pos)                ///< CAN error interrupt
-#define CAN_IR_DOI_Pos              (3)
-#define CAN_IR_DOI                  (0x01U << CAN_IR_DOI_Pos)               ///< CAN data overrun interrupt
-#define CAN_IR_EPI_Pos              (5)
-#define CAN_IR_EPI                  (0x01U << CAN_IR_EPI_Pos)               ///< CAN error passive interrupt
-#define CAN_IR_ALI_Pos              (6)
-#define CAN_IR_ALI                  (0x01U << CAN_IR_ALI_Pos)               ///< CAN arbitration lost interrupt
-#define CAN_IR_BEI_Pos              (7)
-#define CAN_IR_BEI                  (0x01U << CAN_IR_BEI_Pos)               ///< CAN bus error interrupt
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_IR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_IER_RIE_Pos             (0)
-#define CAN_IER_RIE                 (0x01U << CAN_IER_RIE_Pos)              ///< CAN receive interrupt enable
-#define CAN_IER_TIE_Pos             (1)
-#define CAN_IER_TIE                 (0x01U << CAN_IER_TIE_Pos)              ///< CAN transmit interrupt enable
-#define CAN_IER_EIE_Pos             (2)
-#define CAN_IER_EIE                 (0x01U << CAN_IER_EIE_Pos)              ///< CAN error interrupt enable
-#define CAN_IER_DOIE_Pos            (3)
-#define CAN_IER_DOIE                (0x01U << CAN_IER_DOIE_Pos)             ///< CAN data overrun interrupt enable
-#define CAN_IER_EPIE_Pos            (5)
-#define CAN_IER_EPIE                (0x01U << CAN_IER_EPI_Pos)              ///< CAN error passive interrupt enable
-#define CAN_IER_ALIE_Pos            (6)
-#define CAN_IER_ALIE                (0x01U << CAN_IER_ALIE_Pos)             ///< CAN arbitration lost interrupt enable
-#define CAN_IER_BEIE_Pos            (7)
-#define CAN_IER_BEIE                (0x01U << CAN_IER_BEIE_Pos)             ///< CAN bus error interrupt enable
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_ACRn register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_ACRn_AC_Pos             (0)
-#define CAN_ACRn_AC                 (0xFFU << CAN_ACRn_AC_Pos)              ///< CAN acceptance code
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_AMRn register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_AMRn_AM_Pos             (0)
-#define CAN_AMRn_AM                 (0xFFU << CAN_AMRn_AM_Pos)              ///< CAN acceptance mask
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_BTR0 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_BTR0_BRP_Pos            (0)
-#define CAN_BTR0_BRP                (0x003FU << CAN_BTR0_BRP_Pos)           ///< CAN baud rate prescaler
-#define CAN_BTR0_SJW_Pos            (6)
-#define CAN_BTR0_SJW                (0x03U << CAN_BTR0_SJW_Pos)             ///< CAN synchronization jump width
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_ALC register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_ALC_BITNO_Pos           (0)
-#define CAN_ALC_BITNO               (0x001FU << CAN_ALC_BITNO_Pos)          ///< CAN bit number
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_ECC register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_ECC_SEG_Pos             (0)
-#define CAN_ECC_SEG                 (0x001FU <<CAN_ECC_SEG_Pos)             ///< CAN error code capture
-#define CAN_ECC_DIR_Pos             (5)
-#define CAN_ECC_DIR                 (0x01U << CAN_ECC_DIR_Pos)              ///< CAN direction
-#define CAN_ECC_ERRC_Pos            (6)
-#define CAN_ECC_ERRC                (0x03U << CAN_ECC_ERRC_Pos)             ///< CAN error code
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_EWLR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_EWLR_EWL_Pos            (0)
-#define CAN_EWLR_EWL                (0x00FFU << CAN_EWLR_EWL_Pos)           ///< CAN programmable error warning limit
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_RXERR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_RXERR_RXERR_Pos         (0)
-#define CAN_RXERR_RXERR             (0x00FFU << CAN_RXERR_RXERR_Pos)        ///< CAN RX error counter register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_TXERR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_TXERR_TXERR_Pos         (0)
-#define CAN_TXERR_TXERR             (0x00FFU << CAN_TXERR_TXERR_Pos)        ///< CAN TX error counter register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_FF register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_FF_DLC_0_Pos            (0)
-#define CAN_FF_DLC_0                (0x01U << CAN_FF_DLC_0_Pos)             ///< CAN data length code bit
-#define CAN_FF_DLC_1_Pos            (1)
-#define CAN_FF_DLC_1                (0x01U << CAN_FF_DLC_1_Pos)             ///< CAN data length code bit
-#define CAN_FF_DLC_2_Pos            (2)
-#define CAN_FF_DLC_2                (0x01U << CAN_FF_DLC_2_Pos)             ///< CAN data length code bit
-#define CAN_FF_DLC_3_Pos            (3)
-#define CAN_FF_DLC_3                (0x01U << CAN_FF_DLC_3_Pos)             ///< CAN data length code bit
-#define CAN_FF_RTR_Pos              (6)
-#define CAN_FF_RTR                  (0x01U << CAN_FF_RTR_Pos)               ///< CAN remote transmission request
-#define CAN_FF_FF_Pos               (7)
-#define CAN_FF_FF                   (0x01U << CAN_FF_FF_Pos)                ///< CAN frame format
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_TXID0 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_TXID0_ID_21_Pos         (0)
-#define CAN_TXID0_ID_21             (0x01U << CAN_TXID0_ID_21_Pos)          ///< CAN identifier bit 21
-#define CAN_TXID0_ID_22_Pos         (1)
-#define CAN_TXID0_ID_22             (0x01U << CAN_TXID0_ID_22_Pos)          ///< CAN identifier bit 22
-#define CAN_TXID0_ID_23_Pos         (2)
-#define CAN_TXID0_ID_23             (0x01U << CAN_TXID0_ID_23_Pos)          ///< CAN identifier bit 23
-#define CAN_TXID0_ID_24_Pos         (3)
-#define CAN_TXID0_ID_24             (0x01U << CAN_TXID0_ID_24_Pos)          ///< CAN identifier bit 24
-#define CAN_TXID0_ID_25_Pos         (4)
-#define CAN_TXID0_ID_25             (0x01U << CAN_TXID0_ID_25_Pos)          ///< CAN identifier bit 25
-#define CAN_TXID0_ID_26_Pos         (5)
-#define CAN_TXID0_ID_26             (0x01U << CAN_TXID0_ID_26_Pos)          ///< CAN identifier bit 26
-#define CAN_TXID0_ID_27_Pos         (6)
-#define CAN_TXID0_ID_27             (0x01U << CAN_TXID0_ID_27_Pos)          ///< CAN identifier bit 27
-#define CAN_TXID0_ID_28_Pos         (7)
-#define CAN_TXID0_ID_28             (0x01U << CAN_TXID0_ID_28_Pos)          ///< CAN identifier bit 28
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_TXID1 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_TXID1_ID_13_Pos         (0)
-#define CAN_TXID1_ID_13             (0x01U << CAN_TXID1_ID_13_Pos)          ///< CAN identifier bit 13
-#define CAN_TXID1_ID_14_Pos         (1)
-#define CAN_TXID1_ID_14             (0x01U << CAN_TXID1_ID_14_Pos)          ///< CAN identifier bit 14
-#define CAN_TXID1_ID_15_Pos         (2)
-#define CAN_TXID1_ID_15             (0x01U << CAN_TXID1_ID_15_Pos)          ///< CAN identifier bit 15
-#define CAN_TXID1_ID_16_Pos         (3)
-#define CAN_TXID1_ID_16             (0x01U << CAN_TXID1_ID_16_Pos)          ///< CAN identifier bit 16
-#define CAN_TXID1_ID_17_Pos         (4)
-#define CAN_TXID1_ID_17             (0x01U << CAN_TXID1_ID_17_Pos)          ///< CAN identifier bit 17
-#define CAN_TXID1_ID_18_Pos         (5)
-#define CAN_TXID1_ID_18             (0x01U << CAN_TXID1_ID_18_Pos)          ///< CAN identifier bit 18
-#define CAN_TXID1_ID_19_Pos         (6)
-#define CAN_TXID1_ID_19             (0x01U << CAN_TXID1_ID_19_Pos)          ///< CAN identifier bit 19
-#define CAN_TXID1_ID_20_Pos         (7)
-#define CAN_TXID1_ID_20             (0x01U << CAN_TXID1_ID_20_Pos)          ///< CAN identifier bit 20
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_TXDATAn register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_TXDATAn_Pos             (0)
-#define CAN_TXDATAn                 (0x00FFU << CAN_TXDATAn_Pos)            ///< CAN transmit data n
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CAN_CDR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define CAN_CDR_MODE_Pos            (7)
-#define CAN_CDR_MODE                (0x01U << CAN_CDR_MODE_Pos)             ///< CAN mode
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h
deleted file mode 100644
index 6a955cc61..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_common.h
+++ /dev/null
@@ -1,643 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_common.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_COMMON_H
-#define __REG_COMMON_H
-
-// Files includes
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-#ifndef HSE_STARTUP_TIMEOUT
-#define HSE_STARTUP_TIMEOUT     (0x0500U)                                       ///< Time out for HSE start up.
-#endif
-#ifdef  CUSTOM_HSE_VAL
-#ifndef HSE_VALUE
-#define HSE_VALUE               (12000000U)                                     ///< Value of the External oscillator in Hz.
-#endif
-#else
-#ifndef HSE_VALUE
-#define HSE_VALUE               (8000000U)                                      ///< Value of the External oscillator in Hz.
-#endif
-#endif
-
-
-
-#define HSI_VALUE_PLL_ON        (8000000U)                                      ///< Value of the Internal oscillator in Hz.
-#define HSI_DIV6                (8000000U)                                      ///< Value of the Internal oscillator in Hz.
-// Value of the Internal oscillator in Hz.
-
-
-#define LSI_VALUE               (40000U)                                        ///< Value of the Internal oscillator in Hz.
-
-
-
-
-
-#ifndef HSI_VALUE
-
-#define HSI_VALUE               (8000000U)                                      ///< Value of the Internal oscillator in Hz.
-
-#endif
-
-
-
-
-
-
-
-
-#define __MPU_PRESENT               (0)                                     ///< Cortex-M3 does not provide a MPU present or not
-#ifndef __NVIC_PRIO_BITS
-#define __NVIC_PRIO_BITS            (4)                                     ///< Cortex-M3 uses 4 Bits for the Priority Levels
-//#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-#endif
-
-#define __Vendor_SysTickConfig      (0)                                     ///< Set to 1 if different SysTick Config is used
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  MM32 MCU Interrupt Handle
-////////////////////////////////////////////////////////////////////////////////
-typedef enum IRQn {
-    NonMaskableInt_IRQn             = -14,                                  ///< 2 Non Maskable Interrupt
-    MemoryManagement_IRQn           = -12,                                  ///< 4 Cortex-M3 Memory Management Interrupt
-    BusFault_IRQn                   = -11,                                  ///< 5 Cortex-M3 Bus Fault Interrupt
-    UsageFault_IRQn                 = -10,                                  ///< 6 Cortex-M3 Usage Fault Interrupt
-    SVCall_IRQn                     = -5,                                   ///< 11 Cortex-M3 SV Call Interrupt
-    DebugMonitor_IRQn               = -4,                                   ///< 12 Cortex-M3 Debug Monitor Interrupt
-    PendSV_IRQn                     = -2,                                   ///< 14 Cortex-M3 Pend SV Interrupt
-    SysTick_IRQn                    = -1,                                   ///< 15 Cortex-M3 System Tick Interrupt
-
-    WWDG_IWDG_IRQn                      = 0,                                     ///< Watchdog interrupt
-    WWDG_IRQn                           = 0,                                     ///< Watchdog interrupt
-    PVD_IRQn                            = 1,                                     ///< (PVD) Interrupt
-    TAMPER_IRQn                         = 2,                                     ///< Intrusion detection interrupted
-    RTC_IRQn                            = 3,                                     ///< Real-time clock (RTC) global interrupt
-    FLASH_IRQn                          = 4,                                     ///< Flash global interrupt
-    RCC_CRS_IRQn                        = 5,                                     ///< RCC and CRS global interrupt
-    EXTI0_IRQn                          = 6,                                     ///< EXTI line 0 interrupt
-    EXTI1_IRQn                          = 7,                                     ///< EXTI line 1 interrupt
-    EXTI2_IRQn                          = 8,                                     ///< EXTI line 2 interrupt
-    EXTI3_IRQn                          = 9,                                     ///< EXTI line 3 interrupted
-    EXTI4_IRQn                          = 10,                                    ///< EXTI line 4 interrupt
-    DMA1_Channel1_IRQn                  = 11,                                    ///< DMA1 channel 1 global interrupt
-    DMA1_Channel2_IRQn                  = 12,                                    ///< DMA1 channel 2 global interrupt
-    DMA1_Channel3_IRQn                  = 13,                                    ///< DMA1 channel 3 global interrupt
-    DMA1_Channel4_IRQn                  = 14,                                    ///< DMA1 channel 4 global interrupt
-    DMA1_Channel5_IRQn                  = 15,                                    ///< DMA1 channel 5 global interrupt
-    DMA1_Channel6_IRQn                  = 16,                                    ///< DMA1 channel 6 global interrupt
-    DMA1_Channel7_IRQn                  = 17,                                    ///< DMA1 channel 7 global interrupt
-    ADC1_IRQn                           = 18,                                    ///< ADC1 global interrupt
-    ADC1_2_IRQn                         = 18,                                    ///< ADC1&ADC2 global interrupt
-    ADC2_IRQn                           = 18,                                    ///< ADC2 global interrupt
-    FlashCache_IRQn                     = 19,                                    ///< FlashCache outage
-    CAN1_RX_IRQn                        = 21,                                    ///< CAN1 receive interrupt
-    CAN_IRQn                            = 21,                                    ///< CAN interrupt
-    EXTI9_5_IRQn                        = 23,                                    ///< EXTI line [9: 5] interrupted
-    TIM1_BRK_IRQn                       = 24,                                    ///< TIM1 disconnect interrupt
-    TIM1_UP_IRQn                        = 25,                                    ///< TIM1 update interrupt
-    IM1_TRG_COM_IRQn                    = 26,                                    ///< TIM1 trigger and communication interrupt
-    TIM1_CC_IRQn                        = 27,                                    ///< TIM1 capture compare interrupt
-    TIM2_IRQn                           = 28,                                    ///< TIM2 global interrupt
-    TIM3_IRQn                           = 29,                                    ///< TIM3 global interrupt
-    TIM4_IRQn                           = 30,                                    ///< TIM4 global interrupt
-    I2C1_IRQn                           = 31,                                    ///< I2C1 global interrupt
-    I2C2_IRQn                           = 33,                                    ///< I2C2 global interrupt
-    SPI1_IRQn                           = 35,                                    ///< SPI1 global interrupt
-    SPI2_IRQn                           = 36,                                    ///< SPI2 global interrupt
-    UART1_IRQn                          = 37,                                    ///< UART1 global interrupt
-    UART2_IRQn                          = 38,                                    ///< UART2 global interrupt
-    UART3_IRQn                          = 39,                                    ///< UART3 global interrupt
-    EXTI15_10_IRQn                      = 40,                                    ///< EXTI line [15: 10] interrupted
-    RTCAlarm_IRQn                       = 41,                                    ///< RTC alarm connected to EXTI interrupted
-    USB_WKUP_IRQn                       = 42,                                    ///< Wake-up interrupt from USB connected to EXTI
-    TIM8_BRK_IRQn                       = 43,                                    ///< TIM8 brake interruption
-    TIM8_UP_IRQn                        = 44,                                    ///< TIM8 update interrupt
-    TIM8_TRG_COM_IRQn                   = 45,                                    ///< TIM8 trigger, communication interrupt
-    TIM8_CC_IRQn                        = 46,                                    ///< TIM8 capture compare interrupt
-    ADC3_IRQn                           = 47,                                    ///< ADC3 global interrupt
-    SDIO_IRQn                           = 49,                                    ///< SDIO global interrupt
-    TIM5_IRQn                           = 50,                                    ///< TIM5 global interrupt
-    SPI3_IRQn                           = 51,                                    ///< SPI3 global interrupt
-    UART4_IRQn                          = 52,                                    ///< UART4 global interrupt
-    UART5_IRQn                          = 53,                                    ///< UART5 global interrupt
-    TIM6_IRQn                           = 54,                                    ///< TIM6 global interrupt
-    TIM7_IRQn                           = 55,                                    ///< TIM7 global interrupt
-    DMA2_Channel1_IRQn                  = 56,                                    ///< DMA2 channel 1 global interrupt
-    DMA2_Channel2_IRQn                  = 57,                                    ///< DMA2 channel 2 global interrupt
-    DMA2_Channel3_IRQn                  = 58,                                    ///< DMA2 channel 3 global interrupt
-    DMA2_Channel4_IRQn                  = 59,                                    ///< DMA2 channel 4 global interrupt
-    DMA2_Channel5_IRQn                  = 60,                                    ///< DMA2 channel 5 global interrupt
-    ETHERNET_MAC_IRQn                   = 61,                                    ///< ETHERNET global interrupt
-    COMP1_2_IRQn                        = 64,                                  ///< Comparator 1/2 interrupt connected to EXTI
-    USB_FS_IRQn                         = 67,                                  ///< USB FS global interrupt
-    UART6_IRQn                          = 71,                                  ///< UART6 global interrupt
-    UART7_IRQn                          = 82,                                  ///< UART7 global interrupt
-    UART8_IRQn                          = 83,                                  ///< UART8 global interrupt
-} IRQn_Type;
-
-
-
-
-#include <core_cm3.h>
-
-
-
-#define PERIPH_BASE                     (0x40000000U)                           ///< Peripheral base address in the alias region
-
-#define EEPROM_BASE                     (0x08100000U)                           ///< EEPROM base address in the alias region
-
-
-#define SRAM_BITBAND_BASE               (0x22000000U)                           ///< Peripheral base address in the bit-band region
-#define PERIPH_BITBAND_BASE             (0x42000000U)                           ///< SRAM base address in the bit-band region
-
-#define APB1PERIPH_BASE                 (PERIPH_BASE + 0x00000000)
-#define APB2PERIPH_BASE                 (PERIPH_BASE + 0x00010000)
-#define AHBPERIPH_BASE                  (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE                 (PERIPH_BASE + 0x10000000)
-#define AHB3PERIPH_BASE                 (PERIPH_BASE + 0x20000000)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UID type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UID_BASE                        (0x1FFFF7E0U)                           ///< Unique device ID register base address
-
-
-
-
-
-
-
-
-///////////////////////////////////////////////////////////////////////////////
-/// @brief Nested Vectored Interrupt Controller
-///////////////////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_ISER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_ISER_SETENA                (0xFFFFFFFFU)                           ///< Interrupt set enable bits
-#define NVIC_ISER_SETENA_0              (0x00000001U)                           ///< bit 0
-#define NVIC_ISER_SETENA_1              (0x00000002U)                           ///< bit 1
-#define NVIC_ISER_SETENA_2              (0x00000004U)                           ///< bit 2
-#define NVIC_ISER_SETENA_3              (0x00000008U)                           ///< bit 3
-#define NVIC_ISER_SETENA_4              (0x00000010U)                           ///< bit 4
-#define NVIC_ISER_SETENA_5              (0x00000020U)                           ///< bit 5
-#define NVIC_ISER_SETENA_6              (0x00000040U)                           ///< bit 6
-#define NVIC_ISER_SETENA_7              (0x00000080U)                           ///< bit 7
-#define NVIC_ISER_SETENA_8              (0x00000100U)                           ///< bit 8
-#define NVIC_ISER_SETENA_9              (0x00000200U)                           ///< bit 9
-#define NVIC_ISER_SETENA_10             (0x00000400U)                           ///< bit 10
-#define NVIC_ISER_SETENA_11             (0x00000800U)                           ///< bit 11
-#define NVIC_ISER_SETENA_12             (0x00001000U)                           ///< bit 12
-#define NVIC_ISER_SETENA_13             (0x00002000U)                           ///< bit 13
-#define NVIC_ISER_SETENA_14             (0x00004000U)                           ///< bit 14
-#define NVIC_ISER_SETENA_15             (0x00008000U)                           ///< bit 15
-#define NVIC_ISER_SETENA_16             (0x00010000U)                           ///< bit 16
-#define NVIC_ISER_SETENA_17             (0x00020000U)                           ///< bit 17
-#define NVIC_ISER_SETENA_18             (0x00040000U)                           ///< bit 18
-#define NVIC_ISER_SETENA_19             (0x00080000U)                           ///< bit 19
-#define NVIC_ISER_SETENA_20             (0x00100000U)                           ///< bit 20
-#define NVIC_ISER_SETENA_21             (0x00200000U)                           ///< bit 21
-#define NVIC_ISER_SETENA_22             (0x00400000U)                           ///< bit 22
-#define NVIC_ISER_SETENA_23             (0x00800000U)                           ///< bit 23
-#define NVIC_ISER_SETENA_24             (0x01000000U)                           ///< bit 24
-#define NVIC_ISER_SETENA_25             (0x02000000U)                           ///< bit 25
-#define NVIC_ISER_SETENA_26             (0x04000000U)                           ///< bit 26
-#define NVIC_ISER_SETENA_27             (0x08000000U)                           ///< bit 27
-#define NVIC_ISER_SETENA_28             (0x10000000U)                           ///< bit 28
-#define NVIC_ISER_SETENA_29             (0x20000000U)                           ///< bit 29
-#define NVIC_ISER_SETENA_30             (0x40000000U)                           ///< bit 30
-#define NVIC_ISER_SETENA_31             (0x80000000U)                           ///< bit 31
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_ICER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_ICER_CLRENA                (0xFFFFFFFFU)                           ///< Interrupt clear-enable bits
-#define NVIC_ICER_CLRENA_0              (0x00000001U)                           ///< bit 0
-#define NVIC_ICER_CLRENA_1              (0x00000002U)                           ///< bit 1
-#define NVIC_ICER_CLRENA_2              (0x00000004U)                           ///< bit 2
-#define NVIC_ICER_CLRENA_3              (0x00000008U)                           ///< bit 3
-#define NVIC_ICER_CLRENA_4              (0x00000010U)                           ///< bit 4
-#define NVIC_ICER_CLRENA_5              (0x00000020U)                           ///< bit 5
-#define NVIC_ICER_CLRENA_6              (0x00000040U)                           ///< bit 6
-#define NVIC_ICER_CLRENA_7              (0x00000080U)                           ///< bit 7
-#define NVIC_ICER_CLRENA_8              (0x00000100U)                           ///< bit 8
-#define NVIC_ICER_CLRENA_9              (0x00000200U)                           ///< bit 9
-#define NVIC_ICER_CLRENA_10             (0x00000400U)                           ///< bit 10
-#define NVIC_ICER_CLRENA_11             (0x00000800U)                           ///< bit 11
-#define NVIC_ICER_CLRENA_12             (0x00001000U)                           ///< bit 12
-#define NVIC_ICER_CLRENA_13             (0x00002000U)                           ///< bit 13
-#define NVIC_ICER_CLRENA_14             (0x00004000U)                           ///< bit 14
-#define NVIC_ICER_CLRENA_15             (0x00008000U)                           ///< bit 15
-#define NVIC_ICER_CLRENA_16             (0x00010000U)                           ///< bit 16
-#define NVIC_ICER_CLRENA_17             (0x00020000U)                           ///< bit 17
-#define NVIC_ICER_CLRENA_18             (0x00040000U)                           ///< bit 18
-#define NVIC_ICER_CLRENA_19             (0x00080000U)                           ///< bit 19
-#define NVIC_ICER_CLRENA_20             (0x00100000U)                           ///< bit 20
-#define NVIC_ICER_CLRENA_21             (0x00200000U)                           ///< bit 21
-#define NVIC_ICER_CLRENA_22             (0x00400000U)                           ///< bit 22
-#define NVIC_ICER_CLRENA_23             (0x00800000U)                           ///< bit 23
-#define NVIC_ICER_CLRENA_24             (0x01000000U)                           ///< bit 24
-#define NVIC_ICER_CLRENA_25             (0x02000000U)                           ///< bit 25
-#define NVIC_ICER_CLRENA_26             (0x04000000U)                           ///< bit 26
-#define NVIC_ICER_CLRENA_27             (0x08000000U)                           ///< bit 27
-#define NVIC_ICER_CLRENA_28             (0x10000000U)                           ///< bit 28
-#define NVIC_ICER_CLRENA_29             (0x20000000U)                           ///< bit 29
-#define NVIC_ICER_CLRENA_30             (0x40000000U)                           ///< bit 30
-#define NVIC_ICER_CLRENA_31             (0x80000000U)                           ///< bit 31
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_ISPR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_ISPR_SETPEND               (0xFFFFFFFFU)                           ///< Interrupt set-pending bits
-#define NVIC_ISPR_SETPEND_0             (0x00000001U)                           ///< bit 0
-#define NVIC_ISPR_SETPEND_1             (0x00000002U)                           ///< bit 1
-#define NVIC_ISPR_SETPEND_2             (0x00000004U)                           ///< bit 2
-#define NVIC_ISPR_SETPEND_3             (0x00000008U)                           ///< bit 3
-#define NVIC_ISPR_SETPEND_4             (0x00000010U)                           ///< bit 4
-#define NVIC_ISPR_SETPEND_5             (0x00000020U)                           ///< bit 5
-#define NVIC_ISPR_SETPEND_6             (0x00000040U)                           ///< bit 6
-#define NVIC_ISPR_SETPEND_7             (0x00000080U)                           ///< bit 7
-#define NVIC_ISPR_SETPEND_8             (0x00000100U)                           ///< bit 8
-#define NVIC_ISPR_SETPEND_9             (0x00000200U)                           ///< bit 9
-#define NVIC_ISPR_SETPEND_10            (0x00000400U)                           ///< bit 10
-#define NVIC_ISPR_SETPEND_11            (0x00000800U)                           ///< bit 11
-#define NVIC_ISPR_SETPEND_12            (0x00001000U)                           ///< bit 12
-#define NVIC_ISPR_SETPEND_13            (0x00002000U)                           ///< bit 13
-#define NVIC_ISPR_SETPEND_14            (0x00004000U)                           ///< bit 14
-#define NVIC_ISPR_SETPEND_15            (0x00008000U)                           ///< bit 15
-#define NVIC_ISPR_SETPEND_16            (0x00010000U)                           ///< bit 16
-#define NVIC_ISPR_SETPEND_17            (0x00020000U)                           ///< bit 17
-#define NVIC_ISPR_SETPEND_18            (0x00040000U)                           ///< bit 18
-#define NVIC_ISPR_SETPEND_19            (0x00080000U)                           ///< bit 19
-#define NVIC_ISPR_SETPEND_20            (0x00100000U)                           ///< bit 20
-#define NVIC_ISPR_SETPEND_21            (0x00200000U)                           ///< bit 21
-#define NVIC_ISPR_SETPEND_22            (0x00400000U)                           ///< bit 22
-#define NVIC_ISPR_SETPEND_23            (0x00800000U)                           ///< bit 23
-#define NVIC_ISPR_SETPEND_24            (0x01000000U)                           ///< bit 24
-#define NVIC_ISPR_SETPEND_25            (0x02000000U)                           ///< bit 25
-#define NVIC_ISPR_SETPEND_26            (0x04000000U)                           ///< bit 26
-#define NVIC_ISPR_SETPEND_27            (0x08000000U)                           ///< bit 27
-#define NVIC_ISPR_SETPEND_28            (0x10000000U)                           ///< bit 28
-#define NVIC_ISPR_SETPEND_29            (0x20000000U)                           ///< bit 29
-#define NVIC_ISPR_SETPEND_30            (0x40000000U)                           ///< bit 30
-#define NVIC_ISPR_SETPEND_31            (0x80000000U)                           ///< bit 31
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_ICPR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_ICPR_CLRPEND               (0xFFFFFFFFU)                           ///< Interrupt clear-pending bits
-#define NVIC_ICPR_CLRPEND_0             (0x00000001U)                           ///< bit 0
-#define NVIC_ICPR_CLRPEND_1             (0x00000002U)                           ///< bit 1
-#define NVIC_ICPR_CLRPEND_2             (0x00000004U)                           ///< bit 2
-#define NVIC_ICPR_CLRPEND_3             (0x00000008U)                           ///< bit 3
-#define NVIC_ICPR_CLRPEND_4             (0x00000010U)                           ///< bit 4
-#define NVIC_ICPR_CLRPEND_5             (0x00000020U)                           ///< bit 5
-#define NVIC_ICPR_CLRPEND_6             (0x00000040U)                           ///< bit 6
-#define NVIC_ICPR_CLRPEND_7             (0x00000080U)                           ///< bit 7
-#define NVIC_ICPR_CLRPEND_8             (0x00000100U)                           ///< bit 8
-#define NVIC_ICPR_CLRPEND_9             (0x00000200U)                           ///< bit 9
-#define NVIC_ICPR_CLRPEND_10            (0x00000400U)                           ///< bit 10
-#define NVIC_ICPR_CLRPEND_11            (0x00000800U)                           ///< bit 11
-#define NVIC_ICPR_CLRPEND_12            (0x00001000U)                           ///< bit 12
-#define NVIC_ICPR_CLRPEND_13            (0x00002000U)                           ///< bit 13
-#define NVIC_ICPR_CLRPEND_14            (0x00004000U)                           ///< bit 14
-#define NVIC_ICPR_CLRPEND_15            (0x00008000U)                           ///< bit 15
-#define NVIC_ICPR_CLRPEND_16            (0x00010000U)                           ///< bit 16
-#define NVIC_ICPR_CLRPEND_17            (0x00020000U)                           ///< bit 17
-#define NVIC_ICPR_CLRPEND_18            (0x00040000U)                           ///< bit 18
-#define NVIC_ICPR_CLRPEND_19            (0x00080000U)                           ///< bit 19
-#define NVIC_ICPR_CLRPEND_20            (0x00100000U)                           ///< bit 20
-#define NVIC_ICPR_CLRPEND_21            (0x00200000U)                           ///< bit 21
-#define NVIC_ICPR_CLRPEND_22            (0x00400000U)                           ///< bit 22
-#define NVIC_ICPR_CLRPEND_23            (0x00800000U)                           ///< bit 23
-#define NVIC_ICPR_CLRPEND_24            (0x01000000U)                           ///< bit 24
-#define NVIC_ICPR_CLRPEND_25            (0x02000000U)                           ///< bit 25
-#define NVIC_ICPR_CLRPEND_26            (0x04000000U)                           ///< bit 26
-#define NVIC_ICPR_CLRPEND_27            (0x08000000U)                           ///< bit 27
-#define NVIC_ICPR_CLRPEND_28            (0x10000000U)                           ///< bit 28
-#define NVIC_ICPR_CLRPEND_29            (0x20000000U)                           ///< bit 29
-#define NVIC_ICPR_CLRPEND_30            (0x40000000U)                           ///< bit 30
-#define NVIC_ICPR_CLRPEND_31            (0x80000000U)                           ///< bit 31
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_IABR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IABR_ACTIVE                (0xFFFFFFFFU)                           ///< Interrupt active flags
-#define NVIC_IABR_ACTIVE_0              (0x00000001U)                           ///< bit 0
-#define NVIC_IABR_ACTIVE_1              (0x00000002U)                           ///< bit 1
-#define NVIC_IABR_ACTIVE_2              (0x00000004U)                           ///< bit 2
-#define NVIC_IABR_ACTIVE_3              (0x00000008U)                           ///< bit 3
-#define NVIC_IABR_ACTIVE_4              (0x00000010U)                           ///< bit 4
-#define NVIC_IABR_ACTIVE_5              (0x00000020U)                           ///< bit 5
-#define NVIC_IABR_ACTIVE_6              (0x00000040U)                           ///< bit 6
-#define NVIC_IABR_ACTIVE_7              (0x00000080U)                           ///< bit 7
-#define NVIC_IABR_ACTIVE_8              (0x00000100U)                           ///< bit 8
-#define NVIC_IABR_ACTIVE_9              (0x00000200U)                           ///< bit 9
-#define NVIC_IABR_ACTIVE_10             (0x00000400U)                           ///< bit 10
-#define NVIC_IABR_ACTIVE_11             (0x00000800U)                           ///< bit 11
-#define NVIC_IABR_ACTIVE_12             (0x00001000U)                           ///< bit 12
-#define NVIC_IABR_ACTIVE_13             (0x00002000U)                           ///< bit 13
-#define NVIC_IABR_ACTIVE_14             (0x00004000U)                           ///< bit 14
-#define NVIC_IABR_ACTIVE_15             (0x00008000U)                           ///< bit 15
-#define NVIC_IABR_ACTIVE_16             (0x00010000U)                           ///< bit 16
-#define NVIC_IABR_ACTIVE_17             (0x00020000U)                           ///< bit 17
-#define NVIC_IABR_ACTIVE_18             (0x00040000U)                           ///< bit 18
-#define NVIC_IABR_ACTIVE_19             (0x00080000U)                           ///< bit 19
-#define NVIC_IABR_ACTIVE_20             (0x00100000U)                           ///< bit 20
-#define NVIC_IABR_ACTIVE_21             (0x00200000U)                           ///< bit 21
-#define NVIC_IABR_ACTIVE_22             (0x00400000U)                           ///< bit 22
-#define NVIC_IABR_ACTIVE_23             (0x00800000U)                           ///< bit 23
-#define NVIC_IABR_ACTIVE_24             (0x01000000U)                           ///< bit 24
-#define NVIC_IABR_ACTIVE_25             (0x02000000U)                           ///< bit 25
-#define NVIC_IABR_ACTIVE_26             (0x04000000U)                           ///< bit 26
-#define NVIC_IABR_ACTIVE_27             (0x08000000U)                           ///< bit 27
-#define NVIC_IABR_ACTIVE_28             (0x10000000U)                           ///< bit 28
-#define NVIC_IABR_ACTIVE_29             (0x20000000U)                           ///< bit 29
-#define NVIC_IABR_ACTIVE_30             (0x40000000U)                           ///< bit 30
-#define NVIC_IABR_ACTIVE_31             (0x80000000U)                           ///< bit 31
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI0 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR0_PRI_0                 (0x000000FFU)                           ///< Priority of interrupt 0
-#define NVIC_IPR0_PRI_1                 (0x0000FF00U)                           ///< Priority of interrupt 1
-#define NVIC_IPR0_PRI_2                 (0x00FF0000U)                           ///< Priority of interrupt 2
-#define NVIC_IPR0_PRI_3                 (0xFF000000U)                           ///< Priority of interrupt 3
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI1 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR1_PRI_4                 (0x000000FFU)                           ///< Priority of interrupt 4
-#define NVIC_IPR1_PRI_5                 (0x0000FF00U)                           ///< Priority of interrupt 5
-#define NVIC_IPR1_PRI_6                 (0x00FF0000U)                           ///< Priority of interrupt 6
-#define NVIC_IPR1_PRI_7                 (0xFF000000U)                           ///< Priority of interrupt 7
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR2_PRI_8                 (0x000000FFU)                           ///< Priority of interrupt 8
-#define NVIC_IPR2_PRI_9                 (0x0000FF00U)                           ///< Priority of interrupt 9
-#define NVIC_IPR2_PRI_10                (0x00FF0000U)                           ///< Priority of interrupt 10
-#define NVIC_IPR2_PRI_11                (0xFF000000U)                           ///< Priority of interrupt 11
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI3 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR3_PRI_12                (0x000000FFU)                           ///< Priority of interrupt 12
-#define NVIC_IPR3_PRI_13                (0x0000FF00U)                           ///< Priority of interrupt 13
-#define NVIC_IPR3_PRI_14                (0x00FF0000U)                           ///< Priority of interrupt 14
-#define NVIC_IPR3_PRI_15                (0xFF000000U)                           ///< Priority of interrupt 15
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI4 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR4_PRI_16                (0x000000FFU)                           ///< Priority of interrupt 16
-#define NVIC_IPR4_PRI_17                (0x0000FF00U)                           ///< Priority of interrupt 17
-#define NVIC_IPR4_PRI_18                (0x00FF0000U)                           ///< Priority of interrupt 18
-#define NVIC_IPR4_PRI_19                (0xFF000000U)                           ///< Priority of interrupt 19
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI5 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR5_PRI_20                (0x000000FFU)                           ///< Priority of interrupt 20
-#define NVIC_IPR5_PRI_21                (0x0000FF00U)                           ///< Priority of interrupt 21
-#define NVIC_IPR5_PRI_22                (0x00FF0000U)                           ///< Priority of interrupt 22
-#define NVIC_IPR5_PRI_23                (0xFF000000U)                           ///< Priority of interrupt 23
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI6 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR6_PRI_24                (0x000000FFU)                           ///< Priority of interrupt 24
-#define NVIC_IPR6_PRI_25                (0x0000FF00U)                           ///< Priority of interrupt 25
-#define NVIC_IPR6_PRI_26                (0x00FF0000U)                           ///< Priority of interrupt 26
-#define NVIC_IPR6_PRI_27                (0xFF000000U)                           ///< Priority of interrupt 27
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI7 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR7_PRI_28                (0x000000FFU)                           ///< Priority of interrupt 28
-#define NVIC_IPR7_PRI_29                (0x0000FF00U)                           ///< Priority of interrupt 29
-#define NVIC_IPR7_PRI_30                (0x00FF0000U)                           ///< Priority of interrupt 30
-#define NVIC_IPR7_PRI_31                (0xFF000000U)                           ///< Priority of interrupt 31
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI8 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR7_PRI_32                (0x000000FFU)                           ///< Priority of interrupt 32
-#define NVIC_IPR7_PRI_33                (0x0000FF00U)                           ///< Priority of interrupt 33
-#define NVIC_IPR7_PRI_34                (0x00FF0000U)                           ///< Priority of interrupt 34
-#define NVIC_IPR7_PRI_35                (0xFF000000U)                           ///< Priority of interrupt 35
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI9 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR7_PRI_36                (0x000000FFU)                           ///< Priority of interrupt 36
-#define NVIC_IPR7_PRI_37                (0x0000FF00U)                           ///< Priority of interrupt 37
-#define NVIC_IPR7_PRI_38                (0x00FF0000U)                           ///< Priority of interrupt 38
-#define NVIC_IPR7_PRI_39                (0xFF000000U)                           ///< Priority of interrupt 39
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI10 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR7_PRI_40                (0x000000FFU)                           ///< Priority of interrupt 40
-#define NVIC_IPR7_PRI_41                (0x0000FF00U)                           ///< Priority of interrupt 41
-#define NVIC_IPR7_PRI_42                (0x00FF0000U)                           ///< Priority of interrupt 42
-#define NVIC_IPR7_PRI_43                (0xFF000000U)                           ///< Priority of interrupt 43
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief NVIC_PRI11 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define NVIC_IPR7_PRI_44                (0x000000FFU)                           ///< Priority of interrupt 44
-#define NVIC_IPR7_PRI_45                (0x0000FF00U)                           ///< Priority of interrupt 45
-#define NVIC_IPR7_PRI_46                (0x00FF0000U)                           ///< Priority of interrupt 46
-#define NVIC_IPR7_PRI_47                (0xFF000000U)                           ///< Priority of interrupt 47
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_CPUID Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_CPUID_REVISION              (0x0000000FU)                           ///< Implementation defined revision number
-#define SCB_CPUID_PARTNO                (0x0000FFF0U)                           ///< Number of processor within family
-#define SCB_CPUID_Constant              (0x000F0000U)                           ///< Reads as 0x0F
-#define SCB_CPUID_VARIANT               (0x00F00000U)                           ///< Implementation defined variant number
-#define SCB_CPUID_IMPLEMENTER           (0xFF000000U)                           ///< Implementer code. ARM is 0x41
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_ICSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_ICSR_VECTACTIVE             (0x000001FFU)                           ///< Active ISR number field
-#define SCB_ICSR_RETTOBASE              (0x00000800U)                           ///< All active exceptions minus the IPSR_current_exception yields the empty set
-#define SCB_ICSR_VECTPENDING            (0x003FF000U)                           ///< Pending ISR number field
-#define SCB_ICSR_ISRPENDING             (0x00400000U)                           ///< Interrupt pending flag
-#define SCB_ICSR_ISRPREEMPT             (0x00800000U)                           ///< It indicates that a pending interrupt becomes active in the next running cycle
-#define SCB_ICSR_PENDSTCLR              (0x02000000U)                           ///< Clear pending SysTick bit
-#define SCB_ICSR_PENDSTSET              (0x04000000U)                           ///< Set pending SysTick bit
-#define SCB_ICSR_PENDSVCLR              (0x08000000U)                           ///< Clear pending pendSV bit
-#define SCB_ICSR_PENDSVSET              (0x10000000U)                           ///< Set pending pendSV bit
-#define SCB_ICSR_NMIPENDSET             (0x80000000U)                           ///< Set pending NMI bit
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_VTOR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_VTOR_TBLOFF                 (0x1FFFFF80U)                           ///< Vector table base offset field
-#define SCB_VTOR_TBLBASE                (0x20000000U)                           ///< Table base in code(0) or RAM(1)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_AIRCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_AIRCR_VECTRESET             (0x00000001U)                           ///< System Reset bit
-#define SCB_AIRCR_VECTCLRACTIVE         (0x00000002U)                           ///< Clear active vector bit
-#define SCB_AIRCR_SYSRESETREQ           (0x00000004U)                           ///< Requests chip control logic to generate a reset
-#define SCB_AIRCR_PRIGROUP              (0x00000700U)                           ///< PRIGROUP[2:0] bits (Priority group)
-#define SCB_AIRCR_PRIGROUP_0            (0x00000100U)                           ///< Bit 0
-#define SCB_AIRCR_PRIGROUP_1            (0x00000200U)                           ///< Bit 1
-#define SCB_AIRCR_PRIGROUP_2            (0x00000400U)                           ///< Bit 2
-
-#define SCB_AIRCR_PRIGROUP0             (0x00000000U)                           ///< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)
-#define SCB_AIRCR_PRIGROUP1             (0x00000100U)                           ///< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)
-#define SCB_AIRCR_PRIGROUP2             (0x00000200U)                           ///< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)
-#define SCB_AIRCR_PRIGROUP3             (0x00000300U)                           ///< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)
-#define SCB_AIRCR_PRIGROUP4             (0x00000400U)                           ///< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)
-#define SCB_AIRCR_PRIGROUP5             (0x00000500U)                           ///< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)
-#define SCB_AIRCR_PRIGROUP6             (0x00000600U)                           ///< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)
-#define SCB_AIRCR_PRIGROUP7             (0x00000700U)                           ///< Priority group=7 (no pre-emption priority, 8 bits of subpriority)
-
-#define SCB_AIRCR_ENDIANESS             (0x00008000U)                           ///< Data endianness bit
-#define SCB_AIRCR_VECTKEY               (0xFFFF0000U)                           ///< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_SCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_SCR_SLEEPONEXIT             (0x02U)                                 ///< Sleep on exit bit
-#define SCB_SCR_SLEEPDEEP               (0x04U)                                 ///< Sleep deep bit
-#define SCB_SCR_SEVONPEND               (0x10U)                                 ///< Wake up from WFE
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_CCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_CCR_NONBASETHRDENA          (0x0001U)                               ///< Thread mode can be entered from any level in Handler mode by controlled return value
-#define SCB_CCR_USERSETMPEND            (0x0002U)                               ///< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception
-#define SCB_CCR_UNALIGN_TRP             (0x0008U)                               ///< Trap for unaligned access
-#define SCB_CCR_DIV_0_TRP               (0x0010U)                               ///< Trap on Divide by 0
-#define SCB_CCR_BFHFNMIGN               (0x0100U)                               ///< Handlers running at priority -1 and -2
-#define SCB_CCR_STKALIGN                (0x0200U)                               ///< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_SHPR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_SHPR_PRI_N                  (0x000000FFU)                           ///< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor
-#define SCB_SHPR_PRI_N1                 (0x0000FF00U)                           ///< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved
-#define SCB_SHPR_PRI_N2                 (0x00FF0000U)                           ///< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV
-#define SCB_SHPR_PRI_N3                 (0xFF000000U)                           ///< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_SHCSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_SHCSR_MEMFAULTACT           (0x00000001U)                           ///< MemManage is active
-#define SCB_SHCSR_BUSFAULTACT           (0x00000002U)                           ///< BusFault is active
-#define SCB_SHCSR_USGFAULTACT           (0x00000008U)                           ///< UsageFault is active
-#define SCB_SHCSR_SVCALLACT             (0x00000080U)                           ///< SVCall is active
-#define SCB_SHCSR_MONITORACT            (0x00000100U)                           ///< Monitor is active
-#define SCB_SHCSR_PENDSVACT             (0x00000400U)                           ///< PendSV is active
-#define SCB_SHCSR_SYSTICKACT            (0x00000800U)                           ///< SysTick is active
-#define SCB_SHCSR_USGFAULTPENDED        (0x00001000U)                           ///< Usage Fault is pended
-#define SCB_SHCSR_MEMFAULTPENDED        (0x00002000U)                           ///< MemManage is pended
-#define SCB_SHCSR_BUSFAULTPENDED        (0x00004000U)                           ///< Bus Fault is pended
-#define SCB_SHCSR_SVCALLPENDED          (0x00008000U)                           ///< SVCall is pended
-#define SCB_SHCSR_MEMFAULTENA           (0x00010000U)                           ///< MemManage enable
-#define SCB_SHCSR_BUSFAULTENA           (0x00020000U)                           ///< Bus Fault enable
-#define SCB_SHCSR_USGFAULTENA           (0x00040000U)                           ///< UsageFault enable
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_CFSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-///< MFSR
-#define SCB_CFSR_IACCVIOL               (0x00000001U)                           ///< Instruction access violation
-#define SCB_CFSR_DACCVIOL               (0x00000002U)                           ///< Data access violation
-#define SCB_CFSR_MUNSTKERR              (0x00000008U)                           ///< Unstacking error
-#define SCB_CFSR_MSTKERR                (0x00000010U)                           ///< Stacking error
-#define SCB_CFSR_MMARVALID              (0x00000080U)                           ///< Memory Manage Address Register address valid flag
-///< BFSR
-#define SCB_CFSR_IBUSERR                (0x00000100U)                           ///< Instruction bus error flag
-#define SCB_CFSR_PRECISERR              (0x00000200U)                           ///< Precise data bus error
-#define SCB_CFSR_IMPRECISERR            (0x00000400U)                           ///< Imprecise data bus error
-#define SCB_CFSR_UNSTKERR               (0x00000800U)                           ///< Unstacking error
-#define SCB_CFSR_STKERR                 (0x00001000U)                           ///< Stacking error
-#define SCB_CFSR_BFARVALID              (0x00008000U)                           ///< Bus Fault Address Register address valid flag
-///< UFSR
-#define SCB_CFSR_UNDEFINSTR             (0x00010000U)                           ///< The processor attempt to excecute an undefined instruction
-#define SCB_CFSR_INVSTATE               (0x00020000U)                           ///< Invalid combination of EPSR and instruction
-#define SCB_CFSR_INVPC                  (0x00040000U)                           ///< Attempt to load EXC_RETURN into pc illegally
-#define SCB_CFSR_NOCP                   (0x00080000U)                           ///< Attempt to use a coprocessor instruction
-#define SCB_CFSR_UNALIGNED              (0x01000000U)                           ///< Fault occurs when there is an attempt to make an unaligned memory access
-#define SCB_CFSR_DIVBYZERO              (0x02000000U)                           ///< Fault occurs when SDIV or DIV instruction is used with a divisor of 0
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_HFSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_HFSR_VECTTBL                (0x00000002U)                           ///< Fault occures because of vector table read on exception processing
-#define SCB_HFSR_FORCED                 (0x40000000U)                           ///< Hard Fault activated when a configurable Fault was received and cannot activate
-#define SCB_HFSR_DEBUGEVT               (0x80000000U)                           ///< Fault related to debug
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_DFSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_DFSR_HALTED                 (0x01U)                                 ///< Halt request flag
-#define SCB_DFSR_BKPT                   (0x02U)                                 ///< BKPT flag
-#define SCB_DFSR_DWTTRAP                (0x04U)                                 ///< Data Watchpoint and Trace (DWT) flag
-#define SCB_DFSR_VCATCH                 (0x08U)                                 ///< Vector catch flag
-#define SCB_DFSR_EXTERNAL               (0x10U)                                 ///< External debug request flag
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_MMFAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_MMFAR_ADDRESS               (0xFFFFFFFFU)                           ///< Mem Manage fault address field
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_BFAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_BFAR_ADDRESS                (0xFFFFFFFFU)                           ///< Bus fault address field
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SCB_AFSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SCB_AFSR_IMPDEF                 (0xFFFFFFFFU)                           ///< Implementation defined
-
-
-
-#endif
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h
deleted file mode 100644
index 71297819c..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_comp.h
+++ /dev/null
@@ -1,228 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_comp.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_COMP_H
-#define __REG_COMP_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define COMP_BASE                       (APB2PERIPH_BASE + 0x4000)              ///< Base Address: 0x40014000
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Comparators Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-
-
-
-    __IO u32 RESERVED1;                                                         ///<                                                offset: 0x00
-    __IO u32 RESERVED2;                                                         ///<                                                offset: 0x04
-    __IO u32 RESERVED3;                                                         ///<                                                offset: 0x08
-    union {
-        __IO u32 CSR1;                                                          ///< COMP1 Control Status Register                  offset: 0x0C
-        __IO u32 COMP1_CSR;
-    };
-    union {
-        __IO u32 CSR2;                                                          ///< COMP2 Control Status Register                  offset: 0x10
-        __IO u32 COMP2_CSR;
-    };
-    __IO u32 RESERVED4;                                                         ///<                                                offset: 0x14
-    union {
-        __IO u32 CRV;                                                           ///< COMP external reference voltage register       offset: 0x18
-        __IO u32 COMP_CRV;
-    };
-    union {
-        __IO u32 POLL1;                                                         ///< COMP1 polling register                         offset: 0x1C
-        __IO u32 COMP1_POLL;
-    };
-    union {
-        __IO u32 POLL2;                                                         ///< COMP2 polling register                         offset: 0x20
-        __IO u32 COMP2_POLL;
-    };
-} COMP_TypeDef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define COMP                            ((COMP_TypeDef*) COMP_BASE)
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP_CSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define COMP_CSR_EN_Pos             (0)
-#define COMP_CSR_EN                 (0x01U << COMP_CSR_EN_Pos)              ///< Comparator enable
-#define COMP_CSR_MODE_Pos           (2)
-#define COMP_CSR_MODE               (0x03U << COMP_CSR_MODE_Pos)            ///< Comparator mode
-#define COMP_CSR_MODE_LOWESTPOWER   (0x00U << COMP_CSR_MODE_Pos)            ///< Comparator lowest power mode
-#define COMP_CSR_MODE_LOWPOWER      (0x01U << COMP_CSR_MODE_Pos)            ///< Comparator low power mode
-#define COMP_CSR_MODE_MEDIUMRATE    (0x02U << COMP_CSR_MODE_Pos)            ///< Comparator medium rate mode
-#define COMP_CSR_MODE_HIGHRATE      (0x03U << COMP_CSR_MODE_Pos)            ///< Comparator high rate mode
-
-#define COMP_CSR_INM_Pos            (4)
-#define COMP_CSR_INM                (0x03U << COMP_CSR_INM_Pos)             ///< Comparator inverting input selection
-#define COMP_CSR_INM_0              (0x00U << COMP_CSR_INM_Pos)             ///< INM0 as COMP inverting input
-#define COMP_CSR_INM_1              (0x01U << COMP_CSR_INM_Pos)             ///< INM1 as COMP inverting input
-#define COMP_CSR_INM_2              (0x02U << COMP_CSR_INM_Pos)             ///< INM2 as COMP inverting input
-#define COMP_CSR_INM_3              (0x03U << COMP_CSR_INM_Pos)             ///< INM3 as COMP inverting input
-
-#define COMP_CSR_INP_Pos            (7)
-#define COMP_CSR_INP                (0x03U << COMP_CSR_INP_Pos)             ///< Comparator non-inverting input selection
-#define COMP_CSR_INP_INP0           (0x00U << COMP_CSR_INP_Pos)             ///< INP0 as COMP non-inverting input
-#define COMP_CSR_INP_INP1           (0x01U << COMP_CSR_INP_Pos)             ///< INP1 as COMP non-inverting input
-#define COMP_CSR_INP_INP2           (0x02U << COMP_CSR_INP_Pos)             ///< INP2 as COMP non-inverting input
-#define COMP_CSR_INP_INP3           (0x03U << COMP_CSR_INP_Pos)             ///< INP3 as COMP non-inverting input
-
-#define COMP_CSR_OUT_Pos            (10)
-#define COMP_CSR_OUT                (0x0FU << COMP_CSR_OUT_Pos)             ///< Comparator output selection
-#define COMP_CSR_OUT_TIM1_BRAKE     (0x02U << COMP_CSR_OUT_Pos)             ///< Timer1 brake input
-#define COMP_CSR_OUT_TIM8_BRAKE     (0x03U << COMP_CSR_OUT_Pos)             ///< Timer8 brake input
-#define COMP_CSR_OUT_TIM1_OCREFCLR  (0x06U << COMP_CSR_OUT_Pos)             ///< Timer1 ocrefclear input
-#define COMP_CSR_OUT_TIM1_CAPTURE1  (0x07U << COMP_CSR_OUT_Pos)             ///< Timer1 input capture 1
-#define COMP_CSR_OUT_TIM2_CAPTURE4  (0x08U << COMP_CSR_OUT_Pos)             ///< Timer2 input capture 4
-#define COMP_CSR_OUT_TIM2_OCREFCLR  (0x09U << COMP_CSR_OUT_Pos)             ///< Timer2 ocrefclear input
-#define COMP_CSR_OUT_TIM3_CAPTURE1  (0x0AU << COMP_CSR_OUT_Pos)             ///< Timer3 input capture 1
-#define COMP_CSR_OUT_TIM3_OCREFCLR  (0x0BU << COMP_CSR_OUT_Pos)             ///< Timer3 ocrefclear input
-#define COMP_CSR_OUT_TIM8_OCREFCLR  (0x0FU << COMP_CSR_OUT_Pos)             ///< Timer8 ocrefclear input
-
-#define COMP_CSR_POL_Pos            (15)
-#define COMP_CSR_POL                (0x01U << COMP_CSR_POL_Pos)             ///< Comparator output polarity
-#define COMP_CSR_HYST_Pos           (16)
-#define COMP_CSR_HYST               (0x03U << COMP_CSR_HYST_Pos)            ///< Comparator hysteresis
-#define COMP_CSR_HYST_0             (0x00U << COMP_CSR_HYST_Pos)            ///< Hysteresis Voltage: 0mV
-#define COMP_CSR_HYST_15            (0x01U << COMP_CSR_HYST_Pos)            ///< Hysteresis Voltage: 15mV
-#define COMP_CSR_HYST_30            (0x02U << COMP_CSR_HYST_Pos)            ///< Hysteresis Voltage: 30mV
-#define COMP_CSR_HYST_90            (0x03U << COMP_CSR_HYST_Pos)            ///< Hysteresis Voltage: 90mV
-
-#define COMP_CSR_OFLT_Pos           (18)
-#define COMP_CSR_OFLT               (0x07U << COMP_CSR_OFLT_Pos)            ///< Comparator output filter
-#define COMP_CSR_OFLT_0             (0x00U << COMP_CSR_OFLT_Pos)            ///< 0 clock cycle
-#define COMP_CSR_OFLT_1             (0x01U << COMP_CSR_OFLT_Pos)            ///< 2 clock cycle
-#define COMP_CSR_OFLT_2             (0x02U << COMP_CSR_OFLT_Pos)            ///< 4 clock cycle
-#define COMP_CSR_OFLT_3             (0x03U << COMP_CSR_OFLT_Pos)            ///< 8 clock cycle
-#define COMP_CSR_OFLT_4             (0x04U << COMP_CSR_OFLT_Pos)            ///< 16 clock cycle
-#define COMP_CSR_OFLT_5             (0x05U << COMP_CSR_OFLT_Pos)            ///< 32 clock cycle
-#define COMP_CSR_OFLT_6             (0x06U << COMP_CSR_OFLT_Pos)            ///< 64 clock cycle
-#define COMP_CSR_OFLT_7             (0x07U << COMP_CSR_OFLT_Pos)            ///< 128 clock cycle
-
-#define COMP_CSR_STA_Pos            (30)
-#define COMP_CSR_STA                (0x01U << COMP_CSR_STA_Pos)             ///< Comparator output status
-#define COMP_CSR_LOCK_Pos           (31)
-#define COMP_CSR_LOCK               (0x01U << COMP_CSR_LOCK_Pos)            ///< Comparator lock
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP_CRV Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define COMP_CRV_Pos                (0)
-#define COMP_CRV_MASK               (0x0FU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_1_20               (0x00U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_2_20               (0x01U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_3_20               (0x02U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_4_20               (0x03U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_5_20               (0x04U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_6_20               (0x05U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_7_20               (0x06U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_8_20               (0x07U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_9_20               (0x08U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_10_20              (0x09U << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_11_20              (0x0AU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_12_20              (0x0BU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_13_20              (0x0CU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_14_20              (0x0DU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_15_20              (0x0EU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-#define COMP_CRV_16_20              (0x0FU << COMP_CRV_Pos)                 ///< Comparator external reference voltage select
-
-#define COMP_CRV_EN_Pos             (4)
-#define COMP_CRV_EN                 (0x01U << COMP_CRV_EN_Pos)              ///< Comparator external reference voltage enable
-#define COMP_CRV_EN_DISABLE         (0x00U << COMP_CRV_EN_Pos)              ///< Disable comparator external reference voltage
-#define COMP_CRV_EN_ENABLE          (0x01U << COMP_CRV_EN_Pos)              ///< Enable comparator external reference voltage
-#define COMP_CRV_SRC_Pos            (5)
-#define COMP_CRV_SRC                (0x01U << COMP_CRV_SRC_Pos)             ///< Comparator external reference voltage source select
-#define COMP_CRV_SRC_VREF           (0x00U << COMP_CRV_SRC_Pos)             ///< Select VREF
-#define COMP_CRV_SRC_AVDD           (0x01U << COMP_CRV_SRC_Pos)             ///< Select AVDD
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief COMP_POL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define COMP_POLL_EN_Pos            (0)
-#define COMP_POLL_EN                (0x01U << COMP_POLL_EN_Pos)              ///< Comparator polling enable
-#define COMP_POLL_EN_DISABLE        (0x00U << COMP_POLL_EN_Pos)              ///< Disable comparator polling mode
-#define COMP_POLL_EN_ENABLE         (0x01U << COMP_POLL_EN_Pos)              ///< Enable comparator polling mode
-#define COMP_POLL_CH_Pos            (1)
-#define COMP_POLL_CH                (0x01U << COMP_POLL_CH_Pos)              ///< Comparator polling channel
-#define COMP_POLL_CH_1_2            (0x00U << COMP_POLL_CH_Pos)              ///< Polling channel 1/2
-#define COMP_POLL_CH_1_2_3          (0x01U << COMP_POLL_CH_Pos)              ///< Polling channel 1/2/3
-#define COMP_POLL_FIXN_Pos          (2)
-#define COMP_POLL_FIXN              (0x01U << COMP_POLL_FIXN_Pos)            ///< Polling inverting input fix
-#define COMP_POLL_FIXN_NOTFIXED     (0x00U << COMP_POLL_FIXN_Pos)            ///< Polling channel inverting input is not fixed
-#define COMP_POLL_FIXN_FIXED        (0x01U << COMP_POLL_FIXN_Pos)            ///< Polling channel inverting input fixed
-#define COMP_POLL_PERIOD_Pos        (4)
-#define COMP_POLL_PERIOD            (0x07U << COMP_POLL_PERIOD_Pos)          ///< polling wait cycle
-#define COMP_POLL_PERIOD_1          (0x00U << COMP_POLL_PERIOD_Pos)          ///< 1 clock cycle
-#define COMP_POLL_PERIOD_2          (0x01U << COMP_POLL_PERIOD_Pos)          ///< 2 clock cycle
-#define COMP_POLL_PERIOD_4          (0x02U << COMP_POLL_PERIOD_Pos)          ///< 4 clock cycle
-#define COMP_POLL_PERIOD_8          (0x03U << COMP_POLL_PERIOD_Pos)          ///< 8 clock cycle
-#define COMP_POLL_PERIOD_16         (0x04U << COMP_POLL_PERIOD_Pos)          ///< 16 clock cycle
-#define COMP_POLL_PERIOD_32         (0x05U << COMP_POLL_PERIOD_Pos)          ///< 32 clock cycle
-#define COMP_POLL_PERIOD_64         (0x06U << COMP_POLL_PERIOD_Pos)          ///< 64 clock cycle
-#define COMP_POLL_PERIOD_128        (0x07U << COMP_POLL_PERIOD_Pos)          ///< 128 clock cycle
-#define COMP_POLL_POUT_Pos          (8)
-#define COMP_POLL_POUT              (0x07U << COMP_POLL_POUT_Pos)            ///< Polling output
-#define COMP_POLL_POUT_Low          (0x00U << COMP_POLL_POUT_Pos)            ///< Non-inverting input is lower than inverting input
-#define COMP_POLL_POUT_High         (0x01U << COMP_POLL_POUT_Pos)            ///< Non-inverting input is higher than inverting input
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h
deleted file mode 100644
index 9bb28e56f..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crc.h
+++ /dev/null
@@ -1,102 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_crc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_CRC_H
-#define __REG_CRC_H
-
-// Files includes
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRC Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRC_BASE                        (AHBPERIPH_BASE + 0x3000)               ///< Base Address: 0x40023000
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRC Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32   DR;                                                              ///< CRC data register,                             offset: 0x00
-    __IO u32   IDR;                                                             ///< CRC independent data register,                 offset: 0x04
-    __IO u32   CR;                                                              ///< CRC control register,                          offset: 0x08
-    __IO u32   MIR;                                                              ///< Middle data register,                          offset: 0x08
-} CRC_TypeDef;
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRC type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRC                             ((CRC_TypeDef*) CRC_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRC_DR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRC_DR_DATA_Pos                 (0)
-#define CRC_DR_DATA                     (0xFFFFFFFFU << CRC_DR_DATA_Pos)        ///< Data register bits
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRC_IDR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRC_IDR_DATA_Pos                (0)
-#define CRC_IDR_DATA                    (0xFFU << CRC_IDR_DATA_Pos)             ///< General-purpose 8-bit data register bits
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRC_CTRL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRC_CR_RESET_Pos                (0)
-#define CRC_CR_RESET                    (0x01U << CRC_CR_RESET_Pos)             ///< RESET bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRC_MIR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRC_MIR_Pos                 (0)
-#define CRC_MIR                     (0xFFFFFFFFU << CRC_MIR_Pos)        ///< Middle data register
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h
deleted file mode 100644
index a8beece98..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_crs.h
+++ /dev/null
@@ -1,152 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_crs.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_CRS_H
-#define __REG_CRS_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRS Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRS_BASE                        (APB1PERIPH_BASE + 0x6C00)              ///< Base Address: 0x40006C00
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRS Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 CR;                                                                ///< Control Register                    offset: 0x00
-    __IO u32 CFGR;                                                              ///< Configuration Register              offset: 0x04
-    __IO u32 ISR;                                                               ///< Interrupt and Status Register       offset: 0x08
-    __IO u32 ICR;                                                               ///< Interrupt Flag Clear Register       offset: 0x0C
-} CRS_TypeDef;
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRS type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRS                         ((CRS_TypeDef*) CRS_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRS_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRS_CR_OKIE_Pos             (0)
-#define CRS_CR_OKIE                 (0x01U << CRS_CR_OKIE_Pos)              ///< SYNC event OK interrupt enable
-#define CRS_CR_WARNIE_Pos           (1)
-#define CRS_CR_WARNIE               (0x01U << CRS_CR_WARNIE_Pos)            ///< SYNC warning interrupt enable
-#define CRS_CR_ERRIE_Pos            (2)
-#define CRS_CR_ERRIE                (0x01U << CRS_CR_ERRIE_Pos)             ///< Synchronization or trimming error interrupt enable
-#define CRS_CR_EXPTIE_Pos           (3)
-#define CRS_CR_EXPTIE               (0x01U << CRS_CR_EXPTIE_Pos)            ///< Expected SYNC interrupt enable
-#define CRS_CR_CNTEN_Pos            (5)
-#define CRS_CR_CNTEN                (0x01U << CRS_CR_CNTEN_Pos)             ///< Frequency error counter enable
-#define CRS_CR_AUTOTRIMEN_Pos       (6)
-#define CRS_CR_AUTOTRIMEN           (0x01U << CRS_CR_AUTOTRIMEN_Pos)        ///< Automatic trimming enable
-#define CRS_CR_SWSYNC_Pos           (7)
-#define CRS_CR_SWSYNC               (0x01U << CRS_CR_SWSYNC_Pos)            ///< Generate software SYNC event
-#define CRS_CR_TRIM_Pos             (8)
-#define CRS_CR_TRIM                 (0x3FFU << CRS_CR_TRIM_Pos)              ///< HSI 48 oscillator smooth trimming
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRS_CFGR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRS_CFGR_RELOAD_Pos         (0)
-#define CRS_CFGR_RELOAD             (0xFFFFU << CRS_CFGR_RELOAD_Pos)        ///< Counter reload value
-#define CRS_CFGR_FELIM_Pos          (16)
-#define CRS_CFGR_FELIM              (0xFFU << CRS_CFGR_FELIM_Pos)           ///< Frequency error limit
-#define CRS_CFGR_DIV_Pos            (24)
-#define CRS_CFGR_DIV                (0x07U << CRS_CFGR_DIV_Pos)             ///< SYNC divider
-#define CRS_CFGR_SRC_Pos            (28)
-#define CRS_CFGR_SRC                (0x03U << CRS_CFGR_SRC_Pos)             ///< SYNC signal source selection
-#define CRS_CFGR_SRC_MCO            (0x00U << CRS_CFGR_SRC_Pos)
-#define CRS_CFGR_SRC_USBSOF         (0x02U << CRS_CFGR_SRC_Pos)
-#define CRS_CFGR_POL_Pos            (31)
-#define CRS_CFGR_POL                (0x01U << CRS_CFGR_POL_Pos)             ///< SYNC polarity selection
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRS_ISR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRS_ISR_OKIF_Pos            (0)
-#define CRS_ISR_OKIF                (0x01U << CRS_ISR_OKIF_Pos)             ///< SYNC event OK flag
-#define CRS_ISR_WARNIF_Pos          (1)
-#define CRS_ISR_WARNIF              (0x01U << CRS_ISR_WARNIF_Pos)           ///< SYNC warning flag
-#define CRS_ISR_ERRIF_Pos           (2)
-#define CRS_ISR_ERRIF               (0x01U << CRS_ISR_ERRIF_Pos)            ///< Error flag
-#define CRS_ISR_EXPTIF_Pos          (3)
-#define CRS_ISR_EXPTIF              (0x01U << CRS_ISR_EXPTIF_Pos)           ///< Expected SYNC flag
-#define CRS_ISR_ERR_Pos             (8)
-#define CRS_ISR_ERR                 (0x01U << CRS_ISR_ERR_Pos)              ///< SYNC error
-#define CRS_ISR_MISS_Pos            (9)
-#define CRS_ISR_MISS                (0x01U << CRS_ISR_MISS_Pos)             ///< SYNC missed
-#define CRS_ISR_OVERFLOW_Pos        (10)
-#define CRS_ISR_OVERFLOW            (0x01U << CRS_ISR_OVERFLOW_Pos)         ///< Trimming overflow or underflow
-#define CRS_ISR_FEDIR_Pos           (15)
-#define CRS_ISR_FEDIR               (0x01U << CRS_ISR_FEDIR_Pos)            ///< Frequency error direction
-#define CRS_ISR_FECAP_Pos           (16)
-#define CRS_ISR_FECAP               (0xFFFFU << CRS_ISR_FECAP_Pos)          ///< Frequency error capture
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CRS_ICR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CRS_ICR_OK_Pos              (0)
-#define CRS_ICR_OK                  (0x01U << CRS_ICR_OK_Pos)               ///< SYNC event OK clear flag
-#define CRS_ICR_WARN_Pos            (1)
-#define CRS_ICR_WARN                (0x01U << CRS_ICR_WARN_Pos)             ///< SYNC warning clear flag
-#define CRS_ICR_ERR_Pos             (2)
-#define CRS_ICR_ERR                 (0x01U << CRS_ICR_ERR_Pos)              ///< Error clear flag
-#define CRS_ICR_EXPT_Pos            (3)
-#define CRS_ICR_EXPT                (0x01U << CRS_ICR_EXPT_Pos)             ///< Expected SYNC clear flag
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h
deleted file mode 100644
index 2e8d1883d..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dac.h
+++ /dev/null
@@ -1,247 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_dac.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_DAC_H
-#define __REG_DAC_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_BASE                        (APB1PERIPH_BASE + 0x7400)              ///< Base Address: 0x40007400
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Digital to analog converter register
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 CR;                                                                ///<  DAC control register,                         offset: 0x00
-    __IO u32 SWTRIGR;                                                           ///<  DAC software trigger register,                offset: 0x04
-    __IO u32 DHR12R1;                                                           ///<  Channel 1 12-bit right align data register,   offset: 0x08
-    __IO u32 DHR12L1;                                                           ///<  Channel 1 12-bit left align data register,    offset: 0x0C
-    __IO u32 DHR8R1;                                                            ///<  Channel 1 8-bit right align data register,    offset: 0x10
-    __IO u32 DHR12R2;                                                           ///<  Channel 2 12-bit right align data register,   offset: 0x14
-    __IO u32 DHR12L2;                                                           ///<  Channel 2 12-bit left align data register,    offset: 0x18
-    __IO u32 DHR8R2;                                                            ///<  Channel 2 8-bit right align data register,    offset: 0x1C
-    __IO u32 DHR12RD;                                                           ///<  Dual channel 12-bit right align data register,offset: 0x20
-    __IO u32 DHR12LD;                                                           ///<  Dual channel 12-bit left align data register, offset: 0x24
-    __IO u32 DHR8RD;                                                            ///<  Dual channel 8-bit right align data register, offset: 0x28
-    __IO u32 DOR1;                                                              ///<  Channel 1 output register,                    offset: 0x2C
-    __IO u32 DOR2;                                                              ///<  Channel 2 output register,                    offset: 0x30
-} DAC_TypeDef;
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC                         ((DAC_TypeDef*) DAC_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_CR_EN1_Pos              (0)
-#define DAC_CR_EN1                  (0x01U << DAC_CR_EN1_Pos)               ///< DAC channel1 enable
-#define DAC_CR_BOFF1_Pos            (1)
-#define DAC_CR_BOFF1                (0x01U << DAC_CR_BOFF1_Pos)             ///< DAC channel1 output buffer disable
-#define DAC_CR_TEN1_Pos             (2)
-#define DAC_CR_TEN1                 (0x01U << DAC_CR_TEN1_Pos)              ///< DAC channel1 Trigger enable
-#define DAC_CR_TSEL1_Pos            (3)
-#define DAC_CR_TSEL1                (0x07U << DAC_CR_TSEL1_Pos)             ///< TSEL1[2:0] (DAC channel1 Trigger selection)
-#define DAC_CR_TSEL1_TIM1_TRIG      (0x00U << DAC_CR_TSEL1_Pos)             ///< TIM1_TRIG trigger
-#define DAC_CR_TSEL1_TIM3_TRIG      (0x01U << DAC_CR_TSEL1_Pos)             ///< TIM3_TRIG trigger
-#define DAC_CR_TSEL1_TIM2_TRIG      (0x04U << DAC_CR_TSEL1_Pos)             ///< TIM2_TRIG trigger
-#define DAC_CR_TSEL1_TIM4_TRIG      (0x05U << DAC_CR_TSEL1_Pos)             ///< TIM4_TRIG trigger
-#define DAC_CR_TSEL1_EXTI9          (0x06U << DAC_CR_TSEL1_Pos)             ///< External interrupt line 9 trigger
-#define DAC_CR_TSEL1_SOFTWARE       (0x07U << DAC_CR_TSEL1_Pos)             ///< Software trigger
-#define DAC_CR_WAVE1_Pos            (6)
-#define DAC_CR_WAVE1                (0x03U << DAC_CR_WAVE1_Pos)             ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
-#define DAC_CR_WAVE1_NONE           (0x00U << DAC_CR_WAVE1_Pos)             ///< Turn off waveform generation
-#define DAC_CR_WAVE1_NOISE          (0x01U << DAC_CR_WAVE1_Pos)             ///< Noise waveform generation
-#define DAC_CR_WAVE1_TRIANGLE       (0x02U << DAC_CR_WAVE1_Pos)             ///< Triangle wave generation
-#define DAC_CR_MAMP1_Pos            (8)
-#define DAC_CR_MAMP1                (0x0FU << DAC_CR_MAMP1_Pos)             ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
-#define DAC_CR_MAMP1_1              (0x00U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 1
-#define DAC_CR_MAMP1_3              (0x01U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 3
-#define DAC_CR_MAMP1_7              (0x02U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 7
-#define DAC_CR_MAMP1_15             (0x03U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 15
-#define DAC_CR_MAMP1_31             (0x04U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 31
-#define DAC_CR_MAMP1_63             (0x05U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 63
-#define DAC_CR_MAMP1_127            (0x06U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 127
-#define DAC_CR_MAMP1_255            (0x07U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 255
-#define DAC_CR_MAMP1_511            (0x08U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 511
-#define DAC_CR_MAMP1_1023           (0x09U << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 1023
-#define DAC_CR_MAMP1_2047           (0x0AU << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 2047
-#define DAC_CR_MAMP1_4095           (0x0BU << DAC_CR_MAMP1_Pos)             ///< Triangle wave amplitude equal to 4095
-#define DAC_CR_DMAEN1_Pos           (12)
-#define DAC_CR_DMAEN1               (0x01U << DAC_CR_DMAEN1_Pos)            ///< DAC channel1 DMA enable
-#define DAC_CR_EN2_Pos              (16)
-#define DAC_CR_EN2                  (0x01U << DAC_CR_EN2_Pos)               ///< DAC channel2 enable
-#define DAC_CR_BOFF2_Pos            (17)
-#define DAC_CR_BOFF2                (0x01U << DAC_CR_BOFF2_Pos)             ///< DAC channel2 output buffer disable
-#define DAC_CR_TEN2_Pos             (18)
-#define DAC_CR_TEN2                 (0x01U << DAC_CR_TEN2_Pos)              ///< DAC channel2 Trigger enable
-#define DAC_CR_TSEL2_Pos            (19)
-#define DAC_CR_TSEL2                (0x07U << DAC_CR_TSEL2_Pos)             ///< TSEL1[2:0] (DAC channel1 Trigger selection)
-#define DAC_CR_TSEL2_TIM1_TRIG      (0x00U << DAC_CR_TSEL2_Pos)             ///< TIM1_TRIG trigger
-#define DAC_CR_TSEL2_TIM3_TRIG      (0x01U << DAC_CR_TSEL2_Pos)             ///< TIM3_TRIG trigger
-#define DAC_CR_TSEL2_TIM2_TRIG      (0x04U << DAC_CR_TSEL2_Pos)             ///< TIM2_TRIG trigger
-#define DAC_CR_TSEL2_TIM4_TRIG      (0x05U << DAC_CR_TSEL2_Pos)             ///< TIM4_TRIG trigger
-#define DAC_CR_TSEL2_EXTI9          (0x06U << DAC_CR_TSEL2_Pos)             ///< External interrupt line 9 trigger
-#define DAC_CR_TSEL2_SOFTWARE       (0x07U << DAC_CR_TSEL2_Pos)             ///< Software trigger
-#define DAC_CR_WAVE2_Pos            (22)
-#define DAC_CR_WAVE2                (0x03U << DAC_CR_WAVE2_Pos)             ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)
-#define DAC_CR_WAVE2_NONE           (0x00U << DAC_CR_WAVE2_Pos)             ///< Turn off waveform generation
-#define DAC_CR_WAVE2_NOISE          (0x01U << DAC_CR_WAVE2_Pos)             ///< Noise waveform generation
-#define DAC_CR_WAVE2_TRIANGLE       (0x02U << DAC_CR_WAVE2_Pos)             ///< Triangle wave generation
-#define DAC_CR_MAMP2_Pos            (24)
-#define DAC_CR_MAMP2                (0x0FU << DAC_CR_MAMP2_Pos)             ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)
-#define DAC_CR_MAMP2_1              (0x00U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 1
-#define DAC_CR_MAMP2_3              (0x01U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 3
-#define DAC_CR_MAMP2_7              (0x02U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 7
-#define DAC_CR_MAMP2_15             (0x03U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 15
-#define DAC_CR_MAMP2_31             (0x04U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 31
-#define DAC_CR_MAMP2_63             (0x05U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 63
-#define DAC_CR_MAMP2_127            (0x06U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 127
-#define DAC_CR_MAMP2_255            (0x07U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 255
-#define DAC_CR_MAMP2_511            (0x08U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 511
-#define DAC_CR_MAMP2_1023           (0x09U << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 1023
-#define DAC_CR_MAMP2_2047           (0x0AU << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 2047
-#define DAC_CR_MAMP2_4095           (0x0BU << DAC_CR_MAMP2_Pos)             ///< Triangle wave amplitude equal to 4095
-#define DAC_CR_DMAEN2_Pos           (28)
-#define DAC_CR_DMAEN2               (0x01U << DAC_CR_DMAEN2_Pos)            ///< DAC channel2 DMA enabled
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_SWTRIGR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0)
-#define DAC_SWTRIGR_SWTRIG1         (0x01U << DAC_SWTRIGR_SWTRIG1_Pos)      ///< DAC channel1 software trigger
-#define DAC_SWTRIGR_SWTRIG2_Pos     (1)
-#define DAC_SWTRIGR_SWTRIG2         (0x01U << DAC_SWTRIGR_SWTRIG2_Pos)      ///< DAC channel2 software trigger
-#define DAC_SWTRIGR_DACPRE_Pos      (8)
-#define DAC_SWTRIGR_DACPRE          (0x7FU << DAC_SWTRIGR_DACPRE_Pos)       ///< DAC prescale
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DHR12R1 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DHR12R1_DACC1DHR_Pos    (0)
-#define DAC_DHR12R1_DACC1DHR        (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)    ///< DAC channel1 12-bit Right align data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DHR12L1 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DHR12L1_DACC1DHR_Pos    (4)
-#define DAC_DHR12L1_DACC1DHR        (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)    ///< DAC channel1 12-bit Left align data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DHR8R1 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DHR8R1_DACC1DHR_Pos     (0)
-#define DAC_DHR8R1_DACC1DHR         (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)      ///< DAC channel1 8-bit Right align data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DHR12R2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DHR12R2_DACC2DHR_Pos    (0)
-#define DAC_DHR12R2_DACC2DHR        (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)    ///< DAC channel2 12-bit Right align data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DHR12L2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DHR12L2_DACC2DHR_Pos    (4)
-#define DAC_DHR12L2_DACC2DHR        (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)    ///< DAC channel2 12-bit Left align data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DHR8R2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DHR8R2_DACC2DHR_Pos     (0)
-#define DAC_DHR8R2_DACC2DHR         (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)      ///< DAC channel2 8-bit Right align data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DHR12RD Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DHR12RD_DACC1DHR_Pos    (0)
-#define DAC_DHR12RD_DACC1DHR        (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)    ///< DAC channel1 12-bit Right align data
-#define DAC_DHR12RD_DACC2DHR_Pos    (16)
-#define DAC_DHR12RD_DACC2DHR        (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)    ///< DAC channel2 12-bit Right align data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DHR12LD Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DHR12LD_DACC1DHR_Pos    (4)
-#define DAC_DHR12LD_DACC1DHR        (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)    ///< DAC channel1 12-bit Right align data
-#define DAC_DHR12LD_DACC2DHR_Pos    (20)
-#define DAC_DHR12LD_DACC2DHR        (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)    ///< DAC channel2 12-bit Right align data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DHR8RD Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DHR8RD_DACC1DHR_Pos     (0)
-#define DAC_DHR8RD_DACC1DHR         (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)      ///< DAC channel1 8-bit Right align data
-#define DAC_DHR8RD_DACC2DHR_Pos     (8)
-#define DAC_DHR8RD_DACC2DHR         (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)      ///< DAC channel2 8-bit Right align data
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DOR1 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DOR1_DACC1DOR_Pos       (0)
-#define DAC_DOR1_DACC1DOR           (0xFFFU << DAC_DOR1_DACC1DOR_Pos)       ///< DAC channel1 data output
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DAC_DOR2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DAC_DOR2_DACC2DOR_Pos       (0)
-#define DAC_DOR2_DACC2DOR           (0xFFFU << DAC_DOR2_DACC2DOR_Pos)       ///< DAC channel2 data output #endif
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h
deleted file mode 100644
index 5e378753e..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dbg.h
+++ /dev/null
@@ -1,113 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_dbg.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_DBG_H
-#define __REG_DBG_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DBG Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define DBG_BASE                        (0x40007080UL)                         ///< Base Address: 0x40007080
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DEBUG Registers Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 IDCODE;                                                            ///< Code ID                                        offset: 0x00
-    __IO u32 CR;                                                                ///< Control Register                               offset: 0x04
-} DBGMCU_TypeDef;
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DBGMCU type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DBGMCU                          ((DBGMCU_TypeDef*) DBG_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DBGMCU_IDCODE Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DBGMCU_IDCODE_DEV_ID_Pos        (0)
-#define DBGMCU_IDCODE_DEV_ID            (0xFFFFFFFFU << DBGMCU_IDCODE_DEV_ID_Pos)   ///< Device identifier
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DBGMCU_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DBGMCU_CR_SLEEP_Pos             (0)
-#define DBGMCU_CR_SLEEP                 (0x01U << DBGMCU_CR_SLEEP_Pos)          ///< Debug Sleep mode
-#define DBGMCU_CR_STOP_Pos              (1)
-#define DBGMCU_CR_STOP                  (0x01U << DBGMCU_CR_STOP_Pos)           ///< Debug Stop mode
-#define DBGMCU_CR_STANDBY_Pos           (2)
-#define DBGMCU_CR_STANDBY               (0x01U << DBGMCU_CR_STANDBY_Pos)        ///< Debug Standby mode
-#define DBGMCU_CR_TRACE_IOEN_Pos        (5)
-#define DBGMCU_CR_TRACE_IOEN            (0x01U << DBGMCU_CR_TRACE_IOEN_Pos)     ///< Trace pin assignment
-#define DBGMCU_CR_TRACE_MODE_Pos        (6)
-#define DBGMCU_CR_TRACE_MODE_Msk        (0x03U << DBGMCU_CR_TRACE_MODE_Pos)     ///< TRACE_MODE[1:0] bits (Trace Pin Assignment Control)
-#define DBGMCU_CR_TRACE_MODE_0          (0x01U << DBGMCU_CR_TRACE_MODE_Pos)     ///< Bit 0
-#define DBGMCU_CR_TRACE_MODE_1          (0x02U << DBGMCU_CR_TRACE_MODE_Pos)     ///< Bit 1
-#define DBGMCU_CR_TRACE_MODE_ASYNC      (0x00U << DBGMCU_CR_TRACE_MODE_Pos)     ///< Tracking pin uses asynchronous mode
-#define DBGMCU_CR_TRACE_MODE_SYNC1      (0x01U << DBGMCU_CR_TRACE_MODE_Pos)     ///< The trace pin uses synchronous mode, and the data length is 1
-#define DBGMCU_CR_TRACE_MODE_SYNC2      (0x02U << DBGMCU_CR_TRACE_MODE_Pos)     ///< The trace pin uses synchronous mode, and the data length is 2
-
-#define DBGMCU_CR_IWDG_STOP_Pos         (8)
-#define DBGMCU_CR_IWDG_STOP             (0x01U << DBGMCU_CR_IWDG_STOP_Pos)      ///< Debug independent watchdog stopped when core is halted
-#define DBGMCU_CR_WWDG_STOP_Pos         (9)
-#define DBGMCU_CR_WWDG_STOP             (0x01U << DBGMCU_CR_WWDG_STOP_Pos)      ///< Debug window watchdog stopped when core is halted
-#define DBGMCU_CR_TIM_STOP_Pos          (10)
-#define DBGMCU_CR_TIM1_STOP             (0x01U << DBGMCU_CR_TIM_STOP_Pos)       ///< TIM1 counter stopped when core is halted
-#define DBGMCU_CR_TIM2_STOP             (0x02U << DBGMCU_CR_TIM_STOP_Pos)       ///< TIM2 counter stopped when core is halted
-#define DBGMCU_CR_TIM3_STOP             (0x04U << DBGMCU_CR_TIM_STOP_Pos)       ///< TIM3 counter stopped when core is halted
-#define DBGMCU_CR_TIM4_STOP             (0x08U << DBGMCU_CR_TIM_STOP_Pos)       ///< TIM4 counter stopped when core is halted
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h
deleted file mode 100644
index ffcba5654..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_dma.h
+++ /dev/null
@@ -1,325 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_dma.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_DMA_H
-#define __REG_DMA_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DMA1_BASE                       (AHBPERIPH_BASE + 0x0000)               ///< Base Address: 0x40020000
-#define DMA1_Channel1_BASE              (AHBPERIPH_BASE + 0x0008)               ///< Base Address: 0x40020008
-#define DMA1_Channel2_BASE              (AHBPERIPH_BASE + 0x001C)               ///< Base Address: 0x4002001C
-#define DMA1_Channel3_BASE              (AHBPERIPH_BASE + 0x0030)               ///< Base Address: 0x40020030
-#define DMA1_Channel4_BASE              (AHBPERIPH_BASE + 0x0044)               ///< Base Address: 0x40020044
-#define DMA1_Channel5_BASE              (AHBPERIPH_BASE + 0x0058)               ///< Base Address: 0x40020058
-
-#define DMA1_Channel6_BASE              (AHBPERIPH_BASE + 0x006C)               ///< Base Address: 0x4002006C
-#define DMA1_Channel7_BASE              (AHBPERIPH_BASE + 0x0080)               ///< Base Address: 0x40020080
-#define DMA2_BASE                       (AHBPERIPH_BASE + 0x0400)               ///< Base Address: 0x40020400
-#define DMA2_Channel1_BASE              (AHBPERIPH_BASE + 0x0408)               ///< Base Address: 0x40020408
-#define DMA2_Channel2_BASE              (AHBPERIPH_BASE + 0x041C)               ///< Base Address: 0x4002041C
-#define DMA2_Channel3_BASE              (AHBPERIPH_BASE + 0x0430)               ///< Base Address: 0x40020430
-#define DMA2_Channel4_BASE              (AHBPERIPH_BASE + 0x0444)               ///< Base Address: 0x40020444
-#define DMA2_Channel5_BASE              (AHBPERIPH_BASE + 0x0458)               ///< Base Address: 0x40020458
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 CCR;                                                               ///< DMA channel x configuration register           offset: 0x00
-    __IO u32 CNDTR;                                                             ///< DMA channel x number of data register          offset: 0x04
-    __IO u32 CPAR;                                                              ///< DMA channel x peripheral address register      offset: 0x08
-    __IO u32 CMAR;                                                              ///< DMA channel x memory address register          offset: 0x0C
-} DMA_Channel_TypeDef;
-
-typedef struct {
-    __IO u32 ISR;                                                               ///< Interrupt Status Register                      offset: 0x00
-    __IO u32 IFCR;                                                              ///< Interrupt Flag Clear Register                  offset: 0x04
-    __IO u32 CCRx;                                                              ///< Channel X configures registers                 offset: 0x08
-    __IO u32 CNDTRx;                                                            ///< Channel X transfer quantity register           offset: 0x0C
-    __IO u32 CPARx;                                                             ///< Channel X peripheral address register          offset: 0x10
-    __IO u32 CMARx;                                                             ///< Channel X memory address register              offset: 0x14
-} DMA_TypeDef;
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DMA1                            ((DMA_TypeDef*) DMA1_BASE)
-#define DMA1_ch1                        ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE)
-#define DMA1_ch2                        ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE)
-#define DMA1_ch3                        ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE)
-#define DMA1_ch4                        ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE)
-#define DMA1_ch5                        ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE)
-
-#define DMA1_Channel1                   ((DMA_Channel_TypeDef*) DMA1_Channel1_BASE)
-#define DMA1_Channel2                   ((DMA_Channel_TypeDef*) DMA1_Channel2_BASE)
-#define DMA1_Channel3                   ((DMA_Channel_TypeDef*) DMA1_Channel3_BASE)
-#define DMA1_Channel4                   ((DMA_Channel_TypeDef*) DMA1_Channel4_BASE)
-#define DMA1_Channel5                   ((DMA_Channel_TypeDef*) DMA1_Channel5_BASE)
-
-
-#define DMA1_ch6                        ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE)
-#define DMA1_ch7                        ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE)
-
-#define DMA1_Channel6                   ((DMA_Channel_TypeDef*) DMA1_Channel6_BASE)
-#define DMA1_Channel7                   ((DMA_Channel_TypeDef*) DMA1_Channel7_BASE)
-
-#define DMA2                            ((DMA_TypeDef*) DMA2_BASE)
-#define DMA2_ch1                        ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE)
-#define DMA2_ch2                        ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE)
-#define DMA2_ch3                        ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE)
-#define DMA2_ch4                        ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE)
-#define DMA2_ch5                        ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE)
-#define DMA2_Channel1                   ((DMA_Channel_TypeDef*) DMA2_Channel1_BASE)
-#define DMA2_Channel2                   ((DMA_Channel_TypeDef*) DMA2_Channel2_BASE)
-#define DMA2_Channel3                   ((DMA_Channel_TypeDef*) DMA2_Channel3_BASE)
-#define DMA2_Channel4                   ((DMA_Channel_TypeDef*) DMA2_Channel4_BASE)
-#define DMA2_Channel5                   ((DMA_Channel_TypeDef*) DMA2_Channel5_BASE)
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA_ISR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DMA_ISR_GIF1_Pos                (0)
-#define DMA_ISR_GIF1                    (0x01U << DMA_ISR_GIF1_Pos)             ///< Channel 1 Global interrupt flag
-#define DMA_ISR_TCIF1_Pos               (1)
-#define DMA_ISR_TCIF1                   (0x01U << DMA_ISR_TCIF1_Pos)            ///< Channel 1 Transfer Complete flag
-#define DMA_ISR_HTIF1_Pos               (2)
-#define DMA_ISR_HTIF1                   (0x01U << DMA_ISR_HTIF1_Pos)            ///< Channel 1 Half Transfer flag
-#define DMA_ISR_TEIF1_Pos               (3)
-#define DMA_ISR_TEIF1                   (0x01U << DMA_ISR_TEIF1_Pos)            ///< Channel 1 Transfer Error flag
-#define DMA_ISR_GIF2_Pos                (4)
-#define DMA_ISR_GIF2                    (0x01U << DMA_ISR_GIF2_Pos)             ///< Channel 2 Global interrupt flag
-#define DMA_ISR_TCIF2_Pos               (5)
-#define DMA_ISR_TCIF2                   (0x01U << DMA_ISR_TCIF2_Pos)            ///< Channel 2 Transfer Complete flag
-#define DMA_ISR_HTIF2_Pos               (6)
-#define DMA_ISR_HTIF2                   (0x01U << DMA_ISR_HTIF2_Pos)            ///< Channel 2 Half Transfer flag
-#define DMA_ISR_TEIF2_Pos               (7)
-#define DMA_ISR_TEIF2                   (0x01U << DMA_ISR_TEIF2_Pos)            ///< Channel 2 Transfer Error flag
-#define DMA_ISR_GIF3_Pos                (8)
-#define DMA_ISR_GIF3                    (0x01U << DMA_ISR_GIF3_Pos)             ///< Channel 3 Global interrupt flag
-#define DMA_ISR_TCIF3_Pos               (9)
-#define DMA_ISR_TCIF3                   (0x01U << DMA_ISR_TCIF3_Pos)            ///< Channel 3 Transfer Complete flag
-#define DMA_ISR_HTIF3_Pos               (10)
-#define DMA_ISR_HTIF3                   (0x01U << DMA_ISR_HTIF3_Pos)            ///< Channel 3 Half Transfer flag
-#define DMA_ISR_TEIF3_Pos               (11)
-#define DMA_ISR_TEIF3                   (0x01U << DMA_ISR_TEIF3_Pos)            ///< Channel 3 Transfer Error flag
-#define DMA_ISR_GIF4_Pos                (12)
-#define DMA_ISR_GIF4                    (0x01U << DMA_ISR_GIF4_Pos)             ///< Channel 4 Global interrupt flag
-#define DMA_ISR_TCIF4_Pos               (13)
-#define DMA_ISR_TCIF4                   (0x01U << DMA_ISR_TCIF4_Pos)            ///< Channel 4 Transfer Complete flag
-#define DMA_ISR_HTIF4_Pos               (14)
-#define DMA_ISR_HTIF4                   (0x01U << DMA_ISR_HTIF4_Pos)            ///< Channel 4 Half Transfer flag
-#define DMA_ISR_TEIF4_Pos               (15)
-#define DMA_ISR_TEIF4                   (0x01U << DMA_ISR_TEIF4_Pos)            ///< Channel 4 Transfer Error flag
-#define DMA_ISR_GIF5_Pos                (16)
-#define DMA_ISR_GIF5                    (0x01U << DMA_ISR_GIF5_Pos)             ///< Channel 5 Global interrupt flag
-#define DMA_ISR_TCIF5_Pos               (17)
-#define DMA_ISR_TCIF5                   (0x01U << DMA_ISR_TCIF5_Pos)            ///< Channel 5 Transfer Complete flag
-#define DMA_ISR_HTIF5_Pos               (18)
-#define DMA_ISR_HTIF5                   (0x01U << DMA_ISR_HTIF5_Pos)            ///< Channel 5 Half Transfer flag
-#define DMA_ISR_TEIF5_Pos               (19)
-#define DMA_ISR_TEIF5                   (0x01U << DMA_ISR_TEIF5_Pos)            ///< Channel 5 Transfer Error flag
-
-#define DMA_ISR_GIF6_Pos                (20)
-#define DMA_ISR_GIF6                    (0x01U << DMA_ISR_GIF6_Pos)             ///< Channel 6 Global interrupt flag
-#define DMA_ISR_TCIF6_Pos               (21)
-#define DMA_ISR_TCIF6                   (0x01U << DMA_ISR_TCIF6_Pos)            ///< Channel 6 Transfer Complete flag
-#define DMA_ISR_HTIF6_Pos               (22)
-#define DMA_ISR_HTIF6                   (0x01U << DMA_ISR_HTIF6_Pos)            ///< Channel 6 Half Transfer flag
-#define DMA_ISR_TEIF6_Pos               (23)
-#define DMA_ISR_TEIF6                   (0x01U << DMA_ISR_TEIF6_Pos)            ///< Channel 6 Transfer Error flag
-#define DMA_ISR_GIF7_Pos                (24)
-#define DMA_ISR_GIF7                    (0x01U << DMA_ISR_GIF7_Pos)             ///< Channel 7 Global interrupt flag
-#define DMA_ISR_TCIF7_Pos               (25)
-#define DMA_ISR_TCIF7                   (0x01U << DMA_ISR_TCIF7_Pos)            ///< Channel 7 Transfer Complete flag
-#define DMA_ISR_HTIF7_Pos               (26)
-#define DMA_ISR_HTIF7                   (0x01U << DMA_ISR_HTIF7_Pos)            ///< Channel 7 Half Transfer flag
-#define DMA_ISR_TEIF7_Pos               (27)
-#define DMA_ISR_TEIF7                   (0x01U << DMA_ISR_TEIF7_Pos)            ///< Channel 7 Transfer Error flag
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA_IFCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DMA_IFCR_CGIF1_Pos              (0)
-#define DMA_IFCR_CGIF1                  (0x01U << DMA_IFCR_CGIF1_Pos)           ///< Channel 1 Global interrupt clearr
-#define DMA_IFCR_CTCIF1_Pos             (1)
-#define DMA_IFCR_CTCIF1                 (0x01U << DMA_IFCR_CTCIF1_Pos)          ///< Channel 1 Transfer Complete clear
-#define DMA_IFCR_CHTIF1_Pos             (2)
-#define DMA_IFCR_CHTIF1                 (0x01U << DMA_IFCR_CHTIF1_Pos)          ///< Channel 1 Half Transfer clear
-#define DMA_IFCR_CTEIF1_Pos             (3)
-#define DMA_IFCR_CTEIF1                 (0x01U << DMA_IFCR_CTEIF1_Pos)          ///< Channel 1 Transfer Error clear
-#define DMA_IFCR_CGIF2_Pos              (4)
-#define DMA_IFCR_CGIF2                  (0x01U << DMA_IFCR_CGIF2_Pos)           ///< Channel 2 Global interrupt clear
-#define DMA_IFCR_CTCIF2_Pos             (5)
-#define DMA_IFCR_CTCIF2                 (0x01U << DMA_IFCR_CTCIF2_Pos)          ///< Channel 2 Transfer Complete clear
-#define DMA_IFCR_CHTIF2_Pos             (6)
-#define DMA_IFCR_CHTIF2                 (0x01U << DMA_IFCR_CHTIF2_Pos)          ///< Channel 2 Half Transfer clear
-#define DMA_IFCR_CTEIF2_Pos             (7)
-#define DMA_IFCR_CTEIF2                 (0x01U << DMA_IFCR_CTEIF2_Pos)          ///< Channel 2 Transfer Error clear
-#define DMA_IFCR_CGIF3_Pos              (8)
-#define DMA_IFCR_CGIF3                  (0x01U << DMA_IFCR_CGIF3_Pos)           ///< Channel 3 Global interrupt clear
-#define DMA_IFCR_CTCIF3_Pos             (9)
-#define DMA_IFCR_CTCIF3                 (0x01U << DMA_IFCR_CTCIF3_Pos)          ///< Channel 3 Transfer Complete clear
-#define DMA_IFCR_CHTIF3_Pos             (10)
-#define DMA_IFCR_CHTIF3                 (0x01U << DMA_IFCR_CHTIF3_Pos)          ///< Channel 3 Half Transfer clear
-#define DMA_IFCR_CTEIF3_Pos             (11)
-#define DMA_IFCR_CTEIF3                 (0x01U << DMA_IFCR_CTEIF3_Pos)          ///< Channel 3 Transfer Error clear
-#define DMA_IFCR_CGIF4_Pos              (12)
-#define DMA_IFCR_CGIF4                  (0x01U << DMA_IFCR_CGIF4_Pos)           ///< Channel 4 Global interrupt clear
-#define DMA_IFCR_CTCIF4_Pos             (13)
-#define DMA_IFCR_CTCIF4                 (0x01U << DMA_IFCR_CTCIF4_Pos)          ///< Channel 4 Transfer Complete clear
-#define DMA_IFCR_CHTIF4_Pos             (14)
-#define DMA_IFCR_CHTIF4                 (0x01U << DMA_IFCR_CHTIF4_Pos)          ///< Channel 4 Half Transfer clear
-#define DMA_IFCR_CTEIF4_Pos             (15)
-#define DMA_IFCR_CTEIF4                 (0x01U << DMA_IFCR_CTEIF4_Pos)          ///< Channel 4 Transfer Error clear
-#define DMA_IFCR_CGIF5_Pos              (16)
-#define DMA_IFCR_CGIF5                  (0x01U << DMA_IFCR_CGIF5_Pos)           ///< Channel 5 Global interrupt clear
-#define DMA_IFCR_CTCIF5_Pos             (17)
-#define DMA_IFCR_CTCIF5                 (0x01U << DMA_IFCR_CTCIF5_Pos)          ///< Channel 5 Transfer Complete clear
-#define DMA_IFCR_CHTIF5_Pos             (18)
-#define DMA_IFCR_CHTIF5                 (0x01U << DMA_IFCR_CHTIF5_Pos)          ///< Channel 5 Half Transfer clear
-#define DMA_IFCR_CTEIF5_Pos             (19)
-#define DMA_IFCR_CTEIF5                 (0x01U << DMA_IFCR_CTEIF5_Pos)          ///< Channel 5 Transfer Error clear
-
-#define DMA_IFCR_CGIF6_Pos              (20)
-#define DMA_IFCR_CGIF6                  (0x01U << DMA_IFCR_CGIF6_Pos)           ///< Channel 6 Global interrupt clear
-#define DMA_IFCR_CTCIF6_Pos             (21)
-#define DMA_IFCR_CTCIF6                 (0x01U << DMA_IFCR_CTCIF6_Pos)          ///< Channel 6 Transfer Complete clear
-#define DMA_IFCR_CHTIF6_Pos             (22)
-#define DMA_IFCR_CHTIF6                 (0x01U << DMA_IFCR_CHTIF6_Pos)          ///< Channel 6 Half Transfer clear
-#define DMA_IFCR_CTEIF6_Pos             (23)
-#define DMA_IFCR_CTEIF6                 (0x01U << DMA_IFCR_CTEIF6_Pos)          ///< Channel 6 Transfer Error clear
-#define DMA_IFCR_CGIF7_Pos              (24)
-#define DMA_IFCR_CGIF7                  (0x01U << DMA_IFCR_CGIF7_Pos)           ///< Channel 7 Global interrupt clear
-#define DMA_IFCR_CTCIF7_Pos             (25)
-#define DMA_IFCR_CTCIF7                 (0x01U << DMA_IFCR_CTCIF7_Pos)          ///< Channel 7 Transfer Complete clear
-#define DMA_IFCR_CHTIF7_Pos             (26)
-#define DMA_IFCR_CHTIF7                 (0x01U << DMA_IFCR_CHTIF7_Pos)          ///< Channel 7 Half Transfer clear
-#define DMA_IFCR_CTEIF7_Pos             (27)
-#define DMA_IFCR_CTEIF7                 (0x01U << DMA_IFCR_CTEIF7_Pos)          ///< Channel 7 Transfer Error clear
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA_CCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DMA_CCR_EN_Pos                  (0)
-#define DMA_CCR_EN                      (0x01U << DMA_CCR_EN_Pos)               ///< Channel enabl
-#define DMA_CCR_TCIE_Pos                (1)
-#define DMA_CCR_TCIE                    (0x01U << DMA_CCR_TCIE_Pos)             ///< Transfer complete interrupt enable
-#define DMA_CCR_HTIE_Pos                (2)
-#define DMA_CCR_HTIE                    (0x01U << DMA_CCR_HTIE_Pos)             ///< Half Transfer interrupt enable
-#define DMA_CCR_TEIE_Pos                (3)
-#define DMA_CCR_TEIE                    (0x01U << DMA_CCR_TEIE_Pos)             ///< Transfer error interrupt enable
-#define DMA_CCR_DIR_Pos                 (4)
-#define DMA_CCR_DIR                     (0x01U << DMA_CCR_DIR_Pos)              ///< Data transfer direction
-#define DMA_CCR_CIRC_Pos                (5)
-#define DMA_CCR_CIRC                    (0x01U << DMA_CCR_CIRC_Pos)             ///< Circular mode
-#define DMA_CCR_PINC_Pos                (6)
-#define DMA_CCR_PINC                    (0x01U << DMA_CCR_PINC_Pos)             ///< Peripheral increment mode
-#define DMA_CCR_MINC_Pos                (7)
-#define DMA_CCR_MINC                    (0x01U << DMA_CCR_MINC_Pos)             ///< Memory increment mode
-
-#define DMA_CCR_PSIZE_Pos               (8)
-#define DMA_CCR_PSIZE                   (0x03U << DMA_CCR_PSIZE_Pos)            ///< PSIZE[1:0] bits (Peripheral size)
-#define DMA_CCR_PSIZE_0                 (0x01U << DMA_CCR_PSIZE_Pos)            ///< Bit0
-#define DMA_CCR_PSIZE_1                 (0x02U << DMA_CCR_PSIZE_Pos)            ///< Bit1
-
-#define DMA_CCR_PSIZE_BYTE              (0x00U << DMA_CCR_PSIZE_Pos)            ///< DMA Peripheral Data Size Byte
-#define DMA_CCR_PSIZE_HALFWORD          (0x01U << DMA_CCR_PSIZE_Pos)            ///< DMA Peripheral Data Size HalfWord
-#define DMA_CCR_PSIZE_WORD              (0x02U << DMA_CCR_PSIZE_Pos)            ///< DMA Peripheral Data Size Word
-
-#define DMA_CCR_MSIZE_Pos               (10)
-#define DMA_CCR_MSIZE                   (0x03U << DMA_CCR_MSIZE_Pos)            ///< MSIZE[1:0] bits (Memory size)
-#define DMA_CCR_MSIZE_0                 (0x01U << DMA_CCR_MSIZE_Pos)            ///< Bit0
-#define DMA_CCR_MSIZE_1                 (0x02U << DMA_CCR_MSIZE_Pos)            ///< Bit1
-
-#define DMA_CCR_MSIZE_BYTE              (0x00U << DMA_CCR_MSIZE_Pos)            ///< DMA Memory Data Size Byte
-#define DMA_CCR_MSIZE_HALFWORD          (0x01U << DMA_CCR_MSIZE_Pos)            ///< DMA Memory Data Size HalfWord
-#define DMA_CCR_MSIZE_WORD              (0x02U << DMA_CCR_MSIZE_Pos)            ///< DMA Memory Data Size Word
-
-#define DMA_CCR_PL_Pos                  (12)
-#define DMA_CCR_PL                      (0x03U << DMA_CCR_PL_Pos)               ///< PL[1:0] bits(Channel Priority level)
-#define DMA_CCR_PL_0                    (0x01U << DMA_CCR_PL_Pos)               ///< Bit0
-#define DMA_CCR_PL_1                    (0x02U << DMA_CCR_PL_Pos)               ///< Bit1
-
-#define DMA_CCR_PL_Low                  (0x00U << DMA_CCR_PL_Pos)               ///< DMA Priority Low
-#define DMA_CCR_PL_Medium               (0x01U << DMA_CCR_PL_Pos)               ///< DMA Priority Medium
-#define DMA_CCR_PL_High                 (0x02U << DMA_CCR_PL_Pos)               ///< DMA Priority High
-#define DMA_CCR_PL_VeryHigh             (0x03U << DMA_CCR_PL_Pos)               ///< DMA Priority VeryHigh
-#define DMA_CCR_M2M_Pos                 (14)
-#define DMA_CCR_M2M                     (0x01U << DMA_CCR_M2M_Pos)              ///< Memory to memory mode
-
-#define DMA_CCR_ARE_Pos                 (15)
-#define DMA_CCR_ARE                     (0x01U << DMA_CCR_ARE_Pos)              ///< Auto-Reload Enable bit
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA_CNDTR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DMA_CNDTR_NDT_Pos               (0)
-#define DMA_CNDTR_NDT                   (0xFFFFU << DMA_CNDTR_NDT_Pos)          ///< Number of data to Transfer
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA_CPAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DMA_CPAR_PA_Pos                 (0)
-#define DMA_CPAR_PA                     (0xFFFFFFFFU << DMA_CPAR_PA_Pos)        ///< Peripheral Address
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief DMA_CMAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define DMA_CMAR_MA_Pos                 (0)
-#define DMA_CMAR_MA                     (0xFFFFFFFFU << DMA_CMAR_MA_Pos)        ///< Peripheral Address
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h
deleted file mode 100644
index 61a0d25c2..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_eth.h
+++ /dev/null
@@ -1,730 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_iwdg.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_ETH_H
-#define __REG_ETH_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-#include "reg_common.h"
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief IWDG Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_BASE                       (AHBPERIPH_BASE + 0x8000)              ///< Base Address: 0x40028000
-
-
-#define ETH                             ((ETH_TypeDef*) ETH_BASE)
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 MACCR;                                                        ///< configuration register                         offset 0x0000
-    __IO u32 MACFFR;                                                       ///< frame filter register                          offset 0x0004
-    __IO u32 MACHTHR;                                                      ///< Hash list high register                        offset 0x0008
-    __IO u32 MACHTLR;                                                      ///< Hash list low register                         offset 0x000C
-    __IO u32 MACMIIAR;                                                     ///< MII address register                           offset 0x0010
-    __IO u32 MACMIIDR;                                                     ///< MII data register                              offset 0x0014
-    __IO u32 MACFCR;                                                       ///< flow control register                          offset 0x0018
-    __IO u32 MACVLANTR;                                                    ///< VLAN label register                            offset 0x001C
-    __IO u32 RESERVEDX0020[2];                                             /// 0x0020 ~ 0x0024
-    __IO u32 MACRWUFFR;                                                    /// 0x0028
-    __IO u32 MACPMTCSR;                                                    /// 0x002C
-    __IO u32 RESERVEDX0030[4];                                             /// 0x0030 ~ 0x003C
-    __IO u32 MACA0HR;                                                      ///< address 0 high register                        offset 0x0040
-    __IO u32 MACA0LR;                                                      ///< address 0 low register                         offset 0x0044
-    __IO u32 MACA1HR;                                                      ///< address 1 high register                        offset 0x0048
-    __IO u32 MACA1LR;                                                      ///< address 1 low register                         offset 0x004C
-    __IO u32 MACA2HR;                                                      ///< address 2 high register                        offset 0x0050
-    __IO u32 MACA2LR;                                                      ///< address 2 low register                         offset 0x0054
-    __IO u32 MACA3HR;                                                      ///< address 3 high register                        offset 0x0058
-    __IO u32 MACA3LR;                                                      ///< address 3 low register                         offset 0x005C
-    __IO u32 MACA4HR;                                                      ///< address 4 high register                        offset 0x0060
-    __IO u32 MACA4LR;                                                      ///< address 4 low register                         offset 0x0064
-    __IO u32 MACA5HR;                                                      ///< address 5 high register                        offset 0x0068
-    __IO u32 MACA5LR;                                                      ///< address 5 low register                         offset 0x006C
-    __IO u32 MACA6HR;                                                      ///< address 6 high register                        offset 0x0070
-    __IO u32 MACA6LR;                                                      ///< address 6 low register                         offset 0x0074
-    __IO u32 MACA7HR;                                                      ///< address 7 high register                        offset 0x0078
-    __IO u32 MACA7LR;                                                      ///< address 7 low register                         offset 0x007C
-    __IO u32 MACA8HR;                                                      ///< address 8 high register                        offset 0x0080
-    __IO u32 MACA8LR;                                                      ///< address 8 low register                         offset 0x0084
-    __IO u32 MACA9HR;                                                      ///< address 9 high register                        offset 0x0088
-    __IO u32 MACA9LR;                                                      ///< address 9 low register                         offset 0x008C
-    __IO u32 MACA10HR;                                                     ///< address 10 high register                        offset 0x0090
-    __IO u32 MACA10LR;                                                     ///< address 10 low register                         offset 0x0094
-    __IO u32 MACA11HR;                                                     ///< address 11 high register                        offset 0x0098
-    __IO u32 MACA11LR;                                                     ///< address 11 low register                         offset 0x009C
-    __IO u32 MACA12HR;                                                     ///< address 12 high register                        offset 0x00A0
-    __IO u32 MACA12LR;                                                     ///< address 12 low register                         offset 0x00A4
-    __IO u32 MACA13HR;                                                     ///< address 13 high register                        offset 0x00A8
-    __IO u32 MACA13LR;                                                     ///< address 13 low register                         offset 0x00AC
-    __IO u32 MACA14HR;                                                     ///< address 14 high register                        offset 0x00B0
-    __IO u32 MACA14LR;                                                     ///< address 14 low register                         offset 0x00B4
-    __IO u32 MACA15HR;                                                     ///< address 15 high register                        offset 0x00B8
-    __IO u32 MACA15LR;                                                     ///< address 15 low register                         offset 0x00BC
-    __IO u32 MACANCR;                                                      ///< Automatic negotiation control register           offset 0x00C0
-    __IO u32 MACANSR;                                                      ///< Automatic negotiation of the status register     offset 0x00C4
-    __IO u32 MACANAR;                                                      ///< Automatic negotiation of broadcast registers     offset 0x00C8
-    __IO u32 MACANLPAR;                                                    ///< Automatic negotiation of link partner capability register  offset 0x00CC
-    __IO u32 MACANER;                                                      ///< Automatic negotiation of extension registers     offset 0x00D0
-    __IO u32 MACTBIER;                                                     ///< Ten - place interface extension register         offset 0x00D4
-    __IO u32 MACMIISR;                                                     ///< MII status register                              offset 0x00D8
-    __IO u32 RESERVEDX00DC[9];                                             ///<                                                  offset 0x00DC ~ 0x00FC
-    __IO u32 MMCCR;                                                        ///< MMC controls registers  offset 0x0100
-    __IO u32 MMCRIR;                                                       ///< The MMC receives the interrupt register  offset 0x0104
-    __IO u32 MMCTIR;                                                       ///< The MMC sends the interrupt register  offset 0x0108
-    __IO u32 MMCRIMR;                                                      ///< The MMC receives the interrupt mask register  offset 0x010C
-    __IO u32 MMCTIMR;                                                      ///< MMC sends interrupt masking registers  offset 0x0110
-    __IO u32 RESERVEDX0114[14];                                            ///<   offset 0x0114 ~ 0x0148
-    __IO u32 MMCTGFSCCR;                                                   ///< A good frame counter register that MMC sends after a single conflict  offset 0x014C
-    __IO u32 MMCTGFMSCCR;                                                  ///< A good frame counter register that MMC sends after multiple collisions  offset 0x0150
-    __IO u32 RESERVEDX0154[5];                                             ///<   offset 0x0154 ~ 0x0164
-    __IO u32 MMCTGFCR;                                                     ///< Good frame counter register sent by MMC  offset 0x0168
-    __IO u32 RESERVEDX016C[10];                                            ///<   offset 0x016C ~ 0x0190
-    __IO u32 MMCRFCECR;                                                    ///< Ethernet MMC with CRC error counter register receives frame register  offset 0x0194
-    __IO u32 MMCRFAECR;                                                    ///< Ethernet MMC receives frames with alignment error counter registers  offset 0x0198
-    __IO u32 RESERVEDX019C[10];                                            ///<   offset 0x019C ~ 0x01C0
-    __IO u32 MMCRGUFCR;                                                    ///< Good unicast frame counter register received by MMC  offset 0x01C4
-    __IO u32 RESERVEDx01C8[910];                                           ///<   offset 0x01C8 ~ 0x0FFC
-    __IO u32 DMABMR;                                                       ///< Bus mode register                               offset 0x1000
-    __IO u32 DMATPDR;                                                      ///< DMA sends the polling request register          offset 0x1004
-    __IO u32 DMARPDR;                                                      ///< DMA receives the polling request register       offset 0x1008
-    __IO u32 DMARDLAR;                                                     ///< DMA receives a list of descriptor addresses     offset 0x100C
-    __IO u32 DMATDLAR;                                                     ///< DMA sends the descriptor list address           offset 0x1010
-    __IO u32 DMASR;                                                        ///< DMA status register                             offset 0x1014
-    __IO u32 DMAOMR;                                                       ///< DMA working mode register                       offset 0x1018
-    __IO u32 DMAIER;                                                       ///< DMA interrupt enablement register               offset 0x101C
-    __IO u32 DMAMFBOCR;                                                    ///< DMA lost frames and cache overflow counter registers offset 0x1020
-    __IO u32 DMARSWTR;                                                     /// 0x1024
-    __IO u32 RESERVEDX1028[8];                                             /// 0x1028 ~ 0x1044
-    __IO u32 DMACHTDR;                                                     /// 0x1048
-    __IO u32 DMACHRDR;                                                     /// 0x104C
-    __IO u32 DMACHTBAR;                                                    ///< DMA is currently sending the cache address register  offset 0x1050
-    __IO u32 DMACHRBAR;                                                    ///< DMA currently receives the cache address register    offset 0x1054
-} ETH_TypeDef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACCR_WD_Pos                (23)
-#define ETH_MACCR_WD                    (0x01U << ETH_MACCR_WD_Pos)                  ///< Watchdog disable
-#define ETH_MACCR_JD_Pos                (22)
-#define ETH_MACCR_JD                    (0x01U << ETH_MACCR_JD_Pos)                  ///< Jabber disable
-#define ETH_MACCR_FBE_Pos               (21)
-#define ETH_MACCR_FBE                   (0x01U << ETH_MACCR_FBE_Pos)                 ///< Frame Burst Enable
-#define ETH_MACCR_JE_Pos                (20)
-#define ETH_MACCR_JE                    (0x01U << ETH_MACCR_JE_Pos)                  ///< Jumbo Frame Enable
-#define ETH_MACCR_IFG_Pos               (17)                                         ///< Inter-frame gap
-#define ETH_MACCR_IFG_96Bit             (0x00U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 96Bit
-#define ETH_MACCR_IFG_88Bit             (0x01U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 88Bit
-#define ETH_MACCR_IFG_80Bit             (0x02U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 80Bit
-#define ETH_MACCR_IFG_72Bit             (0x03U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 72Bit
-#define ETH_MACCR_IFG_64Bit             (0x04U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 64Bit
-#define ETH_MACCR_IFG_56Bit             (0x05U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 56Bit
-#define ETH_MACCR_IFG_48Bit             (0x06U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 48Bit
-#define ETH_MACCR_IFG_40Bit             (0x07U << ETH_MACCR_IFG_Pos)                 ///< Minimum IFG between frames during transmission is 40Bit
-#define ETH_MACCR_FES_Pos               (14)
-#define ETH_MACCR_FES                   (0x01U << ETH_MACCR_FES_Pos)                  ///< Fast ethernet speed
-#define ETH_MACCR_ROD_Pos               (13)
-#define ETH_MACCR_ROD                   (0x01U << ETH_MACCR_ROD_Pos)                  ///< Receive own disable
-#define ETH_MACCR_LM_Pos                (12)
-#define ETH_MACCR_LM                    (0x01U << ETH_MACCR_LM_Pos)                   ///< loopback mode
-#define ETH_MACCR_DM_Pos                (11)
-#define ETH_MACCR_DM                    (0x01U << ETH_MACCR_DM_Pos)                   ///< Duplex mode
-#define ETH_MACCR_IPCO_Pos              (10)
-#define ETH_MACCR_IPCO                  (0x01U << ETH_MACCR_IPCO_Pos)                 ///< IP Checksum offload
-#define ETH_MACCR_RD_Pos                (9)
-#define ETH_MACCR_RD                    (0x01U << ETH_MACCR_RD_Pos)                   ///< Retry disable
-#define ETH_MACCR_APCS_Pos              (8)
-#define ETH_MACCR_APCS                  (0x01U << ETH_MACCR_APCS_Pos)                 ///< Automatic Pad/CRC stripping
-#define ETH_MACCR_BL_Pos                (5)                                           ///< Back-off limit: random integer number (r) of slot time delays before rescheduling a transmission attempt during retries after a collision: 0 =< r <2^k
-#define ETH_MACCR_BL_10                 (0x00U << ETH_MACCR_BL_Pos)                   ///< k = min (n, 10)
-#define ETH_MACCR_BL_8                  (0x01U << ETH_MACCR_BL_Pos)                   ///< k = min (n, 8)
-#define ETH_MACCR_BL_4                  (0x02U << ETH_MACCR_BL_Pos)                   ///< k = min (n, 4)
-#define ETH_MACCR_BL_1                  (0x03U << ETH_MACCR_BL_Pos)                   ///< k = min (n, 1)
-#define ETH_MACCR_DC_Pos                (4)
-#define ETH_MACCR_DC                    (0x01U << ETH_MACCR_DC_Pos)                  ///< Defferal check
-#define ETH_MACCR_TE_Pos                (3)
-#define ETH_MACCR_TE                    (0x01U << ETH_MACCR_TE_Pos)                  ///< Transmitter enable
-#define ETH_MACCR_RE_Pos                (2)
-#define ETH_MACCR_RE                    (0x01U << ETH_MACCR_RE_Pos)                  ///< Receiver enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACFFR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACFFR_RA_Pos               (31)
-#define ETH_MACFFR_RA                   (0x01U << ETH_MACFFR_RA_Pos)                  ///< Receive all 
-
-#define ETH_MACFFR_SAF_Pos              (9)
-#define ETH_MACFFR_SAF                  (0x01U << ETH_MACFFR_SAF_Pos)                  ///< Source address filter enable 
-#define ETH_MACFFR_SAIF_Pos             (8)
-#define ETH_MACFFR_SAIF                 (0x01U << ETH_MACFFR_SAIF_Pos)                 ///< SA inverse filtering 
-#define ETH_MACFFR_PCF_Pos              (6)
-#define ETH_MACFFR_PCF                  (0x03U << ETH_MACFFR_PCF_Pos)                  ///< Pass control frames: 3 cases 
-#define ETH_MACFFR_PCF_BlockAll         (0x01U << ETH_MACFFR_PCF_Pos)                  ///< MAC filters all control frames from reaching the application 
-#define ETH_MACFFR_PCF_ForwardAll       (0x02U << ETH_MACFFR_PCF_Pos)                  ///< MAC forwards all control frames to application even if they fail the Address Filter 
-#define ETH_MACFFR_PCF_ForwardPassedAddrFilter (0x03U << ETH_MACFFR_PCF_Pos)           ///< MAC forwards control frames that pass the Address Filter. 
-#define ETH_MACFFR_BFD_Pos              (5)
-#define ETH_MACFFR_BFD                  (0x01U << ETH_MACFFR_BFD_Pos)                  ///< Broadcast frame disable 
-#define ETH_MACFFR_PAM_Pos              (4)
-#define ETH_MACFFR_PAM                  (0x01U << ETH_MACFFR_PAM_Pos)                  ///< Pass all mutlicast 
-#define ETH_MACFFR_DAIF_Pos             (3)
-#define ETH_MACFFR_DAIF                 (0x01U << ETH_MACFFR_DAIF_Pos)                 ///< DA Inverse filtering 
-#define ETH_MACFFR_HM_Pos               (2)
-#define ETH_MACFFR_HM                   (0x01U << ETH_MACFFR_HM_Pos)                  ///< Hash multicast 
-#define ETH_MACFFR_HU_Pos               (1)
-#define ETH_MACFFR_HU                   (0x01U << ETH_MACFFR_HU_Pos)                  ///< Hash unicast 
-#define ETH_MACFFR_PM_Pos               (0)
-#define ETH_MACFFR_PM                   (0x01U << ETH_MACFFR_PM_Pos)                  ///< Promiscuous mode 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACHTHR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACHTHR_HTH                 (0xFFFFFFFFU)                                 ///< Hash table high
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACHTLR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACHTLR_HTL                 (0xFFFFFFFFU)                                ///< Hash table low
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACMIIAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACMIIAR_PA_Pos             (11)
-#define ETH_MACMIIAR_PA                 (0x1FU << ETH_MACMIIAR_PA_Pos)              ///< Physical layer address
-#define ETH_MACMIIAR_MR_Pos             (6)
-#define ETH_MACMIIAR_MR                 (0x1FU << ETH_MACMIIAR_MR_Pos)              ///< MII register in the selected PHY
-#define ETH_MACMIIAR_CR_Pos             (2)
-#define ETH_MACMIIAR_CR                 (0x07U << ETH_MACMIIAR_CR_Pos)              ///< CR clock range: 6 cases
-#define ETH_MACMIIAR_CR_Div42           (0x00U << ETH_MACMIIAR_CR_Pos)              ///< HCLK:60-100 MHz; MDC clock= HCLK/42
-#define ETH_MACMIIAR_CR_Div62           (0x01U << ETH_MACMIIAR_CR_Pos)              ///< HCLK:100-150 MHz; MDC clock= HCLK/62
-#define ETH_MACMIIAR_CR_Div16           (0x02U << ETH_MACMIIAR_CR_Pos)              ///< HCLK:20-35 MHz; MDC clock= HCLK/16
-#define ETH_MACMIIAR_CR_Div26           (0x03U << ETH_MACMIIAR_CR_Pos)              ///< HCLK:35-60 MHz; MDC clock= HCLK/26
-#define ETH_MACMIIAR_CR_Div102          (0x04U << ETH_MACMIIAR_CR_Pos)              ///< HCLK:150-168 MHz; MDC clock= HCLK/102
-#define ETH_MACMIIAR_MW_Pos             (1)
-#define ETH_MACMIIAR_MW                 (0x01U << ETH_MACMIIAR_MW_Pos)              ///< MII write
-#define ETH_MACMIIAR_MB_Pos             (0)
-#define ETH_MACMIIAR_MB                 (0x01U << ETH_MACMIIAR_MB_Pos)              ///< MII busy
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACMIIDR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACMIIDR_MD                 (0x0000FFFFU)                               ///< MII data: read/write data from/to PHY 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACFCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACFCR_PT_Pos               (16)
-#define ETH_MACFCR_PT                   ((u32)0xFFFF << ETH_MACFCR_PT_Pos) ///< Pause time
-#define ETH_MACFCR_PLT_Pos              (4)
-#define ETH_MACFCR_PLT                  (0x03U << ETH_MACFCR_PLT_Pos)                  ///< Pause low threshold: 4 cases 
-#define ETH_MACFCR_PLT_Minus4           (0x00U << ETH_MACFCR_PLT_Pos)                  ///< Pause time minus 4 slot times 
-#define ETH_MACFCR_PLT_Minus28          (0x01U << ETH_MACFCR_PLT_Pos)                  ///< Pause time minus 28 slot times 
-#define ETH_MACFCR_PLT_Minus144         (0x02U << ETH_MACFCR_PLT_Pos)                  ///< Pause time minus 144 slot times 
-#define ETH_MACFCR_PLT_Minus256         (0x03U << ETH_MACFCR_PLT_Pos)                  ///< Pause time minus 256 slot times 
-#define ETH_MACFCR_UPFD_Pos             (3)
-#define ETH_MACFCR_UPFD                 (0x01U << ETH_MACFCR_UPFD_Pos)                  ///< Unicast pause frame detect 
-#define ETH_MACFCR_RFCE_Pos             (2)
-#define ETH_MACFCR_RFCE                 (0x01U << ETH_MACFCR_RFCE_Pos)                  ///< Receive flow control enable 
-#define ETH_MACFCR_TFCE_Pos             (1)
-#define ETH_MACFCR_TFCE                 (0x01U << ETH_MACFCR_TFCE_Pos)                  ///< Transmit flow control enable 
-#define ETH_MACFCR_FCBBPA_Pos           (0)
-#define ETH_MACFCR_FCBBPA               (0x01U << ETH_MACFCR_FCBBPA_Pos)                ///< Flow control busy/backpressure activate 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACVLANTR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACVLANTR_VLANTI            (0x0000FFFFU)                                  ///< VLAN tag identifier (for receive frames) 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACRWUFFR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACRWUFFR_D                 (0xFFFFFFFFU)                                  ///< Wake-up frame filter register data 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACPMTCSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACPMTCSR_WFFRPR_Pos        (31)                                     ///< Wake-Up Frame Filter Register Pointer Reset
-#define ETH_MACPMTCSR_WFFRPR            (0x01U << ETH_MACPMTCSR_WFFRPR_Pos)                  ///< Wake-Up Frame Filter Register Pointer Reset
-#define ETH_MACPMTCSR_GU_Pos            (9)
-#define ETH_MACPMTCSR_GU                (0x01U << ETH_MACPMTCSR_GU_Pos)                   ///< Global Unicast 
-#define ETH_MACPMTCSR_WFR_Pos           (6)
-#define ETH_MACPMTCSR_WFR               (0x01U << ETH_MACPMTCSR_WFR_Pos)                  ///< Wake-Up Frame Received 
-#define ETH_MACPMTCSR_MPR_Pos           (5)
-#define ETH_MACPMTCSR_MPR               (0x01U << ETH_MACPMTCSR_MPR_Pos)                  ///< Magic Packet Received 
-#define ETH_MACPMTCSR_WFE_Pos           (2)
-#define ETH_MACPMTCSR_WFE               (0x01U << ETH_MACPMTCSR_WFE_Pos)                  ///< Wake-Up Frame Enable 
-#define ETH_MACPMTCSR_MPE_Pos           (1)
-#define ETH_MACPMTCSR_MPE               (0x01U << ETH_MACPMTCSR_MPE_Pos)                  ///< Magic Packet Enable 
-#define ETH_MACPMTCSR_PD_Pos            (0)
-#define ETH_MACPMTCSR_PD                (0x01U << ETH_MACPMTCSR_PD_Pos)                  ///< Power Down 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACA0HR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACA0HR_MACA0H              ((u32)0x0000FFFF)                  ///< MAC address0 high 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACA0LR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACA0LR_MACA0L              ((u32)0xFFFFFFFF)                  ///< MAC address0 low 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACA1HR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACA1HR_AE_Pos              (31)
-#define ETH_MACA1HR_AE                  (0x01U << ETH_MACA1HR_AE_Pos)                  ///< Address enable 
-#define ETH_MACA1HR_SA_Pos              (30)
-#define ETH_MACA1HR_SA                  (0x01U << ETH_MACA1HR_SA_Pos)                  ///< Source address 
-#define ETH_MACA1HR_MBC_Pos             (24)
-#define ETH_MACA1HR_MBC                 (0x3FU << ETH_MACA1HR_MBC_Pos)                  ///< Mask byte control: bits to mask for comparison of the MAC Address bytes 
-#define ETH_MACA1HR_MBC_HBits15_8       (0x20U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address high reg bits [15:8] 
-#define ETH_MACA1HR_MBC_HBits7_0        (0x10U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address high reg bits [7:0] 
-#define ETH_MACA1HR_MBC_LBits31_24      (0x08U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [31:24] 
-#define ETH_MACA1HR_MBC_LBits23_16      (0x04U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [23:16] 
-#define ETH_MACA1HR_MBC_LBits15_8       (0x02U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [15:8] 
-#define ETH_MACA1HR_MBC_LBits7_0        (0x00U << ETH_MACA1HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [7:0] 
-#define ETH_MACA1HR_MACA1H_Pos          (0)
-#define ETH_MACA1HR_MACA1H              (0x0000FFFFU << ETH_MACA1HR_MACA1H_Pos)         ///< MAC address1 high 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACA1LR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACA1LR_MACA1L              (0xFFFFFFFFU)                                  ///< MAC address1 low 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACA2HR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACA2HR_AE_Pos              (31)
-#define ETH_MACA2HR_AE                  (0x01U << ETH_MACA2HR_AE_Pos)                  ///< Address enable 
-#define ETH_MACA2HR_SA_Pos              (30)
-#define ETH_MACA2HR_SA                  (0x01U << ETH_MACA2HR_SA_Pos)                  ///< Source address 
-#define ETH_MACA2HR_MBC_Pos             (24)
-#define ETH_MACA2HR_MBC                 (0x3FU << ETH_MACA2HR_MBC_Pos)                  ///< Mask byte control: bits to mask for comparison of the MAC Address bytes 
-#define ETH_MACA2HR_MBC_HBits15_8       (0x20U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address high reg bits [15:8] 
-#define ETH_MACA2HR_MBC_HBits7_0        (0x10U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address high reg bits [7:0] 
-#define ETH_MACA2HR_MBC_LBits31_24      (0x08U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [31:24] 
-#define ETH_MACA2HR_MBC_LBits23_16      (0x04U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [23:16] 
-#define ETH_MACA2HR_MBC_LBits15_8       (0x02U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [15:8] 
-#define ETH_MACA2HR_MBC_LBits7_0        (0x00U << ETH_MACA2HR_MBC_Pos)                  ///< Mask MAC Address low reg bits [7:0] 
-#define ETH_MACA2HR_MACA2H_Pos          (0)
-#define ETH_MACA2HR_MACA2H              (0x0000FFFFU << ETH_MACA2HR_MACA2H_Pos)         ///< MAC address2 high 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACA2LR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACA2LR_MACA2L              (0xFFFFFFFFU)                                  ///< MAC address2 low 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACANCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACANCR_LR_Pos              (17)
-#define ETH_MACANCR_LR                  (0x01U << ETH_MACANCR_LR_Pos)                   ///< Lock to Reference
-#define ETH_MACANCR_ECD_Pos             (16)
-#define ETH_MACANCR_ECD                 (0x01U << ETH_MACANCR_ECD_Pos)                  ///< Enable Comma Detect 
-#define ETH_MACANCR_ELE_Pos             (14)
-#define ETH_MACANCR_ELE                 (0x01U << ETH_MACANCR_ELE_Pos)                  ///< External Loopback Enable
-#define ETH_MACANCR_ANE_Pos             (12)
-#define ETH_MACANCR_ANE                 (0x01U << ETH_MACANCR_ANE_Pos)                  ///< Auto-Negotiation Enable 
-#define ETH_MACANCR_RAN_Pos             (9)
-#define ETH_MACANCR_RAN                 (0x01U << ETH_MACANCR_RAN_Pos)                  ///< Restart Auto-Negotiation 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACANSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACANSR_ES_Pos              (8)
-#define ETH_MACANSR_ES                  (0x01U << ETH_MACANSR_ES_Pos)                   ///< Extended Status
-#define ETH_MACANSR_ANC_Pos             (5)
-#define ETH_MACANSR_ANC                 (0x01U << ETH_MACANSR_ANC_Pos)                  ///< Auto-Negotiation Complete 
-#define ETH_MACANSR_ANA_Pos             (3)
-#define ETH_MACANSR_ANA                 (0x01U << ETH_MACANSR_ANA_Pos)                  ///< Auto-Negotiation Ability
-#define ETH_MACANSR_LS_Pos              (2)
-#define ETH_MACANSR_LS                  (0x01U << ETH_MACANSR_LS_Pos)                  ///< Link Status 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACANAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACANAR_NP_Pos              (15)
-#define ETH_MACANAR_NP                  (0x01U << ETH_MACANAR_NP_Pos)                   ///< Next Page Support
-#define ETH_MACANAR_RFE_Pos             (12)
-#define ETH_MACANAR_RFE                 (0x01U << ETH_MACANAR_RFE_Pos)                  ///< Remote Fault Encoding
-#define ETH_MACANAR_PSE_Pos             (7)
-#define ETH_MACANAR_PSE                 (0x01U << ETH_MACANAR_PSE_Pos)                  ///< Pause Encoding
-#define ETH_MACANAR_HD_Pos              (6)
-#define ETH_MACANAR_HD                  (0x01U << ETH_MACANAR_HD_Pos)                  ///< support Half-Duplex 
-#define ETH_MACANAR_FD_Pos              (5)
-#define ETH_MACANAR_FD                  (0x01U << ETH_MACANAR_FD_Pos)                  ///< support Full-Durplex 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACANLPAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACANLPAR_NP_Pos              (15)
-#define ETH_MACANLPAR_NP                  (0x01U << ETH_MACANLPAR_NP_Pos)                   ///< Next Page Support
-#define ETH_MACANLPAR_ACK_Pos             (14)
-#define ETH_MACANLPAR_ACK                 (0x01U << ETH_MACANLPAR_ACK_Pos)                ///< Acknowledge
-#define ETH_MACANLPAR_RFE_Pos             (12)
-#define ETH_MACANLPAR_RFE                 (0x01U << ETH_MACANLPAR_RFE_Pos)                  ///< Remote Fault Encoding
-#define ETH_MACANLPAR_PSE_Pos             (7)
-#define ETH_MACANLPAR_PSE                 (0x01U << ETH_MACANLPAR_PSE_Pos)                  ///< Pause Encoding
-#define ETH_MACANLPAR_HD_Pos              (6)
-#define ETH_MACANLPAR_HD                  (0x01U << ETH_MACANLPAR_HD_Pos)                  ///< support Half-Duplex 
-#define ETH_MACANLPAR_FD_Pos              (5)
-#define ETH_MACANLPAR_FD                  (0x01U << ETH_MACANLPAR_FD_Pos)                  ///< support Full-Durplex 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACANER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACANER_NPA_Pos              (2)
-#define ETH_MACANER_NPA                  (0x01U << ETH_MACANER_NPA_Pos)                   ///< Next Page Ability
-#define ETH_MACANER_NPR_Pos              (1)
-#define ETH_MACANER_NPR                  (0x01U << ETH_MACANER_NPR_Pos)                   ///< New Page Received
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACTBIER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACTBIER_GFD_Pos              (15)
-#define ETH_MACTBIER_GFD                  (0x01U << ETH_MACTBIER_GFD_Pos)                   ///< 1000BASE-X Full-Duplex Capable
-#define ETH_MACTBIER_GHD_Pos              (14)
-#define ETH_MACTBIER_GHD                  (0x01U << ETH_MACTBIER_GHD_Pos)                   ///< 1000BASE-X Half-Duplex Capable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MACMIISR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MACMIISR_LS_Pos               (3)
-#define ETH_MACMIISR_LS                   (0x01U << ETH_MACMIISR_LS_Pos)                   ///< Link Status
-#define ETH_MACMIISR_LSP_Pos              (1)
-#define ETH_MACMIISR_LSP_2_5              (0x00U << ETH_MACMIISR_LSP_Pos)                   ///< Link Speed 2.5 MHz
-#define ETH_MACMIISR_LSP_25               (0x01U << ETH_MACMIISR_LSP_Pos)                   ///< Link Speed 25  MHz
-#define ETH_MACMIISR_LSP_125              (0x02U << ETH_MACMIISR_LSP_Pos)                   ///< Link Speed 125 MHz
-#define ETH_MACMIISR_LM_Pos               (0)
-#define ETH_MACMIISR_LM                   (0x01U << ETH_MACMIISR_LM_Pos)                   ///< Link Mode : Full-Duplex Capable
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCCR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCCR_MCFHP                 ((u32)0x00000020)                  ///< MMC counter Full-Half preset
-#define ETH_MMCCR_MCP                   ((u32)0x00000010)                  ///< MMC counter preset
-#define ETH_MMCCR_MCF                   ((u32)0x00000008)                  ///< MMC Counter Freeze
-#define ETH_MMCCR_ROR_Pos               (2)
-#define ETH_MMCCR_ROR                   (0x01U << ETH_MMCCR_ROR_Pos)                  ///< Reset on Read 
-#define ETH_MMCCR_CSR_Pos               (1)
-#define ETH_MMCCR_CSR                   (0x01U << ETH_MMCCR_CSR_Pos)                  ///< Counter Stop Rollover 
-#define ETH_MMCCR_CR_Pos                (0)
-#define ETH_MMCCR_CR                    (0x01U << ETH_MMCCR_CR_Pos)                  ///< Counters Reset 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCRIR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCRIR_RGUF_Pos             (17)
-#define ETH_MMCRIR_RGUFS                (0x01U << ETH_MMCRIR_RGUF_Pos)                  ///< Set when Rx good unicast frames counter reaches half the maximum value 
-#define ETH_MMCRIR_RFAES_Pos            (6)
-#define ETH_MMCRIR_RFAES                (0x01U << ETH_MMCRIR_RFAES_Pos)                 ///< Set when Rx alignment error counter reaches half the maximum value 
-#define ETH_MMCRIR_RFCES_Pos            (5)
-#define ETH_MMCRIR_RFCES                (0x01U << ETH_MMCRIR_RFCES_Pos)                 ///< Set when Rx crc error counter reaches half the maximum value 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCTIR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCTIR_TGFS_Pos             (21)
-#define ETH_MMCTIR_TGFS                 (0x01U << ETH_MMCTIR_TGFS_Pos)                  ///< Set when Tx good frame count counter reaches half the maximum value 
-#define ETH_MMCTIR_TGFMSCS_Pos          (15)
-#define ETH_MMCTIR_TGFMSCS              (0x01U << ETH_MMCTIR_TGFMSCS_Pos)               ///< Set when Tx good multi col counter reaches half the maximum value 
-#define ETH_MMCTIR_TGFSCS_Pos           (14)
-#define ETH_MMCTIR_TGFSCS               (0x01U << ETH_MMCTIR_TGFSCS_Pos)                ///< Set when Tx good single col counter reaches half the maximum value 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCRIMR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCRIMR_RGUFM_Pos            (17)
-#define ETH_MMCRIMR_RGUFM                (0x01U << ETH_MMCRIMR_RGUFM_Pos)                ///< Mask the interrupt when Rx good unicast frames counter reaches half the maximum value 
-#define ETH_MMCRIMR_RFAEM_Pos            (6)
-#define ETH_MMCRIMR_RFAEM                (0x01U << ETH_MMCRIMR_RFAEM_Pos)                ///< Mask the interrupt when when Rx alignment error counter reaches half the maximum value 
-#define ETH_MMCRIMR_RFCEM_Pos            (5)
-#define ETH_MMCRIMR_RFCEM                (0x01U << ETH_MMCRIMR_RFCEM_Pos)                ///< Mask the interrupt when Rx crc error counter reaches half the maximum value 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCTIMR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCTIMR_TGFM_Pos             (21)
-#define ETH_MMCTIMR_TGFM                 (0x01U << ETH_MMCTIMR_TGFM_Pos)                  ///< Mask the interrupt when Tx good frame count counter reaches half the maximum value 
-#define ETH_MMCTIMR_TGFMSCM_Pos          (15)
-#define ETH_MMCTIMR_TGFMSCM              (0x01U << ETH_MMCTIMR_TGFMSCM_Pos)               ///< Mask the interrupt when Tx good multi col counter reaches half the maximum value 
-#define ETH_MMCTIMR_TGFSCM_Pos           (14)
-#define ETH_MMCTIMR_TGFSCM               (0x01U << ETH_MMCTIMR_TGFSCM_Pos)                ///< Mask the interrupt when Tx good single col counter reaches half the maximum value 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCTGFSCCR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCTGFSCCR_TGFSCC           (0xFFFFFFFFU)                                     ///< Number of successfully transmitted frames after a single collision in Half-duplex mode. 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCTGFMSCCR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCTGFMSCCR_TGFMSCC         (0xFFFFFFFFU)                                    ///< Number of successfully transmitted frames after more than a single collision in Half-duplex mode. 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCTGFCR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCTGFCR_TGFC               (0xFFFFFFFFU)                                    ///< Number of good frames transmitted. 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCRFCECR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCRFCECR_RFCEC             (0xFFFFFFFFU)                                    ///< Number of frames received with CRC error. 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCRFAECR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCRFAECR_RFAEC             (0xFFFFFFFFU)                                   ///< Number of frames received with alignment (dribble) error 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_MMCRGUFCR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_MMCRGUFCR_RGUFC             (0xFFFFFFFFU)                                  ///< Number of good unicast frames received. 
-/// @brief ETH_DMABMR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMABMR_FB_Pos               (16)
-#define ETH_DMABMR_FB                   (0x01U << ETH_DMABMR_FB_Pos)            ///< Fixed Burst 
-#define ETH_DMABMR_RTPR_Pos             (14)
-#define ETH_DMABMR_RTPR                 (0x03U << ETH_DMABMR_RTPR_Pos)          ///< Rx Tx priority ratio 
-#define ETH_DMABMR_RTPR_1_1             (0x00U << ETH_DMABMR_RTPR_Pos)          ///< Rx Tx priority ratio 
-#define ETH_DMABMR_RTPR_2_1             (0x01U << ETH_DMABMR_RTPR_Pos)          ///< Rx Tx priority ratio 
-#define ETH_DMABMR_RTPR_3_1             (0x02U << ETH_DMABMR_RTPR_Pos)          ///< Rx Tx priority ratio 
-#define ETH_DMABMR_RTPR_4_1             (0x03U << ETH_DMABMR_RTPR_Pos)          ///< Rx Tx priority ratio 
-#define ETH_DMABMR_PBL_Pos              (8)
-#define ETH_DMABMR_PBL                  (0x3FU<< ETH_DMABMR_PBL_Pos)            //< Programmable burst length 
-#define ETH_DMABMR_PBL_1Beat            (0x01U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 
-#define ETH_DMABMR_PBL_2Beat            (0x02U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 
-#define ETH_DMABMR_PBL_4Beat            (0x04U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 
-#define ETH_DMABMR_PBL_8Beat            (0x08U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 
-#define ETH_DMABMR_PBL_16Beat           (0x10U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 
-#define ETH_DMABMR_PBL_32Beat           (0x20U << ETH_DMABMR_PBL_Pos)           ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 
-#define ETH_DMABMR_PBL_4xPBL_4Beat      (0x10001U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 
-#define ETH_DMABMR_PBL_4xPBL_8Beat      (0x10002U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 
-#define ETH_DMABMR_PBL_4xPBL_16Beat     (0x10004U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 
-#define ETH_DMABMR_PBL_4xPBL_32Beat     (0x10008U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 
-#define ETH_DMABMR_PBL_4xPBL_64Beat     (0x10010U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 
-#define ETH_DMABMR_PBL_4xPBL_128Beat    (0x10020U << ETH_DMABMR_PBL_Pos)        ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 
-
-#define ETH_DMABMR_DSL_Pos              (2)
-#define ETH_DMABMR_DSL                  (0x01U << ETH_DMABMR_DSL_Pos)            ///< Descriptor Skip Length 
-#define ETH_DMABMR_DA_Pos               (1)
-#define ETH_DMABMR_DA                   (0x1FU << ETH_DMABMR_DA_Pos)             ///< DMA arbitration scheme 
-#define ETH_DMABMR_SR_Pos               (0)
-#define ETH_DMABMR_SR                   (0x01U << ETH_DMABMR_SR_Pos)             ///< Software reset 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMATPDR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMATPDR_TPD                 (0xFFFFFFFFU)                            ///< Transmit poll demand 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMARPDR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMARPDR_RPD                 (0xFFFFFFFFU)                            ///< Receive poll demand  
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMARDLAR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMARDLAR_SRL                (0xFFFFFFFFU)                            ///< Start of receive list 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMATDLAR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMATDLAR_STL                (0xFFFFFFFFU)                            ///< Start of transmit list 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMASR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMASR_PMTS_Pos              (28)
-#define ETH_DMASR_PMTS                  (0x01U << ETH_DMASR_PMTS_Pos)                ///< PMT status 
-#define ETH_DMASR_MMCS_Pos              (27)
-#define ETH_DMASR_MMCS                  (0x01U << ETH_DMASR_MMCS_Pos)                ///< MMC status 
-#define ETH_DMASR_LIS_Pos               (26)
-#define ETH_DMASR_LIS                   (0x01U << ETH_DMASR_LIS_Pos)                ///< GMAC Line interface Status 
-
-#define ETH_DMASR_EBS_Pos               (23)
-#define ETH_DMASR_EBS                   (0x07U << ETH_DMASR_EBS_Pos)                ///< Error bits status 
-#define ETH_DMASR_EBS_DescAccess        (0x04U << ETH_DMASR_EBS_Pos)                ///< Error bits 0-data buffer, 1-desc. access 
-#define ETH_DMASR_EBS_ReadTransf        (0x02U << ETH_DMASR_EBS_Pos)                ///< Error bits 0-write trnsf, 1-read transfr 
-#define ETH_DMASR_EBS_DataTransfTx      (0x01U << ETH_DMASR_EBS_Pos)                ///< Error bits 0-Rx DMA, 1-Tx DMA 
-#define ETH_DMASR_TPS_Pos               (20)
-#define ETH_DMASR_TPS                   (0x007U << ETH_DMASR_TPS_Pos)                  ///< Transmit process state 
-#define ETH_DMASR_TPS_Stopped           (0x000U << ETH_DMASR_TPS_Pos)                  ///< Stopped - Reset or Stop Tx Command issued  
-#define ETH_DMASR_TPS_Fetching          (0x001U << ETH_DMASR_TPS_Pos)                  ///< Running - fetching the Tx descriptor 
-#define ETH_DMASR_TPS_Waiting           (0x002U << ETH_DMASR_TPS_Pos)                  ///< Running - waiting for status 
-#define ETH_DMASR_TPS_Reading           (0x003U << ETH_DMASR_TPS_Pos)                  ///< Running - reading the data from host memory 
-#define ETH_DMASR_TPS_Suspended         (0x006U << ETH_DMASR_TPS_Pos)                  ///< Suspended - Tx Descriptor unavailabe 
-#define ETH_DMASR_TPS_Closing           (0x007U << ETH_DMASR_TPS_Pos)                  ///< Running - closing Rx descriptor 
-#define ETH_DMASR_RPS_Pos               (17)
-#define ETH_DMASR_RPS                   (0x07U << ETH_DMASR_RPS_Pos)                  ///< Receive process state 
-#define ETH_DMASR_RPS_Stopped           (0x00U << ETH_DMASR_RPS_Pos)                  ///< Stopped - Reset or Stop Rx Command issued 
-#define ETH_DMASR_RPS_Fetching          (0x01U << ETH_DMASR_RPS_Pos)                  ///< Running - fetching the Rx descriptor 
-#define ETH_DMASR_RPS_Waiting           (0x03U << ETH_DMASR_RPS_Pos)                  ///< Running - waiting for packet 
-#define ETH_DMASR_RPS_Suspended         (0x04U << ETH_DMASR_RPS_Pos)                  ///< Suspended - Rx Descriptor unavailable 
-#define ETH_DMASR_RPS_Closing           (0x05U << ETH_DMASR_RPS_Pos)                  ///< Running - closing descriptor 
-#define ETH_DMASR_RPS_Queuing           (0x07U << ETH_DMASR_RPS_Pos)                  ///< Running - queuing the recieve frame into host memory 
-#define ETH_DMASR_NIS_Pos               (16)
-#define ETH_DMASR_NIS                   (0x01U << ETH_DMASR_NIS_Pos )                  ///< Normal interrupt summary 
-#define ETH_DMASR_AIS_Pos               (15)
-#define ETH_DMASR_AIS                   (0x01U << ETH_DMASR_AIS_Pos )                  ///< Abnormal interrupt summary 
-#define ETH_DMASR_ERS_Pos               (14)
-#define ETH_DMASR_ERS                   (0x01U << ETH_DMASR_ERS_Pos )                  ///< Early receive status 
-#define ETH_DMASR_FBES_Pos              (13)
-#define ETH_DMASR_FBES                  (0x01U << ETH_DMASR_FBES_Pos)                  ///< Fatal bus error status 
-#define ETH_DMASR_ETS_Pos               (10)
-#define ETH_DMASR_ETS                   (0x01U << ETH_DMASR_ETS_Pos )                  ///< Early transmit status 
-#define ETH_DMASR_RWTS_Pos              (9)
-#define ETH_DMASR_RWTS                  (0x01U << ETH_DMASR_RWTS_Pos)                  ///< Receive watchdog timeout status 
-#define ETH_DMASR_RPSS_Pos              (8)
-#define ETH_DMASR_RPSS                  (0x01U << ETH_DMASR_RPSS_Pos)                  ///< Receive process stopped status 
-#define ETH_DMASR_RBUS_Pos              (7)
-#define ETH_DMASR_RBUS                  (0x01U << ETH_DMASR_RBUS_Pos)                  ///< Receive buffer unavailable status 
-#define ETH_DMASR_RS_Pos                (6)
-#define ETH_DMASR_RS                    (0x01U << ETH_DMASR_RS_Pos  )                  ///< Receive status 
-#define ETH_DMASR_TUS_Pos               (5)
-#define ETH_DMASR_TUS                   (0x01U << ETH_DMASR_TUS_Pos )                  ///< Transmit underflow status 
-#define ETH_DMASR_ROS_Pos               (4)
-#define ETH_DMASR_ROS                   (0x01U << ETH_DMASR_ROS_Pos )                  ///< Receive overflow status 
-#define ETH_DMASR_TJTS_Pos              (3)
-#define ETH_DMASR_TJTS                  (0x01U << ETH_DMASR_TJTS_Pos)                  ///< Transmit jabber timeout status 
-#define ETH_DMASR_TBUS_Pos              (2)
-#define ETH_DMASR_TBUS                  (0x01U << ETH_DMASR_TBUS_Pos)                  ///< Transmit buffer unavailable status 
-#define ETH_DMASR_TPSS_Pos              (1)
-#define ETH_DMASR_TPSS                  (0x01U << ETH_DMASR_TPSS_Pos)                  ///< Transmit process stopped status 
-#define ETH_DMASR_TS_Pos                (0)
-#define ETH_DMASR_TS                    (0x01U << ETH_DMASR_TS_Pos  )                  ///< Transmit status 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMAOMR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define ETH_DMAOMR_TSF_Pos              (21)
-#define ETH_DMAOMR_TSF                  (0x01U << ETH_DMAOMR_TSF_Pos)                  ///< Transmit store and forward 
-#define ETH_DMAOMR_FTF_Pos              (20)
-#define ETH_DMAOMR_FTF                  (0x01U << ETH_DMAOMR_FTF_Pos)                  ///< Flush transmit FIFO 
-#define ETH_DMAOMR_TTC_Pos              (14)
-#define ETH_DMAOMR_TTC                  (0x07U << ETH_DMAOMR_TTC_Pos)                  ///< Transmit threshold control 
-#define ETH_DMAOMR_TTC_64Bytes          (0x00U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 64 Bytes 
-#define ETH_DMAOMR_TTC_128Bytes         (0x01U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 128 Bytes 
-#define ETH_DMAOMR_TTC_192Bytes         (0x02U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 192 Bytes 
-#define ETH_DMAOMR_TTC_256Bytes         (0x03U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 256 Bytes 
-#define ETH_DMAOMR_TTC_40Bytes          (0x04U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 40 Bytes 
-#define ETH_DMAOMR_TTC_32Bytes          (0x05U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 32 Bytes 
-#define ETH_DMAOMR_TTC_24Bytes          (0x06U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 24 Bytes 
-#define ETH_DMAOMR_TTC_16Bytes          (0x07U << ETH_DMAOMR_TTC_Pos)                  ///< threshold level of the MTL Transmit FIFO is 16 Bytes 
-#define ETH_DMAOMR_ST_Pos               (13)
-#define ETH_DMAOMR_ST                   (0x01U << ETH_DMAOMR_ST_Pos  )                  ///< Start/stop transmission command 
-#define ETH_DMAOMR_RFD_Pos              (11)
-#define ETH_DMAOMR_RFD1                 (0x00U << ETH_DMAOMR_RFD_Pos  )                 ///< Threshold for failure flow control 1 byte
-#define ETH_DMAOMR_RFD2                 (0x01U << ETH_DMAOMR_RFD_Pos  )                 ///< Threshold for failure flow control 2 byte
-#define ETH_DMAOMR_RFD3                 (0x02U << ETH_DMAOMR_RFD_Pos  )                 ///< Threshold for failure flow control 3 byte
-#define ETH_DMAOMR_RFD4                 (0x03U << ETH_DMAOMR_RFD_Pos  )                 ///< Threshold for failure flow control 4 byte
-#define ETH_DMAOMR_RFA_Pos              (9)
-#define ETH_DMAOMR_RFA1                 (0x00U << ETH_DMAOMR_RFA_Pos  )                 ///< Activate the threshold for flow control 1 byte
-#define ETH_DMAOMR_RFA2                 (0x01U << ETH_DMAOMR_RFA_Pos  )                 ///< Activate the threshold for flow control 2 byte
-#define ETH_DMAOMR_RFA3                 (0x02U << ETH_DMAOMR_RFA_Pos  )                 ///< Activate the threshold for flow control 3 byte
-#define ETH_DMAOMR_RFA4                 (0x03U << ETH_DMAOMR_RFA_Pos  )                 ///< Activate the threshold for flow control 4 byte
-
-#define ETH_DMAOMR_EFC_Pos              (8)
-#define ETH_DMAOMR_EFC                  (0x01U << ETH_DMAOMR_EFC_Pos )                  ///< Enable HW Flow Control 
-#define ETH_DMAOMR_FEF_Pos              (7)
-#define ETH_DMAOMR_FEF                  (0x01U << ETH_DMAOMR_FEF_Pos )                  ///< Forward error frames 
-#define ETH_DMAOMR_FUGF_Pos             (6)
-#define ETH_DMAOMR_FUGF                 (0x01U << ETH_DMAOMR_FUGF_Pos)                  ///< Forward undersized good frames 
-#define ETH_DMAOMR_RTC_Pos              (3)
-#define ETH_DMAOMR_RTC                  (0x03U << ETH_DMAOMR_RTC_Pos)                  ///< receive threshold control 
-#define ETH_DMAOMR_RTC_64Bytes          (0x00U << ETH_DMAOMR_RTC_Pos)                  ///< threshold level of the MTL Receive FIFO is 64 Bytes 
-#define ETH_DMAOMR_RTC_32Bytes          (0x01U << ETH_DMAOMR_RTC_Pos)                  ///< threshold level of the MTL Receive FIFO is 32 Bytes 
-#define ETH_DMAOMR_RTC_96Bytes          (0x02U << ETH_DMAOMR_RTC_Pos)                  ///< threshold level of the MTL Receive FIFO is 96 Bytes 
-#define ETH_DMAOMR_RTC_128Bytes         (0x03U << ETH_DMAOMR_RTC_Pos)                  ///< threshold level of the MTL Receive FIFO is 128 Bytes 
-#define ETH_DMAOMR_OSF_Pos              (2)
-#define ETH_DMAOMR_OSF                  (0x01U << ETH_DMAOMR_OSF_Pos)                  ///< operate on second frame 
-#define ETH_DMAOMR_SR_Pos               (1)
-#define ETH_DMAOMR_SR                   (0x01U << ETH_DMAOMR_SR_Pos )                  ///< Start/stop receive 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMAIER Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMAIER_NISE_Pos             (16)
-#define ETH_DMAIER_NISE                 (0x01U << ETH_DMAIER_NISE_Pos )                  ///< Normal interrupt summary enable 
-#define ETH_DMAIER_AISE_Pos             (15)
-#define ETH_DMAIER_AISE                 (0x01U << ETH_DMAIER_AISE_Pos )                  ///< Abnormal interrupt summary enable 
-#define ETH_DMAIER_ERIE_Pos             (14)
-#define ETH_DMAIER_ERIE                 (0x01U << ETH_DMAIER_ERIE_Pos )                  ///< Early receive interrupt enable 
-#define ETH_DMAIER_FBEIE_Pos            (13)
-#define ETH_DMAIER_FBEIE                (0x01U << ETH_DMAIER_FBEIE_Pos)                  ///< Fatal bus error interrupt enable 
-#define ETH_DMAIER_ETIE_Pos             (10)
-#define ETH_DMAIER_ETIE                 (0x01U << ETH_DMAIER_ETIE_Pos )                  ///< Early transmit interrupt enable 
-#define ETH_DMAIER_RWTIE_Pos            (9)
-#define ETH_DMAIER_RWTIE                (0x01U << ETH_DMAIER_RWTIE_Pos)                  ///< Receive watchdog timeout interrupt enable 
-#define ETH_DMAIER_RPSIE_Pos            (8)
-#define ETH_DMAIER_RPSIE                (0x01U << ETH_DMAIER_RPSIE_Pos)                  ///< Receive process stopped interrupt enable 
-#define ETH_DMAIER_RBUIE_Pos            (7)
-#define ETH_DMAIER_RBUIE                (0x01U << ETH_DMAIER_RBUIE_Pos)                  ///< Receive buffer unavailable interrupt enable 
-#define ETH_DMAIER_RIE_Pos              (6)
-#define ETH_DMAIER_RIE                  (0x01U << ETH_DMAIER_RIE_Pos  )                  ///< Receive interrupt enable 
-#define ETH_DMAIER_TUIE_Pos             (5)
-#define ETH_DMAIER_TUIE                 (0x01U << ETH_DMAIER_TUIE_Pos )                  ///< Transmit Underflow interrupt enable 
-#define ETH_DMAIER_ROIE_Pos             (4)
-#define ETH_DMAIER_ROIE                 (0x01U << ETH_DMAIER_ROIE_Pos )                  ///< Receive Overflow interrupt enable 
-#define ETH_DMAIER_TJTIE_Pos            (3)
-#define ETH_DMAIER_TJTIE                (0x01U << ETH_DMAIER_TJTIE_Pos)                  ///< Transmit jabber timeout interrupt enable 
-#define ETH_DMAIER_TBUIE_Pos            (2)
-#define ETH_DMAIER_TBUIE                (0x01U << ETH_DMAIER_TBUIE_Pos)                  ///< Transmit buffer unavailable interrupt enable 
-#define ETH_DMAIER_TPSIE_Pos            (1)
-#define ETH_DMAIER_TPSIE                (0x01U << ETH_DMAIER_TPSIE_Pos)                  ///< Transmit process stopped interrupt enable 
-#define ETH_DMAIER_TIE_Pos              (0)
-#define ETH_DMAIER_TIE                  (0x01U << ETH_DMAIER_TIE_Pos  )                  ///< Transmit interrupt enable 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMAMFBOCR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMAMFBOCR_OFOC_Pos          (28)
-#define ETH_DMAMFBOCR_OFOC              (0x01U << ETH_DMAMFBOCR_OFOC_Pos)                  ///< Overflow bit for FIFO overflow counter 
-
-#define ETH_DMAMFBOCR_MFA_Pos           (17)
-#define ETH_DMAMFBOCR_MFA               (0x7FFU << ETH_DMAMFBOCR_MFA_Pos )                 ///< Number of frames missed by the application 
-
-#define ETH_DMAMFBOCR_OMFC_Pos          (16)
-#define ETH_DMAMFBOCR_OMFC              (0x01U << ETH_DMAMFBOCR_OMFC_Pos)                  ///< Overflow bit for missed frame counter 
-
-#define ETH_DMAMFBOCR_MFC_Pos           (0)
-#define ETH_DMAMFBOCR_MFC               (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos )                ///< Number of frames missed by the controller 
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMACHTDR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMACHTDR_HTDAP              (0xFFFFFFFFU)                                      ///< Host transmit descriptor address pointer 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMACHRDR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMACHRDR_HRDAP              (0xFFFFFFFFU)                                      ///< Host receive descriptor address pointer 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMACHTBAR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMACHTBAR_HTBAP             (0xFFFFFFFFU)                                      ///< Host transmit buffer address pointer 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief ETH_DMACHRBAR Registers bits definition
-////////////////////////////////////////////////////////////////////////////////
-#define ETH_DMACHRBAR_HRBAP             (0xFFFFFFFFU)                                     ///< Host receive buffer address pointer 
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h
deleted file mode 100644
index 608c12bc2..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_exti.h
+++ /dev/null
@@ -1,544 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_exti.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_EXTI_H
-#define __REG_EXTI_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_BASE                       (APB2PERIPH_BASE + 0x0000)              ///< Base Address: 0x40010000
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI Registers Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 CFGR;                                                              ///< configuration register,                        offset: 0x00
-    u32 Reserved;                                                               ///< Reserved                                       offset: 0x04
-    __IO u32 CR[4];                                                             ///< External interrupt configuration register,     offset: 0x08 - 0x14
-    __IO u32 CFGR2;                                                             ///< configuration register                        offset: 0x18
-    __IO u32 PDETCSR;                                                           ///< Power detection configuration status register offset: 0x1C
-    __IO u32 VOSDLY;                                                            ///< VOS delay time                                offset: 0x20
-    u32 Reserved1[0x100 - 0x09];                                                ///< Reserved space
-    __IO u32 IMR;                                                               ///< Interrupt Mask Register                        offset: 0x00 + 0x400
-    __IO u32 EMR;                                                               ///< Event Mask Register                            offset: 0x04 + 0x400
-    __IO u32 RTSR;                                                              ///< Rising Trigger Status Register                 offset: 0x08 + 0x400
-    __IO u32 FTSR;                                                              ///< Falling Trigger Status Register                offset: 0x0C + 0x400
-    __IO u32 SWIER;                                                             ///< Software Interrupt Enable Register             offset: 0x10 + 0x400
-    __IO u32 PR;                                                                ///< Pending Register                               offset: 0x14 + 0x400
-} EXTI_TypeDef;
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI                        ((EXTI_TypeDef*) EXTI_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_CFGR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_CFGR_MEMMODE_Pos       (0)
-#define EXTI_CFGR_MEMMODE           (0x03U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config
-#define EXTI_CFGR_MEMMODE_0         (0x01U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config Bit 0
-#define EXTI_CFGR_MEMMODE_1         (0x02U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config Bit 1
-#define EXTI_CFGR_FLASH_MEMORY      (0x00U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config Mode 0
-#define EXTI_CFGR_SYSTEM_MEMORY     (0x01U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config Mode 1
-#define EXTI_CFGR_SRAM_MEMORY       (0x03U << EXTI_CFGR_MEMMODE_Pos)        ///< EXTI_Memory Remap Config Mode 3
-
-
-#define EXTI_CFGR_FC_SYNCEN_Pos     (27)
-#define EXTI_CFGR_FC_SYNCEN         (0x01U << EXTI_CFGR_FC_SYNCEN_Pos)      ///< FSMC synchronization enable
-#define EXTI_CFGR_FC_ODATAEN_Pos    (28)
-#define EXTI_CFGR_FC_ODATAEN        (0x01U << EXTI_CFGR_FC_ODATAEN_Pos)     ///< FSMC Only used as data pin
-#define EXTI_CFGR_MODESEL_Pos       (29)                                    ///< FSMC mode selection
-#define EXTI_CFGR_MODESEL0          (0x00U << EXTI_CFGR_MODESEL0_Pos)       ///< Compatible with 8080 protocol interface
-#define EXTI_CFGR_MODESEL1          (0x01U << EXTI_CFGR_MODESEL1_Pos)       ///< Compatible with NOR FLASH protocol interface
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_CR1 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_CR1_EXTI0_Pos          (0)
-#define EXTI_CR1_EXTI0              (0x0FU << EXTI_CR1_EXTI0_Pos)           ///< EXTI 0 configuration
-#define EXTI_CR1_EXTI0_PA           (0x00U << EXTI_CR1_EXTI0_Pos)           ///< PA[0] pin
-#define EXTI_CR1_EXTI0_PB           (0x01U << EXTI_CR1_EXTI0_Pos)           ///< PB[0] pin
-#define EXTI_CR1_EXTI0_PC           (0x02U << EXTI_CR1_EXTI0_Pos)           ///< PC[0] pin
-#define EXTI_CR1_EXTI0_PD           (0x03U << EXTI_CR1_EXTI0_Pos)           ///< PD[0] pin
-
-#define EXTI_CR1_EXTI1_Pos          (4)
-#define EXTI_CR1_EXTI1              (0x0FU << EXTI_CR1_EXTI1_Pos)           ///< EXTI 1 configuration
-#define EXTI_CR1_EXTI1_PA           (0x00U << EXTI_CR1_EXTI1_Pos)           ///< PA[1] pin
-#define EXTI_CR1_EXTI1_PB           (0x01U << EXTI_CR1_EXTI1_Pos)           ///< PB[1] pin
-#define EXTI_CR1_EXTI1_PC           (0x02U << EXTI_CR1_EXTI1_Pos)           ///< PC[1] pin
-#define EXTI_CR1_EXTI1_PD           (0x03U << EXTI_CR1_EXTI1_Pos)           ///< PD[1] pin
-
-#define EXTI_CR1_EXTI2_Pos          (8)
-#define EXTI_CR1_EXTI2              (0x0FU << EXTI_CR1_EXTI2_Pos)           ///< EXTI 2 configuration
-#define EXTI_CR1_EXTI2_PA           (0x00U << EXTI_CR1_EXTI2_Pos)           ///< PA[2] pin
-#define EXTI_CR1_EXTI2_PB           (0x01U << EXTI_CR1_EXTI2_Pos)           ///< PB[2] pin
-#define EXTI_CR1_EXTI2_PC           (0x02U << EXTI_CR1_EXTI2_Pos)           ///< PC[2] pin
-#define EXTI_CR1_EXTI2_PD           (0x03U << EXTI_CR1_EXTI2_Pos)           ///< PD[2] pin
-
-#define EXTI_CR1_EXTI3_Pos          (12)
-#define EXTI_CR1_EXTI3              (0x0FU << EXTI_CR1_EXTI3_Pos)           ///< EXTI 3 configuration
-#define EXTI_CR1_EXTI3_PA           (0x00U << EXTI_CR1_EXTI3_Pos)           ///< PA[3] pin
-#define EXTI_CR1_EXTI3_PB           (0x01U << EXTI_CR1_EXTI3_Pos)           ///< PB[3] pin
-#define EXTI_CR1_EXTI3_PC           (0x02U << EXTI_CR1_EXTI3_Pos)           ///< PC[3] pin
-#define EXTI_CR1_EXTI3_PD           (0x03U << EXTI_CR1_EXTI3_Pos)           ///< PD[3] pin
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_CR2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_CR2_EXTI4_Pos          (0)
-#define EXTI_CR2_EXTI4              (0x0FU << EXTI_CR2_EXTI4_Pos)           ///< EXTI 4 configuration
-#define EXTI_CR2_EXTI4_PA           (0x00U << EXTI_CR2_EXTI4_Pos)           ///< PA[4] pin
-#define EXTI_CR2_EXTI4_PB           (0x01U << EXTI_CR2_EXTI4_Pos)           ///< PB[4] pin
-#define EXTI_CR2_EXTI4_PC           (0x02U << EXTI_CR2_EXTI4_Pos)           ///< PC[4] pin
-#define EXTI_CR2_EXTI4_PD           (0x03U << EXTI_CR2_EXTI4_Pos)           ///< PD[4] pin
-
-#define EXTI_CR2_EXTI5_Pos          (4)
-#define EXTI_CR2_EXTI5              (0x0FU << EXTI_CR2_EXTI5_Pos)           ///< EXTI 5 configuration
-#define EXTI_CR2_EXTI5_PA           (0x00U << EXTI_CR2_EXTI5_Pos)           ///< PA[5] pin
-#define EXTI_CR2_EXTI5_PB           (0x01U << EXTI_CR2_EXTI5_Pos)           ///< PB[5] pin
-#define EXTI_CR2_EXTI5_PC           (0x02U << EXTI_CR2_EXTI5_Pos)           ///< PC[5] pin
-#define EXTI_CR2_EXTI5_PD           (0x03U << EXTI_CR2_EXTI5_Pos)           ///< PD[5] pin
-
-#define EXTI_CR2_EXTI6_Pos          (8)
-#define EXTI_CR2_EXTI6              (0x0FU << EXTI_CR2_EXTI6_Pos)           ///< EXTI 6 configuration
-#define EXTI_CR2_EXTI6_PA           (0x00U << EXTI_CR2_EXTI6_Pos)           ///< PA[6] pin
-#define EXTI_CR2_EXTI6_PB           (0x01U << EXTI_CR2_EXTI6_Pos)           ///< PB[6] pin
-#define EXTI_CR2_EXTI6_PC           (0x02U << EXTI_CR2_EXTI6_Pos)           ///< PC[6] pin
-#define EXTI_CR2_EXTI6_PD           (0x03U << EXTI_CR2_EXTI6_Pos)           ///< PD[6] pin
-
-#define EXTI_CR2_EXTI7_Pos          (12)
-#define EXTI_CR2_EXTI7              (0x0FU << EXTI_CR2_EXTI7_Pos)           ///< EXTI 7 configuration
-#define EXTI_CR2_EXTI7_PA           (0x00U << EXTI_CR2_EXTI7_Pos)           ///< PA[7] pin
-#define EXTI_CR2_EXTI7_PB           (0x01U << EXTI_CR2_EXTI7_Pos)           ///< PB[7] pin
-#define EXTI_CR2_EXTI7_PC           (0x02U << EXTI_CR2_EXTI7_Pos)           ///< PC[7] pin
-#define EXTI_CR2_EXTI7_PD           (0x03U << EXTI_CR2_EXTI7_Pos)           ///< PD[7] pin
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_CR3 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_CR3_EXTI8_Pos          (0)
-#define EXTI_CR3_EXTI8              (0x0FU << EXTI_CR3_EXTI8_Pos)           ///< EXTI 8 configuration
-#define EXTI_CR3_EXTI8_PA           (0x00U << EXTI_CR3_EXTI8_Pos)           ///< PA[8] pin
-#define EXTI_CR3_EXTI8_PB           (0x01U << EXTI_CR3_EXTI8_Pos)           ///< PB[8] pin
-#define EXTI_CR3_EXTI8_PC           (0x02U << EXTI_CR3_EXTI8_Pos)           ///< PC[8] pin
-#define EXTI_CR3_EXTI8_PD           (0x03U << EXTI_CR3_EXTI8_Pos)           ///< PD[8] pin
-
-#define EXTI_CR3_EXTI9_Pos          (4)
-#define EXTI_CR3_EXTI9              (0x0FU << EXTI_CR3_EXTI9_Pos)           ///< EXTI 9 configuration
-#define EXTI_CR3_EXTI9_PA           (0x00U << EXTI_CR3_EXTI9_Pos)           ///< PA[9] pin
-#define EXTI_CR3_EXTI9_PB           (0x01U << EXTI_CR3_EXTI9_Pos)           ///< PB[9] pin
-#define EXTI_CR3_EXTI9_PC           (0x02U << EXTI_CR3_EXTI9_Pos)           ///< PC[9] pin
-#define EXTI_CR3_EXTI9_PD           (0x03U << EXTI_CR3_EXTI9_Pos)           ///< PD[9] pin
-
-#define EXTI_CR3_EXTI10_Pos         (8)
-#define EXTI_CR3_EXTI10             (0x0FU << EXTI_CR3_EXTI10_Pos)          ///< EXTI 10 configuration
-#define EXTI_CR3_EXTI10_PA          (0x00U << EXTI_CR3_EXTI10_Pos)          ///< PA[10] pin
-#define EXTI_CR3_EXTI10_PB          (0x01U << EXTI_CR3_EXTI10_Pos)          ///< PB[10] pin
-#define EXTI_CR3_EXTI10_PC          (0x02U << EXTI_CR3_EXTI10_Pos)          ///< PC[10] pin
-#define EXTI_CR3_EXTI10_PD          (0x03U << EXTI_CR3_EXTI10_Pos)          ///< PD[10] pin
-
-#define EXTI_CR3_EXTI11_Pos         (12)
-#define EXTI_CR3_EXTI11             (0x0FU << EXTI_CR3_EXTI11_Pos)          ///< EXTI 11 configuration
-#define EXTI_CR3_EXTI11_PA          (0x00U << EXTI_CR3_EXTI11_Pos)          ///< PA[11] pin
-#define EXTI_CR3_EXTI11_PB          (0x01U << EXTI_CR3_EXTI11_Pos)          ///< PB[11] pin
-#define EXTI_CR3_EXTI11_PC          (0x02U << EXTI_CR3_EXTI11_Pos)          ///< PC[11] pin
-#define EXTI_CR3_EXTI11_PD          (0x03U << EXTI_CR3_EXTI11_Pos)          ///< PD[11] pin
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_CR4 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_CR4_EXTI12_Pos         (0)
-#define EXTI_CR4_EXTI12             (0x0FU << EXTI_CR4_EXTI12_Pos)          ///< EXTI 12 configuration
-#define EXTI_CR4_EXTI12_PA          (0x00U << EXTI_CR4_EXTI12_Pos)          ///< PA[12] pin
-#define EXTI_CR4_EXTI12_PB          (0x01U << EXTI_CR4_EXTI12_Pos)          ///< PB[12] pin
-#define EXTI_CR4_EXTI12_PC          (0x02U << EXTI_CR4_EXTI12_Pos)          ///< PC[12] pin
-#define EXTI_CR4_EXTI12_PD          (0x03U << EXTI_CR4_EXTI12_Pos)          ///< PD[12] pin
-
-#define EXTI_CR4_EXTI13_Pos         (4)
-#define EXTI_CR4_EXTI13             (0x0FU << EXTI_CR4_EXTI13_Pos)          ///< EXTI 13 configuration
-#define EXTI_CR4_EXTI13_PA          (0x00U << EXTI_CR4_EXTI13_Pos)          ///< PA[13] pin
-#define EXTI_CR4_EXTI13_PB          (0x01U << EXTI_CR4_EXTI13_Pos)          ///< PB[13] pin
-#define EXTI_CR4_EXTI13_PC          (0x02U << EXTI_CR4_EXTI13_Pos)          ///< PC[13] pin
-#define EXTI_CR4_EXTI13_PD          (0x03U << EXTI_CR4_EXTI13_Pos)          ///< PD[13] pin
-
-#define EXTI_CR4_EXTI14_Pos         (8)
-#define EXTI_CR4_EXTI14             (0x0FU << EXTI_CR4_EXTI14_Pos)          ///< EXTI 14 configuration
-#define EXTI_CR4_EXTI14_PA          (0x00U << EXTI_CR4_EXTI14_Pos)          ///< PA[14] pin
-#define EXTI_CR4_EXTI14_PB          (0x01U << EXTI_CR4_EXTI14_Pos)          ///< PB[14] pin
-#define EXTI_CR4_EXTI14_PC          (0x02U << EXTI_CR4_EXTI14_Pos)          ///< PC[14] pin
-#define EXTI_CR4_EXTI14_PD          (0x03U << EXTI_CR4_EXTI14_Pos)          ///< PD[14] pin
-
-#define EXTI_CR4_EXTI15_Pos         (12)
-#define EXTI_CR4_EXTI15             (0x0FU << EXTI_CR4_EXTI15_Pos)          ///< EXTI 15 configuration
-#define EXTI_CR4_EXTI15_PA          (0x00U << EXTI_CR4_EXTI15_Pos)          ///< PA[15] pin
-#define EXTI_CR4_EXTI15_PB          (0x01U << EXTI_CR4_EXTI15_Pos)          ///< PB[15] pin
-#define EXTI_CR4_EXTI15_PC          (0x02U << EXTI_CR4_EXTI15_Pos)          ///< PC[15] pin
-#define EXTI_CR4_EXTI15_PD          (0x03U << EXTI_CR4_EXTI15_Pos)          ///< PD[15] pin
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_CFGR2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_CFGR2_I2C1_Pos         (16)
-#define EXTI_CFGR2_I2C1_OD          (0x00U << EXTI_CFGR2_I2C1_Pos)          ///< Select open drain mode    
-#define EXTI_CFGR2_I2C1_PP          (0x01U << EXTI_CFGR2_I2C1_Pos)          ///< Select Push-pull mode    
-#define EXTI_CFGR2_I2C2_Pos         (17)
-#define EXTI_CFGR2_I2C2_OD          (0x00U << EXTI_CFGR2_I2C2_Pos)          ///< Select open drain mode    
-#define EXTI_CFGR2_I2C2_PP          (0x01U << EXTI_CFGR2_I2C2_Pos)          ///< Select Push-pull mode    
-#define EXTI_CFGR2_ETPHY_Pos        (20)
-#define EXTI_CFGR2_ETPHY_MII        (0x00U << EXTI_CFGR2_ETPHY_Pos)          ///< Select MII port      
-#define EXTI_CFGR2_ETPHY_RMII       (0x01U << EXTI_CFGR2_ETPHY_Pos)          ///< Select RMII port   
-#define EXTI_CFGR2_MAC_SPD_Pos      (20)
-#define EXTI_CFGR2_MAC_SPD_10       (0x00U << EXTI_CFGR2_ETPHY_Pos)          ///< Select MAC_SPD 10 Mbps     
-#define EXTI_CFGR2_MAC_SPD_100      (0x01U << EXTI_CFGR2_ETPHY_Pos)          ///< Select MAC_SPD 100 Mbps   
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_PDETCSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_PDETCSR_PVDE_Pos       (0)
-#define EXTI_PDETCSR_PVDE           (0x01U << EXTI_PDETCSR_PVDE_Pos)        ///< PVD Enable 
-#define EXTI_PDETCSR_PLS_Pos        (1)
-#define EXTI_PDETCSR_PLS_1_7        (0x00U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 1.7mV 
-#define EXTI_PDETCSR_PLS_2_0        (0x01U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 2.0mV 
-#define EXTI_PDETCSR_PLS_2_3        (0x02U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 2.3mV 
-#define EXTI_PDETCSR_PLS_2_6        (0x03U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 2.6mV 
-#define EXTI_PDETCSR_PLS_2_9        (0x04U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 2.9mV 
-#define EXTI_PDETCSR_PLS_3_2        (0x05U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 3.2mV 
-#define EXTI_PDETCSR_PLS_3_5        (0x06U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 3.5mV 
-#define EXTI_PDETCSR_PLS_3_8        (0x07U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 3.8mV 
-#define EXTI_PDETCSR_PLS_4_1        (0x08U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 4.1mV 
-#define EXTI_PDETCSR_PLS_4_4        (0x09U << EXTI_PDETCSR_PLS_Pos)        ///< PVD 4.4mV 
-#define EXTI_PDETCSR_PLS_4_7        (0x0AU << EXTI_PDETCSR_PLS_Pos)        ///< PVD 4.7mV 
-#define EXTI_PDETCSR_PVDO_Pos       (5)
-#define EXTI_PDETCSR_PVDO           (0x01U << EXTI_PDETCSR_PVDO_Pos)        ///< PVD Output state 
-#define EXTI_PDETCSR_VDTO_Pos       (6)
-#define EXTI_PDETCSR_VDTO           (0x01U << EXTI_PDETCSR_VDTO_Pos)        ///< VDTO Output state 
-#define EXTI_PDETCSR_VDTE_Pos       (8)
-#define EXTI_PDETCSR_VDTE           (0x01U << EXTI_PDETCSR_VDTE_Pos)        ///< VDT Enable 
-#define EXTI_PDETCSR_VDTLS_Pos      (9)
-#define EXTI_PDETCSR_VDTLS0         (0x00U << EXTI_PDETCSR_VDTLS_Pos)       ///< select VDT  0.9V
-#define EXTI_PDETCSR_VDTLS1         (0x01U << EXTI_PDETCSR_VDTLS_Pos)       ///< select VDT  1.0V
-#define EXTI_PDETCSR_VDTLS2         (0x02U << EXTI_PDETCSR_VDTLS_Pos)       ///< select VDT  1.1V
-#define EXTI_PDETCSR_VDTLS3         (0x03U << EXTI_PDETCSR_VDTLS_Pos)       ///< select VDT  1.2V
-#define EXTI_PDETCSR_VBATDIV3_Pos   (11)
-#define EXTI_PDETCSR_VBATDIV3       (0x01U << EXTI_PDETCSR_VBATDIV3_Pos)    ///< PVD Enable 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_VOSDLY Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_EXTI_VOSDLY            (0x3FFU)                               ///< VOS delay time
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_IMR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_IMR_0_Pos              (0)
-#define EXTI_IMR_0                  (0x01U << EXTI_IMR_0_Pos)               ///< Interrupt Mask on line 0
-#define EXTI_IMR_1_Pos              (1)
-#define EXTI_IMR_1                  (0x01U << EXTI_IMR_1_Pos)               ///< Interrupt Mask on line 1
-#define EXTI_IMR_2_Pos              (2)
-#define EXTI_IMR_2                  (0x01U << EXTI_IMR_2_Pos)               ///< Interrupt Mask on line 2
-#define EXTI_IMR_3_Pos              (3)
-#define EXTI_IMR_3                  (0x01U << EXTI_IMR_3_Pos)               ///< Interrupt Mask on line 3
-#define EXTI_IMR_4_Pos              (4)
-#define EXTI_IMR_4                  (0x01U << EXTI_IMR_4_Pos)               ///< Interrupt Mask on line 4
-#define EXTI_IMR_5_Pos              (5)
-#define EXTI_IMR_5                  (0x01U << EXTI_IMR_5_Pos)               ///< Interrupt Mask on line 5
-#define EXTI_IMR_6_Pos              (6)
-#define EXTI_IMR_6                  (0x01U << EXTI_IMR_6_Pos)               ///< Interrupt Mask on line 6
-#define EXTI_IMR_7_Pos              (7)
-#define EXTI_IMR_7                  (0x01U << EXTI_IMR_7_Pos)               ///< Interrupt Mask on line 7
-#define EXTI_IMR_8_Pos              (8)
-#define EXTI_IMR_8                  (0x01U << EXTI_IMR_8_Pos)               ///< Interrupt Mask on line 8
-#define EXTI_IMR_9_Pos              (9)
-#define EXTI_IMR_9                  (0x01U << EXTI_IMR_9_Pos)               ///< Interrupt Mask on line 9
-#define EXTI_IMR_10_Pos             (10)
-#define EXTI_IMR_10                 (0x01U << EXTI_IMR_10_Pos)              ///< Interrupt Mask on line 10
-#define EXTI_IMR_11_Pos             (11)
-#define EXTI_IMR_11                 (0x01U << EXTI_IMR_11_Pos)              ///< Interrupt Mask on line 11
-#define EXTI_IMR_12_Pos             (12)
-#define EXTI_IMR_12                 (0x01U << EXTI_IMR_12_Pos)              ///< Interrupt Mask on line 12
-#define EXTI_IMR_13_Pos             (13)
-#define EXTI_IMR_13                 (0x01U << EXTI_IMR_13_Pos)              ///< Interrupt Mask on line 13
-#define EXTI_IMR_14_Pos             (14)
-#define EXTI_IMR_14                 (0x01U << EXTI_IMR_14_Pos)              ///< Interrupt Mask on line 14
-#define EXTI_IMR_15_Pos             (15)
-#define EXTI_IMR_15                 (0x01U << EXTI_IMR_15_Pos)              ///< Interrupt Mask on line 15
-#define EXTI_IMR_16_Pos             (16)
-#define EXTI_IMR_16                 (0x01U << EXTI_IMR_16_Pos)              ///< Interrupt Mask on line 16
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_EMR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_EMR_0_Pos              (0)
-#define EXTI_EMR_0                  (0x01U << EXTI_EMR_0_Pos)               ///< Event Mask on line 0
-#define EXTI_EMR_1_Pos              (1)
-#define EXTI_EMR_1                  (0x01U << EXTI_EMR_1_Pos)               ///< Event Mask on line 1
-#define EXTI_EMR_2_Pos              (2)
-#define EXTI_EMR_2                  (0x01U << EXTI_EMR_2_Pos)               ///< Event Mask on line 2
-#define EXTI_EMR_3_Pos              (3)
-#define EXTI_EMR_3                  (0x01U << EXTI_EMR_3_Pos)               ///< Event Mask on line 3
-#define EXTI_EMR_4_Pos              (4)
-#define EXTI_EMR_4                  (0x01U << EXTI_EMR_4_Pos)               ///< Event Mask on line 4
-#define EXTI_EMR_5_Pos              (5)
-#define EXTI_EMR_5                  (0x01U << EXTI_EMR_5_Pos)               ///< Event Mask on line 5
-#define EXTI_EMR_6_Pos              (6)
-#define EXTI_EMR_6                  (0x01U << EXTI_EMR_6_Pos)               ///< Event Mask on line 6
-#define EXTI_EMR_7_Pos              (7)
-#define EXTI_EMR_7                  (0x01U << EXTI_EMR_7_Pos)               ///< Event Mask on line 7
-#define EXTI_EMR_8_Pos              (8)
-#define EXTI_EMR_8                  (0x01U << EXTI_EMR_8_Pos)               ///< Event Mask on line 8
-#define EXTI_EMR_9_Pos              (9)
-#define EXTI_EMR_9                  (0x01U << EXTI_EMR_9_Pos)               ///< Event Mask on line 9
-#define EXTI_EMR_10_Pos             (10)
-#define EXTI_EMR_10                 (0x01U << EXTI_EMR_10_Pos)              ///< Event Mask on line 10
-#define EXTI_EMR_11_Pos             (11)
-#define EXTI_EMR_11                 (0x01U << EXTI_EMR_11_Pos)              ///< Event Mask on line 11
-#define EXTI_EMR_12_Pos             (12)
-#define EXTI_EMR_12                 (0x01U << EXTI_EMR_12_Pos)              ///< Event Mask on line 12
-#define EXTI_EMR_13_Pos             (13)
-#define EXTI_EMR_13                 (0x01U << EXTI_EMR_13_Pos)              ///< Event Mask on line 13
-#define EXTI_EMR_14_Pos             (14)
-#define EXTI_EMR_14                 (0x01U << EXTI_EMR_14_Pos)              ///< Event Mask on line 14
-#define EXTI_EMR_15_Pos             (15)
-#define EXTI_EMR_15                 (0x01U << EXTI_EMR_15_Pos)              ///< Event Mask on line 15
-#define EXTI_EMR_16_Pos             (16)
-#define EXTI_EMR_16                 (0x01U << EXTI_EMR_16_Pos)              ///< Event Mask on line 16
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_RTSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_RTSR_0_Pos             (0)
-#define EXTI_RTSR_0                 (0x01U << EXTI_RTSR_0_Pos)              ///< Rising trigger event configuration bit of line 0
-#define EXTI_RTSR_1_Pos             (1)
-#define EXTI_RTSR_1                 (0x01U << EXTI_RTSR_1_Pos)              ///< Rising trigger event configuration bit of line 1
-#define EXTI_RTSR_2_Pos             (2)
-#define EXTI_RTSR_2                 (0x01U << EXTI_RTSR_2_Pos)              ///< Rising trigger event configuration bit of line 2
-#define EXTI_RTSR_3_Pos             (3)
-#define EXTI_RTSR_3                 (0x01U << EXTI_RTSR_3_Pos)              ///< Rising trigger event configuration bit of line 3
-#define EXTI_RTSR_4_Pos             (4)
-#define EXTI_RTSR_4                 (0x01U << EXTI_RTSR_4_Pos)              ///< Rising trigger event configuration bit of line 4
-#define EXTI_RTSR_5_Pos             (5)
-#define EXTI_RTSR_5                 (0x01U << EXTI_RTSR_5_Pos)              ///< Rising trigger event configuration bit of line 5
-#define EXTI_RTSR_6_Pos             (6)
-#define EXTI_RTSR_6                 (0x01U << EXTI_RTSR_6_Pos)              ///< Rising trigger event configuration bit of line 6
-#define EXTI_RTSR_7_Pos             (7)
-#define EXTI_RTSR_7                 (0x01U << EXTI_RTSR_7_Pos)              ///< Rising trigger event configuration bit of line 7
-#define EXTI_RTSR_8_Pos             (8)
-#define EXTI_RTSR_8                 (0x01U << EXTI_RTSR_8_Pos)              ///< Rising trigger event configuration bit of line 8
-#define EXTI_RTSR_9_Pos             (9)
-#define EXTI_RTSR_9                 (0x01U << EXTI_RTSR_9_Pos)              ///< Rising trigger event configuration bit of line 9
-#define EXTI_RTSR_10_Pos            (10)
-#define EXTI_RTSR_10                (0x01U << EXTI_RTSR_10_Pos)             ///< Rising trigger event configuration bit of line 10
-#define EXTI_RTSR_11_Pos            (11)
-#define EXTI_RTSR_11                (0x01U << EXTI_RTSR_11_Pos)             ///< Rising trigger event configuration bit of line 11
-#define EXTI_RTSR_12_Pos            (12)
-#define EXTI_RTSR_12                (0x01U << EXTI_RTSR_12_Pos)             ///< Rising trigger event configuration bit of line 12
-#define EXTI_RTSR_13_Pos            (13)
-#define EXTI_RTSR_13                (0x01U << EXTI_RTSR_13_Pos)             ///< Rising trigger event configuration bit of line 13
-#define EXTI_RTSR_14_Pos            (14)
-#define EXTI_RTSR_14                (0x01U << EXTI_RTSR_14_Pos)             ///< Rising trigger event configuration bit of line 14
-#define EXTI_RTSR_15_Pos            (15)
-#define EXTI_RTSR_15                (0x01U << EXTI_RTSR_15_Pos)             ///< Rising trigger event configuration bit of line 15
-#define EXTI_RTSR_16_Pos            (16)
-#define EXTI_RTSR_16                (0x01U << EXTI_RTSR_16_Pos)             ///< Rising trigger event configuration bit of line 16
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_FTSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_FTSR_0_Pos             (0)
-#define EXTI_FTSR_0                 (0x01U << EXTI_FTSR_0_Pos)              ///< Falling trigger event configuration bit of line 0
-#define EXTI_FTSR_1_Pos             (1)
-#define EXTI_FTSR_1                 (0x01U << EXTI_FTSR_1_Pos)              ///< Falling trigger event configuration bit of line 1
-#define EXTI_FTSR_2_Pos             (2)
-#define EXTI_FTSR_2                 (0x01U << EXTI_FTSR_2_Pos)              ///< Falling trigger event configuration bit of line 2
-#define EXTI_FTSR_3_Pos             (3)
-#define EXTI_FTSR_3                 (0x01U << EXTI_FTSR_3_Pos)              ///< Falling trigger event configuration bit of line 3
-#define EXTI_FTSR_4_Pos             (4)
-#define EXTI_FTSR_4                 (0x01U << EXTI_FTSR_4_Pos)              ///< Falling trigger event configuration bit of line 4
-#define EXTI_FTSR_5_Pos             (5)
-#define EXTI_FTSR_5                 (0x01U << EXTI_FTSR_5_Pos)              ///< Falling trigger event configuration bit of line 5
-#define EXTI_FTSR_6_Pos             (6)
-#define EXTI_FTSR_6                 (0x01U << EXTI_FTSR_6_Pos)              ///< Falling trigger event configuration bit of line 6
-#define EXTI_FTSR_7_Pos             (7)
-#define EXTI_FTSR_7                 (0x01U << EXTI_FTSR_7_Pos)              ///< Falling trigger event configuration bit of line 7
-#define EXTI_FTSR_8_Pos             (8)
-#define EXTI_FTSR_8                 (0x01U << EXTI_FTSR_8_Pos)              ///< Falling trigger event configuration bit of line 8
-#define EXTI_FTSR_9_Pos             (9)
-#define EXTI_FTSR_9                 (0x01U << EXTI_FTSR_9_Pos)              ///< Falling trigger event configuration bit of line 9
-#define EXTI_FTSR_10_Pos            (10)
-#define EXTI_FTSR_10                (0x01U << EXTI_FTSR_10_Pos)             ///< Falling trigger event configuration bit of line 10
-#define EXTI_FTSR_11_Pos            (11)
-#define EXTI_FTSR_11                (0x01U << EXTI_FTSR_11_Pos)             ///< Falling trigger event configuration bit of line 11
-#define EXTI_FTSR_12_Pos            (12)
-#define EXTI_FTSR_12                (0x01U << EXTI_FTSR_12_Pos)             ///< Falling trigger event configuration bit of line 12
-#define EXTI_FTSR_13_Pos            (13)
-#define EXTI_FTSR_13                (0x01U << EXTI_FTSR_13_Pos)             ///< Falling trigger event configuration bit of line 13
-#define EXTI_FTSR_14_Pos            (14)
-#define EXTI_FTSR_14                (0x01U << EXTI_FTSR_14_Pos)             ///< Falling trigger event configuration bit of line 14
-#define EXTI_FTSR_15_Pos            (15)
-#define EXTI_FTSR_15                (0x01U << EXTI_FTSR_15_Pos)             ///< Falling trigger event configuration bit of line 15
-#define EXTI_FTSR_16_Pos            (16)
-#define EXTI_FTSR_16                (0x01U << EXTI_FTSR_16_Pos)             ///< Falling trigger event configuration bit of line 16
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_SWIER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_SWIER_0_Pos            (0)
-#define EXTI_SWIER_0                (0x01U << EXTI_SWIER_0_Pos)             ///< Software Interrupt on line  0
-#define EXTI_SWIER_1_Pos            (1)
-#define EXTI_SWIER_1                (0x01U << EXTI_SWIER_1_Pos)             ///< Software Interrupt on line  1
-#define EXTI_SWIER_2_Pos            (2)
-#define EXTI_SWIER_2                (0x01U << EXTI_SWIER_2_Pos)             ///< Software Interrupt on line  2
-#define EXTI_SWIER_3_Pos            (3)
-#define EXTI_SWIER_3                (0x01U << EXTI_SWIER_3_Pos)             ///< Software Interrupt on line  3
-#define EXTI_SWIER_4_Pos            (4)
-#define EXTI_SWIER_4                (0x01U << EXTI_SWIER_4_Pos)             ///< Software Interrupt on line  4
-#define EXTI_SWIER_5_Pos            (5)
-#define EXTI_SWIER_5                (0x01U << EXTI_SWIER_5_Pos)             ///< Software Interrupt on line  5
-#define EXTI_SWIER_6_Pos            (6)
-#define EXTI_SWIER_6                (0x01U << EXTI_SWIER_6_Pos)             ///< Software Interrupt on line  6
-#define EXTI_SWIER_7_Pos            (7)
-#define EXTI_SWIER_7                (0x01U << EXTI_SWIER_7_Pos)             ///< Software Interrupt on line  7
-#define EXTI_SWIER_8_Pos            (8)
-#define EXTI_SWIER_8                (0x01U << EXTI_SWIER_8_Pos)             ///< Software Interrupt on line  8
-#define EXTI_SWIER_9_Pos            (9)
-#define EXTI_SWIER_9                (0x01U << EXTI_SWIER_9_Pos)             ///< Software Interrupt on line  9
-#define EXTI_SWIER_10_Pos           (10)
-#define EXTI_SWIER_10               (0x01U << EXTI_SWIER_10_Pos)            ///< Software Interrupt on line  10
-#define EXTI_SWIER_11_Pos           (11)
-#define EXTI_SWIER_11               (0x01U << EXTI_SWIER_11_Pos)            ///< Software Interrupt on line  11
-#define EXTI_SWIER_12_Pos           (12)
-#define EXTI_SWIER_12               (0x01U << EXTI_SWIER_12_Pos)            ///< Software Interrupt on line  12
-#define EXTI_SWIER_13_Pos           (13)
-#define EXTI_SWIER_13               (0x01U << EXTI_SWIER_13_Pos)            ///< Software Interrupt on line  13
-#define EXTI_SWIER_14_Pos           (14)
-#define EXTI_SWIER_14               (0x01U << EXTI_SWIER_14_Pos)            ///< Software Interrupt on line  14
-#define EXTI_SWIER_15_Pos           (15)
-#define EXTI_SWIER_15               (0x01U << EXTI_SWIER_15_Pos)            ///< Software Interrupt on line  15
-#define EXTI_SWIER_16_Pos           (16)
-#define EXTI_SWIER_16               (0x01U << EXTI_SWIER_16_Pos)            ///< Software Interrupt on line  16
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief EXTI_PR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define EXTI_PR_0_Pos               (0)
-#define EXTI_PR_0                   (0x01U << EXTI_PR_0_Pos)                ///< Pending bit 0
-#define EXTI_PR_1_Pos               (1)
-#define EXTI_PR_1                   (0x01U << EXTI_PR_1_Pos)                ///< Pending bit 1
-#define EXTI_PR_2_Pos               (2)
-#define EXTI_PR_2                   (0x01U << EXTI_PR_2_Pos)                ///< Pending bit 2
-#define EXTI_PR_3_Pos               (3)
-#define EXTI_PR_3                   (0x01U << EXTI_PR_3_Pos)                ///< Pending bit 3
-#define EXTI_PR_4_Pos               (4)
-#define EXTI_PR_4                   (0x01U << EXTI_PR_4_Pos)                ///< Pending bit 4
-#define EXTI_PR_5_Pos               (5)
-#define EXTI_PR_5                   (0x01U << EXTI_PR_5_Pos)                ///< Pending bit 5
-#define EXTI_PR_6_Pos               (6)
-#define EXTI_PR_6                   (0x01U << EXTI_PR_6_Pos)                ///< Pending bit 6
-#define EXTI_PR_7_Pos               (7)
-#define EXTI_PR_7                   (0x01U << EXTI_PR_7_Pos)                ///< Pending bit 7
-#define EXTI_PR_8_Pos               (8)
-#define EXTI_PR_8                   (0x01U << EXTI_PR_8_Pos)                ///< Pending bit 8
-#define EXTI_PR_9_Pos               (9)
-#define EXTI_PR_9                   (0x01U << EXTI_PR_9_Pos)                ///< Pending bit 9
-#define EXTI_PR_10_Pos              (10)
-#define EXTI_PR_10                  (0x01U << EXTI_PR_10_Pos)               ///< Pending bit 10
-#define EXTI_PR_11_Pos              (11)
-#define EXTI_PR_11                  (0x01U << EXTI_PR_11_Pos)               ///< Pending bit 11
-#define EXTI_PR_12_Pos              (12)
-#define EXTI_PR_12                  (0x01U << EXTI_PR_12_Pos)               ///< Pending bit 12
-#define EXTI_PR_13_Pos              (13)
-#define EXTI_PR_13                  (0x01U << EXTI_PR_13_Pos)               ///< Pending bit 13
-#define EXTI_PR_14_Pos              (14)
-#define EXTI_PR_14                  (0x01U << EXTI_PR_14_Pos)               ///< Pending bit 14
-#define EXTI_PR_15_Pos              (15)
-#define EXTI_PR_15                  (0x01U << EXTI_PR_15_Pos)               ///< Pending bit 15
-#define EXTI_PR_16_Pos              (16)
-#define EXTI_PR_16                  (0x01U << EXTI_PR_16_Pos)               ///< Pending bit 16
-
-
-
-
-
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h
deleted file mode 100644
index b95acef60..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_flash.h
+++ /dev/null
@@ -1,290 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_flash.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_FLASH_H
-#define __REG_FLASH_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  MM32 MCU Memory/Peripherals mapping
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH_BASE                      (0x08000000U)                           ///< FLASH base address in the alias region
-#define SRAM_BASE                       (0x20000000U)                           ///< SRAM base address in the alias region
-
-#define CACHE_BASE                      (APB2PERIPH_BASE + 0x6000)              ///< Base Address: 0x40016000       
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH_REG_BASE                  (AHBPERIPH_BASE + 0x2000)               ///< Base Address: 0x40022000
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OPTB Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OB_BASE                         (0x1FFFF800U)                           ///< Flash Option Bytes base address
-#define PROTECT_BASE                    (0x1FFE0000U)                           ///< Flash Protect Bytes base address
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH Registers Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 ACR;                                                               ///< Access control Register                        offset: 0x00
-    __IO u32 KEYR;                                                              ///< Key Register                                   offset: 0x04
-    __IO u32 OPTKEYR;                                                           ///< Option byte key Register                       offset: 0x08
-    __IO u32 SR;                                                                ///< State Register                                 offset: 0x0C
-    __IO u32 CR;                                                                ///< Control Register                               offset: 0x10
-    __IO u32 AR;                                                                ///< Address Register                               offset: 0x14
-    __IO u32 RESERVED;
-    __IO u32 OBR;                                                               ///< Option bytes Register                          offset: 0x1C
-    __IO u32 WRPR;                                                              ///< Write protect Register                         offset: 0x20
-} FLASH_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  OPT Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u16 RDP;                                                               ///< Read Protect,                                  offset: 0x00
-    __IO u16 USER;                                                              ///< User option byte,                              offset: 0x02
-    __IO u16 Data0;                                                             ///< User data 0,                                   offset: 0x04
-    __IO u16 Data1;                                                             ///< User data 1,                                   offset: 0x06
-    __IO u16 WRP0;                                                              ///< Flash write protection option byte 0,          offset: 0x08
-    __IO u16 WRP1;                                                              ///< Flash write protection option byte 1,          offset: 0x0A
-    __IO u16 WRP2;                                                              ///< Flash write protection option byte 2,          offset: 0x0C
-    __IO u16 WRP3;                                                              ///< Flash write protection option byte 3,          offset: 0x0E
-} OB_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  PROTECT BYTES Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u16 PROTECT_LEN0;                                                      ///< The length of Protect byte 0,                  offset: 0x00
-    __IO u16 PROTECT_ADDR0;                                                     ///< Data of Protect byte 0,                        offset: 0x02
-    __IO u16 PROTECT_LEN1;                                                      ///< The length of Protect byte 1,                  offset: 0x04
-    __IO u16 PROTECT_ADDR1;                                                     ///< Data of Protect byte 1,                        offset: 0x06
-    __IO u16 PROTECT_LEN2;                                                      ///< The length of Protect byte 2,                  offset: 0x08
-    __IO u16 PROTECT_ADDR2;                                                     ///< Data of Protect byte 2,                        offset: 0x0A
-    __IO u16 PROTECT_LEN3;                                                      ///< The length of Protect byte 3,                  offset: 0x0C
-    __IO u16 PROTECT_ADDR3;                                                     ///< Data of Protect byte 3,                        offset: 0x0E
-} PROTECT_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief  CACHE BYTES Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-
-typedef struct {
-    __IO u32 CCR;                                                               ///< Configuration and control register              offset: 0x00
-    __IO u32 SR;                                                                ///< Status register                                 offset: 0x04
-    __IO u32 IMR;                                                               ///< Interrupt mask register                         offset: 0x08
-    __IO u32 ISR;                                                               ///< Interrupt status register                       offset: 0x0C
-    __IO u32 RESERVED0;                                                         ///<                                                 offset: 0x10
-    __IO u32 CSHR;                                                              ///< Hit Statistics Register                         offset: 0x14
-    __IO u32 CSMR;                                                              ///< Lost Statistics Register                        offset: 0x18
-} CACHE_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH                           ((FLASH_TypeDef*) FLASH_REG_BASE)
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OPTB type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OB                              ((OB_TypeDef*) OB_BASE)
-#define PROTECT                         ((PROTECT_TypeDef*) PROTECT_BASE)
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CACHE pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CACHE                           ((CACHE_TypeDef*) CACHE_BASE)
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH_ACR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH_ACR_LATENCY_Pos           (0)
-#define FLASH_ACR_LATENCY               (0x07U << FLASH_ACR_LATENCY_Pos)        ///< LATENCY[2:0] bits (Latency)
-#define FLASH_ACR_LATENCY_0             (0x00U << FLASH_ACR_LATENCY_Pos)        ///< 0 waiting state
-#define FLASH_ACR_LATENCY_1             (0x01U << FLASH_ACR_LATENCY_Pos)        ///< 1 waiting state   
-#define FLASH_ACR_LATENCY_2             (0x02U << FLASH_ACR_LATENCY_Pos)        ///< 2 waiting state
-#define FLASH_ACR_LATENCY_3             (0x03U << FLASH_ACR_LATENCY_Pos)        ///< 3 waiting state
-#define FLASH_ACR_HLFCYA_Pos            (3)
-#define FLASH_ACR_HLFCYA                (0x01U << FLASH_ACR_HLFCYA_Pos)         ///< Flash Half Cycle Access Enable
-#define FLASH_ACR_PRFTBE_Pos            (4)
-#define FLASH_ACR_PRFTBE                (0x01U << FLASH_ACR_PRFTBE_Pos)         ///< Prefetch Buffer Enable
-#define FLASH_ACR_PRFTBS_Pos            (5)
-#define FLASH_ACR_PRFTBS                (0x01U << FLASH_ACR_PRFTBS_Pos)         ///< Prefetch Buffer Status
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH_KEYR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH_KEYR_FKEY_Pos             (0)
-#define FLASH_KEYR_FKEY                 (0xFFFFFFFFU << FLASH_KEYR_FKEY_Pos)    ///< FLASH Key
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH_OPTKEYR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH_OPTKEYR_OPTKEY_Pos        (0)
-#define FLASH_OPTKEYR_OPTKEY            (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEY_Pos)   ///< Option Byte Key
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH_SR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH_SR_BUSY_Pos               (0)
-#define FLASH_SR_BUSY                   (0x01U << FLASH_SR_BUSY_Pos)            ///< Busy
-#define FLASH_SR_PGERR_Pos              (2)
-#define FLASH_SR_PGERR                  (0x01U << FLASH_SR_PGERR_Pos)           ///< Programming Error
-#define FLASH_SR_WRPRTERR_Pos           (4)
-#define FLASH_SR_WRPRTERR               (0x01U << FLASH_SR_WRPRTERR_Pos)        ///< Write Protection Error
-#define FLASH_SR_EOP_Pos                (5)
-#define FLASH_SR_EOP                    (0x01U << FLASH_SR_EOP_Pos)             ///< End of operation
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH_CR_PG_Pos                 (0)
-#define FLASH_CR_PG                     (0x01U << FLASH_CR_PG_Pos)              ///< Programming
-#define FLASH_CR_PER_Pos                (1)
-#define FLASH_CR_PER                    (0x01U << FLASH_CR_PER_Pos)             ///< Page Erase
-#define FLASH_CR_MER_Pos                (2)
-#define FLASH_CR_MER                    (0x01U << FLASH_CR_MER_Pos)             ///< Mass Erase
-#define FLASH_CR_OPTPG_Pos              (4)
-#define FLASH_CR_OPTPG                  (0x01U << FLASH_CR_OPTPG_Pos)           ///< Option Byte Programming
-#define FLASH_CR_OPTER_Pos              (5)
-#define FLASH_CR_OPTER                  (0x01U << FLASH_CR_OPTER_Pos)           ///< Option Byte Erase
-#define FLASH_CR_STRT_Pos               (6)
-#define FLASH_CR_STRT                   (0x01U << FLASH_CR_STRT_Pos)            ///< Start
-#define FLASH_CR_LOCK_Pos               (7)
-#define FLASH_CR_LOCK                   (0x01U << FLASH_CR_LOCK_Pos)            ///< Lock
-#define FLASH_CR_OPTWRE_Pos             (9)
-#define FLASH_CR_OPTWRE                 (0x01U << FLASH_CR_OPTWRE_Pos)          ///< Option Bytes Write Enable
-#define FLASH_CR_ERRIE_Pos              (10)
-#define FLASH_CR_ERRIE                  (0x01U << FLASH_CR_ERRIE_Pos)           ///< Error Interrupt Enable
-#define FLASH_CR_EOPIE_Pos              (12)
-#define FLASH_CR_EOPIE                  (0x01U << FLASH_CR_EOPIE_Pos)           ///< End of operation interrupt enable
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH_AR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH_AR_FAR_Pos                (0)
-#define FLASH_AR_FAR                    (0xFFFFFFFFU << FLASH_AR_FAR_Pos)       ///< Flash Address
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH_OBR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH_OBR_OPTERR_Pos            (0)
-#define FLASH_OBR_OPTERR                (0x01U << FLASH_OBR_OPTERR_Pos)         ///< Option Byte Error
-#define FLASH_OBR_RDPRT_Pos             (1)
-#define FLASH_OBR_RDPRT                 (0x01U << FLASH_OBR_RDPRT_Pos)         ///< Read protection level status
-#define FLASH_OBR_USER_Pos              (2)
-#define FLASH_OBR_USER                  (0xFFU << FLASH_OBR_USER_Pos)           ///< User Option Bytes
-
-#define FLASH_OBR_WDG_SW                (0x01U << FLASH_OBR_USER_Pos)           ///< WDG_SW
-#define FLASH_OBR_RST_STOP              (0x02U << FLASH_OBR_USER_Pos)           ///< nRST_STOP
-#define FLASH_OBR_RST_STDBY             (0x04U << FLASH_OBR_USER_Pos)           ///< nRST_STDBY
-
-
-#define FLASH_OBR_Data0_Pos             (10)
-#define FLASH_OBR_Data0                 (0xFFU << FLASH_OBR_Data0_Pos)          ///< User data storage option byte
-#define FLASH_OBR_Data1_Pos             (18)
-#define FLASH_OBR_Data1                 (0xFFU << FLASH_OBR_Data1_Pos)          ///< User data storage option byte
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH_WRPR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FLASH_WRPR_WRP_Pos              (0)
-#define FLASH_WRPR_WRP                  (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos)     ///< Write Protect
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CACHE_CCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CACHE_CCR_EN_Pos               (0)
-#define CACHE_CCR_EN                   (0x01U << CACHE_CCR_EN_Pos)              ///< Cache Enable
-#define CACHE_CCR_INV_Pos              (1)
-#define CACHE_CCR_INV                  (0x01U << CACHE_CCR_INV_REQ_Pos)         ///< Manually invalidate the request
-#define CACHE_CCR_POW_Pos              (2)
-#define CACHE_CCR_POW                  (0x01U << CACHE_CCR_POW_REQ_Pos)         ///< Manual SRAM power request
-#define CACHE_CCR_MAN_POW_Pos          (3)
-#define CACHE_CCR_MAN_POW              (0x01U << CACHE_CCR_MAN_POW_Pos)         ///< Set manual or automatic SRAM power request
-#define CACHE_CCR_MAN_INV_Pos          (4)
-#define CACHE_CCR_MAN_INV              (0x01U << CACHE_CCR_MAN_INV_Pos)         ///< Manually or automatically disable it
-#define CACHE_CCR_PREFETCH_Pos         (5)
-#define CACHE_CCR_PREFETCH             (0x01U << CACHE_CCR_PREFETCH_Pos)        ///< Prefetch function
-#define CACHE_CCR_STATISTIC_Pos        (6)
-#define CACHE_CCR_STATISTIC            (0x01U << CACHE_CCR_STATISTIC_Pos)       ///< Statistics enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CACHE_SR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CACHE_SR_CS_Pos               (0)
-#define CACHE_SR_CS0                  (0x00U << CACHE_CCR_CS_Pos)              ///< Cache is disabled
-#define CACHE_SR_CS1                  (0x01U << CACHE_CCR_CS_Pos)              ///< Cache is being enabled
-#define CACHE_SR_CS2                  (0x02U << CACHE_CCR_CS_Pos)              ///< Cache is enabled
-#define CACHE_SR_CS3                  (0x03U << CACHE_CCR_CS_Pos)              ///< Cache is being disabled
-#define CACHE_SR_INV_Pos              (2)
-#define CACHE_SR_INV                  (0x01U << CACHE_CCR_INV_REQ_Pos)         ///< Invalidation status
-#define CACHE_SR_POW_Pos              (4)
-#define CACHE_SR_POW                  (0x01U << CACHE_CCR_POW_REQ_Pos)         ///< SRAM power response
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CACHE_IMR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CACHE_IMR_MAN_INV_Pos          (0)
-#define CACHE_IMR_MAN_INV              (0x01U << CACHE_IMR_MAN_INV_Pos)        ///< Mask the interrupt request of manual invalidation error
-#define CACHE_IMR_POW_Pos              (1)
-#define CACHE_IMR_POW                  (0x01U << CACHE_IMR_POW_Pos)            ///< Mask the interrupt request of power supply error 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CACHE_ISR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CACHE_ISR_MAN_INV_Pos          (0)
-#define CACHE_ISR_MAN_INV              (0x01U << CACHE_ISR_MAN_INV_Pos)        ///< Manual invalidation of error flags
-#define CACHE_ISR_POW_Pos              (1)
-#define CACHE_ISR_POW                  (0x01U << CACHE_ISR_POW_Pos)            ///< SRAM power error flags 
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CACHE_CSHR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CACHE_CSHR                     (0xFFFFU )                              ///< Cache  Hits
-////////////////////////////////////////////////////////////////////////////////
-/// @brief CACHE_CSHR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define CACHE_CSMR                     (0xFFFFU )                              ///< Cache  Lost times
-
-
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h
deleted file mode 100644
index 77870dd1e..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_fsmc.h
+++ /dev/null
@@ -1,194 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_fsmc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_FSMC_H
-#define __REG_FSMC_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FLASH Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define FSMC_BANK1_ADDR       (0x60000000UL )
-#define FSMC_BANK2_ADDR       (0x60000000UL + 0x4000000 )
-#define FSMC_BANK3_ADDR       (0x60000000UL + 0x8000000 )
-#define FSMC_BANK4_ADDR       (0x60000000UL + 0xc000000 )
-#define FSMC_BASE             (0x60000000UL + 0x40000000)                      ///< Base Address: 0xA0000000
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FSMC Registers Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-
-typedef struct {
-    __IO u32 Reservedoffset0x00;                                                ///< Reserved Register                              offset: 0x00
-    __IO u32 Reservedoffset0x04;                                                ///< Reserved Register                              offset: 0x04
-    __IO u32 Reservedoffset0x08;                                                ///< Reserved Register                              offset: 0x08
-    __IO u32 Reservedoffset0x0c;                                                ///< Reserved Register                              offset: 0x0c
-    __IO u32 Reservedoffset0x10;                                                ///< Reserved Register                              offset: 0x10
-    __IO u32 Reservedoffset0x14;                                                ///< Reserved Register                              offset: 0x14
-    __IO u32 Reservedoffset0x18;                                                ///< Reserved Register                              offset: 0x18
-    __IO u32 Reservedoffset0x1c;                                                ///< Reserved Register                              offset: 0x1c
-    __IO u32 Reservedoffset0x20;                                                ///< Reserved Register                              offset: 0x20
-    __IO u32 Reservedoffset0x24;                                                ///< Reserved Register                              offset: 0x24
-    __IO u32 Reservedoffset0x28;                                                ///< Reserved Register                              offset: 0x28
-    __IO u32 Reservedoffset0x2c;                                                ///< Reserved Register                              offset: 0x2c
-    __IO u32 Reservedoffset0x30;                                                ///< Reserved Register                              offset: 0x30
-    __IO u32 Reservedoffset0x34;                                                ///< Reserved Register                              offset: 0x34
-    __IO u32 Reservedoffset0x38;                                                ///< Reserved Register                              offset: 0x38
-    __IO u32 Reservedoffset0x3c;                                                ///< Reserved Register                              offset: 0x3c
-    __IO u32 Reservedoffset0x40;                                                ///< Reserved Register                              offset: 0x40
-    __IO u32 Reservedoffset0x44;                                                ///< Reserved Register                              offset: 0x44
-    __IO u32 Reservedoffset0x48;                                                ///< Reserved Register                              offset: 0x48
-    __IO u32 Reservedoffset0x4c;                                                ///< Reserved Register                              offset: 0x4c
-    __IO u32 Reservedoffset0x50;                                                ///< Reserved Register                              offset: 0x50
-    __IO u32 SMSKR;                                                             ///< SMSKR control Register                         offset: 0x54
-    __IO u32 Reservedoffset0x58;                                                ///< Reserved Register                              offset: 0x58
-    __IO u32 Reservedoffset0x5c;                                                ///< Reserved Register                              offset: 0x5c
-    __IO u32 Reservedoffset0x60;                                                ///< Reserved Register                              offset: 0x60
-    __IO u32 Reservedoffset0x64;                                                ///< Reserved Register                              offset: 0x64
-    __IO u32 Reservedoffset0x68;                                                ///< Reserved Register                              offset: 0x68
-    __IO u32 Reservedoffset0x6c;                                                ///< Reserved Register                              offset: 0x6c
-    __IO u32 Reservedoffset0x70;                                                ///< Reserved Register                              offset: 0x70
-    __IO u32 Reservedoffset0x74;                                                ///< Reserved Register                              offset: 0x74
-    __IO u32 Reservedoffset0x78;                                                ///< Reserved Register                              offset: 0x78
-    __IO u32 Reservedoffset0x7c;                                                ///< Reserved Register                              offset: 0x7c
-    __IO u32 Reservedoffset0x80;                                                ///< Reserved Register                              offset: 0x80
-    __IO u32 Reservedoffset0x84;                                                ///< Reserved Register                              offset: 0x84
-    __IO u32 Reservedoffset0x88;                                                ///< Reserved Register                              offset: 0x88
-    __IO u32 Reservedoffset0x8c;                                                ///< Reserved Register                              offset: 0x8c
-    __IO u32 Reservedoffset0x90;                                                ///< Reserved Register                              offset: 0x90
-    __IO u32 SMTMGR_SET0;                                                       ///< SMTMGR_SET Register 0                          offset: 0x94
-    __IO u32 SMTMGR_SET1;                                                       ///< SMTMGR_SET Register 1                          offset: 0x98
-    __IO u32 SMTMGR_SET2;                                                       ///< SMTMGR_SET Register 2                          offset: 0x9c
-    __IO u32 Reservedoffset0xA0;                                                ///< Reserved Register                              offset: 0xa0
-    __IO u32 SMCTLR;                                                            ///< Reserved Register                              offset: 0xa4
-    __IO u32 Reservedoffset0xA8;                                                ///< Reserved Register                              offset: 0xa8
-    __IO u32 Reservedoffset0xAC;                                                ///< Reserved Register                              offset: 0xac
-} FSMC_TypeDef;
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FSMC  type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FSMC                            ((FSMC_TypeDef*) FSMC_BASE)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FSMC_SMSKR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FSMC_SMSKR_REG_SELECT_Pos          (8)
-#define FSMC_SMSKR_REG_SELECT0             (0x00U << FSMC_SMSKR_REG_SELECT_Pos)        ///< timing parameter configures the register group 0
-#define FSMC_SMSKR_REG_SELECT1             (0x01U << FSMC_SMSKR_REG_SELECT_Pos)        ///< timing parameter configures the register group 1
-#define FSMC_SMSKR_REG_SELECT2             (0x02U << FSMC_SMSKR_REG_SELECT_Pos)        ///< timing parameter configures the register group 2
-#define FSMC_SMSKR_MEM_TYPE_Pos            (5)
-#define FSMC_SMSKR_MEM_TYPE0               (0x00U << FSMC_SMSKR_MEM_TYPE_Pos)        ///< SDRAM
-#define FSMC_SMSKR_MEM_TYPE1               (0x01U << FSMC_SMSKR_MEM_TYPE_Pos)        ///< SRAM
-#define FSMC_SMSKR_MEM_TYPE2               (0x02U << FSMC_SMSKR_MEM_TYPE_Pos)        ///< FLASH
-#define FSMC_SMSKR_MEM_SIZE_Pos            (0)
-#define FSMC_SMSKR_MEM_SIZE_64K            (0x01U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 64KB
-#define FSMC_SMSKR_MEM_SIZE_128K           (0x02U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 128KB
-#define FSMC_SMSKR_MEM_SIZE_256K           (0x03U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 256KB
-#define FSMC_SMSKR_MEM_SIZE_512K           (0x04U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 512KB
-#define FSMC_SMSKR_MEM_SIZE_1M             (0x05U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 1MB
-#define FSMC_SMSKR_MEM_SIZE_2M             (0x06U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 2MB
-#define FSMC_SMSKR_MEM_SIZE_4M             (0x07U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 4MB
-#define FSMC_SMSKR_MEM_SIZE_8M             (0x08U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 8MB
-#define FSMC_SMSKR_MEM_SIZE_16M            (0x09U << FSMC_SMSKR_MEM_SIZE_Pos)         ///< external DEVICE size 16MB
-#define FSMC_SMSKR_MEM_SIZE_32M            (0x10U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 32MB
-#define FSMC_SMSKR_MEM_SIZE_64M            (0x11U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 64MB
-#define FSMC_SMSKR_MEM_SIZE_128M           (0x12U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 128MB
-#define FSMC_SMSKR_MEM_SIZE_256M           (0x13U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 256MB
-#define FSMC_SMSKR_MEM_SIZE_512M           (0x14U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 512MB
-#define FSMC_SMSKR_MEM_SIZE_1G             (0x15U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 1GB
-#define FSMC_SMSKR_MEM_SIZE_2G             (0x16U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 2GB
-#define FSMC_SMSKR_MEM_SIZE_4G             (0x17U << FSMC_SMSKR_MEM_SIZE_Pos)        ///< external DEVICE size 4GB
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FSMC_SMTMGR_SET0/1/2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FSMC_SMTMGR_SET_SM_READ_PIPE_Pos          (28)
-#define FSMC_SMTMGR_SET_SM_READ_PIPE              (0x03U << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos)          ///< The period of the latched read data 
-#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos  (27)
-#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE      (0x01U << FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos)  ///< Access low frequency synchronization devices
-#define FSMC_SMTMGR_SET_READ_MODE_Pos             (26)
-#define FSMC_SMTMGR_SET_READ_MODE                 (0x01U << FSMC_SMTMGR_SET_READ_MODE_Pos)             ///< The Hready_RESP signal is from an external DEVICE
-#define FSMC_SMTMGR_SET_T_WP_Pos                  (10)
-#define FSMC_SMTMGR_SET_T_WP                      (0x3FU << FSMC_SMTMGR_SET_T_WP_Pos)                  ///< Write pulse width 64 clock cycles
-#define FSMC_SMTMGR_SET_T_WR_Pos                  (8)
-#define FSMC_SMTMGR_SET_T_WR                      (0x03U << FSMC_SMTMGR_SET_T_WR_Pos)                  ///< Address/data retention time for write operations is 3 clock cycles
-#define FSMC_SMTMGR_SET_T_AS_Pos                  (6)
-#define FSMC_SMTMGR_SET_T_AS                      (0x03U << FSMC_SMTMGR_SET_T_AS_Pos)                  ///< The address establishment time of write operation is 3 clock cycles
-#define FSMC_SMTMGR_SET_T_RC_Pos                  (0)
-#define FSMC_SMTMGR_SET_T_RC                      (0x3FU << FSMC_SMTMGR_SET_T_RC_Pos)                  ///< Read operation cycle 64 clock cycles
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief FSMC_SMCTLR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos          (13)
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2              (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_16           (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)          ///< Memory data bus bit width 16  bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_32           (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)          ///< Memory data bus bit width 32  bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_64           (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)          ///< Memory data bus bit width 64  bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_128          (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)          ///< Memory data bus bit width 128 bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_8            (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)          ///< Memory data bus bit width 8   bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos          (10)
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1              (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_16           (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)          ///< Memory data bus bit width 16  bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_32           (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)          ///< Memory data bus bit width 32  bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_64           (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)          ///< Memory data bus bit width 64  bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_128          (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)          ///< Memory data bus bit width 128 bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_8            (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)          ///< Memory data bus bit width 8   bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos          (7)
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0              (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_16           (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)          ///< Memory data bus bit width 16  bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_32           (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)          ///< Memory data bus bit width 32  bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_64           (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)          ///< Memory data bus bit width 64  bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_128          (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)          ///< Memory data bus bit width 128 bits
-#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_8            (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)          ///< Memory data bus bit width 8   bits
-
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif //__REG_FSMC_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h
deleted file mode 100644
index 44e043bac..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_gpio.h
+++ /dev/null
@@ -1,706 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_gpio.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_GPIO_H
-#define __REG_GPIO_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define GPIOA_BASE                  (AHBPERIPH_BASE + 0x0020000)                ///< Base Address: 0x40040000
-#define GPIOB_BASE                  (AHBPERIPH_BASE + 0x0020400)                ///< Base Address: 0x40040400
-#define GPIOC_BASE                  (AHBPERIPH_BASE + 0x0020800)                ///< Base Address: 0x40040800
-#define GPIOD_BASE                  (AHBPERIPH_BASE + 0x0020C00)                ///< Base Address: 0x40040C00
-#define GPIOE_BASE                  (AHBPERIPH_BASE + 0x0021000)                ///< Base Address: 0x40041000
-#define GPIOF_BASE                  (AHBPERIPH_BASE + 0x0021400)                ///< Base Address: 0x40041400
-#define GPIOG_BASE                  (AHBPERIPH_BASE + 0x0021800)                ///< Base Address: 0x40041800
-#define GPIOH_BASE                  (AHBPERIPH_BASE + 0x0021C00)                ///< Base Address: 0x40041C00
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO Registers Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 CRL;                                                               ///< Control Register Low,                          offset: 0x00
-    __IO u32 CRH;                                                               ///< Control Register High,                         offset: 0x04
-    __IO u32 IDR;                                                               ///< Input Data Register,                           offset: 0x08
-    __IO u32 ODR;                                                               ///< Output Data Register,                          offset: 0x0C
-    __IO u32 BSRR;                                                              ///< Bit Set or Reset Register,                     offset: 0x10
-    __IO u32 BRR;                                                               ///< Bit Reset Register,                            offset: 0x14
-    __IO u32 LCKR;                                                              ///< Lock Register,                                 offset: 0x18
-    __IO u32 DCR;                                                               ///< Pin Output Open Drain Config Register,         offset: 0x1C
-    __IO u32 AFRL;                                                              ///< Port Multiplexing Function Low Register,       offset: 0x20
-    __IO u32 AFRH;                                                              ///< Port Multiplexing Function High Register,      offset: 0x24
-} GPIO_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIOA                           ((GPIO_TypeDef*) GPIOA_BASE)
-#define GPIOB                           ((GPIO_TypeDef*) GPIOB_BASE)
-#define GPIOC                           ((GPIO_TypeDef*) GPIOC_BASE)
-#define GPIOD                           ((GPIO_TypeDef*) GPIOD_BASE)
-#define GPIOE                           ((GPIO_TypeDef*) GPIOE_BASE)
-#define GPIOF                           ((GPIO_TypeDef*) GPIOF_BASE)
-#define GPIOG                           ((GPIO_TypeDef*) GPIOG_BASE)
-#define GPIOH                           ((GPIO_TypeDef*) GPIOH_BASE)
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO Common Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-
-
-
-
-#define GPIO_CNF_MODE_AIN             0x00UL //0b0000,                                ///< Analog input
-#define GPIO_CNF_MODE_FLOATING        0x04UL //0b0100,                                ///< Floating input
-#define GPIO_CNF_MODE_INPUPD          0x08UL //0b1000,                                ///< Pull up and down input
-#define GPIO_CNF_MODE_INRESEVED       0x0CUL //0b1100,                                ///< Reseved input mode
-#define GPIO_CNF_MODE_OUT_PP          0x01UL //0b0001,                                ///< Universal push-pull  output default
-#define GPIO_CNF_MODE_OUT_OD          0x05UL //0b0101,                                ///< Universal open drain output default
-#define GPIO_CNF_MODE_AF_PP           0x09UL //0b1001,                                ///< Multiplex push-pull  output default
-#define GPIO_CNF_MODE_AF_OD           0x0DUL //0b1101                                 ///< Multiplex open drain output default
-#define GPIO_CNF_MODE_50MHZ_OUT_PP    0x01UL //0b0001,                                ///< Universal push-pull  output 50MHZ
-#define GPIO_CNF_MODE_50MHZ_OUT_OD    0x05UL //0b0101,                                ///< Universal open drain output 50MHZ
-#define GPIO_CNF_MODE_50MHZ_AF_PP     0x09UL //0b1001,                                ///< Multiplex push-pull  output 50MHZ
-#define GPIO_CNF_MODE_50MHZ_AF_OD     0x0DUL //0b1101                                 ///< Multiplex open drain output 50MHZ
-#define GPIO_CNF_MODE_20MHZ_OUT_PP    0x02UL //0b0010,                                ///< Universal push-pull  output 20MHZ
-#define GPIO_CNF_MODE_20MHZ_OUT_OD    0x06UL //0b0110,                                ///< Universal open drain output 20MHZ
-#define GPIO_CNF_MODE_20MHZ_AF_PP     0x0AUL //0b1010,                                ///< Multiplex push-pull  output 20MHZ
-#define GPIO_CNF_MODE_20MHZ_AF_OD     0x0EUL //0b1110                                 ///< Multiplex open drain output 20MHZ
-#define GPIO_CNF_MODE_10MHZ_OUT_PP    0x03UL //0b0011,                                ///< Universal push-pull  output 10MHZ
-#define GPIO_CNF_MODE_10MHZ_OUT_OD    0x07UL //0b0111,                                ///< Universal open drain output 10MHZ
-#define GPIO_CNF_MODE_10MHZ_AF_PP     0x0BUL //0b1011,                                ///< Multiplex push-pull  output 10MHZ
-#define GPIO_CNF_MODE_10MHZ_AF_OD     0x0FUL //0b1111                                 ///< Multiplex open drain output 10MHZ
-#define GPIO_CNF_MODE_MASK            0x0FUL //0b1111
-
-#define GPIO_CRL_CNF_MODE_0_Pos       (0)  //                                       ///< Analog input
-#define GPIO_CRL_CNF_MODE_1_Pos       (4)  //                                       ///< Floating input
-#define GPIO_CRL_CNF_MODE_2_Pos       (8)  //                                       ///< Pull up and down input
-#define GPIO_CRL_CNF_MODE_3_Pos       (12) //                                       ///< Reseved input mode
-#define GPIO_CRL_CNF_MODE_4_Pos       (16) //                                       ///< Universal push-pull  output default
-#define GPIO_CRL_CNF_MODE_5_Pos       (20) //                                       ///< Universal open drain output default
-#define GPIO_CRL_CNF_MODE_6_Pos       (24) //                                       ///< Multiplex push-pull  output default
-#define GPIO_CRL_CNF_MODE_7_Pos       (28) //                                       ///< Multiplex open drain output default
-#define GPIO_CRH_CNF_MODE_8_Pos       (0)  //                                       ///< Universal push-pull  output 50MHZ
-#define GPIO_CRH_CNF_MODE_9_Pos       (4)  //                                       ///< Universal open drain output 50MHZ
-#define GPIO_CRH_CNF_MODE_10_Pos      (8)  //                                       ///< Multiplex push-pull  output 50MHZ
-#define GPIO_CRH_CNF_MODE_11_Pos      (12) //                                       ///< Multiplex open drain output 50MHZ
-#define GPIO_CRH_CNF_MODE_12_Pos      (16) //                                       ///< Universal push-pull  output 20MHZ
-#define GPIO_CRH_CNF_MODE_13_Pos      (20) //                                       ///< Universal open drain output 20MHZ
-#define GPIO_CRH_CNF_MODE_14_Pos      (24) //                                       ///< Multiplex push-pull  output 20MHZ
-#define GPIO_CRH_CNF_MODE_15_Pos      (28) //                                       ///< Multiplex open drain output 20MHZ
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_CRL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_CRL_MODE                   ((u32)0x33333333)                       ///< Port x mode bits
-
-#define GPIO_CRL_MODE0_Pos              (0)
-#define GPIO_CRL_MODE0                  (0x03U << GPIO_CRL_MODE0_Pos)           ///< MODE0[1:0] bits (portx mode bits, pin 0)
-#define GPIO_CRL_MODE0_0                (0x01U << GPIO_CRL_MODE0_Pos)           ///< Bit 0
-#define GPIO_CRL_MODE0_1                (0x02U << GPIO_CRL_MODE0_Pos)           ///< Bit 1
-
-#define GPIO_CRL_CNF0_Pos               (2)
-#define GPIO_CRL_CNF0                   (0x03U << GPIO_CRL_CNF0_Pos)            ///< CNF0[1:0] bits (portx configuration bits, pin 0)
-#define GPIO_CRL_CNF0_0                 (0x01U << GPIO_CRL_CNF0_Pos)            ///< Bit 0
-#define GPIO_CRL_CNF0_1                 (0x02U << GPIO_CRL_CNF0_Pos)            ///< Bit 1
-
-#define GPIO_CRL_MODE1_Pos              (4)
-#define GPIO_CRL_MODE1                  (0x03U << GPIO_CRL_MODE1_Pos)           ///< MODE1[1:0] bits (portx mode bits, pin 1)
-#define GPIO_CRL_MODE1_0                (0x01U << GPIO_CRL_MODE1_Pos)           ///< Bit 0
-#define GPIO_CRL_MODE1_1                (0x02U << GPIO_CRL_MODE1_Pos)           ///< Bit 1
-
-#define GPIO_CRL_CNF1_Pos               (6)
-#define GPIO_CRL_CNF1                   (0x03U << GPIO_CRL_CNF1_Pos)            ///< CNF1[1:0] bits (portx configuration bits, pin 1)
-#define GPIO_CRL_CNF1_0                 (0x01U << GPIO_CRL_CNF1_Pos)            ///< Bit 0
-#define GPIO_CRL_CNF1_1                 (0x02U << GPIO_CRL_CNF1_Pos)            ///< Bit 1
-
-#define GPIO_CRL_MODE2_Pos              (8)
-#define GPIO_CRL_MODE2                  (0x03U << GPIO_CRL_MODE2_Pos)           ///< MODE2[1:0] bits (portx mode bits, pin 2)
-#define GPIO_CRL_MODE2_0                (0x01U << GPIO_CRL_MODE2_Pos)           ///< Bit 0
-#define GPIO_CRL_MODE2_1                (0x02U << GPIO_CRL_MODE2_Pos)           ///< Bit 1
-
-#define GPIO_CRL_CNF2_Pos               (10)
-#define GPIO_CRL_CNF2                   (0x03U << GPIO_CRL_CNF2_Pos)            ///< CNF2[1:0] bits (portx configuration bits, pin 2)
-#define GPIO_CRL_CNF2_0                 (0x01U << GPIO_CRL_CNF2_Pos)            ///< Bit 0
-#define GPIO_CRL_CNF2_1                 (0x02U << GPIO_CRL_CNF2_Pos)            ///< Bit 1
-
-#define GPIO_CRL_MODE3_Pos              (12)
-#define GPIO_CRL_MODE3                  (0x03U << GPIO_CRL_MODE3_Pos)           ///< MODE3[1:0] bits (portx mode bits, pin 3)
-#define GPIO_CRL_MODE3_0                (0x01U << GPIO_CRL_MODE3_Pos)           ///< Bit 0
-#define GPIO_CRL_MODE3_1                (0x02U << GPIO_CRL_MODE3_Pos)           ///< Bit 1
-
-#define GPIO_CRL_CNF3_Pos               (14)
-#define GPIO_CRL_CNF3                   (0x03U << GPIO_CRL_CNF3_Pos)            ///< CNF3[1:0] bits (portx configuration bits, pin 3)
-#define GPIO_CRL_CNF3_0                 (0x01U << GPIO_CRL_CNF3_Pos)            ///< Bit 0
-#define GPIO_CRL_CNF3_1                 (0x02U << GPIO_CRL_CNF3_Pos)            ///< Bit 1
-
-
-#define GPIO_CRL_MODE4_Pos              (16)
-#define GPIO_CRL_MODE4                  (0x03U << GPIO_CRL_MODE4_Pos)           ///< MODE4[1:0] bits (portx mode bits, pin 4)
-#define GPIO_CRL_MODE4_0                (0x01U << GPIO_CRL_MODE4_Pos)           ///< Bit 0
-#define GPIO_CRL_MODE4_1                (0x02U << GPIO_CRL_MODE4_Pos)           ///< Bit 1
-
-#define GPIO_CRL_CNF4_Pos               (18)
-#define GPIO_CRL_CNF4                   (0x03U << GPIO_CRL_CNF4_Pos)            ///< CNF4[1:0] bits (portx configuration bits, pin 4)
-#define GPIO_CRL_CNF4_0                 (0x01U << GPIO_CRL_CNF4_Pos)            ///< Bit 0
-#define GPIO_CRL_CNF4_1                 (0x02U << GPIO_CRL_CNF4_Pos)            ///< Bit 1
-
-#define GPIO_CRL_MODE5_Pos              (20)
-#define GPIO_CRL_MODE5                  (0x03U << GPIO_CRL_MODE5_Pos)           ///< MODE5[1:0] bits (portx mode bits, pin 5)
-#define GPIO_CRL_MODE5_0                (0x01U << GPIO_CRL_MODE5_Pos)           ///< Bit 0
-#define GPIO_CRL_MODE5_1                (0x02U << GPIO_CRL_MODE5_Pos)           ///< Bit 1
-
-#define GPIO_CRL_CNF5_Pos               (22)
-#define GPIO_CRL_CNF5                   (0x03U << GPIO_CRL_CNF5_Pos)            ///< CNF5[1:0] bits (portx configuration bits, pin 5)
-#define GPIO_CRL_CNF5_0                 (0x01U << GPIO_CRL_CNF5_Pos)            ///< Bit 0
-#define GPIO_CRL_CNF5_1                 (0x02U << GPIO_CRL_CNF5_Pos)            ///< Bit 1
-
-#define GPIO_CRL_MODE6_Pos              (24)
-#define GPIO_CRL_MODE6                  (0x03U << GPIO_CRL_MODE6_Pos)           ///< MODE6[1:0] bits (portx mode bits, pin 6)
-#define GPIO_CRL_MODE6_0                (0x01U << GPIO_CRL_MODE6_Pos)           ///< Bit 0
-#define GPIO_CRL_MODE6_1                (0x02U << GPIO_CRL_MODE6_Pos)           ///< Bit 1
-
-#define GPIO_CRL_CNF6_Pos               (26)
-#define GPIO_CRL_CNF6                   (0x03U << GPIO_CRL_CNF6_Pos)            ///< CNF6[1:0] bits (portx configuration bits, pin 6)
-#define GPIO_CRL_CNF6_0                 (0x01U << GPIO_CRL_CNF6_Pos)            ///< Bit 0
-#define GPIO_CRL_CNF6_1                 (0x02U << GPIO_CRL_CNF6_Pos)            ///< Bit 1
-
-#define GPIO_CRL_MODE7_Pos              (28)
-#define GPIO_CRL_MODE7                  (0x03U << GPIO_CRL_MODE7_Pos)           ///< MODE7[1:0] bits (portx mode bits, pin 7)
-#define GPIO_CRL_MODE7_0                (0x01U << GPIO_CRL_MODE7_Pos)           ///< Bit 0
-#define GPIO_CRL_MODE7_1                (0x02U << GPIO_CRL_MODE7_Pos)           ///< Bit 1
-
-#define GPIO_CRL_CNF7_Pos               (30)
-#define GPIO_CRL_CNF7                   (0x03U << GPIO_CRL_CNF7_Pos)            ///< CNF7[1:0] bits (portx configuration bits, pin 7)
-#define GPIO_CRL_CNF7_0                 (0x01U << GPIO_CRL_CNF7_Pos)            ///< Bit 0
-#define GPIO_CRL_CNF7_1                 (0x02U << GPIO_CRL_CNF7_Pos)            ///< Bit 1
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_CRH Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_CRH_MODE                   ((u32)0x33333333)                       ///< Port x mode bits
-
-#define GPIO_CRH_MODE8_Pos              (0)
-#define GPIO_CRH_MODE8                  (0x03U << GPIO_CRH_MODE8_Pos)           ///< MODE8[1:0] bits (portx mode bits, pin 0)
-#define GPIO_CRH_MODE8_0                (0x01U << GPIO_CRH_MODE8_Pos)           ///< Bit 0
-#define GPIO_CRH_MODE8_1                (0x02U << GPIO_CRH_MODE8_Pos)           ///< Bit 1
-#define GPIO_CRH_CNF8_Pos               (2)
-#define GPIO_CRH_CNF8                   (0x03U << GPIO_CRH_CNF8_Pos)            ///< CNF8[1:0] bits (portx configuration bits, pin 0)
-#define GPIO_CRH_CNF8_0                 (0x01U << GPIO_CRH_CNF8_Pos)            ///< Bit 0
-#define GPIO_CRH_CNF8_1                 (0x02U << GPIO_CRH_CNF8_Pos)            ///< Bit 1
-#define GPIO_CRH_MODE9_Pos              (4)
-#define GPIO_CRH_MODE9                  (0x03U << GPIO_CRH_MODE9_Pos)           ///< MODE9[1:0] bits (portx mode bits, pin 1)
-#define GPIO_CRH_MODE9_0                (0x01U << GPIO_CRH_MODE9_Pos)           ///< Bit 0
-#define GPIO_CRH_MODE9_1                (0x02U << GPIO_CRH_MODE9_Pos)           ///< Bit 1
-#define GPIO_CRH_CNF9_Pos               (6)
-#define GPIO_CRH_CNF9                   (0x03U << GPIO_CRH_CNF9_Pos)            ///< CNF9[1:0] bits (portx configuration bits, pin 1)
-#define GPIO_CRH_CNF9_0                 (0x01U << GPIO_CRH_CNF9_Pos)            ///< Bit 0
-#define GPIO_CRH_CNF9_1                 (0x02U << GPIO_CRH_CNF9_Pos)            ///< Bit 1
-#define GPIO_CRH_MODE10_Pos             (8)
-#define GPIO_CRH_MODE10                 (0x03U << GPIO_CRH_MODE10_Pos)          ///< MODE10[1:0] bits (portx mode bits, pin 2)
-#define GPIO_CRH_MODE10_0               (0x01U << GPIO_CRH_MODE10_Pos)          ///< Bit 0
-#define GPIO_CRH_MODE10_1               (0x02U << GPIO_CRH_MODE10_Pos)          ///< Bit 1
-#define GPIO_CRH_CNF10_Pos              (10)
-#define GPIO_CRH_CNF10                  (0x03U << GPIO_CRH_CNF10_Pos)           ///< CNF10[1:0] bits (portx configuration bits, pin 2)
-#define GPIO_CRH_CNF10_0                (0x01U << GPIO_CRH_CNF10_Pos)           ///< Bit 0
-#define GPIO_CRH_CNF10_1                (0x02U << GPIO_CRH_CNF10_Pos)           ///< Bit 1
-#define GPIO_CRH_MODE11_Pos             (12)
-#define GPIO_CRH_MODE11                 (0x03U << GPIO_CRH_MODE11_Pos)          ///< MODE11[1:0] bits (portx mode bits, pin 3)
-#define GPIO_CRH_MODE11_0               (0x01U << GPIO_CRH_MODE11_Pos)          ///< Bit 0
-#define GPIO_CRH_MODE11_1               (0x02U << GPIO_CRH_MODE11_Pos)          ///< Bit 1
-#define GPIO_CRH_CNF11_Pos              (14)
-#define GPIO_CRH_CNF11                  (0x03U << GPIO_CRH_CNF11_Pos)           ///< CNF11[1:0] bits (portx configuration bits, pin 3)
-#define GPIO_CRH_CNF11_0                (0x01U << GPIO_CRH_CNF11_Pos)           ///< Bit 0
-#define GPIO_CRH_CNF11_1                (0x02U << GPIO_CRH_CNF11_Pos)           ///< Bit 1
-#define GPIO_CRH_MODE12_Pos             (16)
-#define GPIO_CRH_MODE12                 (0x03U << GPIO_CRH_MODE12_Pos)          ///< MODE12[1:0] bits (portx mode bits, pin 4)
-#define GPIO_CRH_MODE12_0               (0x01U << GPIO_CRH_MODE12_Pos)          ///< Bit 0
-#define GPIO_CRH_MODE12_1               (0x02U << GPIO_CRH_MODE12_Pos)          ///< Bit 1
-#define GPIO_CRH_CNF12_Pos              (18)
-#define GPIO_CRH_CNF12                  (0x03U << GPIO_CRH_CNF12_Pos)           ///< CNF12[1:0] bits (portx configuration bits, pin 4)
-#define GPIO_CRH_CNF12_0                (0x01U << GPIO_CRH_CNF12_Pos)           ///< Bit 0
-#define GPIO_CRH_CNF12_1                (0x02U << GPIO_CRH_CNF12_Pos)           ///< Bit 1
-#define GPIO_CRH_MODE13_Pos             (20)
-#define GPIO_CRH_MODE13                 (0x03U << GPIO_CRH_MODE13_Pos)          ///< MODE13[1:0] bits (portx mode bits, pin 5)
-#define GPIO_CRH_MODE13_0               (0x01U << GPIO_CRH_MODE13_Pos)          ///< Bit 0
-#define GPIO_CRH_MODE13_1               (0x02U << GPIO_CRH_MODE13_Pos)          ///< Bit 1
-#define GPIO_CRH_CNF13_Pos              (22)
-#define GPIO_CRH_CNF13                  (0x03U << GPIO_CRH_CNF13_Pos)           ///< CNF13[1:0] bits (portx configuration bits, pin 5)
-#define GPIO_CRH_CNF13_0                (0x01U << GPIO_CRH_CNF13_Pos)           ///< Bit 0
-#define GPIO_CRH_CNF13_1                (0x02U << GPIO_CRH_CNF13_Pos)           ///< Bit 1
-#define GPIO_CRH_MODE14_Pos             (24)
-#define GPIO_CRH_MODE14                 (0x03U << GPIO_CRH_MODE14_Pos)          ///< MODE14[1:0] bits (portx mode bits, pin 6)
-#define GPIO_CRH_MODE14_0               (0x01U << GPIO_CRH_MODE14_Pos)          ///< Bit 0
-#define GPIO_CRH_MODE14_1               (0x02U << GPIO_CRH_MODE14_Pos)          ///< Bit 1
-#define GPIO_CRH_CNF14_Pos              (26)
-#define GPIO_CRH_CNF14                  (0x03U << GPIO_CRH_CNF14_Pos)           ///< CNF14[1:0] bits (portx configuration bits, pin 6)
-#define GPIO_CRH_CNF14_0                (0x01U << GPIO_CRH_CNF14_Pos)           ///< Bit 0
-#define GPIO_CRH_CNF14_1                (0x02U << GPIO_CRH_CNF14_Pos)           ///< Bit 1
-#define GPIO_CRH_MODE15_Pos             (28)
-#define GPIO_CRH_MODE15                 (0x03U << GPIO_CRH_MODE15_Pos)          ///< MODE15[1:0] bits (portx mode bits, pin 7)
-#define GPIO_CRH_MODE15_0               (0x01U << GPIO_CRH_MODE15_Pos)          ///< Bit 0
-#define GPIO_CRH_MODE15_1               (0x02U << GPIO_CRH_MODE15_Pos)          ///< Bit 1
-#define GPIO_CRH_CNF15_Pos              (30)
-#define GPIO_CRH_CNF15                  (0x03U << GPIO_CRH_CNF15_Pos)           ///< CNF15[1:0] bits (portx configuration bits, pin 7)
-#define GPIO_CRH_CNF15_0                (0x01U << GPIO_CRH_CNF15_Pos)           ///< Bit 0
-#define GPIO_CRH_CNF15_1                (0x02U << GPIO_CRH_CNF15_Pos)           ///< Bit 1
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_IDR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_IDR_DATA_Pos               (0)
-#define GPIO_IDR_DATA                   (0xFFFFU << GPIO_IDR_DATA_Pos)          ///< Port input data
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_IDR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_IDR_IDR0_Pos               (0)
-#define GPIO_IDR_IDR0                   (0x01U << GPIO_IDR_IDR0_Pos)            ///< Portx Set bit 0
-#define GPIO_IDR_IDR1_Pos               (1)
-#define GPIO_IDR_IDR1                   (0x01U << GPIO_IDR_IDR1_Pos)            ///< Portx Set bit 1
-#define GPIO_IDR_IDR2_Pos               (2)
-#define GPIO_IDR_IDR2                   (0x01U << GPIO_IDR_IDR2_Pos)            ///< Portx Set bit 2
-#define GPIO_IDR_IDR3_Pos               (3)
-#define GPIO_IDR_IDR3                   (0x01U << GPIO_IDR_IDR3_Pos)            ///< Portx Set bit 3
-#define GPIO_IDR_IDR4_Pos               (4)
-#define GPIO_IDR_IDR4                   (0x01U << GPIO_IDR_IDR4_Pos)            ///< Portx Set bit 4
-#define GPIO_IDR_IDR5_Pos               (5)
-#define GPIO_IDR_IDR5                   (0x01U << GPIO_IDR_IDR5_Pos)            ///< Portx Set bit 5
-#define GPIO_IDR_IDR6_Pos               (6)
-#define GPIO_IDR_IDR6                   (0x01U << GPIO_IDR_IDR6_Pos)            ///< Portx Set bit 6
-#define GPIO_IDR_IDR7_Pos               (7)
-#define GPIO_IDR_IDR7                   (0x01U << GPIO_IDR_IDR7_Pos)            ///< Portx Set bit 7
-#define GPIO_IDR_IDR8_Pos               (8)
-#define GPIO_IDR_IDR8                   (0x01U << GPIO_IDR_IDR8_Pos)            ///< Portx Set bit 8
-#define GPIO_IDR_IDR9_Pos               (9)
-#define GPIO_IDR_IDR9                   (0x01U << GPIO_IDR_IDR9_Pos)            ///< Portx Set bit 9
-#define GPIO_IDR_IDR10_Pos              (10)
-#define GPIO_IDR_IDR10                  (0x01U << GPIO_IDR_IDR10_Pos)           ///< Portx Set bit 10
-#define GPIO_IDR_IDR11_Pos              (11)
-#define GPIO_IDR_IDR11                  (0x01U << GPIO_IDR_IDR11_Pos)           ///< Portx Set bit 11
-#define GPIO_IDR_IDR12_Pos              (12)
-#define GPIO_IDR_IDR12                  (0x01U << GPIO_IDR_IDR12_Pos)           ///< Portx Set bit 12
-#define GPIO_IDR_IDR13_Pos              (13)
-#define GPIO_IDR_IDR13                  (0x01U << GPIO_IDR_IDR13_Pos)           ///< Portx Set bit 13
-#define GPIO_IDR_IDR14_Pos              (14)
-#define GPIO_IDR_IDR14                  (0x01U << GPIO_IDR_IDR14_Pos)           ///< Portx Set bit 14
-#define GPIO_IDR_IDR15_Pos              (15)
-#define GPIO_IDR_IDR15                  (0x01U << GPIO_IDR_IDR15_Pos)           ///< Portx Set bit 15
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_ODR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_ODR_DATA_Pos               (0)
-#define GPIO_ODR_DATA                   (0xFFFF << GPIO_ODR_DATA_Pos)           ///< Port output data
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_ODR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_ODR_ODR0_Pos               (0)
-#define GPIO_ODR_ODR0                   (0x01U << GPIO_ODR_ODR0_Pos)            ///< Portx Set bit 0
-#define GPIO_ODR_ODR1_Pos               (1)
-#define GPIO_ODR_ODR1                   (0x01U << GPIO_ODR_ODR1_Pos)            ///< Portx Set bit 1
-#define GPIO_ODR_ODR2_Pos               (2)
-#define GPIO_ODR_ODR2                   (0x01U << GPIO_ODR_ODR2_Pos)            ///< Portx Set bit 2
-#define GPIO_ODR_ODR3_Pos               (3)
-#define GPIO_ODR_ODR3                   (0x01U << GPIO_ODR_ODR3_Pos)            ///< Portx Set bit 3
-#define GPIO_ODR_ODR4_Pos               (4)
-#define GPIO_ODR_ODR4                   (0x01U << GPIO_ODR_ODR4_Pos)            ///< Portx Set bit 4
-#define GPIO_ODR_ODR5_Pos               (5)
-#define GPIO_ODR_ODR5                   (0x01U << GPIO_ODR_ODR5_Pos)            ///< Portx Set bit 5
-#define GPIO_ODR_ODR6_Pos               (6)
-#define GPIO_ODR_ODR6                   (0x01U << GPIO_ODR_ODR6_Pos)            ///< Portx Set bit 6
-#define GPIO_ODR_ODR7_Pos               (7)
-#define GPIO_ODR_ODR7                   (0x01U << GPIO_ODR_ODR7_Pos)            ///< Portx Set bit 7
-#define GPIO_ODR_ODR8_Pos               (8)
-#define GPIO_ODR_ODR8                   (0x01U << GPIO_ODR_ODR8_Pos)            ///< Portx Set bit 8
-#define GPIO_ODR_ODR9_Pos               (9)
-#define GPIO_ODR_ODR9                   (0x01U << GPIO_ODR_ODR9_Pos)            ///< Portx Set bit 9
-#define GPIO_ODR_ODR10_Pos              (10)
-#define GPIO_ODR_ODR10                  (0x01U << GPIO_ODR_ODR10_Pos)           ///< Portx Set bit 10
-#define GPIO_ODR_ODR11_Pos              (11)
-#define GPIO_ODR_ODR11                  (0x01U << GPIO_ODR_ODR11_Pos)           ///< Portx Set bit 11
-#define GPIO_ODR_ODR12_Pos              (12)
-#define GPIO_ODR_ODR12                  (0x01U << GPIO_ODR_ODR12_Pos)           ///< Portx Set bit 12
-#define GPIO_ODR_ODR13_Pos              (13)
-#define GPIO_ODR_ODR13                  (0x01U << GPIO_ODR_ODR13_Pos)           ///< Portx Set bit 13
-#define GPIO_ODR_ODR14_Pos              (14)
-#define GPIO_ODR_ODR14                  (0x01U << GPIO_ODR_ODR14_Pos)           ///< Portx Set bit 14
-#define GPIO_ODR_ODR15_Pos              (15)
-#define GPIO_ODR_ODR15                  (0x01U << GPIO_ODR_ODR15_Pos)           ///< Portx Set bit 15
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_BRR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_BSRR_BS_Pos                (0)
-#define GPIO_BSRR_BS                    (0xFFFFU << GPIO_BSRR_BS_Pos)            ///< Portx Reset
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_BSRR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_BSRR_BS0_Pos               (0)
-#define GPIO_BSRR_BS0                   (0x01U << GPIO_BSRR_BS0_Pos)            ///< Portx Set bit 0
-#define GPIO_BSRR_BS1_Pos               (1)
-#define GPIO_BSRR_BS1                   (0x01U << GPIO_BSRR_BS1_Pos)            ///< Portx Set bit 1
-#define GPIO_BSRR_BS2_Pos               (2)
-#define GPIO_BSRR_BS2                   (0x01U << GPIO_BSRR_BS2_Pos)            ///< Portx Set bit 2
-#define GPIO_BSRR_BS3_Pos               (3)
-#define GPIO_BSRR_BS3                   (0x01U << GPIO_BSRR_BS3_Pos)            ///< Portx Set bit 3
-#define GPIO_BSRR_BS4_Pos               (4)
-#define GPIO_BSRR_BS4                   (0x01U << GPIO_BSRR_BS4_Pos)            ///< Portx Set bit 4
-#define GPIO_BSRR_BS5_Pos               (5)
-#define GPIO_BSRR_BS5                   (0x01U << GPIO_BSRR_BS5_Pos)            ///< Portx Set bit 5
-#define GPIO_BSRR_BS6_Pos               (6)
-#define GPIO_BSRR_BS6                   (0x01U << GPIO_BSRR_BS6_Pos)            ///< Portx Set bit 6
-#define GPIO_BSRR_BS7_Pos               (7)
-#define GPIO_BSRR_BS7                   (0x01U << GPIO_BSRR_BS7_Pos)            ///< Portx Set bit 7
-#define GPIO_BSRR_BS8_Pos               (8)
-#define GPIO_BSRR_BS8                   (0x01U << GPIO_BSRR_BS8_Pos)            ///< Portx Set bit 8
-#define GPIO_BSRR_BS9_Pos               (9)
-#define GPIO_BSRR_BS9                   (0x01U << GPIO_BSRR_BS9_Pos)            ///< Portx Set bit 9
-#define GPIO_BSRR_BS10_Pos              (10)
-#define GPIO_BSRR_BS10                  (0x01U << GPIO_BSRR_BS10_Pos)           ///< Portx Set bit 10
-#define GPIO_BSRR_BS11_Pos              (11)
-#define GPIO_BSRR_BS11                  (0x01U << GPIO_BSRR_BS11_Pos)           ///< Portx Set bit 11
-#define GPIO_BSRR_BS12_Pos              (12)
-#define GPIO_BSRR_BS12                  (0x01U << GPIO_BSRR_BS12_Pos)           ///< Portx Set bit 12
-#define GPIO_BSRR_BS13_Pos              (13)
-#define GPIO_BSRR_BS13                  (0x01U << GPIO_BSRR_BS13_Pos)           ///< Portx Set bit 13
-#define GPIO_BSRR_BS14_Pos              (14)
-#define GPIO_BSRR_BS14                  (0x01U << GPIO_BSRR_BS14_Pos)           ///< Portx Set bit 14
-#define GPIO_BSRR_BS15_Pos              (15)
-#define GPIO_BSRR_BS15                  (0x01U << GPIO_BSRR_BS15_Pos)           ///< Portx Set bit 15
-
-#define GPIO_BSRR_BR0_Pos               (16)
-#define GPIO_BSRR_BR0                   (0x01U << GPIO_BSRR_BR0_Pos)            ///< Portx Reset bit 0
-#define GPIO_BSRR_BR1_Pos               (17)
-#define GPIO_BSRR_BR1                   (0x01U << GPIO_BSRR_BR1_Pos)            ///< Portx Reset bit 1
-#define GPIO_BSRR_BR2_Pos               (18)
-#define GPIO_BSRR_BR2                   (0x01U << GPIO_BSRR_BR2_Pos)            ///< Portx Reset bit 2
-#define GPIO_BSRR_BR3_Pos               (19)
-#define GPIO_BSRR_BR3                   (0x01U << GPIO_BSRR_BR3_Pos)            ///< Portx Reset bit 3
-#define GPIO_BSRR_BR4_Pos               (20)
-#define GPIO_BSRR_BR4                   (0x01U << GPIO_BSRR_BR4_Pos)            ///< Portx Reset bit 4
-#define GPIO_BSRR_BR5_Pos               (21)
-#define GPIO_BSRR_BR5                   (0x01U << GPIO_BSRR_BR5_Pos)            ///< Portx Reset bit 5
-#define GPIO_BSRR_BR6_Pos               (22)
-#define GPIO_BSRR_BR6                   (0x01U << GPIO_BSRR_BR6_Pos)            ///< Portx Reset bit 6
-#define GPIO_BSRR_BR7_Pos               (23)
-#define GPIO_BSRR_BR7                   (0x01U << GPIO_BSRR_BR7_Pos)            ///< Portx Reset bit 7
-#define GPIO_BSRR_BR8_Pos               (24)
-#define GPIO_BSRR_BR8                   (0x01U << GPIO_BSRR_BR8_Pos)            ///< Portx Reset bit 8
-#define GPIO_BSRR_BR9_Pos               (25)
-#define GPIO_BSRR_BR9                   (0x01U << GPIO_BSRR_BR9_Pos)            ///< Portx Reset bit 9
-#define GPIO_BSRR_BR10_Pos              (26)
-#define GPIO_BSRR_BR10                  (0x01U << GPIO_BSRR_BR10_Pos)           ///< Portx Reset bit 10
-#define GPIO_BSRR_BR11_Pos              (27)
-#define GPIO_BSRR_BR11                  (0x01U << GPIO_BSRR_BR11_Pos)           ///< Portx Reset bit 11
-#define GPIO_BSRR_BR12_Pos              (28)
-#define GPIO_BSRR_BR12                  (0x01U << GPIO_BSRR_BR12_Pos)           ///< Portx Reset bit 12
-#define GPIO_BSRR_BR13_Pos              (29)
-#define GPIO_BSRR_BR13                  (0x01U << GPIO_BSRR_BR13_Pos)           ///< Portx Reset bit 13
-#define GPIO_BSRR_BR14_Pos              (30)
-#define GPIO_BSRR_BR14                  (0x01U << GPIO_BSRR_BR14_Pos)           ///< Portx Reset bit 14
-#define GPIO_BSRR_BR15_Pos              (31)
-#define GPIO_BSRR_BR15                  (0x01U << GPIO_BSRR_BR15_Pos)           ///< Portx Reset bit 15
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_BRR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_BRR_BR_Pos                 (0)
-#define GPIO_BRR_BR                     (0xFFFFU << GPIO_BRR_BR_Pos)            ///< Portx Reset
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_BRR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_BRR_BR0_Pos               (0)
-#define GPIO_BRR_BR0                   (0x01U << GPIO_BRR_BR0_Pos)            ///< Portx Set bit 0
-#define GPIO_BRR_BR1_Pos               (1)
-#define GPIO_BRR_BR1                   (0x01U << GPIO_BRR_BR1_Pos)            ///< Portx Set bit 1
-#define GPIO_BRR_BR2_Pos               (2)
-#define GPIO_BRR_BR2                   (0x01U << GPIO_BRR_BR2_Pos)            ///< Portx Set bit 2
-#define GPIO_BRR_BR3_Pos               (3)
-#define GPIO_BRR_BR3                   (0x01U << GPIO_BRR_BR3_Pos)            ///< Portx Set bit 3
-#define GPIO_BRR_BR4_Pos               (4)
-#define GPIO_BRR_BR4                   (0x01U << GPIO_BRR_BR4_Pos)            ///< Portx Set bit 4
-#define GPIO_BRR_BR5_Pos               (5)
-#define GPIO_BRR_BR5                   (0x01U << GPIO_BRR_BR5_Pos)            ///< Portx Set bit 5
-#define GPIO_BRR_BR6_Pos               (6)
-#define GPIO_BRR_BR6                   (0x01U << GPIO_BRR_BR6_Pos)            ///< Portx Set bit 6
-#define GPIO_BRR_BR7_Pos               (7)
-#define GPIO_BRR_BR7                   (0x01U << GPIO_BRR_BR7_Pos)            ///< Portx Set bit 7
-#define GPIO_BRR_BR8_Pos               (8)
-#define GPIO_BRR_BR8                   (0x01U << GPIO_BRR_BR8_Pos)            ///< Portx Set bit 8
-#define GPIO_BRR_BR9_Pos               (9)
-#define GPIO_BRR_BR9                   (0x01U << GPIO_BRR_BR9_Pos)            ///< Portx Set bit 9
-#define GPIO_BRR_BR10_Pos              (10)
-#define GPIO_BRR_BR10                  (0x01U << GPIO_BRR_BR10_Pos)           ///< Portx Set bit 10
-#define GPIO_BRR_BR11_Pos              (11)
-#define GPIO_BRR_BR11                  (0x01U << GPIO_BRR_BR11_Pos)           ///< Portx Set bit 11
-#define GPIO_BRR_BR12_Pos              (12)
-#define GPIO_BRR_BR12                  (0x01U << GPIO_BRR_BR12_Pos)           ///< Portx Set bit 12
-#define GPIO_BRR_BR13_Pos              (13)
-#define GPIO_BRR_BR13                  (0x01U << GPIO_BRR_BR13_Pos)           ///< Portx Set bit 13
-#define GPIO_BRR_BR14_Pos              (14)
-#define GPIO_BRR_BR14                  (0x01U << GPIO_BRR_BR14_Pos)           ///< Portx Set bit 14
-#define GPIO_BRR_BR15_Pos              (15)
-#define GPIO_BRR_BR15                  (0x01U << GPIO_BRR_BR15_Pos)           ///< Portx Set bit 15
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_LCKR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_LCKR_LCK_Pos               (0)
-#define GPIO_LCKR_LCK                   (0xFFFFU << GPIO_LCKR_LCK_Pos)          ///< Portx Lock
-#define GPIO_LCKR_LCKK_Pos              (16)
-#define GPIO_LCKR_LCKK                  (0x01U << GPIO_LCKR_LCKK_Pos)           ///< Lock key
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_LCKR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_LCKR_LCK0_Pos               (0)
-#define GPIO_LCKR_LCK0                   (0x01U << GPIO_LCKR_LCK0_Pos)          ///< Portx Set bit 0
-#define GPIO_LCKR_LCK1_Pos               (1)
-#define GPIO_LCKR_LCK1                   (0x01U << GPIO_LCKR_LCK1_Pos)          ///< Portx Set bit 1
-#define GPIO_LCKR_LCK2_Pos               (2)
-#define GPIO_LCKR_LCK2                   (0x01U << GPIO_LCKR_LCK2_Pos)          ///< Portx Set bit 2
-#define GPIO_LCKR_LCK3_Pos               (3)
-#define GPIO_LCKR_LCK3                   (0x01U << GPIO_LCKR_LCK3_Pos)          ///< Portx Set bit 3
-#define GPIO_LCKR_LCK4_Pos               (4)
-#define GPIO_LCKR_LCK4                   (0x01U << GPIO_LCKR_LCK4_Pos)          ///< Portx Set bit 4
-#define GPIO_LCKR_LCK5_Pos               (5)
-#define GPIO_LCKR_LCK5                   (0x01U << GPIO_LCKR_LCK5_Pos)          ///< Portx Set bit 5
-#define GPIO_LCKR_LCK6_Pos               (6)
-#define GPIO_LCKR_LCK6                   (0x01U << GPIO_LCKR_LCK6_Pos)          ///< Portx Set bit 6
-#define GPIO_LCKR_LCK7_Pos               (7)
-#define GPIO_LCKR_LCK7                   (0x01U << GPIO_LCKR_LCK7_Pos)          ///< Portx Set bit 7
-#define GPIO_LCKR_LCK8_Pos               (8)
-#define GPIO_LCKR_LCK8                   (0x01U << GPIO_LCKR_LCK8_Pos)          ///< Portx Set bit 8
-#define GPIO_LCKR_LCK9_Pos               (9)
-#define GPIO_LCKR_LCK9                   (0x01U << GPIO_LCKR_LCK9_Pos)          ///< Portx Set bit 9
-#define GPIO_LCKR_LCK10_Pos              (10)
-#define GPIO_LCKR_LCK10                  (0x01U << GPIO_LCKR_LCK10_Pos)         ///< Portx Set bit 10
-#define GPIO_LCKR_LCK11_Pos              (11)
-#define GPIO_LCKR_LCK11                  (0x01U << GPIO_LCKR_LCK11_Pos)         ///< Portx Set bit 11
-#define GPIO_LCKR_LCK12_Pos              (12)
-#define GPIO_LCKR_LCK12                  (0x01U << GPIO_LCKR_LCK12_Pos)         ///< Portx Set bit 12
-#define GPIO_LCKR_LCK13_Pos              (13)
-#define GPIO_LCKR_LCK13                  (0x01U << GPIO_LCKR_LCK13_Pos)         ///< Portx Set bit 13
-#define GPIO_LCKR_LCK14_Pos              (14)
-#define GPIO_LCKR_LCK14                  (0x01U << GPIO_LCKR_LCK14_Pos)         ///< Portx Set bit 14
-#define GPIO_LCKR_LCK15_Pos              (15)
-#define GPIO_LCKR_LCK15                  (0x01U << GPIO_LCKR_LCK15_Pos)         ///< Portx Set bit 15
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_DCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_DCR_PX0_Pos                (0)
-#define GPIO_DCR_PX0                    (0x03U << GPIO_DCR_PX0_Pos)                  ///< PX0[1:0] bits (pinx configuration bits, pin 0)
-#define GPIO_DCR_PX0_MODE0              (0x00U << GPIO_DCR_PX0_Pos)                  ///< Mode = 0
-#define GPIO_DCR_PX0_MODE1              (0x01U << GPIO_DCR_PX0_Pos)                  ///< Mode = 1
-#define GPIO_DCR_PX0_MODE2              (0x02U << GPIO_DCR_PX0_Pos)                  ///< Mode = 2
-#define GPIO_DCR_PX0_MODE3              (0x03U << GPIO_DCR_PX0_Pos)                  ///< Mode = 3
-#define GPIO_DCR_PX1_Pos                (2)
-#define GPIO_DCR_PX1                    (0x03U << GPIO_DCR_PX1_Pos)                  ///< PX1[1:0] bits (pinx configuration bits, pin 1)
-#define GPIO_DCR_PX1_MODE0              (0x00U << GPIO_DCR_PX1_Pos)                  ///< Mode = 0
-#define GPIO_DCR_PX1_MODE1              (0x01U << GPIO_DCR_PX1_Pos)                  ///< Mode = 1
-#define GPIO_DCR_PX1_MODE2              (0x02U << GPIO_DCR_PX1_Pos)                  ///< Mode = 2
-#define GPIO_DCR_PX1_MODE3              (0x03U << GPIO_DCR_PX1_Pos)                  ///< Mode = 3
-#define GPIO_DCR_PX2_Pos                (4)
-#define GPIO_DCR_PX2                    (0x03U << GPIO_DCR_PX2_Pos)                  ///< PX2[1:0] bits (pinx configuration bits, pin 2)
-#define GPIO_DCR_PX2_MODE0              (0x00U << GPIO_DCR_PX2_Pos)                  ///< Mode = 0
-#define GPIO_DCR_PX2_MODE1              (0x01U << GPIO_DCR_PX2_Pos)                  ///< Mode = 1
-#define GPIO_DCR_PX2_MODE2              (0x02U << GPIO_DCR_PX2_Pos)                  ///< Mode = 2
-#define GPIO_DCR_PX2_MODE3              (0x03U << GPIO_DCR_PX2_Pos)                  ///< Mode = 3
-#define GPIO_DCR_PX3_Pos                (6)
-#define GPIO_DCR_PX3                    (0x03U << GPIO_DCR_PX3_Pos)                  ///< PX3[1:0] bits (pinx configuration bits, pin 3)
-#define GPIO_DCR_PX3_MODE0              (0x00U << GPIO_DCR_PX3_Pos)                  ///< Mode = 0
-#define GPIO_DCR_PX3_MODE1              (0x01U << GPIO_DCR_PX3_Pos)                  ///< Mode = 1
-#define GPIO_DCR_PX3_MODE2              (0x02U << GPIO_DCR_PX3_Pos)                  ///< Mode = 2
-#define GPIO_DCR_PX3_MODE3              (0x03U << GPIO_DCR_PX3_Pos)                  ///< Mode = 3
-
-#define GPIO_DCR_PX4_Pos                (8)
-#define GPIO_DCR_PX4                    (0x03U << GPIO_DCR_PX4_Pos)                  ///< PX4[1:0] bits (pinx configuration bits, pin 4)
-#define GPIO_DCR_PX4_MODE0              (0x00U << GPIO_DCR_PX4_Pos)                  ///< Mode = 0
-#define GPIO_DCR_PX4_MODE1              (0x01U << GPIO_DCR_PX4_Pos)                  ///< Mode = 1
-#define GPIO_DCR_PX4_MODE2              (0x02U << GPIO_DCR_PX4_Pos)                  ///< Mode = 2
-#define GPIO_DCR_PX4_MODE3              (0x03U << GPIO_DCR_PX4_Pos)                  ///< Mode = 3
-
-#define GPIO_DCR_PX5_Pos                (10)
-#define GPIO_DCR_PX5                    (0x03U << GPIO_DCR_PX5_Pos)                  ///< PX5[1:0] bits (pinx configuration bits, pin 5)
-#define GPIO_DCR_PX5_MODE0              (0x00U << GPIO_DCR_PX5_Pos)                  ///< Mode = 0
-#define GPIO_DCR_PX5_MODE1              (0x01U << GPIO_DCR_PX5_Pos)                  ///< Mode = 1
-#define GPIO_DCR_PX5_MODE2              (0x02U << GPIO_DCR_PX5_Pos)                  ///< Mode = 2
-#define GPIO_DCR_PX5_MODE3              (0x03U << GPIO_DCR_PX5_Pos)                  ///< Mode = 3
-
-#define GPIO_DCR_PX6_Pos                (12)
-#define GPIO_DCR_PX6                    (0x03U << GPIO_DCR_PX6_Pos)                  ///< PX6[1:0] bits (pinx configuration bits, pin 6)
-#define GPIO_DCR_PX6_MODE0              (0x00U << GPIO_DCR_PX6_Pos)                  ///< Mode = 0
-#define GPIO_DCR_PX6_MODE1              (0x01U << GPIO_DCR_PX6_Pos)                  ///< Mode = 1
-#define GPIO_DCR_PX6_MODE2              (0x02U << GPIO_DCR_PX6_Pos)                  ///< Mode = 2
-#define GPIO_DCR_PX6_MODE3              (0x03U << GPIO_DCR_PX6_Pos)                  ///< Mode = 3
-
-#define GPIO_DCR_PX7_Pos                (14)
-#define GPIO_DCR_PX7                    (0x03U << GPIO_DCR_PX7_Pos)                  ///< PX7[1:0] bits (pinx configuration bits, pin 7)
-#define GPIO_DCR_PX7_MODE0              (0x00U << GPIO_DCR_PX7_Pos)                  ///< Mode = 0
-#define GPIO_DCR_PX7_MODE1              (0x01U << GPIO_DCR_PX7_Pos)                  ///< Mode = 1
-#define GPIO_DCR_PX7_MODE2              (0x02U << GPIO_DCR_PX7_Pos)                  ///< Mode = 2
-#define GPIO_DCR_PX7_MODE3              (0x03U << GPIO_DCR_PX7_Pos)                  ///< Mode = 3
-
-#define GPIO_DCR_PX8_Pos                (16)
-#define GPIO_DCR_PX8                    (0x03U << GPIO_DCR_PX8_Pos)                  ///< PX8[1:0] bits (pinx configuration bits, pin 8)
-#define GPIO_DCR_PX8_MODE0              (0x00U << GPIO_DCR_PX8_Pos)                  ///< Mode = 0
-#define GPIO_DCR_PX8_MODE1              (0x01U << GPIO_DCR_PX8_Pos)                  ///< Mode = 1
-#define GPIO_DCR_PX8_MODE2              (0x02U << GPIO_DCR_PX8_Pos)                  ///< Mode = 2
-#define GPIO_DCR_PX8_MODE3              (0x03U << GPIO_DCR_PX8_Pos)                  ///< Mode = 3
-
-#define GPIO_DCR_PX9_Pos                (18)
-#define GPIO_DCR_PX9                    (0x03U << GPIO_DCR_PX9_Pos)                  ///< PX9[1:0] bits (pinx configuration bits, pin 9)
-#define GPIO_DCR_PX9_MODE0              (0x00U << GPIO_DCR_PX9_Pos)                  ///< Mode = 0
-#define GPIO_DCR_PX9_MODE1              (0x01U << GPIO_DCR_PX9_Pos)                  ///< Mode = 1
-#define GPIO_DCR_PX9_MODE2              (0x02U << GPIO_DCR_PX9_Pos)                  ///< Mode = 2
-#define GPIO_DCR_PX9_MODE3              (0x03U << GPIO_DCR_PX9_Pos)                  ///< Mode = 3
-
-#define GPIO_DCR_PX10_Pos               (20)
-#define GPIO_DCR_PX10                   (0x03U << GPIO_DCR_PX10_Pos)                 ///< PX10[1:0] bits (pinx configuration bits, pin 10)
-#define GPIO_DCR_PX10_MODE0             (0x00U << GPIO_DCR_PX10_Pos)                 ///< Mode = 0
-#define GPIO_DCR_PX10_MODE1             (0x01U << GPIO_DCR_PX10_Pos)                 ///< Mode = 1
-#define GPIO_DCR_PX10_MODE2             (0x02U << GPIO_DCR_PX10_Pos)                 ///< Mode = 2
-#define GPIO_DCR_PX10_MODE3             (0x03U << GPIO_DCR_PX10_Pos)                 ///< Mode = 3
-
-#define GPIO_DCR_PX11_Pos               (22)
-#define GPIO_DCR_PX11                   (0x03U << GPIO_DCR_PX11_Pos)                 ///< PX11[1:0] bits (pinx configuration bits, pin 11)
-#define GPIO_DCR_PX11_MODE0             (0x00U << GPIO_DCR_PX11_Pos)                 ///< Mode = 0
-#define GPIO_DCR_PX11_MODE1             (0x01U << GPIO_DCR_PX11_Pos)                 ///< Mode = 1
-#define GPIO_DCR_PX11_MODE2             (0x02U << GPIO_DCR_PX11_Pos)                 ///< Mode = 2
-#define GPIO_DCR_PX11_MODE3             (0x03U << GPIO_DCR_PX11_Pos)                 ///< Mode = 3
-#define GPIO_DCR_PX12_Pos               (24)
-#define GPIO_DCR_PX12                   (0x03U << GPIO_DCR_PX12_Pos)                 ///< PX12[1:0] bits (pinx configuration bits, pin 12)
-#define GPIO_DCR_PX12_MODE0             (0x00U << GPIO_DCR_PX12_Pos)                 ///< Mode = 0
-#define GPIO_DCR_PX12_MODE1             (0x01U << GPIO_DCR_PX12_Pos)                 ///< Mode = 1
-#define GPIO_DCR_PX12_MODE2             (0x02U << GPIO_DCR_PX12_Pos)                 ///< Mode = 2
-#define GPIO_DCR_PX12_MODE3             (0x03U << GPIO_DCR_PX12_Pos)                 ///< Mode = 3
-#define GPIO_DCR_PX13_Pos               (26)
-#define GPIO_DCR_PX13                   (0x03U << GPIO_DCR_PX13_Pos)                 ///< PX13[1:0] bits (pinx configuration bits, pin 13)
-#define GPIO_DCR_PX13_MODE0             (0x00U << GPIO_DCR_PX13_Pos)                 ///< Mode = 0
-#define GPIO_DCR_PX13_MODE1             (0x01U << GPIO_DCR_PX13_Pos)                 ///< Mode = 1
-#define GPIO_DCR_PX13_MODE2             (0x02U << GPIO_DCR_PX13_Pos)                 ///< Mode = 2
-#define GPIO_DCR_PX13_MODE3             (0x03U << GPIO_DCR_PX13_Pos)                 ///< Mode = 3
-
-#define GPIO_DCR_PX14_Pos               (28)
-#define GPIO_DCR_PX14                   (0x03U << GPIO_DCR_PX14_Pos)                 ///< PX14[1:0] bits (pinx configuration bits, pin 14)
-#define GPIO_DCR_PX14_MODE0             (0x00U << GPIO_DCR_PX14_Pos)                 ///< Mode = 0
-#define GPIO_DCR_PX14_MODE1             (0x01U << GPIO_DCR_PX14_Pos)                 ///< Mode = 1
-#define GPIO_DCR_PX14_MODE2             (0x02U << GPIO_DCR_PX14_Pos)                 ///< Mode = 2
-#define GPIO_DCR_PX14_MODE3             (0x03U << GPIO_DCR_PX14_Pos)                 ///< Mode = 3
-#define GPIO_DCR_PX15_Pos               (30)
-#define GPIO_DCR_PX15                   (0x03U << GPIO_DCR_PX15_Pos)                 ///< PX15[1:0] bits (pinx configuration bits, pin 15)
-#define GPIO_DCR_PX15_MODE0             (0x00U << GPIO_DCR_PX15_Pos)                 ///< Mode = 0
-#define GPIO_DCR_PX15_MODE1             (0x01U << GPIO_DCR_PX15_Pos)                 ///< Mode = 1
-#define GPIO_DCR_PX15_MODE2             (0x02U << GPIO_DCR_PX15_Pos)                 ///< Mode = 2
-#define GPIO_DCR_PX15_MODE3             (0x03U << GPIO_DCR_PX15_Pos)                 ///< Mode = 3
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_AFRL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_AFRL_AFR0_Pos              (0)
-#define GPIO_AFRL_AFR0                  (0x0FU << GPIO_AFRL_AFR0_Pos)           ///< Multiplexing function selection for bit 0 of portx
-#define GPIO_AFRL_AFR1_Pos              (4)
-#define GPIO_AFRL_AFR1                  (0x0FU << GPIO_AFRL_AFR1_Pos)           ///< Multiplexing function selection for bit 1 of portx
-#define GPIO_AFRL_AFR2_Pos              (8)
-#define GPIO_AFRL_AFR2                  (0x0FU << GPIO_AFRL_AFR2_Pos)           ///< Multiplexing function selection for bit 2 of portx
-#define GPIO_AFRL_AFR3_Pos              (12)
-#define GPIO_AFRL_AFR3                  (0x0FU << GPIO_AFRL_AFR3_Pos)           ///< Multiplexing function selection for bit 3 of portx
-#define GPIO_AFRL_AFR4_Pos              (16)
-#define GPIO_AFRL_AFR4                  (0x0FU << GPIO_AFRL_AFR4_Pos)           ///< Multiplexing function selection for bit 4 of portx
-#define GPIO_AFRL_AFR5_Pos              (20)
-#define GPIO_AFRL_AFR5                  (0x0FU << GPIO_AFRL_AFR5_Pos)           ///< Multiplexing function selection for bit 5 of portx
-#define GPIO_AFRL_AFR6_Pos              (24)
-#define GPIO_AFRL_AFR6                  (0x0FU << GPIO_AFRL_AFR6_Pos)           ///< Multiplexing function selection for bit 6 of portx
-#define GPIO_AFRL_AFR7_Pos              (28)
-#define GPIO_AFRL_AFR7                  (0x0FU << GPIO_AFRL_AFR7_Pos)           ///< Multiplexing function selection for bit 7 of portx
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief GPIO_AFRH Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define GPIO_AFRH_AFR8_Pos              (0)
-#define GPIO_AFRH_AFR8                  (0x0FU << GPIO_AFRH_AFR8_Pos)           ///< Multiplexing function selection for bit 8 of portx
-#define GPIO_AFRH_AFR9_Pos              (4)
-#define GPIO_AFRH_AFR9                  (0x0FU << GPIO_AFRH_AFR9_Pos)           ///< Multiplexing function selection for bit 9 of portx
-#define GPIO_AFRH_AFR10_Pos             (8)
-#define GPIO_AFRH_AFR10                 (0x0FU << GPIO_AFRH_AFR10_Pos)          ///< Multiplexing function selection for bit 10 of portx
-#define GPIO_AFRH_AFR11_Pos             (12)
-#define GPIO_AFRH_AFR11                 (0x0FU << GPIO_AFRH_AFR11_Pos)          ///< Multiplexing function selection for bit 11 of portx
-#define GPIO_AFRH_AFR12_Pos             (16)
-#define GPIO_AFRH_AFR12                 (0x0FU << GPIO_AFRH_AFR12_Pos)          ///< Multiplexing function selection for bit 12 of portx
-#define GPIO_AFRH_AFR13_Pos             (20)
-#define GPIO_AFRH_AFR13                 (0x0FU << GPIO_AFRH_AFR13_Pos)          ///< Multiplexing function selection for bit 13 of portx
-#define GPIO_AFRH_AFR14_Pos             (24)
-#define GPIO_AFRH_AFR14                 (0x0FU << GPIO_AFRH_AFR14_Pos)          ///< Multiplexing function selection for bit 14 of portx
-#define GPIO_AFRH_AFR15_Pos             (28)
-#define GPIO_AFRH_AFR15                 (0x0FU << GPIO_AFRH_AFR15_Pos)          ///< Multiplexing function selection for bit 15 of portx
-#define GPIO_AF_MODEMASK                (0x0FU)                                 ///< Mode = 0
-#define GPIO_AF_MODE0                   (0x00U)                                 ///< Mode = 0
-#define GPIO_AF_MODE1                   (0x01U)                                 ///< Mode = 1
-#define GPIO_AF_MODE2                   (0x02U)                                 ///< Mode = 2
-#define GPIO_AF_MODE3                   (0x03U)                                 ///< Mode = 3
-#define GPIO_AF_MODE4                   (0x04U)                                 ///< Mode = 4
-#define GPIO_AF_MODE5                   (0x05U)                                 ///< Mode = 5
-#define GPIO_AF_MODE6                   (0x06U)                                 ///< Mode = 6
-#define GPIO_AF_MODE7                   (0x07U)                                 ///< Mode = 7
-#define GPIO_AF_MODE8                   (0x08U)                                 ///< Mode = 8 
-#define GPIO_AF_MODE9                   (0x09U)                                 ///< Mode = 9 
-#define GPIO_AF_MODE10                  (0x0AU)                                 ///< Mode = 10
-#define GPIO_AF_MODE11                  (0x0BU)                                 ///< Mode = 11
-#define GPIO_AF_MODE12                  (0x0CU)                                 ///< Mode = 12
-#define GPIO_AF_MODE13                  (0x0DU)                                 ///< Mode = 13
-#define GPIO_AF_MODE14                  (0x0EU)                                 ///< Mode = 14
-#define GPIO_AF_MODE15                  (0x0FU)                                 ///< Mode = 15
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h
deleted file mode 100644
index e12f107e3..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_i2c.h
+++ /dev/null
@@ -1,635 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_i2c.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_I2C_H
-#define __REG_I2C_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C1_BASE                       (APB1PERIPH_BASE + 0x5400)              ///< Base Address: 0x40005400
-#define I2C2_BASE                       (APB1PERIPH_BASE + 0x5800)              ///< Base Address: 0x40005800
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-#undef USENCOMBINEREGISTER
-#undef USENNEWREGISTER
-#undef USENOLDREGISTER
-#define USENCOMBINEREGISTER
-#ifdef USENCOMBINEREGISTER
-typedef struct {
-    union {
-        __IO u32 CR;                                                           ///< Control Register                               offset: 0x00
-        __IO u32 IC_CON;
-    };
-    union {
-        __IO u32 TAR;                                                          ///< Target Address Register                        offset: 0x04
-        __IO u32 IC_TAR;
-    };
-    union {
-        __IO u32 SAR;                                                          ///< Slave Address Register                         offset: 0x08
-        __IO u32 IC_SAR;
-    };
-    __IO u32 IC_HS_MADDR_RESERVED;                                             ///< Reserved Register                              offset: 0x0C
-    union {
-        __IO u32 DR;                                                           ///< Data Command Register                          offset: 0x10
-        __IO u32 IC_DATA_CMD;
-    };
-    union {
-        __IO u32 SSHR;                                                         ///< SCL High Period Count for Std. Speed Register  offset: 0x14
-        __IO u32 IC_SS_SCL_HCNT;
-    };
-    union {
-        __IO u32 SSLR;                                                         ///< SCL Low Period Count for Std. Speed Register   offset: 0x18
-        __IO u32 IC_SS_SCL_LCNT;
-    };
-    union {
-        __IO u32 FSHR;                                                         ///< SCL High Period Count for Fast Speed Register  offset: 0x1C
-        __IO u32 IC_FS_SCL_HCNT;
-    };
-    union {
-        __IO u32 FSLR;                                                         ///< SCL Low Period Count for Fast Speed Register   offset: 0x20
-        __IO u32 IC_FS_SCL_LCNT;
-    };
-    __IO u32 IC_HS_SCL_HCNT_RESERVED;                                          ///< Reserved Register                              offset: 0x24
-    __IO u32 IC_HS_SCL_LCNT_RESERVED;                                          ///< Reserved Register                              offset: 0x28
-    union {
-        __IO u32 ISR;                                                          ///< Interrupt Status Register                      offset: 0x2C
-        __IO u32 IC_INTR_STAT;
-    };
-    union {
-        __IO u32 IMR;                                                          ///< Interrupt Mask Register                        offset: 0x30
-        __IO u32 IC_INTR_MASK;
-    };
-    union {
-        __IO u32 RAWISR;                                                       ///< RAW Interrupt Status Register                  offset: 0x34
-        __IO u32 IC_RAW_INTR_STAT;
-    };
-    union {
-        __IO u32 RXTLR;                                                        ///< Receive FIFO Threshold Level Register          offset: 0x38
-        __IO u32 IC_RX_TL;
-    };
-    union {
-        __IO u32 TXTLR;                                                        ///< Transmit FIFO Threshold Level Register         offset: 0x3C
-        __IO u32 IC_TX_TL;
-    };
-    union {
-        __IO u32 ICR;                                                          ///< Clear All Interrupt Register                   offset: 0x40
-        __IO u32 IC_CLR_INTR;
-    };
-    union {
-        __IO u32 RX_UNDER;                                                     ///< Clear RX_UNDER Interrupt Register              offset: 0x44
-        __IO u32 IC_CLR_RX_UNDER;
-    };
-    union {
-        __IO u32 RX_OVER;                                                      ///< Clear RX_OVER Interrupt Register               offset: 0x48
-        __IO u32 IC_CLR_RX_OVER;
-    };
-    union {
-        __IO u32 TX_OVER;                                                      ///< Clear TX_OVER Interrupt Register               offset: 0x4C
-        __IO u32 IC_CLR_TX_OVER;
-    };
-    union {
-        __IO u32 RD_REQ;                                                       ///< Clear RD_REQ Interrupt Register                offset: 0x50
-        __IO u32 IC_CLR_RD_REQ;
-    };
-    union {
-        __IO u32 TX_ABRT;                                                      ///< Clear TX_ABRT Interrupt Register               offset: 0x54
-        __IO u32 IC_CLR_TX_ABRT;
-    };
-    union {
-        __IO u32 RX_DONE;                                                      ///< Clear RX_DONE Interrupt Register               offset: 0x58
-        __IO u32 IC_CLR_RX_DONE;
-    };
-    union {
-        __IO u32 ACTIV;                                                        ///< Clear ACTIVITY Interrupt Register              offset: 0x5C
-        __IO u32 IC_CLR_ACTIVITY;
-    };
-    union {
-        __IO u32 STOP;                                                         ///< Clear STOP_DET Interrupt Register              offset: 0x60
-        __IO u32 IC_CLR_STOP_DET;
-    };
-    union {
-        __IO u32 START;                                                        ///< Clear START_DET Interrupt Register             offset: 0x64
-        __IO u32 IC_CLR_START_DET;
-    };
-    union {
-        __IO u32 GC;                                                           ///< Clear GEN_CALL Interrupt Register              offset: 0x68
-        __IO u32 IC_CLR_GEN_CALL;
-    };
-    union {
-        __IO u32 ENR;                                                          ///< Enable Register                                offset: 0x6C
-        __IO u32 IC_ENABLE;
-    };
-    union {
-        __IO u32 SR;                                                           ///< Status Register                                offset: 0x70
-        __IO u32 IC_STATUS;
-    };
-    union {
-        __IO u32 TXFLR;                                                        ///< Transmit FIFO Level Register                   offset: 0x74
-        __IO u32 IC_TXFLR;
-    };
-    union {
-        __IO u32 RXFLR;                                                        ///< Receive FIFO Level Register                    offset: 0x78
-        __IO u32 IC_RXFLR;
-    };
-    union {
-        __IO u32 HOLD;                                                         ///< SDA Hold Time Register                         offset: 0x7C
-        __IO u32 IC_SDA_HOLD;
-    };
-    __IO u32 RESERVED28;                                                       ///IC_TX_ABRT_SOURCE_RESERVED;
-    __IO u32 RESERVED29;                                                       ///IC_SLV_DATA_NACK_ONLY_RESERVED;
-
-    union {
-        __IO u32 DMA;                                                          ///< DMA Control Register                           offset: 0x88
-        __IO u32 IC_DMA_CR;
-    };
-    __IO u32 RESERVED30;                                                       ///IC_DMA_TDLR_RESERVED;
-    __IO u32 RESERVED31;                                                       ///IC_DMA_RDLR_RESERVED;
-    union {
-        __IO u32 SETUP;                                                        ///< SDA Setup Time Register                        offset: 0x94
-        __IO u32 IC_SDA_SETUP;
-    };
-    union {
-        __IO u32 GCR;                                                          ///< ACK General Call Register                      offset: 0x98
-        __IO u32 IC_ACK_GENERAL_CALL;
-    };
-    __IO u32 RESERVED32a;                                                       ///_RESERVED;                                     offset: 0x9C
-    __IO u32 RESERVED33;                                                        ///_RESERVED;                                     offset: 0xA0
-    __IO u32 RESERVED34;                                                        ///_RESERVED;                                     offset: 0xA4
-    __IO u32 RESERVED35;                                                        ///_RESERVED;                                     offset: 0xA8
-    __IO u32 RESERVED36;                                                        ///_RESERVED;                                     offset: 0xAC    
-    __IO u32 SLVMASK;                                                           ///<I2C Slave Mode Mask Register                  offset: 0xB0
-    __IO u32 SLVRCVADDR;                                                        ///<I2C Slave Mode Address Register               offset: 0xB4
-
-} I2C_TypeDef;
-#endif
-#ifdef USENNEWREGISTER
-typedef struct {
-    __IO u32 CR;                                                                ///< Control Register                               offset: 0x00
-    __IO u32 TAR;                                                               ///< Target Address Register                        offset: 0x04
-    __IO u32 SAR;                                                               ///< Slave Address Register                         offset: 0x08
-    __IO u32 RESERVED3;
-    __IO u32 DR;                                                                ///< Data Command Register                          offset: 0x10
-    __IO u32 SSHR;                                                              ///< SCL High Period Count for Std. Speed Register  offset: 0x14
-    __IO u32 SSLR;                                                              ///< SCL Low Period Count for Std. Speed Register   offset: 0x18
-    __IO u32 FSHR;                                                              ///< SCL High Period Count for Fast Speed Register  offset: 0x1C
-    __IO u32 FSLR;                                                              ///< SCL Low Period Count for Fast Speed Register   offset: 0x20
-    __IO u32 RESERVED9;
-    __IO u32 RESERVED10;
-    __IO u32 ISR;                                                               ///< Interrupt Status Register                      offset: 0x2C
-    __IO u32 IMR;                                                               ///< Interrupt Mask Register                        offset: 0x30
-    __IO u32 RAWISR;                                                            ///< RAW Interrupt Status Register                  offset: 0x34
-    __IO u32 RXTLR;                                                             ///< Receive FIFO Threshold Level Register          offset: 0x38
-    __IO u32 TXTLR;                                                             ///< Transmit FIFO Threshold Level Register         offset: 0x3C
-    __IO u32 ICR;                                                               ///< Clear All Interrupt Register                   offset: 0x40
-    __IO u32 RX_UNDER;                                                          ///< Clear RX_UNDER Interrupt Register              offset: 0x44
-    __IO u32 RX_OVER;                                                           ///< Clear RX_OVER Interrupt Register               offset: 0x48
-    __IO u32 TX_OVER;                                                           ///< Clear TX_OVER Interrupt Register               offset: 0x4C
-    __IO u32 RD_REQ;                                                            ///< Clear RD_REQ Interrupt Register                offset: 0x50
-    __IO u32 TX_ABRT;                                                           ///< Clear TX_ABRT Interrupt Register               offset: 0x54
-    __IO u32 RX_DONE;                                                           ///< Clear RX_DONE Interrupt Register               offset: 0x58
-    __IO u32 ACTIV;                                                             ///< Clear ACTIVITY Interrupt Register              offset: 0x5C
-    __IO u32 STOP;                                                              ///< Clear STOP_DET Interrupt Register              offset: 0x60
-    __IO u32 START;                                                             ///< Clear START_DET Interrupt Register             offset: 0x64
-    __IO u32 GC;                                                                ///< Clear GEN_CALL Interrupt Register              offset: 0x68
-    __IO u32 ENR;                                                               ///< Enable Register                                offset: 0x6C
-    __IO u32 SR;                                                                ///< Status Register                                offset: 0x70
-    __IO u32 TXFLR;                                                             ///< Transmit FIFO Level Register                   offset: 0x74
-    __IO u32 RXFLR;                                                             ///< Receive FIFO Level Register                    offset: 0x78
-    __IO u32 HOLD;                                                              ///< SDA Hold Time Register                         offset: 0x7C
-    __IO u32 RESERVED28;
-    __IO u32 RESERVED29;
-    __IO u32 RESERVED30;
-    __IO u32 RESERVED30a;
-    __IO u32 SETUP;                                                             ///< SDA Setup Time Register                        offset: 0x94
-    __IO u32 GCR;                                                               ///< ACK General Call Register                      offset: 0x98
-} I2C_TypeDef;
-#endif
-#ifdef USENOLDREGISTER
-typedef struct {
-    __IO u32 IC_CON;
-    __IO u32 IC_TAR;
-    __IO u32 IC_SAR;
-    __IO u32 IC_HS_MADDR_RESERVED;
-    __IO u32 IC_DATA_CMD;
-    __IO u32 IC_SS_SCL_HCNT;
-    __IO u32 IC_SS_SCL_LCNT;
-    __IO u32 IC_FS_SCL_HCNT;
-    __IO u32 IC_FS_SCL_LCNT;
-    __IO u32 IC_HS_SCL_HCNT_RESERVED;
-    __IO u32 IC_HS_SCL_LCNT_RESERVED;
-    __IO u32 IC_INTR_STAT;
-    __IO u32 IC_INTR_MASK;
-    __IO u32 IC_RAW_INTR_STAT;
-    __IO u32 IC_RX_TL;
-    __IO u32 IC_TX_TL;
-    __IO u32 IC_CLR_INTR;
-    __IO u32 IC_CLR_RX_UNDER;
-    __IO u32 IC_CLR_RX_OVER;
-    __IO u32 IC_CLR_TX_OVER;
-    __IO u32 IC_CLR_RD_REQ;
-    __IO u32 IC_CLR_TX_ABRT;
-    __IO u32 IC_CLR_RX_DONE;
-    __IO u32 IC_CLR_ACTIVITY;
-    __IO u32 IC_CLR_STOP_DET;
-    __IO u32 IC_CLR_START_DET;
-    __IO u32 IC_CLR_GEN_CALL;
-    __IO u32 IC_ENABLE;
-    __IO u32 IC_STATUS;
-    __IO u32 IC_TXFLR;
-    __IO u32 IC_RXFLR;
-    __IO u32 IC_SDA_HOLD;
-    __IO u32 IC_TX_ABRT_SOURCE_RESERVED;
-    __IO u32 IC_SLV_DATA_NACK_ONLY_RESERVED;
-    __IO u32 IC_DMA_CR;
-    __IO u32 IC_DMA_TDLR_RESERVED;
-    __IO u32 IC_DMA_RDLR_RESERVED;
-    __IO u32 IC_SDA_SETUP;
-    __IO u32 IC_ACK_GENERAL_CALL;
-} I2C_TypeDef;
-#endif
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C1                            ((I2C_TypeDef*)I2C1_BASE)
-#define I2C2                            ((I2C_TypeDef*)I2C2_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_CR_MASTER_Pos               (0)
-#define I2C_CR_MASTER                   (0x01U << I2C_CR_MASTER_Pos)            ///< I2C master mode enable
-#define I2C_CR_SPEED_Pos                (1)
-#define I2C_CR_SPEED                    (0x03U << I2C_CR_SPEED_Pos)             ///< I2C speed mode
-#define I2C_CR_STD                      (0x01U << I2C_CR_SPEED_Pos)             ///< I2C standard speed mode
-#define I2C_CR_FAST                     (0x02U << I2C_CR_SPEED_Pos)             ///< I2C fast speed mode
-#define I2C_CR_SLAVE10_Pos              (3)
-#define I2C_CR_SLAVE10                  (0x01U << I2C_CR_SLAVE10_Pos)           ///< I2C slave mode responds to 10-bit address
-#define I2C_CR_MASTER10_Pos             (4)
-#define I2C_CR_MASTER10                 (0x01U << I2C_CR_MASTER10_Pos)          ///< I2C master mode responds to 10-bit address
-#define I2C_CR_REPEN_Pos                (5)
-#define I2C_CR_REPEN                    (0x01U << I2C_CR_REPEN_Pos)             ///< Enable send RESTART
-#define I2C_CR_SLAVEDIS_Pos             (6)
-#define I2C_CR_SLAVEDIS                 (0x01U << I2C_CR_SLAVEDIS_Pos)          ///< I2C slave mode disable
-#define I2C_CR_STOPINT_Pos              (7)
-#define I2C_CR_STOPINT                  (0x01U << I2C_CR_STOPINT_Pos)           ///< Generate STOP interrupt in slave mode
-#define I2C_CR_EMPINT_Pos               (8)
-#define I2C_CR_EMPINT                   (0x01U << I2C_CR_EMPINT_Pos)            ///< I2C TX_EMPTY interrupt
-
-#define I2C_CR_STOP_Pos             (9)
-#define I2C_CR_STOP                 (0x01U << I2C_CR_STOP_Pos)                  ///< STOP signal enable
-#define I2C_CR_RESTART_Pos          (10)
-#define I2C_CR_RESTART              (0x01U << I2C_CR_RESTART_Pos)               ///< RESTART signal enable
-#define I2C_CR_SLV_TX_ABRT_DIS_Pos  (11)
-#define I2C_CR_SLV_TX_ABRT_DIS      (0x01U << I2C_CR_SLV_TX_ABRT_DIS_Pos)       ///< I2C as a slave
-#define I2C_CR_PADSEL_Pos           (12)
-#define I2C_CR_PADSEL               (0x01U << I2C_CR_PADSEL_Pos)               ///< PAD mode select
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_TAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_TAR_ADDR_Pos                (0)
-#define I2C_TAR_ADDR                    (0x03FFU << I2C_TAR_ADDR_Pos)           ///< Target address for master mode
-#define I2C_TAR_GC_Pos                  (10)
-#define I2C_TAR_GC                      (0x01U << I2C_TAR_GC_Pos)               ///< General Call or START byte
-#define I2C_TAR_SPECIAL_Pos             (11)
-#define I2C_TAR_SPECIAL                 (0x01U << I2C_TAR_SPECIAL_Pos)          ///< Special command enable like General Call or START byte
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_SAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_SAR_ADDR_Pos                (0)
-#define I2C_SAR_ADDR                    (0x03FFU << I2C_SAR_ADDR_Pos)           ///< Slave address
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_DR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_DR_DAT_Pos                  (0)
-#define I2C_DR_DAT                      (0xFFU << I2C_DR_DAT_Pos)               ///< The data to be transmitted or received
-#define I2C_DR_CMD_Pos                  (8)
-#define I2C_DR_CMD                      (0x01U << I2C_DR_CMD_Pos)               ///< Read or write command
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_SSHR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_SSHR_CNT_Pos                (0)
-#define I2C_SSHR_CNT                    (0xFFFFU << I2C_SSHR_CNT_Pos)           ///< SCL clock high period count for standard speed
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_SSLR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_SSLR_CNT_Pos                (0)
-#define I2C_SSLR_CNT                    (0xFFFFU << I2C_SSLR_CNT_Pos)           ///< SCL clock low period count for standard speed
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_FSHR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_FSHR_CNT_Pos                (0)
-#define I2C_FSHR_CNT                    (0xFFFFU << I2C_FSHR_CNT_Pos)           ///< SCL clock high period count for fast speed
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_FSLR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_FSLR_CNT_Pos                (0)
-#define I2C_FSLR_CNT                    (0xFFFFU << I2C_FSLR_CNT_Pos)           ///< SCL clock low period count for fast speed
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_ISR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_ISR_RX_UNDER_Pos            (0)
-#define I2C_ISR_RX_UNDER                (0x01U << I2C_ISR_RX_UNDER_Pos)         ///< RX_UNDER interrupt status
-#define I2C_ISR_RX_OVER_Pos             (1)
-#define I2C_ISR_RX_OVER                 (0x01U << I2C_ISR_RX_OVER_Pos)          ///< RX_OVER interrupt status
-#define I2C_ISR_RX_FULL_Pos             (2)
-#define I2C_ISR_RX_FULL                 (0x01U << I2C_ISR_RX_FULL_Pos)          ///< RX_FULL interrupt status
-#define I2C_ISR_TX_OVER_Pos             (3)
-#define I2C_ISR_TX_OVER                 (0x01U << I2C_ISR_TX_OVER_Pos)          ///< TX_OVER interrupt status
-#define I2C_ISR_TX_EMPTY_Pos            (4)
-#define I2C_ISR_TX_EMPTY                (0x01U << I2C_ISR_TX_EMPTY_Pos)         ///< TX_EMPTY interrupt status
-#define I2C_ISR_RX_REQ_Pos              (5)
-#define I2C_ISR_RX_REQ                  (0x01U << I2C_ISR_RX_REQ_Pos)           ///< RX_REQ interrupt status
-#define I2C_ISR_TX_ABRT_Pos             (6)
-#define I2C_ISR_TX_ABRT                 (0x01U << I2C_ISR_TX_ABRT_Pos)          ///< TX_ABRT interrupt status
-#define I2C_ISR_RX_DONE_Pos             (7)
-#define I2C_ISR_RX_DONE                 (0x01U << I2C_ISR_RX_DONE_Pos)          ///< RX_DONE interrupt status
-#define I2C_ISR_ACTIV_Pos               (8)
-#define I2C_ISR_ACTIV                   (0x01U << I2C_ISR_ACTIV_Pos)            ///< ACTIVITY interrupt status
-#define I2C_ISR_STOP_Pos                (9)
-#define I2C_ISR_STOP                    (0x01U << I2C_ISR_STOP_Pos)             ///< STOP_DET interrupt status
-#define I2C_ISR_START_Pos               (10)
-#define I2C_ISR_START                   (0x01U << I2C_ISR_START_Pos)            ///< START_DET interrupt status
-#define I2C_ISR_GC_Pos                  (11)
-#define I2C_ISR_GC                      (0x01U << I2C_ISR_GC_Pos)               ///< GEN_CALL interrupt status
-#define I2C_ISR_RESTART_Pos             (12)
-#define I2C_ISR_RESTART                 (0x01U << I2C_ISR_RESTART_Pos)          ///< RESTART_DET interrupt status
-#define I2C_ISR_HOLD_Pos                (13)
-#define I2C_ISR_HOLD                    (0x01U << I2C_ISR_HOLD_Pos)             ///< MST_ON_HOLD interrupt status
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_IMR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_IMR_RX_UNDER_Pos            (0)
-#define I2C_IMR_RX_UNDER                (0x01U << I2C_IMR_RX_UNDER_Pos)         ///< RX_UNDER interrupt mask
-#define I2C_IMR_RX_OVER_Pos             (1)
-#define I2C_IMR_RX_OVER                 (0x01U << I2C_IMR_RX_OVER_Pos)          ///< RX_OVER interrupt mask
-#define I2C_IMR_RX_FULL_Pos             (2)
-#define I2C_IMR_RX_FULL                 (0x01U << I2C_IMR_RX_FULL_Pos)          ///< RX_FULL interrupt mask
-#define I2C_IMR_TX_OVER_Pos             (3)
-#define I2C_IMR_TX_OVER                 (0x01U << I2C_IMR_TX_OVER_Pos)          ///< TX_OVER interrupt mask
-#define I2C_IMR_TX_EMPTY_Pos            (4)
-#define I2C_IMR_TX_EMPTY                (0x01U << I2C_IMR_TX_EMPTY_Pos)         ///< TX_EMPTY interrupt mask
-#define I2C_IMR_RX_REQ_Pos              (5)
-#define I2C_IMR_RX_REQ                  (0x01U << I2C_IMR_RX_REQ_Pos)           ///< RX_REQ interrupt mask
-#define I2C_IMR_TX_ABRT_Pos             (6)
-#define I2C_IMR_TX_ABRT                 (0x01U << I2C_IMR_TX_ABRT_Pos)          ///< TX_ABRT interrupt mask
-#define I2C_IMR_RX_DONE_Pos             (7)
-#define I2C_IMR_RX_DONE                 (0x01U << I2C_IMR_RX_DONE_Pos)          ///< RX_DONE interrupt mask
-
-#define I2C_IMR_ACTIV_Pos               (8)
-#define I2C_IMR_ACTIV                   (0x01U << I2C_IMR_ACTIV_Pos)            ///< ACTIVITY interrupt status
-#define I2C_IMR_STOP_Pos                (9)
-#define I2C_IMR_STOP                    (0x01U << I2C_IMR_STOP_Pos)             ///< STOP_DET interrupt status
-#define I2C_IMR_START_Pos               (10)
-#define I2C_IMR_START                   (0x01U << I2C_IMR_START_Pos)            ///< START_DET interrupt status
-#define I2C_IMR_GC_Pos                  (11)
-#define I2C_IMR_GC                      (0x01U << I2C_IMR_GC_Pos)               ///< GEN_CALL interrupt status
-#define I2C_IMR_RESTART_Pos             (12)
-#define I2C_IMR_RESTART                 (0x01U << I2C_IMR_RESTART_Pos)          ///< RESTART_DET interrupt status
-#define I2C_IMR_HOLD_Pos                (13)
-#define I2C_IMR_HOLD                    (0x01U << I2C_IMR_HOLD_Pos)             ///< MST_ON_HOLD interrupt status
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_RAWISR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_RAWISR_RX_UNDER_Pos         (0)
-#define I2C_RAWISR_RX_UNDER             (0x01U << I2C_RAWISR_RX_UNDER_Pos)      ///< RX_UNDER raw interrupt status
-#define I2C_RAWISR_RX_OVER_Pos          (1)
-#define I2C_RAWISR_RX_OVER              (0x01U << I2C_RAWISR_RX_OVER_Pos)       ///< RX_OVER raw interrupt status
-#define I2C_RAWISR_RX_FULL_Pos          (2)
-#define I2C_RAWISR_RX_FULL              (0x01U << I2C_RAWISR_RX_FULL_Pos)       ///< RX_FULL raw interrupt status
-#define I2C_RAWISR_TX_OVER_Pos          (3)
-#define I2C_RAWISR_TX_OVER              (0x01U << I2C_RAWISR_TX_OVER_Pos)       ///< TX_OVER raw interrupt status
-#define I2C_RAWISR_TX_EMPTY_Pos         (4)
-#define I2C_RAWISR_TX_EMPTY             (0x01U << I2C_RAWISR_TX_EMPTY_Pos)      ///< TX_EMPTY raw interrupt status
-#define I2C_RAWISR_RX_REQ_Pos           (5)
-#define I2C_RAWISR_RX_REQ               (0x01U << I2C_RAWISR_RX_REQ_Pos)        ///< RX_REQ raw interrupt status
-#define I2C_RAWISR_TX_ABRT_Pos          (6)
-#define I2C_RAWISR_TX_ABRT              (0x01U << I2C_RAWISR_TX_ABRT_Pos)       ///< TX_ABRT raw interrupt status
-#define I2C_RAWISR_RX_DONE_Pos          (7)
-#define I2C_RAWISR_RX_DONE              (0x01U << I2C_RAWISR_RX_DONE_Pos)       ///< RX_DONE raw interrupt status
-
-#define I2C_RAWISR_ACTIV_Pos            (8)
-#define I2C_RAWISR_ACTIV                (0x01U << I2C_RAWISR_ACTIV_Pos)         ///< ACTIVITY interrupt status
-#define I2C_RAWISR_STOP_Pos             (9)
-#define I2C_RAWISR_STOP                 (0x01U << I2C_RAWISR_STOP_Pos)          ///< STOP_DET interrupt status
-#define I2C_RAWISR_START_Pos            (10)
-#define I2C_RAWISR_START                (0x01U << I2C_RAWISR_START_Pos)         ///< START_DET interrupt status
-#define I2C_RAWISR_GC_Pos               (11)
-#define I2C_RAWISR_GC                   (0x01U << I2C_RAWISR_GC_Pos)            ///< GEN_CALL interrupt status
-#define I2C_RAWISR_RESTART_Pos          (12)
-#define I2C_RAWISR_RESTART              (0x01U << I2C_RAWISR_RESTART_Pos)       ///< RESTART_DET interrupt status
-#define I2C_RAWISR_HOLD_Pos             (13)
-#define I2C_RAWISR_HOLD                 (0x01U << I2C_RAWISR_HOLD_Pos)          ///< MST_ON_HOLD interrupt status
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_RXTLR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_RXTLR_Pos                   (0)
-#define I2C_RXTLR_TL                    (0xFFU << I2C_RXTLR_Pos)                ///< Receive FIFO threshold level
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_TXTLR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_TXTLR_Pos                   (0)
-#define I2C_TXTLR_TL                    (0xFFU << I2C_TXTLR_Pos)                ///< Transmit FIFO threshold level
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_ICR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_ICR_Pos                     (0)
-#define I2C_ICR                         (0x01U << I2C_ICR_Pos)                  ///< Read this register to clear the combined interrupt, all individual interrupts
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_RX_UNDER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_RX_UNDER_Pos                (0)
-#define I2C_RX_UNDER                    (0x01U << I2C_RX_UNDER_Pos)             ///< Read this register to clear the RX_UNDER interrupt of the I2C_RAW_INTR_STAT register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_RX_OVER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_RX_OVER_Pos                 (0)
-#define I2C_RX_OVER                     (0x01U << I2C_RX_OVER_Pos)              ///< Read this register to clear the RX_OVER interrupt of the I2C_RAW_INTR_STAT register
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_TX_OVER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_TX_OVER_Pos                 (0)
-#define I2C_TX_OVER                     (0x01U << I2C_TX_OVER_Pos)              ///< Read this register to clear the TX_OVER interrupt of the I2C_RAW_INTR_STAT register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_RD_REQ Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_RD_REQ_Pos                  (0)
-#define I2C_RD_REQ                      (0x01U << I2C_RD_REQ_Pos)               ///< Read this register to clear the RD_REQ interrupt of the I2C_RAW_INTR_STAT register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_TX_ABRT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_TX_ABRT_Pos                 (0)
-#define I2C_TX_ABRT                     (0x01U << I2C_TX_ABRT_Pos)              ///< Read this register to clear the TX_ABRT interrupt of the I2C_RAW_INTR_STAT register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_RX_DONE Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_RX_DONE_Pos                 (0)
-#define I2C_RX_DONE                     (0x01U << I2C_RX_DONE_Pos)              ///< Read this register to clear the RX_DONE interrupt of the I2C_RAW_INTR_STAT register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_ACTIV Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_ACTIV_Pos                   (0)
-#define I2C_ACTIV                       (0x01U << I2C_ACTIV_Pos)                ///< Read this register to clear the ACTIVITY interrupt of the I2C_RAW_INTR_STAT register
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_STOP Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_STOP_Pos                    (0)
-#define I2C_STOP                        (0x01U << I2C_STOP_Pos)                 ///< Read this register to clear the STOP_DET interrupt of the I2C_RAW_INTR_STAT register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_START Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_START_Pos                   (0)
-#define I2C_START                       (0x01U << I2C_START_Pos)                ///< Read this register to clear the START_DET interrupt of the I2C_RAW_INTR_STAT register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_GC Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_GC_Pos                      (0)
-#define I2C_GC                          (0x01U << I2C_GC_Pos)                   ///< Read this register to clear the GEN_CALL interrupt of the I2C_RAW_INTR_STAT register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_ENR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_ENR_ENABLE_Pos              (0)
-#define I2C_ENR_ENABLE                  (0x01U << I2C_ENR_ENABLE_Pos)           ///< I2C mode enable
-#define I2C_ENR_ABORT_Pos               (1)
-#define I2C_ENR_ABORT                   (0x01U << I2C_ENR_ABORT_Pos)            ///< I2C transfer abort
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_SR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_SR_ACTIV_Pos                (0)
-#define I2C_SR_ACTIV                    (0x01U << I2C_SR_ACTIV_Pos)             ///< I2C activity status
-#define I2C_SR_TFNF_Pos                 (1)
-#define I2C_SR_TFNF                     (0x01U << I2C_SR_TFNF_Pos)              ///< Transmit FIFO not full
-#define I2C_SR_TFE_Pos                  (2)
-#define I2C_SR_TFE                      (0x01U << I2C_SR_TFE_Pos)               ///< Transmit FIFO completely empty
-#define I2C_SR_RFNE_Pos                 (3)
-#define I2C_SR_RFNE                     (0x01U << I2C_SR_RFNE_Pos)              ///< Receive FIFO not empty
-#define I2C_SR_RFF_Pos                  (4)
-#define I2C_SR_RFF                      (0x01U << I2C_SR_RFF_Pos)               ///< Receive FIFO completely full
-#define I2C_SR_MST_ACTIV_Pos            (5)
-#define I2C_SR_MST_ACTIV                (0x01U << I2C_SR_MST_ACTIV_Pos)         ///< Master FSM activity status
-#define I2C_SR_SLV_ACTIV_Pos            (6)
-#define I2C_SR_SLV_ACTIV                (0x01U << I2C_SR_SLV_ACTIV_Pos)         ///< Slave FSM activity status
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_TXFLR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_TXFLR_CNT_Pos               (0)
-#define I2C_TXFLR_CNT                   (0x03U << I2C_TXFLR_CNT_Pos)            ///< Number of valid data in the transmit FIFO
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_RXFLR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_RXFLR_CNT_Pos               (0)
-#define I2C_RXFLR_CNT                   (0x03U << I2C_RXFLR_CNT_Pos)            ///< Number of valid data in the receive FIFO
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_HOLD Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_HOLD_TXCNT_Pos              (0)
-#define I2C_HOLD_TXCNT                  (0xFFFFU << I2C_HOLD_TXCNT_Pos)         ///< SDA hold time when I2C acts as a transmit
-#define I2C_HOLD_RXCNT_Pos              (16)
-#define I2C_HOLD_RXCNT                  (0xFFU << I2C_HOLD_RXCNT_Pos)           ///< SDA hold time when I2C acts as a receiver
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_DMA Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_DMA_RXEN_Pos                (0)
-#define I2C_DMA_RXEN                    (0x01U << I2C_DMA_RXEN_Pos)             ///< Receive DMA enable
-#define I2C_DMA_TXEN_Pos                (1)
-#define I2C_DMA_TXEN                    (0x01U << I2C_DMA_TXEN_Pos)             ///< Transmit DMA enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_SETUP Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_SETUP_CNT_Pos               (0)
-#define I2C_SETUP_CNT                   (0xFFU << I2C_SETUP_CNT_Pos)            ///< SDA setup
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2C_GCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define I2C_GCR_GC_Pos                  (0)
-#define I2C_GCR_GC                      (0x01U << I2C_GCR_GC_Pos)               ///< ACK general call
-
-
-#define I2C_SLVMASK_Pos                (0)
-#define I2C_SLVMASK                    (0x3FFU <<I2C_SLVMASK_Pos)
-
-#define I2C_SLVRCVADDR_Pos             (0)
-#define I2C_SLVRCVADDR                 (0x3FFU <<I2C_SLVRCVADDR_Pos)
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h
deleted file mode 100644
index 5c77b857c..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_iwdg.h
+++ /dev/null
@@ -1,125 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_iwdg.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_IWDG_H
-#define __REG_IWDG_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief IWDG Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define IWDG_BASE                       (APB1PERIPH_BASE + 0x3000)              ///< Base Address: 0x40003000
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief IWDG Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 KR;                                                                ///< Key Register                                   offset: 0x00
-    __IO u32 PR;                                                                ///< Prescaler Register                             offset: 0x04
-    __IO u32 RLR;                                                               ///< Reload Register                                offset: 0x08
-    __IO u32 SR;                                                                ///< Status Register                                offset: 0x0C
-    __IO u32 CR;                                                                ///< Control Register                               offset: 0x10
-    __IO u32  IGEN;                                                              ///< Interrupt Generator Register                   offset: 0x14
-    __IO u32  CNT;                                                              ///< Interrupt Generator count Register              offset: 0x18
-    __IO u32  PS;                                                              ///< Prescaler count Register              offset: 0x1C
-} IWDG_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief IWDG type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define IWDG                            ((IWDG_TypeDef*) IWDG_BASE)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief IWDG_KR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define IWDG_KEYR_KEY_Pos               (0)
-#define IWDG_KEYR_KEY                   (0xFFFFU << IWDG_KEYR_KEY_Pos)          ///< Key Value
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief IWDG_PR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define IWDG_PR_PRE_Pos                 (0)
-#define IWDG_PR_PRE                     (0x07U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 4
-#define IWDG_PR_PRE_DIV4                (0x00U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 4
-#define IWDG_PR_PRE_DIV8                (0x01U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 8
-#define IWDG_PR_PRE_DIV16               (0x02U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 16
-#define IWDG_PR_PRE_DIV32               (0x03U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 32
-#define IWDG_PR_PRE_DIV64               (0x04U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 64
-#define IWDG_PR_PRE_DIV128              (0x05U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 128
-#define IWDG_PR_PRE_DIV256              (0x06U << IWDG_PR_PRE_Pos)              ///< Prescaler divided by 256
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief IWDG_RLR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define IWDG_RLR_RL_Pos                 (0)
-#define IWDG_RLR_RL                     (0x0FFFU << IWDG_RLR_RL_Pos)            ///< Watchdog counter reload value
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief IWDG_SR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define IWDG_SR_PVU_Pos                 (0)
-#define IWDG_SR_PVU                     (0x01U << IWDG_SR_PVU_Pos)              ///< Watchdog prescaler value update
-#define IWDG_SR_RVU_Pos                 (1)
-#define IWDG_SR_RVU                     (0x01U << IWDG_SR_RVU_Pos)              ///< Watchdog counter reload value update
-
-#define IWDG_SR_IVU_Pos                 (2)
-#define IWDG_SR_IVU                     (0x01U << IWDG_SR_IVU_Pos)
-
-#define IWDG_SR_UPDATE_Pos                 (3)
-#define IWDG_SR_UPDATE                     (0x01U << IWDG_SR_UPDATE_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief IWDG_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define IWDG_CR_IRQSEL_Pos          (0)
-#define IWDG_CR_IRQSEL              (0x01U << IWDG_CR_IRQSEL_Pos)           ///< IWDG overflow operation selection
-#define IWDG_CR_IRQCLR_Pos          (1)
-#define IWDG_CR_IRQCLR              (0x01U << IWDG_CR_IRQCLR_Pos)           ///< IWDG interrupt clear
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief IWDG_IGRN Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define IWDG_IGEN_IGEN_Pos          (0)
-#define IWDG_IGEN_IGEN              (0xFFFU << IWDG_CR_IRQSEL_Pos)          ///< IWDG Interrupt Generate value
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h
deleted file mode 100644
index aa3605524..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwm.h
+++ /dev/null
@@ -1,72 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_pwm.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_PWM_H
-#define __REG_PWM_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWM Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWM Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-
-
-
-
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h
deleted file mode 100644
index 99f523225..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_pwr.h
+++ /dev/null
@@ -1,219 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_pwr.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_PWR_H
-#define __REG_PWR_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_BASE                        (APB1PERIPH_BASE + 0x7000)              ///< Base Address: 0x40007000
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    union {
-        __IO u32 CR;                                                            ///< Control register,                             offset: 0x00
-        __IO u32 CR1;
-    };
-    union {
-        __IO u32 CSR;                                                               ///< Control Status register                        offset: 0x04
-        __IO u32 CSR1;
-    };
-    __IO u32 CR2;                                                               ///< Control register  2                            offset: 0x08
-    __IO u32 CR3;                                                               ///< Control register  3                            offset: 0x0C
-    __IO u32 CR4;                                                               ///< Control register  4                            offset: 0x10
-    __IO u32 CR5;                                                               ///< Control register  5                            offset: 0x14
-    __IO u32 CR6;                                                               ///< Control register  6                            offset: 0x18
-    __IO u32 SR;                                                                ///< Status  register                               offset: 0x1C
-    __IO u32 SCR;                                                               ///< clear status register                          offset: 0x20
-    __IO u32 CFGR;                                                              ///< Configuration register                         offset: 0x24
-} PWR_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR                             ((PWR_TypeDef*) PWR_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR_CR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_CR_LDPS_Pos                 (0)
-#define PWR_CR_LDPS                     (0x01U  << PWR_CR_LDPS_Pos)             ///< Domain Write Protction
-
-#define PWR_CR_PDDS_Pos                 (1)
-#define PWR_CR_PDDS                     (0x01U  << PWR_CR_PDDS_Pos)             ///< Power Down Deepsleep
-#define PWR_CR_CSBF_Pos                 (3)
-#define PWR_CR_CSBF                     (0x01U  << PWR_CR_CSBF_Pos)             ///< Clear Standby Flag
-#define PWR_CR_LPR_Pos                  (13)
-#define PWR_CR_LPR                      (0x01U  << PWR_CR_LPR_Pos)              ///< Low power run
-#define PWR_CR_VOS_Pos                  (14)
-#define PWR_CR_VOS0                     (0x00U  << PWR_CR_VOS_Pos)              ///< Modulator Voltage Output Select 1.80V
-#define PWR_CR_VOS1                     (0x01U  << PWR_CR_VOS_Pos)              ///< Modulator Voltage Output Select 1.70V
-#define PWR_CR_VOS2                     (0x02U  << PWR_CR_VOS_Pos)              ///< Modulator Voltage Output Select 1.60V
-#define PWR_CR_VOS3                     (0x03U  << PWR_CR_VOS_Pos)              ///< Modulator Voltage Output Select 1.55V
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR_CSR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_CSR_SBF_Pos                 (1)
-#define PWR_CSR_SBF                     (0x01U  << PWR_CSR_SBF_Pos)             ///< Standby Flag
-#define PWR_CSR_VOSRDY_Pos              (14)
-#define PWR_CSR_VOSRDY                  (0x01U  << PWR_CR_VOSRDY_Pos)           ///< Voltage Modulator Output Selection Ready
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR_CR2 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_CR2_EWUP1_Pos                (0)
-#define PWR_CR2_EWUP1                    (0x01U << PWR_CR2_EWUP1_Pos)           ///< Enable WKUP1 wake-up pin
-#define PWR_CR2_EWUP2_Pos                (1)
-#define PWR_CR2_EWUP2                    (0x01U << PWR_CR2_EWUP2_Pos)           ///< Enable WKUP2 wake-up pin
-#define PWR_CR2_EWUP3_Pos                (2)
-#define PWR_CR2_EWUP3                    (0x01U << PWR_CR2_EWUP3_Pos)           ///< Enable WKUP3 wake-up pin
-#define PWR_CR2_EWUP4_Pos                (3)
-#define PWR_CR2_EWUP4                    (0x01U << PWR_CR2_EWUP4_Pos)           ///< Enable WKUP4 wake-up pin
-#define PWR_CR2_EWUP5_Pos                (4)
-#define PWR_CR2_EWUP5                    (0x01U << PWR_CR2_EWUP5_Pos)           ///< Enable WKUP5 wake-up pin
-#define PWR_CR2_EWUP6_Pos                (5)
-#define PWR_CR2_EWUP6                    (0x01U << PWR_CR2_EWUP6_Pos)           ///< Enable WKUP6 wake-up pin
-#define PWR_CR2_ENWU_Pos                 (15)
-#define PWR_CR2_ENWU                     (0x01U << PWR_CR2_ENWU_Pos)            ///< Enable wakeup module
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR_CR3 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_CR3_WP1_Pos                (0)
-#define PWR_CR3_WP1                    (0x01U << PWR_CR3_WP1_Pos)               ///<  WKUP1 used for event polarity detection
-#define PWR_CR3_WP2_Pos                (1)
-#define PWR_CR3_WP2                    (0x01U << PWR_CR3_WP2_Pos)               ///<  WKUP2 used for event polarity detection
-#define PWR_CR3_WP3_Pos                (2)
-#define PWR_CR3_WP3                    (0x01U << PWR_CR3_WP3_Pos)               ///<  WKUP3 used for event polarity detection
-#define PWR_CR3_WP4_Pos                (3)
-#define PWR_CR3_WP4                    (0x01U << PWR_CR3_WP4_Pos)               ///<  WKUP4 used for event polarity detection
-#define PWR_CR3_WP5_Pos                (4)
-#define PWR_CR3_WP5                    (0x01U << PWR_CR3_WP5_Pos)               ///<  WKUP5 used for event polarity detection
-#define PWR_CR3_WP6_Pos                (5)
-#define PWR_CR3_WP6                    (0x01U << PWR_CR3_WP6_Pos)               ///<  WKUP6 used for event polarity detection
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR_CR4 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_CR4_FILTSEL0_Pos           (0)
-#define PWR_CR4_FILTSEL0               (0x01U << PWR_CR4_FILTSEL0_Pos)          ///<  selection wake-up source
-#define PWR_CR4_FILTE0_Pos             (2)
-#define PWR_CR4_FILTE0                 (0x01U << PWR_CR4_FILTE0_Pos)            ///<  enable Filter 0
-#define PWR_CR4_FILTF0_Pos             (4)
-#define PWR_CR4_FILTF0                 (0x01U << PWR_CR4_FILTF0_Pos)            ///<  Whether the wake source passes through filter 0
-#define PWR_CR4_FILTCNT0_Pos           (8)
-#define PWR_CR4_FILTCNT0               (0xFFU << PWR_CR4_FILTCNT0_Pos)          ///<  Filter 0 counter
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR_CR5 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_CR5_FILTSEL1_Pos           (0)
-#define PWR_CR5_FILTSEL1               (0x01U << PWR_CR5_FILTSEL1_Pos)          ///<  selection wake-up source
-#define PWR_CR5_FILTE1_Pos             (2)
-#define PWR_CR5_FILTE1                 (0x01U << PWR_CR5_FILTE1_Pos)            ///<  enable Filter 1
-#define PWR_CR5_FILTF1_Pos             (4)
-#define PWR_CR5_FILTF1                 (0x01U << PWR_CR5_FILTF1_Pos)            ///<  Whether the wake source passes through filter 1
-#define PWR_CR5_FILTCNT1_Pos           (8)
-#define PWR_CR5_FILTCNT1               (0xFFU << PWR_CR5_FILTCNT1_Pos)          ///<  Filter 1 counter
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR_CR6 register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_CR6_STDBY_FS_W_Pos          (0)
-#define PWR_CR6_STDBY_FS_W1             (0x00U << PWR_CR6_STDBY_FS_W_Pos)       ///<  1 LSI cycle wake
-#define PWR_CR6_STDBY_FS_W2             (0x01U << PWR_CR6_STDBY_FS_W_Pos)       ///<  2 LSI cycle wake
-#define PWR_CR6_STDBY_FS_W3             (0x02U << PWR_CR6_STDBY_FS_W_Pos)       ///<  3 LSI cycle wake
-#define PWR_CR6_STDBY_FS_W4             (0x03U << PWR_CR6_STDBY_FS_W_Pos)       ///<  4 LSI cycle wake
-#define PWR_CR6_STDBY_FS_W5             (0x04U << PWR_CR6_STDBY_FS_W_Pos)       ///<  5 LSI cycle wake
-#define PWR_CR6_STDBY_FS_W6             (0x05U << PWR_CR6_STDBY_FS_W_Pos)       ///<  6 LSI cycle wake
-#define PWR_CR6_STDBY_FS_W7             (0x06U << PWR_CR6_STDBY_FS_W_Pos)       ///<  7 LSI cycle wake
-#define PWR_CR6_STDBY_FS_W8             (0x07U << PWR_CR6_STDBY_FS_W_Pos)       ///<  8 LSI cycle wake
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR_SR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_SR_WUF1_Pos                (0)
-#define PWR_SR_WUF1                    (0x01U << PWR_SR_WUF1_Pos)               ///<  wake-up flag 1
-#define PWR_SR_WUF2_Pos                (1)
-#define PWR_SR_WUF2                    (0x01U << PWR_SR_WUF2_Pos)               ///<  wake-up flag 2
-#define PWR_SR_WUF3_Pos                (2)
-#define PWR_SR_WUF3                    (0x01U << PWR_SR_WUF3_Pos)               ///<  wake-up flag 3
-#define PWR_SR_WUF4_Pos                (3)
-#define PWR_SR_WUF4                    (0x01U << PWR_SR_WUF4_Pos)               ///<  wake-up flag 4
-#define PWR_SR_WUF5_Pos                (4)
-#define PWR_SR_WUF5                    (0x01U << PWR_SR_WUF5_Pos)               ///<  wake-up flag 5
-#define PWR_SR_WUF6_Pos                (5)
-#define PWR_SR_WUF6                    (0x01U << PWR_SR_WUF6_Pos)               ///<  wake-up flag 6
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR_SCR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_SCR_CWUF1_Pos              (0)
-#define PWR_SCR_CWUF1                  (0x01U << PWR_SCR_CWUF1_Pos)             ///< clear wake-up flag 1 
-#define PWR_SCR_CWUF2_Pos              (1)
-#define PWR_SCR_CWUF2                  (0x01U << PWR_SCR_CWUF2_Pos)             ///< clear wake-up flag 2
-#define PWR_SCR_CWUF3_Pos              (2)
-#define PWR_SCR_CWUF3                  (0x01U << PWR_SCR_CWUF3_Pos)             ///< clear wake-up flag 3
-#define PWR_SCR_CWUF4_Pos              (3)
-#define PWR_SCR_CWUF4                  (0x01U << PWR_SCR_CWUF4_Pos)             ///< clear wake-up flag 4
-#define PWR_SCR_CWUF5_Pos              (4)
-#define PWR_SCR_CWUF5                  (0x01U << PWR_SCR_CWUF5_Pos)             ///< clear wake-up flag 5
-#define PWR_SCR_CWUF6_Pos              (5)
-#define PWR_SCR_CWUF6                  (0x01U << PWR_SCR_CWUF6_Pos)             ///< clear wake-up flag 6
-////////////////////////////////////////////////////////////////////////////////
-/// @brief PWR_CFGR register Bit definition
-////////////////////////////////////////////////////////////////////////////////
-#define PWR_CFGR_LSICALSEL_Pos         (0)
-#define PWR_CFGR_LSICALSEL             (0x1FU << PWR_CFGR_LSICALSEL_Pos)        ///< Enable internal clock calibration 
-#define PWR_CFGR_LSICAL_Pos            (5)
-#define PWR_CFGR_LSICAL                (0x1FU << PWR_CFGR_LSICAL_Pos)           ///< Internal high-speed clock calibration
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h
deleted file mode 100644
index d378371fc..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rcc.h
+++ /dev/null
@@ -1,654 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_rcc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_RCC_H
-#define __REG_RCC_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_BASE                        (AHBPERIPH_BASE + 0x1000)               ///< Base Address: 0x40021000
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 CR;                                                                ///< Control Register                               offset: 0x00
-    __IO u32 CFGR;                                                              ///< Configuration Register                         offset: 0x04
-    __IO u32 CIR;                                                               ///< Clock Interrupt Register                       offset: 0x08
-    __IO u32 AHB3RSTR;                                                          ///< Advanced High Performance Bus 3 Reset Register offset: 0x0C
-    __IO u32 AHB2RSTR;                                                          ///< Advanced High Performance Bus 2 Reset Register offset: 0x10
-    __IO u32 AHBRSTR;                                                           ///<  Advanced High Performance Bus 1 Reset Register  offset: 0x14
-    __IO u32 APB2RSTR;                                                          ///< Advanced Peripheral Bus 2 Reset Register      offset: 0x18
-    __IO u32 APB1RSTR;                                                          ///< Advanced Peripheral Bus 1 Reset Register      offset: 0x1C
-    __IO u32 AHB3ENR;                                                           ///< Advanced High Performance Bus 3 Enable Register  offset: 0x20
-    __IO u32 AHB2ENR;                                                           ///< Advanced High Performance Bus 2 Enable Register  offset: 0x24
-    union {
-        __IO u32 AHBENR;                                                        ///< Advanced High Performance Bus 1 Enable Register  offset: 0x28
-        __IO u32 AHB1ENR;
-    };
-
-    __IO u32 APB2ENR;                                                           ///< Advanced Peripheral Bus 2 Enable Register      offset: 0x2C
-    __IO u32 APB1ENR;                                                           ///< Advanced Peripheral Bus 1 Enable Register      offset: 0x30
-
-
-    __IO u32 BDCR;                                                              ///< Backup Domain Control Register                  offset: 0x34
-    __IO u32 CSR;                                                               ///< Control Status Register                         offset: 0x38
-    __IO u32 SYSCFGR;                                                           ///< System Configuration Register                   offset: 0x3C
-    __IO u32 CFGR2;                                                             ///< System Configuration Register                  offset: 0x40
-    __IO u32 ICSCR;                                                             ///< Internal clock source calibration register     offset: 0x44
-    __IO u32 PLLCFGR;                                                           ///< PLL configures registers                       offset: 0x48
-    u32 Reserved1[13];                                                          ///< Reserved space
-    __IO u32 HSIDLY;                                                            ///< HSI delay register                             offset: 0x80
-    __IO u32 HSEDLY;                                                            ///< HSE delay register                             offset: 0x84
-    __IO u32 PLLDLY;                                                            ///< PLL delay register                             offset: 0x88
-} RCC_TypeDef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC                             ((RCC_TypeDef*) RCC_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_CR_HSION_Pos                (0)
-#define RCC_CR_HSION                    (0x01U << RCC_CR_HSION_Pos)             ///< Internal High Speed clock enable
-
-#define RCC_CR_HSIRDY_Pos               (1)
-#define RCC_CR_HSIRDY                   (0x01U << RCC_CR_HSIRDY_Pos)            ///< Internal High Speed clock ready flag
-
-
-
-#define  RCC_CR_HSIDIV_Pos              (11)
-#define  RCC_CR_HSIDIV_0                (0x00U << RCC_CR_HSIDIV_Pos)            ///< HSI regardless of frequency
-#define  RCC_CR_HSIDIV_2                (0x01U << RCC_CR_HSIDIV_Pos)            ///< HSI 2 frequency division
-#define  RCC_CR_HSIDIV_4                (0x02U << RCC_CR_HSIDIV_Pos)            ///< HSI 4 frequency division
-#define  RCC_CR_HSIDIV_8                (0x03U << RCC_CR_HSIDIV_Pos)            ///< HSI eight points and frequency
-#define  RCC_CR_HSIDIV_16               (0x04U << RCC_CR_HSIDIV_Pos)            ///< HSI 16 points and frequency
-#define  RCC_CR_HSIDIV_32               (0x05U << RCC_CR_HSIDIV_Pos)            ///< HSI 32 points and frequency
-#define  RCC_CR_HSIDIV_64               (0x06U << RCC_CR_HSIDIV_Pos)            ///< HSI 64 frequency division
-#define  RCC_CR_HSIDIV_128              (0x07U << RCC_CR_HSIDIV_Pos)            ///< HSI 128 frequency division
-#define  RCC_CR_HSEON_Pos               (16)
-#define  RCC_CR_HSEON                   (0x01U << RCC_CR_HSEON_Pos)             ///< External High Speed clock enable
-#define  RCC_CR_HSERDY_Pos              (17)
-#define  RCC_CR_HSERDY                  (0x01U << RCC_CR_HSERDY_Pos)            ///< External High Speed clock ready flag
-#define  RCC_CR_HSEBYP_Pos              (18)
-#define  RCC_CR_HSEBYP                  (0x01U << RCC_CR_HSEBYP_Pos)            ///< External High Speed clock Bypass
-#define  RCC_CR_CSSON_Pos               (19)
-#define  RCC_CR_CSSON                   (0x01U << RCC_CR_CSSON_Pos)             ///< Clock Security System enable
-
-
-#define  RCC_CR_PLLON_Pos               (24)
-#define  RCC_CR_PLLON                   (0x01U << RCC_CR_PLLON_Pos)             ///< PLL enable
-#define  RCC_CR_PLLRDY_Pos              (25)
-#define  RCC_CR_PLLRDY                  (0x01U << RCC_CR_PLLRDY_Pos)            ///< PLL clock ready flag
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_CFGR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_CFGR_SW_Pos                 (0)
-#define RCC_CFGR_SW                     (0x03U << RCC_CFGR_SW_Pos)              ///< SW[1:0] bits (System clock Switch)
-#define RCC_CFGR_SW_HSI_DIV6            (0x00U << RCC_CFGR_SW_Pos)              ///< HSI/6 selected as system clock
-#define RCC_CFGR_SW_HSE                 (0x01U << RCC_CFGR_SW_Pos)              ///< HSE selected as system clock
-#define RCC_CFGR_SW_PLL                 (0x02U << RCC_CFGR_SW_Pos)              ///< PLL selected as system clock
-#define RCC_CFGR_SW_LSI                 (0x03U << RCC_CFGR_SW_Pos)              ///< LSI selected as system clock
-
-#define RCC_CFGR_SWS_Pos                (2)
-#define RCC_CFGR_SWS                    (0x03U << RCC_CFGR_SWS_Pos)             ///< SWS[1:0] bits (System Clock Switch Status)
-#define RCC_CFGR_SWS_HSI_DIV6           (0x00U << RCC_CFGR_SWS_Pos)             ///< HSI/6 oscillator used as system clock
-#define RCC_CFGR_SWS_HSE                (0x01U << RCC_CFGR_SWS_Pos)             ///< HSE oscillator used as system clock
-#define RCC_CFGR_SWS_PLL                (0x02U << RCC_CFGR_SWS_Pos)             ///< PLL used as system clock
-#define RCC_CFGR_SWS_LSI                (0x03U << RCC_CFGR_SWS_Pos)             ///< LSI used as system clock
-
-#define RCC_CFGR_HPRE_Pos               (4)
-#define RCC_CFGR_HPRE                   (0x0FU << RCC_CFGR_HPRE_Pos)            ///< HPRE[3:0] bits (AHB prescaler)
-#define RCC_CFGR_PPRE_0                 (0x01U << RCC_CFGR_HPRE_Pos)            ///< Bit 0
-#define RCC_CFGR_PPRE_1                 (0x02U << RCC_CFGR_HPRE_Pos)            ///< Bit 1
-#define RCC_CFGR_PPRE_2                 (0x04U << RCC_CFGR_HPRE_Pos)            ///< Bit 2
-#define RCC_CFGR_PPRE_3                 (0x08U << RCC_CFGR_HPRE_Pos)            ///< Bit 3
-
-#define RCC_CFGR_HPRE_DIV1              (0x00U << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK not divided
-#define RCC_CFGR_HPRE_DIV2              (0x08U << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 2
-#define RCC_CFGR_HPRE_DIV4              (0x09U << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 4
-#define RCC_CFGR_HPRE_DIV8              (0x0AU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 8
-#define RCC_CFGR_HPRE_DIV16             (0x0BU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 16
-#define RCC_CFGR_HPRE_DIV64             (0x0CU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 64
-#define RCC_CFGR_HPRE_DIV128            (0x0DU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 128
-#define RCC_CFGR_HPRE_DIV256            (0x0EU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 256
-#define RCC_CFGR_HPRE_DIV512            (0x0FU << RCC_CFGR_HPRE_Pos)            ///< AHB = FCLK = SYSCLK divided by 512
-
-#define RCC_CFGR_PPRE1_Pos              (8)
-#define RCC_CFGR_PPRE1                  (0x07U << RCC_CFGR_PPRE1_Pos)           ///< PRE1[2:0] bits (APB1 prescaler)
-#define RCC_CFGR_PPRE1_0                (0x01U << RCC_CFGR_PPRE1_Pos)           ///< Bit 0
-#define RCC_CFGR_PPRE1_1                (0x02U << RCC_CFGR_PPRE1_Pos)           ///< Bit 1
-#define RCC_CFGR_PPRE1_2                (0x04U << RCC_CFGR_PPRE1_Pos)           ///< Bit 2
-
-#define RCC_CFGR_PPRE1_DIV1             (0x00U << RCC_CFGR_PPRE1_Pos)           ///< APB1 = HCLK not divided
-#define RCC_CFGR_PPRE1_DIV2             (0x04U << RCC_CFGR_PPRE1_Pos)           ///< APB1 = HCLK divided by 2
-#define RCC_CFGR_PPRE1_DIV4             (0x05U << RCC_CFGR_PPRE1_Pos)           ///< APB1 = HCLK divided by 4
-#define RCC_CFGR_PPRE1_DIV8             (0x06U << RCC_CFGR_PPRE1_Pos)           ///< APB1 = HCLK divided by 8
-#define RCC_CFGR_PPRE1_DIV16            (0x07U << RCC_CFGR_PPRE1_Pos)           ///< APB1 = HCLK divided by 16
-
-#define RCC_CFGR_PPRE2_Pos              (11)
-#define RCC_CFGR_PPRE2                  (0x07U << RCC_CFGR_PPRE2_Pos)           ///< PRE2[2:0] bits (APB2 prescaler)
-#define RCC_CFGR_PPRE2_0                (0x01U << RCC_CFGR_PPRE2_Pos)           ///< Bit 0
-#define RCC_CFGR_PPRE2_1                (0x02U << RCC_CFGR_PPRE2_Pos)           ///< Bit 1
-#define RCC_CFGR_PPRE2_2                (0x04U << RCC_CFGR_PPRE2_Pos)           ///< Bit 2
-
-#define RCC_CFGR_PPRE2_DIV1             (0x00U << RCC_CFGR_PPRE2_Pos)           ///< APB2 = HCLK not divided
-#define RCC_CFGR_PPRE2_DIV2             (0x04U << RCC_CFGR_PPRE2_Pos)           ///< APB2 = HCLK divided by 2
-#define RCC_CFGR_PPRE2_DIV4             (0x05U << RCC_CFGR_PPRE2_Pos)           ///< APB2 = HCLK divided by 4
-#define RCC_CFGR_PPRE2_DIV8             (0x06U << RCC_CFGR_PPRE2_Pos)           ///< APB2 = HCLK divided by 8
-#define RCC_CFGR_PPRE2_DIV16            (0x07U << RCC_CFGR_PPRE2_Pos)           ///< APB2 = HCLK divided by 16
-
-
-#define RCC_CFGR_USBPRE_Pos             (22)
-#define RCC_CFGR_USBPRE                 (0x03U << RCC_CFGR_USBPRE_Pos)          ///< USB prescaler BIT[1:0]
-
-#define RCC_CFGR_MCO_Pos                (24)
-#define RCC_CFGR_MCO                    (0x07U << RCC_CFGR_MCO_Pos)             ///< MCO[2:0] bits (Microcontroller Clock Output)
-#define RCC_CFGR_MCO_NOCLOCK            (0x00U << RCC_CFGR_MCO_Pos)             ///< No clock
-#define RCC_CFGR_MCO_LSI                (0x02U << RCC_CFGR_MCO_Pos)             ///< LSI clock
-#define RCC_CFGR_MCO_LSE                (0x03U << RCC_CFGR_MCO_Pos)             ///< LSE clock
-#define RCC_CFGR_MCO_SYSCLK             (0x04U << RCC_CFGR_MCO_Pos)             ///< System clock selected
-#define RCC_CFGR_MCO_HSI                (0x05U << RCC_CFGR_MCO_Pos)             ///< Internal 48 MHz RC oscillator clock selected
-#define RCC_CFGR_MCO_HSE                (0x06U << RCC_CFGR_MCO_Pos)             ///< External 1-25 MHz oscillator clock selected
-#define RCC_CFGR_MCO_PLL                (0x07U << RCC_CFGR_MCO_Pos)             ///< PLL clock divided by 2 selected
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_CIR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_CIR_LSIRDYF_Pos             (0)
-#define RCC_CIR_LSIRDYF                 (0x01U << RCC_CIR_LSIRDYF_Pos)          ///< LSI Ready Interrupt flag
-
-#define RCC_CIR_LSERDYF_Pos             (1)
-#define RCC_CIR_LSERDYF                 (0x01U << RCC_CIR_LSERDYF_Pos)          ///< LSE Ready Interrupt flag
-
-#define RCC_CIR_HSIRDYF_Pos             (2)
-#define RCC_CIR_HSIRDYF                 (0x01U << RCC_CIR_HSIRDYF_Pos)          ///< HSI Ready Interrupt flag
-#define RCC_CIR_HSERDYF_Pos             (3)
-#define RCC_CIR_HSERDYF                 (0x01U << RCC_CIR_HSERDYF_Pos)          ///< HSE Ready Interrupt flag
-
-#define RCC_CIR_PLLRDYF_Pos             (4)
-#define RCC_CIR_PLLRDYF                 (0x01U << RCC_CIR_PLLRDYF_Pos)          ///< PLL Ready Interrupt flag
-
-#define RCC_CIR_CSSF_Pos                (7)
-#define RCC_CIR_CSSF                    (0x01U << RCC_CIR_CSSF_Pos)             ///< Clock Security System Interrupt flag
-#define RCC_CIR_LSIRDYIE_Pos            (8)
-#define RCC_CIR_LSIRDYIE                (0x01U << RCC_CIR_LSIRDYIE_Pos)         ///< LSI Ready Interrupt Enable
-
-#define RCC_CIR_LSERDYIE_Pos            (9)
-#define RCC_CIR_LSERDYIE                (0x01U << RCC_CIR_LSERDYIE_Pos)         ///< LSE Ready Interrupt Enable
-
-#define RCC_CIR_HSIRDYIE_Pos            (10)
-#define RCC_CIR_HSIRDYIE                (0x01U << RCC_CIR_HSIRDYIE_Pos)         ///< HSI Ready Interrupt Enable
-#define RCC_CIR_HSERDYIE_Pos            (11)
-#define RCC_CIR_HSERDYIE                (0x01U << RCC_CIR_HSIRDYIE_Pos)         ///< HSE Ready Interrupt Enable
-
-#define RCC_CIR_PLLRDYIE_Pos            (12)
-#define RCC_CIR_PLLRDYIE                (0x01U << RCC_CIR_PLLRDYIE_Pos)         ///< PLL Ready Interrupt Enable
-
-#define RCC_CIR_LSIRDYC_Pos             (16)
-#define RCC_CIR_LSIRDYC                 (0x01U << RCC_CIR_LSIRDYC_Pos)          ///< LSI Ready Interrupt Clear
-
-#define RCC_CIR_LSERDYC_Pos             (17)
-#define RCC_CIR_LSERDYC                 (0x01U << RCC_CIR_LSERDYC_Pos)          ///< LSE Ready Interrupt Clear
-
-#define RCC_CIR_HSIRDYC_Pos             (18)
-#define RCC_CIR_HSIRDYC                 (0x01U << RCC_CIR_HSIRDYC_Pos)          ///< HSI Ready Interrupt Clear
-#define RCC_CIR_HSERDYC_Pos             (19)
-#define RCC_CIR_HSERDYC                 (0x01U << RCC_CIR_HSERDYC_Pos)          ///< HSE Ready Interrupt Clear
-
-#define RCC_CIR_PLLRDYC_Pos             (20)
-#define RCC_CIR_PLLRDYC                 (0x01U << RCC_CIR_PLLRDYC_Pos)          ///< PLL Ready Interrupt Clear
-
-#define RCC_CIR_CSSC_Pos                (23)
-#define RCC_CIR_CSSC                    (0x01U << RCC_CIR_CSSC_Pos)             ///< Clock Security System Interrupt Clear
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_APB2RSTR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_APB2RSTR_TIM1_Pos           (0)
-#define RCC_APB2RSTR_TIM1               (0x01U << RCC_APB2RSTR_TIM1_Pos)        ///< TIM1 reset
-#define RCC_APB2RSTR_TIM8_Pos           (1)
-#define RCC_APB2RSTR_TIM8               (0x01U << RCC_APB2RSTR_TIM8_Pos)        ///< TIM8 reset
-#define RCC_APB2RSTR_UART1_Pos          (4)
-#define RCC_APB2RSTR_UART1              (0x01U << RCC_APB2RSTR_UART1_Pos)       ///< UART1 reset
-#define RCC_APB2RSTR_UART6_Pos          (5)
-#define RCC_APB2RSTR_UART6              (0x01U << RCC_APB2RSTR_UART6_Pos)       ///< UART6 reset
-#define RCC_APB2RSTR_ADC1_Pos           (8)
-#define RCC_APB2RSTR_ADC1               (0x01U << RCC_APB2RSTR_ADC1_Pos)        ///< ADC1 reset
-#define RCC_APB2RSTR_ADC2_Pos           (9)
-#define RCC_APB2RSTR_ADC2               (0x01U << RCC_APB2RSTR_ADC2_Pos)        ///< ADC2 reset
-#define RCC_APB2RSTR_ADC3_Pos           (10)
-#define RCC_APB2RSTR_ADC3               (0x01U << RCC_APB2RSTR_ADC3_Pos)        ///< ADC3 reset
-#define RCC_APB2RSTR_SPI1_Pos           (12)
-#define RCC_APB2RSTR_SPI1               (0x01U << RCC_APB2RSTR_SPI1_Pos)        ///< SPI1 reset
-#define RCC_APB2RSTR_SYSCFG_Pos         (14)
-#define RCC_APB2RSTR_SYSCFG             (0x01U << RCC_APB2RSTR_SYSCFG_Pos)      ///< SYSCFG reset
-#define RCC_APB2RSTR_COMP_Pos           (15)
-#define RCC_APB2RSTR_COMP               (0x01U << RCC_APB2RSTR_COMP_Pos)        ///< COMP reset
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_AHB3RSTR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_AHB3RSTR_FSMC_Pos           (0)
-#define RCC_AHB3RSTR_FSMC               (0x01U << RCC_AHB3RSTR_FSMC_Pos)        ///< FSMC reset
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_APB1RSTR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_APB1RSTR_TIM2_Pos           (0)
-#define RCC_APB1RSTR_TIM2               (0x01U << RCC_APB1RSTR_TIM2_Pos)        ///< Timer 2 reset
-#define RCC_APB1RSTR_TIM3_Pos           (1)
-#define RCC_APB1RSTR_TIM3               (0x01U << RCC_APB1RSTR_TIM3_Pos)        ///< Timer 3 reset
-
-#define RCC_APB1RSTR_TIM4_Pos           (2)
-#define RCC_APB1RSTR_TIM4               (0x01U << RCC_APB1RSTR_TIM4_Pos)        ///< Timer 4 reset
-#define RCC_APB1RSTR_TIM5_Pos           (3)
-#define RCC_APB1RSTR_TIM5               (0x01U << RCC_APB1RSTR_TIM5_Pos)        ///< Timer 5 reset
-#define RCC_APB1RSTR_TIM6_Pos           (4)
-#define RCC_APB1RSTR_TIM6               (0x01U << RCC_APB1RSTR_TIM6_Pos)        ///< Timer 6 reset
-#define RCC_APB1RSTR_TIM7_Pos           (5)
-#define RCC_APB1RSTR_TIM7               (0x01U << RCC_APB1RSTR_TIM7_Pos)        ///< Timer 7 reset
-
-#define RCC_APB1RSTR_WWDG_Pos           (11)
-#define RCC_APB1RSTR_WWDG               (0x01U << RCC_APB1RSTR_WWDG_Pos)        ///< Window Watchdog reset
-#define RCC_APB1RSTR_SPI2_Pos           (14)
-#define RCC_APB1RSTR_SPI2               (0x01U << RCC_APB1RSTR_SPI2_Pos)        ///< SPI 2 reset
-#define RCC_APB1RSTR_SPI3_Pos           (15)
-#define RCC_APB1RSTR_SPI3               (0x01U << RCC_APB1RSTR_SPI3_Pos)        ///< SPI 3 reset
-
-#define RCC_APB1RSTR_UART2_Pos          (17)
-#define RCC_APB1RSTR_UART2              (0x01U << RCC_APB1RSTR_UART2_Pos)       ///< UART 2 reset
-#define RCC_APB1RSTR_UART3_Pos          (18)
-#define RCC_APB1RSTR_UART3              (0x01U << RCC_APB1RSTR_UART3_Pos)       ///< UART 3 reset
-#define RCC_APB1RSTR_UART4_Pos          (19)
-#define RCC_APB1RSTR_UART4              (0x01U << RCC_APB1RSTR_UART4_Pos)       ///< UART 4 reset
-#define RCC_APB1RSTR_UART5_Pos          (20)
-#define RCC_APB1RSTR_UART5              (0x01U << RCC_APB1RSTR_UART5_Pos)       ///< UART 5 reset
-#define RCC_APB1RSTR_I2C1_Pos           (21)
-#define RCC_APB1RSTR_I2C1               (0x01U << RCC_APB1RSTR_I2C1_Pos)        ///< I2C 1 reset
-#define RCC_APB1RSTR_I2C2_Pos           (22)
-#define RCC_APB1RSTR_I2C2               (0x01U << RCC_APB1RSTR_I2C2_Pos)        ///< I2C 2 reset
-
-#define RCC_APB1RSTR_CRS_Pos            (24)
-#define RCC_APB1RSTR_CRS                (0x01U << RCC_APB1RSTR_CRS_Pos)         ///< CRS reset
-#define RCC_APB1RSTR_CAN_Pos            (25)
-#define RCC_APB1RSTR_CAN                (0x01U << RCC_APB1RSTR_CAN_Pos)         ///< CAN reset
-
-#define RCC_APB1RSTR_BKP_Pos            (27)
-#define RCC_APB1RSTR_BKP                (0x01U << RCC_APB1RSTR_BKP_Pos)         ///< Backup interface reset
-
-#define RCC_APB1RSTR_PWR_Pos            (28)
-#define RCC_APB1RSTR_PWR                (0x01U << RCC_APB1RSTR_PWR_Pos)         ///< Power interface reset
-#define RCC_APB1RSTR_DAC_Pos            (29)
-#define RCC_APB1RSTR_DAC                (0x01U << RCC_APB1RSTR_DAC_Pos)         ///< DAC interface reset
-
-
-#define RCC_APB1RSTR_UART7_Pos          (30)
-#define RCC_APB1RSTR_UART7              (0x01U << RCC_APB1RSTR_UART7_Pos)        ///< UART7 reset
-#define RCC_APB1RSTR_UART8_Pos          (31)
-#define RCC_APB1RSTR_UART8              (0x01U << RCC_APB1RSTR_UART8_Pos)        ///< UART8 reset
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_AHB2RSTR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_AHB2RSTR_USBFS_Pos          (7)
-#define RCC_AHB2RSTR_USBFS              (0x01U << RCC_AHB2RSTR_USBFS_Pos)       ///< USBFS reset
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_AHB3ENR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_AHB3ENR_FSMC_Pos            (0)
-#define RCC_AHB3ENR_FSMC                (0x01U << RCC_AHB3ENR_FSMC_Pos)       ///< FSMC reset
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_AHB2ENR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_AHB2ENR_USBFS_Pos           (7)
-#define RCC_AHB2ENR_USBFS               (0x01U << RCC_AHB2ENR_USBFS_Pos)       ///< USBFS reset
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_AHBENR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-
-
-
-#define RCC_AHBENR_GPIOA_Pos             (0)
-#define RCC_AHBENR_GPIOA                 (0x01U << RCC_AHBENR_GPIOA_Pos)          ///< GPIOA clock enable
-#define RCC_AHBENR_GPIOB_Pos             (1)
-#define RCC_AHBENR_GPIOB                 (0x01U << RCC_AHBENR_GPIOB_Pos)          ///< GPIOB clock enable
-#define RCC_AHBENR_GPIOC_Pos             (2)
-#define RCC_AHBENR_GPIOC                 (0x01U << RCC_AHBENR_GPIOC_Pos)          ///< GPIOC clock enable
-#define RCC_AHBENR_GPIOD_Pos             (3)
-#define RCC_AHBENR_GPIOD                 (0x01U << RCC_AHBENR_GPIOD_Pos)          ///< GPIOD clock enable
-#define RCC_AHBENR_GPIOE_Pos             (4)
-#define RCC_AHBENR_GPIOE                 (0x01U << RCC_AHBENR_GPIOE_Pos)          ///< GPIOE clock enable
-#define RCC_AHBENR_GPIOF_Pos             (5)
-#define RCC_AHBENR_GPIOF                 (0x01U << RCC_AHBENR_GPIOF_Pos)          ///< GPIOF clock enable
-#define RCC_AHBENR_GPIOG_Pos             (6)
-#define RCC_AHBENR_GPIOG                 (0x01U << RCC_AHBENR_GPIOG_Pos)          ///< GPIOG clock enable
-#define RCC_AHBENR_GPIOH_Pos             (7)
-#define RCC_AHBENR_GPIOH                 (0x01U << RCC_AHBENR_GPIOH_Pos)          ///< GPIOH clock enable
-#define RCC_AHBENR_SDIO_Pos             (10)
-#define RCC_AHBENR_SDIO                 (0x01U << RCC_AHBENR_SDIO_Pos)          ///< SDIO clock enable
-#define RCC_AHBENR_CRC_Pos              (12)
-#define RCC_AHBENR_CRC                  (0x01U << RCC_AHBENR_CRC_Pos)          ///< CRC clock enable
-#define RCC_AHBENR_FLASH_Pos            (13)
-#define RCC_AHBENR_FLASH                (0x01U << RCC_AHBENR_FLASH_Pos)          ///< FLASH clock enable
-#define RCC_AHBENR_SRAM_Pos             (14)
-#define RCC_AHBENR_SRAM                 (0x01U << RCC_AHBENR_SRAM_Pos)          ///< SRAM clock enable
-#define RCC_AHBENR_DMA1_Pos             (21)
-#define RCC_AHBENR_DMA1                 (0x01U << RCC_AHBENR_DMA1_Pos)          ///< DMA1 clock enable
-#define RCC_AHBENR_DMA2_Pos             (22)
-#define RCC_AHBENR_DMA2                 (0x01U << RCC_AHBENR_DMA2_Pos)          ///< DMA2 clock enable
-#define RCC_AHBENR_ETHMAC_Pos           (25)
-#define RCC_AHBENR_ETHMAC               (0x01U << RCC_AHBENR_ETHMAC_Pos)        ///< ETHMAC clock enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_APB2ENR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_APB2ENR_TIM1_Pos         (0)
-#define RCC_APB2ENR_TIM1             (0x01U << RCC_APB2ENR_TIM1_Pos)          ///< TIM1 enable
-#define RCC_APB2ENR_TIM8_Pos         (1)
-#define RCC_APB2ENR_TIM8             (0x01U << RCC_APB2ENR_TIM8_Pos)          ///< TIM8 enable
-#define RCC_APB2ENR_UART1_Pos        (4)
-#define RCC_APB2ENR_UART1            (0x01U << RCC_APB2ENR_UART1_Pos)         ///< UART1 enable
-#define RCC_APB2ENR_UART6_Pos        (5)
-#define RCC_APB2ENR_UART6            (0x01U << RCC_APB2ENR_UART6_Pos)         ///< UART6 enable
-#define RCC_APB2ENR_ADC1_Pos         (8)
-#define RCC_APB2ENR_ADC1             (0x01U << RCC_APB2ENR_ADC1_Pos)          ///< ADC1 enable
-#define RCC_APB2ENR_ADC2_Pos         (9)
-#define RCC_APB2ENR_ADC2             (0x01U << RCC_APB2ENR_ADC2_Pos)          ///< ADC2 enable
-#define RCC_APB2ENR_ADC3_Pos         (10)
-#define RCC_APB2ENR_ADC3             (0x01U << RCC_APB2ENR_ADC3_Pos)          ///< ADC3 enable
-#define RCC_APB2ENR_SPI1_Pos         (12)
-#define RCC_APB2ENR_SPI1             (0x01U << RCC_APB2ENR_SPI1_Pos)          ///< SPI1 enable
-#define RCC_APB2ENR_EXTI_Pos         (14)
-#define RCC_APB2ENR_EXTI             (0x01U << RCC_APB2ENR_EXTI_Pos)          ///< EXTI Block enable
-#define RCC_APB2ENR_SYSCFG_Pos       (14)
-#define RCC_APB2ENR_SYSCFG           (0x01U << RCC_APB2ENR_SYSCFG_Pos)        ///< SYSCFG enable
-#define RCC_APB2ENR_COMP_Pos         (15)
-#define RCC_APB2ENR_COMP             (0x01U << RCC_APB2ENR_COMP_Pos)          ///< COMP enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_APB1ENR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_APB1ENR_TIM2_Pos            (0)
-#define RCC_APB1ENR_TIM2                (0x01U << RCC_APB1ENR_TIM2_Pos)         ///< Timer 2 clock enable
-
-#define RCC_APB1ENR_TIM3_Pos            (1)
-#define RCC_APB1ENR_TIM3                (0x01U << RCC_APB1ENR_TIM3_Pos)         ///< Timer 3 clock enabled
-
-#define RCC_APB1ENR_TIM4_Pos            (2)
-#define RCC_APB1ENR_TIM4                (0x01U << RCC_APB1ENR_TIM4_Pos)         ///< Timer 4 clock enable
-
-
-#define RCC_APB1ENR_TIM5_Pos            (3)
-#define RCC_APB1ENR_TIM5                (0x01U << RCC_APB1ENR_TIM5_Pos)        ///< TIM5 Timer clock enable
-#define RCC_APB1ENR_TIM6_Pos            (4)
-#define RCC_APB1ENR_TIM6                (0x01U << RCC_APB1ENR_TIM6_Pos)        ///< TIM6 Timer clock enable
-#define RCC_APB1ENR_TIM7_Pos            (5)
-#define RCC_APB1ENR_TIM7                (0x01U << RCC_APB1ENR_TIM7_Pos)        ///< TIM7 Timer clock enable
-
-#define RCC_APB1ENR_WWDG_Pos            (11)
-#define RCC_APB1ENR_WWDG                (0x01U << RCC_APB1ENR_WWDG_Pos)         ///< Window Watchdog clock enable
-
-
-#define RCC_APB1ENR_SPI2_Pos            (14)
-#define RCC_APB1ENR_SPI2                (0x01U << RCC_APB1ENR_SPI2_Pos)         ///< SPI 2 clock enable
-#define RCC_APB1ENR_SPI3_Pos            (15)
-#define RCC_APB1ENR_SPI3                (0x01U << RCC_APB1ENR_SPI3_Pos)         ///< SPI 3 clock enable
-
-#define RCC_APB1ENR_UART2_Pos           (17)
-#define RCC_APB1ENR_UART2               (0x01U << RCC_APB1ENR_UART2_Pos)        ///< UART 2 clock enable
-#define RCC_APB1ENR_UART3_Pos           (18)
-#define RCC_APB1ENR_UART3               (0x01U << RCC_APB1ENR_UART3_Pos)        ///< UART 3 clock enable
-#define RCC_APB1ENR_UART4_Pos           (19)
-#define RCC_APB1ENR_UART4               (0x01U << RCC_APB1ENR_UART4_Pos)        ///< UART 4 clock enable
-#define RCC_APB1ENR_UART5_Pos           (20)
-#define RCC_APB1ENR_UART5               (0x01U << RCC_APB1ENR_UART5_Pos)        ///< UART 5 clock enable
-#define RCC_APB1ENR_I2C1_Pos            (21)
-#define RCC_APB1ENR_I2C1                (0x01U << RCC_APB1ENR_I2C1_Pos)         ///< I2C 1 clock enable
-#define RCC_APB1ENR_I2C2_Pos            (22)
-#define RCC_APB1ENR_I2C2                (0x01U << RCC_APB1ENR_I2C2_Pos)         ///< I2C 2 clock enable
-#define RCC_APB1ENR_CRS_Pos             (24)
-#define RCC_APB1ENR_CRS                 (0x01U << RCC_APB1ENR_CRS_Pos)         ///< CRS 4 clock enable
-#define RCC_APB1ENR_CAN_Pos             (25)
-#define RCC_APB1ENR_CAN                 (0x01U << RCC_APB1ENR_CAN_Pos)         ///< CAN 5 clock enable
-
-
-
-#define RCC_APB1ENR_BKP_Pos             (27)
-#define RCC_APB1ENR_BKP                 (0x01U << RCC_APB1ENR_BKP_Pos)          ///< Backup interface clock enable
-
-#define RCC_APB1ENR_PWR_Pos             (28)
-#define RCC_APB1ENR_PWR                 (0x01U << RCC_APB1ENR_PWR_Pos)          ///< Power interface clock enable
-
-#define RCC_APB1ENR_DBGMCU_Pos          (28)
-#define RCC_APB1ENR_DBGMCU              (0x01U << RCC_APB1ENR_DBGMCU_Pos)       ///< DBGMCU clock enable
-
-
-#define RCC_APB1ENR_DAC_Pos             (29)
-#define RCC_APB1ENR_DAC                 (0x01U << RCC_APB1ENR_DAC_Pos)          ///< DAC interface clock enable
-#define RCC_APB1ENR_UART7_Pos            (30)
-#define RCC_APB1ENR_UART7                (0x01U << RCC_APB1ENR_UART7_Pos)       ///< UART7 interface clock enable
-#define RCC_APB1ENR_UART8_Pos            (31)
-#define RCC_APB1ENR_UART8                (0x01U << RCC_APB1ENR_UART8_Pos)       ///< UART8 interface clock enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_BDCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_BDCR_LSEON_Pos              (0)
-#define RCC_BDCR_LSEON                  (0x01U << RCC_BDCR_LSEON_Pos)           ///< External Low Speed oscillator enable
-#define RCC_BDCR_LSERDY_Pos             (1)
-#define RCC_BDCR_LSERDY                 (0x01U << RCC_BDCR_LSERDY_Pos)          ///< External Low Speed oscillator Ready
-#define RCC_BDCR_LSEBYP_Pos             (2)
-#define RCC_BDCR_LSEBYP                 (0x01U << RCC_BDCR_LSEBYP_Pos)          ///< External Low Speed oscillator Bypass
-
-#define RCC_BDCR_RTCSEL_Pos             (8)
-#define RCC_BDCR_RTCSEL                 (0x03U << RCC_BDCR_RTCSEL_Pos)          ///< RTCSEL[1:0] bits (RTC clock source selection)
-#define RCC_BDCR_RTCSEL_LSE             (0x01U << RCC_BDCR_RTCSEL_Pos)          ///< LSE oscillator clock used as RTC clock
-#define RCC_BDCR_RTCSEL_LSI             (0x02U << RCC_BDCR_RTCSEL_Pos)          ///< LSI oscillator clock used as RTC clock
-#define RCC_BDCR_RTCSEL_HSE             (0x03U << RCC_BDCR_RTCSEL_Pos)          ///< HSE oscillator clock divided by 128 used as RTC clock
-
-#define RCC_BDCR_RTCEN_Pos              (15)
-#define RCC_BDCR_RTCEN                  (0x01U << RCC_BDCR_RTCEN_Pos)           ///< RTC clock enable
-#define RCC_BDCR_BDRST_Pos              (16)
-#define RCC_BDCR_BDRST                  (0x01U << RCC_BDCR_BDRST_Pos)           ///< Backup domain software reset
-#define RCC_BDCR_DBP_Pos                (24)
-#define RCC_BDCR_DBP                    (0x01U << RCC_BDCR_DBP_Pos)             ///< DBP clock enable
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_CSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_CSR_LSION_Pos               (0)
-#define RCC_CSR_LSION                   (0x01U << RCC_CSR_LSION_Pos)            ///< Internal Low Speed oscillator enable
-#define RCC_CSR_LSIRDY_Pos              (1)
-#define RCC_CSR_LSIRDY                  (0x01U << RCC_CSR_LSIRDY_Pos)           ///< Internal Low Speed oscillator Ready
-#define RCC_CSR_LSIOENLV_Pos            (5)
-#define RCC_CSR_LSIOENLV                (0x01U << RCC_CSR_LSIOENLV_Pos)         ///< LSI output enable lower voltage
-#define RCC_CSR_PVDRSTEN_Pos            (6)
-#define RCC_CSR_PVDRSTEN                (0x01U << RCC_CSR_PVDRSTEN_Pos)         ///< PVD reset enable
-#define RCC_CSR_LOCKUPEN_Pos            (7)
-#define RCC_CSR_LOCKUPEN                (0x01U << RCC_CSR_LOCKUPEN_Pos)         ///< CPU lockup reset enable
-#define RCC_CSR_VDTRSTNEN_Pos           (8)
-#define RCC_CSR_VDTRSTNEN               (0x01U << RCC_CSR_VDTRSTNEN_Pos)        ///< Voltage detect reset enable
-#define RCC_CSR_VDTRSTF_Pos             (21)
-#define RCC_CSR_VDTRSTF                 (0x01U << RCC_CSR_VDTRSTF_Pos)           ///< Voltage detect reset flag
-#define RCC_CSR_PVDRSTF_Pos             (22)
-#define RCC_CSR_PVDRSTF                 (0x01U << RCC_CSR_PVDRSTF_Pos)           ///< PVD reset flag
-#define RCC_CSR_LOCKUPF_Pos             (23)
-#define RCC_CSR_LOCKUPF                 (0x01U << RCC_CSR_LOCKUPF_Pos)           ///< CPU lockup reset flag
-
-#define RCC_CSR_RMVF_Pos                (24)
-#define RCC_CSR_RMVF                    (0x01U << RCC_CSR_RMVF_Pos)             ///< Remove reset flag
-#define RCC_CSR_PINRSTF_Pos             (26)
-#define RCC_CSR_PINRSTF                 (0x01U << RCC_CSR_PINRSTF_Pos)          ///< PIN reset flag
-
-#define RCC_CSR_PORRSTF_Pos             (27)
-#define RCC_CSR_PORRSTF                 (0x01U << RCC_CSR_PORRSTF_Pos)          ///< POR/PDR reset flag
-
-#define RCC_CSR_SFTRSTF_Pos             (28)
-#define RCC_CSR_SFTRSTF                 (0x01U << RCC_CSR_SFTRSTF_Pos)          ///< Software Reset flag
-
-#define RCC_CSR_IWDGRSTF_Pos            (29)
-#define RCC_CSR_IWDGRSTF                (0x01U << RCC_CSR_IWDGRSTF_Pos)         ///< Independent Watchdog reset flag
-
-#define RCC_CSR_WWDGRSTF_Pos            (30)
-#define RCC_CSR_WWDGRSTF                (0x01U << RCC_CSR_WWDGRSTF_Pos)         ///< Window watchdog reset flag
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_AHBRSTR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_AHBRSTR_GPIOA_Pos       (0)
-#define RCC_AHBRSTR_GPIOA           (0x01U << RCC_AHBRSTR_GPIOA_Pos)        ///< GPIOA clock reset
-#define RCC_AHBRSTR_GPIOB_Pos       (1)
-#define RCC_AHBRSTR_GPIOB           (0x01U << RCC_AHBRSTR_GPIOB_Pos)        ///< GPIOB clock reset
-#define RCC_AHBRSTR_GPIOC_Pos       (2)
-#define RCC_AHBRSTR_GPIOC           (0x01U << RCC_AHBRSTR_GPIOC_Pos)        ///< GPIOC clock reset
-#define RCC_AHBRSTR_GPIOD_Pos       (3)
-#define RCC_AHBRSTR_GPIOD           (0x01U << RCC_AHBRSTR_GPIOD_Pos)        ///< GPIOD clock reset
-#define RCC_AHBRSTR_GPIOE_Pos       (4)
-#define RCC_AHBRSTR_GPIOE           (0x01U << RCC_AHBRSTR_GPIOE_Pos)        ///< GPIOE clock reset
-#define RCC_AHBRSTR_GPIOF_Pos       (5)
-#define RCC_AHBRSTR_GPIOF           (0x01U << RCC_AHBRSTR_GPIOF_Pos)        ///< GPIOF clock reset
-#define RCC_AHBRSTR_GPIOG_Pos       (6)
-#define RCC_AHBRSTR_GPIOG           (0x01U << RCC_AHBRSTR_GPIOG_Pos)        ///< GPIOG clock reset
-#define RCC_AHBRSTR_GPIOH_Pos       (7)
-#define RCC_AHBRSTR_GPIOH           (0x01U << RCC_AHBRSTR_GPIOH_Pos)        ///< GPIOH clock reset
-#define RCC_AHBRSTR_SDIO_Pos       (10)
-#define RCC_AHBRSTR_SDIO           (0x01U << RCC_AHBRSTR_SDIO_Pos)          ///< SDIO clock reset
-#define RCC_AHBRSTR_CRC_Pos        (12)
-#define RCC_AHBRSTR_CRC            (0x01U << RCC_AHBRSTR_CRC_Pos)           ///< CRC clock reset
-#define RCC_AHBRSTR_DMA1_Pos       (21)
-#define RCC_AHBRSTR_DMA1           (0x01U << RCC_AHBRSTR_DMA1_Pos)          ///< DMA1 clock reset
-#define RCC_AHBRSTR_DMA2_Pos       (22)
-#define RCC_AHBRSTR_DMA2           (0x01U << RCC_AHBRSTR_DMA2_Pos)          ///< DMA2 clock reset
-#define RCC_AHBRSTR_ETHMAC_Pos     (25)
-#define RCC_AHBRSTR_ETHMAC         (0x01U << RCC_AHBRSTR_ETHMAC_Pos)        ///< ETHMAC clock reset
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_SYSCFG Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define RCC_SYSCFG_PROGCHECKEN_Pos       (0)
-#define RCC_SYSCFG_PROGCHECKEN           (0x01U << RCC_SYSCFG_PROGCHECKEN_Pos)  ///< Whether to check the number in Flash when writing to Flash
-#define RCC_SYSCFG_SECTOR1KCFG_Pos       (1)
-#define RCC_SYSCFG_SECTOR1KCFG           (0x01U << RCC_SYSCFG_SECTOR1KCFG_Pos)  ///< The size of the Flash page when erased.
-#define RCC_SYSCFG_DATAPREFETCH_Pos      (2)
-#define RCC_SYSCFG_DATAPREFETCH          (0x01U << RCC_SYSCFG_DATAPREFETCH_Pos) ///< DATA prefetch module enable bit
-#define RCC_SYSCFG_PAD_OSC_TRIM_Pos      (8)
-#define RCC_SYSCFG_PAD_OSC_TRIM          (0x1FU << RCC_SYSCFG_PAD_OSC_TRIM_Pos) ///< Calibration value of external crystal vibration
-#define RCC_SYSCFG_OSC_LPFEN_Pos         (14)
-#define RCC_SYSCFG_OSC_LPFEN             (0x01U << RCC_SYSCFG_OSC_LPFEN_Pos)    ///< External crystal oscillator low pass filtering enables  
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_CFGR2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_CFGR2_TIMADVCKSEL_Pos         (1)
-#define RCC_CFGR2_TIMADVCKSEL             (0x01U << RCC_CFGR2_TIMADVCKSEL_Pos)    ///< TIMADV_CKSEL
-#define RCC_CFGR2_TIMADV_PRE_Pos          (1)    ///< 
-#define RCC_CFGR2_TIMADV_PRE              (0x07U << RCC_CFGR2_TIMADV_PRE_Pos)     ///< SYSCLK's advance points are controlled by the software Frequency coefficient
-#define RCC_CFGR2_FSMC_PRE_Pos            (8)
-#define RCC_CFGR2_FSMC_PRE                (0x1FU << RCC_CFGR2_FSMC_PRE_Pos)       ///< FSMC Output clock frequency division factor
-#define RCC_CFGR2_APB1_CLK_HV_PRE_Pos     (16)
-#define RCC_CFGR2_APB1_CLK_HV_PRE         (0x0FU << RCC_CFGR2_APB1_CLK_HV_PRE_Pos) ///< APB1 Output clock frequency division factor
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_ICSCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_ICSCR_TIME_CRS_SEL_Pos         (0)
-#define RCC_ICSCR_TIME_CRS_SEL             (0x01U << RCC_ICSCR_TIME_CRS_SEL_Pos) ///< Whether to use the CRS module as source
-#define RCC_ICSCR_HSI_CAL_SEL_Pos          (11)    ///< 
-#define RCC_ICSCR_HSI_CAL_SEL              (0x1FU << RCC_ICSCR_HSI_CAL_SEL_Pos)  ///< Select the internal high speed clock calibration value
-#define RCC_ICSCR_HSI_CAL_SFT_Pos          (16)
-#define RCC_ICSCR_HSI_CAL_SFT              (0x3FU << RCC_ICSCR_HSI_CAL_SFT_Pos)  ///< Internal high-speed clock calibration
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_PLLCFGR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_PLLCFGR_PLLSRC_Pos             (0)
-#define RCC_PLLCFGR_PLLSRC                 (0x01U << RCC_PLLCFGR_PLLSRC_Pos)     ///< PLL entry clock source
-#define RCC_PLLCFGR_PLLXTPRE_Pos           (1)    ///< 
-#define RCC_PLLCFGR_PLLXTPRE               (0x01U << RCC_PLLCFGR_PLLXTPRE_Pos)   ///< HSE divider for PLL entry
-#define RCC_PLLCFGR_PLL_ICTRL_Pos          (2)
-#define RCC_PLLCFGR_PLL_ICTRL              (0x03U << RCC_PLLCFGR_PLL_ICTRL_Pos)  ///< PLL CP current control signals
-#define RCC_PLLCFGR_PLL_LDS_Pos            (4)
-#define RCC_PLLCFGR_PLL_LDS                (0x03U << RCC_PLLCFGR_PLL_LDS_Pos)    ///< PLL lock detector accuracy select
-#define RCC_PLLCFGR_PLL_DP_Pos             (8)    ///< 
-#define RCC_PLLCFGR_PLL_DP                 (0x07U << RCC_PLLCFGR_PLL_DP_Pos)     ///< PLL divider factor DP
-#define RCC_PLLCFGR_PLL_DN_Pos             (16)
-#define RCC_PLLCFGR_PLL_DN                 (0x7FU << RCC_PLLCFGR_PLL_DN_Pos)     ///< PLL divider factor DN
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_HSIDLY Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_HSIDLY_HSI_EQU_CNT             (0xFFU)                               ///< HSI delay time
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_HSEDLY Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_HSEDLY_HSI_EQU_CNT             (0xFFFFU)                               ///< HSE delay time
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RCC_PLLDLY Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RCC_PLLDLY_HSI_EQU_CNT             (0xFFU)                               ///< PLL delay time
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h
deleted file mode 100644
index 7f8acab01..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_rtc.h
+++ /dev/null
@@ -1,203 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_rtc.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_RTC_H
-#define __REG_RTC_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_BASE                    (APB1PERIPH_BASE + 0x2800)              ///< Base Address: 0x40002800
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC Registers Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    union {
-        __IO u32 CR;                                                                ///< Control Register,                      offset: 0x00
-        __IO u32 CRH;
-    };
-    union {
-        __IO u32 CSR;                                                               ///< Control & Status Register,             offset: 0x04
-        __IO u32 CRL;
-    };
-    __IO u32 PRLH;                                                              ///< Prescaler Reload Value High,           offset: 0x08
-    __IO u32 PRLL;                                                              ///< Prescaler Reload Value Low,            offset: 0x0C
-    __IO u32 DIVH;                                                              ///< Clock Divider High,                    offset: 0x10
-    __IO u32 DIVL;                                                              ///< Clock Divider Low,                     offset: 0x14
-    __IO u32 CNTH;                                                              ///< Counter High,                          offset: 0x18
-    __IO u32 CNTL;                                                              ///< Counter Low,                           offset: 0x1C
-    __IO u32 ALRH;                                                              ///< Alarm High,                            offset: 0x20
-    __IO u32 ALRL;                                                              ///< Alarm Low,                             offset: 0x24
-    __IO u32 MSRH;                                                              ///< Millisecond alarm high register        offset: 0x28
-    __IO u32 MSRL;                                                              ///< Millisecond alarm low register         offset: 0x2C
-    __IO u32 RESERVED0;                                                         ///< Reserved                               offset: 0x30
-    __IO u32 RESERVED1;                                                         ///< Reserved                               offset: 0x34
-    __IO u32 RESERVED2;                                                         ///< Reserved                               offset: 0x38
-    __IO u32 LSE_CFG;                                                           ///< LSE configure register                 offset: 0x3C
-} RTC_TypeDef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC                         ((RTC_TypeDef*)RTC_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_CR_SECIE_Pos            (0)
-#define RTC_CR_SECIE                (0x01U << RTC_CR_SECIE_Pos)             ///< Second Interrupt Enable
-#define RTC_CR_ALRIE_Pos            (1)
-#define RTC_CR_ALRIE                (0x01U << RTC_CR_ALRIE_Pos)             ///< Alarm Interrupt Enable
-#define RTC_CR_OWIE_Pos             (2)
-#define RTC_CR_OWIE                 (0x01U << RTC_CR_OWIE_Pos)              ///< OverfloW Interrupt Enable
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_CSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_CSR_SECF_Pos            (0)
-#define RTC_CSR_SECF                (0x01 << RTC_CSR_SECF_Pos)              ///< Second Flag
-#define RTC_CSR_ALRF_Pos            (1)
-#define RTC_CSR_ALRF                (0x01 << RTC_CSR_ALRF_Pos)              ///< Alarm Flag
-#define RTC_CSR_OWF_Pos             (2)
-#define RTC_CSR_OWF                 (0x01 << RTC_CSR_OWF_Pos)               ///< OverfloW Flag
-#define RTC_CSR_RSF_Pos             (3)
-#define RTC_CSR_RSF                 (0x01 << RTC_CSR_RSF_Pos)               ///< Registers Synchronized Flag
-#define RTC_CSR_CNF_Pos             (4)
-#define RTC_CSR_CNF                 (0x01 << RTC_CSR_CNF_Pos)               ///< Configuration Flag
-#define RTC_CSR_RTOFF_Pos           (5)
-#define RTC_CSR_RTOFF               (0x01 << RTC_CSR_RTOFF_Pos)             ///< RTC operation OFF
-#define RTC_CSR_ALPEN_Pos           (6)
-#define RTC_CSR_ALPEN               (0x01 << RTC_CSR_ALPEN_Pos)             ///< RTC Alarm Loop Enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_PRLH Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_PRLH_PRL_Pos            (0)
-#define RTC_PRLH_PRL                (0x0F << RTC_PRLH_PRL_Pos)              ///< RTC Prescaler Reload Value High
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_PRLL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_PRLL_PRL_Pos            (0)
-#define RTC_PRLL_PRL                (0xFFFFU << RTC_PRLL_PRL_Pos)           ///< RTC Prescaler Reload Value Low
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_DIVH Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_DIVH_DIV_Pos            (0)
-#define RTC_DIVH_DIV                (0x0F << RTC_DIVH_DIV_Pos)              ///< RTC Clock Divider High
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_DIVL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_DIVL_DIV_Pos            (0)
-#define RTC_DIVL_DIV                (0xFFFFU << RTC_DIVL_DIV_Pos)           ///< RTC Clock Divider Low
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_CNTH Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_CNTH_CNT_Pos            (0)
-#define RTC_CNTH_CNT                (0xFFFFU << RTC_CNTH_CNT_Pos)           ///< RTC Counter High
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_CNTL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_CNTL_CNT_Pos            (0)
-#define RTC_CNTL_CNT                (0xFFFFU << RTC_CNTL_CNT_Pos)           ///< RTC Counter Low
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_ALRH Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_ALRH_ALR_Pos            (0)
-#define RTC_ALRH_ALR                (0xFFFFU << RTC_ALRH_ALR_Pos)           ///< RTC Alarm High
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_ALRL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_ALRL_ALR_Pos            (0)
-#define RTC_ALRL_ALR                (0xFFFFU << RTC_ALRL_ALR_Pos)           ///< RTC Alarm Low
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_MSRH Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_MSRH_MSR_Pos            (0)
-#define RTC_MSRH_MSR                (0xFFFFU << RTC_MSRH_MSR_Pos)          ///< RTC MS Alarm Register High
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_MSRL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define RTC_MSRL_MSR_Pos            (0)
-#define RTC_MSRL_MSR                (0xFFFFU << RTC_MSRL_MSR_Pos)           ///< RTC MS Alarm Register Low
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief RTC_LSE_CFG Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define RTC_LSE_CFG_TEST_Pos        (0)
-#define RTC_LSE_CFG_TEST            (0x0FU << RTC_LSE_CFG_TEST_Pos)              ///< Test control signal
-#define RTC_LSE_CFG_DR_Pos          (4)
-#define RTC_LSE_CFG_DR              (0x03U << RTC_LSE_CFG_DR_Pos)                ///< Drive capability selection
-#define RTC_LSE_CFG_RFB_SEL_Pos     (6)
-#define RTC_LSE_CFG_RFB_SEL_3       (0x03U << RTC_LSE_CFG_RFB_SEL_Pos)           ///< Feedback resistance selection 3M  
-#define RTC_LSE_CFG_RFB_SEL_6       (0x02U << RTC_LSE_CFG_RFB_SEL_Pos)           ///< Feedback resistance selection 6M 
-#define RTC_LSE_CFG_RFB_SEL_10      (0x01U << RTC_LSE_CFG_RFB_SEL_Pos)           ///< Feedback resistance selection 10M
-#define RTC_LSE_CFG_RFB_SEL_12      (0x00U << RTC_LSE_CFG_RFB_SEL_Pos)           ///< Feedback resistance selection 12M
-#define RTC_LSE_CFG_IB_Pos          (8)
-#define RTC_LSE_CFG_IB              (0x01U << RTC_MSRL_MSR_Pos)                  ///< Bias current regulation
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h
deleted file mode 100644
index 9c5d0cb60..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_sdio.h
+++ /dev/null
@@ -1,391 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_sdio.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_SDIO_H
-#define __REG_SDIO_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-//#include "types.h"
-#include "mm32_reg.h"
-
-//#if defined ( __CC_ARM )
-//#pragma anon_unions
-//#endif
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_BASE                        (0x40018000U)                            ///< Base Address: 0x40018000
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-
-typedef struct {
-    __IO u32 MMC_CTRL;                                                          ///< SDIO transmit data register,                    offset: 0x00
-    __IO u32 MMC_IO;                                                            ///< SDIO receive data register,                     offset: 0x04
-    __IO u32 MMC_BYTECNTL;                                                      ///< SDIO current state register,                    offset: 0x08
-    __IO u32 MMC_TR_BLOCKCNT;                                                   ///< SDIO interruput state register,                 offset: 0x0C
-    __IO u32 MMC_CRCCTL;                                                        ///< SDIO interruput enable register,                offset: 0x10
-    __IO u32 CMD_CRC;                                                           ///< SDIO interruput control register,               offset: 0x14
-    __IO u32 DAT_CRCL;                                                          ///< SDIO global control register,                   offset: 0x18
-    __IO u32 DAT_CRCH;                                                          ///< SDIO common control register,                   offset: 0x1C
-    __IO u32 MMC_PORT;                                                          ///< SDIO baud rate control register,                offset: 0x20
-    __IO u32 MMC_INT_MASK;                                                      ///< SDIO receive data number register,              offset: 0x24
-    __IO u32 CLR_MMC_INT;                                                       ///< SDIO chip select register,                      offset: 0x28
-    __IO u32 MMC_CARDSEL;                                                       ///< SDIO extand control register,                   offset: 0x2C
-    __IO u32 MMC_SIG;                                                           ///<                                                 0ffset: 0x30
-    __IO u32 MMC_IO_MBCTL;                                                      ///<                                                 0ffset: 0x34
-    __IO u32 MMC_BLOCKCNT;                                                      ///<                                                 0ffset: 0x38
-    __IO u32 MMC_TIMEOUTCNT;                                                    ///<                                                 0ffset: 0x3C
-    __IO u32 CMD_BUF0;                                                          ///<                                                 0ffset: 0x40
-    __IO u32 CMD_BUF1;                                                          ///<                                                 0ffset: 0x44
-    __IO u32 CMD_BUF2;                                                          ///<                                                 0ffset: 0x48
-    __IO u32 CMD_BUF3;                                                          ///<                                                 0ffset: 0x4C
-    __IO u32 CMD_BUF4;                                                          ///<                                                 0ffset: 0x50
-    __IO u32 CMD_BUF5;                                                          ///<                                                 0ffset: 0x54
-    __IO u32 CMD_BUF6;                                                          ///<                                                 0ffset: 0x58
-    __IO u32 CMD_BUF7;                                                          ///<                                                 0ffset: 0x5C
-    __IO u32 CMD_BUF8;                                                          ///<                                                 0ffset: 0x60
-    __IO u32 CMD_BUF9;                                                          ///<                                                 0ffset: 0x64
-    __IO u32 CMD_BUF10;                                                         ///<                                                 0ffset: 0x68
-    __IO u32 CMD_BUF11;                                                         ///<                                                 0ffset: 0x6C
-    __IO u32 CMD_BUF12;                                                         ///<                                                 0ffset: 0x70
-    __IO u32 CMD_BUF13;                                                         ///<                                                 0ffset: 0x74
-    __IO u32 CMD_BUF14;                                                         ///<                                                 0ffset: 0x78
-    __IO u32 CMD_BUF15;                                                         ///<                                                 0ffset: 0x7C
-    __IO u32 BUF_CTL;                                                           ///<                                                 0ffset: 0x80
-
-    __IO u32 RESERVED[31];                                                      ///<                                                 0ffset: 0x84
-    union {
-        __IO u32 DATA_BUF0;                                                         ///<                                                 0ffset: 0x100
-        __IO u32 FIFO;
-    };
-    __IO u32 DATA_BUF1;                                                         ///<                                                 0ffset: 0x104
-    __IO u32 DATA_BUF2;                                                         ///<                                                 0ffset: 0x108
-    __IO u32 DATA_BUF3;                                                         ///<                                                 0ffset: 0x10C
-    __IO u32 DATA_BUF4;                                                         ///<                                                 0ffset: 0x110
-} SDIO_TypeDef;
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO                            ((SDIO_TypeDef*) SDIO_BASE)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_CTRL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_CTRL_OPMSel_Pos               (0)
-#define SDIO_MMC_CTRL_OPMSel                   (0x01U << SDIO_MMC_CTRL_OPMSel_Pos)      ///< SD/MMC/SDIO port operation mode select
-#define SDIO_MMC_CTRL_SelSM_Pos                (1)
-#define SDIO_MMC_CTRL_SelSM                    (0x01U << SDIO_MMC_CTRL_SelSM_Pos)      ///< Select automatic mode
-#define SDIO_MMC_CTRL_OUTM_Pos                 (2)
-#define SDIO_MMC_CTRL_OUTM                     (0x01U << SDIO_MMC_CTRL_OUTM_Pos)      ///< SD/MMC/SDIO port CMD line output driver mode selection Open drain
-#define SDIO_MMC_CTRL_CLKSP_Pos                (3)
-#define SDIO_MMC_CTRL_CLKSP2                   (0x00U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/2  baseclock
-#define SDIO_MMC_CTRL_CLKSP4                   (0x01U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/4  baseclock
-#define SDIO_MMC_CTRL_CLKSP6                   (0x02U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/6  baseclock
-#define SDIO_MMC_CTRL_CLKSP8                   (0x03U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/8  baseclock
-#define SDIO_MMC_CTRL_CLKSP10                  (0x04U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/10 baseclock
-#define SDIO_MMC_CTRL_CLKSP12                  (0x05U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/12 baseclock
-#define SDIO_MMC_CTRL_CLKSP14                  (0x06U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/14 baseclock
-#define SDIO_MMC_CTRL_CLKSP16                  (0x07U << SDIO_MMC_CTRL_CLKSP_Pos)      ///< SD/MMC/SDIO port CLK linespeedselection 1/16 baseclock
-#define SDIO_MMC_CTRL_SelPTSM_Pos              (6)
-#define SDIO_MMC_CTRL_SelPTSM                  (0x01U << SDIO_MMC_CTRL_SelPTSM_Pos)    ///< SelectSD/MMC/SDIO port transfer high speed mode
-#define SDIO_MMC_CTRL_DATWT_Pos                (7)
-#define SDIO_MMC_CTRL_DATWT                    (0x01U << SDIO_MMC_CTRL_DATWT_Pos)      ///< Definethe bus width of SD/MMC/SDIO port DAT line
-#define SDIO_MMC_CTRL_MDEN_Pos                 (8)
-#define SDIO_MMC_CTRL_MDEN                     (0x01U << SDIO_MMC_CTRL_MDEN_Pos)       ///< SDIO mode enable
-#define SDIO_MMC_CTRL_INTEN_Pos                (9)
-#define SDIO_MMC_CTRL_INTEN                    (0x01U << SDIO_MMC_CTRL_INTEN_Pos)      ///< SDIO interrupt enale signal
-#define SDIO_MMC_CTRL_RDWTEN_Pos               (10)
-#define SDIO_MMC_CTRL_RDWTEN                   (0x01U << SDIO_MMC_CTRL_RDWTEN_Pos)     ///< SDIO read wait enable signal
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_IO Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_IO_AUTODATTR_Pos               (0)
-#define SDIO_MMC_IO_AUTODATTR                   (0x01U << SDIO_MMC_IO_AUTODATTR_Pos)      ///< Set up automatic data transfer
-#define SDIO_MMC_IO_TRANSFDIR_Pos               (1)
-#define SDIO_MMC_IO_TRANSFDIR                   (0x01U << SDIO_MMC_IO_TRANSFDIR_Pos)      ///< Set the direction of data transfer
-#define SDIO_MMC_IO_AUTOTR_Pos                  (2)
-#define SDIO_MMC_IO_AUTOTR                      (0x01U << SDIO_MMC_IO_AUTOTR_Pos)        ///< Set up automatic 8-bit/command/response transmission.
-#define SDIO_MMC_IO_RESPCMDSEL_Pos              (3)
-#define SDIO_MMC_IO_RESPCMDSEL                  (0x01U << SDIO_MMC_IO_RESPCMDSEL_Pos)    ///< Receive response
-#define SDIO_MMC_IO_CID_CSDRD_Pos               (4)
-#define SDIO_MMC_IO_CID_CSDRD                   (0x01U << SDIO_MMC_IO_CID_CSDRD_Pos)     ///< CID and CSD reads
-#define SDIO_MMC_IO_PCLKG_Pos                   (5)
-#define SDIO_MMC_IO_PCLKG                       (0x01U << SDIO_MMC_IO_PCLKG_Pos)         ///< SD/MMC/SDIO port CLK line 8 empty clock generated
-#define SDIO_MMC_IO_ENRRESP_Pos                 (6)
-#define SDIO_MMC_IO_ENRRESP                     (0x01U << SDIO_MMC_IO_ENRRESP_Pos)       ///< Enable automatic receiving of responses after a command
-#define SDIO_MMC_IO_AUTOCLKG_Pos                (7)
-#define SDIO_MMC_IO_AUTOCLKG                    (0x01U << SDIO_MMC_IO_AUTOCLKG_Pos)      ///< Enable automatic conversion of the 8 empty clock after a response/command or a single block of data
-#define SDIO_MMC_IO_CMDCH_Pos                   (8)
-#define SDIO_MMC_IO_CMDCH                       (0x01U << SDIO_MMC_IO_CMDCH_Pos)         ///< SDIO mode enable
-#define SDIO_MMC_IO_CMDAF_Pos                   (9)
-#define SDIO_MMC_IO_CMDAF                       (0x01U << SDIO_MMC_IO_CMDAF_Pos)        ///< SDIO CMD12 / IO abort flag
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_BYTECNTL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_BYTECNTL_CNT                    (0xFFFFU)                              ///< Data transfer byte count register
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_TR_BLOCKCNT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_TR_BLOCKCNT_CNT                 (0xFFFFU)                              ///< The value of the counter that completes the transfer when multiple blocks are transferred.
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_CRCCTL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_CRCCTL_DAT_CRCE_Pos             (0)
-#define SDIO_MMC_CRCCTL_DAT_CRCE                 (0x01U << SDIO_MMC_CRCCTL_DAT_CRCE_Pos)      ///< DAT CRC error
-#define SDIO_MMC_CRCCTL_CMD_CRCE_Pos             (1)
-#define SDIO_MMC_CRCCTL_CMD_CRCE                 (0x01U << SDIO_MMC_CRCCTL_CMD_CRCE_Pos)      ///< CMD CRC error
-#define SDIO_MMC_CRCCTL_DAT_CRCS_Pos             (2)
-#define SDIO_MMC_CRCCTL_DAT_CRCS                 (0x03U << SDIO_MMC_CRCCTL_DAT_CRCS_Pos)      ///< DAT CRC selection
-#define SDIO_MMC_CRCCTL_ENRDMB_Pos               (4)
-#define SDIO_MMC_CRCCTL_ENRDMB                   (0x01U << SDIO_MMC_CRCCTL_ENRDMB_Pos)        ///< Enable reading multiple blocks of data before responding
-#define SDIO_MMC_CRCCTL_ENCHK_Pos                (5)
-#define SDIO_MMC_CRCCTL_ENCHK                    (0x01U << SDIO_MMC_CRCCTL_ENCHK_Pos)         ///< Enable automatic checking 
-#define SDIO_MMC_CRCCTL_DAT_CRCEN_Pos            (6)
-#define SDIO_MMC_CRCCTL_DAT_CRCEN                (0x01U << SDIO_MMC_CRCCTL_DAT_CRCEN_Pos)     ///< SD/MMC/SDIO PORT DAT line CRC circuit enablement
-#define SDIO_MMC_CRCCTL_CMD_CRCEN_Pos            (7)
-#define SDIO_MMC_CRCCTL_CMD_CRCEN                (0x01U << SDIO_MMC_CRCCTL_CMD_CRCEN_Pos)     ///< SD/MMC/SDIO port CMD line CRC circuit enablement
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_CRC Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_CRC_CMD_CRCV                    (0x7FU)                                 ///< CMD_CRCV register value
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_DAT_CRCL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_DAT_CRCL_DAT_CRCLV                  (0xFFU)                                 ///< CMD_CRCV low  register value
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_DAT_CRCH Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_DAT_CRCL_DAT_CRCHV                  (0xFFU)                                 ///< CMD_CRCV high register value
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_PORT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_PORT_NTCR_Pos                   (0)
-#define SDIO_MMC_PORT_NTCR                       (0x0FU << SDIO_MMC_PORT_NTCR_Pos)      ///< Ncr timeout count register
-#define SDIO_MMC_PORT_AUTONTEN_Pos               (4)
-#define SDIO_MMC_PORT_AUTONTEN                   (0x01U << SDIO_MMC_PORT_AUTONTEN_Pos)  ///< Automatic Ncr timer output enablement
-#define SDIO_MMC_PORT_PDATS_Pos                  (5)
-#define SDIO_MMC_PORT_PDATS                      (0x01U << SDIO_MMC_PORT_PDATS_Pos)     ///< SD/MMC/SDIO port DAT line signal
-#define SDIO_MMC_PORT_PCMDS_Pos                  (6)
-#define SDIO_MMC_PORT_PCMDS                      (0x01U << SDIO_MMC_PORT_PCMDS_Pos)     ///< SD/MMC/SDIO port CMD line signal
-#define SDIO_MMC_PORT_PCLKS_Pos                  (7)
-#define SDIO_MMC_PORT_PCLKS                      (0x01U << SDIO_MMC_PORT_PCLKS_Pos)     ///< SD/MMC/SDIO port CLK line signal
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_INT_MASK Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_INT_MASK_CMDDINT_Pos             (0)
-#define SDIO_MMC_INT_MASK_CMDDINT                 (0x01U << SDIO_MMC_INT_MASK_CMDDINT_Pos)      ///<CMD completes interrupt shielding
-#define SDIO_MMC_INT_MASK_DATDINT_Pos             (1)
-#define SDIO_MMC_INT_MASK_DATDINT                 (0x01U << SDIO_MMC_INT_MASK_DATDINT_Pos)      ///< DAT completes interrupt shielding
-#define SDIO_MMC_INT_MASK_DATEINT_Pos             (2)
-#define SDIO_MMC_INT_MASK_DATEINT                 (0x01U << SDIO_MMC_INT_MASK_DATEINT_Pos)      ///< DAT CRC error interrupt masking
-#define SDIO_MMC_INT_MASK_CMDEINT_Pos             (3)
-#define SDIO_MMC_INT_MASK_CMDEINT                 (0x01U << SDIO_MMC_INT_MASK_CMDEINT_Pos)     ///< CMD CRC error interrupt masking
-#define SDIO_MMC_INT_MASK_MBDINTM_Pos             (4)
-#define SDIO_MMC_INT_MASK_MBDINTM                 (0x01U << SDIO_MMC_INT_MASK_MBDINTM_Pos)     ///< Multiple blocks complete interrupt shielding 
-#define SDIO_MMC_INT_MASK_MBTINTM_Pos             (5)
-#define SDIO_MMC_INT_MASK_MBTINTM                 (0x01U << SDIO_MMC_INT_MASK_MBTINTM_Pos)     ///< Multiblock timeout interrupt shielding
-#define SDIO_MMC_INT_MASK_CRTINTM_Pos             (6)
-#define SDIO_MMC_INT_MASK_CRTINTM                 (0x01U << SDIO_MMC_INT_MASK_CRTINTM_Pos)     ///< Cmd and Resp Ncr timeout interrupt shielding
-#define SDIO_MMC_INT_MASK_CRCINTM_Pos             (7)
-#define SDIO_MMC_INT_MASK_CRCINTM                 (0x01U << SDIO_MMC_INT_MASK_CRCINTM_Pos)     ///< CRC status token error interrupt masking
-#define SDIO_MMC_INT_MASK_D1INTM_Pos              (8)
-#define SDIO_MMC_INT_MASK_D1INTM                  (0x01U << SDIO_MMC_INT_MASK_D1INTM_Pos)     ///< SDIO Data 1 Line Interrupt Mask
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CLR_MMC_INT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CLR_MMC_INT_CMDDMC_Pos             (0)
-#define SDIO_CLR_MMC_INT_CMDDMC                 (0x01U << SDIO_CLR_MMC_INT_CMDDMC_Pos)      ///< CMD completes interrupt mask bit
-#define SDIO_CLR_MMC_INT_DATDMC_Pos             (1)
-#define SDIO_CLR_MMC_INT_DATDMC                 (0x01U << SDIO_CLR_MMC_INT_DATDMC_Pos)      ///< DAT completes interrupt mask bit
-#define SDIO_CLR_MMC_INT_DATEMC_Pos             (2)
-#define SDIO_CLR_MMC_INT_DATEMC                 (0x01U << SDIO_CLR_MMC_INT_DATEMC_Pos)      ///< DAT CRC error interrupt mask bit
-#define SDIO_CLR_MMC_INT_CMDEMC_Pos             (3)
-#define SDIO_CLR_MMC_INT_CMDEMC                 (0x01U << SDIO_CLR_MMC_INT_CMDEMC_Pos)     ///< CMD CRC error interrupt mask bit
-#define SDIO_CLR_MMC_INT_MBDMC_Pos              (4)
-#define SDIO_CLR_MMC_INT_MBDMC                  (0x01U << SDIO_CLR_MMC_INT_MBDMC_Pos)      ///< Multi - block transmission completion interrupt mask bit 
-#define SDIO_CLR_MMC_INT_MBTMC_Pos              (5)
-#define SDIO_CLR_MMC_INT_MBTMC                  (0x01U << SDIO_CLR_MMC_INT_MBTMC_Pos)      ///< Multiblock transmission timeout interrupt mask bit
-#define SDIO_CLR_MMC_INT_CRNTMC_Pos             (6)
-#define SDIO_CLR_MMC_INT_CRNTMC                 (0x01U << SDIO_CLR_MMC_INT_CRNTMC_Pos)     ///< Command and response Ncr timeout interrupt mask bit
-#define SDIO_CLR_MMC_INT_CRCEMC_Pos             (7)
-#define SDIO_CLR_MMC_INT_CRCEMC                 (0x01U << SDIO_CLR_MMC_INT_CRCEMC_Pos)     ///< CRC status error marks the interrupt mask bit
-#define SDIO_CLR_MMC_INT_D1MC_Pos               (8)
-#define SDIO_CLR_MMC_INT_D1MC                   (0x01U << SDIO_CLR_MMC_INT_D1MC_Pos)       ///< SDIO DatA1 line interrupt flag/clear bit
-#define SDIO_CLR_MMC_INT_MASK                   (0XFFU)
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_CARDSEL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_CARDSEL_TSCALE_Pos             (0)
-#define SDIO_MMC_CARDSEL_TSCALE                 (0x01U << SDIO_MMC_CARDSEL_TSCALE_Pos)      ///< SD/MMC/SDIO clock frequency division factor (based on 1MHz
-#define SDIO_MMC_CARDSEL_ENPCLK_Pos             (6)
-#define SDIO_MMC_CARDSEL_ENPCLK                 (0x01U << SDIO_MMC_CARDSEL_ENPCLK_Pos)      ///< Enabling card's SD/MMC/SDIO port CLK clock
-#define SDIO_MMC_CARDSEL_CTREN_Pos              (7)
-#define SDIO_MMC_CARDSEL_CTREN                  (0x01U << SDIO_MMC_CARDSEL_CTREN_Pos)      ///< SD/MMC/SDIO controller enablement bit
-#define SDIO_MMC_CARDSEL_MASK                   (0XFFU)
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_SIQ Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_SIQ_PDAT0S_Pos                 (0)
-#define SDIO_MMC_SIQ_PDAT0S                     (0x01U << SDIO_MMC_SIQ_PDAT0S_Pos)         ///< SD/MMC/SDIO port DAT0 line signal
-#define SDIO_MMC_SIQ_PDAT1S_Pos                 (1)
-#define SDIO_MMC_SIQ_PDAT1S                     (0x01U << SDIO_MMC_SIQ_PDAT1S_Pos)         ///< SD/MMC/SDIO port DAT1 line signal
-#define SDIO_MMC_SIQ_PDAT2S_Pos                 (2)
-#define SDIO_MMC_SIQ_PDAT2S                     (0x01U << SDIO_MMC_SIQ_PDAT2S_Pos)         ///< SD/MMC/SDIO port DAT2 line signal
-#define SDIO_MMC_SIQ_PDAT3S_Pos                 (3)
-#define SDIO_MMC_SIQ_PDAT3S                     (0x01U << SDIO_MMC_SIQ_PDAT3S_Pos)         ///< SD/MMC/SDIO port DAT3 line signal
-#define SDIO_MMC_SIQ_CRC_status_Pos             (4)
-#define SDIO_MMC_SIQ_CRC_status                 (0x07U << SDIO_MMC_SIQ_CRC_status_Pos)     ///< CRC state
-#define SDIO_MMC_SIQ_PCMDS_Pos                  (7)
-#define SDIO_MMC_SIQ_PCMDS                      (0x01U << SDIO_MMC_SIQ_PCMDS_Pos)          ///< SD/MMC/SDIO port CMD line signal
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_IO_MBCTL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_IO_MBCTL_SPMBDTR_Pos           (0)
-#define SDIO_MMC_IO_MBCTL_SPMBDTR               (0x01U << SDIO_MMC_IO_MBCTL_SPMBDTR_Pos)   ///< Set the SD/MMC/SDIO port to automatically multiblock data transfer bit
-#define SDIO_MMC_IO_MBCTL_SMBDTD_Pos            (1)
-#define SDIO_MMC_IO_MBCTL_SMBDTD                (0x01U << SDIO_MMC_IO_MBCTL_SMBDTD_Pos)    //< Multi - block data transfer direction selection bit
-#define SDIO_MMC_IO_MBCTL_PAUTOTR_Pos           (2)
-#define SDIO_MMC_IO_MBCTL_PAUTOTR               (0x01U << SDIO_MMC_IO_MBCTL_PAUTOTR_Pos)   ///< Set up SD/MMC/SDIO port automatic command and multi - block data transfer
-#define SDIO_MMC_IO_MBCTL_PCLKP_Pos             (3)
-#define SDIO_MMC_IO_MBCTL_PCLKP                 (0x01U << SDIO_MMC_IO_MBCTL_PCLKP_Pos)     ///< SD/MMC/SDIO port CLK line polarity selection bit
-#define SDIO_MMC_IO_MBCTL_BTSSel_Pos            (4)
-#define SDIO_MMC_IO_MBCTL_BTSSel                (0x03U << SDIO_MMC_SIQ_CRC_status_Pos)     ///< SD/MMC/SDIO BUSY Timeout level selects bits
-#define SDIO_MMC_IO_MBCTL_BTSSel_2              (0x02U << SDIO_MMC_SIQ_CRC_status_Pos)     ///< SD/MMC/SDIO BUSY Timeout level selects bits
-#define SDIO_MMC_IO_MBCTL_NTSSel_Pos            (6)
-#define SDIO_MMC_IO_MBCTL_NTSSel                (0x03U << SDIO_MMC_IO_MBCTL_NTSSel_Pos)    ///< SD/MMC/SDIO NAC timeout level selection bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_BLOCKCNT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_BLOCKCNT_EN                    (0xFFFFU)                                 ///< Block count register
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_MMC_TIMEOUTCNT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_MMC_TIMEOUTCNT_DTCNT                (0xFFU)                                 ///< Data transfer timeout count register
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF0 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF0_DAT                        (0xFFU)                                 ///< Cmd_buf0 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF1 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF1_DAT                        (0xFFU)                                 ///< Cmd_buf1 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF2_DAT                        (0xFFU)                                 ///< Cmd_buf2 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF3 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF3_DAT                        (0xFFU)                                 ///< Cmd_buf3 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF4 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF4_DAT                        (0xFFU)                                 ///< Cmd_buf4 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF5 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF5_DAT                        (0xFFU)                                 ///< Cmd_buf5 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF6 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF6_DAT                        (0xFFU)                                 ///< Cmd_buf6 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF7 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF7_DAT                        (0xFFU)                                 ///< Cmd_buf7 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF8 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF8_DAT                        (0xFFU)                                 ///< Cmd_buf8 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF9 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF9_DAT                        (0xFFU)                                 ///< Cmd_buf9 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF10 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF10_DAT                        (0xFFU)                                 ///< Cmd_buf10 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF11 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF11_DAT                        (0xFFU)                                 ///< Cmd_buf11 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF12 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF12_DAT                        (0xFFU)                                 ///< Cmd_buf12 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF13 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF13_DAT                        (0xFFU)                                 ///< Cmd_buf13 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF14 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF14_DAT                        (0xFFU)                                 ///< Cmd_buf14 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_CMD_BUF15 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_CMD_BUF15_DAT                        (0xFFU)                                 ///< Cmd_buf15 byte mapping bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_BUF_CTLL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_BUF_CTLL_DBF_Pos                     (0)
-#define SDIO_BUF_CTLL_DBF                         (0x01U << SDIO_BUF_CTLL_DBF_Pos)        ///< The data cache is full
-#define SDIO_BUF_CTLL_DBE_Pos                     (1)
-#define SDIO_BUF_CTLL_DBE                         (0x01U << SDIO_BUF_CTLL_DBE_Pos)        ///< Data buff is null
-#define SDIO_BUF_CTLL_DBML_Pos                    (2)
-#define SDIO_BUF_CTLL_DBML                        (0xFFU << SDIO_BUF_CTLL_DBML_Pos)       ////< Data buff tags
-#define SDIO_BUF_CTLL_DMAHEN_Pos                  (10)
-#define SDIO_BUF_CTLL_DMAHEN                      (0x01U << SDIO_BUF_CTLL_DMAHEN_Pos)     ///< DMA hardware interface enablement
-#define SDIO_BUF_CTLL_SBAD_Pos                    (11)
-#define SDIO_BUF_CTLL_SBAD                        (0x01U << SDIO_BUF_CTLL_SBAD_Pos)       ///< Sets the access direction of the buff
-#define SDIO_BUF_CTLL_DFIFOSM_Pos                 (12)
-#define SDIO_BUF_CTLL_DFIFOSM                     (0x01U << SDIO_BUF_CTLL_DFIFOSM_Pos)    ///< Data FIFO status signal shielding bit
-#define SDIO_BUF_CTLL_DRM_Pos                     (14)
-#define SDIO_BUF_CTLL_DRM                         (0x01U << SDIO_BUF_CTLL_DRM_Pos)        ///< DMA request masking
-#define SDIO_BUF_CTLL_DBFEN_Pos                   (15)
-#define SDIO_BUF_CTLL_DBFEN                       (0x01U << SDIO_BUF_CTLL_DBFEN_Pos)      ///< Data Buf empty enable bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SDIO_DATA_BUF Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SDIO_DATA_BUF_DB                         (0xFFFFFFFFU)                            ///< Data buffer
-
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h
deleted file mode 100644
index c02b0fae0..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_spi.h
+++ /dev/null
@@ -1,359 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_spi.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_SPI_H
-#define __REG_SPI_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI2_BASE                       (APB1PERIPH_BASE + 0x3800)              ///< Base Address: 0x40003800
-#define SPI1_BASE                       (APB2PERIPH_BASE + 0x3000)              ///< Base Address: 0x400013000
-#define SPI3_BASE                       (APB1PERIPH_BASE + 0x3C00)             ///< Base Address: 0x40003C000
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-#undef USENCOMBINEREGISTER
-#undef USENNEWREGISTER
-#undef USENOLDREGISTER
-#define USENCOMBINEREGISTER
-#ifdef USENCOMBINEREGISTER
-typedef struct {
-    union {
-        __IO u32 TDR;                                                               ///< SPI transmit data register,                    offset: 0x00
-        __IO u32 TXREG;
-    };
-    union {
-        __IO u32 RDR;                                                               ///< SPI receive data register,                     offset: 0x04
-        __IO u32 RXREG;
-    };
-    union {
-        __IO u32 SR;                                                                ///< SPI current state register,                    offset: 0x08
-        __IO u32 CSTAT;
-    };
-    union {
-        __IO u32 ISR;                                                               ///< SPI interruput state register,                 offset: 0x0C
-        __IO u32 INTSTAT;
-    };
-    union {
-        __IO u32 IER;                                                               ///< SPI interruput enable register,                offset: 0x10
-        __IO u32 INTEN;
-    };
-    union {
-        __IO u32 ICR;                                                               ///< SPI interruput control register,               offset: 0x14
-        __IO u32 INTCLR;
-    };
-    union {
-        __IO u32 GCR;                                                               ///< SPI global control register,                   offset: 0x18
-        __IO u32 GCTL;
-    };
-    union {
-        __IO u32 CCR;                                                               ///< SPI common control register,                   offset: 0x1C
-        __IO u32 CCTL;
-    };
-    union {
-        __IO u32 BRR;                                                               ///< SPI baud rate control register,                offset: 0x20
-        __IO u32 SPBRG;
-    };
-    union {
-        __IO u32 RDNR;                                                              ///< SPI receive data number register,              offset: 0x24
-        __IO u32 RXDNR;
-    };
-    union {
-        __IO u32 NSSR;                                                              ///< SPI chip select register,                      offset: 0x28
-        __IO u32 SCSR;
-    };
-    union {
-        __IO u32 ECR;                                                               ///< SPI extand control register,                   offset: 0x2C
-        __IO u32 EXTCTL;
-    };
-    __IO u32 CFGR;                                                              ///< I2S configuration register,                   offset: 0x30
-} SPI_TypeDef;
-#endif
-#ifdef USENNEWREGISTER
-typedef struct {
-    __IO u32 TDR;                                                               ///< SPI transmit data register,                    offset: 0x00
-    __IO u32 RDR;                                                               ///< SPI receive data register,                     offset: 0x04
-    __IO u32 SR;                                                                ///< SPI current state register,                    offset: 0x08
-    __IO u32 ISR;                                                               ///< SPI interruput state register,                 offset: 0x0C
-    __IO u32 IER;                                                               ///< SPI interruput enable register,                offset: 0x10
-    __IO u32 ICR;                                                               ///< SPI interruput control register,               offset: 0x14
-    __IO u32 GCR;                                                               ///< SPI global control register,                   offset: 0x18
-    __IO u32 CCR;                                                               ///< SPI common control register,                   offset: 0x1C
-    __IO u32 BRR;                                                               ///< SPI baud rate control register,                offset: 0x20
-    __IO u32 RDNR;                                                              ///< SPI receive data number register,              offset: 0x24
-    __IO u32 NSSR;                                                              ///< SPI chip select register,                      offset: 0x28
-    __IO u32 ECR;                                                               ///< SPI extand control register,                   offset: 0x2C
-} SPI_TypeDef;
-#endif
-#ifdef USENOLDREGISTER
-typedef struct {
-    __IO u32 TXREG;                                                             ///< SPI transmit data register,                    offset: 0x00
-    __IO u32 RXREG;                                                             ///< SPI receive data register,                     offset: 0x04
-    __IO u32 CSTAT;                                                             ///< SPI current state register,                    offset: 0x08
-    __IO u32 INTSTAT;                                                           ///< SPI interruput state register,                 offset: 0x0C
-    __IO u32 INTEN;                                                             ///< SPI interruput enable register,                offset: 0x10
-    __IO u32 INTCLR;                                                            ///< SPI interruput control register,               offset: 0x14
-    __IO u32 GCTL;                                                              ///< SPI global control register,                   offset: 0x18
-    __IO u32 CCTL;                                                              ///< SPI common control register,                   offset: 0x1C
-    __IO u32 SPBRG;                                                             ///< SPI baud rate control register,                offset: 0x20
-    __IO u32 RXDNR;                                                             ///< SPI receive data number register,              offset: 0x24
-    __IO u32 NSSR;                                                              ///< SPI chip select register,                      offset: 0x28
-    __IO u32 EXTCTL;                                                            ///< SPI extand control register,                   offset: 0x2C
-} SPI_TypeDef;
-#endif
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI2                            ((SPI_TypeDef*) SPI2_BASE)
-#define SPI1                            ((SPI_TypeDef*) SPI1_BASE)
-#define SPI3                            ((SPI_TypeDef*) SPI3_BASE)
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_TDR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_TDR_TXREG_Pos               (0)
-#define SPI_TDR_TXREG                   (0xFFFFFFFFU << SPI_TDR_TXREG_Pos)      ///< Transmit data register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_RDR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_RDR_RXREG_Pos               (0)
-#define SPI_RDR_RXREG                   (0xFFFFFFFFU << SPI_RDR_RXREG_Pos)      ///< Receive data register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_SR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_SR_TXEPT_Pos                (0)
-#define SPI_SR_TXEPT                    (0x01U << SPI_SR_TXEPT_Pos)             ///< Transmitter empty bit
-#define SPI_SR_RXAVL_Pos                (1)
-#define SPI_SR_RXAVL                    (0x01U << SPI_SR_RXAVL_Pos)             ///< Receive available byte data message
-#define SPI_SR_TXFULL_Pos               (2)
-#define SPI_SR_TXFULL                   (0x01U << SPI_SR_TXFULL_Pos)            ///< Transmitter FIFO full status bit
-#define SPI_SR_RXAVL_4BYTE_Pos          (3)
-#define SPI_SR_RXAVL_4BYTE              (0x01U << SPI_SR_RXAVL_4BYTE_Pos)       ///< Receive available 4 byte data message
-#define SPI_SR_TXFADDR_Pos              (4)
-#define SPI_SR_TXFADDR                  (0x0FU << SPI_SR_TXFADDR_Pos)           ///< Transmit FIFO address
-#define SPI_SR_RXFADDR_Pos              (8)
-#define SPI_SR_RXFADDR                  (0x0FU << SPI_SR_RXFADDR_Pos)           ///< Receive FIFO address
-#define SPI_SR_BUSY_Pos                 (12)
-#define SPI_SR_BUSY                     (0x01U << SPI_SR_BUSY_Pos)              ///< Data transfer flag
-#define SPI_SR_CHSIDE_Pos               (13)
-#define SPI_SR_CHSIDE                   (0x01U << SPI_SR_CHSIDE_Pos)            ///< transmission channel     
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_ISR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_ISR_TX_INTF_Pos             (0)
-#define SPI_ISR_TX_INTF                 (0x01U << SPI_ISR_TX_INTF_Pos)          ///<  Transmit FIFO available interrupt flag bit
-#define SPI_ISR_RX_INTF_Pos             (1)
-#define SPI_ISR_RX_INTF                 (0x01U << SPI_ISR_RX_INTF_Pos)          ///<  Receive data available interrupt flag bit
-#define SPI_ISR_UNDERRUN_INTF_Pos       (2)
-#define SPI_ISR_UNDERRUN_INTF           (0x01U << SPI_ISR_UNDERRUN_INTF_Pos)    ///<  SPI underrun interrupt flag bit
-#define SPI_ISR_RXOERR_INTF_Pos         (3)
-#define SPI_ISR_RXOERR_INTF             (0x01U << SPI_ISR_RXOERR_INTF_Pos)      ///<  Receive overrun error interrupt flag bit
-#define SPI_ISR_RXMATCH_INTF_Pos        (4)
-#define SPI_ISR_RXMATCH_INTF            (0x01U << SPI_ISR_RXMATCH_INTF_Pos)     ///<  Receive data match the RXDNR number, the receive process will be completed and generate the interrupt
-#define SPI_ISR_RXFULL_INTF_Pos         (5)
-#define SPI_ISR_RXFULL_INTF             (0x01U << SPI_ISR_RXFULL_INTF_Pos)      ///<  RX FIFO full interrupt flag bit
-#define SPI_ISR_TXEPT_INTF_Pos          (6)
-#define SPI_ISR_TXEPT_INTF              (0x01U << SPI_ISR_TXEPT_INTF_Pos)       ///<  Transmitter empty interrupt flag bit
-#define SPI_ISR_FRE_INTF_Pos            (7)
-#define SPI_ISR_FRE_INTF                (0x01U << SPI_ISR_FRE_INTF_Pos)         ///< I2S frame transmission error flag bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_IER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_IER_TX_IEN_Pos              (0)
-#define SPI_IER_TX_IEN                  (0x01U << SPI_IER_TX_IEN_Pos)           ///<  Transmit FIFO empty interrupt enable bit
-#define SPI_IER_RX_IEN_Pos              (1)
-#define SPI_IER_RX_IEN                  (0x01U << SPI_IER_RX_IEN_Pos)           ///<  Receive FIFO interrupt enable bit
-#define SPI_IER_UNDERRUN_IEN_Pos        (2)
-#define SPI_IER_UNDERRUN_IEN            (0x01U << SPI_IER_UNDERRUN_IEN_Pos)     ///<  Transmitter underrun interrupt enable bit
-#define SPI_IER_RXOERR_IEN_Pos          (3)
-#define SPI_IER_RXOERR_IEN              (0x01U << SPI_IER_RXOERR_IEN_Pos)       ///<  Overrun error interrupt enable bit
-#define SPI_IER_RXMATCH_IEN_Pos         (4)
-#define SPI_IER_RXMATCH_IEN             (0x01U << SPI_IER_RXMATCH_IEN_Pos)      ///<  Receive data complete interrupt enable bit
-#define SPI_IER_RXFULL_IEN_Pos          (5)
-#define SPI_IER_RXFULL_IEN              (0x01U << SPI_IER_RXFULL_IEN_Pos)       ///<  Receive FIFO full interrupt enable bit
-#define SPI_IER_TXEPT_IEN_Pos           (6)
-#define SPI_IER_TXEPT_IEN               (0x01U << SPI_IER_TXEPT_IEN_Pos)        ///<  Transmit empty interrupt enable bit
-#define SPI_IER_FRE_IEN_Pos            (7)
-#define SPI_IER_FRE_IEN                (0x01U << SPI_IER_FRE_IEN_Pos)           ///< I2S frame transmission interrupt enable bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_ICR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_ICR_TX_ICLR_Pos             (0)
-#define SPI_ICR_TX_ICLR                 (0x01U << SPI_ICR_TX_ICLR_Pos)          ///<  Transmitter FIFO empty interrupt clear bit
-#define SPI_ICR_RX_ICLR_Pos             (1)
-#define SPI_ICR_RX_ICLR                 (0x01U << SPI_ICR_RX_ICLR_Pos)          ///<  Receive interrupt clear bit
-#define SPI_ICR_UNDERRUN_ICLR_Pos       (2)
-#define SPI_ICR_UNDERRUN_ICLR           (0x01U << SPI_ICR_UNDERRUN_ICLR_Pos)    ///<  Transmitter underrun interrupt clear bit
-#define SPI_ICR_RXOERR_ICLR_Pos         (3)
-#define SPI_ICR_RXOERR_ICLR             (0x01U << SPI_ICR_RXOERR_ICLR_Pos)      ///<  Overrun error interrupt clear bit
-#define SPI_ICR_RXMATCH_ICLR_Pos        (4)
-#define SPI_ICR_RXMATCH_ICLR            (0x01U << SPI_ICR_RXMATCH_ICLR_Pos)     ///<  Receive completed interrupt clear bit
-#define SPI_ICR_RXFULL_ICLR_Pos         (5)
-#define SPI_ICR_RXFULL_ICLR             (0x01U << SPI_ICR_RXFULL_ICLR_Pos)      ///<  Receiver buffer full interrupt clear bit
-#define SPI_ICR_TXEPT_ICLR_Pos          (6)
-#define SPI_ICR_TXEPT_ICLR              (0x01U << SPI_ICR_TXEPT_ICLR_Pos)       ///<  Transmitter empty interrupt clear bit
-#define SPI_ICR_FRE_ICLR_Pos            (7)
-#define SPI_ICR_FRE_ICLR                (0x01U << SPI_ICR_FRE_ICLR_Pos)         ///< I2S frame transmission interrupt clear bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_GCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_GCR_SPIEN_Pos               (0)
-#define SPI_GCR_SPIEN                   (0x01U << SPI_GCR_SPIEN_Pos)            ///<  SPI select bit
-#define SPI_GCR_IEN_Pos                 (1)
-#define SPI_GCR_IEN                     (0x01U << SPI_GCR_IEN_Pos)              ///<  SPI interrupt enable bit
-#define SPI_GCR_MODE_Pos                (2)
-#define SPI_GCR_MODE                    (0x01U << SPI_GCR_MODE_Pos)             ///<  Master mode bit
-#define SPI_GCR_TXEN_Pos                (3)
-#define SPI_GCR_TXEN                    (0x01U << SPI_GCR_TXEN_Pos)             ///<  Transmit enable bit
-#define SPI_GCR_RXEN_Pos                (4)
-#define SPI_GCR_RXEN                    (0x01U << SPI_GCR_RXEN_Pos)             ///<  Receive enable bit
-
-#define SPI_GCR_RXTLF_Pos               (5)
-#define SPI_GCR_RXTLF                   (0x03U << SPI_GCR_RXTLF_Pos)            ///<  RX FIFO trigger level bit
-#define SPI_GCR_RXTLF_One               (0x00U << SPI_GCR_RXTLF_Pos)            ///<
-#define SPI_GCR_RXTLF_Half              (0x01U << SPI_GCR_RXTLF_Pos)            ///<
-
-#define SPI_GCR_TXTLF_Pos               (7)
-#define SPI_GCR_TXTLF                   (0x03U << SPI_GCR_TXTLF_Pos)            ///<  TX FIFO trigger level bit
-#define SPI_GCR_TXTLF_One               (0x00U << SPI_GCR_TXTLF_Pos)            ///<
-#define SPI_GCR_TXTLF_Half              (0x01U << SPI_GCR_TXTLF_Pos)            ///<
-#define SPI_GCR_DMAEN_Pos               (9)
-#define SPI_GCR_DMAEN                   (0x01U << SPI_GCR_DMAEN_Pos)            ///<  DMA access mode enable
-#define SPI_GCR_NSS_Pos                 (10)
-#define SPI_GCR_NSS                     (0x01U << SPI_GCR_NSS_Pos)              ///<  NSS select signal that from software or hardware
-#define SPI_GCR_DWSEL_Pos               (11)
-#define SPI_GCR_DWSEL                   (0x01U << SPI_GCR_DWSEL_Pos)            ///<  Valid byte or double-word data select signal
-
-#define SPI_GCR_NSSTOG_Pos              (12)
-#define SPI_GCR_NSSTOG                  (0x01U << SPI_GCR_NSSTOG_Pos)           ///<  Slave select toggle
-#define SPI_GCR_PAD_SEL_Pos             (13)
-#define SPI_GCR_PAD_SEL                 (0x1FU << SPI_GCR_PAD_SEL_Pos)          ///< Bus mapping transformation
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_CCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_CCR_CPHA_Pos                (0)
-#define SPI_CCR_CPHA                    (0x01U << SPI_CCR_CPHA_Pos)             ///<  Clock phase select bit
-#define SPI_CCR_CPOL_Pos                (1)
-#define SPI_CCR_CPOL                    (0x01U << SPI_CCR_CPOL_Pos)             ///<  Clock polarity select bit
-#define SPI_CCR_LSBFE_Pos               (2)
-#define SPI_CCR_LSBFE                   (0x01U << SPI_CCR_LSBFE_Pos)            ///<  LSI first enable bit
-#define SPI_CCR_SPILEN_Pos              (3)
-#define SPI_CCR_SPILEN                  (0x01U << SPI_CCR_SPILEN_Pos)           ///<  SPI character length bit
-#define SPI_CCR_RXEDGE_Pos              (4)
-#define SPI_CCR_RXEDGE                  (0x01U << SPI_CCR_RXEDGE_Pos)           ///<  Receive data edge select
-#define SPI_CCR_TXEDGE_Pos              (5)
-#define SPI_CCR_TXEDGE                  (0x01U << SPI_CCR_TXEDGE_Pos)           ///<  Transmit data edge select
-
-#define SPI_CCR_CPHASEL_Pos             (6)
-#define SPI_CCR_CPHASEL                 (0x01U << SPI_CCR_CPHASEL)              ///<  CPHA polarity select
-
-#define SPI_CCR_HISPD_Pos               (7)
-#define SPI_CCR_HISPD                   (0x01U << SPI_CCR_HISPD)                ///<  High speed slave mode
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_BRR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_BRR_DIVF_Pos                (0)
-#define SPI_BRR_DIVF                    (0xFFFFU << SPI_BRR_DIVF_Pos)       ///<  SPI baud rate control register for baud rate
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_RDNR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_RDNR_RDN_Pos                (0)
-#define SPI_RDNR_RDN                    (0xFFFFU << SPI_RDNR_RDN_Pos)       ///<  The register is used to hold a count of to be received bytes in next receive process
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_NSSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_NSSR_NSS_Pos                (0)
-#define SPI_NSSR_NSS                    (0xFFU << SPI_NSSR_NSS_Pos)             ///<  Chip select output signal in Master mode
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SPI_ECR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define SPI_ECR_EXTLEN_Pos              (0)
-#define SPI_ECR_EXTLEN                  (0x1FU << SPI_ECR_EXTLEN_Pos)           ///<  control SPI data length
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief I2S_CFGR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define I2SCFGR_CLEAR_Mask              ((u32)0xFE00F388)
-#define I2S_CFGR_CHLEN_Pos              (0)
-#define I2S_CFGR_CHLEN                  (0x01U << I2S_CFGR_CHLEN_Pos)             ///<  Vocal tract length
-#define I2S_CFGR_DATLEN_Pos             (1)
-#define I2S_CFGR_DATLEN_16              (0x00U << I2S_CFGR_DATLEN_Pos)            ///<  Audio data width 16 
-#define I2S_CFGR_DATLEN_24              (0x01U << I2S_CFGR_DATLEN_Pos)            ///<  Audio data width 24 
-#define I2S_CFGR_DATLEN_32              (0x02U << I2S_CFGR_DATLEN_Pos)            ///<  Audio data width 32 
-
-#define I2S_CFGR_I2SSTD_Pos             (4)
-#define I2S_CFGR_I2SSTD_PCM             (0x00U << I2S_CFGR_I2SSTD_Pos)            ///<  I2S selection PCM standard
-#define I2S_CFGR_I2SSTD_MSB_R           (0x01U << I2S_CFGR_I2SSTD_Pos)            ///<  I2S selection Right alignment (MSB) standard
-#define I2S_CFGR_I2SSTD_MSB_L           (0x02U << I2S_CFGR_I2SSTD_Pos)            ///<  I2S selection Left aligned (MSB) standard
-#define I2S_CFGR_I2SSTD_Philips         (0x03U << I2S_CFGR_I2SSTD_Pos)            ///<  I2S selection Philips standard
-
-#define I2S_CFGR_PCMSYNC_Pos            (6)
-#define I2S_CFGR_PCMSYNC                (0x01U << I2S_CFGR_PCMSYNC_Pos)           ///<  PCM frame synchronization mode
-#define I2S_CFGR_SPI_I2S_Pos            (10)
-#define I2S_CFGR_SPI_I2S                (0x01U << I2S_CFGR_SPI_I2S_Pos)           ///<  SPI/I2S module function selection
-#define I2S_CFGR_MCKOE_Pos              (11)
-#define I2S_CFGR_MCKOE                  (0x01U << I2S_CFGR_MCKOE_Pos)             ///<  I2S master clock output enable
-#define I2S_CFGR_I2SDIV_Pos             (16)
-#define I2S_CFGR_I2SDIV                 (0x1FFU << I2S_CFGR_I2SDIV_Pos)           ///<  The frequency division
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h
deleted file mode 100644
index 677250dc8..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_syscfg.h
+++ /dev/null
@@ -1,299 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_syscfg.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_SYSCFG_H
-#define __REG_SYSCFG_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-
-#define SYSCFG_BASE                     (APB2PERIPH_BASE + 0x0000)              ///< Base Address: 0x40010000
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief SysTem Configuration Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    union {
-        __IO u32 CFGR;                                                          ///< SYSCFG configuration register                  offset: 0x00
-        __IO u32 CFGR1;
-    };
-    __IO u32 RESERVED0x04;                                                      ///< RESERVED register                              offset: 0x04
-    __IO u32 EXTICR[4];                                                         ///< SYSCFG configuration register                  offset: 0x08-0x14
-    __IO u32 CFGR2;                                                             ///< SYSCFG configuration2 register                 offset: 0x18
-    __IO u32 PDETCSR;                                                           ///< SYSCFG Power Detect configuration stautus reg  offset: 0x1C
-    __IO u32 VOSDLY;                                                            ///< SYSCFG VOSDLY Counter register                 offset: 0x20
-} SYSCFG_TypeDef;
-
-
-#define SYSCFG                             ((SYSCFG_TypeDef *) SYSCFG_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-///@brief System Configuration (SYSCFG)
-////////////////////////////////////////////////////////////////////////////////
-
-/// @brief SYSCFG_CFGR Register Bit definition
-#define SYSCFG_CFGR_MEM_MODE_Pos           (0)
-#define SYSCFG_CFGR_MEM_MODE               ((u32)0x00000003)               ///< SYSCFG_Memory Remap Config
-#define SYSCFG_CFGR_MEM_MODE_0             ((u32)0x00000001)               ///< SYSCFG_Memory Remap Config Bit 0
-#define SYSCFG_CFGR_MEM_MODE_1             ((u32)0x00000002)               ///< SYSCFG_Memory Remap Config Bit 1
-///
-
-#define SYSCFG_CFGR_FSMC_SYNC_EN_Pos    (27)
-#define SYSCFG_CFGR_FSMC_SYNC_EN        (0x01U  << SYSCFG_CFGR_FSMC_SYNC_EN_Pos)///< FSMC SYNC Enable
-#define SYSCFG_CFGR_FSMC_AF_ADDR_Pos    (28)
-#define SYSCFG_CFGR_FSMC_AF_ADDR        (0x01U  << SYSCFG_CFGR_FSMC_AF_ADDR_Pos)///< FSMC Databus AF Address
-#define SYSCFG_CFGR_FSMC_MODE_Pos       (29)
-#define SYSCFG_CFGR_FSMC_MODE           ((u32)0x03<<SYSCFG_CFGR_FSMC_MODE_Pos)  ///< FSMC Interface Mode Config
-#define SYSCFG_CFGR_FSMC_MODE0          ((u32)0x00<<SYSCFG_CFGR_FSMC_MODE_Pos)  ///< FSMC Mode Config Mode 0
-#define SYSCFG_CFGR_FSMC_MODE1          ((u32)0x01<<SYSCFG_CFGR_FSMC_MODE_Pos)  ///< FSMC Mode Config Mode 1
-
-
-/// @brief SYSCFG_EXTICR1 Register Bit definition
-#define SYSCFG_EXTICR1_EXTI0               ((u16)0x000F)                   ///< EXTI 0 configuration
-#define SYSCFG_EXTICR1_EXTI1               ((u16)0x00F0)                   ///< EXTI 1 configuration
-#define SYSCFG_EXTICR1_EXTI2               ((u16)0x0F00)                   ///< EXTI 2 configuration
-#define SYSCFG_EXTICR1_EXTI3               ((u16)0xF000)                   ///< EXTI 3 configuration
-
-///  @brief  EXTI0 configuration
-#define SYSCFG_EXTICR1_EXTI0_PA            ((u16)0x0000)                   ///< PA[0] pin
-#define SYSCFG_EXTICR1_EXTI0_PB            ((u16)0x0001)                   ///< PB[0] pin
-#define SYSCFG_EXTICR1_EXTI0_PC            ((u16)0x0002)                   ///< PC[0] pin
-#define SYSCFG_EXTICR1_EXTI0_PD            ((u16)0x0003)                   ///< PD[0] pin
-
-///  @brief  EXTI1 configuration
-#define SYSCFG_EXTICR1_EXTI1_PA            ((u16)0x0000)                   ///< PA[1] pin
-#define SYSCFG_EXTICR1_EXTI1_PB            ((u16)0x0010)                   ///< PB[1] pin
-#define SYSCFG_EXTICR1_EXTI1_PC            ((u16)0x0020)                   ///< PC[1] pin
-#define SYSCFG_EXTICR1_EXTI1_PD            ((u16)0x0030)                   ///< PD[1] pin
-
-///  @brief  EXTI2 configuration
-#define SYSCFG_EXTICR1_EXTI2_PA            ((u16)0x0000)                   ///< PA[2] pin
-#define SYSCFG_EXTICR1_EXTI2_PB            ((u16)0x0100)                   ///< PB[2] pin
-#define SYSCFG_EXTICR1_EXTI2_PC            ((u16)0x0200)                   ///< PC[2] pin
-#define SYSCFG_EXTICR1_EXTI2_PD            ((u16)0x0300)                   ///< PD[2] pin
-
-
-///  @brief  EXTI3 configuration
-#define SYSCFG_EXTICR1_EXTI3_PA            ((u16)0x0000)                   ///< PA[3] pin
-#define SYSCFG_EXTICR1_EXTI3_PB            ((u16)0x1000)                   ///< PB[3] pin
-#define SYSCFG_EXTICR1_EXTI3_PC            ((u16)0x2000)                   ///< PC[3] pin
-#define SYSCFG_EXTICR1_EXTI3_PD            ((u16)0x3000)                   ///< PD[3] pin
-
-
-/// @brief SYSCFG_EXTICR2 Register Bit definition
-#define SYSCFG_EXTICR2_EXTI4               ((u16)0x000F)                   ///< EXTI 4 configuration
-#define SYSCFG_EXTICR2_EXTI5               ((u16)0x00F0)                   ///< EXTI 5 configuration
-#define SYSCFG_EXTICR2_EXTI6               ((u16)0x0F00)                   ///< EXTI 6 configuration
-#define SYSCFG_EXTICR2_EXTI7               ((u16)0xF000)                   ///< EXTI 7 configuration
-
-/// @brief  EXTI4 configuration
-#define SYSCFG_EXTICR2_EXTI4_PA            ((u16)0x0000)                   ///< PA[4] pin
-#define SYSCFG_EXTICR2_EXTI4_PB            ((u16)0x0001)                   ///< PB[4] pin
-#define SYSCFG_EXTICR2_EXTI4_PC            ((u16)0x0002)                   ///< PC[4] pin
-#define SYSCFG_EXTICR2_EXTI4_PD            ((u16)0x0003)                   ///< PD[4] pin
-
-
-/// @brief  EXTI5 configuration
-#define SYSCFG_EXTICR2_EXTI5_PA            ((u16)0x0000)                   ///< PA[5] pin
-#define SYSCFG_EXTICR2_EXTI5_PB            ((u16)0x0010)                   ///< PB[5] pin
-#define SYSCFG_EXTICR2_EXTI5_PC            ((u16)0x0020)                   ///< PC[5] pin
-#define SYSCFG_EXTICR2_EXTI5_PD            ((u16)0x0030)                   ///< PD[5] pin
-
-/// @brief  EXTI6 configuration
-
-#define SYSCFG_EXTICR2_EXTI6_PA            ((u16)0x0000)                   ///< PA[6] pin
-#define SYSCFG_EXTICR2_EXTI6_PB            ((u16)0x0100)                   ///< PB[6] pin
-#define SYSCFG_EXTICR2_EXTI6_PC            ((u16)0x0200)                   ///< PC[6] pin
-#define SYSCFG_EXTICR2_EXTI6_PD            ((u16)0x0300)                   ///< PD[6] pin
-
-
-/// @brief  EXTI7 configuration
-#define SYSCFG_EXTICR2_EXTI7_PA            ((u16)0x0000)                   ///< PA[7] pin
-#define SYSCFG_EXTICR2_EXTI7_PB            ((u16)0x1000)                   ///< PB[7] pin
-#define SYSCFG_EXTICR2_EXTI7_PC            ((u16)0x2000)                   ///< PC[7] pin
-#define SYSCFG_EXTICR2_EXTI7_PD            ((u16)0x3000)                   ///< PD[7] pin
-
-/// @brief SYSCFG_EXTICR3 Register Bit definition
-#define SYSCFG_EXTICR3_EXTI8               ((u16)0x000F)                   ///< EXTI 8 configuration
-#define SYSCFG_EXTICR3_EXTI9               ((u16)0x00F0)                   ///< EXTI 9 configuration
-#define SYSCFG_EXTICR3_EXTI10              ((u16)0x0F00)                   ///< EXTI 10 configuration
-#define SYSCFG_EXTICR3_EXTI11              ((u16)0xF000)                   ///< EXTI 11 configuration
-
-///  @brief  EXTI8 configuration
-#define SYSCFG_EXTICR3_EXTI8_PA            ((u16)0x0000)                   ///< PA[8] pin
-#define SYSCFG_EXTICR3_EXTI8_PB            ((u16)0x0001)                   ///< PB[8] pin
-#define SYSCFG_EXTICR3_EXTI8_PC            ((u16)0x0002)                   ///< PC[8] pin
-#define SYSCFG_EXTICR3_EXTI8_PD            ((u16)0x0003)                   ///< PD[8] pin
-
-
-///  @brief  EXTI9 configuration
-
-#define SYSCFG_EXTICR3_EXTI9_PA            ((u16)0x0000)                   ///< PA[9] pin
-#define SYSCFG_EXTICR3_EXTI9_PB            ((u16)0x0010)                   ///< PB[9] pin
-#define SYSCFG_EXTICR3_EXTI9_PC            ((u16)0x0020)                   ///< PC[9] pin
-#define SYSCFG_EXTICR3_EXTI9_PD            ((u16)0x0030)                   ///< PD[9] pin
-
-///  @brief  EXTI10 configuration
-#define SYSCFG_EXTICR3_EXTI10_PA           ((u16)0x0000)                   ///< PA[10] pin
-#define SYSCFG_EXTICR3_EXTI10_PB           ((u16)0x0100)                   ///< PB[10] pin
-#define SYSCFG_EXTICR3_EXTI10_PC           ((u16)0x0200)                   ///< PC[10] pin
-#define SYSCFG_EXTICR3_EXTI10_PD           ((u16)0x0300)                   ///< PE[10] pin
-
-///  @brief  EXTI11 configuration
-#define SYSCFG_EXTICR3_EXTI11_PA           ((u16)0x0000)                   ///< PA[11] pin
-#define SYSCFG_EXTICR3_EXTI11_PB           ((u16)0x1000)                   ///< PB[11] pin
-#define SYSCFG_EXTICR3_EXTI11_PC           ((u16)0x2000)                   ///< PC[11] pin
-#define SYSCFG_EXTICR3_EXTI11_PD           ((u16)0x3000)                   ///< PD[11] pin
-
-
-/// @brief SYSCFG_EXTICR4 Register Bit definition
-#define SYSCFG_EXTICR4_EXTI12               ((u16)0x000F)                  ///< EXTI 12 configuration
-#define SYSCFG_EXTICR4_EXTI13               ((u16)0x00F0)                  ///< EXTI 13 configuration
-#define SYSCFG_EXTICR4_EXTI14               ((u16)0x0F00)                  ///< EXTI 14 configuration
-#define SYSCFG_EXTICR4_EXTI15               ((u16)0xF000)                  ///< EXTI 15 configuration
-
-#define SYSCFG_EXTICR4_EXTI12_PA            ((u16)0x0000)                  ///< PA[12] pin for EXTI12
-#define SYSCFG_EXTICR4_EXTI12_PB            ((u16)0x0001)                  ///< PB[12] pin for EXTI12
-#define SYSCFG_EXTICR4_EXTI12_PC            ((u16)0x0002)                  ///< PC[12] pin for EXTI12
-#define SYSCFG_EXTICR4_EXTI12_PD            ((u16)0x0003)                  ///< PD[12] pin for EXTI12
-
-#define SYSCFG_EXTICR4_EXTI13_PA            ((u16)0x0000)                  ///< PA[13] pin for EXTI13
-#define SYSCFG_EXTICR4_EXTI13_PB            ((u16)0x0010)                  ///< PB[13] pin for EXTI13
-#define SYSCFG_EXTICR4_EXTI13_PC            ((u16)0x0020)                  ///< PC[13] pin for EXTI13
-#define SYSCFG_EXTICR4_EXTI13_PD            ((u16)0x0030)                  ///< PD[13] pin for EXTI13
-
-#define SYSCFG_EXTICR4_EXTI14_PA            ((u16)0x0000)                  ///< PA[14] pin for EXTI14
-#define SYSCFG_EXTICR4_EXTI14_PB            ((u16)0x0100)                  ///< PB[14] pin for EXTI14
-#define SYSCFG_EXTICR4_EXTI14_PC            ((u16)0x0200)                  ///< PC[14] pin for EXTI14
-#define SYSCFG_EXTICR4_EXTI14_PD            ((u16)0x0300)                  ///< PD[14] pin for EXTI14
-
-#define SYSCFG_EXTICR4_EXTI15_PA            ((u16)0x0000)                  ///< PA[15] pin for EXTI15
-#define SYSCFG_EXTICR4_EXTI15_PB            ((u16)0x1000)                  ///< PB[15] pin for EXTI15
-#define SYSCFG_EXTICR4_EXTI15_PC            ((u16)0x2000)                  ///< PC[15] pin for EXTI15
-#define SYSCFG_EXTICR4_EXTI15_PD            ((u16)0x3000)                  ///< PD[15] pin for EXTI15
-
-
-
-
-#define SYSCFG_CFGR2_I2C1_MODE_SEL_Pos             (16)
-#define SYSCFG_CFGR2_I2C1_MODE_SEL                 (0x01U  << SYSCFG_CFGR2_I2C1_MODE_SEL_Pos)                   ///< I2C1 Enable PushPull mode
-#define SYSCFG_CFGR2_I2C2_MODE_SEL_Pos             (17)
-#define SYSCFG_CFGR2_I2C2_MODE_SEL                 (0x01U  << SYSCFG_CFGR2_I2C2_MODE_SEL_Pos)                   ///< I2C2 Enable PushPull mode
-
-#define SYSCFG_CFGR2_MII_RMII_MODE_SEL_Pos         (20)
-#define SYSCFG_CFGR2_MII_RMII_MODE_SEL             (0x01U  << SYSCFG_CFGR2_MII_RMII_MODE_SEL_Pos)               ///< MII_RMII mode
-#define SYSCFG_CFGR2_MAC_SPEED_SEL_Pos             (21)
-#define SYSCFG_CFGR2_MAC_SPEED_SEL                 (0x01U  << SYSCFG_CFGR2_MAC_SPEED_SEL_Pos)                   ///< MAC_SPEED mode
-
-
-#define SYSCFG_PDETCSR_PVDE_Pos             (0)
-#define SYSCFG_PDETCSR_PVDE                 (0x01U  << SYSCFG_PDETCSR_PVDE_Pos)                     ///< Power Voltage Detector Enable
-
-#define SYSCFG_PDETCSR_PLS_Pos              (1)
-#define SYSCFG_PDETCSR_PLS                  (0x0FU  << SYSCFG_PDETCSR_PLS_Pos)
-
-#define SYSCFG_PDETCSR_PLS_1V7              (0x00U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 1.7V
-#define SYSCFG_PDETCSR_PLS_2V0              (0x01U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 2.0V
-#define SYSCFG_PDETCSR_PLS_2V3              (0x02U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 2.3V
-#define SYSCFG_PDETCSR_PLS_2V6              (0x03U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 2.6V
-#define SYSCFG_PDETCSR_PLS_2V9              (0x04U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 2.9V
-#define SYSCFG_PDETCSR_PLS_3V2              (0x05U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 3.2V
-#define SYSCFG_PDETCSR_PLS_3V5              (0x06U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 3.5V
-#define SYSCFG_PDETCSR_PLS_3V8              (0x07U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 3.8V
-#define SYSCFG_PDETCSR_PLS_4V1              (0x08U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 4.1V
-#define SYSCFG_PDETCSR_PLS_4V4              (0x09U  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 4.4V
-#define SYSCFG_PDETCSR_PLS_4V7              (0x0AU  << SYSCFG_PDETCSR_PLS_Pos)              ///< PVD level 4.7V
-
-// #define PWR_CR_PLS_Pos                      SYSCFG_PDETCSR_PLS_Pos
-// #define PWR_CR_PLS                          SYSCFG_PDETCSR_PLS
-// #define PWR_CR_PLS_1V8                      SYSCFG_PDETCSR_PLS_1V7                          ///< PVD level 1.8V
-// #define PWR_CR_PLS_2V1                      SYSCFG_PDETCSR_PLS_2V0                          ///< PVD level 2.1V
-// #define PWR_CR_PLS_2V4                      SYSCFG_PDETCSR_PLS_2V3                          ///< PVD level 2.4V
-// #define PWR_CR_PLS_2V7                      SYSCFG_PDETCSR_PLS_2V6                          ///< PVD level 2.7V
-// #define PWR_CR_PLS_3V0                      SYSCFG_PDETCSR_PLS_2V9                          ///< PVD level 3.0V
-// #define PWR_CR_PLS_3V3                      SYSCFG_PDETCSR_PLS_3V2                          ///< PVD level 3.3V
-// #define PWR_CR_PLS_3V6                      SYSCFG_PDETCSR_PLS_3V5                          ///< PVD level 3.6V
-// #define PWR_CR_PLS_3V9                      SYSCFG_PDETCSR_PLS_3V8                          ///< PVD level 3.9V
-// #define PWR_CR_PLS_4V2                      SYSCFG_PDETCSR_PLS_4V1                          ///< PVD level 4.2V
-// #define PWR_CR_PLS_4V5                      SYSCFG_PDETCSR_PLS_4V4                          ///< PVD level 4.5V
-// #define PWR_CR_PLS_4V8                      SYSCFG_PDETCSR_PLS_4V7                          ///< PVD level 4.8V
-
-#define SYSCFG_PDETCSR_PVDO_Pos             (5)
-#define SYSCFG_PDETCSR_PVDO                 (0x01U  << SYSCFG_PDETCSR_PVDO_Pos)             ///< PVD Output
-// #define PWR_CSR_PVDO_Pos                    SYSCFG_PDETCSR_PVDO_Pos
-// #define PWR_CSR_PVDO                        SYSCFG_PDETCSR_PVDO                             ///< PVD Output
-
-#define SYSCFG_PDETCSR_VDTO_Pos             (6)
-#define SYSCFG_PDETCSR_VDTO                 (0x01U  << SYSCFG_PDETCSR_VDTO_Pos)             ///< VDT Output Enable
-
-#define SYSCFG_PDETCSR_VDTE_Pos             (8)
-#define SYSCFG_PDETCSR_VDTE                 (0x01U  << SYSCFG_PDETCSR_VDTE_Pos)             ///< VDT Output
-
-#define SYSCFG_PDETCSR_VDTLS_Pos            (9)
-#define SYSCFG_PDETCSR_VDTLS                (0x0FU  << SYSCFG_PDETCSR_VDTLS_Pos)
-#define SYSCFG_PDETCSR_VDTLS_0V9            (0x00U  << SYSCFG_PDETCSR_VDTLS_Pos)            ///< VDT level 0.9V
-#define SYSCFG_PDETCSR_VDTLS_1V0            (0x01U  << SYSCFG_PDETCSR_VDTLS_Pos)            ///< VDT level 1.0V
-#define SYSCFG_PDETCSR_VDTLS_1V1            (0x02U  << SYSCFG_PDETCSR_VDTLS_Pos)            ///< VDT level 1.1V
-#define SYSCFG_PDETCSR_VDTLS_1V2            (0x03U  << SYSCFG_PDETCSR_VDTLS_Pos)            ///< VDT level 1.2V
-
-#define SYSCFG_PDETCSR_VBATDIV3EN_Pos       (11)
-#define SYSCFG_PDETCSR_VBATDIV3EN           (0x01U  << SYSCFG_PDETCSR_VBATDIV3EN_Pos)       ///< VBATDIV3 Enable
-
-#define SYSCFG_VOSDLY_CNT_Pos               (0)
-#define SYSCFG_VOSDLY_CNT                   (0x03FFU << SYSCFG_VOSDLY_CNT_Pos)              ///< SYSCFG VOSDLY CNT
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h
deleted file mode 100644
index b9022e2ff..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_tim.h
+++ /dev/null
@@ -1,681 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_tim.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_TIM_H
-#define __REG_TIM_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM1_BASE                       (APB2PERIPH_BASE + 0x2C00)              ///< Base Address: 0x40012C00
-#define TIM2_BASE                       (APB1PERIPH_BASE + 0x0000)              ///< Base Address: 0x40000000
-#define TIM3_BASE                       (APB1PERIPH_BASE + 0x0400)              ///< Base Address: 0x40000400
-#define TIM4_BASE                       (APB1PERIPH_BASE + 0x0800)              ///< Base Address: 0x40000800
-
-#define TIM5_BASE                       (APB1PERIPH_BASE + 0x0C00)              ///< Base Address: 0x40000C00
-#define TIM6_BASE                       (APB1PERIPH_BASE + 0x1000)              ///< Base Address: 0x40001000
-#define TIM7_BASE                       (APB1PERIPH_BASE + 0x1400)              ///< Base Address: 0x40001400
-#define TIM8_BASE                       (APB2PERIPH_BASE + 0x3400)              ///< Base Address: 0x40013400
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief Timer Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 CR1;                                                               ///< TIM control register 1,                        offset: 0x00
-    __IO u32 CR2;                                                               ///< TIM control register 2,                        offset: 0x04
-    __IO u32 SMCR;                                                              ///< TIM slave Mode Control register,               offset: 0x08
-    __IO u32 DIER;                                                              ///< TIM DMA/interrupt enable register,             offset: 0x0C
-    __IO u32 SR;                                                                ///< TIM status register,                           offset: 0x10
-    __IO u32 EGR;                                                               ///< TIM event generation register,                 offset: 0x14
-    __IO u32 CCMR1;                                                             ///< TIM capture/compare mode register 1,           offset: 0x18
-    __IO u32 CCMR2;                                                             ///< TIM capture/compare mode register 2,           offset: 0x1C
-    __IO u32 CCER;                                                              ///< TIM capture/compare enable register,           offset: 0x20
-    __IO u32 CNT;                                                               ///< TIM counter register,                          offset: 0x24
-    __IO u32 PSC;                                                               ///< TIM prescaler register,                        offset: 0x28
-    __IO u32 ARR;                                                               ///< TIM auto-reload register,                      offset: 0x2C
-    __IO u32 RCR;                                                               ///< TIM repetition counter register,               offset: 0x30
-    __IO u32 CCR1;                                                              ///< TIM capture/compare register 1,                offset: 0x34
-    __IO u32 CCR2;                                                              ///< TIM capture/compare register 2,                offset: 0x38
-    __IO u32 CCR3;                                                              ///< TIM capture/compare register 3,                offset: 0x3C
-    __IO u32 CCR4;                                                              ///< TIM capture/compare register 4,                offset: 0x40
-    __IO u32 BDTR;                                                              ///< TIM break and dead-time register,              offset: 0x44
-    __IO u32 DCR;                                                               ///< TIM DMA control register,                      offset: 0x48
-    __IO u32 DMAR;                                                              ///< TIM DMA address for full transfer register,    offset: 0x4C
-    __IO u32 OR;                                                                ///< Option register,                               offset: 0x50
-    __IO u32 CCMR3;                                                             ///< TIM capture/compare mode register 3,           offset: 0x54
-    __IO u32 CCR5;                                                              ///< TIM capture/compare register 5,                offset: 0x58
-    __IO u32 PDER;                                                              ///< PWM Shift repeat enable register,                offset: 0x5C
-    __IO u32 CCR1FALL;                                                          ///< PWM shift count CCR1 register,                 offset: 0x60
-    __IO u32 CCR2FALL;                                                          ///< PWM shift count CCR2 register,                 offset: 0x64
-    __IO u32 CCR3FALL;                                                          ///< PWM shift count CCR3 register,                 offset: 0x68
-    __IO u32 CCR4FALL;                                                          ///< PWM shift count CCR4 register,                 offset: 0x6c
-    __IO u32 CCR5FALL;                                                          ///< PWM shift count CCR5 register,                 offset: 0x70
-} TIM_TypeDef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM1                            ((TIM_TypeDef*) TIM1_BASE)
-#define TIM2                            ((TIM_TypeDef*) TIM2_BASE)
-#define TIM3                            ((TIM_TypeDef*) TIM3_BASE)
-#define TIM4                            ((TIM_TypeDef*) TIM4_BASE)
-
-#define TIM5                            ((TIM_TypeDef*) TIM5_BASE)
-#define TIM6                            ((TIM_TypeDef*) TIM6_BASE)
-#define TIM7                            ((TIM_TypeDef*) TIM7_BASE)
-
-#define TIM8                            ((TIM_TypeDef*) TIM8_BASE)
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CR1 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CR1_CEN_Pos                 (0)
-#define TIM_CR1_CEN                     (0x01U << TIM_CR1_CEN_Pos)              ///< Counter enable
-#define TIM_CR1_UDIS_Pos                (1)
-#define TIM_CR1_UDIS                    (0x01U << TIM_CR1_UDIS_Pos)             ///< Update disable
-#define TIM_CR1_URS_Pos                 (2)
-#define TIM_CR1_URS                     (0x01U << TIM_CR1_URS_Pos)              ///< Update request source
-#define TIM_CR1_OPM_Pos                 (3)
-#define TIM_CR1_OPM                     (0x01U << TIM_CR1_OPM_Pos)              ///< One pulse mode
-#define TIM_CR1_DIR_Pos                 (4)
-#define TIM_CR1_DIR                     (0x01U << TIM_CR1_DIR_Pos)              ///< Direction
-#define TIM_CR1_CMS_Pos                 (5)
-#define TIM_CR1_CMS                     (0x03U << TIM_CR1_CMS_Pos)              ///< CMS[1:0] bits (Center-aligned mode selection)
-#define TIM_CR1_CMS_EDGEALIGNED         (0x00U << TIM_CR1_CMS_Pos)              ///< Edge-aligned mode
-#define TIM_CR1_CMS_CENTERALIGNED1      (0x01U << TIM_CR1_CMS_Pos)              ///< Center-aligned mode 1
-#define TIM_CR1_CMS_CENTERALIGNED2      (0x02U << TIM_CR1_CMS_Pos)              ///< Center-aligned mode 2
-#define TIM_CR1_CMS_CENTERALIGNED3      (0x03U << TIM_CR1_CMS_Pos)              ///< Center-aligned mode 3
-#define TIM_CR1_ARPEN_Pos               (7)
-#define TIM_CR1_ARPEN                   (0x01U << TIM_CR1_ARPEN_Pos)            ///< Auto-reload preload enable
-#define TIM_CR1_CKD_Pos                 (8)
-#define TIM_CR1_CKD                     (0x03U << TIM_CR1_CKD_Pos)              ///< CKD[1:0] bits (clock division)
-#define TIM_CR1_CKD_DIV1                (0x00U << TIM_CR1_CKD_Pos)              ///< Divided by 1
-#define TIM_CR1_CKD_DIV2                (0x01U << TIM_CR1_CKD_Pos)              ///< Divided by 2
-#define TIM_CR1_CKD_DIV4                (0x02U << TIM_CR1_CKD_Pos)              ///< Divided by 4
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CR2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CR2_CCPC_Pos                (0)
-#define TIM_CR2_CCPC                    (0x01U << TIM_CR2_CCPC_Pos)             ///< Capture/Compare Preloaded Control
-#define TIM_CR2_CCUS_Pos                (2)
-#define TIM_CR2_CCUS                    (0x01U << TIM_CR2_CCUS_Pos)             ///< Capture/Compare Control Update Selection
-#define TIM_CR2_CCDS_Pos                (3)
-#define TIM_CR2_CCDS                    (0x01U << TIM_CR2_CCDS_Pos)             ///< Capture/Compare DMA Selection
-#define TIM_CR2_MMS_Pos                 (4)
-#define TIM_CR2_MMS                     (0x07U << TIM_CR2_MMS_Pos)              ///< MMS[2:0] bits (Master Mode Selection)
-#define TIM_CR2_MMS_RESET               (0x00U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: Reset
-#define TIM_CR2_MMS_ENABLE              (0x01U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: Enable
-#define TIM_CR2_MMS_UPDATE              (0x02U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: Update
-#define TIM_CR2_MMS_OC1                 (0x03U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: OC1
-#define TIM_CR2_MMS_OC1REF              (0x04U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: OC1Ref
-#define TIM_CR2_MMS_OC2REF              (0x05U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: OC2Ref
-#define TIM_CR2_MMS_OC3REF              (0x06U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: OC3Ref
-#define TIM_CR2_MMS_OC4REF              (0x07U << TIM_CR2_MMS_Pos)              ///< Master Mode Select: OC4Ref
-#define TIM_CR2_TI1S_Pos                (7)
-#define TIM_CR2_TI1S                    (0x01U << TIM_CR2_TI1S_Pos)             ///< TI1 Selection
-#define TIM_CR2_OIS1_Pos                (8)
-#define TIM_CR2_OIS1                    (0x01U << TIM_CR2_OIS1_Pos)             ///< Output Idle state 1 (OC1 output)
-#define TIM_CR2_OIS1N_Pos               (9)
-#define TIM_CR2_OIS1N                   (0x01U << TIM_CR2_OIS1N_Pos)            ///< Output Idle state 1 (OC1N output)
-#define TIM_CR2_OIS2_Pos                (10)
-#define TIM_CR2_OIS2                    (0x01U << TIM_CR2_OIS2_Pos)             ///< Output Idle state 2 (OC2 output)
-#define TIM_CR2_OIS2N_Pos               (11)
-#define TIM_CR2_OIS2N                   (0x01U << TIM_CR2_OIS2N_Pos)            ///< Output Idle state 2 (OC2N output)
-#define TIM_CR2_OIS3_Pos                (12)
-#define TIM_CR2_OIS3                    (0x01U << TIM_CR2_OIS3_Pos)             ///< Output Idle state 3 (OC3 output)
-#define TIM_CR2_OIS3N_Pos               (13)
-#define TIM_CR2_OIS3N                   (0x01U << TIM_CR2_OIS3N_Pos)            ///< Output Idle state 3 (OC3N output)
-#define TIM_CR2_OIS4_Pos                (14)
-#define TIM_CR2_OIS4                    (0x01U << TIM_CR2_OIS4_Pos)             ///< Output Idle state 4 (OC4 output)
-
-
-#define TIM_CR2_OIS5_Pos                (16)
-#define TIM_CR2_OIS5                    (0x01U << TIM_CR2_OIS5_Pos)             ///< Output Idle state 5 (OC5 output)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_SMCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_SMCR_SMS_Pos                (0)
-#define TIM_SMCR_SMS                    (0x07U << TIM_SMCR_SMS_Pos)             ///< SMS[2:0] bits (Slave mode selection)
-#define TIM_SMCR_SMS_OFF                (0x00U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: OFF
-#define TIM_SMCR_SMS_ENCODER1           (0x01U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Encoder1
-#define TIM_SMCR_SMS_ENCODER2           (0x02U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Encoder2
-#define TIM_SMCR_SMS_ENCODER3           (0x03U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Encoder3
-#define TIM_SMCR_SMS_RESET              (0x04U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Reset
-#define TIM_SMCR_SMS_GATED              (0x05U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Gated
-#define TIM_SMCR_SMS_TRIGGER            (0x06U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: Trigger
-#define TIM_SMCR_SMS_EXTERNAL1          (0x07U << TIM_SMCR_SMS_Pos)             ///< Slave Mode select: External1
-
-#define TIM_SMCR_OCCS_Pos               (3)
-#define TIM_SMCR_OCCS                   (0x01U << TIM_SMCR_OCCS_Pos)            ///< Output compare clear selection
-
-#define TIM_SMCR_TS_Pos                 (4)
-#define TIM_SMCR_TS                     (0x07U << TIM_SMCR_TS_Pos)              ///< TS[2:0] bits (Trigger selection)
-#define TIM_SMCR_TS_ITR0                (0x00U << TIM_SMCR_TS_Pos)              ///< Internal Trigger 0 (ITR0)
-#define TIM_SMCR_TS_ITR1                (0x01U << TIM_SMCR_TS_Pos)              ///< Internal Trigger 1 (ITR1)
-#define TIM_SMCR_TS_ITR2                (0x02U << TIM_SMCR_TS_Pos)              ///< Internal Trigger 2 (ITR2)
-#define TIM_SMCR_TS_ITR3                (0x03U << TIM_SMCR_TS_Pos)              ///< Internal Trigger 3 (ITR3)
-#define TIM_SMCR_TS_TI1F_ED             (0x04U << TIM_SMCR_TS_Pos)              ///< TI1 Edge Detector (TI1F_ED)
-#define TIM_SMCR_TS_TI1FP1              (0x05U << TIM_SMCR_TS_Pos)              ///< Filtered Timer Input 1 (TI1FP1)
-#define TIM_SMCR_TS_TI2FP2              (0x06U << TIM_SMCR_TS_Pos)              ///< Filtered Timer Input 2 (TI2FP2)
-#define TIM_SMCR_TS_ETRF                (0x07U << TIM_SMCR_TS_Pos)              ///< External Trigger input (ETRF)
-#define TIM_SMCR_MSM_Pos                (7)
-#define TIM_SMCR_MSM                    (0x01U << TIM_SMCR_MSM_Pos)             ///< Master/slave mode
-#define TIM_SMCR_ETF_Pos                (8)
-#define TIM_SMCR_ETF                    (0x0FU << TIM_SMCR_ETF_Pos)             ///< ETF[3:0] bits (External trigger filter)
-#define TIM_SMCR_ETF_0                  (0x01U << TIM_SMCR_ETF_Pos)             ///< Bit 0
-#define TIM_SMCR_ETF_1                  (0x02U << TIM_SMCR_ETF_Pos)             ///< Bit 1
-#define TIM_SMCR_ETF_2                  (0x04U << TIM_SMCR_ETF_Pos)             ///< Bit 2
-#define TIM_SMCR_ETF_3                  (0x08U << TIM_SMCR_ETF_Pos)             ///< Bit 3
-#define TIM_SMCR_ETPS_Pos               (12)
-#define TIM_SMCR_ETPS                   (0x03U << TIM_SMCR_ETPS_Pos)            ///< ETPS[1:0] bits (External trigger prescaler)
-#define TIM_SMCR_ETPS_OFF               (0x00U << TIM_SMCR_ETPS_Pos)            ///< Prescaler OFF
-#define TIM_SMCR_ETPS_DIV2              (0x01U << TIM_SMCR_ETPS_Pos)            ///< ETRP frequency divided by 2
-#define TIM_SMCR_ETPS_DIV4              (0x02U << TIM_SMCR_ETPS_Pos)            ///< ETRP frequency divided by 4
-#define TIM_SMCR_ETPS_DIV8              (0x03U << TIM_SMCR_ETPS_Pos)            ///< ETRP frequency divided by 8
-#define TIM_SMCR_ECEN_Pos               (14)
-#define TIM_SMCR_ECEN                   (0x01U << TIM_SMCR_ECEN_Pos)            ///< External clock enable
-#define TIM_SMCR_ETP_Pos                (15)
-#define TIM_SMCR_ETP                    (0x01U << TIM_SMCR_ETP_Pos)             ///< External trigger polarity
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_DIER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_DIER_UI_Pos                 (0)
-#define TIM_DIER_UI                     (0x01U << TIM_DIER_UI_Pos)              ///< Update interrupt enable
-#define TIM_DIER_CC1I_Pos               (1)
-#define TIM_DIER_CC1I                   (0x01U << TIM_DIER_CC1I_Pos)            ///< Capture/Compare 1 interrupt enable
-#define TIM_DIER_CC2I_Pos               (2)
-#define TIM_DIER_CC2I                   (0x01U << TIM_DIER_CC2I_Pos)            ///< Capture/Compare 2 interrupt enable
-#define TIM_DIER_CC3I_Pos               (3)
-#define TIM_DIER_CC3I                   (0x01U << TIM_DIER_CC3I_Pos)            ///< Capture/Compare 3 interrupt enable
-#define TIM_DIER_CC4I_Pos               (4)
-#define TIM_DIER_CC4I                   (0x01U << TIM_DIER_CC4I_Pos)            ///< Capture/Compare 4 interrupt enable
-#define TIM_DIER_COMI_Pos               (5)
-#define TIM_DIER_COMI                   (0x01U << TIM_DIER_COMI_Pos)            ///< COM interrupt enable
-#define TIM_DIER_TI_Pos                 (6)
-#define TIM_DIER_TI                     (0x01U << TIM_DIER_TI_Pos)              ///< Trigger interrupt enable
-#define TIM_DIER_BI_Pos                 (7)
-#define TIM_DIER_BI                     (0x01U << TIM_DIER_BI_Pos)              ///< Break interrupt enable
-#define TIM_DIER_UD_Pos                 (8)
-#define TIM_DIER_UD                     (0x01U << TIM_DIER_UD_Pos)              ///< Update DMA request enable
-#define TIM_DIER_CC1D_Pos               (9)
-#define TIM_DIER_CC1D                   (0x01U << TIM_DIER_CC1D_Pos)            ///< Capture/Compare 1 DMA request enable
-#define TIM_DIER_CC2D_Pos               (10)
-#define TIM_DIER_CC2D                   (0x01U << TIM_DIER_CC2D_Pos)            ///< Capture/Compare 2 DMA request enable
-#define TIM_DIER_CC3D_Pos               (11)
-#define TIM_DIER_CC3D                   (0x01U << TIM_DIER_CC3D_Pos)            ///< Capture/Compare 3 DMA request enable
-#define TIM_DIER_CC4D_Pos               (12)
-#define TIM_DIER_CC4D                   (0x01U << TIM_DIER_CC4D_Pos)            ///< Capture/Compare 4 DMA request enable
-#define TIM_DIER_COMD_Pos               (13)
-#define TIM_DIER_COMD                   (0x01U << TIM_DIER_COMD_Pos)            ///< COM DMA request enable
-#define TIM_DIER_TD_Pos                 (14)
-#define TIM_DIER_TD                     (0x01U << TIM_DIER_TD_Pos)              ///< Trigger DMA request enable
-#define TIM_DIER_CC5I_Pos               (16)
-#define TIM_DIER_CC5I                   (0x01U << TIM_DIER_CC5I_Pos)            ///< Capture/Compare 5 interrupt enable
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_SR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_SR_UI_Pos                   (0)
-#define TIM_SR_UI                       (0x01U << TIM_SR_UI_Pos)                ///< Update interrupt Flag
-#define TIM_SR_CC1I_Pos                 (1)
-#define TIM_SR_CC1I                     (0x01U << TIM_SR_CC1I_Pos)              ///< Capture/Compare 1 interrupt Flag
-#define TIM_SR_CC2I_Pos                 (2)
-#define TIM_SR_CC2I                     (0x01U << TIM_SR_CC2I_Pos)              ///< Capture/Compare 2 interrupt Flag
-#define TIM_SR_CC3I_Pos                 (3)
-#define TIM_SR_CC3I                     (0x01U << TIM_SR_CC3I_Pos)              ///< Capture/Compare 3 interrupt Flag
-#define TIM_SR_CC4I_Pos                 (4)
-#define TIM_SR_CC4I                     (0x01U << TIM_SR_CC4I_Pos)              ///< Capture/Compare 4 interrupt Flag
-#define TIM_SR_COMI_Pos                 (5)
-#define TIM_SR_COMI                     (0x01U << TIM_SR_COMI_Pos)              ///< COM interrupt Flag
-#define TIM_SR_TI_Pos                   (6)
-#define TIM_SR_TI                       (0x01U << TIM_SR_TI_Pos)                ///< Trigger interrupt Flag
-#define TIM_SR_BI_Pos                   (7)
-#define TIM_SR_BI                       (0x01U << TIM_SR_BI_Pos)                ///< Break interrupt Flag
-#define TIM_SR_CC1O_Pos                 (9)
-#define TIM_SR_CC1O                     (0x01U << TIM_SR_CC1O_Pos)              ///< Capture/Compare 1 Overcapture Flag
-#define TIM_SR_CC2O_Pos                 (10)
-#define TIM_SR_CC2O                     (0x01U << TIM_SR_CC2O_Pos)              ///< Capture/Compare 2 Overcapture Flag
-#define TIM_SR_CC3O_Pos                 (11)
-#define TIM_SR_CC3O                     (0x01U << TIM_SR_CC3O_Pos)              ///< Capture/Compare 3 Overcapture Flag
-#define TIM_SR_CC4O_Pos                 (12)
-#define TIM_SR_CC4O                     (0x01U << TIM_SR_CC4O_Pos)              ///< Capture/Compare 4 Overcapture Flag
-
-#define TIM_SR_CC5I_Pos                 (16)
-#define TIM_SR_CC5I                     (0x01U << TIM_SR_CC5I_Pos)              ///< Capture/Compare 5 interrupt Flag
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_EGR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_EGR_UG_Pos                  (0)
-#define TIM_EGR_UG                      (0x01U << TIM_EGR_UG_Pos)               ///< Update Generation
-#define TIM_EGR_CC1G_Pos                (1)
-#define TIM_EGR_CC1G                    (0x01U << TIM_EGR_CC1G_Pos)             ///< Capture/Compare 1 Generation
-#define TIM_EGR_CC2G_Pos                (2)
-#define TIM_EGR_CC2G                    (0x01U << TIM_EGR_CC2G_Pos)             ///< Capture/Compare 2 Generation
-#define TIM_EGR_CC3G_Pos                (3)
-#define TIM_EGR_CC3G                    (0x01U << TIM_EGR_CC3G_Pos)             ///< Capture/Compare 3 Generation
-#define TIM_EGR_CC4G_Pos                (4)
-#define TIM_EGR_CC4G                    (0x01U << TIM_EGR_CC4G_Pos)             ///< Capture/Compare 4 Generation
-#define TIM_EGR_COMG_Pos                (5)
-#define TIM_EGR_COMG                    (0x01U << TIM_EGR_COMG_Pos)             ///< Capture/Compare Control Update Generation
-#define TIM_EGR_TG_Pos                  (6)
-#define TIM_EGR_TG                      (0x01U << TIM_EGR_TG_Pos)               ///< Trigger Generation
-#define TIM_EGR_BG_Pos                  (7)
-#define TIM_EGR_BG                      (0x01U << TIM_EGR_BG_Pos)               ///< Break Generation
-
-#define TIM_EGR_CC5G_Pos                (16)
-#define TIM_EGR_CC5G                    (0x01U << TIM_EGR_CC5G_Pos)             ///< Capture/Compare 5 Generation
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCMR1 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCMR1_CC1S_Pos              (0)
-#define TIM_CCMR1_CC1S                  (0x03U << TIM_CCMR1_CC1S_Pos)           ///< CC1S[1:0] bits (Capture/Compare 1 Selection)
-#define TIM_CCMR1_CC1S_OC               (0x00U << TIM_CCMR1_CC1S_Pos)           ///< Channel is configured as output
-#define TIM_CCMR1_CC1S_DIRECTTI         (0x01U << TIM_CCMR1_CC1S_Pos)           ///< Channel is configured as input, IC1 is mapped on TI1
-#define TIM_CCMR1_CC1S_INDIRECTTI       (0x02U << TIM_CCMR1_CC1S_Pos)           ///< Channel is configured as input, IC1 is mapped on TI2
-#define TIM_CCMR1_CC1S_TRC              (0x03U << TIM_CCMR1_CC1S_Pos)           ///< Channel is configured as input, IC1 is mapped on TRC
-#define TIM_CCMR1_OC1FEN_Pos            (2)
-#define TIM_CCMR1_OC1FEN                (0x01U << TIM_CCMR1_OC1FEN_Pos)         ///< Output Compare 1 Fast enable
-
-#define TIM_CCMR1_OC1PEN_Pos            (3)
-#define TIM_CCMR1_OC1PEN                (0x01U << TIM_CCMR1_OC1PEN_Pos)         ///< Output Compare 1 Preload enable
-#define TIM_CCMR1_OC1M_Pos              (4)
-#define TIM_CCMR1_OC1M                  (0x07U << TIM_CCMR1_OC1M_Pos)           ///< OC1M[2:0] bits (Output Compare 1 Mode)
-#define TIM_CCMR1_OC1M_TIMING           (0x00U << TIM_CCMR1_OC1M_Pos)           ///< Timing
-#define TIM_CCMR1_OC1M_ACTIVE           (0x01U << TIM_CCMR1_OC1M_Pos)           ///< Active
-#define TIM_CCMR1_OC1M_INACTIVE         (0x02U << TIM_CCMR1_OC1M_Pos)           ///< Inactive
-#define TIM_CCMR1_OC1M_TOGGLE           (0x03U << TIM_CCMR1_OC1M_Pos)           ///< Toggle
-#define TIM_CCMR1_OC1M_FORCEINACTIVE    (0x04U << TIM_CCMR1_OC1M_Pos)           ///< Forceinactive
-#define TIM_CCMR1_OC1M_FORCEACTIVE      (0x05U << TIM_CCMR1_OC1M_Pos)           ///< Forceactive
-#define TIM_CCMR1_OC1M_PWM1             (0x06U << TIM_CCMR1_OC1M_Pos)           ///< PWM1
-#define TIM_CCMR1_OC1M_PWM2             (0x07U << TIM_CCMR1_OC1M_Pos)           ///< PWM2
-
-#define TIM_CCMR1_OC1CEN_Pos            (7)
-#define TIM_CCMR1_OC1CEN                (0x01U << TIM_CCMR1_OC1CEN_Pos)         ///< Output Compare 1Clear Enable
-#define TIM_CCMR1_CC2S_Pos              (8)
-#define TIM_CCMR1_CC2S                  (0x03U << TIM_CCMR1_CC2S_Pos)           ///< CC2S[1:0] bits (Capture/Compare 2 Selection)
-#define TIM_CCMR1_CC2S_OC               (0x00U << TIM_CCMR1_CC2S_Pos)           ///< Channel is configured as output
-#define TIM_CCMR1_CC2S_DIRECTTI         (0x01U << TIM_CCMR1_CC2S_Pos)           ///< Channel is configured as input, IC2 is mapped on TI2
-#define TIM_CCMR1_CC2S_INDIRECTTI       (0x02U << TIM_CCMR1_CC2S_Pos)           ///< Channel is configured as input, IC2 is mapped on TI1
-#define TIM_CCMR1_CC2S_TRC              (0x03U << TIM_CCMR1_CC2S_Pos)           ///< Channel is configured as input, IC2 is mapped on TRC
-#define TIM_CCMR1_OC2FEN_Pos            (10)
-#define TIM_CCMR1_OC2FEN                (0x01U << TIM_CCMR1_OC2FEN_Pos)         ///< Output Compare 2 Fast enable
-#define TIM_CCMR1_OC2PEN_Pos            (11)
-#define TIM_CCMR1_OC2PEN                (0x01U << TIM_CCMR1_OC2PEN_Pos)         ///< Output Compare 2 Preload enable
-#define TIM_CCMR1_OC2M_Pos              (12)
-#define TIM_CCMR1_OC2M                  (0x07U << TIM_CCMR1_OC2M_Pos)           ///< OC2M[2:0] bits (Output Compare 2 Mode)
-#define TIM_CCMR1_OC2M_TIMING           (0x00U << TIM_CCMR1_OC2M_Pos)           ///< Timing
-#define TIM_CCMR1_OC2M_ACTIVE           (0x01U << TIM_CCMR1_OC2M_Pos)           ///< Active
-#define TIM_CCMR1_OC2M_INACTIVE         (0x02U << TIM_CCMR1_OC2M_Pos)           ///< Inactive
-#define TIM_CCMR1_OC2M_TOGGLE           (0x03U << TIM_CCMR1_OC2M_Pos)           ///< Toggle
-#define TIM_CCMR1_OC2M_FORCEINACTIVE    (0x04U << TIM_CCMR1_OC2M_Pos)           ///< Forceinactive
-#define TIM_CCMR1_OC2M_FORCEACTIVE      (0x05U << TIM_CCMR1_OC2M_Pos)           ///< Forceactive
-#define TIM_CCMR1_OC2M_PWM1             (0x06U << TIM_CCMR1_OC2M_Pos)           ///< PWM1
-#define TIM_CCMR1_OC2M_PWM2             (0x07U << TIM_CCMR1_OC2M_Pos)           ///< PWM2
-#define TIM_CCMR1_OC2CEN_Pos            (15)
-#define TIM_CCMR1_OC2CEN                (0x01U << TIM_CCMR1_OC2CEN_Pos)         ///< Output Compare 2 Clear Enable
-
-#define TIM_CCMR1_IC1PSC_Pos            (2)
-#define TIM_CCMR1_IC1PSC                (0x03U << TIM_CCMR1_IC1PSC_Pos)         ///< IC1PSC[1:0] bits (Input Capture 1 Prescaler)
-#define TIM_CCMR1_IC1PSC_DIV1           (0x00U << TIM_CCMR1_IC1PSC_Pos)         ///< No Prescaler
-#define TIM_CCMR1_IC1PSC_DIV2           (0x01U << TIM_CCMR1_IC1PSC_Pos)         ///< Capture is done once every 2 events
-#define TIM_CCMR1_IC1PSC_DIV4           (0x02U << TIM_CCMR1_IC1PSC_Pos)         ///< Capture is done once every 4 events
-#define TIM_CCMR1_IC1PSC_DIV8           (0x03U << TIM_CCMR1_IC1PSC_Pos)         ///< Capture is done once every 8 events
-#define TIM_CCMR1_IC1F_Pos              (4)
-#define TIM_CCMR1_IC1F                  (0x0FU << TIM_CCMR1_IC1F_Pos)           ///< IC1F[3:0] bits (Input Capture 1 Filter)
-#define TIM_CCMR1_IC1F_0                (0x01U << TIM_CCMR1_IC1F_Pos)           ///< Bit 0
-#define TIM_CCMR1_IC1F_1                (0x02U << TIM_CCMR1_IC1F_Pos)           ///< Bit 1
-#define TIM_CCMR1_IC1F_2                (0x04U << TIM_CCMR1_IC1F_Pos)           ///< Bit 2
-#define TIM_CCMR1_IC1F_3                (0x08U << TIM_CCMR1_IC1F_Pos)           ///< Bit 3
-
-#define TIM_CCMR1_IC2PSC_Pos            (10)
-#define TIM_CCMR1_IC2PSC                (0x03U << TIM_CCMR1_IC2PSC_Pos)         ///< IC2PSC[1:0] bits (Input Capture 2 Prescaler)
-#define TIM_CCMR1_IC2PSC_DIV1           (0x00U << TIM_CCMR1_IC2PSC_Pos)         ///< No Prescaler
-#define TIM_CCMR1_IC2PSC_DIV2           (0x01U << TIM_CCMR1_IC2PSC_Pos)         ///< Capture is done once every 2 events
-#define TIM_CCMR1_IC2PSC_DIV4           (0x02U << TIM_CCMR1_IC2PSC_Pos)         ///< Capture is done once every 4 events
-#define TIM_CCMR1_IC2PSC_DIV8           (0x03U << TIM_CCMR1_IC2PSC_Pos)         ///< Capture is done once every 8 events
-#define TIM_CCMR1_IC2F_Pos              (12)
-#define TIM_CCMR1_IC2F                  (0x0FU << TIM_CCMR1_IC2F_Pos)           ///< IC2F[3:0] bits (Input Capture 2 Filter)
-#define TIM_CCMR1_IC2F_0                (0x01U << TIM_CCMR1_IC2F_Pos)           ///< Bit 0
-#define TIM_CCMR1_IC2F_1                (0x02U << TIM_CCMR1_IC2F_Pos)           ///< Bit 1
-#define TIM_CCMR1_IC2F_2                (0x04U << TIM_CCMR1_IC2F_Pos)           ///< Bit 2
-#define TIM_CCMR1_IC2F_3                (0x08U << TIM_CCMR1_IC2F_Pos)           ///< Bit 3
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCMR2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCMR2_CC3S_Pos              (0)
-#define TIM_CCMR2_CC3S                  (0x03U << TIM_CCMR2_CC3S_Pos)           ///< CC3S[1:0] bits (Capture/Compare 3 Selection)
-#define TIM_CCMR2_CC3S_OC               (0x00U << TIM_CCMR2_CC3S_Pos)           ///< Channel is configured as output
-#define TIM_CCMR2_CC3S_DIRECTTI         (0x01U << TIM_CCMR2_CC3S_Pos)           ///< Channel is configured as input, IC3 is mapped on TI3
-#define TIM_CCMR2_CC3S_INDIRECTTI       (0x02U << TIM_CCMR2_CC3S_Pos)           ///< Channel is configured as input, IC3 is mapped on TI4
-#define TIM_CCMR2_CC3S_TRC              (0x03U << TIM_CCMR2_CC3S_Pos)           ///< Channel is configured as input, IC3 is mapped on TRC
-#define TIM_CCMR2_OC3FEN_Pos            (2)
-#define TIM_CCMR2_OC3FEN                (0x01U << TIM_CCMR2_OC3FEN_Pos)         ///< Output Compare 3 Fast enable
-#define TIM_CCMR2_IC3PSC_Pos            (2)
-#define TIM_CCMR2_IC3PSC                (0x03U << TIM_CCMR2_IC3PSC_Pos)         ///< IC3PSC[1:0] bits (Input Capture 3 Prescaler)
-#define TIM_CCMR2_IC3PSC_DIV1           (0x00U << TIM_CCMR2_IC3PSC_Pos)         ///< No Prescaler
-#define TIM_CCMR2_IC3PSC_DIV2           (0x01U << TIM_CCMR2_IC3PSC_Pos)         ///< Capture is done once every 2 events
-#define TIM_CCMR2_IC3PSC_DIV4           (0x02U << TIM_CCMR2_IC3PSC_Pos)         ///< Capture is done once every 4 events
-#define TIM_CCMR2_IC3PSC_DIV8           (0x03U << TIM_CCMR2_IC3PSC_Pos)         ///< Capture is done once every 8 events
-#define TIM_CCMR2_OC3PEN_Pos            (3)
-#define TIM_CCMR2_OC3PEN                (0x01U << TIM_CCMR2_OC3PEN_Pos)         ///< Output Compare 3 Preload enable
-#define TIM_CCMR2_OC3M_Pos              (4)
-#define TIM_CCMR2_OC3M                  (0x07U << TIM_CCMR2_OC3M_Pos)           ///< OC3M[2:0] bits (Output Compare 3 Mode)
-#define TIM_CCMR2_OC3M_TIMING           (0x00U << TIM_CCMR2_OC3M_Pos)           ///< Timing
-#define TIM_CCMR2_OC3M_ACTIVE           (0x01U << TIM_CCMR2_OC3M_Pos)           ///< Active
-#define TIM_CCMR2_OC3M_INACTIVE         (0x02U << TIM_CCMR2_OC3M_Pos)           ///< Inactive
-#define TIM_CCMR2_OC3M_TOGGLE           (0x03U << TIM_CCMR2_OC3M_Pos)           ///< Toggle
-#define TIM_CCMR2_OC3M_FORCEINACTIVE    (0x04U << TIM_CCMR2_OC3M_Pos)           ///< Forceinactive
-#define TIM_CCMR2_OC3M_FORCEACTIVE      (0x05U << TIM_CCMR2_OC3M_Pos)           ///< Forceactive
-#define TIM_CCMR2_OC3M_PWM1             (0x06U << TIM_CCMR2_OC3M_Pos)           ///< PWM1
-#define TIM_CCMR2_OC3M_PWM2             (0x07U << TIM_CCMR2_OC3M_Pos)           ///< PWM2
-#define TIM_CCMR2_IC3F_Pos              (4)
-#define TIM_CCMR2_IC3F                  (0x0FU << TIM_CCMR2_IC3F_Pos)           ///< IC3F[3:0] bits (Input Capture 3 Filter)
-#define TIM_CCMR2_IC3F_0                (0x01U << TIM_CCMR2_IC3F_Pos)           ///< Bit 0
-#define TIM_CCMR2_IC3F_1                (0x02U << TIM_CCMR2_IC3F_Pos)           ///< Bit 1
-#define TIM_CCMR2_IC3F_2                (0x04U << TIM_CCMR2_IC3F_Pos)           ///< Bit 2
-#define TIM_CCMR2_IC3F_3                (0x08U << TIM_CCMR2_IC3F_Pos)           ///< Bit 3
-#define TIM_CCMR2_OC3CEN_Pos            (7)
-#define TIM_CCMR2_OC3CEN                (0x01U << TIM_CCMR2_OC3CEN_Pos)         ///< Output Compare 3 Clear Enable
-#define TIM_CCMR2_CC4S_Pos              (8)
-#define TIM_CCMR2_CC4S                  (0x03U << TIM_CCMR2_CC4S_Pos)           ///< CC4S[1:0] bits (Capture/Compare 4 Selection)
-#define TIM_CCMR2_CC4S_OC               (0x00U << TIM_CCMR2_CC4S_Pos)           ///< Channel is configured as output
-#define TIM_CCMR2_CC4S_DIRECTTI         (0x01U << TIM_CCMR2_CC4S_Pos)           ///< Channel is configured as input, IC4 is mapped on TI4
-#define TIM_CCMR2_CC4S_INDIRECTTI       (0x02U << TIM_CCMR2_CC4S_Pos)           ///< Channel is configured as input, IC4 is mapped on TI3
-#define TIM_CCMR2_CC4S_TRC              (0x03U << TIM_CCMR2_CC4S_Pos)           ///< Channel is configured as input, IC4 is mapped on TRC
-#define TIM_CCMR2_OC4FEN_Pos            (10)
-#define TIM_CCMR2_OC4FEN                (0x01U << TIM_CCMR2_OC4FEN_Pos)         ///< Output Compare 4 Fast enable
-#define TIM_CCMR2_OC4PEN_Pos            (11)
-#define TIM_CCMR2_OC4PEN                (0x01U << TIM_CCMR2_OC4PEN_Pos)         ///< Output Compare 4 Preload enable
-#define TIM_CCMR2_OC4M_Pos              (12)
-#define TIM_CCMR2_OC4M                  (0x07U << TIM_CCMR2_OC4M_Pos)           ///< OC4M[2:0] bits (Output Compare 4 Mode)
-#define TIM_CCMR2_OC4M_TIMING           (0x00U << TIM_CCMR2_OC4M_Pos)           ///< Timing
-#define TIM_CCMR2_OC4M_ACTIVE           (0x01U << TIM_CCMR2_OC4M_Pos)           ///< Active
-#define TIM_CCMR2_OC4M_INACTIVE         (0x02U << TIM_CCMR2_OC4M_Pos)           ///< Inactive
-#define TIM_CCMR2_OC4M_TOGGLE           (0x03U << TIM_CCMR2_OC4M_Pos)           ///< Toggle
-#define TIM_CCMR2_OC4M_FORCEINACTIVE    (0x04U << TIM_CCMR2_OC4M_Pos)           ///< Forceinactive
-#define TIM_CCMR2_OC4M_FORCEACTIVE      (0x05U << TIM_CCMR2_OC4M_Pos)           ///< Forceactive
-#define TIM_CCMR2_OC4M_PWM1             (0x06U << TIM_CCMR2_OC4M_Pos)           ///< PWM1
-#define TIM_CCMR2_OC4M_PWM2             (0x07U << TIM_CCMR2_OC4M_Pos)           ///< PWM2
-#define TIM_CCMR2_OC4CEN_Pos            (15)
-#define TIM_CCMR2_OC4CEN                (0x01U << TIM_CCMR2_OC4CEN_Pos)         ///< Output Compare 4 Clear Enable
-#define TIM_CCMR2_IC4PSC_Pos            (10)
-#define TIM_CCMR2_IC4PSC                (0x03U << TIM_CCMR2_IC4PSC_Pos)         ///< IC4PSC[1:0] bits (Input Capture 4 Prescaler)
-#define TIM_CCMR2_IC4PSC_DIV1           (0x00U << TIM_CCMR2_IC4PSC_Pos)         ///< No Prescaler
-#define TIM_CCMR2_IC4PSC_DIV2           (0x01U << TIM_CCMR2_IC4PSC_Pos)         ///< Capture is done once every 2 events
-#define TIM_CCMR2_IC4PSC_DIV4           (0x02U << TIM_CCMR2_IC4PSC_Pos)         ///< Capture is done once every 4 events
-#define TIM_CCMR2_IC4PSC_DIV8           (0x03U << TIM_CCMR2_IC4PSC_Pos)         ///< Capture is done once every 8 events
-#define TIM_CCMR2_IC4F_Pos              (12)
-#define TIM_CCMR2_IC4F                  (0x0FU << TIM_CCMR2_IC4F_Pos)           ///< IC4F[3:0] bits (Input Capture 4 Filter)
-#define TIM_CCMR2_IC4F_0                (0x01U << TIM_CCMR2_IC4F_Pos)           ///< Bit 0
-#define TIM_CCMR2_IC4F_1                (0x02U << TIM_CCMR2_IC4F_Pos)           ///< Bit 1
-#define TIM_CCMR2_IC4F_2                (0x04U << TIM_CCMR2_IC4F_Pos)           ///< Bit 2
-#define TIM_CCMR2_IC4F_3                (0x08U << TIM_CCMR2_IC4F_Pos)           ///< Bit 3
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCER_CC1EN_Pos              (0)
-#define TIM_CCER_CC1EN                  (0x01U << TIM_CCER_CC1EN_Pos)           ///< Capture/Compare 1 output enable
-#define TIM_CCER_CC1P_Pos               (1)
-#define TIM_CCER_CC1P                   (0x01U << TIM_CCER_CC1P_Pos)            ///< Capture/Compare 1 output Polarity
-#define TIM_CCER_CC1NEN_Pos             (2)
-#define TIM_CCER_CC1NEN                 (0x01U << TIM_CCER_CC1NEN_Pos)          ///< Capture/Compare 1 Complementary output enable
-#define TIM_CCER_CC1NP_Pos              (3)
-#define TIM_CCER_CC1NP                  (0x01U << TIM_CCER_CC1NP_Pos)           ///< Capture/Compare 1 Complementary output Polarity
-#define TIM_CCER_CC2EN_Pos              (4)
-#define TIM_CCER_CC2EN                  (0x01U << TIM_CCER_CC2EN_Pos)           ///< Capture/Compare 2 output enable
-#define TIM_CCER_CC2P_Pos               (5)
-#define TIM_CCER_CC2P                   (0x01U << TIM_CCER_CC2P_Pos)            ///< Capture/Compare 2 output Polarity
-#define TIM_CCER_CC2NEN_Pos             (6)
-#define TIM_CCER_CC2NEN                 (0x01U << TIM_CCER_CC2NEN_Pos)          ///< Capture/Compare 2 Complementary output enable
-#define TIM_CCER_CC2NP_Pos              (7)
-#define TIM_CCER_CC2NP                  (0x01U << TIM_CCER_CC2NP_Pos)           ///< Capture/Compare 2 Complementary output Polarity
-#define TIM_CCER_CC3EN_Pos              (8)
-#define TIM_CCER_CC3EN                  (0x01U << TIM_CCER_CC3EN_Pos)           ///< Capture/Compare 3 output enable
-#define TIM_CCER_CC3P_Pos               (9)
-#define TIM_CCER_CC3P                   (0x01U << TIM_CCER_CC3P_Pos)            ///< Capture/Compare 3 output Polarity
-#define TIM_CCER_CC3NEN_Pos             (10)
-#define TIM_CCER_CC3NEN                 (0x01U << TIM_CCER_CC3NEN_Pos)          ///< Capture/Compare 3 Complementary output enable
-#define TIM_CCER_CC3NP_Pos              (11)
-#define TIM_CCER_CC3NP                  (0x01U << TIM_CCER_CC3NP_Pos)           ///< Capture/Compare 3 Complementary output Polarity
-#define TIM_CCER_CC4EN_Pos              (12)
-#define TIM_CCER_CC4EN                  (0x01U << TIM_CCER_CC4EN_Pos)           ///< Capture/Compare 4 output enable
-#define TIM_CCER_CC4P_Pos               (13)
-#define TIM_CCER_CC4P                   (0x01U << TIM_CCER_CC4P_Pos)            ///< Capture/Compare 4 output Polarity
-#define TIM_CCER_CC4NP_Pos              (15)
-#define TIM_CCER_CC4NP                  (0x01U << TIM_CCER_CC4NP_Pos)           ///< Capture/Compare 4 complementary output polarity
-
-#define TIM_CCER_CC5EN_Pos              (16)
-#define TIM_CCER_CC5EN                  (0x01U << TIM_CCER_CC5EN_Pos)           ///< Capture/Compare 5 output enable
-#define TIM_CCER_CC5P_Pos               (17)
-#define TIM_CCER_CC5P                   (0x01U << TIM_CCER_CC5P_Pos)            ///< Capture/Compare 5 output Polarity
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CNT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CNT_CNT                     (0xFFFFU)                               ///< Counter Value
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_PSC Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_PSC_PSC                     (0xFFFFU)                               ///< Prescaler Value
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_ARR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_ARR_ARR                     (0xFFFFU)                               ///< actual auto-reload Value
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_RCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_RCR_REP                     (0xFFU)                                 ///< Repetition Counter Value
-
-#define TIM_RCR_REP_CNT_Pos             (8)
-#define TIM_RCR_REP_CNT                 (0xFFU << TIM_RCR_REP_CNT_Pos)          ///< Repetition counter value of real-time writing
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCR1 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCR1_CCR1                  (0xFFFFU)                               ///< Capture/Compare 1 Value
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCR2 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCR2_CCR2                  (0xFFFFU)                               ///< Capture/Compare 2 Value
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCR3 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCR3_CCR3                  (0xFFFFU)                               ///< Capture/Compare 3 Value
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCR4 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCR4_CCR4                  (0xFFFFU)                               ///< Capture/Compare 4 Value
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_BDTR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_BDTR_DTG_Pos                (0)
-#define TIM_BDTR_DTG                    (0xFFU << TIM_BDTR_DTG_Pos)             ///< DTG[0:7] bits (Dead-Time Generator set-up)
-#define TIM_BDTR_DTG_0                  (0x01U << TIM_BDTR_DTG_Pos)             ///< Bit 0
-#define TIM_BDTR_DTG_1                  (0x02U << TIM_BDTR_DTG_Pos)             ///< Bit 1
-#define TIM_BDTR_DTG_2                  (0x04U << TIM_BDTR_DTG_Pos)             ///< Bit 2
-#define TIM_BDTR_DTG_3                  (0x08U << TIM_BDTR_DTG_Pos)             ///< Bit 3
-#define TIM_BDTR_DTG_4                  (0x10U << TIM_BDTR_DTG_Pos)             ///< Bit 4
-#define TIM_BDTR_DTG_5                  (0x20U << TIM_BDTR_DTG_Pos)             ///< Bit 5
-#define TIM_BDTR_DTG_6                  (0x40U << TIM_BDTR_DTG_Pos)             ///< Bit 6
-#define TIM_BDTR_DTG_7                  (0x80U << TIM_BDTR_DTG_Pos)             ///< Bit 7
-#define TIM_BDTR_LOCK_Pos               (8)
-#define TIM_BDTR_LOCK                   (0x03U << TIM_BDTR_LOCK_Pos)            ///< LOCK[1:0] bits (Lock Configuration)
-#define TIM_BDTR_LOCK_OFF               (0x00U << TIM_BDTR_LOCK_Pos)            ///< Lock Off
-#define TIM_BDTR_LOCK_1                 (0x01U << TIM_BDTR_LOCK_Pos)            ///< Lock Level 1
-#define TIM_BDTR_LOCK_2                 (0x02U << TIM_BDTR_LOCK_Pos)            ///< Lock Level 2
-#define TIM_BDTR_LOCK_3                 (0x03U << TIM_BDTR_LOCK_Pos)            ///< Lock Level 3
-#define TIM_BDTR_OSSI_Pos               (10)
-#define TIM_BDTR_OSSI                   (0x01U << TIM_BDTR_OSSI_Pos)            ///< Off-State Selection for Idle mode
-#define TIM_BDTR_OSSR_Pos               (11)
-#define TIM_BDTR_OSSR                   (0x01U << TIM_BDTR_OSSR_Pos)            ///< Off-State Selection for Run mode
-#define TIM_BDTR_BKEN_Pos               (12)
-#define TIM_BDTR_BKEN                   (0x01U << TIM_BDTR_BKEN_Pos)            ///< Break enable
-#define TIM_BDTR_BKP_Pos                (13)
-#define TIM_BDTR_BKP                    (0x01U << TIM_BDTR_BKP_Pos)             ///< Break Polarity
-#define TIM_BDTR_AOEN_Pos               (14)
-#define TIM_BDTR_AOEN                   (0x01U << TIM_BDTR_AOEN_Pos)            ///< Automatic Output enable
-#define TIM_BDTR_MOEN_Pos               (15)
-#define TIM_BDTR_MOEN                   (0x01U << TIM_BDTR_MOEN_Pos)            ///< Main Output enable
-
-#define TIM_BDTR_DOEN_Pos               (16)
-#define TIM_BDTR_DOEN                   (0x01U << TIM_BDTR_DOEN_Pos)            ///< Direct Output enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_DCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_DCR_DBA_Pos                 (0)
-#define TIM_DCR_DBA                     (0x1FU << TIM_DCR_DBA_Pos)              ///< DBA[4:0] bits (DMA Base Address)
-#define TIM_DCR_DBA_0                   (0x01U << TIM_DCR_DBA_Pos)              ///< Bit 0
-#define TIM_DCR_DBA_1                   (0x02U << TIM_DCR_DBA_Pos)              ///< Bit 1
-#define TIM_DCR_DBA_2                   (0x04U << TIM_DCR_DBA_Pos)              ///< Bit 2
-#define TIM_DCR_DBA_3                   (0x08U << TIM_DCR_DBA_Pos)              ///< Bit 3
-#define TIM_DCR_DBA_4                   (0x10U << TIM_DCR_DBA_Pos)              ///< Bit 4
-#define TIM_DCR_DBL_Pos                 (8)
-#define TIM_DCR_DBL                     (0x1FU << TIM_DCR_DBL_Pos)              ///< DBL[4:0] bits (DMA Burst Length)
-#define TIM_DCR_DBL_0                   (0x01U << TIM_DCR_DBL_Pos)              ///< Bit 0
-#define TIM_DCR_DBL_1                   (0x02U << TIM_DCR_DBL_Pos)              ///< Bit 1
-#define TIM_DCR_DBL_2                   (0x04U << TIM_DCR_DBL_Pos)              ///< Bit 2
-#define TIM_DCR_DBL_3                   (0x08U << TIM_DCR_DBL_Pos)              ///< Bit 3
-#define TIM_DCR_DBL_4                   (0x10U << TIM_DCR_DBL_Pos)              ///< Bit 4
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_DMAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_DMAR_DMAB                   (0xFFFFU)                               ///< DMA register for burst accesses
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCMR3 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCMR3_OC5FEN_Pos        (2)
-#define TIM_CCMR3_OC5FEN            (0x01U << TIM_CCMR3_OC5FEN_Pos)         ///< Output Compare 5 Fast enable
-#define TIM_CCMR3_OC5PEN_Pos        (3)
-#define TIM_CCMR3_OC5PEN            (0x01U << TIM_CCMR3_OC5PEN_Pos)         ///< Output Compare 5 Preload enable
-#define TIM_CCMR3_OC5M_Pos          (4)
-#define TIM_CCMR3_OC5M              (0x07U << TIM_CCMR3_OC5M_Pos)           ///< OC5M[2:0] bits (Output Compare 5 Mode)
-
-#define TIM_CCMR3_OC5CEN_Pos        (7)
-#define TIM_CCMR3_OC5CEN            (0x01U << TIM_CCMR3_OC5CEN_Pos)         ///< Output Compare 5 Clear Enable
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCR5 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCR5_CCR5               (0xFFFF)                                ///< Capture/Compare 5 Value
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_PDER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_PDER_CCDREPE_Pos        (0)
-#define TIM_PDER_CCDREPE            (0x01U << TIM_PDER_CCDREPE_Pos)         ///< DMA request flow enable
-#define TIM_PDER_CCR1SHIFTEN_Pos    (1)
-#define TIM_PDER_CCR1SHIFTEN        (0x01U << TIM_PDER_CCR1SHIFTEN_Pos)     ///< CCR1 pwm shift enable
-#define TIM_PDER_CCR2SHIFTEN_Pos    (2)
-#define TIM_PDER_CCR2SHIFTEN        (0x01U << TIM_PDER_CCR2SHIFTEN_Pos)     ///< CCR2 pwm shift enable
-#define TIM_PDER_CCR3SHIFTEN_Pos    (3)
-#define TIM_PDER_CCR3SHIFTEN        (0x01U << TIM_PDER_CCR3SHIFTEN_Pos)     ///< CCR3 pwm shift enable
-#define TIM_PDER_CCR4SHIFTEN_Pos    (4)
-#define TIM_PDER_CCR4SHIFTEN        (0x01U << TIM_PDER_CCR4SHIFTEN_Pos)     ///< CCR4 pwm shift enable
-#define TIM_PDER_CCR5SHIFTEN_Pos    (5)
-#define TIM_PDER_CCR5SHIFTEN        (0x01U << TIM_PDER_CCR5SHIFTEN_Pos)     ///< CCR5 pwm shift enable
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCR1FALL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCR1FALL_CCR1FALL       (0xFFFFU)                               ///< Capture/compare value for ch1 when counting down in PWM center-aligned mode
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCR2FALL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCR2FALL_CCR2FALL       (0xFFFFU)                               ///< Capture/compare value for ch2 when counting down in PWM center-aligned mode
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCR3FALL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCR3FALL_CCR3FALL       (0xFFFFU)                               ///< Capture/compare value for ch3 when counting down in PWM center-aligned mode
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCR4FALL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCR4FALL_CCR4FALL       (0xFFFFU)                               ///< Capture/compare value for ch4 when counting down in PWM center-aligned mode
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief TIM_CCR5FALL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define TIM_CCR5FALL_CCR5FALL       (0xFFFFU)                               ///< Capture/compare value for ch5 when counting down in PWM center-aligned mode
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h
deleted file mode 100644
index 069ff2cf9..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_uart.h
+++ /dev/null
@@ -1,362 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_uart.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_UART_H
-#define __REG_UART_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART1_BASE                      (APB2PERIPH_BASE + 0x3800)              ///< Base Address: 0x40013800
-#define UART2_BASE                      (APB1PERIPH_BASE + 0x4400)              ///< Base Address: 0x40004400
-#define UART3_BASE                      (APB1PERIPH_BASE + 0x4800)              ///< Base Address: 0x40004800
-#define UART4_BASE                      (APB1PERIPH_BASE + 0x4C00)              ///< Base Address: 0x40004C00
-#define UART5_BASE                      (APB1PERIPH_BASE + 0x5000)              ///< Base Address: 0x40005000
-#define UART6_BASE                      (APB2PERIPH_BASE + 0x3C00)              ///< Base Address: 0x40013C00
-#define UART7_BASE                      (APB1PERIPH_BASE + 0x7800)              ///< Base Address: 0x40007800
-#define UART8_BASE                      (APB1PERIPH_BASE + 0x7C00)              ///< Base Address: 0x40007C00
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-typedef struct {
-    __IO u32 TDR;                                                               ///< Transmit Data Register,                        offset: 0x00
-    __IO u32 RDR;                                                               ///< Receive Data Register,                         offset: 0x04
-    __IO u32 CSR;                                                               ///< Current Status Register,                       offset: 0x08
-    __IO u32 ISR;                                                               ///< Interrupt Status Register,                     offset: 0x0C
-    __IO u32 IER;                                                               ///< Interrupt Enable Register,                     offset: 0x10
-    __IO u32 ICR;                                                               ///< Interrupt Clear Register,                      offset: 0x14
-    __IO u32 GCR;                                                               ///< Global Control Register,                       offset: 0x18
-    __IO u32 CCR;                                                               ///< Config Control Register,                       offset: 0x1C
-    __IO u32 BRR;                                                               ///< Baud Rate Register,                            offset: 0x20
-    __IO u32 FRA;                                                               ///< Fraction Register,                             offset: 0x24
-
-    __IO u32 RXAR;                                                              ///< Receive Address Register,                      offset: 0x28
-    __IO u32 RXMR;                                                              ///< Receive Address Mask Register,                 offset: 0x2C
-    __IO u32 SCR;                                                               ///< Smart Card Register,                           offset: 0x30
-
-    __IO u32 IDLR;                                                              ///< Data length register                          offset: 0x34
-    __IO u32 ABRCR;                                                             ///< automatic Baud rate control delivery          offset: 0x38
-    __IO u32 IRDA;                                                              ///< Infrared function control register,           offset: 0x3C
-} UART_TypeDef;
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART1                           ((UART_TypeDef*) UART1_BASE)
-#define UART2                           ((UART_TypeDef*) UART2_BASE)
-
-#define UART3                           ((UART_TypeDef*) UART3_BASE)
-#define UART4                           ((UART_TypeDef*) UART4_BASE)
-#define UART5                           ((UART_TypeDef*) UART5_BASE)
-#define UART6                           ((UART_TypeDef*) UART6_BASE)
-#define UART7                           ((UART_TypeDef*) UART7_BASE)
-#define UART8                           ((UART_TypeDef*) UART8_BASE)
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_TDR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_TDR_DATA_Pos               (0)
-#define UART_TDR_DATA                   (0xFFU << UART_TDR_DATA_Pos)            ///< Transmit data register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_RDR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_RDR_DATA_Pos               (0)
-#define UART_RDR_DATA                   (0xFFU << UART_RDR_DATA_Pos)            ///< Receive data register
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_CSR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_CSR_TXC_Pos                (0)
-#define UART_CSR_TXC                    (0x01U << UART_CSR_TXC_Pos)             ///< Transmit complete flag bit
-#define UART_CSR_RXAVL_Pos              (1)
-#define UART_CSR_RXAVL                  (0x01U << UART_CSR_RXAVL_Pos)           ///< Receive valid data flag bit
-#define UART_CSR_TXFULL_Pos             (2)
-#define UART_CSR_TXFULL                 (0x01U << UART_CSR_TXFULL_Pos)          ///< Transmit buffer full flag bit
-#define UART_CSR_TXEPT_Pos              (3)
-#define UART_CSR_TXEPT                  (0x01U << UART_CSR_TXEPT_Pos)           ///< Transmit buffer empty flag bit
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_ISR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_ISR_TX_Pos                 (0)
-#define UART_ISR_TX                     (0x01U << UART_ISR_TX_Pos)              ///< Transmit buffer empty interrupt flag bit
-#define UART_ISR_RX_Pos                 (1)
-#define UART_ISR_RX                     (0x01U << UART_ISR_RX_Pos)              ///< Receive valid data interrupt flag bit
-
-#define UART_ISR_TXC_Pos                (2)
-#define UART_ISR_TXC                    (0x01U << UART_ISR_TXC_Pos)             ///< Transmit complete interrupt flag bit
-
-#define UART_ISR_RXOERR_Pos             (3)
-#define UART_ISR_RXOERR                 (0x01U << UART_ISR_RXOERR_Pos)          ///< Receive overflow error interrupt flag bit
-#define UART_ISR_RXPERR_Pos             (4)
-#define UART_ISR_RXPERR                 (0x01U << UART_ISR_RXPERR_Pos)          ///< Parity error interrupt flag bit
-#define UART_ISR_RXFERR_Pos             (5)
-#define UART_ISR_RXFERR                 (0x01U << UART_ISR_RXFERR_Pos)          ///< Frame error interrupt flag bit
-#define UART_ISR_RXBRK_Pos              (6)
-#define UART_ISR_RXBRK                  (0x01U << UART_ISR_RXBRK_Pos)           ///< Receive frame break interrupt flag bit
-
-#define UART_ISR_TXBRK_Pos              (7)
-#define UART_ISR_TXBRK                  (0x01U << UART_ISR_TXBRK_Pos)           ///< Transmit Break Frame Interrupt Flag Bit
-#define UART_ISR_RXB8_Pos               (8)
-#define UART_ISR_RXB8                   (0x01U << UART_ISR_RXB8_Pos)            ///< Receive Bit 8 Interrupt Flag Bit
-
-#define UART_ISR_RXIDLE_Pos             (9)
-#define UART_ISR_RXIDLE                 (0x01U << UART_ISR_RXIDLE_Pos)          ///< Receive Bit 8 Interrupt clear Bit
-#define UART_ISR_ABREND_INTF_Pos         (10)
-#define UART_ISR_ABREND_INTF             (0x01U << UART_ISR_ABREND_INTF_Pos)          ///< Auto baud rate end interrupt flag bit
-#define UART_ISR_ABRERR_INTF_Pos         (11)
-#define UART_ISR_ABRERR_INTF             (0x01U << UART_ISR_ABRERR_INTF_Pos)          ///< Auto baud rate error interrupt flag bit
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_IER Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_IER_TX_Pos                 (0)
-#define UART_IER_TX                     (0x01U << UART_IER_TX_Pos)              ///< Transmit buffer empty interrupt enable bit
-#define UART_IER_RX_Pos                 (1)
-#define UART_IER_RX                     (0x01U << UART_IER_RX_Pos)              ///< Receive buffer interrupt enable bit
-
-#define UART_IER_TXC_Pos                (2)
-#define UART_IER_TXC                    (0x01U << UART_IER_TXC_Pos)             ///< Transmit complete interrupt enable bit
-
-#define UART_IER_RXOERR_Pos             (3)
-#define UART_IER_RXOERR                 (0x01U << UART_IER_RXOERR_Pos)          ///< Receive overflow error interrupt enable bit
-#define UART_IER_RXPERR_Pos             (4)
-#define UART_IER_RXPERR                 (0x01U << UART_IER_RXPERR_Pos)          ///< Parity error interrupt enable bit
-#define UART_IER_RXFERR_Pos             (5)
-#define UART_IER_RXFERR                 (0x01U << UART_IER_RXFERR_Pos)          ///< Frame error interrupt enable bit
-#define UART_IER_RXBRK_Pos              (6)
-#define UART_IER_RXBRK                  (0x01U << UART_IER_RXBRK_Pos)           ///< Receive frame break interrupt enable bit
-
-#define UART_IER_TXBRK_Pos              (7)
-#define UART_IER_TXBRK                  (0x01U << UART_IER_TXBRK_Pos)           ///< Transmit Break Frame Interrupt Enable Bit
-#define UART_IER_RXB8_Pos               (8)
-#define UART_IER_RXB8                   (0x01U << UART_IER_RXB8_Pos)            ///< Receive Bit 8 Interrupt Enable Bit
-
-#define UART_IER_RXIDLE_Pos             (9)
-#define UART_IER_RXIDLE                 (0x01U << UART_IER_RXIDLE_Pos)          ///< Receive Bit 8 Interrupt clear Bit
-#define UART_IER_ABREND_IEN_Pos         (10)
-#define UART_IER_ABREND_IEN             (0x01U << UART_IER_ABREND_IEN_Pos)          ///< Auto baud rate end enable bit
-#define UART_IER_ABRERR_IEN_Pos         (11)
-#define UART_IER_ABRERR_IEN             (0x01U << UART_IER_ABRERR_IEN_Pos)          ///< Auto baud rate error enable bit
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_ICR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define UART_ICR_TX_Pos                 (0)
-#define UART_ICR_TX                     (0x01U << UART_ICR_TX_Pos)              ///< Transmit buffer empty interrupt clear bit
-#define UART_ICR_RX_Pos                 (1)
-#define UART_ICR_RX                     (0x01U << UART_ICR_RX_Pos)              ///< Receive interrupt clear bit
-
-#define UART_ICR_TXC_Pos                (2)
-#define UART_ICR_TXC                    (0x01U << UART_ICR_TXC_Pos)             ///< Transmit complete interrupt clear bit
-
-#define UART_ICR_RXOERR_Pos             (3)
-#define UART_ICR_RXOERR                 (0x01U << UART_ICR_RXOERR_Pos)          ///< Receive overflow error interrupt clear bit
-#define UART_ICR_RXPERR_Pos             (4)
-#define UART_ICR_RXPERR                 (0x01U << UART_ICR_RXPERR_Pos)          ///< Parity error interrupt clear bit
-
-#define UART_ICR_RXFERR_Pos             (5)
-#define UART_ICR_RXFERR                 (0x01U << UART_ICR_RXFERR_Pos)          ///< Frame error interrupt clear bit
-#define UART_ICR_RXBRK_Pos              (6)
-#define UART_ICR_RXBRK                  (0x01U << UART_ICR_RXBRK_Pos)           ///< Receive frame break interrupt clear bit
-
-#define UART_ICR_TXBRK_Pos              (7)
-#define UART_ICR_TXBRK                  (0x01U << UART_ICR_TXBRK_Pos)           ///< Transmit Break Frame Interrupt clear Bit
-#define UART_ICR_RXB8_Pos               (8)
-#define UART_ICR_RXB8                   (0x01U << UART_ICR_RXB8_Pos)            ///< Receive Bit 8 Interrupt clear Bit
-
-#define UART_ICR_RXIDLE_Pos             (9)
-#define UART_ICR_RXIDLE                 (0x01U << UART_ICR_RXIDLE_Pos)          ///< Receive Bit 8 Interrupt clear Bit
-#define UART_ICR_ABRENDCLR_Pos         (10)
-#define UART_ICR_ABRENDCLR             (0x01U << UART_ICR_ABRENDCLR_Pos)          ///< Auto baud rate end clear bit
-#define UART_ICR_ABRERRCLR_Pos         (11)
-#define UART_ICR_ABRERRCLR             (0x01U << UART_ICR_ABRERRCLR_Pos)          ///< Auto baud rate error clear bit
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_GCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_GCR_UART_Pos               (0)
-#define UART_GCR_UART                   (0x01U << UART_GCR_UART_Pos)            ///< UART mode selection bit
-#define UART_GCR_DMA_Pos                (1)
-#define UART_GCR_DMA                    (0x01U << UART_GCR_DMA_Pos)             ///< DMA mode selection bit
-#define UART_GCR_AUTOFLOW_Pos           (2)
-#define UART_GCR_AUTOFLOW               (0x01U << UART_GCR_AUTOFLOW_Pos)        ///< Automatic flow control enable bit
-#define UART_GCR_RX_Pos                 (3)
-#define UART_GCR_RX                     (0x01U << UART_GCR_RX_Pos)              ///< Enable receive
-#define UART_GCR_TX_Pos                 (4)
-#define UART_GCR_TX                     (0x01U << UART_GCR_TX_Pos)              ///< Enable transmit
-
-#define UART_GCR_SELB8_Pos              (7)
-#define UART_GCR_SELB8                  (0x01U << UART_GCR_SELB8_Pos)           ///< UART mode selection bit
-#define UART_GCR_SWAP_Pos               (8)
-#define UART_GCR_SWAP                   (0x01U << UART_GCR_SWAP_Pos)            ///< DMA mode selection bit
-#define UART_GCR_RXTOG_Pos              (9)
-#define UART_GCR_RXTOG                  (0x01U << UART_GCR_RXTOG_Pos)           ///< Automatic flow control enable bit
-#define UART_GCR_TXTOG_Pos              (10)
-#define UART_GCR_TXTOG                  (0x01U << UART_GCR_TXTOG_Pos)           ///< Enable receive
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_CCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_CCR_PEN_Pos                (0)
-#define UART_CCR_PEN                    (0x01U << UART_CCR_PEN_Pos)             ///< Parity enable bit
-#define UART_CCR_PSEL_Pos               (1)
-#define UART_CCR_PSEL                   (0x01U << UART_CCR_PSEL_Pos)            ///< Parity selection bit
-
-#define UART_CCR_SPB_Pos                (2)
-#define UART_CCR_SPB                    (0x01U << UART_CCR_SPB_Pos)             ///< Stop bit selection
-
-
-
-#define UART_CCR_SPB0_Pos               UART_CCR_SPB_Pos
-#define UART_CCR_SPB0                   UART_CCR_SPB                            ///< Stop bit 0 selection
-
-#define UART_CCR_BRK_Pos                (3)
-#define UART_CCR_BRK                    (0x01U << UART_CCR_BRK_Pos)             ///< UART transmit frame break
-#define UART_CCR_CHAR_Pos               (4)
-#define UART_CCR_CHAR                   (0x03U << UART_CCR_CHAR_Pos)            ///< UART width bit
-#define UART_CCR_CHAR_5b                (0x00U << UART_CCR_CHAR_Pos)            ///< UART Word Length 5b
-#define UART_CCR_CHAR_6b                (0x01U << UART_CCR_CHAR_Pos)            ///< UART Word Length 6b
-#define UART_CCR_CHAR_7b                (0x02U << UART_CCR_CHAR_Pos)            ///< UART Word Length 7b
-#define UART_CCR_CHAR_8b                (0x03U << UART_CCR_CHAR_Pos)            ///< UART Word Length 8b
-
-#define UART_CCR_SPB1_Pos               (6)
-#define UART_CCR_SPB1                   (0x01U << UART_CCR_SPB1_Pos)            ///< Stop bit 1 selection
-#define UART_CCR_B8RXD_Pos              (7)
-#define UART_CCR_B8RXD                  (0x01U << UART_CCR_B8RXD_Pos)           ///< Synchronous frame receive
-#define UART_CCR_B8TXD_Pos              (8)
-#define UART_CCR_B8TXD                  (0x01U << UART_CCR_B8TXD_Pos)           ///< Synchronous frame transmit
-#define UART_CCR_B8POL_Pos              (9)
-#define UART_CCR_B8POL                  (0x01U << UART_CCR_B8POL_Pos)           ///< Synchronous frame polarity control bit
-#define UART_CCR_B8TOG_Pos              (10)
-#define UART_CCR_B8TOG                  (0x01U << UART_CCR_B8TOG_Pos)           ///< Synchronous frame auto toggle bit
-#define UART_CCR_B8EN_Pos               (11)
-#define UART_CCR_B8EN                   (0x01U << UART_CCR_B8EN_Pos)            ///< Synchronous frame enable bit
-#define UART_CCR_RWU_Pos                (12)
-#define UART_CCR_RWU                    (0x01U << UART_CCR_RWU_Pos)             ///< Receive wake up method
-#define UART_CCR_WAKE_Pos               (13)
-#define UART_CCR_WAKE                   (0x01U << UART_CCR_WAKE_Pos)            ///< Wake up method
-
-#define UART_CCR_LIN_Pos            (14)
-#define UART_CCR_LIN                (0x01U << UART_CCR_LIN_Pos)             ///< Wake up method
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_BRR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_BRR_MANTISSA_Pos        (0)
-#define UART_BRR_MANTISSA            (0xFFFFU << UART_BRR_MANTISSA_Pos)      ///< UART DIV MANTISSA
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_FRA Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_BRR_FRACTION_Pos        (0)
-#define UART_BRR_FRACTION            (0x0FU << UART_BRR_FRACTION_Pos)        ///< UART DIV FRACTION
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_RXAR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_RXAR_ADDR_Pos          (0)
-#define UART_RXAR_ADDR              (0xFFU << UART_RXAR_ADDR_Pos)           ///< Synchronous frame match address
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_RXMR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_RXMR_MASK_Pos          (0)
-#define UART_RXMR_MASK              (0xFFU << UART_RXMR_MASK_Pos)           ///< Synchronous frame match address mask
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_SCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_SCR_SCEN_Pos           (0)
-#define UART_SCR_SCEN               (0x01U << UART_SCR_SCEN_Pos)            ///< ISO7816 enable bit
-#define UART_SCR_SCARB_Pos          (1)
-#define UART_SCR_SCARB              (0x01U << UART_SCR_SCARB_Pos)           ///< ISO7816 check auto answer bit
-#define UART_SCR_NACK_Pos           (2)
-#define UART_SCR_NACK               (0x01U << UART_SCR_NACK_Pos)            ///< Master receive frame answer bit
-#define UART_SCR_SCFCNT_Pos         (4)
-#define UART_SCR_SCFCNT             (0xFFU << UART_SCR_SCFCNT_Pos)          ///< ISO7816 protection counter bit
-#define UART_SCR_HDSEL_Pos          (12)
-#define UART_SCR_HDSEL              (0x01U << UART_SCR_HDSEL_Pos)           ///< Single-line half-duplex mode selection bit
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_ABRCR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_ABRCR_ABREN_Pos        (0)
-#define UART_ABRCR_ABREN            (0x01U<<UART_ABRCR_ABREN_Pos)
-#define UART_ABRCR_BITCNT_Pos       (1)
-#define UART_ABRCR_BITCNT           (0x03U<<UART_ABRCR_BITCNT_Pos)
-#define UART_ABRCR_BITCNT_MODE0     (0x00U<<UART_ABRCR_BITCNT_Pos)
-#define UART_ABRCR_BITCNT_MODE1     (0x01U<<UART_ABRCR_BITCNT_Pos)
-#define UART_ABRCR_BITCNT_MODE2     (0x02U<<UART_ABRCR_BITCNT_Pos)
-#define UART_ABRCR_BITCNT_MODE3     (0x03U<<UART_ABRCR_BITCNT_Pos)
-#define UART_ABRCR_FORMER_Pos       (3)
-#define UART_ABRCR_FORMER           (0x01U<<UART_ABRCR_FORMER_Pos)
-#define UART_ABRCR_LATTER_Pos       (4)
-#define UART_ABRCR_LATTER           (0x01U<<UART_ABRCR_LATTER_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief UART_IDLR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define UART_IDLR_IDLR_Pos          (0)
-#define UART_IDLR_IDLR              (0xFFFFU << UART_IDLR_IDLR_Pos)         ///< ISO7816 enable bit
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h
deleted file mode 100644
index 9d8c6bf42..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_usb_otg_fs.h
+++ /dev/null
@@ -1,923 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_usb_otg_fs.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_USB_OTG_FS_H
-#define __REG_USB_OTG_FS_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief USB Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define USB_OTG_FS_BASE                        (AHB2PERIPH_BASE + 0x0000)              ///< Base Address: 0x50000000
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief USB Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-
-typedef struct {
-    __IO u32 PER_ID;                                                             ///< Peripheral ID register                         offset: 0x00
-    __IO u32 ID_COMP;                                                            ///< Peripheral ID complement register              offset: 0x04
-    __IO u32 REV;                                                                ///< Peripheral revision register                   offset: 0x08
-    __IO u32 ADD_INFO;                                                           ///< Peripheral additional info register            offset: 0x0C
-    __IO u32 OTG_ISTAT;                                                          ///< OTG Interrupt Status Register                  offset: 0x10
-    __IO u32 OTG_ICTRL;                                                          ///< OTG Interrupt Control Register                 offset: 0x14
-    __IO u32 OTG_STAT;                                                           ///< OTG Status Register                            offset: 0x18
-    __IO u32 OTG_CTRL;                                                           ///< OTG Control register                           offset: 0x1C
-    __IO u32 RESERVED0[24];                                                      ///< Reserved                                       offset: 0x20
-    __IO u32 INT_STAT;                                                           ///< Interrupt status register                      offset: 0x80
-    __IO u32 INT_ENB;                                                            ///< Interrupt enable register                      offset: 0x84
-    __IO u32 ERR_STAT;                                                           ///< Error interrupt status register                offset: 0x88
-    __IO u32 ERR_ENB;                                                            ///< Error interrupt enable register                offset: 0x8C
-    __IO u32 STAT;                                                               ///< Status register                                offset: 0x90
-    __IO u32 CTL;                                                                ///< Control register                               offset: 0x94
-    __IO u32 ADDR;                                                               ///< Address register                               offset: 0x98
-    __IO u32 BDT_PAGE_01;                                                        ///< BDT page register 1                            offset: 0x9C
-    __IO u32 FRM_NUML;                                                           ///< Frame number register                          offset: 0xA0
-    __IO u32 FRM_NUMH;                                                           ///< Frame number register                          offset: 0xA4
-    __IO u32 TOKEN;                                                              ///< Token register                                 offset: 0xA8
-    __IO u32 SOF_THLD;                                                           ///< SOF threshold register                         offset: 0xAC
-    __IO u32 BDT_PAGE_02;                                                        ///< BDT page register 2                            offset: 0xB0
-    __IO u32 BDT_PAGE_03;                                                        ///< BDT page register 3                            offset: 0xB4
-    __IO u32 RESERVED1;                                                          ///< Reserved                                       offset: 0xB8
-    __IO u32 RESERVED2;                                                          ///< Reserved                                       offset: 0xBC
-    __IO u32 EP_CTL[16];                                                         ///< Endpoint control register                      offset: 0xC0
-} USB_OTG_FS_TypeDef;
-////////////////////////////////////////////////////////////////////////////////
-/// @brief USBD type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define USB_OTG_FS                             ((USB_OTG_FS_TypeDef*) USB_OTG_FS_BASE )
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_PER_ID Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_PER_ID_ID_Pos                    (0)
-#define OTG_FS_PER_ID_ID                        (0x3FU << OTG_FS_PER_ID_ID_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_ID_COMP Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_ID_COMP_NID_Pos                  (0)
-#define OTG_FS_ID_COMP_NID                      (0x3FU << OTG_FS_ID_COMP_NID_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_REV Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_REV_REV_Pos                      (0)
-#define OTG_FS_REV_REV                          (0xFFU << OTG_FS_REV_REV_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_ADD_INFO Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_ADD_INFO_HOST_Pos                (0)
-#define OTG_FS_ADD_INFO_HOST                    (0x01U << OTG_FS_ADD_INFO_HOST_Pos)
-#define OTG_FS_ADD_INFO_IRQ_NUM_Pos             (3)
-#define OTG_FS_ADD_INFO_IRQ_NUM                 (0x1FU << OTG_FS_ADD_INFO_IRQ_NUM_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_OTG_ISTAT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos     (0)
-#define OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG         (0x01U << OTG_FS_OTG_ISTAT_A_VBUS_VLD_CHG_Pos)
-#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos     (2)
-#define OTG_FS_OTG_ISTAT_B_SESS_END_CHG         (0x01U << OTG_FS_OTG_ISTAT_B_SESS_END_CHG_Pos)
-#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos       (3)
-#define OTG_FS_OTG_ISTAT_SESS_VLD_CHG           (0x01U << OTG_FS_OTG_ISTAT_SESS_VLD_CHG_Pos)
-#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos     (5)
-#define OTG_FS_OTG_ISTAT_LINE_STATE_CHG         (0x01U << OTG_FS_OTG_ISTAT_LINE_STATE_CHG_Pos)
-#define OTG_FS_OTG_ISTAT_1_MSEC_Pos             (6)
-#define OTG_FS_OTG_ISTAT_1_MSEC                 (0x01U << OTG_FS_OTG_ISTAT_1_MSEC_Pos)
-#define OTG_FS_OTG_ISTAT_ID_CHG_Pos             (7)
-#define OTG_FS_OTG_ISTAT_ID_CHG                 (0x01U << OTG_FS_OTG_ISTAT_ID_CHG_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_OTG_ICTRL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos      (0)
-#define OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN          (0x01U << OTG_FS_OTG_ICTRL_A_VBUS_VLD_EN_Pos)
-#define OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos      (2)
-#define OTG_FS_OTG_ICTRL_B_SESS_END_EN          (0x01U << OTG_FS_OTG_ICTRL_B_SESS_END_EN_Pos)
-#define OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos        (3)
-#define OTG_FS_OTG_ICTRL_SESS_VLD_EN            (0x01U << OTG_FS_OTG_ICTRL_SESS_VLD_EN_Pos)
-#define OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos      (5)
-#define OTG_FS_OTG_ICTRL_LINE_STATE_EN          (0x01U << OTG_FS_OTG_ICTRL_LINE_STATE_EN_Pos)
-#define OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos          (6)
-#define OTG_FS_OTG_ICTRL_1_MSEC_EN              (0x01U << OTG_FS_OTG_ICTRL_1_MSEC_EN_Pos)
-#define OTG_FS_OTG_ICTRL_ID_EN_Pos              (7)
-#define OTG_FS_OTG_ICTRL_ID_EN                  (0x01U << OTG_FS_OTG_ICTRL_ID_EN_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_OTG_STAT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_OTG_STAT_A_VBUS_VLD_Pos          (0)
-#define OTG_FS_OTG_STAT_A_VBUS_VLD              (0x01U << OTG_FS_OTG_STAT_A_VBUS_VLD_Pos)
-#define OTG_FS_OTG_STAT_B_SESS_END_Pos          (2)
-#define OTG_FS_OTG_STAT_B_SESS_END              (0x01U << OTG_FS_OTG_STAT_B_SESS_END_Pos)
-#define OTG_FS_OTG_STAT_SESS_VLD_Pos            (3)
-#define OTG_FS_OTG_STAT_SESS_VLD                (0x01U << OTG_FS_OTG_STAT_SESS_VLD_Pos)
-#define OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos   (5)
-#define OTG_FS_OTG_STAT_LINE_STATE_STABLE       (0x01U << OTG_FS_OTG_STAT_LINE_STATE_STABLE_Pos)
-#define OTG_FS_OTG_STAT_1_MSEC_Pos              (6)
-#define OTG_FS_OTG_STAT_1_MSEC                  (0x01U << OTG_FS_OTG_STAT_1_MSEC_Pos)
-#define OTG_FS_OTG_STAT_ID_Pos                  (7)
-#define OTG_FS_OTG_STAT_ID                      (0x01U << OTG_FS_OTG_STAT_ID_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_OTG_CTRL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos          (0)
-#define OTG_FS_OTG_CTRL_VBUS_DSCHG              (0x01U << OTG_FS_OTG_CTRL_VBUS_DSCHG_Pos)
-#define OTG_FS_OTG_CTRL_VBUS_CHG_Pos            (1)
-#define OTG_FS_OTG_CTRL_VBUS_CHG                (0x01U << OTG_FS_OTG_CTRL_VBUS_CHG_Pos)
-#define OTG_FS_OTG_CTRL_OTG_EN_Pos              (2)
-#define OTG_FS_OTG_CTRL_OTG_EN                  (0x01U << OTG_FS_OTG_CTRL_OTG_EN_Pos)
-#define OTG_FS_OTG_CTRL_VBUS_ON_Pos             (3)
-#define OTG_FS_OTG_CTRL_VBUS_ON                 (0x01U << OTG_FS_OTG_CTRL_VBUS_ON_Pos)
-#define OTG_FS_OTG_CTRL_DM_LOW_Pos              (4)
-#define OTG_FS_OTG_CTRL_DM_LOW                  (0x01U << OTG_FS_OTG_CTRL_DM_LOW_Pos)
-#define OTG_FS_OTG_CTRL_DP_LOW_Pos              (5)
-#define OTG_FS_OTG_CTRL_DP_LOW                  (0x01U << OTG_FS_OTG_CTRL_DP_LOW_Pos)
-#define OTG_FS_OTG_CTRL_DM_HIGH_Pos             (6)
-#define OTG_FS_OTG_CTRL_DM_HIGH                 (0x01U << OTG_FS_OTG_CTRL_DM_HIGH_Pos)
-#define OTG_FS_OTG_CTRL_DP_HIGH_Pos             (7)
-#define OTG_FS_OTG_CTRL_DP_HIGH                 (0x01U << OTG_FS_OTG_CTRL_DP_HIGH_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_INT_STAT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_INT_STAT_USB_RST_Pos             (0)
-#define OTG_FS_INT_STAT_USB_RST                 (0x01U << OTG_FS_INT_STAT_USB_RST_Pos)
-#define OTG_FS_INT_STAT_ERROR_Pos               (1)
-#define OTG_FS_INT_STAT_ERROR                   (0x01U << OTG_FS_INT_STAT_ERROR_Pos)
-#define OTG_FS_INT_STAT_SOF_TOK_Pos             (2)
-#define OTG_FS_INT_STAT_SOF_TOK                 (0x01U << OTG_FS_INT_STAT_SOF_TOK_Pos)
-#define OTG_FS_INT_STAT_TOK_DNE_Pos             (3)
-#define OTG_FS_INT_STAT_TOK_DNE                 (0x01U << OTG_FS_INT_STAT_TOK_DNE_Pos)
-#define OTG_FS_INT_STAT_SLEEP_Pos               (4)
-#define OTG_FS_INT_STAT_SLEEP                   (0x01U << OTG_FS_INT_STAT_SLEEP_Pos)
-#define OTG_FS_INT_STAT_RESUME_Pos              (5)
-#define OTG_FS_INT_STAT_RESUME                  (0x01U << OTG_FS_INT_STAT_RESUME_Pos)
-#define OTG_FS_INT_STAT_ATTACH_Pos              (6)
-#define OTG_FS_INT_STAT_ATTACH                  (0x01U << OTG_FS_INT_STAT_ATTACH_Pos)
-#define OTG_FS_INT_STAT_STALL_Pos               (7)
-#define OTG_FS_INT_STAT_STALL                   (0x01U << OTG_FS_INT_STAT_STALL_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_INT_ENB Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_INT_ENB_USB_RST_EN_Pos           (0)
-#define OTG_FS_INT_ENB_USB_RST_EN               (0x01U << OTG_FS_INT_ENB_USB_RST_EN_Pos)
-#define OTG_FS_INT_ENB_ERROR_EN_Pos             (1)
-#define OTG_FS_INT_ENB_ERROR_EN                 (0x01U << OTG_FS_INT_ENB_ERROR_EN_Pos)
-#define OTG_FS_INT_ENB_SOF_TOK_EN_Pos           (2)
-#define OTG_FS_INT_ENB_SOF_TOK_EN               (0x01U << OTG_FS_INT_ENB_SOF_TOK_EN_Pos)
-#define OTG_FS_INT_ENB_TOK_DNE_EN_Pos           (3)
-#define OTG_FS_INT_ENB_TOK_DNE_EN               (0x01U << OTG_FS_INT_ENB_TOK_DNE_EN_Pos)
-#define OTG_FS_INT_ENB_SLEEP_EN_Pos             (4)
-#define OTG_FS_INT_ENB_SLEEP_EN                 (0x01U << OTG_FS_INT_ENB_SLEEP_EN_Pos)
-#define OTG_FS_INT_ENB_RESUME_EN_Pos            (5)
-#define OTG_FS_INT_ENB_RESUME_EN                (0x01U << OTG_FS_INT_ENB_RESUME_EN_Pos)
-#define OTG_FS_INT_ENB_ATTACH_EN_Pos            (6)
-#define OTG_FS_INT_ENB_ATTACH_EN                (0x01U << OTG_FS_INT_ENB_ATTACH_EN_Pos)
-#define OTG_FS_INT_ENB_STALL_EN_Pos             (7)
-#define OTG_FS_INT_ENB_STALL_EN                 (0x01U << OTG_FS_INT_ENB_STALL_EN_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_ERR_STAT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_ERR_STAT_PID_ERR_Pos             (0)
-#define OTG_FS_ERR_STAT_PID_ERR                 (0x01U << OTG_FS_ERR_STAT_PID_ERR_Pos)
-#define OTG_FS_ERR_STAT_CRC5_EOF_Pos            (1)
-#define OTG_FS_ERR_STAT_CRC5_EOF                (0x01U << OTG_FS_ERR_STAT_CRC5_EOF_Pos)
-#define OTG_FS_ERR_STAT_CRC16_Pos               (2)
-#define OTG_FS_ERR_STAT_CRC16                   (0x01U << OTG_FS_ERR_STAT_CRC16_Pos)
-#define OTG_FS_ERR_STAT_DFN8_Pos                (3)
-#define OTG_FS_ERR_STAT_DFN8                    (0x01U << OTG_FS_ERR_STAT_DFN8_Pos)
-#define OTG_FS_ERR_STAT_BTO_ERR_Pos             (4)
-#define OTG_FS_ERR_STAT_BTO_ERR                 (0x01U << OTG_FS_ERR_STAT_BTO_ERR_Pos)
-#define OTG_FS_ERR_STAT_DMA_ERR_Pos             (5)
-#define OTG_FS_ERR_STAT_DMA_ERR                 (0x01U << OTG_FS_ERR_STAT_DMA_ERR_Pos)
-#define OTG_FS_ERR_STAT_BTS_ERR_Pos             (7)
-#define OTG_FS_ERR_STAT_BTS_ERR                 (0x01U << OTG_FS_ERR_STAT_BTS_ERR_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_ERR_ENB Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_ERR_ENB_PID_ERR_EN_Pos           (0)
-#define OTG_FS_ERR_ENB_PID_ERR_EN               (0x01U << OTG_FS_ERR_ENB_PID_ERR_EN_Pos)
-#define OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos          (1)
-#define OTG_FS_ERR_ENB_CRC5_EOF_EN              (0x01U << OTG_FS_ERR_ENB_CRC5_EOF_EN_Pos)
-#define OTG_FS_ERR_ENB_CRC16_EN_Pos             (2)
-#define OTG_FS_ERR_ENB_CRC16_EN                 (0x01U << OTG_FS_ERR_ENB_CRC16_EN_Pos)
-#define OTG_FS_ERR_ENB_DFN8_EN_Pos              (3)
-#define OTG_FS_ERR_ENB_DFN8_EN                  (0x01U << OTG_FS_ERR_ENB_DFN8_EN_Pos)
-#define OTG_FS_ERR_ENB_BTO_ERR_EN_Pos           (4)
-#define OTG_FS_ERR_ENB_BTO_ERR_EN               (0x01U << OTG_FS_ERR_ENB_BTO_ERR_EN_Pos)
-#define OTG_FS_ERR_ENB_DMA_ERR_EN_Pos           (5)
-#define OTG_FS_ERR_ENB_DMA_ERR_EN               (0x01U << OTG_FS_ERR_ENB_DMA_ERR_EN_Pos)
-#define OTG_FS_ERR_ENB_BTS_ERR_EN_Pos           (7)
-#define OTG_FS_ERR_ENB_BTS_ERR_EN               (0x01U << OTG_FS_ERR_ENB_BTS_ERR_EN_Pos)
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_STAT Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_STAT_ODD_Pos                     (2)
-#define OTG_FS_STAT_ODD                         (0x01U << OTG_FS_STAT_ODD_Pos)
-#define OTG_FS_STAT_TX_Pos                      (3)
-#define OTG_FS_STAT_TX                          (0x01U << OTG_FS_STAT_TX_Pos)
-#define OTG_FS_STAT_ENDP_Pos                    (4)
-#define OTG_FS_STAT_ENDP                        (0x0FU << OTG_FS_STAT_ENDP_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_CTL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_CTL_USB_EN_SOF_EN_Pos            (0)
-#define OTG_FS_CTL_USB_EN_SOF_EN                (0x01U << OTG_FS_CTL_USB_EN_SOF_EN_Pos)
-#define OTG_FS_CTL_ODD_RST_Pos                  (1)
-#define OTG_FS_CTL_ODD_RST                      (0x01U << OTG_FS_CTL_ODD_RST_Pos)
-#define OTG_FS_CTL_RESUME_Pos                   (2)
-#define OTG_FS_CTL_RESUME                       (0x01U << OTG_FS_CTL_RESUME_Pos)
-#define OTG_FS_CTL_HOST_MODE_EN_Pos             (3)
-#define OTG_FS_CTL_HOST_MODE_EN                 (0x01U << OTG_FS_CTL_HOST_MODE_EN_Pos)
-#define OTG_FS_CTL_RESET_Pos                    (4)
-#define OTG_FS_CTL_RESET                        (0x01U << OTG_FS_CTL_RESET_Pos)
-#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos     (5)
-#define OTG_FS_CTL_TXDSUSPEND_TOKENBUSY         (0x01U << OTG_FS_CTL_TXDSUSPEND_TOKENBUSY_Pos)
-#define OTG_FS_CTL_SE0_Pos                      (6)
-#define OTG_FS_CTL_SE0                          (0x01U << OTG_FS_CTL_SE0_Pos)
-#define OTG_FS_CTL_JSTATE_Pos                   (7)
-#define OTG_FS_CTL_JSTATE                       (0x01U << OTG_FS_CTL_JSTATE_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_ADDR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_ADDR_ADDR_Pos                    (0)
-#define OTG_FS_ADDR_ADDR                        (0x7FU << OTG_FS_ADDR_ADDR_Pos)
-#define OTG_FS_ADDR_LS_EN_Pos                   (7)
-#define OTG_FS_ADDR_LS_EN                       (0x01U << OTG_FS_ADDR_LS_EN_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_BDT_PAGE_01 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos      (1)
-#define OTG_FS_BDT_PAGE_01_BDT_BA_15_9          (0x7FU << OTG_FS_BDT_PAGE_01_BDT_BA_15_9_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_FRM_NUML Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_FRM_NUML_FRM_Pos                 (0)
-#define OTG_FS_FRM_NUML_FRM                     (0xFFU << OTG_FS_FRM_NUML_FRM_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_FRM_NUMH Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_FRM_NUMH_FRM_Pos                 (0)
-#define OTG_FS_FRM_NUMH_FRM                     (0x07U << OTG_FS_FRM_NUMH_FRM_Pos)
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_TOKEN Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_TOKEN_TOKEN_ENDPT_Pos            (0)
-#define OTG_FS_TOKEN_TOKEN_ENDPT                (0x0FU << OTG_FS_TOKEN_TOKEN_ENDPT_Pos)
-#define OTG_FS_TOKEN_TOKEN_PID_Pos              (4)
-#define OTG_FS_TOKEN_TOKEN_PID                  (0x0FU << OTG_FS_TOKEN_TOKEN_PID_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_SOF_THLD Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_SOF_THLD_CNT_Pos                 (0)
-#define OTG_FS_SOF_THLD_CNT                     (0xFFU << OTG_FS_SOF_THLD_CNT_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_BDT_PAGE_02 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos     (0)
-#define OTG_FS_BDT_PAGE_02_BDT_BA_23_16         (0xFFU << OTG_FS_BDT_PAGE_02_BDT_BA_23_16_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_BDT_PAGE_03 Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos     (0)
-#define OTG_FS_BDT_PAGE_03_BDT_BA_31_24         (0xFFU << OTG_FS_BDT_PAGE_03_BDT_BA_31_24_Pos)
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS_EP_CTL Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define OTG_FS_EP_CTL_EP_HSHK_Pos               (0)
-#define OTG_FS_EP_CTL_EP_HSHK                   (0x01U << OTG_FS_EP_CTL_EP_HSHK_Pos)
-#define OTG_FS_EP_CTL_EP_STALL_Pos              (1)
-#define OTG_FS_EP_CTL_EP_STALL                  (0x01U << OTG_FS_EP_CTL_EP_STALL_Pos)
-#define OTG_FS_EP_CTL_EP_TX_EN_Pos              (2)
-#define OTG_FS_EP_CTL_EP_TX_EN                  (0x01U << OTG_FS_EP_CTL_EP_TX_EN_Pos)
-#define OTG_FS_EP_CTL_EP_RX_EN_Pos              (3)
-#define OTG_FS_EP_CTL_EP_RX_EN                  (0x01U << OTG_FS_EP_CTL_EP_RX_EN_Pos)
-#define OTG_FS_EP_CTL_EP_CTL_DIS_Pos            (4)
-#define OTG_FS_EP_CTL_EP_CTL_DIS                (0x01U << OTG_FS_EP_CTL_EP_CTL_DIS_Pos)
-#define OTG_FS_EP_CTL_RETRY_DIS_Pos             (6)
-#define OTG_FS_EP_CTL_RETRY_DIS                 (0x01U << OTG_FS_EP_CTL_RETRY_DIS_Pos)
-#define OTG_FS_EP_CTL_HOST_WO_HUB_Pos           (7)
-#define OTG_FS_EP_CTL_HOST_WO_HUB               (0x01U << OTG_FS_EP_CTL_HOST_WO_HUB_Pos)
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief OTG_FS Buffer Descriptor Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-
-#define OTG_FS_BD_TOK_PID_Pos                   (2)
-#define OTG_FS_BD_TOK_PID                       (0x0FU << OTG_FS_BD_TOK_PID_Pos)
-#define OTG_FS_BD_DATA01_Pos                    (6)
-#define OTG_FS_BD_DATA01                        (0x01U << OTG_FS_BD_DATA01_Pos)
-#define OTG_FS_BD_OWN_Pos                       (7)
-#define OTG_FS_BD_OWN                           (0x01U << OTG_FS_BD_OWN_Pos)
-#define OTG_FS_BD_BC_Pos                        (16)
-#define OTG_FS_BD_BC                            (0x3FFU << OTG_FS_BD_BC_Pos)
-#define OTG_FS_BD_ADDRESS_Pos                   (0)
-#define OTG_FS_BD_ADDRESS                       (0xFFFFFFFFU << OTG_FS_BD_ADDRESS_Pos)
-
-
-
-/**
-* @}
-*/
-//#define OTG_FS_INT_STAT_RST         ((uint32_t)0x01)
-//#define OTG_FS_INT_STAT_ERROR       ((uint32_t)0x02)
-//#define OTG_FS_INT_STAT_SOF         ((uint32_t)0x04)
-//#define OTG_FS_INT_STAT_DNE         ((uint32_t)0x08)
-//#define OTG_FS_INT_STAT_SLEEP       ((uint32_t)0x10)
-//#define OTG_FS_INT_STAT_RESUME      ((uint32_t)0x20)
-//#define OTG_FS_INT_STAT_ATTACH      ((uint32_t)0x40)
-//#define OTG_FS_INT_STAT_STALL       ((uint32_t)0x80)
-
-//TEMP
-#define  USB_INT_STAT_RST       0x01
-#define  USB_INT_STAT_ERROR     0x02
-#define  USB_INT_STAT_SOF_TOK   0x04
-#define  USB_INT_STAT_TOK_DNE   0x08
-#define  USB_INT_STAT_SLEEP     0x10
-#define  USB_INT_STAT_RESUME    0x20
-#define  USB_INT_STAT_ATTACH    0x40
-#define  USB_INT_STAT_STALL     0x80
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-/*! @name PERID - Peripheral ID register */
-#define USB_PERID_ID_MASK                        (0x3FU)
-#define USB_PERID_ID_SHIFT                       (0U)
-#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
-
-/*! @name IDCOMP - Peripheral ID Complement register */
-#define USB_IDCOMP_NID_MASK                      (0x3FU)
-#define USB_IDCOMP_NID_SHIFT                     (0U)
-#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
-
-/*! @name REV - Peripheral Revision register */
-#define USB_REV_REV_MASK                         (0xFFU)
-#define USB_REV_REV_SHIFT                        (0U)
-#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
-
-/*! @name ADDINFO - Peripheral Additional Info register */
-#define USB_ADDINFO_IEHOST_MASK                  (0x1U)
-#define USB_ADDINFO_IEHOST_SHIFT                 (0U)
-#define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
-
-/*! @name OTGISTAT - OTG Interrupt Status register */
-#define USB_OTGISTAT_LINE_STATE_CHG_MASK         (0x20U)
-#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        (5U)
-#define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
-#define USB_OTGISTAT_ONEMSEC_MASK                (0x40U)
-#define USB_OTGISTAT_ONEMSEC_SHIFT               (6U)
-#define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
-
-/*! @name OTGICR - OTG Interrupt Control register */
-#define USB_OTGICR_LINESTATEEN_MASK              (0x20U)
-#define USB_OTGICR_LINESTATEEN_SHIFT             (5U)
-#define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
-#define USB_OTGICR_ONEMSECEN_MASK                (0x40U)
-#define USB_OTGICR_ONEMSECEN_SHIFT               (6U)
-#define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
-
-/*! @name OTGSTAT - OTG Status register */
-#define USB_OTGSTAT_LINESTATESTABLE_MASK         (0x20U)
-#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        (5U)
-#define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
-#define USB_OTGSTAT_ONEMSECEN_MASK               (0x40U)
-#define USB_OTGSTAT_ONEMSECEN_SHIFT              (6U)
-#define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
-
-/*! @name OTGCTL - OTG Control register */
-#define USB_OTGCTL_OTGEN_MASK                    (0x4U)
-#define USB_OTGCTL_OTGEN_SHIFT                   (2U)
-#define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
-#define USB_OTGCTL_DMLOW_MASK                    (0x10U)
-#define USB_OTGCTL_DMLOW_SHIFT                   (4U)
-#define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
-#define USB_OTGCTL_DPLOW_MASK                    (0x20U)
-#define USB_OTGCTL_DPLOW_SHIFT                   (5U)
-#define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
-#define USB_OTGCTL_DPHIGH_MASK                   (0x80U)
-#define USB_OTGCTL_DPHIGH_SHIFT                  (7U)
-#define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
-
-/*! @name ISTAT - Interrupt Status register */
-#define USB_ISTAT_USBRST_MASK                    (0x1U)
-#define USB_ISTAT_USBRST_SHIFT                   (0U)
-#define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
-#define USB_ISTAT_ERROR_MASK                     (0x2U)
-#define USB_ISTAT_ERROR_SHIFT                    (1U)
-#define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
-#define USB_ISTAT_SOFTOK_MASK                    (0x4U)
-#define USB_ISTAT_SOFTOK_SHIFT                   (2U)
-#define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
-#define USB_ISTAT_TOKDNE_MASK                    (0x8U)
-#define USB_ISTAT_TOKDNE_SHIFT                   (3U)
-#define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
-#define USB_ISTAT_SLEEP_MASK                     (0x10U)
-#define USB_ISTAT_SLEEP_SHIFT                    (4U)
-#define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
-#define USB_ISTAT_RESUME_MASK                    (0x20U)
-#define USB_ISTAT_RESUME_SHIFT                   (5U)
-#define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
-#define USB_ISTAT_ATTACH_MASK                    (0x40U)
-#define USB_ISTAT_ATTACH_SHIFT                   (6U)
-#define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
-#define USB_ISTAT_STALL_MASK                     (0x80U)
-#define USB_ISTAT_STALL_SHIFT                    (7U)
-#define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
-
-/*! @name INTEN - Interrupt Enable register */
-#define USB_INTEN_USBRSTEN_MASK                  (0x1U)
-#define USB_INTEN_USBRSTEN_SHIFT                 (0U)
-#define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
-#define USB_INTEN_ERROREN_MASK                   (0x2U)
-#define USB_INTEN_ERROREN_SHIFT                  (1U)
-#define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
-#define USB_INTEN_SOFTOKEN_MASK                  (0x4U)
-#define USB_INTEN_SOFTOKEN_SHIFT                 (2U)
-#define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
-#define USB_INTEN_TOKDNEEN_MASK                  (0x8U)
-#define USB_INTEN_TOKDNEEN_SHIFT                 (3U)
-#define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
-#define USB_INTEN_SLEEPEN_MASK                   (0x10U)
-#define USB_INTEN_SLEEPEN_SHIFT                  (4U)
-#define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
-#define USB_INTEN_RESUMEEN_MASK                  (0x20U)
-#define USB_INTEN_RESUMEEN_SHIFT                 (5U)
-#define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
-#define USB_INTEN_ATTACHEN_MASK                  (0x40U)
-#define USB_INTEN_ATTACHEN_SHIFT                 (6U)
-#define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
-#define USB_INTEN_STALLEN_MASK                   (0x80U)
-#define USB_INTEN_STALLEN_SHIFT                  (7U)
-#define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
-
-/*! @name ERRSTAT - Error Interrupt Status register */
-#define USB_ERRSTAT_PIDERR_MASK                  (0x1U)
-#define USB_ERRSTAT_PIDERR_SHIFT                 (0U)
-#define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
-#define USB_ERRSTAT_CRC5EOF_MASK                 (0x2U)
-#define USB_ERRSTAT_CRC5EOF_SHIFT                (1U)
-#define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
-#define USB_ERRSTAT_CRC16_MASK                   (0x4U)
-#define USB_ERRSTAT_CRC16_SHIFT                  (2U)
-#define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
-#define USB_ERRSTAT_DFN8_MASK                    (0x8U)
-#define USB_ERRSTAT_DFN8_SHIFT                   (3U)
-#define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
-#define USB_ERRSTAT_BTOERR_MASK                  (0x10U)
-#define USB_ERRSTAT_BTOERR_SHIFT                 (4U)
-#define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
-#define USB_ERRSTAT_DMAERR_MASK                  (0x20U)
-#define USB_ERRSTAT_DMAERR_SHIFT                 (5U)
-#define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
-#define USB_ERRSTAT_OWNERR_MASK                  (0x40U)
-#define USB_ERRSTAT_OWNERR_SHIFT                 (6U)
-#define USB_ERRSTAT_OWNERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
-#define USB_ERRSTAT_BTSERR_MASK                  (0x80U)
-#define USB_ERRSTAT_BTSERR_SHIFT                 (7U)
-#define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
-
-/*! @name ERREN - Error Interrupt Enable register */
-#define USB_ERREN_PIDERREN_MASK                  (0x1U)
-#define USB_ERREN_PIDERREN_SHIFT                 (0U)
-#define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
-#define USB_ERREN_CRC5EOFEN_MASK                 (0x2U)
-#define USB_ERREN_CRC5EOFEN_SHIFT                (1U)
-#define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
-#define USB_ERREN_CRC16EN_MASK                   (0x4U)
-#define USB_ERREN_CRC16EN_SHIFT                  (2U)
-#define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
-#define USB_ERREN_DFN8EN_MASK                    (0x8U)
-#define USB_ERREN_DFN8EN_SHIFT                   (3U)
-#define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
-#define USB_ERREN_BTOERREN_MASK                  (0x10U)
-#define USB_ERREN_BTOERREN_SHIFT                 (4U)
-#define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
-#define USB_ERREN_DMAERREN_MASK                  (0x20U)
-#define USB_ERREN_DMAERREN_SHIFT                 (5U)
-#define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
-#define USB_ERREN_OWNERREN_MASK                  (0x40U)
-#define USB_ERREN_OWNERREN_SHIFT                 (6U)
-#define USB_ERREN_OWNERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
-#define USB_ERREN_BTSERREN_MASK                  (0x80U)
-#define USB_ERREN_BTSERREN_SHIFT                 (7U)
-#define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
-
-/*! @name STAT - Status register */
-#define USB_STAT_ODD_MASK                        (0x4U)
-#define USB_STAT_ODD_SHIFT                       (2U)
-#define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
-#define USB_STAT_TX_MASK                         (0x8U)
-#define USB_STAT_TX_SHIFT                        (3U)
-#define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
-#define USB_STAT_ENDP_MASK                       (0xF0U)
-#define USB_STAT_ENDP_SHIFT                      (4U)
-#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
-
-/*! @name CTL - Control register */
-#define USB_CTL_USBENSOFEN_MASK                  (0x1U)
-#define USB_CTL_USBENSOFEN_SHIFT                 (0U)
-#define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
-#define USB_CTL_ODDRST_MASK                      (0x2U)
-#define USB_CTL_ODDRST_SHIFT                     (1U)
-#define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
-#define USB_CTL_RESUME_MASK                      (0x4U)
-#define USB_CTL_RESUME_SHIFT                     (2U)
-#define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
-#define USB_CTL_HOSTMODEEN_MASK                  (0x8U)
-#define USB_CTL_HOSTMODEEN_SHIFT                 (3U)
-#define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
-#define USB_CTL_RESET_MASK                       (0x10U)
-#define USB_CTL_RESET_SHIFT                      (4U)
-#define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
-#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          (0x20U)
-#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         (5U)
-#define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
-#define USB_CTL_SE0_MASK                         (0x40U)
-#define USB_CTL_SE0_SHIFT                        (6U)
-#define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
-#define USB_CTL_JSTATE_MASK                      (0x80U)
-#define USB_CTL_JSTATE_SHIFT                     (7U)
-#define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
-
-/*! @name ADDR - Address register */
-#define USB_ADDR_ADDR_MASK                       (0x7FU)
-#define USB_ADDR_ADDR_SHIFT                      (0U)
-#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
-#define USB_ADDR_LSEN_MASK                       (0x80U)
-#define USB_ADDR_LSEN_SHIFT                      (7U)
-#define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
-
-/*! @name BDTPAGE1 - BDT Page register 1 */
-#define USB_BDTPAGE1_BDTBA_MASK                  (0xFEU)
-#define USB_BDTPAGE1_BDTBA_SHIFT                 (1U)
-#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
-
-/*! @name FRMNUML - Frame Number register Low */
-#define USB_FRMNUML_FRM_MASK                     (0xFFU)
-#define USB_FRMNUML_FRM_SHIFT                    (0U)
-#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
-
-/*! @name FRMNUMH - Frame Number register High */
-#define USB_FRMNUMH_FRM_MASK                     (0x7U)
-#define USB_FRMNUMH_FRM_SHIFT                    (0U)
-#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
-
-/*! @name TOKEN - Token register */
-#define USB_TOKEN_TOKENENDPT_MASK                (0xFU)
-#define USB_TOKEN_TOKENENDPT_SHIFT               (0U)
-#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
-#define USB_TOKEN_TOKENPID_MASK                  (0xF0U)
-#define USB_TOKEN_TOKENPID_SHIFT                 (4U)
-#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
-
-/*! @name SOFTHLD - SOF Threshold register */
-#define USB_SOFTHLD_CNT_MASK                     (0xFFU)
-#define USB_SOFTHLD_CNT_SHIFT                    (0U)
-#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
-
-/*! @name BDTPAGE2 - BDT Page Register 2 */
-#define USB_BDTPAGE2_BDTBA_MASK                  (0xFFU)
-#define USB_BDTPAGE2_BDTBA_SHIFT                 (0U)
-#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
-
-/*! @name BDTPAGE3 - BDT Page Register 3 */
-#define USB_BDTPAGE3_BDTBA_MASK                  (0xFFU)
-#define USB_BDTPAGE3_BDTBA_SHIFT                 (0U)
-#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
-
-/*! @name ENDPT - Endpoint Control register */
-#define USB_ENDPT_EPHSHK_MASK                    (0x1U)
-#define USB_ENDPT_EPHSHK_SHIFT                   (0U)
-#define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
-#define USB_ENDPT_EPSTALL_MASK                   (0x2U)
-#define USB_ENDPT_EPSTALL_SHIFT                  (1U)
-#define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
-#define USB_ENDPT_EPTXEN_MASK                    (0x4U)
-#define USB_ENDPT_EPTXEN_SHIFT                   (2U)
-#define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
-#define USB_ENDPT_EPRXEN_MASK                    (0x8U)
-#define USB_ENDPT_EPRXEN_SHIFT                   (3U)
-#define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
-#define USB_ENDPT_EPCTLDIS_MASK                  (0x10U)
-#define USB_ENDPT_EPCTLDIS_SHIFT                 (4U)
-#define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
-#define USB_ENDPT_RETRYDIS_MASK                  (0x40U)
-#define USB_ENDPT_RETRYDIS_SHIFT                 (6U)
-#define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
-#define USB_ENDPT_HOSTWOHUB_MASK                 (0x80U)
-#define USB_ENDPT_HOSTWOHUB_SHIFT                (7U)
-#define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
-
-/* The count of USB_ENDPT */
-#define USB_ENDPT_COUNT                          (16U)
-
-/*! @name USBCTRL - USB Control register */
-#define USB_USBCTRL_UARTSEL_MASK                 (0x10U)
-#define USB_USBCTRL_UARTSEL_SHIFT                (4U)
-#define USB_USBCTRL_UARTSEL(x)                   (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
-#define USB_USBCTRL_UARTCHLS_MASK                (0x20U)
-#define USB_USBCTRL_UARTCHLS_SHIFT               (5U)
-#define USB_USBCTRL_UARTCHLS(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
-#define USB_USBCTRL_PDE_MASK                     (0x40U)
-#define USB_USBCTRL_PDE_SHIFT                    (6U)
-#define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
-#define USB_USBCTRL_SUSP_MASK                    (0x80U)
-#define USB_USBCTRL_SUSP_SHIFT                   (7U)
-#define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
-
-/*! @name OBSERVE - USB OTG Observe register */
-#define USB_OBSERVE_DMPD_MASK                    (0x10U)
-#define USB_OBSERVE_DMPD_SHIFT                   (4U)
-#define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
-#define USB_OBSERVE_DPPD_MASK                    (0x40U)
-#define USB_OBSERVE_DPPD_SHIFT                   (6U)
-#define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
-#define USB_OBSERVE_DPPU_MASK                    (0x80U)
-#define USB_OBSERVE_DPPU_SHIFT                   (7U)
-#define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
-
-/*! @name CONTROL - USB OTG Control register */
-#define USB_CONTROL_DPPULLUPNONOTG_MASK          (0x10U)
-#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         (4U)
-#define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
-
-/*! @name USBTRC0 - USB Transceiver Control register 0 */
-#define USB_USBTRC0_USB_RESUME_INT_MASK          (0x1U)
-#define USB_USBTRC0_USB_RESUME_INT_SHIFT         (0U)
-#define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
-#define USB_USBTRC0_SYNC_DET_MASK                (0x2U)
-#define USB_USBTRC0_SYNC_DET_SHIFT               (1U)
-#define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    (0x4U)
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   (2U)
-#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
-#define USB_USBTRC0_VREDG_DET_MASK               (0x8U)
-#define USB_USBTRC0_VREDG_DET_SHIFT              (3U)
-#define USB_USBTRC0_VREDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
-#define USB_USBTRC0_VFEDG_DET_MASK               (0x10U)
-#define USB_USBTRC0_VFEDG_DET_SHIFT              (4U)
-#define USB_USBTRC0_VFEDG_DET(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
-#define USB_USBTRC0_USBRESMEN_MASK               (0x20U)
-#define USB_USBTRC0_USBRESMEN_SHIFT              (5U)
-#define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
-#define USB_USBTRC0_USBRESET_MASK                (0x80U)
-#define USB_USBTRC0_USBRESET_SHIFT               (7U)
-#define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
-
-/*! @name USBFRMADJUST - Frame Adjust Register */
-#define USB_USBFRMADJUST_ADJ_MASK                (0xFFU)
-#define USB_USBFRMADJUST_ADJ_SHIFT               (0U)
-#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
-
-/*! @name MISCCTRL - Miscellaneous Control register */
-#define USB_MISCCTRL_SOFDYNTHLD_MASK             (0x1U)
-#define USB_MISCCTRL_SOFDYNTHLD_SHIFT            (0U)
-#define USB_MISCCTRL_SOFDYNTHLD(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
-#define USB_MISCCTRL_SOFBUSSET_MASK              (0x2U)
-#define USB_MISCCTRL_SOFBUSSET_SHIFT             (1U)
-#define USB_MISCCTRL_SOFBUSSET(x)                (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
-#define USB_MISCCTRL_OWNERRISODIS_MASK           (0x4U)
-#define USB_MISCCTRL_OWNERRISODIS_SHIFT          (2U)
-#define USB_MISCCTRL_OWNERRISODIS(x)             (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
-#define USB_MISCCTRL_VREDG_EN_MASK               (0x8U)
-#define USB_MISCCTRL_VREDG_EN_SHIFT              (3U)
-#define USB_MISCCTRL_VREDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
-#define USB_MISCCTRL_VFEDG_EN_MASK               (0x10U)
-#define USB_MISCCTRL_VFEDG_EN_SHIFT              (4U)
-#define USB_MISCCTRL_VFEDG_EN(x)                 (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
-#define USB_MISCCTRL_STL_ADJ_EN_MASK             (0x80U)
-#define USB_MISCCTRL_STL_ADJ_EN_SHIFT            (7U)
-#define USB_MISCCTRL_STL_ADJ_EN(x)               (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK)
-
-/*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */
-#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK       (0x1U)
-#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT      (0U)
-#define USB_STALL_IL_DIS_STALL_I_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
-#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK       (0x2U)
-#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT      (1U)
-#define USB_STALL_IL_DIS_STALL_I_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
-#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK       (0x4U)
-#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT      (2U)
-#define USB_STALL_IL_DIS_STALL_I_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
-#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK       (0x8U)
-#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT      (3U)
-#define USB_STALL_IL_DIS_STALL_I_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
-#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK       (0x10U)
-#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT      (4U)
-#define USB_STALL_IL_DIS_STALL_I_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
-#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK       (0x20U)
-#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT      (5U)
-#define USB_STALL_IL_DIS_STALL_I_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
-#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK       (0x40U)
-#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT      (6U)
-#define USB_STALL_IL_DIS_STALL_I_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
-#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK       (0x80U)
-#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT      (7U)
-#define USB_STALL_IL_DIS_STALL_I_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
-
-/*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */
-#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK       (0x1U)
-#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT      (0U)
-#define USB_STALL_IH_DIS_STALL_I_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
-#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK       (0x2U)
-#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT      (1U)
-#define USB_STALL_IH_DIS_STALL_I_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
-#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK      (0x4U)
-#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT     (2U)
-#define USB_STALL_IH_DIS_STALL_I_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
-#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK      (0x8U)
-#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT     (3U)
-#define USB_STALL_IH_DIS_STALL_I_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
-#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK      (0x10U)
-#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT     (4U)
-#define USB_STALL_IH_DIS_STALL_I_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
-#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK      (0x20U)
-#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT     (5U)
-#define USB_STALL_IH_DIS_STALL_I_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
-#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK      (0x40U)
-#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT     (6U)
-#define USB_STALL_IH_DIS_STALL_I_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
-#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK      (0x80U)
-#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT     (7U)
-#define USB_STALL_IH_DIS_STALL_I_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
-
-/*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */
-#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK       (0x1U)
-#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT      (0U)
-#define USB_STALL_OL_DIS_STALL_O_DIS0(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
-#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK       (0x2U)
-#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT      (1U)
-#define USB_STALL_OL_DIS_STALL_O_DIS1(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
-#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK       (0x4U)
-#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT      (2U)
-#define USB_STALL_OL_DIS_STALL_O_DIS2(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
-#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK       (0x8U)
-#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT      (3U)
-#define USB_STALL_OL_DIS_STALL_O_DIS3(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
-#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK       (0x10U)
-#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT      (4U)
-#define USB_STALL_OL_DIS_STALL_O_DIS4(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
-#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK       (0x20U)
-#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT      (5U)
-#define USB_STALL_OL_DIS_STALL_O_DIS5(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
-#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK       (0x40U)
-#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT      (6U)
-#define USB_STALL_OL_DIS_STALL_O_DIS6(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
-#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK       (0x80U)
-#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT      (7U)
-#define USB_STALL_OL_DIS_STALL_O_DIS7(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
-
-/*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */
-#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK       (0x1U)
-#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT      (0U)
-#define USB_STALL_OH_DIS_STALL_O_DIS8(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
-#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK       (0x2U)
-#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT      (1U)
-#define USB_STALL_OH_DIS_STALL_O_DIS9(x)         (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
-#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK      (0x4U)
-#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT     (2U)
-#define USB_STALL_OH_DIS_STALL_O_DIS10(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
-#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK      (0x8U)
-#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT     (3U)
-#define USB_STALL_OH_DIS_STALL_O_DIS11(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
-#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK      (0x10U)
-#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT     (4U)
-#define USB_STALL_OH_DIS_STALL_O_DIS12(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
-#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK      (0x20U)
-#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT     (5U)
-#define USB_STALL_OH_DIS_STALL_O_DIS13(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
-#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK      (0x40U)
-#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT     (6U)
-#define USB_STALL_OH_DIS_STALL_O_DIS14(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
-#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK      (0x80U)
-#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT     (7U)
-#define USB_STALL_OH_DIS_STALL_O_DIS15(x)        (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
-
-/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
-#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
-#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
-#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
-
-/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       (0x1U)
-#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      (0U)
-#define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       (0x2U)
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      (1U)
-#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
-
-/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
-#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
-#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
-#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)   (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
-
-/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
-#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
-
-#define USB0_BASE                                ((0x50000000))
-
-#define USB_BASE_ADDRS                           { USB0_BASE }
-
-
-
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif //__REG_USB_OTG_FS_H
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h
deleted file mode 100644
index a802bbab6..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/reg_wwdg.h
+++ /dev/null
@@ -1,133 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     reg_wwdg.h
-/// @author   AE TEAM
-/// @brief    THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
-///           MM32 FIRMWARE LIBRARY.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-
-#ifndef __REG_WWDG_H
-#define __REG_WWDG_H
-
-// Files includes
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "types.h"
-
-
-
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-
-
-
-
-
-
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief WWDG Base Address Definition
-////////////////////////////////////////////////////////////////////////////////
-#define WWDG_BASE                       (APB1PERIPH_BASE + 0x2C00)              ///< Base Address: 0x40002C00
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief WWDG Register Structure Definition
-////////////////////////////////////////////////////////////////////////////////
-#undef USENCOMBINEREGISTER
-#undef USENNEWREGISTER
-#undef USENOLDREGISTER
-#define USENCOMBINEREGISTER
-#ifdef USENCOMBINEREGISTER
-typedef struct {
-    __IO u32 CR;                                                                ///< Control register                               offset: 0x00
-    union {
-        __IO u32 CFGR;                                                          ///< Configuration register                         offset: 0x04
-        __IO u32 CFR;
-    };
-    __IO u32 SR;                                                                ///< Status register                                offset: 0x08
-} WWDG_TypeDef;
-#endif
-#ifdef USENNEWREGISTER
-typedef struct {
-    __IO u32 CR;                                                                ///< Control register                               offset: 0x00
-    __IO u32 CFGR;                                                              ///< Configuration register                         offset: 0x04
-    __IO u32 SR;                                                                ///< Status register                                offset: 0x08
-} WWDG_TypeDef;
-#endif
-#ifdef USENOLDREGISTER
-typedef struct {
-    __IO u32 CR;
-    __IO u32 CFR;
-    __IO u32 SR;
-} WWDG_TypeDef;
-#endif
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief WWDG type pointer Definition
-////////////////////////////////////////////////////////////////////////////////
-#define WWDG                            ((WWDG_TypeDef*) WWDG_BASE)
-
-
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief WWDG_CR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define WWDG_CR_CNT_Pos                 (0)
-#define WWDG_CR_CNT                     (0x7FU << WWDG_CR_CNT_Pos)              ///< T[6:0] bits (7-Bit counter (MSB to LSB))
-#define WWDG_CR_WDGA_Pos                (7)
-#define WWDG_CR_WDGA                    (0x01U << WWDG_CR_WDGA_Pos)             ///< Activation bit
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief WWDG_CFR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define WWDG_CFGR_WINDOW_Pos            (0)
-#define WWDG_CFGR_WINDOW                (0x7FU << WWDG_CFGR_WINDOW_Pos)         ///< W[6:0] bits (7-bit window value)
-#define WWDG_CFGR_WDGTB_Pos             (7)
-#define WWDG_CFGR_WDGTB                 (0x03U << WWDG_CFGR_WDGTB_Pos)          ///< WDGTB[1:0] bits (Timer Base)
-#define WWDG_CFGR_WDGTB_1               (0x00U << WWDG_CFGR_WDGTB_Pos)          ///< WDGTB[1:0] bits (Timer Base /1)
-#define WWDG_CFGR_WDGTB_2               (0x01U << WWDG_CFGR_WDGTB_Pos)          ///< WDGTB[1:0] bits (Timer Base /2)
-#define WWDG_CFGR_WDGTB_4               (0x02U << WWDG_CFGR_WDGTB_Pos)          ///< WDGTB[1:0] bits (Timer Base /4)
-#define WWDG_CFGR_WDGTB_8               (0x03U << WWDG_CFGR_WDGTB_Pos)          ///< WDGTB[1:0] bits (Timer Base /8)
-#define WWDG_CFGR_EWI_Pos               (9)
-#define WWDG_CFGR_EWI                   (0x01U << WWDG_CFGR_EWI_Pos)            ///< Early Wakeup Interrupt
-
-////////////////////////////////////////////////////////////////////////////////
-/// @brief WWDG_SR Register Bit Definition
-////////////////////////////////////////////////////////////////////////////////
-#define WWDG_SR_EWIF_Pos                (0)
-#define WWDG_SR_EWIF                    (0x01U << WWDG_SR_EWIF_Pos)             ///< Early Wakeup Interrupt Flag
-
-
-
-
-/// @}
-
-/// @}
-
-/// @}
-
-////////////////////////////////////////////////////////////////////////////////
-#endif
-////////////////////////////////////////////////////////////////////////////////
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h b/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h
deleted file mode 100644
index baceddd05..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Include/types.h
+++ /dev/null
@@ -1,105 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     types.h
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE TYPE FIRMWARE FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#ifndef __TYPES_H
-#define __TYPES_H
-
-// Files includes
-#include <stdint.h>
-#include <stdbool.h>
-
-
-
-#ifdef __cplusplus
-#define     __I     volatile                        ///< Defines 'read only' permissions
-#else
-#define     __I     volatile const                  ///< Defines 'read only' permissions
-#endif
-#define     __O     volatile                        ///< Defines 'write only' permissions
-#define     __IO    volatile                        ///< Defines 'read / write' permissions
-
-typedef long long    s64;                           ///< used for signed 64bit
-
-typedef signed int   s32;
-typedef signed short s16;
-typedef signed char  s8;
-
-typedef signed int  const  sc32;                    ///< Read Only
-typedef signed short const sc16;                    ///< Read Only
-typedef signed char  const sc8;                     ///< Read Only
-
-typedef volatile signed int   vs32;
-typedef volatile signed short vs16;
-typedef volatile signed char  vs8;
-
-typedef volatile signed int  const  vsc32;          ///< Read Only
-typedef volatile signed short const vsc16;          ///< Read Only
-typedef volatile signed char  const vsc8;           ///< Read Only
-
-typedef unsigned int   u32;
-typedef unsigned short u16;
-typedef unsigned char  u8;
-
-typedef unsigned int  const  uc32;                  ///< Read Only
-typedef unsigned short const uc16;                  ///< Read Only
-typedef unsigned char  const uc8;                   ///< Read Only
-
-typedef volatile unsigned int   vu32;
-typedef volatile unsigned short vu16;
-typedef volatile unsigned char  vu8;
-
-typedef volatile unsigned int  const  vuc32;        ///< Read Only
-typedef volatile unsigned short const vuc16;        ///< Read Only
-typedef volatile unsigned char  const vuc8;         ///< Read Only
-typedef bool    BOOL;
-#ifndef NULL
-#define NULL ((void *)0)
-#endif
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-#define U8_MAX     ((u8)255)
-#define S8_MAX     ((s8)127)
-#define S8_MIN     ((s8)-128)
-#define U16_MAX    ((u16)65535u)
-#define S16_MAX    ((s16)32767)
-#define S16_MIN    ((s16)-32768)
-#define U32_MAX    ((u32)4294967295uL)
-#define S32_MAX    ((s32)2147483647)
-#define S32_MIN    ((s32)-2147483648uL)
-
-#define MAX(a,b)((a)>(b)?(a):(b))
-#define MIN(a,b)((a)<(b)?(a):(b))
-
-#define SET_BIT(reg, bit)     ((reg) |= (bit))
-#define CLEAR_BIT(reg, bit)   ((reg) &= ~(bit))
-#define READ_BIT(reg, bit)    ((reg) & (bit))
-#define CLEAR_REG(reg)        ((reg) = (0x0))
-#define WRITE_REG(reg, value)   ((reg) = (value))
-#define READ_REG(reg)         ((reg))
-#define MODIFY_REG(reg, CLEARMASK, SETMASK)  WRITE_REG((reg), (((READ_REG(reg)) & (~(CLEARMASK))) | (SETMASK)))
-#define POSITION_VAL(value)     (__CLZ(__RBIT(value)))
-
-#define LEFT_SHIFT_BIT(x)   (1 << x)
-
-
-#endif
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
deleted file mode 100644
index 920aefcba..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
+++ /dev/null
@@ -1,440 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_mm32m3ux_u_gcc.s
-  * @author    AE Team
-  * @brief     MM32 devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  */
-
-                .syntax     unified
-                .cpu        cortex-m3
-                .fpu        softvfp
-                .thumb
-
-                .global     g_pfnVectors
-                .global     Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-                .word       _sidata
-/* start address for the .data section. defined in linker script */
-                .word       _sdata
-/* end address for the .data section. defined in linker script */
-                .word       _edata
-/* start address for the .bss section. defined in linker script */
-                .word       _sbss
-/* end address for the .bss section. defined in linker script */
-                .word       _ebss
-
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval : None
-*/
-
-                .section    .text.Reset_Handler
-                .weak       Reset_Handler
-                .type       Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */  
-                movs        r1, #0
-                b           LoopCopyDataInit
-
-CopyDataInit:
-                ldr         r3, =_sidata
-                ldr         r3, [r3, r1]
-                str         r3, [r0, r1]
-                adds        r1, r1, #4
-    
-LoopCopyDataInit:
-                ldr         r0, =_sdata
-                ldr         r3, =_edata
-                adds        r2, r0, r1
-                cmp         r2, r3
-                bcc         CopyDataInit
-                ldr         r2, =_sbss
-                b           LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-                movs        r3, #0
-                str         r3, [r2], #4
-    
-LoopFillZerobss:
-                ldr         r3, = _ebss
-                cmp         r2, r3
-                bcc         FillZerobss
-
-/* Call the clock system intitialization function.*/
-                bl          SystemInit
-/* Call static constructors */
-                bl          __libc_init_array
-/* Call the application's entry point.*/
-                bl          main
-                bx          lr    
-                .size       Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- * @param  None     
- * @retval None       
-*/
-                .section    .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-                b           Infinite_Loop
-                .size       Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-                .section    .isr_vector,"a",%progbits
-                .type       g_pfnVectors, %object
-                .size       g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:                                                                   
-                .word       _estack                                             /*        Top of Stack                         */
-                .word       Reset_Handler                                       /*        Reset Handler                        */
-                .word       NMI_Handler                                         /*-14     NMI Handler                          */
-                .word       HardFault_Handler                                   /*-13     Hard Fault Handler                   */
-                .word       MemManage_Handler                                   /*-12     MPU Fault Handler                    */
-                .word       BusFault_Handler                                    /*-11     Bus Fault Handler                    */
-                .word       UsageFault_Handler                                  /*-10     Usage Fault Handler                  */
-                .word       0                                                   /*-9      Reserved                             */
-                .word       0                                                   /*-8      Reserved                             */
-                .word       0                                                   /*-7      Reserved                             */
-                .word       0                                                   /*-6      Reserved                             */
-                .word       SVC_Handler                                         /*-5      SVCall Handler                       */
-                .word       DebugMon_Handler                                    /*-4      Debug Monitor Handler                */
-                .word       0                                                   /*-3      Reserved                             */
-                .word       PendSV_Handler                                      /*-2      PendSV Handler                       */
-                .word       SysTick_Handler                                     /*-1      SysTick Handler                      */
-                                                                                
-                /* External Interrupts */
-                .word       WWDG_IRQHandler                                     /*0       Window Watchdog                      */
-                .word       PVD_IRQHandler                                      /*1       PVD through EXTI Line detect         */
-                .word       TAMPER_IRQHandler                                   /*2       Tamper                               */
-                .word       RTC_IRQHandler                                      /*3       RTC                                  */
-                .word       FLASH_IRQHandler                                    /*4       Flash                                */
-                .word       RCC_CRS_IRQHandler                                  /*5       RCC                                  */
-                .word       EXTI0_IRQHandler                                    /*6       EXTI Line 0                          */
-                .word       EXTI1_IRQHandler                                    /*7       EXTI Line 1                          */
-                .word       EXTI2_IRQHandler                                    /*8       EXTI Line 2                          */
-                .word       EXTI3_IRQHandler                                    /*9       EXTI Line 3                          */
-                .word       EXTI4_IRQHandler                                    /*10      EXTI Line 4                          */
-                .word       DMA1_Channel1_IRQHandler                            /*11      DMA1 Channel 1                       */
-                .word       DMA1_Channel2_IRQHandler                            /*12      DMA1 Channel 2                       */
-                .word       DMA1_Channel3_IRQHandler                            /*13      DMA1 Channel 3                       */
-                .word       DMA1_Channel4_IRQHandler                            /*14      DMA1 Channel 4                       */
-                .word       DMA1_Channel5_IRQHandler                            /*15      DMA1 Channel 5                       */
-                .word       DMA1_Channel6_IRQHandler                            /*16      DMA1 Channel 6                       */
-                .word       DMA1_Channel7_IRQHandler                            /*17      DMA1 Channel 7                       */
-                .word       ADC1_2_IRQHandler                                   /*18      ADC1 and ADC2                        */
-                .word       FlashCache_IRQHandler                               /*19      FlashCache outage                    */
-                .word       0                                                   /*20      Reserved                             */
-                .word       CAN1_RX_IRQHandler                                  /*21      CAN1_RX                              */
-                .word       0                                                   /*22      Reserved                             */
-                .word       EXTI9_5_IRQHandler                                  /*23      EXTI Line 9..5                       */
-                .word       TIM1_BRK_IRQHandler                                 /*24      TIM1 Break                           */
-                .word       TIM1_UP_IRQHandler                                  /*25      TIM1 Update                          */
-                .word       TIM1_TRG_COM_IRQHandler                             /*26      TIM1 Trigger and Commutation         */
-                .word       TIM1_CC_IRQHandler                                  /*27      TIM1 Capture Compare                 */
-                .word       TIM2_IRQHandler                                     /*28      TIM2                                 */
-                .word       TIM3_IRQHandler                                     /*29      TIM3                                 */
-                .word       TIM4_IRQHandler                                     /*30      TIM4                                 */
-                .word       I2C1_IRQHandler                                     /*31      I2C1 Event                           */
-                .word       0                                                   /*32      Reserved                             */
-                .word       I2C2_IRQHandler                                     /*33      I2C2 Event                           */
-                .word       0                                                   /*34      Reserved                             */
-                .word       SPI1_IRQHandler                                     /*35      SPI1                                 */
-                .word       SPI2_IRQHandler                                     /*36      SPI2                                 */
-                .word       UART1_IRQHandler                                    /*37      UART1                                */
-                .word       UART2_IRQHandler                                    /*38      UART2                                */
-                .word       UART3_IRQHandler                                    /*39      UART3                                */
-                .word       EXTI15_10_IRQHandler                                /*40      EXTI Line 15..10                     */
-                .word       RTCAlarm_IRQHandler                                 /*41      RTC Alarm through EXTI Line 17       */
-                .word       OTG_FS_WKUP_IRQHandler                              /*42      USB OTG FS Wakeup through EXTI line  */
-                .word       TIM8_BRK_IRQHandler                                 /*43      TIM8 Break                           */
-                .word       TIM8_UP_IRQHandler                                  /*44      TIM8 Update                          */
-                .word       TIM8_TRG_COM_IRQHandler                             /*45      TIM8 Trigger and Commutation         */
-                .word       TIM8_CC_IRQHandler                                  /*46      TIM8 Capture Compare                 */
-                .word       ADC3_IRQHandler                                     /*47      ADC3                                 */
-                .word       0                                                   /*48      Reserved                             */
-                .word       SDIO_IRQHandler                                     /*49      SDIO                                 */
-                .word       TIM5_IRQHandler                                     /*50      TIM5                                 */
-                .word       SPI3_IRQHandler                                     /*51      SPI3                                 */
-                .word       UART4_IRQHandler                                    /*52      UART4                                */
-                .word       UART5_IRQHandler                                    /*53      UART5                                */
-                .word       TIM6_IRQHandler                                     /*54      TIM6                                 */
-                .word       TIM7_IRQHandler                                     /*55      TIM7                                 */
-                .word       DMA2_Channel1_IRQHandler                            /*56      DMA2 Channel 1                       */
-                .word       DMA2_Channel2_IRQHandler                            /*57      DMA2 Channel 2                       */
-                .word       DMA2_Channel3_IRQHandler                            /*58      DMA2 Channel 3                       */
-                .word       DMA2_Channel4_IRQHandler                            /*59      DMA2 Channel 4                       */
-                .word       DMA2_Channel5_IRQHandler                            /*60      DMA2 Channel 5                       */
-                .word       ETH_IRQHandler                                      /*61      Ethernet                             */
-                .word       0                                                   /*62      Reserved                             */
-                .word       0                                                   /*63      Reserved                             */
-                .word       COMP1_2_IRQHandler                                  /*64      COMP1,COMP2                          */
-                .word       0                                                   /*65      Reserved                             */
-                .word       0                                                   /*66      Reserved                             */
-                .word       OTG_FS_IRQHandler                                   /*67      USB OTG_FullSpeed                    */
-                .word       0                                                   /*68      Reserved                             */
-                .word       0                                                   /*69      Reserved                             */
-                .word       0                                                   /*70      Reserved                             */
-                .word       UART6_IRQHandler                                    /*71      UART6                                */
-                .word       0                                                   /*72      Reserved                             */
-                .word       0                                                   /*73      Reserved                             */
-                .word       0                                                   /*74      Reserved                             */
-                .word       0                                                   /*75      Reserved                             */
-                .word       0                                                   /*76      Reserved                             */
-                .word       0                                                   /*77      Reserved                             */
-                .word       0                                                   /*78      Reserved                             */
-                .word       0                                                   /*79      Reserved                             */
-                .word       0                                                   /*80      Reserved                             */
-                .word       0                                                   /*81      Reserved                             */
-                .word       UART7_IRQHandler                                    /*82      UART7                                */
-                .word       UART8_IRQHandler                                    /*83      UART8                                */
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-* 
-*******************************************************************************/
-                .weak       NMI_Handler
-                .thumb_set  NMI_Handler                 ,Default_Handler
-
-                .weak       HardFault_Handler
-                .thumb_set  HardFault_Handler           ,Default_Handler
-
-                .weak       MemManage_Handler
-                .thumb_set  MemManage_Handler           ,Default_Handler
-
-                .weak       BusFault_Handler
-                .thumb_set  BusFault_Handler            ,Default_Handler
-
-                .weak       UsageFault_Handler
-                .thumb_set  UsageFault_Handler          ,Default_Handler
-
-                .weak       SVC_Handler
-                .thumb_set  SVC_Handler                 ,Default_Handler
-
-                .weak       DebugMon_Handler
-                .thumb_set  DebugMon_Handler            ,Default_Handler
-
-                .weak       PendSV_Handler
-                .thumb_set  PendSV_Handler              ,Default_Handler
-
-                .weak       SysTick_Handler
-                .thumb_set  SysTick_Handler             ,Default_Handler              
-
-
-                .weak       WWDG_IRQHandler             
-                .thumb_set  WWDG_IRQHandler             ,Default_Handler
-                                                        
-                .weak       PVD_IRQHandler              
-                .thumb_set  PVD_IRQHandler              ,Default_Handler
-                                                        
-                .weak       TAMPER_IRQHandler           
-                .thumb_set  TAMPER_IRQHandler           ,Default_Handler
-                                                        
-                .weak       RTC_IRQHandler              
-                .thumb_set  RTC_IRQHandler              ,Default_Handler
-                                                        
-                .weak       FLASH_IRQHandler            
-                .thumb_set  FLASH_IRQHandler            ,Default_Handler
-                                                        
-                .weak       RCC_CRS_IRQHandler          
-                .thumb_set  RCC_CRS_IRQHandler          ,Default_Handler
-                                                        
-                .weak       EXTI0_IRQHandler            
-                .thumb_set  EXTI0_IRQHandler            ,Default_Handler
-                                                        
-                .weak       EXTI1_IRQHandler            
-                .thumb_set  EXTI1_IRQHandler            ,Default_Handler
-                                                        
-                .weak       EXTI2_IRQHandler            
-                .thumb_set  EXTI2_IRQHandler            ,Default_Handler
-                                                        
-                .weak       EXTI3_IRQHandler            
-                .thumb_set  EXTI3_IRQHandler            ,Default_Handler
-                                                        
-                .weak       EXTI4_IRQHandler            
-                .thumb_set  EXTI4_IRQHandler            ,Default_Handler
-                                                        
-                .weak       DMA1_Channel1_IRQHandler    
-                .thumb_set  DMA1_Channel1_IRQHandler    ,Default_Handler
-                                                        
-                .weak       DMA1_Channel2_IRQHandler    
-                .thumb_set  DMA1_Channel2_IRQHandler    ,Default_Handler
-                                                        
-                .weak       DMA1_Channel3_IRQHandler    
-                .thumb_set  DMA1_Channel3_IRQHandler    ,Default_Handler
-                                                        
-                .weak       DMA1_Channel4_IRQHandler    
-                .thumb_set  DMA1_Channel4_IRQHandler    ,Default_Handler
-                                                        
-                .weak       DMA1_Channel5_IRQHandler    
-                .thumb_set  DMA1_Channel5_IRQHandler    ,Default_Handler
-                                                        
-                .weak       DMA1_Channel6_IRQHandler    
-                .thumb_set  DMA1_Channel6_IRQHandler    ,Default_Handler
-                                                        
-                .weak       DMA1_Channel7_IRQHandler    
-                .thumb_set  DMA1_Channel7_IRQHandler    ,Default_Handler
-                                                        
-                .weak       ADC1_2_IRQHandler           
-                .thumb_set  ADC1_2_IRQHandler           ,Default_Handler
-                                                        
-                .weak       FlashCache_IRQHandler       
-                .thumb_set  FlashCache_IRQHandler       ,Default_Handler
-                                                        
-                .weak       CAN1_RX_IRQHandler          
-                .thumb_set  CAN1_RX_IRQHandler          ,Default_Handler
-                                                        
-                .weak       EXTI9_5_IRQHandler          
-                .thumb_set  EXTI9_5_IRQHandler          ,Default_Handler
-                                                        
-                .weak       TIM1_BRK_IRQHandler         
-                .thumb_set  TIM1_BRK_IRQHandler         ,Default_Handler
-                                                        
-                .weak       TIM1_UP_IRQHandler          
-                .thumb_set  TIM1_UP_IRQHandler          ,Default_Handler
-                                                        
-                .weak       TIM1_TRG_COM_IRQHandler     
-                .thumb_set  TIM1_TRG_COM_IRQHandler     ,Default_Handler
-                                                        
-                .weak       TIM1_CC_IRQHandler          
-                .thumb_set  TIM1_CC_IRQHandler          ,Default_Handler
-                                                        
-                .weak       TIM2_IRQHandler             
-                .thumb_set  TIM2_IRQHandler             ,Default_Handler
-                                                        
-                .weak       TIM3_IRQHandler             
-                .thumb_set  TIM3_IRQHandler             ,Default_Handler
-                                                        
-                .weak       TIM4_IRQHandler             
-                .thumb_set  TIM4_IRQHandler             ,Default_Handler
-                                                        
-                .weak       I2C1_IRQHandler             
-                .thumb_set  I2C1_IRQHandler             ,Default_Handler
-                                                        
-                .weak       I2C2_IRQHandler             
-                .thumb_set  I2C2_IRQHandler             ,Default_Handler
-                                                        
-                .weak       SPI1_IRQHandler             
-                .thumb_set  SPI1_IRQHandler             ,Default_Handler
-                                                        
-                .weak       SPI2_IRQHandler             
-                .thumb_set  SPI2_IRQHandler             ,Default_Handler
-                                                        
-                .weak       UART1_IRQHandler            
-                .thumb_set  UART1_IRQHandler            ,Default_Handler
-                                                        
-                .weak       UART2_IRQHandler            
-                .thumb_set  UART2_IRQHandler            ,Default_Handler
-                                                        
-                .weak       UART3_IRQHandler            
-                .thumb_set  UART3_IRQHandler            ,Default_Handler
-                                                        
-                .weak       EXTI15_10_IRQHandler        
-                .thumb_set  EXTI15_10_IRQHandler        ,Default_Handler
-                                                        
-                .weak       RTCAlarm_IRQHandler         
-                .thumb_set  RTCAlarm_IRQHandler         ,Default_Handler
-                                                        
-                .weak       OTG_FS_WKUP_IRQHandler      
-                .thumb_set  OTG_FS_WKUP_IRQHandler      ,Default_Handler
-                                                        
-                .weak       TIM8_BRK_IRQHandler         
-                .thumb_set  TIM8_BRK_IRQHandler         ,Default_Handler
-                                                        
-                .weak       TIM8_UP_IRQHandler          
-                .thumb_set  TIM8_UP_IRQHandler          ,Default_Handler
-                                                        
-                .weak       TIM8_TRG_COM_IRQHandler     
-                .thumb_set  TIM8_TRG_COM_IRQHandler     ,Default_Handler
-                                                        
-                .weak       TIM8_CC_IRQHandler          
-                .thumb_set  TIM8_CC_IRQHandler          ,Default_Handler
-                                                        
-                .weak       ADC3_IRQHandler             
-                .thumb_set  ADC3_IRQHandler             ,Default_Handler
-                                                        
-                .weak       SDIO_IRQHandler             
-                .thumb_set  SDIO_IRQHandler             ,Default_Handler
-                                                        
-                .weak       TIM5_IRQHandler             
-                .thumb_set  TIM5_IRQHandler             ,Default_Handler
-                                                        
-                .weak       SPI3_IRQHandler             
-                .thumb_set  SPI3_IRQHandler             ,Default_Handler
-                                                        
-                .weak       UART4_IRQHandler            
-                .thumb_set  UART4_IRQHandler            ,Default_Handler
-                                                        
-                .weak       UART5_IRQHandler            
-                .thumb_set  UART5_IRQHandler            ,Default_Handler
-                                                        
-                .weak       TIM6_IRQHandler             
-                .thumb_set  TIM6_IRQHandler             ,Default_Handler
-                                                        
-                .weak       TIM7_IRQHandler             
-                .thumb_set  TIM7_IRQHandler             ,Default_Handler
-                                                        
-                .weak       DMA2_Channel1_IRQHandler    
-                .thumb_set  DMA2_Channel1_IRQHandler    ,Default_Handler
-                                                        
-                .weak       DMA2_Channel2_IRQHandler    
-                .thumb_set  DMA2_Channel2_IRQHandler    ,Default_Handler
-                                                        
-                .weak       DMA2_Channel3_IRQHandler    
-                .thumb_set  DMA2_Channel3_IRQHandler    ,Default_Handler
-                                                        
-                .weak       DMA2_Channel4_IRQHandler    
-                .thumb_set  DMA2_Channel4_IRQHandler    ,Default_Handler
-                                                        
-                .weak       DMA2_Channel5_IRQHandler    
-                .thumb_set  DMA2_Channel5_IRQHandler    ,Default_Handler
-                                                        
-                .weak       ETH_IRQHandler              
-                .thumb_set  ETH_IRQHandler              ,Default_Handler
-                                                        
-                .weak       COMP1_2_IRQHandler          
-                .thumb_set  COMP1_2_IRQHandler          ,Default_Handler
-                                                        
-                .weak       OTG_FS_IRQHandler           
-                .thumb_set  OTG_FS_IRQHandler           ,Default_Handler
-                                                        
-                .weak       UART6_IRQHandler            
-                .thumb_set  UART6_IRQHandler            ,Default_Handler
-                                                        
-                .weak       UART7_IRQHandler            
-                .thumb_set  UART7_IRQHandler            ,Default_Handler
-                                                        
-                .weak       UART8_IRQHandler            
-                .thumb_set  UART8_IRQHandler            ,Default_Handler
-
-
-
-
-/****END OF FILE****/
-
diff --git a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c b/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c
deleted file mode 100644
index cdfa8e801..000000000
--- a/hw/mcu/mm32/mm32f327x/MM32F327x/Source/system_mm32f327x.c
+++ /dev/null
@@ -1,866 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     SYSTEM_MM32.C
-/// @author   AE TEAM
-/// @brief    THIS FILE PROVIDES ALL THE SYSTEM FUNCTIONS.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
-
-// Define to prevent recursive inclusion
-#define _SYSTEM_MM32_C_
-
-// Files includes
-
-/// @addtogroup CMSIS
-/// @{
-
-#include "mm32_device.h"
-
-
-/// @}
-
-
-
-/// @}
-
-
-/// Uncomment the line corresponding to the desired System clock (SYSCLK)
-/// frequency (after reset the HSI is used as SYSCLK source)
-///
-/// IMPORTANT NOTE:
-/// ==============
-/// 1. After each device reset the HSI is used as System clock source.
-///
-/// 2. Please make sure that the selected System clock doesn't exceed your device's
-/// maximum frequency.
-///
-/// 3. If none of the define below is enabled, the HSI is used as System clock
-/// source.
-///
-/// 4. The System clock configuration functions provided within this file assume that:
-/// - For Low, Medium and High density Value line devices an external 8MHz
-/// crystal is used to drive the System clock.
-/// - For Low, Medium and High density devices an external 8MHz crystal is
-/// used to drive the System clock.
-/// - For Connectivity line devices an external 25MHz crystal is used to drive
-/// the System clock.
-/// If you are using different crystal you have to adapt those functions accordingly.
-
-//#define SYSCLK_FREQ_HSE    HSE_VALUE          //HSE_VALUE is define in reg_common.h
-//#define SYSCLK_FREQ_24MHz  (HSE_VALUE*3)      //24000000 based HSE_VALUE = 8000000
-//#define SYSCLK_FREQ_36MHz  (HSE_VALUE*9/2)    //36000000 based HSE_VALUE = 8000000
-//#define SYSCLK_FREQ_48MHz  (HSE_VALUE*6)      //48000000 based HSE_VALUE = 8000000
-//#define SYSCLK_FREQ_XXMHz  (HSE_VALUE*6)      //48000000 based HSE_VALUE = 8000000
-//#define SYSCLK_FREQ_XXMHz  (HSE_VALUE*9)      //72000000 based HSE_VALUE = 8000000
-//#define SYSCLK_FREQ_XXMHz  (HSE_VALUE*12)      //96000000 based HSE_VALUE = 8000000
-#define SYSCLK_FREQ_XXMHz (HSE_VALUE*12)       //120000000 based HSE_VALUE = 8000000
-
-#if defined(SYSCLK_FREQ_HSE) || defined(SYSCLK_FREQ_24MHz) || defined(SYSCLK_FREQ_36MHz) || defined(SYSCLK_FREQ_48MHz) || defined(SYSCLK_FREQ_XXMHz)
-
-#if defined(HSE_VALUE) && (!(HSE_VALUE == 8000000))
-#warning redefine HSE_VALUE in reg_common.h Line 48 and ignore this warning
-#endif
-
-#endif
-
-
-//#define SYSCLK_HSI_24MHz  24000000
-//#define SYSCLK_HSI_36MHz  36000000
-//#define SYSCLK_HSI_48MHz  48000000
-//#define SYSCLK_HSI_XXMHz  48000000
-//#define SYSCLK_HSI_XXMHz  72000000
-//#define SYSCLK_HSI_XXMHz  96000000
-#define SYSCLK_HSI_XXMHz  120000000
-/// Uncomment the following line if you need to relocate your vector Table in
-/// Internal SRAM.
-///#define VECT_TAB_SRAM
-#define VECT_TAB_OFFSET  0x0
-/// Vector Table base offset field.
-/// This value must be a multiple of 0x200.
-
-
-/// @}
-
-
-
-
-///////////////////////////////////////////////////////////////
-///Clock Definitions
-///////////////////////////////////////////////////////////////
-#if defined SYSCLK_FREQ_HSE
-u32 SystemCoreClock         = SYSCLK_FREQ_HSE;
-#elif defined SYSCLK_FREQ_24MHz
-u32 SystemCoreClock         = SYSCLK_FREQ_24MHz;
-#elif defined SYSCLK_FREQ_36MHz
-u32 SystemCoreClock         = SYSCLK_FREQ_36MHz;
-#elif defined SYSCLK_FREQ_48MHz
-u32 SystemCoreClock         = SYSCLK_FREQ_48MHz;
-#elif defined SYSCLK_FREQ_XXMHz
-u32 SystemCoreClock         = SYSCLK_FREQ_XXMHz;
-
-
-#elif defined SYSCLK_HSI_24MHz
-u32 SystemCoreClock         = SYSCLK_HSI_24MHz;
-#elif defined SYSCLK_HSI_36MHz
-u32 SystemCoreClock         = SYSCLK_HSI_36MHz;
-#elif defined SYSCLK_HSI_48MHz
-u32 SystemCoreClock         = SYSCLK_HSI_48MHz;
-#elif defined SYSCLK_HSI_XXMHz
-u32 SystemCoreClock         = SYSCLK_HSI_XXMHz;
-#else //HSI Selected as System Clock source 
-u32 SystemCoreClock         = HSI_VALUE;
-#endif
-
-__I u8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/// @}
-
-
-static void SetSysClock(void);
-
-#if defined SYSCLK_FREQ_HSE
-static void SetSysClockToHSE(void);
-#elif defined SYSCLK_FREQ_24MHz
-static void SetSysClockTo24(void);
-#elif defined SYSCLK_FREQ_36MHz
-static void SetSysClockTo36(void);
-#elif defined SYSCLK_FREQ_48MHz
-static void SetSysClockTo48(void);
-#elif defined SYSCLK_FREQ_XXMHz
-static void SetSysClockToXX(void);
-
-#elif defined SYSCLK_HSI_24MHz
-static void SetSysClockTo24_HSI(void);
-#elif defined SYSCLK_HSI_36MHz
-static void SetSysClockTo36_HSI(void);
-#elif defined SYSCLK_HSI_48MHz
-static void SetSysClockTo48_HSI(void);
-#elif defined SYSCLK_HSI_XXMHz
-static void SetSysClockToXX_HSI(void);
-#endif
-
-#ifdef DATA_IN_ExtSRAM
-static void SystemInit_ExtMemCtl(void);
-#endif //DATA_IN_ExtSRAM 
-
-
-/// @}
-
-
-
-/// @brief  Setup the microcontroller system
-///         Initialize the Embedded Flash Interface, the PLL and update the
-///         SystemCoreClock variable.
-/// @note   This function should be used only after reset.
-/// @param  None
-/// @retval None
-
-void SystemInit (void)
-{
-    //Reset the RCC clock configuration to the default reset state(for debug purpose)
-    //Set HSION bit
-    RCC->CR |= (u32)0x00000001;
-
-    //Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits
-    RCC->CFGR &= (u32)0xF8FFC00C;
-
-    //Reset HSEON, CSSON and PLLON bits
-    RCC->CR &= (u32)0xFEF6FFFF;
-
-    //Reset HSEBYP bit
-    RCC->CR &= (u32)0xFFFBFFFF;
-
-    //Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits
-    RCC->CFGR &= (u32)0xFF3CFFFF;
-    RCC->CR &= (u32)0x008FFFFF;
-
-    //Disable all interrupts and clear pending bits
-    RCC->CIR = 0x009F0000;
-    //Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers
-    //Configure the Flash Latency cycles and enable prefetch buffer
-    SetSysClock();
-}
-
-
-/// @brief  use to return the pllm&plln.
-/// @param  pllclkSourceFrq : PLL source clock frquency;
-///         pllclkFrq : Target PLL clock frquency;
-///         plln : PLL factor PLLN
-///         pllm : PLL factor PLLM
-/// @retval amount of error
-u32 AutoCalPllFactor(u32 pllclkSourceFrq, u32 pllclkFrq, u8* plln, u8* pllm)
-{
-    u32 n, m;
-    u32 tempFrq;
-    u32 minDiff = pllclkFrq;
-    u8  flag = 0;
-    for(m = 0; m < 4 ; m++) {
-        for(n = 0; n < 64 ; n++) {
-            tempFrq =  pllclkSourceFrq * (n + 1) / (m + 1);
-            tempFrq = (tempFrq >  pllclkFrq) ? (tempFrq - pllclkFrq) : (pllclkFrq - tempFrq) ;
-
-            if(minDiff > tempFrq) {
-                minDiff =  tempFrq;
-                *plln = n;
-                *pllm = m;
-            }
-            if(minDiff == 0) {
-                flag = 1;
-                break;
-            }
-        }
-        if(flag != 0) {
-            break;
-        }
-    }
-    return  minDiff;
-}
-static void DELAY_xUs(u32 count)
-{
-    u32 temp;
-    SysTick->CTRL = 0x0;                                                        //disable systick function
-    SysTick->LOAD = count * 8;                                                    //time count for 1us with HSI as SYSCLK
-    SysTick->VAL = 0x00;                                                        //clear counter
-    SysTick->CTRL = 0x5;                                                        //start discrease with Polling
-    do {
-        temp = SysTick->CTRL;
-    } while((temp & 0x01) && !(temp & (1 << 16)));                              //wait time count done
-    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;                                  //Close Counter
-    SysTick->VAL = 0X00;                                                        //clear counter
-}
-/// @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
-/// @param  None
-/// @retval None
-
-static void SetSysClock(void)
-{
-    CACHE->CCR &= ~(0x3 << 3);
-    CACHE->CCR |= 1;
-    while((CACHE->SR & 0x3) != 2);
-#ifdef SYSCLK_FREQ_HSE
-    SetSysClockToHSE();
-#elif defined SYSCLK_FREQ_24MHz
-    SetSysClockTo24();
-#elif defined SYSCLK_FREQ_36MHz
-    SetSysClockTo36();
-#elif defined SYSCLK_FREQ_48MHz
-    SetSysClockTo48();
-#elif defined SYSCLK_FREQ_XXMHz
-    SetSysClockToXX();
-
-#elif defined SYSCLK_HSI_24MHz
-    SetSysClockTo24_HSI();
-#elif defined SYSCLK_HSI_36MHz
-    SetSysClockTo36_HSI();
-#elif defined SYSCLK_HSI_48MHz
-    SetSysClockTo48_HSI();
-#elif defined SYSCLK_HSI_XXMHz
-    SetSysClockToXX_HSI();
-#endif
-
-    //If none of the define above is enabled, the HSI is used as System clock
-    //source (default after reset)
-}
-
-#ifdef SYSCLK_FREQ_HSE
-
-/// @brief  Selects HSE as System clock source and configure HCLK, PCLK2
-///         and PCLK1 prescalers.
-/// @note   This function should be used only after reset.
-/// @param  None
-/// @retval None
-
-static void SetSysClockToHSE(void)
-{
-    __IO u32 StartUpCounter = 0, HSEStatus = 0;
-    s32 i;
-
-    //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
-    //Enable HSE
-    RCC->CR |= ((u32)RCC_CR_HSEON);
-
-    //Wait till HSE is ready and if Time out is reached exit
-    do {
-        HSEStatus = RCC->CR & RCC_CR_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
-        HSEStatus = (u32)0x01;
-        i = 2000;
-        while(i--);
-    }
-    else {
-        HSEStatus = (u32)0x00;
-    }
-
-    if (HSEStatus == (u32)0x01) {
-        //Enable Prefetch Buffer
-        FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-        //Flash 0 wait state ,bit0~2
-        FLASH->ACR &= ~0x07;
-        //HCLK = SYSCLK
-        RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
-
-        //PCLK2 = HCLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
-
-        //PCLK1 = HCLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
-
-        //Select HSE as system clock source
-        RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
-        RCC->CFGR |= (u32)RCC_CFGR_SW_HSE;
-
-        //Wait till HSE is used as system clock source
-        while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x04) {
-        }
-    }
-    else {
-        //If HSE fails to start-up, the application will have wrong clock
-        //configuration. User can add here some code to deal with this error
-    }
-}
-#elif defined SYSCLK_FREQ_24MHz
-
-/// @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
-///         and PCLK1 prescalers.
-/// @note   This function should be used only after reset.
-/// @param  None
-/// @retval None
-
-static void SetSysClockTo24(void)
-{
-    __IO u32 StartUpCounter = 0, HSEStatus = 0;
-    s32 i;
-
-    //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
-    //Enable HSE
-    RCC->CR |= ((u32)RCC_CR_HSEON);
-
-    //Wait till HSE is ready and if Time out is reached exit
-    do {
-        HSEStatus = RCC->CR & RCC_CR_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
-        HSEStatus = (u32)0x01;
-        i = 2000;
-        while(i--);
-    }
-    else {
-        HSEStatus = (u32)0x00;
-    }
-
-    if (HSEStatus == (u32)0x01) {
-        //Enable Prefetch Buffer
-        FLASH->ACR |= FLASH_ACR_PRFTBE;
-        //Flash 0 wait state ,bit0~2
-        FLASH->ACR &= ~0x07;
-        FLASH->ACR |= 0x01;
-        //HCLK = SYSCLK
-        RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
-
-        //PCLK2 = HCLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
-
-        //PCLK1 = HCLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
-
-        // PLL configuration:  = (HSE ) * (2+1) = 24 MHz
-        RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
-        RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
-
-        RCC->APB1ENR |= RCC_APB1ENR_PWR;
-        RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
-        RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos));
-        //Enable PLL
-        RCC->CR |= RCC_CR_PLLON;
-
-        //Wait till PLL is ready
-        while((RCC->CR & RCC_CR_PLLRDY) == 0) {
-        }
-
-        //Select PLL as system clock source
-        RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
-        RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
-
-        //Wait till PLL is used as system clock source
-        while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
-        }
-    }
-    else {
-        //If HSE fails to start-up, the application will have wrong clock
-        //configuration. User can add here some code to deal with this error
-    }
-}
-#elif defined SYSCLK_FREQ_36MHz
-
-/// @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
-///         and PCLK1 prescalers.
-/// @note   This function should be used only after reset.
-/// @param  None
-/// @retval None
-
-static void SetSysClockTo36(void)
-{
-    s32 i;
-    __IO u32 StartUpCounter = 0, HSEStatus = 0;
-
-    //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
-    //Enable HSE
-    RCC->CR |= ((u32)RCC_CR_HSEON);
-
-    //Wait till HSE is ready and if Time out is reached exit
-    do {
-        HSEStatus = RCC->CR & RCC_CR_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
-        HSEStatus = (u32)0x01;
-        i = 2000;
-        while(i--);
-    }
-    else {
-        HSEStatus = (u32)0x00;
-    }
-
-    if (HSEStatus == (u32)0x01) {
-        //Enable Prefetch Buffer
-        FLASH->ACR |= FLASH_ACR_PRFTBE;
-
-        //Flash 0 wait state ,bit0~2
-        FLASH->ACR &= ~0x07;
-        FLASH->ACR |= 0x01;
-        //HCLK = SYSCLK
-        RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
-
-        //PCLK2 = HCLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
-
-        //PCLK1 = HCLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV1;
-        RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
-        RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
-
-        RCC->APB1ENR |= RCC_APB1ENR_PWR;
-        RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
-        RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos));
-        //Enable PLL
-        RCC->CR |= RCC_CR_PLLON;
-
-        //Wait till PLL is ready
-        while((RCC->CR & RCC_CR_PLLRDY) == 0) {
-        }
-
-        //Select PLL as system clock source
-        RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
-        RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
-
-        //Wait till PLL is used as system clock source
-        while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
-        }
-    }
-    else {
-        //If HSE fails to start-up, the application will have wrong clock
-        //configuration. User can add here some code to deal with this error
-    }
-}
-#elif defined SYSCLK_FREQ_48MHz
-
-/// @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
-///         and PCLK1 prescalers.
-/// @note   This function should be used only after reset.
-/// @param  None
-/// @retval None
-
-static void SetSysClockTo48(void)
-{
-    __IO u32 StartUpCounter = 0, HSEStatus = 0;
-    s32 i;
-    //SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
-    //Enable HSE
-    RCC->CR |= ((u32)RCC_CR_HSEON);
-
-    //Wait till HSE is ready and if Time out is reached exit
-    do {
-        HSEStatus = RCC->CR & RCC_CR_HSERDY;
-        StartUpCounter++;
-    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-    if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
-        HSEStatus = (u32)0x01;
-        i = 2000;
-        while(i--);
-    }
-    else {
-        HSEStatus = (u32)0x00;
-    }
-
-    if (HSEStatus == (u32)0x01) {
-        //Enable Prefetch Buffer
-        FLASH->ACR |= FLASH_ACR_PRFTBE;
-        //Flash 0 wait state ,bit0~2
-        FLASH->ACR &= ~0x07;
-        FLASH->ACR |= 0x02;
-        //HCLK = SYSCLK
-        RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV1;
-
-        //PCLK2 = HCLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
-
-        //PCLK1 = HCLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
-
-        // PLL configuration:  = (HSE ) * (5+1) = 48MHz
-        RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
-        RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
-
-        RCC->APB1ENR |= RCC_APB1ENR_PWR;
-        RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
-        RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos));
-        //Enable PLL
-        RCC->CR |= RCC_CR_PLLON;
-
-        //Wait till PLL is ready
-        while((RCC->CR & RCC_CR_PLLRDY) == 0) {
-        }
-
-        //Select PLL as system clock source
-        RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
-        RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
-
-        //Wait till PLL is used as system clock source
-        while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)0x08) {
-        }
-    }
-    else {
-        //If HSE fails to start-up, the application will have wrong clock
-        //configuration. User can add here some code to deal with this error
-    }
-}
-#elif defined SYSCLK_FREQ_XXMHz
-
-/// @brief  Sets System clock frequency to XXMHz and configure HCLK, PCLK2
-///         and PCLK1 prescalers.
-/// @note   This function should be used only after reset.
-/// @param  None
-/// @retval None
-
-static void SetSysClockToXX(void)
-{
-    __IO u32 temp, tn, tm;//j,
-    __IO u32 StartUpCounter = 0, HSEStatus = 0;
-
-    u8 plln, pllm;
-
-    RCC->CR |= RCC_CR_HSION;
-    while(!(RCC->CR & RCC_CR_HSIRDY));
-    //PLL SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------
-    //Enable HSE
-    RCC->CR |= ((u32)RCC_CR_HSEON);
-
-    DELAY_xUs(5);
-
-    if(SystemCoreClock > 96000000) {
-        RCC->APB1ENR |= RCC_APB1ENR_PWR;
-        PWR->CR &= ~(3 << 14);
-        PWR->CR |= 3 << 14;
-    }
-    //Wait till HSE is ready and if Time out is reached exit
-    while(1) {
-        HSEStatus = RCC->CR & RCC_CR_HSERDY;
-        if(HSEStatus != 0)
-            break;
-        StartUpCounter++;
-        if(StartUpCounter >= (10 * HSE_STARTUP_TIMEOUT))
-            return;
-    }
-
-    if ((RCC->CR & RCC_CR_HSERDY) == RESET) {
-        //If HSE fails to start-up, the application will have wrong clock
-        //configuration. User can add here some code to deal with this error
-        HSEStatus = (u32)0x00;
-        return;
-    }
-
-    HSEStatus = (u32)0x01;
-    DELAY_xUs(5);
-
-    SystemCoreClock         = SYSCLK_FREQ_XXMHz;
-    //Enable Prefetch Buffer
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-    //Flash 0 wait state ,bit0~2
-    FLASH->ACR &= ~FLASH_ACR_LATENCY;
-    temp = (SystemCoreClock - 1) / 24000000;
-    FLASH->ACR |= (temp & FLASH_ACR_LATENCY);
-    RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2);
-
-    //HCLK = AHB = FCLK = SYSCLK divided by 4
-    RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4;
-
-    //PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK
-    RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
-
-    if(SystemCoreClock > 72000000) {
-        //PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4;
-    }
-    else if(SystemCoreClock > 36000000) {
-        //PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
-    }
-
-    AutoCalPllFactor(HSE_VALUE, SystemCoreClock, &plln, &pllm);
-
-    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
-    RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
-
-    tm = (((u32)pllm) & 0x07);
-    tn = (((u32)plln) & 0x7F);
-
-    RCC->APB1ENR |= RCC_APB1ENR_PWR;
-    RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
-    RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos));
-    //Enable PLL
-    RCC->CR |= RCC_CR_PLLON;
-    //Wait till PLL is ready
-    while((RCC->CR & RCC_CR_PLLRDY) == 0) {
-        __ASM ("nop") ;//__NOP();
-    }
-    //Select PLL as system clock source
-    RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
-    RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
-
-    //Wait till PLL is used as system clock source
-    while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) {
-        __ASM ("nop") ;//__NOP();
-    }
-
-    DELAY_xUs(1);
-    // set HCLK = AHB = FCLK = SYSCLK divided by 2
-    RCC->CFGR &= (~(RCC_CFGR_PPRE_0));
-    DELAY_xUs(1);
-
-    // set HCLK = AHB = FCLK = SYSCLK divided by 1
-    RCC->CFGR &= (~(RCC_CFGR_PPRE_3));
-
-    DELAY_xUs(1);
-
-}
-#elif defined SYSCLK_HSI_24MHz
-void SetSysClockTo24_HSI(void)
-{
-    u8 temp = 0;
-
-    RCC->CR |= RCC_CR_HSION;
-
-    while(!(RCC->CR & RCC_CR_HSIRDY));
-    FLASH->ACR = FLASH_ACR_PRFTBE;
-
-    RCC->CFGR = RCC_CFGR_PPRE1_2;
-    // PLL configuration:  = (HSI = 8M ) * (2+1)/(0+1) = 24 MHz
-    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
-    RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
-
-    RCC->APB1ENR |= RCC_APB1ENR_PWR;
-    RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
-    RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (2 << RCC_PLLCFGR_PLL_DP_Pos));
-
-
-    RCC->CR |= RCC_CR_PLLON;
-
-    while(!(RCC->CR & RCC_CR_PLLRDY));
-
-    RCC->CFGR &= ~RCC_CFGR_SW;
-
-    RCC->CFGR |= RCC_CFGR_SW_PLL;
-
-    while(temp != 0x02) {
-        temp = RCC->CFGR >> 2;
-        temp &= 0x03;
-    }
-}
-
-#elif defined SYSCLK_HSI_36MHz
-void SetSysClockTo36_HSI(void)
-{
-    u8 temp = 0;
-
-    RCC->CR |= RCC_CR_HSION;
-
-    while(!(RCC->CR & RCC_CR_HSIRDY));
-    FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE;
-    RCC->CFGR = RCC_CFGR_PPRE1_2;
-    // PLL configuration:  = (HSI = 8M ) * (8+1)/(1+1) = 36 MHz
-    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
-    RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
-
-    RCC->APB1ENR |= RCC_APB1ENR_PWR;
-    RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
-    RCC->PLLCFGR |= ((1 << RCC_PLLCFGR_PLL_DN_Pos) | (8 << RCC_PLLCFGR_PLL_DP_Pos));
-
-    RCC->CR |= RCC_CR_PLLON;
-
-    while(!(RCC->CR & RCC_CR_PLLRDY));
-
-    RCC->CFGR &= ~ RCC_CFGR_SW;
-
-    RCC->CFGR |= RCC_CFGR_SW_PLL;
-
-    while(temp != 0x02) {
-        temp = RCC->CFGR >> 2;
-        temp &= 0x03;
-    }
-}
-
-#elif defined SYSCLK_HSI_48MHz
-void SetSysClockTo48_HSI(void)
-{
-    u8 temp = 0;
-
-    RCC->CR |= RCC_CR_HSION;
-
-    while(!(RCC->CR & RCC_CR_HSIRDY));
-    FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE;
-    RCC->CFGR = RCC_CFGR_PPRE1_2;
-
-
-
-
-
-    // PLL configuration:  = (HSI = 8M ) * (5+1)/(0+1) = 36 MHz
-    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
-    RCC->PLLCFGR |= (u32 ) RCC_PLLCFGR_PLLSRC  ;
-
-    RCC->APB1ENR |= RCC_APB1ENR_PWR;
-    RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
-    RCC->PLLCFGR |= ((0 << RCC_PLLCFGR_PLL_DN_Pos) | (5 << RCC_PLLCFGR_PLL_DP_Pos));
-
-    RCC->CR |= RCC_CR_PLLON;
-
-    while(!(RCC->CR & RCC_CR_PLLRDY));
-
-    RCC->CFGR &= ~RCC_CFGR_SW;
-
-    RCC->CFGR |= RCC_CFGR_SW_PLL;
-
-    while(temp != 0x02) {
-        temp = RCC->CFGR >> 2;
-        temp &= 0x03;
-    }
-}
-#elif defined SYSCLK_HSI_XXMHz
-
-
-static void SetSysClockToXX_HSI(void)
-{
-    __IO u32 temp, tn, tm;
-    u8 plln, pllm;
-
-    RCC->CR |= RCC_CR_HSION;
-    while(!(RCC->CR & RCC_CR_HSIRDY));
-
-    if(SystemCoreClock > 96000000) {
-        RCC->APB1ENR |= RCC_APB1ENR_PWR;
-        PWR->CR &= ~(3 << 14);
-        PWR->CR |= 3 << 14;
-    }
-
-
-
-    SystemCoreClock         = SYSCLK_HSI_XXMHz;
-    //Enable Prefetch Buffer
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-    //Flash 0 wait state ,bit0~2
-    FLASH->ACR &= ~FLASH_ACR_LATENCY;
-
-    temp = (SystemCoreClock - 1) / 24000000;
-
-    FLASH->ACR |= (temp & FLASH_ACR_LATENCY);
-
-
-    RCC->CFGR &= (~RCC_CFGR_HPRE) & ( ~RCC_CFGR_PPRE1) & (~RCC_CFGR_PPRE2);
-    //HCLK = AHB = FCLK = SYSCLK divided by 4
-    RCC->CFGR |= (u32)RCC_CFGR_HPRE_DIV4;
-
-    //PCLK2 = APB2 = HCLK divided by 1, APB2 is high APB CLK
-    RCC->CFGR |= (u32)RCC_CFGR_PPRE2_DIV1;
-
-    if(SystemCoreClock > 72000000) {
-        //PCLK1 = APB1 = HCLK divided by 4, APB1 is low APB CLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV4;
-    }
-    else if(SystemCoreClock > 36000000) {
-        //PCLK1 = APB1 = HCLK divided by 2, APB1 is low APB CLK
-        RCC->CFGR |= (u32)RCC_CFGR_PPRE1_DIV2;
-    }
-
-
-
-    AutoCalPllFactor(HSI_VALUE_PLL_ON, SystemCoreClock, &plln, &pllm);
-
-    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLXTPRE) ;
-    RCC->PLLCFGR &= ~((u32 ) RCC_PLLCFGR_PLLSRC);
-
-    tm = (((u32)pllm) & 0x07);
-    tn = (((u32)plln) & 0x7F);
-
-    RCC->APB1ENR |= RCC_APB1ENR_PWR;
-    RCC->PLLCFGR &= (u32)((~RCC_PLLCFGR_PLL_DN) & (~RCC_PLLCFGR_PLL_DP));
-    RCC->PLLCFGR |= ((tn << RCC_PLLCFGR_PLL_DN_Pos) | (tm << RCC_PLLCFGR_PLL_DP_Pos));
-    //Enable PLL
-    RCC->CR |= RCC_CR_PLLON;
-    //Wait till PLL is ready
-    while((RCC->CR & RCC_CR_PLLRDY) == 0) {
-        __ASM ("nop") ;//__NOP();
-    }
-    //Select PLL as system clock source
-    RCC->CFGR &= (u32)((u32)~(RCC_CFGR_SW));
-    RCC->CFGR |= (u32)RCC_CFGR_SW_PLL;
-
-    //Wait till PLL is used as system clock source
-    while ((RCC->CFGR & (u32)RCC_CFGR_SWS) != (u32)RCC_CFGR_SWS_PLL) {
-        __ASM ("nop") ;//__NOP();
-    }
-
-    DELAY_xUs(1);
-    // set HCLK = AHB = FCLK = SYSCLK divided by 2
-    RCC->CFGR &= (~(RCC_CFGR_PPRE_0));
-    DELAY_xUs(1);
-
-    // set HCLK = AHB = FCLK = SYSCLK divided by 1
-    RCC->CFGR &= (~(RCC_CFGR_PPRE_3));
-
-    DELAY_xUs(1);
-
-}
-
-#endif
-
-
-
-/// @}
-
-
-
-/// @}
-
-
-
-/// @}
-
-
-

From 7b27607f1ae68b1348e12e3fb0264474bb825f9e Mon Sep 17 00:00:00 2001
From: zhangslice <1304224508@qq.com>
Date: Mon, 7 Jun 2021 16:58:27 +0800
Subject: [PATCH 0085/2085] mit  license

Signed-off-by: zhangslice <1304224508@qq.com>
---
 src/portable/mm32/dcd_mm32f327x_otg.c | 41 ++++++++++++++++-----------
 1 file changed, 25 insertions(+), 16 deletions(-)

diff --git a/src/portable/mm32/dcd_mm32f327x_otg.c b/src/portable/mm32/dcd_mm32f327x_otg.c
index 914bbb38c..e7518830e 100644
--- a/src/portable/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mm32/dcd_mm32f327x_otg.c
@@ -1,19 +1,28 @@
-////////////////////////////////////////////////////////////////////////////////
-/// @file     dcd_mm32f327x_otg.c
-/// @author   SE TEAM
-/// @brief    tinyusb driver.
-////////////////////////////////////////////////////////////////////////////////
-/// @attention
-///
-/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
-/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
-/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
-/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
-/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
-/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
-///
-/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
-////////////////////////////////////////////////////////////////////////////////
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
 
 #include "tusb_option.h"
 #include "reg_usb_otg_fs.h"

From 85f8047ac4f9bfd08e04d29b5c294c8a4547f94c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Jun 2021 17:09:22 +0700
Subject: [PATCH 0086/2085] remove the keil zip

---
 tinyusb_keil.zip | Bin 1001190 -> 0 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 tinyusb_keil.zip

diff --git a/tinyusb_keil.zip b/tinyusb_keil.zip
deleted file mode 100644
index 6b178fcfc3c8d45f0b6515d2311d571bce2ccb69..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 1001190
zcmb5Tb8s&(^FCVJc6(~uHa@j&yFImS+qP}nwr!iIz3=y@JC}2BX0qAr>?VIao6R$c
zf;1=?8qj|=3I745|EBy80so)T+0xF##mPwD+SJm9LE(S6LIJS@M3r3Lk|%6{fq?YD
zfPg6f&#t1THm1&|(qd9F<WfRPDyFs$;+8h1PV`2G&ZbFyazl(rqi)5$BBu!A)ft+U
z;C}}6$Qp2KIb%(EWcM2cWh80qlOup1;AnY4P^3U-+$_s}Zu|PWh8tA4Gb4E#7Yg$5
zzMG`CQ@yNU@PW;0nWKAp&@EBs$>IOhvS#2K<kg%Ym_Mz0R0tC#c?sE?oqfRC!WtJQ
zOGYNV0#9h<57J}T_)jJ)Hkc?Sw^reZIePy-KfM0*c=*0&%*fBm6Y6v5=P`7#N^q$(
z;7n*{)1q;17zxR2k<A7&g#AhdDGrcfm33Y&+=C{ZnbHfRruP=(jQ1jdYopHUl46i(
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E4|7Af;s5{u


From 0ae83458d517777c9f37857a182b0553dd647ffe Mon Sep 17 00:00:00 2001
From: zhangslice <1304224508@qq.com>
Date: Thu, 17 Jun 2021 17:11:37 +0800
Subject: [PATCH 0087/2085] dsp updata

Signed-off-by: zhangslice <1304224508@qq.com>
---
 hw/bsp/mm32/mm32f327x/flash.ld         | 163 +++++++++++++++++++++++++
 hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c | 161 ++++++++++++++++++++++++
 2 files changed, 324 insertions(+)
 create mode 100644 hw/bsp/mm32/mm32f327x/flash.ld
 create mode 100644 hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c

diff --git a/hw/bsp/mm32/mm32f327x/flash.ld b/hw/bsp/mm32/mm32f327x/flash.ld
new file mode 100644
index 000000000..d96d6e43d
--- /dev/null
+++ b/hw/bsp/mm32/mm32f327x/flash.ld
@@ -0,0 +1,163 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2001FFFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c b/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c
new file mode 100644
index 000000000..39b264b70
--- /dev/null
+++ b/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c
@@ -0,0 +1,161 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "mm32_device.h"
+#include "hal_conf.h"
+#include "tusb.h"
+#include "../board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler(void)
+{
+	dcd_int_handler(TUD_OPT_RHPORT);
+
+}
+void USB_DeviceClockInit(void)
+{
+    /* Select USBCLK source */
+    //  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
+    RCC->CFGR &= ~(0x3 << 22);
+    RCC->CFGR |= (0x1 << 22);
+
+    /* Enable USB clock */
+    RCC->AHB2ENR |= 0x1 << 7;
+}
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+
+void board_led_write(bool state);
+extern u32 SystemCoreClock;
+const int baudrate = 115200;
+
+void board_init(void)
+{
+//   usb clock	
+  USB_DeviceClockInit();
+
+	if (SysTick_Config(SystemCoreClock / 1000)) {
+			while (1);
+	}
+	NVIC_SetPriority(SysTick_IRQn, 0x0);
+
+  // LED
+	GPIO_InitTypeDef  GPIO_InitStruct;
+	RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
+	GPIO_StructInit(&GPIO_InitStruct);
+	GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15);                      //Disable JTDI   AF to  AF15
+
+	GPIO_InitStruct.GPIO_Pin  =  GPIO_Pin_15;
+	GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+	board_led_write(true);
+
+  // UART
+	UART_InitTypeDef UART_InitStruct;
+
+	RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE);   //enableUART1,GPIOAclock
+	RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);  //
+	//UART initialset
+
+	GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
+	GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
+
+
+	UART_StructInit(&UART_InitStruct);
+	UART_InitStruct.UART_BaudRate = baudrate;
+	UART_InitStruct.UART_WordLength = UART_WordLength_8b;
+	UART_InitStruct.UART_StopBits = UART_StopBits_1;//one stopbit
+	UART_InitStruct.UART_Parity = UART_Parity_No;//none odd-even  verify bit
+	UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;//No hardware flow control
+	UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; // receive and sent  mode
+
+	UART_Init(UART1, &UART_InitStruct); //initial uart 1
+	UART_Cmd(UART1, ENABLE);                    //enable uart 1
+
+	//UART1_TX   GPIOA.9
+	GPIO_StructInit(&GPIO_InitStruct);
+	GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
+	GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+	//UART1_RX    GPIOA.10
+	GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
+	GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
+	GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+	state ? (GPIO_ResetBits(GPIOA,GPIO_Pin_15)):(GPIO_SetBits(GPIOA,GPIO_Pin_15));
+}
+
+uint32_t board_button_read(void)
+{
+  return 0;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+	const char *buff = buf;
+	while(len){
+		while((UART1->CSR & UART_IT_TXIEN) == 0); //The loop is sent until it is finished
+		UART1->TDR = (*buff & 0xFF);
+		buff++;
+		len--;
+	}
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif

From 5006b1065a21099d3c62bf2ea3ecf6c1e82d2723 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Jun 2021 12:49:41 +0700
Subject: [PATCH 0088/2085] remove duplicate mm32 dcd

---
 src/portable/mm32/dcd_mm32f327x_otg.c | 471 --------------------------
 1 file changed, 471 deletions(-)
 delete mode 100644 src/portable/mm32/dcd_mm32f327x_otg.c

diff --git a/src/portable/mm32/dcd_mm32f327x_otg.c b/src/portable/mm32/dcd_mm32f327x_otg.c
deleted file mode 100644
index e7518830e..000000000
--- a/src/portable/mm32/dcd_mm32f327x_otg.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 SE TEAM
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-#include "reg_usb_otg_fs.h"
-#include "mm32_device.h"
-#include "hal_conf.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MM32F327X )
-
-#include "device/dcd.h"
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-enum {
-  TOK_PID_OUT   = 0x1u,
-  TOK_PID_IN    = 0x9u,
-  TOK_PID_SETUP = 0xDu,
-};
-
-typedef struct TU_ATTR_PACKED
-{
-  union {
-    uint32_t head;
-    struct {
-      union {
-        struct {
-          uint16_t          :  2;
-          uint16_t tok_pid  :  4;
-          uint16_t data     :  1;
-          uint16_t own      :  1;
-          uint16_t          :  8;
-        };
-        struct {
-          uint16_t          :  2;
-          uint16_t bdt_stall:  1;
-          uint16_t dts      :  1;
-          uint16_t ninc     :  1;
-          uint16_t keep     :  1;
-          uint16_t          : 10;
-        };
-      };
-      uint16_t bc          : 10;
-      uint16_t             :  6;
-    };
-  };
-  uint8_t *addr;
-}buffer_descriptor_t;
-
-TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
-
-typedef struct TU_ATTR_PACKED
-{
-  union {
-    uint32_t state;
-    struct {
-      uint32_t max_packet_size :11;
-      uint32_t                 : 5;
-      uint32_t odd             : 1;
-      uint32_t                 :15;
-    };
-  };
-  uint16_t length;
-  uint16_t remaining;
-}endpoint_state_t;
-
-TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
-
-typedef struct
-{
-  union {
-    /* [#EP][OUT,IN][EVEN,ODD] */
-    buffer_descriptor_t bdt[16][2][2];
-    uint16_t            bda[512];
-  };
-  TU_ATTR_ALIGNED(4) union {
-    endpoint_state_t endpoint[16][2];
-    endpoint_state_t endpoint_unified[16 * 2];
-  };
-  uint8_t setup_packet[8];
-  uint8_t addr;
-}dcd_data_t;
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-// BDT(Buffer Descriptor Table) must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
-
-TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
-
-static void prepare_next_setup_packet(uint8_t rhport)
-{
-  const unsigned out_odd = _dcd.endpoint[0][0].odd;
-  const unsigned in_odd  = _dcd.endpoint[0][1].odd;
-  if (_dcd.bdt[0][0][out_odd].own) {
-    TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd);
-    return;
-  }
-  _dcd.bdt[0][0][out_odd].data     = 0;
-  _dcd.bdt[0][0][out_odd ^ 1].data = 1;
-  _dcd.bdt[0][1][in_odd].data      = 1;
-  _dcd.bdt[0][1][in_odd ^ 1].data  = 0;
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
-                _dcd.setup_packet, sizeof(_dcd.setup_packet));
-}
-
-static void process_stall(uint8_t rhport)
-{
-  if (USB_OTG_FS->EP_CTL[0] & USB_ENDPT_EPSTALL_MASK) {
-    /* clear stall condition of the control pipe */
-    prepare_next_setup_packet(rhport);
-    USB_OTG_FS->EP_CTL[0] &= ~USB_ENDPT_EPSTALL_MASK;
-  }
-}
-
-static void process_tokdne(uint8_t rhport)
-{
-  const unsigned s = USB_OTG_FS->STAT;
-  USB_OTG_FS->INT_STAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
-  buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
-  endpoint_state_t    *ep = &_dcd.endpoint_unified[s >> 3];
-  unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0;
-
-  /* fetch pid before discarded by the next steps */
-  const unsigned pid = bd->tok_pid;
-  /* reset values for a next transfer */
-  bd->bdt_stall = 0;
-  bd->dts       = 1;
-  bd->ninc      = 0;
-  bd->keep      = 0;
-  /* update the odd variable to prepare for the next transfer */
-  ep->odd       = odd ^ 1;
-  if (pid == TOK_PID_SETUP) {
-    dcd_event_setup_received(rhport, bd->addr, true);
-    USB_OTG_FS->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
-    return;
-  }
-  if (s >> 4) {
-    TU_LOG1("TKDNE %x\r\n", s);
-  }
-
-  const unsigned bc = bd->bc;
-  const unsigned remaining = ep->remaining - bc;
-  if (remaining && bc == ep->max_packet_size) {
-    /* continue the transferring consecutive data */
-    ep->remaining = remaining;
-    const int next_remaining = remaining - ep->max_packet_size;
-    if (next_remaining > 0) {
-      /* prepare to the after next transfer */
-      bd->addr += ep->max_packet_size * 2;
-      bd->bc    = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
-      __DSB();
-      bd->own   = 1; /* the own bit must set after addr */
-    }
-    return;
-  }
-  const unsigned length = ep->length;
-  dcd_event_xfer_complete(rhport,
-                          ((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT),
-                          length - remaining, XFER_RESULT_SUCCESS, true);
-  if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) {
-    /* After completion a ZLP of control transfer,
-     * it prepares for the next steup transfer. */
-    if (_dcd.addr) {
-      /* When the transfer was the SetAddress,
-       * the device address should be updated here. */
-      USB_OTG_FS->ADDR = _dcd.addr;
-      _dcd.addr  = 0;
-    }
-    prepare_next_setup_packet(rhport);
-  }
-}
-
-static void process_bus_reset(uint8_t rhport)
-{
-  USB_OTG_FS->CTL     |= USB_CTL_ODDRST_MASK;
-  USB_OTG_FS->ADDR     = 0;
-  USB_OTG_FS->INT_ENB    = (USB_OTG_FS->INT_ENB & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
-
-  USB_OTG_FS->EP_CTL[0] = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
-  for (unsigned i = 1; i < 16; ++i) {
-    USB_OTG_FS->EP_CTL[i] = 0;
-  }
-  buffer_descriptor_t *bd = _dcd.bdt[0][0];
-  for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
-    bd->head = 0;
-  }
-  const endpoint_state_t ep0 = {
-    .max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
-    .odd             = 0,
-    .length          = 0,
-    .remaining       = 0,
-  };
-  _dcd.endpoint[0][0] = ep0;
-  _dcd.endpoint[0][1] = ep0;
-  tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
-  _dcd.addr = 0;
-  prepare_next_setup_packet(rhport);
-  USB_OTG_FS->CTL &= ~USB_CTL_ODDRST_MASK;
-  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
-}
-
-static void process_bus_inactive(uint8_t rhport)
-{
-  (void) rhport;
-  const unsigned inten = USB_OTG_FS->INT_ENB;
-  USB_OTG_FS->INT_ENB    = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
-  dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-}
-
-static void process_bus_active(uint8_t rhport)
-{
-  (void) rhport;
-  const unsigned inten = USB_OTG_FS->INT_ENB;
-  USB_OTG_FS->INT_ENB    = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
-  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-}
-
-/*------------------------------------------------------------------*/
-/* Device API
- *------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
-  (void) rhport;
-
-  tu_memclr(&_dcd, sizeof(_dcd));
-  USB_OTG_FS->BDT_PAGE_01 = (uint8_t)((uintptr_t)_dcd.bdt >>  8);
-  USB_OTG_FS->BDT_PAGE_02 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
-  USB_OTG_FS->BDT_PAGE_03 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
-
-  dcd_connect(rhport);
-  NVIC_ClearPendingIRQ(USB_FS_IRQn);
-}
-#define USB_DEVICE_INTERRUPT_PRIORITY (3U)
-void dcd_int_enable(uint8_t rhport)
-{
-  uint8_t irqNumber;
-  irqNumber = USB_FS_IRQn;
-  (void) rhport;
-  USB_OTG_FS->INT_ENB = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK |
-    USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
-  NVIC_SetPriority((IRQn_Type)irqNumber, USB_DEVICE_INTERRUPT_PRIORITY);
-  NVIC_EnableIRQ(USB_FS_IRQn);
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(USB_FS_IRQn);
-  USB_OTG_FS->INT_ENB = 0;
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  (void) rhport;
-  _dcd.addr = dev_addr & 0x7F;
-  /* Response with status first before changing device address */
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-}
-extern u32 SystemCoreClock ;
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
-  unsigned cnt = SystemCoreClock / 100;
-  USB_OTG_FS->CTL |= USB_CTL_RESUME_MASK;
-  while (cnt--) __NOP();
-  USB_OTG_FS->CTL &= ~USB_CTL_RESUME_MASK;
-}
-
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_FS->CTL     |= USB_CTL_USBENSOFEN_MASK;
-}
-
-void dcd_disconnect(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_FS->CTL      = 0;
-}
-
-//--------------------------------------------------------------------+
-// Endpoint API
-//--------------------------------------------------------------------+
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
-{
-  (void) rhport;
-
-  const unsigned ep_addr  = ep_desc->bEndpointAddress;
-  const unsigned epn      = ep_addr & 0xFu;
-  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
-  const unsigned xfer     = ep_desc->bmAttributes.xfer;
-  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
-  const unsigned odd      = ep->odd;
-  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
-
-  /* No support for control transfer */
-  TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
-
-  ep->max_packet_size = ep_desc->wMaxPacketSize.size;
-  unsigned val = USB_ENDPT_EPCTLDIS_MASK;
-  val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
-  val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
-  USB_OTG_FS->EP_CTL[epn] |= val;
-
-  if (xfer != TUSB_XFER_ISOCHRONOUS) {
-    bd[odd].dts      = 1;
-    bd[odd].data     = 0;
-    bd[odd ^ 1].dts  = 1;
-    bd[odd ^ 1].data = 1;
-  }
-
-  return true;
-}
-
-void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  const unsigned epn      = ep_addr & 0xFu;
-  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
-  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
-  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
-  const unsigned msk      = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
-  USB_OTG_FS->EP_CTL[epn] &= ~msk;
-  ep->max_packet_size = 0;
-  ep->length          = 0;
-  ep->remaining       = 0;
-  bd->head            = 0;
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
-{
-  (void) rhport;
-  NVIC_DisableIRQ(USB_FS_IRQn);
-  const unsigned epn = ep_addr & 0xFu;
-  const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
-  endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
-  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
-
-  if (bd->own) {
-    TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head);
-    return false; /* The last transfer has not completed */
-  }
-  ep->length    = total_bytes;
-  ep->remaining = total_bytes;
-
-  const unsigned mps = ep->max_packet_size;
-  if (total_bytes > mps) {
-    buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
-    /* When total_bytes is greater than the max packet size,
-     * it prepares to the next transfer to avoid NAK in advance. */
-    next->bc   = total_bytes >= 2 * mps ? mps: total_bytes - mps;
-    next->addr = buffer + mps;
-    next->own  = 1;
-  }
-  bd->bc        = total_bytes >= mps ? mps: total_bytes;
-  bd->addr      = buffer;
-  __DSB();
-  bd->own  = 1; /* the own bit must set after addr */
-  NVIC_EnableIRQ(USB_FS_IRQn);
-  return true;
-}
-
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-  const unsigned epn = ep_addr & 0xFu;
-  if (0 == epn) {
-    USB_OTG_FS->EP_CTL[epn] |=  USB_ENDPT_EPSTALL_MASK;
-  } else {
-    const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
-    buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
-    bd[0].bdt_stall = 1;
-    bd[1].bdt_stall = 1;
-  }
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-  const unsigned epn      = ep_addr & 0xFu;
-  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
-  const unsigned odd      = _dcd.endpoint[epn][dir].odd;
-  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
-
-  bd[odd ^ 1].own       = 0;
-  bd[odd ^ 1].data      = 1;
-  bd[odd ^ 1].bdt_stall = 0;
-  bd[odd].own           = 0;
-  bd[odd].data          = 0;
-  bd[odd].bdt_stall     = 0;
-}
-
-//--------------------------------------------------------------------+
-// ISR
-//--------------------------------------------------------------------+
-void dcd_int_handler(uint8_t rhport)
-{
-  (void) rhport;
-
-  uint32_t is  = USB_OTG_FS->INT_STAT;
-  uint32_t msk = USB_OTG_FS->INT_ENB;
-  USB_OTG_FS->INT_STAT = is & ~msk;
-  is &= msk;
-  if (is & USB_ISTAT_ERROR_MASK) {
-    /* TODO: */
-    uint32_t es = USB_OTG_FS->ERR_STAT;
-    USB_OTG_FS->ERR_STAT = es;
-    USB_OTG_FS->INT_STAT   = is; /* discard any pending events */
-    return;
-  }
-
-  if (is & USB_ISTAT_USBRST_MASK) {
-    USB_OTG_FS->INT_STAT = is; /* discard any pending events */
-    process_bus_reset(rhport);
-    return;
-  }
-  if (is & USB_ISTAT_SLEEP_MASK) {
-    USB_OTG_FS->INT_STAT = USB_ISTAT_SLEEP_MASK;
-    process_bus_inactive(rhport);
-    return;
-  }
-  if (is & USB_ISTAT_RESUME_MASK) {
-    USB_OTG_FS->INT_STAT = USB_ISTAT_RESUME_MASK;
-    process_bus_active(rhport);
-    return;
-  }
-  if (is & USB_ISTAT_SOFTOK_MASK) {
-    USB_OTG_FS->INT_STAT = USB_ISTAT_SOFTOK_MASK;
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-    return;
-  }
-  if (is & USB_ISTAT_STALL_MASK) {
-    USB_OTG_FS->INT_STAT = USB_ISTAT_STALL_MASK;
-    process_stall(rhport);
-    return;
-  }
-  if (is & USB_ISTAT_TOKDNE_MASK) {
-    process_tokdne(rhport);
-    return;
-  }
-}
-
-#endif

From 82618d2d5f15d0f8dd9631dec3807964a1281782 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Jun 2021 17:18:11 +0700
Subject: [PATCH 0089/2085] fix build with mm32 board

---
 .../cdc_msc_freertos/src/FreeRTOSConfig.h     |   5 +
 .../src/FreeRTOSConfig.h                      |   4 +
 hw/bsp/board_mcu.h                            |   2 +
 hw/bsp/mm32/boards/mm32f327x_mb39/board.mk    |   8 +
 .../mm32f327x_mb39}/flash.ld                  |   0
 .../boards/mm32f327x_mb39/mm32f327x_mb39.c    | 172 ++++++++++++++++++
 hw/bsp/mm32/family.mk                         |  36 ++++
 hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c        | 161 ----------------
 src/class/cdc/cdc_device.h                    |   6 +-
 src/class/vendor/vendor_device.h              |   8 +-
 src/common/tusb_common.h                      |  32 ++--
 .../mindmotion/mm32/dcd_mm32f327x_otg.c       |   2 +-
 12 files changed, 251 insertions(+), 185 deletions(-)
 create mode 100644 hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
 rename hw/bsp/mm32/{mm32f327x => boards/mm32f327x_mb39}/flash.ld (100%)
 create mode 100644 hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
 create mode 100644 hw/bsp/mm32/family.mk
 delete mode 100644 hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c

diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
index b76d59706..c9f553f64 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
@@ -45,7 +45,12 @@
 // Include MCU header
 #include "bsp/board_mcu.h"
 
+// TODO fix later
+#if CFG_TUSB_MCU == OPT_MCU_MM32F327X
+extern u32 SystemCoreClock;
+#else
 extern uint32_t SystemCoreClock;
+#endif
 
 /* Cortex M23/M33 port configuration. */
 #define configENABLE_MPU								        0
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
index b76d59706..99c5bc328 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
@@ -45,7 +45,11 @@
 // Include MCU header
 #include "bsp/board_mcu.h"
 
+#if CFG_TUSB_MCU == OPT_MCU_MM32F327X
+extern u32 SystemCoreClock;
+#else
 extern uint32_t SystemCoreClock;
+#endif
 
 /* Cortex M23/M33 port configuration. */
 #define configENABLE_MPU								        0
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 1a659c410..c9d143bd7 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -130,6 +130,8 @@
 #elif CFG_TUSB_MCU == OPT_MCU_RX63X
   // no header needed
 
+#elif CFG_TUSB_MCU == OPT_MCU_MM32F327X
+  #include "mm32_device.h"
 #else
   #error "Missing MCU header"
 #endif
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
new file mode 100644
index 000000000..b7663926f
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
@@ -0,0 +1,8 @@
+LD_FILE = $(BOARD_PATH)/flash.ld
+SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
+
+# For flash-jlink target
+#JLINK_DEVICE = stm32f411ve
+
+# flash target using on-board stlink
+#flash: flash-jlink
diff --git a/hw/bsp/mm32/mm32f327x/flash.ld b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
similarity index 100%
rename from hw/bsp/mm32/mm32f327x/flash.ld
rename to hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
new file mode 100644
index 000000000..cff7bc15e
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
@@ -0,0 +1,172 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "mm32_device.h"
+#include "hal_conf.h"
+#include "tusb.h"
+#include "../board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler (void)
+{
+  tud_int_handler(0);
+
+}
+void USB_DeviceClockInit (void)
+{
+  /* Select USBCLK source */
+  //  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
+  RCC->CFGR &= ~(0x3 << 22);
+  RCC->CFGR |= (0x1 << 22);
+
+  /* Enable USB clock */
+  RCC->AHB2ENR |= 0x1 << 7;
+}
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+
+void board_led_write (bool state);
+extern u32 SystemCoreClock;
+const int baudrate = 115200;
+
+void board_init (void)
+{
+//   usb clock	
+  USB_DeviceClockInit();
+
+  if ( SysTick_Config(SystemCoreClock / 1000) )
+  {
+    while ( 1 )
+      ;
+  }
+  NVIC_SetPriority(SysTick_IRQn, 0x0);
+
+  // LED
+  GPIO_InitTypeDef GPIO_InitStruct;
+  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
+  GPIO_StructInit(&GPIO_InitStruct);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15);                      //Disable JTDI   AF to  AF15
+
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_15;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  board_led_write(true);
+
+  // UART
+  UART_InitTypeDef UART_InitStruct;
+
+  RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE);    //enableUART1,GPIOAclock
+  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);    //
+  //UART initialset
+
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
+
+  UART_StructInit(&UART_InitStruct);
+  UART_InitStruct.UART_BaudRate = baudrate;
+  UART_InitStruct.UART_WordLength = UART_WordLength_8b;
+  UART_InitStruct.UART_StopBits = UART_StopBits_1;    //one stopbit
+  UART_InitStruct.UART_Parity = UART_Parity_No;    //none odd-even  verify bit
+  UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;    //No hardware flow control
+  UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx;    // receive and sent  mode
+
+  UART_Init(UART1, &UART_InitStruct);    //initial uart 1
+  UART_Cmd(UART1, ENABLE);                    //enable uart 1
+
+  //UART1_TX   GPIOA.9
+  GPIO_StructInit(&GPIO_InitStruct);
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  //UART1_RX    GPIOA.10
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write (bool state)
+{
+  state ? (GPIO_ResetBits(GPIOA, GPIO_Pin_15)) : (GPIO_SetBits(GPIOA, GPIO_Pin_15));
+}
+
+uint32_t board_button_read (void)
+{
+  return 0;
+}
+
+int board_uart_read (uint8_t *buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write (void const *buf, int len)
+{
+  const char *buff = buf;
+  while ( len )
+  {
+    while ( (UART1->CSR & UART_IT_TXIEN) == 0 )
+      ;    //The loop is sent until it is finished
+    UART1->TDR = (*buff & 0xFF);
+    buff++;
+    len--;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis (void)
+{
+  return system_ticks;
+}
+#endif
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk
new file mode 100644
index 000000000..3273ff870
--- /dev/null
+++ b/hw/bsp/mm32/family.mk
@@ -0,0 +1,36 @@
+UF2_FAMILY_ID = 0x0
+SDK_DIR = hw/mcu/mindmotion/mm32sdk
+DEPS_SUBMODULES += lib/CMSIS_5 $(SDK_DIR)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m3 \
+  -mfloat-abi=soft \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_MM32F327X 
+
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized
+
+SRC_C += \
+	src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c \
+	$(SDK_DIR)/mm32f327x/MM32F327x/Source/system_mm32f327x.c \
+	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c \
+	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c \
+	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c \
+	
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/Include \
+	$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Inc
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM3
+
+# flash target using on-board
+flash: flash-jlink
diff --git a/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c b/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c
deleted file mode 100644
index 39b264b70..000000000
--- a/hw/bsp/mm32/mm32f327x/mm32f327x_mb39.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020 MM32 SE TEAM
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "mm32_device.h"
-#include "hal_conf.h"
-#include "tusb.h"
-#include "../board.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-	dcd_int_handler(TUD_OPT_RHPORT);
-
-}
-void USB_DeviceClockInit(void)
-{
-    /* Select USBCLK source */
-    //  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
-    RCC->CFGR &= ~(0x3 << 22);
-    RCC->CFGR |= (0x1 << 22);
-
-    /* Enable USB clock */
-    RCC->AHB2ENR |= 0x1 << 7;
-}
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-// LED
-
-void board_led_write(bool state);
-extern u32 SystemCoreClock;
-const int baudrate = 115200;
-
-void board_init(void)
-{
-//   usb clock	
-  USB_DeviceClockInit();
-
-	if (SysTick_Config(SystemCoreClock / 1000)) {
-			while (1);
-	}
-	NVIC_SetPriority(SysTick_IRQn, 0x0);
-
-  // LED
-	GPIO_InitTypeDef  GPIO_InitStruct;
-	RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
-	GPIO_StructInit(&GPIO_InitStruct);
-	GPIO_PinAFConfig(GPIOA, GPIO_PinSource15, GPIO_AF_15);                      //Disable JTDI   AF to  AF15
-
-	GPIO_InitStruct.GPIO_Pin  =  GPIO_Pin_15;
-	GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
-	GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-	board_led_write(true);
-
-  // UART
-	UART_InitTypeDef UART_InitStruct;
-
-	RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE);   //enableUART1,GPIOAclock
-	RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);  //
-	//UART initialset
-
-	GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
-	GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
-
-
-	UART_StructInit(&UART_InitStruct);
-	UART_InitStruct.UART_BaudRate = baudrate;
-	UART_InitStruct.UART_WordLength = UART_WordLength_8b;
-	UART_InitStruct.UART_StopBits = UART_StopBits_1;//one stopbit
-	UART_InitStruct.UART_Parity = UART_Parity_No;//none odd-even  verify bit
-	UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;//No hardware flow control
-	UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; // receive and sent  mode
-
-	UART_Init(UART1, &UART_InitStruct); //initial uart 1
-	UART_Cmd(UART1, ENABLE);                    //enable uart 1
-
-	//UART1_TX   GPIOA.9
-	GPIO_StructInit(&GPIO_InitStruct);
-	GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
-	GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
-	GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-	//UART1_RX    GPIOA.10
-	GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
-	GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
-	GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-	state ? (GPIO_ResetBits(GPIOA,GPIO_Pin_15)):(GPIO_SetBits(GPIOA,GPIO_Pin_15));
-}
-
-uint32_t board_button_read(void)
-{
-  return 0;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-	const char *buff = buf;
-	while(len){
-		while((UART1->CSR & UART_IT_TXIEN) == 0); //The loop is sent until it is finished
-		UART1->TDR = (*buff & 0xFF);
-		buff++;
-		len--;
-	}
-  return len;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index 7ff757add..72e29705a 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -82,7 +82,7 @@ int32_t  tud_cdc_n_read_char       (uint8_t itf);
 void     tud_cdc_n_read_flush      (uint8_t itf);
 
 // Get a byte from FIFO at the specified position without removing it
-bool     tud_cdc_n_peek            (uint8_t itf, uint8_t* u8);
+bool     tud_cdc_n_peek            (uint8_t itf, uint8_t* uv8);
 
 // Write bytes to TX FIFO, data may remain in the FIFO for a while
 uint32_t tud_cdc_n_write           (uint8_t itf, void const* buffer, uint32_t bufsize);
@@ -206,9 +206,9 @@ static inline void tud_cdc_read_flush (void)
   tud_cdc_n_read_flush(0);
 }
 
-static inline bool tud_cdc_peek (uint8_t* u8)
+static inline bool tud_cdc_peek (uint8_t* uv8)
 {
-  return tud_cdc_n_peek(0, u8);
+  return tud_cdc_n_peek(0, uv8);
 }
 
 static inline uint32_t tud_cdc_write_char (char ch)
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index 6d9c784c0..b54194271 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -44,7 +44,7 @@ bool     tud_vendor_n_mounted         (uint8_t itf);
 
 uint32_t tud_vendor_n_available       (uint8_t itf);
 uint32_t tud_vendor_n_read            (uint8_t itf, void* buffer, uint32_t bufsize);
-bool     tud_vendor_n_peek            (uint8_t itf, uint8_t* u8);
+bool     tud_vendor_n_peek            (uint8_t itf, uint8_t* uv8);
 
 uint32_t tud_vendor_n_write           (uint8_t itf, void const* buffer, uint32_t bufsize);
 uint32_t tud_vendor_n_write_available (uint8_t itf);
@@ -58,7 +58,7 @@ uint32_t tud_vendor_n_write_str       (uint8_t itf, char const* str);
 static inline bool     tud_vendor_mounted         (void);
 static inline uint32_t tud_vendor_available       (void);
 static inline uint32_t tud_vendor_read            (void* buffer, uint32_t bufsize);
-static inline bool     tud_vendor_peek            (uint8_t* u8);
+static inline bool     tud_vendor_peek            (uint8_t* uv8);
 static inline uint32_t tud_vendor_write           (void const* buffer, uint32_t bufsize);
 static inline uint32_t tud_vendor_write_str       (char const* str);
 static inline uint32_t tud_vendor_write_available (void);
@@ -94,9 +94,9 @@ static inline uint32_t tud_vendor_read (void* buffer, uint32_t bufsize)
   return tud_vendor_n_read(0, buffer, bufsize);
 }
 
-static inline bool tud_vendor_peek (uint8_t* u8)
+static inline bool tud_vendor_peek (uint8_t* uv8)
 {
-  return tud_vendor_n_peek(0, u8);
+  return tud_vendor_n_peek(0, uv8);
 }
 
 static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize)
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 889ad7b25..ece5d800a 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -38,18 +38,18 @@
 #define TU_MIN(_x, _y)        ( ( (_x) < (_y) ) ? (_x) : (_y) )
 #define TU_MAX(_x, _y)        ( ( (_x) > (_y) ) ? (_x) : (_y) )
 
-#define TU_U16_HIGH(u16)      ((uint8_t) (((u16) >> 8) & 0x00ff))
-#define TU_U16_LOW(u16)       ((uint8_t) ((u16)       & 0x00ff))
-#define U16_TO_U8S_BE(u16)    TU_U16_HIGH(u16), TU_U16_LOW(u16)
-#define U16_TO_U8S_LE(u16)    TU_U16_LOW(u16), TU_U16_HIGH(u16)
+#define TU_U16_HIGH(_u16)      ((uint8_t) (((_u16) >> 8) & 0x00ff))
+#define TU_U16_LOW(_u16)       ((uint8_t) ((_u16)       & 0x00ff))
+#define U16_TO_U8S_BE(_u16)    TU_U16_HIGH(_u16), TU_U16_LOW(_u16)
+#define U16_TO_U8S_LE(_u16)    TU_U16_LOW(_u16), TU_U16_HIGH(_u16)
 
-#define TU_U32_BYTE3(u32)     ((uint8_t) ((((uint32_t) u32) >> 24) & 0x000000ff)) // MSB
-#define TU_U32_BYTE2(u32)     ((uint8_t) ((((uint32_t) u32) >> 16) & 0x000000ff))
-#define TU_U32_BYTE1(u32)     ((uint8_t) ((((uint32_t) u32) >>  8) & 0x000000ff))
-#define TU_U32_BYTE0(u32)     ((uint8_t) (((uint32_t)  u32)        & 0x000000ff)) // LSB
+#define TU_U32_BYTE3(_u32)     ((uint8_t) ((((uint32_t) _u32) >> 24) & 0x000000ff)) // MSB
+#define TU_U32_BYTE2(_u32)     ((uint8_t) ((((uint32_t) _u32) >> 16) & 0x000000ff))
+#define TU_U32_BYTE1(_u32)     ((uint8_t) ((((uint32_t) _u32) >>  8) & 0x000000ff))
+#define TU_U32_BYTE0(_u32)     ((uint8_t) (((uint32_t)  _u32)        & 0x000000ff)) // LSB
 
-#define U32_TO_U8S_BE(u32)    TU_U32_BYTE3(u32), TU_U32_BYTE2(u32), TU_U32_BYTE1(u32), TU_U32_BYTE0(u32)
-#define U32_TO_U8S_LE(u32)    TU_U32_BYTE0(u32), TU_U32_BYTE1(u32), TU_U32_BYTE2(u32), TU_U32_BYTE3(u32)
+#define U32_TO_U8S_BE(_u32)    TU_U32_BYTE3(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE0(_u32)
+#define U32_TO_U8S_LE(_u32)    TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32)
 
 #define TU_BIT(n)             (1UL << (n))
 
@@ -88,13 +88,13 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low)
   return (uint16_t) ((((uint16_t) high) << 8) | low);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte3(uint32_t u32) { return TU_U32_BYTE3(u32); }
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t u32) { return TU_U32_BYTE2(u32); }
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t u32) { return TU_U32_BYTE1(u32); }
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t u32) { return TU_U32_BYTE0(u32); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte3(uint32_t uv32) { return TU_U32_BYTE3(uv32); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t uv32) { return TU_U32_BYTE2(uv32); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t uv32) { return TU_U32_BYTE1(uv32); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t uv32) { return TU_U32_BYTE0(uv32); }
 
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t u16) { return TU_U16_HIGH(u16); }
-TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t u16) { return TU_U16_LOW(u16); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t uv16) { return TU_U16_HIGH(uv16); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t uv16) { return TU_U16_LOW(uv16); }
 
 //------------- Bits -------------//
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_set  (uint32_t value, uint8_t pos) { return value | TU_BIT(pos);                  }
diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
index 59a40dc68..31b1f7080 100644
--- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -283,7 +283,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   /* Response with status first before changing device address */
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
-extern u32 SystemCoreClock ;
+extern u32 SystemCoreClock;
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;

From 1b33504e14d3bde9b85c436952a1c66af429ea63 Mon Sep 17 00:00:00 2001
From: sabas1080 <sabasjimenez@gmail.com>
Date: Fri, 18 Jun 2021 11:11:26 -0500
Subject: [PATCH 0090/2085] add saml21 to CI

---
 .github/workflows/build.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 529a77bb1..1e149dc65 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -49,6 +49,7 @@ jobs:
         - 'samd11'
         - 'samd21'
         - 'samd51'
+        - 'saml21'
         - 'saml22'
         - 'stm32f0'
         - 'stm32f4'

From 6b621baeb33c08ac92e8e94950250c0923da975e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Jun 2021 01:58:27 +0700
Subject: [PATCH 0091/2085] fix race condition with control since
 TASKS_EP0RCVOUT also require EasyDMA

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 59 +++++++++++++++++++--------
 1 file changed, 41 insertions(+), 18 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 977ec6cdb..b3b2dec2d 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -108,13 +108,21 @@ static inline uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn)
 }
 #endif
 
+// check if we are in ISR
+TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
+{
+  return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) ? true : false;
+}
+
 // helper to start DMA
+// TODO use Cortex M4 LDREX and STREX command (atomic) to have better mutex access to EasyDMA
+// since current implementation does not 100% guarded against race condition
 static void edpt_dma_start(volatile uint32_t* reg_startep)
 {
   // Only one dma can be active
   if ( _dcd.dma_pending )
   {
-    if (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk)
+    if (is_in_isr())
     {
       // Called within ISR, use usbd task to defer later
       usbd_defer_func( (osal_task_func_t) edpt_dma_start, (void*) reg_startep, true );
@@ -159,6 +167,17 @@ static void edpt_dma_end(void)
   _dcd.dma_pending = 0;
 }
 
+// helper to set TASKS_EP0STATUS / TASKS_EP0RCVOUT since they also need EasyDMA
+// However TASKS_EP0STATUS doesn't trigger any DMA transfer and got ENDED event subsequently
+// Therefore dma_running state will be corrected right away
+void start_ep0_task(volatile uint32_t* reg_task)
+{
+  edpt_dma_start(reg_task);
+
+  // correct the dma_running++ in dma start
+  if (_dcd.dma_pending) _dcd.dma_pending--;
+}
+
 // helper getting td
 static inline xfer_td_t* get_td(uint8_t epnum, uint8_t dir)
 {
@@ -407,21 +426,18 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 
   if ( control_status )
   {
-    // Status Phase also requires Easy DMA has to be available as well !!!!
-    // However TASKS_EP0STATUS doesn't trigger any DMA transfer and got ENDED event subsequently
-    // Therefore dma_running state will be corrected right away
-    edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
-    if (_dcd.dma_pending) _dcd.dma_pending--; // correct the dma_running++ in dma start
+    // Status Phase also requires EasyDMA has to be available as well !!!!
+    start_ep0_task(&NRF_USBD->TASKS_EP0STATUS);
 
     // The nRF doesn't interrupt on status transmit so we queue up a success response.
-    dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, false);
+    dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, is_in_isr());
   }
   else if ( dir == TUSB_DIR_OUT )
   {
     if ( epnum == 0 )
     {
-      // Accept next Control Out packet
-      NRF_USBD->TASKS_EP0RCVOUT = 1;
+      // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA
+      start_ep0_task(&NRF_USBD->TASKS_EP0RCVOUT);
     }else
     {
       if ( xfer->data_received )
@@ -581,12 +597,6 @@ void dcd_int_handler(uint8_t rhport)
     }
   }
 
-  if ( int_status & EDPT_END_ALL_MASK )
-  {
-    // DMA complete move data from SRAM -> Endpoint
-    edpt_dma_end();
-  }
- 
   // Setup tokens are specific to the Control endpoint.
   if ( int_status & USBD_INTEN_EP0SETUP_Msk )
   {
@@ -607,6 +617,12 @@ void dcd_int_handler(uint8_t rhport)
     }
   }
 
+  if ( int_status & EDPT_END_ALL_MASK )
+  {
+    // DMA complete move data from SRAM -> Endpoint
+    edpt_dma_end();
+  }
+
   //--------------------------------------------------------------------+
   /* Control/Bulk/Interrupt (CBI) Transfer
    *
@@ -655,8 +671,15 @@ void dcd_int_handler(uint8_t rhport)
       {
         if ( epnum == 0 )
         {
-          // Accept next Control Out packet
-          NRF_USBD->TASKS_EP0RCVOUT = 1;
+          // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA
+          if ( _dcd.dma_pending )
+          {
+            // use usbd task to defer later
+            usbd_defer_func( (osal_task_func_t) start_ep0_task, (void*) &NRF_USBD->TASKS_EP0RCVOUT, true );
+          }else
+          {
+            start_ep0_task(&NRF_USBD->TASKS_EP0RCVOUT);
+          }
         }else
         {
           // nRF auto accept next Bulk/Interrupt OUT packet
@@ -973,7 +996,7 @@ void tusb_hal_nrf_power_event (uint32_t event)
 
         hfclk_disable();
 
-        dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) ? true : false);
+        dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, is_in_isr());
       }
     break;
 

From 76336a67a05ee4b6676a438578819a48cb0f0420 Mon Sep 17 00:00:00 2001
From: Ned Konz <ned@productcreationstudio.com>
Date: Fri, 18 Jun 2021 14:50:55 -0700
Subject: [PATCH 0092/2085] Changed order of struct initializer to avoid
 compiler error

---
 src/common/tusb_fifo.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index cf299269d..de2ae163d 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -86,8 +86,8 @@ typedef struct
   .depth                = _depth,                           \
   .item_size            = sizeof(_type),                    \
   .overwritable         = _overwritable,                    \
-  .max_pointer_idx      = 2*(_depth)-1,                     \
   .non_used_index_space = UINT16_MAX - (2*(_depth)-1),      \
+  .max_pointer_idx      = 2*(_depth)-1,                     \
 }
 
 #define TU_FIFO_DEF(_name, _depth, _type, _overwritable)                      \

From 7dce27c732d8411229007282a34dec43acc6f76b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Jun 2021 16:21:14 +0700
Subject: [PATCH 0093/2085] fix build with saml21, update microchip driver
 submodule

---
 hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld | 1 +
 hw/mcu/microchip                                       | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld b/hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld
index 42f1de8d4..7f6b7fa99 100644
--- a/hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld
+++ b/hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld
@@ -135,6 +135,7 @@ SECTIONS
         . = ALIGN(4);
         _ebss = . ;
         _ezero = .;
+        end = .;
     } > ram
 
     /* stack section */
diff --git a/hw/mcu/microchip b/hw/mcu/microchip
index f7087f047..58eb37632 160000
--- a/hw/mcu/microchip
+++ b/hw/mcu/microchip
@@ -1 +1 @@
-Subproject commit f7087f04783c896627061fc151fa3527b73733c7
+Subproject commit 58eb3763200ff51a998be5f537acf67299add227

From fbda7d58370663e57bde8e011c7045fa85beb397 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 20 Jun 2021 15:04:39 +0700
Subject: [PATCH 0094/2085] adding rx65n

---
 hw/bsp/rx63n/boards/gr_citrus/board.mk        |   8 -
 hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk  |  52 ++++
 .../rx63n/boards/rx65n_cloud_kit/r5f565ne.ld  | 158 ++++++++++++
 .../boards/rx65n_cloud_kit/rx65n_cloud_kit.c  | 243 ++++++++++++++++++
 hw/bsp/rx63n/family.mk                        |  18 +-
 src/tusb_option.h                             |   1 +
 6 files changed, 471 insertions(+), 9 deletions(-)
 create mode 100644 hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
 create mode 100644 hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
 create mode 100644 hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c

diff --git a/hw/bsp/rx63n/boards/gr_citrus/board.mk b/hw/bsp/rx63n/boards/gr_citrus/board.mk
index feab5b5e6..6edd588bc 100644
--- a/hw/bsp/rx63n/boards/gr_citrus/board.mk
+++ b/hw/bsp/rx63n/boards/gr_citrus/board.mk
@@ -1,18 +1,10 @@
 DEPS_SUBMODULES += hw/mcu/renesas/rx
 
 CFLAGS += \
-  -nostartfiles \
-  -ffunction-sections \
-  -fdata-sections \
-  -fshort-enums \
   -mcpu=rx610 \
   -misa=v1 \
-  -mlittle-endian-data \
   -DCFG_TUSB_MCU=OPT_MCU_RX63X
 
-# Cross Compiler for RX
-CROSS_COMPILE = rx-elf-
-
 RX_NEWLIB ?= 1
 
 ifeq ($(CMDEXE),1)
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
new file mode 100644
index 000000000..87cbd74a8
--- /dev/null
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
@@ -0,0 +1,52 @@
+CFLAGS += \
+  -mcpu=rx64m \
+  -misa=v2 \
+  -DCFG_TUSB_MCU=OPT_MCU_RX65X
+
+RX_NEWLIB ?= 1
+
+ifeq ($(CMDEXE),1)
+OPTLIBINC="$(shell for /F "usebackq delims=" %%i in (`where rx-elf-gcc`) do echo %%~dpi..\rx-elf\optlibinc)"
+else
+OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
+endif
+
+ifeq ($(RX_NEWLIB),1)
+CFLAGS += -DSSIZE_MAX=__INT_MAX__
+else
+# setup for optlib
+CFLAGS += -nostdinc \
+  -isystem $(OPTLIBINC) \
+  -DLWIP_NO_INTTYPES_H
+
+LIBS += -loptc -loptm
+endif
+
+MCU_DIR = hw/mcu/renesas/rx/rx65n
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/r5f565ne.ld
+
+SRC_C += \
+	src/portable/renesas/usba/dcd_usba.c \
+	$(MCU_DIR)/vects.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MCU_DIR)
+
+SRC_S += $(MCU_DIR)/start.S
+
+# For freeRTOS port source
+FREERTOS_PORT = RX600
+
+# For flash-jlink target
+JLINK_DEVICE = R5F565NE
+JLINK_IF     = JTAG
+
+# For flash-pyocd target
+PYOCD_TARGET =
+
+# flash using rfp-cli
+flash: $(BUILD)/$(PROJECT).mot
+	rfp-cli -device rx65x -tool e2l -auto $^
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld b/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
new file mode 100644
index 000000000..8d4806f09
--- /dev/null
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
@@ -0,0 +1,158 @@
+MEMORY
+{
+	RAM : ORIGIN = 0x0, LENGTH = 262144
+	RAM2 : ORIGIN = 0x00800000, LENGTH = 393216
+	ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152
+	OFS : ORIGIN = 0xFE7F5D00, LENGTH = 128
+}
+SECTIONS
+{
+	.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
+	{
+		KEEP(*(.exvectors))
+	} > ROM
+	.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
+	{
+		KEEP(*(.fvectors))
+	} > ROM
+	.text 0xFFE00000: AT(0xFFE00000)
+	{
+		*(.text)
+		*(.text.*)
+		*(P)
+		etext = .;
+	} > ROM
+	.rvectors ALIGN(4):
+	{
+		_rvectors_start = .;
+		KEEP(*(.rvectors))
+		_rvectors_end = .;
+	} > ROM
+	.init :
+	{
+		KEEP(*(.init))
+		__preinit_array_start = .;
+		KEEP(*(.preinit_array))
+		__preinit_array_end = .;
+		__init_array_start = (. + 3) & ~ 3;
+		KEEP(*(.init_array))
+		KEEP(*(SORT(.init_array.*)))
+		__init_array_end = .;
+		__fini_array_start = .;
+		KEEP(*(.fini_array))
+		KEEP(*(SORT(.fini_array.*)))
+		__fini_array_end = .;
+	} > ROM
+	.fini :
+	{
+		KEEP(*(.fini))
+	} > ROM
+	.got :
+	{
+		*(.got)
+		*(.got.plt)
+	} > ROM
+	.rodata :
+	{
+		*(.rodata)
+		*(.rodata.*)
+		*(C_1)
+		*(C_2)
+		*(C)
+		_erodata = .;
+	} > ROM
+	.eh_frame_hdr :
+	{
+		*(.eh_frame_hdr)
+	} > ROM
+	.eh_frame :
+	{
+		*(.eh_frame)
+	} > ROM
+	.jcr :
+	{
+		*(.jcr)
+	} > ROM
+	.tors :
+	{
+		__CTOR_LIST__ = .;
+		. = ALIGN(2);
+		___ctors = .;
+		*(.ctors)
+		___ctors_end = .;
+		__CTOR_END__ = .;
+		__DTOR_LIST__ = .;
+		___dtors = .;
+		*(.dtors)
+		___dtors_end = .;
+		__DTOR_END__ = .;
+		. = ALIGN(2);
+		_mdata = .;
+	} > ROM
+	.ustack 0x200: AT(0x200)
+	{
+		_ustack = .;
+	} > RAM
+	.istack 0x100: AT(0x100)
+	{
+		_istack = .;
+	} > RAM
+	.data 0x204: AT(_mdata)
+	{
+		_data = .;
+		*(.data)
+		*(.data.*)
+		*(D)
+		*(D_1)
+		*(D_2)
+		_edata = .;
+	} > RAM
+	.gcc_exc :
+	{
+		*(.gcc_exc)
+	} > RAM
+	.bss :
+	{
+		_bss = .;
+		*(.bss)
+		*(.bss.**)
+		*(COMMON)
+		*(B)
+		*(B_1)
+		*(B_2)
+		_ebss = .;
+		_end = .;
+	} > RAM
+	.ofs1 0xFE7F5D00: AT(0xFE7F5D00)
+	{
+		KEEP(*(.ofs1))
+	} > OFS
+	.ofs2 0xFE7F5D10: AT(0xFE7F5D10)
+	{
+		KEEP(*(.ofs2))
+	} > OFS
+	.ofs3 0xFE7F5D20: AT(0xFE7F5D20)
+	{
+		KEEP(*(.ofs3))
+	} > OFS
+	.ofs4 0xFE7F5D40: AT(0xFE7F5D40)
+	{
+		KEEP(*(.ofs4))
+	} > OFS
+	.ofs5 0xFE7F5D48: AT(0xFE7F5D48)
+	{
+		KEEP(*(.ofs5))
+	} > OFS
+	.ofs6 0xFE7F5D50: AT(0xFE7F5D50)
+	{
+		KEEP(*(.ofs6))
+	} > OFS
+	.ofs7 0xFE7F5D64: AT(0xFE7F5D64)
+	{
+		KEEP(*(.ofs7))
+	} > OFS
+	.ofs8 0xFE7F5D70: AT(0xFE7F5D70)
+	{
+		KEEP(*(.ofs8))
+	} > OFS
+}
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
new file mode 100644
index 000000000..0853763c8
--- /dev/null
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
@@ -0,0 +1,243 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+#include "iodefine.h"
+#include "interrupt_handlers.h"
+
+#define IRQ_PRIORITY_CMT0     5
+#define IRQ_PRIORITY_USBI0    6
+#define IRQ_PRIORITY_SCI0     5
+
+#define SYSTEM_PRCR_PRC1      (1<<1)
+#define SYSTEM_PRCR_PRKEY     (0xA5u<<8)
+
+#define CMT_PCLK              48000000
+#define CMT_CMCR_CKS_DIV_128  2
+#define CMT_CMCR_CMIE         (1<<6)
+#define MPC_PFS_ISEL          (1<<6)
+
+#define SCI_PCLK              48000000
+#define SCI_SSR_FER           (1<<4)
+#define SCI_SSR_ORER          (1<<5)
+
+#define SCI_SCR_TEIE          (1u<<2)
+#define SCI_SCR_RE            (1u<<4)
+#define SCI_SCR_TE            (1u<<5)
+#define SCI_SCR_RIE           (1u<<6)
+#define SCI_SCR_TIE           (1u<<7)
+
+void HardwareSetup(void)
+{
+/*
+ BSC.CS0MOD.WORD = 0x1234;
+ BSC.CS7CNT.WORD = 0x5678;
+
+ SCI0.SCR.BIT.TE  = 0;
+ SCI0.SCR.BIT.RE  = 0;
+ SCI0.SCR.BIT.TE  = 1;
+ SCI2.SSR.BIT.PER = 0;
+
+ TMR0.TCR.BYTE = 0x12;
+ TMR1.TCR.BYTE = 0x12;
+ TMR2.TCR.BYTE = 0x12;
+
+ P0.DDR.BYTE = 0x12;
+ P1.DDR.BYTE = 0x12;
+*/
+}
+
+//--------------------------------------------------------------------+
+// SCI0 handling
+//--------------------------------------------------------------------+
+typedef struct {
+  uint8_t *buf;
+  uint32_t cnt;
+} sci_buf_t;
+static volatile sci_buf_t sci0_buf[2];
+
+void INT_Excep_SCI0_TXI0(void)
+{
+  uint8_t *buf = sci0_buf[0].buf;
+  uint32_t cnt = sci0_buf[0].cnt;
+  
+  if (!buf || !cnt) {
+    SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
+    return;
+  }
+  SCI0.TDR = *buf;
+  if (--cnt) {
+    ++buf;
+  } else {
+    buf = NULL;
+    SCI0.SCR.BIT.TIE  = 0;
+    SCI0.SCR.BIT.TEIE = 1;
+  }
+  sci0_buf[0].buf = buf;
+  sci0_buf[0].cnt = cnt;
+}
+
+void INT_Excep_SCI0_TEI0(void)
+{
+  SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
+}
+
+void INT_Excep_SCI0_RXI0(void)
+{
+  uint8_t *buf = sci0_buf[1].buf;
+  uint32_t cnt = sci0_buf[1].cnt;
+
+  if (!buf || !cnt ||
+      (SCI0.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
+    sci0_buf[1].buf = NULL;
+    SCI0.SSR.BYTE   = 0;
+    SCI0.SCR.BYTE  &= ~(SCI_SCR_RE | SCI_SCR_RIE);
+    return;
+  }
+  *buf = SCI0.RDR;
+  if (--cnt) {
+    ++buf;
+  } else {
+    buf = NULL;
+    SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
+  }
+  sci0_buf[1].buf = buf;
+  sci0_buf[1].cnt = cnt;
+}
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void INT_Excep_USB0_USBI0(void)
+{
+  tud_int_handler(0);
+}
+
+void board_init(void)
+{
+#if CFG_TUSB_OS == OPT_OS_NONE
+  /* Enable CMT0 */
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(CMT0)       = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+  /* Setup 1ms tick timer */
+  CMT0.CMCNT      = 0;
+  CMT0.CMCOR      = CMT_PCLK / 1000 / 128;
+  CMT0.CMCR.WORD  = CMT_CMCR_CMIE | CMT_CMCR_CKS_DIV_128;
+  IR(CMT0, CMI0)  = 0;
+  IPR(CMT0, CMI0) = IRQ_PRIORITY_CMT0;
+  IEN(CMT0, CMI0) = 1;
+  CMT.CMSTR0.BIT.STR0 = 1;
+#endif
+
+  /* Unlock MPC registers */
+  MPC.PWPR.BIT.B0WI  = 0;
+  MPC.PWPR.BIT.PFSWE = 1;
+  /* LED PA0 */
+  PORTA.PMR.BIT.B0  = 0U;
+  PORTA.PODR.BIT.B0 = 0U;
+  PORTA.PDR.BIT.B0  = 1U;
+  /* UART TXD0 => P20, RXD0 => P21 */
+  PORT2.PMR.BIT.B0 = 1U;
+  PORT2.PCR.BIT.B0 = 1U;
+  MPC.P20PFS.BYTE  = 0b01010;
+  PORT2.PMR.BIT.B1 = 1U;
+  MPC.P21PFS.BYTE  = 0b01010;
+  /* USB VBUS -> P16 DPUPE -> P14 */
+  PORT1.PMR.BIT.B4 = 1U;
+  PORT1.PMR.BIT.B6 = 1U;
+  MPC.P14PFS.BYTE  = 0b10001;
+  MPC.P16PFS.BYTE  = MPC_PFS_ISEL | 0b10001;
+//  MPC.PFUSB0.BIT.PUPHZS = 1;
+  /* Lock MPC registers */
+  MPC.PWPR.BIT.PFSWE = 0;
+  MPC.PWPR.BIT.B0WI  = 1;
+
+//  IR(USB0, USBI0)  = 0;
+//  IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
+
+  /* Enable SCI0 */
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(SCI0) = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+  SCI0.BRR = (SCI_PCLK / (32 * 115200)) - 1;
+//  IR(SCI0,  RXI0)  = 0;
+//  IR(SCI0,  TXI0)  = 0;
+//  IR(SCI0,  TEI0)  = 0;
+//  IPR(SCI0, RXI0) = IRQ_PRIORITY_SCI0;
+//  IPR(SCI0, TXI0) = IRQ_PRIORITY_SCI0;
+//  IPR(SCI0, TEI0) = IRQ_PRIORITY_SCI0;
+//  IEN(SCI0, RXI0) = 1;
+//  IEN(SCI0, TXI0) = 1;
+//  IEN(SCI0, TEI0) = 1;
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  PORTA.PODR.BIT.B0 = state ? 1 : 0;
+}
+
+uint32_t board_button_read(void)
+{
+  return 0;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  sci0_buf[1].buf = buf;
+  sci0_buf[1].cnt = len;
+  SCI0.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
+  while (SCI0.SCR.BIT.RE) ;
+  return len - sci0_buf[1].cnt;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+  sci0_buf[0].buf = (uint8_t*)buf;
+  sci0_buf[0].cnt = len;
+  SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
+  while (SCI0.SCR.BIT.TE) ;
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void INT_Excep_CMT0_CMI0(void)
+{
+  ++system_ticks;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#else
+uint32_t SystemCoreClock = 96000000;
+#endif
diff --git a/hw/bsp/rx63n/family.mk b/hw/bsp/rx63n/family.mk
index d3c743ed1..a9c74e6b0 100644
--- a/hw/bsp/rx63n/family.mk
+++ b/hw/bsp/rx63n/family.mk
@@ -1 +1,17 @@
-include $(TOP)/$(BOARD_PATH)/board.mk
\ No newline at end of file
+DEPS_SUBMODULES += hw/mcu/renesas/rx
+
+# Cross Compiler for RX
+CROSS_COMPILE = rx-elf-
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -nostartfiles \
+  -ffunction-sections \
+  -fdata-sections \
+  -fshort-enums \
+  -mlittle-endian-data \
+
+$(BUILD)/$(PROJECT).mot: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	$(OBJCOPY) -O srec -I elf32-rx-be-ns $^ $@
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 5cfcc08e2..5571c91d7 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -112,6 +112,7 @@
 
 // Renesas RX
 #define OPT_MCU_RX63X            1400 ///< Renesas RX63N/631
+#define OPT_MCU_RX65X            1401 ///< Renesas RX65N/RX651
 
 // Mind Motion
 #define OPT_MCU_MM32F327X        1500 ///< Mind Motion MM32F327

From 8433f638e64ce1b13fead28b4395d9a32c480548 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sun, 20 Jun 2021 15:38:20 +0200
Subject: [PATCH 0095/2085] Add bracket to switch case, fix warning.

---
 src/class/audio/audio_device.c | 229 +++++++++++++++++----------------
 1 file changed, 117 insertions(+), 112 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 8e4420ed0..7ad7edf9e 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -393,12 +393,12 @@ static uint8_t audiod_get_audio_fct_idx(audiod_function_t * audio);
 
 #if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING
 static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * p_desc, uint8_t const * p_desc_end, uint8_t const as_itf);
-#endif
 
 static inline uint8_t tu_desc_subtype(void const* desc)
 {
   return ((uint8_t const*) desc)[2];
 }
+#endif
 
 bool tud_audio_n_mounted(uint8_t func_id)
 {
@@ -1658,64 +1658,65 @@ static bool audiod_control_complete(uint8_t rhport, tusb_control_request_t const
 
     switch (p_request->bmRequestType_bit.recipient)
     {
-      case TUSB_REQ_RCPT_INTERFACE: ;       // The semicolon is there to enable a declaration right after the label
-
-      uint8_t itf = TU_U16_LOW(p_request->wIndex);
-      uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
-
-      if (entityID != 0)
+      case TUSB_REQ_RCPT_INTERFACE:
       {
-        if (tud_audio_set_req_entity_cb)
-        {
-          // Check if entity is present and get corresponding driver index
-          TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
+        uint8_t itf = TU_U16_LOW(p_request->wIndex);
+        uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
 
-          // Invoke callback
-          return tud_audio_set_req_entity_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
+        if (entityID != 0)
+        {
+          if (tud_audio_set_req_entity_cb)
+          {
+            // Check if entity is present and get corresponding driver index
+            TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
+
+            // Invoke callback
+            return tud_audio_set_req_entity_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
+          }
+          else
+          {
+            TU_LOG2("  No entity set request callback available!\r\n");
+            return false;     // In case no callback function is present or request can not be conducted we stall it
+          }
         }
         else
         {
-          TU_LOG2("  No entity set request callback available!\r\n");
-          return false;     // In case no callback function is present or request can not be conducted we stall it
+          if (tud_audio_set_req_itf_cb)
+          {
+            // Find index of audio driver structure and verify interface really exists
+            TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
+
+            // Invoke callback
+            return tud_audio_set_req_itf_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
+          }
+          else
+          {
+            TU_LOG2("  No interface set request callback available!\r\n");
+            return false;     // In case no callback function is present or request can not be conducted we stall it
+          }
         }
       }
-      else
-      {
-        if (tud_audio_set_req_itf_cb)
-        {
-          // Find index of audio driver structure and verify interface really exists
-          TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
-
-          // Invoke callback
-          return tud_audio_set_req_itf_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
-        }
-        else
-        {
-          TU_LOG2("  No interface set request callback available!\r\n");
-          return false;     // In case no callback function is present or request can not be conducted we stall it
-        }
-      }
-
       break;
 
-      case TUSB_REQ_RCPT_ENDPOINT: ;        // The semicolon is there to enable a declaration right after the label
-
-      uint8_t ep = TU_U16_LOW(p_request->wIndex);
-
-      if (tud_audio_set_req_ep_cb)
+      case TUSB_REQ_RCPT_ENDPOINT:
       {
-        // Check if entity is present and get corresponding driver index
-        TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
+        uint8_t ep = TU_U16_LOW(p_request->wIndex);
 
-        // Invoke callback
-        return tud_audio_set_req_ep_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
-      }
-      else
-      {
-        TU_LOG2("  No EP set request callback available!\r\n");
-        return false;   // In case no callback function is present or request can not be conducted we stall it
-      }
+        if (tud_audio_set_req_ep_cb)
+        {
+          // Check if entity is present and get corresponding driver index
+          TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
 
+          // Invoke callback
+          return tud_audio_set_req_ep_cb(rhport, p_request, _audiod_fct[func_id].ctrl_buf);
+        }
+        else
+        {
+          TU_LOG2("  No EP set request callback available!\r\n");
+          return false;   // In case no callback function is present or request can not be conducted we stall it
+        }
+      }
+      break;
       // Unknown/Unsupported recipient
       default: TU_BREAKPOINT(); return false;
     }
@@ -1754,69 +1755,71 @@ static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const
     // Conduct checks which depend on the recipient
     switch (p_request->bmRequestType_bit.recipient)
     {
-      case TUSB_REQ_RCPT_INTERFACE: ;       // The semicolon is there to enable a declaration right after the label
-
-      uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
-
-      // Verify if entity is present
-      if (entityID != 0)
+      case TUSB_REQ_RCPT_INTERFACE:
       {
-        // Find index of audio driver structure and verify entity really exists
-        TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
+        uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
 
-        // In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
-        if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
+        // Verify if entity is present
+        if (entityID != 0)
         {
-          if (tud_audio_get_req_entity_cb)
+          // Find index of audio driver structure and verify entity really exists
+          TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
+
+          // In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
+          if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
           {
-            return tud_audio_get_req_entity_cb(rhport, p_request);
-          }
-          else
-          {
-            TU_LOG2("  No entity get request callback available!\r\n");
-            return false;   // Stall
+            if (tud_audio_get_req_entity_cb)
+            {
+              return tud_audio_get_req_entity_cb(rhport, p_request);
+            }
+            else
+            {
+              TU_LOG2("  No entity get request callback available!\r\n");
+              return false;   // Stall
+            }
           }
         }
-      }
-      else
-      {
-        // Find index of audio driver structure and verify interface really exists
-        TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
-
-        // In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
-        if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
+        else
         {
-          if (tud_audio_get_req_itf_cb)
+          // Find index of audio driver structure and verify interface really exists
+          TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
+
+          // In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
+          if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
           {
-            return tud_audio_get_req_itf_cb(rhport, p_request);
-          }
-          else
-          {
-            TU_LOG2("  No interface get request callback available!\r\n");
-            return false;   // Stall
+            if (tud_audio_get_req_itf_cb)
+            {
+              return tud_audio_get_req_itf_cb(rhport, p_request);
+            }
+            else
+            {
+              TU_LOG2("  No interface get request callback available!\r\n");
+              return false;   // Stall
+            }
           }
         }
       }
       break;
 
-      case TUSB_REQ_RCPT_ENDPOINT: ;        // The semicolon is there to enable a declaration right after the label
-
-      uint8_t ep = TU_U16_LOW(p_request->wIndex);
-
-      // Find index of audio driver structure and verify EP really exists
-      TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
-
-      // In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
-      if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
+      case TUSB_REQ_RCPT_ENDPOINT:
       {
-        if (tud_audio_get_req_ep_cb)
+        uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+        // Find index of audio driver structure and verify EP really exists
+        TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
+
+        // In case we got a get request invoke callback - callback needs to answer as defined in UAC2 specification page 89 - 5. Requests
+        if (p_request->bmRequestType_bit.direction == TUSB_DIR_IN)
         {
-          return tud_audio_get_req_ep_cb(rhport, p_request);
-        }
-        else
-        {
-          TU_LOG2("  No EP get request callback available!\r\n");
-          return false;     // Stall
+          if (tud_audio_get_req_ep_cb)
+          {
+            return tud_audio_get_req_ep_cb(rhport, p_request);
+          }
+          else
+          {
+            TU_LOG2("  No EP get request callback available!\r\n");
+            return false;     // Stall
+          }
         }
       }
       break;
@@ -1935,29 +1938,31 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req
   // Conduct checks which depend on the recipient
   switch (p_request->bmRequestType_bit.recipient)
   {
-    case TUSB_REQ_RCPT_INTERFACE: ;     // The semicolon is there to enable a declaration right after the label
-
-    uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
-
-    // Verify if entity is present
-    if (entityID != 0)
+    case TUSB_REQ_RCPT_INTERFACE:
     {
-      // Find index of audio driver structure and verify entity really exists
-      TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
-    }
-    else
-    {
-      // Find index of audio driver structure and verify interface really exists
-      TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
+      uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+      // Verify if entity is present
+      if (entityID != 0)
+      {
+        // Find index of audio driver structure and verify entity really exists
+        TU_VERIFY(audiod_verify_entity_exists(itf, entityID, &func_id));
+      }
+      else
+      {
+        // Find index of audio driver structure and verify interface really exists
+        TU_VERIFY(audiod_verify_itf_exists(itf, &func_id));
+      }
     }
     break;
 
     case TUSB_REQ_RCPT_ENDPOINT: ;      // The semicolon is there to enable a declaration right after the label
+    {
+      uint8_t ep = TU_U16_LOW(p_request->wIndex);
 
-    uint8_t ep = TU_U16_LOW(p_request->wIndex);
-
-    // Find index of audio driver structure and verify EP really exists
-    TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
+      // Find index of audio driver structure and verify EP really exists
+      TU_VERIFY(audiod_verify_ep_exists(ep, &func_id));
+    }
     break;
 
     // Unknown/Unsupported recipient

From 9323a9d094684a25e65fcae964e7ee91c9746f57 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 21 Jun 2021 00:00:46 +0700
Subject: [PATCH 0096/2085] fix issue when calling midi API when not enumerated
 yet

---
 src/class/midi/midi_device.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 953ca26e6..4eac0de48 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -197,9 +197,11 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, ui
 
 bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4])
 {
-  midid_interface_t* p_midi = &_midid_itf[itf];
-  uint32_t num_read = tu_fifo_read_n(&p_midi->rx_ff, packet, 4);
-  _prep_out_transaction(p_midi);
+  midid_interface_t* midi = &_midid_itf[itf];
+  TU_VERIFY(midi->ep_out);
+
+  uint32_t const num_read = tu_fifo_read_n(&midi->rx_ff, packet, 4);
+  _prep_out_transaction(midi);
   return (num_read == 4);
 }
 
@@ -234,7 +236,7 @@ static uint32_t write_flush(midid_interface_t* midi)
 uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize)
 {
   midid_interface_t* midi = &_midid_itf[itf];
-  TU_VERIFY(midi->itf_num, 0);
+  TU_VERIFY(midi->ep_in, 0);
 
   midid_stream_t* stream = &midi->stream_write;
 
@@ -351,9 +353,7 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
 bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4])
 {
   midid_interface_t* midi = &_midid_itf[itf];
-  if (midi->itf_num == 0) {
-    return 0;
-  }
+  TU_VERIFY(midi->ep_in);
 
   if (tu_fifo_remaining(&midi->tx_ff) < 4) return false;
 
@@ -435,6 +435,7 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint
   }
 
   p_midi->itf_num = desc_midi->bInterfaceNumber;
+  (void) p_midi->itf_num;
 
   // next descriptor
   drv_len += tu_desc_len(p_desc);

From 264dc35b95a2313201845f3612d3e807afad62c3 Mon Sep 17 00:00:00 2001
From: Niklas Hauser <niklas.hauser@rwth-aachen.de>
Date: Mon, 21 Jun 2021 05:32:43 +0200
Subject: [PATCH 0097/2085] Fix typo in TUH configuration define

---
 examples/host/cdc_msc_hid/src/tusb_config.h | 2 +-
 src/class/hid/hid_host.c                    | 2 +-
 src/host/usbh.c                             | 4 ++--
 src/host/usbh_control.c                     | 2 +-
 src/tusb_option.h                           | 4 ++--
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 8253964c0..cc77b6554 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -72,7 +72,7 @@
 //--------------------------------------------------------------------
 
 // Size of buffer to hold descriptors and other data used for enumeration
-#define CFG_TUH_ENUMERATION_BUFSZIE 256
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
 
 #define CFG_TUH_HUB                 1
 #define CFG_TUH_CDC                 1
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index cde5e23a5..761258f1b 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -368,7 +368,7 @@ static bool config_get_report_desc(uint8_t dev_addr, tusb_control_request_t cons
 
   // Get Report Descriptor
   // using usbh enumeration buffer since report descriptor can be very long
-  TU_ASSERT( hid_itf->report_desc_len <= CFG_TUH_ENUMERATION_BUFSZIE );
+  TU_ASSERT( hid_itf->report_desc_len <= CFG_TUH_ENUMERATION_BUFSIZE );
 
   TU_LOG2("HID Get Report Descriptor\r\n");
   tusb_control_request_t const new_request =
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 59246a663..8ecc87488 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -130,7 +130,7 @@ CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1];
 OSAL_QUEUE_DEF(OPT_MODE_HOST, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSZIE];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
 //------------- Helper Function Prototypes -------------//
 static bool enum_new_device(hcd_event_t* event);
@@ -907,7 +907,7 @@ static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tusb_control_r
   // Use offsetof to avoid pointer to the odd/misaligned address
   memcpy(&total_len, (uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength), 2);
 
-  TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSZIE);
+  TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE);
 
   // Get full configuration descriptor
   TU_LOG2("Get Configuration Descriptor\r\n");
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index 4dbf8592a..53413b6e5 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -50,7 +50,7 @@ typedef struct
 static usbh_control_xfer_t _ctrl_xfer;
 
 //CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
-//static uint8_t _tuh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSZIE];
+//static uint8_t _tuh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
diff --git a/src/tusb_option.h b/src/tusb_option.h
index d5776c029..815e588de 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -278,8 +278,8 @@
     #error there is no benefit enable hub with max device is 1. Please disable hub or increase CFG_TUSB_HOST_DEVICE_MAX
   #endif
 
-  #ifndef CFG_TUH_ENUMERATION_BUFSZIE
-    #define CFG_TUH_ENUMERATION_BUFSZIE 256
+  #ifndef CFG_TUH_ENUMERATION_BUFSIZE
+    #define CFG_TUH_ENUMERATION_BUFSIZE 256
   #endif
 
   //------------- CLASS -------------//

From dccb3b1a4675b2ece3d860f5903eed70930b7478 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Tue, 22 Jun 2021 00:20:08 +0900
Subject: [PATCH 0098/2085] change stdio channel to SCI5 from SCI0. change
 ports settings for LED and button. add PLL setting for 240MHz based on HOCO
 into HardwareSetup().

---
 .../rx63n/boards/rx65n_cloud_kit/r5f565ne.ld  |  38 ++--
 .../boards/rx65n_cloud_kit/rx65n_cloud_kit.c  | 188 ++++++++++--------
 2 files changed, 130 insertions(+), 96 deletions(-)

diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld b/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
index 8d4806f09..a02f0c02f 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
@@ -1,16 +1,21 @@
+__USTACK_SIZE = 0x00000200;
+__ISTACK_SIZE = 0x00000200;
+
 MEMORY
 {
-	RAM : ORIGIN = 0x0, LENGTH = 262144
-	RAM2 : ORIGIN = 0x00800000, LENGTH = 393216
-	ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152
-	OFS : ORIGIN = 0xFE7F5D00, LENGTH = 128
+	RAM  : ORIGIN = 0x4,        LENGTH = 0x3fffc
+	RAM2 : ORIGIN = 0x00800000, LENGTH = 0x60000
+	OFS  : ORIGIN = 0xFE7F5D00, LENGTH = 128
+	ROM  : ORIGIN = 0xFFE00000, LENGTH = 0x200000
 }
 SECTIONS
 {
 	.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
 	{
+		"_exvectors_start" = .;
 		KEEP(*(.exvectors))
-	} > ROM
+		"_exvectors_end" = .;
+	} >ROM
 	.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
 	{
 		KEEP(*(.fvectors))
@@ -20,6 +25,7 @@ SECTIONS
 		*(.text)
 		*(.text.*)
 		*(P)
+		KEEP(*(.text.*_isr))
 		etext = .;
 	} > ROM
 	.rvectors ALIGN(4):
@@ -89,15 +95,7 @@ SECTIONS
 		. = ALIGN(2);
 		_mdata = .;
 	} > ROM
-	.ustack 0x200: AT(0x200)
-	{
-		_ustack = .;
-	} > RAM
-	.istack 0x100: AT(0x100)
-	{
-		_istack = .;
-	} > RAM
-	.data 0x204: AT(_mdata)
+	.data : AT(_mdata)
 	{
 		_data = .;
 		*(.data)
@@ -123,6 +121,18 @@ SECTIONS
 		_ebss = .;
 		_end = .;
 	} > RAM
+	.ustack :
+	{
+		. = ALIGN(8);
+		. = . + __USTACK_SIZE;
+		PROVIDE(_ustack = .);
+	} > RAM
+	.istack :
+	{
+		. = ALIGN(8);
+		. = . + __ISTACK_SIZE;
+		PROVIDE(_istack = .);
+	} > RAM
 	.ofs1 0xFE7F5D00: AT(0xFE7F5D00)
 	{
 		KEEP(*(.ofs1))
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
index 0853763c8..e3f1483fa 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
@@ -30,17 +30,17 @@
 
 #define IRQ_PRIORITY_CMT0     5
 #define IRQ_PRIORITY_USBI0    6
-#define IRQ_PRIORITY_SCI0     5
+#define IRQ_PRIORITY_SCI5     5
 
 #define SYSTEM_PRCR_PRC1      (1<<1)
 #define SYSTEM_PRCR_PRKEY     (0xA5u<<8)
 
-#define CMT_PCLK              48000000
+#define CMT_PCLK              60000000
 #define CMT_CMCR_CKS_DIV_128  2
 #define CMT_CMCR_CMIE         (1<<6)
 #define MPC_PFS_ISEL          (1<<6)
 
-#define SCI_PCLK              48000000
+#define SCI_PCLK              60000000
 #define SCI_SSR_FER           (1<<4)
 #define SCI_SSR_ORER          (1<<5)
 
@@ -49,83 +49,103 @@
 #define SCI_SCR_TE            (1u<<5)
 #define SCI_SCR_RIE           (1u<<6)
 #define SCI_SCR_TIE           (1u<<7)
+#define INT_Excep_SCI5_TEI5   INT_Excep_ICU_GROUPBL0
+
+#define IRQ_USB0_USBI0        62
+#define IEN_USB0_USBI0        IEN_PERIB_INTB185
+#define VECT_USB0_USBI0       VECT_PERIB_INTB185
+#define IR_USB0_USBI0         IR_PERIB_INTB185
+#define IER_USB0_USBI0        IER_PERIB_INTB185
+#define IPR_USB0_USBI0        IPR_PERIB_INTB185
+#define INT_Excep_USB0_USBI0  INT_Excep_PERIB_INTB185
 
 void HardwareSetup(void)
 {
-/*
- BSC.CS0MOD.WORD = 0x1234;
- BSC.CS7CNT.WORD = 0x5678;
+  FLASH.ROMCIV.WORD = 1;
+  while (FLASH.ROMCIV.WORD) ;
+  FLASH.ROMCE.WORD = 1;
+  while (!FLASH.ROMCE.WORD) ;
 
- SCI0.SCR.BIT.TE  = 0;
- SCI0.SCR.BIT.RE  = 0;
- SCI0.SCR.BIT.TE  = 1;
- SCI2.SSR.BIT.PER = 0;
+  SYSTEM.PRCR.WORD = 0xA503u;
+  if (!SYSTEM.RSTSR1.BYTE) {
+    RTC.RCR4.BYTE = 0;
+    RTC.RCR3.BYTE = 12;
+    while (12 != RTC.RCR3.BYTE) ;
+  }
+  SYSTEM.SOSCCR.BYTE = 1;
 
- TMR0.TCR.BYTE = 0x12;
- TMR1.TCR.BYTE = 0x12;
- TMR2.TCR.BYTE = 0x12;
+  if (SYSTEM.HOCOCR.BYTE) {
+    SYSTEM.HOCOCR.BYTE = 0;
+    while (!SYSTEM.OSCOVFSR.BIT.HCOVF) ;
+  }
+  SYSTEM.PLLCR.WORD  = 0x1D10u; /* HOCO x 15 */
+  SYSTEM.PLLCR2.BYTE = 0;
+  while (!SYSTEM.OSCOVFSR.BIT.PLOVF) ;
 
- P0.DDR.BYTE = 0x12;
- P1.DDR.BYTE = 0x12;
-*/
+  SYSTEM.SCKCR.LONG  = 0x21C11222u;
+  SYSTEM.SCKCR2.WORD = 0x0041u;
+  SYSTEM.ROMWT.BYTE  = 0x02u;
+  while (0x02u != SYSTEM.ROMWT.BYTE) ;
+  SYSTEM.SCKCR3.WORD = 0x400u;
+  SYSTEM.PRCR.WORD   = 0xA500u;
 }
 
 //--------------------------------------------------------------------+
-// SCI0 handling
+// SCI handling
 //--------------------------------------------------------------------+
 typedef struct {
   uint8_t *buf;
   uint32_t cnt;
 } sci_buf_t;
-static volatile sci_buf_t sci0_buf[2];
+static volatile sci_buf_t sci_buf[2];
 
-void INT_Excep_SCI0_TXI0(void)
+void INT_Excep_SCI5_TXI5(void)
 {
-  uint8_t *buf = sci0_buf[0].buf;
-  uint32_t cnt = sci0_buf[0].cnt;
+  uint8_t *buf = sci_buf[0].buf;
+  uint32_t cnt = sci_buf[0].cnt;
   
   if (!buf || !cnt) {
-    SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
+    SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
     return;
   }
-  SCI0.TDR = *buf;
+  SCI5.TDR = *buf;
   if (--cnt) {
     ++buf;
   } else {
     buf = NULL;
-    SCI0.SCR.BIT.TIE  = 0;
-    SCI0.SCR.BIT.TEIE = 1;
+    SCI5.SCR.BIT.TIE  = 0;
+    SCI5.SCR.BIT.TEIE = 1;
   }
-  sci0_buf[0].buf = buf;
-  sci0_buf[0].cnt = cnt;
+  sci_buf[0].buf = buf;
+  sci_buf[0].cnt = cnt;
 }
 
-void INT_Excep_SCI0_TEI0(void)
+void INT_Excep_SCI5_TEI5(void)
 {
-  SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
+  SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
 }
 
-void INT_Excep_SCI0_RXI0(void)
+void INT_Excep_SCI5_RXI5(void)
 {
-  uint8_t *buf = sci0_buf[1].buf;
-  uint32_t cnt = sci0_buf[1].cnt;
+  uint8_t *buf = sci_buf[1].buf;
+  uint32_t cnt = sci_buf[1].cnt;
 
   if (!buf || !cnt ||
-      (SCI0.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
-    sci0_buf[1].buf = NULL;
-    SCI0.SSR.BYTE   = 0;
-    SCI0.SCR.BYTE  &= ~(SCI_SCR_RE | SCI_SCR_RIE);
+      (SCI5.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
+    sci_buf[1].buf = NULL;
+    SCI5.SSR.BYTE   = 0;
+    SCI5.SCR.BYTE  &= ~(SCI_SCR_RE | SCI_SCR_RIE);
     return;
   }
-  *buf = SCI0.RDR;
+  *buf = SCI5.RDR;
   if (--cnt) {
     ++buf;
   } else {
     buf = NULL;
-    SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
+    SCI5.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
   }
-  sci0_buf[1].buf = buf;
-  sci0_buf[1].cnt = cnt;
+  sci_buf[1].buf = buf;
+  sci_buf[1].cnt = cnt;
 }
 
 //--------------------------------------------------------------------+
@@ -156,43 +176,47 @@ void board_init(void)
   /* Unlock MPC registers */
   MPC.PWPR.BIT.B0WI  = 0;
   MPC.PWPR.BIT.PFSWE = 1;
-  /* LED PA0 */
-  PORTA.PMR.BIT.B0  = 0U;
-  PORTA.PODR.BIT.B0 = 0U;
-  PORTA.PDR.BIT.B0  = 1U;
-  /* UART TXD0 => P20, RXD0 => P21 */
-  PORT2.PMR.BIT.B0 = 1U;
-  PORT2.PCR.BIT.B0 = 1U;
-  MPC.P20PFS.BYTE  = 0b01010;
-  PORT2.PMR.BIT.B1 = 1U;
-  MPC.P21PFS.BYTE  = 0b01010;
-  /* USB VBUS -> P16 DPUPE -> P14 */
-  PORT1.PMR.BIT.B4 = 1U;
+  // SW PB1
+  PORTB.PMR.BIT.B1 = 0U;
+  PORTB.PDR.BIT.B1 = 0U;
+  // LED PD6
+  PORTD.PODR.BIT.B6 = 1U;
+  PORTD.ODR1.BIT.B4 = 1U;
+  PORTD.PMR.BIT.B6  = 0U;
+  PORTD.PDR.BIT.B6  = 1U;
+  /* UART TXD5 => PA4, RXD5 => PA3 */
+  PORTA.PMR.BIT.B4 = 1U;
+  PORTA.PCR.BIT.B4 = 1U;
+  MPC.PA4PFS.BYTE  = 0b01010;
+  PORTA.PMR.BIT.B3 = 1U;
+  MPC.PA5PFS.BYTE  = 0b01010;
+  /* USB VBUS -> P16 */
   PORT1.PMR.BIT.B6 = 1U;
-  MPC.P14PFS.BYTE  = 0b10001;
   MPC.P16PFS.BYTE  = MPC_PFS_ISEL | 0b10001;
-//  MPC.PFUSB0.BIT.PUPHZS = 1;
   /* Lock MPC registers */
   MPC.PWPR.BIT.PFSWE = 0;
   MPC.PWPR.BIT.B0WI  = 1;
 
-//  IR(USB0, USBI0)  = 0;
-//  IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
-
-  /* Enable SCI0 */
+  /* Enable SCI5 */
   SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(SCI0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  SCI0.BRR = (SCI_PCLK / (32 * 115200)) - 1;
-//  IR(SCI0,  RXI0)  = 0;
-//  IR(SCI0,  TXI0)  = 0;
-//  IR(SCI0,  TEI0)  = 0;
-//  IPR(SCI0, RXI0) = IRQ_PRIORITY_SCI0;
-//  IPR(SCI0, TXI0) = IRQ_PRIORITY_SCI0;
-//  IPR(SCI0, TEI0) = IRQ_PRIORITY_SCI0;
-//  IEN(SCI0, RXI0) = 1;
-//  IEN(SCI0, TXI0) = 1;
-//  IEN(SCI0, TEI0) = 1;
+  MSTP(SCI5) = 0;
+  SYSTEM.PRCR.WORD  = SYSTEM_PRCR_PRKEY;
+  SCI5.BRR = ((SCI_PCLK * 1.0) / (32.0 * 115200.0)) - 1;
+  IR(SCI5,  RXI5)   = 0;
+  IR(SCI5,  TXI5)   = 0;
+  IS(SCI5,  TEI5)   = 0;
+  IR(ICU, GROUPBL0) = 0;
+  IPR(SCI5, RXI5)   = IRQ_PRIORITY_SCI5;
+  IPR(SCI5, TXI5)   = IRQ_PRIORITY_SCI5;
+  IPR(ICU,GROUPBL0) = IRQ_PRIORITY_SCI5;
+  IEN(SCI5, RXI5)   = 1;
+  IEN(SCI5, TXI5)   = 1;
+  IEN(ICU,GROUPBL0) = 1;
+  EN(SCI5, TEI5)    = 1;
+
+  /* setup USBI0 interrupt. Group B edge */
+  IR(USB0, USBI0)  = 0;
+  IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
 }
 
 //--------------------------------------------------------------------+
@@ -201,29 +225,29 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  PORTA.PODR.BIT.B0 = state ? 1 : 0;
+  PORTD.PODR.BIT.B6 = state ? 0 : 1;
 }
 
 uint32_t board_button_read(void)
 {
-  return 0;
+  return PORTB.PIDR.BIT.B1 ? 0 : 1;
 }
 
 int board_uart_read(uint8_t* buf, int len)
 {
-  sci0_buf[1].buf = buf;
-  sci0_buf[1].cnt = len;
-  SCI0.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
-  while (SCI0.SCR.BIT.RE) ;
-  return len - sci0_buf[1].cnt;
+  sci_buf[1].buf = buf;
+  sci_buf[1].cnt = len;
+  SCI5.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
+  while (SCI5.SCR.BIT.RE) ;
+  return len - sci_buf[1].cnt;
 }
 
 int board_uart_write(void const *buf, int len)
 {
-  sci0_buf[0].buf = (uint8_t*)buf;
-  sci0_buf[0].cnt = len;
-  SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
-  while (SCI0.SCR.BIT.TE) ;
+  sci_buf[0].buf = (uint8_t*)buf;
+  sci_buf[0].cnt = len;
+  SCI5.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
+  while (SCI5.SCR.BIT.TE) ;
   return len;
 }
 
@@ -239,5 +263,5 @@ uint32_t board_millis(void)
   return system_ticks;
 }
 #else
-uint32_t SystemCoreClock = 96000000;
+uint32_t SystemCoreClock = 120000000;
 #endif

From 51c6444e1d8be85d5f4c8b4ebf7e48db7f589bc2 Mon Sep 17 00:00:00 2001
From: Wini-Buh <info@winformatik.ch>
Date: Tue, 22 Jun 2021 23:49:24 +0200
Subject: [PATCH 0099/2085] final clean up

---
 src/common/tusb_compiler.h           | 10 ----------
 src/device/usbd.c                    |  4 ++--
 src/device/usbd_control.c            | 10 +---------
 src/osal/osal_freertos.h             | 25 -------------------------
 src/portable/renesas/usba/dcd_usba.c | 11 +----------
 5 files changed, 4 insertions(+), 56 deletions(-)

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index f77cf94ee..538daa171 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -84,8 +84,6 @@
   // Endian conversion use well-known host to network (big endian) naming
   #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
     #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
-    #define TU_ENDIAN_LITTLE_BEGIN
-    #define TU_ENDIAN_LITTLE_END
   #else
     #define TU_BYTE_ORDER TU_BIG_ENDIAN
   #endif
@@ -153,21 +151,13 @@
   // Endian conversion use well-known host to network (big endian) naming
   #if defined(__LIT)
     #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
-    #define TU_ENDIAN_LITTLE_BEGIN
-    #define TU_ENDIAN_LITTLE_END
   #else
     #define TU_BYTE_ORDER TU_BIG_ENDIAN
-    #define TU_ENDIAN_LITTLE_BEGIN _Pragma("endian little")
-    #define TU_ENDIAN_LITTLE_END _Pragma("endian")
   #endif
 
   #define TU_BSWAP16(u16) ((unsigned short)_builtin_revw((unsigned long)u16))
   #define TU_BSWAP32(u32) (_builtin_revl(u32))
 
-  /* activate the "aligned" emulation, because this toolchain does not know
-     the aligned attribute (or something similar yet) */
-  #define TU_HAS_NO_ATTR_ALIGNED
-
 #else 
   #error "Compiler attribute porting is required"
 #endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index cedca540e..00ec29c9a 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1156,14 +1156,14 @@ void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr)
 
 bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
 {
-  TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, desc_ep->wMaxPacketSize.size);
+  TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, tu_le16toh(desc_ep->wMaxPacketSize.size));
 
   switch (desc_ep->bmAttributes.xfer)
   {
     case TUSB_XFER_ISOCHRONOUS:
     {
       uint16_t const max_epsize = (_usbd_dev.speed == TUSB_SPEED_HIGH ? 1024 : 1023);
-      TU_ASSERT(desc_ep->wMaxPacketSize.size <= max_epsize);
+      TU_ASSERT(tu_le16toh(desc_ep->wMaxPacketSize.size) <= max_epsize);
     }
     break;
 
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index b3bab2e32..5483406e5 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -55,17 +55,9 @@ typedef struct
 
 static usbd_control_xfer_t _ctrl_xfer;
 
-#if defined(TU_HAS_NO_ATTR_ALIGNED)
-// Helper union to overcome the lack of the alignment attribute/pragma
-static union {
-  uint16_t : (sizeof(uint16_t) * 8);  // Alignment of at least the size of the used type
-  uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
-} Align_usbd_ctrl_buf_;
-static uint8_t *_usbd_ctrl_buf = (uint8_t*)&Align_usbd_ctrl_buf_;
-#else
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
 static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
-#endif
+
 
 //--------------------------------------------------------------------+
 // Application API
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index ec33b317d..66070c273 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -51,7 +51,6 @@ static inline void osal_task_delay(uint32_t msec)
 typedef StaticSemaphore_t osal_semaphore_def_t;
 typedef SemaphoreHandle_t osal_semaphore_t;
 
-#if (configSUPPORT_STATIC_ALLOCATION == 1)  //FIXME Only static API supported
 static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
 {
   return xSemaphoreCreateBinaryStatic(semdef);
@@ -77,7 +76,6 @@ static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
     return res != 0;
   }
 }
-#endif
 
 static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
 {
@@ -98,12 +96,7 @@ typedef SemaphoreHandle_t osal_mutex_t;
 
 static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
-#if (configSUPPORT_STATIC_ALLOCATION == 0) //FIXME Only static API supported
-  (void)mdef;
-  return xSemaphoreCreateMutex();
-#else
   return xSemaphoreCreateMutexStatic(mdef);
-#endif
 }
 
 static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
@@ -138,11 +131,7 @@ typedef QueueHandle_t osal_queue_t;
 
 static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
-#if defined(__Tx36V5_Maincard__)
-  return xQueueCreate(qdef->depth, qdef->item_sz);
-#else
   return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
-#endif
 }
 
 static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
@@ -150,19 +139,6 @@ static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
   return xQueueReceive(qhdl, data, portMAX_DELAY);
 }
 
-#if defined(__Tx36V5_Maincard__)
-extern BaseType_t UsbTaskWoken;
-static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
-  if (!in_isr) {
-    return(xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER));
-
-  } else {
-    BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &UsbTaskWoken);
-    return(res != 0);
-  }
-}
-#else
 static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
 {
   if ( !in_isr )
@@ -183,7 +159,6 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
     return res != 0;
   }
 }
-#endif
 
 static inline bool osal_queue_empty(osal_queue_t qhdl)
 {
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 13fc50ae5..51729de06 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -518,22 +518,13 @@ static void process_set_address(uint8_t rhport)
 {
   const uint32_t addr = USB0.USBADDR.BIT.USBADDR;
   if (!addr) return;
-#if defined(__CCRX__)
-  tusb_control_request_t setup_packet;
-  setup_packet.bmRequestType = 0;
-  setup_packet.bRequest = 5;
-  setup_packet.wValue = addr;
-  setup_packet.wIndex = 0;
-  setup_packet.wLength = 0;
-#else
   const tusb_control_request_t setup_packet = {
-      .bmRequestType = 0,
+      .bmRequestType = { 0 },  /* Note: CCRX needs the braces over this struct member */
       .bRequest      = 5,
       .wValue        = addr,
       .wIndex        = 0,
       .wLength       = 0,
     };
-#endif
   dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true);
 }
 

From f5f087b2f85ebf4ff41c84c5f1a70a598d32cb21 Mon Sep 17 00:00:00 2001
From: Jeremiah McCarthy <jeremiahmccarthy@xmos.com>
Date: Wed, 23 Jun 2021 10:58:18 -0400
Subject: [PATCH 0100/2085] Add dfu function memory access protection

Adds TU_VERIFY to dfu internal buffer access from host.

Adds TU_ASSERT to dfu internal buffer access by application.
---
 src/class/dfu/dfu_device.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 81045ff7b..df731ee50 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -249,6 +249,7 @@ static uint16_t dfu_req_upload(uint8_t rhport, tusb_control_request_t const * re
 {
   TU_VERIFY( wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
   uint16_t retval = tud_dfu_req_upload_data_cb(block_num, (uint8_t *)_dfu_state_ctx.transfer_buf, wLength);
+  TU_ASSERT( retval <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
   tud_control_xfer(rhport, request, _dfu_state_ctx.transfer_buf, retval);
   return retval;
 }
@@ -276,6 +277,7 @@ static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const *
   // if they wish, there still will be the internal control buffer copy to this buffer
   // but this mode would provide zero copy from the class driver to the application
 
+  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
   // setup for data phase
   tud_control_xfer(rhport, request, _dfu_state_ctx.transfer_buf, request->wLength);
 }
@@ -283,6 +285,7 @@ static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const *
 static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request)
 {
   (void) rhport;
+  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
   tud_dfu_req_dnload_data_cb(request->wValue, (uint8_t *)_dfu_state_ctx.transfer_buf, request->wLength);
   _dfu_state_ctx.blk_transfer_in_proc = false;
 }

From 9d6fd78b632db5b40e84e4c019f00286aae5d1ad Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 24 Jun 2021 11:34:29 +0200
Subject: [PATCH 0101/2085] Add fifo helper function to CDC class for DMA
 transfer.

---
 src/class/cdc/cdc_device.c | 14 ++++++++++++++
 src/class/cdc/cdc_device.h | 18 ++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index cac811c45..a926081cc 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -483,4 +483,18 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   return true;
 }
 
+// Get the Receive FIFO (for DMA transfer)
+tu_fifo_t* tud_cdc_n_get_rx_ff (uint8_t itf)
+{
+  TU_ASSERT(itf < CFG_TUD_CDC);
+  return &_cdcd_itf[itf].rx_ff;
+}
+
+// Get the transmit FIFO (for DMA transfer)
+tu_fifo_t* tud_cdc_n_get_tx_ff (uint8_t itf)
+{
+  TU_ASSERT(itf < CFG_TUD_CDC);
+  return &_cdcd_itf[itf].tx_ff;
+}
+
 #endif
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index 7ff757add..94678a660 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -104,6 +104,12 @@ uint32_t tud_cdc_n_write_available (uint8_t itf);
 // Clear the transmit FIFO
 bool tud_cdc_n_write_clear (uint8_t itf);
 
+// Get the Receive FIFO (for DMA transfer)
+tu_fifo_t* tud_cdc_n_get_rx_ff (uint8_t itf);
+
+// Get the transmit FIFO (for DMA transfer)
+tu_fifo_t* tud_cdc_n_get_tx_ff (uint8_t itf);
+
 //--------------------------------------------------------------------+
 // Application API (Single Port)
 //--------------------------------------------------------------------+
@@ -241,6 +247,18 @@ static inline bool tud_cdc_write_clear(void)
   return tud_cdc_n_write_clear(0);
 }
 
+// Get the Receive FIFO
+static inline tu_fifo_t* tud_cdc_get_rx_ff (uint8_t itf)
+{
+  return tud_cdc_n_get_rx_ff(0);
+}
+
+// Get the transmit FIFO
+static inline tu_fifo_t* tud_cdc_get_tx_ff (uint8_t itf)
+{
+  return tud_cdc_n_get_tx_ff(0);
+}
+
 /** @} */
 /** @} */
 

From b9e9773d04419032d9e8eb8ca568390f74382690 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 24 Jun 2021 11:35:05 +0200
Subject: [PATCH 0102/2085] fix warning

---
 src/class/cdc/cdc_device.h | 4 ++--
 src/device/usbd.h          | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index 94678a660..f8a2216c1 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -248,13 +248,13 @@ static inline bool tud_cdc_write_clear(void)
 }
 
 // Get the Receive FIFO
-static inline tu_fifo_t* tud_cdc_get_rx_ff (uint8_t itf)
+static inline tu_fifo_t* tud_cdc_get_rx_ff (void)
 {
   return tud_cdc_n_get_rx_ff(0);
 }
 
 // Get the transmit FIFO
-static inline tu_fifo_t* tud_cdc_get_tx_ff (uint8_t itf)
+static inline tu_fifo_t* tud_cdc_get_tx_ff (void)
 {
   return tud_cdc_n_get_tx_ff(0);
 }
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 3857295d7..0a0f0bf00 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -236,7 +236,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 // Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval
 #define TUD_HID_DESCRIPTOR(_itfnum, _stridx, _boot_protocol, _report_desc_len, _epin, _epsize, _ep_interval) \
   /* Interface */\
-  9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_HID, (uint8_t)((_boot_protocol) ? HID_SUBCLASS_BOOT : 0), _boot_protocol, _stridx,\
+  9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_HID, (uint8_t)((_boot_protocol) ? (uint8_t)HID_SUBCLASS_BOOT : 0), _boot_protocol, _stridx,\
   /* HID descriptor */\
   9, HID_DESC_TYPE_HID, U16_TO_U8S_LE(0x0111), 0, 1, HID_DESC_TYPE_REPORT, U16_TO_U8S_LE(_report_desc_len),\
   /* Endpoint In */\
@@ -249,7 +249,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 // Interface number, string index, protocol, report descriptor len, EP OUT & IN address, size & polling interval
 #define TUD_HID_INOUT_DESCRIPTOR(_itfnum, _stridx, _boot_protocol, _report_desc_len, _epout, _epin, _epsize, _ep_interval) \
   /* Interface */\
-  9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_HID, (uint8_t)((_boot_protocol) ? HID_SUBCLASS_BOOT : 0), _boot_protocol, _stridx,\
+  9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_HID, (uint8_t)((_boot_protocol) ? (uint8_t)HID_SUBCLASS_BOOT : 0), _boot_protocol, _stridx,\
   /* HID descriptor */\
   9, HID_DESC_TYPE_HID, U16_TO_U8S_LE(0x0111), 0, 1, HID_DESC_TYPE_REPORT, U16_TO_U8S_LE(_report_desc_len),\
   /* Endpoint Out */\

From 60fedaa050b68201f03682bec3a5b16f4abc739e Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 26 Jun 2021 21:13:35 +0900
Subject: [PATCH 0103/2085] fix baudrate setting

---
 .../boards/rx65n_cloud_kit/rx65n_cloud_kit.c  | 32 ++++++++++---------
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
index e3f1483fa..7ebcfead6 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
@@ -198,21 +198,23 @@ void board_init(void)
   MPC.PWPR.BIT.B0WI  = 1;
 
   /* Enable SCI5 */
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(SCI5) = 0;
-  SYSTEM.PRCR.WORD  = SYSTEM_PRCR_PRKEY;
-  SCI5.BRR = ((SCI_PCLK * 1.0) / (32.0 * 115200.0)) - 1;
-  IR(SCI5,  RXI5)   = 0;
-  IR(SCI5,  TXI5)   = 0;
-  IS(SCI5,  TEI5)   = 0;
-  IR(ICU, GROUPBL0) = 0;
-  IPR(SCI5, RXI5)   = IRQ_PRIORITY_SCI5;
-  IPR(SCI5, TXI5)   = IRQ_PRIORITY_SCI5;
-  IPR(ICU,GROUPBL0) = IRQ_PRIORITY_SCI5;
-  IEN(SCI5, RXI5)   = 1;
-  IEN(SCI5, TXI5)   = 1;
-  IEN(ICU,GROUPBL0) = 1;
-  EN(SCI5, TEI5)    = 1;
+  SYSTEM.PRCR.WORD   = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(SCI5)         = 0;
+  SYSTEM.PRCR.WORD   = SYSTEM_PRCR_PRKEY;
+  SCI5.SEMR.BIT.ABCS = 1;
+  SCI5.SEMR.BIT.BGDM = 1;
+  SCI5.BRR           = (SCI_PCLK / (8 * 115200)) - 1;
+  IR(SCI5,  RXI5)    = 0;
+  IR(SCI5,  TXI5)    = 0;
+  IS(SCI5,  TEI5)    = 0;
+  IR(ICU, GROUPBL0)  = 0;
+  IPR(SCI5, RXI5)    = IRQ_PRIORITY_SCI5;
+  IPR(SCI5, TXI5)    = IRQ_PRIORITY_SCI5;
+  IPR(ICU,GROUPBL0)  = IRQ_PRIORITY_SCI5;
+  IEN(SCI5, RXI5)    = 1;
+  IEN(SCI5, TXI5)    = 1;
+  IEN(ICU,GROUPBL0)  = 1;
+  EN(SCI5, TEI5)     = 1;
 
   /* setup USBI0 interrupt. Group B edge */
   IR(USB0, USBI0)  = 0;

From 511b2d47d1be37bfa1d6f35ddee80393ec93d39c Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 26 Jun 2021 22:42:27 +0900
Subject: [PATCH 0104/2085] add handling for software configurable interrupts.

---
 hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk          |  5 ++++-
 hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c | 11 ++++++-----
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
index 87cbd74a8..a4f19b07b 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
@@ -1,7 +1,10 @@
 CFLAGS += \
   -mcpu=rx64m \
   -misa=v2 \
-  -DCFG_TUSB_MCU=OPT_MCU_RX65X
+  -DCFG_TUSB_MCU=OPT_MCU_RX65X \
+  -DIR_USB0_USBI0=IR_PERIB_INTB185 \
+  -DIER_USB0_USBI0=IER_PERIB_INTB185 \
+  -DIEN_USB0_USBI0=IEN_PERIB_INTB185
 
 RX_NEWLIB ?= 1
 
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
index 7ebcfead6..895b82e23 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
@@ -52,10 +52,7 @@
 #define INT_Excep_SCI5_TEI5   INT_Excep_ICU_GROUPBL0
 
 #define IRQ_USB0_USBI0        62
-#define IEN_USB0_USBI0        IEN_PERIB_INTB185
-#define VECT_USB0_USBI0       VECT_PERIB_INTB185
-#define IR_USB0_USBI0         IR_PERIB_INTB185
-#define IER_USB0_USBI0        IER_PERIB_INTB185
+#define SLIBR_USBI0           SLIBR185
 #define IPR_USB0_USBI0        IPR_PERIB_INTB185
 #define INT_Excep_USB0_USBI0  INT_Excep_PERIB_INTB185
 
@@ -158,6 +155,10 @@ void INT_Excep_USB0_USBI0(void)
 
 void board_init(void)
 {
+  /* setup software configurable interrupts */
+  ICU.SLIBR_USBI0.BYTE = IRQ_USB0_USBI0;
+  ICU.SLIPRCR.BYTE     = 1;
+
 #if CFG_TUSB_OS == OPT_OS_NONE
   /* Enable CMT0 */
   SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
@@ -216,7 +217,7 @@ void board_init(void)
   IEN(ICU,GROUPBL0)  = 1;
   EN(SCI5, TEI5)     = 1;
 
-  /* setup USBI0 interrupt. Group B edge */
+  /* setup USBI0 interrupt. */
   IR(USB0, USBI0)  = 0;
   IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
 }

From 393a9120ac0725ba525aa09fcf8e24fd32735391 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 26 Jun 2021 23:09:18 +0900
Subject: [PATCH 0105/2085] add the entry for RX65N

---
 src/portable/renesas/usba/dcd_usba.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 06ea1a3f9..de3e0e312 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -26,8 +26,8 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X )
-
+#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
+                                 CFG_TUSB_MCU == OPT_MCU_RX65X)
 #include "device/dcd.h"
 #include "iodefine.h"
 

From b5ce269675c4d220806126cc76f8c57406da27d2 Mon Sep 17 00:00:00 2001
From: DuMaM <batek.nowak@yahoo.pl>
Date: Sat, 26 Jun 2021 17:03:46 +0200
Subject: [PATCH 0106/2085] GCC 11 build fix

During Adafruit Bootloader compilation, I spotted bellow error which do not allow me build project.

``` c
    inlined from 'hfclk_running' at lib/tinyusb/src/portable/nordic/nrf5x/dcd_nrf5x.c:785:13:
lib/tinyusb/src/portable/nordic/nrf5x/dcd_nrf5x.c:792:31: error: 'is_running' may be used uninitialized [-Werror=maybe-uninitialized]
  792 |     return (is_running ? true : false);
      |            ~~~~~~~~~~~~~~~~~~~^~~~~~~~
```
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index b3b2dec2d..5f4fe08ad 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -787,7 +787,7 @@ static bool hfclk_running(void)
 #ifdef SOFTDEVICE_PRESENT
   if ( is_sd_enabled() )
   {
-    uint32_t is_running;
+    uint32_t is_running = 0;
     (void) sd_clock_hfclk_is_running(&is_running);
     return (is_running ? true : false);
   }

From 239ecadeca9312af8c0777b9e41fbd25187f45be Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 27 Jun 2021 23:39:50 +0900
Subject: [PATCH 0107/2085] add options for e2l

---
 hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
index a4f19b07b..34a4b2cbb 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
@@ -52,4 +52,4 @@ PYOCD_TARGET =
 
 # flash using rfp-cli
 flash: $(BUILD)/$(PROJECT).mot
-	rfp-cli -device rx65x -tool e2l -auto $^
+	rfp-cli -device rx65x -tool e2l -if fine -fo id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auth id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auto $^

From ec9bfe03336f4053f438ab83a50436808813c256 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 12:27:20 +0700
Subject: [PATCH 0108/2085] update renesas rx submodule

---
 hw/mcu/renesas/rx | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/renesas/rx b/hw/mcu/renesas/rx
index 4a51dfe6e..706b4e0cf 160000
--- a/hw/mcu/renesas/rx
+++ b/hw/mcu/renesas/rx
@@ -1 +1 @@
-Subproject commit 4a51dfe6ecdf936d2d89f223f069e24a2d109207
+Subproject commit 706b4e0cf485605c32351e2f90f5698267996023

From 17137bbfff9fcaf551a652a0ce0cfef8db69ac42 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 12:35:12 +0700
Subject: [PATCH 0109/2085] fix rx65n with freertos build

---
 examples/device/cdc_msc_freertos/src/freertos_hook.c       | 2 +-
 examples/device/hid_composite_freertos/src/freertos_hook.c | 2 +-
 hw/bsp/board_mcu.h                                         | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/freertos_hook.c b/examples/device/cdc_msc_freertos/src/freertos_hook.c
index 273ad46e6..ab885947c 100644
--- a/examples/device/cdc_msc_freertos/src/freertos_hook.c
+++ b/examples/device/cdc_msc_freertos/src/freertos_hook.c
@@ -94,7 +94,7 @@ void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, Stack
   *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
 }
 
-#if CFG_TUSB_MCU == OPT_MCU_RX63X
+#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X
 #include "iodefine.h"
 void vApplicationSetupTimerInterrupt(void)
 {
diff --git a/examples/device/hid_composite_freertos/src/freertos_hook.c b/examples/device/hid_composite_freertos/src/freertos_hook.c
index 273ad46e6..ab885947c 100644
--- a/examples/device/hid_composite_freertos/src/freertos_hook.c
+++ b/examples/device/hid_composite_freertos/src/freertos_hook.c
@@ -94,7 +94,7 @@ void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, Stack
   *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
 }
 
-#if CFG_TUSB_MCU == OPT_MCU_RX63X
+#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X
 #include "iodefine.h"
 void vApplicationSetupTimerInterrupt(void)
 {
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 1a659c410..3628371cd 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -127,7 +127,7 @@
 #elif CFG_TUSB_MCU == OPT_MCU_EFM32GG || CFG_TUSB_MCU == OPT_MCU_EFM32GG11 || CFG_TUSB_MCU == OPT_MCU_EFM32GG12
   #include "em_device.h"
 
-#elif CFG_TUSB_MCU == OPT_MCU_RX63X
+#elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
   // no header needed
 
 #else

From 8c4641fc0587d107b974d8e659d0159fac57665d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 12:49:30 +0700
Subject: [PATCH 0110/2085] refactor rx6x bsp

---
 hw/bsp/rx63n/boards/gr_citrus/board.mk       | 29 --------------------
 hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk | 29 --------------------
 hw/bsp/rx63n/family.mk                       | 29 ++++++++++++++++++++
 3 files changed, 29 insertions(+), 58 deletions(-)

diff --git a/hw/bsp/rx63n/boards/gr_citrus/board.mk b/hw/bsp/rx63n/boards/gr_citrus/board.mk
index 6edd588bc..0eba94610 100644
--- a/hw/bsp/rx63n/boards/gr_citrus/board.mk
+++ b/hw/bsp/rx63n/boards/gr_citrus/board.mk
@@ -5,40 +5,11 @@ CFLAGS += \
   -misa=v1 \
   -DCFG_TUSB_MCU=OPT_MCU_RX63X
 
-RX_NEWLIB ?= 1
-
-ifeq ($(CMDEXE),1)
-OPTLIBINC="$(shell for /F "usebackq delims=" %%i in (`where rx-elf-gcc`) do echo %%~dpi..\rx-elf\optlibinc)"
-else
-OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
-endif
-
-ifeq ($(RX_NEWLIB),1)
-CFLAGS += -DSSIZE_MAX=__INT_MAX__
-else
-# setup for optlib
-CFLAGS += -nostdinc \
-  -isystem $(OPTLIBINC) \
-  -DLWIP_NO_INTTYPES_H
-
-LIBS += -loptc -loptm
-endif
-
 MCU_DIR = hw/mcu/renesas/rx/rx63n
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/r5f5631fd.ld
 
-SRC_C += \
-	src/portable/renesas/usba/dcd_usba.c \
-	$(MCU_DIR)/vects.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)
-
-SRC_S += $(MCU_DIR)/start.S
-
 # For freeRTOS port source
 FREERTOS_PORT = RX600
 
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
index 34a4b2cbb..e0d970435 100644
--- a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
+++ b/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
@@ -6,40 +6,11 @@ CFLAGS += \
   -DIER_USB0_USBI0=IER_PERIB_INTB185 \
   -DIEN_USB0_USBI0=IEN_PERIB_INTB185
 
-RX_NEWLIB ?= 1
-
-ifeq ($(CMDEXE),1)
-OPTLIBINC="$(shell for /F "usebackq delims=" %%i in (`where rx-elf-gcc`) do echo %%~dpi..\rx-elf\optlibinc)"
-else
-OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
-endif
-
-ifeq ($(RX_NEWLIB),1)
-CFLAGS += -DSSIZE_MAX=__INT_MAX__
-else
-# setup for optlib
-CFLAGS += -nostdinc \
-  -isystem $(OPTLIBINC) \
-  -DLWIP_NO_INTTYPES_H
-
-LIBS += -loptc -loptm
-endif
-
 MCU_DIR = hw/mcu/renesas/rx/rx65n
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/r5f565ne.ld
 
-SRC_C += \
-	src/portable/renesas/usba/dcd_usba.c \
-	$(MCU_DIR)/vects.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)
-
-SRC_S += $(MCU_DIR)/start.S
-
 # For freeRTOS port source
 FREERTOS_PORT = RX600
 
diff --git a/hw/bsp/rx63n/family.mk b/hw/bsp/rx63n/family.mk
index a9c74e6b0..057fc8c25 100644
--- a/hw/bsp/rx63n/family.mk
+++ b/hw/bsp/rx63n/family.mk
@@ -12,6 +12,35 @@ CFLAGS += \
   -fshort-enums \
   -mlittle-endian-data \
 
+RX_NEWLIB ?= 1
+
+ifeq ($(CMDEXE),1)
+  OPTLIBINC="$(shell for /F "usebackq delims=" %%i in (`where rx-elf-gcc`) do echo %%~dpi..\rx-elf\optlibinc)"
+else
+  OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
+endif
+
+ifeq ($(RX_NEWLIB),1)
+  CFLAGS += -DSSIZE_MAX=__INT_MAX__
+else
+  # setup for optlib
+  CFLAGS += -nostdinc \
+    -isystem $(OPTLIBINC) \
+    -DLWIP_NO_INTTYPES_H
+
+  LIBS += -loptc -loptm
+endif
+
+SRC_C += \
+	src/portable/renesas/usba/dcd_usba.c \
+	$(MCU_DIR)/vects.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MCU_DIR)
+
+SRC_S += $(MCU_DIR)/start.S
+
 $(BUILD)/$(PROJECT).mot: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
 	$(OBJCOPY) -O srec -I elf32-rx-be-ns $^ $@

From e3b1110cce73291fb6eefed6537aaee5cc56ee20 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 12:51:11 +0700
Subject: [PATCH 0111/2085] rename rx63n to simply rx

---
 hw/bsp/{rx63n => rx}/boards/gr_citrus/board.mk                | 0
 hw/bsp/{rx63n => rx}/boards/gr_citrus/gr_citrus.c             | 0
 hw/bsp/{rx63n => rx}/boards/gr_citrus/hwinit.c                | 0
 hw/bsp/{rx63n => rx}/boards/gr_citrus/r5f5631fd.ld            | 0
 hw/bsp/{rx63n => rx}/boards/rx65n_cloud_kit/board.mk          | 0
 hw/bsp/{rx63n => rx}/boards/rx65n_cloud_kit/r5f565ne.ld       | 0
 hw/bsp/{rx63n => rx}/boards/rx65n_cloud_kit/rx65n_cloud_kit.c | 0
 hw/bsp/{rx63n => rx}/family.mk                                | 0
 8 files changed, 0 insertions(+), 0 deletions(-)
 rename hw/bsp/{rx63n => rx}/boards/gr_citrus/board.mk (100%)
 rename hw/bsp/{rx63n => rx}/boards/gr_citrus/gr_citrus.c (100%)
 rename hw/bsp/{rx63n => rx}/boards/gr_citrus/hwinit.c (100%)
 rename hw/bsp/{rx63n => rx}/boards/gr_citrus/r5f5631fd.ld (100%)
 rename hw/bsp/{rx63n => rx}/boards/rx65n_cloud_kit/board.mk (100%)
 rename hw/bsp/{rx63n => rx}/boards/rx65n_cloud_kit/r5f565ne.ld (100%)
 rename hw/bsp/{rx63n => rx}/boards/rx65n_cloud_kit/rx65n_cloud_kit.c (100%)
 rename hw/bsp/{rx63n => rx}/family.mk (100%)

diff --git a/hw/bsp/rx63n/boards/gr_citrus/board.mk b/hw/bsp/rx/boards/gr_citrus/board.mk
similarity index 100%
rename from hw/bsp/rx63n/boards/gr_citrus/board.mk
rename to hw/bsp/rx/boards/gr_citrus/board.mk
diff --git a/hw/bsp/rx63n/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
similarity index 100%
rename from hw/bsp/rx63n/boards/gr_citrus/gr_citrus.c
rename to hw/bsp/rx/boards/gr_citrus/gr_citrus.c
diff --git a/hw/bsp/rx63n/boards/gr_citrus/hwinit.c b/hw/bsp/rx/boards/gr_citrus/hwinit.c
similarity index 100%
rename from hw/bsp/rx63n/boards/gr_citrus/hwinit.c
rename to hw/bsp/rx/boards/gr_citrus/hwinit.c
diff --git a/hw/bsp/rx63n/boards/gr_citrus/r5f5631fd.ld b/hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld
similarity index 100%
rename from hw/bsp/rx63n/boards/gr_citrus/r5f5631fd.ld
rename to hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk b/hw/bsp/rx/boards/rx65n_cloud_kit/board.mk
similarity index 100%
rename from hw/bsp/rx63n/boards/rx65n_cloud_kit/board.mk
rename to hw/bsp/rx/boards/rx65n_cloud_kit/board.mk
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld b/hw/bsp/rx/boards/rx65n_cloud_kit/r5f565ne.ld
similarity index 100%
rename from hw/bsp/rx63n/boards/rx65n_cloud_kit/r5f565ne.ld
rename to hw/bsp/rx/boards/rx65n_cloud_kit/r5f565ne.ld
diff --git a/hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c b/hw/bsp/rx/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
similarity index 100%
rename from hw/bsp/rx63n/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
rename to hw/bsp/rx/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
diff --git a/hw/bsp/rx63n/family.mk b/hw/bsp/rx/family.mk
similarity index 100%
rename from hw/bsp/rx63n/family.mk
rename to hw/bsp/rx/family.mk

From 856dc0bab92799320d2909638d6988f3776f258a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 12:53:53 +0700
Subject: [PATCH 0112/2085] update doc and clean up

---
 .github/workflows/build_renesas.yml       | 2 +-
 README.md                                 | 2 +-
 docs/boards.md                            | 1 +
 hw/bsp/rx/boards/rx65n_cloud_kit/board.mk | 3 +--
 hw/bsp/rx/family.mk                       | 4 ++++
 5 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 45e0c5fd5..ee9ba8289 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -15,7 +15,7 @@ jobs:
       matrix:
         family:
         # Alphabetical order
-        - 'rx63n'
+        - 'rx'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v2
diff --git a/README.md b/README.md
index bea6d0d49..9b86e3b27 100644
--- a/README.md
+++ b/README.md
@@ -40,7 +40,7 @@ The stack supports the following MCUs:
   - Kinetis: KL25
   - LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
 - **Raspberry Pi:** RP2040
-- **Renesas:** RX63N
+- **Renesas:** RX63N, RX65N
 - **Silabs:** EFM32GG12
 - **Sony:** CXD56
 - **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
diff --git a/docs/boards.md b/docs/boards.md
index ebba1f841..c790c7967 100644
--- a/docs/boards.md
+++ b/docs/boards.md
@@ -126,6 +126,7 @@ This code base already had supported for a handful of following boards (sorted a
 ### Renesas RX
 
 - [GR-CITRUS](https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-citrus)
+- [Renesas RX65N Cloud Kit](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rx65n-cloud-kit-renesas-rx65n-cloud-kit)
 
 ### Raspberry Pi RP2040
 
diff --git a/hw/bsp/rx/boards/rx65n_cloud_kit/board.mk b/hw/bsp/rx/boards/rx65n_cloud_kit/board.mk
index e0d970435..fc76d79fa 100644
--- a/hw/bsp/rx/boards/rx65n_cloud_kit/board.mk
+++ b/hw/bsp/rx/boards/rx65n_cloud_kit/board.mk
@@ -22,5 +22,4 @@ JLINK_IF     = JTAG
 PYOCD_TARGET =
 
 # flash using rfp-cli
-flash: $(BUILD)/$(PROJECT).mot
-	rfp-cli -device rx65x -tool e2l -if fine -fo id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auth id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auto $^
+flash: flash-rfp
diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk
index 057fc8c25..7d7585b4a 100644
--- a/hw/bsp/rx/family.mk
+++ b/hw/bsp/rx/family.mk
@@ -44,3 +44,7 @@ SRC_S += $(MCU_DIR)/start.S
 $(BUILD)/$(PROJECT).mot: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
 	$(OBJCOPY) -O srec -I elf32-rx-be-ns $^ $@
+
+# flash using rfp-cli
+flash-rfp: $(BUILD)/$(PROJECT).mot
+	rfp-cli -device rx65x -tool e2l -if fine -fo id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auth id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auto $^

From 07e6a0e8702793a6dec555cf8de75692fe334f7a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 13:13:00 +0700
Subject: [PATCH 0113/2085] reduce esp32s2 board to ci

---
 .github/workflows/build_esp.yml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 08bb4f5d2..93d582361 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -16,7 +16,6 @@ jobs:
         board:
         # Alphabetical order
         # ESP32-S2
-        - 'adafruit_metro_esp32s2'
         - 'espressif_saola_1'
         # ESP32-S3
         - 'espressif_addax_1'

From 7e449b710e00d3375541bd8aa1893a4b9c5b61e3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 14:06:13 +0700
Subject: [PATCH 0114/2085] rename bsp saml22 to saml2x

---
 hw/bsp/{saml22 => saml2x}/boards/saml22_feather/board.h         | 0
 hw/bsp/{saml22 => saml2x}/boards/saml22_feather/board.mk        | 0
 .../{saml22 => saml2x}/boards/saml22_feather/saml22_feather.ld  | 0
 hw/bsp/{saml22 => saml2x}/boards/sensorwatch_m0/board.h         | 0
 hw/bsp/{saml22 => saml2x}/boards/sensorwatch_m0/board.mk        | 0
 .../{saml22 => saml2x}/boards/sensorwatch_m0/sensorwatch_m0.ld  | 0
 hw/bsp/{saml22 => saml2x}/family.c                              | 2 +-
 hw/bsp/{saml22 => saml2x}/family.mk                             | 0
 8 files changed, 1 insertion(+), 1 deletion(-)
 rename hw/bsp/{saml22 => saml2x}/boards/saml22_feather/board.h (100%)
 rename hw/bsp/{saml22 => saml2x}/boards/saml22_feather/board.mk (100%)
 rename hw/bsp/{saml22 => saml2x}/boards/saml22_feather/saml22_feather.ld (100%)
 rename hw/bsp/{saml22 => saml2x}/boards/sensorwatch_m0/board.h (100%)
 rename hw/bsp/{saml22 => saml2x}/boards/sensorwatch_m0/board.mk (100%)
 rename hw/bsp/{saml22 => saml2x}/boards/sensorwatch_m0/sensorwatch_m0.ld (100%)
 rename hw/bsp/{saml22 => saml2x}/family.c (99%)
 rename hw/bsp/{saml22 => saml2x}/family.mk (100%)

diff --git a/hw/bsp/saml22/boards/saml22_feather/board.h b/hw/bsp/saml2x/boards/saml22_feather/board.h
similarity index 100%
rename from hw/bsp/saml22/boards/saml22_feather/board.h
rename to hw/bsp/saml2x/boards/saml22_feather/board.h
diff --git a/hw/bsp/saml22/boards/saml22_feather/board.mk b/hw/bsp/saml2x/boards/saml22_feather/board.mk
similarity index 100%
rename from hw/bsp/saml22/boards/saml22_feather/board.mk
rename to hw/bsp/saml2x/boards/saml22_feather/board.mk
diff --git a/hw/bsp/saml22/boards/saml22_feather/saml22_feather.ld b/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
similarity index 100%
rename from hw/bsp/saml22/boards/saml22_feather/saml22_feather.ld
rename to hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
diff --git a/hw/bsp/saml22/boards/sensorwatch_m0/board.h b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
similarity index 100%
rename from hw/bsp/saml22/boards/sensorwatch_m0/board.h
rename to hw/bsp/saml2x/boards/sensorwatch_m0/board.h
diff --git a/hw/bsp/saml22/boards/sensorwatch_m0/board.mk b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
similarity index 100%
rename from hw/bsp/saml22/boards/sensorwatch_m0/board.mk
rename to hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
diff --git a/hw/bsp/saml22/boards/sensorwatch_m0/sensorwatch_m0.ld b/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
similarity index 100%
rename from hw/bsp/saml22/boards/sensorwatch_m0/sensorwatch_m0.ld
rename to hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
diff --git a/hw/bsp/saml22/family.c b/hw/bsp/saml2x/family.c
similarity index 99%
rename from hw/bsp/saml22/family.c
rename to hw/bsp/saml2x/family.c
index fff11cbe5..1a185a59c 100644
--- a/hw/bsp/saml22/family.c
+++ b/hw/bsp/saml2x/family.c
@@ -160,4 +160,4 @@ uint32_t board_millis(void)
 void _init(void)
 {
 
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/saml22/family.mk b/hw/bsp/saml2x/family.mk
similarity index 100%
rename from hw/bsp/saml22/family.mk
rename to hw/bsp/saml2x/family.mk

From 01987ef86c677c50c3dc5e83f3278fcd0edd4e82 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 14:37:41 +0700
Subject: [PATCH 0115/2085] merge saml21 + saml22 = saml2x

---
 .github/workflows/build.yml                   |   3 +-
 README.md                                     |   2 +-
 docs/boards.md                                |   3 +-
 hw/bsp/saml21/family.c                        | 163 ------------------
 hw/bsp/saml21/family.mk                       |  50 ------
 .../boards/atsaml21_xpro/board.h              |   0
 .../boards/atsaml21_xpro/board.mk             |   2 +
 .../boards/atsaml21_xpro/saml21j18b_flash.ld  |   0
 hw/bsp/saml2x/boards/saml22_feather/board.mk  |   2 +
 hw/bsp/saml2x/boards/sensorwatch_m0/board.mk  |   2 +
 hw/bsp/saml2x/family.c                        |  14 +-
 hw/bsp/saml2x/family.mk                       |  40 ++---
 12 files changed, 36 insertions(+), 245 deletions(-)
 delete mode 100644 hw/bsp/saml21/family.c
 delete mode 100644 hw/bsp/saml21/family.mk
 rename hw/bsp/{saml21 => saml2x}/boards/atsaml21_xpro/board.h (100%)
 rename hw/bsp/{saml21 => saml2x}/boards/atsaml21_xpro/board.mk (90%)
 rename hw/bsp/{saml21 => saml2x}/boards/atsaml21_xpro/saml21j18b_flash.ld (100%)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 1e149dc65..fc5b92b68 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -49,8 +49,7 @@ jobs:
         - 'samd11'
         - 'samd21'
         - 'samd51'
-        - 'saml21'
-        - 'saml22'
+        - 'saml2x'
         - 'stm32f0'
         - 'stm32f4'
         - 'stm32f7'
diff --git a/README.md b/README.md
index 9b86e3b27..11c1df3f8 100644
--- a/README.md
+++ b/README.md
@@ -32,7 +32,7 @@ The stack supports the following MCUs:
 
 - **Dialog:** DA1469x
 - **Espressif:** ESP32-S2, ESP32-S3
-- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55
+- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22
 - **NordicSemi:** nRF52833, nRF52840
 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
 - **NXP:**
diff --git a/docs/boards.md b/docs/boards.md
index c790c7967..53b0da702 100644
--- a/docs/boards.md
+++ b/docs/boards.md
@@ -47,8 +47,9 @@ This code base already had supported for a handful of following boards (sorted a
 
 - [Microchip SAMG55 Xplained Pro](https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMG55-XPRO)
 
-### MicroChip SAML22
+### MicroChip SAML2x
 
+- [SAML21 Xplaind Pro](https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAML21-XPRO-B)
 - [SAML22 Feather](https://github.com/joeycastillo/Feather-Projects/tree/main/SAML22%20Feather)
 - [Sensor Watch](https://github.com/joeycastillo/Sensor-Watch)
 
diff --git a/hw/bsp/saml21/family.c b/hw/bsp/saml21/family.c
deleted file mode 100644
index d2d25ecac..000000000
--- a/hw/bsp/saml21/family.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "sam.h"
-#include "bsp/board.h"
-#include "board.h"
-
-#include "hal/include/hal_gpio.h"
-#include "hal/include/hal_init.h"
-#include "hpl/gclk/hpl_gclk_base.h"
-#include "hpl_mclk_config.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_Handler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-/* Referenced GCLKs (out of 0~4), should be initialized firstly */
-#define _GCLK_INIT_1ST 0x00000000
-/* Not referenced GCLKs, initialized last */
-#define _GCLK_INIT_LAST 0x0000001F
-
-void board_init(void)
-{
-  // Clock init ( follow hpl_init.c )
-  hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
-
-  _set_performance_level(2);
-
-  _osc32kctrl_init_sources();
-  _oscctrl_init_sources();
-  _mclk_init();
-#if _GCLK_INIT_1ST
-  _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
-#endif
-  _oscctrl_init_referenced_generators();
-  _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
-
-#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
-  hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL);
-  hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL);
-#endif
-
-  // Update SystemCoreClock since it is hard coded with asf4 and not correct
-  // Init 1ms tick timer (samd SystemCoreClock may not correct)
-  SystemCoreClock = CONF_CPU_FREQUENCY;
-  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
-
-  // Led init
-  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(LED_PIN, !LED_STATE_ON);
-
-  // Button init
-  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP);
-
-#if CFG_TUSB_OS  == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-  /* USB Clock init
-   * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
-   * for low speed and full speed operation. */
-  hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
-  hri_mclk_set_AHBMASK_USB_bit(MCLK);
-  hri_mclk_set_APBBMASK_USB_bit(MCLK);
-
-  // USB Pin Init
-  gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA24, false);
-  gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF);
-  gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(PIN_PA25, false);
-  gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF);
-
-  gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM);
-  gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
-
-  // Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed
-  hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
-  TCC0->PER.bit.PER = 48000000 / 1000;
-  TCC0->CC[3].bit.CC = 48000000 / 2000;
-  TCC0->CTRLA.bit.ENABLE = true;
-
-  gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3);
-  hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  gpio_set_pin_level(LED_PIN, state);
-}
-
-uint32_t board_button_read(void)
-{
-  // button is active low
-  return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-void _init(void)
-{
-
-}
\ No newline at end of file
diff --git a/hw/bsp/saml21/family.mk b/hw/bsp/saml21/family.mk
deleted file mode 100644
index a6611d5f4..000000000
--- a/hw/bsp/saml21/family.mk
+++ /dev/null
@@ -1,50 +0,0 @@
-UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES += hw/mcu/microchip
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -nostdlib -nostartfiles \
-  -DCONF_OSC32K_CALIB_ENABLE=0 \
-  -DCFG_TUSB_MCU=OPT_MCU_SAML21
-
-SRC_C += \
-	src/portable/microchip/samd/dcd_samd.c \
-	hw/mcu/microchip/saml21/gcc/gcc/startup_saml21.c \
-	hw/mcu/microchip/saml21/gcc/system_saml21.c \
-	hw/mcu/microchip/saml21/hpl/gclk/hpl_gclk.c \
-	hw/mcu/microchip/saml21/hpl/mclk/hpl_mclk.c \
-	hw/mcu/microchip/saml21/hpl/pm/hpl_pm.c \
-	hw/mcu/microchip/saml21/hpl/osc32kctrl/hpl_osc32kctrl.c \
-	hw/mcu/microchip/saml21/hpl/oscctrl/hpl_oscctrl.c \
-	hw/mcu/microchip/saml21/hal/src/hal_atomic.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/hw/mcu/microchip/saml21/ \
-	$(TOP)/hw/mcu/microchip/saml21/config \
-	$(TOP)/hw/mcu/microchip/saml21/include \
-	$(TOP)/hw/mcu/microchip/saml21/hal/include \
-	$(TOP)/hw/mcu/microchip/saml21/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/saml21/hpl/port \
-	$(TOP)/hw/mcu/microchip/saml21/hri \
-	$(TOP)/hw/mcu/microchip/saml21/CMSIS/Include
-
-# For TinyUSB port source 
-VENDOR = microchip
-CHIP_FAMILY = samd
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# flash using bossac at least version 1.8
-# can be found in arduino15/packages/arduino/tools/bossac/
-# Add it to your PATH or change BOSSAC variable to match your installation
-BOSSAC = bossac
-
-flash-bossac: $(BUILD)/$(PROJECT).bin
-	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	$(BOSSAC) --port=$(SERIAL) -U -i --offset=0x2000 -e -w $^ -R
diff --git a/hw/bsp/saml21/boards/atsaml21_xpro/board.h b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
similarity index 100%
rename from hw/bsp/saml21/boards/atsaml21_xpro/board.h
rename to hw/bsp/saml2x/boards/atsaml21_xpro/board.h
diff --git a/hw/bsp/saml21/boards/atsaml21_xpro/board.mk b/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
similarity index 90%
rename from hw/bsp/saml21/boards/atsaml21_xpro/board.mk
rename to hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
index aa77d4a21..81b4ecdcb 100644
--- a/hw/bsp/saml21/boards/atsaml21_xpro/board.mk
+++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
@@ -1,5 +1,7 @@
 CFLAGS += -D__SAML21J18B__
 
+SAML_VARIANT = saml21
+
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/saml21j18b_flash.ld
 
diff --git a/hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld b/hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld
similarity index 100%
rename from hw/bsp/saml21/boards/atsaml21_xpro/saml21j18b_flash.ld
rename to hw/bsp/saml2x/boards/atsaml21_xpro/saml21j18b_flash.ld
diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.mk b/hw/bsp/saml2x/boards/saml22_feather/board.mk
index a6a773137..0605dca19 100644
--- a/hw/bsp/saml2x/boards/saml22_feather/board.mk
+++ b/hw/bsp/saml2x/boards/saml22_feather/board.mk
@@ -1,5 +1,7 @@
 CFLAGS += -D__SAML22J18A__
 
+SAML_VARIANT = saml22
+
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
 
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
index a6a773137..0605dca19 100644
--- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
@@ -1,5 +1,7 @@
 CFLAGS += -D__SAML22J18A__
 
+SAML_VARIANT = saml22
+
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
 
diff --git a/hw/bsp/saml2x/family.c b/hw/bsp/saml2x/family.c
index 1a185a59c..470fde750 100644
--- a/hw/bsp/saml2x/family.c
+++ b/hw/bsp/saml2x/family.c
@@ -108,13 +108,13 @@ void board_init(void)
   gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP);
 
   // Output 500hz PWM on PB23 (TCC0 WO[3]) so we can validate the GCLK1 clock speed
-  hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
-  TCC0->PER.bit.PER = 48000000 / 1000;
-  TCC0->CC[3].bit.CC = 48000000 / 2000;
-  TCC0->CTRLA.bit.ENABLE = true;
-
-  gpio_set_pin_function(PIN_PB23, PINMUX_PB23F_TCC0_WO3);
-  hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
+//  hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
+//  TCC0->PER.bit.PER = 48000000 / 1000;
+//  TCC0->CC[3].bit.CC = 48000000 / 2000;
+//  TCC0->CTRLA.bit.ENABLE = true;
+//
+//  gpio_set_pin_function(PIN_PB23, PINMUX_PB23F_TCC0_WO3);
+//  hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK1_Val | GCLK_PCHCTRL_CHEN);
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index fbe4e66f8..e0f6b2f77 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -1,8 +1,10 @@
 UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES += hw/mcu/microchip
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/microchip
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+MCU_DIR = hw/mcu/microchip/$(SAML_VARIANT)
+
 CFLAGS += \
   -mthumb \
   -mabi=aapcs \
@@ -13,29 +15,25 @@ CFLAGS += \
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
-	hw/mcu/microchip/saml22/gcc/gcc/startup_saml22.c \
-	hw/mcu/microchip/saml22/gcc/system_saml22.c \
-	hw/mcu/microchip/saml22/hpl/gclk/hpl_gclk.c \
-	hw/mcu/microchip/saml22/hpl/mclk/hpl_mclk.c \
-	hw/mcu/microchip/saml22/hpl/pm/hpl_pm.c \
-	hw/mcu/microchip/saml22/hpl/osc32kctrl/hpl_osc32kctrl.c \
-	hw/mcu/microchip/saml22/hpl/oscctrl/hpl_oscctrl.c \
-	hw/mcu/microchip/saml22/hal/src/hal_atomic.c
+	$(MCU_DIR)/gcc/gcc/startup_$(SAML_VARIANT).c \
+	$(MCU_DIR)/gcc/system_$(SAML_VARIANT).c \
+	$(MCU_DIR)/hpl/gclk/hpl_gclk.c \
+	$(MCU_DIR)/hpl/mclk/hpl_mclk.c \
+	$(MCU_DIR)/hpl/pm/hpl_pm.c \
+	$(MCU_DIR)/hpl/osc32kctrl/hpl_osc32kctrl.c \
+	$(MCU_DIR)/hpl/oscctrl/hpl_oscctrl.c \
+	$(MCU_DIR)/hal/src/hal_atomic.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/hw/mcu/microchip/saml22/ \
-	$(TOP)/hw/mcu/microchip/saml22/config \
-	$(TOP)/hw/mcu/microchip/saml22/include \
-	$(TOP)/hw/mcu/microchip/saml22/hal/include \
-	$(TOP)/hw/mcu/microchip/saml22/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/saml22/hpl/port \
-	$(TOP)/hw/mcu/microchip/saml22/hri \
-	$(TOP)/hw/mcu/microchip/saml22/CMSIS/Core/Include
-
-# For TinyUSB port source 
-VENDOR = microchip
-CHIP_FAMILY = samd
+	$(TOP)/$(MCU_DIR)/ \
+	$(TOP)/$(MCU_DIR)/config \
+	$(TOP)/$(MCU_DIR)/include \
+	$(TOP)/$(MCU_DIR)/hal/include \
+	$(TOP)/$(MCU_DIR)/hal/utils/include \
+	$(TOP)/$(MCU_DIR)/hpl/port \
+	$(TOP)/$(MCU_DIR)/hri \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM0

From 35eaa4a4e3a66e909707201c22ea61f97b331793 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 16:25:22 +0700
Subject: [PATCH 0116/2085] Use bug report form

---
 .github/ISSUE_TEMPLATE/bug_report.md  | 35 -------------
 .github/ISSUE_TEMPLATE/bug_report.yml | 71 +++++++++++++++++++++++++++
 2 files changed, 71 insertions(+), 35 deletions(-)
 delete mode 100644 .github/ISSUE_TEMPLATE/bug_report.md
 create mode 100644 .github/ISSUE_TEMPLATE/bug_report.yml

diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md
deleted file mode 100644
index 3beef45d0..000000000
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ /dev/null
@@ -1,35 +0,0 @@
----
-name: Bug Report
-about: Create a report to help us improve
-title: 'Please provide all details at least for Setup/Describe/Reproduce'
-labels: Bug �
-assignees: ''
-
----
-
-**Set Up**
-
-- **PC OS** e.g Ubuntu 20.04 / Windows 10 / macOS 10.15
-- **Board** e.g Feather nRF52840 Express (if custom specify your MCUs)
-- **TinyUSB version** relase version or git hash (preferrably running with master for lastest code) 
-- **Firmware** e.g examples/device/cdc_msc
-
-**Describe The Bug**
-
-A clear and concise description of what the bug is.
-
-**To Reproduce**
-
-Steps to reproduce the behavior:
-1. Go to '...'
-2. Click on '....'
-3. See error
-
-**Screenshots**
-
-If applicable, add screenshots, bus capture to help explain your problem. 
-
-**Log**
-
-If applicable, provide the stack's log (uart/rtt/swo) where the issue occurred as attached txt file, best with comments to explain the actual events.
-Note: To enable logging, add `LOG=2` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=2` in your tusb_config.h. More information can be found at [example's readme](/docs/getting_started.md)
diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
new file mode 100644
index 000000000..41b9185a5
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -0,0 +1,71 @@
+name: Bug Report
+description: Report a problem with TinyUSB.
+title: ''
+labels: Bug �
+assignees: ''
+body:
+  - type: markdown
+    attributes:
+      value: |
+        Thanks for taking the time to fill out this bug report!
+        It's okay to leave some blank if it doesn't apply to your problem.
+
+  - type: dropdown
+    attributes:
+      label: Operating System
+    validations:
+      required: true
+      options:
+              - Linux
+              - MacOS
+              - RaspberryPi OS
+              - Windows 7
+              - Windows 10
+              - Windows 11
+              - Others
+              
+  - type: input
+    attributes:
+      label: Board
+      placeholder: e.g Feather nRF52840 Express
+    validations:
+      required: true      
+
+  - type: textarea
+    attributes:
+      label: Firmware
+      placeholder: e.g examples/device/cdc_msc. If it is custom firmware, please provide links to your minimal sources or as attached files.
+    validations:
+      required: true      
+
+  - type: textarea
+    attributes:
+      label: What happened ?
+      placeholder: A clear and concise description of what the bug is.
+    validations:
+      required: true
+
+  - type: textarea
+    attributes:
+      label: How to reproduce ?
+      placeholder: |
+        1. Go to '...'
+        2. Click on '....'
+        3. See error      
+    validations:
+      required: true
+
+  - type: textarea
+    attributes:
+      label: Debug Log
+      placeholder: |
+        TinyUSB debug log where the issue occurred as attached txt file, best with comments to explain the actual events.
+        Note: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. More information can be found at [example's readme](/docs/getting_started.md)
+    validations:
+      required: false
+
+  - type: textarea
+    attributes:
+      label: Screenshots (if any)
+    validations:
+      required: false

From b6f226dbaaa9e269d2b3a606f92b8e9ed8576d9e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 16:25:28 +0700
Subject: [PATCH 0117/2085] comment out esp32s3 ci due to USB0 not defined in
 IDF linker

---
 .github/workflows/build_esp.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 93d582361..25f4e68f8 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -18,7 +18,8 @@ jobs:
         # ESP32-S2
         - 'espressif_saola_1'
         # ESP32-S3
-        - 'espressif_addax_1'
+        # latest IDF does not define USB0 in linker
+        #- 'espressif_addax_1'
 
     steps:
     - name: Setup Python

From 903e69927340057f32ad43a04980edb3d091464b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 16:30:38 +0700
Subject: [PATCH 0118/2085] fixing bug form

---
 .github/ISSUE_TEMPLATE/bug_report.yml | 17 ++++-------------
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index 41b9185a5..29c797ee5 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -1,15 +1,12 @@
 name: Bug Report
-description: Report a problem with TinyUSB.
-title: ''
-labels: Bug �
-assignees: ''
+description: Report a problem with TinyUSB
+labels: 'Bug �'
 body:
   - type: markdown
     attributes:
       value: |
         Thanks for taking the time to fill out this bug report!
         It's okay to leave some blank if it doesn't apply to your problem.
-
   - type: dropdown
     attributes:
       label: Operating System
@@ -23,28 +20,24 @@ body:
               - Windows 10
               - Windows 11
               - Others
-              
   - type: input
     attributes:
       label: Board
       placeholder: e.g Feather nRF52840 Express
     validations:
-      required: true      
-
+      required: true
   - type: textarea
     attributes:
       label: Firmware
       placeholder: e.g examples/device/cdc_msc. If it is custom firmware, please provide links to your minimal sources or as attached files.
     validations:
-      required: true      
-
+      required: true
   - type: textarea
     attributes:
       label: What happened ?
       placeholder: A clear and concise description of what the bug is.
     validations:
       required: true
-
   - type: textarea
     attributes:
       label: How to reproduce ?
@@ -54,7 +47,6 @@ body:
         3. See error      
     validations:
       required: true
-
   - type: textarea
     attributes:
       label: Debug Log
@@ -63,7 +55,6 @@ body:
         Note: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. More information can be found at [example's readme](/docs/getting_started.md)
     validations:
       required: false
-
   - type: textarea
     attributes:
       label: Screenshots (if any)

From ddcd657e40b276dab1b8896c07af4bbeacb10982 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 16:33:21 +0700
Subject: [PATCH 0119/2085] more fixing

---
 .github/ISSUE_TEMPLATE/bug_report.yml | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index 29c797ee5..d362a5adc 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -7,11 +7,10 @@ body:
       value: |
         Thanks for taking the time to fill out this bug report!
         It's okay to leave some blank if it doesn't apply to your problem.
+
   - type: dropdown
     attributes:
       label: Operating System
-    validations:
-      required: true
       options:
               - Linux
               - MacOS
@@ -20,24 +19,30 @@ body:
               - Windows 10
               - Windows 11
               - Others
+    validations:
+      required: true
+
   - type: input
     attributes:
       label: Board
       placeholder: e.g Feather nRF52840 Express
     validations:
       required: true
+
   - type: textarea
     attributes:
       label: Firmware
       placeholder: e.g examples/device/cdc_msc. If it is custom firmware, please provide links to your minimal sources or as attached files.
     validations:
       required: true
+
   - type: textarea
     attributes:
       label: What happened ?
       placeholder: A clear and concise description of what the bug is.
     validations:
       required: true
+
   - type: textarea
     attributes:
       label: How to reproduce ?
@@ -47,6 +52,7 @@ body:
         3. See error      
     validations:
       required: true
+
   - type: textarea
     attributes:
       label: Debug Log
@@ -55,6 +61,7 @@ body:
         Note: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. More information can be found at [example's readme](/docs/getting_started.md)
     validations:
       required: false
+
   - type: textarea
     attributes:
       label: Screenshots (if any)

From 3465cbd83900d710b2fd52b52ead92c206b13ecf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 16:37:13 +0700
Subject: [PATCH 0120/2085] more bug form update

---
 .github/ISSUE_TEMPLATE/bug_report.yml | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index d362a5adc..2000443c9 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -32,7 +32,9 @@ body:
   - type: textarea
     attributes:
       label: Firmware
-      placeholder: e.g examples/device/cdc_msc. If it is custom firmware, please provide links to your minimal sources or as attached files.
+      placeholder: |
+        e.g examples/device/cdc_msc.
+        If it is custom firmware, please provide links to your minimal sources or as attached files.
     validations:
       required: true
 
@@ -64,6 +66,7 @@ body:
 
   - type: textarea
     attributes:
-      label: Screenshots (if any)
+      label: Screenshots
+      description: If applicable, add screenshots to help explain your problem.
     validations:
       required: false

From e6d6299706a5a75371fdb99d146c7632ead218e1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 16:39:31 +0700
Subject: [PATCH 0121/2085] more bug form template

---
 .github/ISSUE_TEMPLATE/bug_report.yml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index 2000443c9..7c12e1ab7 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -60,7 +60,9 @@ body:
       label: Debug Log
       placeholder: |
         TinyUSB debug log where the issue occurred as attached txt file, best with comments to explain the actual events.
-        Note: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. More information can be found at [example's readme](/docs/getting_started.md)
+        
+        Note: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. 
+        More information can be found at [example's readme](https://github.com/hathach/tinyusb/blob/master/docs/getting_started.md)
     validations:
       required: false
 

From 3a2317b7dc3767337bc3710b6a1489b1c9a4bc67 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 16:40:30 +0700
Subject: [PATCH 0122/2085] bug form update

---
 .github/ISSUE_TEMPLATE/bug_report.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index 7c12e1ab7..291b22079 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -60,7 +60,7 @@ body:
       label: Debug Log
       placeholder: |
         TinyUSB debug log where the issue occurred as attached txt file, best with comments to explain the actual events.
-        
+
         Note: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. 
         More information can be found at [example's readme](https://github.com/hathach/tinyusb/blob/master/docs/getting_started.md)
     validations:

From 5811122cfd04b84c8760991e287e29fc424453fd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Jun 2021 11:58:34 +0700
Subject: [PATCH 0123/2085] change usbh open driver to have max_len and return
 driver len

---
 src/class/cdc/cdc_device.c  | 10 +++---
 src/class/cdc/cdc_host.c    | 62 ++++++++++++++++++-------------------
 src/class/cdc/cdc_host.h    | 10 +++---
 src/class/hid/hid_host.c    | 20 +++++++-----
 src/class/hid/hid_host.h    | 10 +++---
 src/class/msc/msc_host.c    | 13 +++++---
 src/class/msc/msc_host.h    | 20 +++---------
 src/host/hub.c              | 31 ++++++++++---------
 src/host/hub.h              | 10 +++---
 src/host/usbh.c             | 15 ++++-----
 src/host/usbh_classdriver.h | 10 +++---
 11 files changed, 104 insertions(+), 107 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index cac811c45..e622bd616 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -273,9 +273,6 @@ uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
   TU_VERIFY( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
              CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass, 0);
 
-  // Note: 0xFF can be used with RNDIS
-  TU_VERIFY(tu_within(CDC_COMM_PROTOCOL_NONE, itf_desc->bInterfaceProtocol, CDC_COMM_PROTOCOL_ATCOMMAND_CDMA), 0);
-
   // Find available interface
   cdcd_interface_t * p_cdc = NULL;
   for(uint8_t cdc_id=0; cdc_id<CFG_TUD_CDC; cdc_id++)
@@ -303,10 +300,11 @@ uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
 
   if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
   {
-    // notification endpoint if any
-    TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 );
+    // notification endpoint
+    tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
 
-    p_cdc->ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+    TU_ASSERT( usbd_edpt_open(rhport, desc_ep), 0 );
+    p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
     drv_len += tu_desc_len(p_desc);
     p_desc   = tu_desc_next(p_desc);
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 33f1a8ad3..fc7100e81 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -149,29 +149,27 @@ void cdch_init(void)
   tu_memclr(cdch_data, sizeof(cdch_data_t)*CFG_TUSB_HOST_DEVICE_MAX);
 }
 
-bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length)
+uint16_t cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
-  // Only support ACM
-  TU_VERIFY( CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass);
+  (void) max_len;
 
-  // Only support AT commands, no protocol and vendor specific commands.
-  TU_VERIFY(tu_within(CDC_COMM_PROTOCOL_NONE, itf_desc->bInterfaceProtocol, CDC_COMM_PROTOCOL_ATCOMMAND_CDMA) ||
-            0xff == itf_desc->bInterfaceProtocol);
+  // Only support ACM subclass
+  // Protocol 0xFF can be RNDIS device for windows XP
+  TU_VERIFY( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
+             CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass &&
+             0xFF                                     != itf_desc->bInterfaceProtocol, 0);
 
-  uint8_t const * p_desc;
-  cdch_data_t * p_cdc;
+  cdch_data_t * p_cdc = get_itf(dev_addr);
 
-  p_desc = tu_desc_next(itf_desc);
-  p_cdc  = get_itf(dev_addr);
-
-  p_cdc->itf_num   = itf_desc->bInterfaceNumber;
-  p_cdc->itf_protocol = itf_desc->bInterfaceProtocol; // TODO 0xff is consider as rndis candidate, other is virtual Com
+  p_cdc->itf_num      = itf_desc->bInterfaceNumber;
+  p_cdc->itf_protocol = itf_desc->bInterfaceProtocol;
 
   //------------- Communication Interface -------------//
-  (*p_length) = sizeof(tusb_desc_interface_t);
+  uint16_t drv_len = tu_desc_len(itf_desc);
+  uint8_t const * p_desc = tu_desc_next(itf_desc);
 
   // Communication Functional Descriptors
-  while( TUSB_DESC_CS_INTERFACE == p_desc[DESC_OFFSET_TYPE] )
+  while( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
   {
     if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
     {
@@ -179,52 +177,52 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
       p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
     }
 
-    (*p_length) += p_desc[DESC_OFFSET_LEN];
+    drv_len += tu_desc_len(p_desc);
     p_desc = tu_desc_next(p_desc);
   }
 
-  if ( TUSB_DESC_ENDPOINT == p_desc[DESC_OFFSET_TYPE])
+  if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
   {
     // notification endpoint
-    tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) p_desc;
+    tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
 
-    TU_ASSERT( usbh_edpt_open(rhport, dev_addr, ep_desc) );
-    p_cdc->ep_notif = ep_desc->bEndpointAddress;
+    TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep), 0 );
+    p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
-    (*p_length) += p_desc[DESC_OFFSET_LEN];
+    drv_len += tu_desc_len(p_desc);
     p_desc = tu_desc_next(p_desc);
   }
 
   //------------- Data Interface (if any) -------------//
-  if ( (TUSB_DESC_INTERFACE == p_desc[DESC_OFFSET_TYPE]) &&
+  if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
        (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
   {
-    (*p_length) += p_desc[DESC_OFFSET_LEN];
+    // next to endpoint descriptor
+    drv_len += tu_desc_len(p_desc);
     p_desc = tu_desc_next(p_desc);
 
     // data endpoints expected to be in pairs
     for(uint32_t i=0; i<2; i++)
     {
-      tusb_desc_endpoint_t const *ep_desc = (tusb_desc_endpoint_t const *) p_desc;
-      TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType);
-      TU_ASSERT(TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
+      tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+      TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer, 0);
 
-      TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc));
+      TU_ASSERT(usbh_edpt_open(rhport, dev_addr, desc_ep), 0);
 
-      if ( tu_edpt_dir(ep_desc->bEndpointAddress) ==  TUSB_DIR_IN )
+      if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
       {
-        p_cdc->ep_in = ep_desc->bEndpointAddress;
+        p_cdc->ep_in = desc_ep->bEndpointAddress;
       }else
       {
-        p_cdc->ep_out = ep_desc->bEndpointAddress;
+        p_cdc->ep_out = desc_ep->bEndpointAddress;
       }
 
-      (*p_length) += p_desc[DESC_OFFSET_LEN];
+      drv_len += tu_desc_len(p_desc);
       p_desc = tu_desc_next( p_desc );
     }
   }
 
-  return true;
+  return drv_len;
 }
 
 bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 6ff392709..edcd258a8 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -121,11 +121,11 @@ void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_i
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void cdch_init(void);
-bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
-bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num);
-bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
-void cdch_close(uint8_t dev_addr);
+void     cdch_init       (void);
+uint16_t cdch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+bool     cdch_set_config (uint8_t dev_addr, uint8_t itf_num);
+bool     cdch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void     cdch_close      (uint8_t dev_addr);
 
 #ifdef __cplusplus
  }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 16d908a5d..81ed6e8b6 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -247,29 +247,33 @@ static bool config_get_protocol             (uint8_t dev_addr, tusb_control_requ
 static bool config_get_report_desc          (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 static bool config_get_report_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 
-bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t *p_length)
+uint16_t hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
-  TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass);
+  (void) max_len;
 
+  TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass, 0);
+
+  uint16_t drv_len = sizeof(tusb_desc_interface_t);
   uint8_t const *p_desc = (uint8_t const *) desc_itf;
 
   //------------- HID descriptor -------------//
   p_desc = tu_desc_next(p_desc);
   tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc;
-  TU_ASSERT(HID_DESC_TYPE_HID == desc_hid->bDescriptorType);
+  TU_ASSERT(HID_DESC_TYPE_HID == desc_hid->bDescriptorType, 0);
 
   // not enough interface, try to increase CFG_TUH_HID
   // TODO multiple devices
   hidh_device_t* hid_dev = get_dev(dev_addr);
-  TU_ASSERT(hid_dev->inst_count < CFG_TUH_HID);
+  TU_ASSERT(hid_dev->inst_count < CFG_TUH_HID, 0);
 
   //------------- Endpoint Descriptor -------------//
+  drv_len += tu_desc_len(p_desc);
   p_desc = tu_desc_next(p_desc);
   tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-  TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
+  TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType, 0);
 
   // TODO also open endpoint OUT
-  TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep) );
+  TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep), 0 );
 
   hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count);
   hid_dev->inst_count++;
@@ -285,9 +289,9 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   hid_itf->protocol_mode = HID_PROTOCOL_REPORT; // Per Specs: default is report mode
   if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass ) hid_itf->itf_protocol = desc_itf->bInterfaceProtocol;
 
-  *p_length = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
+  drv_len += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
 
-  return true;
+  return drv_len;
 }
 
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index 2e4cce600..6ae7c6721 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -118,11 +118,11 @@ TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t ins
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void hidh_init(void);
-bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t *p_length);
-bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num);
-bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-void hidh_close(uint8_t dev_addr);
+void     hidh_init       (void);
+uint16_t hidh_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
+bool     hidh_set_config (uint8_t dev_addr, uint8_t itf_num);
+bool     hidh_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+void     hidh_close      (uint8_t dev_addr);
 
 #ifdef __cplusplus
 }
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 7f98ef9b1..83cbe7c89 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -360,18 +360,22 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* c
 static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 
-bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t *p_length)
+uint16_t msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
   TU_VERIFY (MSC_SUBCLASS_SCSI == desc_itf->bInterfaceSubClass &&
              MSC_PROTOCOL_BOT  == desc_itf->bInterfaceProtocol);
 
+  // msc driver length is fixed
+  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t);
+  TU_ASSERT(drv_len <= max_len, 0);
+
   msch_interface_t* p_msc = get_itf(dev_addr);
   tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(desc_itf);
 
   for(uint32_t i=0; i<2; i++)
   {
-    TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
-    TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc));
+    TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer, 0);
+    TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc), 0);
 
     if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
     {
@@ -385,9 +389,8 @@ bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   }
 
   p_msc->itf_num = desc_itf->bInterfaceNumber;
-  (*p_length) += sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t);
 
-  return true;
+  return drv_len;
 }
 
 bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index ce4fe64dc..9e4217ba5 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -41,13 +41,6 @@
 #define CFG_TUH_MSC_MAXLUN  4
 #endif
 
-
-/** \addtogroup ClassDriver_MSC
- *  @{
- * \defgroup MSC_Host Host
- *  The interface API includes status checking function, data transferring function and callback functions
- *  @{ */
-
 typedef bool (*tuh_msc_complete_cb_t)(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 
 //--------------------------------------------------------------------+
@@ -113,17 +106,14 @@ TU_ATTR_WEAK void tuh_msc_umount_cb(uint8_t dev_addr);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 
-void msch_init(void);
-bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t *p_length);
-bool msch_set_config(uint8_t dev_addr, uint8_t itf_num);
-bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
-void msch_close(uint8_t dev_addr);
+void     msch_init       (void);
+uint16_t msch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
+bool     msch_set_config (uint8_t dev_addr, uint8_t itf_num);
+bool     msch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void     msch_close      (uint8_t dev_addr);
 
 #ifdef __cplusplus
  }
 #endif
 
 #endif /* _TUSB_MSC_HOST_H_ */
-
-/// @}
-/// @}
diff --git a/src/host/hub.c b/src/host/hub.c
index b2761184d..2ead5bed1 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -144,29 +144,32 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_con
 //--------------------------------------------------------------------+
 void hub_init(void)
 {
-  tu_memclr(hub_data, CFG_TUSB_HOST_DEVICE_MAX*sizeof( hub_interface_t));
+  tu_memclr(hub_data, CFG_TUSB_HOST_DEVICE_MAX*sizeof(hub_interface_t));
 }
 
-bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length)
+uint16_t hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
-  // not support multiple TT yet
-  if ( itf_desc->bInterfaceProtocol > 1 ) return false;
+  // hub driver does not support multiple TT yet
+  TU_VERIFY(TUSB_CLASS_HUB == itf_desc->bInterfaceClass &&
+            0              == itf_desc->bInterfaceSubClass &&
+            1              <= itf_desc->bInterfaceProtocol, 0);
 
-  //------------- Open Interrupt Status Pipe -------------//
-  tusb_desc_endpoint_t const *ep_desc;
-  ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+  // msc driver length is fixed
+  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t);
+  TU_ASSERT(drv_len <= max_len, 0);
 
-  TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType);
-  TU_ASSERT(TUSB_XFER_INTERRUPT == ep_desc->bmAttributes.xfer);
+  //------------- Interrupt Status endpoint -------------//
+  tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+
+  TU_ASSERT(TUSB_DESC_ENDPOINT  == desc_ep->bDescriptorType &&
+            TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0);
   
-  TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc));
+  TU_ASSERT(usbh_edpt_open(rhport, dev_addr, desc_ep));
 
   hub_data[dev_addr-1].itf_num = itf_desc->bInterfaceNumber;
-  hub_data[dev_addr-1].ep_in   = ep_desc->bEndpointAddress;
+  hub_data[dev_addr-1].ep_in   = desc_ep->bEndpointAddress;
 
-  (*p_length) = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t);
-
-  return true;
+  return drv_len;
 }
 
 void hub_close(uint8_t dev_addr)
diff --git a/src/host/hub.h b/src/host/hub.h
index a5111b8e7..c9ffe4985 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -181,11 +181,11 @@ bool hub_status_pipe_queue(uint8_t dev_addr);
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void hub_init(void);
-bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t *p_length);
-bool hub_set_config(uint8_t dev_addr, uint8_t itf_num);
-bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
-void hub_close(uint8_t dev_addr);
+void     hub_init       (void);
+uint16_t hub_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+bool     hub_set_config (uint8_t dev_addr, uint8_t itf_num);
+bool     hub_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void     hub_close      (uint8_t dev_addr);
 
 #ifdef __cplusplus
  }
diff --git a/src/host/usbh.c b/src/host/usbh.c
index bad1aa61a..93621c42a 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -984,11 +984,12 @@ static bool enum_set_config_complete(uint8_t dev_addr, tusb_control_request_t co
 static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
 {
   usbh_device_t* dev = &_usbh_devices[dev_addr];
-  uint8_t const* p_desc = (uint8_t const*) desc_cfg;
-  p_desc = tu_desc_next(p_desc);
+
+  uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
+  uint8_t const* p_desc   = tu_desc_next(desc_cfg);
 
   // parse each interfaces
-  while( p_desc < _usbh_ctrl_buf + desc_cfg->wTotalLength )
+  while( p_desc < desc_end )
   {
     // TODO Do we need to use IAD
     // tusb_desc_interface_assoc_t const * desc_itf_assoc = NULL;
@@ -1003,8 +1004,9 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
 
     tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
+    uint16_t const remaining_len = desc_end-p_desc;
 
-    // Check if class is supported
+    // Check if class is supported TODO drop class_code
     uint8_t drv_id;
     for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
     {
@@ -1034,9 +1036,8 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
       {
         TU_LOG2("%s open\r\n", driver->name);
 
-        uint16_t itf_len = 0;
-        TU_ASSERT( driver->open(dev->rhport, dev_addr, desc_itf, &itf_len) );
-        TU_ASSERT( itf_len >= sizeof(tusb_desc_interface_t) );
+        uint16_t const itf_len = driver->open(dev->rhport, dev_addr, desc_itf, remaining_len);
+        TU_ASSERT( sizeof(tusb_desc_interface_t) <= itf_len && itf_len <= remaining_len);
         p_desc += itf_len;
       }
     }
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index 07480fe8e..0736fefa1 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -45,11 +45,11 @@ typedef struct {
 
   uint8_t class_code;
 
-  void (* const init       )(void);
-  bool (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t* outlen);
-  bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
-  bool (* const xfer_cb    )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-  void (* const close      )(uint8_t dev_addr);
+  void     (* const init       )(void);
+  uint16_t (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
+  bool     (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
+  bool     (* const xfer_cb    )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+  void     (* const close      )(uint8_t dev_addr);
 } usbh_class_driver_t;
 
 // Call by class driver to tell USBH that it has complete the enumeration

From c99b70c08cb9c3b252e015fd455c35674282aa91 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Jun 2021 12:35:51 +0700
Subject: [PATCH 0124/2085] force boot protocol for keyboard/mouse

---
 src/class/hid/hid_host.c | 27 +++++++++++++++------------
 src/class/hid/hid_host.h |  6 +++---
 2 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 81ed6e8b6..59fbb097e 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -98,7 +98,7 @@ uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance)
   return hid_itf->itf_protocol;
 }
 
-bool tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
+uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
 {
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
   return hid_itf->protocol_mode;
@@ -243,7 +243,7 @@ void hidh_close(uint8_t dev_addr)
 // Enumeration
 //--------------------------------------------------------------------+
 
-static bool config_get_protocol             (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool config_set_protocol             (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 static bool config_get_report_desc          (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 static bool config_get_report_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 
@@ -286,7 +286,8 @@ uint16_t hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const
   hid_itf->report_desc_type = desc_hid->bReportType;
   hid_itf->report_desc_len  = tu_unaligned_read16(&desc_hid->wReportLength);
 
-  hid_itf->protocol_mode = HID_PROTOCOL_REPORT; // Per Specs: default is report mode
+  // Per HID Specs: default is Report protocol, though we will force Boot protocol when set_config
+  hid_itf->protocol_mode = HID_PROTOCOL_BOOT;
   if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass ) hid_itf->itf_protocol = desc_itf->bInterfaceProtocol;
 
   drv_len += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
@@ -318,42 +319,44 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
     .wLength  = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &request, NULL, (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? config_get_protocol : config_get_report_desc) );
+  TU_ASSERT( tuh_control_xfer(dev_addr, &request, NULL, (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? config_set_protocol : config_get_report_desc) );
 
   return true;
 }
 
-static bool config_get_protocol(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+// Force device to work in BOOT protocol
+static bool config_set_protocol(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
-  // Stall is a valid response for SET_IDLE GET_PROTOCOL, therefore we could ignore its result
+  // Stall is a valid response for SET_PROTOCOL, therefore we could ignore its result
   (void) result;
 
   uint8_t const itf_num     = (uint8_t) request->wIndex;
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
-  TU_LOG2("HID Get Protocol\r\n");
+  TU_LOG2("HID Set Protocol\r\n");
+  hid_itf->protocol_mode = HID_PROTOCOL_BOOT;
   tusb_control_request_t const new_request =
   {
     .bmRequestType_bit =
     {
       .recipient = TUSB_REQ_RCPT_INTERFACE,
       .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_IN
+      .direction = TUSB_DIR_OUT
     },
-    .bRequest = HID_REQ_CONTROL_GET_PROTOCOL,
-    .wValue   = 0,
+    .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
+    .wValue   = HID_PROTOCOL_BOOT,
     .wIndex   = hid_itf->itf_num,
     .wLength  = 1
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, &hid_itf->protocol_mode, config_get_report_desc) );
+  TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, NULL, config_get_report_desc) );
   return false;
 }
 
 static bool config_get_report_desc(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
-  // Stall is a valid response for SET_IDLE GET_PROTOCOL, therefore we could ignore its result
+  // Stall is a valid response for SET_IDLE, therefore we could ignore its result
   (void) result;
 
   uint8_t const itf_num     = (uint8_t) request->wIndex;
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index 6ae7c6721..b95f0d9b7 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -66,9 +66,9 @@ bool tuh_hid_mounted(uint8_t dev_addr, uint8_t instance);
 // Get interface supported protocol (bInterfaceProtocol) check out hid_interface_protocol_enum_t for possible values
 uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance);
 
-// Get current active protocol: HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
-// Note: as HID spec, device will be initialized in Report mode
-bool tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance);
+// Get current protocol: HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
+// Note: device will be initialized in Boot protocol for simplicity.
+uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance);
 
 // Set protocol to HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
 // This function is only supported by Boot interface (tuh_n_hid_interface_protocol() != NONE)

From 58d3e8c08b05ac00bd2510c04f7679b5f7503404 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Jun 2021 12:47:48 +0700
Subject: [PATCH 0125/2085] update func comment

---
 src/class/hid/hid_host.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index b95f0d9b7..ef203123d 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -67,7 +67,8 @@ bool tuh_hid_mounted(uint8_t dev_addr, uint8_t instance);
 uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance);
 
 // Get current protocol: HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
-// Note: device will be initialized in Boot protocol for simplicity.
+// Note: Device will be initialized in Boot protocol for simplicity.
+//       Application can use set_protocol() to switch back to Report protocol.
 uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance);
 
 // Set protocol to HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)

From 268dcc8d20da15e64ba7198f0412f758f6b8a911 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Jun 2021 13:05:12 +0700
Subject: [PATCH 0126/2085] fix issue with weird msc device with 3 endpoints

---
 src/class/msc/msc_host.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 83cbe7c89..2c027deff 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -366,7 +366,7 @@ uint16_t msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const
              MSC_PROTOCOL_BOT  == desc_itf->bInterfaceProtocol);
 
   // msc driver length is fixed
-  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t);
+  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
   TU_ASSERT(drv_len <= max_len, 0);
 
   msch_interface_t* p_msc = get_itf(dev_addr);

From efc12ae7d4e2c3d6834203aff5dd1178ed601288 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Jun 2021 23:57:57 +0700
Subject: [PATCH 0127/2085] fix SET_PROTOCOl, update hid host behavior for
 default boot interface

---
 examples/host/cdc_msc_hid/src/hid_app.c | 162 ++++++++++++++----------
 src/class/hid/hid_host.c                |  12 +-
 2 files changed, 106 insertions(+), 68 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index 817646dab..fd00cf653 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -39,11 +39,15 @@
 static uint8_t const keycode2ascii[128][2] =  { HID_KEYCODE_TO_ASCII };
 
 // Each HID instance can has multiple reports
-static uint8_t _report_count[CFG_TUH_HID];
-static tuh_hid_report_info_t _report_info_arr[CFG_TUH_HID][MAX_REPORT];
+static struct
+{
+  uint8_t report_count;
+  tuh_hid_report_info_t report_info[MAX_REPORT];
+}hid_info[CFG_TUH_HID];
 
 static void process_kbd_report(hid_keyboard_report_t const *report);
 static void process_mouse_report(hid_mouse_report_t const * report);
+static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len);
 
 void hid_app_task(void)
 {
@@ -61,13 +65,19 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
 {
   printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance);
 
-  // Interface protocol
-  const char* protocol_str[] = { "None", "Keyboard", "Mouse" }; // hid_protocol_type_t
-  uint8_t const interface_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+  // Interface protocol (hid_interface_protocol_enum_t)
+  const char* protocol_str[] = { "None", "Keyboard", "Mouse" };
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
 
-  // Parse report descriptor with built-in parser
-  _report_count[instance] = tuh_hid_parse_report_descriptor(_report_info_arr[instance], MAX_REPORT, desc_report, desc_len);
-  printf("HID has %u reports and interface protocol = %s\r\n", _report_count[instance], protocol_str[interface_protocol]);
+  printf("HID Interface Protocol = %s\r\n", protocol_str[itf_protocol]);
+
+  // By default host stack will use activate boot protocol on supported interface.
+  // Therefore for this simple example, we only need to parse generic report descriptor (with built-in parser)
+  if ( itf_protocol == HID_ITF_PROTOCOL_NONE )
+  {
+    hid_info[instance].report_count = tuh_hid_parse_report_descriptor(hid_info[instance].report_info, MAX_REPORT, desc_report, desc_len);
+    printf("HID has %u reports \r\n", hid_info[instance].report_count);
+  }
 }
 
 // Invoked when device with hid interface is un-mounted
@@ -79,66 +89,24 @@ void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
 // Invoked when received report from device via interrupt endpoint
 void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
 {
-  (void) dev_addr;
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
 
-  uint8_t const rpt_count = _report_count[instance];
-  tuh_hid_report_info_t* rpt_info_arr = _report_info_arr[instance];
-  tuh_hid_report_info_t* rpt_info = NULL;
-
-  if ( rpt_count == 1 && rpt_info_arr[0].report_id == 0)
+  switch (itf_protocol)
   {
-    // Simple report without report ID as 1st byte
-    rpt_info = &rpt_info_arr[0];
-  }else
-  {
-    // Composite report, 1st byte is report ID, data starts from 2nd byte
-    uint8_t const rpt_id = report[0];
+    case HID_ITF_PROTOCOL_KEYBOARD:
+      TU_LOG2("HID receive boot keyboard report\r\n");
+      process_kbd_report( (hid_keyboard_report_t const*) report );
+    break;
 
-    // Find report id in the arrray
-    for(uint8_t i=0; i<rpt_count; i++)
-    {
-      if (rpt_id == rpt_info_arr[i].report_id )
-      {
-        rpt_info = &rpt_info_arr[i];
-        break;
-      }
-    }
+    case HID_ITF_PROTOCOL_MOUSE:
+      TU_LOG2("HID receive boot mouse report\r\n");
+      process_mouse_report( (hid_mouse_report_t const*) report );
+    break;
 
-    report++;
-    len--;
-  }
-
-  if (!rpt_info)
-  {
-    printf("Couldn't find the report info for this report !\r\n");
-    return;
-  }
-
-  // For complete list of Usage Page & Usage checkout src/class/hid/hid.h. For examples:
-  // - Keyboard                     : Desktop, Keyboard
-  // - Mouse                        : Desktop, Mouse
-  // - Gamepad                      : Desktop, Gamepad
-  // - Consumer Control (Media Key) : Consumer, Consumer Control
-  // - System Control (Power key)   : Desktop, System Control
-  // - Generic (vendor)             : 0xFFxx, xx
-  if ( rpt_info->usage_page == HID_USAGE_PAGE_DESKTOP )
-  {
-    switch (rpt_info->usage)
-    {
-      case HID_USAGE_DESKTOP_KEYBOARD:
-        TU_LOG1("HID receive keyboard report\r\n");
-        // Assume keyboard follow boot report layout
-        process_kbd_report( (hid_keyboard_report_t const*) report );
-      break;
-
-      case HID_USAGE_DESKTOP_MOUSE:
-        TU_LOG1("HID receive mouse report\r\n");
-        // Assume mouse follow boot report layout
-        process_mouse_report( (hid_mouse_report_t const*) report );
-      break;
-
-      default: break;
-    }
+    default:
+      // Generic report requires matching ReportID and contents with previous parsed report info
+      process_generic_report(dev_addr, instance, report, len);
+    break;
   }
 }
 
@@ -243,3 +211,69 @@ static void process_mouse_report(hid_mouse_report_t const * report)
   //------------- cursor movement -------------//
   cursor_movement(report->x, report->y, report->wheel);
 }
+
+//--------------------------------------------------------------------+
+// Generic Report
+//--------------------------------------------------------------------+
+static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
+{
+  uint8_t const rpt_count = hid_info[instance].report_count;
+  tuh_hid_report_info_t* rpt_info_arr = hid_info[instance].report_info;
+  tuh_hid_report_info_t* rpt_info = NULL;
+
+  if ( rpt_count == 1 && rpt_info_arr[0].report_id == 0)
+  {
+    // Simple report without report ID as 1st byte
+    rpt_info = &rpt_info_arr[0];
+  }else
+  {
+    // Composite report, 1st byte is report ID, data starts from 2nd byte
+    uint8_t const rpt_id = report[0];
+
+    // Find report id in the arrray
+    for(uint8_t i=0; i<rpt_count; i++)
+    {
+      if (rpt_id == rpt_info_arr[i].report_id )
+      {
+        rpt_info = &rpt_info_arr[i];
+        break;
+      }
+    }
+
+    report++;
+    len--;
+  }
+
+  if (!rpt_info)
+  {
+    printf("Couldn't find the report info for this report !\r\n");
+    return;
+  }
+
+  // For complete list of Usage Page & Usage checkout src/class/hid/hid.h. For examples:
+  // - Keyboard                     : Desktop, Keyboard
+  // - Mouse                        : Desktop, Mouse
+  // - Gamepad                      : Desktop, Gamepad
+  // - Consumer Control (Media Key) : Consumer, Consumer Control
+  // - System Control (Power key)   : Desktop, System Control
+  // - Generic (vendor)             : 0xFFxx, xx
+  if ( rpt_info->usage_page == HID_USAGE_PAGE_DESKTOP )
+  {
+    switch (rpt_info->usage)
+    {
+      case HID_USAGE_DESKTOP_KEYBOARD:
+        TU_LOG1("HID receive keyboard report\r\n");
+        // Assume keyboard follow boot report layout
+        process_kbd_report( (hid_keyboard_report_t const*) report );
+      break;
+
+      case HID_USAGE_DESKTOP_MOUSE:
+        TU_LOG1("HID receive mouse report\r\n");
+        // Assume mouse follow boot report layout
+        process_mouse_report( (hid_mouse_report_t const*) report );
+      break;
+
+      default: break;
+    }
+  }
+}
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 59fbb097e..091c5c1c4 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -327,7 +327,7 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
 // Force device to work in BOOT protocol
 static bool config_set_protocol(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
-  // Stall is a valid response for SET_PROTOCOL, therefore we could ignore its result
+  // Stall is a valid response for SET_IDLE, therefore we could ignore its result
   (void) result;
 
   uint8_t const itf_num     = (uint8_t) request->wIndex;
@@ -347,7 +347,7 @@ static bool config_set_protocol(uint8_t dev_addr, tusb_control_request_t const *
     .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
     .wValue   = HID_PROTOCOL_BOOT,
     .wIndex   = hid_itf->itf_num,
-    .wLength  = 1
+    .wLength  = 0
   };
 
   TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, NULL, config_get_report_desc) );
@@ -356,8 +356,12 @@ static bool config_set_protocol(uint8_t dev_addr, tusb_control_request_t const *
 
 static bool config_get_report_desc(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
-  // Stall is a valid response for SET_IDLE, therefore we could ignore its result
-  (void) result;
+  // We can be here after SET_IDLE or SET_PROTOCOL (boot device)
+  // Trigger assert if result is not successful with set protocol
+  if ( request->bRequest != HID_REQ_CONTROL_SET_IDLE )
+  {
+    TU_ASSERT(result == XFER_RESULT_SUCCESS);
+  }
 
   uint8_t const itf_num     = (uint8_t) request->wIndex;
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);

From c172caa288213535ed5c59cea2c13d0e5b4a0597 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 29 Jun 2021 00:03:34 +0700
Subject: [PATCH 0128/2085] clean up

---
 src/class/hid/hid_host.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 091c5c1c4..40b6f5631 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -351,7 +351,7 @@ static bool config_set_protocol(uint8_t dev_addr, tusb_control_request_t const *
   };
 
   TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, NULL, config_get_report_desc) );
-  return false;
+  return true;
 }
 
 static bool config_get_report_desc(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)

From 36d2214e39605bdcb64ae837ea0aa657d0633512 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 29 Jun 2021 00:14:01 +0700
Subject: [PATCH 0129/2085] fix warnings

---
 examples/host/cdc_msc_hid/src/hid_app.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index fd00cf653..420600f9a 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -217,6 +217,8 @@ static void process_mouse_report(hid_mouse_report_t const * report)
 //--------------------------------------------------------------------+
 static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
 {
+  (void) dev_addr;
+
   uint8_t const rpt_count = hid_info[instance].report_count;
   tuh_hid_report_info_t* rpt_info_arr = hid_info[instance].report_info;
   tuh_hid_report_info_t* rpt_info = NULL;

From 36ba9608bd2e70513d5ede87c3cefe38d7edf603 Mon Sep 17 00:00:00 2001
From: Wini-Buh <info@winformatik.ch>
Date: Tue, 29 Jun 2021 00:43:41 +0200
Subject: [PATCH 0130/2085] Merge from current master. Fixed a compilation
 error with the GNUC toolchain

---
 src/portable/renesas/usba/dcd_usba.c | 13 +++++++------
 src/tusb_option.h                    |  5 +----
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index bb4a08e2b..6f55a7226 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Koji Kitayama
+ * Portions copyrighted (c) 2021 Roland Winistoerfer
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -26,13 +27,9 @@
 
 #include "tusb_option.h"
 
-<<<<<<< HEAD
-#if TUSB_OPT_DEVICE_ENABLED && (( CFG_TUSB_MCU == OPT_MCU_RX63X ) || ( CFG_TUSB_MCU == OPT_MCU_RX72N ))
-
-=======
 #if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
-                                 CFG_TUSB_MCU == OPT_MCU_RX65X)
->>>>>>> origin/master
+                                 CFG_TUSB_MCU == OPT_MCU_RX65X || \
+                                 CFG_TUSB_MCU == OPT_MCU_RX72N )
 #include "device/dcd.h"
 #include "iodefine.h"
 
@@ -524,7 +521,11 @@ static void process_set_address(uint8_t rhport)
   const uint32_t addr = USB0.USBADDR.BIT.USBADDR;
   if (!addr) return;
   const tusb_control_request_t setup_packet = {
+#if defined(__GNUC__)
+      .bmRequestType = 0,
+#else
       .bmRequestType = { 0 },  /* Note: CCRX needs the braces over this struct member */
+#endif
       .bRequest      = 5,
       .wValue        = addr,
       .wIndex        = 0,
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 2a68dcbc1..e9a7ac54a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -113,11 +113,8 @@
 
 // Renesas RX
 #define OPT_MCU_RX63X            1400 ///< Renesas RX63N/631
-<<<<<<< HEAD
-#define OPT_MCU_RX72N            1401 ///< Renesas RX72N
-=======
 #define OPT_MCU_RX65X            1401 ///< Renesas RX65N/RX651
->>>>>>> origin/master
+#define OPT_MCU_RX72N            1402 ///< Renesas RX72N
 
 // Mind Motion
 #define OPT_MCU_MM32F327X        1500 ///< Mind Motion MM32F327

From 5877f20d4b5d54b2dfe310fedddf1c30fe6dc66c Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 29 Jun 2021 10:57:26 +0200
Subject: [PATCH 0131/2085] Fix IAR compile error on pointer type. Clean up
 warnings.

Signed-off-by: MasterPhi <admin@hifiphile.com>
---
 src/class/audio/audio_device.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 7ad7edf9e..7263958df 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -885,7 +885,7 @@ range [-1, +1)
  * */
 
 // Helper function
-static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, void * src, uint8_t * src_end, uint8_t * dst, uint8_t const n_ff_used)
+static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, uint8_t * src, uint8_t * src_end, uint8_t * dst, uint8_t const n_ff_used)
 {
   // Optimize for fast half word copies
   typedef struct{
@@ -900,15 +900,15 @@ static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const
   switch (nBytesToCopy)
   {
     case 1:
-      while((uint8_t *)src < src_end)
+      while(src < src_end)
       {
-        *dst = *(uint8_t *)src++;
+        *dst = *src++;
         dst += n_ff_used;
       }
       break;
 
     case 2:
-      while((uint8_t *)src < src_end)
+      while(src < src_end)
       {
         *(unaligned_uint16_t*)dst = *(unaligned_uint16_t*)src;
         src += 2;
@@ -917,23 +917,23 @@ static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const
       break;
 
     case 3:
-      while((uint8_t *)src < src_end)
+      while(src < src_end)
       {
         //        memcpy(dst, src, 3);
         //        src = (uint8_t *)src + 3;
         //        dst += 3 * n_ff_used;
 
         // TODO: Is there a faster way to copy 3 bytes?
-        *dst++ = *(uint8_t *)src++;
-        *dst++ = *(uint8_t *)src++;
-        *dst++ = *(uint8_t *)src++;
+        *dst++ = *src++;
+        *dst++ = *src++;
+        *dst++ = *src++;
 
         dst += 3 * (n_ff_used - 1);
       }
       break;
 
     case 4:
-      while((uint8_t *)src < src_end)
+      while(src < src_end)
       {
         *(unaligned_uint32_t*)dst = *(unaligned_uint32_t*)src;
         src += 4;
@@ -993,7 +993,7 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
     if (info.len_lin != 0)
     {
       info.len_lin = tu_min16(nBytesPerFFToSend, info.len_lin);       // Limit up to desired length
-      src_end = info.ptr_lin + info.len_lin;
+      src_end = (uint8_t *)info.ptr_lin + info.len_lin;
       dst = audiod_interleaved_copy_bytes_fast_encode(nBytesToCopy, info.ptr_lin, src_end, dst, n_ff_used);
 
       // Limit up to desired length
@@ -1002,7 +1002,7 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
       // Handle wrapped part of FIFO
       if (info.len_wrap != 0)
       {
-        src_end = info.ptr_wrap + info.len_wrap;
+        src_end = (uint8_t *)info.ptr_wrap + info.len_wrap;
         audiod_interleaved_copy_bytes_fast_encode(nBytesToCopy, info.ptr_wrap, src_end, dst, n_ff_used);
       }
 
@@ -1956,7 +1956,7 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req
     }
     break;
 
-    case TUSB_REQ_RCPT_ENDPOINT: ;      // The semicolon is there to enable a declaration right after the label
+    case TUSB_REQ_RCPT_ENDPOINT:
     {
       uint8_t ep = TU_U16_LOW(p_request->wIndex);
 
@@ -2142,10 +2142,10 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
       if (as_itf == audio->ep_in_as_intf_num)
       {
         audio->n_channels_tx = ((audio_desc_cs_as_interface_t const * )p_desc)->bNrChannels;
-        audio->format_type_tx = ((audio_desc_cs_as_interface_t const * )p_desc)->bFormatType;
+        audio->format_type_tx = (audio_format_type_t)(((audio_desc_cs_as_interface_t const * )p_desc)->bFormatType);
 
 #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
-        audio->format_type_I_tx = ((audio_desc_cs_as_interface_t const * )p_desc)->bmFormats;
+        audio->format_type_I_tx = (audio_data_format_type_I_t)(((audio_desc_cs_as_interface_t const * )p_desc)->bmFormats);
 #endif
       }
 #endif

From 2d423514ee3e538408afe91693652d6079291195 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 29 Jun 2021 16:33:32 +0700
Subject: [PATCH 0132/2085] rename rx65n cloud kit to target

adding note for adding jlink support for rx65n_target board
---
 docs/boards.md                                |  2 +-
 .../board.mk                                  |  0
 .../r5f565ne.ld                               |  0
 .../rx65n_target.c}                           | 31 +++++++++++++++++++
 4 files changed, 32 insertions(+), 1 deletion(-)
 rename hw/bsp/rx/boards/{rx65n_cloud_kit => rx65n_target}/board.mk (100%)
 rename hw/bsp/rx/boards/{rx65n_cloud_kit => rx65n_target}/r5f565ne.ld (100%)
 rename hw/bsp/rx/boards/{rx65n_cloud_kit/rx65n_cloud_kit.c => rx65n_target/rx65n_target.c} (80%)

diff --git a/docs/boards.md b/docs/boards.md
index 53b0da702..324500bd1 100644
--- a/docs/boards.md
+++ b/docs/boards.md
@@ -127,7 +127,7 @@ This code base already had supported for a handful of following boards (sorted a
 ### Renesas RX
 
 - [GR-CITRUS](https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-citrus)
-- [Renesas RX65N Cloud Kit](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rx65n-cloud-kit-renesas-rx65n-cloud-kit)
+- [Renesas RX65N Target Board](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk5rx65n0c00000br-target-board-rx65n)
 
 ### Raspberry Pi RP2040
 
diff --git a/hw/bsp/rx/boards/rx65n_cloud_kit/board.mk b/hw/bsp/rx/boards/rx65n_target/board.mk
similarity index 100%
rename from hw/bsp/rx/boards/rx65n_cloud_kit/board.mk
rename to hw/bsp/rx/boards/rx65n_target/board.mk
diff --git a/hw/bsp/rx/boards/rx65n_cloud_kit/r5f565ne.ld b/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld
similarity index 100%
rename from hw/bsp/rx/boards/rx65n_cloud_kit/r5f565ne.ld
rename to hw/bsp/rx/boards/rx65n_target/r5f565ne.ld
diff --git a/hw/bsp/rx/boards/rx65n_cloud_kit/rx65n_cloud_kit.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
similarity index 80%
rename from hw/bsp/rx/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
rename to hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index 895b82e23..96d8f36f0 100644
--- a/hw/bsp/rx/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -24,6 +24,37 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* How to connect JLink and RX65n Target and option board
+ * (For original comment https://github.com/hathach/tinyusb/pull/922#issuecomment-869786131)
+ *
+ * To enable JTAG, RX65N requires following connections on main board.
+ * - short EJ2 jumper header, to disable onboard E2L.
+ * - short EMLE(J1-2) and 3V3(J1-14 or J2-10), to enable In-Circuit Emulator.
+ *
+ * Note: For RX65N-Cloud-Kit, the option board's JTAG pins to some switches or floating.
+ * To use JLink with the option board, I think some further modifications will be necessary.
+ *
+ * | Function  | RX65N pin  | main board | option board | JLink connector |
+ * |:---------:|:----------:|:----------:|:------------:|:---------------:|
+ * | 3V3       | VCC        |   J1-14    | CN5-6        |    1            |
+ * | TRST      | P34        |   J1-16    | CN5-7        |    3            |
+ * | GND       | VSS        |   J1-12    | CN5-5        |    4            |
+ * | TDI       | P30        |   J1-20    | CN5-10       |    5            |
+ * | TMS       | P31        |   J1-19    | USER_SW      |    7            |
+ * | TCK/FINEC | P27        |   J1-21    | N/A          |    9            |
+ * | TDO       | P26        |   J1-22    | CN5-9        |   13            |
+ * | nRES      | RES#       |   J1-10    | RESET_SW     |   15            |
+ *
+ * JLink firmware needs to update to V6.96 or newer version to avoid
+ * [a bug](https://forum.segger.com/index.php/Thread/7758-SOLVED-Bug-in-JLink-from-V6-88b-regarding-RX65N)
+ * regarding downloading.
+ *
+ * When using SEGGER RTT, `RX_NEWLIB=0` should be added to make command arguments.
+ * The option is used to change the C runtime library to `optlib` from `newlib`.
+ * RTT may not work with `newlib`.
+ *
+ */
+
 #include "bsp/board.h"
 #include "iodefine.h"
 #include "interrupt_handlers.h"

From b2fa7358cf93ec49c2e931034c89b605b0820bb1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 29 Jun 2021 16:38:38 +0700
Subject: [PATCH 0133/2085] fix typo

---
 hw/bsp/rx/boards/gr_citrus/gr_citrus.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
index 6697012a7..b773e0dd0 100644
--- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
+++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
@@ -34,7 +34,7 @@
  *
  * The pads are [the back side of GR-CITRUS](https://www.slideshare.net/MinaoYamamoto/grcitrusrx631/2).
  * 
- * Connet the pins between GR-CITRUS and JLink as follows.
+ * Connect the pins between GR-CITRUS and JLink as follows.
  * 
  * | JTAG Function | GR-CITRUS pin name| JLink pin No.| note     |
  * |:-------------:|:-----------------:|:------------:|:--------:|

From 3eec011a7c7f7c81954a417b9683eded91ad86e5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 29 Jun 2021 17:28:35 +0700
Subject: [PATCH 0134/2085] add tud_vendor_control_request_cb() to poisoned
 list

---
 src/common/tusb_compiler.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 679060b20..f755e13f4 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -83,6 +83,10 @@
   #define TU_BSWAP16(u16) (__builtin_bswap16(u16))
   #define TU_BSWAP32(u32) (__builtin_bswap32(u32))
 
+  // List of obsolete callback function that is renamed and should not be defined.
+  // Put it here since only gcc support this pragma
+  #pragma GCC poison tud_vendor_control_request_cb
+
 #elif defined(__TI_COMPILER_VERSION__)
   #define TU_ATTR_ALIGNED(Bytes)        __attribute__ ((aligned(Bytes)))
   #define TU_ATTR_SECTION(sec_name)     __attribute__ ((section(#sec_name)))

From 4c0cce4b1df707aa1aeb5e861971b5b31e94a416 Mon Sep 17 00:00:00 2001
From: Wini-Buh <info@winformatik.ch>
Date: Tue, 29 Jun 2021 21:45:18 +0200
Subject: [PATCH 0135/2085] Make toolchain dependency more consistent

---
 src/portable/renesas/usba/dcd_usba.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 6f55a7226..c7a6aef47 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -521,10 +521,10 @@ static void process_set_address(uint8_t rhport)
   const uint32_t addr = USB0.USBADDR.BIT.USBADDR;
   if (!addr) return;
   const tusb_control_request_t setup_packet = {
-#if defined(__GNUC__)
-      .bmRequestType = 0,
-#else
+#if defined(__CCRX__)
       .bmRequestType = { 0 },  /* Note: CCRX needs the braces over this struct member */
+#else
+      .bmRequestType = 0,
 #endif
       .bRequest      = 5,
       .wValue        = addr,

From 2b2549b57316033e544e3261334e3e20224563ce Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 30 Jun 2021 16:50:32 +0200
Subject: [PATCH 0136/2085] Fix fifo overflow correction.

---
 src/common/tusb_fifo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 1eb886aa1..1229201b8 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -342,7 +342,7 @@ static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
   // We limit the index space of p such that a correct wrap around happens
   // Check for a wrap around or if we are in unused index space - This has to be checked first!!
   // We are exploiting the wrap around to the correct index
-  if ((p < p - offset) || (p - offset > f->max_pointer_idx))
+  if ((p < (uint16_t)(p - offset)) || ((uint16_t)(p - offset) > f->max_pointer_idx))
   {
     p = (p - offset) - f->non_used_index_space;
   }

From 7321972380b7bf74557293ba975e912f2941ae02 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 30 Jun 2021 20:26:27 +0200
Subject: [PATCH 0137/2085] Force unsigned compare on advance_pointer.

---
 src/common/tusb_fifo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 1229201b8..73217cf75 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -325,7 +325,7 @@ static uint16_t advance_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
   // We are exploiting the wrap around to the correct index
 
   // TODO warning: assuming signed overflow does not occur when assuming that (X + c) < X is always false [-Wstrict-overflow]
-  if ((p > p + offset) || (p + offset > f->max_pointer_idx))
+  if ((p > (uint16_t)(p + offset)) || ((uint16_t)(p + offset) > f->max_pointer_idx))
   {
     p = (p + offset) + f->non_used_index_space;
   }

From 74b51d43e1e8e14def49c140f8f063eb56c9e4d2 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 30 Jun 2021 20:26:44 +0200
Subject: [PATCH 0138/2085] Add test CI.

---
 test/test/test_fifo.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/test/test/test_fifo.c b/test/test/test_fifo.c
index f9bfc5f03..0a5f4d3b9 100644
--- a/test/test/test_fifo.c
+++ b/test/test/test_fifo.c
@@ -292,3 +292,27 @@ void test_full(void)
 
   // write info
 }
+
+void test_rd_idx_wrap()
+{
+  tu_fifo_t ff10;
+  uint8_t buf[10];
+  uint8_t dst[10];
+
+  tu_fifo_config(&ff10, buf, 10, 1, 1);
+
+  uint16_t n;
+
+  ff10.wr_idx = 6;
+  ff10.rd_idx = 15;
+
+  n = tu_fifo_read_n(&ff10, dst, 4);
+  TEST_ASSERT_EQUAL(n, 4);
+  TEST_ASSERT_EQUAL(ff10.rd_idx, 0);
+  n = tu_fifo_read_n(&ff10, dst, 4);
+  TEST_ASSERT_EQUAL(n, 4);
+  TEST_ASSERT_EQUAL(ff10.rd_idx, 4);
+  n = tu_fifo_read_n(&ff10, dst, 4);
+  TEST_ASSERT_EQUAL(n, 2);
+  TEST_ASSERT_EQUAL(ff10.rd_idx, 6);
+}
\ No newline at end of file

From 4ec96c02a6db596fc38edd937ca599a5a06a6aaa Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 29 Jun 2021 22:40:21 +0200
Subject: [PATCH 0139/2085] Fix audiod_get_AS_interface_index in audio class.
 Enhance uac2_headset example with multiple sample rates. Add macro to
 calculate EP size.

---
 examples/device/uac2_headset/src/main.c       | 69 ++++++++++++++-----
 .../device/uac2_headset/src/tusb_config.h     | 13 ++--
 .../device/uac2_headset/src/usb_descriptors.c |  2 +-
 .../device/uac2_headset/src/usb_descriptors.h |  8 +--
 src/class/audio/audio_device.c                | 16 +++--
 src/device/usbd.h                             |  5 ++
 6 files changed, 77 insertions(+), 36 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 1b6a770a3..e76b081c8 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -34,9 +34,11 @@
 // MACRO CONSTANT TYPEDEF PROTOTYPES
 //--------------------------------------------------------------------+
 
-#ifndef AUDIO_SAMPLE_RATE
-#define AUDIO_SAMPLE_RATE     48000
-#endif
+// List of supported sample rates
+const uint32_t sample_rates[]       = {44100, 48000, 88200, 96000};
+uint32_t       current_sample_rate  = 44100;
+
+#define N_SAMPLE_RATES  (sizeof(sample_rates) / 4)
 
 /* Blink pattern
  * - 25 ms   : streaming data
@@ -166,24 +168,30 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
 {
   TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
 
-  // Example supports only single frequency, same value will be used for current value and range
   if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
   {
     if (request->bRequest == AUDIO_CS_REQ_CUR)
     {
-      TU_LOG2("Clock get current freq %u\r\n", AUDIO_SAMPLE_RATE);
+      TU_LOG1("Clock get current freq %u\r\n", current_sample_rate);
 
-      audio_control_cur_4_t curf = { tu_htole32(AUDIO_SAMPLE_RATE) };
+      audio_control_cur_4_t curf = { tu_htole32(current_sample_rate) };
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
     }
     else if (request->bRequest == AUDIO_CS_REQ_RANGE)
     {
-      audio_control_range_4_n_t(1) rangef =
+      audio_control_range_4_n_t(N_SAMPLE_RATES) rangef =
       {
-        .wNumSubRanges = tu_htole16(1),
-        .subrange[0] = { tu_htole32(AUDIO_SAMPLE_RATE), tu_htole32(AUDIO_SAMPLE_RATE), 0}
+        .wNumSubRanges = tu_htole16(N_SAMPLE_RATES)
       };
-      TU_LOG2("Clock get freq range (%d, %d, %d)\r\n", (int)rangef.subrange[0].bMin, (int)rangef.subrange[0].bMax, (int)rangef.subrange[0].bRes);
+      TU_LOG1("Clock get %d freq ranges\r\n", N_SAMPLE_RATES);
+      for(uint8_t i = 0; i < N_SAMPLE_RATES; i++)
+      {
+        rangef.subrange[i].bMin = sample_rates[i];
+        rangef.subrange[i].bMax = sample_rates[i];
+        rangef.subrange[i].bRes = 0;
+        TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
+      }
+      
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef));
     }
   }
@@ -191,7 +199,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
            request->bRequest == AUDIO_CS_REQ_CUR)
   {
     audio_control_cur_1_t cur_valid = { .bCur = 1 };
-    TU_LOG2("Clock get is valid %u\r\n", cur_valid.bCur);
+    TU_LOG1("Clock get is valid %u\r\n", cur_valid.bCur);
     return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_valid, sizeof(cur_valid));
   }
   TU_LOG1("Clock get request not supported, entity = %u, selector = %u, request = %u\r\n",
@@ -199,6 +207,32 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
   return false;
 }
 
+// Helper for clock set requests
+static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+  (void)rhport;
+
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT);
+  TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+  if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_4_t));
+
+    current_sample_rate = ((audio_control_cur_4_t *)buf)->bCur;
+
+    TU_LOG1("Clock set current freq: %d\r\n", current_sample_rate);
+
+    return true;
+  }
+  else
+  {
+    TU_LOG1("Clock set request not supported, entity = %u, selector = %u, request = %u\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+    return false;
+  }
+}
+
 // Helper for feature unit get requests
 static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_request_t const *request)
 {
@@ -207,7 +241,7 @@ static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_req
   if (request->bControlSelector == AUDIO_FU_CTRL_MUTE && request->bRequest == AUDIO_CS_REQ_CUR)
   {
     audio_control_cur_1_t mute1 = { .bCur = mute[request->bChannelNumber] };
-    TU_LOG2("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
+    TU_LOG1("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
     return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &mute1, sizeof(mute1));
   }
   else if (UAC2_ENTITY_SPK_FEATURE_UNIT && request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
@@ -218,14 +252,14 @@ static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_req
         .wNumSubRanges = tu_htole16(1),
         .subrange[0] = { .bMin = tu_htole16(-VOLUME_CTRL_50_DB), tu_htole16(VOLUME_CTRL_0_DB), tu_htole16(256) }
       };
-      TU_LOG2("Get channel %u volume range (%d, %d, %u) dB\r\n", request->bChannelNumber,
+      TU_LOG1("Get channel %u volume range (%d, %d, %u) dB\r\n", request->bChannelNumber,
               range_vol.subrange[0].bMin / 256, range_vol.subrange[0].bMax / 256, range_vol.subrange[0].bRes / 256);
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &range_vol, sizeof(range_vol));
     }
     else if (request->bRequest == AUDIO_CS_REQ_CUR)
     {
       audio_control_cur_2_t cur_vol = { .bCur = tu_htole16(volume[request->bChannelNumber]) };
-      TU_LOG2("Get channel %u volume %u dB\r\n", request->bChannelNumber, cur_vol.bCur);
+      TU_LOG1("Get channel %u volume %d dB\r\n", request->bChannelNumber, cur_vol.bCur / 256);
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_vol, sizeof(cur_vol));
     }
   }
@@ -249,7 +283,7 @@ static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_req
 
     mute[request->bChannelNumber] = ((audio_control_cur_1_t *)buf)->bCur;
 
-    TU_LOG2("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]);
+    TU_LOG1("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]);
 
     return true;
   }
@@ -259,7 +293,7 @@ static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_req
 
     volume[request->bChannelNumber] = ((audio_control_cur_2_t const *)buf)->bCur;
 
-    TU_LOG2("Set channel %d volume: %d dB\r\n", request->bChannelNumber, volume[request->bChannelNumber] / 256);
+    TU_LOG1("Set channel %d volume: %d dB\r\n", request->bChannelNumber, volume[request->bChannelNumber] / 256);
 
     return true;
   }
@@ -299,7 +333,8 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p
 
   if (request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT)
     return tud_audio_feature_unit_set_request(rhport, request, buf);
-
+  if (request->bEntityID == UAC2_ENTITY_CLOCK)
+    return tud_audio_clock_set_request(rhport, request, buf);
   TU_LOG1("Set request not handled, entity = %d, selector = %d, request = %d\r\n",
           request->bEntityID, request->bControlSelector, request->bRequest);
 
diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index 88f9efcff..9b7ed337c 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -93,13 +93,12 @@ extern "C" {
 //--------------------------------------------------------------------
 // AUDIO CLASS DRIVER CONFIGURATION
 //--------------------------------------------------------------------
-#define CFG_TUD_AUDIO_IN_PATH                     (CFG_TUD_AUDIO)
-#define CFG_TUD_AUDIO_OUT_PATH                    (CFG_TUD_AUDIO)
 
 //#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                       220       // This equals TUD_AUDIO_HEADSET_STEREO_DESC_LEN, however, including it from usb_descriptors.h is not possible due to some strange include hassle
 #define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                       TUD_AUDIO_HEADSET_STEREO_DESC_LEN
 
 // Audio format type I specifications
+#define CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE              96000
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                  1
 #define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX          2
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                  2
@@ -108,18 +107,18 @@ extern "C" {
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
 #define CFG_TUD_AUDIO_ENABLE_EP_IN                1
-#define CFG_TUD_AUDIO_EP_SZ_IN                    (CFG_TUD_AUDIO_IN_PATH * (48 + 1) * (CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX) * (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)) // 48 Samples (48 kHz) x 2 Bytes/Sample x n Channels
+#define CFG_TUD_AUDIO_EP_SZ_IN                    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX) // 48 Samples (48 kHz) x 2 Bytes/Sample x n Channels
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      CFG_TUD_AUDIO_EP_SZ_IN
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         CFG_TUD_AUDIO_EP_SZ_IN                  // Maximum EP IN size for all AS alternate settings used
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
 #define CFG_TUD_AUDIO_ENABLE_EP_OUT               1
-#define CFG_TUD_AUDIO_EP_OUT_SZ                   (CFG_TUD_AUDIO_OUT_PATH * ((48 + CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP) * (CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX) * (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX))) // N Samples (N kHz) x 2 Bytes/Sample x n Channels
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     CFG_TUD_AUDIO_EP_OUT_SZ*3
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        CFG_TUD_AUDIO_EP_OUT_SZ                 // Maximum EP IN size for all AS alternate settings used
+#define CFG_TUD_AUDIO_EP_SZ_OUT                   TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX) // N Samples (N kHz) x 2 Bytes/Sample x n Channels
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     CFG_TUD_AUDIO_EP_SZ_OUT*3
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        CFG_TUD_AUDIO_EP_SZ_OUT                 // Maximum EP IN size for all AS alternate settings used
 
 // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
-#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 	          1
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 	          2
 
 // Size of control request buffer
 #define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ	64
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index cd749eb65..f5d8e461b 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -93,7 +93,7 @@ uint8_t const desc_configuration[] =
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
-    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, 2, 16, EPNUM_AUDIO, CFG_TUD_AUDIO_EP_OUT_SZ, EPNUM_AUDIO | 0x80, CFG_TUD_AUDIO_EP_SZ_IN)
+    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, 2, 16, EPNUM_AUDIO, CFG_TUD_AUDIO_EP_SZ_OUT, EPNUM_AUDIO | 0x80, CFG_TUD_AUDIO_EP_SZ_IN)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index d9c5a63a7..1595d9c5d 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -77,7 +77,7 @@ enum
     /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
     TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_HEADSET, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
     /* Clock Source Descriptor(4.7.2.1) */\
-    TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ UAC2_ENTITY_CLOCK, /*_attr*/ 3, /*_ctrl*/ 5, /*_assocTerm*/ 0x00,  /*_stridx*/ 0x00),    \
+    TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ UAC2_ENTITY_CLOCK, /*_attr*/ 3, /*_ctrl*/ 7, /*_assocTerm*/ 0x00,  /*_stridx*/ 0x00),    \
     /* Input Terminal Descriptor(4.7.2.4) */\
     TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
     /* Feature Unit Descriptor(4.7.2.8) */\
@@ -99,21 +99,21 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Standard AS Interface Descriptor(4.9.1) */\
     /* Interface 2, Alternate 0 - default alternate setting with 0 bandwidth */\
     TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x04),\
     /* Standard AS Interface Descriptor(4.9.1) */\
-    /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+    /* Interface 2, Alternate 1 - alternate interface for data streaming */\
     TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
     /* Class-Specific AS Interface Descriptor(4.9.2) */\
     TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epinsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epinsize, /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)\
 
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 7263958df..cb35adb82 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1997,15 +1997,17 @@ static bool audiod_get_AS_interface_index(uint8_t itf, audiod_function_t * audio
     while (p_desc < p_desc_end)
     {
       // We assume the number of alternate settings is increasing thus we return the index of alternate setting zero!
-      if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf)
+      if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == 0)
       {
-        *idxItf = tmp;
-        *pp_desc_int = p_desc;
-        return true;
+        if (((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf)
+        {
+          *idxItf = tmp;
+          *pp_desc_int = p_desc;
+          return true;
+        }
+        // Increase index, bytes read, and pointer
+        tmp++;
       }
-
-      // Increase index, bytes read, and pointer
-      tmp++;
       p_desc = tu_desc_next(p_desc);
     }
   }
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 3857295d7..45aefe53b 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -542,6 +542,11 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
   TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_interval*/ 1)\
 
+//   Calculate wMaxPacketSize of Endpoints
+#define TUD_AUDIO_EP_SIZE(_maxFrequency, _nBytesPerSample, _nChannels) \
+    ((((_maxFrequency + ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 7999 : 999)) / ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels)
+
+
 //------------- TUD_USBTMC/USB488 -------------//
 #define TUD_USBTMC_APP_CLASS    (TUSB_CLASS_APPLICATION_SPECIFIC)
 #define TUD_USBTMC_APP_SUBCLASS 0x03u

From 9b93145a795d6a4094521c52d77892c737f8bc83 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 30 Jun 2021 19:04:04 +0200
Subject: [PATCH 0140/2085] Fix typo

---
 examples/device/uac2_headset/src/main.c            | 2 +-
 examples/device/uac2_headset/src/usb_descriptors.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index e76b081c8..e119ee2c8 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -212,7 +212,7 @@ static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t
 {
   (void)rhport;
 
-  TU_ASSERT(request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT);
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
   TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
 
   if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 1595d9c5d..8ce3b26e0 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -99,7 +99,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Standard AS Interface Descriptor(4.9.1) */\
@@ -113,7 +113,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epinsize, /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epinsize, /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)\
 

From f7519d805e7e0afb07ba27e1831426abd9f91fb2 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 00:26:24 +0200
Subject: [PATCH 0141/2085] Refactor descriptor, add alt settings support.

---
 .../device/uac2_headset/src/tusb_config.h     | 42 ++++++++++------
 .../device/uac2_headset/src/usb_descriptors.c |  2 +-
 .../device/uac2_headset/src/usb_descriptors.h | 49 +++++++++++++++----
 3 files changed, 68 insertions(+), 25 deletions(-)

diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index 9b7ed337c..e97f4c470 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -94,28 +94,42 @@ extern "C" {
 // AUDIO CLASS DRIVER CONFIGURATION
 //--------------------------------------------------------------------
 
-//#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                       220       // This equals TUD_AUDIO_HEADSET_STEREO_DESC_LEN, however, including it from usb_descriptors.h is not possible due to some strange include hassle
-#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                       TUD_AUDIO_HEADSET_STEREO_DESC_LEN
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                TUD_AUDIO_HEADSET_STEREO_DESC_LEN
 
 // Audio format type I specifications
-#define CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE              96000
-#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                  1
-#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX          2
-#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                  2
-#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX          2
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP                    0
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000     // 24bit/96kHz is the best quality for full-speed, high-speed is needed beyond this
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                           1
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                           2
+
+// 16bit in 16bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX          2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX                  16
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX          2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX                  16
+
+// 24bit in 32bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX          4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX                  24
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX          4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX                  24
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
 #define CFG_TUD_AUDIO_ENABLE_EP_IN                1
-#define CFG_TUD_AUDIO_EP_SZ_IN                    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX) // 48 Samples (48 kHz) x 2 Bytes/Sample x n Channels
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      CFG_TUD_AUDIO_EP_SZ_IN
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         CFG_TUD_AUDIO_EP_SZ_IN                  // Maximum EP IN size for all AS alternate settings used
+
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN) // Maximum EP IN size for all AS alternate settings used
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
 #define CFG_TUD_AUDIO_ENABLE_EP_OUT               1
-#define CFG_TUD_AUDIO_EP_SZ_OUT                   TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX) // N Samples (N kHz) x 2 Bytes/Sample x n Channels
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     CFG_TUD_AUDIO_EP_SZ_OUT*3
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        CFG_TUD_AUDIO_EP_SZ_OUT                 // Maximum EP IN size for all AS alternate settings used
+
+#define CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+#define CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT)*3
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT) // Maximum EP IN size for all AS alternate settings used
 
 // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
 #define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 	          2
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index f5d8e461b..6a01f8938 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -93,7 +93,7 @@ uint8_t const desc_configuration[] =
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
-    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, 2, 16, EPNUM_AUDIO, CFG_TUD_AUDIO_EP_SZ_OUT, EPNUM_AUDIO | 0x80, CFG_TUD_AUDIO_EP_SZ_IN)
+    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO, EPNUM_AUDIO | 0x80)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 8ce3b26e0..4fae25831 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -62,14 +62,23 @@ enum
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
 
-
-#define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epoutsize, _epin, _epinsize) \
+#define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin) \
     /* Standard Interface Association Descriptor (IAD) */\
     TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ ITF_NUM_TOTAL, /*_stridx*/ 0x00),\
     /* Standard AC Interface Descriptor(4.7.1) */\
@@ -83,7 +92,7 @@ enum
     /* Feature Unit Descriptor(4.7.2.8) */\
     TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL(/*_unitid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_srcid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrlch0master*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch1*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch2*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_stridx*/ 0x00),\
     /* Output Terminal Descriptor(4.7.2.5) */\
-    TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_OUT_GENERIC_SPEAKER, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+    TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_OUT_HEADPHONES, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
     /* Input Terminal Descriptor(4.7.2.4) */\
     TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_MIC_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
     /* Output Terminal Descriptor(4.7.2.5) */\
@@ -95,11 +104,21 @@ enum
     /* Interface 1, Alternate 1 - alternate interface for data streaming */\
     TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x05),\
     /* Class-Specific AS Interface Descriptor(4.9.2) */\
-    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
-    TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
+    /* Interface 1, Alternate 2 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x05),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Standard AS Interface Descriptor(4.9.1) */\
@@ -109,12 +128,22 @@ enum
     /* Interface 2, Alternate 1 - alternate interface for data streaming */\
     TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
     /* Class-Specific AS Interface Descriptor(4.9.2) */\
-    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
-    TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epinsize, /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
-    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
+    /* Interface 2, Alternate 2 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
 #endif

From 6e1f812e3542f6d9047a3b8148f2f073ba38b91f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jul 2021 14:09:17 +0700
Subject: [PATCH 0142/2085] skip uac2_headset for mcu that does not have enough
 sram

---
 examples/device/uac2_headset/.skip.MCU_LPC11UXX   | 0
 examples/device/uac2_headset/.skip.MCU_LPC13XX    | 0
 examples/device/uac2_headset/.skip.MCU_MSP430x5xx | 0
 examples/device/uac2_headset/.skip.MCU_NUC121     | 0
 examples/device/uac2_headset/.skip.MCU_STM32L0    | 0
 5 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 examples/device/uac2_headset/.skip.MCU_LPC11UXX
 create mode 100644 examples/device/uac2_headset/.skip.MCU_LPC13XX
 create mode 100644 examples/device/uac2_headset/.skip.MCU_MSP430x5xx
 create mode 100644 examples/device/uac2_headset/.skip.MCU_NUC121
 create mode 100644 examples/device/uac2_headset/.skip.MCU_STM32L0

diff --git a/examples/device/uac2_headset/.skip.MCU_LPC11UXX b/examples/device/uac2_headset/.skip.MCU_LPC11UXX
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/uac2_headset/.skip.MCU_LPC13XX b/examples/device/uac2_headset/.skip.MCU_LPC13XX
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/uac2_headset/.skip.MCU_MSP430x5xx b/examples/device/uac2_headset/.skip.MCU_MSP430x5xx
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/uac2_headset/.skip.MCU_NUC121 b/examples/device/uac2_headset/.skip.MCU_NUC121
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/uac2_headset/.skip.MCU_STM32L0 b/examples/device/uac2_headset/.skip.MCU_STM32L0
new file mode 100644
index 000000000..e69de29bb

From ee6cf744ebf4154785203d5a2e11fe6b030964d2 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 11:38:06 +0200
Subject: [PATCH 0143/2085] audio_device : clear fifo on intf change.

---
 src/class/audio/audio_device.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index cb35adb82..230b689cd 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1481,6 +1481,9 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     audio->ep_in_as_intf_num = 0;
     usbd_edpt_close(rhport, audio->ep_in);
 
+    // Clear FIFOs, since data is no longer valid
+    tu_fifo_clear(&audio->ep_in_ff);
+    
     // Invoke callback - can be used to stop data sampling
     if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
 
@@ -1502,6 +1505,13 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   {
     audio->ep_out_as_intf_num = 0;
     usbd_edpt_close(rhport, audio->ep_out);
+
+    // Clear FIFOs, since data is no longer valid
+    tu_fifo_clear(&audio->ep_out_ff);
+
+    // Invoke callback - can be used to stop data sampling
+    if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
+
     audio->ep_out = 0;                          // Necessary?
 
     // Clear support FIFOs if used

From e0a7752fc35e4b613427ebda80553a5392e618be Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 11:39:15 +0200
Subject: [PATCH 0144/2085] Add 24bit loopback in example.

---
 examples/device/uac2_headset/src/main.c       | 58 ++++++++++++++-----
 .../device/uac2_headset/src/tusb_config.h     |  3 +
 .../device/uac2_headset/src/usb_descriptors.h |  6 ++
 3 files changed, 54 insertions(+), 13 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index e119ee2c8..c9e79a543 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -38,7 +38,7 @@
 const uint32_t sample_rates[]       = {44100, 48000, 88200, 96000};
 uint32_t       current_sample_rate  = 44100;
 
-#define N_SAMPLE_RATES  (sizeof(sample_rates) / 4)
+#define N_SAMPLE_RATES  TU_ARRAY_SIZE(sample_rates)
 
 /* Blink pattern
  * - 25 ms   : streaming data
@@ -78,11 +78,16 @@ int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];       // +1 for master chan
 int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];    // +1 for master channel 0
 
 // Buffer for microphone data
-int16_t mic_buf[1000];
+uint8_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
 // Buffer for speaker data
-int16_t spk_buf[1000];
+uint8_t spk_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
 // Speaker data size received in the last frame
 int spk_data_size;
+// Resolution per format
+const uint8_t resolutions_per_format[CFG_TUD_AUDIO_FUNC_1_N_FORMATS] = {CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX,
+                                                                        CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX};
+// Current resolution, update on format change
+uint8_t current_resolution;
 
 void led_blinking_task(void);
 void audio_task(void);
@@ -364,6 +369,13 @@ bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_reque
   if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt != 0)
       blink_interval_ms = BLINK_STREAMING;
 
+  // Clear buffer when streaming format is changed
+  spk_data_size = 0;
+  if(alt != 0)
+  {
+    current_resolution = resolutions_per_format[alt-1];
+  }
+
   return true;
 }
 
@@ -397,20 +409,40 @@ void audio_task(void)
 {
   // When new data arrived, copy data from speaker buffer, to microphone buffer
   // and send it over
+  // Only support speaker & headphone both have the same resolution
+  // If one is 16bit another is 24bit be care of LOUD noise !
   if (spk_data_size)
   {
-    int16_t *src = spk_buf;
-    int16_t *limit = spk_buf + spk_data_size / 2;
-    int16_t *dst = mic_buf;
-    while (src < limit)
+    if (current_resolution == 16)
     {
-      // Combine two channels into one
-      int32_t left = *src++;
-      int32_t right = *src++;
-      *dst++ = (int16_t)((left + right) / 2);
+      int16_t *src = (int16_t*)spk_buf;
+      int16_t *limit = (int16_t*)spk_buf + spk_data_size / 2;
+      int16_t *dst = (int16_t*)mic_buf;
+      while (src < limit)
+      {
+        // Combine two channels into one
+        int32_t left = *src++;
+        int32_t right = *src++;
+        *dst++ = (int16_t)((left + right) / 2);
+      }
+      tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
+      spk_data_size = 0;
+    }
+    else if (current_resolution == 24)
+    {
+      int32_t *src = (int32_t*)spk_buf;
+      int32_t *limit = (int32_t*)spk_buf + spk_data_size / 4;
+      int32_t *dst = (int32_t*)mic_buf;
+      while (src < limit)
+      {
+        // Combine two channels into one
+        int32_t left = (*src++);
+        int32_t right = (*src++);
+        *dst++ = (int32_t)((left + right) / 2) & 0xffffff00;
+      }
+      tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
+      spk_data_size = 0;
     }
-    tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
-    spk_data_size = 0;
   }
 }
 
diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index e97f4c470..642e52551 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -96,6 +96,9 @@ extern "C" {
 
 #define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                TUD_AUDIO_HEADSET_STEREO_DESC_LEN
 
+// How many formats are used, need to adjust USB descriptor if changed
+#define CFG_TUD_AUDIO_FUNC_1_N_FORMATS                               2
+
 // Audio format type I specifications
 #define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000     // 24bit/96kHz is the best quality for full-speed, high-speed is needed beyond this
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                           1
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 4fae25831..d9510ea4f 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -55,23 +55,29 @@ enum
     + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
     + TUD_AUDIO_DESC_INPUT_TERM_LEN\
     + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    /* Interface 1, Alternate 0 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 1, Alternate 2 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 2, Alternate 0 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    /* Interface 2, Alternate 1 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 2, Alternate 2 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\

From 0e7abfcf172671a32e848ec4b30318e7093cfc60 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 11:45:39 +0200
Subject: [PATCH 0145/2085] Clear FIFO only if enabled... Add buffer align

---
 examples/device/uac2_headset/src/main.c        | 14 +++++++-------
 examples/device/uac2_headset/src/tusb_config.h |  4 ++--
 src/class/audio/audio_device.c                 |  4 ++++
 3 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index c9e79a543..f7d20a607 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -78,9 +78,9 @@ int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];       // +1 for master chan
 int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];    // +1 for master channel 0
 
 // Buffer for microphone data
-uint8_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+int32_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ / 4];
 // Buffer for speaker data
-uint8_t spk_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+int32_t spk_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ / 4];
 // Speaker data size received in the last frame
 int spk_data_size;
 // Resolution per format
@@ -430,14 +430,14 @@ void audio_task(void)
     }
     else if (current_resolution == 24)
     {
-      int32_t *src = (int32_t*)spk_buf;
-      int32_t *limit = (int32_t*)spk_buf + spk_data_size / 4;
-      int32_t *dst = (int32_t*)mic_buf;
+      int32_t *src = spk_buf;
+      int32_t *limit = spk_buf + spk_data_size / 4;
+      int32_t *dst = mic_buf;
       while (src < limit)
       {
         // Combine two channels into one
-        int32_t left = (*src++);
-        int32_t right = (*src++);
+        int32_t left = *src++;
+        int32_t right = *src++;
         *dst++ = (int32_t)((left + right) / 2) & 0xffffff00;
       }
       tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index 642e52551..d955a746d 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -122,7 +122,7 @@ extern "C" {
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
 
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN)*2
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN) // Maximum EP IN size for all AS alternate settings used
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
@@ -131,7 +131,7 @@ extern "C" {
 #define CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
 #define CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
 
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT)*3
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT)*2
 #define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT) // Maximum EP IN size for all AS alternate settings used
 
 // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 230b689cd..3e05b3763 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1481,8 +1481,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     audio->ep_in_as_intf_num = 0;
     usbd_edpt_close(rhport, audio->ep_in);
 
+#if !CFG_TUD_AUDIO_ENABLE_ENCODING
     // Clear FIFOs, since data is no longer valid
     tu_fifo_clear(&audio->ep_in_ff);
+#endif
     
     // Invoke callback - can be used to stop data sampling
     if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
@@ -1506,8 +1508,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     audio->ep_out_as_intf_num = 0;
     usbd_edpt_close(rhport, audio->ep_out);
 
+#if !CFG_TUD_AUDIO_ENABLE_ENCODING
     // Clear FIFOs, since data is no longer valid
     tu_fifo_clear(&audio->ep_out_ff);
+#endif
 
     // Invoke callback - can be used to stop data sampling
     if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));

From 8571508b3f2692fc9f40102052e81ab3f1c6d08f Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 12:59:26 +0200
Subject: [PATCH 0146/2085] Partially revert "skip uac2_headset for mcu that
 does not have enough sram"

This reverts commit 6e1f812e3542f6d9047a3b8148f2f073ba38b91f.
---
 examples/device/uac2_headset/.skip.MCU_LPC11UXX   | 0
 examples/device/uac2_headset/.skip.MCU_LPC13XX    | 0
 examples/device/uac2_headset/.skip.MCU_MSP430x5xx | 0
 examples/device/uac2_headset/.skip.MCU_STM32L0    | 0
 4 files changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_LPC11UXX
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_LPC13XX
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_MSP430x5xx
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_STM32L0

diff --git a/examples/device/uac2_headset/.skip.MCU_LPC11UXX b/examples/device/uac2_headset/.skip.MCU_LPC11UXX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_LPC13XX b/examples/device/uac2_headset/.skip.MCU_LPC13XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_MSP430x5xx b/examples/device/uac2_headset/.skip.MCU_MSP430x5xx
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_STM32L0 b/examples/device/uac2_headset/.skip.MCU_STM32L0
deleted file mode 100644
index e69de29bb..000000000

From ca98996e1f9ac802c60d9da4c28ab0e16ca640d6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jul 2021 22:46:39 +0700
Subject: [PATCH 0147/2085] better support for hid device set/get protocol

add caplock detection for hid_composite
---
 examples/device/hid_composite/src/main.c | 31 +++++++++++--
 hw/bsp/board.c                           | 58 ++++++++++++++++++++++--
 hw/bsp/board.h                           |  9 +++-
 src/class/hid/hid_device.c               | 28 +++++++++++-
 src/device/usbd.c                        |  2 +-
 src/device/usbd_control.c                |  1 +
 6 files changed, 115 insertions(+), 14 deletions(-)

diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 512f6f9d9..6ddad5aae 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -255,12 +255,30 @@ uint16_t tud_hid_get_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t
 // received data on OUT endpoint ( Report ID = 0, Type = 0 )
 void tud_hid_set_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize)
 {
-  // TODO set LED based on CAPLOCK, NUMLOCK etc...
   (void) itf;
-  (void) report_id;
-  (void) report_type;
-  (void) buffer;
-  (void) bufsize;
+
+  if (report_type == HID_REPORT_TYPE_OUTPUT)
+  {
+    // Set keyboard LED e.g Capslock, Numlock etc...
+    if (report_id == REPORT_ID_KEYBOARD)
+    {
+      // bufsize should be (at least) 1
+      if ( bufsize < 1 ) return;
+
+      uint8_t const kbd_leds = buffer[0];
+
+      if (kbd_leds & KEYBOARD_LED_CAPSLOCK)
+      {
+        // Capslock On: disable blink, turn led on
+        blink_interval_ms = 0;
+        board_led_write(true);
+      }else
+      {
+        // Caplocks Off: back to normal link
+        blink_interval_ms = BLINK_MOUNTED;
+      }
+    }
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -271,6 +289,9 @@ void led_blinking_task(void)
   static uint32_t start_ms = 0;
   static bool led_state = false;
 
+  // blink is disabled
+  if (!blink_interval_ms) return;
+
   // Blink every interval ms
   if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
   start_ms += blink_interval_ms;
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 383a02ef4..c21c9e976 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -25,6 +25,60 @@
 
 #include "board.h"
 
+#if 0
+#define LED_PHASE_MAX   8
+
+static struct
+{
+  uint32_t phase[LED_PHASE_MAX];
+  uint8_t phase_count;
+
+  bool led_state;
+  uint8_t current_phase;
+  uint32_t current_ms;
+}led_pattern;
+
+void board_led_pattern(uint32_t const phase_ms[], uint8_t count)
+{
+  memcpy(led_pattern.phase, phase_ms, 4*count);
+  led_pattern.phase_count = count;
+
+  // reset with 1st phase is on
+  led_pattern.current_ms = board_millis();
+  led_pattern.current_phase = 0;
+  led_pattern.led_state = true;
+  board_led_on();
+}
+
+void board_led_task(void)
+{
+  if ( led_pattern.phase_count == 0 ) return;
+
+  uint32_t const duration = led_pattern.phase[led_pattern.current_phase];
+
+  // return if not enough time
+  if (board_millis() - led_pattern.current_ms < duration) return;
+
+  led_pattern.led_state = !led_pattern.led_state;
+  board_led_write(led_pattern.led_state);
+
+  led_pattern.current_ms += duration;
+  led_pattern.current_phase++;
+
+  if (led_pattern.current_phase == led_pattern.phase_count)
+  {
+    led_pattern.current_phase = 0;
+    led_pattern.led_state = true;
+    board_led_on();
+  }
+}
+
+#endif
+
+//--------------------------------------------------------------------+
+// newlib read()/write() retarget
+//--------------------------------------------------------------------+
+
 #if defined(__MSP430__)
   #define sys_write   write
   #define sys_read    read
@@ -33,10 +87,6 @@
   #define sys_read    _read
 #endif
 
-//--------------------------------------------------------------------+
-// newlib read()/write() retarget
-//--------------------------------------------------------------------+
-
 #if defined(LOGGER_RTT)
 // Logging with RTT
 
diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index 7b77def50..782e0939c 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -54,6 +54,10 @@ void board_init(void);
 // Turn LED on or off
 void board_led_write(bool state);
 
+// Control led pattern using phase duration in ms.
+// For each phase, LED is toggle then repeated, board_led_task() is required to be called
+//void board_led_pattern(uint32_t const phase_ms[], uint8_t count);
+
 // Get the current state of button
 // a '1' means active (pressed), a '0' means inactive.
 uint32_t board_button_read(void);
@@ -81,11 +85,12 @@ int board_uart_write(void const * buf, int len);
   }
 
 #elif CFG_TUSB_OS == OPT_OS_PICO
-#include "pico/time.h"
-static inline uint32_t board_millis(void)
+  #include "pico/time.h"
+  static inline uint32_t board_millis(void)
   {
     return to_ms_since_boot(get_absolute_time());
   }
+
 #elif CFG_TUSB_OS == OPT_OS_RTTHREAD
   static inline uint32_t board_millis(void)
   {
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index e44f282c4..65c7d1a18 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -280,7 +280,21 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
           uint8_t const report_type = tu_u16_high(request->wValue);
           uint8_t const report_id   = tu_u16_low(request->wValue);
 
-          uint16_t xferlen = tud_hid_get_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, p_hid->epin_buf, request->wLength);
+          uint8_t* report_buf = p_hid->epin_buf;
+          uint16_t req_len = request->wLength;
+
+          uint16_t xferlen = 0;
+
+          // If host request a specific Report ID, add ID to as 1 byte of response
+          if ( (report_id != HID_REPORT_TYPE_INVALID) && (req_len > 1) )
+          {
+            *report_buf++ = report_id;
+            req_len--;
+
+            xferlen++;
+          }
+
+          xferlen += tud_hid_get_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, report_buf, req_len);
           TU_ASSERT( xferlen > 0 );
 
           tud_control_xfer(rhport, request, p_hid->epin_buf, xferlen);
@@ -298,7 +312,17 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
           uint8_t const report_type = tu_u16_high(request->wValue);
           uint8_t const report_id   = tu_u16_low(request->wValue);
 
-          tud_hid_set_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, p_hid->epout_buf, request->wLength);
+          uint8_t const* report_buf = p_hid->epout_buf;
+          uint16_t report_len = request->wLength;
+
+          // If host request a specific Report ID, extract report ID in buffer before invoking callback
+          if ( (report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == p_hid->epout_buf[0]) )
+          {
+            report_buf++;
+            report_len--;
+          }
+
+          tud_hid_set_report_cb(hid_itf, report_id, (hid_report_type_t) report_type, report_buf, report_len);
         }
       break;
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 587d487dc..af4fd58c4 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1243,7 +1243,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
+  TU_LOG2("  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 724c652e6..7a8244699 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -186,6 +186,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
   {
     TU_VERIFY(_ctrl_xfer.buffer);
     memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes);
+    TU_LOG_MEM(2, _usbd_ctrl_buf, xferred_bytes, 2);
   }
 
   _ctrl_xfer.total_xferred += xferred_bytes;

From 6de023d54b944bb467327062e79f3854e79b71a2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jul 2021 22:54:57 +0700
Subject: [PATCH 0148/2085] update hid_composite freertos with capslock as well

---
 examples/device/hid_composite/src/main.c      |  3 +-
 .../device/hid_composite_freertos/src/main.c  | 29 +++++++++++++++----
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 6ddad5aae..d2a8a28fa 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -274,7 +274,8 @@ void tud_hid_set_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t rep
         board_led_write(true);
       }else
       {
-        // Caplocks Off: back to normal link
+        // Caplocks Off: back to normal blink
+        board_led_write(false);
         blink_interval_ms = BLINK_MOUNTED;
       }
     }
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 47f976427..a61710858 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -315,12 +315,31 @@ uint16_t tud_hid_get_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t
 // received data on OUT endpoint ( Report ID = 0, Type = 0 )
 void tud_hid_set_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize)
 {
-  // TODO set LED based on CAPLOCK, NUMLOCK etc...
   (void) itf;
-  (void) report_id;
-  (void) report_type;
-  (void) buffer;
-  (void) bufsize;
+
+  if (report_type == HID_REPORT_TYPE_OUTPUT)
+  {
+    // Set keyboard LED e.g Capslock, Numlock etc...
+    if (report_id == REPORT_ID_KEYBOARD)
+    {
+      // bufsize should be (at least) 1
+      if ( bufsize < 1 ) return;
+
+      uint8_t const kbd_leds = buffer[0];
+
+      if (kbd_leds & KEYBOARD_LED_CAPSLOCK)
+      {
+        // Capslock On: disable blink, turn led on
+        xTimerStop(blinky_tm, portMAX_DELAY);
+        board_led_write(true);
+      }else
+      {
+        // Caplocks Off: back to normal blink
+        board_led_write(false);
+        xTimerStart(blinky_tm, portMAX_DELAY);
+      }
+    }
+  }
 }
 
 //--------------------------------------------------------------------+

From 2b3d547b7bccf46c6a274c75cb1769532611c5bf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jul 2021 23:05:21 +0700
Subject: [PATCH 0149/2085] clean up

---
 src/class/hid/hid_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 65c7d1a18..a10e3a5e3 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -316,7 +316,7 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
           uint16_t report_len = request->wLength;
 
           // If host request a specific Report ID, extract report ID in buffer before invoking callback
-          if ( (report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == p_hid->epout_buf[0]) )
+          if ( (report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == report_buf[0]) )
           {
             report_buf++;
             report_len--;

From eb02b406d855c83394465946b8a691a2c81248ce Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 21:41:19 +0200
Subject: [PATCH 0150/2085] Prevent overflow noise

---
 examples/device/uac2_headset/src/main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index f7d20a607..b459bc2a8 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -423,7 +423,7 @@ void audio_task(void)
         // Combine two channels into one
         int32_t left = *src++;
         int32_t right = *src++;
-        *dst++ = (int16_t)((left + right) / 2);
+        *dst++ = (left >> 1) + (right >> 1);
       }
       tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
       spk_data_size = 0;
@@ -438,7 +438,7 @@ void audio_task(void)
         // Combine two channels into one
         int32_t left = *src++;
         int32_t right = *src++;
-        *dst++ = (int32_t)((left + right) / 2) & 0xffffff00;
+        *dst++ = ((left >> 1) + (right >> 1)) & 0xffffff00;
       }
       tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
       spk_data_size = 0;

From ea9ec1fb43eec29c00611335ea1c0585074f2b1b Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 1 Jul 2021 00:19:03 +0900
Subject: [PATCH 0151/2085] extend stack areas to enable logging add dummy
 functions to avoid warnings when logging is enable remove codes regarding
 OPTLIB

---
 hw/bsp/board.c                               |  2 +-
 hw/bsp/rx/boards/gr_citrus/gr_citrus.c       | 48 ++++++++++++++------
 hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld      |  4 +-
 hw/bsp/rx/boards/rx65n_target/r5f565ne.ld    |  4 +-
 hw/bsp/rx/boards/rx65n_target/rx65n_target.c | 29 ++++++++++--
 hw/bsp/rx/family.mk                          | 20 +-------
 6 files changed, 64 insertions(+), 43 deletions(-)

diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 383a02ef4..9dae8a04d 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -25,7 +25,7 @@
 
 #include "board.h"
 
-#if defined(__MSP430__)
+#if defined(__MSP430__) || defined(__RX__)
   #define sys_write   write
   #define sys_read    read
 #else
diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
index b773e0dd0..caf5fd6fa 100644
--- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
+++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
@@ -36,24 +36,20 @@
  * 
  * Connect the pins between GR-CITRUS and JLink as follows.
  * 
- * | JTAG Function | GR-CITRUS pin name| JLink pin No.| note     |
- * |:-------------:|:-----------------:|:------------:|:--------:|
- * | VTref         |   3.3V            |   1          |          |
- * | TRST          |   5               |   3          |          |
- * | GND           |   GND             |   4          |          |
- * | TDI           |   3               |   5          |          |
- * | TMS           |   2               |   7          |          |
- * | TCK           |   14              |   9          | short J4 |
- * | TDO           |   9               |  13          | short J5 |
- * | nRES          |   RST             |  15          |          |
+ * | Function  | GR-CITRUS pin | JLink pin No.| note     |
+ * |:---------:|:-------------:|:------------:|:--------:|
+ * | VTref     |   3.3V        |   1          |          |
+ * | TRST      |   5           |   3          |          |
+ * | GND       |   GND         |   4          |          |
+ * | TDI       |   3           |   5          |          |
+ * | TMS       |   2           |   7          |          |
+ * | TCK/FINEC |   14          |   9          | short J4 |
+ * | TDO       |   9           |  13          | short J5 |
+ * | nRES      |   RST         |  15          |          |
  *
  * JLink firmware needs to update to V6.96 or newer version to avoid
  * [a bug](https://forum.segger.com/index.php/Thread/7758-SOLVED-Bug-in-JLink-from-V6-88b-regarding-RX65N)
  * regarding downloading.
- *
- * When using SEGGER RTT, `RX_NEWLIB=0` should be added to make command arguments.
- * The option is used to change the C runtime library to `optlib` from `newlib`.
- * RTT may not work with `newlib`.
  */
 
 #include "../board.h"
@@ -253,3 +249,27 @@ uint32_t board_millis(void)
 #else
 uint32_t SystemCoreClock = 96000000;
 #endif
+
+int close(int fd)
+{
+    (void)fd;
+    return -1;
+}
+int fstat(int fd, void *pstat)
+{
+    (void)fd;
+    (void)pstat;
+    return 0;
+}
+off_t lseek(int fd, off_t pos, int whence)
+{
+    (void)fd;
+    (void)pos;
+    (void)whence;
+    return 0;
+}
+int isatty(int fd)
+{
+    (void)fd;
+    return 1;
+}
diff --git a/hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld b/hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld
index fa8142936..bb9c297c7 100644
--- a/hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld
+++ b/hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld
@@ -1,5 +1,5 @@
-__USTACK_SIZE = 0x00000200;
-__ISTACK_SIZE = 0x00000200;
+__USTACK_SIZE = 0x00000400;
+__ISTACK_SIZE = 0x00000400;
 
 MEMORY
 {
diff --git a/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld b/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld
index a02f0c02f..8e5617f23 100644
--- a/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld
+++ b/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld
@@ -1,5 +1,5 @@
-__USTACK_SIZE = 0x00000200;
-__ISTACK_SIZE = 0x00000200;
+__USTACK_SIZE = 0x00000400;
+__ISTACK_SIZE = 0x00000400;
 
 MEMORY
 {
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index 96d8f36f0..20867455e 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -48,11 +48,6 @@
  * JLink firmware needs to update to V6.96 or newer version to avoid
  * [a bug](https://forum.segger.com/index.php/Thread/7758-SOLVED-Bug-in-JLink-from-V6-88b-regarding-RX65N)
  * regarding downloading.
- *
- * When using SEGGER RTT, `RX_NEWLIB=0` should be added to make command arguments.
- * The option is used to change the C runtime library to `optlib` from `newlib`.
- * RTT may not work with `newlib`.
- *
  */
 
 #include "bsp/board.h"
@@ -299,3 +294,27 @@ uint32_t board_millis(void)
 #else
 uint32_t SystemCoreClock = 120000000;
 #endif
+
+int close(int fd)
+{
+    (void)fd;
+    return -1;
+}
+int fstat(int fd, void *pstat)
+{
+    (void)fd;
+    (void)pstat;
+    return 0;
+}
+off_t lseek(int fd, off_t pos, int whence)
+{
+    (void)fd;
+    (void)pos;
+    (void)whence;
+    return 0;
+}
+int isatty(int fd)
+{
+    (void)fd;
+    return 1;
+}
diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk
index 7d7585b4a..5a8281718 100644
--- a/hw/bsp/rx/family.mk
+++ b/hw/bsp/rx/family.mk
@@ -11,25 +11,7 @@ CFLAGS += \
   -fdata-sections \
   -fshort-enums \
   -mlittle-endian-data \
-
-RX_NEWLIB ?= 1
-
-ifeq ($(CMDEXE),1)
-  OPTLIBINC="$(shell for /F "usebackq delims=" %%i in (`where rx-elf-gcc`) do echo %%~dpi..\rx-elf\optlibinc)"
-else
-  OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
-endif
-
-ifeq ($(RX_NEWLIB),1)
-  CFLAGS += -DSSIZE_MAX=__INT_MAX__
-else
-  # setup for optlib
-  CFLAGS += -nostdinc \
-    -isystem $(OPTLIBINC) \
-    -DLWIP_NO_INTTYPES_H
-
-  LIBS += -loptc -loptm
-endif
+  -DSSIZE_MAX=__INT_MAX__
 
 SRC_C += \
 	src/portable/renesas/usba/dcd_usba.c \

From 01fe67be2db3d4c82b05c2aa848100f68c21f84e Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 2 Jul 2021 21:51:54 +0200
Subject: [PATCH 0152/2085] more uac fixes,

---
 src/class/audio/audio.h        |  2 +-
 src/class/audio/audio_device.c | 50 +++++++++++++++++-----------------
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h
index 936f09104..238295d25 100644
--- a/src/class/audio/audio.h
+++ b/src/class/audio/audio.h
@@ -489,7 +489,7 @@ typedef enum
   AUDIO_DATA_FORMAT_TYPE_I_IEEE_FLOAT     = (uint32_t) (1 << 2),
   AUDIO_DATA_FORMAT_TYPE_I_ALAW           = (uint32_t) (1 << 3),
   AUDIO_DATA_FORMAT_TYPE_I_MULAW          = (uint32_t) (1 << 4),
-  AUDIO_DATA_FORMAT_TYPE_I_RAW_DATA       = 0x100000000,
+  AUDIO_DATA_FORMAT_TYPE_I_RAW_DATA       = 0x80000000,
 } audio_data_format_type_I_t;
 
 /// All remaining definitions are taken from the descriptor descriptions in the UAC2 main specification
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 3e05b3763..31b318c3f 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -102,19 +102,19 @@
 // EP IN software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
 #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_in_ff_mutex_wr_1;                                                             // No need for read mutex as only USB driver reads from FIFO
 #endif
 #endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_in_ff_mutex_wr_2;                                                             // No need for read mutex as only USB driver reads from FIFO
 #endif
 #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_in_ff_mutex_wr_3;                                                             // No need for read mutex as only USB driver reads from FIFO
 #endif
@@ -126,32 +126,32 @@ osal_mutex_def_t ep_in_ff_mutex_wr_3;
 // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING)
 #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
 #endif
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
 #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 
 // EP OUT software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
 #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_out_ff_mutex_rd_1;                                                            // No need for write mutex as only USB driver writes into FIFO
 #endif
 #endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_out_ff_mutex_rd_2;                                                            // No need for write mutex as only USB driver writes into FIFO
 #endif
 #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_out_ff_mutex_rd_3;                                                            // No need for write mutex as only USB driver writes into FIFO
 #endif
@@ -163,52 +163,52 @@ osal_mutex_def_t ep_out_ff_mutex_rd_3;
 // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
 #endif
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
 #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 
 // Control buffers
-CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
 #if CFG_TUD_AUDIO > 1
-CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
 #endif
 #if CFG_TUD_AUDIO > 2
-CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
 #endif
 
 // Active alternate setting of interfaces
-CFG_TUSB_MEM_ALIGN uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_N_AS_INT > 0
-CFG_TUSB_MEM_ALIGN uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_N_AS_INT > 0
-CFG_TUSB_MEM_ALIGN uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 #endif
 
 // Software encoding/decoding support FIFOs
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
 #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
 tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
 #endif
 #endif
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
 tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
 #endif
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
 tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
@@ -218,21 +218,21 @@ osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
 #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
 tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
 #endif
 #endif
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
 tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
 #endif
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
 tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
@@ -294,7 +294,7 @@ typedef struct
 
   // Audio control interrupt buffer - no FIFO - 6 Bytes according to UAC 2 specification (p. 74)
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-  CFG_TUSB_MEM_ALIGN uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
+  CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
 #endif
 
   // Decoding parameters - parameters are set when alternate AS interface is set by host

From fdbbe5df3f73d336c36a8ab673cec4f9440d82cf Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 2 Jul 2021 23:44:46 +0200
Subject: [PATCH 0153/2085] Fix speed detection

---
 src/class/audio/audio_device.c | 27 ++++++++++++---------------
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 31b318c3f..cc07d5e19 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2223,22 +2223,19 @@ bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
   // Format the feedback value
-  if (_audiod_fct[func_id].rhport == 0)
-  {
-    uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].fb_val;
+#if !TUD_OPT_HIGH_SPEED
+  uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].fb_val;
 
-    // For FS format is 10.14
-    *(fb++) = (feedback >> 2) & 0xFF;
-    *(fb++) = (feedback >> 10) & 0xFF;
-    *(fb++) = (feedback >> 18) & 0xFF;
-    // 4th byte is needed to work correctly with MS Windows
-    *fb = 0;
-  }
-  else
-  {
-    // For HS format is 16.16 as originally demanded
-    _audiod_fct[func_id].fb_val = feedback;
-  }
+  // For FS format is 10.14
+  *(fb++) = (feedback >> 2) & 0xFF;
+  *(fb++) = (feedback >> 10) & 0xFF;
+  *(fb++) = (feedback >> 18) & 0xFF;
+  // 4th byte is needed to work correctly with MS Windows
+  *fb = 0;
+#else
+  // For HS format is 16.16 as originally demanded
+  _audiod_fct[func_id].fb_val = feedback;
+#endif
 
   // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value
   if (!usbd_edpt_busy(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_fb))

From 12747b61d5a8d4ecf51a93bbbcee09a9c71f183b Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 3 Jul 2021 10:54:20 +0200
Subject: [PATCH 0154/2085] Delay tud_audio_set_itf_cb call with feedback EP.

---
 src/class/audio/audio_device.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index cc07d5e19..61884f867 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1619,9 +1619,17 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             TU_ASSERT( audio->n_ff_used_rx <= audio->n_rx_supp_ff );
 #endif
 #endif
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+            // In case of asynchronous EP, call Cb after ep_fb is set
+            if (((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.sync != 0x01)
+            {
+              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+            }
+#else
             // Invoke callback
             if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
-
+#endif
             // Prepare for incoming data
 #if USE_LINEAR_BUFFER_RX
             TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false);

From 3019c6eb40f5e577a5075a4fccd275c5537c5a34 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 3 Jul 2021 00:48:49 +0900
Subject: [PATCH 0155/2085] Add SUSPEND/RESUME handling for Renesas RX family.

---
 src/portable/renesas/usba/dcd_usba.c | 29 +++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index de3e0e312..fa584945e 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -63,7 +63,10 @@
 #define USB_IS0_CTSQ_SETUP   (1u)
 #define USB_IS0_DVSQ_DEF     (1u<<4)
 #define USB_IS0_DVSQ_ADDR    (2u<<4)
-#define USB_IS0_DVSQ_SUSP    (4u<<4)
+#define USB_IS0_DVSQ_SUSP0   (4u<<4)
+#define USB_IS0_DVSQ_SUSP1   (5u<<4)
+#define USB_IS0_DVSQ_SUSP2   (6u<<4)
+#define USB_IS0_DVSQ_SUSP3   (7u<<4)
 
 #define USB_PIPECTR_PID_NAK   (0u)
 #define USB_PIPECTR_PID_BUF   (1u)
@@ -125,6 +128,7 @@ typedef struct
 {
   pipe_state_t pipe[9];
   uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
+  uint8_t suspended;
 } dcd_data_t;
 
 //--------------------------------------------------------------------+
@@ -517,7 +521,8 @@ void dcd_init(uint8_t rhport)
 
   /* Setup default control pipe */
   USB0.DCPMAXP.BIT.MXPS  = 64;
-  USB0.INTENB0.WORD = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP | USB_IS0_DVST | USB_IS0_CTRT;
+  USB0.INTENB0.WORD = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP |
+    USB_IS0_DVST | USB_IS0_CTRT | USB_IS0_SOFR | USB_IS0_RESM;
   USB0.BEMPENB.WORD = 1;
   USB0.BRDYENB.WORD = 1;
 
@@ -547,7 +552,8 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void)rhport;
-  /* TODO */
+  USB0.DVSTCTR0.BIT.WKUP = 1;
+  while (USB0.DVSTCTR0.BIT.WKUP) ;
 }
 
 void dcd_connect(uint8_t rhport)
@@ -689,6 +695,17 @@ void dcd_int_handler(uint8_t rhport)
       dcd_disconnect(rhport);
     }
   }
+  if (is0 & USB_IS0_RESM) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+    _dcd.suspended = 0;
+  }
+  if (is0 & USB_IS0_SOFR) {
+    if (_dcd.suspended) {
+      dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+      _dcd.suspended = 0;
+    }
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
   if (is0 & USB_IS0_DVST) {
     switch (is0 & USB_IS0_DVSQ) {
     case USB_IS0_DVSQ_DEF:
@@ -697,6 +714,12 @@ void dcd_int_handler(uint8_t rhport)
     case USB_IS0_DVSQ_ADDR:
       process_set_address(rhport);
       break;
+    case USB_IS0_DVSQ_SUSP0:
+    case USB_IS0_DVSQ_SUSP1:
+    case USB_IS0_DVSQ_SUSP2:
+    case USB_IS0_DVSQ_SUSP3:
+       dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+       _dcd.suspended = 1;
     default:
       break;
     }

From e4ae81abd8e9d6373d5e6267eff800248598a70a Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sun, 4 Jul 2021 00:19:33 +0200
Subject: [PATCH 0156/2085] Move audio_control_request_t to audio.h

---
 examples/device/uac2_headset/src/main.c | 26 ------------------------
 src/class/audio/audio.h                 | 27 +++++++++++++++++++++++++
 2 files changed, 27 insertions(+), 26 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index b459bc2a8..ba27350b4 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -142,32 +142,6 @@ void tud_resume_cb(void)
   blink_interval_ms = BLINK_MOUNTED;
 }
 
-typedef struct TU_ATTR_PACKED
-{
-  union
-  {
-    struct TU_ATTR_PACKED
-    {
-      uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.
-      uint8_t type      :  2; ///< Request type tusb_request_type_t.
-      uint8_t direction :  1; ///< Direction type. tusb_dir_t
-    } bmRequestType_bit;
-
-    uint8_t bmRequestType;
-  };
-
-  uint8_t bRequest;  ///< Request type audio_cs_req_t
-  uint8_t bChannelNumber;
-  uint8_t bControlSelector;
-  union
-  {
-    uint8_t bInterface;
-    uint8_t bEndpoint;
-  };
-  uint8_t bEntityID;
-  uint16_t wLength;
-} audio_control_request_t;
-
 // Helper for clock get requests
 static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t const *request)
 {
diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h
index 238295d25..f99061eae 100644
--- a/src/class/audio/audio.h
+++ b/src/class/audio/audio.h
@@ -823,6 +823,33 @@ typedef struct TU_ATTR_PACKED
   uint16_t wLockDelay        ; ///< Indicates the time it takes this endpoint to reliably lock its internal clock recovery circuitry. Units used depend on the value of the bLockDelayUnits field.
 } audio_desc_cs_as_iso_data_ep_t;
 
+// 5.2.2 Control Request Layout
+typedef struct TU_ATTR_PACKED
+{
+    union
+    {
+        struct TU_ATTR_PACKED
+        {
+            uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.
+            uint8_t type      :  2; ///< Request type tusb_request_type_t.
+            uint8_t direction :  1; ///< Direction type. tusb_dir_t
+        } bmRequestType_bit;
+        
+        uint8_t bmRequestType;
+    };
+    
+    uint8_t bRequest;  ///< Request type audio_cs_req_t
+    uint8_t bChannelNumber;
+    uint8_t bControlSelector;
+    union
+    {
+        uint8_t bInterface;
+        uint8_t bEndpoint;
+    };
+    uint8_t bEntityID;
+    uint16_t wLength;
+} audio_control_request_t;
+
 //// 5.2.3 Control Request Parameter Block Layout
 
 // 5.2.3.1 1-byte Control CUR Parameter Block

From fa2320d83712b1860069e429d3924f2d5f8ca316 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sun, 4 Jul 2021 15:10:45 +0200
Subject: [PATCH 0157/2085] Better handling tud_audio_set_itf_cb with FB.

---
 src/class/audio/audio_device.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 61884f867..c7b8b8519 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1622,7 +1622,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
             // In case of asynchronous EP, call Cb after ep_fb is set
-            if (((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.sync != 0x01)
+            if (!(((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.sync == 0x01 && audio->ep_fb == 0))
             {
               if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
             }
@@ -1643,8 +1643,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
           {
             audio->ep_fb = ep_addr;
 
-            // Invoke callback
-            if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+            // Invoke callback after ep_out is set
+            if (audio->ep_out != 0)
+            {
+              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+            }
           }
 #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -1938,8 +1941,12 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     {
       if (tud_audio_fb_done_cb) TU_VERIFY(tud_audio_fb_done_cb(rhport));
 
-      // Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent
-      return audiod_fb_send(rhport, &_audiod_fct[func_id]);
+      // Schedule a transmit with the new value if EP is not busy 
+      if (!usbd_edpt_busy(rhport, _audiod_fct[func_id].ep_fb))
+      {
+        // Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent
+        return audiod_fb_send(rhport, &_audiod_fct[func_id]);
+      }
     }
 #endif
 #endif

From 6e9da70c18a0dbabaedb1c9aadcc9fe53a0113a7 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 29 Jun 2021 22:40:21 +0200
Subject: [PATCH 0158/2085] Fix audiod_get_AS_interface_index in audio class.
 Enhance uac2_headset example with multiple sample rates. Add macro to
 calculate EP size.

---
 examples/device/uac2_headset/src/main.c       | 69 ++++++++++++++-----
 .../device/uac2_headset/src/tusb_config.h     | 13 ++--
 .../device/uac2_headset/src/usb_descriptors.c |  2 +-
 .../device/uac2_headset/src/usb_descriptors.h |  8 +--
 src/class/audio/audio_device.c                | 16 +++--
 src/device/usbd.h                             |  5 ++
 6 files changed, 77 insertions(+), 36 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 1b6a770a3..e76b081c8 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -34,9 +34,11 @@
 // MACRO CONSTANT TYPEDEF PROTOTYPES
 //--------------------------------------------------------------------+
 
-#ifndef AUDIO_SAMPLE_RATE
-#define AUDIO_SAMPLE_RATE     48000
-#endif
+// List of supported sample rates
+const uint32_t sample_rates[]       = {44100, 48000, 88200, 96000};
+uint32_t       current_sample_rate  = 44100;
+
+#define N_SAMPLE_RATES  (sizeof(sample_rates) / 4)
 
 /* Blink pattern
  * - 25 ms   : streaming data
@@ -166,24 +168,30 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
 {
   TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
 
-  // Example supports only single frequency, same value will be used for current value and range
   if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
   {
     if (request->bRequest == AUDIO_CS_REQ_CUR)
     {
-      TU_LOG2("Clock get current freq %u\r\n", AUDIO_SAMPLE_RATE);
+      TU_LOG1("Clock get current freq %u\r\n", current_sample_rate);
 
-      audio_control_cur_4_t curf = { tu_htole32(AUDIO_SAMPLE_RATE) };
+      audio_control_cur_4_t curf = { tu_htole32(current_sample_rate) };
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
     }
     else if (request->bRequest == AUDIO_CS_REQ_RANGE)
     {
-      audio_control_range_4_n_t(1) rangef =
+      audio_control_range_4_n_t(N_SAMPLE_RATES) rangef =
       {
-        .wNumSubRanges = tu_htole16(1),
-        .subrange[0] = { tu_htole32(AUDIO_SAMPLE_RATE), tu_htole32(AUDIO_SAMPLE_RATE), 0}
+        .wNumSubRanges = tu_htole16(N_SAMPLE_RATES)
       };
-      TU_LOG2("Clock get freq range (%d, %d, %d)\r\n", (int)rangef.subrange[0].bMin, (int)rangef.subrange[0].bMax, (int)rangef.subrange[0].bRes);
+      TU_LOG1("Clock get %d freq ranges\r\n", N_SAMPLE_RATES);
+      for(uint8_t i = 0; i < N_SAMPLE_RATES; i++)
+      {
+        rangef.subrange[i].bMin = sample_rates[i];
+        rangef.subrange[i].bMax = sample_rates[i];
+        rangef.subrange[i].bRes = 0;
+        TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
+      }
+      
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef));
     }
   }
@@ -191,7 +199,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
            request->bRequest == AUDIO_CS_REQ_CUR)
   {
     audio_control_cur_1_t cur_valid = { .bCur = 1 };
-    TU_LOG2("Clock get is valid %u\r\n", cur_valid.bCur);
+    TU_LOG1("Clock get is valid %u\r\n", cur_valid.bCur);
     return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_valid, sizeof(cur_valid));
   }
   TU_LOG1("Clock get request not supported, entity = %u, selector = %u, request = %u\r\n",
@@ -199,6 +207,32 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
   return false;
 }
 
+// Helper for clock set requests
+static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+  (void)rhport;
+
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT);
+  TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+  if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_4_t));
+
+    current_sample_rate = ((audio_control_cur_4_t *)buf)->bCur;
+
+    TU_LOG1("Clock set current freq: %d\r\n", current_sample_rate);
+
+    return true;
+  }
+  else
+  {
+    TU_LOG1("Clock set request not supported, entity = %u, selector = %u, request = %u\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+    return false;
+  }
+}
+
 // Helper for feature unit get requests
 static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_request_t const *request)
 {
@@ -207,7 +241,7 @@ static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_req
   if (request->bControlSelector == AUDIO_FU_CTRL_MUTE && request->bRequest == AUDIO_CS_REQ_CUR)
   {
     audio_control_cur_1_t mute1 = { .bCur = mute[request->bChannelNumber] };
-    TU_LOG2("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
+    TU_LOG1("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
     return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &mute1, sizeof(mute1));
   }
   else if (UAC2_ENTITY_SPK_FEATURE_UNIT && request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
@@ -218,14 +252,14 @@ static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_req
         .wNumSubRanges = tu_htole16(1),
         .subrange[0] = { .bMin = tu_htole16(-VOLUME_CTRL_50_DB), tu_htole16(VOLUME_CTRL_0_DB), tu_htole16(256) }
       };
-      TU_LOG2("Get channel %u volume range (%d, %d, %u) dB\r\n", request->bChannelNumber,
+      TU_LOG1("Get channel %u volume range (%d, %d, %u) dB\r\n", request->bChannelNumber,
               range_vol.subrange[0].bMin / 256, range_vol.subrange[0].bMax / 256, range_vol.subrange[0].bRes / 256);
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &range_vol, sizeof(range_vol));
     }
     else if (request->bRequest == AUDIO_CS_REQ_CUR)
     {
       audio_control_cur_2_t cur_vol = { .bCur = tu_htole16(volume[request->bChannelNumber]) };
-      TU_LOG2("Get channel %u volume %u dB\r\n", request->bChannelNumber, cur_vol.bCur);
+      TU_LOG1("Get channel %u volume %d dB\r\n", request->bChannelNumber, cur_vol.bCur / 256);
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_vol, sizeof(cur_vol));
     }
   }
@@ -249,7 +283,7 @@ static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_req
 
     mute[request->bChannelNumber] = ((audio_control_cur_1_t *)buf)->bCur;
 
-    TU_LOG2("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]);
+    TU_LOG1("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]);
 
     return true;
   }
@@ -259,7 +293,7 @@ static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_req
 
     volume[request->bChannelNumber] = ((audio_control_cur_2_t const *)buf)->bCur;
 
-    TU_LOG2("Set channel %d volume: %d dB\r\n", request->bChannelNumber, volume[request->bChannelNumber] / 256);
+    TU_LOG1("Set channel %d volume: %d dB\r\n", request->bChannelNumber, volume[request->bChannelNumber] / 256);
 
     return true;
   }
@@ -299,7 +333,8 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p
 
   if (request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT)
     return tud_audio_feature_unit_set_request(rhport, request, buf);
-
+  if (request->bEntityID == UAC2_ENTITY_CLOCK)
+    return tud_audio_clock_set_request(rhport, request, buf);
   TU_LOG1("Set request not handled, entity = %d, selector = %d, request = %d\r\n",
           request->bEntityID, request->bControlSelector, request->bRequest);
 
diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index 88f9efcff..9b7ed337c 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -93,13 +93,12 @@ extern "C" {
 //--------------------------------------------------------------------
 // AUDIO CLASS DRIVER CONFIGURATION
 //--------------------------------------------------------------------
-#define CFG_TUD_AUDIO_IN_PATH                     (CFG_TUD_AUDIO)
-#define CFG_TUD_AUDIO_OUT_PATH                    (CFG_TUD_AUDIO)
 
 //#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                       220       // This equals TUD_AUDIO_HEADSET_STEREO_DESC_LEN, however, including it from usb_descriptors.h is not possible due to some strange include hassle
 #define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                       TUD_AUDIO_HEADSET_STEREO_DESC_LEN
 
 // Audio format type I specifications
+#define CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE              96000
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                  1
 #define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX          2
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                  2
@@ -108,18 +107,18 @@ extern "C" {
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
 #define CFG_TUD_AUDIO_ENABLE_EP_IN                1
-#define CFG_TUD_AUDIO_EP_SZ_IN                    (CFG_TUD_AUDIO_IN_PATH * (48 + 1) * (CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX) * (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)) // 48 Samples (48 kHz) x 2 Bytes/Sample x n Channels
+#define CFG_TUD_AUDIO_EP_SZ_IN                    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX) // 48 Samples (48 kHz) x 2 Bytes/Sample x n Channels
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      CFG_TUD_AUDIO_EP_SZ_IN
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         CFG_TUD_AUDIO_EP_SZ_IN                  // Maximum EP IN size for all AS alternate settings used
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
 #define CFG_TUD_AUDIO_ENABLE_EP_OUT               1
-#define CFG_TUD_AUDIO_EP_OUT_SZ                   (CFG_TUD_AUDIO_OUT_PATH * ((48 + CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP) * (CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX) * (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX))) // N Samples (N kHz) x 2 Bytes/Sample x n Channels
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     CFG_TUD_AUDIO_EP_OUT_SZ*3
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        CFG_TUD_AUDIO_EP_OUT_SZ                 // Maximum EP IN size for all AS alternate settings used
+#define CFG_TUD_AUDIO_EP_SZ_OUT                   TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX) // N Samples (N kHz) x 2 Bytes/Sample x n Channels
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     CFG_TUD_AUDIO_EP_SZ_OUT*3
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        CFG_TUD_AUDIO_EP_SZ_OUT                 // Maximum EP IN size for all AS alternate settings used
 
 // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
-#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 	          1
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 	          2
 
 // Size of control request buffer
 #define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ	64
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index cd749eb65..f5d8e461b 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -93,7 +93,7 @@ uint8_t const desc_configuration[] =
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
-    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, 2, 16, EPNUM_AUDIO, CFG_TUD_AUDIO_EP_OUT_SZ, EPNUM_AUDIO | 0x80, CFG_TUD_AUDIO_EP_SZ_IN)
+    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, 2, 16, EPNUM_AUDIO, CFG_TUD_AUDIO_EP_SZ_OUT, EPNUM_AUDIO | 0x80, CFG_TUD_AUDIO_EP_SZ_IN)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index d9c5a63a7..1595d9c5d 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -77,7 +77,7 @@ enum
     /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
     TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_HEADSET, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
     /* Clock Source Descriptor(4.7.2.1) */\
-    TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ UAC2_ENTITY_CLOCK, /*_attr*/ 3, /*_ctrl*/ 5, /*_assocTerm*/ 0x00,  /*_stridx*/ 0x00),    \
+    TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ UAC2_ENTITY_CLOCK, /*_attr*/ 3, /*_ctrl*/ 7, /*_assocTerm*/ 0x00,  /*_stridx*/ 0x00),    \
     /* Input Terminal Descriptor(4.7.2.4) */\
     TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
     /* Feature Unit Descriptor(4.7.2.8) */\
@@ -99,21 +99,21 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Standard AS Interface Descriptor(4.9.1) */\
     /* Interface 2, Alternate 0 - default alternate setting with 0 bandwidth */\
     TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x04),\
     /* Standard AS Interface Descriptor(4.9.1) */\
-    /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+    /* Interface 2, Alternate 1 - alternate interface for data streaming */\
     TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
     /* Class-Specific AS Interface Descriptor(4.9.2) */\
     TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epinsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epinsize, /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)\
 
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 7263958df..cb35adb82 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1997,15 +1997,17 @@ static bool audiod_get_AS_interface_index(uint8_t itf, audiod_function_t * audio
     while (p_desc < p_desc_end)
     {
       // We assume the number of alternate settings is increasing thus we return the index of alternate setting zero!
-      if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf)
+      if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == 0)
       {
-        *idxItf = tmp;
-        *pp_desc_int = p_desc;
-        return true;
+        if (((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf)
+        {
+          *idxItf = tmp;
+          *pp_desc_int = p_desc;
+          return true;
+        }
+        // Increase index, bytes read, and pointer
+        tmp++;
       }
-
-      // Increase index, bytes read, and pointer
-      tmp++;
       p_desc = tu_desc_next(p_desc);
     }
   }
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 3857295d7..45aefe53b 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -542,6 +542,11 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
   TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_interval*/ 1)\
 
+//   Calculate wMaxPacketSize of Endpoints
+#define TUD_AUDIO_EP_SIZE(_maxFrequency, _nBytesPerSample, _nChannels) \
+    ((((_maxFrequency + ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 7999 : 999)) / ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels)
+
+
 //------------- TUD_USBTMC/USB488 -------------//
 #define TUD_USBTMC_APP_CLASS    (TUSB_CLASS_APPLICATION_SPECIFIC)
 #define TUD_USBTMC_APP_SUBCLASS 0x03u

From 325742acb45b14ca3e5ebc64f82706cd31fe495b Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 30 Jun 2021 19:04:04 +0200
Subject: [PATCH 0159/2085] Fix typo

---
 examples/device/uac2_headset/src/main.c            | 2 +-
 examples/device/uac2_headset/src/usb_descriptors.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index e76b081c8..e119ee2c8 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -212,7 +212,7 @@ static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t
 {
   (void)rhport;
 
-  TU_ASSERT(request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT);
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
   TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
 
   if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 1595d9c5d..8ce3b26e0 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -99,7 +99,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Standard AS Interface Descriptor(4.9.1) */\
@@ -113,7 +113,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epinsize, /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epinsize, /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)\
 

From a1639b027997706977a550faa34ef85d48a75fba Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 00:26:24 +0200
Subject: [PATCH 0160/2085] Refactor descriptor, add alt settings support.

---
 .../device/uac2_headset/src/tusb_config.h     | 42 ++++++++++------
 .../device/uac2_headset/src/usb_descriptors.c |  2 +-
 .../device/uac2_headset/src/usb_descriptors.h | 49 +++++++++++++++----
 3 files changed, 68 insertions(+), 25 deletions(-)

diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index 9b7ed337c..e97f4c470 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -94,28 +94,42 @@ extern "C" {
 // AUDIO CLASS DRIVER CONFIGURATION
 //--------------------------------------------------------------------
 
-//#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                       220       // This equals TUD_AUDIO_HEADSET_STEREO_DESC_LEN, however, including it from usb_descriptors.h is not possible due to some strange include hassle
-#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                       TUD_AUDIO_HEADSET_STEREO_DESC_LEN
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                TUD_AUDIO_HEADSET_STEREO_DESC_LEN
 
 // Audio format type I specifications
-#define CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE              96000
-#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                  1
-#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX          2
-#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                  2
-#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX          2
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP                    0
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000     // 24bit/96kHz is the best quality for full-speed, high-speed is needed beyond this
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                           1
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                           2
+
+// 16bit in 16bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX          2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX                  16
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX          2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX                  16
+
+// 24bit in 32bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX          4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX                  24
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX          4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX                  24
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
 #define CFG_TUD_AUDIO_ENABLE_EP_IN                1
-#define CFG_TUD_AUDIO_EP_SZ_IN                    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX) // 48 Samples (48 kHz) x 2 Bytes/Sample x n Channels
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      CFG_TUD_AUDIO_EP_SZ_IN
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         CFG_TUD_AUDIO_EP_SZ_IN                  // Maximum EP IN size for all AS alternate settings used
+
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN) // Maximum EP IN size for all AS alternate settings used
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
 #define CFG_TUD_AUDIO_ENABLE_EP_OUT               1
-#define CFG_TUD_AUDIO_EP_SZ_OUT                   TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_N_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX) // N Samples (N kHz) x 2 Bytes/Sample x n Channels
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     CFG_TUD_AUDIO_EP_SZ_OUT*3
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        CFG_TUD_AUDIO_EP_SZ_OUT                 // Maximum EP IN size for all AS alternate settings used
+
+#define CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+#define CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT)*3
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT) // Maximum EP IN size for all AS alternate settings used
 
 // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
 #define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 	          2
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index f5d8e461b..6a01f8938 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -93,7 +93,7 @@ uint8_t const desc_configuration[] =
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
-    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, 2, 16, EPNUM_AUDIO, CFG_TUD_AUDIO_EP_SZ_OUT, EPNUM_AUDIO | 0x80, CFG_TUD_AUDIO_EP_SZ_IN)
+    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO, EPNUM_AUDIO | 0x80)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 8ce3b26e0..4fae25831 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -62,14 +62,23 @@ enum
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
 
-
-#define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epoutsize, _epin, _epinsize) \
+#define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin) \
     /* Standard Interface Association Descriptor (IAD) */\
     TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ ITF_NUM_TOTAL, /*_stridx*/ 0x00),\
     /* Standard AC Interface Descriptor(4.7.1) */\
@@ -83,7 +92,7 @@ enum
     /* Feature Unit Descriptor(4.7.2.8) */\
     TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL(/*_unitid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_srcid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrlch0master*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch1*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch2*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_stridx*/ 0x00),\
     /* Output Terminal Descriptor(4.7.2.5) */\
-    TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_OUT_GENERIC_SPEAKER, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+    TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_OUT_HEADPHONES, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
     /* Input Terminal Descriptor(4.7.2.4) */\
     TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_MIC_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
     /* Output Terminal Descriptor(4.7.2.5) */\
@@ -95,11 +104,21 @@ enum
     /* Interface 1, Alternate 1 - alternate interface for data streaming */\
     TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x05),\
     /* Class-Specific AS Interface Descriptor(4.9.2) */\
-    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
-    TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epoutsize, /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
+    /* Interface 1, Alternate 2 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x05),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Standard AS Interface Descriptor(4.9.1) */\
@@ -109,12 +128,22 @@ enum
     /* Interface 2, Alternate 1 - alternate interface for data streaming */\
     TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
     /* Class-Specific AS Interface Descriptor(4.9.2) */\
-    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
-    TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epinsize, /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
-    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
+    /* Interface 2, Alternate 2 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
 #endif

From 204f3152cb486b8de3817bf940efd4593c8bfd07 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 11:38:06 +0200
Subject: [PATCH 0161/2085] audio_device : clear fifo on intf change.

---
 src/class/audio/audio_device.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index cb35adb82..230b689cd 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1481,6 +1481,9 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     audio->ep_in_as_intf_num = 0;
     usbd_edpt_close(rhport, audio->ep_in);
 
+    // Clear FIFOs, since data is no longer valid
+    tu_fifo_clear(&audio->ep_in_ff);
+    
     // Invoke callback - can be used to stop data sampling
     if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
 
@@ -1502,6 +1505,13 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   {
     audio->ep_out_as_intf_num = 0;
     usbd_edpt_close(rhport, audio->ep_out);
+
+    // Clear FIFOs, since data is no longer valid
+    tu_fifo_clear(&audio->ep_out_ff);
+
+    // Invoke callback - can be used to stop data sampling
+    if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
+
     audio->ep_out = 0;                          // Necessary?
 
     // Clear support FIFOs if used

From 5b7795be4be83daa0a1575a47299af1a89348bc0 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 11:39:15 +0200
Subject: [PATCH 0162/2085] Add 24bit loopback in example.

---
 examples/device/uac2_headset/src/main.c       | 58 ++++++++++++++-----
 .../device/uac2_headset/src/tusb_config.h     |  3 +
 .../device/uac2_headset/src/usb_descriptors.h |  6 ++
 3 files changed, 54 insertions(+), 13 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index e119ee2c8..c9e79a543 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -38,7 +38,7 @@
 const uint32_t sample_rates[]       = {44100, 48000, 88200, 96000};
 uint32_t       current_sample_rate  = 44100;
 
-#define N_SAMPLE_RATES  (sizeof(sample_rates) / 4)
+#define N_SAMPLE_RATES  TU_ARRAY_SIZE(sample_rates)
 
 /* Blink pattern
  * - 25 ms   : streaming data
@@ -78,11 +78,16 @@ int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];       // +1 for master chan
 int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];    // +1 for master channel 0
 
 // Buffer for microphone data
-int16_t mic_buf[1000];
+uint8_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
 // Buffer for speaker data
-int16_t spk_buf[1000];
+uint8_t spk_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
 // Speaker data size received in the last frame
 int spk_data_size;
+// Resolution per format
+const uint8_t resolutions_per_format[CFG_TUD_AUDIO_FUNC_1_N_FORMATS] = {CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX,
+                                                                        CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX};
+// Current resolution, update on format change
+uint8_t current_resolution;
 
 void led_blinking_task(void);
 void audio_task(void);
@@ -364,6 +369,13 @@ bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_reque
   if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt != 0)
       blink_interval_ms = BLINK_STREAMING;
 
+  // Clear buffer when streaming format is changed
+  spk_data_size = 0;
+  if(alt != 0)
+  {
+    current_resolution = resolutions_per_format[alt-1];
+  }
+
   return true;
 }
 
@@ -397,20 +409,40 @@ void audio_task(void)
 {
   // When new data arrived, copy data from speaker buffer, to microphone buffer
   // and send it over
+  // Only support speaker & headphone both have the same resolution
+  // If one is 16bit another is 24bit be care of LOUD noise !
   if (spk_data_size)
   {
-    int16_t *src = spk_buf;
-    int16_t *limit = spk_buf + spk_data_size / 2;
-    int16_t *dst = mic_buf;
-    while (src < limit)
+    if (current_resolution == 16)
     {
-      // Combine two channels into one
-      int32_t left = *src++;
-      int32_t right = *src++;
-      *dst++ = (int16_t)((left + right) / 2);
+      int16_t *src = (int16_t*)spk_buf;
+      int16_t *limit = (int16_t*)spk_buf + spk_data_size / 2;
+      int16_t *dst = (int16_t*)mic_buf;
+      while (src < limit)
+      {
+        // Combine two channels into one
+        int32_t left = *src++;
+        int32_t right = *src++;
+        *dst++ = (int16_t)((left + right) / 2);
+      }
+      tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
+      spk_data_size = 0;
+    }
+    else if (current_resolution == 24)
+    {
+      int32_t *src = (int32_t*)spk_buf;
+      int32_t *limit = (int32_t*)spk_buf + spk_data_size / 4;
+      int32_t *dst = (int32_t*)mic_buf;
+      while (src < limit)
+      {
+        // Combine two channels into one
+        int32_t left = (*src++);
+        int32_t right = (*src++);
+        *dst++ = (int32_t)((left + right) / 2) & 0xffffff00;
+      }
+      tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
+      spk_data_size = 0;
     }
-    tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
-    spk_data_size = 0;
   }
 }
 
diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index e97f4c470..642e52551 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -96,6 +96,9 @@ extern "C" {
 
 #define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                TUD_AUDIO_HEADSET_STEREO_DESC_LEN
 
+// How many formats are used, need to adjust USB descriptor if changed
+#define CFG_TUD_AUDIO_FUNC_1_N_FORMATS                               2
+
 // Audio format type I specifications
 #define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000     // 24bit/96kHz is the best quality for full-speed, high-speed is needed beyond this
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                           1
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 4fae25831..d9510ea4f 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -55,23 +55,29 @@ enum
     + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
     + TUD_AUDIO_DESC_INPUT_TERM_LEN\
     + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    /* Interface 1, Alternate 0 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 1, Alternate 2 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 2, Alternate 0 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    /* Interface 2, Alternate 1 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
     + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
     + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 2, Alternate 2 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\

From 8d1a88cab63334fea19794d8bb040dbdcc06c7ad Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jul 2021 14:09:17 +0700
Subject: [PATCH 0163/2085] skip uac2_headset for mcu that does not have enough
 sram

---
 examples/device/uac2_headset/.skip.MCU_LPC11UXX   | 0
 examples/device/uac2_headset/.skip.MCU_LPC13XX    | 0
 examples/device/uac2_headset/.skip.MCU_MSP430x5xx | 0
 examples/device/uac2_headset/.skip.MCU_NUC121     | 0
 examples/device/uac2_headset/.skip.MCU_STM32L0    | 0
 5 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 examples/device/uac2_headset/.skip.MCU_LPC11UXX
 create mode 100644 examples/device/uac2_headset/.skip.MCU_LPC13XX
 create mode 100644 examples/device/uac2_headset/.skip.MCU_MSP430x5xx
 create mode 100644 examples/device/uac2_headset/.skip.MCU_NUC121
 create mode 100644 examples/device/uac2_headset/.skip.MCU_STM32L0

diff --git a/examples/device/uac2_headset/.skip.MCU_LPC11UXX b/examples/device/uac2_headset/.skip.MCU_LPC11UXX
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/uac2_headset/.skip.MCU_LPC13XX b/examples/device/uac2_headset/.skip.MCU_LPC13XX
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/uac2_headset/.skip.MCU_MSP430x5xx b/examples/device/uac2_headset/.skip.MCU_MSP430x5xx
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/uac2_headset/.skip.MCU_NUC121 b/examples/device/uac2_headset/.skip.MCU_NUC121
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/uac2_headset/.skip.MCU_STM32L0 b/examples/device/uac2_headset/.skip.MCU_STM32L0
new file mode 100644
index 000000000..e69de29bb

From 5f67e5c1e9b10e40ac6e3a649f45f7719b437dc5 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 11:45:39 +0200
Subject: [PATCH 0164/2085] Clear FIFO only if enabled... Add buffer align

---
 examples/device/uac2_headset/src/main.c        | 14 +++++++-------
 examples/device/uac2_headset/src/tusb_config.h |  4 ++--
 src/class/audio/audio_device.c                 |  4 ++++
 3 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index c9e79a543..f7d20a607 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -78,9 +78,9 @@ int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];       // +1 for master chan
 int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];    // +1 for master channel 0
 
 // Buffer for microphone data
-uint8_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+int32_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ / 4];
 // Buffer for speaker data
-uint8_t spk_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+int32_t spk_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ / 4];
 // Speaker data size received in the last frame
 int spk_data_size;
 // Resolution per format
@@ -430,14 +430,14 @@ void audio_task(void)
     }
     else if (current_resolution == 24)
     {
-      int32_t *src = (int32_t*)spk_buf;
-      int32_t *limit = (int32_t*)spk_buf + spk_data_size / 4;
-      int32_t *dst = (int32_t*)mic_buf;
+      int32_t *src = spk_buf;
+      int32_t *limit = spk_buf + spk_data_size / 4;
+      int32_t *dst = mic_buf;
       while (src < limit)
       {
         // Combine two channels into one
-        int32_t left = (*src++);
-        int32_t right = (*src++);
+        int32_t left = *src++;
+        int32_t right = *src++;
         *dst++ = (int32_t)((left + right) / 2) & 0xffffff00;
       }
       tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index 642e52551..d955a746d 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -122,7 +122,7 @@ extern "C" {
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
 
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN)*2
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN) // Maximum EP IN size for all AS alternate settings used
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
@@ -131,7 +131,7 @@ extern "C" {
 #define CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
 #define CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
 
-#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT)*3
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT)*2
 #define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT) // Maximum EP IN size for all AS alternate settings used
 
 // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 230b689cd..3e05b3763 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1481,8 +1481,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     audio->ep_in_as_intf_num = 0;
     usbd_edpt_close(rhport, audio->ep_in);
 
+#if !CFG_TUD_AUDIO_ENABLE_ENCODING
     // Clear FIFOs, since data is no longer valid
     tu_fifo_clear(&audio->ep_in_ff);
+#endif
     
     // Invoke callback - can be used to stop data sampling
     if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
@@ -1506,8 +1508,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     audio->ep_out_as_intf_num = 0;
     usbd_edpt_close(rhport, audio->ep_out);
 
+#if !CFG_TUD_AUDIO_ENABLE_ENCODING
     // Clear FIFOs, since data is no longer valid
     tu_fifo_clear(&audio->ep_out_ff);
+#endif
 
     // Invoke callback - can be used to stop data sampling
     if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));

From 3cc222781011f4ee1de1fdde7db8f9d010a17af6 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 12:59:26 +0200
Subject: [PATCH 0165/2085] Partially revert "skip uac2_headset for mcu that
 does not have enough sram"

This reverts commit 6e1f812e3542f6d9047a3b8148f2f073ba38b91f.
---
 examples/device/uac2_headset/.skip.MCU_LPC11UXX   | 0
 examples/device/uac2_headset/.skip.MCU_LPC13XX    | 0
 examples/device/uac2_headset/.skip.MCU_MSP430x5xx | 0
 examples/device/uac2_headset/.skip.MCU_STM32L0    | 0
 4 files changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_LPC11UXX
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_LPC13XX
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_MSP430x5xx
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_STM32L0

diff --git a/examples/device/uac2_headset/.skip.MCU_LPC11UXX b/examples/device/uac2_headset/.skip.MCU_LPC11UXX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_LPC13XX b/examples/device/uac2_headset/.skip.MCU_LPC13XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_MSP430x5xx b/examples/device/uac2_headset/.skip.MCU_MSP430x5xx
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_STM32L0 b/examples/device/uac2_headset/.skip.MCU_STM32L0
deleted file mode 100644
index e69de29bb..000000000

From 8a42cb36613fdee4427aa6d4f61451310a821bf6 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 1 Jul 2021 21:41:19 +0200
Subject: [PATCH 0166/2085] Prevent overflow noise

---
 examples/device/uac2_headset/src/main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index f7d20a607..b459bc2a8 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -423,7 +423,7 @@ void audio_task(void)
         // Combine two channels into one
         int32_t left = *src++;
         int32_t right = *src++;
-        *dst++ = (int16_t)((left + right) / 2);
+        *dst++ = (left >> 1) + (right >> 1);
       }
       tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
       spk_data_size = 0;
@@ -438,7 +438,7 @@ void audio_task(void)
         // Combine two channels into one
         int32_t left = *src++;
         int32_t right = *src++;
-        *dst++ = (int32_t)((left + right) / 2) & 0xffffff00;
+        *dst++ = ((left >> 1) + (right >> 1)) & 0xffffff00;
       }
       tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
       spk_data_size = 0;

From 449936c0f11ea72dd969c8bb353b0f58814f7bc6 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 2 Jul 2021 21:51:54 +0200
Subject: [PATCH 0167/2085] more uac fixes,

---
 src/class/audio/audio.h        |  2 +-
 src/class/audio/audio_device.c | 50 +++++++++++++++++-----------------
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h
index 936f09104..238295d25 100644
--- a/src/class/audio/audio.h
+++ b/src/class/audio/audio.h
@@ -489,7 +489,7 @@ typedef enum
   AUDIO_DATA_FORMAT_TYPE_I_IEEE_FLOAT     = (uint32_t) (1 << 2),
   AUDIO_DATA_FORMAT_TYPE_I_ALAW           = (uint32_t) (1 << 3),
   AUDIO_DATA_FORMAT_TYPE_I_MULAW          = (uint32_t) (1 << 4),
-  AUDIO_DATA_FORMAT_TYPE_I_RAW_DATA       = 0x100000000,
+  AUDIO_DATA_FORMAT_TYPE_I_RAW_DATA       = 0x80000000,
 } audio_data_format_type_I_t;
 
 /// All remaining definitions are taken from the descriptor descriptions in the UAC2 main specification
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 3e05b3763..31b318c3f 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -102,19 +102,19 @@
 // EP IN software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
 #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_in_ff_mutex_wr_1;                                                             // No need for read mutex as only USB driver reads from FIFO
 #endif
 #endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_in_ff_mutex_wr_2;                                                             // No need for read mutex as only USB driver reads from FIFO
 #endif
 #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_in_ff_mutex_wr_3;                                                             // No need for read mutex as only USB driver reads from FIFO
 #endif
@@ -126,32 +126,32 @@ osal_mutex_def_t ep_in_ff_mutex_wr_3;
 // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING)
 #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
 #endif
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
 #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 
 // EP OUT software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
 #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_out_ff_mutex_rd_1;                                                            // No need for write mutex as only USB driver writes into FIFO
 #endif
 #endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_out_ff_mutex_rd_2;                                                            // No need for write mutex as only USB driver writes into FIFO
 #endif
 #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t ep_out_ff_mutex_rd_3;                                                            // No need for write mutex as only USB driver writes into FIFO
 #endif
@@ -163,52 +163,52 @@ osal_mutex_def_t ep_out_ff_mutex_rd_3;
 // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
 #endif
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
 #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 
 // Control buffers
-CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
 #if CFG_TUD_AUDIO > 1
-CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
 #endif
 #if CFG_TUD_AUDIO > 2
-CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
 #endif
 
 // Active alternate setting of interfaces
-CFG_TUSB_MEM_ALIGN uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_N_AS_INT > 0
-CFG_TUSB_MEM_ALIGN uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_N_AS_INT > 0
-CFG_TUSB_MEM_ALIGN uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 #endif
 
 // Software encoding/decoding support FIFOs
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
 #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
 tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
 #endif
 #endif
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
 tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
 #endif
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
 tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
@@ -218,21 +218,21 @@ osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
 #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
 tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
 #endif
 #endif
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
 tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
 #endif
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
 tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
 #if CFG_FIFO_MUTEX
 osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
@@ -294,7 +294,7 @@ typedef struct
 
   // Audio control interrupt buffer - no FIFO - 6 Bytes according to UAC 2 specification (p. 74)
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-  CFG_TUSB_MEM_ALIGN uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
+  CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
 #endif
 
   // Decoding parameters - parameters are set when alternate AS interface is set by host

From 090859bf424e910002fff7dc9195d38d6c22ae1f Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 2 Jul 2021 23:44:46 +0200
Subject: [PATCH 0168/2085] Fix speed detection

---
 src/class/audio/audio_device.c | 27 ++++++++++++---------------
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 31b318c3f..cc07d5e19 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2223,22 +2223,19 @@ bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
   // Format the feedback value
-  if (_audiod_fct[func_id].rhport == 0)
-  {
-    uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].fb_val;
+#if !TUD_OPT_HIGH_SPEED
+  uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].fb_val;
 
-    // For FS format is 10.14
-    *(fb++) = (feedback >> 2) & 0xFF;
-    *(fb++) = (feedback >> 10) & 0xFF;
-    *(fb++) = (feedback >> 18) & 0xFF;
-    // 4th byte is needed to work correctly with MS Windows
-    *fb = 0;
-  }
-  else
-  {
-    // For HS format is 16.16 as originally demanded
-    _audiod_fct[func_id].fb_val = feedback;
-  }
+  // For FS format is 10.14
+  *(fb++) = (feedback >> 2) & 0xFF;
+  *(fb++) = (feedback >> 10) & 0xFF;
+  *(fb++) = (feedback >> 18) & 0xFF;
+  // 4th byte is needed to work correctly with MS Windows
+  *fb = 0;
+#else
+  // For HS format is 16.16 as originally demanded
+  _audiod_fct[func_id].fb_val = feedback;
+#endif
 
   // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value
   if (!usbd_edpt_busy(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_fb))

From 61fd0e2c1cd60921ea3cc6de01534a1e512aff12 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 3 Jul 2021 10:54:20 +0200
Subject: [PATCH 0169/2085] Delay tud_audio_set_itf_cb call with feedback EP.

---
 src/class/audio/audio_device.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index cc07d5e19..61884f867 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1619,9 +1619,17 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             TU_ASSERT( audio->n_ff_used_rx <= audio->n_rx_supp_ff );
 #endif
 #endif
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+            // In case of asynchronous EP, call Cb after ep_fb is set
+            if (((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.sync != 0x01)
+            {
+              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+            }
+#else
             // Invoke callback
             if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
-
+#endif
             // Prepare for incoming data
 #if USE_LINEAR_BUFFER_RX
             TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false);

From 1c8b685457aee291f8352003c7ca7b852c412982 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sun, 4 Jul 2021 00:19:33 +0200
Subject: [PATCH 0170/2085] Move audio_control_request_t to audio.h

---
 examples/device/uac2_headset/src/main.c | 26 ------------------------
 src/class/audio/audio.h                 | 27 +++++++++++++++++++++++++
 2 files changed, 27 insertions(+), 26 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index b459bc2a8..ba27350b4 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -142,32 +142,6 @@ void tud_resume_cb(void)
   blink_interval_ms = BLINK_MOUNTED;
 }
 
-typedef struct TU_ATTR_PACKED
-{
-  union
-  {
-    struct TU_ATTR_PACKED
-    {
-      uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.
-      uint8_t type      :  2; ///< Request type tusb_request_type_t.
-      uint8_t direction :  1; ///< Direction type. tusb_dir_t
-    } bmRequestType_bit;
-
-    uint8_t bmRequestType;
-  };
-
-  uint8_t bRequest;  ///< Request type audio_cs_req_t
-  uint8_t bChannelNumber;
-  uint8_t bControlSelector;
-  union
-  {
-    uint8_t bInterface;
-    uint8_t bEndpoint;
-  };
-  uint8_t bEntityID;
-  uint16_t wLength;
-} audio_control_request_t;
-
 // Helper for clock get requests
 static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t const *request)
 {
diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h
index 238295d25..f99061eae 100644
--- a/src/class/audio/audio.h
+++ b/src/class/audio/audio.h
@@ -823,6 +823,33 @@ typedef struct TU_ATTR_PACKED
   uint16_t wLockDelay        ; ///< Indicates the time it takes this endpoint to reliably lock its internal clock recovery circuitry. Units used depend on the value of the bLockDelayUnits field.
 } audio_desc_cs_as_iso_data_ep_t;
 
+// 5.2.2 Control Request Layout
+typedef struct TU_ATTR_PACKED
+{
+    union
+    {
+        struct TU_ATTR_PACKED
+        {
+            uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.
+            uint8_t type      :  2; ///< Request type tusb_request_type_t.
+            uint8_t direction :  1; ///< Direction type. tusb_dir_t
+        } bmRequestType_bit;
+        
+        uint8_t bmRequestType;
+    };
+    
+    uint8_t bRequest;  ///< Request type audio_cs_req_t
+    uint8_t bChannelNumber;
+    uint8_t bControlSelector;
+    union
+    {
+        uint8_t bInterface;
+        uint8_t bEndpoint;
+    };
+    uint8_t bEntityID;
+    uint16_t wLength;
+} audio_control_request_t;
+
 //// 5.2.3 Control Request Parameter Block Layout
 
 // 5.2.3.1 1-byte Control CUR Parameter Block

From 98d921c4b3657e473f2231857bb6c82ef567b0e3 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sun, 4 Jul 2021 15:10:45 +0200
Subject: [PATCH 0171/2085] Better handling tud_audio_set_itf_cb with FB.

---
 src/class/audio/audio_device.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 61884f867..c7b8b8519 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1622,7 +1622,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
             // In case of asynchronous EP, call Cb after ep_fb is set
-            if (((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.sync != 0x01)
+            if (!(((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.sync == 0x01 && audio->ep_fb == 0))
             {
               if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
             }
@@ -1643,8 +1643,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
           {
             audio->ep_fb = ep_addr;
 
-            // Invoke callback
-            if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+            // Invoke callback after ep_out is set
+            if (audio->ep_out != 0)
+            {
+              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+            }
           }
 #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -1938,8 +1941,12 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     {
       if (tud_audio_fb_done_cb) TU_VERIFY(tud_audio_fb_done_cb(rhport));
 
-      // Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent
-      return audiod_fb_send(rhport, &_audiod_fct[func_id]);
+      // Schedule a transmit with the new value if EP is not busy 
+      if (!usbd_edpt_busy(rhport, _audiod_fct[func_id].ep_fb))
+      {
+        // Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent
+        return audiod_fb_send(rhport, &_audiod_fct[func_id]);
+      }
     }
 #endif
 #endif

From e2617dc91a9aa8764ad4d60c9d4ba9d54d85c73e Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sun, 4 Jul 2021 19:56:13 +0200
Subject: [PATCH 0172/2085] Skip MCU

---
 examples/device/uac2_headset/.skip.MCU_LPC11UXX | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 examples/device/uac2_headset/.skip.MCU_LPC11UXX

diff --git a/examples/device/uac2_headset/.skip.MCU_LPC11UXX b/examples/device/uac2_headset/.skip.MCU_LPC11UXX
new file mode 100644
index 000000000..e69de29bb

From b68c65faeef0d23ed4196b7a9211845f470a6a96 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sun, 4 Jul 2021 20:22:38 +0200
Subject: [PATCH 0173/2085] Skip MCU

---
 examples/device/uac2_headset/.skip.MCU_LPC13XX | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 examples/device/uac2_headset/.skip.MCU_LPC13XX

diff --git a/examples/device/uac2_headset/.skip.MCU_LPC13XX b/examples/device/uac2_headset/.skip.MCU_LPC13XX
new file mode 100644
index 000000000..e69de29bb

From dfe410ea8beb15b4d85320efeb059f42be647ea6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 5 Jul 2021 12:38:15 +0700
Subject: [PATCH 0174/2085] fix ci build, address review comment

---
 src/class/dfu/dfu_device.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index df731ee50..c696d70a2 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -247,9 +247,8 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
 
 static uint16_t dfu_req_upload(uint8_t rhport, tusb_control_request_t const * request, uint16_t block_num, uint16_t wLength)
 {
-  TU_VERIFY( wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
+  TU_VERIFY( wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 0);
   uint16_t retval = tud_dfu_req_upload_data_cb(block_num, (uint8_t *)_dfu_state_ctx.transfer_buf, wLength);
-  TU_ASSERT( retval <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
   tud_control_xfer(rhport, request, _dfu_state_ctx.transfer_buf, retval);
   return retval;
 }
@@ -277,7 +276,7 @@ static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const *
   // if they wish, there still will be the internal control buffer copy to this buffer
   // but this mode would provide zero copy from the class driver to the application
 
-  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
+  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, );
   // setup for data phase
   tud_control_xfer(rhport, request, _dfu_state_ctx.transfer_buf, request->wLength);
 }
@@ -285,7 +284,7 @@ static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const *
 static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request)
 {
   (void) rhport;
-  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
+  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, );
   tud_dfu_req_dnload_data_cb(request->wValue, (uint8_t *)_dfu_state_ctx.transfer_buf, request->wLength);
   _dfu_state_ctx.blk_transfer_in_proc = false;
 }

From 1ff3b76451c446cfd79fb7728f4e457e4dc0d7cb Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 5 Jul 2021 21:27:08 +0900
Subject: [PATCH 0175/2085] remove unnecessary blocking operation. add comments
 why resume event is sent manually.

---
 src/portable/renesas/usba/dcd_usba.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index fa584945e..338d5b0e6 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -553,7 +553,6 @@ void dcd_remote_wakeup(uint8_t rhport)
 {
   (void)rhport;
   USB0.DVSTCTR0.BIT.WKUP = 1;
-  while (USB0.DVSTCTR0.BIT.WKUP) ;
 }
 
 void dcd_connect(uint8_t rhport)
@@ -701,6 +700,11 @@ void dcd_int_handler(uint8_t rhport)
   }
   if (is0 & USB_IS0_SOFR) {
     if (_dcd.suspended) {
+      /* When USB host resumes caused by `dcd_remote_wakeup()`,
+       * RESM interrupt does not rise.
+       * Therefore we need to manually send resume event.
+       * Of course, when USB host resumes on its own,
+       * RESM interrupt rise properly, then this statements are ignored. */
       dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
       _dcd.suspended = 0;
     }

From c2d8ed3fd1fdb722d67a30a6768720c9ed578779 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Mon, 5 Jul 2021 17:56:21 +0200
Subject: [PATCH 0176/2085] Add alt settings support in DFU class.

---
 examples/device/dfu/src/main.c            | 25 ++++++------
 examples/device/dfu/src/usb_descriptors.c |  8 ++--
 src/class/dfu/dfu_device.c                | 46 +++++++++++++++--------
 src/class/dfu/dfu_device.h                | 10 +++--
 src/device/usbd.h                         |  8 ++--
 5 files changed, 56 insertions(+), 41 deletions(-)

diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 1c09066a8..81532ee90 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -115,25 +115,20 @@ void tud_resume_cb(void)
   blink_interval_ms = BLINK_MOUNTED;
 }
 
-// Invoked on DFU_DETACH request to reboot to the bootloader
-void tud_dfu_runtime_reboot_to_dfu_cb(void)
-{
-  blink_interval_ms = BLINK_DFU_MODE;
-}
-
 //--------------------------------------------------------------------+
 // Class callbacks
 //--------------------------------------------------------------------+
-bool tud_dfu_firmware_valid_check_cb(void)
+bool tud_dfu_firmware_valid_check_cb(uint8_t alt)
 {
+  (void) alt;
   printf("    Firmware check\r\n");
   return true;
 }
 
-void tud_dfu_req_dnload_data_cb(uint16_t wBlockNum, uint8_t* data, uint16_t length)
+void tud_dfu_req_dnload_data_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length)
 {
   (void) data;
-  printf("    Received BlockNum %u of length %u\r\n", wBlockNum, length);
+  printf("    Received Alt %u BlockNum %u of length %u\r\n", alt, wBlockNum, length);
 
 #if DFU_VERBOSE
   for(uint16_t i=0; i<length; i++)
@@ -145,8 +140,9 @@ void tud_dfu_req_dnload_data_cb(uint16_t wBlockNum, uint8_t* data, uint16_t leng
   tud_dfu_dnload_complete();
 }
 
-bool tud_dfu_device_data_done_check_cb(void)
+bool tud_dfu_device_data_done_check_cb(uint8_t alt)
 {
+  (void) alt;
   printf("    Host said no more data... Returning true\r\n");
   return true;
 }
@@ -156,15 +152,16 @@ void tud_dfu_abort_cb(void)
   printf("    Host aborted transfer\r\n");
 }
 
-#define UPLOAD_SIZE (29)
-const uint8_t upload_test[UPLOAD_SIZE] = "Hello world from TinyUSB DFU!";
+#define UPLOAD_SIZE 43
+const uint8_t upload_test[2][UPLOAD_SIZE] = {"Hello world from TinyUSB DFU! - Partition 0",
+                                             "Hello world from TinyUSB DFU! - Partition 1"};
 
-uint16_t tud_dfu_req_upload_data_cb(uint16_t block_num, uint8_t* data, uint16_t length)
+uint16_t tud_dfu_req_upload_data_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length)
 {
   (void) block_num;
   (void) length;
 
-  memcpy(data, upload_test, UPLOAD_SIZE);
+  memcpy(data, upload_test[alt], UPLOAD_SIZE);
 
   return UPLOAD_SIZE;
 }
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 8ad64354b..9565da9b2 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -87,7 +87,7 @@ enum
   ITF_NUM_TOTAL
 };
 
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_DFU_MODE_DESC_LEN)
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + 2 * TUD_DFU_MODE_DESC_LEN)
 
 #define FUNC_ATTRS (DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK | DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK)
 
@@ -97,7 +97,8 @@ uint8_t const desc_configuration[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
   // Interface number, string index, attributes, detach timeout, transfer size */
-  TUD_DFU_MODE_DESCRIPTOR(ITF_NUM_DFU_MODE, 0, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE),
+  TUD_DFU_MODE_DESCRIPTOR(ITF_NUM_DFU_MODE, 0, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE),
+  TUD_DFU_MODE_DESCRIPTOR(ITF_NUM_DFU_MODE, 1, 5, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE),
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
@@ -120,7 +121,8 @@ char const* string_desc_arr [] =
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
   "123456",                      // 3: Serials, should use chip ID
-  "TinyUSB DFU",                 // 4: DFU
+  "FLASH",                       // 4: DFU Partition 1
+  "EEPROM",                      // 5: DFU Partition 2
 };
 
 static uint16_t _desc_str[32];
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index c696d70a2..0570b5958 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -46,6 +46,7 @@ typedef struct TU_ATTR_PACKED
     dfu_state_t state;
     uint8_t attrs;
     bool blk_transfer_in_proc;
+    uint8_t alt;
     CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_TRANSFER_BUFFER_SIZE];
 } dfu_state_ctx_t;
 
@@ -165,22 +166,29 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
   (void) rhport;
   (void) max_len;
 
-  // Ensure this is DFU Mode
-  TU_VERIFY((itf_desc->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS) &&
-            (itf_desc->bInterfaceProtocol == DFU_PROTOCOL_DFU), 0);
+  uint16_t drv_len = 0;
+  uint8_t const * p_desc = (uint8_t*)itf_desc;
 
-  uint8_t const * p_desc = tu_desc_next( itf_desc );
-  uint16_t drv_len = sizeof(tusb_desc_interface_t);
-
-  if ( TUSB_DESC_FUNCTIONAL == tu_desc_type(p_desc) )
+  while (max_len)
   {
-    tusb_desc_dfu_functional_t const *dfu_desc = (tusb_desc_dfu_functional_t const *)p_desc;
-    _dfu_state_ctx.attrs = (uint8_t)dfu_desc->bAttributes;
-
+    // Ensure this is DFU Mode
+    TU_VERIFY((((tusb_desc_interface_t const *)p_desc)->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS) &&
+              (((tusb_desc_interface_t const *)p_desc)->bInterfaceProtocol == DFU_PROTOCOL_DFU), drv_len);
+  
+    p_desc = tu_desc_next( p_desc );
     drv_len += tu_desc_len(p_desc);
-    p_desc   = tu_desc_next(p_desc);
-  }
 
+    if ( TUSB_DESC_FUNCTIONAL == tu_desc_type(p_desc) )
+    {
+      tusb_desc_dfu_functional_t const *dfu_desc = (tusb_desc_dfu_functional_t const *)p_desc;
+      _dfu_state_ctx.attrs = (uint8_t)dfu_desc->bAttributes;
+
+      drv_len += tu_desc_len(p_desc);
+      p_desc   = tu_desc_next(p_desc);
+    }
+
+    max_len -= drv_len;
+  }
   return drv_len;
 }
 
@@ -200,6 +208,8 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
     if ( TUSB_REQ_TYPE_STANDARD == request->bmRequestType_bit.type &&
          TUSB_REQ_SET_INTERFACE == request->bRequest )
     {
+      // Save Alt interface
+      _dfu_state_ctx.alt = request->wValue;
       tud_control_status(rhport, request);
       return true;
     }
@@ -248,7 +258,11 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
 static uint16_t dfu_req_upload(uint8_t rhport, tusb_control_request_t const * request, uint16_t block_num, uint16_t wLength)
 {
   TU_VERIFY( wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 0);
-  uint16_t retval = tud_dfu_req_upload_data_cb(block_num, (uint8_t *)_dfu_state_ctx.transfer_buf, wLength);
+  uint16_t retval = 0;
+  if (tud_dfu_req_upload_data_cb)
+  {
+    tud_dfu_req_upload_data_cb(_dfu_state_ctx.alt, block_num, (uint8_t *)_dfu_state_ctx.transfer_buf, wLength);
+  }
   tud_control_xfer(rhport, request, _dfu_state_ctx.transfer_buf, retval);
   return retval;
 }
@@ -285,7 +299,7 @@ static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const *
 {
   (void) rhport;
   TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, );
-  tud_dfu_req_dnload_data_cb(request->wValue, (uint8_t *)_dfu_state_ctx.transfer_buf, request->wLength);
+  tud_dfu_req_dnload_data_cb(_dfu_state_ctx.alt, request->wValue, (uint8_t *)_dfu_state_ctx.transfer_buf, request->wLength);
   _dfu_state_ctx.blk_transfer_in_proc = false;
 }
 
@@ -426,7 +440,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
               _dfu_state_ctx.blk_transfer_in_proc = true;
               dfu_req_dnload_setup(rhport, request);
             } else {
-              if ( tud_dfu_device_data_done_check_cb() )
+              if ( tud_dfu_device_data_done_check_cb(_dfu_state_ctx.alt) )
               {
                 _dfu_state_ctx.state = DFU_MANIFEST_SYNC;
                 tud_control_status(rhport, request);
@@ -481,7 +495,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
             _dfu_state_ctx.state = DFU_MANIFEST;
             dfu_req_getstatus_reply(rhport, request);
           } else {
-            if ( tud_dfu_firmware_valid_check_cb() )
+            if ( tud_dfu_firmware_valid_check_cb(_dfu_state_ctx.alt) )
             {
               _dfu_state_ctx.state = DFU_IDLE;
             }
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index 9a09a46b1..d5bc88ab2 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -39,13 +39,14 @@
 //--------------------------------------------------------------------+
 // Invoked during DFU_MANIFEST_SYNC get status request to check if firmware
 // is valid
-bool tud_dfu_firmware_valid_check_cb(void);
+bool tud_dfu_firmware_valid_check_cb(uint8_t alt);
 
 // Invoked when a DFU_DNLOAD request is received
 // This callback takes the wBlockNum chunk of length length and provides it
 // to the application at the data pointer.  This data is only valid for this
 // call, so the app must use it not or copy it.
-void tud_dfu_req_dnload_data_cb(uint16_t wBlockNum, uint8_t* data, uint16_t length);
+// alt is used as the partition number, in order to multiple partitions like FLASH, EEPROM, etc.
+void tud_dfu_req_dnload_data_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length);
 
 // Must be called when the application is done using the last block of data
 // provided by tud_dfu_req_dnload_data_cb
@@ -56,7 +57,7 @@ void tud_dfu_dnload_complete(void);
 // Return true if the application agrees there is no more data
 // Return false if the device disagrees, which will stall the pipe, and the Host
 //              should initiate a recovery procedure
-bool tud_dfu_device_data_done_check_cb(void);
+bool tud_dfu_device_data_done_check_cb(uint8_t alt);
 
 // Invoked when the Host has terminated a download or upload transfer
 TU_ATTR_WEAK void tud_dfu_abort_cb(void);
@@ -64,7 +65,8 @@ TU_ATTR_WEAK void tud_dfu_abort_cb(void);
 // Invoked when a DFU_UPLOAD request is received
 // This callback must populate data with up to length bytes
 // Return the number of bytes to write
-uint16_t tud_dfu_req_upload_data_cb(uint16_t block_num, uint8_t* data, uint16_t length);
+// alt is used as the partition number, in order to multiple partitions like FLASH, EEPROM, etc.
+TU_ATTR_WEAK uint16_t tud_dfu_req_upload_data_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length);
 
 //--------------------------------------------------------------------+
 // Internal Class Driver API
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 3857295d7..41c78de10 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -603,11 +603,11 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 // Length of template descriptr: 18 bytes
 #define TUD_DFU_MODE_DESC_LEN (9 + 9)
 
-// DFU runtime descriptor
-// Interface number, string index, attributes, detach timeout, transfer size
-#define TUD_DFU_MODE_DESCRIPTOR(_itfnum, _stridx, _attr, _timeout, _xfer_size) \
+// DFU mode descriptor
+// Interface number, alt settings, string index, attributes, detach timeout, transfer size
+#define TUD_DFU_MODE_DESCRIPTOR(_itfnum, _alt, _stridx, _attr, _timeout, _xfer_size) \
   /* Interface */ \
-  9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx, \
+  9, TUSB_DESC_INTERFACE, _itfnum, _alt, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx, \
   /* Function */ \
   9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
 

From c2b9ac9dd415505350c40f6830c1d211de67c342 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Mon, 5 Jul 2021 17:57:23 +0200
Subject: [PATCH 0177/2085] Fix ATTR_MANIFESTATION_TOLERANT logic.

---
 src/class/dfu/dfu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 0570b5958..9eafca359 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -310,7 +310,7 @@ void tud_dfu_dnload_complete(void)
     _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
   } else if (_dfu_state_ctx.state == DFU_MANIFEST)
   {
-    _dfu_state_ctx.state = ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) != 0)
+    _dfu_state_ctx.state = ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
                            ? DFU_MANIFEST_WAIT_RESET : DFU_MANIFEST_SYNC;
   }
 }
@@ -490,7 +490,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_GETSTATUS:
         {
-          if ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) != 0)
+          if ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
           {
             _dfu_state_ctx.state = DFU_MANIFEST;
             dfu_req_getstatus_reply(rhport, request);

From 05a1b854ffcebe8144481a8af9e447d0eac2ae1f Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Mon, 5 Jul 2021 21:00:04 +0200
Subject: [PATCH 0178/2085] ENCODE -> DECODE

---
 src/class/audio/audio_device.c | 30 ++++++++++++------------------
 1 file changed, 12 insertions(+), 18 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index c7b8b8519..97a9c495e 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1481,9 +1481,14 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     audio->ep_in_as_intf_num = 0;
     usbd_edpt_close(rhport, audio->ep_in);
 
-#if !CFG_TUD_AUDIO_ENABLE_ENCODING
     // Clear FIFOs, since data is no longer valid
+#if !CFG_TUD_AUDIO_ENABLE_ENCODING
     tu_fifo_clear(&audio->ep_in_ff);
+#else
+    for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
+    {
+      tu_fifo_clear(&audio->tx_supp_ff[cnt]);
+    }
 #endif
     
     // Invoke callback - can be used to stop data sampling
@@ -1491,14 +1496,6 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
     audio->ep_in = 0;                           // Necessary?
 
-    // Clear support FIFOs if used
-#if CFG_TUD_AUDIO_ENABLE_ENCODING
-    for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
-    {
-      tu_fifo_clear(&audio->tx_supp_ff[cnt]);
-    }
-#endif
-
   }
 #endif
 
@@ -1508,9 +1505,14 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     audio->ep_out_as_intf_num = 0;
     usbd_edpt_close(rhport, audio->ep_out);
 
-#if !CFG_TUD_AUDIO_ENABLE_ENCODING
     // Clear FIFOs, since data is no longer valid
+#if !CFG_TUD_AUDIO_ENABLE_DECODING
     tu_fifo_clear(&audio->ep_out_ff);
+#else
+    for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++)
+    {
+      tu_fifo_clear(&audio->rx_supp_ff[cnt]);
+    }
 #endif
 
     // Invoke callback - can be used to stop data sampling
@@ -1518,14 +1520,6 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
     audio->ep_out = 0;                          // Necessary?
 
-    // Clear support FIFOs if used
-#if CFG_TUD_AUDIO_ENABLE_DECODING
-    for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++)
-    {
-      tu_fifo_clear(&audio->rx_supp_ff[cnt]);
-    }
-#endif
-
     // Close corresponding feedback EP
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
     usbd_edpt_close(rhport, audio->ep_fb);

From 82d355aefe5251f6dd15a7406920efaf516df705 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 6 Jul 2021 00:25:00 +0200
Subject: [PATCH 0179/2085] - Remove alt_setting alignment

---
 src/class/audio/audio_device.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 97a9c495e..f6e6e13f4 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -183,12 +183,12 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_
 #endif
 
 // Active alternate setting of interfaces
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
+uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_N_AS_INT > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
+uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
 #endif
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_N_AS_INT > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
+uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 #endif
 
 // Software encoding/decoding support FIFOs

From 72f916423e85083a090186ecc05a6a5b8962685a Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 6 Jul 2021 10:56:13 +0200
Subject: [PATCH 0180/2085] Fix copy byte count

---
 src/class/audio/audio_device.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index f6e6e13f4..404d28817 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -643,7 +643,6 @@ static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, u
 
   // Determine amount of samples
   uint8_t const n_ff_used               = audio->n_ff_used_rx;
-  uint16_t const nBytesToCopy           = audio->n_channels_per_ff_rx * audio->n_bytes_per_sampe_rx;
   uint16_t const nBytesPerFFToRead      = n_bytes_received / n_ff_used;
   uint8_t cnt_ff;
 
@@ -662,14 +661,14 @@ static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, u
       info.len_lin = tu_min16(nBytesPerFFToRead, info.len_lin);
       src = &audio->lin_buf_out[cnt_ff*audio->n_channels_per_ff_rx * audio->n_bytes_per_sampe_rx];
       dst_end = info.ptr_lin + info.len_lin;
-      src = audiod_interleaved_copy_bytes_fast_decode(nBytesToCopy, info.ptr_lin, dst_end, src, n_ff_used);
+      src = audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sampe_rx, info.ptr_lin, dst_end, src, n_ff_used);
 
       // Handle wrapped part of FIFO
       info.len_wrap = tu_min16(nBytesPerFFToRead - info.len_lin, info.len_wrap);
       if (info.len_wrap != 0)
       {
         dst_end = info.ptr_wrap + info.len_wrap;
-        audiod_interleaved_copy_bytes_fast_decode(nBytesToCopy, info.ptr_wrap, dst_end, src, n_ff_used);
+        audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sampe_rx, info.ptr_wrap, dst_end, src, n_ff_used);
       }
       tu_fifo_advance_write_pointer(&audio->rx_supp_ff[cnt_ff], info.len_lin + info.len_wrap);
     }
@@ -994,7 +993,7 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
     {
       info.len_lin = tu_min16(nBytesPerFFToSend, info.len_lin);       // Limit up to desired length
       src_end = (uint8_t *)info.ptr_lin + info.len_lin;
-      dst = audiod_interleaved_copy_bytes_fast_encode(nBytesToCopy, info.ptr_lin, src_end, dst, n_ff_used);
+      dst = audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sampe_tx, info.ptr_lin, src_end, dst, n_ff_used);
 
       // Limit up to desired length
       info.len_wrap = tu_min16(nBytesPerFFToSend - info.len_lin, info.len_wrap);
@@ -1003,7 +1002,7 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
       if (info.len_wrap != 0)
       {
         src_end = (uint8_t *)info.ptr_wrap + info.len_wrap;
-        audiod_interleaved_copy_bytes_fast_encode(nBytesToCopy, info.ptr_wrap, src_end, dst, n_ff_used);
+        audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sampe_tx, info.ptr_wrap, src_end, dst, n_ff_used);
       }
 
       tu_fifo_advance_read_pointer(&audio->tx_supp_ff[cnt_ff], info.len_lin + info.len_wrap);

From cf4220a9fb24279b423656257cea39b3ab68aa67 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 6 Jul 2021 18:03:05 +0200
Subject: [PATCH 0181/2085] Update

---
 examples/device/dfu/src/tusb_config.h |  1 +
 src/class/dfu/dfu_device.c            |  3 +++
 src/class/dfu/dfu_device.h            | 11 +++++++++--
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 90e90b2e4..0df46c14e 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -76,6 +76,7 @@
 #define CFG_TUD_ENDPOINT0_SIZE    64
 #endif
 
+// DFU buffer size, must to be set to the largest buffer size used by an any given storage type
 #define CFG_TUD_DFU_TRANSFER_BUFFER_SIZE    4096
 
 //------------- CLASS -------------//
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 9eafca359..a186e9140 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -147,6 +147,7 @@ void dfu_moded_init(void)
   _dfu_state_ctx.status = DFU_STATUS_OK;
   _dfu_state_ctx.attrs = 0;
   _dfu_state_ctx.blk_transfer_in_proc = false;
+  _dfu_state_ctx.alt = 0;
 
   dfu_debug_print_context();
 }
@@ -158,6 +159,8 @@ void dfu_moded_reset(uint8_t rhport)
   _dfu_state_ctx.state = DFU_IDLE;
   _dfu_state_ctx.status = DFU_STATUS_OK;
   _dfu_state_ctx.blk_transfer_in_proc = false;
+  _dfu_state_ctx.alt = 0;
+
   dfu_debug_print_context();
 }
 
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index d5bc88ab2..c5c1ede28 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -33,6 +33,13 @@
   extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Class Driver Default Configure & Validation
+//--------------------------------------------------------------------+
+
+#if !defined(CFG_TUD_DFU_TRANSFER_BUFFER_SIZE)
+  #error " CFG_TUD_DFU_TRANSFER_BUFFER_SIZE must be defined, it have to be set to the largest buffer size used by an any given storage type"
+#endif
 
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
@@ -45,7 +52,7 @@ bool tud_dfu_firmware_valid_check_cb(uint8_t alt);
 // This callback takes the wBlockNum chunk of length length and provides it
 // to the application at the data pointer.  This data is only valid for this
 // call, so the app must use it not or copy it.
-// alt is used as the partition number, in order to multiple partitions like FLASH, EEPROM, etc.
+// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 void tud_dfu_req_dnload_data_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length);
 
 // Must be called when the application is done using the last block of data
@@ -65,7 +72,7 @@ TU_ATTR_WEAK void tud_dfu_abort_cb(void);
 // Invoked when a DFU_UPLOAD request is received
 // This callback must populate data with up to length bytes
 // Return the number of bytes to write
-// alt is used as the partition number, in order to multiple partitions like FLASH, EEPROM, etc.
+// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 TU_ATTR_WEAK uint16_t tud_dfu_req_upload_data_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length);
 
 //--------------------------------------------------------------------+

From bc49ee7f2fc74932c332520b0fd8eccefbae659a Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 7 Jul 2021 11:55:36 +0200
Subject: [PATCH 0182/2085] Better alt settings support

---
 src/class/dfu/dfu_device.c | 92 +++++++++++++++++++++++++++-----------
 src/class/dfu/dfu_device.h |  7 ++-
 2 files changed, 72 insertions(+), 27 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index a186e9140..f6fcb1339 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -37,6 +37,8 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+#define DFU_INTF_UNUSED 0xFF
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
@@ -44,9 +46,10 @@ typedef struct TU_ATTR_PACKED
 {
     dfu_device_status_t status;
     dfu_state_t state;
-    uint8_t attrs;
+    uint8_t attrs[CFG_TUD_DFU_ATL_MAX];
     bool blk_transfer_in_proc;
     uint8_t alt;
+    uint8_t intf;
     CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_TRANSFER_BUFFER_SIZE];
 } dfu_state_ctx_t;
 
@@ -145,9 +148,13 @@ void dfu_moded_init(void)
 {
   _dfu_state_ctx.state = DFU_IDLE;
   _dfu_state_ctx.status = DFU_STATUS_OK;
-  _dfu_state_ctx.attrs = 0;
+  for (uint8_t i = 0; i < CFG_TUD_DFU_ATL_MAX; i++)
+  {
+    _dfu_state_ctx.attrs[i] = 0;
+  }
   _dfu_state_ctx.blk_transfer_in_proc = false;
   _dfu_state_ctx.alt = 0;
+  _dfu_state_ctx.intf = DFU_INTF_UNUSED;
 
   dfu_debug_print_context();
 }
@@ -158,8 +165,13 @@ void dfu_moded_reset(uint8_t rhport)
 
   _dfu_state_ctx.state = DFU_IDLE;
   _dfu_state_ctx.status = DFU_STATUS_OK;
+  for (uint8_t i = 0; i < CFG_TUD_DFU_ATL_MAX; i++)
+  {
+    _dfu_state_ctx.attrs[i] = 0;
+  }
   _dfu_state_ctx.blk_transfer_in_proc = false;
   _dfu_state_ctx.alt = 0;
+  _dfu_state_ctx.intf = DFU_INTF_UNUSED;
 
   dfu_debug_print_context();
 }
@@ -167,32 +179,55 @@ void dfu_moded_reset(uint8_t rhport)
 uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
 {
   (void) rhport;
-  (void) max_len;
 
-  uint16_t drv_len = 0;
-  uint8_t const * p_desc = (uint8_t*)itf_desc;
+  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_dfu_functional_t);
 
-  while (max_len)
+  uint8_t const *p_desc = (uint8_t const *)itf_desc;
+
+  uint16_t total_len = 0;
+  
+  uint8_t last_alt = 0;
+
+  while(max_len >= drv_len)
   {
     // Ensure this is DFU Mode
     TU_VERIFY((((tusb_desc_interface_t const *)p_desc)->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS) &&
-              (((tusb_desc_interface_t const *)p_desc)->bInterfaceProtocol == DFU_PROTOCOL_DFU), drv_len);
-  
-    p_desc = tu_desc_next( p_desc );
-    drv_len += tu_desc_len(p_desc);
+              (((tusb_desc_interface_t const *)p_desc)->bInterfaceProtocol == DFU_PROTOCOL_DFU), 0);
 
-    if ( TUSB_DESC_FUNCTIONAL == tu_desc_type(p_desc) )
+    uint8_t const alt = ((tusb_desc_interface_t const *)p_desc)->bAlternateSetting;
+    uint8_t const intf = ((tusb_desc_interface_t const *)p_desc)->bInterfaceNumber;
+
+    if (_dfu_state_ctx.intf == DFU_INTF_UNUSED)
     {
-      tusb_desc_dfu_functional_t const *dfu_desc = (tusb_desc_dfu_functional_t const *)p_desc;
-      _dfu_state_ctx.attrs = (uint8_t)dfu_desc->bAttributes;
-
-      drv_len += tu_desc_len(p_desc);
-      p_desc   = tu_desc_next(p_desc);
+      _dfu_state_ctx.intf = intf;
+    }
+    else
+    {
+      // Only one DFU interface is supported
+      TU_ASSERT(_dfu_state_ctx.intf == intf);
     }
 
+    // CFG_TUD_DFU_ATL_MAX should big enough to hold all alt settings
+    TU_ASSERT(alt < CFG_TUD_DFU_ATL_MAX);
+
+    // Alt should increse by one every time
+    TU_ASSERT(alt == last_alt++);
+
+    //------------- DFU descriptor -------------//
+    p_desc = tu_desc_next(p_desc);
+    TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_FUNCTIONAL, 0);
+
+    _dfu_state_ctx.attrs[alt] = ((tusb_desc_dfu_functional_t const *)p_desc)->bAttributes;
+
+    // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the largest buffer size used by all alt settings
+    TU_ASSERT(((tusb_desc_dfu_functional_t const *)p_desc)->wTransferSize <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
+
+    p_desc = tu_desc_next(p_desc);
     max_len -= drv_len;
+    total_len += drv_len;
   }
-  return drv_len;
+
+  return total_len;
 }
 
 // Invoked when a control transfer occurred on an interface of this class
@@ -208,11 +243,16 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
   if(stage == CONTROL_STAGE_SETUP)
   {
     // dfu-util will try to claim the interface with SET_INTERFACE request before sending DFU request
-    if ( TUSB_REQ_TYPE_STANDARD == request->bmRequestType_bit.type &&
-         TUSB_REQ_SET_INTERFACE == request->bRequest )
+    if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && request->bRequest == TUSB_REQ_SET_INTERFACE)
     {
-      // Save Alt interface
+      // Switch Alt interface
       _dfu_state_ctx.alt = request->wValue;
+
+      // Re-initalise state machine (Necessary ?)
+      _dfu_state_ctx.state = DFU_IDLE;
+      _dfu_state_ctx.status = DFU_STATUS_OK;
+      _dfu_state_ctx.blk_transfer_in_proc = false;
+
       tud_control_status(rhport, request);
       return true;
     }
@@ -226,7 +266,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
     case DFU_REQUEST_DNLOAD:
     {
       if ( (stage == CONTROL_STAGE_ACK)
-           && ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+           && ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
            && (_dfu_state_ctx.state == DFU_DNLOAD_SYNC))
       {
         dfu_req_dnload_reply(rhport, request);
@@ -313,7 +353,7 @@ void tud_dfu_dnload_complete(void)
     _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
   } else if (_dfu_state_ctx.state == DFU_MANIFEST)
   {
-    _dfu_state_ctx.state = ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
+    _dfu_state_ctx.state = ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
                            ? DFU_MANIFEST_WAIT_RESET : DFU_MANIFEST_SYNC;
   }
 }
@@ -331,7 +371,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_DNLOAD:
         {
-          if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+          if( ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
               && (request->wLength > 0) )
           {
             _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
@@ -345,7 +385,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
 
         case DFU_REQUEST_UPLOAD:
         {
-          if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK) != 0) )
+          if( ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK) != 0) )
           {
             _dfu_state_ctx.state = DFU_UPLOAD_IDLE;
             dfu_req_upload(rhport, request, request->wValue, request->wLength);
@@ -436,7 +476,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         {
           case DFU_REQUEST_DNLOAD:
           {
-            if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+            if( ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
                 && (request->wLength > 0) )
             {
               _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
@@ -493,7 +533,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_GETSTATUS:
         {
-          if ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
+          if ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
           {
             _dfu_state_ctx.state = DFU_MANIFEST;
             dfu_req_getstatus_reply(rhport, request);
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index c5c1ede28..6f826152f 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -37,8 +37,13 @@
 // Class Driver Default Configure & Validation
 //--------------------------------------------------------------------+
 
+// Maximum alternate settings (used for different partitons) supported
+#if !defined(CFG_TUD_DFU_ATL_MAX)
+  #define  CFG_TUD_DFU_ATL_MAX  2
+#endif
+
 #if !defined(CFG_TUD_DFU_TRANSFER_BUFFER_SIZE)
-  #error " CFG_TUD_DFU_TRANSFER_BUFFER_SIZE must be defined, it have to be set to the largest buffer size used by an any given storage type"
+  #error "CFG_TUD_DFU_TRANSFER_BUFFER_SIZE must be defined, it has to be set to the largest buffer size used by an any given storage type"
 #endif
 
 //--------------------------------------------------------------------+

From 88478594bc0c5946853567620beb944940f81a1d Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 7 Jul 2021 12:06:41 +0200
Subject: [PATCH 0183/2085] Update comment

---
 src/class/dfu/dfu_device.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index 6f826152f..67d15c3c6 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -49,15 +49,15 @@
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
 //--------------------------------------------------------------------+
-// Invoked during DFU_MANIFEST_SYNC get status request to check if firmware
-// is valid
+// Invoked during DFU_MANIFEST_SYNC get status request to check if firmware is valid
+// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 bool tud_dfu_firmware_valid_check_cb(uint8_t alt);
 
 // Invoked when a DFU_DNLOAD request is received
+// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 // This callback takes the wBlockNum chunk of length length and provides it
 // to the application at the data pointer.  This data is only valid for this
 // call, so the app must use it not or copy it.
-// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 void tud_dfu_req_dnload_data_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length);
 
 // Must be called when the application is done using the last block of data
@@ -66,6 +66,7 @@ void tud_dfu_dnload_complete(void);
 
 // Invoked during the last DFU_DNLOAD request, signifying that the host believes
 // it is done transmitting data.
+// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 // Return true if the application agrees there is no more data
 // Return false if the device disagrees, which will stall the pipe, and the Host
 //              should initiate a recovery procedure
@@ -75,9 +76,9 @@ bool tud_dfu_device_data_done_check_cb(uint8_t alt);
 TU_ATTR_WEAK void tud_dfu_abort_cb(void);
 
 // Invoked when a DFU_UPLOAD request is received
+// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 // This callback must populate data with up to length bytes
 // Return the number of bytes to write
-// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 TU_ATTR_WEAK uint16_t tud_dfu_req_upload_data_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length);
 
 //--------------------------------------------------------------------+

From 3949fb9e8c1b9a9646223e3edf7a0df4f010b5be Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 7 Jul 2021 12:07:10 +0200
Subject: [PATCH 0184/2085] Add DFU_DETACH support

---
 src/class/dfu/dfu_device.c | 7 ++++++-
 src/class/dfu/dfu_device.h | 2 ++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index f6fcb1339..f4edd713a 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -263,6 +263,12 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
 
   switch (request->bRequest)
   {
+    case DFU_REQUEST_DETACH:
+    {
+      tud_control_status(rhport, request);
+      if (tud_dfu_reboot_cb) tud_dfu_reboot_cb();
+      break;
+    }
     case DFU_REQUEST_DNLOAD:
     {
       if ( (stage == CONTROL_STAGE_ACK)
@@ -273,7 +279,6 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
         return true;
       }
     } // fallthrough
-    case DFU_REQUEST_DETACH:
     case DFU_REQUEST_UPLOAD:
     case DFU_REQUEST_GETSTATUS:
     case DFU_REQUEST_CLRSTATUS:
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index 67d15c3c6..53be0005e 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -81,6 +81,8 @@ TU_ATTR_WEAK void tud_dfu_abort_cb(void);
 // Return the number of bytes to write
 TU_ATTR_WEAK uint16_t tud_dfu_req_upload_data_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length);
 
+// Invoked when a DFU_DETACH request is received
+TU_ATTR_WEAK void tud_dfu_reboot_cb(void);
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+

From 71c00432610780f07d0e0776eacdda1186481854 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 7 Jul 2021 12:18:25 +0200
Subject: [PATCH 0185/2085] TU_ASSERT return 0.

---
 src/class/dfu/dfu_device.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index f4edd713a..8bf2e16be 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -204,14 +204,14 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
     else
     {
       // Only one DFU interface is supported
-      TU_ASSERT(_dfu_state_ctx.intf == intf);
+      TU_ASSERT(_dfu_state_ctx.intf == intf, 0);
     }
 
     // CFG_TUD_DFU_ATL_MAX should big enough to hold all alt settings
-    TU_ASSERT(alt < CFG_TUD_DFU_ATL_MAX);
+    TU_ASSERT(alt < CFG_TUD_DFU_ATL_MAX, 0);
 
     // Alt should increse by one every time
-    TU_ASSERT(alt == last_alt++);
+    TU_ASSERT(alt == last_alt++, 0);
 
     //------------- DFU descriptor -------------//
     p_desc = tu_desc_next(p_desc);
@@ -220,7 +220,7 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
     _dfu_state_ctx.attrs[alt] = ((tusb_desc_dfu_functional_t const *)p_desc)->bAttributes;
 
     // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the largest buffer size used by all alt settings
-    TU_ASSERT(((tusb_desc_dfu_functional_t const *)p_desc)->wTransferSize <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
+    TU_ASSERT(((tusb_desc_dfu_functional_t const *)p_desc)->wTransferSize <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 0);
 
     p_desc = tu_desc_next(p_desc);
     max_len -= drv_len;

From 941b02c6a98cd34eb84cf499db9810108871d49b Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 7 Jul 2021 18:02:04 +0200
Subject: [PATCH 0186/2085] Reactor to one functional descriptor.

---
 examples/device/dfu/src/tusb_config.h     |  8 ++--
 examples/device/dfu/src/usb_descriptors.c |  7 ++--
 src/class/dfu/dfu_device.c                | 51 ++++++++++-------------
 src/class/dfu/dfu_device.h                |  7 +---
 src/device/usbd.h                         | 47 +++++++++++++++++----
 5 files changed, 72 insertions(+), 48 deletions(-)

diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 0df46c14e..55aa19922 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -76,14 +76,16 @@
 #define CFG_TUD_ENDPOINT0_SIZE    64
 #endif
 
-// DFU buffer size, must to be set to the largest buffer size used by an any given storage type
-#define CFG_TUD_DFU_TRANSFER_BUFFER_SIZE    4096
-
 //------------- CLASS -------------//
 
 #define CFG_TUD_DFU_RUNTIME 0
 #define CFG_TUD_DFU_MODE    1
 
+// Count of all alt settings, typically it's the partition count (Flash, EEPROM, etc.)
+#define CFG_TUD_DFU_ALT_COUNT               2
+// DFU buffer size, it has to be set to the buffer size used in TUD_DFU_MODE_DESCRIPTOR
+#define CFG_TUD_DFU_TRANSFER_BUFFER_SIZE    4096
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 9565da9b2..200817eb4 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -87,7 +87,7 @@ enum
   ITF_NUM_TOTAL
 };
 
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + 2 * TUD_DFU_MODE_DESC_LEN)
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_DFU_MODE_DESC_LEN)
 
 #define FUNC_ATTRS (DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK | DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK)
 
@@ -96,9 +96,8 @@ uint8_t const desc_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
-  // Interface number, string index, attributes, detach timeout, transfer size */
-  TUD_DFU_MODE_DESCRIPTOR(ITF_NUM_DFU_MODE, 0, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE),
-  TUD_DFU_MODE_DESCRIPTOR(ITF_NUM_DFU_MODE, 1, 5, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE),
+  // Interface number, detach timeout, transfer size, string index 0, [string index 1 ... string index n]
+  TUD_DFU_MODE_DESCRIPTOR(ITF_NUM_DFU_MODE, 0, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 4, 5),
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 8bf2e16be..834648c5a 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -46,7 +46,7 @@ typedef struct TU_ATTR_PACKED
 {
     dfu_device_status_t status;
     dfu_state_t state;
-    uint8_t attrs[CFG_TUD_DFU_ATL_MAX];
+    uint8_t attrs;
     bool blk_transfer_in_proc;
     uint8_t alt;
     uint8_t intf;
@@ -148,10 +148,7 @@ void dfu_moded_init(void)
 {
   _dfu_state_ctx.state = DFU_IDLE;
   _dfu_state_ctx.status = DFU_STATUS_OK;
-  for (uint8_t i = 0; i < CFG_TUD_DFU_ATL_MAX; i++)
-  {
-    _dfu_state_ctx.attrs[i] = 0;
-  }
+  _dfu_state_ctx.attrs = 0;
   _dfu_state_ctx.blk_transfer_in_proc = false;
   _dfu_state_ctx.alt = 0;
   _dfu_state_ctx.intf = DFU_INTF_UNUSED;
@@ -165,10 +162,7 @@ void dfu_moded_reset(uint8_t rhport)
 
   _dfu_state_ctx.state = DFU_IDLE;
   _dfu_state_ctx.status = DFU_STATUS_OK;
-  for (uint8_t i = 0; i < CFG_TUD_DFU_ATL_MAX; i++)
-  {
-    _dfu_state_ctx.attrs[i] = 0;
-  }
+  _dfu_state_ctx.attrs = 0;
   _dfu_state_ctx.blk_transfer_in_proc = false;
   _dfu_state_ctx.alt = 0;
   _dfu_state_ctx.intf = DFU_INTF_UNUSED;
@@ -180,15 +174,15 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
 {
   (void) rhport;
 
-  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_dfu_functional_t);
+  uint16_t const drv_len = sizeof(tusb_desc_interface_t);
 
   uint8_t const *p_desc = (uint8_t const *)itf_desc;
 
   uint16_t total_len = 0;
-  
+
   uint8_t last_alt = 0;
 
-  while(max_len >= drv_len)
+  while(max_len > drv_len)
   {
     // Ensure this is DFU Mode
     TU_VERIFY((((tusb_desc_interface_t const *)p_desc)->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS) &&
@@ -208,25 +202,26 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
     }
 
     // CFG_TUD_DFU_ATL_MAX should big enough to hold all alt settings
-    TU_ASSERT(alt < CFG_TUD_DFU_ATL_MAX, 0);
+    TU_ASSERT(alt < CFG_TUD_DFU_ALT_COUNT, 0);
 
     // Alt should increse by one every time
     TU_ASSERT(alt == last_alt++, 0);
 
-    //------------- DFU descriptor -------------//
-    p_desc = tu_desc_next(p_desc);
-    TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_FUNCTIONAL, 0);
-
-    _dfu_state_ctx.attrs[alt] = ((tusb_desc_dfu_functional_t const *)p_desc)->bAttributes;
-
-    // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the largest buffer size used by all alt settings
-    TU_ASSERT(((tusb_desc_dfu_functional_t const *)p_desc)->wTransferSize <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 0);
-
     p_desc = tu_desc_next(p_desc);
     max_len -= drv_len;
     total_len += drv_len;
   }
 
+  //------------- DFU descriptor -------------//
+  TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_FUNCTIONAL, 0);
+
+  _dfu_state_ctx.attrs = ((tusb_desc_dfu_functional_t const *)p_desc)->bAttributes;
+
+  // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the buffer size used in TUD_DFU_MODE_DESCRIPTOR
+  TU_ASSERT(((tusb_desc_dfu_functional_t const *)p_desc)->wTransferSize <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 0);
+
+  total_len += sizeof(tusb_desc_dfu_functional_t); 
+
   return total_len;
 }
 
@@ -272,7 +267,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
     case DFU_REQUEST_DNLOAD:
     {
       if ( (stage == CONTROL_STAGE_ACK)
-           && ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+           && ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
            && (_dfu_state_ctx.state == DFU_DNLOAD_SYNC))
       {
         dfu_req_dnload_reply(rhport, request);
@@ -358,7 +353,7 @@ void tud_dfu_dnload_complete(void)
     _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
   } else if (_dfu_state_ctx.state == DFU_MANIFEST)
   {
-    _dfu_state_ctx.state = ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
+    _dfu_state_ctx.state = ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
                            ? DFU_MANIFEST_WAIT_RESET : DFU_MANIFEST_SYNC;
   }
 }
@@ -376,7 +371,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_DNLOAD:
         {
-          if( ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+          if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
               && (request->wLength > 0) )
           {
             _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
@@ -390,7 +385,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
 
         case DFU_REQUEST_UPLOAD:
         {
-          if( ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK) != 0) )
+          if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK) != 0) )
           {
             _dfu_state_ctx.state = DFU_UPLOAD_IDLE;
             dfu_req_upload(rhport, request, request->wValue, request->wLength);
@@ -481,7 +476,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         {
           case DFU_REQUEST_DNLOAD:
           {
-            if( ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+            if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
                 && (request->wLength > 0) )
             {
               _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
@@ -538,7 +533,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_GETSTATUS:
         {
-          if ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
+          if ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
           {
             _dfu_state_ctx.state = DFU_MANIFEST;
             dfu_req_getstatus_reply(rhport, request);
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index 53be0005e..f41b4b651 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -37,13 +37,8 @@
 // Class Driver Default Configure & Validation
 //--------------------------------------------------------------------+
 
-// Maximum alternate settings (used for different partitons) supported
-#if !defined(CFG_TUD_DFU_ATL_MAX)
-  #define  CFG_TUD_DFU_ATL_MAX  2
-#endif
-
 #if !defined(CFG_TUD_DFU_TRANSFER_BUFFER_SIZE)
-  #error "CFG_TUD_DFU_TRANSFER_BUFFER_SIZE must be defined, it has to be set to the largest buffer size used by an any given storage type"
+  #error "CFG_TUD_DFU_TRANSFER_BUFFER_SIZE must be defined, it has to be set to the buffer size used in TUD_DFU_MODE_DESCRIPTOR"
 #endif
 
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 41c78de10..fe1863706 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -600,17 +600,50 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Function */ \
   9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
 
-// Length of template descriptr: 18 bytes
-#define TUD_DFU_MODE_DESC_LEN (9 + 9)
+// Maximum alternate settings (used for different partitons) supported
+#ifndef CFG_TUD_DFU_ALT_COUNT
+#define CFG_TUD_DFU_ALT_COUNT 1
+#endif
 
-// DFU mode descriptor
-// Interface number, alt settings, string index, attributes, detach timeout, transfer size
-#define TUD_DFU_MODE_DESCRIPTOR(_itfnum, _alt, _stridx, _attr, _timeout, _xfer_size) \
-  /* Interface */ \
-  9, TUSB_DESC_INTERFACE, _itfnum, _alt, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx, \
+// Length of template descriptor: 18 bytes + number of alternatives * 9
+#define TUD_DFU_MODE_DESC_LEN (9 + (CFG_TUD_DFU_ALT_COUNT) * 9)
+
+/* Primary Interface */
+#define TUD_DFU_MODE_FUNC(_attr, _timeout, _xfer_size) \
   /* Function */ \
   9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
 
+#define TUD_DFU_MODE_ALT(_itfnum, _alt, _stridx) \
+  /* Interface */ \
+  9, TUSB_DESC_INTERFACE, _itfnum, _alt, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx, \
+
+#define _TUD_DFU_FIRST(a, ...) a
+#define _TUD_DFU_REST(a, ...) __VA_ARGS__
+#define _TUD_DFU_COMBINE(...) __VA_ARGS__
+
+#define TUD_DFU_MODE_ALT_1(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 1, _TUD_DFU_FIRST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_2(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 2, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_1(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_3(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 3, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_2(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_4(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 4, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_3(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_5(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 5, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_4(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_6(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 6, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_5(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_7(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 7, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_6(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_8(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 8, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_7(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+
+#define TUD_DFU_MODE_ALTS(_itfnum, ...) \
+  TU_XSTRCAT(TUD_DFU_MODE_ALT_, CFG_TUD_DFU_ALT_COUNT)(_itfnum, __VA_ARGS__)
+
+// Interface number, detach timeout, transfer size, string index 1, [string index 2, string index n]
+#define TUD_DFU_MODE_DESCRIPTOR(_itfnum, _attr, _timeout, _xfer_size, _stridx, ...) \
+  TUD_DFU_MODE_ALTS(_itfnum, _TUD_DFU_COMBINE(_stridx, __VA_ARGS__)) \
+  TUD_DFU_MODE_FUNC(_attr, _timeout, _xfer_size)
 
 //------------- CDC-ECM -------------//
 

From 7e883e0f41a4fdda699bbaf1d64a28d82527b8f9 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Wed, 7 Jul 2021 19:01:00 +0200
Subject: [PATCH 0187/2085] Refactor with one DFU functionnal descriptor

---
 examples/device/dfu/src/tusb_config.h     |  8 ++--
 examples/device/dfu/src/usb_descriptors.c |  7 ++--
 src/class/dfu/dfu_device.c                | 51 ++++++++++-------------
 src/class/dfu/dfu_device.h                |  7 +---
 src/device/usbd.h                         | 47 +++++++++++++++++----
 5 files changed, 72 insertions(+), 48 deletions(-)

diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 0df46c14e..55aa19922 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -76,14 +76,16 @@
 #define CFG_TUD_ENDPOINT0_SIZE    64
 #endif
 
-// DFU buffer size, must to be set to the largest buffer size used by an any given storage type
-#define CFG_TUD_DFU_TRANSFER_BUFFER_SIZE    4096
-
 //------------- CLASS -------------//
 
 #define CFG_TUD_DFU_RUNTIME 0
 #define CFG_TUD_DFU_MODE    1
 
+// Count of all alt settings, typically it's the partition count (Flash, EEPROM, etc.)
+#define CFG_TUD_DFU_ALT_COUNT               2
+// DFU buffer size, it has to be set to the buffer size used in TUD_DFU_MODE_DESCRIPTOR
+#define CFG_TUD_DFU_TRANSFER_BUFFER_SIZE    4096
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 9565da9b2..8c5eee455 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -87,7 +87,7 @@ enum
   ITF_NUM_TOTAL
 };
 
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + 2 * TUD_DFU_MODE_DESC_LEN)
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_DFU_MODE_DESC_LEN)
 
 #define FUNC_ATTRS (DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK | DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK)
 
@@ -96,9 +96,8 @@ uint8_t const desc_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
-  // Interface number, string index, attributes, detach timeout, transfer size */
-  TUD_DFU_MODE_DESCRIPTOR(ITF_NUM_DFU_MODE, 0, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE),
-  TUD_DFU_MODE_DESCRIPTOR(ITF_NUM_DFU_MODE, 1, 5, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE),
+  // Interface number, attributes, detach timeout, transfer size, string index 0, [string index 1 ... string index n]
+  TUD_DFU_MODE_DESCRIPTOR(ITF_NUM_DFU_MODE, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 4, 5),
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 8bf2e16be..834648c5a 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -46,7 +46,7 @@ typedef struct TU_ATTR_PACKED
 {
     dfu_device_status_t status;
     dfu_state_t state;
-    uint8_t attrs[CFG_TUD_DFU_ATL_MAX];
+    uint8_t attrs;
     bool blk_transfer_in_proc;
     uint8_t alt;
     uint8_t intf;
@@ -148,10 +148,7 @@ void dfu_moded_init(void)
 {
   _dfu_state_ctx.state = DFU_IDLE;
   _dfu_state_ctx.status = DFU_STATUS_OK;
-  for (uint8_t i = 0; i < CFG_TUD_DFU_ATL_MAX; i++)
-  {
-    _dfu_state_ctx.attrs[i] = 0;
-  }
+  _dfu_state_ctx.attrs = 0;
   _dfu_state_ctx.blk_transfer_in_proc = false;
   _dfu_state_ctx.alt = 0;
   _dfu_state_ctx.intf = DFU_INTF_UNUSED;
@@ -165,10 +162,7 @@ void dfu_moded_reset(uint8_t rhport)
 
   _dfu_state_ctx.state = DFU_IDLE;
   _dfu_state_ctx.status = DFU_STATUS_OK;
-  for (uint8_t i = 0; i < CFG_TUD_DFU_ATL_MAX; i++)
-  {
-    _dfu_state_ctx.attrs[i] = 0;
-  }
+  _dfu_state_ctx.attrs = 0;
   _dfu_state_ctx.blk_transfer_in_proc = false;
   _dfu_state_ctx.alt = 0;
   _dfu_state_ctx.intf = DFU_INTF_UNUSED;
@@ -180,15 +174,15 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
 {
   (void) rhport;
 
-  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_dfu_functional_t);
+  uint16_t const drv_len = sizeof(tusb_desc_interface_t);
 
   uint8_t const *p_desc = (uint8_t const *)itf_desc;
 
   uint16_t total_len = 0;
-  
+
   uint8_t last_alt = 0;
 
-  while(max_len >= drv_len)
+  while(max_len > drv_len)
   {
     // Ensure this is DFU Mode
     TU_VERIFY((((tusb_desc_interface_t const *)p_desc)->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS) &&
@@ -208,25 +202,26 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
     }
 
     // CFG_TUD_DFU_ATL_MAX should big enough to hold all alt settings
-    TU_ASSERT(alt < CFG_TUD_DFU_ATL_MAX, 0);
+    TU_ASSERT(alt < CFG_TUD_DFU_ALT_COUNT, 0);
 
     // Alt should increse by one every time
     TU_ASSERT(alt == last_alt++, 0);
 
-    //------------- DFU descriptor -------------//
-    p_desc = tu_desc_next(p_desc);
-    TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_FUNCTIONAL, 0);
-
-    _dfu_state_ctx.attrs[alt] = ((tusb_desc_dfu_functional_t const *)p_desc)->bAttributes;
-
-    // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the largest buffer size used by all alt settings
-    TU_ASSERT(((tusb_desc_dfu_functional_t const *)p_desc)->wTransferSize <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 0);
-
     p_desc = tu_desc_next(p_desc);
     max_len -= drv_len;
     total_len += drv_len;
   }
 
+  //------------- DFU descriptor -------------//
+  TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_FUNCTIONAL, 0);
+
+  _dfu_state_ctx.attrs = ((tusb_desc_dfu_functional_t const *)p_desc)->bAttributes;
+
+  // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the buffer size used in TUD_DFU_MODE_DESCRIPTOR
+  TU_ASSERT(((tusb_desc_dfu_functional_t const *)p_desc)->wTransferSize <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 0);
+
+  total_len += sizeof(tusb_desc_dfu_functional_t); 
+
   return total_len;
 }
 
@@ -272,7 +267,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
     case DFU_REQUEST_DNLOAD:
     {
       if ( (stage == CONTROL_STAGE_ACK)
-           && ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+           && ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
            && (_dfu_state_ctx.state == DFU_DNLOAD_SYNC))
       {
         dfu_req_dnload_reply(rhport, request);
@@ -358,7 +353,7 @@ void tud_dfu_dnload_complete(void)
     _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
   } else if (_dfu_state_ctx.state == DFU_MANIFEST)
   {
-    _dfu_state_ctx.state = ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
+    _dfu_state_ctx.state = ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
                            ? DFU_MANIFEST_WAIT_RESET : DFU_MANIFEST_SYNC;
   }
 }
@@ -376,7 +371,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_DNLOAD:
         {
-          if( ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+          if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
               && (request->wLength > 0) )
           {
             _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
@@ -390,7 +385,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
 
         case DFU_REQUEST_UPLOAD:
         {
-          if( ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK) != 0) )
+          if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK) != 0) )
           {
             _dfu_state_ctx.state = DFU_UPLOAD_IDLE;
             dfu_req_upload(rhport, request, request->wValue, request->wLength);
@@ -481,7 +476,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         {
           case DFU_REQUEST_DNLOAD:
           {
-            if( ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+            if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
                 && (request->wLength > 0) )
             {
               _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
@@ -538,7 +533,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_GETSTATUS:
         {
-          if ((_dfu_state_ctx.attrs[_dfu_state_ctx.alt] & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
+          if ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
           {
             _dfu_state_ctx.state = DFU_MANIFEST;
             dfu_req_getstatus_reply(rhport, request);
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index 53be0005e..f41b4b651 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -37,13 +37,8 @@
 // Class Driver Default Configure & Validation
 //--------------------------------------------------------------------+
 
-// Maximum alternate settings (used for different partitons) supported
-#if !defined(CFG_TUD_DFU_ATL_MAX)
-  #define  CFG_TUD_DFU_ATL_MAX  2
-#endif
-
 #if !defined(CFG_TUD_DFU_TRANSFER_BUFFER_SIZE)
-  #error "CFG_TUD_DFU_TRANSFER_BUFFER_SIZE must be defined, it has to be set to the largest buffer size used by an any given storage type"
+  #error "CFG_TUD_DFU_TRANSFER_BUFFER_SIZE must be defined, it has to be set to the buffer size used in TUD_DFU_MODE_DESCRIPTOR"
 #endif
 
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 41c78de10..3d49d4b12 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -600,17 +600,50 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Function */ \
   9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
 
-// Length of template descriptr: 18 bytes
-#define TUD_DFU_MODE_DESC_LEN (9 + 9)
+// Maximum alternate settings (used for different partitons) supported
+#ifndef CFG_TUD_DFU_ALT_COUNT
+#define CFG_TUD_DFU_ALT_COUNT 1
+#endif
 
-// DFU mode descriptor
-// Interface number, alt settings, string index, attributes, detach timeout, transfer size
-#define TUD_DFU_MODE_DESCRIPTOR(_itfnum, _alt, _stridx, _attr, _timeout, _xfer_size) \
-  /* Interface */ \
-  9, TUSB_DESC_INTERFACE, _itfnum, _alt, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx, \
+// Length of template descriptor: 18 bytes + number of alternatives * 9
+#define TUD_DFU_MODE_DESC_LEN (9 + (CFG_TUD_DFU_ALT_COUNT) * 9)
+
+/* Primary Interface */
+#define TUD_DFU_MODE_FUNC(_attr, _timeout, _xfer_size) \
   /* Function */ \
   9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
 
+#define TUD_DFU_MODE_ALT(_itfnum, _alt, _stridx) \
+  /* Interface */ \
+  9, TUSB_DESC_INTERFACE, _itfnum, _alt, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx, \
+
+#define _TUD_DFU_FIRST(a, ...) a
+#define _TUD_DFU_REST(a, ...) __VA_ARGS__
+#define _TUD_DFU_COMBINE(...) __VA_ARGS__
+
+#define TUD_DFU_MODE_ALT_1(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 1, _TUD_DFU_FIRST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_2(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 2, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_1(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_3(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 3, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_2(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_4(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 4, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_3(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_5(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 5, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_4(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_6(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 6, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_5(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_7(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 7, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_6(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define TUD_DFU_MODE_ALT_8(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 8, _TUD_DFU_FIRST(__VA_ARGS__)) \
+  TUD_DFU_MODE_ALT_7(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+
+#define TUD_DFU_MODE_ALTS(_itfnum, ...) \
+  TU_XSTRCAT(TUD_DFU_MODE_ALT_, CFG_TUD_DFU_ALT_COUNT)(_itfnum, __VA_ARGS__)
+
+// Interface number, attributes, detach timeout, transfer size, string index 1, [string index 2, string index n]
+#define TUD_DFU_MODE_DESCRIPTOR(_itfnum, _attr, _timeout, _xfer_size, _stridx, ...) \
+  TUD_DFU_MODE_ALTS(_itfnum, _TUD_DFU_COMBINE(_stridx, __VA_ARGS__)) \
+  TUD_DFU_MODE_FUNC(_attr, _timeout, _xfer_size)
 
 //------------- CDC-ECM -------------//
 

From 2147a31f25e6e848d9ec690d8324a6fa2d1d3127 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 8 Jul 2021 01:10:02 +0200
Subject: [PATCH 0188/2085] Fix wrong blocknum and length

---
 src/class/dfu/dfu_device.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 34472bcdd..6e7ad151b 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -50,6 +50,8 @@ typedef struct TU_ATTR_PACKED
     bool blk_transfer_in_proc;
     uint8_t alt;
     uint8_t intf;
+    uint16_t block;
+    uint16_t length;
     CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_TRANSFER_BUFFER_SIZE];
 } dfu_state_ctx_t;
 
@@ -270,6 +272,8 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
            && ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
            && (_dfu_state_ctx.state == DFU_DNLOAD_SYNC))
       {
+        _dfu_state_ctx.block = request->wValue;
+        _dfu_state_ctx.length = request->wLength;
         return true;
       }
     } // fallthrough
@@ -349,7 +353,7 @@ static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const *
 {
   (void) rhport;
   TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, );
-  tud_dfu_req_dnload_data_cb(_dfu_state_ctx.alt, request->wValue, (uint8_t *)_dfu_state_ctx.transfer_buf, request->wLength);
+  tud_dfu_req_dnload_data_cb(_dfu_state_ctx.alt,_dfu_state_ctx.block, (uint8_t *)_dfu_state_ctx.transfer_buf, _dfu_state_ctx.length);
   _dfu_state_ctx.blk_transfer_in_proc = false;
 }
 

From 2e0d7e87d07346dc1abeeac279c7e7003630ce5a Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 8 Jul 2021 21:57:28 +0900
Subject: [PATCH 0189/2085] add settings for Renesas RX family

---
 examples/device/uac2_headset/src/main.c        |  4 ++++
 examples/device/uac2_headset/src/tusb_config.h | 12 ++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index ba27350b4..790af088f 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -35,7 +35,11 @@
 //--------------------------------------------------------------------+
 
 // List of supported sample rates
+#if defined(__RX__)
+const uint32_t sample_rates[]       = {44100, 48000};
+#else
 const uint32_t sample_rates[]       = {44100, 48000, 88200, 96000};
+#endif
 uint32_t       current_sample_rate  = 44100;
 
 #define N_SAMPLE_RATES  TU_ARRAY_SIZE(sample_rates)
diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index d955a746d..e8d93f56a 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -100,7 +100,11 @@ extern "C" {
 #define CFG_TUD_AUDIO_FUNC_1_N_FORMATS                               2
 
 // Audio format type I specifications
+#if defined(__RX__)
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         48000     // 16bit/48kHz is the best quality for Renesas RX
+#else
 #define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000     // 24bit/96kHz is the best quality for full-speed, high-speed is needed beyond this
+#endif
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                           1
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                           2
 
@@ -110,11 +114,19 @@ extern "C" {
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX          2
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX                  16
 
+#if defined(__RX__)
+// 8bit in 8bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX          1
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX                  8
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX          1
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX                  8
+#else
 // 24bit in 32bit slots
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX          4
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX                  24
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX          4
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX                  24
+#endif
 
 // EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
 #define CFG_TUD_AUDIO_ENABLE_EP_IN                1

From a0691a4fd426f01915a7ce6452b5367aa667fb0b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jul 2021 18:48:33 +0700
Subject: [PATCH 0190/2085] update dfu_moded_open

---
 src/class/dfu/dfu_device.c | 62 +++++++++++++-------------------------
 1 file changed, 21 insertions(+), 41 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 6e7ad151b..04f086e0e 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -49,7 +49,6 @@ typedef struct TU_ATTR_PACKED
     uint8_t attrs;
     bool blk_transfer_in_proc;
     uint8_t alt;
-    uint8_t intf;
     uint16_t block;
     uint16_t length;
     CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_TRANSFER_BUFFER_SIZE];
@@ -153,7 +152,6 @@ void dfu_moded_init(void)
   _dfu_state_ctx.attrs = 0;
   _dfu_state_ctx.blk_transfer_in_proc = false;
   _dfu_state_ctx.alt = 0;
-  _dfu_state_ctx.intf = DFU_INTF_UNUSED;
 
   dfu_debug_print_context();
 }
@@ -167,7 +165,6 @@ void dfu_moded_reset(uint8_t rhport)
   _dfu_state_ctx.attrs = 0;
   _dfu_state_ctx.blk_transfer_in_proc = false;
   _dfu_state_ctx.alt = 0;
-  _dfu_state_ctx.intf = DFU_INTF_UNUSED;
 
   dfu_debug_print_context();
 }
@@ -176,55 +173,38 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
 {
   (void) rhport;
 
-  uint16_t const drv_len = sizeof(tusb_desc_interface_t);
+  //------------- Interface (with Alt) descriptor -------------//
+  uint8_t const itf_num = itf_desc->bInterfaceNumber;
+  uint8_t alt_count = 0;
 
-  uint8_t const *p_desc = (uint8_t const *)itf_desc;
-
-  uint16_t total_len = 0;
-
-  uint8_t last_alt = 0;
-
-  while(max_len > drv_len)
+  uint16_t drv_len = 0;
+  while(itf_desc->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS && itf_desc->bInterfaceProtocol == DFU_PROTOCOL_DFU)
   {
-    // Ensure this is DFU Mode
-    TU_VERIFY((((tusb_desc_interface_t const *)p_desc)->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS) &&
-              (((tusb_desc_interface_t const *)p_desc)->bInterfaceProtocol == DFU_PROTOCOL_DFU), 0);
+    TU_ASSERT(max_len > drv_len, 0);
 
-    uint8_t const alt = ((tusb_desc_interface_t const *)p_desc)->bAlternateSetting;
-    uint8_t const intf = ((tusb_desc_interface_t const *)p_desc)->bInterfaceNumber;
+    // Alternate must have the same interface number
+    TU_ASSERT(itf_desc->bInterfaceNumber == itf_num, 0);
 
-    if (_dfu_state_ctx.intf == DFU_INTF_UNUSED)
-    {
-      _dfu_state_ctx.intf = intf;
-    }
-    else
-    {
-      // Only one DFU interface is supported
-      TU_ASSERT(_dfu_state_ctx.intf == intf, 0);
-    }
+    // Alt should increase by one every time
+    TU_ASSERT(itf_desc->bAlternateSetting == alt_count, 0);
+    alt_count++;
 
-    // CFG_TUD_DFU_ATL_MAX should big enough to hold all alt settings
-    TU_ASSERT(alt < CFG_TUD_DFU_ALT_COUNT, 0);
-
-    // Alt should increse by one every time
-    TU_ASSERT(alt == last_alt++, 0);
-
-    p_desc = tu_desc_next(p_desc);
-    max_len -= drv_len;
-    total_len += drv_len;
+    drv_len += tu_desc_len(itf_desc);
+    itf_desc = (tusb_desc_interface_t const *) tu_desc_next(itf_desc);
   }
 
-  //------------- DFU descriptor -------------//
-  TU_ASSERT(tu_desc_type(p_desc) == TUSB_DESC_FUNCTIONAL, 0);
+  //------------- DFU Functional descriptor -------------//
+  tusb_desc_dfu_functional_t const *func_desc = (tusb_desc_dfu_functional_t const *) itf_desc;
+  TU_ASSERT(tu_desc_type(func_desc) == TUSB_DESC_FUNCTIONAL, 0);
+  drv_len += sizeof(tusb_desc_dfu_functional_t);
 
-  _dfu_state_ctx.attrs = ((tusb_desc_dfu_functional_t const *)p_desc)->bAttributes;
+  _dfu_state_ctx.attrs = func_desc->bAttributes;
 
   // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the buffer size used in TUD_DFU_MODE_DESCRIPTOR
-  TU_ASSERT(((tusb_desc_dfu_functional_t const *)p_desc)->wTransferSize <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 0);
+  uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16(&func_desc->wTransferSize) );
+  TU_ASSERT(transfer_size <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, drv_len);
 
-  total_len += sizeof(tusb_desc_dfu_functional_t); 
-
-  return total_len;
+  return drv_len;
 }
 
 // Invoked when a control transfer occurred on an interface of this class

From 134ed995c82635d509621e40568b57309fc26101 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jul 2021 18:50:19 +0700
Subject: [PATCH 0191/2085] add alt to tud_dfu_abort_cb()

---
 src/class/dfu/dfu_device.c | 4 ++--
 src/class/dfu/dfu_device.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 04f086e0e..933946b7e 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -503,7 +503,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
           {
             if ( tud_dfu_abort_cb )
             {
-              tud_dfu_abort_cb();
+              tud_dfu_abort_cb(_dfu_state_ctx.alt);
             }
             _dfu_state_ctx.state = DFU_IDLE;
           }
@@ -613,7 +613,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         {
           if (tud_dfu_abort_cb)
           {
-            tud_dfu_abort_cb();
+            tud_dfu_abort_cb(_dfu_state_ctx.alt);
           }
           _dfu_state_ctx.state = DFU_IDLE;
         }
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index c09b9a823..73e5055cd 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -73,7 +73,7 @@ void tud_dfu_dnload_complete(void);
 bool tud_dfu_device_data_done_check_cb(uint8_t alt);
 
 // Invoked when the Host has terminated a download or upload transfer
-TU_ATTR_WEAK void tud_dfu_abort_cb(void);
+TU_ATTR_WEAK void tud_dfu_abort_cb(uint8_t alt);
 
 // Invoked when a DFU_UPLOAD request is received
 // alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.

From 2916cd45753ca579ee1d0b475b2daf3f715243b6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jul 2021 18:51:57 +0700
Subject: [PATCH 0192/2085] rename TUD_DFU_MODE_DESCRIPTOR to
 TUD_DFU_DESCRIPTOR

---
 examples/device/dfu/src/tusb_config.h     | 2 +-
 examples/device/dfu/src/usb_descriptors.c | 2 +-
 src/class/dfu/dfu_device.c                | 2 +-
 src/class/dfu/dfu_device.h                | 2 +-
 src/device/usbd.h                         | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 55aa19922..7e10b4321 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -83,7 +83,7 @@
 
 // Count of all alt settings, typically it's the partition count (Flash, EEPROM, etc.)
 #define CFG_TUD_DFU_ALT_COUNT               2
-// DFU buffer size, it has to be set to the buffer size used in TUD_DFU_MODE_DESCRIPTOR
+// DFU buffer size, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
 #define CFG_TUD_DFU_TRANSFER_BUFFER_SIZE    4096
 
 #ifdef __cplusplus
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 8c5eee455..870c18a04 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -97,7 +97,7 @@ uint8_t const desc_configuration[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
   // Interface number, attributes, detach timeout, transfer size, string index 0, [string index 1 ... string index n]
-  TUD_DFU_MODE_DESCRIPTOR(ITF_NUM_DFU_MODE, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 4, 5),
+  TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 4, 5),
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 933946b7e..ae056b441 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -200,7 +200,7 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
 
   _dfu_state_ctx.attrs = func_desc->bAttributes;
 
-  // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the buffer size used in TUD_DFU_MODE_DESCRIPTOR
+  // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
   uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16(&func_desc->wTransferSize) );
   TU_ASSERT(transfer_size <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, drv_len);
 
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index 73e5055cd..8edb2bae3 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -38,7 +38,7 @@
 //--------------------------------------------------------------------+
 
 #if !defined(CFG_TUD_DFU_TRANSFER_BUFFER_SIZE)
-  #error "CFG_TUD_DFU_TRANSFER_BUFFER_SIZE must be defined, it has to be set to the buffer size used in TUD_DFU_MODE_DESCRIPTOR"
+  #error "CFG_TUD_DFU_TRANSFER_BUFFER_SIZE must be defined, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR"
 #endif
 
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd.h b/src/device/usbd.h
index ba415abe8..8c5f0097d 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -646,7 +646,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   TU_XSTRCAT(TUD_DFU_MODE_ALT_, CFG_TUD_DFU_ALT_COUNT)(_itfnum, __VA_ARGS__)
 
 // Interface number, attributes, detach timeout, transfer size, string index 0, [string index 1, string index n]
-#define TUD_DFU_MODE_DESCRIPTOR(_itfnum, _attr, _timeout, _xfer_size, _stridx, ...) \
+#define TUD_DFU_DESCRIPTOR(_itfnum, _attr, _timeout, _xfer_size, _stridx, ...) \
   TUD_DFU_MODE_ALTS(_itfnum, _TUD_DFU_COMBINE(_stridx, __VA_ARGS__)) \
   TUD_DFU_MODE_FUNC(_attr, _timeout, _xfer_size)
 

From 680b000bd1471d731117ccf4f3fe35579d346cb8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jul 2021 20:15:59 +0700
Subject: [PATCH 0193/2085] simplify TUD_DFU_DESCRIPTOR with alternate count

remove CFG_TUD_DFU_ALT_COUNT since there is only one DFU functional
descriptor
---
 examples/device/dfu/src/main.c            |  3 +-
 examples/device/dfu/src/tusb_config.h     |  2 -
 examples/device/dfu/src/usb_descriptors.c |  9 ++-
 src/device/usbd.h                         | 71 ++++++++++++-----------
 4 files changed, 44 insertions(+), 41 deletions(-)

diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index f7c27174a..ee201c1c5 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -154,8 +154,9 @@ bool tud_dfu_device_data_done_check_cb(uint8_t alt)
   return true;
 }
 
-void tud_dfu_abort_cb(void)
+void tud_dfu_abort_cb(uint8_t alt)
 {
+  (void) alt;
   printf("    Host aborted transfer\r\n");
 }
 
diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 7e10b4321..77d907ffc 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -81,8 +81,6 @@
 #define CFG_TUD_DFU_RUNTIME 0
 #define CFG_TUD_DFU_MODE    1
 
-// Count of all alt settings, typically it's the partition count (Flash, EEPROM, etc.)
-#define CFG_TUD_DFU_ALT_COUNT               2
 // DFU buffer size, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
 #define CFG_TUD_DFU_TRANSFER_BUFFER_SIZE    4096
 
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 870c18a04..78e94194e 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -81,13 +81,16 @@ uint8_t const * tud_descriptor_device_cb(void)
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
+// Number of Alternate Interface (each for 1 flash partition)
+#define ALT_COUNT   2
+
 enum
 {
   ITF_NUM_DFU_MODE,
   ITF_NUM_TOTAL
 };
 
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_DFU_MODE_DESC_LEN)
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_DFU_DESC_LEN(ALT_COUNT))
 
 #define FUNC_ATTRS (DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK | DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK)
 
@@ -96,8 +99,8 @@ uint8_t const desc_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
-  // Interface number, attributes, detach timeout, transfer size, string index 0, [string index 1 ... string index n]
-  TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 4, 5),
+  // Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size
+  TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, ALT_COUNT, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE),
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 8c5f0097d..9697b4497 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -605,50 +605,51 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Function */ \
   9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
 
-// Maximum alternate settings (used for different partitons) supported
-#ifndef CFG_TUD_DFU_ALT_COUNT
-#define CFG_TUD_DFU_ALT_COUNT 1
-#endif
+// Length of template descriptor: 9 bytes + number of alternatives * 9
+#define TUD_DFU_DESC_LEN(_alt_count)    (9 + (_alt_count) * 9)
 
-// Length of template descriptor: 18 bytes + number of alternatives * 9
-#define TUD_DFU_MODE_DESC_LEN (9 + (CFG_TUD_DFU_ALT_COUNT) * 9)
-
-/* Primary Interface */
-#define TUD_DFU_MODE_FUNC(_attr, _timeout, _xfer_size) \
+// Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size
+// Note: Alternate count must be numberic or macro, string index is increased by one for each Alt interface
+#define TUD_DFU_DESCRIPTOR(_itfnum, _alt_count, _stridx, _attr, _timeout, _xfer_size) \
+  TU_XSTRCAT(_TUD_DFU_ALT_,_alt_count)(_itfnum, 0, _stridx), \
   /* Function */ \
   9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
 
-#define TUD_DFU_MODE_ALT(_itfnum, _alt, _stridx) \
+#define _TUD_DFU_ALT(_itfnum, _alt, _stridx) \
   /* Interface */ \
-  9, TUSB_DESC_INTERFACE, _itfnum, _alt, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx, \
+  9, TUSB_DESC_INTERFACE, _itfnum, _alt, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx
 
-#define _TUD_DFU_FIRST(a, ...) a
-#define _TUD_DFU_REST(a, ...) __VA_ARGS__
-#define _TUD_DFU_COMBINE(...) __VA_ARGS__
+#define _TUD_DFU_ALT_1(_itfnum, _alt_count, _stridx) \
+  _TUD_DFU_ALT(_itfnum, _alt_count, _stridx)
 
-#define TUD_DFU_MODE_ALT_1(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 1, _TUD_DFU_FIRST(__VA_ARGS__))
-#define TUD_DFU_MODE_ALT_2(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 2, _TUD_DFU_FIRST(__VA_ARGS__)) \
-  TUD_DFU_MODE_ALT_1(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
-#define TUD_DFU_MODE_ALT_3(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 3, _TUD_DFU_FIRST(__VA_ARGS__)) \
-  TUD_DFU_MODE_ALT_2(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
-#define TUD_DFU_MODE_ALT_4(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 4, _TUD_DFU_FIRST(__VA_ARGS__)) \
-  TUD_DFU_MODE_ALT_3(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
-#define TUD_DFU_MODE_ALT_5(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 5, _TUD_DFU_FIRST(__VA_ARGS__)) \
-  TUD_DFU_MODE_ALT_4(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
-#define TUD_DFU_MODE_ALT_6(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 6, _TUD_DFU_FIRST(__VA_ARGS__)) \
-  TUD_DFU_MODE_ALT_5(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
-#define TUD_DFU_MODE_ALT_7(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 7, _TUD_DFU_FIRST(__VA_ARGS__)) \
-  TUD_DFU_MODE_ALT_6(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
-#define TUD_DFU_MODE_ALT_8(_itfnum, ...) TUD_DFU_MODE_ALT(_itfnum, (CFG_TUD_DFU_ALT_COUNT) - 8, _TUD_DFU_FIRST(__VA_ARGS__)) \
-  TUD_DFU_MODE_ALT_7(_itfnum, _TUD_DFU_REST(__VA_ARGS__))
+#define _TUD_DFU_ALT_2(_itfnum, _alt_count, _stridx) \
+  _TUD_DFU_ALT(_itfnum, _alt_count, _stridx),      \
+  _TUD_DFU_ALT_1(_itfnum, _alt_count+1, _stridx+1)
 
-#define TUD_DFU_MODE_ALTS(_itfnum, ...) \
-  TU_XSTRCAT(TUD_DFU_MODE_ALT_, CFG_TUD_DFU_ALT_COUNT)(_itfnum, __VA_ARGS__)
+#define _TUD_DFU_ALT_3(_itfnum, _alt_count, _stridx) \
+  _TUD_DFU_ALT(_itfnum, _alt_count, _stridx),      \
+  _TUD_DFU_ALT_2(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_4(_itfnum, _alt_count, _stridx) \
+  _TUD_DFU_ALT(_itfnum, _alt_count, _stridx),      \
+  _TUD_DFU_ALT_3(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_5(_itfnum, _alt_count, _stridx) \
+  _TUD_DFU_ALT(_itfnum, _alt_count, _stridx),      \
+  _TUD_DFU_ALT_4(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_6(_itfnum, _alt_count, _stridx) \
+  _TUD_DFU_ALT(_itfnum, _alt_count, _stridx),      \
+  _TUD_DFU_ALT_5(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_7(_itfnum, _alt_count, _stridx) \
+  _TUD_DFU_ALT(_itfnum, _alt_count, _stridx),      \
+  _TUD_DFU_ALT_6(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_8(_itfnum, _alt_count, _stridx) \
+  _TUD_DFU_ALT(_itfnum, _alt_count, _stridx),      \
+  _TUD_DFU_ALT_7(_itfnum, _alt_count+1, _stridx+1)
 
-// Interface number, attributes, detach timeout, transfer size, string index 0, [string index 1, string index n]
-#define TUD_DFU_DESCRIPTOR(_itfnum, _attr, _timeout, _xfer_size, _stridx, ...) \
-  TUD_DFU_MODE_ALTS(_itfnum, _TUD_DFU_COMBINE(_stridx, __VA_ARGS__)) \
-  TUD_DFU_MODE_FUNC(_attr, _timeout, _xfer_size)
 
 //------------- CDC-ECM -------------//
 

From 389d34067854fcf39dd1839f2643bd8300aafe1d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jul 2021 20:17:44 +0700
Subject: [PATCH 0194/2085] clean up

---
 src/class/dfu/dfu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index ae056b441..a7a8f578c 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -42,7 +42,7 @@
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-typedef struct TU_ATTR_PACKED
+typedef struct
 {
     dfu_device_status_t status;
     dfu_state_t state;

From 8c48a4a2886bdac96df274311f84bc6c04c56b95 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jul 2021 20:23:19 +0700
Subject: [PATCH 0195/2085] clean up

---
 src/class/dfu/dfu_device.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index a7a8f578c..51e6179bc 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -37,8 +37,6 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-#define DFU_INTF_UNUSED 0xFF
-
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+

From 86d511f24452b13c8e5779c7a79bff54a03dafd8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jul 2021 21:08:13 +0700
Subject: [PATCH 0196/2085] rename tud_dfu_set_timeout_cb() to
 tud_dfu_get_status_cb()

also add state as argument
---
 examples/device/dfu/src/main.c |  7 +++++--
 src/class/dfu/dfu_device.c     | 19 +++++++++----------
 src/class/dfu/dfu_device.h     |  6 +++---
 3 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index ee201c1c5..4ec6d477c 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -125,10 +125,13 @@ bool tud_dfu_firmware_valid_check_cb(uint8_t alt)
   return true;
 }
 
-uint16_t tud_dfu_set_timeout_cb(uint8_t alt)
+uint32_t tud_dfu_get_status_cb(uint8_t alt, uint8_t state)
 {
   // For example Alt1 (EEPROM) is slow, add 2000ms timeout
-  if (alt == 1) return 2000;
+  if ( state == DFU_DNBUSY )
+  {
+    if (alt == 1) return 2000;
+  }
   return 0;
 }
 
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 51e6179bc..23669b508 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -293,18 +293,17 @@ static uint16_t dfu_req_upload(uint8_t rhport, tusb_control_request_t const * re
 
 static void dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const * request)
 {
-  dfu_status_req_payload_t resp;
-
-  uint16_t timeout = 0;
-  resp.bStatus = _dfu_state_ctx.status;
-  if(_dfu_state_ctx.state == DFU_DNBUSY && tud_dfu_set_timeout_cb)
+  uint32_t timeout = 0;
+  if ( tud_dfu_get_status_cb )
   {
-    timeout = tud_dfu_set_timeout_cb(_dfu_state_ctx.alt);
-    
+    timeout = tud_dfu_get_status_cb(_dfu_state_ctx.alt, _dfu_state_ctx.state);
   }
-  resp.bwPollTimeout[0] = TU_U16_LOW(timeout);
-  resp.bwPollTimeout[1] = TU_U16_HIGH(timeout);
-  resp.bwPollTimeout[2] = 0;
+
+  dfu_status_req_payload_t resp;
+  resp.bStatus = _dfu_state_ctx.status;
+  resp.bwPollTimeout[0] = TU_U32_BYTE0(timeout);
+  resp.bwPollTimeout[1] = TU_U32_BYTE1(timeout);
+  resp.bwPollTimeout[2] = TU_U32_BYTE2(timeout);
   resp.bState = _dfu_state_ctx.state;
   resp.iString = 0;
 
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index 8edb2bae3..647fc2c04 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -48,10 +48,10 @@
 // alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 bool tud_dfu_firmware_valid_check_cb(uint8_t alt);
 
-// Invoked when a DFU_GETSTATUS request is received in DFU_DNBUSY state
-// Used to set the bwPollTimeout value, useful for slow Flash in order to make host wait longer 
+// Invoked when a DFU_GETSTATUS request is received
+// Return the bwPollTimeout value for host's response, useful for slow Flash in order to make host wait longer
 // alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
-TU_ATTR_WEAK uint16_t tud_dfu_set_timeout_cb(uint8_t alt);
+TU_ATTR_WEAK uint32_t tud_dfu_get_status_cb(uint8_t alt, uint8_t state);
 
 // Invoked when a DFU_DNLOAD request is received
 // alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.

From 137dff620bc5890afdf59a61cebe355fc6999f12 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 13 Jul 2021 20:24:12 +0700
Subject: [PATCH 0197/2085] add option to silent a driver log

---
 src/class/msc/msc_device.c | 20 ++++++++++++--------
 src/common/tusb_common.h   | 18 +++++++++++++-----
 src/common/tusb_compiler.h | 12 ++++++++----
 src/common/tusb_fifo.h     |  2 +-
 4 files changed, 34 insertions(+), 18 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 7f13b4891..014e8b69e 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -37,6 +37,10 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
+
+// Can be selectively disabled to reduce logging when troubleshooting other driver
+#define MSC_DEBUG   2
+
 enum
 {
   MSC_STAGE_CMD  = 0,
@@ -99,7 +103,7 @@ static inline uint16_t rdwr10_get_blockcount(uint8_t const command[])
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
 
-static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
+TU_ATTR_UNUSED static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
 {
   { .key = SCSI_CMD_TEST_UNIT_READY              , .data = "Test Unit Ready" },
   { .key = SCSI_CMD_INQUIRY                      , .data = "Inquiry" },
@@ -114,7 +118,7 @@ static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
   { .key = SCSI_CMD_WRITE_10                     , .data = "Write10" }
 };
 
-static tu_lookup_table_t const _msc_scsi_cmd_table =
+TU_ATTR_UNUSED static tu_lookup_table_t const _msc_scsi_cmd_table =
 {
   .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup),
   .items = _msc_scsi_cmd_lookup
@@ -232,8 +236,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       TU_ASSERT( event == XFER_RESULT_SUCCESS &&
                  xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE );
 
-      TU_LOG2("  SCSI Command: %s\r\n", tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
-      // TU_LOG2_MEM(p_cbw, xferred_bytes, 2);
+      TU_LOG(MSC_DEBUG, "  SCSI Command: %s\r\n", tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
+      // TU_LOG_MEM(MSC_DEBUG, p_cbw, xferred_bytes, 2);
 
       p_csw->signature    = MSC_CSW_SIGNATURE;
       p_csw->tag          = p_cbw->tag;
@@ -305,8 +309,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     break;
 
     case MSC_STAGE_DATA:
-      TU_LOG2("  SCSI Data\r\n");
-      //TU_LOG2_MEM(_mscd_buf, xferred_bytes, 2);
+      TU_LOG(MSC_DEBUG, "  SCSI Data\r\n");
+      //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2);
 
       // OUT transfer, invoke callback if needed
       if ( !tu_bit_test(p_cbw->dir, 7) )
@@ -402,8 +406,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       // Wait for the Status phase to complete
       if( (ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t)) )
       {
-        TU_LOG2("  SCSI Status: %u\r\n", p_csw->status);
-        // TU_LOG2_MEM(p_csw, xferred_bytes, 2);
+        TU_LOG(MSC_DEBUG, "  SCSI Status: %u\r\n", p_csw->status);
+        // TU_LOG_MEM(MSC_DEBUG, p_csw, xferred_bytes, 2);
 
         // Invoke complete callback if defined
         // Note: There is racing issue with samd51 + qspi flash testing with arduino
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 8490daad7..c8a66a879 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -305,11 +305,11 @@ void tu_print_var(uint8_t const* buf, uint32_t bufsize)
 }
 
 // Log with Level
-#define TU_LOG(n, ...)        TU_LOG##n(__VA_ARGS__)
-#define TU_LOG_MEM(n, ...)    TU_LOG##n##_MEM(__VA_ARGS__)
-#define TU_LOG_VAR(n, ...)    TU_LOG##n##_VAR(__VA_ARGS__)
-#define TU_LOG_INT(n, ...)    TU_LOG##n##_INT(__VA_ARGS__)
-#define TU_LOG_HEX(n, ...)    TU_LOG##n##_HEX(__VA_ARGS__)
+#define TU_LOG(n, ...)        TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
+#define TU_LOG_MEM(n, ...)    TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
+#define TU_LOG_VAR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _VAR)(__VA_ARGS__)
+#define TU_LOG_INT(n, ...)    TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
+#define TU_LOG_HEX(n, ...)    TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
 #define TU_LOG_LOCATION()     tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
 #define TU_LOG_FAILED()       tu_printf("%s: %d: Failed\r\n", __PRETTY_FUNCTION__, __LINE__)
 
@@ -373,6 +373,14 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #endif
 
 // TODO replace all TU_LOGn with TU_LOG(n)
+
+#define TU_LOG0(...)
+#define TU_LOG0_MEM(...)
+#define TU_LOG0_VAR(...)
+#define TU_LOG0_INT(...)
+#define TU_LOG0_HEX(...)
+
+
 #ifndef TU_LOG1
   #define TU_LOG1(...)
   #define TU_LOG1_MEM(...)
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index f755e13f4..0dd9ba016 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -32,10 +32,14 @@
 #ifndef _TUSB_COMPILER_H_
 #define _TUSB_COMPILER_H_
 
-#define TU_STRING(x)      #x              ///< stringify without expand
-#define TU_XSTRING(x)     TU_STRING(x)    ///< expand then stringify
-#define TU_STRCAT(a, b)   a##b            ///< concat without expand
-#define TU_XSTRCAT(a, b)  TU_STRCAT(a, b) ///< expand then concat
+#define TU_STRING(x)          #x                  ///< stringify without expand
+#define TU_XSTRING(x)         TU_STRING(x)        ///< expand then stringify
+
+#define TU_STRCAT(a, b)       a##b                ///< concat without expand
+#define TU_STRCAT3(a, b, c)   a##b##c             ///< concat without expand
+
+#define TU_XSTRCAT(a, b)      TU_STRCAT(a, b)     ///< expand then concat
+#define TU_XSTRCAT3(a, b, c)  TU_STRCAT3(a, b, c) ///< expand then concat 3 tokens
 
 #if defined __COUNTER__ && __COUNTER__ != __COUNTER__
   #define _TU_COUNTER_ __COUNTER__
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index de2ae163d..18db289a1 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -120,9 +120,9 @@ bool     tu_fifo_peek                   (tu_fifo_t* f, void * p_buffer);
 uint16_t tu_fifo_peek_n                 (tu_fifo_t* f, void * p_buffer, uint16_t n);
 
 uint16_t tu_fifo_count                  (tu_fifo_t* f);
+uint16_t tu_fifo_remaining              (tu_fifo_t* f);
 bool     tu_fifo_empty                  (tu_fifo_t* f);
 bool     tu_fifo_full                   (tu_fifo_t* f);
-uint16_t tu_fifo_remaining              (tu_fifo_t* f);
 bool     tu_fifo_overflowed             (tu_fifo_t* f);
 void     tu_fifo_correct_read_pointer   (tu_fifo_t* f);
 

From ebd98e1a18bf1dfbbf45420310c4dee96a3bfd24 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 13 Jul 2021 21:09:23 +0700
Subject: [PATCH 0198/2085] fix midi stream write return value (off by 1)

---
 src/class/midi/midi_device.c | 21 ++++++++-------------
 1 file changed, 8 insertions(+), 13 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 4eac0de48..c39e03976 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -240,15 +240,15 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
 
   midid_stream_t* stream = &midi->stream_write;
 
-  uint32_t total_written = 0;
   uint32_t i = 0;
-  while ( i < bufsize )
+  while ( (i < bufsize) && (tu_fifo_remaining(&midi->tx_ff) >= 4) )
   {
     uint8_t const data = buffer[i];
+    i++;
 
     if ( stream->index == 0 )
     {
-      // new event packet
+      //------------- New event packet -------------//
 
       uint8_t const msg = data >> 4;
 
@@ -310,9 +310,9 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
     }
     else
     {
-      // On-going (buffering) packet
+      //------------- On-going (buffering) packet -------------//
 
-      TU_ASSERT(stream->index < 4, total_written);
+      TU_ASSERT(stream->index < 4, i);
       stream->buffer[stream->index] = data;
       stream->index++;
 
@@ -335,19 +335,14 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
       // complete current event packet, reset stream
       stream->index = stream->total = 0;
 
-      // fifo overflow, here we assume FIFO is multiple of 4 and didn't check remaining before writing
-      if ( count != 4 ) break;
-
-      // updated written if succeeded
-      total_written = i;
+      // FIFO overflown, since we already check fifo remaining. It is probably race condition
+      TU_ASSERT(count == 4, i);
     }
-
-    i++;
   }
 
   write_flush(midi);
 
-  return total_written;
+  return i;
 }
 
 bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4])

From ac8d0abecf93af2498f9d5d1438c2af7b133bedc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jul 2021 15:04:38 +0700
Subject: [PATCH 0199/2085] rename dfu API

- tud_dfu_dnload_complete() -> tud_dfu_download_complete()
- tud_dfu_req_dnload_data_cb() -> tud_dfu_download_cb()
- tud_dfu_req_upload_data_cb() -> tud_dfu_upload_cb()
---
 examples/device/dfu/src/main.c       |  6 +++---
 examples/device/midi_test/src/main.c | 10 +++++++---
 src/class/dfu/dfu_device.c           |  8 ++++----
 src/class/dfu/dfu_device.h           |  8 ++++----
 4 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 4ec6d477c..8e7fa9ee0 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -135,7 +135,7 @@ uint32_t tud_dfu_get_status_cb(uint8_t alt, uint8_t state)
   return 0;
 }
 
-void tud_dfu_req_dnload_data_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length)
+void tud_dfu_download_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length)
 {
   (void) data;
   printf("    Received Alt %u BlockNum %u of length %u\r\n", alt, wBlockNum, length);
@@ -147,7 +147,7 @@ void tud_dfu_req_dnload_data_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data,
   }
 #endif
 
-  tud_dfu_dnload_complete();
+  tud_dfu_download_complete();
 }
 
 bool tud_dfu_device_data_done_check_cb(uint8_t alt)
@@ -167,7 +167,7 @@ void tud_dfu_abort_cb(uint8_t alt)
 const uint8_t upload_test[2][UPLOAD_SIZE] = {"Hello world from TinyUSB DFU! - Partition 0",
                                              "Hello world from TinyUSB DFU! - Partition 1"};
 
-uint16_t tud_dfu_req_upload_data_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length)
+uint16_t tud_dfu_upload_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length)
 {
   (void) block_num;
   (void) length;
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 9e0e82a10..66b858323 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -134,10 +134,13 @@ void midi_task(void)
   uint8_t packet[4];
   while ( tud_midi_available() ) tud_midi_packet_read(packet);
 
-  // send note every 1000 ms
-  if (board_millis() - start_ms < 286) return; // not enough time
-  start_ms += 286;
+  // send note periodically
+  if (board_millis() - start_ms < 1000) return; // not enough time
+  start_ms += 1000;
 
+#if 1
+
+#else
   // Previous positions in the note sequence.
   int previous = note_pos - 1;
 
@@ -158,6 +161,7 @@ void midi_task(void)
 
   // If we are at the end of the sequence, start over.
   if (note_pos >= sizeof(note_sequence)) note_pos = 0;
+#endif
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 23669b508..c8c0bcfd4 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -283,9 +283,9 @@ static uint16_t dfu_req_upload(uint8_t rhport, tusb_control_request_t const * re
 {
   TU_VERIFY( wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 0);
   uint16_t retval = 0;
-  if (tud_dfu_req_upload_data_cb)
+  if (tud_dfu_upload_cb)
   {
-    tud_dfu_req_upload_data_cb(_dfu_state_ctx.alt, block_num, (uint8_t *)_dfu_state_ctx.transfer_buf, wLength);
+    tud_dfu_upload_cb(_dfu_state_ctx.alt, block_num, (uint8_t *)_dfu_state_ctx.transfer_buf, wLength);
   }
   tud_control_xfer(rhport, request, _dfu_state_ctx.transfer_buf, retval);
   return retval;
@@ -330,11 +330,11 @@ static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const *
 {
   (void) rhport;
   TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, );
-  tud_dfu_req_dnload_data_cb(_dfu_state_ctx.alt,_dfu_state_ctx.block, (uint8_t *)_dfu_state_ctx.transfer_buf, _dfu_state_ctx.length);
+  tud_dfu_download_cb(_dfu_state_ctx.alt,_dfu_state_ctx.block, (uint8_t *)_dfu_state_ctx.transfer_buf, _dfu_state_ctx.length);
   _dfu_state_ctx.blk_transfer_in_proc = false;
 }
 
-void tud_dfu_dnload_complete(void)
+void tud_dfu_download_complete(void)
 {
   if (_dfu_state_ctx.state == DFU_DNBUSY)
   {
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index 647fc2c04..2a1f5a8e7 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -58,11 +58,11 @@ TU_ATTR_WEAK uint32_t tud_dfu_get_status_cb(uint8_t alt, uint8_t state);
 // This callback takes the wBlockNum chunk of length length and provides it
 // to the application at the data pointer.  This data is only valid for this
 // call, so the app must use it not or copy it.
-void tud_dfu_req_dnload_data_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length);
+void tud_dfu_download_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length);
 
 // Must be called when the application is done using the last block of data
-// provided by tud_dfu_req_dnload_data_cb
-void tud_dfu_dnload_complete(void);
+// provided by tud_dfu_download_cb
+void tud_dfu_download_complete(void);
 
 // Invoked during the last DFU_DNLOAD request, signifying that the host believes
 // it is done transmitting data.
@@ -79,7 +79,7 @@ TU_ATTR_WEAK void tud_dfu_abort_cb(uint8_t alt);
 // alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 // This callback must populate data with up to length bytes
 // Return the number of bytes to write
-TU_ATTR_WEAK uint16_t tud_dfu_req_upload_data_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length);
+TU_ATTR_WEAK uint16_t tud_dfu_upload_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length);
 
 // Invoked when a DFU_DETACH request is received
 TU_ATTR_WEAK void tud_dfu_reboot_cb(void);

From 57d9f696a2c11cf0004ea2eec1204d80c657cb03 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jul 2021 15:24:09 +0700
Subject: [PATCH 0200/2085] clean up

---
 src/class/dfu/dfu_device.c | 73 +++++++++-----------------------------
 1 file changed, 16 insertions(+), 57 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index c8c0bcfd4..dcdc34977 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -46,7 +46,7 @@ typedef struct
     dfu_state_t state;
     uint8_t attrs;
     bool blk_transfer_in_proc;
-    uint8_t alt;
+    uint8_t alt_num;
     uint16_t block;
     uint16_t length;
     CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_TRANSFER_BUFFER_SIZE];
@@ -149,7 +149,7 @@ void dfu_moded_init(void)
   _dfu_state_ctx.status = DFU_STATUS_OK;
   _dfu_state_ctx.attrs = 0;
   _dfu_state_ctx.blk_transfer_in_proc = false;
-  _dfu_state_ctx.alt = 0;
+  _dfu_state_ctx.alt_num = 0;
 
   dfu_debug_print_context();
 }
@@ -162,7 +162,7 @@ void dfu_moded_reset(uint8_t rhport)
   _dfu_state_ctx.status = DFU_STATUS_OK;
   _dfu_state_ctx.attrs = 0;
   _dfu_state_ctx.blk_transfer_in_proc = false;
-  _dfu_state_ctx.alt = 0;
+  _dfu_state_ctx.alt_num = 0;
 
   dfu_debug_print_context();
 }
@@ -221,7 +221,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
     if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && request->bRequest == TUSB_REQ_SET_INTERFACE)
     {
       // Switch Alt interface
-      _dfu_state_ctx.alt = request->wValue;
+      _dfu_state_ctx.alt_num = (uint8_t) request->wValue;
 
       // Re-initalise state machine (Necessary ?)
       _dfu_state_ctx.state = DFU_IDLE;
@@ -244,6 +244,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
       if (tud_dfu_reboot_cb) tud_dfu_reboot_cb();
       break;
     }
+
     case DFU_REQUEST_DNLOAD:
     {
       if ( (stage == CONTROL_STAGE_ACK)
@@ -254,7 +255,8 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
         _dfu_state_ctx.length = request->wLength;
         return true;
       }
-    } // fallthrough
+    }
+    // fallthrough
     case DFU_REQUEST_UPLOAD:
     case DFU_REQUEST_GETSTATUS:
     case DFU_REQUEST_CLRSTATUS:
@@ -285,7 +287,7 @@ static uint16_t dfu_req_upload(uint8_t rhport, tusb_control_request_t const * re
   uint16_t retval = 0;
   if (tud_dfu_upload_cb)
   {
-    tud_dfu_upload_cb(_dfu_state_ctx.alt, block_num, (uint8_t *)_dfu_state_ctx.transfer_buf, wLength);
+    tud_dfu_upload_cb(_dfu_state_ctx.alt_num, block_num, (uint8_t *)_dfu_state_ctx.transfer_buf, wLength);
   }
   tud_control_xfer(rhport, request, _dfu_state_ctx.transfer_buf, retval);
   return retval;
@@ -296,7 +298,7 @@ static void dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const
   uint32_t timeout = 0;
   if ( tud_dfu_get_status_cb )
   {
-    timeout = tud_dfu_get_status_cb(_dfu_state_ctx.alt, _dfu_state_ctx.state);
+    timeout = tud_dfu_get_status_cb(_dfu_state_ctx.alt_num, _dfu_state_ctx.state);
   }
 
   dfu_status_req_payload_t resp;
@@ -330,7 +332,7 @@ static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const *
 {
   (void) rhport;
   TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, );
-  tud_dfu_download_cb(_dfu_state_ctx.alt,_dfu_state_ctx.block, (uint8_t *)_dfu_state_ctx.transfer_buf, _dfu_state_ctx.length);
+  tud_dfu_download_cb(_dfu_state_ctx.alt_num,_dfu_state_ctx.block, (uint8_t *)_dfu_state_ctx.transfer_buf, _dfu_state_ctx.length);
   _dfu_state_ctx.blk_transfer_in_proc = false;
 }
 
@@ -384,28 +386,20 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         break;
 
         case DFU_REQUEST_GETSTATUS:
-        {
           dfu_req_getstatus_reply(rhport, request);
-        }
         break;
 
         case DFU_REQUEST_GETSTATE:
-        {
           dfu_req_getstate_reply(rhport, request);
-        }
         break;
 
         case DFU_REQUEST_ABORT:
-        {
           ; // do nothing, but don't stall so continue on
-        }
         break;
 
         default:
-        {
           _dfu_state_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
-        }
         break;
       }
     }
@@ -430,16 +424,12 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         break;
 
         case DFU_REQUEST_GETSTATE:
-        {
           dfu_req_getstate_reply(rhport, request);
-        }
         break;
 
         default:
-        {
           _dfu_state_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
-        }
         break;
       }
     }
@@ -450,10 +440,8 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       switch (request->bRequest)
       {
         default:
-        {
           _dfu_state_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
-        }
         break;
       }
     }
@@ -472,7 +460,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
               _dfu_state_ctx.blk_transfer_in_proc = true;
               dfu_req_dnload_setup(rhport, request);
             } else {
-              if ( tud_dfu_device_data_done_check_cb(_dfu_state_ctx.alt) )
+              if ( tud_dfu_device_data_done_check_cb(_dfu_state_ctx.alt_num) )
               {
                 _dfu_state_ctx.state = DFU_MANIFEST_SYNC;
                 tud_control_status(rhport, request);
@@ -485,32 +473,24 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
           break;
 
           case DFU_REQUEST_GETSTATUS:
-          {
             dfu_req_getstatus_reply(rhport, request);
-          }
           break;
 
           case DFU_REQUEST_GETSTATE:
-          {
             dfu_req_getstate_reply(rhport, request);
-          }
           break;
 
           case DFU_REQUEST_ABORT:
-          {
             if ( tud_dfu_abort_cb )
             {
-              tud_dfu_abort_cb(_dfu_state_ctx.alt);
+              tud_dfu_abort_cb(_dfu_state_ctx.alt_num);
             }
             _dfu_state_ctx.state = DFU_IDLE;
-          }
           break;
 
           default:
-          {
             _dfu_state_ctx.state = DFU_ERROR;
             return false;  // stall on all other requests
-          }
           break;
         }
     }
@@ -528,7 +508,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
             dfu_req_getstatus_reply(rhport, request);
           } else 
           {
-            if ( tud_dfu_firmware_valid_check_cb(_dfu_state_ctx.alt) )
+            if ( tud_dfu_firmware_valid_check_cb(_dfu_state_ctx.alt_num) )
             {
               _dfu_state_ctx.state = DFU_IDLE;
             }
@@ -538,16 +518,12 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         break;
 
         case DFU_REQUEST_GETSTATE:
-        {
           dfu_req_getstate_reply(rhport, request);
-        }
         break;
 
         default:
-        {
           _dfu_state_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
-        }
         break;
       }
     }
@@ -557,10 +533,9 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
     {
       switch (request->bRequest)
       {
+        // stall on all other requests
         default:
-        {
-          return false;  // stall on all other requests
-        }
+          return false;
         break;
       }
     }
@@ -573,9 +548,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       switch (request->bRequest)
       {
         default:
-        {
           return false;  // stall on all other requests
-        }
         break;
       }
     }
@@ -595,31 +568,25 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         break;
 
         case DFU_REQUEST_GETSTATUS:
-        {
           dfu_req_getstatus_reply(rhport, request);
-        }
         break;
 
         case DFU_REQUEST_GETSTATE:
-        {
           dfu_req_getstate_reply(rhport, request);
-        }
         break;
 
         case DFU_REQUEST_ABORT:
         {
           if (tud_dfu_abort_cb)
           {
-            tud_dfu_abort_cb(_dfu_state_ctx.alt);
+            tud_dfu_abort_cb(_dfu_state_ctx.alt_num);
           }
           _dfu_state_ctx.state = DFU_IDLE;
         }
         break;
 
         default:
-        {
           return false;  // stall on all other requests
-        }
         break;
       }
     }
@@ -630,27 +597,19 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       switch (request->bRequest)
       {
         case DFU_REQUEST_GETSTATUS:
-        {
           dfu_req_getstatus_reply(rhport, request);
-        }
         break;
 
         case DFU_REQUEST_CLRSTATUS:
-        {
           _dfu_state_ctx.state = DFU_IDLE;
-        }
         break;
 
         case DFU_REQUEST_GETSTATE:
-        {
           dfu_req_getstate_reply(rhport, request);
-        }
         break;
 
         default:
-        {
           return false;  // stall on all other requests
-        }
         break;
       }
     }

From 27676f738d54c1edf87449531b3a1fd24fca59d3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jul 2021 15:31:20 +0700
Subject: [PATCH 0201/2085] rename tud_dfu_reboot_cb() to tud_dfu_detach_cb()

---
 src/class/dfu/dfu_device.c | 2 +-
 src/class/dfu/dfu_device.h | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index dcdc34977..c807004ec 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -241,7 +241,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
     case DFU_REQUEST_DETACH:
     {
       tud_control_status(rhport, request);
-      if (tud_dfu_reboot_cb) tud_dfu_reboot_cb();
+      if (tud_dfu_detach_cb) tud_dfu_detach_cb();
       break;
     }
 
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index 2a1f5a8e7..d5d464f3b 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -82,7 +82,8 @@ TU_ATTR_WEAK void tud_dfu_abort_cb(uint8_t alt);
 TU_ATTR_WEAK uint16_t tud_dfu_upload_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length);
 
 // Invoked when a DFU_DETACH request is received
-TU_ATTR_WEAK void tud_dfu_reboot_cb(void);
+TU_ATTR_WEAK void tud_dfu_detach_cb(void);
+
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+

From 5b965a38883efb2d7210d48be6f305c0f31ca8fc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jul 2021 15:52:38 +0700
Subject: [PATCH 0202/2085] more rename and update

---
 examples/device/dfu/src/main.c |  14 +-
 src/class/dfu/dfu_device.c     | 241 +++++++++++++++++----------------
 2 files changed, 133 insertions(+), 122 deletions(-)

diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 8e7fa9ee0..2c114c5a2 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -28,11 +28,13 @@
   *
   * To transfer firmware from host to device:
   *
-  * $ dfu-util -D [filename]
+  * $ dfu-util -d cafe -a 0 -D [filename]
+  * $ dfu-util -d cafe -a 1 -D [filename]
   *
   * To transfer firmware from device to host:
   *
-  * $ dfu-util -U [filename]
+  * $ dfu-util -d cafe -a 0 -U [filename]
+  * $ dfu-util -d cafe -a 1 -U [filename]
   *
   */
 
@@ -138,12 +140,12 @@ uint32_t tud_dfu_get_status_cb(uint8_t alt, uint8_t state)
 void tud_dfu_download_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length)
 {
   (void) data;
-  printf("    Received Alt %u BlockNum %u of length %u\r\n", alt, wBlockNum, length);
+  printf("Received Alt %u BlockNum %u of length %u\r\n", alt, wBlockNum, length);
 
 #if DFU_VERBOSE
   for(uint16_t i=0; i<length; i++)
   {
-    printf("    [%u][%u]: %x\r\n", wBlockNum, i, (uint8_t)data[i]);
+    printf("  [%u][%u]: %x\r\n", wBlockNum, i, (uint8_t)data[i]);
   }
 #endif
 
@@ -153,14 +155,14 @@ void tud_dfu_download_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_
 bool tud_dfu_device_data_done_check_cb(uint8_t alt)
 {
   (void) alt;
-  printf("    Host said no more data... Returning true\r\n");
+  printf("Host said no more data... Returning true\r\n");
   return true;
 }
 
 void tud_dfu_abort_cb(uint8_t alt)
 {
   (void) alt;
-  printf("    Host aborted transfer\r\n");
+  printf("Host aborted transfer\r\n");
 }
 
 #define UPLOAD_SIZE 43
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index c807004ec..7b2f920d2 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -53,14 +53,14 @@ typedef struct
 } dfu_state_ctx_t;
 
 // Only a single dfu state is allowed
-CFG_TUSB_MEM_SECTION static dfu_state_ctx_t _dfu_state_ctx;
+CFG_TUSB_MEM_SECTION static dfu_state_ctx_t _dfu_ctx;
 
 
-static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const * request);
-static void dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const * request);
+static void     dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const * request);
+static void     dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const * request);
 static uint16_t dfu_req_upload(uint8_t rhport, tusb_control_request_t const * request, uint16_t block_num, uint16_t wLength);
-static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request);
-static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * request);
+static void     dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request);
+static bool     dfu_state_machine(uint8_t rhport, tusb_control_request_t const * request);
 
 //--------------------------------------------------------------------+
 // Debug
@@ -136,8 +136,8 @@ static tu_lookup_table_t const _dfu_status_table =
 #define dfu_debug_print_context()                                              \
 {                                                                              \
   TU_LOG2("  DFU at State: %s\r\n         Status: %s\r\n",                     \
-          tu_lookup_find(&_dfu_state_table, _dfu_state_ctx.state),        \
-          tu_lookup_find(&_dfu_status_table, _dfu_state_ctx.status) );    \
+          tu_lookup_find(&_dfu_state_table, _dfu_ctx.state),        \
+          tu_lookup_find(&_dfu_status_table, _dfu_ctx.status) );    \
 }
 
 //--------------------------------------------------------------------+
@@ -145,11 +145,11 @@ static tu_lookup_table_t const _dfu_status_table =
 //--------------------------------------------------------------------+
 void dfu_moded_init(void)
 {
-  _dfu_state_ctx.state = DFU_IDLE;
-  _dfu_state_ctx.status = DFU_STATUS_OK;
-  _dfu_state_ctx.attrs = 0;
-  _dfu_state_ctx.blk_transfer_in_proc = false;
-  _dfu_state_ctx.alt_num = 0;
+  _dfu_ctx.state = DFU_IDLE;
+  _dfu_ctx.status = DFU_STATUS_OK;
+  _dfu_ctx.attrs = 0;
+  _dfu_ctx.blk_transfer_in_proc = false;
+  _dfu_ctx.alt_num = 0;
 
   dfu_debug_print_context();
 }
@@ -158,11 +158,11 @@ void dfu_moded_reset(uint8_t rhport)
 {
   (void) rhport;
 
-  _dfu_state_ctx.state = DFU_IDLE;
-  _dfu_state_ctx.status = DFU_STATUS_OK;
-  _dfu_state_ctx.attrs = 0;
-  _dfu_state_ctx.blk_transfer_in_proc = false;
-  _dfu_state_ctx.alt_num = 0;
+  _dfu_ctx.state = DFU_IDLE;
+  _dfu_ctx.status = DFU_STATUS_OK;
+  _dfu_ctx.attrs = 0;
+  _dfu_ctx.blk_transfer_in_proc = false;
+  _dfu_ctx.alt_num = 0;
 
   dfu_debug_print_context();
 }
@@ -196,7 +196,7 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
   TU_ASSERT(tu_desc_type(func_desc) == TUSB_DESC_FUNCTIONAL, 0);
   drv_len += sizeof(tusb_desc_dfu_functional_t);
 
-  _dfu_state_ctx.attrs = func_desc->bAttributes;
+  _dfu_ctx.attrs = func_desc->bAttributes;
 
   // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
   uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16(&func_desc->wTransferSize) );
@@ -215,67 +215,76 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
 
   TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
 
-  if(stage == CONTROL_STAGE_SETUP)
+  if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD )
   {
-    // dfu-util will try to claim the interface with SET_INTERFACE request before sending DFU request
-    if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && request->bRequest == TUSB_REQ_SET_INTERFACE)
+    // Standard request include GET/SET_INTERFACE
+    switch (request->bRequest )
     {
-      // Switch Alt interface
-      _dfu_state_ctx.alt_num = (uint8_t) request->wValue;
+      case TUSB_REQ_SET_INTERFACE:
+        // Switch Alt interface and  Re-initalize state machine
+        _dfu_ctx.alt_num = (uint8_t) request->wValue;
+        _dfu_ctx.state = DFU_IDLE;
+        _dfu_ctx.status = DFU_STATUS_OK;
+        _dfu_ctx.blk_transfer_in_proc = false;
 
-      // Re-initalise state machine (Necessary ?)
-      _dfu_state_ctx.state = DFU_IDLE;
-      _dfu_state_ctx.status = DFU_STATUS_OK;
-      _dfu_state_ctx.blk_transfer_in_proc = false;
+        return tud_control_status(rhport, request);
+      break;
 
-      tud_control_status(rhport, request);
-      return true;
+      case TUSB_REQ_GET_INTERFACE:
+        return tud_control_xfer(rhport, request, &_dfu_ctx.alt_num, 1);
+      break;
+
+      // unsupported request
+      default: return false;
     }
   }
-
-  // Handle class request only from here
-  TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
-
-  switch (request->bRequest)
+  else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS)
   {
-    case DFU_REQUEST_DETACH:
+    // Class request
+    switch (request->bRequest)
     {
-      tud_control_status(rhport, request);
-      if (tud_dfu_detach_cb) tud_dfu_detach_cb();
+      case DFU_REQUEST_DETACH:
+      {
+        tud_control_status(rhport, request);
+        if (tud_dfu_detach_cb) tud_dfu_detach_cb();
+        break;
+      }
+
+      case DFU_REQUEST_DNLOAD:
+      {
+        if ( (stage == CONTROL_STAGE_ACK)
+             && ((_dfu_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+             && (_dfu_ctx.state == DFU_DNLOAD_SYNC))
+        {
+          _dfu_ctx.block = request->wValue;
+          _dfu_ctx.length = request->wLength;
+          return true;
+        }
+      }
+      // fallthrough
+      case DFU_REQUEST_UPLOAD:
+      case DFU_REQUEST_GETSTATUS:
+      case DFU_REQUEST_CLRSTATUS:
+      case DFU_REQUEST_GETSTATE:
+      case DFU_REQUEST_ABORT:
+      {
+        if(stage == CONTROL_STAGE_SETUP)
+        {
+          return dfu_state_machine(rhport, request);
+        }
+      }
+      break;
+
+      default:
+      {
+        TU_LOG2("  DFU Nonstandard Request: %u\r\n", request->bRequest);
+        return false; // stall unsupported request
+      }
       break;
     }
-
-    case DFU_REQUEST_DNLOAD:
-    {
-      if ( (stage == CONTROL_STAGE_ACK)
-           && ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
-           && (_dfu_state_ctx.state == DFU_DNLOAD_SYNC))
-      {
-        _dfu_state_ctx.block = request->wValue;
-        _dfu_state_ctx.length = request->wLength;
-        return true;
-      }
-    }
-    // fallthrough
-    case DFU_REQUEST_UPLOAD:
-    case DFU_REQUEST_GETSTATUS:
-    case DFU_REQUEST_CLRSTATUS:
-    case DFU_REQUEST_GETSTATE:
-    case DFU_REQUEST_ABORT:
-    {
-      if(stage == CONTROL_STAGE_SETUP)
-      {
-        return dfu_state_machine(rhport, request);
-      }
-    }
-    break;
-
-    default:
-    {
-      TU_LOG2("  DFU Nonstandard Request: %u\r\n", request->bRequest);
-      return false; // stall unsupported request
-    }
-    break;
+  }else
+  {
+    return false; // unsupported request
   }
 
   return true;
@@ -287,9 +296,9 @@ static uint16_t dfu_req_upload(uint8_t rhport, tusb_control_request_t const * re
   uint16_t retval = 0;
   if (tud_dfu_upload_cb)
   {
-    tud_dfu_upload_cb(_dfu_state_ctx.alt_num, block_num, (uint8_t *)_dfu_state_ctx.transfer_buf, wLength);
+    tud_dfu_upload_cb(_dfu_ctx.alt_num, block_num, (uint8_t *)_dfu_ctx.transfer_buf, wLength);
   }
-  tud_control_xfer(rhport, request, _dfu_state_ctx.transfer_buf, retval);
+  tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, retval);
   return retval;
 }
 
@@ -298,15 +307,15 @@ static void dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const
   uint32_t timeout = 0;
   if ( tud_dfu_get_status_cb )
   {
-    timeout = tud_dfu_get_status_cb(_dfu_state_ctx.alt_num, _dfu_state_ctx.state);
+    timeout = tud_dfu_get_status_cb(_dfu_ctx.alt_num, _dfu_ctx.state);
   }
 
   dfu_status_req_payload_t resp;
-  resp.bStatus = _dfu_state_ctx.status;
+  resp.bStatus = _dfu_ctx.status;
   resp.bwPollTimeout[0] = TU_U32_BYTE0(timeout);
   resp.bwPollTimeout[1] = TU_U32_BYTE1(timeout);
   resp.bwPollTimeout[2] = TU_U32_BYTE2(timeout);
-  resp.bState = _dfu_state_ctx.state;
+  resp.bState = _dfu_ctx.state;
   resp.iString = 0;
 
   tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_req_payload_t));
@@ -314,7 +323,7 @@ static void dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const
 
 static void dfu_req_getstate_reply(uint8_t rhport, tusb_control_request_t const * request)
 {
-  tud_control_xfer(rhport, request, &_dfu_state_ctx.state, 1);
+  tud_control_xfer(rhport, request, &_dfu_ctx.state, 1);
 }
 
 static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const * request)
@@ -325,25 +334,25 @@ static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const *
 
   TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, );
   // setup for data phase
-  tud_control_xfer(rhport, request, _dfu_state_ctx.transfer_buf, request->wLength);
+  tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, request->wLength);
 }
 
 static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request)
 {
   (void) rhport;
   TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, );
-  tud_dfu_download_cb(_dfu_state_ctx.alt_num,_dfu_state_ctx.block, (uint8_t *)_dfu_state_ctx.transfer_buf, _dfu_state_ctx.length);
-  _dfu_state_ctx.blk_transfer_in_proc = false;
+  tud_dfu_download_cb(_dfu_ctx.alt_num,_dfu_ctx.block, (uint8_t *)_dfu_ctx.transfer_buf, _dfu_ctx.length);
+  _dfu_ctx.blk_transfer_in_proc = false;
 }
 
 void tud_dfu_download_complete(void)
 {
-  if (_dfu_state_ctx.state == DFU_DNBUSY)
+  if (_dfu_ctx.state == DFU_DNBUSY)
   {
-    _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
-  } else if (_dfu_state_ctx.state == DFU_MANIFEST)
+    _dfu_ctx.state = DFU_DNLOAD_SYNC;
+  } else if (_dfu_ctx.state == DFU_MANIFEST)
   {
-    _dfu_state_ctx.state = ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
+    _dfu_ctx.state = ((_dfu_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
                            ? DFU_MANIFEST_WAIT_RESET : DFU_MANIFEST_SYNC;
   }
 }
@@ -351,9 +360,9 @@ void tud_dfu_download_complete(void)
 static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * request)
 {
   TU_LOG2("  DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest));
-  TU_LOG2("  DFU State Machine: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_state_ctx.state));
+  TU_LOG2("  DFU State Machine: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state));
 
-  switch (_dfu_state_ctx.state)
+  switch (_dfu_ctx.state)
   {
     case DFU_IDLE:
     {
@@ -361,26 +370,26 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_DNLOAD:
         {
-          if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+          if( ((_dfu_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
               && (request->wLength > 0) )
           {
-            _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
-            _dfu_state_ctx.blk_transfer_in_proc = true;
+            _dfu_ctx.state = DFU_DNLOAD_SYNC;
+            _dfu_ctx.blk_transfer_in_proc = true;
             dfu_req_dnload_setup(rhport, request);
           } else {
-            _dfu_state_ctx.state = DFU_ERROR;
+            _dfu_ctx.state = DFU_ERROR;
           }
         }
         break;
 
         case DFU_REQUEST_UPLOAD:
         {
-          if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK) != 0) )
+          if( ((_dfu_ctx.attrs & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK) != 0) )
           {
-            _dfu_state_ctx.state = DFU_UPLOAD_IDLE;
+            _dfu_ctx.state = DFU_UPLOAD_IDLE;
             dfu_req_upload(rhport, request, request->wValue, request->wLength);
           } else {
-            _dfu_state_ctx.state = DFU_ERROR;
+            _dfu_ctx.state = DFU_ERROR;
           }
         }
         break;
@@ -398,7 +407,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         break;
 
         default:
-          _dfu_state_ctx.state = DFU_ERROR;
+          _dfu_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
         break;
       }
@@ -411,13 +420,13 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_GETSTATUS:
         {
-          if ( _dfu_state_ctx.blk_transfer_in_proc )
+          if ( _dfu_ctx.blk_transfer_in_proc )
           {
-            _dfu_state_ctx.state = DFU_DNBUSY;
+            _dfu_ctx.state = DFU_DNBUSY;
             dfu_req_getstatus_reply(rhport, request);
             dfu_req_dnload_reply(rhport, request);
           } else {
-            _dfu_state_ctx.state = DFU_DNLOAD_IDLE;
+            _dfu_ctx.state = DFU_DNLOAD_IDLE;
             dfu_req_getstatus_reply(rhport, request);
           }
         }
@@ -428,7 +437,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         break;
 
         default:
-          _dfu_state_ctx.state = DFU_ERROR;
+          _dfu_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
         break;
       }
@@ -440,7 +449,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       switch (request->bRequest)
       {
         default:
-          _dfu_state_ctx.state = DFU_ERROR;
+          _dfu_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
         break;
       }
@@ -453,19 +462,19 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         {
           case DFU_REQUEST_DNLOAD:
           {
-            if( ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+            if( ((_dfu_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
                 && (request->wLength > 0) )
             {
-              _dfu_state_ctx.state = DFU_DNLOAD_SYNC;
-              _dfu_state_ctx.blk_transfer_in_proc = true;
+              _dfu_ctx.state = DFU_DNLOAD_SYNC;
+              _dfu_ctx.blk_transfer_in_proc = true;
               dfu_req_dnload_setup(rhport, request);
             } else {
-              if ( tud_dfu_device_data_done_check_cb(_dfu_state_ctx.alt_num) )
+              if ( tud_dfu_device_data_done_check_cb(_dfu_ctx.alt_num) )
               {
-                _dfu_state_ctx.state = DFU_MANIFEST_SYNC;
+                _dfu_ctx.state = DFU_MANIFEST_SYNC;
                 tud_control_status(rhport, request);
               } else {
-                _dfu_state_ctx.state = DFU_ERROR;
+                _dfu_ctx.state = DFU_ERROR;
                 return false;  // stall
               }
             }
@@ -483,13 +492,13 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
           case DFU_REQUEST_ABORT:
             if ( tud_dfu_abort_cb )
             {
-              tud_dfu_abort_cb(_dfu_state_ctx.alt_num);
+              tud_dfu_abort_cb(_dfu_ctx.alt_num);
             }
-            _dfu_state_ctx.state = DFU_IDLE;
+            _dfu_ctx.state = DFU_IDLE;
           break;
 
           default:
-            _dfu_state_ctx.state = DFU_ERROR;
+            _dfu_ctx.state = DFU_ERROR;
             return false;  // stall on all other requests
           break;
         }
@@ -502,15 +511,15 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_GETSTATUS:
         {
-          if ((_dfu_state_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
+          if ((_dfu_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
           {
-            _dfu_state_ctx.state = DFU_MANIFEST;
+            _dfu_ctx.state = DFU_MANIFEST;
             dfu_req_getstatus_reply(rhport, request);
           } else 
           {
-            if ( tud_dfu_firmware_valid_check_cb(_dfu_state_ctx.alt_num) )
+            if ( tud_dfu_firmware_valid_check_cb(_dfu_ctx.alt_num) )
             {
-              _dfu_state_ctx.state = DFU_IDLE;
+              _dfu_ctx.state = DFU_IDLE;
             }
             dfu_req_getstatus_reply(rhport, request);
           }
@@ -522,7 +531,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         break;
 
         default:
-          _dfu_state_ctx.state = DFU_ERROR;
+          _dfu_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
         break;
       }
@@ -562,7 +571,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         {
           if (dfu_req_upload(rhport, request, request->wValue, request->wLength) != request->wLength)
           {
-            _dfu_state_ctx.state = DFU_IDLE;
+            _dfu_ctx.state = DFU_IDLE;
           }
         }
         break;
@@ -579,9 +588,9 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         {
           if (tud_dfu_abort_cb)
           {
-            tud_dfu_abort_cb(_dfu_state_ctx.alt_num);
+            tud_dfu_abort_cb(_dfu_ctx.alt_num);
           }
-          _dfu_state_ctx.state = DFU_IDLE;
+          _dfu_ctx.state = DFU_IDLE;
         }
         break;
 
@@ -601,7 +610,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         break;
 
         case DFU_REQUEST_CLRSTATUS:
-          _dfu_state_ctx.state = DFU_IDLE;
+          _dfu_ctx.state = DFU_IDLE;
         break;
 
         case DFU_REQUEST_GETSTATE:
@@ -616,7 +625,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
     break;
 
     default:
-      _dfu_state_ctx.state = DFU_ERROR;
+      _dfu_ctx.state = DFU_ERROR;
       TU_LOG2("  DFU ERROR: Unexpected state\r\nStalling control pipe\r\n");
       return false;  // Unexpected state, stall and change to error
   }

From 95ded08e3b96b77bbbb1e11e7f0043fb86b7316f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jul 2021 16:42:12 +0700
Subject: [PATCH 0203/2085] simplify upload request

---
 src/class/dfu/dfu.h        |  8 ++--
 src/class/dfu/dfu_device.c | 88 ++++++++++++++++----------------------
 src/common/tusb_types.h    |  2 +-
 3 files changed, 43 insertions(+), 55 deletions(-)

diff --git a/src/class/dfu/dfu.h b/src/class/dfu/dfu.h
index 18de3bf99..88f2f3529 100644
--- a/src/class/dfu/dfu.h
+++ b/src/class/dfu/dfu.h
@@ -95,10 +95,10 @@ typedef enum {
   DFU_STATUS_ERRSTALLEDPKT   = 0x0F,
 } dfu_device_status_t;
 
-#define DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK              (1 << 0)
-#define DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK                (1 << 1)
-#define DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK    (1 << 2)
-#define DFU_FUNC_ATTR_WILL_DETACH_BITMASK               (1 << 3)
+#define DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK              (1u << 0)
+#define DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK                (1u << 1)
+#define DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK    (1u << 2)
+#define DFU_FUNC_ATTR_WILL_DETACH_BITMASK               (1u << 3)
 
 // DFU Status Request Payload
 typedef struct TU_ATTR_PACKED
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 7b2f920d2..376feb053 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -58,7 +58,6 @@ CFG_TUSB_MEM_SECTION static dfu_state_ctx_t _dfu_ctx;
 
 static void     dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const * request);
 static void     dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const * request);
-static uint16_t dfu_req_upload(uint8_t rhport, tusb_control_request_t const * request, uint16_t block_num, uint16_t wLength);
 static void     dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request);
 static bool     dfu_state_machine(uint8_t rhport, tusb_control_request_t const * request);
 
@@ -218,37 +217,60 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
   if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD )
   {
     // Standard request include GET/SET_INTERFACE
-    switch (request->bRequest )
+    switch ( request->bRequest )
     {
       case TUSB_REQ_SET_INTERFACE:
-        // Switch Alt interface and  Re-initalize state machine
-        _dfu_ctx.alt_num = (uint8_t) request->wValue;
-        _dfu_ctx.state = DFU_IDLE;
-        _dfu_ctx.status = DFU_STATUS_OK;
-        _dfu_ctx.blk_transfer_in_proc = false;
+        if ( stage == CONTROL_STAGE_SETUP )
+        {
+          // Switch Alt interface and  Re-initalize state machine
+          _dfu_ctx.alt_num = (uint8_t) request->wValue;
+          _dfu_ctx.state = DFU_IDLE;
+          _dfu_ctx.status = DFU_STATUS_OK;
+          _dfu_ctx.blk_transfer_in_proc = false;
 
-        return tud_control_status(rhport, request);
+          return tud_control_status(rhport, request);
+        }
       break;
 
       case TUSB_REQ_GET_INTERFACE:
-        return tud_control_xfer(rhport, request, &_dfu_ctx.alt_num, 1);
+        if(stage == CONTROL_STAGE_SETUP)
+        {
+          return tud_control_xfer(rhport, request, &_dfu_ctx.alt_num, 1);
+        }
       break;
 
       // unsupported request
       default: return false;
     }
   }
-  else if (request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS)
+  else if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS )
   {
     // Class request
-    switch (request->bRequest)
+    switch ( request->bRequest )
     {
       case DFU_REQUEST_DETACH:
-      {
-        tud_control_status(rhport, request);
-        if (tud_dfu_detach_cb) tud_dfu_detach_cb();
-        break;
-      }
+        if ( stage == CONTROL_STAGE_SETUP )
+        {
+          tud_control_status(rhport, request);
+        }
+        else if ( stage == CONTROL_STAGE_ACK )
+        {
+          if (tud_dfu_detach_cb) tud_dfu_detach_cb();
+        }
+      break;
+
+      case DFU_REQUEST_UPLOAD:
+        if ( stage == CONTROL_STAGE_SETUP )
+        {
+          TU_VERIFY(_dfu_ctx.attrs & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK);
+          TU_VERIFY(tud_dfu_upload_cb);
+          TU_VERIFY(request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
+
+          uint16_t const xfer_len = tud_dfu_upload_cb(_dfu_ctx.alt_num, request->wValue, _dfu_ctx.transfer_buf, request->wLength);
+
+          tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, xfer_len);
+        }
+      break;
 
       case DFU_REQUEST_DNLOAD:
       {
@@ -262,7 +284,6 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
         }
       }
       // fallthrough
-      case DFU_REQUEST_UPLOAD:
       case DFU_REQUEST_GETSTATUS:
       case DFU_REQUEST_CLRSTATUS:
       case DFU_REQUEST_GETSTATE:
@@ -290,18 +311,6 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
   return true;
 }
 
-static uint16_t dfu_req_upload(uint8_t rhport, tusb_control_request_t const * request, uint16_t block_num, uint16_t wLength)
-{
-  TU_VERIFY( wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, 0);
-  uint16_t retval = 0;
-  if (tud_dfu_upload_cb)
-  {
-    tud_dfu_upload_cb(_dfu_ctx.alt_num, block_num, (uint8_t *)_dfu_ctx.transfer_buf, wLength);
-  }
-  tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, retval);
-  return retval;
-}
-
 static void dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const * request)
 {
   uint32_t timeout = 0;
@@ -382,18 +391,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         }
         break;
 
-        case DFU_REQUEST_UPLOAD:
-        {
-          if( ((_dfu_ctx.attrs & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK) != 0) )
-          {
-            _dfu_ctx.state = DFU_UPLOAD_IDLE;
-            dfu_req_upload(rhport, request, request->wValue, request->wLength);
-          } else {
-            _dfu_ctx.state = DFU_ERROR;
-          }
-        }
-        break;
-
         case DFU_REQUEST_GETSTATUS:
           dfu_req_getstatus_reply(rhport, request);
         break;
@@ -567,15 +564,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
     {
       switch (request->bRequest)
       {
-        case DFU_REQUEST_UPLOAD:
-        {
-          if (dfu_req_upload(rhport, request, request->wValue, request->wLength) != request->wLength)
-          {
-            _dfu_ctx.state = DFU_IDLE;
-          }
-        }
-        break;
-
         case DFU_REQUEST_GETSTATUS:
           dfu_req_getstatus_reply(rhport, request);
         break;
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index ec58a3181..fc1035e2c 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -449,7 +449,7 @@ typedef struct TU_ATTR_PACKED
 /*------------------------------------------------------------------*/
 /* Types
  *------------------------------------------------------------------*/
-typedef struct TU_ATTR_PACKED{
+typedef struct TU_ATTR_PACKED TU_ATTR_ALIGNED(4) {
   union {
     struct TU_ATTR_PACKED {
       uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.

From 6a68fc699724fb216b745dbf48fdae32305f1d35 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jul 2021 16:51:28 +0700
Subject: [PATCH 0204/2085] update dfu abort

---
 src/class/dfu/dfu_device.c | 39 +++++++++++++-------------------------
 1 file changed, 13 insertions(+), 26 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 376feb053..ed36178f1 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -259,6 +259,19 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
         }
       break;
 
+      case DFU_REQUEST_ABORT:
+        if ( stage == CONTROL_STAGE_SETUP )
+        {
+          if (tud_dfu_abort_cb) tud_dfu_abort_cb(_dfu_ctx.alt_num);
+
+          _dfu_ctx.state = DFU_IDLE;
+          _dfu_ctx.status = DFU_STATUS_OK;
+          _dfu_ctx.blk_transfer_in_proc = false;
+
+          tud_control_status(rhport, request);
+        }
+      break;
+
       case DFU_REQUEST_UPLOAD:
         if ( stage == CONTROL_STAGE_SETUP )
         {
@@ -287,7 +300,6 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
       case DFU_REQUEST_GETSTATUS:
       case DFU_REQUEST_CLRSTATUS:
       case DFU_REQUEST_GETSTATE:
-      case DFU_REQUEST_ABORT:
       {
         if(stage == CONTROL_STAGE_SETUP)
         {
@@ -297,10 +309,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
       break;
 
       default:
-      {
-        TU_LOG2("  DFU Nonstandard Request: %u\r\n", request->bRequest);
         return false; // stall unsupported request
-      }
       break;
     }
   }else
@@ -399,10 +408,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
           dfu_req_getstate_reply(rhport, request);
         break;
 
-        case DFU_REQUEST_ABORT:
-          ; // do nothing, but don't stall so continue on
-        break;
-
         default:
           _dfu_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
@@ -486,14 +491,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
             dfu_req_getstate_reply(rhport, request);
           break;
 
-          case DFU_REQUEST_ABORT:
-            if ( tud_dfu_abort_cb )
-            {
-              tud_dfu_abort_cb(_dfu_ctx.alt_num);
-            }
-            _dfu_ctx.state = DFU_IDLE;
-          break;
-
           default:
             _dfu_ctx.state = DFU_ERROR;
             return false;  // stall on all other requests
@@ -572,16 +569,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
           dfu_req_getstate_reply(rhport, request);
         break;
 
-        case DFU_REQUEST_ABORT:
-        {
-          if (tud_dfu_abort_cb)
-          {
-            tud_dfu_abort_cb(_dfu_ctx.alt_num);
-          }
-          _dfu_ctx.state = DFU_IDLE;
-        }
-        break;
-
         default:
           return false;  // stall on all other requests
         break;

From b4fde90b5518c4e92750af2e27eae598267ad8cf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jul 2021 17:03:20 +0700
Subject: [PATCH 0205/2085] update clear status and get state

---
 src/class/dfu/dfu_device.c | 68 ++++++++++++++------------------------
 1 file changed, 25 insertions(+), 43 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index ed36178f1..686d9b023 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -61,6 +61,13 @@ static void     dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t c
 static void     dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request);
 static bool     dfu_state_machine(uint8_t rhport, tusb_control_request_t const * request);
 
+static void reset_state(void)
+{
+  _dfu_ctx.state = DFU_IDLE;
+  _dfu_ctx.status = DFU_STATUS_OK;
+  _dfu_ctx.blk_transfer_in_proc = false;
+}
+
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
@@ -224,10 +231,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
         {
           // Switch Alt interface and  Re-initalize state machine
           _dfu_ctx.alt_num = (uint8_t) request->wValue;
-          _dfu_ctx.state = DFU_IDLE;
-          _dfu_ctx.status = DFU_STATUS_OK;
-          _dfu_ctx.blk_transfer_in_proc = false;
-
+          reset_state();
           return tud_control_status(rhport, request);
         }
       break;
@@ -264,14 +268,26 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
         {
           if (tud_dfu_abort_cb) tud_dfu_abort_cb(_dfu_ctx.alt_num);
 
-          _dfu_ctx.state = DFU_IDLE;
-          _dfu_ctx.status = DFU_STATUS_OK;
-          _dfu_ctx.blk_transfer_in_proc = false;
-
+          reset_state();
           tud_control_status(rhport, request);
         }
       break;
 
+      case DFU_REQUEST_CLRSTATUS:
+        if ( stage == CONTROL_STAGE_SETUP )
+        {
+          reset_state();
+          tud_control_status(rhport, request);
+        }
+      break;
+
+      case DFU_REQUEST_GETSTATE:
+        if ( stage == CONTROL_STAGE_SETUP )
+        {
+          tud_control_xfer(rhport, request, &_dfu_ctx.state, 1);
+        }
+      break;
+
       case DFU_REQUEST_UPLOAD:
         if ( stage == CONTROL_STAGE_SETUP )
         {
@@ -298,8 +314,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
       }
       // fallthrough
       case DFU_REQUEST_GETSTATUS:
-      case DFU_REQUEST_CLRSTATUS:
-      case DFU_REQUEST_GETSTATE:
+
       {
         if(stage == CONTROL_STAGE_SETUP)
         {
@@ -339,11 +354,6 @@ static void dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const
   tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_req_payload_t));
 }
 
-static void dfu_req_getstate_reply(uint8_t rhport, tusb_control_request_t const * request)
-{
-  tud_control_xfer(rhport, request, &_dfu_ctx.state, 1);
-}
-
 static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const * request)
 {
   // TODO: add "zero" copy mode so the buffer we read into can be provided by the user
@@ -404,10 +414,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
           dfu_req_getstatus_reply(rhport, request);
         break;
 
-        case DFU_REQUEST_GETSTATE:
-          dfu_req_getstate_reply(rhport, request);
-        break;
-
         default:
           _dfu_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
@@ -434,10 +440,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         }
         break;
 
-        case DFU_REQUEST_GETSTATE:
-          dfu_req_getstate_reply(rhport, request);
-        break;
-
         default:
           _dfu_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
@@ -487,10 +489,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
             dfu_req_getstatus_reply(rhport, request);
           break;
 
-          case DFU_REQUEST_GETSTATE:
-            dfu_req_getstate_reply(rhport, request);
-          break;
-
           default:
             _dfu_ctx.state = DFU_ERROR;
             return false;  // stall on all other requests
@@ -520,10 +518,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         }
         break;
 
-        case DFU_REQUEST_GETSTATE:
-          dfu_req_getstate_reply(rhport, request);
-        break;
-
         default:
           _dfu_ctx.state = DFU_ERROR;
           return false;  // stall on all other requests
@@ -565,10 +559,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
           dfu_req_getstatus_reply(rhport, request);
         break;
 
-        case DFU_REQUEST_GETSTATE:
-          dfu_req_getstate_reply(rhport, request);
-        break;
-
         default:
           return false;  // stall on all other requests
         break;
@@ -584,14 +574,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
           dfu_req_getstatus_reply(rhport, request);
         break;
 
-        case DFU_REQUEST_CLRSTATUS:
-          _dfu_ctx.state = DFU_IDLE;
-        break;
-
-        case DFU_REQUEST_GETSTATE:
-          dfu_req_getstate_reply(rhport, request);
-        break;
-
         default:
           return false;  // stall on all other requests
         break;

From daca9e520bce0b4eb5882c5692986ec5c513f319 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Jul 2021 20:47:50 +0700
Subject: [PATCH 0206/2085] wrap up DFU update

---
 examples/device/dfu/src/main.c            |  95 ++++--
 examples/device/dfu/src/tusb_config.h     |   2 +-
 examples/device/dfu/src/usb_descriptors.c |   4 +-
 src/class/dfu/dfu.h                       |  47 +--
 src/class/dfu/dfu_device.c                | 397 ++++++++++++++--------
 src/class/dfu/dfu_device.h                |  62 ++--
 src/class/dfu/dfu_rt_device.c             |   6 +-
 src/common/tusb_types.h                   |   2 +-
 src/device/usbd.c                         |   2 +-
 src/tusb_option.h                         |   4 -
 10 files changed, 367 insertions(+), 254 deletions(-)

diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 2c114c5a2..1621a330b 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -26,7 +26,7 @@
  /*
   * After device is enumerated in dfu mode run the following commands
   *
-  * To transfer firmware from host to device:
+  * To transfer firmware from host to device (best to test with text file)
   *
   * $ dfu-util -d cafe -a 0 -D [filename]
   * $ dfu-util -d cafe -a 1 -D [filename]
@@ -45,22 +45,21 @@
 #include "bsp/board.h"
 #include "tusb.h"
 
-
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
-#ifndef DFU_VERBOSE
-#define DFU_VERBOSE 0
-#endif
+const char* upload_image[2]=
+{
+  "Hello world from TinyUSB DFU! - Partition 0",
+  "Hello world from TinyUSB DFU! - Partition 1"
+};
 
 /* Blink pattern
- * - 1000 ms : device should reboot
  * - 250 ms  : device not mounted
  * - 1000 ms : device mounted
  * - 2500 ms : device is suspended
  */
 enum  {
-  BLINK_DFU_MODE = 100,
   BLINK_NOT_MOUNTED = 250,
   BLINK_MOUNTED = 1000,
   BLINK_SUSPENDED = 2500,
@@ -118,65 +117,87 @@ void tud_resume_cb(void)
 }
 
 //--------------------------------------------------------------------+
-// Class callbacks
+// DFU callbacks
+// Note: alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 //--------------------------------------------------------------------+
-bool tud_dfu_firmware_valid_check_cb(uint8_t alt)
-{
-  (void) alt;
-  printf("    Firmware check\r\n");
-  return true;
-}
 
-uint32_t tud_dfu_get_status_cb(uint8_t alt, uint8_t state)
+// Invoked right before tud_dfu_download_cb() (state=DFU_DNBUSY) or tud_dfu_manifest_cb() (state=DFU_MANIFEST)
+// Application return timeout in milliseconds (bwPollTimeout) for the next download/manifest operation.
+// During this period, USB host won't try to communicate with us.
+uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state)
 {
-  // For example Alt1 (EEPROM) is slow, add 2000ms timeout
   if ( state == DFU_DNBUSY )
   {
-    if (alt == 1) return 2000;
+    // For this example
+    // - Atl0 Flash is fast : 1   ms
+    // - Alt1 EEPROM is slow: 100 ms
+    return (alt == 0) ? 1 : 100;
   }
+  else if (state == DFU_MANIFEST)
+  {
+    // since we don't buffer entire image and do any flashing in manifest stage
+    return 0;
+  }
+
   return 0;
 }
 
-void tud_dfu_download_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length)
+// Invoked when received DFU_DNLOAD (wLength>0) following by DFU_GETSTATUS (state=DFU_DNBUSY) requests
+// This callback could be returned before flashing op is complete (async).
+// Once finished flashing, application must call tud_dfu_finish_flashing()
+void tud_dfu_download_cb(uint8_t alt, uint16_t wBlockNum, uint8_t const* data, uint16_t length)
 {
   (void) data;
-  printf("Received Alt %u BlockNum %u of length %u\r\n", alt, wBlockNum, length);
+  printf("\r\nReceived Alt %u BlockNum %u of length %u\r\n", alt, wBlockNum, length);
 
-#if DFU_VERBOSE
   for(uint16_t i=0; i<length; i++)
   {
-    printf("  [%u][%u]: %x\r\n", wBlockNum, i, (uint8_t)data[i]);
+    // printf("  [%u][%u]: %x\r\n", wBlockNum, i, (uint8_t)data[i]);
+    printf("%c", data[i]);
   }
-#endif
 
-  tud_dfu_download_complete();
+  // flashing op for download complete without error
+  tud_dfu_finish_flashing(DFU_STATUS_OK);
 }
 
-bool tud_dfu_device_data_done_check_cb(uint8_t alt)
+// Invoked when download process is complete, received DFU_DNLOAD (wLength=0) following by DFU_GETSTATUS (state=Manifest)
+// Application can do checksum, or actual flashing if buffered entire image previously.
+// Once finished flashing, application must call tud_dfu_finish_flashing()
+void tud_dfu_manifest_cb(uint8_t alt)
 {
   (void) alt;
-  printf("Host said no more data... Returning true\r\n");
-  return true;
+  printf("Download completed, enter manifestation\r\n");
+
+  // flashing op for manifest is complete without error
+  // Application can perform checksum, should it fail, use appropriate status such as errVERIFY.
+  tud_dfu_finish_flashing(DFU_STATUS_OK);
 }
 
+// Invoked when received DFU_UPLOAD request
+// Application must populate data with up to length bytes and
+// Return the number of written bytes
+uint16_t tud_dfu_upload_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length)
+{
+  (void) block_num;
+  (void) length;
+
+  uint16_t const xfer_len = (uint16_t) strlen(upload_image[alt]);
+  memcpy(data, upload_image[alt], xfer_len);
+
+  return xfer_len;
+}
+
+// Invoked when the Host has terminated a download or upload transfer
 void tud_dfu_abort_cb(uint8_t alt)
 {
   (void) alt;
   printf("Host aborted transfer\r\n");
 }
 
-#define UPLOAD_SIZE 43
-const uint8_t upload_test[2][UPLOAD_SIZE] = {"Hello world from TinyUSB DFU! - Partition 0",
-                                             "Hello world from TinyUSB DFU! - Partition 1"};
-
-uint16_t tud_dfu_upload_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length)
+// Invoked when a DFU_DETACH request is received
+void tud_dfu_detach_cb(void)
 {
-  (void) block_num;
-  (void) length;
-
-  memcpy(data, upload_test[alt], UPLOAD_SIZE);
-
-  return UPLOAD_SIZE;
+  printf("Host detach, we should probably reboot\r\n");
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 77d907ffc..5be58e854 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -82,7 +82,7 @@
 #define CFG_TUD_DFU_MODE    1
 
 // DFU buffer size, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
-#define CFG_TUD_DFU_TRANSFER_BUFFER_SIZE    4096
+#define CFG_TUD_DFU_TRANSFER_BUFSIZE    512
 
 #ifdef __cplusplus
  }
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 78e94194e..a15bb6136 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -92,7 +92,7 @@ enum
 
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_DFU_DESC_LEN(ALT_COUNT))
 
-#define FUNC_ATTRS (DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK | DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK)
+#define FUNC_ATTRS (DFU_ATTR_CAN_UPLOAD | DFU_ATTR_CAN_DOWNLOAD | DFU_ATTR_MANIFESTATION_TOLERANT)
 
 uint8_t const desc_configuration[] =
 {
@@ -100,7 +100,7 @@ uint8_t const desc_configuration[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
   // Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size
-  TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, ALT_COUNT, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFFER_SIZE),
+  TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, ALT_COUNT, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFSIZE),
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/src/class/dfu/dfu.h b/src/class/dfu/dfu.h
index 88f2f3529..114c827b8 100644
--- a/src/class/dfu/dfu.h
+++ b/src/class/dfu/dfu.h
@@ -36,6 +36,7 @@
 //--------------------------------------------------------------------+
 // Common Definitions
 //--------------------------------------------------------------------+
+
 // DFU Protocol
 typedef enum
 {
@@ -77,28 +78,28 @@ typedef enum {
 
 // DFU Status
 typedef enum {
-  DFU_STATUS_OK              = 0x00,
-  DFU_STATUS_ERRTARGET       = 0x01,
-  DFU_STATUS_ERRFILE         = 0x02,
-  DFU_STATUS_ERRWRITE        = 0x03,
-  DFU_STATUS_ERRERASE        = 0x04,
-  DFU_STATUS_ERRCHECK_ERASED = 0x05,
-  DFU_STATUS_ERRPROG         = 0x06,
-  DFU_STATUS_ERRVERIFY       = 0x07,
-  DFU_STATUS_ERRADDRESS      = 0x08,
-  DFU_STATUS_ERRNOTDONE      = 0x09,
-  DFU_STATUS_ERRFIRMWARE     = 0x0A,
-  DFU_STATUS_ERRVENDOR       = 0x0B,
-  DFU_STATUS_ERRUSBR         = 0x0C,
-  DFU_STATUS_ERRPOR          = 0x0D,
-  DFU_STATUS_ERRUNKNOWN      = 0x0E,
-  DFU_STATUS_ERRSTALLEDPKT   = 0x0F,
-} dfu_device_status_t;
+  DFU_STATUS_OK               = 0x00,
+  DFU_STATUS_ERR_TARGET       = 0x01,
+  DFU_STATUS_ERR_FILE         = 0x02,
+  DFU_STATUS_ERR_WRITE        = 0x03,
+  DFU_STATUS_ERR_ERASE        = 0x04,
+  DFU_STATUS_ERR_CHECK_ERASED = 0x05,
+  DFU_STATUS_ERR_PROG         = 0x06,
+  DFU_STATUS_ERR_VERIFY       = 0x07,
+  DFU_STATUS_ERR_ADDRESS      = 0x08,
+  DFU_STATUS_ERR_NOTDONE      = 0x09,
+  DFU_STATUS_ERR_FIRMWARE     = 0x0A,
+  DFU_STATUS_ERR_VENDOR       = 0x0B,
+  DFU_STATUS_ERR_USBR         = 0x0C,
+  DFU_STATUS_ERR_POR          = 0x0D,
+  DFU_STATUS_ERR_UNKNOWN      = 0x0E,
+  DFU_STATUS_ERR_STALLEDPKT   = 0x0F,
+} dfu_status_t;
 
-#define DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK              (1u << 0)
-#define DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK                (1u << 1)
-#define DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK    (1u << 2)
-#define DFU_FUNC_ATTR_WILL_DETACH_BITMASK               (1u << 3)
+#define DFU_ATTR_CAN_DOWNLOAD              (1u << 0)
+#define DFU_ATTR_CAN_UPLOAD                (1u << 1)
+#define DFU_ATTR_MANIFESTATION_TOLERANT    (1u << 2)
+#define DFU_ATTR_WILL_DETACH               (1u << 3)
 
 // DFU Status Request Payload
 typedef struct TU_ATTR_PACKED
@@ -107,9 +108,9 @@ typedef struct TU_ATTR_PACKED
   uint8_t bwPollTimeout[3];
   uint8_t bState;
   uint8_t iString;
-} dfu_status_req_payload_t;
+} dfu_status_response_t;
 
-TU_VERIFY_STATIC( sizeof(dfu_status_req_payload_t) == 6, "size is not correct");
+TU_VERIFY_STATIC( sizeof(dfu_status_response_t) == 6, "size is not correct");
 
 #ifdef __cplusplus
  }
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 686d9b023..3aa90f5c5 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -42,32 +42,33 @@
 //--------------------------------------------------------------------+
 typedef struct
 {
-    dfu_device_status_t status;
-    dfu_state_t state;
-    uint8_t attrs;
-    bool blk_transfer_in_proc;
-    uint8_t alt_num;
-    uint16_t block;
-    uint16_t length;
-    CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_TRANSFER_BUFFER_SIZE];
+  uint8_t attrs;
+  uint8_t alt;
+
+  dfu_state_t state;
+  dfu_status_t status;
+
+  bool flashing_in_progress;
+  uint16_t block;
+  uint16_t length;
+
+  CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_TRANSFER_BUFSIZE];
 } dfu_state_ctx_t;
 
 // Only a single dfu state is allowed
 CFG_TUSB_MEM_SECTION static dfu_state_ctx_t _dfu_ctx;
 
-
-static void     dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const * request);
-static void     dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const * request);
-static void     dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request);
-static bool     dfu_state_machine(uint8_t rhport, tusb_control_request_t const * request);
-
 static void reset_state(void)
 {
   _dfu_ctx.state = DFU_IDLE;
   _dfu_ctx.status = DFU_STATUS_OK;
-  _dfu_ctx.blk_transfer_in_proc = false;
+  _dfu_ctx.flashing_in_progress = false;
 }
 
+static bool reply_getstatus(uint8_t rhport, tusb_control_request_t const * request, dfu_state_t state, dfu_status_t status, uint32_t timeout);
+static bool process_download_get_status(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
@@ -75,13 +76,13 @@ static void reset_state(void)
 
 static tu_lookup_entry_t const _dfu_request_lookup[] =
 {
-  { .key = DFU_REQUEST_DETACH         , .data = "DETACH" },
-  { .key = DFU_REQUEST_DNLOAD         , .data = "DNLOAD" },
-  { .key = DFU_REQUEST_UPLOAD         , .data = "UPLOAD" },
+  { .key = DFU_REQUEST_DETACH         , .data = "DETACH"    },
+  { .key = DFU_REQUEST_DNLOAD         , .data = "DNLOAD"    },
+  { .key = DFU_REQUEST_UPLOAD         , .data = "UPLOAD"    },
   { .key = DFU_REQUEST_GETSTATUS      , .data = "GETSTATUS" },
   { .key = DFU_REQUEST_CLRSTATUS      , .data = "CLRSTATUS" },
-  { .key = DFU_REQUEST_GETSTATE       , .data = "GETSTATE" },
-  { .key = DFU_REQUEST_ABORT          , .data = "ABORT" },
+  { .key = DFU_REQUEST_GETSTATE       , .data = "GETSTATE"  },
+  { .key = DFU_REQUEST_ABORT          , .data = "ABORT"     },
 };
 
 static tu_lookup_table_t const _dfu_request_table =
@@ -92,17 +93,17 @@ static tu_lookup_table_t const _dfu_request_table =
 
 static tu_lookup_entry_t const _dfu_state_lookup[] =
 {
-  { .key = APP_IDLE                   , .data = "APP_IDLE" },
-  { .key = APP_DETACH                 , .data = "APP_DETACH" },
-  { .key = DFU_IDLE                   , .data = "DFU_IDLE" },
-  { .key = DFU_DNLOAD_SYNC            , .data = "DFU_DNLOAD_SYNC" },
-  { .key = DFU_DNBUSY                 , .data = "DFU_DNBUSY" },
-  { .key = DFU_DNLOAD_IDLE            , .data = "DFU_DNLOAD_IDLE" },
-  { .key = DFU_MANIFEST_SYNC          , .data = "DFU_MANIFEST_SYNC" },
-  { .key = DFU_MANIFEST               , .data = "DFU_MANIFEST" },
-  { .key = DFU_MANIFEST_WAIT_RESET    , .data = "DFU_MANIFEST_WAIT_RESET" },
-  { .key = DFU_UPLOAD_IDLE            , .data = "DFU_UPLOAD_IDLE" },
-  { .key = DFU_ERROR                  , .data = "DFU_ERROR" },
+  { .key = APP_IDLE                   , .data = "APP_IDLE"                },
+  { .key = APP_DETACH                 , .data = "APP_DETACH"              },
+  { .key = DFU_IDLE                   , .data = "IDLE"                },
+  { .key = DFU_DNLOAD_SYNC            , .data = "DNLOAD_SYNC"         },
+  { .key = DFU_DNBUSY                 , .data = "DNBUSY"              },
+  { .key = DFU_DNLOAD_IDLE            , .data = "DNLOAD_IDLE"         },
+  { .key = DFU_MANIFEST_SYNC          , .data = "MANIFEST_SYNC"       },
+  { .key = DFU_MANIFEST               , .data = "MANIFEST"            },
+  { .key = DFU_MANIFEST_WAIT_RESET    , .data = "MANIFEST_WAIT_RESET" },
+  { .key = DFU_UPLOAD_IDLE            , .data = "UPLOAD_IDLE"         },
+  { .key = DFU_ERROR                  , .data = "ERROR"               },
 };
 
 static tu_lookup_table_t const _dfu_state_table =
@@ -113,22 +114,22 @@ static tu_lookup_table_t const _dfu_state_table =
 
 static tu_lookup_entry_t const _dfu_status_lookup[] =
 {
-  { .key = DFU_STATUS_OK              , .data = "OK" },
-  { .key = DFU_STATUS_ERRTARGET       , .data = "errTARGET" },
-  { .key = DFU_STATUS_ERRFILE         , .data = "errFILE" },
-  { .key = DFU_STATUS_ERRWRITE        , .data = "errWRITE" },
-  { .key = DFU_STATUS_ERRERASE        , .data = "errERASE" },
-  { .key = DFU_STATUS_ERRCHECK_ERASED , .data = "errCHECK_ERASED" },
-  { .key = DFU_STATUS_ERRPROG         , .data = "errPROG" },
-  { .key = DFU_STATUS_ERRVERIFY       , .data = "errVERIFY" },
-  { .key = DFU_STATUS_ERRADDRESS      , .data = "errADDRESS" },
-  { .key = DFU_STATUS_ERRNOTDONE      , .data = "errNOTDONE" },
-  { .key = DFU_STATUS_ERRFIRMWARE     , .data = "errFIRMWARE" },
-  { .key = DFU_STATUS_ERRVENDOR       , .data = "errVENDOR" },
-  { .key = DFU_STATUS_ERRUSBR         , .data = "errUSBR" },
-  { .key = DFU_STATUS_ERRPOR          , .data = "errPOR" },
-  { .key = DFU_STATUS_ERRUNKNOWN      , .data = "errUNKNOWN" },
-  { .key = DFU_STATUS_ERRSTALLEDPKT   , .data = "errSTALLEDPKT" },
+  { .key = DFU_STATUS_OK               , .data = "OK"              },
+  { .key = DFU_STATUS_ERR_TARGET       , .data = "errTARGET"       },
+  { .key = DFU_STATUS_ERR_FILE         , .data = "errFILE"         },
+  { .key = DFU_STATUS_ERR_WRITE        , .data = "errWRITE"        },
+  { .key = DFU_STATUS_ERR_ERASE        , .data = "errERASE"        },
+  { .key = DFU_STATUS_ERR_CHECK_ERASED , .data = "errCHECK_ERASED" },
+  { .key = DFU_STATUS_ERR_PROG         , .data = "errPROG"         },
+  { .key = DFU_STATUS_ERR_VERIFY       , .data = "errVERIFY"       },
+  { .key = DFU_STATUS_ERR_ADDRESS      , .data = "errADDRESS"      },
+  { .key = DFU_STATUS_ERR_NOTDONE      , .data = "errNOTDONE"      },
+  { .key = DFU_STATUS_ERR_FIRMWARE     , .data = "errFIRMWARE"     },
+  { .key = DFU_STATUS_ERR_VENDOR       , .data = "errVENDOR"       },
+  { .key = DFU_STATUS_ERR_USBR         , .data = "errUSBR"         },
+  { .key = DFU_STATUS_ERR_POR          , .data = "errPOR"          },
+  { .key = DFU_STATUS_ERR_UNKNOWN      , .data = "errUNKNOWN"      },
+  { .key = DFU_STATUS_ERR_STALLEDPKT   , .data = "errSTALLEDPKT"   },
 };
 
 static tu_lookup_table_t const _dfu_status_table =
@@ -139,38 +140,22 @@ static tu_lookup_table_t const _dfu_status_table =
 
 #endif
 
-#define dfu_debug_print_context()                                              \
-{                                                                              \
-  TU_LOG2("  DFU at State: %s\r\n         Status: %s\r\n",                     \
-          tu_lookup_find(&_dfu_state_table, _dfu_ctx.state),        \
-          tu_lookup_find(&_dfu_status_table, _dfu_ctx.status) );    \
-}
-
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
-void dfu_moded_init(void)
-{
-  _dfu_ctx.state = DFU_IDLE;
-  _dfu_ctx.status = DFU_STATUS_OK;
-  _dfu_ctx.attrs = 0;
-  _dfu_ctx.blk_transfer_in_proc = false;
-  _dfu_ctx.alt_num = 0;
-
-  dfu_debug_print_context();
-}
-
 void dfu_moded_reset(uint8_t rhport)
 {
   (void) rhport;
 
-  _dfu_ctx.state = DFU_IDLE;
-  _dfu_ctx.status = DFU_STATUS_OK;
   _dfu_ctx.attrs = 0;
-  _dfu_ctx.blk_transfer_in_proc = false;
-  _dfu_ctx.alt_num = 0;
+  _dfu_ctx.alt = 0;
 
-  dfu_debug_print_context();
+  reset_state();
+}
+
+void dfu_moded_init(void)
+{
+  dfu_moded_reset(0);
 }
 
 uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
@@ -204,9 +189,9 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
 
   _dfu_ctx.attrs = func_desc->bAttributes;
 
-  // CFG_TUD_DFU_TRANSFER_BUFFER_SIZE has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
+  // CFG_TUD_DFU_TRANSFER_BUFSIZE has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
   uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16(&func_desc->wTransferSize) );
-  TU_ASSERT(transfer_size <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, drv_len);
+  TU_ASSERT(transfer_size <= CFG_TUD_DFU_TRANSFER_BUFSIZE, drv_len);
 
   return drv_len;
 }
@@ -216,11 +201,10 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
 // return false to stall control endpoint (e.g unsupported request)
 bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
 {
-  // nothing to do with DATA stage
-  if ( stage == CONTROL_STAGE_DATA ) return true;
-
   TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
 
+  TU_LOG2("  DFU State  : %s, Status: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state), tu_lookup_find(&_dfu_status_table, _dfu_ctx.status));
+
   if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD )
   {
     // Standard request include GET/SET_INTERFACE
@@ -229,8 +213,8 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
       case TUSB_REQ_SET_INTERFACE:
         if ( stage == CONTROL_STAGE_SETUP )
         {
-          // Switch Alt interface and  Re-initalize state machine
-          _dfu_ctx.alt_num = (uint8_t) request->wValue;
+          // Switch Alt interface and reset state machine
+          _dfu_ctx.alt = (uint8_t) request->wValue;
           reset_state();
           return tud_control_status(rhport, request);
         }
@@ -239,7 +223,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
       case TUSB_REQ_GET_INTERFACE:
         if(stage == CONTROL_STAGE_SETUP)
         {
-          return tud_control_xfer(rhport, request, &_dfu_ctx.alt_num, 1);
+          return tud_control_xfer(rhport, request, &_dfu_ctx.alt, 1);
         }
       break;
 
@@ -249,6 +233,8 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
   }
   else if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS )
   {
+    TU_LOG2("  DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest));
+
     // Class request
     switch ( request->bRequest )
     {
@@ -259,17 +245,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
         }
         else if ( stage == CONTROL_STAGE_ACK )
         {
-          if (tud_dfu_detach_cb) tud_dfu_detach_cb();
-        }
-      break;
-
-      case DFU_REQUEST_ABORT:
-        if ( stage == CONTROL_STAGE_SETUP )
-        {
-          if (tud_dfu_abort_cb) tud_dfu_abort_cb(_dfu_ctx.alt_num);
-
-          reset_state();
-          tud_control_status(rhport, request);
+          if ( tud_dfu_detach_cb ) tud_dfu_detach_cb();
         }
       break;
 
@@ -288,44 +264,78 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
         }
       break;
 
+      case DFU_REQUEST_ABORT:
+        if ( stage == CONTROL_STAGE_SETUP )
+        {
+          reset_state();
+          tud_control_status(rhport, request);
+        }
+        else if ( stage == CONTROL_STAGE_ACK )
+        {
+          if ( tud_dfu_abort_cb ) tud_dfu_abort_cb(_dfu_ctx.alt);
+        }
+      break;
+
       case DFU_REQUEST_UPLOAD:
         if ( stage == CONTROL_STAGE_SETUP )
         {
-          TU_VERIFY(_dfu_ctx.attrs & DFU_FUNC_ATTR_CAN_UPLOAD_BITMASK);
+          TU_VERIFY(_dfu_ctx.attrs & DFU_ATTR_CAN_UPLOAD);
           TU_VERIFY(tud_dfu_upload_cb);
-          TU_VERIFY(request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE);
+          TU_VERIFY(request->wLength <= CFG_TUD_DFU_TRANSFER_BUFSIZE);
 
-          uint16_t const xfer_len = tud_dfu_upload_cb(_dfu_ctx.alt_num, request->wValue, _dfu_ctx.transfer_buf, request->wLength);
+          uint16_t const xfer_len = tud_dfu_upload_cb(_dfu_ctx.alt, request->wValue, _dfu_ctx.transfer_buf, request->wLength);
 
-          tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, xfer_len);
+          return tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, xfer_len);
         }
       break;
 
       case DFU_REQUEST_DNLOAD:
-      {
-        if ( (stage == CONTROL_STAGE_ACK)
-             && ((_dfu_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
-             && (_dfu_ctx.state == DFU_DNLOAD_SYNC))
+        if ( stage == CONTROL_STAGE_SETUP )
         {
-          _dfu_ctx.block = request->wValue;
+          TU_VERIFY(_dfu_ctx.attrs & DFU_ATTR_CAN_DOWNLOAD);
+          TU_VERIFY(_dfu_ctx.state == DFU_IDLE || _dfu_ctx.state == DFU_DNLOAD_IDLE);
+          TU_VERIFY(request->wLength <= CFG_TUD_DFU_TRANSFER_BUFSIZE);
+
+          // set to true for both download and manifest
+          _dfu_ctx.flashing_in_progress = true;
+
+          // save block and length for flashing
+          _dfu_ctx.block  = request->wValue;
           _dfu_ctx.length = request->wLength;
-          return true;
+
+          if ( request->wLength )
+          {
+            // Download with payload -> transition to DOWNLOAD SYNC
+            _dfu_ctx.state = DFU_DNLOAD_SYNC;
+            return tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, request->wLength);
+          }
+          else
+          {
+            // Download is complete -> transition to MANIFEST SYNC
+            _dfu_ctx.state = DFU_MANIFEST_SYNC;
+            return tud_control_status(rhport, request);
+          }
         }
-      }
-      // fallthrough
+      break;
+
       case DFU_REQUEST_GETSTATUS:
-
-      {
-        if(stage == CONTROL_STAGE_SETUP)
+        switch ( _dfu_ctx.state )
         {
-          return dfu_state_machine(rhport, request);
+          case DFU_DNLOAD_SYNC:
+            return process_download_get_status(rhport, stage, request);
+          break;
+
+          case DFU_MANIFEST_SYNC:
+            return process_manifest_get_status(rhport, stage, request);
+          break;
+
+          default:
+            if ( stage == CONTROL_STAGE_SETUP ) return reply_getstatus(rhport, request, _dfu_ctx.state, _dfu_ctx.status, 0);
+          break;
         }
-      }
       break;
 
-      default:
-        return false; // stall unsupported request
-      break;
+      default: return false; // stall unsupported request
     }
   }else
   {
@@ -335,32 +345,130 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
   return true;
 }
 
-static void dfu_req_getstatus_reply(uint8_t rhport, tusb_control_request_t const * request)
+void tud_dfu_finish_flashing(uint8_t status)
 {
-  uint32_t timeout = 0;
-  if ( tud_dfu_get_status_cb )
+  _dfu_ctx.flashing_in_progress = false;
+
+  if ( status == DFU_STATUS_OK )
   {
-    timeout = tud_dfu_get_status_cb(_dfu_ctx.alt_num, _dfu_ctx.state);
+    if (_dfu_ctx.state == DFU_DNBUSY)
+    {
+      _dfu_ctx.state = DFU_DNLOAD_SYNC;
+    }
+    else if (_dfu_ctx.state == DFU_MANIFEST)
+    {
+      _dfu_ctx.state = (_dfu_ctx.attrs & DFU_ATTR_MANIFESTATION_TOLERANT)
+                               ? DFU_MANIFEST_SYNC : DFU_MANIFEST_WAIT_RESET;
+    }
+  }
+  else
+  {
+    // failed while flashing, move to dfuError
+    _dfu_ctx.state = DFU_ERROR;
+    _dfu_ctx.status = status;
+  }
+}
+
+static bool process_download_get_status(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
+{
+  if ( stage == CONTROL_STAGE_SETUP )
+  {
+    // only transition to next state on CONTROL_STAGE_ACK
+    dfu_state_t next_state;
+    uint32_t timeout;
+
+    if ( _dfu_ctx.flashing_in_progress )
+    {
+      next_state = DFU_DNBUSY;
+      timeout = tud_dfu_get_timeout_cb(_dfu_ctx.alt, (uint8_t) next_state);
+    }
+    else
+    {
+      next_state = DFU_DNLOAD_IDLE;
+      timeout = 0;
+    }
+
+    return reply_getstatus(rhport, request, next_state, _dfu_ctx.status, timeout);
+  }
+  else if ( stage == CONTROL_STAGE_ACK )
+  {
+    if ( _dfu_ctx.flashing_in_progress )
+    {
+      _dfu_ctx.state = DFU_DNBUSY;
+      tud_dfu_download_cb(_dfu_ctx.alt, _dfu_ctx.block, _dfu_ctx.transfer_buf, _dfu_ctx.length);
+    }else
+    {
+      _dfu_ctx.state = DFU_DNLOAD_IDLE;
+    }
   }
 
-  dfu_status_req_payload_t resp;
-  resp.bStatus = _dfu_ctx.status;
+  return true;
+}
+
+static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
+{
+  if ( stage == CONTROL_STAGE_SETUP )
+  {
+    // only transition to next state on CONTROL_STAGE_ACK
+    dfu_state_t next_state;
+    uint32_t timeout;
+
+    if ( _dfu_ctx.flashing_in_progress )
+    {
+      next_state = DFU_MANIFEST;
+      timeout = tud_dfu_get_timeout_cb(_dfu_ctx.alt, next_state);
+    }
+    else
+    {
+      next_state = DFU_IDLE;
+      timeout = 0;
+    }
+
+    return reply_getstatus(rhport, request, next_state, _dfu_ctx.status, timeout);
+  }
+  else if ( stage == CONTROL_STAGE_ACK )
+  {
+    if ( _dfu_ctx.flashing_in_progress )
+    {
+      _dfu_ctx.state = DFU_MANIFEST;
+      tud_dfu_manifest_cb(_dfu_ctx.alt);
+    }
+    else
+    {
+      _dfu_ctx.state = DFU_IDLE;
+    }
+  }
+
+  return true;
+}
+
+static bool reply_getstatus(uint8_t rhport, tusb_control_request_t const * request, dfu_state_t state, dfu_status_t status, uint32_t timeout)
+{
+  dfu_status_response_t resp;
+  resp.bStatus          = (uint8_t) status;
   resp.bwPollTimeout[0] = TU_U32_BYTE0(timeout);
   resp.bwPollTimeout[1] = TU_U32_BYTE1(timeout);
   resp.bwPollTimeout[2] = TU_U32_BYTE2(timeout);
-  resp.bState = _dfu_ctx.state;
-  resp.iString = 0;
+  resp.bState           = (uint8_t) state;
+  resp.iString          = 0;
 
-  tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_req_payload_t));
+  return tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_response_t));
 }
 
+
+#if 0
+
+static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const * request);
+static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request);
+static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * request);
+
 static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const * request)
 {
   // TODO: add "zero" copy mode so the buffer we read into can be provided by the user
   // if they wish, there still will be the internal control buffer copy to this buffer
   // but this mode would provide zero copy from the class driver to the application
 
-  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, );
+  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFSIZE, );
   // setup for data phase
   tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, request->wLength);
 }
@@ -368,21 +476,9 @@ static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const *
 static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request)
 {
   (void) rhport;
-  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFFER_SIZE, );
-  tud_dfu_download_cb(_dfu_ctx.alt_num,_dfu_ctx.block, (uint8_t *)_dfu_ctx.transfer_buf, _dfu_ctx.length);
-  _dfu_ctx.blk_transfer_in_proc = false;
-}
-
-void tud_dfu_download_complete(void)
-{
-  if (_dfu_ctx.state == DFU_DNBUSY)
-  {
-    _dfu_ctx.state = DFU_DNLOAD_SYNC;
-  } else if (_dfu_ctx.state == DFU_MANIFEST)
-  {
-    _dfu_ctx.state = ((_dfu_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
-                           ? DFU_MANIFEST_WAIT_RESET : DFU_MANIFEST_SYNC;
-  }
+  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFSIZE, );
+  tud_dfu_download_cb(_dfu_ctx.alt,_dfu_ctx.block, (uint8_t *)_dfu_ctx.transfer_buf, _dfu_ctx.length);
+  _dfu_ctx.flashing_in_progress = false;
 }
 
 static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * request)
@@ -398,11 +494,11 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_DNLOAD:
         {
-          if( ((_dfu_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+          if( ((_dfu_ctx.attrs & DFU_ATTR_CAN_DOWNLOAD) != 0)
               && (request->wLength > 0) )
           {
             _dfu_ctx.state = DFU_DNLOAD_SYNC;
-            _dfu_ctx.blk_transfer_in_proc = true;
+            _dfu_ctx.flashing_in_progress = true;
             dfu_req_dnload_setup(rhport, request);
           } else {
             _dfu_ctx.state = DFU_ERROR;
@@ -411,7 +507,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         break;
 
         case DFU_REQUEST_GETSTATUS:
-          dfu_req_getstatus_reply(rhport, request);
+          reply_getstatus(rhport, request);
         break;
 
         default:
@@ -428,14 +524,14 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_GETSTATUS:
         {
-          if ( _dfu_ctx.blk_transfer_in_proc )
+          if ( _dfu_ctx.flashing_in_progress )
           {
             _dfu_ctx.state = DFU_DNBUSY;
-            dfu_req_getstatus_reply(rhport, request);
+            reply_getstatus(rhport, request);
             dfu_req_dnload_reply(rhport, request);
           } else {
             _dfu_ctx.state = DFU_DNLOAD_IDLE;
-            dfu_req_getstatus_reply(rhport, request);
+            reply_getstatus(rhport, request);
           }
         }
         break;
@@ -466,14 +562,14 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
         {
           case DFU_REQUEST_DNLOAD:
           {
-            if( ((_dfu_ctx.attrs & DFU_FUNC_ATTR_CAN_DOWNLOAD_BITMASK) != 0)
+            if( ((_dfu_ctx.attrs & DFU_ATTR_CAN_DOWNLOAD) != 0)
                 && (request->wLength > 0) )
             {
               _dfu_ctx.state = DFU_DNLOAD_SYNC;
-              _dfu_ctx.blk_transfer_in_proc = true;
+              _dfu_ctx.flashing_in_progress = true;
               dfu_req_dnload_setup(rhport, request);
             } else {
-              if ( tud_dfu_device_data_done_check_cb(_dfu_ctx.alt_num) )
+              if ( tud_dfu_download_complete_cb(_dfu_ctx.alt) )
               {
                 _dfu_ctx.state = DFU_MANIFEST_SYNC;
                 tud_control_status(rhport, request);
@@ -486,7 +582,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
           break;
 
           case DFU_REQUEST_GETSTATUS:
-            dfu_req_getstatus_reply(rhport, request);
+            reply_getstatus(rhport, request);
           break;
 
           default:
@@ -503,17 +599,17 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       {
         case DFU_REQUEST_GETSTATUS:
         {
-          if ((_dfu_ctx.attrs & DFU_FUNC_ATTR_MANIFESTATION_TOLERANT_BITMASK) == 0)
+          if ((_dfu_ctx.attrs & DFU_ATTR_MANIFESTATION_TOLERANT) == 0)
           {
             _dfu_ctx.state = DFU_MANIFEST;
-            dfu_req_getstatus_reply(rhport, request);
+            reply_getstatus(rhport, request);
           } else 
           {
-            if ( tud_dfu_firmware_valid_check_cb(_dfu_ctx.alt_num) )
+            if ( tud_dfu_manifest_cb(_dfu_ctx.alt) )
             {
               _dfu_ctx.state = DFU_IDLE;
             }
-            dfu_req_getstatus_reply(rhport, request);
+            reply_getstatus(rhport, request);
           }
         }
         break;
@@ -556,7 +652,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       switch (request->bRequest)
       {
         case DFU_REQUEST_GETSTATUS:
-          dfu_req_getstatus_reply(rhport, request);
+          reply_getstatus(rhport, request);
         break;
 
         default:
@@ -571,7 +667,7 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
       switch (request->bRequest)
       {
         case DFU_REQUEST_GETSTATUS:
-          dfu_req_getstatus_reply(rhport, request);
+          reply_getstatus(rhport, request);
         break;
 
         default:
@@ -590,5 +686,6 @@ static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * req
   return true;
 }
 
+#endif
 
 #endif
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index d5d464f3b..2d398aada 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -37,53 +37,51 @@
 // Class Driver Default Configure & Validation
 //--------------------------------------------------------------------+
 
-#if !defined(CFG_TUD_DFU_TRANSFER_BUFFER_SIZE)
-  #error "CFG_TUD_DFU_TRANSFER_BUFFER_SIZE must be defined, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR"
+#if !defined(CFG_TUD_DFU_TRANSFER_BUFSIZE)
+  #error "CFG_TUD_DFU_TRANSFER_BUFSIZE must be defined, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR"
 #endif
 
+//--------------------------------------------------------------------+
+// Application API
+//--------------------------------------------------------------------+
+
+// Must be called when the application is done with flashing started by
+// tud_dfu_download_cb() and tud_dfu_manifest_cb().
+// status is DFU_STATUS_OK if successful, any other error status will cause state to enter dfuError
+void tud_dfu_finish_flashing(uint8_t status);
+
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
 //--------------------------------------------------------------------+
-// Invoked during DFU_MANIFEST_SYNC get status request to check if firmware is valid
-// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
-bool tud_dfu_firmware_valid_check_cb(uint8_t alt);
 
-// Invoked when a DFU_GETSTATUS request is received
-// Return the bwPollTimeout value for host's response, useful for slow Flash in order to make host wait longer
-// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
-TU_ATTR_WEAK uint32_t tud_dfu_get_status_cb(uint8_t alt, uint8_t state);
+// Note: alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
 
-// Invoked when a DFU_DNLOAD request is received
-// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
-// This callback takes the wBlockNum chunk of length length and provides it
-// to the application at the data pointer.  This data is only valid for this
-// call, so the app must use it not or copy it.
-void tud_dfu_download_cb(uint8_t alt, uint16_t wBlockNum, uint8_t* data, uint16_t length);
+// Invoked right before tud_dfu_download_cb() (state=DFU_DNBUSY) or tud_dfu_manifest_cb() (state=DFU_MANIFEST)
+// Application return timeout in milliseconds (bwPollTimeout) for the next download/manifest operation.
+// During this period, USB host won't try to communicate with us.
+uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state);
 
-// Must be called when the application is done using the last block of data
-// provided by tud_dfu_download_cb
-void tud_dfu_download_complete(void);
+// Invoked when received DFU_DNLOAD (wLength>0) following by DFU_GETSTATUS (state=DFU_DNBUSY) requests
+// This callback could be returned before flashing op is complete (async).
+// Once finished flashing, application must call tud_dfu_finish_flashing()
+void tud_dfu_download_cb (uint8_t alt, uint16_t block_num, uint8_t const *data, uint16_t length);
 
-// Invoked during the last DFU_DNLOAD request, signifying that the host believes
-// it is done transmitting data.
-// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
-// Return true if the application agrees there is no more data
-// Return false if the device disagrees, which will stall the pipe, and the Host
-//              should initiate a recovery procedure
-bool tud_dfu_device_data_done_check_cb(uint8_t alt);
+// Invoked when download process is complete, received DFU_DNLOAD (wLength=0) following by DFU_GETSTATUS (state=Manifest)
+// Application can do checksum, or actual flashing if buffered entire image previously.
+// Once finished flashing, application must call tud_dfu_finish_flashing()
+void tud_dfu_manifest_cb(uint8_t alt);
 
-// Invoked when the Host has terminated a download or upload transfer
-TU_ATTR_WEAK void tud_dfu_abort_cb(uint8_t alt);
-
-// Invoked when a DFU_UPLOAD request is received
-// alt is used as the partition number, in order to support multiple partitions like FLASH, EEPROM, etc.
-// This callback must populate data with up to length bytes
-// Return the number of bytes to write
+// Invoked when received DFU_UPLOAD request
+// Application must populate data with up to length bytes and
+// Return the number of written bytes
 TU_ATTR_WEAK uint16_t tud_dfu_upload_cb(uint8_t alt, uint16_t block_num, uint8_t* data, uint16_t length);
 
 // Invoked when a DFU_DETACH request is received
 TU_ATTR_WEAK void tud_dfu_detach_cb(void);
 
+// Invoked when the Host has terminated a download or upload transfer
+TU_ATTR_WEAK void tud_dfu_abort_cb(uint8_t alt);
+
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
diff --git a/src/class/dfu/dfu_rt_device.c b/src/class/dfu/dfu_rt_device.c
index 07e6f30f3..afee2aa1f 100644
--- a/src/class/dfu/dfu_rt_device.c
+++ b/src/class/dfu/dfu_rt_device.c
@@ -108,10 +108,10 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
     case DFU_REQUEST_GETSTATUS:
     {
       TU_LOG2("  DFU RT Request: GETSTATUS\r\n");
-      dfu_status_req_payload_t resp;
+      dfu_status_response_t resp;
       // Status = OK, Poll timeout is ignored during RT, State = APP_IDLE, IString = 0
-      memset(&resp, 0x00, sizeof(dfu_status_req_payload_t));
-      tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_req_payload_t));
+      memset(&resp, 0x00, sizeof(dfu_status_response_t));
+      tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_response_t));
     }
     break;
 
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index fc1035e2c..eab67ebd5 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -449,7 +449,7 @@ typedef struct TU_ATTR_PACKED
 /*------------------------------------------------------------------*/
 /* Types
  *------------------------------------------------------------------*/
-typedef struct TU_ATTR_PACKED TU_ATTR_ALIGNED(4) {
+typedef struct TU_ATTR_PACKED {
   union {
     struct TU_ATTR_PACKED {
       uint8_t recipient :  5; ///< Recipient type tusb_request_recipient_t.
diff --git a/src/device/usbd.c b/src/device/usbd.c
index af4fd58c4..cf9af783d 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -190,7 +190,7 @@ static usbd_class_driver_t const _usbd_driver[] =
 
   #if CFG_TUD_DFU_MODE
   {
-    DRIVER_NAME("DFU-MODE")
+    DRIVER_NAME("DFU")
     .init             = dfu_moded_init,
     .reset            = dfu_moded_reset,
     .open             = dfu_moded_open,
diff --git a/src/tusb_option.h b/src/tusb_option.h
index bf7591dcf..4351d9486 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -253,10 +253,6 @@
   #define CFG_TUD_DFU_MODE        0
 #endif
 
-#ifndef CFG_TUD_DFU_TRANSFER_BUFFER_SIZE
-  #define CFG_TUD_DFU_TRANSFER_BUFFER_SIZE  64
-#endif
-
 #ifndef CFG_TUD_NET
   #define CFG_TUD_NET             0
 #endif

From 3960beece0ea3dccf7ca615bd7841daa6b703d56 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Jul 2021 20:52:58 +0700
Subject: [PATCH 0207/2085] rename CFG_TUD_DFU_MODE to simply CFG_TUD_DFU

---
 examples/device/dfu/src/main.c        | 2 +-
 examples/device/dfu/src/tusb_config.h | 4 +---
 src/class/dfu/dfu_device.c            | 2 +-
 src/device/usbd.c                     | 2 +-
 src/tusb.h                            | 2 +-
 src/tusb_option.h                     | 4 ++--
 6 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 1621a330b..7133d1624 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -148,7 +148,7 @@ uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state)
 void tud_dfu_download_cb(uint8_t alt, uint16_t wBlockNum, uint8_t const* data, uint16_t length)
 {
   (void) data;
-  printf("\r\nReceived Alt %u BlockNum %u of length %u\r\n", alt, wBlockNum, length);
+  //printf("\r\nReceived Alt %u BlockNum %u of length %u\r\n", alt, wBlockNum, length);
 
   for(uint16_t i=0; i<length; i++)
   {
diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 5be58e854..2e3b89f49 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -77,9 +77,7 @@
 #endif
 
 //------------- CLASS -------------//
-
-#define CFG_TUD_DFU_RUNTIME 0
-#define CFG_TUD_DFU_MODE    1
+#define CFG_TUD_DFU    1
 
 // DFU buffer size, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
 #define CFG_TUD_DFU_TRANSFER_BUFSIZE    512
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 3aa90f5c5..222795bec 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_DFU_MODE)
+#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_DFU)
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/device/usbd.c b/src/device/usbd.c
index cf9af783d..42d24fbf3 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -188,7 +188,7 @@ static usbd_class_driver_t const _usbd_driver[] =
   },
   #endif
 
-  #if CFG_TUD_DFU_MODE
+  #if CFG_TUD_DFU
   {
     DRIVER_NAME("DFU")
     .init             = dfu_moded_init,
diff --git a/src/tusb.h b/src/tusb.h
index 2b1d7483a..b52f8839a 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -96,7 +96,7 @@
     #include "class/dfu/dfu_rt_device.h"
   #endif
 
-  #if CFG_TUD_DFU_MODE
+  #if CFG_TUD_DFU
     #include "class/dfu/dfu_device.h"
   #endif
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 4351d9486..97da0bd92 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -249,8 +249,8 @@
   #define CFG_TUD_DFU_RUNTIME     0
 #endif
 
-#ifndef CFG_TUD_DFU_MODE
-  #define CFG_TUD_DFU_MODE        0
+#ifndef CFG_TUD_DFU
+  #define CFG_TUD_DFU             0
 #endif
 
 #ifndef CFG_TUD_NET

From 406832158d326031fa4ab4744a4703293a358fba Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Jul 2021 21:08:10 +0700
Subject: [PATCH 0208/2085] skip lto for samd11 build

---
 hw/bsp/samd11/family.mk | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index 70120ec94..032d11b98 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -3,7 +3,6 @@ DEPS_SUBMODULES += hw/mcu/microchip
 include $(TOP)/$(BOARD_PATH)/board.mk
 
 CFLAGS += \
-	-flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m0plus \

From 6acaa94b3262ab3204ce23b60d20eabae5e0189c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Jul 2021 21:09:05 +0700
Subject: [PATCH 0209/2085] fix warnings

---
 examples/device/dfu/src/main.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 7133d1624..5c8464526 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -145,14 +145,15 @@ uint32_t tud_dfu_get_timeout_cb(uint8_t alt, uint8_t state)
 // Invoked when received DFU_DNLOAD (wLength>0) following by DFU_GETSTATUS (state=DFU_DNBUSY) requests
 // This callback could be returned before flashing op is complete (async).
 // Once finished flashing, application must call tud_dfu_finish_flashing()
-void tud_dfu_download_cb(uint8_t alt, uint16_t wBlockNum, uint8_t const* data, uint16_t length)
+void tud_dfu_download_cb(uint8_t alt, uint16_t block_num, uint8_t const* data, uint16_t length)
 {
-  (void) data;
+  (void) alt;
+  (void) block_num;
+
   //printf("\r\nReceived Alt %u BlockNum %u of length %u\r\n", alt, wBlockNum, length);
 
   for(uint16_t i=0; i<length; i++)
   {
-    // printf("  [%u][%u]: %x\r\n", wBlockNum, i, (uint8_t)data[i]);
     printf("%c", data[i]);
   }
 

From 84bd863cf580515a7ff10baad7b1f23a25dc7bb0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Jul 2021 21:13:44 +0700
Subject: [PATCH 0210/2085] revert debug midi changes

---
 examples/device/midi_test/src/main.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 66b858323..7bdca222a 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -138,9 +138,6 @@ void midi_task(void)
   if (board_millis() - start_ms < 1000) return; // not enough time
   start_ms += 1000;
 
-#if 1
-
-#else
   // Previous positions in the note sequence.
   int previous = note_pos - 1;
 
@@ -161,7 +158,6 @@ void midi_task(void)
 
   // If we are at the end of the sequence, start over.
   if (note_pos >= sizeof(note_sequence)) note_pos = 0;
-#endif
 }
 
 //--------------------------------------------------------------------+

From 4e817ae6d47e3e0636358179ba0d3570fa47c2b0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Jul 2021 21:11:43 +0700
Subject: [PATCH 0211/2085] revert unrelated midi exmample

---
 examples/device/midi_test/src/main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 7bdca222a..193748477 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -135,8 +135,8 @@ void midi_task(void)
   while ( tud_midi_available() ) tud_midi_packet_read(packet);
 
   // send note periodically
-  if (board_millis() - start_ms < 1000) return; // not enough time
-  start_ms += 1000;
+  if (board_millis() - start_ms < 286) return; // not enough time
+  start_ms += 286;
 
   // Previous positions in the note sequence.
   int previous = note_pos - 1;

From 392e16af4d9056507ee765d9bafece55ef755143 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Fri, 16 Jul 2021 23:03:17 +0100
Subject: [PATCH 0212/2085] readme: add openinput to the 'Uses' section

Signed-off-by: Rafael Silva <perigoso@riseup.net>
---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index bea6d0d49..5e11e0f4b 100644
--- a/README.md
+++ b/README.md
@@ -106,6 +106,7 @@ TinyUSB is currently used by these other projects:
 - [Espressif IDF](https://github.com/espressif/esp-idf)
 - [MicroPython](https://github.com/micropython/micropython)
 - [mynewt](https://mynewt.apache.org)
+- [openinput](https://github.com/openinput-fw/openinput)
 - [Raspberry Pi Pico SDK](https://github.com/raspberrypi/pico-sdk)
 - [TinyUF2 Bootloader](https://github.com/adafruit/tinyuf2)
 - [TinyUSB Arduino Library](https://github.com/adafruit/Adafruit_TinyUSB_Arduino)

From 475742984f4d0f2b95c9c78dfff71814117feb90 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 17 Jul 2021 12:08:42 +0200
Subject: [PATCH 0213/2085] Change OPT_MCU_SAMX7X value.

---
 src/tusb_option.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 69c5fb0bd..9b0ea4358 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -61,7 +61,8 @@
 #define OPT_MCU_SAME5X            203 ///< MicroChip SAM E5x
 #define OPT_MCU_SAMD11            204 ///< MicroChip SAMD11
 #define OPT_MCU_SAML22            205 ///< MicroChip SAML22
-#define OPT_MCU_SAMX7X            206 ///< MicroChip SAME70, S70, V70, V71 family
+#define OPT_MCU_SAML21            206 ///< MicroChip SAML21
+#define OPT_MCU_SAMX7X            207 ///< MicroChip SAME70, S70, V70, V71 family
 
 
 // STM32

From 7e3e41952fe4c83a182dfe39e5bab89e65120485 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 17 Jul 2021 13:48:21 +0200
Subject: [PATCH 0214/2085] Fix ISO support.

---
 .../device/uac2_headset/src/usb_descriptors.c  | 16 ++++++++++++----
 src/portable/microchip/samx7x/dcd_samx7x.c     | 18 +++++++++++++-----
 2 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 6a01f8938..4a26b0b1e 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -79,12 +79,20 @@ uint8_t const * tud_descriptor_device_cb(void)
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
 // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
 // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
-#define EPNUM_AUDIO   0x03
+#define EPNUM_AUDIO_IN    0x03
+#define EPNUM_AUDIO_OUT   0x03
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
 // ISO endpoints for NRF5x are fixed to 0x08 (0x88)
-#define EPNUM_AUDIO   0x08
+#define EPNUM_AUDIO_IN    0x08
+#define EPNUM_AUDIO_OUT   0x08
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
+// SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+//    e.g EP1 OUT & EP1 IN cannot exist together
+#define EPNUM_AUDIO_IN    0x01
+#define EPNUM_AUDIO_OUT   0x02
 #else
-#define EPNUM_AUDIO   0x01
+#define EPNUM_AUDIO_IN    0x01
+#define EPNUM_AUDIO_OUT   0x01
 #endif
 
 uint8_t const desc_configuration[] =
@@ -93,7 +101,7 @@ uint8_t const desc_configuration[] =
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
-    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO, EPNUM_AUDIO | 0x80)
+    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO_OUT, EPNUM_AUDIO_IN | 0x80)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 0299d12b9..2a534b95b 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -83,11 +83,8 @@ typedef struct {
 static tusb_speed_t get_speed(void);
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
 
-// DMA descriptors shouldn't be placed in ITCM
-#if defined(USB_DMA_DESC_SECTION)
-TU_ATTR_SECTION(TU_XSTRING(USB_DMA_DESC_SECTION))
-#endif
-dma_desc_t dma_desc[6];
+// DMA descriptors shouldn't be placed in ITCM !
+CFG_TUSB_MEM_SECTION dma_desc_t dma_desc[6];
 
 xfer_ctl_t xfer_status[EP_MAX+1];
 
@@ -531,6 +528,17 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   }
 }
 
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = tu_edpt_number(ep_addr);
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
+
+  // Disable endpoint interrupt
+  USBHS->USBHS_DEVIDR = 1 << (USBHS_DEVIDR_PEP_0_Pos + epnum);
+  // Disable EP
+  USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPEN0_Pos + epnum));
+}
+
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
 {
   uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);

From bae0d3b7bbe5145017ebd08f777fe0b8063f44b7 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 17 Jul 2021 14:42:23 +0200
Subject: [PATCH 0215/2085] Fix build error.

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 2a534b95b..aa9faa5be 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -531,7 +531,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
+  (void) ep_addr;
 
   // Disable endpoint interrupt
   USBHS->USBHS_DEVIDR = 1 << (USBHS_DEVIDR_PEP_0_Pos + epnum);

From f52e1889c7f4bca23311a97b5869eab70c766094 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 17 Jul 2021 20:41:19 +0200
Subject: [PATCH 0216/2085] Fix merge error.

---
 examples/device/cdc_msc/src/msc_disk.c         |  2 +-
 .../device/hid_composite/src/tusb_config.h     |  2 +-
 src/class/cdc/cdc_device.c                     | 14 --------------
 src/class/cdc/cdc_device.h                     | 18 ------------------
 4 files changed, 2 insertions(+), 34 deletions(-)

diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index 3caf3fd42..503baace9 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -23,7 +23,7 @@
  *
  */
 
-//#include "bsp/board.h"
+#include "bsp/board.h"
 #include "tusb.h"
 
 #if CFG_TUD_MSC
diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index 31dea4ee9..868424e6d 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -69,7 +69,7 @@
 #endif
 
 // CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-#define CFG_TUSB_DEBUG           0
+// #define CFG_TUSB_DEBUG           0
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 68080c61d..e622bd616 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -481,18 +481,4 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   return true;
 }
 
-// Get the Receive FIFO (for DMA transfer)
-tu_fifo_t* tud_cdc_n_get_rx_ff (uint8_t itf)
-{
-  TU_ASSERT(itf < CFG_TUD_CDC);
-  return &_cdcd_itf[itf].rx_ff;
-}
-
-// Get the transmit FIFO (for DMA transfer)
-tu_fifo_t* tud_cdc_n_get_tx_ff (uint8_t itf)
-{
-  TU_ASSERT(itf < CFG_TUD_CDC);
-  return &_cdcd_itf[itf].tx_ff;
-}
-
 #endif
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index f8a2216c1..7ff757add 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -104,12 +104,6 @@ uint32_t tud_cdc_n_write_available (uint8_t itf);
 // Clear the transmit FIFO
 bool tud_cdc_n_write_clear (uint8_t itf);
 
-// Get the Receive FIFO (for DMA transfer)
-tu_fifo_t* tud_cdc_n_get_rx_ff (uint8_t itf);
-
-// Get the transmit FIFO (for DMA transfer)
-tu_fifo_t* tud_cdc_n_get_tx_ff (uint8_t itf);
-
 //--------------------------------------------------------------------+
 // Application API (Single Port)
 //--------------------------------------------------------------------+
@@ -247,18 +241,6 @@ static inline bool tud_cdc_write_clear(void)
   return tud_cdc_n_write_clear(0);
 }
 
-// Get the Receive FIFO
-static inline tu_fifo_t* tud_cdc_get_rx_ff (void)
-{
-  return tud_cdc_n_get_rx_ff(0);
-}
-
-// Get the transmit FIFO
-static inline tu_fifo_t* tud_cdc_get_tx_ff (void)
-{
-  return tud_cdc_n_get_tx_ff(0);
-}
-
 /** @} */
 /** @} */
 

From d0dd3c77ff7cffddbcc177d0ed48acd7a70f74a8 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sun, 18 Jul 2021 22:03:45 +0200
Subject: [PATCH 0217/2085] Use USBHS_Handler

---
 hw/bsp/same70_xplained/same70_xplained.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/same70_xplained/same70_xplained.c b/hw/bsp/same70_xplained/same70_xplained.c
index e34b5d35d..f897798e7 100644
--- a/hw/bsp/same70_xplained/same70_xplained.c
+++ b/hw/bsp/same70_xplained/same70_xplained.c
@@ -109,7 +109,7 @@ void board_init(void)
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 //--------------------------------------------------------------------+
-void UDP_Handler(void)
+void USBHS_Handler(void)
 {
   #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
     tud_int_handler(0);

From 8cae17bfc87f49c814827b0a31a4b6b6e8314f69 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Mon, 19 Jul 2021 01:07:33 +0200
Subject: [PATCH 0218/2085] Fixing NAKed OUT xfer

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 53 +++++++++++++++-------
 1 file changed, 36 insertions(+), 17 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index aa9faa5be..3134a0597 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -60,7 +60,8 @@
 #define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
 
 // Errata: The DMA feature is not available for Pipe/Endpoint 7
-#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)
+// #define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)
+#define EP_DMA_SUPPORT(epnum) 0
 
 // DMA Channel Transfer Descriptor
 typedef struct {
@@ -294,8 +295,6 @@ static void dcd_ep_handler(uint8_t ep_ix)
       }
       // Acknowledge the interrupt
       USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
-      // Clear the FIFO control flag to receive more data.
-      USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
       if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
       {
         // RX COMPLETE
@@ -314,10 +313,10 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX not complete
         dcd_transmit_packet(xfer, ep_ix);
-      } else {
+      } else 
+      {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_TXINEC;
       }
     }
   }
@@ -338,7 +337,8 @@ static void dcd_dma_handler(uint8_t ep_ix)
   if(USBHS->USBHS_DEVEPTCFG[ep_ix] & USBHS_DEVEPTCFG_EPDIR)
   {
     dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
-  } else {
+  } else 
+  {
     dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
   }
 }
@@ -483,14 +483,17 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     {
       // Endpoint configuration is successful
       USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
+      USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RXOUTES;
       // Enable Endpoint 0 Interrupts
       USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
       return true;
-    } else {
+    } else 
+    {
       // Endpoint configuration is not successful
       return false;
     }
-  } else {
+  } else 
+  {
     // Enable the endpoint
     USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
     // Set up the maxpacket size, fifo start address fifosize
@@ -520,8 +523,17 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK))
     {
       USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
+      if (dir)
+      {
+        USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_TXINIC;
+		USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_TXINES;
+      } else
+      {
+        USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
+      }
       return true;
-    } else {
+    } else 
+    {
       // Endpoint configuration is not successful
       return false;
     }
@@ -553,7 +565,8 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
     {
       memcpy(ptr, xfer->buffer + xfer->queued_len, len);
     }
-    else {
+    else 
+    {
       tu_fifo_read_n(xfer->fifo, ptr, len);
     }
     __DSB();
@@ -564,11 +577,12 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
   {
     // Control endpoint: clear the interrupt flag to send the data
     USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
-  } else {
+    USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_TXINES;
+  } else 
+  {
     // Other endpoint types: clear the FIFO control flag to send the data
     USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
   }
-  USBHS->USBHS_DEVEPTIER[ep_ix] = USBHS_DEVEPTIER_TXINES;
 }
 
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
@@ -615,11 +629,14 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     // and the DMA transfer must be not started.
     // It is the end of transfer
     return false;
-  } else {
+  } else 
+  {
     if (dir == TUSB_DIR_OUT)
     {
-      USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
-    } else {
+      // Clear the FIFO control flag to receive more data.
+      USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_FIFOCONC;
+    } else 
+    {
       dcd_transmit_packet(xfer,epnum);
     }
   }
@@ -696,11 +713,13 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
     // and the DMA transfer must be not started.
     // It is the end of transfer
     return false;
-  } else {
+  } else
+  {
     if (dir == TUSB_DIR_OUT)
     {
       USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
-    } else {
+    } else 
+    {
       dcd_transmit_packet(xfer,epnum);
     }
   }

From 05f59fb8edc301690042821d447c31631be8d911 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 19 Jul 2021 12:08:01 +0700
Subject: [PATCH 0219/2085] clean up warning

---
 hw/bsp/same70_xplained/board.mk            | 5 -----
 hw/bsp/same70_xplained/same70_xplained.c   | 4 +---
 src/portable/microchip/samx7x/dcd_samx7x.c | 2 +-
 3 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index 94b0bed98..c9bc0cea3 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -43,11 +43,6 @@ INC += \
 	$(TOP)/$(ASF_DIR)/hri \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
-# For TinyUSB port source
-#SRC_C += src/portable/template/dcd_template.c
-VENDOR = .
-CHIP_FAMILY = template
-
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM7
 
diff --git a/hw/bsp/same70_xplained/same70_xplained.c b/hw/bsp/same70_xplained/same70_xplained.c
index f897798e7..ac682a89a 100644
--- a/hw/bsp/same70_xplained/same70_xplained.c
+++ b/hw/bsp/same70_xplained/same70_xplained.c
@@ -111,9 +111,7 @@ void board_init(void)
 //--------------------------------------------------------------------+
 void USBHS_Handler(void)
 {
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
-  #endif
+  tud_int_handler(0);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 3134a0597..31628583a 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -542,8 +542,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
+  (void) rhport;
   uint8_t const epnum  = tu_edpt_number(ep_addr);
-  (void) ep_addr;
 
   // Disable endpoint interrupt
   USBHS->USBHS_DEVIDR = 1 << (USBHS_DEVIDR_PEP_0_Pos + epnum);

From cee980c598ce3ff83f2980280d53c906b7bf1b19 Mon Sep 17 00:00:00 2001
From: Ben Evans <benny.j.evans92@gmail.com>
Date: Mon, 19 Jul 2021 17:45:12 +1000
Subject: [PATCH 0220/2085] Fix for dcd_synopsys driver integer overflow in HS
 mode (issue #968).

---
 src/portable/st/synopsys/dcd_synopsys.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 8a196e061..c15694eba 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -656,7 +656,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   }
 
   uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint8_t const short_packet_size = total_bytes % xfer->max_size;
+  uint16_t const short_packet_size = total_bytes % xfer->max_size;
 
   // Zero-size packet is special case.
   if(short_packet_size > 0 || (total_bytes == 0)) {
@@ -687,7 +687,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   xfer->total_len   = total_bytes;
 
   uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint8_t const short_packet_size = total_bytes % xfer->max_size;
+  uint16_t const short_packet_size = total_bytes % xfer->max_size;
 
   // Zero-size packet is special case.
   if(short_packet_size > 0 || (total_bytes == 0)) num_packets++;

From 75f61328ea8aaffa0e666c56def4efdafcb63a12 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Mon, 19 Jul 2021 22:03:47 +0200
Subject: [PATCH 0221/2085] Remove clock init.

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 3134a0597..c91702c9f 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -102,14 +102,14 @@ static const tusb_desc_endpoint_t ep0_desc =
 // Initialize controller to device mode
 void dcd_init (uint8_t rhport)
 {
-  // Enable USBPLL
-  PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
-  // Wait until USB UTMI stabilize
-  while (!(PMC->PMC_SR & PMC_SR_LOCKU));
-  // Enable USB FS clk
-  PMC->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2;
-  PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
-  PMC->PMC_SCER = PMC_SCER_USBCLK;
+//  // Enable USBPLL
+//  PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
+//  // Wait until USB UTMI stabilize
+//  while (!(PMC->PMC_SR & PMC_SR_LOCKU));
+//  // Enable USB FS clk
+//  PMC->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2;
+//  PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
+//  PMC->PMC_SCER = PMC_SCER_USBCLK;
   dcd_connect(rhport);
 }
 

From fa9a327a7134a53a0a2b1d7c449083110f9a7d37 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 20 Jul 2021 13:24:39 +0200
Subject: [PATCH 0222/2085] Workaround of EP0 issue, clean up.

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 35 ++++++++++------------
 1 file changed, 16 insertions(+), 19 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index bb69619d7..b49724901 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -60,8 +60,7 @@
 #define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
 
 // Errata: The DMA feature is not available for Pipe/Endpoint 7
-// #define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)
-#define EP_DMA_SUPPORT(epnum) 0
+#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)
 
 // DMA Channel Transfer Descriptor
 typedef struct {
@@ -102,14 +101,6 @@ static const tusb_desc_endpoint_t ep0_desc =
 // Initialize controller to device mode
 void dcd_init (uint8_t rhport)
 {
-//  // Enable USBPLL
-//  PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0x3fU);
-//  // Wait until USB UTMI stabilize
-//  while (!(PMC->PMC_SR & PMC_SR_LOCKU));
-//  // Enable USB FS clk
-//  PMC->PMC_MCKR &= ~PMC_MCKR_UPLLDIV2;
-//  PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(10 - 1);
-//  PMC->PMC_SCER = PMC_SCER_USBCLK;
   dcd_connect(rhport);
 }
 
@@ -228,9 +219,14 @@ static void dcd_ep_handler(uint8_t ep_ix)
       }
       // Acknowledge the interrupt
       USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_CTRL_RXSTPIC;
+      // Workaround :
+      // Clear spurious OUT irq
+      USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
+      int_status &=~USBHS_DEVEPTISR_RXOUTI;
     }
     if (int_status & USBHS_DEVEPTISR_RXOUTI)
     {
+      uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
       xfer_ctl_t *xfer = &xfer_status[0];
       if (count && xfer->total_len)
       {
@@ -239,11 +235,11 @@ static void dcd_ep_handler(uint8_t ep_ix)
         {
           count = remain;
         }
-        uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
         if (xfer->buffer)
         {
           memcpy(xfer->buffer + xfer->queued_len, ptr, count);
-        } else {
+        } else 
+        {
           tu_fifo_write_n(xfer->fifo, ptr, count);
         }
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
@@ -253,7 +249,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
       {
         // RX COMPLETE
-        dcd_event_xfer_complete(0, 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
+        dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt
         USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
         // Though the host could still send, we don't know.
@@ -268,12 +264,14 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX not complete
         dcd_transmit_packet(xfer, 0);
-      } else {
+      } else 
+      {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
       }
     }
-  } else {
+  } else 
+  {
     if (int_status & USBHS_DEVEPTISR_RXOUTI)
     {
       xfer_ctl_t *xfer = &xfer_status[ep_ix];
@@ -293,6 +291,8 @@ static void dcd_ep_handler(uint8_t ep_ix)
         }
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
+      // Clear the FIFO control flag to receive more data.
+      USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
       // Acknowledge the interrupt
       USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
       if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
@@ -483,7 +483,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     {
       // Endpoint configuration is successful
       USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
-      USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RXOUTES;
       // Enable Endpoint 0 Interrupts
       USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
       return true;
@@ -529,7 +528,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 		USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_TXINES;
       } else
       {
-        USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
       }
       return true;
     } else 
@@ -633,8 +631,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   {
     if (dir == TUSB_DIR_OUT)
     {
-      // Clear the FIFO control flag to receive more data.
-      USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_FIFOCONC;
+      USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
     } else 
     {
       dcd_transmit_packet(xfer,epnum);

From eec927ea959d6d972c62d60fa634df227e196b36 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 21 Jul 2021 00:14:28 +0200
Subject: [PATCH 0223/2085] Fix EP0 issue (again)

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 34 +++++++++++++---------
 1 file changed, 20 insertions(+), 14 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index b49724901..de1fd2566 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -86,7 +86,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
 // DMA descriptors shouldn't be placed in ITCM !
 CFG_TUSB_MEM_SECTION dma_desc_t dma_desc[6];
 
-xfer_ctl_t xfer_status[EP_MAX+1];
+xfer_ctl_t xfer_status[EP_MAX];
 
 static const tusb_desc_endpoint_t ep0_desc =
 {
@@ -205,29 +205,32 @@ static void dcd_ep_handler(uint8_t ep_ix)
 {
   uint32_t int_status = USBHS->USBHS_DEVEPTISR[ep_ix];
   int_status &= USBHS->USBHS_DEVEPTIMR[ep_ix];
+
   uint16_t count = (USBHS->USBHS_DEVEPTISR[ep_ix] &
                     USBHS_DEVEPTISR_BYCT_Msk) >> USBHS_DEVEPTISR_BYCT_Pos;
+  xfer_ctl_t *xfer = &xfer_status[ep_ix];
+
   if (ep_ix == 0U)
   {
+    static uint8_t ctrl_dir;
+
     if (int_status & USBHS_DEVEPTISR_CTRL_RXSTPI)
     {
+      ctrl_dir = (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk) >> USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos;
       // Setup packet should always be 8 bytes. If not, ignore it, and try again.
       if (count == 8)
       {
         uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
         dcd_event_setup_received(0, ptr, true);
       }
-      // Acknowledge the interrupt
+      // Ack and disable SETUP interrupt
       USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_CTRL_RXSTPIC;
-      // Workaround :
-      // Clear spurious OUT irq
-      USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
-      int_status &=~USBHS_DEVEPTISR_RXOUTI;
+      USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_CTRL_RXSTPEC;
     }
     if (int_status & USBHS_DEVEPTISR_RXOUTI)
     {
       uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
-      xfer_ctl_t *xfer = &xfer_status[0];
+      
       if (count && xfer->total_len)
       {
         uint16_t remain = xfer->total_len - xfer->queued_len;
@@ -252,14 +255,17 @@ static void dcd_ep_handler(uint8_t ep_ix)
         dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt
         USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
-        // Though the host could still send, we don't know.
+        // Re-enable SETUP interrupt
+        if (ctrl_dir == 1)
+        {
+          USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
+        }
       }
     }
     if (int_status & USBHS_DEVEPTISR_TXINI)
     {
       // Disable the interrupt
       USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
-      xfer_ctl_t * xfer = &xfer_status[EP_MAX];
       if ((xfer->total_len != xfer->queued_len))
       {
         // TX not complete
@@ -268,13 +274,17 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
+        // Re-enable SETUP interrupt
+        if (ctrl_dir == 0)
+        {
+          USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
+        }
       }
     }
   } else 
   {
     if (int_status & USBHS_DEVEPTISR_RXOUTI)
     {
-      xfer_ctl_t *xfer = &xfer_status[ep_ix];
       if (count && xfer->total_len)
       {
         uint16_t remain = xfer->total_len - xfer->queued_len;
@@ -308,7 +318,6 @@ static void dcd_ep_handler(uint8_t ep_ix)
     {
       // Acknowledge the interrupt
       USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
-      xfer_ctl_t * xfer = &xfer_status[ep_ix];;
       if ((xfer->total_len != xfer->queued_len))
       {
         // TX not complete
@@ -466,7 +475,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   if (epnum == 0)
   {
-    xfer_status[EP_MAX].max_packet_size = epMaxPktSize;
     // Enable the control endpoint - Endpoint 0
     USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
     // Configure the Endpoint 0 configuration register
@@ -591,8 +599,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   xfer_ctl_t * xfer = &xfer_status[epnum];
-  if(ep_addr == 0x80)
-    xfer = &xfer_status[EP_MAX];
 
   xfer->buffer = buffer;
   xfer->total_len = total_bytes;

From 9c26c0c01e244310dc0e90573f39be7dc7250ead Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 21 Jul 2021 09:42:26 +0200
Subject: [PATCH 0224/2085] Remove redundant TX irq.

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index de1fd2566..35d970b99 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -530,13 +530,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK))
     {
       USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
-      if (dir)
-      {
-        USBHS->USBHS_DEVEPTICR[epnum] = USBHS_DEVEPTICR_TXINIC;
-		USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_TXINES;
-      } else
-      {
-      }
       return true;
     } else 
     {

From 5492d9148cbd09d19137b992f9ee51def9bd076f Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 21 Jul 2021 10:29:47 +0200
Subject: [PATCH 0225/2085] Re-enable SETUP irq on EP0 stall.

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 35d970b99..851978398 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -728,6 +728,11 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_addr);
   USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_CTRL_STALLRQS;
+  // Re-enable SETUP interrupt
+  if (epnum == 0)
+  {
+    USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
+  }
 }
 
 // clear stall, data toggle is also reset to DATA0

From 8c6cd5396c1276aed12fd3a74825debe136d3ded Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 21 Jul 2021 10:50:07 +0200
Subject: [PATCH 0226/2085] Fix non-DMA IN irq.

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 851978398..e35cf80a6 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -326,6 +326,8 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
+        // Disable the interrupt
+        USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_TXINEC;
       }
     }
   }
@@ -576,12 +578,12 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
   {
     // Control endpoint: clear the interrupt flag to send the data
     USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
-    USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_TXINES;
   } else 
   {
     // Other endpoint types: clear the FIFO control flag to send the data
     USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
   }
+  USBHS->USBHS_DEVEPTIER[ep_ix] = USBHS_DEVEPTIER_TXINES;
 }
 
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack

From b192dc0738f0c1d820326127ba0496b54f752414 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 21 Jul 2021 14:18:47 +0200
Subject: [PATCH 0227/2085] Update EPNUM in usb_descriptors.c

---
 .../net_lwip_webserver/src/usb_descriptors.c  |  4 ++--
 .../webusb_serial/src/usb_descriptors.c       | 23 ++++++++++++++-----
 2 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c
index 1a77c39d7..71e6c4582 100644
--- a/examples/device/net_lwip_webserver/src/usb_descriptors.c
+++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c
@@ -107,8 +107,8 @@ uint8_t const * tud_descriptor_device_cb(void)
   #define EPNUM_NET_OUT     0x02
   #define EPNUM_NET_IN      0x82
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG
-  // SAMG doesn't support a same endpoint number with different direction IN and OUT
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
+  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_NET_NOTIF   0x81
   #define EPNUM_NET_OUT     0x02
diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c
index 4aefdb1f7..d1539488f 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.c
+++ b/examples/device/webusb_serial/src/usb_descriptors.c
@@ -86,11 +86,22 @@ enum
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
-  #define EPNUM_CDC     2
-  #define EPNUM_VENDOR  5
+  #define EPNUM_CDC_IN     2
+  #define EPNUM_CDC_OUT    2
+  #define EPNUM_VENDOR_IN  5
+  #define EPNUM_VENDOR_OUT 5
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
+  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_IN     2
+  #define EPNUM_CDC_OUT    3
+  #define EPNUM_VENDOR_IN  4
+  #define EPNUM_VENDOR_OUT 5
 #else
-  #define EPNUM_CDC     2
-  #define EPNUM_VENDOR  3
+  #define EPNUM_CDC_IN     2
+  #define EPNUM_CDC_OUT    2
+  #define EPNUM_VENDOR_IN  3
+  #define EPNUM_VENDOR_OUT 3
 #endif
 
 uint8_t const desc_configuration[] =
@@ -99,10 +110,10 @@ uint8_t const desc_configuration[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
   // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, 0x81, 8, EPNUM_CDC, 0x80 | EPNUM_CDC, TUD_OPT_HIGH_SPEED ? 512 : 64),
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, 0x81, 8, EPNUM_CDC_OUT, 0x80 | EPNUM_CDC_IN, TUD_OPT_HIGH_SPEED ? 512 : 64),
 
   // Interface number, string index, EP Out & IN address, EP size
-  TUD_VENDOR_DESCRIPTOR(ITF_NUM_VENDOR, 5, EPNUM_VENDOR, 0x80 | EPNUM_VENDOR, TUD_OPT_HIGH_SPEED ? 512 : 64)
+  TUD_VENDOR_DESCRIPTOR(ITF_NUM_VENDOR, 5, EPNUM_VENDOR_OUT, 0x80 | EPNUM_VENDOR_IN, TUD_OPT_HIGH_SPEED ? 512 : 64)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR

From a226dbaa4d1df9e5258e7f4dfacdc76906b08084 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Jul 2021 13:21:58 +0700
Subject: [PATCH 0228/2085] add dcd_attr for DCD_ATTR_ENDPOINT_MAX

could be useful with more dcd specific attribute
---
 src/device/dcd.h      |   2 +
 src/device/dcd_attr.h | 146 ++++++++++++++++++++++++++++++++++++++++++
 src/device/usbd.c     |  21 ++++--
 src/device/usbd.h     |   3 -
 src/tusb_option.h     |  34 ++++------
 5 files changed, 176 insertions(+), 30 deletions(-)
 create mode 100644 src/device/dcd_attr.h

diff --git a/src/device/dcd.h b/src/device/dcd.h
index 63e97df96..11f8ca5d3 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -31,6 +31,8 @@
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
 
+#include "dcd_attr.h"
+
 #ifdef __cplusplus
  extern "C" {
 #endif
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
new file mode 100644
index 000000000..5deba27b5
--- /dev/null
+++ b/src/device/dcd_attr.h
@@ -0,0 +1,146 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_DCD_ATTR_H_
+#define TUSB_DCD_ATTR_H_
+
+#include "tusb_option.h"
+
+// Attribute includes
+// - ENDPOINT_MAX: max (logical) number of endpoint
+// - ENDPOINT_EXCLUSIVE_NUMBER: endpoint number with different direction IN and OUT aren't allowed,
+//                              e.g EP1 OUT & EP1 IN cannot exist together
+
+//------------- NXP -------------//
+#if   TU_CHECK_MCU(LPC11UXX) || TU_CHECK_MCU(LPC13XX) || TU_CHECK_MCU(LPC15XX)
+  #define DCD_ATTR_ENDPOINT_MAX   5
+
+#elif TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+  #define DCD_ATTR_ENDPOINT_MAX   16
+
+#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX)
+  // TODO USB0 has 6, USB1 has 4
+  #define DCD_ATTR_ENDPOINT_MAX   6
+
+#elif TU_CHECK_MCU(LPC51UXX)
+   #define DCD_ATTR_ENDPOINT_MAX   5
+
+#elif TU_CHECK_MCU(LPC54XXX) || TU_CHECK_MCU(LPC55XX)
+  // TODO USB0 has 5, USB1 has 6
+  #define DCD_ATTR_ENDPOINT_MAX   6
+
+#elif TU_CHECK_MCU(MIMXRT10XX)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
+#elif TU_CHECK_MCU(MKL25ZXX)
+  #define DCD_ATTR_ENDPOINT_MAX   16
+
+//------------- Nordic -------------//
+#elif TU_CHECK_MCU(NRF5X)
+  // 8 CBI + 1 ISO
+  #define DCD_ATTR_ENDPOINT_MAX   9
+
+//------------- Microchip -------------//
+#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \
+      TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
+#elif TU_CHECK_MCU(SAMG)
+  #define DCD_ATTR_ENDPOINT_MAX   6
+  #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+
+//------------- ST -------------//
+#elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \
+      TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4)
+  // F1: F102, F103
+  // L4: L4x2, L4x3
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
+#elif TU_CHECK_MCU(STM32F2) || TU_CHECK_MCU(STM32F4) || TU_CHECK_MCU(STM32F3)
+  // F1: F105, F107 only has 4
+  // L4: L4x5, L4x6 has 6
+  // For most mcu, FS has 4, HS has 6
+  #define DCD_ATTR_ENDPOINT_MAX   6
+
+#elif TU_CHECK_MCU(STM32F7)
+  // FS has 6, HS has 9
+  #define DCD_ATTR_ENDPOINT_MAX   9
+
+#elif TU_CHECK_MCU(STM32H7)
+  #define DCD_ATTR_ENDPOINT_MAX   9
+
+//------------- Sony -------------//
+#elif TU_CHECK_MCU(CXD56)
+  #define DCD_ATTR_ENDPOINT_MAX   7
+  #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+
+//------------- TI -------------//
+#elif TU_CHECK_MCU(MSP430x5xx)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
+//------------- ValentyUSB -------------//
+#elif TU_CHECK_MCU(VALENTYUSB_EPTRI)
+  #define DCD_ATTR_ENDPOINT_MAX   16
+
+//------------- Nuvoton -------------//
+#elif TU_CHECK_MCU(NUC121) || TU_CHECK_MCU(NUC126)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
+#elif TU_CHECK_MCU(NUC120)
+  #define DCD_ATTR_ENDPOINT_MAX   6
+
+#elif TU_CHECK_MCU(NUC505)
+  #define DCD_ATTR_ENDPOINT_MAX   12
+
+//------------- Espressif -------------//
+#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+  #define DCD_ATTR_ENDPOINT_MAX   6
+
+//------------- Dialog -------------//
+#elif TU_CHECK_MCU(DA1469X)
+  #define DCD_ATTR_ENDPOINT_MAX   4
+
+//------------- Raspberry Pi -------------//
+#elif TU_CHECK_MCU(RP2040)
+  #define DCD_ATTR_ENDPOINT_MAX   16
+
+//------------- Silabs -------------//
+#elif TU_CHECK_MCU(EFM32GG)
+  #define DCD_ATTR_ENDPOINT_MAX   7
+
+//------------- Renesas -------------//
+#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X)
+  #define DCD_ATTR_ENDPOINT_MAX   10
+
+//#elif TU_CHECK_MCU(MM32F327X)
+//  #define DCD_ATTR_ENDPOINT_MAX not knwon yet
+
+#else
+  #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
+  #define DCD_ATTR_ENDPOINT_MAX   8
+#endif
+
+#endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index af4fd58c4..7de3c4377 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -33,12 +33,20 @@
 #include "device/usbd_pvt.h"
 #include "device/dcd.h"
 
-#ifndef CFG_TUD_TASK_QUEUE_SZ
-#define CFG_TUD_TASK_QUEUE_SZ   16
+//--------------------------------------------------------------------+
+// USBD Configuration
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+  #define CFG_TUD_ENDPOINT0_SIZE  64
 #endif
 
-#ifndef CFG_TUD_EP_MAX
-#define CFG_TUD_EP_MAX          9
+#ifndef CFG_TUD_TASK_QUEUE_SZ
+  #define CFG_TUD_TASK_QUEUE_SZ   16
+#endif
+
+#ifndef CFG_TUD_ENDPPOINT_MAX
+  #define CFG_TUD_ENDPPOINT_MAX   DCD_ATTR_ENDPOINT_MAX
 #endif
 
 //--------------------------------------------------------------------+
@@ -65,7 +73,7 @@ typedef struct
   uint8_t speed;
 
   uint8_t itf2drv[16];     // map interface number to driver (0xff is invalid)
-  uint8_t ep2drv[CFG_TUD_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid )
+  uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid )
 
   struct TU_ATTR_PACKED
   {
@@ -74,7 +82,7 @@ typedef struct
     volatile bool claimed : 1;
 
     // TODO merge ep2drv here, 4-bit should be sufficient
-  }ep_status[CFG_TUD_EP_MAX][2];
+  }ep_status[CFG_TUD_ENDPPOINT_MAX][2];
 
 }usbd_device_t;
 
@@ -1151,6 +1159,7 @@ void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr)
 bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
 {
   TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, desc_ep->wMaxPacketSize.size);
+  TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < DCD_ATTR_ENDPOINT_MAX);
 
   switch (desc_ep->bmAttributes.xfer)
   {
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 2de6a5cfd..e6a4d550b 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -24,9 +24,6 @@
  * This file is part of the TinyUSB stack.
  */
 
-/** \ingroup group_usbd
- *  @{ */
-
 #ifndef _TUSB_USBD_H_
 #define _TUSB_USBD_H_
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 13d11fdfe..e24e5947c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -32,9 +32,11 @@
 #define TUSB_VERSION_REVISION  1
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
 
-/** \defgroup group_mcu Supported MCU
- * \ref CFG_TUSB_MCU must be defined to one of these
- *  @{ */
+//--------------------------------------------------------------------+
+// Supported MCUs
+// CFG_TUSB_MCU must be defined to one of following value
+//--------------------------------------------------------------------+
+#define TU_CHECK_MCU(_m)            (CFG_TUSB_MCU == OPT_MCU_##_m)
 
 #define OPT_MCU_NONE                0
 
@@ -119,18 +121,16 @@
 // Mind Motion
 #define OPT_MCU_MM32F327X        1500 ///< Mind Motion MM32F327
 
-/** @} */
+//--------------------------------------------------------------------+
+// Supported OS
+//--------------------------------------------------------------------+
 
-/** \defgroup group_supported_os Supported RTOS
- *  \ref CFG_TUSB_OS must be defined to one of these
- *  @{ */
 #define OPT_OS_NONE       1  ///< No RTOS
 #define OPT_OS_FREERTOS   2  ///< FreeRTOS
 #define OPT_OS_MYNEWT     3  ///< Mynewt OS
 #define OPT_OS_CUSTOM     4  ///< Custom OS is implemented by application
 #define OPT_OS_PICO       5  ///< Raspberry Pi Pico SDK
 #define OPT_OS_RTTHREAD   6  ///< RT-Thread
-/** @} */
 
 // Allow to use command line to change the config name/location
 #ifdef CFG_TUSB_CONFIG_FILE
@@ -139,10 +139,6 @@
   #include "tusb_config.h"
 #endif
 
-/** \addtogroup group_configuration
- *  @{ */
-
-
 //--------------------------------------------------------------------
 // RootHub Mode Configuration
 // CFG_TUSB_RHPORTx_MODE contains operation mode and speed for that port
@@ -214,10 +210,6 @@
 // DEVICE OPTIONS
 //--------------------------------------------------------------------
 
-#ifndef CFG_TUD_ENDPOINT0_SIZE
-  #define CFG_TUD_ENDPOINT0_SIZE  64
-#endif
-
 #ifndef CFG_TUD_CDC
   #define CFG_TUD_CDC             0
 #endif
@@ -277,7 +269,7 @@
 
   //------------- HUB CLASS -------------//
   #if CFG_TUH_HUB && (CFG_TUSB_HOST_DEVICE_MAX == 1)
-    #error there is no benefit enable hub with max device is 1. Please disable hub or increase CFG_TUSB_HOST_DEVICE_MAX
+    #error There is no benefit enable hub with max device is 1. Please disable hub or increase CFG_TUSB_HOST_DEVICE_MAX
   #endif
 
   #ifndef CFG_TUH_ENUMERATION_BUFSIZE
@@ -288,12 +280,11 @@
 #endif // TUSB_OPT_HOST_ENABLED
 
 //--------------------------------------------------------------------+
-// Port Options
-// TUP for TinyUSB Port (can be renamed)
+// Port Specific
+// TUP stand for TinyUSB Port (can be renamed)
 //--------------------------------------------------------------------+
 
-// TUP_ARCH_STRICT_ALIGN if arch cannot access unaligned memory
-
+//------------- Unaligned Memory -------------//
 
 // ARMv7+ (M3-M7, M23-M33) can access unaligned memory
 #if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
@@ -312,6 +303,7 @@
   #define TUP_MCU_STRICT_ALIGN   0
 #endif
 
+
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------

From 37cac414f83fb939d8b9e4c41d5fa49a6f0e309e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Jul 2021 17:00:02 +0700
Subject: [PATCH 0229/2085] fix ci

---
 src/device/dcd.h      | 13 ++++++++++++-
 src/device/dcd_attr.h | 12 +++++++++++-
 src/device/usbd.c     |  8 --------
 src/device/usbd.h     |  4 ++--
 src/tusb_option.h     |  4 ++++
 5 files changed, 29 insertions(+), 12 deletions(-)

diff --git a/src/device/dcd.h b/src/device/dcd.h
index 11f8ca5d3..8bfad9b72 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -30,13 +30,24 @@
 #include "common/tusb_common.h"
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
-
 #include "dcd_attr.h"
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Configuration
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUD_ENDPPOINT_MAX
+  #define CFG_TUD_ENDPPOINT_MAX   DCD_ATTR_ENDPOINT_MAX
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
 typedef enum
 {
   DCD_EVENT_INVALID = 0,
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 5deba27b5..2fd235a96 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -33,6 +33,7 @@
 // - ENDPOINT_MAX: max (logical) number of endpoint
 // - ENDPOINT_EXCLUSIVE_NUMBER: endpoint number with different direction IN and OUT aren't allowed,
 //                              e.g EP1 OUT & EP1 IN cannot exist together
+// - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
 
 //------------- NXP -------------//
 #if   TU_CHECK_MCU(LPC11UXX) || TU_CHECK_MCU(LPC13XX) || TU_CHECK_MCU(LPC15XX)
@@ -48,7 +49,11 @@
 #elif TU_CHECK_MCU(LPC51UXX)
    #define DCD_ATTR_ENDPOINT_MAX   5
 
-#elif TU_CHECK_MCU(LPC54XXX) || TU_CHECK_MCU(LPC55XX)
+#elif TU_CHECK_MCU(LPC54XXX)
+  // TODO USB0 has 5, USB1 has 6
+  #define DCD_ATTR_ENDPOINT_MAX   6
+
+#elif TU_CHECK_MCU(LPC55XX)
   // TODO USB0 has 5, USB1 has 6
   #define DCD_ATTR_ENDPOINT_MAX   6
 
@@ -143,4 +148,9 @@
   #define DCD_ATTR_ENDPOINT_MAX   8
 #endif
 
+// Default to fullspeed if not defined
+//#ifndef PORT_HIGHSPEED
+//  #define DCD_ATTR_PORT_HIGHSPEED 0x00
+//#endif
+
 #endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 7de3c4377..b724c73e8 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -37,18 +37,10 @@
 // USBD Configuration
 //--------------------------------------------------------------------+
 
-#ifndef CFG_TUD_ENDPOINT0_SIZE
-  #define CFG_TUD_ENDPOINT0_SIZE  64
-#endif
-
 #ifndef CFG_TUD_TASK_QUEUE_SZ
   #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
 
-#ifndef CFG_TUD_ENDPPOINT_MAX
-  #define CFG_TUD_ENDPPOINT_MAX   DCD_ATTR_ENDPOINT_MAX
-#endif
-
 //--------------------------------------------------------------------+
 // Device Data
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd.h b/src/device/usbd.h
index e6a4d550b..9500ad70c 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -27,12 +27,12 @@
 #ifndef _TUSB_USBD_H_
 #define _TUSB_USBD_H_
 
+#include "common/tusb_common.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "common/tusb_common.h"
-
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index e24e5947c..dfac46374 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -210,6 +210,10 @@
 // DEVICE OPTIONS
 //--------------------------------------------------------------------
 
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+  #define CFG_TUD_ENDPOINT0_SIZE  64
+#endif
+
 #ifndef CFG_TUD_CDC
   #define CFG_TUD_CDC             0
 #endif

From a9f3532252c09d2bcc0fc23994be3d0753a974ef Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Jul 2021 18:08:19 +0700
Subject: [PATCH 0230/2085] more ci

---
 src/device/dcd_attr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 2fd235a96..4bba03c87 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -133,7 +133,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 //------------- Silabs -------------//
-#elif TU_CHECK_MCU(EFM32GG)
+#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(OPT_MCU_EFM32GG11) || TU_CHECK_MCU(OPT_MCU_EFM32GG12)
   #define DCD_ATTR_ENDPOINT_MAX   7
 
 //------------- Renesas -------------//

From 8ee1141a70dd40063c667ea2b117590a174d9ea6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Jul 2021 18:25:53 +0700
Subject: [PATCH 0231/2085] correct check

---
 src/device/dcd_attr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 4bba03c87..544b0a75b 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -133,7 +133,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 //------------- Silabs -------------//
-#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(OPT_MCU_EFM32GG11) || TU_CHECK_MCU(OPT_MCU_EFM32GG12)
+#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12)
   #define DCD_ATTR_ENDPOINT_MAX   7
 
 //------------- Renesas -------------//

From aff7b100ca87482e9e1d29f7e854d77cadbd6b98 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Jul 2021 00:28:37 +0700
Subject: [PATCH 0232/2085] update dcd attr for samx7x

---
 src/device/dcd_attr.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 544b0a75b..306335642 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -77,6 +77,10 @@
   #define DCD_ATTR_ENDPOINT_MAX   6
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
+#elif TU_CHECK_MCU(SAMX7X)
+  #define DCD_ATTR_ENDPOINT_MAX   10
+  #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+
 //------------- ST -------------//
 #elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \
       TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4)

From 9542fcdbcda23a08fb4d7901bbb01333b6465bfc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Jul 2021 01:00:06 +0700
Subject: [PATCH 0233/2085] rename CFG_TUD_DFU_TRANSFER_BUFSIZE to
 CFG_TUD_DFU_XFER_BUFSIZE

---
 examples/device/dfu/.skip.MCU_SAMD11      |   0
 examples/device/dfu/src/tusb_config.h     |   2 +-
 examples/device/dfu/src/usb_descriptors.c |   2 +-
 src/class/dfu/dfu_device.c                | 243 +---------------------
 src/class/dfu/dfu_device.h                |   4 +-
 5 files changed, 9 insertions(+), 242 deletions(-)
 delete mode 100644 examples/device/dfu/.skip.MCU_SAMD11

diff --git a/examples/device/dfu/.skip.MCU_SAMD11 b/examples/device/dfu/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 2e3b89f49..66e357021 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -80,7 +80,7 @@
 #define CFG_TUD_DFU    1
 
 // DFU buffer size, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
-#define CFG_TUD_DFU_TRANSFER_BUFSIZE    512
+#define CFG_TUD_DFU_XFER_BUFSIZE    512
 
 #ifdef __cplusplus
  }
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index a15bb6136..1cfe29c53 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -100,7 +100,7 @@ uint8_t const desc_configuration[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
   // Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size
-  TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, ALT_COUNT, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_TRANSFER_BUFSIZE),
+  TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, ALT_COUNT, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_XFER_BUFSIZE),
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 222795bec..ad87092e0 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -52,7 +52,7 @@ typedef struct
   uint16_t block;
   uint16_t length;
 
-  CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_TRANSFER_BUFSIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_XFER_BUFSIZE];
 } dfu_state_ctx_t;
 
 // Only a single dfu state is allowed
@@ -189,9 +189,9 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
 
   _dfu_ctx.attrs = func_desc->bAttributes;
 
-  // CFG_TUD_DFU_TRANSFER_BUFSIZE has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
+  // CFG_TUD_DFU_XFER_BUFSIZE has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
   uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16(&func_desc->wTransferSize) );
-  TU_ASSERT(transfer_size <= CFG_TUD_DFU_TRANSFER_BUFSIZE, drv_len);
+  TU_ASSERT(transfer_size <= CFG_TUD_DFU_XFER_BUFSIZE, drv_len);
 
   return drv_len;
 }
@@ -281,7 +281,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
         {
           TU_VERIFY(_dfu_ctx.attrs & DFU_ATTR_CAN_UPLOAD);
           TU_VERIFY(tud_dfu_upload_cb);
-          TU_VERIFY(request->wLength <= CFG_TUD_DFU_TRANSFER_BUFSIZE);
+          TU_VERIFY(request->wLength <= CFG_TUD_DFU_XFER_BUFSIZE);
 
           uint16_t const xfer_len = tud_dfu_upload_cb(_dfu_ctx.alt, request->wValue, _dfu_ctx.transfer_buf, request->wLength);
 
@@ -294,7 +294,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
         {
           TU_VERIFY(_dfu_ctx.attrs & DFU_ATTR_CAN_DOWNLOAD);
           TU_VERIFY(_dfu_ctx.state == DFU_IDLE || _dfu_ctx.state == DFU_DNLOAD_IDLE);
-          TU_VERIFY(request->wLength <= CFG_TUD_DFU_TRANSFER_BUFSIZE);
+          TU_VERIFY(request->wLength <= CFG_TUD_DFU_XFER_BUFSIZE);
 
           // set to true for both download and manifest
           _dfu_ctx.flashing_in_progress = true;
@@ -455,237 +455,4 @@ static bool reply_getstatus(uint8_t rhport, tusb_control_request_t const * reque
   return tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_response_t));
 }
 
-
-#if 0
-
-static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const * request);
-static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request);
-static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * request);
-
-static void dfu_req_dnload_setup(uint8_t rhport, tusb_control_request_t const * request)
-{
-  // TODO: add "zero" copy mode so the buffer we read into can be provided by the user
-  // if they wish, there still will be the internal control buffer copy to this buffer
-  // but this mode would provide zero copy from the class driver to the application
-
-  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFSIZE, );
-  // setup for data phase
-  tud_control_xfer(rhport, request, _dfu_ctx.transfer_buf, request->wLength);
-}
-
-static void dfu_req_dnload_reply(uint8_t rhport, tusb_control_request_t const * request)
-{
-  (void) rhport;
-  TU_VERIFY( request->wLength <= CFG_TUD_DFU_TRANSFER_BUFSIZE, );
-  tud_dfu_download_cb(_dfu_ctx.alt,_dfu_ctx.block, (uint8_t *)_dfu_ctx.transfer_buf, _dfu_ctx.length);
-  _dfu_ctx.flashing_in_progress = false;
-}
-
-static bool dfu_state_machine(uint8_t rhport, tusb_control_request_t const * request)
-{
-  TU_LOG2("  DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest));
-  TU_LOG2("  DFU State Machine: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state));
-
-  switch (_dfu_ctx.state)
-  {
-    case DFU_IDLE:
-    {
-      switch (request->bRequest)
-      {
-        case DFU_REQUEST_DNLOAD:
-        {
-          if( ((_dfu_ctx.attrs & DFU_ATTR_CAN_DOWNLOAD) != 0)
-              && (request->wLength > 0) )
-          {
-            _dfu_ctx.state = DFU_DNLOAD_SYNC;
-            _dfu_ctx.flashing_in_progress = true;
-            dfu_req_dnload_setup(rhport, request);
-          } else {
-            _dfu_ctx.state = DFU_ERROR;
-          }
-        }
-        break;
-
-        case DFU_REQUEST_GETSTATUS:
-          reply_getstatus(rhport, request);
-        break;
-
-        default:
-          _dfu_ctx.state = DFU_ERROR;
-          return false;  // stall on all other requests
-        break;
-      }
-    }
-    break;
-
-    case DFU_DNLOAD_SYNC:
-    {
-      switch (request->bRequest)
-      {
-        case DFU_REQUEST_GETSTATUS:
-        {
-          if ( _dfu_ctx.flashing_in_progress )
-          {
-            _dfu_ctx.state = DFU_DNBUSY;
-            reply_getstatus(rhport, request);
-            dfu_req_dnload_reply(rhport, request);
-          } else {
-            _dfu_ctx.state = DFU_DNLOAD_IDLE;
-            reply_getstatus(rhport, request);
-          }
-        }
-        break;
-
-        default:
-          _dfu_ctx.state = DFU_ERROR;
-          return false;  // stall on all other requests
-        break;
-      }
-    }
-    break;
-
-    case DFU_DNBUSY:
-    {
-      switch (request->bRequest)
-      {
-        default:
-          _dfu_ctx.state = DFU_ERROR;
-          return false;  // stall on all other requests
-        break;
-      }
-    }
-    break;
-
-    case DFU_DNLOAD_IDLE:
-    {
-        switch (request->bRequest)
-        {
-          case DFU_REQUEST_DNLOAD:
-          {
-            if( ((_dfu_ctx.attrs & DFU_ATTR_CAN_DOWNLOAD) != 0)
-                && (request->wLength > 0) )
-            {
-              _dfu_ctx.state = DFU_DNLOAD_SYNC;
-              _dfu_ctx.flashing_in_progress = true;
-              dfu_req_dnload_setup(rhport, request);
-            } else {
-              if ( tud_dfu_download_complete_cb(_dfu_ctx.alt) )
-              {
-                _dfu_ctx.state = DFU_MANIFEST_SYNC;
-                tud_control_status(rhport, request);
-              } else {
-                _dfu_ctx.state = DFU_ERROR;
-                return false;  // stall
-              }
-            }
-          }
-          break;
-
-          case DFU_REQUEST_GETSTATUS:
-            reply_getstatus(rhport, request);
-          break;
-
-          default:
-            _dfu_ctx.state = DFU_ERROR;
-            return false;  // stall on all other requests
-          break;
-        }
-    }
-    break;
-
-    case DFU_MANIFEST_SYNC:
-    {
-      switch (request->bRequest)
-      {
-        case DFU_REQUEST_GETSTATUS:
-        {
-          if ((_dfu_ctx.attrs & DFU_ATTR_MANIFESTATION_TOLERANT) == 0)
-          {
-            _dfu_ctx.state = DFU_MANIFEST;
-            reply_getstatus(rhport, request);
-          } else 
-          {
-            if ( tud_dfu_manifest_cb(_dfu_ctx.alt) )
-            {
-              _dfu_ctx.state = DFU_IDLE;
-            }
-            reply_getstatus(rhport, request);
-          }
-        }
-        break;
-
-        default:
-          _dfu_ctx.state = DFU_ERROR;
-          return false;  // stall on all other requests
-        break;
-      }
-    }
-    break;
-
-    case DFU_MANIFEST:
-    {
-      switch (request->bRequest)
-      {
-        // stall on all other requests
-        default:
-          return false;
-        break;
-      }
-    }
-    break;
-
-    case DFU_MANIFEST_WAIT_RESET:
-    {
-      // technically we should never even get here, but we will handle it just in case
-      TU_LOG2("  DFU was in DFU_MANIFEST_WAIT_RESET and got unexpected request: %u\r\n", request->bRequest);
-      switch (request->bRequest)
-      {
-        default:
-          return false;  // stall on all other requests
-        break;
-      }
-    }
-    break;
-
-    case DFU_UPLOAD_IDLE:
-    {
-      switch (request->bRequest)
-      {
-        case DFU_REQUEST_GETSTATUS:
-          reply_getstatus(rhport, request);
-        break;
-
-        default:
-          return false;  // stall on all other requests
-        break;
-      }
-    }
-    break;
-
-    case DFU_ERROR:
-    {
-      switch (request->bRequest)
-      {
-        case DFU_REQUEST_GETSTATUS:
-          reply_getstatus(rhport, request);
-        break;
-
-        default:
-          return false;  // stall on all other requests
-        break;
-      }
-    }
-    break;
-
-    default:
-      _dfu_ctx.state = DFU_ERROR;
-      TU_LOG2("  DFU ERROR: Unexpected state\r\nStalling control pipe\r\n");
-      return false;  // Unexpected state, stall and change to error
-  }
-
-  return true;
-}
-
-#endif
-
 #endif
diff --git a/src/class/dfu/dfu_device.h b/src/class/dfu/dfu_device.h
index 2d398aada..fecf8596f 100644
--- a/src/class/dfu/dfu_device.h
+++ b/src/class/dfu/dfu_device.h
@@ -37,8 +37,8 @@
 // Class Driver Default Configure & Validation
 //--------------------------------------------------------------------+
 
-#if !defined(CFG_TUD_DFU_TRANSFER_BUFSIZE)
-  #error "CFG_TUD_DFU_TRANSFER_BUFSIZE must be defined, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR"
+#if !defined(CFG_TUD_DFU_XFER_BUFSIZE)
+  #error "CFG_TUD_DFU_XFER_BUFSIZE must be defined, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR"
 #endif
 
 //--------------------------------------------------------------------+

From b35ad6edcb8b723c481246532349d21b35c46ac1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Jul 2021 17:04:55 +0700
Subject: [PATCH 0234/2085] clean up max packet size endian

---
 src/device/dcd_attr.h |  4 ++--
 src/device/usbd.c     | 18 ++++++++++--------
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 306335642..18f369332 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -141,11 +141,11 @@
   #define DCD_ATTR_ENDPOINT_MAX   7
 
 //------------- Renesas -------------//
-#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X)
+#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N)
   #define DCD_ATTR_ENDPOINT_MAX   10
 
 //#elif TU_CHECK_MCU(MM32F327X)
-//  #define DCD_ATTR_ENDPOINT_MAX not knwon yet
+//  #define DCD_ATTR_ENDPOINT_MAX not known yet
 
 #else
   #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
diff --git a/src/device/usbd.c b/src/device/usbd.c
index e4f2e1cf9..5a7d0ab0f 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1150,15 +1150,17 @@ void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr)
 
 bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
 {
-  TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, tu_le16toh(desc_ep->wMaxPacketSize.size));
-  TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < DCD_ATTR_ENDPOINT_MAX);
+  uint16_t const max_packet_size = tu_le16toh(desc_ep->wMaxPacketSize.size);
+
+  TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size);
+  TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX);
 
   switch (desc_ep->bmAttributes.xfer)
   {
     case TUSB_XFER_ISOCHRONOUS:
     {
-      uint16_t const max_epsize = (_usbd_dev.speed == TUSB_SPEED_HIGH ? 1024 : 1023);
-      TU_ASSERT(tu_le16toh(desc_ep->wMaxPacketSize.size) <= max_epsize);
+      uint16_t const spec_size = (_usbd_dev.speed == TUSB_SPEED_HIGH ? 1024 : 1023);
+      TU_ASSERT(max_packet_size <= spec_size);
     }
     break;
 
@@ -1166,18 +1168,18 @@ bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
       if (_usbd_dev.speed == TUSB_SPEED_HIGH)
       {
         // Bulk highspeed must be EXACTLY 512
-        TU_ASSERT(tu_le16toh(desc_ep->wMaxPacketSize.size) == 512);
+        TU_ASSERT(max_packet_size == 512);
       }else
       {
         // TODO Bulk fullspeed can only be 8, 16, 32, 64
-        TU_ASSERT(tu_le16toh(desc_ep->wMaxPacketSize.size) <= 64);
+        TU_ASSERT(max_packet_size <= 64);
       }
     break;
 
     case TUSB_XFER_INTERRUPT:
     {
-      uint16_t const max_epsize = (_usbd_dev.speed == TUSB_SPEED_HIGH ? 1024 : 64);
-      TU_ASSERT(tu_le16toh(desc_ep->wMaxPacketSize.size) <= max_epsize);
+      uint16_t const spec_size = (_usbd_dev.speed == TUSB_SPEED_HIGH ? 1024 : 64);
+      TU_ASSERT(max_packet_size <= spec_size);
     }
     break;
 

From 4e50ceba48c15206543fe662f098a98152ef4235 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Jul 2021 17:07:39 +0700
Subject: [PATCH 0235/2085] rename packed begin/end

---
 src/class/cdc/cdc.h                  | 20 ++++++++++----------
 src/common/tusb_compiler.h           |  8 ++++----
 src/common/tusb_types.h              |  4 ++--
 src/portable/renesas/usba/dcd_usba.c |  4 ++--
 4 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index f59690835..7a06711be 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -215,7 +215,7 @@ typedef enum
 // Class Specific Functional Descriptor (Communication Interface)
 //--------------------------------------------------------------------+
 
-TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
 
 /// Header Functional Descriptor (Communication Interface)
 typedef struct TU_ATTR_PACKED
@@ -236,10 +236,10 @@ typedef struct TU_ATTR_PACKED
   uint8_t bSubordinateInterface    ; ///< Array of Interface number of Data Interface
 }cdc_desc_func_union_t;
 
-TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 #define cdc_desc_func_union_n_t(no_slave)\
- TU_PACK_STRUCT_BEGIN                      \
+ TU_ATTR_PACKED_BEGIN                      \
  struct TU_ATTR_PACKED {                   \
   uint8_t bLength                         ;\
   uint8_t bDescriptorType                 ;\
@@ -247,10 +247,10 @@ TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX too
   uint8_t bControlInterface               ;\
   uint8_t bSubordinateInterface[no_slave] ;\
 }                                          \
-TU_PACK_STRUCT_END
+TU_ATTR_PACKED_END
 
 
-TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
 
 /// Country Selection Functional Descriptor (Communication Interface)
 typedef struct TU_ATTR_PACKED
@@ -262,10 +262,10 @@ typedef struct TU_ATTR_PACKED
   uint16_t wCountryCode       ; ///< Country code in the format as defined in [ISO3166], release date as specified inoffset 3 for the first supported country.
 }cdc_desc_func_country_selection_t;
 
-TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 #define cdc_desc_func_country_selection_n_t(no_country) \
-  TU_PACK_STRUCT_BEGIN               \
+  TU_ATTR_PACKED_BEGIN               \
   struct TU_ATTR_PACKED {            \
   uint8_t bLength                   ;\
   uint8_t bDescriptorType           ;\
@@ -273,13 +273,13 @@ TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX too
   uint8_t iCountryCodeRelDate       ;\
   uint16_t wCountryCode[no_country] ;\
 }                                    \
-TU_PACK_STRUCT_END
+TU_ATTR_PACKED_END
 
 //--------------------------------------------------------------------+
 // PUBLIC SWITCHED TELEPHONE NETWORK (PSTN) SUBCLASS
 //--------------------------------------------------------------------+
 
-TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
 
 /// \brief Call Management Functional Descriptor
 /// \details This functional descriptor describes the processing of calls for the Communications Class interface.
@@ -419,7 +419,7 @@ typedef struct TU_ATTR_PACKED
 } cdc_line_control_state_t;
 TU_BIT_FIELD_ORDER_END
 
-TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 
 TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct");
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 6fdd08032..1f3128e0e 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -79,8 +79,8 @@
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))             // Function/Variable is meant to be used
 
-  #define TU_PACK_STRUCT_BEGIN
-  #define TU_PACK_STRUCT_END
+  #define TU_ATTR_PACKED_BEGIN
+  #define TU_ATTR_PACKED_END
 
   #define TU_BIT_FIELD_ORDER_BEGIN
   #define TU_BIT_FIELD_ORDER_END
@@ -150,8 +150,8 @@
   #define TU_ATTR_UNUSED
   #define TU_ATTR_USED
 
-  #define TU_PACK_STRUCT_BEGIN _Pragma("pack")
-  #define TU_PACK_STRUCT_END _Pragma("packoption")
+  #define TU_ATTR_PACKED_BEGIN _Pragma("pack")
+  #define TU_ATTR_PACKED_END _Pragma("packoption")
 
   #define TU_BIT_FIELD_ORDER_BEGIN _Pragma("bit_order right")
   #define TU_BIT_FIELD_ORDER_END _Pragma("bit_order")
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index f34eb3075..34395365e 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -262,7 +262,7 @@ enum
 // USB Descriptors
 //--------------------------------------------------------------------+
 
-TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
 
 /// USB Device Descriptor
 typedef struct TU_ATTR_PACKED
@@ -479,7 +479,7 @@ typedef struct TU_ATTR_PACKED{
 } tusb_control_request_t;
 TU_BIT_FIELD_ORDER_END
 
-TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 67b92dc89..0c206fdd0 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -120,7 +120,7 @@ typedef union {
 } hw_fifo_t;
 TU_BIT_FIELD_ORDER_END
 
-TU_PACK_STRUCT_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
 
 TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
@@ -135,7 +135,7 @@ typedef struct TU_ATTR_PACKED
 } pipe_state_t;
 TU_BIT_FIELD_ORDER_END
 
-TU_PACK_STRUCT_END  // End of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 typedef struct
 {

From c4da1abb1eaa7aff432535878ada519d02382419 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Jul 2021 17:24:59 +0700
Subject: [PATCH 0236/2085] rename bit filed order

clean up packed/bit order begin end
---
 src/class/cdc/cdc.h                  | 41 ++++++----------------------
 src/common/tusb_compiler.h           |  8 +++---
 src/common/tusb_types.h              | 24 +++++++---------
 src/portable/renesas/usba/dcd_usba.c | 12 ++++----
 4 files changed, 28 insertions(+), 57 deletions(-)

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index 7a06711be..6042cefe3 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -215,7 +215,9 @@ typedef enum
 // Class Specific Functional Descriptor (Communication Interface)
 //--------------------------------------------------------------------+
 
-TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+// Start of all packed definitions for compiler without per-type packed
+TU_ATTR_PACKED_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
 /// Header Functional Descriptor (Communication Interface)
 typedef struct TU_ATTR_PACKED
@@ -236,10 +238,7 @@ typedef struct TU_ATTR_PACKED
   uint8_t bSubordinateInterface    ; ///< Array of Interface number of Data Interface
 }cdc_desc_func_union_t;
 
-TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
-
 #define cdc_desc_func_union_n_t(no_slave)\
- TU_ATTR_PACKED_BEGIN                      \
  struct TU_ATTR_PACKED {                   \
   uint8_t bLength                         ;\
   uint8_t bDescriptorType                 ;\
@@ -247,10 +246,6 @@ TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX too
   uint8_t bControlInterface               ;\
   uint8_t bSubordinateInterface[no_slave] ;\
 }                                          \
-TU_ATTR_PACKED_END
-
-
-TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
 
 /// Country Selection Functional Descriptor (Communication Interface)
 typedef struct TU_ATTR_PACKED
@@ -262,10 +257,7 @@ typedef struct TU_ATTR_PACKED
   uint16_t wCountryCode       ; ///< Country code in the format as defined in [ISO3166], release date as specified inoffset 3 for the first supported country.
 }cdc_desc_func_country_selection_t;
 
-TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
-
 #define cdc_desc_func_country_selection_n_t(no_country) \
-  TU_ATTR_PACKED_BEGIN               \
   struct TU_ATTR_PACKED {            \
   uint8_t bLength                   ;\
   uint8_t bDescriptorType           ;\
@@ -273,17 +265,13 @@ TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX too
   uint8_t iCountryCodeRelDate       ;\
   uint16_t wCountryCode[no_country] ;\
 }                                    \
-TU_ATTR_PACKED_END
 
 //--------------------------------------------------------------------+
 // PUBLIC SWITCHED TELEPHONE NETWORK (PSTN) SUBCLASS
 //--------------------------------------------------------------------+
 
-TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
-
 /// \brief Call Management Functional Descriptor
 /// \details This functional descriptor describes the processing of calls for the Communications Class interface.
-TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
@@ -298,10 +286,7 @@ typedef struct TU_ATTR_PACKED
 
   uint8_t bDataInterface;
 }cdc_desc_func_call_management_t;
-TU_BIT_FIELD_ORDER_END
 
-
-TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t support_comm_request                    : 1; ///< Device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature.
@@ -310,12 +295,11 @@ typedef struct TU_ATTR_PACKED
   uint8_t support_notification_network_connection : 1; ///< Device supports the notification Network_Connection.
   uint8_t TU_RESERVED                             : 4;
 }cdc_acm_capability_t;
-TU_BIT_FIELD_ORDER_END
 
 TU_VERIFY_STATIC(sizeof(cdc_acm_capability_t) == 1, "mostly problem with compiler");
 
-/// \brief Abstract Control Management Functional Descriptor
-/// \details This functional descriptor describes the commands supported by by the Communications Class interface with SubClass code of \ref CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL
+/// Abstract Control Management Functional Descriptor
+/// This functional descriptor describes the commands supported by by the Communications Class interface with SubClass code of \ref CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength                  ; ///< Size of this descriptor in bytes.
@@ -326,7 +310,6 @@ typedef struct TU_ATTR_PACKED
 
 /// \brief Direct Line Management Functional Descriptor
 /// \details This functional descriptor describes the commands supported by the Communications Class interface with SubClass code of \ref CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT
-TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
@@ -339,7 +322,6 @@ typedef struct TU_ATTR_PACKED
     uint8_t TU_RESERVED           : 5;
   } bmCapabilities;
 }cdc_desc_func_direct_line_management_t;
-TU_BIT_FIELD_ORDER_END
 
 /// \brief Telephone Ringer Functional Descriptor
 /// \details The Telephone Ringer functional descriptor describes the ringer capabilities supported by the Communications Class interface,
@@ -356,7 +338,6 @@ typedef struct TU_ATTR_PACKED
 /// \brief Telephone Operational Modes Functional Descriptor
 /// \details The Telephone Operational Modes functional descriptor describes the operational modes supported by
 /// the Communications Class interface, with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL
-TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
@@ -369,12 +350,10 @@ typedef struct TU_ATTR_PACKED
     uint8_t TU_RESERVED           : 5;
   } bmCapabilities;
 }cdc_desc_func_telephone_operational_modes_t;
-TU_BIT_FIELD_ORDER_END
 
 /// \brief Telephone Call and Line State Reporting Capabilities Descriptor
 /// \details The Telephone Call and Line State Reporting Capabilities functional descriptor describes the abilities of a
 /// telephone device to report optional call and line states.
-TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t bLength            ; ///< Size of this descriptor in bytes.
@@ -390,8 +369,8 @@ typedef struct TU_ATTR_PACKED
     uint32_t TU_RESERVED            : 26;
   } bmCapabilities;
 }cdc_desc_func_telephone_call_state_reporting_capabilities_t;
-TU_BIT_FIELD_ORDER_END
 
+// TODO remove
 static inline uint8_t cdc_functional_desc_typeof(uint8_t const * p_desc)
 {
   return p_desc[2];
@@ -410,21 +389,17 @@ typedef struct TU_ATTR_PACKED
 
 TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct");
 
-TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint16_t dte_is_present : 1; ///< Indicates to DCE if DTE is presentor not. This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR.
   uint16_t half_duplex_carrier_control : 1;
   uint16_t : 14;
 } cdc_line_control_state_t;
-TU_BIT_FIELD_ORDER_END
-
-TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
-
 
 TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct");
 
-/** @} */
+TU_ATTR_PACKED_END  // End of all packed definitions
+TU_ATTR_BIT_FIELD_ORDER_END
 
 #ifdef __cplusplus
  }
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 1f3128e0e..820782d65 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -82,8 +82,8 @@
   #define TU_ATTR_PACKED_BEGIN
   #define TU_ATTR_PACKED_END
 
-  #define TU_BIT_FIELD_ORDER_BEGIN
-  #define TU_BIT_FIELD_ORDER_END
+  #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
+  #define TU_ATTR_BIT_FIELD_ORDER_END
 
   // Endian conversion use well-known host to network (big endian) naming
   #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
@@ -153,8 +153,8 @@
   #define TU_ATTR_PACKED_BEGIN _Pragma("pack")
   #define TU_ATTR_PACKED_END _Pragma("packoption")
 
-  #define TU_BIT_FIELD_ORDER_BEGIN _Pragma("bit_order right")
-  #define TU_BIT_FIELD_ORDER_END _Pragma("bit_order")
+  #define TU_ATTR_BIT_FIELD_ORDER_BEGIN _Pragma("bit_order right")
+  #define TU_ATTR_BIT_FIELD_ORDER_END _Pragma("bit_order")
 
   // Endian conversion use well-known host to network (big endian) naming
   #if defined(__LIT)
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 34395365e..d23c6b2dd 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -262,7 +262,9 @@ enum
 // USB Descriptors
 //--------------------------------------------------------------------+
 
-TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
+// Start of all packed definitions for compiler without per-type packed
+TU_ATTR_PACKED_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
 /// USB Device Descriptor
 typedef struct TU_ATTR_PACKED
@@ -297,6 +299,8 @@ typedef struct TU_ATTR_PACKED
   uint8_t  bNumDeviceCaps  ; ///< Number of device capability descriptors in the BOS
 } tusb_desc_bos_t;
 
+TU_VERIFY_STATIC( sizeof(tusb_desc_bos_t) == 5, "size is not correct");
+
 /// USB Configuration Descriptor
 typedef struct TU_ATTR_PACKED
 {
@@ -328,8 +332,9 @@ typedef struct TU_ATTR_PACKED
   uint8_t  iInterface         ; ///< Index of string descriptor describing this interface
 } tusb_desc_interface_t;
 
+TU_VERIFY_STATIC( sizeof(tusb_desc_interface_t) == 9, "size is not correct");
+
 /// USB Endpoint Descriptor
-TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength          ; ///< Size of this descriptor in bytes
@@ -357,7 +362,6 @@ typedef struct TU_ATTR_PACKED
 
   uint8_t  bInterval        ; ///< Interval for polling endpoint for data transfers. Expressed in frames or microframes depending on the device operating speed (i.e., either 1 millisecond or 125 us units). \n- For full-/high-speed isochronous endpoints, this value must be in the range from 1 to 16. The bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \n- For full-/low-speed interrupt endpoints, the value of this field may be from 1 to 255. \n- For high-speed interrupt endpoints, the bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value must be from 1 to 16. \n- For high-speed bulk/control OUT endpoints, the bInterval must specify the maximum NAK rate of the endpoint. A value of 0 indicates the endpoint never NAKs. Other values indicate at most 1 NAK each bInterval number of microframes. This value must be in the range from 0 to 255. \n Refer to Chapter 5 of USB 2.0 specification for more information.
 } tusb_desc_endpoint_t;
-TU_BIT_FIELD_ORDER_END
 
 /// USB Other Speed Configuration Descriptor
 typedef struct TU_ATTR_PACKED
@@ -433,7 +437,6 @@ typedef struct TU_ATTR_PACKED
 } tusb_desc_webusb_url_t;
 
 // DFU Functional Descriptor
-TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength;
@@ -455,12 +458,10 @@ typedef struct TU_ATTR_PACKED
   uint16_t wTransferSize;
   uint16_t bcdDFUVersion;
 } tusb_desc_dfu_functional_t;
-TU_BIT_FIELD_ORDER_END
 
 /*------------------------------------------------------------------*/
 /* Types
  *------------------------------------------------------------------*/
-TU_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED{
   union {
     struct TU_ATTR_PACKED {
@@ -477,17 +478,12 @@ typedef struct TU_ATTR_PACKED{
   uint16_t wIndex;
   uint16_t wLength;
 } tusb_control_request_t;
-TU_BIT_FIELD_ORDER_END
-
-TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 
 TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 
-// TODO move to somewhere suitable
-static inline uint8_t bm_request_type(uint8_t direction, uint8_t type, uint8_t recipient)
-{
-  return ((uint8_t) (direction << 7)) | ((uint8_t) (type << 5)) | (recipient);
-}
+
+TU_ATTR_PACKED_END  // End of all packed definitions
+TU_ATTR_BIT_FIELD_ORDER_END
 
 //--------------------------------------------------------------------+
 // Endpoint helper
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 0c206fdd0..f68f97458 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -95,7 +95,7 @@
 #define FIFO_REQ_CLR         (1u)
 #define FIFO_COMPLETE        (1u<<1)
 
-TU_BIT_FIELD_ORDER_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
 typedef struct {
   union {
     struct {
@@ -108,9 +108,9 @@ typedef struct {
   };
   uint16_t TRN;
 } reg_pipetre_t;
-TU_BIT_FIELD_ORDER_END
+TU_ATTR_BIT_FIELD_ORDER_END
 
-TU_BIT_FIELD_ORDER_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
 typedef union {
   struct {
     volatile uint16_t u8: 8;
@@ -118,11 +118,11 @@ typedef union {
   };
   volatile uint16_t u16;
 } hw_fifo_t;
-TU_BIT_FIELD_ORDER_END
+TU_ATTR_BIT_FIELD_ORDER_END
 
 TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
 
-TU_BIT_FIELD_ORDER_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uintptr_t addr;      /* the start address of a transfer data buffer */
@@ -133,7 +133,7 @@ typedef struct TU_ATTR_PACKED
     uint32_t     : 0;
   };
 } pipe_state_t;
-TU_BIT_FIELD_ORDER_END
+TU_ATTR_BIT_FIELD_ORDER_END
 
 TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 

From 8cd23489d518e96594850207c91dfeefb6d6fb05 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Jul 2021 17:45:24 +0700
Subject: [PATCH 0237/2085] update endian

---
 src/device/usbd.c                    | 10 ++++------
 src/device/usbd_control.c            |  1 -
 src/portable/renesas/usba/dcd_usba.c | 13 +++++--------
 3 files changed, 9 insertions(+), 15 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 5a7d0ab0f..a30eab217 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -953,11 +953,10 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
       tusb_desc_bos_t const* desc_bos = (tusb_desc_bos_t const*) tud_descriptor_bos_cb();
 
-      uint16_t total_len;
       // Use offsetof to avoid pointer to the odd/misaligned address
-      memcpy(&total_len, (uint8_t*) desc_bos + offsetof(tusb_desc_bos_t, wTotalLength), 2);
+      uint16_t const total_len = tu_le16toh( tu_unaligned_read16((uint8_t*) desc_bos + offsetof(tusb_desc_bos_t, wTotalLength)) );
 
-      return tud_control_xfer(rhport, p_request, (void*) desc_bos, tu_le16toh(total_len));
+      return tud_control_xfer(rhport, p_request, (void*) desc_bos, total_len);
     }
     break;
 
@@ -968,11 +967,10 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       tusb_desc_configuration_t const* desc_config = (tusb_desc_configuration_t const*) tud_descriptor_configuration_cb(desc_index);
       TU_ASSERT(desc_config);
 
-      uint16_t total_len;
       // Use offsetof to avoid pointer to the odd/misaligned address
-      memcpy(&total_len, (uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength), 2);
+      uint16_t const total_len = tu_le16toh( tu_unaligned_read16((uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) );
 
-      return tud_control_xfer(rhport, p_request, (void*) desc_config, tu_le16toh(total_len));
+      return tud_control_xfer(rhport, p_request, (void*) desc_config, total_len);
     }
     break;
 
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 124f711a7..7a8244699 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -58,7 +58,6 @@ static usbd_control_xfer_t _ctrl_xfer;
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
 static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
 
-
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index f68f97458..0b78a6e46 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -95,7 +95,10 @@
 #define FIFO_REQ_CLR         (1u)
 #define FIFO_COMPLETE        (1u<<1)
 
+// Start of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
+
 typedef struct {
   union {
     struct {
@@ -108,9 +111,7 @@ typedef struct {
   };
   uint16_t TRN;
 } reg_pipetre_t;
-TU_ATTR_BIT_FIELD_ORDER_END
 
-TU_ATTR_BIT_FIELD_ORDER_BEGIN
 typedef union {
   struct {
     volatile uint16_t u8: 8;
@@ -118,11 +119,7 @@ typedef union {
   };
   volatile uint16_t u16;
 } hw_fifo_t;
-TU_ATTR_BIT_FIELD_ORDER_END
 
-TU_ATTR_PACKED_BEGIN  // Start of definition of packed structs (used by the CCRX toolchain)
-
-TU_ATTR_BIT_FIELD_ORDER_BEGIN
 typedef struct TU_ATTR_PACKED
 {
   uintptr_t addr;      /* the start address of a transfer data buffer */
@@ -133,9 +130,9 @@ typedef struct TU_ATTR_PACKED
     uint32_t     : 0;
   };
 } pipe_state_t;
-TU_ATTR_BIT_FIELD_ORDER_END
 
 TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_BIT_FIELD_ORDER_END
 
 typedef struct
 {
@@ -147,7 +144,7 @@ typedef struct
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION static dcd_data_t _dcd;
+static dcd_data_t _dcd;
 
 static uint32_t disable_interrupt(void)
 {

From 15112fdbba8cf4e9ad0d99fafd8b40f07f29fb6d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Jul 2021 22:10:48 +0700
Subject: [PATCH 0238/2085] clean up compiler

---
 src/class/cdc/cdc.h                  |  4 ++--
 src/common/tusb_compiler.h           | 18 +++++++++++++-----
 src/portable/renesas/usba/dcd_usba.c | 20 ++++----------------
 3 files changed, 19 insertions(+), 23 deletions(-)

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index 6042cefe3..5df47f70b 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -245,7 +245,7 @@ typedef struct TU_ATTR_PACKED
   uint8_t bDescriptorSubType              ;\
   uint8_t bControlInterface               ;\
   uint8_t bSubordinateInterface[no_slave] ;\
-}                                          \
+}
 
 /// Country Selection Functional Descriptor (Communication Interface)
 typedef struct TU_ATTR_PACKED
@@ -264,7 +264,7 @@ typedef struct TU_ATTR_PACKED
   uint8_t bDescriptorSubType        ;\
   uint8_t iCountryCodeRelDate       ;\
   uint16_t wCountryCode[no_country] ;\
-}                                    \
+}
 
 //--------------------------------------------------------------------+
 // PUBLIC SWITCHED TELEPHONE NETWORK (PSTN) SUBCLASS
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 820782d65..d3adbbc2d 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -81,7 +81,6 @@
 
   #define TU_ATTR_PACKED_BEGIN
   #define TU_ATTR_PACKED_END
-
   #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
   #define TU_ATTR_BIT_FIELD_ORDER_END
 
@@ -109,6 +108,11 @@
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))
 
+  #define TU_ATTR_PACKED_BEGIN
+  #define TU_ATTR_PACKED_END
+  #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
+  #define TU_ATTR_BIT_FIELD_ORDER_END
+
   // __BYTE_ORDER is defined in the TI ARM compiler, but not MSP430 (which is little endian)
   #if ((__BYTE_ORDER__) == (__ORDER_LITTLE_ENDIAN__)) || defined(__MSP430__)
     #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
@@ -130,6 +134,11 @@
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))             // Function/Variable is meant to be used
 
+  #define TU_ATTR_PACKED_BEGIN
+  #define TU_ATTR_PACKED_END
+  #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
+  #define TU_ATTR_BIT_FIELD_ORDER_END
+
   // Endian conversion use well-known host to network (big endian) naming
   #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
     #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
@@ -150,11 +159,10 @@
   #define TU_ATTR_UNUSED
   #define TU_ATTR_USED
 
-  #define TU_ATTR_PACKED_BEGIN _Pragma("pack")
-  #define TU_ATTR_PACKED_END _Pragma("packoption")
-
+  #define TU_ATTR_PACKED_BEGIN          _Pragma("pack")
+  #define TU_ATTR_PACKED_END            _Pragma("packoption")
   #define TU_ATTR_BIT_FIELD_ORDER_BEGIN _Pragma("bit_order right")
-  #define TU_ATTR_BIT_FIELD_ORDER_END _Pragma("bit_order")
+  #define TU_ATTR_BIT_FIELD_ORDER_END   _Pragma("bit_order")
 
   // Endian conversion use well-known host to network (big endian) naming
   #if defined(__LIT)
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 0b78a6e46..c7eb6e15e 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -334,11 +334,7 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   pipe_state_t *pipe = &_dcd.pipe[0];
   /* configure fifo direction and access unit settings */
   if (ep_addr) { /* IN, 2 bytes */
-#if TU_BYTE_ORDER == TU_BIG_ENDIAN
-    USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | USB_FIFOSEL_BIGEND;
-#else
-    USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16;
-#endif
+    USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
     while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
   } else {       /* OUT, a byte */
     USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8;
@@ -413,11 +409,7 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   USB0.PIPESEL.WORD  = num;
   const unsigned mps = USB0.PIPEMAXP.WORD;
   if (dir) { /* IN */
-#if TU_BYTE_ORDER == TU_BIG_ENDIAN
-    USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | USB_FIFOSEL_BIGEND;
-#else
-    USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16;
-#endif
+    USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
     while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
     int r = fifo_write((void*)&USB0.D0FIFO.WORD, pipe, mps);
     if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
@@ -442,11 +434,7 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
 {
   pipe_state_t *pipe = &_dcd.pipe[num];
   if (tu_edpt_dir(pipe->ep)) { /* IN */
-#if TU_BYTE_ORDER == TU_BIG_ENDIAN
-    select_pipe(num, USB_FIFOSEL_MBW_16 | USB_FIFOSEL_BIGEND);
-#else
-    select_pipe(num, USB_FIFOSEL_MBW_16);
-#endif
+    select_pipe(num, USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0));
     const unsigned mps = USB0.PIPEMAXP.WORD;
     unsigned rem       = pipe->remaining;
     rem               -= TU_MIN(rem, mps);
@@ -527,7 +515,7 @@ static void process_set_address(uint8_t rhport)
 #else
       .bmRequestType = 0,
 #endif
-      .bRequest      = 5,
+      .bRequest      = TUSB_REQ_SET_ADDRESS,
       .wValue        = addr,
       .wIndex        = 0,
       .wLength       = 0,

From a9726aad0c25074b735cc024e73af2d75ce457a8 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Thu, 22 Jul 2021 20:39:55 +0200
Subject: [PATCH 0239/2085] Quick Readme update

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index bbe3e0184..840ad8a7a 100644
--- a/README.md
+++ b/README.md
@@ -32,7 +32,7 @@ The stack supports the following MCUs:
 
 - **Dialog:** DA1469x
 - **Espressif:** ESP32-S2, ESP32-S3
-- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22
+- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAMx7x
 - **NordicSemi:** nRF52833, nRF52840
 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
 - **NXP:**
@@ -53,7 +53,7 @@ The stack supports the following MCUs:
 
 Supports multiple device configurations by dynamically changing usb descriptors. Low power functions such like suspend, resume, and remote wakeup. Following device classes are supported:
 
-- Audio Class 2.0 (UAC2) still work in progress
+- Audio Class 2.0 (UAC2)
 - Bluetooth Host Controller Interface (BTH HCI)
 - Communication Class (CDC)
 - Device Firmware Update (DFU): DFU mode (WIP) and Runtinme 

From ef63037f1ae10680532367c98f30382c173108d6 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 23 Jul 2021 11:21:51 +0200
Subject: [PATCH 0240/2085] Update README.md

Use SAME7x
---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 840ad8a7a..df0c05e67 100644
--- a/README.md
+++ b/README.md
@@ -32,7 +32,7 @@ The stack supports the following MCUs:
 
 - **Dialog:** DA1469x
 - **Espressif:** ESP32-S2, ESP32-S3
-- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAMx7x
+- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAME7x
 - **NordicSemi:** nRF52833, nRF52840
 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
 - **NXP:**

From f01074681a60bf994d71c2ae3929bbe822135149 Mon Sep 17 00:00:00 2001
From: Ben Evans <benny.j.evans92@gmail.com>
Date: Tue, 27 Jul 2021 11:58:20 +1000
Subject: [PATCH 0241/2085] Added BSP for waveshare openh743i.

---
 .../STM32H743IITX_FLASH.ld                    | 175 +++++++
 hw/bsp/waveshare_openh743i/board.c            | 483 ++++++++++++++++++
 hw/bsp/waveshare_openh743i/board.mk           |  64 +++
 .../waveshare_openh743i/stm32h7xx_hal_conf.h  | 483 ++++++++++++++++++
 4 files changed, 1205 insertions(+)
 create mode 100644 hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld
 create mode 100644 hw/bsp/waveshare_openh743i/board.c
 create mode 100644 hw/bsp/waveshare_openh743i/board.mk
 create mode 100644 hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h

diff --git a/hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld b/hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld
new file mode 100644
index 000000000..73d2dedb2
--- /dev/null
+++ b/hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld
@@ -0,0 +1,175 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32H7 series
+**                2048Kbytes FLASH and 192Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x2000 ;  /* required amount of heap  */
+_Min_Stack_Size = 0x2000 ; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 2048K
+  RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
+  RAM_D1 (xrw)   : ORIGIN = 0x24000000, LENGTH = 512K
+  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K
+  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K
+  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/hw/bsp/waveshare_openh743i/board.c b/hw/bsp/waveshare_openh743i/board.c
new file mode 100644
index 000000000..db05af586
--- /dev/null
+++ b/hw/bsp/waveshare_openh743i/board.c
@@ -0,0 +1,483 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019
+ *    Benjamin Evans
+ *    William D. Jones (thor0505@comcast.net),
+ *    Ha Thach (tinyusb.org)
+ *    Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stm32h7xx_hal.h"
+#include "stm32h7xx_hal_tim.h"
+#include "bsp/board.h"
+
+
+/* ** BOARD SETUP **
+ * 
+ * NOTE: This board has bad signal integrity so you may experience some problems.
+ * This setup assumes you have an openh743i-c Core and breakout board. For the HS
+ * examples it also assumes you have a waveshare USB3300 breakout board plugged
+ * into the ULPI PMOD header on the openh743i-c.
+ * 
+ * UART Debugging:
+ * Due to pin conflicts in the HS configuration, this BSP uses USART3 (PD8, PD9).
+ * As such, you won't be able to use the UART to USB converter on board and will
+ * require an external UART to USB converter. You could use the waveshare FT232
+ * USB UART Board (micro) but any 3.3V UART to USB converter will be fine.
+ * 
+ * Fullspeed:
+ * If VBUS sense is enabled, ensure the PA9-VBUS jumper is connected on the core
+ * board. Connect the PB6 jumper for the LED and the Wakeup - PA0 jumper for the
+ * button. Connect the USB cable to the USB connector on the core board.
+ * 
+ * High Speed:
+ * Remove all jumpers from the openh743i-c (especially the USART1 jumpers as the
+ * pins conflict). Connect the PB6 jumper for the LED and the Wakeup - PA0
+ * jumper for the button.
+ * 
+ * The reset pin on the ULPI PMOD port is not connected to the MCU. You'll need
+ * to solder a wire from the RST pin on the USB3300 to a pin of your choosing on
+ * the openh743i-c board (this example assumes you've used PD14 as specified with
+ * the ULPI_RST_PORT and ULPI_RST_PIN defines below).
+ * 
+ * Preferably power the board using the external 5VDC jack. Connect the USB cable
+ * to the USB connector on the ULPI board. Adjust delays in this file as required.
+ * 
+ * If you're having trouble, ask a question on the tinyUSB Github Discussion boards.
+ * 
+ * Have fun!
+ *
+*/
+
+//--------------------------------------------------------------------+
+// BOARD DEFINES
+//--------------------------------------------------------------------+
+
+//LED Pin
+#define LED_PORT GPIOB
+#define LED_PIN GPIO_PIN_6
+#define LED_STATE_ON 1
+
+//ULPI PHY reset pin
+#define ULPI_RST_PORT GPIOD
+#define ULPI_RST_PIN GPIO_PIN_14
+
+// Tamper push-button
+#define BUTTON_PORT GPIOA
+#define BUTTON_PIN GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE 1
+
+// Need external UART to USB converter as USART1 pins conflict with HS ULPI pins
+#define UART_DEV USART3
+#define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE
+#define UART_GPIO_PORT GPIOD
+#define UART_GPIO_AF GPIO_AF7_USART3
+#define UART_TX_PIN GPIO_PIN_8
+#define UART_RX_PIN GPIO_PIN_9
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE 1
+#define OTG_HS_VBUS_SENSE 0
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+UART_HandleTypeDef uartHandle;
+TIM_HandleTypeDef tim2Handle;
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+// Despite being call USB2_OTG
+// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
+void OTG_FS_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+// Despite being call USB2_OTG
+// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
+void OTG_HS_IRQHandler(void)
+{
+  tud_int_handler(1);
+}
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32h7_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  // Supply configuration update enable
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+  // Configure the main internal regulator output voltage
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+  while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY))
+  {
+  }
+  // Macro to configure the PLL clock source
+  __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
+
+  // Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure.
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 2;
+  RCC_OscInitStruct.PLL.PLLN = 240;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_USART3;
+  PeriphClkInitStruct.PLL3.PLL3M = 8;
+  PeriphClkInitStruct.PLL3.PLL3N = 336;
+  PeriphClkInitStruct.PLL3.PLL3P = 2;
+  PeriphClkInitStruct.PLL3.PLL3Q = 7;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+  PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0;
+  PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL3;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  // Initializes the CPU, AHB and APB buses clocks
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  __HAL_RCC_CSI_ENABLE();
+
+  // Enable SYSCFG clock mondatory for I/O Compensation Cell
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  // Enables the I/O Compensation Cell
+  HAL_EnableCompensationCell();
+
+  // Enable voltage detector
+  HAL_PWREx_EnableUSBVoltageDetector();
+
+  return;
+}
+
+
+//--------------------------------------------------------------------+
+// Timer implementation for board delay
+// This should be OS safe and doesn't require the scheduler to be running
+//--------------------------------------------------------------------+
+static void init_timer(void)
+{
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+
+  __HAL_RCC_TIM2_CLK_ENABLE();
+
+  //Assuming timer clock is running at 260Mhz this should configure the timer counter to 1000Hz
+  tim2Handle.Instance = TIM2;
+  tim2Handle.Init.Prescaler = 60000U - 1U;
+  tim2Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
+  tim2Handle.Init.Period = 0xFFFFFFFFU;
+  tim2Handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4;
+  tim2Handle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  HAL_TIM_Base_Init(&tim2Handle);
+
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  HAL_TIM_ConfigClockSource(&tim2Handle, &sClockSourceConfig);
+
+  //Start the timer
+  HAL_TIM_Base_Start(&tim2Handle);
+
+  return;
+}
+
+//Custom board delay implementation using timer ticks
+static inline void timer_board_delay(uint32_t ms)
+{
+  uint32_t startMs = __HAL_TIM_GET_COUNTER(&tim2Handle);
+  while ((__HAL_TIM_GET_COUNTER(&tim2Handle) - startMs) < ms)
+  {
+    asm("nop");
+  }
+}
+
+
+void board_init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  // Init clocks
+  board_stm32h7_clock_init();
+
+  // Init timer for delays
+  init_timer();
+
+  //Disable systick for now
+  //If using an RTOS and the systick interrupt fires without the scheduler running you might have an issue
+  //Because this init code now introduces delays, the systick should be disabled until after board init
+  SysTick->CTRL &= ~1U;
+
+  // Enable GPIO clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOI_CLK_ENABLE();
+
+  // Enable UART Clock
+  UART_CLK_EN();
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  // LED
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  // PHY RST Pin
+  GPIO_InitStruct.Pin = ULPI_RST_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(ULPI_RST_PORT, &GPIO_InitStruct);
+  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 0U);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+  // Uart
+  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  uartHandle.Instance = UART_DEV;
+  uartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
+  uartHandle.Init.WordLength = UART_WORDLENGTH_8B;
+  uartHandle.Init.StopBits = UART_STOPBITS_1;
+  uartHandle.Init.Parity = UART_PARITY_NONE;
+  uartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  uartHandle.Init.Mode = UART_MODE_TX_RX;
+  uartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
+  HAL_UART_Init(&uartHandle);
+
+#if BOARD_DEVICE_RHPORT_NUM == 0
+  //Full Speed
+
+  // Configure DM DP Pins
+  GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  // This for ID line debug
+  GPIO_InitStruct.Pin = GPIO_PIN_10;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  __HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
+
+#if OTG_FS_VBUS_SENSE
+  // Configure VBUS Pin
+  GPIO_InitStruct.Pin = GPIO_PIN_9;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  // Enable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+#else
+  // Disable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+  // B-peripheral session valid override enable
+  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+#endif // vbus sense
+
+#elif BOARD_DEVICE_RHPORT_NUM == 1
+  //High Speed
+
+  /**USB_OTG_HS GPIO Configuration
+    PC0     ------> USB_OTG_HS_ULPI_STP
+    PC2_C   ------> USB_OTG_HS_ULPI_DIR
+    PC3_C   ------> USB_OTG_HS_ULPI_NXT
+    PA3     ------> USB_OTG_HS_ULPI_D0
+    PA5     ------> USB_OTG_HS_ULPI_CK
+    PB1     ------> USB_OTG_HS_ULPI_D2
+    PB10    ------> USB_OTG_HS_ULPI_D3
+    PB11    ------> USB_OTG_HS_ULPI_D4
+    PB12    ------> USB_OTG_HS_ULPI_D5
+    PB13    ------> USB_OTG_HS_ULPI_D6
+    PB5     ------> USB_OTG_HS_ULPI_D7
+  */
+
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_3 | GPIO_PIN_5;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_5;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  // Peripheral clock enable
+  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
+
+#if OTG_HS_VBUS_SENSE
+#error OTG HS VBUS Sense enabled is not implemented
+#else
+  // No VBUS sense
+  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+  // B-peripheral session valid override enable
+  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+#endif
+
+  // Force device mode
+  USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
+  USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+
+  //Reset the PHY - Change the delays as you see fit
+  timer_board_delay(5U); //Delay 5ms
+  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 1U);
+  timer_board_delay(20U); //Delay 20ms
+  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 0U);
+  timer_board_delay(20U); //Delay 20ms
+
+#endif // rhport = 1
+
+  //Disable the timer use for delays
+  HAL_TIM_Base_Stop(&tim2Handle);
+  __HAL_RCC_TIM2_CLK_DISABLE();
+
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+
+  //Enable systick
+  SysTick->CTRL |= ~1U;
+
+  return;
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return (BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN)) ? 1 : 0;
+}
+
+int board_uart_read(uint8_t *buf, int len)
+{
+  (void)buf;
+  (void)len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+  HAL_UART_Transmit(&uartHandle, (uint8_t *)buf, len, 0xffff);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void)
+{
+  asm("bkpt");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+}
\ No newline at end of file
diff --git a/hw/bsp/waveshare_openh743i/board.mk b/hw/bsp/waveshare_openh743i/board.mk
new file mode 100644
index 000000000..721df1bdf
--- /dev/null
+++ b/hw/bsp/waveshare_openh743i/board.mk
@@ -0,0 +1,64 @@
+UF2_FAMILY_ID = 0x6db66082
+ST_FAMILY = h7
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+# Default is HS port
+PORT ?= 1
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
+LD_FILE = $(BOARD_PATH)/STM32H743IITX_FLASH.ld
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m7 \
+  -mfloat-abi=hard \
+  -mfpu=fpv5-d16 \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32H7 \
+	-DBOARD_DEVICE_RHPORT_NUM=$(PORT) \
+  -DSTM32H743xx \
+  -DHSE_VALUE=8000000
+
+ifeq ($(PORT), 1)
+  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+  $(info "PORT1 High Speed")
+else
+  $(info "PORT0 Full Speed")
+endif
+
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
+
+# All source paths should be relative to the top level.
+SRC_C += \
+	src/portable/st/synopsys/dcd_synopsys.c \
+	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim_ex.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM7/r0p1
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h743ii
+
+# flash target using jlink
+flash: flash-jlink
\ No newline at end of file
diff --git a/hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h b/hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h
new file mode 100644
index 000000000..11d29ed6f
--- /dev/null
+++ b/hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h
@@ -0,0 +1,483 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_conf_template.h
+  * @brief   HAL configuration template file. 
+  *          This file should be copied to the application folder and renamed
+  *          to stm32h7xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_CONF_H
+#define __STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+/* #define HAL_CEC_MODULE_ENABLED */
+/* #define HAL_COMP_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
+/* #define HAL_DCMI_MODULE_ENABLED */
+/* #define HAL_DFSDM_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+/* #define HAL_EXTI_MODULE_ENABLED */
+/* #define HAL_FDCAN_MODULE_ENABLED */
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+/* #define HAL_HASH_MODULE_ENABLED */
+/* #define HAL_HCD_MODULE_ENABLED */
+/* #define HAL_HRTIM_MODULE_ENABLED */
+/* #define HAL_HSEM_MODULE_ENABLED */
+/* #define HAL_I2C_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_JPEG_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+/* #define HAL_MDIOS_MODULE_ENABLED */
+/* #define HAL_MDMA_MODULE_ENABLED */
+/* #define HAL_MMC_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_OPAMP_MODULE_ENABLED */
+/* #define HAL_PCD_MODULE_ENABLED */
+#define HAL_PWR_MODULE_ENABLED
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_RAMECC_MODULE_ENABLED */
+#define HAL_RCC_MODULE_ENABLED
+/* #define HAL_RNG_MODULE_ENABLED */
+/* #define HAL_RTC_MODULE_ENABLED */
+/* #define HAL_SAI_MODULE_ENABLED */
+/* #define HAL_SD_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_SPDIFRX_MODULE_ENABLED */
+#define HAL_SPI_MODULE_ENABLED
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SWPMI_MODULE_ENABLED */
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+//#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#error HSE_VALUE is not defined
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal  oscillator (CSI) default value.
+  *        This value is the default CSI value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+#if !defined  (LSI_VALUE)
+  #define LSI_VALUE  ((uint32_t)32000)      /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                              The real value may vary depending on the variations
+                                              in voltage and temperature.*/
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  USE_SD_TRANSCEIVER           1U               /*!< use uSD Transceiver */
+#define  USE_SPI_CRC                  1U               /*!< use CRC in SPI */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0    ((uint8_t)0x02)
+#define ETH_MAC_ADDR1    ((uint8_t)0x00)
+#define ETH_MAC_ADDR2    ((uint8_t)0x00)
+#define ETH_MAC_ADDR3    ((uint8_t)0x00)
+#define ETH_MAC_ADDR4    ((uint8_t)0x00)
+#define ETH_MAC_ADDR5    ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1 */
+
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t *file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

From d058645f977bfa1358fb4aeae2890f4a371fb66c Mon Sep 17 00:00:00 2001
From: Ben Evans <benny.j.evans92@gmail.com>
Date: Tue, 27 Jul 2021 12:02:13 +1000
Subject: [PATCH 0242/2085] Updated docs to add Wavehsare OpenH743I-C to STM32
 boards list.

---
 docs/boards.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/boards.md b/docs/boards.md
index 324500bd1..6be7597ed 100644
--- a/docs/boards.md
+++ b/docs/boards.md
@@ -170,6 +170,7 @@ This code base already had supported for a handful of following boards (sorted a
 - [STM32 H743zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html)
 - [STM32 H743i Evaluation](https://www.st.com/en/evaluation-tools/stm32h743i-eval.html)
 - [STM32 H745i Discovery](https://www.st.com/en/evaluation-tools/stm32h745i-disco.html)
+- [Waveshare OpenH743I-C](https://www.waveshare.com/openh743i-c-standard.htm)
 
 ### TI
 

From 0953be9d7f037dea3e60011d0c0d0bfac743f3e0 Mon Sep 17 00:00:00 2001
From: Ben Evans <benny.j.evans92@gmail.com>
Date: Tue, 27 Jul 2021 12:07:19 +1000
Subject: [PATCH 0243/2085] Small tidy up for waveshare openh743i BSP.

---
 hw/bsp/waveshare_openh743i/board.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/hw/bsp/waveshare_openh743i/board.c b/hw/bsp/waveshare_openh743i/board.c
index db05af586..4468c0668 100644
--- a/hw/bsp/waveshare_openh743i/board.c
+++ b/hw/bsp/waveshare_openh743i/board.c
@@ -100,6 +100,7 @@
 #define OTG_FS_VBUS_SENSE 1
 #define OTG_HS_VBUS_SENSE 0
 
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -107,6 +108,7 @@
 UART_HandleTypeDef uartHandle;
 TIM_HandleTypeDef tim2Handle;
 
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -125,6 +127,7 @@ void OTG_HS_IRQHandler(void)
   tud_int_handler(1);
 }
 
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -230,17 +233,19 @@ static void init_timer(void)
   return;
 }
 
-//Custom board delay implementation using timer ticks
+
+// Custom board delay implementation using timer ticks
 static inline void timer_board_delay(uint32_t ms)
 {
   uint32_t startMs = __HAL_TIM_GET_COUNTER(&tim2Handle);
   while ((__HAL_TIM_GET_COUNTER(&tim2Handle) - startMs) < ms)
   {
-    asm("nop");
+    asm("nop"); //do nothing
   }
 }
 
 
+//Board initialisation
 void board_init(void)
 {
   GPIO_InitTypeDef GPIO_InitStruct;
@@ -418,11 +423,11 @@ void board_init(void)
 
 #endif // rhport = 1
 
-  //Disable the timer use for delays
+  //Disable the timer used for delays
   HAL_TIM_Base_Stop(&tim2Handle);
   __HAL_RCC_TIM2_CLK_DISABLE();
 
-  // 1ms tick timer
+  // Configure systick 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
   //Enable systick
@@ -431,20 +436,22 @@ void board_init(void)
   return;
 }
 
+
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
-
 void board_led_write(bool state)
 {
   HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
+
 uint32_t board_button_read(void)
 {
   return (BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN)) ? 1 : 0;
 }
 
+
 int board_uart_read(uint8_t *buf, int len)
 {
   (void)buf;
@@ -452,12 +459,14 @@ int board_uart_read(uint8_t *buf, int len)
   return 0;
 }
 
+
 int board_uart_write(void const *buf, int len)
 {
   HAL_UART_Transmit(&uartHandle, (uint8_t *)buf, len, 0xffff);
   return len;
 }
 
+
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler(void)
@@ -465,17 +474,20 @@ void SysTick_Handler(void)
   system_ticks++;
 }
 
+
 uint32_t board_millis(void)
 {
   return system_ticks;
 }
 #endif
 
+
 void HardFault_Handler(void)
 {
   asm("bkpt");
 }
 
+
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
 void _init(void)

From 0ba4315ae559f595c0d01ab650ea924d8e9bec69 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 27 Jul 2021 18:08:52 +0200
Subject: [PATCH 0244/2085] Fix IAR warning

---
 src/class/dfu/dfu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index ad87092e0..28abf6e83 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -190,7 +190,7 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
   _dfu_ctx.attrs = func_desc->bAttributes;
 
   // CFG_TUD_DFU_XFER_BUFSIZE has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
-  uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16(&func_desc->wTransferSize) );
+  uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16((uint8_t*) func_desc + offsetof(tusb_desc_dfu_functional_t, wTransferSize)) );
   TU_ASSERT(transfer_size <= CFG_TUD_DFU_XFER_BUFSIZE, drv_len);
 
   return drv_len;
@@ -365,7 +365,7 @@ void tud_dfu_finish_flashing(uint8_t status)
   {
     // failed while flashing, move to dfuError
     _dfu_ctx.state = DFU_ERROR;
-    _dfu_ctx.status = status;
+    _dfu_ctx.status = (dfu_status_t)status;
   }
 }
 

From 1c2e353193d31ee3869a2417e17be89f0a6aa41c Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 29 May 2021 19:09:13 +0900
Subject: [PATCH 0245/2085] Refactor and clean up

---
 src/portable/renesas/usba/dcd_usba.c | 286 ++++++++++++++-------------
 1 file changed, 150 insertions(+), 136 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index c7eb6e15e..46513590e 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -122,7 +122,7 @@ typedef union {
 
 typedef struct TU_ATTR_PACKED
 {
-  uintptr_t addr;      /* the start address of a transfer data buffer */
+  void      *buf;      /* the start address of a transfer data buffer */
   uint16_t  length;    /* the number of bytes in the buffer */
   uint16_t  remaining; /* the number of bytes remaining in the buffer */
   struct {
@@ -236,34 +236,27 @@ static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
   return ctr;
 }
 
-static unsigned wait_for_pipe_ready(void)
+static unsigned edpt0_max_packet_size(void)
 {
-  unsigned ctr;
-  do {
-    ctr = USB0.D0FIFOCTR.WORD;
-  } while (!(ctr & USB_FIFOCTR_FRDY));
-  return ctr;
+  return USB0.DCPMAXP.BIT.MXPS;
 }
 
-static unsigned select_pipe(unsigned num, unsigned attr)
+static unsigned edpt_max_packet_size(unsigned num)
+{
+  USB0.PIPESEL.WORD = num;
+  return USB0.PIPEMAXP.WORD;
+}
+
+static inline void pipe_wait_for_ready(unsigned num)
 {
-  USB0.PIPESEL.WORD  = num;
-  USB0.D0FIFOSEL.WORD = num | attr;
   while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
-  return wait_for_pipe_ready();
+  while (!USB0.D0FIFOCTR.BIT.FRDY) ;
 }
 
-/* 1 less than mps bytes were written to FIFO
- * 2 no bytes were written to FIFO
- * 0 mps bytes were written to FIFO */
-static int fifo_write(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
+static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 {
-  unsigned rem  = pipe->remaining;
-  if (!rem) return 2;
-  unsigned len  = TU_MIN(rem, mps);
-
   hw_fifo_t *reg = (hw_fifo_t*)fifo;
-  uintptr_t addr = pipe->addr + pipe->length - rem;
+  uintptr_t addr = (uintptr_t)buf;
   while (len >= 2) {
     reg->u16 = *(const uint16_t *)addr;
     addr += 2;
@@ -273,31 +266,107 @@ static int fifo_write(volatile void *fifo, pipe_state_t* pipe, unsigned mps)
     reg->u8 = *(const uint8_t *)addr;
     ++addr;
   }
-  if (rem < mps) return 1;
-  return 0;
 }
 
-/* 1 less than mps bytes were read from FIFO
- * 2 the end of the buffer reached.
- * 0 mps bytes were read from FIFO */
-static int fifo_read(volatile void *fifo, pipe_state_t* pipe, unsigned mps, size_t len)
+static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
 {
-  unsigned rem  = pipe->remaining;
-  if (!rem) return 2;
-  if (rem < len) len = rem;
-  pipe->remaining = rem - len;
-
+  uint8_t *p   = (uint8_t*)buf;
   uint8_t *reg = (uint8_t*)fifo;  /* byte access is always at base register address */
-  uintptr_t addr = pipe->addr;
-  unsigned  loop = len;
-  while (loop--) {
-    *(uint8_t *)addr = *reg;
-    ++addr;
+  while (len--) *p++ = *reg;
+}
+
+static bool pipe0_xfer_in(void)
+{
+  pipe_state_t *pipe = &_dcd.pipe[0];
+  const unsigned rem = pipe->remaining;
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
   }
-  pipe->addr = addr;
-  if (rem < mps)  return 1;
-  if (rem == len) return 2;
-  return 0;
+  const unsigned mps = edpt0_max_packet_size();
+  const unsigned len = TU_MIN(mps, rem);
+  void          *buf = pipe->buf;
+  if (len) {
+    pipe_write_packet(buf, &USB0.CFIFO.WORD, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+  pipe->remaining = rem - len;
+  return false;
+}
+
+static bool pipe0_xfer_out(void)
+{
+  pipe_state_t *pipe = &_dcd.pipe[0];
+  const unsigned rem = pipe->remaining;
+
+  const unsigned mps = edpt0_max_packet_size();
+  const unsigned vld = USB0.CFIFOCTR.BIT.DTLN;
+  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
+  void          *buf = pipe->buf;
+  if (len) {
+    pipe_read_packet(buf, &USB0.CFIFO.WORD, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
+  pipe->remaining = rem - len;
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return true;
+  }
+  return false;
+}
+
+static bool pipe_xfer_in(unsigned num)
+{
+  pipe_state_t  *pipe = &_dcd.pipe[num];
+  const unsigned rem  = pipe->remaining;
+
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+
+  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16;
+  const unsigned mps  = edpt_max_packet_size(num);
+  pipe_wait_for_ready(num);
+  const unsigned len  = TU_MIN(rem, mps);
+  void          *buf  = pipe->buf;
+  if (len) {
+    pipe_write_packet(buf, &USB0.D0FIFO.WORD, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+  USB0.D0FIFOSEL.WORD = 0;
+  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  pipe->remaining = rem - len;
+  return false;
+}
+
+static bool pipe_xfer_out(unsigned num)
+{
+  pipe_state_t  *pipe = &_dcd.pipe[num];
+  const unsigned rem  = pipe->remaining;
+
+  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
+  const unsigned mps  = edpt_max_packet_size(num);
+  pipe_wait_for_ready(num);
+  const unsigned vld  = USB0.D0FIFOCTR.BIT.DTLN;
+  const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
+  void          *buf  = pipe->buf;
+  if (len) {
+    pipe_read_packet(buf, &USB0.D0FIFO.WORD, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
+  USB0.D0FIFOSEL.WORD = 0;
+  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  pipe->remaining     = rem - len;
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return NULL != buf;
+  }
+  return false;
 }
 
 static void process_setup_packet(uint8_t rhport)
@@ -327,11 +396,10 @@ static void process_status_completion(uint8_t rhport)
   dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true);
 }
 
-static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+static bool process_pipe0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
   (void)rhport;
 
-  pipe_state_t *pipe = &_dcd.pipe[0];
   /* configure fifo direction and access unit settings */
   if (ep_addr) { /* IN, 2 bytes */
     USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
@@ -340,57 +408,25 @@ static bool process_edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
     USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8;
     while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
   }
+
+  pipe_state_t *pipe = &_dcd.pipe[0];
+  pipe->length    = total_bytes;
+  pipe->remaining = total_bytes;
   if (total_bytes) {
-    pipe->addr      = (uintptr_t)buffer;
-    pipe->length    = total_bytes;
-    pipe->remaining = total_bytes;
+    pipe->buf     = buffer;
     if (ep_addr) { /* IN */
       TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
-      if (fifo_write((void*)&USB0.CFIFO.WORD, pipe, 64)) {
-        USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
-      }
+      pipe0_xfer_in();
     }
     USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
   } else {
     /* ZLP */
-    pipe->addr       = 0;
-    pipe->length     = 0;
-    pipe->remaining  = 0;
+    pipe->buf        = NULL;
     USB0.DCPCTR.WORD = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
   }
   return true;
 }
 
-static void process_edpt0_bemp(uint8_t rhport)
-{
-  pipe_state_t *pipe = &_dcd.pipe[0];
-  const unsigned rem = pipe->remaining;
-  if (rem > 64) {
-    pipe->remaining = rem - 64;
-    int r = fifo_write((void*)&USB0.CFIFO.WORD, &_dcd.pipe[0], 64);
-    if (r) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
-    return;
-  }
-  pipe->addr      = 0;
-  pipe->remaining = 0;
-  dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
-                          pipe->length, XFER_RESULT_SUCCESS, true);
-}
-
-static void process_edpt0_brdy(uint8_t rhport)
-{
-  size_t len = USB0.CFIFOCTR.BIT.DTLN;
-  int cplt = fifo_read((void*)&USB0.CFIFO.WORD, &_dcd.pipe[0], 64, len);
-  if (cplt || (len < 64)) {
-    if (2 != cplt) {
-      USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
-    }
-    dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
-                            _dcd.pipe[0].length - _dcd.pipe[0].remaining,
-                            XFER_RESULT_SUCCESS, true);
-  }
-}
-
 static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
   (void)rhport;
@@ -401,23 +437,16 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
 
   TU_ASSERT(num);
 
-  pipe_state_t *pipe = &_dcd.pipe[num];
-  pipe->addr      = (uintptr_t)buffer;
+  pipe_state_t *pipe  = &_dcd.pipe[num];
+  pipe->buf       = buffer;
   pipe->length    = total_bytes;
   pipe->remaining = total_bytes;
-
-  USB0.PIPESEL.WORD  = num;
-  const unsigned mps = USB0.PIPEMAXP.WORD;
   if (dir) { /* IN */
-    USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
-    while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
-    int r = fifo_write((void*)&USB0.D0FIFO.WORD, pipe, mps);
-    if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-    USB0.D0FIFOSEL.WORD = 0;
-    while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+    pipe_xfer_in(num);
   } else {
     volatile reg_pipetre_t *pt = get_pipetre(num);
     if (pt) {
+      const unsigned     mps = edpt_max_packet_size(num);
       volatile uint16_t *ctr = get_pipectr(num);
       if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
       pt->TRE   = TU_BIT(8);
@@ -430,47 +459,36 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   return true;
 }
 
+static void process_pipe0_bemp(uint8_t rhport)
+{
+  bool completed = pipe0_xfer_in();
+  if (completed) {
+    pipe_state_t *pipe = &_dcd.pipe[0];
+    dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
+			    pipe->length, XFER_RESULT_SUCCESS, true);
+  }
+}
+
 static void process_pipe_brdy(uint8_t rhport, unsigned num)
 {
-  pipe_state_t *pipe = &_dcd.pipe[num];
-  if (tu_edpt_dir(pipe->ep)) { /* IN */
-    select_pipe(num, USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0));
-    const unsigned mps = USB0.PIPEMAXP.WORD;
-    unsigned rem       = pipe->remaining;
-    rem               -= TU_MIN(rem, mps);
-    pipe->remaining    = rem;
-    if (rem) {
-      int r = 0;
-      r = fifo_write((void*)&USB0.D0FIFO.WORD, pipe, mps);
-      if (r) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-      USB0.D0FIFOSEL.WORD = 0;
-      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-      return;
-    }
-    USB0.D0FIFOSEL.WORD = 0;
-    while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-    pipe->addr      = 0;
-    pipe->remaining = 0;
-    dcd_event_xfer_complete(rhport, pipe->ep, pipe->length,
-                            XFER_RESULT_SUCCESS, true);
+  pipe_state_t  *pipe = &_dcd.pipe[num];
+  const unsigned dir  = tu_edpt_dir(pipe->ep);
+  bool completed;
+
+  if (dir) { /* IN */
+    completed = pipe_xfer_in(num);
   } else {
-    const unsigned ctr = select_pipe(num, USB_FIFOSEL_MBW_8);
-    const unsigned len = ctr & USB_FIFOCTR_DTLN;
-    const unsigned mps = USB0.PIPEMAXP.WORD;
-    int cplt = fifo_read((void*)&USB0.D0FIFO.WORD, pipe, mps, len);
-    if (cplt || (len < mps)) {
-      if (2 != cplt) {
-        USB0.D0FIFO.WORD = USB_FIFOCTR_BCLR;
-      }
-      USB0.D0FIFOSEL.WORD = 0;
-      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-      dcd_event_xfer_complete(rhport, pipe->ep,
-                              pipe->length - pipe->remaining,
-                              XFER_RESULT_SUCCESS, true);
-      return;
+    if (num) {
+      completed = pipe_xfer_out(num);
+    } else {
+      completed = pipe0_xfer_out();
     }
-    USB0.D0FIFOSEL.WORD = 0;
-    while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  }
+  if (completed) {
+    dcd_event_xfer_complete(rhport, pipe->ep,
+			    pipe->length - pipe->remaining,
+			    XFER_RESULT_SUCCESS, true);
+    //  TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining);
   }
 }
 
@@ -649,7 +667,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   if (dir || (xfer != TUSB_XFER_BULK)) {
     *ctr = USB_PIPECTR_PID_BUF;
   }
-  //  TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD);
+  // TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD);
   dcd_int_enable(rhport);
 
   return true;
@@ -677,7 +695,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
   const unsigned epn = tu_edpt_number(ep_addr);
   dcd_int_disable(rhport);
   if (0 == epn) {
-    r = process_edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
+    r = process_pipe0_xfer(rhport, ep_addr, buffer, total_bytes);
   } else {
     r = process_pipe_xfer(rhport, ep_addr, buffer, total_bytes);
   }
@@ -779,7 +797,7 @@ void dcd_int_handler(uint8_t rhport)
     const unsigned s = USB0.BEMPSTS.WORD;
     USB0.BEMPSTS.WORD = 0;
     if (s & 1) {
-      process_edpt0_bemp(rhport);
+      process_pipe0_bemp(rhport);
     }
   }
   if (is0 & USB_IS0_BRDY) {
@@ -787,10 +805,6 @@ void dcd_int_handler(uint8_t rhport)
     unsigned s       = USB0.BRDYSTS.WORD & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
     USB0.BRDYSTS.WORD = ~s;
-    if (s & 1) {
-      process_edpt0_brdy(rhport);
-      s &= ~1;
-    }
     while (s) {
 #if defined(__CCRX__)
       static const int Mod37BitPosition[] = {

From 3f49380b378601a852ed45f2b38dd48c66b0f69d Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 30 May 2021 22:49:53 +0900
Subject: [PATCH 0246/2085] added support for dcd_edpt_xfer_fifo

---
 src/portable/renesas/usba/dcd_usba.c | 86 ++++++++++++++++++++--------
 1 file changed, 62 insertions(+), 24 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 46513590e..ada184541 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -127,6 +127,7 @@ typedef struct TU_ATTR_PACKED
   uint16_t  remaining; /* the number of bytes remaining in the buffer */
   struct {
     uint32_t ep  : 8;  /* an assigned endpoint address */
+    uint32_t ff  : 1;  /* `buf` is TU_FUFO or POD */
     uint32_t     : 0;
   };
 } pipe_state_t;
@@ -287,8 +288,12 @@ static bool pipe0_xfer_in(void)
   const unsigned len = TU_MIN(mps, rem);
   void          *buf = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, &USB0.CFIFO.WORD, len);
-    pipe->buf = (uint8_t*)buf + len;
+    if (pipe->ff) {
+      tu_fifo_read_n_const_addr_full_words(buf, (void*)&USB0.CFIFO.WORD, len);
+    } else {
+      pipe_write_packet(buf, &USB0.CFIFO.WORD, len);
+      pipe->buf = (uint8_t*)buf + len;
+    }
   }
   if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
   pipe->remaining = rem - len;
@@ -305,8 +310,12 @@ static bool pipe0_xfer_out(void)
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
-    pipe_read_packet(buf, &USB0.CFIFO.WORD, len);
-    pipe->buf = (uint8_t*)buf + len;
+    if (pipe->ff) {
+      tu_fifo_write_n_const_addr_full_words(buf, (void*)&USB0.CFIFO.WORD, len);
+    } else {
+      pipe_read_packet(buf, &USB0.CFIFO.WORD, len);
+      pipe->buf = (uint8_t*)buf + len;
+    }
   }
   if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
   pipe->remaining = rem - len;
@@ -333,8 +342,12 @@ static bool pipe_xfer_in(unsigned num)
   const unsigned len  = TU_MIN(rem, mps);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, &USB0.D0FIFO.WORD, len);
-    pipe->buf = (uint8_t*)buf + len;
+    if (pipe->ff) {
+      tu_fifo_read_n_const_addr_full_words(buf, (void*)&USB0.D0FIFO.WORD, len);
+    } else {
+      pipe_write_packet(buf, &USB0.D0FIFO.WORD, len);
+      pipe->buf = (uint8_t*)buf + len;
+    }
   }
   if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
   USB0.D0FIFOSEL.WORD = 0;
@@ -355,8 +368,12 @@ static bool pipe_xfer_out(unsigned num)
   const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_read_packet(buf, &USB0.D0FIFO.WORD, len);
-    pipe->buf = (uint8_t*)buf + len;
+    if (pipe->ff) {
+      tu_fifo_write_n_const_addr_full_words(buf, (void*)&USB0.D0FIFO.WORD, len);
+    } else {
+      pipe_read_packet(buf, &USB0.D0FIFO.WORD, len);
+      pipe->buf = (uint8_t*)buf + len;
+    }
   }
   if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
   USB0.D0FIFOSEL.WORD = 0;
@@ -396,10 +413,8 @@ static void process_status_completion(uint8_t rhport)
   dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true);
 }
 
-static bool process_pipe0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
 {
-  (void)rhport;
-
   /* configure fifo direction and access unit settings */
   if (ep_addr) { /* IN, 2 bytes */
     USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
@@ -410,6 +425,7 @@ static bool process_pipe0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   }
 
   pipe_state_t *pipe = &_dcd.pipe[0];
+  pipe->ff        = buffer_type;
   pipe->length    = total_bytes;
   pipe->remaining = total_bytes;
   if (total_bytes) {
@@ -427,10 +443,8 @@ static bool process_pipe0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   return true;
 }
 
-static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
 {
-  (void)rhport;
-
   const unsigned epn = tu_edpt_number(ep_addr);
   const unsigned dir = tu_edpt_dir(ep_addr);
   const unsigned num = _dcd.ep[dir][epn];
@@ -438,11 +452,19 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   TU_ASSERT(num);
 
   pipe_state_t *pipe  = &_dcd.pipe[num];
+  pipe->ff        = buffer_type;
   pipe->buf       = buffer;
   pipe->length    = total_bytes;
   pipe->remaining = total_bytes;
   if (dir) { /* IN */
-    pipe_xfer_in(num);
+    if (total_bytes) {
+      pipe_xfer_in(num);
+    } else { /* ZLP */
+      USB0.D0FIFOSEL.WORD = num;
+      pipe_wait_for_ready(num);
+      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+      USB0.D0FIFOSEL.WORD = 0;
+    }
   } else {
     volatile reg_pipetre_t *pt = get_pipetre(num);
     if (pt) {
@@ -459,13 +481,23 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer,
   return true;
 }
 
+static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
+{
+  const unsigned epn = tu_edpt_number(ep_addr);
+  if (0 == epn) {
+    return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes);
+  } else {
+    return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes);
+  }
+}
+
 static void process_pipe0_bemp(uint8_t rhport)
 {
   bool completed = pipe0_xfer_in();
   if (completed) {
     pipe_state_t *pipe = &_dcd.pipe[0];
     dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
-			    pipe->length, XFER_RESULT_SUCCESS, true);
+                            pipe->length, XFER_RESULT_SUCCESS, true);
   }
 }
 
@@ -486,8 +518,8 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
   }
   if (completed) {
     dcd_event_xfer_complete(rhport, pipe->ep,
-			    pipe->length - pipe->remaining,
-			    XFER_RESULT_SUCCESS, true);
+                            pipe->length - pipe->remaining,
+                            XFER_RESULT_SUCCESS, true);
     //  TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining);
   }
 }
@@ -692,13 +724,19 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
   bool r;
-  const unsigned epn = tu_edpt_number(ep_addr);
   dcd_int_disable(rhport);
-  if (0 == epn) {
-    r = process_pipe0_xfer(rhport, ep_addr, buffer, total_bytes);
-  } else {
-    r = process_pipe_xfer(rhport, ep_addr, buffer, total_bytes);
-  }
+  r = process_edpt_xfer(0, ep_addr, buffer, total_bytes);
+  dcd_int_enable(rhport);
+  return r;
+}
+
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
+  TU_ASSERT(ff->item_size == 1);
+  bool r;
+  dcd_int_disable(rhport);
+  r = process_edpt_xfer(1, ep_addr, ff, total_bytes);
   dcd_int_enable(rhport);
   return r;
 }

From e7c9cf4aea1515306765eb2b43dbe7002b50ed62 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 2 Jun 2021 22:18:15 +0900
Subject: [PATCH 0247/2085] Change the accessing method of TU_FIFO from
 read/write_n_const_addr_full_words to get_write/read_info and
 advance_write/read_pointer pairs.

---
 src/portable/renesas/usba/dcd_usba.c | 34 ++++++++++++++++++++++++----
 1 file changed, 29 insertions(+), 5 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index ada184541..09622d894 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -276,6 +276,30 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
   while (len--) *p++ = *reg;
 }
 
+static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir)
+{
+  static const struct {
+    void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
+    void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n);
+    void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len);
+  } ops[] = {
+    /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet},
+    /* IN  */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet},
+  };
+  tu_fifo_buffer_info_t info;
+  ops[dir].tu_fifo_get_info(f, &info);
+  unsigned total_len = len;
+  len = TU_MIN(total_len, info.len_lin);
+  ops[dir].pipe_read_write(info.ptr_lin, fifo, len);
+  unsigned rem = total_len - len;
+  if (rem) {
+    len = TU_MIN(rem, info.len_wrap);
+    ops[dir].pipe_read_write(info.ptr_wrap, fifo, len);
+    rem -= len;
+  }
+  ops[dir].tu_fifo_advance(f, total_len - rem);
+}
+
 static bool pipe0_xfer_in(void)
 {
   pipe_state_t *pipe = &_dcd.pipe[0];
@@ -289,7 +313,7 @@ static bool pipe0_xfer_in(void)
   void          *buf = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      tu_fifo_read_n_const_addr_full_words(buf, (void*)&USB0.CFIFO.WORD, len);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, &USB0.CFIFO.WORD, len, TUSB_DIR_IN);
     } else {
       pipe_write_packet(buf, &USB0.CFIFO.WORD, len);
       pipe->buf = (uint8_t*)buf + len;
@@ -311,7 +335,7 @@ static bool pipe0_xfer_out(void)
   void          *buf = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      tu_fifo_write_n_const_addr_full_words(buf, (void*)&USB0.CFIFO.WORD, len);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, &USB0.CFIFO.WORD, len, TUSB_DIR_OUT);
     } else {
       pipe_read_packet(buf, &USB0.CFIFO.WORD, len);
       pipe->buf = (uint8_t*)buf + len;
@@ -343,7 +367,7 @@ static bool pipe_xfer_in(unsigned num)
   void          *buf  = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      tu_fifo_read_n_const_addr_full_words(buf, (void*)&USB0.D0FIFO.WORD, len);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, &USB0.D0FIFO.WORD, len, TUSB_DIR_IN);
     } else {
       pipe_write_packet(buf, &USB0.D0FIFO.WORD, len);
       pipe->buf = (uint8_t*)buf + len;
@@ -369,7 +393,7 @@ static bool pipe_xfer_out(unsigned num)
   void          *buf  = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      tu_fifo_write_n_const_addr_full_words(buf, (void*)&USB0.D0FIFO.WORD, len);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, &USB0.D0FIFO.WORD, len, TUSB_DIR_OUT);
     } else {
       pipe_read_packet(buf, &USB0.D0FIFO.WORD, len);
       pipe->buf = (uint8_t*)buf + len;
@@ -477,7 +501,7 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
       *ctr = USB_PIPECTR_PID_BUF;
     }
   }
-  //  TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
+  //  TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
   return true;
 }
 

From 6b9f8e454eaf5ac3a9474d0a09f019e700532093 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Fri, 4 Jun 2021 01:22:57 +0900
Subject: [PATCH 0248/2085] add a condition regarding OPT_MCU_RX63N

---
 src/class/audio/audio_device.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 404d28817..86a00ea73 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -86,7 +86,8 @@
     CFG_TUSB_MCU == OPT_MCU_STM32F4                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32F7                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32H7                               || \
-    (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS))
+    (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) || \
+    CFG_TUSB_MCU == OPT_MCU_RX63X
 #define  USE_LINEAR_BUFFER     0
 #else
 #define  USE_LINEAR_BUFFER     1

From 3c3563288d643fc70ccff80c02a72d330cd65678 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Tue, 29 Jun 2021 20:41:16 +0900
Subject: [PATCH 0249/2085] add RX65N

---
 src/class/audio/audio_device.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 86a00ea73..092e5e125 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -87,7 +87,8 @@
     CFG_TUSB_MCU == OPT_MCU_STM32F7                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32H7                               || \
     (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) || \
-    CFG_TUSB_MCU == OPT_MCU_RX63X
+    CFG_TUSB_MCU == OPT_MCU_RX63X                                 || \
+    CFG_TUSB_MCU == OPT_MCU_RX65X
 #define  USE_LINEAR_BUFFER     0
 #else
 #define  USE_LINEAR_BUFFER     1

From ff20e4d6bcffc5d66666050c57719031fa2820e8 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 29 Jul 2021 20:45:51 +0900
Subject: [PATCH 0250/2085] add the entry for RX72N

---
 src/class/audio/audio_device.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 092e5e125..de0bddcd3 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -88,7 +88,8 @@
     CFG_TUSB_MCU == OPT_MCU_STM32H7                               || \
     (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) || \
     CFG_TUSB_MCU == OPT_MCU_RX63X                                 || \
-    CFG_TUSB_MCU == OPT_MCU_RX65X
+    CFG_TUSB_MCU == OPT_MCU_RX65X                                 || \
+    CFG_TUSB_MCU == OPT_MCU_RX72N
 #define  USE_LINEAR_BUFFER     0
 #else
 #define  USE_LINEAR_BUFFER     1

From 8b5625bf4e846bd4e286c663912fdfb40bc234d8 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 30 Jul 2021 12:03:35 +0200
Subject: [PATCH 0251/2085] Move clock enable to BSP.

---
 hw/bsp/same70_xplained/same70_xplained.c | 56 ++++++++++--------------
 1 file changed, 23 insertions(+), 33 deletions(-)

diff --git a/hw/bsp/same70_xplained/same70_xplained.c b/hw/bsp/same70_xplained/same70_xplained.c
index ac682a89a..e6e7db0f3 100644
--- a/hw/bsp/same70_xplained/same70_xplained.c
+++ b/hw/bsp/same70_xplained/same70_xplained.c
@@ -59,51 +59,41 @@ static void tx_cb_EDBG_COM(const struct usart_async_descriptor *const io_descr)
 //------------- IMPLEMENTATION -------------//
 void board_init(void)
 {
-	init_mcu();
+  init_mcu();
 
-	/* Disable Watchdog */
-	hri_wdt_set_MR_WDDIS_bit(WDT);
+  /* Disable Watchdog */
+  hri_wdt_set_MR_WDDIS_bit(WDT);
 
-	// LED
-	_pmc_enable_periph_clock(ID_PIOC);
-	gpio_set_pin_level(LED_PIN, false);
-	gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
-	gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
+  // LED
+  _pmc_enable_periph_clock(ID_PIOC);
+  gpio_set_pin_level(LED_PIN, false);
+  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
 
-	// Button
-	_pmc_enable_periph_clock(ID_PIOA);
-	gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-	gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
-	gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
+  // Button
+  _pmc_enable_periph_clock(ID_PIOA);
+  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
+  gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
 
-	// Uart via EDBG Com
-	_pmc_enable_periph_clock(ID_USART1);
-	gpio_set_pin_function(UART_RX_PIN, MUX_PA21A_USART1_RXD1);
-	gpio_set_pin_function(UART_TX_PIN, MUX_PB4D_USART1_TXD1);
+  // Uart via EDBG Com
+  _pmc_enable_periph_clock(ID_USART1);
+  gpio_set_pin_function(UART_RX_PIN, MUX_PA21A_USART1_RXD1);
+  gpio_set_pin_function(UART_TX_PIN, MUX_PB4D_USART1_TXD1);
 
-	usart_async_init(&edbg_com, USART1, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async());
-	usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
-	usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_cb_EDBG_COM);
-//	usart_async_register_callback(&EDBG_COM, USART_ASYNC_RXC_CB, rx_cb_EDBG_COM);
-	usart_async_enable(&edbg_com);
+  usart_async_init(&edbg_com, USART1, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async());
+  usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
+  usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_cb_EDBG_COM);
+  usart_async_enable(&edbg_com);
 
 #if CFG_TUSB_OS  == OPT_OS_NONE
   // 1ms tick timer (samd SystemCoreClock may not correct)
   SysTick_Config(CONF_CPU_FREQUENCY / 1000);
 #endif
 
-#if 0
-  // USB Pin, Clock init
+  // Enable USB clock
+  _pmc_enable_periph_clock(ID_USBHS);
 
-  /* Clear SYSIO 10 & 11 for USB DM & DP */
-  hri_matrix_clear_CCFG_SYSIO_reg(MATRIX, CCFG_SYSIO_SYSIO10 | CCFG_SYSIO_SYSIO11);
-
-  // Enable clock
-  _pmc_enable_periph_clock(ID_UDP);
-
-	/* USB Device mode & Transceiver active */
-	hri_matrix_write_CCFG_USBMR_reg(MATRIX, CCFG_USBMR_USBMODE);
-#endif
 }
 
 //--------------------------------------------------------------------+

From c4cd36980ded509bd45c26ab35410d2234ac2734 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 30 Jul 2021 12:06:02 +0200
Subject: [PATCH 0252/2085] Add cache clean/invalidate.

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 28 ++++++++++++++++++----
 1 file changed, 24 insertions(+), 4 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index e35cf80a6..465c5953b 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -94,6 +94,18 @@ static const tusb_desc_endpoint_t ep0_desc =
   .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
 };
 
+TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, int32_t size)
+{
+  if (SCB->CCR & SCB_CCR_DC_Msk)
+  {
+    SCB_CleanInvalidateDCache_by_Addr(addr, size);
+  }
+  else
+  {
+    __DSB();
+    __ISB();
+  }
+}
 //------------------------------------------------------------------
 // Device API
 //------------------------------------------------------------------
@@ -141,8 +153,6 @@ void dcd_connect(uint8_t rhport)
 {
   (void) rhport;
   dcd_int_disable(rhport);
-  // Enable USB clock
-  PMC->PMC_PCER1 = 1 << (ID_USBHS - 32);
   // Enable the USB controller in device mode
   USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE;
   while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
@@ -602,6 +612,9 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   
   if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {
+    // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
+    // address to 32-byte boundaries.
+    CleanInValidateCache((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31);
     uint32_t udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
     if (dir == TUSB_DIR_OUT)
     {
@@ -679,16 +692,23 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
       udd_dma_ctrl_wrap |= USBHS_DEVDMACONTROL_END_B_EN;
     }
 
+    // Clean invalidate cache of linear part
+    CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31);
+    
     USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)info.ptr_lin;
     if (info.len_wrap)
     {
+      // Clean invalidate cache of wrapped part
+      CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_wrap, 4), info.len_wrap + 31);
+      
       dma_desc[epnum - 1].next_desc = 0;
       dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
       dma_desc[epnum - 1].chnl_ctrl =
         udd_dma_ctrl_wrap | USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_wrap);
+      // Clean cache of wrapped DMA descriptor
+      CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t));
+      
       udd_dma_ctrl_lin |= USBHS_DEVDMASTATUS_DESC_LDST;
-      __DSB();
-      __ISB();
       USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
     } else {
       udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_END_BUFFIT;

From bf99adc3c9f0306e263677e17bfaf0dee356f450 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Mon, 26 Jul 2021 19:18:12 +0100
Subject: [PATCH 0253/2085] docs: setup sphinx docs

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/boards.md          | 216 -------------------
 docs/changelog.md       | 468 ----------------------------------------
 docs/concurrency.md     |  36 ----
 docs/conf.py            |  42 ++++
 docs/getting_started.md | 137 ------------
 docs/index.rst          |  20 ++
 docs/porting.md         | 191 ----------------
 docs/requirements.txt   |   4 +
 8 files changed, 66 insertions(+), 1048 deletions(-)
 delete mode 100644 docs/boards.md
 delete mode 100644 docs/changelog.md
 delete mode 100644 docs/concurrency.md
 create mode 100644 docs/conf.py
 delete mode 100644 docs/getting_started.md
 create mode 100644 docs/index.rst
 delete mode 100644 docs/porting.md
 create mode 100644 docs/requirements.txt

diff --git a/docs/boards.md b/docs/boards.md
deleted file mode 100644
index 6be7597ed..000000000
--- a/docs/boards.md
+++ /dev/null
@@ -1,216 +0,0 @@
-# Boards
-
-The board support code is only used for self-contained examples and testing. It is not used when TinyUSB is part of a larger project. It is responsible for getting the MCU started and the USB peripheral clocked with minimal of on-board devices
-- One LED : for status
-- One Button : to get input from user
-- One UART : optional for device, but required for host examples
-
-## Supported Boards
-
-This code base already had supported for a handful of following boards (sorted alphabetically)
-
-### Dialog DA146xx
-
-- [DA14695 Development Kit – USB](https://www.dialog-semiconductor.com/products/da14695-development-kit-usb)
-- [DA1469x Development Kit – Pro](https://www.dialog-semiconductor.com/products/da14695-development-kit-pro)
-
-### Espressif ESP32-S2
-
-- Adafruit Feather ESP32-S2
-- [Adafruit Magtag 2.9" E-Ink WiFi Display](https://www.adafruit.com/product/4800)
-- [Adafruit Metro ESP32-S2](https://www.adafruit.com/product/4775)
-- [ESP32-S2-Kaluga-1](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit.html)
-- [ESP32-S2-Saola-1](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html)
-
-### MicroChip SAMD11 & SAMD21
-
-- [Adafruit Circuit Playground Express](https://www.adafruit.com/product/3333)
-- [Adafruit Feather M0 Express](https://www.adafruit.com/product/3403)
-- [Adafruit ItsyBitsy M0 Express](https://www.adafruit.com/product/3727)
-- [Adafruit Metro M0 Express](https://www.adafruit.com/product/3505)
-- [Great Scott Gadgets LUNA](https://greatscottgadgets.com/luna/)
-- [Microchip SAMD11 Xplained Pro](https://www.microchip.com/developmenttools/ProductDetails/atsamd11-xpro)
-- [Microchip SAMD21 Xplained Pro](https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMD21-XPRO)
-- [Seeeduino Xiao](https://www.seeedstudio.com/Seeeduino-XIAO-Arduino-Microcontroller-SAMD21-Cortex-M0+-p-4426.html)
-
-### MicroChip SAMD51 & SAME54
-
-- [Adafruit Feather M4 Express](https://www.adafruit.com/product/3857)
-- [Adafruit ItsyBitsy M4 Express](https://www.adafruit.com/product/3800)
-- [Adafruit PyBadge](https://www.adafruit.com/product/4200)
-- [Adafruit PyPortal](https://www.adafruit.com/product/4116)
-- [Adafruit Metro M4 Express](https://www.adafruit.com/product/3382)
-- [D5035-01](https://github.com/RudolphRiedel/USB_CAN-FD)
-- [Microchip SAME54 Xplained Pro](https://www.microchip.com/developmenttools/productdetails/atsame54-xpro)
-
-### MicroChip SAMG
-
-- [Microchip SAMG55 Xplained Pro](https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMG55-XPRO)
-
-### MicroChip SAML2x
-
-- [SAML21 Xplaind Pro](https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAML21-XPRO-B)
-- [SAML22 Feather](https://github.com/joeycastillo/Feather-Projects/tree/main/SAML22%20Feather)
-- [Sensor Watch](https://github.com/joeycastillo/Sensor-Watch)
-
-### Nordic nRF5x
-
-- [Adafruit Circuit Playground Bluefruit](https://www.adafruit.com/product/4333)
-- [Adafruit CLUE](https://www.adafruit.com/product/4500)
-- [Adafruit Feather nRF52840 Express](https://www.adafruit.com/product/4062)
-- [Adafruit Feather nRF52840 Sense](https://www.adafruit.com/product/4516)
-- [Adafruit ItsyBitsy nRF52840 Express](https://www.adafruit.com/product/4481)
-- [Arduino Nano 33 BLE](https://store.arduino.cc/usa/nano-33-ble)
-- [Arduino Nano 33 BLE Sense](https://store.arduino.cc/usa/nano-33-ble-sense)
-- [Maker Diary nRF52840 MDK Dongle](https://wiki.makerdiary.com/nrf52840-mdk-usb-dongle)
-- [Nordic nRF52840 Development Kit (aka pca10056)](https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK)
-- [Nordic nRF52840 Dongle (aka pca10059)](https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle)
-- [Nordic nRF52833 Development Kit (aka pca10100)](https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK)
-- [Raytac MDBT50Q-RX Dongle](https://www.raytac.com/product/ins.php?index_id=89)
-
-### Nuvoton
-
-- NuTiny SDK NUC120
-- [NuTiny NUC121S](https://direct.nuvoton.com/en/nutiny-nuc121s)
-- [NuTiny NUC125S](https://direct.nuvoton.com/en/nutiny-nuc125s)
-- [NuTiny NUC126V](https://direct.nuvoton.com/en/nutiny-nuc126v)
-- [NuTiny SDK NUC505Y](https://direct.nuvoton.com/en/nutiny-nuc505y)
-
-### NXP iMX RT
-
-- [MIMX RT1010 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1010-evaluation-kit:MIMXRT1010-EVK)
-- [MIMX RT1015 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1015-evaluation-kit:MIMXRT1015-EVK)
-- [MIMX RT1020 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1020-evaluation-kit:MIMXRT1020-EVK)
-- [MIMX RT1050 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK)
-- [MIMX RT1060 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1060-evk-i.mx-rt1060-evaluation-kit:MIMXRT1060-EVK)
-- [MIMX RT1064 Evaluation Kit](https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK)
-- [Teensy 4.0 Development Board](https://www.pjrc.com/store/teensy40.html)
-
-### NXP Kinetis
-
-- [FRDM-KL25Z](https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z)
-
-### NXP LPC 11-13-15
-
-- [LPCXpresso 11u37](https://www.nxp.com/design/microcontrollers-developer-resources/lpcxpresso-boards/lpcxpresso-board-for-lpc11u37h:OM13074)
-- [LPCXpresso 11u68](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc11u68:OM13058)
-- [LPCXpresso 1347](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1347:OM13045)
-- [LPCXpresso 1549](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1500-cortex-m3/lpcxpresso-board-for-lpc1549:OM13056)
-
-### NXP LPC 17-40
-
-- [ARM mbed LPC1768](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1700-cortex-m3/arm-mbed-lpc1768-board:OM11043)
-- [Embedded Artists LPC4088 Quick Start board](https://www.embeddedartists.com/products/lpc4088-quickstart-board)
-- [LPCXpresso 1769](https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1769:OM13000)
-
-### NXP LPC 18-43
-
-- [Embedded Artists LPC4357 Developer Kit](http://www.embeddedartists.com/products/kits/lpc4357_kit.php)
-- [Keil MCB1800 Evaluation Board](http://www.keil.com/mcb1800)
-- [LPCXpresso18S37 Development Board](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc4000-cortex-m4/lpcxpresso18s37-development-board:OM13076)
-- [NGX LPC4330-Xplorer](https://www.nxp.com/design/designs/lpc4330-xplorer-board:OM13027)
-
-### NXP LPC 51
-- [LPCXpresso 51U68](https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005)
-
-### NXP LPC 54
-
-- [LPCXpresso 54114](https://www.nxp.com/design/microcontrollers-developer-resources/lpcxpresso-boards/lpcxpresso54114-board:OM13089)
-
-## NXP LPC55
-
-- [Double M33 Express](https://www.crowdsupply.com/steiert-solutions/double-m33-express)
-- [LPCXpresso 55s28 EVK](https://www.nxp.com/design/software/development-software/lpcxpresso55s28-development-board:LPC55S28-EVK)
-- [LPCXpresso 55s69 EVK](https://www.nxp.com/design/development-boards/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK)
-- [MCU-Link](https://www.nxp.com/design/development-boards/lpcxpresso-boards/mcu-link-debug-probe:MCU-LINK)
-
-### Renesas RX
-
-- [GR-CITRUS](https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-citrus)
-- [Renesas RX65N Target Board](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk5rx65n0c00000br-target-board-rx65n)
-
-### Raspberry Pi RP2040
-
-- [Adafruit Feather RP2040](https://www.adafruit.com/product/4884)
-- [Adafruit ItsyBitsy RP2040](https://www.adafruit.com/product/4888)
-- [Adafruit QT Py RP2040](https://www.adafruit.com/product/4900)
-- [Raspberry Pi Pico](https://www.raspberrypi.org/products/raspberry-pi-pico/)
-
-### Silabs
-
-- [EFM32GG12 Thunderboard Kit (SLTB009A)](https://www.silabs.com/development-tools/thunderboard/thunderboard-gg12-kit)
-
-### Sony
-
-- [Sony Spresense CXD5602](https://developer.sony.com/develop/spresense)
-
-### ST STM32
-
-- [Adafruit Feather STM32F405](https://www.adafruit.com/product/4382)
-- [Micro Python PyBoard v1.1](https://store.micropython.org/product/PYBv1.1)
-- [STLink-V3 Mini](https://www.st.com/en/development-tools/stlink-v3mini.html)
-- [STM32 L035c8 Discovery](https://www.st.com/en/evaluation-tools/32l0538discovery.html)
-- [STM32 L4R5zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html)
-- [STM32 F070rb Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f070rb.html)
-- [STM32 F072 Evaluation](https://www.st.com/en/evaluation-tools/stm32072b-eval.html)
-- [STM32 F072rb Discovery](https://www.st.com/en/evaluation-tools/32f072bdiscovery.html)
-- STM32 F103c Blue Pill
-- [STM32 F207zg Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f207zg.html)
-- [STM32 F303vc Discovery](https://www.st.com/en/evaluation-tools/stm32f3discovery.html)
-- STM32 F401cc Black Pill
-- [STM32 F407vg Discovery](https://www.st.com/en/evaluation-tools/stm32f4discovery.html)
-- [STM32 F411ce Black Pill](https://www.adafruit.com/product/4877)
-- [STM32 F411ve Discovery](https://www.st.com/en/evaluation-tools/32f411ediscovery.html)
-- [STM32 F412zg Discovery](https://www.st.com/en/evaluation-tools/32f412gdiscovery.html)
-- [STM32 F723e Discovery](https://www.st.com/en/evaluation-tools/32f723ediscovery.html)
-- [STM32 F746zg Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f746zg.html)
-- [STM32 F746g Discovery](https://www.st.com/en/evaluation-tools/32f746gdiscovery.html)
-- [STM32 F767zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f767zi.html)
-- [STM32 F769i Discovery](https://www.st.com/en/evaluation-tools/32f769idiscovery.html)
-- [STM32 H743zi Nucleo](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html)
-- [STM32 H743i Evaluation](https://www.st.com/en/evaluation-tools/stm32h743i-eval.html)
-- [STM32 H745i Discovery](https://www.st.com/en/evaluation-tools/stm32h745i-disco.html)
-- [Waveshare OpenH743I-C](https://www.waveshare.com/openh743i-c-standard.htm)
-
-### TI
-
- - [MSP430F5529 USB LaunchPad Evaluation Kit](http://www.ti.com/tool/MSP-EXP430F5529LP)
-
-### Tomu
-
-- [Fomu](https://www.crowdsupply.com/sutajio-kosagi/fomu)
-
-## Add your own board
-
-If you don't possess any of supported board above. Don't worry you can easily implemented your own one by following this guide as long as the mcu is supported.
-
-- Create new makefile for your board at `hw/bsp/<board name>/board.mk` and linker file as well if needed.
-- Create new source file for your board at `hw/bsp/<board name>/<board name>.c` and implement following APIs
-
-### Board APIs
-
-#### board_init()
-
-Is responsible for starting the MCU, setting up the USB clock and USB pins. It is also responsible for initializing LED and button pins.
-One useful clock debugging technique is to set up a PWM output at a known value such as 500hz based on the USB clock so that you can verify it is correct with a logic probe or oscilloscope.
-Setup your USB in a crystal-less mode when available. That makes the code easier to port across boards.
-
-#### board_led_write()
-
-Set the pin corresponding to the led to output a value that lights the LED when `state` is true.
-
-#### board_button_read()
-
-Return current state of button, a `1` means active (pressed), a `0` means inactive.
-
-#### board_millis()
-
-The function returns the elapsed number of milliseconds since startup. On ARM this is commonly done with SysTick or Timer. This provide examples a way to measure time to blink LED or delay properly. It is only required when run examples without RTOS `CFG_TUSB_OS == OPT_OS_NONE`.
-
-#### board_uart_read()
-
-Get characters from UART peripheral.
-
-####  board_uart_write()
-
-Send characters to UART peripheral.
diff --git a/docs/changelog.md b/docs/changelog.md
deleted file mode 100644
index 3725c5a81..000000000
--- a/docs/changelog.md
+++ /dev/null
@@ -1,468 +0,0 @@
-# TinyUSB Changelog
-
-## 0.10.1 - 2021.06.03
-
-- rework rp2040 examples and CMake build, allow better integration with pico-sdk
-
-### Host Controller Driver (HCD)
-
-- Fix rp2040 host driver: incorrect PID with low speed device with max packet size of 8 bytes
-- Improve hub driver
-- Remove obsolete hcd_pipe_queue_xfer()/hcd_pipe_xfer()
-- Use hcd_frame_number() instead of micro frame
-- Fix OHCI endpoint address and xferred_bytes in xfer complete event
-
-## 0.10.0 - 2021.05.28
-
-- Rework tu_fifo_t with separated mutex for read and write, better support DMA with read/write buffer info. And constant address mode
-- Improve audio_test example and add audio_4_channel_mic example
-- Add new dfu example
-- Remove pico-sdk from submodule
-
-### Device Controller Driver (DCD)
-
-- Add new DCD port for Silabs EFM32GG12 with board Thunderboard Kit (SLTB009A)
-- Add new DCD port Renesas RX63N, board GR-CITRUS
-- Add new (optional) endpoint API dcd_edpt_xfer_fifo 
-- Fix build with nRF5340
-- Fix build with lpc15 and lpc54
-- Fix build with lpc177x_8x
-- STM32 Synopsys: greatly improve Isochronous transfer with edpt_xfer_fifo API
-- Support LPC55 port1 highspeed
-- Add support for Espressif esp32s3
-- nRF: fix race condition that could cause drop packet of Bulk OUT transfer
-
-### USB Device Driver (USBD)
-
-- Add new (optional) endpoint ADPI usbd_edpt_xfer_fifo
-
-### Device Class Driver
-
-CDC
-
-- [Breaking] tud_cdc_peek(), tud_vendor_peek() no longer support random offset and dropped position parameter.
-
-DFU
-
-- Add new DFU 1.1 class driver (WIP)
-
-HID
-
-- Fix keyboard report descriptor template
-- Add more hid keys constant from 0x6B to 0xA4
-- [Breaking] rename API
-  - HID_PROTOCOL_NONE/KEYBOARD/MOUST to HID_ITF_PROTOCOL_NONE/KEYBOARD/MOUSE
-  - tud_hid_boot_mode() to tud_hid_get_protocol()
-  - tud_hid_boot_mode_cb() to tud_hid_set_protocol_cb()
-
-MIDI
-
-- Fix MIDI buffer overflow issue
-- [Breaking] rename API
-  - Rename tud_midi_read() to tud_midi_stream_read()
-  - Rename tud_midi_write() to tud_midi_stream_write()
-  - Rename tud_midi_receive() to tud_midi_packet_read()
-  - Rename tud_midi_send() to tud_midi_packet_write()
-
-### Host Controller Driver (HCD)
-
-- No noticable changes
-
-### USB Host Driver (USBH)
-
-- No noticable changes
-
-### Host Class Driver
-
-- HID: Rework host hid driver, basically everything changes
-
-## 0.9.0 - 2021.03.12
-
-### Device Stack
-
-#### Device Controller Driver (DCD)
-
-RP2040
-
-- Fix endpoint buffer reallocation overrun problem
-- Fix osal_pico queue overflow in initialization
-- Fix Isochronous endpoint buffer size in transfer
-- Optimize hardware endpoint struct to reduce RAM usage
-- Fix enum walkaround forever check for SE0 when pull up is disabled
-
-Sony CXD56
-
-- Pass the correct speed on Spresense
-- Fix setup processed flag
-
-NXP Transdimention
-
-- Update dcd_init() to reset controller to device mode
-
-#### USB Device Driver (USBD)
-
-- Fix issue with status zlp (tud_control_status) is returned by class driver with SET/CLEAR_FEATURE for endpoint.
-- Correct endpoint size check for fullspeed bulk, can be 8, 16, 32, 64
-- Ack SET_INTERFACE even if it is not implemented by class driver.
-
-#### Device Class Driver
-
-DFU Runtime
-
-- rename dfu_rt to dfu_runtime for easy reading
-
-CDC
-
-- Add tud_cdc_send_break_cb() to support break request
-- Improve CDC receive, minor behavior changes: when tud_cdc_rx_wanted_cb() is invoked wanted_char may not be the last byte in the fifo 
-
-HID
-
-- [Breaking] Add itf argument to hid API to support multiple instances, follow API has signature changes
-  - tud_hid_descriptor_report_cb()
-  - tud_hid_get_report_cb()
-  - tud_hid_set_report_cb()
-  - tud_hid_boot_mode_cb()
-  - tud_hid_set_idle_cb()
-- Add report complete callback tud_hid_report_complete_cb() API
-- Add DPad/Hat support for HID Gamepad
-  - TUD_HID_REPORT_DESC_GAMEPAD() now support 16 buttons, 2 joysticks, 1 hat/dpad
-  - Add hid_gamepad_report_t along with GAMEPAD_BUTTON_ and GAMEPAD_HAT_ enum
-  - Add Gamepad to hid_composite / hid_composite_freertos example
-
-MIDI
-
-- Fix dropping MIDI sysex message when fifo is full
-- Fix typo in tud_midi_write24(), make example less ambigous for cable and channel
-- Fix incorrect endpoint descriptor length, MIDI v1 use Audio v1 which has 9-byte endpoint descriptor (instead of 7)
-
-### Host Stack
-
-#### Host Controller Driver (HCD)
-
-- Add rhport to hcd_init()
-- Improve EHCI/OHCI driver abstraction
-  - Move echi/ohci files to portable/
-  - Rename hcd_lpc18_43 to hcd_transdimension
-  - Sub hcd API with hcd_ehci_init(), hcd_ehci_register_addr()
-- Update NXP transdimention hcd_init() to reset controller to host mode
-  - Ported hcd to rt10xx
-
-#### USB Host Driver (USBH)
-
-- No noticeable changes to usbh
-
-#### Host Class Driver
-
-MSC
-
-- Rename tuh_msc_scsi_inquiry() to tuh_msc_inquiry()
-- Rename tuh_msc_mounted_cb/tuh_msc_unmounted_cb to tuh_msc_mount_cb/tuh_msc_unmount_cb to match device stack naming
-- Change tuh_msc_is_busy() to tuh_msc_ready()
-- Add read10 and write10 function: tuh_msc_read10(), tuh_msc_write10()
-- Read_Capacity is invoked as part of enumeration process
-- Add tuh_msc_get_block_count(), tuh_msc_get_block_size()
-- Add CFG_TUH_MSC_MAXLUN (default to 4) to hold lun capacities
-
-### Others
-
-- Add basic support for rt-thread OS
-- Change zero bitfield length to more explicit padding
-- Build example now fetch required submodules on the fly while running `make` without prio submodule init for mcu drivers
-- Update pico-sdk to v1.1.0
-
-**New Boards**
-
-- Microchip SAM E54 Xplained Pro
-- LPCXpresso 55s28
-- LPCXpresso 18s37
-
-## 0.8.0 - 2021.02.05
-
-### Device Controller Driver
-
-- Added new device support for Raspberry Pi RP2040
-- Added new device support for NXP Kinetis KL25ZXX
-- Use dcd_event_bus_reset() with link speed to replace bus_signal
-- ESP32-S2:
-  - Add bus suspend and wakeup support
-- SAMD21:
-  - Fix (walkaround) samd21 setup_packet overflow by USB DMA
-- STM32 Synopsys:
-  - Rework USB FIFO allocation scheme and allow RX FIFO size reduction
-- Sony CXD56
-  - Update Update Spresense SDK to 2.0.2
-  - Fix dcd issues with setup packets
-  - Correct EP number for cdc_msc example
-
-### USB Device 
-
-**USBD**
-
-- Rework usbd control transfer to have additional stage parameter for setup, data, status
-- Fix tusb_init() return true instead of TUSB_ERROR_NONE
-- Added new API tud_connected() that return true after device got out of bus reset and received the very first setup packet
-
-**Class Driver**
-
-- CDC
-  - Allow to transmit data, even if the host does not support control line states i.e set DTR
-- HID
-  - change default CFG_TUD_HID_EP_BUFSIZE from 16 to 64
-- MIDI
-  - Fix midi sysex sending bug
-- MSC
-  - Invoke only scsi complete callback after status transaction is complete.
-  - Fix scsi_mode_sense6_t padding, which cause IAR compiler internal error.
-- USBTMC
-  - Change interrupt endpoint example size to 8 instead of 2 for better compatibility with mcu 
-
-**Example**
-
-- Support make from windows cmd.exe 
-- Add HID Consumer Control (media keys) to hid_composite & hid_composite_freertos examples
-
-### USB Host
-
-No noticeable changes to host stack
-
-### New Boards
-
-- NXP/Freescale Freedom FRDM-KL25Z
-- Feather Double M33 express
-- Raspberry Pi Pico
-- Adafruit Feather RP2040
-- Adafruit Itsy Bitsy RP2040
-- Adafruit QT RP2040
-- Adfruit Feather ESP32-S2
-- Adafruit Magtag 29" Eink
-- Adafruit Metro ESP32-S2
-- Adafruit PyBadge
-- Adafruit PyPortal
-- Great Scott Gadgets' LUNA D11 & D21
-
-## 0.7.0 - 2020.11.08
-
-### Device Controller Driver
-
-- Added new support for Espressif ESP32-S2
-- Added new support for Dialog DA1469x
-- Enhance STM32 Synopsys
-  - Support bus events disconnection/suspend/resume/wakeup
-  - Improve transfer performance with optimizing xfer and fifo size
-  - Support Highspeed port (OTG_HS) with both internal and external PHY
-  - Support multiple usb ports with rhport=1 is highspeed on selected MCUs e.g H743, F23. It is possible to have OTG_HS to run on Fullspeed PHY (e.g lacking external PHY)
-  - Add ISO transfer, fix odd/even frame
-  - Fix FIFO flush during stall
-  - Implement dcd_edpt_close() API
-  - Support F105, F107
-- Enhance STM32 fsdev
-  - Improve dcd fifo allocation
-  - Fix ISTR race condition
-  - Support remap USB IRQ on supported MCUs
-  - Implement dcd_edpt_close() API
-- Enhance NUC 505: enhance set configure behavior
-- Enhance SAMD
-  - Fix race condition with setup packet
-  - Add SAMD11 option `OPT_MCU_SAMD11`
-  - Add SAME5x option `OPT_MCU_SAME5X`
-- Fix SAMG control data toggle and stall race condition
-- Enhance nRF
-  - Fix hanged when tud_task() is called within critical section (disabled interrupt)
-  - Fix disconnect bus event not submitted
-  - Implement ISO transfer and dcd_edpt_close()
-
-### USB Device
-
-**USBD**
-
-- Add new class driver for **Bluetooth HCI** class driver with example can be found in [mynewt-tinyusb-example](https://github.com/hathach/mynewt-tinyusb-example) since it needs mynewt OS to run with.
-- Fix USBD endpoint usage racing condition with `usbd_edpt_claim()/usbd_edpt_release()`
-- Added `tud_task_event_ready()` and `osal_queue_empty()`. This API is needed to check before enter low power mode with WFI/WFE
-- Rename USB IRQ Handler to `dcd_int_handler()`. Application must define IRQ handler in which it calls this API.
-- Add `dcd_connect()` and `dcd_disconnect()` to enable/disable internal pullup on D+/D- on supported MCUs.
-- Add `usbd_edpt_open()`
-- Remove `dcd_set_config()`
-- Add *OPT_OS_CUMSTOM* as hook for application to overwrite and/or add their own OS implementation
-- Support SET_INTERFACE, GET_INTERFACE request
-- Add Logging for debug with optional uart/rtt/swo printf retarget or `CFG_TUSB_DEBUG_PRINTF` hook
-- Add IAR compiler support
-- Support multiple configuration descriptors. `TUD_CONFIG_DESCRIPTOR()` template has extra config_num as 1st argument
-- Improve USB Highspeed support with actual link speed detection with `dcd_event_bus_reset()`
-- Enhance class driver management
-  - `usbd_driver_open()` add max length argument, and return length of interface (0 for not supported). Return value is used for finding appropriate driver
-  - Add application implemented class driver via `usbd_app_driver_get_cb()`
-  - IAD is handled to assign driver id
-- Added `tud_descriptor_device_qualifier_cb()` callback
-- Optimize `tu_fifo` bulk write/read transfer
-- Forward non-std control request to class driver
-- Let application handle Microsoft OS 1.0 Descriptors (the 0xEE index string)
-- Fix OSAL FreeRTOS yield from ISR
-
-**Class Drivers**
-
-- USBNET: remove ACM-EEM due to lack of support from host
-- USBTMC: fix descriptors when INT EP is disabled
-- CDC:
-  - Send zero length packet for end of data when needed
-  - Add `tud_cdc_tx_complete_cb()` callback
-  - Change tud_cdc_n_write_flush() return number of bytes forced to transfer, and flush when writing enough data to fifo
-- MIDI:
-  - Add packet interface
-  - Add multiple jack descriptors
-  - Fix MIDI driver for sysex
-- DFU Runtime: fix response to SET_INTERFACE and DFU_GETSTATUS request
-- Rename some configure macro to make it clear that those are used directly for endpoint transfer
-  - CFG_TUD_HID_BUFSIZE to `CFG_TUD_HID_EP_BUFSIZE
-  - CFG_TUD_CDC_EPSIZE to CFG_TUD_CDC_EP_BUFSIZE
-  - CFG_TUD_MSC_BUFSIZE to CFG_TUD_MSC_EP_BUFSIZE
-  - CFG_TUD_MIDI_EPSIZE to CFG_TUD_MIDI_EP_BUFSIZE
-- HID:
-  - Fix gamepad template descriptor
-  - Add multiple HID interface API
-  - Add extra comma to HID_REPORT_ID
-
-### USB Host
-
-- Rework USB host stack (still work in progress)
-  - Fix compile error with pipehandle
-  - Rework usbh control and enumeration as non-blocking
-- Improve Hub, MSC, HID host driver
-
-### Examples
-
-- Add new hid_composite_freertos
-- Add new dynamic_configuration to demonstrate how to switch configuration descriptors
-- Add new hid_multiple_interface
-- Enhance `net_lwip_webserver` example
-  - Add multiple configuration: RNDIS for Windows, CDC-ECM for macOS (Linux will work with both)
-  - Update lwip to STABLE-2_1_2_RELEASE for net_lwip_webserver
-- Added new Audio example: audio_test uac2_headsest
-
-### New Boards
-
-- Espressif ESP32-S2: saola_1, kaluga_1
-- STM32: F746 Nucleo, H743 Eval, H743 Nucleo, F723 discovery, stlink v3 mini, STM32L4r5 Nucleo
-- Dialog DA1469x dk pro and dk usb
-- Microchip: Great Scoot Gadgets' LUNA, samd11_xplained, D5035-01, atsamd21 xplained pro
-- nRF: ItsyBitsy nRF52840
-
-## 0.6.0 - 2020.03.30
-
-Added **CONTRIBUTORS.md** to give proper credit for contributors to the stack. Special thanks to [Nathan Conrad](https://github.com/pigrew), [Peter Lawrence](https://github.com/majbthrd) and [William D. Jones](https://github.com/cr1901) and others for spending their precious time to add lots of features and ports for this release.
-
-### Added
-
-**MCUs**
-
-- Added support for Microchip SAMG55
-- Added support for Nordic nRF52833
-- Added support for Nuvoton: NUC120, NUC121/NUC125, NUC126, NUC505
-- Added support for NXP LPC: 51Uxx, 54xxx, 55xx
-- Added support for NXP iMXRT: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
-- Added support for Sony CXD56 (Spresense)
-- Added support for STM32: L0, F0, F1, F2, F3, F4, F7, H7
-- Added support for TI MSP430
-- Added support for ValentyUSB's eptri
-
-**Class Driver**
-
-- Added DFU Runtime class driver
-- Added Network class driver with RNDIS, CDC-ECM, CDC-EEM (work in progress)
-- Added USBTMC class driver
-- Added WebUSB class driver using vendor-specific class
-- Added multiple instances support for CDC and MIDI
-- Added a handful of unit test with Ceedling.
-- Added LOG support for debugging with CFG_TUSB_DEBUG
-- Added `tud_descriptor_bos_cb()` for BOS descriptor (required for USB 2.1)
-- Added `dcd_edpt0_status_complete()` as optional API for DCD
-
-**Examples**
-
-Following examples are added:
-
-- board_test
-- cdc_dual_ports
-- dfu_rt
-- hid_composite
-- net_lwip_webserver
-- usbtmc
-- webusb_serial
-
-**Boards**
-
-Following boards are added:
-
-- adafruit_clue
-- arduino_nano33_ble
-- circuitplayground_bluefruit
-- circuitplayground_express
-- feather_m0_express
-- feather_nrf52840_sense
-- feather_stm32f405
-- fomu
-- itsybitsy_m0
-- itsybitsy_m4
-- lpcxpresso11u37
-- lpcxpresso1549
-- lpcxpresso51u68
-- lpcxpresso54114
-- lpcxpresso55s69
-- mbed1768
-- mimxrt1010_evk
-- mimxrt1015_evk
-- mimxrt1020_evk
-- mimxrt1050_evkb
-- mimxrt1060_evk
-- mimxrt1064_evk
-- msp_exp430f5529lp
-- ngx4330
-- nrf52840_mdk_dongle
-- nutiny_nuc121s
-- nutiny_nuc125s
-- nutiny_nuc126v
-- nutiny_sdk_nuc120
-- nutiny_sdk_nuc505
-- pca10059
-- pca10100
-- pyboardv11
-- raytac_mdbt50q_rx
-- samg55xplained
-- seeeduino_xiao
-- spresense
-- stm32f070rbnucleo
-- stm32f072disco
-- stm32f103bluepill
-- stm32f207nucleo
-- stm32f401blackpill
-- stm32f411blackpill
-- stm32f411disco
-- stm32f412disco
-- stm32f767nucleo
-- stm32h743nucleo
-- stm32l0538disco
-- stm32l476disco
-- teensy_40
-
-### Changed
-
-- Changed `tud_descriptor_string_cb()` to have additional Language ID argument
-- Merged hal_nrf5x.c into dcd_nrf5x.c
-- Merged dcd_samd21.c and dcd_samd51.c into dcd_samd.c
-- Generalized dcd_stm32f4.c to dcd_synopsys.c
-- Changed cdc_msc_hid to cdc_msc (drop hid) due to limited endpoints number of some MCUs 
-- Improved DCD SAMD stability, fix missing setup packet occasionally
-- Improved usbd/usbd_control with proper hanlding of zero-length packet (ZLP)
-- Improved STM32 DCD FSDev
-- Improved STM32 DCD Synopsys
-- Migrated CI from Travis to Github Action
-- Updated nrfx submodule to 2.1.0
-- Fixed mynewt osal queue definition
-- Fixed cdc_msc_freertos example build for all MCUs
-
-## 0.5.0 (Initial Release) - 2019.07.10
-
-First release, device stack works great, host stack works but still need improvement. 
-- Special thanks to @adafruit team, especially @tannewt to help out immensely to rework device stack: simplify osal & control transfer, adding SAMD21/SAMD51 ports, writing porting docs, adding MIDI class support etc... 
-- Thanks to @cr1901 for adding STM32F4 port.
-- Thanks to @PTS93 and @todbot for HID raw API
diff --git a/docs/concurrency.md b/docs/concurrency.md
deleted file mode 100644
index e05ca6ffe..000000000
--- a/docs/concurrency.md
+++ /dev/null
@@ -1,36 +0,0 @@
-# Concurrency
-
-The TinyUSB library is designed to operate on single-core MCUs with multi-threaded applications in mind. Interaction with interrupts is especially important to pay attention to.
-It is compatible with optionally using a RTOS.
-
-## General
-
-When writing code, keep in mind that the OS (if using a RTOS) may swap out your code at any time. Also, your code can be preempted by an interrupt at any time.
-
-## Application Code
-
-The USB core does not execute application callbacks while in an interrupt context. Calls to application code are from within the USB core task context. Note that the application core will call class drivers from within their own task.
-
-## Class Drivers
-
-Class driver code should never be called from an interrupt context by the USB core, though the application is allowed to call class driver functions from interrupts. USB core functions may be called simultaneously by multiple tasks. Use care that proper locking is used to guard the USBD core functions from this case.
-
-Class drivers are allowed to call `usbd_*` functions, but not `dcd_*` functions.
-
-## USB Core
-
-All functions that may be called from an (USB core) interrupt context have a `bool in_isr` parameter to remind the implementer that special care must be taken.
-
-Interrupt handlers must not directly call class driver code, they must pass a message to the USB core's task.
-
- `usbd_*` functions may be called from interrupts without any notice. They may also be called simultaneously by multiple tasks.
-
-## Device Drivers
-
-Much of the processing of the USB stack is done in an interrupt context, and care must be taken in order to ensure variables are handled in the appropriate ways by the compiler and optimizer.
-
-In particular:
-
-- Ensure that all memory-mapped registers (including packet memory) are marked as volatile. GCC's optimizer will even combine memory access (like two 16-bit to be a 32-bit) if you don't mark the pointers as volatile. On some architectures, this can use macros like `_I`, `_O`, or `_IO'.
-- All defined global variables are marked as  `static`.
- 
diff --git a/docs/conf.py b/docs/conf.py
new file mode 100644
index 000000000..c7a17478f
--- /dev/null
+++ b/docs/conf.py
@@ -0,0 +1,42 @@
+# Configuration file for the Sphinx documentation builder.
+#
+# This file only contains a selection of the most common options. For a full
+# list see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Path setup --------------------------------------------------------------
+
+
+# -- Project information -----------------------------------------------------
+
+project = 'TinyUSB'
+copyright = '2021, Ha Thach'
+author = 'Ha Thach'
+
+
+# -- General configuration ---------------------------------------------------
+
+extensions = [
+    'sphinx.ext.autodoc',
+    'sphinx.ext.intersphinx',
+    'sphinx.ext.todo',
+    'sphinx_autodoc_typehints',
+    'sphinxemoji.sphinxemoji',
+]
+
+templates_path = ['_templates']
+
+exclude_patterns = ['_build']
+
+
+# -- Options for HTML output -------------------------------------------------
+
+html_theme = 'furo'
+html_title = 'TinyUSB'
+html_logo = 'assets/logo.svg'
+html_favicon = 'assets/logo.svg'
+html_theme_options = {
+    'sidebar_hide_name': True,
+}
+
+todo_include_todos = True
diff --git a/docs/getting_started.md b/docs/getting_started.md
deleted file mode 100644
index 8ec0ea748..000000000
--- a/docs/getting_started.md
+++ /dev/null
@@ -1,137 +0,0 @@
-# Getting Started #
-
-## Add TinyUSB to your project
-
-It is relatively simple to incorporate tinyusb to your (existing) project
-
-- Copy or `git submodule` this repo into your project in a subfolder. Let's say it is *your_project/tinyusb*
-- Add all the .c in the `tinyusb/src` folder to your project
-- Add *your_project/tinyusb/src* to your include path. Also make sure your current include path also contains the configuration file tusb_config.h.
-- Make sure all required macros are all defined properly in tusb_config.h (configure file in demo application is sufficient, but you need to add a few more such as CFG_TUSB_MCU, CFG_TUSB_OS since they are passed by IDE/compiler to maintain a unique configure for all boards).
-- If you use the device stack, make sure you have created/modified usb descriptors for your own need. Ultimately you need to implement all **tud_descriptor_** callbacks for the stack to work.
-- Add tusb_init() call to your reset initialization code.
-- Call `tud_int_handler()` (device) and/or `tuh_int_handler()` (host) in your USB IRQ Handler
-- Implement all enabled classes's callbacks.
-- If you don't use any RTOSes at all, you need to continuously and/or periodically call tud_task()/tuh_task() function. All of the callbacks and functionality are handled and invoked within the call of that task runner.
-
-~~~{.c}
-int main(void)
-{
-  your_init_code();
-  tusb_init(); // initialize tinyusb stack
-
-  while(1) // the mainloop
-  {
-    your_application_code();
-
-    tud_task(); // device task
-    tuh_task(); // host task
-  }
-}
-~~~
-
-## Examples
-
-For your convenience, TinyUSB contains a handful of examples for both host and device with/without RTOS to quickly test the functionality as well as demonstrate how API() should be used. Most examples will work on most of [the supported Boards](boards.md). Firstly we need to `git clone` if not already
-
-```
-$ git clone https://github.com/hathach/tinyusb tinyusb
-$ cd tinyusb
-```
-
-Some TinyUSB examples also requires external submodule libraries in `/lib` such as FreeRTOS, Lightweight IP to build. Run following command to fetch them 
-
-```
-$ git submodule update --init lib
-```
-
-In addition, MCU driver submodule is also needed to provide low-level MCU peripheral's driver. Luckily, it will be fetched if needed when you run the `make` to build your board.
-
-Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy `/examples/device/99-tinyusb.rules` file to /etc/udev/rules.d/ then run `sudo udevadm control --reload-rules && sudo udevadm trigger` is good enough.
-
-### Build
-
-To build example, first change directory to an example folder. 
-
-```
-$ cd examples/device/cdc_msc
-```
-
-Then compile with `make BOARD=[board_name] all`, for example
-
-```
-$ make BOARD=feather_nrf52840_express all
-```
-
-Note: `BOARD` can be found as directory name in `hw/bsp`, either in its family/boards or directly under bsp (no family).
-
-#### Port Selection
-
-If a board has several ports, one port is chosen by default in the individual board.mk file. Use option `PORT=x` To choose another port. For example to select the HS port of a STM32F746Disco board, use:
-
-```
-$ make BOARD=stm32f746disco PORT=1 all
-```
-
-#### Port Speed
-
-A MCU can support multiple operational speed. By default, the example build system will use the fastest supported on the board. Use option `SPEED=full/high` e.g To force F723 operate at full instead of default high speed
-
-```
-$ make BOARD=stm32f746disco SPEED=full all
-```
-
-### Debug
-
-To compile for debugging add `DEBUG=1`, for example
-
-```
-$ make BOARD=feather_nrf52840_express DEBUG=1 all
-```
-
-#### Log
-
-Should you have an issue running example and/or submitting an bug report. You could enable TinyUSB built-in debug logging with optional `LOG=`. LOG=1 will only print out error message, LOG=2 print more information with on-going events. LOG=3 or higher is not used yet. 
-
-```
-$ make BOARD=feather_nrf52840_express LOG=2 all
-```
-
-#### Logger
-
-By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols: 
-
-- `LOGGER=rtt`: use [Segger RTT protocol](https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/)   
-  - Cons: requires jlink as the debugger.
-  - Pros: work with most if not all MCUs
-  - Software viewer is JLink RTT Viewer/Client/Logger which is bundled with JLink driver package.
-- `LOGGER=swo`: Use dedicated SWO pin of ARM Cortex SWD debug header.
-  - Cons: only work with ARM Cortex MCUs minus M0
-  - Pros: should be compatible with more debugger that support SWO.
-  - Software viewer should be provided along with your debugger driver.
-
-```
-$ make BOARD=feather_nrf52840_express LOG=2 LOGGER=rtt all
-$ make BOARD=feather_nrf52840_express LOG=2 LOGGER=swo all
-```
-
-### Flash
-
-`flash` target will use the default on-board debugger (jlink/cmsisdap/stlink/dfu) to flash the binary, please install those support software in advance. Some board use bootloader/DFU via serial which is required to pass to make command
-
-```
-$ make BOARD=feather_nrf52840_express flash
-$ make SERIAL=/dev/ttyACM0 BOARD=feather_nrf52840_express flash
-```
-
-Since jlink can be used with most of the boards, there is also `flash-jlink` target for your convenience.
-
-```
-$ make BOARD=feather_nrf52840_express flash-jlink
-```
-
-Some board use uf2 bootloader for drag & drop in to mass storage device, uf2 can be generated with `uf2` target
-
-```
-$ make BOARD=feather_nrf52840_express all uf2
-```
diff --git a/docs/index.rst b/docs/index.rst
new file mode 100644
index 000000000..d30b743f4
--- /dev/null
+++ b/docs/index.rst
@@ -0,0 +1,20 @@
+.. TinyUSB documentation master file, created by
+   sphinx-quickstart on Mon Jul 26 17:17:52 2021.
+   You can adapt this file completely to your liking, but it should at least
+   contain the root `toctree` directive.
+
+Welcome to TinyUSB's documentation!
+===================================
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+
+
+Indices and tables
+==================
+
+* :ref:`genindex`
+* :ref:`modindex`
+* :ref:`search`
diff --git a/docs/porting.md b/docs/porting.md
deleted file mode 100644
index d3c688a81..000000000
--- a/docs/porting.md
+++ /dev/null
@@ -1,191 +0,0 @@
-# Porting
-
-TinyUSB is designed to be a universal USB protocol stack for microcontrollers. It
-handles most of the high level USB protocol and relies on the microcontroller's USB peripheral for
-data transactions on different endpoints. Porting is the process of adding low-level support for
-the rest of the common stack. Once the low-level is implemented, it is very easy to add USB support
-for the microcontroller to other projects, especially those already using TinyUSB such as CircuitPython.
-
-Below are instructions on how to get the cdc_msc device example running on a new microcontroller. Doing so includes adding the common code necessary for other uses while minimizing other extra code. Whenever you see a phrase or word in <> it should be replaced.
-
-## Register defs
-
-The first step to adding support is including the register definitions and startup code for the
-microcontroller in TinyUSB. We write the TinyUSB implementation against these structs instead of higher level functions to keep the code small and to prevent function name collisions in linking of larger projects. For ARM microcontrollers this is the CMSIS definitions. They should be
-placed in the `hw/mcu/<vendor>/<chip_family>` directory.
-
-Once this is done, create a directory in `hw/bsp/<your board name>` for the specific board you are using to test the code.  (Duplicating an existing board's directory is the best way to get started.) The board should be a readily available development board so that others can also test.
-
-## Build
-Now that those directories are in place, we can start our iteration process to get the example building successfully. To build, run from the root of TinyUSB:
-
-`make -C examples/device/cdc_msc BOARD=<board>`
-
-Unless, you've read ahead, this will fail miserably. Now, lets get it to fail less by updating the files in the board directory. The code in the board's directory is responsible for setting up the microcontroller's clocks and pins so that USB works. TinyUSB itself only operates on the USB peripheral. The board directory also includes information what files are needed to build the example.
-
-One of the first things to change is the `-DCFG_TUSB_MCU` cflag in the `board.mk` file. This is used to tell TinyUSB what platform is being built. So, add an entry to `src/tusb_option.h` and update the CFLAG to match.
-
-Update `board.mk`'s VENDOR and CHIP_FAMILY values when creating the directory for the struct files. Duplicate one of the other sources from `src/portable` into `src/portable/<vendor>/<chip_family>` and delete all of the implementation internals. We'll cover what everything there does later. For now, get it compiling.
-
-## Implementation
-At this point you should get an error due to an implementation issue and hopefully the build is setup for the new MCU. You will still need to modify the `board.mk` to include specific CFLAGS, the linker script, linker flags, source files, include directories. All file paths are relative to the top of the TinyUSB repo.
-
-### Board Support (BSP)
-The board support code is only used for self-contained examples and testing. It is not used when TinyUSB is part of a larger project. Its responsible for getting the MCU started and the USB peripheral clocked. It also optionally provides LED definitions that are used to blink an LED to show that the code is running.
-
-It is located in `hw/bsp/<board name>/board_<board name>.c`.
-
-#### board_init
-`board_init` is responsible for starting the MCU, setting up the USB clock and USB pins. It is also responsible for initializing LED pins.
-
-One useful clock debugging technique is to set up a PWM output at a known value such as 500hz based on the USB clock so that you can verify it is correct with a logic probe or oscilloscope.
-
-Setup your USB in a crystal-less mode when available. That makes the code easier to port across boards.
-
-#### board_led_write
-Feel free to skip this until you want to verify your demo code is running. To implement, set the pin corresponding to the led to output a value that lights the LED when `state` is true.
-
-### OS Abstraction Layer (OSAL)
-
-The OS Abstraction Layer is responsible for providing basic data structures for TinyUSB that may allow for concurrency when used with an RTOS. Without an RTOS it simply handles concurrency issues between the main code and interrupts.
-
-The code is almost entirely agnostic of MCU and lives in `src/osal`.
-
-### Device API
-
-After the USB device is setup, the USB device code works by processing events on the main thread (by calling `tud_task`). These events are queued by the USB interrupt handler. So, there are three parts to the device low-level API: device setup, endpoint setup and interrupt processing.
-
-All of the code for the low-level device API is in `src/portable/<vendor>/<chip family>/dcd_<chip family>.c`.
-
-#### Device Setup
-
-##### dcd_init
-
-Initializes the USB peripheral for device mode and enables it.
-This function should enable internal D+/D- pull-up for enumeration.
-
-##### dcd_int_enable / dcd_int_disable
-
-Enables or disables the USB device interrupt(s). May be used to prevent concurrency issues when mutating data structures shared between main code and the interrupt handler.
-
-##### dcd_int_handler
-
-Processes all the hardware generated events e.g Bus reset, new data packet from host etc ... It will be called by application in the MCU USB interrupt handler.
-
-##### dcd_set_address
-
-Called when the device is given a new bus address.
-
-If your peripheral automatically changes address during enumeration (like the nrf52) you may leave this empty and also no queue an event for the corresponding SETUP packet.
-
-##### dcd_remote_wakeup
-
-Called to remote wake up host when suspended (e.g hid keyboard)
-
-##### dcd_connect / dcd_disconnect
-
-Connect or disconnect the data-line pull-up resistor. Define only if MCU has an internal pull-up. (BSP may define for MCU without internal pull-up.)
-
-#### Special events
-
-You must let TinyUSB know when certain events occur so that it can continue its work. There are a few methods you can call to queue events for TinyUSB to process.
-
-##### dcd_event_bus_signal
-
-There are a number of events that your peripheral may communicate about the state of the bus. Here is an overview of what they are. Events in **BOLD** must be provided for TinyUSB to work.
-
-* **DCD_EVENT_RESET** - Triggered when the host resets the bus causing the peripheral to reset. Do any other internal reset you need from the interrupt handler such as resetting the control endpoint.
-* DCD_EVENT_SOF - Signals the start of a new USB frame.
-
-Calls to this look like:
-
-    dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
-
-The first `0` is the USB peripheral number. Statically saying 0 is common for single USB device MCUs.
-
-The `true` indicates the call is from an interrupt handler and will always be the case when porting in this way.
-
-##### dcd_setup_received
-
-SETUP packets are a special type of transaction that can occur at any time on the control endpoint, numbered `0`. Since they are unique, most peripherals have special handling for them. Their data is always 8 bytes in length as well.
-
-Calls to this look like:
-
-    dcd_event_setup_received(0, setup, true);
-
-As before with `dcd_event_bus_signal` the first argument is the USB peripheral number and the third is true to signal its being called from an interrupt handler. The middle argument is byte array of length 8 with the contents of the SETUP packet. It can be stack allocated because it is copied into the queue.
-
-#### Endpoints
-
-Endpoints are the core of the USB data transfer process. They come in a few forms such as control, isochronous, bulk, and interrupt. We won't cover the details here except with some caveats in open below. In general, data is transferred by setting up a buffer of a given length to be transferred on a given endpoint address and then waiting for an interrupt to signal that the transfer is finished. Further details below.
-
-Endpoints within USB have an address which encodes both the number and direction of an endpoint. TinyUSB provides `tu_edpt_number` and `tu_edpt_dir` to unpack this data from the address. Here is a snippet that does it.
-
-    uint8_t epnum = tu_edpt_number(ep_addr);
-    uint8_t dir   = tu_edpt_dir(ep_addr);
-
-##### dcd_edpt_open
-
-Opening an endpoint is done for all non-control endpoints once the host picks a configuration that the device should use. At this point, the endpoint should be enabled in the peripheral and configured to match the endpoint descriptor. Pay special attention to the direction of the endpoint you can get from the helper methods above. It will likely change what registers you are setting.
-
-Also make sure to enable endpoint specific interrupts.
-
-##### dcd_edpt_close
-
-Close an endpoint. his function is used for implementing alternate settings.
-
-After calling this, the device should not respond to any packets directed towards this endpoint. When called, this function must abort any transfers in progress through this endpoint, before returning.
-
-Implementation is optional. Must be called from the USB task. Interrupts could be disabled or enabled during the call.
-
-##### dcd_edpt_xfer
-
-`dcd_edpt_xfer` is responsible for configuring the peripheral to send or receive data from the host. "xfer" is short for "transfer". **This is one of the core methods you must implement for TinyUSB to work (one other is the interrupt handler).**  Data from the host is the OUT direction and data to the host is IN. It  is used for all endpoints including the control endpoint 0. Make sure to handle the zero-length packet STATUS packet on endpoint 0 correctly. It may be a special transaction to the peripheral.
-
-Besides that, all other transactions are relatively straight-forward. The endpoint address provides the endpoint
-number and direction which usually determines where to write the buffer info. The buffer and its length are usually
-written to a specific location in memory and the peripheral is told the data is valid. (Maybe by writing a 1 to a
-register or setting a counter register to 0 for OUT or length for IN.)
-
-The transmit buffer alignment is determined by `CFG_TUSB_MEM_ALIGN`.
-
-One potential pitfall is that the buffer may be longer than the maximum endpoint size of one USB
-packet. Some peripherals can handle transmitting multiple USB packets for a provided buffer (like the SAMD21).
-Others (like the nRF52) may need each USB packet queued individually. To make this work you'll need to track
-some state for yourself and queue up an intermediate USB packet from the interrupt handler.
-
-Once the transaction is going, the interrupt handler will notify TinyUSB of transfer completion.
-During transmission, the IN data buffer is guarenteed to remain unchanged in memory until the `dcd_xfer_complete` function is called.
-
-The dcd_edpt_xfer function must never add zero-length-packets (ZLP) on its own to a transfer. If a ZLP is required,
-then it must be explicitly sent by the stack calling dcd_edpt_xfer(), by calling dcd_edpt_xfer() a second time with len=0.
-For control transfers, this is automatically done in `usbd_control.c`.
-
-At the moment, only a single buffer can be transmitted at once. There is no provision for double-buffering. new dcd_edpt_xfer() will not
-be called again on the same endpoint address until the driver calls dcd_xfer_complete() (except in cases of USB resets).
-
-##### dcd_xfer_complete
-
-Once a transfer completes you must call dcd_xfer_complete from the USB interrupt handler to let TinyUSB know that a transaction has completed. Here is a sample call:
-
-    dcd_event_xfer_complete(0, ep_addr, xfer->actual_len, XFER_RESULT_SUCCESS, true);
-
-The arguments are:
-* the USB peripheral number
-* the endpoint address
-* the actual length of the transfer. (OUT transfers may be smaller than the buffer given in `dcd_edpt_xfer`)
-* the result of the transfer. Failure isn't handled yet.
-* `true` to note the call is from an interrupt handler.
-
-##### dcd_edpt_stall / dcd_edpt_clear_stall
-
-Stalling is one way an endpoint can indicate failure such as when an unsupported command is transmitted. The pair of `dcd_edpt_stall`, `dcd_edpt_clear_stall` help manage the stall state of all endpoints.
-
-## Woohoo!
-
-At this point you should have everything working! ;-) Of course, you may not write perfect code. Here are some tips and tricks for debugging.
-
-Use [WireShark](https://www.wireshark.org/) or [a Beagle](https://www.totalphase.com/protocols/usb/) to sniff the USB traffic. When things aren't working its likely very early in the USB enumeration process. Figuring out where can help clue in where the issue is. For example:
-* If the host sends a SETUP packet and its not ACKed then your USB peripheral probably isn't started correctly.
-* If the peripheral is started correctly but it still didn't work, then verify your usb clock is correct. (You did output a PWM based on it right? ;-) )
-* If the SETUP packet is ACKed but nothing is sent back then you interrupt handler isn't queueing the setup packet correctly. (Also, if you are using your own code instead of an example `tud_task` may not be called.) If thats OK, the `dcd_xfer_complete` may not be setting up the next transaction correctly.
diff --git a/docs/requirements.txt b/docs/requirements.txt
new file mode 100644
index 000000000..e415ae03e
--- /dev/null
+++ b/docs/requirements.txt
@@ -0,0 +1,4 @@
+sphinx~=3.0
+furo>=2020.12.30.b24
+sphinxemoji>=0.1.8
+sphinx-autodoc-typehints>=1.10

From 665c9c996ac80401f5a79ee62e642ea82b734ebb Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Mon, 26 Jul 2021 19:18:54 +0100
Subject: [PATCH 0254/2085] docs: add new svg logo

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/assets/logo.svg | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 docs/assets/logo.svg

diff --git a/docs/assets/logo.svg b/docs/assets/logo.svg
new file mode 100644
index 000000000..01c763ba9
--- /dev/null
+++ b/docs/assets/logo.svg
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<svg width="280" height="140" version="1.1" viewBox="0 0 74.083 37.042" xmlns="http://www.w3.org/2000/svg">
+  <g transform="translate(-60.931 -79.245)">
+    <g transform="matrix(1.0442 0 0 1.1531 -27.105 33.588)" fill="#fff">
+      <path d="m86.972 39.594c-1.4683 3.2e-5 -2.6588 1.181-2.66 2.6384v26.844c3.3e-5 1.4583 1.1909 2.6404 2.66 2.6404h65.63c1.469-3.2e-5 2.66-1.1822 2.66-2.6404v-26.844c-1e-3 -1.4575-1.1917-2.6384-2.66-2.6384z" color="#000000" fill="#fff" style="-inkscape-stroke:none"/>
+    </g>
+    <g transform="matrix(.35278 0 0 -.35278 -160.36 421.93)" fill="#231f20">
+      <path transform="translate(672.09 955.48)" d="m0 0h-21.484v-12.601h-5.349v-6.436h5.349v-25.383c0-11.331 7.252-13.87 17.223-13.87 4.352 0 8.613 0.272 12.873 0.907v6.073c-0.816-0.09-2.266-0.362-3.535-0.362-3.807 0-5.077 0.816-5.077 4.896v27.739h8.612v6.436h-8.612z"/>
+      <path transform="translate(693.61 925.33)" d="m0 0h-0.049c-1.518 0-2.165-0.896-2.165-2.24v-0.05h4.504v0.05c0 1.344-0.771 2.24-2.29 2.24"/>
+      <path transform="translate(700.92 925.5)" d="m0 0h-0.124c-1.443 0-2.265-0.995-2.265-2.389v-0.074h4.654v0.074c0 1.394-0.822 2.389-2.265 2.389"/>
+      <path transform="translate(750.09 943.78)" d="m0 0c-6.165 0-11.876-2.267-14.505-5.893v4.986h-20.578v-45.326h21.484v36.533c1.27 0.272 2.449 0.453 3.717 0.453 4.715 0 5.44-2.538 5.44-6.436v-30.55h21.484v30.278c0 11.694-7.523 15.955-17.042 15.955"/>
+      <path transform="translate(811.83 942.88)" d="m0 0-10.516-23.57-11.784 23.57h-23.388l24.204-48.046-6.799-15.411h8.249l28.193 63.457z"/>
+      <path transform="translate(706 920)" d="m0 0h-17.421v2.637c0 2.938 1.194 5.675 4.43 5.675h0.124c2.24 0 3.335-1.269 3.932-2.514 0.647 1.469 1.667 2.738 3.883 2.738h0.224c3.086 0 4.828-2.39 4.828-5.774zm-0.598-9.412h-3.16c0.622 1.07 0.971 1.917 0.971 2.737 0 0.871-0.424 1.618-1.493 1.618h-0.05c-0.797 0-1.394-0.249-3.037-1.692-2.339-2.065-3.459-2.912-5.574-2.912h-0.05c-2.787 0-4.555 1.816-4.555 4.231 0 1.219 0.175 1.941 0.548 2.687h3.161c-0.548-0.945-0.797-1.518-0.797-2.314 0-0.845 0.548-1.568 1.493-1.568h0.05c0.821 0 1.12 0.25 2.788 1.692 2.762 2.39 3.832 2.912 5.824 2.912h0.048c2.739 0 4.555-1.917 4.555-4.305 0-1.195-0.298-2.215-0.722-3.086m-4.479-10.93h-12.344v3.011h12.643c1.567 0 2.189 0.548 2.189 1.319 0 0.772-0.622 1.32-2.189 1.32h-12.643v3.01h12.344c3.658 0 5.301-1.841 5.301-4.33 0-2.488-1.643-4.33-5.301-4.33m-9.641 53.817h12.114v-10.601h-12.114zm14.114 2h-16.114v-12.601h-2.685v-45.326h21.484v45.326h-2.685z"/>
+      <path d="m692.79 947.02h2.827v2.319h-2.827z"/>
+      <path d="m699.06 947.02h2.826v2.319h-2.826z"/>
+    </g>
+  </g>
+</svg>

From 51c2240efae38d10f472af49e30e12a3e9cfa1bc Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Mon, 26 Jul 2021 19:20:26 +0100
Subject: [PATCH 0255/2085] docs: add readthedocs config

Signed-off-by: perigoso <perigoso@riseup.net>
---
 .readthedocs.yml | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 .readthedocs.yml

diff --git a/.readthedocs.yml b/.readthedocs.yml
new file mode 100644
index 000000000..215b5fed1
--- /dev/null
+++ b/.readthedocs.yml
@@ -0,0 +1,13 @@
+# .readthedocs.yaml
+# Read the Docs configuration file
+# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
+
+version: 2
+
+sphinx:
+   configuration: docs/conf.py
+
+python:
+  version: 3.8
+  install:
+    - requirements: docs/requirements.txt

From 27a9a7d7f11c84e5994200f396b0b1865c8631ba Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Mon, 26 Jul 2021 19:29:24 +0100
Subject: [PATCH 0256/2085] readme: use new svg logo

Signed-off-by: perigoso <perigoso@riseup.net>
---
 README.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/README.md b/README.md
index df0c05e67..c1f09720d 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,4 @@
-# TinyUSB
-
-![TinyUSB](https://user-images.githubusercontent.com/2847802/108847382-a0a6a580-75ad-11eb-96d9-280c79389281.png)
+![TinyUSB](docs/assets/logo.svg)
 
 [![Build Status](https://github.com/hathach/tinyusb/workflows/Build/badge.svg)](https://github.com/hathach/tinyusb/actions) [![License](https://img.shields.io/badge/license-MIT-brightgreen.svg)](https://opensource.org/licenses/MIT)
 

From f424765514ef0fc863b236dca8e22e4279b3322f Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 03:51:22 +0100
Subject: [PATCH 0257/2085] contributors: refactor contributors file from
 markdown to restructuredtext

Signed-off-by: perigoso <perigoso@riseup.net>
---
 CONTRIBUTORS.md  |  97 -------------------------
 CONTRIBUTORS.rst | 180 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 180 insertions(+), 97 deletions(-)
 delete mode 100644 CONTRIBUTORS.md
 create mode 100644 CONTRIBUTORS.rst

diff --git a/CONTRIBUTORS.md b/CONTRIBUTORS.md
deleted file mode 100644
index 5fa3e5250..000000000
--- a/CONTRIBUTORS.md
+++ /dev/null
@@ -1,97 +0,0 @@
-# TinyUSB contributors (sorted alphabetically)
-
-- **[Adafruit Team](https://github.com/adafruit)**
-  - Main supporter and sponsor for hardware boards and kits
-  - Discussion and suggestion for feature and improvement
-  - Design the project logo
-
-- **[Ha Thach](https://github.com/hathach)**
-  - *Author and maintainer*
-  - Most features development
-
-- **[Hristo Gochkov](https://github.com/me-no-dev)**
-  - Improve ESP32s2 DCD
-
-- **[Jan Dümpelmann](https://github.com/duempel)**
-  - Improve transfer performance for Synopsys DCD for STM32 MCUs
-
-- **[Jeff Epler](https://github.com/jepler)**
-  - Improve MIDI class driver
-
-- **[Jerzy Kasenberg](https://github.com/kasjer)**
-  - Add new DCD port for **Dialog DA1469x**
-  - Add new class driver for **Bluetooth HCI**
-  - Add ISO transfer for STM32 Synopsys, Nordic nRF, Dialog DA1469x
-  - Improve Audio driver and add uac2_headset example
-  - Improve STM32 Synopsys DCD with various PRs
-
-- **[J McCarthy](https://github.com/xmos-jmccarthy)**
-  - Add new DFU 1.1 class driver
-  - Add new example for dfu
-
-- **[Kamil Tomaszewski](https://github.com/kamtom480)**
-  - Add new DCD port for **Sony CXD56** (spresnese board)
-
-- **[Kay Sievers](https://github.com/kaysievers)**
-  - Improve MIDI driver with packet API
-
-- **[Koji KITAYAMA](https://github.com/kkitayam)**
-  - Add new DCD port for **NXP Kinetis KL25**
-  - Add new DCD port for **Renesas RX63n** with GR-CITRUS board
-
-- **[Nathan Conrad](https://github.com/pigrew)**
-  - Add new DCD port for **STM32 fsdev** Fullspeed device for STM32 L0, F0, F1, F3 etc ...
-  - Add new class driver for **USB Test and Measurement Class (USBTMC)**
-  - Various improvement e.g Zero-length packet, Lint setup
-  - Board support for STM32F070RB Nucleo, STM32F303 Discovery
-
-- **[Peter Lawrence](https://github.com/majbthrd)**
-  - Add new DCD port for **Nuvoton NUC 120, 121, 125, 126, 505**
-  - Add new class driver for **USBNET RNDIS, CDC-ECM**
-  - Add *net_lwip_webserver* example for demonstration of usbnet with lwip
-  - Board support for NuTiny NUC120, NUC121s, NUC125s, NUC126V, NUC505
-  - Improve multiple cdc interfaces API & add cdc_dual_ports example
-
-- **[Rafael Silva](https://github.com/perigoso)**
-  - Add new DCD port for **Silabs EFM32GG12** with SLTB009A board
-
-- **[Raspberry Pi Team](https://github.com/raspberrypi)**
-  - Add new DCD port for **Raspberry Pi RP2040**
-  - Add new HCD port for **Raspberry Pi RP2040**
-
-- **[Reinhard Panhuber](https://github.com/PanRe)**
-  - Add new class driver for **USB Audio Class 2.0 (UAC2)**
-  - Rework tu_fifo with unmasked pointer, add DMA support, and constant address support
-  - Add new DCD/USBD edpt_xfer_fifo() API for optimizing endpoint transfer
-  - Add and greatly improve Isochronous transfer
-  - Add new audio examples: audio_test and audio_4_channel_mic
-
-- **[Scott Shawcroft](https://github.com/tannewt)**
-  - Add new DCD port for **SAMD21 and SAMD51**
-  - Add new class driver for **Musical Instrument Digital Interface (MIDI)**
-  - Improve USBD control transfer, MSC, CDC class driver
-  - Board support for Metro M0 & M4 express
-  - Write the excellent porting.md documentation
-  - Add initial Makefile
-
-- **[Sean Cross](https://github.com/xobs)**
-  - Add new DCD port for **ValentyUSB eptri** (fomu board)
-
-- **[Sylvain "tnt" Munaut](https://github.com/smunaut)**
-  - Add new class driver for DFU Runtime
-
-- **[Timon Skerutsch](https://github.com/PTS93)**
-  - Add hid_test.js script and extensive test for bi-directional raw HID
-
-- **[Tod E. Kurt](https://github.com/todbot)**
-  - Add hid_test.js script and extensive test for bi-directional raw HID
-
-- **[Uwe Bonnes](https://github.com/UweBonnes)**
-  - Improve STM32 Synopsys highspeed DCD
-
-- **[William D. Jones](https://github.com/cr1901)**
-  - Add new DCD port for **Synopsys DesignWare** for STM32 L4, F2, F4, F7, H7 etc ...
-  - Add new DCD port for **TI MSP430**
-  - Board support for STM32F407 Discovery, STM32H743 Nucleo, pyboard v1.1, msp_exp430f5529lp etc ...
-
-**[Full contributors list](https://github.com/hathach/tinyusb/contributors).**
diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
new file mode 100644
index 000000000..b1ebb10ef
--- /dev/null
+++ b/CONTRIBUTORS.rst
@@ -0,0 +1,180 @@
+************
+Contributors
+************
+
+Special thanks to all the people who spent their precious time and effort to help this project so far.
+list contributors and their awesome work for the stack:
+
+Notable contributors
+====================
+
+(sorted alphabetically)
+
+`Adafruit Team <https://github.com/adafruit>`__
+-----------------------------------------------
+
+-  Main supporter and sponsor for hardware boards and kits
+-  Discussion and suggestion for feature and improvement
+-  Design the project logo
+
+
+`Ha Thach <https://github.com/hathach>`__
+-----------------------------------------
+
+-  *Author and maintainer*
+-  Most features development
+
+
+`Hristo Gochkov <https://github.com/me-no-dev>`__
+-------------------------------------------------
+
+-  Improve ESP32s2 DCD
+
+
+`Jan Dümpelmann <https://github.com/duempel>`__
+-----------------------------------------------
+
+-  Improve transfer performance for Synopsys DCD for STM32 MCUs
+
+
+`Jeff Epler <https://github.com/jepler>`__
+------------------------------------------
+
+-  Improve MIDI class driver
+
+
+`Jerzy Kasenberg <https://github.com/kasjer>`__
+-----------------------------------------------
+
+-  Add new DCD port for Dialog DA1469x
+-  Add new class driver for Bluetooth HCI
+-  Add ISO transfer for STM32 Synopsys, Nordic nRF, Dialog DA1469x
+-  Improve Audio driver and add uac2\_headset example
+-  Improve STM32 Synopsys DCD with various PRs
+
+
+`J McCarthy <https://github.com/xmos-jmccarthy>`__
+--------------------------------------------------
+
+-  Add new DFU 1.1 class driver
+-  Add new example for dfu
+
+
+`Kamil Tomaszewski <https://github.com/kamtom480>`__
+----------------------------------------------------
+
+-  Add new DCD port for Sony CXD56 (spresnese board)
+
+
+`Kay Sievers <https://github.com/kaysievers>`__
+-----------------------------------------------
+
+-  Improve MIDI driver with packet API
+
+
+`Koji KITAYAMA <https://github.com/kkitayam>`__
+-----------------------------------------------
+
+-  Add new DCD port for NXP Kinetis KL25
+-  Add new DCD port for Renesas RX63n with GR-CITRUS board
+
+
+`Nathan Conrad <https://github.com/pigrew>`__
+---------------------------------------------
+
+-  Add new DCD port for STM32 fsdev Fullspeed device for STM32 L0,
+   F0, F1, F3 etc ...
+-  Add new class driver for USB Test and Measurement Class (USBTMC)
+-  Various improvement e.g Zero-length packet, Lint setup
+-  Board support for STM32F070RB Nucleo, STM32F303 Discovery
+
+
+`Peter Lawrence <https://github.com/majbthrd>`__
+------------------------------------------------
+
+-  Add new DCD port for Nuvoton NUC 120, 121, 125, 126, 505
+-  Add new class driver for USBNET RNDIS, CDC-ECM
+-  Add *net\_lwip\_webserver* example for demonstration of usbnet with
+   lwip
+-  Board support for NuTiny NUC120, NUC121s, NUC125s, NUC126V, NUC505
+-  Improve multiple cdc interfaces API & add cdc\_dual\_ports example
+
+
+`Rafael Silva <https://github.com/perigoso>`__
+----------------------------------------------
+
+-  Add new DCD port for Silabs EFM32GG12 with SLTB009A board
+
+
+`Raspberry Pi Team <https://github.com/raspberrypi>`__
+------------------------------------------------------
+
+-  Add new DCD port for Raspberry Pi RP2040
+-  Add new HCD port for Raspberry Pi RP2040
+
+
+`Reinhard Panhuber <https://github.com/PanRe>`__
+------------------------------------------------
+
+-  Add new class driver for USB Audio Class 2.0 (UAC2)
+-  Rework tu\_fifo with unmasked pointer, add DMA support, and constant
+   address support
+-  Add new DCD/USBD edpt\_xfer\_fifo() API for optimizing endpoint
+   transfer
+-  Add and greatly improve Isochronous transfer
+-  Add new audio examples: audio\_test and audio\_4\_channel\_mic
+
+
+`Scott Shawcroft <https://github.com/tannewt>`__
+------------------------------------------------
+
+-  Add new DCD port for SAMD21 and SAMD51
+-  Add new class driver for Musical Instrument Digital Interface
+   (MIDI)
+-  Improve USBD control transfer, MSC, CDC class driver
+-  Board support for Metro M0 & M4 express
+-  Write the excellent porting.md documentation
+-  Add initial Makefile
+
+`Sean Cross <https://github.com/xobs>`__
+----------------------------------------
+
+-  Add new DCD port for ValentyUSB eptri (fomu board)
+
+
+`Sylvain "tnt" Munaut <https://github.com/smunaut>`__
+-----------------------------------------------------
+
+-  Add new class driver for DFU Runtime
+
+
+`Timon Skerutsch <https://github.com/PTS93>`__
+----------------------------------------------
+
+-  Add hid\_test.js script and extensive test for bi-directional raw HID
+
+
+`Tod E. Kurt <https://github.com/todbot>`__
+-------------------------------------------
+
+-  Add hid\_test.js script and extensive test for bi-directional raw HID
+
+
+`Uwe Bonnes <https://github.com/UweBonnes>`__
+---------------------------------------------
+
+-  Improve STM32 Synopsys highspeed DCD
+
+
+`William D. Jones <https://github.com/cr1901>`__
+------------------------------------------------
+
+-  Add new DCD port for Synopsys DesignWare for STM32 L4, F2, F4,
+   F7, H7 etc ...
+-  Add new DCD port for TI MSP430
+-  Board support for STM32F407 Discovery, STM32H743 Nucleo, pyboard
+   v1.1, msp\_exp430f5529lp etc ...
+
+
+`Full contributors list <https://github.com/hathach/tinyusb/contributors>`__
+============================================================================

From c4c0c987e8abcd3f76d0f2281346a739e5a38347 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 03:52:27 +0100
Subject: [PATCH 0258/2085] docs: symbolic link contributors file for use in
 documentation

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/contributing/contributors.rst | 1 +
 1 file changed, 1 insertion(+)
 create mode 120000 docs/contributing/contributors.rst

diff --git a/docs/contributing/contributors.rst b/docs/contributing/contributors.rst
new file mode 120000
index 000000000..b3748ccb5
--- /dev/null
+++ b/docs/contributing/contributors.rst
@@ -0,0 +1 @@
+../../CONTRIBUTORS.rst
\ No newline at end of file

From a8c9d999c7ede0810fe8b945fd89fa265a64bc83 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 03:53:02 +0100
Subject: [PATCH 0259/2085] code_of_conduct: refactor file from markdown to
 restructuredtext

Signed-off-by: perigoso <perigoso@riseup.net>
---
 CODE_OF_CONDUCT.md  | 76 ---------------------------------------
 CODE_OF_CONDUCT.rst | 88 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 88 insertions(+), 76 deletions(-)
 delete mode 100644 CODE_OF_CONDUCT.md
 create mode 100644 CODE_OF_CONDUCT.rst

diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md
deleted file mode 100644
index 0da6ff68e..000000000
--- a/CODE_OF_CONDUCT.md
+++ /dev/null
@@ -1,76 +0,0 @@
-# Contributor Covenant Code of Conduct
-
-## Our Pledge
-
-In the interest of fostering an open and welcoming environment, we as
-contributors and maintainers pledge to making participation in our project and
-our community a harassment-free experience for everyone, regardless of age, body
-size, disability, ethnicity, sex characteristics, gender identity and expression,
-level of experience, education, socio-economic status, nationality, personal
-appearance, race, religion, or sexual identity and orientation.
-
-## Our Standards
-
-Examples of behavior that contributes to creating a positive environment
-include:
-
-* Using welcoming and inclusive language
-* Being respectful of differing viewpoints and experiences
-* Gracefully accepting constructive criticism
-* Focusing on what is best for the community
-* Showing empathy towards other community members
-
-Examples of unacceptable behavior by participants include:
-
-* The use of sexualized language or imagery and unwelcome sexual attention or
- advances
-* Trolling, insulting/derogatory comments, and personal or political attacks
-* Public or private harassment
-* Publishing others' private information, such as a physical or electronic
- address, without explicit permission
-* Other conduct which could reasonably be considered inappropriate in a
- professional setting
-
-## Our Responsibilities
-
-Project maintainers are responsible for clarifying the standards of acceptable
-behavior and are expected to take appropriate and fair corrective action in
-response to any instances of unacceptable behavior.
-
-Project maintainers have the right and responsibility to remove, edit, or
-reject comments, commits, code, wiki edits, issues, and other contributions
-that are not aligned to this Code of Conduct, or to ban temporarily or
-permanently any contributor for other behaviors that they deem inappropriate,
-threatening, offensive, or harmful.
-
-## Scope
-
-This Code of Conduct applies both within project spaces and in public spaces
-when an individual is representing the project or its community. Examples of
-representing a project or community include using an official project e-mail
-address, posting via an official social media account, or acting as an appointed
-representative at an online or offline event. Representation of a project may be
-further defined and clarified by project maintainers.
-
-## Enforcement
-
-Instances of abusive, harassing, or otherwise unacceptable behavior may be
-reported by contacting the project team at thach@tinyusb.org. All
-complaints will be reviewed and investigated and will result in a response that
-is deemed necessary and appropriate to the circumstances. The project team is
-obligated to maintain confidentiality with regard to the reporter of an incident.
-Further details of specific enforcement policies may be posted separately.
-
-Project maintainers who do not follow or enforce the Code of Conduct in good
-faith may face temporary or permanent repercussions as determined by other
-members of the project's leadership.
-
-## Attribution
-
-This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4,
-available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html
-
-[homepage]: https://www.contributor-covenant.org
-
-For answers to common questions about this code of conduct, see
-https://www.contributor-covenant.org/faq
diff --git a/CODE_OF_CONDUCT.rst b/CODE_OF_CONDUCT.rst
new file mode 100644
index 000000000..4035c528f
--- /dev/null
+++ b/CODE_OF_CONDUCT.rst
@@ -0,0 +1,88 @@
+***************
+Code of Conduct
+***************
+
+Our Pledge
+----------
+
+In the interest of fostering an open and welcoming environment, we as
+contributors and maintainers pledge to making participation in our
+project and our community a harassment-free experience for everyone,
+regardless of age, body size, disability, ethnicity, sex
+characteristics, gender identity and expression, level of experience,
+education, socio-economic status, nationality, personal appearance,
+race, religion, or sexual identity and orientation.
+
+Our Standards
+-------------
+
+Examples of behavior that contributes to creating a positive environment
+include:
+
+-  Using welcoming and inclusive language
+-  Being respectful of differing viewpoints and experiences
+-  Gracefully accepting constructive criticism
+-  Focusing on what is best for the community
+-  Showing empathy towards other community members
+
+Examples of unacceptable behavior by participants include:
+
+-  The use of sexualized language or imagery and unwelcome sexual
+   attention or advances
+-  Trolling, insulting/derogatory comments, and personal or political
+   attacks
+-  Public or private harassment
+-  Publishing others' private information, such as a physical or
+   electronic address, without explicit permission
+-  Other conduct which could reasonably be considered inappropriate in a
+   professional setting
+
+Our Responsibilities
+--------------------
+
+Project maintainers are responsible for clarifying the standards of
+acceptable behavior and are expected to take appropriate and fair
+corrective action in response to any instances of unacceptable behavior.
+
+Project maintainers have the right and responsibility to remove, edit,
+or reject comments, commits, code, wiki edits, issues, and other
+contributions that are not aligned to this Code of Conduct, or to ban
+temporarily or permanently any contributor for other behaviors that they
+deem inappropriate, threatening, offensive, or harmful.
+
+Scope
+-----
+
+This Code of Conduct applies both within project spaces and in public
+spaces when an individual is representing the project or its community.
+Examples of representing a project or community include using an
+official project e-mail address, posting via an official social media
+account, or acting as an appointed representative at an online or
+offline event. Representation of a project may be further defined and
+clarified by project maintainers.
+
+Enforcement
+-----------
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may
+be reported by contacting the project team at thach@tinyusb.org. All
+complaints will be reviewed and investigated and will result in a
+response that is deemed necessary and appropriate to the circumstances.
+The project team is obligated to maintain confidentiality with regard to
+the reporter of an incident. Further details of specific enforcement
+policies may be posted separately.
+
+Project maintainers who do not follow or enforce the Code of Conduct in
+good faith may face temporary or permanent repercussions as determined
+by other members of the project's leadership.
+
+Attribution
+-----------
+
+This Code of Conduct is adapted from the `Contributor
+Covenant <https://www.contributor-covenant.org>`__, version 1.4,
+available at
+https://www.contributor-covenant.org/version/1/4/code-of-conduct.html
+
+For answers to common questions about this code of conduct, see
+https://www.contributor-covenant.org/faq

From d9518eb33726db13d76ffcd5d6ff4af625eef174 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 03:53:33 +0100
Subject: [PATCH 0260/2085] docs: symbolic link to code of conduct file for use
 in documentation

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/contributing/code_of_conduct.rst | 1 +
 1 file changed, 1 insertion(+)
 create mode 120000 docs/contributing/code_of_conduct.rst

diff --git a/docs/contributing/code_of_conduct.rst b/docs/contributing/code_of_conduct.rst
new file mode 120000
index 000000000..b52bf14c5
--- /dev/null
+++ b/docs/contributing/code_of_conduct.rst
@@ -0,0 +1 @@
+../../CODE_OF_CONDUCT.rst
\ No newline at end of file

From 883040e88eb22071b316d53eda6fdde13adda6ab Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 03:54:13 +0100
Subject: [PATCH 0261/2085] changelog: create changelog file and import from
 release

Signed-off-by: perigoso <perigoso@riseup.net>
---
 CHANGELOG.rst | 513 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 513 insertions(+)
 create mode 100644 CHANGELOG.rst

diff --git a/CHANGELOG.rst b/CHANGELOG.rst
new file mode 100644
index 000000000..80205a721
--- /dev/null
+++ b/CHANGELOG.rst
@@ -0,0 +1,513 @@
+*********
+Changelog
+*********
+
+0.10.1 (03-06-221)
+===================
+
+-  rework rp2040 examples and CMake build, allow better integration with pico-sdk
+
+Host Controller Driver (HCD)
+----------------------------
+
+-  Fix rp2040 host driver: incorrect PID with low speed device with max packet size of 8 bytes
+-  Improve hub driver
+-  Remove obsolete hcd_pipe_queue_xfer()/hcd_pipe_xfer()
+-  Use hcd_frame_number() instead of micro frame
+-  Fix OHCI endpoint address and xferred_bytes in xfer complete event
+
+
+0.10.0 (28-05-2021)
+===================
+
+-  Rework tu_fifo_t with separated mutex for read and write, better support DMA with read/write buffer info. And constant address mode
+-  Improve audio_test example and add audio_4_channel_mic example
+-  Add new dfu example
+-  Remove pico-sdk from submodule
+
+Device Controller Driver (DCD)
+------------------------------
+
+-  Add new DCD port for Silabs EFM32GG12 with board Thunderboard Kit (SLTB009A)
+-  Add new DCD port Renesas RX63N, board GR-CITRUS
+-  Add new (optional) endpoint API dcd_edpt_xfer_fifo
+-  Fix build with nRF5340
+-  Fix build with lpc15 and lpc54
+-  Fix build with lpc177x_8x
+-  STM32 Synopsys: greatly improve Isochronous transfer with edpt_xfer_fifo API
+-  Support LPC55 port1 highspeed
+-  Add support for Espressif esp32s3
+-  nRF: fix race condition that could cause drop packet of Bulk OUT transfer
+
+USB Device Driver (USBD)
+------------------------
+
+-  Add new (optional) endpoint ADPI usbd_edpt_xfer_fifo
+
+Device Class Driver
+-------------------
+
+CDC
+
+-  [Breaking] tud_cdc_peek(), tud_vendor_peek() no longer support random offset and dropped position parameter.
+
+DFU
+
+-  Add new DFU 1.1 class driver (WIP)
+
+HID
+
+-  Fix keyboard report descriptor template
+-  Add more hid keys constant from 0x6B to 0xA4
+-  [Breaking] rename API
+   -  HID_PROTOCOL_NONE/KEYBOARD/MOUST to HID_ITF_PROTOCOL_NONE/KEYBOARD/MOUSE
+   -  tud_hid_boot_mode() to tud_hid_get_protocol()
+   -  tud_hid_boot_mode_cb() to tud_hid_set_protocol_cb()
+
+MIDI
+
+-  Fix MIDI buffer overflow issue
+-  [Breaking] rename API
+   -  Rename tud_midi_read() to tud_midi_stream_read()
+   -  Rename tud_midi_write() to tud_midi_stream_write()
+   -  Rename tud_midi_receive() to tud_midi_packet_read()
+   -  Rename tud_midi_send() to tud_midi_packet_write()
+
+Host Controller Driver (HCD)
+----------------------------
+
+-  No noticable changes
+
+USB Host Driver (USBH)
+----------------------
+
+-  No noticable changes
+
+Host Class Driver
+-----------------
+
+-  HID: Rework host hid driver, basically everything changes
+
+
+0.9.0 (12-03-2021)
+==================
+
+Device Stack
+------------
+
+Device Controller Driver (DCD)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+RP2040
+
+-  Fix endpoint buffer reallocation overrun problem
+-  Fix osal_pico queue overflow in initialization
+-  Fix Isochronous endpoint buffer size in transfer
+-  Optimize hardware endpoint struct to reduce RAM usage
+-  Fix enum walkaround forever check for SE0 when pull up is disabled
+
+Sony CXD56
+
+-  Pass the correct speed on Spresense
+-  Fix setup processed flag
+
+NXP Transdimention
+
+-  Update dcd_init() to reset controller to device mode
+
+USB Device Driver (USBD)
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+-  Fix issue with status zlp (tud_control_status) is returned by class driver with SET/CLEAR_FEATURE for endpoint.
+-  Correct endpoint size check for fullspeed bulk, can be 8, 16, 32, 64
+-  Ack SET_INTERFACE even if it is not implemented by class driver.
+
+Device Class Driver
+^^^^^^^^^^^^^^^^^^^
+
+DFU Runtime
+
+-  rename dfu_rt to dfu_runtime for easy reading
+
+CDC
+
+-  Add tud_cdc_send_break_cb() to support break request
+-  Improve CDC receive, minor behavior changes: when tud_cdc_rx_wanted_cb() is invoked wanted_char may not be the last byte in the fifo
+
+HID
+
+-  [Breaking] Add itf argument to hid API to support multiple instances, follow API has signature changes
+   -  tud_hid_descriptor_report_cb()
+   -  tud_hid_get_report_cb()
+   -  tud_hid_set_report_cb()
+   -  tud_hid_boot_mode_cb()
+   -  tud_hid_set_idle_cb()
+-  Add report complete callback tud_hid_report_complete_cb() API
+-  Add DPad/Hat support for HID Gamepad
+   -  `TUD_HID_REPORT_DESC_GAMEPAD()` now support 16 buttons, 2 joysticks, 1 hat/dpad
+   -  Add hid_gamepad_report_t along with `GAMEPAD_BUTTON_` and `GAMEPAD_HAT_` enum
+   -  Add Gamepad to hid_composite / hid_composite_freertos example
+
+MIDI
+
+-  Fix dropping MIDI sysex message when fifo is full
+-  Fix typo in tud_midi_write24(), make example less ambigous for cable and channel
+-  Fix incorrect endpoint descriptor length, MIDI v1 use Audio v1 which has 9-byte endpoint descriptor (instead of 7)
+
+Host Stack
+----------
+
+Host Controller Driver (HCD)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+-  Add rhport to hcd_init()
+-  Improve EHCI/OHCI driver abstraction
+   -  Move echi/ohci files to portable/
+   -  Rename hcd_lpc18_43 to hcd_transdimension
+   -  Sub hcd API with hcd_ehci_init(), hcd_ehci_register_addr()
+-  Update NXP transdimention hcd_init() to reset controller to host mode
+   -  Ported hcd to rt10xx
+
+USB Host Driver (USBH)
+^^^^^^^^^^^^^^^^^^^^^^
+
+-  No noticeable changes to usbh
+
+Host Class Driver
+^^^^^^^^^^^^^^^^^
+
+MSC
+
+-  Rename tuh_msc_scsi_inquiry() to tuh_msc_inquiry()
+-  Rename tuh_msc_mounted_cb/tuh_msc_unmounted_cb to tuh_msc_mount_cb/tuh_msc_unmount_cb to match device stack naming
+-  Change tuh_msc_is_busy() to tuh_msc_ready()
+-  Add read10 and write10 function: tuh_msc_read10(), tuh_msc_write10()
+-  Read_Capacity is invoked as part of enumeration process
+-  Add tuh_msc_get_block_count(), tuh_msc_get_block_size()
+-  Add CFG_TUH_MSC_MAXLUN (default to 4) to hold lun capacities
+
+Others
+------
+
+-  Add basic support for rt-thread OS
+-  Change zero bitfield length to more explicit padding
+-  Build example now fetch required submodules on the fly while running `make` without prio submodule init for mcu drivers
+-  Update pico-sdk to v1.1.0
+
+**New Boards**
+
+-  Microchip SAM E54 Xplained Pro
+-  LPCXpresso 55s28
+-  LPCXpresso 18s37
+
+
+0.8.0 (05-02-2021)
+==================
+
+Device Controller Driver
+------------------------
+
+-  Added new device support for Raspberry Pi RP2040
+-  Added new device support for NXP Kinetis KL25ZXX
+-  Use dcd_event_bus_reset() with link speed to replace bus_signal
+-  ESP32-S2:
+   -  Add bus suspend and wakeup support
+-  SAMD21:
+   -  Fix (walkaround) samd21 setup_packet overflow by USB DMA
+-  STM32 Synopsys:
+   -  Rework USB FIFO allocation scheme and allow RX FIFO size reduction
+-  Sony CXD56
+   -  Update Update Spresense SDK to 2.0.2
+   -  Fix dcd issues with setup packets
+   -  Correct EP number for cdc_msc example
+
+USB Device
+----------
+
+**USBD**
+
+-  Rework usbd control transfer to have additional stage parameter for setup, data, status
+-  Fix tusb_init() return true instead of TUSB_ERROR_NONE
+-  Added new API tud_connected() that return true after device got out of bus reset and received the very first setup packet
+
+**Class Driver**
+
+-  CDC
+   -  Allow to transmit data, even if the host does not support control line states i.e set DTR
+-  HID
+   -  change default CFG_TUD_HID_EP_BUFSIZE from 16 to 64
+-  MIDI
+   -  Fix midi sysex sending bug
+-  MSC
+   -  Invoke only scsi complete callback after status transaction is complete.
+   -  Fix scsi_mode_sense6_t padding, which cause IAR compiler internal error.
+-  USBTMC
+   -  Change interrupt endpoint example size to 8 instead of 2 for better compatibility with mcu
+
+**Example**
+
+-  Support make from windows cmd.exe
+-  Add HID Consumer Control (media keys) to hid_composite & hid_composite_freertos examples
+
+
+USB Host
+--------
+
+No noticeable changes to host stack
+
+New Boards
+----------
+
+-  NXP/Freescale Freedom FRDM-KL25Z
+-  Feather Double M33 express
+-  Raspberry Pi Pico
+-  Adafruit Feather RP2040
+-  Adafruit Itsy Bitsy RP2040
+-  Adafruit QT RP2040
+-  Adfruit Feather ESP32-S2
+-  Adafruit Magtag 29" Eink
+-  Adafruit Metro ESP32-S2
+-  Adafruit PyBadge
+-  Adafruit PyPortal
+-  Great Scott Gadgets' LUNA D11 & D21
+
+
+0.7.0 (08-11-2020)
+==================
+
+Device Controller Driver
+------------------------
+
+-  Added new support for Espressif ESP32-S2
+-  Added new support for Dialog DA1469x
+-  Enhance STM32 Synopsys
+-  Support bus events disconnection/suspend/resume/wakeup
+   -  Improve transfer performance with optimizing xfer and fifo size
+   -  Support Highspeed port (OTG_HS) with both internal and external PHY
+   -  Support multiple usb ports with rhport=1 is highspeed on selected MCUs e.g H743, F23. It is possible to have OTG_HS to run on Fullspeed PHY (e.g lacking external PHY)
+   -  Add ISO transfer, fix odd/even frame
+   -  Fix FIFO flush during stall
+   -  Implement dcd_edpt_close() API
+   -  Support F105, F107
+-  Enhance STM32 fsdev
+   -  Improve dcd fifo allocation
+   -  Fix ISTR race condition
+   -  Support remap USB IRQ on supported MCUs
+   -  Implement dcd_edpt_close() API
+-  Enhance NUC 505: enhance set configure behavior
+-  Enhance SAMD
+   -  Fix race condition with setup packet
+   -  Add SAMD11 option `OPT_MCU_SAMD11`
+   -  Add SAME5x option `OPT_MCU_SAME5X`
+-  Fix SAMG control data toggle and stall race condition
+-  Enhance nRF
+   -  Fix hanged when tud_task() is called within critical section (disabled interrupt)
+   -  Fix disconnect bus event not submitted
+   -  Implement ISO transfer and dcd_edpt_close()
+
+
+USB Device
+----------
+
+**USBD**
+
+-  Add new class driver for **Bluetooth HCI** class driver with example can be found in [mynewt-tinyusb-example](https://github.com/hathach/mynewt-tinyusb-example) since it needs mynewt OS to run with.
+-  Fix USBD endpoint usage racing condition with `usbd_edpt_claim()/usbd_edpt_release()`
+-  Added `tud_task_event_ready()` and `osal_queue_empty()`. This API is needed to check before enter low power mode with WFI/WFE
+-  Rename USB IRQ Handler to `dcd_int_handler()`. Application must define IRQ handler in which it calls this API.
+-  Add `dcd_connect()` and `dcd_disconnect()` to enable/disable internal pullup on D+/D-  on supported MCUs.
+-  Add `usbd_edpt_open()`
+-  Remove `dcd_set_config()`
+-  Add *OPT_OS_CUMSTOM* as hook for application to overwrite and/or add their own OS implementation
+-  Support SET_INTERFACE, GET_INTERFACE request
+-  Add Logging for debug with optional uart/rtt/swo printf retarget or `CFG_TUSB_DEBUG_PRINTF` hook
+-  Add IAR compiler support
+-  Support multiple configuration descriptors. `TUD_CONFIG_DESCRIPTOR()` template has extra config_num as 1st argument
+-  Improve USB Highspeed support with actual link speed detection with `dcd_event_bus_reset()`
+-  Enhance class driver management
+   -  `usbd_driver_open()` add max length argument, and return length of interface (0 for not supported). Return value is used for finding appropriate driver
+   -  Add application implemented class driver via `usbd_app_driver_get_cb()`
+   -  IAD is handled to assign driver id
+-  Added `tud_descriptor_device_qualifier_cb()` callback
+-  Optimize `tu_fifo` bulk write/read transfer
+-  Forward non-std control request to class driver
+-  Let application handle Microsoft OS 1.0 Descriptors (the 0xEE index string)
+-  Fix OSAL FreeRTOS yield from ISR
+
+**Class Drivers**
+
+-  USBNET: remove ACM-EEM due to lack of support from host
+-  USBTMC: fix descriptors when INT EP is disabled
+-  CDC:
+   -  Send zero length packet for end of data when needed
+   -  Add `tud_cdc_tx_complete_cb()` callback
+   -  Change tud_cdc_n_write_flush() return number of bytes forced to transfer, and flush when writing enough data to fifo
+-  MIDI:
+   -  Add packet interface
+   -  Add multiple jack descriptors
+   -  Fix MIDI driver for sysex
+-  DFU Runtime: fix response to SET_INTERFACE and DFU_GETSTATUS request
+-  Rename some configure macro to make it clear that those are used directly for endpoint transfer
+   -  CFG_TUD_HID_BUFSIZE to CFG_TUD_HID_EP_BUFSIZE
+   -  CFG_TUD_CDC_EPSIZE to CFG_TUD_CDC_EP_BUFSIZE
+   -  CFG_TUD_MSC_BUFSIZE to CFG_TUD_MSC_EP_BUFSIZE
+   -  CFG_TUD_MIDI_EPSIZE to CFG_TUD_MIDI_EP_BUFSIZE
+-  HID:
+   -  Fix gamepad template descriptor
+   -  Add multiple HID interface API
+   -  Add extra comma to HID_REPORT_ID
+
+USB Host
+--------
+
+-  Rework USB host stack (still work in progress)
+   -  Fix compile error with pipehandle
+   -  Rework usbh control and enumeration as non-blocking
+-  Improve Hub, MSC, HID host driver
+
+Examples
+--------
+
+-  Add new hid_composite_freertos
+-  Add new dynamic_configuration to demonstrate how to switch configuration descriptors
+-  Add new hid_multiple_interface
+-  Enhance `net_lwip_webserver` example
+   -  Add multiple configuration: RNDIS for Windows, CDC-ECM for macOS (Linux will work with both)
+   -  Update lwip to STABLE-2_1_2_RELEASE for net_lwip_webserver
+-  Added new Audio example: audio_test uac2_headsest
+
+New Boards
+----------
+
+-  Espressif ESP32-S2: saola_1, kaluga_1
+-  STM32: F746 Nucleo, H743 Eval, H743 Nucleo, F723 discovery, stlink v3 mini, STM32L4r5 Nucleo
+-  Dialog DA1469x dk pro and dk usb
+-  Microchip: Great Scoot Gadgets' LUNA, samd11_xplained, D5035-01, atsamd21 xplained pro
+-  nRF: ItsyBitsy nRF52840
+
+
+0.6.0 (30-03-2020)
+==================
+
+Added **CONTRIBUTORS.md** to give proper credit for contributors to the stack. Special thanks to `Nathan Conrad <https://github.com/pigrew>`__ , `Peter Lawrence <https://github.com/majbthrd>`__ , `William D. Jones <https://github.com/cr1901>`__ and `Sean Cross <https://github.com/xobs>`__ and others for spending their precious time to add lots of features and ports for this release.
+
+Added
+-----
+
+**MCU**
+
+-  Added support for Microchip SAMG55
+-  Added support for Nordic nRF52833
+-  Added support for Nuvoton: NUC120, NUC121/NUC125, NUC126, NUC505
+-  Added support for NXP LPC: 51Uxx, 54xxx, 55xx
+-  Added support for NXP iMXRT: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
+-  Added support for Sony CXD56 (Spresense)
+-  Added support for STM32: L0, F0, F1, F2, F3, F4, F7, H7
+-  Added support for TI MSP430
+-  Added support for ValentyUSB's eptri
+
+**Class Driver**
+
+-  Added DFU Runtime class driver
+-  Added Network class driver with RNDIS, CDC-ECM, CDC-EEM (work in progress)
+-  Added USBTMC class driver
+-  Added WebUSB class driver using vendor-specific class
+-  Added multiple instances support for CDC and MIDI
+-  Added a handful of unit test with Ceedling.
+-  Added LOG support for debugging with CFG_TUSB_DEBUG
+-  Added `tud_descriptor_bos_cb()` for BOS descriptor (required for USB 2.1)
+-  Added `dcd_edpt0_status_complete()` as optional API for DCD
+
+**Examples**
+
+Following examples are added:
+
+-  board_test
+-  cdc_dual_ports
+-  dfu_rt
+-  hid_composite
+-  net_lwip_webserver
+-  usbtmc
+-  webusb_serial
+
+**Boards**
+
+Following boards are added:
+
+-  adafruit_clue
+-  arduino_nano33_ble
+-  circuitplayground_bluefruit
+-  circuitplayground_express
+-  feather_m0_express
+-  feather_nrf52840_sense
+-  feather_stm32f405
+-  fomu
+-  itsybitsy_m0
+-  itsybitsy_m4
+-  lpcxpresso11u37
+-  lpcxpresso1549
+-  lpcxpresso51u68
+-  lpcxpresso54114
+-  lpcxpresso55s69
+-  mbed1768
+-  mimxrt1010_evk
+-  mimxrt1015_evk
+-  mimxrt1020_evk
+-  mimxrt1050_evkb
+-  mimxrt1060_evk
+-  mimxrt1064_evk
+-  msp_exp430f5529lp
+-  ngx4330
+-  nrf52840_mdk_dongle
+-  nutiny_nuc121s
+-  nutiny_nuc125s
+-  nutiny_nuc126v
+-  nutiny_sdk_nuc120
+-  nutiny_sdk_nuc505
+-  pca10059
+-  pca10100
+-  pyboardv11
+-  raytac_mdbt50q_rx
+-  samg55xplained
+-  seeeduino_xiao
+-  spresense
+-  stm32f070rbnucleo
+-  stm32f072disco
+-  stm32f103bluepill
+-  stm32f207nucleo
+-  stm32f401blackpill
+-  stm32f411blackpill
+-  stm32f411disco
+-  stm32f412disco
+-  stm32f767nucleo
+-  stm32h743nucleo
+-  stm32l0538disco
+-  stm32l476disco
+-  teensy_40
+
+Changed
+-------
+
+-  Changed `tud_descriptor_string_cb()` to have additional Language ID argument
+-  Merged hal_nrf5x.c into dcd_nrf5x.c
+-  Merged dcd_samd21.c and dcd_samd51.c into dcd_samd.c
+-  Generalized dcd_stm32f4.c to dcd_synopsys.c
+-  Changed cdc_msc_hid to cdc_msc (drop hid) due to limited endpoints number of some MCUs
+-  Improved DCD SAMD stability, fix missing setup packet occasionally
+-  Improved usbd/usbd_control with proper hanlding of zero-length packet (ZLP)
+-  Improved STM32 DCD FSDev
+-  Improved STM32 DCD Synopsys
+-  Migrated CI from Travis to Github Action
+-  Updated nrfx submodule to 2.1.0
+-  Fixed mynewt osal queue definition
+-  Fixed cdc_msc_freertos example build for all MCUs
+
+
+0.5.0 (06-2019)
+===============
+
+First release, device stack works great, host stack works but still need improvement.
+
+-  Special thanks to @adafruit team, especially @tannewt to help out immensely to rework device stack: simplify osal & control transfer, adding SAMD21/SAMD51 ports, writing porting docs, adding MIDI class support etc...
+-  Thanks to @cr1901 for adding STM32F4 port.
+-  Thanks to @PTS93 and @todbot for HID raw API

From 4fde6a81d9ae07faa5fa6e2cbe9c38c227590a52 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 03:54:38 +0100
Subject: [PATCH 0262/2085] docs: symbolic link to changelog file for use in
 documentation

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/changelog.rst | 1 +
 1 file changed, 1 insertion(+)
 create mode 120000 docs/changelog.rst

diff --git a/docs/changelog.rst b/docs/changelog.rst
new file mode 120000
index 000000000..e22698baf
--- /dev/null
+++ b/docs/changelog.rst
@@ -0,0 +1 @@
+../CHANGELOG.rst
\ No newline at end of file

From 1bbac1c818432b58523d71a775eddfc00e265953 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 14:17:26 +0100
Subject: [PATCH 0263/2085] changelog: move from root to docs subdirectory

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/changelog.rst                       | 1 -
 CHANGELOG.rst => docs/info/changelog.rst | 0
 2 files changed, 1 deletion(-)
 delete mode 120000 docs/changelog.rst
 rename CHANGELOG.rst => docs/info/changelog.rst (100%)

diff --git a/docs/changelog.rst b/docs/changelog.rst
deleted file mode 120000
index e22698baf..000000000
--- a/docs/changelog.rst
+++ /dev/null
@@ -1 +0,0 @@
-../CHANGELOG.rst
\ No newline at end of file
diff --git a/CHANGELOG.rst b/docs/info/changelog.rst
similarity index 100%
rename from CHANGELOG.rst
rename to docs/info/changelog.rst

From 9d3e1aaafc00275d3ad7ba072d6e1721aa3d9df7 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:22:00 +0100
Subject: [PATCH 0264/2085] docs: port concurrency doc to rst

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/reference/concurrency.rst | 42 ++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 docs/reference/concurrency.rst

diff --git a/docs/reference/concurrency.rst b/docs/reference/concurrency.rst
new file mode 100644
index 000000000..776fa4b6d
--- /dev/null
+++ b/docs/reference/concurrency.rst
@@ -0,0 +1,42 @@
+***********
+Concurrency
+***********
+
+The TinyUSB library is designed to operate on single-core MCUs with multi-threaded applications in mind. Interaction with interrupts is especially important to pay attention to.
+It is compatible with optionally using a RTOS.
+
+General
+-------
+
+When writing code, keep in mind that the OS (if using a RTOS) may swap out your code at any time. Also, your code can be preempted by an interrupt at any time.
+
+Application Code
+----------------
+
+The USB core does not execute application callbacks while in an interrupt context. Calls to application code are from within the USB core task context. Note that the application core will call class drivers from within their own task.
+
+Class Drivers
+-------------
+
+Class driver code should never be called from an interrupt context by the USB core, though the application is allowed to call class driver functions from interrupts. USB core functions may be called simultaneously by multiple tasks. Use care that proper locking is used to guard the USBD core functions from this case.
+
+Class drivers are allowed to call ``usbd_*`` functions, but not ``dcd_*`` functions.
+
+USB Core
+--------
+
+All functions that may be called from an (USB core) interrupt context have a ``bool in_isr`` parameter to remind the implementer that special care must be taken.
+
+Interrupt handlers must not directly call class driver code, they must pass a message to the USB core's task.
+
+ ``usbd_*`` functions may be called from interrupts without any notice. They may also be called simultaneously by multiple tasks.
+
+Device Drivers
+--------------
+
+Much of the processing of the USB stack is done in an interrupt context, and care must be taken in order to ensure variables are handled in the appropriate ways by the compiler and optimizer.
+
+In particular:
+
+*  Ensure that all memory-mapped registers (including packet memory) are marked as volatile. GCC's optimizer will even combine memory access (like two 16-bit to be a 32-bit) if you don't mark the pointers as volatile. On some architectures, this can use macros like _I , _O , or _IO.
+*  All defined global variables are marked as  ``static``.

From 106924be9a6cd2cbc8eae3f6c51d335321a9f296 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:22:20 +0100
Subject: [PATCH 0265/2085] docs: port getting started doc to rst

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/reference/getting_started.rst | 153 +++++++++++++++++++++++++++++
 1 file changed, 153 insertions(+)
 create mode 100644 docs/reference/getting_started.rst

diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
new file mode 100644
index 000000000..5f3227927
--- /dev/null
+++ b/docs/reference/getting_started.rst
@@ -0,0 +1,153 @@
+***************
+Getting Started
+***************
+
+Add TinyUSB to your project
+---------------------------
+
+It is relatively simple to incorporate tinyusb to your (existing) project
+
+
+* Copy or ``git submodule`` this repo into your project in a subfolder. Let's say it is *your_project/tinyusb*
+* Add all the .c in the ``tinyusb/src`` folder to your project
+* Add *your_project/tinyusb/src* to your include path. Also make sure your current include path also contains the configuration file tusb_config.h.
+* Make sure all required macros are all defined properly in tusb_config.h (configure file in demo application is sufficient, but you need to add a few more such as CFG_TUSB_MCU, CFG_TUSB_OS since they are passed by IDE/compiler to maintain a unique configure for all boards).
+* If you use the device stack, make sure you have created/modified usb descriptors for your own need. Ultimately you need to implement all **tud descriptor** callbacks for the stack to work.
+* Add tusb_init() call to your reset initialization code.
+* Call ``tud_int_handler()`` (device) and/or ``tuh_int_handler()`` (host) in your USB IRQ Handler
+* Implement all enabled classes's callbacks.
+* If you don't use any RTOSes at all, you need to continuously and/or periodically call tud_task()/tuh_task() function. All of the callbacks and functionality are handled and invoked within the call of that task runner.
+
+.. code-block::
+
+   int main(void)
+   {
+     your_init_code();
+     tusb_init(); // initialize tinyusb stack
+
+     while(1) // the mainloop
+     {
+       your_application_code();
+
+       tud_task(); // device task
+       tuh_task(); // host task
+     }
+   }
+
+Examples
+--------
+
+For your convenience, TinyUSB contains a handful of examples for both host and device with/without RTOS to quickly test the functionality as well as demonstrate how API() should be used. Most examples will work on most of `the supported Boards <boards.md>`_. Firstly we need to ``git clone`` if not already
+
+.. code-block::
+
+   $ git clone https://github.com/hathach/tinyusb tinyusb
+   $ cd tinyusb
+
+Some TinyUSB examples also requires external submodule libraries in ``/lib`` such as FreeRTOS, Lightweight IP to build. Run following command to fetch them 
+
+.. code-block::
+
+   $ git submodule update --init lib
+
+In addition, MCU driver submodule is also needed to provide low-level MCU peripheral's driver. Luckily, it will be fetched if needed when you run the ``make`` to build your board.
+
+Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``/examples/device/99-tinyusb.rules`` file to /etc/udev/rules.d/ then run ``sudo udevadm control --reload-rules && sudo udevadm trigger`` is good enough.
+
+Build
+^^^^^
+
+To build example, first change directory to an example folder. 
+
+.. code-block::
+
+   $ cd examples/device/cdc_msc
+
+Then compile with ``make BOARD=[board_name] all``\ , for example
+
+.. code-block::
+
+   $ make BOARD=feather_nrf52840_express all
+
+Note: ``BOARD`` can be found as directory name in ``hw/bsp``\ , either in its family/boards or directly under bsp (no family).
+
+Port Selection
+~~~~~~~~~~~~~~
+
+If a board has several ports, one port is chosen by default in the individual board.mk file. Use option ``PORT=x`` To choose another port. For example to select the HS port of a STM32F746Disco board, use:
+
+.. code-block::
+
+   $ make BOARD=stm32f746disco PORT=1 all
+
+Port Speed
+~~~~~~~~~~
+
+A MCU can support multiple operational speed. By default, the example build system will use the fastest supported on the board. Use option ``SPEED=full/high`` e.g To force F723 operate at full instead of default high speed
+
+.. code-block::
+
+   $ make BOARD=stm32f746disco SPEED=full all
+
+Debug
+^^^^^
+
+To compile for debugging add ``DEBUG=1``\ , for example
+
+.. code-block::
+
+   $ make BOARD=feather_nrf52840_express DEBUG=1 all
+
+Log
+~~~
+
+Should you have an issue running example and/or submitting an bug report. You could enable TinyUSB built-in debug logging with optional ``LOG=``. LOG=1 will only print out error message, LOG=2 print more information with on-going events. LOG=3 or higher is not used yet. 
+
+.. code-block::
+
+   $ make BOARD=feather_nrf52840_express LOG=2 all
+
+Logger
+~~~~~~
+
+By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols: 
+
+
+* `LOGGER=rtt`: use [Segger RTT protocol](https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/)   
+
+  * Cons: requires jlink as the debugger.
+  * Pros: work with most if not all MCUs
+  * Software viewer is JLink RTT Viewer/Client/Logger which is bundled with JLink driver package.
+
+* ``LOGGER=swo``\ : Use dedicated SWO pin of ARM Cortex SWD debug header.
+
+  * Cons: only work with ARM Cortex MCUs minus M0
+  * Pros: should be compatible with more debugger that support SWO.
+  * Software viewer should be provided along with your debugger driver.
+
+.. code-block::
+
+   $ make BOARD=feather_nrf52840_express LOG=2 LOGGER=rtt all
+   $ make BOARD=feather_nrf52840_express LOG=2 LOGGER=swo all
+
+Flash
+^^^^^
+
+``flash`` target will use the default on-board debugger (jlink/cmsisdap/stlink/dfu) to flash the binary, please install those support software in advance. Some board use bootloader/DFU via serial which is required to pass to make command
+
+.. code-block::
+
+   $ make BOARD=feather_nrf52840_express flash
+   $ make SERIAL=/dev/ttyACM0 BOARD=feather_nrf52840_express flash
+
+Since jlink can be used with most of the boards, there is also ``flash-jlink`` target for your convenience.
+
+.. code-block::
+
+   $ make BOARD=feather_nrf52840_express flash-jlink
+
+Some board use uf2 bootloader for drag & drop in to mass storage device, uf2 can be generated with ``uf2`` target
+
+.. code-block::
+
+   $ make BOARD=feather_nrf52840_express all uf2

From 62049089bacd4e604c7533e8d9de1ae09fe7222a Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:22:42 +0100
Subject: [PATCH 0266/2085] docs: add reference section index

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/reference/index.rst | 64 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 docs/reference/index.rst

diff --git a/docs/reference/index.rst b/docs/reference/index.rst
new file mode 100644
index 000000000..5da51d71a
--- /dev/null
+++ b/docs/reference/index.rst
@@ -0,0 +1,64 @@
+*********
+Reference
+*********
+
+.. figure:: ../assets/stack.png
+   :width: 1600px
+   :alt: stackup
+
+   representation of the TinyUSB stack.
+
+Device Stack
+============
+
+Supports multiple device configurations by dynamically changing usb descriptors. Low power functions such like suspend, resume, and remote wakeup. Following device classes are supported:
+
+-  Audio Class 2.0 (UAC2)
+-  Bluetooth Host Controller Interface (BTH HCI)
+-  Communication Class (CDC)
+-  Device Firmware Update (DFU): DFU mode (WIP) and Runtinme
+-  Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ...
+-  Mass Storage Class (MSC): with multiple LUNs
+-  Musical Instrument Digital Interface (MIDI)
+-  Network with RNDIS, CDC-ECM (work in progress)
+-  USB Test and Measurement Class (USBTMC)
+-  Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file.
+-  `WebUSB <https://github.com/WICG/webusb>`__ with vendor-specific class
+
+If you have special need, `usbd_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. Here is how RPi team add their reset interface [raspberrypi/pico-sdk#197](https://github.com/raspberrypi/pico-sdk/pull/197)
+
+Host Stack
+==========
+
+.. admonition:: Warning
+   :class: warning
+
+   Most active development is on the Device stack. The Host stack is under rework and largely untested.
+
+- Human Interface Device (HID): Keyboard, Mouse, Generic
+- Mass Storage Class (MSC)
+- Hub currently only supports 1 level of hub (due to my laziness)
+
+OS Abstraction layer
+====================
+
+TinyUSB is completely thread-safe by pushing all ISR events into a central queue, then process it later in the non-ISR context task function. It also uses semaphore/mutex to access shared resources such as CDC FIFO. Therefore the stack needs to use some of OS's basic APIs. Following OSes are already supported out of the box.
+
+- **No OS**
+- **FreeRTOS**
+- **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its [own repo](https://github.com/hathach/mynewt-tinyusb-example)
+
+License
+=======
+
+All TinyUSB sources in the `src` folder are licensed under MIT license. However, each file can be individually licensed especially those in `lib` and `hw/mcu` folder. Please make sure you understand all the license term for files you use in your project.
+
+Index
+=====
+
+.. toctree::
+   :maxdepth: 2
+
+   supported
+   getting_started
+   concurrency

From f4f1e1f06f99f23c172bad3b15e3ca8e7d03bb65 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:23:06 +0100
Subject: [PATCH 0267/2085] docs: port porting doc to rst

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/contributing/porting.rst | 241 ++++++++++++++++++++++++++++++++++
 1 file changed, 241 insertions(+)
 create mode 100644 docs/contributing/porting.rst

diff --git a/docs/contributing/porting.rst b/docs/contributing/porting.rst
new file mode 100644
index 000000000..7e9e462f0
--- /dev/null
+++ b/docs/contributing/porting.rst
@@ -0,0 +1,241 @@
+
+*******
+Porting
+*******
+
+TinyUSB is designed to be a universal USB protocol stack for microcontrollers. It
+handles most of the high level USB protocol and relies on the microcontroller's USB peripheral for
+data transactions on different endpoints. Porting is the process of adding low-level support for
+the rest of the common stack. Once the low-level is implemented, it is very easy to add USB support
+for the microcontroller to other projects, especially those already using TinyUSB such as CircuitPython.
+
+Below are instructions on how to get the cdc_msc device example running on a new microcontroller. Doing so includes adding the common code necessary for other uses while minimizing other extra code. Whenever you see a phrase or word in <> it should be replaced.
+
+Register defs
+-------------
+
+The first step to adding support is including the register definitions and startup code for the
+microcontroller in TinyUSB. We write the TinyUSB implementation against these structs instead of higher level functions to keep the code small and to prevent function name collisions in linking of larger projects. For ARM microcontrollers this is the CMSIS definitions. They should be
+placed in the ``hw/mcu/<vendor>/<chip_family>`` directory.
+
+Once this is done, create a directory in ``hw/bsp/<your board name>`` for the specific board you are using to test the code.  (Duplicating an existing board's directory is the best way to get started.) The board should be a readily available development board so that others can also test.
+
+Build
+-----
+
+Now that those directories are in place, we can start our iteration process to get the example building successfully. To build, run from the root of TinyUSB:
+
+``make -C examples/device/cdc_msc BOARD=<board>``
+
+Unless, you've read ahead, this will fail miserably. Now, lets get it to fail less by updating the files in the board directory. The code in the board's directory is responsible for setting up the microcontroller's clocks and pins so that USB works. TinyUSB itself only operates on the USB peripheral. The board directory also includes information what files are needed to build the example.
+
+One of the first things to change is the ``-DCFG_TUSB_MCU`` cflag in the ``board.mk`` file. This is used to tell TinyUSB what platform is being built. So, add an entry to ``src/tusb_option.h`` and update the CFLAG to match.
+
+Update ``board.mk``\ 's VENDOR and CHIP_FAMILY values when creating the directory for the struct files. Duplicate one of the other sources from ``src/portable`` into ``src/portable/<vendor>/<chip_family>`` and delete all of the implementation internals. We'll cover what everything there does later. For now, get it compiling.
+
+Implementation
+--------------
+
+At this point you should get an error due to an implementation issue and hopefully the build is setup for the new MCU. You will still need to modify the ``board.mk`` to include specific CFLAGS, the linker script, linker flags, source files, include directories. All file paths are relative to the top of the TinyUSB repo.
+
+Board Support (BSP)
+^^^^^^^^^^^^^^^^^^^
+
+The board support code is only used for self-contained examples and testing. It is not used when TinyUSB is part of a larger project. Its responsible for getting the MCU started and the USB peripheral clocked. It also optionally provides LED definitions that are used to blink an LED to show that the code is running.
+
+It is located in ``hw/bsp/<board name>/board_<board name>.c``.
+
+board_init
+~~~~~~~~~~
+
+``board_init`` is responsible for starting the MCU, setting up the USB clock and USB pins. It is also responsible for initializing LED pins.
+
+One useful clock debugging technique is to set up a PWM output at a known value such as 500hz based on the USB clock so that you can verify it is correct with a logic probe or oscilloscope.
+
+Setup your USB in a crystal-less mode when available. That makes the code easier to port across boards.
+
+board_led_write
+~~~~~~~~~~~~~~~
+
+Feel free to skip this until you want to verify your demo code is running. To implement, set the pin corresponding to the led to output a value that lights the LED when ``state`` is true.
+
+OS Abstraction Layer (OSAL)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The OS Abstraction Layer is responsible for providing basic data structures for TinyUSB that may allow for concurrency when used with an RTOS. Without an RTOS it simply handles concurrency issues between the main code and interrupts.
+
+The code is almost entirely agnostic of MCU and lives in ``src/osal``.
+
+Device API
+^^^^^^^^^^
+
+After the USB device is setup, the USB device code works by processing events on the main thread (by calling ``tud_task``\ ). These events are queued by the USB interrupt handler. So, there are three parts to the device low-level API: device setup, endpoint setup and interrupt processing.
+
+All of the code for the low-level device API is in ``src/portable/<vendor>/<chip family>/dcd_<chip family>.c``.
+
+Device Setup
+~~~~~~~~~~~~
+
+dcd_init
+""""""""
+
+Initializes the USB peripheral for device mode and enables it.
+This function should enable internal D+/D- pull-up for enumeration.
+
+dcd_int_enable / dcd_int_disable
+""""""""""""""""""""""""""""""""
+
+Enables or disables the USB device interrupt(s). May be used to prevent concurrency issues when mutating data structures shared between main code and the interrupt handler.
+
+dcd_int_handler
+"""""""""""""""
+
+Processes all the hardware generated events e.g Bus reset, new data packet from host etc ... It will be called by application in the MCU USB interrupt handler.
+
+dcd_set_address
+"""""""""""""""
+
+Called when the device is given a new bus address.
+
+If your peripheral automatically changes address during enumeration (like the nrf52) you may leave this empty and also no queue an event for the corresponding SETUP packet.
+
+dcd_remote_wakeup
+"""""""""""""""""
+
+Called to remote wake up host when suspended (e.g hid keyboard)
+
+dcd_connect / dcd_disconnect
+""""""""""""""""""""""""""""
+
+Connect or disconnect the data-line pull-up resistor. Define only if MCU has an internal pull-up. (BSP may define for MCU without internal pull-up.)
+
+Special events
+~~~~~~~~~~~~~~
+
+You must let TinyUSB know when certain events occur so that it can continue its work. There are a few methods you can call to queue events for TinyUSB to process.
+
+dcd_event_bus_signal
+""""""""""""""""""""
+
+There are a number of events that your peripheral may communicate about the state of the bus. Here is an overview of what they are. Events in **BOLD** must be provided for TinyUSB to work.
+
+
+* **DCD_EVENT_RESET** - Triggered when the host resets the bus causing the peripheral to reset. Do any other internal reset you need from the interrupt handler such as resetting the control endpoint.
+* DCD_EVENT_SOF - Signals the start of a new USB frame.
+
+Calls to this look like:
+
+.. code-block::
+
+   dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+
+
+The first ``0`` is the USB peripheral number. Statically saying 0 is common for single USB device MCUs.
+
+The ``true`` indicates the call is from an interrupt handler and will always be the case when porting in this way.
+
+dcd_setup_received
+""""""""""""""""""
+
+SETUP packets are a special type of transaction that can occur at any time on the control endpoint, numbered ``0``. Since they are unique, most peripherals have special handling for them. Their data is always 8 bytes in length as well.
+
+Calls to this look like:
+
+.. code-block::
+
+   dcd_event_setup_received(0, setup, true);
+
+
+As before with ``dcd_event_bus_signal`` the first argument is the USB peripheral number and the third is true to signal its being called from an interrupt handler. The middle argument is byte array of length 8 with the contents of the SETUP packet. It can be stack allocated because it is copied into the queue.
+
+Endpoints
+~~~~~~~~~
+
+Endpoints are the core of the USB data transfer process. They come in a few forms such as control, isochronous, bulk, and interrupt. We won't cover the details here except with some caveats in open below. In general, data is transferred by setting up a buffer of a given length to be transferred on a given endpoint address and then waiting for an interrupt to signal that the transfer is finished. Further details below.
+
+Endpoints within USB have an address which encodes both the number and direction of an endpoint. TinyUSB provides ``tu_edpt_number`` and ``tu_edpt_dir`` to unpack this data from the address. Here is a snippet that does it.
+
+.. code-block::
+
+   uint8_t epnum = tu_edpt_number(ep_addr);
+   uint8_t dir   = tu_edpt_dir(ep_addr);
+
+
+dcd_edpt_open
+"""""""""""""
+
+Opening an endpoint is done for all non-control endpoints once the host picks a configuration that the device should use. At this point, the endpoint should be enabled in the peripheral and configured to match the endpoint descriptor. Pay special attention to the direction of the endpoint you can get from the helper methods above. It will likely change what registers you are setting.
+
+Also make sure to enable endpoint specific interrupts.
+
+dcd_edpt_close
+""""""""""""""
+
+Close an endpoint. his function is used for implementing alternate settings.
+
+After calling this, the device should not respond to any packets directed towards this endpoint. When called, this function must abort any transfers in progress through this endpoint, before returning.
+
+Implementation is optional. Must be called from the USB task. Interrupts could be disabled or enabled during the call.
+
+dcd_edpt_xfer
+"""""""""""""
+
+``dcd_edpt_xfer`` is responsible for configuring the peripheral to send or receive data from the host. "xfer" is short for "transfer". **This is one of the core methods you must implement for TinyUSB to work (one other is the interrupt handler).**  Data from the host is the OUT direction and data to the host is IN. It  is used for all endpoints including the control endpoint 0. Make sure to handle the zero-length packet STATUS packet on endpoint 0 correctly. It may be a special transaction to the peripheral.
+
+Besides that, all other transactions are relatively straight-forward. The endpoint address provides the endpoint
+number and direction which usually determines where to write the buffer info. The buffer and its length are usually
+written to a specific location in memory and the peripheral is told the data is valid. (Maybe by writing a 1 to a
+register or setting a counter register to 0 for OUT or length for IN.)
+
+The transmit buffer alignment is determined by ``CFG_TUSB_MEM_ALIGN``.
+
+One potential pitfall is that the buffer may be longer than the maximum endpoint size of one USB
+packet. Some peripherals can handle transmitting multiple USB packets for a provided buffer (like the SAMD21).
+Others (like the nRF52) may need each USB packet queued individually. To make this work you'll need to track
+some state for yourself and queue up an intermediate USB packet from the interrupt handler.
+
+Once the transaction is going, the interrupt handler will notify TinyUSB of transfer completion.
+During transmission, the IN data buffer is guarenteed to remain unchanged in memory until the ``dcd_xfer_complete`` function is called.
+
+The dcd_edpt_xfer function must never add zero-length-packets (ZLP) on its own to a transfer. If a ZLP is required,
+then it must be explicitly sent by the stack calling dcd_edpt_xfer(), by calling dcd_edpt_xfer() a second time with len=0.
+For control transfers, this is automatically done in ``usbd_control.c``.
+
+At the moment, only a single buffer can be transmitted at once. There is no provision for double-buffering. new dcd_edpt_xfer() will not
+be called again on the same endpoint address until the driver calls dcd_xfer_complete() (except in cases of USB resets).
+
+dcd_xfer_complete
+"""""""""""""""""
+
+Once a transfer completes you must call dcd_xfer_complete from the USB interrupt handler to let TinyUSB know that a transaction has completed. Here is a sample call:
+
+.. code-block::
+
+   dcd_event_xfer_complete(0, ep_addr, xfer->actual_len, XFER_RESULT_SUCCESS, true);
+
+
+The arguments are:
+
+
+* the USB peripheral number
+* the endpoint address
+* the actual length of the transfer. (OUT transfers may be smaller than the buffer given in ``dcd_edpt_xfer``\ )
+* the result of the transfer. Failure isn't handled yet.
+* ``true`` to note the call is from an interrupt handler.
+
+dcd_edpt_stall / dcd_edpt_clear_stall
+"""""""""""""""""""""""""""""""""""""
+
+Stalling is one way an endpoint can indicate failure such as when an unsupported command is transmitted. The pair of ``dcd_edpt_stall``\ , ``dcd_edpt_clear_stall`` help manage the stall state of all endpoints.
+
+Woohoo!
+-------
+
+At this point you should have everything working! ;-) Of course, you may not write perfect code. Here are some tips and tricks for debugging.
+
+Use `WireShark <https://www.wireshark.org/>`_ or `a Beagle <https://www.totalphase.com/protocols/usb/>`_ to sniff the USB traffic. When things aren't working its likely very early in the USB enumeration process. Figuring out where can help clue in where the issue is. For example:
+
+
+* If the host sends a SETUP packet and its not ACKed then your USB peripheral probably isn't started correctly.
+* If the peripheral is started correctly but it still didn't work, then verify your usb clock is correct. (You did output a PWM based on it right? ;-) )
+* If the SETUP packet is ACKed but nothing is sent back then you interrupt handler isn't queueing the setup packet correctly. (Also, if you are using your own code instead of an example ``tud_task`` may not be called.) If thats OK, the ``dcd_xfer_complete`` may not be setting up the next transaction correctly.

From e2d05bff9360b021fa3d3bec8dfcc09e1753d3ba Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:23:33 +0100
Subject: [PATCH 0268/2085] docs: add contributing section index

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/contributing/index.rst | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 docs/contributing/index.rst

diff --git a/docs/contributing/index.rst b/docs/contributing/index.rst
new file mode 100644
index 000000000..c572894ad
--- /dev/null
+++ b/docs/contributing/index.rst
@@ -0,0 +1,23 @@
+************
+Contributing
+************
+
+Contributing can be highly rewarding, but it can also be frustrating at times.
+It takes time to review patches, and as this is an open source project, that
+sometimes can take a while. The reviewing process depends on the availability
+of the maintainers, who may not be always available. Please try to be
+understanding throught the process.
+
+There a few guidelines you need to keep in mind when contributing. Please have
+a look at them as that will make the contribution process easier for all
+parties.
+
+Index
+=====
+
+.. toctree::
+   :maxdepth: 2
+
+   code_of_conduct
+   structure
+   porting

From a183e5a72b9195800ea79601b8a804319efb7cde Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:41:01 +0100
Subject: [PATCH 0269/2085] docs: add structure doc

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/contributing/structure.rst | 59 +++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 docs/contributing/structure.rst

diff --git a/docs/contributing/structure.rst b/docs/contributing/structure.rst
new file mode 100644
index 000000000..e8c658850
--- /dev/null
+++ b/docs/contributing/structure.rst
@@ -0,0 +1,59 @@
+*********
+Structure
+*********
+
+Tree
+====
+
+::
+
+  .
+  ├── docs
+  ├── examples
+  ├── hw
+  │   ├── bsp
+  │   └── mcu
+  ├── lib
+  ├── src
+  ├── test
+  └── tools
+
+docs
+----
+
+Documentation
+
+examples
+--------
+
+Sample with Makefile build support
+
+hw/bsp
+------
+
+Supported boards source files
+
+hw/mcu
+------
+
+Low level mcu core & peripheral drivers
+
+lib
+---
+
+Sources from 3rd party such as freeRTOS, fatfs ...
+
+src
+---
+
+All sources files for TinyUSB stack itself.
+
+test
+----
+
+Unit tests for the stack
+
+tools
+-----
+
+Files used internally

From ff3c01ecc286c5606ce6072d4b591d489d7108d0 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:42:07 +0100
Subject: [PATCH 0270/2085] docs: move contributors to info section

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/{contributing => info}/contributors.rst | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename docs/{contributing => info}/contributors.rst (100%)

diff --git a/docs/contributing/contributors.rst b/docs/info/contributors.rst
similarity index 100%
rename from docs/contributing/contributors.rst
rename to docs/info/contributors.rst

From 42f551ec545543c22bb00e1dae4ac2358dae2528 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:43:30 +0100
Subject: [PATCH 0271/2085] docs: add supported devices list

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/reference/supported.rst | 335 +++++++++++++++++++++++++++++++++++
 1 file changed, 335 insertions(+)
 create mode 100644 docs/reference/supported.rst

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
new file mode 100644
index 000000000..e280e10a4
--- /dev/null
+++ b/docs/reference/supported.rst
@@ -0,0 +1,335 @@
+*****************
+Supported Devices
+*****************
+
+
+Supported MCUs
+==============
+
+.. admonition:: Warning
+   :class: warning
+
+   This table is a WIP! the data is not correct, tho if a device is listed, it likely works as a usb full speed device at the least.
+
++--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| Manufacturer | Family             | Device            | Host               | FS                | HS                | Known Issues |
++==============+====================+===================+====================+===================+===================+==============+
+| Dialog       | DA1469x            | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
++--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| Espressif    | ESP32-S2           | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | ESP32-S3           | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
++--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| MicroChip    | SAMD11             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | SAMD21             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | SAMD51             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | SAME5x             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | SAMG55             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | SAML21             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | SAML22             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | SAME70,S70,V70,V71 | |:green_square:|  | |:red_square:|     | |:green_square:|  | |:green_square:|  |              |
++--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| NordicSemi   | nRF52833           | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | nRF52840           | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
++--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| Nuvoton      | NUC120             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | NUC121/NUC125      | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | NUC126             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | NUC505             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
++--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| NXP          | iMX   | RT1011     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | RT1015     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | RT1021     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | RT1052     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | RT1062     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | RT1064     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
+|              +-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | Kinetis KL25       | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              +-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | LPC   | 11u        | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | 13         | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | 15         | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | 17         | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | 18         |                   | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | 40         |                   | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | 43         | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | 51u        | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | 54         | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | 55         | |:green_square:|  | |:x:|              | |:green_square:|  |                   |              |
++--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| Raspberry Pi | RP2040             | |:green_square:|  | |:x:|              | |:green_square:|  |                   |              |
++--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| Renesas      | RX63N              |                   |                    |                   |                   |              |
+|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              | RX65N              |                   |                    |                   |                   |              |
++--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| Silabs       | EFM32GG12          | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             | #750         |
++--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| Sony         | CXD56              | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
++--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| ST           | STM32 | L0         | |:green_square:|  |                    | |:green_square:|  |                   |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | F0         | |:green_square:|  |                    | |:green_square:|  |                   |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | F1         | |:green_square:|  |                    | |:green_square:|  |                   |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | F2         | |:green_square:|  |                    | |:green_square:|  |                   |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | F3         | |:green_square:|  |                    | |:green_square:|  |                   |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | F4         | |:green_square:|  |                    | |:green_square:|  |                   |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | F7         | |:green_square:|  |                    | |:green_square:|  |                   |              |
+|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
+|              |       | H7         | |:green_square:|  |                    | |:green_square:|  | |:green_square:|  |              |
++--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| TI           | MSP430             | |:green_square:|  |                    | |:green_square:|  |                   |              |
++--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+| ValentyUSB   | eptri              | |:green_square:|  |                    | |:green_square:|  |                   |              |
++--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
+
+Table Legend
+------------
+
+================= ===================
+|:x:|             Not available
+|:red_square:|    Not supported
+|:yellow_square:| WIP/partial support
+|:green_square:|  Supported
+================= ===================
+
+Supported Boards
+================
+
+The board support code is only used for self-contained examples and testing. It is not used when TinyUSB is part of a larger project. It is responsible for getting the MCU started and the USB peripheral clocked with minimal of on-board devices
+
+-  One LED : for status
+-  One Button : to get input from user
+-  One UART : optional for device, but required for host examples
+
+The following boards are supported (sorted alphabetically):
+
+Dialog DA146xx
+--------------
+
+-  `DA14695 Development Kit – USB <https://www.dialog-semiconductor.com/products/da14695-development-kit-usb>`__
+-  `DA1469x Development Kit – Pro <https://www.dialog-semiconductor.com/products/da14695-development-kit-pro>`__
+
+Espressif ESP32-S2
+------------------
+
+-  Adafruit Feather ESP32-S2
+-  `Adafruit Magtag 2.9" E-Ink WiFi Display <https://www.adafruit.com/product/4800>`__
+-  `Adafruit Metro ESP32-S2 <https://www.adafruit.com/product/4775>`__
+-  `ESP32-S2-Kaluga-1 <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit.html>`__
+-  `ESP32-S2-Saola-1 <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html>`__
+
+MicroChip
+---------
+
+SAMD11 & SAMD21
+^^^^^^^^^^^^^^^
+
+-  `Adafruit Circuit Playground Express <https://www.adafruit.com/product/3333>`__
+-  `Adafruit Feather M0 Express <https://www.adafruit.com/product/3403>`__
+-  `Adafruit ItsyBitsy M0 Express <https://www.adafruit.com/product/3727>`__
+-  `Adafruit Metro M0 Express <https://www.adafruit.com/product/3505>`__
+-  `Great Scott Gadgets LUNA <https://greatscottgadgets.com/luna/>`__
+-  `Microchip SAMD11 Xplained Pro <https://www.microchip.com/developmenttools/ProductDetails/atsamd11-xpro>`__
+-  `Microchip SAMD21 Xplained Pro <https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMD21-XPRO>`__
+-  `Seeeduino Xiao <https://www.seeedstudio.com/Seeeduino-XIAO-Arduino-Microcontroller-SAMD21-Cortex-M0+-p-4426.html>`__
+
+SAMD51 & SAME54
+^^^^^^^^^^^^^^^
+
+-  `Adafruit Feather M4 Express <https://www.adafruit.com/product/3857>`__
+-  `Adafruit ItsyBitsy M4 Express <https://www.adafruit.com/product/3800>`__
+-  `Adafruit PyBadge <https://www.adafruit.com/product/4200>`__
+-  `Adafruit PyPortal <https://www.adafruit.com/product/4116>`__
+-  `Adafruit Metro M4 Express <https://www.adafruit.com/product/3382>`__
+-  `D5035-01 <https://github.com/RudolphRiedel/USB_CAN-FD>`__
+-  `Microchip SAME54 Xplained Pro <https://www.microchip.com/developmenttools/productdetails/atsame54-xpro>`__
+
+SAMG
+^^^^
+
+-  `Microchip SAMG55 Xplained Pro <https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMG55-XPRO>`__
+
+SAML2x
+^^^^^^
+
+-  `SAML21 Xplaind Pro <https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAML21-XPRO-B>`__
+-  `SAML22 Feather <https://github.com/joeycastillo/Feather-Projects/tree/main/SAML22%20Feather>`__
+-  `Sensor Watch <https://github.com/joeycastillo/Sensor-Watch>`__
+
+Nordic nRF5x
+------------
+
+-  `Adafruit Circuit Playground Bluefruit <https://www.adafruit.com/product/4333>`__
+-  `Adafruit CLUE <https://www.adafruit.com/product/4500>`__
+-  `Adafruit Feather nRF52840 Express <https://www.adafruit.com/product/4062>`__
+-  `Adafruit Feather nRF52840 Sense <https://www.adafruit.com/product/4516>`__
+-  `Adafruit ItsyBitsy nRF52840 Express <https://www.adafruit.com/product/4481>`__
+-  `Arduino Nano 33 BLE <https://store.arduino.cc/usa/nano-33-ble>`__
+-  `Arduino Nano 33 BLE Sense <https://store.arduino.cc/usa/nano-33-ble-sense>`__
+-  `Maker Diary nRF52840 MDK Dongle <https://wiki.makerdiary.com/nrf52840-mdk-usb-dongle>`__
+-  `Nordic nRF52840 Development Kit (aka pca10056) <https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK>`__
+-  `Nordic nRF52840 Dongle (aka pca10059) <https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle>`__
+-  `Nordic nRF52833 Development Kit (aka pca10100) <https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK>`__
+-  `Raytac MDBT50Q-RX Dongle <https://www.raytac.com/product/ins.php?index_id=89>`__
+
+Nuvoton
+-------
+
+-  NuTiny SDK NUC120
+-  `NuTiny NUC121S <https://direct.nuvoton.com/en/nutiny-nuc121s>`__
+-  `NuTiny NUC125S <https://direct.nuvoton.com/en/nutiny-nuc125s>`__
+-  `NuTiny NUC126V <https://direct.nuvoton.com/en/nutiny-nuc126v>`__
+-  `NuTiny SDK NUC505Y <https://direct.nuvoton.com/en/nutiny-nuc505y>`__
+
+NXP
+---
+
+iMX RT
+^^^^^^
+
+-  `MIMX RT1010 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1010-evaluation-kit:MIMXRT1010-EVK>`__
+-  `MIMX RT1015 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1015-evaluation-kit:MIMXRT1015-EVK>`__
+-  `MIMX RT1020 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1020-evaluation-kit:MIMXRT1020-EVK>`__
+-  `MIMX RT1050 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK>`__
+-  `MIMX RT1060 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1060-evk-i.mx-rt1060-evaluation-kit:MIMXRT1060-EVK>`__
+-  `MIMX RT1064 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK>`__
+-  `Teensy 4.0 Development Board <https://www.pjrc.com/store/teensy40.html>`__
+
+Kinetis
+^^^^^^^
+
+-  `FRDM-KL25Z <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z>`__
+
+LPC 11-13-15
+^^^^^^^^^^^^
+
+-  `LPCXpresso 11u37 <https://www.nxp.com/design/microcontrollers-developer-resources/lpcxpresso-boards/lpcxpresso-board-for-lpc11u37h:OM13074>`__
+-  `LPCXpresso 11u68 <https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc11u68:OM13058>`__
+-  `LPCXpresso 1347 <https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1347:OM13045>`__
+-  `LPCXpresso 1549 <https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1500-cortex-m3/lpcxpresso-board-for-lpc1549:OM13056>`__
+
+LPC 17-40
+^^^^^^^^^
+
+-  `ARM mbed LPC1768 <https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1700-cortex-m3/arm-mbed-lpc1768-board:OM11043>`__
+-  `Embedded Artists LPC4088 Quick Start board <https://www.embeddedartists.com/products/lpc4088-quickstart-board>`__
+-  `LPCXpresso 1769 <https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso-board-for-lpc1769:OM13000>`__
+
+LPC 18-43
+^^^^^^^^^
+
+-  `Embedded Artists LPC4357 Developer Kit <http://www.embeddedartists.com/products/kits/lpc4357_kit.php>`__
+-  `Keil MCB1800 Evaluation Board <http://www.keil.com/mcb1800>`__
+-  `LPCXpresso18S37 Development Board <https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc4000-cortex-m4/lpcxpresso18s37-development-board:OM13076>`__
+-  `NGX LPC4330-Xplorer <https://www.nxp.com/design/designs/lpc4330-xplorer-board:OM13027>`__
+
+LPC 51
+^^^^^^
+
+-  `LPCXpresso 51U68 <https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005>`__
+
+LPC 54
+^^^^^^
+
+-  `LPCXpresso 54114 <https://www.nxp.com/design/microcontrollers-developer-resources/lpcxpresso-boards/lpcxpresso54114-board:OM13089>`__
+
+LPC55
+^^^^^
+
+-  `Double M33 Express <https://www.crowdsupply.com/steiert-solutions/double-m33-express>`__
+-  `LPCXpresso 55s28 EVK <https://www.nxp.com/design/software/development-software/lpcxpresso55s28-development-board:LPC55S28-EVK>`__
+-  `LPCXpresso 55s69 EVK <https://www.nxp.com/design/development-boards/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK>`__
+-  `MCU-Link <https://www.nxp.com/design/development-boards/lpcxpresso-boards/mcu-link-debug-probe:MCU-LINK>`__
+
+Renesas RX
+----------
+
+-  `GR-CITRUS <https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-citrus>`__
+-  `Renesas RX65N Target Board <https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk5rx65n0c00000br-target-board-rx65n>`__
+
+Raspberry Pi RP2040
+-------------------
+
+-  `Adafruit Feather RP2040 <https://www.adafruit.com/product/4884>`__
+-  `Adafruit ItsyBitsy RP2040 <https://www.adafruit.com/product/4888>`__
+-  `Adafruit QT Py RP2040 <https://www.adafruit.com/product/4900>`__
+-  `Raspberry Pi Pico <https://www.raspberrypi.org/products/raspberry-pi-pico/>`__
+
+Silabs
+------
+
+-  `EFM32GG12 Thunderboard Kit (SLTB009A) <https://www.silabs.com/development-tools/thunderboard/thunderboard-gg12-kit>`__
+
+Sony
+----
+
+-  `Sony Spresense CXD5602 <https://developer.sony.com/develop/spresense>`__
+
+ST STM32
+--------
+
+-  `Adafruit Feather STM32F405 <https://www.adafruit.com/product/4382>`__
+-  `Micro Python PyBoard v1.1 <https://store.micropython.org/product/PYBv1.1>`__
+-  `STLink-V3 Mini <https://www.st.com/en/development-tools/stlink-v3mini.html>`__
+-  `STM32 L035c8 Discovery <https://www.st.com/en/evaluation-tools/32l0538discovery.html>`__
+-  `STM32 L4R5zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html>`__
+-  `STM32 F070rb Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f070rb.html>`__
+-  `STM32 F072 Evaluation <https://www.st.com/en/evaluation-tools/stm32072b-eval.html>`__
+-  `STM32 F072rb Discovery <https://www.st.com/en/evaluation-tools/32f072bdiscovery.html>`__
+-  STM32 F103c Blue Pill
+-  `STM32 F207zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f207zg.html>`__
+-  `STM32 F303vc Discovery <https://www.st.com/en/evaluation-tools/stm32f3discovery.html>`__
+-  STM32 F401cc Black Pill
+-  `STM32 F407vg Discovery <https://www.st.com/en/evaluation-tools/stm32f4discovery.html>`__
+-  `STM32 F411ce Black Pill <https://www.adafruit.com/product/4877>`__
+-  `STM32 F411ve Discovery <https://www.st.com/en/evaluation-tools/32f411ediscovery.html>`__
+-  `STM32 F412zg Discovery <https://www.st.com/en/evaluation-tools/32f412gdiscovery.html>`__
+-  `STM32 F723e Discovery <https://www.st.com/en/evaluation-tools/32f723ediscovery.html>`__
+-  `STM32 F746zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f746zg.html>`__
+-  `STM32 F746g Discovery <https://www.st.com/en/evaluation-tools/32f746gdiscovery.html>`__
+-  `STM32 F767zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f767zi.html>`__
+-  `STM32 F769i Discovery <https://www.st.com/en/evaluation-tools/32f769idiscovery.html>`__
+-  `STM32 H743zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-h743zi.html>`__
+-  `STM32 H743i Evaluation <https://www.st.com/en/evaluation-tools/stm32h743i-eval.html>`__
+-  `STM32 H745i Discovery <https://www.st.com/en/evaluation-tools/stm32h745i-disco.html>`__
+
+TI
+--
+
+-  `MSP430F5529 USB LaunchPad Evaluation Kit <http://www.ti.com/tool/MSP-EXP430F5529LP>`__
+
+Tomu
+----
+
+-  `Fomu <https://www.crowdsupply.com/sutajio-kosagi/fomu>`__

From 21e3fca4bee938479dffce3bb080f35829a4a2c0 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:44:18 +0100
Subject: [PATCH 0272/2085] docs: add list of projects that use Tusb

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/info/uses.rst | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 docs/info/uses.rst

diff --git a/docs/info/uses.rst b/docs/info/uses.rst
new file mode 100644
index 000000000..f67df49f8
--- /dev/null
+++ b/docs/info/uses.rst
@@ -0,0 +1,17 @@
+****
+Uses
+****
+
+TinyUSB is currently used by these other projects:
+
+-  `Adafruit nRF52 Arduino <https://github.com/adafruit/Adafruit_nRF52_Arduino>`__
+-  `Adafruit nRF52 Bootloader <https://github.com/adafruit/Adafruit_nRF52_Bootloader>`__
+-  `Adafruit SAMD Arduino <https://github.com/adafruit/ArduinoCore-samd>`__
+-  `CircuitPython <https://github.com/adafruit/circuitpython>`__
+-  `Espressif IDF <https://github.com/espressif/esp-idf>`__
+-  `MicroPython <https://github.com/micropython/micropython>`__
+-  `mynewt <https://mynewt.apache.org>`__
+-  `openinput <https://github.com/openinput-fw/openinput>`__
+-  `Raspberry Pi Pico SDK <https://github.com/raspberrypi/pico-sdk>`__
+-  `TinyUF2 Bootloader <https://github.com/adafruit/tinyuf2>`__
+-  `TinyUSB Arduino Library <https://github.com/adafruit/Adafruit_TinyUSB_Arduino>`__

From 8e791c118c9c2ede2bf4d80c27ad387a5a08b6e2 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:44:44 +0100
Subject: [PATCH 0273/2085] docs: add info section index

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/info/index.rst | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 docs/info/index.rst

diff --git a/docs/info/index.rst b/docs/info/index.rst
new file mode 100644
index 000000000..fa56512b6
--- /dev/null
+++ b/docs/info/index.rst
@@ -0,0 +1,13 @@
+****
+Info
+****
+
+Index
+=====
+
+.. toctree::
+   :maxdepth: 2
+
+   uses
+   changelog
+   contributors

From 37c56d677a3cb01b3b89bafb3f53dacfb9264863 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:46:08 +0100
Subject: [PATCH 0274/2085] docs: add local copy of stackup image, with added
 backround

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/assets/stack.png | Bin 0 -> 63797 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 docs/assets/stack.png

diff --git a/docs/assets/stack.png b/docs/assets/stack.png
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literal 0
HcmV?d00001


From 358d7811627ab70bacf6c28fbec4a6b5a3783463 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:47:05 +0100
Subject: [PATCH 0275/2085] docs: update main index

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/index.rst | 33 +++++++++++++++++++--------------
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/docs/index.rst b/docs/index.rst
index d30b743f4..2a032c51e 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -1,20 +1,25 @@
-.. TinyUSB documentation master file, created by
-   sphinx-quickstart on Mon Jul 26 17:17:52 2021.
-   You can adapt this file completely to your liking, but it should at least
-   contain the root `toctree` directive.
+:hide-toc:
+
+*********
+TinyUSB
+*********
+
+TinyUSB is an open-source cross-platform USB Host/Device stack for embedded systems,
+designed to be memory-safe with no dynamic allocation and thread-safe with all interrupt events being deferred and then handled in the non-ISR task function.
 
-Welcome to TinyUSB's documentation!
-===================================
 
 .. toctree::
-   :maxdepth: 2
-   :caption: Contents:
+   :caption: Index
+   :hidden:
 
+   Info <info/index>
+   Reference <reference/index>
+   Contributing <contributing/index>
 
+.. toctree::
+   :caption: External Links
+   :hidden:
 
-Indices and tables
-==================
-
-* :ref:`genindex`
-* :ref:`modindex`
-* :ref:`search`
+   Source Code <https://github.com/hathach/tinyusb>
+   Issue Tracker <https://github.com/hathach/tinyusb/issues>
+   Discussions <https://github.com/hathach/tinyusb/discussions>

From 37e2342086f0da24ee39522e417e6cdf4d3fa108 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 19:47:55 +0100
Subject: [PATCH 0276/2085] readme: remove redundant info, and point to new
 docs

Signed-off-by: perigoso <perigoso@riseup.net>
---
 README.md | 100 ++----------------------------------------------------
 1 file changed, 3 insertions(+), 97 deletions(-)

diff --git a/README.md b/README.md
index c1f09720d..95486ecd9 100644
--- a/README.md
+++ b/README.md
@@ -4,107 +4,13 @@
 
 TinyUSB is an open-source cross-platform USB Host/Device stack for embedded system, designed to be memory-safe with no dynamic allocation and thread-safe with all interrupt events are deferred then handled in the non-ISR task function.
 
-![tinyusb](https://user-images.githubusercontent.com/249515/49858616-f60c9700-fe27-11e8-8627-e76936352ff7.png)
-
-```
-.
-├── docs            # Documentation
-├── examples        # Sample with Makefile build support
-├── hw
-│   ├── bsp         # Supported boards source files
-│   └── mcu         # Low level mcu core & peripheral drivers
-├── lib             # Sources from 3rd party such as freeRTOS, fatfs ...
-├── src             # All sources files for TinyUSB stack itself.
-├── test            # Unit tests for the stack
-└── tools           # Files used internally
-```
+Please head over to the online [documentation](www.tinyusb.org) for more info.
 
 ## Contributors
 
 Special thanks to all the people who spent their precious time and effort to help this project so far. Check out the 
-[CONTRIBUTORS.md](CONTRIBUTORS.md) file for the list of all contributors and their awesome work for the stack.
-
-## Supported MCUs
-
-The stack supports the following MCUs:
-
-- **Dialog:** DA1469x
-- **Espressif:** ESP32-S2, ESP32-S3
-- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAME7x
-- **NordicSemi:** nRF52833, nRF52840
-- **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
-- **NXP:**
-  - iMX RT Series: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
-  - Kinetis: KL25
-  - LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
-- **Raspberry Pi:** RP2040
-- **Renesas:** RX63N, RX65N
-- **Silabs:** EFM32GG12
-- **Sony:** CXD56
-- **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
-- **TI:** MSP430
-- **[ValentyUSB](https://github.com/im-tomu/valentyusb)** eptri
-
-[Here is the list of supported Boards](docs/boards.md) that can be used with provided examples.
-
-## Device Stack
-
-Supports multiple device configurations by dynamically changing usb descriptors. Low power functions such like suspend, resume, and remote wakeup. Following device classes are supported:
-
-- Audio Class 2.0 (UAC2)
-- Bluetooth Host Controller Interface (BTH HCI)
-- Communication Class (CDC)
-- Device Firmware Update (DFU): DFU mode (WIP) and Runtinme 
-- Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ...
-- Mass Storage Class (MSC): with multiple LUNs
-- Musical Instrument Digital Interface (MIDI)
-- Network with RNDIS, CDC-ECM (work in progress)
-- USB Test and Measurement Class (USBTMC)
-- Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file.
-- [WebUSB](https://github.com/WICG/webusb) with vendor-specific class
-
-If you have special need, `usbd_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. Here is how RPi team add their reset interface [raspberrypi/pico-sdk#197](https://github.com/raspberrypi/pico-sdk/pull/197)
-
-## Host Stack
-
-**Most active development is on the Device stack. The Host stack is under rework and largely untested.**
-
-- Human Interface Device (HID): Keyboard, Mouse, Generic
-- Mass Storage Class (MSC)
-- Hub currently only supports 1 level of hub (due to my laziness)
-
-## OS Abstraction layer
-
-TinyUSB is completely thread-safe by pushing all ISR events into a central queue, then process it later in the non-ISR context task function. It also uses semaphore/mutex to access shared resources such as CDC FIFO. Therefore the stack needs to use some of OS's basic APIs. Following OSes are already supported out of the box.
-
-- **No OS**
-- **FreeRTOS**
-- **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its [own repo](https://github.com/hathach/mynewt-tinyusb-example) 
-
-## Getting Started
-
-[Here are the details for getting started](docs/getting_started.md) with the stack.
-
-## Porting
-
-Want to help add TinyUSB support for a new MCU? Read [here](docs/porting.md) for an explanation on the low-level API needed by TinyUSB.
+[CONTRIBUTORS](CONTRIBUTORS.rst) file for the list of all contributors and their awesome work for the stack.
 
 ## License
 
-MIT license for all TinyUSB sources `src` folder, [Full license is here](LICENSE). However, each file is individually licensed especially those in `lib` and `hw/mcu` folder. Please make sure you understand all the license term for files you use in your project.
-
-## Uses
-
-TinyUSB is currently used by these other projects:
-
-- [Adafruit nRF52 Arduino](https://github.com/adafruit/Adafruit_nRF52_Arduino)
-- [Adafruit nRF52 Bootloader](https://github.com/adafruit/Adafruit_nRF52_Bootloader)
-- [Adafruit SAMD Arduino](https://github.com/adafruit/ArduinoCore-samd)
-- [CircuitPython](https://github.com/adafruit/circuitpython)
-- [Espressif IDF](https://github.com/espressif/esp-idf)
-- [MicroPython](https://github.com/micropython/micropython)
-- [mynewt](https://mynewt.apache.org)
-- [openinput](https://github.com/openinput-fw/openinput)
-- [Raspberry Pi Pico SDK](https://github.com/raspberrypi/pico-sdk)
-- [TinyUF2 Bootloader](https://github.com/adafruit/tinyuf2)
-- [TinyUSB Arduino Library](https://github.com/adafruit/Adafruit_TinyUSB_Arduino)
+All TinyUSB sources in the `src` folder are licensed under MIT license, [Full license is here](LICENSE). However, each file can be individually licensed especially those in `lib` and `hw/mcu` folder. Please make sure you understand all the license term for files you use in your project.

From f900a3ba7f013d65114af946c4fbeba6dd8b7551 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 20:08:59 +0100
Subject: [PATCH 0277/2085] docs: remove doxygen files

Signed-off-by: perigoso <perigoso@riseup.net>
---
 tinyusb.Doxyfile | 2384 ----------------------------------------------
 1 file changed, 2384 deletions(-)
 delete mode 100644 tinyusb.Doxyfile

diff --git a/tinyusb.Doxyfile b/tinyusb.Doxyfile
deleted file mode 100644
index 4e380f138..000000000
--- a/tinyusb.Doxyfile
+++ /dev/null
@@ -1,2384 +0,0 @@
-# Doxyfile 1.8.6
-
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-
-DOXYFILE_ENCODING      = UTF-8
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-
-PROJECT_NAME           = tinyusb
-
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-PROJECT_NUMBER         = 0.4
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-# doxygen will become slower. If the cache is too large, memory is wasted. The
-# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range
-# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536
-# symbols. At the end of a run doxygen will report the cache usage and suggest
-# the optimal cache size from a speed point of view.
-# Minimum value: 0, maximum value: 9, default value: 0.
-
-LOOKUP_CACHE_SIZE      = 0
-
-#---------------------------------------------------------------------------
-# Build related configuration options
-#---------------------------------------------------------------------------
-
-# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
-# documentation are documented, even if no documentation was available. Private
-# class members and static file members will be hidden unless the
-# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.
-# Note: This will also disable the warnings about undocumented members that are
-# normally produced when WARNINGS is set to YES.
-# The default value is: NO.
-
-EXTRACT_ALL            = NO
-
-# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will
-# be included in the documentation.
-# The default value is: NO.
-
-EXTRACT_PRIVATE        = NO
-
-# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal
-# scope will be included in the documentation.
-# The default value is: NO.
-
-EXTRACT_PACKAGE        = NO
-
-# If the EXTRACT_STATIC tag is set to YES all static members of a file will be
-# included in the documentation.
-# The default value is: NO.
-
-EXTRACT_STATIC         = YES
-
-# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined
-# locally in source files will be included in the documentation. If set to NO
-# only classes defined in header files are included. Does not have any effect
-# for Java sources.
-# The default value is: YES.
-
-EXTRACT_LOCAL_CLASSES  = YES
-
-# This flag is only useful for Objective-C code. When set to YES local methods,
-# which are defined in the implementation section but not in the interface are
-# included in the documentation. If set to NO only methods in the interface are
-# included.
-# The default value is: NO.
-
-EXTRACT_LOCAL_METHODS  = NO
-
-# If this flag is set to YES, the members of anonymous namespaces will be
-# extracted and appear in the documentation as a namespace called
-# 'anonymous_namespace{file}', where file will be replaced with the base name of
-# the file that contains the anonymous namespace. By default anonymous namespace
-# are hidden.
-# The default value is: NO.
-
-EXTRACT_ANON_NSPACES   = NO
-
-# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all
-# undocumented members inside documented classes or files. If set to NO these
-# members will be included in the various overviews, but no documentation
-# section is generated. This option has no effect if EXTRACT_ALL is enabled.
-# The default value is: NO.
-
-HIDE_UNDOC_MEMBERS     = NO
-
-# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all
-# undocumented classes that are normally visible in the class hierarchy. If set
-# to NO these classes will be included in the various overviews. This option has
-# no effect if EXTRACT_ALL is enabled.
-# The default value is: NO.
-
-HIDE_UNDOC_CLASSES     = NO
-
-# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend
-# (class|struct|union) declarations. If set to NO these declarations will be
-# included in the documentation.
-# The default value is: NO.
-
-HIDE_FRIEND_COMPOUNDS  = NO
-
-# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any
-# documentation blocks found inside the body of a function. If set to NO these
-# blocks will be appended to the function's detailed documentation block.
-# The default value is: NO.
-
-HIDE_IN_BODY_DOCS      = NO
-
-# The INTERNAL_DOCS tag determines if documentation that is typed after a
-# \internal command is included. If the tag is set to NO then the documentation
-# will be excluded. Set it to YES to include the internal documentation.
-# The default value is: NO.
-
-INTERNAL_DOCS          = NO
-
-# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file
-# names in lower-case letters. If set to YES upper-case letters are also
-# allowed. This is useful if you have classes or files whose names only differ
-# in case and if your file system supports case sensitive file names. Windows
-# and Mac users are advised to set this option to NO.
-# The default value is: system dependent.
-
-CASE_SENSE_NAMES       = NO
-
-# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with
-# their full class and namespace scopes in the documentation. If set to YES the
-# scope will be hidden.
-# The default value is: NO.
-
-HIDE_SCOPE_NAMES       = YES
-
-# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of
-# the files that are included by a file in the documentation of that file.
-# The default value is: YES.
-
-SHOW_INCLUDE_FILES     = YES
-
-
-SHOW_GROUPED_MEMB_INC  = NO
-
-# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include
-# files with double quotes in the documentation rather than with sharp brackets.
-# The default value is: NO.
-
-FORCE_LOCAL_INCLUDES   = NO
-
-# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the
-# documentation for inline members.
-# The default value is: YES.
-
-INLINE_INFO            = YES
-
-# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the
-# (detailed) documentation of file and class members alphabetically by member
-# name. If set to NO the members will appear in declaration order.
-# The default value is: YES.
-
-SORT_MEMBER_DOCS       = YES
-
-# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief
-# descriptions of file, namespace and class members alphabetically by member
-# name. If set to NO the members will appear in declaration order. Note that
-# this will also influence the order of the classes in the class list.
-# The default value is: NO.
-
-SORT_BRIEF_DOCS        = NO
-
-# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the
-# (brief and detailed) documentation of class members so that constructors and
-# destructors are listed first. If set to NO the constructors will appear in the
-# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.
-# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief
-# member documentation.
-# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting
-# detailed member documentation.
-# The default value is: NO.
-
-SORT_MEMBERS_CTORS_1ST = NO
-
-# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy
-# of group names into alphabetical order. If set to NO the group names will
-# appear in their defined order.
-# The default value is: NO.
-
-SORT_GROUP_NAMES       = NO
-
-# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by
-# fully-qualified names, including namespaces. If set to NO, the class list will
-# be sorted only by class name, not including the namespace part.
-# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
-# Note: This option applies only to the class list, not to the alphabetical
-# list.
-# The default value is: NO.
-
-SORT_BY_SCOPE_NAME     = NO
-
-# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper
-# type resolution of all parameters of a function it will reject a match between
-# the prototype and the implementation of a member function even if there is
-# only one candidate or it is obvious which candidate to choose by doing a
-# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still
-# accept a match between prototype and implementation in such cases.
-# The default value is: NO.
-
-STRICT_PROTO_MATCHING  = NO
-
-# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the
-# todo list. This list is created by putting \todo commands in the
-# documentation.
-# The default value is: YES.
-
-GENERATE_TODOLIST      = YES
-
-# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the
-# test list. This list is created by putting \test commands in the
-# documentation.
-# The default value is: YES.
-
-GENERATE_TESTLIST      = YES
-
-# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug
-# list. This list is created by putting \bug commands in the documentation.
-# The default value is: YES.
-
-GENERATE_BUGLIST       = YES
-
-# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)
-# the deprecated list. This list is created by putting \deprecated commands in
-# the documentation.
-# The default value is: YES.
-
-GENERATE_DEPRECATEDLIST= YES
-
-# The ENABLED_SECTIONS tag can be used to enable conditional documentation
-# sections, marked by \if <section_label> ... \endif and \cond <section_label>
-# ... \endcond blocks.
-
-ENABLED_SECTIONS       = 
-
-# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the
-# initial value of a variable or macro / define can have for it to appear in the
-# documentation. If the initializer consists of more lines than specified here
-# it will be hidden. Use a value of 0 to hide initializers completely. The
-# appearance of the value of individual variables and macros / defines can be
-# controlled using \showinitializer or \hideinitializer command in the
-# documentation regardless of this setting.
-# Minimum value: 0, maximum value: 10000, default value: 30.
-
-MAX_INITIALIZER_LINES  = 30
-
-# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at
-# the bottom of the documentation of classes and structs. If set to YES the list
-# will mention the files that were used to generate the documentation.
-# The default value is: YES.
-
-SHOW_USED_FILES        = YES
-
-# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This
-# will remove the Files entry from the Quick Index and from the Folder Tree View
-# (if specified).
-# The default value is: YES.
-
-SHOW_FILES             = YES
-
-# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces
-# page. This will remove the Namespaces entry from the Quick Index and from the
-# Folder Tree View (if specified).
-# The default value is: YES.
-
-SHOW_NAMESPACES        = YES
-
-# The FILE_VERSION_FILTER tag can be used to specify a program or script that
-# doxygen should invoke to get the current version for each file (typically from
-# the version control system). Doxygen will invoke the program by executing (via
-# popen()) the command command input-file, where command is the value of the
-# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided
-# by doxygen. Whatever the program writes to standard output is used as the file
-# version. For an example see the documentation.
-
-FILE_VERSION_FILTER    = 
-
-# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
-# by doxygen. The layout file controls the global structure of the generated
-# output files in an output format independent way. To create the layout file
-# that represents doxygen's defaults, run doxygen with the -l option. You can
-# optionally specify a file name after the option, if omitted DoxygenLayout.xml
-# will be used as the name of the layout file.
-#
-# Note that if you run doxygen from a directory containing a file called
-# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE
-# tag is left empty.
-
-LAYOUT_FILE            = 
-
-# The CITE_BIB_FILES tag can be used to specify one or more bib files containing
-# the reference definitions. This must be a list of .bib files. The .bib
-# extension is automatically appended if omitted. This requires the bibtex tool
-# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.
-# For LaTeX the style of the bibliography can be controlled using
-# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the
-# search path. Do not use file names with spaces, bibtex cannot handle them. See
-# also \cite for info how to create references.
-
-CITE_BIB_FILES         = 
-
-#---------------------------------------------------------------------------
-# Configuration options related to warning and progress messages
-#---------------------------------------------------------------------------
-
-# The QUIET tag can be used to turn on/off the messages that are generated to
-# standard output by doxygen. If QUIET is set to YES this implies that the
-# messages are off.
-# The default value is: NO.
-
-QUIET                  = NO
-
-# The WARNINGS tag can be used to turn on/off the warning messages that are
-# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES
-# this implies that the warnings are on.
-#
-# Tip: Turn warnings on while writing the documentation.
-# The default value is: YES.
-
-WARNINGS               = YES
-
-# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate
-# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag
-# will automatically be disabled.
-# The default value is: YES.
-
-WARN_IF_UNDOCUMENTED   = YES
-
-# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for
-# potential errors in the documentation, such as not documenting some parameters
-# in a documented function, or documenting parameters that don't exist or using
-# markup commands wrongly.
-# The default value is: YES.
-
-WARN_IF_DOC_ERROR      = YES
-
-# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that
-# are documented, but have no documentation for their parameters or return
-# value. If set to NO doxygen will only warn about wrong or incomplete parameter
-# documentation, but not about the absence of documentation.
-# The default value is: NO.
-
-WARN_NO_PARAMDOC       = NO
-
-# The WARN_FORMAT tag determines the format of the warning messages that doxygen
-# can produce. The string should contain the $file, $line, and $text tags, which
-# will be replaced by the file and line number from which the warning originated
-# and the warning text. Optionally the format may contain $version, which will
-# be replaced by the version of the file (if it could be obtained via
-# FILE_VERSION_FILTER)
-# The default value is: $file:$line: $text.
-
-WARN_FORMAT            = "$file:$line: $text"
-
-# The WARN_LOGFILE tag can be used to specify a file to which warning and error
-# messages should be written. If left blank the output is written to standard
-# error (stderr).
-
-WARN_LOGFILE           = 
-
-#---------------------------------------------------------------------------
-# Configuration options related to the input files
-#---------------------------------------------------------------------------
-
-# The INPUT tag is used to specify the files and/or directories that contain
-# documented source files. You may enter file names like myfile.cpp or
-# directories like /usr/src/myproject. Separate the files or directories with
-# spaces.
-# Note: If this tag is empty the current directory is searched.
-
-INPUT                  = doxygen \
-                         readme.markdown \
-                         tinyusb \
-                         boards \
-                         tests/readme.md \
-                         tools/readme.md \
-                         demos/readme.md \
-                         demos/device/readme.md \
-                         demos/host/readme.md
-
-# This tag can be used to specify the character encoding of the source files
-# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses
-# libiconv (or the iconv built into libc) for the transcoding. See the libiconv
-# documentation (see: http://www.gnu.org/software/libiconv) for the list of
-# possible encodings.
-# The default value is: UTF-8.
-
-INPUT_ENCODING         = UTF-8
-
-# If the value of the INPUT tag contains directories, you can use the
-# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and
-# *.h) to filter out the source-files in the directories. If left blank the
-# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,
-# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,
-# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,
-# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,
-# *.qsf, *.as and *.js.
-
-FILE_PATTERNS          = *.c \
-                         *.cc \
-                         *.cxx \
-                         *.cpp \
-                         *.c++ \
-                         *.java \
-                         *.ii \
-                         *.ixx \
-                         *.ipp \
-                         *.i++ \
-                         *.inl \
-                         *.idl \
-                         *.ddl \
-                         *.odl \
-                         *.h \
-                         *.hh \
-                         *.hxx \
-                         *.hpp \
-                         *.h++ \
-                         *.cs \
-                         *.d \
-                         *.php \
-                         *.php4 \
-                         *.php5 \
-                         *.phtml \
-                         *.inc \
-                         *.m \
-                         *.markdown \
-                         *.md \
-                         *.mm \
-                         *.dox \
-                         *.py \
-                         *.f90 \
-                         *.f \
-                         *.for \
-                         *.tcl \
-                         *.vhd \
-                         *.vhdl \
-                         *.ucf \
-                         *.qsf \
-                         *.as \
-                         *.js \
-                         *.txt
-
-# The RECURSIVE tag can be used to specify whether or not subdirectories should
-# be searched for input files as well.
-# The default value is: NO.
-
-RECURSIVE              = YES
-
-# The EXCLUDE tag can be used to specify files and/or directories that should be
-# excluded from the INPUT source files. This way you can easily exclude a
-# subdirectory from a directory tree whose root is specified with the INPUT tag.
-#
-# Note that relative paths are relative to the directory from which doxygen is
-# run.
-
-EXCLUDE                = 
-
-# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
-# directories that are symbolic links (a Unix file system feature) are excluded
-# from the input.
-# The default value is: NO.
-
-EXCLUDE_SYMLINKS       = NO
-
-# If the value of the INPUT tag contains directories, you can use the
-# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
-# certain files from those directories.
-#
-# Note that the wildcards are matched against the file with absolute path, so to
-# exclude all test directories for example use the pattern */test/*
-
-EXCLUDE_PATTERNS       = 
-
-# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
-# (namespaces, classes, functions, etc.) that should be excluded from the
-# output. The symbol name can be a fully qualified name, a word, or if the
-# wildcard * is used, a substring. Examples: ANamespace, AClass,
-# AClass::ANamespace, ANamespace::*Test
-#
-# Note that the wildcards are matched against the file with absolute path, so to
-# exclude all test directories use the pattern */test/*
-
-EXCLUDE_SYMBOLS        = 
-
-# The EXAMPLE_PATH tag can be used to specify one or more files or directories
-# that contain example code fragments that are included (see the \include
-# command).
-
-EXAMPLE_PATH           = 
-
-# If the value of the EXAMPLE_PATH tag contains directories, you can use the
-# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and
-# *.h) to filter out the source-files in the directories. If left blank all
-# files are included.
-
-EXAMPLE_PATTERNS       = *
-
-# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
-# searched for input files to be used with the \include or \dontinclude commands
-# irrespective of the value of the RECURSIVE tag.
-# The default value is: NO.
-
-EXAMPLE_RECURSIVE      = NO
-
-# The IMAGE_PATH tag can be used to specify one or more files or directories
-# that contain images that are to be included in the documentation (see the
-# \image command).
-
-IMAGE_PATH             = 
-
-# The INPUT_FILTER tag can be used to specify a program that doxygen should
-# invoke to filter for each input file. Doxygen will invoke the filter program
-# by executing (via popen()) the command:
-#
-# <filter> <input-file>
-#
-# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the
-# name of an input file. Doxygen will then use the output that the filter
-# program writes to standard output. If FILTER_PATTERNS is specified, this tag
-# will be ignored.
-#
-# Note that the filter must not add or remove lines; it is applied before the
-# code is scanned, but not when the output code is generated. If lines are added
-# or removed, the anchors will not be placed correctly.
-
-INPUT_FILTER           = 
-
-# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
-# basis. Doxygen will compare the file name with each pattern and apply the
-# filter if there is a match. The filters are a list of the form: pattern=filter
-# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how
-# filters are used. If the FILTER_PATTERNS tag is empty or if none of the
-# patterns match the file name, INPUT_FILTER is applied.
-
-FILTER_PATTERNS        = 
-
-# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
-# INPUT_FILTER ) will also be used to filter the input files that are used for
-# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).
-# The default value is: NO.
-
-FILTER_SOURCE_FILES    = NO
-
-# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
-# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and
-# it is also possible to disable source filtering for a specific pattern using
-# *.ext= (so without naming a filter).
-# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.
-
-FILTER_SOURCE_PATTERNS = 
-
-# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that
-# is part of the input, its contents will be placed on the main page
-# (index.html). This can be useful if you have a project on for instance GitHub
-# and want to reuse the introduction page also for the doxygen output.
-
-USE_MDFILE_AS_MAINPAGE = readme.markdown
-
-#---------------------------------------------------------------------------
-# Configuration options related to source browsing
-#---------------------------------------------------------------------------
-
-# If the SOURCE_BROWSER tag is set to YES then a list of source files will be
-# generated. Documented entities will be cross-referenced with these sources.
-#
-# Note: To get rid of all source code in the generated output, make sure that
-# also VERBATIM_HEADERS is set to NO.
-# The default value is: NO.
-
-SOURCE_BROWSER         = YES
-
-# Setting the INLINE_SOURCES tag to YES will include the body of functions,
-# classes and enums directly into the documentation.
-# The default value is: NO.
-
-INLINE_SOURCES         = NO
-
-# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any
-# special comment blocks from generated source code fragments. Normal C, C++ and
-# Fortran comments will always remain visible.
-# The default value is: YES.
-
-STRIP_CODE_COMMENTS    = YES
-
-# If the REFERENCED_BY_RELATION tag is set to YES then for each documented
-# function all documented functions referencing it will be listed.
-# The default value is: NO.
-
-REFERENCED_BY_RELATION = NO
-
-# If the REFERENCES_RELATION tag is set to YES then for each documented function
-# all documented entities called/used by that function will be listed.
-# The default value is: NO.
-
-REFERENCES_RELATION    = NO
-
-# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set
-# to YES, then the hyperlinks from functions in REFERENCES_RELATION and
-# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will
-# link to the documentation.
-# The default value is: YES.
-
-REFERENCES_LINK_SOURCE = YES
-
-# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the
-# source code will show a tooltip with additional information such as prototype,
-# brief description and links to the definition and documentation. Since this
-# will make the HTML file larger and loading of large files a bit slower, you
-# can opt to disable this feature.
-# The default value is: YES.
-# This tag requires that the tag SOURCE_BROWSER is set to YES.
-
-SOURCE_TOOLTIPS        = YES
-
-# If the USE_HTAGS tag is set to YES then the references to source code will
-# point to the HTML generated by the htags(1) tool instead of doxygen built-in
-# source browser. The htags tool is part of GNU's global source tagging system
-# (see http://www.gnu.org/software/global/global.html). You will need version
-# 4.8.6 or higher.
-#
-# To use it do the following:
-# - Install the latest version of global
-# - Enable SOURCE_BROWSER and USE_HTAGS in the config file
-# - Make sure the INPUT points to the root of the source tree
-# - Run doxygen as normal
-#
-# Doxygen will invoke htags (and that will in turn invoke gtags), so these
-# tools must be available from the command line (i.e. in the search path).
-#
-# The result: instead of the source browser generated by doxygen, the links to
-# source code will now point to the output of htags.
-# The default value is: NO.
-# This tag requires that the tag SOURCE_BROWSER is set to YES.
-
-USE_HTAGS              = NO
-
-# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a
-# verbatim copy of the header file for each class for which an include is
-# specified. Set to NO to disable this.
-# See also: Section \class.
-# The default value is: YES.
-
-VERBATIM_HEADERS       = YES
-
-# If the CLANG_ASSISTED_PARSING tag is set to YES, then doxygen will use the
-# clang parser (see: http://clang.llvm.org/) for more acurate parsing at the
-# cost of reduced performance. This can be particularly helpful with template
-# rich C++ code for which doxygen's built-in parser lacks the necessary type
-# information.
-# Note: The availability of this option depends on whether or not doxygen was
-# compiled with the --with-libclang option.
-# The default value is: NO.
-
-CLANG_ASSISTED_PARSING = NO
-
-# If clang assisted parsing is enabled you can provide the compiler with command
-# line options that you would normally use when invoking the compiler. Note that
-# the include paths will already be set by doxygen for the files and directories
-# specified with INPUT and INCLUDE_PATH.
-# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
-
-CLANG_OPTIONS          = 
-
-#---------------------------------------------------------------------------
-# Configuration options related to the alphabetical class index
-#---------------------------------------------------------------------------
-
-# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all
-# compounds will be generated. Enable this if the project contains a lot of
-# classes, structs, unions or interfaces.
-# The default value is: YES.
-
-ALPHABETICAL_INDEX     = YES
-
-# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in
-# which the alphabetical index list will be split.
-# Minimum value: 1, maximum value: 20, default value: 5.
-# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
-
-COLS_IN_ALPHA_INDEX    = 5
-
-# In case all classes in a project start with a common prefix, all classes will
-# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag
-# can be used to specify a prefix (or a list of prefixes) that should be ignored
-# while generating the index headers.
-# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
-
-IGNORE_PREFIX          = 
-
-#---------------------------------------------------------------------------
-# Configuration options related to the HTML output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output
-# The default value is: YES.
-
-GENERATE_HTML          = YES
-
-# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a
-# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
-# it.
-# The default directory is: html.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_OUTPUT            = 0.4
-
-# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each
-# generated HTML page (for example: .htm, .php, .asp).
-# The default value is: .html.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_FILE_EXTENSION    = .html
-
-# The HTML_HEADER tag can be used to specify a user-defined HTML header file for
-# each generated HTML page. If the tag is left blank doxygen will generate a
-# standard header.
-#
-# To get valid HTML the header file that includes any scripts and style sheets
-# that doxygen needs, which is dependent on the configuration options used (e.g.
-# the setting GENERATE_TREEVIEW). It is highly recommended to start with a
-# default header using
-# doxygen -w html new_header.html new_footer.html new_stylesheet.css
-# YourConfigFile
-# and then modify the file new_header.html. See also section "Doxygen usage"
-# for information on how to generate the default header that doxygen normally
-# uses.
-# Note: The header is subject to change so you typically have to regenerate the
-# default header when upgrading to a newer version of doxygen. For a description
-# of the possible markers and block names see the documentation.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_HEADER            = doxygen/header.html
-
-# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each
-# generated HTML page. If the tag is left blank doxygen will generate a standard
-# footer. See HTML_HEADER for more information on how to generate a default
-# footer and what special commands can be used inside the footer. See also
-# section "Doxygen usage" for information on how to generate the default footer
-# that doxygen normally uses.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_FOOTER            = 
-
-# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style
-# sheet that is used by each HTML page. It can be used to fine-tune the look of
-# the HTML output. If left blank doxygen will generate a default style sheet.
-# See also section "Doxygen usage" for information on how to generate the style
-# sheet that doxygen normally uses.
-# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as
-# it is more robust and this tag (HTML_STYLESHEET) will in the future become
-# obsolete.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_STYLESHEET        = 
-
-# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-
-# defined cascading style sheet that is included after the standard style sheets
-# created by doxygen. Using this option one can overrule certain style aspects.
-# This is preferred over using HTML_STYLESHEET since it does not replace the
-# standard style sheet and is therefor more robust against future updates.
-# Doxygen will copy the style sheet file to the output directory. For an example
-# see the documentation.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_EXTRA_STYLESHEET  = 
-
-# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
-# other source files which should be copied to the HTML output directory. Note
-# that these files will be copied to the base HTML output directory. Use the
-# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
-# files. In the HTML_STYLESHEET file, use the file name only. Also note that the
-# files will be copied as-is; there are no commands or markers available.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_EXTRA_FILES       = 
-
-# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen
-# will adjust the colors in the stylesheet and background images according to
-# this color. Hue is specified as an angle on a colorwheel, see
-# http://en.wikipedia.org/wiki/Hue for more information. For instance the value
-# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300
-# purple, and 360 is red again.
-# Minimum value: 0, maximum value: 359, default value: 220.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_COLORSTYLE_HUE    = 220
-
-# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors
-# in the HTML output. For a value of 0 the output will use grayscales only. A
-# value of 255 will produce the most vivid colors.
-# Minimum value: 0, maximum value: 255, default value: 100.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_COLORSTYLE_SAT    = 100
-
-# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the
-# luminance component of the colors in the HTML output. Values below 100
-# gradually make the output lighter, whereas values above 100 make the output
-# darker. The value divided by 100 is the actual gamma applied, so 80 represents
-# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not
-# change the gamma.
-# Minimum value: 40, maximum value: 240, default value: 80.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_COLORSTYLE_GAMMA  = 80
-
-# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
-# page will contain the date and time when the page was generated. Setting this
-# to NO can help when comparing the output of multiple runs.
-# The default value is: YES.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_TIMESTAMP         = YES
-
-# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
-# documentation will contain sections that can be hidden and shown after the
-# page has loaded.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_DYNAMIC_SECTIONS  = NO
-
-# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries
-# shown in the various tree structured indices initially; the user can expand
-# and collapse entries dynamically later on. Doxygen will expand the tree to
-# such a level that at most the specified number of entries are visible (unless
-# a fully collapsed tree already exceeds this amount). So setting the number of
-# entries 1 will produce a full collapsed tree by default. 0 is a special value
-# representing an infinite number of entries and will result in a full expanded
-# tree by default.
-# Minimum value: 0, maximum value: 9999, default value: 100.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-HTML_INDEX_NUM_ENTRIES = 100
-
-# If the GENERATE_DOCSET tag is set to YES, additional index files will be
-# generated that can be used as input for Apple's Xcode 3 integrated development
-# environment (see: http://developer.apple.com/tools/xcode/), introduced with
-# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a
-# Makefile in the HTML output directory. Running make will produce the docset in
-# that directory and running make install will install the docset in
-# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at
-# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
-# for more information.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-GENERATE_DOCSET        = NO
-
-# This tag determines the name of the docset feed. A documentation feed provides
-# an umbrella under which multiple documentation sets from a single provider
-# (such as a company or product suite) can be grouped.
-# The default value is: Doxygen generated docs.
-# This tag requires that the tag GENERATE_DOCSET is set to YES.
-
-DOCSET_FEEDNAME        = "Doxygen generated docs"
-
-# This tag specifies a string that should uniquely identify the documentation
-# set bundle. This should be a reverse domain-name style string, e.g.
-# com.mycompany.MyDocSet. Doxygen will append .docset to the name.
-# The default value is: org.doxygen.Project.
-# This tag requires that the tag GENERATE_DOCSET is set to YES.
-
-DOCSET_BUNDLE_ID       = org.doxygen.Project
-
-# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify
-# the documentation publisher. This should be a reverse domain-name style
-# string, e.g. com.mycompany.MyDocSet.documentation.
-# The default value is: org.doxygen.Publisher.
-# This tag requires that the tag GENERATE_DOCSET is set to YES.
-
-DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
-
-# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.
-# The default value is: Publisher.
-# This tag requires that the tag GENERATE_DOCSET is set to YES.
-
-DOCSET_PUBLISHER_NAME  = Publisher
-
-# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three
-# additional HTML index files: index.hhp, index.hhc, and index.hhk. The
-# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop
-# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on
-# Windows.
-#
-# The HTML Help Workshop contains a compiler that can convert all HTML output
-# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML
-# files are now used as the Windows 98 help format, and will replace the old
-# Windows help format (.hlp) on all Windows platforms in the future. Compressed
-# HTML files also contain an index, a table of contents, and you can search for
-# words in the documentation. The HTML workshop also contains a viewer for
-# compressed HTML files.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-GENERATE_HTMLHELP      = NO
-
-# The CHM_FILE tag can be used to specify the file name of the resulting .chm
-# file. You can add a path in front of the file if the result should not be
-# written to the html output directory.
-# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-
-CHM_FILE               = 
-
-# The HHC_LOCATION tag can be used to specify the location (absolute path
-# including file name) of the HTML help compiler ( hhc.exe). If non-empty
-# doxygen will try to run the HTML help compiler on the generated index.hhp.
-# The file has to be specified with full path.
-# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-
-HHC_LOCATION           = 
-
-# The GENERATE_CHI flag controls if a separate .chi index file is generated (
-# YES) or that it should be included in the master .chm file ( NO).
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-
-GENERATE_CHI           = NO
-
-# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)
-# and project file content.
-# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-
-CHM_INDEX_ENCODING     = 
-
-# The BINARY_TOC flag controls whether a binary table of contents is generated (
-# YES) or a normal table of contents ( NO) in the .chm file.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-
-BINARY_TOC             = NO
-
-# The TOC_EXPAND flag can be set to YES to add extra items for group members to
-# the table of contents of the HTML help documentation and to the tree view.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
-
-TOC_EXPAND             = NO
-
-# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
-# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that
-# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help
-# (.qch) of the generated HTML documentation.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-GENERATE_QHP           = NO
-
-# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify
-# the file name of the resulting .qch file. The path specified is relative to
-# the HTML output folder.
-# This tag requires that the tag GENERATE_QHP is set to YES.
-
-QCH_FILE               = 
-
-# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help
-# Project output. For more information please see Qt Help Project / Namespace
-# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).
-# The default value is: org.doxygen.Project.
-# This tag requires that the tag GENERATE_QHP is set to YES.
-
-QHP_NAMESPACE          = org.doxygen.Project
-
-# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt
-# Help Project output. For more information please see Qt Help Project / Virtual
-# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-
-# folders).
-# The default value is: doc.
-# This tag requires that the tag GENERATE_QHP is set to YES.
-
-QHP_VIRTUAL_FOLDER     = doc
-
-# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom
-# filter to add. For more information please see Qt Help Project / Custom
-# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-
-# filters).
-# This tag requires that the tag GENERATE_QHP is set to YES.
-
-QHP_CUST_FILTER_NAME   = 
-
-# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the
-# custom filter to add. For more information please see Qt Help Project / Custom
-# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-
-# filters).
-# This tag requires that the tag GENERATE_QHP is set to YES.
-
-QHP_CUST_FILTER_ATTRS  = 
-
-# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
-# project's filter section matches. Qt Help Project / Filter Attributes (see:
-# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).
-# This tag requires that the tag GENERATE_QHP is set to YES.
-
-QHP_SECT_FILTER_ATTRS  = 
-
-# The QHG_LOCATION tag can be used to specify the location of Qt's
-# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the
-# generated .qhp file.
-# This tag requires that the tag GENERATE_QHP is set to YES.
-
-QHG_LOCATION           = 
-
-# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be
-# generated, together with the HTML files, they form an Eclipse help plugin. To
-# install this plugin and make it available under the help contents menu in
-# Eclipse, the contents of the directory containing the HTML and XML files needs
-# to be copied into the plugins directory of eclipse. The name of the directory
-# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.
-# After copying Eclipse needs to be restarted before the help appears.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-GENERATE_ECLIPSEHELP   = NO
-
-# A unique identifier for the Eclipse help plugin. When installing the plugin
-# the directory name containing the HTML and XML files should also have this
-# name. Each documentation set should have its own identifier.
-# The default value is: org.doxygen.Project.
-# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.
-
-ECLIPSE_DOC_ID         = org.doxygen.Project
-
-# If you want full control over the layout of the generated HTML pages it might
-# be necessary to disable the index and replace it with your own. The
-# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top
-# of each HTML page. A value of NO enables the index and the value YES disables
-# it. Since the tabs in the index contain the same information as the navigation
-# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-DISABLE_INDEX          = NO
-
-# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
-# structure should be generated to display hierarchical information. If the tag
-# value is set to YES, a side panel will be generated containing a tree-like
-# index structure (just like the one that is generated for HTML Help). For this
-# to work a browser that supports JavaScript, DHTML, CSS and frames is required
-# (i.e. any modern browser). Windows users are probably better off using the
-# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can
-# further fine-tune the look of the index. As an example, the default style
-# sheet generated by doxygen has an example that shows how to put an image at
-# the root of the tree instead of the PROJECT_NAME. Since the tree basically has
-# the same information as the tab index, you could consider setting
-# DISABLE_INDEX to YES when enabling this option.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-GENERATE_TREEVIEW      = YES
-
-# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
-# doxygen will group on one line in the generated HTML documentation.
-#
-# Note that a value of 0 will completely suppress the enum values from appearing
-# in the overview section.
-# Minimum value: 0, maximum value: 20, default value: 4.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-ENUM_VALUES_PER_LINE   = 4
-
-# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used
-# to set the initial width (in pixels) of the frame in which the tree is shown.
-# Minimum value: 0, maximum value: 1500, default value: 250.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-TREEVIEW_WIDTH         = 250
-
-# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to
-# external symbols imported via tag files in a separate window.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-EXT_LINKS_IN_WINDOW    = NO
-
-# Use this tag to change the font size of LaTeX formulas included as images in
-# the HTML documentation. When you change the font size after a successful
-# doxygen run you need to manually remove any form_*.png images from the HTML
-# output directory to force them to be regenerated.
-# Minimum value: 8, maximum value: 50, default value: 10.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-FORMULA_FONTSIZE       = 10
-
-# Use the FORMULA_TRANPARENT tag to determine whether or not the images
-# generated for formulas are transparent PNGs. Transparent PNGs are not
-# supported properly for IE 6.0, but are supported on all modern browsers.
-#
-# Note that when changing this option you need to delete any form_*.png files in
-# the HTML output directory before the changes have effect.
-# The default value is: YES.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-FORMULA_TRANSPARENT    = YES
-
-# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see
-# http://www.mathjax.org) which uses client side Javascript for the rendering
-# instead of using prerendered bitmaps. Use this if you do not have LaTeX
-# installed or if you want to formulas look prettier in the HTML output. When
-# enabled you may also need to install MathJax separately and configure the path
-# to it using the MATHJAX_RELPATH option.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-USE_MATHJAX            = NO
-
-# When MathJax is enabled you can set the default output format to be used for
-# the MathJax output. See the MathJax site (see:
-# http://docs.mathjax.org/en/latest/output.html) for more details.
-# Possible values are: HTML-CSS (which is slower, but has the best
-# compatibility), NativeMML (i.e. MathML) and SVG.
-# The default value is: HTML-CSS.
-# This tag requires that the tag USE_MATHJAX is set to YES.
-
-MATHJAX_FORMAT         = HTML-CSS
-
-# When MathJax is enabled you need to specify the location relative to the HTML
-# output directory using the MATHJAX_RELPATH option. The destination directory
-# should contain the MathJax.js script. For instance, if the mathjax directory
-# is located at the same level as the HTML output directory, then
-# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax
-# Content Delivery Network so you can quickly see the result without installing
-# MathJax. However, it is strongly recommended to install a local copy of
-# MathJax from http://www.mathjax.org before deployment.
-# The default value is: http://cdn.mathjax.org/mathjax/latest.
-# This tag requires that the tag USE_MATHJAX is set to YES.
-
-MATHJAX_RELPATH        = http://cdn.mathjax.org/mathjax/latest
-
-# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax
-# extension names that should be enabled during MathJax rendering. For example
-# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols
-# This tag requires that the tag USE_MATHJAX is set to YES.
-
-MATHJAX_EXTENSIONS     = 
-
-# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces
-# of code that will be used on startup of the MathJax code. See the MathJax site
-# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an
-# example see the documentation.
-# This tag requires that the tag USE_MATHJAX is set to YES.
-
-MATHJAX_CODEFILE       = 
-
-# When the SEARCHENGINE tag is enabled doxygen will generate a search box for
-# the HTML output. The underlying search engine uses javascript and DHTML and
-# should work on any modern browser. Note that when using HTML help
-# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)
-# there is already a search function so this one should typically be disabled.
-# For large projects the javascript based search engine can be slow, then
-# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to
-# search using the keyboard; to jump to the search box use <access key> + S
-# (what the <access key> is depends on the OS and browser, but it is typically
-# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down
-# key> to jump into the search results window, the results can be navigated
-# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel
-# the search. The filter options can be selected when the cursor is inside the
-# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>
-# to select a filter and <Enter> or <escape> to activate or cancel the filter
-# option.
-# The default value is: YES.
-# This tag requires that the tag GENERATE_HTML is set to YES.
-
-SEARCHENGINE           = YES
-
-# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
-# implemented using a web server instead of a web client using Javascript. There
-# are two flavours of web server based searching depending on the
-# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for
-# searching and an index file used by the script. When EXTERNAL_SEARCH is
-# enabled the indexing and searching needs to be provided by external tools. See
-# the section "External Indexing and Searching" for details.
-# The default value is: NO.
-# This tag requires that the tag SEARCHENGINE is set to YES.
-
-SERVER_BASED_SEARCH    = NO
-
-# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP
-# script for searching. Instead the search results are written to an XML file
-# which needs to be processed by an external indexer. Doxygen will invoke an
-# external search engine pointed to by the SEARCHENGINE_URL option to obtain the
-# search results.
-#
-# Doxygen ships with an example indexer ( doxyindexer) and search engine
-# (doxysearch.cgi) which are based on the open source search engine library
-# Xapian (see: http://xapian.org/).
-#
-# See the section "External Indexing and Searching" for details.
-# The default value is: NO.
-# This tag requires that the tag SEARCHENGINE is set to YES.
-
-EXTERNAL_SEARCH        = NO
-
-# The SEARCHENGINE_URL should point to a search engine hosted by a web server
-# which will return the search results when EXTERNAL_SEARCH is enabled.
-#
-# Doxygen ships with an example indexer ( doxyindexer) and search engine
-# (doxysearch.cgi) which are based on the open source search engine library
-# Xapian (see: http://xapian.org/). See the section "External Indexing and
-# Searching" for details.
-# This tag requires that the tag SEARCHENGINE is set to YES.
-
-SEARCHENGINE_URL       = 
-
-# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed
-# search data is written to a file for indexing by an external tool. With the
-# SEARCHDATA_FILE tag the name of this file can be specified.
-# The default file is: searchdata.xml.
-# This tag requires that the tag SEARCHENGINE is set to YES.
-
-SEARCHDATA_FILE        = searchdata.xml
-
-# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the
-# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is
-# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple
-# projects and redirect the results back to the right project.
-# This tag requires that the tag SEARCHENGINE is set to YES.
-
-EXTERNAL_SEARCH_ID     = 
-
-# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen
-# projects other than the one defined by this configuration file, but that are
-# all added to the same external search index. Each project needs to have a
-# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of
-# to a relative location where the documentation can be found. The format is:
-# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...
-# This tag requires that the tag SEARCHENGINE is set to YES.
-
-EXTRA_SEARCH_MAPPINGS  = 
-
-#---------------------------------------------------------------------------
-# Configuration options related to the LaTeX output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.
-# The default value is: YES.
-
-GENERATE_LATEX         = NO
-
-# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a
-# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
-# it.
-# The default directory is: latex.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-LATEX_OUTPUT           = latex
-
-# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
-# invoked.
-#
-# Note that when enabling USE_PDFLATEX this option is only used for generating
-# bitmaps for formulas in the HTML output, but not in the Makefile that is
-# written to the output directory.
-# The default file is: latex.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-LATEX_CMD_NAME         = latex
-
-# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate
-# index for LaTeX.
-# The default file is: makeindex.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-MAKEINDEX_CMD_NAME     = makeindex
-
-# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX
-# documents. This may be useful for small projects and may help to save some
-# trees in general.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-COMPACT_LATEX          = NO
-
-# The PAPER_TYPE tag can be used to set the paper type that is used by the
-# printer.
-# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x
-# 14 inches) and executive (7.25 x 10.5 inches).
-# The default value is: a4.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-PAPER_TYPE             = a4
-
-# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names
-# that should be included in the LaTeX output. To get the times font for
-# instance you can specify
-# EXTRA_PACKAGES=times
-# If left blank no extra packages will be included.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-EXTRA_PACKAGES         = 
-
-# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the
-# generated LaTeX document. The header should contain everything until the first
-# chapter. If it is left blank doxygen will generate a standard header. See
-# section "Doxygen usage" for information on how to let doxygen write the
-# default header to a separate file.
-#
-# Note: Only use a user-defined header if you know what you are doing! The
-# following commands have a special meaning inside the header: $title,
-# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will
-# replace them by respectively the title of the page, the current date and time,
-# only the current date, the version number of doxygen, the project name (see
-# PROJECT_NAME), or the project number (see PROJECT_NUMBER).
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-LATEX_HEADER           = 
-
-# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the
-# generated LaTeX document. The footer should contain everything after the last
-# chapter. If it is left blank doxygen will generate a standard footer.
-#
-# Note: Only use a user-defined footer if you know what you are doing!
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-LATEX_FOOTER           = 
-
-# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or
-# other source files which should be copied to the LATEX_OUTPUT output
-# directory. Note that the files will be copied as-is; there are no commands or
-# markers available.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-LATEX_EXTRA_FILES      = 
-
-# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is
-# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will
-# contain links (just like the HTML output) instead of page references. This
-# makes the output suitable for online browsing using a PDF viewer.
-# The default value is: YES.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-PDF_HYPERLINKS         = YES
-
-# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate
-# the PDF file directly from the LaTeX files. Set this option to YES to get a
-# higher quality PDF documentation.
-# The default value is: YES.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-USE_PDFLATEX           = YES
-
-# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \batchmode
-# command to the generated LaTeX files. This will instruct LaTeX to keep running
-# if errors occur, instead of asking the user for help. This option is also used
-# when generating formulas in HTML.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-LATEX_BATCHMODE        = NO
-
-# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the
-# index chapters (such as File Index, Compound Index, etc.) in the output.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-LATEX_HIDE_INDICES     = NO
-
-# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source
-# code with syntax highlighting in the LaTeX output.
-#
-# Note that which sources are shown also depends on other settings such as
-# SOURCE_BROWSER.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-LATEX_SOURCE_CODE      = NO
-
-# The LATEX_BIB_STYLE tag can be used to specify the style to use for the
-# bibliography, e.g. plainnat, or ieeetr. See
-# http://en.wikipedia.org/wiki/BibTeX and \cite for more info.
-# The default value is: plain.
-# This tag requires that the tag GENERATE_LATEX is set to YES.
-
-LATEX_BIB_STYLE        = plain
-
-#---------------------------------------------------------------------------
-# Configuration options related to the RTF output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The
-# RTF output is optimized for Word 97 and may not look too pretty with other RTF
-# readers/editors.
-# The default value is: NO.
-
-GENERATE_RTF           = NO
-
-# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a
-# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
-# it.
-# The default directory is: rtf.
-# This tag requires that the tag GENERATE_RTF is set to YES.
-
-RTF_OUTPUT             = rtf
-
-# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF
-# documents. This may be useful for small projects and may help to save some
-# trees in general.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_RTF is set to YES.
-
-COMPACT_RTF            = NO
-
-# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will
-# contain hyperlink fields. The RTF file will contain links (just like the HTML
-# output) instead of page references. This makes the output suitable for online
-# browsing using Word or some other Word compatible readers that support those
-# fields.
-#
-# Note: WordPad (write) and others do not support links.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_RTF is set to YES.
-
-RTF_HYPERLINKS         = NO
-
-# Load stylesheet definitions from file. Syntax is similar to doxygen's config
-# file, i.e. a series of assignments. You only have to provide replacements,
-# missing definitions are set to their default value.
-#
-# See also section "Doxygen usage" for information on how to generate the
-# default style sheet that doxygen normally uses.
-# This tag requires that the tag GENERATE_RTF is set to YES.
-
-RTF_STYLESHEET_FILE    = 
-
-# Set optional variables used in the generation of an RTF document. Syntax is
-# similar to doxygen's config file. A template extensions file can be generated
-# using doxygen -e rtf extensionFile.
-# This tag requires that the tag GENERATE_RTF is set to YES.
-
-RTF_EXTENSIONS_FILE    = 
-
-#---------------------------------------------------------------------------
-# Configuration options related to the man page output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for
-# classes and files.
-# The default value is: NO.
-
-GENERATE_MAN           = NO
-
-# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a
-# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
-# it. A directory man3 will be created inside the directory specified by
-# MAN_OUTPUT.
-# The default directory is: man.
-# This tag requires that the tag GENERATE_MAN is set to YES.
-
-MAN_OUTPUT             = man
-
-# The MAN_EXTENSION tag determines the extension that is added to the generated
-# man pages. In case the manual section does not start with a number, the number
-# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is
-# optional.
-# The default value is: .3.
-# This tag requires that the tag GENERATE_MAN is set to YES.
-
-MAN_EXTENSION          = .3
-
-# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
-# will generate one additional man file for each entity documented in the real
-# man page(s). These additional files only source the real man page, but without
-# them the man command would be unable to find the correct page.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_MAN is set to YES.
-
-MAN_LINKS              = NO
-
-#---------------------------------------------------------------------------
-# Configuration options related to the XML output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that
-# captures the structure of the code including all documentation.
-# The default value is: NO.
-
-GENERATE_XML           = NO
-
-# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a
-# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
-# it.
-# The default directory is: xml.
-# This tag requires that the tag GENERATE_XML is set to YES.
-
-XML_OUTPUT             = xml
-
-# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a
-# validating XML parser to check the syntax of the XML files.
-# This tag requires that the tag GENERATE_XML is set to YES.
-
-XML_SCHEMA             = 
-
-# The XML_DTD tag can be used to specify a XML DTD, which can be used by a
-# validating XML parser to check the syntax of the XML files.
-# This tag requires that the tag GENERATE_XML is set to YES.
-
-XML_DTD                = 
-
-# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program
-# listings (including syntax highlighting and cross-referencing information) to
-# the XML output. Note that enabling this will significantly increase the size
-# of the XML output.
-# The default value is: YES.
-# This tag requires that the tag GENERATE_XML is set to YES.
-
-XML_PROGRAMLISTING     = YES
-
-#---------------------------------------------------------------------------
-# Configuration options related to the DOCBOOK output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_DOCBOOK tag is set to YES doxygen will generate Docbook files
-# that can be used to generate PDF.
-# The default value is: NO.
-
-GENERATE_DOCBOOK       = NO
-
-# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.
-# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in
-# front of it.
-# The default directory is: docbook.
-# This tag requires that the tag GENERATE_DOCBOOK is set to YES.
-
-DOCBOOK_OUTPUT         = docbook
-
-#---------------------------------------------------------------------------
-# Configuration options for the AutoGen Definitions output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_AUTOGEN_DEF tag is set to YES doxygen will generate an AutoGen
-# Definitions (see http://autogen.sf.net) file that captures the structure of
-# the code including all documentation. Note that this feature is still
-# experimental and incomplete at the moment.
-# The default value is: NO.
-
-GENERATE_AUTOGEN_DEF   = NO
-
-#---------------------------------------------------------------------------
-# Configuration options related to the Perl module output
-#---------------------------------------------------------------------------
-
-# If the GENERATE_PERLMOD tag is set to YES doxygen will generate a Perl module
-# file that captures the structure of the code including all documentation.
-#
-# Note that this feature is still experimental and incomplete at the moment.
-# The default value is: NO.
-
-GENERATE_PERLMOD       = NO
-
-# If the PERLMOD_LATEX tag is set to YES doxygen will generate the necessary
-# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI
-# output from the Perl module output.
-# The default value is: NO.
-# This tag requires that the tag GENERATE_PERLMOD is set to YES.
-
-PERLMOD_LATEX          = NO
-
-# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be nicely
-# formatted so it can be parsed by a human reader. This is useful if you want to
-# understand what is going on. On the other hand, if this tag is set to NO the
-# size of the Perl module output will be much smaller and Perl will parse it
-# just the same.
-# The default value is: YES.
-# This tag requires that the tag GENERATE_PERLMOD is set to YES.
-
-PERLMOD_PRETTY         = YES
-
-# The names of the make variables in the generated doxyrules.make file are
-# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful
-# so different doxyrules.make files included by the same Makefile don't
-# overwrite each other's variables.
-# This tag requires that the tag GENERATE_PERLMOD is set to YES.
-
-PERLMOD_MAKEVAR_PREFIX = 
-
-#---------------------------------------------------------------------------
-# Configuration options related to the preprocessor
-#---------------------------------------------------------------------------
-
-# If the ENABLE_PREPROCESSING tag is set to YES doxygen will evaluate all
-# C-preprocessor directives found in the sources and include files.
-# The default value is: YES.
-
-ENABLE_PREPROCESSING   = YES
-
-# If the MACRO_EXPANSION tag is set to YES doxygen will expand all macro names
-# in the source code. If set to NO only conditional compilation will be
-# performed. Macro expansion can be done in a controlled way by setting
-# EXPAND_ONLY_PREDEF to YES.
-# The default value is: NO.
-# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-
-MACRO_EXPANSION        = YES
-
-# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then
-# the macro expansion is limited to the macros specified with the PREDEFINED and
-# EXPAND_AS_DEFINED tags.
-# The default value is: NO.
-# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-
-EXPAND_ONLY_PREDEF     = YES
-
-# If the SEARCH_INCLUDES tag is set to YES the includes files in the
-# INCLUDE_PATH will be searched if a #include is found.
-# The default value is: YES.
-# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-
-SEARCH_INCLUDES        = YES
-
-# The INCLUDE_PATH tag can be used to specify one or more directories that
-# contain include files that are not input files but should be processed by the
-# preprocessor.
-# This tag requires that the tag SEARCH_INCLUDES is set to YES.
-
-INCLUDE_PATH           = 
-
-# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
-# patterns (like *.h and *.hpp) to filter out the header-files in the
-# directories. If left blank, the patterns specified with FILE_PATTERNS will be
-# used.
-# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-
-INCLUDE_FILE_PATTERNS  = 
-
-# The PREDEFINED tag can be used to specify one or more macro names that are
-# defined before the preprocessor is started (similar to the -D option of e.g.
-# gcc). The argument of the tag is a list of macros of the form: name or
-# name=definition (no spaces). If the definition and the "=" are omitted, "=1"
-# is assumed. To prevent a macro definition from being undefined via #undef or
-# recursively expanded use the := operator instead of the = operator.
-# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-
-PREDEFINED             = CFG_TUSB_CONTROLLER_0_MODE=TUSB_MODE_HOST \
-                         CFG_TUSB_CONTROLLER_1_MODE=TUSB_MODE_NONE \
-                         CFG_TUSB_HOST_HID_KEYBOARD=1 \
-                         ATTR_PACKED_STRUCT(x)=x \
-                         CFG_TUSB_HOST_CDC_RNDIS=1 \
-                         ATTR_ALIGNED(x)= \
-                         CFG_TUSB_OS=TUSB_OS_NONE
-
-# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this
-# tag can be used to specify a list of macro names that should be expanded. The
-# macro definition that is found in the sources will be used. Use the PREDEFINED
-# tag if you want to use a different macro definition that overrules the
-# definition found in the source code.
-# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-
-EXPAND_AS_DEFINED      = 
-
-# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will
-# remove all refrences to function-like macros that are alone on a line, have an
-# all uppercase name, and do not end with a semicolon. Such function macros are
-# typically used for boiler-plate code, and will confuse the parser if not
-# removed.
-# The default value is: YES.
-# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
-
-SKIP_FUNCTION_MACROS   = YES
-
-#---------------------------------------------------------------------------
-# Configuration options related to external references
-#---------------------------------------------------------------------------
-
-# The TAGFILES tag can be used to specify one or more tag files. For each tag
-# file the location of the external documentation should be added. The format of
-# a tag file without this location is as follows:
-# TAGFILES = file1 file2 ...
-# Adding location for the tag files is done as follows:
-# TAGFILES = file1=loc1 "file2 = loc2" ...
-# where loc1 and loc2 can be relative or absolute paths or URLs. See the
-# section "Linking to external documentation" for more information about the use
-# of tag files.
-# Note: Each tag file must have an unique name (where the name does NOT include
-# the path). If a tag file is not located in the directory in which doxygen is
-# run, you must also specify the path to the tagfile here.
-
-TAGFILES               = 
-
-# When a file name is specified after GENERATE_TAGFILE, doxygen will create a
-# tag file that is based on the input files it reads. See section "Linking to
-# external documentation" for more information about the usage of tag files.
-
-GENERATE_TAGFILE       = 
-
-# If the ALLEXTERNALS tag is set to YES all external class will be listed in the
-# class index. If set to NO only the inherited external classes will be listed.
-# The default value is: NO.
-
-ALLEXTERNALS           = NO
-
-# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed in
-# the modules index. If set to NO, only the current project's groups will be
-# listed.
-# The default value is: YES.
-
-EXTERNAL_GROUPS        = YES
-
-# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed in
-# the related pages index. If set to NO, only the current project's pages will
-# be listed.
-# The default value is: YES.
-
-EXTERNAL_PAGES         = YES
-
-# The PERL_PATH should be the absolute path and name of the perl script
-# interpreter (i.e. the result of 'which perl').
-# The default file (with absolute path) is: /usr/bin/perl.
-
-PERL_PATH              = /usr/bin/perl
-
-#---------------------------------------------------------------------------
-# Configuration options related to the dot tool
-#---------------------------------------------------------------------------
-
-# If the CLASS_DIAGRAMS tag is set to YES doxygen will generate a class diagram
-# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to
-# NO turns the diagrams off. Note that this option also works with HAVE_DOT
-# disabled, but it is recommended to install and use dot, since it yields more
-# powerful graphs.
-# The default value is: YES.
-
-CLASS_DIAGRAMS         = YES
-
-# You can define message sequence charts within doxygen comments using the \msc
-# command. Doxygen will then run the mscgen tool (see:
-# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the
-# documentation. The MSCGEN_PATH tag allows you to specify the directory where
-# the mscgen tool resides. If left empty the tool is assumed to be found in the
-# default search path.
-
-MSCGEN_PATH            = 
-
-# You can include diagrams made with dia in doxygen documentation. Doxygen will
-# then run dia to produce the diagram and insert it in the documentation. The
-# DIA_PATH tag allows you to specify the directory where the dia binary resides.
-# If left empty dia is assumed to be found in the default search path.
-
-DIA_PATH               = 
-
-# If set to YES, the inheritance and collaboration graphs will hide inheritance
-# and usage relations if the target is undocumented or is not a class.
-# The default value is: YES.
-
-HIDE_UNDOC_RELATIONS   = YES
-
-# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
-# available from the path. This tool is part of Graphviz (see:
-# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent
-# Bell Labs. The other options in this section have no effect if this option is
-# set to NO
-# The default value is: NO.
-
-HAVE_DOT               = NO
-
-# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed
-# to run in parallel. When set to 0 doxygen will base this on the number of
-# processors available in the system. You can set it explicitly to a value
-# larger than 0 to get control over the balance between CPU load and processing
-# speed.
-# Minimum value: 0, maximum value: 32, default value: 0.
-# This tag requires that the tag HAVE_DOT is set to YES.
-
-DOT_NUM_THREADS        = 0
-
-# When you want a differently looking font n the dot files that doxygen
-# generates you can specify the font name using DOT_FONTNAME. You need to make
-# sure dot is able to find the font, which can be done by putting it in a
-# standard location or by setting the DOTFONTPATH environment variable or by
-# setting DOT_FONTPATH to the directory containing the font.
-# The default value is: Helvetica.
-# This tag requires that the tag HAVE_DOT is set to YES.
-
-DOT_FONTNAME           = Helvetica
-
-# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of
-# dot graphs.
-# Minimum value: 4, maximum value: 24, default value: 10.
-# This tag requires that the tag HAVE_DOT is set to YES.
-
-DOT_FONTSIZE           = 10
-
-# By default doxygen will tell dot to use the default font as specified with
-# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set
-# the path where dot can find it using this tag.
-# This tag requires that the tag HAVE_DOT is set to YES.
-
-DOT_FONTPATH           = 
-
-# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for
-# each documented class showing the direct and indirect inheritance relations.
-# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.
-# The default value is: YES.
-# This tag requires that the tag HAVE_DOT is set to YES.
-
-CLASS_GRAPH            = YES
-
-# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a
-# graph for each documented class showing the direct and indirect implementation
-# dependencies (inheritance, containment, and class references variables) of the
-# class with other documented classes.
-# The default value is: YES.
-# This tag requires that the tag HAVE_DOT is set to YES.
-
-COLLABORATION_GRAPH    = YES
-
-# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for
-# groups, showing the direct groups dependencies.
-# The default value is: YES.
-# This tag requires that the tag HAVE_DOT is set to YES.
-
-GROUP_GRAPHS           = YES
-
-# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
-# collaboration diagrams in a style similar to the OMG's Unified Modeling
-# Language.
-# The default value is: NO.
-# This tag requires that the tag HAVE_DOT is set to YES.
-
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From 0da08031eaf62dd7dc4b490fc0c5bcd268a6bc5e Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Tue, 27 Jul 2021 20:18:39 +0100
Subject: [PATCH 0278/2085] readme: added docs status badge

Signed-off-by: perigoso <perigoso@riseup.net>
---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 95486ecd9..81864252f 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
 ![TinyUSB](docs/assets/logo.svg)
 
-[![Build Status](https://github.com/hathach/tinyusb/workflows/Build/badge.svg)](https://github.com/hathach/tinyusb/actions) [![License](https://img.shields.io/badge/license-MIT-brightgreen.svg)](https://opensource.org/licenses/MIT)
+[![Build Status](https://github.com/hathach/tinyusb/workflows/Build/badge.svg)](https://github.com/hathach/tinyusb/actions) [![Documentation Status](https://readthedocs.org/projects/tinyusb/badge/?version=latest)](https://openinput.readthedocs.io/en/latest/?badge=latest) [![License](https://img.shields.io/badge/license-MIT-brightgreen.svg)](https://opensource.org/licenses/MIT)
 
 TinyUSB is an open-source cross-platform USB Host/Device stack for embedded system, designed to be memory-safe with no dynamic allocation and thread-safe with all interrupt events are deferred then handled in the non-ISR task function.
 

From 83d72cc1d568d509ca2c7bd8d0e959db22c90924 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Wed, 28 Jul 2021 00:36:18 +0100
Subject: [PATCH 0279/2085] docs/contributors: add credit for docs

Signed-off-by: perigoso <perigoso@riseup.net>
---
 CONTRIBUTORS.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index b1ebb10ef..4466fdd8e 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -104,6 +104,7 @@ Notable contributors
 ----------------------------------------------
 
 -  Add new DCD port for Silabs EFM32GG12 with SLTB009A board
+-  Rewrite documentation in rst and setup for readthedocs
 
 
 `Raspberry Pi Team <https://github.com/raspberrypi>`__

From a6ae310f5f64ecc6a0db84d5a34e7edd273b9ca2 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Fri, 30 Jul 2021 11:17:09 +0100
Subject: [PATCH 0280/2085] readme: convert md readme to rst

Signed-off-by: perigoso <perigoso@riseup.net>
---
 README.md  | 16 ----------------
 README.rst | 37 +++++++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+), 16 deletions(-)
 delete mode 100644 README.md
 create mode 100644 README.rst

diff --git a/README.md b/README.md
deleted file mode 100644
index 81864252f..000000000
--- a/README.md
+++ /dev/null
@@ -1,16 +0,0 @@
-![TinyUSB](docs/assets/logo.svg)
-
-[![Build Status](https://github.com/hathach/tinyusb/workflows/Build/badge.svg)](https://github.com/hathach/tinyusb/actions) [![Documentation Status](https://readthedocs.org/projects/tinyusb/badge/?version=latest)](https://openinput.readthedocs.io/en/latest/?badge=latest) [![License](https://img.shields.io/badge/license-MIT-brightgreen.svg)](https://opensource.org/licenses/MIT)
-
-TinyUSB is an open-source cross-platform USB Host/Device stack for embedded system, designed to be memory-safe with no dynamic allocation and thread-safe with all interrupt events are deferred then handled in the non-ISR task function.
-
-Please head over to the online [documentation](www.tinyusb.org) for more info.
-
-## Contributors
-
-Special thanks to all the people who spent their precious time and effort to help this project so far. Check out the 
-[CONTRIBUTORS](CONTRIBUTORS.rst) file for the list of all contributors and their awesome work for the stack.
-
-## License
-
-All TinyUSB sources in the `src` folder are licensed under MIT license, [Full license is here](LICENSE). However, each file can be individually licensed especially those in `lib` and `hw/mcu` folder. Please make sure you understand all the license term for files you use in your project.
diff --git a/README.rst b/README.rst
new file mode 100644
index 000000000..ace572552
--- /dev/null
+++ b/README.rst
@@ -0,0 +1,37 @@
+.. figure:: docs/assets/logo.svg
+   :alt: TinyUSB
+
+   TinyUSB
+
+|Build Status| |Documentation Status| |License|
+
+TinyUSB is an open-source cross-platform USB Host/Device stack for
+embedded system, designed to be memory-safe with no dynamic allocation
+and thread-safe with all interrupt events are deferred then handled in
+the non-ISR task function.
+
+Please take a look at the online `documentation <www.tinyusb.org>`__.
+
+Contributors
+============
+
+Special thanks to all the people who spent their precious time and
+effort to help this project so far. Check out the
+`CONTRIBUTORS <CONTRIBUTORS.rst>`__ file for the list of all
+contributors and their awesome work for the stack.
+
+License
+=======
+
+All TinyUSB sources in the ``src`` folder are licensed under MIT
+license, `Full license is here <LICENSE>`__. However, each file can be
+individually licensed especially those in ``lib`` and ``hw/mcu`` folder.
+Please make sure you understand all the license term for files you use
+in your project.
+
+.. |Build Status| image:: https://github.com/hathach/tinyusb/workflows/Build/badge.svg
+   :target: https://github.com/hathach/tinyusb/actions
+.. |Documentation Status| image:: https://readthedocs.org/projects/tinyusb/badge/?version=latest
+   :target: https://openinput.readthedocs.io/en/latest/?badge=latest
+.. |License| image:: https://img.shields.io/badge/license-MIT-brightgreen.svg
+   :target: https://opensource.org/licenses/MIT

From 0e6e137f5dfd7ea5dd287ed8b6da7faab554fdd9 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Fri, 30 Jul 2021 11:26:14 +0100
Subject: [PATCH 0281/2085] readme: add local links to documentation

Signed-off-by: perigoso <perigoso@riseup.net>
---
 README.rst | 41 +++++++++++++++++++++++++++++++++--------
 1 file changed, 33 insertions(+), 8 deletions(-)

diff --git a/README.rst b/README.rst
index ace572552..b738c7894 100644
--- a/README.rst
+++ b/README.rst
@@ -1,8 +1,6 @@
 .. figure:: docs/assets/logo.svg
    :alt: TinyUSB
 
-   TinyUSB
-
 |Build Status| |Documentation Status| |License|
 
 TinyUSB is an open-source cross-platform USB Host/Device stack for
@@ -12,13 +10,26 @@ the non-ISR task function.
 
 Please take a look at the online `documentation <www.tinyusb.org>`__.
 
-Contributors
-============
+Local Docs
+==========
 
-Special thanks to all the people who spent their precious time and
-effort to help this project so far. Check out the
-`CONTRIBUTORS <CONTRIBUTORS.rst>`__ file for the list of all
-contributors and their awesome work for the stack.
+- Info
+
+  - `Uses`_
+  - `Changelog`_
+  - `Contributors`_
+
+- `Reference`_
+
+  - `Supported Devices`_
+  - `Gettin Started`_
+  - `Concurrency`_
+
+- `Contributing`_
+
+  - `Code of Conduct`_
+  - `Structure`_
+  - `Porting`_
 
 License
 =======
@@ -29,9 +40,23 @@ individually licensed especially those in ``lib`` and ``hw/mcu`` folder.
 Please make sure you understand all the license term for files you use
 in your project.
 
+
 .. |Build Status| image:: https://github.com/hathach/tinyusb/workflows/Build/badge.svg
    :target: https://github.com/hathach/tinyusb/actions
 .. |Documentation Status| image:: https://readthedocs.org/projects/tinyusb/badge/?version=latest
    :target: https://openinput.readthedocs.io/en/latest/?badge=latest
 .. |License| image:: https://img.shields.io/badge/license-MIT-brightgreen.svg
    :target: https://opensource.org/licenses/MIT
+
+
+.. _Uses: docs/info/uses.rst
+.. _Changelog: docs/info/changelog.rst
+.. _Contributors: CONTRIBUTORS.rst
+.. _Reference: docs/reference/index.rst
+.. _Supported Devices: docs/reference/supported.rst
+.. _Gettin Started: docs/reference/getting_started.rst
+.. _Concurrency: docs/reference/concurrency.rst
+.. _Contributing: docs/contributing/index.rst
+.. _Code of Conduct: CODE_OF_CONDUCT.rst
+.. _Structure: docs/contributing/structure.rst
+.. _Porting: docs/contributing/porting.rst

From 1a27dad7bb0ecec1b52159a6c96aa4d86b560d87 Mon Sep 17 00:00:00 2001
From: perigoso <perigoso@riseup.net>
Date: Fri, 30 Jul 2021 12:48:08 +0100
Subject: [PATCH 0282/2085] docs/supported: add Waveshare OpenH743I-C to board
 support list

Signed-off-by: perigoso <perigoso@riseup.net>
---
 docs/reference/supported.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index e280e10a4..0028744f6 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -323,6 +323,7 @@ ST STM32
 -  `STM32 H743zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-h743zi.html>`__
 -  `STM32 H743i Evaluation <https://www.st.com/en/evaluation-tools/stm32h743i-eval.html>`__
 -  `STM32 H745i Discovery <https://www.st.com/en/evaluation-tools/stm32h745i-disco.html>`__
+-  `Waveshare OpenH743I-C <https://www.waveshare.com/openh743i-c-standard.htm>`__
 
 TI
 --

From 383290a634a562edc081a3935aba8073d35657c3 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 30 Jul 2021 19:43:04 +0200
Subject: [PATCH 0283/2085] Move register define to separate header.

---
 .../microchip/samx7x/common_usb_regs.h        | 2108 +++++++++++++++++
 src/portable/microchip/samx7x/dcd_samx7x.c    |  291 ++-
 2 files changed, 2250 insertions(+), 149 deletions(-)
 create mode 100644 src/portable/microchip/samx7x/common_usb_regs.h

diff --git a/src/portable/microchip/samx7x/common_usb_regs.h b/src/portable/microchip/samx7x/common_usb_regs.h
new file mode 100644
index 000000000..d232f0bcb
--- /dev/null
+++ b/src/portable/microchip/samx7x/common_usb_regs.h
@@ -0,0 +1,2108 @@
+ /*
+* The MIT License (MIT)
+*
+* Copyright (c) 2019 Microchip Technology Inc.
+* Copyright (c) 2018, hathach (tinyusb.org)
+* Copyright (c) 2021, HiFiPhile
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+* This file is part of the TinyUSB stack.
+*/
+
+#ifndef _COMMON_USB_REGS_H_
+#define _COMMON_USB_REGS_H_
+
+#if CFG_TUSB_MCU == OPT_MCU_SAMX7X
+
+/* -------- DEVDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Device DMA Channel Next Descriptor Address Register -------- */
+
+#define DEVDMANXTDSC_OFFSET           (0x00)                                        /**<  (DEVDMANXTDSC) Device DMA Channel Next Descriptor Address Register  Offset */
+
+#define DEVDMANXTDSC_NXT_DSC_ADD_Pos  0                                              /**< (DEVDMANXTDSC) Next Descriptor Address Position */
+#define DEVDMANXTDSC_NXT_DSC_ADD      (_U_(0xFFFFFFFF) << DEVDMANXTDSC_NXT_DSC_ADD_Pos)  /**< (DEVDMANXTDSC) Next Descriptor Address Mask */
+#define DEVDMANXTDSC_Msk              _U_(0xFFFFFFFF)                                /**< (DEVDMANXTDSC) Register Mask  */
+
+
+/* -------- DEVDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Device DMA Channel Address Register -------- */
+
+#define DEVDMAADDRESS_OFFSET          (0x04)                                        /**<  (DEVDMAADDRESS) Device DMA Channel Address Register  Offset */
+
+#define DEVDMAADDRESS_BUFF_ADD_Pos    0                                              /**< (DEVDMAADDRESS) Buffer Address Position */
+#define DEVDMAADDRESS_BUFF_ADD        (_U_(0xFFFFFFFF) << DEVDMAADDRESS_BUFF_ADD_Pos)  /**< (DEVDMAADDRESS) Buffer Address Mask */
+#define DEVDMAADDRESS_Msk             _U_(0xFFFFFFFF)                                /**< (DEVDMAADDRESS) Register Mask  */
+
+
+/* -------- DEVDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Device DMA Channel Control Register -------- */
+
+#define DEVDMACONTROL_OFFSET          (0x08)                                        /**<  (DEVDMACONTROL) Device DMA Channel Control Register  Offset */
+
+#define DEVDMACONTROL_CHANN_ENB_Pos   0                                              /**< (DEVDMACONTROL) Channel Enable Command Position */
+#define DEVDMACONTROL_CHANN_ENB       (_U_(0x1) << DEVDMACONTROL_CHANN_ENB_Pos)  /**< (DEVDMACONTROL) Channel Enable Command Mask */
+#define DEVDMACONTROL_LDNXT_DSC_Pos   1                                              /**< (DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */
+#define DEVDMACONTROL_LDNXT_DSC       (_U_(0x1) << DEVDMACONTROL_LDNXT_DSC_Pos)  /**< (DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */
+#define DEVDMACONTROL_END_TR_EN_Pos   2                                              /**< (DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */
+#define DEVDMACONTROL_END_TR_EN       (_U_(0x1) << DEVDMACONTROL_END_TR_EN_Pos)  /**< (DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */
+#define DEVDMACONTROL_END_B_EN_Pos    3                                              /**< (DEVDMACONTROL) End of Buffer Enable Control Position */
+#define DEVDMACONTROL_END_B_EN        (_U_(0x1) << DEVDMACONTROL_END_B_EN_Pos)  /**< (DEVDMACONTROL) End of Buffer Enable Control Mask */
+#define DEVDMACONTROL_END_TR_IT_Pos   4                                              /**< (DEVDMACONTROL) End of Transfer Interrupt Enable Position */
+#define DEVDMACONTROL_END_TR_IT       (_U_(0x1) << DEVDMACONTROL_END_TR_IT_Pos)  /**< (DEVDMACONTROL) End of Transfer Interrupt Enable Mask */
+#define DEVDMACONTROL_END_BUFFIT_Pos  5                                              /**< (DEVDMACONTROL) End of Buffer Interrupt Enable Position */
+#define DEVDMACONTROL_END_BUFFIT      (_U_(0x1) << DEVDMACONTROL_END_BUFFIT_Pos)  /**< (DEVDMACONTROL) End of Buffer Interrupt Enable Mask */
+#define DEVDMACONTROL_DESC_LD_IT_Pos  6                                              /**< (DEVDMACONTROL) Descriptor Loaded Interrupt Enable Position */
+#define DEVDMACONTROL_DESC_LD_IT      (_U_(0x1) << DEVDMACONTROL_DESC_LD_IT_Pos)  /**< (DEVDMACONTROL) Descriptor Loaded Interrupt Enable Mask */
+#define DEVDMACONTROL_BURST_LCK_Pos   7                                              /**< (DEVDMACONTROL) Burst Lock Enable Position */
+#define DEVDMACONTROL_BURST_LCK       (_U_(0x1) << DEVDMACONTROL_BURST_LCK_Pos)  /**< (DEVDMACONTROL) Burst Lock Enable Mask */
+#define DEVDMACONTROL_BUFF_LENGTH_Pos 16                                             /**< (DEVDMACONTROL) Buffer Byte Length (Write-only) Position */
+#define DEVDMACONTROL_BUFF_LENGTH     (_U_(0xFFFF) << DEVDMACONTROL_BUFF_LENGTH_Pos)  /**< (DEVDMACONTROL) Buffer Byte Length (Write-only) Mask */
+#define DEVDMACONTROL_Msk             _U_(0xFFFF00FF)                                /**< (DEVDMACONTROL) Register Mask  */
+
+
+/* -------- DEVDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Device DMA Channel Status Register -------- */
+
+#define DEVDMASTATUS_OFFSET           (0x0C)                                        /**<  (DEVDMASTATUS) Device DMA Channel Status Register  Offset */
+
+#define DEVDMASTATUS_CHANN_ENB_Pos    0                                              /**< (DEVDMASTATUS) Channel Enable Status Position */
+#define DEVDMASTATUS_CHANN_ENB        (_U_(0x1) << DEVDMASTATUS_CHANN_ENB_Pos)  /**< (DEVDMASTATUS) Channel Enable Status Mask */
+#define DEVDMASTATUS_CHANN_ACT_Pos    1                                              /**< (DEVDMASTATUS) Channel Active Status Position */
+#define DEVDMASTATUS_CHANN_ACT        (_U_(0x1) << DEVDMASTATUS_CHANN_ACT_Pos)  /**< (DEVDMASTATUS) Channel Active Status Mask */
+#define DEVDMASTATUS_END_TR_ST_Pos    4                                              /**< (DEVDMASTATUS) End of Channel Transfer Status Position */
+#define DEVDMASTATUS_END_TR_ST        (_U_(0x1) << DEVDMASTATUS_END_TR_ST_Pos)  /**< (DEVDMASTATUS) End of Channel Transfer Status Mask */
+#define DEVDMASTATUS_END_BF_ST_Pos    5                                              /**< (DEVDMASTATUS) End of Channel Buffer Status Position */
+#define DEVDMASTATUS_END_BF_ST        (_U_(0x1) << DEVDMASTATUS_END_BF_ST_Pos)  /**< (DEVDMASTATUS) End of Channel Buffer Status Mask */
+#define DEVDMASTATUS_DESC_LDST_Pos    6                                              /**< (DEVDMASTATUS) Descriptor Loaded Status Position */
+#define DEVDMASTATUS_DESC_LDST        (_U_(0x1) << DEVDMASTATUS_DESC_LDST_Pos)  /**< (DEVDMASTATUS) Descriptor Loaded Status Mask */
+#define DEVDMASTATUS_BUFF_COUNT_Pos   16                                             /**< (DEVDMASTATUS) Buffer Byte Count Position */
+#define DEVDMASTATUS_BUFF_COUNT       (_U_(0xFFFF) << DEVDMASTATUS_BUFF_COUNT_Pos)  /**< (DEVDMASTATUS) Buffer Byte Count Mask */
+#define DEVDMASTATUS_Msk              _U_(0xFFFF0073)                                /**< (DEVDMASTATUS) Register Mask  */
+
+
+/* -------- HSTDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Host DMA Channel Next Descriptor Address Register -------- */
+
+#define HSTDMANXTDSC_OFFSET           (0x00)                                        /**<  (HSTDMANXTDSC) Host DMA Channel Next Descriptor Address Register  Offset */
+
+#define HSTDMANXTDSC_NXT_DSC_ADD_Pos  0                                              /**< (HSTDMANXTDSC) Next Descriptor Address Position */
+#define HSTDMANXTDSC_NXT_DSC_ADD      (_U_(0xFFFFFFFF) << HSTDMANXTDSC_NXT_DSC_ADD_Pos)  /**< (HSTDMANXTDSC) Next Descriptor Address Mask */
+#define HSTDMANXTDSC_Msk              _U_(0xFFFFFFFF)                                /**< (HSTDMANXTDSC) Register Mask  */
+
+
+/* -------- HSTDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Host DMA Channel Address Register -------- */
+
+#define HSTDMAADDRESS_OFFSET          (0x04)                                        /**<  (HSTDMAADDRESS) Host DMA Channel Address Register  Offset */
+
+#define HSTDMAADDRESS_BUFF_ADD_Pos    0                                              /**< (HSTDMAADDRESS) Buffer Address Position */
+#define HSTDMAADDRESS_BUFF_ADD        (_U_(0xFFFFFFFF) << HSTDMAADDRESS_BUFF_ADD_Pos)  /**< (HSTDMAADDRESS) Buffer Address Mask */
+#define HSTDMAADDRESS_Msk             _U_(0xFFFFFFFF)                                /**< (HSTDMAADDRESS) Register Mask  */
+
+
+/* -------- HSTDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Host DMA Channel Control Register -------- */
+
+#define HSTDMACONTROL_OFFSET          (0x08)                                        /**<  (HSTDMACONTROL) Host DMA Channel Control Register  Offset */
+
+#define HSTDMACONTROL_CHANN_ENB_Pos   0                                              /**< (HSTDMACONTROL) Channel Enable Command Position */
+#define HSTDMACONTROL_CHANN_ENB       (_U_(0x1) << HSTDMACONTROL_CHANN_ENB_Pos)  /**< (HSTDMACONTROL) Channel Enable Command Mask */
+#define HSTDMACONTROL_LDNXT_DSC_Pos   1                                              /**< (HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */
+#define HSTDMACONTROL_LDNXT_DSC       (_U_(0x1) << HSTDMACONTROL_LDNXT_DSC_Pos)  /**< (HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */
+#define HSTDMACONTROL_END_TR_EN_Pos   2                                              /**< (HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */
+#define HSTDMACONTROL_END_TR_EN       (_U_(0x1) << HSTDMACONTROL_END_TR_EN_Pos)  /**< (HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */
+#define HSTDMACONTROL_END_B_EN_Pos    3                                              /**< (HSTDMACONTROL) End of Buffer Enable Control Position */
+#define HSTDMACONTROL_END_B_EN        (_U_(0x1) << HSTDMACONTROL_END_B_EN_Pos)  /**< (HSTDMACONTROL) End of Buffer Enable Control Mask */
+#define HSTDMACONTROL_END_TR_IT_Pos   4                                              /**< (HSTDMACONTROL) End of Transfer Interrupt Enable Position */
+#define HSTDMACONTROL_END_TR_IT       (_U_(0x1) << HSTDMACONTROL_END_TR_IT_Pos)  /**< (HSTDMACONTROL) End of Transfer Interrupt Enable Mask */
+#define HSTDMACONTROL_END_BUFFIT_Pos  5                                              /**< (HSTDMACONTROL) End of Buffer Interrupt Enable Position */
+#define HSTDMACONTROL_END_BUFFIT      (_U_(0x1) << HSTDMACONTROL_END_BUFFIT_Pos)  /**< (HSTDMACONTROL) End of Buffer Interrupt Enable Mask */
+#define HSTDMACONTROL_DESC_LD_IT_Pos  6                                              /**< (HSTDMACONTROL) Descriptor Loaded Interrupt Enable Position */
+#define HSTDMACONTROL_DESC_LD_IT      (_U_(0x1) << HSTDMACONTROL_DESC_LD_IT_Pos)  /**< (HSTDMACONTROL) Descriptor Loaded Interrupt Enable Mask */
+#define HSTDMACONTROL_BURST_LCK_Pos   7                                              /**< (HSTDMACONTROL) Burst Lock Enable Position */
+#define HSTDMACONTROL_BURST_LCK       (_U_(0x1) << HSTDMACONTROL_BURST_LCK_Pos)  /**< (HSTDMACONTROL) Burst Lock Enable Mask */
+#define HSTDMACONTROL_BUFF_LENGTH_Pos 16                                             /**< (HSTDMACONTROL) Buffer Byte Length (Write-only) Position */
+#define HSTDMACONTROL_BUFF_LENGTH     (_U_(0xFFFF) << HSTDMACONTROL_BUFF_LENGTH_Pos)  /**< (HSTDMACONTROL) Buffer Byte Length (Write-only) Mask */
+#define HSTDMACONTROL_Msk             _U_(0xFFFF00FF)                                /**< (HSTDMACONTROL) Register Mask  */
+
+
+/* -------- HSTDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Host DMA Channel Status Register -------- */
+
+#define HSTDMASTATUS_OFFSET           (0x0C)                                        /**<  (HSTDMASTATUS) Host DMA Channel Status Register  Offset */
+
+#define HSTDMASTATUS_CHANN_ENB_Pos    0                                              /**< (HSTDMASTATUS) Channel Enable Status Position */
+#define HSTDMASTATUS_CHANN_ENB        (_U_(0x1) << HSTDMASTATUS_CHANN_ENB_Pos)  /**< (HSTDMASTATUS) Channel Enable Status Mask */
+#define HSTDMASTATUS_CHANN_ACT_Pos    1                                              /**< (HSTDMASTATUS) Channel Active Status Position */
+#define HSTDMASTATUS_CHANN_ACT        (_U_(0x1) << HSTDMASTATUS_CHANN_ACT_Pos)  /**< (HSTDMASTATUS) Channel Active Status Mask */
+#define HSTDMASTATUS_END_TR_ST_Pos    4                                              /**< (HSTDMASTATUS) End of Channel Transfer Status Position */
+#define HSTDMASTATUS_END_TR_ST        (_U_(0x1) << HSTDMASTATUS_END_TR_ST_Pos)  /**< (HSTDMASTATUS) End of Channel Transfer Status Mask */
+#define HSTDMASTATUS_END_BF_ST_Pos    5                                              /**< (HSTDMASTATUS) End of Channel Buffer Status Position */
+#define HSTDMASTATUS_END_BF_ST        (_U_(0x1) << HSTDMASTATUS_END_BF_ST_Pos)  /**< (HSTDMASTATUS) End of Channel Buffer Status Mask */
+#define HSTDMASTATUS_DESC_LDST_Pos    6                                              /**< (HSTDMASTATUS) Descriptor Loaded Status Position */
+#define HSTDMASTATUS_DESC_LDST        (_U_(0x1) << HSTDMASTATUS_DESC_LDST_Pos)  /**< (HSTDMASTATUS) Descriptor Loaded Status Mask */
+#define HSTDMASTATUS_BUFF_COUNT_Pos   16                                             /**< (HSTDMASTATUS) Buffer Byte Count Position */
+#define HSTDMASTATUS_BUFF_COUNT       (_U_(0xFFFF) << HSTDMASTATUS_BUFF_COUNT_Pos)  /**< (HSTDMASTATUS) Buffer Byte Count Mask */
+#define HSTDMASTATUS_Msk              _U_(0xFFFF0073)                                /**< (HSTDMASTATUS) Register Mask  */
+
+
+/* -------- DEVCTRL : (USBHS Offset: 0x00) (R/W 32) Device General Control Register -------- */
+
+#define DEVCTRL_OFFSET                (0x00)                                        /**<  (DEVCTRL) Device General Control Register  Offset */
+
+#define DEVCTRL_UADD_Pos              0                                              /**< (DEVCTRL) USB Address Position */
+#define DEVCTRL_UADD                  (_U_(0x7F) << DEVCTRL_UADD_Pos)          /**< (DEVCTRL) USB Address Mask */
+#define DEVCTRL_ADDEN_Pos             7                                              /**< (DEVCTRL) Address Enable Position */
+#define DEVCTRL_ADDEN                 (_U_(0x1) << DEVCTRL_ADDEN_Pos)          /**< (DEVCTRL) Address Enable Mask */
+#define DEVCTRL_DETACH_Pos            8                                              /**< (DEVCTRL) Detach Position */
+#define DEVCTRL_DETACH                (_U_(0x1) << DEVCTRL_DETACH_Pos)         /**< (DEVCTRL) Detach Mask */
+#define DEVCTRL_RMWKUP_Pos            9                                              /**< (DEVCTRL) Remote Wake-Up Position */
+#define DEVCTRL_RMWKUP                (_U_(0x1) << DEVCTRL_RMWKUP_Pos)         /**< (DEVCTRL) Remote Wake-Up Mask */
+#define DEVCTRL_SPDCONF_Pos           10                                             /**< (DEVCTRL) Mode Configuration Position */
+#define DEVCTRL_SPDCONF               (_U_(0x3) << DEVCTRL_SPDCONF_Pos)        /**< (DEVCTRL) Mode Configuration Mask */
+#define   DEVCTRL_SPDCONF_NORMAL_Val  _U_(0x0)                                       /**< (DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable.  */
+#define   DEVCTRL_SPDCONF_LOW_POWER_Val _U_(0x1)                                       /**< (DEVCTRL) For a better consumption, if high speed is not needed.  */
+#define   DEVCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2)                                       /**< (DEVCTRL) Forced high speed.  */
+#define   DEVCTRL_SPDCONF_FORCED_FS_Val _U_(0x3)                                       /**< (DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability.  */
+#define DEVCTRL_SPDCONF_NORMAL        (DEVCTRL_SPDCONF_NORMAL_Val << DEVCTRL_SPDCONF_Pos)  /**< (DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. Position  */
+#define DEVCTRL_SPDCONF_LOW_POWER     (DEVCTRL_SPDCONF_LOW_POWER_Val << DEVCTRL_SPDCONF_Pos)  /**< (DEVCTRL) For a better consumption, if high speed is not needed. Position  */
+#define DEVCTRL_SPDCONF_HIGH_SPEED    (DEVCTRL_SPDCONF_HIGH_SPEED_Val << DEVCTRL_SPDCONF_Pos)  /**< (DEVCTRL) Forced high speed. Position  */
+#define DEVCTRL_SPDCONF_FORCED_FS     (DEVCTRL_SPDCONF_FORCED_FS_Val << DEVCTRL_SPDCONF_Pos)  /**< (DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. Position  */
+#define DEVCTRL_LS_Pos                12                                             /**< (DEVCTRL) Low-Speed Mode Force Position */
+#define DEVCTRL_LS                    (_U_(0x1) << DEVCTRL_LS_Pos)             /**< (DEVCTRL) Low-Speed Mode Force Mask */
+#define DEVCTRL_TSTJ_Pos              13                                             /**< (DEVCTRL) Test mode J Position */
+#define DEVCTRL_TSTJ                  (_U_(0x1) << DEVCTRL_TSTJ_Pos)           /**< (DEVCTRL) Test mode J Mask */
+#define DEVCTRL_TSTK_Pos              14                                             /**< (DEVCTRL) Test mode K Position */
+#define DEVCTRL_TSTK                  (_U_(0x1) << DEVCTRL_TSTK_Pos)           /**< (DEVCTRL) Test mode K Mask */
+#define DEVCTRL_TSTPCKT_Pos           15                                             /**< (DEVCTRL) Test packet mode Position */
+#define DEVCTRL_TSTPCKT               (_U_(0x1) << DEVCTRL_TSTPCKT_Pos)        /**< (DEVCTRL) Test packet mode Mask */
+#define DEVCTRL_OPMODE2_Pos           16                                             /**< (DEVCTRL) Specific Operational mode Position */
+#define DEVCTRL_OPMODE2               (_U_(0x1) << DEVCTRL_OPMODE2_Pos)        /**< (DEVCTRL) Specific Operational mode Mask */
+#define DEVCTRL_Msk                   _U_(0x1FFFF)                                   /**< (DEVCTRL) Register Mask  */
+
+#define DEVCTRL_OPMODE_Pos            16                                             /**< (DEVCTRL Position) Specific Operational mode */
+#define DEVCTRL_OPMODE                (_U_(0x1) << DEVCTRL_OPMODE_Pos)         /**< (DEVCTRL Mask) OPMODE */
+
+/* -------- DEVISR : (USBHS Offset: 0x04) (R/ 32) Device Global Interrupt Status Register -------- */
+
+#define DEVISR_OFFSET                 (0x04)                                        /**<  (DEVISR) Device Global Interrupt Status Register  Offset */
+
+#define DEVISR_SUSP_Pos               0                                              /**< (DEVISR) Suspend Interrupt Position */
+#define DEVISR_SUSP                   (_U_(0x1) << DEVISR_SUSP_Pos)            /**< (DEVISR) Suspend Interrupt Mask */
+#define DEVISR_MSOF_Pos               1                                              /**< (DEVISR) Micro Start of Frame Interrupt Position */
+#define DEVISR_MSOF                   (_U_(0x1) << DEVISR_MSOF_Pos)            /**< (DEVISR) Micro Start of Frame Interrupt Mask */
+#define DEVISR_SOF_Pos                2                                              /**< (DEVISR) Start of Frame Interrupt Position */
+#define DEVISR_SOF                    (_U_(0x1) << DEVISR_SOF_Pos)             /**< (DEVISR) Start of Frame Interrupt Mask */
+#define DEVISR_EORST_Pos              3                                              /**< (DEVISR) End of Reset Interrupt Position */
+#define DEVISR_EORST                  (_U_(0x1) << DEVISR_EORST_Pos)           /**< (DEVISR) End of Reset Interrupt Mask */
+#define DEVISR_WAKEUP_Pos             4                                              /**< (DEVISR) Wake-Up Interrupt Position */
+#define DEVISR_WAKEUP                 (_U_(0x1) << DEVISR_WAKEUP_Pos)          /**< (DEVISR) Wake-Up Interrupt Mask */
+#define DEVISR_EORSM_Pos              5                                              /**< (DEVISR) End of Resume Interrupt Position */
+#define DEVISR_EORSM                  (_U_(0x1) << DEVISR_EORSM_Pos)           /**< (DEVISR) End of Resume Interrupt Mask */
+#define DEVISR_UPRSM_Pos              6                                              /**< (DEVISR) Upstream Resume Interrupt Position */
+#define DEVISR_UPRSM                  (_U_(0x1) << DEVISR_UPRSM_Pos)           /**< (DEVISR) Upstream Resume Interrupt Mask */
+#define DEVISR_PEP_0_Pos              12                                             /**< (DEVISR) Endpoint 0 Interrupt Position */
+#define DEVISR_PEP_0                  (_U_(0x1) << DEVISR_PEP_0_Pos)           /**< (DEVISR) Endpoint 0 Interrupt Mask */
+#define DEVISR_PEP_1_Pos              13                                             /**< (DEVISR) Endpoint 1 Interrupt Position */
+#define DEVISR_PEP_1                  (_U_(0x1) << DEVISR_PEP_1_Pos)           /**< (DEVISR) Endpoint 1 Interrupt Mask */
+#define DEVISR_PEP_2_Pos              14                                             /**< (DEVISR) Endpoint 2 Interrupt Position */
+#define DEVISR_PEP_2                  (_U_(0x1) << DEVISR_PEP_2_Pos)           /**< (DEVISR) Endpoint 2 Interrupt Mask */
+#define DEVISR_PEP_3_Pos              15                                             /**< (DEVISR) Endpoint 3 Interrupt Position */
+#define DEVISR_PEP_3                  (_U_(0x1) << DEVISR_PEP_3_Pos)           /**< (DEVISR) Endpoint 3 Interrupt Mask */
+#define DEVISR_PEP_4_Pos              16                                             /**< (DEVISR) Endpoint 4 Interrupt Position */
+#define DEVISR_PEP_4                  (_U_(0x1) << DEVISR_PEP_4_Pos)           /**< (DEVISR) Endpoint 4 Interrupt Mask */
+#define DEVISR_PEP_5_Pos              17                                             /**< (DEVISR) Endpoint 5 Interrupt Position */
+#define DEVISR_PEP_5                  (_U_(0x1) << DEVISR_PEP_5_Pos)           /**< (DEVISR) Endpoint 5 Interrupt Mask */
+#define DEVISR_PEP_6_Pos              18                                             /**< (DEVISR) Endpoint 6 Interrupt Position */
+#define DEVISR_PEP_6                  (_U_(0x1) << DEVISR_PEP_6_Pos)           /**< (DEVISR) Endpoint 6 Interrupt Mask */
+#define DEVISR_PEP_7_Pos              19                                             /**< (DEVISR) Endpoint 7 Interrupt Position */
+#define DEVISR_PEP_7                  (_U_(0x1) << DEVISR_PEP_7_Pos)           /**< (DEVISR) Endpoint 7 Interrupt Mask */
+#define DEVISR_PEP_8_Pos              20                                             /**< (DEVISR) Endpoint 8 Interrupt Position */
+#define DEVISR_PEP_8                  (_U_(0x1) << DEVISR_PEP_8_Pos)           /**< (DEVISR) Endpoint 8 Interrupt Mask */
+#define DEVISR_PEP_9_Pos              21                                             /**< (DEVISR) Endpoint 9 Interrupt Position */
+#define DEVISR_PEP_9                  (_U_(0x1) << DEVISR_PEP_9_Pos)           /**< (DEVISR) Endpoint 9 Interrupt Mask */
+#define DEVISR_DMA_1_Pos              25                                             /**< (DEVISR) DMA Channel 1 Interrupt Position */
+#define DEVISR_DMA_1                  (_U_(0x1) << DEVISR_DMA_1_Pos)           /**< (DEVISR) DMA Channel 1 Interrupt Mask */
+#define DEVISR_DMA_2_Pos              26                                             /**< (DEVISR) DMA Channel 2 Interrupt Position */
+#define DEVISR_DMA_2                  (_U_(0x1) << DEVISR_DMA_2_Pos)           /**< (DEVISR) DMA Channel 2 Interrupt Mask */
+#define DEVISR_DMA_3_Pos              27                                             /**< (DEVISR) DMA Channel 3 Interrupt Position */
+#define DEVISR_DMA_3                  (_U_(0x1) << DEVISR_DMA_3_Pos)           /**< (DEVISR) DMA Channel 3 Interrupt Mask */
+#define DEVISR_DMA_4_Pos              28                                             /**< (DEVISR) DMA Channel 4 Interrupt Position */
+#define DEVISR_DMA_4                  (_U_(0x1) << DEVISR_DMA_4_Pos)           /**< (DEVISR) DMA Channel 4 Interrupt Mask */
+#define DEVISR_DMA_5_Pos              29                                             /**< (DEVISR) DMA Channel 5 Interrupt Position */
+#define DEVISR_DMA_5                  (_U_(0x1) << DEVISR_DMA_5_Pos)           /**< (DEVISR) DMA Channel 5 Interrupt Mask */
+#define DEVISR_DMA_6_Pos              30                                             /**< (DEVISR) DMA Channel 6 Interrupt Position */
+#define DEVISR_DMA_6                  (_U_(0x1) << DEVISR_DMA_6_Pos)           /**< (DEVISR) DMA Channel 6 Interrupt Mask */
+#define DEVISR_DMA_7_Pos              31                                             /**< (DEVISR) DMA Channel 7 Interrupt Position */
+#define DEVISR_DMA_7                  (_U_(0x1) << DEVISR_DMA_7_Pos)           /**< (DEVISR) DMA Channel 7 Interrupt Mask */
+#define DEVISR_Msk                    _U_(0xFE3FF07F)                                /**< (DEVISR) Register Mask  */
+
+#define DEVISR_PEP__Pos               12                                             /**< (DEVISR Position) Endpoint x Interrupt */
+#define DEVISR_PEP_                   (_U_(0x3FF) << DEVISR_PEP__Pos)          /**< (DEVISR Mask) PEP_ */
+#define DEVISR_DMA__Pos               25                                             /**< (DEVISR Position) DMA Channel 7 Interrupt */
+#define DEVISR_DMA_                   (_U_(0x7F) << DEVISR_DMA__Pos)           /**< (DEVISR Mask) DMA_ */
+
+/* -------- DEVICR : (USBHS Offset: 0x08) (/W 32) Device Global Interrupt Clear Register -------- */
+
+#define DEVICR_OFFSET                 (0x08)                                        /**<  (DEVICR) Device Global Interrupt Clear Register  Offset */
+
+#define DEVICR_SUSPC_Pos              0                                              /**< (DEVICR) Suspend Interrupt Clear Position */
+#define DEVICR_SUSPC                  (_U_(0x1) << DEVICR_SUSPC_Pos)           /**< (DEVICR) Suspend Interrupt Clear Mask */
+#define DEVICR_MSOFC_Pos              1                                              /**< (DEVICR) Micro Start of Frame Interrupt Clear Position */
+#define DEVICR_MSOFC                  (_U_(0x1) << DEVICR_MSOFC_Pos)           /**< (DEVICR) Micro Start of Frame Interrupt Clear Mask */
+#define DEVICR_SOFC_Pos               2                                              /**< (DEVICR) Start of Frame Interrupt Clear Position */
+#define DEVICR_SOFC                   (_U_(0x1) << DEVICR_SOFC_Pos)            /**< (DEVICR) Start of Frame Interrupt Clear Mask */
+#define DEVICR_EORSTC_Pos             3                                              /**< (DEVICR) End of Reset Interrupt Clear Position */
+#define DEVICR_EORSTC                 (_U_(0x1) << DEVICR_EORSTC_Pos)          /**< (DEVICR) End of Reset Interrupt Clear Mask */
+#define DEVICR_WAKEUPC_Pos            4                                              /**< (DEVICR) Wake-Up Interrupt Clear Position */
+#define DEVICR_WAKEUPC                (_U_(0x1) << DEVICR_WAKEUPC_Pos)         /**< (DEVICR) Wake-Up Interrupt Clear Mask */
+#define DEVICR_EORSMC_Pos             5                                              /**< (DEVICR) End of Resume Interrupt Clear Position */
+#define DEVICR_EORSMC                 (_U_(0x1) << DEVICR_EORSMC_Pos)          /**< (DEVICR) End of Resume Interrupt Clear Mask */
+#define DEVICR_UPRSMC_Pos             6                                              /**< (DEVICR) Upstream Resume Interrupt Clear Position */
+#define DEVICR_UPRSMC                 (_U_(0x1) << DEVICR_UPRSMC_Pos)          /**< (DEVICR) Upstream Resume Interrupt Clear Mask */
+#define DEVICR_Msk                    _U_(0x7F)                                      /**< (DEVICR) Register Mask  */
+
+
+/* -------- DEVIFR : (USBHS Offset: 0x0c) (/W 32) Device Global Interrupt Set Register -------- */
+
+#define DEVIFR_OFFSET                 (0x0C)                                        /**<  (DEVIFR) Device Global Interrupt Set Register  Offset */
+
+#define DEVIFR_SUSPS_Pos              0                                              /**< (DEVIFR) Suspend Interrupt Set Position */
+#define DEVIFR_SUSPS                  (_U_(0x1) << DEVIFR_SUSPS_Pos)           /**< (DEVIFR) Suspend Interrupt Set Mask */
+#define DEVIFR_MSOFS_Pos              1                                              /**< (DEVIFR) Micro Start of Frame Interrupt Set Position */
+#define DEVIFR_MSOFS                  (_U_(0x1) << DEVIFR_MSOFS_Pos)           /**< (DEVIFR) Micro Start of Frame Interrupt Set Mask */
+#define DEVIFR_SOFS_Pos               2                                              /**< (DEVIFR) Start of Frame Interrupt Set Position */
+#define DEVIFR_SOFS                   (_U_(0x1) << DEVIFR_SOFS_Pos)            /**< (DEVIFR) Start of Frame Interrupt Set Mask */
+#define DEVIFR_EORSTS_Pos             3                                              /**< (DEVIFR) End of Reset Interrupt Set Position */
+#define DEVIFR_EORSTS                 (_U_(0x1) << DEVIFR_EORSTS_Pos)          /**< (DEVIFR) End of Reset Interrupt Set Mask */
+#define DEVIFR_WAKEUPS_Pos            4                                              /**< (DEVIFR) Wake-Up Interrupt Set Position */
+#define DEVIFR_WAKEUPS                (_U_(0x1) << DEVIFR_WAKEUPS_Pos)         /**< (DEVIFR) Wake-Up Interrupt Set Mask */
+#define DEVIFR_EORSMS_Pos             5                                              /**< (DEVIFR) End of Resume Interrupt Set Position */
+#define DEVIFR_EORSMS                 (_U_(0x1) << DEVIFR_EORSMS_Pos)          /**< (DEVIFR) End of Resume Interrupt Set Mask */
+#define DEVIFR_UPRSMS_Pos             6                                              /**< (DEVIFR) Upstream Resume Interrupt Set Position */
+#define DEVIFR_UPRSMS                 (_U_(0x1) << DEVIFR_UPRSMS_Pos)          /**< (DEVIFR) Upstream Resume Interrupt Set Mask */
+#define DEVIFR_DMA_1_Pos              25                                             /**< (DEVIFR) DMA Channel 1 Interrupt Set Position */
+#define DEVIFR_DMA_1                  (_U_(0x1) << DEVIFR_DMA_1_Pos)           /**< (DEVIFR) DMA Channel 1 Interrupt Set Mask */
+#define DEVIFR_DMA_2_Pos              26                                             /**< (DEVIFR) DMA Channel 2 Interrupt Set Position */
+#define DEVIFR_DMA_2                  (_U_(0x1) << DEVIFR_DMA_2_Pos)           /**< (DEVIFR) DMA Channel 2 Interrupt Set Mask */
+#define DEVIFR_DMA_3_Pos              27                                             /**< (DEVIFR) DMA Channel 3 Interrupt Set Position */
+#define DEVIFR_DMA_3                  (_U_(0x1) << DEVIFR_DMA_3_Pos)           /**< (DEVIFR) DMA Channel 3 Interrupt Set Mask */
+#define DEVIFR_DMA_4_Pos              28                                             /**< (DEVIFR) DMA Channel 4 Interrupt Set Position */
+#define DEVIFR_DMA_4                  (_U_(0x1) << DEVIFR_DMA_4_Pos)           /**< (DEVIFR) DMA Channel 4 Interrupt Set Mask */
+#define DEVIFR_DMA_5_Pos              29                                             /**< (DEVIFR) DMA Channel 5 Interrupt Set Position */
+#define DEVIFR_DMA_5                  (_U_(0x1) << DEVIFR_DMA_5_Pos)           /**< (DEVIFR) DMA Channel 5 Interrupt Set Mask */
+#define DEVIFR_DMA_6_Pos              30                                             /**< (DEVIFR) DMA Channel 6 Interrupt Set Position */
+#define DEVIFR_DMA_6                  (_U_(0x1) << DEVIFR_DMA_6_Pos)           /**< (DEVIFR) DMA Channel 6 Interrupt Set Mask */
+#define DEVIFR_DMA_7_Pos              31                                             /**< (DEVIFR) DMA Channel 7 Interrupt Set Position */
+#define DEVIFR_DMA_7                  (_U_(0x1) << DEVIFR_DMA_7_Pos)           /**< (DEVIFR) DMA Channel 7 Interrupt Set Mask */
+#define DEVIFR_Msk                    _U_(0xFE00007F)                                /**< (DEVIFR) Register Mask  */
+
+#define DEVIFR_DMA__Pos               25                                             /**< (DEVIFR Position) DMA Channel 7 Interrupt Set */
+#define DEVIFR_DMA_                   (_U_(0x7F) << DEVIFR_DMA__Pos)           /**< (DEVIFR Mask) DMA_ */
+
+/* -------- DEVIMR : (USBHS Offset: 0x10) (R/ 32) Device Global Interrupt Mask Register -------- */
+
+#define DEVIMR_OFFSET                 (0x10)                                        /**<  (DEVIMR) Device Global Interrupt Mask Register  Offset */
+
+#define DEVIMR_SUSPE_Pos              0                                              /**< (DEVIMR) Suspend Interrupt Mask Position */
+#define DEVIMR_SUSPE                  (_U_(0x1) << DEVIMR_SUSPE_Pos)           /**< (DEVIMR) Suspend Interrupt Mask Mask */
+#define DEVIMR_MSOFE_Pos              1                                              /**< (DEVIMR) Micro Start of Frame Interrupt Mask Position */
+#define DEVIMR_MSOFE                  (_U_(0x1) << DEVIMR_MSOFE_Pos)           /**< (DEVIMR) Micro Start of Frame Interrupt Mask Mask */
+#define DEVIMR_SOFE_Pos               2                                              /**< (DEVIMR) Start of Frame Interrupt Mask Position */
+#define DEVIMR_SOFE                   (_U_(0x1) << DEVIMR_SOFE_Pos)            /**< (DEVIMR) Start of Frame Interrupt Mask Mask */
+#define DEVIMR_EORSTE_Pos             3                                              /**< (DEVIMR) End of Reset Interrupt Mask Position */
+#define DEVIMR_EORSTE                 (_U_(0x1) << DEVIMR_EORSTE_Pos)          /**< (DEVIMR) End of Reset Interrupt Mask Mask */
+#define DEVIMR_WAKEUPE_Pos            4                                              /**< (DEVIMR) Wake-Up Interrupt Mask Position */
+#define DEVIMR_WAKEUPE                (_U_(0x1) << DEVIMR_WAKEUPE_Pos)         /**< (DEVIMR) Wake-Up Interrupt Mask Mask */
+#define DEVIMR_EORSME_Pos             5                                              /**< (DEVIMR) End of Resume Interrupt Mask Position */
+#define DEVIMR_EORSME                 (_U_(0x1) << DEVIMR_EORSME_Pos)          /**< (DEVIMR) End of Resume Interrupt Mask Mask */
+#define DEVIMR_UPRSME_Pos             6                                              /**< (DEVIMR) Upstream Resume Interrupt Mask Position */
+#define DEVIMR_UPRSME                 (_U_(0x1) << DEVIMR_UPRSME_Pos)          /**< (DEVIMR) Upstream Resume Interrupt Mask Mask */
+#define DEVIMR_PEP_0_Pos              12                                             /**< (DEVIMR) Endpoint 0 Interrupt Mask Position */
+#define DEVIMR_PEP_0                  (_U_(0x1) << DEVIMR_PEP_0_Pos)           /**< (DEVIMR) Endpoint 0 Interrupt Mask Mask */
+#define DEVIMR_PEP_1_Pos              13                                             /**< (DEVIMR) Endpoint 1 Interrupt Mask Position */
+#define DEVIMR_PEP_1                  (_U_(0x1) << DEVIMR_PEP_1_Pos)           /**< (DEVIMR) Endpoint 1 Interrupt Mask Mask */
+#define DEVIMR_PEP_2_Pos              14                                             /**< (DEVIMR) Endpoint 2 Interrupt Mask Position */
+#define DEVIMR_PEP_2                  (_U_(0x1) << DEVIMR_PEP_2_Pos)           /**< (DEVIMR) Endpoint 2 Interrupt Mask Mask */
+#define DEVIMR_PEP_3_Pos              15                                             /**< (DEVIMR) Endpoint 3 Interrupt Mask Position */
+#define DEVIMR_PEP_3                  (_U_(0x1) << DEVIMR_PEP_3_Pos)           /**< (DEVIMR) Endpoint 3 Interrupt Mask Mask */
+#define DEVIMR_PEP_4_Pos              16                                             /**< (DEVIMR) Endpoint 4 Interrupt Mask Position */
+#define DEVIMR_PEP_4                  (_U_(0x1) << DEVIMR_PEP_4_Pos)           /**< (DEVIMR) Endpoint 4 Interrupt Mask Mask */
+#define DEVIMR_PEP_5_Pos              17                                             /**< (DEVIMR) Endpoint 5 Interrupt Mask Position */
+#define DEVIMR_PEP_5                  (_U_(0x1) << DEVIMR_PEP_5_Pos)           /**< (DEVIMR) Endpoint 5 Interrupt Mask Mask */
+#define DEVIMR_PEP_6_Pos              18                                             /**< (DEVIMR) Endpoint 6 Interrupt Mask Position */
+#define DEVIMR_PEP_6                  (_U_(0x1) << DEVIMR_PEP_6_Pos)           /**< (DEVIMR) Endpoint 6 Interrupt Mask Mask */
+#define DEVIMR_PEP_7_Pos              19                                             /**< (DEVIMR) Endpoint 7 Interrupt Mask Position */
+#define DEVIMR_PEP_7                  (_U_(0x1) << DEVIMR_PEP_7_Pos)           /**< (DEVIMR) Endpoint 7 Interrupt Mask Mask */
+#define DEVIMR_PEP_8_Pos              20                                             /**< (DEVIMR) Endpoint 8 Interrupt Mask Position */
+#define DEVIMR_PEP_8                  (_U_(0x1) << DEVIMR_PEP_8_Pos)           /**< (DEVIMR) Endpoint 8 Interrupt Mask Mask */
+#define DEVIMR_PEP_9_Pos              21                                             /**< (DEVIMR) Endpoint 9 Interrupt Mask Position */
+#define DEVIMR_PEP_9                  (_U_(0x1) << DEVIMR_PEP_9_Pos)           /**< (DEVIMR) Endpoint 9 Interrupt Mask Mask */
+#define DEVIMR_DMA_1_Pos              25                                             /**< (DEVIMR) DMA Channel 1 Interrupt Mask Position */
+#define DEVIMR_DMA_1                  (_U_(0x1) << DEVIMR_DMA_1_Pos)           /**< (DEVIMR) DMA Channel 1 Interrupt Mask Mask */
+#define DEVIMR_DMA_2_Pos              26                                             /**< (DEVIMR) DMA Channel 2 Interrupt Mask Position */
+#define DEVIMR_DMA_2                  (_U_(0x1) << DEVIMR_DMA_2_Pos)           /**< (DEVIMR) DMA Channel 2 Interrupt Mask Mask */
+#define DEVIMR_DMA_3_Pos              27                                             /**< (DEVIMR) DMA Channel 3 Interrupt Mask Position */
+#define DEVIMR_DMA_3                  (_U_(0x1) << DEVIMR_DMA_3_Pos)           /**< (DEVIMR) DMA Channel 3 Interrupt Mask Mask */
+#define DEVIMR_DMA_4_Pos              28                                             /**< (DEVIMR) DMA Channel 4 Interrupt Mask Position */
+#define DEVIMR_DMA_4                  (_U_(0x1) << DEVIMR_DMA_4_Pos)           /**< (DEVIMR) DMA Channel 4 Interrupt Mask Mask */
+#define DEVIMR_DMA_5_Pos              29                                             /**< (DEVIMR) DMA Channel 5 Interrupt Mask Position */
+#define DEVIMR_DMA_5                  (_U_(0x1) << DEVIMR_DMA_5_Pos)           /**< (DEVIMR) DMA Channel 5 Interrupt Mask Mask */
+#define DEVIMR_DMA_6_Pos              30                                             /**< (DEVIMR) DMA Channel 6 Interrupt Mask Position */
+#define DEVIMR_DMA_6                  (_U_(0x1) << DEVIMR_DMA_6_Pos)           /**< (DEVIMR) DMA Channel 6 Interrupt Mask Mask */
+#define DEVIMR_DMA_7_Pos              31                                             /**< (DEVIMR) DMA Channel 7 Interrupt Mask Position */
+#define DEVIMR_DMA_7                  (_U_(0x1) << DEVIMR_DMA_7_Pos)           /**< (DEVIMR) DMA Channel 7 Interrupt Mask Mask */
+#define DEVIMR_Msk                    _U_(0xFE3FF07F)                                /**< (DEVIMR) Register Mask  */
+
+#define DEVIMR_PEP__Pos               12                                             /**< (DEVIMR Position) Endpoint x Interrupt Mask */
+#define DEVIMR_PEP_                   (_U_(0x3FF) << DEVIMR_PEP__Pos)          /**< (DEVIMR Mask) PEP_ */
+#define DEVIMR_DMA__Pos               25                                             /**< (DEVIMR Position) DMA Channel 7 Interrupt Mask */
+#define DEVIMR_DMA_                   (_U_(0x7F) << DEVIMR_DMA__Pos)           /**< (DEVIMR Mask) DMA_ */
+
+/* -------- DEVIDR : (USBHS Offset: 0x14) (/W 32) Device Global Interrupt Disable Register -------- */
+
+#define DEVIDR_OFFSET                 (0x14)                                        /**<  (DEVIDR) Device Global Interrupt Disable Register  Offset */
+
+#define DEVIDR_SUSPEC_Pos             0                                              /**< (DEVIDR) Suspend Interrupt Disable Position */
+#define DEVIDR_SUSPEC                 (_U_(0x1) << DEVIDR_SUSPEC_Pos)          /**< (DEVIDR) Suspend Interrupt Disable Mask */
+#define DEVIDR_MSOFEC_Pos             1                                              /**< (DEVIDR) Micro Start of Frame Interrupt Disable Position */
+#define DEVIDR_MSOFEC                 (_U_(0x1) << DEVIDR_MSOFEC_Pos)          /**< (DEVIDR) Micro Start of Frame Interrupt Disable Mask */
+#define DEVIDR_SOFEC_Pos              2                                              /**< (DEVIDR) Start of Frame Interrupt Disable Position */
+#define DEVIDR_SOFEC                  (_U_(0x1) << DEVIDR_SOFEC_Pos)           /**< (DEVIDR) Start of Frame Interrupt Disable Mask */
+#define DEVIDR_EORSTEC_Pos            3                                              /**< (DEVIDR) End of Reset Interrupt Disable Position */
+#define DEVIDR_EORSTEC                (_U_(0x1) << DEVIDR_EORSTEC_Pos)         /**< (DEVIDR) End of Reset Interrupt Disable Mask */
+#define DEVIDR_WAKEUPEC_Pos           4                                              /**< (DEVIDR) Wake-Up Interrupt Disable Position */
+#define DEVIDR_WAKEUPEC               (_U_(0x1) << DEVIDR_WAKEUPEC_Pos)        /**< (DEVIDR) Wake-Up Interrupt Disable Mask */
+#define DEVIDR_EORSMEC_Pos            5                                              /**< (DEVIDR) End of Resume Interrupt Disable Position */
+#define DEVIDR_EORSMEC                (_U_(0x1) << DEVIDR_EORSMEC_Pos)         /**< (DEVIDR) End of Resume Interrupt Disable Mask */
+#define DEVIDR_UPRSMEC_Pos            6                                              /**< (DEVIDR) Upstream Resume Interrupt Disable Position */
+#define DEVIDR_UPRSMEC                (_U_(0x1) << DEVIDR_UPRSMEC_Pos)         /**< (DEVIDR) Upstream Resume Interrupt Disable Mask */
+#define DEVIDR_PEP_0_Pos              12                                             /**< (DEVIDR) Endpoint 0 Interrupt Disable Position */
+#define DEVIDR_PEP_0                  (_U_(0x1) << DEVIDR_PEP_0_Pos)           /**< (DEVIDR) Endpoint 0 Interrupt Disable Mask */
+#define DEVIDR_PEP_1_Pos              13                                             /**< (DEVIDR) Endpoint 1 Interrupt Disable Position */
+#define DEVIDR_PEP_1                  (_U_(0x1) << DEVIDR_PEP_1_Pos)           /**< (DEVIDR) Endpoint 1 Interrupt Disable Mask */
+#define DEVIDR_PEP_2_Pos              14                                             /**< (DEVIDR) Endpoint 2 Interrupt Disable Position */
+#define DEVIDR_PEP_2                  (_U_(0x1) << DEVIDR_PEP_2_Pos)           /**< (DEVIDR) Endpoint 2 Interrupt Disable Mask */
+#define DEVIDR_PEP_3_Pos              15                                             /**< (DEVIDR) Endpoint 3 Interrupt Disable Position */
+#define DEVIDR_PEP_3                  (_U_(0x1) << DEVIDR_PEP_3_Pos)           /**< (DEVIDR) Endpoint 3 Interrupt Disable Mask */
+#define DEVIDR_PEP_4_Pos              16                                             /**< (DEVIDR) Endpoint 4 Interrupt Disable Position */
+#define DEVIDR_PEP_4                  (_U_(0x1) << DEVIDR_PEP_4_Pos)           /**< (DEVIDR) Endpoint 4 Interrupt Disable Mask */
+#define DEVIDR_PEP_5_Pos              17                                             /**< (DEVIDR) Endpoint 5 Interrupt Disable Position */
+#define DEVIDR_PEP_5                  (_U_(0x1) << DEVIDR_PEP_5_Pos)           /**< (DEVIDR) Endpoint 5 Interrupt Disable Mask */
+#define DEVIDR_PEP_6_Pos              18                                             /**< (DEVIDR) Endpoint 6 Interrupt Disable Position */
+#define DEVIDR_PEP_6                  (_U_(0x1) << DEVIDR_PEP_6_Pos)           /**< (DEVIDR) Endpoint 6 Interrupt Disable Mask */
+#define DEVIDR_PEP_7_Pos              19                                             /**< (DEVIDR) Endpoint 7 Interrupt Disable Position */
+#define DEVIDR_PEP_7                  (_U_(0x1) << DEVIDR_PEP_7_Pos)           /**< (DEVIDR) Endpoint 7 Interrupt Disable Mask */
+#define DEVIDR_PEP_8_Pos              20                                             /**< (DEVIDR) Endpoint 8 Interrupt Disable Position */
+#define DEVIDR_PEP_8                  (_U_(0x1) << DEVIDR_PEP_8_Pos)           /**< (DEVIDR) Endpoint 8 Interrupt Disable Mask */
+#define DEVIDR_PEP_9_Pos              21                                             /**< (DEVIDR) Endpoint 9 Interrupt Disable Position */
+#define DEVIDR_PEP_9                  (_U_(0x1) << DEVIDR_PEP_9_Pos)           /**< (DEVIDR) Endpoint 9 Interrupt Disable Mask */
+#define DEVIDR_DMA_1_Pos              25                                             /**< (DEVIDR) DMA Channel 1 Interrupt Disable Position */
+#define DEVIDR_DMA_1                  (_U_(0x1) << DEVIDR_DMA_1_Pos)           /**< (DEVIDR) DMA Channel 1 Interrupt Disable Mask */
+#define DEVIDR_DMA_2_Pos              26                                             /**< (DEVIDR) DMA Channel 2 Interrupt Disable Position */
+#define DEVIDR_DMA_2                  (_U_(0x1) << DEVIDR_DMA_2_Pos)           /**< (DEVIDR) DMA Channel 2 Interrupt Disable Mask */
+#define DEVIDR_DMA_3_Pos              27                                             /**< (DEVIDR) DMA Channel 3 Interrupt Disable Position */
+#define DEVIDR_DMA_3                  (_U_(0x1) << DEVIDR_DMA_3_Pos)           /**< (DEVIDR) DMA Channel 3 Interrupt Disable Mask */
+#define DEVIDR_DMA_4_Pos              28                                             /**< (DEVIDR) DMA Channel 4 Interrupt Disable Position */
+#define DEVIDR_DMA_4                  (_U_(0x1) << DEVIDR_DMA_4_Pos)           /**< (DEVIDR) DMA Channel 4 Interrupt Disable Mask */
+#define DEVIDR_DMA_5_Pos              29                                             /**< (DEVIDR) DMA Channel 5 Interrupt Disable Position */
+#define DEVIDR_DMA_5                  (_U_(0x1) << DEVIDR_DMA_5_Pos)           /**< (DEVIDR) DMA Channel 5 Interrupt Disable Mask */
+#define DEVIDR_DMA_6_Pos              30                                             /**< (DEVIDR) DMA Channel 6 Interrupt Disable Position */
+#define DEVIDR_DMA_6                  (_U_(0x1) << DEVIDR_DMA_6_Pos)           /**< (DEVIDR) DMA Channel 6 Interrupt Disable Mask */
+#define DEVIDR_DMA_7_Pos              31                                             /**< (DEVIDR) DMA Channel 7 Interrupt Disable Position */
+#define DEVIDR_DMA_7                  (_U_(0x1) << DEVIDR_DMA_7_Pos)           /**< (DEVIDR) DMA Channel 7 Interrupt Disable Mask */
+#define DEVIDR_Msk                    _U_(0xFE3FF07F)                                /**< (DEVIDR) Register Mask  */
+
+#define DEVIDR_PEP__Pos               12                                             /**< (DEVIDR Position) Endpoint x Interrupt Disable */
+#define DEVIDR_PEP_                   (_U_(0x3FF) << DEVIDR_PEP__Pos)          /**< (DEVIDR Mask) PEP_ */
+#define DEVIDR_DMA__Pos               25                                             /**< (DEVIDR Position) DMA Channel 7 Interrupt Disable */
+#define DEVIDR_DMA_                   (_U_(0x7F) << DEVIDR_DMA__Pos)           /**< (DEVIDR Mask) DMA_ */
+
+/* -------- DEVIER : (USBHS Offset: 0x18) (/W 32) Device Global Interrupt Enable Register -------- */
+
+#define DEVIER_OFFSET                 (0x18)                                        /**<  (DEVIER) Device Global Interrupt Enable Register  Offset */
+
+#define DEVIER_SUSPES_Pos             0                                              /**< (DEVIER) Suspend Interrupt Enable Position */
+#define DEVIER_SUSPES                 (_U_(0x1) << DEVIER_SUSPES_Pos)          /**< (DEVIER) Suspend Interrupt Enable Mask */
+#define DEVIER_MSOFES_Pos             1                                              /**< (DEVIER) Micro Start of Frame Interrupt Enable Position */
+#define DEVIER_MSOFES                 (_U_(0x1) << DEVIER_MSOFES_Pos)          /**< (DEVIER) Micro Start of Frame Interrupt Enable Mask */
+#define DEVIER_SOFES_Pos              2                                              /**< (DEVIER) Start of Frame Interrupt Enable Position */
+#define DEVIER_SOFES                  (_U_(0x1) << DEVIER_SOFES_Pos)           /**< (DEVIER) Start of Frame Interrupt Enable Mask */
+#define DEVIER_EORSTES_Pos            3                                              /**< (DEVIER) End of Reset Interrupt Enable Position */
+#define DEVIER_EORSTES                (_U_(0x1) << DEVIER_EORSTES_Pos)         /**< (DEVIER) End of Reset Interrupt Enable Mask */
+#define DEVIER_WAKEUPES_Pos           4                                              /**< (DEVIER) Wake-Up Interrupt Enable Position */
+#define DEVIER_WAKEUPES               (_U_(0x1) << DEVIER_WAKEUPES_Pos)        /**< (DEVIER) Wake-Up Interrupt Enable Mask */
+#define DEVIER_EORSMES_Pos            5                                              /**< (DEVIER) End of Resume Interrupt Enable Position */
+#define DEVIER_EORSMES                (_U_(0x1) << DEVIER_EORSMES_Pos)         /**< (DEVIER) End of Resume Interrupt Enable Mask */
+#define DEVIER_UPRSMES_Pos            6                                              /**< (DEVIER) Upstream Resume Interrupt Enable Position */
+#define DEVIER_UPRSMES                (_U_(0x1) << DEVIER_UPRSMES_Pos)         /**< (DEVIER) Upstream Resume Interrupt Enable Mask */
+#define DEVIER_PEP_0_Pos              12                                             /**< (DEVIER) Endpoint 0 Interrupt Enable Position */
+#define DEVIER_PEP_0                  (_U_(0x1) << DEVIER_PEP_0_Pos)           /**< (DEVIER) Endpoint 0 Interrupt Enable Mask */
+#define DEVIER_PEP_1_Pos              13                                             /**< (DEVIER) Endpoint 1 Interrupt Enable Position */
+#define DEVIER_PEP_1                  (_U_(0x1) << DEVIER_PEP_1_Pos)           /**< (DEVIER) Endpoint 1 Interrupt Enable Mask */
+#define DEVIER_PEP_2_Pos              14                                             /**< (DEVIER) Endpoint 2 Interrupt Enable Position */
+#define DEVIER_PEP_2                  (_U_(0x1) << DEVIER_PEP_2_Pos)           /**< (DEVIER) Endpoint 2 Interrupt Enable Mask */
+#define DEVIER_PEP_3_Pos              15                                             /**< (DEVIER) Endpoint 3 Interrupt Enable Position */
+#define DEVIER_PEP_3                  (_U_(0x1) << DEVIER_PEP_3_Pos)           /**< (DEVIER) Endpoint 3 Interrupt Enable Mask */
+#define DEVIER_PEP_4_Pos              16                                             /**< (DEVIER) Endpoint 4 Interrupt Enable Position */
+#define DEVIER_PEP_4                  (_U_(0x1) << DEVIER_PEP_4_Pos)           /**< (DEVIER) Endpoint 4 Interrupt Enable Mask */
+#define DEVIER_PEP_5_Pos              17                                             /**< (DEVIER) Endpoint 5 Interrupt Enable Position */
+#define DEVIER_PEP_5                  (_U_(0x1) << DEVIER_PEP_5_Pos)           /**< (DEVIER) Endpoint 5 Interrupt Enable Mask */
+#define DEVIER_PEP_6_Pos              18                                             /**< (DEVIER) Endpoint 6 Interrupt Enable Position */
+#define DEVIER_PEP_6                  (_U_(0x1) << DEVIER_PEP_6_Pos)           /**< (DEVIER) Endpoint 6 Interrupt Enable Mask */
+#define DEVIER_PEP_7_Pos              19                                             /**< (DEVIER) Endpoint 7 Interrupt Enable Position */
+#define DEVIER_PEP_7                  (_U_(0x1) << DEVIER_PEP_7_Pos)           /**< (DEVIER) Endpoint 7 Interrupt Enable Mask */
+#define DEVIER_PEP_8_Pos              20                                             /**< (DEVIER) Endpoint 8 Interrupt Enable Position */
+#define DEVIER_PEP_8                  (_U_(0x1) << DEVIER_PEP_8_Pos)           /**< (DEVIER) Endpoint 8 Interrupt Enable Mask */
+#define DEVIER_PEP_9_Pos              21                                             /**< (DEVIER) Endpoint 9 Interrupt Enable Position */
+#define DEVIER_PEP_9                  (_U_(0x1) << DEVIER_PEP_9_Pos)           /**< (DEVIER) Endpoint 9 Interrupt Enable Mask */
+#define DEVIER_DMA_1_Pos              25                                             /**< (DEVIER) DMA Channel 1 Interrupt Enable Position */
+#define DEVIER_DMA_1                  (_U_(0x1) << DEVIER_DMA_1_Pos)           /**< (DEVIER) DMA Channel 1 Interrupt Enable Mask */
+#define DEVIER_DMA_2_Pos              26                                             /**< (DEVIER) DMA Channel 2 Interrupt Enable Position */
+#define DEVIER_DMA_2                  (_U_(0x1) << DEVIER_DMA_2_Pos)           /**< (DEVIER) DMA Channel 2 Interrupt Enable Mask */
+#define DEVIER_DMA_3_Pos              27                                             /**< (DEVIER) DMA Channel 3 Interrupt Enable Position */
+#define DEVIER_DMA_3                  (_U_(0x1) << DEVIER_DMA_3_Pos)           /**< (DEVIER) DMA Channel 3 Interrupt Enable Mask */
+#define DEVIER_DMA_4_Pos              28                                             /**< (DEVIER) DMA Channel 4 Interrupt Enable Position */
+#define DEVIER_DMA_4                  (_U_(0x1) << DEVIER_DMA_4_Pos)           /**< (DEVIER) DMA Channel 4 Interrupt Enable Mask */
+#define DEVIER_DMA_5_Pos              29                                             /**< (DEVIER) DMA Channel 5 Interrupt Enable Position */
+#define DEVIER_DMA_5                  (_U_(0x1) << DEVIER_DMA_5_Pos)           /**< (DEVIER) DMA Channel 5 Interrupt Enable Mask */
+#define DEVIER_DMA_6_Pos              30                                             /**< (DEVIER) DMA Channel 6 Interrupt Enable Position */
+#define DEVIER_DMA_6                  (_U_(0x1) << DEVIER_DMA_6_Pos)           /**< (DEVIER) DMA Channel 6 Interrupt Enable Mask */
+#define DEVIER_DMA_7_Pos              31                                             /**< (DEVIER) DMA Channel 7 Interrupt Enable Position */
+#define DEVIER_DMA_7                  (_U_(0x1) << DEVIER_DMA_7_Pos)           /**< (DEVIER) DMA Channel 7 Interrupt Enable Mask */
+#define DEVIER_Msk                    _U_(0xFE3FF07F)                                /**< (DEVIER) Register Mask  */
+
+#define DEVIER_PEP__Pos               12                                             /**< (DEVIER Position) Endpoint x Interrupt Enable */
+#define DEVIER_PEP_                   (_U_(0x3FF) << DEVIER_PEP__Pos)          /**< (DEVIER Mask) PEP_ */
+#define DEVIER_DMA__Pos               25                                             /**< (DEVIER Position) DMA Channel 7 Interrupt Enable */
+#define DEVIER_DMA_                   (_U_(0x7F) << DEVIER_DMA__Pos)           /**< (DEVIER Mask) DMA_ */
+
+/* -------- DEVEPT : (USBHS Offset: 0x1c) (R/W 32) Device Endpoint Register -------- */
+
+#define DEVEPT_OFFSET                 (0x1C)                                        /**<  (DEVEPT) Device Endpoint Register  Offset */
+
+#define DEVEPT_EPEN0_Pos              0                                              /**< (DEVEPT) Endpoint 0 Enable Position */
+#define DEVEPT_EPEN0                  (_U_(0x1) << DEVEPT_EPEN0_Pos)           /**< (DEVEPT) Endpoint 0 Enable Mask */
+#define DEVEPT_EPEN1_Pos              1                                              /**< (DEVEPT) Endpoint 1 Enable Position */
+#define DEVEPT_EPEN1                  (_U_(0x1) << DEVEPT_EPEN1_Pos)           /**< (DEVEPT) Endpoint 1 Enable Mask */
+#define DEVEPT_EPEN2_Pos              2                                              /**< (DEVEPT) Endpoint 2 Enable Position */
+#define DEVEPT_EPEN2                  (_U_(0x1) << DEVEPT_EPEN2_Pos)           /**< (DEVEPT) Endpoint 2 Enable Mask */
+#define DEVEPT_EPEN3_Pos              3                                              /**< (DEVEPT) Endpoint 3 Enable Position */
+#define DEVEPT_EPEN3                  (_U_(0x1) << DEVEPT_EPEN3_Pos)           /**< (DEVEPT) Endpoint 3 Enable Mask */
+#define DEVEPT_EPEN4_Pos              4                                              /**< (DEVEPT) Endpoint 4 Enable Position */
+#define DEVEPT_EPEN4                  (_U_(0x1) << DEVEPT_EPEN4_Pos)           /**< (DEVEPT) Endpoint 4 Enable Mask */
+#define DEVEPT_EPEN5_Pos              5                                              /**< (DEVEPT) Endpoint 5 Enable Position */
+#define DEVEPT_EPEN5                  (_U_(0x1) << DEVEPT_EPEN5_Pos)           /**< (DEVEPT) Endpoint 5 Enable Mask */
+#define DEVEPT_EPEN6_Pos              6                                              /**< (DEVEPT) Endpoint 6 Enable Position */
+#define DEVEPT_EPEN6                  (_U_(0x1) << DEVEPT_EPEN6_Pos)           /**< (DEVEPT) Endpoint 6 Enable Mask */
+#define DEVEPT_EPEN7_Pos              7                                              /**< (DEVEPT) Endpoint 7 Enable Position */
+#define DEVEPT_EPEN7                  (_U_(0x1) << DEVEPT_EPEN7_Pos)           /**< (DEVEPT) Endpoint 7 Enable Mask */
+#define DEVEPT_EPEN8_Pos              8                                              /**< (DEVEPT) Endpoint 8 Enable Position */
+#define DEVEPT_EPEN8                  (_U_(0x1) << DEVEPT_EPEN8_Pos)           /**< (DEVEPT) Endpoint 8 Enable Mask */
+#define DEVEPT_EPEN9_Pos              9                                              /**< (DEVEPT) Endpoint 9 Enable Position */
+#define DEVEPT_EPEN9                  (_U_(0x1) << DEVEPT_EPEN9_Pos)           /**< (DEVEPT) Endpoint 9 Enable Mask */
+#define DEVEPT_EPRST0_Pos             16                                             /**< (DEVEPT) Endpoint 0 Reset Position */
+#define DEVEPT_EPRST0                 (_U_(0x1) << DEVEPT_EPRST0_Pos)          /**< (DEVEPT) Endpoint 0 Reset Mask */
+#define DEVEPT_EPRST1_Pos             17                                             /**< (DEVEPT) Endpoint 1 Reset Position */
+#define DEVEPT_EPRST1                 (_U_(0x1) << DEVEPT_EPRST1_Pos)          /**< (DEVEPT) Endpoint 1 Reset Mask */
+#define DEVEPT_EPRST2_Pos             18                                             /**< (DEVEPT) Endpoint 2 Reset Position */
+#define DEVEPT_EPRST2                 (_U_(0x1) << DEVEPT_EPRST2_Pos)          /**< (DEVEPT) Endpoint 2 Reset Mask */
+#define DEVEPT_EPRST3_Pos             19                                             /**< (DEVEPT) Endpoint 3 Reset Position */
+#define DEVEPT_EPRST3                 (_U_(0x1) << DEVEPT_EPRST3_Pos)          /**< (DEVEPT) Endpoint 3 Reset Mask */
+#define DEVEPT_EPRST4_Pos             20                                             /**< (DEVEPT) Endpoint 4 Reset Position */
+#define DEVEPT_EPRST4                 (_U_(0x1) << DEVEPT_EPRST4_Pos)          /**< (DEVEPT) Endpoint 4 Reset Mask */
+#define DEVEPT_EPRST5_Pos             21                                             /**< (DEVEPT) Endpoint 5 Reset Position */
+#define DEVEPT_EPRST5                 (_U_(0x1) << DEVEPT_EPRST5_Pos)          /**< (DEVEPT) Endpoint 5 Reset Mask */
+#define DEVEPT_EPRST6_Pos             22                                             /**< (DEVEPT) Endpoint 6 Reset Position */
+#define DEVEPT_EPRST6                 (_U_(0x1) << DEVEPT_EPRST6_Pos)          /**< (DEVEPT) Endpoint 6 Reset Mask */
+#define DEVEPT_EPRST7_Pos             23                                             /**< (DEVEPT) Endpoint 7 Reset Position */
+#define DEVEPT_EPRST7                 (_U_(0x1) << DEVEPT_EPRST7_Pos)          /**< (DEVEPT) Endpoint 7 Reset Mask */
+#define DEVEPT_EPRST8_Pos             24                                             /**< (DEVEPT) Endpoint 8 Reset Position */
+#define DEVEPT_EPRST8                 (_U_(0x1) << DEVEPT_EPRST8_Pos)          /**< (DEVEPT) Endpoint 8 Reset Mask */
+#define DEVEPT_EPRST9_Pos             25                                             /**< (DEVEPT) Endpoint 9 Reset Position */
+#define DEVEPT_EPRST9                 (_U_(0x1) << DEVEPT_EPRST9_Pos)          /**< (DEVEPT) Endpoint 9 Reset Mask */
+#define DEVEPT_Msk                    _U_(0x3FF03FF)                                 /**< (DEVEPT) Register Mask  */
+
+#define DEVEPT_EPEN_Pos               0                                              /**< (DEVEPT Position) Endpoint x Enable */
+#define DEVEPT_EPEN                   (_U_(0x3FF) << DEVEPT_EPEN_Pos)          /**< (DEVEPT Mask) EPEN */
+#define DEVEPT_EPRST_Pos              16                                             /**< (DEVEPT Position) Endpoint 9 Reset */
+#define DEVEPT_EPRST                  (_U_(0x3FF) << DEVEPT_EPRST_Pos)         /**< (DEVEPT Mask) EPRST */
+
+/* -------- DEVFNUM : (USBHS Offset: 0x20) (R/ 32) Device Frame Number Register -------- */
+
+#define DEVFNUM_OFFSET                (0x20)                                        /**<  (DEVFNUM) Device Frame Number Register  Offset */
+
+#define DEVFNUM_MFNUM_Pos             0                                              /**< (DEVFNUM) Micro Frame Number Position */
+#define DEVFNUM_MFNUM                 (_U_(0x7) << DEVFNUM_MFNUM_Pos)          /**< (DEVFNUM) Micro Frame Number Mask */
+#define DEVFNUM_FNUM_Pos              3                                              /**< (DEVFNUM) Frame Number Position */
+#define DEVFNUM_FNUM                  (_U_(0x7FF) << DEVFNUM_FNUM_Pos)         /**< (DEVFNUM) Frame Number Mask */
+#define DEVFNUM_FNCERR_Pos            15                                             /**< (DEVFNUM) Frame Number CRC Error Position */
+#define DEVFNUM_FNCERR                (_U_(0x1) << DEVFNUM_FNCERR_Pos)         /**< (DEVFNUM) Frame Number CRC Error Mask */
+#define DEVFNUM_Msk                   _U_(0xBFFF)                                    /**< (DEVFNUM) Register Mask  */
+
+
+/* -------- DEVEPTCFG : (USBHS Offset: 0x100) (R/W 32) Device Endpoint Configuration Register -------- */
+
+#define DEVEPTCFG_OFFSET              (0x100)                                       /**<  (DEVEPTCFG) Device Endpoint Configuration Register  Offset */
+
+#define DEVEPTCFG_ALLOC_Pos           1                                              /**< (DEVEPTCFG) Endpoint Memory Allocate Position */
+#define DEVEPTCFG_ALLOC               (_U_(0x1) << DEVEPTCFG_ALLOC_Pos)        /**< (DEVEPTCFG) Endpoint Memory Allocate Mask */
+#define DEVEPTCFG_EPBK_Pos            2                                              /**< (DEVEPTCFG) Endpoint Banks Position */
+#define DEVEPTCFG_EPBK                (_U_(0x3) << DEVEPTCFG_EPBK_Pos)         /**< (DEVEPTCFG) Endpoint Banks Mask */
+#define   DEVEPTCFG_EPBK_1_BANK_Val   _U_(0x0)                                       /**< (DEVEPTCFG) Single-bank endpoint  */
+#define   DEVEPTCFG_EPBK_2_BANK_Val   _U_(0x1)                                       /**< (DEVEPTCFG) Double-bank endpoint  */
+#define   DEVEPTCFG_EPBK_3_BANK_Val   _U_(0x2)                                       /**< (DEVEPTCFG) Triple-bank endpoint  */
+#define DEVEPTCFG_EPBK_1_BANK         (DEVEPTCFG_EPBK_1_BANK_Val << DEVEPTCFG_EPBK_Pos)  /**< (DEVEPTCFG) Single-bank endpoint Position  */
+#define DEVEPTCFG_EPBK_2_BANK         (DEVEPTCFG_EPBK_2_BANK_Val << DEVEPTCFG_EPBK_Pos)  /**< (DEVEPTCFG) Double-bank endpoint Position  */
+#define DEVEPTCFG_EPBK_3_BANK         (DEVEPTCFG_EPBK_3_BANK_Val << DEVEPTCFG_EPBK_Pos)  /**< (DEVEPTCFG) Triple-bank endpoint Position  */
+#define DEVEPTCFG_EPSIZE_Pos          4                                              /**< (DEVEPTCFG) Endpoint Size Position */
+#define DEVEPTCFG_EPSIZE              (_U_(0x7) << DEVEPTCFG_EPSIZE_Pos)       /**< (DEVEPTCFG) Endpoint Size Mask */
+#define   DEVEPTCFG_EPSIZE_8_BYTE_Val _U_(0x0)                                       /**< (DEVEPTCFG) 8 bytes  */
+#define   DEVEPTCFG_EPSIZE_16_BYTE_Val _U_(0x1)                                       /**< (DEVEPTCFG) 16 bytes  */
+#define   DEVEPTCFG_EPSIZE_32_BYTE_Val _U_(0x2)                                       /**< (DEVEPTCFG) 32 bytes  */
+#define   DEVEPTCFG_EPSIZE_64_BYTE_Val _U_(0x3)                                       /**< (DEVEPTCFG) 64 bytes  */
+#define   DEVEPTCFG_EPSIZE_128_BYTE_Val _U_(0x4)                                       /**< (DEVEPTCFG) 128 bytes  */
+#define   DEVEPTCFG_EPSIZE_256_BYTE_Val _U_(0x5)                                       /**< (DEVEPTCFG) 256 bytes  */
+#define   DEVEPTCFG_EPSIZE_512_BYTE_Val _U_(0x6)                                       /**< (DEVEPTCFG) 512 bytes  */
+#define   DEVEPTCFG_EPSIZE_1024_BYTE_Val _U_(0x7)                                       /**< (DEVEPTCFG) 1024 bytes  */
+#define DEVEPTCFG_EPSIZE_8_BYTE       (DEVEPTCFG_EPSIZE_8_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)  /**< (DEVEPTCFG) 8 bytes Position  */
+#define DEVEPTCFG_EPSIZE_16_BYTE      (DEVEPTCFG_EPSIZE_16_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)  /**< (DEVEPTCFG) 16 bytes Position  */
+#define DEVEPTCFG_EPSIZE_32_BYTE      (DEVEPTCFG_EPSIZE_32_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)  /**< (DEVEPTCFG) 32 bytes Position  */
+#define DEVEPTCFG_EPSIZE_64_BYTE      (DEVEPTCFG_EPSIZE_64_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)  /**< (DEVEPTCFG) 64 bytes Position  */
+#define DEVEPTCFG_EPSIZE_128_BYTE     (DEVEPTCFG_EPSIZE_128_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)  /**< (DEVEPTCFG) 128 bytes Position  */
+#define DEVEPTCFG_EPSIZE_256_BYTE     (DEVEPTCFG_EPSIZE_256_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)  /**< (DEVEPTCFG) 256 bytes Position  */
+#define DEVEPTCFG_EPSIZE_512_BYTE     (DEVEPTCFG_EPSIZE_512_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)  /**< (DEVEPTCFG) 512 bytes Position  */
+#define DEVEPTCFG_EPSIZE_1024_BYTE    (DEVEPTCFG_EPSIZE_1024_BYTE_Val << DEVEPTCFG_EPSIZE_Pos)  /**< (DEVEPTCFG) 1024 bytes Position  */
+#define DEVEPTCFG_EPDIR_Pos           8                                              /**< (DEVEPTCFG) Endpoint Direction Position */
+#define DEVEPTCFG_EPDIR               (_U_(0x1) << DEVEPTCFG_EPDIR_Pos)        /**< (DEVEPTCFG) Endpoint Direction Mask */
+#define   DEVEPTCFG_EPDIR_OUT_Val     _U_(0x0)                                       /**< (DEVEPTCFG) The endpoint direction is OUT.  */
+#define   DEVEPTCFG_EPDIR_IN_Val      _U_(0x1)                                       /**< (DEVEPTCFG) The endpoint direction is IN (nor for control endpoints).  */
+#define DEVEPTCFG_EPDIR_OUT           (DEVEPTCFG_EPDIR_OUT_Val << DEVEPTCFG_EPDIR_Pos)  /**< (DEVEPTCFG) The endpoint direction is OUT. Position  */
+#define DEVEPTCFG_EPDIR_IN            (DEVEPTCFG_EPDIR_IN_Val << DEVEPTCFG_EPDIR_Pos)  /**< (DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). Position  */
+#define DEVEPTCFG_AUTOSW_Pos          9                                              /**< (DEVEPTCFG) Automatic Switch Position */
+#define DEVEPTCFG_AUTOSW              (_U_(0x1) << DEVEPTCFG_AUTOSW_Pos)       /**< (DEVEPTCFG) Automatic Switch Mask */
+#define DEVEPTCFG_EPTYPE_Pos          11                                             /**< (DEVEPTCFG) Endpoint Type Position */
+#define DEVEPTCFG_EPTYPE              (_U_(0x3) << DEVEPTCFG_EPTYPE_Pos)       /**< (DEVEPTCFG) Endpoint Type Mask */
+#define   DEVEPTCFG_EPTYPE_CTRL_Val   _U_(0x0)                                       /**< (DEVEPTCFG) Control  */
+#define   DEVEPTCFG_EPTYPE_ISO_Val    _U_(0x1)                                       /**< (DEVEPTCFG) Isochronous  */
+#define   DEVEPTCFG_EPTYPE_BLK_Val    _U_(0x2)                                       /**< (DEVEPTCFG) Bulk  */
+#define   DEVEPTCFG_EPTYPE_INTRPT_Val _U_(0x3)                                       /**< (DEVEPTCFG) Interrupt  */
+#define DEVEPTCFG_EPTYPE_CTRL         (DEVEPTCFG_EPTYPE_CTRL_Val << DEVEPTCFG_EPTYPE_Pos)  /**< (DEVEPTCFG) Control Position  */
+#define DEVEPTCFG_EPTYPE_ISO          (DEVEPTCFG_EPTYPE_ISO_Val << DEVEPTCFG_EPTYPE_Pos)  /**< (DEVEPTCFG) Isochronous Position  */
+#define DEVEPTCFG_EPTYPE_BLK          (DEVEPTCFG_EPTYPE_BLK_Val << DEVEPTCFG_EPTYPE_Pos)  /**< (DEVEPTCFG) Bulk Position  */
+#define DEVEPTCFG_EPTYPE_INTRPT       (DEVEPTCFG_EPTYPE_INTRPT_Val << DEVEPTCFG_EPTYPE_Pos)  /**< (DEVEPTCFG) Interrupt Position  */
+#define DEVEPTCFG_NBTRANS_Pos         13                                             /**< (DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Position */
+#define DEVEPTCFG_NBTRANS             (_U_(0x3) << DEVEPTCFG_NBTRANS_Pos)      /**< (DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Mask */
+#define   DEVEPTCFG_NBTRANS_0_TRANS_Val _U_(0x0)                                       /**< (DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability.  */
+#define   DEVEPTCFG_NBTRANS_1_TRANS_Val _U_(0x1)                                       /**< (DEVEPTCFG) Default value: one transaction per microframe.  */
+#define   DEVEPTCFG_NBTRANS_2_TRANS_Val _U_(0x2)                                       /**< (DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank.  */
+#define   DEVEPTCFG_NBTRANS_3_TRANS_Val _U_(0x3)                                       /**< (DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank.  */
+#define DEVEPTCFG_NBTRANS_0_TRANS     (DEVEPTCFG_NBTRANS_0_TRANS_Val << DEVEPTCFG_NBTRANS_Pos)  /**< (DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. Position  */
+#define DEVEPTCFG_NBTRANS_1_TRANS     (DEVEPTCFG_NBTRANS_1_TRANS_Val << DEVEPTCFG_NBTRANS_Pos)  /**< (DEVEPTCFG) Default value: one transaction per microframe. Position  */
+#define DEVEPTCFG_NBTRANS_2_TRANS     (DEVEPTCFG_NBTRANS_2_TRANS_Val << DEVEPTCFG_NBTRANS_Pos)  /**< (DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. Position  */
+#define DEVEPTCFG_NBTRANS_3_TRANS     (DEVEPTCFG_NBTRANS_3_TRANS_Val << DEVEPTCFG_NBTRANS_Pos)  /**< (DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. Position  */
+#define DEVEPTCFG_Msk                 _U_(0x7B7E)                                    /**< (DEVEPTCFG) Register Mask  */
+
+
+/* -------- DEVEPTISR : (USBHS Offset: 0x130) (R/ 32) Device Endpoint Interrupt Status Register -------- */
+
+#define DEVEPTISR_OFFSET              (0x130)                                       /**<  (DEVEPTISR) Device Endpoint Interrupt Status Register  Offset */
+
+#define DEVEPTISR_TXINI_Pos           0                                              /**< (DEVEPTISR) Transmitted IN Data Interrupt Position */
+#define DEVEPTISR_TXINI               (_U_(0x1) << DEVEPTISR_TXINI_Pos)        /**< (DEVEPTISR) Transmitted IN Data Interrupt Mask */
+#define DEVEPTISR_RXOUTI_Pos          1                                              /**< (DEVEPTISR) Received OUT Data Interrupt Position */
+#define DEVEPTISR_RXOUTI              (_U_(0x1) << DEVEPTISR_RXOUTI_Pos)       /**< (DEVEPTISR) Received OUT Data Interrupt Mask */
+#define DEVEPTISR_OVERFI_Pos          5                                              /**< (DEVEPTISR) Overflow Interrupt Position */
+#define DEVEPTISR_OVERFI              (_U_(0x1) << DEVEPTISR_OVERFI_Pos)       /**< (DEVEPTISR) Overflow Interrupt Mask */
+#define DEVEPTISR_SHORTPACKET_Pos     7                                              /**< (DEVEPTISR) Short Packet Interrupt Position */
+#define DEVEPTISR_SHORTPACKET         (_U_(0x1) << DEVEPTISR_SHORTPACKET_Pos)  /**< (DEVEPTISR) Short Packet Interrupt Mask */
+#define DEVEPTISR_DTSEQ_Pos           8                                              /**< (DEVEPTISR) Data Toggle Sequence Position */
+#define DEVEPTISR_DTSEQ               (_U_(0x3) << DEVEPTISR_DTSEQ_Pos)        /**< (DEVEPTISR) Data Toggle Sequence Mask */
+#define   DEVEPTISR_DTSEQ_DATA0_Val   _U_(0x0)                                       /**< (DEVEPTISR) Data0 toggle sequence  */
+#define   DEVEPTISR_DTSEQ_DATA1_Val   _U_(0x1)                                       /**< (DEVEPTISR) Data1 toggle sequence  */
+#define   DEVEPTISR_DTSEQ_DATA2_Val   _U_(0x2)                                       /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint  */
+#define   DEVEPTISR_DTSEQ_MDATA_Val   _U_(0x3)                                       /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint  */
+#define DEVEPTISR_DTSEQ_DATA0         (DEVEPTISR_DTSEQ_DATA0_Val << DEVEPTISR_DTSEQ_Pos)  /**< (DEVEPTISR) Data0 toggle sequence Position  */
+#define DEVEPTISR_DTSEQ_DATA1         (DEVEPTISR_DTSEQ_DATA1_Val << DEVEPTISR_DTSEQ_Pos)  /**< (DEVEPTISR) Data1 toggle sequence Position  */
+#define DEVEPTISR_DTSEQ_DATA2         (DEVEPTISR_DTSEQ_DATA2_Val << DEVEPTISR_DTSEQ_Pos)  /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position  */
+#define DEVEPTISR_DTSEQ_MDATA         (DEVEPTISR_DTSEQ_MDATA_Val << DEVEPTISR_DTSEQ_Pos)  /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position  */
+#define DEVEPTISR_NBUSYBK_Pos         12                                             /**< (DEVEPTISR) Number of Busy Banks Position */
+#define DEVEPTISR_NBUSYBK             (_U_(0x3) << DEVEPTISR_NBUSYBK_Pos)      /**< (DEVEPTISR) Number of Busy Banks Mask */
+#define   DEVEPTISR_NBUSYBK_0_BUSY_Val _U_(0x0)                                       /**< (DEVEPTISR) 0 busy bank (all banks free)  */
+#define   DEVEPTISR_NBUSYBK_1_BUSY_Val _U_(0x1)                                       /**< (DEVEPTISR) 1 busy bank  */
+#define   DEVEPTISR_NBUSYBK_2_BUSY_Val _U_(0x2)                                       /**< (DEVEPTISR) 2 busy banks  */
+#define   DEVEPTISR_NBUSYBK_3_BUSY_Val _U_(0x3)                                       /**< (DEVEPTISR) 3 busy banks  */
+#define DEVEPTISR_NBUSYBK_0_BUSY      (DEVEPTISR_NBUSYBK_0_BUSY_Val << DEVEPTISR_NBUSYBK_Pos)  /**< (DEVEPTISR) 0 busy bank (all banks free) Position  */
+#define DEVEPTISR_NBUSYBK_1_BUSY      (DEVEPTISR_NBUSYBK_1_BUSY_Val << DEVEPTISR_NBUSYBK_Pos)  /**< (DEVEPTISR) 1 busy bank Position  */
+#define DEVEPTISR_NBUSYBK_2_BUSY      (DEVEPTISR_NBUSYBK_2_BUSY_Val << DEVEPTISR_NBUSYBK_Pos)  /**< (DEVEPTISR) 2 busy banks Position  */
+#define DEVEPTISR_NBUSYBK_3_BUSY      (DEVEPTISR_NBUSYBK_3_BUSY_Val << DEVEPTISR_NBUSYBK_Pos)  /**< (DEVEPTISR) 3 busy banks Position  */
+#define DEVEPTISR_CURRBK_Pos          14                                             /**< (DEVEPTISR) Current Bank Position */
+#define DEVEPTISR_CURRBK              (_U_(0x3) << DEVEPTISR_CURRBK_Pos)       /**< (DEVEPTISR) Current Bank Mask */
+#define   DEVEPTISR_CURRBK_BANK0_Val  _U_(0x0)                                       /**< (DEVEPTISR) Current bank is bank0  */
+#define   DEVEPTISR_CURRBK_BANK1_Val  _U_(0x1)                                       /**< (DEVEPTISR) Current bank is bank1  */
+#define   DEVEPTISR_CURRBK_BANK2_Val  _U_(0x2)                                       /**< (DEVEPTISR) Current bank is bank2  */
+#define DEVEPTISR_CURRBK_BANK0        (DEVEPTISR_CURRBK_BANK0_Val << DEVEPTISR_CURRBK_Pos)  /**< (DEVEPTISR) Current bank is bank0 Position  */
+#define DEVEPTISR_CURRBK_BANK1        (DEVEPTISR_CURRBK_BANK1_Val << DEVEPTISR_CURRBK_Pos)  /**< (DEVEPTISR) Current bank is bank1 Position  */
+#define DEVEPTISR_CURRBK_BANK2        (DEVEPTISR_CURRBK_BANK2_Val << DEVEPTISR_CURRBK_Pos)  /**< (DEVEPTISR) Current bank is bank2 Position  */
+#define DEVEPTISR_RWALL_Pos           16                                             /**< (DEVEPTISR) Read/Write Allowed Position */
+#define DEVEPTISR_RWALL               (_U_(0x1) << DEVEPTISR_RWALL_Pos)        /**< (DEVEPTISR) Read/Write Allowed Mask */
+#define DEVEPTISR_CFGOK_Pos           18                                             /**< (DEVEPTISR) Configuration OK Status Position */
+#define DEVEPTISR_CFGOK               (_U_(0x1) << DEVEPTISR_CFGOK_Pos)        /**< (DEVEPTISR) Configuration OK Status Mask */
+#define DEVEPTISR_BYCT_Pos            20                                             /**< (DEVEPTISR) Byte Count Position */
+#define DEVEPTISR_BYCT                (_U_(0x7FF) << DEVEPTISR_BYCT_Pos)       /**< (DEVEPTISR) Byte Count Mask */
+#define DEVEPTISR_Msk                 _U_(0x7FF5F3A3)                                /**< (DEVEPTISR) Register Mask  */
+
+/* CTRL mode */
+#define DEVEPTISR_CTRL_RXSTPI_Pos     2                                              /**< (DEVEPTISR) Received SETUP Interrupt Position */
+#define DEVEPTISR_CTRL_RXSTPI         (_U_(0x1) << DEVEPTISR_CTRL_RXSTPI_Pos)  /**< (DEVEPTISR) Received SETUP Interrupt Mask */
+#define DEVEPTISR_CTRL_NAKOUTI_Pos    3                                              /**< (DEVEPTISR) NAKed OUT Interrupt Position */
+#define DEVEPTISR_CTRL_NAKOUTI        (_U_(0x1) << DEVEPTISR_CTRL_NAKOUTI_Pos)  /**< (DEVEPTISR) NAKed OUT Interrupt Mask */
+#define DEVEPTISR_CTRL_NAKINI_Pos     4                                              /**< (DEVEPTISR) NAKed IN Interrupt Position */
+#define DEVEPTISR_CTRL_NAKINI         (_U_(0x1) << DEVEPTISR_CTRL_NAKINI_Pos)  /**< (DEVEPTISR) NAKed IN Interrupt Mask */
+#define DEVEPTISR_CTRL_STALLEDI_Pos   6                                              /**< (DEVEPTISR) STALLed Interrupt Position */
+#define DEVEPTISR_CTRL_STALLEDI       (_U_(0x1) << DEVEPTISR_CTRL_STALLEDI_Pos)  /**< (DEVEPTISR) STALLed Interrupt Mask */
+#define DEVEPTISR_CTRL_CTRLDIR_Pos    17                                             /**< (DEVEPTISR) Control Direction Position */
+#define DEVEPTISR_CTRL_CTRLDIR        (_U_(0x1) << DEVEPTISR_CTRL_CTRLDIR_Pos)  /**< (DEVEPTISR) Control Direction Mask */
+#define DEVEPTISR_CTRL_Msk            _U_(0x2005C)                                   /**< (DEVEPTISR_CTRL) Register Mask  */
+
+/* ISO mode */
+#define DEVEPTISR_ISO_UNDERFI_Pos     2                                              /**< (DEVEPTISR) Underflow Interrupt Position */
+#define DEVEPTISR_ISO_UNDERFI         (_U_(0x1) << DEVEPTISR_ISO_UNDERFI_Pos)  /**< (DEVEPTISR) Underflow Interrupt Mask */
+#define DEVEPTISR_ISO_HBISOINERRI_Pos 3                                              /**< (DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */
+#define DEVEPTISR_ISO_HBISOINERRI     (_U_(0x1) << DEVEPTISR_ISO_HBISOINERRI_Pos)  /**< (DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */
+#define DEVEPTISR_ISO_HBISOFLUSHI_Pos 4                                              /**< (DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Position */
+#define DEVEPTISR_ISO_HBISOFLUSHI     (_U_(0x1) << DEVEPTISR_ISO_HBISOFLUSHI_Pos)  /**< (DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Mask */
+#define DEVEPTISR_ISO_CRCERRI_Pos     6                                              /**< (DEVEPTISR) CRC Error Interrupt Position */
+#define DEVEPTISR_ISO_CRCERRI         (_U_(0x1) << DEVEPTISR_ISO_CRCERRI_Pos)  /**< (DEVEPTISR) CRC Error Interrupt Mask */
+#define DEVEPTISR_ISO_ERRORTRANS_Pos  10                                             /**< (DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Position */
+#define DEVEPTISR_ISO_ERRORTRANS      (_U_(0x1) << DEVEPTISR_ISO_ERRORTRANS_Pos)  /**< (DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Mask */
+#define DEVEPTISR_ISO_Msk             _U_(0x45C)                                     /**< (DEVEPTISR_ISO) Register Mask  */
+
+/* BLK mode */
+#define DEVEPTISR_BLK_RXSTPI_Pos      2                                              /**< (DEVEPTISR) Received SETUP Interrupt Position */
+#define DEVEPTISR_BLK_RXSTPI          (_U_(0x1) << DEVEPTISR_BLK_RXSTPI_Pos)   /**< (DEVEPTISR) Received SETUP Interrupt Mask */
+#define DEVEPTISR_BLK_NAKOUTI_Pos     3                                              /**< (DEVEPTISR) NAKed OUT Interrupt Position */
+#define DEVEPTISR_BLK_NAKOUTI         (_U_(0x1) << DEVEPTISR_BLK_NAKOUTI_Pos)  /**< (DEVEPTISR) NAKed OUT Interrupt Mask */
+#define DEVEPTISR_BLK_NAKINI_Pos      4                                              /**< (DEVEPTISR) NAKed IN Interrupt Position */
+#define DEVEPTISR_BLK_NAKINI          (_U_(0x1) << DEVEPTISR_BLK_NAKINI_Pos)   /**< (DEVEPTISR) NAKed IN Interrupt Mask */
+#define DEVEPTISR_BLK_STALLEDI_Pos    6                                              /**< (DEVEPTISR) STALLed Interrupt Position */
+#define DEVEPTISR_BLK_STALLEDI        (_U_(0x1) << DEVEPTISR_BLK_STALLEDI_Pos)  /**< (DEVEPTISR) STALLed Interrupt Mask */
+#define DEVEPTISR_BLK_CTRLDIR_Pos     17                                             /**< (DEVEPTISR) Control Direction Position */
+#define DEVEPTISR_BLK_CTRLDIR         (_U_(0x1) << DEVEPTISR_BLK_CTRLDIR_Pos)  /**< (DEVEPTISR) Control Direction Mask */
+#define DEVEPTISR_BLK_Msk             _U_(0x2005C)                                   /**< (DEVEPTISR_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define DEVEPTISR_INTRPT_RXSTPI_Pos   2                                              /**< (DEVEPTISR) Received SETUP Interrupt Position */
+#define DEVEPTISR_INTRPT_RXSTPI       (_U_(0x1) << DEVEPTISR_INTRPT_RXSTPI_Pos)  /**< (DEVEPTISR) Received SETUP Interrupt Mask */
+#define DEVEPTISR_INTRPT_NAKOUTI_Pos  3                                              /**< (DEVEPTISR) NAKed OUT Interrupt Position */
+#define DEVEPTISR_INTRPT_NAKOUTI      (_U_(0x1) << DEVEPTISR_INTRPT_NAKOUTI_Pos)  /**< (DEVEPTISR) NAKed OUT Interrupt Mask */
+#define DEVEPTISR_INTRPT_NAKINI_Pos   4                                              /**< (DEVEPTISR) NAKed IN Interrupt Position */
+#define DEVEPTISR_INTRPT_NAKINI       (_U_(0x1) << DEVEPTISR_INTRPT_NAKINI_Pos)  /**< (DEVEPTISR) NAKed IN Interrupt Mask */
+#define DEVEPTISR_INTRPT_STALLEDI_Pos 6                                              /**< (DEVEPTISR) STALLed Interrupt Position */
+#define DEVEPTISR_INTRPT_STALLEDI     (_U_(0x1) << DEVEPTISR_INTRPT_STALLEDI_Pos)  /**< (DEVEPTISR) STALLed Interrupt Mask */
+#define DEVEPTISR_INTRPT_CTRLDIR_Pos  17                                             /**< (DEVEPTISR) Control Direction Position */
+#define DEVEPTISR_INTRPT_CTRLDIR      (_U_(0x1) << DEVEPTISR_INTRPT_CTRLDIR_Pos)  /**< (DEVEPTISR) Control Direction Mask */
+#define DEVEPTISR_INTRPT_Msk          _U_(0x2005C)                                   /**< (DEVEPTISR_INTRPT) Register Mask  */
+
+
+/* -------- DEVEPTICR : (USBHS Offset: 0x160) (/W 32) Device Endpoint Interrupt Clear Register -------- */
+
+#define DEVEPTICR_OFFSET              (0x160)                                       /**<  (DEVEPTICR) Device Endpoint Interrupt Clear Register  Offset */
+
+#define DEVEPTICR_TXINIC_Pos          0                                              /**< (DEVEPTICR) Transmitted IN Data Interrupt Clear Position */
+#define DEVEPTICR_TXINIC              (_U_(0x1) << DEVEPTICR_TXINIC_Pos)       /**< (DEVEPTICR) Transmitted IN Data Interrupt Clear Mask */
+#define DEVEPTICR_RXOUTIC_Pos         1                                              /**< (DEVEPTICR) Received OUT Data Interrupt Clear Position */
+#define DEVEPTICR_RXOUTIC             (_U_(0x1) << DEVEPTICR_RXOUTIC_Pos)      /**< (DEVEPTICR) Received OUT Data Interrupt Clear Mask */
+#define DEVEPTICR_OVERFIC_Pos         5                                              /**< (DEVEPTICR) Overflow Interrupt Clear Position */
+#define DEVEPTICR_OVERFIC             (_U_(0x1) << DEVEPTICR_OVERFIC_Pos)      /**< (DEVEPTICR) Overflow Interrupt Clear Mask */
+#define DEVEPTICR_SHORTPACKETC_Pos    7                                              /**< (DEVEPTICR) Short Packet Interrupt Clear Position */
+#define DEVEPTICR_SHORTPACKETC        (_U_(0x1) << DEVEPTICR_SHORTPACKETC_Pos)  /**< (DEVEPTICR) Short Packet Interrupt Clear Mask */
+#define DEVEPTICR_Msk                 _U_(0xA3)                                      /**< (DEVEPTICR) Register Mask  */
+
+/* CTRL mode */
+#define DEVEPTICR_CTRL_RXSTPIC_Pos    2                                              /**< (DEVEPTICR) Received SETUP Interrupt Clear Position */
+#define DEVEPTICR_CTRL_RXSTPIC        (_U_(0x1) << DEVEPTICR_CTRL_RXSTPIC_Pos)  /**< (DEVEPTICR) Received SETUP Interrupt Clear Mask */
+#define DEVEPTICR_CTRL_NAKOUTIC_Pos   3                                              /**< (DEVEPTICR) NAKed OUT Interrupt Clear Position */
+#define DEVEPTICR_CTRL_NAKOUTIC       (_U_(0x1) << DEVEPTICR_CTRL_NAKOUTIC_Pos)  /**< (DEVEPTICR) NAKed OUT Interrupt Clear Mask */
+#define DEVEPTICR_CTRL_NAKINIC_Pos    4                                              /**< (DEVEPTICR) NAKed IN Interrupt Clear Position */
+#define DEVEPTICR_CTRL_NAKINIC        (_U_(0x1) << DEVEPTICR_CTRL_NAKINIC_Pos)  /**< (DEVEPTICR) NAKed IN Interrupt Clear Mask */
+#define DEVEPTICR_CTRL_STALLEDIC_Pos  6                                              /**< (DEVEPTICR) STALLed Interrupt Clear Position */
+#define DEVEPTICR_CTRL_STALLEDIC      (_U_(0x1) << DEVEPTICR_CTRL_STALLEDIC_Pos)  /**< (DEVEPTICR) STALLed Interrupt Clear Mask */
+#define DEVEPTICR_CTRL_Msk            _U_(0x5C)                                      /**< (DEVEPTICR_CTRL) Register Mask  */
+
+/* ISO mode */
+#define DEVEPTICR_ISO_UNDERFIC_Pos    2                                              /**< (DEVEPTICR) Underflow Interrupt Clear Position */
+#define DEVEPTICR_ISO_UNDERFIC        (_U_(0x1) << DEVEPTICR_ISO_UNDERFIC_Pos)  /**< (DEVEPTICR) Underflow Interrupt Clear Mask */
+#define DEVEPTICR_ISO_HBISOINERRIC_Pos 3                                              /**< (DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */
+#define DEVEPTICR_ISO_HBISOINERRIC     (_U_(0x1) << DEVEPTICR_ISO_HBISOINERRIC_Pos)  /**< (DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */
+#define DEVEPTICR_ISO_HBISOFLUSHIC_Pos 4                                              /**< (DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */
+#define DEVEPTICR_ISO_HBISOFLUSHIC     (_U_(0x1) << DEVEPTICR_ISO_HBISOFLUSHIC_Pos)  /**< (DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */
+#define DEVEPTICR_ISO_CRCERRIC_Pos    6                                              /**< (DEVEPTICR) CRC Error Interrupt Clear Position */
+#define DEVEPTICR_ISO_CRCERRIC        (_U_(0x1) << DEVEPTICR_ISO_CRCERRIC_Pos)  /**< (DEVEPTICR) CRC Error Interrupt Clear Mask */
+#define DEVEPTICR_ISO_Msk             _U_(0x5C)                                      /**< (DEVEPTICR_ISO) Register Mask  */
+
+/* BLK mode */
+#define DEVEPTICR_BLK_RXSTPIC_Pos     2                                              /**< (DEVEPTICR) Received SETUP Interrupt Clear Position */
+#define DEVEPTICR_BLK_RXSTPIC         (_U_(0x1) << DEVEPTICR_BLK_RXSTPIC_Pos)  /**< (DEVEPTICR) Received SETUP Interrupt Clear Mask */
+#define DEVEPTICR_BLK_NAKOUTIC_Pos    3                                              /**< (DEVEPTICR) NAKed OUT Interrupt Clear Position */
+#define DEVEPTICR_BLK_NAKOUTIC        (_U_(0x1) << DEVEPTICR_BLK_NAKOUTIC_Pos)  /**< (DEVEPTICR) NAKed OUT Interrupt Clear Mask */
+#define DEVEPTICR_BLK_NAKINIC_Pos     4                                              /**< (DEVEPTICR) NAKed IN Interrupt Clear Position */
+#define DEVEPTICR_BLK_NAKINIC         (_U_(0x1) << DEVEPTICR_BLK_NAKINIC_Pos)  /**< (DEVEPTICR) NAKed IN Interrupt Clear Mask */
+#define DEVEPTICR_BLK_STALLEDIC_Pos   6                                              /**< (DEVEPTICR) STALLed Interrupt Clear Position */
+#define DEVEPTICR_BLK_STALLEDIC       (_U_(0x1) << DEVEPTICR_BLK_STALLEDIC_Pos)  /**< (DEVEPTICR) STALLed Interrupt Clear Mask */
+#define DEVEPTICR_BLK_Msk             _U_(0x5C)                                      /**< (DEVEPTICR_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define DEVEPTICR_INTRPT_RXSTPIC_Pos  2                                              /**< (DEVEPTICR) Received SETUP Interrupt Clear Position */
+#define DEVEPTICR_INTRPT_RXSTPIC      (_U_(0x1) << DEVEPTICR_INTRPT_RXSTPIC_Pos)  /**< (DEVEPTICR) Received SETUP Interrupt Clear Mask */
+#define DEVEPTICR_INTRPT_NAKOUTIC_Pos 3                                              /**< (DEVEPTICR) NAKed OUT Interrupt Clear Position */
+#define DEVEPTICR_INTRPT_NAKOUTIC     (_U_(0x1) << DEVEPTICR_INTRPT_NAKOUTIC_Pos)  /**< (DEVEPTICR) NAKed OUT Interrupt Clear Mask */
+#define DEVEPTICR_INTRPT_NAKINIC_Pos  4                                              /**< (DEVEPTICR) NAKed IN Interrupt Clear Position */
+#define DEVEPTICR_INTRPT_NAKINIC      (_U_(0x1) << DEVEPTICR_INTRPT_NAKINIC_Pos)  /**< (DEVEPTICR) NAKed IN Interrupt Clear Mask */
+#define DEVEPTICR_INTRPT_STALLEDIC_Pos 6                                              /**< (DEVEPTICR) STALLed Interrupt Clear Position */
+#define DEVEPTICR_INTRPT_STALLEDIC     (_U_(0x1) << DEVEPTICR_INTRPT_STALLEDIC_Pos)  /**< (DEVEPTICR) STALLed Interrupt Clear Mask */
+#define DEVEPTICR_INTRPT_Msk          _U_(0x5C)                                      /**< (DEVEPTICR_INTRPT) Register Mask  */
+
+
+/* -------- DEVEPTIFR : (USBHS Offset: 0x190) (/W 32) Device Endpoint Interrupt Set Register -------- */
+
+#define DEVEPTIFR_OFFSET              (0x190)                                       /**<  (DEVEPTIFR) Device Endpoint Interrupt Set Register  Offset */
+
+#define DEVEPTIFR_TXINIS_Pos          0                                              /**< (DEVEPTIFR) Transmitted IN Data Interrupt Set Position */
+#define DEVEPTIFR_TXINIS              (_U_(0x1) << DEVEPTIFR_TXINIS_Pos)       /**< (DEVEPTIFR) Transmitted IN Data Interrupt Set Mask */
+#define DEVEPTIFR_RXOUTIS_Pos         1                                              /**< (DEVEPTIFR) Received OUT Data Interrupt Set Position */
+#define DEVEPTIFR_RXOUTIS             (_U_(0x1) << DEVEPTIFR_RXOUTIS_Pos)      /**< (DEVEPTIFR) Received OUT Data Interrupt Set Mask */
+#define DEVEPTIFR_OVERFIS_Pos         5                                              /**< (DEVEPTIFR) Overflow Interrupt Set Position */
+#define DEVEPTIFR_OVERFIS             (_U_(0x1) << DEVEPTIFR_OVERFIS_Pos)      /**< (DEVEPTIFR) Overflow Interrupt Set Mask */
+#define DEVEPTIFR_SHORTPACKETS_Pos    7                                              /**< (DEVEPTIFR) Short Packet Interrupt Set Position */
+#define DEVEPTIFR_SHORTPACKETS        (_U_(0x1) << DEVEPTIFR_SHORTPACKETS_Pos)  /**< (DEVEPTIFR) Short Packet Interrupt Set Mask */
+#define DEVEPTIFR_NBUSYBKS_Pos        12                                             /**< (DEVEPTIFR) Number of Busy Banks Interrupt Set Position */
+#define DEVEPTIFR_NBUSYBKS            (_U_(0x1) << DEVEPTIFR_NBUSYBKS_Pos)     /**< (DEVEPTIFR) Number of Busy Banks Interrupt Set Mask */
+#define DEVEPTIFR_Msk                 _U_(0x10A3)                                    /**< (DEVEPTIFR) Register Mask  */
+
+/* CTRL mode */
+#define DEVEPTIFR_CTRL_RXSTPIS_Pos    2                                              /**< (DEVEPTIFR) Received SETUP Interrupt Set Position */
+#define DEVEPTIFR_CTRL_RXSTPIS        (_U_(0x1) << DEVEPTIFR_CTRL_RXSTPIS_Pos)  /**< (DEVEPTIFR) Received SETUP Interrupt Set Mask */
+#define DEVEPTIFR_CTRL_NAKOUTIS_Pos   3                                              /**< (DEVEPTIFR) NAKed OUT Interrupt Set Position */
+#define DEVEPTIFR_CTRL_NAKOUTIS       (_U_(0x1) << DEVEPTIFR_CTRL_NAKOUTIS_Pos)  /**< (DEVEPTIFR) NAKed OUT Interrupt Set Mask */
+#define DEVEPTIFR_CTRL_NAKINIS_Pos    4                                              /**< (DEVEPTIFR) NAKed IN Interrupt Set Position */
+#define DEVEPTIFR_CTRL_NAKINIS        (_U_(0x1) << DEVEPTIFR_CTRL_NAKINIS_Pos)  /**< (DEVEPTIFR) NAKed IN Interrupt Set Mask */
+#define DEVEPTIFR_CTRL_STALLEDIS_Pos  6                                              /**< (DEVEPTIFR) STALLed Interrupt Set Position */
+#define DEVEPTIFR_CTRL_STALLEDIS      (_U_(0x1) << DEVEPTIFR_CTRL_STALLEDIS_Pos)  /**< (DEVEPTIFR) STALLed Interrupt Set Mask */
+#define DEVEPTIFR_CTRL_Msk            _U_(0x5C)                                      /**< (DEVEPTIFR_CTRL) Register Mask  */
+
+/* ISO mode */
+#define DEVEPTIFR_ISO_UNDERFIS_Pos    2                                              /**< (DEVEPTIFR) Underflow Interrupt Set Position */
+#define DEVEPTIFR_ISO_UNDERFIS        (_U_(0x1) << DEVEPTIFR_ISO_UNDERFIS_Pos)  /**< (DEVEPTIFR) Underflow Interrupt Set Mask */
+#define DEVEPTIFR_ISO_HBISOINERRIS_Pos 3                                              /**< (DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Position */
+#define DEVEPTIFR_ISO_HBISOINERRIS     (_U_(0x1) << DEVEPTIFR_ISO_HBISOINERRIS_Pos)  /**< (DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Mask */
+#define DEVEPTIFR_ISO_HBISOFLUSHIS_Pos 4                                              /**< (DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Position */
+#define DEVEPTIFR_ISO_HBISOFLUSHIS     (_U_(0x1) << DEVEPTIFR_ISO_HBISOFLUSHIS_Pos)  /**< (DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Mask */
+#define DEVEPTIFR_ISO_CRCERRIS_Pos    6                                              /**< (DEVEPTIFR) CRC Error Interrupt Set Position */
+#define DEVEPTIFR_ISO_CRCERRIS        (_U_(0x1) << DEVEPTIFR_ISO_CRCERRIS_Pos)  /**< (DEVEPTIFR) CRC Error Interrupt Set Mask */
+#define DEVEPTIFR_ISO_Msk             _U_(0x5C)                                      /**< (DEVEPTIFR_ISO) Register Mask  */
+
+/* BLK mode */
+#define DEVEPTIFR_BLK_RXSTPIS_Pos     2                                              /**< (DEVEPTIFR) Received SETUP Interrupt Set Position */
+#define DEVEPTIFR_BLK_RXSTPIS         (_U_(0x1) << DEVEPTIFR_BLK_RXSTPIS_Pos)  /**< (DEVEPTIFR) Received SETUP Interrupt Set Mask */
+#define DEVEPTIFR_BLK_NAKOUTIS_Pos    3                                              /**< (DEVEPTIFR) NAKed OUT Interrupt Set Position */
+#define DEVEPTIFR_BLK_NAKOUTIS        (_U_(0x1) << DEVEPTIFR_BLK_NAKOUTIS_Pos)  /**< (DEVEPTIFR) NAKed OUT Interrupt Set Mask */
+#define DEVEPTIFR_BLK_NAKINIS_Pos     4                                              /**< (DEVEPTIFR) NAKed IN Interrupt Set Position */
+#define DEVEPTIFR_BLK_NAKINIS         (_U_(0x1) << DEVEPTIFR_BLK_NAKINIS_Pos)  /**< (DEVEPTIFR) NAKed IN Interrupt Set Mask */
+#define DEVEPTIFR_BLK_STALLEDIS_Pos   6                                              /**< (DEVEPTIFR) STALLed Interrupt Set Position */
+#define DEVEPTIFR_BLK_STALLEDIS       (_U_(0x1) << DEVEPTIFR_BLK_STALLEDIS_Pos)  /**< (DEVEPTIFR) STALLed Interrupt Set Mask */
+#define DEVEPTIFR_BLK_Msk             _U_(0x5C)                                      /**< (DEVEPTIFR_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define DEVEPTIFR_INTRPT_RXSTPIS_Pos  2                                              /**< (DEVEPTIFR) Received SETUP Interrupt Set Position */
+#define DEVEPTIFR_INTRPT_RXSTPIS      (_U_(0x1) << DEVEPTIFR_INTRPT_RXSTPIS_Pos)  /**< (DEVEPTIFR) Received SETUP Interrupt Set Mask */
+#define DEVEPTIFR_INTRPT_NAKOUTIS_Pos 3                                              /**< (DEVEPTIFR) NAKed OUT Interrupt Set Position */
+#define DEVEPTIFR_INTRPT_NAKOUTIS     (_U_(0x1) << DEVEPTIFR_INTRPT_NAKOUTIS_Pos)  /**< (DEVEPTIFR) NAKed OUT Interrupt Set Mask */
+#define DEVEPTIFR_INTRPT_NAKINIS_Pos  4                                              /**< (DEVEPTIFR) NAKed IN Interrupt Set Position */
+#define DEVEPTIFR_INTRPT_NAKINIS      (_U_(0x1) << DEVEPTIFR_INTRPT_NAKINIS_Pos)  /**< (DEVEPTIFR) NAKed IN Interrupt Set Mask */
+#define DEVEPTIFR_INTRPT_STALLEDIS_Pos 6                                              /**< (DEVEPTIFR) STALLed Interrupt Set Position */
+#define DEVEPTIFR_INTRPT_STALLEDIS     (_U_(0x1) << DEVEPTIFR_INTRPT_STALLEDIS_Pos)  /**< (DEVEPTIFR) STALLed Interrupt Set Mask */
+#define DEVEPTIFR_INTRPT_Msk          _U_(0x5C)                                      /**< (DEVEPTIFR_INTRPT) Register Mask  */
+
+
+/* -------- DEVEPTIMR : (USBHS Offset: 0x1c0) (R/ 32) Device Endpoint Interrupt Mask Register -------- */
+
+#define DEVEPTIMR_OFFSET              (0x1C0)                                       /**<  (DEVEPTIMR) Device Endpoint Interrupt Mask Register  Offset */
+
+#define DEVEPTIMR_TXINE_Pos           0                                              /**< (DEVEPTIMR) Transmitted IN Data Interrupt Position */
+#define DEVEPTIMR_TXINE               (_U_(0x1) << DEVEPTIMR_TXINE_Pos)        /**< (DEVEPTIMR) Transmitted IN Data Interrupt Mask */
+#define DEVEPTIMR_RXOUTE_Pos          1                                              /**< (DEVEPTIMR) Received OUT Data Interrupt Position */
+#define DEVEPTIMR_RXOUTE              (_U_(0x1) << DEVEPTIMR_RXOUTE_Pos)       /**< (DEVEPTIMR) Received OUT Data Interrupt Mask */
+#define DEVEPTIMR_OVERFE_Pos          5                                              /**< (DEVEPTIMR) Overflow Interrupt Position */
+#define DEVEPTIMR_OVERFE              (_U_(0x1) << DEVEPTIMR_OVERFE_Pos)       /**< (DEVEPTIMR) Overflow Interrupt Mask */
+#define DEVEPTIMR_SHORTPACKETE_Pos    7                                              /**< (DEVEPTIMR) Short Packet Interrupt Position */
+#define DEVEPTIMR_SHORTPACKETE        (_U_(0x1) << DEVEPTIMR_SHORTPACKETE_Pos)  /**< (DEVEPTIMR) Short Packet Interrupt Mask */
+#define DEVEPTIMR_NBUSYBKE_Pos        12                                             /**< (DEVEPTIMR) Number of Busy Banks Interrupt Position */
+#define DEVEPTIMR_NBUSYBKE            (_U_(0x1) << DEVEPTIMR_NBUSYBKE_Pos)     /**< (DEVEPTIMR) Number of Busy Banks Interrupt Mask */
+#define DEVEPTIMR_KILLBK_Pos          13                                             /**< (DEVEPTIMR) Kill IN Bank Position */
+#define DEVEPTIMR_KILLBK              (_U_(0x1) << DEVEPTIMR_KILLBK_Pos)       /**< (DEVEPTIMR) Kill IN Bank Mask */
+#define DEVEPTIMR_FIFOCON_Pos         14                                             /**< (DEVEPTIMR) FIFO Control Position */
+#define DEVEPTIMR_FIFOCON             (_U_(0x1) << DEVEPTIMR_FIFOCON_Pos)      /**< (DEVEPTIMR) FIFO Control Mask */
+#define DEVEPTIMR_EPDISHDMA_Pos       16                                             /**< (DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Position */
+#define DEVEPTIMR_EPDISHDMA           (_U_(0x1) << DEVEPTIMR_EPDISHDMA_Pos)    /**< (DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Mask */
+#define DEVEPTIMR_RSTDT_Pos           18                                             /**< (DEVEPTIMR) Reset Data Toggle Position */
+#define DEVEPTIMR_RSTDT               (_U_(0x1) << DEVEPTIMR_RSTDT_Pos)        /**< (DEVEPTIMR) Reset Data Toggle Mask */
+#define DEVEPTIMR_Msk                 _U_(0x570A3)                                   /**< (DEVEPTIMR) Register Mask  */
+
+/* CTRL mode */
+#define DEVEPTIMR_CTRL_RXSTPE_Pos     2                                              /**< (DEVEPTIMR) Received SETUP Interrupt Position */
+#define DEVEPTIMR_CTRL_RXSTPE         (_U_(0x1) << DEVEPTIMR_CTRL_RXSTPE_Pos)  /**< (DEVEPTIMR) Received SETUP Interrupt Mask */
+#define DEVEPTIMR_CTRL_NAKOUTE_Pos    3                                              /**< (DEVEPTIMR) NAKed OUT Interrupt Position */
+#define DEVEPTIMR_CTRL_NAKOUTE        (_U_(0x1) << DEVEPTIMR_CTRL_NAKOUTE_Pos)  /**< (DEVEPTIMR) NAKed OUT Interrupt Mask */
+#define DEVEPTIMR_CTRL_NAKINE_Pos     4                                              /**< (DEVEPTIMR) NAKed IN Interrupt Position */
+#define DEVEPTIMR_CTRL_NAKINE         (_U_(0x1) << DEVEPTIMR_CTRL_NAKINE_Pos)  /**< (DEVEPTIMR) NAKed IN Interrupt Mask */
+#define DEVEPTIMR_CTRL_STALLEDE_Pos   6                                              /**< (DEVEPTIMR) STALLed Interrupt Position */
+#define DEVEPTIMR_CTRL_STALLEDE       (_U_(0x1) << DEVEPTIMR_CTRL_STALLEDE_Pos)  /**< (DEVEPTIMR) STALLed Interrupt Mask */
+#define DEVEPTIMR_CTRL_NYETDIS_Pos    17                                             /**< (DEVEPTIMR) NYET Token Disable Position */
+#define DEVEPTIMR_CTRL_NYETDIS        (_U_(0x1) << DEVEPTIMR_CTRL_NYETDIS_Pos)  /**< (DEVEPTIMR) NYET Token Disable Mask */
+#define DEVEPTIMR_CTRL_STALLRQ_Pos    19                                             /**< (DEVEPTIMR) STALL Request Position */
+#define DEVEPTIMR_CTRL_STALLRQ        (_U_(0x1) << DEVEPTIMR_CTRL_STALLRQ_Pos)  /**< (DEVEPTIMR) STALL Request Mask */
+#define DEVEPTIMR_CTRL_Msk            _U_(0xA005C)                                   /**< (DEVEPTIMR_CTRL) Register Mask  */
+
+/* ISO mode */
+#define DEVEPTIMR_ISO_UNDERFE_Pos     2                                              /**< (DEVEPTIMR) Underflow Interrupt Position */
+#define DEVEPTIMR_ISO_UNDERFE         (_U_(0x1) << DEVEPTIMR_ISO_UNDERFE_Pos)  /**< (DEVEPTIMR) Underflow Interrupt Mask */
+#define DEVEPTIMR_ISO_HBISOINERRE_Pos 3                                              /**< (DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */
+#define DEVEPTIMR_ISO_HBISOINERRE     (_U_(0x1) << DEVEPTIMR_ISO_HBISOINERRE_Pos)  /**< (DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */
+#define DEVEPTIMR_ISO_HBISOFLUSHE_Pos 4                                              /**< (DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Position */
+#define DEVEPTIMR_ISO_HBISOFLUSHE     (_U_(0x1) << DEVEPTIMR_ISO_HBISOFLUSHE_Pos)  /**< (DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Mask */
+#define DEVEPTIMR_ISO_CRCERRE_Pos     6                                              /**< (DEVEPTIMR) CRC Error Interrupt Position */
+#define DEVEPTIMR_ISO_CRCERRE         (_U_(0x1) << DEVEPTIMR_ISO_CRCERRE_Pos)  /**< (DEVEPTIMR) CRC Error Interrupt Mask */
+#define DEVEPTIMR_ISO_MDATAE_Pos      8                                              /**< (DEVEPTIMR) MData Interrupt Position */
+#define DEVEPTIMR_ISO_MDATAE          (_U_(0x1) << DEVEPTIMR_ISO_MDATAE_Pos)   /**< (DEVEPTIMR) MData Interrupt Mask */
+#define DEVEPTIMR_ISO_DATAXE_Pos      9                                              /**< (DEVEPTIMR) DataX Interrupt Position */
+#define DEVEPTIMR_ISO_DATAXE          (_U_(0x1) << DEVEPTIMR_ISO_DATAXE_Pos)   /**< (DEVEPTIMR) DataX Interrupt Mask */
+#define DEVEPTIMR_ISO_ERRORTRANSE_Pos 10                                             /**< (DEVEPTIMR) Transaction Error Interrupt Position */
+#define DEVEPTIMR_ISO_ERRORTRANSE     (_U_(0x1) << DEVEPTIMR_ISO_ERRORTRANSE_Pos)  /**< (DEVEPTIMR) Transaction Error Interrupt Mask */
+#define DEVEPTIMR_ISO_Msk             _U_(0x75C)                                     /**< (DEVEPTIMR_ISO) Register Mask  */
+
+/* BLK mode */
+#define DEVEPTIMR_BLK_RXSTPE_Pos      2                                              /**< (DEVEPTIMR) Received SETUP Interrupt Position */
+#define DEVEPTIMR_BLK_RXSTPE          (_U_(0x1) << DEVEPTIMR_BLK_RXSTPE_Pos)   /**< (DEVEPTIMR) Received SETUP Interrupt Mask */
+#define DEVEPTIMR_BLK_NAKOUTE_Pos     3                                              /**< (DEVEPTIMR) NAKed OUT Interrupt Position */
+#define DEVEPTIMR_BLK_NAKOUTE         (_U_(0x1) << DEVEPTIMR_BLK_NAKOUTE_Pos)  /**< (DEVEPTIMR) NAKed OUT Interrupt Mask */
+#define DEVEPTIMR_BLK_NAKINE_Pos      4                                              /**< (DEVEPTIMR) NAKed IN Interrupt Position */
+#define DEVEPTIMR_BLK_NAKINE          (_U_(0x1) << DEVEPTIMR_BLK_NAKINE_Pos)   /**< (DEVEPTIMR) NAKed IN Interrupt Mask */
+#define DEVEPTIMR_BLK_STALLEDE_Pos    6                                              /**< (DEVEPTIMR) STALLed Interrupt Position */
+#define DEVEPTIMR_BLK_STALLEDE        (_U_(0x1) << DEVEPTIMR_BLK_STALLEDE_Pos)  /**< (DEVEPTIMR) STALLed Interrupt Mask */
+#define DEVEPTIMR_BLK_NYETDIS_Pos     17                                             /**< (DEVEPTIMR) NYET Token Disable Position */
+#define DEVEPTIMR_BLK_NYETDIS         (_U_(0x1) << DEVEPTIMR_BLK_NYETDIS_Pos)  /**< (DEVEPTIMR) NYET Token Disable Mask */
+#define DEVEPTIMR_BLK_STALLRQ_Pos     19                                             /**< (DEVEPTIMR) STALL Request Position */
+#define DEVEPTIMR_BLK_STALLRQ         (_U_(0x1) << DEVEPTIMR_BLK_STALLRQ_Pos)  /**< (DEVEPTIMR) STALL Request Mask */
+#define DEVEPTIMR_BLK_Msk             _U_(0xA005C)                                   /**< (DEVEPTIMR_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define DEVEPTIMR_INTRPT_RXSTPE_Pos   2                                              /**< (DEVEPTIMR) Received SETUP Interrupt Position */
+#define DEVEPTIMR_INTRPT_RXSTPE       (_U_(0x1) << DEVEPTIMR_INTRPT_RXSTPE_Pos)  /**< (DEVEPTIMR) Received SETUP Interrupt Mask */
+#define DEVEPTIMR_INTRPT_NAKOUTE_Pos  3                                              /**< (DEVEPTIMR) NAKed OUT Interrupt Position */
+#define DEVEPTIMR_INTRPT_NAKOUTE      (_U_(0x1) << DEVEPTIMR_INTRPT_NAKOUTE_Pos)  /**< (DEVEPTIMR) NAKed OUT Interrupt Mask */
+#define DEVEPTIMR_INTRPT_NAKINE_Pos   4                                              /**< (DEVEPTIMR) NAKed IN Interrupt Position */
+#define DEVEPTIMR_INTRPT_NAKINE       (_U_(0x1) << DEVEPTIMR_INTRPT_NAKINE_Pos)  /**< (DEVEPTIMR) NAKed IN Interrupt Mask */
+#define DEVEPTIMR_INTRPT_STALLEDE_Pos 6                                              /**< (DEVEPTIMR) STALLed Interrupt Position */
+#define DEVEPTIMR_INTRPT_STALLEDE     (_U_(0x1) << DEVEPTIMR_INTRPT_STALLEDE_Pos)  /**< (DEVEPTIMR) STALLed Interrupt Mask */
+#define DEVEPTIMR_INTRPT_NYETDIS_Pos  17                                             /**< (DEVEPTIMR) NYET Token Disable Position */
+#define DEVEPTIMR_INTRPT_NYETDIS      (_U_(0x1) << DEVEPTIMR_INTRPT_NYETDIS_Pos)  /**< (DEVEPTIMR) NYET Token Disable Mask */
+#define DEVEPTIMR_INTRPT_STALLRQ_Pos  19                                             /**< (DEVEPTIMR) STALL Request Position */
+#define DEVEPTIMR_INTRPT_STALLRQ      (_U_(0x1) << DEVEPTIMR_INTRPT_STALLRQ_Pos)  /**< (DEVEPTIMR) STALL Request Mask */
+#define DEVEPTIMR_INTRPT_Msk          _U_(0xA005C)                                   /**< (DEVEPTIMR_INTRPT) Register Mask  */
+
+
+/* -------- DEVEPTIER : (USBHS Offset: 0x1f0) (/W 32) Device Endpoint Interrupt Enable Register -------- */
+
+#define DEVEPTIER_OFFSET              (0x1F0)                                       /**<  (DEVEPTIER) Device Endpoint Interrupt Enable Register  Offset */
+
+#define DEVEPTIER_TXINES_Pos          0                                              /**< (DEVEPTIER) Transmitted IN Data Interrupt Enable Position */
+#define DEVEPTIER_TXINES              (_U_(0x1) << DEVEPTIER_TXINES_Pos)       /**< (DEVEPTIER) Transmitted IN Data Interrupt Enable Mask */
+#define DEVEPTIER_RXOUTES_Pos         1                                              /**< (DEVEPTIER) Received OUT Data Interrupt Enable Position */
+#define DEVEPTIER_RXOUTES             (_U_(0x1) << DEVEPTIER_RXOUTES_Pos)      /**< (DEVEPTIER) Received OUT Data Interrupt Enable Mask */
+#define DEVEPTIER_OVERFES_Pos         5                                              /**< (DEVEPTIER) Overflow Interrupt Enable Position */
+#define DEVEPTIER_OVERFES             (_U_(0x1) << DEVEPTIER_OVERFES_Pos)      /**< (DEVEPTIER) Overflow Interrupt Enable Mask */
+#define DEVEPTIER_SHORTPACKETES_Pos   7                                              /**< (DEVEPTIER) Short Packet Interrupt Enable Position */
+#define DEVEPTIER_SHORTPACKETES       (_U_(0x1) << DEVEPTIER_SHORTPACKETES_Pos)  /**< (DEVEPTIER) Short Packet Interrupt Enable Mask */
+#define DEVEPTIER_NBUSYBKES_Pos       12                                             /**< (DEVEPTIER) Number of Busy Banks Interrupt Enable Position */
+#define DEVEPTIER_NBUSYBKES           (_U_(0x1) << DEVEPTIER_NBUSYBKES_Pos)    /**< (DEVEPTIER) Number of Busy Banks Interrupt Enable Mask */
+#define DEVEPTIER_KILLBKS_Pos         13                                             /**< (DEVEPTIER) Kill IN Bank Position */
+#define DEVEPTIER_KILLBKS             (_U_(0x1) << DEVEPTIER_KILLBKS_Pos)      /**< (DEVEPTIER) Kill IN Bank Mask */
+#define DEVEPTIER_FIFOCONS_Pos        14                                             /**< (DEVEPTIER) FIFO Control Position */
+#define DEVEPTIER_FIFOCONS            (_U_(0x1) << DEVEPTIER_FIFOCONS_Pos)     /**< (DEVEPTIER) FIFO Control Mask */
+#define DEVEPTIER_EPDISHDMAS_Pos      16                                             /**< (DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Position */
+#define DEVEPTIER_EPDISHDMAS          (_U_(0x1) << DEVEPTIER_EPDISHDMAS_Pos)   /**< (DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Mask */
+#define DEVEPTIER_RSTDTS_Pos          18                                             /**< (DEVEPTIER) Reset Data Toggle Enable Position */
+#define DEVEPTIER_RSTDTS              (_U_(0x1) << DEVEPTIER_RSTDTS_Pos)       /**< (DEVEPTIER) Reset Data Toggle Enable Mask */
+#define DEVEPTIER_Msk                 _U_(0x570A3)                                   /**< (DEVEPTIER) Register Mask  */
+
+/* CTRL mode */
+#define DEVEPTIER_CTRL_RXSTPES_Pos    2                                              /**< (DEVEPTIER) Received SETUP Interrupt Enable Position */
+#define DEVEPTIER_CTRL_RXSTPES        (_U_(0x1) << DEVEPTIER_CTRL_RXSTPES_Pos)  /**< (DEVEPTIER) Received SETUP Interrupt Enable Mask */
+#define DEVEPTIER_CTRL_NAKOUTES_Pos   3                                              /**< (DEVEPTIER) NAKed OUT Interrupt Enable Position */
+#define DEVEPTIER_CTRL_NAKOUTES       (_U_(0x1) << DEVEPTIER_CTRL_NAKOUTES_Pos)  /**< (DEVEPTIER) NAKed OUT Interrupt Enable Mask */
+#define DEVEPTIER_CTRL_NAKINES_Pos    4                                              /**< (DEVEPTIER) NAKed IN Interrupt Enable Position */
+#define DEVEPTIER_CTRL_NAKINES        (_U_(0x1) << DEVEPTIER_CTRL_NAKINES_Pos)  /**< (DEVEPTIER) NAKed IN Interrupt Enable Mask */
+#define DEVEPTIER_CTRL_STALLEDES_Pos  6                                              /**< (DEVEPTIER) STALLed Interrupt Enable Position */
+#define DEVEPTIER_CTRL_STALLEDES      (_U_(0x1) << DEVEPTIER_CTRL_STALLEDES_Pos)  /**< (DEVEPTIER) STALLed Interrupt Enable Mask */
+#define DEVEPTIER_CTRL_NYETDISS_Pos   17                                             /**< (DEVEPTIER) NYET Token Disable Enable Position */
+#define DEVEPTIER_CTRL_NYETDISS       (_U_(0x1) << DEVEPTIER_CTRL_NYETDISS_Pos)  /**< (DEVEPTIER) NYET Token Disable Enable Mask */
+#define DEVEPTIER_CTRL_STALLRQS_Pos   19                                             /**< (DEVEPTIER) STALL Request Enable Position */
+#define DEVEPTIER_CTRL_STALLRQS       (_U_(0x1) << DEVEPTIER_CTRL_STALLRQS_Pos)  /**< (DEVEPTIER) STALL Request Enable Mask */
+#define DEVEPTIER_CTRL_Msk            _U_(0xA005C)                                   /**< (DEVEPTIER_CTRL) Register Mask  */
+
+/* ISO mode */
+#define DEVEPTIER_ISO_UNDERFES_Pos    2                                              /**< (DEVEPTIER) Underflow Interrupt Enable Position */
+#define DEVEPTIER_ISO_UNDERFES        (_U_(0x1) << DEVEPTIER_ISO_UNDERFES_Pos)  /**< (DEVEPTIER) Underflow Interrupt Enable Mask */
+#define DEVEPTIER_ISO_HBISOINERRES_Pos 3                                              /**< (DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Position */
+#define DEVEPTIER_ISO_HBISOINERRES     (_U_(0x1) << DEVEPTIER_ISO_HBISOINERRES_Pos)  /**< (DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Mask */
+#define DEVEPTIER_ISO_HBISOFLUSHES_Pos 4                                              /**< (DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Position */
+#define DEVEPTIER_ISO_HBISOFLUSHES     (_U_(0x1) << DEVEPTIER_ISO_HBISOFLUSHES_Pos)  /**< (DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Mask */
+#define DEVEPTIER_ISO_CRCERRES_Pos    6                                              /**< (DEVEPTIER) CRC Error Interrupt Enable Position */
+#define DEVEPTIER_ISO_CRCERRES        (_U_(0x1) << DEVEPTIER_ISO_CRCERRES_Pos)  /**< (DEVEPTIER) CRC Error Interrupt Enable Mask */
+#define DEVEPTIER_ISO_MDATAES_Pos     8                                              /**< (DEVEPTIER) MData Interrupt Enable Position */
+#define DEVEPTIER_ISO_MDATAES         (_U_(0x1) << DEVEPTIER_ISO_MDATAES_Pos)  /**< (DEVEPTIER) MData Interrupt Enable Mask */
+#define DEVEPTIER_ISO_DATAXES_Pos     9                                              /**< (DEVEPTIER) DataX Interrupt Enable Position */
+#define DEVEPTIER_ISO_DATAXES         (_U_(0x1) << DEVEPTIER_ISO_DATAXES_Pos)  /**< (DEVEPTIER) DataX Interrupt Enable Mask */
+#define DEVEPTIER_ISO_ERRORTRANSES_Pos 10                                             /**< (DEVEPTIER) Transaction Error Interrupt Enable Position */
+#define DEVEPTIER_ISO_ERRORTRANSES     (_U_(0x1) << DEVEPTIER_ISO_ERRORTRANSES_Pos)  /**< (DEVEPTIER) Transaction Error Interrupt Enable Mask */
+#define DEVEPTIER_ISO_Msk             _U_(0x75C)                                     /**< (DEVEPTIER_ISO) Register Mask  */
+
+/* BLK mode */
+#define DEVEPTIER_BLK_RXSTPES_Pos     2                                              /**< (DEVEPTIER) Received SETUP Interrupt Enable Position */
+#define DEVEPTIER_BLK_RXSTPES         (_U_(0x1) << DEVEPTIER_BLK_RXSTPES_Pos)  /**< (DEVEPTIER) Received SETUP Interrupt Enable Mask */
+#define DEVEPTIER_BLK_NAKOUTES_Pos    3                                              /**< (DEVEPTIER) NAKed OUT Interrupt Enable Position */
+#define DEVEPTIER_BLK_NAKOUTES        (_U_(0x1) << DEVEPTIER_BLK_NAKOUTES_Pos)  /**< (DEVEPTIER) NAKed OUT Interrupt Enable Mask */
+#define DEVEPTIER_BLK_NAKINES_Pos     4                                              /**< (DEVEPTIER) NAKed IN Interrupt Enable Position */
+#define DEVEPTIER_BLK_NAKINES         (_U_(0x1) << DEVEPTIER_BLK_NAKINES_Pos)  /**< (DEVEPTIER) NAKed IN Interrupt Enable Mask */
+#define DEVEPTIER_BLK_STALLEDES_Pos   6                                              /**< (DEVEPTIER) STALLed Interrupt Enable Position */
+#define DEVEPTIER_BLK_STALLEDES       (_U_(0x1) << DEVEPTIER_BLK_STALLEDES_Pos)  /**< (DEVEPTIER) STALLed Interrupt Enable Mask */
+#define DEVEPTIER_BLK_NYETDISS_Pos    17                                             /**< (DEVEPTIER) NYET Token Disable Enable Position */
+#define DEVEPTIER_BLK_NYETDISS        (_U_(0x1) << DEVEPTIER_BLK_NYETDISS_Pos)  /**< (DEVEPTIER) NYET Token Disable Enable Mask */
+#define DEVEPTIER_BLK_STALLRQS_Pos    19                                             /**< (DEVEPTIER) STALL Request Enable Position */
+#define DEVEPTIER_BLK_STALLRQS        (_U_(0x1) << DEVEPTIER_BLK_STALLRQS_Pos)  /**< (DEVEPTIER) STALL Request Enable Mask */
+#define DEVEPTIER_BLK_Msk             _U_(0xA005C)                                   /**< (DEVEPTIER_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define DEVEPTIER_INTRPT_RXSTPES_Pos  2                                              /**< (DEVEPTIER) Received SETUP Interrupt Enable Position */
+#define DEVEPTIER_INTRPT_RXSTPES      (_U_(0x1) << DEVEPTIER_INTRPT_RXSTPES_Pos)  /**< (DEVEPTIER) Received SETUP Interrupt Enable Mask */
+#define DEVEPTIER_INTRPT_NAKOUTES_Pos 3                                              /**< (DEVEPTIER) NAKed OUT Interrupt Enable Position */
+#define DEVEPTIER_INTRPT_NAKOUTES     (_U_(0x1) << DEVEPTIER_INTRPT_NAKOUTES_Pos)  /**< (DEVEPTIER) NAKed OUT Interrupt Enable Mask */
+#define DEVEPTIER_INTRPT_NAKINES_Pos  4                                              /**< (DEVEPTIER) NAKed IN Interrupt Enable Position */
+#define DEVEPTIER_INTRPT_NAKINES      (_U_(0x1) << DEVEPTIER_INTRPT_NAKINES_Pos)  /**< (DEVEPTIER) NAKed IN Interrupt Enable Mask */
+#define DEVEPTIER_INTRPT_STALLEDES_Pos 6                                              /**< (DEVEPTIER) STALLed Interrupt Enable Position */
+#define DEVEPTIER_INTRPT_STALLEDES     (_U_(0x1) << DEVEPTIER_INTRPT_STALLEDES_Pos)  /**< (DEVEPTIER) STALLed Interrupt Enable Mask */
+#define DEVEPTIER_INTRPT_NYETDISS_Pos 17                                             /**< (DEVEPTIER) NYET Token Disable Enable Position */
+#define DEVEPTIER_INTRPT_NYETDISS     (_U_(0x1) << DEVEPTIER_INTRPT_NYETDISS_Pos)  /**< (DEVEPTIER) NYET Token Disable Enable Mask */
+#define DEVEPTIER_INTRPT_STALLRQS_Pos 19                                             /**< (DEVEPTIER) STALL Request Enable Position */
+#define DEVEPTIER_INTRPT_STALLRQS     (_U_(0x1) << DEVEPTIER_INTRPT_STALLRQS_Pos)  /**< (DEVEPTIER) STALL Request Enable Mask */
+#define DEVEPTIER_INTRPT_Msk          _U_(0xA005C)                                   /**< (DEVEPTIER_INTRPT) Register Mask  */
+
+
+/* -------- DEVEPTIDR : (USBHS Offset: 0x220) (/W 32) Device Endpoint Interrupt Disable Register -------- */
+
+#define DEVEPTIDR_OFFSET              (0x220)                                       /**<  (DEVEPTIDR) Device Endpoint Interrupt Disable Register  Offset */
+
+#define DEVEPTIDR_TXINEC_Pos          0                                              /**< (DEVEPTIDR) Transmitted IN Interrupt Clear Position */
+#define DEVEPTIDR_TXINEC              (_U_(0x1) << DEVEPTIDR_TXINEC_Pos)       /**< (DEVEPTIDR) Transmitted IN Interrupt Clear Mask */
+#define DEVEPTIDR_RXOUTEC_Pos         1                                              /**< (DEVEPTIDR) Received OUT Data Interrupt Clear Position */
+#define DEVEPTIDR_RXOUTEC             (_U_(0x1) << DEVEPTIDR_RXOUTEC_Pos)      /**< (DEVEPTIDR) Received OUT Data Interrupt Clear Mask */
+#define DEVEPTIDR_OVERFEC_Pos         5                                              /**< (DEVEPTIDR) Overflow Interrupt Clear Position */
+#define DEVEPTIDR_OVERFEC             (_U_(0x1) << DEVEPTIDR_OVERFEC_Pos)      /**< (DEVEPTIDR) Overflow Interrupt Clear Mask */
+#define DEVEPTIDR_SHORTPACKETEC_Pos   7                                              /**< (DEVEPTIDR) Shortpacket Interrupt Clear Position */
+#define DEVEPTIDR_SHORTPACKETEC       (_U_(0x1) << DEVEPTIDR_SHORTPACKETEC_Pos)  /**< (DEVEPTIDR) Shortpacket Interrupt Clear Mask */
+#define DEVEPTIDR_NBUSYBKEC_Pos       12                                             /**< (DEVEPTIDR) Number of Busy Banks Interrupt Clear Position */
+#define DEVEPTIDR_NBUSYBKEC           (_U_(0x1) << DEVEPTIDR_NBUSYBKEC_Pos)    /**< (DEVEPTIDR) Number of Busy Banks Interrupt Clear Mask */
+#define DEVEPTIDR_FIFOCONC_Pos        14                                             /**< (DEVEPTIDR) FIFO Control Clear Position */
+#define DEVEPTIDR_FIFOCONC            (_U_(0x1) << DEVEPTIDR_FIFOCONC_Pos)     /**< (DEVEPTIDR) FIFO Control Clear Mask */
+#define DEVEPTIDR_EPDISHDMAC_Pos      16                                             /**< (DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Position */
+#define DEVEPTIDR_EPDISHDMAC          (_U_(0x1) << DEVEPTIDR_EPDISHDMAC_Pos)   /**< (DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Mask */
+#define DEVEPTIDR_Msk                 _U_(0x150A3)                                   /**< (DEVEPTIDR) Register Mask  */
+
+/* CTRL mode */
+#define DEVEPTIDR_CTRL_RXSTPEC_Pos    2                                              /**< (DEVEPTIDR) Received SETUP Interrupt Clear Position */
+#define DEVEPTIDR_CTRL_RXSTPEC        (_U_(0x1) << DEVEPTIDR_CTRL_RXSTPEC_Pos)  /**< (DEVEPTIDR) Received SETUP Interrupt Clear Mask */
+#define DEVEPTIDR_CTRL_NAKOUTEC_Pos   3                                              /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Position */
+#define DEVEPTIDR_CTRL_NAKOUTEC       (_U_(0x1) << DEVEPTIDR_CTRL_NAKOUTEC_Pos)  /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Mask */
+#define DEVEPTIDR_CTRL_NAKINEC_Pos    4                                              /**< (DEVEPTIDR) NAKed IN Interrupt Clear Position */
+#define DEVEPTIDR_CTRL_NAKINEC        (_U_(0x1) << DEVEPTIDR_CTRL_NAKINEC_Pos)  /**< (DEVEPTIDR) NAKed IN Interrupt Clear Mask */
+#define DEVEPTIDR_CTRL_STALLEDEC_Pos  6                                              /**< (DEVEPTIDR) STALLed Interrupt Clear Position */
+#define DEVEPTIDR_CTRL_STALLEDEC      (_U_(0x1) << DEVEPTIDR_CTRL_STALLEDEC_Pos)  /**< (DEVEPTIDR) STALLed Interrupt Clear Mask */
+#define DEVEPTIDR_CTRL_NYETDISC_Pos   17                                             /**< (DEVEPTIDR) NYET Token Disable Clear Position */
+#define DEVEPTIDR_CTRL_NYETDISC       (_U_(0x1) << DEVEPTIDR_CTRL_NYETDISC_Pos)  /**< (DEVEPTIDR) NYET Token Disable Clear Mask */
+#define DEVEPTIDR_CTRL_STALLRQC_Pos   19                                             /**< (DEVEPTIDR) STALL Request Clear Position */
+#define DEVEPTIDR_CTRL_STALLRQC       (_U_(0x1) << DEVEPTIDR_CTRL_STALLRQC_Pos)  /**< (DEVEPTIDR) STALL Request Clear Mask */
+#define DEVEPTIDR_CTRL_Msk            _U_(0xA005C)                                   /**< (DEVEPTIDR_CTRL) Register Mask  */
+
+/* ISO mode */
+#define DEVEPTIDR_ISO_UNDERFEC_Pos    2                                              /**< (DEVEPTIDR) Underflow Interrupt Clear Position */
+#define DEVEPTIDR_ISO_UNDERFEC        (_U_(0x1) << DEVEPTIDR_ISO_UNDERFEC_Pos)  /**< (DEVEPTIDR) Underflow Interrupt Clear Mask */
+#define DEVEPTIDR_ISO_HBISOINERREC_Pos 3                                              /**< (DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */
+#define DEVEPTIDR_ISO_HBISOINERREC     (_U_(0x1) << DEVEPTIDR_ISO_HBISOINERREC_Pos)  /**< (DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */
+#define DEVEPTIDR_ISO_HBISOFLUSHEC_Pos 4                                              /**< (DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */
+#define DEVEPTIDR_ISO_HBISOFLUSHEC     (_U_(0x1) << DEVEPTIDR_ISO_HBISOFLUSHEC_Pos)  /**< (DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */
+#define DEVEPTIDR_ISO_MDATAEC_Pos     8                                              /**< (DEVEPTIDR) MData Interrupt Clear Position */
+#define DEVEPTIDR_ISO_MDATAEC         (_U_(0x1) << DEVEPTIDR_ISO_MDATAEC_Pos)  /**< (DEVEPTIDR) MData Interrupt Clear Mask */
+#define DEVEPTIDR_ISO_DATAXEC_Pos     9                                              /**< (DEVEPTIDR) DataX Interrupt Clear Position */
+#define DEVEPTIDR_ISO_DATAXEC         (_U_(0x1) << DEVEPTIDR_ISO_DATAXEC_Pos)  /**< (DEVEPTIDR) DataX Interrupt Clear Mask */
+#define DEVEPTIDR_ISO_ERRORTRANSEC_Pos 10                                             /**< (DEVEPTIDR) Transaction Error Interrupt Clear Position */
+#define DEVEPTIDR_ISO_ERRORTRANSEC     (_U_(0x1) << DEVEPTIDR_ISO_ERRORTRANSEC_Pos)  /**< (DEVEPTIDR) Transaction Error Interrupt Clear Mask */
+#define DEVEPTIDR_ISO_Msk             _U_(0x71C)                                     /**< (DEVEPTIDR_ISO) Register Mask  */
+
+/* BLK mode */
+#define DEVEPTIDR_BLK_RXSTPEC_Pos     2                                              /**< (DEVEPTIDR) Received SETUP Interrupt Clear Position */
+#define DEVEPTIDR_BLK_RXSTPEC         (_U_(0x1) << DEVEPTIDR_BLK_RXSTPEC_Pos)  /**< (DEVEPTIDR) Received SETUP Interrupt Clear Mask */
+#define DEVEPTIDR_BLK_NAKOUTEC_Pos    3                                              /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Position */
+#define DEVEPTIDR_BLK_NAKOUTEC        (_U_(0x1) << DEVEPTIDR_BLK_NAKOUTEC_Pos)  /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Mask */
+#define DEVEPTIDR_BLK_NAKINEC_Pos     4                                              /**< (DEVEPTIDR) NAKed IN Interrupt Clear Position */
+#define DEVEPTIDR_BLK_NAKINEC         (_U_(0x1) << DEVEPTIDR_BLK_NAKINEC_Pos)  /**< (DEVEPTIDR) NAKed IN Interrupt Clear Mask */
+#define DEVEPTIDR_BLK_STALLEDEC_Pos   6                                              /**< (DEVEPTIDR) STALLed Interrupt Clear Position */
+#define DEVEPTIDR_BLK_STALLEDEC       (_U_(0x1) << DEVEPTIDR_BLK_STALLEDEC_Pos)  /**< (DEVEPTIDR) STALLed Interrupt Clear Mask */
+#define DEVEPTIDR_BLK_NYETDISC_Pos    17                                             /**< (DEVEPTIDR) NYET Token Disable Clear Position */
+#define DEVEPTIDR_BLK_NYETDISC        (_U_(0x1) << DEVEPTIDR_BLK_NYETDISC_Pos)  /**< (DEVEPTIDR) NYET Token Disable Clear Mask */
+#define DEVEPTIDR_BLK_STALLRQC_Pos    19                                             /**< (DEVEPTIDR) STALL Request Clear Position */
+#define DEVEPTIDR_BLK_STALLRQC        (_U_(0x1) << DEVEPTIDR_BLK_STALLRQC_Pos)  /**< (DEVEPTIDR) STALL Request Clear Mask */
+#define DEVEPTIDR_BLK_Msk             _U_(0xA005C)                                   /**< (DEVEPTIDR_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define DEVEPTIDR_INTRPT_RXSTPEC_Pos  2                                              /**< (DEVEPTIDR) Received SETUP Interrupt Clear Position */
+#define DEVEPTIDR_INTRPT_RXSTPEC      (_U_(0x1) << DEVEPTIDR_INTRPT_RXSTPEC_Pos)  /**< (DEVEPTIDR) Received SETUP Interrupt Clear Mask */
+#define DEVEPTIDR_INTRPT_NAKOUTEC_Pos 3                                              /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Position */
+#define DEVEPTIDR_INTRPT_NAKOUTEC     (_U_(0x1) << DEVEPTIDR_INTRPT_NAKOUTEC_Pos)  /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Mask */
+#define DEVEPTIDR_INTRPT_NAKINEC_Pos  4                                              /**< (DEVEPTIDR) NAKed IN Interrupt Clear Position */
+#define DEVEPTIDR_INTRPT_NAKINEC      (_U_(0x1) << DEVEPTIDR_INTRPT_NAKINEC_Pos)  /**< (DEVEPTIDR) NAKed IN Interrupt Clear Mask */
+#define DEVEPTIDR_INTRPT_STALLEDEC_Pos 6                                              /**< (DEVEPTIDR) STALLed Interrupt Clear Position */
+#define DEVEPTIDR_INTRPT_STALLEDEC     (_U_(0x1) << DEVEPTIDR_INTRPT_STALLEDEC_Pos)  /**< (DEVEPTIDR) STALLed Interrupt Clear Mask */
+#define DEVEPTIDR_INTRPT_NYETDISC_Pos 17                                             /**< (DEVEPTIDR) NYET Token Disable Clear Position */
+#define DEVEPTIDR_INTRPT_NYETDISC     (_U_(0x1) << DEVEPTIDR_INTRPT_NYETDISC_Pos)  /**< (DEVEPTIDR) NYET Token Disable Clear Mask */
+#define DEVEPTIDR_INTRPT_STALLRQC_Pos 19                                             /**< (DEVEPTIDR) STALL Request Clear Position */
+#define DEVEPTIDR_INTRPT_STALLRQC     (_U_(0x1) << DEVEPTIDR_INTRPT_STALLRQC_Pos)  /**< (DEVEPTIDR) STALL Request Clear Mask */
+#define DEVEPTIDR_INTRPT_Msk          _U_(0xA005C)                                   /**< (DEVEPTIDR_INTRPT) Register Mask  */
+
+
+/* -------- HSTCTRL : (USBHS Offset: 0x400) (R/W 32) Host General Control Register -------- */
+
+#define HSTCTRL_OFFSET                (0x400)                                       /**<  (HSTCTRL) Host General Control Register  Offset */
+
+#define HSTCTRL_SOFE_Pos              8                                              /**< (HSTCTRL) Start of Frame Generation Enable Position */
+#define HSTCTRL_SOFE                  (_U_(0x1) << HSTCTRL_SOFE_Pos)           /**< (HSTCTRL) Start of Frame Generation Enable Mask */
+#define HSTCTRL_RESET_Pos             9                                              /**< (HSTCTRL) Send USB Reset Position */
+#define HSTCTRL_RESET                 (_U_(0x1) << HSTCTRL_RESET_Pos)          /**< (HSTCTRL) Send USB Reset Mask */
+#define HSTCTRL_RESUME_Pos            10                                             /**< (HSTCTRL) Send USB Resume Position */
+#define HSTCTRL_RESUME                (_U_(0x1) << HSTCTRL_RESUME_Pos)         /**< (HSTCTRL) Send USB Resume Mask */
+#define HSTCTRL_SPDCONF_Pos           12                                             /**< (HSTCTRL) Mode Configuration Position */
+#define HSTCTRL_SPDCONF               (_U_(0x3) << HSTCTRL_SPDCONF_Pos)        /**< (HSTCTRL) Mode Configuration Mask */
+#define   HSTCTRL_SPDCONF_NORMAL_Val  _U_(0x0)                                       /**< (HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable.  */
+#define   HSTCTRL_SPDCONF_LOW_POWER_Val _U_(0x1)                                       /**< (HSTCTRL) For a better consumption, if high speed is not needed.  */
+#define   HSTCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2)                                       /**< (HSTCTRL) Forced high speed.  */
+#define   HSTCTRL_SPDCONF_FORCED_FS_Val _U_(0x3)                                       /**< (HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability.  */
+#define HSTCTRL_SPDCONF_NORMAL        (HSTCTRL_SPDCONF_NORMAL_Val << HSTCTRL_SPDCONF_Pos)  /**< (HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. Position  */
+#define HSTCTRL_SPDCONF_LOW_POWER     (HSTCTRL_SPDCONF_LOW_POWER_Val << HSTCTRL_SPDCONF_Pos)  /**< (HSTCTRL) For a better consumption, if high speed is not needed. Position  */
+#define HSTCTRL_SPDCONF_HIGH_SPEED    (HSTCTRL_SPDCONF_HIGH_SPEED_Val << HSTCTRL_SPDCONF_Pos)  /**< (HSTCTRL) Forced high speed. Position  */
+#define HSTCTRL_SPDCONF_FORCED_FS     (HSTCTRL_SPDCONF_FORCED_FS_Val << HSTCTRL_SPDCONF_Pos)  /**< (HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. Position  */
+#define HSTCTRL_Msk                   _U_(0x3700)                                    /**< (HSTCTRL) Register Mask  */
+
+
+/* -------- HSTISR : (USBHS Offset: 0x404) (R/ 32) Host Global Interrupt Status Register -------- */
+
+#define HSTISR_OFFSET                 (0x404)                                       /**<  (HSTISR) Host Global Interrupt Status Register  Offset */
+
+#define HSTISR_DCONNI_Pos             0                                              /**< (HSTISR) Device Connection Interrupt Position */
+#define HSTISR_DCONNI                 (_U_(0x1) << HSTISR_DCONNI_Pos)          /**< (HSTISR) Device Connection Interrupt Mask */
+#define HSTISR_DDISCI_Pos             1                                              /**< (HSTISR) Device Disconnection Interrupt Position */
+#define HSTISR_DDISCI                 (_U_(0x1) << HSTISR_DDISCI_Pos)          /**< (HSTISR) Device Disconnection Interrupt Mask */
+#define HSTISR_RSTI_Pos               2                                              /**< (HSTISR) USB Reset Sent Interrupt Position */
+#define HSTISR_RSTI                   (_U_(0x1) << HSTISR_RSTI_Pos)            /**< (HSTISR) USB Reset Sent Interrupt Mask */
+#define HSTISR_RSMEDI_Pos             3                                              /**< (HSTISR) Downstream Resume Sent Interrupt Position */
+#define HSTISR_RSMEDI                 (_U_(0x1) << HSTISR_RSMEDI_Pos)          /**< (HSTISR) Downstream Resume Sent Interrupt Mask */
+#define HSTISR_RXRSMI_Pos             4                                              /**< (HSTISR) Upstream Resume Received Interrupt Position */
+#define HSTISR_RXRSMI                 (_U_(0x1) << HSTISR_RXRSMI_Pos)          /**< (HSTISR) Upstream Resume Received Interrupt Mask */
+#define HSTISR_HSOFI_Pos              5                                              /**< (HSTISR) Host Start of Frame Interrupt Position */
+#define HSTISR_HSOFI                  (_U_(0x1) << HSTISR_HSOFI_Pos)           /**< (HSTISR) Host Start of Frame Interrupt Mask */
+#define HSTISR_HWUPI_Pos              6                                              /**< (HSTISR) Host Wake-Up Interrupt Position */
+#define HSTISR_HWUPI                  (_U_(0x1) << HSTISR_HWUPI_Pos)           /**< (HSTISR) Host Wake-Up Interrupt Mask */
+#define HSTISR_PEP_0_Pos              8                                              /**< (HSTISR) Pipe 0 Interrupt Position */
+#define HSTISR_PEP_0                  (_U_(0x1) << HSTISR_PEP_0_Pos)           /**< (HSTISR) Pipe 0 Interrupt Mask */
+#define HSTISR_PEP_1_Pos              9                                              /**< (HSTISR) Pipe 1 Interrupt Position */
+#define HSTISR_PEP_1                  (_U_(0x1) << HSTISR_PEP_1_Pos)           /**< (HSTISR) Pipe 1 Interrupt Mask */
+#define HSTISR_PEP_2_Pos              10                                             /**< (HSTISR) Pipe 2 Interrupt Position */
+#define HSTISR_PEP_2                  (_U_(0x1) << HSTISR_PEP_2_Pos)           /**< (HSTISR) Pipe 2 Interrupt Mask */
+#define HSTISR_PEP_3_Pos              11                                             /**< (HSTISR) Pipe 3 Interrupt Position */
+#define HSTISR_PEP_3                  (_U_(0x1) << HSTISR_PEP_3_Pos)           /**< (HSTISR) Pipe 3 Interrupt Mask */
+#define HSTISR_PEP_4_Pos              12                                             /**< (HSTISR) Pipe 4 Interrupt Position */
+#define HSTISR_PEP_4                  (_U_(0x1) << HSTISR_PEP_4_Pos)           /**< (HSTISR) Pipe 4 Interrupt Mask */
+#define HSTISR_PEP_5_Pos              13                                             /**< (HSTISR) Pipe 5 Interrupt Position */
+#define HSTISR_PEP_5                  (_U_(0x1) << HSTISR_PEP_5_Pos)           /**< (HSTISR) Pipe 5 Interrupt Mask */
+#define HSTISR_PEP_6_Pos              14                                             /**< (HSTISR) Pipe 6 Interrupt Position */
+#define HSTISR_PEP_6                  (_U_(0x1) << HSTISR_PEP_6_Pos)           /**< (HSTISR) Pipe 6 Interrupt Mask */
+#define HSTISR_PEP_7_Pos              15                                             /**< (HSTISR) Pipe 7 Interrupt Position */
+#define HSTISR_PEP_7                  (_U_(0x1) << HSTISR_PEP_7_Pos)           /**< (HSTISR) Pipe 7 Interrupt Mask */
+#define HSTISR_PEP_8_Pos              16                                             /**< (HSTISR) Pipe 8 Interrupt Position */
+#define HSTISR_PEP_8                  (_U_(0x1) << HSTISR_PEP_8_Pos)           /**< (HSTISR) Pipe 8 Interrupt Mask */
+#define HSTISR_PEP_9_Pos              17                                             /**< (HSTISR) Pipe 9 Interrupt Position */
+#define HSTISR_PEP_9                  (_U_(0x1) << HSTISR_PEP_9_Pos)           /**< (HSTISR) Pipe 9 Interrupt Mask */
+#define HSTISR_DMA_0_Pos              25                                             /**< (HSTISR) DMA Channel 0 Interrupt Position */
+#define HSTISR_DMA_0                  (_U_(0x1) << HSTISR_DMA_0_Pos)           /**< (HSTISR) DMA Channel 0 Interrupt Mask */
+#define HSTISR_DMA_1_Pos              26                                             /**< (HSTISR) DMA Channel 1 Interrupt Position */
+#define HSTISR_DMA_1                  (_U_(0x1) << HSTISR_DMA_1_Pos)           /**< (HSTISR) DMA Channel 1 Interrupt Mask */
+#define HSTISR_DMA_2_Pos              27                                             /**< (HSTISR) DMA Channel 2 Interrupt Position */
+#define HSTISR_DMA_2                  (_U_(0x1) << HSTISR_DMA_2_Pos)           /**< (HSTISR) DMA Channel 2 Interrupt Mask */
+#define HSTISR_DMA_3_Pos              28                                             /**< (HSTISR) DMA Channel 3 Interrupt Position */
+#define HSTISR_DMA_3                  (_U_(0x1) << HSTISR_DMA_3_Pos)           /**< (HSTISR) DMA Channel 3 Interrupt Mask */
+#define HSTISR_DMA_4_Pos              29                                             /**< (HSTISR) DMA Channel 4 Interrupt Position */
+#define HSTISR_DMA_4                  (_U_(0x1) << HSTISR_DMA_4_Pos)           /**< (HSTISR) DMA Channel 4 Interrupt Mask */
+#define HSTISR_DMA_5_Pos              30                                             /**< (HSTISR) DMA Channel 5 Interrupt Position */
+#define HSTISR_DMA_5                  (_U_(0x1) << HSTISR_DMA_5_Pos)           /**< (HSTISR) DMA Channel 5 Interrupt Mask */
+#define HSTISR_DMA_6_Pos              31                                             /**< (HSTISR) DMA Channel 6 Interrupt Position */
+#define HSTISR_DMA_6                  (_U_(0x1) << HSTISR_DMA_6_Pos)           /**< (HSTISR) DMA Channel 6 Interrupt Mask */
+#define HSTISR_Msk                    _U_(0xFE03FF7F)                                /**< (HSTISR) Register Mask  */
+
+#define HSTISR_PEP__Pos               8                                              /**< (HSTISR Position) Pipe x Interrupt */
+#define HSTISR_PEP_                   (_U_(0x3FF) << HSTISR_PEP__Pos)          /**< (HSTISR Mask) PEP_ */
+#define HSTISR_DMA__Pos               25                                             /**< (HSTISR Position) DMA Channel 6 Interrupt */
+#define HSTISR_DMA_                   (_U_(0x7F) << HSTISR_DMA__Pos)           /**< (HSTISR Mask) DMA_ */
+
+/* -------- HSTICR : (USBHS Offset: 0x408) (/W 32) Host Global Interrupt Clear Register -------- */
+
+#define HSTICR_OFFSET                 (0x408)                                       /**<  (HSTICR) Host Global Interrupt Clear Register  Offset */
+
+#define HSTICR_DCONNIC_Pos            0                                              /**< (HSTICR) Device Connection Interrupt Clear Position */
+#define HSTICR_DCONNIC                (_U_(0x1) << HSTICR_DCONNIC_Pos)         /**< (HSTICR) Device Connection Interrupt Clear Mask */
+#define HSTICR_DDISCIC_Pos            1                                              /**< (HSTICR) Device Disconnection Interrupt Clear Position */
+#define HSTICR_DDISCIC                (_U_(0x1) << HSTICR_DDISCIC_Pos)         /**< (HSTICR) Device Disconnection Interrupt Clear Mask */
+#define HSTICR_RSTIC_Pos              2                                              /**< (HSTICR) USB Reset Sent Interrupt Clear Position */
+#define HSTICR_RSTIC                  (_U_(0x1) << HSTICR_RSTIC_Pos)           /**< (HSTICR) USB Reset Sent Interrupt Clear Mask */
+#define HSTICR_RSMEDIC_Pos            3                                              /**< (HSTICR) Downstream Resume Sent Interrupt Clear Position */
+#define HSTICR_RSMEDIC                (_U_(0x1) << HSTICR_RSMEDIC_Pos)         /**< (HSTICR) Downstream Resume Sent Interrupt Clear Mask */
+#define HSTICR_RXRSMIC_Pos            4                                              /**< (HSTICR) Upstream Resume Received Interrupt Clear Position */
+#define HSTICR_RXRSMIC                (_U_(0x1) << HSTICR_RXRSMIC_Pos)         /**< (HSTICR) Upstream Resume Received Interrupt Clear Mask */
+#define HSTICR_HSOFIC_Pos             5                                              /**< (HSTICR) Host Start of Frame Interrupt Clear Position */
+#define HSTICR_HSOFIC                 (_U_(0x1) << HSTICR_HSOFIC_Pos)          /**< (HSTICR) Host Start of Frame Interrupt Clear Mask */
+#define HSTICR_HWUPIC_Pos             6                                              /**< (HSTICR) Host Wake-Up Interrupt Clear Position */
+#define HSTICR_HWUPIC                 (_U_(0x1) << HSTICR_HWUPIC_Pos)          /**< (HSTICR) Host Wake-Up Interrupt Clear Mask */
+#define HSTICR_Msk                    _U_(0x7F)                                      /**< (HSTICR) Register Mask  */
+
+
+/* -------- HSTIFR : (USBHS Offset: 0x40c) (/W 32) Host Global Interrupt Set Register -------- */
+
+#define HSTIFR_OFFSET                 (0x40C)                                       /**<  (HSTIFR) Host Global Interrupt Set Register  Offset */
+
+#define HSTIFR_DCONNIS_Pos            0                                              /**< (HSTIFR) Device Connection Interrupt Set Position */
+#define HSTIFR_DCONNIS                (_U_(0x1) << HSTIFR_DCONNIS_Pos)         /**< (HSTIFR) Device Connection Interrupt Set Mask */
+#define HSTIFR_DDISCIS_Pos            1                                              /**< (HSTIFR) Device Disconnection Interrupt Set Position */
+#define HSTIFR_DDISCIS                (_U_(0x1) << HSTIFR_DDISCIS_Pos)         /**< (HSTIFR) Device Disconnection Interrupt Set Mask */
+#define HSTIFR_RSTIS_Pos              2                                              /**< (HSTIFR) USB Reset Sent Interrupt Set Position */
+#define HSTIFR_RSTIS                  (_U_(0x1) << HSTIFR_RSTIS_Pos)           /**< (HSTIFR) USB Reset Sent Interrupt Set Mask */
+#define HSTIFR_RSMEDIS_Pos            3                                              /**< (HSTIFR) Downstream Resume Sent Interrupt Set Position */
+#define HSTIFR_RSMEDIS                (_U_(0x1) << HSTIFR_RSMEDIS_Pos)         /**< (HSTIFR) Downstream Resume Sent Interrupt Set Mask */
+#define HSTIFR_RXRSMIS_Pos            4                                              /**< (HSTIFR) Upstream Resume Received Interrupt Set Position */
+#define HSTIFR_RXRSMIS                (_U_(0x1) << HSTIFR_RXRSMIS_Pos)         /**< (HSTIFR) Upstream Resume Received Interrupt Set Mask */
+#define HSTIFR_HSOFIS_Pos             5                                              /**< (HSTIFR) Host Start of Frame Interrupt Set Position */
+#define HSTIFR_HSOFIS                 (_U_(0x1) << HSTIFR_HSOFIS_Pos)          /**< (HSTIFR) Host Start of Frame Interrupt Set Mask */
+#define HSTIFR_HWUPIS_Pos             6                                              /**< (HSTIFR) Host Wake-Up Interrupt Set Position */
+#define HSTIFR_HWUPIS                 (_U_(0x1) << HSTIFR_HWUPIS_Pos)          /**< (HSTIFR) Host Wake-Up Interrupt Set Mask */
+#define HSTIFR_DMA_0_Pos              25                                             /**< (HSTIFR) DMA Channel 0 Interrupt Set Position */
+#define HSTIFR_DMA_0                  (_U_(0x1) << HSTIFR_DMA_0_Pos)           /**< (HSTIFR) DMA Channel 0 Interrupt Set Mask */
+#define HSTIFR_DMA_1_Pos              26                                             /**< (HSTIFR) DMA Channel 1 Interrupt Set Position */
+#define HSTIFR_DMA_1                  (_U_(0x1) << HSTIFR_DMA_1_Pos)           /**< (HSTIFR) DMA Channel 1 Interrupt Set Mask */
+#define HSTIFR_DMA_2_Pos              27                                             /**< (HSTIFR) DMA Channel 2 Interrupt Set Position */
+#define HSTIFR_DMA_2                  (_U_(0x1) << HSTIFR_DMA_2_Pos)           /**< (HSTIFR) DMA Channel 2 Interrupt Set Mask */
+#define HSTIFR_DMA_3_Pos              28                                             /**< (HSTIFR) DMA Channel 3 Interrupt Set Position */
+#define HSTIFR_DMA_3                  (_U_(0x1) << HSTIFR_DMA_3_Pos)           /**< (HSTIFR) DMA Channel 3 Interrupt Set Mask */
+#define HSTIFR_DMA_4_Pos              29                                             /**< (HSTIFR) DMA Channel 4 Interrupt Set Position */
+#define HSTIFR_DMA_4                  (_U_(0x1) << HSTIFR_DMA_4_Pos)           /**< (HSTIFR) DMA Channel 4 Interrupt Set Mask */
+#define HSTIFR_DMA_5_Pos              30                                             /**< (HSTIFR) DMA Channel 5 Interrupt Set Position */
+#define HSTIFR_DMA_5                  (_U_(0x1) << HSTIFR_DMA_5_Pos)           /**< (HSTIFR) DMA Channel 5 Interrupt Set Mask */
+#define HSTIFR_DMA_6_Pos              31                                             /**< (HSTIFR) DMA Channel 6 Interrupt Set Position */
+#define HSTIFR_DMA_6                  (_U_(0x1) << HSTIFR_DMA_6_Pos)           /**< (HSTIFR) DMA Channel 6 Interrupt Set Mask */
+#define HSTIFR_Msk                    _U_(0xFE00007F)                                /**< (HSTIFR) Register Mask  */
+
+#define HSTIFR_DMA__Pos               25                                             /**< (HSTIFR Position) DMA Channel 6 Interrupt Set */
+#define HSTIFR_DMA_                   (_U_(0x7F) << HSTIFR_DMA__Pos)           /**< (HSTIFR Mask) DMA_ */
+
+/* -------- HSTIMR : (USBHS Offset: 0x410) (R/ 32) Host Global Interrupt Mask Register -------- */
+
+#define HSTIMR_OFFSET                 (0x410)                                       /**<  (HSTIMR) Host Global Interrupt Mask Register  Offset */
+
+#define HSTIMR_DCONNIE_Pos            0                                              /**< (HSTIMR) Device Connection Interrupt Enable Position */
+#define HSTIMR_DCONNIE                (_U_(0x1) << HSTIMR_DCONNIE_Pos)         /**< (HSTIMR) Device Connection Interrupt Enable Mask */
+#define HSTIMR_DDISCIE_Pos            1                                              /**< (HSTIMR) Device Disconnection Interrupt Enable Position */
+#define HSTIMR_DDISCIE                (_U_(0x1) << HSTIMR_DDISCIE_Pos)         /**< (HSTIMR) Device Disconnection Interrupt Enable Mask */
+#define HSTIMR_RSTIE_Pos              2                                              /**< (HSTIMR) USB Reset Sent Interrupt Enable Position */
+#define HSTIMR_RSTIE                  (_U_(0x1) << HSTIMR_RSTIE_Pos)           /**< (HSTIMR) USB Reset Sent Interrupt Enable Mask */
+#define HSTIMR_RSMEDIE_Pos            3                                              /**< (HSTIMR) Downstream Resume Sent Interrupt Enable Position */
+#define HSTIMR_RSMEDIE                (_U_(0x1) << HSTIMR_RSMEDIE_Pos)         /**< (HSTIMR) Downstream Resume Sent Interrupt Enable Mask */
+#define HSTIMR_RXRSMIE_Pos            4                                              /**< (HSTIMR) Upstream Resume Received Interrupt Enable Position */
+#define HSTIMR_RXRSMIE                (_U_(0x1) << HSTIMR_RXRSMIE_Pos)         /**< (HSTIMR) Upstream Resume Received Interrupt Enable Mask */
+#define HSTIMR_HSOFIE_Pos             5                                              /**< (HSTIMR) Host Start of Frame Interrupt Enable Position */
+#define HSTIMR_HSOFIE                 (_U_(0x1) << HSTIMR_HSOFIE_Pos)          /**< (HSTIMR) Host Start of Frame Interrupt Enable Mask */
+#define HSTIMR_HWUPIE_Pos             6                                              /**< (HSTIMR) Host Wake-Up Interrupt Enable Position */
+#define HSTIMR_HWUPIE                 (_U_(0x1) << HSTIMR_HWUPIE_Pos)          /**< (HSTIMR) Host Wake-Up Interrupt Enable Mask */
+#define HSTIMR_PEP_0_Pos              8                                              /**< (HSTIMR) Pipe 0 Interrupt Enable Position */
+#define HSTIMR_PEP_0                  (_U_(0x1) << HSTIMR_PEP_0_Pos)           /**< (HSTIMR) Pipe 0 Interrupt Enable Mask */
+#define HSTIMR_PEP_1_Pos              9                                              /**< (HSTIMR) Pipe 1 Interrupt Enable Position */
+#define HSTIMR_PEP_1                  (_U_(0x1) << HSTIMR_PEP_1_Pos)           /**< (HSTIMR) Pipe 1 Interrupt Enable Mask */
+#define HSTIMR_PEP_2_Pos              10                                             /**< (HSTIMR) Pipe 2 Interrupt Enable Position */
+#define HSTIMR_PEP_2                  (_U_(0x1) << HSTIMR_PEP_2_Pos)           /**< (HSTIMR) Pipe 2 Interrupt Enable Mask */
+#define HSTIMR_PEP_3_Pos              11                                             /**< (HSTIMR) Pipe 3 Interrupt Enable Position */
+#define HSTIMR_PEP_3                  (_U_(0x1) << HSTIMR_PEP_3_Pos)           /**< (HSTIMR) Pipe 3 Interrupt Enable Mask */
+#define HSTIMR_PEP_4_Pos              12                                             /**< (HSTIMR) Pipe 4 Interrupt Enable Position */
+#define HSTIMR_PEP_4                  (_U_(0x1) << HSTIMR_PEP_4_Pos)           /**< (HSTIMR) Pipe 4 Interrupt Enable Mask */
+#define HSTIMR_PEP_5_Pos              13                                             /**< (HSTIMR) Pipe 5 Interrupt Enable Position */
+#define HSTIMR_PEP_5                  (_U_(0x1) << HSTIMR_PEP_5_Pos)           /**< (HSTIMR) Pipe 5 Interrupt Enable Mask */
+#define HSTIMR_PEP_6_Pos              14                                             /**< (HSTIMR) Pipe 6 Interrupt Enable Position */
+#define HSTIMR_PEP_6                  (_U_(0x1) << HSTIMR_PEP_6_Pos)           /**< (HSTIMR) Pipe 6 Interrupt Enable Mask */
+#define HSTIMR_PEP_7_Pos              15                                             /**< (HSTIMR) Pipe 7 Interrupt Enable Position */
+#define HSTIMR_PEP_7                  (_U_(0x1) << HSTIMR_PEP_7_Pos)           /**< (HSTIMR) Pipe 7 Interrupt Enable Mask */
+#define HSTIMR_PEP_8_Pos              16                                             /**< (HSTIMR) Pipe 8 Interrupt Enable Position */
+#define HSTIMR_PEP_8                  (_U_(0x1) << HSTIMR_PEP_8_Pos)           /**< (HSTIMR) Pipe 8 Interrupt Enable Mask */
+#define HSTIMR_PEP_9_Pos              17                                             /**< (HSTIMR) Pipe 9 Interrupt Enable Position */
+#define HSTIMR_PEP_9                  (_U_(0x1) << HSTIMR_PEP_9_Pos)           /**< (HSTIMR) Pipe 9 Interrupt Enable Mask */
+#define HSTIMR_DMA_0_Pos              25                                             /**< (HSTIMR) DMA Channel 0 Interrupt Enable Position */
+#define HSTIMR_DMA_0                  (_U_(0x1) << HSTIMR_DMA_0_Pos)           /**< (HSTIMR) DMA Channel 0 Interrupt Enable Mask */
+#define HSTIMR_DMA_1_Pos              26                                             /**< (HSTIMR) DMA Channel 1 Interrupt Enable Position */
+#define HSTIMR_DMA_1                  (_U_(0x1) << HSTIMR_DMA_1_Pos)           /**< (HSTIMR) DMA Channel 1 Interrupt Enable Mask */
+#define HSTIMR_DMA_2_Pos              27                                             /**< (HSTIMR) DMA Channel 2 Interrupt Enable Position */
+#define HSTIMR_DMA_2                  (_U_(0x1) << HSTIMR_DMA_2_Pos)           /**< (HSTIMR) DMA Channel 2 Interrupt Enable Mask */
+#define HSTIMR_DMA_3_Pos              28                                             /**< (HSTIMR) DMA Channel 3 Interrupt Enable Position */
+#define HSTIMR_DMA_3                  (_U_(0x1) << HSTIMR_DMA_3_Pos)           /**< (HSTIMR) DMA Channel 3 Interrupt Enable Mask */
+#define HSTIMR_DMA_4_Pos              29                                             /**< (HSTIMR) DMA Channel 4 Interrupt Enable Position */
+#define HSTIMR_DMA_4                  (_U_(0x1) << HSTIMR_DMA_4_Pos)           /**< (HSTIMR) DMA Channel 4 Interrupt Enable Mask */
+#define HSTIMR_DMA_5_Pos              30                                             /**< (HSTIMR) DMA Channel 5 Interrupt Enable Position */
+#define HSTIMR_DMA_5                  (_U_(0x1) << HSTIMR_DMA_5_Pos)           /**< (HSTIMR) DMA Channel 5 Interrupt Enable Mask */
+#define HSTIMR_DMA_6_Pos              31                                             /**< (HSTIMR) DMA Channel 6 Interrupt Enable Position */
+#define HSTIMR_DMA_6                  (_U_(0x1) << HSTIMR_DMA_6_Pos)           /**< (HSTIMR) DMA Channel 6 Interrupt Enable Mask */
+#define HSTIMR_Msk                    _U_(0xFE03FF7F)                                /**< (HSTIMR) Register Mask  */
+
+#define HSTIMR_PEP__Pos               8                                              /**< (HSTIMR Position) Pipe x Interrupt Enable */
+#define HSTIMR_PEP_                   (_U_(0x3FF) << HSTIMR_PEP__Pos)          /**< (HSTIMR Mask) PEP_ */
+#define HSTIMR_DMA__Pos               25                                             /**< (HSTIMR Position) DMA Channel 6 Interrupt Enable */
+#define HSTIMR_DMA_                   (_U_(0x7F) << HSTIMR_DMA__Pos)           /**< (HSTIMR Mask) DMA_ */
+
+/* -------- HSTIDR : (USBHS Offset: 0x414) (/W 32) Host Global Interrupt Disable Register -------- */
+
+#define HSTIDR_OFFSET                 (0x414)                                       /**<  (HSTIDR) Host Global Interrupt Disable Register  Offset */
+
+#define HSTIDR_DCONNIEC_Pos           0                                              /**< (HSTIDR) Device Connection Interrupt Disable Position */
+#define HSTIDR_DCONNIEC               (_U_(0x1) << HSTIDR_DCONNIEC_Pos)        /**< (HSTIDR) Device Connection Interrupt Disable Mask */
+#define HSTIDR_DDISCIEC_Pos           1                                              /**< (HSTIDR) Device Disconnection Interrupt Disable Position */
+#define HSTIDR_DDISCIEC               (_U_(0x1) << HSTIDR_DDISCIEC_Pos)        /**< (HSTIDR) Device Disconnection Interrupt Disable Mask */
+#define HSTIDR_RSTIEC_Pos             2                                              /**< (HSTIDR) USB Reset Sent Interrupt Disable Position */
+#define HSTIDR_RSTIEC                 (_U_(0x1) << HSTIDR_RSTIEC_Pos)          /**< (HSTIDR) USB Reset Sent Interrupt Disable Mask */
+#define HSTIDR_RSMEDIEC_Pos           3                                              /**< (HSTIDR) Downstream Resume Sent Interrupt Disable Position */
+#define HSTIDR_RSMEDIEC               (_U_(0x1) << HSTIDR_RSMEDIEC_Pos)        /**< (HSTIDR) Downstream Resume Sent Interrupt Disable Mask */
+#define HSTIDR_RXRSMIEC_Pos           4                                              /**< (HSTIDR) Upstream Resume Received Interrupt Disable Position */
+#define HSTIDR_RXRSMIEC               (_U_(0x1) << HSTIDR_RXRSMIEC_Pos)        /**< (HSTIDR) Upstream Resume Received Interrupt Disable Mask */
+#define HSTIDR_HSOFIEC_Pos            5                                              /**< (HSTIDR) Host Start of Frame Interrupt Disable Position */
+#define HSTIDR_HSOFIEC                (_U_(0x1) << HSTIDR_HSOFIEC_Pos)         /**< (HSTIDR) Host Start of Frame Interrupt Disable Mask */
+#define HSTIDR_HWUPIEC_Pos            6                                              /**< (HSTIDR) Host Wake-Up Interrupt Disable Position */
+#define HSTIDR_HWUPIEC                (_U_(0x1) << HSTIDR_HWUPIEC_Pos)         /**< (HSTIDR) Host Wake-Up Interrupt Disable Mask */
+#define HSTIDR_PEP_0_Pos              8                                              /**< (HSTIDR) Pipe 0 Interrupt Disable Position */
+#define HSTIDR_PEP_0                  (_U_(0x1) << HSTIDR_PEP_0_Pos)           /**< (HSTIDR) Pipe 0 Interrupt Disable Mask */
+#define HSTIDR_PEP_1_Pos              9                                              /**< (HSTIDR) Pipe 1 Interrupt Disable Position */
+#define HSTIDR_PEP_1                  (_U_(0x1) << HSTIDR_PEP_1_Pos)           /**< (HSTIDR) Pipe 1 Interrupt Disable Mask */
+#define HSTIDR_PEP_2_Pos              10                                             /**< (HSTIDR) Pipe 2 Interrupt Disable Position */
+#define HSTIDR_PEP_2                  (_U_(0x1) << HSTIDR_PEP_2_Pos)           /**< (HSTIDR) Pipe 2 Interrupt Disable Mask */
+#define HSTIDR_PEP_3_Pos              11                                             /**< (HSTIDR) Pipe 3 Interrupt Disable Position */
+#define HSTIDR_PEP_3                  (_U_(0x1) << HSTIDR_PEP_3_Pos)           /**< (HSTIDR) Pipe 3 Interrupt Disable Mask */
+#define HSTIDR_PEP_4_Pos              12                                             /**< (HSTIDR) Pipe 4 Interrupt Disable Position */
+#define HSTIDR_PEP_4                  (_U_(0x1) << HSTIDR_PEP_4_Pos)           /**< (HSTIDR) Pipe 4 Interrupt Disable Mask */
+#define HSTIDR_PEP_5_Pos              13                                             /**< (HSTIDR) Pipe 5 Interrupt Disable Position */
+#define HSTIDR_PEP_5                  (_U_(0x1) << HSTIDR_PEP_5_Pos)           /**< (HSTIDR) Pipe 5 Interrupt Disable Mask */
+#define HSTIDR_PEP_6_Pos              14                                             /**< (HSTIDR) Pipe 6 Interrupt Disable Position */
+#define HSTIDR_PEP_6                  (_U_(0x1) << HSTIDR_PEP_6_Pos)           /**< (HSTIDR) Pipe 6 Interrupt Disable Mask */
+#define HSTIDR_PEP_7_Pos              15                                             /**< (HSTIDR) Pipe 7 Interrupt Disable Position */
+#define HSTIDR_PEP_7                  (_U_(0x1) << HSTIDR_PEP_7_Pos)           /**< (HSTIDR) Pipe 7 Interrupt Disable Mask */
+#define HSTIDR_PEP_8_Pos              16                                             /**< (HSTIDR) Pipe 8 Interrupt Disable Position */
+#define HSTIDR_PEP_8                  (_U_(0x1) << HSTIDR_PEP_8_Pos)           /**< (HSTIDR) Pipe 8 Interrupt Disable Mask */
+#define HSTIDR_PEP_9_Pos              17                                             /**< (HSTIDR) Pipe 9 Interrupt Disable Position */
+#define HSTIDR_PEP_9                  (_U_(0x1) << HSTIDR_PEP_9_Pos)           /**< (HSTIDR) Pipe 9 Interrupt Disable Mask */
+#define HSTIDR_DMA_0_Pos              25                                             /**< (HSTIDR) DMA Channel 0 Interrupt Disable Position */
+#define HSTIDR_DMA_0                  (_U_(0x1) << HSTIDR_DMA_0_Pos)           /**< (HSTIDR) DMA Channel 0 Interrupt Disable Mask */
+#define HSTIDR_DMA_1_Pos              26                                             /**< (HSTIDR) DMA Channel 1 Interrupt Disable Position */
+#define HSTIDR_DMA_1                  (_U_(0x1) << HSTIDR_DMA_1_Pos)           /**< (HSTIDR) DMA Channel 1 Interrupt Disable Mask */
+#define HSTIDR_DMA_2_Pos              27                                             /**< (HSTIDR) DMA Channel 2 Interrupt Disable Position */
+#define HSTIDR_DMA_2                  (_U_(0x1) << HSTIDR_DMA_2_Pos)           /**< (HSTIDR) DMA Channel 2 Interrupt Disable Mask */
+#define HSTIDR_DMA_3_Pos              28                                             /**< (HSTIDR) DMA Channel 3 Interrupt Disable Position */
+#define HSTIDR_DMA_3                  (_U_(0x1) << HSTIDR_DMA_3_Pos)           /**< (HSTIDR) DMA Channel 3 Interrupt Disable Mask */
+#define HSTIDR_DMA_4_Pos              29                                             /**< (HSTIDR) DMA Channel 4 Interrupt Disable Position */
+#define HSTIDR_DMA_4                  (_U_(0x1) << HSTIDR_DMA_4_Pos)           /**< (HSTIDR) DMA Channel 4 Interrupt Disable Mask */
+#define HSTIDR_DMA_5_Pos              30                                             /**< (HSTIDR) DMA Channel 5 Interrupt Disable Position */
+#define HSTIDR_DMA_5                  (_U_(0x1) << HSTIDR_DMA_5_Pos)           /**< (HSTIDR) DMA Channel 5 Interrupt Disable Mask */
+#define HSTIDR_DMA_6_Pos              31                                             /**< (HSTIDR) DMA Channel 6 Interrupt Disable Position */
+#define HSTIDR_DMA_6                  (_U_(0x1) << HSTIDR_DMA_6_Pos)           /**< (HSTIDR) DMA Channel 6 Interrupt Disable Mask */
+#define HSTIDR_Msk                    _U_(0xFE03FF7F)                                /**< (HSTIDR) Register Mask  */
+
+#define HSTIDR_PEP__Pos               8                                              /**< (HSTIDR Position) Pipe x Interrupt Disable */
+#define HSTIDR_PEP_                   (_U_(0x3FF) << HSTIDR_PEP__Pos)          /**< (HSTIDR Mask) PEP_ */
+#define HSTIDR_DMA__Pos               25                                             /**< (HSTIDR Position) DMA Channel 6 Interrupt Disable */
+#define HSTIDR_DMA_                   (_U_(0x7F) << HSTIDR_DMA__Pos)           /**< (HSTIDR Mask) DMA_ */
+
+/* -------- HSTIER : (USBHS Offset: 0x418) (/W 32) Host Global Interrupt Enable Register -------- */
+
+#define HSTIER_OFFSET                 (0x418)                                       /**<  (HSTIER) Host Global Interrupt Enable Register  Offset */
+
+#define HSTIER_DCONNIES_Pos           0                                              /**< (HSTIER) Device Connection Interrupt Enable Position */
+#define HSTIER_DCONNIES               (_U_(0x1) << HSTIER_DCONNIES_Pos)        /**< (HSTIER) Device Connection Interrupt Enable Mask */
+#define HSTIER_DDISCIES_Pos           1                                              /**< (HSTIER) Device Disconnection Interrupt Enable Position */
+#define HSTIER_DDISCIES               (_U_(0x1) << HSTIER_DDISCIES_Pos)        /**< (HSTIER) Device Disconnection Interrupt Enable Mask */
+#define HSTIER_RSTIES_Pos             2                                              /**< (HSTIER) USB Reset Sent Interrupt Enable Position */
+#define HSTIER_RSTIES                 (_U_(0x1) << HSTIER_RSTIES_Pos)          /**< (HSTIER) USB Reset Sent Interrupt Enable Mask */
+#define HSTIER_RSMEDIES_Pos           3                                              /**< (HSTIER) Downstream Resume Sent Interrupt Enable Position */
+#define HSTIER_RSMEDIES               (_U_(0x1) << HSTIER_RSMEDIES_Pos)        /**< (HSTIER) Downstream Resume Sent Interrupt Enable Mask */
+#define HSTIER_RXRSMIES_Pos           4                                              /**< (HSTIER) Upstream Resume Received Interrupt Enable Position */
+#define HSTIER_RXRSMIES               (_U_(0x1) << HSTIER_RXRSMIES_Pos)        /**< (HSTIER) Upstream Resume Received Interrupt Enable Mask */
+#define HSTIER_HSOFIES_Pos            5                                              /**< (HSTIER) Host Start of Frame Interrupt Enable Position */
+#define HSTIER_HSOFIES                (_U_(0x1) << HSTIER_HSOFIES_Pos)         /**< (HSTIER) Host Start of Frame Interrupt Enable Mask */
+#define HSTIER_HWUPIES_Pos            6                                              /**< (HSTIER) Host Wake-Up Interrupt Enable Position */
+#define HSTIER_HWUPIES                (_U_(0x1) << HSTIER_HWUPIES_Pos)         /**< (HSTIER) Host Wake-Up Interrupt Enable Mask */
+#define HSTIER_PEP_0_Pos              8                                              /**< (HSTIER) Pipe 0 Interrupt Enable Position */
+#define HSTIER_PEP_0                  (_U_(0x1) << HSTIER_PEP_0_Pos)           /**< (HSTIER) Pipe 0 Interrupt Enable Mask */
+#define HSTIER_PEP_1_Pos              9                                              /**< (HSTIER) Pipe 1 Interrupt Enable Position */
+#define HSTIER_PEP_1                  (_U_(0x1) << HSTIER_PEP_1_Pos)           /**< (HSTIER) Pipe 1 Interrupt Enable Mask */
+#define HSTIER_PEP_2_Pos              10                                             /**< (HSTIER) Pipe 2 Interrupt Enable Position */
+#define HSTIER_PEP_2                  (_U_(0x1) << HSTIER_PEP_2_Pos)           /**< (HSTIER) Pipe 2 Interrupt Enable Mask */
+#define HSTIER_PEP_3_Pos              11                                             /**< (HSTIER) Pipe 3 Interrupt Enable Position */
+#define HSTIER_PEP_3                  (_U_(0x1) << HSTIER_PEP_3_Pos)           /**< (HSTIER) Pipe 3 Interrupt Enable Mask */
+#define HSTIER_PEP_4_Pos              12                                             /**< (HSTIER) Pipe 4 Interrupt Enable Position */
+#define HSTIER_PEP_4                  (_U_(0x1) << HSTIER_PEP_4_Pos)           /**< (HSTIER) Pipe 4 Interrupt Enable Mask */
+#define HSTIER_PEP_5_Pos              13                                             /**< (HSTIER) Pipe 5 Interrupt Enable Position */
+#define HSTIER_PEP_5                  (_U_(0x1) << HSTIER_PEP_5_Pos)           /**< (HSTIER) Pipe 5 Interrupt Enable Mask */
+#define HSTIER_PEP_6_Pos              14                                             /**< (HSTIER) Pipe 6 Interrupt Enable Position */
+#define HSTIER_PEP_6                  (_U_(0x1) << HSTIER_PEP_6_Pos)           /**< (HSTIER) Pipe 6 Interrupt Enable Mask */
+#define HSTIER_PEP_7_Pos              15                                             /**< (HSTIER) Pipe 7 Interrupt Enable Position */
+#define HSTIER_PEP_7                  (_U_(0x1) << HSTIER_PEP_7_Pos)           /**< (HSTIER) Pipe 7 Interrupt Enable Mask */
+#define HSTIER_PEP_8_Pos              16                                             /**< (HSTIER) Pipe 8 Interrupt Enable Position */
+#define HSTIER_PEP_8                  (_U_(0x1) << HSTIER_PEP_8_Pos)           /**< (HSTIER) Pipe 8 Interrupt Enable Mask */
+#define HSTIER_PEP_9_Pos              17                                             /**< (HSTIER) Pipe 9 Interrupt Enable Position */
+#define HSTIER_PEP_9                  (_U_(0x1) << HSTIER_PEP_9_Pos)           /**< (HSTIER) Pipe 9 Interrupt Enable Mask */
+#define HSTIER_DMA_0_Pos              25                                             /**< (HSTIER) DMA Channel 0 Interrupt Enable Position */
+#define HSTIER_DMA_0                  (_U_(0x1) << HSTIER_DMA_0_Pos)           /**< (HSTIER) DMA Channel 0 Interrupt Enable Mask */
+#define HSTIER_DMA_1_Pos              26                                             /**< (HSTIER) DMA Channel 1 Interrupt Enable Position */
+#define HSTIER_DMA_1                  (_U_(0x1) << HSTIER_DMA_1_Pos)           /**< (HSTIER) DMA Channel 1 Interrupt Enable Mask */
+#define HSTIER_DMA_2_Pos              27                                             /**< (HSTIER) DMA Channel 2 Interrupt Enable Position */
+#define HSTIER_DMA_2                  (_U_(0x1) << HSTIER_DMA_2_Pos)           /**< (HSTIER) DMA Channel 2 Interrupt Enable Mask */
+#define HSTIER_DMA_3_Pos              28                                             /**< (HSTIER) DMA Channel 3 Interrupt Enable Position */
+#define HSTIER_DMA_3                  (_U_(0x1) << HSTIER_DMA_3_Pos)           /**< (HSTIER) DMA Channel 3 Interrupt Enable Mask */
+#define HSTIER_DMA_4_Pos              29                                             /**< (HSTIER) DMA Channel 4 Interrupt Enable Position */
+#define HSTIER_DMA_4                  (_U_(0x1) << HSTIER_DMA_4_Pos)           /**< (HSTIER) DMA Channel 4 Interrupt Enable Mask */
+#define HSTIER_DMA_5_Pos              30                                             /**< (HSTIER) DMA Channel 5 Interrupt Enable Position */
+#define HSTIER_DMA_5                  (_U_(0x1) << HSTIER_DMA_5_Pos)           /**< (HSTIER) DMA Channel 5 Interrupt Enable Mask */
+#define HSTIER_DMA_6_Pos              31                                             /**< (HSTIER) DMA Channel 6 Interrupt Enable Position */
+#define HSTIER_DMA_6                  (_U_(0x1) << HSTIER_DMA_6_Pos)           /**< (HSTIER) DMA Channel 6 Interrupt Enable Mask */
+#define HSTIER_Msk                    _U_(0xFE03FF7F)                                /**< (HSTIER) Register Mask  */
+
+#define HSTIER_PEP__Pos               8                                              /**< (HSTIER Position) Pipe x Interrupt Enable */
+#define HSTIER_PEP_                   (_U_(0x3FF) << HSTIER_PEP__Pos)          /**< (HSTIER Mask) PEP_ */
+#define HSTIER_DMA__Pos               25                                             /**< (HSTIER Position) DMA Channel 6 Interrupt Enable */
+#define HSTIER_DMA_                   (_U_(0x7F) << HSTIER_DMA__Pos)           /**< (HSTIER Mask) DMA_ */
+
+/* -------- HSTPIP : (USBHS Offset: 0x41c) (R/W 32) Host Pipe Register -------- */
+
+#define HSTPIP_OFFSET                 (0x41C)                                       /**<  (HSTPIP) Host Pipe Register  Offset */
+
+#define HSTPIP_PEN0_Pos               0                                              /**< (HSTPIP) Pipe 0 Enable Position */
+#define HSTPIP_PEN0                   (_U_(0x1) << HSTPIP_PEN0_Pos)            /**< (HSTPIP) Pipe 0 Enable Mask */
+#define HSTPIP_PEN1_Pos               1                                              /**< (HSTPIP) Pipe 1 Enable Position */
+#define HSTPIP_PEN1                   (_U_(0x1) << HSTPIP_PEN1_Pos)            /**< (HSTPIP) Pipe 1 Enable Mask */
+#define HSTPIP_PEN2_Pos               2                                              /**< (HSTPIP) Pipe 2 Enable Position */
+#define HSTPIP_PEN2                   (_U_(0x1) << HSTPIP_PEN2_Pos)            /**< (HSTPIP) Pipe 2 Enable Mask */
+#define HSTPIP_PEN3_Pos               3                                              /**< (HSTPIP) Pipe 3 Enable Position */
+#define HSTPIP_PEN3                   (_U_(0x1) << HSTPIP_PEN3_Pos)            /**< (HSTPIP) Pipe 3 Enable Mask */
+#define HSTPIP_PEN4_Pos               4                                              /**< (HSTPIP) Pipe 4 Enable Position */
+#define HSTPIP_PEN4                   (_U_(0x1) << HSTPIP_PEN4_Pos)            /**< (HSTPIP) Pipe 4 Enable Mask */
+#define HSTPIP_PEN5_Pos               5                                              /**< (HSTPIP) Pipe 5 Enable Position */
+#define HSTPIP_PEN5                   (_U_(0x1) << HSTPIP_PEN5_Pos)            /**< (HSTPIP) Pipe 5 Enable Mask */
+#define HSTPIP_PEN6_Pos               6                                              /**< (HSTPIP) Pipe 6 Enable Position */
+#define HSTPIP_PEN6                   (_U_(0x1) << HSTPIP_PEN6_Pos)            /**< (HSTPIP) Pipe 6 Enable Mask */
+#define HSTPIP_PEN7_Pos               7                                              /**< (HSTPIP) Pipe 7 Enable Position */
+#define HSTPIP_PEN7                   (_U_(0x1) << HSTPIP_PEN7_Pos)            /**< (HSTPIP) Pipe 7 Enable Mask */
+#define HSTPIP_PEN8_Pos               8                                              /**< (HSTPIP) Pipe 8 Enable Position */
+#define HSTPIP_PEN8                   (_U_(0x1) << HSTPIP_PEN8_Pos)            /**< (HSTPIP) Pipe 8 Enable Mask */
+#define HSTPIP_PRST0_Pos              16                                             /**< (HSTPIP) Pipe 0 Reset Position */
+#define HSTPIP_PRST0                  (_U_(0x1) << HSTPIP_PRST0_Pos)           /**< (HSTPIP) Pipe 0 Reset Mask */
+#define HSTPIP_PRST1_Pos              17                                             /**< (HSTPIP) Pipe 1 Reset Position */
+#define HSTPIP_PRST1                  (_U_(0x1) << HSTPIP_PRST1_Pos)           /**< (HSTPIP) Pipe 1 Reset Mask */
+#define HSTPIP_PRST2_Pos              18                                             /**< (HSTPIP) Pipe 2 Reset Position */
+#define HSTPIP_PRST2                  (_U_(0x1) << HSTPIP_PRST2_Pos)           /**< (HSTPIP) Pipe 2 Reset Mask */
+#define HSTPIP_PRST3_Pos              19                                             /**< (HSTPIP) Pipe 3 Reset Position */
+#define HSTPIP_PRST3                  (_U_(0x1) << HSTPIP_PRST3_Pos)           /**< (HSTPIP) Pipe 3 Reset Mask */
+#define HSTPIP_PRST4_Pos              20                                             /**< (HSTPIP) Pipe 4 Reset Position */
+#define HSTPIP_PRST4                  (_U_(0x1) << HSTPIP_PRST4_Pos)           /**< (HSTPIP) Pipe 4 Reset Mask */
+#define HSTPIP_PRST5_Pos              21                                             /**< (HSTPIP) Pipe 5 Reset Position */
+#define HSTPIP_PRST5                  (_U_(0x1) << HSTPIP_PRST5_Pos)           /**< (HSTPIP) Pipe 5 Reset Mask */
+#define HSTPIP_PRST6_Pos              22                                             /**< (HSTPIP) Pipe 6 Reset Position */
+#define HSTPIP_PRST6                  (_U_(0x1) << HSTPIP_PRST6_Pos)           /**< (HSTPIP) Pipe 6 Reset Mask */
+#define HSTPIP_PRST7_Pos              23                                             /**< (HSTPIP) Pipe 7 Reset Position */
+#define HSTPIP_PRST7                  (_U_(0x1) << HSTPIP_PRST7_Pos)           /**< (HSTPIP) Pipe 7 Reset Mask */
+#define HSTPIP_PRST8_Pos              24                                             /**< (HSTPIP) Pipe 8 Reset Position */
+#define HSTPIP_PRST8                  (_U_(0x1) << HSTPIP_PRST8_Pos)           /**< (HSTPIP) Pipe 8 Reset Mask */
+#define HSTPIP_Msk                    _U_(0x1FF01FF)                                 /**< (HSTPIP) Register Mask  */
+
+#define HSTPIP_PEN_Pos                0                                              /**< (HSTPIP Position) Pipe x Enable */
+#define HSTPIP_PEN                    (_U_(0x1FF) << HSTPIP_PEN_Pos)           /**< (HSTPIP Mask) PEN */
+#define HSTPIP_PRST_Pos               16                                             /**< (HSTPIP Position) Pipe 8 Reset */
+#define HSTPIP_PRST                   (_U_(0x1FF) << HSTPIP_PRST_Pos)          /**< (HSTPIP Mask) PRST */
+
+/* -------- HSTFNUM : (USBHS Offset: 0x420) (R/W 32) Host Frame Number Register -------- */
+
+#define HSTFNUM_OFFSET                (0x420)                                       /**<  (HSTFNUM) Host Frame Number Register  Offset */
+
+#define HSTFNUM_MFNUM_Pos             0                                              /**< (HSTFNUM) Micro Frame Number Position */
+#define HSTFNUM_MFNUM                 (_U_(0x7) << HSTFNUM_MFNUM_Pos)          /**< (HSTFNUM) Micro Frame Number Mask */
+#define HSTFNUM_FNUM_Pos              3                                              /**< (HSTFNUM) Frame Number Position */
+#define HSTFNUM_FNUM                  (_U_(0x7FF) << HSTFNUM_FNUM_Pos)         /**< (HSTFNUM) Frame Number Mask */
+#define HSTFNUM_FLENHIGH_Pos          16                                             /**< (HSTFNUM) Frame Length Position */
+#define HSTFNUM_FLENHIGH              (_U_(0xFF) << HSTFNUM_FLENHIGH_Pos)      /**< (HSTFNUM) Frame Length Mask */
+#define HSTFNUM_Msk                   _U_(0xFF3FFF)                                  /**< (HSTFNUM) Register Mask  */
+
+
+/* -------- HSTADDR1 : (USBHS Offset: 0x424) (R/W 32) Host Address 1 Register -------- */
+
+#define HSTADDR1_OFFSET               (0x424)                                       /**<  (HSTADDR1) Host Address 1 Register  Offset */
+
+#define HSTADDR1_HSTADDRP0_Pos        0                                              /**< (HSTADDR1) USB Host Address Position */
+#define HSTADDR1_HSTADDRP0            (_U_(0x7F) << HSTADDR1_HSTADDRP0_Pos)    /**< (HSTADDR1) USB Host Address Mask */
+#define HSTADDR1_HSTADDRP1_Pos        8                                              /**< (HSTADDR1) USB Host Address Position */
+#define HSTADDR1_HSTADDRP1            (_U_(0x7F) << HSTADDR1_HSTADDRP1_Pos)    /**< (HSTADDR1) USB Host Address Mask */
+#define HSTADDR1_HSTADDRP2_Pos        16                                             /**< (HSTADDR1) USB Host Address Position */
+#define HSTADDR1_HSTADDRP2            (_U_(0x7F) << HSTADDR1_HSTADDRP2_Pos)    /**< (HSTADDR1) USB Host Address Mask */
+#define HSTADDR1_HSTADDRP3_Pos        24                                             /**< (HSTADDR1) USB Host Address Position */
+#define HSTADDR1_HSTADDRP3            (_U_(0x7F) << HSTADDR1_HSTADDRP3_Pos)    /**< (HSTADDR1) USB Host Address Mask */
+#define HSTADDR1_Msk                  _U_(0x7F7F7F7F)                                /**< (HSTADDR1) Register Mask  */
+
+
+/* -------- HSTADDR2 : (USBHS Offset: 0x428) (R/W 32) Host Address 2 Register -------- */
+
+#define HSTADDR2_OFFSET               (0x428)                                       /**<  (HSTADDR2) Host Address 2 Register  Offset */
+
+#define HSTADDR2_HSTADDRP4_Pos        0                                              /**< (HSTADDR2) USB Host Address Position */
+#define HSTADDR2_HSTADDRP4            (_U_(0x7F) << HSTADDR2_HSTADDRP4_Pos)    /**< (HSTADDR2) USB Host Address Mask */
+#define HSTADDR2_HSTADDRP5_Pos        8                                              /**< (HSTADDR2) USB Host Address Position */
+#define HSTADDR2_HSTADDRP5            (_U_(0x7F) << HSTADDR2_HSTADDRP5_Pos)    /**< (HSTADDR2) USB Host Address Mask */
+#define HSTADDR2_HSTADDRP6_Pos        16                                             /**< (HSTADDR2) USB Host Address Position */
+#define HSTADDR2_HSTADDRP6            (_U_(0x7F) << HSTADDR2_HSTADDRP6_Pos)    /**< (HSTADDR2) USB Host Address Mask */
+#define HSTADDR2_HSTADDRP7_Pos        24                                             /**< (HSTADDR2) USB Host Address Position */
+#define HSTADDR2_HSTADDRP7            (_U_(0x7F) << HSTADDR2_HSTADDRP7_Pos)    /**< (HSTADDR2) USB Host Address Mask */
+#define HSTADDR2_Msk                  _U_(0x7F7F7F7F)                                /**< (HSTADDR2) Register Mask  */
+
+
+/* -------- HSTADDR3 : (USBHS Offset: 0x42c) (R/W 32) Host Address 3 Register -------- */
+
+#define HSTADDR3_OFFSET               (0x42C)                                       /**<  (HSTADDR3) Host Address 3 Register  Offset */
+
+#define HSTADDR3_HSTADDRP8_Pos        0                                              /**< (HSTADDR3) USB Host Address Position */
+#define HSTADDR3_HSTADDRP8            (_U_(0x7F) << HSTADDR3_HSTADDRP8_Pos)    /**< (HSTADDR3) USB Host Address Mask */
+#define HSTADDR3_HSTADDRP9_Pos        8                                              /**< (HSTADDR3) USB Host Address Position */
+#define HSTADDR3_HSTADDRP9            (_U_(0x7F) << HSTADDR3_HSTADDRP9_Pos)    /**< (HSTADDR3) USB Host Address Mask */
+#define HSTADDR3_Msk                  _U_(0x7F7F)                                    /**< (HSTADDR3) Register Mask  */
+
+
+/* -------- HSTPIPCFG : (USBHS Offset: 0x500) (R/W 32) Host Pipe Configuration Register -------- */
+
+#define HSTPIPCFG_OFFSET              (0x500)                                       /**<  (HSTPIPCFG) Host Pipe Configuration Register  Offset */
+
+#define HSTPIPCFG_ALLOC_Pos           1                                              /**< (HSTPIPCFG) Pipe Memory Allocate Position */
+#define HSTPIPCFG_ALLOC               (_U_(0x1) << HSTPIPCFG_ALLOC_Pos)        /**< (HSTPIPCFG) Pipe Memory Allocate Mask */
+#define HSTPIPCFG_PBK_Pos             2                                              /**< (HSTPIPCFG) Pipe Banks Position */
+#define HSTPIPCFG_PBK                 (_U_(0x3) << HSTPIPCFG_PBK_Pos)          /**< (HSTPIPCFG) Pipe Banks Mask */
+#define   HSTPIPCFG_PBK_1_BANK_Val    _U_(0x0)                                       /**< (HSTPIPCFG) Single-bank pipe  */
+#define   HSTPIPCFG_PBK_2_BANK_Val    _U_(0x1)                                       /**< (HSTPIPCFG) Double-bank pipe  */
+#define   HSTPIPCFG_PBK_3_BANK_Val    _U_(0x2)                                       /**< (HSTPIPCFG) Triple-bank pipe  */
+#define HSTPIPCFG_PBK_1_BANK          (HSTPIPCFG_PBK_1_BANK_Val << HSTPIPCFG_PBK_Pos)  /**< (HSTPIPCFG) Single-bank pipe Position  */
+#define HSTPIPCFG_PBK_2_BANK          (HSTPIPCFG_PBK_2_BANK_Val << HSTPIPCFG_PBK_Pos)  /**< (HSTPIPCFG) Double-bank pipe Position  */
+#define HSTPIPCFG_PBK_3_BANK          (HSTPIPCFG_PBK_3_BANK_Val << HSTPIPCFG_PBK_Pos)  /**< (HSTPIPCFG) Triple-bank pipe Position  */
+#define HSTPIPCFG_PSIZE_Pos           4                                              /**< (HSTPIPCFG) Pipe Size Position */
+#define HSTPIPCFG_PSIZE               (_U_(0x7) << HSTPIPCFG_PSIZE_Pos)        /**< (HSTPIPCFG) Pipe Size Mask */
+#define   HSTPIPCFG_PSIZE_8_BYTE_Val  _U_(0x0)                                       /**< (HSTPIPCFG) 8 bytes  */
+#define   HSTPIPCFG_PSIZE_16_BYTE_Val _U_(0x1)                                       /**< (HSTPIPCFG) 16 bytes  */
+#define   HSTPIPCFG_PSIZE_32_BYTE_Val _U_(0x2)                                       /**< (HSTPIPCFG) 32 bytes  */
+#define   HSTPIPCFG_PSIZE_64_BYTE_Val _U_(0x3)                                       /**< (HSTPIPCFG) 64 bytes  */
+#define   HSTPIPCFG_PSIZE_128_BYTE_Val _U_(0x4)                                       /**< (HSTPIPCFG) 128 bytes  */
+#define   HSTPIPCFG_PSIZE_256_BYTE_Val _U_(0x5)                                       /**< (HSTPIPCFG) 256 bytes  */
+#define   HSTPIPCFG_PSIZE_512_BYTE_Val _U_(0x6)                                       /**< (HSTPIPCFG) 512 bytes  */
+#define   HSTPIPCFG_PSIZE_1024_BYTE_Val _U_(0x7)                                       /**< (HSTPIPCFG) 1024 bytes  */
+#define HSTPIPCFG_PSIZE_8_BYTE        (HSTPIPCFG_PSIZE_8_BYTE_Val << HSTPIPCFG_PSIZE_Pos)  /**< (HSTPIPCFG) 8 bytes Position  */
+#define HSTPIPCFG_PSIZE_16_BYTE       (HSTPIPCFG_PSIZE_16_BYTE_Val << HSTPIPCFG_PSIZE_Pos)  /**< (HSTPIPCFG) 16 bytes Position  */
+#define HSTPIPCFG_PSIZE_32_BYTE       (HSTPIPCFG_PSIZE_32_BYTE_Val << HSTPIPCFG_PSIZE_Pos)  /**< (HSTPIPCFG) 32 bytes Position  */
+#define HSTPIPCFG_PSIZE_64_BYTE       (HSTPIPCFG_PSIZE_64_BYTE_Val << HSTPIPCFG_PSIZE_Pos)  /**< (HSTPIPCFG) 64 bytes Position  */
+#define HSTPIPCFG_PSIZE_128_BYTE      (HSTPIPCFG_PSIZE_128_BYTE_Val << HSTPIPCFG_PSIZE_Pos)  /**< (HSTPIPCFG) 128 bytes Position  */
+#define HSTPIPCFG_PSIZE_256_BYTE      (HSTPIPCFG_PSIZE_256_BYTE_Val << HSTPIPCFG_PSIZE_Pos)  /**< (HSTPIPCFG) 256 bytes Position  */
+#define HSTPIPCFG_PSIZE_512_BYTE      (HSTPIPCFG_PSIZE_512_BYTE_Val << HSTPIPCFG_PSIZE_Pos)  /**< (HSTPIPCFG) 512 bytes Position  */
+#define HSTPIPCFG_PSIZE_1024_BYTE     (HSTPIPCFG_PSIZE_1024_BYTE_Val << HSTPIPCFG_PSIZE_Pos)  /**< (HSTPIPCFG) 1024 bytes Position  */
+#define HSTPIPCFG_PTOKEN_Pos          8                                              /**< (HSTPIPCFG) Pipe Token Position */
+#define HSTPIPCFG_PTOKEN              (_U_(0x3) << HSTPIPCFG_PTOKEN_Pos)       /**< (HSTPIPCFG) Pipe Token Mask */
+#define   HSTPIPCFG_PTOKEN_SETUP_Val  _U_(0x0)                                       /**< (HSTPIPCFG) SETUP  */
+#define   HSTPIPCFG_PTOKEN_IN_Val     _U_(0x1)                                       /**< (HSTPIPCFG) IN  */
+#define   HSTPIPCFG_PTOKEN_OUT_Val    _U_(0x2)                                       /**< (HSTPIPCFG) OUT  */
+#define HSTPIPCFG_PTOKEN_SETUP        (HSTPIPCFG_PTOKEN_SETUP_Val << HSTPIPCFG_PTOKEN_Pos)  /**< (HSTPIPCFG) SETUP Position  */
+#define HSTPIPCFG_PTOKEN_IN           (HSTPIPCFG_PTOKEN_IN_Val << HSTPIPCFG_PTOKEN_Pos)  /**< (HSTPIPCFG) IN Position  */
+#define HSTPIPCFG_PTOKEN_OUT          (HSTPIPCFG_PTOKEN_OUT_Val << HSTPIPCFG_PTOKEN_Pos)  /**< (HSTPIPCFG) OUT Position  */
+#define HSTPIPCFG_AUTOSW_Pos          10                                             /**< (HSTPIPCFG) Automatic Switch Position */
+#define HSTPIPCFG_AUTOSW              (_U_(0x1) << HSTPIPCFG_AUTOSW_Pos)       /**< (HSTPIPCFG) Automatic Switch Mask */
+#define HSTPIPCFG_PTYPE_Pos           12                                             /**< (HSTPIPCFG) Pipe Type Position */
+#define HSTPIPCFG_PTYPE               (_U_(0x3) << HSTPIPCFG_PTYPE_Pos)        /**< (HSTPIPCFG) Pipe Type Mask */
+#define   HSTPIPCFG_PTYPE_CTRL_Val    _U_(0x0)                                       /**< (HSTPIPCFG) Control  */
+#define   HSTPIPCFG_PTYPE_ISO_Val     _U_(0x1)                                       /**< (HSTPIPCFG) Isochronous  */
+#define   HSTPIPCFG_PTYPE_BLK_Val     _U_(0x2)                                       /**< (HSTPIPCFG) Bulk  */
+#define   HSTPIPCFG_PTYPE_INTRPT_Val  _U_(0x3)                                       /**< (HSTPIPCFG) Interrupt  */
+#define HSTPIPCFG_PTYPE_CTRL          (HSTPIPCFG_PTYPE_CTRL_Val << HSTPIPCFG_PTYPE_Pos)  /**< (HSTPIPCFG) Control Position  */
+#define HSTPIPCFG_PTYPE_ISO           (HSTPIPCFG_PTYPE_ISO_Val << HSTPIPCFG_PTYPE_Pos)  /**< (HSTPIPCFG) Isochronous Position  */
+#define HSTPIPCFG_PTYPE_BLK           (HSTPIPCFG_PTYPE_BLK_Val << HSTPIPCFG_PTYPE_Pos)  /**< (HSTPIPCFG) Bulk Position  */
+#define HSTPIPCFG_PTYPE_INTRPT        (HSTPIPCFG_PTYPE_INTRPT_Val << HSTPIPCFG_PTYPE_Pos)  /**< (HSTPIPCFG) Interrupt Position  */
+#define HSTPIPCFG_PEPNUM_Pos          16                                             /**< (HSTPIPCFG) Pipe Endpoint Number Position */
+#define HSTPIPCFG_PEPNUM              (_U_(0xF) << HSTPIPCFG_PEPNUM_Pos)       /**< (HSTPIPCFG) Pipe Endpoint Number Mask */
+#define HSTPIPCFG_INTFRQ_Pos          24                                             /**< (HSTPIPCFG) Pipe Interrupt Request Frequency Position */
+#define HSTPIPCFG_INTFRQ              (_U_(0xFF) << HSTPIPCFG_INTFRQ_Pos)      /**< (HSTPIPCFG) Pipe Interrupt Request Frequency Mask */
+#define HSTPIPCFG_Msk                 _U_(0xFF0F377E)                                /**< (HSTPIPCFG) Register Mask  */
+
+/* CTRL_BULK mode */
+#define HSTPIPCFG_CTRL_BULK_PINGEN_Pos 20                                             /**< (HSTPIPCFG) Ping Enable Position */
+#define HSTPIPCFG_CTRL_BULK_PINGEN     (_U_(0x1) << HSTPIPCFG_CTRL_BULK_PINGEN_Pos)  /**< (HSTPIPCFG) Ping Enable Mask */
+#define HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos 24                                             /**< (HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Position */
+#define HSTPIPCFG_CTRL_BULK_BINTERVAL     (_U_(0xFF) << HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos)  /**< (HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Mask */
+#define HSTPIPCFG_CTRL_BULK_Msk       _U_(0xFF100000)                                /**< (HSTPIPCFG_CTRL_BULK) Register Mask  */
+
+
+/* -------- HSTPIPISR : (USBHS Offset: 0x530) (R/ 32) Host Pipe Status Register -------- */
+
+#define HSTPIPISR_OFFSET              (0x530)                                       /**<  (HSTPIPISR) Host Pipe Status Register  Offset */
+
+#define HSTPIPISR_RXINI_Pos           0                                              /**< (HSTPIPISR) Received IN Data Interrupt Position */
+#define HSTPIPISR_RXINI               (_U_(0x1) << HSTPIPISR_RXINI_Pos)        /**< (HSTPIPISR) Received IN Data Interrupt Mask */
+#define HSTPIPISR_TXOUTI_Pos          1                                              /**< (HSTPIPISR) Transmitted OUT Data Interrupt Position */
+#define HSTPIPISR_TXOUTI              (_U_(0x1) << HSTPIPISR_TXOUTI_Pos)       /**< (HSTPIPISR) Transmitted OUT Data Interrupt Mask */
+#define HSTPIPISR_PERRI_Pos           3                                              /**< (HSTPIPISR) Pipe Error Interrupt Position */
+#define HSTPIPISR_PERRI               (_U_(0x1) << HSTPIPISR_PERRI_Pos)        /**< (HSTPIPISR) Pipe Error Interrupt Mask */
+#define HSTPIPISR_NAKEDI_Pos          4                                              /**< (HSTPIPISR) NAKed Interrupt Position */
+#define HSTPIPISR_NAKEDI              (_U_(0x1) << HSTPIPISR_NAKEDI_Pos)       /**< (HSTPIPISR) NAKed Interrupt Mask */
+#define HSTPIPISR_OVERFI_Pos          5                                              /**< (HSTPIPISR) Overflow Interrupt Position */
+#define HSTPIPISR_OVERFI              (_U_(0x1) << HSTPIPISR_OVERFI_Pos)       /**< (HSTPIPISR) Overflow Interrupt Mask */
+#define HSTPIPISR_SHORTPACKETI_Pos    7                                              /**< (HSTPIPISR) Short Packet Interrupt Position */
+#define HSTPIPISR_SHORTPACKETI        (_U_(0x1) << HSTPIPISR_SHORTPACKETI_Pos)  /**< (HSTPIPISR) Short Packet Interrupt Mask */
+#define HSTPIPISR_DTSEQ_Pos           8                                              /**< (HSTPIPISR) Data Toggle Sequence Position */
+#define HSTPIPISR_DTSEQ               (_U_(0x3) << HSTPIPISR_DTSEQ_Pos)        /**< (HSTPIPISR) Data Toggle Sequence Mask */
+#define   HSTPIPISR_DTSEQ_DATA0_Val   _U_(0x0)                                       /**< (HSTPIPISR) Data0 toggle sequence  */
+#define   HSTPIPISR_DTSEQ_DATA1_Val   _U_(0x1)                                       /**< (HSTPIPISR) Data1 toggle sequence  */
+#define HSTPIPISR_DTSEQ_DATA0         (HSTPIPISR_DTSEQ_DATA0_Val << HSTPIPISR_DTSEQ_Pos)  /**< (HSTPIPISR) Data0 toggle sequence Position  */
+#define HSTPIPISR_DTSEQ_DATA1         (HSTPIPISR_DTSEQ_DATA1_Val << HSTPIPISR_DTSEQ_Pos)  /**< (HSTPIPISR) Data1 toggle sequence Position  */
+#define HSTPIPISR_NBUSYBK_Pos         12                                             /**< (HSTPIPISR) Number of Busy Banks Position */
+#define HSTPIPISR_NBUSYBK             (_U_(0x3) << HSTPIPISR_NBUSYBK_Pos)      /**< (HSTPIPISR) Number of Busy Banks Mask */
+#define   HSTPIPISR_NBUSYBK_0_BUSY_Val _U_(0x0)                                       /**< (HSTPIPISR) 0 busy bank (all banks free)  */
+#define   HSTPIPISR_NBUSYBK_1_BUSY_Val _U_(0x1)                                       /**< (HSTPIPISR) 1 busy bank  */
+#define   HSTPIPISR_NBUSYBK_2_BUSY_Val _U_(0x2)                                       /**< (HSTPIPISR) 2 busy banks  */
+#define   HSTPIPISR_NBUSYBK_3_BUSY_Val _U_(0x3)                                       /**< (HSTPIPISR) 3 busy banks  */
+#define HSTPIPISR_NBUSYBK_0_BUSY      (HSTPIPISR_NBUSYBK_0_BUSY_Val << HSTPIPISR_NBUSYBK_Pos)  /**< (HSTPIPISR) 0 busy bank (all banks free) Position  */
+#define HSTPIPISR_NBUSYBK_1_BUSY      (HSTPIPISR_NBUSYBK_1_BUSY_Val << HSTPIPISR_NBUSYBK_Pos)  /**< (HSTPIPISR) 1 busy bank Position  */
+#define HSTPIPISR_NBUSYBK_2_BUSY      (HSTPIPISR_NBUSYBK_2_BUSY_Val << HSTPIPISR_NBUSYBK_Pos)  /**< (HSTPIPISR) 2 busy banks Position  */
+#define HSTPIPISR_NBUSYBK_3_BUSY      (HSTPIPISR_NBUSYBK_3_BUSY_Val << HSTPIPISR_NBUSYBK_Pos)  /**< (HSTPIPISR) 3 busy banks Position  */
+#define HSTPIPISR_CURRBK_Pos          14                                             /**< (HSTPIPISR) Current Bank Position */
+#define HSTPIPISR_CURRBK              (_U_(0x3) << HSTPIPISR_CURRBK_Pos)       /**< (HSTPIPISR) Current Bank Mask */
+#define   HSTPIPISR_CURRBK_BANK0_Val  _U_(0x0)                                       /**< (HSTPIPISR) Current bank is bank0  */
+#define   HSTPIPISR_CURRBK_BANK1_Val  _U_(0x1)                                       /**< (HSTPIPISR) Current bank is bank1  */
+#define   HSTPIPISR_CURRBK_BANK2_Val  _U_(0x2)                                       /**< (HSTPIPISR) Current bank is bank2  */
+#define HSTPIPISR_CURRBK_BANK0        (HSTPIPISR_CURRBK_BANK0_Val << HSTPIPISR_CURRBK_Pos)  /**< (HSTPIPISR) Current bank is bank0 Position  */
+#define HSTPIPISR_CURRBK_BANK1        (HSTPIPISR_CURRBK_BANK1_Val << HSTPIPISR_CURRBK_Pos)  /**< (HSTPIPISR) Current bank is bank1 Position  */
+#define HSTPIPISR_CURRBK_BANK2        (HSTPIPISR_CURRBK_BANK2_Val << HSTPIPISR_CURRBK_Pos)  /**< (HSTPIPISR) Current bank is bank2 Position  */
+#define HSTPIPISR_RWALL_Pos           16                                             /**< (HSTPIPISR) Read/Write Allowed Position */
+#define HSTPIPISR_RWALL               (_U_(0x1) << HSTPIPISR_RWALL_Pos)        /**< (HSTPIPISR) Read/Write Allowed Mask */
+#define HSTPIPISR_CFGOK_Pos           18                                             /**< (HSTPIPISR) Configuration OK Status Position */
+#define HSTPIPISR_CFGOK               (_U_(0x1) << HSTPIPISR_CFGOK_Pos)        /**< (HSTPIPISR) Configuration OK Status Mask */
+#define HSTPIPISR_PBYCT_Pos           20                                             /**< (HSTPIPISR) Pipe Byte Count Position */
+#define HSTPIPISR_PBYCT               (_U_(0x7FF) << HSTPIPISR_PBYCT_Pos)      /**< (HSTPIPISR) Pipe Byte Count Mask */
+#define HSTPIPISR_Msk                 _U_(0x7FF5F3BB)                                /**< (HSTPIPISR) Register Mask  */
+
+/* CTRL mode */
+#define HSTPIPISR_CTRL_TXSTPI_Pos     2                                              /**< (HSTPIPISR) Transmitted SETUP Interrupt Position */
+#define HSTPIPISR_CTRL_TXSTPI         (_U_(0x1) << HSTPIPISR_CTRL_TXSTPI_Pos)  /**< (HSTPIPISR) Transmitted SETUP Interrupt Mask */
+#define HSTPIPISR_CTRL_RXSTALLDI_Pos  6                                              /**< (HSTPIPISR) Received STALLed Interrupt Position */
+#define HSTPIPISR_CTRL_RXSTALLDI      (_U_(0x1) << HSTPIPISR_CTRL_RXSTALLDI_Pos)  /**< (HSTPIPISR) Received STALLed Interrupt Mask */
+#define HSTPIPISR_CTRL_Msk            _U_(0x44)                                      /**< (HSTPIPISR_CTRL) Register Mask  */
+
+/* ISO mode */
+#define HSTPIPISR_ISO_UNDERFI_Pos     2                                              /**< (HSTPIPISR) Underflow Interrupt Position */
+#define HSTPIPISR_ISO_UNDERFI         (_U_(0x1) << HSTPIPISR_ISO_UNDERFI_Pos)  /**< (HSTPIPISR) Underflow Interrupt Mask */
+#define HSTPIPISR_ISO_CRCERRI_Pos     6                                              /**< (HSTPIPISR) CRC Error Interrupt Position */
+#define HSTPIPISR_ISO_CRCERRI         (_U_(0x1) << HSTPIPISR_ISO_CRCERRI_Pos)  /**< (HSTPIPISR) CRC Error Interrupt Mask */
+#define HSTPIPISR_ISO_Msk             _U_(0x44)                                      /**< (HSTPIPISR_ISO) Register Mask  */
+
+/* BLK mode */
+#define HSTPIPISR_BLK_TXSTPI_Pos      2                                              /**< (HSTPIPISR) Transmitted SETUP Interrupt Position */
+#define HSTPIPISR_BLK_TXSTPI          (_U_(0x1) << HSTPIPISR_BLK_TXSTPI_Pos)   /**< (HSTPIPISR) Transmitted SETUP Interrupt Mask */
+#define HSTPIPISR_BLK_RXSTALLDI_Pos   6                                              /**< (HSTPIPISR) Received STALLed Interrupt Position */
+#define HSTPIPISR_BLK_RXSTALLDI       (_U_(0x1) << HSTPIPISR_BLK_RXSTALLDI_Pos)  /**< (HSTPIPISR) Received STALLed Interrupt Mask */
+#define HSTPIPISR_BLK_Msk             _U_(0x44)                                      /**< (HSTPIPISR_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define HSTPIPISR_INTRPT_UNDERFI_Pos  2                                              /**< (HSTPIPISR) Underflow Interrupt Position */
+#define HSTPIPISR_INTRPT_UNDERFI      (_U_(0x1) << HSTPIPISR_INTRPT_UNDERFI_Pos)  /**< (HSTPIPISR) Underflow Interrupt Mask */
+#define HSTPIPISR_INTRPT_RXSTALLDI_Pos 6                                              /**< (HSTPIPISR) Received STALLed Interrupt Position */
+#define HSTPIPISR_INTRPT_RXSTALLDI     (_U_(0x1) << HSTPIPISR_INTRPT_RXSTALLDI_Pos)  /**< (HSTPIPISR) Received STALLed Interrupt Mask */
+#define HSTPIPISR_INTRPT_Msk          _U_(0x44)                                      /**< (HSTPIPISR_INTRPT) Register Mask  */
+
+
+/* -------- HSTPIPICR : (USBHS Offset: 0x560) (/W 32) Host Pipe Clear Register -------- */
+
+#define HSTPIPICR_OFFSET              (0x560)                                       /**<  (HSTPIPICR) Host Pipe Clear Register  Offset */
+
+#define HSTPIPICR_RXINIC_Pos          0                                              /**< (HSTPIPICR) Received IN Data Interrupt Clear Position */
+#define HSTPIPICR_RXINIC              (_U_(0x1) << HSTPIPICR_RXINIC_Pos)       /**< (HSTPIPICR) Received IN Data Interrupt Clear Mask */
+#define HSTPIPICR_TXOUTIC_Pos         1                                              /**< (HSTPIPICR) Transmitted OUT Data Interrupt Clear Position */
+#define HSTPIPICR_TXOUTIC             (_U_(0x1) << HSTPIPICR_TXOUTIC_Pos)      /**< (HSTPIPICR) Transmitted OUT Data Interrupt Clear Mask */
+#define HSTPIPICR_NAKEDIC_Pos         4                                              /**< (HSTPIPICR) NAKed Interrupt Clear Position */
+#define HSTPIPICR_NAKEDIC             (_U_(0x1) << HSTPIPICR_NAKEDIC_Pos)      /**< (HSTPIPICR) NAKed Interrupt Clear Mask */
+#define HSTPIPICR_OVERFIC_Pos         5                                              /**< (HSTPIPICR) Overflow Interrupt Clear Position */
+#define HSTPIPICR_OVERFIC             (_U_(0x1) << HSTPIPICR_OVERFIC_Pos)      /**< (HSTPIPICR) Overflow Interrupt Clear Mask */
+#define HSTPIPICR_SHORTPACKETIC_Pos   7                                              /**< (HSTPIPICR) Short Packet Interrupt Clear Position */
+#define HSTPIPICR_SHORTPACKETIC       (_U_(0x1) << HSTPIPICR_SHORTPACKETIC_Pos)  /**< (HSTPIPICR) Short Packet Interrupt Clear Mask */
+#define HSTPIPICR_Msk                 _U_(0xB3)                                      /**< (HSTPIPICR) Register Mask  */
+
+/* CTRL mode */
+#define HSTPIPICR_CTRL_TXSTPIC_Pos    2                                              /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Position */
+#define HSTPIPICR_CTRL_TXSTPIC        (_U_(0x1) << HSTPIPICR_CTRL_TXSTPIC_Pos)  /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */
+#define HSTPIPICR_CTRL_RXSTALLDIC_Pos 6                                              /**< (HSTPIPICR) Received STALLed Interrupt Clear Position */
+#define HSTPIPICR_CTRL_RXSTALLDIC     (_U_(0x1) << HSTPIPICR_CTRL_RXSTALLDIC_Pos)  /**< (HSTPIPICR) Received STALLed Interrupt Clear Mask */
+#define HSTPIPICR_CTRL_Msk            _U_(0x44)                                      /**< (HSTPIPICR_CTRL) Register Mask  */
+
+/* ISO mode */
+#define HSTPIPICR_ISO_UNDERFIC_Pos    2                                              /**< (HSTPIPICR) Underflow Interrupt Clear Position */
+#define HSTPIPICR_ISO_UNDERFIC        (_U_(0x1) << HSTPIPICR_ISO_UNDERFIC_Pos)  /**< (HSTPIPICR) Underflow Interrupt Clear Mask */
+#define HSTPIPICR_ISO_CRCERRIC_Pos    6                                              /**< (HSTPIPICR) CRC Error Interrupt Clear Position */
+#define HSTPIPICR_ISO_CRCERRIC        (_U_(0x1) << HSTPIPICR_ISO_CRCERRIC_Pos)  /**< (HSTPIPICR) CRC Error Interrupt Clear Mask */
+#define HSTPIPICR_ISO_Msk             _U_(0x44)                                      /**< (HSTPIPICR_ISO) Register Mask  */
+
+/* BLK mode */
+#define HSTPIPICR_BLK_TXSTPIC_Pos     2                                              /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Position */
+#define HSTPIPICR_BLK_TXSTPIC         (_U_(0x1) << HSTPIPICR_BLK_TXSTPIC_Pos)  /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */
+#define HSTPIPICR_BLK_RXSTALLDIC_Pos  6                                              /**< (HSTPIPICR) Received STALLed Interrupt Clear Position */
+#define HSTPIPICR_BLK_RXSTALLDIC      (_U_(0x1) << HSTPIPICR_BLK_RXSTALLDIC_Pos)  /**< (HSTPIPICR) Received STALLed Interrupt Clear Mask */
+#define HSTPIPICR_BLK_Msk             _U_(0x44)                                      /**< (HSTPIPICR_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define HSTPIPICR_INTRPT_UNDERFIC_Pos 2                                              /**< (HSTPIPICR) Underflow Interrupt Clear Position */
+#define HSTPIPICR_INTRPT_UNDERFIC     (_U_(0x1) << HSTPIPICR_INTRPT_UNDERFIC_Pos)  /**< (HSTPIPICR) Underflow Interrupt Clear Mask */
+#define HSTPIPICR_INTRPT_RXSTALLDIC_Pos 6                                              /**< (HSTPIPICR) Received STALLed Interrupt Clear Position */
+#define HSTPIPICR_INTRPT_RXSTALLDIC     (_U_(0x1) << HSTPIPICR_INTRPT_RXSTALLDIC_Pos)  /**< (HSTPIPICR) Received STALLed Interrupt Clear Mask */
+#define HSTPIPICR_INTRPT_Msk          _U_(0x44)                                      /**< (HSTPIPICR_INTRPT) Register Mask  */
+
+
+/* -------- HSTPIPIFR : (USBHS Offset: 0x590) (/W 32) Host Pipe Set Register -------- */
+
+#define HSTPIPIFR_OFFSET              (0x590)                                       /**<  (HSTPIPIFR) Host Pipe Set Register  Offset */
+
+#define HSTPIPIFR_RXINIS_Pos          0                                              /**< (HSTPIPIFR) Received IN Data Interrupt Set Position */
+#define HSTPIPIFR_RXINIS              (_U_(0x1) << HSTPIPIFR_RXINIS_Pos)       /**< (HSTPIPIFR) Received IN Data Interrupt Set Mask */
+#define HSTPIPIFR_TXOUTIS_Pos         1                                              /**< (HSTPIPIFR) Transmitted OUT Data Interrupt Set Position */
+#define HSTPIPIFR_TXOUTIS             (_U_(0x1) << HSTPIPIFR_TXOUTIS_Pos)      /**< (HSTPIPIFR) Transmitted OUT Data Interrupt Set Mask */
+#define HSTPIPIFR_PERRIS_Pos          3                                              /**< (HSTPIPIFR) Pipe Error Interrupt Set Position */
+#define HSTPIPIFR_PERRIS              (_U_(0x1) << HSTPIPIFR_PERRIS_Pos)       /**< (HSTPIPIFR) Pipe Error Interrupt Set Mask */
+#define HSTPIPIFR_NAKEDIS_Pos         4                                              /**< (HSTPIPIFR) NAKed Interrupt Set Position */
+#define HSTPIPIFR_NAKEDIS             (_U_(0x1) << HSTPIPIFR_NAKEDIS_Pos)      /**< (HSTPIPIFR) NAKed Interrupt Set Mask */
+#define HSTPIPIFR_OVERFIS_Pos         5                                              /**< (HSTPIPIFR) Overflow Interrupt Set Position */
+#define HSTPIPIFR_OVERFIS             (_U_(0x1) << HSTPIPIFR_OVERFIS_Pos)      /**< (HSTPIPIFR) Overflow Interrupt Set Mask */
+#define HSTPIPIFR_SHORTPACKETIS_Pos   7                                              /**< (HSTPIPIFR) Short Packet Interrupt Set Position */
+#define HSTPIPIFR_SHORTPACKETIS       (_U_(0x1) << HSTPIPIFR_SHORTPACKETIS_Pos)  /**< (HSTPIPIFR) Short Packet Interrupt Set Mask */
+#define HSTPIPIFR_NBUSYBKS_Pos        12                                             /**< (HSTPIPIFR) Number of Busy Banks Set Position */
+#define HSTPIPIFR_NBUSYBKS            (_U_(0x1) << HSTPIPIFR_NBUSYBKS_Pos)     /**< (HSTPIPIFR) Number of Busy Banks Set Mask */
+#define HSTPIPIFR_Msk                 _U_(0x10BB)                                    /**< (HSTPIPIFR) Register Mask  */
+
+/* CTRL mode */
+#define HSTPIPIFR_CTRL_TXSTPIS_Pos    2                                              /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Position */
+#define HSTPIPIFR_CTRL_TXSTPIS        (_U_(0x1) << HSTPIPIFR_CTRL_TXSTPIS_Pos)  /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */
+#define HSTPIPIFR_CTRL_RXSTALLDIS_Pos 6                                              /**< (HSTPIPIFR) Received STALLed Interrupt Set Position */
+#define HSTPIPIFR_CTRL_RXSTALLDIS     (_U_(0x1) << HSTPIPIFR_CTRL_RXSTALLDIS_Pos)  /**< (HSTPIPIFR) Received STALLed Interrupt Set Mask */
+#define HSTPIPIFR_CTRL_Msk            _U_(0x44)                                      /**< (HSTPIPIFR_CTRL) Register Mask  */
+
+/* ISO mode */
+#define HSTPIPIFR_ISO_UNDERFIS_Pos    2                                              /**< (HSTPIPIFR) Underflow Interrupt Set Position */
+#define HSTPIPIFR_ISO_UNDERFIS        (_U_(0x1) << HSTPIPIFR_ISO_UNDERFIS_Pos)  /**< (HSTPIPIFR) Underflow Interrupt Set Mask */
+#define HSTPIPIFR_ISO_CRCERRIS_Pos    6                                              /**< (HSTPIPIFR) CRC Error Interrupt Set Position */
+#define HSTPIPIFR_ISO_CRCERRIS        (_U_(0x1) << HSTPIPIFR_ISO_CRCERRIS_Pos)  /**< (HSTPIPIFR) CRC Error Interrupt Set Mask */
+#define HSTPIPIFR_ISO_Msk             _U_(0x44)                                      /**< (HSTPIPIFR_ISO) Register Mask  */
+
+/* BLK mode */
+#define HSTPIPIFR_BLK_TXSTPIS_Pos     2                                              /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Position */
+#define HSTPIPIFR_BLK_TXSTPIS         (_U_(0x1) << HSTPIPIFR_BLK_TXSTPIS_Pos)  /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */
+#define HSTPIPIFR_BLK_RXSTALLDIS_Pos  6                                              /**< (HSTPIPIFR) Received STALLed Interrupt Set Position */
+#define HSTPIPIFR_BLK_RXSTALLDIS      (_U_(0x1) << HSTPIPIFR_BLK_RXSTALLDIS_Pos)  /**< (HSTPIPIFR) Received STALLed Interrupt Set Mask */
+#define HSTPIPIFR_BLK_Msk             _U_(0x44)                                      /**< (HSTPIPIFR_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define HSTPIPIFR_INTRPT_UNDERFIS_Pos 2                                              /**< (HSTPIPIFR) Underflow Interrupt Set Position */
+#define HSTPIPIFR_INTRPT_UNDERFIS     (_U_(0x1) << HSTPIPIFR_INTRPT_UNDERFIS_Pos)  /**< (HSTPIPIFR) Underflow Interrupt Set Mask */
+#define HSTPIPIFR_INTRPT_RXSTALLDIS_Pos 6                                              /**< (HSTPIPIFR) Received STALLed Interrupt Set Position */
+#define HSTPIPIFR_INTRPT_RXSTALLDIS     (_U_(0x1) << HSTPIPIFR_INTRPT_RXSTALLDIS_Pos)  /**< (HSTPIPIFR) Received STALLed Interrupt Set Mask */
+#define HSTPIPIFR_INTRPT_Msk          _U_(0x44)                                      /**< (HSTPIPIFR_INTRPT) Register Mask  */
+
+
+/* -------- HSTPIPIMR : (USBHS Offset: 0x5c0) (R/ 32) Host Pipe Mask Register -------- */
+
+#define HSTPIPIMR_OFFSET              (0x5C0)                                       /**<  (HSTPIPIMR) Host Pipe Mask Register  Offset */
+
+#define HSTPIPIMR_RXINE_Pos           0                                              /**< (HSTPIPIMR) Received IN Data Interrupt Enable Position */
+#define HSTPIPIMR_RXINE               (_U_(0x1) << HSTPIPIMR_RXINE_Pos)        /**< (HSTPIPIMR) Received IN Data Interrupt Enable Mask */
+#define HSTPIPIMR_TXOUTE_Pos          1                                              /**< (HSTPIPIMR) Transmitted OUT Data Interrupt Enable Position */
+#define HSTPIPIMR_TXOUTE              (_U_(0x1) << HSTPIPIMR_TXOUTE_Pos)       /**< (HSTPIPIMR) Transmitted OUT Data Interrupt Enable Mask */
+#define HSTPIPIMR_PERRE_Pos           3                                              /**< (HSTPIPIMR) Pipe Error Interrupt Enable Position */
+#define HSTPIPIMR_PERRE               (_U_(0x1) << HSTPIPIMR_PERRE_Pos)        /**< (HSTPIPIMR) Pipe Error Interrupt Enable Mask */
+#define HSTPIPIMR_NAKEDE_Pos          4                                              /**< (HSTPIPIMR) NAKed Interrupt Enable Position */
+#define HSTPIPIMR_NAKEDE              (_U_(0x1) << HSTPIPIMR_NAKEDE_Pos)       /**< (HSTPIPIMR) NAKed Interrupt Enable Mask */
+#define HSTPIPIMR_OVERFIE_Pos         5                                              /**< (HSTPIPIMR) Overflow Interrupt Enable Position */
+#define HSTPIPIMR_OVERFIE             (_U_(0x1) << HSTPIPIMR_OVERFIE_Pos)      /**< (HSTPIPIMR) Overflow Interrupt Enable Mask */
+#define HSTPIPIMR_SHORTPACKETIE_Pos   7                                              /**< (HSTPIPIMR) Short Packet Interrupt Enable Position */
+#define HSTPIPIMR_SHORTPACKETIE       (_U_(0x1) << HSTPIPIMR_SHORTPACKETIE_Pos)  /**< (HSTPIPIMR) Short Packet Interrupt Enable Mask */
+#define HSTPIPIMR_NBUSYBKE_Pos        12                                             /**< (HSTPIPIMR) Number of Busy Banks Interrupt Enable Position */
+#define HSTPIPIMR_NBUSYBKE            (_U_(0x1) << HSTPIPIMR_NBUSYBKE_Pos)     /**< (HSTPIPIMR) Number of Busy Banks Interrupt Enable Mask */
+#define HSTPIPIMR_FIFOCON_Pos         14                                             /**< (HSTPIPIMR) FIFO Control Position */
+#define HSTPIPIMR_FIFOCON             (_U_(0x1) << HSTPIPIMR_FIFOCON_Pos)      /**< (HSTPIPIMR) FIFO Control Mask */
+#define HSTPIPIMR_PDISHDMA_Pos        16                                             /**< (HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Position */
+#define HSTPIPIMR_PDISHDMA            (_U_(0x1) << HSTPIPIMR_PDISHDMA_Pos)     /**< (HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Mask */
+#define HSTPIPIMR_PFREEZE_Pos         17                                             /**< (HSTPIPIMR) Pipe Freeze Position */
+#define HSTPIPIMR_PFREEZE             (_U_(0x1) << HSTPIPIMR_PFREEZE_Pos)      /**< (HSTPIPIMR) Pipe Freeze Mask */
+#define HSTPIPIMR_RSTDT_Pos           18                                             /**< (HSTPIPIMR) Reset Data Toggle Position */
+#define HSTPIPIMR_RSTDT               (_U_(0x1) << HSTPIPIMR_RSTDT_Pos)        /**< (HSTPIPIMR) Reset Data Toggle Mask */
+#define HSTPIPIMR_Msk                 _U_(0x750BB)                                   /**< (HSTPIPIMR) Register Mask  */
+
+/* CTRL mode */
+#define HSTPIPIMR_CTRL_TXSTPE_Pos     2                                              /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */
+#define HSTPIPIMR_CTRL_TXSTPE         (_U_(0x1) << HSTPIPIMR_CTRL_TXSTPE_Pos)  /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */
+#define HSTPIPIMR_CTRL_RXSTALLDE_Pos  6                                              /**< (HSTPIPIMR) Received STALLed Interrupt Enable Position */
+#define HSTPIPIMR_CTRL_RXSTALLDE      (_U_(0x1) << HSTPIPIMR_CTRL_RXSTALLDE_Pos)  /**< (HSTPIPIMR) Received STALLed Interrupt Enable Mask */
+#define HSTPIPIMR_CTRL_Msk            _U_(0x44)                                      /**< (HSTPIPIMR_CTRL) Register Mask  */
+
+/* ISO mode */
+#define HSTPIPIMR_ISO_UNDERFIE_Pos    2                                              /**< (HSTPIPIMR) Underflow Interrupt Enable Position */
+#define HSTPIPIMR_ISO_UNDERFIE        (_U_(0x1) << HSTPIPIMR_ISO_UNDERFIE_Pos)  /**< (HSTPIPIMR) Underflow Interrupt Enable Mask */
+#define HSTPIPIMR_ISO_CRCERRE_Pos     6                                              /**< (HSTPIPIMR) CRC Error Interrupt Enable Position */
+#define HSTPIPIMR_ISO_CRCERRE         (_U_(0x1) << HSTPIPIMR_ISO_CRCERRE_Pos)  /**< (HSTPIPIMR) CRC Error Interrupt Enable Mask */
+#define HSTPIPIMR_ISO_Msk             _U_(0x44)                                      /**< (HSTPIPIMR_ISO) Register Mask  */
+
+/* BLK mode */
+#define HSTPIPIMR_BLK_TXSTPE_Pos      2                                              /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */
+#define HSTPIPIMR_BLK_TXSTPE          (_U_(0x1) << HSTPIPIMR_BLK_TXSTPE_Pos)   /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */
+#define HSTPIPIMR_BLK_RXSTALLDE_Pos   6                                              /**< (HSTPIPIMR) Received STALLed Interrupt Enable Position */
+#define HSTPIPIMR_BLK_RXSTALLDE       (_U_(0x1) << HSTPIPIMR_BLK_RXSTALLDE_Pos)  /**< (HSTPIPIMR) Received STALLed Interrupt Enable Mask */
+#define HSTPIPIMR_BLK_Msk             _U_(0x44)                                      /**< (HSTPIPIMR_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define HSTPIPIMR_INTRPT_UNDERFIE_Pos 2                                              /**< (HSTPIPIMR) Underflow Interrupt Enable Position */
+#define HSTPIPIMR_INTRPT_UNDERFIE     (_U_(0x1) << HSTPIPIMR_INTRPT_UNDERFIE_Pos)  /**< (HSTPIPIMR) Underflow Interrupt Enable Mask */
+#define HSTPIPIMR_INTRPT_RXSTALLDE_Pos 6                                              /**< (HSTPIPIMR) Received STALLed Interrupt Enable Position */
+#define HSTPIPIMR_INTRPT_RXSTALLDE     (_U_(0x1) << HSTPIPIMR_INTRPT_RXSTALLDE_Pos)  /**< (HSTPIPIMR) Received STALLed Interrupt Enable Mask */
+#define HSTPIPIMR_INTRPT_Msk          _U_(0x44)                                      /**< (HSTPIPIMR_INTRPT) Register Mask  */
+
+
+/* -------- HSTPIPIER : (USBHS Offset: 0x5f0) (/W 32) Host Pipe Enable Register -------- */
+
+#define HSTPIPIER_OFFSET              (0x5F0)                                       /**<  (HSTPIPIER) Host Pipe Enable Register  Offset */
+
+#define HSTPIPIER_RXINES_Pos          0                                              /**< (HSTPIPIER) Received IN Data Interrupt Enable Position */
+#define HSTPIPIER_RXINES              (_U_(0x1) << HSTPIPIER_RXINES_Pos)       /**< (HSTPIPIER) Received IN Data Interrupt Enable Mask */
+#define HSTPIPIER_TXOUTES_Pos         1                                              /**< (HSTPIPIER) Transmitted OUT Data Interrupt Enable Position */
+#define HSTPIPIER_TXOUTES             (_U_(0x1) << HSTPIPIER_TXOUTES_Pos)      /**< (HSTPIPIER) Transmitted OUT Data Interrupt Enable Mask */
+#define HSTPIPIER_PERRES_Pos          3                                              /**< (HSTPIPIER) Pipe Error Interrupt Enable Position */
+#define HSTPIPIER_PERRES              (_U_(0x1) << HSTPIPIER_PERRES_Pos)       /**< (HSTPIPIER) Pipe Error Interrupt Enable Mask */
+#define HSTPIPIER_NAKEDES_Pos         4                                              /**< (HSTPIPIER) NAKed Interrupt Enable Position */
+#define HSTPIPIER_NAKEDES             (_U_(0x1) << HSTPIPIER_NAKEDES_Pos)      /**< (HSTPIPIER) NAKed Interrupt Enable Mask */
+#define HSTPIPIER_OVERFIES_Pos        5                                              /**< (HSTPIPIER) Overflow Interrupt Enable Position */
+#define HSTPIPIER_OVERFIES            (_U_(0x1) << HSTPIPIER_OVERFIES_Pos)     /**< (HSTPIPIER) Overflow Interrupt Enable Mask */
+#define HSTPIPIER_SHORTPACKETIES_Pos  7                                              /**< (HSTPIPIER) Short Packet Interrupt Enable Position */
+#define HSTPIPIER_SHORTPACKETIES      (_U_(0x1) << HSTPIPIER_SHORTPACKETIES_Pos)  /**< (HSTPIPIER) Short Packet Interrupt Enable Mask */
+#define HSTPIPIER_NBUSYBKES_Pos       12                                             /**< (HSTPIPIER) Number of Busy Banks Enable Position */
+#define HSTPIPIER_NBUSYBKES           (_U_(0x1) << HSTPIPIER_NBUSYBKES_Pos)    /**< (HSTPIPIER) Number of Busy Banks Enable Mask */
+#define HSTPIPIER_PDISHDMAS_Pos       16                                             /**< (HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Position */
+#define HSTPIPIER_PDISHDMAS           (_U_(0x1) << HSTPIPIER_PDISHDMAS_Pos)    /**< (HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Mask */
+#define HSTPIPIER_PFREEZES_Pos        17                                             /**< (HSTPIPIER) Pipe Freeze Enable Position */
+#define HSTPIPIER_PFREEZES            (_U_(0x1) << HSTPIPIER_PFREEZES_Pos)     /**< (HSTPIPIER) Pipe Freeze Enable Mask */
+#define HSTPIPIER_RSTDTS_Pos          18                                             /**< (HSTPIPIER) Reset Data Toggle Enable Position */
+#define HSTPIPIER_RSTDTS              (_U_(0x1) << HSTPIPIER_RSTDTS_Pos)       /**< (HSTPIPIER) Reset Data Toggle Enable Mask */
+#define HSTPIPIER_Msk                 _U_(0x710BB)                                   /**< (HSTPIPIER) Register Mask  */
+
+/* CTRL mode */
+#define HSTPIPIER_CTRL_TXSTPES_Pos    2                                              /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Position */
+#define HSTPIPIER_CTRL_TXSTPES        (_U_(0x1) << HSTPIPIER_CTRL_TXSTPES_Pos)  /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */
+#define HSTPIPIER_CTRL_RXSTALLDES_Pos 6                                              /**< (HSTPIPIER) Received STALLed Interrupt Enable Position */
+#define HSTPIPIER_CTRL_RXSTALLDES     (_U_(0x1) << HSTPIPIER_CTRL_RXSTALLDES_Pos)  /**< (HSTPIPIER) Received STALLed Interrupt Enable Mask */
+#define HSTPIPIER_CTRL_Msk            _U_(0x44)                                      /**< (HSTPIPIER_CTRL) Register Mask  */
+
+/* ISO mode */
+#define HSTPIPIER_ISO_UNDERFIES_Pos   2                                              /**< (HSTPIPIER) Underflow Interrupt Enable Position */
+#define HSTPIPIER_ISO_UNDERFIES       (_U_(0x1) << HSTPIPIER_ISO_UNDERFIES_Pos)  /**< (HSTPIPIER) Underflow Interrupt Enable Mask */
+#define HSTPIPIER_ISO_CRCERRES_Pos    6                                              /**< (HSTPIPIER) CRC Error Interrupt Enable Position */
+#define HSTPIPIER_ISO_CRCERRES        (_U_(0x1) << HSTPIPIER_ISO_CRCERRES_Pos)  /**< (HSTPIPIER) CRC Error Interrupt Enable Mask */
+#define HSTPIPIER_ISO_Msk             _U_(0x44)                                      /**< (HSTPIPIER_ISO) Register Mask  */
+
+/* BLK mode */
+#define HSTPIPIER_BLK_TXSTPES_Pos     2                                              /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Position */
+#define HSTPIPIER_BLK_TXSTPES         (_U_(0x1) << HSTPIPIER_BLK_TXSTPES_Pos)  /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */
+#define HSTPIPIER_BLK_RXSTALLDES_Pos  6                                              /**< (HSTPIPIER) Received STALLed Interrupt Enable Position */
+#define HSTPIPIER_BLK_RXSTALLDES      (_U_(0x1) << HSTPIPIER_BLK_RXSTALLDES_Pos)  /**< (HSTPIPIER) Received STALLed Interrupt Enable Mask */
+#define HSTPIPIER_BLK_Msk             _U_(0x44)                                      /**< (HSTPIPIER_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define HSTPIPIER_INTRPT_UNDERFIES_Pos 2                                              /**< (HSTPIPIER) Underflow Interrupt Enable Position */
+#define HSTPIPIER_INTRPT_UNDERFIES     (_U_(0x1) << HSTPIPIER_INTRPT_UNDERFIES_Pos)  /**< (HSTPIPIER) Underflow Interrupt Enable Mask */
+#define HSTPIPIER_INTRPT_RXSTALLDES_Pos 6                                              /**< (HSTPIPIER) Received STALLed Interrupt Enable Position */
+#define HSTPIPIER_INTRPT_RXSTALLDES     (_U_(0x1) << HSTPIPIER_INTRPT_RXSTALLDES_Pos)  /**< (HSTPIPIER) Received STALLed Interrupt Enable Mask */
+#define HSTPIPIER_INTRPT_Msk          _U_(0x44)                                      /**< (HSTPIPIER_INTRPT) Register Mask  */
+
+
+/* -------- HSTPIPIDR : (USBHS Offset: 0x620) (/W 32) Host Pipe Disable Register -------- */
+
+#define HSTPIPIDR_OFFSET              (0x620)                                       /**<  (HSTPIPIDR) Host Pipe Disable Register  Offset */
+
+#define HSTPIPIDR_RXINEC_Pos          0                                              /**< (HSTPIPIDR) Received IN Data Interrupt Disable Position */
+#define HSTPIPIDR_RXINEC              (_U_(0x1) << HSTPIPIDR_RXINEC_Pos)       /**< (HSTPIPIDR) Received IN Data Interrupt Disable Mask */
+#define HSTPIPIDR_TXOUTEC_Pos         1                                              /**< (HSTPIPIDR) Transmitted OUT Data Interrupt Disable Position */
+#define HSTPIPIDR_TXOUTEC             (_U_(0x1) << HSTPIPIDR_TXOUTEC_Pos)      /**< (HSTPIPIDR) Transmitted OUT Data Interrupt Disable Mask */
+#define HSTPIPIDR_PERREC_Pos          3                                              /**< (HSTPIPIDR) Pipe Error Interrupt Disable Position */
+#define HSTPIPIDR_PERREC              (_U_(0x1) << HSTPIPIDR_PERREC_Pos)       /**< (HSTPIPIDR) Pipe Error Interrupt Disable Mask */
+#define HSTPIPIDR_NAKEDEC_Pos         4                                              /**< (HSTPIPIDR) NAKed Interrupt Disable Position */
+#define HSTPIPIDR_NAKEDEC             (_U_(0x1) << HSTPIPIDR_NAKEDEC_Pos)      /**< (HSTPIPIDR) NAKed Interrupt Disable Mask */
+#define HSTPIPIDR_OVERFIEC_Pos        5                                              /**< (HSTPIPIDR) Overflow Interrupt Disable Position */
+#define HSTPIPIDR_OVERFIEC            (_U_(0x1) << HSTPIPIDR_OVERFIEC_Pos)     /**< (HSTPIPIDR) Overflow Interrupt Disable Mask */
+#define HSTPIPIDR_SHORTPACKETIEC_Pos  7                                              /**< (HSTPIPIDR) Short Packet Interrupt Disable Position */
+#define HSTPIPIDR_SHORTPACKETIEC      (_U_(0x1) << HSTPIPIDR_SHORTPACKETIEC_Pos)  /**< (HSTPIPIDR) Short Packet Interrupt Disable Mask */
+#define HSTPIPIDR_NBUSYBKEC_Pos       12                                             /**< (HSTPIPIDR) Number of Busy Banks Disable Position */
+#define HSTPIPIDR_NBUSYBKEC           (_U_(0x1) << HSTPIPIDR_NBUSYBKEC_Pos)    /**< (HSTPIPIDR) Number of Busy Banks Disable Mask */
+#define HSTPIPIDR_FIFOCONC_Pos        14                                             /**< (HSTPIPIDR) FIFO Control Disable Position */
+#define HSTPIPIDR_FIFOCONC            (_U_(0x1) << HSTPIPIDR_FIFOCONC_Pos)     /**< (HSTPIPIDR) FIFO Control Disable Mask */
+#define HSTPIPIDR_PDISHDMAC_Pos       16                                             /**< (HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Position */
+#define HSTPIPIDR_PDISHDMAC           (_U_(0x1) << HSTPIPIDR_PDISHDMAC_Pos)    /**< (HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Mask */
+#define HSTPIPIDR_PFREEZEC_Pos        17                                             /**< (HSTPIPIDR) Pipe Freeze Disable Position */
+#define HSTPIPIDR_PFREEZEC            (_U_(0x1) << HSTPIPIDR_PFREEZEC_Pos)     /**< (HSTPIPIDR) Pipe Freeze Disable Mask */
+#define HSTPIPIDR_Msk                 _U_(0x350BB)                                   /**< (HSTPIPIDR) Register Mask  */
+
+/* CTRL mode */
+#define HSTPIPIDR_CTRL_TXSTPEC_Pos    2                                              /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */
+#define HSTPIPIDR_CTRL_TXSTPEC        (_U_(0x1) << HSTPIPIDR_CTRL_TXSTPEC_Pos)  /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */
+#define HSTPIPIDR_CTRL_RXSTALLDEC_Pos 6                                              /**< (HSTPIPIDR) Received STALLed Interrupt Disable Position */
+#define HSTPIPIDR_CTRL_RXSTALLDEC     (_U_(0x1) << HSTPIPIDR_CTRL_RXSTALLDEC_Pos)  /**< (HSTPIPIDR) Received STALLed Interrupt Disable Mask */
+#define HSTPIPIDR_CTRL_Msk            _U_(0x44)                                      /**< (HSTPIPIDR_CTRL) Register Mask  */
+
+/* ISO mode */
+#define HSTPIPIDR_ISO_UNDERFIEC_Pos   2                                              /**< (HSTPIPIDR) Underflow Interrupt Disable Position */
+#define HSTPIPIDR_ISO_UNDERFIEC       (_U_(0x1) << HSTPIPIDR_ISO_UNDERFIEC_Pos)  /**< (HSTPIPIDR) Underflow Interrupt Disable Mask */
+#define HSTPIPIDR_ISO_CRCERREC_Pos    6                                              /**< (HSTPIPIDR) CRC Error Interrupt Disable Position */
+#define HSTPIPIDR_ISO_CRCERREC        (_U_(0x1) << HSTPIPIDR_ISO_CRCERREC_Pos)  /**< (HSTPIPIDR) CRC Error Interrupt Disable Mask */
+#define HSTPIPIDR_ISO_Msk             _U_(0x44)                                      /**< (HSTPIPIDR_ISO) Register Mask  */
+
+/* BLK mode */
+#define HSTPIPIDR_BLK_TXSTPEC_Pos     2                                              /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */
+#define HSTPIPIDR_BLK_TXSTPEC         (_U_(0x1) << HSTPIPIDR_BLK_TXSTPEC_Pos)  /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */
+#define HSTPIPIDR_BLK_RXSTALLDEC_Pos  6                                              /**< (HSTPIPIDR) Received STALLed Interrupt Disable Position */
+#define HSTPIPIDR_BLK_RXSTALLDEC      (_U_(0x1) << HSTPIPIDR_BLK_RXSTALLDEC_Pos)  /**< (HSTPIPIDR) Received STALLed Interrupt Disable Mask */
+#define HSTPIPIDR_BLK_Msk             _U_(0x44)                                      /**< (HSTPIPIDR_BLK) Register Mask  */
+
+/* INTRPT mode */
+#define HSTPIPIDR_INTRPT_UNDERFIEC_Pos 2                                              /**< (HSTPIPIDR) Underflow Interrupt Disable Position */
+#define HSTPIPIDR_INTRPT_UNDERFIEC     (_U_(0x1) << HSTPIPIDR_INTRPT_UNDERFIEC_Pos)  /**< (HSTPIPIDR) Underflow Interrupt Disable Mask */
+#define HSTPIPIDR_INTRPT_RXSTALLDEC_Pos 6                                              /**< (HSTPIPIDR) Received STALLed Interrupt Disable Position */
+#define HSTPIPIDR_INTRPT_RXSTALLDEC     (_U_(0x1) << HSTPIPIDR_INTRPT_RXSTALLDEC_Pos)  /**< (HSTPIPIDR) Received STALLed Interrupt Disable Mask */
+#define HSTPIPIDR_INTRPT_Msk          _U_(0x44)                                      /**< (HSTPIPIDR_INTRPT) Register Mask  */
+
+
+/* -------- HSTPIPINRQ : (USBHS Offset: 0x650) (R/W 32) Host Pipe IN Request Register -------- */
+
+#define HSTPIPINRQ_OFFSET             (0x650)                                       /**<  (HSTPIPINRQ) Host Pipe IN Request Register  Offset */
+
+#define HSTPIPINRQ_INRQ_Pos           0                                              /**< (HSTPIPINRQ) IN Request Number before Freeze Position */
+#define HSTPIPINRQ_INRQ               (_U_(0xFF) << HSTPIPINRQ_INRQ_Pos)       /**< (HSTPIPINRQ) IN Request Number before Freeze Mask */
+#define HSTPIPINRQ_INMODE_Pos         8                                              /**< (HSTPIPINRQ) IN Request Mode Position */
+#define HSTPIPINRQ_INMODE             (_U_(0x1) << HSTPIPINRQ_INMODE_Pos)      /**< (HSTPIPINRQ) IN Request Mode Mask */
+#define HSTPIPINRQ_Msk                _U_(0x1FF)                                     /**< (HSTPIPINRQ) Register Mask  */
+
+
+/* -------- HSTPIPERR : (USBHS Offset: 0x680) (R/W 32) Host Pipe Error Register -------- */
+
+#define HSTPIPERR_OFFSET              (0x680)                                       /**<  (HSTPIPERR) Host Pipe Error Register  Offset */
+
+#define HSTPIPERR_DATATGL_Pos         0                                              /**< (HSTPIPERR) Data Toggle Error Position */
+#define HSTPIPERR_DATATGL             (_U_(0x1) << HSTPIPERR_DATATGL_Pos)      /**< (HSTPIPERR) Data Toggle Error Mask */
+#define HSTPIPERR_DATAPID_Pos         1                                              /**< (HSTPIPERR) Data PID Error Position */
+#define HSTPIPERR_DATAPID             (_U_(0x1) << HSTPIPERR_DATAPID_Pos)      /**< (HSTPIPERR) Data PID Error Mask */
+#define HSTPIPERR_PID_Pos             2                                              /**< (HSTPIPERR) Data PID Error Position */
+#define HSTPIPERR_PID                 (_U_(0x1) << HSTPIPERR_PID_Pos)          /**< (HSTPIPERR) Data PID Error Mask */
+#define HSTPIPERR_TIMEOUT_Pos         3                                              /**< (HSTPIPERR) Time-Out Error Position */
+#define HSTPIPERR_TIMEOUT             (_U_(0x1) << HSTPIPERR_TIMEOUT_Pos)      /**< (HSTPIPERR) Time-Out Error Mask */
+#define HSTPIPERR_CRC16_Pos           4                                              /**< (HSTPIPERR) CRC16 Error Position */
+#define HSTPIPERR_CRC16               (_U_(0x1) << HSTPIPERR_CRC16_Pos)        /**< (HSTPIPERR) CRC16 Error Mask */
+#define HSTPIPERR_COUNTER_Pos         5                                              /**< (HSTPIPERR) Error Counter Position */
+#define HSTPIPERR_COUNTER             (_U_(0x3) << HSTPIPERR_COUNTER_Pos)      /**< (HSTPIPERR) Error Counter Mask */
+#define HSTPIPERR_Msk                 _U_(0x7F)                                      /**< (HSTPIPERR) Register Mask  */
+
+#define HSTPIPERR_CRC_Pos             4                                              /**< (HSTPIPERR Position) CRCx6 Error */
+#define HSTPIPERR_CRC                 (_U_(0x1) << HSTPIPERR_CRC_Pos)          /**< (HSTPIPERR Mask) CRC */
+
+/* -------- CTRL : (USBHS Offset: 0x800) (R/W 32) General Control Register -------- */
+
+#define CTRL_OFFSET                   (0x800)                                       /**<  (CTRL) General Control Register  Offset */
+
+#define CTRL_RDERRE_Pos               4                                              /**< (CTRL) Remote Device Connection Error Interrupt Enable Position */
+#define CTRL_RDERRE                   (_U_(0x1) << CTRL_RDERRE_Pos)            /**< (CTRL) Remote Device Connection Error Interrupt Enable Mask */
+#define CTRL_VBUSHWC_Pos              8                                              /**< (CTRL) VBUS Hardware Control Position */
+#define CTRL_VBUSHWC                  (_U_(0x1) << CTRL_VBUSHWC_Pos)           /**< (CTRL) VBUS Hardware Control Mask */
+#define CTRL_FRZCLK_Pos               14                                             /**< (CTRL) Freeze USB Clock Position */
+#define CTRL_FRZCLK                   (_U_(0x1) << CTRL_FRZCLK_Pos)            /**< (CTRL) Freeze USB Clock Mask */
+#define CTRL_USBE_Pos                 15                                             /**< (CTRL) USBHS Enable Position */
+#define CTRL_USBE                     (_U_(0x1) << CTRL_USBE_Pos)              /**< (CTRL) USBHS Enable Mask */
+#define CTRL_UID_Pos                  24                                             /**< (CTRL) UID Pin Enable Position */
+#define CTRL_UID                      (_U_(0x1) << CTRL_UID_Pos)               /**< (CTRL) UID Pin Enable Mask */
+#define CTRL_UIMOD_Pos                25                                             /**< (CTRL) USBHS Mode Position */
+#define CTRL_UIMOD                    (_U_(0x1) << CTRL_UIMOD_Pos)             /**< (CTRL) USBHS Mode Mask */
+#define   CTRL_UIMOD_HOST_Val         _U_(0x0)                                       /**< (CTRL) The module is in USB Host mode.  */
+#define   CTRL_UIMOD_DEVICE_Val       _U_(0x1)                                       /**< (CTRL) The module is in USB Device mode.  */
+#define CTRL_UIMOD_HOST               (CTRL_UIMOD_HOST_Val << CTRL_UIMOD_Pos)  /**< (CTRL) The module is in USB Host mode. Position  */
+#define CTRL_UIMOD_DEVICE             (CTRL_UIMOD_DEVICE_Val << CTRL_UIMOD_Pos)  /**< (CTRL) The module is in USB Device mode. Position  */
+#define CTRL_Msk                      _U_(0x300C110)                                 /**< (CTRL) Register Mask  */
+
+
+/* -------- SR : (USBHS Offset: 0x804) (R/ 32) General Status Register -------- */
+
+#define SR_OFFSET                     (0x804)                                       /**<  (SR) General Status Register  Offset */
+
+#define SR_RDERRI_Pos                 4                                              /**< (SR) Remote Device Connection Error Interrupt (Host mode only) Position */
+#define SR_RDERRI                     (_U_(0x1) << SR_RDERRI_Pos)              /**< (SR) Remote Device Connection Error Interrupt (Host mode only) Mask */
+#define SR_SPEED_Pos                  12                                             /**< (SR) Speed Status (Device mode only) Position */
+#define SR_SPEED                      (_U_(0x3) << SR_SPEED_Pos)               /**< (SR) Speed Status (Device mode only) Mask */
+#define   SR_SPEED_FULL_SPEED_Val     _U_(0x0)                                       /**< (SR) Full-Speed mode  */
+#define   SR_SPEED_HIGH_SPEED_Val     _U_(0x1)                                       /**< (SR) High-Speed mode  */
+#define   SR_SPEED_LOW_SPEED_Val      _U_(0x2)                                       /**< (SR) Low-Speed mode  */
+#define SR_SPEED_FULL_SPEED           (SR_SPEED_FULL_SPEED_Val << SR_SPEED_Pos)  /**< (SR) Full-Speed mode Position  */
+#define SR_SPEED_HIGH_SPEED           (SR_SPEED_HIGH_SPEED_Val << SR_SPEED_Pos)  /**< (SR) High-Speed mode Position  */
+#define SR_SPEED_LOW_SPEED            (SR_SPEED_LOW_SPEED_Val << SR_SPEED_Pos)  /**< (SR) Low-Speed mode Position  */
+#define SR_CLKUSABLE_Pos              14                                             /**< (SR) UTMI Clock Usable Position */
+#define SR_CLKUSABLE                  (_U_(0x1) << SR_CLKUSABLE_Pos)           /**< (SR) UTMI Clock Usable Mask */
+#define SR_Msk                        _U_(0x7010)                                    /**< (SR) Register Mask  */
+
+
+/* -------- SCR : (USBHS Offset: 0x808) (/W 32) General Status Clear Register -------- */
+
+#define SCR_OFFSET                    (0x808)                                       /**<  (SCR) General Status Clear Register  Offset */
+
+#define SCR_RDERRIC_Pos               4                                              /**< (SCR) Remote Device Connection Error Interrupt Clear Position */
+#define SCR_RDERRIC                   (_U_(0x1) << SCR_RDERRIC_Pos)            /**< (SCR) Remote Device Connection Error Interrupt Clear Mask */
+#define SCR_Msk                       _U_(0x10)                                      /**< (SCR) Register Mask  */
+
+
+/* -------- SFR : (USBHS Offset: 0x80c) (/W 32) General Status Set Register -------- */
+
+#define SFR_OFFSET                    (0x80C)                                       /**<  (SFR) General Status Set Register  Offset */
+
+#define SFR_RDERRIS_Pos               4                                              /**< (SFR) Remote Device Connection Error Interrupt Set Position */
+#define SFR_RDERRIS                   (_U_(0x1) << SFR_RDERRIS_Pos)            /**< (SFR) Remote Device Connection Error Interrupt Set Mask */
+#define SFR_VBUSRQS_Pos               9                                              /**< (SFR) VBUS Request Set Position */
+#define SFR_VBUSRQS                   (_U_(0x1) << SFR_VBUSRQS_Pos)            /**< (SFR) VBUS Request Set Mask */
+#define SFR_Msk                       _U_(0x210)                                     /**< (SFR) Register Mask  */
+
+
+/** \brief DEVDMA hardware registers */
+typedef struct
+{  
+  __IO uint32_t DEVDMANXTDSC; /**< (DEVDMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */
+  __IO uint32_t DEVDMAADDRESS; /**< (DEVDMA Offset: 0x04) Device DMA Channel Address Register */
+  __IO uint32_t DEVDMACONTROL; /**< (DEVDMA Offset: 0x08) Device DMA Channel Control Register */
+  __IO uint32_t DEVDMASTATUS; /**< (DEVDMA Offset: 0x0C) Device DMA Channel Status Register */
+} devdma_t;
+
+/** \brief HSTDMA hardware registers */
+typedef struct
+{  
+  __IO uint32_t HSTDMANXTDSC; /**< (HSTDMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */
+  __IO uint32_t HSTDMAADDRESS; /**< (HSTDMA Offset: 0x04) Host DMA Channel Address Register */
+  __IO uint32_t HSTDMACONTROL; /**< (HSTDMA Offset: 0x08) Host DMA Channel Control Register */
+  __IO uint32_t HSTDMASTATUS; /**< (HSTDMA Offset: 0x0C) Host DMA Channel Status Register */
+} hstdma_t;
+
+/** \brief USBHS hardware registers */
+typedef struct
+{  
+  __IO uint32_t DEVCTRL;  /**< (USBHS Offset: 0x00) Device General Control Register */
+  __I  uint32_t DEVISR;   /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */
+  __O  uint32_t DEVICR;   /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */
+  __O  uint32_t DEVIFR;   /**< (USBHS Offset: 0x0C) Device Global Interrupt Set Register */
+  __I  uint32_t DEVIMR;   /**< (USBHS Offset: 0x10) Device Global Interrupt Mask Register */
+  __O  uint32_t DEVIDR;   /**< (USBHS Offset: 0x14) Device Global Interrupt Disable Register */
+  __O  uint32_t DEVIER;   /**< (USBHS Offset: 0x18) Device Global Interrupt Enable Register */
+  __IO uint32_t DEVEPT;   /**< (USBHS Offset: 0x1C) Device Endpoint Register */
+  __I  uint32_t DEVFNUM;  /**< (USBHS Offset: 0x20) Device Frame Number Register */
+  __I  uint8_t                        Reserved1[220];
+  __IO uint32_t DEVEPTCFG[10]; /**< (USBHS Offset: 0x100) Device Endpoint Configuration Register */
+  __I  uint8_t                        Reserved2[8];
+  __I  uint32_t DEVEPTISR[10]; /**< (USBHS Offset: 0x130) Device Endpoint Interrupt Status Register */
+  __I  uint8_t                        Reserved3[8];
+  __O  uint32_t DEVEPTICR[10]; /**< (USBHS Offset: 0x160) Device Endpoint Interrupt Clear Register */
+  __I  uint8_t                        Reserved4[8];
+  __O  uint32_t DEVEPTIFR[10]; /**< (USBHS Offset: 0x190) Device Endpoint Interrupt Set Register */
+  __I  uint8_t                        Reserved5[8];
+  __I  uint32_t DEVEPTIMR[10]; /**< (USBHS Offset: 0x1C0) Device Endpoint Interrupt Mask Register */
+  __I  uint8_t                        Reserved6[8];
+  __O  uint32_t DEVEPTIER[10]; /**< (USBHS Offset: 0x1F0) Device Endpoint Interrupt Enable Register */
+  __I  uint8_t                        Reserved7[8];
+  __O  uint32_t DEVEPTIDR[10]; /**< (USBHS Offset: 0x220) Device Endpoint Interrupt Disable Register */
+  __I  uint8_t                        Reserved8[200];
+       devdma_t DEVDMA[7]; /**< Offset: 0x310 Device DMA Channel Next Descriptor Address Register */
+  __I  uint8_t                        Reserved9[128];
+  __IO uint32_t HSTCTRL;  /**< (USBHS Offset: 0x400) Host General Control Register */
+  __I  uint32_t HSTISR;   /**< (USBHS Offset: 0x404) Host Global Interrupt Status Register */
+  __O  uint32_t HSTICR;   /**< (USBHS Offset: 0x408) Host Global Interrupt Clear Register */
+  __O  uint32_t HSTIFR;   /**< (USBHS Offset: 0x40C) Host Global Interrupt Set Register */
+  __I  uint32_t HSTIMR;   /**< (USBHS Offset: 0x410) Host Global Interrupt Mask Register */
+  __O  uint32_t HSTIDR;   /**< (USBHS Offset: 0x414) Host Global Interrupt Disable Register */
+  __O  uint32_t HSTIER;   /**< (USBHS Offset: 0x418) Host Global Interrupt Enable Register */
+  __IO uint32_t HSTPIP;   /**< (USBHS Offset: 0x41C) Host Pipe Register */
+  __IO uint32_t HSTFNUM;  /**< (USBHS Offset: 0x420) Host Frame Number Register */
+  __IO uint32_t HSTADDR1; /**< (USBHS Offset: 0x424) Host Address 1 Register */
+  __IO uint32_t HSTADDR2; /**< (USBHS Offset: 0x428) Host Address 2 Register */
+  __IO uint32_t HSTADDR3; /**< (USBHS Offset: 0x42C) Host Address 3 Register */
+  __I  uint8_t                        Reserved10[208];
+  __IO uint32_t HSTPIPCFG[10]; /**< (USBHS Offset: 0x500) Host Pipe Configuration Register */
+  __I  uint8_t                        Reserved11[8];
+  __I  uint32_t HSTPIPISR[10]; /**< (USBHS Offset: 0x530) Host Pipe Status Register */
+  __I  uint8_t                        Reserved12[8];
+  __O  uint32_t HSTPIPICR[10]; /**< (USBHS Offset: 0x560) Host Pipe Clear Register */
+  __I  uint8_t                        Reserved13[8];
+  __O  uint32_t HSTPIPIFR[10]; /**< (USBHS Offset: 0x590) Host Pipe Set Register */
+  __I  uint8_t                        Reserved14[8];
+  __I  uint32_t HSTPIPIMR[10]; /**< (USBHS Offset: 0x5C0) Host Pipe Mask Register */
+  __I  uint8_t                        Reserved15[8];
+  __O  uint32_t HSTPIPIER[10]; /**< (USBHS Offset: 0x5F0) Host Pipe Enable Register */
+  __I  uint8_t                        Reserved16[8];
+  __O  uint32_t HSTPIPIDR[10]; /**< (USBHS Offset: 0x620) Host Pipe Disable Register */
+  __I  uint8_t                        Reserved17[8];
+  __IO uint32_t HSTPIPINRQ[10]; /**< (USBHS Offset: 0x650) Host Pipe IN Request Register */
+  __I  uint8_t                        Reserved18[8];
+  __IO uint32_t HSTPIPERR[10]; /**< (USBHS Offset: 0x680) Host Pipe Error Register */
+  __I  uint8_t                        Reserved19[104];
+       hstdma_t HSTDMA[7]; /**< Offset: 0x710 Host DMA Channel Next Descriptor Address Register */
+  __I  uint8_t                        Reserved20[128];
+  __IO uint32_t CTRL;     /**< (USBHS Offset: 0x800) General Control Register */
+  __I  uint32_t SR;       /**< (USBHS Offset: 0x804) General Status Register */
+  __O  uint32_t SCR;      /**< (USBHS Offset: 0x808) General Status Clear Register */
+  __O  uint32_t SFR;      /**< (USBHS Offset: 0x80C) General Status Set Register */
+} dcd_registers_t;
+
+#define USB_REG           ((dcd_registers_t *)0x40038000U)         /**< \brief (USBHS) Base Address */
+
+#define EP_MAX            10
+
+#define FIFO_RAM_ADDR     0xA0100000u
+
+// Errata: The DMA feature is not available for Pipe/Endpoint 7
+#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)
+
+#else // TODO : SAM3U
+
+
+#endif
+
+#endif /* _COMMON_USB_REGS_H_ */
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 465c5953b..419265723 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -30,8 +30,8 @@
 #if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMX7X
 
 #include "device/dcd.h"
-
 #include "sam.h"
+#include "common_usb_regs.h"
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
@@ -53,14 +53,7 @@
 #  endif
 #endif
 
-#define EP_MAX            10
-
-#define USBHS_RAM_ADDR  0xA0100000u
-
-#define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
-
-// Errata: The DMA feature is not available for Pipe/Endpoint 7
-#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6)
+#define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale),_t) (*)[0x8000 / ((scale) / 8)])FIFO_RAM_ADDR)[(ep)])
 
 // DMA Channel Transfer Descriptor
 typedef struct {
@@ -145,7 +138,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 void dcd_remote_wakeup (uint8_t rhport)
 {
   (void) rhport;
-  USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP;
+  USB_REG->DEVCTRL |= DEVCTRL_RMWKUP;
 }
 
 // Connect by enabling internal pull-up resistor on D+/D-
@@ -154,28 +147,28 @@ void dcd_connect(uint8_t rhport)
   (void) rhport;
   dcd_int_disable(rhport);
   // Enable the USB controller in device mode
-  USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE;
-  while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+  USB_REG->CTRL = CTRL_UIMOD | CTRL_USBE;
+  while (SR_CLKUSABLE != (USB_REG->SR & SR_CLKUSABLE));
 #if TUD_OPT_HIGH_SPEED
-  USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_SPDCONF_Msk;
+  USB_REG->DEVCTRL &= ~DEVCTRL_SPDCONF;
 #else
-  USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_LOW_POWER;
+  USB_REG->DEVCTRL |= DEVCTRL_SPDCONF_LOW_POWER;
 #endif
   // Enable the End Of Reset, Suspend & Wakeup interrupts
-  USBHS->USBHS_DEVIER = (USBHS_DEVIER_EORSTES | USBHS_DEVIER_SUSPES | USBHS_DEVIER_WAKEUPES);
+  USB_REG->DEVIER = (DEVIER_EORSTES | DEVIER_SUSPES | DEVIER_WAKEUPES);
 #if USE_SOF
-  USBHS->USBHS_DEVIER = USBHS_DEVIER_SOFES;
+  USB_REG->DEVIER = DEVIER_SOFES;
 #endif
   // Clear the End Of Reset, SOF & Wakeup interrupts
-  USBHS->USBHS_DEVICR = (USBHS_DEVICR_EORSTC | USBHS_DEVICR_SOFC | USBHS_DEVICR_WAKEUPC);
+  USB_REG->DEVICR = (DEVICR_EORSTC | DEVICR_SOFC | DEVICR_WAKEUPC);
   // Manually set the Suspend Interrupt
-  USBHS->USBHS_DEVIFR |= USBHS_DEVIFR_SUSPS;
+  USB_REG->DEVIFR |= DEVIFR_SUSPS;
   // Ack the Wakeup Interrupt
-  USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
+  USB_REG->DEVICR = DEVICR_WAKEUPC;
   // Attach the device
-  USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH;
+  USB_REG->DEVCTRL &= ~DEVCTRL_DETACH;
   // Freeze USB clock
-  USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
+  USB_REG->CTRL |= CTRL_FRZCLK;
 }
 
 // Disconnect by disabling internal pull-up resistor on D+/D-
@@ -184,49 +177,49 @@ void dcd_disconnect(uint8_t rhport)
   (void) rhport;
   dcd_int_disable(rhport);
   // Disable all endpoints
-  USBHS->USBHS_DEVEPT &= ~(0x3FF << USBHS_DEVEPT_EPEN0_Pos);
+  USB_REG->DEVEPT &= ~(0x3FF << DEVEPT_EPEN0_Pos);
   // Unfreeze USB clock
-  USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-  while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+  USB_REG->CTRL &= ~CTRL_FRZCLK;
+  while (SR_CLKUSABLE != (USB_REG->SR & SR_CLKUSABLE));
   // Clear all the pending interrupts
-  USBHS->USBHS_DEVICR = USBHS_DEVICR_Msk;
+  USB_REG->DEVICR = DEVICR_Msk;
   // Disable all interrupts
-  USBHS->USBHS_DEVIDR = USBHS_DEVCTRL_UADD_Msk;
+  USB_REG->DEVIDR = DEVIDR_Msk;
   // Detach the device
-  USBHS->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH;
+  USB_REG->DEVCTRL |= DEVCTRL_DETACH;
   // Disable the device address
-  USBHS->USBHS_DEVCTRL &=~(USBHS_DEVCTRL_ADDEN | USBHS_DEVCTRL_UADD_Msk);
+  USB_REG->DEVCTRL &=~(DEVCTRL_ADDEN | DEVCTRL_UADD);
 }
 
 static tusb_speed_t get_speed(void)
 {
-  switch ((USBHS->USBHS_SR & USBHS_SR_SPEED_Msk) >> USBHS_SR_SPEED_Pos) {
-  case USBHS_SR_SPEED_FULL_SPEED_Val:
+  switch ((USB_REG->SR & SR_SPEED) >> SR_SPEED_Pos) {
+  case SR_SPEED_FULL_SPEED:
   default:
     return TUSB_SPEED_FULL;
-  case USBHS_SR_SPEED_HIGH_SPEED_Val:
+  case SR_SPEED_HIGH_SPEED:
     return TUSB_SPEED_HIGH;
-  case USBHS_SR_SPEED_LOW_SPEED_Val:
+  case SR_SPEED_LOW_SPEED:
     return TUSB_SPEED_LOW;
   }
 }
 
 static void dcd_ep_handler(uint8_t ep_ix)
 {
-  uint32_t int_status = USBHS->USBHS_DEVEPTISR[ep_ix];
-  int_status &= USBHS->USBHS_DEVEPTIMR[ep_ix];
+  uint32_t int_status = USB_REG->DEVEPTISR[ep_ix];
+  int_status &= USB_REG->DEVEPTIMR[ep_ix];
 
-  uint16_t count = (USBHS->USBHS_DEVEPTISR[ep_ix] &
-                    USBHS_DEVEPTISR_BYCT_Msk) >> USBHS_DEVEPTISR_BYCT_Pos;
+  uint16_t count = (USB_REG->DEVEPTISR[ep_ix] &
+                    DEVEPTISR_BYCT) >> DEVEPTISR_BYCT_Pos;
   xfer_ctl_t *xfer = &xfer_status[ep_ix];
 
   if (ep_ix == 0U)
   {
     static uint8_t ctrl_dir;
 
-    if (int_status & USBHS_DEVEPTISR_CTRL_RXSTPI)
+    if (int_status & DEVEPTISR_CTRL_RXSTPI)
     {
-      ctrl_dir = (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk) >> USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos;
+      ctrl_dir = (USB_REG->DEVEPTISR[0] & DEVEPTISR_CTRL_CTRLDIR) >> DEVEPTISR_CTRL_CTRLDIR_Pos;
       // Setup packet should always be 8 bytes. If not, ignore it, and try again.
       if (count == 8)
       {
@@ -234,10 +227,10 @@ static void dcd_ep_handler(uint8_t ep_ix)
         dcd_event_setup_received(0, ptr, true);
       }
       // Ack and disable SETUP interrupt
-      USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_CTRL_RXSTPIC;
-      USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_CTRL_RXSTPEC;
+      USB_REG->DEVEPTICR[0] = DEVEPTICR_CTRL_RXSTPIC;
+      USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_RXSTPEC;
     }
-    if (int_status & USBHS_DEVEPTISR_RXOUTI)
+    if (int_status & DEVEPTISR_RXOUTI)
     {
       uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
       
@@ -258,24 +251,24 @@ static void dcd_ep_handler(uint8_t ep_ix)
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
       // Acknowledge the interrupt
-      USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXOUTIC;
+      USB_REG->DEVEPTICR[0] = DEVEPTICR_RXOUTIC;
       if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
       {
         // RX COMPLETE
         dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt
-        USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
+        USB_REG->DEVEPTIDR[0] = DEVEPTIDR_RXOUTEC;
         // Re-enable SETUP interrupt
         if (ctrl_dir == 1)
         {
-          USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
+          USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
         }
       }
     }
-    if (int_status & USBHS_DEVEPTISR_TXINI)
+    if (int_status & DEVEPTISR_TXINI)
     {
       // Disable the interrupt
-      USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
+      USB_REG->DEVEPTIDR[0] = DEVEPTIDR_TXINEC;
       if ((xfer->total_len != xfer->queued_len))
       {
         // TX not complete
@@ -287,13 +280,13 @@ static void dcd_ep_handler(uint8_t ep_ix)
         // Re-enable SETUP interrupt
         if (ctrl_dir == 0)
         {
-          USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
+          USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
         }
       }
     }
   } else 
   {
-    if (int_status & USBHS_DEVEPTISR_RXOUTI)
+    if (int_status & DEVEPTISR_RXOUTI)
     {
       if (count && xfer->total_len)
       {
@@ -312,22 +305,22 @@ static void dcd_ep_handler(uint8_t ep_ix)
         xfer->queued_len = (uint16_t)(xfer->queued_len + count);
       }
       // Clear the FIFO control flag to receive more data.
-      USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
+      USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC;
       // Acknowledge the interrupt
-      USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
+      USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_RXOUTIC;
       if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
       {
         // RX COMPLETE
         dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt
-        USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_RXOUTEC;
+        USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_RXOUTEC;
         // Though the host could still send, we don't know.
       }
     }
-    if (int_status & USBHS_DEVEPTISR_TXINI)
+    if (int_status & DEVEPTISR_TXINI)
     {
       // Acknowledge the interrupt
-      USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
+      USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_TXINIC;
       if ((xfer->total_len != xfer->queued_len))
       {
         // TX not complete
@@ -337,7 +330,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
         // Disable the interrupt
-        USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_TXINEC;
+        USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_TXINEC;
       }
     }
   }
@@ -345,17 +338,17 @@ static void dcd_ep_handler(uint8_t ep_ix)
 
 static void dcd_dma_handler(uint8_t ep_ix)
 {
-  uint32_t status = USBHS->UsbhsDevdma[ep_ix - 1].USBHS_DEVDMASTATUS;
-  if (status & USBHS_DEVDMASTATUS_CHANN_ENB)
+  uint32_t status = USB_REG->DEVDMA[ep_ix - 1].DEVDMASTATUS;
+  if (status & DEVDMASTATUS_CHANN_ENB)
   {
     return; // Ignore EOT_STA interrupt
   }
   // Disable DMA interrupt
-  USBHS->USBHS_DEVIDR = USBHS_DEVIDR_DMA_1 << (ep_ix - 1);
+  USB_REG->DEVIDR = DEVIDR_DMA_1 << (ep_ix - 1);
 
   xfer_ctl_t *xfer = &xfer_status[ep_ix];
-  uint16_t count = xfer->total_len - ((status & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos);
-  if(USBHS->USBHS_DEVEPTCFG[ep_ix] & USBHS_DEVEPTCFG_EPDIR)
+  uint16_t count = xfer->total_len - ((status & DEVDMASTATUS_BUFF_COUNT) >> DEVDMASTATUS_BUFF_COUNT_Pos);
+  if(USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR)
   {
     dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
   } else 
@@ -367,56 +360,56 @@ static void dcd_dma_handler(uint8_t ep_ix)
 void dcd_int_handler(uint8_t rhport)
 {
   (void) rhport;
-  uint32_t int_status = USBHS->USBHS_DEVISR;
-  int_status &= USBHS->USBHS_DEVIMR;
+  uint32_t int_status = USB_REG->DEVISR;
+  int_status &= USB_REG->DEVIMR;
   // End of reset interrupt
-  if (int_status & USBHS_DEVISR_EORST)
+  if (int_status & DEVISR_EORST)
   {
     // Unfreeze USB clock
-    USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-    while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
+    USB_REG->CTRL &= ~CTRL_FRZCLK;
+    while(SR_CLKUSABLE != (USB_REG->SR & SR_CLKUSABLE));
     // Reset all endpoints
     for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++)
     {
-      USBHS->USBHS_DEVEPT |= 1 << (USBHS_DEVEPT_EPRST0_Pos + ep_ix);
-      USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPRST0_Pos + ep_ix));
+      USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + ep_ix);
+      USB_REG->DEVEPT &=~(1 << (DEVEPT_EPRST0_Pos + ep_ix));
     }
     dcd_edpt_open (0, &ep0_desc);
-    USBHS->USBHS_DEVICR = USBHS_DEVICR_EORSTC;
-    USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
-    USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
-    USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
+    USB_REG->DEVICR = DEVICR_EORSTC;
+    USB_REG->DEVICR = DEVICR_WAKEUPC;
+    USB_REG->DEVICR = DEVICR_SUSPC;
+    USB_REG->DEVIER = DEVIER_SUSPES;
 
     dcd_event_bus_reset(rhport, get_speed(), true);
   }
   // End of Wakeup interrupt
-  if (int_status & USBHS_DEVISR_WAKEUP)
+  if (int_status & DEVISR_WAKEUP)
   {
-    USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-    while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
-    USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
-    USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC;
-    USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
+    USB_REG->CTRL &= ~CTRL_FRZCLK;
+    while (SR_CLKUSABLE != (USB_REG->SR & SR_CLKUSABLE));
+    USB_REG->DEVICR = DEVICR_WAKEUPC;
+    USB_REG->DEVIDR = DEVIDR_WAKEUPEC;
+    USB_REG->DEVIER = DEVIER_SUSPES;
 
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
   }
   // Suspend interrupt
-  if (int_status & USBHS_DEVISR_SUSP)
+  if (int_status & DEVISR_SUSP)
   {
     // Unfreeze USB clock
-    USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
-    while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
-    USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
-    USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC;
-    USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES;
-    USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
+    USB_REG->CTRL &= ~CTRL_FRZCLK;
+    while (SR_CLKUSABLE != (USB_REG->SR & SR_CLKUSABLE));
+    USB_REG->DEVICR = DEVICR_SUSPC;
+    USB_REG->DEVIDR = DEVIDR_SUSPEC;
+    USB_REG->DEVIER = DEVIER_WAKEUPES;
+    USB_REG->CTRL |= CTRL_FRZCLK;
 
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 #if USE_SOF
-  if(int_status & USBHS_DEVISR_SOF)
+  if(int_status & DEVISR_SOF)
   {
-    USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC;
+    USB_REG->DEVICR = DEVICR_SOFC;
 
     dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
   }
@@ -424,7 +417,7 @@ void dcd_int_handler(uint8_t rhport)
   // Endpoints interrupt
   for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
   {
-    if (int_status & (USBHS_DEVISR_PEP_0 << ep_ix))
+    if (int_status & (DEVISR_PEP_0 << ep_ix))
     {
       dcd_ep_handler(ep_ix);
     }
@@ -434,7 +427,7 @@ void dcd_int_handler(uint8_t rhport)
   {
     if (EP_DMA_SUPPORT(ep_ix))
     {
-      if (int_status & (USBHS_DEVISR_DMA_1 << (ep_ix - 1)))
+      if (int_status & (DEVISR_DMA_1 << (ep_ix - 1)))
       {
         dcd_dma_handler(ep_ix);
       }
@@ -457,7 +450,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
   {
     uint8_t const dev_addr = (uint8_t) request->wValue;
 
-    USBHS->USBHS_DEVCTRL |= dev_addr | USBHS_DEVCTRL_ADDEN;
+    USB_REG->DEVCTRL |= dev_addr | DEVCTRL_ADDEN;
   }
 }
 
@@ -482,29 +475,29 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   }
   xfer_status[epnum].max_packet_size = epMaxPktSize;
 
-  USBHS->USBHS_DEVEPT |= 1 << (USBHS_DEVEPT_EPRST0_Pos + epnum);
-  USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPRST0_Pos + epnum));
+  USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + epnum);
+  USB_REG->DEVEPT &=~(1 << (DEVEPT_EPRST0_Pos + epnum));
 
   if (epnum == 0)
   {
     // Enable the control endpoint - Endpoint 0
-    USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
+    USB_REG->DEVEPT |= DEVEPT_EPEN0;
     // Configure the Endpoint 0 configuration register
-    USBHS->USBHS_DEVEPTCFG[0] =
+    USB_REG->DEVEPTCFG[0] =
       (
-       USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
-       USBHS_DEVEPTCFG_EPTYPE(TUSB_XFER_CONTROL) |
-       USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
-       USBHS_DEVEPTCFG_ALLOC
+       (fifoSize << DEVEPTCFG_EPSIZE_Pos)            |
+       (TUSB_XFER_CONTROL << DEVEPTCFG_EPTYPE_Pos)   |
+       (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) |
+       DEVEPTCFG_ALLOC
        );
-    USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_RSTDTS;
-    USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_CTRL_STALLRQC;
-    if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK))
+    USB_REG->DEVEPTIER[0] = DEVEPTIER_RSTDTS;
+    USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_STALLRQC;
+    if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[0] & DEVEPTISR_CFGOK))
     {
       // Endpoint configuration is successful
-      USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
+      USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
       // Enable Endpoint 0 Interrupts
-      USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
+      USB_REG->DEVIER = DEVIER_PEP_0;
       return true;
     } else 
     {
@@ -514,34 +507,34 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   } else 
   {
     // Enable the endpoint
-    USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
+    USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos);
     // Set up the maxpacket size, fifo start address fifosize
     // and enable the interrupt. CLear the data toggle.
     // AUTOSW is needed for DMA ack !
-    USBHS->USBHS_DEVEPTCFG[epnum] =
+    USB_REG->DEVEPTCFG[epnum] =
       (
-       USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
-       USBHS_DEVEPTCFG_EPTYPE(eptype) |
-       USBHS_DEVEPTCFG_EPBK(USBHS_DEVEPTCFG_EPBK_1_BANK) |
-       USBHS_DEVEPTCFG_AUTOSW |
-       ((dir & 0x01) << USBHS_DEVEPTCFG_EPDIR_Pos)
+       (fifoSize << DEVEPTCFG_EPSIZE_Pos)            |
+       (eptype  << DEVEPTCFG_EPTYPE_Pos)             |
+       (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) |
+       DEVEPTCFG_AUTOSW |
+       ((dir & 0x01) << DEVEPTCFG_EPDIR_Pos)
        );
     if (eptype == TUSB_XFER_ISOCHRONOUS)
     {
-      USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1);
+      USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_NBTRANS_1_TRANS;
     }
 #if USE_DUAL_BANK
     if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK)
     {
-      USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_EPBK_2_BANK;
+      USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_EPBK_2_BANK;
     }
 #endif
-    USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_ALLOC;
-    USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RSTDTS;
-    USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_CTRL_STALLRQC;
-    if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[epnum] & USBHS_DEVEPTISR_CFGOK))
+    USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_ALLOC;
+    USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RSTDTS;
+    USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC;
+    if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[epnum] & DEVEPTISR_CFGOK))
     {
-      USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
+      USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos);
       return true;
     } else 
     {
@@ -557,9 +550,9 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   uint8_t const epnum  = tu_edpt_number(ep_addr);
 
   // Disable endpoint interrupt
-  USBHS->USBHS_DEVIDR = 1 << (USBHS_DEVIDR_PEP_0_Pos + epnum);
+  USB_REG->DEVIDR = 1 << (DEVIDR_PEP_0_Pos + epnum);
   // Disable EP
-  USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPEN0_Pos + epnum));
+  USB_REG->DEVEPT &=~(1 << (DEVEPT_EPEN0_Pos + epnum));
 }
 
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
@@ -587,13 +580,13 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
   if (ep_ix == 0U)
   {
     // Control endpoint: clear the interrupt flag to send the data
-    USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
+    USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC;
   } else 
   {
     // Other endpoint types: clear the FIFO control flag to send the data
-    USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
+    USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC;
   }
-  USBHS->USBHS_DEVEPTIER[ep_ix] = USBHS_DEVEPTIER_TXINES;
+  USB_REG->DEVEPTIER[ep_ix] = DEVEPTIER_TXINES;
 }
 
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
@@ -615,23 +608,23 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
     // address to 32-byte boundaries.
     CleanInValidateCache((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31);
-    uint32_t udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
+    uint32_t udd_dma_ctrl = total_bytes << DEVDMACONTROL_BUFF_LENGTH_Pos;
     if (dir == TUSB_DIR_OUT)
     {
-      udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_TR_IT | USBHS_DEVDMACONTROL_END_TR_EN;
+      udd_dma_ctrl |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN;
     } else {
-      udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_B_EN;
+      udd_dma_ctrl |= DEVDMACONTROL_END_B_EN;
     }
-    USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)buffer;
-    udd_dma_ctrl |= USBHS_DEVDMACONTROL_END_BUFFIT | USBHS_DEVDMACONTROL_CHANN_ENB;
+    USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)buffer;
+    udd_dma_ctrl |= DEVDMACONTROL_END_BUFFIT | DEVDMACONTROL_CHANN_ENB;
     // Disable IRQs to have a short sequence
     // between read of EOT_STA and DMA enable
     uint32_t irq_state = __get_PRIMASK();
     __disable_irq();
-    if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST))
+    if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST))
     {
-      USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMACONTROL = udd_dma_ctrl;
-      USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << (epnum - 1);
+      USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl;
+      USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1);
       __set_PRIMASK(irq_state);
       return true;
     }
@@ -645,7 +638,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   {
     if (dir == TUSB_DIR_OUT)
     {
-      USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
+      USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
     } else 
     {
       dcd_transmit_packet(xfer,epnum);
@@ -676,26 +669,26 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {
     tu_fifo_buffer_info_t info;
-    uint32_t udd_dma_ctrl_lin = USBHS_DEVDMACONTROL_CHANN_ENB;
-    uint32_t udd_dma_ctrl_wrap = USBHS_DEVDMACONTROL_CHANN_ENB | USBHS_DEVDMACONTROL_END_BUFFIT;
+    uint32_t udd_dma_ctrl_lin = DEVDMACONTROL_CHANN_ENB;
+    uint32_t udd_dma_ctrl_wrap = DEVDMACONTROL_CHANN_ENB | DEVDMACONTROL_END_BUFFIT;
     if (dir == TUSB_DIR_OUT)
     {
       tu_fifo_get_write_info(ff, &info);
-      udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_END_TR_IT | USBHS_DEVDMACONTROL_END_TR_EN;
-      udd_dma_ctrl_wrap |= USBHS_DEVDMACONTROL_END_TR_IT | USBHS_DEVDMACONTROL_END_TR_EN;
+      udd_dma_ctrl_lin |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN;
+      udd_dma_ctrl_wrap |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN;
     } else {
       tu_fifo_get_read_info(ff, &info);
       if(info.len_wrap == 0)
       {
-        udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_END_B_EN;
+        udd_dma_ctrl_lin |= DEVDMACONTROL_END_B_EN;
       }
-      udd_dma_ctrl_wrap |= USBHS_DEVDMACONTROL_END_B_EN;
+      udd_dma_ctrl_wrap |= DEVDMACONTROL_END_B_EN;
     }
 
     // Clean invalidate cache of linear part
     CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31);
     
-    USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)info.ptr_lin;
+    USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.ptr_lin;
     if (info.len_wrap)
     {
       // Clean invalidate cache of wrapped part
@@ -704,24 +697,24 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
       dma_desc[epnum - 1].next_desc = 0;
       dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
       dma_desc[epnum - 1].chnl_ctrl =
-        udd_dma_ctrl_wrap | USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_wrap);
+        udd_dma_ctrl_wrap | (info.len_wrap << DEVDMACONTROL_BUFF_LENGTH_Pos);
       // Clean cache of wrapped DMA descriptor
       CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t));
       
-      udd_dma_ctrl_lin |= USBHS_DEVDMASTATUS_DESC_LDST;
-      USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
+      udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST;
+      USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
     } else {
-      udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_END_BUFFIT;
+      udd_dma_ctrl_lin |= DEVDMACONTROL_END_BUFFIT;
     }
-    udd_dma_ctrl_lin |= USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_lin);
+    udd_dma_ctrl_lin |= (info.len_lin << DEVDMACONTROL_BUFF_LENGTH_Pos);
     // Disable IRQs to have a short sequence
     // between read of EOT_STA and DMA enable
     uint32_t irq_state = __get_PRIMASK();
     __disable_irq();
-    if (!(USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_END_TR_ST))
+    if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST))
     {
-      USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMACONTROL = udd_dma_ctrl_lin;
-      USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << (epnum - 1);
+      USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl_lin;
+      USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1);
       __set_PRIMASK(irq_state);
       return true;
     }
@@ -735,7 +728,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   {
     if (dir == TUSB_DIR_OUT)
     {
-      USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_RXOUTES;
+      USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
     } else 
     {
       dcd_transmit_packet(xfer,epnum);
@@ -749,11 +742,11 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  USBHS->USBHS_DEVEPTIER[epnum] = USBHS_DEVEPTIER_CTRL_STALLRQS;
+  USB_REG->DEVEPTIER[epnum] = DEVEPTIER_CTRL_STALLRQS;
   // Re-enable SETUP interrupt
   if (epnum == 0)
   {
-    USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
+    USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES;
   }
 }
 
@@ -762,8 +755,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_addr);
-  USBHS->USBHS_DEVEPTIDR[epnum] = USBHS_DEVEPTIDR_CTRL_STALLRQC;
-  USBHS->USBHS_DEVEPTIER[epnum] = USBHS_HSTPIPIER_RSTDTS;
+  USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC;
+  USB_REG->DEVEPTIER[epnum] = HSTPIPIER_RSTDTS;
 }
 
 #endif

From 45e55a8ea05d1101626addb74c9a2059030f6ff2 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 31 Jul 2021 12:20:19 +0900
Subject: [PATCH 0284/2085] fix: D0FIFOSEL setting was incorrectly when
 big-endian is selected.

In pipe_xfer_in(), the endianness setting of D0FIFOSEL was lacking due to refactoring.
And add type cast operation to avoid warnings by CCRX.
---
 src/portable/renesas/usba/dcd_usba.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 09622d894..739861413 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -313,9 +313,9 @@ static bool pipe0_xfer_in(void)
   void          *buf = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, &USB0.CFIFO.WORD, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, &USB0.CFIFO.WORD, len);
+      pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -335,9 +335,9 @@ static bool pipe0_xfer_out(void)
   void          *buf = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, &USB0.CFIFO.WORD, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, &USB0.CFIFO.WORD, len);
+      pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -360,16 +360,16 @@ static bool pipe_xfer_in(unsigned num)
     return true;
   }
 
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16;
+  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
   const unsigned len  = TU_MIN(rem, mps);
   void          *buf  = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, &USB0.D0FIFO.WORD, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, &USB0.D0FIFO.WORD, len);
+      pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -393,9 +393,9 @@ static bool pipe_xfer_out(unsigned num)
   void          *buf  = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, &USB0.D0FIFO.WORD, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, &USB0.D0FIFO.WORD, len);
+      pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -488,6 +488,7 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
       pipe_wait_for_ready(num);
       USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
       USB0.D0FIFOSEL.WORD = 0;
+      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
     }
   } else {
     volatile reg_pipetre_t *pt = get_pipetre(num);

From 98e4ba6a12f8ce2b060635dc01f68676b047ce25 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 2 Aug 2021 18:55:12 +0700
Subject: [PATCH 0285/2085] correct midi available with already stream read

---
 src/class/midi/midi_device.c | 7 ++++++-
 src/common/tusb_fifo.c       | 2 --
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index c39e03976..9d9619132 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -122,7 +122,12 @@ static void _prep_out_transaction (midid_interface_t* p_midi)
 uint32_t tud_midi_n_available(uint8_t itf, uint8_t cable_num)
 {
   (void) cable_num;
-  return tu_fifo_count(&_midid_itf[itf].rx_ff);
+
+  midid_interface_t const* midi = &_midid_itf[itf];
+  midid_stream_t const* stream = &midi->stream_read;
+
+  // when using with packet API stream total & index are both zero
+  return tu_fifo_count(&midi->rx_ff) + (stream->total - stream->index);
 }
 
 uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, uint32_t bufsize)
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 73217cf75..11b8fc5f3 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -323,8 +323,6 @@ static uint16_t advance_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
   // We limit the index space of p such that a correct wrap around happens
   // Check for a wrap around or if we are in unused index space - This has to be checked first!!
   // We are exploiting the wrap around to the correct index
-
-  // TODO warning: assuming signed overflow does not occur when assuming that (X + c) < X is always false [-Wstrict-overflow]
   if ((p > (uint16_t)(p + offset)) || ((uint16_t)(p + offset) > f->max_pointer_idx))
   {
     p = (p + offset) + f->non_used_index_space;

From 794bbd7177dd5f3cab35eadf9a9268eddf61736f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 2 Aug 2021 18:58:27 +0700
Subject: [PATCH 0286/2085] fix warning

---
 src/class/midi/midi_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 9d9619132..eb85b668c 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -123,7 +123,7 @@ uint32_t tud_midi_n_available(uint8_t itf, uint8_t cable_num)
 {
   (void) cable_num;
 
-  midid_interface_t const* midi = &_midid_itf[itf];
+  midid_interface_t* midi = &_midid_itf[itf];
   midid_stream_t const* stream = &midi->stream_read;
 
   // when using with packet API stream total & index are both zero

From bece3bca088dd3f5c1e909d142b0b47c0e2ca2f9 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Mon, 2 Aug 2021 20:20:23 +0200
Subject: [PATCH 0287/2085] Add @HiFiPhile in CONTRIBUTORS.rst

---
 CONTRIBUTORS.rst | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index 4466fdd8e..040f40166 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -177,5 +177,13 @@ Notable contributors
    v1.1, msp\_exp430f5529lp etc ...
 
 
+`Zixun Li <https://github.com/HiFiPhile>`__
+-----------------------------------------------
+
+-  Add new DCD port for Microchip SAMx7x
+-  Add IAR compiler support
+-  Improve UAC2, CDC, DFU class driver
+
+
 `Full contributors list <https://github.com/hathach/tinyusb/contributors>`__
 ============================================================================

From b682ce916a4284fc94cc37bb0478506cda40c375 Mon Sep 17 00:00:00 2001
From: Peter Lawrence <12226419+majbthrd@users.noreply.github.com>
Date: Mon, 2 Aug 2021 20:52:45 -0500
Subject: [PATCH 0288/2085] net_lwip_webserver: utilize pbuf_copy_partial()

---
 examples/device/net_lwip_webserver/src/main.c | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 27adce86f..7c0adae01 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -178,21 +178,12 @@ bool tud_network_recv_cb(const uint8_t *src, uint16_t size)
 uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg)
 {
   struct pbuf *p = (struct pbuf *)ref;
-  struct pbuf *q;
-  uint16_t len = 0;
 
   (void)arg; /* unused for this example */
 
-  /* traverse the "pbuf chain"; see ./lwip/src/core/pbuf.c for more info */
-  for(q = p; q != NULL; q = q->next)
-  {
-    memcpy(dst, (char *)q->payload, q->len);
-    dst += q->len;
-    len += q->len;
-    if (q->len == q->tot_len) break;
-  }
+  pbuf_copy_partial(p, dst, p->tot_len, 0);
 
-  return len;
+  return p->tot_len;
 }
 
 static void service_traffic(void)

From 6805c9d7349ed85c48714fc3285bb6f88bcd9f97 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 3 Aug 2021 16:36:03 +0700
Subject: [PATCH 0289/2085] add back info to readme, use stack.svg

---
 README.rst               |  78 +++++++++++++++++++++++++++++++++++++++
 docs/assets/stack.png    | Bin 63797 -> 0 bytes
 docs/assets/stack.svg    |   1 +
 docs/reference/index.rst |   7 +---
 4 files changed, 80 insertions(+), 6 deletions(-)
 delete mode 100644 docs/assets/stack.png
 create mode 100644 docs/assets/stack.svg

diff --git a/README.rst b/README.rst
index b738c7894..6de51535b 100644
--- a/README.rst
+++ b/README.rst
@@ -10,6 +10,84 @@ the non-ISR task function.
 
 Please take a look at the online `documentation <www.tinyusb.org>`__.
 
+.. figure:: docs/assets/stack.svg
+   :width: 500px
+   :alt: stackup
+
+::
+
+	.
+	├── docs            # Documentation
+	├── examples        # Sample with Makefile build support
+	├── hw
+	│   ├── bsp         # Supported boards source files
+	│   └── mcu         # Low level mcu core & peripheral drivers
+	├── lib             # Sources from 3rd party such as freeRTOS, fatfs ...
+	├── src             # All sources files for TinyUSB stack itself.
+	├── test            # Unit tests for the stack
+	└── tools           # Files used internally
+
+Supported MCUs
+==============
+
+The stack supports the following MCUs:
+
+- **Dialog:** DA1469x
+- **Espressif:** ESP32-S2, ESP32-S3
+- **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAME7x
+- **NordicSemi:** nRF52833, nRF52840
+- **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
+- **NXP:**
+
+  - iMX RT Series: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
+  - Kinetis: KL25
+  - LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
+
+- **Raspberry Pi:** RP2040
+- **Renesas:** RX63N, RX65N
+- **Silabs:** EFM32GG12
+- **Sony:** CXD56
+- **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
+- **TI:** MSP430
+- **ValentyUSB:** eptri
+
+Here is the list of `Supported Devices`_ that can be used with provided examples.
+
+Device Stack
+============
+
+Supports multiple device configurations by dynamically changing usb descriptors. Low power functions such like suspend, resume, and remote wakeup. Following device classes are supported:
+
+-  Audio Class 2.0 (UAC2)
+-  Bluetooth Host Controller Interface (BTH HCI)
+-  Communication Class (CDC)
+-  Device Firmware Update (DFU): DFU mode (WIP) and Runtinme
+-  Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ...
+-  Mass Storage Class (MSC): with multiple LUNs
+-  Musical Instrument Digital Interface (MIDI)
+-  Network with RNDIS, CDC-ECM (work in progress)
+-  USB Test and Measurement Class (USBTMC)
+-  Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file.
+-  `WebUSB <https://github.com/WICG/webusb>`__ with vendor-specific class
+
+If you have special need, `usbd_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. Here is how RPi team add their reset interface [raspberrypi/pico-sdk#197](https://github.com/raspberrypi/pico-sdk/pull/197)
+
+Host Stack
+==========
+
+- Human Interface Device (HID): Keyboard, Mouse, Generic
+- Mass Storage Class (MSC)
+- Hub currently only supports 1 level of hub (due to my laziness)
+
+OS Abstraction layer
+====================
+
+TinyUSB is completely thread-safe by pushing all ISR events into a central queue, then process it later in the non-ISR context task function. It also uses semaphore/mutex to access shared resources such as CDC FIFO. Therefore the stack needs to use some of OS's basic APIs. Following OSes are already supported out of the box.
+
+- **No OS**
+- **FreeRTOS**
+- **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its [own repo](https://github.com/hathach/mynewt-tinyusb-example)
+
 Local Docs
 ==========
 
diff --git a/docs/assets/stack.png b/docs/assets/stack.png
deleted file mode 100644
index 3a9e1c7fc5bdc72e111b64a468e94a09a3415510..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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\ No newline at end of file
diff --git a/docs/reference/index.rst b/docs/reference/index.rst
index 5da51d71a..fcff03590 100644
--- a/docs/reference/index.rst
+++ b/docs/reference/index.rst
@@ -2,7 +2,7 @@
 Reference
 *********
 
-.. figure:: ../assets/stack.png
+.. figure:: ../assets/stack.svg
    :width: 1600px
    :alt: stackup
 
@@ -30,11 +30,6 @@ If you have special need, `usbd_app_driver_get_cb()` can be used to write your o
 Host Stack
 ==========
 
-.. admonition:: Warning
-   :class: warning
-
-   Most active development is on the Device stack. The Host stack is under rework and largely untested.
-
 - Human Interface Device (HID): Keyboard, Mouse, Generic
 - Mass Storage Class (MSC)
 - Hub currently only supports 1 level of hub (due to my laziness)

From 2657560b633b877fc393787755e9b1ec8dfbe843 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Fri, 9 Jul 2021 23:39:41 +0200
Subject: [PATCH 0290/2085] Add hacky GD32VF103 support

---
 src/portable/st/synopsys/dcd_synopsys.c    |   17 +-
 src/portable/st/synopsys/synopsys_common.h | 1448 ++++++++++++++++++++
 src/tusb_option.h                          |    3 +
 3 files changed, 1466 insertions(+), 2 deletions(-)
 create mode 100644 src/portable/st/synopsys/synopsys_common.h

diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index c15694eba..4b39844a1 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -34,7 +34,7 @@
 #define USE_SOF     0
 
 #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
-    defined (STM32F107xB) || defined (STM32F107xC)
+    defined (STM32F107xB) || defined (STM32F107xC) || defined (GD32VF103)
 #define STM32F1_SYNOPSYS
 #endif
 
@@ -51,7 +51,8 @@
        CFG_TUSB_MCU == OPT_MCU_STM32F4                               || \
        CFG_TUSB_MCU == OPT_MCU_STM32F7                               || \
        CFG_TUSB_MCU == OPT_MCU_STM32H7                               || \
-      (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS))    \
+      (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)  || \
+       CFG_TUSB_MCU == OPT_MCU_GD32VF103 )                           \
     )
 
 // EP_MAX       : Max number of bi-directional endpoints including EP0
@@ -92,6 +93,18 @@
 #define EP_MAX_FS       6
 #define EP_FIFO_SIZE_FS 1280
 
+#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
+#define STM32F1_SYNOPSYS
+#include "gd32vf103.h"
+#include "nmsis_core.h"
+#include "core_feature_eclic.h"
+#include "synopsys_common.h"
+#define EP_MAX_FS       4
+#define EP_FIFO_SIZE_FS 1280
+#define OTG_FS_IRQn USBFS_IRQn
+#define NVIC_EnableIRQ ECLIC_EnableIRQ
+#define NVIC_DisableIRQ ECLIC_DisableIRQ
+
 #else
 #error "Unsupported MCUs"
 #endif
diff --git a/src/portable/st/synopsys/synopsys_common.h b/src/portable/st/synopsys/synopsys_common.h
new file mode 100644
index 000000000..4e71e8258
--- /dev/null
+++ b/src/portable/st/synopsys/synopsys_common.h
@@ -0,0 +1,1448 @@
+#include "stdint.h"
+
+#pragma once
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+/** 
+  * @brief __USB_OTG_Core_register
+  */
+
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register       Address offset: 000h */
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                Address offset: 004h */
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register           Address offset: 008h */
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register           Address offset: 00Ch */
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                       Address offset: 010h */
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                   Address offset: 014h */
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register              Address offset: 018h */
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register               Address offset: 01Ch */
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register         Address offset: 020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                 Address offset: 024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register  Address offset: 028h */
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg        Address offset: 02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved 030h*/
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                Address offset: 038h */
+  __IO uint32_t CID;                  /*!< User ID Register                           Address offset: 03Ch */
+  uint32_t  Reserved40[48];           /*!< Reserved 040h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg             Address offset: 100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                 Address offset: 0x104 */
+} USB_OTG_GlobalTypeDef;
+
+/** 
+  * @brief __device_Registers
+  */
+
+typedef struct 
+{
+  __IO uint32_t DCFG;                 /*!< dev Configuration Register                 Address offset: 800h*/
+  __IO uint32_t DCTL;                 /*!< dev Control Register                       Address offset: 804h*/
+  __IO uint32_t DSTS;                 /*!< dev Status Register (RO)                   Address offset: 808h*/
+  uint32_t Reserved0C;                /*!< Reserved 80Ch*/
+  __IO uint32_t DIEPMSK;              /*!< dev IN Endpoint Mask                       Address offset: 810h*/
+  __IO uint32_t DOEPMSK;              /*!< dev OUT Endpoint Mask                      Address offset: 814h*/
+  __IO uint32_t DAINT;                /*!< dev All Endpoints Itr Reg                  Address offset: 818h*/
+  __IO uint32_t DAINTMSK;             /*!< dev All Endpoints Itr Mask                 Address offset: 81Ch*/
+  uint32_t  Reserved20;               /*!< Reserved 820h*/
+  uint32_t Reserved9;                 /*!< Reserved 824h*/
+  __IO uint32_t DVBUSDIS;             /*!< dev VBUS discharge Register                Address offset: 828h*/
+  __IO uint32_t DVBUSPULSE;           /*!< dev VBUS Pulse Register                    Address offset: 82Ch*/
+  __IO uint32_t DTHRCTL;              /*!< dev thr                                    Address offset: 830h*/
+  __IO uint32_t DIEPEMPMSK;           /*!< dev empty msk                              Address offset: 834h*/
+  __IO uint32_t DEACHINT;             /*!< dedicated EP interrupt                     Address offset: 838h*/
+  __IO uint32_t DEACHMSK;             /*!< dedicated EP msk                           Address offset: 83Ch*/  
+  uint32_t Reserved40;                /*!< dedicated EP mask                          Address offset: 840h*/
+  __IO uint32_t DINEP1MSK;            /*!< dedicated EP mask                          Address offset: 844h*/
+  uint32_t  Reserved44[15];           /*!< Reserved 844-87Ch*/
+  __IO uint32_t DOUTEP1MSK;           /*!< dedicated EP msk                           Address offset: 884h*/
+} USB_OTG_DeviceTypeDef;
+
+/** 
+  * @brief __IN_Endpoint-Specific_Register
+  */
+
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;              /*!< dev IN Endpoint Control Reg                900h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;                /*!< Reserved                                   900h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DIEPINT;              /*!< dev IN Endpoint Itr Reg                    900h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;                /*!< Reserved                                   900h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DIEPTSIZ;             /*!< IN Endpoint Txfer Size                     900h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DIEPDMA;              /*!< IN Endpoint DMA Address Reg                900h + (ep_num * 20h) + 14h*/
+  __IO uint32_t DTXFSTS;              /*!< IN Endpoint Tx FIFO Status Reg             900h + (ep_num * 20h) + 18h*/
+  uint32_t Reserved18;                /*!< Reserved                                   900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/** 
+  * @brief __OUT_Endpoint-Specific_Registers
+  */
+
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;              /*!< dev OUT Endpoint Control Reg               B00h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;                /*!< Reserved                                   B00h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DOEPINT;              /*!< dev OUT Endpoint Itr Reg                   B00h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;                /*!< Reserved                                   B00h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DOEPTSIZ;             /*!< dev OUT Endpoint Txfer Size                B00h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DOEPDMA;              /*!< dev OUT Endpoint DMA Address               B00h + (ep_num * 20h) + 14h*/
+  uint32_t Reserved18[2];             /*!< Reserved                                   B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/** 
+  * @brief __Host_Mode_Register_Structures
+  */
+
+typedef struct 
+{
+  __IO uint32_t HCFG;                 /*!< Host Configuration Register    400h*/
+  __IO uint32_t HFIR;                 /*!< Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;               /*!< Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief __Host_Channel_Specific_Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t HCCHAR;
+  __IO uint32_t HCSPLT;
+  __IO uint32_t HCINT;
+  __IO uint32_t HCINTMSK;
+  __IO uint32_t HCTSIZ;
+  __IO uint32_t HCDMA;
+  uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE                  0x00000000UL
+#define USB_OTG_DEVICE_BASE                  0x00000800UL
+#define USB_OTG_IN_ENDPOINT_BASE             0x00000900UL
+#define USB_OTG_OUT_ENDPOINT_BASE            0x00000B00UL
+#define USB_OTG_EP_REG_SIZE                  0x00000020UL
+#define USB_OTG_HOST_BASE                    0x00000400UL
+#define USB_OTG_HOST_PORT_BASE               0x00000440UL
+#define USB_OTG_HOST_CHANNEL_BASE            0x00000500UL
+#define USB_OTG_HOST_CHANNEL_SIZE            0x00000020UL
+#define USB_OTG_PCGCCTL_BASE                 0x00000E00UL
+#define USB_OTG_FIFO_BASE                    0x00001000UL
+#define USB_OTG_FIFO_SIZE                    0x00001000UL
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 USB_OTG                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos              (0U)                           
+#define USB_OTG_GOTGCTL_SRQSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                  USB_OTG_GOTGCTL_SRQSCS_Msk     /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                 (1U)                           
+#define USB_OTG_GOTGCTL_SRQ_Msk                 (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                     USB_OTG_GOTGCTL_SRQ_Msk        /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos              (8U)                           
+#define USB_OTG_GOTGCTL_HNGSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos               (9U)                           
+#define USB_OTG_GOTGCTL_HNPRQ_Msk               (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                   USB_OTG_GOTGCTL_HNPRQ_Msk      /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos             (10U)                          
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk             (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                 USB_OTG_GOTGCTL_HSHNPEN_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos              (11U)                          
+#define USB_OTG_GOTGCTL_DHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                  USB_OTG_GOTGCTL_DHNPEN_Msk     /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos              (16U)                          
+#define USB_OTG_GOTGCTL_CIDSTS_Msk              (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                  USB_OTG_GOTGCTL_CIDSTS_Msk     /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                (17U)                          
+#define USB_OTG_GOTGCTL_DBCT_Msk                (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                    USB_OTG_GOTGCTL_DBCT_Msk       /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos               (18U)                          
+#define USB_OTG_GOTGCTL_ASVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                   USB_OTG_GOTGCTL_ASVLD_Msk      /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos               (19U)                          
+#define USB_OTG_GOTGCTL_BSVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD                   USB_OTG_GOTGCTL_BSVLD_Msk      /*!< B-session valid */
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                (0U)                           
+#define USB_OTG_HCFG_FSLSPCS_Msk                (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                    USB_OTG_HCFG_FSLSPCS_Msk       /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0                  (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                  (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                  (2U)                           
+#define USB_OTG_HCFG_FSLSS_Msk                  (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                      USB_OTG_HCFG_FSLSS_Msk         /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                   (0U)                           
+#define USB_OTG_DCFG_DSPD_Msk                   (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                       USB_OTG_DCFG_DSPD_Msk          /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                     (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                     (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos               (2U)                           
+#define USB_OTG_DCFG_NZLSOHSK_Msk               (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                   USB_OTG_DCFG_NZLSOHSK_Msk      /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                    (4U)                           
+#define USB_OTG_DCFG_DAD_Msk                    (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                        USB_OTG_DCFG_DAD_Msk           /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                      (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                      (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                      (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                      (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                      (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                      (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                      (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                  (11U)                          
+#define USB_OTG_DCFG_PFIVL_Msk                  (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                      USB_OTG_DCFG_PFIVL_Msk         /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                    (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                    (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos              (24U)                          
+#define USB_OTG_DCFG_PERSCHIVL_Msk              (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                  USB_OTG_DCFG_PERSCHIVL_Msk     /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos               (0U)                           
+#define USB_OTG_PCGCR_STPPCLK_Msk               (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                   USB_OTG_PCGCR_STPPCLK_Msk      /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos              (1U)                           
+#define USB_OTG_PCGCR_GATEHCLK_Msk              (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                  USB_OTG_PCGCR_GATEHCLK_Msk     /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos               (4U)                           
+#define USB_OTG_PCGCR_PHYSUSP_Msk               (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                   USB_OTG_PCGCR_PHYSUSP_Msk      /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos               (2U)                           
+#define USB_OTG_GOTGINT_SEDET_Msk               (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                   USB_OTG_GOTGINT_SEDET_Msk      /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos             (8U)                           
+#define USB_OTG_GOTGINT_SRSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                 USB_OTG_GOTGINT_SRSSCHG_Msk    /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos             (9U)                           
+#define USB_OTG_GOTGINT_HNSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                 USB_OTG_GOTGINT_HNSSCHG_Msk    /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos              (17U)                          
+#define USB_OTG_GOTGINT_HNGDET_Msk              (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                  USB_OTG_GOTGINT_HNGDET_Msk     /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos             (18U)                          
+#define USB_OTG_GOTGINT_ADTOCHG_Msk             (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                 USB_OTG_GOTGINT_ADTOCHG_Msk    /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos              (19U)                          
+#define USB_OTG_GOTGINT_DBCDNE_Msk              (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                  USB_OTG_GOTGINT_DBCDNE_Msk     /*!< Debounce done */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                 (0U)                           
+#define USB_OTG_DCTL_RWUSIG_Msk                 (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                     USB_OTG_DCTL_RWUSIG_Msk        /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                   (1U)                           
+#define USB_OTG_DCTL_SDIS_Msk                   (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                       USB_OTG_DCTL_SDIS_Msk          /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos                 (2U)                           
+#define USB_OTG_DCTL_GINSTS_Msk                 (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                     USB_OTG_DCTL_GINSTS_Msk        /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos                 (3U)                           
+#define USB_OTG_DCTL_GONSTS_Msk                 (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                     USB_OTG_DCTL_GONSTS_Msk        /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos                   (4U)                           
+#define USB_OTG_DCTL_TCTL_Msk                   (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                       USB_OTG_DCTL_TCTL_Msk          /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                     (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                     (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                     (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                 (7U)                           
+#define USB_OTG_DCTL_SGINAK_Msk                 (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                     USB_OTG_DCTL_SGINAK_Msk        /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos                 (8U)                           
+#define USB_OTG_DCTL_CGINAK_Msk                 (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                     USB_OTG_DCTL_CGINAK_Msk        /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos                 (9U)                           
+#define USB_OTG_DCTL_SGONAK_Msk                 (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                     USB_OTG_DCTL_SGONAK_Msk        /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos                 (10U)                          
+#define USB_OTG_DCTL_CGONAK_Msk                 (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                     USB_OTG_DCTL_CGONAK_Msk        /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos               (11U)                          
+#define USB_OTG_DCTL_POPRGDNE_Msk               (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                   USB_OTG_DCTL_POPRGDNE_Msk      /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                  (0U)                           
+#define USB_OTG_HFIR_FRIVL_Msk                  (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                      USB_OTG_HFIR_FRIVL_Msk         /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                 (0U)                           
+#define USB_OTG_HFNUM_FRNUM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                     USB_OTG_HFNUM_FRNUM_Msk        /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos                 (16U)                          
+#define USB_OTG_HFNUM_FTREM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                     USB_OTG_HFNUM_FTREM_Msk        /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                (0U)                           
+#define USB_OTG_DSTS_SUSPSTS_Msk                (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                    USB_OTG_DSTS_SUSPSTS_Msk       /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                (1U)                           
+#define USB_OTG_DSTS_ENUMSPD_Msk                (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                    USB_OTG_DSTS_ENUMSPD_Msk       /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                  (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                  (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                   (3U)                           
+#define USB_OTG_DSTS_EERR_Msk                   (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                       USB_OTG_DSTS_EERR_Msk          /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos                  (8U)                           
+#define USB_OTG_DSTS_FNSOF_Msk                  (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                      USB_OTG_DSTS_FNSOF_Msk         /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                (0U)                           
+#define USB_OTG_GAHBCFG_GINT_Msk                (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                    USB_OTG_GAHBCFG_GINT_Msk       /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)                           
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk             (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                 USB_OTG_GAHBCFG_HBSTLEN_Msk    /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)                           
+#define USB_OTG_GAHBCFG_DMAEN_Msk               (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                   USB_OTG_GAHBCFG_DMAEN_Msk      /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos             (7U)                           
+#define USB_OTG_GAHBCFG_TXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                 USB_OTG_GAHBCFG_TXFELVL_Msk    /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos            (8U)                           
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk            (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                USB_OTG_GAHBCFG_PTXFELVL_Msk   /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos               (0U)                           
+#define USB_OTG_GUSBCFG_TOCAL_Msk               (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                   USB_OTG_GUSBCFG_TOCAL_Msk      /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos              (6U)                           
+#define USB_OTG_GUSBCFG_PHYSEL_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                  USB_OTG_GUSBCFG_PHYSEL_Msk     /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos              (8U)                           
+#define USB_OTG_GUSBCFG_SRPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                  USB_OTG_GUSBCFG_SRPCAP_Msk     /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos              (9U)                           
+#define USB_OTG_GUSBCFG_HNPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                  USB_OTG_GUSBCFG_HNPCAP_Msk     /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                (10U)                          
+#define USB_OTG_GUSBCFG_TRDT_Msk                (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                    USB_OTG_GUSBCFG_TRDT_Msk       /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                  (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                  (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                  (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos             (15U)                          
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk             (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 USB_OTG_GUSBCFG_PHYLPCS_Msk    /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos            (17U)                          
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk            (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                USB_OTG_GUSBCFG_ULPIFSLS_Msk   /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos              (18U)                          
+#define USB_OTG_GUSBCFG_ULPIAR_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                  USB_OTG_GUSBCFG_ULPIAR_Msk     /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos             (19U)                          
+#define USB_OTG_GUSBCFG_ULPICSM_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                 USB_OTG_GUSBCFG_ULPICSM_Msk    /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos          (20U)                          
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos          (21U)                          
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos               (22U)                          
+#define USB_OTG_GUSBCFG_TSDPS_Msk               (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                   USB_OTG_GUSBCFG_TSDPS_Msk      /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                (23U)                          
+#define USB_OTG_GUSBCFG_PCCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                    USB_OTG_GUSBCFG_PCCI_Msk       /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos                (24U)                          
+#define USB_OTG_GUSBCFG_PTCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                    USB_OTG_GUSBCFG_PTCI_Msk       /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos             (25U)                          
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                 USB_OTG_GUSBCFG_ULPIIPD_Msk    /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos               (29U)                          
+#define USB_OTG_GUSBCFG_FHMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                   USB_OTG_GUSBCFG_FHMOD_Msk      /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos               (30U)                          
+#define USB_OTG_GUSBCFG_FDMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                   USB_OTG_GUSBCFG_FDMOD_Msk      /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos              (31U)                          
+#define USB_OTG_GUSBCFG_CTXPKT_Msk              (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                  USB_OTG_GUSBCFG_CTXPKT_Msk     /*!< Corrupt Tx packet */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos               (0U)                           
+#define USB_OTG_GRSTCTL_CSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                   USB_OTG_GRSTCTL_CSRST_Msk      /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos               (1U)                           
+#define USB_OTG_GRSTCTL_HSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                   USB_OTG_GRSTCTL_HSRST_Msk      /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos               (2U)                           
+#define USB_OTG_GRSTCTL_FCRST_Msk               (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                   USB_OTG_GRSTCTL_FCRST_Msk      /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos             (4U)                           
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                 USB_OTG_GRSTCTL_RXFFLSH_Msk    /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos             (5U)                           
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                 USB_OTG_GRSTCTL_TXFFLSH_Msk    /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos              (6U)                           
+#define USB_OTG_GRSTCTL_TXFNUM_Msk              (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                  USB_OTG_GRSTCTL_TXFNUM_Msk     /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos              (30U)                          
+#define USB_OTG_GRSTCTL_DMAREQ_Msk              (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                  USB_OTG_GRSTCTL_DMAREQ_Msk     /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos              (31U)                          
+#define USB_OTG_GRSTCTL_AHBIDL_Msk              (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                  USB_OTG_GRSTCTL_AHBIDL_Msk     /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos               (0U)                           
+#define USB_OTG_DIEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                   USB_OTG_DIEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos                (1U)                           
+#define USB_OTG_DIEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                    USB_OTG_DIEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos                 (3U)                           
+#define USB_OTG_DIEPMSK_TOM_Msk                 (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                     USB_OTG_DIEPMSK_TOM_Msk        /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos           (4U)                           
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk           (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               USB_OTG_DIEPMSK_ITTXFEMSK_Msk  /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos             (5U)                           
+#define USB_OTG_DIEPMSK_INEPNMM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                 USB_OTG_DIEPMSK_INEPNMM_Msk    /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos             (6U)                           
+#define USB_OTG_DIEPMSK_INEPNEM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                 USB_OTG_DIEPMSK_INEPNEM_Msk    /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos              (8U)                           
+#define USB_OTG_DIEPMSK_TXFURM_Msk              (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                  USB_OTG_DIEPMSK_TXFURM_Msk     /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos                 (9U)                           
+#define USB_OTG_DIEPMSK_BIM_Msk                 (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                     USB_OTG_DIEPMSK_BIM_Msk        /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos            (0U)                           
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk            (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                USB_OTG_HPTXSTS_PTXFSAVL_Msk   /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos             (16U)                          
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 USB_OTG_HPTXSTS_PTXQSAV_Msk    /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos             (24U)                          
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 USB_OTG_HPTXSTS_PTXQTOP_Msk    /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                 (0U)                           
+#define USB_OTG_HAINT_HAINT_Msk                 (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                     USB_OTG_HAINT_HAINT_Msk        /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos               (0U)                           
+#define USB_OTG_DOEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                   USB_OTG_DOEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                (1U)                           
+#define USB_OTG_DOEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                    USB_OTG_DOEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
+#define USB_OTG_DOEPMSK_STUPM_Pos               (3U)                           
+#define USB_OTG_DOEPMSK_STUPM_Msk               (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                   USB_OTG_DOEPMSK_STUPM_Msk      /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos              (4U)                           
+#define USB_OTG_DOEPMSK_OTEPDM_Msk              (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                  USB_OTG_DOEPMSK_OTEPDM_Msk     /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos             (6U)                           
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                 USB_OTG_DOEPMSK_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos                (8U)                           
+#define USB_OTG_DOEPMSK_OPEM_Msk                (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                    USB_OTG_DOEPMSK_OPEM_Msk       /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos                (9U)                           
+#define USB_OTG_DOEPMSK_BOIM_Msk                (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                    USB_OTG_DOEPMSK_BOIM_Msk       /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                (0U)                           
+#define USB_OTG_GINTSTS_CMOD_Msk                (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                    USB_OTG_GINTSTS_CMOD_Msk       /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos                (1U)                           
+#define USB_OTG_GINTSTS_MMIS_Msk                (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                    USB_OTG_GINTSTS_MMIS_Msk       /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos              (2U)                           
+#define USB_OTG_GINTSTS_OTGINT_Msk              (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                  USB_OTG_GINTSTS_OTGINT_Msk     /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos                 (3U)                           
+#define USB_OTG_GINTSTS_SOF_Msk                 (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                     USB_OTG_GINTSTS_SOF_Msk        /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos              (4U)                           
+#define USB_OTG_GINTSTS_RXFLVL_Msk              (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                  USB_OTG_GINTSTS_RXFLVL_Msk     /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos              (5U)                           
+#define USB_OTG_GINTSTS_NPTXFE_Msk              (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                  USB_OTG_GINTSTS_NPTXFE_Msk     /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos            (6U)                           
+#define USB_OTG_GINTSTS_GINAKEFF_Msk            (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                USB_OTG_GINTSTS_GINAKEFF_Msk   /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos          (7U)                           
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk          (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos               (10U)                          
+#define USB_OTG_GINTSTS_ESUSP_Msk               (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                   USB_OTG_GINTSTS_ESUSP_Msk      /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos             (11U)                          
+#define USB_OTG_GINTSTS_USBSUSP_Msk             (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                 USB_OTG_GINTSTS_USBSUSP_Msk    /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos              (12U)                          
+#define USB_OTG_GINTSTS_USBRST_Msk              (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                  USB_OTG_GINTSTS_USBRST_Msk     /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos             (13U)                          
+#define USB_OTG_GINTSTS_ENUMDNE_Msk             (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                 USB_OTG_GINTSTS_ENUMDNE_Msk    /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos             (14U)                          
+#define USB_OTG_GINTSTS_ISOODRP_Msk             (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                 USB_OTG_GINTSTS_ISOODRP_Msk    /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos                (15U)                          
+#define USB_OTG_GINTSTS_EOPF_Msk                (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                    USB_OTG_GINTSTS_EOPF_Msk       /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos              (18U)                          
+#define USB_OTG_GINTSTS_IEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                  USB_OTG_GINTSTS_IEPINT_Msk     /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos              (19U)                          
+#define USB_OTG_GINTSTS_OEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                  USB_OTG_GINTSTS_OEPINT_Msk     /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos            (20U)                          
+#define USB_OTG_GINTSTS_IISOIXFR_Msk            (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                USB_OTG_GINTSTS_IISOIXFR_Msk   /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)                          
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos           (22U)                          
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk           (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP               USB_OTG_GINTSTS_DATAFSUSP_Msk  /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos             (24U)                          
+#define USB_OTG_GINTSTS_HPRTINT_Msk             (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                 USB_OTG_GINTSTS_HPRTINT_Msk    /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos               (25U)                          
+#define USB_OTG_GINTSTS_HCINT_Msk               (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                   USB_OTG_GINTSTS_HCINT_Msk      /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos               (26U)                          
+#define USB_OTG_GINTSTS_PTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                   USB_OTG_GINTSTS_PTXFE_Msk      /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos             (28U)                          
+#define USB_OTG_GINTSTS_CIDSCHG_Msk             (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                 USB_OTG_GINTSTS_CIDSCHG_Msk    /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos             (29U)                          
+#define USB_OTG_GINTSTS_DISCINT_Msk             (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                 USB_OTG_GINTSTS_DISCINT_Msk    /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos              (30U)                          
+#define USB_OTG_GINTSTS_SRQINT_Msk              (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                  USB_OTG_GINTSTS_SRQINT_Msk     /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos              (31U)                          
+#define USB_OTG_GINTSTS_WKUINT_Msk              (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                  USB_OTG_GINTSTS_WKUINT_Msk     /*!< Resume/remote wakeup detected interrupt */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos               (1U)                           
+#define USB_OTG_GINTMSK_MMISM_Msk               (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                   USB_OTG_GINTMSK_MMISM_Msk      /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos              (2U)                           
+#define USB_OTG_GINTMSK_OTGINT_Msk              (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                  USB_OTG_GINTMSK_OTGINT_Msk     /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos                (3U)                           
+#define USB_OTG_GINTMSK_SOFM_Msk                (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                    USB_OTG_GINTMSK_SOFM_Msk       /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos             (4U)                           
+#define USB_OTG_GINTMSK_RXFLVLM_Msk             (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                 USB_OTG_GINTMSK_RXFLVLM_Msk    /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos             (5U)                           
+#define USB_OTG_GINTMSK_NPTXFEM_Msk             (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                 USB_OTG_GINTMSK_NPTXFEM_Msk    /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos           (6U)                           
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM               USB_OTG_GINTMSK_GINAKEFFM_Msk  /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos           (7U)                           
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM               USB_OTG_GINTMSK_GONAKEFFM_Msk  /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos              (10U)                          
+#define USB_OTG_GINTMSK_ESUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                  USB_OTG_GINTMSK_ESUSPM_Msk     /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos            (11U)                          
+#define USB_OTG_GINTMSK_USBSUSPM_Msk            (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                USB_OTG_GINTMSK_USBSUSPM_Msk   /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos              (12U)                          
+#define USB_OTG_GINTMSK_USBRST_Msk              (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                  USB_OTG_GINTMSK_USBRST_Msk     /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos            (13U)                          
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk            (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                USB_OTG_GINTMSK_ENUMDNEM_Msk   /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos            (14U)                          
+#define USB_OTG_GINTMSK_ISOODRPM_Msk            (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                USB_OTG_GINTMSK_ISOODRPM_Msk   /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos               (15U)                          
+#define USB_OTG_GINTMSK_EOPFM_Msk               (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                   USB_OTG_GINTMSK_EOPFM_Msk      /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos              (17U)                          
+#define USB_OTG_GINTMSK_EPMISM_Msk              (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                  USB_OTG_GINTMSK_EPMISM_Msk     /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos              (18U)                          
+#define USB_OTG_GINTMSK_IEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                  USB_OTG_GINTMSK_IEPINT_Msk     /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos              (19U)                          
+#define USB_OTG_GINTMSK_OEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                  USB_OTG_GINTMSK_OEPINT_Msk     /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos           (20U)                          
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk           (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM               USB_OTG_GINTMSK_IISOIXFRM_Msk  /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos     (21U)                          
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk     (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos              (22U)                          
+#define USB_OTG_GINTMSK_FSUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                  USB_OTG_GINTMSK_FSUSPM_Msk     /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos               (24U)                          
+#define USB_OTG_GINTMSK_PRTIM_Msk               (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                   USB_OTG_GINTMSK_PRTIM_Msk      /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos                (25U)                          
+#define USB_OTG_GINTMSK_HCIM_Msk                (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                    USB_OTG_GINTMSK_HCIM_Msk       /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos              (26U)                          
+#define USB_OTG_GINTMSK_PTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                  USB_OTG_GINTMSK_PTXFEM_Msk     /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos            (28U)                          
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk            (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                USB_OTG_GINTMSK_CIDSCHGM_Msk   /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos             (29U)                          
+#define USB_OTG_GINTMSK_DISCINT_Msk             (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                 USB_OTG_GINTMSK_DISCINT_Msk    /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos               (30U)                          
+#define USB_OTG_GINTMSK_SRQIM_Msk               (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                   USB_OTG_GINTMSK_SRQIM_Msk      /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                (31U)                          
+#define USB_OTG_GINTMSK_WUIM_Msk                (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                    USB_OTG_GINTMSK_WUIM_Msk       /*!< Resume/remote wakeup detected interrupt mask */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                (0U)                           
+#define USB_OTG_DAINT_IEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                    USB_OTG_DAINT_IEPINT_Msk       /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos                (16U)                          
+#define USB_OTG_DAINT_OEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                    USB_OTG_DAINT_OEPINT_Msk       /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos             (0U)                           
+#define USB_OTG_HAINTMSK_HAINTM_Msk             (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                 USB_OTG_HAINTMSK_HAINTM_Msk    /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos               (0U)                           
+#define USB_OTG_GRXSTSP_EPNUM_Msk               (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                   USB_OTG_GRXSTSP_EPNUM_Msk      /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos                (4U)                           
+#define USB_OTG_GRXSTSP_BCNT_Msk                (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                    USB_OTG_GRXSTSP_BCNT_Msk       /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                (15U)                          
+#define USB_OTG_GRXSTSP_DPID_Msk                (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                    USB_OTG_GRXSTSP_DPID_Msk       /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos              (17U)                          
+#define USB_OTG_GRXSTSP_PKTSTS_Msk              (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                  USB_OTG_GRXSTSP_PKTSTS_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos               (0U)                           
+#define USB_OTG_DAINTMSK_IEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                   USB_OTG_DAINTMSK_IEPM_Msk      /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos               (16U)                          
+#define USB_OTG_DAINTMSK_OEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                   USB_OTG_DAINTMSK_OEPM_Msk      /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                (0U)                           
+#define USB_OTG_GRXFSIZ_RXFD_Msk                (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                    USB_OTG_GRXFSIZ_RXFD_Msk       /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos             (0U)                           
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk             (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                 USB_OTG_DVBUSDIS_VBUSDT_Msk    /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                     (0U)                           
+#define USB_OTG_NPTXFSA_Msk                     (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                         USB_OTG_NPTXFSA_Msk            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                      (16U)                          
+#define USB_OTG_NPTXFD_Msk                      (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                          USB_OTG_NPTXFD_Msk             /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos                      (0U)                           
+#define USB_OTG_TX0FSA_Msk                      (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                          USB_OTG_TX0FSA_Msk             /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos                       (16U)                          
+#define USB_OTG_TX0FD_Msk                       (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                           USB_OTG_TX0FD_Msk              /*!< Endpoint 0 TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos           (0U)                           
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk           (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP               USB_OTG_DVBUSPULSE_DVBUSP_Msk  /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos           (0U)                           
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk           (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV               USB_OTG_GNPTXSTS_NPTXFSAV_Msk  /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos           (16U)                          
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk           (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV               USB_OTG_GNPTXSTS_NPTQXSAV_Msk  /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0             (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1             (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2             (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3             (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4             (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5             (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6             (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7             (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos           (24U)                          
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk           (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP               USB_OTG_GNPTXSTS_NPTXQTOP_Msk  /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0             (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1             (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2             (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3             (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4             (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5             (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6             (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos         (0U)                           
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk         (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN             USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos            (1U)                           
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk            (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                USB_OTG_DTHRCTL_ISOTHREN_Msk   /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos            (2U)                           
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                USB_OTG_DTHRCTL_TXTHRLEN_Msk   /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos             (16U)                          
+#define USB_OTG_DTHRCTL_RXTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                 USB_OTG_DTHRCTL_RXTHREN_Msk    /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos            (17U)                          
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                USB_OTG_DTHRCTL_RXTHRLEN_Msk   /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos               (27U)                          
+#define USB_OTG_DTHRCTL_ARPEN_Msk               (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                   USB_OTG_DTHRCTL_ARPEN_Msk      /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos        (0U)                           
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk        (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM            USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos            (1U)                           
+#define USB_OTG_DEACHINT_IEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                USB_OTG_DEACHINT_IEP1INT_Msk   /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos            (17U)                          
+#define USB_OTG_DEACHINT_OEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                USB_OTG_DEACHINT_OEP1INT_Msk   /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos                (16U)                          
+#define USB_OTG_GCCFG_PWRDWN_Msk                (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                    USB_OTG_GCCFG_PWRDWN_Msk       /*!< Power down */
+#define USB_OTG_GCCFG_VBUSASEN_Pos              (18U)                          
+#define USB_OTG_GCCFG_VBUSASEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN                  USB_OTG_GCCFG_VBUSASEN_Msk     /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos              (19U)                          
+#define USB_OTG_GCCFG_VBUSBSEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN                  USB_OTG_GCCFG_VBUSBSEN_Msk     /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos              (20U)                          
+#define USB_OTG_GCCFG_SOFOUTEN_Msk              (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN                  USB_OTG_GCCFG_SOFOUTEN_Msk     /*!< SOF output enable */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos        (1U)                           
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM            USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos        (17U)                          
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM            USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos              (0U)                           
+#define USB_OTG_CID_PRODUCT_ID_Msk              (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                  USB_OTG_CID_PRODUCT_ID_Msk     /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos          (0U)                           
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM              USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos           (1U)                           
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM               USB_OTG_DIEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos            (3U)                           
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                USB_OTG_DIEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK          USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos        (5U)                           
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM            USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos        (6U)                           
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM            USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos         (8U)                           
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM             USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos            (9U)                           
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                USB_OTG_DIEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos           (13U)                          
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM               USB_OTG_DIEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                  (0U)                           
+#define USB_OTG_HPRT_PCSTS_Msk                  (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                      USB_OTG_HPRT_PCSTS_Msk         /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos                  (1U)                           
+#define USB_OTG_HPRT_PCDET_Msk                  (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                      USB_OTG_HPRT_PCDET_Msk         /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos                   (2U)                           
+#define USB_OTG_HPRT_PENA_Msk                   (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                       USB_OTG_HPRT_PENA_Msk          /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos                (3U)                           
+#define USB_OTG_HPRT_PENCHNG_Msk                (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                    USB_OTG_HPRT_PENCHNG_Msk       /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                   (4U)                           
+#define USB_OTG_HPRT_POCA_Msk                   (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                       USB_OTG_HPRT_POCA_Msk          /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos                (5U)                           
+#define USB_OTG_HPRT_POCCHNG_Msk                (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                    USB_OTG_HPRT_POCCHNG_Msk       /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos                   (6U)                           
+#define USB_OTG_HPRT_PRES_Msk                   (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                       USB_OTG_HPRT_PRES_Msk          /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos                  (7U)                           
+#define USB_OTG_HPRT_PSUSP_Msk                  (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                      USB_OTG_HPRT_PSUSP_Msk         /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos                   (8U)                           
+#define USB_OTG_HPRT_PRST_Msk                   (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                       USB_OTG_HPRT_PRST_Msk          /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos                  (10U)                          
+#define USB_OTG_HPRT_PLSTS_Msk                  (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                      USB_OTG_HPRT_PLSTS_Msk         /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                    (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                    (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                   (12U)                          
+#define USB_OTG_HPRT_PPWR_Msk                   (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                       USB_OTG_HPRT_PPWR_Msk          /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                  (13U)                          
+#define USB_OTG_HPRT_PTCTL_Msk                  (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                      USB_OTG_HPRT_PTCTL_Msk         /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                    (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                    (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                    (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                    (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                   (17U)                          
+#define USB_OTG_HPRT_PSPD_Msk                   (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                       USB_OTG_HPRT_PSPD_Msk          /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                     (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                     (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos          (0U)                           
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM              USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos           (1U)                           
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM               USB_OTG_DOEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos            (3U)                           
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                USB_OTG_DOEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK          USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos        (5U)                           
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM            USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos        (6U)                           
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM            USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos         (8U)                           
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM             USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos            (9U)                           
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                USB_OTG_DOEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos          (12U)                          
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM              USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos           (13U)                          
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM               USB_OTG_DOEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos          (14U)                          
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM              USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos              (0U)                           
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                  USB_OTG_HPTXFSIZ_PTXSA_Msk     /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos              (16U)                          
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                  USB_OTG_HPTXFSIZ_PTXFD_Msk     /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos               (0U)                           
+#define USB_OTG_DIEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                   USB_OTG_DIEPCTL_MPSIZ_Msk      /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos              (15U)                          
+#define USB_OTG_DIEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                  USB_OTG_DIEPCTL_USBAEP_Msk     /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos          (16U)                          
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk          (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID              USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos              (17U)                          
+#define USB_OTG_DIEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                  USB_OTG_DIEPCTL_NAKSTS_Msk     /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos               (18U)                          
+#define USB_OTG_DIEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                   USB_OTG_DIEPCTL_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos               (21U)                          
+#define USB_OTG_DIEPCTL_STALL_Msk               (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                   USB_OTG_DIEPCTL_STALL_Msk      /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos              (22U)                          
+#define USB_OTG_DIEPCTL_TXFNUM_Msk              (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                  USB_OTG_DIEPCTL_TXFNUM_Msk     /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                (26U)                          
+#define USB_OTG_DIEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                    USB_OTG_DIEPCTL_CNAK_Msk       /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                (27U)                          
+#define USB_OTG_DIEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                    USB_OTG_DIEPCTL_SNAK_Msk       /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos             (29U)                          
+#define USB_OTG_DIEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                 USB_OTG_DIEPCTL_SODDFRM_Msk    /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos               (30U)                          
+#define USB_OTG_DIEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                   USB_OTG_DIEPCTL_EPDIS_Msk      /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos               (31U)                          
+#define USB_OTG_DIEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                   USB_OTG_DIEPCTL_EPENA_Msk      /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                (0U)                           
+#define USB_OTG_HCCHAR_MPSIZ_Msk                (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                    USB_OTG_HCCHAR_MPSIZ_Msk       /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                (11U)                          
+#define USB_OTG_HCCHAR_EPNUM_Msk                (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                    USB_OTG_HCCHAR_EPNUM_Msk       /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                  (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                  (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                  (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                  (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                (15U)                          
+#define USB_OTG_HCCHAR_EPDIR_Msk                (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                    USB_OTG_HCCHAR_EPDIR_Msk       /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                (17U)                          
+#define USB_OTG_HCCHAR_LSDEV_Msk                (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                    USB_OTG_HCCHAR_LSDEV_Msk       /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                (18U)                          
+#define USB_OTG_HCCHAR_EPTYP_Msk                (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                    USB_OTG_HCCHAR_EPTYP_Msk       /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                  (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                  (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+                                      
+#define USB_OTG_HCCHAR_MC_Pos                   (20U)                          
+#define USB_OTG_HCCHAR_MC_Msk                   (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                       USB_OTG_HCCHAR_MC_Msk          /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                     (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                     (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                  (22U)                          
+#define USB_OTG_HCCHAR_DAD_Msk                  (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                      USB_OTG_HCCHAR_DAD_Msk         /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                    (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                    (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                    (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                    (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                    (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                    (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                    (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos               (29U)                          
+#define USB_OTG_HCCHAR_ODDFRM_Msk               (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                   USB_OTG_HCCHAR_ODDFRM_Msk      /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                (30U)                          
+#define USB_OTG_HCCHAR_CHDIS_Msk                (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                    USB_OTG_HCCHAR_CHDIS_Msk       /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                (31U)                          
+#define USB_OTG_HCCHAR_CHENA_Msk                (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                    USB_OTG_HCCHAR_CHENA_Msk       /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos              (0U)                           
+#define USB_OTG_HCSPLT_PRTADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                  USB_OTG_HCSPLT_PRTADDR_Msk     /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos              (7U)                           
+#define USB_OTG_HCSPLT_HUBADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                  USB_OTG_HCSPLT_HUBADDR_Msk     /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos              (14U)                          
+#define USB_OTG_HCSPLT_XACTPOS_Msk              (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                  USB_OTG_HCSPLT_XACTPOS_Msk     /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos            (16U)                          
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk            (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                USB_OTG_HCSPLT_COMPLSPLT_Msk   /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos              (31U)                          
+#define USB_OTG_HCSPLT_SPLITEN_Msk              (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                  USB_OTG_HCSPLT_SPLITEN_Msk     /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                  (0U)                           
+#define USB_OTG_HCINT_XFRC_Msk                  (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                      USB_OTG_HCINT_XFRC_Msk         /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                   (1U)                           
+#define USB_OTG_HCINT_CHH_Msk                   (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                       USB_OTG_HCINT_CHH_Msk          /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                (2U)                           
+#define USB_OTG_HCINT_AHBERR_Msk                (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                    USB_OTG_HCINT_AHBERR_Msk       /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                 (3U)                           
+#define USB_OTG_HCINT_STALL_Msk                 (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                     USB_OTG_HCINT_STALL_Msk        /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                   (4U)                           
+#define USB_OTG_HCINT_NAK_Msk                   (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                       USB_OTG_HCINT_NAK_Msk          /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                   (5U)                           
+#define USB_OTG_HCINT_ACK_Msk                   (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                       USB_OTG_HCINT_ACK_Msk          /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                  (6U)                           
+#define USB_OTG_HCINT_NYET_Msk                  (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                      USB_OTG_HCINT_NYET_Msk         /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                 (7U)                           
+#define USB_OTG_HCINT_TXERR_Msk                 (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                     USB_OTG_HCINT_TXERR_Msk        /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                 (8U)                           
+#define USB_OTG_HCINT_BBERR_Msk                 (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                     USB_OTG_HCINT_BBERR_Msk        /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                 (9U)                           
+#define USB_OTG_HCINT_FRMOR_Msk                 (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                     USB_OTG_HCINT_FRMOR_Msk        /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                 (10U)                          
+#define USB_OTG_HCINT_DTERR_Msk                 (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                     USB_OTG_HCINT_DTERR_Msk        /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                (0U)                           
+#define USB_OTG_DIEPINT_XFRC_Msk                (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                    USB_OTG_DIEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos              (1U)                           
+#define USB_OTG_DIEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                  USB_OTG_DIEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                 (3U)                           
+#define USB_OTG_DIEPINT_TOC_Msk                 (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                     USB_OTG_DIEPINT_TOC_Msk        /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos              (4U)                           
+#define USB_OTG_DIEPINT_ITTXFE_Msk              (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                  USB_OTG_DIEPINT_ITTXFE_Msk     /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos              (6U)                           
+#define USB_OTG_DIEPINT_INEPNE_Msk              (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                  USB_OTG_DIEPINT_INEPNE_Msk     /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                (7U)                           
+#define USB_OTG_DIEPINT_TXFE_Msk                (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                    USB_OTG_DIEPINT_TXFE_Msk       /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos          (8U)                           
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk          (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                 (9U)                           
+#define USB_OTG_DIEPINT_BNA_Msk                 (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                     USB_OTG_DIEPINT_BNA_Msk        /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos           (11U)                          
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk           (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS               USB_OTG_DIEPINT_PKTDRPSTS_Msk  /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                (12U)                          
+#define USB_OTG_DIEPINT_BERR_Msk                (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                    USB_OTG_DIEPINT_BERR_Msk       /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                 (13U)                          
+#define USB_OTG_DIEPINT_NAK_Msk                 (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                     USB_OTG_DIEPINT_NAK_Msk        /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos              (0U)                           
+#define USB_OTG_HCINTMSK_XFRCM_Msk              (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                  USB_OTG_HCINTMSK_XFRCM_Msk     /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos               (1U)                           
+#define USB_OTG_HCINTMSK_CHHM_Msk               (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                   USB_OTG_HCINTMSK_CHHM_Msk      /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos             (2U)                           
+#define USB_OTG_HCINTMSK_AHBERR_Msk             (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                 USB_OTG_HCINTMSK_AHBERR_Msk    /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos             (3U)                           
+#define USB_OTG_HCINTMSK_STALLM_Msk             (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                 USB_OTG_HCINTMSK_STALLM_Msk    /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos               (4U)                           
+#define USB_OTG_HCINTMSK_NAKM_Msk               (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                   USB_OTG_HCINTMSK_NAKM_Msk      /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos               (5U)                           
+#define USB_OTG_HCINTMSK_ACKM_Msk               (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                   USB_OTG_HCINTMSK_ACKM_Msk      /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos               (6U)                           
+#define USB_OTG_HCINTMSK_NYET_Msk               (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                   USB_OTG_HCINTMSK_NYET_Msk      /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos             (7U)                           
+#define USB_OTG_HCINTMSK_TXERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                 USB_OTG_HCINTMSK_TXERRM_Msk    /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos             (8U)                           
+#define USB_OTG_HCINTMSK_BBERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                 USB_OTG_HCINTMSK_BBERRM_Msk    /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos             (9U)                           
+#define USB_OTG_HCINTMSK_FRMORM_Msk             (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                 USB_OTG_HCINTMSK_FRMORM_Msk    /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos             (10U)                          
+#define USB_OTG_HCINTMSK_DTERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                 USB_OTG_HCINTMSK_DTERRM_Msk    /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos             (0U)                           
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                 USB_OTG_DIEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos             (19U)                          
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                 USB_OTG_DIEPTSIZ_PKTCNT_Msk    /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos             (29U)                          
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk             (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                 USB_OTG_DIEPTSIZ_MULCNT_Msk    /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos               (0U)                           
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk               (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                   USB_OTG_HCTSIZ_XFRSIZ_Msk      /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos               (19U)                          
+#define USB_OTG_HCTSIZ_PKTCNT_Msk               (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                   USB_OTG_HCTSIZ_PKTCNT_Msk      /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos               (31U)                          
+#define USB_OTG_HCTSIZ_DOPING_Msk               (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                   USB_OTG_HCTSIZ_DOPING_Msk      /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                 (29U)                          
+#define USB_OTG_HCTSIZ_DPID_Msk                 (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                     USB_OTG_HCTSIZ_DPID_Msk        /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos             (0U)                           
+#define USB_OTG_DIEPDMA_DMAADDR_Msk             (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                 USB_OTG_DIEPDMA_DMAADDR_Msk    /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos               (0U)                           
+#define USB_OTG_HCDMA_DMAADDR_Msk               (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                   USB_OTG_HCDMA_DMAADDR_Msk      /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos           (0U)                           
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk           (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos            (0U)                           
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                USB_OTG_DIEPTXF_INEPTXSA_Msk   /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos            (16U)                          
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                USB_OTG_DIEPTXF_INEPTXFD_Msk   /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos               (0U)                           
+#define USB_OTG_DOEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos              (15U)                          
+#define USB_OTG_DOEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                  USB_OTG_DOEPCTL_USBAEP_Msk     /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos              (17U)                          
+#define USB_OTG_DOEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                  USB_OTG_DOEPCTL_NAKSTS_Msk     /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM          USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos             (29U)                          
+#define USB_OTG_DOEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                 USB_OTG_DOEPCTL_SODDFRM_Msk    /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos               (18U)                          
+#define USB_OTG_DOEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                   USB_OTG_DOEPCTL_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                (20U)                          
+#define USB_OTG_DOEPCTL_SNPM_Msk                (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                    USB_OTG_DOEPCTL_SNPM_Msk       /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos               (21U)                          
+#define USB_OTG_DOEPCTL_STALL_Msk               (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                   USB_OTG_DOEPCTL_STALL_Msk      /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                (26U)                          
+#define USB_OTG_DOEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                    USB_OTG_DOEPCTL_CNAK_Msk       /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                (27U)                          
+#define USB_OTG_DOEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                    USB_OTG_DOEPCTL_SNAK_Msk       /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos               (30U)                          
+#define USB_OTG_DOEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                   USB_OTG_DOEPCTL_EPDIS_Msk      /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos               (31U)                          
+#define USB_OTG_DOEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                   USB_OTG_DOEPCTL_EPENA_Msk      /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                (0U)                           
+#define USB_OTG_DOEPINT_XFRC_Msk                (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                    USB_OTG_DOEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos              (1U)                           
+#define USB_OTG_DOEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                  USB_OTG_DOEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                (3U)                           
+#define USB_OTG_DOEPINT_STUP_Msk                (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                    USB_OTG_DOEPINT_STUP_Msk       /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos             (4U)                           
+#define USB_OTG_DOEPINT_OTEPDIS_Msk             (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                 USB_OTG_DOEPINT_OTEPDIS_Msk    /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos             (6U)                           
+#define USB_OTG_DOEPINT_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                 USB_OTG_DOEPINT_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                (14U)                          
+#define USB_OTG_DOEPINT_NYET_Msk                (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                    USB_OTG_DOEPINT_NYET_Msk       /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos             (0U)                           
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                 USB_OTG_DOEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos             (19U)                          
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                 USB_OTG_DOEPTSIZ_PKTCNT_Msk    /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos            (29U)                          
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk            (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                USB_OTG_DOEPTSIZ_STUPCNT_Msk   /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0              (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1              (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos             (0U)                           
+#define USB_OTG_PCGCCTL_STOPCLK_Msk             (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                 USB_OTG_PCGCCTL_STOPCLK_Msk    /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos             (1U)                           
+#define USB_OTG_PCGCCTL_GATECLK_Msk             (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                 USB_OTG_PCGCCTL_GATECLK_Msk    /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos             (4U)                           
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk             (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 USB_OTG_PCGCCTL_PHYSUSP_Msk    /*!<Bit 1 */
+
+/* Legacy define */
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_CHNUM_Pos                       (0U)                           
+#define USB_OTG_CHNUM_Msk                       (0xFUL << USB_OTG_CHNUM_Pos)    /*!< 0x0000000F */
+#define USB_OTG_CHNUM                           USB_OTG_CHNUM_Msk              /*!< Channel number */
+#define USB_OTG_CHNUM_0                         (0x1UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                         (0x2UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                         (0x4UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                         (0x8UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                        (4U)                           
+#define USB_OTG_BCNT_Msk                        (0x7FFUL << USB_OTG_BCNT_Pos)   /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                            USB_OTG_BCNT_Msk               /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                        (15U)                          
+#define USB_OTG_DPID_Msk                        (0x3UL << USB_OTG_DPID_Pos)     /*!< 0x00018000 */
+#define USB_OTG_DPID                            USB_OTG_DPID_Msk               /*!< Data PID */
+#define USB_OTG_DPID_0                          (0x1UL << USB_OTG_DPID_Pos)     /*!< 0x00008000 */
+#define USB_OTG_DPID_1                          (0x2UL << USB_OTG_DPID_Pos)     /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                      (17U)                          
+#define USB_OTG_PKTSTS_Msk                      (0xFUL << USB_OTG_PKTSTS_Pos)   /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                          USB_OTG_PKTSTS_Msk             /*!< Packet status */
+#define USB_OTG_PKTSTS_0                        (0x1UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                        (0x2UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                        (0x4UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                        (0x8UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                       (0U)                           
+#define USB_OTG_EPNUM_Msk                       (0xFUL << USB_OTG_EPNUM_Pos)    /*!< 0x0000000F */
+#define USB_OTG_EPNUM                           USB_OTG_EPNUM_Msk              /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                         (0x1UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                         (0x2UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                         (0x4UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                         (0x8UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                      (21U)                          
+#define USB_OTG_FRMNUM_Msk                      (0xFUL << USB_OTG_FRMNUM_Pos)   /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                          USB_OTG_FRMNUM_Msk             /*!< Frame number */
+#define USB_OTG_FRMNUM_0                        (0x1UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                        (0x2UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                        (0x4UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                        (0x8UL << USB_OTG_FRMNUM_Pos)   /*!< 0x01000000 */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 91f28fdec..e189c65bb 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -122,6 +122,9 @@
 // Mind Motion
 #define OPT_MCU_MM32F327X        1500 ///< Mind Motion MM32F327
 
+// GigaDevice
+#define OPT_MCU_GD32VF103        1600 ///< GigaDevice GD32VF103
+
 //--------------------------------------------------------------------+
 // Supported OS
 //--------------------------------------------------------------------+

From 19b971cb24368148cf3d298c506aad39569fe2e2 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 10 Jul 2021 11:17:24 +0200
Subject: [PATCH 0291/2085] Add board support for gd32vf103 longan nano

---
 .gitmodules                                   |    3 +
 hw/bsp/board_mcu.h                            |    3 +
 hw/bsp/gd32vf103_longan_nano/board.mk         |   59 +
 .../gcc_gd32vf103x8_flashxip.ld               |  284 ++++
 .../gcc_gd32vf103xb_flashxip.ld               |  284 ++++
 .../gd32vf103_longan_nano.c                   |  274 ++++
 hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h |   20 +
 .../gd32vf103_longan_nano/system_gd32vf103.c  | 1256 +++++++++++++++++
 hw/mcu/gd/nuclei-sdk                          |    1 +
 9 files changed, 2184 insertions(+)
 create mode 100644 hw/bsp/gd32vf103_longan_nano/board.mk
 create mode 100644 hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103x8_flashxip.ld
 create mode 100644 hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103xb_flashxip.ld
 create mode 100644 hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
 create mode 100644 hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
 create mode 100644 hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c
 create mode 160000 hw/mcu/gd/nuclei-sdk

diff --git a/.gitmodules b/.gitmodules
index c0e6f8f91..1636b9765 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -124,3 +124,6 @@
 [submodule "hw/mcu/mindmotion/mm32sdk"]
 	path = hw/mcu/mindmotion/mm32sdk
 	url = https://github.com/zhangslice/mm32sdk.git
+[submodule "hw/mcu/gd/nuclei-sdk"]
+	path = hw/mcu/gd/nuclei-sdk
+	url = git@github.com:Nuclei-Software/nuclei-sdk.git
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 9f6b489ea..acfd7348d 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -130,6 +130,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
   // no header needed
 
+#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
+  #include "gd32vf103.h"
+
 #else
   #error "Missing MCU header"
 #endif
diff --git a/hw/bsp/gd32vf103_longan_nano/board.mk b/hw/bsp/gd32vf103_longan_nano/board.mk
new file mode 100644
index 000000000..f34f68c22
--- /dev/null
+++ b/hw/bsp/gd32vf103_longan_nano/board.mk
@@ -0,0 +1,59 @@
+CROSS_COMPILE = riscv32-unknown-elf-
+
+DEPS_SUBMODULES += hw/mcu/gd/nuclei-sdk
+
+NUCLEI_SDK = hw/mcu/gd/nuclei-sdk
+GD32VF103_SDK_SOC_COMMON = $(NUCLEI_SDK)/SoC/gd32vf103/Common
+GD32VF103_SDK_DRIVER = $(GD32VF103_SDK_SOC_COMMON)/Source/Drivers
+SKIP_NANOLIB = 1
+
+CFLAGS += \
+  -march=rv32imac \
+  -mabi=ilp32 \
+  -mcmodel=medlow \
+  -mstrict-align \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_GD32VF103 \
+  -DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP \
+  -DGD32VF103 
+
+# mcu driver cause following warnings
+#CFLAGS += -Wno-error=unused-parameter
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/$(BOARD)/gcc_gd32vf103xb_flashxip.ld # 128kb ROM 32kb RAM
+# LD_FILE = hw/bsp/$(BOARD)/gcc_gd32vf103x8_flashxip.ld # 64kb ROM 20kb RAM Longan Nano Lite
+
+SRC_C += \
+  src/portable/st/synopsys/dcd_synopsys.c \
+	$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
+	$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
+	$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
+	$(GD32VF103_SDK_DRIVER)/gd32vf103_fmc.c \
+	$(GD32VF103_SDK_DRIVER)/gd32vf103_usart.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/sbrk.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/close.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/isatty.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/fstat.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/lseek.c \
+	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/read.c 
+
+SRC_S += \
+  $(GD32VF103_SDK_SOC_COMMON)/Source/GCC/startup_gd32vf103.S \
+  $(GD32VF103_SDK_SOC_COMMON)/Source/GCC/intexc_gd32vf103.S
+
+INC += \
+  $(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(NUCLEI_SDK)/NMSIS/Core/Include \
+	$(TOP)/$(GD32VF103_SDK_SOC_COMMON)/Include \
+	$(TOP)/$(GD32VF103_SDK_SOC_COMMON)/Include/Usb \
+
+# For freeRTOS port source
+#FREERTOS_PORT = ARM_CM3
+
+# For flash-jlink target
+JLINK_DEVICE = gd32vf103cb
+
+# flash target ROM bootloader
+flash: $(BUILD)/$(PROJECT).bin
+	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
diff --git a/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103x8_flashxip.ld b/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103x8_flashxip.ld
new file mode 100644
index 000000000..10f3747e0
--- /dev/null
+++ b/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103x8_flashxip.ld
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2019 - 2020 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     gcc_gd32vf103x8_flashxip.ld
+ * @brief    GNU Linker Script for gd32vf103x8 based device
+ * @version  V1.0.0
+ * @date     1. Dec 2020
+ ******************************************************************************/
+
+/*********** Use Configuration Wizard in Context Menu *************************/
+
+OUTPUT_ARCH( "riscv" )
+/********************* Flash Configuration ************************************
+ * <h> Flash Configuration
+ * <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+ * <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__ROM_BASE = 0x08000000;
+__ROM_SIZE = 0x00010000;
+
+/*--------------------- ILM RAM Configuration ---------------------------
+ * <h> ILM RAM Configuration
+ * <o0> ILM RAM Base Address    <0x0-0xFFFFFFFF:8>
+ * <o1> ILM RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__ILM_RAM_BASE = 0x80000000;
+__ILM_RAM_SIZE = 0x00010000;
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+ * <h> RAM Configuration
+ * <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+ * <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00005000;
+
+/********************* Stack / Heap Configuration ****************************
+ * <h> Stack / Heap Configuration
+ * <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__STACK_SIZE = 0x00000800;
+__HEAP_SIZE  = 0x00000800;
+
+/**************************** end of configuration section ********************/
+
+/* Define base address and length of flash and ram */
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  ram (wxa!ri) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH,ILM and RAM.
+ * It references following symbols, which must be defined in code:
+ *   _Start : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   _ilm_lma
+ *   _ilm
+ *   __etext
+ *   _etext
+ *   etext
+ *   _eilm
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   _data_lma
+ *   _edata
+ *   edata
+ *   __data_end__
+ *   __bss_start
+ *   __fbss
+ *   _end
+ *   end
+ *   __heap_end
+ *   __StackLimit
+ *   __StackTop
+ *   __STACK_SIZE
+ */
+/* Define entry label of program */
+ENTRY(_start)
+SECTIONS
+{
+  __STACK_SIZE = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2K;
+
+  .init           :
+  {
+    /* vector table locate at flash */
+    *(.vtable)
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash
+
+  .ilalign         :
+  {
+    . = ALIGN(4);
+    /* Create a section label as _ilm_lma which located at flash */
+    PROVIDE( _ilm_lma = . );
+  } >flash AT>flash
+
+  .ialign         :
+  {
+    /* Create a section label as _ilm which located at flash */
+    PROVIDE( _ilm = . );
+  } >flash AT>flash
+
+  /* Code section located at flash */
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash
+
+  .rodata : ALIGN(4)
+  {
+    . = ALIGN(4);
+    *(.rdata)
+    *(.rodata .rodata.*)
+    /* section information for initial. */
+    . = ALIGN(4);
+    __rt_init_start = .;
+    KEEP(*(SORT(.rti_fn*)))
+    __rt_init_end = .;
+    /* section information for finsh shell */
+    . = ALIGN(4);
+    __fsymtab_start = .;
+    KEEP(*(FSymTab))
+    __fsymtab_end = .;
+    . = ALIGN(4);
+    __vsymtab_start = .;
+    KEEP(*(VSymTab))
+    __vsymtab_end = .;
+    *(.gnu.linkonce.r.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >flash AT>flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash
+
+  . = ALIGN(4);
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  PROVIDE( _eilm = . );
+
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+     * the constructors, so we make sure it is
+     * first.  Because this is a wildcard, it
+     * doesn't matter if the user does not
+     * actually link against crtbegin.o; the
+     * linker won't look for a file to match a
+     * wildcard.  The wildcard also means that it
+     * doesn't matter which directory crtbegin.o
+     * is in.
+     */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+     * the crtend.o file until after the sorted ctors.
+     * The .ctor section from the crtend file contains the
+     * end of ctors marker and it must be last
+     */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash
+
+  /* Define data section virtual address is ram and physical address is flash */
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.* .sdata*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>flash
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+  /* Define stack and head location at ram */
+  .stack ORIGIN(ram) + LENGTH(ram) - __STACK_SIZE :
+  {
+    PROVIDE( _heap_end = . );
+    . = __STACK_SIZE;
+    PROVIDE( _sp = . );
+  } >ram AT>ram
+}
diff --git a/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103xb_flashxip.ld b/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103xb_flashxip.ld
new file mode 100644
index 000000000..14d317f14
--- /dev/null
+++ b/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103xb_flashxip.ld
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2019 - 2020 Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     gcc_gd32vf103xb_flashxip.ld
+ * @brief    GNU Linker Script for gd32vf103xb based device
+ * @version  V1.0.0
+ * @date     1. Dec 2020
+ ******************************************************************************/
+
+/*********** Use Configuration Wizard in Context Menu *************************/
+
+OUTPUT_ARCH( "riscv" )
+/********************* Flash Configuration ************************************
+ * <h> Flash Configuration
+ * <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
+ * <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__ROM_BASE = 0x08000000;
+__ROM_SIZE = 0x00020000;
+
+/*--------------------- ILM RAM Configuration ---------------------------
+ * <h> ILM RAM Configuration
+ * <o0> ILM RAM Base Address    <0x0-0xFFFFFFFF:8>
+ * <o1> ILM RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__ILM_RAM_BASE = 0x80000000;
+__ILM_RAM_SIZE = 0x00010000;
+
+/*--------------------- Embedded RAM Configuration ---------------------------
+ * <h> RAM Configuration
+ * <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
+ * <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+*/
+__RAM_BASE = 0x20000000;
+__RAM_SIZE = 0x00008000;
+
+/********************* Stack / Heap Configuration ****************************
+ * <h> Stack / Heap Configuration
+ * <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ * </h>
+ */
+__STACK_SIZE = 0x00000800;
+__HEAP_SIZE  = 0x00000800;
+
+/**************************** end of configuration section ********************/
+
+/* Define base address and length of flash and ram */
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
+  ram (wxa!ri) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
+}
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH,ILM and RAM.
+ * It references following symbols, which must be defined in code:
+ *   _Start : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   _ilm_lma
+ *   _ilm
+ *   __etext
+ *   _etext
+ *   etext
+ *   _eilm
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   _data_lma
+ *   _edata
+ *   edata
+ *   __data_end__
+ *   __bss_start
+ *   __fbss
+ *   _end
+ *   end
+ *   __heap_end
+ *   __StackLimit
+ *   __StackTop
+ *   __STACK_SIZE
+ */
+/* Define entry label of program */
+ENTRY(_start)
+SECTIONS
+{
+  __STACK_SIZE = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2K;
+
+  .init           :
+  {
+    /* vector table locate at flash */
+    *(.vtable)
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash
+
+  .ilalign         :
+  {
+    . = ALIGN(4);
+    /* Create a section label as _ilm_lma which located at flash */
+    PROVIDE( _ilm_lma = . );
+  } >flash AT>flash
+
+  .ialign         :
+  {
+    /* Create a section label as _ilm which located at flash */
+    PROVIDE( _ilm = . );
+  } >flash AT>flash
+
+  /* Code section located at flash */
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash
+
+  .rodata : ALIGN(4)
+  {
+    . = ALIGN(4);
+    *(.rdata)
+    *(.rodata .rodata.*)
+    /* section information for initial. */
+    . = ALIGN(4);
+    __rt_init_start = .;
+    KEEP(*(SORT(.rti_fn*)))
+    __rt_init_end = .;
+    /* section information for finsh shell */
+    . = ALIGN(4);
+    __fsymtab_start = .;
+    KEEP(*(FSymTab))
+    __fsymtab_end = .;
+    . = ALIGN(4);
+    __vsymtab_start = .;
+    KEEP(*(VSymTab))
+    __vsymtab_end = .;
+    *(.gnu.linkonce.r.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >flash AT>flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash
+
+  . = ALIGN(4);
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  PROVIDE( _eilm = . );
+
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+     * the constructors, so we make sure it is
+     * first.  Because this is a wildcard, it
+     * doesn't matter if the user does not
+     * actually link against crtbegin.o; the
+     * linker won't look for a file to match a
+     * wildcard.  The wildcard also means that it
+     * doesn't matter which directory crtbegin.o
+     * is in.
+     */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+     * the crtend.o file until after the sorted ctors.
+     * The .ctor section from the crtend file contains the
+     * end of ctors marker and it must be last
+     */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash
+
+  /* Define data section virtual address is ram and physical address is flash */
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.* .sdata*)
+    *(.gnu.linkonce.s.*)
+  } >ram AT>flash
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+  /* Define stack and head location at ram */
+  .stack ORIGIN(ram) + LENGTH(ram) - __STACK_SIZE :
+  {
+    PROVIDE( _heap_end = . );
+    . = __STACK_SIZE;
+    PROVIDE( _sp = . );
+  } >ram AT>ram
+}
diff --git a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
new file mode 100644
index 000000000..f501c20b4
--- /dev/null
+++ b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
@@ -0,0 +1,274 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../board.h"
+#include "nuclei_sdk_hal.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+void USBFS_IRQHandler(void) { tud_int_handler(0); }
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+#define HXTAL_VALUE \
+  ((uint32_t)8000000) /*!< value of the external oscillator in Hz */
+#define USB_NO_VBUS_PIN 1
+
+//--------------------------------------------------------------------+
+// LED
+//--------------------------------------------------------------------+
+
+#define LED_PORT GPIOC
+#define LED_PIN GPIO_PIN_13
+#define LED_STATE_ON 1
+
+#define BUTTON_PORT GPIOA
+#define BUTTON_PIN GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE 1
+
+//--------------------------------------------------------------------+
+// UART
+//--------------------------------------------------------------------+
+
+#define UART_DEV USART0
+#define UART_GPIO_PORT GPIOA
+#define UART_TX_PIN GPIO_PIN_9
+#define UART_RX_PIN GPIO_PIN_10
+
+/* sipeed longan nano board UART com port */
+#define GD32_COM0 USART0
+#define GD32_COM_CLK RCU_USART0
+#define GD32_COM_TX_PIN GPIO_PIN_9
+#define GD32_COM_RX_PIN GPIO_PIN_10
+#define GD32_COM_TX_GPIO_PORT GPIOA
+#define GD32_COM_RX_GPIO_PORT GPIOA
+#define GD32_COM_TX_GPIO_CLK RCU_GPIOA
+#define GD32_COM_RX_GPIO_CLK RCU_GPIOA
+
+void board_init(void) {
+  /* Disable interrupts during init */
+  __disable_irq();
+
+  /* Reset eclic configuration registers */
+  ECLIC->CFG = 0;
+  ECLIC->MTH = 0;
+
+  /* Reset eclic interrupt registers */
+  for (int32_t i = 0; i < SOC_INT_MAX; i++) {
+    ECLIC->CTRL[0].INTIP = 0;
+    ECLIC->CTRL[0].INTIE = 0;
+    ECLIC->CTRL[0].INTATTR = 0;
+    ECLIC->CTRL[0].INTCTRL = 0;
+  }
+
+  /* Set 4 bits for interrupt level and 0 bits for priority */
+  __ECLIC_SetCfgNlbits(4);
+
+  SystemCoreClockUpdate();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTimer_SetLoadValue(0);
+  SysTimer_SetCompareValue(SystemCoreClock / 1000);
+  ECLIC_SetLevelIRQ(SysTimer_IRQn, 3);
+  ECLIC_SetTrigIRQ(SysTimer_IRQn, ECLIC_POSTIVE_EDGE_TRIGGER);
+  ECLIC_EnableIRQ(SysTimer_IRQn);
+  SysTimer_Start();
+#endif
+
+  rcu_periph_clock_enable(RCU_GPIOA);
+  rcu_periph_clock_enable(RCU_GPIOB);
+  rcu_periph_clock_enable(RCU_GPIOC);
+  rcu_periph_clock_enable(RCU_GPIOD);
+  rcu_periph_clock_enable(RCU_AF);
+
+#ifdef BUTTON_PIN
+  gpio_init(BUTTON_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, BUTTON_PIN);
+#endif
+
+#ifdef LED_PIN
+  gpio_init(LED_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LED_PIN);
+  board_led_write(0);
+#endif
+
+#if defined(UART_DEV) && CFG_TUSB_DEBUG
+  /* enable GPIO TX and RX clock */
+  rcu_periph_clock_enable(GD32_COM_TX_GPIO_CLK);
+  rcu_periph_clock_enable(GD32_COM_RX_GPIO_CLK);
+
+  /* enable USART clock */
+  rcu_periph_clock_enable(GD32_COM_CLK);
+
+  /* connect port to USARTx_Tx */
+  gpio_init(GD32_COM_TX_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ,
+            GD32_COM_TX_PIN);
+
+  /* connect port to USARTx_Rx */
+  gpio_init(GD32_COM_RX_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ,
+            GD32_COM_RX_PIN);
+
+  /* USART configure */
+  usart_deinit(UART_DEV);
+  usart_baudrate_set(UART_DEV, 115200U);
+  usart_word_length_set(UART_DEV, USART_WL_8BIT);
+  usart_stop_bit_set(UART_DEV, USART_STB_1BIT);
+  usart_parity_config(UART_DEV, USART_PM_NONE);
+  usart_hardware_flow_rts_config(UART_DEV, USART_RTS_DISABLE);
+  usart_hardware_flow_cts_config(UART_DEV, USART_CTS_DISABLE);
+  usart_receive_config(UART_DEV, USART_RECEIVE_ENABLE);
+  usart_transmit_config(UART_DEV, USART_TRANSMIT_ENABLE);
+  usart_enable(UART_DEV);
+#endif
+
+  /* USB D+ and D- pins don't need to be configured. */
+  /* Configure VBUS Pin */
+#ifndef USB_NO_VBUS_PIN
+  gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
+#endif
+
+  /* This for ID line debug */
+  // gpio_init(GPIOA, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10);
+
+  /* Enable USB OTG clock */
+  usb_rcu_config();
+
+  /* Reset USB OTG peripheral */
+  rcu_periph_reset_enable(RCU_USBFSRST);
+  rcu_periph_reset_disable(RCU_USBFSRST);
+
+  /* Set IRQ priority and trigger */
+  ECLIC_SetLevelIRQ(USBFS_IRQn, 15);
+  ECLIC_SetTrigIRQ(USBFS_IRQn, ECLIC_POSTIVE_EDGE_TRIGGER);
+
+  /* Retrieve otg core registers */
+  usb_gr* otg_core_regs = (usb_gr*)(USBFS_REG_BASE + USB_REG_OFFSET_CORE);
+
+#ifdef USB_NO_VBUS_PIN
+  /* Disable VBUS sense*/
+  otg_core_regs->GCCFG |= GCCFG_VBUSIG | GCCFG_PWRON | GCCFG_VBUSBCEN;
+#else
+  /* Enable VBUS sense via pin PA9 */
+  otg_core_regs->GCCFG |= GCCFG_VBUSIG | GCCFG_PWRON | GCCFG_VBUSBCEN;
+  otg_core_regs->GCCFG &= ~GCCFG_VBUSIG;
+#endif
+
+  /* Enable interrupts globaly */
+  __enable_irq();
+}
+
+#include "gd32vf103_dbg.h"
+
+#define DBG_KEY_UNLOCK 0x4B5A6978
+#define DBG_CMD_RESET 0x1
+
+#define DBG_KEY REG32(DBG + 0x0C)
+#define DBG_CMD REG32(DBG + 0x08)
+
+void gd32vf103_reset(void) {
+  /* The MTIMER unit of the GD32VF103 doesn't have the MSFRST
+   * register to generate a software reset request.
+   * BUT instead two undocumented registers in the debug peripheral
+   * that allow issueing a software reset.
+   * https://github.com/esmil/gd32vf103inator/blob/master/include/gd32vf103/dbg.h
+   */
+  DBG_KEY = DBG_KEY_UNLOCK;
+  DBG_CMD = DBG_CMD_RESET;
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  gpio_bit_write(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == gpio_input_bit_get(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+#if defined(UART_DEV) && CFG_TUSB_DEBUG
+
+  int rxsize = len;
+  while (rxsize--) {
+    *(uint8_t*)buf = usart_read(UART_DEV);
+    buf++;
+  }
+  return len;
+#else
+  (void)buf;
+  (void)len;
+  return 0;
+#endif
+}
+
+int board_uart_write(void const* buf, int len) {
+#if defined(UART_DEV) && CFG_TUSB_DEBUG
+
+  int txsize = len;
+  while (txsize--) {
+    usart_write(UART_DEV, *(uint8_t*)buf);
+    buf++;
+  }
+  return len;
+#else
+  (void)buf;
+  (void)len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void eclic_mtip_handler(void) { system_ticks++; }
+uint32_t board_millis(void) { return system_ticks; }
+#endif
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief  Reports the name of the source file and the source line number
+ *         where the assert_param error has occurred.
+ * @param  file: pointer to the source file name
+ * @param  line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(char* file, uint32_t line) {
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line
+     number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line)
+   */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+// void _init(void) {}
diff --git a/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h b/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
new file mode 100644
index 000000000..eacfb5eef
--- /dev/null
+++ b/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
@@ -0,0 +1,20 @@
+// See LICENSE for license details.
+#ifndef _NUCLEI_SDK_HAL_H
+#define _NUCLEI_SDK_HAL_H
+
+#include "nmsis_gcc.h"
+#include "gd32vf103.h"
+#include "gd32vf103_libopt.h"
+#include "drv_usb_hw.h"
+#include "drv_usb_dev.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SOC_DEBUG_UART      USART0
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c b/hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c
new file mode 100644
index 000000000..54c8804c4
--- /dev/null
+++ b/hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c
@@ -0,0 +1,1256 @@
+/*!
+ \file    system_gd32vf103.h
+\brief   RISC-V Device Peripheral Access Layer Source File for
+          GD32VF103 Device Series
+
+*/
+
+/*
+    Copyright (c) 2020, GigaDevice Semiconductor Inc.
+
+    Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+    1. Redistributions of source code must retain the above copyright notice, this
+       list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
+       and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
+       specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+*/
+
+/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */
+
+#include "gd32vf103_libopt.h"
+
+/* system frequency define */
+#define __IRC8M           (IRC8M_VALUE)            /* internal 8 MHz RC oscillator frequency */
+#define __HXTAL           (HXTAL_VALUE)            /* high speed crystal oscillator frequency */
+#define __SYS_OSC_CLK     (__IRC8M)                /* main oscillator frequency */
+
+/* select a system clock by uncommenting the following line */
+/* use IRC8M */
+//#define __SYSTEM_CLOCK_48M_PLL_IRC8M            (uint32_t)(48000000)
+//#define __SYSTEM_CLOCK_72M_PLL_IRC8M            (uint32_t)(72000000)
+//#define __SYSTEM_CLOCK_108M_PLL_IRC8M           (uint32_t)(108000000)
+
+/********************************************************************/
+//#define __SYSTEM_CLOCK_HXTAL                    (HXTAL_VALUE)
+//#define __SYSTEM_CLOCK_24M_PLL_HXTAL            (uint32_t)(24000000)
+/********************************************************************/
+
+//#define __SYSTEM_CLOCK_36M_PLL_HXTAL            (uint32_t)(36000000)
+//#define __SYSTEM_CLOCK_48M_PLL_HXTAL            (uint32_t)(48000000)
+//#define __SYSTEM_CLOCK_56M_PLL_HXTAL            (uint32_t)(56000000)
+//#define __SYSTEM_CLOCK_72M_PLL_HXTAL            (uint32_t)(72000000)
+#define __SYSTEM_CLOCK_96M_PLL_HXTAL            (uint32_t)(96000000)
+//#define __SYSTEM_CLOCK_108M_PLL_HXTAL           (uint32_t)(108000000)
+
+/*#define SEL_IRC8M       0x00U
+#define SEL_HXTAL       0x01U
+#define SEL_PLL         0x02U*/
+
+/* set the system clock frequency and declare the system clock configuration function */
+#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M;
+static void system_clock_48m_irc8m(void);
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M;
+static void system_clock_72m_irc8m(void);
+#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M;
+static void system_clock_108m_irc8m(void);
+
+#elif defined (__SYSTEM_CLOCK_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
+static void system_clock_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL;
+static void system_clock_24m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL;
+static void system_clock_36m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL;
+static void system_clock_48m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL;
+static void system_clock_56m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
+static void system_clock_72m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL;
+static void system_clock_96m_hxtal(void);
+#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
+uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL;
+static void system_clock_108m_hxtal(void);
+#else
+uint32_t SystemCoreClock = IRC8M_VALUE;
+#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */
+
+/* configure the system clock */
+static void system_clock_config(void);
+
+/*!
+    \brief      configure the system clock
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_config(void)
+{
+#ifdef __SYSTEM_CLOCK_HXTAL
+    system_clock_hxtal();
+#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL)
+    system_clock_24m_hxtal();
+#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL)
+    system_clock_36m_hxtal();
+#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
+    system_clock_48m_hxtal();
+#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL)
+    system_clock_56m_hxtal();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+    system_clock_72m_hxtal();
+#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
+    system_clock_96m_hxtal();
+#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
+    system_clock_108m_hxtal();
+
+#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
+    system_clock_48m_irc8m();
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
+    system_clock_72m_irc8m();
+#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
+    system_clock_108m_irc8m();
+#endif /* __SYSTEM_CLOCK_HXTAL */
+}
+
+/*!
+    \brief      setup the microcontroller system, initialize the system
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SystemInit(void)
+{
+    /* reset the RCC clock configuration to the default reset state */
+    /* enable IRC8M */
+    RCU_CTL |= RCU_CTL_IRC8MEN;
+    
+    /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */
+    RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
+                  RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL);
+
+    /* reset HXTALEN, CKMEN, PLLEN bits */
+    RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN);
+
+    /* Reset HXTALBPS bit */
+    RCU_CTL &= ~(RCU_CTL_HXTALBPS);
+
+    /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */
+    
+    RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
+                  RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4);
+    RCU_CFG1 = 0x00000000U;
+
+    /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
+    RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
+    /* disable all interrupts */
+    RCU_INT = 0x00FF0000U;
+
+    /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
+    system_clock_config();
+}
+
+/*!
+    \brief      update the SystemCoreClock with current core clock retrieved from cpu registers
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+void SystemCoreClockUpdate(void)
+{
+    uint32_t scss;
+    uint32_t pllsel, predv0sel, pllmf, ck_src;
+    uint32_t predv0, predv1, pll1mf;
+
+    scss = GET_BITS(RCU_CFG0, 2, 3);
+
+    switch (scss)
+    {
+        /* IRC8M is selected as CK_SYS */
+        case SEL_IRC8M:
+            SystemCoreClock = IRC8M_VALUE;
+            break;
+            
+        /* HXTAL is selected as CK_SYS */
+        case SEL_HXTAL:
+            SystemCoreClock = HXTAL_VALUE;
+            break;
+            
+        /* PLL is selected as CK_SYS */
+        case SEL_PLL:
+            /* PLL clock source selection, HXTAL or IRC8M/2 */
+            pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
+
+
+            if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){
+                /* PLL clock source is IRC8M/2 */
+                ck_src = IRC8M_VALUE / 2U;
+            }else{
+                /* PLL clock source is HXTAL */
+                ck_src = HXTAL_VALUE;
+
+                predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
+
+                /* source clock use PLL1 */
+                if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
+                    predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
+                    pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
+                    if(17U == pll1mf){
+                        pll1mf = 20U;
+                    }
+                    ck_src = (ck_src / predv1) * pll1mf;
+                }
+                predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
+                ck_src /= predv0;
+            }
+
+            /* PLL multiplication factor */
+            pllmf = GET_BITS(RCU_CFG0, 18, 21);
+
+            if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
+                pllmf |= 0x10U;
+            }
+
+            if(pllmf >= 15U){
+                pllmf += 1U;
+            }else{
+                pllmf += 2U;
+            }
+
+            SystemCoreClock = ck_src * pllmf;
+
+            if(15U == pllmf){
+                /* PLL source clock multiply by 6.5 */
+                SystemCoreClock = ck_src * 6U + ck_src / 2U;
+            }
+
+            break;
+
+        /* IRC8M is selected as CK_SYS */
+        default:
+            SystemCoreClock = IRC8M_VALUE;
+            break;
+    }
+}
+
+#ifdef __SYSTEM_CLOCK_HXTAL
+/*!
+    \brief      configure the system clock to HXTAL
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+    
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+    
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+    
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+    
+    /* select HXTAL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
+    
+    /* wait until HXTAL is selected as system clock */
+    while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_24m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6);
+
+    if(HXTAL_VALUE==25000000){
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_36m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
+
+    if(HXTAL_VALUE==25000000){
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_48m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12);
+
+    if(HXTAL_VALUE==25000000){
+
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_56m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14);
+
+    if(HXTAL_VALUE==25000000){
+
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_72m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ 
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18);
+
+
+    if(HXTAL_VALUE==25000000){
+
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_96m_hxtal(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    if(HXTAL_VALUE==25000000){
+
+        /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */
+        RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+        RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24);
+
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
+        }
+
+    }else if(HXTAL_VALUE==8000000){
+        /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */
+        RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+        RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24);
+
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
+    }
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
+/*!
+    \brief      configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+
+static void system_clock_108m_hxtal(void)
+{
+    uint32_t timeout   = 0U;
+    uint32_t stab_flag = 0U;
+
+    /* enable HXTAL */
+    RCU_CTL |= RCU_CTL_HXTALEN;
+
+    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
+    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
+        while(1){
+        }
+    }
+
+    /* HXTAL is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ 
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27);
+
+    if(HXTAL_VALUE==25000000){
+        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){
+        }
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL2EN;
+        /* wait till PLL1 is ready */
+        while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){
+        }
+    }else if(HXTAL_VALUE==8000000){
+        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
+        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20);
+
+        /* enable PLL1 */
+        RCU_CTL |= RCU_CTL_PLL1EN;
+        /* wait till PLL1 is ready */
+        while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){
+        }
+
+        /* enable PLL2 */
+        RCU_CTL |= RCU_CTL_PLL2EN;
+        /* wait till PLL1 is ready */
+        while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){
+        }
+
+    }
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
+/*!
+    \brief      configure the system clock to 48M by PLL which selects IRC8M as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_48m_irc8m(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    
+    /* enable IRC8M */
+    RCU_CTL |= RCU_CTL_IRC8MEN;
+
+    /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
+    }
+    while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
+      while(1){
+      }
+    }
+
+    /* IRC8M is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= RCU_PLL_MUL12;
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
+/*!
+    \brief      configure the system clock to 72M by PLL which selects IRC8M as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_72m_irc8m(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    
+    /* enable IRC8M */
+    RCU_CTL |= RCU_CTL_IRC8MEN;
+
+    /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
+    }
+    while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
+      while(1){
+      }
+    }
+
+    /* IRC8M is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= RCU_PLL_MUL18;
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
+/*!
+    \brief      configure the system clock to 108M by PLL which selects IRC8M as its clock source
+    \param[in]  none
+    \param[out] none
+    \retval     none
+*/
+static void system_clock_108m_irc8m(void)
+{
+    uint32_t timeout = 0U;
+    uint32_t stab_flag = 0U;
+    
+    /* enable IRC8M */
+    RCU_CTL |= RCU_CTL_IRC8MEN;
+
+    /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
+    do{
+        timeout++;
+        stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
+    }
+    while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
+
+    /* if fail */
+    if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
+      while(1){
+      }
+    }
+
+    /* IRC8M is stable */
+    /* AHB = SYSCLK */
+    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
+    /* APB2 = AHB/1 */
+    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
+    /* APB1 = AHB/2 */
+    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
+
+    /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
+    RCU_CFG0 |= RCU_PLL_MUL27;
+
+    /* enable PLL */
+    RCU_CTL |= RCU_CTL_PLLEN;
+
+    /* wait until PLL is stable */
+    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
+    }
+
+    /* select PLL as system clock */
+    RCU_CFG0 &= ~RCU_CFG0_SCS;
+    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
+
+    /* wait until PLL is selected as system clock */
+    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
+    }
+}
+
+#endif
+
+/**
+ * \defgroup  NMSIS_Core_IntExcNMI_Handling   Interrupt and Exception and NMI Handling
+ * \brief Functions for interrupt, exception and nmi handle available in system_<device>.c.
+ * \details
+ * Nuclei provide a template for interrupt, exception and NMI handling. Silicon Vendor could adapat according
+ * to their requirement. Silicon vendor could implement interface for different exception code and
+ * replace current implementation.
+ *
+ * @{
+ */
+/** \brief Max exception handler number, don't include the NMI(0xFFF) one */
+#define MAX_SYSTEM_EXCEPTION_NUM        12
+/**
+ * \brief      Store the exception handlers for each exception ID
+ * \note
+ * - This SystemExceptionHandlers are used to store all the handlers for all
+ * the exception codes Nuclei N/NX core provided.
+ * - Exception code 0 - 11, totally 12 exceptions are mapped to SystemExceptionHandlers[0:11]
+ * - Exception for NMI is also re-routed to exception handling(exception code 0xFFF) in startup code configuration, the handler itself is mapped to SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM]
+ */
+static unsigned long SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM + 1];
+
+/**
+ * \brief      Exception Handler Function Typedef
+ * \note
+ * This typedef is only used internal in this system_gd32vf103.c file.
+ * It is used to do type conversion for registered exception handler before calling it.
+ */
+typedef void (*EXC_HANDLER)(unsigned long mcause, unsigned long sp);
+
+/**
+ * \brief      System Default Exception Handler
+ * \details
+ * This function provided a default exception and NMI handling code for all exception ids.
+ * By default, It will just print some information for debug, Vendor can customize it according to its requirements.
+ */
+static void system_default_exception_handler(unsigned long mcause, unsigned long sp)
+{
+    /* TODO: Uncomment this if you have implement printf function */
+    /*printf("MCAUSE: 0x%lx\r\n", mcause);
+    printf("MEPC  : 0x%lx\r\n", __RV_CSR_READ(CSR_MEPC));
+    printf("MTVAL : 0x%lx\r\n", __RV_CSR_READ(CSR_MBADADDR));*/
+    while (1);
+}
+
+/**
+ * \brief      Initialize all the default core exception handlers
+ * \details
+ * The core exception handler for each exception id will be initialized to \ref system_default_exception_handler.
+ * \note
+ * Called in \ref _init function, used to initialize default exception handlers for all exception IDs
+ */
+static void Exception_Init(void)
+{
+    for (int i = 0; i < MAX_SYSTEM_EXCEPTION_NUM + 1; i++) {
+        SystemExceptionHandlers[i] = (unsigned long)system_default_exception_handler;
+    }
+}
+
+/**
+ * \brief       Register an exception handler for exception code EXCn
+ * \details
+ * * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will be registered into SystemExceptionHandlers[EXCn-1].
+ * * For EXCn == NMI_EXCn, it will be registered into SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM].
+ * \param   EXCn    See \ref EXCn_Type
+ * \param   exc_handler     The exception handler for this exception code EXCn
+ */
+void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler)
+{
+    if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn != 0)) {
+        SystemExceptionHandlers[EXCn] = exc_handler;
+    } else if (EXCn == NMI_EXCn) {
+        SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM] = exc_handler;
+    }
+}
+
+/**
+ * \brief       Get current exception handler for exception code EXCn
+ * \details
+ * * For EXCn < \ref MAX_SYSTEM_EXCEPTION_NUM, it will return SystemExceptionHandlers[EXCn-1].
+ * * For EXCn == NMI_EXCn, it will return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM].
+ * \param   EXCn    See \ref EXCn_Type
+ * \return  Current exception handler for exception code EXCn, if not found, return 0.
+ */
+unsigned long Exception_Get_EXC(uint32_t EXCn)
+{
+    if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn != 0)) {
+        return SystemExceptionHandlers[EXCn];
+    } else if (EXCn == NMI_EXCn) {
+        return SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM];
+    } else {
+        return 0;
+    }
+}
+
+/**
+ * \brief      Common NMI and Exception handler entry
+ * \details
+ * This function provided a command entry for NMI and exception. Silicon Vendor could modify
+ * this template implementation according to requirement.
+ * \remarks
+ * - RISCV provided common entry for all types of exception. This is proposed code template
+ *   for exception entry function, Silicon Vendor could modify the implementation.
+ * - For the core_exception_handler template, we provided exception register function \ref Exception_Register_EXC
+ *   which can help developer to register your exception handler for specific exception number.
+ */
+uint32_t core_exception_handler(unsigned long mcause, unsigned long sp)
+{
+    uint32_t EXCn = (uint32_t)(mcause & 0X00000fff);
+    EXC_HANDLER exc_handler;
+
+    if ((EXCn < MAX_SYSTEM_EXCEPTION_NUM) && (EXCn > 0)) {
+        exc_handler = (EXC_HANDLER)SystemExceptionHandlers[EXCn];
+    } else if (EXCn == NMI_EXCn) {
+        exc_handler = (EXC_HANDLER)SystemExceptionHandlers[MAX_SYSTEM_EXCEPTION_NUM];
+    } else {
+        exc_handler = (EXC_HANDLER)system_default_exception_handler;
+    }
+    if (exc_handler != NULL) {
+        exc_handler(mcause, sp);
+    }
+    return 0;
+}
+/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
+
+void SystemBannerPrint(void)
+{
+#if defined(NUCLEI_BANNER) && (NUCLEI_BANNER == 1)
+#ifndef DOWNLOAD_MODE
+#error DOWNLOAD_MODE is not defined via build system, please check!
+#endif
+    const char* download_modes[] = {"FLASHXIP", "FLASH", "ILM", "DDR"};
+    printf("Nuclei SDK Build Time: %s, %s\r\n", __DATE__, __TIME__);
+    printf("Download Mode: %s\r\n", download_modes[DOWNLOAD_MODE]);
+    printf("CPU Frequency %d Hz\r\n", SystemCoreClock);
+#endif
+}
+
+/**
+ * \brief initialize eclic config
+ * \details
+ * Eclic need initialize after boot up, Vendor could also change the initialization
+ * configuration.
+ */
+void ECLIC_Init(void)
+{
+    /* TODO: Add your own initialization code here. This function will be called by main */
+    ECLIC_SetMth(0);
+    ECLIC_SetCfgNlbits(__ECLIC_INTCTLBITS);
+}
+
+/**
+ * \brief  Initialize a specific IRQ and register the handler
+ * \details
+ * This function set vector mode, trigger mode and polarity, interrupt level and priority,
+ * assign handler for specific IRQn.
+ * \param [in]  IRQn        NMI interrupt handler address
+ * \param [in]  shv         \ref ECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and \ref ECLIC_VECTOR_INTERRUPT is vector mode
+ * \param [in]  trig_mode   see \ref ECLIC_TRIGGER_Type
+ * \param [in]  lvl         interupt level
+ * \param [in]  priority    interrupt priority
+ * \param [in]  handler     interrupt handler, if NULL, handler will not be installed
+ * \return       -1 means invalid input parameter. 0 means successful.
+ * \remarks
+ * - This function use to configure specific eclic interrupt and register its interrupt handler and enable its interrupt.
+ * - If the vector table is placed in read-only section(FLASHXIP mode), handler could not be installed
+ */
+int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler)
+{
+    if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) \
+        || (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
+        return -1;
+    }
+
+    /* set interrupt vector mode */
+    ECLIC_SetShvIRQ(IRQn, shv);
+    /* set interrupt trigger mode and polarity */
+    ECLIC_SetTrigIRQ(IRQn, trig_mode);
+    /* set interrupt level */
+    ECLIC_SetLevelIRQ(IRQn, lvl);
+    /* set interrupt priority */
+    ECLIC_SetPriorityIRQ(IRQn, priority);
+    if (handler != NULL) {
+        /* set interrupt handler entry to vector table */
+        ECLIC_SetVector(IRQn, (rv_csr_t)handler);
+    }
+    /* enable interrupt */
+    ECLIC_EnableIRQ(IRQn);
+    return 0;
+}
+/** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
+
+/**
+ * \brief early init function before main
+ * \details
+ * This function is executed right before main function.
+ * For RISC-V gnu toolchain, _init function might not be called
+ * by __libc_init_array function, so we defined a new function
+ * to do initialization
+ */
+void _premain_init(void)
+{
+    /* TODO: Add your own initialization code here, called before main */
+    //SystemCoreClock = get_cpu_freq();
+    /* configure USART */
+    /*gd_com_init(SOC_DEBUG_UART);*/
+    /* Display banner after UART initialized */
+    /*SystemBannerPrint();*/
+    /* Initialize exception default handlers */
+    Exception_Init();
+    /* ECLIC initialization, mainly MTH and NLBIT */
+    ECLIC_Init();
+}
+
+/**
+ * \brief finish function after main
+ * \param [in]  status     status code return from main
+ * \details
+ * This function is executed right after main function.
+ * For RISC-V gnu toolchain, _fini function might not be called
+ * by __libc_fini_array function, so we defined a new function
+ * to do initialization
+ */
+void _postmain_fini(int status)
+{
+    /* TODO: Add your own finishing code here, called after main */
+}
+
+/**
+ * \brief _init function called in __libc_init_array()
+ * \details
+ * This `__libc_init_array()` function is called during startup code,
+ * user need to implement this function, otherwise when link it will
+ * error init.c:(.text.__libc_init_array+0x26): undefined reference to `_init'
+ * \note
+ * Please use \ref _premain_init function now
+ */
+void _init(void)
+{
+    /* Don't put any code here, please use _premain_init now */
+}
+
+/**
+ * \brief _fini function called in __libc_fini_array()
+ * \details
+ * This `__libc_fini_array()` function is called when exit main.
+ * user need to implement this function, otherwise when link it will
+ * error fini.c:(.text.__libc_fini_array+0x28): undefined reference to `_fini'
+ * \note
+ * Please use \ref _postmain_fini function now
+ */
+void _fini(void)
+{
+    /* Don't put any code here, please use _postmain_fini now */
+}
+
+/** @} */ /* End of Doxygen Group NMSIS_Core_SystemAndClock */
diff --git a/hw/mcu/gd/nuclei-sdk b/hw/mcu/gd/nuclei-sdk
new file mode 160000
index 000000000..834e02fa7
--- /dev/null
+++ b/hw/mcu/gd/nuclei-sdk
@@ -0,0 +1 @@
+Subproject commit 834e02fa7fcc9bb1823cf517003296e01adaa7c7

From ddb83787a00c20db8f92b00dc78c8c1ee972c489 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 10 Jul 2021 11:21:24 +0200
Subject: [PATCH 0292/2085] Disable -Werror for now

Without having __riscv_flen defined we get multiple warinings. But
defining it causes the startup code to contain floating point instructions.
This results in a exception right after booting.

See startup_gd32vf103.S lines 289-294 should open a PR at nuclei sdk
---
 examples/make.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/make.mk b/examples/make.mk
index 9daf60e35..70ce77b41 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -91,7 +91,6 @@ CFLAGS += \
   -Wstrict-overflow \
   -Wall \
   -Wextra \
-  -Werror \
   -Wfatal-errors \
   -Werror-implicit-function-declaration \
   -Wfloat-equal \
@@ -102,7 +101,8 @@ CFLAGS += \
   -Wmissing-format-attribute \
   -Wunreachable-code \
   -Wcast-align \
-  -Wcast-function-type
+  -Wcast-function-type \
+  # -Werror disable for now\
 
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)

From 771bbe8af7d1ab1785dc9b244c2b41ec0742968c Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 10 Jul 2021 11:24:37 +0200
Subject: [PATCH 0293/2085] Use https github as submodule

---
 .gitmodules | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.gitmodules b/.gitmodules
index 1636b9765..4c86fd55c 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -126,4 +126,4 @@
 	url = https://github.com/zhangslice/mm32sdk.git
 [submodule "hw/mcu/gd/nuclei-sdk"]
 	path = hw/mcu/gd/nuclei-sdk
-	url = git@github.com:Nuclei-Software/nuclei-sdk.git
+	url = https://github.com/Nuclei-Software/nuclei-sdk.git

From 3db2089aa9b8139a996ee2003be6b3faff6ffad2 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 10 Jul 2021 11:47:42 +0200
Subject: [PATCH 0294/2085] Minor clean ups

---
 hw/bsp/gd32vf103_longan_nano/board.mk         |  8 ++++----
 .../gd32vf103_longan_nano.c                   | 20 ++++---------------
 hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h |  9 +++++++++
 3 files changed, 17 insertions(+), 20 deletions(-)

diff --git a/hw/bsp/gd32vf103_longan_nano/board.mk b/hw/bsp/gd32vf103_longan_nano/board.mk
index f34f68c22..86dc1dcef 100644
--- a/hw/bsp/gd32vf103_longan_nano/board.mk
+++ b/hw/bsp/gd32vf103_longan_nano/board.mk
@@ -21,15 +21,14 @@ CFLAGS += \
 #CFLAGS += -Wno-error=unused-parameter
 
 # All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/gcc_gd32vf103xb_flashxip.ld # 128kb ROM 32kb RAM
-# LD_FILE = hw/bsp/$(BOARD)/gcc_gd32vf103x8_flashxip.ld # 64kb ROM 20kb RAM Longan Nano Lite
+LD_FILE = hw/bsp/$(BOARD)/gcc_gd32vf103xb_flashxip.ld # Longan Nano 128k ROM 32k RAM
+# LD_FILE = hw/bsp/$(BOARD)/gcc_gd32vf103x8_flashxip.ld # Longan Nano Lite 64k ROM 20k RAM 
 
 SRC_C += \
   src/portable/st/synopsys/dcd_synopsys.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
 	$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
-	$(GD32VF103_SDK_DRIVER)/gd32vf103_fmc.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_usart.c \
 	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/sbrk.c \
 	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/close.c \
@@ -52,7 +51,8 @@ INC += \
 #FREERTOS_PORT = ARM_CM3
 
 # For flash-jlink target
-JLINK_DEVICE = gd32vf103cb
+JLINK_DEVICE = gd32vf103cbt6 # Longan Nano 128k ROM 32k RAM
+#JLINK_DEVICE = gd32vf103c8t6 # Longan Nano Lite 64k ROM 20k RAM
 
 # flash target ROM bootloader
 flash: $(BUILD)/$(PROJECT).bin
diff --git a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
index f501c20b4..6affd6fa5 100644
--- a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
+++ b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
@@ -39,7 +39,7 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); }
 
 #define HXTAL_VALUE \
   ((uint32_t)8000000) /*!< value of the external oscillator in Hz */
-#define USB_NO_VBUS_PIN 1
+#define USB_NO_VBUS_PIN
 
 //--------------------------------------------------------------------+
 // LED
@@ -62,16 +62,6 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); }
 #define UART_TX_PIN GPIO_PIN_9
 #define UART_RX_PIN GPIO_PIN_10
 
-/* sipeed longan nano board UART com port */
-#define GD32_COM0 USART0
-#define GD32_COM_CLK RCU_USART0
-#define GD32_COM_TX_PIN GPIO_PIN_9
-#define GD32_COM_RX_PIN GPIO_PIN_10
-#define GD32_COM_TX_GPIO_PORT GPIOA
-#define GD32_COM_RX_GPIO_PORT GPIOA
-#define GD32_COM_TX_GPIO_CLK RCU_GPIOA
-#define GD32_COM_RX_GPIO_CLK RCU_GPIOA
-
 void board_init(void) {
   /* Disable interrupts during init */
   __disable_irq();
@@ -117,7 +107,7 @@ void board_init(void) {
   board_led_write(0);
 #endif
 
-#if defined(UART_DEV) && CFG_TUSB_DEBUG
+#if defined(UART_DEV)
   /* enable GPIO TX and RX clock */
   rcu_periph_clock_enable(GD32_COM_TX_GPIO_CLK);
   rcu_periph_clock_enable(GD32_COM_RX_GPIO_CLK);
@@ -214,8 +204,7 @@ uint32_t board_button_read(void) {
 }
 
 int board_uart_read(uint8_t* buf, int len) {
-#if defined(UART_DEV) && CFG_TUSB_DEBUG
-
+#if defined(UART_DEV)
   int rxsize = len;
   while (rxsize--) {
     *(uint8_t*)buf = usart_read(UART_DEV);
@@ -230,8 +219,7 @@ int board_uart_read(uint8_t* buf, int len) {
 }
 
 int board_uart_write(void const* buf, int len) {
-#if defined(UART_DEV) && CFG_TUSB_DEBUG
-
+#if defined(UART_DEV)
   int txsize = len;
   while (txsize--) {
     usart_write(UART_DEV, *(uint8_t*)buf);
diff --git a/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h b/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
index eacfb5eef..f8245cc48 100644
--- a/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
+++ b/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
@@ -12,7 +12,16 @@
 extern "C" {
 #endif
 
+/* sipeed longan nano board UART com port */
 #define SOC_DEBUG_UART      USART0
+#define GD32_COM0 USART0
+#define GD32_COM_CLK RCU_USART0
+#define GD32_COM_TX_PIN GPIO_PIN_9
+#define GD32_COM_RX_PIN GPIO_PIN_10
+#define GD32_COM_TX_GPIO_PORT GPIOA
+#define GD32_COM_RX_GPIO_PORT GPIOA
+#define GD32_COM_TX_GPIO_CLK RCU_GPIOA
+#define GD32_COM_RX_GPIO_CLK RCU_GPIOA
 
 #ifdef __cplusplus
 }

From 23e3b1680be72ac72db14e6e5518c0b7e633b781 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 10 Jul 2021 14:03:20 +0200
Subject: [PATCH 0295/2085] Use JTAG for jlink flashing

---
 hw/bsp/gd32vf103_longan_nano/board.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/bsp/gd32vf103_longan_nano/board.mk b/hw/bsp/gd32vf103_longan_nano/board.mk
index 86dc1dcef..538cbae73 100644
--- a/hw/bsp/gd32vf103_longan_nano/board.mk
+++ b/hw/bsp/gd32vf103_longan_nano/board.mk
@@ -51,6 +51,7 @@ INC += \
 #FREERTOS_PORT = ARM_CM3
 
 # For flash-jlink target
+JLINK_IF = jtag
 JLINK_DEVICE = gd32vf103cbt6 # Longan Nano 128k ROM 32k RAM
 #JLINK_DEVICE = gd32vf103c8t6 # Longan Nano Lite 64k ROM 20k RAM
 

From 790d90bf263daabd08718f1847f0e315abdea380 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sun, 11 Jul 2021 14:17:32 +0200
Subject: [PATCH 0296/2085] Set FreeRTOS to RISC-V (doesn't compile)

---
 hw/bsp/gd32vf103_longan_nano/board.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/gd32vf103_longan_nano/board.mk b/hw/bsp/gd32vf103_longan_nano/board.mk
index 538cbae73..0c0c26427 100644
--- a/hw/bsp/gd32vf103_longan_nano/board.mk
+++ b/hw/bsp/gd32vf103_longan_nano/board.mk
@@ -48,7 +48,7 @@ INC += \
 	$(TOP)/$(GD32VF103_SDK_SOC_COMMON)/Include/Usb \
 
 # For freeRTOS port source
-#FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = RISC-V
 
 # For flash-jlink target
 JLINK_IF = jtag

From e5bd6bdeffd11cea6a998dfa8ebb89978ac8fff0 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Mon, 12 Jul 2021 09:54:49 +0200
Subject: [PATCH 0297/2085] Update nuclei-sdk with __riscv_flen fix

---
 hw/mcu/gd/nuclei-sdk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/gd/nuclei-sdk b/hw/mcu/gd/nuclei-sdk
index 834e02fa7..7eb7bfa9e 160000
--- a/hw/mcu/gd/nuclei-sdk
+++ b/hw/mcu/gd/nuclei-sdk
@@ -1 +1 @@
-Subproject commit 834e02fa7fcc9bb1823cf517003296e01adaa7c7
+Subproject commit 7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7

From ab1979e2d35d5246335f41008375ffb471b44e7c Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Mon, 12 Jul 2021 09:55:44 +0200
Subject: [PATCH 0298/2085] Revert "Disable -Werror for now"

This reverts commit 5e0c2e122300e7a6289b3bd08044f9cf1dbdef05.
---
 examples/make.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/make.mk b/examples/make.mk
index 70ce77b41..9daf60e35 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -91,6 +91,7 @@ CFLAGS += \
   -Wstrict-overflow \
   -Wall \
   -Wextra \
+  -Werror \
   -Wfatal-errors \
   -Werror-implicit-function-declaration \
   -Wfloat-equal \
@@ -101,8 +102,7 @@ CFLAGS += \
   -Wmissing-format-attribute \
   -Wunreachable-code \
   -Wcast-align \
-  -Wcast-function-type \
-  # -Werror disable for now\
+  -Wcast-function-type
 
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)

From 3eb54d878af0492a85fab2811b5f84187c2f703c Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Tue, 3 Aug 2021 20:21:06 +0200
Subject: [PATCH 0299/2085] Add stm32 license header

---
 src/portable/st/synopsys/synopsys_common.h | 55 ++++++++++++++--------
 1 file changed, 36 insertions(+), 19 deletions(-)

diff --git a/src/portable/st/synopsys/synopsys_common.h b/src/portable/st/synopsys/synopsys_common.h
index 4e71e8258..6f0602fe9 100644
--- a/src/portable/st/synopsys/synopsys_common.h
+++ b/src/portable/st/synopsys/synopsys_common.h
@@ -1,29 +1,45 @@
+/**
+  ******************************************************************************
+  * @file    synopsys_common.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M3 Device USB OTG peripheral Header File. 
+  *          This file contains the USB OTG peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F1xx devices.
+  *            
+  *          This file contains:
+  *           - Data structures and the address mapping for the USB OTG peripheral
+  *           - The Peripheral's registers declarations and bits definition
+  *           - Macros to access the peripheral's registers hardware
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
 #include "stdint.h"
 
 #pragma once
 
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
 #ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
+  #define   __I   volatile
 #else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+  #define   __I   volatile const
 #endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+#define     __O   volatile
+#define     __IO  volatile
+#define     __IM  volatile const
+#define     __OM  volatile
+#define     __IOM volatile
 
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M3 */
 /** 
   * @brief __USB_OTG_Core_register
   */
@@ -155,7 +171,6 @@ typedef struct
 #define USB_OTG_FIFO_BASE                    0x00001000UL
 #define USB_OTG_FIFO_SIZE                    0x00001000UL
 
-
 /******************************************************************************/
 /*                                                                            */
 /*                                 USB_OTG                                    */
@@ -1446,3 +1461,5 @@ typedef struct
 #define USB_OTG_FRMNUM_1                        (0x2UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00400000 */
 #define USB_OTG_FRMNUM_2                        (0x4UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00800000 */
 #define USB_OTG_FRMNUM_3                        (0x8UL << USB_OTG_FRMNUM_Pos)   /*!< 0x01000000 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

From 546d869ffb8d80b785cc7ceabd876223fbc1ca93 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Wed, 4 Aug 2021 16:25:01 +0100
Subject: [PATCH 0300/2085] readme: fix link to online documentation

---
 README.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index 6de51535b..9e7c3139b 100644
--- a/README.rst
+++ b/README.rst
@@ -8,7 +8,7 @@ embedded system, designed to be memory-safe with no dynamic allocation
 and thread-safe with all interrupt events are deferred then handled in
 the non-ISR task function.
 
-Please take a look at the online `documentation <www.tinyusb.org>`__.
+Please take a look at the online `documentation <https://www.tinyusb.org/>`__.
 
 .. figure:: docs/assets/stack.svg
    :width: 500px

From 2b521e0c101c371d1b0f36d594aa1e20642b9603 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 5 Aug 2021 12:29:32 +0700
Subject: [PATCH 0301/2085] rename to .readthedocs.yaml

exclude all submodules for docs
---
 .readthedocs.yml => .readthedocs.yaml | 5 +++++
 1 file changed, 5 insertions(+)
 rename .readthedocs.yml => .readthedocs.yaml (83%)

diff --git a/.readthedocs.yml b/.readthedocs.yaml
similarity index 83%
rename from .readthedocs.yml
rename to .readthedocs.yaml
index 215b5fed1..e83cd90fd 100644
--- a/.readthedocs.yml
+++ b/.readthedocs.yaml
@@ -11,3 +11,8 @@ python:
   version: 3.8
   install:
     - requirements: docs/requirements.txt
+
+submodules:
+  include: []
+  recursive: false
+    
\ No newline at end of file

From b5d218e6845da43f693e5caa31d883de3b997f41 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 5 Aug 2021 14:06:08 +0700
Subject: [PATCH 0302/2085] add html extra for webusb example

---
 README.rst                                    |   2 +-
 docs/conf.py                                  |   3 +
 .../examples/webusb-serial/application.css    | 107 ++++++++++++++++++
 .../examples/webusb-serial/application.js     |  90 +++++++++++++++
 .../examples/webusb-serial/index.html         |  33 ++++++
 .../examples/webusb-serial/serial.js          |  89 +++++++++++++++
 6 files changed, 323 insertions(+), 1 deletion(-)
 create mode 100644 docs/html_extra/examples/webusb-serial/application.css
 create mode 100644 docs/html_extra/examples/webusb-serial/application.js
 create mode 100644 docs/html_extra/examples/webusb-serial/index.html
 create mode 100644 docs/html_extra/examples/webusb-serial/serial.js

diff --git a/README.rst b/README.rst
index 9e7c3139b..8a92c267f 100644
--- a/README.rst
+++ b/README.rst
@@ -122,7 +122,7 @@ in your project.
 .. |Build Status| image:: https://github.com/hathach/tinyusb/workflows/Build/badge.svg
    :target: https://github.com/hathach/tinyusb/actions
 .. |Documentation Status| image:: https://readthedocs.org/projects/tinyusb/badge/?version=latest
-   :target: https://openinput.readthedocs.io/en/latest/?badge=latest
+   :target: https://tinyusb.readthedocs.io/en/latest/?badge=latest
 .. |License| image:: https://img.shields.io/badge/license-MIT-brightgreen.svg
    :target: https://opensource.org/licenses/MIT
 
diff --git a/docs/conf.py b/docs/conf.py
index c7a17478f..1d05d7cb6 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -39,4 +39,7 @@ html_theme_options = {
     'sidebar_hide_name': True,
 }
 
+# examples for webusb
+html_extra_path = ['html_extra']
+
 todo_include_todos = True
diff --git a/docs/html_extra/examples/webusb-serial/application.css b/docs/html_extra/examples/webusb-serial/application.css
new file mode 100644
index 000000000..4ae0138bd
--- /dev/null
+++ b/docs/html_extra/examples/webusb-serial/application.css
@@ -0,0 +1,107 @@
+.main-content {
+  width: 1440px;
+  margin: auto;
+  font-size: 14px;
+}
+
+.connect-container {
+  margin: 20px 0;
+}
+
+.container {
+  display: flex;
+}
+
+.sender, .receiver {
+  flex: 1;
+}
+
+.sender {
+  margin-right: 8px;
+}
+
+.receiver {
+  margin-left: 8px;
+}
+
+.lines-header {
+  height: 30px;
+  width: 100%;
+  box-sizing: border-box;
+  background-color: #444;
+  line-height: 30px;
+  color: white;
+  padding-left: 10px;
+}
+
+.lines-body {
+  width: 100%;
+  background-color: #222;
+  min-height: 300px;
+  padding: 10px 0 20px 0;
+}
+
+.line, .command-line {
+  box-sizing: border-box;
+  width: 100%;
+  color: #f1f1f1;
+  background-color: #222;
+  outline: none;
+  border: none;
+  padding: 5px 10px;
+  font-size: 14px;
+}
+
+.line:hover {
+   background-color: #444;
+}
+
+.button::before {
+    -webkit-border-radius: 3px;
+    -moz-border-radius: 3px;
+    -webkit-box-shadow: #959595 0 2px 5px;
+    -moz-box-shadow: #959595 0 2px 5px;
+    border-radius: 3px;
+    box-shadow: #959595 0 2px 5px;
+    content: "";
+    display: block;
+    left: 0;
+    padding: 2px 0 0;
+    position: absolute;
+    top: 0;
+}
+
+.button:active::before { padding: 1px 0 0; }
+
+.button.black {
+    background: #656565;
+    background: -webkit-gradient(linear, 0 0, 0 bottom, from(#656565), to(#444));
+    background: -moz-linear-gradient(#656565, #444);
+    background: linear-gradient(#656565, #444);
+    border: solid 1px #535353;
+    border-bottom: solid 3px #414141;
+    box-shadow: inset 0 0 0 1px #939393;
+    color: #fff;
+    text-shadow: 0 1px 0 #2f2f2f;
+    padding: 8px 16px;
+    outline: none;
+}
+
+.button.black:hover {
+    background: #4c4c4c;
+    background: -webkit-gradient(linear, 0 0, 0 bottom, from(#4c4c4c), to(#565656));
+    background: -moz-linear-gradient(#4c4c4c, #565656);
+    background: linear-gradient(#4c4c4c, #565656);
+    border: solid 1px #464646;
+    border-bottom: solid 3px #414141;
+    box-shadow: inset 0 0 0 1px #818181;
+}
+
+.button.black:active {
+    background: #474747;
+    background: -webkit-gradient(linear, 0 0, 0 bottom, from(#474747), to(#444));
+    background: -moz-linear-gradient(#474747, #444);
+    background: linear-gradient(#474747, #444);
+    border: solid 1px #2f2f2f;
+    box-shadow: inset 0 10px 15px 0 #3e3e3e;
+}
diff --git a/docs/html_extra/examples/webusb-serial/application.js b/docs/html_extra/examples/webusb-serial/application.js
new file mode 100644
index 000000000..283121e32
--- /dev/null
+++ b/docs/html_extra/examples/webusb-serial/application.js
@@ -0,0 +1,90 @@
+(function() {
+  'use strict';
+
+  document.addEventListener('DOMContentLoaded', event => {
+    let connectButton = document.querySelector("#connect");
+    let statusDisplay = document.querySelector('#status');
+    let port;
+
+    function addLine(linesId, text) {
+      var senderLine = document.createElement("div");
+      senderLine.className = 'line';
+      var textnode = document.createTextNode(text);
+      senderLine.appendChild(textnode);
+      document.getElementById(linesId).appendChild(senderLine);
+      return senderLine;
+    }
+
+    let currentReceiverLine;
+
+    function appendLine(linesId, text) {
+      if (currentReceiverLine) {
+        currentReceiverLine.innerHTML =  currentReceiverLine.innerHTML + text;
+      } else {
+        currentReceiverLine = addLine(linesId, text);
+      }
+    }
+
+    function connect() {
+      port.connect().then(() => {
+        statusDisplay.textContent = '';
+        connectButton.textContent = 'Disconnect';
+
+        port.onReceive = data => {
+          let textDecoder = new TextDecoder();
+          console.log(textDecoder.decode(data));
+          if (data.getInt8() === 13) {
+            currentReceiverLine = null;
+          } else {
+            appendLine('receiver_lines', textDecoder.decode(data));
+          }
+        };
+        port.onReceiveError = error => {
+          console.error(error);
+        };
+      }, error => {
+        statusDisplay.textContent = error;
+      });
+    }
+
+    connectButton.addEventListener('click', function() {
+      if (port) {
+        port.disconnect();
+        connectButton.textContent = 'Connect';
+        statusDisplay.textContent = '';
+        port = null;
+      } else {
+        serial.requestPort().then(selectedPort => {
+          port = selectedPort;
+          connect();
+        }).catch(error => {
+          statusDisplay.textContent = error;
+        });
+      }
+    });
+
+    serial.getPorts().then(ports => {
+      if (ports.length === 0) {
+        statusDisplay.textContent = 'No device found.';
+      } else {
+        statusDisplay.textContent = 'Connecting...';
+        port = ports[0];
+        connect();
+      }
+    });
+
+
+    let commandLine = document.getElementById("command_line");
+
+    commandLine.addEventListener("keypress", function(event) {
+      if (event.keyCode === 13) {
+        if (commandLine.value.length > 0) {
+          addLine('sender_lines', commandLine.value);
+          commandLine.value = '';
+        }
+      }
+
+      port.send(new TextEncoder('utf-8').encode(String.fromCharCode(event.which || event.keyCode)));
+    });
+  });
+})();
diff --git a/docs/html_extra/examples/webusb-serial/index.html b/docs/html_extra/examples/webusb-serial/index.html
new file mode 100644
index 000000000..2f1432b0b
--- /dev/null
+++ b/docs/html_extra/examples/webusb-serial/index.html
@@ -0,0 +1,33 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>TinyUSB</title>
+    <script src="serial.js"></script>
+    <script src="application.js"></script>
+    <link rel="stylesheet" href="application.css">
+  </head>
+  <body>
+    <div class="main-content">
+      <h1>TinyUSB - WebUSB Serial Example</h1>
+      <div class="connect-container">
+        <button id="connect" class="button black">Connect</button>
+        <span id="status"></span>
+      </div>
+      <div class="container">
+        <div class="sender">
+          <div class="lines-header">Sender</div>
+          <div class="lines-body">
+            <div id="sender_lines" class="lines"></div>
+            <input id="command_line" class="command-line" placeholder="Start typing ...." />
+          </div>
+        </div>
+        <div class="receiver">
+          <div class="lines-header">Receiver</div>
+          <div class="lines-body">
+            <div id="receiver_lines" class="lines"></div>
+          </div>
+        </div>
+      </div>
+    </div>
+  </body>
+</html>
diff --git a/docs/html_extra/examples/webusb-serial/serial.js b/docs/html_extra/examples/webusb-serial/serial.js
new file mode 100644
index 000000000..8e985d897
--- /dev/null
+++ b/docs/html_extra/examples/webusb-serial/serial.js
@@ -0,0 +1,89 @@
+var serial = {};
+
+(function() {
+  'use strict';
+
+  serial.getPorts = function() {
+    return navigator.usb.getDevices().then(devices => {
+      return devices.map(device => new serial.Port(device));
+    });
+  };
+
+  serial.requestPort = function() {
+    const filters = [
+      { 'vendorId': 0x239A }, // Adafruit boards
+      { 'vendorId': 0xcafe }, // TinyUSB example
+    ];
+    return navigator.usb.requestDevice({ 'filters': filters }).then(
+      device => new serial.Port(device)
+    );
+  }
+
+  serial.Port = function(device) {
+    this.device_ = device;
+    this.interfaceNumber = 0;
+    this.endpointIn = 0;
+    this.endpointOut = 0;
+  };
+
+  serial.Port.prototype.connect = function() {
+    let readLoop = () => {
+      this.device_.transferIn(this.endpointIn, 64).then(result => {
+        this.onReceive(result.data);
+        readLoop();
+      }, error => {
+        this.onReceiveError(error);
+      });
+    };
+
+    return this.device_.open()
+        .then(() => {
+          if (this.device_.configuration === null) {
+            return this.device_.selectConfiguration(1);
+          }
+        })
+        .then(() => {
+          var interfaces = this.device_.configuration.interfaces;
+          interfaces.forEach(element => {
+            element.alternates.forEach(elementalt => {
+              if (elementalt.interfaceClass==0xFF) {
+                this.interfaceNumber = element.interfaceNumber;
+                elementalt.endpoints.forEach(elementendpoint => {
+                  if (elementendpoint.direction == "out") {
+                    this.endpointOut = elementendpoint.endpointNumber;
+                  }
+                  if (elementendpoint.direction=="in") {
+                    this.endpointIn =elementendpoint.endpointNumber;
+                  }
+                })
+              }
+            })
+          })
+        })
+        .then(() => this.device_.claimInterface(this.interfaceNumber))
+        .then(() => this.device_.selectAlternateInterface(this.interfaceNumber, 0))
+        .then(() => this.device_.controlTransferOut({
+            'requestType': 'class',
+            'recipient': 'interface',
+            'request': 0x22,
+            'value': 0x01,
+            'index': this.interfaceNumber}))
+        .then(() => {
+          readLoop();
+        });
+  };
+
+  serial.Port.prototype.disconnect = function() {
+    return this.device_.controlTransferOut({
+            'requestType': 'class',
+            'recipient': 'interface',
+            'request': 0x22,
+            'value': 0x00,
+            'index': this.interfaceNumber})
+        .then(() => this.device_.close());
+  };
+
+  serial.Port.prototype.send = function(data) {
+    return this.device_.transferOut(this.endpointOut, data);
+  };
+})();

From a698dda67ef9980a0b8eaf0ab9d3edc9adf1c2f4 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Thu, 5 Aug 2021 09:56:24 +0200
Subject: [PATCH 0303/2085] Minor fix.

---
 src/portable/microchip/samx7x/dcd_samx7x.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 419265723..0d9e184f6 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -77,9 +77,9 @@ static tusb_speed_t get_speed(void);
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
 
 // DMA descriptors shouldn't be placed in ITCM !
-CFG_TUSB_MEM_SECTION dma_desc_t dma_desc[6];
+CFG_TUSB_MEM_SECTION static dma_desc_t dma_desc[6];
 
-xfer_ctl_t xfer_status[EP_MAX];
+static xfer_ctl_t xfer_status[EP_MAX];
 
 static const tusb_desc_endpoint_t ep0_desc =
 {
@@ -148,7 +148,7 @@ void dcd_connect(uint8_t rhport)
   dcd_int_disable(rhport);
   // Enable the USB controller in device mode
   USB_REG->CTRL = CTRL_UIMOD | CTRL_USBE;
-  while (SR_CLKUSABLE != (USB_REG->SR & SR_CLKUSABLE));
+  while (!(USB_REG->SR & SR_CLKUSABLE));
 #if TUD_OPT_HIGH_SPEED
   USB_REG->DEVCTRL &= ~DEVCTRL_SPDCONF;
 #else
@@ -180,7 +180,7 @@ void dcd_disconnect(uint8_t rhport)
   USB_REG->DEVEPT &= ~(0x3FF << DEVEPT_EPEN0_Pos);
   // Unfreeze USB clock
   USB_REG->CTRL &= ~CTRL_FRZCLK;
-  while (SR_CLKUSABLE != (USB_REG->SR & SR_CLKUSABLE));
+  while (!(USB_REG->SR & SR_CLKUSABLE));
   // Clear all the pending interrupts
   USB_REG->DEVICR = DEVICR_Msk;
   // Disable all interrupts
@@ -193,7 +193,7 @@ void dcd_disconnect(uint8_t rhport)
 
 static tusb_speed_t get_speed(void)
 {
-  switch ((USB_REG->SR & SR_SPEED) >> SR_SPEED_Pos) {
+  switch (USB_REG->SR & SR_SPEED) {
   case SR_SPEED_FULL_SPEED:
   default:
     return TUSB_SPEED_FULL;
@@ -367,7 +367,7 @@ void dcd_int_handler(uint8_t rhport)
   {
     // Unfreeze USB clock
     USB_REG->CTRL &= ~CTRL_FRZCLK;
-    while(SR_CLKUSABLE != (USB_REG->SR & SR_CLKUSABLE));
+    while(!(USB_REG->SR & SR_CLKUSABLE));
     // Reset all endpoints
     for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++)
     {
@@ -386,7 +386,7 @@ void dcd_int_handler(uint8_t rhport)
   if (int_status & DEVISR_WAKEUP)
   {
     USB_REG->CTRL &= ~CTRL_FRZCLK;
-    while (SR_CLKUSABLE != (USB_REG->SR & SR_CLKUSABLE));
+    while (!(USB_REG->SR & SR_CLKUSABLE));
     USB_REG->DEVICR = DEVICR_WAKEUPC;
     USB_REG->DEVIDR = DEVIDR_WAKEUPEC;
     USB_REG->DEVIER = DEVIER_SUSPES;
@@ -398,7 +398,7 @@ void dcd_int_handler(uint8_t rhport)
   {
     // Unfreeze USB clock
     USB_REG->CTRL &= ~CTRL_FRZCLK;
-    while (SR_CLKUSABLE != (USB_REG->SR & SR_CLKUSABLE));
+    while (!(USB_REG->SR & SR_CLKUSABLE));
     USB_REG->DEVICR = DEVICR_SUSPC;
     USB_REG->DEVIDR = DEVIDR_SUSPEC;
     USB_REG->DEVIER = DEVIER_WAKEUPES;

From 188bc0e991df95390d2965febf9a7cf483e6ab21 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 5 Aug 2021 18:00:41 +0700
Subject: [PATCH 0304/2085] change webusb-serial landing page

- to example.tinyusb.org/webusb-serial/
- remove landing page from doc
---
 docs/conf.py                                  |   3 -
 .../examples/webusb-serial/application.css    | 107 ------------------
 .../examples/webusb-serial/application.js     |  90 ---------------
 .../examples/webusb-serial/index.html         |  33 ------
 .../examples/webusb-serial/serial.js          |  89 ---------------
 examples/device/webusb_serial/src/main.c      |   2 +-
 6 files changed, 1 insertion(+), 323 deletions(-)
 delete mode 100644 docs/html_extra/examples/webusb-serial/application.css
 delete mode 100644 docs/html_extra/examples/webusb-serial/application.js
 delete mode 100644 docs/html_extra/examples/webusb-serial/index.html
 delete mode 100644 docs/html_extra/examples/webusb-serial/serial.js

diff --git a/docs/conf.py b/docs/conf.py
index 1d05d7cb6..c7a17478f 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -39,7 +39,4 @@ html_theme_options = {
     'sidebar_hide_name': True,
 }
 
-# examples for webusb
-html_extra_path = ['html_extra']
-
 todo_include_todos = True
diff --git a/docs/html_extra/examples/webusb-serial/application.css b/docs/html_extra/examples/webusb-serial/application.css
deleted file mode 100644
index 4ae0138bd..000000000
--- a/docs/html_extra/examples/webusb-serial/application.css
+++ /dev/null
@@ -1,107 +0,0 @@
-.main-content {
-  width: 1440px;
-  margin: auto;
-  font-size: 14px;
-}
-
-.connect-container {
-  margin: 20px 0;
-}
-
-.container {
-  display: flex;
-}
-
-.sender, .receiver {
-  flex: 1;
-}
-
-.sender {
-  margin-right: 8px;
-}
-
-.receiver {
-  margin-left: 8px;
-}
-
-.lines-header {
-  height: 30px;
-  width: 100%;
-  box-sizing: border-box;
-  background-color: #444;
-  line-height: 30px;
-  color: white;
-  padding-left: 10px;
-}
-
-.lines-body {
-  width: 100%;
-  background-color: #222;
-  min-height: 300px;
-  padding: 10px 0 20px 0;
-}
-
-.line, .command-line {
-  box-sizing: border-box;
-  width: 100%;
-  color: #f1f1f1;
-  background-color: #222;
-  outline: none;
-  border: none;
-  padding: 5px 10px;
-  font-size: 14px;
-}
-
-.line:hover {
-   background-color: #444;
-}
-
-.button::before {
-    -webkit-border-radius: 3px;
-    -moz-border-radius: 3px;
-    -webkit-box-shadow: #959595 0 2px 5px;
-    -moz-box-shadow: #959595 0 2px 5px;
-    border-radius: 3px;
-    box-shadow: #959595 0 2px 5px;
-    content: "";
-    display: block;
-    left: 0;
-    padding: 2px 0 0;
-    position: absolute;
-    top: 0;
-}
-
-.button:active::before { padding: 1px 0 0; }
-
-.button.black {
-    background: #656565;
-    background: -webkit-gradient(linear, 0 0, 0 bottom, from(#656565), to(#444));
-    background: -moz-linear-gradient(#656565, #444);
-    background: linear-gradient(#656565, #444);
-    border: solid 1px #535353;
-    border-bottom: solid 3px #414141;
-    box-shadow: inset 0 0 0 1px #939393;
-    color: #fff;
-    text-shadow: 0 1px 0 #2f2f2f;
-    padding: 8px 16px;
-    outline: none;
-}
-
-.button.black:hover {
-    background: #4c4c4c;
-    background: -webkit-gradient(linear, 0 0, 0 bottom, from(#4c4c4c), to(#565656));
-    background: -moz-linear-gradient(#4c4c4c, #565656);
-    background: linear-gradient(#4c4c4c, #565656);
-    border: solid 1px #464646;
-    border-bottom: solid 3px #414141;
-    box-shadow: inset 0 0 0 1px #818181;
-}
-
-.button.black:active {
-    background: #474747;
-    background: -webkit-gradient(linear, 0 0, 0 bottom, from(#474747), to(#444));
-    background: -moz-linear-gradient(#474747, #444);
-    background: linear-gradient(#474747, #444);
-    border: solid 1px #2f2f2f;
-    box-shadow: inset 0 10px 15px 0 #3e3e3e;
-}
diff --git a/docs/html_extra/examples/webusb-serial/application.js b/docs/html_extra/examples/webusb-serial/application.js
deleted file mode 100644
index 283121e32..000000000
--- a/docs/html_extra/examples/webusb-serial/application.js
+++ /dev/null
@@ -1,90 +0,0 @@
-(function() {
-  'use strict';
-
-  document.addEventListener('DOMContentLoaded', event => {
-    let connectButton = document.querySelector("#connect");
-    let statusDisplay = document.querySelector('#status');
-    let port;
-
-    function addLine(linesId, text) {
-      var senderLine = document.createElement("div");
-      senderLine.className = 'line';
-      var textnode = document.createTextNode(text);
-      senderLine.appendChild(textnode);
-      document.getElementById(linesId).appendChild(senderLine);
-      return senderLine;
-    }
-
-    let currentReceiverLine;
-
-    function appendLine(linesId, text) {
-      if (currentReceiverLine) {
-        currentReceiverLine.innerHTML =  currentReceiverLine.innerHTML + text;
-      } else {
-        currentReceiverLine = addLine(linesId, text);
-      }
-    }
-
-    function connect() {
-      port.connect().then(() => {
-        statusDisplay.textContent = '';
-        connectButton.textContent = 'Disconnect';
-
-        port.onReceive = data => {
-          let textDecoder = new TextDecoder();
-          console.log(textDecoder.decode(data));
-          if (data.getInt8() === 13) {
-            currentReceiverLine = null;
-          } else {
-            appendLine('receiver_lines', textDecoder.decode(data));
-          }
-        };
-        port.onReceiveError = error => {
-          console.error(error);
-        };
-      }, error => {
-        statusDisplay.textContent = error;
-      });
-    }
-
-    connectButton.addEventListener('click', function() {
-      if (port) {
-        port.disconnect();
-        connectButton.textContent = 'Connect';
-        statusDisplay.textContent = '';
-        port = null;
-      } else {
-        serial.requestPort().then(selectedPort => {
-          port = selectedPort;
-          connect();
-        }).catch(error => {
-          statusDisplay.textContent = error;
-        });
-      }
-    });
-
-    serial.getPorts().then(ports => {
-      if (ports.length === 0) {
-        statusDisplay.textContent = 'No device found.';
-      } else {
-        statusDisplay.textContent = 'Connecting...';
-        port = ports[0];
-        connect();
-      }
-    });
-
-
-    let commandLine = document.getElementById("command_line");
-
-    commandLine.addEventListener("keypress", function(event) {
-      if (event.keyCode === 13) {
-        if (commandLine.value.length > 0) {
-          addLine('sender_lines', commandLine.value);
-          commandLine.value = '';
-        }
-      }
-
-      port.send(new TextEncoder('utf-8').encode(String.fromCharCode(event.which || event.keyCode)));
-    });
-  });
-})();
diff --git a/docs/html_extra/examples/webusb-serial/index.html b/docs/html_extra/examples/webusb-serial/index.html
deleted file mode 100644
index 2f1432b0b..000000000
--- a/docs/html_extra/examples/webusb-serial/index.html
+++ /dev/null
@@ -1,33 +0,0 @@
-<!DOCTYPE html>
-<html>
-  <head>
-    <title>TinyUSB</title>
-    <script src="serial.js"></script>
-    <script src="application.js"></script>
-    <link rel="stylesheet" href="application.css">
-  </head>
-  <body>
-    <div class="main-content">
-      <h1>TinyUSB - WebUSB Serial Example</h1>
-      <div class="connect-container">
-        <button id="connect" class="button black">Connect</button>
-        <span id="status"></span>
-      </div>
-      <div class="container">
-        <div class="sender">
-          <div class="lines-header">Sender</div>
-          <div class="lines-body">
-            <div id="sender_lines" class="lines"></div>
-            <input id="command_line" class="command-line" placeholder="Start typing ...." />
-          </div>
-        </div>
-        <div class="receiver">
-          <div class="lines-header">Receiver</div>
-          <div class="lines-body">
-            <div id="receiver_lines" class="lines"></div>
-          </div>
-        </div>
-      </div>
-    </div>
-  </body>
-</html>
diff --git a/docs/html_extra/examples/webusb-serial/serial.js b/docs/html_extra/examples/webusb-serial/serial.js
deleted file mode 100644
index 8e985d897..000000000
--- a/docs/html_extra/examples/webusb-serial/serial.js
+++ /dev/null
@@ -1,89 +0,0 @@
-var serial = {};
-
-(function() {
-  'use strict';
-
-  serial.getPorts = function() {
-    return navigator.usb.getDevices().then(devices => {
-      return devices.map(device => new serial.Port(device));
-    });
-  };
-
-  serial.requestPort = function() {
-    const filters = [
-      { 'vendorId': 0x239A }, // Adafruit boards
-      { 'vendorId': 0xcafe }, // TinyUSB example
-    ];
-    return navigator.usb.requestDevice({ 'filters': filters }).then(
-      device => new serial.Port(device)
-    );
-  }
-
-  serial.Port = function(device) {
-    this.device_ = device;
-    this.interfaceNumber = 0;
-    this.endpointIn = 0;
-    this.endpointOut = 0;
-  };
-
-  serial.Port.prototype.connect = function() {
-    let readLoop = () => {
-      this.device_.transferIn(this.endpointIn, 64).then(result => {
-        this.onReceive(result.data);
-        readLoop();
-      }, error => {
-        this.onReceiveError(error);
-      });
-    };
-
-    return this.device_.open()
-        .then(() => {
-          if (this.device_.configuration === null) {
-            return this.device_.selectConfiguration(1);
-          }
-        })
-        .then(() => {
-          var interfaces = this.device_.configuration.interfaces;
-          interfaces.forEach(element => {
-            element.alternates.forEach(elementalt => {
-              if (elementalt.interfaceClass==0xFF) {
-                this.interfaceNumber = element.interfaceNumber;
-                elementalt.endpoints.forEach(elementendpoint => {
-                  if (elementendpoint.direction == "out") {
-                    this.endpointOut = elementendpoint.endpointNumber;
-                  }
-                  if (elementendpoint.direction=="in") {
-                    this.endpointIn =elementendpoint.endpointNumber;
-                  }
-                })
-              }
-            })
-          })
-        })
-        .then(() => this.device_.claimInterface(this.interfaceNumber))
-        .then(() => this.device_.selectAlternateInterface(this.interfaceNumber, 0))
-        .then(() => this.device_.controlTransferOut({
-            'requestType': 'class',
-            'recipient': 'interface',
-            'request': 0x22,
-            'value': 0x01,
-            'index': this.interfaceNumber}))
-        .then(() => {
-          readLoop();
-        });
-  };
-
-  serial.Port.prototype.disconnect = function() {
-    return this.device_.controlTransferOut({
-            'requestType': 'class',
-            'recipient': 'interface',
-            'request': 0x22,
-            'value': 0x00,
-            'index': this.interfaceNumber})
-        .then(() => this.device_.close());
-  };
-
-  serial.Port.prototype.send = function(data) {
-    return this.device_.transferOut(this.endpointOut, data);
-  };
-})();
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index c85b3cc9a..aba4aedff 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -71,7 +71,7 @@ enum  {
 
 static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
-#define URL  "www.tinyusb.org/examples/webusb-serial"
+#define URL  "example.tinyusb.org/webusb-serial/"
 
 const tusb_desc_webusb_url_t desc_url =
 {

From 6be2d46b53cba37ad9cbfb1737a446bc76ec7fd4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 5 Aug 2021 18:32:44 +0700
Subject: [PATCH 0305/2085] update link to docs.tinyusb.org

---
 README.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.rst b/README.rst
index 8a92c267f..2119c26d2 100644
--- a/README.rst
+++ b/README.rst
@@ -8,7 +8,7 @@ embedded system, designed to be memory-safe with no dynamic allocation
 and thread-safe with all interrupt events are deferred then handled in
 the non-ISR task function.
 
-Please take a look at the online `documentation <https://www.tinyusb.org/>`__.
+Please take a look at the online `documentation <https://docs.tinyusb.org/>`__.
 
 .. figure:: docs/assets/stack.svg
    :width: 500px
@@ -122,7 +122,7 @@ in your project.
 .. |Build Status| image:: https://github.com/hathach/tinyusb/workflows/Build/badge.svg
    :target: https://github.com/hathach/tinyusb/actions
 .. |Documentation Status| image:: https://readthedocs.org/projects/tinyusb/badge/?version=latest
-   :target: https://tinyusb.readthedocs.io/en/latest/?badge=latest
+   :target: https://docs.tinyusb.org/en/latest/?badge=latest
 .. |License| image:: https://img.shields.io/badge/license-MIT-brightgreen.svg
    :target: https://opensource.org/licenses/MIT
 

From c6d495d6436c797b4efd029bd16ee8f19ff0a9f0 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 08:54:32 +0200
Subject: [PATCH 0306/2085] Remove dependencies to external libraries for the
 dcd driver

The core of tinyusb must be as independent as possible, we previously
relied on nuclei-sdk or the GD32VF103 firmware library for the synopsys
driver to work with the GD32VF103. Fortunatly we needed very few parts
from them so we implement them here.
---
 src/portable/st/synopsys/dcd_synopsys.c | 26 ++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 4b39844a1..7545ef6f7 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -94,16 +94,28 @@
 #define EP_FIFO_SIZE_FS 1280
 
 #elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
-#define STM32F1_SYNOPSYS
-#include "gd32vf103.h"
-#include "nmsis_core.h"
-#include "core_feature_eclic.h"
 #include "synopsys_common.h"
+
+// These numbers are the same for the whole GD32VF103 family.
+#define OTG_FS_IRQn     86
 #define EP_MAX_FS       4
 #define EP_FIFO_SIZE_FS 1280
-#define OTG_FS_IRQn USBFS_IRQn
-#define NVIC_EnableIRQ ECLIC_EnableIRQ
-#define NVIC_DisableIRQ ECLIC_DisableIRQ
+
+// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
+// Interrupt Controller by Nuclei. It is nearly API compatible to the
+// NVIC used by ARM MCUs.
+#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL
+
+#define NVIC_EnableIRQ __eclic_enable_interrupt
+#define NVIC_DisableIRQ __eclic_disable_interrupt
+
+static inline void __eclic_enable_interrupt (uint32_t irq) {
+  *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1;
+}
+
+static inline void __eclic_disable_interrupt (uint32_t irq){
+  *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
+}
 
 #else
 #error "Unsupported MCUs"

From 768282982039001128cecfe125d88f58ce640713 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 09:01:01 +0200
Subject: [PATCH 0307/2085] Add correct endpoint count for GD32VF103

This controller family only supports USB FS with four endpoints
---
 src/device/dcd_attr.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 18f369332..7772a6d96 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -147,6 +147,10 @@
 //#elif TU_CHECK_MCU(MM32F327X)
 //  #define DCD_ATTR_ENDPOINT_MAX not known yet
 
+//------------- GigaDevice -------------//
+#elif TU_CHECK_MCU(GD32VF103)
+  #define DCD_ATTR_ENDPOINT_MAX   4
+
 #else
   #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define DCD_ATTR_ENDPOINT_MAX   8

From b473923f42427bc314519a84e64bb3c3477e8de1 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 09:51:16 +0200
Subject: [PATCH 0308/2085] Remove redundant linker files

We use the linker files provided by nuclei-sdk instead
---
 .../gcc_gd32vf103x8_flashxip.ld               | 284 ------------------
 .../gcc_gd32vf103xb_flashxip.ld               | 284 ------------------
 2 files changed, 568 deletions(-)
 delete mode 100644 hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103x8_flashxip.ld
 delete mode 100644 hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103xb_flashxip.ld

diff --git a/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103x8_flashxip.ld b/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103x8_flashxip.ld
deleted file mode 100644
index 10f3747e0..000000000
--- a/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103x8_flashxip.ld
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright (c) 2019 - 2020 Nuclei Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-/******************************************************************************
- * @file     gcc_gd32vf103x8_flashxip.ld
- * @brief    GNU Linker Script for gd32vf103x8 based device
- * @version  V1.0.0
- * @date     1. Dec 2020
- ******************************************************************************/
-
-/*********** Use Configuration Wizard in Context Menu *************************/
-
-OUTPUT_ARCH( "riscv" )
-/********************* Flash Configuration ************************************
- * <h> Flash Configuration
- * <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
- * <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
- * </h>
- */
-__ROM_BASE = 0x08000000;
-__ROM_SIZE = 0x00010000;
-
-/*--------------------- ILM RAM Configuration ---------------------------
- * <h> ILM RAM Configuration
- * <o0> ILM RAM Base Address    <0x0-0xFFFFFFFF:8>
- * <o1> ILM RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
- * </h>
- */
-__ILM_RAM_BASE = 0x80000000;
-__ILM_RAM_SIZE = 0x00010000;
-
-/*--------------------- Embedded RAM Configuration ---------------------------
- * <h> RAM Configuration
- * <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
- * <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
- * </h>
-*/
-__RAM_BASE = 0x20000000;
-__RAM_SIZE = 0x00005000;
-
-/********************* Stack / Heap Configuration ****************************
- * <h> Stack / Heap Configuration
- * <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
- * <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
- * </h>
- */
-__STACK_SIZE = 0x00000800;
-__HEAP_SIZE  = 0x00000800;
-
-/**************************** end of configuration section ********************/
-
-/* Define base address and length of flash and ram */
-MEMORY
-{
-  flash (rxai!w) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
-  ram (wxa!ri) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
-}
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH,ILM and RAM.
- * It references following symbols, which must be defined in code:
- *   _Start : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   _ilm_lma
- *   _ilm
- *   __etext
- *   _etext
- *   etext
- *   _eilm
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   _data_lma
- *   _edata
- *   edata
- *   __data_end__
- *   __bss_start
- *   __fbss
- *   _end
- *   end
- *   __heap_end
- *   __StackLimit
- *   __StackTop
- *   __STACK_SIZE
- */
-/* Define entry label of program */
-ENTRY(_start)
-SECTIONS
-{
-  __STACK_SIZE = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2K;
-
-  .init           :
-  {
-    /* vector table locate at flash */
-    *(.vtable)
-    KEEP (*(SORT_NONE(.init)))
-  } >flash AT>flash
-
-  .ilalign         :
-  {
-    . = ALIGN(4);
-    /* Create a section label as _ilm_lma which located at flash */
-    PROVIDE( _ilm_lma = . );
-  } >flash AT>flash
-
-  .ialign         :
-  {
-    /* Create a section label as _ilm which located at flash */
-    PROVIDE( _ilm = . );
-  } >flash AT>flash
-
-  /* Code section located at flash */
-  .text           :
-  {
-    *(.text.unlikely .text.unlikely.*)
-    *(.text.startup .text.startup.*)
-    *(.text .text.*)
-    *(.gnu.linkonce.t.*)
-  } >flash AT>flash
-
-  .rodata : ALIGN(4)
-  {
-    . = ALIGN(4);
-    *(.rdata)
-    *(.rodata .rodata.*)
-    /* section information for initial. */
-    . = ALIGN(4);
-    __rt_init_start = .;
-    KEEP(*(SORT(.rti_fn*)))
-    __rt_init_end = .;
-    /* section information for finsh shell */
-    . = ALIGN(4);
-    __fsymtab_start = .;
-    KEEP(*(FSymTab))
-    __fsymtab_end = .;
-    . = ALIGN(4);
-    __vsymtab_start = .;
-    KEEP(*(VSymTab))
-    __vsymtab_end = .;
-    *(.gnu.linkonce.r.*)
-    . = ALIGN(8);
-    *(.srodata.cst16)
-    *(.srodata.cst8)
-    *(.srodata.cst4)
-    *(.srodata.cst2)
-    *(.srodata .srodata.*)
-  } >flash AT>flash
-
-  .fini           :
-  {
-    KEEP (*(SORT_NONE(.fini)))
-  } >flash AT>flash
-
-  . = ALIGN(4);
-
-  PROVIDE (__etext = .);
-  PROVIDE (_etext = .);
-  PROVIDE (etext = .);
-  PROVIDE( _eilm = . );
-
-
-  .preinit_array  :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >flash AT>flash
-
-  .init_array     :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
-    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >flash AT>flash
-
-  .fini_array     :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
-    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >flash AT>flash
-
-  .ctors          :
-  {
-    /* gcc uses crtbegin.o to find the start of
-     * the constructors, so we make sure it is
-     * first.  Because this is a wildcard, it
-     * doesn't matter if the user does not
-     * actually link against crtbegin.o; the
-     * linker won't look for a file to match a
-     * wildcard.  The wildcard also means that it
-     * doesn't matter which directory crtbegin.o
-     * is in.
-     */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*crtbegin?.o(.ctors))
-    /* We don't want to include the .ctor section from
-     * the crtend.o file until after the sorted ctors.
-     * The .ctor section from the crtend file contains the
-     * end of ctors marker and it must be last
-     */
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-  } >flash AT>flash
-
-  .dtors          :
-  {
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*crtbegin?.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-  } >flash AT>flash
-
-  .lalign         :
-  {
-    . = ALIGN(4);
-    PROVIDE( _data_lma = . );
-  } >flash AT>flash
-
-  .dalign         :
-  {
-    . = ALIGN(4);
-    PROVIDE( _data = . );
-  } >ram AT>flash
-
-  /* Define data section virtual address is ram and physical address is flash */
-  .data          :
-  {
-    *(.data .data.*)
-    *(.gnu.linkonce.d.*)
-    . = ALIGN(8);
-    PROVIDE( __global_pointer$ = . + 0x800 );
-    *(.sdata .sdata.* .sdata*)
-    *(.gnu.linkonce.s.*)
-  } >ram AT>flash
-
-  . = ALIGN(4);
-  PROVIDE( _edata = . );
-  PROVIDE( edata = . );
-
-  PROVIDE( _fbss = . );
-  PROVIDE( __bss_start = . );
-  .bss            :
-  {
-    *(.sbss*)
-    *(.gnu.linkonce.sb.*)
-    *(.bss .bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN(4);
-  } >ram AT>ram
-
-  . = ALIGN(8);
-  PROVIDE( _end = . );
-  PROVIDE( end = . );
-  /* Define stack and head location at ram */
-  .stack ORIGIN(ram) + LENGTH(ram) - __STACK_SIZE :
-  {
-    PROVIDE( _heap_end = . );
-    . = __STACK_SIZE;
-    PROVIDE( _sp = . );
-  } >ram AT>ram
-}
diff --git a/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103xb_flashxip.ld b/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103xb_flashxip.ld
deleted file mode 100644
index 14d317f14..000000000
--- a/hw/bsp/gd32vf103_longan_nano/gcc_gd32vf103xb_flashxip.ld
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright (c) 2019 - 2020 Nuclei Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-/******************************************************************************
- * @file     gcc_gd32vf103xb_flashxip.ld
- * @brief    GNU Linker Script for gd32vf103xb based device
- * @version  V1.0.0
- * @date     1. Dec 2020
- ******************************************************************************/
-
-/*********** Use Configuration Wizard in Context Menu *************************/
-
-OUTPUT_ARCH( "riscv" )
-/********************* Flash Configuration ************************************
- * <h> Flash Configuration
- * <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
- * <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
- * </h>
- */
-__ROM_BASE = 0x08000000;
-__ROM_SIZE = 0x00020000;
-
-/*--------------------- ILM RAM Configuration ---------------------------
- * <h> ILM RAM Configuration
- * <o0> ILM RAM Base Address    <0x0-0xFFFFFFFF:8>
- * <o1> ILM RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
- * </h>
- */
-__ILM_RAM_BASE = 0x80000000;
-__ILM_RAM_SIZE = 0x00010000;
-
-/*--------------------- Embedded RAM Configuration ---------------------------
- * <h> RAM Configuration
- * <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>
- * <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
- * </h>
-*/
-__RAM_BASE = 0x20000000;
-__RAM_SIZE = 0x00008000;
-
-/********************* Stack / Heap Configuration ****************************
- * <h> Stack / Heap Configuration
- * <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
- * <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
- * </h>
- */
-__STACK_SIZE = 0x00000800;
-__HEAP_SIZE  = 0x00000800;
-
-/**************************** end of configuration section ********************/
-
-/* Define base address and length of flash and ram */
-MEMORY
-{
-  flash (rxai!w) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE
-  ram (wxa!ri) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
-}
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH,ILM and RAM.
- * It references following symbols, which must be defined in code:
- *   _Start : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   _ilm_lma
- *   _ilm
- *   __etext
- *   _etext
- *   etext
- *   _eilm
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   _data_lma
- *   _edata
- *   edata
- *   __data_end__
- *   __bss_start
- *   __fbss
- *   _end
- *   end
- *   __heap_end
- *   __StackLimit
- *   __StackTop
- *   __STACK_SIZE
- */
-/* Define entry label of program */
-ENTRY(_start)
-SECTIONS
-{
-  __STACK_SIZE = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2K;
-
-  .init           :
-  {
-    /* vector table locate at flash */
-    *(.vtable)
-    KEEP (*(SORT_NONE(.init)))
-  } >flash AT>flash
-
-  .ilalign         :
-  {
-    . = ALIGN(4);
-    /* Create a section label as _ilm_lma which located at flash */
-    PROVIDE( _ilm_lma = . );
-  } >flash AT>flash
-
-  .ialign         :
-  {
-    /* Create a section label as _ilm which located at flash */
-    PROVIDE( _ilm = . );
-  } >flash AT>flash
-
-  /* Code section located at flash */
-  .text           :
-  {
-    *(.text.unlikely .text.unlikely.*)
-    *(.text.startup .text.startup.*)
-    *(.text .text.*)
-    *(.gnu.linkonce.t.*)
-  } >flash AT>flash
-
-  .rodata : ALIGN(4)
-  {
-    . = ALIGN(4);
-    *(.rdata)
-    *(.rodata .rodata.*)
-    /* section information for initial. */
-    . = ALIGN(4);
-    __rt_init_start = .;
-    KEEP(*(SORT(.rti_fn*)))
-    __rt_init_end = .;
-    /* section information for finsh shell */
-    . = ALIGN(4);
-    __fsymtab_start = .;
-    KEEP(*(FSymTab))
-    __fsymtab_end = .;
-    . = ALIGN(4);
-    __vsymtab_start = .;
-    KEEP(*(VSymTab))
-    __vsymtab_end = .;
-    *(.gnu.linkonce.r.*)
-    . = ALIGN(8);
-    *(.srodata.cst16)
-    *(.srodata.cst8)
-    *(.srodata.cst4)
-    *(.srodata.cst2)
-    *(.srodata .srodata.*)
-  } >flash AT>flash
-
-  .fini           :
-  {
-    KEEP (*(SORT_NONE(.fini)))
-  } >flash AT>flash
-
-  . = ALIGN(4);
-
-  PROVIDE (__etext = .);
-  PROVIDE (_etext = .);
-  PROVIDE (etext = .);
-  PROVIDE( _eilm = . );
-
-
-  .preinit_array  :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >flash AT>flash
-
-  .init_array     :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
-    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >flash AT>flash
-
-  .fini_array     :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
-    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >flash AT>flash
-
-  .ctors          :
-  {
-    /* gcc uses crtbegin.o to find the start of
-     * the constructors, so we make sure it is
-     * first.  Because this is a wildcard, it
-     * doesn't matter if the user does not
-     * actually link against crtbegin.o; the
-     * linker won't look for a file to match a
-     * wildcard.  The wildcard also means that it
-     * doesn't matter which directory crtbegin.o
-     * is in.
-     */
-    KEEP (*crtbegin.o(.ctors))
-    KEEP (*crtbegin?.o(.ctors))
-    /* We don't want to include the .ctor section from
-     * the crtend.o file until after the sorted ctors.
-     * The .ctor section from the crtend file contains the
-     * end of ctors marker and it must be last
-     */
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
-    KEEP (*(SORT(.ctors.*)))
-    KEEP (*(.ctors))
-  } >flash AT>flash
-
-  .dtors          :
-  {
-    KEEP (*crtbegin.o(.dtors))
-    KEEP (*crtbegin?.o(.dtors))
-    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
-    KEEP (*(SORT(.dtors.*)))
-    KEEP (*(.dtors))
-  } >flash AT>flash
-
-  .lalign         :
-  {
-    . = ALIGN(4);
-    PROVIDE( _data_lma = . );
-  } >flash AT>flash
-
-  .dalign         :
-  {
-    . = ALIGN(4);
-    PROVIDE( _data = . );
-  } >ram AT>flash
-
-  /* Define data section virtual address is ram and physical address is flash */
-  .data          :
-  {
-    *(.data .data.*)
-    *(.gnu.linkonce.d.*)
-    . = ALIGN(8);
-    PROVIDE( __global_pointer$ = . + 0x800 );
-    *(.sdata .sdata.* .sdata*)
-    *(.gnu.linkonce.s.*)
-  } >ram AT>flash
-
-  . = ALIGN(4);
-  PROVIDE( _edata = . );
-  PROVIDE( edata = . );
-
-  PROVIDE( _fbss = . );
-  PROVIDE( __bss_start = . );
-  .bss            :
-  {
-    *(.sbss*)
-    *(.gnu.linkonce.sb.*)
-    *(.bss .bss.*)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN(4);
-  } >ram AT>ram
-
-  . = ALIGN(8);
-  PROVIDE( _end = . );
-  PROVIDE( end = . );
-  /* Define stack and head location at ram */
-  .stack ORIGIN(ram) + LENGTH(ram) - __STACK_SIZE :
-  {
-    PROVIDE( _heap_end = . );
-    . = __STACK_SIZE;
-    PROVIDE( _sp = . );
-  } >ram AT>ram
-}

From 6e287a7c5e190d71cc73ddc2f6fa2745f13f4d6b Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 09:51:56 +0200
Subject: [PATCH 0309/2085] Cleanup include paths and use linker files from
 nuclei-sdk

---
 hw/bsp/gd32vf103_longan_nano/board.mk | 61 +++++++++++++++------------
 1 file changed, 35 insertions(+), 26 deletions(-)

diff --git a/hw/bsp/gd32vf103_longan_nano/board.mk b/hw/bsp/gd32vf103_longan_nano/board.mk
index 0c0c26427..5ab275dbe 100644
--- a/hw/bsp/gd32vf103_longan_nano/board.mk
+++ b/hw/bsp/gd32vf103_longan_nano/board.mk
@@ -1,51 +1,60 @@
 CROSS_COMPILE = riscv32-unknown-elf-
 
+# Submodules
 DEPS_SUBMODULES += hw/mcu/gd/nuclei-sdk
-
 NUCLEI_SDK = hw/mcu/gd/nuclei-sdk
-GD32VF103_SDK_SOC_COMMON = $(NUCLEI_SDK)/SoC/gd32vf103/Common
-GD32VF103_SDK_DRIVER = $(GD32VF103_SDK_SOC_COMMON)/Source/Drivers
+
+# Nuclei-SDK paths
+GD32VF103_SDK_SOC = $(NUCLEI_SDK)/SoC/gd32vf103
+GD32VF103_SDK_DRIVER = $(GD32VF103_SDK_SOC)/Common/Source/Drivers
+LONGAN_NANO_SDK_BSP = $(GD32VF103_SDK_SOC)/Board/gd32vf103c_longan_nano
+LINKER_SCRIPTS = $(LONGAN_NANO_SDK_BSP)/Source/GCC
+LIBC_STUBS = $(GD32VF103_SDK_SOC)/Common/Source/Stubs
+STARTUP_ASM = $(GD32VF103_SDK_SOC)/Common/Source/GCC
+
 SKIP_NANOLIB = 1
 
 CFLAGS += \
-  -march=rv32imac \
-  -mabi=ilp32 \
-  -mcmodel=medlow \
-  -mstrict-align \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_GD32VF103 \
-  -DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP \
-  -DGD32VF103 
+	-march=rv32imac \
+	-mabi=ilp32 \
+	-mcmodel=medlow \
+	-mstrict-align \
+	-nostdlib -nostartfiles \
+	-DCFG_TUSB_MCU=OPT_MCU_GD32VF103 \
+	-DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP \
+	-DGD32VF103 
 
 # mcu driver cause following warnings
-#CFLAGS += -Wno-error=unused-parameter
+CFLAGS += -Wno-error=unused-parameter
 
 # All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/gcc_gd32vf103xb_flashxip.ld # Longan Nano 128k ROM 32k RAM
-# LD_FILE = hw/bsp/$(BOARD)/gcc_gd32vf103x8_flashxip.ld # Longan Nano Lite 64k ROM 20k RAM 
+LD_FILE = $(LINKER_SCRIPTS)/gcc_gd32vf103xb_flashxip.ld # Longan Nano 128k ROM 32k RAM
+#LD_FILE = $(LINKER_SCRIPTS)/gcc_gd32vf103x8_flashxip.ld # Longan Nano Lite 64k ROM 20k RAM 
 
 SRC_C += \
-  src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/st/synopsys/dcd_synopsys.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
 	$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_usart.c \
-	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/sbrk.c \
-	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/close.c \
-	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/isatty.c \
-	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/fstat.c \
-	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/lseek.c \
-	$(GD32VF103_SDK_SOC_COMMON)/Source/Stubs/read.c 
+	$(LONGAN_NANO_SDK_BSP)/Source/gd32vf103c_longan_nano.c \
+	$(LIBC_STUBS)/sbrk.c \
+	$(LIBC_STUBS)/close.c \
+	$(LIBC_STUBS)/isatty.c \
+	$(LIBC_STUBS)/fstat.c \
+	$(LIBC_STUBS)/lseek.c \
+	$(LIBC_STUBS)/read.c 
 
 SRC_S += \
-  $(GD32VF103_SDK_SOC_COMMON)/Source/GCC/startup_gd32vf103.S \
-  $(GD32VF103_SDK_SOC_COMMON)/Source/GCC/intexc_gd32vf103.S
+	$(STARTUP_ASM)/startup_gd32vf103.S \
+	$(STARTUP_ASM)/intexc_gd32vf103.S
 
 INC += \
-  $(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/hw/bsp/$(BOARD) \
 	$(TOP)/$(NUCLEI_SDK)/NMSIS/Core/Include \
-	$(TOP)/$(GD32VF103_SDK_SOC_COMMON)/Include \
-	$(TOP)/$(GD32VF103_SDK_SOC_COMMON)/Include/Usb \
+	$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include \
+	$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include/Usb \
+	$(TOP)/$(LONGAN_NANO_SDK_BSP)/Include
 
 # For freeRTOS port source
 FREERTOS_PORT = RISC-V

From 733a36243662ba693e8dc78b65e7a031137c3687 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 10:08:42 +0200
Subject: [PATCH 0310/2085] Use nuclei-sdk functions for init code

Instead of using the HAL functions we can just use the defines from the
board support for the longan nano that comes with the nuclei-sdk. Also
we move some includes and defines to the header file.
---
 .../gd32vf103_longan_nano.c                   | 73 ++++---------------
 hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h | 30 +++-----
 2 files changed, 23 insertions(+), 80 deletions(-)

diff --git a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
index 6affd6fa5..d832503b1 100644
--- a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
+++ b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
@@ -37,38 +37,21 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); }
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#define HXTAL_VALUE \
-  ((uint32_t)8000000) /*!< value of the external oscillator in Hz */
 #define USB_NO_VBUS_PIN
 
-//--------------------------------------------------------------------+
-// LED
-//--------------------------------------------------------------------+
-
-#define LED_PORT GPIOC
-#define LED_PIN GPIO_PIN_13
-#define LED_STATE_ON 1
-
-#define BUTTON_PORT GPIOA
-#define BUTTON_PIN GPIO_PIN_0
+#define BUTTON_PORT         GPIOA
+#define BUTTON_PIN          GPIO_PIN_0
 #define BUTTON_STATE_ACTIVE 1
 
-//--------------------------------------------------------------------+
-// UART
-//--------------------------------------------------------------------+
+#define UART_DEV            SOC_DEBUG_UART
 
-#define UART_DEV USART0
-#define UART_GPIO_PORT GPIOA
-#define UART_TX_PIN GPIO_PIN_9
-#define UART_RX_PIN GPIO_PIN_10
+#define LED_PIN             LED_R
 
 void board_init(void) {
   /* Disable interrupts during init */
   __disable_irq();
 
-  /* Reset eclic configuration registers */
-  ECLIC->CFG = 0;
-  ECLIC->MTH = 0;
+  ECLIC_Init();
 
   /* Reset eclic interrupt registers */
   for (int32_t i = 0; i < SOC_INT_MAX; i++) {
@@ -103,37 +86,11 @@ void board_init(void) {
 #endif
 
 #ifdef LED_PIN
-  gpio_init(LED_PORT, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, LED_PIN);
-  board_led_write(0);
+  gd_led_init(LED_PIN);
 #endif
 
 #if defined(UART_DEV)
-  /* enable GPIO TX and RX clock */
-  rcu_periph_clock_enable(GD32_COM_TX_GPIO_CLK);
-  rcu_periph_clock_enable(GD32_COM_RX_GPIO_CLK);
-
-  /* enable USART clock */
-  rcu_periph_clock_enable(GD32_COM_CLK);
-
-  /* connect port to USARTx_Tx */
-  gpio_init(GD32_COM_TX_GPIO_PORT, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ,
-            GD32_COM_TX_PIN);
-
-  /* connect port to USARTx_Rx */
-  gpio_init(GD32_COM_RX_GPIO_PORT, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ,
-            GD32_COM_RX_PIN);
-
-  /* USART configure */
-  usart_deinit(UART_DEV);
-  usart_baudrate_set(UART_DEV, 115200U);
-  usart_word_length_set(UART_DEV, USART_WL_8BIT);
-  usart_stop_bit_set(UART_DEV, USART_STB_1BIT);
-  usart_parity_config(UART_DEV, USART_PM_NONE);
-  usart_hardware_flow_rts_config(UART_DEV, USART_RTS_DISABLE);
-  usart_hardware_flow_cts_config(UART_DEV, USART_CTS_DISABLE);
-  usart_receive_config(UART_DEV, USART_RECEIVE_ENABLE);
-  usart_transmit_config(UART_DEV, USART_TRANSMIT_ENABLE);
-  usart_enable(UART_DEV);
+  gd_com_init(UART_DEV);
 #endif
 
   /* USB D+ and D- pins don't need to be configured. */
@@ -153,7 +110,7 @@ void board_init(void) {
   rcu_periph_reset_disable(RCU_USBFSRST);
 
   /* Set IRQ priority and trigger */
-  ECLIC_SetLevelIRQ(USBFS_IRQn, 15);
+  ECLIC_SetLevelIRQ(USBFS_IRQn, 3);
   ECLIC_SetTrigIRQ(USBFS_IRQn, ECLIC_POSTIVE_EDGE_TRIGGER);
 
   /* Retrieve otg core registers */
@@ -172,14 +129,6 @@ void board_init(void) {
   __enable_irq();
 }
 
-#include "gd32vf103_dbg.h"
-
-#define DBG_KEY_UNLOCK 0x4B5A6978
-#define DBG_CMD_RESET 0x1
-
-#define DBG_KEY REG32(DBG + 0x0C)
-#define DBG_CMD REG32(DBG + 0x08)
-
 void gd32vf103_reset(void) {
   /* The MTIMER unit of the GD32VF103 doesn't have the MSFRST
    * register to generate a software reset request.
@@ -196,7 +145,11 @@ void gd32vf103_reset(void) {
 //--------------------------------------------------------------------+
 
 void board_led_write(bool state) {
-  gpio_bit_write(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+  if (state) {
+    gd_led_on(LED_PIN);
+  } else {
+    gd_led_off(LED_PIN);
+  }
 }
 
 uint32_t board_button_read(void) {
diff --git a/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h b/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
index f8245cc48..6ce158a31 100644
--- a/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
+++ b/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
@@ -1,29 +1,19 @@
-// See LICENSE for license details.
 #ifndef _NUCLEI_SDK_HAL_H
 #define _NUCLEI_SDK_HAL_H
 
-#include "nmsis_gcc.h"
-#include "gd32vf103.h"
-#include "gd32vf103_libopt.h"
+#include "gd32vf103c_longan_nano.h"
 #include "drv_usb_hw.h"
 #include "drv_usb_dev.h"
 
-#ifdef __cplusplus
-extern "C" {
-#endif
+// 4 bits for interrupt level, 0 for priority.
+// level 0 = lowest priority, level 15 = highest priority.
+#define __ECLIC_INTCTLBITS 4
 
-/* sipeed longan nano board UART com port */
-#define SOC_DEBUG_UART      USART0
-#define GD32_COM0 USART0
-#define GD32_COM_CLK RCU_USART0
-#define GD32_COM_TX_PIN GPIO_PIN_9
-#define GD32_COM_RX_PIN GPIO_PIN_10
-#define GD32_COM_TX_GPIO_PORT GPIOA
-#define GD32_COM_RX_GPIO_PORT GPIOA
-#define GD32_COM_TX_GPIO_CLK RCU_GPIOA
-#define GD32_COM_RX_GPIO_CLK RCU_GPIOA
+#define SOC_DEBUG_UART GD32_COM0
+
+#define DBG_KEY_UNLOCK 0x4B5A6978
+#define DBG_CMD_RESET  0x1
+#define DBG_KEY        REG32(DBG + 0x0C)
+#define DBG_CMD        REG32(DBG + 0x08)
 
-#ifdef __cplusplus
-}
-#endif
 #endif

From 1d2a57a9e17e0a2bd1f315a17a092363ef79bab2 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 11:03:16 +0200
Subject: [PATCH 0311/2085] Remove unsuitable clock configurations from init
 code

Only 48MHz, 72MHz, 96MHz and 120 MHz system clocks derived from an
external crystal are suitable for the usb peripheral, as the internal
oscillator is not stable enough. Also the usb-prescaler only supports
division by 1 (48MHZ), 1.5(72MHz), 2(96MHz) and 2.5(120Mhz).
120Mhz is also out of spec and not added here.
---
 hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h |  15 +-
 .../gd32vf103_longan_nano/system_gd32vf103.c  | 630 +-----------------
 2 files changed, 30 insertions(+), 615 deletions(-)

diff --git a/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h b/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
index 6ce158a31..9b2a616a8 100644
--- a/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
+++ b/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
@@ -7,13 +7,16 @@
 
 // 4 bits for interrupt level, 0 for priority.
 // level 0 = lowest priority, level 15 = highest priority.
-#define __ECLIC_INTCTLBITS 4
+#define __ECLIC_INTCTLBITS  4
 
-#define SOC_DEBUG_UART GD32_COM0
+#define __SYSTEM_CLOCK      72000000
+#define HXTAL_VALUE         ((uint32_t)8000000)
 
-#define DBG_KEY_UNLOCK 0x4B5A6978
-#define DBG_CMD_RESET  0x1
-#define DBG_KEY        REG32(DBG + 0x0C)
-#define DBG_CMD        REG32(DBG + 0x08)
+#define SOC_DEBUG_UART      GD32_COM0
+
+#define DBG_KEY_UNLOCK      0x4B5A6978
+#define DBG_CMD_RESET       0x1
+#define DBG_KEY             REG32(DBG + 0x0C)
+#define DBG_CMD             REG32(DBG + 0x08)
 
 #endif
diff --git a/hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c b/hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c
index 54c8804c4..8019974d6 100644
--- a/hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c
+++ b/hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c
@@ -33,74 +33,36 @@ OF SUCH DAMAGE.
 */
 
 /* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */
-
-#include "gd32vf103_libopt.h"
+#include "nuclei_sdk_hal.h"
 
 /* system frequency define */
 #define __IRC8M           (IRC8M_VALUE)            /* internal 8 MHz RC oscillator frequency */
 #define __HXTAL           (HXTAL_VALUE)            /* high speed crystal oscillator frequency */
 #define __SYS_OSC_CLK     (__IRC8M)                /* main oscillator frequency */
+#define __SYSTEM_CLOCK_HXTAL                    (HXTAL_VALUE)
 
-/* select a system clock by uncommenting the following line */
-/* use IRC8M */
-//#define __SYSTEM_CLOCK_48M_PLL_IRC8M            (uint32_t)(48000000)
-//#define __SYSTEM_CLOCK_72M_PLL_IRC8M            (uint32_t)(72000000)
-//#define __SYSTEM_CLOCK_108M_PLL_IRC8M           (uint32_t)(108000000)
+#if !defined(__SYSTEM_CLOCK)
+#define __SYSTEM_CLOCK 72000000
+#endif
 
-/********************************************************************/
-//#define __SYSTEM_CLOCK_HXTAL                    (HXTAL_VALUE)
-//#define __SYSTEM_CLOCK_24M_PLL_HXTAL            (uint32_t)(24000000)
-/********************************************************************/
+#if __SYSTEM_CLOCK == 48000000
+  #define __SYSTEM_CLOCK_48M_PLL_HXTAL            (uint32_t)(48000000)
+  uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL;
+  static void system_clock_48m_hxtal(void);
 
-//#define __SYSTEM_CLOCK_36M_PLL_HXTAL            (uint32_t)(36000000)
-//#define __SYSTEM_CLOCK_48M_PLL_HXTAL            (uint32_t)(48000000)
-//#define __SYSTEM_CLOCK_56M_PLL_HXTAL            (uint32_t)(56000000)
-//#define __SYSTEM_CLOCK_72M_PLL_HXTAL            (uint32_t)(72000000)
-#define __SYSTEM_CLOCK_96M_PLL_HXTAL            (uint32_t)(96000000)
-//#define __SYSTEM_CLOCK_108M_PLL_HXTAL           (uint32_t)(108000000)
+#elif __SYSTEM_CLOCK == 72000000
+  #define __SYSTEM_CLOCK_72M_PLL_HXTAL            (uint32_t)(72000000)
+  uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
+  static void system_clock_72m_hxtal(void);
 
-/*#define SEL_IRC8M       0x00U
-#define SEL_HXTAL       0x01U
-#define SEL_PLL         0x02U*/
+#elif __SYSTEM_CLOCK == 96000000
+  #define __SYSTEM_CLOCK_96M_PLL_HXTAL            (uint32_t)(96000000)
+  uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL;
+  static void system_clock_96m_hxtal(void);
 
-/* set the system clock frequency and declare the system clock configuration function */
-#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M;
-static void system_clock_48m_irc8m(void);
-#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M;
-static void system_clock_72m_irc8m(void);
-#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M;
-static void system_clock_108m_irc8m(void);
-
-#elif defined (__SYSTEM_CLOCK_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
-static void system_clock_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL;
-static void system_clock_24m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL;
-static void system_clock_36m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL;
-static void system_clock_48m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL;
-static void system_clock_56m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
-static void system_clock_72m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL;
-static void system_clock_96m_hxtal(void);
-#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
-uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL;
-static void system_clock_108m_hxtal(void);
 #else
-uint32_t SystemCoreClock = IRC8M_VALUE;
-#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */
+#error No valid system clock configuration set!
+#endif
 
 /* configure the system clock */
 static void system_clock_config(void);
@@ -113,29 +75,12 @@ static void system_clock_config(void);
 */
 static void system_clock_config(void)
 {
-#ifdef __SYSTEM_CLOCK_HXTAL
-    system_clock_hxtal();
-#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL)
-    system_clock_24m_hxtal();
-#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL)
-    system_clock_36m_hxtal();
-#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
+#if defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
     system_clock_48m_hxtal();
-#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL)
-    system_clock_56m_hxtal();
 #elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
     system_clock_72m_hxtal();
 #elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
     system_clock_96m_hxtal();
-#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
-    system_clock_108m_hxtal();
-
-#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
-    system_clock_48m_irc8m();
-#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
-    system_clock_72m_irc8m();
-#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
-    system_clock_108m_irc8m();
 #endif /* __SYSTEM_CLOCK_HXTAL */
 }
 
@@ -259,192 +204,7 @@ void SystemCoreClockUpdate(void)
     }
 }
 
-#ifdef __SYSTEM_CLOCK_HXTAL
-/*!
-    \brief      configure the system clock to HXTAL
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_hxtal(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-    
-    /* enable HXTAL */
-    RCU_CTL |= RCU_CTL_HXTALEN;
-    
-    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
-    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-    
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
-        while(1){
-        }
-    }
-    
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-    
-    /* select HXTAL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
-    
-    /* wait until HXTAL is selected as system clock */
-    while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){
-    }
-}
-
-#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL)
-/*!
-    \brief      configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_24m_hxtal(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-
-    /* enable HXTAL */
-    RCU_CTL |= RCU_CTL_HXTALEN;
-
-    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
-    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
-        while(1){
-        }
-    }
-
-    /* HXTAL is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-
-    /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6);
-
-    if(HXTAL_VALUE==25000000){
-        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
-
-        /* enable PLL1 */
-        RCU_CTL |= RCU_CTL_PLL1EN;
-        /* wait till PLL1 is ready */
-        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
-        }
-
-    }else if(HXTAL_VALUE==8000000){
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
-    }
-
-    /* enable PLL */
-    RCU_CTL |= RCU_CTL_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
-#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL)
-/*!
-    \brief      configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_36m_hxtal(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-
-    /* enable HXTAL */
-    RCU_CTL |= RCU_CTL_HXTALEN;
-
-    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
-    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
-        while(1){
-        }
-    }
-
-    /* HXTAL is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-
-    /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
-
-    if(HXTAL_VALUE==25000000){
-        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
-
-        /* enable PLL1 */
-        RCU_CTL |= RCU_CTL_PLL1EN;
-        /* wait till PLL1 is ready */
-        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
-        }
-
-    }else if(HXTAL_VALUE==8000000){
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
-    }
-
-    /* enable PLL */
-    RCU_CTL |= RCU_CTL_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
-#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
+#if defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
 /*!
     \brief      configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
     \param[in]  none
@@ -518,78 +278,6 @@ static void system_clock_48m_hxtal(void)
     }
 }
 
-#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL)
-/*!
-    \brief      configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_56m_hxtal(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-
-    /* enable HXTAL */
-    RCU_CTL |= RCU_CTL_HXTALEN;
-
-    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
-    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
-        while(1){
-        }
-    }
-
-    /* HXTAL is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-
-    /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14);
-
-    if(HXTAL_VALUE==25000000){
-
-        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
-
-        /* enable PLL1 */
-        RCU_CTL |= RCU_CTL_PLL1EN;
-        /* wait till PLL1 is ready */
-        while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
-        }
-
-    }else if(HXTAL_VALUE==8000000){
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 );
-    }
-
-    /* enable PLL */
-    RCU_CTL |= RCU_CTL_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
 #elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
 /*!
     \brief      configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
@@ -738,263 +426,6 @@ static void system_clock_96m_hxtal(void)
     }
 }
 
-#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
-/*!
-    \brief      configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-
-static void system_clock_108m_hxtal(void)
-{
-    uint32_t timeout   = 0U;
-    uint32_t stab_flag = 0U;
-
-    /* enable HXTAL */
-    RCU_CTL |= RCU_CTL_HXTALEN;
-
-    /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
-    }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
-        while(1){
-        }
-    }
-
-    /* HXTAL is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-
-    /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ 
-    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-    RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27);
-
-    if(HXTAL_VALUE==25000000){
-        /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 | RCU_PREDV0_DIV10);
-
-        /* enable PLL1 */
-        RCU_CTL |= RCU_CTL_PLL1EN;
-        /* wait till PLL1 is ready */
-        while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){
-        }
-
-        /* enable PLL1 */
-        RCU_CTL |= RCU_CTL_PLL2EN;
-        /* wait till PLL1 is ready */
-        while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){
-        }
-    }else if(HXTAL_VALUE==8000000){
-        RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0);
-        RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 | RCU_PLL1_MUL20 | RCU_PLL2_MUL20);
-
-        /* enable PLL1 */
-        RCU_CTL |= RCU_CTL_PLL1EN;
-        /* wait till PLL1 is ready */
-        while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){
-        }
-
-        /* enable PLL2 */
-        RCU_CTL |= RCU_CTL_PLL2EN;
-        /* wait till PLL1 is ready */
-        while(0U == (RCU_CTL & RCU_CTL_PLL2STB)){
-        }
-
-    }
-    /* enable PLL */
-    RCU_CTL |= RCU_CTL_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
-#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
-/*!
-    \brief      configure the system clock to 48M by PLL which selects IRC8M as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_48m_irc8m(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-    
-    /* enable IRC8M */
-    RCU_CTL |= RCU_CTL_IRC8MEN;
-
-    /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
-    }
-    while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
-      while(1){
-      }
-    }
-
-    /* IRC8M is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-
-    /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-    RCU_CFG0 |= RCU_PLL_MUL12;
-
-    /* enable PLL */
-    RCU_CTL |= RCU_CTL_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
-#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
-/*!
-    \brief      configure the system clock to 72M by PLL which selects IRC8M as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_72m_irc8m(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-    
-    /* enable IRC8M */
-    RCU_CTL |= RCU_CTL_IRC8MEN;
-
-    /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
-    }
-    while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
-      while(1){
-      }
-    }
-
-    /* IRC8M is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-
-    /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-    RCU_CFG0 |= RCU_PLL_MUL18;
-
-    /* enable PLL */
-    RCU_CTL |= RCU_CTL_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
-#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
-/*!
-    \brief      configure the system clock to 108M by PLL which selects IRC8M as its clock source
-    \param[in]  none
-    \param[out] none
-    \retval     none
-*/
-static void system_clock_108m_irc8m(void)
-{
-    uint32_t timeout = 0U;
-    uint32_t stab_flag = 0U;
-    
-    /* enable IRC8M */
-    RCU_CTL |= RCU_CTL_IRC8MEN;
-
-    /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
-    do{
-        timeout++;
-        stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
-    }
-    while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
-
-    /* if fail */
-    if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
-      while(1){
-      }
-    }
-
-    /* IRC8M is stable */
-    /* AHB = SYSCLK */
-    RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
-    /* APB2 = AHB/1 */
-    RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
-    /* APB1 = AHB/2 */
-    RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
-
-    /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */
-    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
-    RCU_CFG0 |= RCU_PLL_MUL27;
-
-    /* enable PLL */
-    RCU_CTL |= RCU_CTL_PLLEN;
-
-    /* wait until PLL is stable */
-    while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
-    }
-
-    /* select PLL as system clock */
-    RCU_CFG0 &= ~RCU_CFG0_SCS;
-    RCU_CFG0 |= RCU_CKSYSSRC_PLL;
-
-    /* wait until PLL is selected as system clock */
-    while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
-    }
-}
-
 #endif
 
 /**
@@ -1122,19 +553,6 @@ uint32_t core_exception_handler(unsigned long mcause, unsigned long sp)
 }
 /** @} */ /* End of Doxygen Group NMSIS_Core_ExceptionAndNMI */
 
-void SystemBannerPrint(void)
-{
-#if defined(NUCLEI_BANNER) && (NUCLEI_BANNER == 1)
-#ifndef DOWNLOAD_MODE
-#error DOWNLOAD_MODE is not defined via build system, please check!
-#endif
-    const char* download_modes[] = {"FLASHXIP", "FLASH", "ILM", "DDR"};
-    printf("Nuclei SDK Build Time: %s, %s\r\n", __DATE__, __TIME__);
-    printf("Download Mode: %s\r\n", download_modes[DOWNLOAD_MODE]);
-    printf("CPU Frequency %d Hz\r\n", SystemCoreClock);
-#endif
-}
-
 /**
  * \brief initialize eclic config
  * \details
@@ -1199,12 +617,6 @@ int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_
  */
 void _premain_init(void)
 {
-    /* TODO: Add your own initialization code here, called before main */
-    //SystemCoreClock = get_cpu_freq();
-    /* configure USART */
-    /*gd_com_init(SOC_DEBUG_UART);*/
-    /* Display banner after UART initialized */
-    /*SystemBannerPrint();*/
     /* Initialize exception default handlers */
     Exception_Init();
     /* ECLIC initialization, mainly MTH and NLBIT */

From 60d03110f73830fd468a957e0f14467e9c900174 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 11:24:40 +0200
Subject: [PATCH 0312/2085] Correctly initialize and handle the system tick

Forgot to reload the systick timer in the irq handler
---
 .../gd32vf103_longan_nano.c                      | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
index d832503b1..99eb3d6b6 100644
--- a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
+++ b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
@@ -67,12 +67,7 @@ void board_init(void) {
   SystemCoreClockUpdate();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
-  SysTimer_SetLoadValue(0);
-  SysTimer_SetCompareValue(SystemCoreClock / 1000);
-  ECLIC_SetLevelIRQ(SysTimer_IRQn, 3);
-  ECLIC_SetTrigIRQ(SysTimer_IRQn, ECLIC_POSTIVE_EDGE_TRIGGER);
-  ECLIC_EnableIRQ(SysTimer_IRQn);
-  SysTimer_Start();
+  SysTick_Config(TIMER_TICKS);
 #endif
 
   rcu_periph_clock_enable(RCU_GPIOA);
@@ -188,7 +183,10 @@ int board_uart_write(void const* buf, int len) {
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void eclic_mtip_handler(void) { system_ticks++; }
+void eclic_mtip_handler(void) {
+  system_ticks++;
+  SysTick_Reload(TIMER_TICKS);
+}
 uint32_t board_millis(void) { return system_ticks; }
 #endif
 
@@ -209,7 +207,3 @@ void assert_failed(char* file, uint32_t line) {
   /* USER CODE END 6 */
 }
 #endif /* USE_FULL_ASSERT */
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-// void _init(void) {}

From 66d566f8c0a4bc2f08ec7fe146c3142dcd8c6f3b Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 11:25:28 +0200
Subject: [PATCH 0313/2085] Use functions provided by the nuclei-sdk hal

---
 .../gd32vf103_longan_nano.c                   | 30 +++++--------------
 1 file changed, 8 insertions(+), 22 deletions(-)

diff --git a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
index 99eb3d6b6..7c71a89f5 100644
--- a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
+++ b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
@@ -39,33 +39,19 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); }
 
 #define USB_NO_VBUS_PIN
 
-#define BUTTON_PORT         GPIOA
-#define BUTTON_PIN          GPIO_PIN_0
+#define BUTTON_PORT GPIOA
+#define BUTTON_PIN GPIO_PIN_0
 #define BUTTON_STATE_ACTIVE 1
 
-#define UART_DEV            SOC_DEBUG_UART
+#define UART_DEV SOC_DEBUG_UART
 
-#define LED_PIN             LED_R
+#define LED_PIN LED_R
+#define TIMER_TICKS (SystemCoreClock / 1000)
 
 void board_init(void) {
   /* Disable interrupts during init */
   __disable_irq();
 
-  ECLIC_Init();
-
-  /* Reset eclic interrupt registers */
-  for (int32_t i = 0; i < SOC_INT_MAX; i++) {
-    ECLIC->CTRL[0].INTIP = 0;
-    ECLIC->CTRL[0].INTIE = 0;
-    ECLIC->CTRL[0].INTATTR = 0;
-    ECLIC->CTRL[0].INTCTRL = 0;
-  }
-
-  /* Set 4 bits for interrupt level and 0 bits for priority */
-  __ECLIC_SetCfgNlbits(4);
-
-  SystemCoreClockUpdate();
-
 #if CFG_TUSB_OS == OPT_OS_NONE
   SysTick_Config(TIMER_TICKS);
 #endif
@@ -104,9 +90,9 @@ void board_init(void) {
   rcu_periph_reset_enable(RCU_USBFSRST);
   rcu_periph_reset_disable(RCU_USBFSRST);
 
-  /* Set IRQ priority and trigger */
-  ECLIC_SetLevelIRQ(USBFS_IRQn, 3);
-  ECLIC_SetTrigIRQ(USBFS_IRQn, ECLIC_POSTIVE_EDGE_TRIGGER);
+  /* Configure USBFS IRQ */
+  ECLIC_Register_IRQ(USBFS_IRQn, ECLIC_NON_VECTOR_INTERRUPT,
+                     ECLIC_POSTIVE_EDGE_TRIGGER, 3, 0, NULL);
 
   /* Retrieve otg core registers */
   usb_gr* otg_core_regs = (usb_gr*)(USBFS_REG_BASE + USB_REG_OFFSET_CORE);

From 0399996ee5b7062a6d7ae65c722f32a6d5f4de6d Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 11:31:03 +0200
Subject: [PATCH 0314/2085] Code style changes

---
 hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
index 7c71a89f5..0a1008399 100644
--- a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
+++ b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
@@ -46,6 +46,7 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); }
 #define UART_DEV SOC_DEBUG_UART
 
 #define LED_PIN LED_R
+
 #define TIMER_TICKS (SystemCoreClock / 1000)
 
 void board_init(void) {
@@ -126,11 +127,7 @@ void gd32vf103_reset(void) {
 //--------------------------------------------------------------------+
 
 void board_led_write(bool state) {
-  if (state) {
-    gd_led_on(LED_PIN);
-  } else {
-    gd_led_off(LED_PIN);
-  }
+  state ? gd_led_on(LED_PIN) : gd_led_off(LED_PIN);
 }
 
 uint32_t board_button_read(void) {

From 4cebde65ec59f21f282c67a590c09bf982e99af5 Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 12:00:13 +0200
Subject: [PATCH 0315/2085] Remove unnecessary define guard

The GD32VF103 family only has USB-OTG peripherals.
---
 src/portable/st/synopsys/dcd_synopsys.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 7545ef6f7..b8f6ceda2 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -34,7 +34,7 @@
 #define USE_SOF     0
 
 #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
-    defined (STM32F107xB) || defined (STM32F107xC) || defined (GD32VF103)
+    defined (STM32F107xB) || defined (STM32F107xC)
 #define STM32F1_SYNOPSYS
 #endif
 

From 8b78067cc1142c5915ad5fa1275996e92f91a58d Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 12:06:54 +0200
Subject: [PATCH 0316/2085] Use linear buffer for GD32VF103

As the peripheral is the same as on the STM32F1 and STM32F4 lines we do the same.
---
 src/class/audio/audio_device.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index de0bddcd3..ff4e312a7 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -89,7 +89,8 @@
     (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) || \
     CFG_TUSB_MCU == OPT_MCU_RX63X                                 || \
     CFG_TUSB_MCU == OPT_MCU_RX65X                                 || \
-    CFG_TUSB_MCU == OPT_MCU_RX72N
+    CFG_TUSB_MCU == OPT_MCU_RX72N                                 || \
+    CFG_TUSB_MCU == OPT_MCU_GD32VF103
 #define  USE_LINEAR_BUFFER     0
 #else
 #define  USE_LINEAR_BUFFER     1

From 27f147f421927c6822f00608e2c3757687834e2f Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Sat, 7 Aug 2021 14:08:18 +0200
Subject: [PATCH 0317/2085] Minor style changes

---
 hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
index 0a1008399..e15d4e2b2 100644
--- a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
+++ b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
@@ -39,15 +39,15 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); }
 
 #define USB_NO_VBUS_PIN
 
-#define BUTTON_PORT GPIOA
-#define BUTTON_PIN GPIO_PIN_0
+#define TIMER_TICKS         (SystemCoreClock / 1000)
+
+#define BUTTON_PORT         GPIOA
+#define BUTTON_PIN          GPIO_PIN_0
 #define BUTTON_STATE_ACTIVE 1
 
-#define UART_DEV SOC_DEBUG_UART
+#define UART_DEV            SOC_DEBUG_UART
 
-#define LED_PIN LED_R
-
-#define TIMER_TICKS (SystemCoreClock / 1000)
+#define LED_PIN             LED_R
 
 void board_init(void) {
   /* Disable interrupts during init */

From ea72d64992e7ec1453b1c449f72354aba2758ce8 Mon Sep 17 00:00:00 2001
From: Robert Manzke <robert.manzke@fh-kiel.de>
Date: Sun, 8 Aug 2021 08:30:52 +0200
Subject: [PATCH 0318/2085] STM32L151 portable driver adaptations

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 21 ++++++++++++++++++-
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   |  4 ++++
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 74c144107..eeba7204f 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -113,7 +113,8 @@
       (CFG_TUSB_MCU == OPT_MCU_STM32F0                          ) || \
       (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_FSDEV)) || \
       (CFG_TUSB_MCU == OPT_MCU_STM32F3                          ) || \
-      (CFG_TUSB_MCU == OPT_MCU_STM32L0                          ) \
+	  (CFG_TUSB_MCU == OPT_MCU_STM32L0                          ) || \
+      (CFG_TUSB_MCU == OPT_MCU_STM32L1                          ) \
     )
 
 // In order to reduce the dependance on HAL, we undefine this.
@@ -273,6 +274,20 @@ void dcd_connect(uint8_t rhport)
   USB->BCDR |= USB_BCDR_DPPU;
 }
 
+#elif defined(SYSCFG_PMC_USB_PU) // works e.g. on STM32L151
+// Disable internal D+ PU
+void dcd_disconnect(uint8_t rhport)
+{
+  (void) rhport;
+  SYSCFG->PMC &= ~(SYSCFG_PMC_USB_PU);
+}
+
+// Enable internal D+ PU
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  SYSCFG->PMC |= SYSCFG_PMC_USB_PU;
+}
 #endif
 
 // Enable device interrupt
@@ -284,6 +299,8 @@ void dcd_int_enable (uint8_t rhport)
   __ISB();
 #if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
   NVIC_EnableIRQ(USB_IRQn);
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
+  NVIC_EnableIRQ(USB_LP_IRQn);
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F3
   // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
   // shared USB/CAN IRQs to separate CAN and USB IRQs.
@@ -318,6 +335,8 @@ void dcd_int_disable(uint8_t rhport)
 
 #if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
   NVIC_DisableIRQ(USB_IRQn);
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
+  NVIC_DisableIRQ(USB_LP_IRQn);
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F3
   // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
   // shared USB/CAN IRQs to separate CAN and USB IRQs.
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index d26c700d2..eca8bf575 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -83,6 +83,10 @@
   #include "stm32l0xx.h"
   #define PMA_LENGTH (1024u)
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L1
+  #include "stm32l1xx.h"
+  #define PMA_LENGTH (512u)
+
 #else
   #error You are using an untested or unimplemented STM32 variant. Please update the driver.
   // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4

From 312fd5f839059773982378177beacae0bc28385c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 9 Aug 2021 22:57:11 +0700
Subject: [PATCH 0319/2085] fix hid_test.py for hid inout to correctly
 preceeded with dummy reportID

add note for install hidapi on windows
---
 examples/device/hid_generic_inout/hid_test.py |  5 +++-
 examples/device/hid_generic_inout/src/main.c  | 26 ++++++++++++-------
 2 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/examples/device/hid_generic_inout/hid_test.py b/examples/device/hid_generic_inout/hid_test.py
index c89d89062..a42930fb5 100644
--- a/examples/device/hid_generic_inout/hid_test.py
+++ b/examples/device/hid_generic_inout/hid_test.py
@@ -11,7 +11,10 @@ for dict in hid.enumerate(USB_VID):
     if dev:
         while True:
             # Get input from console and encode to UTF8 for array of chars.
-            str_out = input("Send text to HID Device : ").encode('utf-8')
+            # hid generic inout is single report therefore by HIDAPI requirement
+            # it must be preceeded with 0x00 as dummy reportID
+            str_out = b'\x00'
+            str_out += input("Send text to HID Device : ").encode('utf-8')
             dev.write(str_out)
             str_in = dev.read(64)
             print("Received from HID Device:", str_in, '\n')
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 65874f483..32185560e 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -36,16 +36,24 @@
  *
  * There are 2 ways to test the sketch
  * 1. Using nodejs
- *    - Install nodejs and npm to your PC
- *    - Install excellent node-hid (https://github.com/node-hid/node-hid) by
- *      $ npm install node-hid
- *    - Run provided hid test script
- *      $ node hid_test.js
+ * - Install nodejs and npm to your PC
  *
- * 2. Using python hidRun
- *    - Python and `hid` package is required, for installation please follow https://pypi.org/project/hid/
- *    - Run provided hid test script to send and receive data to this device.
- *      $ python3 hid_test.py
+ * - Install excellent node-hid (https://github.com/node-hid/node-hid) by
+ *   $ npm install node-hid
+ *
+ * - Run provided hid test script
+ *   $ node hid_test.js
+ *
+ * 2. Using python
+ * - Install `hid` package (https://pypi.org/project/hid/) by
+ *   $ pip install hid
+ *
+ * - hid package replies on hidapi (https://github.com/libusb/hidapi) for backend,
+ *   which already available in Linux. However on windows, you may need to download its dlls from their release page and
+ *   copy it over to folder where python is installed.
+ *
+ * - Run provided hid test script to send and receive data to this device.
+ *   $ python3 hid_test.py
  */
 
 //--------------------------------------------------------------------+

From 1b6540a61cef4f7c5eb5b6001a64cd1425e805ff Mon Sep 17 00:00:00 2001
From: Stefan Kerkmann <karlk90@pm.me>
Date: Mon, 9 Aug 2021 21:36:50 +0200
Subject: [PATCH 0320/2085] Update systick reload value

The systick timer is driven by the AHB bus divided by 4, set the correct
reload value to generate a timer irq every ms.
---
 hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
index e15d4e2b2..951ab844c 100644
--- a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
+++ b/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
@@ -39,7 +39,9 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); }
 
 #define USB_NO_VBUS_PIN
 
-#define TIMER_TICKS         (SystemCoreClock / 1000)
+// According to GD32VF103 user manual clock tree:
+// Systick clock = AHB clock / 4.
+#define TIMER_TICKS         ((SystemCoreClock / 4) / 1000) 
 
 #define BUTTON_PORT         GPIOA
 #define BUTTON_PIN          GPIO_PIN_0

From 40afc8c5de7785d7da7653763abad03b9a548542 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 10 Aug 2021 15:40:25 +0700
Subject: [PATCH 0321/2085] update node script to always shift dummy reportID
 like python

allow specify all product id with 0xFFFF in boards.js
---
 examples/device/hid_generic_inout/boards.js   |  6 +++---
 examples/device/hid_generic_inout/hid_test.js | 11 ++++-------
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/examples/device/hid_generic_inout/boards.js b/examples/device/hid_generic_inout/boards.js
index e8437cf53..6b78231a7 100644
--- a/examples/device/hid_generic_inout/boards.js
+++ b/examples/device/hid_generic_inout/boards.js
@@ -1,4 +1,4 @@
 module.exports = {
-	"Feather_nRF52840":[0X239A,0X8029],
-	"Metro_nRF52840":[0X239A,0X803F],
-}
\ No newline at end of file
+	"Adafruit Boards":[0x239A,0xFFFF],
+	"TinyUSB example":[0xCAFE,0xFFFF]
+}
diff --git a/examples/device/hid_generic_inout/hid_test.js b/examples/device/hid_generic_inout/hid_test.js
index eed6b78e2..daa958fd5 100644
--- a/examples/device/hid_generic_inout/hid_test.js
+++ b/examples/device/hid_generic_inout/hid_test.js
@@ -5,8 +5,6 @@ var HID = require('node-hid');
 var os = require('os')
 // list of supported devices
 var boards = require('./boards.js')
-
-var isWin = (os.platform() === 'win32');
 var devices = HID.devices();
 
 // this will choose any device found in the boards.js file
@@ -19,10 +17,8 @@ var message = "Hello World!"
 // This means if you have characters in your string that are not Latin-1 you will have to add additional logic for character codes above 255
 var messageBuffer = Array.from(message, function(c){return c.charCodeAt(0)});
 
-// Windows wants you to prepend a 0 to whatever you send
-if(isWin){
-	messageBuffer.unshift(0)
-}
+// HIDAPI requires us to prepend a 0 for single hid report as dummy reportID
+messageBuffer.unshift(0)
 
 // Some OSes expect that you always send a buffer that equals your report length
 // So lets fill up the rest of the buffer with zeros
@@ -66,6 +62,7 @@ function anySupportedBoard(d) {
 
 
 function isDevice(board,d){
-	return d.vendorId==board[0] && d.productId==board[1];
+	// product id 0xff is matches all
+	return d.vendorId==board[0] && (d.productId==board[1] || board[1] == 0xFFFF);
 }
 

From 2ea0ef4543ed8a3d127f6354ab3a5ae2a48ec245 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 10 Aug 2021 16:40:43 +0700
Subject: [PATCH 0322/2085] correct newline usage keycode (ENTER 0x28)

---
 src/class/hid/hid.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index ec14c9c7c..9265a2ede 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -871,10 +871,10 @@ enum
     {0, 0                     }, /* 0x07           */ \
     {0, HID_KEY_BACKSPACE     }, /* 0x08 Backspace */ \
     {0, HID_KEY_TAB           }, /* 0x09 Tab       */ \
-    {0, HID_KEY_RETURN        }, /* 0x0A Line Feed */ \
+    {0, HID_KEY_ENTER         }, /* 0x0A Line Feed */ \
     {0, 0                     }, /* 0x0B           */ \
     {0, 0                     }, /* 0x0C           */ \
-    {0, HID_KEY_RETURN        }, /* 0x0D CR        */ \
+    {0, HID_KEY_ENTER         }, /* 0x0D CR        */ \
     {0, 0                     }, /* 0x0E           */ \
     {0, 0                     }, /* 0x0F           */ \
     {0, 0                     }, /* 0x10           */ \

From 2c7bb540b41d3609d25cda44add46f5b685cdf7a Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Tue, 10 Aug 2021 20:26:51 +0200
Subject: [PATCH 0323/2085] dcd_da1469x: Use mcu.h instead of MCU specific
 header

dcd_da1469x can work with broader range of MCUs that
share same USB core.
Specific header file that was used DA1469xAB.h now it is changed
to mcu/mcu.h which includes actual MCU specific register file.
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 59f728d08..d209b152d 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -28,7 +28,7 @@
 
 #if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_DA1469X
 
-#include "DA1469xAB.h"
+#include "mcu/mcu.h"
 
 #include "device/dcd.h"
 

From f3a6e564ee9dfe3587d8d9dce051eae76bdb9d0c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 11 Aug 2021 20:06:57 +0700
Subject: [PATCH 0324/2085] rp2040 enable suspend and resume interrupt

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 74 ++++++++++++--------
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |  7 +-
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  6 +-
 3 files changed, 52 insertions(+), 35 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index f78a932f1..f39cfab3e 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -37,6 +37,14 @@
 
 #include "device/dcd.h"
 
+// Current implementation force vbus detection as always present, causing device think it is always plugged into host.
+// Therefore it cannot detect disconnect event, mistaken it as suspend.
+// Note: won't work if change to 0 (for now)
+//
+// Note: Line state when disconnected is very sensitive, in actual testing,
+// it can toggles between J-state (idle) and SE1 if cable still connected to rp2040 (not connected to host)
+#define FORCE_VBUS_DETECT   1
+
 /*------------------------------------------------------------------*/
 /* Low level controller
  *------------------------------------------------------------------*/
@@ -52,14 +60,14 @@ static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2] = {0};
 
 static inline struct hw_endpoint *hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir)
 {
-    return &hw_endpoints[num][dir];
+  return &hw_endpoints[num][dir];
 }
 
 static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
 {
-    uint8_t num = tu_edpt_number(ep_addr);
-    tusb_dir_t dir = tu_edpt_dir(ep_addr);
-    return hw_endpoint_get_by_num(num, dir);
+  uint8_t num = tu_edpt_number(ep_addr);
+  tusb_dir_t dir = tu_edpt_dir(ep_addr);
+  return hw_endpoint_get_by_num(num, dir);
 }
 
 static void _hw_endpoint_alloc(struct hw_endpoint *ep)
@@ -290,7 +298,9 @@ static void dcd_rp2040_irq(void)
         hw_handle_buff_status();
     }
 
-    // SE0 for 2 us or more, usually together with Bus Reset
+#if FORCE_VBUS_DETECT == 0
+    // Since we force VBUS detect On, device will always think it is connected and
+    // couldn't distinguish between disconnect and suspend
     if (status & USB_INTS_DEV_CONN_DIS_BITS)
     {
         handled |= USB_INTS_DEV_CONN_DIS_BITS;
@@ -306,6 +316,7 @@ static void dcd_rp2040_irq(void)
 
         usb_hw_clear->sie_status = USB_SIE_STATUS_CONNECTED_BITS;
     }
+#endif
 
     // SE0 for 2.5 us or more
     if (status & USB_INTS_BUS_RESET_BITS)
@@ -322,7 +333,7 @@ static void dcd_rp2040_irq(void)
 #endif
     }
 
-#if 0
+#if 1
     // TODO Enable SUSPEND & RESUME interrupt and test later on with/without VBUS detection
 
     /* Note from pico datasheet 4.1.2.6.4 (v1.2)
@@ -364,36 +375,43 @@ static void dcd_rp2040_irq(void)
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
+
 void dcd_init (uint8_t rhport)
 {
-    pico_trace("dcd_init %d\n", rhport);
-    assert(rhport == 0);
+  pico_trace("dcd_init %d\n", rhport);
+  assert(rhport == 0);
 
-    // Reset hardware to default state
-    rp2040_usb_init();
+  // Reset hardware to default state
+  rp2040_usb_init();
 
-    irq_set_exclusive_handler(USBCTRL_IRQ, dcd_rp2040_irq);
-    memset(hw_endpoints, 0, sizeof(hw_endpoints));
-    next_buffer_ptr = &usb_dpram->epx_data[0];
+#if FORCE_VBUS_DETECT
+  // Force VBUS detect so the device thinks it is plugged into a host
+  usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
+#endif
 
-    // EP0 always exists so init it now
-    // EP0 OUT
-    hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL);
-    // EP0 IN
-    hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL);
+  irq_set_exclusive_handler(USBCTRL_IRQ, dcd_rp2040_irq);
+  memset(hw_endpoints, 0, sizeof(hw_endpoints));
+  next_buffer_ptr = &usb_dpram->epx_data[0];
 
-    // Initializes the USB peripheral for device mode and enables it.
-    // Don't need to enable the pull up here. Force VBUS
-    usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS;
+  // EP0 always exists so init it now
+  // EP0 OUT
+  hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL);
+  // EP0 IN
+  hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL);
 
-    // Enable individual controller IRQS here. Processor interrupt enable will be used
-    // for the global interrupt enable...
-    // TODO Enable SUSPEND & RESUME interrupt
-    usb_hw->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS; 
-    usb_hw->inte     = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS |
-                       USB_INTS_DEV_CONN_DIS_BITS /* | USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS */  ;
+  // Initializes the USB peripheral for device mode and enables it.
+  // Don't need to enable the pull up here. Force VBUS
+  usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS;
 
-    dcd_connect(rhport);
+  // Enable individual controller IRQS here. Processor interrupt enable will be used
+  // for the global interrupt enable...
+  // Note: Force VBUS detect cause disconnection not detectable
+  usb_hw->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS;
+  usb_hw->inte     = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS |
+                     USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS |
+                     (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS);
+
+  dcd_connect(rhport);
 }
 
 void dcd_int_enable(uint8_t rhport)
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 40a0805c6..2c007ddd3 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -61,8 +61,8 @@ static struct hw_endpoint ep_pool[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
 
 // Flags we set by default in sie_ctrl (we add other bits on top)
 enum {
-  SIE_CTRL_BASE = USB_SIE_CTRL_SOF_EN_BITS        | USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
-                  USB_SIE_CTRL_PULLDOWN_EN_BITS   | USB_SIE_CTRL_EP0_INT_1BUF_BITS
+  SIE_CTRL_BASE = USB_SIE_CTRL_SOF_EN_BITS      | USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
+                  USB_SIE_CTRL_PULLDOWN_EN_BITS | USB_SIE_CTRL_EP0_INT_1BUF_BITS
 };
 
 static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
@@ -360,6 +360,9 @@ bool hcd_init(uint8_t rhport)
     // Reset any previous state
     rp2040_usb_init();
 
+    // Force VBUS detect to always present, for now we assume vbus is always provided (without using VBUS En)
+    usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
+
     irq_set_exclusive_handler(USBCTRL_IRQ, hcd_rp2040_irq);
 
     // clear epx and interrupt eps
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index dc12e6d82..43554d28b 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -62,11 +62,7 @@ void rp2040_usb_init(void)
   memset(usb_dpram, 0, sizeof(*usb_dpram));
 
   // Mux the controller to the onboard usb phy
-  usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS    | USB_USB_MUXING_SOFTCON_BITS;
-
-  // Force VBUS detect so the device thinks it is plugged into a host
-  // TODO support VBUs detect
-  usb_hw->pwr    = USB_USB_PWR_VBUS_DETECT_BITS  | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
+  usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;
 }
 
 void hw_endpoint_reset_transfer(struct hw_endpoint *ep)

From 979af6c2a859a1e76930d429f37abff6a224599a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 11 Aug 2021 20:29:39 +0700
Subject: [PATCH 0325/2085] clean up endpoint set/clear stall

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 78 +++++++++-----------
 src/portable/raspberrypi/rp2040/rp2040_usb.h |  2 +-
 2 files changed, 35 insertions(+), 45 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index f39cfab3e..6b1e79af4 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -230,7 +230,6 @@ static void reset_ep0(void)
     {
         struct hw_endpoint *ep = hw_endpoint_get_by_addr(addrs[i]);
         ep->next_pid = 1u;
-        ep->stalled  = 0;
     }
 }
 
@@ -241,39 +240,9 @@ static void ep0_0len_status(void)
     hw_endpoint_xfer(0x80, NULL, 0);
 }
 
-static void _hw_endpoint_stall(struct hw_endpoint *ep)
+static void bus_reset(void)
 {
-    assert(!ep->stalled);
-    if (tu_edpt_number(ep->ep_addr) == 0)
-    {
-        // A stall on EP0 has to be armed so it can be cleared on the next setup packet
-        usb_hw_set->ep_stall_arm = (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS;
-    }
-    _hw_endpoint_buffer_control_set_mask32(ep, USB_BUF_CTRL_STALL);
-    ep->stalled = true;
-}
 
-static void hw_endpoint_stall(uint8_t ep_addr)
-{
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
-    _hw_endpoint_stall(ep);
-}
-
-static void _hw_endpoint_clear_stall(struct hw_endpoint *ep)
-{
-    if (tu_edpt_number(ep->ep_addr) == 0)
-    {
-        // Probably already been cleared but no harm
-        usb_hw_clear->ep_stall_arm = (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS;
-    }
-    _hw_endpoint_buffer_control_clear_mask32(ep, USB_BUF_CTRL_STALL);
-    ep->stalled = false;
-}
-
-static void hw_endpoint_clear_stall(uint8_t ep_addr)
-{
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
-    _hw_endpoint_clear_stall(ep);
 }
 
 static void dcd_rp2040_irq(void)
@@ -322,9 +291,13 @@ static void dcd_rp2040_irq(void)
     if (status & USB_INTS_BUS_RESET_BITS)
     {
         pico_trace("BUS RESET\n");
-        usb_hw->dev_addr_ctrl = 0;
+
         handled |= USB_INTS_BUS_RESET_BITS;
+
+        usb_hw->dev_addr_ctrl = 0;
+        bus_reset();
         dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
+
         usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
 
 #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
@@ -492,20 +465,37 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
     return true;
 }
 
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
-    pico_trace("dcd_edpt_stall %02x\n", ep_addr);
-    assert(rhport == 0);
-    hw_endpoint_stall(ep_addr);
+  pico_trace("dcd_edpt_stall %02x\n", ep_addr);
+  assert(rhport == 0);
+
+  if ( tu_edpt_number(ep_addr) == 0 )
+  {
+    // A stall on EP0 has to be armed so it can be cleared on the next setup packet
+    usb_hw_set->ep_stall_arm = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS;
+  }
+
+  struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+
+  // TODO check with double buffered
+  _hw_endpoint_buffer_control_set_mask32(ep, USB_BUF_CTRL_STALL);
 }
 
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
-    pico_trace("dcd_edpt_clear_stall %02x\n", ep_addr);
-    assert(rhport == 0);
-    hw_endpoint_clear_stall(ep_addr);
-}
+  pico_trace("dcd_edpt_clear_stall %02x\n", ep_addr);
+  assert(rhport == 0);
 
+  if (tu_edpt_number(ep_addr))
+  {
+    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+
+    // clear stall also reset toggle to DATA0
+    // TODO check with double buffered
+    _hw_endpoint_buffer_control_clear_mask32(ep, USB_BUF_CTRL_STALL | USB_BUF_CTRL_DATA1_PID);
+  }
+}
 
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
@@ -518,8 +508,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 
 void dcd_int_handler(uint8_t rhport)
 {
-    (void) rhport;
-    dcd_rp2040_irq();
+  (void) rhport;
+  dcd_rp2040_irq();
 }
 
 #endif
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 514152cd9..5570a731a 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -42,7 +42,7 @@ struct hw_endpoint
     // Buffer pointer in usb dpram
     uint8_t *hw_data_buf;
 
-    // Have we been stalled
+    // Have we been stalled TODO remove later
     bool stalled;
 
     // Current transfer information

From a2baf9427d62ecb49b8d0e58a7ddb12698ddf814 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 11 Aug 2021 20:36:23 +0700
Subject: [PATCH 0326/2085] more dcd clean up

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 6b1e79af4..0dabdd1d7 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -233,13 +233,6 @@ static void reset_ep0(void)
     }
 }
 
-static void ep0_0len_status(void)
-{
-    // Send 0len complete response on EP0 IN
-    reset_ep0();
-    hw_endpoint_xfer(0x80, NULL, 0);
-}
-
 static void bus_reset(void)
 {
 
@@ -405,7 +398,9 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
     assert(rhport == 0);
 
     // Can't set device address in hardware until status xfer has complete
-    ep0_0len_status();
+    // Send 0len complete response on EP0 IN
+    reset_ep0();
+    hw_endpoint_xfer(0x80, NULL, 0);
 }
 
 void dcd_remote_wakeup(uint8_t rhport)

From 88d4cb402d5db6cb88ffa0aecb78fccfe3ab0afd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Aug 2021 00:11:04 +0700
Subject: [PATCH 0327/2085] simplify hw_endpoint_init()

---
 src/device/dcd.h                             |  1 +
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 65 +++++++++-----------
 2 files changed, 31 insertions(+), 35 deletions(-)

diff --git a/src/device/dcd.h b/src/device/dcd.h
index 8bfad9b72..66767c1fe 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -152,6 +152,7 @@ bool dcd_edpt_xfer_fifo       (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff,
 void dcd_edpt_stall           (uint8_t rhport, uint8_t ep_addr);
 
 // clear stall, data toggle is also reset to DATA0
+// This API never calls with control endpoints, since it is auto cleared when receiving setup packet
 void dcd_edpt_clear_stall     (uint8_t rhport, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 0dabdd1d7..ca083d500 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -101,8 +101,29 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep)
   *ep->endpoint_control = reg;
 }
 
-static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type)
+#if 0 // todo unused
+static void _hw_endpoint_close(struct hw_endpoint *ep)
 {
+    // Clear hardware registers and then zero the struct
+    // Clears endpoint enable
+    *ep->endpoint_control = 0;
+    // Clears buffer available, etc
+    *ep->buffer_control = 0;
+    // Clear any endpoint state
+    memset(ep, 0, sizeof(struct hw_endpoint));
+}
+
+static void hw_endpoint_close(uint8_t ep_addr)
+{
+    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+    _hw_endpoint_close(ep);
+}
+#endif
+
+static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type)
+{
+    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+
     const uint8_t num = tu_edpt_number(ep_addr);
     const tusb_dir_t dir = tu_edpt_dir(ep_addr);
 
@@ -112,7 +133,7 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t ep_addr, uint16_t
     ep->rx = (dir == TUSB_DIR_OUT);
 
     // Response to a setup packet on EP0 starts with pid of 1
-    ep->next_pid = num == 0 ? 1u : 0u;
+    ep->next_pid = (num == 0 ? 1u : 0u);
 
     ep->wMaxPacketSize = wMaxPacketSize;
     ep->transfer_type = transfer_type;
@@ -152,7 +173,7 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t ep_addr, uint16_t
         }
 
         // Now if it hasn't already been done
-        //alloc a buffer and fill in endpoint control register
+        // alloc a buffer and fill in endpoint control register
         // TODO device may change configuration (dynamic), should clear and reallocate
         if(!(ep->configured))
         {
@@ -163,31 +184,6 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t ep_addr, uint16_t
     ep->configured = true;
 }
 
-#if 0 // todo unused
-static void _hw_endpoint_close(struct hw_endpoint *ep)
-{
-    // Clear hardware registers and then zero the struct
-    // Clears endpoint enable
-    *ep->endpoint_control = 0;
-    // Clears buffer available, etc
-    *ep->buffer_control = 0;
-    // Clear any endpoint state
-    memset(ep, 0, sizeof(struct hw_endpoint));
-}
-
-static void hw_endpoint_close(uint8_t ep_addr)
-{
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
-    _hw_endpoint_close(ep);
-}
-#endif
-
-static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t bmAttributes)
-{
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
-    _hw_endpoint_init(ep, ep_addr, wMaxPacketSize, bmAttributes);
-}
-
 static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
     struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
@@ -290,7 +286,6 @@ static void dcd_rp2040_irq(void)
         usb_hw->dev_addr_ctrl = 0;
         bus_reset();
         dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
-
         usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
 
 #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
@@ -394,13 +389,13 @@ void dcd_int_disable(uint8_t rhport)
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-    pico_trace("dcd_set_address %d %d\n", rhport, dev_addr);
-    assert(rhport == 0);
+  pico_trace("dcd_set_address %d %d\n", rhport, dev_addr);
+  assert(rhport == 0);
 
-    // Can't set device address in hardware until status xfer has complete
-    // Send 0len complete response on EP0 IN
-    reset_ep0();
-    hw_endpoint_xfer(0x80, NULL, 0);
+  // Can't set device address in hardware until status xfer has complete
+  // Send 0len complete response on EP0 IN
+  reset_ep0();
+  hw_endpoint_xfer(0x80, NULL, 0);
 }
 
 void dcd_remote_wakeup(uint8_t rhport)

From 4f2999bc0488cf6bb9823ea315e0960888d1d593 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Aug 2021 00:12:15 +0700
Subject: [PATCH 0328/2085] white space

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 96 ++++++++++----------
 1 file changed, 48 insertions(+), 48 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index ca083d500..24c6c010e 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -70,13 +70,13 @@ static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
   return hw_endpoint_get_by_num(num, dir);
 }
 
-static void _hw_endpoint_alloc(struct hw_endpoint *ep)
+static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
 {
   // size must be multiple of 64
   uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
 
   // double buffered for Control and Bulk endpoint
-  if ( ep->transfer_type == TUSB_XFER_CONTROL || ep->transfer_type == TUSB_XFER_BULK)
+  if ( transfer_type == TUSB_XFER_CONTROL || transfer_type == TUSB_XFER_BULK )
   {
     size *= 2u;
   }
@@ -96,7 +96,7 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep)
             ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
 
   // Fill in endpoint control register with buffer offset
-  uint32_t const reg = EP_CTRL_ENABLE_BITS | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
+  uint32_t const reg = EP_CTRL_ENABLE_BITS | (transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
 
   *ep->endpoint_control = reg;
 }
@@ -122,66 +122,66 @@ static void hw_endpoint_close(uint8_t ep_addr)
 
 static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type)
 {
-    struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+  struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
 
-    const uint8_t num = tu_edpt_number(ep_addr);
-    const tusb_dir_t dir = tu_edpt_dir(ep_addr);
+  const uint8_t num = tu_edpt_number(ep_addr);
+  const tusb_dir_t dir = tu_edpt_dir(ep_addr);
 
-    ep->ep_addr = ep_addr;
+  ep->ep_addr = ep_addr;
 
-    // For device, IN is a tx transfer and OUT is an rx transfer
-    ep->rx = (dir == TUSB_DIR_OUT);
+  // For device, IN is a tx transfer and OUT is an rx transfer
+  ep->rx = (dir == TUSB_DIR_OUT);
 
-    // Response to a setup packet on EP0 starts with pid of 1
-    ep->next_pid = (num == 0 ? 1u : 0u);
+  // Response to a setup packet on EP0 starts with pid of 1
+  ep->next_pid = (num == 0 ? 1u : 0u);
 
-    ep->wMaxPacketSize = wMaxPacketSize;
-    ep->transfer_type = transfer_type;
+  ep->wMaxPacketSize = wMaxPacketSize;
+  ep->transfer_type = transfer_type;
 
-    // Every endpoint has a buffer control register in dpram
-    if (dir == TUSB_DIR_IN)
+  // Every endpoint has a buffer control register in dpram
+  if ( dir == TUSB_DIR_IN )
+  {
+    ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in;
+  }
+  else
+  {
+    ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].out;
+  }
+
+  // Clear existing buffer control state
+  *ep->buffer_control = 0;
+
+  if ( num == 0 )
+  {
+    // EP0 has no endpoint control register because
+    // the buffer offsets are fixed
+    ep->endpoint_control = NULL;
+
+    // Buffer offset is fixed
+    ep->hw_data_buf = (uint8_t*) &usb_dpram->ep0_buf_a[0];
+  }
+  else
+  {
+    // Set the endpoint control register (starts at EP1, hence num-1)
+    if ( dir == TUSB_DIR_IN )
     {
-        ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in;
+      ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].in;
     }
     else
     {
-        ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].out;
+      ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].out;
     }
 
-    // Clear existing buffer control state
-    *ep->buffer_control = 0;
-
-    if (num == 0)
+    // Now if it hasn't already been done
+    // alloc a buffer and fill in endpoint control register
+    // TODO device may change configuration (dynamic), should clear and reallocate
+    if ( !(ep->configured) )
     {
-        // EP0 has no endpoint control register because
-        // the buffer offsets are fixed
-        ep->endpoint_control = NULL;
-
-        // Buffer offset is fixed
-        ep->hw_data_buf = (uint8_t*)&usb_dpram->ep0_buf_a[0];
+      _hw_endpoint_alloc(ep, transfer_type);
     }
-    else
-    {
-        // Set the endpoint control register (starts at EP1, hence num-1)
-        if (dir == TUSB_DIR_IN)
-        {
-            ep->endpoint_control = &usb_dpram->ep_ctrl[num-1].in;
-        }
-        else
-        {
-            ep->endpoint_control = &usb_dpram->ep_ctrl[num-1].out;
-        }
+  }
 
-        // Now if it hasn't already been done
-        // alloc a buffer and fill in endpoint control register
-        // TODO device may change configuration (dynamic), should clear and reallocate
-        if(!(ep->configured))
-        {
-            _hw_endpoint_alloc(ep);
-        }
-    }
-
-    ep->configured = true;
+  ep->configured = true;
 }
 
 static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)

From cde607338d723e3d62fba6cfb9ea4b07eb89a55d Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Wed, 11 Aug 2021 14:45:47 +0200
Subject: [PATCH 0329/2085] da1469x: Fix no VBUS startup

For self powered device if device started without VBUS present
it would not be correctly attached to USB bus even if tusb_vbus_changed()
was later called.

This modifies dcd_init() so it starts USB state machine without checking
if VBUS is present or not, like all others drivers do.
tusb_vbus_changed() function is also removed its content was moved to dcd_init.
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 38 ++++++-----------------
 1 file changed, 10 insertions(+), 28 deletions(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index d209b152d..5fcf3bc5b 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -258,33 +258,6 @@ static const tusb_desc_endpoint_t ep0IN_desc =
 
 #define XFER_CTL_BASE(_ep, _dir) &_dcd.xfer_status[_ep][_dir]
 
-// Function could be called when VBUS change was detected.
-void tusb_vbus_changed(bool present)
-{
-  if (present != _dcd.vbus_present)
-  {
-    _dcd.vbus_present = present;
-    if (present)
-    {
-      USB->USB_MCTRL_REG = USB_USB_MCTRL_REG_USBEN_Msk;
-      USB->USB_NFSR_REG = 0;
-      USB->USB_FAR_REG = 0x80;
-      USB->USB_NFSR_REG = NFSR_NODE_RESET;
-      USB->USB_TXMSK_REG = 0;
-      USB->USB_RXMSK_REG = 0;
-
-      USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk |
-                           USB_USB_MAMSK_REG_USB_M_ALT_Msk |
-                           USB_USB_MAMSK_REG_USB_M_WARN_Msk;
-      USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk;
-    }
-    else
-    {
-      USB->USB_MCTRL_REG = 0;
-    }
-  }
-}
-
 static void fill_tx_fifo(xfer_ctl_t * xfer)
 {
   int left_to_send;
@@ -763,7 +736,16 @@ static void handle_ep0_nak(void)
 void dcd_init(uint8_t rhport)
 {
   USB->USB_MCTRL_REG = USB_USB_MCTRL_REG_USBEN_Msk;
-  tusb_vbus_changed((CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk) != 0);
+  USB->USB_NFSR_REG = 0;
+  USB->USB_FAR_REG = 0x80;
+  USB->USB_NFSR_REG = NFSR_NODE_RESET;
+  USB->USB_TXMSK_REG = 0;
+  USB->USB_RXMSK_REG = 0;
+
+  USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk |
+                       USB_USB_MAMSK_REG_USB_M_ALT_Msk |
+                       USB_USB_MAMSK_REG_USB_M_WARN_Msk;
+  USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk;
 
   dcd_connect(rhport);
 }

From 4ad47d9e264a7119f5429a045a185ad0d448d998 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Aug 2021 15:40:26 +0700
Subject: [PATCH 0330/2085] bus_reset will reset all endpoints

allow for dynamic configuration as well as state-less enumeration
---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 50 +++++++-------------
 1 file changed, 17 insertions(+), 33 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 24c6c010e..63d8278da 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -40,9 +40,6 @@
 // Current implementation force vbus detection as always present, causing device think it is always plugged into host.
 // Therefore it cannot detect disconnect event, mistaken it as suspend.
 // Note: won't work if change to 0 (for now)
-//
-// Note: Line state when disconnected is very sensitive, in actual testing,
-// it can toggles between J-state (idle) and SE1 if cable still connected to rp2040 (not connected to host)
 #define FORCE_VBUS_DETECT   1
 
 /*------------------------------------------------------------------*/
@@ -56,7 +53,7 @@
 static uint8_t *next_buffer_ptr;
 
 // USB_MAX_ENDPOINTS Endpoints, direction TUSB_DIR_OUT for out and TUSB_DIR_IN for in.
-static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2] = {0};
+static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2];
 
 static inline struct hw_endpoint *hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir)
 {
@@ -75,8 +72,8 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
   // size must be multiple of 64
   uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
 
-  // double buffered for Control and Bulk endpoint
-  if ( transfer_type == TUSB_XFER_CONTROL || transfer_type == TUSB_XFER_BULK )
+  // double buffered Bulk endpoint
+  if ( transfer_type == TUSB_XFER_BULK )
   {
     size *= 2u;
   }
@@ -88,12 +85,7 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
   uint dpram_offset = hw_data_offset(ep->hw_data_buf);
   assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX);
 
-  pico_info("Alloced %d bytes at offset 0x%x (0x%p) for ep %d %s\n",
-            size,
-            dpram_offset,
-            ep->hw_data_buf,
-            tu_edpt_number(ep->ep_addr),
-            ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+  pico_info("  Alloced %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf);
 
   // Fill in endpoint control register with buffer offset
   uint32_t const reg = EP_CTRL_ENABLE_BITS | (transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
@@ -157,7 +149,7 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t
     // the buffer offsets are fixed
     ep->endpoint_control = NULL;
 
-    // Buffer offset is fixed
+    // Buffer offset is fixed (also double buffered)
     ep->hw_data_buf = (uint8_t*) &usb_dpram->ep0_buf_a[0];
   }
   else
@@ -172,16 +164,9 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t
       ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].out;
     }
 
-    // Now if it hasn't already been done
     // alloc a buffer and fill in endpoint control register
-    // TODO device may change configuration (dynamic), should clear and reallocate
-    if ( !(ep->configured) )
-    {
-      _hw_endpoint_alloc(ep, transfer_type);
-    }
+    _hw_endpoint_alloc(ep, transfer_type);
   }
-
-  ep->configured = true;
 }
 
 static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
@@ -229,14 +214,19 @@ static void reset_ep0(void)
     }
 }
 
-static void bus_reset(void)
+static void reset_all_endpoints(void)
 {
+  memset(hw_endpoints, 0, sizeof(hw_endpoints));
+  next_buffer_ptr = &usb_dpram->epx_data[0];
 
+  // Init Control endpoint out & in
+  hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL);
+  hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL);
 }
 
 static void dcd_rp2040_irq(void)
 {
-    uint32_t status = usb_hw->ints;
+    uint32_t const status = usb_hw->ints;
     uint32_t handled = 0;
 
     if (status & USB_INTS_SETUP_REQ_BITS)
@@ -276,7 +266,7 @@ static void dcd_rp2040_irq(void)
     }
 #endif
 
-    // SE0 for 2.5 us or more
+    // SE0 for 2.5 us or more (will last at least 10ms)
     if (status & USB_INTS_BUS_RESET_BITS)
     {
         pico_trace("BUS RESET\n");
@@ -284,7 +274,7 @@ static void dcd_rp2040_irq(void)
         handled |= USB_INTS_BUS_RESET_BITS;
 
         usb_hw->dev_addr_ctrl = 0;
-        bus_reset();
+        reset_all_endpoints();
         dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
         usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
 
@@ -351,14 +341,9 @@ void dcd_init (uint8_t rhport)
 #endif
 
   irq_set_exclusive_handler(USBCTRL_IRQ, dcd_rp2040_irq);
-  memset(hw_endpoints, 0, sizeof(hw_endpoints));
-  next_buffer_ptr = &usb_dpram->epx_data[0];
 
-  // EP0 always exists so init it now
-  // EP0 OUT
-  hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL);
-  // EP0 IN
-  hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL);
+  // reset endpoints
+  reset_all_endpoints();
 
   // Initializes the USB peripheral for device mode and enables it.
   // Don't need to enable the pull up here. Force VBUS
@@ -442,7 +427,6 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
 
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
-    pico_info("dcd_edpt_open %02x\n", desc_edpt->bEndpointAddress);
     assert(rhport == 0);
     hw_endpoint_init(desc_edpt->bEndpointAddress, desc_edpt->wMaxPacketSize.size, desc_edpt->bmAttributes.xfer);
     return true;

From 17ef9f4843250e8c6b6b1fde53ed6a54a4f20470 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Aug 2021 15:46:33 +0700
Subject: [PATCH 0331/2085] add ready check for edpt claim

---
 src/device/usbd.c                            | 5 +++++
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 4 ----
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index a30eab217..bef7725b5 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1191,6 +1191,8 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
 
+  TU_VERIFY(tud_ready());
+
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
@@ -1244,6 +1246,9 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
+  // TODO skip ready() check for now since enumeration also use this API
+  // TU_VERIFY(tud_ready());
+
   TU_LOG2("  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 63d8278da..49284e92e 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -284,9 +284,6 @@ static void dcd_rp2040_irq(void)
 #endif
     }
 
-#if 1
-    // TODO Enable SUSPEND & RESUME interrupt and test later on with/without VBUS detection
-
     /* Note from pico datasheet 4.1.2.6.4 (v1.2)
      * If you enable the suspend interrupt, it is likely you will see a suspend interrupt when
      * the device is first connected but the bus is idle. The bus can be idle for a few ms before
@@ -308,7 +305,6 @@ static void dcd_rp2040_irq(void)
         dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
         usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS;
     }
-#endif
 
     if (status ^ handled)
     {

From d52b981c3af06233891e827edcd484ece244a5a8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Aug 2021 17:07:39 +0700
Subject: [PATCH 0332/2085] revert ready() check in claim (do it later in
 separated PR)

---
 src/device/usbd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index bef7725b5..a15959710 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1191,7 +1191,8 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
 
-  TU_VERIFY(tud_ready());
+  // TODO add this check later, also make sure we don't starve an out endpoint while suspending
+  // TU_VERIFY(tud_ready());
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);

From 0ec794376bdc28aea3def01cc9fcbb7bcc6d5201 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tobias=20Ringstr=C3=B6m?= <tobias@platform42.se>
Date: Fri, 13 Aug 2021 14:11:14 +0200
Subject: [PATCH 0333/2085] Fix dcd_set_address bug when called more than once
 with different addresses (e.g. after plugging the device into a different
 port).

---
 src/portable/st/synopsys/dcd_synopsys.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index c15694eba..e36c2ba26 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -519,7 +519,7 @@ void dcd_int_disable (uint8_t rhport)
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
   USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  dev->DCFG |= (dev_addr << USB_OTG_DCFG_DAD_Pos) & USB_OTG_DCFG_DAD_Msk;
+  dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos);
 
   // Response with status after changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);

From 6af1950c8d90c41664b079ad78a0918b4821ea92 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 14 Aug 2021 01:51:13 +0700
Subject: [PATCH 0334/2085] synopsys clear DAD on bus_reset

---
 src/portable/st/synopsys/dcd_synopsys.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index e36c2ba26..5a5645dd4 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -192,6 +192,10 @@ static void bus_reset(uint8_t rhport)
     out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
   }
 
+  // clear device address
+  dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
+
+  // TODO should probably assign value when reset rather than OR
   dev->DAINTMSK |= (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
   dev->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
   dev->DIEPMSK |= USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;

From 09e4348adcdb0af74a15d8077edf610690dd55a4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 15 Aug 2021 17:19:25 +0700
Subject: [PATCH 0335/2085] move gd32vf103 to its own family

---
 hw/bsp/fomu/family.mk                         |  2 +-
 .../boards/sipeed_longan_nano/board.h}        |  2 --
 .../boards/sipeed_longan_nano/board.mk        | 13 +++++++++
 .../family.c}                                 |  5 +++-
 .../board.mk => gd32vf103/family.mk}          | 27 +++++++++----------
 .../system_gd32vf103.c                        |  2 +-
 src/portable/st/synopsys/dcd_synopsys.c       |  4 +++
 7 files changed, 36 insertions(+), 19 deletions(-)
 rename hw/bsp/{gd32vf103_longan_nano/nuclei_sdk_hal.h => gd32vf103/boards/sipeed_longan_nano/board.h} (91%)
 create mode 100644 hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
 rename hw/bsp/{gd32vf103_longan_nano/gd32vf103_longan_nano.c => gd32vf103/family.c} (98%)
 rename hw/bsp/{gd32vf103_longan_nano/board.mk => gd32vf103/family.mk} (65%)
 rename hw/bsp/{gd32vf103_longan_nano => gd32vf103}/system_gd32vf103.c (99%)

diff --git a/hw/bsp/fomu/family.mk b/hw/bsp/fomu/family.mk
index 40cb5dd45..165535c6b 100644
--- a/hw/bsp/fomu/family.mk
+++ b/hw/bsp/fomu/family.mk
@@ -5,7 +5,7 @@ CFLAGS += \
   -nostdlib \
   -DCFG_TUSB_MCU=OPT_MCU_VALENTYUSB_EPTRI
 
-# Cross Compiler for RISC-V
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
 CROSS_COMPILE = riscv-none-embed-
 
 # All source paths should be relative to the top level.
diff --git a/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h
similarity index 91%
rename from hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
rename to hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h
index 9b2a616a8..fae7c40b7 100644
--- a/hw/bsp/gd32vf103_longan_nano/nuclei_sdk_hal.h
+++ b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h
@@ -2,8 +2,6 @@
 #define _NUCLEI_SDK_HAL_H
 
 #include "gd32vf103c_longan_nano.h"
-#include "drv_usb_hw.h"
-#include "drv_usb_dev.h"
 
 // 4 bits for interrupt level, 0 for priority.
 // level 0 = lowest priority, level 15 = highest priority.
diff --git a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
new file mode 100644
index 000000000..3b8944452
--- /dev/null
+++ b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.mk
@@ -0,0 +1,13 @@
+LONGAN_NANO_SDK_BSP = $(GD32VF103_SDK_SOC)/Board/gd32vf103c_longan_nano
+LINKER_SCRIPTS = $(LONGAN_NANO_SDK_BSP)/Source/GCC
+
+# All source paths should be relative to the top level.
+LD_FILE = $(LINKER_SCRIPTS)/gcc_gd32vf103xb_flashxip.ld # Longan Nano 128k ROM 32k RAM
+#LD_FILE = $(LINKER_SCRIPTS)/gcc_gd32vf103x8_flashxip.ld # Longan Nano Lite 64k ROM 20k RAM
+
+SRC_C += $(LONGAN_NANO_SDK_BSP)/Source/gd32vf103c_longan_nano.c
+INC += $(TOP)/$(LONGAN_NANO_SDK_BSP)/Include
+
+# Longan Nano 128k ROM 32k RAM
+JLINK_DEVICE = gd32vf103cbt6
+#JLINK_DEVICE = gd32vf103c8t6 # Longan Nano Lite 64k ROM 20k RAM
diff --git a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c b/hw/bsp/gd32vf103/family.c
similarity index 98%
rename from hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
rename to hw/bsp/gd32vf103/family.c
index 951ab844c..d76fb9a2a 100644
--- a/hw/bsp/gd32vf103_longan_nano/gd32vf103_longan_nano.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -24,8 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
+#include "board.h"
+#include "drv_usb_hw.h"
+#include "drv_usb_dev.h"
+
 #include "../board.h"
-#include "nuclei_sdk_hal.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/gd32vf103_longan_nano/board.mk b/hw/bsp/gd32vf103/family.mk
similarity index 65%
rename from hw/bsp/gd32vf103_longan_nano/board.mk
rename to hw/bsp/gd32vf103/family.mk
index 5ab275dbe..3479433e4 100644
--- a/hw/bsp/gd32vf103_longan_nano/board.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -1,17 +1,24 @@
-CROSS_COMPILE = riscv32-unknown-elf-
+# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
+#CROSS_COMPILE ?= riscv32-unknown-elf-
+
+# Toolchain from https://nucleisys.com/download.php
+CROSS_COMPILE ?= riscv-nuclei-elf-
+
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
+#CROSS_COMPILE ?= riscv-none-embed-
 
 # Submodules
-DEPS_SUBMODULES += hw/mcu/gd/nuclei-sdk
 NUCLEI_SDK = hw/mcu/gd/nuclei-sdk
+DEPS_SUBMODULES += $(NUCLEI_SDK)
 
 # Nuclei-SDK paths
 GD32VF103_SDK_SOC = $(NUCLEI_SDK)/SoC/gd32vf103
 GD32VF103_SDK_DRIVER = $(GD32VF103_SDK_SOC)/Common/Source/Drivers
-LONGAN_NANO_SDK_BSP = $(GD32VF103_SDK_SOC)/Board/gd32vf103c_longan_nano
-LINKER_SCRIPTS = $(LONGAN_NANO_SDK_BSP)/Source/GCC
 LIBC_STUBS = $(GD32VF103_SDK_SOC)/Common/Source/Stubs
 STARTUP_ASM = $(GD32VF103_SDK_SOC)/Common/Source/GCC
 
+include $(TOP)/$(BOARD_PATH)/board.mk
+
 SKIP_NANOLIB = 1
 
 CFLAGS += \
@@ -27,17 +34,12 @@ CFLAGS += \
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
 
-# All source paths should be relative to the top level.
-LD_FILE = $(LINKER_SCRIPTS)/gcc_gd32vf103xb_flashxip.ld # Longan Nano 128k ROM 32k RAM
-#LD_FILE = $(LINKER_SCRIPTS)/gcc_gd32vf103x8_flashxip.ld # Longan Nano Lite 64k ROM 20k RAM 
-
 SRC_C += \
 	src/portable/st/synopsys/dcd_synopsys.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
 	$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_usart.c \
-	$(LONGAN_NANO_SDK_BSP)/Source/gd32vf103c_longan_nano.c \
 	$(LIBC_STUBS)/sbrk.c \
 	$(LIBC_STUBS)/close.c \
 	$(LIBC_STUBS)/isatty.c \
@@ -50,19 +52,16 @@ SRC_S += \
 	$(STARTUP_ASM)/intexc_gd32vf103.S
 
 INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(NUCLEI_SDK)/NMSIS/Core/Include \
 	$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include \
-	$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include/Usb \
-	$(TOP)/$(LONGAN_NANO_SDK_BSP)/Include
+	$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include/Usb
 
 # For freeRTOS port source
 FREERTOS_PORT = RISC-V
 
 # For flash-jlink target
 JLINK_IF = jtag
-JLINK_DEVICE = gd32vf103cbt6 # Longan Nano 128k ROM 32k RAM
-#JLINK_DEVICE = gd32vf103c8t6 # Longan Nano Lite 64k ROM 20k RAM
 
 # flash target ROM bootloader
 flash: $(BUILD)/$(PROJECT).bin
diff --git a/hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c b/hw/bsp/gd32vf103/system_gd32vf103.c
similarity index 99%
rename from hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c
rename to hw/bsp/gd32vf103/system_gd32vf103.c
index 8019974d6..29518a54a 100644
--- a/hw/bsp/gd32vf103_longan_nano/system_gd32vf103.c
+++ b/hw/bsp/gd32vf103/system_gd32vf103.c
@@ -33,7 +33,7 @@ OF SUCH DAMAGE.
 */
 
 /* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */
-#include "nuclei_sdk_hal.h"
+#include "board.h"
 
 /* system frequency define */
 #define __IRC8M           (IRC8M_VALUE)            /* internal 8 MHz RC oscillator frequency */
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index b8f6ceda2..ea19080ae 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -303,6 +303,8 @@ static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed)
     // Turnaround timeout depends on the MCU clock
     uint32_t turnaround;
 
+    TU_LOG_INT(2, SystemCoreClock);
+
     if ( SystemCoreClock >= 32000000U )
       turnaround = 0x6U;
     else if ( SystemCoreClock >= 27500000U )
@@ -646,6 +648,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 
     _allocated_fifo_words_tx += fifo_size;
 
+    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
+
     // DIEPTXF starts at FIFO #1.
     // Both TXFD and TXSA are in unit of 32-bit words.
     usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);

From 37d9f940eed4380241b7d16a0a2c1812ac7c6861 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 15 Aug 2021 17:21:31 +0700
Subject: [PATCH 0336/2085] add gd32vf103 to riscv ci

---
 .github/workflows/build_riscv.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 1e3046d2c..78510751c 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -16,6 +16,7 @@ jobs:
         family:
         # Alphabetical order
         - 'fomu'
+        - 'gd32vf103'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v2

From 73f8fae036ca6fa1b51113b752486ce3970cd54e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 15 Aug 2021 17:28:14 +0700
Subject: [PATCH 0337/2085] change toolchain to riscv-none-embed-gcc-xpack for
 ci

---
 hw/bsp/gd32vf103/family.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk
index 3479433e4..9148e7f8b 100644
--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -2,10 +2,10 @@
 #CROSS_COMPILE ?= riscv32-unknown-elf-
 
 # Toolchain from https://nucleisys.com/download.php
-CROSS_COMPILE ?= riscv-nuclei-elf-
+#CROSS_COMPILE ?= riscv-nuclei-elf-
 
 # Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-#CROSS_COMPILE ?= riscv-none-embed-
+CROSS_COMPILE ?= riscv-none-embed-
 
 # Submodules
 NUCLEI_SDK = hw/mcu/gd/nuclei-sdk

From c4a6a5ccb710828111eda25b98704ae489fc63ab Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 15 Aug 2021 17:56:04 +0700
Subject: [PATCH 0338/2085] skip freertos example for gd32vf103

---
 examples/device/cdc_msc_freertos/.skip.MCU_GD32VF103     | 0
 examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h    | 9 ++++++---
 .../device/hid_composite_freertos/.skip.MCU_GD32VF103    | 0
 .../device/hid_composite_freertos/src/FreeRTOSConfig.h   | 9 ++++++---
 4 files changed, 12 insertions(+), 6 deletions(-)
 create mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_GD32VF103
 create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_GD32VF103

diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_GD32VF103 b/examples/device/cdc_msc_freertos/.skip.MCU_GD32VF103
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
index b76d59706..568b27a18 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
@@ -150,11 +150,14 @@ extern uint32_t SystemCoreClock;
 //--------------------------------------------------------------------+
 // Interrupt nesting behavior configuration.
 //--------------------------------------------------------------------+
-/* Cortex-M specific definitions. __NVIC_PRIO_BITS is defined in core_cmx.h */
-#ifdef __NVIC_PRIO_BITS
+#if defined(__NVIC_PRIO_BITS)
+  // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
 	#define configPRIO_BITS       __NVIC_PRIO_BITS
+#elif defined(__ECLIC_INTCTLBITS)
+  // RISC-V Bumblebee core from nuclei
+  #define configPRIO_BITS       __ECLIC_INTCTLBITS
 #else
-  #error "This port requires __NVIC_PRIO_BITS to be defined"
+  #error "FreeRTOS configPRIO_BITS to be defined"
 #endif
 
 /* The lowest interrupt priority that can be used in a call to a "set priority" function. */
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_GD32VF103 b/examples/device/hid_composite_freertos/.skip.MCU_GD32VF103
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
index b76d59706..568b27a18 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
@@ -150,11 +150,14 @@ extern uint32_t SystemCoreClock;
 //--------------------------------------------------------------------+
 // Interrupt nesting behavior configuration.
 //--------------------------------------------------------------------+
-/* Cortex-M specific definitions. __NVIC_PRIO_BITS is defined in core_cmx.h */
-#ifdef __NVIC_PRIO_BITS
+#if defined(__NVIC_PRIO_BITS)
+  // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
 	#define configPRIO_BITS       __NVIC_PRIO_BITS
+#elif defined(__ECLIC_INTCTLBITS)
+  // RISC-V Bumblebee core from nuclei
+  #define configPRIO_BITS       __ECLIC_INTCTLBITS
 #else
-  #error "This port requires __NVIC_PRIO_BITS to be defined"
+  #error "FreeRTOS configPRIO_BITS to be defined"
 #endif
 
 /* The lowest interrupt priority that can be used in a call to a "set priority" function. */

From ab2eec77d46b0c4984ff0daa13467dde2dc4ad3c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 16 Aug 2021 20:22:14 +0700
Subject: [PATCH 0339/2085] complete suspend, resume, remote wakeup for nrf52

---
 src/device/usbd.c                     |  29 ++++++--
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 103 ++++++++++++++++++--------
 2 files changed, 97 insertions(+), 35 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index a30eab217..538964a3d 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -37,6 +37,9 @@
 // USBD Configuration
 //--------------------------------------------------------------------+
 
+// Debug level of USBD
+#define USBD_DBG_LVL   2
+
 #ifndef CFG_TUD_TASK_QUEUE_SZ
   #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
@@ -556,7 +559,7 @@ void tud_task (void)
       break;
 
       case DCD_EVENT_SUSPEND:
-        TU_LOG2("\r\n");
+        TU_LOG2(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
         if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
       break;
 
@@ -684,6 +687,8 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           // Only support remote wakeup for device feature
           TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
 
+          TU_LOG(USBD_DBG_LVL, "    Enable Remote Wakeup\r\n");
+
           // Host may enable remote wake up before suspending especially HID device
           _usbd_dev.remote_wakeup_en = true;
           tud_control_status(rhport, p_request);
@@ -693,6 +698,8 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           // Only support remote wakeup for device feature
           TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
 
+          TU_LOG(USBD_DBG_LVL, "    Disable Remote Wakeup\r\n");
+
           // Host may disable remote wake up after resuming
           _usbd_dev.remote_wakeup_en = false;
           tud_control_status(rhport, p_request);
@@ -1036,10 +1043,6 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
       }
     break;
 
-    case DCD_EVENT_SOF:
-      return;   // skip SOF event for now
-    break;
-
     case DCD_EVENT_SUSPEND:
       // NOTE: When plugging/unplugging device, the D+/D- state are unstable and
       // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ).
@@ -1061,6 +1064,17 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
       }
     break;
 
+    case DCD_EVENT_SOF:
+      // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup
+      // which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational
+      if ( _usbd_dev.suspended )
+      {
+        _usbd_dev.suspended = 0;
+        dcd_event_t const event_resume = { .rhport = event->rhport, .event_id = DCD_EVENT_RESUME };
+        osal_queue_send(_usbd_q, &event_resume, in_isr);
+      }
+    break;
+
     default:
       osal_queue_send(_usbd_q, event, in_isr);
     break;
@@ -1312,6 +1326,8 @@ bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
+  TU_LOG(USBD_DBG_LVL, "    Stall EP %02X", ep_addr);
+
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
@@ -1322,9 +1338,12 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
+  TU_LOG(USBD_DBG_LVL, "    Clear Stall EP %02X", ep_addr);
+
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
+
   dcd_edpt_clear_stall(rhport, ep_addr);
   _usbd_dev.ep_status[epnum][dir].stalled = false;
   _usbd_dev.ep_status[epnum][dir].busy = false;
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 5f4fe08ad..f6b64c986 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -85,7 +85,7 @@ static struct
   // Number of pending DMA that is started but not handled yet by dcd_int_handler().
   // Since nRF can only carry one DMA can run at a time, this value is normally be either 0 or 1.
   // However, in critical section with interrupt disabled, the DMA can be finished and added up
-  // until handled by dcd_init_handler() when exiting critical section.
+  // until handled by dcd_int_handler() when exiting critical section.
   volatile uint8_t dma_pending;
 }_dcd;
 
@@ -277,14 +277,8 @@ void dcd_remote_wakeup(uint8_t rhport)
   (void) rhport;
 
   // Bring controller out of low power mode
+  // will start wakeup when USBWUALLOWED is set
   NRF_USBD->LOWPOWER = 0;
-
-  // Initiate RESUME signal
-  NRF_USBD->DPDMVALUE = USBD_DPDMVALUE_STATE_Resume;
-  NRF_USBD->TASKS_DPDMDRIVE = 1;
-
-  // TODO There is no USBEVENT Resume interrupt
-  // We may manually raise DCD_EVENT_RESUME event here
 }
 
 // disconnect by disabling internal pull-up resistor on D+/D-
@@ -339,10 +333,13 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     {
       // SPLIT ISO buffer when ISO IN endpoint is already opened.
       if (_dcd.xfer[EP_ISO_NUM][TUSB_DIR_IN].mps) NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_HalfIN;
+
       // Clear old events
       NRF_USBD->EVENTS_ENDISOOUT = 0;
+
       // Clear SOF event in case interrupt was not enabled yet.
       if ((NRF_USBD->INTEN & USBD_INTEN_SOF_Msk) == 0) NRF_USBD->EVENTS_SOF = 0;
+
       // Enable SOF and ISOOUT interrupts, and ISOOUT endpoint.
       NRF_USBD->INTENSET = USBD_INTENSET_ENDISOOUT_Msk | USBD_INTENSET_SOF_Msk;
       NRF_USBD->EPOUTEN |= USBD_EPOUTEN_ISOOUT_Msk;
@@ -350,10 +347,13 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     else
     {
       NRF_USBD->EVENTS_ENDISOIN = 0;
+
       // SPLIT ISO buffer when ISO OUT endpoint is already opened.
       if (_dcd.xfer[EP_ISO_NUM][TUSB_DIR_OUT].mps) NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_HalfIN;
+
       // Clear SOF event in case interrupt was not enabled yet.
       if ((NRF_USBD->INTEN & USBD_INTEN_SOF_Msk) == 0) NRF_USBD->EVENTS_SOF = 0;
+
       // Enable SOF and ISOIN interrupts, and ISOIN endpoint.
       NRF_USBD->INTENSET = USBD_INTENSET_ENDISOIN_Msk | USBD_INTENSET_SOF_Msk;
       NRF_USBD->EPINEN  |= USBD_EPINEN_ISOIN_Msk;
@@ -507,6 +507,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
  *------------------------------------------------------------------*/
 void bus_reset(void)
 {
+  // 6.35.6 USB controller automatically disabled all endpoints (except control)
+  // i.e EPOUTEN and EPINEN and reset USBADDR to 0
   for(int i=0; i<8; i++)
   {
     NRF_USBD->TASKS_STARTEPIN[i] = 0;
@@ -516,6 +518,15 @@ void bus_reset(void)
   NRF_USBD->TASKS_STARTISOIN  = 0;
   NRF_USBD->TASKS_STARTISOOUT = 0;
 
+  // Clear USB Event Interrupt
+  NRF_USBD->EVENTS_USBEVENT = 0;
+  NRF_USBD->EVENTCAUSE |= NRF_USBD->EVENTCAUSE;
+
+  // Reset interrupt
+  NRF_USBD->INTENCLR = NRF_USBD->INTEN;
+  NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_USBEVENT_Msk | USBD_INTEN_EPDATA_Msk |
+          USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk | USBD_INTEN_ENDEPOUT0_Msk;
+
   tu_varclr(&_dcd);
   _dcd.xfer[0][TUSB_DIR_IN].mps = MAX_PACKET_SIZE;
   _dcd.xfer[0][TUSB_DIR_OUT].mps = MAX_PACKET_SIZE;
@@ -561,39 +572,71 @@ void dcd_int_handler(uint8_t rhport)
 
   if ( int_status & USBD_INTEN_SOF_Msk )
   {
+    bool iso_enabled = false;
+
     // ISOOUT: Transfer data gathered in previous frame from buffer to RAM
     if (NRF_USBD->EPOUTEN & USBD_EPOUTEN_ISOOUT_Msk)
     {
+      iso_enabled = true;
       xact_out_dma(EP_ISO_NUM);
     }
+
     // ISOIN: Notify client that data was transferred
-    xfer_td_t* xfer = get_td(EP_ISO_NUM, TUSB_DIR_IN);
-    if ( xfer->iso_in_transfer_ready )
+    if (NRF_USBD->EPINEN & USBD_EPINEN_ISOIN_Msk)
     {
-      xfer->iso_in_transfer_ready = false;
-      dcd_event_xfer_complete(0, EP_ISO_NUM | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
+      iso_enabled = true;
+
+      xfer_td_t* xfer = get_td(EP_ISO_NUM, TUSB_DIR_IN);
+      if ( xfer->iso_in_transfer_ready )
+      {
+        xfer->iso_in_transfer_ready = false;
+        dcd_event_xfer_complete(0, EP_ISO_NUM | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
+      }
     }
+
+    if ( !iso_enabled )
+    {
+      // ISO endpoint is not used, SOF is only enabled one-time for remote wakeup
+      // so we disable it now
+      NRF_USBD->INTENCLR = USBD_INTENSET_SOF_Msk;
+    }
+
     dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
   }
 
   if ( int_status & USBD_INTEN_USBEVENT_Msk )
   {
-    uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & (USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk);
+    TU_LOG(2, "EVENTCAUSE = 0x%04lX\r\n", NRF_USBD->EVENTCAUSE);
+
+    enum { EVT_CAUSE_MASK = USBD_EVENTCAUSE_SUSPEND_Msk | USBD_EVENTCAUSE_RESUME_Msk | USBD_EVENTCAUSE_USBWUALLOWED_Msk };
+    uint32_t const evt_cause = NRF_USBD->EVENTCAUSE & EVT_CAUSE_MASK;
     NRF_USBD->EVENTCAUSE = evt_cause; // clear interrupt
 
     if ( evt_cause & USBD_EVENTCAUSE_SUSPEND_Msk )
     {
-      dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
-
       // Put controller into low power mode
+      // Leave HFXO disable to application, since it may be used by other peripherals
       NRF_USBD->LOWPOWER = 1;
 
-      // Leave HFXO disable to application, since it may be used by other
+      dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
     }
 
-    if ( evt_cause & USBD_EVENTCAUSE_RESUME_Msk  )
+    if ( evt_cause & USBD_EVENTCAUSE_USBWUALLOWED_Msk )
     {
-      dcd_event_bus_signal(0, DCD_EVENT_RESUME , true);
+      // USB is out of low power mode, and wakeup is allowed
+      // Initiate RESUME signal
+      NRF_USBD->DPDMVALUE = USBD_DPDMVALUE_STATE_Resume;
+      NRF_USBD->TASKS_DPDMDRIVE = 1;
+
+      // There is no Resume interrupt for remote wakeup, enable SOF for to report bus ready state
+      // Clear SOF event in case interrupt was not enabled yet.
+      if ((NRF_USBD->INTEN & USBD_INTEN_SOF_Msk) == 0) NRF_USBD->EVENTS_SOF = 0;
+      NRF_USBD->INTENSET = USBD_INTENSET_SOF_Msk;
+    }
+
+    if ( evt_cause & USBD_EVENTCAUSE_RESUME_Msk )
+    {
+      dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
     }
   }
 
@@ -845,18 +888,22 @@ void tusb_hal_nrf_power_event (uint32_t event)
     USB_EVT_READY = 2
   };
 
+#if CFG_TUSB_DEBUG >= 2
+  const char* const power_evt_str[] = { "Detected", "Removed", "Ready" };
+  TU_LOG(2, "Power USB event: %s\r\n", power_evt_str[event]);
+#endif
+
   switch ( event )
   {
     case USB_EVT_DETECTED:
-      TU_LOG2("Power USB Detect\r\n");
-
       if ( !NRF_USBD->ENABLE )
       {
-        /* Prepare for READY event receiving */
+        // Prepare for receiving READY event: disable interrupt since we will blocking wait
+        NRF_USBD->INTENCLR = USBD_INTEN_USBEVENT_Msk;
         NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
         __ISB(); __DSB(); // for sync
 
-#ifdef NRF52_SERIES
+#ifdef NRF52_SERIES // NRF53 does not need this errata
         // ERRATA 171, 187, 166
         if ( nrfx_usbd_errata_187() )
         {
@@ -891,7 +938,7 @@ void tusb_hal_nrf_power_event (uint32_t event)
         }
 #endif
 
-        /* Enable the peripheral */
+        // Enable the peripheral (will cause Ready event)
         NRF_USBD->ENABLE = 1;
         __ISB(); __DSB(); // for sync
 
@@ -901,13 +948,11 @@ void tusb_hal_nrf_power_event (uint32_t event)
     break;
 
     case USB_EVT_READY:
-      TU_LOG2("Power USB Ready\r\n");
-
       // Skip if pull-up is enabled and HCLK is already running.
       // Application probably call this more than necessary.
       if ( NRF_USBD->USBPULLUP && hfclk_running() ) break;
 
-      /* Waiting for USBD peripheral enabled */
+      // Waiting for USBD peripheral enabled
       while ( !(USBD_EVENTCAUSE_READY_Msk & NRF_USBD->EVENTCAUSE) ) { }
 
       NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
@@ -959,9 +1004,8 @@ void tusb_hal_nrf_power_event (uint32_t event)
       // ISO buffer Lower half for IN, upper half for OUT
       NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_HalfIN;
 
-      // Enable interrupt
-      NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk | USBD_INTEN_EPDATA_Msk |
-          USBD_INTEN_EP0SETUP_Msk | USBD_INTEN_EP0DATADONE_Msk | USBD_INTEN_ENDEPIN0_Msk | USBD_INTEN_ENDEPOUT0_Msk;
+      // Enable bus-reset interrupt
+      NRF_USBD->INTENSET = USBD_INTEN_USBRESET_Msk;
 
       // Enable interrupt, priorities should be set by application
       NVIC_ClearPendingIRQ(USBD_IRQn);
@@ -976,7 +1020,6 @@ void tusb_hal_nrf_power_event (uint32_t event)
     break;
 
     case USB_EVT_REMOVED:
-      TU_LOG2("Power USB Removed\r\n");
       if ( NRF_USBD->ENABLE )
       {
         // Abort all transfers

From 26d347be17b68b4c4e22cb3af69bb9428d300c3a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 16 Aug 2021 20:24:07 +0700
Subject: [PATCH 0340/2085] add note for renesas rx remote wakeup

---
 src/portable/renesas/usba/dcd_usba.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 739861413..1db1fdb32 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -824,6 +824,8 @@ void dcd_int_handler(uint8_t rhport)
        * Therefore we need to manually send resume event.
        * Of course, when USB host resumes on its own,
        * RESM interrupt rise properly, then this statements are ignored. */
+      // TODO can be dropped since this logic is implemented by usbd
+      // USBD will exit suspended mode when SOF event is received
       dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
       _dcd.suspended = 0;
     }

From 5a8ea0e0e24f6b6c8374b73f3e0b6df7b15e7b7c Mon Sep 17 00:00:00 2001
From: Peter Lawrence <12226419+majbthrd@users.noreply.github.com>
Date: Mon, 16 Aug 2021 17:04:57 -0500
Subject: [PATCH 0341/2085] net_lwip_webserver: further simplify
 pbuf_copy_partial() usage

---
 examples/device/net_lwip_webserver/src/main.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 7c0adae01..80831921a 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -181,9 +181,7 @@ uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg)
 
   (void)arg; /* unused for this example */
 
-  pbuf_copy_partial(p, dst, p->tot_len, 0);
-
-  return p->tot_len;
+  return pbuf_copy_partial(p, dst, p->tot_len, 0);
 }
 
 static void service_traffic(void)

From 7aff4b178ec415a5d5af2eaebc87e99098037cb8 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Tue, 17 Aug 2021 00:19:24 +0200
Subject: [PATCH 0342/2085] use USBD_MemCopy.

---
 src/portable/nuvoton/nuc121/dcd_nuc121.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index 37b7b0106..959c2eeb0 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -101,6 +101,11 @@ static void usb_detach(void)
   USBD->SE0 |= USBD_SE0_SE0_Msk;
 }
 
+static void usb_memcpy(uint8_t *dest, uint8_t *src, uint16_t size)
+{
+  while(size--) *dest++ = *src++;
+}
+
 static void usb_control_send_zlp(void)
 {
   USBD->EP[PERIPH_EP0].CFG |= USBD_CFG_DSQSYNC_Msk;
@@ -153,7 +158,7 @@ static void dcd_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
   else
 #endif
   {
-    memcpy((uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), xfer->data_ptr, bytes_now);
+    usb_memcpy((uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), xfer->data_ptr, bytes_now);
   }
 
   ep->MXPLD = bytes_now;
@@ -252,7 +257,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   /* mine the data for the information we need */
   int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   int const size = p_endpoint_desc->wMaxPacketSize.size;
-  tusb_xfer_type_t const type = p_endpoint_desc->bmAttributes.xfer;
+  tusb_xfer_type_t const type = (tusb_xfer_type_t)p_endpoint_desc->bmAttributes.xfer;
   struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
 
   /* allocate buffer from USB RAM */
@@ -450,7 +455,7 @@ void dcd_int_handler(uint8_t rhport)
           else
 #endif
           {
-            memcpy(xfer->data_ptr, (uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), available_bytes);
+            usb_memcpy(xfer->data_ptr, (uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), available_bytes);
             xfer->data_ptr += available_bytes;
           }
 

From 5f6418ccd79892c0f8c2152244f7e7a78e17a162 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Aug 2021 13:21:24 +0700
Subject: [PATCH 0343/2085] add hid_boot_interface example

---
 .../device/hid_boot_interface/CMakeLists.txt  |  28 ++
 examples/device/hid_boot_interface/Makefile   |  15 ++
 examples/device/hid_boot_interface/src/main.c | 253 ++++++++++++++++++
 .../hid_boot_interface/src/tusb_config.h      | 111 ++++++++
 .../hid_boot_interface/src/usb_descriptors.c  | 180 +++++++++++++
 .../hid_boot_interface/src/usb_descriptors.h  |  35 +++
 examples/device/hid_composite/src/main.c      |  12 +-
 .../hid_composite/src/usb_descriptors.c       |   4 +-
 .../device/hid_composite_freertos/src/main.c  |  12 +-
 .../src/usb_descriptors.c                     |   4 +-
 10 files changed, 638 insertions(+), 16 deletions(-)
 create mode 100644 examples/device/hid_boot_interface/CMakeLists.txt
 create mode 100644 examples/device/hid_boot_interface/Makefile
 create mode 100644 examples/device/hid_boot_interface/src/main.c
 create mode 100644 examples/device/hid_boot_interface/src/tusb_config.h
 create mode 100644 examples/device/hid_boot_interface/src/usb_descriptors.c
 create mode 100644 examples/device/hid_boot_interface/src/usb_descriptors.h

diff --git a/examples/device/hid_boot_interface/CMakeLists.txt b/examples/device/hid_boot_interface/CMakeLists.txt
new file mode 100644
index 000000000..abc4d91da
--- /dev/null
+++ b/examples/device/hid_boot_interface/CMakeLists.txt
@@ -0,0 +1,28 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/hid_boot_interface/Makefile b/examples/device/hid_boot_interface/Makefile
new file mode 100644
index 000000000..138c27846
--- /dev/null
+++ b/examples/device/hid_boot_interface/Makefile
@@ -0,0 +1,15 @@
+include ../../../tools/top.mk
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += \
+	src/main.c \
+	src/usb_descriptors.c
+	
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../rules.mk
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
new file mode 100644
index 000000000..0d4bc8499
--- /dev/null
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -0,0 +1,253 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+void led_blinking_task(void);
+void hid_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+  tusb_init();
+
+  while (1)
+  {
+    tud_task(); // tinyusb device task
+    led_blinking_task();
+
+    hid_task();
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+  (void) remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// USB HID
+//--------------------------------------------------------------------+
+
+// Every 10ms, we will sent 1 report for each HID profile (keyboard, mouse etc ..)
+// tud_hid_report_complete_cb() is used to send the next report after previous one is complete
+void hid_task(void)
+{
+  // Poll every 10ms
+  const uint32_t interval_ms = 10;
+  static uint32_t start_ms = 0;
+
+  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  start_ms += interval_ms;
+
+  uint32_t const btn = board_button_read();
+
+  if ( tud_suspended() && btn )
+  {
+    // Wake up host if we are in suspend mode
+    // and REMOTE_WAKEUP feature is enabled by host
+    tud_remote_wakeup();
+  }
+  else
+  {
+    // keyboard interface
+    if ( tud_hid_n_ready(ITF_NUM_KEYBOARD) )
+    {
+      // used to avoid send multiple consecutive zero report for keyboard
+      static bool has_keyboard_key = false;
+
+      uint8_t const report_id = 0;
+      uint8_t const modifier  = 0;
+
+      if ( btn )
+      {
+        uint8_t keycode[6] = { 0 };
+        keycode[0] = HID_KEY_ARROW_RIGHT;
+
+        tud_hid_n_keyboard_report(ITF_NUM_KEYBOARD, report_id, modifier, keycode);
+        has_keyboard_key = true;
+      }else
+      {
+        // send empty key report if previously has key pressed
+        if (has_keyboard_key) tud_hid_n_keyboard_report(ITF_NUM_KEYBOARD, report_id, modifier, NULL);
+        has_keyboard_key = false;
+      }
+    }
+
+    // mouse interface
+    if ( tud_hid_n_ready(ITF_NUM_MOUSE) )
+    {
+      if ( btn )
+      {
+        uint8_t const report_id   = 0;
+        uint8_t const button_mask = 0;
+        uint8_t const veritical   = 0;
+        uint8_t const horizontal  = 0;
+        int8_t  const delta       = 5;
+
+        tud_hid_n_mouse_report(ITF_NUM_MOUSE, report_id, button_mask, delta, delta, veritical, horizontal);
+      }
+    }
+  }
+}
+
+// Invoked when received SET_PROTOCOL request
+// protocol is either HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
+void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol)
+{
+  (void) instance;
+  (void) protocol;
+
+  // nothing to do since we use the same compatible boot report for both Boot and Report mode.
+  // TOOD set a indicator for user
+}
+
+// Invoked when sent REPORT successfully to host
+// Application can use this to send the next report
+// Note: For composite reports, report[0] is report ID
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint8_t len)
+{
+  (void) instance;
+  (void) report;
+  (void) len;
+
+  // nothing to do
+}
+
+// Invoked when received GET_REPORT control request
+// Application must fill buffer report's content and return its length.
+// Return zero will cause the stack to STALL request
+uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen)
+{
+  // TODO not Implemented
+  (void) instance;
+  (void) report_id;
+  (void) report_type;
+  (void) buffer;
+  (void) reqlen;
+
+  return 0;
+}
+
+// Invoked when received SET_REPORT control request or
+// received data on OUT endpoint ( Report ID = 0, Type = 0 )
+void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize)
+{
+  // keyboard interface
+  if (instance == ITF_NUM_KEYBOARD)
+  {
+    // Set keyboard LED e.g Capslock, Numlock etc...
+    if (report_type == HID_REPORT_TYPE_OUTPUT)
+    {
+      // bufsize should be (at least) 1
+      if ( bufsize < 1 ) return;
+
+      uint8_t const kbd_leds = buffer[0];
+
+      if (kbd_leds & KEYBOARD_LED_CAPSLOCK)
+      {
+        // Capslock On: disable blink, turn led on
+        blink_interval_ms = 0;
+        board_led_write(true);
+      }else
+      {
+        // Caplocks Off: back to normal blink
+        board_led_write(false);
+        blink_interval_ms = BLINK_MOUNTED;
+      }
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // blink is disabled
+  if (!blink_interval_ms) return;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/device/hid_boot_interface/src/tusb_config.h b/examples/device/hid_boot_interface/src/tusb_config.h
new file mode 100644
index 000000000..59fb9962c
--- /dev/null
+++ b/examples/device/hid_boot_interface/src/tusb_config.h
@@ -0,0 +1,111 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by board.mk
+#ifndef CFG_TUSB_MCU
+  #error CFG_TUSB_MCU must be defined
+#endif
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_DEVICE_RHPORT_NUM
+  #define BOARD_DEVICE_RHPORT_NUM     0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+#ifndef BOARD_DEVICE_RHPORT_SPEED
+  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
+    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
+  #else
+    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
+  #endif
+#endif
+
+// Device mode with rhport and speed defined by board.mk
+#if   BOARD_DEVICE_RHPORT_NUM == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#elif BOARD_DEVICE_RHPORT_NUM == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#else
+  #error "Incorrect RHPort configuration"
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS               OPT_OS_NONE
+#endif
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_HID               2 // 1 for boot keyboard, 1 for boot mouse
+#define CFG_TUD_CDC               0
+#define CFG_TUD_MSC               0
+#define CFG_TUD_MIDI              0
+#define CFG_TUD_VENDOR            0
+
+// HID buffer size Should be sufficient to hold ID (if any) + Data
+#define CFG_TUD_HID_EP_BUFSIZE    8
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.c b/examples/device/hid_boot_interface/src/usb_descriptors.c
new file mode 100644
index 000000000..3fa48d98d
--- /dev/null
+++ b/examples/device/hid_boot_interface/src/usb_descriptors.c
@@ -0,0 +1,180 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]         HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+                           _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = 0x0200,
+    .bDeviceClass       = 0x00,
+    .bDeviceSubClass    = 0x00,
+    .bDeviceProtocol    = 0x00,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = 0xCafe,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+  return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// HID Report Descriptor
+//--------------------------------------------------------------------+
+
+uint8_t const desc_hid_keyboard_report[] =
+{
+  TUD_HID_REPORT_DESC_KEYBOARD()
+};
+
+uint8_t const desc_hid_mouse_report[] =
+{
+  TUD_HID_REPORT_DESC_MOUSE()
+};
+
+// Invoked when received GET HID REPORT DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_hid_descriptor_report_cb(uint8_t instance)
+{
+  return (instance == 0) ? desc_hid_keyboard_report : desc_hid_mouse_report;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+#define CONFIG_TOTAL_LEN  (TUD_CONFIG_DESC_LEN + 2*TUD_HID_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 1 Interrupt, 2 Bulk, 3 Iso, 4 Interrupt, 5 Bulk etc ...
+  #define EPNUM_KEYBOARD   0x81
+  #define EPNUM_MOUSE      0x84
+#else
+  #define EPNUM_KEYBOARD   0x81
+  #define EPNUM_MOUSE      0x82
+#endif
+
+uint8_t const desc_configuration[] =
+{
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+
+  // Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval
+  TUD_HID_DESCRIPTOR(ITF_NUM_KEYBOARD, 0, HID_ITF_PROTOCOL_KEYBOARD, sizeof(desc_hid_keyboard_report), EPNUM_KEYBOARD, CFG_TUD_HID_EP_BUFSIZE, 10),
+
+  // Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval
+  TUD_HID_DESCRIPTOR(ITF_NUM_MOUSE, 0, HID_ITF_PROTOCOL_MOUSE, sizeof(desc_hid_mouse_report), EPNUM_MOUSE, CFG_TUD_HID_EP_BUFSIZE, 10)
+};
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+  return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] =
+{
+  (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+  "TinyUSB",                     // 1: Manufacturer
+  "TinyUSB Device",              // 2: Product
+  "123456",                      // 3: Serials, should use chip ID
+};
+
+static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
+{
+  (void) langid;
+
+  uint8_t chr_count;
+
+  if ( index == 0)
+  {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  }else
+  {
+    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+
+    const char* str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = strlen(str);
+    if ( chr_count > 31 ) chr_count = 31;
+
+    // Convert ASCII string into UTF-16
+    for(uint8_t i=0; i<chr_count; i++)
+    {
+      _desc_str[1+i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+
+  return _desc_str;
+}
diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.h b/examples/device/hid_boot_interface/src/usb_descriptors.h
new file mode 100644
index 000000000..57cf0e2c0
--- /dev/null
+++ b/examples/device/hid_boot_interface/src/usb_descriptors.h
@@ -0,0 +1,35 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef USB_DESCRIPTORS_H_
+#define USB_DESCRIPTORS_H_
+
+enum
+{
+  ITF_NUM_KEYBOARD,
+  ITF_NUM_MOUSE,
+  ITF_NUM_TOTAL
+};
+
+#endif
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index d2a8a28fa..fd25e620a 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -223,9 +223,9 @@ void hid_task(void)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t itf, uint8_t const* report, uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint8_t len)
 {
-  (void) itf;
+  (void) instance;
   (void) len;
 
   uint8_t next_report_id = report[0] + 1;
@@ -239,10 +239,10 @@ void tud_hid_report_complete_cb(uint8_t itf, uint8_t const* report, uint8_t len)
 // Invoked when received GET_REPORT control request
 // Application must fill buffer report's content and return its length.
 // Return zero will cause the stack to STALL request
-uint16_t tud_hid_get_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen)
+uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen)
 {
   // TODO not Implemented
-  (void) itf;
+  (void) instance;
   (void) report_id;
   (void) report_type;
   (void) buffer;
@@ -253,9 +253,9 @@ uint16_t tud_hid_get_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t
 
 // Invoked when received SET_REPORT control request or
 // received data on OUT endpoint ( Report ID = 0, Type = 0 )
-void tud_hid_set_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize)
+void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize)
 {
-  (void) itf;
+  (void) instance;
 
   if (report_type == HID_REPORT_TYPE_OUTPUT)
   {
diff --git a/examples/device/hid_composite/src/usb_descriptors.c b/examples/device/hid_composite/src/usb_descriptors.c
index 1aff5e68e..b9a6e7292 100644
--- a/examples/device/hid_composite/src/usb_descriptors.c
+++ b/examples/device/hid_composite/src/usb_descriptors.c
@@ -82,9 +82,9 @@ uint8_t const desc_hid_report[] =
 // Invoked when received GET HID REPORT DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
-uint8_t const * tud_hid_descriptor_report_cb(uint8_t itf)
+uint8_t const * tud_hid_descriptor_report_cb(uint8_t instance)
 {
-  (void) itf;
+  (void) instance;
   return desc_hid_report;
 }
 
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index a61710858..9c9830e34 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -282,9 +282,9 @@ void hid_task(void* param)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t itf, uint8_t const* report, uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint8_t len)
 {
-  (void) itf;
+  (void) instance;
   (void) len;
 
   uint8_t next_report_id = report[0] + 1;
@@ -299,10 +299,10 @@ void tud_hid_report_complete_cb(uint8_t itf, uint8_t const* report, uint8_t len)
 // Invoked when received GET_REPORT control request
 // Application must fill buffer report's content and return its length.
 // Return zero will cause the stack to STALL request
-uint16_t tud_hid_get_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen)
+uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen)
 {
   // TODO not Implemented
-  (void) itf;
+  (void) instance;
   (void) report_id;
   (void) report_type;
   (void) buffer;
@@ -313,9 +313,9 @@ uint16_t tud_hid_get_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t
 
 // Invoked when received SET_REPORT control request or
 // received data on OUT endpoint ( Report ID = 0, Type = 0 )
-void tud_hid_set_report_cb(uint8_t itf, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize)
+void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize)
 {
-  (void) itf;
+  (void) instance;
 
   if (report_type == HID_REPORT_TYPE_OUTPUT)
   {
diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.c b/examples/device/hid_composite_freertos/src/usb_descriptors.c
index 1aff5e68e..b9a6e7292 100644
--- a/examples/device/hid_composite_freertos/src/usb_descriptors.c
+++ b/examples/device/hid_composite_freertos/src/usb_descriptors.c
@@ -82,9 +82,9 @@ uint8_t const desc_hid_report[] =
 // Invoked when received GET HID REPORT DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
-uint8_t const * tud_hid_descriptor_report_cb(uint8_t itf)
+uint8_t const * tud_hid_descriptor_report_cb(uint8_t instance)
 {
-  (void) itf;
+  (void) instance;
   return desc_hid_report;
 }
 

From a6d18c400ddc6b61f665baae5672ed46af17c99c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Aug 2021 13:29:26 +0700
Subject: [PATCH 0344/2085] fix keyboard report reserved is always 0

---
 src/class/hid/hid_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index a10e3a5e3..2ee80750a 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -121,6 +121,7 @@ bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modi
   hid_keyboard_report_t report;
 
   report.modifier = modifier;
+  report.reserved = 0;
 
   if ( keycode )
   {

From c050612142ba1ab52cce7c7141230d5108e9936b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Aug 2021 13:33:15 +0700
Subject: [PATCH 0345/2085] fix ci build

---
 examples/device/hid_boot_interface/src/main.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 0d4bc8499..e5e2f6856 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -207,6 +207,8 @@ uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id, hid_report_t
 // received data on OUT endpoint ( Report ID = 0, Type = 0 )
 void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id, hid_report_type_t report_type, uint8_t const* buffer, uint16_t bufsize)
 {
+  (void) report_id;
+
   // keyboard interface
   if (instance == ITF_NUM_KEYBOARD)
   {

From 9b869463ddd7277befa30f8e781b9d72ae005c07 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Aug 2021 17:00:53 +0700
Subject: [PATCH 0346/2085] skipped suspend/resume if not connected

---
 src/device/usbd.c | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 538964a3d..e8a50352c 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -559,13 +559,28 @@ void tud_task (void)
       break;
 
       case DCD_EVENT_SUSPEND:
-        TU_LOG2(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
-        if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
+        // NOTE: When plugging/unplugging device, the D+/D- state are unstable and
+        // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ), which result in a series of event
+        // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected
+        if ( _usbd_dev.connected )
+        {
+          TU_LOG2(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
+          if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
+        }else
+        {
+          TU_LOG2(" Skipped\r\n");
+        }
       break;
 
       case DCD_EVENT_RESUME:
-        TU_LOG2("\r\n");
-        if (tud_resume_cb) tud_resume_cb();
+        if ( _usbd_dev.connected )
+        {
+          TU_LOG2("\r\n");
+          if (tud_resume_cb) tud_resume_cb();
+        }else
+        {
+          TU_LOG2(" Skipped\r\n");
+        }
       break;
 
       case DCD_EVENT_SOF:

From 3e8276846ec4db204caf0e3136871b9f4e6b5c81 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 18 Aug 2021 16:38:13 +0700
Subject: [PATCH 0347/2085] correct usb memcpy for nuc120 as well

---
 src/portable/nuvoton/nuc120/dcd_nuc120.c | 13 ++++++++++---
 src/portable/nuvoton/nuc121/dcd_nuc121.c |  6 ++++--
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c
index 047fa3fa6..57cc76e81 100644
--- a/src/portable/nuvoton/nuc120/dcd_nuc120.c
+++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c
@@ -99,6 +99,11 @@ static void usb_detach(void)
   USBD->DRVSE0 |= USBD_DRVSE0_DRVSE0_Msk;
 }
 
+static inline void usb_memcpy(uint8_t *dest, uint8_t *src, uint16_t size)
+{
+  while(size--) *dest++ = *src++;
+}
+
 static void usb_control_send_zlp(void)
 {
   USBD->EP[PERIPH_EP0].CFG |= USBD_CFG_DSQ_SYNC_Msk;
@@ -151,7 +156,8 @@ static void dcd_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
   else
 #endif
   {
-    memcpy((uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), xfer->data_ptr, bytes_now);
+    // USB SRAM seems to only support byte access and memcpy could possibly do it by words
+    usb_memcpy((uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), xfer->data_ptr, bytes_now);
   }
 
   ep->MXPLD = bytes_now;
@@ -246,7 +252,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   /* mine the data for the information we need */
   int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   int const size = p_endpoint_desc->wMaxPacketSize.size;
-  tusb_xfer_type_t const type = p_endpoint_desc->bmAttributes.xfer;
+  tusb_xfer_type_t const type = (tusb_xfer_type_t) p_endpoint_desc->bmAttributes.xfer;
   struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
 
   /* allocate buffer from USB RAM */
@@ -439,7 +445,8 @@ void dcd_int_handler(uint8_t rhport)
           else
 #endif
           {
-            memcpy(xfer->data_ptr, (uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), available_bytes);
+            // USB SRAM seems to only support byte access and memcpy could possibly do it by words
+            usb_memcpy(xfer->data_ptr, (uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), available_bytes);
             xfer->data_ptr += available_bytes;
           }
 
diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index 959c2eeb0..20519ec28 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -101,7 +101,7 @@ static void usb_detach(void)
   USBD->SE0 |= USBD_SE0_SE0_Msk;
 }
 
-static void usb_memcpy(uint8_t *dest, uint8_t *src, uint16_t size)
+static inline void usb_memcpy(uint8_t *dest, uint8_t *src, uint16_t size)
 {
   while(size--) *dest++ = *src++;
 }
@@ -158,6 +158,7 @@ static void dcd_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
   else
 #endif
   {
+    // USB SRAM seems to only support byte access and memcpy could possibly do it by words
     usb_memcpy((uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), xfer->data_ptr, bytes_now);
   }
 
@@ -257,7 +258,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   /* mine the data for the information we need */
   int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   int const size = p_endpoint_desc->wMaxPacketSize.size;
-  tusb_xfer_type_t const type = (tusb_xfer_type_t)p_endpoint_desc->bmAttributes.xfer;
+  tusb_xfer_type_t const type = (tusb_xfer_type_t) p_endpoint_desc->bmAttributes.xfer;
   struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
 
   /* allocate buffer from USB RAM */
@@ -455,6 +456,7 @@ void dcd_int_handler(uint8_t rhport)
           else
 #endif
           {
+            // USB SRAM seems to only support byte access and memcpy could possibly do it by words
             usb_memcpy(xfer->data_ptr, (uint8_t *)(USBD_BUF_BASE + ep->BUFSEG), available_bytes);
             xfer->data_ptr += available_bytes;
           }

From a9279ece33e0e56cf8390da443d0042766f83c3f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 19 Aug 2021 17:27:53 +0700
Subject: [PATCH 0348/2085] merge waveshare to h7 family

---
 hw/bsp/stm32h7/boards/stm32h743eval/board.h   |  11 +
 hw/bsp/stm32h7/boards/stm32h743nucleo/board.h |   6 +
 hw/bsp/stm32h7/boards/stm32h745disco/board.h  |   5 +
 .../STM32H743IITX_FLASH.ld                    | 175 +++++++++++++
 .../boards/waveshare_openh743i_2/board.h      | 229 ++++++++++++++++++
 .../boards/waveshare_openh743i_2/board.mk     |  19 ++
 hw/bsp/stm32h7/family.c                       |  75 +++---
 7 files changed, 472 insertions(+), 48 deletions(-)
 create mode 100644 hw/bsp/stm32h7/boards/waveshare_openh743i_2/STM32H743IITX_FLASH.ld
 create mode 100644 hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.h
 create mode 100644 hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.mk

diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
index ab263d2b7..af2063ce0 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
@@ -52,6 +52,12 @@
 #define OTG_FS_VBUS_SENSE     1
 #define OTG_HS_VBUS_SENSE     0
 
+// USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
+#define ULPI_PINS \
+  {GPIOA, GPIO_PIN_3 }, {GPIOA, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_0 }, {GPIOB, GPIO_PIN_1 }, \
+  {GPIOB, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_10}, {GPIOB, GPIO_PIN_11}, {GPIOB, GPIO_PIN_12}, \
+  {GPIOB, GPIO_PIN_13}, {GPIOC, GPIO_PIN_0 }, {GPIOH, GPIO_PIN_4 }, {GPIOI, GPIO_PIN_11}
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -125,6 +131,11 @@ static inline void board_stm32h7_clock_init(void)
   HAL_EnableCompensationCell();
 }
 
+static inline void board_stm32h7_post_init(void)
+{
+  // For this board does nothing
+}
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
index 3a31783a8..06148c875 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
@@ -109,6 +109,12 @@ static inline void board_stm32h7_clock_init(void)
   HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
 }
 
+static inline void board_stm32h7_post_init(void)
+{
+  // For this board does nothing
+}
+
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.h b/hw/bsp/stm32h7/boards/stm32h745disco/board.h
index 30a7a9ff6..d33e0c8eb 100644
--- a/hw/bsp/stm32h7/boards/stm32h745disco/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.h
@@ -127,6 +127,11 @@ static inline void board_stm32h7_clock_init(void)
   HAL_EnableCompensationCell();
 }
 
+static inline void board_stm32h7_post_init(void)
+{
+  // For this board does nothing
+}
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i_2/STM32H743IITX_FLASH.ld b/hw/bsp/stm32h7/boards/waveshare_openh743i_2/STM32H743IITX_FLASH.ld
new file mode 100644
index 000000000..73d2dedb2
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i_2/STM32H743IITX_FLASH.ld
@@ -0,0 +1,175 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32H7 series
+**                2048Kbytes FLASH and 192Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
+**
+** This software component is licensed by ST under BSD 3-Clause license,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/BSD-3-Clause
+**
+****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x2000 ;  /* required amount of heap  */
+_Min_Stack_Size = 0x2000 ; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 2048K
+  RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
+  RAM_D1 (xrw)   : ORIGIN = 0x24000000, LENGTH = 512K
+  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K
+  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K
+  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.h
new file mode 100644
index 000000000..09442c233
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.h
@@ -0,0 +1,229 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021
+ *    Ha Thach (tinyusb.org)
+ *    Benjamin Evans
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+/* ** BOARD SETUP **
+ *
+ * NOTE: This board has bad signal integrity so you may experience some problems.
+ * This setup assumes you have an openh743i-c Core and breakout board. For the HS
+ * examples it also assumes you have a waveshare USB3300 breakout board plugged
+ * into the ULPI PMOD header on the openh743i-c.
+ *
+ * UART Debugging:
+ * Due to pin conflicts in the HS configuration, this BSP uses USART3 (PD8, PD9).
+ * As such, you won't be able to use the UART to USB converter on board and will
+ * require an external UART to USB converter. You could use the waveshare FT232
+ * USB UART Board (micro) but any 3.3V UART to USB converter will be fine.
+ *
+ * Fullspeed:
+ * If VBUS sense is enabled, ensure the PA9-VBUS jumper is connected on the core
+ * board. Connect the PB6 jumper for the LED and the Wakeup - PA0 jumper for the
+ * button. Connect the USB cable to the USB connector on the core board.
+ *
+ * High Speed:
+ * Remove all jumpers from the openh743i-c (especially the USART1 jumpers as the
+ * pins conflict). Connect the PB6 jumper for the LED and the Wakeup - PA0
+ * jumper for the button.
+ *
+ * The reset pin on the ULPI PMOD port is not connected to the MCU. You'll need
+ * to solder a wire from the RST pin on the USB3300 to a pin of your choosing on
+ * the openh743i-c board (this example assumes you've used PD14 as specified with
+ * the ULPI_RST_PORT and ULPI_RST_PIN defines below).
+ *
+ * Preferably power the board using the external 5VDC jack. Connect the USB cable
+ * to the USB connector on the ULPI board. Adjust delays in this file as required.
+ *
+ * If you're having trouble, ask a question on the tinyUSB Github Discussion boards.
+ *
+ * Have fun!
+ *
+*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_6
+#define LED_STATE_ON          1
+
+// Tamper push-button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE   1
+
+// Need to change jumper setting J7 and J8 from RS-232 to STLink
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOD
+#define UART_GPIO_AF          GPIO_AF7_USART3
+#define UART_TX_PIN           GPIO_PIN_8
+#define UART_RX_PIN           GPIO_PIN_9
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     0
+
+ // USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7
+#define ULPI_PINS \
+  {GPIOA, GPIO_PIN_3 }, {GPIOA, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_0 }, {GPIOB, GPIO_PIN_1 }, \
+  {GPIOB, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_10}, {GPIOB, GPIO_PIN_11}, {GPIOB, GPIO_PIN_12}, \
+  {GPIOB, GPIO_PIN_13}, {GPIOC, GPIO_PIN_0 }, {GPIOC, GPIO_PIN_2 }, {GPIOC, GPIO_PIN_3 }
+
+// ULPI PHY reset pin used by walkaround
+#define ULPI_RST_PORT GPIOD
+#define ULPI_RST_PIN GPIO_PIN_14
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32h7_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  // Supply configuration update enable
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+  // Configure the main internal regulator output voltage
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+  while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY))
+  {
+  }
+  // Macro to configure the PLL clock source
+  __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
+
+  // Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure.
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 2;
+  RCC_OscInitStruct.PLL.PLLN = 240;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_USART3;
+  PeriphClkInitStruct.PLL3.PLL3M = 8;
+  PeriphClkInitStruct.PLL3.PLL3N = 336;
+  PeriphClkInitStruct.PLL3.PLL3P = 2;
+  PeriphClkInitStruct.PLL3.PLL3Q = 7;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+  PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0;
+  PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL3;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  // Initializes the CPU, AHB and APB buses clocks
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  __HAL_RCC_CSI_ENABLE();
+
+  // Enable SYSCFG clock mondatory for I/O Compensation Cell
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  // Enables the I/O Compensation Cell
+  HAL_EnableCompensationCell();
+
+  // Enable voltage detector
+  HAL_PWREx_EnableUSBVoltageDetector();
+}
+
+static inline void timer_board_delay(TIM_HandleTypeDef* tim_hdl, uint32_t ms)
+{
+  uint32_t startMs = __HAL_TIM_GET_COUNTER(tim_hdl);
+  while ((__HAL_TIM_GET_COUNTER(tim_hdl) - startMs) < ms)
+  {
+    asm("nop"); //do nothing
+  }
+}
+
+static inline void board_stm32h7_post_init(void)
+{
+  // walkaround for reseting the ULPI PHY using Timer since systick is not
+  // available when RTOS is used.
+
+  // Init timer
+  TIM_HandleTypeDef tim2Handle;
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+
+  __HAL_RCC_TIM2_CLK_ENABLE();
+
+  //Assuming timer clock is running at 260Mhz this should configure the timer counter to 1000Hz
+  tim2Handle.Instance = TIM2;
+  tim2Handle.Init.Prescaler = 60000U - 1U;
+  tim2Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
+  tim2Handle.Init.Period = 0xFFFFFFFFU;
+  tim2Handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4;
+  tim2Handle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  HAL_TIM_Base_Init(&tim2Handle);
+
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  HAL_TIM_ConfigClockSource(&tim2Handle, &sClockSourceConfig);
+
+  //Start the timer
+  HAL_TIM_Base_Start(&tim2Handle);
+
+  // Reset PHY, change the delays as you see fit
+  timer_board_delay(&tim2Handle, 5U);
+  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 1U);
+  timer_board_delay(&tim2Handle, 20U);
+  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 0U);
+  timer_board_delay(&tim2Handle, 20U);
+
+  //Disable the timer used for delays
+  HAL_TIM_Base_Stop(&tim2Handle);
+  __HAL_RCC_TIM2_CLK_DISABLE();
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.mk b/hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.mk
new file mode 100644
index 000000000..4dfcc1cac
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.mk
@@ -0,0 +1,19 @@
+CFLAGS += -DSTM32H743xx -DHSE_VALUE=8000000
+
+# Default is HS port
+PORT ?= 1
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
+LD_FILE = $(BOARD_PATH)/STM32H743IITX_FLASH.ld
+
+# Use Timer module for ULPI PHY reset
+CFLAGS += -DHAL_TIM_MODULE_ENABLED
+SRC_C += \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim_ex.c
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h743ii
+
+# flash target using jlink
+flash: flash-jlink
\ No newline at end of file
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 2cbd87414..3e1ed9e84 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -75,13 +75,15 @@ void board_init(void)
   // Enable UART Clock
   UART_CLK_EN();
 
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+
 #endif
   
   GPIO_InitTypeDef  GPIO_InitStruct;
@@ -123,7 +125,7 @@ void board_init(void)
   // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
   // PA9 VUSB, PA10 ID, PA11 DM, PA12 DP
 
-  /* Configure DM DP Pins */
+  // Configure DM DP Pins
   GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -131,7 +133,7 @@ void board_init(void)
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
-  /* This for ID line debug */
+  // This for ID line debug
   GPIO_InitStruct.Pin = GPIO_PIN_10;
   GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
   GPIO_InitStruct.Pull = GPIO_PULLUP;
@@ -145,7 +147,7 @@ void board_init(void)
   __HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
 
 #if OTG_FS_VBUS_SENSE
-  /* Configure VBUS Pin */
+  // Configure VBUS Pin
   GPIO_InitStruct.Pin = GPIO_PIN_9;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
@@ -166,49 +168,23 @@ void board_init(void)
   // Despite being call USB2_OTG
   // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
 
-  /* CLK */
-  GPIO_InitStruct.Pin = GPIO_PIN_5;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+  struct {
+    GPIO_TypeDef* port;
+    uint32_t pin;
+  } const ulpi_pins[] =
+  {
+    ULPI_PINS
+  };
 
-  /* D0 */
-  GPIO_InitStruct.Pin = GPIO_PIN_3;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* D1 D2 D3 D4 D5 D6 D7 */
-  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_5 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-  /* STP */
-  GPIO_InitStruct.Pin = GPIO_PIN_0;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-  /* NXT */
-  GPIO_InitStruct.Pin = GPIO_PIN_4;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
-
-  /* DIR */
-  GPIO_InitStruct.Pin = GPIO_PIN_11;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+  for (uint8_t i=0; i < sizeof(ulpi_pins)/sizeof(ulpi_pins[0]); i++)
+  {
+    GPIO_InitStruct.Pin       = ulpi_pins[i].pin;
+    GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull      = GPIO_NOPULL;
+    GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
+    HAL_GPIO_Init(ulpi_pins[i].port, &GPIO_InitStruct);
+  }
 
   // Enable USB HS & ULPI Clocks
   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE();
@@ -230,6 +206,9 @@ void board_init(void)
   USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
 
   HAL_PWREx_EnableUSBVoltageDetector();
+
+  // For waveshare openh743 ULPI PHY reset walkaround
+  board_stm32h7_post_init();
 #endif // rhport = 1
 
 }
@@ -263,7 +242,7 @@ int board_uart_write(void const * buf, int len)
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
+void SysTick_Handler(void)
 {
   system_ticks++;
 }
@@ -274,7 +253,7 @@ uint32_t board_millis(void)
 }
 #endif
 
-void HardFault_Handler (void)
+void HardFault_Handler(void)
 {
   asm("bkpt");
 }

From 1992f49343fa7f5b73ae4e938a620e01900d2362 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 19 Aug 2021 18:02:16 +0700
Subject: [PATCH 0349/2085] group stm32f1 board

---
 hw/bsp/stm32f0/family.c                       |  5 +-
 .../stm32f103bluepill/STM32F103XB_FLASH.ld    |  0
 .../stm32f1/boards/stm32f103bluepill/board.h  | 92 +++++++++++++++++++
 .../stm32f1/boards/stm32f103bluepill/board.mk | 11 +++
 .../stm32f103bluepill.c => stm32f1/family.c}  | 78 ++++------------
 .../board.mk => stm32f1/family.mk}            | 14 +--
 .../stm32f1xx_hal_conf.h                      |  0
 7 files changed, 128 insertions(+), 72 deletions(-)
 rename hw/bsp/{ => stm32f1/boards}/stm32f103bluepill/STM32F103XB_FLASH.ld (100%)
 create mode 100644 hw/bsp/stm32f1/boards/stm32f103bluepill/board.h
 create mode 100644 hw/bsp/stm32f1/boards/stm32f103bluepill/board.mk
 rename hw/bsp/{stm32f103bluepill/stm32f103bluepill.c => stm32f1/family.c} (65%)
 rename hw/bsp/{stm32f103bluepill/board.mk => stm32f1/family.mk} (84%)
 rename hw/bsp/{stm32f103bluepill => stm32f1}/stm32f1xx_hal_conf.h (100%)

diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index b2e0453c5..853bb9d64 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -55,12 +55,13 @@ void board_init(void)
   // Enable UART Clock
   UART_CLK_EN();
 
+#if CFG_TUSB_OS  == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
   // LED
diff --git a/hw/bsp/stm32f103bluepill/STM32F103XB_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103bluepill/STM32F103XB_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32f103bluepill/STM32F103XB_FLASH.ld
rename to hw/bsp/stm32f1/boards/stm32f103bluepill/STM32F103XB_FLASH.ld
diff --git a/hw/bsp/stm32f1/boards/stm32f103bluepill/board.h b/hw/bsp/stm32f1/boards/stm32f103bluepill/board.h
new file mode 100644
index 000000000..57a607ed5
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103bluepill/board.h
@@ -0,0 +1,92 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOC
+#define LED_PIN               GPIO_PIN_13
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE   1
+
+// UART
+//#define UART_DEV              USART1
+//#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
+//#define UART_GPIO_PORT        GPIOA
+//#define UART_GPIO_AF          GPIO_AF1_USART1
+//#define UART_TX_PIN           GPIO_PIN_9
+//#define UART_RX_PIN           GPIO_PIN_10
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32f1_clock_init(void)
+{
+  RCC_ClkInitTypeDef clkinitstruct = {0};
+  RCC_OscInitTypeDef oscinitstruct = {0};
+  RCC_PeriphCLKInitTypeDef rccperiphclkinit = {0};
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  oscinitstruct.OscillatorType  = RCC_OSCILLATORTYPE_HSE;
+  oscinitstruct.HSEState        = RCC_HSE_ON;
+  oscinitstruct.HSEPredivValue  = RCC_HSE_PREDIV_DIV1;
+  oscinitstruct.PLL.PLLMUL      = RCC_PLL_MUL9;
+  oscinitstruct.PLL.PLLState    = RCC_PLL_ON;
+  oscinitstruct.PLL.PLLSource   = RCC_PLLSOURCE_HSE;
+  HAL_RCC_OscConfig(&oscinitstruct);
+
+  /* USB clock selection */
+  rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  rccperiphclkinit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+  HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  clkinitstruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  clkinitstruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  clkinitstruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  clkinitstruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  clkinitstruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&clkinitstruct, FLASH_LATENCY_2);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32f1/boards/stm32f103bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103bluepill/board.mk
new file mode 100644
index 000000000..1f8564c1a
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103bluepill/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32F103XB_FLASH.ld
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f103c8
+
+# flash target ROM bootloader
+flash: flash-dfu-util
diff --git a/hw/bsp/stm32f103bluepill/stm32f103bluepill.c b/hw/bsp/stm32f1/family.c
similarity index 65%
rename from hw/bsp/stm32f103bluepill/stm32f103bluepill.c
rename to hw/bsp/stm32f1/family.c
index 600f3aaef..d4ae098b2 100644
--- a/hw/bsp/stm32f103bluepill/stm32f103bluepill.c
+++ b/hw/bsp/stm32f1/family.c
@@ -24,8 +24,9 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
 #include "stm32f1xx_hal.h"
+#include "bsp/board.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
@@ -48,72 +49,29 @@ void USBWakeUp_IRQHandler(void)
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
-#define LED_PORT              GPIOC
-#define LED_PIN               GPIO_PIN_13
-#define LED_STATE_ON          0
-
-#define BUTTON_PORT           GPIOA
-#define BUTTON_PIN            GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE   1
-
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (HSE)
-  *            SYSCLK(Hz)                     = 72000000
-  *            HCLK(Hz)                       = 72000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 2
-  *            APB2 Prescaler                 = 1
-  *            HSE Frequency(Hz)              = 8000000
-  *            HSE PREDIV1                    = 1
-  *            PLLMUL                         = 9
-  *            Flash Latency(WS)              = 2
-  * @param  None
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef clkinitstruct = {0};
-  RCC_OscInitTypeDef oscinitstruct = {0};
-  RCC_PeriphCLKInitTypeDef rccperiphclkinit = {0};
-
-  /* Enable HSE Oscillator and activate PLL with HSE as source */
-  oscinitstruct.OscillatorType  = RCC_OSCILLATORTYPE_HSE;
-  oscinitstruct.HSEState        = RCC_HSE_ON;
-  oscinitstruct.HSEPredivValue  = RCC_HSE_PREDIV_DIV1;
-  oscinitstruct.PLL.PLLMUL      = RCC_PLL_MUL9;
-  oscinitstruct.PLL.PLLState    = RCC_PLL_ON;
-  oscinitstruct.PLL.PLLSource   = RCC_PLLSOURCE_HSE;
-  HAL_RCC_OscConfig(&oscinitstruct);
-
-  /* USB clock selection */
-  rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  rccperiphclkinit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
-  HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  clkinitstruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  clkinitstruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  clkinitstruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  clkinitstruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  clkinitstruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&clkinitstruct, FLASH_LATENCY_2);
-}
 
 void board_init(void)
 {
-
-  SystemClock_Config();
+  board_stm32f1_clock_init();
   
-  #if CFG_TUSB_OS  == OPT_OS_NONE
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
-  #endif
+
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_HP_CAN1_TX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
   
   // LED
-  __HAL_RCC_GPIOC_CLK_ENABLE();
   GPIO_InitTypeDef  GPIO_InitStruct;
   GPIO_InitStruct.Pin = LED_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@@ -122,7 +80,6 @@ void board_init(void)
   HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
 
   // Button
-  __HAL_RCC_GPIOA_CLK_ENABLE();
   GPIO_InitStruct.Pin = BUTTON_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_PULLDOWN;
@@ -131,7 +88,6 @@ void board_init(void)
 
   // USB Pins
   // Configure USB DM and DP pins.
-  __HAL_RCC_GPIOA_CLK_ENABLE();
   GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
diff --git a/hw/bsp/stm32f103bluepill/board.mk b/hw/bsp/stm32f1/family.mk
similarity index 84%
rename from hw/bsp/stm32f103bluepill/board.mk
rename to hw/bsp/stm32f1/family.mk
index 656a37323..aebd6d2ff 100644
--- a/hw/bsp/stm32f103bluepill/board.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -4,6 +4,8 @@ DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
+include $(TOP)/$(BOARD_PATH)/board.mk
+
 CFLAGS += \
   -flto \
   -mthumb \
@@ -11,15 +13,12 @@ CFLAGS += \
   -mcpu=cortex-m3 \
   -mfloat-abi=soft \
   -nostdlib -nostartfiles \
-  -DSTM32F103xB \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F1
 
 # mcu driver cause following warnings
 #CFLAGS += -Wno-error=unused-parameter
 
 # All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32F103XB_FLASH.ld
-
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
@@ -29,14 +28,11 @@ SRC_C += \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
-
 INC += \
+	$(TOP)/$(BOARD_PATH) \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
   $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc \
-  $(TOP)/hw/bsp/$(BOARD)
+  $(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM3
@@ -45,5 +41,5 @@ FREERTOS_PORT = ARM_CM3
 JLINK_DEVICE = stm32f103c8
 
 # flash target ROM bootloader
-flash: $(BUILD)/$(PROJECT).bin
+flash-dfu-util: $(BUILD)/$(PROJECT).bin
 	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
diff --git a/hw/bsp/stm32f103bluepill/stm32f1xx_hal_conf.h b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
similarity index 100%
rename from hw/bsp/stm32f103bluepill/stm32f1xx_hal_conf.h
rename to hw/bsp/stm32f1/stm32f1xx_hal_conf.h

From ebfd65a9ca438a9b0f8ad485c4825131cbb8efe8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 19 Aug 2021 18:51:51 +0700
Subject: [PATCH 0350/2085] add stm32f103 mini v2.0 board

---
 docs/reference/supported.rst                  |   5 +-
 .../stm32f103_mini_2/STM32F103XC_FLASH.ld     | 167 ++++++++++++++++++
 .../stm32f1/boards/stm32f103_mini_2/board.h   |  92 ++++++++++
 .../stm32f1/boards/stm32f103_mini_2/board.mk  |  11 ++
 ...32F103XB_FLASH.ld => STM32F103X8_FLASH.ld} |   2 +-
 .../stm32f1/boards/stm32f103bluepill/board.mk |   2 +-
 hw/bsp/stm32f1/family.c                       |   4 +-
 7 files changed, 277 insertions(+), 6 deletions(-)
 create mode 100644 hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
 create mode 100644 hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
 create mode 100644 hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
 rename hw/bsp/stm32f1/boards/stm32f103bluepill/{STM32F103XB_FLASH.ld => STM32F103X8_FLASH.ld} (98%)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 0028744f6..4c7d753c2 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -307,10 +307,11 @@ ST STM32
 -  `STM32 F070rb Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f070rb.html>`__
 -  `STM32 F072 Evaluation <https://www.st.com/en/evaluation-tools/stm32072b-eval.html>`__
 -  `STM32 F072rb Discovery <https://www.st.com/en/evaluation-tools/32f072bdiscovery.html>`__
--  STM32 F103c Blue Pill
+-  `STM32 F103c8 Blue Pill <https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill>`__
+-  `STM32 F103rc Mini v2.0 <https://stm32-base.org/boards/STM32F103RCT6-STM32-Mini-V2.0>`__
 -  `STM32 F207zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f207zg.html>`__
 -  `STM32 F303vc Discovery <https://www.st.com/en/evaluation-tools/stm32f3discovery.html>`__
--  STM32 F401cc Black Pill
+-  `STM32 F401cc Black Pill <https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2>`__
 -  `STM32 F407vg Discovery <https://www.st.com/en/evaluation-tools/stm32f4discovery.html>`__
 -  `STM32 F411ce Black Pill <https://www.adafruit.com/product/4877>`__
 -  `STM32 F411ve Discovery <https://www.st.com/en/evaluation-tools/32f411ediscovery.html>`__
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
new file mode 100644
index 000000000..da40d1eb2
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
@@ -0,0 +1,167 @@
+/*
+*****************************************************************************
+**
+**  File        : STM32F103XB_FLASH.ld
+**
+**  Abstract    : Linker script for STM32F103xB Device with
+**                128KByte FLASH, 20KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+**  (c)Copyright Ac6.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Ac6 permit registered System Workbench for MCU users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the System Workbench for MCU toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20004FFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 48K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
new file mode 100644
index 000000000..bedce7f14
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
@@ -0,0 +1,92 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_PIN_8
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE   1
+
+// UART
+//#define UART_DEV              USART1
+//#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
+//#define UART_GPIO_PORT        GPIOA
+//#define UART_GPIO_AF          GPIO_AF1_USART1
+//#define UART_TX_PIN           GPIO_PIN_9
+//#define UART_RX_PIN           GPIO_PIN_10
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32f1_clock_init(void)
+{
+  RCC_ClkInitTypeDef clkinitstruct = {0};
+  RCC_OscInitTypeDef oscinitstruct = {0};
+  RCC_PeriphCLKInitTypeDef rccperiphclkinit = {0};
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  oscinitstruct.OscillatorType  = RCC_OSCILLATORTYPE_HSE;
+  oscinitstruct.HSEState        = RCC_HSE_ON;
+  oscinitstruct.HSEPredivValue  = RCC_HSE_PREDIV_DIV1;
+  oscinitstruct.PLL.PLLMUL      = RCC_PLL_MUL9;
+  oscinitstruct.PLL.PLLState    = RCC_PLL_ON;
+  oscinitstruct.PLL.PLLSource   = RCC_PLLSOURCE_HSE;
+  HAL_RCC_OscConfig(&oscinitstruct);
+
+  /* USB clock selection */
+  rccperiphclkinit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  rccperiphclkinit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+  HAL_RCCEx_PeriphCLKConfig(&rccperiphclkinit);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+  clkinitstruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  clkinitstruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  clkinitstruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  clkinitstruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  clkinitstruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&clkinitstruct, FLASH_LATENCY_2);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
new file mode 100644
index 000000000..eeda87080
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32F103XC_FLASH.ld
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f103rc
+
+# flash target ROM bootloader
+flash: flash-jlink
diff --git a/hw/bsp/stm32f1/boards/stm32f103bluepill/STM32F103XB_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103bluepill/STM32F103X8_FLASH.ld
similarity index 98%
rename from hw/bsp/stm32f1/boards/stm32f103bluepill/STM32F103XB_FLASH.ld
rename to hw/bsp/stm32f1/boards/stm32f103bluepill/STM32F103X8_FLASH.ld
index 4be9df61b..ca1804905 100644
--- a/hw/bsp/stm32f1/boards/stm32f103bluepill/STM32F103XB_FLASH.ld
+++ b/hw/bsp/stm32f1/boards/stm32f103bluepill/STM32F103X8_FLASH.ld
@@ -41,7 +41,7 @@ _Min_Stack_Size = 0x400; /* required amount of stack */
 /* Specify the memory areas */
 MEMORY
 {
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 64K
 RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 20K
 }
 
diff --git a/hw/bsp/stm32f1/boards/stm32f103bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103bluepill/board.mk
index 1f8564c1a..9c690ca7e 100644
--- a/hw/bsp/stm32f1/boards/stm32f103bluepill/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103bluepill/board.mk
@@ -1,7 +1,7 @@
 CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
 
 # All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32F103XB_FLASH.ld
+LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
 
 # For flash-jlink target
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index d4ae098b2..8fcf9ebd6 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -75,14 +75,14 @@ void board_init(void)
   GPIO_InitTypeDef  GPIO_InitStruct;
   GPIO_InitStruct.Pin = LED_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Pull = LED_STATE_ON ? GPIO_PULLDOWN : GPIO_PULLUP;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
 
   // Button
   GPIO_InitStruct.Pin = BUTTON_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 

From 175a6fbc5ff5ab73344f52472d75f016d57b8a36 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 19 Aug 2021 18:53:55 +0700
Subject: [PATCH 0351/2085] rename to stm32f103_bluepill

---
 .../STM32F103X8_FLASH.ld                                          | 0
 .../boards/{stm32f103bluepill => stm32f103_bluepill}/board.h      | 0
 .../boards/{stm32f103bluepill => stm32f103_bluepill}/board.mk     | 0
 3 files changed, 0 insertions(+), 0 deletions(-)
 rename hw/bsp/stm32f1/boards/{stm32f103bluepill => stm32f103_bluepill}/STM32F103X8_FLASH.ld (100%)
 rename hw/bsp/stm32f1/boards/{stm32f103bluepill => stm32f103_bluepill}/board.h (100%)
 rename hw/bsp/stm32f1/boards/{stm32f103bluepill => stm32f103_bluepill}/board.mk (100%)

diff --git a/hw/bsp/stm32f1/boards/stm32f103bluepill/STM32F103X8_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32f1/boards/stm32f103bluepill/STM32F103X8_FLASH.ld
rename to hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
diff --git a/hw/bsp/stm32f1/boards/stm32f103bluepill/board.h b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
similarity index 100%
rename from hw/bsp/stm32f1/boards/stm32f103bluepill/board.h
rename to hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
diff --git a/hw/bsp/stm32f1/boards/stm32f103bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
similarity index 100%
rename from hw/bsp/stm32f1/boards/stm32f103bluepill/board.mk
rename to hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk

From 4b72ad9b9f78e8cec96d0fa17f3c0ec5e1989cc2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 19 Aug 2021 18:54:53 +0700
Subject: [PATCH 0352/2085] add f1 to ci build

---
 .github/workflows/build.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index fc5b92b68..8ef19b0a0 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -51,6 +51,7 @@ jobs:
         - 'samd51'
         - 'saml2x'
         - 'stm32f0'
+        - 'stm32f1'
         - 'stm32f4'
         - 'stm32f7'
         - 'stm32h7'

From eda5b92e92d8a3be0fb40d28c1772fcb62965856 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 19 Aug 2021 19:13:47 +0700
Subject: [PATCH 0353/2085] whitespace

---
 hw/bsp/stm32f1/family.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index aebd6d2ff..3fb2e6e70 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -29,7 +29,7 @@ SRC_C += \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
 INC += \
-	$(TOP)/$(BOARD_PATH) \
+  $(TOP)/$(BOARD_PATH) \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc

From 351581537f47a9cca84e1b4f13af704c0effaa78 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Tue, 17 Aug 2021 23:13:11 +0900
Subject: [PATCH 0354/2085] Removes redundant SOF processing from the Renesas
 RX family.

The same logic regarding the resume signal was implemented by usbd.

See also: #1023
---
 src/portable/renesas/usba/dcd_usba.c | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 1db1fdb32..cdc66079a 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -139,7 +139,6 @@ typedef struct
 {
   pipe_state_t pipe[10];
   uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
-  uint8_t suspended;
 } dcd_data_t;
 
 //--------------------------------------------------------------------+
@@ -815,20 +814,9 @@ void dcd_int_handler(uint8_t rhport)
   }
   if (is0 & USB_IS0_RESM) {
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-    _dcd.suspended = 0;
   }
   if (is0 & USB_IS0_SOFR) {
-    if (_dcd.suspended) {
-      /* When USB host resumes caused by `dcd_remote_wakeup()`,
-       * RESM interrupt does not rise.
-       * Therefore we need to manually send resume event.
-       * Of course, when USB host resumes on its own,
-       * RESM interrupt rise properly, then this statements are ignored. */
-      // TODO can be dropped since this logic is implemented by usbd
-      // USBD will exit suspended mode when SOF event is received
-      dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-      _dcd.suspended = 0;
-    }
+    // USBD will exit suspended mode when SOF event is received
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
   if (is0 & USB_IS0_DVST) {
@@ -844,7 +832,6 @@ void dcd_int_handler(uint8_t rhport)
     case USB_IS0_DVSQ_SUSP2:
     case USB_IS0_DVSQ_SUSP3:
        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-       _dcd.suspended = 1;
     default:
       break;
     }

From ff59e98a6ab29c70cdf743db7412ddb609e32730 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 19 Aug 2021 23:57:34 +0900
Subject: [PATCH 0355/2085] Add compile switch to enable SOF during suspend
 only

---
 src/portable/renesas/usba/dcd_usba.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index cdc66079a..095dcc136 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -27,6 +27,10 @@
 
 #include "tusb_option.h"
 
+// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
+// We disable SOF for now until needed later on
+#define USE_SOF     0
+
 #if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
                                  CFG_TUSB_MCU == OPT_MCU_RX65X || \
                                  CFG_TUSB_MCU == OPT_MCU_RX72N )
@@ -626,7 +630,7 @@ void dcd_init(uint8_t rhport)
   /* Setup default control pipe */
   USB0.DCPMAXP.BIT.MXPS  = 64;
   USB0.INTENB0.WORD = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP |
-    USB_IS0_DVST | USB_IS0_CTRT | USB_IS0_SOFR | USB_IS0_RESM;
+    USB_IS0_DVST | USB_IS0_CTRT | (USE_SOF ? USB_IS0_SOFR: 0) | USB_IS0_RESM;
   USB0.BEMPENB.WORD = 1;
   USB0.BRDYENB.WORD = 1;
 
@@ -814,10 +818,16 @@ void dcd_int_handler(uint8_t rhport)
   }
   if (is0 & USB_IS0_RESM) {
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+#if (0==USE_SOF)
+    USB0.INTENB0.BIT.SOFE = 0;
+#endif
   }
-  if (is0 & USB_IS0_SOFR) {
+  if ((is0 & USB_IS0_SOFR) && USB0.INTENB0.BIT.SOFE) {
     // USBD will exit suspended mode when SOF event is received
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+#if (0==USE_SOF)
+    USB0.INTENB0.BIT.SOFE = 0;
+#endif
   }
   if (is0 & USB_IS0_DVST) {
     switch (is0 & USB_IS0_DVSQ) {
@@ -832,6 +842,9 @@ void dcd_int_handler(uint8_t rhport)
     case USB_IS0_DVSQ_SUSP2:
     case USB_IS0_DVSQ_SUSP3:
        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+#if (0==USE_SOF)
+       USB0.INTENB0.BIT.SOFE = 1;
+#endif
     default:
       break;
     }

From 1cef2b6a42d93704847c1a6ab82617e5baf04f4a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 20 Aug 2021 18:01:10 +0700
Subject: [PATCH 0356/2085] extra common edpt helper for device and host stack

tu_edpt_validate() and tu_edpt_bind_driver()
---
 src/common/tusb_common.h    |  14 ++
 src/device/usbd.c           |  58 +------
 src/host/usbh.c             | 338 ++++++++++++++++++++----------------
 src/host/usbh_classdriver.h |   2 +
 src/tusb.c                  |  62 +++++++
 5 files changed, 265 insertions(+), 209 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index c8a66a879..302e75277 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -73,6 +73,20 @@
 #include "tusb_error.h"   // TODO remove
 #include "tusb_timeout.h" // TODO remove
 
+//--------------------------------------------------------------------+
+// Internal Helper used by Host and Device Stack
+//--------------------------------------------------------------------+
+
+// Check if endpoint descriptor is valid per USB specs
+bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed);
+
+// Bind all endpoint of a interface descriptor to class driver
+void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
+
+//--------------------------------------------------------------------+
+// Internal Inline Functions
+//--------------------------------------------------------------------+
+
 //------------- Mem -------------//
 #define tu_memclr(buffer, size)  memset((buffer), 0, (size))
 #define tu_varclr(_var)          tu_memclr(_var, sizeof(*(_var)))
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 8b4f4e7e3..23f174dab 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -274,7 +274,6 @@ static osal_mutex_t _usbd_mutex;
 //--------------------------------------------------------------------+
 // Prototypes
 //--------------------------------------------------------------------+
-static void mark_interface_endpoint(uint8_t ep2drv[][2], uint8_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
 static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request);
 static bool process_set_config(uint8_t rhport, uint8_t cfg_num);
 static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const * p_request);
@@ -901,7 +900,8 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
           }
         }
 
-        mark_interface_endpoint(_usbd_dev.ep2drv, p_desc, drv_len, drv_id); // TODO refactor
+        // bind all endpoints for this driver
+        tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id);
 
         p_desc += drv_len; // next interface
 
@@ -919,25 +919,6 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
   return true;
 }
 
-// Helper marking endpoint of interface belongs to class driver
-static void mark_interface_endpoint(uint8_t ep2drv[][2], uint8_t const* p_desc, uint16_t desc_len, uint8_t driver_id)
-{
-  uint16_t len = 0;
-
-  while( len < desc_len )
-  {
-    if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
-    {
-      uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
-
-      ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id;
-    }
-
-    len   = (uint16_t)(len + tu_desc_len(p_desc));
-    p_desc = tu_desc_next(p_desc);
-  }
-}
-
 // return descriptor's buffer and update desc_len
 static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const * p_request)
 {
@@ -1177,41 +1158,8 @@ void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr)
 
 bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
 {
-  uint16_t const max_packet_size = tu_le16toh(desc_ep->wMaxPacketSize.size);
-
-  TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size);
   TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX);
-
-  switch (desc_ep->bmAttributes.xfer)
-  {
-    case TUSB_XFER_ISOCHRONOUS:
-    {
-      uint16_t const spec_size = (_usbd_dev.speed == TUSB_SPEED_HIGH ? 1024 : 1023);
-      TU_ASSERT(max_packet_size <= spec_size);
-    }
-    break;
-
-    case TUSB_XFER_BULK:
-      if (_usbd_dev.speed == TUSB_SPEED_HIGH)
-      {
-        // Bulk highspeed must be EXACTLY 512
-        TU_ASSERT(max_packet_size == 512);
-      }else
-      {
-        // TODO Bulk fullspeed can only be 8, 16, 32, 64
-        TU_ASSERT(max_packet_size <= 64);
-      }
-    break;
-
-    case TUSB_XFER_INTERRUPT:
-    {
-      uint16_t const spec_size = (_usbd_dev.speed == TUSB_SPEED_HIGH ? 1024 : 64);
-      TU_ASSERT(max_packet_size <= spec_size);
-    }
-    break;
-
-    default: return false;
-  }
+  TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
 
   return dcd_edpt_open(rhport, desc_ep);
 }
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 93621c42a..36c2ea7c8 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -28,16 +28,23 @@
 
 #if TUSB_OPT_HOST_ENABLED
 
-#ifndef CFG_TUH_TASK_QUEUE_SZ
-#define CFG_TUH_TASK_QUEUE_SZ   16
-#endif
-
 #include "tusb.h"
 #include "host/usbh.h"
 #include "host/usbh_classdriver.h"
 #include "hub.h"
 #include "usbh_hcd.h"
 
+//--------------------------------------------------------------------+
+// USBH Configuration
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUH_TASK_QUEUE_SZ
+#define CFG_TUH_TASK_QUEUE_SZ   16
+#endif
+
+// Debug level of USBD
+#define USBH_DBG_LVL   2
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -135,6 +142,7 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_EN
 //------------- Helper Function Prototypes -------------//
 static bool enum_new_device(hcd_event_t* event);
 static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port);
+static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
 
 // from usbh_control.c
 extern bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
@@ -314,151 +322,6 @@ uint8_t* usbh_get_enum_buf(void)
   return _usbh_ctrl_buf;
 }
 
-//--------------------------------------------------------------------+
-// Endpoint API
-//--------------------------------------------------------------------+
-
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
-
-#if CFG_TUSB_OS != OPT_OS_NONE
-  // pre-check to help reducing mutex lock
-  TU_VERIFY((dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 0));
-  osal_mutex_lock(dev->mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-#endif
-
-  // can only claim the endpoint if it is not busy and not claimed yet.
-  bool const ret = (dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 0);
-  if (ret)
-  {
-    dev->ep_status[epnum][dir].claimed = 1;
-  }
-
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_unlock(dev->mutex);
-#endif
-
-  return ret;
-}
-
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
-
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_lock(dev->mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-#endif
-
-  // can only release the endpoint if it is claimed and not busy
-  bool const ret = (dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 1);
-  if (ret)
-  {
-    dev->ep_status[epnum][dir].claimed = 0;
-  }
-
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_unlock(dev->mutex);
-#endif
-
-  return ret;
-}
-
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
-
-  TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
-
-  // Attempt to transfer on a busy endpoint, sound like an race condition !
-  TU_ASSERT(dev->ep_status[epnum][dir].busy == 0);
-
-  // Set busy first since the actual transfer can be complete before hcd_edpt_xfer()
-  // could return and USBH task can preempt and clear the busy
-  dev->ep_status[epnum][dir].busy = true;
-
-  if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
-  {
-    TU_LOG2("OK\r\n");
-    return true;
-  }else
-  {
-    // HCD error, mark endpoint as ready to allow next transfer
-    dev->ep_status[epnum][dir].busy = false;
-    dev->ep_status[epnum][dir].claimed = 0;
-    TU_LOG2("failed\r\n");
-    TU_BREAKPOINT();
-    return false;
-  }
-}
-
-bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
-{
-  TU_LOG2("Open EP Control with Size = %u\r\n", max_packet_size);
-
-  tusb_desc_endpoint_t ep0_desc =
-  {
-    .bLength          = sizeof(tusb_desc_endpoint_t),
-    .bDescriptorType  = TUSB_DESC_ENDPOINT,
-    .bEndpointAddress = 0,
-    .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-    .wMaxPacketSize   = { .size = max_packet_size },
-    .bInterval        = 0
-  };
-
-  return hcd_edpt_open(_usbh_devices[dev_addr].rhport, dev_addr, &ep0_desc);
-}
-
-bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
-{
-  TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, desc_ep->wMaxPacketSize.size);
-
-  bool ret = hcd_edpt_open(rhport, dev_addr, desc_ep);
-
-  if (ret)
-  {
-    usbh_device_t* dev = &_usbh_devices[dev_addr];
-
-    // new endpoints belongs to latest interface (last valid value)
-    // TODO FIXME not true with ISO
-    uint8_t drvid = 0xff;
-    for(uint8_t i=0; i < sizeof(dev->itf2drv); i++)
-    {
-      if ( dev->itf2drv[i] == 0xff ) break;
-      drvid = dev->itf2drv[i];
-    }
-    TU_ASSERT(drvid < USBH_CLASS_DRIVER_COUNT);
-
-    uint8_t const ep_addr = desc_ep->bEndpointAddress;
-    dev->ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = drvid;
-  }
-
-  return ret;
-}
-
-bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
-
-  return dev->ep_status[epnum][dir].busy;
-}
-
-
 //--------------------------------------------------------------------+
 // HCD Event Handler
 //--------------------------------------------------------------------+
@@ -841,7 +704,7 @@ static bool enum_set_address_complete(uint8_t dev_addr, tusb_control_request_t c
   dev0->state = TUSB_DEVICE_STATE_UNPLUG;
 
   // open control pipe for new address
-  TU_ASSERT ( usbh_edpt_control_open(new_addr, new_dev->ep0_packet_size) );
+  TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_packet_size) );
 
   // Get full device descriptor
   TU_LOG2("Get Device Descriptor\r\n");
@@ -981,6 +844,34 @@ static bool enum_set_config_complete(uint8_t dev_addr, tusb_control_request_t co
   return true;
 }
 
+// Get total length of n interface (depending on IAD)
+static uint16_t get_interface_length(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len)
+{
+  uint8_t const* p_desc = (uint8_t const*) desc_itf;
+  uint16_t len = 0;
+
+  while (itf_count--)
+  {
+    // Next on interface desc
+    len += tu_desc_len(desc_itf);
+    p_desc = tu_desc_next(p_desc);
+
+    while (len < max_len)
+    {
+      // return on IAD regardless of itf count
+      if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len;
+
+      if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
+          ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 ) break;
+
+      len += tu_desc_len(p_desc);
+      p_desc = tu_desc_next(p_desc);
+    }
+  }
+
+  return len;
+}
+
 static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
 {
   usbh_device_t* dev = &_usbh_devices[dev_addr];
@@ -992,20 +883,25 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
   while( p_desc < desc_end )
   {
     // TODO Do we need to use IAD
-    // tusb_desc_interface_assoc_t const * desc_itf_assoc = NULL;
+     tusb_desc_interface_assoc_t const * desc_iad = NULL;
 
     // Class will always starts with Interface Association (if any) and then Interface descriptor
     if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
     {
-      // desc_itf_assoc = (tusb_desc_interface_assoc_t const *) p_desc;
+      desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
       p_desc = tu_desc_next(p_desc);
     }
 
+    TU_LOG_INT(2, p_desc - (uint8_t*) desc_cfg);
+    TU_LOG_INT(2, tu_desc_type(p_desc));
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
 
     tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
     uint16_t const remaining_len = desc_end-p_desc;
 
+    uint16_t const drv_len = get_interface_length(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, remaining_len);
+    TU_ASSERT(drv_len);
+
     // Check if class is supported TODO drop class_code
     uint8_t drv_id;
     for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
@@ -1015,8 +911,11 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
 
     if( drv_id >= USBH_CLASS_DRIVER_COUNT )
     {
-      // skip unsupported class
-      p_desc = tu_desc_next(p_desc);
+      TU_LOG(USBH_DBG_LVL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+             desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
+
+      // skip unsupported class until next Interface or IAD descriptor
+      p_desc += drv_len;
     }
     else
     {
@@ -1038,6 +937,10 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
 
         uint16_t const itf_len = driver->open(dev->rhport, dev_addr, desc_itf, remaining_len);
         TU_ASSERT( sizeof(tusb_desc_interface_t) <= itf_len && itf_len <= remaining_len);
+
+        // bind all endpoints for this driver
+        tu_edpt_bind_driver(dev->ep2drv, desc_itf, drv_len, drv_id);
+
         p_desc += itf_len;
       }
     }
@@ -1046,4 +949,131 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
   return true;
 }
 
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  usbh_device_t* dev = &_usbh_devices[dev_addr];
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+  // pre-check to help reducing mutex lock
+  TU_VERIFY((dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 0));
+  osal_mutex_lock(dev->mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+#endif
+
+  // can only claim the endpoint if it is not busy and not claimed yet.
+  bool const ret = (dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 0);
+  if (ret)
+  {
+    dev->ep_status[epnum][dir].claimed = 1;
+  }
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+  osal_mutex_unlock(dev->mutex);
+#endif
+
+  return ret;
+}
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  usbh_device_t* dev = &_usbh_devices[dev_addr];
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+  osal_mutex_lock(dev->mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+#endif
+
+  // can only release the endpoint if it is claimed and not busy
+  bool const ret = (dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 1);
+  if (ret)
+  {
+    dev->ep_status[epnum][dir].claimed = 0;
+  }
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+  osal_mutex_unlock(dev->mutex);
+#endif
+
+  return ret;
+}
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  usbh_device_t* dev = &_usbh_devices[dev_addr];
+
+  TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
+
+  // Attempt to transfer on a busy endpoint, sound like an race condition !
+  TU_ASSERT(dev->ep_status[epnum][dir].busy == 0);
+
+  // Set busy first since the actual transfer can be complete before hcd_edpt_xfer()
+  // could return and USBH task can preempt and clear the busy
+  dev->ep_status[epnum][dir].busy = true;
+
+  if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
+  {
+    TU_LOG2("OK\r\n");
+    return true;
+  }else
+  {
+    // HCD error, mark endpoint as ready to allow next transfer
+    dev->ep_status[epnum][dir].busy = false;
+    dev->ep_status[epnum][dir].claimed = 0;
+    TU_LOG2("failed\r\n");
+    TU_BREAKPOINT();
+    return false;
+  }
+}
+
+static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
+{
+  TU_LOG2("Open EP Control with Size = %u\r\n", max_packet_size);
+
+  tusb_desc_endpoint_t ep0_desc =
+  {
+    .bLength          = sizeof(tusb_desc_endpoint_t),
+    .bDescriptorType  = TUSB_DESC_ENDPOINT,
+    .bEndpointAddress = 0,
+    .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
+    .wMaxPacketSize   = { .size = max_packet_size },
+    .bInterval        = 0
+  };
+
+  return hcd_edpt_open(_usbh_devices[dev_addr].rhport, dev_addr, &ep0_desc);
+}
+
+bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
+{
+  usbh_device_t* dev = &_usbh_devices[dev_addr];
+  TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) dev->speed));
+
+  return hcd_edpt_open(rhport, dev_addr, desc_ep);
+}
+
+bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  usbh_device_t* dev = &_usbh_devices[dev_addr];
+
+  return dev->ep_status[epnum][dir].busy;
+}
+
+
+
 #endif
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index 0736fefa1..b05a33580 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -73,6 +73,8 @@ bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_
 // If caller does not make any transfer, it must release endpoint for others.
 bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
 
+bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr);
+
 // Check if endpoint transferring is complete
 bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
 
diff --git a/src/tusb.c b/src/tusb.c
index 0350fa1de..260a6506f 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -63,6 +63,68 @@ bool tusb_inited(void)
   return ret;
 }
 
+//--------------------------------------------------------------------+
+// Internal Helper for both Host and Device stack
+//--------------------------------------------------------------------+
+
+bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed)
+{
+  uint16_t const max_packet_size = tu_le16toh(desc_ep->wMaxPacketSize.size);
+  TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size);
+
+  switch (desc_ep->bmAttributes.xfer)
+  {
+    case TUSB_XFER_ISOCHRONOUS:
+    {
+      uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 1023);
+      TU_ASSERT(max_packet_size <= spec_size);
+    }
+    break;
+
+    case TUSB_XFER_BULK:
+      if (speed == TUSB_SPEED_HIGH)
+      {
+        // Bulk highspeed must be EXACTLY 512
+        TU_ASSERT(max_packet_size == 512);
+      }else
+      {
+        // TODO Bulk fullspeed can only be 8, 16, 32, 64
+        TU_ASSERT(max_packet_size <= 64);
+      }
+    break;
+
+    case TUSB_XFER_INTERRUPT:
+    {
+      uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64);
+      TU_ASSERT(max_packet_size <= spec_size);
+    }
+    break;
+
+    default: return false;
+  }
+
+  return true;
+}
+
+void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id)
+{
+  uint8_t const* p_desc = (uint8_t const*) desc_itf;
+  uint16_t len = 0;
+
+  while( len < desc_len )
+  {
+    if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
+    {
+      uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
+
+      ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id;
+    }
+
+    len   = (uint16_t)(len + tu_desc_len(p_desc));
+    p_desc = tu_desc_next(p_desc);
+  }
+}
+
 /*------------------------------------------------------------------*/
 /* Debug
  *------------------------------------------------------------------*/

From 62f2efbe8cf1e61f70660abac28f4226bca93daf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 20 Aug 2021 18:26:56 +0700
Subject: [PATCH 0357/2085] hid host skip get report descriptor if too large
 instead of assert

---
 examples/host/cdc_msc_hid/src/hid_app.c |  2 +
 src/class/hid/hid_host.c                | 62 ++++++++++++++++---------
 src/class/hid/hid_host.h                |  2 +
 src/host/usbh.c                         |  2 -
 4 files changed, 43 insertions(+), 25 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index 420600f9a..5e3ac6a72 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -61,6 +61,8 @@ void hid_app_task(void)
 // Invoked when device with hid interface is mounted
 // Report descriptor is also available for use. tuh_hid_parse_report_descriptor()
 // can be used to parse common/simple enough descriptor.
+// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
+// therefore report_desc = NULL, desc_len = 0
 void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
 {
   printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance);
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 40b6f5631..a39ac8bec 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -247,6 +247,8 @@ static bool config_set_protocol             (uint8_t dev_addr, tusb_control_requ
 static bool config_get_report_desc          (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 static bool config_get_report_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 
+static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
+
 uint16_t hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
   (void) max_len;
@@ -367,26 +369,34 @@ static bool config_get_report_desc(uint8_t dev_addr, tusb_control_request_t cons
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
-  // Get Report Descriptor
+  // Get Report Descriptor if possible
   // using usbh enumeration buffer since report descriptor can be very long
-  TU_ASSERT( hid_itf->report_desc_len <= CFG_TUH_ENUMERATION_BUFSIZE );
-
-  TU_LOG2("HID Get Report Descriptor\r\n");
-  tusb_control_request_t const new_request =
+  if( hid_itf->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE )
   {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
-    },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = tu_u16(hid_itf->report_desc_type, 0),
-    .wIndex   = itf_num,
-    .wLength  = hid_itf->report_desc_len
-  };
+    TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", hid_itf->report_desc_len);
+
+    // Driver is mounted without report descriptor
+    config_driver_mount_complete(dev_addr, instance, NULL, 0);
+  }else
+  {
+    TU_LOG2("HID Get Report Descriptor\r\n");
+    tusb_control_request_t const new_request =
+    {
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_STANDARD,
+        .direction = TUSB_DIR_IN
+      },
+      .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+      .wValue   = tu_u16(hid_itf->report_desc_type, 0),
+      .wIndex   = itf_num,
+      .wLength  = hid_itf->report_desc_len
+    };
+
+    TU_ASSERT(tuh_control_xfer(dev_addr, &new_request, usbh_get_enum_buf(), config_get_report_desc_complete));
+  }
 
-  TU_ASSERT(tuh_control_xfer(dev_addr, &new_request, usbh_get_enum_buf(), config_get_report_desc_complete));
   return true;
 }
 
@@ -394,13 +404,21 @@ static bool config_get_report_desc_complete(uint8_t dev_addr, tusb_control_reque
 {
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
-  uint8_t const itf_num     = (uint8_t) request->wIndex;
-  uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  uint8_t const itf_num      = (uint8_t) request->wIndex;
+  uint8_t const instance     = get_instance_id_by_itfnum(dev_addr, itf_num);
 
   uint8_t const* desc_report = usbh_get_enum_buf();
   uint16_t const desc_len    = request->wLength;
 
+  config_driver_mount_complete(dev_addr, instance, desc_report, desc_len);
+
+  return true;
+}
+
+static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
+{
+  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+
   // enumeration is complete
   tuh_hid_mount_cb(dev_addr, instance, desc_report, desc_len);
 
@@ -408,9 +426,7 @@ static bool config_get_report_desc_complete(uint8_t dev_addr, tusb_control_reque
   hidh_get_report(dev_addr, hid_itf);
 
   // notify usbh that driver enumeration is complete
-  usbh_driver_set_config_complete(dev_addr, itf_num);
-
-  return true;
+  usbh_driver_set_config_complete(dev_addr, hid_itf->itf_num);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index ef203123d..bbef05e25 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -97,6 +97,8 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr,
 // Invoked when device with hid interface is mounted
 // Report descriptor is also available for use. tuh_hid_parse_report_descriptor()
 // can be used to parse common/simple enough descriptor.
+// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
+// therefore report_desc = NULL, desc_len = 0
 void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report_desc, uint16_t desc_len);
 
 // Invoked when device with hid interface is un-mounted
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 36c2ea7c8..979fc5065 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -892,8 +892,6 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
       p_desc = tu_desc_next(p_desc);
     }
 
-    TU_LOG_INT(2, p_desc - (uint8_t*) desc_cfg);
-    TU_LOG_INT(2, tu_desc_type(p_desc));
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
 
     tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;

From 97703587d9f306f01a9435c1515a585f1b8d0975 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 20 Aug 2021 19:08:38 +0700
Subject: [PATCH 0358/2085] improve host configuration parsing

- remove driver class code binding
- fully support IAD
- auto calculate total length for interface descriptor for driver
---
 src/common/tusb_common.h    |   3 +
 src/host/usbh.c             | 135 ++++++++++++++++--------------------
 src/host/usbh_classdriver.h |   2 -
 src/host/usbh_hcd.h         |   4 +-
 src/tusb.c                  |  30 ++++++++
 5 files changed, 93 insertions(+), 81 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 302e75277..c2356ffee 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -83,6 +83,9 @@ bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed);
 // Bind all endpoint of a interface descriptor to class driver
 void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
 
+// Calculate total length of n interfaces (depending on IAD)
+uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len);
+
 //--------------------------------------------------------------------+
 // Internal Inline Functions
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 979fc5065..662ce2673 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -48,6 +48,10 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
+
+// Invalid driver ID in itf2drv[] ep2drv[][] mapping
+enum { DRVID_INVALID = 0xFFu };
+
 #if CFG_TUSB_DEBUG >= 2
   #define DRIVER_NAME(_name)    .name = _name,
 #else
@@ -59,7 +63,6 @@ static usbh_class_driver_t const usbh_class_drivers[] =
   #if CFG_TUH_CDC
     {
       DRIVER_NAME("CDC")
-      .class_code = TUSB_CLASS_CDC,
       .init       = cdch_init,
       .open       = cdch_open,
       .set_config = cdch_set_config,
@@ -71,7 +74,6 @@ static usbh_class_driver_t const usbh_class_drivers[] =
   #if CFG_TUH_MSC
     {
       DRIVER_NAME("MSC")
-      .class_code = TUSB_CLASS_MSC,
       .init       = msch_init,
       .open       = msch_open,
       .set_config = msch_set_config,
@@ -83,7 +85,6 @@ static usbh_class_driver_t const usbh_class_drivers[] =
   #if CFG_TUH_HID
     {
       DRIVER_NAME("HID")
-      .class_code = TUSB_CLASS_HID,
       .init       = hidh_init,
       .open       = hidh_open,
       .set_config = hidh_set_config,
@@ -95,7 +96,6 @@ static usbh_class_driver_t const usbh_class_drivers[] =
   #if CFG_TUH_HUB
     {
       DRIVER_NAME("HUB")
-      .class_code = TUSB_CLASS_HUB,
       .init       = hub_init,
       .open       = hub_open,
       .set_config = hub_set_config,
@@ -107,7 +107,6 @@ static usbh_class_driver_t const usbh_class_drivers[] =
   #if CFG_TUH_VENDOR
     {
       DRIVER_NAME("VENDOR")
-      .class_code = TUSB_CLASS_VENDOR_SPECIFIC,
       .init       = cush_init,
       .open       = cush_open_subtask,
       .xfer_cb    = cush_isr,
@@ -203,8 +202,8 @@ bool tuh_init(uint8_t rhport)
     TU_ASSERT(dev->mutex);
 #endif
 
-    memset(dev->itf2drv, 0xff, sizeof(dev->itf2drv)); // invalid mapping
-    memset(dev->ep2drv , 0xff, sizeof(dev->ep2drv )); // invalid mapping
+    memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
+    memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
   }
 
   // Class drivers init
@@ -336,7 +335,6 @@ void hcd_event_handler(hcd_event_t const* event, bool in_isr)
   }
 }
 
-// interrupt caused by a TD (with IOC=1) in pipe of class class_code
 void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
 {
   hcd_event_t event =
@@ -409,8 +407,8 @@ void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port
         usbh_class_drivers[drv_id].close(dev_addr);
       }
 
-      memset(dev->itf2drv, 0xff, sizeof(dev->itf2drv)); // invalid mapping
-      memset(dev->ep2drv , 0xff, sizeof(dev->ep2drv )); // invalid mapping
+      memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
+      memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
 
       hcd_device_close(rhport, dev_addr);
 
@@ -439,7 +437,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
   {
     // continue with next valid interface
     uint8_t const drv_id = dev->itf2drv[itf_num];
-    if (drv_id != 0xff)
+    if (drv_id != DRVID_INVALID)
     {
       usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
       TU_LOG2("%s set config: itf = %u\r\n", driver->name, itf_num);
@@ -835,43 +833,15 @@ static bool enum_set_config_complete(uint8_t dev_addr, tusb_control_request_t co
   dev->configured = 1;
   dev->state = TUSB_DEVICE_STATE_CONFIGURED;
 
-  // Start the Set Configuration process for interfaces (itf = 0xff)
+  // Start the Set Configuration process for interfaces (itf = DRVID_INVALID)
   // Since driver can perform control transfer within its set_config, this is done asynchronously.
   // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete()
-  // TODO use separated API instead of usig 0xff
-  usbh_driver_set_config_complete(dev_addr, 0xff);
+  // TODO use separated API instead of using DRVID_INVALID
+  usbh_driver_set_config_complete(dev_addr, DRVID_INVALID);
 
   return true;
 }
 
-// Get total length of n interface (depending on IAD)
-static uint16_t get_interface_length(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len)
-{
-  uint8_t const* p_desc = (uint8_t const*) desc_itf;
-  uint16_t len = 0;
-
-  while (itf_count--)
-  {
-    // Next on interface desc
-    len += tu_desc_len(desc_itf);
-    p_desc = tu_desc_next(p_desc);
-
-    while (len < max_len)
-    {
-      // return on IAD regardless of itf count
-      if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len;
-
-      if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
-          ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 ) break;
-
-      len += tu_desc_len(p_desc);
-      p_desc = tu_desc_next(p_desc);
-    }
-  }
-
-  return len;
-}
-
 static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
 {
   usbh_device_t* dev = &_usbh_devices[dev_addr];
@@ -895,53 +865,64 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
 
     tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
-    uint16_t const remaining_len = desc_end-p_desc;
 
-    uint16_t const drv_len = get_interface_length(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, remaining_len);
+    // Interface number must not be used already
+    TU_ASSERT( dev->itf2drv[desc_itf->bInterfaceNumber] == DRVID_INVALID );
+
+    uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, desc_end-p_desc);
     TU_ASSERT(drv_len);
 
-    // Check if class is supported TODO drop class_code
-    uint8_t drv_id;
-    for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+    if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && dev->hub_addr != 0)
     {
-      if ( usbh_class_drivers[drv_id].class_code == desc_itf->bInterfaceClass ) break;
-    }
-
-    if( drv_id >= USBH_CLASS_DRIVER_COUNT )
-    {
-      TU_LOG(USBH_DBG_LVL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
-             desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
-
-      // skip unsupported class until next Interface or IAD descriptor
-      p_desc += drv_len;
+      // TODO Attach hub to Hub is not currently supported
+      // skip this interface
+      TU_LOG(USBH_DBG_LVL, "Only 1 level of HUB is supported\r\n");
     }
     else
     {
-      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
-
-      // Interface number must not be used already TODO alternate interface
-      TU_ASSERT( dev->itf2drv[desc_itf->bInterfaceNumber] == 0xff );
-      dev->itf2drv[desc_itf->bInterfaceNumber] = drv_id;
-
-      if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && dev->hub_addr != 0)
+      // Find driver for this interface
+      uint8_t drv_id;
+      for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
       {
-        // TODO Attach hub to Hub is not currently supported
-        // skip this interface
-        p_desc = tu_desc_next(p_desc);
+        usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+
+        if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
+        {
+          // open successfully
+          TU_LOG2("%s opened\r\n", driver->name);
+
+          // bind interface to found driver
+          dev->itf2drv[desc_itf->bInterfaceNumber] = drv_id;
+
+          // If using IAD, bind all interfaces to the same driver
+          if (desc_iad)
+          {
+            // IAD's first interface number and class should match with opened interface
+            TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber &&
+                      desc_iad->bFunctionClass  == desc_itf->bInterfaceClass);
+
+            for(uint8_t i=1; i<desc_iad->bInterfaceCount; i++)
+            {
+              dev->itf2drv[desc_itf->bInterfaceNumber+i] = drv_id;
+            }
+          }
+
+          // bind all endpoints to found driver
+          tu_edpt_bind_driver(dev->ep2drv, desc_itf, drv_len, drv_id);
+
+          break; // exit driver find loop
+        }
       }
-      else
+
+      if( drv_id >= USBH_CLASS_DRIVER_COUNT )
       {
-        TU_LOG2("%s open\r\n", driver->name);
-
-        uint16_t const itf_len = driver->open(dev->rhport, dev_addr, desc_itf, remaining_len);
-        TU_ASSERT( sizeof(tusb_desc_interface_t) <= itf_len && itf_len <= remaining_len);
-
-        // bind all endpoints for this driver
-        tu_edpt_bind_driver(dev->ep2drv, desc_itf, drv_len, drv_id);
-
-        p_desc += itf_len;
+        TU_LOG(USBH_DBG_LVL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+               desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
       }
     }
+
+    // next Interface or IAD descriptor
+    p_desc += drv_len;
   }
 
   return true;
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index b05a33580..fccb30253 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -43,8 +43,6 @@ typedef struct {
   char const* name;
   #endif
 
-  uint8_t class_code;
-
   void     (* const init       )(void);
   uint16_t (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
   bool     (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
diff --git a/src/host/usbh_hcd.h b/src/host/usbh_hcd.h
index b3856d6b7..450b3e447 100644
--- a/src/host/usbh_hcd.h
+++ b/src/host/usbh_hcd.h
@@ -73,9 +73,9 @@ typedef struct {
     uint8_t suspended    : 1;
   };
 
-  volatile uint8_t state;             // device state, value from enum tusbh_device_state_t
+  volatile uint8_t state;            // device state, value from enum tusbh_device_state_t
 
-  uint8_t itf2drv[16];  // map interface number to driver (0xff is invalid)
+  uint8_t itf2drv[16];               // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUH_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid )
 
   struct TU_ATTR_PACKED
diff --git a/src/tusb.c b/src/tusb.c
index 260a6506f..1fc775399 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -125,6 +125,36 @@ void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_
   }
 }
 
+uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len)
+{
+  uint8_t const* p_desc = (uint8_t const*) desc_itf;
+  uint16_t len = 0;
+
+  while (itf_count--)
+  {
+    // Next on interface desc
+    len += tu_desc_len(desc_itf);
+    p_desc = tu_desc_next(p_desc);
+
+    while (len < max_len)
+    {
+      // return on IAD regardless of itf count
+      if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len;
+
+      if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
+           ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 )
+      {
+        break;
+      }
+
+      len += tu_desc_len(p_desc);
+      p_desc = tu_desc_next(p_desc);
+    }
+  }
+
+  return len;
+}
+
 /*------------------------------------------------------------------*/
 /* Debug
  *------------------------------------------------------------------*/

From 22a5b1608c0949d46f8e346878bff730712858e4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 20 Aug 2021 19:31:38 +0700
Subject: [PATCH 0359/2085] change host driver open return type to bool

the descriptor len used by driver will be calculated by usbh
---
 src/class/cdc/cdc_host.c    | 12 ++++++------
 src/class/cdc/cdc_host.h    | 10 +++++-----
 src/class/hid/hid_host.c    | 20 ++++++++++----------
 src/class/hid/hid_host.h    | 10 +++++-----
 src/class/msc/msc_host.c    | 10 +++++-----
 src/class/msc/msc_host.h    | 10 +++++-----
 src/host/hub.c              | 13 +++++++------
 src/host/hub.h              | 10 +++++-----
 src/host/usbh_classdriver.h | 10 +++++-----
 9 files changed, 53 insertions(+), 52 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index fc7100e81..35b8de3b1 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -149,7 +149,7 @@ void cdch_init(void)
   tu_memclr(cdch_data, sizeof(cdch_data_t)*CFG_TUSB_HOST_DEVICE_MAX);
 }
 
-uint16_t cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
+bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
   (void) max_len;
 
@@ -157,7 +157,7 @@ uint16_t cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const
   // Protocol 0xFF can be RNDIS device for windows XP
   TU_VERIFY( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
              CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass &&
-             0xFF                                     != itf_desc->bInterfaceProtocol, 0);
+             0xFF                                     != itf_desc->bInterfaceProtocol);
 
   cdch_data_t * p_cdc = get_itf(dev_addr);
 
@@ -186,7 +186,7 @@ uint16_t cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const
     // notification endpoint
     tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
 
-    TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep), 0 );
+    TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep) );
     p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
     drv_len += tu_desc_len(p_desc);
@@ -205,9 +205,9 @@ uint16_t cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const
     for(uint32_t i=0; i<2; i++)
     {
       tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-      TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer, 0);
+      TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
 
-      TU_ASSERT(usbh_edpt_open(rhport, dev_addr, desc_ep), 0);
+      TU_ASSERT(usbh_edpt_open(rhport, dev_addr, desc_ep));
 
       if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
       {
@@ -222,7 +222,7 @@ uint16_t cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const
     }
   }
 
-  return drv_len;
+  return true;
 }
 
 bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index edcd258a8..0d435138b 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -121,11 +121,11 @@ void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_i
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void     cdch_init       (void);
-uint16_t cdch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
-bool     cdch_set_config (uint8_t dev_addr, uint8_t itf_num);
-bool     cdch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
-void     cdch_close      (uint8_t dev_addr);
+void cdch_init       (void);
+bool cdch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+bool cdch_set_config (uint8_t dev_addr, uint8_t itf_num);
+bool cdch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void cdch_close      (uint8_t dev_addr);
 
 #ifdef __cplusplus
  }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index a39ac8bec..4dd198369 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -249,19 +249,22 @@ static bool config_get_report_desc_complete (uint8_t dev_addr, tusb_control_requ
 
 static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
 
-uint16_t hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
+bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
   (void) max_len;
 
-  TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass, 0);
+  TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass);
+
+  // len = interface + hid + n*endpoints
+  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
+  TU_ASSERT(max_len >= drv_len);
 
-  uint16_t drv_len = sizeof(tusb_desc_interface_t);
   uint8_t const *p_desc = (uint8_t const *) desc_itf;
 
   //------------- HID descriptor -------------//
   p_desc = tu_desc_next(p_desc);
   tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc;
-  TU_ASSERT(HID_DESC_TYPE_HID == desc_hid->bDescriptorType, 0);
+  TU_ASSERT(HID_DESC_TYPE_HID == desc_hid->bDescriptorType);
 
   // not enough interface, try to increase CFG_TUH_HID
   // TODO multiple devices
@@ -269,13 +272,12 @@ uint16_t hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const
   TU_ASSERT(hid_dev->inst_count < CFG_TUH_HID, 0);
 
   //------------- Endpoint Descriptor -------------//
-  drv_len += tu_desc_len(p_desc);
   p_desc = tu_desc_next(p_desc);
   tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-  TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType, 0);
+  TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
 
   // TODO also open endpoint OUT
-  TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep), 0 );
+  TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep) );
 
   hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count);
   hid_dev->inst_count++;
@@ -292,9 +294,7 @@ uint16_t hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const
   hid_itf->protocol_mode = HID_PROTOCOL_BOOT;
   if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass ) hid_itf->itf_protocol = desc_itf->bInterfaceProtocol;
 
-  drv_len += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
-
-  return drv_len;
+  return true;
 }
 
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index bbef05e25..9a498afec 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -121,11 +121,11 @@ TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t ins
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void     hidh_init       (void);
-uint16_t hidh_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
-bool     hidh_set_config (uint8_t dev_addr, uint8_t itf_num);
-bool     hidh_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-void     hidh_close      (uint8_t dev_addr);
+void hidh_init       (void);
+bool hidh_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
+bool hidh_set_config (uint8_t dev_addr, uint8_t itf_num);
+bool hidh_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+void hidh_close      (uint8_t dev_addr);
 
 #ifdef __cplusplus
 }
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 2c027deff..f02f4550a 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -360,22 +360,22 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* c
 static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 
-uint16_t msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
+bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
   TU_VERIFY (MSC_SUBCLASS_SCSI == desc_itf->bInterfaceSubClass &&
              MSC_PROTOCOL_BOT  == desc_itf->bInterfaceProtocol);
 
   // msc driver length is fixed
   uint16_t const drv_len = sizeof(tusb_desc_interface_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
-  TU_ASSERT(drv_len <= max_len, 0);
+  TU_ASSERT(drv_len <= max_len);
 
   msch_interface_t* p_msc = get_itf(dev_addr);
   tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(desc_itf);
 
   for(uint32_t i=0; i<2; i++)
   {
-    TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer, 0);
-    TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc), 0);
+    TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
+    TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc));
 
     if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
     {
@@ -390,7 +390,7 @@ uint16_t msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const
 
   p_msc->itf_num = desc_itf->bInterfaceNumber;
 
-  return drv_len;
+  return true;
 }
 
 bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index 9e4217ba5..7718ad4fe 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -106,11 +106,11 @@ TU_ATTR_WEAK void tuh_msc_umount_cb(uint8_t dev_addr);
 // Internal Class Driver API
 //--------------------------------------------------------------------+
 
-void     msch_init       (void);
-uint16_t msch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
-bool     msch_set_config (uint8_t dev_addr, uint8_t itf_num);
-bool     msch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
-void     msch_close      (uint8_t dev_addr);
+void msch_init       (void);
+bool msch_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
+bool msch_set_config (uint8_t dev_addr, uint8_t itf_num);
+void msch_close      (uint8_t dev_addr);
+bool msch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
 
 #ifdef __cplusplus
  }
diff --git a/src/host/hub.c b/src/host/hub.c
index 2ead5bed1..00dce4e65 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -147,16 +147,17 @@ void hub_init(void)
   tu_memclr(hub_data, CFG_TUSB_HOST_DEVICE_MAX*sizeof(hub_interface_t));
 }
 
-uint16_t hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
+bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
-  // hub driver does not support multiple TT yet
   TU_VERIFY(TUSB_CLASS_HUB == itf_desc->bInterfaceClass &&
-            0              == itf_desc->bInterfaceSubClass &&
-            1              <= itf_desc->bInterfaceProtocol, 0);
+            0              == itf_desc->bInterfaceSubClass);
+
+  // hub driver does not support multiple TT yet
+  TU_VERIFY(itf_desc->bInterfaceProtocol <= 1);
 
   // msc driver length is fixed
   uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t);
-  TU_ASSERT(drv_len <= max_len, 0);
+  TU_ASSERT(drv_len <= max_len);
 
   //------------- Interrupt Status endpoint -------------//
   tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
@@ -169,7 +170,7 @@ uint16_t hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const
   hub_data[dev_addr-1].itf_num = itf_desc->bInterfaceNumber;
   hub_data[dev_addr-1].ep_in   = desc_ep->bEndpointAddress;
 
-  return drv_len;
+  return true;
 }
 
 void hub_close(uint8_t dev_addr)
diff --git a/src/host/hub.h b/src/host/hub.h
index c9ffe4985..c4d544193 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -181,11 +181,11 @@ bool hub_status_pipe_queue(uint8_t dev_addr);
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void     hub_init       (void);
-uint16_t hub_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
-bool     hub_set_config (uint8_t dev_addr, uint8_t itf_num);
-bool     hub_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
-void     hub_close      (uint8_t dev_addr);
+void hub_init       (void);
+bool hub_open       (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+bool hub_set_config (uint8_t dev_addr, uint8_t itf_num);
+bool hub_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void hub_close      (uint8_t dev_addr);
 
 #ifdef __cplusplus
  }
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index fccb30253..8bc2622aa 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -43,11 +43,11 @@ typedef struct {
   char const* name;
   #endif
 
-  void     (* const init       )(void);
-  uint16_t (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
-  bool     (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
-  bool     (* const xfer_cb    )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-  void     (* const close      )(uint8_t dev_addr);
+  void (* const init       )(void);
+  bool (* const open       )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
+  bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
+  bool (* const xfer_cb    )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+  void (* const close      )(uint8_t dev_addr);
 } usbh_class_driver_t;
 
 // Call by class driver to tell USBH that it has complete the enumeration

From beb1a5c678dd50c3142d2c74a29e92affa0b06c9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 20 Aug 2021 19:39:33 +0700
Subject: [PATCH 0360/2085] minor clean up

---
 src/device/usbd.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 23f174dab..e12dafcfd 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -856,12 +856,12 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
 
   while( p_desc < desc_end )
   {
-    tusb_desc_interface_assoc_t const * desc_itf_assoc = NULL;
+    tusb_desc_interface_assoc_t const * desc_iad = NULL;
 
     // Class will always starts with Interface Association (if any) and then Interface descriptor
     if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
     {
-      desc_itf_assoc = (tusb_desc_interface_assoc_t const *) p_desc;
+      desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
       p_desc = tu_desc_next(p_desc); // next to Interface
     }
 
@@ -870,6 +870,13 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
     tusb_desc_interface_t const * desc_itf = (tusb_desc_interface_t const*) p_desc;
     uint16_t const remaining_len = desc_end-p_desc;
 
+    // Interface number must not be used already
+    TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[desc_itf->bInterfaceNumber]);
+
+    // TODO usbd can calculate the total length used for driver --> driver open() does not need to calculate it
+    // uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, desc_end-p_desc);
+
+    // Find driver for this interface
     uint8_t drv_id;
     for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
     {
@@ -881,31 +888,30 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
         // Open successfully, check if length is correct
         TU_ASSERT( sizeof(tusb_desc_interface_t) <= drv_len && drv_len <= remaining_len);
 
-        // Interface number must not be used already
-        TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[desc_itf->bInterfaceNumber]);
-
         TU_LOG2("  %s opened\r\n", driver->name);
+
+        // bind interface to found driver
         _usbd_dev.itf2drv[desc_itf->bInterfaceNumber] = drv_id;
 
-        // If IAD exist, assign all interfaces to the same driver
-        if (desc_itf_assoc)
+        // If using IAD, bind all interfaces to the same driver
+        if (desc_iad)
         {
           // IAD's first interface number and class should match with opened interface
-          TU_ASSERT(desc_itf_assoc->bFirstInterface == desc_itf->bInterfaceNumber &&
-                    desc_itf_assoc->bFunctionClass  == desc_itf->bInterfaceClass);
+          TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber &&
+                    desc_iad->bFunctionClass  == desc_itf->bInterfaceClass);
 
-          for(uint8_t i=1; i<desc_itf_assoc->bInterfaceCount; i++)
+          for(uint8_t i=1; i<desc_iad->bInterfaceCount; i++)
           {
             _usbd_dev.itf2drv[desc_itf->bInterfaceNumber+i] = drv_id;
           }
         }
 
-        // bind all endpoints for this driver
+        // bind all endpoints to found driver
         tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id);
 
         p_desc += drv_len; // next interface
 
-        break;
+        break; // exit driver find loop
       }
     }
 

From e20755442a3fe2141c9be8d54bee2aa4e092cdfc Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 21 Aug 2021 12:02:20 +0200
Subject: [PATCH 0361/2085] nuc126: fix set_address & disable sof

---
 src/portable/nuvoton/nuc121/dcd_nuc121.c | 37 +++++++++++++++++++-----
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index 20519ec28..80a19eb17 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -40,6 +40,12 @@
 #include "device/dcd.h"
 #include "NuMicro.h"
 
+// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
+// We disable SOF for now until needed later on
+#ifndef USE_SOF
+#  define USE_SOF     0
+#endif
+
 /* allocation of USBD RAM for Setup, EP0_IN, and and EP_OUT */
 #define PERIPH_SETUP_BUF_BASE  0
 #define PERIPH_SETUP_BUF_LEN   8
@@ -65,9 +71,6 @@ enum ep_enum
   PERIPH_MAX_EP,
 };
 
-/* set by dcd_set_address() */
-static volatile uint8_t assigned_address;
-
 /* reset by dcd_init(), this is used by dcd_edpt_open() to assign USBD peripheral buffer addresses */
 static uint32_t bufseg_addr;
 
@@ -197,7 +200,11 @@ static void bus_reset(void)
 }
 
 /* centralized location for USBD interrupt enable bit mask */
+#if USE_SOF
 static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk;
+#else
+static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk;
+#endif
 
 /*
   NUC121/NUC125/NUC126 TinyUSB API driver implementation
@@ -239,7 +246,9 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
   (void) rhport;
   usb_control_send_zlp(); /* SET_ADDRESS is the one exception where TinyUSB doesn't use dcd_edpt_xfer() to generate a ZLP */
-  assigned_address = dev_addr;
+
+  // DCD can only set address after status for this request is complete.
+  // do it at dcd_edpt0_status_complete()
 }
 
 void dcd_remote_wakeup(uint8_t rhport)
@@ -420,9 +429,6 @@ void dcd_int_handler(uint8_t rhport)
   {
     if (status & USBD_INTSTS_EPEVT0_Msk) /* PERIPH_EP0 (EP0_IN) event: this is treated separately from the rest */
     {
-      /* given ACK from host has happened, we can now set the address (if not already done) */
-      if((USBD->FADDR != assigned_address) && (USBD->FADDR == 0)) USBD->FADDR = assigned_address;
-
       uint16_t const available_bytes = USBD->EP[PERIPH_EP0].MXPLD;
 
       active_ep0_xfer = (available_bytes == xfer_table[PERIPH_EP0].max_packet_size);
@@ -495,6 +501,23 @@ void dcd_int_handler(uint8_t rhport)
   USBD->INTSTS = status & enabled_irqs;
 }
 
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  (void) rhport;
+
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+      request->bRequest == TUSB_REQ_SET_ADDRESS )
+  {
+    uint8_t const dev_addr = (uint8_t) request->wValue;
+
+    // Setting new address after the whole request is complete
+    USBD->FADDR = dev_addr;
+  }
+}
+
 void dcd_disconnect(uint8_t rhport)
 {
   (void) rhport;

From 69e539fda4c72a2f3177b3944f83632ef6752c11 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 21 Aug 2021 12:11:35 +0200
Subject: [PATCH 0362/2085] Fix CI.

---
 src/portable/nuvoton/nuc121/dcd_nuc121.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index 80a19eb17..a776e46f5 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -245,6 +245,7 @@ void dcd_int_disable(uint8_t rhport)
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
   (void) rhport;
+  (void) dev_addr;
   usb_control_send_zlp(); /* SET_ADDRESS is the one exception where TinyUSB doesn't use dcd_edpt_xfer() to generate a ZLP */
 
   // DCD can only set address after status for this request is complete.

From 4941cde175af2ef21bbe24d7d3271b46363c0759 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sun, 22 Aug 2021 13:26:50 +0200
Subject: [PATCH 0363/2085] Fix vendor fifo deadlock, add
 tud_vendor_n_read_flush

---
 src/class/vendor/vendor_device.c | 9 +++++++++
 src/class/vendor/vendor_device.h | 7 +++++++
 2 files changed, 16 insertions(+)

diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 6718a97bf..8c59b4ea7 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -103,6 +103,13 @@ uint32_t tud_vendor_n_read (uint8_t itf, void* buffer, uint32_t bufsize)
   return num_read;
 }
 
+void tud_vendor_n_read_flush (uint8_t itf)
+{
+  vendord_interface_t* p_itf = &_vendord_itf[itf];
+  tu_fifo_clear(&p_itf->rx_ff);
+  _prep_out_transaction(p_itf);
+}
+
 //--------------------------------------------------------------------+
 // Write API
 //--------------------------------------------------------------------+
@@ -199,6 +206,8 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, ui
     TU_BREAKPOINT();
   }
 
+  maybe_transmit(p_vendor);
+
   return drv_len;
 }
 
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index 6d9c784c0..844693c68 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -45,6 +45,7 @@ bool     tud_vendor_n_mounted         (uint8_t itf);
 uint32_t tud_vendor_n_available       (uint8_t itf);
 uint32_t tud_vendor_n_read            (uint8_t itf, void* buffer, uint32_t bufsize);
 bool     tud_vendor_n_peek            (uint8_t itf, uint8_t* u8);
+void     tud_vendor_n_read_flush      (uint8_t itf);
 
 uint32_t tud_vendor_n_write           (uint8_t itf, void const* buffer, uint32_t bufsize);
 uint32_t tud_vendor_n_write_available (uint8_t itf);
@@ -59,6 +60,7 @@ static inline bool     tud_vendor_mounted         (void);
 static inline uint32_t tud_vendor_available       (void);
 static inline uint32_t tud_vendor_read            (void* buffer, uint32_t bufsize);
 static inline bool     tud_vendor_peek            (uint8_t* u8);
+static inline void     tud_vendor_read_flush      (void);
 static inline uint32_t tud_vendor_write           (void const* buffer, uint32_t bufsize);
 static inline uint32_t tud_vendor_write_str       (char const* str);
 static inline uint32_t tud_vendor_write_available (void);
@@ -99,6 +101,11 @@ static inline bool tud_vendor_peek (uint8_t* u8)
   return tud_vendor_n_peek(0, u8);
 }
 
+static inline void tud_vendor_read_flush(void)
+{
+    tud_vendor_n_read_flush(0);
+}
+
 static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize)
 {
   return tud_vendor_n_write(0, buffer, bufsize);

From 800f85329ea21bdefc778c246c8098dea12fb402 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 23 Aug 2021 11:00:21 +0700
Subject: [PATCH 0364/2085] add tuh_hid_receive_report() for applicaiton to
 explicitly request report

---
 examples/host/cdc_msc_hid/src/hid_app.c     | 13 +++++++
 examples/host/cdc_msc_hid/src/main.c        | 29 ++-------------
 examples/host/cdc_msc_hid/src/tusb_config.h |  6 ++--
 src/class/hid/hid_host.c                    | 39 +++++++++++++--------
 src/class/hid/hid_host.h                    | 30 ++++++++++++----
 src/host/usbh.c                             |  8 +++--
 src/tusb.c                                  |  3 +-
 7 files changed, 73 insertions(+), 55 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index 5e3ac6a72..11437c2b4 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -80,6 +80,13 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
     hid_info[instance].report_count = tuh_hid_parse_report_descriptor(hid_info[instance].report_info, MAX_REPORT, desc_report, desc_len);
     printf("HID has %u reports \r\n", hid_info[instance].report_count);
   }
+
+  // request to receive report
+  // tuh_hid_report_received_cb() will be invoked when report is available
+  if ( !tuh_hid_receive_report(dev_addr, instance) )
+  {
+    printf("Error: cannot request to receive report\r\n");
+  }
 }
 
 // Invoked when device with hid interface is un-mounted
@@ -110,6 +117,12 @@ void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t cons
       process_generic_report(dev_addr, instance, report, len);
     break;
   }
+
+  // continue to request to receive report
+  if ( !tuh_hid_receive_report(dev_addr, instance) )
+  {
+    printf("Error: cannot request to receive report\r\n");
+  }
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index 7ae814e38..a14be05ea 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -33,7 +33,6 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
-void print_greeting(void);
 void led_blinking_task(void);
 
 extern void cdc_task(void);
@@ -43,7 +42,8 @@ extern void hid_app_task(void);
 int main(void)
 {
   board_init();
-  print_greeting();
+
+  printf("TinyUSB Host CDC MSC HID Example\r\n");
 
   tusb_init();
 
@@ -126,28 +126,3 @@ void led_blinking_task(void)
   board_led_write(led_state);
   led_state = 1 - led_state; // toggle
 }
-
-//--------------------------------------------------------------------+
-// HELPER FUNCTION
-//--------------------------------------------------------------------+
-void print_greeting(void)
-{
-  char const * const rtos_name[] =
-  {
-      [OPT_OS_NONE]      = "None",
-      [OPT_OS_FREERTOS]  = "FreeRTOS",
-      [OPT_OS_MYNEWT]    = "Mynewt OS",
-      [OPT_OS_CUSTOM]    = "Custom OS implemnted by application",
-      [OPT_OS_PICO]      = "Raspberry Pi Pico SDK",
-      [OPT_OS_RTTHREAD]  = "RT-Thread"
-  };
-
-  printf("----------------------------------------------------\r\n");
-  printf("TinyUSB Host Example\r\n");
-  printf("If you find any bugs or problems, feel free to open\r\n");
-  printf("an issue at https://github.com/hathach/tinyusb\r\n");
-  printf("----------------------------------------------------\r\n\r\n");
-
-  printf("This Host demo is configured to support:\r\n");
-  printf("  - RTOS = %s\r\n", rtos_name[CFG_TUSB_OS]);
-}
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index b574acf9b..80f07f446 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -76,15 +76,15 @@
 
 #define CFG_TUH_HUB                 1
 #define CFG_TUH_CDC                 1
-#define CFG_TUH_HID                 4
+#define CFG_TUH_HID                 4 // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
 
 #define CFG_TUSB_HOST_DEVICE_MAX    (CFG_TUH_HUB ? 5 : 1) // normal hub has 4 ports
 
 //------------- HID -------------//
-
-#define CFG_TUH_HID_EP_BUFSIZE      64
+#define CFG_TUH_HID_EPIN_BUFSIZE    64
+#define CFG_TUH_HID_EPOUT_BUFSIZE   64
 
 #ifdef __cplusplus
  }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 4dd198369..2d76df588 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -52,8 +52,8 @@ typedef struct
   uint16_t epin_size;
   uint16_t epout_size;
 
-  uint8_t epin_buf[CFG_TUH_HID_EP_BUFSIZE];
-  uint8_t epout_buf[CFG_TUH_HID_EP_BUFSIZE];
+  uint8_t epin_buf[CFG_TUH_HID_EPIN_BUFSIZE];
+  uint8_t epout_buf[CFG_TUH_HID_EPOUT_BUFSIZE];
 } hidh_interface_t;
 
 typedef struct
@@ -72,13 +72,8 @@ TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_instance(uint8_t dev_a
 static uint8_t get_instance_id_by_itfnum(uint8_t dev_addr, uint8_t itf);
 static uint8_t get_instance_id_by_epaddr(uint8_t dev_addr, uint8_t ep_addr);
 
-TU_ATTR_ALWAYS_INLINE static inline bool hidh_get_report(uint8_t dev_addr, hidh_interface_t* hid_itf)
-{
-  return usbh_edpt_xfer(dev_addr, hid_itf->ep_in, hid_itf->epin_buf, hid_itf->epin_size);
-}
-
 //--------------------------------------------------------------------+
-// Application API
+// Interface API
 //--------------------------------------------------------------------+
 
 uint8_t tuh_hid_instance_count(uint8_t dev_addr)
@@ -98,6 +93,10 @@ uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance)
   return hid_itf->itf_protocol;
 }
 
+//--------------------------------------------------------------------+
+// Control Endpoint API
+//--------------------------------------------------------------------+
+
 uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
 {
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
@@ -186,6 +185,20 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
   return true;
 }
 
+//--------------------------------------------------------------------+
+// Interrupt Endpoint API
+//--------------------------------------------------------------------+
+
+bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance)
+{
+  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+
+  // claim endpoint
+  TU_VERIFY( usbh_edpt_claim(dev_addr, hid_itf->ep_in) );
+
+  return usbh_edpt_xfer(dev_addr, hid_itf->ep_in, hid_itf->epin_buf, hid_itf->epin_size);
+}
+
 //bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t instance)
 //{
 //  TU_VERIFY(tuh_n_hid_n_mounted(dev_addr, instance));
@@ -217,9 +230,6 @@ bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint3
     TU_LOG2("  Get Report callback (%u, %u)\r\n", dev_addr, instance);
     TU_LOG1_MEM(hid_itf->epin_buf, 8, 2);
     tuh_hid_report_received_cb(dev_addr, instance, hid_itf->epin_buf, xferred_bytes);
-
-    // queue next report
-    hidh_get_report(dev_addr, hid_itf);
   }else
   {
     if (tuh_hid_report_sent_cb) tuh_hid_report_sent_cb(dev_addr, instance, hid_itf->epout_buf, xferred_bytes);
@@ -255,6 +265,8 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
 
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass);
 
+  TU_LOG2("HID opening Interface %u (addr = %u)\r\n", desc_itf->bInterfaceNumber, dev_addr);
+
   // len = interface + hid + n*endpoints
   uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
   TU_ASSERT(max_len >= drv_len);
@@ -336,7 +348,7 @@ static bool config_set_protocol(uint8_t dev_addr, tusb_control_request_t const *
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
-  TU_LOG2("HID Set Protocol\r\n");
+  TU_LOG2("HID Set Protocol to Boot Mode\r\n");
   hid_itf->protocol_mode = HID_PROTOCOL_BOOT;
   tusb_control_request_t const new_request =
   {
@@ -422,9 +434,6 @@ static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uin
   // enumeration is complete
   tuh_hid_mount_cb(dev_addr, instance, desc_report, desc_len);
 
-  // queue transfer for IN endpoint
-  hidh_get_report(dev_addr, hid_itf);
-
   // notify usbh that driver enumeration is complete
   usbh_driver_set_config_complete(dev_addr, hid_itf->itf_num);
 }
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index 9a498afec..fe09b03b2 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -38,10 +38,15 @@
 //--------------------------------------------------------------------+
 
 // TODO Highspeed interrupt can be up to 512 bytes
-#ifndef CFG_TUH_HID_EP_BUFSIZE
-#define CFG_TUH_HID_EP_BUFSIZE 64
+#ifndef CFG_TUH_HID_EPIN_BUFSIZE
+#define CFG_TUH_HID_EPIN_BUFSIZE 64
 #endif
 
+#ifndef CFG_TUH_HID_EPOUT_BUFSIZE
+#define CFG_TUH_HID_EPOUT_BUFSIZE 64
+#endif
+
+
 typedef struct
 {
   uint8_t  report_id;
@@ -54,7 +59,7 @@ typedef struct
 } tuh_hid_report_info_t;
 
 //--------------------------------------------------------------------+
-// Application API
+// Interface API
 //--------------------------------------------------------------------+
 
 // Get the number of HID instances
@@ -66,6 +71,14 @@ bool tuh_hid_mounted(uint8_t dev_addr, uint8_t instance);
 // Get interface supported protocol (bInterfaceProtocol) check out hid_interface_protocol_enum_t for possible values
 uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance);
 
+// Parse report descriptor into array of report_info struct and return number of reports.
+// For complicated report, application should write its own parser.
+uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, uint8_t arr_count, uint8_t const* desc_report, uint16_t desc_len) TU_ATTR_UNUSED;
+
+//--------------------------------------------------------------------+
+// Control Endpoint API
+//--------------------------------------------------------------------+
+
 // Get current protocol: HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
 // Note: Device will be initialized in Boot protocol for simplicity.
 //       Application can use set_protocol() to switch back to Report protocol.
@@ -79,13 +92,18 @@ bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol);
 // report_type is either Intput, Output or Feature, (value from hid_report_type_t)
 bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, void* report, uint16_t len);
 
-// Parse report descriptor into array of report_info struct and return number of reports.
-// For complicated report, application should write its own parser.
-uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, uint8_t arr_count, uint8_t const* desc_report, uint16_t desc_len) TU_ATTR_UNUSED;
+//--------------------------------------------------------------------+
+// Interrupt Endpoint API
+//--------------------------------------------------------------------+
 
 // Check if the interface is ready to use
 //bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t instance);
 
+// Try to receive next report on Interrupt Endpoint. Immediately return
+// - true If succeeded, tuh_hid_report_received_cb() callback will be invoked when report is available
+// - false if failed to queue the transfer e.g endpoint is busy
+bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance);
+
 // Send report using interrupt endpoint
 // If report_id > 0 (composite), it will be sent as 1st byte, then report contents. Otherwise only report content is sent.
 //void tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 662ce2673..40c23a69d 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -186,7 +186,7 @@ bool tuh_init(uint8_t rhport)
 
   TU_LOG2("USBH init\r\n");
 
-  tu_memclr(_usbh_devices, sizeof(usbh_device_t)*(CFG_TUSB_HOST_DEVICE_MAX+1));
+  tu_memclr(_usbh_devices, sizeof(_usbh_devices));
 
   //------------- Enumeration & Reporter Task init -------------//
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -436,6 +436,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
   for(itf_num++; itf_num < sizeof(dev->itf2drv); itf_num++)
   {
     // continue with next valid interface
+    // TODO skip IAD binding interface such as CDCs
     uint8_t const drv_id = dev->itf2drv[itf_num];
     if (drv_id != DRVID_INVALID)
     {
@@ -474,6 +475,7 @@ static bool enum_get_config_desc_complete       (uint8_t dev_addr, tusb_control_
 static bool enum_set_config_complete            (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 static bool parse_configuration_descriptor      (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
 
+#if CFG_TUH_HUB
 static bool enum_hub_clear_reset0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
   (void) dev_addr; (void) request;
@@ -540,7 +542,7 @@ static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request
 
   return true;
 }
-
+#endif
 
 static bool enum_request_set_addr(void)
 {
@@ -889,7 +891,7 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
         if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
         {
           // open successfully
-          TU_LOG2("%s opened\r\n", driver->name);
+          TU_LOG2("  Opened successfully\r\n");
 
           // bind interface to found driver
           dev->itf2drv[desc_itf->bInterfaceNumber] = drv_id;
diff --git a/src/tusb.c b/src/tusb.c
index 1fc775399..6494287d2 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -117,10 +117,11 @@ void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_
     {
       uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
 
+      TU_LOG(2, "  Bind EP %02x to driver id %u\r\n", ep_addr, driver_id);
       ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id;
     }
 
-    len   = (uint16_t)(len + tu_desc_len(p_desc));
+    len    = (uint16_t)(len + tu_desc_len(p_desc));
     p_desc = tu_desc_next(p_desc);
   }
 }

From 6a16f6ccddf77e1b0232aec0c89d2105e391b297 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 23 Aug 2021 11:01:40 +0700
Subject: [PATCH 0365/2085] rename CFG_TUSB_HOST_DEVICE_MAX to
 CFG_TUH_DEVICE_MAX

---
 examples/host/cdc_msc_hid/src/msc_app.c     |  2 +-
 examples/host/cdc_msc_hid/src/tusb_config.h |  2 +-
 lib/fatfs/diskio.c                          |  4 ++--
 lib/fatfs/diskio.h                          |  2 +-
 lib/fatfs/ffconf.h                          |  2 +-
 src/class/cdc/cdc_host.c                    |  4 ++--
 src/class/cdc/cdc_rndis_host.c              | 10 +++++-----
 src/class/hid/hid_host.c                    |  2 +-
 src/class/msc/msc_host.c                    |  4 ++--
 src/class/vendor/vendor_host.c              |  4 ++--
 src/host/hcd.h                              |  2 +-
 src/host/hub.c                              |  4 ++--
 src/host/usbh.c                             | 14 +++++++-------
 src/host/usbh_hcd.h                         |  2 +-
 src/portable/ehci/ehci.c                    |  4 ++--
 src/portable/ohci/ohci.h                    |  2 +-
 src/tusb_option.h                           | 10 +++++-----
 17 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c
index 3657a3d35..77a72052d 100644
--- a/examples/host/cdc_msc_hid/src/msc_app.c
+++ b/examples/host/cdc_msc_hid/src/msc_app.c
@@ -92,7 +92,7 @@ void tuh_msc_umount_cb(uint8_t dev_addr)
 //
 //  if ( phy_disk == f_get_current_drive() )
 //  { // active drive is unplugged --> change to other drive
-//    for(uint8_t i=0; i<CFG_TUSB_HOST_DEVICE_MAX; i++)
+//    for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
 //    {
 //      if ( disk_is_ready(i) )
 //      {
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 80f07f446..e2eb566bd 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -80,7 +80,7 @@
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
 
-#define CFG_TUSB_HOST_DEVICE_MAX    (CFG_TUH_HUB ? 5 : 1) // normal hub has 4 ports
+#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 5 : 1) // normal hub has 4 ports
 
 //------------- HID -------------//
 #define CFG_TUH_HID_EPIN_BUFSIZE    64
diff --git a/lib/fatfs/diskio.c b/lib/fatfs/diskio.c
index 401f583a2..a6132f27b 100644
--- a/lib/fatfs/diskio.c
+++ b/lib/fatfs/diskio.c
@@ -36,7 +36,7 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 // TODO change it to portable init
-static DSTATUS disk_state[CFG_TUSB_HOST_DEVICE_MAX];
+static DSTATUS disk_state[CFG_TUH_DEVICE_MAX];
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -61,7 +61,7 @@ static DRESULT wait_for_io_complete(uint8_t usb_addr)
 
 void diskio_init(void)
 {
-  memset(disk_state, STA_NOINIT, CFG_TUSB_HOST_DEVICE_MAX);
+  memset(disk_state, STA_NOINIT, CFG_TUH_DEVICE_MAX);
 }
 
 //pdrv Specifies the physical drive number.
diff --git a/lib/fatfs/diskio.h b/lib/fatfs/diskio.h
index 99743538a..f1f4bd327 100644
--- a/lib/fatfs/diskio.h
+++ b/lib/fatfs/diskio.h
@@ -83,7 +83,7 @@ DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
 static inline bool disk_is_ready(BYTE pdrv);
 static inline bool disk_is_ready(BYTE pdrv)
 {
-  return (pdrv < CFG_TUSB_HOST_DEVICE_MAX) &&
+  return (pdrv < CFG_TUH_DEVICE_MAX) &&
          ( (disk_status(pdrv) & (STA_NOINIT | STA_NODISK)) == 0 );
 }
 
diff --git a/lib/fatfs/ffconf.h b/lib/fatfs/ffconf.h
index bc132d2c3..782057ea4 100644
--- a/lib/fatfs/ffconf.h
+++ b/lib/fatfs/ffconf.h
@@ -128,7 +128,7 @@
 / Physical Drive Configurations
 /----------------------------------------------------------------------------*/
 
-#define _VOLUMES	CFG_TUSB_HOST_DEVICE_MAX
+#define _VOLUMES	CFG_TUH_DEVICE_MAX
 /* Number of volumes (logical drives) to be used. */
 
 
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 35b8de3b1..e14cb0bab 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -51,7 +51,7 @@ typedef struct {
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-static cdch_data_t cdch_data[CFG_TUSB_HOST_DEVICE_MAX];
+static cdch_data_t cdch_data[CFG_TUH_DEVICE_MAX];
 
 static inline cdch_data_t* get_itf(uint8_t dev_addr)
 {
@@ -146,7 +146,7 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_co
 //--------------------------------------------------------------------+
 void cdch_init(void)
 {
-  tu_memclr(cdch_data, sizeof(cdch_data_t)*CFG_TUSB_HOST_DEVICE_MAX);
+  tu_memclr(cdch_data, sizeof(cdch_data_t)*CFG_TUH_DEVICE_MAX);
 }
 
 bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c
index 42b9993bc..cc4ffd1cf 100644
--- a/src/class/cdc/cdc_rndis_host.c
+++ b/src/class/cdc/cdc_rndis_host.c
@@ -40,10 +40,10 @@
 //--------------------------------------------------------------------+
 #define RNDIS_MSG_PAYLOAD_MAX   (1024*4)
 
-CFG_TUSB_MEM_SECTION static uint8_t msg_notification[CFG_TUSB_HOST_DEVICE_MAX][8];
+CFG_TUSB_MEM_SECTION static uint8_t msg_notification[CFG_TUH_DEVICE_MAX][8];
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t msg_payload[RNDIS_MSG_PAYLOAD_MAX];
 
-static rndish_data_t rndish_data[CFG_TUSB_HOST_DEVICE_MAX];
+static rndish_data_t rndish_data[CFG_TUH_DEVICE_MAX];
 
 // TODO Microsoft requires message length for any get command must be at least 4096 bytes
 
@@ -88,7 +88,7 @@ static tusb_error_t rndis_body_subtask(void)
 
   OSAL_SUBTASK_BEGIN
 
-  for (relative_addr = 0; relative_addr < CFG_TUSB_HOST_DEVICE_MAX; relative_addr++)
+  for (relative_addr = 0; relative_addr < CFG_TUH_DEVICE_MAX; relative_addr++)
   {
 
   }
@@ -103,12 +103,12 @@ static tusb_error_t rndis_body_subtask(void)
 //--------------------------------------------------------------------+
 void rndish_init(void)
 {
-  tu_memclr(rndish_data, sizeof(rndish_data_t)*CFG_TUSB_HOST_DEVICE_MAX);
+  tu_memclr(rndish_data, sizeof(rndish_data_t)*CFG_TUH_DEVICE_MAX);
 
   //------------- Task creation -------------//
 
   //------------- semaphore creation for notificaiton pipe -------------//
-  for(uint8_t i=0; i<CFG_TUSB_HOST_DEVICE_MAX; i++)
+  for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
   {
     rndish_data[i].sem_notification_hdl = osal_semaphore_create( OSAL_SEM_REF(rndish_data[i].semaphore_notification) );
   }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 2d76df588..915f0b21a 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -62,7 +62,7 @@ typedef struct
   hidh_interface_t instances[CFG_TUH_HID];
 } hidh_device_t;
 
-static hidh_device_t _hidh_dev[CFG_TUSB_HOST_DEVICE_MAX-1];
+static hidh_device_t _hidh_dev[CFG_TUH_DEVICE_MAX-1];
 
 //------------- Internal prototypes -------------//
 
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index f02f4550a..c7669aa21 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -69,7 +69,7 @@ typedef struct
   msc_csw_t csw;
 }msch_interface_t;
 
-CFG_TUSB_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUSB_HOST_DEVICE_MAX];
+CFG_TUSB_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
 
 // buffer used to read scsi information when mounted
 // largest response data currently is inquiry TODO Inquiry is not part of enum anymore
@@ -291,7 +291,7 @@ bool tuh_msc_reset(uint8_t dev_addr)
 //--------------------------------------------------------------------+
 void msch_init(void)
 {
-  tu_memclr(_msch_itf, sizeof(msch_interface_t)*CFG_TUSB_HOST_DEVICE_MAX);
+  tu_memclr(_msch_itf, sizeof(msch_interface_t)*CFG_TUH_DEVICE_MAX);
 }
 
 void msch_close(uint8_t dev_addr)
diff --git a/src/class/vendor/vendor_host.c b/src/class/vendor/vendor_host.c
index f7a6b2bf0..1e28e9af4 100644
--- a/src/class/vendor/vendor_host.c
+++ b/src/class/vendor/vendor_host.c
@@ -41,7 +41,7 @@
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-custom_interface_info_t custom_interface[CFG_TUSB_HOST_DEVICE_MAX];
+custom_interface_info_t custom_interface[CFG_TUH_DEVICE_MAX];
 
 static tusb_error_t cush_validate_paras(uint8_t dev_addr, uint16_t vendor_id, uint16_t product_id, void * p_buffer, uint16_t length)
 {
@@ -90,7 +90,7 @@ tusb_error_t tusbh_custom_write(uint8_t dev_addr, uint16_t vendor_id, uint16_t p
 //--------------------------------------------------------------------+
 void cush_init(void)
 {
-  tu_memclr(&custom_interface, sizeof(custom_interface_info_t) * CFG_TUSB_HOST_DEVICE_MAX);
+  tu_memclr(&custom_interface, sizeof(custom_interface_info_t) * CFG_TUH_DEVICE_MAX);
 }
 
 tusb_error_t cush_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length)
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 7a9aadc73..62ff8b3f2 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -84,7 +84,7 @@ typedef struct
 // Max number of endpoints per device
 enum {
   // TODO better computation
-  HCD_MAX_ENDPOINT = CFG_TUSB_HOST_DEVICE_MAX*(CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3),
+  HCD_MAX_ENDPOINT = CFG_TUH_DEVICE_MAX*(CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3),
   HCD_MAX_XFER     = HCD_MAX_ENDPOINT*2,
 };
 
diff --git a/src/host/hub.c b/src/host/hub.c
index 00dce4e65..d685c6529 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -45,7 +45,7 @@ typedef struct
   hub_port_status_response_t port_status;
 } hub_interface_t;
 
-CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUSB_HOST_DEVICE_MAX];
+CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_DEVICE_MAX];
 TU_ATTR_ALIGNED(4) CFG_TUSB_MEM_SECTION static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
 
 #if CFG_TUSB_DEBUG
@@ -144,7 +144,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_con
 //--------------------------------------------------------------------+
 void hub_init(void)
 {
-  tu_memclr(hub_data, CFG_TUSB_HOST_DEVICE_MAX*sizeof(hub_interface_t));
+  tu_memclr(hub_data, CFG_TUH_DEVICE_MAX*sizeof(hub_interface_t));
 }
 
 bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 40c23a69d..98132a8c0 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -129,7 +129,7 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1
 static bool _usbh_initialized = false;
 
 // including zero-address
-CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1];
+CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUH_DEVICE_MAX+1];
 
 // Event queue
 // role device/host is used by OS NONE for mutex (disable usb isr)
@@ -156,7 +156,7 @@ bool tuh_device_configured(uint8_t dev_addr)
 
 tusb_speed_t tuh_device_get_speed (uint8_t const dev_addr)
 {
-  TU_ASSERT( dev_addr <= CFG_TUSB_HOST_DEVICE_MAX, TUSB_SPEED_INVALID);
+  TU_ASSERT( dev_addr <= CFG_TUH_DEVICE_MAX, TUSB_SPEED_INVALID);
   return (tusb_speed_t) _usbh_devices[dev_addr].speed;
 }
 
@@ -193,7 +193,7 @@ bool tuh_init(uint8_t rhport)
   TU_ASSERT(_usbh_q != NULL);
 
   //------------- Semaphore, Mutex for Control Pipe -------------//
-  for(uint8_t i=0; i<CFG_TUSB_HOST_DEVICE_MAX+1; i++) // including address zero
+  for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX+1; i++) // including address zero
   {
     usbh_device_t * const dev = &_usbh_devices[i];
 
@@ -387,7 +387,7 @@ void hcd_event_device_remove(uint8_t hostid, bool in_isr)
 void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
 {
   //------------- find the all devices (star-network) under port that is unplugged -------------//
-  for (uint8_t dev_addr = 0; dev_addr <= CFG_TUSB_HOST_DEVICE_MAX; dev_addr ++)
+  for (uint8_t dev_addr = 0; dev_addr <= CFG_TUH_DEVICE_MAX; dev_addr ++)
   {
     usbh_device_t* dev = &_usbh_devices[dev_addr];
 
@@ -422,11 +422,11 @@ void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port
 //--------------------------------------------------------------------+
 static uint8_t get_new_address(void)
 {
-  for (uint8_t addr=1; addr <= CFG_TUSB_HOST_DEVICE_MAX; addr++)
+  for (uint8_t addr=1; addr <= CFG_TUH_DEVICE_MAX; addr++)
   {
     if (_usbh_devices[addr].state == TUSB_DEVICE_STATE_UNPLUG) return addr;
   }
-  return CFG_TUSB_HOST_DEVICE_MAX+1;
+  return CFG_TUH_DEVICE_MAX+1;
 }
 
 void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
@@ -548,7 +548,7 @@ static bool enum_request_set_addr(void)
 {
   // Set Address
   uint8_t const new_addr = get_new_address();
-  TU_ASSERT(new_addr <= CFG_TUSB_HOST_DEVICE_MAX); // TODO notify application we reach max devices
+  TU_ASSERT(new_addr <= CFG_TUH_DEVICE_MAX); // TODO notify application we reach max devices
 
   TU_LOG2("Set Address = %d\r\n", new_addr);
 
diff --git a/src/host/usbh_hcd.h b/src/host/usbh_hcd.h
index 450b3e447..9f8d3407d 100644
--- a/src/host/usbh_hcd.h
+++ b/src/host/usbh_hcd.h
@@ -95,7 +95,7 @@ typedef struct {
 
 } usbh_device_t;
 
-extern usbh_device_t _usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1]; // including zero-address
+extern usbh_device_t _usbh_devices[CFG_TUH_DEVICE_MAX+1]; // including zero-address
 
 #ifdef __cplusplus
  }
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 48788ba06..62be83468 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -56,7 +56,7 @@ typedef struct
   struct {
     ehci_qhd_t qhd;
     ehci_qtd_t qtd;
-  }control[CFG_TUSB_HOST_DEVICE_MAX+1];
+  }control[CFG_TUH_DEVICE_MAX+1];
 
   ehci_qhd_t qhd_pool[HCD_MAX_ENDPOINT];
   ehci_qtd_t qtd_pool[HCD_MAX_XFER] TU_ATTR_ALIGNED(32);
@@ -528,7 +528,7 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms)
   // TODO abstract max loop guard for period
   while( !next_item.terminate &&
       !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) &&
-      max_loop < (HCD_MAX_ENDPOINT + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUSB_HOST_DEVICE_MAX)
+      max_loop < (HCD_MAX_ENDPOINT + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUH_DEVICE_MAX)
   {
     switch ( next_item.type )
     {
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index 6a634592a..cd90aa45a 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -159,7 +159,7 @@ typedef struct TU_ATTR_ALIGNED(256)
   struct {
     ohci_ed_t ed;
     ohci_gtd_t gtd;
-  }control[CFG_TUSB_HOST_DEVICE_MAX+1];
+  }control[CFG_TUH_DEVICE_MAX+1];
 
   //  ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
   ohci_ed_t ed_pool[HCD_MAX_ENDPOINT];
diff --git a/src/tusb_option.h b/src/tusb_option.h
index e189c65bb..bbbf10a84 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -266,14 +266,14 @@
 // HOST OPTIONS
 //--------------------------------------------------------------------
 #if TUSB_OPT_HOST_ENABLED
-  #ifndef CFG_TUSB_HOST_DEVICE_MAX
-    #define CFG_TUSB_HOST_DEVICE_MAX 1
-    #warning CFG_TUSB_HOST_DEVICE_MAX is not defined, default value is 1
+  #ifndef CFG_TUH_DEVICE_MAX
+    #define CFG_TUH_DEVICE_MAX 1
+    #warning CFG_TUH_DEVICE_MAX is not defined, default value is 1
   #endif
 
   //------------- HUB CLASS -------------//
-  #if CFG_TUH_HUB && (CFG_TUSB_HOST_DEVICE_MAX == 1)
-    #error There is no benefit enable hub with max device is 1. Please disable hub or increase CFG_TUSB_HOST_DEVICE_MAX
+  #if CFG_TUH_HUB && (CFG_TUH_DEVICE_MAX == 1)
+    #error There is no benefit enable hub with max device is 1. Please disable hub or increase CFG_TUH_DEVICE_MAX
   #endif
 
   #ifndef CFG_TUH_ENUMERATION_BUFSIZE

From 4ca176c291a138f19ecf2426d636609d8c25da06 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 23 Aug 2021 12:37:54 +0700
Subject: [PATCH 0366/2085] refactor ehci init api

---
 src/portable/ehci/ehci.c                      | 37 +++++++++++++------
 src/portable/ehci/ehci.h                      |  7 +---
 src/portable/ehci/{hcd_ehci.h => ehci_api.h}  | 14 ++-----
 .../transdimension/common_transdimension.h    |  2 +-
 .../nxp/transdimension/hcd_transdimension.c   | 26 +++++--------
 5 files changed, 39 insertions(+), 47 deletions(-)
 rename src/portable/ehci/{hcd_ehci.h => ehci_api.h} (79%)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 62be83468..bc83f5b8b 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -37,13 +37,25 @@
 
 #include "host/hcd.h"
 #include "host/usbh_hcd.h"
-#include "hcd_ehci.h"
+#include "ehci_api.h"
 #include "ehci.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+// Debug level of EHCI
+#define EHCI_DBG     2
+
+// Framelist size as small as possible
+// - Standard EHCI : 256 elements
+// - NXP Transdimension:  8 elements
+#define	EHCI_CFG_FRAMELIST_SIZE_BITS		7
+#define EHCI_FRAMELIST_SIZE             (1024 >> EHCI_CFG_FRAMELIST_SIZE_BITS)
+
+TU_VERIFY_STATIC(EHCI_CFG_FRAMELIST_SIZE_BITS <= 7, "incorrect value");
+
+
 typedef struct
 {
   ehci_link_t period_framelist[EHCI_FRAMELIST_SIZE];
@@ -65,9 +77,7 @@ typedef struct
 
   volatile uint32_t uframe_number;
 }ehci_data_t;
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
+
 // Periodic frame list must be 4K alignment
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
 
@@ -109,7 +119,7 @@ static inline bool qhd_has_xact_error (ehci_qhd_t * p_qhd)
   //p_qhd->qtd_overlay.non_hs_period_missed_uframe || p_qhd->qtd_overlay.pingstate_err TODO split transaction error
 }
 
-static void qhd_init (ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
+static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
 
 static inline ehci_qtd_t* qtd_find_free (void);
 static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd);
@@ -218,12 +228,13 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
   ehci_data.regs->command_bm.async_adv_doorbell = 1;
 }
 
-// EHCI controller init
-bool hcd_ehci_init(uint8_t rhport)
+bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
 {
+  (void) capability_reg; // not used yet
+
   tu_memclr(&ehci_data, sizeof(ehci_data_t));
 
-  ehci_data.regs = (ehci_registers_t* ) hcd_ehci_register_addr(rhport);
+  ehci_data.regs = (ehci_registers_t* ) operatial_reg;
 
   ehci_registers_t* regs = ehci_data.regs;
 
@@ -470,16 +481,16 @@ static void async_advance_isr(uint8_t rhport)
   }
 }
 
-static void port_connect_status_change_isr(uint8_t hostid)
+static void port_connect_status_change_isr(uint8_t rhport)
 {
   // NOTE There is an sequence plug->unplug->…..-> plug if device is powering with pre-plugged device
   if (ehci_data.regs->portsc_bm.current_connect_status)
   {
-    hcd_port_reset(hostid);
-    hcd_event_device_attach(hostid, true);
+    hcd_port_reset(rhport);
+    hcd_event_device_attach(rhport, true);
   }else // device unplugged
   {
-    hcd_event_device_remove(hostid, true);
+    hcd_event_device_remove(rhport, true);
   }
 }
 
@@ -656,6 +667,8 @@ void hcd_int_handler(uint8_t rhport)
   {
     uint32_t port_status = regs->portsc & EHCI_PORTSC_MASK_ALL;
 
+    TU_LOG_HEX(EHCI_DBG, regs->portsc);
+
     if (regs->portsc_bm.connect_status_change)
     {
       port_connect_status_change_isr(rhport);
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index 874195a0c..cbcf1712a 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -46,8 +46,6 @@
 //--------------------------------------------------------------------+
 // EHCI CONFIGURATION & CONSTANTS
 //--------------------------------------------------------------------+
-#define	EHCI_CFG_FRAMELIST_SIZE_BITS		7			/// Framelist Size (NXP specific) (0:1024) - (1:512) - (2:256) - (3:128) - (4:64) - (5:32) - (6:16) - (7:8)
-#define EHCI_FRAMELIST_SIZE             (1024 >> EHCI_CFG_FRAMELIST_SIZE_BITS)
 
 // TODO merge OHCI with EHCI
 enum {
@@ -55,9 +53,6 @@ enum {
   EHCI_MAX_SITD = 16
 };
 
-//------------- Validation -------------//
-TU_VERIFY_STATIC(EHCI_CFG_FRAMELIST_SIZE_BITS <= 7, "incorrect value");
-
 //--------------------------------------------------------------------+
 // EHCI Data Structure
 //--------------------------------------------------------------------+
@@ -411,7 +406,7 @@ typedef volatile struct
       uint32_t wake_on_over_current_enable : 1; ///< Enables over-current conditions as wake-up events
       uint32_t nxp_phy_clock_disable       : 1; ///< NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock
       uint32_t nxp_port_force_fullspeed    : 1; ///< NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
-      uint32_t                             : 1;
+      uint32_t TU_RESERVED                 : 1;
       uint32_t nxp_port_speed              : 2; ///< NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed
       uint32_t TU_RESERVED                 : 4;
     }portsc_bm;
diff --git a/src/portable/ehci/hcd_ehci.h b/src/portable/ehci/ehci_api.h
similarity index 79%
rename from src/portable/ehci/hcd_ehci.h
rename to src/portable/ehci/ehci_api.h
index 480d11eda..12e0a73d7 100644
--- a/src/portable/ehci/hcd_ehci.h
+++ b/src/portable/ehci/ehci_api.h
@@ -24,27 +24,19 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_HCD_EHCI_H_
-#define _TUSB_HCD_EHCI_H_
+#ifndef _TUSB_EHCI_API_H_
+#define _TUSB_EHCI_API_H_
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-
-//--------------------------------------------------------------------+
-// API Implemented by HCD
-//--------------------------------------------------------------------+
-
-// Get operational address i.e EHCI Command register
-uint32_t hcd_ehci_register_addr(uint8_t rhport);
-
 //--------------------------------------------------------------------+
 // API Implemented by EHCI
 //--------------------------------------------------------------------+
 
 // Initialize EHCI driver
-extern bool hcd_ehci_init (uint8_t rhport);
+bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg);
 
 #ifdef __cplusplus
  }
diff --git a/src/portable/nxp/transdimension/common_transdimension.h b/src/portable/nxp/transdimension/common_transdimension.h
index 7b94dac34..69074de41 100644
--- a/src/portable/nxp/transdimension/common_transdimension.h
+++ b/src/portable/nxp/transdimension/common_transdimension.h
@@ -127,7 +127,7 @@ typedef struct
   __I  uint32_t ENDPTSTAT;       ///< Endpoint Status
   __IO uint32_t ENDPTCOMPLETE;   ///< Endpoint Complete
   __IO uint32_t ENDPTCTRL[8];    ///< Endpoint Control 0 - 7
-} dcd_registers_t;
+} dcd_registers_t, hcd_registers_t;
 
 #ifdef __cplusplus
  }
diff --git a/src/portable/nxp/transdimension/hcd_transdimension.c b/src/portable/nxp/transdimension/hcd_transdimension.c
index db447ef23..d216f0728 100644
--- a/src/portable/nxp/transdimension/hcd_transdimension.c
+++ b/src/portable/nxp/transdimension/hcd_transdimension.c
@@ -43,7 +43,7 @@
 
 #include "common/tusb_common.h"
 #include "common_transdimension.h"
-#include "portable/ehci/hcd_ehci.h"
+#include "portable/ehci/ehci_api.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
@@ -82,26 +82,26 @@ typedef struct
 
 bool hcd_init(uint8_t rhport)
 {
-  dcd_registers_t* dcd_reg = (dcd_registers_t*) _hcd_controller[rhport].regs_base;
+  hcd_registers_t* hcd_reg = (hcd_registers_t*) _hcd_controller[rhport].regs_base;
 
   // Reset controller
-  dcd_reg->USBCMD |= USBCMD_RESET;
-  while( dcd_reg->USBCMD & USBCMD_RESET ) {}
+  hcd_reg->USBCMD |= USBCMD_RESET;
+  while( hcd_reg->USBCMD & USBCMD_RESET ) {}
 
   // Set mode to device, must be set immediately after reset
 #if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
   // LPC18XX/43XX need to set VBUS Power Select to HIGH
   // RHPORT1 is fullspeed only (need external PHY for Highspeed)
-  dcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
-  if (rhport == 1) dcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+  hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
+  if (rhport == 1) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
 #else
-  dcd_reg->USBMODE = USBMODE_CM_HOST;
+  hcd_reg->USBMODE = USBMODE_CM_HOST;
 #endif
 
   // FIXME force full speed, still have issue with Highspeed enumeration
-  dcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+  hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
 
-  return hcd_ehci_init(rhport);
+  return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD);
 }
 
 void hcd_int_enable(uint8_t rhport)
@@ -114,12 +114,4 @@ void hcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(_hcd_controller[rhport].irqnum);
 }
 
-uint32_t hcd_ehci_register_addr(uint8_t rhport)
-{
-  dcd_registers_t* hcd_reg = (dcd_registers_t*) _hcd_controller[rhport].regs_base;
-
-  // EHCI USBCMD has same address within dcd_register_t
-  return (uint32_t) &hcd_reg->USBCMD;
-}
-
 #endif

From a490a3fe616205115ed351ddbc0bd202bcbdc3db Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 23 Aug 2021 15:40:57 +0700
Subject: [PATCH 0367/2085] add hcd attr, add note for ehci framelist on NXP
 derivative

---
 src/host/hcd.h           |   4 +-
 src/host/hcd_attr.h      | 104 +++++++++++++++++++++++++++++++++++++++
 src/host/hub.c           |   6 +--
 src/host/usbh.c          |   3 +-
 src/portable/ehci/ehci.c |  72 ++++++++++++++-------------
 src/portable/ehci/ehci.h |   2 +-
 6 files changed, 151 insertions(+), 40 deletions(-)
 create mode 100644 src/host/hcd_attr.h

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 62ff8b3f2..e1d21bf45 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -30,6 +30,7 @@
 #include "common/tusb_common.h"
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
+#include "hcd_attr.h"
 
 #ifdef __cplusplus
  extern "C" {
@@ -62,6 +63,7 @@ typedef struct
     struct {
       uint8_t hub_addr;
       uint8_t hub_port;
+      uint8_t speed;
     } connection;
 
     // XFER_COMPLETE
@@ -140,7 +142,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
-// Event API (implemented by stack)
+// USBH implemented API
 //--------------------------------------------------------------------+
 
 // Called by HCD to notify stack
diff --git a/src/host/hcd_attr.h b/src/host/hcd_attr.h
new file mode 100644
index 000000000..d18686587
--- /dev/null
+++ b/src/host/hcd_attr.h
@@ -0,0 +1,104 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_HCD_ATTR_H_
+#define TUSB_HCD_ATTR_H_
+
+#include "tusb_option.h"
+
+// Attribute includes
+// - ENDPOINT_MAX: max (logical) number of endpoint
+// - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
+
+//------------- NXP -------------//
+#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+
+#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX)
+  #define HCD_ATTR_EHCI_TRANSDIMENSION
+
+#elif TU_CHECK_MCU(LPC54XXX)
+  // #define HCD_ATTR_EHCI_NXP_PTD
+
+#elif TU_CHECK_MCU(LPC55XX)
+  // #define HCD_ATTR_EHCI_NXP_PTD
+
+#elif TU_CHECK_MCU(MIMXRT10XX)
+  #define HCD_ATTR_EHCI_TRANSDIMENSION
+
+#elif TU_CHECK_MCU(MKL25ZXX)
+
+//------------- Microchip -------------//
+#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \
+      TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22)
+
+#elif TU_CHECK_MCU(SAMG)
+
+#elif TU_CHECK_MCU(SAMX7X)
+
+//------------- ST -------------//
+#elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \
+      TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4)
+
+#elif TU_CHECK_MCU(STM32F2) || TU_CHECK_MCU(STM32F4) || TU_CHECK_MCU(STM32F3)
+
+#elif TU_CHECK_MCU(STM32F7)
+
+#elif TU_CHECK_MCU(STM32H7)
+
+//------------- Sony -------------//
+#elif TU_CHECK_MCU(CXD56)
+
+//------------- Nuvoton -------------//
+#elif TU_CHECK_MCU(NUC505)
+
+//------------- Espressif -------------//
+#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+
+//------------- Raspberry Pi -------------//
+#elif TU_CHECK_MCU(RP2040)
+
+//------------- Silabs -------------//
+#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12)
+
+//------------- Renesas -------------//
+#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N)
+
+//#elif TU_CHECK_MCU(MM32F327X)
+//  #define DCD_ATTR_ENDPOINT_MAX not known yet
+
+//------------- GigaDevice -------------//
+#elif TU_CHECK_MCU(GD32VF103)
+
+#else
+//  #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
+#endif
+
+// Default to fullspeed if not defined
+//#ifndef PORT_HIGHSPEED
+//  #define DCD_ATTR_PORT_HIGHSPEED 0x00
+//#endif
+
+#endif
diff --git a/src/host/hub.c b/src/host/hub.c
index d685c6529..65e747e41 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -45,8 +45,8 @@ typedef struct
   hub_port_status_response_t port_status;
 } hub_interface_t;
 
-CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_DEVICE_MAX];
-TU_ATTR_ALIGNED(4) CFG_TUSB_MEM_SECTION static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
+CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB];
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
 
 #if CFG_TUSB_DEBUG
 static char const* const _hub_feature_str[] =
@@ -144,7 +144,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_con
 //--------------------------------------------------------------------+
 void hub_init(void)
 {
-  tu_memclr(hub_data, CFG_TUH_DEVICE_MAX*sizeof(hub_interface_t));
+  tu_memclr(hub_data, sizeof(hub_data));
 }
 
 bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 98132a8c0..76c1ba078 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -128,7 +128,8 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
 static bool _usbh_initialized = false;
 
-// including zero-address
+// all devices including hub and zero-address TODO exclude device0 to save space
+// hub address start from CFG_TUH_DEVICE_MAX
 CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUH_DEVICE_MAX+1];
 
 // Event queue
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index bc83f5b8b..4d240cc50 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -24,11 +24,9 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "common/tusb_common.h"
+#include "host/hcd_attr.h"
 
-#if TUSB_OPT_HOST_ENABLED && \
-   (CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || \
-    CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX )
+#if TUSB_OPT_HOST_ENABLED && defined(HCD_ATTR_EHCI_TRANSDIMENSION)
 
 //--------------------------------------------------------------------+
 // INCLUDE
@@ -47,21 +45,27 @@
 // Debug level of EHCI
 #define EHCI_DBG     2
 
-// Framelist size as small as possible
-// - Standard EHCI : 256 elements
-// - NXP Transdimension:  8 elements
-#define	EHCI_CFG_FRAMELIST_SIZE_BITS		7
-#define EHCI_FRAMELIST_SIZE             (1024 >> EHCI_CFG_FRAMELIST_SIZE_BITS)
-
-TU_VERIFY_STATIC(EHCI_CFG_FRAMELIST_SIZE_BITS <= 7, "incorrect value");
+// Framelist size as small as possible to save SRAM
+#ifdef HCD_ATTR_EHCI_TRANSDIMENSION
+  // NXP Transdimension: 8 elements
+  #define FRAMELIST_SIZE_BIT_VALUE      7u
+  #define FRAMELIST_SIZE_USBCMD_VALUE   (((FRAMELIST_SIZE_BIT_VALUE &  3) << EHCI_USBCMD_POS_FRAMELIST_SIZE) | \
+                                         ((FRAMELIST_SIZE_BIT_VALUE >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB))
+#else
+  // STD EHCI: 256 elements
+  #define FRAMELIST_SIZE_BIT_VALUE      2u
+  #define FRAMELIST_SIZE_USBCMD_VALUE   ((FRAMELIST_SIZE_BIT_VALUE &  3) << EHCI_USBCMD_POS_FRAMELIST_SIZE)
+#endif
 
+#define FRAMELIST_SIZE                  (1024 >> FRAMELIST_SIZE_BIT_VALUE)
 
 typedef struct
 {
-  ehci_link_t period_framelist[EHCI_FRAMELIST_SIZE];
+  ehci_link_t period_framelist[FRAMELIST_SIZE];
 
-  // for NXP ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
+  // TODO only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
   // [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms
+  // TODO better implementation without dummy head to save SRAM
   ehci_qhd_t period_head_arr[4];
 
   // Note control qhd of dev0 is used as head of async list
@@ -84,10 +88,10 @@ CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
 //--------------------------------------------------------------------+
 // PROTOTYPE
 //--------------------------------------------------------------------+
-static inline ehci_link_t* get_period_head(uint8_t rhport, uint8_t interval_ms)
+static inline ehci_link_t* get_period_head(uint8_t rhport, uint32_t interval_ms)
 {
   (void) rhport;
-  return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min8(EHCI_FRAMELIST_SIZE, interval_ms) ) ];
+  return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min32(FRAMELIST_SIZE, interval_ms) ) ];
 }
 
 static inline ehci_qhd_t* qhd_control(uint8_t dev_addr)
@@ -260,37 +264,38 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
 
   //------------- Periodic List -------------//
   // Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only
-  for(uint32_t i=0; i<4; i++)
+  for ( uint32_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++ )
   {
-    ehci_data.period_head_arr[i].int_smask    = 1; // queue head in period list must have smask non-zero
+    ehci_data.period_head_arr[i].int_smask          = 1; // queue head in period list must have smask non-zero
     ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive
   }
 
   ehci_link_t * const framelist  = ehci_data.period_framelist;
-  ehci_link_t * const period_1ms = get_period_head(rhport, 1);
+  ehci_link_t * const period_1ms = get_period_head(rhport, 1u);
+
   // all links --> period_head_arr[0] (1ms)
   // 0, 2, 4, 6 etc --> period_head_arr[1] (2ms)
   // 1, 5 --> period_head_arr[2] (4ms)
   // 3 --> period_head_arr[3] (8ms)
 
   // TODO EHCI_FRAMELIST_SIZE with other size than 8
-  for(uint32_t i=0; i<EHCI_FRAMELIST_SIZE; i++)
+  for(uint32_t i=0; i<FRAMELIST_SIZE; i++)
   {
     framelist[i].address = (uint32_t) period_1ms;
     framelist[i].type    = EHCI_QTYPE_QHD;
   }
 
-  for(uint32_t i=0; i<EHCI_FRAMELIST_SIZE; i+=2)
+  for(uint32_t i=0; i<FRAMELIST_SIZE; i+=2)
   {
-    list_insert(framelist + i, get_period_head(rhport, 2), EHCI_QTYPE_QHD);
+    list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD);
   }
 
-  for(uint32_t i=1; i<EHCI_FRAMELIST_SIZE; i+=4)
+  for(uint32_t i=1; i<FRAMELIST_SIZE; i+=4)
   {
-    list_insert(framelist + i, get_period_head(rhport, 4), EHCI_QTYPE_QHD);
+    list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD);
   }
 
-  list_insert(framelist+3, get_period_head(rhport, 8), EHCI_QTYPE_QHD);
+  list_insert(framelist+3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD);
 
   period_1ms->terminate    = 1;
 
@@ -300,10 +305,9 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   regs->nxp_tt_control = 0;
 
   //------------- USB CMD Register -------------//
-  regs->command |= TU_BIT(EHCI_USBCMD_POS_RUN_STOP) | TU_BIT(EHCI_USBCMD_POS_ASYNC_ENABLE)
-                | TU_BIT(EHCI_USBCMD_POS_PERIOD_ENABLE) // TODO enable period list only there is int/iso endpoint
-                | ((EHCI_CFG_FRAMELIST_SIZE_BITS & TU_BIN8(011)) << EHCI_USBCMD_POS_FRAMELIST_SZIE)
-                | ((EHCI_CFG_FRAMELIST_SIZE_BITS >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB);
+  regs->command |= TU_BIT(EHCI_USBCMD_POS_RUN_STOP) | TU_BIT(EHCI_USBCMD_POS_ASYNC_ENABLE) |
+                   TU_BIT(EHCI_USBCMD_POS_PERIOD_ENABLE) |  // TODO enable period list only there is int/iso endpoint
+                   FRAMELIST_SIZE_USBCMD_VALUE;
 
   //------------- ConfigFlag Register (skip) -------------//
   regs->portsc_bm.port_power = 1; // enable port power
@@ -530,10 +534,10 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
   }while(p_qhd != async_head); // async list traversal, stop if loop around
 }
 
-static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms)
+static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms)
 {
   uint16_t max_loop = 0;
-  uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1);
+  uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1u);
   ehci_link_t next_item = * get_period_head(hostid, interval_ms);
 
   // TODO abstract max loop guard for period
@@ -616,8 +620,8 @@ static void xfer_error_isr(uint8_t hostid)
   }while(p_qhd != async_head); // async list traversal, stop if loop around
 
   //------------- TODO refractor period list -------------//
-  uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1);
-  for (uint8_t interval_ms=1; interval_ms <= EHCI_FRAMELIST_SIZE; interval_ms *= 2)
+  uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1u);
+  for (uint32_t interval_ms=1; interval_ms <= FRAMELIST_SIZE; interval_ms *= 2)
   {
     ehci_link_t next_item = * get_period_head(hostid, interval_ms);
 
@@ -660,7 +664,7 @@ void hcd_int_handler(uint8_t rhport)
 
   if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER)
   {
-    ehci_data.uframe_number += (EHCI_FRAMELIST_SIZE << 3);
+    ehci_data.uframe_number += (FRAMELIST_SIZE << 3);
   }
 
   if (int_status & EHCI_INT_MASK_PORT_CHANGE)
@@ -690,7 +694,7 @@ void hcd_int_handler(uint8_t rhport)
 
   if (int_status & EHCI_INT_MASK_NXP_PERIODIC)
   {
-    for (uint8_t i=1; i <= EHCI_FRAMELIST_SIZE; i *= 2)
+    for (uint32_t i=1; i <= FRAMELIST_SIZE; i *= 2)
     {
       period_list_xfer_complete_isr( rhport, i );
     }
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index cbcf1712a..c2bee67a5 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -289,7 +289,7 @@ enum ehci_interrupt_mask_{
 
 enum ehci_usbcmd_pos_ {
   EHCI_USBCMD_POS_RUN_STOP               = 0,
-  EHCI_USBCMD_POS_FRAMELIST_SZIE         = 2,
+  EHCI_USBCMD_POS_FRAMELIST_SIZE         = 2,
   EHCI_USBCMD_POS_PERIOD_ENABLE          = 4,
   EHCI_USBCMD_POS_ASYNC_ENABLE           = 5,
   EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB = 15,

From 75cd593b609340b3101d0b002ac765c5595fa2eb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 23 Aug 2021 17:00:41 +0700
Subject: [PATCH 0368/2085] add hcd_devtree_get_info()

remove usbh_hcd.h
---
 src/host/hcd.h           |  15 ++++++
 src/host/hcd_attr.h      |   1 +
 src/host/usbh.c          |  78 ++++++++++++++++++++++++++--
 src/host/usbh_control.c  |   9 ++--
 src/host/usbh_hcd.h      | 106 ---------------------------------------
 src/portable/ehci/ehci.c |  10 ++--
 src/portable/ohci/ohci.c |  11 ++--
 src/tusb_option.h        |   6 ---
 8 files changed, 106 insertions(+), 130 deletions(-)
 delete mode 100644 src/host/usbh_hcd.h

diff --git a/src/host/hcd.h b/src/host/hcd.h
index e1d21bf45..eb53d2e80 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -92,6 +92,14 @@ enum {
 
 //#define HCD_MAX_ENDPOINT 16
 //#define HCD_MAX_XFER 16
+
+typedef struct {
+  uint8_t rhport;
+  uint8_t hub_addr;
+  uint8_t hub_port;
+  uint8_t speed;
+} hcd_devtree_info_t;
+
 #endif
 
 //--------------------------------------------------------------------+
@@ -145,6 +153,13 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
 // USBH implemented API
 //--------------------------------------------------------------------+
 
+// Get device tree information of a device
+// USB device tree can be complicated and manged by USBH, this help HCD to retrieve
+// needed topology info to carry out its work
+extern void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info);
+
+//------------- Event API -------------//
+
 // Called by HCD to notify stack
 extern void hcd_event_handler(hcd_event_t const* event, bool in_isr);
 
diff --git a/src/host/hcd_attr.h b/src/host/hcd_attr.h
index d18686587..729fc407b 100644
--- a/src/host/hcd_attr.h
+++ b/src/host/hcd_attr.h
@@ -35,6 +35,7 @@
 
 //------------- NXP -------------//
 #if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+  #define HCD_ATTR_OHCI
 
 #elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX)
   #define HCD_ATTR_EHCI_TRANSDIMENSION
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 76c1ba078..8e9628cb2 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -32,12 +32,16 @@
 #include "host/usbh.h"
 #include "host/usbh_classdriver.h"
 #include "hub.h"
-#include "usbh_hcd.h"
 
 //--------------------------------------------------------------------+
 // USBH Configuration
 //--------------------------------------------------------------------+
 
+// TODO remove,update
+#ifndef CFG_TUH_EP_MAX
+#define CFG_TUH_EP_MAX          9
+#endif
+
 #ifndef CFG_TUH_TASK_QUEUE_SZ
 #define CFG_TUH_TASK_QUEUE_SZ   16
 #endif
@@ -45,6 +49,57 @@
 // Debug level of USBD
 #define USBH_DBG_LVL   2
 
+//--------------------------------------------------------------------+
+// USBH-HCD common data structure
+//--------------------------------------------------------------------+
+
+typedef struct {
+  //------------- port -------------//
+  uint8_t rhport;
+  uint8_t hub_addr;
+  uint8_t hub_port;
+  uint8_t speed;
+
+  //------------- device descriptor -------------//
+  uint16_t vendor_id;
+  uint16_t product_id;
+  uint8_t  ep0_packet_size;
+
+  //------------- configuration descriptor -------------//
+  // uint8_t interface_count; // bNumInterfaces alias
+
+  //------------- device -------------//
+  struct TU_ATTR_PACKED
+  {
+    uint8_t connected    : 1;
+    uint8_t addressed    : 1;
+    uint8_t configured   : 1;
+    uint8_t suspended    : 1;
+  };
+
+  volatile uint8_t state;            // device state, value from enum tusbh_device_state_t
+
+  uint8_t itf2drv[16];               // map interface number to driver (0xff is invalid)
+  uint8_t ep2drv[CFG_TUH_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid )
+
+  struct TU_ATTR_PACKED
+  {
+    volatile bool busy    : 1;
+    volatile bool stalled : 1;
+    volatile bool claimed : 1;
+
+    // TODO merge ep2drv here, 4-bit should be sufficient
+  }ep_status[CFG_TUH_EP_MAX][2];
+
+  // Mutex for claiming endpoint, only needed when using with preempted RTOS
+#if CFG_TUSB_OS != OPT_OS_NONE
+  osal_mutex_def_t mutexdef;
+  osal_mutex_t mutex;
+#endif
+
+} usbh_device_t;
+
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -130,7 +185,7 @@ static bool _usbh_initialized = false;
 
 // all devices including hub and zero-address TODO exclude device0 to save space
 // hub address start from CFG_TUH_DEVICE_MAX
-CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUH_DEVICE_MAX+1];
+CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[1+CFG_TUH_DEVICE_MAX+CFG_TUH_HUB];
 
 // Event queue
 // role device/host is used by OS NONE for mutex (disable usb isr)
@@ -139,7 +194,14 @@ static osal_queue_t _usbh_q;
 
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
-//------------- Helper Function Prototypes -------------//
+//------------- Helper Function -------------//
+
+TU_ATTR_ALWAYS_INLINE
+static inline usbh_device_t* get_device(uint8_t dev_addr)
+{
+  return &_usbh_devices[dev_addr];
+}
+
 static bool enum_new_device(hcd_event_t* event);
 static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port);
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
@@ -326,6 +388,16 @@ uint8_t* usbh_get_enum_buf(void)
 // HCD Event Handler
 //--------------------------------------------------------------------+
 
+void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info)
+{
+  usbh_device_t const* dev = get_device(dev_addr);
+
+  devtree_info->rhport   = dev->rhport;
+  devtree_info->hub_addr = dev->hub_addr;
+  devtree_info->hub_port = dev->hub_port;
+  devtree_info->speed    = dev->speed;
+}
+
 void hcd_event_handler(hcd_event_t const* event, bool in_isr)
 {
   switch (event->event_id)
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index 0bdb66fb5..9204576ac 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -29,7 +29,7 @@
 #if TUSB_OPT_HOST_ENABLED
 
 #include "tusb.h"
-#include "usbh_hcd.h"
+#include "usbh_classdriver.h"
 
 enum
 {
@@ -59,9 +59,7 @@ static usbh_control_xfer_t _ctrl_xfer;
 bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
 {
   // TODO need to claim the endpoint first
-
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
-  const uint8_t rhport = dev->rhport;
+  const uint8_t rhport = usbh_get_rhport(dev_addr);
 
   _ctrl_xfer.request     = (*request);
   _ctrl_xfer.buffer      = buffer;
@@ -89,8 +87,7 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
   (void) ep_addr;
   (void) xferred_bytes;
 
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
-  const uint8_t rhport = dev->rhport;
+  const uint8_t rhport = usbh_get_rhport(dev_addr);
 
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
diff --git a/src/host/usbh_hcd.h b/src/host/usbh_hcd.h
deleted file mode 100644
index 9f8d3407d..000000000
--- a/src/host/usbh_hcd.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/** \ingroup Group_HCD
- *  @{ */
-
-#ifndef _TUSB_USBH_HCD_H_
-#define _TUSB_USBH_HCD_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "common/tusb_common.h"
-#include "osal/osal.h"
-
-#ifndef CFG_TUH_EP_MAX
-#define CFG_TUH_EP_MAX          9
-#endif
-
-//--------------------------------------------------------------------+
-// USBH-HCD common data structure
-//--------------------------------------------------------------------+
-
-// TODO move to usbh.c
-typedef struct {
-  //------------- port -------------//
-  uint8_t rhport;
-  uint8_t hub_addr;
-  uint8_t hub_port;
-  uint8_t speed;
-
-  //------------- device descriptor -------------//
-  uint16_t vendor_id;
-  uint16_t product_id;
-  uint8_t  ep0_packet_size;
-
-  //------------- configuration descriptor -------------//
-  // uint8_t interface_count; // bNumInterfaces alias
-
-  //------------- device -------------//
-  struct TU_ATTR_PACKED
-  {
-    uint8_t connected    : 1;
-    uint8_t addressed    : 1;
-    uint8_t configured   : 1;
-    uint8_t suspended    : 1;
-  };
-
-  volatile uint8_t state;            // device state, value from enum tusbh_device_state_t
-
-  uint8_t itf2drv[16];               // map interface number to driver (0xff is invalid)
-  uint8_t ep2drv[CFG_TUH_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid )
-
-  struct TU_ATTR_PACKED
-  {
-    volatile bool busy    : 1;
-    volatile bool stalled : 1;
-    volatile bool claimed : 1;
-
-    // TODO merge ep2drv here, 4-bit should be sufficient
-  }ep_status[CFG_TUH_EP_MAX][2];
-
-  // Mutex for claiming endpoint, only needed when using with preempted RTOS
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_def_t mutexdef;
-  osal_mutex_t mutex;
-#endif
-
-} usbh_device_t;
-
-extern usbh_device_t _usbh_devices[CFG_TUH_DEVICE_MAX+1]; // including zero-address
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_USBH_HCD_H_ */
-
-/** @} */
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 4d240cc50..124d88ff3 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -34,7 +34,6 @@
 #include "osal/osal.h"
 
 #include "host/hcd.h"
-#include "host/usbh_hcd.h"
 #include "ehci_api.h"
 #include "ehci.h"
 
@@ -791,13 +790,16 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
     tu_memclr(p_qhd, sizeof(ehci_qhd_t));
   }
 
+  hcd_devtree_info_t devtree_info;
+  hcd_devtree_get_info(dev_addr, &devtree_info);
+
   uint8_t const xfer_type = ep_desc->bmAttributes.xfer;
   uint8_t const interval = ep_desc->bInterval;
 
   p_qhd->dev_addr           = dev_addr;
   p_qhd->fl_inactive_next_xact = 0;
   p_qhd->ep_number          = tu_edpt_number(ep_desc->bEndpointAddress);
-  p_qhd->ep_speed           = _usbh_devices[dev_addr].speed;
+  p_qhd->ep_speed           = devtree_info.speed;
   p_qhd->data_toggle_control= (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0;
   p_qhd->head_list_flag     = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static asyn list head
   p_qhd->max_packet_size    = ep_desc->wMaxPacketSize.size;
@@ -834,8 +836,8 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
     p_qhd->int_smask = p_qhd->fl_int_cmask = 0;
   }
 
-  p_qhd->fl_hub_addr     = _usbh_devices[dev_addr].hub_addr;
-  p_qhd->fl_hub_port     = _usbh_devices[dev_addr].hub_port;
+  p_qhd->fl_hub_addr     = devtree_info.hub_addr;
+  p_qhd->fl_hub_port     = devtree_info.hub_port;
   p_qhd->mult            = 1; // TODO not use high bandwidth/park mode yet
 
   //------------- HCD Management Data -------------//
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 73489c764..bcee34938 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -24,10 +24,9 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include <common/tusb_common.h>
+#include "host/hcd_attr.h"
 
-#if TUSB_OPT_HOST_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
+#if TUSB_OPT_HOST_ENABLED && defined(HCD_ATTR_OHCI)
 
 //--------------------------------------------------------------------+
 // INCLUDE
@@ -35,7 +34,6 @@
 #include "osal/osal.h"
 
 #include "host/hcd.h"
-#include "host/usbh_hcd.h"
 #include "ohci.h"
 
 // TODO remove
@@ -280,10 +278,13 @@ static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t ep_size, uint8_t
     tu_memclr(p_ed, sizeof(ohci_ed_t));
   }
 
+  hcd_devtree_info_t devtree_info;
+  hcd_devtree_get_info(dev_addr, &devtree_info);
+
   p_ed->dev_addr          = dev_addr;
   p_ed->ep_number         = ep_addr & 0x0F;
   p_ed->pid               = (xfer_type == TUSB_XFER_CONTROL) ? PID_FROM_TD : (tu_edpt_dir(ep_addr) ? PID_IN : PID_OUT);
-  p_ed->speed             = _usbh_devices[dev_addr].speed;
+  p_ed->speed             = devtree_info.speed;
   p_ed->is_iso            = (xfer_type == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
   p_ed->max_packet_size   = ep_size;
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index bbbf10a84..925f395e7 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -268,12 +268,6 @@
 #if TUSB_OPT_HOST_ENABLED
   #ifndef CFG_TUH_DEVICE_MAX
     #define CFG_TUH_DEVICE_MAX 1
-    #warning CFG_TUH_DEVICE_MAX is not defined, default value is 1
-  #endif
-
-  //------------- HUB CLASS -------------//
-  #if CFG_TUH_HUB && (CFG_TUH_DEVICE_MAX == 1)
-    #error There is no benefit enable hub with max device is 1. Please disable hub or increase CFG_TUH_DEVICE_MAX
   #endif
 
   #ifndef CFG_TUH_ENUMERATION_BUFSIZE

From 49278a4a9b784918d0878ec12af9964b39733e22 Mon Sep 17 00:00:00 2001
From: Adrian Hesketh <a-h@users.noreply.github.com>
Date: Mon, 23 Aug 2021 11:29:56 +0100
Subject: [PATCH 0369/2085] Minor README grammar updates

---
 README.rst | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/README.rst b/README.rst
index 2119c26d2..09de8fcb7 100644
--- a/README.rst
+++ b/README.rst
@@ -56,11 +56,11 @@ Here is the list of `Supported Devices`_ that can be used with provided examples
 Device Stack
 ============
 
-Supports multiple device configurations by dynamically changing usb descriptors. Low power functions such like suspend, resume, and remote wakeup. Following device classes are supported:
+Supports multiple device configurations by dynamically changing USB descriptors, low power functions such like suspend, resume, and remote wakeup. The following device classes are supported:
 
 -  Audio Class 2.0 (UAC2)
 -  Bluetooth Host Controller Interface (BTH HCI)
--  Communication Class (CDC)
+-  Communication Device Class (CDC)
 -  Device Firmware Update (DFU): DFU mode (WIP) and Runtinme
 -  Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ...
 -  Mass Storage Class (MSC): with multiple LUNs
@@ -70,7 +70,7 @@ Supports multiple device configurations by dynamically changing usb descriptors.
 -  Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file.
 -  `WebUSB <https://github.com/WICG/webusb>`__ with vendor-specific class
 
-If you have special need, `usbd_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. Here is how RPi team add their reset interface [raspberrypi/pico-sdk#197](https://github.com/raspberrypi/pico-sdk/pull/197)
+If you have a special requirement, `usbd_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. Here is how the RPi team added their reset interface [raspberrypi/pico-sdk#197](https://github.com/raspberrypi/pico-sdk/pull/197)
 
 Host Stack
 ==========
@@ -82,7 +82,7 @@ Host Stack
 OS Abstraction layer
 ====================
 
-TinyUSB is completely thread-safe by pushing all ISR events into a central queue, then process it later in the non-ISR context task function. It also uses semaphore/mutex to access shared resources such as CDC FIFO. Therefore the stack needs to use some of OS's basic APIs. Following OSes are already supported out of the box.
+TinyUSB is completely thread-safe by pushing all Interrupt Service Request (ISR) events into a central queue, then processing them later in the non-ISR context task function. It also uses semaphore/mutex to access shared resources such as Communication Device Class (CDC) FIFO. Therefore the stack needs to use some of the OS's basic APIs. Following OSes are already supported out of the box.
 
 - **No OS**
 - **FreeRTOS**

From a893e6d2a21f8824eb1000a97e28e47d659cb057 Mon Sep 17 00:00:00 2001
From: Adrian Hesketh <a-h@users.noreply.github.com>
Date: Mon, 23 Aug 2021 11:31:11 +0100
Subject: [PATCH 0370/2085] Update README.rst

---
 README.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.rst b/README.rst
index 09de8fcb7..79676c45a 100644
--- a/README.rst
+++ b/README.rst
@@ -113,7 +113,7 @@ License
 =======
 
 All TinyUSB sources in the ``src`` folder are licensed under MIT
-license, `Full license is here <LICENSE>`__. However, each file can be
+license, the `Full license is here <LICENSE>`__. However, each file can be
 individually licensed especially those in ``lib`` and ``hw/mcu`` folder.
 Please make sure you understand all the license term for files you use
 in your project.
@@ -132,7 +132,7 @@ in your project.
 .. _Contributors: CONTRIBUTORS.rst
 .. _Reference: docs/reference/index.rst
 .. _Supported Devices: docs/reference/supported.rst
-.. _Gettin Started: docs/reference/getting_started.rst
+.. _Getting Started: docs/reference/getting_started.rst
 .. _Concurrency: docs/reference/concurrency.rst
 .. _Contributing: docs/contributing/index.rst
 .. _Code of Conduct: CODE_OF_CONDUCT.rst

From 49bcbf0f5dc57cb11b77800ae7b31ea5e91ab18f Mon Sep 17 00:00:00 2001
From: Adrian Hesketh <a-h@users.noreply.github.com>
Date: Mon, 23 Aug 2021 11:32:12 +0100
Subject: [PATCH 0371/2085] Update README.rst

---
 README.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index 79676c45a..9a41e3ff1 100644
--- a/README.rst
+++ b/README.rst
@@ -100,7 +100,7 @@ Local Docs
 - `Reference`_
 
   - `Supported Devices`_
-  - `Gettin Started`_
+  - `Getting Started`_
   - `Concurrency`_
 
 - `Contributing`_

From 3309425211639121ce72784405106ab22c4a426e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 23 Aug 2021 19:56:53 +0700
Subject: [PATCH 0372/2085] sepearate CFG_TUH_DEVICE_MAX and CFG_TUH_HUB

separate dev0 from _usbh_devices pool to save sram
---
 examples/host/cdc_msc_hid/src/tusb_config.h |   3 +-
 src/class/cdc/cdc_host.c                    |   2 +
 src/class/hid/hid_host.c                    |   4 +-
 src/class/msc/msc_host.c                    |   5 +-
 src/host/hub.c                              |  36 ++++---
 src/host/usbh.c                             | 104 +++++++++++---------
 src/portable/ehci/ehci.c                    |   2 +-
 7 files changed, 93 insertions(+), 63 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index e2eb566bd..bc6c68e5b 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -80,7 +80,8 @@
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
 
-#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 5 : 1) // normal hub has 4 ports
+// max device support (excluding hub device)
+#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
 
 //------------- HID -------------//
 #define CFG_TUH_HID_EPIN_BUFSIZE    64
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index e14cb0bab..08b9bab99 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -240,6 +240,8 @@ bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 
 void cdch_close(uint8_t dev_addr)
 {
+  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
+
   cdch_data_t * p_cdc = get_itf(dev_addr);
   tu_memclr(p_cdc, sizeof(cdch_data_t));
 }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 915f0b21a..a9ea03de6 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -62,7 +62,7 @@ typedef struct
   hidh_interface_t instances[CFG_TUH_HID];
 } hidh_device_t;
 
-static hidh_device_t _hidh_dev[CFG_TUH_DEVICE_MAX-1];
+static hidh_device_t _hidh_dev[CFG_TUH_DEVICE_MAX];
 
 //------------- Internal prototypes -------------//
 
@@ -240,6 +240,8 @@ bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint3
 
 void hidh_close(uint8_t dev_addr)
 {
+  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
+
   hidh_device_t* hid_dev = get_dev(dev_addr);
   if (tuh_hid_umount_cb)
   {
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index c7669aa21..8069353cd 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -76,6 +76,7 @@ CFG_TUSB_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4)
 static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)];
 
+TU_ATTR_ALWAYS_INLINE
 static inline msch_interface_t* get_itf(uint8_t dev_addr)
 {
   return &_msch_itf[dev_addr-1];
@@ -291,11 +292,13 @@ bool tuh_msc_reset(uint8_t dev_addr)
 //--------------------------------------------------------------------+
 void msch_init(void)
 {
-  tu_memclr(_msch_itf, sizeof(msch_interface_t)*CFG_TUH_DEVICE_MAX);
+  tu_memclr(_msch_itf, sizeof(_msch_itf));
 }
 
 void msch_close(uint8_t dev_addr)
 {
+  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
+
   msch_interface_t* p_msc = get_itf(dev_addr);
 
   // invoke Application Callback
diff --git a/src/host/hub.c b/src/host/hub.c
index 65e747e41..fd4dbd04a 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -48,6 +48,12 @@ typedef struct
 CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB];
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
 
+TU_ATTR_ALWAYS_INLINE
+static inline hub_interface_t* get_itf(uint8_t dev_addr)
+{
+  return &hub_data[dev_addr-1-CFG_TUH_DEVICE_MAX];
+}
+
 #if CFG_TUSB_DEBUG
 static char const* const _hub_feature_str[] =
 {
@@ -167,21 +173,26 @@ bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf
   
   TU_ASSERT(usbh_edpt_open(rhport, dev_addr, desc_ep));
 
-  hub_data[dev_addr-1].itf_num = itf_desc->bInterfaceNumber;
-  hub_data[dev_addr-1].ep_in   = desc_ep->bEndpointAddress;
+  hub_interface_t* p_hub = get_itf(dev_addr);
+
+  p_hub->itf_num = itf_desc->bInterfaceNumber;
+  p_hub->ep_in   = desc_ep->bEndpointAddress;
 
   return true;
 }
 
 void hub_close(uint8_t dev_addr)
 {
-  tu_memclr(&hub_data[dev_addr-1], sizeof( hub_interface_t));
+  TU_VERIFY(dev_addr > CFG_TUH_DEVICE_MAX, );
+  hub_interface_t* p_hub = get_itf(dev_addr);
+
+  if (p_hub->ep_in) tu_memclr(p_hub, sizeof( hub_interface_t));
 }
 
 bool hub_status_pipe_queue(uint8_t dev_addr)
 {
-  hub_interface_t * p_hub = &hub_data[dev_addr-1];
-  return usbh_edpt_xfer(dev_addr, p_hub->ep_in, &p_hub->status_change, 1);
+  hub_interface_t* hub_itf = get_itf(dev_addr);
+  return usbh_edpt_xfer(dev_addr, hub_itf->ep_in, &hub_itf->status_change, 1);
 }
 
 
@@ -194,7 +205,7 @@ static bool config_port_power_complete (uint8_t dev_addr, tusb_control_request_t
 
 bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
-   hub_interface_t* p_hub = &hub_data[dev_addr-1];
+  hub_interface_t* p_hub = get_itf(dev_addr);
   TU_ASSERT(itf_num == p_hub->itf_num);
 
   // Get Hub Descriptor
@@ -222,7 +233,7 @@ static bool config_set_port_power (uint8_t dev_addr, tusb_control_request_t cons
   (void) request;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
-  hub_interface_t* p_hub = &hub_data[dev_addr-1];
+  hub_interface_t* p_hub = get_itf(dev_addr);
 
   // only use number of ports in hub descriptor
   descriptor_hub_desc_t const* desc_hub = (descriptor_hub_desc_t const*) _hub_buffer;
@@ -238,7 +249,7 @@ static bool config_set_port_power (uint8_t dev_addr, tusb_control_request_t cons
 static bool config_port_power_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
-   hub_interface_t* p_hub = &hub_data[dev_addr-1];
+   hub_interface_t* p_hub = get_itf(dev_addr);
 
   if (request->wIndex == p_hub->port_count)
   {
@@ -272,7 +283,7 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   (void) ep_addr;
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
 
-  hub_interface_t * p_hub = &hub_data[dev_addr-1];
+  hub_interface_t* p_hub = get_itf(dev_addr);
 
   TU_LOG2("  Port Status Change = 0x%02X\r\n", p_hub->status_change);
 
@@ -294,7 +305,8 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
 static bool connection_get_status_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
-  hub_interface_t * p_hub = &hub_data[dev_addr-1];
+
+  hub_interface_t* p_hub = get_itf(dev_addr);
   uint8_t const port_num = (uint8_t) request->wIndex;
 
   // Connection change
@@ -322,7 +334,7 @@ static bool connection_clear_conn_change_complete (uint8_t dev_addr, tusb_contro
 {
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
 
-  hub_interface_t * p_hub = &hub_data[dev_addr-1];
+  hub_interface_t* p_hub = get_itf(dev_addr);
   uint8_t const port_num = (uint8_t) request->wIndex;
 
   if ( p_hub->port_status.status.connection )
@@ -353,7 +365,7 @@ static bool connection_port_reset_complete (uint8_t dev_addr, tusb_control_reque
 {
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
 
-  // usbh_hub_t * p_hub = &hub_data[dev_addr-1];
+  // hub_interface_t* p_hub = get_itf(dev_addr);
   uint8_t const port_num = (uint8_t) request->wIndex;
 
   // submit attach event
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 8e9628cb2..52c552408 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -99,6 +99,14 @@ typedef struct {
 
 } usbh_device_t;
 
+typedef struct
+{
+  uint8_t rhport;
+  uint8_t hub_addr;
+  uint8_t hub_port;
+  uint8_t speed;
+} usbh_dev0_t;
+
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
@@ -106,6 +114,7 @@ typedef struct {
 
 // Invalid driver ID in itf2drv[] ep2drv[][] mapping
 enum { DRVID_INVALID = 0xFFu };
+enum { ADDR_INVALID  = 0xFFu };
 
 #if CFG_TUSB_DEBUG >= 2
   #define DRIVER_NAME(_name)    .name = _name,
@@ -183,9 +192,12 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
 static bool _usbh_initialized = false;
 
+// Device with address = 0 for enumeration
+static usbh_dev0_t _dev0;
+
 // all devices including hub and zero-address TODO exclude device0 to save space
-// hub address start from CFG_TUH_DEVICE_MAX
-CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[1+CFG_TUH_DEVICE_MAX+CFG_TUH_HUB];
+// hub address start from CFG_TUH_DEVICE_MAX+1
+CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[1 + CFG_TUH_DEVICE_MAX + CFG_TUH_HUB];
 
 // Event queue
 // role device/host is used by OS NONE for mutex (disable usb isr)
@@ -214,13 +226,13 @@ extern bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 //--------------------------------------------------------------------+
 bool tuh_device_configured(uint8_t dev_addr)
 {
-  return _usbh_devices[dev_addr].configured;
+  return get_device(dev_addr)->configured;
 }
 
 tusb_speed_t tuh_device_get_speed (uint8_t const dev_addr)
 {
-  TU_ASSERT( dev_addr <= CFG_TUH_DEVICE_MAX, TUSB_SPEED_INVALID);
-  return (tusb_speed_t) _usbh_devices[dev_addr].speed;
+  TU_ASSERT( dev_addr <= CFG_TUH_DEVICE_MAX + CFG_TUH_HUB, TUSB_SPEED_INVALID);
+  return (tusb_speed_t) get_device(dev_addr)->speed;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -250,15 +262,16 @@ bool tuh_init(uint8_t rhport)
   TU_LOG2("USBH init\r\n");
 
   tu_memclr(_usbh_devices, sizeof(_usbh_devices));
+  tu_memclr(&_dev0, sizeof(_dev0));
 
   //------------- Enumeration & Reporter Task init -------------//
   _usbh_q = osal_queue_create( &_usbh_qdef );
   TU_ASSERT(_usbh_q != NULL);
 
   //------------- Semaphore, Mutex for Control Pipe -------------//
-  for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX+1; i++) // including address zero
+  for(uint8_t i=0; i<TU_ARRAY_SIZE(_usbh_devices); i++)
   {
-    usbh_device_t * const dev = &_usbh_devices[i];
+    usbh_device_t * dev = &_usbh_devices[i];
 
 #if CFG_TUSB_OS != OPT_OS_NONE
     dev->mutex = osal_mutex_create(&dev->mutexdef);
@@ -460,7 +473,7 @@ void hcd_event_device_remove(uint8_t hostid, bool in_isr)
 void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
 {
   //------------- find the all devices (star-network) under port that is unplugged -------------//
-  for (uint8_t dev_addr = 0; dev_addr <= CFG_TUH_DEVICE_MAX; dev_addr ++)
+  for (uint8_t dev_addr = 0; dev_addr < TU_ARRAY_SIZE(_usbh_devices); dev_addr ++)
   {
     usbh_device_t* dev = &_usbh_devices[dev_addr];
 
@@ -493,13 +506,17 @@ void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port
 //--------------------------------------------------------------------+
 // INTERNAL HELPER
 //--------------------------------------------------------------------+
-static uint8_t get_new_address(void)
+static uint8_t get_new_address(bool is_hub)
 {
-  for (uint8_t addr=1; addr <= CFG_TUH_DEVICE_MAX; addr++)
+  uint8_t const start = (is_hub ? CFG_TUH_DEVICE_MAX : 0) + 1;
+  uint8_t const count = (is_hub ? CFG_TUH_HUB : CFG_TUH_DEVICE_MAX);
+
+  for (uint8_t i=0; i < count; i++)
   {
+    uint8_t const addr = start + i;
     if (_usbh_devices[addr].state == TUSB_DEVICE_STATE_UNPLUG) return addr;
   }
-  return CFG_TUH_DEVICE_MAX+1;
+  return ADDR_INVALID;
 }
 
 void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
@@ -561,12 +578,11 @@ static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tusb_control_reques
 {
   (void) dev_addr; (void) request;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
-  usbh_device_t* dev0 = &_usbh_devices[0];
 
   enum_request_set_addr();
 
   // done with hub, waiting for next data on status pipe
-  (void) hub_status_pipe_queue( dev0->hub_addr );
+  (void) hub_status_pipe_queue( _dev0.hub_addr );
 
   return true;
 }
@@ -575,7 +591,6 @@ static bool enum_hub_get_status1_complete(uint8_t dev_addr, tusb_control_request
 {
   (void) dev_addr; (void) request;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
-  usbh_device_t* dev0 = &_usbh_devices[0];
 
   hub_port_status_response_t port_status;
   memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
@@ -583,7 +598,7 @@ static bool enum_hub_get_status1_complete(uint8_t dev_addr, tusb_control_request
   // Acknowledge Port Reset Change if Reset Successful
   if (port_status.change.reset)
   {
-    TU_ASSERT( hub_port_clear_feature(dev0->hub_addr, dev0->hub_port, HUB_FEATURE_PORT_RESET_CHANGE, enum_hub_clear_reset1_complete) );
+    TU_ASSERT( hub_port_clear_feature(_dev0.hub_addr, _dev0.hub_port, HUB_FEATURE_PORT_RESET_CHANGE, enum_hub_clear_reset1_complete) );
   }
 
   return true;
@@ -593,7 +608,6 @@ static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request
 {
   (void) dev_addr; (void) request;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
-  usbh_device_t* dev0 = &_usbh_devices[0];
 
   hub_port_status_response_t port_status;
   memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
@@ -604,13 +618,13 @@ static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request
     return hub_status_pipe_queue(dev_addr);
   }
 
-  dev0->speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH :
+  _dev0.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH :
                 (port_status.status.low_speed ) ? TUSB_SPEED_LOW  : TUSB_SPEED_FULL;
 
   // Acknowledge Port Reset Change
   if (port_status.change.reset)
   {
-    hub_port_clear_feature(dev0->hub_addr, dev0->hub_port, HUB_FEATURE_PORT_RESET_CHANGE, enum_hub_clear_reset0_complete);
+    hub_port_clear_feature(_dev0.hub_addr, _dev0.hub_port, HUB_FEATURE_PORT_RESET_CHANGE, enum_hub_clear_reset0_complete);
   }
 
   return true;
@@ -619,21 +633,22 @@ static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request
 
 static bool enum_request_set_addr(void)
 {
-  // Set Address
-  uint8_t const new_addr = get_new_address();
-  TU_ASSERT(new_addr <= CFG_TUH_DEVICE_MAX); // TODO notify application we reach max devices
+  tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+
+  // Get new address
+  uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
+  TU_ASSERT(new_addr != ADDR_INVALID);
 
   TU_LOG2("Set Address = %d\r\n", new_addr);
 
-  usbh_device_t* dev0    = &_usbh_devices[0];
   usbh_device_t* new_dev = &_usbh_devices[new_addr];
 
-  new_dev->rhport          = dev0->rhport;
-  new_dev->hub_addr        = dev0->hub_addr;
-  new_dev->hub_port        = dev0->hub_port;
-  new_dev->speed           = dev0->speed;
+  new_dev->rhport          = _dev0.rhport;
+  new_dev->hub_addr        = _dev0.hub_addr;
+  new_dev->hub_port        = _dev0.hub_port;
+  new_dev->speed           = _dev0.speed;
   new_dev->connected       = 1;
-  new_dev->ep0_packet_size = ((tusb_desc_device_t*) _usbh_ctrl_buf)->bMaxPacketSize0;
+  new_dev->ep0_packet_size = desc_device->bMaxPacketSize0;
 
   tusb_control_request_t const new_request =
   {
@@ -656,22 +671,20 @@ static bool enum_request_set_addr(void)
 
 static bool enum_new_device(hcd_event_t* event)
 {
-  usbh_device_t* dev0 = &_usbh_devices[0];
-  dev0->rhport   = event->rhport; // TODO refractor integrate to device_pool
-  dev0->hub_addr = event->connection.hub_addr;
-  dev0->hub_port = event->connection.hub_port;
-  dev0->state    = TUSB_DEVICE_STATE_UNPLUG;
+  _dev0.rhport   = event->rhport; // TODO refractor integrate to device_pool
+  _dev0.hub_addr = event->connection.hub_addr;
+  _dev0.hub_port = event->connection.hub_port;
 
   //------------- connected/disconnected directly with roothub -------------//
-  if (dev0->hub_addr == 0)
+  if (_dev0.hub_addr == 0)
   {
     // wait until device is stable TODO non blocking
     osal_task_delay(RESET_DELAY);
 
     // device unplugged while delaying
-    if ( !hcd_port_connect_status(dev0->rhport) ) return true;
+    if ( !hcd_port_connect_status(_dev0.rhport) ) return true;
 
-    dev0->speed = hcd_port_speed_get( dev0->rhport );
+    _dev0.speed = hcd_port_speed_get(_dev0.rhport );
 
     enum_request_addr0_device_desc();
   }
@@ -681,7 +694,7 @@ static bool enum_new_device(hcd_event_t* event)
   {
     // wait until device is stable
     osal_task_delay(RESET_DELAY);
-    TU_ASSERT( hub_port_get_status(dev0->hub_addr, dev0->hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete) );
+    TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete) );
   }
 #endif // CFG_TUH_HUB
 
@@ -719,27 +732,26 @@ static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_r
   (void) request;
   TU_ASSERT(0 == dev_addr);
 
-  usbh_device_t* dev0 = &_usbh_devices[0];
-
   if (XFER_RESULT_SUCCESS != result)
   {
 #if CFG_TUH_HUB
     // TODO remove, waiting for next data on status pipe
-    if (dev0->hub_addr != 0) hub_status_pipe_queue(dev0->hub_addr);
+    if (_dev0.hub_addr != 0) hub_status_pipe_queue(_dev0.hub_addr);
 #endif
 
     return false;
   }
 
-  TU_ASSERT(tu_desc_type(_usbh_ctrl_buf) == TUSB_DESC_DEVICE);
+  tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+  TU_ASSERT( tu_desc_type(desc_device) == TUSB_DESC_DEVICE );
 
   // Reset device again before Set Address
   TU_LOG2("Port reset \r\n");
 
-  if (dev0->hub_addr == 0)
+  if (_dev0.hub_addr == 0)
   {
     // connected directly to roothub
-    hcd_port_reset( dev0->rhport ); // reset port after 8 byte descriptor
+    hcd_port_reset( _dev0.rhport ); // reset port after 8 byte descriptor
     osal_task_delay(RESET_DELAY);
 
     enum_request_set_addr();
@@ -748,12 +760,12 @@ static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_r
   else
   {
     // after RESET_DELAY the hub_port_reset() already complete
-    TU_ASSERT( hub_port_reset(dev0->hub_addr, dev0->hub_port, NULL) );
+    TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, NULL) );
     osal_task_delay(RESET_DELAY);
 
     tuh_task(); // FIXME temporarily to clean up port_reset control transfer
 
-    TU_ASSERT( hub_port_get_status(dev0->hub_addr, dev0->hub_port, _usbh_ctrl_buf, enum_hub_get_status1_complete) );
+    TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status1_complete) );
   }
 #endif
 
@@ -772,9 +784,7 @@ static bool enum_set_address_complete(uint8_t dev_addr, tusb_control_request_t c
   new_dev->addressed = 1;
 
   // TODO close device 0, may not be needed
-  usbh_device_t* dev0 = &_usbh_devices[0];
-  hcd_device_close(dev0->rhport, 0);
-  dev0->state = TUSB_DEVICE_STATE_UNPLUG;
+  hcd_device_close(_dev0.rhport, 0);
 
   // open control pipe for new address
   TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_packet_size) );
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 124d88ff3..e3b7499cc 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -71,7 +71,7 @@ typedef struct
   struct {
     ehci_qhd_t qhd;
     ehci_qtd_t qtd;
-  }control[CFG_TUH_DEVICE_MAX+1];
+  }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
 
   ehci_qhd_t qhd_pool[HCD_MAX_ENDPOINT];
   ehci_qtd_t qtd_pool[HCD_MAX_XFER] TU_ATTR_ALIGNED(32);

From 353c070d00a31ef9eed1e701d4048414fe704738 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 24 Aug 2021 01:06:05 +0700
Subject: [PATCH 0373/2085] exclude dev0 from usbh devices pool

---
 src/class/cdc/cdc_host.c |  2 +-
 src/class/hid/hid_host.c |  3 ++-
 src/host/usbh.c          | 41 ++++++++++++++++++++--------------------
 3 files changed, 24 insertions(+), 22 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 08b9bab99..e7eaf4d05 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -146,7 +146,7 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_co
 //--------------------------------------------------------------------+
 void cdch_init(void)
 {
-  tu_memclr(cdch_data, sizeof(cdch_data_t)*CFG_TUH_DEVICE_MAX);
+  tu_memclr(cdch_data, sizeof(cdch_data));
 }
 
 bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index a9ea03de6..3a832a247 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -243,9 +243,10 @@ void hidh_close(uint8_t dev_addr)
   TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
 
   hidh_device_t* hid_dev = get_dev(dev_addr);
+
   if (tuh_hid_umount_cb)
   {
-    for ( uint8_t inst = 0; inst < hid_dev->inst_count; inst++ ) tuh_hid_umount_cb(dev_addr, inst);
+    for (uint8_t inst = 0; inst < hid_dev->inst_count; inst++ ) tuh_hid_umount_cb(dev_addr, inst);
   }
 
   tu_memclr(hid_dev, sizeof(hidh_device_t));
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 52c552408..fde51f5c9 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -195,9 +195,9 @@ static bool _usbh_initialized = false;
 // Device with address = 0 for enumeration
 static usbh_dev0_t _dev0;
 
-// all devices including hub and zero-address TODO exclude device0 to save space
+// all devices excluding zero-address
 // hub address start from CFG_TUH_DEVICE_MAX+1
-CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[1 + CFG_TUH_DEVICE_MAX + CFG_TUH_HUB];
+CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUH_DEVICE_MAX + CFG_TUH_HUB];
 
 // Event queue
 // role device/host is used by OS NONE for mutex (disable usb isr)
@@ -211,7 +211,7 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_EN
 TU_ATTR_ALWAYS_INLINE
 static inline usbh_device_t* get_device(uint8_t dev_addr)
 {
-  return &_usbh_devices[dev_addr];
+  return &_usbh_devices[dev_addr-1];
 }
 
 static bool enum_new_device(hcd_event_t* event);
@@ -350,7 +350,7 @@ void tuh_task(void)
 
       case HCD_EVENT_XFER_COMPLETE:
       {
-        usbh_device_t* dev = &_usbh_devices[event.dev_addr];
+        usbh_device_t* dev    = get_device(event.dev_addr);
         uint8_t const ep_addr = event.xfer_complete.ep_addr;
         uint8_t const epnum   = tu_edpt_number(ep_addr);
         uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
@@ -389,7 +389,7 @@ void tuh_task(void)
 
 uint8_t usbh_get_rhport(uint8_t dev_addr)
 {
-  return _usbh_devices[dev_addr].rhport;
+  return get_device(dev_addr)->rhport;
 }
 
 uint8_t* usbh_get_enum_buf(void)
@@ -473,9 +473,10 @@ void hcd_event_device_remove(uint8_t hostid, bool in_isr)
 void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
 {
   //------------- find the all devices (star-network) under port that is unplugged -------------//
-  for (uint8_t dev_addr = 0; dev_addr < TU_ARRAY_SIZE(_usbh_devices); dev_addr ++)
+  for ( uint8_t dev_id = 0; dev_id < TU_ARRAY_SIZE(_usbh_devices); dev_id++ )
   {
-    usbh_device_t* dev = &_usbh_devices[dev_addr];
+    usbh_device_t* dev = &_usbh_devices[dev_id];
+    uint8_t const dev_addr = dev_id+1;
 
     // TODO Hub multiple level
     if (dev->rhport == rhport   &&
@@ -514,14 +515,14 @@ static uint8_t get_new_address(bool is_hub)
   for (uint8_t i=0; i < count; i++)
   {
     uint8_t const addr = start + i;
-    if (_usbh_devices[addr].state == TUSB_DEVICE_STATE_UNPLUG) return addr;
+    if (get_device(addr)->state == TUSB_DEVICE_STATE_UNPLUG) return addr;
   }
   return ADDR_INVALID;
 }
 
 void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
 {
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
+  usbh_device_t* dev = get_device(dev_addr);
 
   for(itf_num++; itf_num < sizeof(dev->itf2drv); itf_num++)
   {
@@ -641,7 +642,7 @@ static bool enum_request_set_addr(void)
 
   TU_LOG2("Set Address = %d\r\n", new_addr);
 
-  usbh_device_t* new_dev = &_usbh_devices[new_addr];
+  usbh_device_t* new_dev = get_device(new_addr);
 
   new_dev->rhport          = _dev0.rhport;
   new_dev->hub_addr        = _dev0.hub_addr;
@@ -780,7 +781,7 @@ static bool enum_set_address_complete(uint8_t dev_addr, tusb_control_request_t c
 
   uint8_t const new_addr = (uint8_t const) request->wValue;
 
-  usbh_device_t* new_dev = &_usbh_devices[new_addr];
+  usbh_device_t* new_dev = get_device(new_addr);
   new_dev->addressed = 1;
 
   // TODO close device 0, may not be needed
@@ -816,7 +817,7 @@ static bool enum_get_device_desc_complete(uint8_t dev_addr, tusb_control_request
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
+  usbh_device_t* dev = get_device(dev_addr);
 
   dev->vendor_id  = desc_device->idVendor;
   dev->product_id = desc_device->idProduct;
@@ -914,7 +915,7 @@ static bool enum_set_config_complete(uint8_t dev_addr, tusb_control_request_t co
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   TU_LOG2("Device configured\r\n");
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
+  usbh_device_t* dev = get_device(dev_addr);
   dev->configured = 1;
   dev->state = TUSB_DEVICE_STATE_CONFIGURED;
 
@@ -929,7 +930,7 @@ static bool enum_set_config_complete(uint8_t dev_addr, tusb_control_request_t co
 
 static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
 {
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
+  usbh_device_t* dev = get_device(dev_addr);
 
   uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
   uint8_t const* p_desc   = tu_desc_next(desc_cfg);
@@ -1023,7 +1024,7 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
+  usbh_device_t* dev = get_device(dev_addr);
 
 #if CFG_TUSB_OS != OPT_OS_NONE
   // pre-check to help reducing mutex lock
@@ -1051,7 +1052,7 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
+  usbh_device_t* dev = get_device(dev_addr);
 
 #if CFG_TUSB_OS != OPT_OS_NONE
   osal_mutex_lock(dev->mutex, OSAL_TIMEOUT_WAIT_FOREVER);
@@ -1077,7 +1078,7 @@ bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
+  usbh_device_t* dev = get_device(dev_addr);
 
   TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
 
@@ -1117,12 +1118,12 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
     .bInterval        = 0
   };
 
-  return hcd_edpt_open(_usbh_devices[dev_addr].rhport, dev_addr, &ep0_desc);
+  return hcd_edpt_open(get_device(dev_addr)->rhport, dev_addr, &ep0_desc);
 }
 
 bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
 {
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
+  usbh_device_t* dev = get_device(dev_addr);
   TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) dev->speed));
 
   return hcd_edpt_open(rhport, dev_addr, desc_ep);
@@ -1133,7 +1134,7 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  usbh_device_t* dev = &_usbh_devices[dev_addr];
+  usbh_device_t* dev = get_device(dev_addr);
 
   return dev->ep_status[epnum][dir].busy;
 }

From 8dc16dd3a73dc2dd85dafd7460ba19cff2579fed Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 24 Aug 2021 01:19:06 +0700
Subject: [PATCH 0374/2085] fix rp2040 build

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 2c007ddd3..34803c674 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -39,7 +39,6 @@
 
 #include "host/hcd.h"
 #include "host/usbh.h"
-#include "host/usbh_hcd.h"
 
 #define ROOT_PORT 0
 

From 86201f77be1c2fc058f7896b99d6069b4b0b12a5 Mon Sep 17 00:00:00 2001
From: Greg Steiert <greg.steiert@nxp.com>
Date: Mon, 23 Aug 2021 16:17:57 -0700
Subject: [PATCH 0375/2085] initial commit of support for K32L2B

---
 hw/bsp/board_mcu.h               |   3 +-
 hw/bsp/frdm_k32l2b/board.h       |  58 +++++++++++
 hw/bsp/frdm_k32l2b/board.mk      |  51 +++++++++
 hw/bsp/frdm_k32l2b/frdm_k32l2b.c | 174 +++++++++++++++++++++++++++++++
 src/device/dcd_attr.h            |   2 +-
 src/portable/nxp/khci/dcd_khci.c |   4 +-
 src/tusb_option.h                |   1 +
 7 files changed, 290 insertions(+), 3 deletions(-)
 create mode 100644 hw/bsp/frdm_k32l2b/board.h
 create mode 100644 hw/bsp/frdm_k32l2b/board.mk
 create mode 100644 hw/bsp/frdm_k32l2b/frdm_k32l2b.c

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index acfd7348d..8cc50c808 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -46,7 +46,8 @@
   #include "chip.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
-      CFG_TUSB_MCU == OPT_MCU_LPC55XX  || CFG_TUSB_MCU == OPT_MCU_MKL25ZXX
+      CFG_TUSB_MCU == OPT_MCU_LPC55XX  || CFG_TUSB_MCU == OPT_MCU_MKL25ZXX || \
+      CFG_TUSB_MCU == OPT_MCU_K32L2BXX
   #include "fsl_device_registers.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
diff --git a/hw/bsp/frdm_k32l2b/board.h b/hw/bsp/frdm_k32l2b/board.h
new file mode 100644
index 000000000..60bc03fbd
--- /dev/null
+++ b/hw/bsp/frdm_k32l2b/board.h
@@ -0,0 +1,58 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "fsl_device_registers.h"
+
+// LED
+//#define LED_PINMUX            IOMUXC_GPIO_11_GPIOMUX_IO11
+//#define LED_PIN_CLOCK         kCLOCK_PortB
+#define LED_GPIO              GPIOD
+#define LED_PORT              PORTD
+#define LED_PIN               5
+#define LED_STATE_ON          0
+
+// SW3 button1
+//#define BUTTON_PINMUX         IOMUXC_GPIO_SD_05_GPIO2_IO05
+//#define BUTTON_PIN_CLOCK      kCLOCK_PortC
+#define BUTTON_GPIO           GPIOC
+#define BUTTON_PORT           PORTC
+#define BUTTON_PIN            3
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_PORT             LPUART0
+//#define UART_PIN_CLOCK        kCLOCK_PortA
+#define UART_PIN_PORT         PORTA
+#define UART_PIN_RX           1u
+#define UART_PIN_TX           2u
+#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */
+#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/frdm_k32l2b/board.mk b/hw/bsp/frdm_k32l2b/board.mk
new file mode 100644
index 000000000..56df553da
--- /dev/null
+++ b/hw/bsp/frdm_k32l2b/board.mk
@@ -0,0 +1,51 @@
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+DEPS_SUBMODULES += $(SDK_DIR)
+
+CFLAGS += \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0plus \
+  -DCPU_K32L2B31VLH0A \
+  -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter
+
+MCU_DIR = $(SDK_DIR)/devices/K32L2B31A
+
+# All source paths should be relative to the top level.
+LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
+
+SRC_C += \
+	src/portable/nxp/khci/dcd_khci.c \
+	$(MCU_DIR)/system_K32L2B31A.c \
+	$(MCU_DIR)/project_template/clock_config.c \
+	$(MCU_DIR)/drivers/fsl_clock.c \
+	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
+
+INC += \
+	$(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(SDK_DIR)/CMSIS/Include \
+	$(TOP)/$(SDK_DIR)/drivers/smc \
+	$(TOP)/$(SDK_DIR)/drivers/common \
+	$(TOP)/$(SDK_DIR)/drivers/gpio \
+	$(TOP)/$(SDK_DIR)/drivers/port \
+	$(TOP)/$(SDK_DIR)/drivers/lpuart \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/drivers \
+	$(TOP)/$(MCU_DIR)/project_template \
+
+SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM0
+
+# For flash-jlink target
+JLINK_DEVICE = MKL25Z128xxx4
+
+# For flash-pyocd target
+PYOCD_TARGET = K32L2B
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
new file mode 100644
index 000000000..c5e92d37d
--- /dev/null
+++ b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
@@ -0,0 +1,174 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ * Copyright (c) 2020, Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../board.h"
+#include "board.h"
+#include "fsl_gpio.h"
+#include "fsl_port.h"
+#include "fsl_clock.h"
+#include "fsl_lpuart.h"
+
+#include "clock_config.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+/*
+//#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
+#define LED_PORT              GPIOB
+#define LED_PIN_CLOCK         kCLOCK_PortD
+#define LED_PIN_PORT          PORTD
+#define LED_PIN               5U
+#define LED_PIN_FUNCTION      kPORT_MuxAsGpio
+#define LED_STATE_ON          0
+
+// UART
+#define UART_PORT             LPUART0
+#define UART_PIN_CLOCK        kCLOCK_PortA
+#define UART_PIN_PORT         PORTA
+#define UART_PIN_RX           1u
+#define UART_PIN_TX           2u
+#define UART_PIN_FUNCTION     kPORT_MuxAlt2
+*/
+//#define SOPT5_UART0RXSRC_UART_RX      0x00u   /*!< UART0 receive data source select: UART0_RX pin */
+//#define SOPT5_UART0TXSRC_UART_TX      0x00u   /*!< UART0 transmit data source select: UART0_TX pin */
+
+//const uint8_t dcd_data[] = { 0x00 };
+
+void board_init(void)
+{
+  /* Port A Clock Gate Control: Clock enabled */
+  CLOCK_EnableClock(kCLOCK_PortA);
+  /* Port B Clock Gate Control: Clock enabled */
+  CLOCK_EnableClock(kCLOCK_PortB);
+  /* Port C Clock Gate Control: Clock enabled */
+  CLOCK_EnableClock(kCLOCK_PortC);
+  /* Port D Clock Gate Control: Clock enabled */
+  CLOCK_EnableClock(kCLOCK_PortD);
+  /* Port E Clock Gate Control: Clock enabled */
+  CLOCK_EnableClock(kCLOCK_PortE);
+
+  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
+  GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
+  PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio);
+
+  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
+  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
+  const port_pin_config_t BUTTON_CFG = {
+    kPORT_PullUp, 
+    kPORT_FastSlewRate, 
+    kPORT_PassiveFilterDisable, 
+    kPORT_LowDriveStrength, 
+    kPORT_MuxAsGpio
+  };
+  PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
+
+  /* PORTA1 (pin 23) is configured as LPUART0_RX */
+  PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2);
+  /* PORTA2 (pin 24) is configured as LPUART0_TX */
+  PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2);
+  
+  SIM->SOPT5 = ((SIM->SOPT5 &
+               /* Mask bits to zero which are setting */
+               (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
+               /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
+               | SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)
+               /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
+               | SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
+
+  BOARD_BootClockRUN();
+  SystemCoreClockUpdate();
+  CLOCK_SetLpuart0Clock(1);
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  lpuart_config_t uart_config;
+  LPUART_GetDefaultConfig(&uart_config);
+  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
+  uart_config.enableTx = true;
+  uart_config.enableRx = true;
+  LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk));
+
+  // USB
+//  SystemCoreClockUpdate();
+  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
+//  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  LPUART_ReadBlocking(UART_PORT, buf, len);
+  return len;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 7772a6d96..a35fc0ac5 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -60,7 +60,7 @@
 #elif TU_CHECK_MCU(MIMXRT10XX)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(MKL25ZXX)
+#elif TU_CHECK_MCU(MKL25ZXX) || TU_CHECK_MCU(K32L2BXX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 //------------- Nordic -------------//
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 519b8fb7b..dce464fd2 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -26,7 +26,9 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX )
+#if TUSB_OPT_DEVICE_ENABLED && ( \
+      ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \
+    )
 
 #include "fsl_device_registers.h"
 #define KHCI        USB0
diff --git a/src/tusb_option.h b/src/tusb_option.h
index e189c65bb..d551765ae 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -108,6 +108,7 @@
 
 // NXP Kinetis
 #define OPT_MCU_MKL25ZXX         1200 ///< NXP MKL25Zxx
+#define OPT_MCU_K32L2BXX         1201 ///< NXP K32L2Bxx
 
 // Silabs
 #define OPT_MCU_EFM32GG          1300 ///< Silabs EFM32GG

From 5bd7788950c8e7118d2394e7821f0486ca66aaab Mon Sep 17 00:00:00 2001
From: Greg Steiert <greg.steiert@nxp.com>
Date: Mon, 23 Aug 2021 16:36:58 -0700
Subject: [PATCH 0376/2085] cleaned up unused code, only enalbing port clocks
 as needed

---
 hw/bsp/frdm_k32l2b/board.h       |  8 +++---
 hw/bsp/frdm_k32l2b/frdm_k32l2b.c | 42 +++-----------------------------
 2 files changed, 7 insertions(+), 43 deletions(-)

diff --git a/hw/bsp/frdm_k32l2b/board.h b/hw/bsp/frdm_k32l2b/board.h
index 60bc03fbd..825367915 100644
--- a/hw/bsp/frdm_k32l2b/board.h
+++ b/hw/bsp/frdm_k32l2b/board.h
@@ -31,16 +31,14 @@
 #include "fsl_device_registers.h"
 
 // LED
-//#define LED_PINMUX            IOMUXC_GPIO_11_GPIOMUX_IO11
-//#define LED_PIN_CLOCK         kCLOCK_PortB
+#define LED_PIN_CLOCK         kCLOCK_PortD
 #define LED_GPIO              GPIOD
 #define LED_PORT              PORTD
 #define LED_PIN               5
 #define LED_STATE_ON          0
 
 // SW3 button1
-//#define BUTTON_PINMUX         IOMUXC_GPIO_SD_05_GPIO2_IO05
-//#define BUTTON_PIN_CLOCK      kCLOCK_PortC
+#define BUTTON_PIN_CLOCK      kCLOCK_PortC
 #define BUTTON_GPIO           GPIOC
 #define BUTTON_PORT           PORTC
 #define BUTTON_PIN            3
@@ -48,7 +46,7 @@
 
 // UART
 #define UART_PORT             LPUART0
-//#define UART_PIN_CLOCK        kCLOCK_PortA
+#define UART_PIN_CLOCK        kCLOCK_PortA
 #define UART_PIN_PORT         PORTA
 #define UART_PIN_RX           1u
 #define UART_PIN_TX           2u
diff --git a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
index c5e92d37d..c45095caa 100644
--- a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
+++ b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
@@ -42,44 +42,12 @@ void USB0_IRQHandler(void)
   tud_int_handler(0);
 }
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-// LED
-/*
-//#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT              GPIOB
-#define LED_PIN_CLOCK         kCLOCK_PortD
-#define LED_PIN_PORT          PORTD
-#define LED_PIN               5U
-#define LED_PIN_FUNCTION      kPORT_MuxAsGpio
-#define LED_STATE_ON          0
-
-// UART
-#define UART_PORT             LPUART0
-#define UART_PIN_CLOCK        kCLOCK_PortA
-#define UART_PIN_PORT         PORTA
-#define UART_PIN_RX           1u
-#define UART_PIN_TX           2u
-#define UART_PIN_FUNCTION     kPORT_MuxAlt2
-*/
-//#define SOPT5_UART0RXSRC_UART_RX      0x00u   /*!< UART0 receive data source select: UART0_RX pin */
-//#define SOPT5_UART0TXSRC_UART_TX      0x00u   /*!< UART0 transmit data source select: UART0_TX pin */
-
-//const uint8_t dcd_data[] = { 0x00 };
-
 void board_init(void)
 {
-  /* Port A Clock Gate Control: Clock enabled */
-  CLOCK_EnableClock(kCLOCK_PortA);
-  /* Port B Clock Gate Control: Clock enabled */
-  CLOCK_EnableClock(kCLOCK_PortB);
-  /* Port C Clock Gate Control: Clock enabled */
-  CLOCK_EnableClock(kCLOCK_PortC);
-  /* Port D Clock Gate Control: Clock enabled */
-  CLOCK_EnableClock(kCLOCK_PortD);
-  /* Port E Clock Gate Control: Clock enabled */
-  CLOCK_EnableClock(kCLOCK_PortE);
+  /* Enable port clocks for UART/LED/Button pins */
+  CLOCK_EnableClock(UART_PIN_CLOCK);
+  CLOCK_EnableClock(LED_PIN_CLOCK);
+  CLOCK_EnableClock(BUTTON_PIN_CLOCK);
 
   gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
   GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
@@ -129,9 +97,7 @@ void board_init(void)
   LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk));
 
   // USB
-//  SystemCoreClockUpdate();
   CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
-//  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0, CLOCK_GetFreq(kCLOCK_PllFllSelClk));
 }
 
 //--------------------------------------------------------------------+

From 5d152503ee6c31c7cf3ad2dfeb9ac38c70c42bd4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 24 Aug 2021 12:16:23 +0700
Subject: [PATCH 0377/2085] fix dev0 out of bound array due to leftover

---
 src/host/usbh.c | 64 +++++++++++++++++++++++++++++++++----------------
 1 file changed, 43 insertions(+), 21 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index fde51f5c9..75ed13e87 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -211,6 +211,7 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_EN
 TU_ATTR_ALWAYS_INLINE
 static inline usbh_device_t* get_device(uint8_t dev_addr)
 {
+  TU_ASSERT(dev_addr, NULL);
   return &_usbh_devices[dev_addr-1];
 }
 
@@ -350,26 +351,35 @@ void tuh_task(void)
 
       case HCD_EVENT_XFER_COMPLETE:
       {
-        usbh_device_t* dev    = get_device(event.dev_addr);
         uint8_t const ep_addr = event.xfer_complete.ep_addr;
         uint8_t const epnum   = tu_edpt_number(ep_addr);
         uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
         TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
 
-        dev->ep_status[epnum][ep_dir].busy = false;
-        dev->ep_status[epnum][ep_dir].claimed = 0;
-
-        if ( 0 == epnum )
+        if (event.dev_addr == 0)
         {
+          // device 0 only has control endpoint
+          TU_ASSERT(epnum == 0, );
           usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
-        }else
+        }
+        else
         {
-          uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
-          TU_ASSERT(drv_id < USBH_CLASS_DRIVER_COUNT, );
+          usbh_device_t* dev = get_device(event.dev_addr);
+          dev->ep_status[epnum][ep_dir].busy = false;
+          dev->ep_status[epnum][ep_dir].claimed = 0;
 
-          TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
-          usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+          if ( 0 == epnum )
+          {
+            usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+          }else
+          {
+            uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
+            TU_ASSERT(drv_id < USBH_CLASS_DRIVER_COUNT, );
+
+            TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
+            usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+          }
         }
       }
       break;
@@ -389,7 +399,7 @@ void tuh_task(void)
 
 uint8_t usbh_get_rhport(uint8_t dev_addr)
 {
-  return get_device(dev_addr)->rhport;
+  return (dev_addr == 0) ? _dev0.rhport : get_device(dev_addr)->rhport;
 }
 
 uint8_t* usbh_get_enum_buf(void)
@@ -403,12 +413,21 @@ uint8_t* usbh_get_enum_buf(void)
 
 void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info)
 {
-  usbh_device_t const* dev = get_device(dev_addr);
+  if (dev_addr)
+  {
+    usbh_device_t const* dev = get_device(dev_addr);
 
-  devtree_info->rhport   = dev->rhport;
-  devtree_info->hub_addr = dev->hub_addr;
-  devtree_info->hub_port = dev->hub_port;
-  devtree_info->speed    = dev->speed;
+    devtree_info->rhport   = dev->rhport;
+    devtree_info->hub_addr = dev->hub_addr;
+    devtree_info->hub_port = dev->hub_port;
+    devtree_info->speed    = dev->speed;
+  }else
+  {
+    devtree_info->rhport   = _dev0.rhport;
+    devtree_info->hub_addr = _dev0.hub_addr;
+    devtree_info->hub_port = _dev0.hub_port;
+    devtree_info->speed    = _dev0.speed;
+  }
 }
 
 void hcd_event_handler(hcd_event_t const* event, bool in_isr)
@@ -473,6 +492,7 @@ void hcd_event_device_remove(uint8_t hostid, bool in_isr)
 void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
 {
   //------------- find the all devices (star-network) under port that is unplugged -------------//
+  // TODO mark as disconnected in ISR, also handle dev0
   for ( uint8_t dev_id = 0; dev_id < TU_ARRAY_SIZE(_usbh_devices); dev_id++ )
   {
     usbh_device_t* dev = &_usbh_devices[dev_id];
@@ -634,6 +654,7 @@ static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request
 
 static bool enum_request_set_addr(void)
 {
+  uint8_t const addr0 = 0;
   tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
 
   // Get new address
@@ -665,7 +686,7 @@ static bool enum_request_set_addr(void)
     .wLength  = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(0, &new_request, NULL, enum_set_address_complete) );
+  TU_ASSERT( tuh_control_xfer(addr0, &new_request, NULL, enum_set_address_complete) );
 
   return true;
 }
@@ -705,7 +726,8 @@ static bool enum_new_device(hcd_event_t* event)
 static bool enum_request_addr0_device_desc(void)
 {
   // TODO probably doesn't need to open/close each enumeration
-  TU_ASSERT( usbh_edpt_control_open(0, 8) );
+  uint8_t const addr0 = 0;
+  TU_ASSERT( usbh_edpt_control_open(addr0, 8) );
 
   //------------- Get first 8 bytes of device descriptor to get Control Endpoint Size -------------//
   TU_LOG2("Get 8 byte of Device Descriptor\r\n");
@@ -722,7 +744,7 @@ static bool enum_request_addr0_device_desc(void)
     .wIndex   = 0,
     .wLength  = 8
   };
-  TU_ASSERT( tuh_control_xfer(0, &request, _usbh_ctrl_buf, enum_get_addr0_device_desc_complete) );
+  TU_ASSERT( tuh_control_xfer(addr0, &request, _usbh_ctrl_buf, enum_get_addr0_device_desc_complete) );
 
   return true;
 }
@@ -1106,7 +1128,7 @@ bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_
 
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
 {
-  TU_LOG2("Open EP Control with Size = %u\r\n", max_packet_size);
+  TU_LOG2("Open EP0 with Size = %u (addr = %u)\r\n", max_packet_size, dev_addr);
 
   tusb_desc_endpoint_t ep0_desc =
   {
@@ -1118,7 +1140,7 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
     .bInterval        = 0
   };
 
-  return hcd_edpt_open(get_device(dev_addr)->rhport, dev_addr, &ep0_desc);
+  return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc);
 }
 
 bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)

From 88bb8fac3d555e390f59770200c73a13eb61504b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 24 Aug 2021 12:30:57 +0700
Subject: [PATCH 0378/2085] rename host API to be consistent with naming on
 device stack

- tuh_device_get_speed() to tuh_speed_get()
- tuh_device_configured() to tuh_mounted()
- tuh_device_ready() to tuh_ready()
---
 src/host/usbh.c                              |  4 ++--
 src/host/usbh.h                              | 17 ++++++++++++-----
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |  2 +-
 3 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 75ed13e87..1b5a422f4 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -225,12 +225,12 @@ extern bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 //--------------------------------------------------------------------+
 // PUBLIC API (Parameter Verification is required)
 //--------------------------------------------------------------------+
-bool tuh_device_configured(uint8_t dev_addr)
+bool tuh_mounted(uint8_t dev_addr)
 {
   return get_device(dev_addr)->configured;
 }
 
-tusb_speed_t tuh_device_get_speed (uint8_t const dev_addr)
+tusb_speed_t tuh_speed_get (uint8_t const dev_addr)
 {
   TU_ASSERT( dev_addr <= CFG_TUH_DEVICE_MAX + CFG_TUH_HUB, TUSB_SPEED_INVALID);
   return (tusb_speed_t) get_device(dev_addr)->speed;
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 4de6e7ba6..5f7229f27 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -57,16 +57,23 @@ void tuh_task(void);
 extern void hcd_int_handler(uint8_t rhport);
 #define tuh_int_handler   hcd_int_handler
 
-tusb_speed_t tuh_device_get_speed (uint8_t dev_addr);
+tusb_speed_t tuh_speed_get (uint8_t dev_addr);
 
-// Check if device is configured
-bool tuh_device_configured(uint8_t dev_addr);
+// Check if device is connected and configured
+bool tuh_mounted(uint8_t dev_addr);
+
+// Check if device is suspended
+static inline bool tuh_suspended(uint8_t dev_addr)
+{
+  // TODO implement suspend & resume on host
+  return false;
+}
 
 // Check if device is ready to communicate with
 TU_ATTR_ALWAYS_INLINE
-static inline bool tuh_device_ready(uint8_t dev_addr)
+static inline bool tuh_ready(uint8_t dev_addr)
 {
-  return tuh_device_configured(dev_addr);
+  return tuh_mounted(dev_addr) && !tuh_suspended(dev_addr);
 }
 
 // Carry out control transfer
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 34803c674..e51dfac2b 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -87,7 +87,7 @@ static bool need_pre(uint8_t dev_addr)
 {
     // If this device is different to the speed of the root device
     // (i.e. is a low speed device on a full speed hub) then need pre
-    return hcd_port_speed_get(0) != tuh_device_get_speed(dev_addr);
+    return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
 }
 
 static void hw_xfer_complete(struct hw_endpoint *ep, xfer_result_t xfer_result)

From 3c0c051df182cb7261e0f5eb6c52e84f860d0ae1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 24 Aug 2021 19:10:23 +0700
Subject: [PATCH 0379/2085] add tuh_vid_pid_get()

complete Sony PS4 dualshock controller example
---
 .../host/hid_controller/.only.MCU_LPC175X_6X  |   0
 .../host/hid_controller/.only.MCU_LPC177X_8X  |   0
 .../host/hid_controller/.only.MCU_LPC18XX     |   0
 .../host/hid_controller/.only.MCU_LPC40XX     |   0
 .../host/hid_controller/.only.MCU_LPC43XX     |   0
 .../host/hid_controller/.only.MCU_MIMXRT10XX  |   0
 examples/host/hid_controller/.only.MCU_RP2040 |   0
 examples/host/hid_controller/CMakeLists.txt   |  29 ++
 examples/host/hid_controller/Makefile         |  30 +++
 examples/host/hid_controller/src/hid_app.c    | 249 ++++++++++++++++++
 examples/host/hid_controller/src/main.c       |  93 +++++++
 .../host/hid_controller/src/tusb_config.h     |  95 +++++++
 src/class/hid/hid_host.c                      |   2 +-
 src/host/usbh.c                               | 116 ++++----
 src/host/usbh.h                               |   4 +-
 15 files changed, 569 insertions(+), 49 deletions(-)
 create mode 100644 examples/host/hid_controller/.only.MCU_LPC175X_6X
 create mode 100644 examples/host/hid_controller/.only.MCU_LPC177X_8X
 create mode 100644 examples/host/hid_controller/.only.MCU_LPC18XX
 create mode 100644 examples/host/hid_controller/.only.MCU_LPC40XX
 create mode 100644 examples/host/hid_controller/.only.MCU_LPC43XX
 create mode 100644 examples/host/hid_controller/.only.MCU_MIMXRT10XX
 create mode 100644 examples/host/hid_controller/.only.MCU_RP2040
 create mode 100644 examples/host/hid_controller/CMakeLists.txt
 create mode 100644 examples/host/hid_controller/Makefile
 create mode 100644 examples/host/hid_controller/src/hid_app.c
 create mode 100644 examples/host/hid_controller/src/main.c
 create mode 100644 examples/host/hid_controller/src/tusb_config.h

diff --git a/examples/host/hid_controller/.only.MCU_LPC175X_6X b/examples/host/hid_controller/.only.MCU_LPC175X_6X
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/hid_controller/.only.MCU_LPC177X_8X b/examples/host/hid_controller/.only.MCU_LPC177X_8X
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/hid_controller/.only.MCU_LPC18XX b/examples/host/hid_controller/.only.MCU_LPC18XX
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/hid_controller/.only.MCU_LPC40XX b/examples/host/hid_controller/.only.MCU_LPC40XX
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/hid_controller/.only.MCU_LPC43XX b/examples/host/hid_controller/.only.MCU_LPC43XX
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/hid_controller/.only.MCU_MIMXRT10XX b/examples/host/hid_controller/.only.MCU_MIMXRT10XX
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/hid_controller/.only.MCU_RP2040 b/examples/host/hid_controller/.only.MCU_RP2040
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
new file mode 100644
index 000000000..0a99bc3a9
--- /dev/null
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -0,0 +1,29 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
new file mode 100644
index 000000000..6f59faeee
--- /dev/null
+++ b/examples/host/hid_controller/Makefile
@@ -0,0 +1,30 @@
+include ../../../tools/top.mk
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += \
+	src/hid_app.c \
+	src/main.c
+	
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+CFLAGS += -Wno-error=cast-align
+
+# TinyUSB Host Stack source
+SRC_C += \
+	src/class/cdc/cdc_host.c \
+	src/class/hid/hid_host.c \
+	src/class/msc/msc_host.c \
+	src/host/hub.c \
+	src/host/usbh.c \
+	src/host/usbh_control.c \
+	src/portable/ehci/ehci.c \
+	src/portable/ohci/ohci.c \
+	src/portable/nxp/transdimension/hcd_transdimension.c \
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+
+include ../../rules.mk
diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
new file mode 100644
index 000000000..37ae94abd
--- /dev/null
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -0,0 +1,249 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board.h"
+#include "tusb.h"
+
+/* From https://www.kernel.org/doc/html/latest/input/gamepad.html
+          ____________________________              __
+         / [__ZL__]          [__ZR__] \               |
+        / [__ TL __]        [__ TR __] \              | Front Triggers
+     __/________________________________\__         __|
+    /                                  _   \          |
+   /      /\           __             (N)   \         |
+  /       ||      __  |MO|  __     _       _ \        | Main Pad
+ |    <===DP===> |SE|      |ST|   (W) -|- (E) |       |
+  \       ||    ___          ___       _     /        |
+  /\      \/   /   \        /   \     (S)   /\      __|
+ /  \________ | LS  | ____ |  RS | ________/  \       |
+|         /  \ \___/ /    \ \___/ /  \         |      | Control Sticks
+|        /    \_____/      \_____/    \        |    __|
+|       /                              \       |
+ \_____/                                \_____/
+
+     |________|______|    |______|___________|
+       D-Pad    Left       Right   Action Pad
+               Stick       Stick
+
+                 |_____________|
+                    Menu Pad
+
+  Most gamepads have the following features:
+  - Action-Pad 4 buttons in diamonds-shape (on the right side) NORTH, SOUTH, WEST and EAST.
+  - D-Pad (Direction-pad) 4 buttons (on the left side) that point up, down, left and right.
+  - Menu-Pad Different constellations, but most-times 2 buttons: SELECT - START.
+  - Analog-Sticks provide freely moveable sticks to control directions, Analog-sticks may also
+  provide a digital button if you press them.
+  - Triggers are located on the upper-side of the pad in vertical direction. The upper buttons
+  are normally named Left- and Right-Triggers, the lower buttons Z-Left and Z-Right.
+  - Rumble Many devices provide force-feedback features. But are mostly just simple rumble motors.
+ */
+
+// Sony DS4 report layout detail https://www.psdevwiki.com/ps4/DS4-USB
+typedef struct TU_ATTR_PACKED
+{
+  int8_t x, y, z, rz; // joystick
+
+  struct {
+    uint8_t dpad     : 4; // (hat format, 0x08 is released, 0=N, 1=NE, 2=E, 3=SE, 4=S, 5=SW, 6=W, 7=NW)
+    uint8_t square   : 1; // west
+    uint8_t cross    : 1; // south
+    uint8_t circle   : 1; // east
+    uint8_t triangle : 1; // north
+  };
+
+  struct {
+    uint8_t l1     : 1;
+    uint8_t r1     : 1;
+    uint8_t l2     : 1;
+    uint8_t r2     : 1;
+    uint8_t share  : 1;
+    uint8_t option : 1;
+    uint8_t l3     : 1;
+    uint8_t r3     : 1;
+  };
+
+  struct {
+    uint8_t ps      : 1; // playstation button
+    uint8_t tpad    : 1; // track pad click
+    uint8_t counter : 6; // +1 each report
+  };
+
+  // comment out since not used by this example
+  // uint8_t l2_trigger; // 0 released, 0xff fully pressed
+  // uint8_t r2_trigger; // as above
+
+  //  uint16_t timestamp;
+  //  uint8_t  battery;
+  //
+  //  int16_t gyro[3];  // x, y, z;
+  //  int16_t accel[3]; // x, y, z
+
+  // there is still lots more info
+
+} sony_ds4_report_t;
+
+// check if device is Sony DualShock 4
+static inline bool is_sony_ds4(uint8_t dev_addr)
+{
+  uint16_t vid, pid;
+  tuh_vid_pid_get(dev_addr, &vid, &pid);
+
+  return (vid == 0x054c && pid == 0x09cc);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+void hid_app_task(void)
+{
+  // nothing to do
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device with hid interface is mounted
+// Report descriptor is also available for use. tuh_hid_parse_report_descriptor()
+// can be used to parse common/simple enough descriptor.
+// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
+// therefore report_desc = NULL, desc_len = 0
+void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
+{
+  uint16_t vid, pid;
+  tuh_vid_pid_get(dev_addr, &vid, &pid);
+
+  printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance);
+  printf("VID = %04x, PID = %04x\r\n", vid, pid);
+
+  // Sony DualShock 4 [CUH-ZCT2x]
+  if ( is_sony_ds4(dev_addr) )
+  {
+    // request to receive report
+    // tuh_hid_report_received_cb() will be invoked when report is available
+    if ( !tuh_hid_receive_report(dev_addr, instance) )
+    {
+      printf("Error: cannot request to receive report\r\n");
+    }
+  }
+}
+
+// Invoked when device with hid interface is un-mounted
+void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
+{
+  printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+
+}
+
+// check if different than 2
+bool diff_than_2(int8_t x, int8_t y)
+{
+  return (x - y > 2) || (y - x > 2);
+}
+
+// check if 2 reports are different enough
+bool diff_report(sony_ds4_report_t const* rpt1, sony_ds4_report_t const* rpt2)
+{
+  bool result;
+
+  // x, y, z, rz must different than 2 to be counted
+  result = diff_than_2(rpt1->x, rpt2->x) || diff_than_2(rpt1->y , rpt2->y ) ||
+           diff_than_2(rpt1->z, rpt2->z) || diff_than_2(rpt1->rz, rpt2->rz);
+
+  // check the reset with mem compare
+  result |= memcmp(&rpt1->rz + 1, &rpt2->rz + 1, sizeof(sony_ds4_report_t)-4);
+
+  return result;
+}
+
+void process_sony_ds4(uint8_t const* report, uint16_t len)
+{
+  const char* dpad_str[] = { "N", "NE", "E", "SE", "S", "SW", "W", "NW", "none" };
+
+  // previous report used to compare for changes
+  static sony_ds4_report_t prev_report = { 0 };
+
+  uint8_t const report_id = report[0];
+  report++;
+  len--;
+
+  // all buttons state is stored in ID 1
+  if (report_id == 1)
+  {
+    sony_ds4_report_t ds4_report;
+    memcpy(&ds4_report, report, sizeof(ds4_report));
+
+    // counter is +1, assign to make it easier to compare 2 report
+    prev_report.counter = ds4_report.counter;
+
+    // only print if changes since it is polled ~ 5ms
+    // Since count+1 after each report and  x, y, z, rz fluctuate within 1 or 2
+    // We need more than memcmp to check if report is different enough
+    if ( diff_report(&prev_report, &ds4_report) )
+    {
+      printf("(x, y, z, rz) = (%d, %d, %d, %d)\r\n", ds4_report.x, ds4_report.y, ds4_report.z, ds4_report.rz);
+      printf("DPad = %s ", dpad_str[ds4_report.dpad]);
+
+      if (ds4_report.square   ) printf("Square ");
+      if (ds4_report.cross    ) printf("Cross ");
+      if (ds4_report.circle   ) printf("Circle ");
+      if (ds4_report.triangle ) printf("Triangle ");
+
+      if (ds4_report.l1) printf("L1 ");
+      if (ds4_report.r1) printf("R1 ");
+      if (ds4_report.l2) printf("L2 ");
+      if (ds4_report.r2) printf("R2 ");
+
+      if (ds4_report.share) printf("Share ");
+      if (ds4_report.option) printf("Option ");
+      if (ds4_report.l3) printf("L3 ");
+      if (ds4_report.r3) printf("R3 ");
+
+      if (ds4_report.ps       ) printf("PS ");
+      if (ds4_report.tpad     ) printf("TPad ");
+
+      printf("\r\n");
+    }
+
+    prev_report = ds4_report;
+  }
+}
+
+// Invoked when received report from device via interrupt endpoint
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
+{
+  if ( is_sony_ds4(dev_addr) )
+  {
+    process_sony_ds4(report, len);
+  }
+
+  // continue to request to receive report
+  if ( !tuh_hid_receive_report(dev_addr, instance) )
+  {
+    printf("Error: cannot request to receive report\r\n");
+  }
+}
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
new file mode 100644
index 000000000..e13fa818a
--- /dev/null
+++ b/examples/host/hid_controller/src/main.c
@@ -0,0 +1,93 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* This example current worked and tested with following controller
+ * - Sony DualShock 4 [CUH-ZCT2x] VID = 0x054c, PID = 0x09cc
+ */
+
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+void led_blinking_task(void);
+
+extern void cdc_task(void);
+extern void hid_app_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  printf("TinyUSB Host HID Controller Example\r\n");
+
+  tusb_init();
+
+  while (1)
+  {
+    // tinyusb host task
+    tuh_task();
+    led_blinking_task();
+
+#if CFG_TUH_CDC
+    cdc_task();
+#endif
+
+#if CFG_TUH_HID
+    hid_app_task();
+#endif
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  const uint32_t interval_ms = 1000;
+  static uint32_t start_ms = 0;
+
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  start_ms += interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
new file mode 100644
index 000000000..74b471ae4
--- /dev/null
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -0,0 +1,95 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+  #error CFG_TUSB_MCU must be defined
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
+#else
+  #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS                 OPT_OS_NONE
+#endif
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#define CFG_TUH_HUB                 0
+#define CFG_TUH_CDC                 0
+#define CFG_TUH_HID                 4 // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_MSC                 0
+#define CFG_TUH_VENDOR              0
+
+// max device support (excluding hub device)
+// 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1)
+
+//------------- HID -------------//
+
+#define CFG_TUH_HID_EP_BUFSIZE      64
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 3a832a247..8c66477b3 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -228,7 +228,7 @@ bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint3
   if ( dir == TUSB_DIR_IN )
   {
     TU_LOG2("  Get Report callback (%u, %u)\r\n", dev_addr, instance);
-    TU_LOG1_MEM(hid_itf->epin_buf, 8, 2);
+    TU_LOG3_MEM(hid_itf->epin_buf, xferred_bytes, 2);
     tuh_hid_report_received_cb(dev_addr, instance, hid_itf->epin_buf, xferred_bytes);
   }else
   {
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 1b5a422f4..548456a40 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -61,9 +61,13 @@ typedef struct {
   uint8_t speed;
 
   //------------- device descriptor -------------//
-  uint16_t vendor_id;
-  uint16_t product_id;
-  uint8_t  ep0_packet_size;
+  uint16_t vid;
+  uint16_t pid;
+
+  uint8_t  ep0_size;
+  uint8_t  i_manufacturer;
+  uint8_t  i_product;
+  uint8_t  i_serial;
 
   //------------- configuration descriptor -------------//
   // uint8_t interface_count; // bNumInterfaces alias
@@ -105,6 +109,8 @@ typedef struct
   uint8_t hub_addr;
   uint8_t hub_port;
   uint8_t speed;
+
+  volatile uint8_t connected;
 } usbh_dev0_t;
 
 
@@ -230,9 +236,22 @@ bool tuh_mounted(uint8_t dev_addr)
   return get_device(dev_addr)->configured;
 }
 
-tusb_speed_t tuh_speed_get (uint8_t const dev_addr)
+bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
+{
+  *vid = *pid = 0;
+
+  TU_VERIFY(tuh_mounted(dev_addr));
+
+  usbh_device_t const* dev = get_device(dev_addr);
+
+  *vid = dev->vid;
+  *pid = dev->pid;
+
+  return true;
+}
+
+tusb_speed_t tuh_speed_get (uint8_t dev_addr)
 {
-  TU_ASSERT( dev_addr <= CFG_TUH_DEVICE_MAX + CFG_TUH_HUB, TUSB_SPEED_INVALID);
   return (tusb_speed_t) get_device(dev_addr)->speed;
 }
 
@@ -652,45 +671,6 @@ static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request
 }
 #endif
 
-static bool enum_request_set_addr(void)
-{
-  uint8_t const addr0 = 0;
-  tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
-
-  // Get new address
-  uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
-  TU_ASSERT(new_addr != ADDR_INVALID);
-
-  TU_LOG2("Set Address = %d\r\n", new_addr);
-
-  usbh_device_t* new_dev = get_device(new_addr);
-
-  new_dev->rhport          = _dev0.rhport;
-  new_dev->hub_addr        = _dev0.hub_addr;
-  new_dev->hub_port        = _dev0.hub_port;
-  new_dev->speed           = _dev0.speed;
-  new_dev->connected       = 1;
-  new_dev->ep0_packet_size = desc_device->bMaxPacketSize0;
-
-  tusb_control_request_t const new_request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = TUSB_REQ_SET_ADDRESS,
-    .wValue   = new_addr,
-    .wIndex   = 0,
-    .wLength  = 0
-  };
-
-  TU_ASSERT( tuh_control_xfer(addr0, &new_request, NULL, enum_set_address_complete) );
-
-  return true;
-}
-
 static bool enum_new_device(hcd_event_t* event)
 {
   _dev0.rhport   = event->rhport; // TODO refractor integrate to device_pool
@@ -795,6 +775,45 @@ static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_r
   return true;
 }
 
+static bool enum_request_set_addr(void)
+{
+  uint8_t const addr0 = 0;
+  tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+
+  // Get new address
+  uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
+  TU_ASSERT(new_addr != ADDR_INVALID);
+
+  TU_LOG2("Set Address = %d\r\n", new_addr);
+
+  usbh_device_t* new_dev = get_device(new_addr);
+
+  new_dev->rhport    = _dev0.rhport;
+  new_dev->hub_addr  = _dev0.hub_addr;
+  new_dev->hub_port  = _dev0.hub_port;
+  new_dev->speed     = _dev0.speed;
+  new_dev->connected = 1;
+  new_dev->ep0_size  = desc_device->bMaxPacketSize0;
+
+  tusb_control_request_t const new_request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_STANDARD,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = TUSB_REQ_SET_ADDRESS,
+    .wValue   = new_addr,
+    .wIndex   = 0,
+    .wLength  = 0
+  };
+
+  TU_ASSERT( tuh_control_xfer(addr0, &new_request, NULL, enum_set_address_complete) );
+
+  return true;
+}
+
 // After SET_ADDRESS is complete
 static bool enum_set_address_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
@@ -810,7 +829,7 @@ static bool enum_set_address_complete(uint8_t dev_addr, tusb_control_request_t c
   hcd_device_close(_dev0.rhport, 0);
 
   // open control pipe for new address
-  TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_packet_size) );
+  TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size) );
 
   // Get full device descriptor
   TU_LOG2("Get Device Descriptor\r\n");
@@ -841,8 +860,11 @@ static bool enum_get_device_desc_complete(uint8_t dev_addr, tusb_control_request
   tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
   usbh_device_t* dev = get_device(dev_addr);
 
-  dev->vendor_id  = desc_device->idVendor;
-  dev->product_id = desc_device->idProduct;
+  dev->vid            = desc_device->idVendor;
+  dev->pid            = desc_device->idProduct;
+  dev->i_manufacturer = desc_device->iManufacturer;
+  dev->i_product      = desc_device->iProduct;
+  dev->i_serial       = desc_device->iSerialNumber;
 
 //  if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 5f7229f27..8411cad28 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -57,7 +57,8 @@ void tuh_task(void);
 extern void hcd_int_handler(uint8_t rhport);
 #define tuh_int_handler   hcd_int_handler
 
-tusb_speed_t tuh_speed_get (uint8_t dev_addr);
+bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid);
+tusb_speed_t tuh_speed_get(uint8_t dev_addr);
 
 // Check if device is connected and configured
 bool tuh_mounted(uint8_t dev_addr);
@@ -66,6 +67,7 @@ bool tuh_mounted(uint8_t dev_addr);
 static inline bool tuh_suspended(uint8_t dev_addr)
 {
   // TODO implement suspend & resume on host
+  (void) dev_addr;
   return false;
 }
 

From 3debeb637acb49222f36fa08f904adc4f5d9e1b7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 24 Aug 2021 21:34:51 +0700
Subject: [PATCH 0380/2085] test hid controller with rp2040

---
 examples/host/hid_controller/CMakeLists.txt |  1 -
 examples/host/hid_controller/src/hid_app.c  | 22 ++++++++++-----------
 src/host/usbh.c                             |  2 +-
 3 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index 0a99bc3a9..aaf8bc34f 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -16,7 +16,6 @@ add_executable(${PROJECT})
 target_sources(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
         ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
         )
 
 # Example include
diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index 37ae94abd..c61ce70f3 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -64,7 +64,7 @@
 // Sony DS4 report layout detail https://www.psdevwiki.com/ps4/DS4-USB
 typedef struct TU_ATTR_PACKED
 {
-  int8_t x, y, z, rz; // joystick
+  uint8_t x, y, z, rz; // joystick
 
   struct {
     uint8_t dpad     : 4; // (hat format, 0x08 is released, 0=N, 1=NE, 2=E, 3=SE, 4=S, 5=SW, 6=W, 7=NW)
@@ -160,7 +160,7 @@ void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
 }
 
 // check if different than 2
-bool diff_than_2(int8_t x, int8_t y)
+bool diff_than_2(uint8_t x, uint8_t y)
 {
   return (x - y > 2) || (y - x > 2);
 }
@@ -205,7 +205,7 @@ void process_sony_ds4(uint8_t const* report, uint16_t len)
     // We need more than memcmp to check if report is different enough
     if ( diff_report(&prev_report, &ds4_report) )
     {
-      printf("(x, y, z, rz) = (%d, %d, %d, %d)\r\n", ds4_report.x, ds4_report.y, ds4_report.z, ds4_report.rz);
+      printf("(x, y, z, rz) = (%u, %u, %u, %u)\r\n", ds4_report.x, ds4_report.y, ds4_report.z, ds4_report.rz);
       printf("DPad = %s ", dpad_str[ds4_report.dpad]);
 
       if (ds4_report.square   ) printf("Square ");
@@ -213,15 +213,15 @@ void process_sony_ds4(uint8_t const* report, uint16_t len)
       if (ds4_report.circle   ) printf("Circle ");
       if (ds4_report.triangle ) printf("Triangle ");
 
-      if (ds4_report.l1) printf("L1 ");
-      if (ds4_report.r1) printf("R1 ");
-      if (ds4_report.l2) printf("L2 ");
-      if (ds4_report.r2) printf("R2 ");
+      if (ds4_report.l1       ) printf("L1 ");
+      if (ds4_report.r1       ) printf("R1 ");
+      if (ds4_report.l2       ) printf("L2 ");
+      if (ds4_report.r2       ) printf("R2 ");
 
-      if (ds4_report.share) printf("Share ");
-      if (ds4_report.option) printf("Option ");
-      if (ds4_report.l3) printf("L3 ");
-      if (ds4_report.r3) printf("R3 ");
+      if (ds4_report.share    ) printf("Share ");
+      if (ds4_report.option   ) printf("Option ");
+      if (ds4_report.l3       ) printf("L3 ");
+      if (ds4_report.r3       ) printf("R3 ");
 
       if (ds4_report.ps       ) printf("PS ");
       if (ds4_report.tpad     ) printf("TPad ");
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 548456a40..51b8f85b6 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -252,7 +252,7 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
 
 tusb_speed_t tuh_speed_get (uint8_t dev_addr)
 {
-  return (tusb_speed_t) get_device(dev_addr)->speed;
+  return (tusb_speed_t) (dev_addr ? get_device(dev_addr)->speed : _dev0.speed);
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE

From 07adc26ce32ee663905a25bd0300d56c265dc2ad Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 26 Aug 2021 13:07:10 +0700
Subject: [PATCH 0381/2085] fix usbcv TD 9.4 Interface Descriptor test

---
 src/device/usbd.c | 26 +++++++++++++++++---------
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index e12dafcfd..2b706e291 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -751,16 +751,24 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
         // driver doesn't use alternate settings or implement this
         TU_VERIFY(TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type);
 
-        if (TUSB_REQ_GET_INTERFACE == p_request->bRequest)
+        switch(p_request->bRequest)
         {
-          uint8_t alternate = 0;
-          tud_control_xfer(rhport, p_request, &alternate, 1);
-        }else if (TUSB_REQ_SET_INTERFACE == p_request->bRequest)
-        {
-          tud_control_status(rhport, p_request);
-        } else
-        {
-          return false;
+          case TUSB_REQ_GET_INTERFACE:
+          case TUSB_REQ_SET_INTERFACE:
+            // Clear complete callback if driver set since it can also stall the request.
+            usbd_control_set_complete_callback(NULL);
+
+            if (TUSB_REQ_GET_INTERFACE == p_request->bRequest)
+            {
+              uint8_t alternate = 0;
+              tud_control_xfer(rhport, p_request, &alternate, 1);
+            }else
+            {
+              tud_control_status(rhport, p_request);
+            }
+          break;
+
+          default: return false;
         }
       }
     }

From 71e77e47fa6056937bfcd1a883a66e2bc0b622b2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 26 Aug 2021 17:02:24 +0700
Subject: [PATCH 0382/2085] add dcd_edpt_close_all() for clear existing
 configured state

correctly responded to TD 9.13 Set Configuration Test
---
 src/device/dcd.h                              |  5 ++
 src/device/usbd.c                             | 56 +++++++++++++------
 src/portable/dialog/da146xx/dcd_da146xx.c     |  6 ++
 src/portable/espressif/esp32sx/dcd_esp32sx.c  |  6 ++
 src/portable/microchip/samd/dcd_samd.c        |  6 ++
 src/portable/microchip/samg/dcd_samg.c        |  6 ++
 src/portable/microchip/samx7x/dcd_samx7x.c    |  6 ++
 .../mindmotion/mm32/dcd_mm32f327x_otg.c       |  6 ++
 src/portable/nordic/nrf5x/dcd_nrf5x.c         |  6 ++
 src/portable/nuvoton/nuc120/dcd_nuc120.c      |  6 ++
 src/portable/nuvoton/nuc121/dcd_nuc121.c      |  6 ++
 src/portable/nuvoton/nuc505/dcd_nuc505.c      |  6 ++
 src/portable/nxp/khci/dcd_khci.c              |  6 ++
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c      |  6 ++
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c  |  6 ++
 .../nxp/transdimension/dcd_transdimension.c   |  6 ++
 src/portable/raspberrypi/rp2040/dcd_rp2040.c  |  6 ++
 src/portable/renesas/usba/dcd_usba.c          |  6 ++
 src/portable/silabs/efm32/dcd_efm32.c         |  6 ++
 src/portable/sony/cxd56/dcd_cxd56.c           |  6 ++
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |  6 ++
 src/portable/st/synopsys/dcd_synopsys.c       |  6 ++
 src/portable/template/dcd_template.c          |  5 ++
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c   |  6 ++
 src/portable/valentyusb/eptri/dcd_eptri.c     |  6 ++
 25 files changed, 182 insertions(+), 16 deletions(-)

diff --git a/src/device/dcd.h b/src/device/dcd.h
index 66767c1fe..8d042bbde 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -137,6 +137,11 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
 // Configure endpoint's registers according to descriptor
 bool dcd_edpt_open            (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
 
+// Close all non-control endpoints, cancel all pending transfers if any.
+// Invoked when switching from a non-zero Configuration by SET_CONFIGURE therefore
+// required for multiple configuration support.
+void dcd_edpt_close_all       (uint8_t rhport);
+
 // Close an endpoint.
 // Since it is weak, caller must TU_ASSERT this function's existence before calling it.
 void dcd_edpt_close           (uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK;
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 2b706e291..b2babb7a0 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -38,7 +38,7 @@
 //--------------------------------------------------------------------+
 
 // Debug level of USBD
-#define USBD_DBG_LVL   2
+#define USBD_DBG   2
 
 #ifndef CFG_TUD_TASK_QUEUE_SZ
   #define CFG_TUD_TASK_QUEUE_SZ   16
@@ -432,19 +432,22 @@ bool tud_init (uint8_t rhport)
   return true;
 }
 
-static void usbd_reset(uint8_t rhport)
+static void configuration_reset(uint8_t rhport)
 {
-  tu_varclr(&_usbd_dev);
-
-  memset(_usbd_dev.itf2drv, DRVID_INVALID, sizeof(_usbd_dev.itf2drv)); // invalid mapping
-  memset(_usbd_dev.ep2drv , DRVID_INVALID, sizeof(_usbd_dev.ep2drv )); // invalid mapping
-
-  usbd_control_reset();
-
   for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ )
   {
     get_driver(i)->reset(rhport);
   }
+
+  tu_varclr(&_usbd_dev);
+  memset(_usbd_dev.itf2drv, DRVID_INVALID, sizeof(_usbd_dev.itf2drv)); // invalid mapping
+  memset(_usbd_dev.ep2drv , DRVID_INVALID, sizeof(_usbd_dev.ep2drv )); // invalid mapping
+}
+
+static void usbd_reset(uint8_t rhport)
+{
+  configuration_reset(rhport);
+  usbd_control_reset();
 }
 
 bool tud_task_event_ready(void)
@@ -686,9 +689,29 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
         {
           uint8_t const cfg_num = (uint8_t) p_request->wValue;
 
-          if ( !_usbd_dev.cfg_num && cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) );
-          _usbd_dev.cfg_num = cfg_num;
+          // Only process if new configure is different
+          if (_usbd_dev.cfg_num != cfg_num)
+          {
+            if ( _usbd_dev.cfg_num )
+            {
+              // already configured: need to clear all endpoints and driver first
+              TU_LOG(USBD_DBG, "Clear current config (%u) before switching\r\n", _usbd_dev.cfg_num);
 
+              // close all non-control endpoints, cancel all pending transfers if any
+              dcd_edpt_close_all(rhport);
+
+              // close all drivers and current configured state except bus speed
+              uint8_t const speed = _usbd_dev.speed;
+              configuration_reset(rhport);
+
+              _usbd_dev.speed = speed; // restore speed
+            }
+
+            // switch to new configuration if not zero
+            if ( cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) );
+          }
+
+          _usbd_dev.cfg_num = cfg_num;
           tud_control_status(rhport, p_request);
         }
         break;
@@ -701,7 +724,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           // Only support remote wakeup for device feature
           TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
 
-          TU_LOG(USBD_DBG_LVL, "    Enable Remote Wakeup\r\n");
+          TU_LOG(USBD_DBG, "    Enable Remote Wakeup\r\n");
 
           // Host may enable remote wake up before suspending especially HID device
           _usbd_dev.remote_wakeup_en = true;
@@ -712,7 +735,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           // Only support remote wakeup for device feature
           TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
 
-          TU_LOG(USBD_DBG_LVL, "    Disable Remote Wakeup\r\n");
+          TU_LOG(USBD_DBG, "    Disable Remote Wakeup\r\n");
 
           // Host may disable remote wake up after resuming
           _usbd_dev.remote_wakeup_en = false;
@@ -851,7 +874,8 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
 // This function parse configuration descriptor & open drivers accordingly
 static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
 {
-  tusb_desc_configuration_t const * desc_cfg = (tusb_desc_configuration_t const *) tud_descriptor_configuration_cb(cfg_num-1); // index is cfg_num-1
+  // index is cfg_num-1
+  tusb_desc_configuration_t const * desc_cfg = (tusb_desc_configuration_t const *) tud_descriptor_configuration_cb(cfg_num-1);
   TU_ASSERT(desc_cfg != NULL && desc_cfg->bDescriptorType == TUSB_DESC_CONFIGURATION);
 
   // Parse configuration descriptor
@@ -1309,7 +1333,7 @@ bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  TU_LOG(USBD_DBG_LVL, "    Stall EP %02X", ep_addr);
+  TU_LOG(USBD_DBG, "    Stall EP %02X", ep_addr);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
@@ -1321,7 +1345,7 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  TU_LOG(USBD_DBG_LVL, "    Clear Stall EP %02X", ep_addr);
+  TU_LOG(USBD_DBG, "    Clear Stall EP %02X", ep_addr);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 5fcf3bc5b..7b0d8f86c 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -847,6 +847,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t const epnum = tu_edpt_number(ep_addr);
diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index d728487c2..a5ada0da8 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -312,6 +312,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
   return true;
 }
 
+void dcd_edpt_close_all(uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
   (void)rhport;
diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index 577bd0e05..54e8e62d9 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -240,6 +240,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
   (void) rhport;
diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c
index d50621ce4..81779c56b 100644
--- a/src/portable/microchip/samg/dcd_samg.c
+++ b/src/portable/microchip/samg/dcd_samg.c
@@ -269,6 +269,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 0d9e184f6..032547e47 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -544,6 +544,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   }
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
index 59a40dc68..c472f2175 100644
--- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -339,6 +339,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index f6b64c986..efc4d3183 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -364,6 +364,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c
index 57cc76e81..7618f288d 100644
--- a/src/portable/nuvoton/nuc120/dcd_nuc120.c
+++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c
@@ -273,6 +273,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
   (void) rhport;
diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index a776e46f5..7edafe5d3 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -289,6 +289,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
   (void) rhport;
diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c
index 4e633086d..ea5a8bea5 100644
--- a/src/portable/nuvoton/nuc505/dcd_nuc505.c
+++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c
@@ -353,6 +353,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
   (void) rhport;
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index dce464fd2..1f5f4e5e1 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -347,6 +347,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 519d09151..2eae6d0f7 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -326,6 +326,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 4392d1882..1bdf72d6d 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -323,6 +323,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 static void prepare_setup_packet(uint8_t rhport)
 {
   if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index eeab3f487..42047ef92 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -366,6 +366,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 49284e92e..e81681d4f 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -428,6 +428,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
     assert(rhport == 0);
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 095dcc136..a837b5724 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -733,6 +733,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
diff --git a/src/portable/silabs/efm32/dcd_efm32.c b/src/portable/silabs/efm32/dcd_efm32.c
index bd1f32e6b..3bef83408 100644
--- a/src/portable/silabs/efm32/dcd_efm32.c
+++ b/src/portable/silabs/efm32/dcd_efm32.c
@@ -434,6 +434,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
   (void)rhport;
diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index 834976468..cfd74330f 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -312,6 +312,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
   (void) rhport;
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index eeba7204f..ccffa42d7 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -800,6 +800,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 /**
  * Close an endpoint.
  * 
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 8a998aa3a..fe165e830 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -670,6 +670,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
   uint8_t const epnum = tu_edpt_number(ep_addr);
diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c
index 12b9144bf..977369300 100644
--- a/src/portable/template/dcd_template.c
+++ b/src/portable/template/dcd_template.c
@@ -94,6 +94,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   return false;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+}
+
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index 027ed26c9..ee85f0a77 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -298,6 +298,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
   (void) rhport;
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c
index b68f04faa..89bc7a1ab 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.c
+++ b/src/portable/valentyusb/eptri/dcd_eptri.c
@@ -429,6 +429,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   return true;
 }
 
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+  // TODO implement dcd_edpt_close_all()
+}
+
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;

From ed4602158bb4e19f4dba122383be1c4845914bde Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 26 Aug 2021 17:08:22 +0700
Subject: [PATCH 0383/2085] TD 9.12 remote wakeup test

remove TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP attribute from non-hid
examples
---
 examples/device/audio_4_channel_mic/src/usb_descriptors.c   | 2 +-
 examples/device/audio_test/src/usb_descriptors.c            | 2 +-
 examples/device/cdc_dual_ports/src/usb_descriptors.c        | 4 ++--
 examples/device/cdc_msc/src/usb_descriptors.c               | 4 ++--
 examples/device/cdc_msc_freertos/src/usb_descriptors.c      | 4 ++--
 examples/device/dfu/src/usb_descriptors.c                   | 2 +-
 examples/device/dfu_runtime/src/usb_descriptors.c           | 2 +-
 examples/device/dynamic_configuration/src/usb_descriptors.c | 4 ++--
 examples/device/hid_generic_inout/src/usb_descriptors.c     | 2 +-
 examples/device/midi_test/src/usb_descriptors.c             | 4 ++--
 examples/device/msc_dual_lun/src/usb_descriptors.c          | 4 ++--
 examples/device/uac2_headset/src/usb_descriptors.c          | 2 +-
 examples/device/usbtmc/src/usb_descriptors.c                | 2 +-
 examples/device/webusb_serial/src/usb_descriptors.c         | 2 +-
 14 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index 93ec6e9f7..018919bf3 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -92,7 +92,7 @@ enum
 uint8_t const desc_configuration[] =
 {
     // Interface count, string index, total length, attribute, power in mA
-    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
     TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN)
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index 67dd34d2a..a4e9dc8e1 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -92,7 +92,7 @@ enum
 uint8_t const desc_configuration[] =
 {
     // Interface count, string index, total length, attribute, power in mA
-    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
     TUD_AUDIO_MIC_ONE_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN)
diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index b935b672f..02ccbcc9e 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -118,7 +118,7 @@ enum
 uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size.
   TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_OUT, EPNUM_CDC_0_IN, 64),
@@ -131,7 +131,7 @@ uint8_t const desc_fs_configuration[] =
 uint8_t const desc_hs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size.
   TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_OUT, EPNUM_CDC_0_IN, 512),
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 1a89ce561..3cf1eaf91 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -129,7 +129,7 @@ enum
 uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
   TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
@@ -142,7 +142,7 @@ uint8_t const desc_fs_configuration[] =
 uint8_t const desc_hs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
   TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
index 75b5ce7bb..c8dbcd415 100644
--- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c
+++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
@@ -117,7 +117,7 @@ enum
 uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
   TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
@@ -130,7 +130,7 @@ uint8_t const desc_fs_configuration[] =
 uint8_t const desc_hs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
   TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 1cfe29c53..350334aa5 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -97,7 +97,7 @@ enum
 uint8_t const desc_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size
   TUD_DFU_DESCRIPTOR(ITF_NUM_DFU_MODE, ALT_COUNT, 4, FUNC_ATTRS, 1000, CFG_TUD_DFU_XFER_BUFSIZE),
diff --git a/examples/device/dfu_runtime/src/usb_descriptors.c b/examples/device/dfu_runtime/src/usb_descriptors.c
index 8b2bd265d..060943289 100644
--- a/examples/device/dfu_runtime/src/usb_descriptors.c
+++ b/examples/device/dfu_runtime/src/usb_descriptors.c
@@ -92,7 +92,7 @@ enum
 uint8_t const desc_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, attributes, detach timeout, transfer size */
   TUD_DFU_RT_DESCRIPTOR(ITF_NUM_DFU_RT, 4, 0x0d, 1000, 4096),
diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index 9ccb37654..3352972a5 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -160,7 +160,7 @@ enum
 uint8_t const desc_configuration_0[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_0_NUM_TOTAL, 0, CONFIG_0_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_0_NUM_TOTAL, 0, CONFIG_0_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
   TUD_CDC_DESCRIPTOR(ITF_0_NUM_CDC, 0, EPNUM_0_CDC_NOTIF, 8, EPNUM_0_CDC_OUT, EPNUM_0_CDC_IN, 64),
@@ -173,7 +173,7 @@ uint8_t const desc_configuration_0[] =
 uint8_t const desc_configuraiton_1[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_1_NUM_TOTAL, 0, CONFIG_1_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_1_NUM_TOTAL, 0, CONFIG_1_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP Out & EP In address, EP size
   TUD_MSC_DESCRIPTOR(ITF_1_NUM_MSC, 0, EPNUM_1_MSC_OUT, EPNUM_1_MSC_IN, TUD_OPT_HIGH_SPEED ? 512 : 64),
diff --git a/examples/device/hid_generic_inout/src/usb_descriptors.c b/examples/device/hid_generic_inout/src/usb_descriptors.c
index 5a2f5ffdc..5dabf42a3 100644
--- a/examples/device/hid_generic_inout/src/usb_descriptors.c
+++ b/examples/device/hid_generic_inout/src/usb_descriptors.c
@@ -101,7 +101,7 @@ enum
 uint8_t const desc_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, protocol, report descriptor len, EP In & Out address, size & polling interval
   TUD_HID_INOUT_DESCRIPTOR(ITF_NUM_HID, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_HID, 0x80 | EPNUM_HID, CFG_TUD_HID_EP_BUFSIZE, 10)
diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c
index 9d92a7753..bd5a0eeab 100644
--- a/examples/device/midi_test/src/usb_descriptors.c
+++ b/examples/device/midi_test/src/usb_descriptors.c
@@ -91,7 +91,7 @@ enum
 uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP Out & EP In address, EP size
   TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI, 0x80 | EPNUM_MIDI, 64)
@@ -101,7 +101,7 @@ uint8_t const desc_fs_configuration[] =
 uint8_t const desc_hs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP Out & EP In address, EP size
   TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI, 0x80 | EPNUM_MIDI, 512)
diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c
index 138de62a3..7e194ea7a 100644
--- a/examples/device/msc_dual_lun/src/usb_descriptors.c
+++ b/examples/device/msc_dual_lun/src/usb_descriptors.c
@@ -99,7 +99,7 @@ enum
 uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP Out & EP In address, EP size
   TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 0, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64),
@@ -109,7 +109,7 @@ uint8_t const desc_fs_configuration[] =
 uint8_t const desc_hs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP Out & EP In address, EP size
   TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 0, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 4a26b0b1e..64fa3c25b 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -98,7 +98,7 @@ uint8_t const * tud_descriptor_device_cb(void)
 uint8_t const desc_configuration[] =
 {
     // Interface count, string index, total length, attribute, power in mA
-    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
     TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO_OUT, EPNUM_AUDIO_IN | 0x80)
diff --git a/examples/device/usbtmc/src/usb_descriptors.c b/examples/device/usbtmc/src/usb_descriptors.c
index 2336266b8..423482634 100644
--- a/examples/device/usbtmc/src/usb_descriptors.c
+++ b/examples/device/usbtmc/src/usb_descriptors.c
@@ -122,7 +122,7 @@ enum
 uint8_t const desc_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   TUD_USBTMC_DESC(ITF_NUM_USBTMC),
 };
diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c
index d1539488f..93e802a90 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.c
+++ b/examples/device/webusb_serial/src/usb_descriptors.c
@@ -107,7 +107,7 @@ enum
 uint8_t const desc_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
   TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, 0x81, 8, EPNUM_CDC_OUT, 0x80 | EPNUM_CDC_IN, TUD_OPT_HIGH_SPEED ? 512 : 64),

From 629da937f84854d76cd8da20daa4a80dd02e56e2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 26 Aug 2021 17:55:31 +0700
Subject: [PATCH 0384/2085] slightly change the keyboard descriptor template to
 pass usb compliant test

---
 src/class/hid/hid_device.h | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index e2c950dd1..5cf4b3060 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -195,16 +195,7 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
       HID_REPORT_COUNT ( 1                                      )  ,\
       HID_REPORT_SIZE  ( 8                                      )  ,\
       HID_INPUT        ( HID_CONSTANT                           )  ,\
-    /* 6-byte Keycodes */ \
-    HID_USAGE_PAGE ( HID_USAGE_PAGE_KEYBOARD )                     ,\
-      HID_USAGE_MIN    ( 0                                   )     ,\
-      HID_USAGE_MAX_N  ( 255, 2                              )     ,\
-      HID_LOGICAL_MIN  ( 0                                   )     ,\
-      HID_LOGICAL_MAX_N( 255, 2                              )     ,\
-      HID_REPORT_COUNT ( 6                                   )     ,\
-      HID_REPORT_SIZE  ( 8                                   )     ,\
-      HID_INPUT        ( HID_DATA | HID_ARRAY | HID_ABSOLUTE )     ,\
-    /* 5-bit LED Indicator Kana | Compose | ScrollLock | CapsLock | NumLock */ \
+    /* Output 5-bit LED Indicator Kana | Compose | ScrollLock | CapsLock | NumLock */ \
     HID_USAGE_PAGE  ( HID_USAGE_PAGE_LED                   )       ,\
       HID_USAGE_MIN    ( 1                                       ) ,\
       HID_USAGE_MAX    ( 5                                       ) ,\
@@ -215,6 +206,15 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
       HID_REPORT_COUNT ( 1                                       ) ,\
       HID_REPORT_SIZE  ( 3                                       ) ,\
       HID_OUTPUT       ( HID_CONSTANT                            ) ,\
+    /* 6-byte Keycodes */ \
+    HID_USAGE_PAGE ( HID_USAGE_PAGE_KEYBOARD )                     ,\
+      HID_USAGE_MIN    ( 0                                   )     ,\
+      HID_USAGE_MAX_N  ( 255, 2                              )     ,\
+      HID_LOGICAL_MIN  ( 0                                   )     ,\
+      HID_LOGICAL_MAX_N( 255, 2                              )     ,\
+      HID_REPORT_COUNT ( 6                                   )     ,\
+      HID_REPORT_SIZE  ( 8                                   )     ,\
+      HID_INPUT        ( HID_DATA | HID_ARRAY | HID_ABSOLUTE )     ,\
   HID_COLLECTION_END \
 
 // Mouse Report Descriptor Template

From 22028455077eb1bb4e9c98735cb990305067ef36 Mon Sep 17 00:00:00 2001
From: Xu Chun Guang <xuchunguang@espressif.com>
Date: Fri, 27 Aug 2021 10:50:25 +0800
Subject: [PATCH 0385/2085] fix: bth stridx error

---
 src/device/usbd.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/usbd.h b/src/device/usbd.h
index c85616c95..9becf2d0d 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -734,7 +734,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 /* Primary Interface */
 #define TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \
-  9, TUSB_DESC_INTERFACE, _itfnum, _stridx, 3, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, 0, \
+  9, TUSB_DESC_INTERFACE, _itfnum, 0, 3, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, _stridx, \
   /* Endpoint In for events */ \
   7, TUSB_DESC_ENDPOINT, _ep_evt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_evt_size), _ep_evt_interval, \
   /* Endpoint In for ACL data */ \

From 9394de6ae74cf01ba8c8f1dab57dbbdfad6d6407 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 Aug 2021 12:38:41 +0700
Subject: [PATCH 0386/2085] update msc driver to pass MSC BOT error recovery
 compliant test

---
 examples/device/cdc_msc/src/msc_disk.c        |  11 ++
 .../device/msc_dual_lun/src/msc_disk_dual.c   |  11 ++
 src/class/msc/msc_device.c                    | 139 +++++++++++++-----
 src/class/msc/msc_device.h                    |   2 +-
 src/common/tusb_common.h                      |   7 +-
 src/device/usbd.c                             |   7 +-
 6 files changed, 137 insertions(+), 40 deletions(-)

diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index 503baace9..32f2563cb 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -194,6 +194,17 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
   return bufsize;
 }
 
+bool tud_msc_is_writable_cb (uint8_t lun)
+{
+  (void) lun;
+
+#ifdef CFG_EXAMPLE_MSC_READONLY
+  return false;
+#else
+  return true;
+#endif
+}
+
 // Callback invoked when received WRITE10 command.
 // Process data in buffer to disk's storage and return number of written bytes
 int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize)
diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c
index 2ab050da8..cc7dfae0e 100644
--- a/examples/device/msc_dual_lun/src/msc_disk_dual.c
+++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c
@@ -274,6 +274,17 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
   return bufsize;
 }
 
+bool tud_msc_is_writable_cb (uint8_t lun)
+{
+  (void) lun;
+
+#ifdef CFG_EXAMPLE_MSC_READONLY
+  return false;
+#else
+  return true;
+#endif
+}
+
 // Callback invoked when received WRITE10 command.
 // Process data in buffer to disk's storage and return number of written bytes
 int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize)
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 014e8b69e..9e3689d84 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -46,7 +46,8 @@ enum
   MSC_STAGE_CMD  = 0,
   MSC_STAGE_DATA,
   MSC_STAGE_STATUS,
-  MSC_STAGE_STATUS_SENT
+  MSC_STAGE_STATUS_SENT,
+  MSC_STAGE_NEED_RESET,
 };
 
 typedef struct
@@ -174,35 +175,91 @@ uint16_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
   TU_ASSERT( usbd_open_edpt_pair(rhport, tu_desc_next(itf_desc), 2, TUSB_XFER_BULK, &p_msc->ep_out, &p_msc->ep_in), 0 );
 
   // Prepare for Command Block Wrapper
-  if ( !usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) )
-  {
-    TU_LOG_FAILED();
-    TU_BREAKPOINT();
-  }
+  TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)), drv_len);
 
   return drv_len;
 }
 
+static void process_bot_reset(mscd_interface_t* p_msc)
+{
+  p_msc->stage       = MSC_STAGE_CMD;
+  p_msc->total_len   = 0;
+  p_msc->xferred_len = 0;
+
+  p_msc->sense_key           = 0;
+  p_msc->add_sense_code      = 0;
+  p_msc->add_sense_qualifier = 0;
+}
+
+
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
-bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * p_request)
+bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
 {
   // nothing to do with DATA & ACK stage
   if (stage != CONTROL_STAGE_SETUP) return true;
 
-  // Handle class request only
-  TU_VERIFY(p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
+  mscd_interface_t* p_msc = &_mscd_itf;
 
-  switch ( p_request->bRequest )
+  // Clear Endpoint Feature (stall) for recovery
+  if ( TUSB_REQ_TYPE_STANDARD     == request->bmRequestType_bit.type      &&
+       TUSB_REQ_RCPT_ENDPOINT     == request->bmRequestType_bit.recipient &&
+       TUSB_REQ_CLEAR_FEATURE     == request->bRequest                    &&
+       TUSB_REQ_FEATURE_EDPT_HALT == request->wValue )
+  {
+    uint8_t const ep_addr = tu_u16_low(request->wIndex);
+
+    if ( p_msc->stage == MSC_STAGE_NEED_RESET )
+    {
+      // reset recovery is required to recover from this stage
+      // Clear Stall request cannot resolve this -> continue to stall endpoint
+      usbd_edpt_stall(rhport, ep_addr);
+    }
+    else
+    {
+      if ( ep_addr == p_msc->ep_in )
+      {
+        if ( p_msc->stage == MSC_STAGE_STATUS )
+        {
+          // resume sending SCSI status if we are in this stage previously before stalled
+          p_msc->stage = MSC_STAGE_STATUS_SENT;
+          TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)) );
+        }
+      }
+      else if ( ep_addr == p_msc->ep_out )
+      {
+        if ( p_msc->stage == MSC_STAGE_CMD )
+        {
+          // part of reset recovery (probably due to invalid CBW) -> prepare for new command
+          TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) );
+        }
+      }
+    }
+
+    return true;
+  }
+
+  // From this point only handle class request only
+  TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
+
+  switch ( request->bRequest )
   {
     case MSC_REQ_RESET:
-      // TODO: Actually reset interface.
-      tud_control_status(rhport, p_request);
+      TU_LOG(MSC_DEBUG, "  MSC BOT Reset\r\n");
+      TU_VERIFY(request->wValue == 0 && request->wLength == 0);
+
+      // driver state reset
+      process_bot_reset(p_msc);
+
+      tud_control_status(rhport, request);
     break;
 
     case MSC_REQ_GET_MAX_LUN:
     {
+      TU_LOG(MSC_DEBUG, "  MSC Get Max Lun\r\n");
+      TU_VERIFY(request->wValue == 0 && request->wLength == 1);
+
       uint8_t maxlun = 1;
       if (tud_msc_get_maxlun_cb) maxlun = tud_msc_get_maxlun_cb();
       TU_VERIFY(maxlun);
@@ -210,7 +267,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
       // MAX LUN is minus 1 by specs
       maxlun--;
 
-      tud_control_xfer(rhport, p_request, &maxlun, 1);
+      tud_control_xfer(rhport, request, &maxlun, 1);
     }
     break;
 
@@ -222,6 +279,8 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
 
 bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
 {
+  (void) event;
+
   mscd_interface_t* p_msc = &_mscd_itf;
   msc_cbw_t const * p_cbw = &p_msc->cbw;
   msc_csw_t       * p_csw = &p_msc->csw;
@@ -233,11 +292,20 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       // Complete IN while waiting for CMD is usually Status of previous SCSI op, ignore it
       if(ep_addr != p_msc->ep_out) return true;
 
-      TU_ASSERT( event == XFER_RESULT_SUCCESS &&
-                 xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE );
+      if ( !(xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE) )
+      {
+        // BOT 6.6.1 If CBW is not valid stall both endpoints until reset recovery
+        p_msc->stage = MSC_STAGE_NEED_RESET;
+
+        // invalid CBW stall both endpoints
+        usbd_edpt_stall(rhport, p_msc->ep_in);
+        usbd_edpt_stall(rhport, p_msc->ep_out);
+
+        return false;
+      }
 
       TU_LOG(MSC_DEBUG, "  SCSI Command: %s\r\n", tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
-      // TU_LOG_MEM(MSC_DEBUG, p_cbw, xferred_bytes, 2);
+      //TU_LOG_MEM(MSC_DEBUG, p_cbw, xferred_bytes, 2);
 
       p_csw->signature    = MSC_CSW_SIGNATURE;
       p_csw->tag          = p_cbw->tag;
@@ -440,15 +508,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
 
   if ( p_msc->stage == MSC_STAGE_STATUS )
   {
-    // Either endpoints is stalled, need to wait until it is cleared by host
-    if ( usbd_edpt_stalled(rhport,  p_msc->ep_in) || usbd_edpt_stalled(rhport,  p_msc->ep_out) )
-    {
-      // simulate an transfer complete with adjusted parameters --> this driver callback will fired again
-      // and response with status phase after halted endpoints are cleared.
-      // note: use ep_out to prevent confusing with STATUS complete
-      dcd_event_xfer_complete(rhport, p_msc->ep_out, 0, XFER_RESULT_SUCCESS, false);
-    }
-    else
+    // skip status if epin is currently stalled, will do it when received Clear Stall request
+    if ( !usbd_edpt_stalled(rhport,  p_msc->ep_in) )
     {
       // Move to Status Sent stage
       p_msc->stage = MSC_STAGE_STATUS_SENT;
@@ -600,9 +661,11 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       };
 
       bool writable = true;
-      if (tud_msc_is_writable_cb) {
-          writable = tud_msc_is_writable_cb(lun);
+      if ( tud_msc_is_writable_cb )
+      {
+        writable = tud_msc_is_writable_cb(lun);
       }
+
       mode_resp.write_protected = !writable;
 
       resplen = sizeof(mode_resp);
@@ -660,7 +723,8 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
 
   if ( nbytes < 0 )
   {
-    // negative means error -> pipe is stalled & status in CSW set to failed
+    // negative means error -> endpoint is stalled & status in CSW set to failed
+    p_msc->stage = MSC_STAGE_STATUS;
     p_csw->data_residue = p_cbw->total_bytes - p_msc->xferred_len;
     p_csw->status       = MSC_CSW_STATUS_FAILED;
 
@@ -682,15 +746,22 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
 {
   msc_cbw_t const * p_cbw = &p_msc->cbw;
   bool writable = true;
-  if (tud_msc_is_writable_cb) {
+
+  if ( tud_msc_is_writable_cb )
+  {
     writable = tud_msc_is_writable_cb(p_cbw->lun);
   }
-  if (!writable) {
-    msc_csw_t* p_csw = &p_msc->csw;
-    p_csw->data_residue = p_cbw->total_bytes;
-    p_csw->status       = MSC_CSW_STATUS_FAILED;
 
-    tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00); // Sense = Write protected
+  if ( !writable )
+  {
+    // Not writable, complete this SCSI op with error
+    msc_csw_t *p_csw = &p_msc->csw;
+
+    p_msc->stage = MSC_STAGE_STATUS;
+    p_csw->status = MSC_CSW_STATUS_FAILED;
+    p_csw->data_residue = p_cbw->total_bytes;
+
+    tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00);    // Sense = Write protected
     usbd_edpt_stall(rhport, p_msc->ep_out);
     return;
   }
diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h
index 8f90ef4ad..d32694340 100644
--- a/src/class/msc/msc_device.h
+++ b/src/class/msc/msc_device.h
@@ -140,7 +140,7 @@ TU_ATTR_WEAK void tud_msc_write10_complete_cb(uint8_t lun);
 // Invoked when command in tud_msc_scsi_cb is complete
 TU_ATTR_WEAK void tud_msc_scsi_complete_cb(uint8_t lun, uint8_t const scsi_cmd[16]);
 
-// Hook to make a mass storage device read-only. TODO remove
+// Invoked to check if device is writable as part of SCSI WRITE10
 TU_ATTR_WEAK bool tud_msc_is_writable_cb(uint8_t lun);
 
 //--------------------------------------------------------------------+
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index c2356ffee..1452e0105 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -369,12 +369,17 @@ typedef struct
 
 static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
 {
+  static char not_found[10];
+
   for(uint16_t i=0; i<p_table->count; i++)
   {
     if (p_table->items[i].key == key) return p_table->items[i].data;
   }
 
-  return NULL;
+  // not found return the key value in hex
+  sprintf(not_found, "0x%08lX", key);
+
+  return not_found;
 }
 
 #endif // CFG_TUSB_DEBUG
diff --git a/src/device/usbd.c b/src/device/usbd.c
index b2babb7a0..7cd8fad42 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -695,7 +695,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
             if ( _usbd_dev.cfg_num )
             {
               // already configured: need to clear all endpoints and driver first
-              TU_LOG(USBD_DBG, "Clear current config (%u) before switching\r\n", _usbd_dev.cfg_num);
+              TU_LOG(USBD_DBG, "  Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num);
 
               // close all non-control endpoints, cancel all pending transfers if any
               dcd_edpt_close_all(rhport);
@@ -1333,7 +1333,7 @@ bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  TU_LOG(USBD_DBG, "    Stall EP %02X", ep_addr);
+  TU_LOG(USBD_DBG, "    Stall EP %02X\r\n", ep_addr);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
@@ -1345,12 +1345,11 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  TU_LOG(USBD_DBG, "    Clear Stall EP %02X", ep_addr);
+  TU_LOG(USBD_DBG, "    Clear Stall EP %02X\r\n", ep_addr);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-
   dcd_edpt_clear_stall(rhport, ep_addr);
   _usbd_dev.ep_status[epnum][dir].stalled = false;
   _usbd_dev.ep_status[epnum][dir].busy = false;

From 032770682ee856a32d0087ae9fd9a04c03e2bd0e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 Aug 2021 13:18:51 +0700
Subject: [PATCH 0387/2085] minor clean up

---
 src/class/msc/msc_device.c | 36 +++++++++++++++++++-----------------
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 9e3689d84..c0ea5ae40 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -99,6 +99,18 @@ static inline uint16_t rdwr10_get_blockcount(uint8_t const command[])
   return tu_ntohs(block_count);
 }
 
+static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc)
+{
+  p_msc->stage = MSC_STAGE_STATUS_SENT;
+  return usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t));
+}
+
+static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc)
+{
+  p_msc->stage = MSC_STAGE_CMD;
+  return usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t));
+}
+
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
@@ -175,12 +187,12 @@ uint16_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
   TU_ASSERT( usbd_open_edpt_pair(rhport, tu_desc_next(itf_desc), 2, TUSB_XFER_BULK, &p_msc->ep_out, &p_msc->ep_in), 0 );
 
   // Prepare for Command Block Wrapper
-  TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)), drv_len);
+  TU_ASSERT( prepare_cbw(rhport, p_msc), drv_len);
 
   return drv_len;
 }
 
-static void process_bot_reset(mscd_interface_t* p_msc)
+static void proc_bot_reset(mscd_interface_t* p_msc)
 {
   p_msc->stage       = MSC_STAGE_CMD;
   p_msc->total_len   = 0;
@@ -191,7 +203,6 @@ static void process_bot_reset(mscd_interface_t* p_msc)
   p_msc->add_sense_qualifier = 0;
 }
 
-
 // Invoked when a control transfer occurred on an interface of this class
 // Driver response accordingly to the request and the transfer stage (setup/data/ack)
 // return false to stall control endpoint (e.g unsupported request)
@@ -223,8 +234,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         if ( p_msc->stage == MSC_STAGE_STATUS )
         {
           // resume sending SCSI status if we are in this stage previously before stalled
-          p_msc->stage = MSC_STAGE_STATUS_SENT;
-          TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)) );
+          TU_ASSERT( send_csw(rhport, p_msc) );
         }
       }
       else if ( ep_addr == p_msc->ep_out )
@@ -232,7 +242,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         if ( p_msc->stage == MSC_STAGE_CMD )
         {
           // part of reset recovery (probably due to invalid CBW) -> prepare for new command
-          TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) );
+          TU_ASSERT( prepare_cbw(rhport, p_msc) );
         }
       }
     }
@@ -250,7 +260,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
       TU_VERIFY(request->wValue == 0 && request->wLength == 0);
 
       // driver state reset
-      process_bot_reset(p_msc);
+      proc_bot_reset(p_msc);
 
       tud_control_status(rhport, request);
     break;
@@ -495,11 +505,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           break;
         }
 
-        // Move to default CMD stage
-        p_msc->stage = MSC_STAGE_CMD;
-
-        // Queue for the next CBW
-        TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)) );
+        TU_ASSERT( prepare_cbw(rhport, p_msc) );
       }
     break;
 
@@ -511,11 +517,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     // skip status if epin is currently stalled, will do it when received Clear Stall request
     if ( !usbd_edpt_stalled(rhport,  p_msc->ep_in) )
     {
-      // Move to Status Sent stage
-      p_msc->stage = MSC_STAGE_STATUS_SENT;
-
-      // Send SCSI Status
-      TU_ASSERT(usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)));
+      TU_ASSERT( send_csw(rhport, p_msc) );
     }
   }
 

From 893dceb1984d6304918a45ec8be5a63d3e9993ca Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 Aug 2021 17:30:02 +0700
Subject: [PATCH 0388/2085] refactor msc device

---
 src/class/msc/msc_device.c | 277 ++++++++++++++++++++++---------------
 1 file changed, 165 insertions(+), 112 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index c0ea5ae40..716b7e503 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -79,25 +79,9 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _mscd_buf[CFG_TUD_MSC_EP_
 //--------------------------------------------------------------------+
 static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_t* buffer, uint32_t bufsize);
 static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
+
 static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
-
-static inline uint32_t rdwr10_get_lba(uint8_t const command[])
-{
-  // use offsetof to avoid pointer to the odd/unaligned address
-  uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba));
-
-  // lba is in Big Endian
-  return tu_ntohl(lba);
-}
-
-static inline uint16_t rdwr10_get_blockcount(uint8_t const command[])
-{
-  // use offsetof to avoid pointer to the odd/misaligned address
-  uint16_t const block_count = tu_unaligned_read16(command + offsetof(scsi_write10_t, block_count));
-
-  // block count is in Big Endian
-  return tu_ntohs(block_count);
-}
+static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes);
 
 static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc)
 {
@@ -111,6 +95,20 @@ static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc)
   return usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t));
 }
 
+static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status)
+{
+  msc_cbw_t const * p_cbw = &p_msc->cbw;
+  msc_csw_t       * p_csw = &p_msc->csw;
+
+  p_csw->status       = status;
+  p_csw->data_residue = p_cbw->total_bytes - p_msc->xferred_len;
+
+  p_msc->stage = MSC_STAGE_STATUS;
+
+  // failed but sense key is not set: default to Illegal Request
+  if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+}
+
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
@@ -358,12 +356,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
 
           if ( resplen < 0 )
           {
-            p_msc->total_len = 0;
-            p_csw->status = MSC_CSW_STATUS_FAILED;
-            p_msc->stage = MSC_STAGE_STATUS;
-
-            // failed but senskey is not set: default to Illegal Request
-            if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+            fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
 
             // Stall bulk In if needed
             if (p_cbw->total_bytes) usbd_edpt_stall(rhport, p_msc->ep_in);
@@ -390,10 +383,27 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       TU_LOG(MSC_DEBUG, "  SCSI Data\r\n");
       //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2);
 
-      // OUT transfer, invoke callback if needed
-      if ( !tu_bit_test(p_cbw->dir, 7) )
+      if (SCSI_CMD_READ_10 == p_cbw->command[0])
       {
-        if ( SCSI_CMD_WRITE_10 != p_cbw->command[0] )
+        p_msc->xferred_len += xferred_bytes;
+
+        if ( p_msc->xferred_len >= p_msc->total_len )
+        {
+          // Data Stage is complete
+          p_msc->stage = MSC_STAGE_STATUS;
+        }else
+        {
+          proc_read10_cmd(rhport, p_msc);
+        }
+      }
+      else if (SCSI_CMD_WRITE_10 == p_cbw->command[0])
+      {
+        proc_write10_new_data(rhport, p_msc, xferred_bytes);
+      }
+      else
+      {
+        // OUT transfer, invoke callback if needed
+        if ( !tu_bit_test(p_cbw->dir, 7) )
         {
           int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, p_msc->total_len);
 
@@ -406,74 +416,46 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
             p_csw->status = MSC_CSW_STATUS_PASSED;
           }
         }
+
+        p_msc->xferred_len += xferred_bytes;
+
+        if ( p_msc->xferred_len >= p_msc->total_len )
+        {
+          // Data Stage is complete
+          p_msc->stage = MSC_STAGE_STATUS;
+        }
         else
         {
-          uint16_t const block_sz = p_cbw->total_bytes / rdwr10_get_blockcount(p_cbw->command);
-
-          // Adjust lba with transferred bytes
-          uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz);
-
-          // Application can consume smaller bytes
-          int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, p_msc->xferred_len % block_sz, _mscd_buf, xferred_bytes);
-
-          if ( nbytes < 0 )
-          {
-            // negative means error -> skip to status phase, status in CSW set to failed
-            p_csw->data_residue = p_cbw->total_bytes - p_msc->xferred_len;
-            p_csw->status       = MSC_CSW_STATUS_FAILED;
-            p_msc->stage        = MSC_STAGE_STATUS;
-
-            tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); // Sense = Invalid Command Operation
-            break;
-          }else
-          {
-            // Application consume less than what we got (including zero)
-            if ( nbytes < (int32_t) xferred_bytes )
-            {
-              if ( nbytes > 0 )
-              {
-                p_msc->xferred_len += nbytes;
-                memmove(_mscd_buf, _mscd_buf+nbytes, xferred_bytes-nbytes);
-              }
-
-              // simulate an transfer complete with adjusted parameters --> this driver callback will fired again
-              dcd_event_xfer_complete(rhport, p_msc->ep_out, xferred_bytes-nbytes, XFER_RESULT_SUCCESS, false);
-
-              return true; // skip the rest
-            }
-            else
-            {
-              // Application consume all bytes in our buffer. Nothing to do, process with normal flow
-            }
-          }
-        }
-      }
-
-      // Accumulate data so far
-      p_msc->xferred_len += xferred_bytes;
-
-      if ( p_msc->xferred_len >= p_msc->total_len )
-      {
-        // Data Stage is complete
-        p_msc->stage = MSC_STAGE_STATUS;
-      }
-      else
-      {
-        // READ10 & WRITE10 Can be executed with large bulk of data e.g write 8K bytes (several flash write)
-        // We break it into multiple smaller command whose data size is up to CFG_TUD_MSC_EP_BUFSIZE
-        if (SCSI_CMD_READ_10 == p_cbw->command[0])
-        {
-          proc_read10_cmd(rhport, p_msc);
-        }
-        else if (SCSI_CMD_WRITE_10 == p_cbw->command[0])
-        {
-          proc_write10_cmd(rhport, p_msc);
-        }else
-        {
-          // No other command take more than one transfer yet -> unlikely error
+          // No command take more than one transfer yet -> unlikely error
           TU_BREAKPOINT();
         }
       }
+
+//      // Accumulate data so far
+//      p_msc->xferred_len += xferred_bytes;
+//
+//      if ( p_msc->xferred_len >= p_msc->total_len )
+//      {
+//        // Data Stage is complete
+//        p_msc->stage = MSC_STAGE_STATUS;
+//      }
+//      else
+//      {
+//        // READ10 & WRITE10 Can be executed with large bulk of data e.g write 8K bytes (several flash write)
+//        // We break it into multiple smaller command whose data size is up to CFG_TUD_MSC_EP_BUFSIZE
+//        if (SCSI_CMD_READ_10 == p_cbw->command[0])
+//        {
+//          proc_read10_cmd(rhport, p_msc);
+//        }
+//        else if (SCSI_CMD_WRITE_10 == p_cbw->command[0])
+//        {
+//          proc_write10_cmd(rhport, p_msc);
+//        }else
+//        {
+//          // No other command take more than one transfer yet -> unlikely error
+//          TU_BREAKPOINT();
+//        }
+//      }
     break;
 
     case MSC_STAGE_STATUS:
@@ -535,6 +517,8 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
   (void) bufsize; // TODO refractor later
   int32_t resplen;
 
+  mscd_interface_t* p_msc = &_mscd_itf;
+
   switch ( scsi_cmd[0] )
   {
     case SCSI_CMD_TEST_UNIT_READY:
@@ -545,7 +529,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         resplen = - 1;
 
         // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
-        if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
+        if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
       }
     break;
 
@@ -561,7 +545,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
           resplen = - 1;
 
           // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
-          if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
+          if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
         }
       }
     break;
@@ -582,7 +566,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         resplen = -1;
 
         // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
-        if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
+        if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
       }else
       {
         scsi_read_capacity10_resp_t read_capa10;
@@ -618,7 +602,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         resplen = -1;
 
         // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
-        if ( _mscd_itf.sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
+        if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
       }else
       {
         read_fmt_capa.block_num = tu_htonl(block_count);
@@ -685,9 +669,9 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
 
       sense_rsp.add_sense_len = sizeof(scsi_sense_fixed_resp_t) - 8;
 
-      sense_rsp.sense_key           = _mscd_itf.sense_key;
-      sense_rsp.add_sense_code      = _mscd_itf.add_sense_code;
-      sense_rsp.add_sense_qualifier = _mscd_itf.add_sense_qualifier;
+      sense_rsp.sense_key           = p_msc->sense_key;
+      sense_rsp.add_sense_code      = p_msc->add_sense_code;
+      sense_rsp.add_sense_qualifier = p_msc->add_sense_qualifier;
 
       resplen = sizeof(sense_rsp);
       memcpy(buffer, &sense_rsp, resplen);
@@ -703,15 +687,33 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
   return resplen;
 }
 
+
+static inline uint32_t rdwr10_get_lba(uint8_t const command[])
+{
+  // use offsetof to avoid pointer to the odd/unaligned address
+  uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba));
+
+  // lba is in Big Endian
+  return tu_ntohl(lba);
+}
+
+static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw)
+{
+  // first extract block count in the command
+  uint16_t block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count));
+  block_count = tu_ntohs(block_count);
+
+  // invalid block count
+  if (block_count == 0) return 0;
+
+  return cbw->total_bytes / block_count;
+}
+
 static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
 {
   msc_cbw_t const * p_cbw = &p_msc->cbw;
-  msc_csw_t       * p_csw = &p_msc->csw;
 
-  uint16_t const block_cnt = rdwr10_get_blockcount(p_cbw->command);
-  TU_ASSERT(block_cnt, ); // prevent div by zero
-
-  uint16_t const block_sz = p_cbw->total_bytes / block_cnt;
+  uint16_t const block_sz = rdwr10_get_blocksize(p_cbw);
   TU_ASSERT(block_sz, ); // prevent div by zero
 
   // Adjust lba with transferred bytes
@@ -726,11 +728,11 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   if ( nbytes < 0 )
   {
     // negative means error -> endpoint is stalled & status in CSW set to failed
-    p_msc->stage = MSC_STAGE_STATUS;
-    p_csw->data_residue = p_cbw->total_bytes - p_msc->xferred_len;
-    p_csw->status       = MSC_CSW_STATUS_FAILED;
 
-    tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); // Sense = Invalid Command Operation
+    // Sense = Flash not ready for access
+    tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00);
+
+    fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
     usbd_edpt_stall(rhport, p_msc->ep_in);
   }
   else if ( nbytes == 0 )
@@ -757,13 +759,10 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   if ( !writable )
   {
     // Not writable, complete this SCSI op with error
-    msc_csw_t *p_csw = &p_msc->csw;
+    // Sense = Write protected
+    tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00);
 
-    p_msc->stage = MSC_STAGE_STATUS;
-    p_csw->status = MSC_CSW_STATUS_FAILED;
-    p_csw->data_residue = p_cbw->total_bytes;
-
-    tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00);    // Sense = Write protected
+    fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
     usbd_edpt_stall(rhport, p_msc->ep_out);
     return;
   }
@@ -775,4 +774,58 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, nbytes), );
 }
 
+// process new data arrived from WRITE10
+static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes)
+{
+  msc_cbw_t const * p_cbw = &p_msc->cbw;
+
+  uint16_t const block_sz = rdwr10_get_blocksize(p_cbw);
+  TU_ASSERT(block_sz, ); // prevent div by zero
+
+  // Adjust lba with transferred bytes
+  uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz);
+
+  // Application can consume smaller bytes
+  int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, p_msc->xferred_len % block_sz, _mscd_buf, xferred_bytes);
+
+  if ( nbytes < 0 )
+  {
+    // negative means error -> failed this scsi op
+
+    // Sense = Flash not ready for access
+    tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00);
+
+    fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
+    usbd_edpt_stall(rhport, p_msc->ep_out);
+  }else
+  {
+    // Application consume less than what we got (including zero)
+    if ( nbytes < (int32_t) xferred_bytes )
+    {
+      if ( nbytes > 0 )
+      {
+        p_msc->xferred_len += nbytes;
+        memmove(_mscd_buf, _mscd_buf+nbytes, xferred_bytes-nbytes);
+      }
+
+      // simulate an transfer complete with adjusted parameters --> this driver callback will fired again
+      dcd_event_xfer_complete(rhport, p_msc->ep_out, xferred_bytes-nbytes, XFER_RESULT_SUCCESS, false);
+    }
+    else
+    {
+      // Application consume all bytes in our buffer, prepare to receive more data from host
+      p_msc->xferred_len += xferred_bytes;
+
+      if ( p_msc->xferred_len >= p_msc->total_len )
+      {
+        // Data Stage is complete
+        p_msc->stage = MSC_STAGE_STATUS;
+      }else
+      {
+        proc_write10_cmd(rhport, p_msc);
+      }
+    }
+  }
+}
+
 #endif

From 2667ce6981b409a0431a00d48a37f58bf3aa5875 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 Aug 2021 17:50:02 +0700
Subject: [PATCH 0389/2085] fix BOT case 2 test compliant

---
 src/class/msc/msc_device.c | 34 +++++++---------------------------
 1 file changed, 7 insertions(+), 27 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 716b7e503..cc495a1c4 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -430,32 +430,6 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           TU_BREAKPOINT();
         }
       }
-
-//      // Accumulate data so far
-//      p_msc->xferred_len += xferred_bytes;
-//
-//      if ( p_msc->xferred_len >= p_msc->total_len )
-//      {
-//        // Data Stage is complete
-//        p_msc->stage = MSC_STAGE_STATUS;
-//      }
-//      else
-//      {
-//        // READ10 & WRITE10 Can be executed with large bulk of data e.g write 8K bytes (several flash write)
-//        // We break it into multiple smaller command whose data size is up to CFG_TUD_MSC_EP_BUFSIZE
-//        if (SCSI_CMD_READ_10 == p_cbw->command[0])
-//        {
-//          proc_read10_cmd(rhport, p_msc);
-//        }
-//        else if (SCSI_CMD_WRITE_10 == p_cbw->command[0])
-//        {
-//          proc_write10_cmd(rhport, p_msc);
-//        }else
-//        {
-//          // No other command take more than one transfer yet -> unlikely error
-//          TU_BREAKPOINT();
-//        }
-//      }
     break;
 
     case MSC_STAGE_STATUS:
@@ -714,7 +688,13 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   msc_cbw_t const * p_cbw = &p_msc->cbw;
 
   uint16_t const block_sz = rdwr10_get_blocksize(p_cbw);
-  TU_ASSERT(block_sz, ); // prevent div by zero
+
+  if ( block_sz == 0 )
+  {
+    // 6.7.1 BOT The 13 Cases: case 2 and 3 when cbw->total_bytes == 0
+    fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
+    return;
+  }
 
   // Adjust lba with transferred bytes
   uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz);

From e01239ccc936d32cb2933dba3a78555d0e47d17c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 Aug 2021 20:05:56 +0700
Subject: [PATCH 0390/2085] more msc refactoring

---
 src/class/msc/msc_device.c | 35 ++++++++++++++++++++++-------------
 1 file changed, 22 insertions(+), 13 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index cc495a1c4..a25fa6109 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -107,6 +107,18 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status
 
   // failed but sense key is not set: default to Illegal Request
   if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+
+  // If there is data stage, stall it
+  if ( p_cbw->total_bytes )
+  {
+    if ( tu_bit_test(p_cbw->dir, 7) )
+    {
+      usbd_edpt_stall(rhport, p_msc->ep_in);
+    }else
+    {
+      usbd_edpt_stall(rhport, p_msc->ep_out);
+    }
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -343,12 +355,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, p_msc->total_len) );
         }else
         {
-          int32_t resplen;
-
           // First process if it is a built-in commands
-          resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, _mscd_buf, sizeof(_mscd_buf));
+          int32_t resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, _mscd_buf, sizeof(_mscd_buf));
 
-          // Not built-in, invoke user callback
+          // Invoke user callback if not built-in
           if ( (resplen < 0) && (p_msc->sense_key == 0) )
           {
             resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, p_msc->total_len);
@@ -356,10 +366,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
 
           if ( resplen < 0 )
           {
+            // unsupported command
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-
-            // Stall bulk In if needed
-            if (p_cbw->total_bytes) usbd_edpt_stall(rhport, p_msc->ep_in);
           }
           else
           {
@@ -692,7 +700,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   if ( block_sz == 0 )
   {
     // 6.7.1 BOT The 13 Cases: case 2 and 3 when cbw->total_bytes == 0
-    fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
+    fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
     return;
   }
 
@@ -713,7 +721,6 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
     tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00);
 
     fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-    usbd_edpt_stall(rhport, p_msc->ep_in);
   }
   else if ( nbytes == 0 )
   {
@@ -741,9 +748,7 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
     // Not writable, complete this SCSI op with error
     // Sense = Write protected
     tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00);
-
     fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-    usbd_edpt_stall(rhport, p_msc->ep_out);
     return;
   }
 
@@ -760,7 +765,12 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
   msc_cbw_t const * p_cbw = &p_msc->cbw;
 
   uint16_t const block_sz = rdwr10_get_blocksize(p_cbw);
-  TU_ASSERT(block_sz, ); // prevent div by zero
+  if ( block_sz == 0 )
+  {
+    // 6.7.1 BOT The 13 Cases: case 2 and 3 when cbw->total_bytes == 0
+    fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
+    return;
+  }
 
   // Adjust lba with transferred bytes
   uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz);
@@ -776,7 +786,6 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
     tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00);
 
     fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
-    usbd_edpt_stall(rhport, p_msc->ep_out);
   }else
   {
     // Application consume less than what we got (including zero)

From 81c73c235f477adf753ffe40c1d0192185d798ba Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 Aug 2021 22:30:30 +0700
Subject: [PATCH 0391/2085] implement dcd_edpt_close_all() for nrf52840

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 34 ++++++++++++++++++++++++---
 1 file changed, 31 insertions(+), 3 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index efc4d3183..7dc5731ab 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -366,8 +366,34 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 
 void dcd_edpt_close_all (uint8_t rhport)
 {
-  (void) rhport;
-  // TODO implement dcd_edpt_close_all()
+  // disable interrupt to prevent race condition
+  dcd_int_disable(rhport);
+
+  // disable all non-control (bulk + interrupt) endpoints
+  for ( uint8_t ep = 1; ep < EP_CBI_COUNT; ep++ )
+  {
+    NRF_USBD->INTENCLR = TU_BIT(USBD_INTEN_ENDEPOUT0_Pos + ep) | TU_BIT(USBD_INTEN_ENDEPIN0_Pos + ep);
+
+    NRF_USBD->TASKS_STARTEPIN[ep] = 0;
+    NRF_USBD->TASKS_STARTEPOUT[ep] = 0;
+
+    tu_memclr(_dcd.xfer[ep], 2*sizeof(xfer_td_t));
+  }
+
+  // disable both ISO
+  NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk | USBD_INTENCLR_ENDISOOUT_Msk | USBD_INTENCLR_ENDISOIN_Msk;
+  NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_OneDir;
+
+  NRF_USBD->TASKS_STARTISOIN  = 0;
+  NRF_USBD->TASKS_STARTISOOUT = 0;
+
+  tu_memclr(_dcd.xfer[EP_ISO_NUM], 2*sizeof(xfer_td_t));
+
+  // de-activate all non-control
+  NRF_USBD->EPOUTEN = 1UL;
+  NRF_USBD->EPINEN = 1UL;
+
+  dcd_int_enable(rhport);
 }
 
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
@@ -514,7 +540,9 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 void bus_reset(void)
 {
   // 6.35.6 USB controller automatically disabled all endpoints (except control)
-  // i.e EPOUTEN and EPINEN and reset USBADDR to 0
+  NRF_USBD->EPOUTEN = 1UL;
+  NRF_USBD->EPINEN = 1UL;
+
   for(int i=0; i<8; i++)
   {
     NRF_USBD->TASKS_STARTEPIN[i] = 0;

From 8bad0af849f79f56940ba2d1ea3442b58c75861d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 Aug 2021 22:31:08 +0700
Subject: [PATCH 0392/2085] explicitly clear stall and data toggle for edpoint
 upon open()

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 7dc5731ab..c962d9228 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -306,8 +306,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
   (void) rhport;
 
-  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
+  uint8_t const ep_addr = desc_edpt->bEndpointAddress;
+  uint8_t const epnum   = tu_edpt_number(ep_addr);
+  uint8_t const dir     = tu_edpt_dir(ep_addr);
 
   _dcd.xfer[epnum][dir].mps = desc_edpt->wMaxPacketSize.size;
 
@@ -359,6 +360,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
       NRF_USBD->EPINEN  |= USBD_EPINEN_ISOIN_Msk;
     }
   }
+
+  // clear stall and reset DataToggle
+  NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr;
+  NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
+
   __ISB(); __DSB();
 
   return true;

From c6b9f8a530e9dd9a6ec7e4f55016f275ddcdaa67 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 Aug 2021 23:33:11 +0700
Subject: [PATCH 0393/2085] fix msc case 3 complaint test

---
 src/class/msc/msc_device.c | 78 ++++++++++++++++++--------------------
 1 file changed, 37 insertions(+), 41 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index a25fa6109..11fc4e80f 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -121,6 +121,27 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status
   }
 }
 
+static inline uint32_t rdwr10_get_lba(uint8_t const command[])
+{
+  // use offsetof to avoid pointer to the odd/unaligned address
+  uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba));
+
+  // lba is in Big Endian
+  return tu_ntohl(lba);
+}
+
+static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw)
+{
+  // first extract block count in the command
+  uint16_t block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count));
+  block_count = tu_ntohs(block_count);
+
+  // invalid block count
+  if (block_count == 0) return 0;
+
+  return cbw->total_bytes / block_count;
+}
+
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
@@ -336,13 +357,21 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       p_msc->total_len = p_cbw->total_bytes;
       p_msc->xferred_len = 0;
 
-      if (SCSI_CMD_READ_10 == p_cbw->command[0])
+      if (SCSI_CMD_READ_10 == p_cbw->command[0] || SCSI_CMD_WRITE_10 == p_cbw->command[0])
       {
-        proc_read10_cmd(rhport, p_msc);
-      }
-      else if (SCSI_CMD_WRITE_10 == p_cbw->command[0])
-      {
-        proc_write10_cmd(rhport, p_msc);
+        if ( rdwr10_get_blocksize(p_cbw) == 0 )
+        {
+          // Invalid CBW length == 0 (not match SCSI command block count)
+          // 6.7.1 BOT The 13 Cases: case 2 and case 3 -> phase error
+          fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
+        }
+        else if (SCSI_CMD_READ_10 == p_cbw->command[0])
+        {
+          proc_read10_cmd(rhport, p_msc);
+        }else
+        {
+          proc_write10_cmd(rhport, p_msc);
+        }
       }
       else
       {
@@ -669,41 +698,13 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
   return resplen;
 }
 
-
-static inline uint32_t rdwr10_get_lba(uint8_t const command[])
-{
-  // use offsetof to avoid pointer to the odd/unaligned address
-  uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba));
-
-  // lba is in Big Endian
-  return tu_ntohl(lba);
-}
-
-static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw)
-{
-  // first extract block count in the command
-  uint16_t block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count));
-  block_count = tu_ntohs(block_count);
-
-  // invalid block count
-  if (block_count == 0) return 0;
-
-  return cbw->total_bytes / block_count;
-}
-
 static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
 {
   msc_cbw_t const * p_cbw = &p_msc->cbw;
 
+  // block size already verified not zero
   uint16_t const block_sz = rdwr10_get_blocksize(p_cbw);
 
-  if ( block_sz == 0 )
-  {
-    // 6.7.1 BOT The 13 Cases: case 2 and 3 when cbw->total_bytes == 0
-    fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
-    return;
-  }
-
   // Adjust lba with transferred bytes
   uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz);
 
@@ -764,13 +765,8 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
 {
   msc_cbw_t const * p_cbw = &p_msc->cbw;
 
+  // block size already verified not zero
   uint16_t const block_sz = rdwr10_get_blocksize(p_cbw);
-  if ( block_sz == 0 )
-  {
-    // 6.7.1 BOT The 13 Cases: case 2 and 3 when cbw->total_bytes == 0
-    fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
-    return;
-  }
 
   // Adjust lba with transferred bytes
   uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz);

From 53ea1e13243eae30455cc008eda0ee5d63ccf361 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 Aug 2021 23:52:59 +0700
Subject: [PATCH 0394/2085] fix msc test case 8 and 10

---
 src/class/msc/msc_device.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 11fc4e80f..e29cd473a 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -357,17 +357,25 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       p_msc->total_len = p_cbw->total_bytes;
       p_msc->xferred_len = 0;
 
-      if (SCSI_CMD_READ_10 == p_cbw->command[0] || SCSI_CMD_WRITE_10 == p_cbw->command[0])
+      if ( SCSI_CMD_READ_10 == p_cbw->command[0] )
       {
-        if ( rdwr10_get_blocksize(p_cbw) == 0 )
+        // Invalid CBW length == 0 or Direction bit is incorrect
+        // 6.7 The 13 Cases: case 2, case 3, case 10 -> phase error
+        if ( rdwr10_get_blocksize(p_cbw) == 0 || !tu_bit_test(p_cbw->dir, 7) )
         {
-          // Invalid CBW length == 0 (not match SCSI command block count)
-          // 6.7.1 BOT The 13 Cases: case 2 and case 3 -> phase error
           fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
-        }
-        else if (SCSI_CMD_READ_10 == p_cbw->command[0])
+        }else
         {
           proc_read10_cmd(rhport, p_msc);
+        }
+      }
+      else if (SCSI_CMD_WRITE_10 == p_cbw->command[0])
+      {
+        // Invalid CBW length == 0 or Direction bit is incorrect
+        // 6.7 The 13 Cases: case 2, case 3, case 8 -> phase error
+        if ( rdwr10_get_blocksize(p_cbw) == 0 || tu_bit_test(p_cbw->dir, 7) )
+        {
+          fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
         }else
         {
           proc_write10_cmd(rhport, p_msc);

From a53839ef44345377e863e4635909c2dacc81f059 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 28 Aug 2021 01:23:20 +0700
Subject: [PATCH 0395/2085] correct msc example return type of
 tud_msc_scsi_cb()

---
 examples/device/cdc_msc/src/msc_disk.c               | 2 +-
 examples/device/cdc_msc_freertos/src/msc_disk.c      | 2 +-
 examples/device/dynamic_configuration/src/msc_disk.c | 2 +-
 examples/device/msc_dual_lun/src/msc_disk_dual.c     | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index 32f2563cb..42b080cce 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -229,7 +229,7 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
   // read10 & write10 has their own callback and MUST not be handled here
 
   void const* response = NULL;
-  uint16_t resplen = 0;
+  int32_t resplen = 0;
 
   // most scsi handled is input
   bool in_xfer = true;
diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c
index 5aa7befc9..a4826fbe1 100644
--- a/examples/device/cdc_msc_freertos/src/msc_disk.c
+++ b/examples/device/cdc_msc_freertos/src/msc_disk.c
@@ -208,7 +208,7 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
   // read10 & write10 has their own callback and MUST not be handled here
 
   void const* response = NULL;
-  uint16_t resplen = 0;
+  int32_t resplen = 0;
 
   // most scsi handled is input
   bool in_xfer = true;
diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c
index 5aa7befc9..a4826fbe1 100644
--- a/examples/device/dynamic_configuration/src/msc_disk.c
+++ b/examples/device/dynamic_configuration/src/msc_disk.c
@@ -208,7 +208,7 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
   // read10 & write10 has their own callback and MUST not be handled here
 
   void const* response = NULL;
-  uint16_t resplen = 0;
+  int32_t resplen = 0;
 
   // most scsi handled is input
   bool in_xfer = true;
diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c
index cc7dfae0e..3cc59b46c 100644
--- a/examples/device/msc_dual_lun/src/msc_disk_dual.c
+++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c
@@ -307,7 +307,7 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
   // read10 & write10 has their own callback and MUST not be handled here
 
   void const* response = NULL;
-  uint16_t resplen = 0;
+  int32_t resplen = 0;
 
   // most scsi handled is input
   bool in_xfer = true;

From 54013737d5949152959e470d3df3d0465296e251 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 28 Aug 2021 20:26:56 +0700
Subject: [PATCH 0396/2085] fix msc example with out of bound lba (due to
 compliant test)

---
 examples/device/cdc_msc/src/msc_disk.c               | 6 ++++++
 examples/device/cdc_msc_freertos/src/msc_disk.c      | 6 ++++++
 examples/device/dynamic_configuration/src/msc_disk.c | 6 ++++++
 examples/device/msc_dual_lun/src/msc_disk_dual.c     | 6 ++++++
 4 files changed, 24 insertions(+)

diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index 42b080cce..cad2602a2 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -188,6 +188,9 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
 {
   (void) lun;
 
+  // out of ramdisk
+  if ( lba >= DISK_BLOCK_NUM ) return -1;
+
   uint8_t const* addr = msc_disk[lba] + offset;
   memcpy(buffer, addr, bufsize);
 
@@ -211,6 +214,9 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
 {
   (void) lun;
 
+  // out of ramdisk
+  if ( lba >= DISK_BLOCK_NUM ) return -1;
+
 #ifndef CFG_EXAMPLE_MSC_READONLY
   uint8_t* addr = msc_disk[lba] + offset;
   memcpy(addr, buffer, bufsize);
diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c
index a4826fbe1..b9205f0c2 100644
--- a/examples/device/cdc_msc_freertos/src/msc_disk.c
+++ b/examples/device/cdc_msc_freertos/src/msc_disk.c
@@ -178,6 +178,9 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
 {
   (void) lun;
 
+  // out of ramdisk
+  if ( lba >= DISK_BLOCK_NUM ) return -1;
+
   uint8_t const* addr = msc_disk[lba] + offset;
   memcpy(buffer, addr, bufsize);
 
@@ -190,6 +193,9 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
 {
   (void) lun;
 
+  // out of ramdisk
+  if ( lba >= DISK_BLOCK_NUM ) return -1;
+
 #ifndef CFG_EXAMPLE_MSC_READONLY
   uint8_t* addr = msc_disk[lba] + offset;
   memcpy(addr, buffer, bufsize);
diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c
index a4826fbe1..b9205f0c2 100644
--- a/examples/device/dynamic_configuration/src/msc_disk.c
+++ b/examples/device/dynamic_configuration/src/msc_disk.c
@@ -178,6 +178,9 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
 {
   (void) lun;
 
+  // out of ramdisk
+  if ( lba >= DISK_BLOCK_NUM ) return -1;
+
   uint8_t const* addr = msc_disk[lba] + offset;
   memcpy(buffer, addr, bufsize);
 
@@ -190,6 +193,9 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
 {
   (void) lun;
 
+  // out of ramdisk
+  if ( lba >= DISK_BLOCK_NUM ) return -1;
+
 #ifndef CFG_EXAMPLE_MSC_READONLY
   uint8_t* addr = msc_disk[lba] + offset;
   memcpy(addr, buffer, bufsize);
diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c
index 3cc59b46c..18d3ca0d7 100644
--- a/examples/device/msc_dual_lun/src/msc_disk_dual.c
+++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c
@@ -268,6 +268,9 @@ bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, boo
 // Copy disk's data to buffer (up to bufsize) and return number of copied bytes.
 int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize)
 {
+  // out of ramdisk
+  if ( lba >= DISK_BLOCK_NUM ) return -1;
+
   uint8_t const* addr = (lun ? msc_disk1[lba] : msc_disk0[lba]) + offset;
   memcpy(buffer, addr, bufsize);
 
@@ -289,6 +292,9 @@ bool tud_msc_is_writable_cb (uint8_t lun)
 // Process data in buffer to disk's storage and return number of written bytes
 int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize)
 {
+  // out of ramdisk
+  if ( lba >= DISK_BLOCK_NUM ) return -1;
+
 #ifndef CFG_EXAMPLE_MSC_READONLY
   uint8_t* addr = (lun ? msc_disk1[lba] : msc_disk0[lba])  + offset;
   memcpy(addr, buffer, bufsize);

From be98cd56c7ac3bbd8b8762e42f752c9cec7c92f0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 29 Aug 2021 00:29:20 +0700
Subject: [PATCH 0397/2085] update msc to be more robuse

add more log, pass more complaint test
---
 src/class/msc/msc_device.c | 87 ++++++++++++++++++++++++++++----------
 1 file changed, 65 insertions(+), 22 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index e29cd473a..792d26dea 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -62,7 +62,7 @@ typedef struct
 
   // Bulk Only Transfer (BOT) Protocol
   uint8_t  stage;
-  uint32_t total_len;
+  uint32_t total_len;   // byte to be transferred, can be smaller than total_bytes in cbw
   uint32_t xferred_len; // numbered of bytes transferred so far in the Data Stage
 
   // Sense Response Data
@@ -83,8 +83,16 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
 static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc);
 static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes);
 
+TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir)
+{
+  return tu_bit_test(dir, 7);
+}
+
 static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc)
 {
+  // Data residue is always = host expect - actual transferred
+  p_msc->csw.data_residue = p_msc->cbw.total_bytes - p_msc->xferred_len;
+
   p_msc->stage = MSC_STAGE_STATUS_SENT;
   return usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t));
 }
@@ -100,10 +108,9 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status
   msc_cbw_t const * p_cbw = &p_msc->cbw;
   msc_csw_t       * p_csw = &p_msc->csw;
 
-  p_csw->status       = status;
-  p_csw->data_residue = p_cbw->total_bytes - p_msc->xferred_len;
-
-  p_msc->stage = MSC_STAGE_STATUS;
+  // data_residue will be calculated before sending out csw
+  p_csw->status = status;
+  p_msc->stage  = MSC_STAGE_STATUS;
 
   // failed but sense key is not set: default to Illegal Request
   if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
@@ -111,7 +118,7 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status
   // If there is data stage, stall it
   if ( p_cbw->total_bytes )
   {
-    if ( tu_bit_test(p_cbw->dir, 7) )
+    if ( is_data_in(p_cbw->dir) )
     {
       usbd_edpt_stall(rhport, p_msc->ep_in);
     }else
@@ -335,6 +342,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
 
       if ( !(xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE) )
       {
+        TU_LOG(MSC_DEBUG, "  SCSI CBW is not valid\r\n");
+
         // BOT 6.6.1 If CBW is not valid stall both endpoints until reset recovery
         p_msc->stage = MSC_STAGE_NEED_RESET;
 
@@ -351,6 +360,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       p_csw->signature    = MSC_CSW_SIGNATURE;
       p_csw->tag          = p_cbw->tag;
       p_csw->data_residue = 0;
+      p_csw->status       = MSC_CSW_STATUS_PASSED;
 
       /*------------- Parse command and prepare DATA -------------*/
       p_msc->stage = MSC_STAGE_DATA;
@@ -360,9 +370,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       if ( SCSI_CMD_READ_10 == p_cbw->command[0] )
       {
         // Invalid CBW length == 0 or Direction bit is incorrect
-        // 6.7 The 13 Cases: case 2, case 3, case 10 -> phase error
-        if ( rdwr10_get_blocksize(p_cbw) == 0 || !tu_bit_test(p_cbw->dir, 7) )
+        // 6.7 The 13 Cases: case 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di) -> phase error
+        if ( rdwr10_get_blocksize(p_cbw) == 0 || !is_data_in(p_cbw->dir) )
         {
+          TU_LOG(MSC_DEBUG, "  SCSI ase 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di)\r\n");
           fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
         }else
         {
@@ -372,9 +383,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       else if (SCSI_CMD_WRITE_10 == p_cbw->command[0])
       {
         // Invalid CBW length == 0 or Direction bit is incorrect
-        // 6.7 The 13 Cases: case 2, case 3, case 8 -> phase error
-        if ( rdwr10_get_blocksize(p_cbw) == 0 || tu_bit_test(p_cbw->dir, 7) )
+        // 6.7 The 13 Cases: case 2 (Hn < Do), case 3 (Hn < Do), case 8 (Hi <> Do) -> phase error
+        if ( rdwr10_get_blocksize(p_cbw) == 0 || is_data_in(p_cbw->dir) )
         {
+          TU_LOG(MSC_DEBUG, "  SCSI ase 2 (Hn < Di), case 3 (Hn < Do), case 8 (Hi <> Do)\r\n");
           fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
         }else
         {
@@ -386,9 +398,12 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         // For other SCSI commands
         // 1. OUT : queue transfer (invoke app callback after done)
         // 2. IN & Zero: Process if is built-in, else Invoke app callback. Skip DATA if zero length
-        if ( (p_cbw->total_bytes > 0 ) && !tu_bit_test(p_cbw->dir, 7) )
+        if ( (p_cbw->total_bytes > 0 ) && !is_data_in(p_cbw->dir) )
         {
-          // queue transfer
+          // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first
+          // but it is OK to just receive data then responded with failed status
+
+          // Prepare for Data stage
           TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, p_msc->total_len) );
         }else
         {
@@ -404,20 +419,34 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           if ( resplen < 0 )
           {
             // unsupported command
+            TU_LOG(MSC_DEBUG, "  SCSI unsupported command\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
           }
+          else if (resplen == 0)
+          {
+            if (p_cbw->total_bytes)
+            {
+              // 6.7 The 13 Cases: case 4 (Hi > Dn)
+              TU_LOG(MSC_DEBUG, "  SCSI case 4 (Hi > Dn): %lu\r\n", p_cbw->total_bytes);
+              fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
+            }else
+            {
+              // case 1 Hn = Dn: all good
+              p_msc->stage = MSC_STAGE_STATUS;
+            }
+          }
           else
           {
-            p_msc->total_len = (uint32_t) resplen;
-            p_csw->status = MSC_CSW_STATUS_PASSED;
-
-            if (p_msc->total_len)
+            if ( p_cbw->total_bytes == 0 )
             {
-              TU_ASSERT( p_cbw->total_bytes >= p_msc->total_len ); // cannot return more than host expect
-              TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, p_msc->total_len) );
+              // 6.7 The 13 Cases: case 2 (Hn < Di)
+              TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di): %lu\r\n", p_cbw->total_bytes);
+              fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
             }else
             {
-              p_msc->stage = MSC_STAGE_STATUS;
+              // cannot return more than host expect
+              p_msc->total_len = tu_min32((uint32_t) resplen, p_cbw->total_bytes);
+              TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, p_msc->total_len) );
             }
           }
         }
@@ -448,7 +477,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       else
       {
         // OUT transfer, invoke callback if needed
-        if ( !tu_bit_test(p_cbw->dir, 7) )
+        if ( !is_data_in(p_cbw->dir) )
         {
           int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, p_msc->total_len);
 
@@ -485,7 +514,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       // Wait for the Status phase to complete
       if( (ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t)) )
       {
-        TU_LOG(MSC_DEBUG, "  SCSI Status: %u\r\n", p_csw->status);
+        TU_LOG(MSC_DEBUG, "  SCSI Status = %u\r\n", p_csw->status);
         // TU_LOG_MEM(MSC_DEBUG, p_csw, xferred_bytes, 2);
 
         // Invoke complete callback if defined
@@ -507,6 +536,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         }
 
         TU_ASSERT( prepare_cbw(rhport, p_msc) );
+      }else
+      {
+        // Any xfer ended here is consider unknown error, ignore it
+        TU_LOG1("  Warning expect SCSI Status but received unknown data\r\n");
       }
     break;
 
@@ -518,7 +551,15 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     // skip status if epin is currently stalled, will do it when received Clear Stall request
     if ( !usbd_edpt_stalled(rhport,  p_msc->ep_in) )
     {
-      TU_ASSERT( send_csw(rhport, p_msc) );
+      if ( (p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir) )
+      {
+        // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status
+        TU_LOG(MSC_DEBUG, "  SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len);
+        usbd_edpt_stall(rhport, p_msc->ep_in);
+      }else
+      {
+        TU_ASSERT( send_csw(rhport, p_msc) );
+      }
     }
   }
 
@@ -725,6 +766,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   if ( nbytes < 0 )
   {
     // negative means error -> endpoint is stalled & status in CSW set to failed
+    TU_LOG(MSC_DEBUG, "  tud_msc_read10_cb() return -1\r\n");
 
     // Sense = Flash not ready for access
     tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00);
@@ -785,6 +827,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
   if ( nbytes < 0 )
   {
     // negative means error -> failed this scsi op
+    TU_LOG(MSC_DEBUG, "  tud_msc_write10_cb() return -1\r\n");
 
     // Sense = Flash not ready for access
     tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00);

From 66c292e2ecb2cbc888074f2801c50e019f0bacf3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 29 Aug 2021 00:34:21 +0700
Subject: [PATCH 0398/2085] fix a couple of nrf dcd issue

- limit out xact dma to prevent usbd overflow in certain situation after
stalled
- drained already acked data when stalling an OUT endpoint
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index c962d9228..2013c5649 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -206,7 +206,8 @@ static void xact_out_dma(uint8_t epnum)
   }
   else
   {
-    xact_len = (uint8_t)NRF_USBD->SIZE.EPOUT[epnum];
+    // limit xact len to remaining length
+    xact_len = tu_min16((uint16_t) NRF_USBD->SIZE.EPOUT[epnum], xfer->total_len - xfer->actual_len);
 
     // Trigger DMA move data from Endpoint -> SRAM
     NRF_USBD->EPOUT[epnum].PTR = (uint32_t) xfer->buffer;
@@ -480,10 +481,9 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     {
       if ( xfer->data_received )
       {
-        // Data may already be received previously
-        xfer->data_received = false;
-
+        // Data is already received previously
         // start DMA to copy to SRAM
+        xfer->data_received = false;
         xact_out_dma(epnum);
       }
       else
@@ -505,7 +505,11 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
+
   uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  xfer_td_t* xfer = get_td(epnum, dir);
 
   if ( epnum == 0 )
   {
@@ -513,6 +517,15 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
   }else if (epnum != EP_ISO_NUM)
   {
     NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_Stall << USBD_EPSTALL_STALL_Pos) | ep_addr;
+
+    // Note: nRF can auto ACK packet OUT before get stalled.
+    // There maybe data in endpoint fifo already, we need to pull it out
+    if ( (dir == TUSB_DIR_OUT) && xfer->data_received )
+    {
+      TU_LOG_LOCATION();
+      xfer->data_received = false;
+      xact_out_dma(epnum);
+    }
   }
 
   __ISB(); __DSB();
@@ -533,7 +546,6 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
     NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
 
     // Write any value to SIZE register will allow nRF to ACK/accept data
-    // Drop any pending data
     if (dir == TUSB_DIR_OUT) NRF_USBD->SIZE.EPOUT[epnum] = 0;
 
     __ISB(); __DSB();

From ad21b692775f5c75c09bc550ef77fdca64690a5a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 29 Aug 2021 12:05:34 +0700
Subject: [PATCH 0399/2085] fix nrf clear data toggle sequence when clearing
 stall

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 2013c5649..f40ba2d4f 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -539,12 +539,15 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 
   if ( epnum != 0 && epnum != EP_ISO_NUM )
   {
+    // reset data toggle to DATA0
+    // First write this register with VALUE=Nop to select the endpoint, then either read it to get the status from
+    // VALUE, or write it again with VALUE=Data0 or Data1
+    NRF_USBD->DTOGGLE = ep_addr;
+    NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
+
     // clear stall
     NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep_addr;
 
-    // reset data toggle to DATA0
-    NRF_USBD->DTOGGLE = (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos) | ep_addr;
-
     // Write any value to SIZE register will allow nRF to ACK/accept data
     if (dir == TUSB_DIR_OUT) NRF_USBD->SIZE.EPOUT[epnum] = 0;
 

From ee18cc42f2771cb63e7e5529f9be376cd0080f5e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 29 Aug 2021 12:06:10 +0700
Subject: [PATCH 0400/2085] msc handle more test, passed Command Self Test
 compliant

---
 src/class/msc/msc_device.c | 28 +++++++++++++++++-----------
 1 file changed, 17 insertions(+), 11 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 792d26dea..247575ed4 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -373,7 +373,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         // 6.7 The 13 Cases: case 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di) -> phase error
         if ( rdwr10_get_blocksize(p_cbw) == 0 || !is_data_in(p_cbw->dir) )
         {
-          TU_LOG(MSC_DEBUG, "  SCSI ase 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di)\r\n");
+          TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di)\r\n");
           fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
         }else
         {
@@ -386,7 +386,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         // 6.7 The 13 Cases: case 2 (Hn < Do), case 3 (Hn < Do), case 8 (Hi <> Do) -> phase error
         if ( rdwr10_get_blocksize(p_cbw) == 0 || is_data_in(p_cbw->dir) )
         {
-          TU_LOG(MSC_DEBUG, "  SCSI ase 2 (Hn < Di), case 3 (Hn < Do), case 8 (Hi <> Do)\r\n");
+          TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di), case 3 (Hn < Do), case 8 (Hi <> Do)\r\n");
           fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
         }else
         {
@@ -400,11 +400,16 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         // 2. IN & Zero: Process if is built-in, else Invoke app callback. Skip DATA if zero length
         if ( (p_cbw->total_bytes > 0 ) && !is_data_in(p_cbw->dir) )
         {
-          // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first
-          // but it is OK to just receive data then responded with failed status
-
-          // Prepare for Data stage
-          TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, p_msc->total_len) );
+          if (p_cbw->total_bytes > sizeof(_mscd_buf))
+          {
+            TU_LOG(MSC_DEBUG, "  SCSI reject non READ10/WRITE10 with large data\r\n");
+            fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
+          }else
+          {
+            // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first
+            // but it is OK to just receive data then responded with failed status
+            TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, p_msc->total_len) );
+          }
         }else
         {
           // First process if it is a built-in commands
@@ -483,11 +488,12 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
 
           if ( cb_result < 0 )
           {
-            p_csw->status = MSC_CSW_STATUS_FAILED;
-            tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); // Sense = Invalid Command Operation
+            // unsupported command
+            TU_LOG(MSC_DEBUG, "  SCSI unsupported command\r\n");
+            fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
           }else
           {
-            p_csw->status = MSC_CSW_STATUS_PASSED;
+            // TODO haven't implement this scenario any further yet
           }
         }
 
@@ -500,7 +506,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         }
         else
         {
-          // No command take more than one transfer yet -> unlikely error
+          // This scenario with command that take more than one transfer is already rejected at Command stage
           TU_BREAKPOINT();
         }
       }

From 4e3ed8159e420b80aa3d558d0ed728460ba4506f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 29 Aug 2021 13:34:47 +0700
Subject: [PATCH 0401/2085] passed all USBCV bot complaince test

---
 src/class/msc/msc_device.c | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 247575ed4..52dfcb836 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -108,20 +108,21 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status
   msc_cbw_t const * p_cbw = &p_msc->cbw;
   msc_csw_t       * p_csw = &p_msc->csw;
 
-  // data_residue will be calculated before sending out csw
-  p_csw->status = status;
-  p_msc->stage  = MSC_STAGE_STATUS;
+  p_csw->status       = status;
+  p_csw->data_residue = p_msc->cbw.total_bytes - p_msc->xferred_len;
+  p_msc->stage        = MSC_STAGE_STATUS;
 
   // failed but sense key is not set: default to Illegal Request
   if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
 
-  // If there is data stage, stall it
-  if ( p_cbw->total_bytes )
+  // If there is data stage and not yet complete, stall it
+  if ( p_cbw->total_bytes && p_csw->data_residue )
   {
     if ( is_data_in(p_cbw->dir) )
     {
       usbd_edpt_stall(rhport, p_msc->ep_in);
-    }else
+    }
+    else
     {
       usbd_edpt_stall(rhport, p_msc->ep_out);
     }
@@ -481,6 +482,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       }
       else
       {
+        p_msc->xferred_len += xferred_bytes;
+
         // OUT transfer, invoke callback if needed
         if ( !is_data_in(p_cbw->dir) )
         {
@@ -497,8 +500,6 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           }
         }
 
-        p_msc->xferred_len += xferred_bytes;
-
         if ( p_msc->xferred_len >= p_msc->total_len )
         {
           // Data Stage is complete
@@ -767,7 +768,8 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   int32_t nbytes = (int32_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len);
 
   // Application can consume smaller bytes
-  nbytes = tud_msc_read10_cb(p_cbw->lun, lba, p_msc->xferred_len % block_sz, _mscd_buf, (uint32_t) nbytes);
+  uint32_t const offset = p_msc->xferred_len % block_sz;
+  nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_buf, (uint32_t) nbytes);
 
   if ( nbytes < 0 )
   {
@@ -827,14 +829,18 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
   // Adjust lba with transferred bytes
   uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz);
 
-  // Application can consume smaller bytes
-  int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, p_msc->xferred_len % block_sz, _mscd_buf, xferred_bytes);
+  // Invoke callback to consume new data
+  uint32_t const offset = p_msc->xferred_len % block_sz;
+  int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_buf, xferred_bytes);
 
   if ( nbytes < 0 )
   {
     // negative means error -> failed this scsi op
     TU_LOG(MSC_DEBUG, "  tud_msc_write10_cb() return -1\r\n");
 
+    // update actual byte before failed
+    p_msc->xferred_len += xferred_bytes;
+
     // Sense = Flash not ready for access
     tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00);
 
@@ -842,7 +848,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
   }else
   {
     // Application consume less than what we got (including zero)
-    if ( nbytes < (int32_t) xferred_bytes )
+    if ( (uint32_t) nbytes < xferred_bytes )
     {
       if ( nbytes > 0 )
       {
@@ -850,12 +856,12 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
         memmove(_mscd_buf, _mscd_buf+nbytes, xferred_bytes-nbytes);
       }
 
-      // simulate an transfer complete with adjusted parameters --> this driver callback will fired again
+      // simulate an transfer complete with adjusted parameters --> callback will be invoked with adjusted parameter
       dcd_event_xfer_complete(rhport, p_msc->ep_out, xferred_bytes-nbytes, XFER_RESULT_SUCCESS, false);
     }
     else
     {
-      // Application consume all bytes in our buffer, prepare to receive more data from host
+      // Application consume all bytes in our buffer
       p_msc->xferred_len += xferred_bytes;
 
       if ( p_msc->xferred_len >= p_msc->total_len )
@@ -864,6 +870,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
         p_msc->stage = MSC_STAGE_STATUS;
       }else
       {
+        // prepare to receive more data from host
         proc_write10_cmd(rhport, p_msc);
       }
     }

From fdf1ff545f41c23f63e86d6debaa852e731d7644 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 29 Aug 2021 15:44:27 +0700
Subject: [PATCH 0402/2085] responding with status per-spec in test case 4

---
 src/class/msc/msc_device.c | 83 ++++++++++++++++++++++++++++----------
 1 file changed, 61 insertions(+), 22 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 52dfcb836..7dcd4983e 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -138,11 +138,16 @@ static inline uint32_t rdwr10_get_lba(uint8_t const command[])
   return tu_ntohl(lba);
 }
 
+static inline uint16_t rdwr10_get_blockcount(msc_cbw_t const* cbw)
+{
+  uint16_t const block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count));
+  return tu_ntohs(block_count);
+}
+
 static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw)
 {
   // first extract block count in the command
-  uint16_t block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count));
-  block_count = tu_ntohs(block_count);
+  uint16_t const block_count = rdwr10_get_blockcount(cbw);
 
   // invalid block count
   if (block_count == 0) return 0;
@@ -150,6 +155,43 @@ static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw)
   return cbw->total_bytes / block_count;
 }
 
+uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
+{
+  uint8_t status = MSC_CSW_STATUS_PASSED;
+  uint16_t const block_count = rdwr10_get_blockcount(cbw);
+
+  if ( cbw->total_bytes == 0 )
+  {
+    if ( block_count )
+    {
+      TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n");
+      status = MSC_CSW_STATUS_PHASE_ERROR;
+    }else
+    {
+      // no data transfer, only exist in complaint test suite
+    }
+  }else
+  {
+    if ( SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir) )
+    {
+      TU_LOG(MSC_DEBUG, "  SCSI case 10 (Ho <> Di)\r\n");
+      status = MSC_CSW_STATUS_PHASE_ERROR;
+    }
+    else if ( SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir) )
+    {
+      TU_LOG(MSC_DEBUG, "  SCSI case 8 (Hi <> Do)\r\n");
+      status = MSC_CSW_STATUS_PHASE_ERROR;
+    }
+    else if ( !block_count )
+    {
+      TU_LOG(MSC_DEBUG, "  SCSI case 4 Hi > Dn\r\n");
+      status =  MSC_CSW_STATUS_FAILED;
+    }
+  }
+
+  return status;
+}
+
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
@@ -368,30 +410,27 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       p_msc->total_len = p_cbw->total_bytes;
       p_msc->xferred_len = 0;
 
-      if ( SCSI_CMD_READ_10 == p_cbw->command[0] )
+      // Read10 or Write10
+      if ( (SCSI_CMD_READ_10 == p_cbw->command[0]) || (SCSI_CMD_WRITE_10 == p_cbw->command[0]) )
       {
-        // Invalid CBW length == 0 or Direction bit is incorrect
-        // 6.7 The 13 Cases: case 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di) -> phase error
-        if ( rdwr10_get_blocksize(p_cbw) == 0 || !is_data_in(p_cbw->dir) )
+        uint8_t const status = rdwr10_validate_cmd(p_cbw);
+
+        if ( status != MSC_CSW_STATUS_PASSED)
         {
-          TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di), case 3 (Hn < Do), case 10 (Ho <> Di)\r\n");
-          fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
+          fail_scsi_op(rhport, p_msc, status);
+        }else if ( p_cbw->total_bytes )
+        {
+          if (SCSI_CMD_READ_10 == p_cbw->command[0])
+          {
+            proc_read10_cmd(rhport, p_msc);
+          }else
+          {
+            proc_write10_cmd(rhport, p_msc);
+          }
         }else
         {
-          proc_read10_cmd(rhport, p_msc);
-        }
-      }
-      else if (SCSI_CMD_WRITE_10 == p_cbw->command[0])
-      {
-        // Invalid CBW length == 0 or Direction bit is incorrect
-        // 6.7 The 13 Cases: case 2 (Hn < Do), case 3 (Hn < Do), case 8 (Hi <> Do) -> phase error
-        if ( rdwr10_get_blocksize(p_cbw) == 0 || is_data_in(p_cbw->dir) )
-        {
-          TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di), case 3 (Hn < Do), case 8 (Hi <> Do)\r\n");
-          fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_PHASE_ERROR);
-        }else
-        {
-          proc_write10_cmd(rhport, p_msc);
+          // no data transfer, only exist in complaint test suite
+          p_msc->stage = MSC_STAGE_STATUS;
         }
       }
       else

From 00e66cf2e0bdb5221586f640dc25d26168ee1daf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 29 Aug 2021 21:26:47 +0700
Subject: [PATCH 0403/2085] remove old openh743i, explicitly disable systick
 when using freertos for H7

---
 .../STM32H743IITX_FLASH.ld                    |   0
 .../board.h                                   |   0
 .../board.mk                                  |   0
 hw/bsp/stm32h7/family.c                       |   3 +
 .../STM32H743IITX_FLASH.ld                    | 175 -------
 hw/bsp/waveshare_openh743i/board.c            | 495 ------------------
 hw/bsp/waveshare_openh743i/board.mk           |  64 ---
 .../waveshare_openh743i/stm32h7xx_hal_conf.h  | 483 -----------------
 8 files changed, 3 insertions(+), 1217 deletions(-)
 rename hw/bsp/stm32h7/boards/{waveshare_openh743i_2 => waveshare_openh743i}/STM32H743IITX_FLASH.ld (100%)
 rename hw/bsp/stm32h7/boards/{waveshare_openh743i_2 => waveshare_openh743i}/board.h (100%)
 rename hw/bsp/stm32h7/boards/{waveshare_openh743i_2 => waveshare_openh743i}/board.mk (100%)
 delete mode 100644 hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld
 delete mode 100644 hw/bsp/waveshare_openh743i/board.c
 delete mode 100644 hw/bsp/waveshare_openh743i/board.mk
 delete mode 100644 hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h

diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i_2/STM32H743IITX_FLASH.ld b/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32h7/boards/waveshare_openh743i_2/STM32H743IITX_FLASH.ld
rename to hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
similarity index 100%
rename from hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.h
rename to hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.mk b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
similarity index 100%
rename from hw/bsp/stm32h7/boards/waveshare_openh743i_2/board.mk
rename to hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 3e1ed9e84..ba3c3e954 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -80,6 +80,9 @@ void board_init(void)
   SysTick_Config(SystemCoreClock / 1000);
 
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent it is trigger before scheduler start
+  SysTick->CTRL &= ~1U;
+
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
diff --git a/hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld b/hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld
deleted file mode 100644
index 73d2dedb2..000000000
--- a/hw/bsp/waveshare_openh743i/STM32H743IITX_FLASH.ld
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
-******************************************************************************
-**
-**  File        : LinkerScript.ld
-**
-**  Author      : STM32CubeIDE
-**
-**  Abstract    : Linker script for STM32H7 series
-**                2048Kbytes FLASH and 192Kbytes RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-*****************************************************************************
-** @attention
-**
-** Copyright (c) 2019 STMicroelectronics.
-** All rights reserved.
-**
-** This software component is licensed by ST under BSD 3-Clause license,
-** the "License"; You may not use this file except in compliance with the
-** License. You may obtain a copy of the License at:
-**                        opensource.org/licenses/BSD-3-Clause
-**
-****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x2000 ;  /* required amount of heap  */
-_Min_Stack_Size = 0x2000 ; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 2048K
-  RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-  RAM_D1 (xrw)   : ORIGIN = 0x24000000, LENGTH = 512K
-  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K
-  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K
-  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data :
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-    *(.RamFunc)        /* .RamFunc sections */
-    *(.RamFunc*)       /* .RamFunc* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss secion */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/hw/bsp/waveshare_openh743i/board.c b/hw/bsp/waveshare_openh743i/board.c
deleted file mode 100644
index 4468c0668..000000000
--- a/hw/bsp/waveshare_openh743i/board.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019
- *    Benjamin Evans
- *    William D. Jones (thor0505@comcast.net),
- *    Ha Thach (tinyusb.org)
- *    Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "stm32h7xx_hal.h"
-#include "stm32h7xx_hal_tim.h"
-#include "bsp/board.h"
-
-
-/* ** BOARD SETUP **
- * 
- * NOTE: This board has bad signal integrity so you may experience some problems.
- * This setup assumes you have an openh743i-c Core and breakout board. For the HS
- * examples it also assumes you have a waveshare USB3300 breakout board plugged
- * into the ULPI PMOD header on the openh743i-c.
- * 
- * UART Debugging:
- * Due to pin conflicts in the HS configuration, this BSP uses USART3 (PD8, PD9).
- * As such, you won't be able to use the UART to USB converter on board and will
- * require an external UART to USB converter. You could use the waveshare FT232
- * USB UART Board (micro) but any 3.3V UART to USB converter will be fine.
- * 
- * Fullspeed:
- * If VBUS sense is enabled, ensure the PA9-VBUS jumper is connected on the core
- * board. Connect the PB6 jumper for the LED and the Wakeup - PA0 jumper for the
- * button. Connect the USB cable to the USB connector on the core board.
- * 
- * High Speed:
- * Remove all jumpers from the openh743i-c (especially the USART1 jumpers as the
- * pins conflict). Connect the PB6 jumper for the LED and the Wakeup - PA0
- * jumper for the button.
- * 
- * The reset pin on the ULPI PMOD port is not connected to the MCU. You'll need
- * to solder a wire from the RST pin on the USB3300 to a pin of your choosing on
- * the openh743i-c board (this example assumes you've used PD14 as specified with
- * the ULPI_RST_PORT and ULPI_RST_PIN defines below).
- * 
- * Preferably power the board using the external 5VDC jack. Connect the USB cable
- * to the USB connector on the ULPI board. Adjust delays in this file as required.
- * 
- * If you're having trouble, ask a question on the tinyUSB Github Discussion boards.
- * 
- * Have fun!
- *
-*/
-
-//--------------------------------------------------------------------+
-// BOARD DEFINES
-//--------------------------------------------------------------------+
-
-//LED Pin
-#define LED_PORT GPIOB
-#define LED_PIN GPIO_PIN_6
-#define LED_STATE_ON 1
-
-//ULPI PHY reset pin
-#define ULPI_RST_PORT GPIOD
-#define ULPI_RST_PIN GPIO_PIN_14
-
-// Tamper push-button
-#define BUTTON_PORT GPIOA
-#define BUTTON_PIN GPIO_PIN_0
-#define BUTTON_STATE_ACTIVE 1
-
-// Need external UART to USB converter as USART1 pins conflict with HS ULPI pins
-#define UART_DEV USART3
-#define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE
-#define UART_GPIO_PORT GPIOD
-#define UART_GPIO_AF GPIO_AF7_USART3
-#define UART_TX_PIN GPIO_PIN_8
-#define UART_RX_PIN GPIO_PIN_9
-
-// VBUS Sense detection
-#define OTG_FS_VBUS_SENSE 1
-#define OTG_HS_VBUS_SENSE 0
-
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-UART_HandleTypeDef uartHandle;
-TIM_HandleTypeDef tim2Handle;
-
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-
-// Despite being call USB2_OTG
-// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-// Despite being call USB2_OTG
-// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
-void OTG_HS_IRQHandler(void)
-{
-  tud_int_handler(1);
-}
-
-
-//--------------------------------------------------------------------+
-// RCC Clock
-//--------------------------------------------------------------------+
-static inline void board_stm32h7_clock_init(void)
-{
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  // Supply configuration update enable
-  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
-
-  // Configure the main internal regulator output voltage
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
-
-  while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY))
-  {
-  }
-  // Macro to configure the PLL clock source
-  __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
-
-  // Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure.
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = 2;
-  RCC_OscInitStruct.PLL.PLLN = 240;
-  RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLQ = 2;
-  RCC_OscInitStruct.PLL.PLLR = 2;
-  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
-  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
-  RCC_OscInitStruct.PLL.PLLFRACN = 0;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_USART3;
-  PeriphClkInitStruct.PLL3.PLL3M = 8;
-  PeriphClkInitStruct.PLL3.PLL3N = 336;
-  PeriphClkInitStruct.PLL3.PLL3P = 2;
-  PeriphClkInitStruct.PLL3.PLL3Q = 7;
-  PeriphClkInitStruct.PLL3.PLL3R = 2;
-  PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0;
-  PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
-  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
-  PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_PLL3;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  // Initializes the CPU, AHB and APB buses clocks
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
-  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
-
-  __HAL_RCC_CSI_ENABLE();
-
-  // Enable SYSCFG clock mondatory for I/O Compensation Cell
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-  // Enables the I/O Compensation Cell
-  HAL_EnableCompensationCell();
-
-  // Enable voltage detector
-  HAL_PWREx_EnableUSBVoltageDetector();
-
-  return;
-}
-
-
-//--------------------------------------------------------------------+
-// Timer implementation for board delay
-// This should be OS safe and doesn't require the scheduler to be running
-//--------------------------------------------------------------------+
-static void init_timer(void)
-{
-  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
-
-  __HAL_RCC_TIM2_CLK_ENABLE();
-
-  //Assuming timer clock is running at 260Mhz this should configure the timer counter to 1000Hz
-  tim2Handle.Instance = TIM2;
-  tim2Handle.Init.Prescaler = 60000U - 1U;
-  tim2Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
-  tim2Handle.Init.Period = 0xFFFFFFFFU;
-  tim2Handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV4;
-  tim2Handle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
-  HAL_TIM_Base_Init(&tim2Handle);
-
-  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
-  HAL_TIM_ConfigClockSource(&tim2Handle, &sClockSourceConfig);
-
-  //Start the timer
-  HAL_TIM_Base_Start(&tim2Handle);
-
-  return;
-}
-
-
-// Custom board delay implementation using timer ticks
-static inline void timer_board_delay(uint32_t ms)
-{
-  uint32_t startMs = __HAL_TIM_GET_COUNTER(&tim2Handle);
-  while ((__HAL_TIM_GET_COUNTER(&tim2Handle) - startMs) < ms)
-  {
-    asm("nop"); //do nothing
-  }
-}
-
-
-//Board initialisation
-void board_init(void)
-{
-  GPIO_InitTypeDef GPIO_InitStruct;
-
-  // Init clocks
-  board_stm32h7_clock_init();
-
-  // Init timer for delays
-  init_timer();
-
-  //Disable systick for now
-  //If using an RTOS and the systick interrupt fires without the scheduler running you might have an issue
-  //Because this init code now introduces delays, the systick should be disabled until after board init
-  SysTick->CTRL &= ~1U;
-
-  // Enable GPIO clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_GPIOH_CLK_ENABLE();
-  __HAL_RCC_GPIOI_CLK_ENABLE();
-
-  // Enable UART Clock
-  UART_CLK_EN();
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  // PHY RST Pin
-  GPIO_InitStruct.Pin = ULPI_RST_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  HAL_GPIO_Init(ULPI_RST_PORT, &GPIO_InitStruct);
-  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 0U);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // Uart
-  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
-
-  uartHandle.Instance = UART_DEV;
-  uartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
-  uartHandle.Init.WordLength = UART_WORDLENGTH_8B;
-  uartHandle.Init.StopBits = UART_STOPBITS_1;
-  uartHandle.Init.Parity = UART_PARITY_NONE;
-  uartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
-  uartHandle.Init.Mode = UART_MODE_TX_RX;
-  uartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
-  HAL_UART_Init(&uartHandle);
-
-#if BOARD_DEVICE_RHPORT_NUM == 0
-  //Full Speed
-
-  // Configure DM DP Pins
-  GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // This for ID line debug
-  GPIO_InitStruct.Pin = GPIO_PIN_10;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  __HAL_RCC_USB2_OTG_FS_CLK_ENABLE();
-
-#if OTG_FS_VBUS_SENSE
-  // Configure VBUS Pin
-  GPIO_InitStruct.Pin = GPIO_PIN_9;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-#else
-  // Disable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif // vbus sense
-
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  //High Speed
-
-  /**USB_OTG_HS GPIO Configuration
-    PC0     ------> USB_OTG_HS_ULPI_STP
-    PC2_C   ------> USB_OTG_HS_ULPI_DIR
-    PC3_C   ------> USB_OTG_HS_ULPI_NXT
-    PA3     ------> USB_OTG_HS_ULPI_D0
-    PA5     ------> USB_OTG_HS_ULPI_CK
-    PB1     ------> USB_OTG_HS_ULPI_D2
-    PB10    ------> USB_OTG_HS_ULPI_D3
-    PB11    ------> USB_OTG_HS_ULPI_D4
-    PB12    ------> USB_OTG_HS_ULPI_D5
-    PB13    ------> USB_OTG_HS_ULPI_D6
-    PB5     ------> USB_OTG_HS_ULPI_D7
-  */
-
-  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-  GPIO_InitStruct.Pin = GPIO_PIN_3 | GPIO_PIN_5;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_5;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG2_HS;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-  // Peripheral clock enable
-  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
-  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
-
-#if OTG_HS_VBUS_SENSE
-#error OTG HS VBUS Sense enabled is not implemented
-#else
-  // No VBUS sense
-  USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
-
-  // B-peripheral session valid override enable
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
-  USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
-#endif
-
-  // Force device mode
-  USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
-  USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
-
-  //Reset the PHY - Change the delays as you see fit
-  timer_board_delay(5U); //Delay 5ms
-  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 1U);
-  timer_board_delay(20U); //Delay 20ms
-  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 0U);
-  timer_board_delay(20U); //Delay 20ms
-
-#endif // rhport = 1
-
-  //Disable the timer used for delays
-  HAL_TIM_Base_Stop(&tim2Handle);
-  __HAL_RCC_TIM2_CLK_DISABLE();
-
-  // Configure systick 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-
-  //Enable systick
-  SysTick->CTRL |= ~1U;
-
-  return;
-}
-
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
-}
-
-
-uint32_t board_button_read(void)
-{
-  return (BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN)) ? 1 : 0;
-}
-
-
-int board_uart_read(uint8_t *buf, int len)
-{
-  (void)buf;
-  (void)len;
-  return 0;
-}
-
-
-int board_uart_write(void const *buf, int len)
-{
-  HAL_UART_Transmit(&uartHandle, (uint8_t *)buf, len, 0xffff);
-  return len;
-}
-
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-
-void HardFault_Handler(void)
-{
-  asm("bkpt");
-}
-
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-}
\ No newline at end of file
diff --git a/hw/bsp/waveshare_openh743i/board.mk b/hw/bsp/waveshare_openh743i/board.mk
deleted file mode 100644
index 721df1bdf..000000000
--- a/hw/bsp/waveshare_openh743i/board.mk
+++ /dev/null
@@ -1,64 +0,0 @@
-UF2_FAMILY_ID = 0x6db66082
-ST_FAMILY = h7
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-# Default is HS port
-PORT ?= 1
-
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-LD_FILE = $(BOARD_PATH)/STM32H743IITX_FLASH.ld
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32H7 \
-	-DBOARD_DEVICE_RHPORT_NUM=$(PORT) \
-  -DSTM32H743xx \
-  -DHSE_VALUE=8000000
-
-ifeq ($(PORT), 1)
-  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
-  $(info "PORT1 High Speed")
-else
-  $(info "PORT0 Full Speed")
-endif
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
-
-# All source paths should be relative to the top level.
-SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
-	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim_ex.c
-
-INC += \
-	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
-
-# For flash-jlink target
-JLINK_DEVICE = stm32h743ii
-
-# flash target using jlink
-flash: flash-jlink
\ No newline at end of file
diff --git a/hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h b/hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h
deleted file mode 100644
index 11d29ed6f..000000000
--- a/hw/bsp/waveshare_openh743i/stm32h7xx_hal_conf.h
+++ /dev/null
@@ -1,483 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32h7xx_hal_conf_template.h
-  * @brief   HAL configuration template file. 
-  *          This file should be copied to the application folder and renamed
-  *          to stm32h7xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32H7xx_HAL_CONF_H
-#define __STM32H7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-/* #define HAL_CEC_MODULE_ENABLED */
-/* #define HAL_COMP_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-/* #define HAL_DCMI_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-/* #define HAL_EXTI_MODULE_ENABLED */
-/* #define HAL_FDCAN_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_HASH_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_HRTIM_MODULE_ENABLED */
-/* #define HAL_HSEM_MODULE_ENABLED */
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-/* #define HAL_MDMA_MODULE_ENABLED */
-/* #define HAL_MMC_MODULE_ENABLED */
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_OPAMP_MODULE_ENABLED */
-/* #define HAL_PCD_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED */
-/* #define HAL_RAMECC_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED */
-/* #define HAL_SD_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-#define HAL_SPI_MODULE_ENABLED
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SWPMI_MODULE_ENABLED */
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-//#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#error HSE_VALUE is not defined
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal  oscillator (CSI) default value.
-  *        This value is the default CSI value after Reset.
-  */
-#if !defined  (CSI_VALUE)
-  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* CSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-#if !defined  (LSI_VALUE)
-  #define LSI_VALUE  ((uint32_t)32000)      /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                              The real value may vary depending on the variations
-                                              in voltage and temperature.*/
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  USE_SD_TRANSCEIVER           1U               /*!< use uSD Transceiver */
-#define  USE_SPI_CRC                  1U               /*!< use CRC in SPI */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################### Ethernet Configuration ######################### */
-#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
-#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
-
-#define ETH_MAC_ADDR0    ((uint8_t)0x02)
-#define ETH_MAC_ADDR1    ((uint8_t)0x00)
-#define ETH_MAC_ADDR2    ((uint8_t)0x00)
-#define ETH_MAC_ADDR3    ((uint8_t)0x00)
-#define ETH_MAC_ADDR4    ((uint8_t)0x00)
-#define ETH_MAC_ADDR5    ((uint8_t)0x00)
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32h7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32h7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32h7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_MDMA_MODULE_ENABLED
- #include "stm32h7xx_hal_mdma.h"
-#endif /* HAL_MDMA_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
-  #include "stm32h7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32h7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32h7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
-  #include "stm32h7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
-  #include "stm32h7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32h7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32h7xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32h7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32h7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_FDCAN_MODULE_ENABLED
-  #include "stm32h7xx_hal_fdcan.h"
-#endif /* HAL_FDCAN_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32h7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32h7xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32h7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32h7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32h7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32h7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_HRTIM_MODULE_ENABLED
-  #include "stm32h7xx_hal_hrtim.h"
-#endif /* HAL_HRTIM_MODULE_ENABLED */
-
-#ifdef HAL_HSEM_MODULE_ENABLED
-  #include "stm32h7xx_hal_hsem.h"
-#endif /* HAL_HSEM_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32h7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32h7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32h7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32h7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32h7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32h7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32h7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32h7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32h7xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32h7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
-#include "stm32h7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-#include "stm32h7xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32h7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32h7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RAMECC_MODULE_ENABLED
- #include "stm32h7xx_hal_ramecc.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32h7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32h7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32h7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32h7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
- #include "stm32h7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32h7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32h7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SWPMI_MODULE_ENABLED
- #include "stm32h7xx_hal_swpmi.h"
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32h7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32h7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32h7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32h7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32h7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32h7xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32h7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32h7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32h7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t *file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32H7xx_HAL_CONF_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

From 61592526928be9626317ef82bbe42d0edaf7fa14 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 29 Aug 2021 21:34:10 +0700
Subject: [PATCH 0404/2085] disable systick when running freertos on other stm
 families

---
 hw/bsp/stm32f0/family.c |  6 +++++-
 hw/bsp/stm32f4/family.c |  3 +++
 hw/bsp/stm32f7/family.c | 10 +++++++++-
 hw/bsp/stm32h7/family.c |  3 +--
 4 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index b2e0453c5..351a7c8c6 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -55,10 +55,14 @@ void board_init(void)
   // Enable UART Clock
   UART_CLK_EN();
 
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index 4a0dbcb11..cf0cb2b08 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -50,6 +50,9 @@ void board_init(void)
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index c0d324598..2eb737ee3 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -70,9 +70,17 @@ void board_init(void)
 
   UART_CLK_EN();
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
+
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
   GPIO_InitTypeDef  GPIO_InitStruct;
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index ba3c3e954..a2116d0bd 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -80,13 +80,12 @@ void board_init(void)
   SysTick_Config(SystemCoreClock / 1000);
 
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // Explicitly disable systick to prevent it is trigger before scheduler start
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
   SysTick->CTRL &= ~1U;
 
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-
 #endif
   
   GPIO_InitTypeDef  GPIO_InitStruct;

From 90af8562b1e361c213d70242fc3ae5883e54f33a Mon Sep 17 00:00:00 2001
From: mainr <rmain.mws@gmail.com>
Date: Wed, 25 Aug 2021 12:05:35 -0400
Subject: [PATCH 0405/2085] Added support for Microchip Curiosity Nano SAMD21
 board (DM320119)

Added support for Microchip Curiosity Nano SAMD21 board (DM320119) under hw/bsp/samd21/boards/curiosity_nano
The nEDBG on this board requires dap_protocol be specified as SWD (changed in examples/rules.mk)

NOTE: requires entry (03eb:2175) for VID:PID of nEDBG be added to /etc/udev/rules for pyocd
---
 examples/rules.mk                             |   2 +-
 hw/bsp/samd21/boards/curiosity_nano/board.h   |  50 ++++++
 hw/bsp/samd21/boards/curiosity_nano/board.mk  |  13 ++
 .../boards/curiosity_nano/samd21g17a_flash.ld | 144 ++++++++++++++++++
 4 files changed, 208 insertions(+), 1 deletion(-)
 create mode 100644 hw/bsp/samd21/boards/curiosity_nano/board.h
 create mode 100644 hw/bsp/samd21/boards/curiosity_nano/board.mk
 create mode 100644 hw/bsp/samd21/boards/curiosity_nano/samd21g17a_flash.ld

diff --git a/examples/rules.mk b/examples/rules.mk
index 4fce468fd..4bad747da 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -170,7 +170,7 @@ flash-stlink: $(BUILD)/$(PROJECT).elf
 
 # flash with pyocd
 flash-pyocd: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t $(PYOCD_TARGET) $<
+	pyocd flash -t $(PYOCD_TARGET) -O dap_protocol=swd $<
 	pyocd reset -t $(PYOCD_TARGET)
 
 # flash with Black Magic Probe
diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.h b/hw/bsp/samd21/boards/curiosity_nano/board.h
new file mode 100644
index 000000000..67924d809
--- /dev/null
+++ b/hw/bsp/samd21/boards/curiosity_nano/board.h
@@ -0,0 +1,50 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PIN               (32 + 10) // PB10
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PIN            (0  + 11) // PB11
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_RX_PIN           31	// CDC5_RX
+#define UART_TX_PIN           37	// CDC5_TX
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.mk b/hw/bsp/samd21/boards/curiosity_nano/board.mk
new file mode 100644
index 000000000..05257e88c
--- /dev/null
+++ b/hw/bsp/samd21/boards/curiosity_nano/board.mk
@@ -0,0 +1,13 @@
+CFLAGS += -D__SAMD21G17A__
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/samd21g17a_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = atsamd21g17a
+
+# flash using jlink (options are: jlink/cmsisdap/stlink/dfu)
+#flash: flash-jlink
+
+PYOCD_TARGET = atsamd21g17a
+flash: flash-pyocd
diff --git a/hw/bsp/samd21/boards/curiosity_nano/samd21g17a_flash.ld b/hw/bsp/samd21/boards/curiosity_nano/samd21g17a_flash.ld
new file mode 100644
index 000000000..153f0cbb9
--- /dev/null
+++ b/hw/bsp/samd21/boards/curiosity_nano/samd21g17a_flash.ld
@@ -0,0 +1,144 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G17A/D
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+        end = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}

From b169db3fd6359a127ba92d4bd5cd48a3a5286fd7 Mon Sep 17 00:00:00 2001
From: mainr <rmain.mws@gmail.com>
Date: Thu, 26 Aug 2021 07:46:23 -0400
Subject: [PATCH 0406/2085] Add PYOCD_OPTION

Added PYOCD_OPTION to pass board-specific options to build
---
 examples/rules.mk                            | 2 +-
 hw/bsp/samd21/boards/curiosity_nano/board.mk | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/examples/rules.mk b/examples/rules.mk
index 4bad747da..4af2f2be4 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -170,7 +170,7 @@ flash-stlink: $(BUILD)/$(PROJECT).elf
 
 # flash with pyocd
 flash-pyocd: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t $(PYOCD_TARGET) -O dap_protocol=swd $<
+	pyocd flash -t $(PYOCD_TARGET) $(PYOCD_OPTION) $<
 	pyocd reset -t $(PYOCD_TARGET)
 
 # flash with Black Magic Probe
diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.mk b/hw/bsp/samd21/boards/curiosity_nano/board.mk
index 05257e88c..767788b86 100644
--- a/hw/bsp/samd21/boards/curiosity_nano/board.mk
+++ b/hw/bsp/samd21/boards/curiosity_nano/board.mk
@@ -10,4 +10,5 @@ JLINK_DEVICE = atsamd21g17a
 #flash: flash-jlink
 
 PYOCD_TARGET = atsamd21g17a
+PYOCD_OPTION = -O dap_protocol=swd
 flash: flash-pyocd

From a05ea0d83b6c59316751e546dfec3ee4e2a286e1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 29 Aug 2021 22:51:05 +0700
Subject: [PATCH 0407/2085] add CFG_EXAMPLE_MSC_READONLY for curiosity

allow family/board to exclude specific example. exclude
net_lwip_webserver from curiosity.
---
 examples/rules.mk                               |  1 +
 .../.skip.device.net_lwip_webserver             |  0
 hw/bsp/samd21/boards/curiosity_nano/board.mk    |  2 +-
 tools/build_family.py                           | 17 ++++++++++++-----
 4 files changed, 14 insertions(+), 6 deletions(-)
 create mode 100644 hw/bsp/samd21/boards/curiosity_nano/.skip.device.net_lwip_webserver

diff --git a/examples/rules.mk b/examples/rules.mk
index 4af2f2be4..861973284 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -169,6 +169,7 @@ flash-stlink: $(BUILD)/$(PROJECT).elf
 	STM32_Programmer_CLI --connect port=swd --write $< --go
 
 # flash with pyocd
+PYOCD_OPTION ?=
 flash-pyocd: $(BUILD)/$(PROJECT).hex
 	pyocd flash -t $(PYOCD_TARGET) $(PYOCD_OPTION) $<
 	pyocd reset -t $(PYOCD_TARGET)
diff --git a/hw/bsp/samd21/boards/curiosity_nano/.skip.device.net_lwip_webserver b/hw/bsp/samd21/boards/curiosity_nano/.skip.device.net_lwip_webserver
new file mode 100644
index 000000000..e69de29bb
diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.mk b/hw/bsp/samd21/boards/curiosity_nano/board.mk
index 767788b86..ec3217f89 100644
--- a/hw/bsp/samd21/boards/curiosity_nano/board.mk
+++ b/hw/bsp/samd21/boards/curiosity_nano/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G17A__
+CFLAGS += -D__SAMD21G17A__ -DCFG_EXAMPLE_MSC_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/samd21g17a_flash.ld
diff --git a/tools/build_family.py b/tools/build_family.py
index c46781904..4195c259b 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -98,21 +98,28 @@ def build_size(example, board):
 def skip_example(example, board):
     ex_dir = 'examples/' + example
     
+    # Check if example is skipped by family or board directory
+    skip_file = ".skip." + example.replace('/', '.');
+    if os.path.isfile("hw/bsp/{}/{}".format(family, skip_file)) or os.path.isfile("hw/bsp/{}/boards/{}/{}".format(family, board, skip_file)):
+        return 1
+
+    # Otherwise check if mcu is excluded by example directory
+
     # family CMake
-    board_mk = 'hw/bsp/{}/family.cmake'.format(family)
+    family_mk = 'hw/bsp/{}/family.cmake'.format(family)
 
     # family.mk
-    if not os.path.exists(board_mk):
-        board_mk = 'hw/bsp/{}/family.mk'.format(family)
+    if not os.path.exists(family_mk):
+        family_mk = 'hw/bsp/{}/family.mk'.format(family)
 
-    with open(board_mk) as mk:
+    with open(family_mk) as mk:
         mk_contents = mk.read()
 
         # Skip all OPT_MCU_NONE these are WIP port
         if 'CFG_TUSB_MCU=OPT_MCU_NONE' in mk_contents:
             return 1
 
-        # Skip if CFG_TUSB_MCU in board.mk to match skip file
+        # Skip if CFG_TUSB_MCU in family.mk to match skip file
         for skip_file in glob.iglob(ex_dir + '/.skip.MCU_*'):
             mcu_cflag = 'CFG_TUSB_MCU=OPT_' + os.path.basename(skip_file).split('.')[2]
             if mcu_cflag in mk_contents:

From 6fadf530e07d99010bc15e6a16402b63fd4af596 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Aug 2021 12:44:38 +0700
Subject: [PATCH 0408/2085] increase version and update changelog

---
 README.rst              |   4 +-
 docs/info/changelog.rst | 715 ++++++++++++++++++++++------------------
 repository.yml          |   5 +-
 src/tusb_option.h       |   4 +-
 4 files changed, 404 insertions(+), 324 deletions(-)

diff --git a/README.rst b/README.rst
index 9a41e3ff1..52738da32 100644
--- a/README.rst
+++ b/README.rst
@@ -40,14 +40,14 @@ The stack supports the following MCUs:
 - **NXP:**
 
   - iMX RT Series: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
-  - Kinetis: KL25
+  - Kinetis: KL25, K32L2Bxx
   - LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
 
 - **Raspberry Pi:** RP2040
 - **Renesas:** RX63N, RX65N
 - **Silabs:** EFM32GG12
 - **Sony:** CXD56
-- **ST:** STM32 series: L0, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
+- **ST:** STM32 series: L0, L1, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
 - **TI:** MSP430
 - **ValentyUSB:** eptri
 
diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index 80205a721..b28ddcc54 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -2,91 +2,193 @@
 Changelog
 *********
 
-0.10.1 (03-06-221)
+0.11.0 (29-08-2021)
 ===================
 
--  rework rp2040 examples and CMake build, allow better integration with pico-sdk
-
-Host Controller Driver (HCD)
-----------------------------
-
--  Fix rp2040 host driver: incorrect PID with low speed device with max packet size of 8 bytes
--  Improve hub driver
--  Remove obsolete hcd_pipe_queue_xfer()/hcd_pipe_xfer()
--  Use hcd_frame_number() instead of micro frame
--  Fix OHCI endpoint address and xferred_bytes in xfer complete event
-
-
-0.10.0 (28-05-2021)
-===================
-
--  Rework tu_fifo_t with separated mutex for read and write, better support DMA with read/write buffer info. And constant address mode
--  Improve audio_test example and add audio_4_channel_mic example
--  Add new dfu example
--  Remove pico-sdk from submodule
+- Add host/hid_controller example: only worked/tested with Sony PS4 DualShock controller
+- Add device/hid_boot_interface example
+- Add support for Renesas CCRX toolchain for RX mcu
 
 Device Controller Driver (DCD)
 ------------------------------
 
--  Add new DCD port for Silabs EFM32GG12 with board Thunderboard Kit (SLTB009A)
--  Add new DCD port Renesas RX63N, board GR-CITRUS
--  Add new (optional) endpoint API dcd_edpt_xfer_fifo
--  Fix build with nRF5340
--  Fix build with lpc15 and lpc54
--  Fix build with lpc177x_8x
--  STM32 Synopsys: greatly improve Isochronous transfer with edpt_xfer_fifo API
--  Support LPC55 port1 highspeed
--  Add support for Espressif esp32s3
--  nRF: fix race condition that could cause drop packet of Bulk OUT transfer
+- Add new DCD port for SAMx7x (E70, S70, V70, V71)
+- Add new mcu K32L2Bxx
+- Add new mcu GD32VF103
+- Add new mcu STM32l151
+- Add new mcu SAML21
+- Add new mcu RX65n RX72n
+- Fix NUC120/121/126 USBRAM can only be accessed in byte manner. Also improve set_address & disable sof
+- Add Suspend/Resume handling for Renesas RX family.
+- Fix DA1469x no VBUS startup
+
+Synopsys
+^^^^^^^^
+
+- Fix Synopsys set address bug which could cause re-enumeration failed
+- Fix for dcd_synopsys driver integer overflow in HS mode (issue #968)
+
+nRF5x
+^^^^^
+
+- Add nRF5x suspend, resume and remote wakeup
+- Fix nRF5x race condition with TASKS_EP0RCVOUT
+
+RP2040
+^^^^^^
+
+- Add RP2040 suspend & resume support
+- Implement double buffer for both host and device (#891). Howver device EPOUT is still single bufferred due to techinical issue with short packet 
+
+Host Controller Driver (HCD)
+----------------------------
+
+RP2040
+^^^^^^
+
+- Implement double bufferred to fix E4 errata and boost performance
+- Lots of rp2040 update and enhancment
+
+Device Stack
+------------
+
+USBD
+^^^^
+
+- Better support big endian mcu
+- Add tuh_inited() and tud_inited(), will separte tusb_init/inited() to tud/tuh init/inited
+- Add dcd_attr.h for defining common controller attribute such as max endpoints
+
+Bluetooth
+^^^^^^^^^
+
+- Fix stridx error in descriptor template
+
+DFU
+^^^
+
+- Enhance DFU implementation to support multiple alternate interface and better support bwPollTimeout
+- Rename CFG_TUD_DFU_MODE to simply CFG_TUD_DFU 
+
+HID
+^^^
+
+- Fix newline usage keyboard (ENTER 0x28)
+- Better support Hid Get/Set report
+- Change max gamepad support from 16 to 32 buttons
+
+MIDI
+^^^^
+
+- Fix midi available
+- Fix midi data
+- Fix an issue when calling midi API when not enumerated yet
+
+UAC2
+^^^^
+
+- Fix bug and enhance of UAC2
+ 
+Vendor
+^^^^^^
+
+- Fix vendor fifo deadlock in certain case
+- Add tud_vendor_n_read_flush
+
+Host Stack
+----------
+
+- Major update and rework most of host stack, still needs more improvement
+- Lots of improvement and update in parsing configuration and control
+- Rework and major update to HID driver. Will default to enable boot interface if available
+- Sepearate CFG_TUH_DEVICE_MAX and CFG_TUH_HUB for better management and reduce SRAM usage
+
+0.10.1 (03-06-2021)
+===================
+
+- rework rp2040 examples and CMake build, allow better integration with pico-sdk
+
+Host Controller Driver (HCD)
+----------------------------
+
+- Fix rp2040 host driver: incorrect PID with low speed device with max packet size of 8 bytes
+- Improve hub driver
+- Remove obsolete hcd_pipe_queue_xfer()/hcd_pipe_xfer()
+- Use hcd_frame_number() instead of micro frame
+- Fix OHCI endpoint address and xferred_bytes in xfer complete event
+
+0.10.0 (28-05-2021)
+===================
+
+- Rework tu_fifo_t with separated mutex for read and write, better support DMA with read/write buffer info. And constant address mode
+- Improve audio_test example and add audio_4_channel_mic example
+- Add new dfu example
+- Remove pico-sdk from submodule
+
+Device Controller Driver (DCD)
+------------------------------
+
+- Add new DCD port for Silabs EFM32GG12 with board Thunderboard Kit (SLTB009A)
+- Add new DCD port Renesas RX63N, board GR-CITRUS
+- Add new (optional) endpoint API dcd_edpt_xfer_fifo
+- Fix build with nRF5340
+- Fix build with lpc15 and lpc54
+- Fix build with lpc177x_8x
+- STM32 Synopsys: greatly improve Isochronous transfer with edpt_xfer_fifo API
+- Support LPC55 port1 highspeed
+- Add support for Espressif esp32s3
+- nRF: fix race condition that could cause drop packet of Bulk OUT transfer
 
 USB Device Driver (USBD)
 ------------------------
 
--  Add new (optional) endpoint ADPI usbd_edpt_xfer_fifo
+- Add new (optional) endpoint ADPI usbd_edpt_xfer_fifo
 
 Device Class Driver
 -------------------
 
 CDC
 
--  [Breaking] tud_cdc_peek(), tud_vendor_peek() no longer support random offset and dropped position parameter.
+- [Breaking] tud_cdc_peek(), tud_vendor_peek() no longer support random offset and dropped position parameter.
 
 DFU
 
--  Add new DFU 1.1 class driver (WIP)
+- Add new DFU 1.1 class driver (WIP)
 
 HID
 
--  Fix keyboard report descriptor template
--  Add more hid keys constant from 0x6B to 0xA4
--  [Breaking] rename API
-   -  HID_PROTOCOL_NONE/KEYBOARD/MOUST to HID_ITF_PROTOCOL_NONE/KEYBOARD/MOUSE
-   -  tud_hid_boot_mode() to tud_hid_get_protocol()
-   -  tud_hid_boot_mode_cb() to tud_hid_set_protocol_cb()
+- Fix keyboard report descriptor template
+- Add more hid keys constant from 0x6B to 0xA4
+
+- [Breaking] rename API
+  - HID_PROTOCOL_NONE/KEYBOARD/MOUST to HID_ITF_PROTOCOL_NONE/KEYBOARD/MOUSE
+  - tud_hid_boot_mode() to tud_hid_get_protocol()
+  - tud_hid_boot_mode_cb() to tud_hid_set_protocol_cb()
 
 MIDI
 
--  Fix MIDI buffer overflow issue
--  [Breaking] rename API
-   -  Rename tud_midi_read() to tud_midi_stream_read()
-   -  Rename tud_midi_write() to tud_midi_stream_write()
-   -  Rename tud_midi_receive() to tud_midi_packet_read()
-   -  Rename tud_midi_send() to tud_midi_packet_write()
+- Fix MIDI buffer overflow issue
+
+- [Breaking] rename API
+  - Rename tud_midi_read() to tud_midi_stream_read()
+  - Rename tud_midi_write() to tud_midi_stream_write()
+  - Rename tud_midi_receive() to tud_midi_packet_read()
+  - Rename tud_midi_send() to tud_midi_packet_write()
 
 Host Controller Driver (HCD)
 ----------------------------
 
--  No noticable changes
+- No noticable changes
 
 USB Host Driver (USBH)
 ----------------------
 
--  No noticable changes
+- No noticable changes
 
 Host Class Driver
 -----------------
 
--  HID: Rework host hid driver, basically everything changes
+- HID: Rework host hid driver, basically everything changes
 
 
 0.9.0 (12-03-2021)
@@ -100,59 +202,62 @@ Device Controller Driver (DCD)
 
 RP2040
 
--  Fix endpoint buffer reallocation overrun problem
--  Fix osal_pico queue overflow in initialization
--  Fix Isochronous endpoint buffer size in transfer
--  Optimize hardware endpoint struct to reduce RAM usage
--  Fix enum walkaround forever check for SE0 when pull up is disabled
+- Fix endpoint buffer reallocation overrun problem
+- Fix osal_pico queue overflow in initialization
+- Fix Isochronous endpoint buffer size in transfer
+- Optimize hardware endpoint struct to reduce RAM usage
+- Fix enum walkaround forever check for SE0 when pull up is disabled
 
 Sony CXD56
 
--  Pass the correct speed on Spresense
--  Fix setup processed flag
+- Pass the correct speed on Spresense
+- Fix setup processed flag
 
 NXP Transdimention
 
--  Update dcd_init() to reset controller to device mode
+- Update dcd_init() to reset controller to device mode
 
 USB Device Driver (USBD)
 ^^^^^^^^^^^^^^^^^^^^^^^^
 
--  Fix issue with status zlp (tud_control_status) is returned by class driver with SET/CLEAR_FEATURE for endpoint.
--  Correct endpoint size check for fullspeed bulk, can be 8, 16, 32, 64
--  Ack SET_INTERFACE even if it is not implemented by class driver.
+- Fix issue with status zlp (tud_control_status) is returned by class driver with SET/CLEAR_FEATURE for endpoint.
+- Correct endpoint size check for fullspeed bulk, can be 8, 16, 32, 64
+- Ack SET_INTERFACE even if it is not implemented by class driver.
 
 Device Class Driver
 ^^^^^^^^^^^^^^^^^^^
 
 DFU Runtime
 
--  rename dfu_rt to dfu_runtime for easy reading
+- rename dfu_rt to dfu_runtime for easy reading
 
 CDC
 
--  Add tud_cdc_send_break_cb() to support break request
--  Improve CDC receive, minor behavior changes: when tud_cdc_rx_wanted_cb() is invoked wanted_char may not be the last byte in the fifo
+- Add tud_cdc_send_break_cb() to support break request
+- Improve CDC receive, minor behavior changes: when tud_cdc_rx_wanted_cb() is invoked wanted_char may not be the last byte in the fifo
 
 HID
 
--  [Breaking] Add itf argument to hid API to support multiple instances, follow API has signature changes
-   -  tud_hid_descriptor_report_cb()
-   -  tud_hid_get_report_cb()
-   -  tud_hid_set_report_cb()
-   -  tud_hid_boot_mode_cb()
-   -  tud_hid_set_idle_cb()
--  Add report complete callback tud_hid_report_complete_cb() API
--  Add DPad/Hat support for HID Gamepad
-   -  `TUD_HID_REPORT_DESC_GAMEPAD()` now support 16 buttons, 2 joysticks, 1 hat/dpad
-   -  Add hid_gamepad_report_t along with `GAMEPAD_BUTTON_` and `GAMEPAD_HAT_` enum
-   -  Add Gamepad to hid_composite / hid_composite_freertos example
+- [Breaking] Add itf argument to hid API to support multiple instances, follow API has signature changes
+
+  - tud_hid_descriptor_report_cb()
+  - tud_hid_get_report_cb()
+  - tud_hid_set_report_cb()
+  - tud_hid_boot_mode_cb()
+  - tud_hid_set_idle_cb()
+
+- Add report complete callback tud_hid_report_complete_cb() API
+- Add DPad/Hat support for HID Gamepad
+
+  - `TUD_HID_REPORT_DESC_GAMEPAD()` now support 16 buttons, 2 joysticks, 1 hat/dpad
+  - Add hid_gamepad_report_t along with `GAMEPAD_BUTTON_` and `GAMEPAD_HAT_` enum
+  - Add Gamepad to hid_composite / hid_composite_freertos example
 
 MIDI
 
--  Fix dropping MIDI sysex message when fifo is full
--  Fix typo in tud_midi_write24(), make example less ambigous for cable and channel
--  Fix incorrect endpoint descriptor length, MIDI v1 use Audio v1 which has 9-byte endpoint descriptor (instead of 7)
+- Fix dropping MIDI sysex message when fifo is full
+- Fix typo in tud_midi_write24(), make example less ambigous for cable and channel
+- Fix incorrect endpoint descriptor length, MIDI v1 use Audio v1 which has 9-byte endpoint descriptor (instead of 7)
 
 Host Stack
 ----------
@@ -160,45 +265,48 @@ Host Stack
 Host Controller Driver (HCD)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
--  Add rhport to hcd_init()
--  Improve EHCI/OHCI driver abstraction
-   -  Move echi/ohci files to portable/
-   -  Rename hcd_lpc18_43 to hcd_transdimension
-   -  Sub hcd API with hcd_ehci_init(), hcd_ehci_register_addr()
--  Update NXP transdimention hcd_init() to reset controller to host mode
-   -  Ported hcd to rt10xx
+- Add rhport to hcd_init()
+- Improve EHCI/OHCI driver abstraction
+
+  - Move echi/ohci files to portable/
+  - Rename hcd_lpc18_43 to hcd_transdimension
+  - Sub hcd API with hcd_ehci_init(), hcd_ehci_register_addr()
+  
+- Update NXP transdimention hcd_init() to reset controller to host mode
+
+  - Ported hcd to rt10xx
 
 USB Host Driver (USBH)
 ^^^^^^^^^^^^^^^^^^^^^^
 
--  No noticeable changes to usbh
+- No noticeable changes to usbh
 
 Host Class Driver
 ^^^^^^^^^^^^^^^^^
 
 MSC
 
--  Rename tuh_msc_scsi_inquiry() to tuh_msc_inquiry()
--  Rename tuh_msc_mounted_cb/tuh_msc_unmounted_cb to tuh_msc_mount_cb/tuh_msc_unmount_cb to match device stack naming
--  Change tuh_msc_is_busy() to tuh_msc_ready()
--  Add read10 and write10 function: tuh_msc_read10(), tuh_msc_write10()
--  Read_Capacity is invoked as part of enumeration process
--  Add tuh_msc_get_block_count(), tuh_msc_get_block_size()
--  Add CFG_TUH_MSC_MAXLUN (default to 4) to hold lun capacities
+- Rename tuh_msc_scsi_inquiry() to tuh_msc_inquiry()
+- Rename tuh_msc_mounted_cb/tuh_msc_unmounted_cb to tuh_msc_mount_cb/tuh_msc_unmount_cb to match device stack naming
+- Change tuh_msc_is_busy() to tuh_msc_ready()
+- Add read10 and write10 function: tuh_msc_read10(), tuh_msc_write10()
+- Read_Capacity is invoked as part of enumeration process
+- Add tuh_msc_get_block_count(), tuh_msc_get_block_size()
+- Add CFG_TUH_MSC_MAXLUN (default to 4) to hold lun capacities
 
 Others
 ------
 
--  Add basic support for rt-thread OS
--  Change zero bitfield length to more explicit padding
--  Build example now fetch required submodules on the fly while running `make` without prio submodule init for mcu drivers
--  Update pico-sdk to v1.1.0
+- Add basic support for rt-thread OS
+- Change zero bitfield length to more explicit padding
+- Build example now fetch required submodules on the fly while running `make` without prio submodule init for mcu drivers
+- Update pico-sdk to v1.1.0
 
 **New Boards**
 
--  Microchip SAM E54 Xplained Pro
--  LPCXpresso 55s28
--  LPCXpresso 18s37
+- Microchip SAM E54 Xplained Pro
+- LPCXpresso 55s28
+- LPCXpresso 18s37
 
 
 0.8.0 (05-02-2021)
@@ -207,47 +315,55 @@ Others
 Device Controller Driver
 ------------------------
 
--  Added new device support for Raspberry Pi RP2040
--  Added new device support for NXP Kinetis KL25ZXX
--  Use dcd_event_bus_reset() with link speed to replace bus_signal
--  ESP32-S2:
-   -  Add bus suspend and wakeup support
--  SAMD21:
-   -  Fix (walkaround) samd21 setup_packet overflow by USB DMA
--  STM32 Synopsys:
-   -  Rework USB FIFO allocation scheme and allow RX FIFO size reduction
--  Sony CXD56
-   -  Update Update Spresense SDK to 2.0.2
-   -  Fix dcd issues with setup packets
-   -  Correct EP number for cdc_msc example
+- Added new device support for Raspberry Pi RP2040
+- Added new device support for NXP Kinetis KL25ZXX
+- Use dcd_event_bus_reset() with link speed to replace bus_signal
+
+- ESP32-S2:
+  - Add bus suspend and wakeup support
+  
+- SAMD21:
+  - Fix (walkaround) samd21 setup_packet overflow by USB DMA
+  
+- STM32 Synopsys:
+  - Rework USB FIFO allocation scheme and allow RX FIFO size reduction
+  
+- Sony CXD56
+  - Update Update Spresense SDK to 2.0.2
+  - Fix dcd issues with setup packets
+  - Correct EP number for cdc_msc example
 
 USB Device
 ----------
 
 **USBD**
 
--  Rework usbd control transfer to have additional stage parameter for setup, data, status
--  Fix tusb_init() return true instead of TUSB_ERROR_NONE
--  Added new API tud_connected() that return true after device got out of bus reset and received the very first setup packet
+- Rework usbd control transfer to have additional stage parameter for setup, data, status
+- Fix tusb_init() return true instead of TUSB_ERROR_NONE
+- Added new API tud_connected() that return true after device got out of bus reset and received the very first setup packet
 
 **Class Driver**
 
--  CDC
-   -  Allow to transmit data, even if the host does not support control line states i.e set DTR
--  HID
-   -  change default CFG_TUD_HID_EP_BUFSIZE from 16 to 64
--  MIDI
-   -  Fix midi sysex sending bug
--  MSC
-   -  Invoke only scsi complete callback after status transaction is complete.
-   -  Fix scsi_mode_sense6_t padding, which cause IAR compiler internal error.
--  USBTMC
-   -  Change interrupt endpoint example size to 8 instead of 2 for better compatibility with mcu
+- CDC
+  - Allow to transmit data, even if the host does not support control line states i.e set DTR
+  
+- HID
+  - change default CFG_TUD_HID_EP_BUFSIZE from 16 to 64
+  
+- MIDI
+  - Fix midi sysex sending bug
+  
+- MSC
+  - Invoke only scsi complete callback after status transaction is complete.
+  - Fix scsi_mode_sense6_t padding, which cause IAR compiler internal error.
+  
+- USBTMC
+  - Change interrupt endpoint example size to 8 instead of 2 for better compatibility with mcu
 
 **Example**
 
--  Support make from windows cmd.exe
--  Add HID Consumer Control (media keys) to hid_composite & hid_composite_freertos examples
+- Support make from windows cmd.exe
+- Add HID Consumer Control (media keys) to hid_composite & hid_composite_freertos examples
 
 
 USB Host
@@ -258,18 +374,18 @@ No noticeable changes to host stack
 New Boards
 ----------
 
--  NXP/Freescale Freedom FRDM-KL25Z
--  Feather Double M33 express
--  Raspberry Pi Pico
--  Adafruit Feather RP2040
--  Adafruit Itsy Bitsy RP2040
--  Adafruit QT RP2040
--  Adfruit Feather ESP32-S2
--  Adafruit Magtag 29" Eink
--  Adafruit Metro ESP32-S2
--  Adafruit PyBadge
--  Adafruit PyPortal
--  Great Scott Gadgets' LUNA D11 & D21
+- NXP/Freescale Freedom FRDM-KL25Z
+- Feather Double M33 express
+- Raspberry Pi Pico
+- Adafruit Feather RP2040
+- Adafruit Itsy Bitsy RP2040
+- Adafruit QT RP2040
+- Adfruit Feather ESP32-S2
+- Adafruit Magtag 29" Eink
+- Adafruit Metro ESP32-S2
+- Adafruit PyBadge
+- Adafruit PyPortal
+- Great Scott Gadgets' LUNA D11 & D21
 
 
 0.7.0 (08-11-2020)
@@ -278,32 +394,38 @@ New Boards
 Device Controller Driver
 ------------------------
 
--  Added new support for Espressif ESP32-S2
--  Added new support for Dialog DA1469x
--  Enhance STM32 Synopsys
--  Support bus events disconnection/suspend/resume/wakeup
-   -  Improve transfer performance with optimizing xfer and fifo size
-   -  Support Highspeed port (OTG_HS) with both internal and external PHY
-   -  Support multiple usb ports with rhport=1 is highspeed on selected MCUs e.g H743, F23. It is possible to have OTG_HS to run on Fullspeed PHY (e.g lacking external PHY)
-   -  Add ISO transfer, fix odd/even frame
-   -  Fix FIFO flush during stall
-   -  Implement dcd_edpt_close() API
-   -  Support F105, F107
--  Enhance STM32 fsdev
-   -  Improve dcd fifo allocation
-   -  Fix ISTR race condition
-   -  Support remap USB IRQ on supported MCUs
-   -  Implement dcd_edpt_close() API
--  Enhance NUC 505: enhance set configure behavior
--  Enhance SAMD
-   -  Fix race condition with setup packet
-   -  Add SAMD11 option `OPT_MCU_SAMD11`
-   -  Add SAME5x option `OPT_MCU_SAME5X`
--  Fix SAMG control data toggle and stall race condition
--  Enhance nRF
-   -  Fix hanged when tud_task() is called within critical section (disabled interrupt)
-   -  Fix disconnect bus event not submitted
-   -  Implement ISO transfer and dcd_edpt_close()
+- Added new support for Espressif ESP32-S2
+- Added new support for Dialog DA1469x
+- Enhance STM32 Synopsys
+
+- Support bus events disconnection/suspend/resume/wakeup
+  - Improve transfer performance with optimizing xfer and fifo size
+  - Support Highspeed port (OTG_HS) with both internal and external PHY
+  - Support multiple usb ports with rhport=1 is highspeed on selected MCUs e.g H743, F23. It is possible to have OTG_HS to run on Fullspeed PHY (e.g lacking external PHY)
+  - Add ISO transfer, fix odd/even frame
+  - Fix FIFO flush during stall
+  - Implement dcd_edpt_close() API
+  - Support F105, F107
+  
+- Enhance STM32 fsdev
+  - Improve dcd fifo allocation
+  - Fix ISTR race condition
+  - Support remap USB IRQ on supported MCUs
+  - Implement dcd_edpt_close() API
+  
+- Enhance NUC 505: enhance set configure behavior
+
+- Enhance SAMD
+  - Fix race condition with setup packet
+  - Add SAMD11 option `OPT_MCU_SAMD11`
+  - Add SAME5x option `OPT_MCU_SAME5X`
+  
+- Fix SAMG control data toggle and stall race condition
+
+- Enhance nRF
+  - Fix hanged when tud_task() is called within critical section (disabled interrupt)
+  - Fix disconnect bus event not submitted
+  - Implement ISO transfer and dcd_edpt_close()
 
 
 USB Device
@@ -311,79 +433,89 @@ USB Device
 
 **USBD**
 
--  Add new class driver for **Bluetooth HCI** class driver with example can be found in [mynewt-tinyusb-example](https://github.com/hathach/mynewt-tinyusb-example) since it needs mynewt OS to run with.
--  Fix USBD endpoint usage racing condition with `usbd_edpt_claim()/usbd_edpt_release()`
--  Added `tud_task_event_ready()` and `osal_queue_empty()`. This API is needed to check before enter low power mode with WFI/WFE
--  Rename USB IRQ Handler to `dcd_int_handler()`. Application must define IRQ handler in which it calls this API.
--  Add `dcd_connect()` and `dcd_disconnect()` to enable/disable internal pullup on D+/D-  on supported MCUs.
--  Add `usbd_edpt_open()`
--  Remove `dcd_set_config()`
--  Add *OPT_OS_CUMSTOM* as hook for application to overwrite and/or add their own OS implementation
--  Support SET_INTERFACE, GET_INTERFACE request
--  Add Logging for debug with optional uart/rtt/swo printf retarget or `CFG_TUSB_DEBUG_PRINTF` hook
--  Add IAR compiler support
--  Support multiple configuration descriptors. `TUD_CONFIG_DESCRIPTOR()` template has extra config_num as 1st argument
--  Improve USB Highspeed support with actual link speed detection with `dcd_event_bus_reset()`
--  Enhance class driver management
-   -  `usbd_driver_open()` add max length argument, and return length of interface (0 for not supported). Return value is used for finding appropriate driver
-   -  Add application implemented class driver via `usbd_app_driver_get_cb()`
-   -  IAD is handled to assign driver id
--  Added `tud_descriptor_device_qualifier_cb()` callback
--  Optimize `tu_fifo` bulk write/read transfer
--  Forward non-std control request to class driver
--  Let application handle Microsoft OS 1.0 Descriptors (the 0xEE index string)
--  Fix OSAL FreeRTOS yield from ISR
+- Add new class driver for **Bluetooth HCI** class driver with example can be found in [mynewt-tinyusb-example](https://github.com/hathach/mynewt-tinyusb-example) since it needs mynewt OS to run with.
+- Fix USBD endpoint usage racing condition with `usbd_edpt_claim()/usbd_edpt_release()`
+- Added `tud_task_event_ready()` and `osal_queue_empty()`. This API is needed to check before enter low power mode with WFI/WFE
+- Rename USB IRQ Handler to `dcd_int_handler()`. Application must define IRQ handler in which it calls this API.
+- Add `dcd_connect()` and `dcd_disconnect()` to enable/disable internal pullup on D+/D- on supported MCUs.
+- Add `usbd_edpt_open()`
+- Remove `dcd_set_config()`
+- Add *OPT_OS_CUMSTOM* as hook for application to overwrite and/or add their own OS implementation
+- Support SET_INTERFACE, GET_INTERFACE request
+- Add Logging for debug with optional uart/rtt/swo printf retarget or `CFG_TUSB_DEBUG_PRINTF` hook
+- Add IAR compiler support
+- Support multiple configuration descriptors. `TUD_CONFIG_DESCRIPTOR()` template has extra config_num as 1st argument
+- Improve USB Highspeed support with actual link speed detection with `dcd_event_bus_reset()`
+
+- Enhance class driver management
+  - `usbd_driver_open()` add max length argument, and return length of interface (0 for not supported). Return value is used for finding appropriate driver
+  - Add application implemented class driver via `usbd_app_driver_get_cb()`
+  - IAD is handled to assign driver id
+  
+- Added `tud_descriptor_device_qualifier_cb()` callback
+- Optimize `tu_fifo` bulk write/read transfer
+- Forward non-std control request to class driver
+- Let application handle Microsoft OS 1.0 Descriptors (the 0xEE index string)
+- Fix OSAL FreeRTOS yield from ISR
 
 **Class Drivers**
 
--  USBNET: remove ACM-EEM due to lack of support from host
--  USBTMC: fix descriptors when INT EP is disabled
--  CDC:
-   -  Send zero length packet for end of data when needed
-   -  Add `tud_cdc_tx_complete_cb()` callback
-   -  Change tud_cdc_n_write_flush() return number of bytes forced to transfer, and flush when writing enough data to fifo
--  MIDI:
-   -  Add packet interface
-   -  Add multiple jack descriptors
-   -  Fix MIDI driver for sysex
--  DFU Runtime: fix response to SET_INTERFACE and DFU_GETSTATUS request
--  Rename some configure macro to make it clear that those are used directly for endpoint transfer
-   -  CFG_TUD_HID_BUFSIZE to CFG_TUD_HID_EP_BUFSIZE
-   -  CFG_TUD_CDC_EPSIZE to CFG_TUD_CDC_EP_BUFSIZE
-   -  CFG_TUD_MSC_BUFSIZE to CFG_TUD_MSC_EP_BUFSIZE
-   -  CFG_TUD_MIDI_EPSIZE to CFG_TUD_MIDI_EP_BUFSIZE
--  HID:
-   -  Fix gamepad template descriptor
-   -  Add multiple HID interface API
-   -  Add extra comma to HID_REPORT_ID
+- USBNET: remove ACM-EEM due to lack of support from host
+- USBTMC: fix descriptors when INT EP is disabled
+
+- CDC:
+  - Send zero length packet for end of data when needed
+  - Add `tud_cdc_tx_complete_cb()` callback
+  - Change tud_cdc_n_write_flush() return number of bytes forced to transfer, and flush when writing enough data to fifo
+  
+- MIDI:
+  - Add packet interface
+  - Add multiple jack descriptors
+  - Fix MIDI driver for sysex
+  
+- DFU Runtime: fix response to SET_INTERFACE and DFU_GETSTATUS request
+
+- Rename some configure macro to make it clear that those are used directly for endpoint transfer
+  - CFG_TUD_HID_BUFSIZE to CFG_TUD_HID_EP_BUFSIZE
+  - CFG_TUD_CDC_EPSIZE to CFG_TUD_CDC_EP_BUFSIZE
+  - CFG_TUD_MSC_BUFSIZE to CFG_TUD_MSC_EP_BUFSIZE
+  - CFG_TUD_MIDI_EPSIZE to CFG_TUD_MIDI_EP_BUFSIZE
+  
+- HID:
+  - Fix gamepad template descriptor
+  - Add multiple HID interface API
+  - Add extra comma to HID_REPORT_ID
 
 USB Host
 --------
 
--  Rework USB host stack (still work in progress)
-   -  Fix compile error with pipehandle
-   -  Rework usbh control and enumeration as non-blocking
--  Improve Hub, MSC, HID host driver
+- Rework USB host stack (still work in progress)
+   - Fix compile error with pipehandle
+   - Rework usbh control and enumeration as non-blocking
+   
+- Improve Hub, MSC, HID host driver
 
 Examples
 --------
 
--  Add new hid_composite_freertos
--  Add new dynamic_configuration to demonstrate how to switch configuration descriptors
--  Add new hid_multiple_interface
--  Enhance `net_lwip_webserver` example
-   -  Add multiple configuration: RNDIS for Windows, CDC-ECM for macOS (Linux will work with both)
-   -  Update lwip to STABLE-2_1_2_RELEASE for net_lwip_webserver
--  Added new Audio example: audio_test uac2_headsest
+- Add new hid_composite_freertos
+- Add new dynamic_configuration to demonstrate how to switch configuration descriptors
+- Add new hid_multiple_interface
+
+- Enhance `net_lwip_webserver` example
+  - Add multiple configuration: RNDIS for Windows, CDC-ECM for macOS (Linux will work with both)
+  - Update lwip to STABLE-2_1_2_RELEASE for net_lwip_webserver
+  
+- Added new Audio example: audio_test uac2_headsest
 
 New Boards
 ----------
 
--  Espressif ESP32-S2: saola_1, kaluga_1
--  STM32: F746 Nucleo, H743 Eval, H743 Nucleo, F723 discovery, stlink v3 mini, STM32L4r5 Nucleo
--  Dialog DA1469x dk pro and dk usb
--  Microchip: Great Scoot Gadgets' LUNA, samd11_xplained, D5035-01, atsamd21 xplained pro
--  nRF: ItsyBitsy nRF52840
+- Espressif ESP32-S2: saola_1, kaluga_1
+- STM32: F746 Nucleo, H743 Eval, H743 Nucleo, F723 discovery, stlink v3 mini, STM32L4r5 Nucleo
+- Dialog DA1469x dk pro and dk usb
+- Microchip: Great Scoot Gadgets' LUNA, samd11_xplained, D5035-01, atsamd21 xplained pro
+- nRF: ItsyBitsy nRF52840
 
 
 0.6.0 (30-03-2020)
@@ -396,111 +528,56 @@ Added
 
 **MCU**
 
--  Added support for Microchip SAMG55
--  Added support for Nordic nRF52833
--  Added support for Nuvoton: NUC120, NUC121/NUC125, NUC126, NUC505
--  Added support for NXP LPC: 51Uxx, 54xxx, 55xx
--  Added support for NXP iMXRT: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
--  Added support for Sony CXD56 (Spresense)
--  Added support for STM32: L0, F0, F1, F2, F3, F4, F7, H7
--  Added support for TI MSP430
--  Added support for ValentyUSB's eptri
+- Added support for Microchip SAMG55
+- Added support for Nordic nRF52833
+- Added support for Nuvoton: NUC120, NUC121/NUC125, NUC126, NUC505
+- Added support for NXP LPC: 51Uxx, 54xxx, 55xx
+- Added support for NXP iMXRT: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
+- Added support for Sony CXD56 (Spresense)
+- Added support for STM32: L0, F0, F1, F2, F3, F4, F7, H7
+- Added support for TI MSP430
+- Added support for ValentyUSB's eptri
 
 **Class Driver**
 
--  Added DFU Runtime class driver
--  Added Network class driver with RNDIS, CDC-ECM, CDC-EEM (work in progress)
--  Added USBTMC class driver
--  Added WebUSB class driver using vendor-specific class
--  Added multiple instances support for CDC and MIDI
--  Added a handful of unit test with Ceedling.
--  Added LOG support for debugging with CFG_TUSB_DEBUG
--  Added `tud_descriptor_bos_cb()` for BOS descriptor (required for USB 2.1)
--  Added `dcd_edpt0_status_complete()` as optional API for DCD
+- Added DFU Runtime class driver
+- Added Network class driver with RNDIS, CDC-ECM, CDC-EEM (work in progress)
+- Added USBTMC class driver
+- Added WebUSB class driver using vendor-specific class
+- Added multiple instances support for CDC and MIDI
+- Added a handful of unit test with Ceedling.
+- Added LOG support for debugging with CFG_TUSB_DEBUG
+- Added `tud_descriptor_bos_cb()` for BOS descriptor (required for USB 2.1)
+- Added `dcd_edpt0_status_complete()` as optional API for DCD
 
 **Examples**
 
 Following examples are added:
 
--  board_test
--  cdc_dual_ports
--  dfu_rt
--  hid_composite
--  net_lwip_webserver
--  usbtmc
--  webusb_serial
-
-**Boards**
-
-Following boards are added:
-
--  adafruit_clue
--  arduino_nano33_ble
--  circuitplayground_bluefruit
--  circuitplayground_express
--  feather_m0_express
--  feather_nrf52840_sense
--  feather_stm32f405
--  fomu
--  itsybitsy_m0
--  itsybitsy_m4
--  lpcxpresso11u37
--  lpcxpresso1549
--  lpcxpresso51u68
--  lpcxpresso54114
--  lpcxpresso55s69
--  mbed1768
--  mimxrt1010_evk
--  mimxrt1015_evk
--  mimxrt1020_evk
--  mimxrt1050_evkb
--  mimxrt1060_evk
--  mimxrt1064_evk
--  msp_exp430f5529lp
--  ngx4330
--  nrf52840_mdk_dongle
--  nutiny_nuc121s
--  nutiny_nuc125s
--  nutiny_nuc126v
--  nutiny_sdk_nuc120
--  nutiny_sdk_nuc505
--  pca10059
--  pca10100
--  pyboardv11
--  raytac_mdbt50q_rx
--  samg55xplained
--  seeeduino_xiao
--  spresense
--  stm32f070rbnucleo
--  stm32f072disco
--  stm32f103bluepill
--  stm32f207nucleo
--  stm32f401blackpill
--  stm32f411blackpill
--  stm32f411disco
--  stm32f412disco
--  stm32f767nucleo
--  stm32h743nucleo
--  stm32l0538disco
--  stm32l476disco
--  teensy_40
+- board_test
+- cdc_dual_ports
+- dfu_rt
+- hid_composite
+- net_lwip_webserver
+- usbtmc
+- webusb_serial
 
 Changed
 -------
 
--  Changed `tud_descriptor_string_cb()` to have additional Language ID argument
--  Merged hal_nrf5x.c into dcd_nrf5x.c
--  Merged dcd_samd21.c and dcd_samd51.c into dcd_samd.c
--  Generalized dcd_stm32f4.c to dcd_synopsys.c
--  Changed cdc_msc_hid to cdc_msc (drop hid) due to limited endpoints number of some MCUs
--  Improved DCD SAMD stability, fix missing setup packet occasionally
--  Improved usbd/usbd_control with proper hanlding of zero-length packet (ZLP)
--  Improved STM32 DCD FSDev
--  Improved STM32 DCD Synopsys
--  Migrated CI from Travis to Github Action
--  Updated nrfx submodule to 2.1.0
--  Fixed mynewt osal queue definition
--  Fixed cdc_msc_freertos example build for all MCUs
+- Changed `tud_descriptor_string_cb()` to have additional Language ID argument
+- Merged hal_nrf5x.c into dcd_nrf5x.c
+- Merged dcd_samd21.c and dcd_samd51.c into dcd_samd.c
+- Generalized dcd_stm32f4.c to dcd_synopsys.c
+- Changed cdc_msc_hid to cdc_msc (drop hid) due to limited endpoints number of some MCUs
+- Improved DCD SAMD stability, fix missing setup packet occasionally
+- Improved usbd/usbd_control with proper hanlding of zero-length packet (ZLP)
+- Improved STM32 DCD FSDev
+- Improved STM32 DCD Synopsys
+- Migrated CI from Travis to Github Action
+- Updated nrfx submodule to 2.1.0
+- Fixed mynewt osal queue definition
+- Fixed cdc_msc_freertos example build for all MCUs
 
 
 0.5.0 (06-2019)
@@ -508,6 +585,6 @@ Changed
 
 First release, device stack works great, host stack works but still need improvement.
 
--  Special thanks to @adafruit team, especially @tannewt to help out immensely to rework device stack: simplify osal & control transfer, adding SAMD21/SAMD51 ports, writing porting docs, adding MIDI class support etc...
--  Thanks to @cr1901 for adding STM32F4 port.
--  Thanks to @PTS93 and @todbot for HID raw API
+- Special thanks to @adafruit team, especially @tannewt to help out immensely to rework device stack: simplify osal & control transfer, adding SAMD21/SAMD51 ports, writing porting docs, adding MIDI class support etc...
+- Thanks to @cr1901 for adding STM32F4 port.
+- Thanks to @PTS93 and @todbot for HID raw API
diff --git a/repository.yml b/repository.yml
index 16afbca55..21d092373 100644
--- a/repository.yml
+++ b/repository.yml
@@ -6,7 +6,10 @@ repo.versions:
     "0.7.0": "0.7.0"
     "0.8.0": "0.8.0"
     "0.9.0": "0.9.0"
+    "0.10.0": "0.10.0"
+    "0.10.1": "0.10.1"
+    "0.11.0": "0.11.0"
 
     "0-dev": "0.0.0"        # master
-    "0-latest": "0.9.0"     # latest stable release
+    "0-latest": "0.11.0"     # latest stable release
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index da1a39f1e..a00f3489f 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -28,8 +28,8 @@
 #define _TUSB_OPTION_H_
 
 #define TUSB_VERSION_MAJOR     0
-#define TUSB_VERSION_MINOR     10
-#define TUSB_VERSION_REVISION  1
+#define TUSB_VERSION_MINOR     11
+#define TUSB_VERSION_REVISION  0
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
 
 //--------------------------------------------------------------------+

From e72d48ee2960f48385950225aa35221a46a60dad Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Mon, 30 Aug 2021 13:40:01 +0700
Subject: [PATCH 0409/2085] Update changelog.rst

---
 docs/info/changelog.rst | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index b28ddcc54..5396c714f 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -40,15 +40,6 @@ RP2040
 - Add RP2040 suspend & resume support
 - Implement double buffer for both host and device (#891). Howver device EPOUT is still single bufferred due to techinical issue with short packet 
 
-Host Controller Driver (HCD)
-----------------------------
-
-RP2040
-^^^^^^
-
-- Implement double bufferred to fix E4 errata and boost performance
-- Lots of rp2040 update and enhancment
-
 Device Stack
 ------------
 
@@ -95,6 +86,15 @@ Vendor
 - Fix vendor fifo deadlock in certain case
 - Add tud_vendor_n_read_flush
 
+Host Controller Driver (HCD)
+----------------------------
+
+RP2040
+^^^^^^
+
+- Implement double bufferred to fix E4 errata and boost performance
+- Lots of rp2040 update and enhancment
+
 Host Stack
 ----------
 

From 36dc25a22d05cf9826944e363dd9ca4eb3416661 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Aug 2021 15:01:12 +0700
Subject: [PATCH 0410/2085] changelog

---
 docs/info/changelog.rst | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index 5396c714f..4325ff2ca 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -2,7 +2,7 @@
 Changelog
 *********
 
-0.11.0 (29-08-2021)
+0.11.0 (2021-08-29)
 ===================
 
 - Add host/hid_controller example: only worked/tested with Sony PS4 DualShock controller
@@ -103,7 +103,7 @@ Host Stack
 - Rework and major update to HID driver. Will default to enable boot interface if available
 - Sepearate CFG_TUH_DEVICE_MAX and CFG_TUH_HUB for better management and reduce SRAM usage
 
-0.10.1 (03-06-2021)
+0.10.1 (2021-06-03)
 ===================
 
 - rework rp2040 examples and CMake build, allow better integration with pico-sdk
@@ -117,7 +117,7 @@ Host Controller Driver (HCD)
 - Use hcd_frame_number() instead of micro frame
 - Fix OHCI endpoint address and xferred_bytes in xfer complete event
 
-0.10.0 (28-05-2021)
+0.10.0 (2021-05-28)
 ===================
 
 - Rework tu_fifo_t with separated mutex for read and write, better support DMA with read/write buffer info. And constant address mode
@@ -191,7 +191,7 @@ Host Class Driver
 - HID: Rework host hid driver, basically everything changes
 
 
-0.9.0 (12-03-2021)
+0.9.0 (2021-03-12)
 ==================
 
 Device Stack
@@ -309,7 +309,7 @@ Others
 - LPCXpresso 18s37
 
 
-0.8.0 (05-02-2021)
+0.8.0 (2021-02-05)
 ==================
 
 Device Controller Driver
@@ -388,7 +388,7 @@ New Boards
 - Great Scott Gadgets' LUNA D11 & D21
 
 
-0.7.0 (08-11-2020)
+0.7.0 (2020-11-08)
 ==================
 
 Device Controller Driver
@@ -518,7 +518,7 @@ New Boards
 - nRF: ItsyBitsy nRF52840
 
 
-0.6.0 (30-03-2020)
+0.6.0 (2020-03-30)
 ==================
 
 Added **CONTRIBUTORS.md** to give proper credit for contributors to the stack. Special thanks to `Nathan Conrad <https://github.com/pigrew>`__ , `Peter Lawrence <https://github.com/majbthrd>`__ , `William D. Jones <https://github.com/cr1901>`__ and `Sean Cross <https://github.com/xobs>`__ and others for spending their precious time to add lots of features and ports for this release.
@@ -580,7 +580,7 @@ Changed
 - Fixed cdc_msc_freertos example build for all MCUs
 
 
-0.5.0 (06-2019)
+0.5.0 (2019-06)
 ===============
 
 First release, device stack works great, host stack works but still need improvement.

From 8305766afe909a6f1b3be6a88cd4e6c4017255a8 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 31 Aug 2021 11:27:43 +0200
Subject: [PATCH 0411/2085] fix HID_LOGICAL_MAX overflow.

---
 src/class/hid/hid_device.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 5cf4b3060..7f67fa9cf 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -364,14 +364,14 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
       /* Input */ \
       HID_USAGE       ( 0x02                                   ),\
       HID_LOGICAL_MIN ( 0x00                                   ),\
-      HID_LOGICAL_MAX ( 0xff                                   ),\
+      HID_LOGICAL_MAX_N ( 0xff, 2                              ),\
       HID_REPORT_SIZE ( 8                                      ),\
       HID_REPORT_COUNT( report_size                            ),\
       HID_INPUT       ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ),\
       /* Output */ \
       HID_USAGE       ( 0x03                                    ),\
       HID_LOGICAL_MIN ( 0x00                                    ),\
-      HID_LOGICAL_MAX ( 0xff                                    ),\
+      HID_LOGICAL_MAX_N ( 0xff, 2                               ),\
       HID_REPORT_SIZE ( 8                                       ),\
       HID_REPORT_COUNT( report_size                             ),\
       HID_OUTPUT      ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE  ),\

From 76345ea3a1d78924585b8c4e0c5b5cb5e89d74e7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Aug 2021 16:41:45 +0700
Subject: [PATCH 0412/2085] clear stall and reset data toggle when open edpt

required to pass one of msc test.
---
 hw/bsp/samd21/boards/metro_m0_express/board.h | 2 +-
 hw/bsp/samd51/boards/metro_m4_express/board.h | 4 ++--
 src/portable/microchip/samd/dcd_samd.c        | 2 ++
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.h b/hw/bsp/samd21/boards/metro_m0_express/board.h
index b9292b9af..13b7556b0 100644
--- a/hw/bsp/samd21/boards/metro_m0_express/board.h
+++ b/hw/bsp/samd21/boards/metro_m0_express/board.h
@@ -35,7 +35,7 @@
 #define LED_PIN               17
 #define LED_STATE_ON          1
 
-// Button
+// Button: D5
 #define BUTTON_PIN            15
 #define BUTTON_STATE_ACTIVE   0
 
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h
index 9bb5f815e..ab10ae4f8 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.h
+++ b/hw/bsp/samd51/boards/metro_m4_express/board.h
@@ -35,8 +35,8 @@
 #define LED_PIN               16
 #define LED_STATE_ON          1
 
-// Button
-#define BUTTON_PIN            (32+14) // D5
+// Button: D5
+#define BUTTON_PIN            (32+14)
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index 54e8e62d9..526a6fb63 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -230,10 +230,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   if ( dir == TUSB_DIR_OUT )
   {
     ep->EPCFG.bit.EPTYPE0 = desc_edpt->bmAttributes.xfer + 1;
+    ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0 | USB_DEVICE_EPSTATUSCLR_DTGLOUT; // clear stall & dtoggle
     ep->EPINTENSET.bit.TRCPT0 = true;
   }else
   {
     ep->EPCFG.bit.EPTYPE1 = desc_edpt->bmAttributes.xfer + 1;
+    ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1 | USB_DEVICE_EPSTATUSCLR_DTGLIN; // clear stall & dtoggle
     ep->EPINTENSET.bit.TRCPT1 = true;
   }
 

From 864d8381a7acbd89053b6d478c064872b4871ed9 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 26 Jun 2021 19:53:57 +0200
Subject: [PATCH 0413/2085] dcd_transmission xfer_fifo support.

---
 .../nxp/transdimension/dcd_transdimension.c   | 114 +++++++++++++++++-
 1 file changed, 112 insertions(+), 2 deletions(-)

diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 42047ef92..156695fc4 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -128,7 +128,8 @@ typedef struct
   /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
   /// thus there are 16 bytes padding free that we can make use of.
   //--------------------------------------------------------------------+
-  uint8_t reserved[16];
+  tu_fifo_t * ff;
+  uint8_t reserved[12];
 } dcd_qhd_t;
 
 TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
@@ -314,6 +315,39 @@ static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
   }
 }
 
+static void qtd_init_fifo(dcd_qtd_t* p_qtd, tu_fifo_buffer_info_t *info, uint16_t total_bytes)
+{
+  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
+
+  p_qtd->next        = QTD_NEXT_INVALID;
+  p_qtd->active      = 1;
+  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
+
+  // Fifo length has been trimmed to total_bytes
+  int16_t len_lin  = info->len_lin;
+
+  if (len_lin != 0)
+  {
+    p_qtd->buffer[0]   = (uint32_t) info->ptr_lin;
+                
+    len_lin -= 4096 - ((uint32_t) info->ptr_lin - tu_align4k((uint32_t) info->ptr_lin));
+    
+    // Set linear part
+    uint8_t i = 1;
+    for(; i<5; i++)
+    {
+      if (len_lin <= 0) break;
+      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
+      len_lin -= 4096;  
+    }
+    // Set wrapped part
+    for(uint8_t page = 0; i<5; i++, page++)
+    {
+      p_qtd->buffer[i] |= (uint32_t) info->ptr_wrap + 4096 * page;
+    }  
+  }
+}
+
 //--------------------------------------------------------------------+
 // DCD Endpoint Port
 //--------------------------------------------------------------------+
@@ -407,6 +441,67 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
   return true;
 }
 
+// fifo has to be aligned to 4k boundary
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) 
+{
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const ep_idx = 2*epnum + dir;
+
+  if ( epnum == 0 )
+  {
+    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
+    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
+    while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
+  }
+
+  dcd_qhd_t * p_qhd      = &_dcd_data.qhd[ep_idx];
+  dcd_qtd_t * p_qtd      = &_dcd_data.qtd[ep_idx];
+
+  tu_fifo_buffer_info_t fifo_info;
+    
+  if(dir == TUSB_DIR_IN)
+  {
+    tu_fifo_get_read_info(ff, &fifo_info);
+  }
+  else
+  {
+    tu_fifo_get_write_info(ff, &fifo_info);
+  }
+    
+  if(total_bytes <= fifo_info.len_lin)
+  {
+    // Limit transfer length to total_bytes
+    fifo_info.len_wrap = 0;
+    fifo_info.len_lin = total_bytes;
+  }
+  else
+  {
+    // Class driver ensure at least total_bytes elements in fifo
+    fifo_info.len_wrap = total_bytes - fifo_info.len_lin;
+  }
+  // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
+  // address to 32-byte boundaries.
+  // void* cast to suppress cast-align warning, buffer must be
+  CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_lin, 4), fifo_info.len_lin + 31);
+  if(fifo_info.len_wrap > 0)
+     CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31);
+
+  //------------- Prepare qtd -------------//
+  qtd_init_fifo(p_qtd, &fifo_info, total_bytes);
+  p_qtd->int_on_complete = true;
+  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
+  p_qhd->ff = ff;
+
+  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+
+  // start transfer
+  dcd_reg->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
+
+  return true;
+}
+
 //--------------------------------------------------------------------+
 // ISR
 //--------------------------------------------------------------------+
@@ -474,13 +569,28 @@ void dcd_int_handler(uint8_t rhport)
         if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) )
         {
           // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
+          dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
           dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
 
           uint8_t result = p_qtd->halted  ? XFER_RESULT_STALLED :
               ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
 
           uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
-          dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
+            
+          uint16_t xferred_bytes = p_qtd->expected_bytes - p_qtd->total_bytes;
+
+          if (p_qhd->ff)
+          {
+            if(tu_edpt_dir(ep_addr) == TUSB_DIR_IN)
+            {
+              tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes);
+            }
+            else
+            {
+              tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
+            }
+          }  
+          dcd_event_xfer_complete(rhport, ep_addr, xferred_bytes, result, true); // only number of bytes in the IOC qtd
         }
       }
     }

From 16b802d50cff6118952767b8fefa33dd0447ea91 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sat, 26 Jun 2021 23:13:01 +0200
Subject: [PATCH 0414/2085] add dcd_edpt_close and iso xfer.

---
 .../nxp/transdimension/dcd_transdimension.c   | 75 ++++++++++++-------
 1 file changed, 49 insertions(+), 26 deletions(-)

diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 156695fc4..a4d6c5d48 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -239,8 +239,9 @@ void dcd_init(uint8_t rhport)
   dcd_reg->USBMODE = USBMODE_CM_DEVICE;
   dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
 
-  // TODO Force fullspeed on non-highspeed port
-  // dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
+#if !TUD_OPT_HIGH_SPEED
+  dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
+#endif
 
   CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
 
@@ -329,22 +330,22 @@ static void qtd_init_fifo(dcd_qtd_t* p_qtd, tu_fifo_buffer_info_t *info, uint16_
   if (len_lin != 0)
   {
     p_qtd->buffer[0]   = (uint32_t) info->ptr_lin;
-                
+
     len_lin -= 4096 - ((uint32_t) info->ptr_lin - tu_align4k((uint32_t) info->ptr_lin));
-    
+
     // Set linear part
     uint8_t i = 1;
     for(; i<5; i++)
     {
       if (len_lin <= 0) break;
       p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
-      len_lin -= 4096;  
+      len_lin -= 4096;
     }
     // Set wrapped part
     for(uint8_t page = 0; i<5; i++, page++)
     {
       p_qtd->buffer[i] |= (uint32_t) info->ptr_wrap + 4096 * page;
-    }  
+    }
   }
 }
 
@@ -373,9 +374,6 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
-  // TODO not support ISO yet
-  TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
-
   uint8_t const epnum  = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
   uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   uint8_t const ep_idx = 2*epnum + dir;
@@ -387,14 +385,25 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
   tu_memclr(p_qhd, sizeof(dcd_qhd_t));
 
-  p_qhd->zero_length_termination = 1;
   p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
   p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
 
+  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
+  {
+    p_qhd->iso_mult = 1;
+  } else
+  {
+    p_qhd->zero_length_termination = 1;
+  }
+
   CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
 
   // Enable EP Control
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
+  // Clear EP type
+  dcd_reg->ENDPTCTRL[epnum] &=~(0x03 << (dir ? 18 : 2));
+
   dcd_reg->ENDPTCTRL[epnum] |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0);
 
   return true;
@@ -406,6 +415,22 @@ void dcd_edpt_close_all (uint8_t rhport)
   // TODO implement dcd_edpt_close_all()
 }
 
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = tu_edpt_number(ep_addr);
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
+
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
+  // Flush EP
+  uint32_t flush_mask = TU_BIT(epnum) << (dir ? 16 : 0);
+  dcd_reg->ENDPTFLUSH = flush_mask;
+  while(dcd_reg->ENDPTFLUSH & flush_mask);
+
+  // Clear EP enable
+  dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0));
+}
+
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -442,7 +467,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 }
 
 // fifo has to be aligned to 4k boundary
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) 
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
   uint8_t const epnum = tu_edpt_number(ep_addr);
@@ -460,34 +485,33 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   dcd_qtd_t * p_qtd      = &_dcd_data.qtd[ep_idx];
 
   tu_fifo_buffer_info_t fifo_info;
-    
-  if(dir == TUSB_DIR_IN)
+
+  if (dir)
   {
     tu_fifo_get_read_info(ff, &fifo_info);
-  }
-  else
+  } else
   {
     tu_fifo_get_write_info(ff, &fifo_info);
   }
-    
+
   if(total_bytes <= fifo_info.len_lin)
   {
     // Limit transfer length to total_bytes
     fifo_info.len_wrap = 0;
     fifo_info.len_lin = total_bytes;
-  }
-  else
+  } else
   {
-    // Class driver ensure at least total_bytes elements in fifo
+    // Class driver need to ensure at least total_bytes elements in fifo
     fifo_info.len_wrap = total_bytes - fifo_info.len_lin;
   }
   // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
   // address to 32-byte boundaries.
   // void* cast to suppress cast-align warning, buffer must be
   CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_lin, 4), fifo_info.len_lin + 31);
-  if(fifo_info.len_wrap > 0)
+  if (fifo_info.len_wrap > 0)
+  {
      CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31);
-
+  }
   //------------- Prepare qtd -------------//
   qtd_init_fifo(p_qtd, &fifo_info, total_bytes);
   p_qtd->int_on_complete = true;
@@ -576,20 +600,19 @@ void dcd_int_handler(uint8_t rhport)
               ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
 
           uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
-            
+
           uint16_t xferred_bytes = p_qtd->expected_bytes - p_qtd->total_bytes;
 
           if (p_qhd->ff)
           {
-            if(tu_edpt_dir(ep_addr) == TUSB_DIR_IN)
+            if (tu_edpt_dir(ep_addr))
             {
               tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes);
-            }
-            else
+            } else
             {
               tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
             }
-          }  
+          }
           dcd_event_xfer_complete(rhport, ep_addr, xferred_bytes, result, true); // only number of bytes in the IOC qtd
         }
       }

From e3bf4c069b4624807a7eade9f2432c0bebfae4ec Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 6 Jul 2021 00:37:14 +0200
Subject: [PATCH 0415/2085] UAC2: Add ring buffer support for
 dcd_transdimension. Add ring buffer ON/OFF switch.

---
 src/class/audio/audio_device.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index ff4e312a7..e16771cd3 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -64,10 +64,19 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+// Use ring buffer if it's available, some MCUs need extra RAM requirements
+#ifndef TUD_AUDIO_PREFER_RING_BUFFER
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+#define TUD_AUDIO_PREFER_RING_BUFFER 0
+#else
+#define TUD_AUDIO_PREFER_RING_BUFFER 1
+#endif
+#endif
+
 // Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer
 // is available or driver is would need to be changed dramatically
 
-// Only STM32 synopsys use non-linear buffer for now
+// Only STM32 synopsys and dcd_transdimension use non-linear buffer for now
 // Synopsys detection copied from dcd_synopsys.c (refactor later on)
 #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
     defined (STM32F107xB) || defined (STM32F107xC)
@@ -90,11 +99,18 @@
     CFG_TUSB_MCU == OPT_MCU_RX63X                                 || \
     CFG_TUSB_MCU == OPT_MCU_RX65X                                 || \
     CFG_TUSB_MCU == OPT_MCU_RX72N                                 || \
-    CFG_TUSB_MCU == OPT_MCU_GD32VF103
+    CFG_TUSB_MCU == OPT_MCU_GD32VF103                             || \
+    CFG_TUSB_MCU == OPT_MCU_LPC18XX                               || \
+    CFG_TUSB_MCU == OPT_MCU_LPC43XX                               || \
+    CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+#if TUD_AUDIO_PREFER_RING_BUFFER
 #define  USE_LINEAR_BUFFER     0
 #else
 #define  USE_LINEAR_BUFFER     1
 #endif
+#else
+#define  USE_LINEAR_BUFFER     1
+#endif
 
 // Declaration of buffers
 

From d047b28aa262f253b758b82bc32fed55eb59d213 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Aug 2021 17:39:54 +0700
Subject: [PATCH 0416/2085] remove set/clear busy flag in set/clear stall since
 they are different status

note: dcd should resume to prio-stalled queued transfer when unstall
---
 src/device/usbd.c     | 6 ++----
 src/device/usbd_pvt.h | 3 ++-
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 7cd8fad42..4f5a2f8ed 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1214,12 +1214,12 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr)
 
 #if CFG_TUSB_OS != OPT_OS_NONE
   // pre-check to help reducing mutex lock
-  TU_VERIFY((_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0));
+  TU_VERIFY( usbd_edpt_ready(rhport, ep_addr) && (_usbd_dev.ep_status[epnum][dir].claimed == 0));
   osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 #endif
 
   // can only claim the endpoint if it is not busy and not claimed yet.
-  bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0);
+  bool const ret = usbd_edpt_ready(rhport, ep_addr) && (_usbd_dev.ep_status[epnum][dir].claimed == 0);
   if (ret)
   {
     _usbd_dev.ep_status[epnum][dir].claimed = 1;
@@ -1340,7 +1340,6 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
   dcd_edpt_stall(rhport, ep_addr);
   _usbd_dev.ep_status[epnum][dir].stalled = true;
-  _usbd_dev.ep_status[epnum][dir].busy = true;
 }
 
 void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
@@ -1352,7 +1351,6 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
   dcd_edpt_clear_stall(rhport, ep_addr);
   _usbd_dev.ep_status[epnum][dir].stalled = false;
-  _usbd_dev.ep_status[epnum][dir].busy = false;
 }
 
 bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 6a4b30956..7607b9895 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -81,7 +81,7 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr);
 // Release an endpoint without submitting a transfer
 bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr);
 
-// Check if endpoint transferring is complete
+// Check if endpoint is busy transferring
 bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr);
 
 // Stall endpoint
@@ -93,6 +93,7 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr);
 // Check if endpoint is stalled
 bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr);
 
+// Check if endpoint is ready (not busy and not stalled)
 TU_ATTR_ALWAYS_INLINE static inline
 bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr)
 {

From ab0c3e8dd00e8baed6c0a233dd5377ef4497531d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Aug 2021 17:41:08 +0700
Subject: [PATCH 0417/2085] fix rp2040 chapter 9 TD 9.6 test

---
 src/class/msc/msc_device.c                   |  6 +++++-
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 10 ++++------
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 7dcd4983e..6b3a392a8 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -323,7 +323,11 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         if ( p_msc->stage == MSC_STAGE_CMD )
         {
           // part of reset recovery (probably due to invalid CBW) -> prepare for new command
-          TU_ASSERT( prepare_cbw(rhport, p_msc) );
+          // Note: skip if already queued previously
+          if ( usbd_edpt_ready(rhport, p_msc->ep_out) )
+          {
+            TU_ASSERT( prepare_cbw(rhport, p_msc) );
+          }
         }
       }
     }
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index e81681d4f..0cd3e97de 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -389,17 +389,15 @@ void dcd_remote_wakeup(uint8_t rhport)
 // disconnect by disabling internal pull-up resistor on D+/D-
 void dcd_disconnect(uint8_t rhport)
 {
-    pico_info("dcd_disconnect %d\n", rhport);
-    assert(rhport == 0);
-    usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
+  (void) rhport;
+  usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
 }
 
 // connect by enabling internal pull-up resistor on D+/D-
 void dcd_connect(uint8_t rhport)
 {
-    pico_info("dcd_connect %d\n", rhport);
-    assert(rhport == 0);
-    usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
+  (void) rhport;
+  usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
 }
 
 /*------------------------------------------------------------------*/

From 90dc9bc289e12950fba9ea5dafe20e1b0777d0ba Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Sep 2021 12:42:45 +0700
Subject: [PATCH 0418/2085] revert previous changes, edpt stall also clear any
 pending (not complete) transfer

---
 src/class/msc/msc_device.c | 6 +-----
 src/device/usbd.c          | 6 ++++--
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 6b3a392a8..7dcd4983e 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -323,11 +323,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         if ( p_msc->stage == MSC_STAGE_CMD )
         {
           // part of reset recovery (probably due to invalid CBW) -> prepare for new command
-          // Note: skip if already queued previously
-          if ( usbd_edpt_ready(rhport, p_msc->ep_out) )
-          {
-            TU_ASSERT( prepare_cbw(rhport, p_msc) );
-          }
+          TU_ASSERT( prepare_cbw(rhport, p_msc) );
         }
       }
     }
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 4f5a2f8ed..9af9b2a6e 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1214,12 +1214,12 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr)
 
 #if CFG_TUSB_OS != OPT_OS_NONE
   // pre-check to help reducing mutex lock
-  TU_VERIFY( usbd_edpt_ready(rhport, ep_addr) && (_usbd_dev.ep_status[epnum][dir].claimed == 0));
+  TU_VERIFY( (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0));
   osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 #endif
 
   // can only claim the endpoint if it is not busy and not claimed yet.
-  bool const ret = usbd_edpt_ready(rhport, ep_addr) && (_usbd_dev.ep_status[epnum][dir].claimed == 0);
+  bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0);
   if (ret)
   {
     _usbd_dev.ep_status[epnum][dir].claimed = 1;
@@ -1340,6 +1340,7 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
   dcd_edpt_stall(rhport, ep_addr);
   _usbd_dev.ep_status[epnum][dir].stalled = true;
+  _usbd_dev.ep_status[epnum][dir].busy = true;
 }
 
 void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
@@ -1351,6 +1352,7 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
   dcd_edpt_clear_stall(rhport, ep_addr);
   _usbd_dev.ep_status[epnum][dir].stalled = false;
+  _usbd_dev.ep_status[epnum][dir].busy = false;
 }
 
 bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)

From fc889ece74626f49a08898039102f0a9bf2b85a1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Sep 2021 16:52:27 +0700
Subject: [PATCH 0419/2085] rp2040 correct ep set/clear stall

- stall will remove pending (not complete) transfer. Correct reset data
toggle when clear stall.
- remove buf ctrl debug code
---
 src/common/tusb_common.h                     |  3 ++
 src/device/dcd.h                             |  2 +-
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 29 +++++------
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |  3 +-
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 11 ++---
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 51 --------------------
 6 files changed, 22 insertions(+), 77 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 1452e0105..687f980be 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -110,6 +110,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t u32) { return
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t u32) { return TU_U32_BYTE1(u32); }
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t u32) { return TU_U32_BYTE0(u32); }
 
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_high16(uint32_t u32) { return (uint16_t) (u32 >> 16); }
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_low16 (uint32_t u32) { return (uint16_t) (u32 & 0x0000ffffu); }
+
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t u16) { return TU_U16_HIGH(u16); }
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t u16) { return TU_U16_LOW(u16); }
 
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 8d042bbde..d43a0dd9a 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -153,7 +153,7 @@ bool dcd_edpt_xfer            (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer
 // This API is optional, may be useful for register-based for transferring data.
 bool dcd_edpt_xfer_fifo       (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) TU_ATTR_WEAK;
 
-// Stall endpoint
+// Stall endpoint, any queuing transfer should be removed from endpoint
 void dcd_edpt_stall           (uint8_t rhport, uint8_t ep_addr);
 
 // clear stall, data toggle is also reset to DATA0
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 0cd3e97de..42ffaf883 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -145,8 +145,7 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t
 
   if ( num == 0 )
   {
-    // EP0 has no endpoint control register because
-    // the buffer offsets are fixed
+    // EP0 has no endpoint control register because the buffer offsets are fixed
     ep->endpoint_control = NULL;
 
     // Buffer offset is fixed (also double buffered)
@@ -178,7 +177,7 @@ static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_by
 static void hw_handle_buff_status(void)
 {
     uint32_t remaining_buffers = usb_hw->buf_status;
-    pico_trace("buf_status 0x%08x\n", remaining_buffers);
+    pico_trace("buf_status = 0x%08x\n", remaining_buffers);
     uint bit = 1u;
     for (uint i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++)
     {
@@ -186,8 +185,10 @@ static void hw_handle_buff_status(void)
         {
             // clear this in advance
             usb_hw_clear->buf_status = bit;
+
             // IN transfer for even i, OUT transfer for odd i
             struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, !(i & 1u));
+
             // Continue xfer
             bool done = hw_endpoint_xfer_continue(ep);
             if (done)
@@ -325,7 +326,6 @@ static void dcd_rp2040_irq(void)
 
 void dcd_init (uint8_t rhport)
 {
-  pico_trace("dcd_init %d\n", rhport);
   assert(rhport == 0);
 
   // Reset hardware to default state
@@ -370,7 +370,6 @@ void dcd_int_disable(uint8_t rhport)
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-  pico_trace("dcd_set_address %d %d\n", rhport, dev_addr);
   assert(rhport == 0);
 
   // Can't set device address in hardware until status xfer has complete
@@ -412,7 +411,6 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
        request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
        request->bRequest == TUSB_REQ_SET_ADDRESS )
   {
-    pico_trace("Set HW address %d\n", request->wValue);
     usb_hw->dev_addr_ctrl = (uint8_t) request->wValue;
   }
 
@@ -429,7 +427,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
-  // TODO implement dcd_edpt_close_all()
+  // reset_all_endpoints(); TODO double check endpoint control
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
@@ -441,8 +439,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  pico_trace("dcd_edpt_stall %02x\n", ep_addr);
-  assert(rhport == 0);
+  (void) rhport;
 
   if ( tu_edpt_number(ep_addr) == 0 )
   {
@@ -452,22 +449,22 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
   struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
 
-  // TODO check with double buffered
-  _hw_endpoint_buffer_control_set_mask32(ep, USB_BUF_CTRL_STALL);
+  // stall and clear current pending buffer
+  // may need to use EP_ABORT
+  _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_STALL);
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  pico_trace("dcd_edpt_clear_stall %02x\n", ep_addr);
-  assert(rhport == 0);
+  (void) rhport;
 
   if (tu_edpt_number(ep_addr))
   {
     struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
 
-    // clear stall also reset toggle to DATA0
-    // TODO check with double buffered
-    _hw_endpoint_buffer_control_clear_mask32(ep, USB_BUF_CTRL_STALL | USB_BUF_CTRL_DATA1_PID);
+    // clear stall also reset toggle to DATA0, ready for next transfer
+    ep->next_pid = 0;
+    _hw_endpoint_buffer_control_clear_mask32(ep, USB_BUF_CTRL_STALL);
   }
 }
 
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index e51dfac2b..5e5bb4906 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -201,7 +201,6 @@ static void hcd_rp2040_irq(void)
     {
         handled |= USB_INTS_BUFF_STATUS_BITS;
         TU_LOG(2, "Buffer complete\n");
-        // print_bufctrl32(*epx.buffer_control);
         hw_handle_buff_status();
     }
 
@@ -231,7 +230,7 @@ static void hcd_rp2040_irq(void)
     if (status & USB_INTS_ERROR_DATA_SEQ_BITS)
     {
         usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
-        print_bufctrl32(*epx.buffer_control);
+        TU_LOG(3, "  Seq Error: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(*epx.buffer_control), tu_u32_high16(*epx.buffer_control));
         panic("Data Seq Error \n");
     }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 43554d28b..f9b4d9b17 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -67,7 +67,6 @@ void rp2040_usb_init(void)
 
 void hw_endpoint_reset_transfer(struct hw_endpoint *ep)
 {
-  ep->stalled = false;
   ep->active = false;
   ep->remaining_len = 0;
   ep->xferred_len = 0;
@@ -171,8 +170,7 @@ static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
 
   *ep->endpoint_control = ep_ctrl;
 
-  TU_LOG(3, "Prepare Buffer Control:\r\n");
-  print_bufctrl32(buf_ctrl);
+  TU_LOG(3, "  Prepare BufCtrl: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
 
   // Finally, write to buffer_control which will trigger the transfer
   // the next time the controller polls this dpram address
@@ -231,7 +229,7 @@ static uint16_t sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
   // Short packet
   if (xferred_bytes < ep->wMaxPacketSize)
   {
-    pico_trace("Short rx transfer on buffer %d with %u bytes\n", buf_id, xferred_bytes);
+    pico_trace("  Short packet on buffer %d with %u bytes\n", buf_id, xferred_bytes);
     // Reduce total length as this is last packet
     ep->remaining_len = 0;
   }
@@ -245,8 +243,7 @@ static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
   // after a buff status interrupt
 
   uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
-  TU_LOG(3, "_hw_endpoint_xfer_sync:\r\n");
-  print_bufctrl32(buf_ctrl);
+  TU_LOG(3, "  Sync BufCtrl: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
 
   // always sync buffer 0
   uint16_t buf0_bytes = sync_ep_buffer(ep, 0);
@@ -284,7 +281,7 @@ static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
       usb_hw->abort &= ~TU_BIT(ep_id);
 
       TU_LOG(3, "----SHORT PACKET buffer0 on EP %02X:\r\n", ep->ep_addr);
-      print_bufctrl32(buf_ctrl);
+      TU_LOG(3, "  BufCtrl: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
 #endif
     }
   }
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 5570a731a..b7bb51d1e 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -42,9 +42,6 @@ struct hw_endpoint
     // Buffer pointer in usb dpram
     uint8_t *hw_data_buf;
 
-    // Have we been stalled TODO remove later
-    bool stalled;
-
     // Current transfer information
     bool active;
     uint16_t remaining_len;
@@ -96,52 +93,4 @@ static inline uintptr_t hw_data_offset(uint8_t *buf)
 
 extern const char *ep_dir_string[];
 
-typedef union TU_ATTR_PACKED
-{
-  uint16_t u16;
-  struct TU_ATTR_PACKED
-  {
-    uint16_t xfer_len     : 10;
-    uint16_t available    : 1;
-    uint16_t stall        : 1;
-    uint16_t reset_bufsel : 1;
-    uint16_t data_toggle  : 1;
-    uint16_t last_buf     : 1;
-    uint16_t full         : 1;
-  };
-} rp2040_buffer_control_t;
-
-TU_VERIFY_STATIC(sizeof(rp2040_buffer_control_t) == 2, "size is not correct");
-
-#if CFG_TUSB_DEBUG >= 3
-static inline void print_bufctrl16(uint32_t u16)
-{
-  rp2040_buffer_control_t bufctrl = {
-      .u16 = u16
-  };
-
-  TU_LOG(3, "len = %u, available = %u, full = %u, last = %u, stall = %u, reset = %u, toggle = %u\r\n",
-         bufctrl.xfer_len, bufctrl.available, bufctrl.full, bufctrl.last_buf, bufctrl.stall, bufctrl.reset_bufsel, bufctrl.data_toggle);
-}
-
-static inline void print_bufctrl32(uint32_t u32)
-{
-  uint16_t u16;
-
-  u16 = u32 >> 16;
-  TU_LOG(3, "  Buffer Control 1 0x%x: ", u16);
-  print_bufctrl16(u16);
-
-  u16 = u32 & 0x0000ffff;
-  TU_LOG(3, "  Buffer Control 0 0x%x: ", u16);
-  print_bufctrl16(u16);
-}
-
-#else
-
-#define print_bufctrl16(u16)
-#define print_bufctrl32(u32)
-
-#endif
-
 #endif

From 15fa2f447b9187f2cef5dd5ba904449bd4c6703e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Sep 2021 16:53:12 +0700
Subject: [PATCH 0420/2085] add back edpt check before cbw, since bot reset can
 occurred any time

---
 src/class/msc/msc_device.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 7dcd4983e..6b3a392a8 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -323,7 +323,11 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         if ( p_msc->stage == MSC_STAGE_CMD )
         {
           // part of reset recovery (probably due to invalid CBW) -> prepare for new command
-          TU_ASSERT( prepare_cbw(rhport, p_msc) );
+          // Note: skip if already queued previously
+          if ( usbd_edpt_ready(rhport, p_msc->ep_out) )
+          {
+            TU_ASSERT( prepare_cbw(rhport, p_msc) );
+          }
         }
       }
     }

From 1398226bb5c141db43b4dc2dae846c96c743274d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Sep 2021 16:54:03 +0700
Subject: [PATCH 0421/2085] only attempt to clear if stalled, and stall if
 cleared

---
 src/device/usbd.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 9af9b2a6e..912bae9a8 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1333,26 +1333,33 @@ bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  TU_LOG(USBD_DBG, "    Stall EP %02X\r\n", ep_addr);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  dcd_edpt_stall(rhport, ep_addr);
-  _usbd_dev.ep_status[epnum][dir].stalled = true;
-  _usbd_dev.ep_status[epnum][dir].busy = true;
+  // only stalled if currently cleared
+  if ( !_usbd_dev.ep_status[epnum][dir].stalled )
+  {
+    TU_LOG(USBD_DBG, "    Stall EP %02X\r\n", ep_addr);
+    dcd_edpt_stall(rhport, ep_addr);
+    _usbd_dev.ep_status[epnum][dir].stalled = true;
+    _usbd_dev.ep_status[epnum][dir].busy = true;
+  }
 }
 
 void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  TU_LOG(USBD_DBG, "    Clear Stall EP %02X\r\n", ep_addr);
-
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  dcd_edpt_clear_stall(rhport, ep_addr);
-  _usbd_dev.ep_status[epnum][dir].stalled = false;
-  _usbd_dev.ep_status[epnum][dir].busy = false;
+  // only clear if currently stalled
+  if ( _usbd_dev.ep_status[epnum][dir].stalled )
+  {
+    TU_LOG(USBD_DBG, "    Clear Stall EP %02X\r\n", ep_addr);
+    dcd_edpt_clear_stall(rhport, ep_addr);
+    _usbd_dev.ep_status[epnum][dir].stalled = false;
+    _usbd_dev.ep_status[epnum][dir].busy = false;
+  }
 }
 
 bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)

From d6e9fe38beefbea787dad151dfeb3c62be96d527 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Sep 2021 19:42:40 +0700
Subject: [PATCH 0422/2085] rp2040 implement dcd_edpt_close_all()

aslo rename reset_ep0_pid() and clean up. We only need to reset pid when
setup packet received
---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 46 ++++++++++++--------
 src/portable/raspberrypi/rp2040/rp2040_usb.h |  4 +-
 2 files changed, 29 insertions(+), 21 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 42ffaf883..a710bd557 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -124,9 +124,7 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t
   // For device, IN is a tx transfer and OUT is an rx transfer
   ep->rx = (dir == TUSB_DIR_OUT);
 
-  // Response to a setup packet on EP0 starts with pid of 1
-  ep->next_pid = (num == 0 ? 1u : 0u);
-
+  ep->next_pid = 0u;
   ep->wMaxPacketSize = wMaxPacketSize;
   ep->transfer_type = transfer_type;
 
@@ -203,7 +201,7 @@ static void hw_handle_buff_status(void)
     }
 }
 
-static void reset_ep0(void)
+static void reset_ep0_pid(void)
 {
     // If we have finished this transfer on EP0 set pid back to 1 for next
     // setup transfer. Also clear a stall in case
@@ -215,14 +213,18 @@ static void reset_ep0(void)
     }
 }
 
-static void reset_all_endpoints(void)
+static void reset_non_control_endpoints(void)
 {
-  memset(hw_endpoints, 0, sizeof(hw_endpoints));
-  next_buffer_ptr = &usb_dpram->epx_data[0];
+  // Disable all non-control
+  for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS-1; i++ )
+  {
+    usb_dpram->ep_ctrl[i].in = 0;
+    usb_dpram->ep_ctrl[i].out = 0;
+  }
 
-  // Init Control endpoint out & in
-  hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL);
-  hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL);
+  // clear non-control hw endpoints
+  tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2*sizeof(hw_endpoint_t));
+  next_buffer_ptr = &usb_dpram->epx_data[0];
 }
 
 static void dcd_rp2040_irq(void)
@@ -234,8 +236,10 @@ static void dcd_rp2040_irq(void)
     {
         handled |= USB_INTS_SETUP_REQ_BITS;
         uint8_t const *setup = (uint8_t const *)&usb_dpram->setup_packet;
-        // Clear stall bits and reset pid
-        reset_ep0();
+
+        // reset pid to both 1 (data and ack)
+        reset_ep0_pid();
+
         // Pass setup packet to tiny usb
         dcd_event_setup_received(0, setup, true);
         usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS;
@@ -275,7 +279,7 @@ static void dcd_rp2040_irq(void)
         handled |= USB_INTS_BUS_RESET_BITS;
 
         usb_hw->dev_addr_ctrl = 0;
-        reset_all_endpoints();
+        reset_non_control_endpoints();
         dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
         usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
 
@@ -338,8 +342,13 @@ void dcd_init (uint8_t rhport)
 
   irq_set_exclusive_handler(USBCTRL_IRQ, dcd_rp2040_irq);
 
-  // reset endpoints
-  reset_all_endpoints();
+  // Init control endpoints
+  tu_memclr(hw_endpoints[0], 2*sizeof(hw_endpoint_t));
+  hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL);
+  hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL);
+
+  // Init non-control endpoints
+  reset_non_control_endpoints();
 
   // Initializes the USB peripheral for device mode and enables it.
   // Don't need to enable the pull up here. Force VBUS
@@ -374,7 +383,6 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 
   // Can't set device address in hardware until status xfer has complete
   // Send 0len complete response on EP0 IN
-  reset_ep0();
   hw_endpoint_xfer(0x80, NULL, 0);
 }
 
@@ -413,8 +421,6 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
   {
     usb_hw->dev_addr_ctrl = (uint8_t) request->wValue;
   }
-
-  reset_ep0();
 }
 
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
@@ -427,7 +433,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
-  // reset_all_endpoints(); TODO double check endpoint control
+
+  // may need to use EP Abort
+  reset_non_control_endpoints();
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index b7bb51d1e..a9cf1dd07 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -21,7 +21,7 @@
 #define pico_trace(...) TU_LOG(3, __VA_ARGS__)
 
 // Hardware information per endpoint
-struct hw_endpoint
+typedef struct hw_endpoint
 {
     // Is this a valid struct
     bool configured;
@@ -63,7 +63,7 @@ struct hw_endpoint
     // If interrupt endpoint
     uint8_t interrupt_num;
 #endif
-};
+} hw_endpoint_t;
 
 void rp2040_usb_init(void);
 

From d4c56c70a80a6df81f403627e897c50b0a94601e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Sep 2021 20:01:40 +0700
Subject: [PATCH 0423/2085] minor clean up

---
 src/device/usbd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 912bae9a8..a52ea9afe 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1214,7 +1214,7 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr)
 
 #if CFG_TUSB_OS != OPT_OS_NONE
   // pre-check to help reducing mutex lock
-  TU_VERIFY( (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0));
+  TU_VERIFY((_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0));
   osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 #endif
 

From 2e23f3dd7287186445aeab39108f81c51644ed77 Mon Sep 17 00:00:00 2001
From: Kamil Tomaszewski <kamil.tomaszewski@sony.com>
Date: Fri, 3 Sep 2021 18:13:45 +0200
Subject: [PATCH 0424/2085] Fix for MSC during stage STATUS

---
 src/class/msc/msc_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 6b3a392a8..71875b014 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -601,10 +601,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     // skip status if epin is currently stalled, will do it when received Clear Stall request
     if ( !usbd_edpt_stalled(rhport,  p_msc->ep_in) )
     {
-      if ( (p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir) )
+      if ( (p_msc->total_len > p_msc->xferred_len) && is_data_in(p_cbw->dir) )
       {
         // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status
-        TU_LOG(MSC_DEBUG, "  SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len);
+        TU_LOG(MSC_DEBUG, "  SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_msc->total_len, p_msc->xferred_len);
         usbd_edpt_stall(rhport, p_msc->ep_in);
       }else
       {

From 51dddf63fa617dd8da8471f485b1c28e5c9513ca Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 3 Sep 2021 18:26:39 +0200
Subject: [PATCH 0425/2085] Add IAR project connections.

---
 .../iar_audio_4_channel_mic.ipcf              | 154 +++++++++++++++++
 .../device/audio_test/iar_audio_test.ipcf     | 154 +++++++++++++++++
 .../device/board_test/iar_board_test.ipcf     | 153 +++++++++++++++++
 .../cdc_dual_ports/iar_cdc_dual_ports.ipcf    | 154 +++++++++++++++++
 examples/device/cdc_msc/iar_cdc_msc.ipcf      | 155 +++++++++++++++++
 .../iar_cdc_msc_freertos.ipcf                 | 157 ++++++++++++++++++
 examples/device/dfu/iar_dfu.ipcf              | 154 +++++++++++++++++
 .../device/dfu_runtime/iar_dfu_runtime.ipcf   | 154 +++++++++++++++++
 .../iar_dynamic_configuration.ipcf            | 155 +++++++++++++++++
 .../iar_hid_boot_interface.ipcf               | 155 +++++++++++++++++
 .../hid_composite/iar_hid_composite.ipcf      | 155 +++++++++++++++++
 .../iar_hid_composite_freertos.ipcf           | 157 ++++++++++++++++++
 .../iar_hid_generic_inout.ipcf                | 154 +++++++++++++++++
 .../iar_hid_multiple_interface.ipcf           | 154 +++++++++++++++++
 examples/device/midi_test/iar_midi_test.ipcf  | 154 +++++++++++++++++
 .../device/msc_dual_lun/iar_msc_dual_lun.ipcf | 155 +++++++++++++++++
 .../iar_net_lwip_webserver.ipcf               | 155 +++++++++++++++++
 .../device/uac2_headset/iar_uac2_headset.ipcf | 155 +++++++++++++++++
 examples/device/usbtmc/iar_usbtmc.ipcf        | 157 ++++++++++++++++++
 .../webusb_serial/iar_webusb_serial.ipcf      | 155 +++++++++++++++++
 .../host/cdc_msc_hid/iar_cdc_msc_hid.ipcf     | 155 +++++++++++++++++
 .../hid_controller/iar_hid_controller.ipcf    | 154 +++++++++++++++++
 tools/iar.ipcf                                | 147 ++++++++++++++++
 tools/iar_gen.py                              |  51 ++++++
 24 files changed, 3603 insertions(+)
 create mode 100644 examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf
 create mode 100644 examples/device/audio_test/iar_audio_test.ipcf
 create mode 100644 examples/device/board_test/iar_board_test.ipcf
 create mode 100644 examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf
 create mode 100644 examples/device/cdc_msc/iar_cdc_msc.ipcf
 create mode 100644 examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf
 create mode 100644 examples/device/dfu/iar_dfu.ipcf
 create mode 100644 examples/device/dfu_runtime/iar_dfu_runtime.ipcf
 create mode 100644 examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf
 create mode 100644 examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf
 create mode 100644 examples/device/hid_composite/iar_hid_composite.ipcf
 create mode 100644 examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf
 create mode 100644 examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf
 create mode 100644 examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf
 create mode 100644 examples/device/midi_test/iar_midi_test.ipcf
 create mode 100644 examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf
 create mode 100644 examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf
 create mode 100644 examples/device/uac2_headset/iar_uac2_headset.ipcf
 create mode 100644 examples/device/usbtmc/iar_usbtmc.ipcf
 create mode 100644 examples/device/webusb_serial/iar_webusb_serial.ipcf
 create mode 100644 examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf
 create mode 100644 examples/host/hid_controller/iar_hid_controller.ipcf
 create mode 100644 tools/iar.ipcf
 create mode 100644 tools/iar_gen.py

diff --git a/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf b/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf
new file mode 100644
index 000000000..a862b871f
--- /dev/null
+++ b/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf
@@ -0,0 +1,154 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/audio_4_channel_mic/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/audio_4_channel_mic/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/audio_4_channel_mic/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/audio_test/iar_audio_test.ipcf b/examples/device/audio_test/iar_audio_test.ipcf
new file mode 100644
index 000000000..a5fdd5350
--- /dev/null
+++ b/examples/device/audio_test/iar_audio_test.ipcf
@@ -0,0 +1,154 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/audio_test/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/audio_test/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/audio_test/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/board_test/iar_board_test.ipcf b/examples/device/board_test/iar_board_test.ipcf
new file mode 100644
index 000000000..942911640
--- /dev/null
+++ b/examples/device/board_test/iar_board_test.ipcf
@@ -0,0 +1,153 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/board_test/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/board_test/src/tusb_config.h</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf b/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf
new file mode 100644
index 000000000..69e321150
--- /dev/null
+++ b/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf
@@ -0,0 +1,154 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/cdc_dual_ports/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/cdc_dual_ports/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/cdc_dual_ports/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/cdc_msc/iar_cdc_msc.ipcf b/examples/device/cdc_msc/iar_cdc_msc.ipcf
new file mode 100644
index 000000000..7b7576e8c
--- /dev/null
+++ b/examples/device/cdc_msc/iar_cdc_msc.ipcf
@@ -0,0 +1,155 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/cdc_msc/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/msc_disk.c">$TUSB_DIR$/examples/device/cdc_msc/src/msc_disk.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/cdc_msc/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/cdc_msc/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf b/examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf
new file mode 100644
index 000000000..f1a00c391
--- /dev/null
+++ b/examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf
@@ -0,0 +1,157 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/FreeRTOSConfig.h">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h</path>
+			<path copyTo="$PROJ_DIR$/freertos_hook.c">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/freertos_hook.c</path>
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/msc_disk.c">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/msc_disk.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/dfu/iar_dfu.ipcf b/examples/device/dfu/iar_dfu.ipcf
new file mode 100644
index 000000000..d2eb2f043
--- /dev/null
+++ b/examples/device/dfu/iar_dfu.ipcf
@@ -0,0 +1,154 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/dfu/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/dfu/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/dfu/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/dfu_runtime/iar_dfu_runtime.ipcf b/examples/device/dfu_runtime/iar_dfu_runtime.ipcf
new file mode 100644
index 000000000..18ade4125
--- /dev/null
+++ b/examples/device/dfu_runtime/iar_dfu_runtime.ipcf
@@ -0,0 +1,154 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/dfu_runtime/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/dfu_runtime/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/dfu_runtime/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf b/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf
new file mode 100644
index 000000000..1185e774c
--- /dev/null
+++ b/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf
@@ -0,0 +1,155 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/dynamic_configuration/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/msc_disk.c">$TUSB_DIR$/examples/device/dynamic_configuration/src/msc_disk.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/dynamic_configuration/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/dynamic_configuration/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf b/examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf
new file mode 100644
index 000000000..4214121d0
--- /dev/null
+++ b/examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf
@@ -0,0 +1,155 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/hid_boot_interface/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/hid_boot_interface/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/hid_boot_interface/src/usb_descriptors.c</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.h">$TUSB_DIR$/examples/device/hid_boot_interface/src/usb_descriptors.h</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/hid_composite/iar_hid_composite.ipcf b/examples/device/hid_composite/iar_hid_composite.ipcf
new file mode 100644
index 000000000..a2c5c9855
--- /dev/null
+++ b/examples/device/hid_composite/iar_hid_composite.ipcf
@@ -0,0 +1,155 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/hid_composite/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/hid_composite/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/hid_composite/src/usb_descriptors.c</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.h">$TUSB_DIR$/examples/device/hid_composite/src/usb_descriptors.h</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf b/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf
new file mode 100644
index 000000000..eabff34f5
--- /dev/null
+++ b/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf
@@ -0,0 +1,157 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/FreeRTOSConfig.h">$TUSB_DIR$/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h</path>
+			<path copyTo="$PROJ_DIR$/freertos_hook.c">$TUSB_DIR$/examples/device/hid_composite_freertos/src/freertos_hook.c</path>
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/hid_composite_freertos/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/hid_composite_freertos/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/hid_composite_freertos/src/usb_descriptors.c</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.h">$TUSB_DIR$/examples/device/hid_composite_freertos/src/usb_descriptors.h</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf b/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf
new file mode 100644
index 000000000..d917fa956
--- /dev/null
+++ b/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf
@@ -0,0 +1,154 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/hid_generic_inout/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/hid_generic_inout/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/hid_generic_inout/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf b/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf
new file mode 100644
index 000000000..f50f39616
--- /dev/null
+++ b/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf
@@ -0,0 +1,154 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/hid_multiple_interface/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/hid_multiple_interface/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/hid_multiple_interface/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/midi_test/iar_midi_test.ipcf b/examples/device/midi_test/iar_midi_test.ipcf
new file mode 100644
index 000000000..f8ab96a1f
--- /dev/null
+++ b/examples/device/midi_test/iar_midi_test.ipcf
@@ -0,0 +1,154 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/midi_test/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/midi_test/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/midi_test/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf b/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf
new file mode 100644
index 000000000..257230891
--- /dev/null
+++ b/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf
@@ -0,0 +1,155 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/msc_dual_lun/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/msc_disk_dual.c">$TUSB_DIR$/examples/device/msc_dual_lun/src/msc_disk_dual.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/msc_dual_lun/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/msc_dual_lun/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf b/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf
new file mode 100644
index 000000000..1fb5b1eac
--- /dev/null
+++ b/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf
@@ -0,0 +1,155 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/lwipopts.h">$TUSB_DIR$/examples/device/net_lwip_webserver/src/lwipopts.h</path>
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/net_lwip_webserver/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/net_lwip_webserver/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/net_lwip_webserver/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/uac2_headset/iar_uac2_headset.ipcf b/examples/device/uac2_headset/iar_uac2_headset.ipcf
new file mode 100644
index 000000000..1d1b9b88c
--- /dev/null
+++ b/examples/device/uac2_headset/iar_uac2_headset.ipcf
@@ -0,0 +1,155 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/uac2_headset/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/uac2_headset/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/uac2_headset/src/usb_descriptors.c</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.h">$TUSB_DIR$/examples/device/uac2_headset/src/usb_descriptors.h</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/usbtmc/iar_usbtmc.ipcf b/examples/device/usbtmc/iar_usbtmc.ipcf
new file mode 100644
index 000000000..20a6f954a
--- /dev/null
+++ b/examples/device/usbtmc/iar_usbtmc.ipcf
@@ -0,0 +1,157 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/usbtmc/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/main.h">$TUSB_DIR$/examples/device/usbtmc/src/main.h</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/usbtmc/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usbtmc_app.c">$TUSB_DIR$/examples/device/usbtmc/src/usbtmc_app.c</path>
+			<path copyTo="$PROJ_DIR$/usbtmc_app.h">$TUSB_DIR$/examples/device/usbtmc/src/usbtmc_app.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/usbtmc/src/usb_descriptors.c</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/webusb_serial/iar_webusb_serial.ipcf b/examples/device/webusb_serial/iar_webusb_serial.ipcf
new file mode 100644
index 000000000..391b21451
--- /dev/null
+++ b/examples/device/webusb_serial/iar_webusb_serial.ipcf
@@ -0,0 +1,155 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/webusb_serial/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/webusb_serial/src/tusb_config.h</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/webusb_serial/src/usb_descriptors.c</path>
+			<path copyTo="$PROJ_DIR$/usb_descriptors.h">$TUSB_DIR$/examples/device/webusb_serial/src/usb_descriptors.h</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf b/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf
new file mode 100644
index 000000000..c3d48b369
--- /dev/null
+++ b/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf
@@ -0,0 +1,155 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/hid_app.c">$TUSB_DIR$/examples/host/cdc_msc_hid/src/hid_app.c</path>
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/host/cdc_msc_hid/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/msc_app.c">$TUSB_DIR$/examples/host/cdc_msc_hid/src/msc_app.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/host/cdc_msc_hid/src/tusb_config.h</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/host/hid_controller/iar_hid_controller.ipcf b/examples/host/hid_controller/iar_hid_controller.ipcf
new file mode 100644
index 000000000..b3ce73a91
--- /dev/null
+++ b/examples/host/hid_controller/iar_hid_controller.ipcf
@@ -0,0 +1,154 @@
+<?xml version="1.0" ?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+		<path>$PROJ_DIR$</path>
+		<path>$TUSB_DIR$/hw</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+		<group name="src">
+			<path>$TUSB_DIR$/src/tusb.c</path>
+		</group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+		<group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+		<group name="bsp">
+			<path>$TUSB_DIR$/hw/bsp/board.c</path>
+		</group>
+		<group name="example">
+			<path copyTo="$PROJ_DIR$/hid_app.c">$TUSB_DIR$/examples/host/hid_controller/src/hid_app.c</path>
+			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/host/hid_controller/src/main.c</path>
+			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/host/hid_controller/src/tusb_config.h</path>
+		</group>
+	</files>
+</iarProjectConnection>
\ No newline at end of file
diff --git a/tools/iar.ipcf b/tools/iar.ipcf
new file mode 100644
index 000000000..b8e50a1d2
--- /dev/null
+++ b/tools/iar.ipcf
@@ -0,0 +1,147 @@
+<?xml version="1.0"?>
+<iarProjectConnection name="tinyusb" oneShot="true">
+
+	<includePath>
+		<path>$TUSB_DIR$/src</path>
+        <path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+        <path>$PROJ_DIR$</path>
+	</includePath>
+	<files>
+		<group name="src/device">
+			<path>$TUSB_DIR$/src/device/usbd.c</path>
+			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
+		</group>
+		<group name="src/common">
+			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+		</group>
+		<group name="src/class/audio">
+			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+		</group>
+		<group name="src/class/bth">
+			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+		</group>
+		<group name="src/class/cdc">
+			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+		</group>
+		<group name="src/class/dfu">
+			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+		</group>
+		<group name="src/class/hid">
+			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+		</group>
+		<group name="src/class/midi">
+			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+		</group>
+		<group name="src/class/msc">
+			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+		</group>
+		<group name="src/class/net">
+			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+		</group>
+		<group name="src/class/usbtmc">
+			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+		</group>
+		<group name="src/class/vendor">
+			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+		</group>
+        <group name="src">
+            <path>$TUSB_DIR$/src/tusb.c</path>
+        </group>
+		<group name="src/host">
+			<path>$TUSB_DIR$/src/host/hub.c</path>
+			<path>$TUSB_DIR$/src/host/usbh.c</path>
+			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/dialog/da146xx">
+			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+		</group>
+		<group name="src/portable/ehci">
+			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+		</group>
+		<group name="src/portable/espressif/esp32sx">
+			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
+		</group>
+		<group name="src/portable/microchip/samd">
+			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+		</group>
+		<group name="src/portable/microchip/samg">
+			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+		</group>
+		<group name="src/portable/microchip/samx7x">
+			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+		</group>
+		<group name="src/portable/mindmotion/mm32">
+			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+		</group>
+		<group name="src/portable/nordic/nrf5x">
+			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc120">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc121">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+		</group>
+		<group name="src/portable/nuvoton/nuc505">
+			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+		</group>
+		<group name="src/portable/nxp/khci">
+			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc17_40">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+		</group>
+		<group name="src/portable/nxp/lpc_ip3511">
+			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+		</group>
+		<group name="src/portable/nxp/transdimension">
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
+		</group>
+		<group name="src/portable/ohci">
+			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+		</group>
+		<group name="src/portable/raspberrypi/rp2040">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+		</group>
+		<group name="src/portable/renesas/usba">
+			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		</group>
+		<group name="src/portable/silabs/efm32">
+			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
+		</group>
+		<group name="src/portable/sony/cxd56">
+			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+		</group>
+		<group name="src/portable/st/stm32_fsdev">
+			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/template">
+			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
+		</group>
+		<group name="src/portable/ti/msp430x5xx">
+			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+		</group>
+		<group name="src/portable/valentyusb/eptri">
+			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+		</group>
+        <group name="lib/SEGGER_RTT">
+			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+            <path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
+            <path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
+		</group>
+    </files>
+    
+</iarProjectConnection>
diff --git a/tools/iar_gen.py b/tools/iar_gen.py
new file mode 100644
index 000000000..b8c270ff7
--- /dev/null
+++ b/tools/iar_gen.py
@@ -0,0 +1,51 @@
+#!/usr/bin/python3
+
+import os
+import xml.dom.minidom as XML
+
+# Read base configuration
+base = ""
+with open("iar.ipcf") as f:
+    base = f.read()
+
+# Enumerate all device/host examples
+dir_1 = os.listdir("../examples")
+for dir_2 in dir_1:
+    if os.path.isdir("../examples/{}".format(dir_2)):
+        print(dir_2)
+        examples = os.listdir("../examples/{}".format(dir_2))
+        for example in examples:
+            if os.path.isdir("../examples/{}/{}".format(dir_2, example)):
+                print("../examples/{}/{}".format(dir_2, example))
+                conf = XML.parseString(base)
+                files = conf.getElementsByTagName("files")[0]
+                inc   = conf.getElementsByTagName("includePath")[0]
+                # Add bsp inc
+                path = conf.createElement('path')
+                path_txt = conf.createTextNode("$TUSB_DIR$/hw")
+                path.appendChild(path_txt)
+                inc.appendChild(path)
+                # Add board.c/.h
+                grp = conf.createElement('group')
+                grp.setAttribute("name", "bsp")
+                path = conf.createElement('path')
+                path_txt = conf.createTextNode("$TUSB_DIR$/hw/bsp/board.c")
+                path.appendChild(path_txt)
+                grp.appendChild(path)
+                files.appendChild(grp)
+                # Add example's .c/.h
+                grp = conf.createElement('group')
+                grp.setAttribute("name", "example")
+                for file in os.listdir("../examples/{}/{}/src".format(dir_2, example)):
+                    if file.endswith(".c") or file.endswith(".h"):
+                        path = conf.createElement('path')
+                        path.setAttribute("copyTo", "$PROJ_DIR$/{}".format(file))
+                        path_txt = conf.createTextNode("$TUSB_DIR$/examples/{0}/{1}/src/{2}".format(dir_2, example, file))
+                        path.appendChild(path_txt)
+                        grp.appendChild(path)
+                files.appendChild(grp)
+                cfg_str = conf.toprettyxml()
+                cfg_str = '\n'.join([s for s in cfg_str.splitlines() if s.strip()])
+                #print(cfg_str)
+                with open("../examples/{0}/{1}/iar_{1}.ipcf".format(dir_2, example), 'w') as f:
+                    f.write(cfg_str)

From fa030075c228390741e450664506892d317c0038 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Sep 2021 19:26:28 +0700
Subject: [PATCH 0426/2085] Revert "Fix for MSC during stage STATUS"

This reverts commit 2e23f3dd7287186445aeab39108f81c51644ed77.
---
 src/class/msc/msc_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 71875b014..6b3a392a8 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -601,10 +601,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     // skip status if epin is currently stalled, will do it when received Clear Stall request
     if ( !usbd_edpt_stalled(rhport,  p_msc->ep_in) )
     {
-      if ( (p_msc->total_len > p_msc->xferred_len) && is_data_in(p_cbw->dir) )
+      if ( (p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir) )
       {
         // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status
-        TU_LOG(MSC_DEBUG, "  SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_msc->total_len, p_msc->xferred_len);
+        TU_LOG(MSC_DEBUG, "  SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len);
         usbd_edpt_stall(rhport, p_msc->ep_in);
       }else
       {

From c53ce53058fc4d2cd7928836cdc2a83615287f3e Mon Sep 17 00:00:00 2001
From: Christian Arlt <arlt_c@arcor.de>
Date: Mon, 6 Sep 2021 19:38:31 +0200
Subject: [PATCH 0427/2085] Added Sony DualShock4 CUH-ZCT1E pid

---
 examples/host/hid_controller/src/hid_app.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index c61ce70f3..ce084dc85 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -111,7 +111,7 @@ static inline bool is_sony_ds4(uint8_t dev_addr)
   uint16_t vid, pid;
   tuh_vid_pid_get(dev_addr, &vid, &pid);
 
-  return (vid == 0x054c && pid == 0x09cc);
+  return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) ); // Sony DualShock4 
 }
 
 //--------------------------------------------------------------------+

From a0646f20ba515185ec12d9da4ff5954f2db8bef2 Mon Sep 17 00:00:00 2001
From: Christian Arlt <arlt_c@arcor.de>
Date: Mon, 6 Sep 2021 19:40:14 +0200
Subject: [PATCH 0428/2085] Added Hori Fighting Commander 4 VID PID

---
 examples/host/hid_controller/src/hid_app.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index ce084dc85..c9bd6a722 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -111,7 +111,9 @@ static inline bool is_sony_ds4(uint8_t dev_addr)
   uint16_t vid, pid;
   tuh_vid_pid_get(dev_addr, &vid, &pid);
 
-  return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) ); // Sony DualShock4 
+  return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4 
+           || (vid == 0x0f0d && pid == 0x005e)                 // Hori FC4 
+         );
 }
 
 //--------------------------------------------------------------------+

From cc08bb6f994f9d5d004d786835809cc1d998205d Mon Sep 17 00:00:00 2001
From: Christian Arlt <arlt_c@arcor.de>
Date: Mon, 6 Sep 2021 19:41:09 +0200
Subject: [PATCH 0429/2085] Added Arc System Works GG Xrd Limited Edition
 controller VID PID

---
 examples/host/hid_controller/src/hid_app.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index c9bd6a722..d88c74ac4 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -113,6 +113,7 @@ static inline bool is_sony_ds4(uint8_t dev_addr)
 
   return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4 
            || (vid == 0x0f0d && pid == 0x005e)                 // Hori FC4 
+           || (vid == 0x1f4f && pid == 0x1002)                 // ASW GG xrd controller
          );
 }
 

From f47e5402fa928c5a0cd581c894e9e18c3dfcbdfb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 7 Sep 2021 13:30:51 +0700
Subject: [PATCH 0430/2085] add msc workaround for cxd56

---
 examples/make.mk           |  1 +
 hw/bsp/spresense/board.mk  |  3 ++-
 src/class/msc/msc_device.c | 11 +++++++++++
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/examples/make.mk b/examples/make.mk
index 9daf60e35..24f8c5572 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -61,6 +61,7 @@ GDB = $(CROSS_COMPILE)gdb
 OBJCOPY = $(CROSS_COMPILE)objcopy
 SIZE = $(CROSS_COMPILE)size
 MKDIR = mkdir
+PYTHON = python
 
 ifeq ($(CMDEXE),1)
   CP = copy
diff --git a/hw/bsp/spresense/board.mk b/hw/bsp/spresense/board.mk
index a46c42bd6..ba291e817 100644
--- a/hw/bsp/spresense/board.mk
+++ b/hw/bsp/spresense/board.mk
@@ -70,4 +70,5 @@ $(BUILD)/$(PROJECT).spk: $(MKSPK)
 
 # flash
 flash: $(BUILD)/$(PROJECT).spk
-	@$(TOP)/hw/mcu/sony/cxd56/tools/flash_writer.py -s -c $(SERIAL) -d -b 115200 -n $<
+	@echo FLASH $<
+	@$(PYTHON) $(TOP)/hw/mcu/sony/cxd56/tools/flash_writer.py -s -c $(SERIAL) -d -b 115200 -n $<
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 6b3a392a8..0fd592129 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -611,6 +611,17 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         TU_ASSERT( send_csw(rhport, p_msc) );
       }
     }
+
+    #if TU_CHECK_MCU(CXD56)
+    // WORKAROUND: cxd56 has its own nuttx usb stack which does not forward Set/ClearFeature(Endpoint) to DCD.
+    // There is no way for us to know when EP is un-stall, therefore we will unconditionally un-stall here and
+    // hope everything will work
+    if ( usbd_edpt_stalled(rhport, p_msc->ep_in) )
+    {
+      usbd_edpt_clear_stall(rhport, p_msc->ep_in);
+      send_csw(rhport, p_msc);
+    }
+    #endif
   }
 
   return true;

From f735ee4f3618d14511416310f12bd087d8c1f59c Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 7 Sep 2021 11:25:35 +0200
Subject: [PATCH 0431/2085] Remove ipcf of examples.

---
 .../iar_audio_4_channel_mic.ipcf              | 154 -----------------
 .../device/audio_test/iar_audio_test.ipcf     | 154 -----------------
 .../device/board_test/iar_board_test.ipcf     | 153 -----------------
 .../cdc_dual_ports/iar_cdc_dual_ports.ipcf    | 154 -----------------
 examples/device/cdc_msc/iar_cdc_msc.ipcf      | 155 -----------------
 .../iar_cdc_msc_freertos.ipcf                 | 157 ------------------
 examples/device/dfu/iar_dfu.ipcf              | 154 -----------------
 .../device/dfu_runtime/iar_dfu_runtime.ipcf   | 154 -----------------
 .../iar_dynamic_configuration.ipcf            | 155 -----------------
 .../iar_hid_boot_interface.ipcf               | 155 -----------------
 .../hid_composite/iar_hid_composite.ipcf      | 155 -----------------
 .../iar_hid_composite_freertos.ipcf           | 157 ------------------
 .../iar_hid_generic_inout.ipcf                | 154 -----------------
 .../iar_hid_multiple_interface.ipcf           | 154 -----------------
 examples/device/midi_test/iar_midi_test.ipcf  | 154 -----------------
 .../device/msc_dual_lun/iar_msc_dual_lun.ipcf | 155 -----------------
 .../iar_net_lwip_webserver.ipcf               | 155 -----------------
 .../device/uac2_headset/iar_uac2_headset.ipcf | 155 -----------------
 examples/device/usbtmc/iar_usbtmc.ipcf        | 157 ------------------
 .../webusb_serial/iar_webusb_serial.ipcf      | 155 -----------------
 .../host/cdc_msc_hid/iar_cdc_msc_hid.ipcf     | 155 -----------------
 .../hid_controller/iar_hid_controller.ipcf    | 154 -----------------
 22 files changed, 3405 deletions(-)
 delete mode 100644 examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf
 delete mode 100644 examples/device/audio_test/iar_audio_test.ipcf
 delete mode 100644 examples/device/board_test/iar_board_test.ipcf
 delete mode 100644 examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf
 delete mode 100644 examples/device/cdc_msc/iar_cdc_msc.ipcf
 delete mode 100644 examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf
 delete mode 100644 examples/device/dfu/iar_dfu.ipcf
 delete mode 100644 examples/device/dfu_runtime/iar_dfu_runtime.ipcf
 delete mode 100644 examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf
 delete mode 100644 examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf
 delete mode 100644 examples/device/hid_composite/iar_hid_composite.ipcf
 delete mode 100644 examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf
 delete mode 100644 examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf
 delete mode 100644 examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf
 delete mode 100644 examples/device/midi_test/iar_midi_test.ipcf
 delete mode 100644 examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf
 delete mode 100644 examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf
 delete mode 100644 examples/device/uac2_headset/iar_uac2_headset.ipcf
 delete mode 100644 examples/device/usbtmc/iar_usbtmc.ipcf
 delete mode 100644 examples/device/webusb_serial/iar_webusb_serial.ipcf
 delete mode 100644 examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf
 delete mode 100644 examples/host/hid_controller/iar_hid_controller.ipcf

diff --git a/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf b/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf
deleted file mode 100644
index a862b871f..000000000
--- a/examples/device/audio_4_channel_mic/iar_audio_4_channel_mic.ipcf
+++ /dev/null
@@ -1,154 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/audio_4_channel_mic/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/audio_4_channel_mic/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/audio_4_channel_mic/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/audio_test/iar_audio_test.ipcf b/examples/device/audio_test/iar_audio_test.ipcf
deleted file mode 100644
index a5fdd5350..000000000
--- a/examples/device/audio_test/iar_audio_test.ipcf
+++ /dev/null
@@ -1,154 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/audio_test/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/audio_test/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/audio_test/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/board_test/iar_board_test.ipcf b/examples/device/board_test/iar_board_test.ipcf
deleted file mode 100644
index 942911640..000000000
--- a/examples/device/board_test/iar_board_test.ipcf
+++ /dev/null
@@ -1,153 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/board_test/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/board_test/src/tusb_config.h</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf b/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf
deleted file mode 100644
index 69e321150..000000000
--- a/examples/device/cdc_dual_ports/iar_cdc_dual_ports.ipcf
+++ /dev/null
@@ -1,154 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/cdc_dual_ports/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/cdc_dual_ports/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/cdc_dual_ports/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/cdc_msc/iar_cdc_msc.ipcf b/examples/device/cdc_msc/iar_cdc_msc.ipcf
deleted file mode 100644
index 7b7576e8c..000000000
--- a/examples/device/cdc_msc/iar_cdc_msc.ipcf
+++ /dev/null
@@ -1,155 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/cdc_msc/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/msc_disk.c">$TUSB_DIR$/examples/device/cdc_msc/src/msc_disk.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/cdc_msc/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/cdc_msc/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf b/examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf
deleted file mode 100644
index f1a00c391..000000000
--- a/examples/device/cdc_msc_freertos/iar_cdc_msc_freertos.ipcf
+++ /dev/null
@@ -1,157 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/FreeRTOSConfig.h">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h</path>
-			<path copyTo="$PROJ_DIR$/freertos_hook.c">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/freertos_hook.c</path>
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/msc_disk.c">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/msc_disk.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/cdc_msc_freertos/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/dfu/iar_dfu.ipcf b/examples/device/dfu/iar_dfu.ipcf
deleted file mode 100644
index d2eb2f043..000000000
--- a/examples/device/dfu/iar_dfu.ipcf
+++ /dev/null
@@ -1,154 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/dfu/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/dfu/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/dfu/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/dfu_runtime/iar_dfu_runtime.ipcf b/examples/device/dfu_runtime/iar_dfu_runtime.ipcf
deleted file mode 100644
index 18ade4125..000000000
--- a/examples/device/dfu_runtime/iar_dfu_runtime.ipcf
+++ /dev/null
@@ -1,154 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/dfu_runtime/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/dfu_runtime/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/dfu_runtime/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf b/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf
deleted file mode 100644
index 1185e774c..000000000
--- a/examples/device/dynamic_configuration/iar_dynamic_configuration.ipcf
+++ /dev/null
@@ -1,155 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/dynamic_configuration/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/msc_disk.c">$TUSB_DIR$/examples/device/dynamic_configuration/src/msc_disk.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/dynamic_configuration/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/dynamic_configuration/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf b/examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf
deleted file mode 100644
index 4214121d0..000000000
--- a/examples/device/hid_boot_interface/iar_hid_boot_interface.ipcf
+++ /dev/null
@@ -1,155 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/hid_boot_interface/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/hid_boot_interface/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/hid_boot_interface/src/usb_descriptors.c</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.h">$TUSB_DIR$/examples/device/hid_boot_interface/src/usb_descriptors.h</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/hid_composite/iar_hid_composite.ipcf b/examples/device/hid_composite/iar_hid_composite.ipcf
deleted file mode 100644
index a2c5c9855..000000000
--- a/examples/device/hid_composite/iar_hid_composite.ipcf
+++ /dev/null
@@ -1,155 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/hid_composite/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/hid_composite/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/hid_composite/src/usb_descriptors.c</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.h">$TUSB_DIR$/examples/device/hid_composite/src/usb_descriptors.h</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf b/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf
deleted file mode 100644
index eabff34f5..000000000
--- a/examples/device/hid_composite_freertos/iar_hid_composite_freertos.ipcf
+++ /dev/null
@@ -1,157 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/FreeRTOSConfig.h">$TUSB_DIR$/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h</path>
-			<path copyTo="$PROJ_DIR$/freertos_hook.c">$TUSB_DIR$/examples/device/hid_composite_freertos/src/freertos_hook.c</path>
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/hid_composite_freertos/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/hid_composite_freertos/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/hid_composite_freertos/src/usb_descriptors.c</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.h">$TUSB_DIR$/examples/device/hid_composite_freertos/src/usb_descriptors.h</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf b/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf
deleted file mode 100644
index d917fa956..000000000
--- a/examples/device/hid_generic_inout/iar_hid_generic_inout.ipcf
+++ /dev/null
@@ -1,154 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/hid_generic_inout/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/hid_generic_inout/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/hid_generic_inout/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf b/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf
deleted file mode 100644
index f50f39616..000000000
--- a/examples/device/hid_multiple_interface/iar_hid_multiple_interface.ipcf
+++ /dev/null
@@ -1,154 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/hid_multiple_interface/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/hid_multiple_interface/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/hid_multiple_interface/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/midi_test/iar_midi_test.ipcf b/examples/device/midi_test/iar_midi_test.ipcf
deleted file mode 100644
index f8ab96a1f..000000000
--- a/examples/device/midi_test/iar_midi_test.ipcf
+++ /dev/null
@@ -1,154 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/midi_test/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/midi_test/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/midi_test/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf b/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf
deleted file mode 100644
index 257230891..000000000
--- a/examples/device/msc_dual_lun/iar_msc_dual_lun.ipcf
+++ /dev/null
@@ -1,155 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/msc_dual_lun/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/msc_disk_dual.c">$TUSB_DIR$/examples/device/msc_dual_lun/src/msc_disk_dual.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/msc_dual_lun/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/msc_dual_lun/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf b/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf
deleted file mode 100644
index 1fb5b1eac..000000000
--- a/examples/device/net_lwip_webserver/iar_net_lwip_webserver.ipcf
+++ /dev/null
@@ -1,155 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/lwipopts.h">$TUSB_DIR$/examples/device/net_lwip_webserver/src/lwipopts.h</path>
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/net_lwip_webserver/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/net_lwip_webserver/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/net_lwip_webserver/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/uac2_headset/iar_uac2_headset.ipcf b/examples/device/uac2_headset/iar_uac2_headset.ipcf
deleted file mode 100644
index 1d1b9b88c..000000000
--- a/examples/device/uac2_headset/iar_uac2_headset.ipcf
+++ /dev/null
@@ -1,155 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/uac2_headset/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/uac2_headset/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/uac2_headset/src/usb_descriptors.c</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.h">$TUSB_DIR$/examples/device/uac2_headset/src/usb_descriptors.h</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/usbtmc/iar_usbtmc.ipcf b/examples/device/usbtmc/iar_usbtmc.ipcf
deleted file mode 100644
index 20a6f954a..000000000
--- a/examples/device/usbtmc/iar_usbtmc.ipcf
+++ /dev/null
@@ -1,157 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/usbtmc/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/main.h">$TUSB_DIR$/examples/device/usbtmc/src/main.h</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/usbtmc/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usbtmc_app.c">$TUSB_DIR$/examples/device/usbtmc/src/usbtmc_app.c</path>
-			<path copyTo="$PROJ_DIR$/usbtmc_app.h">$TUSB_DIR$/examples/device/usbtmc/src/usbtmc_app.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/usbtmc/src/usb_descriptors.c</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/device/webusb_serial/iar_webusb_serial.ipcf b/examples/device/webusb_serial/iar_webusb_serial.ipcf
deleted file mode 100644
index 391b21451..000000000
--- a/examples/device/webusb_serial/iar_webusb_serial.ipcf
+++ /dev/null
@@ -1,155 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/device/webusb_serial/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/device/webusb_serial/src/tusb_config.h</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.c">$TUSB_DIR$/examples/device/webusb_serial/src/usb_descriptors.c</path>
-			<path copyTo="$PROJ_DIR$/usb_descriptors.h">$TUSB_DIR$/examples/device/webusb_serial/src/usb_descriptors.h</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf b/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf
deleted file mode 100644
index c3d48b369..000000000
--- a/examples/host/cdc_msc_hid/iar_cdc_msc_hid.ipcf
+++ /dev/null
@@ -1,155 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/hid_app.c">$TUSB_DIR$/examples/host/cdc_msc_hid/src/hid_app.c</path>
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/host/cdc_msc_hid/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/msc_app.c">$TUSB_DIR$/examples/host/cdc_msc_hid/src/msc_app.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/host/cdc_msc_hid/src/tusb_config.h</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file
diff --git a/examples/host/hid_controller/iar_hid_controller.ipcf b/examples/host/hid_controller/iar_hid_controller.ipcf
deleted file mode 100644
index b3ce73a91..000000000
--- a/examples/host/hid_controller/iar_hid_controller.ipcf
+++ /dev/null
@@ -1,154 +0,0 @@
-<?xml version="1.0" ?>
-<iarProjectConnection name="tinyusb" oneShot="true">
-	<includePath>
-		<path>$TUSB_DIR$/src</path>
-		<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
-		<path>$PROJ_DIR$</path>
-		<path>$TUSB_DIR$/hw</path>
-	</includePath>
-	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
-		<group name="src">
-			<path>$TUSB_DIR$/src/tusb.c</path>
-		</group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
-		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
-		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
-		<group name="bsp">
-			<path>$TUSB_DIR$/hw/bsp/board.c</path>
-		</group>
-		<group name="example">
-			<path copyTo="$PROJ_DIR$/hid_app.c">$TUSB_DIR$/examples/host/hid_controller/src/hid_app.c</path>
-			<path copyTo="$PROJ_DIR$/main.c">$TUSB_DIR$/examples/host/hid_controller/src/main.c</path>
-			<path copyTo="$PROJ_DIR$/tusb_config.h">$TUSB_DIR$/examples/host/hid_controller/src/tusb_config.h</path>
-		</group>
-	</files>
-</iarProjectConnection>
\ No newline at end of file

From a754205acb391b7605c835657c22c0a6c155c28e Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 7 Sep 2021 12:32:17 +0200
Subject: [PATCH 0432/2085] Rename iar.ipcf to iar_template.ipcf

---
 tools/iar_gen.py                      | 2 +-
 tools/{iar.ipcf => iar_template.ipcf} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename tools/{iar.ipcf => iar_template.ipcf} (100%)

diff --git a/tools/iar_gen.py b/tools/iar_gen.py
index b8c270ff7..73c8b29fc 100644
--- a/tools/iar_gen.py
+++ b/tools/iar_gen.py
@@ -5,7 +5,7 @@ import xml.dom.minidom as XML
 
 # Read base configuration
 base = ""
-with open("iar.ipcf") as f:
+with open("iar_template.ipcf") as f:
     base = f.read()
 
 # Enumerate all device/host examples
diff --git a/tools/iar.ipcf b/tools/iar_template.ipcf
similarity index 100%
rename from tools/iar.ipcf
rename to tools/iar_template.ipcf

From b6cda41dafe51dd7d7a28c8b9473929bfe36c933 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 7 Sep 2021 12:32:27 +0200
Subject: [PATCH 0433/2085] Add doc for IAR.

---
 docs/reference/getting_started.rst | 36 ++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index 5f3227927..be2e1b5ea 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -151,3 +151,39 @@ Some board use uf2 bootloader for drag & drop in to mass storage device, uf2 can
 .. code-block::
 
    $ make BOARD=feather_nrf52840_express all uf2
+
+IAR Support
+-----------
+
+IAR Project Connection files are provided to import TinyUSB stack into your project.
+
+* A buldable project of your MCU need to be created in advance.
+
+
+  * Take example of STM32F0:
+  
+    -  You need `stm32l0xx.h`, `startup_stm32f0xx.s`, `system_stm32f0xx.c`.
+
+    - `STM32L0xx_HAL_Driver` is only needed to run examples, TinyUSB stack itself doesn't rely on MCU's SDKs.
+
+* Open `Tools -> Configure Custom Argument Variables` (Switch to `Global` tab if you want to do it for all your projects) 
+   Click `New Group ...`, name it to `TUSB`, Click `Add Variable ...`, name it to `TUSB_DIR`, change it's value to the path of your TinyUSB stack,
+   for example `C:\\tinyusb`
+
+Import stack only
+^^^^^^^^^^^^^^^^^
+
+1. Open `Project -> Add project Connection ...`, click `OK`, choose `tinyusb\\tools\\iar_template.ipcf`.
+
+Run examples
+^^^^^^^^^^^^
+
+1. (Python3 is needed) Run `iar_gen.py` to generate .ipcf files of examples:
+
+   .. code-block::
+
+     cd C:\tinyusb\tools
+     python iar_gen.py
+
+2. Open `Project -> Add project Connection ...`, click `OK`, choose `tinyusb\\examples\\(.ipcf of example)`.
+   For example `C:\\tinyusb\\examples\\device\\cdc_msc\\iar_cdc_msc.ipcf`

From 785cdf67f0e03a456fd2dfad7b769b094f7e07ce Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 7 Sep 2021 17:43:45 +0700
Subject: [PATCH 0434/2085] default PYTHON to python3 on linux, and python on
 windows

---
 examples/make.mk | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/examples/make.mk b/examples/make.mk
index 24f8c5572..c894d35f4 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -61,15 +61,16 @@ GDB = $(CROSS_COMPILE)gdb
 OBJCOPY = $(CROSS_COMPILE)objcopy
 SIZE = $(CROSS_COMPILE)size
 MKDIR = mkdir
-PYTHON = python
 
 ifeq ($(CMDEXE),1)
   CP = copy
   RM = del
+  PYTHON = python
 else
   SED = sed
   CP = cp
   RM = rm
+  PYTHON = python3
 endif
 
 #-------------- Source files and compiler flags --------------

From e06a632b72aa926473375a2ed97d142196429d7f Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 28 Aug 2021 23:55:41 +0900
Subject: [PATCH 0435/2085] Update Renesas RX

---
 docs/reference/supported.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 4c7d753c2..d114d8405 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -84,9 +84,9 @@ Supported MCUs
 +--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
 | Raspberry Pi | RP2040             | |:green_square:|  | |:x:|              | |:green_square:|  |                   |              |
 +--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| Renesas      | RX63N              |                   |                    |                   |                   |              |
+| Renesas      | RX63N              | |:green_square:|  |                    | |:green_square:|  | |:x:|             |              |
 |              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | RX65N              |                   |                    |                   |                   |              |
+|              | RX65N              | |:green_square:|  |                    | |:green_square:|  | |:x:|             |              |
 +--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
 | Silabs       | EFM32GG12          | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             | #750         |
 +--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+

From f3da48d46adac415846985643c1b6d04c3866b94 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Tue, 31 Aug 2021 00:14:39 +0900
Subject: [PATCH 0436/2085] Implement dcd_edpt_close_all() for Renesas RX
 family

---
 src/portable/renesas/usba/dcd_usba.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index a837b5724..8e2e3dc26 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -733,10 +733,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   return true;
 }
 
-void dcd_edpt_close_all (uint8_t rhport)
+void dcd_edpt_close_all(uint8_t rhport)
 {
-  (void) rhport;
-  // TODO implement dcd_edpt_close_all()
+  unsigned i = TU_ARRAY_SIZE(_dcd.pipe);
+  dcd_int_disable(rhport);
+  while (--i) { /* Close all pipes except 0 */
+    const unsigned ep_addr = _dcd.pipe[i].ep;
+    if (!ep_addr) continue;
+    dcd_edpt_close(rhport, ep_addr);
+  }
+  dcd_int_enable(rhport);
 }
 
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)

From a54a974fa58c3c863ea6855ac911cecffb2afc04 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 7 Sep 2021 23:02:57 +0700
Subject: [PATCH 0437/2085] make synopsys usbcv compliance

- implement dcd_edpt_close_all()
- reset dtoggle when open endpoint
- correct dev interrupt mask on bus reset
---
 src/portable/st/synopsys/dcd_synopsys.c | 63 +++++++++++++++----------
 1 file changed, 38 insertions(+), 25 deletions(-)

diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index fe165e830..93bbaf23b 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -213,17 +213,18 @@ static void bus_reset(uint8_t rhport)
   tu_memclr(xfer_status, sizeof(xfer_status));
   _out_ep_closed = false;
 
+  // clear device address
+  dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
+
+  // 1. NAK for all OUT endpoints
   for(uint8_t n = 0; n < EP_MAX; n++) {
     out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
   }
 
-  // clear device address
-  dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
-
-  // TODO should probably assign value when reset rather than OR
-  dev->DAINTMSK |= (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
-  dev->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
-  dev->DIEPMSK |= USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
+  // 2. Un-mask interrupt bits
+  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
+  dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
+  dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
 
   // "USB Data FIFOs" section in reference manual
   // Peripheral FIFO architecture
@@ -307,8 +308,6 @@ static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed)
     // Turnaround timeout depends on the MCU clock
     uint32_t turnaround;
 
-    TU_LOG_INT(2, SystemCoreClock);
-
     if ( SystemCoreClock >= 32000000U )
       turnaround = 0x6U;
     else if ( SystemCoreClock >= 27500000U )
@@ -618,8 +617,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
       usb_otg->GRXFSIZ = sz;
     }
 
-    out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) |
-        (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) |
+    out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos)        |
+        (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos)   |
+        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
         (desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos);
 
     dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
@@ -661,7 +661,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
         (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
         (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
+        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
         (desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos);
 
     dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
@@ -670,10 +670,32 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   return true;
 }
 
+// Close all non-control endpoints, cancel all pending transfers if any.
 void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
-  // TODO implement dcd_edpt_close_all()
+
+//  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
+  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
+
+  // Disable non-control interrupt
+  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
+
+  for(uint8_t n = 1; n < EP_MAX; n++)
+  {
+    // disable OUT endpoint
+    out_ep[n].DOEPCTL = 0;
+    xfer_status[n][TUSB_DIR_OUT].max_size = 0;
+
+    // disable IN endpoint
+    in_ep[n].DIEPCTL = 0;
+    xfer_status[n][TUSB_DIR_IN].max_size = 0;
+  }
+
+  // reset allocated fifo IN
+  _allocated_fifo_words_tx = 16;
 }
 
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
@@ -835,22 +857,13 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
+  // Clear stall and reset data toggle
   if(dir == TUSB_DIR_IN) {
     in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-
-    uint8_t eptype = (in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP_Msk) >> USB_OTG_DIEPCTL_EPTYP_Pos;
-    // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints.
-    if(eptype == 2 || eptype == 3) {
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
-    }
+    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
   } else {
     out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
-
-    uint8_t eptype = (out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP_Msk) >> USB_OTG_DOEPCTL_EPTYP_Pos;
-    // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints.
-    if(eptype == 2 || eptype == 3) {
-      out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
-    }
+    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
   }
 }
 

From 4ac136d81d452ea1dcfc1e9e2e8afbf02749044d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Sep 2021 00:57:07 +0700
Subject: [PATCH 0438/2085] implement remote wakeup for stm synopsys

---
 src/portable/st/synopsys/dcd_synopsys.c | 38 +++++++++++++++++++------
 1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 93bbaf23b..b1435a6c8 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -555,13 +555,31 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
 
+static void remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+  uint32_t count = SystemCoreClock / 1000;
+  while(count--) __NOP();
+}
+
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
 
-  // TODO must manually clear this bit after 1-15 ms
-  // USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  // dev->DCTL |= USB_OTG_DCTL_RWUSIG;
+  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+
+  // set remote wakeup
+  dev->DCTL |= USB_OTG_DCTL_RWUSIG;
+
+  // enable SOF to detect bus resume
+  usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
+  usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+
+  // Per specs: remote wakeup signal bit must be clear within 1-15ms
+  remote_wakeup_delay();
+
+  dev->DCTL &= ~USB_OTG_DCTL_RWUSIG;
 }
 
 void dcd_connect(uint8_t rhport)
@@ -1100,7 +1118,7 @@ void dcd_int_handler(uint8_t rhport)
   USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
   USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
 
-  uint32_t int_status = usb_otg->GINTSTS;
+  uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
 
   if(int_status & USB_OTG_GINTSTS_USBRST)
   {
@@ -1133,6 +1151,9 @@ void dcd_int_handler(uint8_t rhport)
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
   }
 
+  // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection
+  // if(int_status & USB_OTG_GINTSTS_DISCINT)
+
   if(int_status & USB_OTG_GINTSTS_OTGINT)
   {
     // OTG INT bit is read-only
@@ -1146,13 +1167,15 @@ void dcd_int_handler(uint8_t rhport)
     usb_otg->GOTGINT = otg_int;
   }
 
-#if USE_SOF
   if(int_status & USB_OTG_GINTSTS_SOF)
   {
     usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
+
+    // Disable SOF interrupt since currently only used for remote wakeup detection
+    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM;
+
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
-#endif
 
   // RxFIFO non-empty interrupt handling.
   if(int_status & USB_OTG_GINTSTS_RXFLVL)
@@ -1166,8 +1189,7 @@ void dcd_int_handler(uint8_t rhport)
     do
     {
       handle_rxflvl_ints(rhport, out_ep);
-      int_status = usb_otg->GINTSTS;
-    } while(int_status & USB_OTG_GINTSTS_RXFLVL);
+    } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL);
 
     // Manage RX FIFO size
     if (_out_ep_closed)

From 185bb21bdd1177b14415751fd0b626d0f9c79e15 Mon Sep 17 00:00:00 2001
From: David Shadoff <david.shadoff@gmail.com>
Date: Tue, 7 Sep 2021 21:13:34 -0400
Subject: [PATCH 0439/2085] Add PS4-compatible controllers

---
 examples/host/hid_controller/src/hid_app.c | 1 +
 examples/host/hid_controller/src/main.c    | 1 +
 2 files changed, 2 insertions(+)

diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index d88c74ac4..bbfea8182 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -113,6 +113,7 @@ static inline bool is_sony_ds4(uint8_t dev_addr)
 
   return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4 
            || (vid == 0x0f0d && pid == 0x005e)                 // Hori FC4 
+           || (vid == 0x0f0d && pid == 0x00ee)                 // Hori PS4 Mini (PS4-099U) 
            || (vid == 0x1f4f && pid == 0x1002)                 // ASW GG xrd controller
          );
 }
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index e13fa818a..b9b37a4d2 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -49,6 +49,7 @@ int main(void)
   board_init();
 
   printf("TinyUSB Host HID Controller Example\r\n");
+  printf("Note: Events only displayed for explictly supported controllers\r\n");
 
   tusb_init();
 

From 67e80f60e3841497779a319bbd93133c05b013f8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Sep 2021 13:35:11 +0700
Subject: [PATCH 0440/2085] fix build with gd32vf103

---
 src/portable/st/synopsys/dcd_synopsys.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index b1435a6c8..85abf940e 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -96,6 +96,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
 #include "synopsys_common.h"
 
+// for remote wakeup delay
+#define __NOP()   __asm volatile ("nop")
+
 // These numbers are the same for the whole GD32VF103 family.
 #define OTG_FS_IRQn     86
 #define EP_MAX_FS       4
@@ -559,7 +562,10 @@ static void remote_wakeup_delay(void)
 {
   // try to delay for 1 ms
   uint32_t count = SystemCoreClock / 1000;
-  while(count--) __NOP();
+  while ( count-- )
+  {
+    __NOP();
+  }
 }
 
 void dcd_remote_wakeup(uint8_t rhport)

From d077574097e4ab992f8b7c732341250797acef4f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Sep 2021 17:56:22 +0700
Subject: [PATCH 0441/2085] reset PID to DATA0 when open endpoint

---
 src/portable/renesas/usba/dcd_usba.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 8e2e3dc26..92e29f9bf 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -711,7 +711,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   USB0.PIPESEL.WORD  = num;
   USB0.PIPEMAXP.WORD = mps;
   volatile uint16_t *ctr = get_pipectr(num);
-  *ctr = USB_PIPECTR_ACLRM;
+  *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
   *ctr = 0;
   unsigned cfg = (dir << 4) | epn;
   if (xfer == TUSB_XFER_BULK) {

From 22b5b4704591da35c804045b81b63dd5094d5050 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 8 Sep 2021 21:52:27 +0900
Subject: [PATCH 0442/2085] Implement dcd_edpt_close_all for NXP khci

---
 src/portable/nxp/khci/dcd_khci.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 1f5f4e5e1..625ddcf8c 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -347,10 +347,26 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   return true;
 }
 
-void dcd_edpt_close_all (uint8_t rhport)
+void dcd_edpt_close_all(uint8_t rhport)
 {
   (void) rhport;
-  // TODO implement dcd_edpt_close_all()
+  const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  for (unsigned i = 1; i < 16; ++i) {
+    KHCI->ENDPOINT[i].ENDPT = 0;
+  }
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  buffer_descriptor_t *bd = _dcd.bdt[1][0];
+  for (unsigned i = 2; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
+    bd->head = 0;
+  }
+  endpoint_state_t *ep = &_dcd.endpoint[1][0];
+  for (unsigned i = 2; i < sizeof(_dcd.endpoint)/sizeof(*ep); ++i, ++ep) {
+    /* Clear except the odd */
+    ep->max_packet_size = 0;
+    ep->length          = 0;
+    ep->remaining       = 0;
+  }
 }
 
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
@@ -372,6 +388,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
   (void) rhport;
+  const unsigned ie  = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
   const unsigned epn = ep_addr & 0xFu;
   const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
@@ -380,6 +397,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 
   if (bd->own) {
     TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head);
+    if (ie) NVIC_EnableIRQ(USB0_IRQn);
     return false; /* The last transfer has not completed */
   }
   ep->length    = total_bytes;
@@ -398,7 +416,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
   bd->addr      = buffer;
   __DSB();
   bd->own  = 1; /* the own bit must set after addr */
-  NVIC_EnableIRQ(USB0_IRQn);
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
   return true;
 }
 

From 780852efb3c1686fef7f47b42eaabfc65356faae Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 9 Sep 2021 00:55:02 +0900
Subject: [PATCH 0443/2085] Fix stall handling

---
 src/portable/nxp/khci/dcd_khci.c | 73 ++++++++++++++++----------------
 1 file changed, 37 insertions(+), 36 deletions(-)

diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 625ddcf8c..0ddd0f75e 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -121,7 +121,7 @@ static void prepare_next_setup_packet(uint8_t rhport)
   const unsigned out_odd = _dcd.endpoint[0][0].odd;
   const unsigned in_odd  = _dcd.endpoint[0][1].odd;
   if (_dcd.bdt[0][0][out_odd].own) {
-    TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd);
+    //    TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd);
     return;
   }
   _dcd.bdt[0][0][out_odd].data     = 0;
@@ -163,9 +163,6 @@ static void process_tokdne(uint8_t rhport)
     KHCI->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
     return;
   }
-  if (s >> 4) {
-    TU_LOG1("TKDNE %x\r\n", s);
-  }
 
   const unsigned bc = bd->bc;
   const unsigned remaining = ep->remaining - bc;
@@ -321,8 +318,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   (void) rhport;
 
   const unsigned ep_addr  = ep_desc->bEndpointAddress;
-  const unsigned epn      = ep_addr & 0xFu;
-  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
   const unsigned xfer     = ep_desc->bmAttributes.xfer;
   endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
   const unsigned odd      = ep->odd;
@@ -373,8 +370,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
 
-  const unsigned epn      = ep_addr & 0xFu;
-  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
   endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
   buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
   const unsigned msk      = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
@@ -388,18 +385,15 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
   (void) rhport;
-  const unsigned ie  = NVIC_GetEnableIRQ(USB0_IRQn);
-  NVIC_DisableIRQ(USB0_IRQn);
-  const unsigned epn = ep_addr & 0xFu;
-  const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
   endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
   buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
+  TU_ASSERT(0 == bd->own);
+
+  const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
 
-  if (bd->own) {
-    TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head);
-    if (ie) NVIC_EnableIRQ(USB0_IRQn);
-    return false; /* The last transfer has not completed */
-  }
   ep->length    = total_bytes;
   ep->remaining = total_bytes;
 
@@ -412,10 +406,10 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
     next->addr = buffer + mps;
     next->own  = 1;
   }
-  bd->bc        = total_bytes >= mps ? mps: total_bytes;
-  bd->addr      = buffer;
+  bd->bc   = total_bytes >= mps ? mps: total_bytes;
+  bd->addr = buffer;
   __DSB();
-  bd->own  = 1; /* the own bit must set after addr */
+  bd->own  = 1; /* This bit must be set last */
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
   return true;
 }
@@ -423,31 +417,38 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
-  const unsigned epn = ep_addr & 0xFu;
+  const unsigned epn = tu_edpt_number(ep_addr);
   if (0 == epn) {
     KHCI->ENDPOINT[epn].ENDPT |=  USB_ENDPT_EPSTALL_MASK;
   } else {
-    const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
-    buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
-    bd[0].bdt_stall = 1;
-    bd[1].bdt_stall = 1;
+    const unsigned dir      = tu_edpt_dir(ep_addr);
+    endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
+    buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
+    TU_ASSERT(0 == bd->own,);
+    const unsigned ie       = NVIC_GetEnableIRQ(USB0_IRQn);
+    NVIC_DisableIRQ(USB0_IRQn);
+    bd->bdt_stall = 1;
+    __DSB();
+    bd->own       = 1; /* This bit must be set last */
+    if (ie) NVIC_EnableIRQ(USB0_IRQn);
   }
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
-  const unsigned epn      = ep_addr & 0xFu;
-  const unsigned dir      = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
-  const unsigned odd      = _dcd.endpoint[epn][dir].odd;
-  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
-
-  bd[odd ^ 1].own       = 0;
-  bd[odd ^ 1].data      = 1;
-  bd[odd ^ 1].bdt_stall = 0;
-  bd[odd].own           = 0;
-  bd[odd].data          = 0;
-  bd[odd].bdt_stall     = 0;
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  TU_VERIFY(epn,);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
+  TU_ASSERT(bd->own,);
+  const unsigned ie       = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  bd->own       = 0;
+  __DSB();
+  bd->bdt_stall = 0;
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
 }
 
 //--------------------------------------------------------------------+

From f81368174b613f4168ddb0e2ec1822c8dbc31d59 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 9 Sep 2021 14:34:03 +0700
Subject: [PATCH 0444/2085] add other speed descriptor callback
 tud_descriptor_other_speed_configuration_cb()

example implement tud_descriptor_device_qualifier_cb() and
tud_descriptor_other_speed_configuration_cb() on high speed device to
fully compliant to usbcv
---
 .../cdc_dual_ports/src/usb_descriptors.c      | 48 +++++++++-
 examples/device/cdc_msc/src/usb_descriptors.c | 92 +++++++++++++++----
 .../cdc_msc_freertos/src/usb_descriptors.c    | 63 ++++++++++++-
 .../hid_composite/src/usb_descriptors.c       | 57 +++++++++++-
 .../src/usb_descriptors.c                     | 55 ++++++++++-
 src/common/tusb_types.h                       |  5 +-
 src/device/usbd.c                             | 40 ++++----
 src/device/usbd.h                             |  9 +-
 8 files changed, 315 insertions(+), 54 deletions(-)

diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index 02ccbcc9e..aa400d486 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -35,6 +35,9 @@
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
                            _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
 
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
@@ -42,7 +45,7 @@ tusb_desc_device_t const desc_device =
 {
     .bLength            = sizeof(tusb_desc_device_t),
     .bDescriptorType    = TUSB_DESC_DEVICE,
-    .bcdUSB             = 0x0200,
+    .bcdUSB             = USB_BCD,
 
     // Use Interface Association Descriptor (IAD) for CDC
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
@@ -51,7 +54,7 @@ tusb_desc_device_t const desc_device =
     .bDeviceProtocol    = MISC_PROTOCOL_IAD,
     .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-    .idVendor           = 0xCafe,
+    .idVendor           = USB_VID,
     .idProduct          = USB_PID,
     .bcdDevice          = 0x0100,
 
@@ -128,6 +131,8 @@ uint8_t const desc_fs_configuration[] =
 };
 
 #if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
+
 uint8_t const desc_hs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
@@ -139,7 +144,44 @@ uint8_t const desc_hs_configuration[] =
   // 2nd CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size.
   TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_1, 4, EPNUM_CDC_1_NOTIF, 8, EPNUM_CDC_1_OUT, EPNUM_CDC_1_IN, 512),
 };
-#endif
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier =
+{
+  .bLength            = sizeof(tusb_desc_device_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE,
+  .bcdUSB             = USB_BCD,
+
+  .bDeviceClass       = TUSB_CLASS_MISC,
+  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+  .bNumConfigurations = 0x01,
+  .bReserved          = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void)
+{
+  return (uint8_t const*) &desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ?  desc_fs_configuration : desc_hs_configuration;
+}
+
+#endif // highspeed
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 3cf1eaf91..34537b8f0 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -35,32 +35,35 @@
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
                            _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
 
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
 tusb_desc_device_t const desc_device =
 {
-    .bLength            = sizeof(tusb_desc_device_t),
-    .bDescriptorType    = TUSB_DESC_DEVICE,
-    .bcdUSB             = 0x0200,
+  .bLength            = sizeof(tusb_desc_device_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE,
+  .bcdUSB             = USB_BCD,
 
-    // Use Interface Association Descriptor (IAD) for CDC
-    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
-    .bDeviceClass       = TUSB_CLASS_MISC,
-    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
-    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+  // Use Interface Association Descriptor (IAD) for CDC
+  // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+  .bDeviceClass       = TUSB_CLASS_MISC,
+  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
 
-    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-    .idVendor           = 0xCafe,
-    .idProduct          = USB_PID,
-    .bcdDevice          = 0x0100,
+  .idVendor           = USB_VID,
+  .idProduct          = USB_PID,
+  .bcdDevice          = 0x0100,
 
-    .iManufacturer      = 0x01,
-    .iProduct           = 0x02,
-    .iSerialNumber      = 0x03,
+  .iManufacturer      = 0x01,
+  .iProduct           = 0x02,
+  .iSerialNumber      = 0x03,
 
-    .bNumConfigurations = 0x01
+  .bNumConfigurations = 0x01
 };
 
 // Invoked when received GET DEVICE DESCRIPTOR
@@ -82,8 +85,6 @@ enum
   ITF_NUM_TOTAL
 };
 
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN)
-
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
@@ -126,6 +127,9 @@ enum
 
 #endif
 
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN)
+
+// full speed configuration
 uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
@@ -139,6 +143,9 @@ uint8_t const desc_fs_configuration[] =
 };
 
 #if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
+
+// high speed configuration
 uint8_t const desc_hs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
@@ -150,7 +157,54 @@ uint8_t const desc_hs_configuration[] =
   // Interface number, string index, EP Out & EP In address, EP size
   TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
 };
-#endif
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier =
+{
+  .bLength            = sizeof(tusb_desc_device_qualifier_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
+  .bcdUSB             = USB_BCD,
+
+  .bDeviceClass       = TUSB_CLASS_MISC,
+  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+  .bNumConfigurations = 0x01,
+  .bReserved          = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void)
+{
+  return (uint8_t const*) &desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
 
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
index c8dbcd415..f3ff305f8 100644
--- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c
+++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
@@ -35,6 +35,9 @@
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
                            _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
 
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
@@ -42,7 +45,7 @@ tusb_desc_device_t const desc_device =
 {
     .bLength            = sizeof(tusb_desc_device_t),
     .bDescriptorType    = TUSB_DESC_DEVICE,
-    .bcdUSB             = 0x0200,
+    .bcdUSB             = USB_BCD,
 
     // Use Interface Association Descriptor (IAD) for CDC
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
@@ -52,7 +55,7 @@ tusb_desc_device_t const desc_device =
 
     .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-    .idVendor           = 0xCafe,
+    .idVendor           = USB_VID,
     .idProduct          = USB_PID,
     .bcdDevice          = 0x0100,
 
@@ -82,8 +85,6 @@ enum
   ITF_NUM_TOTAL
 };
 
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN)
-
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
@@ -114,6 +115,8 @@ enum
 
 #endif
 
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN)
+
 uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
@@ -127,6 +130,9 @@ uint8_t const desc_fs_configuration[] =
 };
 
 #if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
+
+// high speed configuration
 uint8_t const desc_hs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
@@ -138,7 +144,54 @@ uint8_t const desc_hs_configuration[] =
   // Interface number, string index, EP Out & EP In address, EP size
   TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
 };
-#endif
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier =
+{
+  .bLength            = sizeof(tusb_desc_device_qualifier_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
+  .bcdUSB             = USB_BCD,
+
+  .bDeviceClass       = TUSB_CLASS_MISC,
+  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+  .bNumConfigurations = 0x01,
+  .bReserved          = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void)
+{
+  return (uint8_t const*) &desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
diff --git a/examples/device/hid_composite/src/usb_descriptors.c b/examples/device/hid_composite/src/usb_descriptors.c
index b9a6e7292..e760b20ba 100644
--- a/examples/device/hid_composite/src/usb_descriptors.c
+++ b/examples/device/hid_composite/src/usb_descriptors.c
@@ -36,6 +36,9 @@
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
                            _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
 
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
@@ -43,13 +46,13 @@ tusb_desc_device_t const desc_device =
 {
     .bLength            = sizeof(tusb_desc_device_t),
     .bDescriptorType    = TUSB_DESC_DEVICE,
-    .bcdUSB             = 0x0200,
+    .bcdUSB             = USB_BCD,
     .bDeviceClass       = 0x00,
     .bDeviceSubClass    = 0x00,
     .bDeviceProtocol    = 0x00,
     .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-    .idVendor           = 0xCafe,
+    .idVendor           = USB_VID,
     .idProduct          = USB_PID,
     .bcdDevice          = 0x0100,
 
@@ -111,12 +114,62 @@ uint8_t const desc_configuration[] =
   TUD_HID_DESCRIPTOR(ITF_NUM_HID, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_HID, CFG_TUD_HID_EP_BUFSIZE, 5)
 };
 
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier =
+{
+  .bLength            = sizeof(tusb_desc_device_qualifier_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
+  .bcdUSB             = USB_BCD,
+
+  .bDeviceClass       = 0x00,
+  .bDeviceSubClass    = 0x00,
+  .bDeviceProtocol    = 0x00,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+  .bNumConfigurations = 0x01,
+  .bReserved          = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void)
+{
+  return (uint8_t const*) &desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+
+  // other speed config is basically configuration with type = OHER_SPEED_CONFIG
+  memcpy(desc_other_speed_config, desc_configuration, CONFIG_TOTAL_LEN);
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  // this example use the same configuration for both high and full speed mode
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
+
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
 uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 {
   (void) index; // for multiple configurations
+
+  // This example use the same configuration for both high and full speed mode
   return desc_configuration;
 }
 
diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.c b/examples/device/hid_composite_freertos/src/usb_descriptors.c
index b9a6e7292..791813fdf 100644
--- a/examples/device/hid_composite_freertos/src/usb_descriptors.c
+++ b/examples/device/hid_composite_freertos/src/usb_descriptors.c
@@ -36,6 +36,9 @@
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
                            _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
 
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
@@ -43,13 +46,13 @@ tusb_desc_device_t const desc_device =
 {
     .bLength            = sizeof(tusb_desc_device_t),
     .bDescriptorType    = TUSB_DESC_DEVICE,
-    .bcdUSB             = 0x0200,
+    .bcdUSB             = USB_BCD,
     .bDeviceClass       = 0x00,
     .bDeviceSubClass    = 0x00,
     .bDeviceProtocol    = 0x00,
     .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-    .idVendor           = 0xCafe,
+    .idVendor           = USB_VID,
     .idProduct          = USB_PID,
     .bcdDevice          = 0x0100,
 
@@ -111,6 +114,54 @@ uint8_t const desc_configuration[] =
   TUD_HID_DESCRIPTOR(ITF_NUM_HID, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_HID, CFG_TUD_HID_EP_BUFSIZE, 5)
 };
 
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier =
+{
+  .bLength            = sizeof(tusb_desc_device_qualifier_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
+  .bcdUSB             = USB_BCD,
+
+  .bDeviceClass       = 0x00,
+  .bDeviceSubClass    = 0x00,
+  .bDeviceProtocol    = 0x00,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+  .bNumConfigurations = 0x01,
+  .bReserved          = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void)
+{
+  return (uint8_t const*) &desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+
+  // other speed config is basically configuration with type = OHER_SPEED_CONFIG
+  memcpy(desc_other_speed_config, desc_configuration, CONFIG_TOTAL_LEN);
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  // this example use the same configuration for both high and full speed mode
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
+
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index d23c6b2dd..f26983a74 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -372,7 +372,7 @@ typedef struct TU_ATTR_PACKED
 
   uint8_t  bNumInterfaces      ; ///< Number of interfaces supported by this speed configuration
   uint8_t  bConfigurationValue ; ///< Value to use to select configuration
-  uint8_t  IConfiguration      ; ///< Index of string descriptor
+  uint8_t  iConfiguration      ; ///< Index of string descriptor
   uint8_t  bmAttributes        ; ///< Same as Configuration descriptor
   uint8_t  bMaxPower           ; ///< Same as Configuration descriptor
 } tusb_desc_other_speed_t;
@@ -387,11 +387,14 @@ typedef struct TU_ATTR_PACKED
   uint8_t  bDeviceClass       ; ///< Class Code
   uint8_t  bDeviceSubClass    ; ///< SubClass Code
   uint8_t  bDeviceProtocol    ; ///< Protocol Code
+
   uint8_t  bMaxPacketSize0    ; ///< Maximum packet size for other speed
   uint8_t  bNumConfigurations ; ///< Number of Other-speed Configurations
   uint8_t  bReserved          ; ///< Reserved for future use, must be zero
 } tusb_desc_device_qualifier_t;
 
+TU_VERIFY_STATIC( sizeof(tusb_desc_device_qualifier_t) == 10, "size is not correct");
+
 /// USB Interface Association Descriptor (IAD ECN)
 typedef struct TU_ATTR_PACKED
 {
diff --git a/src/device/usbd.c b/src/device/usbd.c
index a52ea9afe..58b3a5701 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1002,10 +1002,22 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
     break;
 
     case TUSB_DESC_CONFIGURATION:
+    case TUSB_DESC_OTHER_SPEED_CONFIG:
     {
-      TU_LOG2(" Configuration[%u]\r\n", desc_index);
+      tusb_desc_configuration_t const* desc_config;
+
+      if ( desc_type == TUSB_DESC_CONFIGURATION )
+      {
+        TU_LOG2(" Configuration[%u]\r\n", desc_index);
+        desc_config = (tusb_desc_configuration_t const*) tud_descriptor_configuration_cb(desc_index);
+      }else
+      {
+        // Host only request this after getting Device Qualifier descriptor
+        TU_LOG2(" Other Speed Configuration\r\n");
+        TU_VERIFY( tud_descriptor_other_speed_configuration_cb );
+        desc_config = (tusb_desc_configuration_t const*) tud_descriptor_other_speed_configuration_cb(desc_index);
+      }
 
-      tusb_desc_configuration_t const* desc_config = (tusb_desc_configuration_t const*) tud_descriptor_configuration_cb(desc_index);
       TU_ASSERT(desc_config);
 
       // Use offsetof to avoid pointer to the odd/misaligned address
@@ -1031,27 +1043,13 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
     case TUSB_DESC_DEVICE_QUALIFIER:
       TU_LOG2(" Device Qualifier\r\n");
 
-      // Host sends this request to ask why our device with USB BCD from 2.0
-      // but is running at Full/Low Speed. If not highspeed capable stall this request,
-      // otherwise return the descriptor that could work in highspeed mode
-      if ( tud_descriptor_device_qualifier_cb )
-      {
-        uint8_t const* desc_qualifier = tud_descriptor_device_qualifier_cb();
-        TU_ASSERT(desc_qualifier);
+      TU_VERIFY( tud_descriptor_device_qualifier_cb );
 
-        // first byte of descriptor is its size
-        return tud_control_xfer(rhport, p_request, (void*) desc_qualifier, desc_qualifier[0]);
-      }else
-      {
-        return false;
-      }
-    break;
+      uint8_t const* desc_qualifier = tud_descriptor_device_qualifier_cb();
+      TU_VERIFY(desc_qualifier);
 
-    case TUSB_DESC_OTHER_SPEED_CONFIG:
-      TU_LOG2(" Other Speed Configuration\r\n");
-
-      // After Device Qualifier descriptor is received host will ask for this descriptor
-      return false; // not supported
+      // first byte of descriptor is its size
+      return tud_control_xfer(rhport, p_request, (void*) desc_qualifier, desc_qualifier[0]);
     break;
 
     default: return false;
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 9becf2d0d..638d93094 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -113,9 +113,16 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid);
 TU_ATTR_WEAK uint8_t const * tud_descriptor_bos_cb(void);
 
 // Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
-// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
 TU_ATTR_WEAK uint8_t const* tud_descriptor_device_qualifier_cb(void);
 
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+TU_ATTR_WEAK uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index);
+
 // Invoked when device is mounted (configured)
 TU_ATTR_WEAK void tud_mount_cb(void);
 

From 27800f7e4f39c856d2fe82e6320e855d8c283518 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 9 Sep 2021 16:01:05 +0700
Subject: [PATCH 0445/2085] remove connected check for DCD_EVENT_UNPLUGGED
 since previous bus reset can clear this

implement unplugged detection for trans dimension dcd
---
 src/device/usbd.c                             | 14 ++++------
 .../nxp/transdimension/dcd_transdimension.c   | 28 ++++++++++---------
 2 files changed, 20 insertions(+), 22 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 58b3a5701..4ab60569b 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1064,15 +1064,11 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
   switch (event->event_id)
   {
     case DCD_EVENT_UNPLUGGED:
-      // UNPLUGGED event can be bouncing, only processing if we are currently connected
-      if ( _usbd_dev.connected )
-      {
-        _usbd_dev.connected  = 0;
-        _usbd_dev.addressed  = 0;
-        _usbd_dev.cfg_num    = 0;
-        _usbd_dev.suspended  = 0;
-        osal_queue_send(_usbd_q, event, in_isr);
-      }
+      _usbd_dev.connected  = 0;
+      _usbd_dev.addressed  = 0;
+      _usbd_dev.cfg_num    = 0;
+      _usbd_dev.suspended  = 0;
+      osal_queue_send(_usbd_q, event, in_isr);
     break;
 
     case DCD_EVENT_SUSPEND:
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 42047ef92..da766afa1 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -245,7 +245,7 @@ void dcd_init(uint8_t rhport)
 
   dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
   dcd_reg->USBSTS  = dcd_reg->USBSTS;
-  dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND /*| INTR_SOF*/;
+  dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND;
 
   dcd_reg->USBCMD &= ~0x00FF0000;     // Interrupt Threshold Interval = 0
   dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
@@ -272,7 +272,9 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 
 void dcd_remote_wakeup(uint8_t rhport)
 {
-  (void) rhport;
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  (void) dcd_reg;
+//  dcd_reg->PORTSC1 =
 }
 
 void dcd_connect(uint8_t rhport)
@@ -412,7 +414,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 //--------------------------------------------------------------------+
 void dcd_int_handler(uint8_t rhport)
 {
-  dcd_registers_t* const dcd_reg = _dcd_controller[rhport].regs;
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
 
   uint32_t const int_enable = dcd_reg->USBINTR;
   uint32_t const int_status = dcd_reg->USBSTS & int_enable;
@@ -433,6 +435,7 @@ void dcd_int_handler(uint8_t rhport)
     if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
     {
       // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+      // Skip suspend event if we are not addressed
       if ((dcd_reg->DEVICEADDR >> 25) & 0x0f)
       {
         dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
@@ -440,19 +443,18 @@ void dcd_int_handler(uint8_t rhport)
     }
   }
 
+  // Set if the port controller enters the full or high-speed operational state.
+	if (int_status & INTR_PORT_CHANGE)
+	{
+	  if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) )
+	  {
+      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+	  }
+	}
+
   // Make sure we read the latest version of _dcd_data.
   CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
 
-  // TODO disconnection does not generate interrupt !!!!!!
-//	if (int_status & INTR_PORT_CHANGE)
-//	{
-//	  if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) )
-//	  {
-//      dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_UNPLUGGED };
-//      dcd_event_handler(&event, true);
-//	  }
-//	}
-
   if (int_status & INTR_USB)
   {
     uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;

From f948cbe4710c800cd168de793cc1c4fb80a55dd7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 9 Sep 2021 17:04:04 +0700
Subject: [PATCH 0446/2085] nxp tdi implement remote wakeup

enhance bus reset, unplugged, suspend, resume detection
---
 .../nxp/transdimension/dcd_transdimension.c   | 53 ++++++++++++-------
 1 file changed, 35 insertions(+), 18 deletions(-)

diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index da766afa1..4a8205162 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -245,7 +245,7 @@ void dcd_init(uint8_t rhport)
 
   dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
   dcd_reg->USBSTS  = dcd_reg->USBSTS;
-  dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_RESET | INTR_SUSPEND;
+  dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND;
 
   dcd_reg->USBCMD &= ~0x00FF0000;     // Interrupt Threshold Interval = 0
   dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
@@ -273,8 +273,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 void dcd_remote_wakeup(uint8_t rhport)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  (void) dcd_reg;
-//  dcd_reg->PORTSC1 =
+  dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME;
 }
 
 void dcd_connect(uint8_t rhport)
@@ -423,15 +422,42 @@ void dcd_int_handler(uint8_t rhport)
   // disabled interrupt sources
   if (int_status == 0) return;
 
-  if (int_status & INTR_RESET)
-  {
-    bus_reset(rhport);
-    uint32_t speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS;
-    dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true);
-  }
+  // Set if the port controller enters the full or high-speed operational state.
+  // either from Bus Reset or Suspended state
+	if (int_status & INTR_PORT_CHANGE)
+	{
+	  // TU_LOG2("PortChange %08lx\r\n", dcd_reg->PORTSC1);
+
+	  // Reset interrupt is not enabled, we manually check if Port Change is due
+	  // to connection / disconnection
+	  if ( dcd_reg->USBSTS & INTR_RESET )
+	  {
+	    dcd_reg->USBSTS = INTR_RESET;
+
+	    if (dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS)
+	    {
+	      uint32_t const speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS;
+	      bus_reset(rhport);
+	      dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true);
+	    }else
+	    {
+	      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+	    }
+	  }
+	  else
+	  {
+	    // Triggered by resuming from suspended state
+	    if ( !(dcd_reg->PORTSC1 & PORTSC1_SUSPEND) )
+	    {
+	      dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+	    }
+	  }
+	}
 
   if (int_status & INTR_SUSPEND)
   {
+    // TU_LOG2("Suspend %08lx\r\n", dcd_reg->PORTSC1);
+
     if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
     {
       // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
@@ -443,15 +469,6 @@ void dcd_int_handler(uint8_t rhport)
     }
   }
 
-  // Set if the port controller enters the full or high-speed operational state.
-	if (int_status & INTR_PORT_CHANGE)
-	{
-	  if ( !(dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS) )
-	  {
-      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-	  }
-	}
-
   // Make sure we read the latest version of _dcd_data.
   CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
 

From ad8c0ee8182f6c6120bf8124dbdcd2883f285f8f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 9 Sep 2021 20:26:03 +0700
Subject: [PATCH 0447/2085] nxp tdi: enhance qhd using DCD_ATTR_ENDPOINT_MAX

---
 src/common/tusb_common.h                      |  2 +-
 .../nxp/transdimension/dcd_transdimension.c   | 87 +++++++++----------
 2 files changed, 44 insertions(+), 45 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 687f980be..d0cc41285 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -372,7 +372,7 @@ typedef struct
 
 static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
 {
-  static char not_found[10];
+  static char not_found[11];
 
   for(uint16_t i=0; i<p_table->count; i++)
   {
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 4a8205162..35f824112 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -145,10 +145,6 @@ typedef struct
 }dcd_controller_t;
 
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-  // Each endpoint with direction (IN/OUT) occupies a queue head
-  // Therefore QHD_MAX is 2 x max endpoint count
-  #define QHD_MAX  (8*2)
-
   static const dcd_controller_t _dcd_controller[] =
   {
     // RT1010 and RT1020 only has 1 USB controller
@@ -161,8 +157,6 @@ typedef struct
   };
 
 #else
-  #define QHD_MAX (6*2)
-
   static const dcd_controller_t _dcd_controller[] =
   {
     { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
@@ -174,8 +168,10 @@ typedef struct
 
 typedef struct {
   // Must be at 2K alignment
-  dcd_qhd_t qhd[QHD_MAX] TU_ATTR_ALIGNED(64);
-  dcd_qtd_t qtd[QHD_MAX] TU_ATTR_ALIGNED(32); // for portability, TinyUSB only queue 1 TD for each Qhd
+  // Each endpoint with direction (IN/OUT) occupies a queue head
+  // for portability, TinyUSB only queue 1 TD for each Qhd
+  dcd_qhd_t qhd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64);
+  dcd_qtd_t qtd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
 }dcd_data_t;
 
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
@@ -217,11 +213,11 @@ static void bus_reset(uint8_t rhport)
   tu_memclr(&_dcd_data, sizeof(dcd_data_t));
 
   //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
-  _dcd_data.qhd[0].zero_length_termination = _dcd_data.qhd[1].zero_length_termination = 1;
-  _dcd_data.qhd[0].max_package_size = _dcd_data.qhd[1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
-  _dcd_data.qhd[0].qtd_overlay.next = _dcd_data.qhd[1].qtd_overlay.next = QTD_NEXT_INVALID;
+  _dcd_data.qhd[0][0].zero_length_termination = _dcd_data.qhd[0][1].zero_length_termination = 1;
+  _dcd_data.qhd[0][0].max_package_size = _dcd_data.qhd[0][1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
+  _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID;
 
-  _dcd_data.qhd[0].int_on_setup = 1; // OUT only
+  _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
 }
 
 void dcd_init(uint8_t rhport)
@@ -291,11 +287,6 @@ void dcd_disconnect(uint8_t rhport)
 //--------------------------------------------------------------------+
 // HELPER
 //--------------------------------------------------------------------+
-// index to bit position in register
-static inline uint8_t ep_idx2bit(uint8_t ep_idx)
-{
-  return ep_idx/2 + ( (ep_idx%2) ? 16 : 0);
-}
 
 static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
 {
@@ -325,12 +316,15 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
   dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
+
+  // flush to abort any primed buffer
+  dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   // data toggle also need to be reset
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -343,15 +337,14 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   // TODO not support ISO yet
   TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
 
-  uint8_t const epnum  = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  uint8_t const ep_idx = 2*epnum + dir;
+  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
 
   // Must not exceed max endpoint number
   TU_ASSERT( epnum < _dcd_controller[rhport].ep_count );
 
   //------------- Prepare Queue Head -------------//
-  dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
   tu_memclr(p_qhd, sizeof(dcd_qhd_t));
 
   p_qhd->zero_length_termination = 1;
@@ -378,7 +371,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
-  uint8_t const ep_idx = 2*epnum + dir;
 
   if ( epnum == 0 )
   {
@@ -387,8 +379,8 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
     while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
   }
 
-  dcd_qhd_t * p_qhd = &_dcd_data.qhd[ep_idx];
-  dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
+  dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
 
   // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
   // address to 32-byte boundaries.
@@ -403,7 +395,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
   CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
 
   // start transfer
-  dcd_reg->ENDPTPRIME = TU_BIT( ep_idx2bit(ep_idx) ) ;
+  dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0));
 
   return true;
 }
@@ -411,6 +403,18 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 //--------------------------------------------------------------------+
 // ISR
 //--------------------------------------------------------------------+
+
+static void process_edpt_complete_isr(uint8_t rhport, uint8_t ep_num, uint8_t dir)
+{
+  dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_num][dir];
+
+  uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
+      ( p_qtd->xact_err || p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
+
+  // only number of bytes in the IOC qtd
+  dcd_event_xfer_complete(rhport, tu_edpt_addr(ep_num, dir), p_qtd->expected_bytes - p_qtd->total_bytes, result, true);
+}
+
 void dcd_int_handler(uint8_t rhport)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -481,26 +485,24 @@ void dcd_int_handler(uint8_t rhport)
     {
       //------------- Set up Received -------------//
       // 23.10.10.2 Operational model for setup transfers
-      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;// acknowledge
+      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
 
-      dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0].setup_request, true);
+      dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0][0].setup_request, true);
+    }
+
+    // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
+    if (int_status & INTR_ERROR)
+    {
+      TU_LOG_HEX(1, int_status);
+      TU_LOG_HEX(1, edpt_complete);
     }
 
     if ( edpt_complete )
     {
-      for(uint8_t ep_idx = 0; ep_idx < QHD_MAX; ep_idx++)
+      for(uint8_t ep_num = 0; ep_num < DCD_ATTR_ENDPOINT_MAX; ep_num++)
       {
-        if ( tu_bit_test(edpt_complete, ep_idx2bit(ep_idx)) )
-        {
-          // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
-          dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_idx];
-
-          uint8_t result = p_qtd->halted  ? XFER_RESULT_STALLED :
-              ( p_qtd->xact_err ||p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
-
-          uint8_t const ep_addr = (ep_idx/2) | ( (ep_idx & 0x01) ? TUSB_DIR_IN_MASK : 0 );
-          dcd_event_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, result, true); // only number of bytes in the IOC qtd
-        }
+        if ( tu_bit_test(edpt_complete, ep_num)    ) process_edpt_complete_isr(rhport, ep_num, TUSB_DIR_OUT);
+        if ( tu_bit_test(edpt_complete, ep_num+16) ) process_edpt_complete_isr(rhport, ep_num, TUSB_DIR_IN);
       }
     }
   }
@@ -509,9 +511,6 @@ void dcd_int_handler(uint8_t rhport)
   {
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
-
-  if (int_status & INTR_NAK) {}
-  if (int_status & INTR_ERROR) TU_ASSERT(false, );
 }
 
 #endif

From 283783c082d2253984066cb475714217c63454d6 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 9 Sep 2021 16:45:18 +0200
Subject: [PATCH 0448/2085] dcd_edpt_xfer_fifo: use qtd_init if restriction not
 met.

---
 .../nxp/transdimension/dcd_transdimension.c   | 20 +++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index a4d6c5d48..0a18e711e 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -494,7 +494,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
     tu_fifo_get_write_info(ff, &fifo_info);
   }
 
-  if(total_bytes <= fifo_info.len_lin)
+  if (total_bytes <= fifo_info.len_lin)
   {
     // Limit transfer length to total_bytes
     fifo_info.len_wrap = 0;
@@ -508,12 +508,20 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   // address to 32-byte boundaries.
   // void* cast to suppress cast-align warning, buffer must be
   CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_lin, 4), fifo_info.len_lin + 31);
-  if (fifo_info.len_wrap > 0)
-  {
-     CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31);
-  }
+
   //------------- Prepare qtd -------------//
-  qtd_init_fifo(p_qtd, &fifo_info, total_bytes);
+
+  // In case of : wrapped part is present & buffer is aligned to 4k & buffer size is multiple of 4k
+  if (total_bytes > fifo_info.len_lin && (uint32_t)fifo_info.ptr_wrap == tu_align4k((uint32_t)fifo_info.ptr_wrap) && tu_fifo_depth(ff) == tu_align4k(tu_fifo_depth(ff)))
+  {
+    CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31);
+    qtd_init_fifo(p_qtd, &fifo_info, total_bytes);
+  }
+  else
+  {
+    qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes);
+  }
+
   p_qtd->int_on_complete = true;
   p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
   p_qhd->ff = ff;

From d7238d9a86901f0da77c8a08330eb647e6ea912b Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Fri, 10 Sep 2021 00:13:29 +0900
Subject: [PATCH 0449/2085] Remove heap memory area

---
 hw/bsp/frdm_kl25z/board.mk | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
index 451bc37c2..bc9240e55 100644
--- a/hw/bsp/frdm_kl25z/board.mk
+++ b/hw/bsp/frdm_kl25z/board.mk
@@ -8,8 +8,12 @@ CFLAGS += \
   -DCPU_MKL25Z128VLK4 \
   -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX
 
+LDFLAGS += \
+  -Wl,--defsym,__stack_size__=0x400 \
+  -Wl,--defsym,__heap_size__=0
+
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
+CFLAGS += -Wno-error=unused-parameter -Wno-error=format
 
 MCU_DIR = $(SDK_DIR)/devices/MKL25Z4
 

From 2998f67eacfb007806198a7d91cc1623ee966c2c Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Fri, 10 Sep 2021 00:18:43 +0900
Subject: [PATCH 0450/2085] Fix dcd_edpt_clear_stall to reset data toggle

---
 src/portable/nxp/khci/dcd_khci.c | 30 +++++++++++++++++++-----------
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 0ddd0f75e..2ba063ff2 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -323,7 +323,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   const unsigned xfer     = ep_desc->bmAttributes.xfer;
   endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
   const unsigned odd      = ep->odd;
-  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
 
   /* No support for control transfer */
   TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
@@ -373,13 +373,17 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   const unsigned epn      = tu_edpt_number(ep_addr);
   const unsigned dir      = tu_edpt_dir(ep_addr);
   endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
-  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
   const unsigned msk      = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+  const unsigned ie       = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
   KHCI->ENDPOINT[epn].ENDPT &= ~msk;
   ep->max_packet_size = 0;
   ep->length          = 0;
   ep->remaining       = 0;
-  bd->head            = 0;
+  bd[0].head          = 0;
+  bd[1].head          = 0;
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
@@ -422,9 +426,9 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
     KHCI->ENDPOINT[epn].ENDPT |=  USB_ENDPT_EPSTALL_MASK;
   } else {
     const unsigned dir      = tu_edpt_dir(ep_addr);
-    endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
-    buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
-    TU_ASSERT(0 == bd->own,);
+    const unsigned odd      = _dcd.endpoint[epn][dir].odd;
+    buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][odd];
+    TU_VERIFY(0 == bd->own,);
     const unsigned ie       = NVIC_GetEnableIRQ(USB0_IRQn);
     NVIC_DisableIRQ(USB0_IRQn);
     bd->bdt_stall = 1;
@@ -440,14 +444,18 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   const unsigned epn      = tu_edpt_number(ep_addr);
   TU_VERIFY(epn,);
   const unsigned dir      = tu_edpt_dir(ep_addr);
-  endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
-  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
-  TU_ASSERT(bd->own,);
+  const unsigned odd      = _dcd.endpoint[epn][dir].odd;
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+  TU_VERIFY(bd[odd].own,);
   const unsigned ie       = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
-  bd->own       = 0;
+  bd[odd].own = 0;
   __DSB();
-  bd->bdt_stall = 0;
+  bd[odd].bdt_stall  = 0;
+  if (bd[odd].data) {
+    bd[odd    ].data = 0;
+    bd[odd ^ 1].data = 1;
+  }
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
 }
 

From 580893b3fe802d0aaeefa6c851dda828289c806c Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 10 Sep 2021 11:17:33 +0200
Subject: [PATCH 0451/2085] Shorter expr.

---
 src/portable/nxp/transdimension/dcd_transdimension.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 0a18e711e..d669791dc 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -512,7 +512,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   //------------- Prepare qtd -------------//
 
   // In case of : wrapped part is present & buffer is aligned to 4k & buffer size is multiple of 4k
-  if (total_bytes > fifo_info.len_lin && (uint32_t)fifo_info.ptr_wrap == tu_align4k((uint32_t)fifo_info.ptr_wrap) && tu_fifo_depth(ff) == tu_align4k(tu_fifo_depth(ff)))
+  if (total_bytes > fifo_info.len_lin && !tu_offset4k((uint32_t)fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff)))
   {
     CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31);
     qtd_init_fifo(p_qtd, &fifo_info, total_bytes);

From 8886de0d8a14daa70d1fcf4101e3fdeda12a1b26 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 10 Sep 2021 13:05:15 +0200
Subject: [PATCH 0452/2085] Fix remote_wakeup

---
 src/portable/nuvoton/nuc121/dcd_nuc121.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index 7edafe5d3..d101550b6 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -252,10 +252,23 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   // do it at dcd_edpt0_status_complete()
 }
 
+static void remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+  uint32_t count = SystemCoreClock / 1000;
+  while(count--) __NOP();
+}
+
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
-  USBD->ATTR = USBD_ATTR_RWAKEUP_Msk;
+  // Enable PHY before sending Resume('K') state
+  USBD->ATTR |= USBD_ATTR_PHYEN_Msk;
+  USBD->ATTR |= USBD_ATTR_RWAKEUP_Msk;
+
+  // Per specs: remote wakeup signal bit must be clear within 1-15ms
+  remote_wakeup_delay();
+  USBD->ATTR &=~USBD_ATTR_RWAKEUP_Msk;
 }
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
@@ -374,7 +387,8 @@ void dcd_int_handler(uint8_t rhport)
 {
   (void) rhport;
 
-  uint32_t status = USBD->INTSTS;
+  // Mask non-enabled irqs, ex. SOF
+  uint32_t status = USBD->INTSTS & (enabled_irqs | 0xffffff00);
 #ifdef SUPPORT_LPM
   uint32_t state = USBD->ATTR & 0x300f;
 #else

From 22571ec98ef89a76239b27c86cbdac3db3c42f09 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Fri, 10 Sep 2021 16:04:47 +0200
Subject: [PATCH 0453/2085] reset PID to DATA0 on clear_stall.

---
 src/portable/nuvoton/nuc121/dcd_nuc121.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index d101550b6..5dfc77bb7 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -381,6 +381,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   (void) rhport;
   USBD_EP_T *ep = ep_entry(ep_addr, false);
   ep->CFG |= USBD_CFG_CSTALL_Msk;
+  ep->CFG &=~USBD_CFG_DSQSYNC_Msk;
 }
 
 void dcd_int_handler(uint8_t rhport)

From 1f7ade2b751d899a73e58c2b7f0d17a00dbf6899 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 11 Sep 2021 19:27:37 +0700
Subject: [PATCH 0454/2085] nxp tdi: fix error td prevent further transfer

---
 .../nxp/transdimension/dcd_transdimension.c   | 54 +++++++++++--------
 1 file changed, 31 insertions(+), 23 deletions(-)

diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 35f824112..ee1a50db3 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -91,12 +91,15 @@ typedef struct
   uint32_t                      : 3  ;
   uint32_t int_on_complete      : 1  ;
   volatile uint32_t total_bytes : 15 ;
-  uint32_t                      : 0  ;
+  uint32_t                      : 1  ;
 
   // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
   uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
 
-  //------------- DCD Area -------------//
+  //--------------------------------------------------------------------+
+  // TD is 32 bytes aligned but occupies only 28 bytes
+  // Therefore there are 4 bytes padding that we can use.
+  //--------------------------------------------------------------------+
   uint16_t expected_bytes;
   uint8_t reserved[2];
 } dcd_qtd_t;
@@ -109,11 +112,10 @@ typedef struct
   // Word 0: Capabilities and Characteristics
   uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
   uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
-  uint32_t max_package_size        : 11 ; ///< This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize)
+  uint32_t max_packet_size         : 11 ; ///< Endpoint's wMaxPacketSize
   uint32_t                         : 2  ;
   uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple�. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
   uint32_t iso_mult                : 2  ; ///<
-  uint32_t                         : 0  ;
 
   // Word 1: Current qTD Pointer
   volatile uint32_t qtd_addr;
@@ -125,8 +127,8 @@ typedef struct
   volatile tusb_control_request_t setup_request;
 
   //--------------------------------------------------------------------+
-  /// Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes
-  /// thus there are 16 bytes padding free that we can make use of.
+  // QHD is 64 bytes aligned but occupies only 48 bytes
+  // Therefore there are 16 bytes padding that we can use.
   //--------------------------------------------------------------------+
   uint8_t reserved[16];
 } dcd_qhd_t;
@@ -214,7 +216,7 @@ static void bus_reset(uint8_t rhport)
 
   //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
   _dcd_data.qhd[0][0].zero_length_termination = _dcd_data.qhd[0][1].zero_length_termination = 1;
-  _dcd_data.qhd[0][0].max_package_size = _dcd_data.qhd[0][1].max_package_size = CFG_TUD_ENDPOINT0_SIZE;
+  _dcd_data.qhd[0][0].max_packet_size  = _dcd_data.qhd[0][1].max_packet_size  = CFG_TUD_ENDPOINT0_SIZE;
   _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID;
 
   _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
@@ -348,7 +350,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   tu_memclr(p_qhd, sizeof(dcd_qhd_t));
 
   p_qhd->zero_length_termination = 1;
-  p_qhd->max_package_size        = p_endpoint_desc->wMaxPacketSize.size;
+  p_qhd->max_packet_size         = p_endpoint_desc->wMaxPacketSize.size;
   p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
 
   CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
@@ -390,7 +392,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
   //------------- Prepare qtd -------------//
   qtd_init(p_qtd, buffer, total_bytes);
   p_qtd->int_on_complete = true;
-  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
+
+  p_qhd->qtd_overlay.halted = false;            // clear any previous error
+  p_qhd->qtd_overlay.next   = (uint32_t) p_qtd; // activate by linking qtd to qhd
 
   CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
 
@@ -404,15 +408,22 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 // ISR
 //--------------------------------------------------------------------+
 
-static void process_edpt_complete_isr(uint8_t rhport, uint8_t ep_num, uint8_t dir)
+static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir)
 {
-  dcd_qtd_t * p_qtd = &_dcd_data.qtd[ep_num][dir];
+  dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
 
   uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
       ( p_qtd->xact_err || p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
 
+  if ( result != XFER_RESULT_SUCCESS )
+  {
+    dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+    // flush to abort error buffer
+    dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
+  }
+
   // only number of bytes in the IOC qtd
-  dcd_event_xfer_complete(rhport, tu_edpt_addr(ep_num, dir), p_qtd->expected_bytes - p_qtd->total_bytes, result, true);
+  dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), p_qtd->expected_bytes - p_qtd->total_bytes, result, true);
 }
 
 void dcd_int_handler(uint8_t rhport)
@@ -473,11 +484,11 @@ void dcd_int_handler(uint8_t rhport)
     }
   }
 
-  // Make sure we read the latest version of _dcd_data.
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
   if (int_status & INTR_USB)
   {
+    // Make sure we read the latest version of _dcd_data.
+    CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+
     uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
     dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
 
@@ -491,18 +502,15 @@ void dcd_int_handler(uint8_t rhport)
     }
 
     // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
-    if (int_status & INTR_ERROR)
-    {
-      TU_LOG_HEX(1, int_status);
-      TU_LOG_HEX(1, edpt_complete);
-    }
+    // nothing to do, we will submit xfer as error to usbd
+    // if (int_status & INTR_ERROR) { }
 
     if ( edpt_complete )
     {
-      for(uint8_t ep_num = 0; ep_num < DCD_ATTR_ENDPOINT_MAX; ep_num++)
+      for(uint8_t epnum = 0; epnum < DCD_ATTR_ENDPOINT_MAX; epnum++)
       {
-        if ( tu_bit_test(edpt_complete, ep_num)    ) process_edpt_complete_isr(rhport, ep_num, TUSB_DIR_OUT);
-        if ( tu_bit_test(edpt_complete, ep_num+16) ) process_edpt_complete_isr(rhport, ep_num, TUSB_DIR_IN);
+        if ( tu_bit_test(edpt_complete, epnum)    ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_OUT);
+        if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN);
       }
     }
   }

From dd60ce784c635addf01ae3039d3be55a74f3d506 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 11 Sep 2021 21:29:04 +0700
Subject: [PATCH 0455/2085] nxp tdi: implement dcd edpt close all

---
 .../nxp/transdimension/dcd_transdimension.c   | 23 +++++++++++++++----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index ee1a50db3..07009ff50 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -57,11 +57,15 @@
 // ENDPTCTRL
 enum {
   ENDPTCTRL_STALL          = TU_BIT(0),
-  ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), ///< used for test only
+  ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), // used for test only
   ENDPTCTRL_TOGGLE_RESET   = TU_BIT(6),
   ENDPTCTRL_ENABLE         = TU_BIT(7)
 };
 
+enum {
+  ENDPTCTRL_TYPE_POS  = 2, // Endpoint type is 2-bit field
+};
+
 // USBSTS, USBINTR
 enum {
   INTR_USB         = TU_BIT(0),
@@ -193,9 +197,9 @@ static void bus_reset(uint8_t rhport)
   // endpoint type of the unused direction must be changed from the control type to any other
   // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
   // for the data PID tracking on the active endpoint.
-  for( int i=1; i < _dcd_controller[rhport].ep_count; i++)
+  for( uint8_t i=1; i < _dcd_controller[rhport].ep_count; i++)
   {
-    dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
+    dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
   }
 
   //------------- Clear All Registers -------------//
@@ -364,8 +368,17 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 
 void dcd_edpt_close_all (uint8_t rhport)
 {
-  (void) rhport;
-  // TODO implement dcd_edpt_close_all()
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
+  // Disable all non-control endpoints
+  for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++)
+  {
+    _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1;
+    _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1;
+
+    dcd_reg->ENDPTFLUSH = TU_BIT(epnum) |  TU_BIT(epnum+16);
+    dcd_reg->ENDPTCTRL[epnum] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
+  }
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)

From 9bed4e2e21dda8c6aac89852492bd178916d6be0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Sep 2021 00:45:15 +0700
Subject: [PATCH 0456/2085] refactor nxp TDI dcd_edpt_xfer_fifo

---
 .../nxp/transdimension/dcd_transdimension.c   | 167 ++++++++----------
 1 file changed, 73 insertions(+), 94 deletions(-)

diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 294f88c56..a61f503f6 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -298,51 +298,30 @@ void dcd_disconnect(uint8_t rhport)
 
 static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
 {
+  // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the
+  // address to 32-byte boundaries. Buffer must be word aligned
+  CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
+
   tu_memclr(p_qtd, sizeof(dcd_qtd_t));
 
-  p_qtd->next        = QTD_NEXT_INVALID;
-  p_qtd->active      = 1;
-  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
+  p_qtd->next            = QTD_NEXT_INVALID;
+  p_qtd->active          = 1;
+  p_qtd->total_bytes     = p_qtd->expected_bytes = total_bytes;
+  p_qtd->int_on_complete = true;
 
   if (data_ptr != NULL)
   {
-    p_qtd->buffer[0]   = (uint32_t) data_ptr;
+    p_qtd->buffer[0] = (uint32_t) data_ptr;
+
+    uint32_t const bufend = p_qtd->buffer[0] + total_bytes;
     for(uint8_t i=1; i<5; i++)
     {
-      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
-    }
-  }
-}
+      uint32_t const next_page = tu_align4k( p_qtd->buffer[i-1] ) + 4096;
+      if ( bufend <= next_page ) break;
 
-static void qtd_init_fifo(dcd_qtd_t* p_qtd, tu_fifo_buffer_info_t *info, uint16_t total_bytes)
-{
-  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
+      p_qtd->buffer[i] = next_page;
 
-  p_qtd->next        = QTD_NEXT_INVALID;
-  p_qtd->active      = 1;
-  p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
-
-  // Fifo length has been trimmed to total_bytes
-  int16_t len_lin  = info->len_lin;
-
-  if (len_lin != 0)
-  {
-    p_qtd->buffer[0]   = (uint32_t) info->ptr_lin;
-
-    len_lin -= 4096 - ((uint32_t) info->ptr_lin - tu_align4k((uint32_t) info->ptr_lin));
-
-    // Set linear part
-    uint8_t i = 1;
-    for(; i<5; i++)
-    {
-      if (len_lin <= 0) break;
-      p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
-      len_lin -= 4096;
-    }
-    // Set wrapped part
-    for(uint8_t page = 0; i<5; i++, page++)
-    {
-      p_qtd->buffer[i] |= (uint32_t) info->ptr_wrap + 4096 * page;
+      // TODO page[1] FRAME_N for ISO transfer
     }
   }
 }
@@ -445,11 +424,17 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0));
 }
 
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
+  dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
+
+  p_qhd->qtd_overlay.halted = false;            // clear any previous error
+  p_qhd->qtd_overlay.next   = (uint32_t) p_qtd; // link qtd to qhd
+
+  // flush cache
+  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
 
   if ( epnum == 0 )
   {
@@ -458,26 +443,24 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
     while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
   }
 
-  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
-  dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
-
-  // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
-  // address to 32-byte boundaries.
-  // void* cast to suppress cast-align warning, buffer must be
-  CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31);
-
-  //------------- Prepare qtd -------------//
-  qtd_init(p_qtd, buffer, total_bytes);
-  p_qtd->int_on_complete = true;
-
-  p_qhd->ff = NULL;
-  p_qhd->qtd_overlay.halted = false;            // clear any previous error
-  p_qhd->qtd_overlay.next   = (uint32_t) p_qtd; // activate by linking qtd to qhd
-
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
   // start transfer
   dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0));
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
+  dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
+
+  // Prepare qtd
+  qtd_init(p_qtd, buffer, total_bytes);
+
+  // Start qhd transfer
+  p_qhd->ff = NULL;
+  qhd_start_xfer(rhport, epnum, dir);
 
   return true;
 }
@@ -485,17 +468,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 // fifo has to be aligned to 4k boundary
 bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
 {
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  if ( epnum == 0 )
-  {
-    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
-    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
-    while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
-  }
-
   dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
   dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
 
@@ -509,42 +484,45 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
     tu_fifo_get_write_info(ff, &fifo_info);
   }
 
-  if (total_bytes <= fifo_info.len_lin)
+  if ( fifo_info.len_lin >= total_bytes )
   {
-    // Limit transfer length to total_bytes
-    fifo_info.len_wrap = 0;
-    fifo_info.len_lin = total_bytes;
-  } else
-  {
-    // Class driver need to ensure at least total_bytes elements in fifo
-    fifo_info.len_wrap = total_bytes - fifo_info.len_lin;
-  }
-  // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
-  // address to 32-byte boundaries.
-  // void* cast to suppress cast-align warning, buffer must be
-  CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_lin, 4), fifo_info.len_lin + 31);
-
-  //------------- Prepare qtd -------------//
-
-  // In case of : wrapped part is present & buffer is aligned to 4k & buffer size is multiple of 4k
-  if (total_bytes > fifo_info.len_lin && !tu_offset4k((uint32_t)fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff)))
-  {
-    CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), fifo_info.len_wrap + 31);
-    qtd_init_fifo(p_qtd, &fifo_info, total_bytes);
+    // Linear length is enough for this transfer
+    qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes);
   }
   else
   {
-    qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes);
+    // linear part is not enough
+
+    // prepare TD up to linear length
+    qtd_init(p_qtd, fifo_info.ptr_lin, fifo_info.len_lin);
+
+    if ( !tu_offset4k((uint32_t) fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff)) )
+    {
+      // If buffer is aligned to 4K & buffer size is multiple of 4K
+      // We can make use of buffer page array to also combine the linear + wrapped length
+      p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
+
+      for(uint8_t i = 1, page = 0; i < 5; i++)
+      {
+        // pick up buffer array where linear ends
+        if (p_qtd->buffer[i] == 0)
+        {
+          p_qtd->buffer[i] = (uint32_t) fifo_info.ptr_wrap + 4096 * page;
+          page++;
+        }
+      }
+
+      CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
+    }
+    else
+    {
+      // TODO we need to carry the wrapped length after the linear part complete
+    }
   }
 
-  p_qtd->int_on_complete = true;
-  p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd
+  // Start qhd transfer
   p_qhd->ff = ff;
-
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
-  // start transfer
-  dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0));
+  qhd_start_xfer(rhport, epnum, dir);
 
   return true;
 }
@@ -582,6 +560,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
   }
   
   // only number of bytes in the IOC qtd
+  // TODO there is still a case with xfer_fifo with additional wrapped buffer to fullfil the requested length
   dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
 }
 

From d5f2c34eaa3e840b32817829031b95c6b7780314 Mon Sep 17 00:00:00 2001
From: szymonh <12231135+szymonh@users.noreply.github.com>
Date: Sun, 12 Sep 2021 20:09:58 +0200
Subject: [PATCH 0457/2085] Prevent buffer overflow in bth_device.c

---
 src/class/bth/bth_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index 1d27ae7c5..09fab953e 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -214,7 +214,7 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c
     }
     else return false;
 
-    return tud_control_xfer(rhport, request, &_btd_itf.hci_cmd, request->wLength);
+    return tud_control_xfer(rhport, request, &_btd_itf.hci_cmd, sizeof(_btd_itf.hci_cmd));
   }
   else if ( stage == CONTROL_STAGE_DATA )
   {

From ce5db06ba03f356b2049edc3b36aea398fa50036 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Sep 2021 12:05:49 +0700
Subject: [PATCH 0458/2085] clear PID along with clear stall

---
 src/portable/nuvoton/nuc121/dcd_nuc121.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index 5dfc77bb7..dbc5cd18a 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -200,11 +200,10 @@ static void bus_reset(void)
 }
 
 /* centralized location for USBD interrupt enable bit mask */
-#if USE_SOF
-static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk | USBD_INTSTS_SOFIF_Msk;
-#else
-static const uint32_t enabled_irqs = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk | USBD_INTSTS_USBIF_Msk;
-#endif
+enum {
+  ENABLED_IRQS = USBD_INTSTS_VBDETIF_Msk | USBD_INTSTS_BUSIF_Msk | USBD_INTSTS_SETUP_Msk |
+                 USBD_INTSTS_USBIF_Msk   | (USE_SOF ? USBD_INTSTS_SOFIF_Msk : 0)
+};
 
 /*
   NUC121/NUC125/NUC126 TinyUSB API driver implementation
@@ -226,8 +225,8 @@ void dcd_init(uint8_t rhport)
 
   usb_attach();
 
-  USBD->INTSTS = enabled_irqs;
-  USBD->INTEN  = enabled_irqs;
+  USBD->INTSTS = ENABLED_IRQS;
+  USBD->INTEN  = ENABLED_IRQS;
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -380,8 +379,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
   USBD_EP_T *ep = ep_entry(ep_addr, false);
-  ep->CFG |= USBD_CFG_CSTALL_Msk;
-  ep->CFG &=~USBD_CFG_DSQSYNC_Msk;
+  ep->CFG = (ep->CFG & ~USBD_CFG_DSQSYNC_Msk) | USBD_CFG_CSTALL_Msk;
 }
 
 void dcd_int_handler(uint8_t rhport)
@@ -389,7 +387,8 @@ void dcd_int_handler(uint8_t rhport)
   (void) rhport;
 
   // Mask non-enabled irqs, ex. SOF
-  uint32_t status = USBD->INTSTS & (enabled_irqs | 0xffffff00);
+  uint32_t status = USBD->INTSTS & (ENABLED_IRQS | 0xffffff00);
+
 #ifdef SUPPORT_LPM
   uint32_t state = USBD->ATTR & 0x300f;
 #else
@@ -520,7 +519,7 @@ void dcd_int_handler(uint8_t rhport)
   }
 
   /* acknowledge all interrupts */
-  USBD->INTSTS = status & enabled_irqs;
+  USBD->INTSTS = status & ENABLED_IRQS;
 }
 
 // Invoked when a control transfer's status stage is complete.

From 43e6555fd03906c4524f2f212199cdf32cb5fb0f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Sep 2021 13:09:38 +0700
Subject: [PATCH 0459/2085] clean up

---
 src/portable/nxp/transdimension/dcd_transdimension.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index a61f503f6..a7c4545c2 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -516,7 +516,8 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
     }
     else
     {
-      // TODO we need to carry the wrapped length after the linear part complete
+      // TODO we may need to carry the wrapped length after the linear part complete
+      // for now only transfer up to linear part
     }
   }
 
@@ -560,7 +561,6 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
   }
   
   // only number of bytes in the IOC qtd
-  // TODO there is still a case with xfer_fifo with additional wrapped buffer to fullfil the requested length
   dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
 }
 

From 50e3c0054f8d26340863667a50aae5a798f6aefc Mon Sep 17 00:00:00 2001
From: szymonh <12231135+szymonh@users.noreply.github.com>
Date: Mon, 13 Sep 2021 10:23:03 +0200
Subject: [PATCH 0460/2085] Add size check to tud_bt_hci_cmd_cb call in
 bth_device.c

---
 src/class/bth/bth_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index 09fab953e..b73f829cc 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -221,7 +221,7 @@ bool btd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t c
     // Handle class request only
     TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
 
-    if (tud_bt_hci_cmd_cb) tud_bt_hci_cmd_cb(&_btd_itf.hci_cmd, request->wLength);
+    if (tud_bt_hci_cmd_cb) tud_bt_hci_cmd_cb(&_btd_itf.hci_cmd, tu_min16(request->wLength, sizeof(_btd_itf.hci_cmd)));
   }
 
   return true;

From e64bfb9ff53647e21ba755c4ae4aa6bb3f2677ac Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Sep 2021 16:16:37 +0700
Subject: [PATCH 0461/2085] implement dcd_edpt_close_all(), pass chapter9 test
 suite (without remote wakeup)

---
 src/portable/espressif/esp32sx/dcd_esp32sx.c | 79 +++++++-------------
 1 file changed, 28 insertions(+), 51 deletions(-)

diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index a5ada0da8..541f7d586 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -92,11 +92,12 @@ static void bus_reset(void)
     USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
   }
 
-  USB0.dcfg &= ~USB_DEVADDR_M; // reset address
+  // clear device address
+  USB0.dcfg &= ~USB_DEVADDR_M;
 
-  USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M;
-  USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK;
-  USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/;
+  USB0.daintmsk = USB_OUTEPMSK0_M | USB_INEPMSK0_M;
+  USB0.doepmsk  = USB_SETUPMSK_M | USB_XFERCOMPLMSK;
+  USB0.diepmsk  = USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/;
 
   // "USB Data FIFOs" section in reference manual
   // Peripheral FIFO architecture
@@ -260,9 +261,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
   xfer->max_size = desc_edpt->wMaxPacketSize.size;
 
   if (dir == TUSB_DIR_OUT) {
-    out_ep[epnum].doepctl |= USB_USBACTEP0_M |
-                             desc_edpt->bmAttributes.xfer << USB_EPTYPE0_S |
-                             desc_edpt->wMaxPacketSize.size << USB_MPS0_S;
+    out_ep[epnum].doepctl |= USB_USBACTEP1_M |
+                             desc_edpt->bmAttributes.xfer << USB_EPTYPE1_S |
+                             (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_DO_SETD0PID1_M : 0) |
+                             desc_edpt->wMaxPacketSize.size << USB_MPS1_S;
     USB0.daintmsk |= (1 << (16 + epnum));
   } else {
     // "USB Data FIFOs" section in reference manual
@@ -315,7 +317,25 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
 void dcd_edpt_close_all(uint8_t rhport)
 {
   (void) rhport;
-  // TODO implement dcd_edpt_close_all()
+
+  usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
+  usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
+
+  // Disable non-control interrupt
+  USB0.daintmsk = USB_OUTEPMSK0_M | USB_INEPMSK0_M;
+
+  for(uint8_t n = 1; n < EP_MAX; n++)
+  {
+    // disable OUT endpoint
+    out_ep[n].doepctl = 0;
+    xfer_status[n][TUSB_DIR_OUT].max_size = 0;
+
+    // disable IN endpoint
+    in_ep[n].diepctl = 0;
+    xfer_status[n][TUSB_DIR_IN].max_size = 0;
+  }
+
+  _allocated_fifos = 1;
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
@@ -367,49 +387,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
 bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
 {
   (void)rhport;
-
-  // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
-  TU_ASSERT(ff->item_size == 1);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer       = NULL;
-  xfer->ff           = ff;
-  xfer->total_len    = total_bytes;
-  xfer->queued_len   = 0;
-  xfer->short_packet = false;
-
-  uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint8_t short_packet_size = total_bytes % xfer->max_size;
-
-  // Zero-size packet is special case.
-  if (short_packet_size > 0 || (total_bytes == 0)) {
-    num_packets++;
-  }
-
-  ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i",
-           epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"),
-           num_packets, total_bytes);
-
-  // IN and OUT endpoint xfers are interrupt-driven, we just schedule them
-  // here.
-  if (dir == TUSB_DIR_IN) {
-    // A full IN transfer (multiple packets, possibly) triggers XFRC.
-    USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes;
-    USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK
-
-    // Enable fifo empty interrupt only if there are something to put in the fifo.
-    if(total_bytes != 0) {
-      USB0.dtknqr4_fifoemptymsk |= (1 << epnum);
-    }
-  } else {
-    // Each complete packet for OUT xfers triggers XFRC.
-    USB0.out_ep_reg[epnum].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S);
-    USB0.out_ep_reg[epnum].doepctl  |= USB_EPENA0_M | USB_CNAK0_M;
-  }
-  return true;
 }
 #endif
 

From cdc63459ebf5bd979d1e98253abd3d75693dcdaf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Sep 2021 16:49:38 +0700
Subject: [PATCH 0462/2085] esp32sx implement dcd_remote_wakeup(), fully
 compliance to chapter9 test suite

---
 .../hid_composite_freertos/src/tusb_config.h  |  5 +--
 src/common/tusb_common.h                      |  2 +-
 src/portable/espressif/esp32sx/dcd_esp32sx.c  | 33 +++++++++++--------
 3 files changed, 23 insertions(+), 17 deletions(-)

diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index 4b0458ef0..4fbccc294 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -67,8 +67,9 @@
 // This examples use FreeRTOS
 #define CFG_TUSB_OS               OPT_OS_FREERTOS
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG           0
+#endif
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index d0cc41285..1899b35cc 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -380,7 +380,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
   }
 
   // not found return the key value in hex
-  sprintf(not_found, "0x%08lX", key);
+  sprintf(not_found, "0x%08lX", (unsigned long) key);
 
   return not_found;
 }
diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index 541f7d586..cfbbab233 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -42,10 +42,6 @@
 
 #include "device/dcd.h"
 
-// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
-// We disable SOF for now until needed later on
-#define USE_SOF     0
-
 // Max number of bi-directional endpoints including EP0
 // Note: ESP32S2 specs say there are only up to 5 IN active endpoints include EP0
 // We should probably prohibit enabling Endpoint IN > 4 (not done yet)
@@ -194,9 +190,6 @@ void dcd_init(uint8_t rhport)
   USB0.gintsts = ~0U; //clear pending ints
   USB0.gintmsk = USB_OTGINTMSK_M   |
                  USB_MODEMISMSK_M  |
-          #if USE_SOF
-                 USB_SOFMSK_M      |
-          #endif
                  USB_RXFLVIMSK_M   |
                  USB_ERLYSUSPMSK_M |
                  USB_USBSUSPMSK_M  |
@@ -221,8 +214,17 @@ void dcd_remote_wakeup(uint8_t rhport)
 {
   (void)rhport;
 
-  // TODO must manually clear this bit after 1-15 ms
-  // USB0.DCTL |= USB_RMTWKUPSIG_M;
+  // set remote wakeup
+  USB0.dctl |= USB_RMTWKUPSIG_M;
+
+  // enable SOF to detect bus resume
+  USB0.gintsts = USB_SOF_M;
+  USB0.gintmsk |= USB_SOFMSK_M;
+
+  // Per specs: remote wakeup signal bit must be clear within 1-15ms
+  vTaskDelay(pdMS_TO_TICKS(1));
+
+  USB0.dctl &= ~USB_RMTWKUPSIG_M;
 }
 
 // connect by enabling internal pull-up resistor on D+/D-
@@ -731,8 +733,8 @@ static void _dcd_int_handler(void* arg)
   (void) arg;
   uint8_t const rhport = 0;
 
-  const uint32_t int_status = USB0.gintsts;
-  //const uint32_t int_msk = USB0.gintmsk;
+  const uint32_t int_msk = USB0.gintmsk;
+  const uint32_t int_status = USB0.gintsts & int_msk;
 
   if (int_status & USB_USBRST_M) {
     // start of reset
@@ -785,12 +787,15 @@ static void _dcd_int_handler(void* arg)
     USB0.gotgint = otg_int;
   }
 
-#if USE_SOF
   if (int_status & USB_SOF_M) {
     USB0.gintsts = USB_SOF_M;
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); // do nothing actually
+
+    // Disable SOF interrupt since currently only used for remote wakeup detection
+    USB0.gintmsk &= ~USB_SOFMSK_M;
+
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
-#endif
+
 
   if (int_status & USB_RXFLVI_M) {
     // RXFLVL bit is read-only

From 1a87b605bd14404cdabd9f938a49e4e08c1adf95 Mon Sep 17 00:00:00 2001
From: szymonh <12231135+szymonh@users.noreply.github.com>
Date: Mon, 13 Sep 2021 13:21:25 +0200
Subject: [PATCH 0463/2085] Add support for Nucleo F412ZG

---
 .../stm32f412nucleo/STM32F412ZGTx_FLASH.ld    | 169 ++++++
 hw/bsp/stm32f4/boards/stm32f412nucleo/board.h | 119 +++++
 .../stm32f4/boards/stm32f412nucleo/board.mk   |  11 +
 .../stm32f412nucleo/stm32f4xx_hal_conf.h      | 493 ++++++++++++++++++
 4 files changed, 792 insertions(+)
 create mode 100644 hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
 create mode 100644 hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
 create mode 100644 hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
 create mode 100644 hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h

diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
new file mode 100644
index 000000000..b00b5dbe0
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
@@ -0,0 +1,169 @@
+/*
+*****************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Abstract    : Linker script for STM32F412ZGTx Device with
+**                1024KByte FLASH, 256KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+**  (c)Copyright Ac6.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Ac6 permit registered System Workbench for MCU users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the System Workbench for MCU toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20040000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
new file mode 100644
index 000000000..73c5f83b9
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h
@@ -0,0 +1,119 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_14
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART3
+#define UART_GPIO_PORT        GPIOD
+#define UART_GPIO_AF          GPIO_AF7_USART3
+#define UART_TX_PIN           GPIO_PIN_8
+#define UART_RX_PIN           GPIO_PIN_9
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+  /* Enable Power Control clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* The voltage scaling allows optimizing the power consumption when the
+   * device is clocked below the maximum system frequency, to update the
+   * voltage scaling value regarding system frequency refer to product
+   * datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
+  RCC_OscInitStruct.PLL.PLLN = 200;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Select PLLSAI output as USB clock source */
+  PeriphClkInitStruct.PLLI2S.PLLI2SM = 8;
+  PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4;
+  PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CK48;
+  PeriphClkInitStruct.Clk48ClockSelection = RCC_CK48CLKSOURCE_PLLI2SQ;
+  PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC;
+  PeriphClkInitStruct.PLLI2S.PLLI2SR = 7;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+   * clocks dividers */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+                                RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
+
+  // Enable clocks for LED, Button, Uart
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_USART3_CLK_ENABLE();
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
new file mode 100644
index 000000000..50973f737
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += -DSTM32F412Zx
+
+LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f412zg
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
new file mode 100644
index 000000000..7864f8d5f
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED         
+/* #define HAL_ADC_MODULE_ENABLED      */
+/* #define HAL_CAN_MODULE_ENABLED      */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
+/* #define HAL_CRC_MODULE_ENABLED      */ 
+/* #define HAL_CEC_MODULE_ENABLED      */ 
+/* #define HAL_CRYP_MODULE_ENABLED     */ 
+/* #define HAL_DAC_MODULE_ENABLED      */ 
+/* #define HAL_DCMI_MODULE_ENABLED     */ 
+#define HAL_DMA_MODULE_ENABLED 
+/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_ETH_MODULE_ENABLED      */
+#define HAL_FLASH_MODULE_ENABLED 
+/* #define HAL_NAND_MODULE_ENABLED     */
+/* #define HAL_NOR_MODULE_ENABLED      */
+/* #define HAL_PCCARD_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED     */
+/* #define HAL_SDRAM_MODULE_ENABLED    */
+/* #define HAL_HASH_MODULE_ENABLED     */  
+#define HAL_GPIO_MODULE_ENABLED
+/* #define HAL_EXTI_MODULE_ENABLED     */
+/* #define HAL_I2C_MODULE_ENABLED      */
+/* #define HAL_SMBUS_MODULE_ENABLED    */
+/* #define HAL_I2S_MODULE_ENABLED      */
+/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_LTDC_MODULE_ENABLED     */
+/* #define HAL_DSI_MODULE_ENABLED      */
+#define HAL_PWR_MODULE_ENABLED
+/* #define HAL_QSPI_MODULE_ENABLED     */
+#define HAL_RCC_MODULE_ENABLED      
+/* #define HAL_RNG_MODULE_ENABLED      */
+/* #define HAL_RTC_MODULE_ENABLED      */
+/* #define HAL_SAI_MODULE_ENABLED      */
+/* #define HAL_SD_MODULE_ENABLED       */
+// #define HAL_SPI_MODULE_ENABLED
+/* #define HAL_TIM_MODULE_ENABLED      */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_IRDA_MODULE_ENABLED     */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED     */
+#define HAL_CORTEX_MODULE_ENABLED   
+/* #define HAL_PCD_MODULE_ENABLED      */
+/* #define HAL_HCD_MODULE_ENABLED      */
+/* #define HAL_FMPI2C_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED  */
+/* #define HAL_DFSDM_MODULE_ENABLED    */
+/* #define HAL_LPTIM_MODULE_ENABLED    */
+/* #define HAL_MMC_MODULE_ENABLED      */
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000U)    
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */   
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/ 
+#define DP83848_PHY_ADDRESS             0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+  
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
+ 
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h" 
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+  
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */      
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+   
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

From 43aac7074be0d14e72cb04eaddcddf1a926c6a74 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Mon, 13 Sep 2021 22:16:34 +0700
Subject: [PATCH 0464/2085] Update supported.rst

---
 docs/reference/supported.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index d114d8405..daf5bce75 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -316,6 +316,7 @@ ST STM32
 -  `STM32 F411ce Black Pill <https://www.adafruit.com/product/4877>`__
 -  `STM32 F411ve Discovery <https://www.st.com/en/evaluation-tools/32f411ediscovery.html>`__
 -  `STM32 F412zg Discovery <https://www.st.com/en/evaluation-tools/32f412gdiscovery.html>`__
+-  `STM32 F412zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f412zg.html>`__
 -  `STM32 F723e Discovery <https://www.st.com/en/evaluation-tools/32f723ediscovery.html>`__
 -  `STM32 F746zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f746zg.html>`__
 -  `STM32 F746g Discovery <https://www.st.com/en/evaluation-tools/32f746gdiscovery.html>`__

From 2d6407e7a5e6c99280ce11f1b02ea4b75dda133f Mon Sep 17 00:00:00 2001
From: szymonh <12231135+szymonh@users.noreply.github.com>
Date: Mon, 13 Sep 2021 22:56:25 +0200
Subject: [PATCH 0465/2085] Enforced buffer boundaries for hid devices

---
 src/class/hid/hid_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 2ee80750a..55071a5ce 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -282,7 +282,7 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
           uint8_t const report_id   = tu_u16_low(request->wValue);
 
           uint8_t* report_buf = p_hid->epin_buf;
-          uint16_t req_len = request->wLength;
+          uint16_t req_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
 
           uint16_t xferlen = 0;
 
@@ -314,7 +314,7 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
           uint8_t const report_id   = tu_u16_low(request->wValue);
 
           uint8_t const* report_buf = p_hid->epout_buf;
-          uint16_t report_len = request->wLength;
+          uint16_t report_len = tu_min16(request->wLength, CFG_TUD_HID_EP_BUFSIZE);
 
           // If host request a specific Report ID, extract report ID in buffer before invoking callback
           if ( (report_id != HID_REPORT_TYPE_INVALID) && (report_len > 1) && (report_id == report_buf[0]) )

From 103a11d44973c587156bbd9db8502f2b99c7b71e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 14 Sep 2021 12:25:08 +0700
Subject: [PATCH 0466/2085] add host hid_controller to cmake all list

fix 1067
---
 examples/host/CMakeLists.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt
index f185ac4f8..5c63ec0c0 100644
--- a/examples/host/CMakeLists.txt
+++ b/examples/host/CMakeLists.txt
@@ -7,3 +7,4 @@ family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
 
 # family_add_subdirectory will filter what to actually add based on selected FAMILY
 family_add_subdirectory(cdc_msc_hid)
+family_add_subdirectory(hid_controller)

From 5404d6d8ae02fac16eb8dbfd4a9d15de8e6c1342 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 14 Sep 2021 12:47:20 +0700
Subject: [PATCH 0467/2085] usbd pre-compute total interface length without
 replying on driver open

---
 src/device/usbd.c | 18 ++++++++----------
 src/host/usbh.c   |  2 +-
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 4ab60569b..a5773c625 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -880,7 +880,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
 
   // Parse configuration descriptor
   _usbd_dev.remote_wakeup_support = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP) ? 1 : 0;
-  _usbd_dev.self_powered = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_SELF_POWERED) ? 1 : 0;
+  _usbd_dev.self_powered          = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_SELF_POWERED ) ? 1 : 0;
 
   // Parse interface descriptor
   uint8_t const * p_desc   = ((uint8_t const*) desc_cfg) + sizeof(tusb_desc_configuration_t);
@@ -900,26 +900,22 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
 
     tusb_desc_interface_t const * desc_itf = (tusb_desc_interface_t const*) p_desc;
-    uint16_t const remaining_len = desc_end-p_desc;
 
     // Interface number must not be used already
     TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[desc_itf->bInterfaceNumber]);
 
-    // TODO usbd can calculate the total length used for driver --> driver open() does not need to calculate it
-    // uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, desc_end-p_desc);
+    uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, desc_end-p_desc);
+    TU_ASSERT(drv_len);
 
     // Find driver for this interface
     uint8_t drv_id;
     for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
     {
       usbd_class_driver_t const *driver = get_driver(drv_id);
-      uint16_t const drv_len = driver->open(rhport, desc_itf, remaining_len);
 
-      if ( drv_len > 0 )
+      if ( driver->open(rhport, desc_itf, drv_len) )
       {
         // Open successfully, check if length is correct
-        TU_ASSERT( sizeof(tusb_desc_interface_t) <= drv_len && drv_len <= remaining_len);
-
         TU_LOG2("  %s opened\r\n", driver->name);
 
         // bind interface to found driver
@@ -941,14 +937,16 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
         // bind all endpoints to found driver
         tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id);
 
-        p_desc += drv_len; // next interface
 
         break; // exit driver find loop
       }
     }
 
-    // Failed if cannot find supported driver
+    // Failed if there is no supported drivers
     TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT);
+
+    // next Interface or IAD descriptor
+    p_desc += drv_len;
   }
 
   // invoke callback
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 51b8f85b6..886a120a8 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -989,7 +989,7 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
     if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
     {
       desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
-      p_desc = tu_desc_next(p_desc);
+      p_desc = tu_desc_next(p_desc); // next to Interface
     }
 
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );

From 36391680660f1ec0960003eece7e7605c29574af Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 14 Sep 2021 11:58:22 +0200
Subject: [PATCH 0468/2085] Fix warning.

---
 src/device/usbd.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 4ab60569b..1184f8e47 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1041,6 +1041,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
     break;
 
     case TUSB_DESC_DEVICE_QUALIFIER:
+    {
       TU_LOG2(" Device Qualifier\r\n");
 
       TU_VERIFY( tud_descriptor_device_qualifier_cb );
@@ -1050,6 +1051,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
       // first byte of descriptor is its size
       return tud_control_xfer(rhport, p_request, (void*) desc_qualifier, desc_qualifier[0]);
+    }
     break;
 
     default: return false;

From 25ea8f9c9e65d1617382a7896df07afd0dc90ce3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 14 Sep 2021 21:02:38 +0700
Subject: [PATCH 0469/2085] update configuration parser

---
 .../audio_4_channel_mic/src/usb_descriptors.c | 13 ++++--
 src/class/msc/msc_device.c                    |  2 +-
 src/device/usbd.c                             | 44 ++++++++++--------
 src/host/usbh.c                               | 46 +++++++++++--------
 src/tusb.c                                    |  2 +-
 src/tusb_option.h                             | 24 ++++++++++
 6 files changed, 85 insertions(+), 46 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index 018919bf3..2b66bfe34 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -81,12 +81,15 @@ enum
 
 #define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_FOUR_CH_DESC_LEN)
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
-// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
-// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
-#define EPNUM_AUDIO   0x03
+#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_AUDIO   0x03
+#elif TU_CHECK_MCU(NRF5X)
+  // nRF5x ISO can only be endpoint 8
+  #define EPNUM_AUDIO   0x08
 #else
-#define EPNUM_AUDIO   0x01
+  #define EPNUM_AUDIO   0x01
 #endif
 
 uint8_t const desc_configuration[] =
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 0fd592129..765760fd1 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -258,7 +258,7 @@ uint16_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
   // msc driver length is fixed
   uint16_t const drv_len = sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t);
 
-  // Max length mus be at least 1 interface + 2 endpoints
+  // Max length must be at least 1 interface + 2 endpoints
   TU_ASSERT(max_len >= drv_len, 0);
 
   mscd_interface_t * p_msc = &_mscd_itf;
diff --git a/src/device/usbd.c b/src/device/usbd.c
index a5773c625..2874dc5eb 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -888,23 +888,40 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
 
   while( p_desc < desc_end )
   {
-    tusb_desc_interface_assoc_t const * desc_iad = NULL;
+    uint8_t assoc_itf_count = 1;
 
     // Class will always starts with Interface Association (if any) and then Interface descriptor
     if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
     {
-      desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
+      tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
+      assoc_itf_count = desc_iad->bInterfaceCount;
+
       p_desc = tu_desc_next(p_desc); // next to Interface
+
+      // IAD's first interface number and class should match with opened interface
+      //TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber &&
+      //          desc_iad->bFunctionClass  == desc_itf->bInterfaceClass);
     }
 
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
-
     tusb_desc_interface_t const * desc_itf = (tusb_desc_interface_t const*) p_desc;
 
     // Interface number must not be used already
     TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[desc_itf->bInterfaceNumber]);
 
-    uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, desc_end-p_desc);
+#if CFG_TUD_MIDI
+    // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD
+    // manually increase the associated count
+    if (1                              == assoc_itf_count              &&
+        TUSB_CLASS_AUDIO               == desc_itf->bInterfaceClass    &&
+        AUDIO_SUBCLASS_CONTROL         == desc_itf->bInterfaceSubClass &&
+        AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol)
+    {
+      assoc_itf_count = 2;
+    }
+#endif
+
+    uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
     TU_ASSERT(drv_len);
 
     // Find driver for this interface
@@ -915,29 +932,18 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
 
       if ( driver->open(rhport, desc_itf, drv_len) )
       {
-        // Open successfully, check if length is correct
+        // Open successfully
         TU_LOG2("  %s opened\r\n", driver->name);
 
-        // bind interface to found driver
-        _usbd_dev.itf2drv[desc_itf->bInterfaceNumber] = drv_id;
-
-        // If using IAD, bind all interfaces to the same driver
-        if (desc_iad)
+        // bind (associated) interfaces to found driver
+        for(uint8_t i=0; i<assoc_itf_count; i++)
         {
-          // IAD's first interface number and class should match with opened interface
-          TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber &&
-                    desc_iad->bFunctionClass  == desc_itf->bInterfaceClass);
-
-          for(uint8_t i=1; i<desc_iad->bInterfaceCount; i++)
-          {
-            _usbd_dev.itf2drv[desc_itf->bInterfaceNumber+i] = drv_id;
-          }
+          _usbd_dev.itf2drv[desc_itf->bInterfaceNumber+i] = drv_id;
         }
 
         // bind all endpoints to found driver
         tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id);
 
-
         break; // exit driver find loop
       }
     }
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 886a120a8..14e71379b 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -982,24 +982,40 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
   // parse each interfaces
   while( p_desc < desc_end )
   {
-    // TODO Do we need to use IAD
-     tusb_desc_interface_assoc_t const * desc_iad = NULL;
+    uint8_t assoc_itf_count = 1;
 
     // Class will always starts with Interface Association (if any) and then Interface descriptor
     if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
     {
-      desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
+      tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
+      assoc_itf_count = desc_iad->bInterfaceCount;
+
       p_desc = tu_desc_next(p_desc); // next to Interface
+
+      // IAD's first interface number and class should match with opened interface
+      //TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber &&
+      //          desc_iad->bFunctionClass  == desc_itf->bInterfaceClass);
     }
 
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
-
     tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
 
     // Interface number must not be used already
-    TU_ASSERT( dev->itf2drv[desc_itf->bInterfaceNumber] == DRVID_INVALID );
+    TU_ASSERT( DRVID_INVALID == dev->itf2drv[desc_itf->bInterfaceNumber] );
 
-    uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, desc_iad ? desc_iad->bInterfaceCount : 1, desc_end-p_desc);
+#if CFG_TUH_MIDI
+    // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD
+    // manually increase the associated count
+    if (1                              == assoc_itf_count              &&
+        TUSB_CLASS_AUDIO               == desc_itf->bInterfaceClass    &&
+        AUDIO_SUBCLASS_CONTROL         == desc_itf->bInterfaceSubClass &&
+        AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol)
+    {
+      assoc_itf_count = 2;
+    }
+#endif
+
+    uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
     TU_ASSERT(drv_len);
 
     if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && dev->hub_addr != 0)
@@ -1019,22 +1035,12 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
         if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
         {
           // open successfully
-          TU_LOG2("  Opened successfully\r\n");
+          TU_LOG2("  %s opened\r\n", driver->name);
 
-          // bind interface to found driver
-          dev->itf2drv[desc_itf->bInterfaceNumber] = drv_id;
-
-          // If using IAD, bind all interfaces to the same driver
-          if (desc_iad)
+          // bind (associated) interfaces to found driver
+          for(uint8_t i=0; i<assoc_itf_count; i++)
           {
-            // IAD's first interface number and class should match with opened interface
-            TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber &&
-                      desc_iad->bFunctionClass  == desc_itf->bInterfaceClass);
-
-            for(uint8_t i=1; i<desc_iad->bInterfaceCount; i++)
-            {
-              dev->itf2drv[desc_itf->bInterfaceNumber+i] = drv_id;
-            }
+            dev->itf2drv[desc_itf->bInterfaceNumber+i] = drv_id;
           }
 
           // bind all endpoints to found driver
diff --git a/src/tusb.c b/src/tusb.c
index 6494287d2..5c6adad24 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -121,7 +121,7 @@ void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_
       ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id;
     }
 
-    len    = (uint16_t)(len + tu_desc_len(p_desc));
+    len   += (uint16_t) tu_desc_len(p_desc);
     p_desc = tu_desc_next(p_desc);
   }
 }
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a00f3489f..4d7e1e9d2 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -278,6 +278,30 @@
   //------------- CLASS -------------//
 #endif // TUSB_OPT_HOST_ENABLED
 
+#ifndef CFG_TUH_HUB
+#define CFG_TUH_HUB    0
+#endif
+
+#ifndef CFG_TUH_CDC
+#define CFG_TUH_CDC    0
+#endif
+
+#ifndef CFG_TUH_HID
+#define CFG_TUH_HID    0
+#endif
+
+#ifndef CFG_TUH_MIDI
+#define CFG_TUH_MIDI   0
+#endif
+
+#ifndef CFG_TUH_MSC
+#define CFG_TUH_MSC    0
+#endif
+
+#ifndef CFG_TUH_VENDOR
+#define CFG_TUH_VENDOR 0
+#endif
+
 //--------------------------------------------------------------------+
 // Port Specific
 // TUP stand for TinyUSB Port (can be renamed)

From b4745222457d2a2c6c6e6a0747dd6082557c4c8e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 14 Sep 2021 21:30:38 +0700
Subject: [PATCH 0470/2085] make vendor driver more flexible

- skip additional custom descriptor between interface and endpoints
- can have up to 2 bulk endpoint ( 1 in & 1 out)
---
 src/class/vendor/vendor_device.c | 40 +++++++++++++++++++-------------
 src/device/usbd.c                |  2 +-
 src/host/usbh.c                  |  2 +-
 3 files changed, 26 insertions(+), 18 deletions(-)

diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 8c59b4ea7..c73ca2538 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -175,12 +175,12 @@ void vendord_reset(uint8_t rhport)
   }
 }
 
-uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
+uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len)
 {
-  TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass, 0);
+  TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0);
 
-  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + itf_desc->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
-  TU_VERIFY(max_len >= drv_len, 0);
+  uint16_t drv_len = tu_desc_len(desc_itf);
+  uint8_t const * p_desc = tu_desc_next(desc_itf);
 
   // Find available interface
   vendord_interface_t* p_vendor = NULL;
@@ -194,21 +194,29 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, ui
   }
   TU_VERIFY(p_vendor, 0);
 
-  // Open endpoint pair with usbd helper
-  TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(itf_desc), 2, TUSB_XFER_BULK, &p_vendor->ep_out, &p_vendor->ep_in), 0);
-
-  p_vendor->itf_num = itf_desc->bInterfaceNumber;
-
-  // Prepare for incoming data
-  if ( !usbd_edpt_xfer(rhport, p_vendor->ep_out, p_vendor->epout_buf, sizeof(p_vendor->epout_buf)) )
+  p_vendor->itf_num = desc_itf->bInterfaceNumber;
+  if (desc_itf->bNumEndpoints)
   {
-    TU_LOG_FAILED();
-    TU_BREAKPOINT();
+    // skip non-endpoint descriptors
+    while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (drv_len <= max_len) )
+    {
+      drv_len += tu_desc_len(p_desc);
+      p_desc   = tu_desc_next(p_desc);
+    }
+
+    // Open endpoint pair with usbd helper
+    TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_BULK, &p_vendor->ep_out, &p_vendor->ep_in), 0);
+
+    // Prepare for incoming data
+    if ( p_vendor->ep_out )
+    {
+      TU_ASSERT(usbd_edpt_xfer(rhport, p_vendor->ep_out, p_vendor->epout_buf, sizeof(p_vendor->epout_buf)), 0);
+    }
+
+    if ( p_vendor->ep_in ) maybe_transmit(p_vendor);
   }
 
-  maybe_transmit(p_vendor);
-
-  return drv_len;
+  return (uint16_t) true;
 }
 
 bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 2874dc5eb..f23d3048d 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -922,7 +922,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
 #endif
 
     uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
-    TU_ASSERT(drv_len);
+    TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
     // Find driver for this interface
     uint8_t drv_id;
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 14e71379b..100a17aa4 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1016,7 +1016,7 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
 #endif
 
     uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
-    TU_ASSERT(drv_len);
+    TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
     if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && dev->hub_addr != 0)
     {

From a23944035dab67a206edad9e31e3ee7400b68bbb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 15 Sep 2021 00:51:01 +0700
Subject: [PATCH 0471/2085] correct assoc_itf_count for bth driver

---
 src/device/usbd.c | 11 +++++++++++
 src/device/usbd.h |  1 +
 2 files changed, 12 insertions(+)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index f23d3048d..f7846cc0a 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -921,6 +921,17 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
     }
 #endif
 
+#if CFG_TUD_BTH && CFG_TUD_BTH_ISO_ALT_COUNT
+    // BTH implementation currently does not use IAD. TODO should also use IAD for composite device
+    if (1                                  == assoc_itf_count              &&
+        TUD_BT_APP_CLASS                   == desc_itf->bInterfaceClass    &&
+        TUD_BT_APP_SUBCLASS                == desc_itf->bInterfaceSubClass &&
+        TUD_BT_PROTOCOL_PRIMARY_CONTROLLER == desc_itf->bInterfaceProtocol)
+    {
+      assoc_itf_count = 2;
+    }
+#endif
+
     uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 638d93094..c83509234 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -777,6 +777,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 // BT Primary controller descriptor
 // Interface number, string index, attributes, event endpoint, event endpoint size, interval, data in, data out, data endpoint size, iso endpoint sizes
+// TODO BTH should also use IAD like CDC for composite device
 #define TUD_BTH_DESCRIPTOR(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size,...) \
   TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \
   TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__)

From 0ded1c5bacfba180bb5f6fef2f7cb469adbe19f6 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Tue, 14 Sep 2021 21:08:12 +0200
Subject: [PATCH 0472/2085] Reset EP flags on close.

---
 src/device/usbd.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 1184f8e47..3043fc7bc 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1379,7 +1379,13 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   TU_ASSERT(dcd_edpt_close, /**/);
   TU_LOG2("  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
 
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
   dcd_edpt_close(rhport, ep_addr);
+  _usbd_dev.ep_status[epnum][dir].stalled = false;
+  _usbd_dev.ep_status[epnum][dir].busy = false;
+  _usbd_dev.ep_status[epnum][dir].claimed = false;
 
   return;
 }

From 93ed3034c01d1b7b312acf5e8c79475e0dc516f9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 15 Sep 2021 18:35:52 +0700
Subject: [PATCH 0473/2085] merge master and minor clean up

---
 src/portable/nxp/khci/dcd_khci.c | 59 ++++++++++++++++++++++----------
 1 file changed, 40 insertions(+), 19 deletions(-)

diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 2ba063ff2..69bd07eb0 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -52,23 +52,23 @@ typedef struct TU_ATTR_PACKED
     struct {
       union {
         struct {
-          uint16_t          :  2;
-          uint16_t tok_pid  :  4;
-          uint16_t data     :  1;
-          uint16_t own      :  1;
-          uint16_t          :  8;
+               uint16_t           :  2;
+          __IO uint16_t tok_pid   :  4;
+               uint16_t data      :  1;
+          __IO uint16_t own       :  1;
+               uint16_t           :  8;
         };
         struct {
-          uint16_t          :  2;
-          uint16_t bdt_stall:  1;
-          uint16_t dts      :  1;
-          uint16_t ninc     :  1;
-          uint16_t keep     :  1;
-          uint16_t          : 10;
+               uint16_t           :  2;
+               uint16_t bdt_stall :  1;
+               uint16_t dts       :  1;
+               uint16_t ninc      :  1;
+               uint16_t keep      :  1;
+               uint16_t           : 10;
         };
       };
-      uint16_t bc          : 10;
-      uint16_t             :  6;
+      __IO uint16_t bc : 10;
+           uint16_t    :  6;
     };
   };
   uint8_t *addr;
@@ -145,12 +145,17 @@ static void process_tokdne(uint8_t rhport)
 {
   const unsigned s = KHCI->STAT;
   KHCI->ISTAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
+
+  uint8_t const epnum = (s >> USB_STAT_ENDP_SHIFT);
+  uint8_t const dir   = (s & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT;
+
   buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
   endpoint_state_t    *ep = &_dcd.endpoint_unified[s >> 3];
   unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0;
 
   /* fetch pid before discarded by the next steps */
   const unsigned pid = bd->tok_pid;
+
   /* reset values for a next transfer */
   bd->bdt_stall = 0;
   bd->dts       = 1;
@@ -181,7 +186,7 @@ static void process_tokdne(uint8_t rhport)
   }
   const unsigned length = ep->length;
   dcd_event_xfer_complete(rhport,
-                          ((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT),
+                          tu_edpt_addr(epnum, dir),
                           length - remaining, XFER_RESULT_SUCCESS, true);
   if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) {
     /* After completion a ZLP of control transfer,
@@ -414,6 +419,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
   bd->addr = buffer;
   __DSB();
   bd->own  = 1; /* This bit must be set last */
+
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
   return true;
 }
@@ -422,18 +428,22 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
   const unsigned epn = tu_edpt_number(ep_addr);
+
   if (0 == epn) {
     KHCI->ENDPOINT[epn].ENDPT |=  USB_ENDPT_EPSTALL_MASK;
   } else {
     const unsigned dir      = tu_edpt_dir(ep_addr);
     const unsigned odd      = _dcd.endpoint[epn][dir].odd;
     buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][odd];
-    TU_VERIFY(0 == bd->own,);
+    TU_ASSERT(0 == bd->own,);
+
     const unsigned ie       = NVIC_GetEnableIRQ(USB0_IRQn);
     NVIC_DisableIRQ(USB0_IRQn);
+
     bd->bdt_stall = 1;
     __DSB();
     bd->own       = 1; /* This bit must be set last */
+
     if (ie) NVIC_EnableIRQ(USB0_IRQn);
   }
 }
@@ -447,15 +457,20 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   const unsigned odd      = _dcd.endpoint[epn][dir].odd;
   buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
   TU_VERIFY(bd[odd].own,);
+
   const unsigned ie       = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
+
   bd[odd].own = 0;
   __DSB();
+
+  // clear stall
   bd[odd].bdt_stall  = 0;
-  if (bd[odd].data) {
-    bd[odd    ].data = 0;
-    bd[odd ^ 1].data = 1;
-  }
+
+  // Reset data toggle
+  bd[odd    ].data = 0;
+  bd[odd ^ 1].data = 1;
+
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
 }
 
@@ -470,6 +485,7 @@ void dcd_int_handler(uint8_t rhport)
   uint32_t msk = KHCI->INTEN;
   KHCI->ISTAT = is & ~msk;
   is &= msk;
+
   if (is & USB_ISTAT_ERROR_MASK) {
     /* TODO: */
     uint32_t es = KHCI->ERRSTAT;
@@ -483,26 +499,31 @@ void dcd_int_handler(uint8_t rhport)
     process_bus_reset(rhport);
     return;
   }
+
   if (is & USB_ISTAT_SLEEP_MASK) {
     KHCI->ISTAT = USB_ISTAT_SLEEP_MASK;
     process_bus_inactive(rhport);
     return;
   }
+
   if (is & USB_ISTAT_RESUME_MASK) {
     KHCI->ISTAT = USB_ISTAT_RESUME_MASK;
     process_bus_active(rhport);
     return;
   }
+
   if (is & USB_ISTAT_SOFTOK_MASK) {
     KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK;
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
     return;
   }
+
   if (is & USB_ISTAT_STALL_MASK) {
     KHCI->ISTAT = USB_ISTAT_STALL_MASK;
     process_stall(rhport);
     return;
   }
+
   if (is & USB_ISTAT_TOKDNE_MASK) {
     process_tokdne(rhport);
     return;

From ecbe8c3376038317269c30af6d47a399e4f6b6d5 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 13 Sep 2021 23:46:14 +0900
Subject: [PATCH 0474/2085] Change default LED state to off

---
 hw/bsp/frdm_kl25z/frdm_kl25z.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c
index 7d3a173ed..7cfbaab85 100644
--- a/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c
@@ -84,7 +84,7 @@ void board_init(void)
   PORT_SetPinMux(LED_PIN_PORT, LED_PIN, LED_PIN_FUNCTION);
   gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
   GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
-  board_led_write(true);
+  board_led_write(false);
 
   // UART
   CLOCK_EnableClock(UART_PIN_CLOCK);

From 46bb821753e677e5048f31c07fb26e2427f79ac2 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 15 Sep 2021 20:21:30 +0900
Subject: [PATCH 0475/2085] Add J1-19 pin setting as a button

---
 hw/bsp/frdm_kl25z/frdm_kl25z.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c
index 7cfbaab85..cdc996bc2 100644
--- a/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c
@@ -54,6 +54,14 @@ void USB0_IRQHandler(void)
 #define LED_PIN_FUNCTION      kPORT_MuxAsGpio
 #define LED_STATE_ON          0
 
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN_CLOCK      kCLOCK_PortC
+#define BUTTON_PIN_PORT       PORTC
+#define BUTTON_PIN            9U
+#define BUTTON_PIN_FUNCTION   kPORT_MuxAsGpio
+#define BUTTON_STATE_ACTIVE   0
+
 // UART
 #define UART_PORT             UART0
 #define UART_PIN_CLOCK        kCLOCK_PortA
@@ -86,6 +94,18 @@ void board_init(void)
   GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
   board_led_write(false);
 
+#if defined(BUTTON_PORT) && defined(BUTTON_PIN)
+  // Button
+  CLOCK_EnableClock(BUTTON_PIN_CLOCK);
+  port_pin_config_t button_port = {
+    .pullSelect = kPORT_PullUp, 
+    .mux = BUTTON_PIN_FUNCTION,
+  };
+  PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port);
+  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
+  GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config);
+#endif
+
   // UART
   CLOCK_EnableClock(UART_PIN_CLOCK);
   PORT_SetPinMux(UART_PIN_PORT, UART_PIN_RX, UART_PIN_FUNCTION);
@@ -119,6 +139,9 @@ void board_led_write(bool state)
 
 uint32_t board_button_read(void)
 {
+#if defined(BUTTON_PORT) && defined(BUTTON_PIN)
+  return BUTTON_STATE_ACTIVE == GPIO_ReadPinInput(BUTTON_PORT, BUTTON_PIN);
+#endif
   return 0;
 }
 

From fbe1bf375c8240e2d97683346fedd1a557cafdc0 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 15 Sep 2021 21:28:36 +0900
Subject: [PATCH 0476/2085] Fix stall interrupt handling

---
 src/portable/nxp/khci/dcd_khci.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 69bd07eb0..1c3af3433 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -134,10 +134,20 @@ static void prepare_next_setup_packet(uint8_t rhport)
 
 static void process_stall(uint8_t rhport)
 {
-  if (KHCI->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK) {
+  unsigned endpt;
+  endpt = KHCI->ENDPOINT[0].ENDPT;
+  if (endpt & USB_ENDPT_EPSTALL_MASK) {
     /* clear stall condition of the control pipe */
     prepare_next_setup_packet(rhport);
-    KHCI->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
+    KHCI->ENDPOINT[0].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK;
+    return;
+  }
+  for (int i = 1; i < 16; ++i) {
+    endpt = KHCI->ENDPOINT[i].ENDPT;
+    if (endpt & USB_ENDPT_EPSTALL_MASK) {
+      KHCI->ENDPOINT[i].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK;
+      return;
+    }
   }
 }
 
@@ -471,6 +481,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   bd[odd    ].data = 0;
   bd[odd ^ 1].data = 1;
 
+  const unsigned endpt = KHCI->ENDPOINT[epn].ENDPT;
+  if (endpt & USB_ENDPT_EPSTALL_MASK)
+    KHCI->ENDPOINT[epn].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK;
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
 }
 

From 8dfe0898e7daa551d7d320df5398ef92a4b28ea3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Sep 2021 00:43:10 +0700
Subject: [PATCH 0477/2085] minor update to dcd khci

---
 src/portable/nxp/khci/dcd_khci.c | 83 +++++++++++++++++---------------
 1 file changed, 43 insertions(+), 40 deletions(-)

diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 1c3af3433..3a62ff01e 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -120,10 +120,8 @@ static void prepare_next_setup_packet(uint8_t rhport)
 {
   const unsigned out_odd = _dcd.endpoint[0][0].odd;
   const unsigned in_odd  = _dcd.endpoint[0][1].odd;
-  if (_dcd.bdt[0][0][out_odd].own) {
-    //    TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd);
-    return;
-  }
+  TU_ASSERT(0 == _dcd.bdt[0][0][out_odd].own, );
+
   _dcd.bdt[0][0][out_odd].data     = 0;
   _dcd.bdt[0][0][out_odd ^ 1].data = 1;
   _dcd.bdt[0][1][in_odd].data      = 1;
@@ -134,19 +132,15 @@ static void prepare_next_setup_packet(uint8_t rhport)
 
 static void process_stall(uint8_t rhport)
 {
-  unsigned endpt;
-  endpt = KHCI->ENDPOINT[0].ENDPT;
-  if (endpt & USB_ENDPT_EPSTALL_MASK) {
-    /* clear stall condition of the control pipe */
-    prepare_next_setup_packet(rhport);
-    KHCI->ENDPOINT[0].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK;
-    return;
-  }
-  for (int i = 1; i < 16; ++i) {
-    endpt = KHCI->ENDPOINT[i].ENDPT;
+  for (int i = 0; i < 16; ++i) {
+    unsigned const endpt = KHCI->ENDPOINT[i].ENDPT;
+
     if (endpt & USB_ENDPT_EPSTALL_MASK) {
+      // prepare next setup if endpoint0
+      if ( i == 0 ) prepare_next_setup_packet(rhport);
+
+      // clear stall bit
       KHCI->ENDPOINT[i].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK;
-      return;
     }
   }
 }
@@ -158,10 +152,10 @@ static void process_tokdne(uint8_t rhport)
 
   uint8_t const epnum = (s >> USB_STAT_ENDP_SHIFT);
   uint8_t const dir   = (s & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT;
+  unsigned const odd  = (s & USB_STAT_ODD_MASK) ? 1 : 0;
 
   buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
   endpoint_state_t    *ep = &_dcd.endpoint_unified[s >> 3];
-  unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0;
 
   /* fetch pid before discarded by the next steps */
   const unsigned pid = bd->tok_pid;
@@ -241,21 +235,27 @@ static void process_bus_reset(uint8_t rhport)
   dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
 }
 
-static void process_bus_inactive(uint8_t rhport)
+static void process_bus_sleep(uint8_t rhport)
 {
-  (void) rhport;
+  // Enable resume & disable suspend interrupt
   const unsigned inten = KHCI->INTEN;
+
   KHCI->INTEN    = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
+  //KHCI->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK;
   KHCI->USBCTRL |= USB_USBCTRL_SUSP_MASK;
+
   dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
 }
 
-static void process_bus_active(uint8_t rhport)
+static void process_bus_resume(uint8_t rhport)
 {
-  (void) rhport;
-  KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
+  // Enable suspend & disable resume interrupt
   const unsigned inten = KHCI->INTEN;
+
+  KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
+  //KHCI->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK;
   KHCI->INTEN    = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
+
   dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
 }
 
@@ -268,12 +268,16 @@ void dcd_init(uint8_t rhport)
 
   KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
   while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
+
   tu_memclr(&_dcd, sizeof(_dcd));
   KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
   KHCI->BDTPAGE1 = (uint8_t)((uintptr_t)_dcd.bdt >>  8);
   KHCI->BDTPAGE2 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
   KHCI->BDTPAGE3 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
 
+  KHCI->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK |
+    USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
+
   dcd_connect(rhport);
   NVIC_ClearPendingIRQ(USB0_IRQn);
 }
@@ -281,8 +285,6 @@ void dcd_init(uint8_t rhport)
 void dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
-  KHCI->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK |
-    USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
   NVIC_EnableIRQ(USB0_IRQn);
 }
 
@@ -290,23 +292,24 @@ void dcd_int_disable(uint8_t rhport)
 {
   (void) rhport;
   NVIC_DisableIRQ(USB0_IRQn);
-  KHCI->INTEN = 0;
 }
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
-  (void) rhport;
-  _dcd.addr = dev_addr & 0x7F;
-  /* Response with status first before changing device address */
+  _dcd.addr = dev_addr & 0x7F; 
+ /* Response with status first before changing device address */
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
 
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
-  unsigned cnt = SystemCoreClock / 100;
+
   KHCI->CTL |= USB_CTL_RESUME_MASK;
+
+  unsigned cnt = SystemCoreClock / 1000;
   while (cnt--) __NOP();
+
   KHCI->CTL &= ~USB_CTL_RESUME_MASK;
 }
 
@@ -481,9 +484,12 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   bd[odd    ].data = 0;
   bd[odd ^ 1].data = 1;
 
+  // We already cleared this in ISR, but just clear it here to be safe
   const unsigned endpt = KHCI->ENDPOINT[epn].ENDPT;
-  if (endpt & USB_ENDPT_EPSTALL_MASK)
+  if (endpt & USB_ENDPT_EPSTALL_MASK) {
     KHCI->ENDPOINT[epn].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK;
+  }
+
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
 }
 
@@ -492,10 +498,10 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 //--------------------------------------------------------------------+
 void dcd_int_handler(uint8_t rhport)
 {
-  (void) rhport;
-
   uint32_t is  = KHCI->ISTAT;
   uint32_t msk = KHCI->INTEN;
+
+  // clear non-enabled interrupts
   KHCI->ISTAT = is & ~msk;
   is &= msk;
 
@@ -504,42 +510,39 @@ void dcd_int_handler(uint8_t rhport)
     uint32_t es = KHCI->ERRSTAT;
     KHCI->ERRSTAT = es;
     KHCI->ISTAT   = is; /* discard any pending events */
-    return;
   }
 
   if (is & USB_ISTAT_USBRST_MASK) {
     KHCI->ISTAT = is; /* discard any pending events */
     process_bus_reset(rhport);
-    return;
   }
 
   if (is & USB_ISTAT_SLEEP_MASK) {
+    TU_LOG_LOCATION();
+    TU_LOG2_HEX(is);
     KHCI->ISTAT = USB_ISTAT_SLEEP_MASK;
-    process_bus_inactive(rhport);
-    return;
+    process_bus_sleep(rhport);
   }
 
   if (is & USB_ISTAT_RESUME_MASK) {
+    TU_LOG_LOCATION();
+    TU_LOG2_HEX(is);
     KHCI->ISTAT = USB_ISTAT_RESUME_MASK;
-    process_bus_active(rhport);
-    return;
+    process_bus_resume(rhport);
   }
 
   if (is & USB_ISTAT_SOFTOK_MASK) {
     KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK;
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-    return;
   }
 
   if (is & USB_ISTAT_STALL_MASK) {
     KHCI->ISTAT = USB_ISTAT_STALL_MASK;
     process_stall(rhport);
-    return;
   }
 
   if (is & USB_ISTAT_TOKDNE_MASK) {
     process_tokdne(rhport);
-    return;
   }
 }
 

From c65cc75c6b9369a384e3266ce28ea043607230d2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Sep 2021 00:44:39 +0700
Subject: [PATCH 0478/2085] use correct resume detection for kl25z

---
 src/portable/nxp/khci/dcd_khci.c | 30 +++++++++++++++++++-----------
 1 file changed, 19 insertions(+), 11 deletions(-)

diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 3a62ff01e..3bb40aeb2 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -210,7 +210,8 @@ static void process_bus_reset(uint8_t rhport)
   KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
   KHCI->CTL     |= USB_CTL_ODDRST_MASK;
   KHCI->ADDR     = 0;
-  KHCI->INTEN    = (KHCI->INTEN & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
+  KHCI->INTEN    = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | USB_INTEN_SLEEPEN_MASK |
+                   USB_INTEN_ERROREN_MASK  | USB_INTEN_STALLEN_MASK;
 
   KHCI->ENDPOINT[0].ENDPT = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
   for (unsigned i = 1; i < 16; ++i) {
@@ -241,7 +242,7 @@ static void process_bus_sleep(uint8_t rhport)
   const unsigned inten = KHCI->INTEN;
 
   KHCI->INTEN    = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
-  //KHCI->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK;
+  KHCI->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK;
   KHCI->USBCTRL |= USB_USBCTRL_SUSP_MASK;
 
   dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
@@ -252,8 +253,8 @@ static void process_bus_resume(uint8_t rhport)
   // Enable suspend & disable resume interrupt
   const unsigned inten = KHCI->INTEN;
 
-  KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
-  //KHCI->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK;
+  KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; // will also clear USB_USBTRC0_USB_RESUME_INT_MASK
+  KHCI->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK;
   KHCI->INTEN    = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
 
   dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
@@ -275,8 +276,7 @@ void dcd_init(uint8_t rhport)
   KHCI->BDTPAGE2 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
   KHCI->BDTPAGE3 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
 
-  KHCI->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK |
-    USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
+  KHCI->INTEN = USB_INTEN_USBRSTEN_MASK;
 
   dcd_connect(rhport);
   NVIC_ClearPendingIRQ(USB0_IRQn);
@@ -297,7 +297,7 @@ void dcd_int_disable(uint8_t rhport)
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
   _dcd.addr = dev_addr & 0x7F; 
- /* Response with status first before changing device address */
+  /* Response with status first before changing device address */
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
 
@@ -518,18 +518,26 @@ void dcd_int_handler(uint8_t rhport)
   }
 
   if (is & USB_ISTAT_SLEEP_MASK) {
-    TU_LOG_LOCATION();
-    TU_LOG2_HEX(is);
+    // TU_LOG2("Suspend: "); TU_LOG2_HEX(is);
+
+    // Note Host usually has extra delay after bus reset (without SOF), which could falsely 
+    // detected as Sleep event. Though usbd has debouncing logic so we are good
     KHCI->ISTAT = USB_ISTAT_SLEEP_MASK;
     process_bus_sleep(rhport);
   }
 
+#if 0 // ISTAT_RESUME never trigger, probably for host mode ?
   if (is & USB_ISTAT_RESUME_MASK) {
-    TU_LOG_LOCATION();
-    TU_LOG2_HEX(is);
+    // TU_LOG2("ISTAT Resume: "); TU_LOG2_HEX(is);
     KHCI->ISTAT = USB_ISTAT_RESUME_MASK;
     process_bus_resume(rhport);
   }
+#endif
+
+  if (KHCI->USBTRC0 & USB_USBTRC0_USB_RESUME_INT_MASK) {
+     // TU_LOG2("USBTRC0 Resume: "); TU_LOG2_HEX(is); TU_LOG2_HEX(KHCI->USBTRC0);
+    process_bus_resume(rhport);
+  }
 
   if (is & USB_ISTAT_SOFTOK_MASK) {
     KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK;

From b363afc091b1cccafd7ebaf6365a6f655037d986 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Sep 2021 00:46:29 +0700
Subject: [PATCH 0479/2085] minor clean up

---
 src/portable/nxp/khci/dcd_khci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 3bb40aeb2..ff1997440 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -192,7 +192,7 @@ static void process_tokdne(uint8_t rhport)
   dcd_event_xfer_complete(rhport,
                           tu_edpt_addr(epnum, dir),
                           length - remaining, XFER_RESULT_SUCCESS, true);
-  if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) {
+  if (0 == epnum && 0 == length) {
     /* After completion a ZLP of control transfer,
      * it prepares for the next steup transfer. */
     if (_dcd.addr) {

From 6d8677a78ab4973ff498ec2fe8ea40a1cde230a1 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 17 Sep 2021 11:41:58 +0200
Subject: [PATCH 0480/2085] dcd_da146xx: Add VBUS handling

DA146xx are Bluetooth devices that may be battery
powered and when not connected to USB host there
is no need for USB peripheral to be running.

This change allows to enable USB peripheral when
VBUS is present otherwise USB is down reducing
power consumption.

tud_vsub_changed() function must be called
whenever VBUS change was detected.
For bus-powered devices this function should be called
at startup since VBUS must be present while device
is working.
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 65 +++++++++++++++++------
 1 file changed, 50 insertions(+), 15 deletions(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 7b0d8f86c..112cdb502 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -217,6 +217,7 @@ typedef struct {
 static struct
 {
   bool vbus_present;
+  bool init_called;
   bool in_reset;
   xfer_ctl_t xfer_status[EP_MAX][2];
   // Endpoints that use DMA, one for each direction
@@ -224,6 +225,7 @@ static struct
 } _dcd =
 {
   .vbus_present = false,
+  .init_called = false,
   .xfer_status =
   {
     { { .regs = EP_REGS(USB_EPC0_REG) }, { .regs = EP_REGS(USB_EPC0_REG) } },
@@ -735,19 +737,13 @@ static void handle_ep0_nak(void)
  *------------------------------------------------------------------*/
 void dcd_init(uint8_t rhport)
 {
-  USB->USB_MCTRL_REG = USB_USB_MCTRL_REG_USBEN_Msk;
-  USB->USB_NFSR_REG = 0;
-  USB->USB_FAR_REG = 0x80;
-  USB->USB_NFSR_REG = NFSR_NODE_RESET;
-  USB->USB_TXMSK_REG = 0;
-  USB->USB_RXMSK_REG = 0;
+  (void) rhport;
 
-  USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk |
-                       USB_USB_MAMSK_REG_USB_M_ALT_Msk |
-                       USB_USB_MAMSK_REG_USB_M_WARN_Msk;
-  USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk;
-
-  dcd_connect(rhport);
+  _dcd.init_called = true;
+  if (_dcd.vbus_present)
+  {
+    dcd_connect(rhport);
+  }
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -783,10 +779,25 @@ void dcd_connect(uint8_t rhport)
 {
   (void)rhport;
 
-  REG_SET_BIT(USB_MCTRL_REG, USB_NAT);
+  if (GET_BIT(USB->USB_MCTRL_REG, USB_USB_MCTRL_REG_USB_NAT) == 0)
+  {
+    USB->USB_MCTRL_REG = USB_USB_MCTRL_REG_USBEN_Msk;
+    USB->USB_NFSR_REG = 0;
+    USB->USB_FAR_REG = 0x80;
+    USB->USB_NFSR_REG = NFSR_NODE_RESET;
+    USB->USB_TXMSK_REG = 0;
+    USB->USB_RXMSK_REG = 0;
 
-  // Select chosen DMA to be triggered by USB.
-  DMA->DMA_REQ_MUX_REG = (DMA->DMA_REQ_MUX_REG & ~DA146XX_DMA_USB_MUX_MASK) | DA146XX_DMA_USB_MUX;
+    USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk |
+                         USB_USB_MAMSK_REG_USB_M_ALT_Msk |
+                         USB_USB_MAMSK_REG_USB_M_WARN_Msk;
+    USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk;
+
+    REG_SET_BIT(USB_MCTRL_REG, USB_NAT);
+
+    // Select chosen DMA to be triggered by USB.
+    DMA->DMA_REQ_MUX_REG = (DMA->DMA_REQ_MUX_REG & ~DA146XX_DMA_USB_MUX_MASK) | DA146XX_DMA_USB_MUX;
+  }
 }
 
 void dcd_disconnect(uint8_t rhport)
@@ -796,6 +807,30 @@ void dcd_disconnect(uint8_t rhport)
   REG_CLR_BIT(USB_MCTRL_REG, USB_NAT);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
+{
+  return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0;
+}
+
+void tusb_vbus_changed(bool present)
+{
+  if (present && !_dcd.vbus_present)
+  {
+    _dcd.vbus_present = true;
+    // If power event happened before USB started, delay dcd_connect
+    // until dcd_init is called.
+    if (_dcd.init_called)
+    {
+      dcd_connect(0);
+    }
+  }
+  else if (!present && _dcd.vbus_present)
+  {
+    _dcd.vbus_present = false;
+    USB->USB_MCTRL_REG = 0;
+    dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, is_in_isr());
+  }
+}
 
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port

From a71ac71d7f9fda4f72b02148a194987821864fa4 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 17 Sep 2021 11:48:38 +0200
Subject: [PATCH 0481/2085] da1469x_dk_xxx: Add VBUS handling

Two BSPs with DA146xx MCUs are now adopted to
VBUS handling changed introduced to dcd_da146xx driver.

da14695_dk_usb as bus-powered devices informs driver that
VBUS is present at startup.

da1469x-dk-pro has VBUS change interrupt handler that
informs driver about VBUS changes.
---
 hw/bsp/da14695_dk_usb/da14695_dk_usb.c |  9 ++++++++-
 hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c | 26 +++++++++++++++++++++++++-
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
index e7c7ae364..bdb30e0e5 100644
--- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
@@ -53,6 +53,9 @@ void UnhandledIRQ(void)
   while(1);
 }
 
+// DA146xx driver function that must be called whenever VBUS changes.
+extern void tusb_vbus_changed(bool present);
+
 void board_init(void)
 {
   // LED
@@ -70,7 +73,10 @@ void board_init(void)
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-  NVIC_SetPriority(USB_IRQn, 2);
+#if TUSB_OPT_DEVICE_ENABLED
+  // This board is USB powered there is no need to monitor
+  // VBUS line.  Notify driver that VBUS is present.
+  tusb_vbus_changed(true);
 
   /* Setup USB IRQ */
   NVIC_SetPriority(USB_IRQn, 2);
@@ -81,6 +87,7 @@ void board_init(void)
 
   mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
   mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
+#endif
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
index 85fa17152..2b6931e4e 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
+++ b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
@@ -36,6 +36,21 @@ void USB_IRQHandler(void)
   tud_int_handler(0);
 }
 
+#if TUSB_OPT_DEVICE_ENABLED
+// DA146xx driver function that must be called whenever VBUS changes
+extern void tusb_vbus_changed(bool present);
+
+// VBUS change interrupt handler
+void VBUS_IRQHandler(void)
+{
+  bool present = (CRG_TOP->ANA_STATUS_REG & CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk) != 0;
+  // Clear VBUS interrupt
+  CRG_TOP->VBUS_IRQ_CLEAR_REG = 1;
+
+  tusb_vbus_changed(present);
+}
+#endif
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -70,7 +85,15 @@ void board_init(void)
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-  NVIC_SetPriority(USB_IRQn, 2);
+#if TUSB_OPT_DEVICE_ENABLED
+  // Setup interrupt for both connect and disconnect
+  CRG_TOP->VBUS_IRQ_MASK_REG = CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk |
+                               CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk;
+  NVIC_SetPriority(VBUS_IRQn, 2);
+  // Trigger interrupt at the start to inform driver about VBUS state at start
+  // otherwise it could go unnoticed.
+  NVIC_SetPendingIRQ(VBUS_IRQn);
+  NVIC_EnableIRQ(VBUS_IRQn);
 
   /* Setup USB IRQ */
   NVIC_SetPriority(USB_IRQn, 2);
@@ -81,6 +104,7 @@ void board_init(void)
 
   mcu_gpio_set_pin_function(14, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
   mcu_gpio_set_pin_function(15, MCU_GPIO_MODE_INPUT, MCU_GPIO_FUNC_USB);
+#endif
 }
 
 //--------------------------------------------------------------------+

From 2499c9382d4ff0d67106f6dc6cd4a9dfbd0be20e Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Fri, 17 Sep 2021 16:51:34 -0700
Subject: [PATCH 0482/2085] rpi start. doesn't work

---
 .../boards/raspberrypi_cm4/board.h            |   38 +
 .../boards/raspberrypi_cm4/board.mk           |    0
 hw/bsp/raspberrypi4/family.c                  |  151 ++
 hw/bsp/raspberrypi4/family.mk                 |   37 +
 hw/mcu/broadcom/bcm2711/boot.s                |  170 ++
 hw/mcu/broadcom/bcm2711/interrupts.c          |   26 +
 hw/mcu/broadcom/bcm2711/interrupts.h          |    8 +
 hw/mcu/broadcom/bcm2711/io.c                  |  168 ++
 hw/mcu/broadcom/bcm2711/io.h                  |   13 +
 hw/mcu/broadcom/bcm2711/link.ld               |   20 +
 src/class/msc/msc_device.c                    |    6 +-
 src/device/dcd_attr.h                         |    4 +
 src/portable/broadcom/synopsys/dcd_synopsys.c | 1212 ++++++++++++++
 .../broadcom/synopsys/synopsys_common.h       | 1465 +++++++++++++++++
 src/tusb_option.h                             |    3 +
 15 files changed, 3318 insertions(+), 3 deletions(-)
 create mode 100644 hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h
 create mode 100644 hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk
 create mode 100644 hw/bsp/raspberrypi4/family.c
 create mode 100644 hw/bsp/raspberrypi4/family.mk
 create mode 100644 hw/mcu/broadcom/bcm2711/boot.s
 create mode 100644 hw/mcu/broadcom/bcm2711/interrupts.c
 create mode 100644 hw/mcu/broadcom/bcm2711/interrupts.h
 create mode 100644 hw/mcu/broadcom/bcm2711/io.c
 create mode 100644 hw/mcu/broadcom/bcm2711/io.h
 create mode 100644 hw/mcu/broadcom/bcm2711/link.ld
 create mode 100644 src/portable/broadcom/synopsys/dcd_synopsys.c
 create mode 100644 src/portable/broadcom/synopsys/synopsys_common.h

diff --git a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h
new file mode 100644
index 000000000..1d3565d5c
--- /dev/null
+++ b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h
@@ -0,0 +1,38 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk
new file mode 100644
index 000000000..e69de29bb
diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c
new file mode 100644
index 000000000..b2665f42d
--- /dev/null
+++ b/hw/bsp/raspberrypi4/family.c
@@ -0,0 +1,151 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+#include "board.h"
+
+#include "io.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void print(void) {
+  const char* greeting2 = "hello from cm100\r\n";
+  board_uart_write(greeting2, strlen(greeting2));
+}
+
+void board_init(void)
+{
+  gpio_initOutputPinWithPullNone(18);
+  gpio_setPinOutputBool(18, true);
+  gpio_initOutputPinWithPullNone(42);
+  // gpio_initOutputPinWithPullNone(23);
+  // gpio_initOutputPinWithPullNone(24);
+  // gpio_initOutputPinWithPullNone(25);
+  gpio_setPinOutputBool(18, false);
+  uart_init();
+  gpio_setPinOutputBool(18, true);
+  const char* greeting = "hello to gdb2\r\n";
+  gpio_setPinOutputBool(18, false);
+  for (size_t i = 0; i < 5; i++) {
+  // while (true) {
+    for (size_t j = 0; j < 1000000; j++) {
+      __asm__("nop");
+    }
+    gpio_setPinOutputBool(42, true);
+    gpio_setPinOutputBool(18, true);
+    for (size_t j = 0; j < 1000000; j++) {
+      __asm__("nop");
+    }
+    gpio_setPinOutputBool(42, false);
+    gpio_setPinOutputBool(18, false);
+  }
+  // uart_writeText("hello from io\n");
+  // gpio_setPinOutputBool(24, true);
+  board_uart_write(greeting, strlen(greeting));
+  // gpio_setPinOutputBool(24, false);
+  // gpio_setPinOutputBool(25, true);
+  print();
+  // gpio_setPinOutputBool(25, false);
+  while (true) {
+  // for (size_t i = 0; i < 5; i++) {
+    for (size_t j = 0; j < 10000000000; j++) {
+      __asm__("nop");
+    }
+    gpio_setPinOutputBool(42, true);
+    for (size_t j = 0; j < 10000000000; j++) {
+      __asm__("nop");
+    }
+    gpio_setPinOutputBool(42, false);
+  }
+  // while (1) uart_update();
+}
+
+void board_led_write(bool state)
+{
+  gpio_setPinOutputBool(42, state);
+}
+
+uint32_t board_button_read(void)
+{
+  return 0;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  for (int i = 0; i < len; i++) {
+    const char* cbuf = buf;
+    if (cbuf[i] == '\n') {
+      uart_writeByteBlockingActual('\r');
+    }
+    uart_writeByteBlockingActual(cbuf[i]);
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler (void)
+{
+  // asm("bkpt");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
new file mode 100644
index 000000000..2d5c78d22
--- /dev/null
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -0,0 +1,37 @@
+UF2_FAMILY_ID = 0x57755a57
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+MCU_DIR = hw/mcu/broadcom/bcm2711
+
+CC = clang
+
+CFLAGS += \
+	-Wall \
+	-O0 \
+	-ffreestanding \
+	-nostdlib \
+	-nostartfiles \
+	-std=c17 \
+	-mgeneral-regs-only \
+	-DCFG_TUSB_MCU=OPT_MCU_BCM2711
+
+SRC_C += \
+	src/portable/broadcom/synopsys/dcd_synopsys.c \
+	$(MCU_DIR)/io.c \
+	$(MCU_DIR)/interrupts.c
+
+CROSS_COMPILE = aarch64-none-elf-
+
+SKIP_NANOLIB = 1
+
+LD_FILE = $(MCU_DIR)/link.ld
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MCU_DIR)
+
+SRC_S += $(MCU_DIR)/boot.S
+
+$(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf
+	$(OBJCOPY) -O binary $^ $@
diff --git a/hw/mcu/broadcom/bcm2711/boot.s b/hw/mcu/broadcom/bcm2711/boot.s
new file mode 100644
index 000000000..076b3a76a
--- /dev/null
+++ b/hw/mcu/broadcom/bcm2711/boot.s
@@ -0,0 +1,170 @@
+.section ".text.boot"  // Make sure the linker puts this at the start of the kernel image
+
+.global _start  // Execution starts here
+
+_start:
+    // Check processor ID is zero (executing on main core), else hang
+    mrs     x1, mpidr_el1
+    and     x1, x1, #3
+    cbz     x1, 2f
+    // We're not on the main core, so hang in an infinite wait loop
+1:  wfe
+    b       1b
+2:  // We're on the main core!
+
+    // Set stack to start below our code
+    ldr     x1, =_start
+    mov     sp, x1
+
+    adr    x0, vectors        // load VBAR_EL1 with virtual
+    // msr    vbar_el3, x0        // vector table address
+    msr    vbar_el1, x0        // vector table address
+    // msr    vbar_el2, x0        // vector table address
+    isb
+
+    // Clean the BSS section
+    ldr     x1, =__bss_start     // Start address
+    ldr     w2, =__bss_size      // Size of the section
+3:  cbz     w2, 4f               // Quit loop if zero
+    str     xzr, [x1], #8
+    sub     w2, w2, #1
+    cbnz    w2, 3b               // Loop if non-zero
+
+    // Jump to our main() routine in C (make sure it doesn't return)
+4:  bl      main
+    // In case it does return, halt the master core too
+    b       1b
+
+.macro  ventry  label
+.align  7
+b   \label
+.endm
+
+.macro handle_invalid_entry type
+irq_entry
+mov x0, #\type
+mrs x1, esr_el1
+mrs x2, elr_el1
+b   err_hang
+.endm
+
+.macro  irq_entry
+sub sp, sp, #272
+stp x0, x1, [sp, #16 * 0]
+stp x2, x3, [sp, #16 * 1]
+stp x4, x5, [sp, #16 * 2]
+stp x6, x7, [sp, #16 * 3]
+stp x8, x9, [sp, #16 * 4]
+stp x10, x11, [sp, #16 * 5]
+stp x12, x13, [sp, #16 * 6]
+stp x14, x15, [sp, #16 * 7]
+stp x16, x17, [sp, #16 * 8]
+stp x18, x19, [sp, #16 * 9]
+stp x20, x21, [sp, #16 * 10]
+stp x22, x23, [sp, #16 * 11]
+stp x24, x25, [sp, #16 * 12]
+stp x26, x27, [sp, #16 * 13]
+stp x28, x29, [sp, #16 * 14]
+str x30, [sp, #16 * 15] 
+.endm
+
+.macro  irq_exit
+ldp x0, x1, [sp, #16 * 0]
+ldp x2, x3, [sp, #16 * 1]
+ldp x4, x5, [sp, #16 * 2]
+ldp x6, x7, [sp, #16 * 3]
+ldp x8, x9, [sp, #16 * 4]
+ldp x10, x11, [sp, #16 * 5]
+ldp x12, x13, [sp, #16 * 6]
+ldp x14, x15, [sp, #16 * 7]
+ldp x16, x17, [sp, #16 * 8]
+ldp x18, x19, [sp, #16 * 9]
+ldp x20, x21, [sp, #16 * 10]
+ldp x22, x23, [sp, #16 * 11]
+ldp x24, x25, [sp, #16 * 12]
+ldp x26, x27, [sp, #16 * 13]
+ldp x28, x29, [sp, #16 * 14]
+ldr x30, [sp, #16 * 15] 
+add sp, sp, #272       
+eret
+.endm
+
+
+/*
+ * Exception vectors.
+ */
+.align  11
+.globl vectors 
+vectors:
+    ventry  sync_invalid_el1t           // Synchronous EL1t
+    ventry  irq_invalid_el1t            // IRQ EL1t
+    ventry  fiq_invalid_el1t            // FIQ EL1t
+    ventry  error_invalid_el1t          // Error EL1t
+
+    ventry  sync_invalid_el1h           // Synchronous EL1h
+    ventry  el1_irq                 // IRQ EL1h
+    ventry  fiq_invalid_el1h            // FIQ EL1h
+    ventry  error_invalid_el1h          // Error EL1h
+
+    ventry  sync_invalid_el0_64         // Synchronous 64-bit EL0
+    ventry  irq_invalid_el0_64          // IRQ 64-bit EL0
+    ventry  fiq_invalid_el0_64          // FIQ 64-bit EL0
+    ventry  error_invalid_el0_64            // Error 64-bit EL0
+
+    ventry  sync_invalid_el0_32         // Synchronous 32-bit EL0
+    ventry  irq_invalid_el0_32          // IRQ 32-bit EL0
+    ventry  fiq_invalid_el0_32          // FIQ 32-bit EL0
+    ventry  error_invalid_el0_32            // Error 32-bit EL0
+
+sync_invalid_el1t:
+    handle_invalid_entry  0
+
+irq_invalid_el1t:
+    handle_invalid_entry  1
+
+fiq_invalid_el1t:
+    handle_invalid_entry  2
+
+error_invalid_el1t:
+    handle_invalid_entry  3
+
+sync_invalid_el1h:
+    handle_invalid_entry  4
+
+fiq_invalid_el1h:
+    handle_invalid_entry  5
+
+error_invalid_el1h:
+    handle_invalid_entry  6
+
+sync_invalid_el0_64:
+    handle_invalid_entry  7
+
+irq_invalid_el0_64:
+    handle_invalid_entry  8
+
+fiq_invalid_el0_64:
+    handle_invalid_entry  9
+
+error_invalid_el0_64:
+    handle_invalid_entry  10
+
+sync_invalid_el0_32:
+    handle_invalid_entry  11
+
+irq_invalid_el0_32:
+    handle_invalid_entry  12
+
+fiq_invalid_el0_32:
+    handle_invalid_entry  13
+
+error_invalid_el0_32:
+    handle_invalid_entry  14
+
+el1_irq:
+    irq_entry 
+    bl  handle_irq
+    irq_exit 
+
+.globl err_hang
+err_hang: b err_hang
diff --git a/hw/mcu/broadcom/bcm2711/interrupts.c b/hw/mcu/broadcom/bcm2711/interrupts.c
new file mode 100644
index 000000000..cb5607526
--- /dev/null
+++ b/hw/mcu/broadcom/bcm2711/interrupts.c
@@ -0,0 +1,26 @@
+#include <stdbool.h>
+#include <stdint.h>
+
+void disable_async_interrupts(void) {
+    
+}
+
+void enable_async_interrupts(void) {
+    
+}
+
+void Default_Handler(void) {
+    while (true) {}
+}
+
+__attribute__((weak)) void handle_irq(void) {
+    unsigned int irq = *((volatile uint32_t*) 0x3F00B204);
+    switch (irq) {
+        // case (SYSTEM_TIMER_IRQ_1):
+        //     handle_timer_irq();
+        //     break;
+        default:
+            // printf("Unknown pending irq: %x\r\n", irq);
+            Default_Handler();
+    }
+}
\ No newline at end of file
diff --git a/hw/mcu/broadcom/bcm2711/interrupts.h b/hw/mcu/broadcom/bcm2711/interrupts.h
new file mode 100644
index 000000000..5f36d6daa
--- /dev/null
+++ b/hw/mcu/broadcom/bcm2711/interrupts.h
@@ -0,0 +1,8 @@
+#pragma once
+
+void disable_async_interrupts(void);
+void enable_async_interrupts(void);
+
+#define GIC_BASE 0x4c0040000
+#define NUM_CPUS 4
+#define NUM_SPIS 192
diff --git a/hw/mcu/broadcom/bcm2711/io.c b/hw/mcu/broadcom/bcm2711/io.c
new file mode 100644
index 000000000..213d6f2fb
--- /dev/null
+++ b/hw/mcu/broadcom/bcm2711/io.c
@@ -0,0 +1,168 @@
+// From: https://github.com/isometimes/rpi4-osdev/blob/master/part4-miniuart/io.c
+// CC-0 License
+
+// GPIO
+
+enum {
+    PERIPHERAL_BASE = 0xFE000000,
+    GPFSEL0         = PERIPHERAL_BASE + 0x200000,
+    GPSET0          = PERIPHERAL_BASE + 0x20001C,
+    GPCLR0          = PERIPHERAL_BASE + 0x200028,
+    GPPUPPDN0       = PERIPHERAL_BASE + 0x2000E4
+};
+
+enum {
+    GPIO_MAX_PIN       = 53,
+    GPIO_FUNCTION_OUT  = 1,
+    GPIO_FUNCTION_ALT5 = 2,
+    GPIO_FUNCTION_ALT3 = 7
+};
+
+enum {
+    Pull_None = 0,
+    Pull_Down = 1, // Are down and up the right way around?
+    Pull_Up = 2
+};
+
+void mmio_write(long reg, unsigned int val) { *(volatile unsigned int *)reg = val; }
+unsigned int mmio_read(long reg) { return *(volatile unsigned int *)reg; }
+
+unsigned int gpio_call(unsigned int pin_number, unsigned int value, unsigned int base, unsigned int field_size, unsigned int field_max) {
+    unsigned int field_mask = (1 << field_size) - 1;
+  
+    if (pin_number > field_max) return 0;
+    if (value > field_mask) return 0; 
+
+    unsigned int num_fields = 32 / field_size;
+    unsigned int reg = base + ((pin_number / num_fields) * 4);
+    unsigned int shift = (pin_number % num_fields) * field_size;
+
+    unsigned int curval = mmio_read(reg);
+    curval &= ~(field_mask << shift);
+    curval |= value << shift;
+    mmio_write(reg, curval);
+
+    return 1;
+}
+
+unsigned int gpio_set     (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPSET0, 1, GPIO_MAX_PIN); }
+unsigned int gpio_clear   (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPCLR0, 1, GPIO_MAX_PIN); }
+unsigned int gpio_pull    (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPPUPPDN0, 2, GPIO_MAX_PIN); }
+unsigned int gpio_function(unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPFSEL0, 3, GPIO_MAX_PIN); }
+
+void gpio_useAsAlt3(unsigned int pin_number) {
+    gpio_pull(pin_number, Pull_None);
+    gpio_function(pin_number, GPIO_FUNCTION_ALT3);
+}
+
+void gpio_useAsAlt5(unsigned int pin_number) {
+    gpio_pull(pin_number, Pull_None);
+    gpio_function(pin_number, GPIO_FUNCTION_ALT5);
+}
+
+void gpio_initOutputPinWithPullNone(unsigned int pin_number) {
+    gpio_pull(pin_number, Pull_None);
+    gpio_function(pin_number, GPIO_FUNCTION_OUT);
+}
+
+void gpio_setPinOutputBool(unsigned int pin_number, unsigned int onOrOff) {
+    if (onOrOff) {
+        gpio_set(pin_number, 1);
+    } else {
+        gpio_clear(pin_number, 1);
+    }
+}
+
+// UART
+
+enum {
+    AUX_BASE        = PERIPHERAL_BASE + 0x215000,
+    AUX_IRQ         = AUX_BASE,
+    AUX_ENABLES     = AUX_BASE + 4,
+    AUX_MU_IO_REG   = AUX_BASE + 64,
+    AUX_MU_IER_REG  = AUX_BASE + 68,
+    AUX_MU_IIR_REG  = AUX_BASE + 72,
+    AUX_MU_LCR_REG  = AUX_BASE + 76,
+    AUX_MU_MCR_REG  = AUX_BASE + 80,
+    AUX_MU_LSR_REG  = AUX_BASE + 84,
+    AUX_MU_MSR_REG  = AUX_BASE + 88,
+    AUX_MU_SCRATCH  = AUX_BASE + 92,
+    AUX_MU_CNTL_REG = AUX_BASE + 96,
+    AUX_MU_STAT_REG = AUX_BASE + 100,
+    AUX_MU_BAUD_REG = AUX_BASE + 104,
+    AUX_UART_CLOCK  = 500000000,
+    UART_MAX_QUEUE  = 16 * 1024
+};
+
+#define AUX_MU_BAUD(baud) ((AUX_UART_CLOCK/(baud*8))-1)
+
+unsigned char uart_output_queue[UART_MAX_QUEUE];
+unsigned int uart_output_queue_write = 0;
+unsigned int uart_output_queue_read = 0;
+
+void uart_init(void) {
+    mmio_write(AUX_ENABLES, 1); //enable UART1
+    mmio_write(AUX_MU_IER_REG, 0);
+    mmio_write(AUX_MU_CNTL_REG, 0);
+    mmio_write(AUX_MU_LCR_REG, 3); //8 bits
+    mmio_write(AUX_MU_MCR_REG, 0);
+    mmio_write(AUX_MU_IER_REG, 0);
+    mmio_write(AUX_MU_IIR_REG, 0xC6); //disable interrupts
+    mmio_write(AUX_MU_BAUD_REG, AUX_MU_BAUD(115200));
+    gpio_useAsAlt5(14);
+    gpio_useAsAlt5(15);
+    mmio_write(AUX_MU_CNTL_REG, 3); //enable RX/TX
+}
+
+unsigned int uart_isOutputQueueEmpty(void) {
+    return uart_output_queue_read == uart_output_queue_write;
+}
+
+unsigned int uart_isReadByteReady(void)  { return mmio_read(AUX_MU_LSR_REG) & 0x01; }
+unsigned int uart_isWriteByteReady(void) { return mmio_read(AUX_MU_LSR_REG) & 0x20; }
+
+unsigned char uart_readByte(void) {
+    while (!uart_isReadByteReady());
+    return (unsigned char)mmio_read(AUX_MU_IO_REG);
+}
+
+void uart_writeByteBlockingActual(unsigned char ch) {
+    while (!uart_isWriteByteReady()); 
+    mmio_write(AUX_MU_IO_REG, (unsigned int)ch);
+}
+
+void uart_loadOutputFifo(void) {
+    while (!uart_isOutputQueueEmpty() && uart_isWriteByteReady()) {
+        uart_writeByteBlockingActual(uart_output_queue[uart_output_queue_read]);
+        uart_output_queue_read = (uart_output_queue_read + 1) & (UART_MAX_QUEUE - 1); // Don't overrun
+    }
+}
+
+void uart_writeByteBlocking(unsigned char ch) {
+    unsigned int next = (uart_output_queue_write + 1) & (UART_MAX_QUEUE - 1); // Don't overrun
+
+    while (next == uart_output_queue_read) uart_loadOutputFifo();
+
+    uart_output_queue[uart_output_queue_write] = ch;
+    uart_output_queue_write = next;
+}
+
+void uart_writeText(const char *buffer) {
+    while (*buffer) {
+       if (*buffer == '\n') uart_writeByteBlocking('\r');
+       uart_writeByteBlocking(*buffer++);
+    }
+}
+
+void uart_drainOutputQueue(void) {
+    while (!uart_isOutputQueueEmpty()) uart_loadOutputFifo();
+}
+
+void uart_update(void) {
+    uart_loadOutputFifo();
+
+    if (uart_isReadByteReady()) {
+       unsigned char ch = uart_readByte();
+       if (ch == '\r') uart_writeText("\n"); else uart_writeByteBlocking(ch);
+    }
+}
diff --git a/hw/mcu/broadcom/bcm2711/io.h b/hw/mcu/broadcom/bcm2711/io.h
new file mode 100644
index 000000000..9f70ce504
--- /dev/null
+++ b/hw/mcu/broadcom/bcm2711/io.h
@@ -0,0 +1,13 @@
+// From: https://github.com/isometimes/rpi4-osdev/blob/master/part4-miniuart/io.h
+// CC-0 License
+
+void uart_init(void);
+void uart_writeText(const char *buffer);
+void uart_loadOutputFifo(void);
+unsigned char uart_readByte(void);
+unsigned int uart_isReadByteReady(void);
+void uart_writeByteBlocking(unsigned char ch);
+void uart_update(void);
+void gpio_setPinOutputBool(unsigned int pin_number, unsigned int onOrOff);
+void uart_writeByteBlockingActual(unsigned char ch);
+void gpio_initOutputPinWithPullNone(unsigned int pin_number);
diff --git a/hw/mcu/broadcom/bcm2711/link.ld b/hw/mcu/broadcom/bcm2711/link.ld
new file mode 100644
index 000000000..0d5ebe2ab
--- /dev/null
+++ b/hw/mcu/broadcom/bcm2711/link.ld
@@ -0,0 +1,20 @@
+SECTIONS
+{
+    . = 0x80000;     /* Kernel load address for AArch64 */
+    .text : { KEEP(*(.text.boot)) *(.text .text.* .gnu.linkonce.t*) }
+    .rodata : { *(.rodata .rodata.* .gnu.linkonce.r*) }
+    PROVIDE(_data = .);
+    .data : { *(.data .data.* .gnu.linkonce.d*) }
+    .bss (NOLOAD) : {
+        . = ALIGN(16);
+        __bss_start = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        __bss_end = .;
+    }
+    _end = .;
+    end = .;
+
+   /DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) }
+}
+__bss_size = (__bss_end - __bss_start)>>3;
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 0fd592129..5eb28e694 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -476,7 +476,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
             if (p_cbw->total_bytes)
             {
               // 6.7 The 13 Cases: case 4 (Hi > Dn)
-              TU_LOG(MSC_DEBUG, "  SCSI case 4 (Hi > Dn): %lu\r\n", p_cbw->total_bytes);
+              // TU_LOG(MSC_DEBUG, "  SCSI case 4 (Hi > Dn): %lu\r\n", p_cbw->total_bytes);
               fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
             }else
             {
@@ -489,7 +489,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
             if ( p_cbw->total_bytes == 0 )
             {
               // 6.7 The 13 Cases: case 2 (Hn < Di)
-              TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di): %lu\r\n", p_cbw->total_bytes);
+              // TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di): %lu\r\n", p_cbw->total_bytes);
               fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
             }else
             {
@@ -604,7 +604,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       if ( (p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir) )
       {
         // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status
-        TU_LOG(MSC_DEBUG, "  SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len);
+        // TU_LOG(MSC_DEBUG, "  SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len);
         usbd_edpt_stall(rhport, p_msc->ep_in);
       }else
       {
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index a35fc0ac5..9e833c7bb 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -151,6 +151,10 @@
 #elif TU_CHECK_MCU(GD32VF103)
   #define DCD_ATTR_ENDPOINT_MAX   4
 
+//------------- Broadcom -------------//
+#elif TU_CHECK_MCU(BCM2711)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
 #else
   #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define DCD_ATTR_ENDPOINT_MAX   8
diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c
new file mode 100644
index 000000000..5967565a5
--- /dev/null
+++ b/src/portable/broadcom/synopsys/dcd_synopsys.c
@@ -0,0 +1,1212 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018 Scott Shawcroft, 2019 William D. Jones for Adafruit Industries
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jan Duempelmann
+ * Copyright (c) 2020 Reinhard Panhuber
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#include "synopsys_common.h"
+
+// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
+// We disable SOF for now until needed later on
+#define USE_SOF     0
+
+#if TUSB_OPT_DEVICE_ENABLED &&                                          \
+    ( (CFG_TUSB_MCU == OPT_MCU_BCM2711 )                           \
+    )
+
+// EP_MAX       : Max number of bi-directional endpoints including EP0
+// EP_FIFO_SIZE : Size of dedicated USB SRAM
+#if CFG_TUSB_MCU == OPT_MCU_BCM2711
+// #include "bcm2711.h"
+#define EP_MAX_FS       8
+#define EP_FIFO_SIZE_FS 4096
+#define EP_MAX_HS       8
+#define EP_FIFO_SIZE_HS 4096
+#else
+#error "Unsupported MCUs"
+#endif
+
+#define EP_MAX 8
+#define EP_FIFO_SIZE 4096
+
+// Info on values here: https://github.com/torvalds/linux/blob/79160a603bdb51916226caf4a6616cc4e1c58a58/Documentation/devicetree/bindings/usb/dwc2.yaml
+
+// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm283x.dtsi
+// usb: usb@7e980000 {
+//   compatible = "brcm,bcm2835-usb";
+//   reg = <0x7e980000 0x10000>;
+//   interrupts = <1 9>;
+//   #address-cells = <1>;
+//   #size-cells = <0>;
+//   clocks = <&clk_usb>;
+//   clock-names = "otg";
+//   phys = <&usbphy>;
+//   phy-names = "usb2-phy";
+// };
+
+// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi
+// SPDX-License-Identifier: GPL-2.0
+// &usb {
+//   dr_mode = "otg";
+//   g-rx-fifo-size = <256>;
+//   g-np-tx-fifo-size = <32>;
+  
+//    * According to dwc2 the sum of all device EP
+//    * fifo sizes shouldn't exceed 3776 bytes.
+   
+//   g-tx-fifo-size = <256 256 512 512 512 768 768>;
+// };
+
+// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm2711-rpi.dtsi
+// &usb {
+//   /* Enable the FIQ support */
+//   reg = <0x7e980000 0x10000>,
+//         <0x7e00b200 0x200>;
+//   interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+//          <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+//   status = "disabled";
+// };
+
+// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm2711.dtsi
+// &usb {
+//   interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+// };
+
+// From: https://github.com/torvalds/linux/blob/1d597682d3e669ec7021aa33d088ed3d136a5149/drivers/usb/dwc2/params.c
+// static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
+// {
+//   struct dwc2_core_params *p = &hsotg->params;
+
+//   p->host_rx_fifo_size = 774;
+//   p->max_transfer_size = 65535;
+//   p->max_packet_count = 511;
+//   p->ahbcfg = 0x10;
+// }
+
+#include "device/dcd.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+#define RHPORT_REGS_BASE 0x7e980000
+
+#define GLOBAL_BASE(_port)     ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE)
+#define DEVICE_BASE(_port)     (USB_OTG_DeviceTypeDef *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE)
+#define OUT_EP_BASE(_port)     (USB_OTG_OUTEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE)
+#define IN_EP_BASE(_port)      (USB_OTG_INEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE)
+#define FIFO_BASE(_port, _x)   ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
+
+enum
+{
+  DCD_HIGH_SPEED        = 0, // Highspeed mode
+  DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY)
+  DCD_FULL_SPEED        = 3, // Full speed with internal PHY
+};
+
+static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
+
+typedef struct {
+  uint8_t * buffer;
+  tu_fifo_t * ff;
+  uint16_t total_len;
+  uint16_t max_size;
+  uint8_t interval;
+} xfer_ctl_t;
+
+typedef volatile uint32_t * usb_fifo_t;
+
+xfer_ctl_t xfer_status[EP_MAX][2];
+#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
+
+// EP0 transfers are limited to 1 packet - larger sizes has to be split
+static uint16_t ep0_pending[2];                   // Index determines direction as tusb_dir_t type
+
+// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ
+static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
+static bool _out_ep_closed;                       // Flag to check if RX FIFO size needs an update (reduce its size)
+
+// Calculate the RX FIFO size according to recommendations from reference manual
+static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
+{
+  return 15 + 2*(ep_size/4) + 2*EP_MAX;
+}
+
+static void update_grxfsiz(uint8_t rhport)
+{
+  (void) rhport;
+
+  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+
+  // Determine largest EP size for RX FIFO
+  uint16_t max_epsize = 0;
+  for (uint8_t epnum = 0; epnum < EP_MAX; epnum++)
+  {
+    max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
+  }
+
+  // Update size of RX FIFO
+  usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize);
+}
+
+// Setup the control endpoint 0.
+static void bus_reset(uint8_t rhport)
+{
+  (void) rhport;
+
+  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
+  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
+
+  tu_memclr(xfer_status, sizeof(xfer_status));
+  _out_ep_closed = false;
+
+  // clear device address
+  dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
+
+  // 1. NAK for all OUT endpoints
+  for(uint8_t n = 0; n < EP_MAX; n++) {
+    out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+  }
+
+  // 2. Un-mask interrupt bits
+  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
+  dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
+  dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
+
+  // "USB Data FIFOs" section in reference manual
+  // Peripheral FIFO architecture
+  //
+  // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
+  // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
+  // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
+  // configuration done below.
+  //
+  // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
+  // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
+  // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
+  // opened when the host sends an additional command: setInterface. At this point in time
+  // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
+  // an additional memory
+  //
+  // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+  // | IN FIFO 0   |
+  // --------------- (320 or 1024) - 16
+  // | IN FIFO 1   |
+  // --------------- (320 or 1024) - 16 - x
+  // |   . . . .   |
+  // --------------- (320 or 1024) - 16 - x - y - ... - z
+  // | IN FIFO MAX |
+  // ---------------
+  // |    FREE     |
+  // --------------- GRXFSIZ
+  // | OUT FIFO    |
+  // | ( Shared )  |
+  // --------------- 0
+  //
+  // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
+  // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
+  //
+  // - All EP OUT shared a unique OUT FIFO which uses
+  //   - 13 for setup packets + control words (up to 3 setup packets).
+  //   - 1 for global NAK (not required/used here).
+  //   - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is  "2 x (Largest-EPsize/4) + 1"
+  //   - 2 for each used OUT endpoint
+  //
+  //   Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
+  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x EP_MAX = 47  + 2 x EP_MAX
+  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX
+  //
+  //   NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
+  //   of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
+  //
+  //   For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
+  //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
+  //   overwrite this.
+
+  #if TUD_OPT_HIGH_SPEED
+  usb_otg->GRXFSIZ = calc_rx_ff_size(512);
+  #else
+  usb_otg->GRXFSIZ = calc_rx_ff_size(64);
+  #endif
+
+  _allocated_fifo_words_tx = 16;
+
+  // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
+  usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+
+  // Fixed control EP0 size to 64 bytes
+  in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
+  xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
+
+  out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
+
+  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
+}
+
+// Set turn-around timeout according to link speed
+extern uint32_t SystemCoreClock;
+static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed)
+{
+  usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+
+  if ( speed == TUSB_SPEED_HIGH )
+  {
+    // Use fixed 0x09 for Highspeed
+    usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos);
+  }
+  else
+  {
+    // Turnaround timeout depends on the MCU clock
+    uint32_t turnaround;
+
+    if ( SystemCoreClock >= 32000000U )
+      turnaround = 0x6U;
+    else if ( SystemCoreClock >= 27500000U )
+      turnaround = 0x7U;
+    else if ( SystemCoreClock >= 24000000U )
+      turnaround = 0x8U;
+    else if ( SystemCoreClock >= 21800000U )
+      turnaround = 0x9U;
+    else if ( SystemCoreClock >= 20000000U )
+      turnaround = 0xAU;
+    else if ( SystemCoreClock >= 18500000U )
+      turnaround = 0xBU;
+    else if ( SystemCoreClock >= 17200000U )
+      turnaround = 0xCU;
+    else if ( SystemCoreClock >= 16000000U )
+      turnaround = 0xDU;
+    else if ( SystemCoreClock >= 15000000U )
+      turnaround = 0xEU;
+    else
+      turnaround = 0xFU;
+
+    // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
+    usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos);
+  }
+}
+
+static tusb_speed_t get_speed(uint8_t rhport)
+{
+  (void) rhport;
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
+  return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
+}
+
+static void set_speed(uint8_t rhport, tusb_speed_t speed)
+{
+  uint32_t bitvalue;
+
+  if ( rhport == 1 )
+  {
+    bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
+  }
+  else
+  {
+    bitvalue = DCD_FULL_SPEED;
+  }
+
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+
+  // Clear and set speed bits
+  dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos);
+  dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos);
+}
+
+#if defined(USB_HS_PHYC)
+static bool USB_HS_PHYCInit(void)
+{
+  USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
+
+  // Enable LDO
+  usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
+
+  // Wait until LDO ready
+  while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
+
+  uint32_t phyc_pll = 0;
+
+  // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
+  switch ( HSE_VALUE )
+  {
+    case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
+    case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
+    case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
+    case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
+    case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
+    case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
+    default:
+      TU_ASSERT(0);
+  }
+  usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
+
+  // Control the tuning interface of the High Speed PHY
+  // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
+  usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
+
+  // Enable PLL internal PHY
+  usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
+
+  // Original ST code has 2 ms delay for PLL stabilization.
+  // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
+
+  return true;
+}
+#endif
+
+static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
+{
+  (void) rhport;
+
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
+  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
+
+  // EP0 is limited to one packet each xfer
+  // We use multiple transaction of xfer->max_size length to get a whole transfer done
+  if(epnum == 0) {
+    xfer_ctl_t * const xfer = XFER_CTL_BASE(epnum, dir);
+    total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
+    ep0_pending[dir] -= total_bytes;
+  }
+
+  // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
+  if(dir == TUSB_DIR_IN) {
+    // A full IN transfer (multiple packets, possibly) triggers XFRC.
+    in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) |
+        ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk);
+
+    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK;
+    // For ISO endpoint set correct odd/even bit for next frame.
+    if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
+    {
+      // Take odd/even bit from frame counter.
+      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
+      in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk);
+    }
+    // Enable fifo empty interrupt only if there are something to put in the fifo.
+    if(total_bytes != 0) {
+      dev->DIEPEMPMSK |= (1 << epnum);
+    }
+  } else {
+    // A full OUT transfer (multiple packets, possibly) triggers XFRC.
+    out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ);
+    out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) |
+        ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk);
+
+    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
+    if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
+    {
+      // Take odd/even bit from frame counter.
+      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
+      out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk);
+    }
+  }
+}
+
+/*------------------------------------------------------------------*/
+/* Controller API
+ *------------------------------------------------------------------*/
+void dcd_init (uint8_t rhport)
+{
+  // Programming model begins in the last section of the chapter on the USB
+  // peripheral in each Reference Manual.
+
+  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+
+  // No HNP/SRP (no OTG support), program timeout later.
+  if ( rhport == 1 )
+  {
+    // On selected MCUs HS port1 can be used with external PHY via ULPI interface
+#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
+    // deactivate internal PHY
+    usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
+
+    // Init The UTMI Interface
+    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+
+    // Select default internal VBUS Indicator and Drive for ULPI
+    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+#else
+    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+#endif
+
+#if defined(USB_HS_PHYC)
+    // Highspeed with embedded UTMI PHYC
+
+    // Select UTMI Interface
+    usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
+    usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
+
+    // Enables control of a High Speed USB PHY
+    USB_HS_PHYCInit();
+#endif
+  } else
+  {
+    // Enable internal PHY
+    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+  }
+
+  // Reset core after selecting PHY
+  // Wait AHB IDLE, reset then wait until it is cleared
+  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
+  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
+
+  // Restart PHY clock
+  *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
+
+  // Clear all interrupts
+  usb_otg->GINTSTS |= usb_otg->GINTSTS;
+
+  // Required as part of core initialization.
+  // TODO: How should mode mismatch be handled? It will cause
+  // the core to stop working/require reset.
+  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM;
+
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+
+  // If USB host misbehaves during status portion of control xfer
+  // (non zero-length packet), send STALL back and discard.
+  dev->DCFG |=  USB_OTG_DCFG_NZLSOHSK;
+
+  #if TUD_OPT_HIGH_SPEED
+  set_speed(rhport, TUSB_SPEED_HIGH);
+  #else
+  set_speed(rhport, TUSB_SPEED_FULL);
+  #endif
+
+  // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
+  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+
+  usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST   | USB_OTG_GINTMSK_ENUMDNEM |
+      USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM     |
+      USB_OTG_GINTMSK_RXFLVLM  | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0);
+
+  // Enable global interrupt
+  usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+
+  dcd_connect(rhport);
+}
+
+void dcd_int_enable (uint8_t rhport)
+{
+  (void) rhport;
+  // NVIC_EnableIRQ(RHPORT_IRQn);
+}
+
+void dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  // NVIC_DisableIRQ(RHPORT_IRQn);
+}
+
+void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
+{
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos);
+
+  // Response with status after changing device address
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+
+static void remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+  uint32_t count = SystemCoreClock / 1000;
+  while ( count-- )
+  {
+    // __NOP();
+  }
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+
+  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+
+  // set remote wakeup
+  dev->DCTL |= USB_OTG_DCTL_RWUSIG;
+
+  // enable SOF to detect bus resume
+  usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
+  usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+
+  // Per specs: remote wakeup signal bit must be clear within 1-15ms
+  remote_wakeup_delay();
+
+  dev->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  dev->DCTL &= ~USB_OTG_DCTL_SDIS;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  (void) rhport;
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  dev->DCTL |= USB_OTG_DCTL_SDIS;
+}
+
+
+/*------------------------------------------------------------------*/
+/* DCD Endpoint port
+ *------------------------------------------------------------------*/
+
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
+{
+  (void) rhport;
+
+  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
+  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
+
+  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
+  uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
+
+  TU_ASSERT(epnum < EP_MAX);
+
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->max_size = desc_edpt->wMaxPacketSize.size;
+  xfer->interval = desc_edpt->bInterval;
+
+  uint16_t const fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // Round up to next full word
+
+  if(dir == TUSB_DIR_OUT)
+  {
+    // Calculate required size of RX FIFO
+    uint16_t const sz = calc_rx_ff_size(4*fifo_size);
+
+    // If size_rx needs to be extended check if possible and if so enlarge it
+    if (usb_otg->GRXFSIZ < sz)
+    {
+      TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
+
+      // Enlarge RX FIFO
+      usb_otg->GRXFSIZ = sz;
+    }
+
+    out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos)        |
+        (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos)   |
+        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
+        (desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos);
+
+    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
+  }
+  else
+  {
+    // "USB Data FIFOs" section in reference manual
+    // Peripheral FIFO architecture
+    //
+    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+    // | IN FIFO 0   |
+    // --------------- (320 or 1024) - 16
+    // | IN FIFO 1   |
+    // --------------- (320 or 1024) - 16 - x
+    // |   . . . .   |
+    // --------------- (320 or 1024) - 16 - x - y - ... - z
+    // | IN FIFO MAX |
+    // ---------------
+    // |    FREE     |
+    // --------------- GRXFSIZ
+    // | OUT FIFO    |
+    // | ( Shared )  |
+    // --------------- 0
+    //
+    // In FIFO is allocated by following rules:
+    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
+
+    // Check if free space is available
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4);
+
+    _allocated_fifo_words_tx += fifo_size;
+
+    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
+
+    // DIEPTXF starts at FIFO #1.
+    // Both TXFD and TXSA are in unit of 32-bit words.
+    usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+
+    in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
+        (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
+        (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
+        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
+        (desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos);
+
+    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
+  }
+
+  return true;
+}
+
+// Close all non-control endpoints, cancel all pending transfers if any.
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+
+//  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
+  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
+
+  // Disable non-control interrupt
+  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
+
+  for(uint8_t n = 1; n < EP_MAX; n++)
+  {
+    // disable OUT endpoint
+    out_ep[n].DOEPCTL = 0;
+    xfer_status[n][TUSB_DIR_OUT].max_size = 0;
+
+    // disable IN endpoint
+    in_ep[n].DIEPCTL = 0;
+    xfer_status[n][TUSB_DIR_IN].max_size = 0;
+  }
+
+  // reset allocated fifo IN
+  _allocated_fifo_words_tx = 16;
+}
+
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->buffer      = buffer;
+  xfer->ff          = NULL;
+  xfer->total_len   = total_bytes;
+
+  // EP0 can only handle one packet
+  if(epnum == 0) {
+    ep0_pending[dir] = total_bytes;
+    // Schedule the first transaction for EP0 transfer
+    edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
+    return true;
+  }
+
+  uint16_t num_packets = (total_bytes / xfer->max_size);
+  uint16_t const short_packet_size = total_bytes % xfer->max_size;
+
+  // Zero-size packet is special case.
+  if(short_packet_size > 0 || (total_bytes == 0)) {
+    num_packets++;
+  }
+
+  // Schedule packets to be sent within interrupt
+  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
+
+  return true;
+}
+
+// The number of bytes has to be given explicitly to allow more flexible control of how many
+// bytes should be written and second to keep the return value free to give back a boolean
+// success message. If total_bytes is too big, the FIFO will copy only what is available
+// into the USB buffer!
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
+  TU_ASSERT(ff->item_size == 1);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->buffer      = NULL;
+  xfer->ff          = ff;
+  xfer->total_len   = total_bytes;
+
+  uint16_t num_packets = (total_bytes / xfer->max_size);
+  uint16_t const short_packet_size = total_bytes % xfer->max_size;
+
+  // Zero-size packet is special case.
+  if(short_packet_size > 0 || (total_bytes == 0)) num_packets++;
+
+  // Schedule packets to be sent within interrupt
+  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
+
+  return true;
+}
+
+static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
+{
+  (void) rhport;
+
+  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
+  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  if(dir == TUSB_DIR_IN) {
+    // Only disable currently enabled non-control endpoint
+    if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){
+      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0);
+    } else {
+      // Stop transmitting packets and NAK IN xfers.
+      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0);
+
+      // Disable the endpoint.
+      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0);
+      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0);
+      in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD;
+    }
+
+    // Flush the FIFO, and wait until we have confirmed it cleared.
+    usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos);
+    usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
+    while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
+  } else {
+    // Only disable currently enabled non-control endpoint
+    if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){
+      out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0;
+    } else {
+      // Asserting GONAK is required to STALL an OUT endpoint.
+      // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
+      // anyway, and it can't be cleared by user code. If this while loop never
+      // finishes, we have bigger problems than just the stack.
+      dev->DCTL |= USB_OTG_DCTL_SGONAK;
+      while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
+
+      // Ditto here- disable the endpoint.
+      out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0);
+      while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0);
+      out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD;
+
+      // Allow other OUT endpoints to keep receiving.
+      dev->DCTL |= USB_OTG_DCTL_CGONAK;
+    }
+  }
+}
+
+/**
+ * Close an endpoint.
+ */
+void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
+{
+  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  dcd_edpt_disable(rhport, ep_addr, false);
+
+  // Update max_size
+  xfer_status[epnum][dir].max_size = 0;  // max_size = 0 marks a disabled EP - required for changing FIFO allocation
+
+  if (dir == TUSB_DIR_IN)
+  {
+    uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos;
+    uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos;
+    // For now only the last opened endpoint can be closed without fuss.
+    TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
+    _allocated_fifo_words_tx -= fifo_size;
+  }
+  else
+  {
+    _out_ep_closed = true;     // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
+  }
+}
+
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  dcd_edpt_disable(rhport, ep_addr, true);
+}
+
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
+  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  // Clear stall and reset data toggle
+  if(dir == TUSB_DIR_IN) {
+    in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+  } else {
+    out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+  }
+}
+
+/*------------------------------------------------------------------*/
+
+// Read a single data packet from receive FIFO
+static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
+{
+  (void) rhport;
+
+  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
+
+  // Reading full available 32 bit words from fifo
+  uint16_t full_words = len >> 2;
+  for(uint16_t i = 0; i < full_words; i++) {
+    uint32_t tmp = *rx_fifo;
+    dst[0] = tmp & 0x000000FF;
+    dst[1] = (tmp & 0x0000FF00) >> 8;
+    dst[2] = (tmp & 0x00FF0000) >> 16;
+    dst[3] = (tmp & 0xFF000000) >> 24;
+    dst += 4;
+  }
+
+  // Read the remaining 1-3 bytes from fifo
+  uint8_t bytes_rem = len & 0x03;
+  if(bytes_rem != 0) {
+    uint32_t tmp = *rx_fifo;
+    dst[0] = tmp & 0x000000FF;
+    if(bytes_rem > 1) {
+      dst[1] = (tmp & 0x0000FF00) >> 8;
+    }
+    if(bytes_rem > 2) {
+      dst[2] = (tmp & 0x00FF0000) >> 16;
+    }
+  }
+}
+
+// Write a single data packet to EPIN FIFO
+static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len)
+{
+  (void) rhport;
+
+  usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num);
+
+  // Pushing full available 32 bit words to fifo
+  uint16_t full_words = len >> 2;
+  for(uint16_t i = 0; i < full_words; i++){
+    *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0];
+    src += 4;
+  }
+
+  // Write the remaining 1-3 bytes into fifo
+  uint8_t bytes_rem = len & 0x03;
+  if(bytes_rem){
+    uint32_t tmp_word = 0;
+    tmp_word |= src[0];
+    if(bytes_rem > 1){
+      tmp_word |= src[1] << 8;
+    }
+    if(bytes_rem > 2){
+      tmp_word |= src[2] << 16;
+    }
+    *tx_fifo = tmp_word;
+  }
+}
+
+static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_ep) {
+  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
+
+  // Pop control word off FIFO
+  uint32_t ctl_word = usb_otg->GRXSTSP;
+  uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos;
+  uint8_t epnum = (ctl_word &  USB_OTG_GRXSTSP_EPNUM_Msk) >>  USB_OTG_GRXSTSP_EPNUM_Pos;
+  uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos;
+
+  switch(pktsts) {
+    case 0x01: // Global OUT NAK (Interrupt)
+      break;
+
+    case 0x02: // Out packet recvd
+    {
+      xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+
+      // Read packet off RxFIFO
+      if (xfer->ff)
+      {
+        // Ring buffer
+        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *) rx_fifo, bcnt);
+      }
+      else
+      {
+        // Linear buffer
+        read_fifo_packet(rhport, xfer->buffer, bcnt);
+
+        // Increment pointer to xfer data
+        xfer->buffer += bcnt;
+      }
+
+      // Truncate transfer length in case of short packet
+      if(bcnt < xfer->max_size) {
+        xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
+        if(epnum == 0) {
+          xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
+          ep0_pending[TUSB_DIR_OUT] = 0;
+        }
+      }
+    }
+    break;
+
+    case 0x03: // Out packet done (Interrupt)
+      break;
+
+    case 0x04: // Setup packet done (Interrupt)
+      out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
+      break;
+
+    case 0x06: // Setup packet recvd
+      // We can receive up to three setup packets in succession, but
+      // only the last one is valid.
+      _setup_packet[0] = (* rx_fifo);
+      _setup_packet[1] = (* rx_fifo);
+      break;
+
+    default: // Invalid
+      TU_BREAKPOINT();
+      break;
+  }
+}
+
+static void handle_epout_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
+  // DAINT for a given EP clears when DOEPINTx is cleared.
+  // OEPINT will be cleared when DAINT's out bits are cleared.
+  for(uint8_t n = 0; n < EP_MAX; n++) {
+    xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
+
+    if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) {
+      // SETUP packet Setup Phase done.
+      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) {
+        out_ep[n].DOEPINT =  USB_OTG_DOEPINT_STUP;
+        dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
+      }
+
+      // OUT XFER complete
+      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) {
+        out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC;
+
+        // EP0 can only handle one packet
+        if((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
+          // Schedule another packet to be received.
+          edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
+        } else {
+          dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
+        }
+      }
+    }
+  }
+}
+
+static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) {
+  // DAINT for a given EP clears when DIEPINTx is cleared.
+  // IEPINT will be cleared when DAINT's out bits are cleared.
+  for ( uint8_t n = 0; n < EP_MAX; n++ )
+  {
+    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
+
+    if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) )
+    {
+      // IN XFER complete (entire xfer).
+      if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC )
+      {
+        in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC;
+
+        // EP0 can only handle one packet
+        if((n == 0) && ep0_pending[TUSB_DIR_IN]) {
+          // Schedule another packet to be transmitted.
+          edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
+        } else {
+          dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+        }
+      }
+
+      // XFER FIFO empty
+      if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
+      {
+        // DIEPINT's TXFE bit is read-only, software cannot clear it.
+        // It will only be cleared by hardware when written bytes is more than
+        // - 64 bytes or
+        // - Half of TX FIFO size (configured by DIEPTXF)
+
+        uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos;
+
+        // Process every single packet (only whole packets can be written to fifo)
+        for(uint16_t i = 0; i < remaining_packets; i++)
+        {
+          uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos;
+
+          // Packet can not be larger than ep max size
+          uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
+
+          // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
+          // EP has to be checked if the buffer can take another WHOLE packet
+          if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break;
+
+          // Push packet to Tx-FIFO
+          if (xfer->ff)
+          {
+            usb_fifo_t tx_fifo = FIFO_BASE(rhport, n);
+            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *) tx_fifo, packet_size);
+          }
+          else
+          {
+            write_fifo_packet(rhport, n, xfer->buffer, packet_size);
+
+            // Increment pointer to xfer data
+            xfer->buffer += packet_size;
+          }
+        }
+
+        // Turn off TXFE if all bytes are written.
+        if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0)
+        {
+          dev->DIEPEMPMSK &= ~(1 << n);
+        }
+      }
+    }
+  }
+}
+
+void dcd_int_handler(uint8_t rhport)
+{
+  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
+  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
+  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
+  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
+
+  uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
+
+  if(int_status & USB_OTG_GINTSTS_USBRST)
+  {
+    // USBRST is start of reset.
+    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST;
+    bus_reset(rhport);
+  }
+
+  if(int_status & USB_OTG_GINTSTS_ENUMDNE)
+  {
+    // ENUMDNE is the end of reset where speed of the link is detected
+
+    usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
+
+    tusb_speed_t const speed = get_speed(rhport);
+
+    set_turnaround(usb_otg, speed);
+    dcd_event_bus_reset(rhport, speed, true);
+  }
+
+  if(int_status & USB_OTG_GINTSTS_USBSUSP)
+  {
+    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP;
+    dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+  }
+
+  if(int_status & USB_OTG_GINTSTS_WKUINT)
+  {
+    usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT;
+    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+  }
+
+  // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection
+  // if(int_status & USB_OTG_GINTSTS_DISCINT)
+
+  if(int_status & USB_OTG_GINTSTS_OTGINT)
+  {
+    // OTG INT bit is read-only
+    uint32_t const otg_int = usb_otg->GOTGINT;
+
+    if (otg_int & USB_OTG_GOTGINT_SEDET)
+    {
+      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+    }
+
+    usb_otg->GOTGINT = otg_int;
+  }
+
+  if(int_status & USB_OTG_GINTSTS_SOF)
+  {
+    usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
+
+    // Disable SOF interrupt since currently only used for remote wakeup detection
+    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM;
+
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+
+  // RxFIFO non-empty interrupt handling.
+  if(int_status & USB_OTG_GINTSTS_RXFLVL)
+  {
+    // RXFLVL bit is read-only
+
+    // Mask out RXFLVL while reading data from FIFO
+    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM;
+
+    // Loop until all available packets were handled
+    do
+    {
+      handle_rxflvl_ints(rhport, out_ep);
+    } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL);
+
+    // Manage RX FIFO size
+    if (_out_ep_closed)
+    {
+      update_grxfsiz(rhport);
+
+      // Disable flag
+      _out_ep_closed = false;
+    }
+
+    usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+  }
+
+  // OUT endpoint interrupt handling.
+  if(int_status & USB_OTG_GINTSTS_OEPINT)
+  {
+    // OEPINT is read-only
+    handle_epout_ints(rhport, dev, out_ep);
+  }
+
+  // IN endpoint interrupt handling.
+  if(int_status & USB_OTG_GINTSTS_IEPINT)
+  {
+    // IEPINT bit read-only
+    handle_epin_ints(rhport, dev, in_ep);
+  }
+
+  //  // Check for Incomplete isochronous IN transfer
+  //  if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
+  //    printf("      IISOIXFR!\r\n");
+  ////    TU_LOG2("      IISOIXFR!\r\n");
+  //  }
+}
+
+#endif
diff --git a/src/portable/broadcom/synopsys/synopsys_common.h b/src/portable/broadcom/synopsys/synopsys_common.h
new file mode 100644
index 000000000..6f0602fe9
--- /dev/null
+++ b/src/portable/broadcom/synopsys/synopsys_common.h
@@ -0,0 +1,1465 @@
+/**
+  ******************************************************************************
+  * @file    synopsys_common.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M3 Device USB OTG peripheral Header File. 
+  *          This file contains the USB OTG peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F1xx devices.
+  *            
+  *          This file contains:
+  *           - Data structures and the address mapping for the USB OTG peripheral
+  *           - The Peripheral's registers declarations and bits definition
+  *           - Macros to access the peripheral's registers hardware
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+#include "stdint.h"
+
+#pragma once
+
+#ifdef __cplusplus
+  #define   __I   volatile
+#else
+  #define   __I   volatile const
+#endif
+#define     __O   volatile
+#define     __IO  volatile
+#define     __IM  volatile const
+#define     __OM  volatile
+#define     __IOM volatile
+
+/** 
+  * @brief __USB_OTG_Core_register
+  */
+
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register       Address offset: 000h */
+  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                Address offset: 004h */
+  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register           Address offset: 008h */
+  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register           Address offset: 00Ch */
+  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                       Address offset: 010h */
+  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                   Address offset: 014h */
+  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register              Address offset: 018h */
+  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register               Address offset: 01Ch */
+  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register         Address offset: 020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                 Address offset: 024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register  Address offset: 028h */
+  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg        Address offset: 02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved 030h*/
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                Address offset: 038h */
+  __IO uint32_t CID;                  /*!< User ID Register                           Address offset: 03Ch */
+  uint32_t  Reserved40[48];           /*!< Reserved 040h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg             Address offset: 100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                 Address offset: 0x104 */
+} USB_OTG_GlobalTypeDef;
+
+/** 
+  * @brief __device_Registers
+  */
+
+typedef struct 
+{
+  __IO uint32_t DCFG;                 /*!< dev Configuration Register                 Address offset: 800h*/
+  __IO uint32_t DCTL;                 /*!< dev Control Register                       Address offset: 804h*/
+  __IO uint32_t DSTS;                 /*!< dev Status Register (RO)                   Address offset: 808h*/
+  uint32_t Reserved0C;                /*!< Reserved 80Ch*/
+  __IO uint32_t DIEPMSK;              /*!< dev IN Endpoint Mask                       Address offset: 810h*/
+  __IO uint32_t DOEPMSK;              /*!< dev OUT Endpoint Mask                      Address offset: 814h*/
+  __IO uint32_t DAINT;                /*!< dev All Endpoints Itr Reg                  Address offset: 818h*/
+  __IO uint32_t DAINTMSK;             /*!< dev All Endpoints Itr Mask                 Address offset: 81Ch*/
+  uint32_t  Reserved20;               /*!< Reserved 820h*/
+  uint32_t Reserved9;                 /*!< Reserved 824h*/
+  __IO uint32_t DVBUSDIS;             /*!< dev VBUS discharge Register                Address offset: 828h*/
+  __IO uint32_t DVBUSPULSE;           /*!< dev VBUS Pulse Register                    Address offset: 82Ch*/
+  __IO uint32_t DTHRCTL;              /*!< dev thr                                    Address offset: 830h*/
+  __IO uint32_t DIEPEMPMSK;           /*!< dev empty msk                              Address offset: 834h*/
+  __IO uint32_t DEACHINT;             /*!< dedicated EP interrupt                     Address offset: 838h*/
+  __IO uint32_t DEACHMSK;             /*!< dedicated EP msk                           Address offset: 83Ch*/  
+  uint32_t Reserved40;                /*!< dedicated EP mask                          Address offset: 840h*/
+  __IO uint32_t DINEP1MSK;            /*!< dedicated EP mask                          Address offset: 844h*/
+  uint32_t  Reserved44[15];           /*!< Reserved 844-87Ch*/
+  __IO uint32_t DOUTEP1MSK;           /*!< dedicated EP msk                           Address offset: 884h*/
+} USB_OTG_DeviceTypeDef;
+
+/** 
+  * @brief __IN_Endpoint-Specific_Register
+  */
+
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;              /*!< dev IN Endpoint Control Reg                900h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;                /*!< Reserved                                   900h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DIEPINT;              /*!< dev IN Endpoint Itr Reg                    900h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;                /*!< Reserved                                   900h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DIEPTSIZ;             /*!< IN Endpoint Txfer Size                     900h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DIEPDMA;              /*!< IN Endpoint DMA Address Reg                900h + (ep_num * 20h) + 14h*/
+  __IO uint32_t DTXFSTS;              /*!< IN Endpoint Tx FIFO Status Reg             900h + (ep_num * 20h) + 18h*/
+  uint32_t Reserved18;                /*!< Reserved                                   900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+} USB_OTG_INEndpointTypeDef;
+
+/** 
+  * @brief __OUT_Endpoint-Specific_Registers
+  */
+
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;              /*!< dev OUT Endpoint Control Reg               B00h + (ep_num * 20h) + 00h*/
+  uint32_t Reserved04;                /*!< Reserved                                   B00h + (ep_num * 20h) + 04h*/
+  __IO uint32_t DOEPINT;              /*!< dev OUT Endpoint Itr Reg                   B00h + (ep_num * 20h) + 08h*/
+  uint32_t Reserved0C;                /*!< Reserved                                   B00h + (ep_num * 20h) + 0Ch*/
+  __IO uint32_t DOEPTSIZ;             /*!< dev OUT Endpoint Txfer Size                B00h + (ep_num * 20h) + 10h*/
+  __IO uint32_t DOEPDMA;              /*!< dev OUT Endpoint DMA Address               B00h + (ep_num * 20h) + 14h*/
+  uint32_t Reserved18[2];             /*!< Reserved                                   B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
+} USB_OTG_OUTEndpointTypeDef;
+
+/** 
+  * @brief __Host_Mode_Register_Structures
+  */
+
+typedef struct 
+{
+  __IO uint32_t HCFG;                 /*!< Host Configuration Register    400h*/
+  __IO uint32_t HFIR;                 /*!< Host Frame Interval Register   404h*/
+  __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining 408h*/
+  uint32_t Reserved40C;               /*!< Reserved                       40Ch*/
+  __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status 410h*/
+  __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register 414h*/
+  __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask 418h*/
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief __Host_Channel_Specific_Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t HCCHAR;
+  __IO uint32_t HCSPLT;
+  __IO uint32_t HCINT;
+  __IO uint32_t HCINTMSK;
+  __IO uint32_t HCTSIZ;
+  __IO uint32_t HCDMA;
+  uint32_t Reserved[2];
+} USB_OTG_HostChannelTypeDef;
+
+/*!< USB registers base address */
+#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE                  0x00000000UL
+#define USB_OTG_DEVICE_BASE                  0x00000800UL
+#define USB_OTG_IN_ENDPOINT_BASE             0x00000900UL
+#define USB_OTG_OUT_ENDPOINT_BASE            0x00000B00UL
+#define USB_OTG_EP_REG_SIZE                  0x00000020UL
+#define USB_OTG_HOST_BASE                    0x00000400UL
+#define USB_OTG_HOST_PORT_BASE               0x00000440UL
+#define USB_OTG_HOST_CHANNEL_BASE            0x00000500UL
+#define USB_OTG_HOST_CHANNEL_SIZE            0x00000020UL
+#define USB_OTG_PCGCCTL_BASE                 0x00000E00UL
+#define USB_OTG_FIFO_BASE                    0x00001000UL
+#define USB_OTG_FIFO_SIZE                    0x00001000UL
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 USB_OTG                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos              (0U)                           
+#define USB_OTG_GOTGCTL_SRQSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                  USB_OTG_GOTGCTL_SRQSCS_Msk     /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                 (1U)                           
+#define USB_OTG_GOTGCTL_SRQ_Msk                 (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                     USB_OTG_GOTGCTL_SRQ_Msk        /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos              (8U)                           
+#define USB_OTG_GOTGCTL_HNGSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos               (9U)                           
+#define USB_OTG_GOTGCTL_HNPRQ_Msk               (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                   USB_OTG_GOTGCTL_HNPRQ_Msk      /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos             (10U)                          
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk             (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                 USB_OTG_GOTGCTL_HSHNPEN_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos              (11U)                          
+#define USB_OTG_GOTGCTL_DHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                  USB_OTG_GOTGCTL_DHNPEN_Msk     /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos              (16U)                          
+#define USB_OTG_GOTGCTL_CIDSTS_Msk              (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                  USB_OTG_GOTGCTL_CIDSTS_Msk     /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                (17U)                          
+#define USB_OTG_GOTGCTL_DBCT_Msk                (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                    USB_OTG_GOTGCTL_DBCT_Msk       /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos               (18U)                          
+#define USB_OTG_GOTGCTL_ASVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                   USB_OTG_GOTGCTL_ASVLD_Msk      /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos               (19U)                          
+#define USB_OTG_GOTGCTL_BSVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD                   USB_OTG_GOTGCTL_BSVLD_Msk      /*!< B-session valid */
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                (0U)                           
+#define USB_OTG_HCFG_FSLSPCS_Msk                (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                    USB_OTG_HCFG_FSLSPCS_Msk       /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0                  (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                  (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                  (2U)                           
+#define USB_OTG_HCFG_FSLSS_Msk                  (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                      USB_OTG_HCFG_FSLSS_Msk         /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                   (0U)                           
+#define USB_OTG_DCFG_DSPD_Msk                   (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                       USB_OTG_DCFG_DSPD_Msk          /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                     (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                     (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos               (2U)                           
+#define USB_OTG_DCFG_NZLSOHSK_Msk               (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                   USB_OTG_DCFG_NZLSOHSK_Msk      /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                    (4U)                           
+#define USB_OTG_DCFG_DAD_Msk                    (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                        USB_OTG_DCFG_DAD_Msk           /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                      (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                      (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                      (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                      (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                      (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                      (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                      (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                  (11U)                          
+#define USB_OTG_DCFG_PFIVL_Msk                  (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                      USB_OTG_DCFG_PFIVL_Msk         /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                    (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                    (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos              (24U)                          
+#define USB_OTG_DCFG_PERSCHIVL_Msk              (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                  USB_OTG_DCFG_PERSCHIVL_Msk     /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos               (0U)                           
+#define USB_OTG_PCGCR_STPPCLK_Msk               (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                   USB_OTG_PCGCR_STPPCLK_Msk      /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos              (1U)                           
+#define USB_OTG_PCGCR_GATEHCLK_Msk              (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                  USB_OTG_PCGCR_GATEHCLK_Msk     /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos               (4U)                           
+#define USB_OTG_PCGCR_PHYSUSP_Msk               (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                   USB_OTG_PCGCR_PHYSUSP_Msk      /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos               (2U)                           
+#define USB_OTG_GOTGINT_SEDET_Msk               (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                   USB_OTG_GOTGINT_SEDET_Msk      /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos             (8U)                           
+#define USB_OTG_GOTGINT_SRSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                 USB_OTG_GOTGINT_SRSSCHG_Msk    /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos             (9U)                           
+#define USB_OTG_GOTGINT_HNSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                 USB_OTG_GOTGINT_HNSSCHG_Msk    /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos              (17U)                          
+#define USB_OTG_GOTGINT_HNGDET_Msk              (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                  USB_OTG_GOTGINT_HNGDET_Msk     /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos             (18U)                          
+#define USB_OTG_GOTGINT_ADTOCHG_Msk             (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                 USB_OTG_GOTGINT_ADTOCHG_Msk    /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos              (19U)                          
+#define USB_OTG_GOTGINT_DBCDNE_Msk              (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                  USB_OTG_GOTGINT_DBCDNE_Msk     /*!< Debounce done */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                 (0U)                           
+#define USB_OTG_DCTL_RWUSIG_Msk                 (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                     USB_OTG_DCTL_RWUSIG_Msk        /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                   (1U)                           
+#define USB_OTG_DCTL_SDIS_Msk                   (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                       USB_OTG_DCTL_SDIS_Msk          /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos                 (2U)                           
+#define USB_OTG_DCTL_GINSTS_Msk                 (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                     USB_OTG_DCTL_GINSTS_Msk        /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos                 (3U)                           
+#define USB_OTG_DCTL_GONSTS_Msk                 (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                     USB_OTG_DCTL_GONSTS_Msk        /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos                   (4U)                           
+#define USB_OTG_DCTL_TCTL_Msk                   (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                       USB_OTG_DCTL_TCTL_Msk          /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                     (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                     (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                     (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                 (7U)                           
+#define USB_OTG_DCTL_SGINAK_Msk                 (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                     USB_OTG_DCTL_SGINAK_Msk        /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos                 (8U)                           
+#define USB_OTG_DCTL_CGINAK_Msk                 (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                     USB_OTG_DCTL_CGINAK_Msk        /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos                 (9U)                           
+#define USB_OTG_DCTL_SGONAK_Msk                 (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                     USB_OTG_DCTL_SGONAK_Msk        /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos                 (10U)                          
+#define USB_OTG_DCTL_CGONAK_Msk                 (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                     USB_OTG_DCTL_CGONAK_Msk        /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos               (11U)                          
+#define USB_OTG_DCTL_POPRGDNE_Msk               (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                   USB_OTG_DCTL_POPRGDNE_Msk      /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                  (0U)                           
+#define USB_OTG_HFIR_FRIVL_Msk                  (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                      USB_OTG_HFIR_FRIVL_Msk         /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                 (0U)                           
+#define USB_OTG_HFNUM_FRNUM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                     USB_OTG_HFNUM_FRNUM_Msk        /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos                 (16U)                          
+#define USB_OTG_HFNUM_FTREM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                     USB_OTG_HFNUM_FTREM_Msk        /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                (0U)                           
+#define USB_OTG_DSTS_SUSPSTS_Msk                (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                    USB_OTG_DSTS_SUSPSTS_Msk       /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                (1U)                           
+#define USB_OTG_DSTS_ENUMSPD_Msk                (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                    USB_OTG_DSTS_ENUMSPD_Msk       /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                  (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                  (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                   (3U)                           
+#define USB_OTG_DSTS_EERR_Msk                   (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                       USB_OTG_DSTS_EERR_Msk          /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos                  (8U)                           
+#define USB_OTG_DSTS_FNSOF_Msk                  (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                      USB_OTG_DSTS_FNSOF_Msk         /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                (0U)                           
+#define USB_OTG_GAHBCFG_GINT_Msk                (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                    USB_OTG_GAHBCFG_GINT_Msk       /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)                           
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk             (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                 USB_OTG_GAHBCFG_HBSTLEN_Msk    /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)                           
+#define USB_OTG_GAHBCFG_DMAEN_Msk               (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                   USB_OTG_GAHBCFG_DMAEN_Msk      /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos             (7U)                           
+#define USB_OTG_GAHBCFG_TXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                 USB_OTG_GAHBCFG_TXFELVL_Msk    /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos            (8U)                           
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk            (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                USB_OTG_GAHBCFG_PTXFELVL_Msk   /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos               (0U)                           
+#define USB_OTG_GUSBCFG_TOCAL_Msk               (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                   USB_OTG_GUSBCFG_TOCAL_Msk      /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos              (6U)                           
+#define USB_OTG_GUSBCFG_PHYSEL_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                  USB_OTG_GUSBCFG_PHYSEL_Msk     /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos              (8U)                           
+#define USB_OTG_GUSBCFG_SRPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                  USB_OTG_GUSBCFG_SRPCAP_Msk     /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos              (9U)                           
+#define USB_OTG_GUSBCFG_HNPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                  USB_OTG_GUSBCFG_HNPCAP_Msk     /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                (10U)                          
+#define USB_OTG_GUSBCFG_TRDT_Msk                (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                    USB_OTG_GUSBCFG_TRDT_Msk       /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                  (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                  (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                  (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos             (15U)                          
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk             (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 USB_OTG_GUSBCFG_PHYLPCS_Msk    /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos            (17U)                          
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk            (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                USB_OTG_GUSBCFG_ULPIFSLS_Msk   /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos              (18U)                          
+#define USB_OTG_GUSBCFG_ULPIAR_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                  USB_OTG_GUSBCFG_ULPIAR_Msk     /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos             (19U)                          
+#define USB_OTG_GUSBCFG_ULPICSM_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                 USB_OTG_GUSBCFG_ULPICSM_Msk    /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos          (20U)                          
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos          (21U)                          
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos               (22U)                          
+#define USB_OTG_GUSBCFG_TSDPS_Msk               (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                   USB_OTG_GUSBCFG_TSDPS_Msk      /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                (23U)                          
+#define USB_OTG_GUSBCFG_PCCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                    USB_OTG_GUSBCFG_PCCI_Msk       /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos                (24U)                          
+#define USB_OTG_GUSBCFG_PTCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                    USB_OTG_GUSBCFG_PTCI_Msk       /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos             (25U)                          
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                 USB_OTG_GUSBCFG_ULPIIPD_Msk    /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos               (29U)                          
+#define USB_OTG_GUSBCFG_FHMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                   USB_OTG_GUSBCFG_FHMOD_Msk      /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos               (30U)                          
+#define USB_OTG_GUSBCFG_FDMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                   USB_OTG_GUSBCFG_FDMOD_Msk      /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos              (31U)                          
+#define USB_OTG_GUSBCFG_CTXPKT_Msk              (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                  USB_OTG_GUSBCFG_CTXPKT_Msk     /*!< Corrupt Tx packet */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos               (0U)                           
+#define USB_OTG_GRSTCTL_CSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                   USB_OTG_GRSTCTL_CSRST_Msk      /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos               (1U)                           
+#define USB_OTG_GRSTCTL_HSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                   USB_OTG_GRSTCTL_HSRST_Msk      /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos               (2U)                           
+#define USB_OTG_GRSTCTL_FCRST_Msk               (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                   USB_OTG_GRSTCTL_FCRST_Msk      /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos             (4U)                           
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                 USB_OTG_GRSTCTL_RXFFLSH_Msk    /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos             (5U)                           
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                 USB_OTG_GRSTCTL_TXFFLSH_Msk    /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos              (6U)                           
+#define USB_OTG_GRSTCTL_TXFNUM_Msk              (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                  USB_OTG_GRSTCTL_TXFNUM_Msk     /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos              (30U)                          
+#define USB_OTG_GRSTCTL_DMAREQ_Msk              (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                  USB_OTG_GRSTCTL_DMAREQ_Msk     /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos              (31U)                          
+#define USB_OTG_GRSTCTL_AHBIDL_Msk              (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                  USB_OTG_GRSTCTL_AHBIDL_Msk     /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos               (0U)                           
+#define USB_OTG_DIEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                   USB_OTG_DIEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos                (1U)                           
+#define USB_OTG_DIEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                    USB_OTG_DIEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos                 (3U)                           
+#define USB_OTG_DIEPMSK_TOM_Msk                 (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                     USB_OTG_DIEPMSK_TOM_Msk        /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos           (4U)                           
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk           (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               USB_OTG_DIEPMSK_ITTXFEMSK_Msk  /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos             (5U)                           
+#define USB_OTG_DIEPMSK_INEPNMM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                 USB_OTG_DIEPMSK_INEPNMM_Msk    /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos             (6U)                           
+#define USB_OTG_DIEPMSK_INEPNEM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                 USB_OTG_DIEPMSK_INEPNEM_Msk    /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos              (8U)                           
+#define USB_OTG_DIEPMSK_TXFURM_Msk              (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                  USB_OTG_DIEPMSK_TXFURM_Msk     /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos                 (9U)                           
+#define USB_OTG_DIEPMSK_BIM_Msk                 (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                     USB_OTG_DIEPMSK_BIM_Msk        /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos            (0U)                           
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk            (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                USB_OTG_HPTXSTS_PTXFSAVL_Msk   /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos             (16U)                          
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 USB_OTG_HPTXSTS_PTXQSAV_Msk    /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos             (24U)                          
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 USB_OTG_HPTXSTS_PTXQTOP_Msk    /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                 (0U)                           
+#define USB_OTG_HAINT_HAINT_Msk                 (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                     USB_OTG_HAINT_HAINT_Msk        /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos               (0U)                           
+#define USB_OTG_DOEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                   USB_OTG_DOEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                (1U)                           
+#define USB_OTG_DOEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                    USB_OTG_DOEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
+#define USB_OTG_DOEPMSK_STUPM_Pos               (3U)                           
+#define USB_OTG_DOEPMSK_STUPM_Msk               (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                   USB_OTG_DOEPMSK_STUPM_Msk      /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos              (4U)                           
+#define USB_OTG_DOEPMSK_OTEPDM_Msk              (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                  USB_OTG_DOEPMSK_OTEPDM_Msk     /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos             (6U)                           
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                 USB_OTG_DOEPMSK_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos                (8U)                           
+#define USB_OTG_DOEPMSK_OPEM_Msk                (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                    USB_OTG_DOEPMSK_OPEM_Msk       /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos                (9U)                           
+#define USB_OTG_DOEPMSK_BOIM_Msk                (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                    USB_OTG_DOEPMSK_BOIM_Msk       /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                (0U)                           
+#define USB_OTG_GINTSTS_CMOD_Msk                (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                    USB_OTG_GINTSTS_CMOD_Msk       /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos                (1U)                           
+#define USB_OTG_GINTSTS_MMIS_Msk                (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                    USB_OTG_GINTSTS_MMIS_Msk       /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos              (2U)                           
+#define USB_OTG_GINTSTS_OTGINT_Msk              (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                  USB_OTG_GINTSTS_OTGINT_Msk     /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos                 (3U)                           
+#define USB_OTG_GINTSTS_SOF_Msk                 (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                     USB_OTG_GINTSTS_SOF_Msk        /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos              (4U)                           
+#define USB_OTG_GINTSTS_RXFLVL_Msk              (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                  USB_OTG_GINTSTS_RXFLVL_Msk     /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos              (5U)                           
+#define USB_OTG_GINTSTS_NPTXFE_Msk              (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                  USB_OTG_GINTSTS_NPTXFE_Msk     /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos            (6U)                           
+#define USB_OTG_GINTSTS_GINAKEFF_Msk            (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                USB_OTG_GINTSTS_GINAKEFF_Msk   /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos          (7U)                           
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk          (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos               (10U)                          
+#define USB_OTG_GINTSTS_ESUSP_Msk               (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                   USB_OTG_GINTSTS_ESUSP_Msk      /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos             (11U)                          
+#define USB_OTG_GINTSTS_USBSUSP_Msk             (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                 USB_OTG_GINTSTS_USBSUSP_Msk    /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos              (12U)                          
+#define USB_OTG_GINTSTS_USBRST_Msk              (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                  USB_OTG_GINTSTS_USBRST_Msk     /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos             (13U)                          
+#define USB_OTG_GINTSTS_ENUMDNE_Msk             (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                 USB_OTG_GINTSTS_ENUMDNE_Msk    /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos             (14U)                          
+#define USB_OTG_GINTSTS_ISOODRP_Msk             (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                 USB_OTG_GINTSTS_ISOODRP_Msk    /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos                (15U)                          
+#define USB_OTG_GINTSTS_EOPF_Msk                (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                    USB_OTG_GINTSTS_EOPF_Msk       /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos              (18U)                          
+#define USB_OTG_GINTSTS_IEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                  USB_OTG_GINTSTS_IEPINT_Msk     /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos              (19U)                          
+#define USB_OTG_GINTSTS_OEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                  USB_OTG_GINTSTS_OEPINT_Msk     /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos            (20U)                          
+#define USB_OTG_GINTSTS_IISOIXFR_Msk            (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                USB_OTG_GINTSTS_IISOIXFR_Msk   /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)                          
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos           (22U)                          
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk           (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP               USB_OTG_GINTSTS_DATAFSUSP_Msk  /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos             (24U)                          
+#define USB_OTG_GINTSTS_HPRTINT_Msk             (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                 USB_OTG_GINTSTS_HPRTINT_Msk    /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos               (25U)                          
+#define USB_OTG_GINTSTS_HCINT_Msk               (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                   USB_OTG_GINTSTS_HCINT_Msk      /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos               (26U)                          
+#define USB_OTG_GINTSTS_PTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                   USB_OTG_GINTSTS_PTXFE_Msk      /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos             (28U)                          
+#define USB_OTG_GINTSTS_CIDSCHG_Msk             (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                 USB_OTG_GINTSTS_CIDSCHG_Msk    /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos             (29U)                          
+#define USB_OTG_GINTSTS_DISCINT_Msk             (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                 USB_OTG_GINTSTS_DISCINT_Msk    /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos              (30U)                          
+#define USB_OTG_GINTSTS_SRQINT_Msk              (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                  USB_OTG_GINTSTS_SRQINT_Msk     /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos              (31U)                          
+#define USB_OTG_GINTSTS_WKUINT_Msk              (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                  USB_OTG_GINTSTS_WKUINT_Msk     /*!< Resume/remote wakeup detected interrupt */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos               (1U)                           
+#define USB_OTG_GINTMSK_MMISM_Msk               (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                   USB_OTG_GINTMSK_MMISM_Msk      /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos              (2U)                           
+#define USB_OTG_GINTMSK_OTGINT_Msk              (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                  USB_OTG_GINTMSK_OTGINT_Msk     /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos                (3U)                           
+#define USB_OTG_GINTMSK_SOFM_Msk                (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                    USB_OTG_GINTMSK_SOFM_Msk       /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos             (4U)                           
+#define USB_OTG_GINTMSK_RXFLVLM_Msk             (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                 USB_OTG_GINTMSK_RXFLVLM_Msk    /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos             (5U)                           
+#define USB_OTG_GINTMSK_NPTXFEM_Msk             (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                 USB_OTG_GINTMSK_NPTXFEM_Msk    /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos           (6U)                           
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM               USB_OTG_GINTMSK_GINAKEFFM_Msk  /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos           (7U)                           
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM               USB_OTG_GINTMSK_GONAKEFFM_Msk  /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos              (10U)                          
+#define USB_OTG_GINTMSK_ESUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                  USB_OTG_GINTMSK_ESUSPM_Msk     /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos            (11U)                          
+#define USB_OTG_GINTMSK_USBSUSPM_Msk            (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                USB_OTG_GINTMSK_USBSUSPM_Msk   /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos              (12U)                          
+#define USB_OTG_GINTMSK_USBRST_Msk              (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                  USB_OTG_GINTMSK_USBRST_Msk     /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos            (13U)                          
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk            (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                USB_OTG_GINTMSK_ENUMDNEM_Msk   /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos            (14U)                          
+#define USB_OTG_GINTMSK_ISOODRPM_Msk            (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                USB_OTG_GINTMSK_ISOODRPM_Msk   /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos               (15U)                          
+#define USB_OTG_GINTMSK_EOPFM_Msk               (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                   USB_OTG_GINTMSK_EOPFM_Msk      /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos              (17U)                          
+#define USB_OTG_GINTMSK_EPMISM_Msk              (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                  USB_OTG_GINTMSK_EPMISM_Msk     /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos              (18U)                          
+#define USB_OTG_GINTMSK_IEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                  USB_OTG_GINTMSK_IEPINT_Msk     /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos              (19U)                          
+#define USB_OTG_GINTMSK_OEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                  USB_OTG_GINTMSK_OEPINT_Msk     /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos           (20U)                          
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk           (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM               USB_OTG_GINTMSK_IISOIXFRM_Msk  /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos     (21U)                          
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk     (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos              (22U)                          
+#define USB_OTG_GINTMSK_FSUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                  USB_OTG_GINTMSK_FSUSPM_Msk     /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos               (24U)                          
+#define USB_OTG_GINTMSK_PRTIM_Msk               (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                   USB_OTG_GINTMSK_PRTIM_Msk      /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos                (25U)                          
+#define USB_OTG_GINTMSK_HCIM_Msk                (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                    USB_OTG_GINTMSK_HCIM_Msk       /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos              (26U)                          
+#define USB_OTG_GINTMSK_PTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                  USB_OTG_GINTMSK_PTXFEM_Msk     /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos            (28U)                          
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk            (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                USB_OTG_GINTMSK_CIDSCHGM_Msk   /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos             (29U)                          
+#define USB_OTG_GINTMSK_DISCINT_Msk             (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                 USB_OTG_GINTMSK_DISCINT_Msk    /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos               (30U)                          
+#define USB_OTG_GINTMSK_SRQIM_Msk               (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                   USB_OTG_GINTMSK_SRQIM_Msk      /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                (31U)                          
+#define USB_OTG_GINTMSK_WUIM_Msk                (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                    USB_OTG_GINTMSK_WUIM_Msk       /*!< Resume/remote wakeup detected interrupt mask */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                (0U)                           
+#define USB_OTG_DAINT_IEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                    USB_OTG_DAINT_IEPINT_Msk       /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos                (16U)                          
+#define USB_OTG_DAINT_OEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                    USB_OTG_DAINT_OEPINT_Msk       /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos             (0U)                           
+#define USB_OTG_HAINTMSK_HAINTM_Msk             (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                 USB_OTG_HAINTMSK_HAINTM_Msk    /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos               (0U)                           
+#define USB_OTG_GRXSTSP_EPNUM_Msk               (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                   USB_OTG_GRXSTSP_EPNUM_Msk      /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos                (4U)                           
+#define USB_OTG_GRXSTSP_BCNT_Msk                (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                    USB_OTG_GRXSTSP_BCNT_Msk       /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                (15U)                          
+#define USB_OTG_GRXSTSP_DPID_Msk                (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                    USB_OTG_GRXSTSP_DPID_Msk       /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos              (17U)                          
+#define USB_OTG_GRXSTSP_PKTSTS_Msk              (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                  USB_OTG_GRXSTSP_PKTSTS_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos               (0U)                           
+#define USB_OTG_DAINTMSK_IEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                   USB_OTG_DAINTMSK_IEPM_Msk      /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos               (16U)                          
+#define USB_OTG_DAINTMSK_OEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                   USB_OTG_DAINTMSK_OEPM_Msk      /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                (0U)                           
+#define USB_OTG_GRXFSIZ_RXFD_Msk                (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                    USB_OTG_GRXFSIZ_RXFD_Msk       /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos             (0U)                           
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk             (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                 USB_OTG_DVBUSDIS_VBUSDT_Msk    /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                     (0U)                           
+#define USB_OTG_NPTXFSA_Msk                     (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                         USB_OTG_NPTXFSA_Msk            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                      (16U)                          
+#define USB_OTG_NPTXFD_Msk                      (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                          USB_OTG_NPTXFD_Msk             /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos                      (0U)                           
+#define USB_OTG_TX0FSA_Msk                      (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                          USB_OTG_TX0FSA_Msk             /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos                       (16U)                          
+#define USB_OTG_TX0FD_Msk                       (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                           USB_OTG_TX0FD_Msk              /*!< Endpoint 0 TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos           (0U)                           
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk           (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP               USB_OTG_DVBUSPULSE_DVBUSP_Msk  /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos           (0U)                           
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk           (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV               USB_OTG_GNPTXSTS_NPTXFSAV_Msk  /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos           (16U)                          
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk           (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV               USB_OTG_GNPTXSTS_NPTQXSAV_Msk  /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0             (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1             (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2             (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3             (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4             (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5             (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6             (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7             (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos           (24U)                          
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk           (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP               USB_OTG_GNPTXSTS_NPTXQTOP_Msk  /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0             (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1             (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2             (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3             (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4             (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5             (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6             (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos         (0U)                           
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk         (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN             USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos            (1U)                           
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk            (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                USB_OTG_DTHRCTL_ISOTHREN_Msk   /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos            (2U)                           
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                USB_OTG_DTHRCTL_TXTHRLEN_Msk   /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos             (16U)                          
+#define USB_OTG_DTHRCTL_RXTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                 USB_OTG_DTHRCTL_RXTHREN_Msk    /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos            (17U)                          
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                USB_OTG_DTHRCTL_RXTHRLEN_Msk   /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos               (27U)                          
+#define USB_OTG_DTHRCTL_ARPEN_Msk               (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                   USB_OTG_DTHRCTL_ARPEN_Msk      /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos        (0U)                           
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk        (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM            USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos            (1U)                           
+#define USB_OTG_DEACHINT_IEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                USB_OTG_DEACHINT_IEP1INT_Msk   /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos            (17U)                          
+#define USB_OTG_DEACHINT_OEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                USB_OTG_DEACHINT_OEP1INT_Msk   /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos                (16U)                          
+#define USB_OTG_GCCFG_PWRDWN_Msk                (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                    USB_OTG_GCCFG_PWRDWN_Msk       /*!< Power down */
+#define USB_OTG_GCCFG_VBUSASEN_Pos              (18U)                          
+#define USB_OTG_GCCFG_VBUSASEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN                  USB_OTG_GCCFG_VBUSASEN_Msk     /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos              (19U)                          
+#define USB_OTG_GCCFG_VBUSBSEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN                  USB_OTG_GCCFG_VBUSBSEN_Msk     /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos              (20U)                          
+#define USB_OTG_GCCFG_SOFOUTEN_Msk              (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN                  USB_OTG_GCCFG_SOFOUTEN_Msk     /*!< SOF output enable */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos        (1U)                           
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM            USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos        (17U)                          
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM            USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos              (0U)                           
+#define USB_OTG_CID_PRODUCT_ID_Msk              (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                  USB_OTG_CID_PRODUCT_ID_Msk     /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos          (0U)                           
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM              USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos           (1U)                           
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM               USB_OTG_DIEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos            (3U)                           
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                USB_OTG_DIEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK          USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos        (5U)                           
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM            USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos        (6U)                           
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM            USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos         (8U)                           
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM             USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos            (9U)                           
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                USB_OTG_DIEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos           (13U)                          
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM               USB_OTG_DIEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                  (0U)                           
+#define USB_OTG_HPRT_PCSTS_Msk                  (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                      USB_OTG_HPRT_PCSTS_Msk         /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos                  (1U)                           
+#define USB_OTG_HPRT_PCDET_Msk                  (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                      USB_OTG_HPRT_PCDET_Msk         /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos                   (2U)                           
+#define USB_OTG_HPRT_PENA_Msk                   (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                       USB_OTG_HPRT_PENA_Msk          /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos                (3U)                           
+#define USB_OTG_HPRT_PENCHNG_Msk                (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                    USB_OTG_HPRT_PENCHNG_Msk       /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                   (4U)                           
+#define USB_OTG_HPRT_POCA_Msk                   (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                       USB_OTG_HPRT_POCA_Msk          /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos                (5U)                           
+#define USB_OTG_HPRT_POCCHNG_Msk                (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                    USB_OTG_HPRT_POCCHNG_Msk       /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos                   (6U)                           
+#define USB_OTG_HPRT_PRES_Msk                   (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                       USB_OTG_HPRT_PRES_Msk          /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos                  (7U)                           
+#define USB_OTG_HPRT_PSUSP_Msk                  (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                      USB_OTG_HPRT_PSUSP_Msk         /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos                   (8U)                           
+#define USB_OTG_HPRT_PRST_Msk                   (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                       USB_OTG_HPRT_PRST_Msk          /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos                  (10U)                          
+#define USB_OTG_HPRT_PLSTS_Msk                  (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                      USB_OTG_HPRT_PLSTS_Msk         /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                    (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                    (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                   (12U)                          
+#define USB_OTG_HPRT_PPWR_Msk                   (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                       USB_OTG_HPRT_PPWR_Msk          /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                  (13U)                          
+#define USB_OTG_HPRT_PTCTL_Msk                  (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                      USB_OTG_HPRT_PTCTL_Msk         /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                    (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                    (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                    (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                    (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                   (17U)                          
+#define USB_OTG_HPRT_PSPD_Msk                   (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                       USB_OTG_HPRT_PSPD_Msk          /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                     (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                     (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos          (0U)                           
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM              USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos           (1U)                           
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM               USB_OTG_DOEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos            (3U)                           
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                USB_OTG_DOEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK          USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos        (5U)                           
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM            USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos        (6U)                           
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM            USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos         (8U)                           
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM             USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos            (9U)                           
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                USB_OTG_DOEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos          (12U)                          
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM              USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos           (13U)                          
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM               USB_OTG_DOEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos          (14U)                          
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM              USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos              (0U)                           
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                  USB_OTG_HPTXFSIZ_PTXSA_Msk     /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos              (16U)                          
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                  USB_OTG_HPTXFSIZ_PTXFD_Msk     /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos               (0U)                           
+#define USB_OTG_DIEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                   USB_OTG_DIEPCTL_MPSIZ_Msk      /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos              (15U)                          
+#define USB_OTG_DIEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                  USB_OTG_DIEPCTL_USBAEP_Msk     /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos          (16U)                          
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk          (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID              USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos              (17U)                          
+#define USB_OTG_DIEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                  USB_OTG_DIEPCTL_NAKSTS_Msk     /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos               (18U)                          
+#define USB_OTG_DIEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                   USB_OTG_DIEPCTL_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos               (21U)                          
+#define USB_OTG_DIEPCTL_STALL_Msk               (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                   USB_OTG_DIEPCTL_STALL_Msk      /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos              (22U)                          
+#define USB_OTG_DIEPCTL_TXFNUM_Msk              (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                  USB_OTG_DIEPCTL_TXFNUM_Msk     /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                (26U)                          
+#define USB_OTG_DIEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                    USB_OTG_DIEPCTL_CNAK_Msk       /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                (27U)                          
+#define USB_OTG_DIEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                    USB_OTG_DIEPCTL_SNAK_Msk       /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos             (29U)                          
+#define USB_OTG_DIEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                 USB_OTG_DIEPCTL_SODDFRM_Msk    /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos               (30U)                          
+#define USB_OTG_DIEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                   USB_OTG_DIEPCTL_EPDIS_Msk      /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos               (31U)                          
+#define USB_OTG_DIEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                   USB_OTG_DIEPCTL_EPENA_Msk      /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                (0U)                           
+#define USB_OTG_HCCHAR_MPSIZ_Msk                (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                    USB_OTG_HCCHAR_MPSIZ_Msk       /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                (11U)                          
+#define USB_OTG_HCCHAR_EPNUM_Msk                (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                    USB_OTG_HCCHAR_EPNUM_Msk       /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                  (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                  (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                  (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                  (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                (15U)                          
+#define USB_OTG_HCCHAR_EPDIR_Msk                (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                    USB_OTG_HCCHAR_EPDIR_Msk       /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                (17U)                          
+#define USB_OTG_HCCHAR_LSDEV_Msk                (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                    USB_OTG_HCCHAR_LSDEV_Msk       /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                (18U)                          
+#define USB_OTG_HCCHAR_EPTYP_Msk                (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                    USB_OTG_HCCHAR_EPTYP_Msk       /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                  (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                  (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+                                      
+#define USB_OTG_HCCHAR_MC_Pos                   (20U)                          
+#define USB_OTG_HCCHAR_MC_Msk                   (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                       USB_OTG_HCCHAR_MC_Msk          /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                     (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                     (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                  (22U)                          
+#define USB_OTG_HCCHAR_DAD_Msk                  (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                      USB_OTG_HCCHAR_DAD_Msk         /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                    (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                    (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                    (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                    (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                    (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                    (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                    (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos               (29U)                          
+#define USB_OTG_HCCHAR_ODDFRM_Msk               (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                   USB_OTG_HCCHAR_ODDFRM_Msk      /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                (30U)                          
+#define USB_OTG_HCCHAR_CHDIS_Msk                (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                    USB_OTG_HCCHAR_CHDIS_Msk       /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                (31U)                          
+#define USB_OTG_HCCHAR_CHENA_Msk                (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                    USB_OTG_HCCHAR_CHENA_Msk       /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos              (0U)                           
+#define USB_OTG_HCSPLT_PRTADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                  USB_OTG_HCSPLT_PRTADDR_Msk     /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos              (7U)                           
+#define USB_OTG_HCSPLT_HUBADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                  USB_OTG_HCSPLT_HUBADDR_Msk     /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos              (14U)                          
+#define USB_OTG_HCSPLT_XACTPOS_Msk              (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                  USB_OTG_HCSPLT_XACTPOS_Msk     /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos            (16U)                          
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk            (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                USB_OTG_HCSPLT_COMPLSPLT_Msk   /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos              (31U)                          
+#define USB_OTG_HCSPLT_SPLITEN_Msk              (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                  USB_OTG_HCSPLT_SPLITEN_Msk     /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                  (0U)                           
+#define USB_OTG_HCINT_XFRC_Msk                  (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                      USB_OTG_HCINT_XFRC_Msk         /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                   (1U)                           
+#define USB_OTG_HCINT_CHH_Msk                   (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                       USB_OTG_HCINT_CHH_Msk          /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                (2U)                           
+#define USB_OTG_HCINT_AHBERR_Msk                (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                    USB_OTG_HCINT_AHBERR_Msk       /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                 (3U)                           
+#define USB_OTG_HCINT_STALL_Msk                 (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                     USB_OTG_HCINT_STALL_Msk        /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                   (4U)                           
+#define USB_OTG_HCINT_NAK_Msk                   (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                       USB_OTG_HCINT_NAK_Msk          /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                   (5U)                           
+#define USB_OTG_HCINT_ACK_Msk                   (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                       USB_OTG_HCINT_ACK_Msk          /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                  (6U)                           
+#define USB_OTG_HCINT_NYET_Msk                  (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                      USB_OTG_HCINT_NYET_Msk         /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                 (7U)                           
+#define USB_OTG_HCINT_TXERR_Msk                 (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                     USB_OTG_HCINT_TXERR_Msk        /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                 (8U)                           
+#define USB_OTG_HCINT_BBERR_Msk                 (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                     USB_OTG_HCINT_BBERR_Msk        /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                 (9U)                           
+#define USB_OTG_HCINT_FRMOR_Msk                 (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                     USB_OTG_HCINT_FRMOR_Msk        /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                 (10U)                          
+#define USB_OTG_HCINT_DTERR_Msk                 (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                     USB_OTG_HCINT_DTERR_Msk        /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                (0U)                           
+#define USB_OTG_DIEPINT_XFRC_Msk                (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                    USB_OTG_DIEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos              (1U)                           
+#define USB_OTG_DIEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                  USB_OTG_DIEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                 (3U)                           
+#define USB_OTG_DIEPINT_TOC_Msk                 (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                     USB_OTG_DIEPINT_TOC_Msk        /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos              (4U)                           
+#define USB_OTG_DIEPINT_ITTXFE_Msk              (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                  USB_OTG_DIEPINT_ITTXFE_Msk     /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos              (6U)                           
+#define USB_OTG_DIEPINT_INEPNE_Msk              (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                  USB_OTG_DIEPINT_INEPNE_Msk     /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                (7U)                           
+#define USB_OTG_DIEPINT_TXFE_Msk                (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                    USB_OTG_DIEPINT_TXFE_Msk       /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos          (8U)                           
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk          (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                 (9U)                           
+#define USB_OTG_DIEPINT_BNA_Msk                 (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                     USB_OTG_DIEPINT_BNA_Msk        /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos           (11U)                          
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk           (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS               USB_OTG_DIEPINT_PKTDRPSTS_Msk  /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                (12U)                          
+#define USB_OTG_DIEPINT_BERR_Msk                (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                    USB_OTG_DIEPINT_BERR_Msk       /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                 (13U)                          
+#define USB_OTG_DIEPINT_NAK_Msk                 (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                     USB_OTG_DIEPINT_NAK_Msk        /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos              (0U)                           
+#define USB_OTG_HCINTMSK_XFRCM_Msk              (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                  USB_OTG_HCINTMSK_XFRCM_Msk     /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos               (1U)                           
+#define USB_OTG_HCINTMSK_CHHM_Msk               (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                   USB_OTG_HCINTMSK_CHHM_Msk      /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos             (2U)                           
+#define USB_OTG_HCINTMSK_AHBERR_Msk             (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                 USB_OTG_HCINTMSK_AHBERR_Msk    /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos             (3U)                           
+#define USB_OTG_HCINTMSK_STALLM_Msk             (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                 USB_OTG_HCINTMSK_STALLM_Msk    /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos               (4U)                           
+#define USB_OTG_HCINTMSK_NAKM_Msk               (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                   USB_OTG_HCINTMSK_NAKM_Msk      /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos               (5U)                           
+#define USB_OTG_HCINTMSK_ACKM_Msk               (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                   USB_OTG_HCINTMSK_ACKM_Msk      /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos               (6U)                           
+#define USB_OTG_HCINTMSK_NYET_Msk               (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                   USB_OTG_HCINTMSK_NYET_Msk      /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos             (7U)                           
+#define USB_OTG_HCINTMSK_TXERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                 USB_OTG_HCINTMSK_TXERRM_Msk    /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos             (8U)                           
+#define USB_OTG_HCINTMSK_BBERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                 USB_OTG_HCINTMSK_BBERRM_Msk    /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos             (9U)                           
+#define USB_OTG_HCINTMSK_FRMORM_Msk             (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                 USB_OTG_HCINTMSK_FRMORM_Msk    /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos             (10U)                          
+#define USB_OTG_HCINTMSK_DTERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                 USB_OTG_HCINTMSK_DTERRM_Msk    /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos             (0U)                           
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                 USB_OTG_DIEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos             (19U)                          
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                 USB_OTG_DIEPTSIZ_PKTCNT_Msk    /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos             (29U)                          
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk             (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                 USB_OTG_DIEPTSIZ_MULCNT_Msk    /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos               (0U)                           
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk               (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                   USB_OTG_HCTSIZ_XFRSIZ_Msk      /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos               (19U)                          
+#define USB_OTG_HCTSIZ_PKTCNT_Msk               (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                   USB_OTG_HCTSIZ_PKTCNT_Msk      /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos               (31U)                          
+#define USB_OTG_HCTSIZ_DOPING_Msk               (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                   USB_OTG_HCTSIZ_DOPING_Msk      /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                 (29U)                          
+#define USB_OTG_HCTSIZ_DPID_Msk                 (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                     USB_OTG_HCTSIZ_DPID_Msk        /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos             (0U)                           
+#define USB_OTG_DIEPDMA_DMAADDR_Msk             (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                 USB_OTG_DIEPDMA_DMAADDR_Msk    /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos               (0U)                           
+#define USB_OTG_HCDMA_DMAADDR_Msk               (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                   USB_OTG_HCDMA_DMAADDR_Msk      /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos           (0U)                           
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk           (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos            (0U)                           
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                USB_OTG_DIEPTXF_INEPTXSA_Msk   /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos            (16U)                          
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                USB_OTG_DIEPTXF_INEPTXFD_Msk   /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos               (0U)                           
+#define USB_OTG_DOEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos              (15U)                          
+#define USB_OTG_DOEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                  USB_OTG_DOEPCTL_USBAEP_Msk     /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos              (17U)                          
+#define USB_OTG_DOEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                  USB_OTG_DOEPCTL_NAKSTS_Msk     /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM          USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos             (29U)                          
+#define USB_OTG_DOEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                 USB_OTG_DOEPCTL_SODDFRM_Msk    /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos               (18U)                          
+#define USB_OTG_DOEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                   USB_OTG_DOEPCTL_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                (20U)                          
+#define USB_OTG_DOEPCTL_SNPM_Msk                (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                    USB_OTG_DOEPCTL_SNPM_Msk       /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos               (21U)                          
+#define USB_OTG_DOEPCTL_STALL_Msk               (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                   USB_OTG_DOEPCTL_STALL_Msk      /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                (26U)                          
+#define USB_OTG_DOEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                    USB_OTG_DOEPCTL_CNAK_Msk       /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                (27U)                          
+#define USB_OTG_DOEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                    USB_OTG_DOEPCTL_SNAK_Msk       /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos               (30U)                          
+#define USB_OTG_DOEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                   USB_OTG_DOEPCTL_EPDIS_Msk      /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos               (31U)                          
+#define USB_OTG_DOEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                   USB_OTG_DOEPCTL_EPENA_Msk      /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                (0U)                           
+#define USB_OTG_DOEPINT_XFRC_Msk                (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                    USB_OTG_DOEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos              (1U)                           
+#define USB_OTG_DOEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                  USB_OTG_DOEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                (3U)                           
+#define USB_OTG_DOEPINT_STUP_Msk                (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                    USB_OTG_DOEPINT_STUP_Msk       /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos             (4U)                           
+#define USB_OTG_DOEPINT_OTEPDIS_Msk             (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                 USB_OTG_DOEPINT_OTEPDIS_Msk    /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos             (6U)                           
+#define USB_OTG_DOEPINT_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                 USB_OTG_DOEPINT_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                (14U)                          
+#define USB_OTG_DOEPINT_NYET_Msk                (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                    USB_OTG_DOEPINT_NYET_Msk       /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos             (0U)                           
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                 USB_OTG_DOEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos             (19U)                          
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                 USB_OTG_DOEPTSIZ_PKTCNT_Msk    /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos            (29U)                          
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk            (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                USB_OTG_DOEPTSIZ_STUPCNT_Msk   /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0              (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1              (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos             (0U)                           
+#define USB_OTG_PCGCCTL_STOPCLK_Msk             (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                 USB_OTG_PCGCCTL_STOPCLK_Msk    /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos             (1U)                           
+#define USB_OTG_PCGCCTL_GATECLK_Msk             (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                 USB_OTG_PCGCCTL_GATECLK_Msk    /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos             (4U)                           
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk             (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 USB_OTG_PCGCCTL_PHYSUSP_Msk    /*!<Bit 1 */
+
+/* Legacy define */
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_CHNUM_Pos                       (0U)                           
+#define USB_OTG_CHNUM_Msk                       (0xFUL << USB_OTG_CHNUM_Pos)    /*!< 0x0000000F */
+#define USB_OTG_CHNUM                           USB_OTG_CHNUM_Msk              /*!< Channel number */
+#define USB_OTG_CHNUM_0                         (0x1UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                         (0x2UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                         (0x4UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                         (0x8UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                        (4U)                           
+#define USB_OTG_BCNT_Msk                        (0x7FFUL << USB_OTG_BCNT_Pos)   /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                            USB_OTG_BCNT_Msk               /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                        (15U)                          
+#define USB_OTG_DPID_Msk                        (0x3UL << USB_OTG_DPID_Pos)     /*!< 0x00018000 */
+#define USB_OTG_DPID                            USB_OTG_DPID_Msk               /*!< Data PID */
+#define USB_OTG_DPID_0                          (0x1UL << USB_OTG_DPID_Pos)     /*!< 0x00008000 */
+#define USB_OTG_DPID_1                          (0x2UL << USB_OTG_DPID_Pos)     /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                      (17U)                          
+#define USB_OTG_PKTSTS_Msk                      (0xFUL << USB_OTG_PKTSTS_Pos)   /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                          USB_OTG_PKTSTS_Msk             /*!< Packet status */
+#define USB_OTG_PKTSTS_0                        (0x1UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                        (0x2UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                        (0x4UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                        (0x8UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                       (0U)                           
+#define USB_OTG_EPNUM_Msk                       (0xFUL << USB_OTG_EPNUM_Pos)    /*!< 0x0000000F */
+#define USB_OTG_EPNUM                           USB_OTG_EPNUM_Msk              /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                         (0x1UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                         (0x2UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                         (0x4UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                         (0x8UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                      (21U)                          
+#define USB_OTG_FRMNUM_Msk                      (0xFUL << USB_OTG_FRMNUM_Pos)   /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                          USB_OTG_FRMNUM_Msk             /*!< Frame number */
+#define USB_OTG_FRMNUM_0                        (0x1UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                        (0x2UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                        (0x4UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                        (0x8UL << USB_OTG_FRMNUM_Pos)   /*!< 0x01000000 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a00f3489f..0240857d9 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -126,6 +126,9 @@
 // GigaDevice
 #define OPT_MCU_GD32VF103        1600 ///< GigaDevice GD32VF103
 
+// Broadcom
+#define OPT_MCU_BCM2711          1700 ///< Broadcom BCM2711
+
 //--------------------------------------------------------------------+
 // Supported OS
 //--------------------------------------------------------------------+

From ea595d3161b1e32c17a2df5c166f92c051b67409 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 18 Sep 2021 16:53:16 +0700
Subject: [PATCH 0483/2085] update dcd attr for mm32

---
 src/device/dcd_attr.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index a35fc0ac5..44f2cc1d6 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -63,6 +63,9 @@
 #elif TU_CHECK_MCU(MKL25ZXX) || TU_CHECK_MCU(K32L2BXX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
+#elif TU_CHECK_MCU(MM32F327X)
+  #define DCD_ATTR_ENDPOINT_MAX   16
+
 //------------- Nordic -------------//
 #elif TU_CHECK_MCU(NRF5X)
   // 8 CBI + 1 ISO

From 829f92d00f05167f788375a2a4e0ff5342bb30f7 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Wed, 22 Sep 2021 15:19:02 -0700
Subject: [PATCH 0484/2085] Trying to setup the mmu

---
 hw/bsp/raspberrypi4/family.c    | 24 +++++++-------
 hw/bsp/raspberrypi4/family.mk   |  3 +-
 hw/mcu/broadcom/bcm2711/boot.s  |  4 ++-
 hw/mcu/broadcom/bcm2711/link.ld | 16 ++++++---
 hw/mcu/broadcom/bcm2711/mmu.c   | 58 +++++++++++++++++++++++++++++++++
 hw/mcu/broadcom/bcm2711/mmu.h   | 44 +++++++++++++++++++++++++
 6 files changed, 132 insertions(+), 17 deletions(-)
 create mode 100644 hw/mcu/broadcom/bcm2711/mmu.c
 create mode 100644 hw/mcu/broadcom/bcm2711/mmu.h

diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c
index b2665f42d..6266d5a35 100644
--- a/hw/bsp/raspberrypi4/family.c
+++ b/hw/bsp/raspberrypi4/family.c
@@ -28,6 +28,7 @@
 #include "board.h"
 
 #include "io.h"
+#include "mmu.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
@@ -55,6 +56,7 @@ void board_init(void)
   gpio_initOutputPinWithPullNone(18);
   gpio_setPinOutputBool(18, true);
   gpio_initOutputPinWithPullNone(42);
+  setup_mmu_flat_map();
   // gpio_initOutputPinWithPullNone(23);
   // gpio_initOutputPinWithPullNone(24);
   // gpio_initOutputPinWithPullNone(25);
@@ -83,17 +85,17 @@ void board_init(void)
   // gpio_setPinOutputBool(25, true);
   print();
   // gpio_setPinOutputBool(25, false);
-  while (true) {
-  // for (size_t i = 0; i < 5; i++) {
-    for (size_t j = 0; j < 10000000000; j++) {
-      __asm__("nop");
-    }
-    gpio_setPinOutputBool(42, true);
-    for (size_t j = 0; j < 10000000000; j++) {
-      __asm__("nop");
-    }
-    gpio_setPinOutputBool(42, false);
-  }
+  // while (true) {
+  // // for (size_t i = 0; i < 5; i++) {
+  //   for (size_t j = 0; j < 10000000000; j++) {
+  //     __asm__("nop");
+  //   }
+  //   gpio_setPinOutputBool(42, true);
+  //   for (size_t j = 0; j < 10000000000; j++) {
+  //     __asm__("nop");
+  //   }
+  //   gpio_setPinOutputBool(42, false);
+  // }
   // while (1) uart_update();
 }
 
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
index 2d5c78d22..1547beee1 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -18,8 +18,9 @@ CFLAGS += \
 
 SRC_C += \
 	src/portable/broadcom/synopsys/dcd_synopsys.c \
+	$(MCU_DIR)/interrupts.c \
 	$(MCU_DIR)/io.c \
-	$(MCU_DIR)/interrupts.c
+	$(MCU_DIR)/mmu.c
 
 CROSS_COMPILE = aarch64-none-elf-
 
diff --git a/hw/mcu/broadcom/bcm2711/boot.s b/hw/mcu/broadcom/bcm2711/boot.s
index 076b3a76a..dcc588924 100644
--- a/hw/mcu/broadcom/bcm2711/boot.s
+++ b/hw/mcu/broadcom/bcm2711/boot.s
@@ -19,7 +19,7 @@ _start:
     adr    x0, vectors        // load VBAR_EL1 with virtual
     // msr    vbar_el3, x0        // vector table address
     msr    vbar_el1, x0        // vector table address
-    // msr    vbar_el2, x0        // vector table address
+    msr    vbar_el2, x0        // vector table address
     isb
 
     // Clean the BSS section
@@ -45,6 +45,8 @@ irq_entry
 mov x0, #\type
 mrs x1, esr_el1
 mrs x2, elr_el1
+mrs x3, esr_el2
+mrs x4, elr_el2
 b   err_hang
 .endm
 
diff --git a/hw/mcu/broadcom/bcm2711/link.ld b/hw/mcu/broadcom/bcm2711/link.ld
index 0d5ebe2ab..43c4e722f 100644
--- a/hw/mcu/broadcom/bcm2711/link.ld
+++ b/hw/mcu/broadcom/bcm2711/link.ld
@@ -1,12 +1,20 @@
 SECTIONS
 {
     . = 0x80000;     /* Kernel load address for AArch64 */
-    .text : { KEEP(*(.text.boot)) *(.text .text.* .gnu.linkonce.t*) }
-    .rodata : { *(.rodata .rodata.* .gnu.linkonce.r*) }
+    .text : {
+        KEEP(*(.text.boot))
+        *(.text .text.* .gnu.linkonce.t*)
+    }
+    .rodata : {
+        . = ALIGN(4096);
+        *(.rodata .rodata.* .gnu.linkonce.r*)
+    }
     PROVIDE(_data = .);
-    .data : { *(.data .data.* .gnu.linkonce.d*) }
+    .data : {
+        . = ALIGN(4096);
+        *(.data .data.* .gnu.linkonce.d*)
+    }
     .bss (NOLOAD) : {
-        . = ALIGN(16);
         __bss_start = .;
         *(.bss .bss.*)
         *(COMMON)
diff --git a/hw/mcu/broadcom/bcm2711/mmu.c b/hw/mcu/broadcom/bcm2711/mmu.c
new file mode 100644
index 000000000..3c20436e6
--- /dev/null
+++ b/hw/mcu/broadcom/bcm2711/mmu.c
@@ -0,0 +1,58 @@
+#include <stdbool.h>
+#include <stdint.h>
+
+
+#include "mmu.h"
+
+// Each entry is a gig.
+volatile uint64_t level_1_table[32] __attribute__((aligned(4096)));
+
+// Third gig has peripherals
+uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096)));
+
+void setup_mmu_flat_map(void) {
+    // Set the first gig to regular access.
+    level_1_table[0] = 0x0000000000000000 | 
+                       MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) |
+                       MM_DESCRIPTOR_BLOCK |
+                       MM_DESCRIPTOR_VALID;
+    level_1_table[2] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
+                       MM_DESCRIPTOR_TABLE |
+                       MM_DESCRIPTOR_VALID;
+    // Set peripherals to register access.
+    for (uint64_t i = 480; i < 512; i++) {
+        level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) |
+                                                    MM_DESCRIPTOR_EXECUTE_NEVER |
+                                                    MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) |
+                                                    MM_DESCRIPTOR_BLOCK |
+                                                    MM_DESCRIPTOR_VALID;
+    }
+    uint64_t mair = MAIR_VALUE;
+    uint64_t tcr = TCR_VALUE;
+    uint64_t ttbr0 = ((uint64_t) level_1_table) | MM_TTBR_CNP;
+    uint64_t sctlr = 0;
+    __asm__ volatile (
+        // Set MAIR
+        "MSR MAIR_EL2, %[mair]\n\t"
+        // Set TTBR0
+        "MSR TTBR0_EL2, %[ttbr0]\n\t"
+        // Set TCR
+        "MSR TCR_EL2, %[tcr]\n\t"
+        // The ISB forces these changes to be seen before the MMU is enabled.
+        "ISB\n\t"
+        // Read System Control Register configuration data
+        "MRS %[sctlr], SCTLR_EL2\n\t"
+        // Write System Control Register configuration data
+        "ORR %[sctlr], %[sctlr], #1\n\t"
+        // Set [M] bit and enable the MMU.
+        "MSR SCTLR_EL2, %[sctlr]\n\t"
+        // The ISB forces these changes to be seen by the next instruction
+        "ISB"
+        : /* No outputs. */
+        : [mair] "r" (mair),
+          [tcr] "r" (tcr),
+          [ttbr0] "r" (ttbr0),
+          [sctlr] "r" (sctlr)
+    );
+    while (true) {}
+}
diff --git a/hw/mcu/broadcom/bcm2711/mmu.h b/hw/mcu/broadcom/bcm2711/mmu.h
new file mode 100644
index 000000000..9f0a7db49
--- /dev/null
+++ b/hw/mcu/broadcom/bcm2711/mmu.h
@@ -0,0 +1,44 @@
+#pragma once
+
+
+// From: https://github.com/s-matyukevich/raspberry-pi-os/blob/master/docs/lesson06/rpi-os.md
+/*
+ * Memory region attributes:
+ *
+ *   n = AttrIndx[2:0]
+ *            n    MAIR
+ *   DEVICE_nGnRnE    000    00000000
+ *   NORMAL_NC        001    01000100
+ */
+#define MT_DEVICE_nGnRnE         0x0
+#define MT_NORMAL_NC            0x1
+#define MT_DEVICE_nGnRnE_FLAGS        0x00
+#define MT_NORMAL_NC_FLAGS          0x44
+#define MAIR_VALUE            (MT_DEVICE_nGnRnE_FLAGS << (8 * MT_DEVICE_nGnRnE)) | (MT_NORMAL_NC_FLAGS << (8 * MT_NORMAL_NC))
+
+
+#define TCR_T0SZ            (64 - 35) 
+#define TCR_PS              (0x01 << 16) // 36-bit physical address
+#define TCR_TG0_4K          (0 << 14)
+#define TCR_SH0_OUTER_SHAREABLE (0x2 << 12)
+#define TCR_VALUE           (TCR_T0SZ | TCR_PS | TCR_TG0_4K | TCR_SH0_OUTER_SHAREABLE)
+
+#define ENTRY_TYPE_TABLE_DESCRIPTOR 0x11
+#define ENTRY_TYPE_BLOCK_ENTRY 0x01
+#define ENTRY_TYPE_TABLE_ENTRY 0x11
+#define ENTRY_TYPE_INVALID 0x00
+
+#define MM_DESCRIPTOR_VALID (0x1)
+
+#define MM_DESCRIPTOR_BLOCK (0x0 << 1)
+#define MM_DESCRIPTOR_TABLE (0x1 << 1)
+
+// Block attributes
+#define MM_DESCRIPTOR_EXECUTE_NEVER (0x1ull << 54)
+#define MM_DESCRIPTOR_CONTIGUOUS    (0x1ull << 52)
+
+#define MM_DESCRIPTOR_MAIR_INDEX(index) (index << 2)
+
+#define MM_TTBR_CNP (0x1)
+
+void setup_mmu_flat_map(void);

From dd2a518881f975583ae0ae018c9479ab61392a7c Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 23 Sep 2021 11:51:41 +0200
Subject: [PATCH 0485/2085] da1469x_dk_pro: Fix button setup

Button on board has 1k resistor to ground when pressed.
When not pressed pin 6 is floating.

This forces MCU pull-up for this pin for correct behavior.
---
 hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
index 2b6931e4e..0441c000c 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
+++ b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
@@ -80,7 +80,7 @@ void board_init(void)
   hal_gpio_init_out(5, 0);
 
   // Button
-  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_NONE);
+  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_UP);
 
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);

From 417677aae40469594ba69b70a41d988522c5ec96 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 23 Sep 2021 12:32:17 +0200
Subject: [PATCH 0486/2085] da14695_dk_usb: Fix button configuration

Unlike da1469x_dk_pro, K1 pin (6) is connected to VCC when
active.
This adds required pull down and reverses active logic state.
---
 hw/bsp/da14695_dk_usb/da14695_dk_usb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
index bdb30e0e5..95fe70d01 100644
--- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
@@ -68,7 +68,7 @@ void board_init(void)
   hal_gpio_init_out(5, 0);
 
   // Button
-  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_NONE);
+  hal_gpio_init_in(BUTTON_PIN, HAL_GPIO_PULL_DOWN);
 
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
@@ -101,8 +101,8 @@ void board_led_write(bool state)
 
 uint32_t board_button_read(void)
 {
-  // button is active LOW
-  return hal_gpio_read(BUTTON_PIN) ^ 1;
+  // button is active HIGH
+  return hal_gpio_read(BUTTON_PIN);
 }
 
 int board_uart_read(uint8_t* buf, int len)

From c4277124499430ecfc6bed9cb2789144a3872b02 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 23 Sep 2021 13:36:28 +0200
Subject: [PATCH 0487/2085] dcd_da146xx: Handle only enabled interrupts

Not much of an improvement but handle only interrupts
that were enabled and are expected.
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 112cdb502..b7ef77c01 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -1037,7 +1037,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
 void dcd_int_handler(uint8_t rhport)
 {
-  uint32_t int_status = USB->USB_MAEV_REG;
+  uint32_t int_status = USB->USB_MAEV_REG & USB->USB_MAMSK_REG;
 
   (void)rhport;
 

From 428eedcd04bf6e84f15252df6aebd030942c0f01 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 23 Sep 2021 13:40:47 +0200
Subject: [PATCH 0488/2085] dcd_da146xx: Update bus handling

So far bus reset was handled (with some holes in it).
Sleep and remote wakeup were not really tested and did not work.

With this change:
- bus reset is reworked
- remote wakeup works
- bus signal sleep is handled
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 136 ++++++++++++++++------
 1 file changed, 99 insertions(+), 37 deletions(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index b7ef77c01..3b006de91 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -60,10 +60,17 @@
 
 #define EP_MAX            4
 
+// Node functional states
 #define NFSR_NODE_RESET         0
 #define NFSR_NODE_RESUME        1
 #define NFSR_NODE_OPERATIONAL   2
 #define NFSR_NODE_SUSPEND       3
+// Those two following states are added to allow going out of sleep mode
+// using frame interrupt.  On remove wakeup RESUME state must be kept for
+// at least 1ms. It is accomplished by using FRAME interrupt that goes
+// through those two fake states before entering OPERATIONAL state.
+#define NFSR_NODE_WAKING        (0x10 | (NFSR_NODE_RESUME))
+#define NFSR_NODE_WAKING2       (0x20 | (NFSR_NODE_RESUME))
 
 static TU_ATTR_ALIGNED(4) uint8_t _setup_packet[8];
 
@@ -218,7 +225,7 @@ static struct
 {
   bool vbus_present;
   bool init_called;
-  bool in_reset;
+  uint8_t nfsr;
   xfer_ctl_t xfer_status[EP_MAX][2];
   // Endpoints that use DMA, one for each direction
   uint8_t dma_ep[2];
@@ -260,6 +267,15 @@ static const tusb_desc_endpoint_t ep0IN_desc =
 
 #define XFER_CTL_BASE(_ep, _dir) &_dcd.xfer_status[_ep][_dir]
 
+static void set_nfsr(uint8_t val)
+{
+  _dcd.nfsr = val;
+  // Write only lower 2 bits to register, higher bits are used
+  // to count down till OPERATIONAL state can be entered when
+  // remote wakeup activated.
+  USB->USB_NFSR_REG = val & 3;
+}
+
 static void fill_tx_fifo(xfer_ctl_t * xfer)
 {
   int left_to_send;
@@ -628,60 +644,81 @@ static void handle_tx_ev(void)
     handle_epx_tx_ev(XFER_CTL_BASE(3, TUSB_DIR_IN));
 }
 
+static uint32_t check_reset_end(uint32_t alt_ev)
+{
+  if (_dcd.nfsr == NFSR_NODE_RESET)
+  {
+    if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESET))
+    {
+      // Could be still in reset, but since USB_M_RESET is disabled it can
+      // be also old reset state that was not cleared yet.
+      // If (after reading USB_ALTEV_REG register again) bit is cleared
+      // reset state just ended.
+      // Keep non-reset bits combined from two previous ALTEV read and
+      // one from the next line.
+      alt_ev = (alt_ev & ~USB_USB_ALTEV_REG_USB_RESET_Msk) | USB->USB_ALTEV_REG;
+    }
+    if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESET) == 0)
+    {
+      USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk |
+                            USB_USB_ALTEV_REG_USB_SD3_Msk;
+      set_nfsr(NFSR_NODE_OPERATIONAL);
+      dcd_edpt_open(0, &ep0OUT_desc);
+      dcd_edpt_open(0, &ep0IN_desc);
+    }
+  }
+  return alt_ev;
+}
+
 static void handle_bus_reset(void)
 {
+  uint32_t alt_ev;
+
   USB->USB_NFSR_REG = 0;
   USB->USB_FAR_REG = 0x80;
   USB->USB_ALTMSK_REG = 0;
   USB->USB_NFSR_REG = NFSR_NODE_RESET;
   USB->USB_TXMSK_REG = 0;
   USB->USB_RXMSK_REG = 0;
-  (void)USB->USB_ALTEV_REG;
-  _dcd.in_reset = true;
+  set_nfsr(NFSR_NODE_RESET);
 
   dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
   USB->USB_DMA_CTRL_REG = 0;
 
   USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk |
-#if USE_SOF
                        USB_USB_MAMSK_REG_USB_M_FRAME_Msk |
-#endif
                        USB_USB_MAMSK_REG_USB_M_WARN_Msk |
                        USB_USB_MAMSK_REG_USB_M_ALT_Msk;
-  USB->USB_NFSR_REG = NFSR_NODE_OPERATIONAL;
-  USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_SD3_Msk |
-                        USB_USB_ALTMSK_REG_USB_M_RESUME_Msk;
-  // There is no information about end of reset state
-  // USB_FRAME event will be used to enable reset detection again
-  REG_SET_BIT(USB_MAEV_REG, USB_FRAME);
-  dcd_edpt_open (0, &ep0OUT_desc);
-  dcd_edpt_open (0, &ep0IN_desc);
+  USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESUME_Msk;
+  alt_ev = USB->USB_ALTEV_REG;
+  check_reset_end(alt_ev);
 }
 
 static void handle_alt_ev(void)
 {
   uint32_t alt_ev = USB->USB_ALTEV_REG;
 
-  if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESET))
+  alt_ev = check_reset_end(alt_ev);
+  if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESET) && _dcd.nfsr != NFSR_NODE_RESET)
   {
     handle_bus_reset();
   }
-  else
+  else if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESUME))
   {
-    if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_RESUME))
+    if (USB->USB_NFSR_REG == NFSR_NODE_SUSPEND)
     {
-      USB->USB_NFSR_REG = NFSR_NODE_OPERATIONAL;
-      USB->USB_ALTMSK_REG &= ~USB_USB_ALTMSK_REG_USB_M_RESUME_Msk;
-      USB->USB_ALTMSK_REG |= USB_USB_ALTMSK_REG_USB_M_SD3_Msk;
+      set_nfsr(NFSR_NODE_OPERATIONAL);
+      USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk |
+                            USB_USB_ALTMSK_REG_USB_M_SD3_Msk;
       dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
     }
-    if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_SD3))
-    {
-      USB->USB_NFSR_REG = NFSR_NODE_SUSPEND;
-      USB->USB_ALTMSK_REG |= USB_USB_ALTMSK_REG_USB_M_RESUME_Msk;
-      USB->USB_ALTMSK_REG &= ~USB_USB_ALTMSK_REG_USB_M_SD3_Msk | USB_USB_ALTMSK_REG_USB_M_SD5_Msk;
-      dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
-    }
+  }
+  else if (GET_BIT(alt_ev, USB_USB_ALTEV_REG_USB_SD3))
+  {
+    set_nfsr(NFSR_NODE_SUSPEND);
+    USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk |
+                          USB_USB_ALTMSK_REG_USB_M_RESUME_Msk;
+    dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 }
 
@@ -773,6 +810,12 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void)rhport;
+  if (_dcd.nfsr == NFSR_NODE_SUSPEND)
+  {
+    // Enter fake state that will use FRAME interrupt to wait before going operational.
+    set_nfsr(NFSR_NODE_WAKING);
+    USB->USB_MAMSK_REG |= USB_USB_MAMSK_REG_USB_M_FRAME_Msk;
+  }
 }
 
 void dcd_connect(uint8_t rhport)
@@ -784,16 +827,16 @@ void dcd_connect(uint8_t rhport)
     USB->USB_MCTRL_REG = USB_USB_MCTRL_REG_USBEN_Msk;
     USB->USB_NFSR_REG = 0;
     USB->USB_FAR_REG = 0x80;
-    USB->USB_NFSR_REG = NFSR_NODE_RESET;
     USB->USB_TXMSK_REG = 0;
     USB->USB_RXMSK_REG = 0;
 
     USB->USB_MAMSK_REG = USB_USB_MAMSK_REG_USB_M_INTR_Msk |
                          USB_USB_MAMSK_REG_USB_M_ALT_Msk |
                          USB_USB_MAMSK_REG_USB_M_WARN_Msk;
-    USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk;
+    USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk |
+                          USB_USB_ALTEV_REG_USB_SD3_Msk;
 
-    REG_SET_BIT(USB_MCTRL_REG, USB_NAT);
+    USB->USB_MCTRL_REG = USB_USB_MCTRL_REG_USBEN_Msk | USB_USB_MCTRL_REG_USB_NAT_Msk;
 
     // Select chosen DMA to be triggered by USB.
     DMA->DMA_REQ_MUX_REG = (DMA->DMA_REQ_MUX_REG & ~DA146XX_DMA_USB_MUX_MASK) | DA146XX_DMA_USB_MUX;
@@ -1079,19 +1122,38 @@ void dcd_int_handler(uint8_t rhport)
 
   if (GET_BIT(int_status, USB_USB_MAEV_REG_USB_FRAME))
   {
-    if (_dcd.in_reset)
+    if (_dcd.nfsr == NFSR_NODE_RESET)
     {
-      // Enable reset detection
-      _dcd.in_reset = false;
-      (void)USB->USB_ALTEV_REG;
+      // During reset FRAME interrupt is enabled to periodically
+      // check when reset state ends.
+      // FRAME interrupt is generated every 1ms without host sending
+      // actual SOF.
+      check_reset_end(USB_USB_ALTEV_REG_USB_RESET_Msk);
     }
+    else if (_dcd.nfsr == NFSR_NODE_WAKING)
+    {
+      // No need to call set_nfsr, just set state
+      _dcd.nfsr = NFSR_NODE_WAKING2;
+    }
+    else if (_dcd.nfsr == NFSR_NODE_WAKING2)
+    {
+      // No need to call set_nfsr, just set state
+      _dcd.nfsr = NFSR_NODE_RESUME;
+    }
+    else if (_dcd.nfsr == NFSR_NODE_RESUME)
+    {
+      set_nfsr(NFSR_NODE_OPERATIONAL);
+    }
+    else
+    {
 #if USE_SOF
-    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+      dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
 #else
-    // SOF was used to re-enable reset detection
-    // No need to keep it enabled
-    USB->USB_MAMSK_REG &= ~USB_USB_MAMSK_REG_USB_M_FRAME_Msk;
+      // FRAME interrupt was used to re-enable reset detection or remote
+      // wakeup no need to keep it enabled when USE_SOF is off.
+      USB->USB_MAMSK_REG &= ~USB_USB_MAMSK_REG_USB_M_FRAME_Msk;
 #endif
+    }
   }
 
   if (GET_BIT(int_status, USB_USB_MAEV_REG_USB_TX_EV))

From f172c5ee13fe9eb00e7560c5f2ded34290b9e4f7 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 24 Sep 2021 09:12:52 +0200
Subject: [PATCH 0489/2085] dcd_da146xx: Remove registers pointer from
 xfer_ctl_t

Note: this commit does not change any logic.

xfer_ctl_t structure keeps all dynamic data connected with transfer.
It used to have pointer to register set that was constant and was there
for convenience only.
Removing register pointer from structure makes cleanup easier as whole
structure can be erased with memset like function.

In many cases functions were using local variable regs and xfer->regs which
were same, that could be confusing so this part is unified.

Few macros were added for easy conversion between epnum, xfer, and regs.
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 81 +++++++++++++----------
 1 file changed, 46 insertions(+), 35 deletions(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 112cdb502..b98a996ee 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -193,8 +193,14 @@ typedef struct
 #define REG_CLR_BIT(reg, field) USB->reg &= ~USB_ ## reg ## _ ## field ## _Msk
 #define REG_SET_VAL(reg, field, val) USB->reg = (USB->reg & ~USB_ ## reg ## _ ## field ## _Msk) | (val << USB_ ## reg ## _ ## field ## _Pos)
 
+static EPx_REGS * const ep_regs[EP_MAX] = {
+  EP_REGS(USB_EPC0_REG),
+  EP_REGS(USB_EPC1_REG),
+  EP_REGS(USB_EPC3_REG),
+  EP_REGS(USB_EPC5_REG),
+};
+
 typedef struct {
-  EPx_REGS * regs;
   uint8_t * buffer;
   // Total length of current transfer
   uint16_t total_len;
@@ -226,15 +232,15 @@ static struct
 {
   .vbus_present = false,
   .init_called = false,
-  .xfer_status =
-  {
-    { { .regs = EP_REGS(USB_EPC0_REG) }, { .regs = EP_REGS(USB_EPC0_REG) } },
-    { { .regs = EP_REGS(USB_EPC1_REG) }, { .regs = EP_REGS(USB_EPC1_REG) } },
-    { { .regs = EP_REGS(USB_EPC3_REG) }, { .regs = EP_REGS(USB_EPC3_REG) } },
-    { { .regs = EP_REGS(USB_EPC5_REG) }, { .regs = EP_REGS(USB_EPC5_REG) } },
-  }
 };
 
+// Converts xfer pointer to epnum (0,1,2,3) regardless of xfer direction
+#define XFER_EPNUM(xfer)      ((xfer - &_dcd.xfer_status[0][0]) >> 1)
+// Converts xfer pinter to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number)
+#define XFER_REGS(xfer)       ep_regs[XFER_EPNUM(xfer)]
+// Converts epnum (0,1,2,3) to EPx_REGS pointer
+#define EPNUM_REGS(epnum)     ep_regs[epnum]
+
 // Two endpoint 0 descriptor definition for unified dcd_edpt_open()
 static const tusb_desc_endpoint_t ep0OUT_desc =
 {
@@ -264,8 +270,8 @@ static void fill_tx_fifo(xfer_ctl_t * xfer)
 {
   int left_to_send;
   uint8_t const *src;
-  EPx_REGS *regs = xfer->regs;
   uint8_t const epnum = tu_edpt_number(xfer->ep_addr);
+  EPx_REGS *regs = EPNUM_REGS(epnum);
 
   src = &xfer->buffer[xfer->transferred];
   left_to_send = xfer->total_len - xfer->transferred;
@@ -293,7 +299,7 @@ static void fill_tx_fifo(xfer_ctl_t * xfer)
     }
     else
     {
-      xfer->regs->txc &= ~USB_USB_TXC1_REG_USB_TFWL_Msk;
+      regs->txc &= ~USB_USB_TXC1_REG_USB_TFWL_Msk;
       USB->USB_FWMSK_REG &= ~(1 << (epnum - 1 + USB_USB_FWMSK_REG_USB_M_TXWARN31_Pos));
       // Whole packet already in fifo, no need to refill it later.  Mark last.
       regs->txc |= USB_USB_TXC1_REG_USB_LAST_Msk;
@@ -334,30 +340,31 @@ static void start_rx_packet(xfer_ctl_t *xfer)
   uint8_t const epnum = tu_edpt_number(xfer->ep_addr);
   uint16_t remaining = xfer->total_len - xfer->transferred;
   uint16_t size = tu_min16(remaining, xfer->max_packet_size);
+  EPx_REGS *regs = XFER_REGS(xfer);
 
   xfer->last_packet_size = 0;
   if (xfer->max_packet_size > FIFO_SIZE && remaining > FIFO_SIZE)
   {
     if (try_allocate_dma(epnum, TUSB_DIR_OUT))
     {
-      start_rx_dma(&xfer->regs->rxd, xfer->buffer + xfer->transferred, size);
+      start_rx_dma(&regs->rxd, xfer->buffer + xfer->transferred, size);
     }
     else
     {
       // Other endpoint is using DMA in that direction, fall back to interrupts.
       // For endpoint size greater then FIFO size enable FIFO level warning interrupt
       // when FIFO has less then 17 bytes free.
-      xfer->regs->rxc |= USB_USB_RXC1_REG_USB_RFWL_Msk;
+      regs->rxc |= USB_USB_RXC1_REG_USB_RFWL_Msk;
       USB->USB_FWMSK_REG |= 1 << (epnum - 1 + USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos);
     }
   }
   else if (epnum != 0)
   {
     // If max_packet_size would fit in FIFO no need for FIFO level warning interrupt.
-    xfer->regs->rxc &= ~USB_USB_RXC1_REG_USB_RFWL_Msk;
+    regs->rxc &= ~USB_USB_RXC1_REG_USB_RFWL_Msk;
     USB->USB_FWMSK_REG &= ~(1 << (epnum - 1 + USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos));
   }
-  xfer->regs->rxc |= USB_USB_RXC1_REG_USB_RX_EN_Msk;
+  regs->rxc |= USB_USB_RXC1_REG_USB_RX_EN_Msk;
 }
 
 static void start_tx_dma(void *src, volatile void *dst, uint16_t size)
@@ -376,13 +383,13 @@ static void start_tx_packet(xfer_ctl_t *xfer)
   uint8_t const epnum = tu_edpt_number(xfer->ep_addr);
   uint16_t remaining = xfer->total_len - xfer->transferred;
   uint16_t size = tu_min16(remaining, xfer->max_packet_size);
-  EPx_REGS *regs = xfer->regs;
+  EPx_REGS *regs = EPNUM_REGS(epnum);
 
   xfer->last_packet_size = 0;
 
   regs->txc = USB_USB_TXC1_REG_USB_FLUSH_Msk;
   regs->txc = USB_USB_TXC1_REG_USB_IGN_ISOMSK_Msk;
-  if (xfer->data1) xfer->regs->txc |= USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk;
+  if (xfer->data1) regs->txc |= USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk;
 
   if (xfer->max_packet_size > FIFO_SIZE && remaining > FIFO_SIZE && try_allocate_dma(epnum, TUSB_DIR_IN))
   {
@@ -399,7 +406,7 @@ static void start_tx_packet(xfer_ctl_t *xfer)
 
 static void read_rx_fifo(xfer_ctl_t *xfer, uint16_t bytes_in_fifo)
 {
-  EPx_REGS *regs = xfer->regs;
+  EPx_REGS *regs = XFER_REGS(xfer);
   uint16_t remaining = xfer->total_len - xfer->transferred - xfer->last_packet_size;
   uint16_t receive_this_time = bytes_in_fifo;
 
@@ -469,7 +476,7 @@ static void handle_ep0_tx(void)
 {
   uint32_t txs0;
   xfer_ctl_t *xfer = XFER_CTL_BASE(0, TUSB_DIR_IN);
-  EPx_REGS *regs = xfer->regs;
+  EPx_REGS *regs = XFER_REGS(xfer);
 
   txs0 = regs->USB_TXS0_REG;
 
@@ -503,7 +510,7 @@ static void handle_epx_rx_ev(uint8_t ep)
   int fifo_bytes;
   xfer_ctl_t *xfer = XFER_CTL_BASE(ep, TUSB_DIR_OUT);
 
-  EPx_REGS *regs = xfer->regs;
+  EPx_REGS *regs = EPNUM_REGS(ep);
 
   do
   {
@@ -582,7 +589,7 @@ static void handle_epx_tx_ev(xfer_ctl_t *xfer)
 {
   uint8_t const epnum = tu_edpt_number(xfer->ep_addr);
   uint32_t txs;
-  EPx_REGS *regs = xfer->regs;
+  EPx_REGS *regs = EPNUM_REGS(epnum);
 
   txs = regs->txs;
 
@@ -843,6 +850,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
   xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  EPx_REGS *regs = EPNUM_REGS(epnum);
   uint8_t iso_mask = 0;
 
   TU_ASSERT(epnum < EP_MAX);
@@ -867,13 +875,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   {
     if (dir == TUSB_DIR_OUT)
     {
-      xfer->regs->epc_out = epnum | USB_USB_EPC1_REG_USB_EP_EN_Msk | iso_mask;
+      regs->epc_out = epnum | USB_USB_EPC1_REG_USB_EP_EN_Msk | iso_mask;
       USB->USB_RXMSK_REG |= 0x101 << (epnum - 1);
       REG_SET_BIT(USB_MAMSK_REG, USB_M_RX_EV);
     }
     else
     {
-      xfer->regs->epc_in = epnum | USB_USB_EPC1_REG_USB_EP_EN_Msk | iso_mask;
+      regs->epc_in = epnum | USB_USB_EPC1_REG_USB_EP_EN_Msk | iso_mask;
       USB->USB_TXMSK_REG |= 0x101 << (epnum - 1);
       REG_SET_BIT(USB_MAMSK_REG, USB_M_TX_EV);
     }
@@ -892,6 +900,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
+  EPx_REGS *regs = EPNUM_REGS(epnum);
   xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
 
   (void)rhport;
@@ -907,8 +916,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   {
     if (dir == TUSB_DIR_OUT)
     {
-      xfer->regs->rxc = USB_USB_RXC1_REG_USB_FLUSH_Msk;
-      xfer->regs->epc_out = 0;
+      regs->rxc = USB_USB_RXC1_REG_USB_FLUSH_Msk;
+      regs->epc_out = 0;
       USB->USB_RXMSK_REG &= ~(0x101 << (epnum - 1));
       // Release DMA if needed
       if (_dcd.dma_ep[TUSB_DIR_OUT] == epnum)
@@ -919,8 +928,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
     }
     else
     {
-      xfer->regs->txc = USB_USB_TXC1_REG_USB_FLUSH_Msk;
-      xfer->regs->epc_in = 0;
+      regs->txc = USB_USB_TXC1_REG_USB_FLUSH_Msk;
+      regs->epc_in = 0;
       USB->USB_TXMSK_REG &= ~(0x101 << (epnum - 1));
       // Release DMA if needed
       if (_dcd.dma_ep[TUSB_DIR_IN] == epnum)
@@ -965,6 +974,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   (void)rhport;
 
   xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  EPx_REGS *regs = EPNUM_REGS(epnum);
   xfer->stall = 1;
 
   if (epnum == 0)
@@ -973,11 +983,11 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
     REG_SET_BIT(USB_EPC0_REG, USB_STALL);
     if (dir == TUSB_DIR_OUT)
     {
-      xfer->regs->USB_RXC0_REG = USB_USB_RXC0_REG_USB_RX_EN_Msk;
+      regs->USB_RXC0_REG = USB_USB_RXC0_REG_USB_RX_EN_Msk;
     }
     else
     {
-      if (xfer->regs->USB_RXC0_REG & USB_USB_RXC0_REG_USB_RX_EN_Msk)
+      if (regs->USB_RXC0_REG & USB_USB_RXC0_REG_USB_RX_EN_Msk)
       {
         // If RX is also enabled TX will not be stalled since RX has
         // higher priority. Enable NAK interrupt to handle stall.
@@ -985,7 +995,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
       }
       else
       {
-        xfer->regs->USB_TXC0_REG |= USB_USB_TXC0_REG_USB_TX_EN_Msk;
+        regs->USB_TXC0_REG |= USB_USB_TXC0_REG_USB_TX_EN_Msk;
       }
     }
   }
@@ -993,13 +1003,13 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   {
     if (dir == TUSB_DIR_OUT)
     {
-      xfer->regs->epc_out |= USB_USB_EPC1_REG_USB_STALL_Msk;
-      xfer->regs->rxc |= USB_USB_RXC1_REG_USB_RX_EN_Msk;
+      regs->epc_out |= USB_USB_EPC1_REG_USB_STALL_Msk;
+      regs->rxc |= USB_USB_RXC1_REG_USB_RX_EN_Msk;
     }
     else
     {
-      xfer->regs->epc_in |= USB_USB_EPC1_REG_USB_STALL_Msk;
-      xfer->regs->txc |= USB_USB_TXC1_REG_USB_TX_EN_Msk | USB_USB_TXC1_REG_USB_LAST_Msk;
+      regs->epc_in |= USB_USB_EPC1_REG_USB_STALL_Msk;
+      regs->txc |= USB_USB_TXC1_REG_USB_TX_EN_Msk | USB_USB_TXC1_REG_USB_LAST_Msk;
     }
   }
 }
@@ -1012,6 +1022,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   (void)rhport;
 
   xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  EPx_REGS *regs = EPNUM_REGS(epnum);
 
   // Clear stall is called in response to Clear Feature ENDPOINT_HALT, reset toggle
   xfer->data1 = 0;
@@ -1019,11 +1030,11 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
   if (dir == TUSB_DIR_OUT)
   {
-    xfer->regs->epc_out &= ~USB_USB_EPC1_REG_USB_STALL_Msk;
+    regs->epc_out &= ~USB_USB_EPC1_REG_USB_STALL_Msk;
   }
   else
   {
-    xfer->regs->epc_in &= ~USB_USB_EPC1_REG_USB_STALL_Msk;
+    regs->epc_in &= ~USB_USB_EPC1_REG_USB_STALL_Msk;
   }
   if (epnum == 0)
   {

From 1503955860ba1b0797a07dfab15a9d424f105839 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 24 Sep 2021 09:15:18 +0200
Subject: [PATCH 0490/2085] dcd_da146xx: Clear transfer data on dcd_edpt_close

Closing endpoint clears data in affected xfer_ctl_t
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index b98a996ee..6eaba7098 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -939,6 +939,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
       }
     }
   }
+  tu_memclr(xfer, sizeof(*xfer));
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)

From fbac58e3e40a3741db96c258ac88ec5d19ee0251 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Mon, 20 Sep 2021 15:32:58 +0200
Subject: [PATCH 0491/2085] dcd_da146xx: Implement dcd_edpt_close_all()

Unconditionally disables all endpoints except EP0.
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 112cdb502..8c49d9a51 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -885,7 +885,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
-  // TODO implement dcd_edpt_close_all()
+
+  for (int epnum = 1; epnum < EP_MAX; ++epnum)
+  {
+    dcd_edpt_close(0, epnum | TUSB_DIR_OUT);
+    dcd_edpt_close(0, epnum | TUSB_DIR_IN);
+  }
 }
 
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)

From c62c1433e7d35ee18d97a7c76a4de91aa66a9486 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 23 Sep 2021 14:03:22 +0200
Subject: [PATCH 0492/2085] usbd: Workaround for non standard device descriptor
 request

Windows and Linux host during enumeration requests device
descriptor with request size set to 64 bytes when device
was in default state (no address).
Those systems do not want 64 bytes though since usb descriptors is
only 18 bytes long so they silently expect that only one packet
will be received possibly 18 bytes for EPS > 16 or 8 or 16 bytes
for smaller EP0.

For devices with CFG_TUD_ENDPOINT0_SIZE size 8 or 16 there was
workaround that reduced request size to CFG_TUD_ENDPOINT0_SIZE
and that was enough to satisfy Windows and Linux hosts.

However USBCV testing application also requests device descriptor
but with size set to 18 bytes. Workaround for Window/Linux
prevented USBVC to tests devices with 8 bytes EP0 size since it
send only 8 bytes while application did wanted 18 bytes.

Solution that satisfies both cases it to check if in default state device
descriptor request wants more bytes than descriptor size (18).
If so host is expecting to receive less bytes then requested
and workaround would be applied since Linux/Windows only try
to read one packet.
If 18 bytes was requested as is the case for USBCV, core returns
descriptor in 2 or 3 packets as application expects.
---
 src/device/usbd.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 3043fc7bc..cf3ecea42 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -971,9 +971,11 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
       uint16_t len = sizeof(tusb_desc_device_t);
 
-      // Only send up to EP0 Packet Size if not addressed
+      // Only send up to EP0 Packet Size if not addressed and host requested more data
+      // that device descriptor has.
       // This only happens with the very first get device descriptor and EP0 size = 8 or 16.
-      if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed)
+      if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed &&
+          ((tusb_control_request_t*) p_request)->wLength > sizeof(tusb_desc_device_t))
       {
         len = CFG_TUD_ENDPOINT0_SIZE;
 

From 0a6ca65e3f8a113c182c7df0a05889b123ba67a2 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Fri, 24 Sep 2021 16:14:01 -0700
Subject: [PATCH 0493/2085] MMU works

---
 cortex-a.py                                   | 157 ++++++++++++++++++
 hw/mcu/broadcom/bcm2711/io.c                  |   2 +
 hw/mcu/broadcom/bcm2711/mmu.c                 |  12 +-
 hw/mcu/broadcom/bcm2711/mmu.h                 |   5 +-
 src/portable/broadcom/synopsys/dcd_synopsys.c |   8 +-
 5 files changed, 177 insertions(+), 7 deletions(-)
 create mode 100644 cortex-a.py

diff --git a/cortex-a.py b/cortex-a.py
new file mode 100644
index 000000000..9de16bae9
--- /dev/null
+++ b/cortex-a.py
@@ -0,0 +1,157 @@
+class Armv8AException(gdb.Command):
+    def __init__ (self):
+        super (Armv8AException, self).__init__ ("armv8a-exception", gdb.COMMAND_USER)
+    
+    def print_data_abort(self, frame, iss):
+        isv = (iss >> 23) & 0x1
+        sas = (iss >> 21) & 0x3
+        sse = (iss >> 20) & 0x1
+        srt = (iss >> 15) & 0x1f
+        sf = (iss >> 14) & 0x1
+        ar = (iss >> 13) & 0x1
+        vncr = (iss >> 12) & 0x1
+        _set = (iss >> 10) & 0x3
+        fnv = (iss >> 9) & 0x1
+        ea = (iss >> 8) & 0x1
+        cm = (iss >> 7) & 0x1
+        s1ptw = (iss >> 6) & 0x1
+        wnr = (iss >> 5) & 0x1
+        dfsc = iss & 0x1f
+        if isv:
+            # print("isv valid", sas, sse, srt, sf, ar)
+            access_sizes = ("Byte", "Halfword", "Word", "Doubleword")
+            print("Access size:", access_sizes[sas])
+            print("Sign extended:", "Yes" if sse else "No")
+            print("Register:", hex(srt), "64-bit" if sf else "32-bit")
+            print("Acquire/Release:", "Yes" if ar else "No")
+        if dfsc == 0b010000:
+            print("Not on translation table walk")
+            if not fnv:
+                value = int(frame.read_register("FAR_EL2"))
+                print("FAR", hex(value))
+        elif dfsc == 0b000101:
+            print("translation fault level 1")
+        elif dfsc == 0b010001:
+            print("tag check fault")
+        elif dfsc == 0b100001:
+            print("alignment fault")
+        else:
+            print(bin(dfsc))
+        print(vncr, _set, fnv, ea, cm, s1ptw, wnr, dfsc)
+
+    def print_instruction_abort(self, frame, iss):
+        _set = (iss >> 10) & 0x3
+        fnv = (iss >> 9) & 0x1
+        ea = (iss >> 8) & 0x1
+        s1ptw = (iss >> 6) & 0x1
+        ifsc = iss & 0x1f
+        if ifsc == 0b010000:
+            print("Not on translation table walk")
+            if not fnv:
+                value = int(frame.read_register("FAR_EL2"))
+                print("FAR", hex(value))
+        elif ifsc == 0b00101:
+            print("translation fault level 1")
+        elif ifsc == 0b01001:
+            print("access flag fault level 1")
+        # elif dfsc == 0b100001:
+        #     print("alignment fault")
+        else:
+            print(bin(ifsc))
+
+    def invoke (self, arg, from_tty):
+        frame = gdb.selected_frame()
+        value = int(frame.read_register("ESR_EL2"))
+        if value == 0:
+            return None
+        iss2 = (value >> 32) & 0x1ff
+        ec = (value >> 26) & 0x3ff
+        il = (value >> 25) & 0x1
+        iss = value & 0xffffff
+        if ec == 0b000000:
+            print("Unknown fault")
+        elif ec == 0b000001:
+            print("Trapped WF*")
+        elif ec == 0b000011:
+            print("Trapped MCR or MRC")
+        elif ec == 0b000100:
+            print("Trapped MCRR or MRRC")
+        elif ec == 0b000101:
+            print("Trapped MCR or MRC")
+        elif ec == 0b000110:
+            print("Trapped LDC or STC")
+        elif ec == 0b000111:
+            print("Trapped SIMD")
+        elif ec == 0b001000:
+            print("Trapped VMRS")
+        elif ec == 0b001001:
+            print("Trapped pointer authentication")
+        elif ec == 0b001010:
+            print("Trapped LD64B or ST64B*")
+        elif ec == 0b001100:
+            print("Trapped MRRC")
+        elif ec == 0b001101:
+            print("Branch target exception")
+        elif ec == 0b001110:
+            print("Illegal execution state")
+        elif ec == 0b010001:
+            print("SVC instruction")
+        elif ec == 0b010010:
+            print("HVC instruction")
+        elif ec == 0b010011:
+            print("SMC instruction")
+        elif ec == 0b010101:
+            print("SVC instruction")
+        elif ec == 0b010110:
+            print("HVC instruction")
+        elif ec == 0b010111:
+            print("SMC instruction")
+        elif ec == 0b011000:
+            print("Trapped MRS, MRS or system instruction")
+        elif ec == 0b011001:
+            print("Trapped SVE")
+        elif ec == 0b011010:
+            print("Trapped ERET")
+        elif ec == 0b011100:
+            print("Failed pointer authentication")
+        elif ec == 0b100000:
+            print("Instruction abort from lower level")
+        elif ec == 0b100001:
+            print("Instruction abort from same level")
+            self.print_instruction_abort(frame, iss)
+        elif ec == 0b100010:
+            print("PC alignment failure")
+        elif ec == 0b100100:
+            print("Data abort from lower level")
+        elif ec == 0b100101:
+            print("Data abort from same level")
+            self.print_data_abort(frame, iss)
+        elif ec == 0b100110:
+            print("SP alignment fault")
+        elif ec == 0b101000:
+            print("32-bit floating point exception")
+        elif ec == 0b101100:
+            print("64-bit floating point exception")
+        elif ec == 0b101111:
+            print("SError interrupt")
+        elif ec == 0b110000:
+            print("Breakpoint from lower level")
+        elif ec == 0b110001:
+            print("Breakpoint from same level")
+        elif ec == 0b110010:
+            print("Software step from lower level")
+        elif ec == 0b110011:
+            print("Software step from same level")
+        elif ec == 0b110100:
+            print ("Watch point from same level")
+        elif ec == 0b110101:
+            print("Watch point from lower level")
+        elif ec == 0b111000:
+            print("Breakpoint in aarch32 mode")
+        elif ec == 0b111010:
+            print("Vector catch in aarch32")
+        elif ec == 0b111100:
+            print("Brk instruction in aarch64")
+        print(hex(int(value)), iss2, bin(ec), il, iss)
+
+Armv8AException()
diff --git a/hw/mcu/broadcom/bcm2711/io.c b/hw/mcu/broadcom/bcm2711/io.c
index 213d6f2fb..8ccfdc692 100644
--- a/hw/mcu/broadcom/bcm2711/io.c
+++ b/hw/mcu/broadcom/bcm2711/io.c
@@ -3,6 +3,8 @@
 
 // GPIO
 
+// Pi 4 base address: 0xFE000000
+// Pi 3 base address: 0x3F000000
 enum {
     PERIPHERAL_BASE = 0xFE000000,
     GPFSEL0         = PERIPHERAL_BASE + 0x200000,
diff --git a/hw/mcu/broadcom/bcm2711/mmu.c b/hw/mcu/broadcom/bcm2711/mmu.c
index 3c20436e6..e5ae236bd 100644
--- a/hw/mcu/broadcom/bcm2711/mmu.c
+++ b/hw/mcu/broadcom/bcm2711/mmu.c
@@ -5,7 +5,7 @@
 #include "mmu.h"
 
 // Each entry is a gig.
-volatile uint64_t level_1_table[32] __attribute__((aligned(4096)));
+volatile uint64_t level_1_table[512] __attribute__((aligned(4096)));
 
 // Third gig has peripherals
 uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096)));
@@ -14,9 +14,10 @@ void setup_mmu_flat_map(void) {
     // Set the first gig to regular access.
     level_1_table[0] = 0x0000000000000000 | 
                        MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) |
+                       MM_DESCRIPTOR_ACCESS_FLAG |
                        MM_DESCRIPTOR_BLOCK |
                        MM_DESCRIPTOR_VALID;
-    level_1_table[2] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
+    level_1_table[3] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
                        MM_DESCRIPTOR_TABLE |
                        MM_DESCRIPTOR_VALID;
     // Set peripherals to register access.
@@ -24,6 +25,7 @@ void setup_mmu_flat_map(void) {
         level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) |
                                                     MM_DESCRIPTOR_EXECUTE_NEVER |
                                                     MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) |
+                                                    MM_DESCRIPTOR_ACCESS_FLAG |
                                                     MM_DESCRIPTOR_BLOCK |
                                                     MM_DESCRIPTOR_VALID;
     }
@@ -47,12 +49,14 @@ void setup_mmu_flat_map(void) {
         // Set [M] bit and enable the MMU.
         "MSR SCTLR_EL2, %[sctlr]\n\t"
         // The ISB forces these changes to be seen by the next instruction
-        "ISB"
+        "ISB\n\t"
+        // "AT S1EL2R %[ttbr0]"
         : /* No outputs. */
         : [mair] "r" (mair),
           [tcr] "r" (tcr),
           [ttbr0] "r" (ttbr0),
           [sctlr] "r" (sctlr)
     );
-    while (true) {}
+    //__asm__ ("brk #123");
+    //while (true) {}
 }
diff --git a/hw/mcu/broadcom/bcm2711/mmu.h b/hw/mcu/broadcom/bcm2711/mmu.h
index 9f0a7db49..1fe081f34 100644
--- a/hw/mcu/broadcom/bcm2711/mmu.h
+++ b/hw/mcu/broadcom/bcm2711/mmu.h
@@ -13,11 +13,11 @@
 #define MT_DEVICE_nGnRnE         0x0
 #define MT_NORMAL_NC            0x1
 #define MT_DEVICE_nGnRnE_FLAGS        0x00
-#define MT_NORMAL_NC_FLAGS          0x44
+#define MT_NORMAL_NC_FLAGS          0xff
 #define MAIR_VALUE            (MT_DEVICE_nGnRnE_FLAGS << (8 * MT_DEVICE_nGnRnE)) | (MT_NORMAL_NC_FLAGS << (8 * MT_NORMAL_NC))
 
 
-#define TCR_T0SZ            (64 - 35) 
+#define TCR_T0SZ            (64 - 36) 
 #define TCR_PS              (0x01 << 16) // 36-bit physical address
 #define TCR_TG0_4K          (0 << 14)
 #define TCR_SH0_OUTER_SHAREABLE (0x2 << 12)
@@ -36,6 +36,7 @@
 // Block attributes
 #define MM_DESCRIPTOR_EXECUTE_NEVER (0x1ull << 54)
 #define MM_DESCRIPTOR_CONTIGUOUS    (0x1ull << 52)
+#define MM_DESCRIPTOR_ACCESS_FLAG   (0x1ull << 10)
 
 #define MM_DESCRIPTOR_MAIR_INDEX(index) (index << 2)
 
diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c
index 5967565a5..aecae503c 100644
--- a/src/portable/broadcom/synopsys/dcd_synopsys.c
+++ b/src/portable/broadcom/synopsys/dcd_synopsys.c
@@ -114,7 +114,7 @@
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#define RHPORT_REGS_BASE 0x7e980000
+#define RHPORT_REGS_BASE 0xfe980000
 
 #define GLOBAL_BASE(_port)     ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE)
 #define DEVICE_BASE(_port)     (USB_OTG_DeviceTypeDef *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE)
@@ -438,6 +438,7 @@ void dcd_init (uint8_t rhport)
 {
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
+  TU_LOG(2, "    dcd_init");
 
   USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
 
@@ -477,9 +478,14 @@ void dcd_init (uint8_t rhport)
   // Reset core after selecting PHY
   // Wait AHB IDLE, reset then wait until it is cleared
   while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
+
+  TU_LOG(2, "    resetting");
   usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+  TU_LOG(2, "    waiting");
   while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
 
+  TU_LOG(2, "    reset done");
+
   // Restart PHY clock
   *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
 

From 73872a5df04a8939d5f71509788c659e38efcecd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 25 Sep 2021 16:16:55 +0700
Subject: [PATCH 0494/2085] add CFG_TUSB_OS_INC_PATH for os include path

useful for freertos/ prefix with esp IDF
---
 examples/device/cdc_msc_freertos/Makefile       |  8 +++++++-
 .../device/cdc_msc_freertos/src/CMakeLists.txt  |  2 --
 .../src/{ => FreeRTOSConfig}/FreeRTOSConfig.h   |  4 ++++
 examples/device/cdc_msc_freertos/src/main.c     | 16 +++++++++-------
 .../device/cdc_msc_freertos/src/tusb_config.h   |  5 +++++
 examples/device/hid_boot_interface/Makefile     |  2 +-
 examples/device/hid_composite_freertos/Makefile |  7 ++++++-
 .../hid_composite_freertos/src/CMakeLists.txt   |  2 --
 .../src/{ => FreeRTOSConfig}/FreeRTOSConfig.h   |  4 ++++
 .../device/hid_composite_freertos/src/main.c    | 17 +++++++++--------
 .../hid_composite_freertos/src/tusb_config.h    |  6 ++++++
 hw/bsp/esp32s2/boards/CMakeLists.txt            |  2 --
 src/common/tusb_compiler.h                      |  3 +++
 src/osal/osal_freertos.h                        |  8 ++++----
 src/tusb_option.h                               |  6 ++++++
 15 files changed, 64 insertions(+), 28 deletions(-)
 rename examples/device/cdc_msc_freertos/src/{ => FreeRTOSConfig}/FreeRTOSConfig.h (98%)
 rename examples/device/hid_composite_freertos/src/{ => FreeRTOSConfig}/FreeRTOSConfig.h (98%)

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 86bacd2d4..677dcac9c 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -7,12 +7,18 @@ FREERTOS_SRC = lib/FreeRTOS-Kernel
 
 INC += \
 	src \
+	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
 	$(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)
 	
 # Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
+EXAMPLE_SOURCE = \
+	src/freertos_hook.c \
+	src/main.c \
+	src/msc_disk.c \
+	src/usb_descriptors.c
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 # FreeRTOS source, all files in port folder
diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index 6b188fd30..c0a665fa0 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -8,9 +8,7 @@ if(EXISTS ${board_cmake})
     include(${board_cmake})
 endif()
 
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
 target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${FREERTOS_ORIG_INCLUDE_PATH}"
   "${TOP}/hw"
   "${TOP}/src"
 )
diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
similarity index 98%
rename from examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
rename to examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 568b27a18..85d86b329 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -45,6 +45,10 @@
 // Include MCU header
 #include "bsp/board_mcu.h"
 
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+#error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
+#endif
+
 extern uint32_t SystemCoreClock;
 
 /* Cortex M23/M33 port configuration. */
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index c27b7feda..af00b3cc2 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -27,15 +27,17 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "FreeRTOS.h"
-#include "task.h"
-#include "timers.h"
-#include "queue.h"
-#include "semphr.h"
-
 #include "bsp/board.h"
 #include "tusb.h"
 
+// FreeRTOS headers, MCUs such as esp32sx requires "freertos/" prefix in include path.
+// CFG_TUSB_OS_INC_PATH should be defined accordingly.
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,timers.h)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
@@ -95,7 +97,7 @@ int main(void)
   (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if CFG_TUSB_MCU != OPT_MCU_ESP32S2 && CFG_TUSB_MCU != OPT_MCU_ESP32S3
+#if !( TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) )
   vTaskStartScheduler();
 #endif
 
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index ff5438349..d4bbdee48 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -67,6 +67,11 @@
 // This examples use FreeRTOS
 #define CFG_TUSB_OS               OPT_OS_FREERTOS
 
+// Espressif IDF requires "freertos/" prefix in include path
+#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+  #define CFG_TUSB_OS_INC_PATH    freertos/
+#endif
+
 // can be defined by compiler in DEBUG build
 #ifndef CFG_TUSB_DEBUG
   #define CFG_TUSB_DEBUG           0
diff --git a/examples/device/hid_boot_interface/Makefile b/examples/device/hid_boot_interface/Makefile
index 138c27846..c6a9c5b21 100644
--- a/examples/device/hid_boot_interface/Makefile
+++ b/examples/device/hid_boot_interface/Makefile
@@ -6,7 +6,7 @@ INC += \
 	$(TOP)/hw \
 
 # Example source
-EXAMPLE_SOURCE += \
+EXAMPLE_SOURCE = \
 	src/main.c \
 	src/usb_descriptors.c
 	
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index 1c1959590..256db3d8c 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -7,12 +7,17 @@ FREERTOS_SRC = lib/FreeRTOS-Kernel
 
 INC += \
 	src \
+	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
 	$(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)	
 
 # Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
+EXAMPLE_SOURCE = \
+	src/freertos_hook.c \
+	src/main.c \
+	src/usb_descriptors.c
+	
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 # FreeRTOS source, all files in port folder
diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt
index 6d4a3c1e2..a2a4fc9b1 100644
--- a/examples/device/hid_composite_freertos/src/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt
@@ -8,9 +8,7 @@ if(EXISTS ${board_cmake})
     include(${board_cmake})
 endif()
 
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
 target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${FREERTOS_ORIG_INCLUDE_PATH}"
   "${TOP}/hw"
   "${TOP}/src"
 )
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
similarity index 98%
rename from examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
rename to examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 568b27a18..85d86b329 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -45,6 +45,10 @@
 // Include MCU header
 #include "bsp/board_mcu.h"
 
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+#error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
+#endif
+
 extern uint32_t SystemCoreClock;
 
 /* Cortex M23/M33 port configuration. */
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 9c9830e34..8a184f60f 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -27,17 +27,18 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "FreeRTOS.h"
-#include "task.h"
-#include "timers.h"
-#include "queue.h"
-#include "semphr.h"
-
 #include "bsp/board.h"
 #include "tusb.h"
-
 #include "usb_descriptors.h"
 
+// FreeRTOS headers, MCUs such as esp32sx requires "freertos/" prefix in include path.
+// CFG_TUSB_OS_INC_PATH should be defined accordingly.
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,timers.h)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
@@ -96,7 +97,7 @@ int main(void)
   (void) xTaskCreateStatic( hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if CFG_TUSB_MCU != OPT_MCU_ESP32S2 && CFG_TUSB_MCU != OPT_MCU_ESP32S3
+#if !( TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) )
   vTaskStartScheduler();
 #endif
 
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index 4fbccc294..b061dce3f 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -67,6 +67,12 @@
 // This examples use FreeRTOS
 #define CFG_TUSB_OS               OPT_OS_FREERTOS
 
+// Espressif IDF requires "freertos/" prefix in include path
+#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+  #define CFG_TUSB_OS_INC_PATH    freertos/
+#endif
+
+
 #ifndef CFG_TUSB_DEBUG
 #define CFG_TUSB_DEBUG           0
 #endif
diff --git a/hw/bsp/esp32s2/boards/CMakeLists.txt b/hw/bsp/esp32s2/boards/CMakeLists.txt
index 71753012b..c3c687a70 100644
--- a/hw/bsp/esp32s2/boards/CMakeLists.txt
+++ b/hw/bsp/esp32s2/boards/CMakeLists.txt
@@ -6,9 +6,7 @@ idf_component_register(SRCS esp32s2.c
 # Apply board specific content
 include("${BOARD}/board.cmake")
 
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
 target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${FREERTOS_ORIG_INCLUDE_PATH}"
   "${TOP}/hw"
   "${TOP}/src"  
 )
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index d3adbbc2d..3e85939b0 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -32,6 +32,7 @@
 #ifndef _TUSB_COMPILER_H_
 #define _TUSB_COMPILER_H_
 
+#define TU_TOKEN(x)           x
 #define TU_STRING(x)          #x                  ///< stringify without expand
 #define TU_XSTRING(x)         TU_STRING(x)        ///< expand then stringify
 
@@ -41,6 +42,8 @@
 #define TU_XSTRCAT(a, b)      TU_STRCAT(a, b)     ///< expand then concat
 #define TU_XSTRCAT3(a, b, c)  TU_STRCAT3(a, b, c) ///< expand then concat 3 tokens
 
+#define TU_INCLUDE_PATH(_dir,_file) TU_XSTRING( TU_TOKEN(_dir)TU_TOKEN(_file) )
+
 #if defined __COUNTER__ && __COUNTER__ != __COUNTER__
   #define _TU_COUNTER_ __COUNTER__
 #else
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 66070c273..4573e01f5 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -28,10 +28,10 @@
 #define _TUSB_OSAL_FREERTOS_H_
 
 // FreeRTOS Headers
-#include "FreeRTOS.h"
-#include "semphr.h"
-#include "queue.h"
-#include "task.h"
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h)
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a00f3489f..ad2a26a66 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -203,14 +203,20 @@
   #define CFG_TUSB_MEM_SECTION
 #endif
 
+// alignment requirement of buffer used for endpoint transferring
 #ifndef CFG_TUSB_MEM_ALIGN
   #define CFG_TUSB_MEM_ALIGN      TU_ATTR_ALIGNED(4)
 #endif
 
+// OS selection
 #ifndef CFG_TUSB_OS
   #define CFG_TUSB_OS             OPT_OS_NONE
 #endif
 
+#ifndef CFG_TUSB_OS_INC_PATH
+  #define CFG_TUSB_OS_INC_PATH
+#endif
+
 //--------------------------------------------------------------------
 // DEVICE OPTIONS
 //--------------------------------------------------------------------

From 03d7988df3f491515389751a8cf4baecafb155fc Mon Sep 17 00:00:00 2001
From: Peter Lawrence <12226419+majbthrd@users.noreply.github.com>
Date: Tue, 3 Aug 2021 11:28:44 -0500
Subject: [PATCH 0495/2085] add NCM driver in a compatible manner :
 hathach/tinyusb#550

---
 .../cdc_msc_freertos/src/CMakeLists.txt       |   3 +-
 .../hid_composite_freertos/src/CMakeLists.txt |   3 +-
 examples/device/net_lwip_webserver/src/main.c |   2 +-
 .../net_lwip_webserver/src/tusb_config.h      |   1 +
 .../net_lwip_webserver/src/usb_descriptors.c  |  20 +
 examples/rules.mk                             |   3 +-
 hw/bsp/rp2040/family.cmake                    |   3 +-
 src/class/cdc/cdc.h                           |   6 +-
 .../net/{net_device.c => ecmrndis_device.c}   |   8 +-
 src/class/net/ncm_device.c                    | 500 ++++++++++++++++++
 src/class/net/net_device.h                    |  21 +-
 src/device/usbd.h                             |  31 ++
 src/tusb_option.h                             |   4 +
 13 files changed, 595 insertions(+), 10 deletions(-)
 rename src/class/net/{net_device.c => ecmrndis_device.c} (98%)
 create mode 100644 src/class/net/ncm_device.c

diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index c0a665fa0..f1c1e8c5d 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -23,7 +23,8 @@ target_sources(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src/class/hid/hid_device.c"
   "${TOP}/src/class/midi/midi_device.c"
   "${TOP}/src/class/msc/msc_device.c"
-  "${TOP}/src/class/net/net_device.c"
+  "${TOP}/src/class/net/ecmrndis_device.c"
+  "${TOP}/src/class/net/ncm_device.c"
   "${TOP}/src/class/usbtmc/usbtmc_device.c"
   "${TOP}/src/class/vendor/vendor_device.c"
   "${TOP}/src/portable/espressif/esp32sx/dcd_esp32sx.c"
diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt
index a2a4fc9b1..70df447dd 100644
--- a/examples/device/hid_composite_freertos/src/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt
@@ -23,7 +23,8 @@ target_sources(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src/class/hid/hid_device.c"
   "${TOP}/src/class/midi/midi_device.c"
   "${TOP}/src/class/msc/msc_device.c"
-  "${TOP}/src/class/net/net_device.c"
+  "${TOP}/src/class/net/ecmrndis_device.c"
+  "${TOP}/src/class/net/ncm_device.c"
   "${TOP}/src/class/usbtmc/usbtmc_device.c"
   "${TOP}/src/class/vendor/vendor_device.c"
   "${TOP}/src/portable/espressif/esp32sx/dcd_esp32sx.c"
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 80831921a..a5bd2153a 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -97,7 +97,7 @@ static err_t linkoutput_fn(struct netif *netif, struct pbuf *p)
       return ERR_USE;
 
     /* if the network driver can accept another packet, we make it happen */
-    if (tud_network_can_xmit())
+    if (tud_network_can_xmit(p->tot_len))
     {
       tud_network_xmit(p, 0 /* unused for this example */);
       return ERR_OK;
diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h
index 262d4ebce..457918cac 100644
--- a/examples/device/net_lwip_webserver/src/tusb_config.h
+++ b/examples/device/net_lwip_webserver/src/tusb_config.h
@@ -101,6 +101,7 @@
 #define CFG_TUD_MIDI              0
 #define CFG_TUD_VENDOR            0
 #define CFG_TUD_NET               1
+#define CFG_TUD_NCM               0
 
 #ifdef __cplusplus
  }
diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c
index 71e6c4582..d9618a3dc 100644
--- a/examples/device/net_lwip_webserver/src/usb_descriptors.c
+++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c
@@ -55,8 +55,12 @@ enum
 
 enum
 {
+#if !CFG_TUD_NCM
   CONFIG_ID_RNDIS = 0,
   CONFIG_ID_ECM   = 1,
+#else
+  CONFIG_ID_NCM   = 0,
+#endif
   CONFIG_ID_COUNT
 };
 
@@ -99,6 +103,7 @@ uint8_t const * tud_descriptor_device_cb(void)
 //--------------------------------------------------------------------+
 #define MAIN_CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_RNDIS_DESC_LEN)
 #define ALT_CONFIG_TOTAL_LEN     (TUD_CONFIG_DESC_LEN + TUD_CDC_ECM_DESC_LEN)
+#define NCM_CONFIG_TOTAL_LEN     (TUD_CONFIG_DESC_LEN + TUD_CDC_NCM_DESC_LEN)
 
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
@@ -120,6 +125,7 @@ uint8_t const * tud_descriptor_device_cb(void)
   #define EPNUM_NET_IN      0x82
 #endif
 
+#if !CFG_TUD_NCM
 static uint8_t const rndis_configuration[] =
 {
   // Config number (index+1), interface count, string index, total length, attribute, power in mA
@@ -137,6 +143,16 @@ static uint8_t const ecm_configuration[] =
   // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size.
   TUD_CDC_ECM_DESCRIPTOR(ITF_NUM_CDC, STRID_INTERFACE, STRID_MAC, EPNUM_NET_NOTIF, 64, EPNUM_NET_OUT, EPNUM_NET_IN, CFG_TUD_NET_ENDPOINT_SIZE, CFG_TUD_NET_MTU),
 };
+#else
+static uint8_t const ncm_configuration[] =
+{
+  // Config number (index+1), interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(CONFIG_ID_NCM+1, ITF_NUM_TOTAL, 0, NCM_CONFIG_TOTAL_LEN, 0, 100),
+
+  // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size.
+  TUD_CDC_NCM_DESCRIPTOR(ITF_NUM_CDC, STRID_INTERFACE, STRID_MAC, EPNUM_NET_NOTIF, 64, EPNUM_NET_OUT, EPNUM_NET_IN, CFG_TUD_NET_ENDPOINT_SIZE, CFG_TUD_NET_MTU),
+};
+#endif
 
 // Configuration array: RNDIS and CDC-ECM
 // - Windows only works with RNDIS
@@ -144,8 +160,12 @@ static uint8_t const ecm_configuration[] =
 // - Linux will work on both
 static uint8_t const * const configuration_arr[2] =
 {
+#if !CFG_TUD_NCM
   [CONFIG_ID_RNDIS] = rndis_configuration,
   [CONFIG_ID_ECM  ] = ecm_configuration
+#else
+  [CONFIG_ID_NCM  ] = ncm_configuration
+#endif
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/examples/rules.mk b/examples/rules.mk
index 861973284..a9dfa1363 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -33,7 +33,8 @@ SRC_C += \
 	src/class/hid/hid_device.c \
 	src/class/midi/midi_device.c \
 	src/class/msc/msc_device.c \
-	src/class/net/net_device.c \
+	src/class/net/ecmrndis_device.c \
+	src/class/net/ncm_device.c \
 	src/class/usbtmc/usbtmc_device.c \
 	src/class/vendor/vendor_device.c
 
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 41960b6cd..a0f41212c 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -70,7 +70,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/class/hid/hid_device.c
 			${TOP}/src/class/midi/midi_device.c
 			${TOP}/src/class/msc/msc_device.c
-			${TOP}/src/class/net/net_device.c
+			${TOP}/src/class/net/ecmrndis_device.c
+			${TOP}/src/class/net/ncm_device.c
 			${TOP}/src/class/usbtmc/usbtmc_device.c
 			${TOP}/src/class/vendor/vendor_device.c
 			)
diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index 5df47f70b..52de859ca 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -69,7 +69,8 @@ typedef enum
   CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT                 , ///< Device Management  [USBWMC1.1]
   CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL          , ///< Mobile Direct Line Model  [USBWMC1.1]
   CDC_COMM_SUBCLASS_OBEX                              , ///< OBEX  [USBWMC1.1]
-  CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL            ///< Ethernet Emulation Model  [USBEEM1.0]
+  CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL          , ///< Ethernet Emulation Model  [USBEEM1.0]
+  CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL               ///< Network Control Model  [USBNCM1.0]
 } cdc_comm_sublcass_type_t;
 
 /// Communication Interface Protocol Codes
@@ -114,7 +115,8 @@ typedef enum
   CDC_FUNC_DESC_COMMAND_SET                                      = 0x16 , ///< Command Set Functional Descriptor
   CDC_FUNC_DESC_COMMAND_SET_DETAIL                               = 0x17 , ///< Command Set Detail Functional Descriptor
   CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL                          = 0x18 , ///< Telephone Control Model Functional Descriptor
-  CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER                          = 0x19   ///< OBEX Service Identifier Functional Descriptor
+  CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER                          = 0x19 , ///< OBEX Service Identifier Functional Descriptor
+  CDC_FUNC_DESC_NCM                                              = 0x1A , ///< NCM Functional Descriptor
 }cdc_func_desc_type_t;
 
 //--------------------------------------------------------------------+
diff --git a/src/class/net/net_device.c b/src/class/net/ecmrndis_device.c
similarity index 98%
rename from src/class/net/net_device.c
rename to src/class/net/ecmrndis_device.c
index 9d9719ce4..288ecb7e2 100644
--- a/src/class/net/net_device.c
+++ b/src/class/net/ecmrndis_device.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NET )
+#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NET && !CFG_TUD_NCM )
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
@@ -119,6 +119,8 @@ static void do_in_xfer(uint8_t *buf, uint16_t len)
 
 void netd_report(uint8_t *buf, uint16_t len)
 {
+  // skip if previous report not yet acknowledged by host
+  if ( usbd_edpt_busy(TUD_OPT_RHPORT, _netd_itf.ep_notif) ) return;
   usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_notif, buf, len);
 }
 
@@ -407,8 +409,10 @@ bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   return true;
 }
 
-bool tud_network_can_xmit(void)
+bool tud_network_can_xmit(uint16_t size)
 {
+  (void)size;
+
   return can_xmit;
 }
 
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
new file mode 100644
index 000000000..1f592401e
--- /dev/null
+++ b/src/class/net/ncm_device.c
@@ -0,0 +1,500 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jacob Berg Potter
+ * Copyright (c) 2020 Peter Lawrence
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NET && CFG_TUD_NCM )
+
+#include "device/usbd.h"
+#include "device/usbd_pvt.h"
+#include "net_device.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+#define NTH16_SIGNATURE 0x484D434E
+#define NDP16_SIGNATURE_NCM0 0x304D434E
+#define NDP16_SIGNATURE_NCM1 0x314D434E
+
+typedef struct TU_ATTR_PACKED
+{
+  uint16_t wLength;
+  uint16_t bmNtbFormatsSupported;
+  uint32_t dwNtbInMaxSize;
+  uint16_t wNdbInDivisor;
+  uint16_t wNdbInPayloadRemainder;
+  uint16_t wNdbInAlignment;
+  uint16_t wReserved;
+  uint32_t dwNtbOutMaxSize;
+  uint16_t wNdbOutDivisor;
+  uint16_t wNdbOutPayloadRemainder;
+  uint16_t wNdbOutAlignment;
+  uint16_t wNtbOutMaxDatagrams;
+} ntb_parameters_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  uint32_t dwSignature;
+  uint16_t wHeaderLength;
+  uint16_t wSequence;
+  uint16_t wBlockLength;
+  uint16_t wNdpIndex;
+} nth16_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  uint16_t wDatagramIndex;
+  uint16_t wDatagramLength;
+} ndp16_datagram_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  uint32_t dwSignature;
+  uint16_t wLength;
+  uint16_t wNextNdpIndex;
+  ndp16_datagram_t datagram[];
+} ndp16_t;
+
+typedef union TU_ATTR_PACKED {
+  struct {
+    nth16_t nth;
+    ndp16_t ndp;
+  };
+  uint8_t data[CFG_TUD_NCM_IN_NTB_MAX_SIZE];
+} transmit_ntb_t;
+
+struct ecm_notify_struct
+{
+  tusb_control_request_t header;
+  uint32_t downlink, uplink;
+};
+
+typedef struct
+{
+  uint8_t itf_num;      // Index number of Management Interface, +1 for Data Interface
+  uint8_t itf_data_alt; // Alternate setting of Data Interface. 0 : inactive, 1 : active
+
+  uint8_t ep_notif;
+  uint8_t ep_in;
+  uint8_t ep_out;
+
+  const ndp16_t *ndp;
+  uint8_t num_datagrams, current_datagram_index;
+
+  enum {
+    REPORT_SPEED,
+    REPORT_CONNECTED,
+    REPORT_DONE
+  } report_state;
+  bool report_pending;
+
+  uint8_t current_ntb; // Index in transmit_ntb[] that is currently being filled with datagrams
+  uint8_t datagram_count; // Number of datagrams in transmit_ntb[current_ntb]
+  uint16_t next_datagram_offset; // Offset in transmit_ntb[current_ntb].data to place the next datagram
+  uint16_t ntb_in_size; // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE
+  uint8_t max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
+
+  uint16_t nth_sequence; // Sequence number counter for transmitted NTBs
+
+  bool transferring;
+
+} ncm_interface_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parameters = {
+    .wLength = sizeof(ntb_parameters_t),
+    .bmNtbFormatsSupported = 0x01,
+    .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
+    .wNdbInDivisor = 4,
+    .wNdbInPayloadRemainder = 0,
+    .wNdbInAlignment = CFG_TUD_NCM_ALIGNMENT,
+    .wReserved = 0,
+    .dwNtbOutMaxSize = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
+    .wNdbOutDivisor = 4,
+    .wNdbOutPayloadRemainder = 0,
+    .wNdbOutAlignment = CFG_TUD_NCM_ALIGNMENT,
+    .wNtbOutMaxDatagrams = 0
+};
+
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static transmit_ntb_t transmit_ntb[2];
+
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+
+static ncm_interface_t ncm_interface;
+
+/*
+ * Set up the NTB state in ncm_interface to be ready to add datagrams.
+ */
+static void ncm_prepare_for_tx(void) {
+  ncm_interface.datagram_count = 0;
+  // datagrams start after all the headers
+  ncm_interface.next_datagram_offset = sizeof(nth16_t) + sizeof(ndp16_t)
+      + ((CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB + 1) * sizeof(ndp16_datagram_t));
+}
+
+/*
+ * If not already transmitting, start sending the current NTB to the host and swap buffers
+ * to start filling the other one with datagrams.
+ */
+static void ncm_start_tx(void) {
+  if (ncm_interface.transferring) {
+    return;
+  }
+
+  transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
+  size_t ntb_length = ncm_interface.next_datagram_offset;
+
+  // Fill in NTB header
+  ntb->nth.dwSignature = NTH16_SIGNATURE;
+  ntb->nth.wHeaderLength = sizeof(nth16_t);
+  ntb->nth.wSequence = ncm_interface.nth_sequence++;
+  ntb->nth.wBlockLength = ntb_length;
+  ntb->nth.wNdpIndex = sizeof(nth16_t);
+
+  // Fill in NDP16 header and terminator
+  ntb->ndp.dwSignature = NDP16_SIGNATURE_NCM0;
+  ntb->ndp.wLength = sizeof(ndp16_t) + (ncm_interface.datagram_count + 1) * sizeof(ndp16_datagram_t);
+  ntb->ndp.wNextNdpIndex = 0;
+  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = 0;
+  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = 0;
+
+  // Kick off an endpoint transfer
+  usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_in, ntb->data, ntb_length);
+  ncm_interface.transferring = true;
+
+  // Swap to the other NTB and clear it out
+  ncm_interface.current_ntb = 1 - ncm_interface.current_ntb;
+  ncm_prepare_for_tx();
+}
+
+static struct ecm_notify_struct ncm_notify_connected =
+    {
+        .header = {
+            .bmRequestType = 0xA1,
+            .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */,
+            .wValue = 1 /* Connected */,
+            .wLength = 0,
+        },
+    };
+
+static struct ecm_notify_struct ncm_notify_speed_change =
+    {
+        .header = {
+            .bmRequestType = 0xA1,
+            .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */,
+            .wLength = 8,
+        },
+        .downlink = 10000000,
+        .uplink = 10000000,
+    };
+
+void tud_network_recv_renew(void)
+{
+  if (!ncm_interface.num_datagrams)
+  {
+    usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_out, receive_ntb, sizeof(receive_ntb));
+    return;
+  }
+
+  const ndp16_t *ndp = ncm_interface.ndp;
+  const int i = ncm_interface.current_datagram_index;
+  ncm_interface.current_datagram_index++;
+  ncm_interface.num_datagrams--;
+
+  tud_network_recv_cb(receive_ntb + ndp->datagram[i].wDatagramIndex, ndp->datagram[i].wDatagramLength);
+}
+
+//--------------------------------------------------------------------+
+// USBD Driver API
+//--------------------------------------------------------------------+
+
+void netd_init(void)
+{
+  tu_memclr(&ncm_interface, sizeof(ncm_interface));
+  ncm_interface.ntb_in_size = CFG_TUD_NCM_IN_NTB_MAX_SIZE;
+  ncm_interface.max_datagrams_per_ntb = CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB;
+  ncm_prepare_for_tx();
+}
+
+void netd_reset(uint8_t rhport)
+{
+  (void) rhport;
+
+  netd_init();
+}
+
+uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
+{
+  // confirm interface hasn't already been allocated
+  TU_ASSERT(0 == ncm_interface.ep_notif, 0);
+
+  //------------- Management Interface -------------//
+  ncm_interface.itf_num = itf_desc->bInterfaceNumber;
+
+  uint16_t drv_len = sizeof(tusb_desc_interface_t);
+  uint8_t const * p_desc = tu_desc_next( itf_desc );
+
+  // Communication Functional Descriptors
+  while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
+  {
+    drv_len += tu_desc_len(p_desc);
+    p_desc   = tu_desc_next(p_desc);
+  }
+
+  // notification endpoint (if any)
+  if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
+  {
+    TU_ASSERT( usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *) p_desc), 0 );
+
+    ncm_interface.ep_notif = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+
+    drv_len += tu_desc_len(p_desc);
+    p_desc   = tu_desc_next(p_desc);
+  }
+
+  //------------- Data Interface -------------//
+  // - CDC-NCM data interface has 2 alternate settings
+  //   - 0 : zero endpoints for inactive (default)
+  //   - 1 : IN & OUT endpoints for transfer of NTBs
+  TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0);
+
+  do
+  {
+    tusb_desc_interface_t const * data_itf_desc = (tusb_desc_interface_t const *) p_desc;
+    TU_ASSERT(TUSB_CLASS_CDC_DATA == data_itf_desc->bInterfaceClass, 0);
+
+    drv_len += tu_desc_len(p_desc);
+    p_desc   = tu_desc_next(p_desc);
+  } while((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && (drv_len <= max_len));
+
+  // Pair of endpoints
+  TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc), 0);
+
+  TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &ncm_interface.ep_out, &ncm_interface.ep_in) );
+
+  drv_len += 2*sizeof(tusb_desc_endpoint_t);
+
+  return drv_len;
+}
+
+static void ncm_report(void)
+{
+  if (ncm_interface.report_state == REPORT_SPEED) {
+    ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
+    usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
+    ncm_interface.report_state = REPORT_CONNECTED;
+    ncm_interface.report_pending = true;
+  } else if (ncm_interface.report_state == REPORT_CONNECTED) {
+    ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
+    usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected));
+    ncm_interface.report_state = REPORT_DONE;
+    ncm_interface.report_pending = true;
+  }
+}
+
+TU_ATTR_WEAK void tud_network_link_state_cb(bool state)
+{
+  (void)state;
+}
+
+// Handle class control request
+// return false to stall control endpoint (e.g unsupported request)
+bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
+{
+  if ( stage != CONTROL_STAGE_SETUP ) return true;
+
+  switch ( request->bmRequestType_bit.type )
+  {
+    case TUSB_REQ_TYPE_STANDARD:
+      switch ( request->bRequest )
+      {
+        case TUSB_REQ_GET_INTERFACE:
+        {
+          uint8_t const req_itfnum = (uint8_t) request->wIndex;
+          TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum);
+
+          tud_control_xfer(rhport, request, &ncm_interface.itf_data_alt, 1);
+        }
+          break;
+
+        case TUSB_REQ_SET_INTERFACE:
+        {
+          uint8_t const req_itfnum = (uint8_t) request->wIndex;
+          uint8_t const req_alt    = (uint8_t) request->wValue;
+
+          // Only valid for Data Interface with Alternate is either 0 or 1
+          TU_VERIFY(ncm_interface.itf_num + 1 == req_itfnum && req_alt < 2);
+
+          if (req_alt != ncm_interface.itf_data_alt) {
+            ncm_interface.itf_data_alt = req_alt;
+
+            if (ncm_interface.itf_data_alt) {
+              if (!usbd_edpt_busy(rhport, ncm_interface.ep_out)) {
+                tud_network_recv_renew(); // prepare for incoming datagrams
+              }
+              if (!ncm_interface.report_pending) {
+                ncm_report();
+              }
+            }
+
+            tud_network_link_state_cb(ncm_interface.itf_data_alt);
+          }
+
+          tud_control_status(rhport, request);
+        }
+          break;
+
+          // unsupported request
+        default: return false;
+      }
+      break;
+
+    case TUSB_REQ_TYPE_CLASS:
+      TU_VERIFY (ncm_interface.itf_num == request->wIndex);
+
+      if (0x80 /* GET_NTB_PARAMETERS */ == request->bRequest)
+      {
+        tud_control_xfer(rhport, request, (void*)&ntb_parameters, sizeof(ntb_parameters));
+      }
+
+      break;
+
+      // unsupported request
+    default: return false;
+  }
+
+  return true;
+}
+
+static void handle_incoming_datagram(uint32_t len)
+{
+  uint32_t size = len;
+
+  if (len == 0) {
+    return;
+  }
+
+  TU_ASSERT(size >= sizeof(nth16_t), );
+
+  const nth16_t *hdr = (const nth16_t *)receive_ntb;
+  TU_ASSERT(hdr->dwSignature == NTH16_SIGNATURE, );
+  TU_ASSERT(hdr->wNdpIndex >= sizeof(nth16_t) && (hdr->wNdpIndex + sizeof(ndp16_t)) <= len, );
+
+  const ndp16_t *ndp = (const ndp16_t *)(receive_ntb + hdr->wNdpIndex);
+  TU_ASSERT(ndp->dwSignature == NDP16_SIGNATURE_NCM0 || ndp->dwSignature == NDP16_SIGNATURE_NCM1, );
+  TU_ASSERT(hdr->wNdpIndex + ndp->wLength <= len, );
+
+  int num_datagrams = (ndp->wLength - 12) / 4;
+  ncm_interface.current_datagram_index = 0;
+  ncm_interface.num_datagrams = 0;
+  ncm_interface.ndp = ndp;
+  for (int i = 0; i < num_datagrams && ndp->datagram[i].wDatagramIndex && ndp->datagram[i].wDatagramLength; i++)
+    ncm_interface.num_datagrams++;
+  
+  tud_network_recv_renew();
+}
+
+bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+{
+  (void) rhport;
+  (void) result;
+
+  /* new datagram receive_ntb */
+  if (ep_addr == ncm_interface.ep_out )
+  {
+    handle_incoming_datagram(xferred_bytes);
+  }
+
+  /* data transmission finished */
+  if (ep_addr == ncm_interface.ep_in )
+  {
+    if (ncm_interface.transferring) {
+      ncm_interface.transferring = false;
+    }
+
+    // If there are datagrams queued up that we tried to send while this NTB was being emitted, send them now
+    if (ncm_interface.datagram_count && ncm_interface.itf_data_alt == 1) {
+      ncm_start_tx();
+    }
+  }
+
+  if (ep_addr == ncm_interface.ep_notif )
+  {
+    ncm_interface.report_pending = false;
+    ncm_report();
+  }
+
+  return true;
+}
+
+// poll network driver for its ability to accept another packet to transmit
+bool tud_network_can_xmit(uint16_t size)
+{
+  TU_VERIFY(ncm_interface.itf_data_alt == 1);
+
+  if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) {
+    TU_LOG2("NTB full [by count]\r\n");
+    return false;
+  }
+
+  size_t next_datagram_offset = ncm_interface.next_datagram_offset;
+  if (next_datagram_offset + size > ncm_interface.ntb_in_size) {
+    TU_LOG2("ntb full [by size]\r\n");
+    return false;
+  }
+
+  return true;
+}
+
+void tud_network_xmit(void *ref, uint16_t arg)
+{
+  transmit_ntb_t *ntb = &transmit_ntb[ncm_interface.current_ntb];
+  size_t next_datagram_offset = ncm_interface.next_datagram_offset;
+
+  uint16_t size = tud_network_xmit_cb(ntb->data + next_datagram_offset, ref, arg);
+
+  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramIndex = ncm_interface.next_datagram_offset;
+  ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = size;
+
+  ncm_interface.datagram_count++;
+  next_datagram_offset += size;
+
+  // round up so the next datagram is aligned correctly
+  next_datagram_offset += (CFG_TUD_NCM_ALIGNMENT - 1);
+  next_datagram_offset -= (next_datagram_offset % CFG_TUD_NCM_ALIGNMENT);
+
+  ncm_interface.next_datagram_offset = next_datagram_offset;
+
+  ncm_start_tx();
+}
+
+#endif
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index f030f3077..e6cdc8b8b 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -38,6 +38,22 @@
 #define CFG_TUD_NET_MTU           1514
 #endif
 
+#ifndef CFG_TUD_NCM_IN_NTB_MAX_SIZE
+#define CFG_TUD_NCM_IN_NTB_MAX_SIZE 3200
+#endif
+
+#ifndef CFG_TUD_NCM_OUT_NTB_MAX_SIZE
+#define CFG_TUD_NCM_OUT_NTB_MAX_SIZE 3200
+#endif
+
+#ifndef CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
+#define CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB 8
+#endif
+
+#ifndef CFG_TUD_NCM_ALIGNMENT
+#define CFG_TUD_NCM_ALIGNMENT 4
+#endif
+
 #ifdef __cplusplus
  extern "C" {
 #endif
@@ -63,11 +79,14 @@ extern const uint8_t tud_network_mac_address[6];
 void tud_network_recv_renew(void);
 
 // poll network driver for its ability to accept another packet to transmit
-bool tud_network_can_xmit(void);
+bool tud_network_can_xmit(uint16_t size);
 
 // if network_can_xmit() returns true, network_xmit() can be called once
 void tud_network_xmit(void *ref, uint16_t arg);
 
+// callback to client providing optional indication of internal state of network driver
+void tud_network_link_state_cb(bool state);
+
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 638d93094..200e1cca1 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -781,6 +781,37 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \
   TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__)
 
+//------------- CDC-NCM -------------//
+
+// Length of template descriptor
+#define TUD_CDC_NCM_DESC_LEN  (8+9+5+5+13+6+7+9+9+7+7)
+
+// CDC-ECM Descriptor Template
+// Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size.
+#define TUD_CDC_NCM_DESCRIPTOR(_itfnum, _desc_stridx, _mac_stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize, _maxsegmentsize) \
+  /* Interface Association */\
+  8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, 0,\
+  /* CDC Control Interface */\
+  9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, _desc_stridx,\
+  /* CDC-NCM Header */\
+  5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110),\
+  /* CDC-NCM Union */\
+  5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\
+  /* CDC-ECM Functional Descriptor */\
+  13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0, \
+  /* CDC-ECM Functional Descriptor */\
+  6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, \
+  /* Endpoint Notification */\
+  7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 50,\
+  /* CDC Data Interface (default inactive) */\
+  9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 1, 0,\
+  /* CDC Data Interface (alternative active) */\
+  9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, 1, 0,\
+  /* Endpoint In */\
+  7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\
+  /* Endpoint Out */\
+  7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index ad2a26a66..12aab82fc 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -269,6 +269,10 @@
   #define CFG_TUD_BTH             0
 #endif
 
+#ifndef CFG_TUD_NCM
+  #define CFG_TUD_NCM             0
+#endif
+
 //--------------------------------------------------------------------
 // HOST OPTIONS
 //--------------------------------------------------------------------

From fba5ec813423b3e3e0f08c5c54e40143a9632e4e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 26 Sep 2021 12:23:08 +0700
Subject: [PATCH 0496/2085] make freertos header include in examples more
 explicit

---
 examples/device/cdc_msc_freertos/src/main.c   | 22 +++++++++++++------
 .../device/hid_composite_freertos/src/main.c  | 22 +++++++++++++------
 2 files changed, 30 insertions(+), 14 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index af00b3cc2..65b7fda3b 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -30,13 +30,21 @@
 #include "bsp/board.h"
 #include "tusb.h"
 
-// FreeRTOS headers, MCUs such as esp32sx requires "freertos/" prefix in include path.
-// CFG_TUSB_OS_INC_PATH should be defined accordingly.
-#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h)
-#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h)
-#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h)
-#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h)
-#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,timers.h)
+#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+  // ESP-IDF need "freertos/" prefix in include path.
+  // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+  #include "freertos/FreeRTOS.h"
+  #include "freertos/semphr.h"
+  #include "freertos/queue.h"
+  #include "freertos/task.h"
+  #include "freertos/timers.h"
+#else
+  #include "FreeRTOS.h"
+  #include "semphr.h"
+  #include "queue.h"
+  #include "task.h"
+  #include "timers.h"
+#endif
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 8a184f60f..b25c71f64 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -31,13 +31,21 @@
 #include "tusb.h"
 #include "usb_descriptors.h"
 
-// FreeRTOS headers, MCUs such as esp32sx requires "freertos/" prefix in include path.
-// CFG_TUSB_OS_INC_PATH should be defined accordingly.
-#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h)
-#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h)
-#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h)
-#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h)
-#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,timers.h)
+#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+  // ESP-IDF need "freertos/" prefix in include path.
+  // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+  #include "freertos/FreeRTOS.h"
+  #include "freertos/semphr.h"
+  #include "freertos/queue.h"
+  #include "freertos/task.h"
+  #include "freertos/timers.h"
+#else
+  #include "FreeRTOS.h"
+  #include "semphr.h"
+  #include "queue.h"
+  #include "task.h"
+  #include "timers.h"
+#endif
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES

From 196a0da813ced4f13f04a3062873b352bc728d6d Mon Sep 17 00:00:00 2001
From: Hans Baier <hansfbaier@gmail.com>
Date: Mon, 27 Sep 2021 05:58:58 +0700
Subject: [PATCH 0497/2085] add support for the QMTech ATMSAME70N19A board

---
 hw/bsp/same70_qmtech/board.mk                |   56 +
 hw/bsp/same70_qmtech/hpl_pmc_config.h        | 1053 +++++
 hw/bsp/same70_qmtech/hpl_usart_config.h      |  215 +
 hw/bsp/same70_qmtech/hpl_xdmac_config.h      | 4400 ++++++++++++++++++
 hw/bsp/same70_qmtech/peripheral_clk_config.h |  126 +
 hw/bsp/same70_qmtech/same70_qmtech.c         |  159 +
 6 files changed, 6009 insertions(+)
 create mode 100644 hw/bsp/same70_qmtech/board.mk
 create mode 100644 hw/bsp/same70_qmtech/hpl_pmc_config.h
 create mode 100644 hw/bsp/same70_qmtech/hpl_usart_config.h
 create mode 100644 hw/bsp/same70_qmtech/hpl_xdmac_config.h
 create mode 100644 hw/bsp/same70_qmtech/peripheral_clk_config.h
 create mode 100644 hw/bsp/same70_qmtech/same70_qmtech.c

diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
new file mode 100644
index 000000000..6c84810f3
--- /dev/null
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -0,0 +1,56 @@
+DEPS_SUBMODULES += hw/mcu/microchip
+
+CFLAGS += \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m7 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -nostdlib -nostartfiles \
+  -D__SAME70N19B__ \
+  -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
+
+# suppress following warnings from mcu driver
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
+
+ASF_DIR = hw/mcu/microchip/same70
+
+# All source paths should be relative to the top level.
+LD_FILE = $(ASF_DIR)/same70b/gcc/gcc/same70q21b_flash.ld
+
+SRC_C += \
+	src/portable/microchip/samx7x/dcd_samx7x.c \
+	$(ASF_DIR)/same70b/gcc/gcc/startup_same70q21b.c \
+	$(ASF_DIR)/same70b/gcc/system_same70q21b.c \
+	$(ASF_DIR)/hpl/core/hpl_init.c \
+	$(ASF_DIR)/hpl/usart/hpl_usart.c \
+	$(ASF_DIR)/hpl/pmc/hpl_pmc.c \
+	$(ASF_DIR)/hal/src/hal_usart_async.c \
+	$(ASF_DIR)/hal/src/hal_io.c \
+	$(ASF_DIR)/hal/src/hal_atomic.c \
+	$(ASF_DIR)/hal/utils/src/utils_ringbuffer.c
+
+INC += \
+  $(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(ASF_DIR) \
+	$(TOP)/$(ASF_DIR)/config \
+	$(TOP)/$(ASF_DIR)/same70b/include \
+	$(TOP)/$(ASF_DIR)/hal/include \
+	$(TOP)/$(ASF_DIR)/hal/utils/include \
+	$(TOP)/$(ASF_DIR)/hpl/core \
+	$(TOP)/$(ASF_DIR)/hpl/pio \
+	$(TOP)/$(ASF_DIR)/hpl/pmc \
+	$(TOP)/$(ASF_DIR)/hri \
+	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM7
+
+# For flash-jlink target
+JLINK_DEVICE = SAME70N19B
+
+# flash using edbg from https://github.com/ataradov/edbg
+# Note: SAME70's GPNVM1 must be set to 1 to boot from flash with
+# 	edbg -t same70 -F w0,1,1
+flash: $(BUILD)/$(PROJECT).bin
+	edbg --verbose -t same70 -pv -f $<
diff --git a/hw/bsp/same70_qmtech/hpl_pmc_config.h b/hw/bsp/same70_qmtech/hpl_pmc_config.h
new file mode 100644
index 000000000..387aaa5df
--- /dev/null
+++ b/hw/bsp/same70_qmtech/hpl_pmc_config.h
@@ -0,0 +1,1053 @@
+/* Auto-generated config file hpl_pmc_config.h */
+#ifndef HPL_PMC_CONFIG_H
+#define HPL_PMC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#define CLK_SRC_OPTION_OSC32K 0
+#define CLK_SRC_OPTION_XOSC32K 1
+#define CLK_SRC_OPTION_OSC12M 2
+#define CLK_SRC_OPTION_XOSC20M 3
+
+#define CLK_SRC_OPTION_SLCK 0
+#define CLK_SRC_OPTION_MAINCK 1
+#define CLK_SRC_OPTION_PLLACK 2
+#define CLK_SRC_OPTION_UPLLCKDIV 3
+#define CLK_SRC_OPTION_MCK 4
+
+#define CLK_SRC_OPTION_UPLLCK 3
+
+#define CONF_RC_4M 0
+#define CONF_RC_8M 1
+#define CONF_RC_12M 2
+
+#define CONF_XOSC32K_NO_BYPASS 0
+#define CONF_XOSC32K_BYPASS 1
+
+#define CONF_XOSC20M_NO_BYPASS 0
+#define CONF_XOSC20M_BYPASS 1
+
+// <e> Clock_SLCK configuration
+// <i> Indicates whether SLCK configuration is enabled or not
+// <id> enable_clk_gen_slck
+#ifndef CONF_CLK_SLCK_CONFIG
+#define CONF_CLK_SLCK_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator SLCK source
+
+// <CLK_SRC_OPTION_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K)
+
+// <CLK_SRC_OPTION_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
+
+// <i> This defines the clock source for SLCK
+// <id> clk_gen_slck_oscillator
+#ifndef CONF_CLK_GEN_SLCK_SRC
+#define CONF_CLK_GEN_SLCK_SRC CLK_SRC_OPTION_OSC32K
+#endif
+
+// <q> Enable Clock_SLCK
+// <i> Indicates whether SLCK is enabled or disable
+// <id> clk_gen_slck_arch_enable
+#ifndef CONF_CLK_SLCK_ENABLE
+#define CONF_CLK_SLCK_ENABLE 1
+#endif
+
+// </h>
+
+// <h>
+
+// </h>
+// </e>// <e> Clock_MAINCK configuration
+// <i> Indicates whether MAINCK configuration is enabled or not
+// <id> enable_clk_gen_mainck
+#ifndef CONF_CLK_MAINCK_CONFIG
+#define CONF_CLK_MAINCK_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator MAINCK source
+
+// <CLK_SRC_OPTION_OSC12M"> Embedded 4/8/12MHz RC Oscillator (OSC12M)
+
+// <CLK_SRC_OPTION_XOSC20M"> External 3-20MHz Oscillator (XOSC20M)
+
+// <i> This defines the clock source for MAINCK
+// <id> clk_gen_mainck_oscillator
+#ifndef CONF_CLK_GEN_MAINCK_SRC
+#define CONF_CLK_GEN_MAINCK_SRC CLK_SRC_OPTION_XOSC20M
+#endif
+
+// <q> Enable Clock_MAINCK
+// <i> Indicates whether MAINCK is enabled or disable
+// <id> clk_gen_mainck_arch_enable
+#ifndef CONF_CLK_MAINCK_ENABLE
+#define CONF_CLK_MAINCK_ENABLE 1
+#endif
+
+// <q> Enable Main Clock Failure Detection
+// <i> Indicates whether Main Clock Failure Detection is enabled or disable.
+// <i> The 4/8/12 MHz RC oscillator must be selected as the source of MAINCK.
+// <id> clk_gen_cfden_enable
+#ifndef CONF_CLK_CFDEN_ENABLE
+#define CONF_CLK_CFDEN_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// </h>
+// </e>// <e> Clock_MCKR configuration
+// <i> Indicates whether MCKR configuration is enabled or not
+// <id> enable_clk_gen_mckr
+#ifndef CONF_CLK_MCKR_CONFIG
+#define CONF_CLK_MCKR_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator MCKR source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <i> This defines the clock source for MCKR
+// <id> clk_gen_mckr_oscillator
+#ifndef CONF_CLK_GEN_MCKR_SRC
+#define CONF_CLK_GEN_MCKR_SRC CLK_SRC_OPTION_PLLACK
+#endif
+
+// <q> Enable Clock_MCKR
+// <i> Indicates whether MCKR is enabled or disable
+// <id> clk_gen_mckr_arch_enable
+#ifndef CONF_CLK_MCKR_ENABLE
+#define CONF_CLK_MCKR_ENABLE 1
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Master Clock Prescaler
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// <4=> 16
+// <5=> 32
+// <6=> 64
+// <7=> 3
+// <i> Select the clock prescaler.
+// <id> mckr_presc
+#ifndef CONF_MCKR_PRESC
+#define CONF_MCKR_PRESC 0
+#endif
+
+// </h>
+// </e>// <e> Clock_MCK configuration
+// <i> Indicates whether MCK configuration is enabled or not
+// <id> enable_clk_gen_mck
+#ifndef CONF_CLK_MCK_CONFIG
+#define CONF_CLK_MCK_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator MCK source
+
+// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR)
+
+// <i> This defines the clock source for MCK
+// <id> clk_gen_mck_oscillator
+#ifndef CONF_CLK_GEN_MCK_SRC
+#define CONF_CLK_GEN_MCK_SRC CLK_SRC_OPTION_MCKR
+#endif
+
+// </h>
+
+// <h>
+
+//<o> Master Clock Controller Divider MCK divider
+// <0=> 1
+// <1=> 2
+// <3=> 3
+// <2=> 4
+// <i> Select the master clock divider.
+// <id> mck_div
+#ifndef CONF_MCK_DIV
+#define CONF_MCK_DIV 1
+#endif
+
+// </h>
+// </e>// <e> Clock_SYSTICK configuration
+// <i> Indicates whether SYSTICK configuration is enabled or not
+// <id> enable_clk_gen_systick
+#ifndef CONF_CLK_SYSTICK_CONFIG
+#define CONF_CLK_SYSTICK_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator SYSTICK source
+
+// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR)
+
+// <i> This defines the clock source for SYSTICK
+// <id> clk_gen_systick_oscillator
+#ifndef CONF_CLK_GEN_SYSTICK_SRC
+#define CONF_CLK_GEN_SYSTICK_SRC CLK_SRC_OPTION_MCKR
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Systick clock divider
+// <8=> 8
+// <i> Select systick clock divider
+// <id> systick_clock_div
+#ifndef CONF_SYSTICK_DIV
+#define CONF_SYSTICK_DIV 8
+#endif
+
+// </h>
+// </e>// <e> Clock_FCLK configuration
+// <i> Indicates whether FCLK configuration is enabled or not
+// <id> enable_clk_gen_fclk
+#ifndef CONF_CLK_FCLK_CONFIG
+#define CONF_CLK_FCLK_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator FCLK source
+
+// <CLK_SRC_OPTION_MCKR"> Master Clock Controller (PMC_MCKR)
+
+// <i> This defines the clock source for FCLK
+// <id> clk_gen_fclk_oscillator
+#ifndef CONF_CLK_GEN_FCLK_SRC
+#define CONF_CLK_GEN_FCLK_SRC CLK_SRC_OPTION_MCKR
+#endif
+
+// </h>
+
+// <h>
+
+// </h>
+// </e>// <e> Clock_GCLK0 configuration
+// <i> Indicates whether GCLK0 configuration is enabled or not
+// <id> enable_clk_gen_gclk0
+#ifndef CONF_CLK_GCLK0_CONFIG
+#define CONF_CLK_GCLK0_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator GCLK0 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for GCLK0
+// <id> clk_gen_gclk0_oscillator
+#ifndef CONF_CLK_GEN_GCLK0_SRC
+#define CONF_CLK_GEN_GCLK0_SRC CLK_SRC_OPTION_MCK
+#endif
+
+// <q> Enable Clock_GCLK0
+// <i> Indicates whether GCLK0 is enabled or disable
+// <id> clk_gen_gclk0_arch_enable
+#ifndef CONF_CLK_GCLK0_ENABLE
+#define CONF_CLK_GCLK0_ENABLE 1
+#endif
+
+// </h>
+
+// <h>
+// <q> Enable GCLK0 GCLKEN
+// <i> Indicates whether GCLK0 GCLKEN is enabled or disable
+// <id> gclk0_gclken_enable
+#ifndef CONF_GCLK0_GCLKEN_ENABLE
+#define CONF_GCLK0_GCLKEN_ENABLE 0
+#endif
+
+// <o> Generic Clock GCLK0 divider <1-256>
+// <i> Select the clock divider (divider = GCLKDIV + 1).
+// <id> gclk0_div
+#ifndef CONF_GCLK0_DIV
+#define CONF_GCLK0_DIV 2
+#endif
+
+// </h>
+// </e>// <e> Clock_GCLK1 configuration
+// <i> Indicates whether GCLK1 configuration is enabled or not
+// <id> enable_clk_gen_gclk1
+#ifndef CONF_CLK_GCLK1_CONFIG
+#define CONF_CLK_GCLK1_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator GCLK1 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for GCLK1
+// <id> clk_gen_gclk1_oscillator
+#ifndef CONF_CLK_GEN_GCLK1_SRC
+#define CONF_CLK_GEN_GCLK1_SRC CLK_SRC_OPTION_PLLACK
+#endif
+
+// <q> Enable Clock_GCLK1
+// <i> Indicates whether GCLK1 is enabled or disable
+// <id> clk_gen_gclk1_arch_enable
+#ifndef CONF_CLK_GCLK1_ENABLE
+#define CONF_CLK_GCLK1_ENABLE 1
+#endif
+
+// </h>
+
+// <h>
+// <q> Enable GCLK1 GCLKEN
+// <i> Indicates whether GCLK1 GCLKEN is enabled or disable
+// <id> gclk1_gclken_enable
+#ifndef CONF_GCLK1_GCLKEN_ENABLE
+#define CONF_GCLK1_GCLKEN_ENABLE 0
+#endif
+
+// <o> Generic Clock GCLK1 divider <1-256>
+// <i> Select the clock divider (divider = GCLKDIV + 1).
+// <id> gclk1_div
+#ifndef CONF_GCLK1_DIV
+#define CONF_GCLK1_DIV 3
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK0 configuration
+// <i> Indicates whether PCK0 configuration is enabled or not
+// <id> enable_clk_gen_pck0
+#ifndef CONF_CLK_PCK0_CONFIG
+#define CONF_CLK_PCK0_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK0 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK0
+// <id> clk_gen_pck0_oscillator
+#ifndef CONF_CLK_GEN_PCK0_SRC
+#define CONF_CLK_GEN_PCK0_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK0
+// <i> Indicates whether PCK0 is enabled or disable
+// <id> clk_gen_pck0_arch_enable
+#ifndef CONF_CLK_PCK0_ENABLE
+#define CONF_CLK_PCK0_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck0_presc
+#ifndef CONF_PCK0_PRESC
+#define CONF_PCK0_PRESC 1
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK1 configuration
+// <i> Indicates whether PCK1 configuration is enabled or not
+// <id> enable_clk_gen_pck1
+#ifndef CONF_CLK_PCK1_CONFIG
+#define CONF_CLK_PCK1_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK1 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK1
+// <id> clk_gen_pck1_oscillator
+#ifndef CONF_CLK_GEN_PCK1_SRC
+#define CONF_CLK_GEN_PCK1_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK1
+// <i> Indicates whether PCK1 is enabled or disable
+// <id> clk_gen_pck1_arch_enable
+#ifndef CONF_CLK_PCK1_ENABLE
+#define CONF_CLK_PCK1_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck1_presc
+#ifndef CONF_PCK1_PRESC
+#define CONF_PCK1_PRESC 2
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK2 configuration
+// <i> Indicates whether PCK2 configuration is enabled or not
+// <id> enable_clk_gen_pck2
+#ifndef CONF_CLK_PCK2_CONFIG
+#define CONF_CLK_PCK2_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK2 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK2
+// <id> clk_gen_pck2_oscillator
+#ifndef CONF_CLK_GEN_PCK2_SRC
+#define CONF_CLK_GEN_PCK2_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK2
+// <i> Indicates whether PCK2 is enabled or disable
+// <id> clk_gen_pck2_arch_enable
+#ifndef CONF_CLK_PCK2_ENABLE
+#define CONF_CLK_PCK2_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck2_presc
+#ifndef CONF_PCK2_PRESC
+#define CONF_PCK2_PRESC 3
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK3 configuration
+// <i> Indicates whether PCK3 configuration is enabled or not
+// <id> enable_clk_gen_pck3
+#ifndef CONF_CLK_PCK3_CONFIG
+#define CONF_CLK_PCK3_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK3 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK3
+// <id> clk_gen_pck3_oscillator
+#ifndef CONF_CLK_GEN_PCK3_SRC
+#define CONF_CLK_GEN_PCK3_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK3
+// <i> Indicates whether PCK3 is enabled or disable
+// <id> clk_gen_pck3_arch_enable
+#ifndef CONF_CLK_PCK3_ENABLE
+#define CONF_CLK_PCK3_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck3_presc
+#ifndef CONF_PCK3_PRESC
+#define CONF_PCK3_PRESC 4
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK4 configuration
+// <i> Indicates whether PCK4 configuration is enabled or not
+// <id> enable_clk_gen_pck4
+#ifndef CONF_CLK_PCK4_CONFIG
+#define CONF_CLK_PCK4_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK4 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK4
+// <id> clk_gen_pck4_oscillator
+#ifndef CONF_CLK_GEN_PCK4_SRC
+#define CONF_CLK_GEN_PCK4_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK4
+// <i> Indicates whether PCK4 is enabled or disable
+// <id> clk_gen_pck4_arch_enable
+#ifndef CONF_CLK_PCK4_ENABLE
+#define CONF_CLK_PCK4_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck4_presc
+#ifndef CONF_PCK4_PRESC
+#define CONF_PCK4_PRESC 5
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK5 configuration
+// <i> Indicates whether PCK5 configuration is enabled or not
+// <id> enable_clk_gen_pck5
+#ifndef CONF_CLK_PCK5_CONFIG
+#define CONF_CLK_PCK5_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK5 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK5
+// <id> clk_gen_pck5_oscillator
+#ifndef CONF_CLK_GEN_PCK5_SRC
+#define CONF_CLK_GEN_PCK5_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK5
+// <i> Indicates whether PCK5 is enabled or disable
+// <id> clk_gen_pck5_arch_enable
+#ifndef CONF_CLK_PCK5_ENABLE
+#define CONF_CLK_PCK5_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck5_presc
+#ifndef CONF_PCK5_PRESC
+#define CONF_PCK5_PRESC 6
+#endif
+
+// </h>
+// </e>// <e> Clock_PCK6 configuration
+// <i> Indicates whether PCK6 configuration is enabled or not
+// <id> enable_clk_gen_pck6
+#ifndef CONF_CLK_PCK6_CONFIG
+#define CONF_CLK_PCK6_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator PCK6 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <CLK_SRC_OPTION_MAINCK"> Main Clock (MAINCK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_MCK"> Master Clock (MCK)
+
+// <i> This defines the clock source for PCK6
+// <id> clk_gen_pck6_oscillator
+#ifndef CONF_CLK_GEN_PCK6_SRC
+#define CONF_CLK_GEN_PCK6_SRC CLK_SRC_OPTION_MAINCK
+#endif
+
+// <q> Enable Clock_PCK6
+// <i> Indicates whether PCK6 is enabled or disable
+// <id> clk_gen_pck6_arch_enable
+#ifndef CONF_CLK_PCK6_ENABLE
+#define CONF_CLK_PCK6_ENABLE 0
+#endif
+
+// </h>
+
+// <h>
+
+// <o> Programmable Clock Controller Prescaler <1-256>
+// <i> Select the clock prescaler (prescaler = PRESC + 1).
+// <id> pck6_presc
+#ifndef CONF_PCK6_PRESC
+#define CONF_PCK6_PRESC 7
+#endif
+
+// </h>
+// </e>// <e> Clock_USB_480M configuration
+// <i> Indicates whether USB_480M configuration is enabled or not
+// <id> enable_clk_gen_usb_480m
+#ifndef CONF_CLK_USB_480M_CONFIG
+#define CONF_CLK_USB_480M_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator USB_480M source
+
+// <CLK_SRC_OPTION_UPLLCK"> USB 480M Clock (UPLLCK)
+
+// <i> This defines the clock source for USB_480M
+// <id> clk_gen_usb_480m_oscillator
+#ifndef CONF_CLK_GEN_USB_480M_SRC
+#define CONF_CLK_GEN_USB_480M_SRC CLK_SRC_OPTION_UPLLCK
+#endif
+
+// </h>
+
+// <h>
+
+// </h>
+// </e>// <e> Clock_USB_48M configuration
+// <i> Indicates whether USB_48M configuration is enabled or not
+// <id> enable_clk_gen_usb_48m
+#ifndef CONF_CLK_USB_48M_CONFIG
+#define CONF_CLK_USB_48M_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator USB_48M source
+
+// <CLK_SRC_OPTION_PLLACK"> PLLA Clock (PLLACK)
+
+// <CLK_SRC_OPTION_UPLLCKDIV"> UDPLL with Divider (MCKR UPLLDIV2)
+
+// <i> This defines the clock source for USB_48M
+// <id> clk_gen_usb_48m_oscillator
+#ifndef CONF_CLK_GEN_USB_48M_SRC
+#define CONF_CLK_GEN_USB_48M_SRC CLK_SRC_OPTION_UPLLCKDIV
+#endif
+
+// <q> Enable Clock_USB_48M
+// <i> Indicates whether USB_48M is enabled or disable
+// <id> clk_gen_usb_48m_arch_enable
+#ifndef CONF_CLK_USB_48M_ENABLE
+#define CONF_CLK_USB_48M_ENABLE 1
+#endif
+
+// </h>
+
+// <h>
+
+// <o> USB Clock Controller Divider <1-16>
+// <i> Select the USB clock divider (divider = USBDIV + 1).
+// <id> usb_48m_div
+#ifndef CONF_USB_48M_DIV
+#define CONF_USB_48M_DIV 5
+#endif
+
+// </h>
+// </e>// <e> Clock_SLCK2 configuration
+// <i> Indicates whether SLCK2 configuration is enabled or not
+// <id> enable_clk_gen_slck2
+#ifndef CONF_CLK_SLCK2_CONFIG
+#define CONF_CLK_SLCK2_CONFIG 1
+#endif
+
+//<h> Clock Generator
+// <y> clock generator SLCK2 source
+
+// <CLK_SRC_OPTION_SLCK"> Slow Clock (SLCK)
+
+// <i> This defines the clock source for SLCK2
+// <id> clk_gen_slck2_oscillator
+#ifndef CONF_CLK_GEN_SLCK2_SRC
+#define CONF_CLK_GEN_SLCK2_SRC CLK_SRC_OPTION_SLCK
+#endif
+
+// </h>
+
+// <h>
+
+// </h>
+// </e>
+
+// <e> System Configuration
+// <i> Indicates whether configuration for system is enabled or not
+// <id> enable_hclk_clock
+#ifndef CONF_SYSTEM_CONFIG
+#define CONF_SYSTEM_CONFIG 1
+#endif
+
+// <h> Processor Clock Settings
+// <y> Processor Clock source
+// <MCKR"> Master Clock Controller (PMC_MCKR)
+// <i> This defines the clock source for the HCLK (Processor clock)
+// <id> hclk_clock_source
+#ifndef CONF_HCLK_SRC
+#define CONF_HCLK_SRC MCKR
+#endif
+
+// <o> Flash Wait State
+// <0=> 1 cycle
+// <1=> 2 cycles
+// <2=> 3 cycles
+// <3=> 4 cycles
+// <4=> 5 cycles
+// <5=> 6 cycles
+// <6=> 7 cycles
+// <i> This field defines the number of wait states for read and write operations.
+// <id> efc_fws
+#ifndef CONF_EFC_WAIT_STATE
+#define CONF_EFC_WAIT_STATE 5
+#endif
+
+// </h>
+// </e>
+
+// <e> SysTick Clock
+// <id> enable_systick_clk_clock
+#ifndef CONF_SYSTICK_CLK_CONFIG
+#define CONF_SYSTICK_CLK_CONFIG 1
+#endif
+
+// <y> SysTick Clock source
+// <MCKR"> Master Clock Controller (PMC_MCKR)
+// <i> This defines the clock source for the SysTick Clock
+// <id> systick_clk_clock_source
+#ifndef CONF_SYSTICK_CLK_SRC
+#define CONF_SYSTICK_CLK_SRC MCKR
+#endif
+
+// <o> SysTick Clock Divider
+// <8=> 8
+// <i> Fixed to 8 if Systick is not using Processor clock
+// <id> systick_clk_clock_div
+#ifndef CONF_SYSTICK_CLK_DIV
+#define CONF_SYSTICK_CLK_DIV 8
+#endif
+
+// </e>
+
+// <e> OSC32K Oscillator Configuration
+// <i> Indicates whether configuration for OSC32K is enabled or not
+// <id> enable_osc32k
+#ifndef CONF_OSC32K_CONFIG
+#define CONF_OSC32K_CONFIG 1
+#endif
+
+// <h> OSC32K Oscillator Control
+// <q> OSC32K Oscillator Enable
+// <i> Indicates whether OSC32K Oscillator is enabled or not
+// <id> osc32k_arch_enable
+#ifndef CONF_OSC32K_ENABLE
+#define CONF_OSC32K_ENABLE 0
+#endif
+// </h>
+// </e>
+
+// <e> XOSC32K Oscillator Configuration
+// <i> Indicates whether configuration for XOSC32K is enabled or not
+// <id> enable_xosc32k
+#ifndef CONF_XOSC32K_CONFIG
+#define CONF_XOSC32K_CONFIG 0
+#endif
+
+// <h> XOSC32K Oscillator Control
+// <y> Oscillator Bypass Select
+// <CONF_XOSC32K_NO_BYPASS"> The 32kHz crystal oscillator is not bypassed.
+// <CONF_XOSC32K_BYPASS"> The 32kHz crystal oscillator is bypassed.
+// <i> Indicates whether XOSC32K is bypassed.
+// <id> xosc32k_bypass
+#ifndef CONF_XOSC32K
+#define CONF_XOSC32K CONF_XOSC32K_NO_BYPASS
+#endif
+
+// <q> XOSC32K Oscillator Enable
+// <i> Indicates whether XOSC32K Oscillator is enabled or not
+// <id> xosc32k_arch_enable
+#ifndef CONF_XOSC32K_ENABLE
+#define CONF_XOSC32K_ENABLE 0
+#endif
+// </h>
+// </e>
+
+// <e> OSC12M Oscillator Configuration
+// <i> Indicates whether configuration for OSC12M is enabled or not
+// <id> enable_osc12m
+#ifndef CONF_OSC12M_CONFIG
+#define CONF_OSC12M_CONFIG 0
+#endif
+
+// <h> OSC12M Oscillator Control
+// <q> OSC12M Oscillator Enable
+// <i> Indicates whether OSC12M Oscillator is enabled or not.
+// <id> osc12m_arch_enable
+#ifndef CONF_OSC12M_ENABLE
+#define CONF_OSC12M_ENABLE 0
+#endif
+
+// <o> OSC12M selector
+//  <0=> 4000000
+//  <1=> 8000000
+//  <2=> 12000000
+// <i> Select the frequency of embedded fast RC oscillator.
+// <id> osc12m_selector
+#ifndef CONF_OSC12M_SELECTOR
+#define CONF_OSC12M_SELECTOR 2
+#endif
+// </h>
+// </e>
+
+// <e> XOSC20M Oscillator Configuration
+// <i> Indicates whether configuration for XOSC20M is enabled or not.
+// <id> enable_xosc20m
+#ifndef CONF_XOSC20M_CONFIG
+#define CONF_XOSC20M_CONFIG 1
+#endif
+
+// <h> XOSC20M Oscillator Control
+// <o> XOSC20M selector <3000000-20000000>
+// <i> Select the frequency of crystal or ceramic resonator oscillator.
+// <id> xosc20m_selector
+#ifndef CONF_XOSC20M_SELECTOR
+#define CONF_XOSC20M_SELECTOR 12000000
+#endif
+
+// <o> Start up time for the external oscillator (ms): <0-256>
+// <i> Select start-up time.
+// <id> xosc20m_startup_time
+#ifndef CONF_XOSC20M_STARTUP_TIME
+#define CONF_XOSC20M_STARTUP_TIME 62
+#endif
+
+// <y> Oscillator Bypass Select
+// <CONF_XOSC20M_NO_BYPASS"> The external crystal oscillator is not bypassed.
+// <CONF_XOSC20M_BYPASS"> The external crystal oscillator is bypassed.
+// <i> Indicates whether XOSC20M is bypassed.
+// <id> xosc20m_bypass
+#ifndef CONF_XOSC20M
+#define CONF_XOSC20M CONF_XOSC20M_NO_BYPASS
+#endif
+
+// <q> XOSC20M Oscillator Enable
+// <i> Indicates whether XOSC20M Oscillator is enabled or not
+// <id> xosc20m_arch_enable
+#ifndef CONF_XOSC20M_ENABLE
+#define CONF_XOSC20M_ENABLE 1
+#endif
+// </h>
+// </e>
+
+// <e> PLLACK Oscillator Configuration
+// <i> Indicates whether configuration for PLLACK is enabled or not
+// <id> enable_pllack
+#ifndef CONF_PLLACK_CONFIG
+#define CONF_PLLACK_CONFIG 1
+#endif
+
+// <y> PLLACK Reference Clock Source
+// <MAINCK"> Main Clock (MAINCK)
+// <i> Select the clock source.
+// <id> pllack_ref_clock
+#ifndef CONF_PLLACK_CLK
+#define CONF_PLLACK_CLK MAINCK
+#endif
+
+// <h> PLLACK Oscillator Control
+// <q> PLLACK Oscillator Enable
+// <i> Indicates whether PLLACK Oscillator is enabled or not
+// <id> pllack_arch_enable
+#ifndef CONF_PLLACK_ENABLE
+#define CONF_PLLACK_ENABLE 1
+#endif
+
+// <o> PLLA Frontend Divider (DIVA)  <1-255>
+// <i> Select the clock divider
+// <id> pllack_div
+#ifndef CONF_PLLACK_DIV
+#define CONF_PLLACK_DIV 1
+#endif
+
+// <o> PLLACK Muliplier <1-62>
+// <i> Indicates PLLA multiplier (multiplier = MULA + 1).
+// <id> pllack_mul
+#ifndef CONF_PLLACK_MUL
+#define CONF_PLLACK_MUL 25
+#endif
+// </h>
+// </e>
+
+// <e> UPLLCK Oscillator Configuration
+// <i> Indicates whether configuration for UPLLCK is enabled or not
+// <id> enable_upllck
+#ifndef CONF_UPLLCK_CONFIG
+#define CONF_UPLLCK_CONFIG 1
+#endif
+
+// <y> UPLLCK Reference Clock Source
+// <XOSC20M"> External 3-20MHz Oscillator (XOSC20M)
+// <i> Select the clock source,only when the input frequency is 12M or 16M, the upllck output is 480M.
+// <id> upllck_ref_clock
+#ifndef CONF_UPLLCK_CLK
+#define CONF_UPLLCK_CLK XOSC20M
+#endif
+
+// <h> UPLLCK Oscillator Control
+// <q> UPLLCK Oscillator Enable
+// <i> Indicates whether UPLLCK Oscillator is enabled or not
+// <id> upllck_arch_enable
+#ifndef CONF_UPLLCK_ENABLE
+#define CONF_UPLLCK_ENABLE 1
+#endif
+// </h>
+// </e>
+
+// <e> UPLLCKDIV Oscillator Configuration
+// <i> Indicates whether configuration for UPLLCKDIV is enabled or not
+// <id> enable_upllckdiv
+#ifndef CONF_UPLLCKDIV_CONFIG
+#define CONF_UPLLCKDIV_CONFIG 1
+#endif
+
+// <y> UPLLCKDIV Reference Clock Source
+// <UPLLCK"> USB 480M Clock (UPLLCK)
+// <i> Select the clock source.
+// <id> upllckdiv_ref_clock
+#ifndef CONF_UPLLCKDIV_CLK
+#define CONF_UPLLCKDIV_CLK UPLLCK
+#endif
+
+// <h> UPLLCKDIV Oscillator Control
+// <o> UPLLCKDIV Clock Divider
+// <0=> 1
+// <1=> 2
+// <i> Select the clock divider.
+// <id> upllckdiv_div
+#ifndef CONF_UPLLCKDIV_DIV
+#define CONF_UPLLCKDIV_DIV 1
+#endif
+// </h>
+// </e>
+
+// <e> MCK/8
+// <id> enable_mck_div_8
+#ifndef CONF_MCK_DIV_8_CONFIG
+#define CONF_MCK_DIV_8_CONFIG 0
+#endif
+
+// <o> MCK/8 Source
+// <0=> Master Clock (MCK)
+// <id> mck_div_8_src
+#ifndef CONF_MCK_DIV_8_SRC
+#define CONF_MCK_DIV_8_SRC 0
+#endif
+// </e>
+
+// <e> External Clock Input Configuration
+// <id> enable_dummy_ext
+#ifndef CONF_DUMMY_EXT_CONFIG
+#define CONF_DUMMY_EXT_CONFIG 1
+#endif
+
+// <o> External Clock Input Source
+// <i> All here are dummy values
+// <i> Refer to the peripherals settings for actual input information
+// <0=> Specific clock input from specific pin
+// <id> dummy_ext_src
+#ifndef CONF_DUMMY_EXT_SRC
+#define CONF_DUMMY_EXT_SRC 0
+#endif
+// </e>
+
+// <e> External Clock Configuration
+// <id> enable_dummy_ext_clk
+#ifndef CONF_DUMMY_EXT_CLK_CONFIG
+#define CONF_DUMMY_EXT_CLK_CONFIG 1
+#endif
+
+// <o> External Clock Source
+// <i> All here are dummy values
+// <i> Refer to the peripherals settings for actual input information
+// <0=> External Clock Input
+// <id> dummy_ext_clk_src
+#ifndef CONF_DUMMY_EXT_CLK_SRC
+#define CONF_DUMMY_EXT_CLK_SRC 0
+#endif
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_PMC_CONFIG_H
diff --git a/hw/bsp/same70_qmtech/hpl_usart_config.h b/hw/bsp/same70_qmtech/hpl_usart_config.h
new file mode 100644
index 000000000..50ca3f15c
--- /dev/null
+++ b/hw/bsp/same70_qmtech/hpl_usart_config.h
@@ -0,0 +1,215 @@
+/* Auto-generated config file hpl_usart_config.h */
+#ifndef HPL_USART_CONFIG_H
+#define HPL_USART_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_USART_1_ENABLE
+#define CONF_USART_1_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Frame parity
+// <0x0=>Even parity
+// <0x1=>Odd parity
+// <0x2=>Parity forced to 0
+// <0x3=>Parity forced to 1
+// <0x4=>No parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_USART_1_PARITY
+#define CONF_USART_1_PARITY 0x4
+#endif
+
+// <o> Character Size
+// <0x0=>5 bits
+// <0x1=>6 bits
+// <0x2=>7 bits
+// <0x3=>8 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_USART_1_CHSIZE
+#define CONF_USART_1_CHSIZE 0x3
+#endif
+
+// <o> Stop Bit
+// <0=>1 stop bit
+// <1=>1.5 stop bits
+// <2=>2 stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_USART_1_SBMODE
+#define CONF_USART_1_SBMODE 0
+#endif
+
+// <o> Clock Output Select
+// <0=>The USART does not drive the SCK pin
+// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK
+// <i> Clock Output Select in USART sck, if in usrt master mode, please drive SCK.
+// <id> usart_clock_output_select
+#ifndef CONF_USART_1_CLKO
+#define CONF_USART_1_CLKO 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_USART_1_BAUD
+#define CONF_USART_1_BAUD 9600
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_USART_1_ADVANCED_CONFIG
+#define CONF_USART_1_ADVANCED_CONFIG 0
+#endif
+
+// <o> Channel Mode
+// <0=>Normal Mode
+// <1=>Automatic Echo
+// <2=>Local Loopback
+// <3=>Remote Loopback
+// <i> Channel mode in USART frame
+// <id> usart_channel_mode
+#ifndef CONF_USART_1_CHMODE
+#define CONF_USART_1_CHMODE 0
+#endif
+
+// <q> 9 bits character enable
+// <i> Enable 9 bits character, this has high priority than 5/6/7/8 bits.
+// <id> usart_9bits_enable
+#ifndef CONF_USART_1_MODE9
+#define CONF_USART_1_MODE9 0
+#endif
+
+// <o> Variable Sync
+// <0=>User defined configuration
+// <1=>sync field is updated when a character is written into US_THR
+// <i> Variable Synchronization of Command/Data Sync Start Frarm Delimiter
+// <id> variable_sync
+#ifndef CONF_USART_1_VAR_SYNC
+#define CONF_USART_1_VAR_SYNC 0
+#endif
+
+// <o> Oversampling Mode
+// <0=>16 Oversampling
+// <1=>8 Oversampling
+// <i> Oversampling Mode in UART mode
+// <id> usart__oversampling_mode
+#ifndef CONF_USART_1_OVER
+#define CONF_USART_1_OVER 0
+#endif
+
+// <o> Inhibit Non Ack
+// <0=>The NACK is generated
+// <1=>The NACK is not generated
+// <i> Inhibit Non Acknowledge
+// <id> usart__inack
+#ifndef CONF_USART_1_INACK
+#define CONF_USART_1_INACK 1
+#endif
+
+// <o> Disable Successive NACK
+// <0=>NACK is sent on the ISO line as soon as a parity error occurs
+// <1=>Many parity errors generate a NACK on the ISO line
+// <i> Disable Successive NACK
+// <id> usart_dsnack
+#ifndef CONF_USART_1_DSNACK
+#define CONF_USART_1_DSNACK 0
+#endif
+
+// <o> Inverted Data
+// <0=>Data isn't inverted, nomal mode
+// <1=>Data is inverted
+// <i> Inverted Data
+// <id> usart_invdata
+#ifndef CONF_USART_1_INVDATA
+#define CONF_USART_1_INVDATA 0
+#endif
+
+// <o> Maximum Number of Automatic Iteration <0-7>
+// <i> Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
+// <id> usart_max_iteration
+#ifndef CONF_USART_1_MAX_ITERATION
+#define CONF_USART_1_MAX_ITERATION 0
+#endif
+
+// <q> Receive Line Filter enable
+// <i> whether the USART filters the receive line using a three-sample filter
+// <id> usart_receive_filter_enable
+#ifndef CONF_USART_1_FILTER
+#define CONF_USART_1_FILTER 0
+#endif
+
+// <q> Manchester Encoder/Decoder Enable
+// <i> whether the USART Manchester Encoder/Decoder
+// <id> usart_manchester_filter_enable
+#ifndef CONF_USART_1_MAN
+#define CONF_USART_1_MAN 0
+#endif
+
+// <o> Manchester Synchronization Mode
+// <0=>The Manchester start bit is a 0 to 1 transition
+// <1=>The Manchester start bit is a 1 to 0 transition
+// <i> Manchester Synchronization Mode
+// <id> usart_manchester_synchronization_mode
+#ifndef CONF_USART_1_MODSYNC
+#define CONF_USART_1_MODSYNC 0
+#endif
+
+// <o> Start Frame Delimiter Selector
+// <0=>Start frame delimiter is COMMAND or DATA SYNC
+// <1=>Start frame delimiter is one bit
+// <i> Start Frame Delimiter Selector
+// <id> usart_start_frame_delimiter
+#ifndef CONF_USART_1_ONEBIT
+#define CONF_USART_1_ONEBIT 0
+#endif
+
+// <o> Fractional Part <0-7>
+// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
+// <id> usart_arch_fractional
+#ifndef CONF_USART_1_FRACTIONAL
+#define CONF_USART_1_FRACTIONAL 0x0
+#endif
+
+// <o> Data Order
+// <0=>LSB is transmitted first
+// <1=>MSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_msbf
+#ifndef CONF_USART_1_MSBF
+#define CONF_USART_1_MSBF 0
+#endif
+
+// </e>
+
+#define CONF_USART_1_MODE 0x0
+
+// Calculate BAUD register value in UART mode
+#if CONF_USART1_CK_SRC < 3
+#ifndef CONF_USART_1_BAUD_CD
+#define CONF_USART_1_BAUD_CD ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / 8 / (2 - CONF_USART_1_OVER))
+#endif
+#ifndef CONF_USART_1_BAUD_FP
+#define CONF_USART_1_BAUD_FP                                                                                           \
+	((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / (2 - CONF_USART_1_OVER) - 8 * CONF_USART_1_BAUD_CD)
+#endif
+#elif CONF_USART1_CK_SRC == 3
+// No division is active. The value written in US_BRGR has no effect.
+#ifndef CONF_USART_1_BAUD_CD
+#define CONF_USART_1_BAUD_CD 1
+#endif
+#ifndef CONF_USART_1_BAUD_FP
+#define CONF_USART_1_BAUD_FP 1
+#endif
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // HPL_USART_CONFIG_H
diff --git a/hw/bsp/same70_qmtech/hpl_xdmac_config.h b/hw/bsp/same70_qmtech/hpl_xdmac_config.h
new file mode 100644
index 000000000..a3d62c6fc
--- /dev/null
+++ b/hw/bsp/same70_qmtech/hpl_xdmac_config.h
@@ -0,0 +1,4400 @@
+/* Auto-generated config file hpl_xdmac_config.h */
+#ifndef HPL_XDMAC_CONFIG_H
+#define HPL_XDMAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <e> XDMAC enable
+// <i> Indicates whether xdmac is enabled or not
+// <id> xdmac_enable
+#ifndef CONF_DMA_ENABLE
+#define CONF_DMA_ENABLE 0
+#endif
+
+// <e> Channel 0 settings
+// <id> dmac_channel_0_settings
+#ifndef CONF_DMAC_CHANNEL_0_SETTINGS
+#define CONF_DMAC_CHANNEL_0_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_0
+#ifndef CONF_DMAC_BURSTSIZE_0
+#define CONF_DMAC_BURSTSIZE_0 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_0
+#ifndef CONF_DMAC_CHUNKSIZE_0
+#define CONF_DMAC_CHUNKSIZE_0 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_0
+#ifndef CONF_DMAC_BEATSIZE_0
+#define CONF_DMAC_BEATSIZE_0 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_0
+#ifndef CONF_DMAC_SRC_INTERFACE_0
+#define CONF_DMAC_SRC_INTERFACE_0 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_0
+#ifndef CONF_DMAC_DES_INTERFACE_0
+#define CONF_DMAC_DES_INTERFACE_0 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_0
+#ifndef CONF_DMAC_SRCINC_0
+#define CONF_DMAC_SRCINC_0 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_0
+#ifndef CONF_DMAC_DSTINC_0
+#define CONF_DMAC_DSTINC_0 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_0
+#ifndef CONF_DMAC_TRANS_TYPE_0
+#define CONF_DMAC_TRANS_TYPE_0 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_0
+#ifndef CONF_DMAC_TRIGSRC_0
+#define CONF_DMAC_TRIGSRC_0 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_0 == 0
+#define CONF_DMAC_TYPE_0 0
+#define CONF_DMAC_DSYNC_0 0
+#elif CONF_DMAC_TRANS_TYPE_0 == 1
+#define CONF_DMAC_TYPE_0 1
+#define CONF_DMAC_DSYNC_0 0
+#elif CONF_DMAC_TRANS_TYPE_0 == 2
+#define CONF_DMAC_TYPE_0 1
+#define CONF_DMAC_DSYNC_0 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_0 == 0xFF
+#define CONF_DMAC_SWREQ_0 1
+#else
+#define CONF_DMAC_SWREQ_0 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_0_SETTINGS == 1 && CONF_DMAC_BEATSIZE_0 != 2 && ((!CONF_DMAC_SRCINC_0) || (!CONF_DMAC_DSTINC_0)))
+#if (!CONF_DMAC_SRCINC_0)
+#define CONF_DMAC_SRC_STRIDE_0 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_0)
+#define CONF_DMAC_DES_STRIDE_0 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_0
+#define CONF_DMAC_SRC_STRIDE_0 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_0
+#define CONF_DMAC_DES_STRIDE_0 0
+#endif
+
+// <e> Channel 1 settings
+// <id> dmac_channel_1_settings
+#ifndef CONF_DMAC_CHANNEL_1_SETTINGS
+#define CONF_DMAC_CHANNEL_1_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_1
+#ifndef CONF_DMAC_BURSTSIZE_1
+#define CONF_DMAC_BURSTSIZE_1 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_1
+#ifndef CONF_DMAC_CHUNKSIZE_1
+#define CONF_DMAC_CHUNKSIZE_1 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_1
+#ifndef CONF_DMAC_BEATSIZE_1
+#define CONF_DMAC_BEATSIZE_1 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_1
+#ifndef CONF_DMAC_SRC_INTERFACE_1
+#define CONF_DMAC_SRC_INTERFACE_1 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_1
+#ifndef CONF_DMAC_DES_INTERFACE_1
+#define CONF_DMAC_DES_INTERFACE_1 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_1
+#ifndef CONF_DMAC_SRCINC_1
+#define CONF_DMAC_SRCINC_1 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_1
+#ifndef CONF_DMAC_DSTINC_1
+#define CONF_DMAC_DSTINC_1 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_1
+#ifndef CONF_DMAC_TRANS_TYPE_1
+#define CONF_DMAC_TRANS_TYPE_1 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_1
+#ifndef CONF_DMAC_TRIGSRC_1
+#define CONF_DMAC_TRIGSRC_1 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_1 == 0
+#define CONF_DMAC_TYPE_1 0
+#define CONF_DMAC_DSYNC_1 0
+#elif CONF_DMAC_TRANS_TYPE_1 == 1
+#define CONF_DMAC_TYPE_1 1
+#define CONF_DMAC_DSYNC_1 0
+#elif CONF_DMAC_TRANS_TYPE_1 == 2
+#define CONF_DMAC_TYPE_1 1
+#define CONF_DMAC_DSYNC_1 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_1 == 0xFF
+#define CONF_DMAC_SWREQ_1 1
+#else
+#define CONF_DMAC_SWREQ_1 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_1_SETTINGS == 1 && CONF_DMAC_BEATSIZE_1 != 2 && ((!CONF_DMAC_SRCINC_1) || (!CONF_DMAC_DSTINC_1)))
+#if (!CONF_DMAC_SRCINC_1)
+#define CONF_DMAC_SRC_STRIDE_1 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_1)
+#define CONF_DMAC_DES_STRIDE_1 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_1
+#define CONF_DMAC_SRC_STRIDE_1 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_1
+#define CONF_DMAC_DES_STRIDE_1 0
+#endif
+
+// <e> Channel 2 settings
+// <id> dmac_channel_2_settings
+#ifndef CONF_DMAC_CHANNEL_2_SETTINGS
+#define CONF_DMAC_CHANNEL_2_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_2
+#ifndef CONF_DMAC_BURSTSIZE_2
+#define CONF_DMAC_BURSTSIZE_2 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_2
+#ifndef CONF_DMAC_CHUNKSIZE_2
+#define CONF_DMAC_CHUNKSIZE_2 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_2
+#ifndef CONF_DMAC_BEATSIZE_2
+#define CONF_DMAC_BEATSIZE_2 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_2
+#ifndef CONF_DMAC_SRC_INTERFACE_2
+#define CONF_DMAC_SRC_INTERFACE_2 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_2
+#ifndef CONF_DMAC_DES_INTERFACE_2
+#define CONF_DMAC_DES_INTERFACE_2 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_2
+#ifndef CONF_DMAC_SRCINC_2
+#define CONF_DMAC_SRCINC_2 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_2
+#ifndef CONF_DMAC_DSTINC_2
+#define CONF_DMAC_DSTINC_2 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_2
+#ifndef CONF_DMAC_TRANS_TYPE_2
+#define CONF_DMAC_TRANS_TYPE_2 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_2
+#ifndef CONF_DMAC_TRIGSRC_2
+#define CONF_DMAC_TRIGSRC_2 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_2 == 0
+#define CONF_DMAC_TYPE_2 0
+#define CONF_DMAC_DSYNC_2 0
+#elif CONF_DMAC_TRANS_TYPE_2 == 1
+#define CONF_DMAC_TYPE_2 1
+#define CONF_DMAC_DSYNC_2 0
+#elif CONF_DMAC_TRANS_TYPE_2 == 2
+#define CONF_DMAC_TYPE_2 1
+#define CONF_DMAC_DSYNC_2 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_2 == 0xFF
+#define CONF_DMAC_SWREQ_2 1
+#else
+#define CONF_DMAC_SWREQ_2 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_2_SETTINGS == 1 && CONF_DMAC_BEATSIZE_2 != 2 && ((!CONF_DMAC_SRCINC_2) || (!CONF_DMAC_DSTINC_2)))
+#if (!CONF_DMAC_SRCINC_2)
+#define CONF_DMAC_SRC_STRIDE_2 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_2)
+#define CONF_DMAC_DES_STRIDE_2 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_2
+#define CONF_DMAC_SRC_STRIDE_2 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_2
+#define CONF_DMAC_DES_STRIDE_2 0
+#endif
+
+// <e> Channel 3 settings
+// <id> dmac_channel_3_settings
+#ifndef CONF_DMAC_CHANNEL_3_SETTINGS
+#define CONF_DMAC_CHANNEL_3_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_3
+#ifndef CONF_DMAC_BURSTSIZE_3
+#define CONF_DMAC_BURSTSIZE_3 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_3
+#ifndef CONF_DMAC_CHUNKSIZE_3
+#define CONF_DMAC_CHUNKSIZE_3 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_3
+#ifndef CONF_DMAC_BEATSIZE_3
+#define CONF_DMAC_BEATSIZE_3 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_3
+#ifndef CONF_DMAC_SRC_INTERFACE_3
+#define CONF_DMAC_SRC_INTERFACE_3 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_3
+#ifndef CONF_DMAC_DES_INTERFACE_3
+#define CONF_DMAC_DES_INTERFACE_3 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_3
+#ifndef CONF_DMAC_SRCINC_3
+#define CONF_DMAC_SRCINC_3 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_3
+#ifndef CONF_DMAC_DSTINC_3
+#define CONF_DMAC_DSTINC_3 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_3
+#ifndef CONF_DMAC_TRANS_TYPE_3
+#define CONF_DMAC_TRANS_TYPE_3 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_3
+#ifndef CONF_DMAC_TRIGSRC_3
+#define CONF_DMAC_TRIGSRC_3 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_3 == 0
+#define CONF_DMAC_TYPE_3 0
+#define CONF_DMAC_DSYNC_3 0
+#elif CONF_DMAC_TRANS_TYPE_3 == 1
+#define CONF_DMAC_TYPE_3 1
+#define CONF_DMAC_DSYNC_3 0
+#elif CONF_DMAC_TRANS_TYPE_3 == 2
+#define CONF_DMAC_TYPE_3 1
+#define CONF_DMAC_DSYNC_3 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_3 == 0xFF
+#define CONF_DMAC_SWREQ_3 1
+#else
+#define CONF_DMAC_SWREQ_3 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_3_SETTINGS == 1 && CONF_DMAC_BEATSIZE_3 != 2 && ((!CONF_DMAC_SRCINC_3) || (!CONF_DMAC_DSTINC_3)))
+#if (!CONF_DMAC_SRCINC_3)
+#define CONF_DMAC_SRC_STRIDE_3 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_3)
+#define CONF_DMAC_DES_STRIDE_3 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_3
+#define CONF_DMAC_SRC_STRIDE_3 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_3
+#define CONF_DMAC_DES_STRIDE_3 0
+#endif
+
+// <e> Channel 4 settings
+// <id> dmac_channel_4_settings
+#ifndef CONF_DMAC_CHANNEL_4_SETTINGS
+#define CONF_DMAC_CHANNEL_4_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_4
+#ifndef CONF_DMAC_BURSTSIZE_4
+#define CONF_DMAC_BURSTSIZE_4 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_4
+#ifndef CONF_DMAC_CHUNKSIZE_4
+#define CONF_DMAC_CHUNKSIZE_4 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_4
+#ifndef CONF_DMAC_BEATSIZE_4
+#define CONF_DMAC_BEATSIZE_4 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_4
+#ifndef CONF_DMAC_SRC_INTERFACE_4
+#define CONF_DMAC_SRC_INTERFACE_4 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_4
+#ifndef CONF_DMAC_DES_INTERFACE_4
+#define CONF_DMAC_DES_INTERFACE_4 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_4
+#ifndef CONF_DMAC_SRCINC_4
+#define CONF_DMAC_SRCINC_4 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_4
+#ifndef CONF_DMAC_DSTINC_4
+#define CONF_DMAC_DSTINC_4 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_4
+#ifndef CONF_DMAC_TRANS_TYPE_4
+#define CONF_DMAC_TRANS_TYPE_4 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_4
+#ifndef CONF_DMAC_TRIGSRC_4
+#define CONF_DMAC_TRIGSRC_4 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_4 == 0
+#define CONF_DMAC_TYPE_4 0
+#define CONF_DMAC_DSYNC_4 0
+#elif CONF_DMAC_TRANS_TYPE_4 == 1
+#define CONF_DMAC_TYPE_4 1
+#define CONF_DMAC_DSYNC_4 0
+#elif CONF_DMAC_TRANS_TYPE_4 == 2
+#define CONF_DMAC_TYPE_4 1
+#define CONF_DMAC_DSYNC_4 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_4 == 0xFF
+#define CONF_DMAC_SWREQ_4 1
+#else
+#define CONF_DMAC_SWREQ_4 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_4_SETTINGS == 1 && CONF_DMAC_BEATSIZE_4 != 2 && ((!CONF_DMAC_SRCINC_4) || (!CONF_DMAC_DSTINC_4)))
+#if (!CONF_DMAC_SRCINC_4)
+#define CONF_DMAC_SRC_STRIDE_4 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_4)
+#define CONF_DMAC_DES_STRIDE_4 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_4
+#define CONF_DMAC_SRC_STRIDE_4 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_4
+#define CONF_DMAC_DES_STRIDE_4 0
+#endif
+
+// <e> Channel 5 settings
+// <id> dmac_channel_5_settings
+#ifndef CONF_DMAC_CHANNEL_5_SETTINGS
+#define CONF_DMAC_CHANNEL_5_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_5
+#ifndef CONF_DMAC_BURSTSIZE_5
+#define CONF_DMAC_BURSTSIZE_5 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_5
+#ifndef CONF_DMAC_CHUNKSIZE_5
+#define CONF_DMAC_CHUNKSIZE_5 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_5
+#ifndef CONF_DMAC_BEATSIZE_5
+#define CONF_DMAC_BEATSIZE_5 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_5
+#ifndef CONF_DMAC_SRC_INTERFACE_5
+#define CONF_DMAC_SRC_INTERFACE_5 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_5
+#ifndef CONF_DMAC_DES_INTERFACE_5
+#define CONF_DMAC_DES_INTERFACE_5 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_5
+#ifndef CONF_DMAC_SRCINC_5
+#define CONF_DMAC_SRCINC_5 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_5
+#ifndef CONF_DMAC_DSTINC_5
+#define CONF_DMAC_DSTINC_5 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_5
+#ifndef CONF_DMAC_TRANS_TYPE_5
+#define CONF_DMAC_TRANS_TYPE_5 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_5
+#ifndef CONF_DMAC_TRIGSRC_5
+#define CONF_DMAC_TRIGSRC_5 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_5 == 0
+#define CONF_DMAC_TYPE_5 0
+#define CONF_DMAC_DSYNC_5 0
+#elif CONF_DMAC_TRANS_TYPE_5 == 1
+#define CONF_DMAC_TYPE_5 1
+#define CONF_DMAC_DSYNC_5 0
+#elif CONF_DMAC_TRANS_TYPE_5 == 2
+#define CONF_DMAC_TYPE_5 1
+#define CONF_DMAC_DSYNC_5 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_5 == 0xFF
+#define CONF_DMAC_SWREQ_5 1
+#else
+#define CONF_DMAC_SWREQ_5 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_5_SETTINGS == 1 && CONF_DMAC_BEATSIZE_5 != 2 && ((!CONF_DMAC_SRCINC_5) || (!CONF_DMAC_DSTINC_5)))
+#if (!CONF_DMAC_SRCINC_5)
+#define CONF_DMAC_SRC_STRIDE_5 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_5)
+#define CONF_DMAC_DES_STRIDE_5 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_5
+#define CONF_DMAC_SRC_STRIDE_5 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_5
+#define CONF_DMAC_DES_STRIDE_5 0
+#endif
+
+// <e> Channel 6 settings
+// <id> dmac_channel_6_settings
+#ifndef CONF_DMAC_CHANNEL_6_SETTINGS
+#define CONF_DMAC_CHANNEL_6_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_6
+#ifndef CONF_DMAC_BURSTSIZE_6
+#define CONF_DMAC_BURSTSIZE_6 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_6
+#ifndef CONF_DMAC_CHUNKSIZE_6
+#define CONF_DMAC_CHUNKSIZE_6 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_6
+#ifndef CONF_DMAC_BEATSIZE_6
+#define CONF_DMAC_BEATSIZE_6 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_6
+#ifndef CONF_DMAC_SRC_INTERFACE_6
+#define CONF_DMAC_SRC_INTERFACE_6 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_6
+#ifndef CONF_DMAC_DES_INTERFACE_6
+#define CONF_DMAC_DES_INTERFACE_6 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_6
+#ifndef CONF_DMAC_SRCINC_6
+#define CONF_DMAC_SRCINC_6 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_6
+#ifndef CONF_DMAC_DSTINC_6
+#define CONF_DMAC_DSTINC_6 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_6
+#ifndef CONF_DMAC_TRANS_TYPE_6
+#define CONF_DMAC_TRANS_TYPE_6 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_6
+#ifndef CONF_DMAC_TRIGSRC_6
+#define CONF_DMAC_TRIGSRC_6 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_6 == 0
+#define CONF_DMAC_TYPE_6 0
+#define CONF_DMAC_DSYNC_6 0
+#elif CONF_DMAC_TRANS_TYPE_6 == 1
+#define CONF_DMAC_TYPE_6 1
+#define CONF_DMAC_DSYNC_6 0
+#elif CONF_DMAC_TRANS_TYPE_6 == 2
+#define CONF_DMAC_TYPE_6 1
+#define CONF_DMAC_DSYNC_6 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_6 == 0xFF
+#define CONF_DMAC_SWREQ_6 1
+#else
+#define CONF_DMAC_SWREQ_6 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_6_SETTINGS == 1 && CONF_DMAC_BEATSIZE_6 != 2 && ((!CONF_DMAC_SRCINC_6) || (!CONF_DMAC_DSTINC_6)))
+#if (!CONF_DMAC_SRCINC_6)
+#define CONF_DMAC_SRC_STRIDE_6 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_6)
+#define CONF_DMAC_DES_STRIDE_6 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_6
+#define CONF_DMAC_SRC_STRIDE_6 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_6
+#define CONF_DMAC_DES_STRIDE_6 0
+#endif
+
+// <e> Channel 7 settings
+// <id> dmac_channel_7_settings
+#ifndef CONF_DMAC_CHANNEL_7_SETTINGS
+#define CONF_DMAC_CHANNEL_7_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_7
+#ifndef CONF_DMAC_BURSTSIZE_7
+#define CONF_DMAC_BURSTSIZE_7 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_7
+#ifndef CONF_DMAC_CHUNKSIZE_7
+#define CONF_DMAC_CHUNKSIZE_7 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_7
+#ifndef CONF_DMAC_BEATSIZE_7
+#define CONF_DMAC_BEATSIZE_7 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_7
+#ifndef CONF_DMAC_SRC_INTERFACE_7
+#define CONF_DMAC_SRC_INTERFACE_7 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_7
+#ifndef CONF_DMAC_DES_INTERFACE_7
+#define CONF_DMAC_DES_INTERFACE_7 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_7
+#ifndef CONF_DMAC_SRCINC_7
+#define CONF_DMAC_SRCINC_7 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_7
+#ifndef CONF_DMAC_DSTINC_7
+#define CONF_DMAC_DSTINC_7 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_7
+#ifndef CONF_DMAC_TRANS_TYPE_7
+#define CONF_DMAC_TRANS_TYPE_7 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_7
+#ifndef CONF_DMAC_TRIGSRC_7
+#define CONF_DMAC_TRIGSRC_7 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_7 == 0
+#define CONF_DMAC_TYPE_7 0
+#define CONF_DMAC_DSYNC_7 0
+#elif CONF_DMAC_TRANS_TYPE_7 == 1
+#define CONF_DMAC_TYPE_7 1
+#define CONF_DMAC_DSYNC_7 0
+#elif CONF_DMAC_TRANS_TYPE_7 == 2
+#define CONF_DMAC_TYPE_7 1
+#define CONF_DMAC_DSYNC_7 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_7 == 0xFF
+#define CONF_DMAC_SWREQ_7 1
+#else
+#define CONF_DMAC_SWREQ_7 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_7_SETTINGS == 1 && CONF_DMAC_BEATSIZE_7 != 2 && ((!CONF_DMAC_SRCINC_7) || (!CONF_DMAC_DSTINC_7)))
+#if (!CONF_DMAC_SRCINC_7)
+#define CONF_DMAC_SRC_STRIDE_7 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_7)
+#define CONF_DMAC_DES_STRIDE_7 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_7
+#define CONF_DMAC_SRC_STRIDE_7 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_7
+#define CONF_DMAC_DES_STRIDE_7 0
+#endif
+
+// <e> Channel 8 settings
+// <id> dmac_channel_8_settings
+#ifndef CONF_DMAC_CHANNEL_8_SETTINGS
+#define CONF_DMAC_CHANNEL_8_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_8
+#ifndef CONF_DMAC_BURSTSIZE_8
+#define CONF_DMAC_BURSTSIZE_8 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_8
+#ifndef CONF_DMAC_CHUNKSIZE_8
+#define CONF_DMAC_CHUNKSIZE_8 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_8
+#ifndef CONF_DMAC_BEATSIZE_8
+#define CONF_DMAC_BEATSIZE_8 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_8
+#ifndef CONF_DMAC_SRC_INTERFACE_8
+#define CONF_DMAC_SRC_INTERFACE_8 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_8
+#ifndef CONF_DMAC_DES_INTERFACE_8
+#define CONF_DMAC_DES_INTERFACE_8 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_8
+#ifndef CONF_DMAC_SRCINC_8
+#define CONF_DMAC_SRCINC_8 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_8
+#ifndef CONF_DMAC_DSTINC_8
+#define CONF_DMAC_DSTINC_8 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_8
+#ifndef CONF_DMAC_TRANS_TYPE_8
+#define CONF_DMAC_TRANS_TYPE_8 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_8
+#ifndef CONF_DMAC_TRIGSRC_8
+#define CONF_DMAC_TRIGSRC_8 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_8 == 0
+#define CONF_DMAC_TYPE_8 0
+#define CONF_DMAC_DSYNC_8 0
+#elif CONF_DMAC_TRANS_TYPE_8 == 1
+#define CONF_DMAC_TYPE_8 1
+#define CONF_DMAC_DSYNC_8 0
+#elif CONF_DMAC_TRANS_TYPE_8 == 2
+#define CONF_DMAC_TYPE_8 1
+#define CONF_DMAC_DSYNC_8 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_8 == 0xFF
+#define CONF_DMAC_SWREQ_8 1
+#else
+#define CONF_DMAC_SWREQ_8 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_8_SETTINGS == 1 && CONF_DMAC_BEATSIZE_8 != 2 && ((!CONF_DMAC_SRCINC_8) || (!CONF_DMAC_DSTINC_8)))
+#if (!CONF_DMAC_SRCINC_8)
+#define CONF_DMAC_SRC_STRIDE_8 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_8)
+#define CONF_DMAC_DES_STRIDE_8 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_8
+#define CONF_DMAC_SRC_STRIDE_8 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_8
+#define CONF_DMAC_DES_STRIDE_8 0
+#endif
+
+// <e> Channel 9 settings
+// <id> dmac_channel_9_settings
+#ifndef CONF_DMAC_CHANNEL_9_SETTINGS
+#define CONF_DMAC_CHANNEL_9_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_9
+#ifndef CONF_DMAC_BURSTSIZE_9
+#define CONF_DMAC_BURSTSIZE_9 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_9
+#ifndef CONF_DMAC_CHUNKSIZE_9
+#define CONF_DMAC_CHUNKSIZE_9 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_9
+#ifndef CONF_DMAC_BEATSIZE_9
+#define CONF_DMAC_BEATSIZE_9 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_9
+#ifndef CONF_DMAC_SRC_INTERFACE_9
+#define CONF_DMAC_SRC_INTERFACE_9 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_9
+#ifndef CONF_DMAC_DES_INTERFACE_9
+#define CONF_DMAC_DES_INTERFACE_9 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_9
+#ifndef CONF_DMAC_SRCINC_9
+#define CONF_DMAC_SRCINC_9 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_9
+#ifndef CONF_DMAC_DSTINC_9
+#define CONF_DMAC_DSTINC_9 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_9
+#ifndef CONF_DMAC_TRANS_TYPE_9
+#define CONF_DMAC_TRANS_TYPE_9 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_9
+#ifndef CONF_DMAC_TRIGSRC_9
+#define CONF_DMAC_TRIGSRC_9 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_9 == 0
+#define CONF_DMAC_TYPE_9 0
+#define CONF_DMAC_DSYNC_9 0
+#elif CONF_DMAC_TRANS_TYPE_9 == 1
+#define CONF_DMAC_TYPE_9 1
+#define CONF_DMAC_DSYNC_9 0
+#elif CONF_DMAC_TRANS_TYPE_9 == 2
+#define CONF_DMAC_TYPE_9 1
+#define CONF_DMAC_DSYNC_9 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_9 == 0xFF
+#define CONF_DMAC_SWREQ_9 1
+#else
+#define CONF_DMAC_SWREQ_9 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_9_SETTINGS == 1 && CONF_DMAC_BEATSIZE_9 != 2 && ((!CONF_DMAC_SRCINC_9) || (!CONF_DMAC_DSTINC_9)))
+#if (!CONF_DMAC_SRCINC_9)
+#define CONF_DMAC_SRC_STRIDE_9 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_9)
+#define CONF_DMAC_DES_STRIDE_9 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_9
+#define CONF_DMAC_SRC_STRIDE_9 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_9
+#define CONF_DMAC_DES_STRIDE_9 0
+#endif
+
+// <e> Channel 10 settings
+// <id> dmac_channel_10_settings
+#ifndef CONF_DMAC_CHANNEL_10_SETTINGS
+#define CONF_DMAC_CHANNEL_10_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_10
+#ifndef CONF_DMAC_BURSTSIZE_10
+#define CONF_DMAC_BURSTSIZE_10 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_10
+#ifndef CONF_DMAC_CHUNKSIZE_10
+#define CONF_DMAC_CHUNKSIZE_10 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_10
+#ifndef CONF_DMAC_BEATSIZE_10
+#define CONF_DMAC_BEATSIZE_10 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_10
+#ifndef CONF_DMAC_SRC_INTERFACE_10
+#define CONF_DMAC_SRC_INTERFACE_10 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_10
+#ifndef CONF_DMAC_DES_INTERFACE_10
+#define CONF_DMAC_DES_INTERFACE_10 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_10
+#ifndef CONF_DMAC_SRCINC_10
+#define CONF_DMAC_SRCINC_10 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_10
+#ifndef CONF_DMAC_DSTINC_10
+#define CONF_DMAC_DSTINC_10 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_10
+#ifndef CONF_DMAC_TRANS_TYPE_10
+#define CONF_DMAC_TRANS_TYPE_10 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_10
+#ifndef CONF_DMAC_TRIGSRC_10
+#define CONF_DMAC_TRIGSRC_10 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_10 == 0
+#define CONF_DMAC_TYPE_10 0
+#define CONF_DMAC_DSYNC_10 0
+#elif CONF_DMAC_TRANS_TYPE_10 == 1
+#define CONF_DMAC_TYPE_10 1
+#define CONF_DMAC_DSYNC_10 0
+#elif CONF_DMAC_TRANS_TYPE_10 == 2
+#define CONF_DMAC_TYPE_10 1
+#define CONF_DMAC_DSYNC_10 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_10 == 0xFF
+#define CONF_DMAC_SWREQ_10 1
+#else
+#define CONF_DMAC_SWREQ_10 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_10_SETTINGS == 1 && CONF_DMAC_BEATSIZE_10 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_10) || (!CONF_DMAC_DSTINC_10)))
+#if (!CONF_DMAC_SRCINC_10)
+#define CONF_DMAC_SRC_STRIDE_10 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_10)
+#define CONF_DMAC_DES_STRIDE_10 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_10
+#define CONF_DMAC_SRC_STRIDE_10 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_10
+#define CONF_DMAC_DES_STRIDE_10 0
+#endif
+
+// <e> Channel 11 settings
+// <id> dmac_channel_11_settings
+#ifndef CONF_DMAC_CHANNEL_11_SETTINGS
+#define CONF_DMAC_CHANNEL_11_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_11
+#ifndef CONF_DMAC_BURSTSIZE_11
+#define CONF_DMAC_BURSTSIZE_11 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_11
+#ifndef CONF_DMAC_CHUNKSIZE_11
+#define CONF_DMAC_CHUNKSIZE_11 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_11
+#ifndef CONF_DMAC_BEATSIZE_11
+#define CONF_DMAC_BEATSIZE_11 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_11
+#ifndef CONF_DMAC_SRC_INTERFACE_11
+#define CONF_DMAC_SRC_INTERFACE_11 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_11
+#ifndef CONF_DMAC_DES_INTERFACE_11
+#define CONF_DMAC_DES_INTERFACE_11 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_11
+#ifndef CONF_DMAC_SRCINC_11
+#define CONF_DMAC_SRCINC_11 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_11
+#ifndef CONF_DMAC_DSTINC_11
+#define CONF_DMAC_DSTINC_11 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_11
+#ifndef CONF_DMAC_TRANS_TYPE_11
+#define CONF_DMAC_TRANS_TYPE_11 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_11
+#ifndef CONF_DMAC_TRIGSRC_11
+#define CONF_DMAC_TRIGSRC_11 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_11 == 0
+#define CONF_DMAC_TYPE_11 0
+#define CONF_DMAC_DSYNC_11 0
+#elif CONF_DMAC_TRANS_TYPE_11 == 1
+#define CONF_DMAC_TYPE_11 1
+#define CONF_DMAC_DSYNC_11 0
+#elif CONF_DMAC_TRANS_TYPE_11 == 2
+#define CONF_DMAC_TYPE_11 1
+#define CONF_DMAC_DSYNC_11 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_11 == 0xFF
+#define CONF_DMAC_SWREQ_11 1
+#else
+#define CONF_DMAC_SWREQ_11 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_11_SETTINGS == 1 && CONF_DMAC_BEATSIZE_11 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_11) || (!CONF_DMAC_DSTINC_11)))
+#if (!CONF_DMAC_SRCINC_11)
+#define CONF_DMAC_SRC_STRIDE_11 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_11)
+#define CONF_DMAC_DES_STRIDE_11 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_11
+#define CONF_DMAC_SRC_STRIDE_11 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_11
+#define CONF_DMAC_DES_STRIDE_11 0
+#endif
+
+// <e> Channel 12 settings
+// <id> dmac_channel_12_settings
+#ifndef CONF_DMAC_CHANNEL_12_SETTINGS
+#define CONF_DMAC_CHANNEL_12_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_12
+#ifndef CONF_DMAC_BURSTSIZE_12
+#define CONF_DMAC_BURSTSIZE_12 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_12
+#ifndef CONF_DMAC_CHUNKSIZE_12
+#define CONF_DMAC_CHUNKSIZE_12 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_12
+#ifndef CONF_DMAC_BEATSIZE_12
+#define CONF_DMAC_BEATSIZE_12 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_12
+#ifndef CONF_DMAC_SRC_INTERFACE_12
+#define CONF_DMAC_SRC_INTERFACE_12 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_12
+#ifndef CONF_DMAC_DES_INTERFACE_12
+#define CONF_DMAC_DES_INTERFACE_12 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_12
+#ifndef CONF_DMAC_SRCINC_12
+#define CONF_DMAC_SRCINC_12 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_12
+#ifndef CONF_DMAC_DSTINC_12
+#define CONF_DMAC_DSTINC_12 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_12
+#ifndef CONF_DMAC_TRANS_TYPE_12
+#define CONF_DMAC_TRANS_TYPE_12 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_12
+#ifndef CONF_DMAC_TRIGSRC_12
+#define CONF_DMAC_TRIGSRC_12 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_12 == 0
+#define CONF_DMAC_TYPE_12 0
+#define CONF_DMAC_DSYNC_12 0
+#elif CONF_DMAC_TRANS_TYPE_12 == 1
+#define CONF_DMAC_TYPE_12 1
+#define CONF_DMAC_DSYNC_12 0
+#elif CONF_DMAC_TRANS_TYPE_12 == 2
+#define CONF_DMAC_TYPE_12 1
+#define CONF_DMAC_DSYNC_12 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_12 == 0xFF
+#define CONF_DMAC_SWREQ_12 1
+#else
+#define CONF_DMAC_SWREQ_12 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_12_SETTINGS == 1 && CONF_DMAC_BEATSIZE_12 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_12) || (!CONF_DMAC_DSTINC_12)))
+#if (!CONF_DMAC_SRCINC_12)
+#define CONF_DMAC_SRC_STRIDE_12 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_12)
+#define CONF_DMAC_DES_STRIDE_12 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_12
+#define CONF_DMAC_SRC_STRIDE_12 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_12
+#define CONF_DMAC_DES_STRIDE_12 0
+#endif
+
+// <e> Channel 13 settings
+// <id> dmac_channel_13_settings
+#ifndef CONF_DMAC_CHANNEL_13_SETTINGS
+#define CONF_DMAC_CHANNEL_13_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_13
+#ifndef CONF_DMAC_BURSTSIZE_13
+#define CONF_DMAC_BURSTSIZE_13 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_13
+#ifndef CONF_DMAC_CHUNKSIZE_13
+#define CONF_DMAC_CHUNKSIZE_13 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_13
+#ifndef CONF_DMAC_BEATSIZE_13
+#define CONF_DMAC_BEATSIZE_13 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_13
+#ifndef CONF_DMAC_SRC_INTERFACE_13
+#define CONF_DMAC_SRC_INTERFACE_13 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_13
+#ifndef CONF_DMAC_DES_INTERFACE_13
+#define CONF_DMAC_DES_INTERFACE_13 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_13
+#ifndef CONF_DMAC_SRCINC_13
+#define CONF_DMAC_SRCINC_13 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_13
+#ifndef CONF_DMAC_DSTINC_13
+#define CONF_DMAC_DSTINC_13 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_13
+#ifndef CONF_DMAC_TRANS_TYPE_13
+#define CONF_DMAC_TRANS_TYPE_13 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_13
+#ifndef CONF_DMAC_TRIGSRC_13
+#define CONF_DMAC_TRIGSRC_13 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_13 == 0
+#define CONF_DMAC_TYPE_13 0
+#define CONF_DMAC_DSYNC_13 0
+#elif CONF_DMAC_TRANS_TYPE_13 == 1
+#define CONF_DMAC_TYPE_13 1
+#define CONF_DMAC_DSYNC_13 0
+#elif CONF_DMAC_TRANS_TYPE_13 == 2
+#define CONF_DMAC_TYPE_13 1
+#define CONF_DMAC_DSYNC_13 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_13 == 0xFF
+#define CONF_DMAC_SWREQ_13 1
+#else
+#define CONF_DMAC_SWREQ_13 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_13_SETTINGS == 1 && CONF_DMAC_BEATSIZE_13 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_13) || (!CONF_DMAC_DSTINC_13)))
+#if (!CONF_DMAC_SRCINC_13)
+#define CONF_DMAC_SRC_STRIDE_13 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_13)
+#define CONF_DMAC_DES_STRIDE_13 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_13
+#define CONF_DMAC_SRC_STRIDE_13 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_13
+#define CONF_DMAC_DES_STRIDE_13 0
+#endif
+
+// <e> Channel 14 settings
+// <id> dmac_channel_14_settings
+#ifndef CONF_DMAC_CHANNEL_14_SETTINGS
+#define CONF_DMAC_CHANNEL_14_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_14
+#ifndef CONF_DMAC_BURSTSIZE_14
+#define CONF_DMAC_BURSTSIZE_14 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_14
+#ifndef CONF_DMAC_CHUNKSIZE_14
+#define CONF_DMAC_CHUNKSIZE_14 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_14
+#ifndef CONF_DMAC_BEATSIZE_14
+#define CONF_DMAC_BEATSIZE_14 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_14
+#ifndef CONF_DMAC_SRC_INTERFACE_14
+#define CONF_DMAC_SRC_INTERFACE_14 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_14
+#ifndef CONF_DMAC_DES_INTERFACE_14
+#define CONF_DMAC_DES_INTERFACE_14 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_14
+#ifndef CONF_DMAC_SRCINC_14
+#define CONF_DMAC_SRCINC_14 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_14
+#ifndef CONF_DMAC_DSTINC_14
+#define CONF_DMAC_DSTINC_14 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_14
+#ifndef CONF_DMAC_TRANS_TYPE_14
+#define CONF_DMAC_TRANS_TYPE_14 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_14
+#ifndef CONF_DMAC_TRIGSRC_14
+#define CONF_DMAC_TRIGSRC_14 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_14 == 0
+#define CONF_DMAC_TYPE_14 0
+#define CONF_DMAC_DSYNC_14 0
+#elif CONF_DMAC_TRANS_TYPE_14 == 1
+#define CONF_DMAC_TYPE_14 1
+#define CONF_DMAC_DSYNC_14 0
+#elif CONF_DMAC_TRANS_TYPE_14 == 2
+#define CONF_DMAC_TYPE_14 1
+#define CONF_DMAC_DSYNC_14 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_14 == 0xFF
+#define CONF_DMAC_SWREQ_14 1
+#else
+#define CONF_DMAC_SWREQ_14 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_14_SETTINGS == 1 && CONF_DMAC_BEATSIZE_14 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_14) || (!CONF_DMAC_DSTINC_14)))
+#if (!CONF_DMAC_SRCINC_14)
+#define CONF_DMAC_SRC_STRIDE_14 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_14)
+#define CONF_DMAC_DES_STRIDE_14 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_14
+#define CONF_DMAC_SRC_STRIDE_14 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_14
+#define CONF_DMAC_DES_STRIDE_14 0
+#endif
+
+// <e> Channel 15 settings
+// <id> dmac_channel_15_settings
+#ifndef CONF_DMAC_CHANNEL_15_SETTINGS
+#define CONF_DMAC_CHANNEL_15_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_15
+#ifndef CONF_DMAC_BURSTSIZE_15
+#define CONF_DMAC_BURSTSIZE_15 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_15
+#ifndef CONF_DMAC_CHUNKSIZE_15
+#define CONF_DMAC_CHUNKSIZE_15 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_15
+#ifndef CONF_DMAC_BEATSIZE_15
+#define CONF_DMAC_BEATSIZE_15 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_15
+#ifndef CONF_DMAC_SRC_INTERFACE_15
+#define CONF_DMAC_SRC_INTERFACE_15 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_15
+#ifndef CONF_DMAC_DES_INTERFACE_15
+#define CONF_DMAC_DES_INTERFACE_15 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_15
+#ifndef CONF_DMAC_SRCINC_15
+#define CONF_DMAC_SRCINC_15 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_15
+#ifndef CONF_DMAC_DSTINC_15
+#define CONF_DMAC_DSTINC_15 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_15
+#ifndef CONF_DMAC_TRANS_TYPE_15
+#define CONF_DMAC_TRANS_TYPE_15 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_15
+#ifndef CONF_DMAC_TRIGSRC_15
+#define CONF_DMAC_TRIGSRC_15 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_15 == 0
+#define CONF_DMAC_TYPE_15 0
+#define CONF_DMAC_DSYNC_15 0
+#elif CONF_DMAC_TRANS_TYPE_15 == 1
+#define CONF_DMAC_TYPE_15 1
+#define CONF_DMAC_DSYNC_15 0
+#elif CONF_DMAC_TRANS_TYPE_15 == 2
+#define CONF_DMAC_TYPE_15 1
+#define CONF_DMAC_DSYNC_15 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_15 == 0xFF
+#define CONF_DMAC_SWREQ_15 1
+#else
+#define CONF_DMAC_SWREQ_15 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_15_SETTINGS == 1 && CONF_DMAC_BEATSIZE_15 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_15) || (!CONF_DMAC_DSTINC_15)))
+#if (!CONF_DMAC_SRCINC_15)
+#define CONF_DMAC_SRC_STRIDE_15 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_15)
+#define CONF_DMAC_DES_STRIDE_15 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_15
+#define CONF_DMAC_SRC_STRIDE_15 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_15
+#define CONF_DMAC_DES_STRIDE_15 0
+#endif
+
+// <e> Channel 16 settings
+// <id> dmac_channel_16_settings
+#ifndef CONF_DMAC_CHANNEL_16_SETTINGS
+#define CONF_DMAC_CHANNEL_16_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_16
+#ifndef CONF_DMAC_BURSTSIZE_16
+#define CONF_DMAC_BURSTSIZE_16 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_16
+#ifndef CONF_DMAC_CHUNKSIZE_16
+#define CONF_DMAC_CHUNKSIZE_16 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_16
+#ifndef CONF_DMAC_BEATSIZE_16
+#define CONF_DMAC_BEATSIZE_16 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_16
+#ifndef CONF_DMAC_SRC_INTERFACE_16
+#define CONF_DMAC_SRC_INTERFACE_16 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_16
+#ifndef CONF_DMAC_DES_INTERFACE_16
+#define CONF_DMAC_DES_INTERFACE_16 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_16
+#ifndef CONF_DMAC_SRCINC_16
+#define CONF_DMAC_SRCINC_16 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_16
+#ifndef CONF_DMAC_DSTINC_16
+#define CONF_DMAC_DSTINC_16 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_16
+#ifndef CONF_DMAC_TRANS_TYPE_16
+#define CONF_DMAC_TRANS_TYPE_16 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_16
+#ifndef CONF_DMAC_TRIGSRC_16
+#define CONF_DMAC_TRIGSRC_16 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_16 == 0
+#define CONF_DMAC_TYPE_16 0
+#define CONF_DMAC_DSYNC_16 0
+#elif CONF_DMAC_TRANS_TYPE_16 == 1
+#define CONF_DMAC_TYPE_16 1
+#define CONF_DMAC_DSYNC_16 0
+#elif CONF_DMAC_TRANS_TYPE_16 == 2
+#define CONF_DMAC_TYPE_16 1
+#define CONF_DMAC_DSYNC_16 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_16 == 0xFF
+#define CONF_DMAC_SWREQ_16 1
+#else
+#define CONF_DMAC_SWREQ_16 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_16_SETTINGS == 1 && CONF_DMAC_BEATSIZE_16 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_16) || (!CONF_DMAC_DSTINC_16)))
+#if (!CONF_DMAC_SRCINC_16)
+#define CONF_DMAC_SRC_STRIDE_16 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_16)
+#define CONF_DMAC_DES_STRIDE_16 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_16
+#define CONF_DMAC_SRC_STRIDE_16 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_16
+#define CONF_DMAC_DES_STRIDE_16 0
+#endif
+
+// <e> Channel 17 settings
+// <id> dmac_channel_17_settings
+#ifndef CONF_DMAC_CHANNEL_17_SETTINGS
+#define CONF_DMAC_CHANNEL_17_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_17
+#ifndef CONF_DMAC_BURSTSIZE_17
+#define CONF_DMAC_BURSTSIZE_17 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_17
+#ifndef CONF_DMAC_CHUNKSIZE_17
+#define CONF_DMAC_CHUNKSIZE_17 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_17
+#ifndef CONF_DMAC_BEATSIZE_17
+#define CONF_DMAC_BEATSIZE_17 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_17
+#ifndef CONF_DMAC_SRC_INTERFACE_17
+#define CONF_DMAC_SRC_INTERFACE_17 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_17
+#ifndef CONF_DMAC_DES_INTERFACE_17
+#define CONF_DMAC_DES_INTERFACE_17 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_17
+#ifndef CONF_DMAC_SRCINC_17
+#define CONF_DMAC_SRCINC_17 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_17
+#ifndef CONF_DMAC_DSTINC_17
+#define CONF_DMAC_DSTINC_17 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_17
+#ifndef CONF_DMAC_TRANS_TYPE_17
+#define CONF_DMAC_TRANS_TYPE_17 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_17
+#ifndef CONF_DMAC_TRIGSRC_17
+#define CONF_DMAC_TRIGSRC_17 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_17 == 0
+#define CONF_DMAC_TYPE_17 0
+#define CONF_DMAC_DSYNC_17 0
+#elif CONF_DMAC_TRANS_TYPE_17 == 1
+#define CONF_DMAC_TYPE_17 1
+#define CONF_DMAC_DSYNC_17 0
+#elif CONF_DMAC_TRANS_TYPE_17 == 2
+#define CONF_DMAC_TYPE_17 1
+#define CONF_DMAC_DSYNC_17 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_17 == 0xFF
+#define CONF_DMAC_SWREQ_17 1
+#else
+#define CONF_DMAC_SWREQ_17 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_17_SETTINGS == 1 && CONF_DMAC_BEATSIZE_17 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_17) || (!CONF_DMAC_DSTINC_17)))
+#if (!CONF_DMAC_SRCINC_17)
+#define CONF_DMAC_SRC_STRIDE_17 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_17)
+#define CONF_DMAC_DES_STRIDE_17 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_17
+#define CONF_DMAC_SRC_STRIDE_17 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_17
+#define CONF_DMAC_DES_STRIDE_17 0
+#endif
+
+// <e> Channel 18 settings
+// <id> dmac_channel_18_settings
+#ifndef CONF_DMAC_CHANNEL_18_SETTINGS
+#define CONF_DMAC_CHANNEL_18_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_18
+#ifndef CONF_DMAC_BURSTSIZE_18
+#define CONF_DMAC_BURSTSIZE_18 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_18
+#ifndef CONF_DMAC_CHUNKSIZE_18
+#define CONF_DMAC_CHUNKSIZE_18 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_18
+#ifndef CONF_DMAC_BEATSIZE_18
+#define CONF_DMAC_BEATSIZE_18 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_18
+#ifndef CONF_DMAC_SRC_INTERFACE_18
+#define CONF_DMAC_SRC_INTERFACE_18 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_18
+#ifndef CONF_DMAC_DES_INTERFACE_18
+#define CONF_DMAC_DES_INTERFACE_18 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_18
+#ifndef CONF_DMAC_SRCINC_18
+#define CONF_DMAC_SRCINC_18 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_18
+#ifndef CONF_DMAC_DSTINC_18
+#define CONF_DMAC_DSTINC_18 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_18
+#ifndef CONF_DMAC_TRANS_TYPE_18
+#define CONF_DMAC_TRANS_TYPE_18 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_18
+#ifndef CONF_DMAC_TRIGSRC_18
+#define CONF_DMAC_TRIGSRC_18 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_18 == 0
+#define CONF_DMAC_TYPE_18 0
+#define CONF_DMAC_DSYNC_18 0
+#elif CONF_DMAC_TRANS_TYPE_18 == 1
+#define CONF_DMAC_TYPE_18 1
+#define CONF_DMAC_DSYNC_18 0
+#elif CONF_DMAC_TRANS_TYPE_18 == 2
+#define CONF_DMAC_TYPE_18 1
+#define CONF_DMAC_DSYNC_18 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_18 == 0xFF
+#define CONF_DMAC_SWREQ_18 1
+#else
+#define CONF_DMAC_SWREQ_18 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_18_SETTINGS == 1 && CONF_DMAC_BEATSIZE_18 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_18) || (!CONF_DMAC_DSTINC_18)))
+#if (!CONF_DMAC_SRCINC_18)
+#define CONF_DMAC_SRC_STRIDE_18 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_18)
+#define CONF_DMAC_DES_STRIDE_18 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_18
+#define CONF_DMAC_SRC_STRIDE_18 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_18
+#define CONF_DMAC_DES_STRIDE_18 0
+#endif
+
+// <e> Channel 19 settings
+// <id> dmac_channel_19_settings
+#ifndef CONF_DMAC_CHANNEL_19_SETTINGS
+#define CONF_DMAC_CHANNEL_19_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_19
+#ifndef CONF_DMAC_BURSTSIZE_19
+#define CONF_DMAC_BURSTSIZE_19 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_19
+#ifndef CONF_DMAC_CHUNKSIZE_19
+#define CONF_DMAC_CHUNKSIZE_19 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_19
+#ifndef CONF_DMAC_BEATSIZE_19
+#define CONF_DMAC_BEATSIZE_19 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_19
+#ifndef CONF_DMAC_SRC_INTERFACE_19
+#define CONF_DMAC_SRC_INTERFACE_19 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_19
+#ifndef CONF_DMAC_DES_INTERFACE_19
+#define CONF_DMAC_DES_INTERFACE_19 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_19
+#ifndef CONF_DMAC_SRCINC_19
+#define CONF_DMAC_SRCINC_19 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_19
+#ifndef CONF_DMAC_DSTINC_19
+#define CONF_DMAC_DSTINC_19 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_19
+#ifndef CONF_DMAC_TRANS_TYPE_19
+#define CONF_DMAC_TRANS_TYPE_19 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_19
+#ifndef CONF_DMAC_TRIGSRC_19
+#define CONF_DMAC_TRIGSRC_19 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_19 == 0
+#define CONF_DMAC_TYPE_19 0
+#define CONF_DMAC_DSYNC_19 0
+#elif CONF_DMAC_TRANS_TYPE_19 == 1
+#define CONF_DMAC_TYPE_19 1
+#define CONF_DMAC_DSYNC_19 0
+#elif CONF_DMAC_TRANS_TYPE_19 == 2
+#define CONF_DMAC_TYPE_19 1
+#define CONF_DMAC_DSYNC_19 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_19 == 0xFF
+#define CONF_DMAC_SWREQ_19 1
+#else
+#define CONF_DMAC_SWREQ_19 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_19_SETTINGS == 1 && CONF_DMAC_BEATSIZE_19 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_19) || (!CONF_DMAC_DSTINC_19)))
+#if (!CONF_DMAC_SRCINC_19)
+#define CONF_DMAC_SRC_STRIDE_19 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_19)
+#define CONF_DMAC_DES_STRIDE_19 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_19
+#define CONF_DMAC_SRC_STRIDE_19 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_19
+#define CONF_DMAC_DES_STRIDE_19 0
+#endif
+
+// <e> Channel 20 settings
+// <id> dmac_channel_20_settings
+#ifndef CONF_DMAC_CHANNEL_20_SETTINGS
+#define CONF_DMAC_CHANNEL_20_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_20
+#ifndef CONF_DMAC_BURSTSIZE_20
+#define CONF_DMAC_BURSTSIZE_20 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_20
+#ifndef CONF_DMAC_CHUNKSIZE_20
+#define CONF_DMAC_CHUNKSIZE_20 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_20
+#ifndef CONF_DMAC_BEATSIZE_20
+#define CONF_DMAC_BEATSIZE_20 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_20
+#ifndef CONF_DMAC_SRC_INTERFACE_20
+#define CONF_DMAC_SRC_INTERFACE_20 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_20
+#ifndef CONF_DMAC_DES_INTERFACE_20
+#define CONF_DMAC_DES_INTERFACE_20 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_20
+#ifndef CONF_DMAC_SRCINC_20
+#define CONF_DMAC_SRCINC_20 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_20
+#ifndef CONF_DMAC_DSTINC_20
+#define CONF_DMAC_DSTINC_20 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_20
+#ifndef CONF_DMAC_TRANS_TYPE_20
+#define CONF_DMAC_TRANS_TYPE_20 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_20
+#ifndef CONF_DMAC_TRIGSRC_20
+#define CONF_DMAC_TRIGSRC_20 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_20 == 0
+#define CONF_DMAC_TYPE_20 0
+#define CONF_DMAC_DSYNC_20 0
+#elif CONF_DMAC_TRANS_TYPE_20 == 1
+#define CONF_DMAC_TYPE_20 1
+#define CONF_DMAC_DSYNC_20 0
+#elif CONF_DMAC_TRANS_TYPE_20 == 2
+#define CONF_DMAC_TYPE_20 1
+#define CONF_DMAC_DSYNC_20 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_20 == 0xFF
+#define CONF_DMAC_SWREQ_20 1
+#else
+#define CONF_DMAC_SWREQ_20 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_20_SETTINGS == 1 && CONF_DMAC_BEATSIZE_20 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_20) || (!CONF_DMAC_DSTINC_20)))
+#if (!CONF_DMAC_SRCINC_20)
+#define CONF_DMAC_SRC_STRIDE_20 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_20)
+#define CONF_DMAC_DES_STRIDE_20 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_20
+#define CONF_DMAC_SRC_STRIDE_20 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_20
+#define CONF_DMAC_DES_STRIDE_20 0
+#endif
+
+// <e> Channel 21 settings
+// <id> dmac_channel_21_settings
+#ifndef CONF_DMAC_CHANNEL_21_SETTINGS
+#define CONF_DMAC_CHANNEL_21_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_21
+#ifndef CONF_DMAC_BURSTSIZE_21
+#define CONF_DMAC_BURSTSIZE_21 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_21
+#ifndef CONF_DMAC_CHUNKSIZE_21
+#define CONF_DMAC_CHUNKSIZE_21 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_21
+#ifndef CONF_DMAC_BEATSIZE_21
+#define CONF_DMAC_BEATSIZE_21 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_21
+#ifndef CONF_DMAC_SRC_INTERFACE_21
+#define CONF_DMAC_SRC_INTERFACE_21 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_21
+#ifndef CONF_DMAC_DES_INTERFACE_21
+#define CONF_DMAC_DES_INTERFACE_21 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_21
+#ifndef CONF_DMAC_SRCINC_21
+#define CONF_DMAC_SRCINC_21 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_21
+#ifndef CONF_DMAC_DSTINC_21
+#define CONF_DMAC_DSTINC_21 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_21
+#ifndef CONF_DMAC_TRANS_TYPE_21
+#define CONF_DMAC_TRANS_TYPE_21 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_21
+#ifndef CONF_DMAC_TRIGSRC_21
+#define CONF_DMAC_TRIGSRC_21 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_21 == 0
+#define CONF_DMAC_TYPE_21 0
+#define CONF_DMAC_DSYNC_21 0
+#elif CONF_DMAC_TRANS_TYPE_21 == 1
+#define CONF_DMAC_TYPE_21 1
+#define CONF_DMAC_DSYNC_21 0
+#elif CONF_DMAC_TRANS_TYPE_21 == 2
+#define CONF_DMAC_TYPE_21 1
+#define CONF_DMAC_DSYNC_21 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_21 == 0xFF
+#define CONF_DMAC_SWREQ_21 1
+#else
+#define CONF_DMAC_SWREQ_21 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_21_SETTINGS == 1 && CONF_DMAC_BEATSIZE_21 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_21) || (!CONF_DMAC_DSTINC_21)))
+#if (!CONF_DMAC_SRCINC_21)
+#define CONF_DMAC_SRC_STRIDE_21 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_21)
+#define CONF_DMAC_DES_STRIDE_21 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_21
+#define CONF_DMAC_SRC_STRIDE_21 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_21
+#define CONF_DMAC_DES_STRIDE_21 0
+#endif
+
+// <e> Channel 22 settings
+// <id> dmac_channel_22_settings
+#ifndef CONF_DMAC_CHANNEL_22_SETTINGS
+#define CONF_DMAC_CHANNEL_22_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_22
+#ifndef CONF_DMAC_BURSTSIZE_22
+#define CONF_DMAC_BURSTSIZE_22 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_22
+#ifndef CONF_DMAC_CHUNKSIZE_22
+#define CONF_DMAC_CHUNKSIZE_22 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_22
+#ifndef CONF_DMAC_BEATSIZE_22
+#define CONF_DMAC_BEATSIZE_22 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_22
+#ifndef CONF_DMAC_SRC_INTERFACE_22
+#define CONF_DMAC_SRC_INTERFACE_22 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_22
+#ifndef CONF_DMAC_DES_INTERFACE_22
+#define CONF_DMAC_DES_INTERFACE_22 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_22
+#ifndef CONF_DMAC_SRCINC_22
+#define CONF_DMAC_SRCINC_22 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_22
+#ifndef CONF_DMAC_DSTINC_22
+#define CONF_DMAC_DSTINC_22 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_22
+#ifndef CONF_DMAC_TRANS_TYPE_22
+#define CONF_DMAC_TRANS_TYPE_22 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_22
+#ifndef CONF_DMAC_TRIGSRC_22
+#define CONF_DMAC_TRIGSRC_22 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_22 == 0
+#define CONF_DMAC_TYPE_22 0
+#define CONF_DMAC_DSYNC_22 0
+#elif CONF_DMAC_TRANS_TYPE_22 == 1
+#define CONF_DMAC_TYPE_22 1
+#define CONF_DMAC_DSYNC_22 0
+#elif CONF_DMAC_TRANS_TYPE_22 == 2
+#define CONF_DMAC_TYPE_22 1
+#define CONF_DMAC_DSYNC_22 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_22 == 0xFF
+#define CONF_DMAC_SWREQ_22 1
+#else
+#define CONF_DMAC_SWREQ_22 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_22_SETTINGS == 1 && CONF_DMAC_BEATSIZE_22 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_22) || (!CONF_DMAC_DSTINC_22)))
+#if (!CONF_DMAC_SRCINC_22)
+#define CONF_DMAC_SRC_STRIDE_22 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_22)
+#define CONF_DMAC_DES_STRIDE_22 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_22
+#define CONF_DMAC_SRC_STRIDE_22 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_22
+#define CONF_DMAC_DES_STRIDE_22 0
+#endif
+
+// <e> Channel 23 settings
+// <id> dmac_channel_23_settings
+#ifndef CONF_DMAC_CHANNEL_23_SETTINGS
+#define CONF_DMAC_CHANNEL_23_SETTINGS 0
+#endif
+
+// <o> Burst Size
+// <0x0=> 1 burst size
+// <0x1=> 4 burst size
+// <0x2=> 8 burst size
+// <0x3=> 16 burst size
+// <i> Define the memory burst size
+// <id> dmac_burstsize_23
+#ifndef CONF_DMAC_BURSTSIZE_23
+#define CONF_DMAC_BURSTSIZE_23 0x0
+#endif
+
+// <o> Chunk Size
+// <0x0=> 1 data transferred
+// <0x1=> 2 data transferred
+// <0x2=> 4 data transferred
+// <0x3=> 8 data transferred
+// <0x4=> 16 data transferred
+// <i> Define the peripheral chunk size
+// <id> dmac_chunksize_23
+#ifndef CONF_DMAC_CHUNKSIZE_23
+#define CONF_DMAC_CHUNKSIZE_23 0x0
+#endif
+
+// <o> Beat Size
+// <0=> 8-bit bus transfer
+// <1=> 16-bit bus transfer
+// <2=> 32-bit bus transfer
+// <i> Defines the size of one beat
+// <id> dmac_beatsize_23
+#ifndef CONF_DMAC_BEATSIZE_23
+#define CONF_DMAC_BEATSIZE_23 0x0
+#endif
+
+// <o> Source Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is read through the system bus interface 0 or 1
+// <id> dma_src_interface_23
+#ifndef CONF_DMAC_SRC_INTERFACE_23
+#define CONF_DMAC_SRC_INTERFACE_23 0x0
+#endif
+
+// <o> Destination Interface Identifier
+// <0x0=> AHB_IF0
+// <0x1=> AHB_IF1
+// <i> Define the data is written through the system bus interface 0 or 1
+// <id> dma_des_interface_23
+#ifndef CONF_DMAC_DES_INTERFACE_23
+#define CONF_DMAC_DES_INTERFACE_23 0x0
+#endif
+
+// <q> Source Address Increment
+// <i> Indicates whether the source address incremented as beat size or not
+// <id> dmac_srcinc_23
+#ifndef CONF_DMAC_SRCINC_23
+#define CONF_DMAC_SRCINC_23 0
+#endif
+
+// <q> Destination Address Increment
+// <i> Indicates whether the destination address incremented as beat size or not
+// <id> dmac_dstinc_23
+#ifndef CONF_DMAC_DSTINC_23
+#define CONF_DMAC_DSTINC_23 0
+#endif
+
+// <o> Transfer Type
+// <0x0=> Memory to Memory Transfer
+// <0x1=> Peripheral to Memory Transfer
+// <0x2=> Memory to Peripheral Transfer
+// <i> Define the data transfer type
+// <id> dma_trans_type_23
+#ifndef CONF_DMAC_TRANS_TYPE_23
+#define CONF_DMAC_TRANS_TYPE_23 0x0
+#endif
+
+// <o> Trigger source
+// <0xFF=> Software Trigger
+// <0x00=> HSMCI TX/RX Trigger
+// <0x01=> SPI0 TX Trigger
+// <0x02=> SPI0 RX Trigger
+// <0x03=> SPI1 TX Trigger
+// <0x04=> SPI1 RX Trigger
+// <0x05=> QSPI TX Trigger
+// <0x06=> QSPI RX Trigger
+// <0x07=> USART0 TX Trigger
+// <0x08=> USART0 RX Trigger
+// <0x09=> USART1 TX Trigger
+// <0x0A=> USART1 RX Trigger
+// <0x0B=> USART2 TX Trigger
+// <0x0C=> USART2 RX Trigger
+// <0x0D=> PWM0 TX Trigger
+// <0x0E=> TWIHS0 TX Trigger
+// <0x0F=> TWIHS0 RX Trigger
+// <0x10=> TWIHS1 TX Trigger
+// <0x11=> TWIHS1 RX Trigger
+// <0x12=> TWIHS2 TX Trigger
+// <0x13=> TWIHS2 RX Trigger
+// <0x14=> UART0 TX Trigger
+// <0x15=> UART0 RX Trigger
+// <0x16=> UART1 TX Trigger
+// <0x17=> UART1 RX Trigger
+// <0x18=> UART2 TX Trigger
+// <0x19=> UART2 RX Trigger
+// <0x1A=> UART3 TX Trigger
+// <0x1B=> UART3 RX Trigger
+// <0x1C=> UART4 TX Trigger
+// <0x1D=> UART4 RX Trigger
+// <0x1E=> DACC TX Trigger
+// <0x20=> SSC TX Trigger
+// <0x21=> SSC RX Trigger
+// <0x22=> PIOA RX Trigger
+// <0x23=> AFEC0 RX Trigger
+// <0x24=> AFEC1 RX Trigger
+// <0x25=> AES TX Trigger
+// <0x26=> AES RX Trigger
+// <0x27=> PWM1 TX Trigger
+// <0x28=> TC0 RX Trigger
+// <0x29=> TC3 RX Trigger
+// <0x2A=> TC6 RX Trigger
+// <0x2B=> TC9 RX Trigger
+// <0x2C=> I2SC0 TX Left Trigger
+// <0x2D=> I2SC0 RX Left Trigger
+// <0x2E=> I2SC1 TX Left Trigger
+// <0x2F=> I2SC1 RX Left Trigger
+// <0x30=> I2SC0 TX Right Trigger
+// <0x31=> I2SC0 RX Right Trigger
+// <0x32=> I2SC1 TX Right Trigger
+// <0x33=> I2SC1 RX Right Trigger
+// <i> Define the DMA trigger source
+// <id> dmac_trifsrc_23
+#ifndef CONF_DMAC_TRIGSRC_23
+#define CONF_DMAC_TRIGSRC_23 0xff
+#endif
+
+// </e>
+
+#if CONF_DMAC_TRANS_TYPE_23 == 0
+#define CONF_DMAC_TYPE_23 0
+#define CONF_DMAC_DSYNC_23 0
+#elif CONF_DMAC_TRANS_TYPE_23 == 1
+#define CONF_DMAC_TYPE_23 1
+#define CONF_DMAC_DSYNC_23 0
+#elif CONF_DMAC_TRANS_TYPE_23 == 2
+#define CONF_DMAC_TYPE_23 1
+#define CONF_DMAC_DSYNC_23 1
+#endif
+
+#if CONF_DMAC_TRIGSRC_23 == 0xFF
+#define CONF_DMAC_SWREQ_23 1
+#else
+#define CONF_DMAC_SWREQ_23 0
+#endif
+
+/* Errata: If XDMA is used to transfer 8-bit or 16-bit data in fixed source address
+ * or fixed destination address mode, source and destination addresses are incremented
+ * by 8-bit or 16-bit.
+ * Workaround: The user can fix the problem by setting the source addressing mode to
+ * use microblock and data striding with microblock stride set to 0 and data stride set to -1.
+ */
+#if (CONF_DMAC_CHANNEL_23_SETTINGS == 1 && CONF_DMAC_BEATSIZE_23 != 2                                                  \
+     && ((!CONF_DMAC_SRCINC_23) || (!CONF_DMAC_DSTINC_23)))
+#if (!CONF_DMAC_SRCINC_23)
+#define CONF_DMAC_SRC_STRIDE_23 ((int16_t)(-1))
+#endif
+#if (!CONF_DMAC_DSTINC_23)
+#define CONF_DMAC_DES_STRIDE_23 ((int16_t)(-1))
+#endif
+#endif
+
+#ifndef CONF_DMAC_SRC_STRIDE_23
+#define CONF_DMAC_SRC_STRIDE_23 0
+#endif
+
+#ifndef CONF_DMAC_DES_STRIDE_23
+#define CONF_DMAC_DES_STRIDE_23 0
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_XDMAC_CONFIG_H
diff --git a/hw/bsp/same70_qmtech/peripheral_clk_config.h b/hw/bsp/same70_qmtech/peripheral_clk_config.h
new file mode 100644
index 000000000..84756f5ac
--- /dev/null
+++ b/hw/bsp/same70_qmtech/peripheral_clk_config.h
@@ -0,0 +1,126 @@
+/* Auto-generated config file peripheral_clk_config.h */
+#ifndef PERIPHERAL_CLK_CONFIG_H
+#define PERIPHERAL_CLK_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+/**
+ * \def CONF_HCLK_FREQUENCY
+ * \brief HCLK's Clock frequency
+ */
+#ifndef CONF_HCLK_FREQUENCY
+#define CONF_HCLK_FREQUENCY 300000000
+#endif
+
+/**
+ * \def CONF_FCLK_FREQUENCY
+ * \brief FCLK's Clock frequency
+ */
+#ifndef CONF_FCLK_FREQUENCY
+#define CONF_FCLK_FREQUENCY 300000000
+#endif
+
+/**
+ * \def CONF_CPU_FREQUENCY
+ * \brief CPU's Clock frequency
+ */
+#ifndef CONF_CPU_FREQUENCY
+#define CONF_CPU_FREQUENCY 300000000
+#endif
+
+/**
+ * \def CONF_SLCK_FREQUENCY
+ * \brief Slow Clock frequency
+ */
+#define CONF_SLCK_FREQUENCY 0
+
+/**
+ * \def CONF_MCK_FREQUENCY
+ * \brief Master Clock frequency
+ */
+#define CONF_MCK_FREQUENCY 150000000
+
+/**
+ * \def CONF_PCK6_FREQUENCY
+ * \brief Programmable Clock Controller 6 frequency
+ */
+#define CONF_PCK6_FREQUENCY 1714285
+
+// <h> USART Clock Settings
+// <o> USART Clock source
+
+// <0=> Master Clock (MCK)
+// <1=> MCK / 8 for USART
+// <2=> Programmable Clock Controller 4 (PMC_PCK4)
+// <3=> External Clock
+// <i> This defines the clock source for the USART
+// <id> usart_clock_source
+#ifndef CONF_USART1_CK_SRC
+#define CONF_USART1_CK_SRC 0
+#endif
+
+// <o> USART External Clock Input on SCK <1-4294967295>
+// <i> Inputs the external clock frequency on SCK
+// <id> usart_clock_freq
+#ifndef CONF_USART1_SCK_FREQ
+#define CONF_USART1_SCK_FREQ 10000000
+#endif
+
+// </h>
+
+/**
+ * \def USART FREQUENCY
+ * \brief USART's Clock frequency
+ */
+#ifndef CONF_USART1_FREQUENCY
+#define CONF_USART1_FREQUENCY 150000000
+#endif
+
+#ifndef CONF_SRC_USB_480M
+#define CONF_SRC_USB_480M 0
+#endif
+
+#ifndef CONF_SRC_USB_48M
+#define CONF_SRC_USB_48M 1
+#endif
+
+// <y> USB Full/Low Speed Clock
+// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M)
+// <id> usb_fsls_clock_source
+// <i> 48MHz clock source for low speed and full speed.
+// <i> It must be available when low speed is supported by host driver.
+// <i> It must be available when low power mode is selected.
+#ifndef CONF_USBHS_FSLS_SRC
+#define CONF_USBHS_FSLS_SRC CONF_SRC_USB_48M
+#endif
+
+// <y> USB Clock Source(Normal/Low-power Mode Selection)
+// <CONF_SRC_USB_480M"> USB High Speed Clock (USB_480M)
+// <CONF_SRC_USB_48M"> USB Clock Controller (USB_48M)
+// <id> usb_clock_source
+// <i> Select the clock source for USB.
+// <i> In normal mode, use "USB High Speed Clock (USB_480M)".
+// <i> In low-power mode, use "USB Clock Controller (USB_48M)".
+#ifndef CONF_USBHS_SRC
+#define CONF_USBHS_SRC CONF_SRC_USB_480M
+#endif
+
+/**
+ * \def CONF_USBHS_FSLS_FREQUENCY
+ * \brief USBHS's Full/Low Speed Clock Source frequency
+ */
+#ifndef CONF_USBHS_FSLS_FREQUENCY
+#define CONF_USBHS_FSLS_FREQUENCY 48000000
+#endif
+
+/**
+ * \def CONF_USBHS_FREQUENCY
+ * \brief USBHS's Selected Clock Source frequency
+ */
+#ifndef CONF_USBHS_FREQUENCY
+#define CONF_USBHS_FREQUENCY 480000000
+#endif
+
+// <<< end of configuration section >>>
+
+#endif // PERIPHERAL_CLK_CONFIG_H
diff --git a/hw/bsp/same70_qmtech/same70_qmtech.c b/hw/bsp/same70_qmtech/same70_qmtech.c
new file mode 100644
index 000000000..6e6ad0602
--- /dev/null
+++ b/hw/bsp/same70_qmtech/same70_qmtech.c
@@ -0,0 +1,159 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "sam.h"
+#include "bsp/board.h"
+
+#include "peripheral_clk_config.h"
+#include "hpl/usart/hpl_usart_base.h"
+#include "hpl/pmc/hpl_pmc.h"
+#include "hal/include/hal_init.h"
+#include "hal/include/hal_usart_async.h"
+#include "hal/include/hal_gpio.h"
+
+
+// You can get the board here:
+// https://www.aliexpress.com/item/1005003173783268.html
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+#define LED_PIN               GPIO(GPIO_PORTA, 15)
+
+#define BUTTON_PIN            GPIO(GPIO_PORTA, 21)
+#define BUTTON_STATE_ACTIVE   0
+
+#define UART_TX_PIN           GPIO(GPIO_PORTB, 1)
+#define UART_RX_PIN           GPIO(GPIO_PORTB, 0)
+
+static struct usart_async_descriptor edbg_com;
+static uint8_t edbg_com_buffer[64];
+static volatile bool uart_busy = false;
+
+static void tx_cb_EDBG_COM(const struct usart_async_descriptor *const io_descr)
+{
+  (void) io_descr;
+  uart_busy = false;
+}
+
+//------------- IMPLEMENTATION -------------//
+void board_init(void)
+{
+  init_mcu();
+
+  /* Disable Watchdog */
+  hri_wdt_set_MR_WDDIS_bit(WDT);
+
+  // LED
+  _pmc_enable_periph_clock(ID_PIOB);
+  gpio_set_pin_level(LED_PIN, false);
+  gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_function(LED_PIN, GPIO_PIN_FUNCTION_OFF);
+
+  // Button
+  _pmc_enable_periph_clock(ID_PIOA);
+  gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
+  gpio_set_pin_function(BUTTON_PIN, GPIO_PIN_FUNCTION_OFF);
+
+  // Uart via EDBG Com
+  _pmc_enable_periph_clock(ID_USART1);
+  gpio_set_pin_function(UART_RX_PIN, MUX_PA21A_USART1_RXD1);
+  gpio_set_pin_function(UART_TX_PIN, MUX_PB4D_USART1_TXD1);
+
+  usart_async_init(&edbg_com, USART1, edbg_com_buffer, sizeof(edbg_com_buffer), _usart_get_usart_async());
+  usart_async_set_baud_rate(&edbg_com, CFG_BOARD_UART_BAUDRATE);
+  usart_async_register_callback(&edbg_com, USART_ASYNC_TXC_CB, tx_cb_EDBG_COM);
+  usart_async_enable(&edbg_com);
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+  // 1ms tick timer (samd SystemCoreClock may not correct)
+  SysTick_Config(CONF_CPU_FREQUENCY / 1000);
+#endif
+
+  // Enable USB clock
+  _pmc_enable_periph_clock(ID_USBHS);
+
+}
+
+//--------------------------------------------------------------------+
+// USB Interrupt Handler
+//--------------------------------------------------------------------+
+void USBHS_Handler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  gpio_set_pin_level(LED_PIN, state);
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  // while until previous transfer is complete
+  while(uart_busy) {}
+  uart_busy = true;
+
+  io_write(&edbg_com.io, buf, len);
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}

From db862ae72501a726cb70571395725a1938c6dcc1 Mon Sep 17 00:00:00 2001
From: szymonh <12231135+szymonh@users.noreply.github.com>
Date: Mon, 27 Sep 2021 21:11:44 +0200
Subject: [PATCH 0498/2085] Assure msc device block size is not zero

---
 src/class/msc/msc_device.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 0fd592129..b65abe979 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -187,6 +187,11 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
       TU_LOG(MSC_DEBUG, "  SCSI case 4 Hi > Dn\r\n");
       status =  MSC_CSW_STATUS_FAILED;
     }
+    else if ( SCSI_CMD_READ_10 == cbw->command[0] && cbw->total_bytes / block_count == 0)
+    {
+      TU_LOG(MSC_DEBUG, " Computed block size 0\r\n");
+      status = MSC_CSW_STATUS_FAILED;
+    }
   }
 
   return status;

From bbb68ffefbe867e26795567269f4815257d883f0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Sep 2021 14:55:20 +0700
Subject: [PATCH 0499/2085] remove official mm32sdk submodule

---
 .gitmodules               | 3 ---
 hw/mcu/mindmotion/mm32sdk | 1 -
 2 files changed, 4 deletions(-)
 delete mode 160000 hw/mcu/mindmotion/mm32sdk

diff --git a/.gitmodules b/.gitmodules
index 4c86fd55c..538b4ed66 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -121,9 +121,6 @@
 [submodule "hw/mcu/nxp/nxp_sdk"]
 	path = hw/mcu/nxp/nxp_sdk
 	url = https://github.com/hathach/nxp_sdk.git
-[submodule "hw/mcu/mindmotion/mm32sdk"]
-	path = hw/mcu/mindmotion/mm32sdk
-	url = https://github.com/zhangslice/mm32sdk.git
 [submodule "hw/mcu/gd/nuclei-sdk"]
 	path = hw/mcu/gd/nuclei-sdk
 	url = https://github.com/Nuclei-Software/nuclei-sdk.git
diff --git a/hw/mcu/mindmotion/mm32sdk b/hw/mcu/mindmotion/mm32sdk
deleted file mode 160000
index b6b99de3a..000000000
--- a/hw/mcu/mindmotion/mm32sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit b6b99de3ab26218784ec158488bdd91377288f94

From 7af57e41b51bb491b064786748301a0a7b7365b4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Sep 2021 14:58:47 +0700
Subject: [PATCH 0500/2085] add submodule hathach/mm32sdk

---
 .gitmodules               | 3 +++
 hw/mcu/mindmotion/mm32sdk | 1 +
 2 files changed, 4 insertions(+)
 create mode 160000 hw/mcu/mindmotion/mm32sdk

diff --git a/.gitmodules b/.gitmodules
index 538b4ed66..5f5bee56c 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -124,3 +124,6 @@
 [submodule "hw/mcu/gd/nuclei-sdk"]
 	path = hw/mcu/gd/nuclei-sdk
 	url = https://github.com/Nuclei-Software/nuclei-sdk.git
+[submodule "hw/mcu/mindmotion/mm32sdk"]
+	path = hw/mcu/mindmotion/mm32sdk
+	url = https://github.com/hathach/mm32sdk.git
diff --git a/hw/mcu/mindmotion/mm32sdk b/hw/mcu/mindmotion/mm32sdk
new file mode 160000
index 000000000..6512211cc
--- /dev/null
+++ b/hw/mcu/mindmotion/mm32sdk
@@ -0,0 +1 @@
+Subproject commit 6512211cc9e7b0219b88d837a6e44f0bb661e1f5

From 3eeb79be4f54b8ab954ae2542e211bc37575e2bf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Sep 2021 15:20:14 +0700
Subject: [PATCH 0501/2085] update mm32sdk submodule

---
 hw/mcu/mindmotion/mm32sdk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/mindmotion/mm32sdk b/hw/mcu/mindmotion/mm32sdk
index 6512211cc..708a71529 160000
--- a/hw/mcu/mindmotion/mm32sdk
+++ b/hw/mcu/mindmotion/mm32sdk
@@ -1 +1 @@
-Subproject commit 6512211cc9e7b0219b88d837a6e44f0bb661e1f5
+Subproject commit 708a7152952ac595d24837069dcc0f7f59a4c30b

From f3c1b2a60da15d0466d3e076726c868989b77b3b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Sep 2021 15:31:03 +0700
Subject: [PATCH 0502/2085] clean up

---
 src/class/cdc/cdc_device.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index 72e29705a..fbc7162a3 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -82,7 +82,7 @@ int32_t  tud_cdc_n_read_char       (uint8_t itf);
 void     tud_cdc_n_read_flush      (uint8_t itf);
 
 // Get a byte from FIFO at the specified position without removing it
-bool     tud_cdc_n_peek            (uint8_t itf, uint8_t* uv8);
+bool     tud_cdc_n_peek            (uint8_t itf, uint8_t* ui8);
 
 // Write bytes to TX FIFO, data may remain in the FIFO for a while
 uint32_t tud_cdc_n_write           (uint8_t itf, void const* buffer, uint32_t bufsize);
@@ -116,7 +116,7 @@ static inline uint32_t tud_cdc_available       (void);
 static inline int32_t  tud_cdc_read_char       (void);
 static inline uint32_t tud_cdc_read            (void* buffer, uint32_t bufsize);
 static inline void     tud_cdc_read_flush      (void);
-static inline bool     tud_cdc_peek            (uint8_t* u8);
+static inline bool     tud_cdc_peek            (uint8_t* ui8);
 
 static inline uint32_t tud_cdc_write_char      (char ch);
 static inline uint32_t tud_cdc_write           (void const* buffer, uint32_t bufsize);
@@ -206,9 +206,9 @@ static inline void tud_cdc_read_flush (void)
   tud_cdc_n_read_flush(0);
 }
 
-static inline bool tud_cdc_peek (uint8_t* uv8)
+static inline bool tud_cdc_peek (uint8_t* ui8)
 {
-  return tud_cdc_n_peek(0, uv8);
+  return tud_cdc_n_peek(0, ui8);
 }
 
 static inline uint32_t tud_cdc_write_char (char ch)

From b5b03e6c7f598a0ba8540d19acf798e35d24faf9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Sep 2021 15:33:44 +0700
Subject: [PATCH 0503/2085] add mm32 to ci build, also re-enable esp32s3

---
 .github/workflows/build.yml     | 1 +
 .github/workflows/build_esp.yml | 3 +--
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 8ef19b0a0..1ef0bf5ea 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -44,6 +44,7 @@ jobs:
         - 'lpc18'
         - 'lpc54'
         - 'lpc55'
+        - 'mm32'
         - 'nrf'
         - 'rp2040'
         - 'samd11'
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 25f4e68f8..93d582361 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -18,8 +18,7 @@ jobs:
         # ESP32-S2
         - 'espressif_saola_1'
         # ESP32-S3
-        # latest IDF does not define USB0 in linker
-        #- 'espressif_addax_1'
+        - 'espressif_addax_1'
 
     steps:
     - name: Setup Python

From 2f2fb3d8d92f35c756d66db0eb256037f0a7d62f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Sep 2021 16:18:11 +0700
Subject: [PATCH 0504/2085] clean up

---
 .../audio_4_channel_mic/src/usb_descriptors.c |  2 ++
 .../device/audio_test/src/usb_descriptors.c   | 13 ++++++---
 .../device/uac2_headset/src/usb_descriptors.c | 29 ++++++++++---------
 src/class/vendor/vendor_device.c              |  2 +-
 4 files changed, 28 insertions(+), 18 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index 2b66bfe34..b6a5bd5c2 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -85,9 +85,11 @@ enum
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
   #define EPNUM_AUDIO   0x03
+
 #elif TU_CHECK_MCU(NRF5X)
   // nRF5x ISO can only be endpoint 8
   #define EPNUM_AUDIO   0x08
+
 #else
   #define EPNUM_AUDIO   0x01
 #endif
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index a4e9dc8e1..348f5eede 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -82,11 +82,16 @@ enum
 #define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_ONE_CH_DESC_LEN)
 
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
-// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
-// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
-#define EPNUM_AUDIO   0x03
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_AUDIO   0x03
+
+#elif TU_CHECK_MCU(NRF5X)
+  // nRF5x ISO can only be endpoint 8
+  #define EPNUM_AUDIO   0x08
+
 #else
-#define EPNUM_AUDIO   0x01
+  #define EPNUM_AUDIO   0x01
 #endif
 
 uint8_t const desc_configuration[] =
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 64fa3c25b..9e97845b8 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -77,22 +77,25 @@ uint8_t const * tud_descriptor_device_cb(void)
 #define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_HEADSET_STEREO_DESC_LEN)
 
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
-// LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
-// 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
-#define EPNUM_AUDIO_IN    0x03
-#define EPNUM_AUDIO_OUT   0x03
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_AUDIO_IN    0x03
+  #define EPNUM_AUDIO_OUT   0x03
+
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
-// ISO endpoints for NRF5x are fixed to 0x08 (0x88)
-#define EPNUM_AUDIO_IN    0x08
-#define EPNUM_AUDIO_OUT   0x08
+  // ISO endpoints for NRF5x are fixed to 0x08 (0x88)
+  #define EPNUM_AUDIO_IN    0x08
+  #define EPNUM_AUDIO_OUT   0x08
+
 #elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
-// SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
-//    e.g EP1 OUT & EP1 IN cannot exist together
-#define EPNUM_AUDIO_IN    0x01
-#define EPNUM_AUDIO_OUT   0x02
+  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_AUDIO_IN    0x01
+  #define EPNUM_AUDIO_OUT   0x02
+
 #else
-#define EPNUM_AUDIO_IN    0x01
-#define EPNUM_AUDIO_OUT   0x01
+  #define EPNUM_AUDIO_IN    0x01
+  #define EPNUM_AUDIO_OUT   0x01
 #endif
 
 uint8_t const desc_configuration[] =
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index c73ca2538..188b561d7 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -216,7 +216,7 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui
     if ( p_vendor->ep_in ) maybe_transmit(p_vendor);
   }
 
-  return (uint16_t) true;
+  return drv_len;
 }
 
 bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)

From 1d5bdf7d396afe22b114f6f8edf45cbc3d88325b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Sep 2021 16:29:15 +0700
Subject: [PATCH 0505/2085] add same7x to board list

---
 docs/reference/supported.rst     | 6 ++++++
 src/class/vendor/vendor_device.c | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index daf5bce75..c8a441f18 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -175,6 +175,12 @@ SAMD51 & SAME54
 -  `D5035-01 <https://github.com/RudolphRiedel/USB_CAN-FD>`__
 -  `Microchip SAME54 Xplained Pro <https://www.microchip.com/developmenttools/productdetails/atsame54-xpro>`__
 
+SAME7x
+^^^^^^
+
+- `Microchip SAME70 Xplained <https://www.microchip.com/en-us/development-tool/ATSAME70-XPLD>`_
+- `QMTECH ATSAME70N19 <https://www.aliexpress.com/item/1005003173783268.html>`_
+
 SAMG
 ^^^^
 
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 188b561d7..8f25141b8 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -207,6 +207,8 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui
     // Open endpoint pair with usbd helper
     TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_BULK, &p_vendor->ep_out, &p_vendor->ep_in), 0);
 
+    drv_len += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
+
     // Prepare for incoming data
     if ( p_vendor->ep_out )
     {

From 97d5d1e491565d6d546bcf27af1ff3525f3df722 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 17 Jul 2021 18:51:33 +0900
Subject: [PATCH 0506/2085] add files for video class device

---
 src/class/video/video.h        | 284 ++++++++++++++++++++++++
 src/class/video/video_device.c | 384 +++++++++++++++++++++++++++++++++
 src/class/video/video_device.h |  50 +++++
 src/device/usbd.c              |  12 ++
 src/tusb.h                     |   4 +
 src/tusb_option.h              |   4 +
 6 files changed, 738 insertions(+)
 create mode 100644 src/class/video/video.h
 create mode 100644 src/class/video/video_device.c
 create mode 100644 src/class/video/video_device.h

diff --git a/src/class/video/video.h b/src/class/video/video.h
new file mode 100644
index 000000000..55ffffa7f
--- /dev/null
+++ b/src/class/video/video.h
@@ -0,0 +1,284 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Koji KITAYAMA
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_VIDEO_H_
+#define TUSB_VIDEO_H_
+
+#include "common/tusb_common.h"
+
+/* A.2 */
+typedef enum {
+  VIDEO_SUBCLASS_UNDEFINED = 0x00,
+  VIDEO_SUBCLASS_CONTROL,
+  VIDEO_SUBCLASS_STREAMING,
+  VIDEO_SUBCLASS_INTERFACE_COLLECTION,
+} video_subclass_type_t;
+
+/* A.3 */
+typedef enum
+{
+  VIDEO_INT_PROTOCOL_CODE_UNDEF = 0x00,
+  VIDEO_INT_PROTOCOL_CODE_15,
+} video_interface_protocol_code_t;
+
+/* A.5 */
+typedef enum
+{
+  VIDEO_CS_VC_INTERFACE_VC_DESCRIPTOR_UNDEF = 0x00,
+  VIDEO_CS_VC_INTERFACE_HEADER,
+  VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL,
+  VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL,
+  VIDEO_CS_VC_INTERFACE_SELECTOR_UNIT,
+  VIDEO_CS_VC_INTERFACE_PROCESSING_UNIT,
+  VIDEO_CS_VC_INTERFACE_EXTENSION_UNIT,
+  VIDEO_CS_VC_INTERFACE_ENCODING_UNIT,
+} vide_cs_vc_interface_subtype_t;
+
+/* A.6 */
+typedef enum
+{
+  VIDEO_CS_VS_INTERFACE_VS_DESCRIPTOR_UNDEF = 0x00,
+  VIDEO_CS_VS_INTERFACE_INPUT_HEADER,
+  VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER,
+  VIDEO_CS_VS_INTERFACE_STILL_IMAGE_FRAME,
+  VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED,
+  VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED,
+  VIDEO_CS_VS_INTERFACE_FORMAT_MJPEG,
+  VIDEO_CS_VS_INTERFACE_FRAME_MJPEG,
+  VIDEO_CS_VS_INTERFACE_FORMAT_MPEG2TS      = 0x0A,
+  VIDEO_CS_VS_INTERFACE_FORMAT_DV           = 0x0c,
+  VIDEO_CS_VS_INTERFACE_COLORFORMAT,
+  VIDEO_CS_VS_INTERFACE_FORMAT_FRAME_BASED  = 0x10,
+  VIDEO_CS_VS_INTERFACE_FRAME_FRAME_BASED,
+  VIDEO_CS_VS_INTERFACE_FORMAT_STREAM_BASED,
+  VIDEO_CS_VS_INTERFACE_FORMAT_H264,
+  VIDEO_CS_VS_INTERFACE_FRAME_H264,
+  VIDEO_CS_VS_INTERFACE_FORMAT_H264_SIMULCAST,
+  VIDEO_CS_VS_INTERFACE_FORMAT_VP8,
+  VIDEO_CS_VS_INTERFACE_FRAME_VP8,
+  VIDEO_CS_VS_INTERFACE_FORMAT_VP8_SIMULCAST,
+} video_cs_vs_interface_subtype_t;
+
+/* A.8 */
+typedef enum
+{
+  VIDEO_REQUEST_UNDEF = 0x00,
+  VIDEO_REQUEST_SET_CUR,
+  VIDEO_REQUEST_SET_CUR_ALL = 0x11,
+  VIDEO_REQUEST_GET = 0x80,
+  VIDEO_REQUEST_GET_CUR,
+  VIDEO_REQUEST_GET_MIN,
+  VIDEO_REQUEST_GET_MAX,
+  VIDEO_REQUEST_GET_RES,
+  VIDEO_REQUEST_GET_LEN,
+  VIDEO_REQUEST_GET_INFO,
+  VIDEO_REQUEST_GET_DEF,
+  VIDEO_REQUEST_GET_CUR_ALL = 0x91,
+  VIDEO_REQUEST_GET_MIN_ALL,
+  VIDEO_REQUEST_GET_MAX_ALL,
+  VIDEO_REQUEST_GET_RES_ALL,
+  VIDEO_REQUEST_GET_DEF_ALL = 0x97
+} video_control_request_t;
+
+/* B. Terminal Types */
+typedef enum
+{
+  VIDEO_TT_VENDOR_SPECIFIC         = 0x0100,
+  VIDEO_TT_STREAMING,
+  VIDEO_ITT_VENDOR_SPECIFIC        = 0x0200,
+  VIDEO_ITT_CAMERA,
+  VIDEO_ITT_MEDIA_TRANSPORT_INPUT,
+  VIDEO_OTT_VENDOR_SPECIFIC        = 0x0300,
+  VIDEO_OTT_DISPLAY,
+  VIDEO_OTT_MEDIA_TRANSPORT_OUTPUT,
+  VIDEO_TT_EXTERNAL_VENDOR_SPEIFIC = 0x0400,
+  VIDEO_TT_COMPOSITE_CONNECTOR,
+  VIDEO_TT_SVIDEO_CONNECTOR,
+  VIDEO_TT_COMPONENT_CONNECTOR,
+} video_terminal_type_t;
+
+/* 2.3.4.2 */
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint16_t bcdUVC;
+  uint16_t wTotalLength;
+  uint32_t dwClockFrequency;
+  uint8_t  bInCollection;
+  uint8_t  baInterfaceNr[];
+} tusb_desc_video_control_interface_t;
+
+/* 3.9.2.1 */
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bNumFormats;
+  uint16_t wTotalLength;
+  uint8_t  bEndpointAddress;
+  uint8_t  bmInfo;
+  uint8_t  bTerminalLink;
+  uint8_t  bStillCaptureMethod;
+  uint8_t  bTriggerSupport;
+  uint8_t  bTriggerUsage;
+  uint8_t  bControlSize;
+  uint8_t  bmaControls[];
+} tusb_desc_video_streaming_interface_input_t;
+
+/* 3.9.2.2 */
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bNumFormats;
+  uint16_t wTotalLength;
+  uint8_t  bEndpointAddress;
+  uint8_t  bTerminalLink;
+  uint8_t  bControlSize;
+  uint8_t  bmaControls[];
+} tusb_desc_video_streaming_interface_output_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bNumFormats;
+  uint16_t wTotalLength;
+  uint8_t  bEndpointAddress;
+  union {
+    struct {
+      uint8_t  bmInfo;
+      uint8_t  bTerminalLink;
+      uint8_t  bStillCaptureMethod;
+      uint8_t  bTriggerSupport;
+      uint8_t  bTriggerUsage;
+      uint8_t  bControlSize;
+      uint8_t  bmaControls[];
+    } in;
+    struct {
+      uint8_t  bEndpointAddress;
+      uint8_t  bTerminalLink;
+      uint8_t  bControlSize;
+      uint8_t  bmaControls[];
+    } out;
+} tusb_desc_video_streaming_interface_t;
+
+#define TUD_VIDEO_DESC_IAD_LEN                    8
+#define TUD_VIDEO_DESC_STD_VC_LEN                 9
+#define TUD_VIDEO_DESC_CS_VC_LEN                  12
+#define TUD_VIDEO_DESC_INPUT_TERM_LEN             8
+#define TUD_VIDEO_DESC_OUTPUT_TERM_LEN            9
+#define TUD_VIDEO_DESC_STD_VS_LEN                 9
+#define TUD_VIDEO_DESC_CS_VS_IN_LEN               13
+#define TUD_VIDEO_DESC_CS_VS_OUT_LEN              9
+#define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN      27
+#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN 38
+#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN 26
+
+/* 2.2 compression formats */
+#define TUD_VIDEO_GUID_YUY2   0x59,0x55,0x59,0x32,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00
+#define TUD_VIDEO_GUID_NV12   0x4E,0x56,0x31,0x32,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00
+#define TUD_VIDEO_GUID_M420   0x4D,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00
+#define TUD_VIDEO_GUID_I420   0x49,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00
+
+#define TUD_VIDEO_DESC_IAD(_firstitfs, _nitfs, _stridx) \
+  TUD_VIDEO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, \
+  _firstitfs, _nitfs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_INTERFACE_COLLECTION, \
+  VIDEO_INT_PROTOCOL_CODE_UNDEF, _stridx
+
+#define TUD_VIDEO_DESC_STD_VC(_itfnum, _nEPs, _stridx) \
+  TUD_VIDEO_DESC_STD_VC_LEN, TUSB_DESC_INTERFACE, _itfnum, /* fixed to zero */ 0x00, \
+  _nEPs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_CONTROL, VIDEO_INT_PROTOCOL_CODE_15, _stridx
+
+/* 3.7.2 */
+#define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, _coll, ...)	\
+  TUD_VIDEO_DESC_CS_VC_LEN + _coll, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \
+  U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE(_totallen + TUD_VIDEO_DESC_CS_AC_LEN), \
+  U32_TO_U8S_LE(_clkfreq), _coll, __VA_ARGS__
+
+/* 3.7.2.1 */
+#define TUD_VIDEO_DESC_INPUT_TERM(_tid, _tt, _at, _stridx) \
+  TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL, \
+    _tid, U16_TO_U8S_LE(_tt), _at, _ti
+
+/* 3.7.2.2 */
+#define TUD_VIDEO_DESC_OUTPUT_TERM(_tid, _tt, _at, _srcid, _stridx) \
+  TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, \
+    _tid, U16_TO_U8S_LE(_tt), _at, _ti
+
+/* 3.9.1 */
+#define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx)   \
+  TUD_VIDEO_DESC_STD_VC_LEN, TUSB_DESC_INTERFACE, _itfnum, _alt, \
+  _epn, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_STREAMING, VIDEO_INT_PROTOCOL_CODE_15, _stridx
+
+/* 3.9.2.1 */
+#define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totlen, _epn, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, ...) \
+  TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \
+  VIDEO_CS_VS_INTERFACE_INPUT_HEADER, _numfmt, \
+  U16_TO_U8S_LE(_totlen + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz)), \
+  _epn, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, __VA_ARGS__
+
+/* 3.9.2.2 */
+#define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totlen, _epn, _inf, _termlnk, _ctlsz, ...) \
+  TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \
+  VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, _numfmt, \
+  U16_TO_U8S_LE(_totlen + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz)), \
+  _epn, _inf, _termlnk,  _trgusg, _ctlsz, __VA_ARGS__
+
+/* Uncompressed 3.1.1 */
+#define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfrmdesc, \
+  _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15, \
+  _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, \
+  _fmtidx, _numfrmdesc,\
+  _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15,\
+  _bitsperpix, _frmidx, _asrx,  _asry, _interlace, _cp
+
+/* Uncompressed 3.1.2 Table 3-3 */
+#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \
+  TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \
+  _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
+  U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), 0, \
+  U32_TO_U8S_LE(_minfrminterval), U32_TO_U8S_LE(_maxfrminterval), U32_TO_U8S_LE(_frmintervalstep)
+
+/* Uncompressed 3.1.2 Table 3-4 */
+#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _numfrminterval, ...) \
+  TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN + _numfrminterval * 4, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \
+  _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
+  U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), _numfrminterval, __VA_ARGS__
+
+/* 3.10.1.1 */
+#define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval)
+  7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\
+  U16_TO_U8S_LE(_epsize), _ep_interval
+
+/* 3.10.1.2 */
+#define TUD_VIDEO_DESC_EP_BULK(_ep, _epsize, _ep_interval)
+  7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), _ep_interval
+
+#endif
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
new file mode 100644
index 000000000..12526f43b
--- /dev/null
+++ b/src/class/video/video_device.c
@@ -0,0 +1,384 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Reinhard Panhuber, Jerzy Kasenberg
+ * Copyright (c) 2021 Koji KITAYAMA
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_VIDEO)
+
+#include "device/usbd.h"
+#include "device/usbd_pvt.h"
+
+#include "video_device.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+typedef struct
+{
+  uint8_t itf_ctl;
+  uint8_t itf_in;
+  uint8_t itf_out;
+  uint8_t const *desc_beg;
+  uint8_t const *desc_end;
+  tusb_desc_video_control_interface_t const          *ctl;
+  tusb_desc_video_streaming_interface_input_t const  *stm_in;
+  tusb_desc_video_streaming_interface_output_t const *stm_out;
+  uint8_t ep_notif; /* notification */
+  uint8_t ep_in;    /* video IN */
+  uint8_t ep_sti;   /* still image IN */
+  uint8_t ep_out;   /* video OUT */
+
+  /*------------- From this point, data is not cleared by bus reset -------------*/
+
+  // Endpoint Transfer buffer
+  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE];
+
+} videod_interface_t;
+
+#define ITF_MEM_RESET_SIZE   offsetof(cdcd_interface_t, wanted_char)
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
+
+static tusb_desc_interface_t const* videod_next_interface_desc(void const *beg, void const *end)
+{
+  for (void const *cur = tu_desc_next(beg); cur < end; cur = tu_desc_next(cur)) {
+    if (TUSB_DESC_INTERFACE != tu_desc_type(cur))
+      return (uint8_t const*)cur;
+  }
+}
+
+static tusb_desc_interface_t const* videod_find_interface_desc(void const *beg, void const *end, unsigned itfnum)
+{
+  tusb_desc_interface_t const *cur = (tusb_desc_interface_t const *)beg;
+  for (; cur; cur = videod_next_interface_desc(cur, end)) {
+    if (cur->bInterfaceNumber == itfnum)
+      return cur;
+  }
+  return NULL;
+}
+
+static void _prep_out_transaction (cdcd_interface_t* p_cdc)
+{
+  uint8_t const rhport = TUD_OPT_RHPORT;
+  uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff);
+
+  // Prepare for incoming data but only allow what we can store in the ring buffer.
+  // TODO Actually we can still carry out the transfer, keeping count of received bytes
+  // and slowly move it to the FIFO when read().
+  // This pre-check reduces endpoint claiming
+  TU_VERIFY(available >= sizeof(p_cdc->epout_buf), );
+
+  // claim endpoint
+  TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out), );
+
+  // fifo can be changed before endpoint is claimed
+  available = tu_fifo_remaining(&p_cdc->rx_ff);
+
+  if ( available >= sizeof(p_cdc->epout_buf) )
+  {
+    usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf));
+  }else
+  {
+    // Release endpoint since we don't make any transfer
+    usbd_edpt_release(rhport, p_cdc->ep_out);
+  }
+}
+
+//--------------------------------------------------------------------+
+// APPLICATION API
+//--------------------------------------------------------------------+
+bool tud_video_n_connected(uint8_t itf)
+{
+  // DTR (bit 0) active  is considered as connected
+  return tud_ready() && tu_bit_test(_cdcd_itf[itf].line_state, 0);
+}
+
+//--------------------------------------------------------------------+
+// READ API
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// WRITE API
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// USBD Driver API
+//--------------------------------------------------------------------+
+void videod_init(void)
+{
+  tu_memclr(_videod_itf, sizeof(_videod_itf));
+
+  for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i)
+  {
+    videod_interface_t* p_video = &_videod_itf[i];
+
+    // TODO
+  }
+}
+
+void videod_reset(uint8_t rhport)
+{
+  (void) rhport;
+
+  for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i)
+  {
+    videod_interface_t* p_video = &_videod_itf[i];
+
+    // TODO
+    tu_memclr(p_video, ITF_MEM_RESET_SIZE);
+  }
+}
+
+uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
+{
+  TU_VERIFY(TUSB_CLASS_VIDEO           == itf_desc->bInterfaceClass &&
+            VIDEO_SUBCLASS_CONTROL     == itf_desc->bInterfaceSubClass &&
+            VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bFunctionProtool, 0);
+
+  /* Find available interface */
+  videod_interface_t *p_video = NULL;
+  for (unsigned video_id = 0; video_id < CFG_TUD_VIDEO; ++video_id) {
+    if (!_videod_itf[video_id].itf_in && !_videod_itf[video_id].itf_out) {
+      p_video = &_videod_itf[video_id];
+      break;
+    }
+  }
+  TU_ASSERT(p_video, 0);
+
+  /*------------- Video Control Interface -------------*/
+  TU_VERIFY(itf_desc->bNumEndpoints < 2, 0); /* support only 1 notification endpoint */
+  unsigned itf_ctl = itf_desc->bInterfaceNumber;
+  unsigned drv_len = sizeof(*itf_desc);
+  tusb_desc_endpoint_t const * desc_ep = NULL;
+
+  uint8_t const *p_desc = tu_desc_next(itf_desc);
+  tusb_desc_video_control_interface_t const *ctl = (tusb_desc_video_control_interface_t const*)p_desc;
+  TU_VERIFY(TUSB_DESC_CS_INTERFACE       == ctl->bDescriptorType &&
+            VIDEO_CS_VC_INTERFACE_HEADER == ctl->bDescriptorSubType, 0);
+
+  if (itf_desc->bNumEndpoints) { /* has a notification endpoint */
+    p_desc = tu_desc_next(ctl);
+    /* skip to the notification endpoint descriptor */
+    while (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc) && drv_len <= max_len ) {
+      p_desc   = tu_desc_next(p_desc);
+    }
+    desc_ep = (tusb_desc_endpoint_t const *)p_desc;
+  }
+  drv_len += tu_desc_len(ctl)  + ctl->wTotalLength;
+  p_desc   = tu_desc_next(ctl) + ctl->wTotalLength;
+  TU_VERIFY(drv_len <= max_len, 0);
+
+  /*------------- Video Stream Interface -------------*/
+  uint8_t itf_in  = 0, itf_out = 0;
+  tusb_desc_video_streaming_interface_input_t  const *stm_in  = NULL;
+  tusb_desc_video_streaming_interface_output_t const *stm_out = NULL;
+
+  for (unsigned itf_stm = 0; itf_stm < ctl->bInCollection; ++itf_stm) {
+    itf_desc = (tusb_desc_interface_t const *)p_desc;
+    TU_VERIFY(TUSB_DESC_INTERFACE        == itf_desc->bDescriptorType &&
+              0                          == itf_desc->bInterfaceNumber &&
+              TUSB_CLASS_VIDEO           == itf_desc->bInterfaceClass &&
+              VIDEO_SUBCLASS_STREAMING   == itf_desc->bInterfaceSubClass &&
+              VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bFunctionProtool &&
+              0 == itf_desc->bNumEndpoints, 0);
+    drv_len += sizeof(*itf_desc);
+    p_desc   = tu_desc_next(itf_desc);
+    TU_VERIFY(TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc));
+    tusb_desc_video_streaming_interface_t const *stm = (tusb_desc_video_streaming_interface_t const *)p_desc;
+    TU_VERIFY(TUSB_DESC_CS_INTERFACE == stm->bDescriptorType);
+    switch (stm->bDescriptorSubType) {
+    default: return 0;
+    case VIDEO_CS_VS_INTERFACE_INPUT_HEADER:
+      TU_VERIFY(0 == itf_in, 0);
+      itf_in = itf_desc->bInterfaceNumber;
+      stm_in = (tusb_desc_video_streaming_interface_input_t const*)stm;
+      break;
+    case VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER:
+      TU_VERIFY(0 == itf_out, 0);
+      itf_out = itf_desc->bInterfaceNumber;
+      stm_out = (tusb_desc_video_streaming_interface_output_t const*)stm;
+      break;
+    }
+    drv_len += tu_desc_len(stm)  + stm->wTotalLength;
+    p_desc   = tu_desc_next(stm) + ctl->wTotalLength;
+  }
+  if (desc_ep) {
+    /* open the notification endpoint */
+    TU_ASSERT( usbd_edpt_open(rhport, desc_ep), 0);
+    p_video->ep_notif = desc_ep->bEndpointAddress;
+  }
+  p_video->itf_ctl = itf_ctl;
+  p_video->itf_in  = itf_in;
+  p_video->itf_out = itf_out;
+  p_video->ctl     = ctl;
+  p_video->stm_in  = stm_in;
+  p_video->stm_out = stm_out;
+
+  return drv_len;
+}
+
+// Invoked when a control transfer occurred on an interface of this class
+// Driver response accordingly to the request and the transfer stage (setup/data/ack)
+// return false to stall control endpoint (e.g unsupported request)
+bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
+{
+  /* Standard request */
+  if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) {
+    tusb_desc_interface_t const *itf;
+    unsigned itf;
+    switch (p_request->bRequest) {
+    case TUSB_REQ_GET_INTERFACE:
+      itf = tu_u16_low(p_request->wIndex);
+      return audiod_get_interface(rhport, p_request);
+    case TUSB_REQ_SET_INTERFACE:
+      itf = videod_find_interface_desc(void const *beg, void const *end, unsigned itfnum)
+      itf = tu_u16_low(p_request->wIndex);
+      
+      return audiod_set_interface(rhport, p_request);
+      /* Unknown/Unsupported request */
+    default: TU_BREAKPOINT(); return false;
+    }
+  }
+
+  uint8_t itf = 0;
+  videod_interface_t* p_video = _videod_itf;
+
+  // Identify which interface to use
+  for ( ; ; itf++, p_video++) {
+    if (itf >= TU_ARRAY_SIZE(_videod_itf)) return false;
+    if ( p_video->itf_num == request->wIndex ) break;
+  }
+
+  if (stage == CONTROL_STAGE_SETUP) {
+    TU_VERIFY((TUSB_DIR_IN_MASK & request->bmRequestType) ==
+	      (TUSB_DIR_IN_MASK & request->bRequest));
+  }
+
+
+  unsigned cs = TU_U16_HIGH(request->wValue);
+
+
+  unsigned req = request->bRequest;
+  switch (request->bRequest) {
+  case VIDEO_REQUEST_GET_INFO:
+    TU_VERIFY(1 == request->wLength);
+    
+    break;
+  case VIDEO_REQUEST_SET_CUR:
+    if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Set Current Setting Attribute\r\n");
+        tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t));
+    } else if ( stage == CONTROL_STAGE_ACK) {
+      if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding);
+    }
+    break;
+  case VIDEO_REQUEST_GET_CUR:
+    if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Set Current Setting Attribute\r\n");
+        tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t));
+    } else if ( stage == CONTROL_STAGE_ACK) {
+      if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding);
+    }
+    break;
+  default: return false; // stall unsupported request
+  }
+
+  return true;
+}
+
+bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+{
+  (void) result;
+
+  uint8_t itf;
+  videod_interface_t* p_video;
+
+  // Identify which interface to use
+  for (itf = 0; itf < CFG_TUD_CDC; itf++)
+  {
+    p_video = &_videod_itf[itf];
+    if ( ( ep_addr == p_video->ep_out ) || ( ep_addr == p_video->ep_in ) ) break;
+  }
+  TU_ASSERT(itf < CFG_TUD_CDC);
+
+  // Received new data
+  if ( ep_addr == p_video->ep_out )
+  {
+    tu_fifo_write_n(&p_video->rx_ff, &p_video->epout_buf, xferred_bytes);
+    
+    // Check for wanted char and invoke callback if needed
+    if ( tud_cdc_rx_wanted_cb && (((signed char) p_video->wanted_char) != -1) )
+    {
+      for ( uint32_t i = 0; i < xferred_bytes; i++ )
+      {
+        if ( (p_video->wanted_char == p_video->epout_buf[i]) && !tu_fifo_empty(&p_video->rx_ff) )
+        {
+          tud_cdc_rx_wanted_cb(itf, p_video->wanted_char);
+        }
+      }
+    }
+    
+    // invoke receive callback (if there is still data)
+    if (tud_cdc_rx_cb && !tu_fifo_empty(&p_video->rx_ff) ) tud_cdc_rx_cb(itf);
+    
+    // prepare for OUT transaction
+    _prep_out_transaction(p_video);
+  }
+  
+  // Data sent to host, we continue to fetch from tx fifo to send.
+  // Note: This will cause incorrect baudrate set in line coding.
+  //       Though maybe the baudrate is not really important !!!
+  if ( ep_addr == p_video->ep_in )
+  {
+    // invoke transmit callback to possibly refill tx fifo
+    if ( tud_cdc_tx_complete_cb ) tud_cdc_tx_complete_cb(itf);
+
+    if ( 0 == tud_cdc_n_write_flush(itf) )
+    {
+      // If there is no data left, a ZLP should be sent if
+      // xferred_bytes is multiple of EP Packet size and not zero
+      if ( !tu_fifo_count(&p_video->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE-1))) )
+      {
+        if ( usbd_edpt_claim(rhport, p_video->ep_in) )
+        {
+          usbd_edpt_xfer(rhport, p_video->ep_in, NULL, 0);
+        }
+      }
+    }
+  }
+
+  // nothing to do with notif endpoint for now
+
+  return true;
+}
+
+#endif
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
new file mode 100644
index 000000000..b077a9a76
--- /dev/null
+++ b/src/class/video/video_device.h
@@ -0,0 +1,50 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2021 Koji KITAYAMA
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_VIDEO_DEVICE_H_
+#define TUSB_VIDEO_DEVICE_H_
+
+#include "video_device.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// INTERNAL USBD-CLASS DRIVER API
+//--------------------------------------------------------------------+
+void     videod_init           (void);
+void     videod_reset          (uint8_t rhport);
+uint16_t videod_open           (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
+bool     videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+bool     videod_xfer_cb        (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index cf3ecea42..87f0e05ca 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -143,6 +143,18 @@ static usbd_class_driver_t const _usbd_driver[] =
   },
   #endif
 
+  #if CFG_TUD_VIDEO
+  {
+    DRIVER_NAME("VIDEO")
+    .init             = videod_init,
+    .reset            = videod_reset,
+    .open             = videod_open,
+    .control_xfer_cb  = videod_control_xfer_cb,
+    .xfer_cb          = videod_xfer_cb,
+    .sof              = NULL
+  },
+  #endif
+
   #if CFG_TUD_MIDI
   {
     DRIVER_NAME("MIDI")
diff --git a/src/tusb.h b/src/tusb.h
index b52f8839a..f2f72a510 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -80,6 +80,10 @@
   #include "class/audio/audio_device.h"
 #endif
 
+  #if CFG_TUD_VIDEO
+    #include "class/video/video_device.h"
+  #endif
+
   #if CFG_TUD_MIDI
     #include "class/midi/midi_device.h"
   #endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index ad2a26a66..a728581f6 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -241,6 +241,10 @@
   #define CFG_TUD_AUDIO           0
 #endif
 
+#ifndef CFG_TUD_VIDEO
+  #define CFG_TUD_VIDEO           0
+#endif
+
 #ifndef CFG_TUD_MIDI
   #define CFG_TUD_MIDI            0
 #endif

From e8de4113223f2a435bde87c13a4d99c1d886619f Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 19 Jul 2021 21:28:05 +0900
Subject: [PATCH 0507/2085] cleanup open()

---
 src/class/video/video.h        |  20 +-
 src/class/video/video_device.c | 450 ++++++++++++++++++++++++---------
 src/class/video/video_device.h |  13 +-
 3 files changed, 358 insertions(+), 125 deletions(-)

diff --git a/src/class/video/video.h b/src/class/video/video.h
index 55ffffa7f..f994c7fed 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -103,6 +103,14 @@ typedef enum
   VIDEO_REQUEST_GET_DEF_ALL = 0x97
 } video_control_request_t;
 
+/* A.9 */
+typedef enum
+{
+  VIDEO_CTL_SEL_UNDEF = 0x00,
+  VIDEO_CTL_SEL_VIDEO_POWER_MODE_CONTROL,
+  VIDEO_CTL_SEL_REQUEST_ERROR_CODE_CONTROL,
+} video_interface_control_selector_t;
+
 /* B. Terminal Types */
 typedef enum
 {
@@ -130,7 +138,7 @@ typedef struct TU_ATTR_PACKED {
   uint32_t dwClockFrequency;
   uint8_t  bInCollection;
   uint8_t  baInterfaceNr[];
-} tusb_desc_video_control_interface_t;
+} tusb_desc_cs_video_ctl_itf_hdr_t;
 
 /* 3.9.2.1 */
 typedef struct TU_ATTR_PACKED {
@@ -147,7 +155,7 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bTriggerUsage;
   uint8_t  bControlSize;
   uint8_t  bmaControls[];
-} tusb_desc_video_streaming_interface_input_t;
+} tusb_desc_cs_video_stm_itf_in_hdr_t;
 
 /* 3.9.2.2 */
 typedef struct TU_ATTR_PACKED {
@@ -160,7 +168,7 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  bTerminalLink;
   uint8_t  bControlSize;
   uint8_t  bmaControls[];
-} tusb_desc_video_streaming_interface_output_t;
+} tusb_desc_cs_video_stm_itf_out_hdr_t;
 
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
@@ -178,14 +186,14 @@ typedef struct TU_ATTR_PACKED {
       uint8_t  bTriggerUsage;
       uint8_t  bControlSize;
       uint8_t  bmaControls[];
-    } in;
+    } input;
     struct {
       uint8_t  bEndpointAddress;
       uint8_t  bTerminalLink;
       uint8_t  bControlSize;
       uint8_t  bmaControls[];
-    } out;
-} tusb_desc_video_streaming_interface_t;
+    } output;
+} tusb_desc_cs_video_stm_itf_hdr_t;
 
 #define TUD_VIDEO_DESC_IAD_LEN                    8
 #define TUD_VIDEO_DESC_STD_VC_LEN                 9
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 12526f43b..637e7a127 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -38,16 +38,38 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
+typedef struct {
+  uint8_t num;
+  uint8_t alt;
+} itf_setting_t;
+
+typedef struct {
+  tusb_desc_interface_t            std;
+  tusb_desc_cs_video_ctl_itf_hdr_t ctl;
+} tusb_desc_vc_itf_t;
+
+typedef struct {
+  tusb_desc_interface_t            std;
+  tusb_desc_cs_video_stm_itf_hdr_t stm;
+} tusb_desc_vs_itf_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t bLength;
+  uint8_t bDescriptorType;
+  uint8_t bDescriptorSubtype;
+  union {
+    uint8_t bId;
+    uint8_t bTerminalId;
+    uint8_t bUnitId;
+  };
+} tusb_desc_cs_video_entity_itf_t;
+
 typedef struct
 {
-  uint8_t itf_ctl;
-  uint8_t itf_in;
-  uint8_t itf_out;
-  uint8_t const *desc_beg;
-  uint8_t const *desc_end;
-  tusb_desc_video_control_interface_t const          *ctl;
-  tusb_desc_video_streaming_interface_input_t const  *stm_in;
-  tusb_desc_video_streaming_interface_output_t const *stm_out;
+  void const *beg;
+  void const *end;
+  tusb_desc_vc_itf_t const *vc;    /* current video control interface */
+  tusb_desc_vs_itf_t const *vs[2]; /* current video streaming interfaces */
   uint8_t ep_notif; /* notification */
   uint8_t ep_in;    /* video IN */
   uint8_t ep_sti;   /* still image IN */
@@ -68,24 +90,266 @@ typedef struct
 //--------------------------------------------------------------------+
 CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
 
-static tusb_desc_interface_t const* videod_next_interface_desc(void const *beg, void const *end)
+/** Find the first descriptor with the specified descriptor type.
+ *
+ * @param[in] beg     The head of descriptor byte array.
+ * @param[in] end     The tail of descriptor byte array.
+ * @param[in] target  The target descriptor type.
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* videod_find_desc(void const *beg, void const *end, uint8_t target)
 {
-  for (void const *cur = tu_desc_next(beg); cur < end; cur = tu_desc_next(cur)) {
-    if (TUSB_DESC_INTERFACE != tu_desc_type(cur))
+  for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) {
+    if (target != tu_desc_type(cur))
       return (uint8_t const*)cur;
   }
+  return end;
 }
 
-static tusb_desc_interface_t const* videod_find_interface_desc(void const *beg, void const *end, unsigned itfnum)
+/** Find the first interface descriptor with the specified interface number and alternate setting number.
+ *
+ * @param[in] beg     The head of descriptor byte array.
+ * @param[in] end     The tail of descriptor byte array.
+ * @param[in] itfnum  The target interface number.
+ * @param[in] altnum  The target alternate setting number.
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* videod_find_desc_itf(void const *beg, void const *end, unsigned itfnum, unsigned altnum)
 {
-  tusb_desc_interface_t const *cur = (tusb_desc_interface_t const *)beg;
-  for (; cur; cur = videod_next_interface_desc(cur, end)) {
-    if (cur->bInterfaceNumber == itfnum)
-      return cur;
+  for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_INTERFACE)) {
+    tusb_desc_interface_t const *itf = (tusb_desc_interface_t const *)cur;
+    if (itf->bInterfaceNumber == itfnum && itf->bAlternateSettings == altnum) {
+      return itf;
+    }
+    cur = tu_desc_next(cur);
+  }
+  return end;
+}
+
+/** Find the first input or output terminal descriptor with the specified terminal id.
+ *
+ * @param[in] beg     The head of descriptor byte array.
+ * @param[in] end     The tail of descriptor byte array.
+ * @param[in] termid  The target terminal id.
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* videod_find_desc_term(void const *beg, void const *end, unsigned termid)
+{
+  for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
+    tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
+    if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL  == itf->bDescriptorSubtype ||
+         VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL == itf->bDescriptorSubtype) &&
+        itf->bTerminalId == termid) {
+      return itf;
+    }
+    cur = tu_desc_next(cur);
+  }
+  return end;
+}
+
+/** Find the first selector/processing/extension/encoding unit descriptor with the specified unit id.
+ *
+ * @param[in] beg     The head of descriptor byte array.
+ * @param[in] end     The tail of descriptor byte array.
+ * @param[in] unitid  The target unit id.
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* videod_find_desc_unit(void const *beg, void const *end, unsigned unitid)
+{
+  for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
+    tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
+    if (VIDEO_CS_VC_INTERFACE_SELECTOR_UNIT <= itf->bDescriptorSubtype &&
+        itf->bDescriptorSubtype <= VIDEO_CS_VC_INTERFACE_ENCODING_UNIT &&
+        itf->bUnitId == unitid) {
+      return itf;
+    }
+    cur = tu_desc_next(cur);
+  }
+  return end;
+}
+
+/** Set the specified alternate setting to own video control interface.
+ *
+ * @param[in,out] self     The context.
+ * @param[in]     altnum   The target alternate setting number.
+ *
+ * @return The next descriptor after the video control interface descriptor.
+ * @retval NULL   did not found interface descriptor or alternate setting */
+static void const* videod_set_vc_itf(videod_interface_t *self, unsigned altnum)
+{
+  void const *beg = self->beg;
+  void const *end = self->end;
+  /* The head descriptor is a video control interface descriptor. */
+  unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber;
+  void const *cur = videod_find_desc_itf(beg, end, itfnum, altnum);
+  TU_VERIFY(cur < end, NULL);
+
+  tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
+  /* Support for up to 2 streaming interfaces only. */
+  TU_VERIFY(vc->ctl.bInCollection < 3, NULL);
+
+  /* Close the previous notification endpoint if it is opened */
+  if (self->ep_notif) {
+    usbd_edpt_close(rhport, self->ep_notif);
+    self->ep_notif = 0;
+  }
+  /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
+  cur += vc->std.bLength + vc->ctl.bLength;
+  /* Update to point the end of the video control interface descriptor. */
+  end  = cur + vc->ctl.wTotalLength;
+  /* Open the notification endpoint if it exist. */
+  if (vc->std.bNumEndpoints) {
+    /* Support for 1 endpoint only. */
+    TU_VERIFY(1 == vc->std.bNumEndpoints, NULL);
+    /* Find the notification endpoint descriptor. */
+    cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT);
+    TU_VERIFY(cur < end, NULL);
+    tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur;
+    /* Open the notification endpoint */
+    TU_ASSERT(usbd_edpt_open(rhport, notif), NULL);
+    self->ep_notif = notif->bEndpointAddress;
+  }
+  self->vc = vc;
+  return end;
+}
+
+/** Set the specified alternate setting to own video control interface.
+ *
+ * @param[in,out] self     The context.
+ * @param[in]     itfnum   The target interface number.
+ * @param[in]     altnum   The target alternate setting number.
+ *
+ * @return The next descriptor after the video control interface descriptor.
+ * @retval NULL   did not found interface descriptor or alternate setting */
+static void const* videod_set_vs_itf(videod_interface_t *self, unsigned itfnum, unsigned altnum)
+{
+  unsigned i;
+  tusb_desc_vc_itf_t const *vc = self->vc;
+  void const *end = self->end;
+  /* Set the end of the video control interface descriptor. */
+  void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength;
+
+  /* Check itfnum is valid */
+  unsigned bInCollection = self->vc->ctl.bInCollection;
+  for (i = 0; (i < bInCollection) && (vc->ctl.baInterfaceNr[i] != itfnum); ++i) ;
+  TU_VERIFY(i < bInCollection, NULL);
+  
+  cur = videod_find_desc_itf(cur, end, itfnum, altnum);
+  TU_VERIFY(cur < end, NULL);
+  tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur;
+  /* Advance to the next descriptor after the class-specific VS interface header descriptor. */
+  cur += vs->std.bLength + vs->stm.bLength;
+  /* Update to point the end of the video control interface descriptor. */
+  end  = cur + vs->stm.wTotalLength;
+
+  switch (vs->stm.bDescriptorSubType) {
+  default: return end;
+  case VIDEO_CS_VS_INTERFACE_INPUT_HEADER:
+    /* Support for up to 2 endpoint only. */
+    TU_VERIFY(vc->std.bNumEndpoints < 3, NULL);
+    if (self->ep_sti) {
+      usbd_edpt_close(rhport, self->ep_sti);
+      self->ep_sti = 0;
+    }
+    if (self->ep_in) {
+      usbd_edpt_close(rhport, self->ep_in);
+      self->ep_in  = 0;
+    }
+    if (i = 0; i < vs->std.bNumEndpoints; ++i) {
+      cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT);
+      TU_VERIFY(cur < end, NULL);
+      tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
+      if (vs->stm.bEndpointAddress == ep->bEndpointAddress) {
+        /* video input endpoint */
+        TU_ASSERT(!self->ep_in, NULL);
+        TU_ASSERT(usbd_edpt_open(rhport, ep), NULL);
+        self->ep_in  = ep->bEndpointAddress;
+      } else {
+        /* still image input endpoint */
+        TU_ASSERT(!self->ep_sti, NULL);
+        TU_ASSERT(usbd_edpt_open(rhport, ep), NULL);
+        self->ep_sti = ep->bEndpointAddress;
+      }
+      cur += tu_desc_len(cur);
+    }
+    break;
+  case VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER:
+    /* Support for up to 1 endpoint only. */
+    TU_VERIFY(vc->std.bNumEndpoints < 2, NULL);
+    if (self->ep_out) {
+      usbd_edpt_close(rhport, self->ep_out);
+      self->ep_out = 0;
+    }
+    if (vs->std.bNumEndpoints) {
+      cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT);
+      TU_VERIFY(cur < end, NULL);
+      tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
+      if (vs->stm.bEndpointAddress == ep->bEndpointAddress) {
+        /* video output endpoint */
+        TU_ASSERT(usbd_edpt_open(rhport, ep), NULL);
+        self->ep_out = ep->bEndpointAddress;
+      }
+    }
+    break;
+  }
+  for (i = 0; i < sizeof(self->vs)/sizeof(self->vs[0]); ++i) {
+    if (!self->vs[i] || self->vs[i].stm.bInterfaceNumber == vs->stm.bInterfaceNumber) {
+      self->vs[i] = vs;
+      return end;
+    }
   }
   return NULL;
 }
 
+static bool videod_get_itf(uint8_t rhport, videod_interface_t *self, tusb_control_request_t const * request)
+{
+  unsigned altnum = tu_u16_low(p_request->wValue);
+  unsigned itfnum = tu_u16_low(p_request->wLength);
+
+  tusb_desc_vc_itf_t const *vc = self->vc;
+  if (vc->std.bInterfaceNumber == itfnum) {
+    tud_control_xfer(rhport, request, &vc->std.bAlternateSettings, sizeof(vc->std.bAlternateSettings));
+    return true;
+  }
+  for (unsigned i = 0; i < vc->ctl.bInCollection; ++i) {
+    tusb_desc_vs_itf_t const *vs = self->vs[i];
+    if (!vs || vs->std.bInterfaceNumber == itfnum) {
+      continue;
+    }
+    tud_control_xfer(rhport, request, &vs->std.bAlternateSettings, sizeof(vs->std.bAlternateSettings));
+    return true;
+  }
+  return false;
+}
+
+static bool videod_set_itf(uint8_t rhport, videod_interface_t *self, tusb_control_request_t const * request)
+{
+  (void)rhport;
+  unsigned altnum = tu_u16_low(p_request->wValue);
+  unsigned itfnum = tu_u16_low(p_request->wLength);
+
+  tusb_desc_vc_itf_t const *vc = self->vc;
+  if (vc->std.bInterfaceNumber == itfnum) {
+    if (videod_set_vc_itf(self, altnum))
+      return true;
+    return false;
+  }
+  for (unsigned i = 0; i < vc->ctl.bInCollection; ++i) {
+    tusb_desc_vs_itf_t const *vs = self->vs[i];
+    if (!vs || vs->std.bInterfaceNumber == itfnum) {
+      continue;
+    }
+    if (videod_set_vs_itf(self, itfnum, altnum))
+      return true;
+    return false;
+  }
+  return false;
+}
+
 static void _prep_out_transaction (cdcd_interface_t* p_cdc)
 {
   uint8_t const rhport = TUD_OPT_RHPORT;
@@ -165,85 +429,43 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
             VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bFunctionProtool, 0);
 
   /* Find available interface */
-  videod_interface_t *p_video = NULL;
-  for (unsigned video_id = 0; video_id < CFG_TUD_VIDEO; ++video_id) {
-    if (!_videod_itf[video_id].itf_in && !_videod_itf[video_id].itf_out) {
-      p_video = &_videod_itf[video_id];
+  videod_interface_t *self = NULL;
+  for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) {
+    if (!_videod_itf[i].vc) {
+      self = &_videod_itf[i];
       break;
     }
   }
-  TU_ASSERT(p_video, 0);
+  TU_ASSERT(self, 0);
 
+  void const *end = (void const*)itf_desc + max_len;
+  self->beg = itf_desc;
+  self->end = end;
   /*------------- Video Control Interface -------------*/
-  TU_VERIFY(itf_desc->bNumEndpoints < 2, 0); /* support only 1 notification endpoint */
-  unsigned itf_ctl = itf_desc->bInterfaceNumber;
-  unsigned drv_len = sizeof(*itf_desc);
-  tusb_desc_endpoint_t const * desc_ep = NULL;
-
-  uint8_t const *p_desc = tu_desc_next(itf_desc);
-  tusb_desc_video_control_interface_t const *ctl = (tusb_desc_video_control_interface_t const*)p_desc;
-  TU_VERIFY(TUSB_DESC_CS_INTERFACE       == ctl->bDescriptorType &&
-            VIDEO_CS_VC_INTERFACE_HEADER == ctl->bDescriptorSubType, 0);
-
-  if (itf_desc->bNumEndpoints) { /* has a notification endpoint */
-    p_desc = tu_desc_next(ctl);
-    /* skip to the notification endpoint descriptor */
-    while (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc) && drv_len <= max_len ) {
-      p_desc   = tu_desc_next(p_desc);
-    }
-    desc_ep = (tusb_desc_endpoint_t const *)p_desc;
-  }
-  drv_len += tu_desc_len(ctl)  + ctl->wTotalLength;
-  p_desc   = tu_desc_next(ctl) + ctl->wTotalLength;
-  TU_VERIFY(drv_len <= max_len, 0);
-
+  void const* cur = videod_set_vc_itf(self, 0);
+  TU_VERIFY(cur, 0);
+  unsigned bInCollection = self->vc->ctl.bInCollection;
   /*------------- Video Stream Interface -------------*/
-  uint8_t itf_in  = 0, itf_out = 0;
-  tusb_desc_video_streaming_interface_input_t  const *stm_in  = NULL;
-  tusb_desc_video_streaming_interface_output_t const *stm_out = NULL;
+  unsigned itfnum = 0;
+  for (unsigned i = 0; i < bInCollection; ++i) {
+    itfnum = vc->ctl.baInterfaceNr[i];
+    cur = videod_set_vs_itf(self, itfnum, 0);
+    TU_VERIFY(cur, 0);
+  }
 
-  for (unsigned itf_stm = 0; itf_stm < ctl->bInCollection; ++itf_stm) {
-    itf_desc = (tusb_desc_interface_t const *)p_desc;
-    TU_VERIFY(TUSB_DESC_INTERFACE        == itf_desc->bDescriptorType &&
-              0                          == itf_desc->bInterfaceNumber &&
-              TUSB_CLASS_VIDEO           == itf_desc->bInterfaceClass &&
-              VIDEO_SUBCLASS_STREAMING   == itf_desc->bInterfaceSubClass &&
-              VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bFunctionProtool &&
-              0 == itf_desc->bNumEndpoints, 0);
-    drv_len += sizeof(*itf_desc);
-    p_desc   = tu_desc_next(itf_desc);
-    TU_VERIFY(TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc));
-    tusb_desc_video_streaming_interface_t const *stm = (tusb_desc_video_streaming_interface_t const *)p_desc;
-    TU_VERIFY(TUSB_DESC_CS_INTERFACE == stm->bDescriptorType);
-    switch (stm->bDescriptorSubType) {
-    default: return 0;
-    case VIDEO_CS_VS_INTERFACE_INPUT_HEADER:
-      TU_VERIFY(0 == itf_in, 0);
-      itf_in = itf_desc->bInterfaceNumber;
-      stm_in = (tusb_desc_video_streaming_interface_input_t const*)stm;
-      break;
-    case VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER:
-      TU_VERIFY(0 == itf_out, 0);
-      itf_out = itf_desc->bInterfaceNumber;
-      stm_out = (tusb_desc_video_streaming_interface_output_t const*)stm;
+  /* Skip alternate setting interfaces */
+  while (cur < end && TUSB_DESC_INTERFACE == tu_desc_type(cur)) {
+    tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)cur;
+    if (itfnum                              != vs->std.bInterfaceNumber ||
+        TUSB_DESC_CS_INTERFACE              != vs->stm.bDescriptorType  ||
+        (VIDEO_CS_VS_INTERFACE_INPUT_HEADER != vs->stm.bDescriptorSubType &&
+         VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER!= vs->stm.bDescriptorSubType)) {
       break;
     }
-    drv_len += tu_desc_len(stm)  + stm->wTotalLength;
-    p_desc   = tu_desc_next(stm) + ctl->wTotalLength;
+    cur += itf->std.bLength + itf->stm.bLength + itf->stm.wTotalLength;
   }
-  if (desc_ep) {
-    /* open the notification endpoint */
-    TU_ASSERT( usbd_edpt_open(rhport, desc_ep), 0);
-    p_video->ep_notif = desc_ep->bEndpointAddress;
-  }
-  p_video->itf_ctl = itf_ctl;
-  p_video->itf_in  = itf_in;
-  p_video->itf_out = itf_out;
-  p_video->ctl     = ctl;
-  p_video->stm_in  = stm_in;
-  p_video->stm_out = stm_out;
-
-  return drv_len;
+  self->end = cur;
+  return end - cur;
 }
 
 // Invoked when a control transfer occurred on an interface of this class
@@ -251,43 +473,37 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 // return false to stall control endpoint (e.g unsupported request)
 bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
 {
+  if (p_request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) {
+    return false;
+  }
+  unsigned itfnum = tu_u16_low(p_request->wIndex);
+  /* Identify which interface to use */
+  videod_interface_t *self = NULL;
+  for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) {
+    if (_videod_itf[i].vc->bInterfaceNumber == itfnum) {
+      self = &_videod_itf[i];
+      break;
+    }
+  }
+  if (!self) return false;
+
   /* Standard request */
   if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) {
-    tusb_desc_interface_t const *itf;
-    unsigned itf;
+    if (stage != CONTROL_STAGE_SETUP) return true;
     switch (p_request->bRequest) {
     case TUSB_REQ_GET_INTERFACE:
-      itf = tu_u16_low(p_request->wIndex);
-      return audiod_get_interface(rhport, p_request);
+      return videod_get_itf(rhport, self, request);
     case TUSB_REQ_SET_INTERFACE:
-      itf = videod_find_interface_desc(void const *beg, void const *end, unsigned itfnum)
-      itf = tu_u16_low(p_request->wIndex);
-      
-      return audiod_set_interface(rhport, p_request);
-      /* Unknown/Unsupported request */
-    default: TU_BREAKPOINT(); return false;
+      return videod_set_itf(rhport, self, request);
+    default: /* Unknown/Unsupported request */
+      TU_BREAKPOINT();
+      return false;
     }
   }
 
-  uint8_t itf = 0;
-  videod_interface_t* p_video = _videod_itf;
+  unsigned cs  = TU_U16_HIGH(request->wValue);
+  unsigned uid = TU_U16_HIGH(request->wIndex);
 
-  // Identify which interface to use
-  for ( ; ; itf++, p_video++) {
-    if (itf >= TU_ARRAY_SIZE(_videod_itf)) return false;
-    if ( p_video->itf_num == request->wIndex ) break;
-  }
-
-  if (stage == CONTROL_STAGE_SETUP) {
-    TU_VERIFY((TUSB_DIR_IN_MASK & request->bmRequestType) ==
-	      (TUSB_DIR_IN_MASK & request->bRequest));
-  }
-
-
-  unsigned cs = TU_U16_HIGH(request->wValue);
-
-
-  unsigned req = request->bRequest;
   switch (request->bRequest) {
   case VIDEO_REQUEST_GET_INFO:
     TU_VERIFY(1 == request->wLength);
@@ -295,16 +511,16 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
     break;
   case VIDEO_REQUEST_SET_CUR:
     if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Set Current Setting Attribute\r\n");
-        tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t));
+      TU_LOG2("  Set Current Setting Attribute\r\n");
+      tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t));
     } else if ( stage == CONTROL_STAGE_ACK) {
       if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding);
     }
     break;
   case VIDEO_REQUEST_GET_CUR:
     if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Set Current Setting Attribute\r\n");
-        tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t));
+      TU_LOG2("  Set Current Setting Attribute\r\n");
+      tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t));
     } else if ( stage == CONTROL_STAGE_ACK) {
       if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding);
     }
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index b077a9a76..e0ff21694 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -28,12 +28,21 @@
 #ifndef TUSB_VIDEO_DEVICE_H_
 #define TUSB_VIDEO_DEVICE_H_
 
-#include "video_device.h"
-
 #ifdef __cplusplus
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Application Callback API (weak is optional)
+//--------------------------------------------------------------------+
+
+// Invoked when GET_INFO request received
+TU_ATTR_WEAK bool tud_video_get_info_cb(uint8_t rhport, tusb_control_request_t const *request, uint8_t const *itf_desc);
+// Invoked when GET_INFO request received
+TU_ATTR_WEAK bool tud_video_set_cur_cb(uint8_t rhport, tusb_control_request_t const *request);
+// Invoked when GET_CUR request received
+TU_ATTR_WEAK bool tud_video_get_info_cb(uint8_t rhport, tusb_control_request_t const *request);
+
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+

From 033d6b28fff1644411ef430a968ca7f0d9aa3b05 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 25 Jul 2021 14:01:35 +0900
Subject: [PATCH 0508/2085] moved ISO attributes from audio to common

---
 examples/rules.mk              |   1 +
 src/class/audio/audio.h        |  12 -
 src/class/video/video.h        |  85 ++++-
 src/class/video/video_device.c | 646 +++++++++++++++++++++++----------
 src/class/video/video_device.h |   7 +-
 src/common/tusb_types.h        |  12 +
 6 files changed, 541 insertions(+), 222 deletions(-)

diff --git a/examples/rules.mk b/examples/rules.mk
index 861973284..6f2d5a0ee 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -35,6 +35,7 @@ SRC_C += \
 	src/class/msc/msc_device.c \
 	src/class/net/net_device.c \
 	src/class/usbtmc/usbtmc_device.c \
+	src/class/video/video_device.c \
 	src/class/vendor/vendor_device.c
 
 # TinyUSB stack include
diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h
index f99061eae..6f9c1a6b5 100644
--- a/src/class/audio/audio.h
+++ b/src/class/audio/audio.h
@@ -494,18 +494,6 @@ typedef enum
 
 /// All remaining definitions are taken from the descriptor descriptions in the UAC2 main specification
 
-/// Isochronous End Point Attributes
-typedef enum
-{
-  TUSB_ISO_EP_ATT_NO_SYNC         = 0x00,
-  TUSB_ISO_EP_ATT_ASYNCHRONOUS    = 0x04,
-  TUSB_ISO_EP_ATT_ADAPTIVE        = 0x08,
-  TUSB_ISO_EP_ATT_SYNCHRONOUS     = 0x0C,
-  TUSB_ISO_EP_ATT_DATA            = 0x00, ///< Data End Point
-  TUSB_ISO_EP_ATT_EXPLICIT_FB     = 0x10, ///< Feedback End Point
-  TUSB_ISO_EP_ATT_IMPLICIT_FB     = 0x20, ///< Data endpoint that also serves as an implicit feedback
-} tusb_iso_ep_attribute_t;
-
 /// Audio Class-Control Values UAC2
 typedef enum
 {
diff --git a/src/class/video/video.h b/src/class/video/video.h
index f994c7fed..081860c83 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -29,6 +29,20 @@
 
 #include "common/tusb_common.h"
 
+/* 4.2.1.2 */
+typedef enum {
+  VIDEO_NO_ERROR = 0, /* The request succeeded. */
+  VIDEO_NOT_READY,
+  VIDEO_WRONG_STATE,
+  VIDEO_POWER,
+  VIDEO_OUT_OF_RANGE,
+  VIDEO_INVALID_UNIT,
+  VIDEO_INVALID_CONTROL,
+  VIDEO_INVALID_REQUEST,
+  VIDEO_INVALID_VALUE_WITHIN_RANGE,
+  VIDEO_UNKNOWN = 0xFF,
+} video_error_code_t;
+
 /* A.2 */
 typedef enum {
   VIDEO_SUBCLASS_UNDEFINED = 0x00,
@@ -103,14 +117,29 @@ typedef enum
   VIDEO_REQUEST_GET_DEF_ALL = 0x97
 } video_control_request_t;
 
-/* A.9 */
+/* A.9.1 */
 typedef enum
 {
-  VIDEO_CTL_SEL_UNDEF = 0x00,
-  VIDEO_CTL_SEL_VIDEO_POWER_MODE_CONTROL,
-  VIDEO_CTL_SEL_REQUEST_ERROR_CODE_CONTROL,
+  VIDEO_VC_CTL_UNDEF = 0x00,
+  VIDEO_VC_CTL_VIDEO_POWER_MODE,
+  VIDEO_VC_CTL_REQUEST_ERROR_CODE,
 } video_interface_control_selector_t;
 
+/* A.9.8 */
+typedef enum
+{
+  VIDEO_VS_CTL_UNDEF = 0x00,
+  VIDEO_VS_CTL_PROBE,
+  VIDEO_VS_CTL_COMMIT,
+  VIDEO_VS_CTL_STILL_PROBE,
+  VIDEO_VS_CTL_STILL_COMMIT,
+  VIDEO_VS_CTL_STILL_IMAGE_TRIGGER,
+  VIDEO_VS_CTL_STREAM_ERROR_CODE,
+  VIDEO_VS_CTL_GENERATE_KEY_FRAME,
+  VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT,
+  VIDEO_VS_CTL_SYNCH_DELAY_CONTROL,
+} video_interface_streaming_selector_t;
+
 /* B. Terminal Types */
 typedef enum
 {
@@ -193,8 +222,37 @@ typedef struct TU_ATTR_PACKED {
       uint8_t  bControlSize;
       uint8_t  bmaControls[];
     } output;
+  };
 } tusb_desc_cs_video_stm_itf_hdr_t;
 
+//--------------------------------------------------------------------+
+// Requests
+//--------------------------------------------------------------------+
+typedef struct TU_ATTR_PACKED {
+  uint16_t bmHint;
+  uint8_t  bFormatIndex;
+  uint8_t  bFrameIndex;
+  uint32_t dwFrameInterval;
+  uint16_t wKeyFrameRate;
+  uint16_t wPFrameRate;
+  uint16_t wCompQuality;
+  uint16_t wCompWindowSize;
+  uint16_t wDelay;
+  uint32_t dwMaxVideoFrameSize;
+  uint32_t dwMaxPayloadTransferSize;
+  uint32_t dwClockFrequency;
+  uint8_t  bmFramingInfo;
+  uint8_t  bPreferedVersion;
+  uint8_t  bMinVersion;
+  uint8_t  bMaxVersion;
+  uint8_t  bUsage;
+  uint8_t  bBitDepthLum;
+  uint8_t  bmSettings;
+  uint8_t  bMaxNumberOfRefFramesPlus1;
+  uint16_t bmRateControlModes;
+  uint64_t bmLayoutPerStream;
+} video_probe_and_commit_t;
+
 #define TUD_VIDEO_DESC_IAD_LEN                    8
 #define TUD_VIDEO_DESC_STD_VC_LEN                 9
 #define TUD_VIDEO_DESC_CS_VC_LEN                  12
@@ -225,18 +283,18 @@ typedef struct TU_ATTR_PACKED {
 /* 3.7.2 */
 #define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, _coll, ...)	\
   TUD_VIDEO_DESC_CS_VC_LEN + _coll, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \
-  U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE(_totallen + TUD_VIDEO_DESC_CS_AC_LEN), \
+  U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE(_totallen + TUD_VIDEO_DESC_CS_VC_LEN), \
   U32_TO_U8S_LE(_clkfreq), _coll, __VA_ARGS__
 
 /* 3.7.2.1 */
 #define TUD_VIDEO_DESC_INPUT_TERM(_tid, _tt, _at, _stridx) \
   TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL, \
-    _tid, U16_TO_U8S_LE(_tt), _at, _ti
+    _tid, U16_TO_U8S_LE(_tt), _at, _stridx
 
 /* 3.7.2.2 */
 #define TUD_VIDEO_DESC_OUTPUT_TERM(_tid, _tt, _at, _srcid, _stridx) \
   TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, \
-    _tid, U16_TO_U8S_LE(_tt), _at, _ti
+    _tid, U16_TO_U8S_LE(_tt), _at, _stridx
 
 /* 3.9.1 */
 #define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx)   \
@@ -258,14 +316,15 @@ typedef struct TU_ATTR_PACKED {
   _epn, _inf, _termlnk,  _trgusg, _ctlsz, __VA_ARGS__
 
 /* Uncompressed 3.1.1 */
+#define TUD_VIDEO_GUID(_g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15) _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15
 #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfrmdesc, \
-  _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15, \
-  _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \
+  _guid, _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \
   TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, \
-  _fmtidx, _numfrmdesc,\
-  _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15,\
+  _fmtidx, _numfrmdesc, TUD_VIDEO_GUID(_guid), \
   _bitsperpix, _frmidx, _asrx,  _asry, _interlace, _cp
 
+//  _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15,
+
 /* Uncompressed 3.1.2 Table 3-3 */
 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \
   TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \
@@ -281,12 +340,12 @@ typedef struct TU_ATTR_PACKED {
   U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), _numfrminterval, __VA_ARGS__
 
 /* 3.10.1.1 */
-#define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval)
+#define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) \
   7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\
   U16_TO_U8S_LE(_epsize), _ep_interval
 
 /* 3.10.1.2 */
-#define TUD_VIDEO_DESC_EP_BULK(_ep, _epsize, _ep_interval)
+#define TUD_VIDEO_DESC_EP_BULK(_ep, _epsize, _ep_interval) \
   7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), _ep_interval
 
 #endif
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 637e7a127..ed703d79a 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -53,33 +53,32 @@ typedef struct {
   tusb_desc_cs_video_stm_itf_hdr_t stm;
 } tusb_desc_vs_itf_t;
 
+typedef union {
+  tusb_desc_cs_video_ctl_itf_hdr_t ctl;
+  tusb_desc_cs_video_stm_itf_hdr_t stm;
+} tusb_desc_video_itf_hdr_t;
+
 typedef struct TU_ATTR_PACKED {
   uint8_t bLength;
   uint8_t bDescriptorType;
   uint8_t bDescriptorSubtype;
-  union {
-    uint8_t bId;
-    uint8_t bTerminalId;
-    uint8_t bUnitId;
-  };
+  uint8_t bEntityId;
 } tusb_desc_cs_video_entity_itf_t;
 
 typedef struct
 {
-  void const *beg;
-  void const *end;
-  tusb_desc_vc_itf_t const *vc;    /* current video control interface */
-  tusb_desc_vs_itf_t const *vs[2]; /* current video streaming interfaces */
-  uint8_t ep_notif; /* notification */
-  uint8_t ep_in;    /* video IN */
-  uint8_t ep_sti;   /* still image IN */
-  uint8_t ep_out;   /* video OUT */
+  void const *beg;  /* The head of the first video control interface descriptor */
+  uint16_t    len;  /* Byte length of the descriptors */
+  uint16_t    ofs[3];  /* offsets for video control/streaming interface. 0:control 1:streaming 2:streaming */
+  uint8_t power_mode;
+  uint8_t error_code;
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
 
   // Endpoint Transfer buffer
-  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
-  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE];
+  //  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
+  //  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE];
+  uint8_t ctl_buf;
 
 } videod_interface_t;
 
@@ -90,6 +89,26 @@ typedef struct
 //--------------------------------------------------------------------+
 CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
 
+static uint8_t const _cap_get     = 0x1u; /* support for GET */
+static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
+
+static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self)
+{
+  return (tusb_desc_vc_itf_t const *)(self->beg + self->ofs[0]);
+}
+
+static uint16_t* _get_desc_ofs(videod_interface_t *self, unsigned itfnum)
+{
+  void const *beg = self->beg;
+  uint16_t   *ofs = self->ofs;
+  for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(self->ofs[0]); ++i) {
+    if (!ofs[i]) continue;
+    tusb_desc_interface_t const* itf = (tusb_desc_interface_t const*)(beg + ofs[i]);
+    if (itfnum == itf->bInterfaceNumber) return &ofs[i];
+  }
+  return NULL;
+}
+
 /** Find the first descriptor with the specified descriptor type.
  *
  * @param[in] beg     The head of descriptor byte array.
@@ -98,13 +117,31 @@ CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* videod_find_desc(void const *beg, void const *end, uint8_t target)
+static void const* _find_desc(void const *beg, void const *end, uint8_t target)
 {
-  for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) {
-    if (target != tu_desc_type(cur))
-      return (uint8_t const*)cur;
+  void const *cur = beg;
+  while ((cur < end) && (target != tu_desc_type(cur))) {
+    cur = tu_desc_next(cur);
   }
-  return end;
+  return cur;
+}
+
+/** Return the next interface descriptor except alternate ones.
+ *
+ * @param[in] beg     The head of descriptor byte array.
+ * @param[in] end     The tail of descriptor byte array.
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* _next_desc_itf(void const *beg, void const *end)
+{
+  void const *cur = beg;
+  unsigned itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber;
+  while ((cur < end) &&
+	 (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) {
+    cur = _find_desc(tu_desc_next(cur), end, TUSB_DESC_INTERFACE);
+  }
+  return cur;
 }
 
 /** Find the first interface descriptor with the specified interface number and alternate setting number.
@@ -116,11 +153,11 @@ static void const* videod_find_desc(void const *beg, void const *end, uint8_t ta
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* videod_find_desc_itf(void const *beg, void const *end, unsigned itfnum, unsigned altnum)
+static void const* _find_desc_itf(void const *beg, void const *end, unsigned itfnum, unsigned altnum)
 {
-  for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_INTERFACE)) {
+  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_INTERFACE)) {
     tusb_desc_interface_t const *itf = (tusb_desc_interface_t const *)cur;
-    if (itf->bInterfaceNumber == itfnum && itf->bAlternateSettings == altnum) {
+    if (itf->bInterfaceNumber == itfnum && itf->bAlternateSetting == altnum) {
       return itf;
     }
     cur = tu_desc_next(cur);
@@ -128,21 +165,22 @@ static void const* videod_find_desc_itf(void const *beg, void const *end, unsign
   return end;
 }
 
-/** Find the first input or output terminal descriptor with the specified terminal id.
+/** Find the first entity descriptor with the specified entity ID in the video control interface descriptor.
  *
- * @param[in] beg     The head of descriptor byte array.
- * @param[in] end     The tail of descriptor byte array.
- * @param[in] termid  The target terminal id.
+ * @param[in] vc        The video control interface descriptor.
+ * @param[in] entityid  The target entity id.
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* videod_find_desc_term(void const *beg, void const *end, unsigned termid)
+static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, unsigned entityid)
 {
-  for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
+  void const *beg = (void const*)vc;
+  void const *end = beg + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength;
+  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
     tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
     if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL  == itf->bDescriptorSubtype ||
          VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL == itf->bDescriptorSubtype) &&
-        itf->bTerminalId == termid) {
+        itf->bEntityId == entityid) {
       return itf;
     }
     cur = tu_desc_next(cur);
@@ -150,47 +188,72 @@ static void const* videod_find_desc_term(void const *beg, void const *end, unsig
   return end;
 }
 
-/** Find the first selector/processing/extension/encoding unit descriptor with the specified unit id.
- *
- * @param[in] beg     The head of descriptor byte array.
- * @param[in] end     The tail of descriptor byte array.
- * @param[in] unitid  The target unit id.
- *
- * @return The pointer for interface descriptor.
- * @retval end   did not found interface descriptor */
-static void const* videod_find_desc_unit(void const *beg, void const *end, unsigned unitid)
+static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
 {
-  for (void const *cur = beg; cur < end; cur = videod_find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
-    tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
-    if (VIDEO_CS_VC_INTERFACE_SELECTOR_UNIT <= itf->bDescriptorSubtype &&
-        itf->bDescriptorSubtype <= VIDEO_CS_VC_INTERFACE_ENCODING_UNIT &&
-        itf->bUnitId == unitid) {
-      return itf;
-    }
-    cur = tu_desc_next(cur);
+  tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
+  /* The next descriptor after the class-specific VC interface header descriptor. */
+  void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength;
+  /* The end of the video control interface descriptor. */
+  void const *end = cur + vc->ctl.wTotalLength;
+  if (vc->std.bNumEndpoints) {
+    /* Find the notification endpoint descriptor. */
+    cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
+    TU_ASSERT(cur < end);
+    tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur;
+    usbd_edpt_close(rhport, notif->bEndpointAddress);
   }
-  return end;
+  self->ofs[0] = 0;
+  return true;
+}
+
+static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum)
+{
+  void const *beg = self->beg;
+  void const *end = beg + self->len;
+  /* The first descriptor is a video control interface descriptor. */
+  unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber;
+  void const *cur = _find_desc_itf(beg, end, itfnum, altnum);
+  TU_VERIFY(cur < end);
+
+  tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
+  /* Support for up to 2 streaming interfaces only. */
+  TU_ASSERT(vc->ctl.bInCollection < 3);
+
+  /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
+  cur += vc->std.bLength + vc->ctl.bLength;
+  /* Update to point the end of the video control interface descriptor. */
+  end  = cur + vc->ctl.wTotalLength;
+  /* Open the notification endpoint if it exist. */
+  if (vc->std.bNumEndpoints) {
+    /* Support for 1 endpoint only. */
+    TU_VERIFY(1 == vc->std.bNumEndpoints);
+    /* Find the notification endpoint descriptor. */
+    cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
+    TU_VERIFY(cur < end);
+    tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur;
+    /* Open the notification endpoint */
+    TU_ASSERT(usbd_edpt_open(rhport, notif));
+  }
+  self->ofs[0] = (void const*)vc - beg;
+  return true;
 }
 
 /** Set the specified alternate setting to own video control interface.
  *
  * @param[in,out] self     The context.
- * @param[in]     altnum   The target alternate setting number.
- *
- * @return The next descriptor after the video control interface descriptor.
- * @retval NULL   did not found interface descriptor or alternate setting */
-static void const* videod_set_vc_itf(videod_interface_t *self, unsigned altnum)
+ * @param[in]     altnum   The target alternate setting number. */
+static bool _set_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum)
 {
   void const *beg = self->beg;
-  void const *end = self->end;
+  void const *end = beg + self->len;
   /* The head descriptor is a video control interface descriptor. */
   unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber;
-  void const *cur = videod_find_desc_itf(beg, end, itfnum, altnum);
-  TU_VERIFY(cur < end, NULL);
+  void const *cur = _find_desc_itf(beg, end, itfnum, altnum);
+  TU_VERIFY(cur < end);
 
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
   /* Support for up to 2 streaming interfaces only. */
-  TU_VERIFY(vc->ctl.bInCollection < 3, NULL);
+  TU_VERIFY(vc->ctl.bInCollection < 3);
 
   /* Close the previous notification endpoint if it is opened */
   if (self->ep_notif) {
@@ -204,42 +267,104 @@ static void const* videod_set_vc_itf(videod_interface_t *self, unsigned altnum)
   /* Open the notification endpoint if it exist. */
   if (vc->std.bNumEndpoints) {
     /* Support for 1 endpoint only. */
-    TU_VERIFY(1 == vc->std.bNumEndpoints, NULL);
+    TU_VERIFY(1 == vc->std.bNumEndpoints);
     /* Find the notification endpoint descriptor. */
-    cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT);
-    TU_VERIFY(cur < end, NULL);
+    cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
+    TU_VERIFY(cur < end);
     tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur;
     /* Open the notification endpoint */
-    TU_ASSERT(usbd_edpt_open(rhport, notif), NULL);
+    TU_ASSERT(usbd_edpt_open(rhport, notif));
     self->ep_notif = notif->bEndpointAddress;
   }
-  self->vc = vc;
-  return end;
+  self->ofs[0] = (void const*)vc - beg;
+  return true;
+}
+
+/** Set the specified alternate setting to own video control interface.
+ *
+ * @param[in,out] self     The context.
+ * @param[in]     itfnum   The target interface number. */
+static bool _close_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum)
+{
+  uint16_t *ofs = _get_desc_ofs(self, itfnum);
+  if (!ofs) return true;
+  tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)(self->beg + *ofs);
+  /* The next of the video streaming interface header descriptor. */
+  void const *cur = (void const*)vs + vs->std.bLength + vs->stm.bLength;
+  /* The end of the video streaming interface descriptor. */
+  void const *end = cur + vs->stm.wTotalLength;
+  if (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) {
+    cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
+    TU_ASSERT(cur < end);
+    tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
+    usbd_edpt_close(rhport, ep->bEndpointAddress);
+    cur += tu_desc_len(cur);
+  }
+  *ofs = 0;
+  return true;
 }
 
 /** Set the specified alternate setting to own video control interface.
  *
  * @param[in,out] self     The context.
  * @param[in]     itfnum   The target interface number.
- * @param[in]     altnum   The target alternate setting number.
+ * @param[in]     altnum   The target alternate setting number. */
+static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum, unsigned altnum)
+{
+  uint16_t   *ofs = NULL;
+  for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(self->ofs[0]); ++i) {
+    if (!self->ofs[i]) {
+      ofs = &self->ofs[i];
+      break;
+    }
+  }
+  if (!ofs) return false;
+
+  tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
+  void const *end = self->beg + self->len;
+  /* Set the end of the video control interface descriptor. */
+  void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength;
+
+  cur = _find_desc_itf(cur, end, itfnum, altnum);
+  TU_VERIFY(cur < end);
+  tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur;
+  /* Support for up to 2 endpoint only. */
+  TU_ASSERT(vs->std.bNumEndpoints < 3);
+  /* Advance to the next descriptor after the class-specific VS interface header descriptor. */
+  cur += vs->std.bLength + vs->stm.bLength;
+  /* Update to point the end of the video control interface descriptor. */
+  end  = cur + vs->stm.wTotalLength;
+  for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) {
+    cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
+    TU_VERIFY(cur < end);
+    tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
+    TU_ASSERT(usbd_edpt_open(rhport, ep));
+    cur += tu_desc_len(cur);
+  }
+  *ofs = (void const*)vs - self->beg;
+  return true;
+}
+
+/** Set the specified alternate setting to own video control interface.
  *
- * @return The next descriptor after the video control interface descriptor.
- * @retval NULL   did not found interface descriptor or alternate setting */
-static void const* videod_set_vs_itf(videod_interface_t *self, unsigned itfnum, unsigned altnum)
+ * @param[in,out] self     The context.
+ * @param[in]     itfnum   The target interface number.
+ * @param[in]     altnum   The target alternate setting number. */
+static bool _set_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum, unsigned altnum)
 {
   unsigned i;
-  tusb_desc_vc_itf_t const *vc = self->vc;
-  void const *end = self->end;
+  tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
+  void const *end = self->beg + self->len;
   /* Set the end of the video control interface descriptor. */
   void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength;
 
   /* Check itfnum is valid */
-  unsigned bInCollection = self->vc->ctl.bInCollection;
+  unsigned bInCollection = vc->ctl.bInCollection;
   for (i = 0; (i < bInCollection) && (vc->ctl.baInterfaceNr[i] != itfnum); ++i) ;
-  TU_VERIFY(i < bInCollection, NULL);
-  
-  cur = videod_find_desc_itf(cur, end, itfnum, altnum);
-  TU_VERIFY(cur < end, NULL);
+  TU_VERIFY(i < bInCollection);
+
+  cur = _find_desc_itf(cur, end, itfnum, altnum);
+  TU_VERIFY(cur < end);
   tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur;
   /* Advance to the next descriptor after the class-specific VS interface header descriptor. */
   cur += vs->std.bLength + vs->stm.bLength;
@@ -247,10 +372,10 @@ static void const* videod_set_vs_itf(videod_interface_t *self, unsigned itfnum,
   end  = cur + vs->stm.wTotalLength;
 
   switch (vs->stm.bDescriptorSubType) {
-  default: return end;
+  default: return false;
   case VIDEO_CS_VS_INTERFACE_INPUT_HEADER:
     /* Support for up to 2 endpoint only. */
-    TU_VERIFY(vc->std.bNumEndpoints < 3, NULL);
+    TU_VERIFY(vc->std.bNumEndpoints < 3);
     if (self->ep_sti) {
       usbd_edpt_close(rhport, self->ep_sti);
       self->ep_sti = 0;
@@ -260,18 +385,18 @@ static void const* videod_set_vs_itf(videod_interface_t *self, unsigned itfnum,
       self->ep_in  = 0;
     }
     if (i = 0; i < vs->std.bNumEndpoints; ++i) {
-      cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT);
-      TU_VERIFY(cur < end, NULL);
+      cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
+      TU_VERIFY(cur < end);
       tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
       if (vs->stm.bEndpointAddress == ep->bEndpointAddress) {
         /* video input endpoint */
-        TU_ASSERT(!self->ep_in, NULL);
-        TU_ASSERT(usbd_edpt_open(rhport, ep), NULL);
+        TU_ASSERT(!self->ep_in);
+        TU_ASSERT(usbd_edpt_open(rhport, ep));
         self->ep_in  = ep->bEndpointAddress;
       } else {
         /* still image input endpoint */
-        TU_ASSERT(!self->ep_sti, NULL);
-        TU_ASSERT(usbd_edpt_open(rhport, ep), NULL);
+        TU_ASSERT(!self->ep_sti);
+        TU_ASSERT(usbd_edpt_open(rhport, ep));
         self->ep_sti = ep->bEndpointAddress;
       }
       cur += tu_desc_len(cur);
@@ -279,78 +404,245 @@ static void const* videod_set_vs_itf(videod_interface_t *self, unsigned itfnum,
     break;
   case VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER:
     /* Support for up to 1 endpoint only. */
-    TU_VERIFY(vc->std.bNumEndpoints < 2, NULL);
+    TU_VERIFY(vc->std.bNumEndpoints < 2);
     if (self->ep_out) {
       usbd_edpt_close(rhport, self->ep_out);
       self->ep_out = 0;
     }
     if (vs->std.bNumEndpoints) {
-      cur = videod_find_desc(cur, end, TUSB_DESC_ENDPOINT);
-      TU_VERIFY(cur < end, NULL);
+      cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
+      TU_VERIFY(cur < end);
       tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
       if (vs->stm.bEndpointAddress == ep->bEndpointAddress) {
         /* video output endpoint */
-        TU_ASSERT(usbd_edpt_open(rhport, ep), NULL);
+        TU_ASSERT(usbd_edpt_open(rhport, ep));
         self->ep_out = ep->bEndpointAddress;
       }
     }
     break;
   }
-  for (i = 0; i < sizeof(self->vs)/sizeof(self->vs[0]); ++i) {
-    if (!self->vs[i] || self->vs[i].stm.bInterfaceNumber == vs->stm.bInterfaceNumber) {
-      self->vs[i] = vs;
-      return end;
+  for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(ofs[0]); ++i) {
+    if (!self->ofs[i]) {
+      return true;
     }
+    tusb_desc_interface_t const* itf = (tusb_desc_interface_t const*)(beg + ofs[i]);
+    if (itfnum == itf->bInterfaceNumber) return itf;
   }
   return NULL;
-}
-
-static bool videod_get_itf(uint8_t rhport, videod_interface_t *self, tusb_control_request_t const * request)
-{
-  unsigned altnum = tu_u16_low(p_request->wValue);
-  unsigned itfnum = tu_u16_low(p_request->wLength);
-
-  tusb_desc_vc_itf_t const *vc = self->vc;
-  if (vc->std.bInterfaceNumber == itfnum) {
-    tud_control_xfer(rhport, request, &vc->std.bAlternateSettings, sizeof(vc->std.bAlternateSettings));
-    return true;
-  }
-  for (unsigned i = 0; i < vc->ctl.bInCollection; ++i) {
-    tusb_desc_vs_itf_t const *vs = self->vs[i];
-    if (!vs || vs->std.bInterfaceNumber == itfnum) {
-      continue;
+  for (i = 0; i < sizeof(self->vs)/sizeof(self->vs[0]); ++i) {
+    if (!self->vs[i] || self->vs[i].stm.bInterfaceNumber == vs->stm.bInterfaceNumber) {
+      self->ofs[i] = (void const*)vs - self->beg;
+      return true;
     }
-    tud_control_xfer(rhport, request, &vs->std.bAlternateSettings, sizeof(vs->std.bAlternateSettings));
-    return true;
   }
   return false;
 }
 
-static bool videod_set_itf(uint8_t rhport, videod_interface_t *self, tusb_control_request_t const * request)
+static int handle_video_ctl_std_req_get_itf(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
-  (void)rhport;
-  unsigned altnum = tu_u16_low(p_request->wValue);
-  unsigned itfnum = tu_u16_low(p_request->wLength);
-
-  tusb_desc_vc_itf_t const *vc = self->vc;
-  if (vc->std.bInterfaceNumber == itfnum) {
-    if (videod_set_vc_itf(self, altnum))
-      return true;
-    return false;
-  }
-  for (unsigned i = 0; i < vc->ctl.bInCollection; ++i) {
-    tusb_desc_vs_itf_t const *vs = self->vs[i];
-    if (!vs || vs->std.bInterfaceNumber == itfnum) {
-      continue;
-    }
-    if (videod_set_vs_itf(self, itfnum, altnum))
-      return true;
-    return false;
-  }
-  return false;
+  if (stage != CONTROL_STAGE_SETUP)
+    return VIDEO_NO_ERROR;
+  videod_interface_t *self = &_videod_itf[itf];
+  TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+  tusb_desc_interface_t const *p = _get_desc_cur_itf(self, itfnum);
+  if (!p) return VIDEO_UNKNOWN;
+  if (tud_control_xfer(rhport, request, &p->bAlternateSettings, sizeof(p->bAlternateSettings)))
+    return VIDEO_NO_ERROR;
+  return VIDEO_UNKNOWN;
 }
 
-static void _prep_out_transaction (cdcd_interface_t* p_cdc)
+/** Handle a standard request to the video control interface. */
+static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+{
+  switch (p_request->bRequest) {
+  case TUSB_REQ_GET_INTERFACE:
+    handle_video_ctl_std_req_get_itf(rhport, stage, request, itf);
+  case TUSB_REQ_SET_INTERFACE:
+    if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+    if (_set_vc_itf(rhport, &_videod_itf[itf], request->wValue))
+      return VIDEO_NO_ERROR;
+    return VIDEO_UNKNOWN;
+  default: /* Unknown/Unsupported request */
+    TU_BREAKPOINT();
+    return VIDEO_INVALID_REQUEST;
+  }
+}
+
+static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+{
+  videod_interface_t *self = &_videod_itf[i];
+  /* 4.2.1 Interface Control Request */
+  switch (TU_U16_HIGH(request->wValue)) {
+  case VIDEO_VC_CTL_VIDEO_POWER_MODE:
+    switch (p_request->bRequest) {
+    case VIDEO_REQUEST_SET_CUR:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Set Power Mode\r\n");
+        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+        if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
+          return VIDEO_UNKNOWN;
+      } else if (stage == CONTROL_STAGE_ACK) {
+        if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, &self->power_mode);
+      }
+      return VIDEO_NO_ERROR;
+    case VIDEO_REQUEST_GET_CUR:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Get Power Mode\r\n");
+        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+        if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
+          return VIDEO_UNKNOWN;
+      }
+      return VIDEO_NO_ERROR;
+    case VIDEO_REQUEST_GET_INFO:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Get Info Power Mode\r\n");
+        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+        if (!tud_control_xfer(rhport, request, &_cap_get_set, sizeof(_cap_get_set)))
+          return VIDEO_UNKNOWN;
+      }
+      return VIDEO_NO_ERROR;
+    default: break;
+    }
+    break;
+  case VIDEO_VC_CTL_REQUEST_ERROR_CODE:
+    switch (p_request->bRequest) {
+    case VIDEO_REQUEST_GET_CUR:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Get Error Code\r\n");
+        if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(self->error_code)))
+          return VIDEO_UNKNOWN;
+      }
+      return VIDEO_NO_ERROR;
+    case VIDEO_REQUEST_GET_INFO:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Get Info Error Code\r\n");
+        if (tud_control_xfer(rhport, request, &_cap_get, sizeof(_cap_get)))
+          return VIDEO_UNKNOWN;
+      }
+      return VIDEO_NO_ERROR;
+    default: break;
+    }
+    break;
+  default: break;
+  }
+  /* Unknown/Unsupported request */
+  TU_BREAKPOINT();
+  return VIDEO_INVALID_REQUEST;
+}
+
+static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+{
+  switch (p_request->bmRequestType_bit.type) {
+  case TUSB_REQ_TYPE_STANDARD:
+    return handle_video_ctl_std_req(rhport, stage, request, itf);
+  case TUSB_REQ_TYPE_CLASS:
+    if (!TU_U16_HIGH(request->wIndex)) {
+      return handle_video_ctl_cs_req(rhport, stage, request, itf);
+    } else {
+      /* TODO: */
+      return VIDEO_INVALID_REQUEST;
+    }
+  default:
+    return VIDEO_INVALID_REQUEST;
+  }
+}
+
+static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+{
+  switch (p_request->bRequest) {
+  case TUSB_REQ_GET_INTERFACE:
+    handle_video_ctl_std_req_get_itf(rhport, stage, request, itf);
+  case TUSB_REQ_SET_INTERFACE:
+    videod_interface_t *self   = &_videod_itf[itf];
+    unsigned            itfnum = tu_u16_low(p_request->wIndex);
+    if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+    if (_set_vs_itf(rhport, self, itfnum, request->wValue))
+      return VIDEO_NO_ERROR;
+    return VIDEO_UNKNOWN;
+  default: /* Unknown/Unsupported request */
+    TU_BREAKPOINT();
+    return VIDEO_INVALID_REQUEST;
+  }
+}
+
+static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+{
+  videod_interface_t *self = &_videod_itf[i];
+  /* 4.2.1 Interface Control Request */
+  switch (TU_U16_HIGH(request->wValue)) {
+  case VIDEO_VS_CTL_PROBE:
+    switch (p_request->bRequest) {
+    case VIDEO_REQUEST_SET_CUR:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Set Power Mode\r\n");
+        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+        if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
+          return VIDEO_UNKNOWN;
+      } else if (stage == CONTROL_STAGE_ACK) {
+        if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, &self->power_mode);
+      }
+      return VIDEO_NO_ERROR;
+    case VIDEO_REQUEST_GET_CUR:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Get Power Mode\r\n");
+        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+        if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
+          return VIDEO_UNKNOWN;
+      }
+      return VIDEO_NO_ERROR;
+    case VIDEO_REQUEST_GET_INFO:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Get Info Power Mode\r\n");
+        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+        if (!tud_control_xfer(rhport, request, &_cap_get_set, sizeof(_cap_get_set)))
+          return VIDEO_UNKNOWN;
+      }
+      return VIDEO_NO_ERROR;
+    default: break;
+    }
+    break;
+  case VIDEO_VS_CTL_COMMIT:
+    switch (p_request->bRequest) {
+    case VIDEO_REQUEST_GET_CUR:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Get Error Code\r\n");
+        if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(self->error_code)))
+          return VIDEO_UNKNOWN;
+      }
+      return VIDEO_NO_ERROR;
+    case VIDEO_REQUEST_GET_INFO:
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_LOG2("  Get Info Error Code\r\n");
+        if (tud_control_xfer(rhport, request, &_cap_get, sizeof(_cap_get)))
+          return VIDEO_UNKNOWN;
+      }
+      return VIDEO_NO_ERROR;
+    default: break;
+    }
+    break;
+  default: break;
+  }
+  /* Unknown/Unsupported request */
+  TU_BREAKPOINT();
+  return VIDEO_INVALID_REQUEST;
+}
+
+static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+{
+  switch (p_request->bmRequestType_bit.type) {
+  case TUSB_REQ_TYPE_STANDARD:
+    return handle_video_stm_std_req(rhport, stage, request, itf);
+  case TUSB_REQ_TYPE_CLASS:
+    if (TU_U16_HIGH(request->wIndex))
+      return VIDEO_INVALID_REQUEST;
+    return handle_video_stm_cs_req(rhport, stage, request, itf);
+  default:
+    return VIDEO_INVALID_REQUEST;
+  }
+  return VIDEO_UNKNOWN;
+}
+
+static void _prep_out_transaction(cdcd_interface_t* p_cdc)
 {
   uint8_t const rhport = TUD_OPT_RHPORT;
   uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff);
@@ -440,31 +732,23 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 
   void const *end = (void const*)itf_desc + max_len;
   self->beg = itf_desc;
-  self->end = end;
+  self->len = max_len;
   /*------------- Video Control Interface -------------*/
-  void const* cur = videod_set_vc_itf(self, 0);
-  TU_VERIFY(cur, 0);
-  unsigned bInCollection = self->vc->ctl.bInCollection;
+  if (!_open_vc_itf(rhport, self, 0)) return 0;
+  tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
+  unsigned bInCollection       = vc->ctl.bInCollection;
+  /* Update end */
+  void const *cur = _next_desc_itf(itf_desc, end);
+  for (unsigned i = 0; i < bInCollection; ++i) {
+    cur = _next_desc_itf(cur, end);
+  }
+  self->len = (uintptr_t)cur - (uintptr_t)itf_desc;
   /*------------- Video Stream Interface -------------*/
   unsigned itfnum = 0;
   for (unsigned i = 0; i < bInCollection; ++i) {
     itfnum = vc->ctl.baInterfaceNr[i];
-    cur = videod_set_vs_itf(self, itfnum, 0);
-    TU_VERIFY(cur, 0);
+    if (!_open_vs_itf(rhport, self, itfnum, 0)) return 0;
   }
-
-  /* Skip alternate setting interfaces */
-  while (cur < end && TUSB_DESC_INTERFACE == tu_desc_type(cur)) {
-    tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)cur;
-    if (itfnum                              != vs->std.bInterfaceNumber ||
-        TUSB_DESC_CS_INTERFACE              != vs->stm.bDescriptorType  ||
-        (VIDEO_CS_VS_INTERFACE_INPUT_HEADER != vs->stm.bDescriptorSubType &&
-         VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER!= vs->stm.bDescriptorSubType)) {
-      break;
-    }
-    cur += itf->std.bLength + itf->stm.bLength + itf->stm.wTotalLength;
-  }
-  self->end = cur;
   return end - cur;
 }
 
@@ -473,61 +757,33 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 // return false to stall control endpoint (e.g unsupported request)
 bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
 {
+  int err;
   if (p_request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) {
     return false;
   }
   unsigned itfnum = tu_u16_low(p_request->wIndex);
   /* Identify which interface to use */
-  videod_interface_t *self = NULL;
-  for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) {
-    if (_videod_itf[i].vc->bInterfaceNumber == itfnum) {
-      self = &_videod_itf[i];
+  int itf;
+  tusb_desc_vc_itf_t const *vc = NULL;
+  for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
+    vc = _videod_itf[itf].vc;
+    if (!vc) continue;
+    unsigned beg_itfnum = vc->bInterfaceNumber;
+    unsigned end_itfnum = vc->ctl.bInCollection;
+    if (beg_itfnum <= itfnum && itfnum < end_itfnum)
       break;
-    }
   }
-  if (!self) return false;
+  if (itf == CFG_TUD_VIDEO) return false;
 
-  /* Standard request */
-  if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) {
-    if (stage != CONTROL_STAGE_SETUP) return true;
-    switch (p_request->bRequest) {
-    case TUSB_REQ_GET_INTERFACE:
-      return videod_get_itf(rhport, self, request);
-    case TUSB_REQ_SET_INTERFACE:
-      return videod_set_itf(rhport, self, request);
-    default: /* Unknown/Unsupported request */
-      TU_BREAKPOINT();
-      return false;
-    }
+  if (itfnum == vc->bInterfaceNumber) {
+    /* To video control interface */
+    err = handle_video_ctl_req(rhport, stage, request, itf);
+  } else {
+    /* To video streaming interface */
+    err = handle_video_stm_req(rhport, stage, request, itf);
   }
-
-  unsigned cs  = TU_U16_HIGH(request->wValue);
-  unsigned uid = TU_U16_HIGH(request->wIndex);
-
-  switch (request->bRequest) {
-  case VIDEO_REQUEST_GET_INFO:
-    TU_VERIFY(1 == request->wLength);
-    
-    break;
-  case VIDEO_REQUEST_SET_CUR:
-    if (stage == CONTROL_STAGE_SETUP) {
-      TU_LOG2("  Set Current Setting Attribute\r\n");
-      tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t));
-    } else if ( stage == CONTROL_STAGE_ACK) {
-      if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding);
-    }
-    break;
-  case VIDEO_REQUEST_GET_CUR:
-    if (stage == CONTROL_STAGE_SETUP) {
-      TU_LOG2("  Set Current Setting Attribute\r\n");
-      tud_control_xfer(rhport, request, &p_video->line_coding, sizeof(cdc_line_coding_t));
-    } else if ( stage == CONTROL_STAGE_ACK) {
-      if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_video->line_coding);
-    }
-    break;
-  default: return false; // stall unsupported request
-  }
-
+  _videod_itf[itf].error_code = (uint8_t)err;
+  if (err) return false;
   return true;
 }
 
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index e0ff21694..cd04b7391 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -28,8 +28,11 @@
 #ifndef TUSB_VIDEO_DEVICE_H_
 #define TUSB_VIDEO_DEVICE_H_
 
+#include "common/tusb_common.h"
+#include "video.h"
+
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 //--------------------------------------------------------------------+
@@ -41,7 +44,7 @@ TU_ATTR_WEAK bool tud_video_get_info_cb(uint8_t rhport, tusb_control_request_t c
 // Invoked when GET_INFO request received
 TU_ATTR_WEAK bool tud_video_set_cur_cb(uint8_t rhport, tusb_control_request_t const *request);
 // Invoked when GET_CUR request received
-TU_ATTR_WEAK bool tud_video_get_info_cb(uint8_t rhport, tusb_control_request_t const *request);
+TU_ATTR_WEAK bool tud_video_get_cur_cb(uint8_t rhport, tusb_control_request_t const *request);
 
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index f26983a74..897e89b39 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -69,6 +69,18 @@ typedef enum
   TUSB_DIR_IN_MASK = 0x80
 }tusb_dir_t;
 
+/// Isochronous End Point Attributes
+typedef enum
+{
+  TUSB_ISO_EP_ATT_NO_SYNC         = 0x00,
+  TUSB_ISO_EP_ATT_ASYNCHRONOUS    = 0x04,
+  TUSB_ISO_EP_ATT_ADAPTIVE        = 0x08,
+  TUSB_ISO_EP_ATT_SYNCHRONOUS     = 0x0C,
+  TUSB_ISO_EP_ATT_DATA            = 0x00, ///< Data End Point
+  TUSB_ISO_EP_ATT_EXPLICIT_FB     = 0x10, ///< Feedback End Point
+  TUSB_ISO_EP_ATT_IMPLICIT_FB     = 0x20, ///< Data endpoint that also serves as an implicit feedback
+}tusb_iso_ep_attribute_t;
+
 /// USB Descriptor Types
 typedef enum
 {

From 019c1ab09e98517ce5422e9a0e2995928feff027 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 31 Jul 2021 19:35:22 +0900
Subject: [PATCH 0509/2085] add tentative example

---
 examples/device/video_capture/Makefile        |  12 +
 examples/device/video_capture/src/main.c      | 123 +++++
 .../device/video_capture/src/tusb_config.h    | 106 +++++
 .../video_capture/src/usb_descriptors.c       | 172 +++++++
 .../video_capture/src/usb_descriptors.h       |  97 ++++
 src/class/video/video.h                       |  18 +-
 src/class/video/video_device.c                | 420 +++++-------------
 src/class/video/video_device.h                |   2 +
 8 files changed, 639 insertions(+), 311 deletions(-)
 create mode 100644 examples/device/video_capture/Makefile
 create mode 100644 examples/device/video_capture/src/main.c
 create mode 100644 examples/device/video_capture/src/tusb_config.h
 create mode 100644 examples/device/video_capture/src/usb_descriptors.c
 create mode 100644 examples/device/video_capture/src/usb_descriptors.h

diff --git a/examples/device/video_capture/Makefile b/examples/device/video_capture/Makefile
new file mode 100644
index 000000000..69b633fea
--- /dev/null
+++ b/examples/device/video_capture/Makefile
@@ -0,0 +1,12 @@
+include ../../../tools/top.mk
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../rules.mk
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
new file mode 100644
index 000000000..098cd2f8d
--- /dev/null
+++ b/examples/device/video_capture/src/main.c
@@ -0,0 +1,123 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+void led_blinking_task(void);
+void video_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+  tusb_init();
+
+  while (1)
+  {
+    tud_task(); // tinyusb device task
+    led_blinking_task();
+
+    video_task();
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+  (void) remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+
+//--------------------------------------------------------------------+
+// USB Video
+//--------------------------------------------------------------------+
+void video_task(void)
+{
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
new file mode 100644
index 000000000..ae2387357
--- /dev/null
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -0,0 +1,106 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_DEVICE_RHPORT_NUM
+  #define BOARD_DEVICE_RHPORT_NUM     0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+#ifndef BOARD_DEVICE_RHPORT_SPEED
+  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
+    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
+  #else
+    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
+  #endif
+#endif
+
+// Device mode with rhport and speed defined by board.mk
+#if   BOARD_DEVICE_RHPORT_NUM == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#elif BOARD_DEVICE_RHPORT_NUM == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#else
+  #error "Incorrect RHPort configuration"
+#endif
+
+// This example doesn't use an RTOS
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS               OPT_OS_NONE
+#endif
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC              0
+#define CFG_TUD_MSC              0
+#define CFG_TUD_HID              0
+#define CFG_TUD_MIDI             0
+#define CFG_TUD_AUDIO            0
+#define CFG_TUD_VIDEO            1
+#define CFG_TUD_VENDOR           0
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
new file mode 100644
index 000000000..df8c41721
--- /dev/null
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -0,0 +1,172 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]  VIDEO | AUDIO | MIDI | HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+    _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VIDEO, 5) | _PID_MAP(VENDOR, 6) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = 0x0200,
+
+    // Use Interface Association Descriptor (IAD) for CDC
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = 0xCafe,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+  return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
+  #define EPNUM_VIDEO_IN    0x83
+
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_CXD56
+  // SAMG doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_VIDEO_IN    0x81
+
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  #define EPNUM_VIDEO_IN    0x81
+
+#else
+  #define EPNUM_VIDEO_IN    0x81
+
+#endif
+
+uint8_t const desc_fs_configuration[] =
+{
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  // IAD for Video Control
+  TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 15)
+};
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+
+  return desc_fs_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] =
+{
+  (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+  "TinyUSB",                     // 1: Manufacturer
+  "TinyUSB Device",              // 2: Product
+  "123456",                      // 3: Serials, should use chip ID
+  "TinyUSB UVC",                 // 4: UVC Interface
+};
+
+static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
+{
+  (void) langid;
+
+  uint8_t chr_count;
+
+  if ( index == 0)
+  {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  }else
+  {
+    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+
+    const char* str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = strlen(str);
+    if ( chr_count > 31 ) chr_count = 31;
+
+    // Convert ASCII string into UTF-16
+    for(uint8_t i=0; i<chr_count; i++)
+    {
+      _desc_str[1+i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+
+  return _desc_str;
+}
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
new file mode 100644
index 000000000..6c6c14d35
--- /dev/null
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -0,0 +1,97 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenbreg
+ * Copyright (c) 2021 Koji KITAYAMA
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _USB_DESCRIPTORS_H_
+#define _USB_DESCRIPTORS_H_
+
+/* Time stamp base clock. It is a deprecated parameter. */
+#define UVC_CLOCK_FREQUENCY    27000000
+// video capture path
+#define UVC_ENTITY_CAP_INPUT_TERMINAL  0x01
+#define UVC_ENTITY_CAP_OUTPUT_TERMINAL 0x02
+
+enum {
+  ITF_NUM_VIDEO_CONTROL = 0,
+  ITF_NUM_VIDEO_STREAMING,
+  ITF_NUM_TOTAL
+};
+
+#define TUD_VIDEO_CAPTURE_DESC_LEN (TUD_VIDEO_DESC_IAD_LEN\
+    /* control */\
+    + TUD_VIDEO_DESC_STD_VC_LEN\
+    + TUD_VIDEO_DESC_CS_VC_LEN\
+    + TUD_VIDEO_DESC_INPUT_TERM_LEN\
+    + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + TUD_VIDEO_DESC_CS_VS_IN_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN)
+
+
+#define TUD_VIDEO_DESC_CS_VS_FMT_YUY2(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_YUY2, 16, _frmidx, _asrx, _asry, _interlace, _cp)
+#define TUD_VIDEO_DESC_CS_VS_FMT_NV12(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_NV12, 12, _frmidx, _asrx, _asry, _interlace, _cp)
+#define TUD_VIDEO_DESC_CS_VS_FMT_M420(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_M420, 12, _frmidx, _asrx, _asry, _interlace, _cp)
+#define TUD_VIDEO_DESC_CS_VS_FMT_I420(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_I420, 12, _frmidx, _asrx, _asry, _interlace, _cp)
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps) \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, ITF_NUM_TOTAL, _stridx), \
+    /* Video control 0 */ \
+    TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, 0), \
+      TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
+           TUD_VIDEO_DESC_INPUT_TERM_LEN + \
+           TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
+           UVC_CLOCK_FREQUENCY, 1, 1), \
+        TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL,\
+                                   VIDEO_TT_COMPOSITE_CONNECTOR, 0, 0), \
+        TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL,\
+                                   VIDEO_TT_STREAMING, 0, 1, 0),   \
+    /* Video stream alt. 0 */ \
+    TUD_VIDEO_DESC_STD_VS( 1, 0, 0, 0), \
+      /* Video stream header for without still image capture */ \
+      TUD_VIDEO_DESC_CS_VS_INPUT(1, \
+          TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + \
+          TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN,\
+          _epin, /*bmInfo*/ 0, UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+          0, 2, 0, 0, 0, 1, 0), \
+        /* Video stream format */ \
+        TUD_VIDEO_DESC_CS_VS_FMT_I420(0, 1, 0, 1, 1, 0, 0), \
+          /* Video stream frame format */ \
+          TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT( 1, 0, _width, _height, \
+                                                 _width * _height * 12, _width * _height * 12 * _fps, \
+                                                 _width * _height * 12, \
+                                                 (10000000/_fps), (10000000/1), (10000000/_fps), 166666), \
+    /* VS alt 1 */ \
+    TUD_VIDEO_DESC_STD_VS( 1, 1, 1, 0), \
+    /* EP */ \
+    TUD_VIDEO_DESC_EP_ISO(_epin, (_width * _height * 12 / 8) * _fps, 1)
+
+
+#endif
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 081860c83..489af8da2 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -228,8 +228,17 @@ typedef struct TU_ATTR_PACKED {
 //--------------------------------------------------------------------+
 // Requests
 //--------------------------------------------------------------------+
+
+/* 4.3.1.1 */
 typedef struct TU_ATTR_PACKED {
-  uint16_t bmHint;
+  struct TU_ATTR_PACKEDt {
+    uint16_t dwFrameInterval: 1;
+    uint16_t wKeyFrameRatel : 1;
+    uint16_t wPFrameRate    : 1;
+    uint16_t wCompQuality   : 1;
+    uint16_t wCompWindowSize: 1;
+    uint16_t                : 0;
+  } bmHint;
   uint8_t  bFormatIndex;
   uint8_t  bFrameIndex;
   uint32_t dwFrameInterval;
@@ -241,7 +250,12 @@ typedef struct TU_ATTR_PACKED {
   uint32_t dwMaxVideoFrameSize;
   uint32_t dwMaxPayloadTransferSize;
   uint32_t dwClockFrequency;
-  uint8_t  bmFramingInfo;
+  struct TU_ATTR_PACKED {
+    uint8_t FrameID   : 1;
+    uint8_t EndOfFrame: 1;
+    uint8_t EndOfSlice: 1;
+    uint8_t           : 0;
+  } bmFramingInfo;
   uint8_t  bPreferedVersion;
   uint8_t  bMinVersion;
   uint8_t  bMaxVersion;
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index ed703d79a..badd838a1 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -82,7 +82,7 @@ typedef struct
 
 } videod_interface_t;
 
-#define ITF_MEM_RESET_SIZE   offsetof(cdcd_interface_t, wanted_char)
+#define ITF_MEM_RESET_SIZE   offsetof(videod_interface_t, ctl_buf)
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -109,6 +109,14 @@ static uint16_t* _get_desc_ofs(videod_interface_t *self, unsigned itfnum)
   return NULL;
 }
 
+static tusb_desc_vs_itf_t const *_get_desc_vs(videod_interface_t const *self, unsigned itfnum)
+{
+  uint16_t const *ofs = _get_desc_ofs((videod_interface_t*)self, itfnum);
+  if (!ofs) return NULL;
+  return (tusb_desc_vs_itf_t const*)(self->beg + *ofs);
+}
+
+
 /** Find the first descriptor with the specified descriptor type.
  *
  * @param[in] beg     The head of descriptor byte array.
@@ -188,6 +196,10 @@ static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, unsigned enti
   return end;
 }
 
+/** Close current video control interface.
+ *
+ * @param[in,out] self     The context.
+ * @param[in]     altnum   The target alternate setting number. */
 static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
 {
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
@@ -206,6 +218,10 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
   return true;
 }
 
+/** Set the specified alternate setting to own video control interface.
+ *
+ * @param[in,out] self     The context.
+ * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum)
 {
   void const *beg = self->beg;
@@ -238,48 +254,6 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altn
   return true;
 }
 
-/** Set the specified alternate setting to own video control interface.
- *
- * @param[in,out] self     The context.
- * @param[in]     altnum   The target alternate setting number. */
-static bool _set_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum)
-{
-  void const *beg = self->beg;
-  void const *end = beg + self->len;
-  /* The head descriptor is a video control interface descriptor. */
-  unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber;
-  void const *cur = _find_desc_itf(beg, end, itfnum, altnum);
-  TU_VERIFY(cur < end);
-
-  tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
-  /* Support for up to 2 streaming interfaces only. */
-  TU_VERIFY(vc->ctl.bInCollection < 3);
-
-  /* Close the previous notification endpoint if it is opened */
-  if (self->ep_notif) {
-    usbd_edpt_close(rhport, self->ep_notif);
-    self->ep_notif = 0;
-  }
-  /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
-  cur += vc->std.bLength + vc->ctl.bLength;
-  /* Update to point the end of the video control interface descriptor. */
-  end  = cur + vc->ctl.wTotalLength;
-  /* Open the notification endpoint if it exist. */
-  if (vc->std.bNumEndpoints) {
-    /* Support for 1 endpoint only. */
-    TU_VERIFY(1 == vc->std.bNumEndpoints);
-    /* Find the notification endpoint descriptor. */
-    cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
-    TU_VERIFY(cur < end);
-    tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur;
-    /* Open the notification endpoint */
-    TU_ASSERT(usbd_edpt_open(rhport, notif));
-    self->ep_notif = notif->bEndpointAddress;
-  }
-  self->ofs[0] = (void const*)vc - beg;
-  return true;
-}
-
 /** Set the specified alternate setting to own video control interface.
  *
  * @param[in,out] self     The context.
@@ -293,7 +267,7 @@ static bool _close_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itf
   void const *cur = (void const*)vs + vs->std.bLength + vs->stm.bLength;
   /* The end of the video streaming interface descriptor. */
   void const *end = cur + vs->stm.wTotalLength;
-  if (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) {
+  for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) {
     cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
     TU_ASSERT(cur < end);
     tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
@@ -345,123 +319,28 @@ static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfn
   return true;
 }
 
-/** Set the specified alternate setting to own video control interface.
- *
- * @param[in,out] self     The context.
- * @param[in]     itfnum   The target interface number.
- * @param[in]     altnum   The target alternate setting number. */
-static bool _set_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum, unsigned altnum)
-{
-  unsigned i;
-  tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
-  void const *end = self->beg + self->len;
-  /* Set the end of the video control interface descriptor. */
-  void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength;
-
-  /* Check itfnum is valid */
-  unsigned bInCollection = vc->ctl.bInCollection;
-  for (i = 0; (i < bInCollection) && (vc->ctl.baInterfaceNr[i] != itfnum); ++i) ;
-  TU_VERIFY(i < bInCollection);
-
-  cur = _find_desc_itf(cur, end, itfnum, altnum);
-  TU_VERIFY(cur < end);
-  tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur;
-  /* Advance to the next descriptor after the class-specific VS interface header descriptor. */
-  cur += vs->std.bLength + vs->stm.bLength;
-  /* Update to point the end of the video control interface descriptor. */
-  end  = cur + vs->stm.wTotalLength;
-
-  switch (vs->stm.bDescriptorSubType) {
-  default: return false;
-  case VIDEO_CS_VS_INTERFACE_INPUT_HEADER:
-    /* Support for up to 2 endpoint only. */
-    TU_VERIFY(vc->std.bNumEndpoints < 3);
-    if (self->ep_sti) {
-      usbd_edpt_close(rhport, self->ep_sti);
-      self->ep_sti = 0;
-    }
-    if (self->ep_in) {
-      usbd_edpt_close(rhport, self->ep_in);
-      self->ep_in  = 0;
-    }
-    if (i = 0; i < vs->std.bNumEndpoints; ++i) {
-      cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
-      TU_VERIFY(cur < end);
-      tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
-      if (vs->stm.bEndpointAddress == ep->bEndpointAddress) {
-        /* video input endpoint */
-        TU_ASSERT(!self->ep_in);
-        TU_ASSERT(usbd_edpt_open(rhport, ep));
-        self->ep_in  = ep->bEndpointAddress;
-      } else {
-        /* still image input endpoint */
-        TU_ASSERT(!self->ep_sti);
-        TU_ASSERT(usbd_edpt_open(rhport, ep));
-        self->ep_sti = ep->bEndpointAddress;
-      }
-      cur += tu_desc_len(cur);
-    }
-    break;
-  case VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER:
-    /* Support for up to 1 endpoint only. */
-    TU_VERIFY(vc->std.bNumEndpoints < 2);
-    if (self->ep_out) {
-      usbd_edpt_close(rhport, self->ep_out);
-      self->ep_out = 0;
-    }
-    if (vs->std.bNumEndpoints) {
-      cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
-      TU_VERIFY(cur < end);
-      tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
-      if (vs->stm.bEndpointAddress == ep->bEndpointAddress) {
-        /* video output endpoint */
-        TU_ASSERT(usbd_edpt_open(rhport, ep));
-        self->ep_out = ep->bEndpointAddress;
-      }
-    }
-    break;
-  }
-  for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(ofs[0]); ++i) {
-    if (!self->ofs[i]) {
-      return true;
-    }
-    tusb_desc_interface_t const* itf = (tusb_desc_interface_t const*)(beg + ofs[i]);
-    if (itfnum == itf->bInterfaceNumber) return itf;
-  }
-  return NULL;
-  for (i = 0; i < sizeof(self->vs)/sizeof(self->vs[0]); ++i) {
-    if (!self->vs[i] || self->vs[i].stm.bInterfaceNumber == vs->stm.bInterfaceNumber) {
-      self->ofs[i] = (void const*)vs - self->beg;
-      return true;
-    }
-  }
-  return false;
-}
-
-static int handle_video_ctl_std_req_get_itf(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
-{
-  if (stage != CONTROL_STAGE_SETUP)
-    return VIDEO_NO_ERROR;
-  videod_interface_t *self = &_videod_itf[itf];
-  TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
-  tusb_desc_interface_t const *p = _get_desc_cur_itf(self, itfnum);
-  if (!p) return VIDEO_UNKNOWN;
-  if (tud_control_xfer(rhport, request, &p->bAlternateSettings, sizeof(p->bAlternateSettings)))
-    return VIDEO_NO_ERROR;
-  return VIDEO_UNKNOWN;
-}
-
 /** Handle a standard request to the video control interface. */
 static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
-  switch (p_request->bRequest) {
+  switch (request->bRequest) {
   case TUSB_REQ_GET_INTERFACE:
-    handle_video_ctl_std_req_get_itf(rhport, stage, request, itf);
-  case TUSB_REQ_SET_INTERFACE:
     if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-    if (_set_vc_itf(rhport, &_videod_itf[itf], request->wValue))
+    TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+    tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[itf]);
+    if (!vc) return VIDEO_UNKNOWN;
+    if (tud_control_xfer(rhport, request,
+			 (void*)&vc->std.bAlternateSetting,
+			 sizeof(vc->std.bAlternateSetting)))
       return VIDEO_NO_ERROR;
     return VIDEO_UNKNOWN;
+  case TUSB_REQ_SET_INTERFACE:
+    if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+    TU_VERIFY(0 == request->wLength, VIDEO_UNKNOWN);
+    if (!_close_vc_itf(rhport, &_videod_itf[itf]))
+      return VIDEO_UNKNOWN;
+    if (!_open_vc_itf(rhport, &_videod_itf[itf], request->wValue))
+      return VIDEO_UNKNOWN;
+    return VIDEO_NO_ERROR;
   default: /* Unknown/Unsupported request */
     TU_BREAKPOINT();
     return VIDEO_INVALID_REQUEST;
@@ -470,11 +349,11 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_
 
 static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
-  videod_interface_t *self = &_videod_itf[i];
+  videod_interface_t *self = &_videod_itf[itf];
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
   case VIDEO_VC_CTL_VIDEO_POWER_MODE:
-    switch (p_request->bRequest) {
+    switch (request->bRequest) {
     case VIDEO_REQUEST_SET_CUR:
       if (stage == CONTROL_STAGE_SETUP) {
         TU_LOG2("  Set Power Mode\r\n");
@@ -482,7 +361,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
         if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
           return VIDEO_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
-        if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, &self->power_mode);
+        if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, self->power_mode);
       }
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
@@ -497,7 +376,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
       if (stage == CONTROL_STAGE_SETUP) {
         TU_LOG2("  Get Info Power Mode\r\n");
         TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, &_cap_get_set, sizeof(_cap_get_set)))
+        if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
           return VIDEO_UNKNOWN;
       }
       return VIDEO_NO_ERROR;
@@ -505,7 +384,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
     }
     break;
   case VIDEO_VC_CTL_REQUEST_ERROR_CODE:
-    switch (p_request->bRequest) {
+    switch (request->bRequest) {
     case VIDEO_REQUEST_GET_CUR:
       if (stage == CONTROL_STAGE_SETUP) {
         TU_LOG2("  Get Error Code\r\n");
@@ -516,7 +395,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
     case VIDEO_REQUEST_GET_INFO:
       if (stage == CONTROL_STAGE_SETUP) {
         TU_LOG2("  Get Info Error Code\r\n");
-        if (tud_control_xfer(rhport, request, &_cap_get, sizeof(_cap_get)))
+        if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)))
           return VIDEO_UNKNOWN;
       }
       return VIDEO_NO_ERROR;
@@ -532,14 +411,17 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
 
 static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
-  switch (p_request->bmRequestType_bit.type) {
+  unsigned entity_id;
+  switch (request->bmRequestType_bit.type) {
   case TUSB_REQ_TYPE_STANDARD:
     return handle_video_ctl_std_req(rhport, stage, request, itf);
   case TUSB_REQ_TYPE_CLASS:
-    if (!TU_U16_HIGH(request->wIndex)) {
+    entity_id = TU_U16_HIGH(request->wIndex);
+    if (!entity_id) {
       return handle_video_ctl_cs_req(rhport, stage, request, itf);
     } else {
-      /* TODO: */
+      if (!_find_desc_entity(_get_desc_vc(&_videod_itf[itf]), entity_id))
+	return VIDEO_INVALID_REQUEST;
       return VIDEO_INVALID_REQUEST;
     }
   default:
@@ -549,16 +431,27 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_requ
 
 static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
-  switch (p_request->bRequest) {
+  unsigned itfnum;
+  switch (request->bRequest) {
   case TUSB_REQ_GET_INTERFACE:
-    handle_video_ctl_std_req_get_itf(rhport, stage, request, itf);
-  case TUSB_REQ_SET_INTERFACE:
-    videod_interface_t *self   = &_videod_itf[itf];
-    unsigned            itfnum = tu_u16_low(p_request->wIndex);
     if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-    if (_set_vs_itf(rhport, self, itfnum, request->wValue))
+    TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+    itfnum = tu_u16_low(request->wIndex);
+    tusb_desc_vs_itf_t const *vs = _get_desc_vs(&_videod_itf[itf], itfnum);
+    if (!vs) return VIDEO_UNKNOWN;
+    if (tud_control_xfer(rhport, request,
+			 (void*)&vs->std.bAlternateSetting,
+			 sizeof(vs->std.bAlternateSetting)))
       return VIDEO_NO_ERROR;
     return VIDEO_UNKNOWN;
+  case TUSB_REQ_SET_INTERFACE:
+    if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+    itfnum = tu_u16_low(request->wIndex);
+    if (!_close_vs_itf(rhport, &_videod_itf[itf], itfnum))
+      return VIDEO_UNKNOWN;
+    if (!_open_vs_itf(rhport, &_videod_itf[itf], itfnum, request->wValue))
+      return VIDEO_UNKNOWN;
+    return VIDEO_NO_ERROR;
   default: /* Unknown/Unsupported request */
     TU_BREAKPOINT();
     return VIDEO_INVALID_REQUEST;
@@ -567,56 +460,52 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_
 
 static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
-  videod_interface_t *self = &_videod_itf[i];
+  //  videod_interface_t *self = &_videod_itf[itf];
+  (void)rhport; (void)stage; (void)itf;
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
   case VIDEO_VS_CTL_PROBE:
-    switch (p_request->bRequest) {
+    TU_LOG2("  Probe ");
+    switch (request->bRequest) {
     case VIDEO_REQUEST_SET_CUR:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Set Power Mode\r\n");
-        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
-          return VIDEO_UNKNOWN;
-      } else if (stage == CONTROL_STAGE_ACK) {
-        if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, &self->power_mode);
-      }
-      return VIDEO_NO_ERROR;
+      TU_LOG2("Set\r\n");
+      return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_CUR:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Get Power Mode\r\n");
-        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
-          return VIDEO_UNKNOWN;
-      }
-      return VIDEO_NO_ERROR;
+      TU_LOG2("Get\r\n");
+      return VIDEO_UNKNOWN;
+    case VIDEO_REQUEST_GET_MIN:
+      TU_LOG2("Get Min\r\n");
+      return VIDEO_UNKNOWN;
+    case VIDEO_REQUEST_GET_MAX:
+      TU_LOG2("Get Man\r\n");
+      return VIDEO_UNKNOWN;
+    case VIDEO_REQUEST_GET_RES:
+      TU_LOG2("Get Res\r\n");
+      return VIDEO_UNKNOWN;
+    case VIDEO_REQUEST_GET_DEF:
+      TU_LOG2("Get Def\r\n");
+      return VIDEO_UNKNOWN;
+    case VIDEO_REQUEST_GET_LEN:
+      TU_LOG2("Get Len\r\n");
+      return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_INFO:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Get Info Power Mode\r\n");
-        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, &_cap_get_set, sizeof(_cap_get_set)))
-          return VIDEO_UNKNOWN;
-      }
-      return VIDEO_NO_ERROR;
+      TU_LOG2("Get Info\r\n");
+      return VIDEO_UNKNOWN;
     default: break;
     }
     break;
   case VIDEO_VS_CTL_COMMIT:
-    switch (p_request->bRequest) {
+    TU_LOG2("  Commit ");
+    switch (request->bRequest) {
+    case VIDEO_REQUEST_SET_CUR:
+      TU_LOG2("Set\r\n");
+      return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_CUR:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Get Error Code\r\n");
-        if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(self->error_code)))
-          return VIDEO_UNKNOWN;
-      }
-      return VIDEO_NO_ERROR;
+      TU_LOG2("Get\r\n");
+      return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_INFO:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Get Info Error Code\r\n");
-        if (tud_control_xfer(rhport, request, &_cap_get, sizeof(_cap_get)))
-          return VIDEO_UNKNOWN;
-      }
-      return VIDEO_NO_ERROR;
+      TU_LOG2("Get Info\r\n");
+      return VIDEO_UNKNOWN;
     default: break;
     }
     break;
@@ -629,7 +518,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
 
 static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
-  switch (p_request->bmRequestType_bit.type) {
+  switch (request->bmRequestType_bit.type) {
   case TUSB_REQ_TYPE_STANDARD:
     return handle_video_stm_std_req(rhport, stage, request, itf);
   case TUSB_REQ_TYPE_CLASS:
@@ -642,40 +531,14 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_requ
   return VIDEO_UNKNOWN;
 }
 
-static void _prep_out_transaction(cdcd_interface_t* p_cdc)
-{
-  uint8_t const rhport = TUD_OPT_RHPORT;
-  uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff);
-
-  // Prepare for incoming data but only allow what we can store in the ring buffer.
-  // TODO Actually we can still carry out the transfer, keeping count of received bytes
-  // and slowly move it to the FIFO when read().
-  // This pre-check reduces endpoint claiming
-  TU_VERIFY(available >= sizeof(p_cdc->epout_buf), );
-
-  // claim endpoint
-  TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out), );
-
-  // fifo can be changed before endpoint is claimed
-  available = tu_fifo_remaining(&p_cdc->rx_ff);
-
-  if ( available >= sizeof(p_cdc->epout_buf) )
-  {
-    usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf));
-  }else
-  {
-    // Release endpoint since we don't make any transfer
-    usbd_edpt_release(rhport, p_cdc->ep_out);
-  }
-}
-
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
 bool tud_video_n_connected(uint8_t itf)
 {
+  (void)itf;
   // DTR (bit 0) active  is considered as connected
-  return tud_ready() && tu_bit_test(_cdcd_itf[itf].line_state, 0);
+  return tud_ready();
 }
 
 //--------------------------------------------------------------------+
@@ -695,7 +558,7 @@ void videod_init(void)
 
   for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i)
   {
-    videod_interface_t* p_video = &_videod_itf[i];
+    // videod_interface_t* p_video = &_videod_itf[i];
 
     // TODO
   }
@@ -716,14 +579,14 @@ void videod_reset(uint8_t rhport)
 
 uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
 {
-  TU_VERIFY(TUSB_CLASS_VIDEO           == itf_desc->bInterfaceClass &&
-            VIDEO_SUBCLASS_CONTROL     == itf_desc->bInterfaceSubClass &&
-            VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bFunctionProtool, 0);
+  TU_VERIFY((TUSB_CLASS_VIDEO           == itf_desc->bInterfaceClass) &&
+	    (VIDEO_SUBCLASS_CONTROL     == itf_desc->bInterfaceSubClass) &&
+	    (VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bInterfaceProtocol), 0);
 
   /* Find available interface */
   videod_interface_t *self = NULL;
   for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) {
-    if (!_videod_itf[i].vc) {
+    if (!_videod_itf[i].beg) {
       self = &_videod_itf[i];
       break;
     }
@@ -758,24 +621,23 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
 {
   int err;
-  if (p_request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) {
+  if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) {
     return false;
   }
-  unsigned itfnum = tu_u16_low(p_request->wIndex);
+  unsigned itfnum = tu_u16_low(request->wIndex);
   /* Identify which interface to use */
   int itf;
   tusb_desc_vc_itf_t const *vc = NULL;
   for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
-    vc = _videod_itf[itf].vc;
-    if (!vc) continue;
-    unsigned beg_itfnum = vc->bInterfaceNumber;
+    vc = _get_desc_vc(&_videod_itf[itf]);
+    unsigned beg_itfnum = vc->std.bInterfaceNumber;
     unsigned end_itfnum = vc->ctl.bInCollection;
     if (beg_itfnum <= itfnum && itfnum < end_itfnum)
       break;
   }
   if (itf == CFG_TUD_VIDEO) return false;
 
-  if (itfnum == vc->bInterfaceNumber) {
+  if (itfnum == vc->std.bInterfaceNumber) {
     /* To video control interface */
     err = handle_video_ctl_req(rhport, stage, request, itf);
   } else {
@@ -789,68 +651,8 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
 
 bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
 {
-  (void) result;
-
-  uint8_t itf;
-  videod_interface_t* p_video;
-
-  // Identify which interface to use
-  for (itf = 0; itf < CFG_TUD_CDC; itf++)
-  {
-    p_video = &_videod_itf[itf];
-    if ( ( ep_addr == p_video->ep_out ) || ( ep_addr == p_video->ep_in ) ) break;
-  }
-  TU_ASSERT(itf < CFG_TUD_CDC);
-
-  // Received new data
-  if ( ep_addr == p_video->ep_out )
-  {
-    tu_fifo_write_n(&p_video->rx_ff, &p_video->epout_buf, xferred_bytes);
-    
-    // Check for wanted char and invoke callback if needed
-    if ( tud_cdc_rx_wanted_cb && (((signed char) p_video->wanted_char) != -1) )
-    {
-      for ( uint32_t i = 0; i < xferred_bytes; i++ )
-      {
-        if ( (p_video->wanted_char == p_video->epout_buf[i]) && !tu_fifo_empty(&p_video->rx_ff) )
-        {
-          tud_cdc_rx_wanted_cb(itf, p_video->wanted_char);
-        }
-      }
-    }
-    
-    // invoke receive callback (if there is still data)
-    if (tud_cdc_rx_cb && !tu_fifo_empty(&p_video->rx_ff) ) tud_cdc_rx_cb(itf);
-    
-    // prepare for OUT transaction
-    _prep_out_transaction(p_video);
-  }
-  
-  // Data sent to host, we continue to fetch from tx fifo to send.
-  // Note: This will cause incorrect baudrate set in line coding.
-  //       Though maybe the baudrate is not really important !!!
-  if ( ep_addr == p_video->ep_in )
-  {
-    // invoke transmit callback to possibly refill tx fifo
-    if ( tud_cdc_tx_complete_cb ) tud_cdc_tx_complete_cb(itf);
-
-    if ( 0 == tud_cdc_n_write_flush(itf) )
-    {
-      // If there is no data left, a ZLP should be sent if
-      // xferred_bytes is multiple of EP Packet size and not zero
-      if ( !tu_fifo_count(&p_video->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE-1))) )
-      {
-        if ( usbd_edpt_claim(rhport, p_video->ep_in) )
-        {
-          usbd_edpt_xfer(rhport, p_video->ep_in, NULL, 0);
-        }
-      }
-    }
-  }
-
-  // nothing to do with notif endpoint for now
-
-  return true;
+  (void)rhport; (void)ep_addr; (void)result; (void)xferred_bytes;
+  return false;
 }
 
 #endif
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index cd04b7391..95d352524 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -46,6 +46,8 @@ TU_ATTR_WEAK bool tud_video_set_cur_cb(uint8_t rhport, tusb_control_request_t co
 // Invoked when GET_CUR request received
 TU_ATTR_WEAK bool tud_video_get_cur_cb(uint8_t rhport, tusb_control_request_t const *request);
 
+/* @return video_error_code_t */
+TU_ATTR_WEAK int tud_video_power_mode_cb(unsigned itf, uint8_t power_mod);
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+

From d026f174576b0567e2a954292bd4339349e3f139 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 1 Aug 2021 17:11:43 +0900
Subject: [PATCH 0510/2085] fix: configuration descriptor has incorrectly sizes

update some descriptors
---
 .../video_capture/src/usb_descriptors.c       |  2 +-
 .../video_capture/src/usb_descriptors.h       | 59 ++++++++++-------
 src/class/video/video.h                       | 63 +++++++++++++++----
 src/class/video/video_device.c                | 23 ++++---
 4 files changed, 102 insertions(+), 45 deletions(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index df8c41721..067c1d946 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -102,7 +102,7 @@ uint8_t const * tud_descriptor_device_cb(void)
 uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
   // IAD for Video Control
   TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 15)
 };
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 6c6c14d35..d37ab1338 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -39,18 +39,27 @@ enum {
   ITF_NUM_TOTAL
 };
 
-#define TUD_VIDEO_CAPTURE_DESC_LEN (TUD_VIDEO_DESC_IAD_LEN\
+#define TUD_VIDEO_CAPTURE_DESC_LEN (\
+    TUD_VIDEO_DESC_IAD_LEN\
     /* control */\
     + TUD_VIDEO_DESC_STD_VC_LEN\
-    + TUD_VIDEO_DESC_CS_VC_LEN\
+    + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
     + TUD_VIDEO_DESC_INPUT_TERM_LEN\
     + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
     /* Interface 1, Alternate 0 */\
     + TUD_VIDEO_DESC_STD_VS_LEN\
-    + TUD_VIDEO_DESC_CS_VS_IN_LEN\
+    + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
     + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-    + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN)
+    + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+  )
 
+#if 0
+    /* Interface 1, Alternate 1 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + 7/* Endpoint */\
+
+#endif
 
 #define TUD_VIDEO_DESC_CS_VS_FMT_YUY2(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
   TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_YUY2, 16, _frmidx, _asrx, _asry, _interlace, _cp)
@@ -64,34 +73,40 @@ enum {
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, ITF_NUM_TOTAL, _stridx), \
     /* Video control 0 */ \
-    TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, 0), \
+    TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
       TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-           TUD_VIDEO_DESC_INPUT_TERM_LEN + \
-           TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
+           /* wTotalLength - bLength */ \
+           TUD_VIDEO_DESC_INPUT_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
            UVC_CLOCK_FREQUENCY, 1, 1), \
         TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL,\
                                    VIDEO_TT_COMPOSITE_CONNECTOR, 0, 0), \
         TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL,\
-                                   VIDEO_TT_STREAMING, 0, 1, 0),   \
+                                   VIDEO_TT_STREAMING, 0, 1, 0), \
     /* Video stream alt. 0 */ \
     TUD_VIDEO_DESC_STD_VS( 1, 0, 0, 0), \
       /* Video stream header for without still image capture */ \
-      TUD_VIDEO_DESC_CS_VS_INPUT(1, \
-          TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN + \
-          TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN,\
-          _epin, /*bmInfo*/ 0, UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
-          0, 2, 0, 0, 0, 1, 0), \
+      TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+          /*wTotalLength - bLength */\
+          TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+          + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+          + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+          _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+          /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+          /*bControlSize*/1, /*bmaControls(1)*/0), \
         /* Video stream format */ \
-        TUD_VIDEO_DESC_CS_VS_FMT_I420(0, 1, 0, 1, 1, 0, 0), \
+        TUD_VIDEO_DESC_CS_VS_FMT_I420(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\
+          /*bDefaultFrameIndex*/1, 1, 1, 0, /*bCopyProtect*/0), \
           /* Video stream frame format */ \
-          TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT( 1, 0, _width, _height, \
-                                                 _width * _height * 12, _width * _height * 12 * _fps, \
-                                                 _width * _height * 12, \
-                                                 (10000000/_fps), (10000000/1), (10000000/_fps), 166666), \
-    /* VS alt 1 */ \
-    TUD_VIDEO_DESC_STD_VS( 1, 1, 1, 0), \
-    /* EP */ \
-    TUD_VIDEO_DESC_EP_ISO(_epin, (_width * _height * 12 / 8) * _fps, 1)
+          TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
+              _width * _height * 12, _width * _height * 12 * _fps, \
+              _width * _height * 12, \
+              (10000000/_fps), (10000000/1), (10000000/_fps), 166666), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709,\
+           VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+    /* VS alt 1 */\
+    TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \
+      /* EP */ \
+      TUD_VIDEO_DESC_EP_ISO(_epin, (_width * _height * 12 / 8) * _fps, 1)
 
 
 #endif
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 489af8da2..597ad7d39 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -29,6 +29,35 @@
 
 #include "common/tusb_common.h"
 
+typedef enum {
+  VIDEO_COLOR_PRIMARIES_UNDEFINED = 0x00,
+  VIDEO_COLOR_PRIMARIES_BT709,
+  VIDEO_COLOR_PRIMARIES_BT470_2M,
+  VIDEO_COLOR_PRIMARIES_BT470_2BG,
+  VIDEO_COLOR_PRIMARIES_SMPTE170M,
+  VIDEO_COLOR_PRIMARIES_SMPTE240M,
+} video_color_primaries_t;
+
+typedef enum {
+  VIDEO_COLOR_XFER_CH_UNDEFINED = 0x00,
+  VIDEO_COLOR_XFER_CH_BT709,
+  VIDEO_COLOR_XFER_CH_BT470_2M,
+  VIDEO_COLOR_XFER_CH_BT470_2BG,
+  VIDEO_COLOR_XFER_CH_SMPTE170M,
+  VIDEO_COLOR_XFER_CH_SMPTE240M,
+  VIDEO_COLOR_XFER_CH_LINEAR,
+  VIDEO_COLOR_XFER_CH_SRGB,
+} video_color_transfer_characteristics_t;
+
+typedef enum {
+  VIDEO_COLOR_COEF_UNDEFINED = 0x00,
+  VIDEO_COLOR_COEF_BT709,
+  VIDEO_COLOR_COEF_FCC,
+  VIDEO_COLOR_COEF_BT470_2BG,
+  VIDEO_COLOR_COEF_SMPTE170M,
+  VIDEO_COLOR_COEF_SMPTE240M,
+} video_color_matrix_coefficients_t;
+
 /* 4.2.1.2 */
 typedef enum {
   VIDEO_NO_ERROR = 0, /* The request succeeded. */
@@ -69,7 +98,7 @@ typedef enum
   VIDEO_CS_VC_INTERFACE_PROCESSING_UNIT,
   VIDEO_CS_VC_INTERFACE_EXTENSION_UNIT,
   VIDEO_CS_VC_INTERFACE_ENCODING_UNIT,
-} vide_cs_vc_interface_subtype_t;
+} video_cs_vc_interface_subtype_t;
 
 /* A.6 */
 typedef enum
@@ -278,6 +307,7 @@ typedef struct TU_ATTR_PACKED {
 #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN      27
 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN 38
 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN 26
+#define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN   6
 
 /* 2.2 compression formats */
 #define TUD_VIDEO_GUID_YUY2   0x59,0x55,0x59,0x32,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00
@@ -296,8 +326,8 @@ typedef struct TU_ATTR_PACKED {
 
 /* 3.7.2 */
 #define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, _coll, ...)	\
-  TUD_VIDEO_DESC_CS_VC_LEN + _coll, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \
-  U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE(_totallen + TUD_VIDEO_DESC_CS_VC_LEN), \
+  TUD_VIDEO_DESC_CS_VC_LEN + (_coll), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \
+  U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VC_LEN + (_coll)), \
   U32_TO_U8S_LE(_clkfreq), _coll, __VA_ARGS__
 
 /* 3.7.2.1 */
@@ -307,30 +337,31 @@ typedef struct TU_ATTR_PACKED {
 
 /* 3.7.2.2 */
 #define TUD_VIDEO_DESC_OUTPUT_TERM(_tid, _tt, _at, _srcid, _stridx) \
-  TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, \
-    _tid, U16_TO_U8S_LE(_tt), _at, _stridx
+  TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, \
+    _tid, U16_TO_U8S_LE(_tt), _at, _srcid, _stridx
 
 /* 3.9.1 */
-#define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx)   \
-  TUD_VIDEO_DESC_STD_VC_LEN, TUSB_DESC_INTERFACE, _itfnum, _alt, \
+#define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx) \
+  TUD_VIDEO_DESC_STD_VS_LEN, TUSB_DESC_INTERFACE, _itfnum, _alt, \
   _epn, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_STREAMING, VIDEO_INT_PROTOCOL_CODE_15, _stridx
 
 /* 3.9.2.1 */
-#define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totlen, _epn, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, ...) \
+#define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, ...) \
   TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \
   VIDEO_CS_VS_INTERFACE_INPUT_HEADER, _numfmt, \
-  U16_TO_U8S_LE(_totlen + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz)), \
-  _epn, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, __VA_ARGS__
+  U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz)), \
+  _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, __VA_ARGS__
 
 /* 3.9.2.2 */
-#define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totlen, _epn, _inf, _termlnk, _ctlsz, ...) \
+#define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _ctlsz, ...) \
   TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \
   VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, _numfmt, \
-  U16_TO_U8S_LE(_totlen + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz)), \
-  _epn, _inf, _termlnk,  _trgusg, _ctlsz, __VA_ARGS__
+  U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz)), \
+  _ep, _inf, _termlnk, _ctlsz, __VA_ARGS__
 
 /* Uncompressed 3.1.1 */
 #define TUD_VIDEO_GUID(_g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15) _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15
+
 #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfrmdesc, \
   _guid, _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \
   TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, \
@@ -353,6 +384,12 @@ typedef struct TU_ATTR_PACKED {
   _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
   U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), _numfrminterval, __VA_ARGS__
 
+/* 3.9.2.6 */
+#define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(_color, _trns, _mat) \
+  TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_COLORFORMAT, \
+  _color, _trns, _mat
+
 /* 3.10.1.1 */
 #define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) \
   7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index badd838a1..94ae325dc 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -183,7 +183,7 @@ static void const* _find_desc_itf(void const *beg, void const *end, unsigned itf
 static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, unsigned entityid)
 {
   void const *beg = (void const*)vc;
-  void const *end = beg + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength;
+  void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength;
   for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
     tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
     if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL  == itf->bDescriptorSubtype ||
@@ -206,7 +206,7 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
   /* The next descriptor after the class-specific VC interface header descriptor. */
   void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength;
   /* The end of the video control interface descriptor. */
-  void const *end = cur + vc->ctl.wTotalLength;
+  void const *end = (void const*)vc + vc->std.bLength + vc->ctl.wTotalLength;
   if (vc->std.bNumEndpoints) {
     /* Find the notification endpoint descriptor. */
     cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
@@ -224,21 +224,25 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
  * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum)
 {
+  TU_LOG2("    open VC %d\r\n", altnum);
   void const *beg = self->beg;
   void const *end = beg + self->len;
   /* The first descriptor is a video control interface descriptor. */
   unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber;
   void const *cur = _find_desc_itf(beg, end, itfnum, altnum);
+  TU_LOG2("    cur %ld\r\n", cur - beg);
   TU_VERIFY(cur < end);
 
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
+  TU_LOG2("    bInCollection %d\r\n", vc->ctl.bInCollection);
   /* Support for up to 2 streaming interfaces only. */
   TU_ASSERT(vc->ctl.bInCollection < 3);
 
+  /* Update to point the end of the video control interface descriptor. */
+  end  = cur + vc->std.bLength + vc->ctl.wTotalLength;
   /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
   cur += vc->std.bLength + vc->ctl.bLength;
-  /* Update to point the end of the video control interface descriptor. */
-  end  = cur + vc->ctl.wTotalLength;
+  TU_LOG2("    bNumEndpoints %d\r\n", vc->std.bNumEndpoints);
   /* Open the notification endpoint if it exist. */
   if (vc->std.bNumEndpoints) {
     /* Support for 1 endpoint only. */
@@ -266,7 +270,7 @@ static bool _close_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itf
   /* The next of the video streaming interface header descriptor. */
   void const *cur = (void const*)vs + vs->std.bLength + vs->stm.bLength;
   /* The end of the video streaming interface descriptor. */
-  void const *end = cur + vs->stm.wTotalLength;
+  void const *end = (void const*)vs + vs->std.bLength + vs->stm.wTotalLength;
   for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) {
     cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
     TU_ASSERT(cur < end);
@@ -285,6 +289,7 @@ static bool _close_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itf
  * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum, unsigned altnum)
 {
+  TU_LOG2("    open VS %d,%d\r\n", itfnum, altnum);
   uint16_t   *ofs = NULL;
   for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(self->ofs[0]); ++i) {
     if (!self->ofs[i]) {
@@ -297,17 +302,17 @@ static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfn
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
   void const *end = self->beg + self->len;
   /* Set the end of the video control interface descriptor. */
-  void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength + vc->ctl.wTotalLength;
+  void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.wTotalLength;
 
   cur = _find_desc_itf(cur, end, itfnum, altnum);
   TU_VERIFY(cur < end);
   tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur;
   /* Support for up to 2 endpoint only. */
   TU_ASSERT(vs->std.bNumEndpoints < 3);
+  /* Update to point the end of the video control interface descriptor. */
+  end  = cur + vs->std.bLength + vs->stm.wTotalLength;
   /* Advance to the next descriptor after the class-specific VS interface header descriptor. */
   cur += vs->std.bLength + vs->stm.bLength;
-  /* Update to point the end of the video control interface descriptor. */
-  end  = cur + vs->stm.wTotalLength;
   for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) {
     cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
     TU_VERIFY(cur < end);
@@ -612,7 +617,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
     itfnum = vc->ctl.baInterfaceNr[i];
     if (!_open_vs_itf(rhport, self, itfnum, 0)) return 0;
   }
-  return end - cur;
+  return (uintptr_t)cur - (uintptr_t)itf_desc;
 }
 
 // Invoked when a control transfer occurred on an interface of this class

From c52cf9c8a5c3cbc7ebe0c4409e0b6df1ea138b30 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 1 Aug 2021 17:51:15 +0900
Subject: [PATCH 0511/2085] fix: endpoint descriptor has incorrectly settings

---
 .../device/video_capture/src/usb_descriptors.c |  2 +-
 .../device/video_capture/src/usb_descriptors.h | 18 +++++-------------
 2 files changed, 6 insertions(+), 14 deletions(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 067c1d946..d3544cc63 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -104,7 +104,7 @@ uint8_t const desc_fs_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
   // IAD for Video Control
-  TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 15)
+  TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 15, 256)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index d37ab1338..246125217 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -51,15 +51,10 @@ enum {
     + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
     + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
     + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
-    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
-  )
-
-#if 0
     /* Interface 1, Alternate 1 */\
     + TUD_VIDEO_DESC_STD_VS_LEN\
     + 7/* Endpoint */\
-
-#endif
+  )
 
 #define TUD_VIDEO_DESC_CS_VS_FMT_YUY2(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
   TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_YUY2, 16, _frmidx, _asrx, _asry, _interlace, _cp)
@@ -70,7 +65,7 @@ enum {
 #define TUD_VIDEO_DESC_CS_VS_FMT_I420(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
   TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_I420, 12, _frmidx, _asrx, _asry, _interlace, _cp)
 
-#define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps) \
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, ITF_NUM_TOTAL, _stridx), \
     /* Video control 0 */ \
     TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
@@ -88,25 +83,22 @@ enum {
       TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
           /*wTotalLength - bLength */\
           TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-          + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
-          + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+          + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, \
           _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
           /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
           /*bControlSize*/1, /*bmaControls(1)*/0), \
         /* Video stream format */ \
         TUD_VIDEO_DESC_CS_VS_FMT_I420(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\
-          /*bDefaultFrameIndex*/1, 1, 1, 0, /*bCopyProtect*/0), \
+          /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
           /* Video stream frame format */ \
           TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
               _width * _height * 12, _width * _height * 12 * _fps, \
               _width * _height * 12, \
               (10000000/_fps), (10000000/1), (10000000/_fps), 166666), \
-        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709,\
-           VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
     /* VS alt 1 */\
     TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \
       /* EP */ \
-      TUD_VIDEO_DESC_EP_ISO(_epin, (_width * _height * 12 / 8) * _fps, 1)
+      TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
 
 
 #endif

From 20572a6ed22ef54a511b731dc6044928d9ad5993 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 4 Aug 2021 00:32:16 +0900
Subject: [PATCH 0512/2085] Fix regarding standard video stream request

---
 .../video_capture/src/usb_descriptors.h       |  5 +++-
 src/class/video/video_device.c                | 23 +++++++++++--------
 2 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 246125217..396131f83 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -56,6 +56,9 @@ enum {
     + 7/* Endpoint */\
   )
 
+/* Windows support YUV2 and NV12
+ * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
+
 #define TUD_VIDEO_DESC_CS_VS_FMT_YUY2(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
   TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_YUY2, 16, _frmidx, _asrx, _asry, _interlace, _cp)
 #define TUD_VIDEO_DESC_CS_VS_FMT_NV12(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
@@ -88,7 +91,7 @@ enum {
           /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
           /*bControlSize*/1, /*bmaControls(1)*/0), \
         /* Video stream format */ \
-        TUD_VIDEO_DESC_CS_VS_FMT_I420(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\
+        TUD_VIDEO_DESC_CS_VS_FMT_NV12(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\
           /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
           /* Video stream frame format */ \
           TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 94ae325dc..bee80d6e8 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -321,6 +321,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfn
     cur += tu_desc_len(cur);
   }
   *ofs = (void const*)vs - self->beg;
+  TU_LOG2("    done\r\n");
   return true;
 }
 
@@ -626,6 +627,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
 {
   int err;
+  int (*handle_video_req)(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) = NULL;
   if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) {
     return false;
   }
@@ -635,20 +637,21 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   tusb_desc_vc_itf_t const *vc = NULL;
   for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
     vc = _get_desc_vc(&_videod_itf[itf]);
-    unsigned beg_itfnum = vc->std.bInterfaceNumber;
-    unsigned end_itfnum = vc->ctl.bInCollection;
-    if (beg_itfnum <= itfnum && itfnum < end_itfnum)
+    if (itfnum == vc->std.bInterfaceNumber) {
+      handle_video_req = handle_video_ctl_req;
       break;
+    }
+    int i;
+    int bInCollection = vc->ctl.bInCollection;
+    for (i = 0; i < bInCollection && itfnum != vc->ctl.baInterfaceNr[i]; ++i) ;
+    if (i < bInCollection) {
+      handle_video_req = handle_video_stm_req;
+      break;
+    }
   }
   if (itf == CFG_TUD_VIDEO) return false;
 
-  if (itfnum == vc->std.bInterfaceNumber) {
-    /* To video control interface */
-    err = handle_video_ctl_req(rhport, stage, request, itf);
-  } else {
-    /* To video streaming interface */
-    err = handle_video_stm_req(rhport, stage, request, itf);
-  }
+  err = handle_video_req(rhport, stage, request, itf);
   _videod_itf[itf].error_code = (uint8_t)err;
   if (err) return false;
   return true;

From 4995d9cbd2022b703edf4ca4bdef8ee43724fd99 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 9 Aug 2021 17:11:05 +0900
Subject: [PATCH 0513/2085] Fix handling for set_interface

---
 .../video_capture/src/usb_descriptors.h       | 11 ++++---
 src/class/video/video.h                       | 30 +++++++++----------
 src/class/video/video_device.c                |  9 ++----
 3 files changed, 24 insertions(+), 26 deletions(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 396131f83..e7b47b66a 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -51,6 +51,7 @@ enum {
     + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
     + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
     + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
     /* Interface 1, Alternate 1 */\
     + TUD_VIDEO_DESC_STD_VS_LEN\
     + 7/* Endpoint */\
@@ -75,7 +76,7 @@ enum {
       TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
            /* wTotalLength - bLength */ \
            TUD_VIDEO_DESC_INPUT_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-           UVC_CLOCK_FREQUENCY, 1, 1), \
+           UVC_CLOCK_FREQUENCY, 1), \
         TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL,\
                                    VIDEO_TT_COMPOSITE_CONNECTOR, 0, 0), \
         TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL,\
@@ -86,10 +87,11 @@ enum {
       TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
           /*wTotalLength - bLength */\
           TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-          + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, \
+          + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+          + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
           _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
           /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
-          /*bControlSize*/1, /*bmaControls(1)*/0), \
+          /*bmaControls(1)*/0), \
         /* Video stream format */ \
         TUD_VIDEO_DESC_CS_VS_FMT_NV12(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\
           /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
@@ -97,7 +99,8 @@ enum {
           TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
               _width * _height * 12, _width * _height * 12 * _fps, \
               _width * _height * 12, \
-              (10000000/_fps), (10000000/1), (10000000/_fps), 166666), \
+              (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+          TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
     /* VS alt 1 */\
     TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \
       /* EP */ \
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 597ad7d39..773c87845 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -325,10 +325,10 @@ typedef struct TU_ATTR_PACKED {
   _nEPs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_CONTROL, VIDEO_INT_PROTOCOL_CODE_15, _stridx
 
 /* 3.7.2 */
-#define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, _coll, ...)	\
-  TUD_VIDEO_DESC_CS_VC_LEN + (_coll), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \
-  U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VC_LEN + (_coll)), \
-  U32_TO_U8S_LE(_clkfreq), _coll, __VA_ARGS__
+#define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, ...)	\
+  TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \
+  U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__))), \
+  U32_TO_U8S_LE(_clkfreq), TU_ARGS_NUM(__VA_ARGS__), __VA_ARGS__
 
 /* 3.7.2.1 */
 #define TUD_VIDEO_DESC_INPUT_TERM(_tid, _tt, _at, _stridx) \
@@ -346,18 +346,18 @@ typedef struct TU_ATTR_PACKED {
   _epn, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_STREAMING, VIDEO_INT_PROTOCOL_CODE_15, _stridx
 
 /* 3.9.2.1 */
-#define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, ...) \
-  TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \
+#define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, ...) \
+  TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \
   VIDEO_CS_VS_INTERFACE_INPUT_HEADER, _numfmt, \
-  U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (_ctlsz)), \
-  _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, _ctlsz, __VA_ARGS__
+  U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \
+  _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
 /* 3.9.2.2 */
-#define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _ctlsz, ...) \
-  TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz), TUSB_DESC_CS_INTERFACE, \
+#define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totallen, _ep, _inf, _termlnk, ...) \
+  TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \
   VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, _numfmt, \
-  U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (_ctlsz)), \
-  _ep, _inf, _termlnk, _ctlsz, __VA_ARGS__
+  U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \
+  _ep, _inf, _termlnk, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
 /* Uncompressed 3.1.1 */
 #define TUD_VIDEO_GUID(_g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15) _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15
@@ -378,11 +378,11 @@ typedef struct TU_ATTR_PACKED {
   U32_TO_U8S_LE(_minfrminterval), U32_TO_U8S_LE(_maxfrminterval), U32_TO_U8S_LE(_frmintervalstep)
 
 /* Uncompressed 3.1.2 Table 3-4 */
-#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _numfrminterval, ...) \
-  TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN + _numfrminterval * 4, \
+#define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \
+  TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \
   TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \
   _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
-  U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), _numfrminterval, __VA_ARGS__
+  U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
 /* 3.9.2.6 */
 #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(_color, _trns, _mat) \
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index bee80d6e8..001de388e 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -321,7 +321,6 @@ static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfn
     cur += tu_desc_len(cur);
   }
   *ofs = (void const*)vs - self->beg;
-  TU_LOG2("    done\r\n");
   return true;
 }
 
@@ -346,6 +345,7 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_
       return VIDEO_UNKNOWN;
     if (!_open_vc_itf(rhport, &_videod_itf[itf], request->wValue))
       return VIDEO_UNKNOWN;
+    tud_control_status(rhport, request);
     return VIDEO_NO_ERROR;
   default: /* Unknown/Unsupported request */
     TU_BREAKPOINT();
@@ -457,6 +457,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_
       return VIDEO_UNKNOWN;
     if (!_open_vs_itf(rhport, &_videod_itf[itf], itfnum, request->wValue))
       return VIDEO_UNKNOWN;
+    tud_control_status(rhport, request);
     return VIDEO_NO_ERROR;
   default: /* Unknown/Unsupported request */
     TU_BREAKPOINT();
@@ -612,12 +613,6 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
     cur = _next_desc_itf(cur, end);
   }
   self->len = (uintptr_t)cur - (uintptr_t)itf_desc;
-  /*------------- Video Stream Interface -------------*/
-  unsigned itfnum = 0;
-  for (unsigned i = 0; i < bInCollection; ++i) {
-    itfnum = vc->ctl.baInterfaceNr[i];
-    if (!_open_vs_itf(rhport, self, itfnum, 0)) return 0;
-  }
   return (uintptr_t)cur - (uintptr_t)itf_desc;
 }
 

From 2b4e02f192446f4fdf92c7e83ab260ae743503e9 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 15 Aug 2021 18:07:53 +0900
Subject: [PATCH 0514/2085] Implement some mandatory requests on streaming
 interface

---
 .../video_capture/src/usb_descriptors.h       |   2 +-
 src/class/video/video.h                       |  92 +++++---
 src/class/video/video_device.c                | 213 +++++++++++++-----
 src/class/video/video_device.h                |   6 +
 4 files changed, 224 insertions(+), 89 deletions(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index e7b47b66a..867e9af42 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -29,7 +29,7 @@
 
 /* Time stamp base clock. It is a deprecated parameter. */
 #define UVC_CLOCK_FREQUENCY    27000000
-// video capture path
+/* video capture path */
 #define UVC_ENTITY_CAP_INPUT_TERMINAL  0x01
 #define UVC_ENTITY_CAP_OUTPUT_TERMINAL 0x02
 
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 773c87845..17e1658b5 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -81,15 +81,13 @@ typedef enum {
 } video_subclass_type_t;
 
 /* A.3 */
-typedef enum
-{
+typedef enum {
   VIDEO_INT_PROTOCOL_CODE_UNDEF = 0x00,
   VIDEO_INT_PROTOCOL_CODE_15,
 } video_interface_protocol_code_t;
 
 /* A.5 */
-typedef enum
-{
+typedef enum {
   VIDEO_CS_VC_INTERFACE_VC_DESCRIPTOR_UNDEF = 0x00,
   VIDEO_CS_VC_INTERFACE_HEADER,
   VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL,
@@ -98,11 +96,11 @@ typedef enum
   VIDEO_CS_VC_INTERFACE_PROCESSING_UNIT,
   VIDEO_CS_VC_INTERFACE_EXTENSION_UNIT,
   VIDEO_CS_VC_INTERFACE_ENCODING_UNIT,
+  VIDEO_CS_VC_INTERFACE_MAX,
 } video_cs_vc_interface_subtype_t;
 
 /* A.6 */
-typedef enum
-{
+typedef enum {
   VIDEO_CS_VS_INTERFACE_VS_DESCRIPTOR_UNDEF = 0x00,
   VIDEO_CS_VS_INTERFACE_INPUT_HEADER,
   VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER,
@@ -126,8 +124,7 @@ typedef enum
 } video_cs_vs_interface_subtype_t;
 
 /* A.8 */
-typedef enum
-{
+typedef enum {
   VIDEO_REQUEST_UNDEF = 0x00,
   VIDEO_REQUEST_SET_CUR,
   VIDEO_REQUEST_SET_CUR_ALL = 0x11,
@@ -147,16 +144,14 @@ typedef enum
 } video_control_request_t;
 
 /* A.9.1 */
-typedef enum
-{
+typedef enum {
   VIDEO_VC_CTL_UNDEF = 0x00,
   VIDEO_VC_CTL_VIDEO_POWER_MODE,
   VIDEO_VC_CTL_REQUEST_ERROR_CODE,
 } video_interface_control_selector_t;
 
 /* A.9.8 */
-typedef enum
-{
+typedef enum {
   VIDEO_VS_CTL_UNDEF = 0x00,
   VIDEO_VS_CTL_PROBE,
   VIDEO_VS_CTL_COMMIT,
@@ -170,8 +165,7 @@ typedef enum
 } video_interface_streaming_selector_t;
 
 /* B. Terminal Types */
-typedef enum
-{
+typedef enum {
   VIDEO_TT_VENDOR_SPECIFIC         = 0x0100,
   VIDEO_TT_STREAMING,
   VIDEO_ITT_VENDOR_SPECIFIC        = 0x0200,
@@ -254,20 +248,53 @@ typedef struct TU_ATTR_PACKED {
   };
 } tusb_desc_cs_video_stm_itf_hdr_t;
 
+typedef struct TU_ATTR_PACKED {
+  uint8_t bLength;
+  uint8_t bDescriptorType;
+  uint8_t bDescriptorSubType;
+  uint8_t bFormatIndex;
+  uint8_t bNumFrameDescriptors;
+  uint8_t guidFormat[16];
+  uint8_t bBitsPerPixel;
+  uint8_t bDefaultFrameIndex;
+  uint8_t bAspectRatioX;
+  uint8_t bAspectRatioY;
+  uint8_t bmInterlaceFlags;
+  uint8_t bCopyProtect;
+} tusb_desc_cs_video_fmt_uncompressed_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t bLength;
+  uint8_t bDescriptorType;
+  uint8_t bDescriptorSubType;
+  uint8_t bFrameIndex;
+  uint8_t bNumFrameDescriptors;
+  uint8_t guidFormat[16];
+  uint8_t bBitsPerPixel;
+  uint8_t bDefaultFrameIndex;
+  uint8_t bAspectRatioX;
+  uint8_t bAspectRatioY;
+  uint8_t bmInterlaceFlags;
+  uint8_t bCopyProtect;
+} tusb_desc_cs_video_frm_uncompressed_t;
+
 //--------------------------------------------------------------------+
 // Requests
 //--------------------------------------------------------------------+
 
 /* 4.3.1.1 */
 typedef struct TU_ATTR_PACKED {
-  struct TU_ATTR_PACKEDt {
-    uint16_t dwFrameInterval: 1;
-    uint16_t wKeyFrameRatel : 1;
-    uint16_t wPFrameRate    : 1;
-    uint16_t wCompQuality   : 1;
-    uint16_t wCompWindowSize: 1;
-    uint16_t                : 0;
-  } bmHint;
+  union {
+    uint8_t bmHint;
+    struct TU_ATTR_PACKED {
+      uint16_t dwFrameInterval: 1;
+      uint16_t wKeyFrameRatel : 1;
+      uint16_t wPFrameRate    : 1;
+      uint16_t wCompQuality   : 1;
+      uint16_t wCompWindowSize: 1;
+      uint16_t                : 0;
+    } Hint;
+  };
   uint8_t  bFormatIndex;
   uint8_t  bFrameIndex;
   uint32_t dwFrameInterval;
@@ -279,22 +306,27 @@ typedef struct TU_ATTR_PACKED {
   uint32_t dwMaxVideoFrameSize;
   uint32_t dwMaxPayloadTransferSize;
   uint32_t dwClockFrequency;
-  struct TU_ATTR_PACKED {
-    uint8_t FrameID   : 1;
-    uint8_t EndOfFrame: 1;
-    uint8_t EndOfSlice: 1;
-    uint8_t           : 0;
-  } bmFramingInfo;
+  union {
+    uint8_t bmFramingInfo;
+    struct TU_ATTR_PACKED {
+      uint8_t FrameID   : 1;
+      uint8_t EndOfFrame: 1;
+      uint8_t EndOfSlice: 1;
+      uint8_t           : 0;
+    } FramingInfo;
+  };
   uint8_t  bPreferedVersion;
   uint8_t  bMinVersion;
   uint8_t  bMaxVersion;
   uint8_t  bUsage;
-  uint8_t  bBitDepthLum;
+  uint8_t  bBitDepthLuma;
   uint8_t  bmSettings;
   uint8_t  bMaxNumberOfRefFramesPlus1;
   uint16_t bmRateControlModes;
   uint64_t bmLayoutPerStream;
-} video_probe_and_commit_t;
+} video_probe_and_commit_control_t;
+
+TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not correct");
 
 #define TUD_VIDEO_DESC_IAD_LEN                    8
 #define TUD_VIDEO_DESC_STD_VC_LEN                 9
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 001de388e..ee6f0b790 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -65,20 +65,35 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bEntityId;
 } tusb_desc_cs_video_entity_itf_t;
 
-typedef struct
-{
+
+typedef struct {
+  void const *beg;  /* The head of the first video control interface descriptor */
+  uint16_t length;  /* Byte length of the video control interface descriptors */
+  uint16_t offset;  /* offset bytes for the current video control interface descripter */
+  uint8_t  error_code;  /* error code set by previous transaction */
+  uint8_t  power_mode;  /* current power mode */
+} videod_control_interface_t;
+
+typedef struct {
+  tusb_desc_vs_itf_t const *descriptor; /* video streaming interface descriptor */
+  uint16_t    offset;     /* video streaming interface descriptor */
+  video_probe_and_commit_control_t settings;  /* last video streaming interface descriptor */
+  uint8_t error_code;
+} videod_streaming_interface_t;
+
+typedef struct {
   void const *beg;  /* The head of the first video control interface descriptor */
   uint16_t    len;  /* Byte length of the descriptors */
   uint16_t    ofs[3];  /* offsets for video control/streaming interface. 0:control 1:streaming 2:streaming */
+  uint8_t error_code[3];  /* error code for video control/streaming interface. 0:control 1:streaming 2:streaming */
   uint8_t power_mode;
-  uint8_t error_code;
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
 
   // Endpoint Transfer buffer
   //  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
   //  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE];
-  uint8_t ctl_buf;
+  uint8_t ctl_buf[64];
 
 } videod_interface_t;
 
@@ -91,6 +106,30 @@ CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
 
 static uint8_t const _cap_get     = 0x1u; /* support for GET */
 static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
+static video_probe_and_commit_control_t const def_stm_settings = {
+  .bmHint = 0,
+  .bFormatIndex = 1,
+  .bFrameIndex = 1,
+  .dwFrameInterval = (10000000/15),
+  .wKeyFrameRate = 1,
+  .wPFrameRate = 0,
+  .wCompQuality = 1, /* 1 to 10000 */
+  .wCompWindowSize = 1, /* Maybe it is match to GOP size */
+  .wDelay = 240, /* milliseconds */
+  .dwMaxVideoFrameSize = 128 * 96 * 12 / 8,
+  .dwMaxPayloadTransferSize = 256, /* Maybe it is the maximum packet size under this settings */
+  .dwClockFrequency = 27000000, /* same as MPEG-2 system time clock  */
+  .bmFramingInfo = 0,
+  .bPreferedVersion = 1,
+  .bMinVersion = 1,
+  .bMaxVersion = 1,
+  .bUsage = 0,
+  .bBitDepthLuma = 8,
+  .bmSettings = 0,
+  .bMaxNumberOfRefFramesPlus1 = 0,
+  .bmRateControlModes = 0,
+  .bmLayoutPerStream = 0
+};
 
 static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self)
 {
@@ -116,7 +155,6 @@ static tusb_desc_vs_itf_t const *_get_desc_vs(videod_interface_t const *self, un
   return (tusb_desc_vs_itf_t const*)(self->beg + *ofs);
 }
 
-
 /** Find the first descriptor with the specified descriptor type.
  *
  * @param[in] beg     The head of descriptor byte array.
@@ -146,7 +184,7 @@ static void const* _next_desc_itf(void const *beg, void const *end)
   void const *cur = beg;
   unsigned itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber;
   while ((cur < end) &&
-	 (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) {
+         (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) {
     cur = _find_desc(tu_desc_next(cur), end, TUSB_DESC_INTERFACE);
   }
   return cur;
@@ -186,9 +224,9 @@ static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, unsigned enti
   void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength;
   for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
     tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
-    if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL  == itf->bDescriptorSubtype ||
-         VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL == itf->bDescriptorSubtype) &&
-        itf->bEntityId == entityid) {
+    if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL  <= itf->bDescriptorSubtype
+         && itf->bDescriptorSubtype < VIDEO_CS_VC_INTERFACE_MAX)
+        && itf->bEntityId == entityid) {
       return itf;
     }
     cur = tu_desc_next(cur);
@@ -334,8 +372,8 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_
     tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[itf]);
     if (!vc) return VIDEO_UNKNOWN;
     if (tud_control_xfer(rhport, request,
-			 (void*)&vc->std.bAlternateSetting,
-			 sizeof(vc->std.bAlternateSetting)))
+                         (void*)&vc->std.bAlternateSetting,
+                         sizeof(vc->std.bAlternateSetting)))
       return VIDEO_NO_ERROR;
     return VIDEO_UNKNOWN;
   case TUSB_REQ_SET_INTERFACE:
@@ -359,10 +397,11 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
   case VIDEO_VC_CTL_VIDEO_POWER_MODE:
+    TU_LOG2("    Power Mode ");
     switch (request->bRequest) {
     case VIDEO_REQUEST_SET_CUR:
       if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Set Power Mode\r\n");
+        TU_LOG2("Set\r\n");
         TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
         if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
           return VIDEO_UNKNOWN;
@@ -371,39 +410,36 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
       }
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Get Power Mode\r\n");
-        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
-          return VIDEO_UNKNOWN;
-      }
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_LOG2("Get\r\n");
+      TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+      if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
+        return VIDEO_UNKNOWN;
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_INFO:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Get Info Power Mode\r\n");
-        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
-          return VIDEO_UNKNOWN;
-      }
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_LOG2("GetInfo\r\n");
+      TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+      if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
+        return VIDEO_UNKNOWN;
       return VIDEO_NO_ERROR;
     default: break;
     }
     break;
   case VIDEO_VC_CTL_REQUEST_ERROR_CODE:
+    TU_LOG2("  Error Code");
     switch (request->bRequest) {
     case VIDEO_REQUEST_GET_CUR:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Get Error Code\r\n");
-        if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(self->error_code)))
-          return VIDEO_UNKNOWN;
-      }
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_LOG2(" Get\r\n");
+      if (!tud_control_xfer(rhport, request, &self->error_code[0], sizeof(uint8_t)))
+        return VIDEO_UNKNOWN;
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_INFO:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("  Get Info Error Code\r\n");
-        if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)))
-          return VIDEO_UNKNOWN;
-      }
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_LOG2(" GetInfo\r\n");
+      if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)))
+        return VIDEO_UNKNOWN;
       return VIDEO_NO_ERROR;
     default: break;
     }
@@ -427,7 +463,7 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_requ
       return handle_video_ctl_cs_req(rhport, stage, request, itf);
     } else {
       if (!_find_desc_entity(_get_desc_vc(&_videod_itf[itf]), entity_id))
-	return VIDEO_INVALID_REQUEST;
+        return VIDEO_INVALID_REQUEST;
       return VIDEO_INVALID_REQUEST;
     }
   default:
@@ -446,8 +482,8 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_
     tusb_desc_vs_itf_t const *vs = _get_desc_vs(&_videod_itf[itf], itfnum);
     if (!vs) return VIDEO_UNKNOWN;
     if (tud_control_xfer(rhport, request,
-			 (void*)&vs->std.bAlternateSetting,
-			 sizeof(vs->std.bAlternateSetting)))
+                         (void*)&vs->std.bAlternateSetting,
+                         sizeof(vs->std.bAlternateSetting)))
       return VIDEO_NO_ERROR;
     return VIDEO_UNKNOWN;
   case TUSB_REQ_SET_INTERFACE:
@@ -467,55 +503,113 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_
 
 static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
-  //  videod_interface_t *self = &_videod_itf[itf];
-  (void)rhport; (void)stage; (void)itf;
+  (void)rhport;
+  videod_interface_t *self = &_videod_itf[itf];
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
+  case VIDEO_VS_CTL_STREAM_ERROR_CODE:
+    TU_LOG2("    Error Code ");
+    switch (request->bRequest) {
+    case VIDEO_REQUEST_GET_CUR:
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_LOG2("Get\r\n");
+      /* TODO */
+      if (!tud_control_xfer(rhport, request, &self->error_code[0], sizeof(uint8_t)))
+        return VIDEO_UNKNOWN;
+      return VIDEO_NO_ERROR;
+    case VIDEO_REQUEST_GET_INFO:
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_LOG2("GetInfo\r\n");
+      if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)))
+        return VIDEO_UNKNOWN;
+      return VIDEO_NO_ERROR;
+    default: break;
+    }
+    break;
   case VIDEO_VS_CTL_PROBE:
-    TU_LOG2("  Probe ");
     switch (request->bRequest) {
     case VIDEO_REQUEST_SET_CUR:
-      TU_LOG2("Set\r\n");
-      return VIDEO_UNKNOWN;
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN);
+        if (!tud_control_xfer(rhport, request, self->ctl_buf, sizeof(video_probe_and_commit_control_t)))
+          return VIDEO_UNKNOWN;
+      } else if (stage == CONTROL_STAGE_ACK) {
+        if (tud_video_probe_set_cb)
+          return tud_video_probe_set_cb(itf, (video_probe_and_commit_control_t const*)self->ctl_buf);
+      }
+      return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
-      TU_LOG2("Get\r\n");
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
+      if (tud_control_xfer(rhport, request, (void*)&def_stm_settings,
+                           sizeof(video_probe_and_commit_control_t)))
+        return VIDEO_NO_ERROR;
       return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_MIN:
-      TU_LOG2("Get Min\r\n");
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
+      if (tud_control_xfer(rhport, request, (void*)&def_stm_settings,
+                           sizeof(video_probe_and_commit_control_t)))
+        return VIDEO_NO_ERROR;
       return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_MAX:
-      TU_LOG2("Get Man\r\n");
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
+      if (tud_control_xfer(rhport, request, (void*)&def_stm_settings,
+                           sizeof(video_probe_and_commit_control_t)))
+        return VIDEO_NO_ERROR;
       return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_RES:
-      TU_LOG2("Get Res\r\n");
       return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_DEF:
-      TU_LOG2("Get Def\r\n");
       return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_LEN:
-      TU_LOG2("Get Len\r\n");
       return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_INFO:
-      TU_LOG2("Get Info\r\n");
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+      if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
+        return VIDEO_NO_ERROR;
       return VIDEO_UNKNOWN;
     default: break;
     }
     break;
   case VIDEO_VS_CTL_COMMIT:
-    TU_LOG2("  Commit ");
     switch (request->bRequest) {
     case VIDEO_REQUEST_SET_CUR:
-      TU_LOG2("Set\r\n");
-      return VIDEO_UNKNOWN;
+      if (stage == CONTROL_STAGE_SETUP) {
+        TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN);
+        if (!tud_control_xfer(rhport, request, self->ctl_buf, sizeof(video_probe_and_commit_control_t)))
+          return VIDEO_UNKNOWN;
+      } else if (stage == CONTROL_STAGE_ACK) {
+        if (tud_video_commit_set_cb)
+          return tud_video_commit_set_cb(itf, (video_probe_and_commit_control_t const*)self->ctl_buf);
+      }
+      return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
-      TU_LOG2("Get\r\n");
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
+      if (tud_control_xfer(rhport, request, (void*)&def_stm_settings,
+                           sizeof(video_probe_and_commit_control_t)))
+        return VIDEO_NO_ERROR;
       return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_INFO:
-      TU_LOG2("Get Info\r\n");
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+      if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
+        return VIDEO_NO_ERROR;
       return VIDEO_UNKNOWN;
     default: break;
     }
     break;
+  case VIDEO_VS_CTL_STILL_PROBE:
+  case VIDEO_VS_CTL_STILL_COMMIT:
+  case VIDEO_VS_CTL_STILL_IMAGE_TRIGGER:
+  case VIDEO_VS_CTL_GENERATE_KEY_FRAME:
+  case VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT:
+  case VIDEO_VS_CTL_SYNCH_DELAY_CONTROL:
+    /* TODO */
+    break;
   default: break;
   }
   /* Unknown/Unsupported request */
@@ -587,8 +681,8 @@ void videod_reset(uint8_t rhport)
 uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
 {
   TU_VERIFY((TUSB_CLASS_VIDEO           == itf_desc->bInterfaceClass) &&
-	    (VIDEO_SUBCLASS_CONTROL     == itf_desc->bInterfaceSubClass) &&
-	    (VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bInterfaceProtocol), 0);
+            (VIDEO_SUBCLASS_CONTROL     == itf_desc->bInterfaceSubClass) &&
+            (VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bInterfaceProtocol), 0);
 
   /* Find available interface */
   videod_interface_t *self = NULL;
@@ -607,7 +701,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   if (!_open_vc_itf(rhport, self, 0)) return 0;
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
   unsigned bInCollection       = vc->ctl.bInCollection;
-  /* Update end */
+  /* Find the end of the video interface descriptor */
   void const *cur = _next_desc_itf(itf_desc, end);
   for (unsigned i = 0; i < bInCollection; ++i) {
     cur = _next_desc_itf(cur, end);
@@ -623,6 +717,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
 {
   int err;
   int (*handle_video_req)(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) = NULL;
+  uint8_t *error_code;
   if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) {
     return false;
   }
@@ -634,6 +729,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
     vc = _get_desc_vc(&_videod_itf[itf]);
     if (itfnum == vc->std.bInterfaceNumber) {
       handle_video_req = handle_video_ctl_req;
+      error_code = &_videod_itf[itf].error_code[0];
       break;
     }
     int i;
@@ -641,13 +737,14 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
     for (i = 0; i < bInCollection && itfnum != vc->ctl.baInterfaceNr[i]; ++i) ;
     if (i < bInCollection) {
       handle_video_req = handle_video_stm_req;
+      error_code = &_videod_itf[itf].error_code[1 + i];
       break;
     }
   }
   if (itf == CFG_TUD_VIDEO) return false;
 
   err = handle_video_req(rhport, stage, request, itf);
-  _videod_itf[itf].error_code = (uint8_t)err;
+  *error_code = (uint8_t)err;
   if (err) return false;
   return true;
 }
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index 95d352524..b4bdfc699 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -48,6 +48,12 @@ TU_ATTR_WEAK bool tud_video_get_cur_cb(uint8_t rhport, tusb_control_request_t co
 
 /* @return video_error_code_t */
 TU_ATTR_WEAK int tud_video_power_mode_cb(unsigned itf, uint8_t power_mod);
+
+/* @return video_error_code_t */
+TU_ATTR_WEAK int tud_video_probe_set_cb(unsigned itf, video_probe_and_commit_control_t const *settings);
+
+/* @return video_error_code_t */
+TU_ATTR_WEAK int tud_video_commit_set_cb(unsigned itf, video_probe_and_commit_control_t const *settings);
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+

From 3cb4bb391d814d88662581f47b4dc13097d7c69e Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 20 Sep 2021 14:55:56 +0900
Subject: [PATCH 0515/2085] Separate a handling resource into controller and
 streaming

---
 examples/device/video_capture/src/main.c      |  41 ++
 .../device/video_capture/src/tusb_config.h    |   4 +
 .../video_capture/src/usb_descriptors.c       |   2 +-
 src/class/video/video.h                       |  17 +
 src/class/video/video_device.c                | 359 +++++++++++-------
 src/class/video/video_device.h                |  22 +-
 6 files changed, 303 insertions(+), 142 deletions(-)

diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 098cd2f8d..1921da4bf 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -30,10 +30,14 @@
 #include "bsp/board.h"
 #include "tusb.h"
 
+#include "images.h"
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
 
+#define FRAME_WIDTH   128
+#define FRAME_HEIGHT  96
+
 /* Blink pattern
  * - 250 ms  : device not mounted
  * - 1000 ms : device mounted
@@ -102,8 +106,45 @@ void tud_resume_cb(void)
 //--------------------------------------------------------------------+
 // USB Video
 //--------------------------------------------------------------------+
+static unsigned char const *frames[] = {
+  black_128x96_yuv, white_128x96_yuv
+};
+uint8_t current_frame = 0;
+
 void video_task(void)
 {
+  static unsigned start_ms = 0;
+  static unsigned interval_ms = 66;
+  static unsigned frame_num = 0;
+  static unsigned already_sent = 0;
+
+  if (!tud_video_n_streaming(0)) return;
+
+  if (!already_sent) {
+    tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
+    current_frame ^= 1;
+    already_sent = 1;
+  }
+
+  unsigned cur = board_millis();
+  if (cur - start_ms < interval_ms) return; // not enough time
+  start_ms += interval_ms;
+
+  /* flip buffer */
+  ++frame_num;
+  if (frame_num % 3) {
+    interval_ms = 66;
+  } else {
+    interval_ms = 67;
+  }
+}
+
+int tud_video_frame_xfer_complete_cb(void)
+{
+  /* prepare tx */
+  tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
+  current_frame ^= 1;
+  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index ae2387357..3958b85b6 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -90,6 +90,10 @@
 #define CFG_TUD_ENDPOINT0_SIZE    64
 #endif
 
+#define CFG_TUD_VIDEO_EP_BUFSIZE  256
+
+#define CFG_TUD_VIDEO_STREAMING  1
+
 //------------- CLASS -------------//
 #define CFG_TUD_CDC              0
 #define CFG_TUD_MSC              0
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index d3544cc63..096ac4373 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -104,7 +104,7 @@ uint8_t const desc_fs_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
   // IAD for Video Control
-  TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 15, 256)
+  TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 10, 256)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 17e1658b5..444433e86 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -192,6 +192,23 @@ typedef struct TU_ATTR_PACKED {
   uint8_t  baInterfaceNr[];
 } tusb_desc_cs_video_ctl_itf_hdr_t;
 
+/* 2.4.3.3 */
+typedef struct TU_ATTR_PACKED {
+  uint8_t bHeaderLength;
+  union {
+    uint8_t bmHeaderInfo;
+    struct {
+      uint8_t FrameID:              1;
+      uint8_t EndOfFrame:           1;
+      uint8_t PresentationTime:     1;
+      uint8_t SourceClockReference: 1;
+      uint8_t StillImage:           1;
+      uint8_t Error:                1;
+      uint8_t EndOfHeader:          1;
+    };
+  };
+} tusb_video_payload_header_t;
+
 /* 3.9.2.1 */
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index ee6f0b790..dc6cf376c 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -66,7 +66,7 @@ typedef struct TU_ATTR_PACKED {
 } tusb_desc_cs_video_entity_itf_t;
 
 
-typedef struct {
+typedef struct TU_ATTR_PACKED {
   void const *beg;  /* The head of the first video control interface descriptor */
   uint16_t length;  /* Byte length of the video control interface descriptors */
   uint16_t offset;  /* offset bytes for the current video control interface descripter */
@@ -74,18 +74,29 @@ typedef struct {
   uint8_t  power_mode;  /* current power mode */
 } videod_control_interface_t;
 
-typedef struct {
-  tusb_desc_vs_itf_t const *descriptor; /* video streaming interface descriptor */
-  uint16_t    offset;     /* video streaming interface descriptor */
-  video_probe_and_commit_control_t settings;  /* last video streaming interface descriptor */
-  uint8_t error_code;
+typedef struct TU_ATTR_PACKED {
+  uint8_t index_vc;  /* index of video control interface */
+  uint8_t error_code;/* error code for video control/streaming interface. 0:control 1:streaming 2:streaming */
+  struct {
+    uint16_t beg;    /* Offset of the beggining of video streaming interface descriptor */
+    uint16_t end;    /* Offset of the end of video streaming interface descriptor */
+    uint16_t cur;    /* Offset of the current settings */
+    uint16_t ep[2];  /* Offset of endpoint descriptors */
+  } desc;
+
+  uint8_t  *buffer; /* frame buffer. assume linear buffer. no support for stride access */
+  uint32_t bufsize; /* frame buffer */
+  uint32_t offset;  /* offset for the next payload transfer */
+  uint32_t max_payload_transfer_size;
+  uint8_t  ep_buf[CFG_TUD_VIDEO_EP_BUFSIZE];
 } videod_streaming_interface_t;
 
-typedef struct {
+typedef struct TU_ATTR_PACKED {
   void const *beg;  /* The head of the first video control interface descriptor */
   uint16_t    len;  /* Byte length of the descriptors */
-  uint16_t    ofs[3];  /* offsets for video control/streaming interface. 0:control 1:streaming 2:streaming */
-  uint8_t error_code[3];  /* error code for video control/streaming interface. 0:control 1:streaming 2:streaming */
+  uint16_t    cur;  /* offset for current video control interface */
+  uint8_t     stm[CFG_TUD_VIDEO_STREAMING]; /* Indices of streaming interface */
+  uint8_t error_code;  /* error code for video control/streaming interface. */
   uint8_t power_mode;
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
@@ -103,6 +114,7 @@ typedef struct {
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
+CFG_TUSB_MEM_SECTION static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
 
 static uint8_t const _cap_get     = 0x1u; /* support for GET */
 static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
@@ -110,7 +122,7 @@ static video_probe_and_commit_control_t const def_stm_settings = {
   .bmHint = 0,
   .bFormatIndex = 1,
   .bFrameIndex = 1,
-  .dwFrameInterval = (10000000/15),
+  .dwFrameInterval = (10000000/10),
   .wKeyFrameRate = 1,
   .wPFrameRate = 0,
   .wCompQuality = 1, /* 1 to 10000 */
@@ -131,28 +143,26 @@ static video_probe_and_commit_control_t const def_stm_settings = {
   .bmLayoutPerStream = 0
 };
 
+static inline uint8_t _desc_itfnum(void const *desc)
+{
+  return ((uint8_t const*)desc)[2];
+}
+
+static inline uint8_t _desc_ep_addr(void const *desc)
+{
+  return ((uint8_t const*)desc)[2];
+}
+
 static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self)
 {
-  return (tusb_desc_vc_itf_t const *)(self->beg + self->ofs[0]);
+  return (tusb_desc_vc_itf_t const *)(self->beg + self->cur);
 }
 
-static uint16_t* _get_desc_ofs(videod_interface_t *self, unsigned itfnum)
+static tusb_desc_vs_itf_t const *_get_desc_vs(videod_streaming_interface_t const *self)
 {
-  void const *beg = self->beg;
-  uint16_t   *ofs = self->ofs;
-  for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(self->ofs[0]); ++i) {
-    if (!ofs[i]) continue;
-    tusb_desc_interface_t const* itf = (tusb_desc_interface_t const*)(beg + ofs[i]);
-    if (itfnum == itf->bInterfaceNumber) return &ofs[i];
-  }
-  return NULL;
-}
-
-static tusb_desc_vs_itf_t const *_get_desc_vs(videod_interface_t const *self, unsigned itfnum)
-{
-  uint16_t const *ofs = _get_desc_ofs((videod_interface_t*)self, itfnum);
-  if (!ofs) return NULL;
-  return (tusb_desc_vs_itf_t const*)(self->beg + *ofs);
+  if (!self->desc.cur) return NULL;
+  void const *desc = _videod_itf[self->index_vc].beg;
+  return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur);
 }
 
 /** Find the first descriptor with the specified descriptor type.
@@ -211,6 +221,23 @@ static void const* _find_desc_itf(void const *beg, void const *end, unsigned itf
   return end;
 }
 
+/** Find the first endpoint descriptor in front of the next interface descriptor.
+ *
+ * @param[in] beg     The head of descriptor byte array.
+ * @param[in] end     The tail of descriptor byte array.
+ *
+ * @return The pointer for endpoint descriptor.
+ * @retval end   did not found endpoint descriptor */
+static void const* _find_desc_ep(void const *beg, void const *end)
+{
+  for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) {
+    uint8_t desc_type = tu_desc_type(cur);
+    if (TUSB_DESC_ENDPOINT == desc_type) return cur;
+    if (TUSB_DESC_INTERFACE == desc_type) break;
+  }
+  return end;
+}
+
 /** Find the first entity descriptor with the specified entity ID in the video control interface descriptor.
  *
  * @param[in] vc        The video control interface descriptor.
@@ -252,7 +279,7 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
     tusb_desc_endpoint_t const *notif = (tusb_desc_endpoint_t const *)cur;
     usbd_edpt_close(rhport, notif->bEndpointAddress);
   }
-  self->ofs[0] = 0;
+  self->cur = 0;
   return true;
 }
 
@@ -266,15 +293,14 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altn
   void const *beg = self->beg;
   void const *end = beg + self->len;
   /* The first descriptor is a video control interface descriptor. */
-  unsigned itfnum = ((tusb_desc_interface_t const *)beg)->bInterfaceNumber;
-  void const *cur = _find_desc_itf(beg, end, itfnum, altnum);
+  void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
   TU_LOG2("    cur %ld\r\n", cur - beg);
   TU_VERIFY(cur < end);
 
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
   TU_LOG2("    bInCollection %d\r\n", vc->ctl.bInCollection);
   /* Support for up to 2 streaming interfaces only. */
-  TU_ASSERT(vc->ctl.bInCollection < 3);
+  TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING);
 
   /* Update to point the end of the video control interface descriptor. */
   end  = cur + vc->std.bLength + vc->ctl.wTotalLength;
@@ -292,76 +318,88 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altn
     /* Open the notification endpoint */
     TU_ASSERT(usbd_edpt_open(rhport, notif));
   }
-  self->ofs[0] = (void const*)vc - beg;
+  self->cur = (void const*)vc - beg;
   return true;
 }
 
 /** Set the specified alternate setting to own video control interface.
  *
  * @param[in,out] self     The context.
- * @param[in]     itfnum   The target interface number. */
-static bool _close_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum)
-{
-  uint16_t *ofs = _get_desc_ofs(self, itfnum);
-  if (!ofs) return true;
-  tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)(self->beg + *ofs);
-  /* The next of the video streaming interface header descriptor. */
-  void const *cur = (void const*)vs + vs->std.bLength + vs->stm.bLength;
-  /* The end of the video streaming interface descriptor. */
-  void const *end = (void const*)vs + vs->std.bLength + vs->stm.wTotalLength;
-  for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) {
-    cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
-    TU_ASSERT(cur < end);
-    tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
-    usbd_edpt_close(rhport, ep->bEndpointAddress);
-    cur += tu_desc_len(cur);
-  }
-  *ofs = 0;
-  return true;
-}
-
-/** Set the specified alternate setting to own video control interface.
- *
- * @param[in,out] self     The context.
- * @param[in]     itfnum   The target interface number.
  * @param[in]     altnum   The target alternate setting number. */
-static bool _open_vs_itf(uint8_t rhport, videod_interface_t *self, unsigned itfnum, unsigned altnum)
+static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, unsigned altnum)
 {
-  TU_LOG2("    open VS %d,%d\r\n", itfnum, altnum);
-  uint16_t   *ofs = NULL;
-  for (unsigned i = 1; i < sizeof(self->ofs)/sizeof(self->ofs[0]); ++i) {
-    if (!self->ofs[i]) {
-      ofs = &self->ofs[i];
-      break;
-    }
+  unsigned i;
+  TU_LOG1("    reopen VS %d\r\n", altnum);
+  void const *desc = _videod_itf[stm->index_vc].beg;
+
+  /* Close endpoints of previous settings. */
+  for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) {
+    unsigned ofs_ep = stm->desc.ep[i];
+    if (!ofs_ep) break;
+    unsigned ep_adr = _desc_ep_addr(desc + ofs_ep);
+    usbd_edpt_close(rhport, ep_adr);
+    stm->desc.ep[i] = 0;
+    TU_LOG1("    close EP%02x\n", ep_adr);
   }
-  if (!ofs) return false;
 
-  tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
-  void const *end = self->beg + self->len;
-  /* Set the end of the video control interface descriptor. */
-  void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.wTotalLength;
-
-  cur = _find_desc_itf(cur, end, itfnum, altnum);
+  /* Find a alternate interface */
+  void const *beg = desc + stm->desc.beg;
+  void const *end = desc + stm->desc.end;
+  void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
   TU_VERIFY(cur < end);
-  tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const*)cur;
-  /* Support for up to 2 endpoint only. */
-  TU_ASSERT(vs->std.bNumEndpoints < 3);
-  /* Update to point the end of the video control interface descriptor. */
-  end  = cur + vs->std.bLength + vs->stm.wTotalLength;
-  /* Advance to the next descriptor after the class-specific VS interface header descriptor. */
-  cur += vs->std.bLength + vs->stm.bLength;
-  for (unsigned i = 0; i < vs->std.bNumEndpoints; ++i) {
-    cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
-    TU_VERIFY(cur < end);
-    tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const *)cur;
-    TU_ASSERT(usbd_edpt_open(rhport, ep));
-    cur += tu_desc_len(cur);
+  unsigned numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints;
+  TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep));
+  stm->desc.cur = cur - desc; /* Save the offset of the new settings */
+  /* Open endpoints of the new settings. */
+  for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) {
+    cur = _find_desc_ep(cur, end);
+    TU_ASSERT(cur < end);
+    TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *)cur));
+    stm->desc.ep[i] = cur - desc;
+    stm->max_payload_transfer_size = CFG_TUD_VIDEO_EP_BUFSIZE;
+    TU_LOG1("    open EP%02x\n", _desc_ep_addr(cur));
   }
-  *ofs = (void const*)vs - self->beg;
   return true;
 }
 
+static int _payload_xfer_in(uint8_t rhport, uint8_t itf)
+{
+  videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
+  void const *desc = _videod_itf[stm->index_vc].beg;
+  unsigned ep_addr = 0;
+  for (unsigned i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
+    unsigned ofs_ep = stm->desc.ep[i];
+    if (!ofs_ep) continue;
+    ep_addr = _desc_ep_addr(desc + ofs_ep);
+    if (tu_edpt_dir(ep_addr))
+      break;
+  }
+  TU_ASSERT(ep_addr, 0);
+  /* Claim the endpoint */
+  TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0);
+
+  /* prepare a payload */
+  unsigned mps = stm->max_payload_transfer_size;
+  uint32_t remaining = stm->bufsize - stm->offset;
+  uint32_t data_len = remaining < (mps - 2) ? remaining: (mps - 2);
+  stm->ep_buf[0] = 1;
+  stm->ep_buf[1] = 0;
+  memcpy(&stm->ep_buf[2], stm->buffer + stm->offset, data_len);
+  stm->offset += data_len;
+  remaining -= data_len;
+  TU_LOG2(" %d\n", data_len, remaining);
+  TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, 2 + data_len), 0 );
+
+  if (!remaining) {
+    stm->buffer  = NULL;
+    stm->bufsize = 0;
+    stm->offset  = 0;
+    if (tud_video_frame_xfer_complete_cb)
+      tud_video_frame_xfer_complete_cb();
+  }
+  return data_len;
+}
+
 /** Handle a standard request to the video control interface. */
 static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
@@ -432,7 +470,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
     case VIDEO_REQUEST_GET_CUR:
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
       TU_LOG2(" Get\r\n");
-      if (!tud_control_xfer(rhport, request, &self->error_code[0], sizeof(uint8_t)))
+      if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)))
         return VIDEO_UNKNOWN;
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_INFO:
@@ -473,13 +511,12 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_requ
 
 static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
-  unsigned itfnum;
+  videod_streaming_interface_t *self = &_videod_streaming_itf[itf];
   switch (request->bRequest) {
   case TUSB_REQ_GET_INTERFACE:
     if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
     TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
-    itfnum = tu_u16_low(request->wIndex);
-    tusb_desc_vs_itf_t const *vs = _get_desc_vs(&_videod_itf[itf], itfnum);
+    tusb_desc_vs_itf_t const *vs = _get_desc_vs(self);
     if (!vs) return VIDEO_UNKNOWN;
     if (tud_control_xfer(rhport, request,
                          (void*)&vs->std.bAlternateSetting,
@@ -488,10 +525,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_
     return VIDEO_UNKNOWN;
   case TUSB_REQ_SET_INTERFACE:
     if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-    itfnum = tu_u16_low(request->wIndex);
-    if (!_close_vs_itf(rhport, &_videod_itf[itf], itfnum))
-      return VIDEO_UNKNOWN;
-    if (!_open_vs_itf(rhport, &_videod_itf[itf], itfnum, request->wValue))
+    if (!_open_vs_itf(rhport, self, request->wValue))
       return VIDEO_UNKNOWN;
     tud_control_status(rhport, request);
     return VIDEO_NO_ERROR;
@@ -504,7 +538,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_
 static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
 {
   (void)rhport;
-  videod_interface_t *self = &_videod_itf[itf];
+  videod_streaming_interface_t *self = &_videod_streaming_itf[itf];
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
   case VIDEO_VS_CTL_STREAM_ERROR_CODE:
@@ -512,9 +546,8 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
     switch (request->bRequest) {
     case VIDEO_REQUEST_GET_CUR:
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_LOG2("Get\r\n");
       /* TODO */
-      if (!tud_control_xfer(rhport, request, &self->error_code[0], sizeof(uint8_t)))
+      if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)))
         return VIDEO_UNKNOWN;
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_INFO:
@@ -531,11 +564,11 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
     case VIDEO_REQUEST_SET_CUR:
       if (stage == CONTROL_STAGE_SETUP) {
         TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, self->ctl_buf, sizeof(video_probe_and_commit_control_t)))
+        if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
           return VIDEO_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
         if (tud_video_probe_set_cb)
-          return tud_video_probe_set_cb(itf, (video_probe_and_commit_control_t const*)self->ctl_buf);
+          return tud_video_probe_set_cb(itf, (video_probe_and_commit_control_t const*)self->ep_buf);
       }
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
@@ -579,11 +612,11 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
     case VIDEO_REQUEST_SET_CUR:
       if (stage == CONTROL_STAGE_SETUP) {
         TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, self->ctl_buf, sizeof(video_probe_and_commit_control_t)))
+        if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
           return VIDEO_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
         if (tud_video_commit_set_cb)
-          return tud_video_commit_set_cb(itf, (video_probe_and_commit_control_t const*)self->ctl_buf);
+          return tud_video_commit_set_cb(itf, (video_probe_and_commit_control_t const*)self->ep_buf);
       }
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
@@ -635,6 +668,15 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_requ
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
+/* itf     streaming interface number */
+bool tud_video_n_streaming(uint8_t itf)
+{
+  videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
+  if (stm->desc.ep[0])
+    return true;
+  return false;
+}
+
 bool tud_video_n_connected(uint8_t itf)
 {
   (void)itf;
@@ -642,6 +684,21 @@ bool tud_video_n_connected(uint8_t itf)
   return tud_ready();
 }
 
+int tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize)
+{
+  (void)pts;
+
+  if (!tud_video_n_streaming(itf))
+    return false;
+
+  videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
+  stm->buffer  = (uint8_t*)buffer;
+  stm->bufsize = bufsize;
+  TU_LOG1(" xfer %d\n", bufsize);
+  _payload_xfer_in(0, itf);
+  return 0;
+}
+
 //--------------------------------------------------------------------+
 // READ API
 //--------------------------------------------------------------------+
@@ -686,25 +743,40 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 
   /* Find available interface */
   videod_interface_t *self = NULL;
-  for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) {
-    if (!_videod_itf[i].beg) {
-      self = &_videod_itf[i];
-      break;
-    }
+  unsigned itf;
+  for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
+    if (_videod_itf[itf].beg)
+      continue;
+    self = &_videod_itf[itf];
+    break;
   }
-  TU_ASSERT(self, 0);
+  TU_ASSERT(itf < CFG_TUD_VIDEO, 0);
 
   void const *end = (void const*)itf_desc + max_len;
   self->beg = itf_desc;
   self->len = max_len;
   /*------------- Video Control Interface -------------*/
-  if (!_open_vc_itf(rhport, self, 0)) return 0;
+  if (!_open_vc_itf(rhport, self, 0))
+    return 0;
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
   unsigned bInCollection       = vc->ctl.bInCollection;
   /* Find the end of the video interface descriptor */
   void const *cur = _next_desc_itf(itf_desc, end);
   for (unsigned i = 0; i < bInCollection; ++i) {
+    videod_streaming_interface_t *stm = NULL;
+    /* find free streaming interface handle */
+    for (unsigned j = 0; j < TU_ARRAY_SIZE(_videod_streaming_itf); ++j) {
+      if (_videod_streaming_itf[i].desc.beg)
+        continue;
+      stm = &_videod_streaming_itf[i];
+      self->stm[i] = j;
+      break;
+    }
+    TU_ASSERT(stm, 0);
+    stm->index_vc = itf;
+    stm->desc.beg = (uintptr_t)cur - (uintptr_t)itf_desc;
     cur = _next_desc_itf(cur, end);
+    stm->desc.end = (uintptr_t)cur - (uintptr_t)itf_desc;
   }
   self->len = (uintptr_t)cur - (uintptr_t)itf_desc;
   return (uintptr_t)cur - (uintptr_t)itf_desc;
@@ -716,43 +788,64 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
 {
   int err;
-  int (*handle_video_req)(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf) = NULL;
-  uint8_t *error_code;
   if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) {
     return false;
   }
   unsigned itfnum = tu_u16_low(request->wIndex);
-  /* Identify which interface to use */
-  int itf;
-  tusb_desc_vc_itf_t const *vc = NULL;
-  for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
-    vc = _get_desc_vc(&_videod_itf[itf]);
-    if (itfnum == vc->std.bInterfaceNumber) {
-      handle_video_req = handle_video_ctl_req;
-      error_code = &_videod_itf[itf].error_code[0];
-      break;
-    }
-    int i;
-    int bInCollection = vc->ctl.bInCollection;
-    for (i = 0; i < bInCollection && itfnum != vc->ctl.baInterfaceNr[i]; ++i) ;
-    if (i < bInCollection) {
-      handle_video_req = handle_video_stm_req;
-      error_code = &_videod_itf[itf].error_code[1 + i];
+
+  /* Identify which control interface to use */
+  int itf = -1;
+  for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) {
+    void const *desc = _videod_itf[i].beg;
+    if (!desc) break;
+    if (itfnum == _desc_itfnum(desc)) {
+      itf = i;
       break;
     }
   }
-  if (itf == CFG_TUD_VIDEO) return false;
+  if (itf >= 0) {
+    err = handle_video_ctl_req(rhport, stage, request, itf);
+    _videod_itf[itf].error_code = (uint8_t)err;
+    if (err) return false;
+    return true;
+  }
 
-  err = handle_video_req(rhport, stage, request, itf);
-  *error_code = (uint8_t)err;
-  if (err) return false;
-  return true;
+  /* Identify which streaming interface to use */
+  for (unsigned i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
+    videod_streaming_interface_t *stm = &_videod_streaming_itf[i];
+    if (!stm->desc.beg) return false;
+    void const *desc = _videod_itf[stm->index_vc].beg;
+    if (itfnum == _desc_itfnum(desc + stm->desc.beg)) {
+      itf = i;
+      break;
+    }
+  }
+  if (itf >= 0) {
+    err = handle_video_stm_req(rhport, stage, request, itf);
+    _videod_streaming_itf[itf].error_code = (uint8_t)err;
+    if (err) return false;
+    return true;
+  }
+  return false;
 }
 
 bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
 {
-  (void)rhport; (void)ep_addr; (void)result; (void)xferred_bytes;
-  return false;
+  (void)rhport; (void)result; (void)xferred_bytes;
+
+  /* find streaming handle */
+  unsigned i;
+  for (i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
+    videod_streaming_interface_t *stm = &_videod_streaming_itf[i];
+    unsigned const ep_ofs = stm->desc.ep[0];
+    if (!ep_ofs) continue;
+    void const *desc = _videod_itf[stm->index_vc].beg;
+    if (ep_addr == _desc_ep_addr(desc + ep_ofs))
+      break;
+  }
+  TU_ASSERT(i < CFG_TUD_VIDEO_STREAMING);
+  _payload_xfer_in(rhport, i);
+  return true;
 }
 
 #endif
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index b4bdfc699..a1b13b9af 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -35,18 +35,24 @@
 extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Application API (Multiple Ports)
+// CFG_TUD_VIDEO > 1
+//--------------------------------------------------------------------+
+bool tud_video_n_streaming(uint8_t itf);
+
+
+int tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize);
+
+/*------------- Optional callbacks -------------*/
+TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(void);
+
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
 //--------------------------------------------------------------------+
 
-// Invoked when GET_INFO request received
-TU_ATTR_WEAK bool tud_video_get_info_cb(uint8_t rhport, tusb_control_request_t const *request, uint8_t const *itf_desc);
-// Invoked when GET_INFO request received
-TU_ATTR_WEAK bool tud_video_set_cur_cb(uint8_t rhport, tusb_control_request_t const *request);
-// Invoked when GET_CUR request received
-TU_ATTR_WEAK bool tud_video_get_cur_cb(uint8_t rhport, tusb_control_request_t const *request);
-
-/* @return video_error_code_t */
+/* Invoked when SET POWER_MODE request received to 
+ * @return video_error_code_t */
 TU_ATTR_WEAK int tud_video_power_mode_cb(unsigned itf, uint8_t power_mod);
 
 /* @return video_error_code_t */

From cd3f6eac2f31ccd21aae7fd9a323fe416c77409b Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 25 Sep 2021 13:08:00 +0900
Subject: [PATCH 0516/2085] Fix streaming payload handling

---
 src/class/video/video.h        |  1 +
 src/class/video/video_device.c | 50 ++++++++++++++++++++++------------
 2 files changed, 34 insertions(+), 17 deletions(-)

diff --git a/src/class/video/video.h b/src/class/video/video.h
index 444433e86..c62706e5b 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -202,6 +202,7 @@ typedef struct TU_ATTR_PACKED {
       uint8_t EndOfFrame:           1;
       uint8_t PresentationTime:     1;
       uint8_t SourceClockReference: 1;
+      uint8_t PayloadSpecific:      1;
       uint8_t StillImage:           1;
       uint8_t Error:                1;
       uint8_t EndOfHeader:          1;
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index dc6cf376c..acec7a992 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -65,7 +65,6 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bEntityId;
 } tusb_desc_cs_video_entity_itf_t;
 
-
 typedef struct TU_ATTR_PACKED {
   void const *beg;  /* The head of the first video control interface descriptor */
   uint16_t length;  /* Byte length of the video control interface descriptors */
@@ -356,9 +355,14 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, unsi
     TU_ASSERT(cur < end);
     TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *)cur));
     stm->desc.ep[i] = cur - desc;
-    stm->max_payload_transfer_size = CFG_TUD_VIDEO_EP_BUFSIZE;
+    stm->max_payload_transfer_size = def_stm_settings.dwMaxPayloadTransferSize;
     TU_LOG1("    open EP%02x\n", _desc_ep_addr(cur));
   }
+  /* initialize payload header */
+  tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
+  hdr->bHeaderLength = sizeof(*hdr);
+  hdr->bmHeaderInfo  = 0;
+
   return true;
 }
 
@@ -379,24 +383,22 @@ static int _payload_xfer_in(uint8_t rhport, uint8_t itf)
   TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0);
 
   /* prepare a payload */
-  unsigned mps = stm->max_payload_transfer_size;
   uint32_t remaining = stm->bufsize - stm->offset;
-  uint32_t data_len = remaining < (mps - 2) ? remaining: (mps - 2);
-  stm->ep_buf[0] = 1;
-  stm->ep_buf[1] = 0;
-  memcpy(&stm->ep_buf[2], stm->buffer + stm->offset, data_len);
+  unsigned hdr_len   = stm->ep_buf[0];
+  unsigned pkt_len   = stm->max_payload_transfer_size;
+  if (hdr_len + remaining < pkt_len) {
+    pkt_len = hdr_len + remaining;
+  }
+  uint32_t data_len = pkt_len - hdr_len;
+  memcpy(&stm->ep_buf[hdr_len], stm->buffer + stm->offset, data_len);
   stm->offset += data_len;
   remaining -= data_len;
-  TU_LOG2(" %d\n", data_len, remaining);
-  TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, 2 + data_len), 0 );
-
   if (!remaining) {
-    stm->buffer  = NULL;
-    stm->bufsize = 0;
-    stm->offset  = 0;
-    if (tud_video_frame_xfer_complete_cb)
-      tud_video_frame_xfer_complete_cb();
+    tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
+    hdr->EndOfFrame = 1;
   }
+  TU_LOG2(" %d\n", data_len, remaining);
+  TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, hdr_len + data_len), 0 );
   return data_len;
 }
 
@@ -691,7 +693,12 @@ int tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsi
   if (!tud_video_n_streaming(itf))
     return false;
 
+  /* update the packet header */
   videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
+  tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
+  hdr->FrameID   ^= 1;
+  hdr->EndOfFrame = 0;
+
   stm->buffer  = (uint8_t*)buffer;
   stm->bufsize = bufsize;
   TU_LOG1(" xfer %d\n", bufsize);
@@ -835,8 +842,9 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 
   /* find streaming handle */
   unsigned i;
+  videod_streaming_interface_t *stm;
   for (i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
-    videod_streaming_interface_t *stm = &_videod_streaming_itf[i];
+    stm = &_videod_streaming_itf[i];
     unsigned const ep_ofs = stm->desc.ep[0];
     if (!ep_ofs) continue;
     void const *desc = _videod_itf[stm->index_vc].beg;
@@ -844,7 +852,15 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
       break;
   }
   TU_ASSERT(i < CFG_TUD_VIDEO_STREAMING);
-  _payload_xfer_in(rhport, i);
+  if (stm->offset < stm->bufsize) {
+    _payload_xfer_in(rhport, i);
+  } else {
+    stm->buffer  = NULL;
+    stm->bufsize = 0;
+    stm->offset  = 0;
+    if (tud_video_frame_xfer_complete_cb)
+      tud_video_frame_xfer_complete_cb();
+  }
   return true;
 }
 

From a978828c3abdf864f9806cec6aa73a36f9209cc3 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 25 Sep 2021 17:09:05 +0900
Subject: [PATCH 0517/2085] Add green plain

---
 examples/device/video_capture/src/images.h | 4614 ++++++++++++++++++++
 examples/device/video_capture/src/main.c   |   10 +-
 2 files changed, 4621 insertions(+), 3 deletions(-)
 create mode 100644 examples/device/video_capture/src/images.h

diff --git a/examples/device/video_capture/src/images.h b/examples/device/video_capture/src/images.h
new file mode 100644
index 000000000..2f4c42ad4
--- /dev/null
+++ b/examples/device/video_capture/src/images.h
@@ -0,0 +1,4614 @@
+static const unsigned char black_128x96_yuv[] = {
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
+};
+static const unsigned char white_128x96_yuv[] = {
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
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+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
+};
+static const unsigned char green_128x96_yuv[] = {
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
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+  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
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+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
+  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a
+};
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 1921da4bf..ce4272639 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -107,7 +107,7 @@ void tud_resume_cb(void)
 // USB Video
 //--------------------------------------------------------------------+
 static unsigned char const *frames[] = {
-  black_128x96_yuv, white_128x96_yuv
+  black_128x96_yuv, white_128x96_yuv, green_128x96_yuv
 };
 uint8_t current_frame = 0;
 
@@ -122,7 +122,9 @@ void video_task(void)
 
   if (!already_sent) {
     tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
-    current_frame ^= 1;
+    ++current_frame;
+    if (current_frame == sizeof(frames)/sizeof(frames[0]))
+      current_frame = 0;
     already_sent = 1;
   }
 
@@ -143,7 +145,9 @@ int tud_video_frame_xfer_complete_cb(void)
 {
   /* prepare tx */
   tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
-  current_frame ^= 1;
+  ++current_frame;
+  if (current_frame == sizeof(frames)/sizeof(frames[0]))
+    current_frame = 0;
   return 0;
 }
 

From d88cc23ca5eced51167edad00ea43c86038ee481 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 25 Sep 2021 16:59:17 +0900
Subject: [PATCH 0518/2085] Refactor packet handling

---
 examples/device/video_capture/src/main.c |   4 +-
 src/class/video/video_device.c           | 175 +++++++++++------------
 src/class/video/video_device.h           |   6 +-
 3 files changed, 90 insertions(+), 95 deletions(-)

diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index ce4272639..4ca0e5d90 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -141,10 +141,10 @@ void video_task(void)
   }
 }
 
-int tud_video_frame_xfer_complete_cb(void)
+int tud_video_frame_xfer_complete_cb(unsigned itf)
 {
   /* prepare tx */
-  tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
+  tud_video_n_frame_xfer(itf, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
   ++current_frame;
   if (current_frame == sizeof(frames)/sizeof(frames[0]))
     current_frame = 0;
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index acec7a992..344c4e0f9 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -191,7 +191,7 @@ static void const* _find_desc(void const *beg, void const *end, uint8_t target)
 static void const* _next_desc_itf(void const *beg, void const *end)
 {
   void const *cur = beg;
-  unsigned itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber;
+  uint_fast8_t itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber;
   while ((cur < end) &&
          (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) {
     cur = _find_desc(tu_desc_next(cur), end, TUSB_DESC_INTERFACE);
@@ -208,7 +208,7 @@ static void const* _next_desc_itf(void const *beg, void const *end)
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _find_desc_itf(void const *beg, void const *end, unsigned itfnum, unsigned altnum)
+static void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum)
 {
   for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_INTERFACE)) {
     tusb_desc_interface_t const *itf = (tusb_desc_interface_t const *)cur;
@@ -244,7 +244,7 @@ static void const* _find_desc_ep(void const *beg, void const *end)
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, unsigned entityid)
+static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, uint_fast8_t entityid)
 {
   void const *beg = (void const*)vc;
   void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength;
@@ -286,7 +286,7 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
  *
  * @param[in,out] self     The context.
  * @param[in]     altnum   The target alternate setting number. */
-static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altnum)
+static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum)
 {
   TU_LOG2("    open VC %d\r\n", altnum);
   void const *beg = self->beg;
@@ -325,17 +325,17 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, unsigned altn
  *
  * @param[in,out] self     The context.
  * @param[in]     altnum   The target alternate setting number. */
-static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, unsigned altnum)
+static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum)
 {
-  unsigned i;
+  uint_fast8_t i;
   TU_LOG1("    reopen VS %d\r\n", altnum);
   void const *desc = _videod_itf[stm->index_vc].beg;
 
   /* Close endpoints of previous settings. */
   for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) {
-    unsigned ofs_ep = stm->desc.ep[i];
+    uint_fast16_t ofs_ep = stm->desc.ep[i];
     if (!ofs_ep) break;
-    unsigned ep_adr = _desc_ep_addr(desc + ofs_ep);
+    uint_fast8_t  ep_adr = _desc_ep_addr(desc + ofs_ep);
     usbd_edpt_close(rhport, ep_adr);
     stm->desc.ep[i] = 0;
     TU_LOG1("    close EP%02x\n", ep_adr);
@@ -346,7 +346,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, unsi
   void const *end = desc + stm->desc.end;
   void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
   TU_VERIFY(cur < end);
-  unsigned numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints;
+  uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints;
   TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep));
   stm->desc.cur = cur - desc; /* Save the offset of the new settings */
   /* Open endpoints of the new settings. */
@@ -366,30 +366,15 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, unsi
   return true;
 }
 
-static int _payload_xfer_in(uint8_t rhport, uint8_t itf)
+static uint_fast16_t _prepair_in_payload(videod_streaming_interface_t *stm)
 {
-  videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
-  void const *desc = _videod_itf[stm->index_vc].beg;
-  unsigned ep_addr = 0;
-  for (unsigned i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
-    unsigned ofs_ep = stm->desc.ep[i];
-    if (!ofs_ep) continue;
-    ep_addr = _desc_ep_addr(desc + ofs_ep);
-    if (tu_edpt_dir(ep_addr))
-      break;
-  }
-  TU_ASSERT(ep_addr, 0);
-  /* Claim the endpoint */
-  TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0);
-
-  /* prepare a payload */
-  uint32_t remaining = stm->bufsize - stm->offset;
-  unsigned hdr_len   = stm->ep_buf[0];
-  unsigned pkt_len   = stm->max_payload_transfer_size;
+  uint_fast16_t remaining = stm->bufsize - stm->offset;
+  uint_fast16_t hdr_len   = stm->ep_buf[0];
+  uint_fast16_t pkt_len   = stm->max_payload_transfer_size;
   if (hdr_len + remaining < pkt_len) {
     pkt_len = hdr_len + remaining;
   }
-  uint32_t data_len = pkt_len - hdr_len;
+  uint_fast16_t data_len = pkt_len - hdr_len;
   memcpy(&stm->ep_buf[hdr_len], stm->buffer + stm->offset, data_len);
   stm->offset += data_len;
   remaining -= data_len;
@@ -397,13 +382,11 @@ static int _payload_xfer_in(uint8_t rhport, uint8_t itf)
     tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
     hdr->EndOfFrame = 1;
   }
-  TU_LOG2(" %d\n", data_len, remaining);
-  TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, hdr_len + data_len), 0 );
-  return data_len;
+  return hdr_len + data_len;
 }
 
 /** Handle a standard request to the video control interface. */
-static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
 {
   switch (request->bRequest) {
   case TUSB_REQ_GET_INTERFACE:
@@ -431,7 +414,7 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_
   }
 }
 
-static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
 {
   videod_interface_t *self = &_videod_itf[itf];
   /* 4.2.1 Interface Control Request */
@@ -491,9 +474,9 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
   return VIDEO_INVALID_REQUEST;
 }
 
-static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
 {
-  unsigned entity_id;
+  uint_fast8_t entity_id;
   switch (request->bmRequestType_bit.type) {
   case TUSB_REQ_TYPE_STANDARD:
     return handle_video_ctl_std_req(rhport, stage, request, itf);
@@ -511,7 +494,7 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_requ
   }
 }
 
-static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
 {
   videod_streaming_interface_t *self = &_videod_streaming_itf[itf];
   switch (request->bRequest) {
@@ -537,7 +520,7 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_
   }
 }
 
-static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
 {
   (void)rhport;
   videod_streaming_interface_t *self = &_videod_streaming_itf[itf];
@@ -652,7 +635,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
   return VIDEO_INVALID_REQUEST;
 }
 
-static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, unsigned itf)
+static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
 {
   switch (request->bmRequestType_bit.type) {
   case TUSB_REQ_TYPE_STANDARD:
@@ -670,6 +653,15 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_requ
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
+
+/* itf     control interface number */
+bool tud_video_n_connected(uint8_t itf)
+{
+  (void)itf;
+  // DTR (bit 0) active  is considered as connected
+  return tud_ready();
+}
+
 /* itf     streaming interface number */
 bool tud_video_n_streaming(uint8_t itf)
 {
@@ -679,41 +671,43 @@ bool tud_video_n_streaming(uint8_t itf)
   return false;
 }
 
-bool tud_video_n_connected(uint8_t itf)
-{
-  (void)itf;
-  // DTR (bit 0) active  is considered as connected
-  return tud_ready();
-}
-
-int tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize)
+bool tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize)
 {
   (void)pts;
 
+  if (!buffer || !buffer)
+    return false;
   if (!tud_video_n_streaming(itf))
     return false;
-
-  /* update the packet header */
   videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
+  if (stm->buffer)
+    return false;
+
+  /* find EP address */
+  void const *desc = _videod_itf[stm->index_vc].beg;
+  uint_fast8_t ep_addr = 0;
+  for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
+    uint_fast16_t ofs_ep = stm->desc.ep[i];
+    if (!ofs_ep) continue;
+    ep_addr = _desc_ep_addr(desc + ofs_ep);
+    break;
+  }
+  if (!ep_addr)
+    return false;
+
+  TU_VERIFY( usbd_edpt_claim(0, ep_addr));
+  /* update the packet header */
   tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
   hdr->FrameID   ^= 1;
   hdr->EndOfFrame = 0;
-
-  stm->buffer  = (uint8_t*)buffer;
-  stm->bufsize = bufsize;
-  TU_LOG1(" xfer %d\n", bufsize);
-  _payload_xfer_in(0, itf);
-  return 0;
+  /* update the packet data */
+  stm->buffer     = (uint8_t*)buffer;
+  stm->bufsize    = bufsize;
+  uint_fast16_t pkt_len = _prepair_in_payload(stm);
+  TU_ASSERT( usbd_edpt_xfer(0, ep_addr, stm->ep_buf, pkt_len), 0);
+  return true;
 }
 
-//--------------------------------------------------------------------+
-// READ API
-//--------------------------------------------------------------------+
-
-//--------------------------------------------------------------------+
-// WRITE API
-//--------------------------------------------------------------------+
-
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
@@ -750,7 +744,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 
   /* Find available interface */
   videod_interface_t *self = NULL;
-  unsigned itf;
+  uint_fast8_t itf;
   for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
     if (_videod_itf[itf].beg)
       continue;
@@ -766,13 +760,13 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   if (!_open_vc_itf(rhport, self, 0))
     return 0;
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
-  unsigned bInCollection       = vc->ctl.bInCollection;
+  uint_fast8_t bInCollection       = vc->ctl.bInCollection;
   /* Find the end of the video interface descriptor */
   void const *cur = _next_desc_itf(itf_desc, end);
-  for (unsigned i = 0; i < bInCollection; ++i) {
+  for (uint_fast8_t i = 0; i < bInCollection; ++i) {
     videod_streaming_interface_t *stm = NULL;
     /* find free streaming interface handle */
-    for (unsigned j = 0; j < TU_ARRAY_SIZE(_videod_streaming_itf); ++j) {
+    for (uint_fast8_t j = 0; j < TU_ARRAY_SIZE(_videod_streaming_itf); ++j) {
       if (_videod_streaming_itf[i].desc.beg)
         continue;
       stm = &_videod_streaming_itf[i];
@@ -798,19 +792,17 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) {
     return false;
   }
-  unsigned itfnum = tu_u16_low(request->wIndex);
+  uint_fast8_t itfnum = tu_u16_low(request->wIndex);
 
   /* Identify which control interface to use */
-  int itf = -1;
-  for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i) {
-    void const *desc = _videod_itf[i].beg;
-    if (!desc) break;
-    if (itfnum == _desc_itfnum(desc)) {
-      itf = i;
+  uint_fast8_t itf;
+  for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
+    void const *desc = _videod_itf[itf].beg;
+    if (!desc) continue;
+    if (itfnum == _desc_itfnum(desc))
       break;
-    }
   }
-  if (itf >= 0) {
+  if (itf < CFG_TUD_VIDEO) {
     err = handle_video_ctl_req(rhport, stage, request, itf);
     _videod_itf[itf].error_code = (uint8_t)err;
     if (err) return false;
@@ -818,16 +810,14 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   }
 
   /* Identify which streaming interface to use */
-  for (unsigned i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
-    videod_streaming_interface_t *stm = &_videod_streaming_itf[i];
-    if (!stm->desc.beg) return false;
+  for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) {
+    videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
+    if (!stm->desc.beg) continue;
     void const *desc = _videod_itf[stm->index_vc].beg;
-    if (itfnum == _desc_itfnum(desc + stm->desc.beg)) {
-      itf = i;
+    if (itfnum == _desc_itfnum(desc + stm->desc.beg))
       break;
-    }
   }
-  if (itf >= 0) {
+  if (itf < CFG_TUD_VIDEO_STREAMING) {
     err = handle_video_stm_req(rhport, stage, request, itf);
     _videod_streaming_itf[itf].error_code = (uint8_t)err;
     if (err) return false;
@@ -838,28 +828,31 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
 
 bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
 {
-  (void)rhport; (void)result; (void)xferred_bytes;
+  (void)result; (void)xferred_bytes;
 
   /* find streaming handle */
-  unsigned i;
+  uint_fast8_t itf;
   videod_streaming_interface_t *stm;
-  for (i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
-    stm = &_videod_streaming_itf[i];
-    unsigned const ep_ofs = stm->desc.ep[0];
+  for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) {
+    stm = &_videod_streaming_itf[itf];
+    uint_fast16_t const ep_ofs = stm->desc.ep[0];
     if (!ep_ofs) continue;
     void const *desc = _videod_itf[stm->index_vc].beg;
     if (ep_addr == _desc_ep_addr(desc + ep_ofs))
       break;
   }
-  TU_ASSERT(i < CFG_TUD_VIDEO_STREAMING);
+  TU_ASSERT(itf < CFG_TUD_VIDEO_STREAMING);
   if (stm->offset < stm->bufsize) {
-    _payload_xfer_in(rhport, i);
+    /* Claim the endpoint */
+    TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0);
+    uint_fast16_t pkt_len = _prepair_in_payload(stm);
+    TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, pkt_len), 0);
   } else {
     stm->buffer  = NULL;
     stm->bufsize = 0;
     stm->offset  = 0;
     if (tud_video_frame_xfer_complete_cb)
-      tud_video_frame_xfer_complete_cb();
+      tud_video_frame_xfer_complete_cb(itf);
   }
   return true;
 }
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index a1b13b9af..acf4c4d2b 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -42,10 +42,12 @@ extern "C" {
 bool tud_video_n_streaming(uint8_t itf);
 
 
-int tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize);
+/* itf       instance number of streaming interface */
+bool tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize);
 
 /*------------- Optional callbacks -------------*/
-TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(void);
+/* itf       instance number of streaming interface */
+TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(unsigned itf);
 
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)

From 0d6496886cae22f33408bd126925b5d6c4908d65 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 25 Sep 2021 20:49:04 +0900
Subject: [PATCH 0519/2085] Change frame buffer management

---
 examples/device/video_capture/src/main.c | 25 ++++++++++++++----------
 src/class/video/video_device.c           |  4 ++--
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 4ca0e5d90..4a124c537 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -109,30 +109,35 @@ void tud_resume_cb(void)
 static unsigned char const *frames[] = {
   black_128x96_yuv, white_128x96_yuv, green_128x96_yuv
 };
-uint8_t current_frame = 0;
+static unsigned current_frame = 0;
+static unsigned tx_busy = 0;
 
 void video_task(void)
 {
   static unsigned start_ms = 0;
-  static unsigned interval_ms = 66;
+  static unsigned interval_ms = 100;
   static unsigned frame_num = 0;
   static unsigned already_sent = 0;
 
-  if (!tud_video_n_streaming(0)) return;
+  if (!tud_video_n_streaming(0)) {
+    already_sent  = 0;
+    current_frame = 0;
+    return;
+  }
 
   if (!already_sent) {
-    tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
-    ++current_frame;
-    if (current_frame == sizeof(frames)/sizeof(frames[0]))
-      current_frame = 0;
     already_sent = 1;
+    start_ms = board_millis();
+    tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
   }
 
   unsigned cur = board_millis();
   if (cur - start_ms < interval_ms) return; // not enough time
+  if (tx_busy) return;
   start_ms += interval_ms;
 
-  /* flip buffer */
+  tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
+
   ++frame_num;
   if (frame_num % 3) {
     interval_ms = 66;
@@ -143,8 +148,8 @@ void video_task(void)
 
 int tud_video_frame_xfer_complete_cb(unsigned itf)
 {
-  /* prepare tx */
-  tud_video_n_frame_xfer(itf, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
+  tx_busy = 0;
+  /* flip buffer */
   ++current_frame;
   if (current_frame == sizeof(frames)/sizeof(frames[0]))
     current_frame = 0;
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 344c4e0f9..ad7057d30 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -128,9 +128,9 @@ static video_probe_and_commit_control_t const def_stm_settings = {
   .wCompWindowSize = 1, /* Maybe it is match to GOP size */
   .wDelay = 240, /* milliseconds */
   .dwMaxVideoFrameSize = 128 * 96 * 12 / 8,
-  .dwMaxPayloadTransferSize = 256, /* Maybe it is the maximum packet size under this settings */
+  .dwMaxPayloadTransferSize = ((128 * 96 * 12 / 8 * 10) + 999) / 1000 + 2,
   .dwClockFrequency = 27000000, /* same as MPEG-2 system time clock  */
-  .bmFramingInfo = 0,
+  .bmFramingInfo = 0x3,
   .bPreferedVersion = 1,
   .bMinVersion = 1,
   .bMaxVersion = 1,

From f7bbdea0b8f360d1fcf2f835211ed5c26e0240ea Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 26 Sep 2021 17:15:00 +0900
Subject: [PATCH 0520/2085] Refactor application API parameters

---
 examples/device/video_capture/src/main.c      |  22 +--
 .../device/video_capture/src/tusb_config.h    |  12 ++
 .../video_capture/src/usb_descriptors.c       |   2 +-
 src/class/video/video_device.c                | 163 +++++++++---------
 src/class/video/video_device.h                |  20 ++-
 5 files changed, 116 insertions(+), 103 deletions(-)

diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 4a124c537..abc97a377 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -35,9 +35,6 @@
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
 
-#define FRAME_WIDTH   128
-#define FRAME_HEIGHT  96
-
 /* Blink pattern
  * - 250 ms  : device not mounted
  * - 1000 ms : device mounted
@@ -115,11 +112,10 @@ static unsigned tx_busy = 0;
 void video_task(void)
 {
   static unsigned start_ms = 0;
-  static unsigned interval_ms = 100;
-  static unsigned frame_num = 0;
+  static unsigned interval_ms = 1000 / FRAME_RATE;
   static unsigned already_sent = 0;
 
-  if (!tud_video_n_streaming(0)) {
+  if (!tud_video_n_streaming(0, 0)) {
     already_sent  = 0;
     current_frame = 0;
     return;
@@ -128,7 +124,7 @@ void video_task(void)
   if (!already_sent) {
     already_sent = 1;
     start_ms = board_millis();
-    tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
+    tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], FRAME_WIDTH * FRAME_HEIGHT * 12/8);
   }
 
   unsigned cur = board_millis();
@@ -136,18 +132,12 @@ void video_task(void)
   if (tx_busy) return;
   start_ms += interval_ms;
 
-  tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], 128 * 96 * 12/8);
-
-  ++frame_num;
-  if (frame_num % 3) {
-    interval_ms = 66;
-  } else {
-    interval_ms = 67;
-  }
+  tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], FRAME_WIDTH * FRAME_HEIGHT * 12/8);
 }
 
-int tud_video_frame_xfer_complete_cb(unsigned itf)
+int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
 {
+  (void)ctl_idx; (void)stm_idx;
   tx_busy = 0;
   /* flip buffer */
   ++current_frame;
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index 3958b85b6..fb194c55a 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -90,8 +90,10 @@
 #define CFG_TUD_ENDPOINT0_SIZE    64
 #endif
 
+// video streaming endpoint size
 #define CFG_TUD_VIDEO_EP_BUFSIZE  256
 
+// The number of video streaming interfaces
 #define CFG_TUD_VIDEO_STREAMING  1
 
 //------------- CLASS -------------//
@@ -100,9 +102,19 @@
 #define CFG_TUD_HID              0
 #define CFG_TUD_MIDI             0
 #define CFG_TUD_AUDIO            0
+// The number of video control interfaces
 #define CFG_TUD_VIDEO            1
 #define CFG_TUD_VENDOR           0
 
+
+//--------------------------------------------------------------------
+// APPLICATION CONFIGURATION
+//--------------------------------------------------------------------
+#define FRAME_WIDTH   128
+#define FRAME_HEIGHT  96
+#define FRAME_RATE    10
+
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 096ac4373..a9fa2c043 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -104,7 +104,7 @@ uint8_t const desc_fs_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
   // IAD for Video Control
-  TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, 128, 96, 10, 256)
+  TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE, CFG_TUD_VIDEO_EP_BUFSIZE)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index ad7057d30..d01bbb146 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -38,11 +38,6 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-typedef struct {
-  uint8_t num;
-  uint8_t alt;
-} itf_setting_t;
-
 typedef struct {
   tusb_desc_interface_t            std;
   tusb_desc_cs_video_ctl_itf_hdr_t ctl;
@@ -65,49 +60,41 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bEntityId;
 } tusb_desc_cs_video_entity_itf_t;
 
+/* video streaming interface */
 typedef struct TU_ATTR_PACKED {
-  void const *beg;  /* The head of the first video control interface descriptor */
-  uint16_t length;  /* Byte length of the video control interface descriptors */
-  uint16_t offset;  /* offset bytes for the current video control interface descripter */
-  uint8_t  error_code;  /* error code set by previous transaction */
-  uint8_t  power_mode;  /* current power mode */
-} videod_control_interface_t;
-
-typedef struct TU_ATTR_PACKED {
-  uint8_t index_vc;  /* index of video control interface */
-  uint8_t error_code;/* error code for video control/streaming interface. 0:control 1:streaming 2:streaming */
+  uint8_t index_vc;  /* index of bound video control interface */
+  uint8_t index_vs;  /* index from the video control interface */
+  uint8_t error_code;/* error code */
   struct {
     uint16_t beg;    /* Offset of the beggining of video streaming interface descriptor */
     uint16_t end;    /* Offset of the end of video streaming interface descriptor */
     uint16_t cur;    /* Offset of the current settings */
-    uint16_t ep[2];  /* Offset of endpoint descriptors */
+    uint16_t ep[2];  /* Offset of endpoint descriptors. 0: streaming, 1: still capture */
   } desc;
-
   uint8_t  *buffer; /* frame buffer. assume linear buffer. no support for stride access */
-  uint32_t bufsize; /* frame buffer */
+  uint32_t bufsize; /* frame buffer size */
   uint32_t offset;  /* offset for the next payload transfer */
   uint32_t max_payload_transfer_size;
-  uint8_t  ep_buf[CFG_TUD_VIDEO_EP_BUFSIZE];
+  /*------------- From this point, data is not cleared by bus reset -------------*/
+  CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_EP_BUFSIZE]; /* EP transfer buffer for streaming */
 } videod_streaming_interface_t;
 
+/* video control interface */
 typedef struct TU_ATTR_PACKED {
   void const *beg;  /* The head of the first video control interface descriptor */
   uint16_t    len;  /* Byte length of the descriptors */
   uint16_t    cur;  /* offset for current video control interface */
   uint8_t     stm[CFG_TUD_VIDEO_STREAMING]; /* Indices of streaming interface */
-  uint8_t error_code;  /* error code for video control/streaming interface. */
+  uint8_t error_code;  /* error code */
   uint8_t power_mode;
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
-
-  // Endpoint Transfer buffer
-  //  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
-  //  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE];
-  uint8_t ctl_buf[64];
+  // 
+  // CFG_TUSB_MEM_ALIGN uint8_t ctl_buf[64]; /* EP transfer buffer for control */
 
 } videod_interface_t;
 
-#define ITF_MEM_RESET_SIZE   offsetof(videod_interface_t, ctl_buf)
+#define ITF_STM_MEM_RESET_SIZE   offsetof(videod_streaming_interface_t, ep_buf)
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -121,14 +108,14 @@ static video_probe_and_commit_control_t const def_stm_settings = {
   .bmHint = 0,
   .bFormatIndex = 1,
   .bFrameIndex = 1,
-  .dwFrameInterval = (10000000/10),
+  .dwFrameInterval = (10000000/FRAME_RATE),
   .wKeyFrameRate = 1,
   .wPFrameRate = 0,
   .wCompQuality = 1, /* 1 to 10000 */
   .wCompWindowSize = 1, /* Maybe it is match to GOP size */
   .wDelay = 240, /* milliseconds */
-  .dwMaxVideoFrameSize = 128 * 96 * 12 / 8,
-  .dwMaxPayloadTransferSize = ((128 * 96 * 12 / 8 * 10) + 999) / 1000 + 2,
+  .dwMaxVideoFrameSize = FRAME_WIDTH * FRAME_HEIGHT * 12 / 8,
+  .dwMaxPayloadTransferSize = ((FRAME_WIDTH * FRAME_HEIGHT * 12 / 8 * 10) + 999) / 1000 + 2,
   .dwClockFrequency = 27000000, /* same as MPEG-2 system time clock  */
   .bmFramingInfo = 0x3,
   .bPreferedVersion = 1,
@@ -142,22 +129,33 @@ static video_probe_and_commit_control_t const def_stm_settings = {
   .bmLayoutPerStream = 0
 };
 
+/* return bInterfaceNumber */
 static inline uint8_t _desc_itfnum(void const *desc)
 {
   return ((uint8_t const*)desc)[2];
 }
 
+/* return bEndpointAddress */
 static inline uint8_t _desc_ep_addr(void const *desc)
 {
   return ((uint8_t const*)desc)[2];
 }
 
+static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
+{
+  videod_interface_t *ctl = &_videod_itf[ctl_idx];
+  if (!ctl->beg) return NULL;
+  videod_streaming_interface_t *stm = &_videod_streaming_itf[ctl->stm[stm_idx]];
+  if (!stm->desc.beg) return NULL;
+  return stm;
+}
+
 static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self)
 {
   return (tusb_desc_vc_itf_t const *)(self->beg + self->cur);
 }
 
-static tusb_desc_vs_itf_t const *_get_desc_vs(videod_streaming_interface_t const *self)
+static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self)
 {
   if (!self->desc.cur) return NULL;
   void const *desc = _videod_itf[self->index_vc].beg;
@@ -230,7 +228,7 @@ static void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t
 static void const* _find_desc_ep(void const *beg, void const *end)
 {
   for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) {
-    uint8_t desc_type = tu_desc_type(cur);
+    uint_fast8_t desc_type = tu_desc_type(cur);
     if (TUSB_DESC_ENDPOINT == desc_type) return cur;
     if (TUSB_DESC_INTERFACE == desc_type) break;
   }
@@ -429,7 +427,8 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
         if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
           return VIDEO_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
-        if (tud_video_power_mode_cb) return tud_video_power_mode_cb(itf, self->power_mode);
+        if (tud_video_power_mode_cb)
+          return tud_video_power_mode_cb(itf, self->power_mode);
       }
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
@@ -553,7 +552,8 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
           return VIDEO_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
         if (tud_video_probe_set_cb)
-          return tud_video_probe_set_cb(itf, (video_probe_and_commit_control_t const*)self->ep_buf);
+          return tud_video_probe_set_cb(self->index_vc, self->index_vs,
+                                        (video_probe_and_commit_control_t const*)self->ep_buf);
       }
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
@@ -601,7 +601,8 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
           return VIDEO_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
         if (tud_video_commit_set_cb)
-          return tud_video_commit_set_cb(itf, (video_probe_and_commit_control_t const*)self->ep_buf);
+          return tud_video_commit_set_cb(self->index_vc, self->index_vs,
+                                         (video_probe_and_commit_control_t const*)self->ep_buf);
       }
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
@@ -654,33 +655,36 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_requ
 // APPLICATION API
 //--------------------------------------------------------------------+
 
-/* itf     control interface number */
-bool tud_video_n_connected(uint8_t itf)
+/* ctl_idx      instance number of video control interface */
+bool tud_video_n_connected(uint_fast8_t ctl_idx)
 {
-  (void)itf;
-  // DTR (bit 0) active  is considered as connected
-  return tud_ready();
-}
-
-/* itf     streaming interface number */
-bool tud_video_n_streaming(uint8_t itf)
-{
-  videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
-  if (stm->desc.ep[0])
+  TU_ASSERT(ctl_idx < CFG_TUD_VIDEO);
+  videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, 0);
+  if (stm)
     return true;
   return false;
 }
 
-bool tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize)
+/* ctl_idx      instance number of video control interface
+ * stm_idx      index number of streaming interface as per video control */
+bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
 {
-  (void)pts;
+  TU_ASSERT(ctl_idx < CFG_TUD_VIDEO);
+  TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING);
+  videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx);
+  if (!stm || !stm->desc.ep[0])
+    return false;
+  return true;
+}
 
+bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *buffer, size_t bufsize)
+{
+  TU_ASSERT(ctl_idx < CFG_TUD_VIDEO);
+  TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING);
   if (!buffer || !buffer)
     return false;
-  if (!tud_video_n_streaming(itf))
-    return false;
-  videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
-  if (stm->buffer)
+  videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx);
+  if (!stm || !stm->desc.ep[0] || stm->buffer)
     return false;
 
   /* find EP address */
@@ -713,26 +717,26 @@ bool tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufs
 //--------------------------------------------------------------------+
 void videod_init(void)
 {
-  tu_memclr(_videod_itf, sizeof(_videod_itf));
-
-  for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i)
-  {
-    // videod_interface_t* p_video = &_videod_itf[i];
-
-    // TODO
+  for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) {
+    videod_interface_t* ctl = &_videod_itf[i];
+    tu_memclr(ctl, sizeof(*ctl));
+  }
+  for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
+    videod_streaming_interface_t *stm = &_videod_streaming_itf[i];
+    tu_memclr(stm, ITF_STM_MEM_RESET_SIZE);
   }
 }
 
 void videod_reset(uint8_t rhport)
 {
   (void) rhport;
-
-  for (unsigned i = 0; i < CFG_TUD_VIDEO; ++i)
-  {
-    videod_interface_t* p_video = &_videod_itf[i];
-
-    // TODO
-    tu_memclr(p_video, ITF_MEM_RESET_SIZE);
+  for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO; ++i) {
+    videod_interface_t* ctl = &_videod_itf[i];
+    tu_memclr(ctl, sizeof(*ctl));
+  }
+  for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
+    videod_streaming_interface_t *stm = &_videod_streaming_itf[i];
+    tu_memclr(stm, ITF_STM_MEM_RESET_SIZE);
   }
 }
 
@@ -744,14 +748,14 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 
   /* Find available interface */
   videod_interface_t *self = NULL;
-  uint_fast8_t itf;
-  for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
-    if (_videod_itf[itf].beg)
+  uint_fast8_t ctl_idx;
+  for (ctl_idx = 0; ctl_idx < CFG_TUD_VIDEO; ++ctl_idx) {
+    if (_videod_itf[ctl_idx].beg)
       continue;
-    self = &_videod_itf[itf];
+    self = &_videod_itf[ctl_idx];
     break;
   }
-  TU_ASSERT(itf < CFG_TUD_VIDEO, 0);
+  TU_ASSERT(ctl_idx < CFG_TUD_VIDEO, 0);
 
   void const *end = (void const*)itf_desc + max_len;
   self->beg = itf_desc;
@@ -760,21 +764,22 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   if (!_open_vc_itf(rhport, self, 0))
     return 0;
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
-  uint_fast8_t bInCollection       = vc->ctl.bInCollection;
+  uint_fast8_t bInCollection   = vc->ctl.bInCollection;
   /* Find the end of the video interface descriptor */
   void const *cur = _next_desc_itf(itf_desc, end);
-  for (uint_fast8_t i = 0; i < bInCollection; ++i) {
+  for (uint_fast8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) {
     videod_streaming_interface_t *stm = NULL;
     /* find free streaming interface handle */
-    for (uint_fast8_t j = 0; j < TU_ARRAY_SIZE(_videod_streaming_itf); ++j) {
+    for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
       if (_videod_streaming_itf[i].desc.beg)
         continue;
       stm = &_videod_streaming_itf[i];
-      self->stm[i] = j;
+      self->stm[stm_idx] = i;
       break;
     }
     TU_ASSERT(stm, 0);
-    stm->index_vc = itf;
+    stm->index_vc = ctl_idx;
+    stm->index_vs = stm_idx;
     stm->desc.beg = (uintptr_t)cur - (uintptr_t)itf_desc;
     cur = _next_desc_itf(cur, end);
     stm->desc.end = (uintptr_t)cur - (uintptr_t)itf_desc;
@@ -832,12 +837,14 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 
   /* find streaming handle */
   uint_fast8_t itf;
+  videod_interface_t *ctl;
   videod_streaming_interface_t *stm;
   for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) {
     stm = &_videod_streaming_itf[itf];
     uint_fast16_t const ep_ofs = stm->desc.ep[0];
     if (!ep_ofs) continue;
-    void const *desc = _videod_itf[stm->index_vc].beg;
+    ctl = &_videod_itf[stm->index_vc];
+    void const *desc = ctl->beg;
     if (ep_addr == _desc_ep_addr(desc + ep_ofs))
       break;
   }
@@ -852,7 +859,7 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     stm->bufsize = 0;
     stm->offset  = 0;
     if (tud_video_frame_xfer_complete_cb)
-      tud_video_frame_xfer_complete_cb(itf);
+      tud_video_frame_xfer_complete_cb(stm->index_vc, stm->index_vs);
   }
   return true;
 }
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index acf4c4d2b..e6f53fed8 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -39,15 +39,19 @@ extern "C" {
 // Application API (Multiple Ports)
 // CFG_TUD_VIDEO > 1
 //--------------------------------------------------------------------+
-bool tud_video_n_streaming(uint8_t itf);
+/* ctl_idx       instance number of control interface
+ * stm_idx       instance number of streaming interface */
+bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx);
 
 
-/* itf       instance number of streaming interface */
-bool tud_video_n_frame_xfer(uint8_t itf, uint32_t pts, void *buffer, size_t bufsize);
+/* ctl_idx       instance number of control interface
+ * stm_idx       instance number of streaming interface */
+bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *buffer, size_t bufsize);
 
 /*------------- Optional callbacks -------------*/
-/* itf       instance number of streaming interface */
-TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(unsigned itf);
+/* ctl_idx       instance number of control interface
+ * stm_idx       instance number of streaming interface */
+TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx);
 
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
@@ -55,13 +59,13 @@ TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(unsigned itf);
 
 /* Invoked when SET POWER_MODE request received to 
  * @return video_error_code_t */
-TU_ATTR_WEAK int tud_video_power_mode_cb(unsigned itf, uint8_t power_mod);
+TU_ATTR_WEAK int tud_video_power_mode_cb(uint_fast8_t ctl_idx, uint8_t power_mod);
 
 /* @return video_error_code_t */
-TU_ATTR_WEAK int tud_video_probe_set_cb(unsigned itf, video_probe_and_commit_control_t const *settings);
+TU_ATTR_WEAK int tud_video_probe_set_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *settings);
 
 /* @return video_error_code_t */
-TU_ATTR_WEAK int tud_video_commit_set_cb(unsigned itf, video_probe_and_commit_control_t const *settings);
+TU_ATTR_WEAK int tud_video_commit_set_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *settings);
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+

From a15c3543296098ab292ef0c815000c6eb2c3a9fb Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 26 Sep 2021 17:44:36 +0900
Subject: [PATCH 0521/2085] Fix typo

---
 src/class/video/video_device.c | 47 +++++++++++++++++++---------------
 1 file changed, 26 insertions(+), 21 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index d01bbb146..5b5d0b430 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -129,18 +129,32 @@ static video_probe_and_commit_control_t const def_stm_settings = {
   .bmLayoutPerStream = 0
 };
 
-/* return bInterfaceNumber */
+/** Get interface number from the interface descriptor
+ *
+ * @param[in] desc    interface descriptor
+ *
+ * @return bInterfaceNumber */
 static inline uint8_t _desc_itfnum(void const *desc)
 {
   return ((uint8_t const*)desc)[2];
 }
 
-/* return bEndpointAddress */
+/** Get endpoint address from the endpoint descriptor
+ *
+ * @param[in] desc    endpoint descriptor
+ *
+ * @return bEndpointAddress */
 static inline uint8_t _desc_ep_addr(void const *desc)
 {
   return ((uint8_t const*)desc)[2];
 }
 
+/** Get instance of streaming interface
+ *
+ * @param[in] ctl_idx    instance number of video control
+ * @param[in] stm_idx    index number of streaming interface
+ *
+ * @return instance */
 static videod_streaming_interface_t* _get_instance_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
 {
   videod_interface_t *ctl = &_videod_itf[ctl_idx];
@@ -286,16 +300,16 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
  * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum)
 {
-  TU_LOG2("    open VC %d\r\n", altnum);
+  TU_LOG2("    open VC %d\n", altnum);
   void const *beg = self->beg;
   void const *end = beg + self->len;
   /* The first descriptor is a video control interface descriptor. */
   void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
-  TU_LOG2("    cur %ld\r\n", cur - beg);
+  TU_LOG2("    cur %ld\n", cur - beg);
   TU_VERIFY(cur < end);
 
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
-  TU_LOG2("    bInCollection %d\r\n", vc->ctl.bInCollection);
+  TU_LOG2("    bInCollection %d\n", vc->ctl.bInCollection);
   /* Support for up to 2 streaming interfaces only. */
   TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING);
 
@@ -303,7 +317,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
   end  = cur + vc->std.bLength + vc->ctl.wTotalLength;
   /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
   cur += vc->std.bLength + vc->ctl.bLength;
-  TU_LOG2("    bNumEndpoints %d\r\n", vc->std.bNumEndpoints);
+  TU_LOG2("    bNumEndpoints %d\n", vc->std.bNumEndpoints);
   /* Open the notification endpoint if it exist. */
   if (vc->std.bNumEndpoints) {
     /* Support for 1 endpoint only. */
@@ -326,7 +340,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
 static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum)
 {
   uint_fast8_t i;
-  TU_LOG1("    reopen VS %d\r\n", altnum);
+  TU_LOG2("    reopen VS %d\n", altnum);
   void const *desc = _videod_itf[stm->index_vc].beg;
 
   /* Close endpoints of previous settings. */
@@ -336,7 +350,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     uint_fast8_t  ep_adr = _desc_ep_addr(desc + ofs_ep);
     usbd_edpt_close(rhport, ep_adr);
     stm->desc.ep[i] = 0;
-    TU_LOG1("    close EP%02x\n", ep_adr);
+    TU_LOG2("    close EP%02x\n", ep_adr);
   }
 
   /* Find a alternate interface */
@@ -354,7 +368,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *)cur));
     stm->desc.ep[i] = cur - desc;
     stm->max_payload_transfer_size = def_stm_settings.dwMaxPayloadTransferSize;
-    TU_LOG1("    open EP%02x\n", _desc_ep_addr(cur));
+    TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
   }
   /* initialize payload header */
   tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
@@ -364,7 +378,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
   return true;
 }
 
-static uint_fast16_t _prepair_in_payload(videod_streaming_interface_t *stm)
+static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm)
 {
   uint_fast16_t remaining = stm->bufsize - stm->offset;
   uint_fast16_t hdr_len   = stm->ep_buf[0];
@@ -418,11 +432,9 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
   case VIDEO_VC_CTL_VIDEO_POWER_MODE:
-    TU_LOG2("    Power Mode ");
     switch (request->bRequest) {
     case VIDEO_REQUEST_SET_CUR:
       if (stage == CONTROL_STAGE_SETUP) {
-        TU_LOG2("Set\r\n");
         TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
         if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
           return VIDEO_UNKNOWN;
@@ -433,14 +445,12 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_LOG2("Get\r\n");
       TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
       if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
         return VIDEO_UNKNOWN;
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_INFO:
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_LOG2("GetInfo\r\n");
       TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
       if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
         return VIDEO_UNKNOWN;
@@ -449,17 +459,14 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
     }
     break;
   case VIDEO_VC_CTL_REQUEST_ERROR_CODE:
-    TU_LOG2("  Error Code");
     switch (request->bRequest) {
     case VIDEO_REQUEST_GET_CUR:
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_LOG2(" Get\r\n");
       if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)))
         return VIDEO_UNKNOWN;
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_INFO:
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_LOG2(" GetInfo\r\n");
       if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)))
         return VIDEO_UNKNOWN;
       return VIDEO_NO_ERROR;
@@ -526,7 +533,6 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
   case VIDEO_VS_CTL_STREAM_ERROR_CODE:
-    TU_LOG2("    Error Code ");
     switch (request->bRequest) {
     case VIDEO_REQUEST_GET_CUR:
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
@@ -536,7 +542,6 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_INFO:
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_LOG2("GetInfo\r\n");
       if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)))
         return VIDEO_UNKNOWN;
       return VIDEO_NO_ERROR;
@@ -707,7 +712,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
   /* update the packet data */
   stm->buffer     = (uint8_t*)buffer;
   stm->bufsize    = bufsize;
-  uint_fast16_t pkt_len = _prepair_in_payload(stm);
+  uint_fast16_t pkt_len = _prepare_in_payload(stm);
   TU_ASSERT( usbd_edpt_xfer(0, ep_addr, stm->ep_buf, pkt_len), 0);
   return true;
 }
@@ -852,7 +857,7 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
   if (stm->offset < stm->bufsize) {
     /* Claim the endpoint */
     TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0);
-    uint_fast16_t pkt_len = _prepair_in_payload(stm);
+    uint_fast16_t pkt_len = _prepare_in_payload(stm);
     TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, pkt_len), 0);
   } else {
     stm->buffer  = NULL;

From 319db9573c679e45a663326fbd4baa240a3da0ea Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 26 Sep 2021 18:33:30 +0900
Subject: [PATCH 0522/2085] Change video frames to project logo

---
 examples/device/video_capture/src/images.h | 9226 +++++++++++++-------
 examples/device/video_capture/src/main.c   |    4 +-
 2 files changed, 6154 insertions(+), 3076 deletions(-)

diff --git a/examples/device/video_capture/src/images.h b/examples/device/video_capture/src/images.h
index 2f4c42ad4..a55353d91 100644
--- a/examples/device/video_capture/src/images.h
+++ b/examples/device/video_capture/src/images.h
@@ -1,1541 +1,3 @@
-static const unsigned char black_128x96_yuv[] = {
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
-};
 static const unsigned char white_128x96_yuv[] = {
   0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
   0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -3074,1541 +1536,6155 @@ static const unsigned char white_128x96_yuv[] = {
   0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
   0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
 };
-static const unsigned char green_128x96_yuv[] = {
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
-  0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b,
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-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a,
-  0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a, 0x4a
+static const unsigned char t_128x96_yuv[] = {
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xa0, 0x54, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c,
+  0x5c, 0x5c, 0x5c, 0x5c, 0x55, 0x90, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x75, 0x0b,
+  0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
+  0x0d, 0x60, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x84, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x6e, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x31,
+  0x3f, 0x42, 0x2c, 0x1d, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x1d, 0x29, 0x43, 0x3f, 0x3f, 0x3f, 0x38, 0x6f,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb4, 0x08, 0x1a, 0x1a, 0x1d, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1d, 0x1a, 0x1a, 0x1a, 0x1a, 0x12, 0x53, 0xff, 0xff, 0xff, 0xf4,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xb6, 0x0e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb3, 0x06,
+  0x18, 0x18, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1d, 0x18, 0x18, 0x18, 0x18, 0x10, 0x52,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc7, 0x43, 0x50, 0x54, 0x33, 0x1c,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x1d, 0x2e, 0x55, 0x50, 0x50, 0x50, 0x4a, 0x7c, 0xff, 0xff, 0xff, 0xf5,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x83, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x6d, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x83, 0x13, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x94, 0x11, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0x0c,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x18, 0x53, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0d, 0x1e, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x2c, 0xfd, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x55, 0x16, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x1f, 0x17, 0x4e, 0xc7, 0xeb, 0xed, 0xc2, 0xc6,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd8,
+  0x06, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x18, 0x0d, 0x09, 0x09, 0x04, 0x4a, 0xff, 0xff, 0xff, 0xf5,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x09, 0x1e, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0x9c, 0x08, 0x10, 0x1b, 0x1f, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x17, 0x56,
+  0xff, 0xff, 0xff, 0xf5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x93, 0x2f, 0x06, 0x0c, 0x0f, 0x12, 0x15, 0x15, 0x14,
+  0x13, 0x12, 0x12, 0x10, 0x0d, 0x09, 0x01, 0x55, 0xff, 0xff, 0xff, 0xf3,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xef, 0xc7, 0xa8, 0x8a, 0x71, 0x72, 0x79, 0x81, 0x89, 0x91, 0xa1,
+  0xc2, 0xe3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
+};
+static const unsigned char ti_128x96_yuv[] = {
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xa0, 0x54, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c,
+  0x5c, 0x5c, 0x5c, 0x5c, 0x55, 0x90, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x4c, 0x58, 0x56, 0x56, 0x56, 0x56,
+  0x56, 0x56, 0x56, 0x58, 0x4f, 0xd9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x75, 0x0b,
+  0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
+  0x0d, 0x60, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf1, 0x00, 0x36, 0x3a, 0x39, 0x39, 0x39, 0x39, 0x39, 0x3a, 0x34,
+  0x01, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xf8,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0x03, 0xcb, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xe6, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xda, 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf3, 0x00, 0xed, 0xce, 0xad, 0xed, 0xff, 0xf1, 0xad, 0xcb, 0xe0,
+  0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xfa,
+  0x43, 0x00, 0xba, 0xff, 0xc9, 0x00, 0x38, 0xeb, 0x02, 0xcb, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xec, 0xdd, 0xc4, 0xf2, 0xff,
+  0xf5, 0xc3, 0xdc, 0xdf, 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf3, 0x00, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xda,
+  0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x84, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x6e, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xf8,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0x03, 0xdb, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x31,
+  0x3f, 0x42, 0x2c, 0x1d, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x1d, 0x29, 0x43, 0x3f, 0x3f, 0x3f, 0x38, 0x6f,
+  0xff, 0xff, 0xff, 0xf5, 0x2d, 0x3f, 0x16, 0x3d, 0x40, 0x3f, 0x3f, 0x3f,
+  0x3f, 0x3f, 0x40, 0x3b, 0x19, 0x37, 0x3e, 0xe3, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb4, 0x08, 0x1a, 0x1a, 0x1d, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1d, 0x1a, 0x1a, 0x1a, 0x1a, 0x12, 0x53, 0xff, 0xff, 0xff, 0xf4,
+  0x02, 0x1b, 0x20, 0x1b, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1b,
+  0x1f, 0x1a, 0x16, 0xde, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xb6, 0x0e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb3, 0x06,
+  0x18, 0x18, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1d, 0x18, 0x18, 0x18, 0x18, 0x10, 0x52,
+  0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc7, 0x43, 0x50, 0x54, 0x33, 0x1c,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x1d, 0x2e, 0x55, 0x50, 0x50, 0x50, 0x4a, 0x7c, 0xff, 0xff, 0xff, 0xf5,
+  0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x83, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x6d, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x1e, 0x17, 0x14, 0x17, 0x1e, 0x1f,
+  0x1a, 0x11, 0x10, 0x16, 0x1e, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x08, 0x1d, 0x18, 0x5d, 0x84, 0x59, 0x19, 0x13, 0x39, 0xa2, 0xa7, 0x6c,
+  0x16, 0x1b, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x0c, 0xce, 0xff,
+  0xff, 0xff, 0xc1, 0x40, 0xff, 0xff, 0xff, 0xff, 0xb1, 0x14, 0x1a, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x01, 0x5a, 0xff, 0xff, 0xc3, 0xd8, 0xff, 0xfb,
+  0xff, 0xae, 0xa8, 0xff, 0xff, 0x53, 0x13, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x00, 0xac, 0xff, 0x72, 0x00, 0x00, 0xb8, 0xff, 0x82, 0x00, 0x00, 0x7f,
+  0xff, 0xa3, 0x0c, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x00, 0xbb, 0xff, 0xd4,
+  0xc8, 0xc6, 0xdf, 0xff, 0xd7, 0xc8, 0xc8, 0xd5, 0xff, 0xc1, 0x09, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x00, 0xc4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xca, 0x09, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x02, 0x5b, 0x79, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x71, 0x70, 0x72,
+  0x79, 0x5c, 0x14, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x0f, 0x04, 0x0a,
+  0x14, 0x14, 0x14, 0x0f, 0x05, 0x2b, 0x34, 0x24, 0x05, 0x15, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x01, 0x68, 0xb8, 0x83, 0x19, 0x1f, 0x14, 0x2c,
+  0xbb, 0xff, 0xff, 0xfb, 0x96, 0x14, 0x1a, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4,
+  0x00, 0xcc, 0xff, 0x6c, 0x12, 0x11, 0x4d, 0xf9, 0xff, 0xff, 0xf9, 0xff,
+  0xff, 0x73, 0x10, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x00, 0xd4, 0xff, 0x79,
+  0x05, 0x70, 0xff, 0xff, 0xff, 0x76, 0x10, 0x94, 0xff, 0xc2, 0x09, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x00, 0x91, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xfb,
+  0x39, 0x0e, 0x12, 0x62, 0xff, 0xc5, 0x09, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x06, 0x0d, 0xc3, 0xff, 0xff, 0xff, 0xbf, 0x1f, 0x16, 0x20, 0x0c, 0xe5,
+  0xff, 0x7e, 0x0f, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x83, 0x13, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x18, 0x05, 0x1b,
+  0x34, 0x1c, 0x06, 0x12, 0x16, 0x16, 0x16, 0x12, 0x11, 0x16, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x94, 0x11, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x03, 0x52, 0x6c, 0x66, 0x64, 0x66, 0x69, 0x69,
+  0x69, 0x6a, 0x5b, 0x3e, 0x0d, 0x1a, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0x0c,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x18, 0x53, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x00, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xcb, 0x20, 0x18, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0d, 0x1e, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x2c, 0xfd, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x00, 0x9e, 0xdf, 0xd8,
+  0xd8, 0xd8, 0xd8, 0xd8, 0xd8, 0xd7, 0xdf, 0xff, 0xff, 0x99, 0x0e, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x55, 0x16, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x1f, 0x17, 0x4e, 0xc7, 0xeb, 0xed, 0xc2, 0xc6,
+  0xff, 0xff, 0xff, 0xf5, 0x07, 0x0b, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+  0x01, 0x01, 0x03, 0x5b, 0xff, 0xd8, 0x14, 0xde, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd8,
+  0x06, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x18, 0x0d, 0x09, 0x09, 0x04, 0x4a, 0xff, 0xff, 0xff, 0xf5,
+  0x03, 0x55, 0x71, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x64, 0xb5,
+  0xff, 0xcc, 0x0f, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x09, 0x1e, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0x00, 0xc7, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x13, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0x9c, 0x08, 0x10, 0x1b, 0x1f, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x17, 0x56,
+  0xff, 0xff, 0xff, 0xf5, 0x00, 0xb3, 0xfe, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6,
+  0xf6, 0xf7, 0xd7, 0xb6, 0x41, 0x11, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x93, 0x2f, 0x06, 0x0c, 0x0f, 0x12, 0x15, 0x15, 0x14,
+  0x13, 0x12, 0x12, 0x10, 0x0d, 0x09, 0x01, 0x55, 0xff, 0xff, 0xff, 0xf3,
+  0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x07, 0x0b, 0x0a, 0xdc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xef, 0xc7, 0xa8, 0x8a, 0x71, 0x72, 0x79, 0x81, 0x89, 0x91, 0xa1,
+  0xc2, 0xe3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xb4, 0xbc, 0xbc, 0xbc,
+  0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbb, 0xba, 0xf6,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
+};
+static const unsigned char tin_128x96_yuv[] = {
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xa0, 0x54, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c,
+  0x5c, 0x5c, 0x5c, 0x5c, 0x55, 0x90, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x4c, 0x58, 0x56, 0x56, 0x56, 0x56,
+  0x56, 0x56, 0x56, 0x58, 0x4f, 0xd9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x75, 0x0b,
+  0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
+  0x0d, 0x60, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf1, 0x00, 0x36, 0x3a, 0x39, 0x39, 0x39, 0x39, 0x39, 0x3a, 0x34,
+  0x01, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xf8,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0x03, 0xcb, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xe6, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xda, 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf3, 0x00, 0xed, 0xce, 0xad, 0xed, 0xff, 0xf1, 0xad, 0xcb, 0xe0,
+  0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xfa,
+  0x43, 0x00, 0xba, 0xff, 0xc9, 0x00, 0x38, 0xeb, 0x02, 0xcb, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xec, 0xdd, 0xc4, 0xf2, 0xff,
+  0xf5, 0xc3, 0xdc, 0xdf, 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf3, 0x00, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xda,
+  0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x84, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x6e, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xf8,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0x03, 0xdb, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xde, 0xca, 0xbb, 0xa4, 0x9a, 0xa7, 0xc7, 0xeb, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x31,
+  0x3f, 0x42, 0x2c, 0x1d, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x1d, 0x29, 0x43, 0x3f, 0x3f, 0x3f, 0x38, 0x6f,
+  0xff, 0xff, 0xff, 0xf5, 0x2d, 0x3f, 0x16, 0x3d, 0x40, 0x3f, 0x3f, 0x3f,
+  0x3f, 0x3f, 0x40, 0x3b, 0x19, 0x37, 0x3e, 0xe3, 0xff, 0xff, 0xff, 0xff,
+  0x35, 0x3e, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f,
+  0x3f, 0x36, 0x86, 0xff, 0xff, 0xff, 0xce, 0x73, 0x36, 0x1d, 0x12, 0x0d,
+  0x10, 0x10, 0x0f, 0x10, 0x25, 0x3d, 0x7e, 0xdb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb4, 0x08, 0x1a, 0x1a, 0x1d, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1d, 0x1a, 0x1a, 0x1a, 0x1a, 0x12, 0x53, 0xff, 0xff, 0xff, 0xf4,
+  0x02, 0x1b, 0x20, 0x1b, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1b,
+  0x1f, 0x1a, 0x16, 0xde, 0xff, 0xff, 0xff, 0xff, 0x0c, 0x18, 0x1a, 0x1a,
+  0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0f, 0x6e, 0xff,
+  0xe6, 0x55, 0x11, 0x13, 0x1a, 0x1d, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x1f,
+  0x1d, 0x1a, 0x12, 0x13, 0x6e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xb6, 0x0e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x15, 0x7d, 0xdd, 0x10, 0x15, 0x1e, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e,
+  0x0e, 0x45, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb3, 0x06,
+  0x18, 0x18, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1d, 0x18, 0x18, 0x18, 0x18, 0x10, 0x52,
+  0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1a, 0x57, 0x20, 0x1b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x0f, 0x5c, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc7, 0x43, 0x50, 0x54, 0x33, 0x1c,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x1d, 0x2e, 0x55, 0x50, 0x50, 0x50, 0x4a, 0x7c, 0xff, 0xff, 0xff, 0xf5,
+  0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1a, 0x1d,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x05, 0xb1, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x83, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x6d, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x14, 0x0d, 0x0a, 0x0b, 0x0f,
+  0x19, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x1b, 0x29, 0xff, 0xff, 0xf4, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x19, 0x86, 0xc3, 0xdf, 0xd4, 0xae, 0x44, 0x14, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x09,
+  0xca, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xd4,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0x38, 0x1a, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x13, 0x82, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0x8d, 0x12, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x17, 0x55, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x1e, 0x17, 0x14, 0x17, 0x1e, 0x1f,
+  0x1a, 0x11, 0x10, 0x16, 0x1e, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb9, 0x0e, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x19,
+  0x44, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x08, 0x1d, 0x18, 0x5d, 0x84, 0x59, 0x19, 0x13, 0x39, 0xa2, 0xa7, 0x6c,
+  0x16, 0x1b, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcc,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xcc, 0x0c, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x37, 0xfb, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x0c, 0xce, 0xff,
+  0xff, 0xff, 0xc1, 0x40, 0xff, 0xff, 0xff, 0xff, 0xb1, 0x14, 0x1a, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x32, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x01, 0x5a, 0xff, 0xff, 0xc3, 0xd8, 0xff, 0xfb,
+  0xff, 0xae, 0xa8, 0xff, 0xff, 0x53, 0x13, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x00, 0xac, 0xff, 0x72, 0x00, 0x00, 0xb8, 0xff, 0x82, 0x00, 0x00, 0x7f,
+  0xff, 0xa3, 0x0c, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x00, 0xbb, 0xff, 0xd4,
+  0xc8, 0xc6, 0xdf, 0xff, 0xd7, 0xc8, 0xc8, 0xd5, 0xff, 0xc1, 0x09, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x00, 0xc4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xca, 0x09, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x02, 0x5b, 0x79, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x71, 0x70, 0x72,
+  0x79, 0x5c, 0x14, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x0f, 0x04, 0x0a,
+  0x14, 0x14, 0x14, 0x0f, 0x05, 0x2b, 0x34, 0x24, 0x05, 0x15, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x01, 0x68, 0xb8, 0x83, 0x19, 0x1f, 0x14, 0x2c,
+  0xbb, 0xff, 0xff, 0xfb, 0x96, 0x14, 0x1a, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4,
+  0x00, 0xcc, 0xff, 0x6c, 0x12, 0x11, 0x4d, 0xf9, 0xff, 0xff, 0xf9, 0xff,
+  0xff, 0x73, 0x10, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x00, 0xd4, 0xff, 0x79,
+  0x05, 0x70, 0xff, 0xff, 0xff, 0x76, 0x10, 0x94, 0xff, 0xc2, 0x09, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x00, 0x91, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xfb,
+  0x39, 0x0e, 0x12, 0x62, 0xff, 0xc5, 0x09, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x06, 0x0d, 0xc3, 0xff, 0xff, 0xff, 0xbf, 0x1f, 0x16, 0x20, 0x0c, 0xe5,
+  0xff, 0x7e, 0x0f, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x83, 0x13, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x18, 0x05, 0x1b,
+  0x34, 0x1c, 0x06, 0x12, 0x16, 0x16, 0x16, 0x12, 0x11, 0x16, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x94, 0x11, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x03, 0x52, 0x6c, 0x66, 0x64, 0x66, 0x69, 0x69,
+  0x69, 0x6a, 0x5b, 0x3e, 0x0d, 0x1a, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0x0c,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x18, 0x53, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x00, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xcb, 0x20, 0x18, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0d, 0x1e, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x2c, 0xfd, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x00, 0x9e, 0xdf, 0xd8,
+  0xd8, 0xd8, 0xd8, 0xd8, 0xd8, 0xd7, 0xdf, 0xff, 0xff, 0x99, 0x0e, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x55, 0x16, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x1f, 0x17, 0x4e, 0xc7, 0xeb, 0xed, 0xc2, 0xc6,
+  0xff, 0xff, 0xff, 0xf5, 0x07, 0x0b, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+  0x01, 0x01, 0x03, 0x5b, 0xff, 0xd8, 0x14, 0xde, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd8,
+  0x06, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x18, 0x0d, 0x09, 0x09, 0x04, 0x4a, 0xff, 0xff, 0xff, 0xf5,
+  0x03, 0x55, 0x71, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x64, 0xb5,
+  0xff, 0xcc, 0x0f, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x09, 0x1e, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0x00, 0xc7, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x13, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0x9c, 0x08, 0x10, 0x1b, 0x1f, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x17, 0x56,
+  0xff, 0xff, 0xff, 0xf5, 0x00, 0xb3, 0xfe, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6,
+  0xf6, 0xf7, 0xd7, 0xb6, 0x41, 0x11, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x93, 0x2f, 0x06, 0x0c, 0x0f, 0x12, 0x15, 0x15, 0x14,
+  0x13, 0x12, 0x12, 0x10, 0x0d, 0x09, 0x01, 0x55, 0xff, 0xff, 0xff, 0xf3,
+  0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x07, 0x0b, 0x0a, 0xdc, 0xff, 0xff, 0xff, 0xff, 0x01, 0x0c, 0x0d, 0x0d,
+  0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0c, 0x03, 0xc6,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xcb, 0x00, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d,
+  0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x09, 0x23, 0xf6, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xef, 0xc7, 0xa8, 0x8a, 0x71, 0x72, 0x79, 0x81, 0x89, 0x91, 0xa1,
+  0xc2, 0xe3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xb4, 0xbc, 0xbc, 0xbc,
+  0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbb, 0xba, 0xf6,
+  0xff, 0xff, 0xff, 0xff, 0xb7, 0xbb, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc,
+  0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xb7, 0xef, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf1, 0xb5, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc,
+  0xbc, 0xbc, 0xbc, 0xba, 0xc1, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
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+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
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+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
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+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
+};
+static const unsigned char logo_128x96_yuv[] = {
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xa0, 0x54, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c, 0x5c,
+  0x5c, 0x5c, 0x5c, 0x5c, 0x55, 0x90, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x4c, 0x58, 0x56, 0x56, 0x56, 0x56,
+  0x56, 0x56, 0x56, 0x58, 0x4f, 0xd9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x75, 0x0b,
+  0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
+  0x0d, 0x60, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf1, 0x00, 0x36, 0x3a, 0x39, 0x39, 0x39, 0x39, 0x39, 0x3a, 0x34,
+  0x01, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xf8,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0x03, 0xcb, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xe6, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xda, 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf3, 0x00, 0xed, 0xce, 0xad, 0xed, 0xff, 0xf1, 0xad, 0xcb, 0xe0,
+  0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xfa,
+  0x43, 0x00, 0xba, 0xff, 0xc9, 0x00, 0x38, 0xeb, 0x02, 0xcb, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0x00, 0xec, 0xdd, 0xc4, 0xf2, 0xff,
+  0xf5, 0xc3, 0xdc, 0xdf, 0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf3, 0x00, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xda,
+  0x02, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x31,
+  0x3f, 0x42, 0x2c, 0x1d, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
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+  0xff, 0xff, 0xff, 0xf5, 0x2d, 0x3f, 0x16, 0x3d, 0x40, 0x3f, 0x3f, 0x3f,
+  0x3f, 0x3f, 0x40, 0x3b, 0x19, 0x37, 0x3e, 0xe3, 0xff, 0xff, 0xff, 0xff,
+  0x35, 0x3e, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f,
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+  0x8e, 0x32, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x91, 0x36, 0x3f, 0x3f,
+  0x3e, 0x35, 0xd5, 0xff, 0xff, 0xff, 0xb4, 0x08, 0x1a, 0x1a, 0x1d, 0x20,
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+  0x20, 0x1d, 0x1a, 0x1a, 0x1a, 0x1a, 0x12, 0x53, 0xff, 0xff, 0xff, 0xf4,
+  0x02, 0x1b, 0x20, 0x1b, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1b,
+  0x1f, 0x1a, 0x16, 0xde, 0xff, 0xff, 0xff, 0xff, 0x0c, 0x18, 0x1a, 0x1a,
+  0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x0f, 0x6e, 0xff,
+  0xe6, 0x55, 0x11, 0x13, 0x1a, 0x1d, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x1f,
+  0x1d, 0x1a, 0x12, 0x13, 0x6e, 0xff, 0xff, 0xff, 0xe2, 0x17, 0x17, 0x1a,
+  0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a,
+  0x09, 0x9f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0x16, 0x17, 0x1a, 0x1a, 0x13, 0x36, 0xff, 0xff,
+  0xff, 0xff, 0xb6, 0x0e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
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+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x15, 0x7d, 0xdd, 0x10, 0x15, 0x1e, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1e,
+  0x0e, 0x45, 0xff, 0xff, 0xff, 0x73, 0x12, 0x1f, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x2f, 0xfd, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa5,
+  0x10, 0x1f, 0x20, 0x1f, 0x11, 0xb0, 0xff, 0xff, 0xff, 0xff, 0xb3, 0x06,
+  0x18, 0x18, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
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+  0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
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+  0x20, 0x20, 0x20, 0x20, 0x1f, 0x0d, 0xa0, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2b, 0x1b, 0x20, 0x20, 0x1b,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x4d, 0x18,
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+  0xca, 0xff, 0xff, 0x7d, 0x11, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
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+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0x38, 0x1a, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x13, 0x82, 0xff, 0xff, 0xf6,
+  0x14, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
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+  0xff, 0x68, 0x15, 0x20, 0x20, 0x1e, 0x16, 0xe5, 0xff, 0xff, 0xff, 0xff,
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+  0x26, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x16, 0x1e, 0x20,
+  0x20, 0x16, 0x60, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xf5, 0x08, 0x20, 0x1e, 0x17, 0x14, 0x17, 0x1e, 0x1f,
+  0x1a, 0x11, 0x10, 0x16, 0x1e, 0x1e, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
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+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x19,
+  0x44, 0xff, 0xff, 0xff, 0xfc, 0x11, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x12, 0x9d, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0x87, 0x11, 0x20, 0x20, 0x1f, 0x0c, 0xd4, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x08, 0x1d, 0x18, 0x5d, 0x84, 0x59, 0x19, 0x13, 0x39, 0xa2, 0xa7, 0x6c,
+  0x16, 0x1b, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcc,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xcc, 0x0c, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x37, 0xfb, 0xff, 0xff,
+  0xff, 0x7d, 0x12, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x1c, 0x22, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9,
+  0x2b, 0x1c, 0x20, 0x20, 0x19, 0x48, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x0c, 0xce, 0xff,
+  0xff, 0xff, 0xc1, 0x40, 0xff, 0xff, 0xff, 0xff, 0xb1, 0x14, 0x1a, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x32, 0xf8, 0xff, 0xff, 0xff, 0xff, 0x0b, 0x1e,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x1f, 0x10, 0xa1, 0xff, 0xff, 0xff, 0xff, 0xa5, 0x0d, 0x1f, 0x20, 0x1f,
+  0x0b, 0xb6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x01, 0x5a, 0xff, 0xff, 0xc3, 0xd8, 0xff, 0xfb,
+  0xff, 0xae, 0xa8, 0xff, 0xff, 0x53, 0x13, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x13, 0x1f, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x1a, 0xff,
+  0xff, 0xff, 0xff, 0x39, 0x1a, 0x20, 0x20, 0x1b, 0x29, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x00, 0xac, 0xff, 0x72, 0x00, 0x00, 0xb8, 0xff, 0x82, 0x00, 0x00, 0x7f,
+  0xff, 0xa3, 0x0c, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x11, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x0d, 0xa5, 0xff, 0xff, 0xbf, 0x0e,
+  0x1f, 0x20, 0x20, 0x0f, 0x99, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x00, 0xbb, 0xff, 0xd4,
+  0xc8, 0xc6, 0xdf, 0xff, 0xd7, 0xc8, 0xc8, 0xd5, 0xff, 0xc1, 0x09, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x82,
+  0x12, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x1c, 0x1f, 0xff, 0xff, 0x47, 0x18, 0x20, 0x20, 0x1e, 0x0f,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x00, 0xc4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xca, 0x09, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf8, 0x1b, 0x1d, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x0d,
+  0xaa, 0xdf, 0x16, 0x1e, 0x20, 0x1f, 0x13, 0x7a, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x02, 0x5b, 0x79, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x71, 0x70, 0x72,
+  0x79, 0x5c, 0x14, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0x84, 0x11, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x3d, 0x61, 0x17, 0x1f,
+  0x20, 0x1f, 0x0b, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x0f, 0x04, 0x0a,
+  0x14, 0x14, 0x14, 0x0f, 0x05, 0x2b, 0x34, 0x24, 0x05, 0x15, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xf3, 0x22, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1f, 0x1c, 0x1b, 0x1f, 0x20, 0x20, 0x16, 0x59, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x01, 0x68, 0xb8, 0x83, 0x19, 0x1f, 0x14, 0x2c,
+  0xbb, 0xff, 0xff, 0xfb, 0x96, 0x14, 0x1a, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x85, 0x11, 0x1f,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x1f, 0x1f, 0x20, 0x20, 0x1f, 0x11, 0xd0, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4,
+  0x00, 0xcc, 0xff, 0x6c, 0x12, 0x11, 0x4d, 0xf9, 0xff, 0xff, 0xf9, 0xff,
+  0xff, 0x73, 0x10, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xf2, 0x24, 0x1c, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x19, 0x3d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf4, 0x00, 0xd4, 0xff, 0x79,
+  0x05, 0x70, 0xff, 0xff, 0xff, 0x76, 0x10, 0x94, 0xff, 0xc2, 0x09, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x85, 0x10, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x11, 0xb1, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x7a, 0x14, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x00, 0x91, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xfb,
+  0x39, 0x0e, 0x12, 0x62, 0xff, 0xc5, 0x09, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x21,
+  0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x2a, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7a, 0x14,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x06, 0x0d, 0xc3, 0xff, 0xff, 0xff, 0xbf, 0x1f, 0x16, 0x20, 0x0c, 0xe5,
+  0xff, 0x7e, 0x0f, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8c, 0x0f, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x0e,
+  0x9b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x83, 0x13, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x07, 0x18, 0x05, 0x1b,
+  0x34, 0x1c, 0x06, 0x12, 0x16, 0x16, 0x16, 0x12, 0x11, 0x16, 0x1b, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xfc, 0x1f, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x25, 0xf8, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x94, 0x11, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x16, 0x66, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xf5, 0x03, 0x52, 0x6c, 0x66, 0x64, 0x66, 0x69, 0x69,
+  0x69, 0x6a, 0x5b, 0x3e, 0x0d, 0x1a, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0x8f, 0x0f, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x11, 0x7d, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0x0c,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x18, 0x53, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5,
+  0x00, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xcb, 0x20, 0x18, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1c, 0x1d, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1d, 0x19, 0xe3,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, 0x0d, 0x1e, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1c, 0x2c, 0xfd, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf5, 0x00, 0x9e, 0xdf, 0xd8,
+  0xd8, 0xd8, 0xd8, 0xd8, 0xd8, 0xd7, 0xdf, 0xff, 0xff, 0x99, 0x0e, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0x92, 0x0f, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x15, 0x60, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x55, 0x16, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x1f, 0x17, 0x4e, 0xc7, 0xeb, 0xed, 0xc2, 0xc6,
+  0xff, 0xff, 0xff, 0xf5, 0x07, 0x0b, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+  0x01, 0x01, 0x03, 0x5b, 0xff, 0xd8, 0x14, 0xde, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0x15, 0x1d, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x1f, 0x0e, 0xd3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd8,
+  0x06, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x18, 0x0d, 0x09, 0x09, 0x04, 0x4a, 0xff, 0xff, 0xff, 0xf5,
+  0x03, 0x55, 0x71, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x6d, 0x64, 0xb5,
+  0xff, 0xcc, 0x0f, 0xdf, 0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x91, 0x11,
+  0x1f, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x18, 0x4a, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x09, 0x1e, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x17, 0x57, 0xff, 0xff, 0xff, 0xf5, 0x00, 0xc7, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x13, 0xdf,
+  0xff, 0xff, 0xff, 0xff, 0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xd0, 0x0b, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1b, 0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x15, 0x1d, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x1f, 0x0b, 0xb9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0x9c, 0x08, 0x10, 0x1b, 0x1f, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x17, 0x56,
+  0xff, 0xff, 0xff, 0xf5, 0x00, 0xb3, 0xfe, 0xf6, 0xf6, 0xf6, 0xf6, 0xf6,
+  0xf6, 0xf7, 0xd7, 0xb6, 0x41, 0x11, 0x1b, 0xdf, 0xff, 0xff, 0xff, 0xff,
+  0x12, 0x1e, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x1f, 0x15, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd0, 0x0b, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x33, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x90, 0x11, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x20, 0x1b,
+  0x2e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x93, 0x2f, 0x06, 0x0c, 0x0f, 0x12, 0x15, 0x15, 0x14,
+  0x13, 0x12, 0x12, 0x10, 0x0d, 0x09, 0x01, 0x55, 0xff, 0xff, 0xff, 0xf3,
+  0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x07, 0x0b, 0x0a, 0xdc, 0xff, 0xff, 0xff, 0xff, 0x01, 0x0c, 0x0d, 0x0d,
+  0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0c, 0x03, 0xc6,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xcb, 0x00, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d,
+  0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x09, 0x23, 0xf6, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0x1d, 0x1c, 0x20, 0x20, 0x20, 0x20, 0x20, 0x0e, 0x9d, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xef, 0xc7, 0xa8, 0x8a, 0x71, 0x72, 0x79, 0x81, 0x89, 0x91, 0xa1,
+  0xc2, 0xe3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xb4, 0xbc, 0xbc, 0xbc,
+  0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbb, 0xba, 0xf6,
+  0xff, 0xff, 0xff, 0xff, 0xb7, 0xbb, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc,
+  0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xb7, 0xef, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xf1, 0xb5, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc,
+  0xbc, 0xbc, 0xbc, 0xba, 0xc1, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x96, 0x11, 0x1f, 0x20,
+  0x20, 0x20, 0x1d, 0x16, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0x30, 0x1c, 0x20, 0x20, 0x20, 0x12, 0x81,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0x48, 0x19, 0x20, 0x20, 0x1f, 0x08, 0xf7, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd7, 0x18, 0x1e, 0x20,
+  0x1f, 0x16, 0x5a, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0x69, 0x14, 0x20, 0x20, 0x1f, 0x0f, 0xd4, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf6,
+  0x16, 0x1d, 0x20, 0x20, 0x19, 0x3b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8a, 0x12, 0x1f, 0x20, 0x1f,
+  0x11, 0xb6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0x16, 0x1d, 0x20, 0x20, 0x1b, 0x28, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7, 0x10,
+  0x1f, 0x20, 0x1f, 0x0f, 0x9c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x2e, 0x1a, 0x20, 0x20, 0x1c, 0x24,
+  0xf9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xca, 0x09, 0x1f, 0x20, 0x20, 0x11, 0x7f, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x50, 0x15, 0x1d,
+  0x1d, 0x1b, 0x1c, 0xe5, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xe6, 0x0f, 0x21, 0x22, 0x22, 0x1a, 0x63, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xf2, 0xe3, 0xe7, 0xe7, 0xe7, 0xe5, 0xf9, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
+  0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
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+  0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
+  0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81,
+  0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80,
+  0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81,
+  0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x7f, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x81, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81,
+  0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x7f,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81,
+  0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
 };
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index abc97a377..6f47a1841 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -104,7 +104,9 @@ void tud_resume_cb(void)
 // USB Video
 //--------------------------------------------------------------------+
 static unsigned char const *frames[] = {
-  black_128x96_yuv, white_128x96_yuv, green_128x96_yuv
+  white_128x96_yuv, white_128x96_yuv, white_128x96_yuv,
+  t_128x96_yuv, ti_128x96_yuv, tin_128x96_yuv, logo_128x96_yuv,
+  logo_128x96_yuv, logo_128x96_yuv, logo_128x96_yuv, logo_128x96_yuv
 };
 static unsigned current_frame = 0;
 static unsigned tx_busy = 0;

From 0c89292a8dae9e5dad98a33ed3b66a4b5e796ff0 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 26 Sep 2021 21:52:56 +0900
Subject: [PATCH 0523/2085] Fix transfer failure when reconnecting

---
 .../device/video_capture/src/tusb_config.h    | 10 +--
 .../video_capture/src/usb_descriptors.c       |  6 +-
 src/class/video/video.h                       |  2 -
 src/class/video/video_device.c                | 79 +++++++++++--------
 4 files changed, 55 insertions(+), 42 deletions(-)

diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index fb194c55a..06a949b1c 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -90,12 +90,6 @@
 #define CFG_TUD_ENDPOINT0_SIZE    64
 #endif
 
-// video streaming endpoint size
-#define CFG_TUD_VIDEO_EP_BUFSIZE  256
-
-// The number of video streaming interfaces
-#define CFG_TUD_VIDEO_STREAMING  1
-
 //------------- CLASS -------------//
 #define CFG_TUD_CDC              0
 #define CFG_TUD_MSC              0
@@ -104,8 +98,12 @@
 #define CFG_TUD_AUDIO            0
 // The number of video control interfaces
 #define CFG_TUD_VIDEO            1
+// The number of video streaming interfaces
+#define CFG_TUD_VIDEO_STREAMING  1
 #define CFG_TUD_VENDOR           0
 
+// video streaming endpoint size
+#define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE  256
 
 //--------------------------------------------------------------------
 // APPLICATION CONFIGURATION
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index a9fa2c043..b0e41b97e 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -45,7 +45,7 @@ tusb_desc_device_t const desc_device =
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = 0x0200,
 
-    // Use Interface Association Descriptor (IAD) for CDC
+    // Use Interface Association Descriptor (IAD) for Video
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
     .bDeviceClass       = TUSB_CLASS_MISC,
     .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
@@ -104,7 +104,9 @@ uint8_t const desc_fs_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
   // IAD for Video Control
-  TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN, FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE, CFG_TUD_VIDEO_EP_BUFSIZE)
+  TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN,
+                               FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
+                               CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/src/class/video/video.h b/src/class/video/video.h
index c62706e5b..026857aad 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -418,8 +418,6 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
   _fmtidx, _numfrmdesc, TUD_VIDEO_GUID(_guid), \
   _bitsperpix, _frmidx, _asrx,  _asry, _interlace, _cp
 
-//  _g0,_g1,_g2,_g3,_g4,_g5,_g6,_g7,_g8,_g9,_g10,_g11,_g12,_g13,_g14,_g15,
-
 /* Uncompressed 3.1.2 Table 3-3 */
 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \
   TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 5b5d0b430..e820afbd4 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -28,7 +28,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_VIDEO)
+#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_VIDEO && CFG_TUD_VIDEO_STREAMING)
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
@@ -66,17 +66,17 @@ typedef struct TU_ATTR_PACKED {
   uint8_t index_vs;  /* index from the video control interface */
   uint8_t error_code;/* error code */
   struct {
-    uint16_t beg;    /* Offset of the beggining of video streaming interface descriptor */
+    uint16_t beg;    /* Offset of the begging of video streaming interface descriptor */
     uint16_t end;    /* Offset of the end of video streaming interface descriptor */
     uint16_t cur;    /* Offset of the current settings */
     uint16_t ep[2];  /* Offset of endpoint descriptors. 0: streaming, 1: still capture */
   } desc;
-  uint8_t  *buffer; /* frame buffer. assume linear buffer. no support for stride access */
-  uint32_t bufsize; /* frame buffer size */
-  uint32_t offset;  /* offset for the next payload transfer */
+  uint8_t *buffer;   /* frame buffer. assume linear buffer. no support for stride access */
+  uint32_t bufsize;  /* frame buffer size */
+  uint32_t offset;   /* offset for the next payload transfer */
   uint32_t max_payload_transfer_size;
   /*------------- From this point, data is not cleared by bus reset -------------*/
-  CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_EP_BUFSIZE]; /* EP transfer buffer for streaming */
+  CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE]; /* EP transfer buffer for streaming */
 } videod_streaming_interface_t;
 
 /* video control interface */
@@ -89,8 +89,7 @@ typedef struct TU_ATTR_PACKED {
   uint8_t power_mode;
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
-  // 
-  // CFG_TUSB_MEM_ALIGN uint8_t ctl_buf[64]; /* EP transfer buffer for control */
+  // CFG_TUSB_MEM_ALIGN uint8_t ctl_buf[64]; /* EP transfer buffer for interrupt transfer */
 
 } videod_interface_t;
 
@@ -115,7 +114,7 @@ static video_probe_and_commit_control_t const def_stm_settings = {
   .wCompWindowSize = 1, /* Maybe it is match to GOP size */
   .wDelay = 240, /* milliseconds */
   .dwMaxVideoFrameSize = FRAME_WIDTH * FRAME_HEIGHT * 12 / 8,
-  .dwMaxPayloadTransferSize = ((FRAME_WIDTH * FRAME_HEIGHT * 12 / 8 * 10) + 999) / 1000 + 2,
+  .dwMaxPayloadTransferSize = ((FRAME_WIDTH * FRAME_HEIGHT * 12 / 8 * FRAME_RATE) + 999) / 1000 + 2,
   .dwClockFrequency = 27000000, /* same as MPEG-2 system time clock  */
   .bmFramingInfo = 0x3,
   .bPreferedVersion = 1,
@@ -274,7 +273,7 @@ static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, uint_fast8_t
 
 /** Close current video control interface.
  *
- * @param[in,out] self     The context.
+ * @param[in,out] self     Video control interface context.
  * @param[in]     altnum   The target alternate setting number. */
 static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
 {
@@ -294,9 +293,9 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
   return true;
 }
 
-/** Set the specified alternate setting to own video control interface.
+/** Set the alternate setting to own video control interface.
  *
- * @param[in,out] self     The context.
+ * @param[in,out] self     Video control interface context.
  * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum)
 {
@@ -333,9 +332,9 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
   return true;
 }
 
-/** Set the specified alternate setting to own video control interface.
+/** Set the alternate setting to own video streaming interface.
  *
- * @param[in,out] self     The context.
+ * @param[in,out] stm      Streaming interface context.
  * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum)
 {
@@ -374,6 +373,10 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
   tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
   hdr->bHeaderLength = sizeof(*hdr);
   hdr->bmHeaderInfo  = 0;
+  /* clear transfer management information */
+  stm->buffer  = NULL;
+  stm->bufsize = 0;
+  stm->offset  = 0;
 
   return true;
 }
@@ -398,13 +401,15 @@ static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm)
 }
 
 /** Handle a standard request to the video control interface. */
-static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
+static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage,
+                                    tusb_control_request_t const *request,
+                                    uint_fast8_t ctl_idx)
 {
   switch (request->bRequest) {
   case TUSB_REQ_GET_INTERFACE:
     if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
     TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
-    tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[itf]);
+    tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[ctl_idx]);
     if (!vc) return VIDEO_UNKNOWN;
     if (tud_control_xfer(rhport, request,
                          (void*)&vc->std.bAlternateSetting,
@@ -414,9 +419,9 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_
   case TUSB_REQ_SET_INTERFACE:
     if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
     TU_VERIFY(0 == request->wLength, VIDEO_UNKNOWN);
-    if (!_close_vc_itf(rhport, &_videod_itf[itf]))
+    if (!_close_vc_itf(rhport, &_videod_itf[ctl_idx]))
       return VIDEO_UNKNOWN;
-    if (!_open_vc_itf(rhport, &_videod_itf[itf], request->wValue))
+    if (!_open_vc_itf(rhport, &_videod_itf[ctl_idx], request->wValue))
       return VIDEO_UNKNOWN;
     tud_control_status(rhport, request);
     return VIDEO_NO_ERROR;
@@ -426,9 +431,11 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage, tusb_control_
   }
 }
 
-static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
+static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage,
+                                   tusb_control_request_t const *request,
+                                   uint_fast8_t ctl_idx)
 {
-  videod_interface_t *self = &_videod_itf[itf];
+  videod_interface_t *self = &_videod_itf[ctl_idx];
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
   case VIDEO_VC_CTL_VIDEO_POWER_MODE:
@@ -440,7 +447,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
           return VIDEO_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
         if (tud_video_power_mode_cb)
-          return tud_video_power_mode_cb(itf, self->power_mode);
+          return tud_video_power_mode_cb(ctl_idx, self->power_mode);
       }
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
@@ -480,18 +487,20 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
   return VIDEO_INVALID_REQUEST;
 }
 
-static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
+static int handle_video_ctl_req(uint8_t rhport, uint8_t stage,
+                                tusb_control_request_t const *request,
+                                uint_fast8_t ctl_idx)
 {
   uint_fast8_t entity_id;
   switch (request->bmRequestType_bit.type) {
   case TUSB_REQ_TYPE_STANDARD:
-    return handle_video_ctl_std_req(rhport, stage, request, itf);
+    return handle_video_ctl_std_req(rhport, stage, request, ctl_idx);
   case TUSB_REQ_TYPE_CLASS:
     entity_id = TU_U16_HIGH(request->wIndex);
     if (!entity_id) {
-      return handle_video_ctl_cs_req(rhport, stage, request, itf);
+      return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx);
     } else {
-      if (!_find_desc_entity(_get_desc_vc(&_videod_itf[itf]), entity_id))
+      if (!_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id))
         return VIDEO_INVALID_REQUEST;
       return VIDEO_INVALID_REQUEST;
     }
@@ -500,9 +509,11 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_requ
   }
 }
 
-static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
+static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage,
+                                    tusb_control_request_t const *request,
+                                    uint_fast8_t stm_idx)
 {
-  videod_streaming_interface_t *self = &_videod_streaming_itf[itf];
+  videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx];
   switch (request->bRequest) {
   case TUSB_REQ_GET_INTERFACE:
     if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
@@ -526,10 +537,12 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage, tusb_control_
   }
 }
 
-static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
+static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
+                                   tusb_control_request_t const *request,
+                                   uint_fast8_t stm_idx)
 {
   (void)rhport;
-  videod_streaming_interface_t *self = &_videod_streaming_itf[itf];
+  videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx];
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
   case VIDEO_VS_CTL_STREAM_ERROR_CODE:
@@ -641,15 +654,17 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage, tusb_control_r
   return VIDEO_INVALID_REQUEST;
 }
 
-static int handle_video_stm_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request, uint_fast8_t itf)
+static int handle_video_stm_req(uint8_t rhport, uint8_t stage,
+                                tusb_control_request_t const *request,
+                                uint_fast8_t stm_idx)
 {
   switch (request->bmRequestType_bit.type) {
   case TUSB_REQ_TYPE_STANDARD:
-    return handle_video_stm_std_req(rhport, stage, request, itf);
+    return handle_video_stm_std_req(rhport, stage, request, stm_idx);
   case TUSB_REQ_TYPE_CLASS:
     if (TU_U16_HIGH(request->wIndex))
       return VIDEO_INVALID_REQUEST;
-    return handle_video_stm_cs_req(rhport, stage, request, itf);
+    return handle_video_stm_cs_req(rhport, stage, request, stm_idx);
   default:
     return VIDEO_INVALID_REQUEST;
   }

From dba5e7b17d4f39c9f74b90142a2e17056f4db6d7 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 29 Sep 2021 01:18:33 +0900
Subject: [PATCH 0524/2085] Implement negotiation process for streaming
 parameters

---
 src/class/video/video.h        |  25 +--
 src/class/video/video_device.c | 305 ++++++++++++++++++++++++++-------
 src/class/video/video_device.h |   7 +-
 3 files changed, 257 insertions(+), 80 deletions(-)

diff --git a/src/class/video/video.h b/src/class/video/video.h
index 026857aad..3c27c8093 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -282,18 +282,19 @@ typedef struct TU_ATTR_PACKED {
 } tusb_desc_cs_video_fmt_uncompressed_t;
 
 typedef struct TU_ATTR_PACKED {
-  uint8_t bLength;
-  uint8_t bDescriptorType;
-  uint8_t bDescriptorSubType;
-  uint8_t bFrameIndex;
-  uint8_t bNumFrameDescriptors;
-  uint8_t guidFormat[16];
-  uint8_t bBitsPerPixel;
-  uint8_t bDefaultFrameIndex;
-  uint8_t bAspectRatioX;
-  uint8_t bAspectRatioY;
-  uint8_t bmInterlaceFlags;
-  uint8_t bCopyProtect;
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bFrameIndex;
+  uint8_t  bmCapabilities;
+  uint16_t wWidth;
+  uint16_t wHeight;
+  uint32_t dwMinBitRate;
+  uint32_t dwMaxBitRate;
+  uint32_t dwMaxVideoFrameBufferSize; /* deprecated */
+  uint32_t dwDefaultFrameInterval;
+  uint8_t  bFrameIntervalType;
+  uint32_t dwFrameInterval[];
 } tusb_desc_cs_video_frm_uncompressed_t;
 
 //--------------------------------------------------------------------+
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index e820afbd4..f4ecef446 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -64,7 +64,6 @@ typedef struct TU_ATTR_PACKED {
 typedef struct TU_ATTR_PACKED {
   uint8_t index_vc;  /* index of bound video control interface */
   uint8_t index_vs;  /* index from the video control interface */
-  uint8_t error_code;/* error code */
   struct {
     uint16_t beg;    /* Offset of the begging of video streaming interface descriptor */
     uint16_t end;    /* Offset of the end of video streaming interface descriptor */
@@ -75,6 +74,7 @@ typedef struct TU_ATTR_PACKED {
   uint32_t bufsize;  /* frame buffer size */
   uint32_t offset;   /* offset for the next payload transfer */
   uint32_t max_payload_transfer_size;
+  uint8_t  error_code;/* error code */
   /*------------- From this point, data is not cleared by bus reset -------------*/
   CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE]; /* EP transfer buffer for streaming */
 } videod_streaming_interface_t;
@@ -103,30 +103,6 @@ CFG_TUSB_MEM_SECTION static videod_streaming_interface_t _videod_streaming_itf[C
 
 static uint8_t const _cap_get     = 0x1u; /* support for GET */
 static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
-static video_probe_and_commit_control_t const def_stm_settings = {
-  .bmHint = 0,
-  .bFormatIndex = 1,
-  .bFrameIndex = 1,
-  .dwFrameInterval = (10000000/FRAME_RATE),
-  .wKeyFrameRate = 1,
-  .wPFrameRate = 0,
-  .wCompQuality = 1, /* 1 to 10000 */
-  .wCompWindowSize = 1, /* Maybe it is match to GOP size */
-  .wDelay = 240, /* milliseconds */
-  .dwMaxVideoFrameSize = FRAME_WIDTH * FRAME_HEIGHT * 12 / 8,
-  .dwMaxPayloadTransferSize = ((FRAME_WIDTH * FRAME_HEIGHT * 12 / 8 * FRAME_RATE) + 999) / 1000 + 2,
-  .dwClockFrequency = 27000000, /* same as MPEG-2 system time clock  */
-  .bmFramingInfo = 0x3,
-  .bPreferedVersion = 1,
-  .bMinVersion = 1,
-  .bMaxVersion = 1,
-  .bUsage = 0,
-  .bBitDepthLuma = 8,
-  .bmSettings = 0,
-  .bMaxNumberOfRefFramesPlus1 = 0,
-  .bmRateControlModes = 0,
-  .bmLayoutPerStream = 0
-};
 
 /** Get interface number from the interface descriptor
  *
@@ -175,24 +151,49 @@ static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const
   return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur);
 }
 
-/** Find the first descriptor with the specified descriptor type.
+/** Find the first descriptor of a given type
  *
- * @param[in] beg     The head of descriptor byte array.
- * @param[in] end     The tail of descriptor byte array.
- * @param[in] target  The target descriptor type.
+ * @param[in] beg        The head of descriptor byte array.
+ * @param[in] end        The tail of descriptor byte array.
+ * @param[in] desc_type  The target descriptor type.
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _find_desc(void const *beg, void const *end, uint8_t target)
+static void const* _find_desc(void const *beg, void const *end, uint_fast8_t desc_type)
 {
   void const *cur = beg;
-  while ((cur < end) && (target != tu_desc_type(cur))) {
+  while ((cur < end) && (desc_type != tu_desc_type(cur))) {
     cur = tu_desc_next(cur);
   }
   return cur;
 }
 
-/** Return the next interface descriptor except alternate ones.
+/** Find the first descriptor specified by the arguments
+ *
+ * @param[in] beg        The head of descriptor byte array.
+ * @param[in] end        The tail of descriptor byte array.
+ * @param[in] desc_type  The target descriptor type
+ * @param[in] element_0  The target element following the desc_type
+ * @param[in] element_1  The target element following the element_0
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* _find_desc_3(void const *beg, void const *end,
+                                uint_fast8_t desc_type,
+                                uint_fast8_t element_0,
+                                uint_fast8_t element_1)
+{
+  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) {
+    uint8_t const *p = (uint8_t const *)cur;
+    if ((p[2] == element_0) && (p[3] == element_1)) {
+      return cur;
+    }
+    cur = tu_desc_next(cur);
+  }
+  return end;
+}
+
+/** Return the next interface descriptor which has another interface number.
  *
  * @param[in] beg     The head of descriptor byte array.
  * @param[in] end     The tail of descriptor byte array.
@@ -219,19 +220,14 @@ static void const* _next_desc_itf(void const *beg, void const *end)
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum)
+static inline void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum)
 {
-  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_INTERFACE)) {
-    tusb_desc_interface_t const *itf = (tusb_desc_interface_t const *)cur;
-    if (itf->bInterfaceNumber == itfnum && itf->bAlternateSetting == altnum) {
-      return itf;
-    }
-    cur = tu_desc_next(cur);
-  }
-  return end;
+  return _find_desc_3(beg, end, TUSB_DESC_INTERFACE, itfnum, altnum);
 }
 
-/** Find the first endpoint descriptor in front of the next interface descriptor.
+/** Find the first endpoint descriptor belonging to the current interface descriptor.
+ *
+ * The search range is from `beg` to `end` or the next interface descriptor.
  *
  * @param[in] beg     The head of descriptor byte array.
  * @param[in] end     The tail of descriptor byte array.
@@ -248,16 +244,18 @@ static void const* _find_desc_ep(void const *beg, void const *end)
   return end;
 }
 
-/** Find the first entity descriptor with the specified entity ID in the video control interface descriptor.
+/** Find the first entity descriptor with the entity ID
+ *  specified by the argument belonging to the current video control descriptor.
  *
- * @param[in] vc        The video control interface descriptor.
+ * @param[in] desc      The video control interface descriptor.
  * @param[in] entityid  The target entity id.
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, uint_fast8_t entityid)
+static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid)
 {
-  void const *beg = (void const*)vc;
+  tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const*)desc;
+  void const *beg = vc;
   void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength;
   for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
     tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
@@ -271,6 +269,153 @@ static void const* _find_desc_entity(tusb_desc_vc_itf_t const *vc, uint_fast8_t
   return end;
 }
 
+/** Return the end of the video streaming descriptor. */
+static inline void const* _end_of_streaming_descriptor(void const *desc)
+{
+  tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)desc;
+  return desc + vs->std.bLength + vs->stm.wTotalLength;
+}
+
+/** Find the first format descriptor with the specified format number. */
+static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum)
+{
+  return (tusb_desc_cs_video_fmt_uncompressed_t const*)
+    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, fmtnum);
+}
+
+/** Find the first frame descriptor with the specified format number. */
+static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum)
+{
+  return (tusb_desc_cs_video_frm_uncompressed_t const*)
+    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, frmnum);
+}
+
+static bool _update_streaming_parameters(videod_streaming_interface_t const *stm,
+                                         video_probe_and_commit_control_t *param)
+{
+  tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
+  uint_fast8_t fmtnum = param->bFormatIndex;
+  TU_ASSERT(fmtnum <= vs->stm.bNumFormats);
+  if (!fmtnum) {
+    if (1 < vs->stm.bNumFormats)
+      return true; /* Need to negotiate all variables. */
+    fmtnum = 1;
+    param->bFormatIndex = 1;
+  }
+
+  /* Set the parameters determined by the format  */
+  param->wKeyFrameRate    = 1;
+  param->wPFrameRate      = 0;
+  param->wCompQuality     = 1; /* 1 to 10000 */
+  param->wCompWindowSize  = 1; /* GOP size? */
+  param->wDelay           = 0; /* milliseconds */
+  param->dwClockFrequency = 27000000; /* same as MPEG-2 system time clock  */
+  param->bmFramingInfo    = 0x3; /* enables FrameID and EndOfFrame */
+  param->bPreferedVersion = 1;
+  param->bMinVersion      = 1;
+  param->bMaxVersion      = 1;
+  param->bUsage           = 0;
+  param->bBitDepthLuma    = 8;
+
+  void const *end = _end_of_streaming_descriptor(vs);
+  tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
+  TU_ASSERT(fmt != end);
+  uint_fast8_t frmnum = param->bFrameIndex;
+  TU_ASSERT(frmnum <= fmt->bNumFrameDescriptors);
+  if (!frmnum) {
+    if (1 < fmt->bNumFrameDescriptors)
+      return true;
+    frmnum = 1;
+    param->bFrameIndex = 1;
+  }
+  tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
+  TU_ASSERT(frm != end);
+
+  /* Set the parameters determined by the frame  */
+  uint_fast32_t frame_size = param->dwMaxVideoFrameSize;
+  if (!frame_size) {
+    frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->bBitsPerPixel / 8;
+    param->dwMaxVideoFrameSize = frame_size;
+  }
+
+  uint_fast32_t interval = param->dwFrameInterval;
+  if (!interval) {
+    if ((1 < frm->bFrameIntervalType) ||
+        ((0 == frm->bFrameIntervalType) && (frm->dwFrameInterval[1] != frm->dwFrameInterval[0])))
+      return true;
+    interval = frm->dwFrameInterval[0];
+    param->dwFrameInterval = interval;
+  }
+  uint_fast32_t interval_ms = interval / 10000;
+  TU_ASSERT(interval_ms);
+  uint_fast32_t payload_size = (frame_size + interval_ms - 1) / interval_ms + 2;
+  param->dwMaxPayloadTransferSize = payload_size;
+  return true;
+}
+
+static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *stm, bool set_max,
+                                            video_probe_and_commit_control_t *param)
+{
+  uint_fast8_t const fmtnum = param->bFormatIndex;
+  if (!fmtnum) {
+    if (set_max) {
+      tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
+      param->bFormatIndex   = vs->stm.bNumFormats;
+    } else {
+      param->bFormatIndex   = 1;
+    }
+    /* Set the parameters determined by the format  */
+    param->wKeyFrameRate    = 1;
+    param->wPFrameRate      = 0;
+    param->wCompQuality     = 1; /* 1 to 10000 */
+    param->wCompWindowSize  = 1; /* GOP size? */
+    param->wDelay           = 0; /* milliseconds */
+    param->dwClockFrequency = 27000000; /* same as MPEG-2 system time clock  */
+    param->bmFramingInfo    = 0x3; /* enables FrameID and EndOfFrame */
+    param->bPreferedVersion = 1;
+    param->bMinVersion      = 1;
+    param->bMaxVersion      = 1;
+    param->bUsage           = 0;
+    param->bBitDepthLuma    = 8;
+    return true;
+  }
+
+  uint_fast8_t frmnum = param->bFrameIndex;
+  if (!frmnum) {
+    tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
+    void const *end = _end_of_streaming_descriptor(vs);
+    tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
+    frmnum = set_max ? fmt->bNumFrameDescriptors: 1;
+    param->bFrameIndex = frmnum;
+    /* Set the parameters determined by the frame */
+    tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
+    param->dwMaxVideoFrameSize = frm->wWidth * frm->wHeight * fmt->bBitsPerPixel / 8;
+    return true;
+  }
+
+  if (!param->dwFrameInterval) {
+    tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
+    void const *end = _end_of_streaming_descriptor(vs);
+    tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
+    tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
+
+    uint_fast32_t interval;
+    uint_fast8_t num_intervals = frm->bFrameIntervalType;
+    if (!num_intervals) {
+      interval = set_max ? frm->dwFrameInterval[1]: frm->dwFrameInterval[0];
+    } else {
+      interval = set_max ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[0];
+    }
+    param->dwFrameInterval = interval;
+    uint_fast32_t interval_ms = interval / 10000;
+    TU_ASSERT(interval_ms);
+    uint_fast32_t frame_size = param->dwMaxVideoFrameSize;
+    param->dwMaxPayloadTransferSize = (frame_size + interval_ms - 1) / interval_ms + 2;
+    return true;
+  }
+  return true;
+}
+
 /** Close current video control interface.
  *
  * @param[in,out] self     Video control interface context.
@@ -351,6 +496,10 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     stm->desc.ep[i] = 0;
     TU_LOG2("    close EP%02x\n", ep_adr);
   }
+  /* clear transfer management information */
+  stm->buffer  = NULL;
+  stm->bufsize = 0;
+  stm->offset  = 0;
 
   /* Find a alternate interface */
   void const *beg = desc + stm->desc.beg;
@@ -360,23 +509,38 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
   uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints;
   TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep));
   stm->desc.cur = cur - desc; /* Save the offset of the new settings */
+  if (!altnum) {
+    /* initialize streaming settings */
+    stm->max_payload_transfer_size = 0;
+    video_probe_and_commit_control_t *param =
+      (video_probe_and_commit_control_t *)&stm->ep_buf;
+    return _update_streaming_parameters(stm, param);
+  }
   /* Open endpoints of the new settings. */
   for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) {
     cur = _find_desc_ep(cur, end);
     TU_ASSERT(cur < end);
-    TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *)cur));
+    tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur;
+    if (!stm->max_payload_transfer_size) {
+      video_probe_and_commit_control_t const *param =
+        (video_probe_and_commit_control_t const*)&stm->ep_buf;
+      uint_fast32_t max_size = param->dwMaxPayloadTransferSize;
+      if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) &&
+          (ep->wMaxPacketSize.size < max_size)) {
+        /* FS must be less than or equal to max packet size */
+        return false;
+      }
+      /* Set the negotiated value */
+      stm->max_payload_transfer_size = max_size;
+    }
+    TU_ASSERT(usbd_edpt_open(rhport, ep));
     stm->desc.ep[i] = cur - desc;
-    stm->max_payload_transfer_size = def_stm_settings.dwMaxPayloadTransferSize;
     TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
   }
   /* initialize payload header */
   tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
   hdr->bHeaderLength = sizeof(*hdr);
   hdr->bmHeaderInfo  = 0;
-  /* clear transfer management information */
-  stm->buffer  = NULL;
-  stm->bufsize = 0;
-  stm->offset  = 0;
 
   return true;
 }
@@ -569,32 +733,40 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
         if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
           return VIDEO_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
-        if (tud_video_probe_set_cb)
-          return tud_video_probe_set_cb(self->index_vc, self->index_vs,
-                                        (video_probe_and_commit_control_t const*)self->ep_buf);
+        if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf))
+          return VIDEO_INVALID_VALUE_WITHIN_RANGE;
       }
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
       TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
-      if (tud_control_xfer(rhport, request, (void*)&def_stm_settings,
-                           sizeof(video_probe_and_commit_control_t)))
+      if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
         return VIDEO_NO_ERROR;
       return VIDEO_UNKNOWN;
-    case VIDEO_REQUEST_GET_MIN:
+    case VIDEO_REQUEST_GET_MIN: {
+      video_probe_and_commit_control_t tmp;
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
       TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
-      if (tud_control_xfer(rhport, request, (void*)&def_stm_settings,
+      tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
+      if (!_negotiate_streaming_parameters(self, false, &tmp))
+        return VIDEO_INVALID_VALUE_WITHIN_RANGE;
+      if (tud_control_xfer(rhport, request, &tmp,
                            sizeof(video_probe_and_commit_control_t)))
         return VIDEO_NO_ERROR;
       return VIDEO_UNKNOWN;
-    case VIDEO_REQUEST_GET_MAX:
+    }
+    case VIDEO_REQUEST_GET_MAX: {
+      video_probe_and_commit_control_t tmp;
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
       TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
-      if (tud_control_xfer(rhport, request, (void*)&def_stm_settings,
+      tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
+      if (!_negotiate_streaming_parameters(self, true, &tmp))
+        return VIDEO_INVALID_VALUE_WITHIN_RANGE;
+      if (tud_control_xfer(rhport, request, self->ep_buf,
                            sizeof(video_probe_and_commit_control_t)))
         return VIDEO_NO_ERROR;
       return VIDEO_UNKNOWN;
+    }
     case VIDEO_REQUEST_GET_RES:
       return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_DEF:
@@ -618,16 +790,17 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
         if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
           return VIDEO_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
-        if (tud_video_commit_set_cb)
-          return tud_video_commit_set_cb(self->index_vc, self->index_vs,
-                                         (video_probe_and_commit_control_t const*)self->ep_buf);
+        if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf))
+          return VIDEO_INVALID_VALUE_WITHIN_RANGE;
+        if (tud_video_commit_cb)
+          return tud_video_commit_cb(self->index_vc, self->index_vs,
+                                     (video_probe_and_commit_control_t*)self->ep_buf);
       }
       return VIDEO_NO_ERROR;
     case VIDEO_REQUEST_GET_CUR:
       if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
       TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
-      if (tud_control_xfer(rhport, request, (void*)&def_stm_settings,
-                           sizeof(video_probe_and_commit_control_t)))
+      if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
         return VIDEO_NO_ERROR;
       return VIDEO_UNKNOWN;
     case VIDEO_REQUEST_GET_INFO:
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index e6f53fed8..8654b63c5 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -61,8 +61,11 @@ TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fas
  * @return video_error_code_t */
 TU_ATTR_WEAK int tud_video_power_mode_cb(uint_fast8_t ctl_idx, uint8_t power_mod);
 
-/* @return video_error_code_t */
-TU_ATTR_WEAK int tud_video_probe_set_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *settings);
+/** 
+ *
+ * @return video_error_code_t */
+TU_ATTR_WEAK int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
+                                     video_probe_and_commit_control_t const *parameters);
 
 /* @return video_error_code_t */
 TU_ATTR_WEAK int tud_video_commit_set_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *settings);

From 9bcab53c2cb0b52baf8bc0c768887428ac87fbff Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 29 Sep 2021 22:53:26 +0900
Subject: [PATCH 0525/2085] Implement frame rate settings

---
 examples/device/video_capture/src/main.c      | 13 ++++++---
 .../video_capture/src/usb_descriptors.h       |  2 +-
 src/class/video/video_device.c                | 11 +++++++-
 src/class/video/video_device.h                | 27 ++++++++++++-------
 4 files changed, 38 insertions(+), 15 deletions(-)

diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 6f47a1841..a38791365 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -110,11 +110,11 @@ static unsigned char const *frames[] = {
 };
 static unsigned current_frame = 0;
 static unsigned tx_busy = 0;
+static unsigned interval_ms = 1000 / FRAME_RATE;
 
 void video_task(void)
 {
   static unsigned start_ms = 0;
-  static unsigned interval_ms = 1000 / FRAME_RATE;
   static unsigned already_sent = 0;
 
   if (!tud_video_n_streaming(0, 0)) {
@@ -137,7 +137,7 @@ void video_task(void)
   tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], FRAME_WIDTH * FRAME_HEIGHT * 12/8);
 }
 
-int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
+void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
 {
   (void)ctl_idx; (void)stm_idx;
   tx_busy = 0;
@@ -145,7 +145,14 @@ int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
   ++current_frame;
   if (current_frame == sizeof(frames)/sizeof(frames[0]))
     current_frame = 0;
-  return 0;
+}
+
+int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
+			video_probe_and_commit_control_t const *parameters)
+{
+  /* convert unit to ms from 100 ns */
+  interval_ms = parameters->dwFrameInterval / 10000;
+  return VIDEO_NO_ERROR;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 867e9af42..eff57f1fa 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -99,7 +99,7 @@ enum {
           TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
               _width * _height * 12, _width * _height * 12 * _fps, \
               _width * _height * 12, \
-              (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+              (10000000/_fps), (10000000/_fps), 10000000, 100000), \
           TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
     /* VS alt 1 */\
     TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index f4ecef446..28ac860e1 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -290,6 +290,9 @@ static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void
     _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, frmnum);
 }
 
+/** Set uniquely determined values to variables that have not been set
+ *
+ * @param[in,out] param       Target */
 static bool _update_streaming_parameters(videod_streaming_interface_t const *stm,
                                          video_probe_and_commit_control_t *param)
 {
@@ -353,6 +356,11 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   return true;
 }
 
+/** Set the minimum or the maximum values to variables which need to negotiate with the host
+ *
+ * @param[in]     set_max     If true, the maximum values is set, otherwise the minimum value is set.
+ * @param[in,out] param       Target
+ */
 static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *stm, bool set_max,
                                             video_probe_and_commit_control_t *param)
 {
@@ -514,6 +522,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     stm->max_payload_transfer_size = 0;
     video_probe_and_commit_control_t *param =
       (video_probe_and_commit_control_t *)&stm->ep_buf;
+    tu_memclr(param, sizeof(*param));
     return _update_streaming_parameters(stm, param);
   }
   /* Open endpoints of the new settings. */
@@ -880,7 +889,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
   if (!stm || !stm->desc.ep[0] || stm->buffer)
     return false;
 
-  /* find EP address */
+  /* Find EP address */
   void const *desc = _videod_itf[stm->index_vc].beg;
   uint_fast8_t ep_addr = 0;
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index 8654b63c5..e5012ca7e 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -43,32 +43,39 @@ extern "C" {
  * stm_idx       instance number of streaming interface */
 bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx);
 
-
-/* ctl_idx       instance number of control interface
- * stm_idx       instance number of streaming interface */
+/**
+ * @param[in] ctl_idx    Destination control interface index
+ * @param[in] stm_idx    Destination streaming interface index
+ * @param[in] buffer     Frame buffer. The caller must not use this buffer until the operation is completed.
+ * @param[in] bufsize    Byte size of the frame buffer */
 bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *buffer, size_t bufsize);
 
 /*------------- Optional callbacks -------------*/
-/* ctl_idx       instance number of control interface
- * stm_idx       instance number of streaming interface */
-TU_ATTR_WEAK int tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx);
+/** Invoked when compeletion of a frame transfer
+ *
+ * @param[in] ctl_idx    Destination control interface index
+ * @param[in] stm_idx    Destination streaming interface index */
+TU_ATTR_WEAK void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx);
 
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
 //--------------------------------------------------------------------+
 
-/* Invoked when SET POWER_MODE request received to 
+/** Invoked when SET_POWER_MODE request received
+ *
+ * @param[in] ctl_idx    Destination control interface index
+ * @param[in] stm_idx    Destination streaming interface index
  * @return video_error_code_t */
 TU_ATTR_WEAK int tud_video_power_mode_cb(uint_fast8_t ctl_idx, uint8_t power_mod);
 
-/** 
+/** Invoked when VS_COMMIT_CONTROL(SET_CUR) request received
  *
+ * @param[in] ctl_idx    Destination control interface index
+ * @param[in] stm_idx    Destination streaming interface index
  * @return video_error_code_t */
 TU_ATTR_WEAK int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
                                      video_probe_and_commit_control_t const *parameters);
 
-/* @return video_error_code_t */
-TU_ATTR_WEAK int tud_video_commit_set_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, video_probe_and_commit_control_t const *settings);
 //--------------------------------------------------------------------+
 // INTERNAL USBD-CLASS DRIVER API
 //--------------------------------------------------------------------+

From 4ca466b00b05d50ec338712f82a5b8b16ae7ce09 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 29 Sep 2021 22:59:46 +0900
Subject: [PATCH 0526/2085] Update comments

---
 src/class/video/video_device.c |  4 +---
 src/class/video/video_device.h | 15 ++++++++++-----
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 28ac860e1..12ccbd165 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -554,6 +554,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
   return true;
 }
 
+/** Prepare the next packet payload. */
 static uint_fast16_t _prepare_in_payload(videod_streaming_interface_t *stm)
 {
   uint_fast16_t remaining = stm->bufsize - stm->offset;
@@ -857,7 +858,6 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage,
 // APPLICATION API
 //--------------------------------------------------------------------+
 
-/* ctl_idx      instance number of video control interface */
 bool tud_video_n_connected(uint_fast8_t ctl_idx)
 {
   TU_ASSERT(ctl_idx < CFG_TUD_VIDEO);
@@ -867,8 +867,6 @@ bool tud_video_n_connected(uint_fast8_t ctl_idx)
   return false;
 }
 
-/* ctl_idx      instance number of video control interface
- * stm_idx      index number of streaming interface as per video control */
 bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
 {
   TU_ASSERT(ctl_idx < CFG_TUD_VIDEO);
diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h
index e5012ca7e..ee2fcb9d5 100644
--- a/src/class/video/video_device.h
+++ b/src/class/video/video_device.h
@@ -39,11 +39,15 @@ extern "C" {
 // Application API (Multiple Ports)
 // CFG_TUD_VIDEO > 1
 //--------------------------------------------------------------------+
-/* ctl_idx       instance number of control interface
- * stm_idx       instance number of streaming interface */
+
+/** Return true if streaming
+ *
+ * @param[in] ctl_idx    Destination control interface index
+ * @param[in] stm_idx    Destination streaming interface index */
 bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx);
 
-/**
+/** Transfer a frame
+ *
  * @param[in] ctl_idx    Destination control interface index
  * @param[in] stm_idx    Destination streaming interface index
  * @param[in] buffer     Frame buffer. The caller must not use this buffer until the operation is completed.
@@ -70,8 +74,9 @@ TU_ATTR_WEAK int tud_video_power_mode_cb(uint_fast8_t ctl_idx, uint8_t power_mod
 
 /** Invoked when VS_COMMIT_CONTROL(SET_CUR) request received
  *
- * @param[in] ctl_idx    Destination control interface index
- * @param[in] stm_idx    Destination streaming interface index
+ * @param[in] ctl_idx     Destination control interface index
+ * @param[in] stm_idx     Destination streaming interface index
+ * @param[in] parameters  Video streaming parameters
  * @return video_error_code_t */
 TU_ATTR_WEAK int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
                                      video_probe_and_commit_control_t const *parameters);

From 831443a2dce346cafab47a0a7f593e72fa33bfa4 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 30 Sep 2021 01:13:19 +0900
Subject: [PATCH 0527/2085] Move frame settings to usb_descriptors.h

---
 examples/device/video_capture/src/main.c            | 1 +
 examples/device/video_capture/src/tusb_config.h     | 8 --------
 examples/device/video_capture/src/usb_descriptors.h | 4 ++++
 3 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index a38791365..b24f01555 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -29,6 +29,7 @@
 
 #include "bsp/board.h"
 #include "tusb.h"
+#include "usb_descriptors.h"
 
 #include "images.h"
 //--------------------------------------------------------------------+
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index 06a949b1c..5d2d5470c 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -105,14 +105,6 @@
 // video streaming endpoint size
 #define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE  256
 
-//--------------------------------------------------------------------
-// APPLICATION CONFIGURATION
-//--------------------------------------------------------------------
-#define FRAME_WIDTH   128
-#define FRAME_HEIGHT  96
-#define FRAME_RATE    10
-
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index eff57f1fa..e52703b29 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -33,6 +33,10 @@
 #define UVC_ENTITY_CAP_INPUT_TERMINAL  0x01
 #define UVC_ENTITY_CAP_OUTPUT_TERMINAL 0x02
 
+#define FRAME_WIDTH   128
+#define FRAME_HEIGHT  96
+#define FRAME_RATE    10
+
 enum {
   ITF_NUM_VIDEO_CONTROL = 0,
   ITF_NUM_VIDEO_STREAMING,

From 9a7795464ea88a0d8c8001a42404f791d486af64 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 30 Sep 2021 21:08:57 +0900
Subject: [PATCH 0528/2085] Add cast operations to unused parameters

---
 examples/device/video_capture/src/main.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index b24f01555..b76af071a 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -151,6 +151,7 @@ void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx
 int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
 			video_probe_and_commit_control_t const *parameters)
 {
+  (void)ctl_idx; (void)stm_idx;
   /* convert unit to ms from 100 ns */
   interval_ms = parameters->dwFrameInterval / 10000;
   return VIDEO_NO_ERROR;

From 889e4103d9aa8f9a5b51cc01ec0dae2486e31b6b Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 30 Sep 2021 21:27:09 +0900
Subject: [PATCH 0529/2085] Add files to skip building for small ROM

---
 examples/device/video_capture/.skip.MCU_MSP430x5xx | 1 +
 examples/device/video_capture/.skip.MCU_SAMD11     | 0
 2 files changed, 1 insertion(+)
 create mode 100644 examples/device/video_capture/.skip.MCU_MSP430x5xx
 create mode 100644 examples/device/video_capture/.skip.MCU_SAMD11

diff --git a/examples/device/video_capture/.skip.MCU_MSP430x5xx b/examples/device/video_capture/.skip.MCU_MSP430x5xx
new file mode 100644
index 000000000..17600f062
--- /dev/null
+++ b/examples/device/video_capture/.skip.MCU_MSP430x5xx
@@ -0,0 +1 @@
+too many warnings for 16-bit integer overflow
diff --git a/examples/device/video_capture/.skip.MCU_SAMD11 b/examples/device/video_capture/.skip.MCU_SAMD11
new file mode 100644
index 000000000..e69de29bb

From 98e6a93a7807e67b5589b859c2871b9a36233e3d Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 30 Sep 2021 21:38:27 +0900
Subject: [PATCH 0530/2085] Add a list file for rp2040

---
 examples/device/video_capture/CMakeLists.txt | 28 ++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 examples/device/video_capture/CMakeLists.txt

diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt
new file mode 100644
index 000000000..cb321f9a8
--- /dev/null
+++ b/examples/device/video_capture/CMakeLists.txt
@@ -0,0 +1,28 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+)
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+)
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
\ No newline at end of file

From 2800a6a5830e721baffdf95e4fe6cd1475771582 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 30 Sep 2021 21:46:16 +0900
Subject: [PATCH 0531/2085] Add a file to skip bluepill

---
 examples/device/video_capture/.skip.MCU_STM32F1 | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 examples/device/video_capture/.skip.MCU_STM32F1

diff --git a/examples/device/video_capture/.skip.MCU_STM32F1 b/examples/device/video_capture/.skip.MCU_STM32F1
new file mode 100644
index 000000000..e69de29bb

From 7708997a679f61b2ea8fdc7bec880cd19ecaa28f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 30 Sep 2021 20:14:23 +0700
Subject: [PATCH 0532/2085] change scsis status to phase error when total_bytes
 < block_count

---
 src/class/msc/msc_device.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index b65abe979..87ebe227f 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -182,15 +182,15 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
       TU_LOG(MSC_DEBUG, "  SCSI case 8 (Hi <> Do)\r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
     }
-    else if ( !block_count )
+    else if ( 0 == block_count )
     {
-      TU_LOG(MSC_DEBUG, "  SCSI case 4 Hi > Dn\r\n");
+      TU_LOG(MSC_DEBUG, "  SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n");
       status =  MSC_CSW_STATUS_FAILED;
     }
-    else if ( SCSI_CMD_READ_10 == cbw->command[0] && cbw->total_bytes / block_count == 0)
+    else if ( cbw->total_bytes / block_count == 0 )
     {
-      TU_LOG(MSC_DEBUG, " Computed block size 0\r\n");
-      status = MSC_CSW_STATUS_FAILED;
+      TU_LOG(MSC_DEBUG, " Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n");
+      status = MSC_CSW_STATUS_PHASE_ERROR;
     }
   }
 

From a1788da4105b762e919dee0e1f2141288751e7b8 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 30 Sep 2021 22:14:29 +0900
Subject: [PATCH 0533/2085] Add video class entry to rp2040 building scripts

---
 examples/device/CMakeLists.txt | 1 +
 hw/bsp/rp2040/family.cmake     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index a0e4600f6..edf5ab805 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -24,4 +24,5 @@ family_add_subdirectory(msc_dual_lun)
 family_add_subdirectory(net_lwip_webserver)
 family_add_subdirectory(uac2_headset)
 family_add_subdirectory(usbtmc)
+family_add_subdirectory(video_capture)
 family_add_subdirectory(webusb_serial)
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 41960b6cd..10c103a9e 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -73,6 +73,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/class/net/net_device.c
 			${TOP}/src/class/usbtmc/usbtmc_device.c
 			${TOP}/src/class/vendor/vendor_device.c
+			${TOP}/src/class/video/video_device.c
 			)
 
 

From 0932d502c78796762a7d4ec7ee709707ede83dc8 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Thu, 30 Sep 2021 14:50:38 -0700
Subject: [PATCH 0534/2085] remove bcm files

---
 hw/mcu/broadcom/bcm2711/boot.s       | 172 ---------------------------
 hw/mcu/broadcom/bcm2711/interrupts.c |  26 ----
 hw/mcu/broadcom/bcm2711/interrupts.h |   8 --
 hw/mcu/broadcom/bcm2711/io.c         | 170 --------------------------
 hw/mcu/broadcom/bcm2711/io.h         |  13 --
 hw/mcu/broadcom/bcm2711/link.ld      |  28 -----
 hw/mcu/broadcom/bcm2711/mmu.c        |  62 ----------
 hw/mcu/broadcom/bcm2711/mmu.h        |  45 -------
 8 files changed, 524 deletions(-)
 delete mode 100644 hw/mcu/broadcom/bcm2711/boot.s
 delete mode 100644 hw/mcu/broadcom/bcm2711/interrupts.c
 delete mode 100644 hw/mcu/broadcom/bcm2711/interrupts.h
 delete mode 100644 hw/mcu/broadcom/bcm2711/io.c
 delete mode 100644 hw/mcu/broadcom/bcm2711/io.h
 delete mode 100644 hw/mcu/broadcom/bcm2711/link.ld
 delete mode 100644 hw/mcu/broadcom/bcm2711/mmu.c
 delete mode 100644 hw/mcu/broadcom/bcm2711/mmu.h

diff --git a/hw/mcu/broadcom/bcm2711/boot.s b/hw/mcu/broadcom/bcm2711/boot.s
deleted file mode 100644
index dcc588924..000000000
--- a/hw/mcu/broadcom/bcm2711/boot.s
+++ /dev/null
@@ -1,172 +0,0 @@
-.section ".text.boot"  // Make sure the linker puts this at the start of the kernel image
-
-.global _start  // Execution starts here
-
-_start:
-    // Check processor ID is zero (executing on main core), else hang
-    mrs     x1, mpidr_el1
-    and     x1, x1, #3
-    cbz     x1, 2f
-    // We're not on the main core, so hang in an infinite wait loop
-1:  wfe
-    b       1b
-2:  // We're on the main core!
-
-    // Set stack to start below our code
-    ldr     x1, =_start
-    mov     sp, x1
-
-    adr    x0, vectors        // load VBAR_EL1 with virtual
-    // msr    vbar_el3, x0        // vector table address
-    msr    vbar_el1, x0        // vector table address
-    msr    vbar_el2, x0        // vector table address
-    isb
-
-    // Clean the BSS section
-    ldr     x1, =__bss_start     // Start address
-    ldr     w2, =__bss_size      // Size of the section
-3:  cbz     w2, 4f               // Quit loop if zero
-    str     xzr, [x1], #8
-    sub     w2, w2, #1
-    cbnz    w2, 3b               // Loop if non-zero
-
-    // Jump to our main() routine in C (make sure it doesn't return)
-4:  bl      main
-    // In case it does return, halt the master core too
-    b       1b
-
-.macro  ventry  label
-.align  7
-b   \label
-.endm
-
-.macro handle_invalid_entry type
-irq_entry
-mov x0, #\type
-mrs x1, esr_el1
-mrs x2, elr_el1
-mrs x3, esr_el2
-mrs x4, elr_el2
-b   err_hang
-.endm
-
-.macro  irq_entry
-sub sp, sp, #272
-stp x0, x1, [sp, #16 * 0]
-stp x2, x3, [sp, #16 * 1]
-stp x4, x5, [sp, #16 * 2]
-stp x6, x7, [sp, #16 * 3]
-stp x8, x9, [sp, #16 * 4]
-stp x10, x11, [sp, #16 * 5]
-stp x12, x13, [sp, #16 * 6]
-stp x14, x15, [sp, #16 * 7]
-stp x16, x17, [sp, #16 * 8]
-stp x18, x19, [sp, #16 * 9]
-stp x20, x21, [sp, #16 * 10]
-stp x22, x23, [sp, #16 * 11]
-stp x24, x25, [sp, #16 * 12]
-stp x26, x27, [sp, #16 * 13]
-stp x28, x29, [sp, #16 * 14]
-str x30, [sp, #16 * 15] 
-.endm
-
-.macro  irq_exit
-ldp x0, x1, [sp, #16 * 0]
-ldp x2, x3, [sp, #16 * 1]
-ldp x4, x5, [sp, #16 * 2]
-ldp x6, x7, [sp, #16 * 3]
-ldp x8, x9, [sp, #16 * 4]
-ldp x10, x11, [sp, #16 * 5]
-ldp x12, x13, [sp, #16 * 6]
-ldp x14, x15, [sp, #16 * 7]
-ldp x16, x17, [sp, #16 * 8]
-ldp x18, x19, [sp, #16 * 9]
-ldp x20, x21, [sp, #16 * 10]
-ldp x22, x23, [sp, #16 * 11]
-ldp x24, x25, [sp, #16 * 12]
-ldp x26, x27, [sp, #16 * 13]
-ldp x28, x29, [sp, #16 * 14]
-ldr x30, [sp, #16 * 15] 
-add sp, sp, #272       
-eret
-.endm
-
-
-/*
- * Exception vectors.
- */
-.align  11
-.globl vectors 
-vectors:
-    ventry  sync_invalid_el1t           // Synchronous EL1t
-    ventry  irq_invalid_el1t            // IRQ EL1t
-    ventry  fiq_invalid_el1t            // FIQ EL1t
-    ventry  error_invalid_el1t          // Error EL1t
-
-    ventry  sync_invalid_el1h           // Synchronous EL1h
-    ventry  el1_irq                 // IRQ EL1h
-    ventry  fiq_invalid_el1h            // FIQ EL1h
-    ventry  error_invalid_el1h          // Error EL1h
-
-    ventry  sync_invalid_el0_64         // Synchronous 64-bit EL0
-    ventry  irq_invalid_el0_64          // IRQ 64-bit EL0
-    ventry  fiq_invalid_el0_64          // FIQ 64-bit EL0
-    ventry  error_invalid_el0_64            // Error 64-bit EL0
-
-    ventry  sync_invalid_el0_32         // Synchronous 32-bit EL0
-    ventry  irq_invalid_el0_32          // IRQ 32-bit EL0
-    ventry  fiq_invalid_el0_32          // FIQ 32-bit EL0
-    ventry  error_invalid_el0_32            // Error 32-bit EL0
-
-sync_invalid_el1t:
-    handle_invalid_entry  0
-
-irq_invalid_el1t:
-    handle_invalid_entry  1
-
-fiq_invalid_el1t:
-    handle_invalid_entry  2
-
-error_invalid_el1t:
-    handle_invalid_entry  3
-
-sync_invalid_el1h:
-    handle_invalid_entry  4
-
-fiq_invalid_el1h:
-    handle_invalid_entry  5
-
-error_invalid_el1h:
-    handle_invalid_entry  6
-
-sync_invalid_el0_64:
-    handle_invalid_entry  7
-
-irq_invalid_el0_64:
-    handle_invalid_entry  8
-
-fiq_invalid_el0_64:
-    handle_invalid_entry  9
-
-error_invalid_el0_64:
-    handle_invalid_entry  10
-
-sync_invalid_el0_32:
-    handle_invalid_entry  11
-
-irq_invalid_el0_32:
-    handle_invalid_entry  12
-
-fiq_invalid_el0_32:
-    handle_invalid_entry  13
-
-error_invalid_el0_32:
-    handle_invalid_entry  14
-
-el1_irq:
-    irq_entry 
-    bl  handle_irq
-    irq_exit 
-
-.globl err_hang
-err_hang: b err_hang
diff --git a/hw/mcu/broadcom/bcm2711/interrupts.c b/hw/mcu/broadcom/bcm2711/interrupts.c
deleted file mode 100644
index cb5607526..000000000
--- a/hw/mcu/broadcom/bcm2711/interrupts.c
+++ /dev/null
@@ -1,26 +0,0 @@
-#include <stdbool.h>
-#include <stdint.h>
-
-void disable_async_interrupts(void) {
-    
-}
-
-void enable_async_interrupts(void) {
-    
-}
-
-void Default_Handler(void) {
-    while (true) {}
-}
-
-__attribute__((weak)) void handle_irq(void) {
-    unsigned int irq = *((volatile uint32_t*) 0x3F00B204);
-    switch (irq) {
-        // case (SYSTEM_TIMER_IRQ_1):
-        //     handle_timer_irq();
-        //     break;
-        default:
-            // printf("Unknown pending irq: %x\r\n", irq);
-            Default_Handler();
-    }
-}
\ No newline at end of file
diff --git a/hw/mcu/broadcom/bcm2711/interrupts.h b/hw/mcu/broadcom/bcm2711/interrupts.h
deleted file mode 100644
index 5f36d6daa..000000000
--- a/hw/mcu/broadcom/bcm2711/interrupts.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#pragma once
-
-void disable_async_interrupts(void);
-void enable_async_interrupts(void);
-
-#define GIC_BASE 0x4c0040000
-#define NUM_CPUS 4
-#define NUM_SPIS 192
diff --git a/hw/mcu/broadcom/bcm2711/io.c b/hw/mcu/broadcom/bcm2711/io.c
deleted file mode 100644
index 8ccfdc692..000000000
--- a/hw/mcu/broadcom/bcm2711/io.c
+++ /dev/null
@@ -1,170 +0,0 @@
-// From: https://github.com/isometimes/rpi4-osdev/blob/master/part4-miniuart/io.c
-// CC-0 License
-
-// GPIO
-
-// Pi 4 base address: 0xFE000000
-// Pi 3 base address: 0x3F000000
-enum {
-    PERIPHERAL_BASE = 0xFE000000,
-    GPFSEL0         = PERIPHERAL_BASE + 0x200000,
-    GPSET0          = PERIPHERAL_BASE + 0x20001C,
-    GPCLR0          = PERIPHERAL_BASE + 0x200028,
-    GPPUPPDN0       = PERIPHERAL_BASE + 0x2000E4
-};
-
-enum {
-    GPIO_MAX_PIN       = 53,
-    GPIO_FUNCTION_OUT  = 1,
-    GPIO_FUNCTION_ALT5 = 2,
-    GPIO_FUNCTION_ALT3 = 7
-};
-
-enum {
-    Pull_None = 0,
-    Pull_Down = 1, // Are down and up the right way around?
-    Pull_Up = 2
-};
-
-void mmio_write(long reg, unsigned int val) { *(volatile unsigned int *)reg = val; }
-unsigned int mmio_read(long reg) { return *(volatile unsigned int *)reg; }
-
-unsigned int gpio_call(unsigned int pin_number, unsigned int value, unsigned int base, unsigned int field_size, unsigned int field_max) {
-    unsigned int field_mask = (1 << field_size) - 1;
-  
-    if (pin_number > field_max) return 0;
-    if (value > field_mask) return 0; 
-
-    unsigned int num_fields = 32 / field_size;
-    unsigned int reg = base + ((pin_number / num_fields) * 4);
-    unsigned int shift = (pin_number % num_fields) * field_size;
-
-    unsigned int curval = mmio_read(reg);
-    curval &= ~(field_mask << shift);
-    curval |= value << shift;
-    mmio_write(reg, curval);
-
-    return 1;
-}
-
-unsigned int gpio_set     (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPSET0, 1, GPIO_MAX_PIN); }
-unsigned int gpio_clear   (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPCLR0, 1, GPIO_MAX_PIN); }
-unsigned int gpio_pull    (unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPPUPPDN0, 2, GPIO_MAX_PIN); }
-unsigned int gpio_function(unsigned int pin_number, unsigned int value) { return gpio_call(pin_number, value, GPFSEL0, 3, GPIO_MAX_PIN); }
-
-void gpio_useAsAlt3(unsigned int pin_number) {
-    gpio_pull(pin_number, Pull_None);
-    gpio_function(pin_number, GPIO_FUNCTION_ALT3);
-}
-
-void gpio_useAsAlt5(unsigned int pin_number) {
-    gpio_pull(pin_number, Pull_None);
-    gpio_function(pin_number, GPIO_FUNCTION_ALT5);
-}
-
-void gpio_initOutputPinWithPullNone(unsigned int pin_number) {
-    gpio_pull(pin_number, Pull_None);
-    gpio_function(pin_number, GPIO_FUNCTION_OUT);
-}
-
-void gpio_setPinOutputBool(unsigned int pin_number, unsigned int onOrOff) {
-    if (onOrOff) {
-        gpio_set(pin_number, 1);
-    } else {
-        gpio_clear(pin_number, 1);
-    }
-}
-
-// UART
-
-enum {
-    AUX_BASE        = PERIPHERAL_BASE + 0x215000,
-    AUX_IRQ         = AUX_BASE,
-    AUX_ENABLES     = AUX_BASE + 4,
-    AUX_MU_IO_REG   = AUX_BASE + 64,
-    AUX_MU_IER_REG  = AUX_BASE + 68,
-    AUX_MU_IIR_REG  = AUX_BASE + 72,
-    AUX_MU_LCR_REG  = AUX_BASE + 76,
-    AUX_MU_MCR_REG  = AUX_BASE + 80,
-    AUX_MU_LSR_REG  = AUX_BASE + 84,
-    AUX_MU_MSR_REG  = AUX_BASE + 88,
-    AUX_MU_SCRATCH  = AUX_BASE + 92,
-    AUX_MU_CNTL_REG = AUX_BASE + 96,
-    AUX_MU_STAT_REG = AUX_BASE + 100,
-    AUX_MU_BAUD_REG = AUX_BASE + 104,
-    AUX_UART_CLOCK  = 500000000,
-    UART_MAX_QUEUE  = 16 * 1024
-};
-
-#define AUX_MU_BAUD(baud) ((AUX_UART_CLOCK/(baud*8))-1)
-
-unsigned char uart_output_queue[UART_MAX_QUEUE];
-unsigned int uart_output_queue_write = 0;
-unsigned int uart_output_queue_read = 0;
-
-void uart_init(void) {
-    mmio_write(AUX_ENABLES, 1); //enable UART1
-    mmio_write(AUX_MU_IER_REG, 0);
-    mmio_write(AUX_MU_CNTL_REG, 0);
-    mmio_write(AUX_MU_LCR_REG, 3); //8 bits
-    mmio_write(AUX_MU_MCR_REG, 0);
-    mmio_write(AUX_MU_IER_REG, 0);
-    mmio_write(AUX_MU_IIR_REG, 0xC6); //disable interrupts
-    mmio_write(AUX_MU_BAUD_REG, AUX_MU_BAUD(115200));
-    gpio_useAsAlt5(14);
-    gpio_useAsAlt5(15);
-    mmio_write(AUX_MU_CNTL_REG, 3); //enable RX/TX
-}
-
-unsigned int uart_isOutputQueueEmpty(void) {
-    return uart_output_queue_read == uart_output_queue_write;
-}
-
-unsigned int uart_isReadByteReady(void)  { return mmio_read(AUX_MU_LSR_REG) & 0x01; }
-unsigned int uart_isWriteByteReady(void) { return mmio_read(AUX_MU_LSR_REG) & 0x20; }
-
-unsigned char uart_readByte(void) {
-    while (!uart_isReadByteReady());
-    return (unsigned char)mmio_read(AUX_MU_IO_REG);
-}
-
-void uart_writeByteBlockingActual(unsigned char ch) {
-    while (!uart_isWriteByteReady()); 
-    mmio_write(AUX_MU_IO_REG, (unsigned int)ch);
-}
-
-void uart_loadOutputFifo(void) {
-    while (!uart_isOutputQueueEmpty() && uart_isWriteByteReady()) {
-        uart_writeByteBlockingActual(uart_output_queue[uart_output_queue_read]);
-        uart_output_queue_read = (uart_output_queue_read + 1) & (UART_MAX_QUEUE - 1); // Don't overrun
-    }
-}
-
-void uart_writeByteBlocking(unsigned char ch) {
-    unsigned int next = (uart_output_queue_write + 1) & (UART_MAX_QUEUE - 1); // Don't overrun
-
-    while (next == uart_output_queue_read) uart_loadOutputFifo();
-
-    uart_output_queue[uart_output_queue_write] = ch;
-    uart_output_queue_write = next;
-}
-
-void uart_writeText(const char *buffer) {
-    while (*buffer) {
-       if (*buffer == '\n') uart_writeByteBlocking('\r');
-       uart_writeByteBlocking(*buffer++);
-    }
-}
-
-void uart_drainOutputQueue(void) {
-    while (!uart_isOutputQueueEmpty()) uart_loadOutputFifo();
-}
-
-void uart_update(void) {
-    uart_loadOutputFifo();
-
-    if (uart_isReadByteReady()) {
-       unsigned char ch = uart_readByte();
-       if (ch == '\r') uart_writeText("\n"); else uart_writeByteBlocking(ch);
-    }
-}
diff --git a/hw/mcu/broadcom/bcm2711/io.h b/hw/mcu/broadcom/bcm2711/io.h
deleted file mode 100644
index 9f70ce504..000000000
--- a/hw/mcu/broadcom/bcm2711/io.h
+++ /dev/null
@@ -1,13 +0,0 @@
-// From: https://github.com/isometimes/rpi4-osdev/blob/master/part4-miniuart/io.h
-// CC-0 License
-
-void uart_init(void);
-void uart_writeText(const char *buffer);
-void uart_loadOutputFifo(void);
-unsigned char uart_readByte(void);
-unsigned int uart_isReadByteReady(void);
-void uart_writeByteBlocking(unsigned char ch);
-void uart_update(void);
-void gpio_setPinOutputBool(unsigned int pin_number, unsigned int onOrOff);
-void uart_writeByteBlockingActual(unsigned char ch);
-void gpio_initOutputPinWithPullNone(unsigned int pin_number);
diff --git a/hw/mcu/broadcom/bcm2711/link.ld b/hw/mcu/broadcom/bcm2711/link.ld
deleted file mode 100644
index 43c4e722f..000000000
--- a/hw/mcu/broadcom/bcm2711/link.ld
+++ /dev/null
@@ -1,28 +0,0 @@
-SECTIONS
-{
-    . = 0x80000;     /* Kernel load address for AArch64 */
-    .text : {
-        KEEP(*(.text.boot))
-        *(.text .text.* .gnu.linkonce.t*)
-    }
-    .rodata : {
-        . = ALIGN(4096);
-        *(.rodata .rodata.* .gnu.linkonce.r*)
-    }
-    PROVIDE(_data = .);
-    .data : {
-        . = ALIGN(4096);
-        *(.data .data.* .gnu.linkonce.d*)
-    }
-    .bss (NOLOAD) : {
-        __bss_start = .;
-        *(.bss .bss.*)
-        *(COMMON)
-        __bss_end = .;
-    }
-    _end = .;
-    end = .;
-
-   /DISCARD/ : { *(.comment) *(.gnu*) *(.note*) *(.eh_frame*) }
-}
-__bss_size = (__bss_end - __bss_start)>>3;
diff --git a/hw/mcu/broadcom/bcm2711/mmu.c b/hw/mcu/broadcom/bcm2711/mmu.c
deleted file mode 100644
index e5ae236bd..000000000
--- a/hw/mcu/broadcom/bcm2711/mmu.c
+++ /dev/null
@@ -1,62 +0,0 @@
-#include <stdbool.h>
-#include <stdint.h>
-
-
-#include "mmu.h"
-
-// Each entry is a gig.
-volatile uint64_t level_1_table[512] __attribute__((aligned(4096)));
-
-// Third gig has peripherals
-uint64_t level_2_0x0_c000_0000_to_0x1_0000_0000[512] __attribute__((aligned(4096)));
-
-void setup_mmu_flat_map(void) {
-    // Set the first gig to regular access.
-    level_1_table[0] = 0x0000000000000000 | 
-                       MM_DESCRIPTOR_MAIR_INDEX(MT_NORMAL_NC) |
-                       MM_DESCRIPTOR_ACCESS_FLAG |
-                       MM_DESCRIPTOR_BLOCK |
-                       MM_DESCRIPTOR_VALID;
-    level_1_table[3] = ((uint64_t) level_2_0x0_c000_0000_to_0x1_0000_0000) |
-                       MM_DESCRIPTOR_TABLE |
-                       MM_DESCRIPTOR_VALID;
-    // Set peripherals to register access.
-    for (uint64_t i = 480; i < 512; i++) {
-        level_2_0x0_c000_0000_to_0x1_0000_0000[i] = (0x00000000c0000000 + (i << 21)) |
-                                                    MM_DESCRIPTOR_EXECUTE_NEVER |
-                                                    MM_DESCRIPTOR_MAIR_INDEX(MT_DEVICE_nGnRnE) |
-                                                    MM_DESCRIPTOR_ACCESS_FLAG |
-                                                    MM_DESCRIPTOR_BLOCK |
-                                                    MM_DESCRIPTOR_VALID;
-    }
-    uint64_t mair = MAIR_VALUE;
-    uint64_t tcr = TCR_VALUE;
-    uint64_t ttbr0 = ((uint64_t) level_1_table) | MM_TTBR_CNP;
-    uint64_t sctlr = 0;
-    __asm__ volatile (
-        // Set MAIR
-        "MSR MAIR_EL2, %[mair]\n\t"
-        // Set TTBR0
-        "MSR TTBR0_EL2, %[ttbr0]\n\t"
-        // Set TCR
-        "MSR TCR_EL2, %[tcr]\n\t"
-        // The ISB forces these changes to be seen before the MMU is enabled.
-        "ISB\n\t"
-        // Read System Control Register configuration data
-        "MRS %[sctlr], SCTLR_EL2\n\t"
-        // Write System Control Register configuration data
-        "ORR %[sctlr], %[sctlr], #1\n\t"
-        // Set [M] bit and enable the MMU.
-        "MSR SCTLR_EL2, %[sctlr]\n\t"
-        // The ISB forces these changes to be seen by the next instruction
-        "ISB\n\t"
-        // "AT S1EL2R %[ttbr0]"
-        : /* No outputs. */
-        : [mair] "r" (mair),
-          [tcr] "r" (tcr),
-          [ttbr0] "r" (ttbr0),
-          [sctlr] "r" (sctlr)
-    );
-    //__asm__ ("brk #123");
-    //while (true) {}
-}
diff --git a/hw/mcu/broadcom/bcm2711/mmu.h b/hw/mcu/broadcom/bcm2711/mmu.h
deleted file mode 100644
index 1fe081f34..000000000
--- a/hw/mcu/broadcom/bcm2711/mmu.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#pragma once
-
-
-// From: https://github.com/s-matyukevich/raspberry-pi-os/blob/master/docs/lesson06/rpi-os.md
-/*
- * Memory region attributes:
- *
- *   n = AttrIndx[2:0]
- *            n    MAIR
- *   DEVICE_nGnRnE    000    00000000
- *   NORMAL_NC        001    01000100
- */
-#define MT_DEVICE_nGnRnE         0x0
-#define MT_NORMAL_NC            0x1
-#define MT_DEVICE_nGnRnE_FLAGS        0x00
-#define MT_NORMAL_NC_FLAGS          0xff
-#define MAIR_VALUE            (MT_DEVICE_nGnRnE_FLAGS << (8 * MT_DEVICE_nGnRnE)) | (MT_NORMAL_NC_FLAGS << (8 * MT_NORMAL_NC))
-
-
-#define TCR_T0SZ            (64 - 36) 
-#define TCR_PS              (0x01 << 16) // 36-bit physical address
-#define TCR_TG0_4K          (0 << 14)
-#define TCR_SH0_OUTER_SHAREABLE (0x2 << 12)
-#define TCR_VALUE           (TCR_T0SZ | TCR_PS | TCR_TG0_4K | TCR_SH0_OUTER_SHAREABLE)
-
-#define ENTRY_TYPE_TABLE_DESCRIPTOR 0x11
-#define ENTRY_TYPE_BLOCK_ENTRY 0x01
-#define ENTRY_TYPE_TABLE_ENTRY 0x11
-#define ENTRY_TYPE_INVALID 0x00
-
-#define MM_DESCRIPTOR_VALID (0x1)
-
-#define MM_DESCRIPTOR_BLOCK (0x0 << 1)
-#define MM_DESCRIPTOR_TABLE (0x1 << 1)
-
-// Block attributes
-#define MM_DESCRIPTOR_EXECUTE_NEVER (0x1ull << 54)
-#define MM_DESCRIPTOR_CONTIGUOUS    (0x1ull << 52)
-#define MM_DESCRIPTOR_ACCESS_FLAG   (0x1ull << 10)
-
-#define MM_DESCRIPTOR_MAIR_INDEX(index) (index << 2)
-
-#define MM_TTBR_CNP (0x1)
-
-void setup_mmu_flat_map(void);

From fdd1e4fbf03726703cba701f9ea7d9541e9bab9e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Oct 2021 21:52:29 +0700
Subject: [PATCH 0535/2085] more usbd  clean up

---
 src/device/usbd.c     | 62 +++++++++++++++++++------------------------
 src/device/usbd.h     | 59 +++++++++++++++++++++++++++++-----------
 src/device/usbd_pvt.h |  4 +++
 3 files changed, 75 insertions(+), 50 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index fda4a343e..a33d778db 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -906,64 +906,58 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
     tusb_desc_interface_t const * desc_itf = (tusb_desc_interface_t const*) p_desc;
 
-    // Interface number must not be used already
-    TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[desc_itf->bInterfaceNumber]);
-
-#if CFG_TUD_MIDI
-    // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD
-    // manually increase the associated count
-    if (1                              == assoc_itf_count              &&
-        TUSB_CLASS_AUDIO               == desc_itf->bInterfaceClass    &&
-        AUDIO_SUBCLASS_CONTROL         == desc_itf->bInterfaceSubClass &&
-        AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol)
-    {
-      assoc_itf_count = 2;
-    }
-#endif
-
-#if CFG_TUD_BTH && CFG_TUD_BTH_ISO_ALT_COUNT
-    // BTH implementation currently does not use IAD. TODO should also use IAD for composite device
-    if (1                                  == assoc_itf_count              &&
-        TUD_BT_APP_CLASS                   == desc_itf->bInterfaceClass    &&
-        TUD_BT_APP_SUBCLASS                == desc_itf->bInterfaceSubClass &&
-        TUD_BT_PROTOCOL_PRIMARY_CONTROLLER == desc_itf->bInterfaceProtocol)
-    {
-      assoc_itf_count = 2;
-    }
-#endif
-
-    uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
-    TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
-
     // Find driver for this interface
+    uint16_t const remaining_len = desc_end-p_desc;
     uint8_t drv_id;
     for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
     {
       usbd_class_driver_t const *driver = get_driver(drv_id);
+      uint16_t const drv_len = driver->open(rhport, desc_itf, remaining_len);
 
-      if ( driver->open(rhport, desc_itf, drv_len) )
+      if ( (sizeof(tusb_desc_interface_t) <= drv_len)  && (drv_len <= remaining_len) )
       {
         // Open successfully
         TU_LOG2("  %s opened\r\n", driver->name);
 
+        // Some drivers use 2 or more interfaces but may not have IAD e.g MIDI (always) or
+        // BTH (even CDC) with class in device descriptor (single interface)
+        if ( assoc_itf_count == 1)
+        {
+          #if CFG_TUD_CDC
+          if ( driver->open == cdcd_open ) assoc_itf_count = 2;
+          #endif
+
+          #if CFG_TUD_MIDI
+          if ( driver->open == midid_open ) assoc_itf_count = 2;
+          #endif
+
+          #if CFG_TUD_BTH && CFG_TUD_BTH_ISO_ALT_COUNT
+          if ( driver->open == btd_open ) assoc_itf_count = 2;
+          #endif
+        }
+
         // bind (associated) interfaces to found driver
         for(uint8_t i=0; i<assoc_itf_count; i++)
         {
-          _usbd_dev.itf2drv[desc_itf->bInterfaceNumber+i] = drv_id;
+          uint8_t const itf_num = desc_itf->bInterfaceNumber+i;
+
+          // Interface number must not be used already
+          TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[itf_num]);
+          _usbd_dev.itf2drv[itf_num] = drv_id;
         }
 
         // bind all endpoints to found driver
         tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id);
 
+        // next Interface
+        p_desc += drv_len;
+
         break; // exit driver find loop
       }
     }
 
     // Failed if there is no supported drivers
     TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT);
-
-    // next Interface or IAD descriptor
-    p_desc += drv_len;
   }
 
   // invoke callback
diff --git a/src/device/usbd.h b/src/device/usbd.h
index c83509234..6b19e7217 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -178,17 +178,18 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   0x9C, 0xD2, 0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F
 
 //--------------------------------------------------------------------+
-// Configuration & Interface Descriptor Templates
+// Configuration Descriptor Templates
 //--------------------------------------------------------------------+
 
-//------------- Configuration -------------//
 #define TUD_CONFIG_DESC_LEN   (9)
 
 // Config number, interface count, string index, total length, attribute, power in mA
 #define TUD_CONFIG_DESCRIPTOR(config_num, _itfcount, _stridx, _total_len, _attribute, _power_ma) \
   9, TUSB_DESC_CONFIGURATION, U16_TO_U8S_LE(_total_len), _itfcount, config_num, _stridx, TU_BIT(7) | _attribute, (_power_ma)/2
 
-//------------- CDC -------------//
+//--------------------------------------------------------------------+
+// CDC Descriptor Templates
+//--------------------------------------------------------------------+
 
 // Length of template descriptor: 66 bytes
 #define TUD_CDC_DESC_LEN  (8+9+5+5+4+5+7+9+7+7)
@@ -217,7 +218,9 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Endpoint In */\
   7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
 
-//------------- MSC -------------//
+//--------------------------------------------------------------------+
+// MSC Descriptor Templates
+//--------------------------------------------------------------------+
 
 // Length of template descriptor: 23 bytes
 #define TUD_MSC_DESC_LEN    (9 + 7 + 7)
@@ -231,7 +234,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Endpoint In */\
   7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
 
-//------------- HID -------------//
+
+//--------------------------------------------------------------------+
+// HID Descriptor Templates
+//--------------------------------------------------------------------+
 
 // Length of template descriptor: 25 bytes
 #define TUD_HID_DESC_LEN    (9 + 9 + 7)
@@ -261,8 +267,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Endpoint In */\
   7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval
 
-//------------- MIDI -------------//
-// MIDI v1.0 is based on Audio v1.0
+//--------------------------------------------------------------------+
+// MIDI Descriptor Templates
+// Note: MIDI v1.0 is based on Audio v1.0
+//--------------------------------------------------------------------+
 
 #define TUD_MIDI_DESC_HEAD_LEN (9 + 9 + 9 + 7)
 #define TUD_MIDI_DESC_HEAD(_itfnum,  _stridx, _numcables) \
@@ -319,7 +327,9 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   TUD_MIDI_DESC_EP(_epin, _epsize, 1),\
   TUD_MIDI_JACKID_OUT_EMB(1)
 
-//------------- AUDIO -------------//
+//--------------------------------------------------------------------+
+// Audio v2.0 Descriptor Templates
+//--------------------------------------------------------------------+
 
 /* Standard Interface Association Descriptor (IAD) */
 #define TUD_AUDIO_DESC_IAD_LEN 8
@@ -551,7 +561,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
     ((((_maxFrequency + ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 7999 : 999)) / ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels)
 
 
-//------------- TUD_USBTMC/USB488 -------------//
+//--------------------------------------------------------------------+
+// USBTMC/USB488 Descriptor Templates
+//--------------------------------------------------------------------+
+
 #define TUD_USBTMC_APP_CLASS    (TUSB_CLASS_APPLICATION_SPECIFIC)
 #define TUD_USBTMC_APP_SUBCLASS 0x03u
 
@@ -581,8 +594,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 #define TUD_USBTMC_INT_DESCRIPTOR_LEN (7u)
 
+//--------------------------------------------------------------------+
+// Vendor Descriptor Templates
+//--------------------------------------------------------------------+
 
-//------------- Vendor -------------//
 #define TUD_VENDOR_DESC_LEN  (9+7+7)
 
 // Interface number, string index, EP Out & IN address, EP size
@@ -594,7 +609,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Endpoint In */\
   7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
 
-//------------- DFU Runtime -------------//
+//--------------------------------------------------------------------+
+// DFU Runtime Descriptor Templates
+//--------------------------------------------------------------------+
+
 #define TUD_DFU_APP_CLASS    (TUSB_CLASS_APPLICATION_SPECIFIC)
 #define TUD_DFU_APP_SUBCLASS (APP_SUBCLASS_DFU_RUNTIME)
 
@@ -609,6 +627,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Function */ \
   9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
 
+//--------------------------------------------------------------------+
+// DFU Descriptor Templates
+//--------------------------------------------------------------------+
+
 // Length of template descriptor: 9 bytes + number of alternatives * 9
 #define TUD_DFU_DESC_LEN(_alt_count)    (9 + (_alt_count) * 9)
 
@@ -654,8 +676,9 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   _TUD_DFU_ALT(_itfnum, _alt_count, _stridx),      \
   _TUD_DFU_ALT_7(_itfnum, _alt_count+1, _stridx+1)
 
-
-//------------- CDC-ECM -------------//
+//--------------------------------------------------------------------+
+// CDC-ECM Descriptor Templates
+//--------------------------------------------------------------------+
 
 // Length of template descriptor: 71 bytes
 #define TUD_CDC_ECM_DESC_LEN  (8+9+5+5+13+7+9+9+7+7)
@@ -684,8 +707,9 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Endpoint Out */\
   7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
 
-
-//------------- RNDIS -------------//
+//--------------------------------------------------------------------+
+// RNDIS Descriptor Templates
+//--------------------------------------------------------------------+
 
 #if 0
 /* Windows XP */
@@ -726,7 +750,10 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Endpoint Out */\
   7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
 
-//------------- BT Radio -------------//
+//--------------------------------------------------------------------+
+// Bluetooth Radio Descriptor Templates
+//--------------------------------------------------------------------+
+
 #define TUD_BT_APP_CLASS                    (TUSB_CLASS_WIRELESS_CONTROLLER)
 #define TUD_BT_APP_SUBCLASS                 0x01
 #define TUD_BT_PROTOCOL_PRIMARY_CONTROLLER  0x01
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 7607b9895..f66429a02 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -43,6 +43,10 @@ typedef struct
   char const* name;
   #endif
 
+  // Minimum number of Interfaces for this driver to work.
+  // Only needed for driver use 2 or more interfaces without IAD
+  uint8_t itf_count_min;
+
   void     (* init             ) (void);
   void     (* reset            ) (uint8_t rhport);
   uint16_t (* open             ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len);

From 75ad0c7d310bf49b70e737d82b86b7ad4be1f167 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Oct 2021 22:20:50 +0700
Subject: [PATCH 0536/2085] clean up

---
 src/device/usbd_pvt.h | 4 ----
 src/host/usbh.c       | 9 +++++----
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index f66429a02..7607b9895 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -43,10 +43,6 @@ typedef struct
   char const* name;
   #endif
 
-  // Minimum number of Interfaces for this driver to work.
-  // Only needed for driver use 2 or more interfaces without IAD
-  uint8_t itf_count_min;
-
   void     (* init             ) (void);
   void     (* reset            ) (uint8_t rhport);
   uint16_t (* open             ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 100a17aa4..2ef936ad0 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1000,9 +1000,6 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
     TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
     tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
 
-    // Interface number must not be used already
-    TU_ASSERT( DRVID_INVALID == dev->itf2drv[desc_itf->bInterfaceNumber] );
-
 #if CFG_TUH_MIDI
     // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD
     // manually increase the associated count
@@ -1040,7 +1037,11 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
           // bind (associated) interfaces to found driver
           for(uint8_t i=0; i<assoc_itf_count; i++)
           {
-            dev->itf2drv[desc_itf->bInterfaceNumber+i] = drv_id;
+            uint8_t const itf_num = desc_itf->bInterfaceNumber+i;
+
+            // Interface number must not be used already
+            TU_ASSERT( DRVID_INVALID == dev->itf2drv[itf_num] );
+            dev->itf2drv[itf_num] = drv_id;
           }
 
           // bind all endpoints to found driver

From fec2d1598921d59b9112749e670f8ac2bcf37e2b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Oct 2021 23:00:09 +0700
Subject: [PATCH 0537/2085] clean up vendor open

---
 src/class/vendor/vendor_device.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 8f25141b8..8a4ca1d2e 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -179,8 +179,8 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui
 {
   TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0);
 
-  uint16_t drv_len = tu_desc_len(desc_itf);
   uint8_t const * p_desc = tu_desc_next(desc_itf);
+  uint8_t const * desc_end = p_desc + max_len;
 
   // Find available interface
   vendord_interface_t* p_vendor = NULL;
@@ -198,16 +198,15 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui
   if (desc_itf->bNumEndpoints)
   {
     // skip non-endpoint descriptors
-    while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (drv_len <= max_len) )
+    while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (p_desc < desc_end) )
     {
-      drv_len += tu_desc_len(p_desc);
-      p_desc   = tu_desc_next(p_desc);
+      p_desc = tu_desc_next(p_desc);
     }
 
     // Open endpoint pair with usbd helper
     TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, desc_itf->bNumEndpoints, TUSB_XFER_BULK, &p_vendor->ep_out, &p_vendor->ep_in), 0);
 
-    drv_len += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
+    p_desc += desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
 
     // Prepare for incoming data
     if ( p_vendor->ep_out )
@@ -218,7 +217,7 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui
     if ( p_vendor->ep_in ) maybe_transmit(p_vendor);
   }
 
-  return drv_len;
+  return (uintptr_t) p_desc - (uintptr_t) desc_itf;
 }
 
 bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)

From aa97b419b22f466c7034d42a0298fad3eafc5311 Mon Sep 17 00:00:00 2001
From: Charlie Birks <charlie@daft.games>
Date: Mon, 4 Oct 2021 11:43:12 +0100
Subject: [PATCH 0538/2085] Handle HID devices with OUT endpoint listed first

This happens on my PowerA wired Switch pro controller
---
 src/class/hid/hid_host.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 8c66477b3..ac260d39b 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -291,7 +291,15 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
   TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
 
+  // first endpoint may be OUT, skip to IN endpoint
   // TODO also open endpoint OUT
+  if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_OUT)
+  {
+    p_desc = tu_desc_next(p_desc);
+    desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+    TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
+  }
+
   TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep) );
 
   hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count);

From a867d87072e6f25e47f209e9615e00b97a9eb36f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 5 Oct 2021 12:32:07 +0700
Subject: [PATCH 0539/2085] rename CFG_TUD_NET to CFG_TUD_ECM_RNDIS

---
 .../cdc_msc_freertos/src/CMakeLists.txt       |  2 +-
 .../hid_composite_freertos/src/CMakeLists.txt |  2 +-
 .../net_lwip_webserver/src/tusb_config.h      | 12 +++---
 .../net_lwip_webserver/src/usb_descriptors.c  | 12 ++++--
 examples/rules.mk                             |  2 +-
 hw/bsp/rp2040/family.cmake                    |  2 +-
 .../{ecmrndis_device.c => ecm_rndis_device.c} |  2 +-
 src/class/net/ncm_device.c                    | 24 +++++------
 src/class/net/net_device.h                    | 40 ++++++++++++-------
 src/device/usbd.c                             |  2 +-
 src/tusb.h                                    |  2 +-
 src/tusb_option.h                             | 10 ++---
 12 files changed, 63 insertions(+), 49 deletions(-)
 rename src/class/net/{ecmrndis_device.c => ecm_rndis_device.c} (99%)

diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index f1c1e8c5d..07fc4df89 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -23,7 +23,7 @@ target_sources(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src/class/hid/hid_device.c"
   "${TOP}/src/class/midi/midi_device.c"
   "${TOP}/src/class/msc/msc_device.c"
-  "${TOP}/src/class/net/ecmrndis_device.c"
+  "${TOP}/src/class/net/ecm_rndis_device.c"
   "${TOP}/src/class/net/ncm_device.c"
   "${TOP}/src/class/usbtmc/usbtmc_device.c"
   "${TOP}/src/class/vendor/vendor_device.c"
diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt
index 70df447dd..6f156379f 100644
--- a/examples/device/hid_composite_freertos/src/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt
@@ -23,7 +23,7 @@ target_sources(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src/class/hid/hid_device.c"
   "${TOP}/src/class/midi/midi_device.c"
   "${TOP}/src/class/msc/msc_device.c"
-  "${TOP}/src/class/net/ecmrndis_device.c"
+  "${TOP}/src/class/net/ecm_rndis_device.c"
   "${TOP}/src/class/net/ncm_device.c"
   "${TOP}/src/class/usbtmc/usbtmc_device.c"
   "${TOP}/src/class/vendor/vendor_device.c"
diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h
index 457918cac..114961cb7 100644
--- a/examples/device/net_lwip_webserver/src/tusb_config.h
+++ b/examples/device/net_lwip_webserver/src/tusb_config.h
@@ -95,13 +95,11 @@
 #endif
 
 //------------- CLASS -------------//
-#define CFG_TUD_CDC               0
-#define CFG_TUD_MSC               0
-#define CFG_TUD_HID               0
-#define CFG_TUD_MIDI              0
-#define CFG_TUD_VENDOR            0
-#define CFG_TUD_NET               1
-#define CFG_TUD_NCM               0
+
+// Network class has 2 drivers: ECM/RNDIS and NCM.
+// Only one of the drivers can be enabled
+#define CFG_TUD_ECM_RNDIS     1
+#define CFG_TUD_NCM           (1-CFG_TUD_ECM_RNDIS)
 
 #ifdef __cplusplus
  }
diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c
index d9618a3dc..2b4b2a0c3 100644
--- a/examples/device/net_lwip_webserver/src/usb_descriptors.c
+++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c
@@ -33,7 +33,7 @@
  */
 #define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
-                           _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) | _PID_MAP(NET, 5) )
+                           _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) | _PID_MAP(ECM_RNDIS, 5) | _PID_MAP(NCM, 5) )
 
 // String Descriptor Index
 enum
@@ -55,7 +55,7 @@ enum
 
 enum
 {
-#if !CFG_TUD_NCM
+#if CFG_TUD_ECM_RNDIS
   CONFIG_ID_RNDIS = 0,
   CONFIG_ID_ECM   = 1,
 #else
@@ -125,7 +125,8 @@ uint8_t const * tud_descriptor_device_cb(void)
   #define EPNUM_NET_IN      0x82
 #endif
 
-#if !CFG_TUD_NCM
+#if CFG_TUD_ECM_RNDIS
+
 static uint8_t const rndis_configuration[] =
 {
   // Config number (index+1), interface count, string index, total length, attribute, power in mA
@@ -143,7 +144,9 @@ static uint8_t const ecm_configuration[] =
   // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size.
   TUD_CDC_ECM_DESCRIPTOR(ITF_NUM_CDC, STRID_INTERFACE, STRID_MAC, EPNUM_NET_NOTIF, 64, EPNUM_NET_OUT, EPNUM_NET_IN, CFG_TUD_NET_ENDPOINT_SIZE, CFG_TUD_NET_MTU),
 };
+
 #else
+
 static uint8_t const ncm_configuration[] =
 {
   // Config number (index+1), interface count, string index, total length, attribute, power in mA
@@ -152,6 +155,7 @@ static uint8_t const ncm_configuration[] =
   // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size.
   TUD_CDC_NCM_DESCRIPTOR(ITF_NUM_CDC, STRID_INTERFACE, STRID_MAC, EPNUM_NET_NOTIF, 64, EPNUM_NET_OUT, EPNUM_NET_IN, CFG_TUD_NET_ENDPOINT_SIZE, CFG_TUD_NET_MTU),
 };
+
 #endif
 
 // Configuration array: RNDIS and CDC-ECM
@@ -160,7 +164,7 @@ static uint8_t const ncm_configuration[] =
 // - Linux will work on both
 static uint8_t const * const configuration_arr[2] =
 {
-#if !CFG_TUD_NCM
+#if CFG_TUD_ECM_RNDIS
   [CONFIG_ID_RNDIS] = rndis_configuration,
   [CONFIG_ID_ECM  ] = ecm_configuration
 #else
diff --git a/examples/rules.mk b/examples/rules.mk
index a9dfa1363..5f9dd9d19 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -33,7 +33,7 @@ SRC_C += \
 	src/class/hid/hid_device.c \
 	src/class/midi/midi_device.c \
 	src/class/msc/msc_device.c \
-	src/class/net/ecmrndis_device.c \
+	src/class/net/ecm_rndis_device.c \
 	src/class/net/ncm_device.c \
 	src/class/usbtmc/usbtmc_device.c \
 	src/class/vendor/vendor_device.c
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index a0f41212c..4ba24b3aa 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -70,7 +70,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/class/hid/hid_device.c
 			${TOP}/src/class/midi/midi_device.c
 			${TOP}/src/class/msc/msc_device.c
-			${TOP}/src/class/net/ecmrndis_device.c
+			${TOP}/src/class/net/ecm_rndis_device.c
 			${TOP}/src/class/net/ncm_device.c
 			${TOP}/src/class/usbtmc/usbtmc_device.c
 			${TOP}/src/class/vendor/vendor_device.c
diff --git a/src/class/net/ecmrndis_device.c b/src/class/net/ecm_rndis_device.c
similarity index 99%
rename from src/class/net/ecmrndis_device.c
rename to src/class/net/ecm_rndis_device.c
index 288ecb7e2..c6cd388e3 100644
--- a/src/class/net/ecmrndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NET && !CFG_TUD_NCM )
+#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_ECM_RNDIS )
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 1f592401e..2f7d58f99 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -28,7 +28,7 @@
 
 #include "tusb_option.h"
 
-#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NET && CFG_TUD_NCM )
+#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NCM )
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
@@ -131,18 +131,18 @@ typedef struct
 //--------------------------------------------------------------------+
 
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parameters = {
-    .wLength = sizeof(ntb_parameters_t),
-    .bmNtbFormatsSupported = 0x01,
-    .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
-    .wNdbInDivisor = 4,
-    .wNdbInPayloadRemainder = 0,
-    .wNdbInAlignment = CFG_TUD_NCM_ALIGNMENT,
-    .wReserved = 0,
-    .dwNtbOutMaxSize = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
-    .wNdbOutDivisor = 4,
+    .wLength                 = sizeof(ntb_parameters_t),
+    .bmNtbFormatsSupported   = 0x01,
+    .dwNtbInMaxSize          = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
+    .wNdbInDivisor           = 4,
+    .wNdbInPayloadRemainder  = 0,
+    .wNdbInAlignment         = CFG_TUD_NCM_ALIGNMENT,
+    .wReserved               = 0,
+    .dwNtbOutMaxSize         = CFG_TUD_NCM_OUT_NTB_MAX_SIZE,
+    .wNdbOutDivisor          = 4,
     .wNdbOutPayloadRemainder = 0,
-    .wNdbOutAlignment = CFG_TUD_NCM_ALIGNMENT,
-    .wNtbOutMaxDatagrams = 0
+    .wNdbOutAlignment        = CFG_TUD_NCM_ALIGNMENT,
+    .wNtbOutMaxDatagrams     = 0
 };
 
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static transmit_ntb_t transmit_ntb[2];
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index e6cdc8b8b..ad369b680 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -30,10 +30,14 @@
 
 #include "class/cdc/cdc.h"
 
+#if CFG_TUD_ECM_RNDIS && CFG_TUD_NCM
+#error "Cannot enable both ECM_RNDIS and NCM network drivers"
+#endif
+
 /* declared here, NOT in usb_descriptors.c, so that the driver can intelligently ZLP as needed */
 #define CFG_TUD_NET_ENDPOINT_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
-/* Maximum Tranmission Unit (in bytes) of the network, including Ethernet header */
+/* Maximum Transmission Unit (in bytes) of the network, including Ethernet header */
 #ifndef CFG_TUD_NET_MTU
 #define CFG_TUD_NET_MTU           1514
 #endif
@@ -62,19 +66,6 @@
 // Application API
 //--------------------------------------------------------------------+
 
-// client must provide this: initialize any network state back to the beginning
-void tud_network_init_cb(void);
-
-// client must provide this: return false if the packet buffer was not accepted
-bool tud_network_recv_cb(const uint8_t *src, uint16_t size);
-
-// client must provide this: copy from network stack packet pointer to dst
-uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg);
-
-// client must provide this: 48-bit MAC address
-// TODO removed later since it is not part of tinyusb stack
-extern const uint8_t tud_network_mac_address[6];
-
 // indicate to network driver that client has finished with the packet provided to network_recv_cb()
 void tud_network_recv_renew(void);
 
@@ -84,6 +75,27 @@ bool tud_network_can_xmit(uint16_t size);
 // if network_can_xmit() returns true, network_xmit() can be called once
 void tud_network_xmit(void *ref, uint16_t arg);
 
+//--------------------------------------------------------------------+
+// Application Callbacks (WEAK is optional)
+//--------------------------------------------------------------------+
+
+// client must provide this: return false if the packet buffer was not accepted
+bool tud_network_recv_cb(const uint8_t *src, uint16_t size);
+
+// client must provide this: copy from network stack packet pointer to dst
+uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg);
+
+//------------- ECM/RNDIS -------------//
+
+// client must provide this: initialize any network state back to the beginning
+void tud_network_init_cb(void);
+
+// client must provide this: 48-bit MAC address
+// TODO removed later since it is not part of tinyusb stack
+extern const uint8_t tud_network_mac_address[6];
+
+//------------- NCM -------------//
+
 // callback to client providing optional indication of internal state of network driver
 void tud_network_link_state_cb(bool state);
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index a33d778db..ab1837895 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -203,7 +203,7 @@ static usbd_class_driver_t const _usbd_driver[] =
   },
   #endif
 
-  #if CFG_TUD_NET
+  #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
   {
     DRIVER_NAME("NET")
     .init             = netd_init,
diff --git a/src/tusb.h b/src/tusb.h
index b52f8839a..2e1b7a43d 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -100,7 +100,7 @@
     #include "class/dfu/dfu_device.h"
   #endif
 
-  #if CFG_TUD_NET
+  #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
     #include "class/net/net_device.h"
   #endif
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 3cb672d80..369c35e2d 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -261,16 +261,16 @@
   #define CFG_TUD_DFU             0
 #endif
 
-#ifndef CFG_TUD_NET
-  #define CFG_TUD_NET             0
-#endif
-
 #ifndef CFG_TUD_BTH
   #define CFG_TUD_BTH             0
 #endif
 
+#ifndef CFG_TUD_ECM_RNDIS
+  #define CFG_TUD_ECM_RNDIS   0
+#endif
+
 #ifndef CFG_TUD_NCM
-  #define CFG_TUD_NCM             0
+  #define CFG_TUD_NCM         0
 #endif
 
 //--------------------------------------------------------------------

From 6fd62c8902915b987d600cd17e70383cbef78802 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 5 Oct 2021 16:06:54 +0700
Subject: [PATCH 0540/2085] update docs

---
 CONTRIBUTORS.rst | 23 +++++++++++++----------
 README.rst       |  2 +-
 2 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index 040f40166..cd1c19373 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -31,6 +31,12 @@ Notable contributors
 -  Improve ESP32s2 DCD
 
 
+`Jacob Berg Potter <https://github.com/j4cbo>`__
+------------------------------------------------
+
+-  Add new class driver for network CDC-NCM
+
+
 `Jan Dümpelmann <https://github.com/duempel>`__
 -----------------------------------------------
 
@@ -93,9 +99,9 @@ Notable contributors
 ------------------------------------------------
 
 -  Add new DCD port for Nuvoton NUC 120, 121, 125, 126, 505
--  Add new class driver for USBNET RNDIS, CDC-ECM
--  Add *net\_lwip\_webserver* example for demonstration of usbnet with
-   lwip
+-  Add new class driver for network RNDIS, CDC-ECM
+-  Enhance NCM network driver to compatible with RNDIS/ECM
+-  Add *net\_lwip\_webserver* example for demonstration of usbnet with lwip
 -  Board support for NuTiny NUC120, NUC121s, NUC125s, NUC126V, NUC505
 -  Improve multiple cdc interfaces API & add cdc\_dual\_ports example
 
@@ -118,10 +124,8 @@ Notable contributors
 ------------------------------------------------
 
 -  Add new class driver for USB Audio Class 2.0 (UAC2)
--  Rework tu\_fifo with unmasked pointer, add DMA support, and constant
-   address support
--  Add new DCD/USBD edpt\_xfer\_fifo() API for optimizing endpoint
-   transfer
+-  Rework tu\_fifo with unmasked pointer, add DMA support, and constant address support
+-  Add new DCD/USBD edpt\_xfer\_fifo() API for optimizing endpoint transfer
 -  Add and greatly improve Isochronous transfer
 -  Add new audio examples: audio\_test and audio\_4\_channel\_mic
 
@@ -130,8 +134,7 @@ Notable contributors
 ------------------------------------------------
 
 -  Add new DCD port for SAMD21 and SAMD51
--  Add new class driver for Musical Instrument Digital Interface
-   (MIDI)
+-  Add new class driver for Musical Instrument Digital Interface (MIDI)
 -  Improve USBD control transfer, MSC, CDC class driver
 -  Board support for Metro M0 & M4 express
 -  Write the excellent porting.md documentation
@@ -178,7 +181,7 @@ Notable contributors
 
 
 `Zixun Li <https://github.com/HiFiPhile>`__
------------------------------------------------
+-------------------------------------------
 
 -  Add new DCD port for Microchip SAMx7x
 -  Add IAR compiler support
diff --git a/README.rst b/README.rst
index 52738da32..5eecd63ac 100644
--- a/README.rst
+++ b/README.rst
@@ -65,7 +65,7 @@ Supports multiple device configurations by dynamically changing USB descriptors,
 -  Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ...
 -  Mass Storage Class (MSC): with multiple LUNs
 -  Musical Instrument Digital Interface (MIDI)
--  Network with RNDIS, CDC-ECM (work in progress)
+-  Network with RNDIS, Ethernet Control Model (ECM), Network Control Model (NCM)
 -  USB Test and Measurement Class (USBTMC)
 -  Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file.
 -  `WebUSB <https://github.com/WICG/webusb>`__ with vendor-specific class

From 62c613f6d2d4e3e2cf0918f75e302d48a3df673e Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@ftdichip.com>
Date: Tue, 5 Oct 2021 13:54:47 +0100
Subject: [PATCH 0541/2085] Add initial port for FT9xx series from Bridgetek.
 Add FT90X and FT93X to the list of devices in tusb_option.h. 1700 for FT90x
 and 1701 for FT93x. Set endpoint attributes for FT90x and FT93x in
 dcd_attr.h. Add FT90x routines for USB device in
 src/portable/bridgetek/ft90x/dcd_ft90x.c The location for hardware header
 files and libraries is hw/mcu/bridgetek/ft90x/hardware. There are no files in
 the repository, but files will be linked as a submodule in the future. The
 required files can be copied from or linked to the location "C:/Program
 Files(x86)/Bridgetek/FT9xx Toolchain/Toolchain/hardware" once the toolchain
 is installed. Makefile for the MM900EV1B board for developing with an FT900
 device is present. Use "BOARD=mm900ev1b".

---
 hw/bsp/brtmm90x/boards/mm900ev1b/board.h      |   56 +
 hw/bsp/brtmm90x/family.c                      |  210 ++++
 hw/bsp/brtmm90x/family.mk                     |   35 +
 hw/mcu/bridgetek/ft90x/Readme.md              |    6 +
 .../bridgetek/ft90x/hardware/scripts/crt0.S   |  286 +++++
 .../ft90x/hardware/scripts/ldscript.ld        |   94 ++
 src/device/dcd_attr.h                         |    7 +
 src/portable/bridgetek/ft90x/dcd_ft90x.c      | 1101 +++++++++++++++++
 src/tusb_option.h                             |    4 +
 9 files changed, 1799 insertions(+)
 create mode 100644 hw/bsp/brtmm90x/boards/mm900ev1b/board.h
 create mode 100644 hw/bsp/brtmm90x/family.c
 create mode 100644 hw/bsp/brtmm90x/family.mk
 create mode 100644 hw/mcu/bridgetek/ft90x/Readme.md
 create mode 100644 hw/mcu/bridgetek/ft90x/hardware/scripts/crt0.S
 create mode 100644 hw/mcu/bridgetek/ft90x/hardware/scripts/ldscript.ld
 create mode 100644 src/portable/bridgetek/ft90x/dcd_ft90x.c

diff --git a/hw/bsp/brtmm90x/boards/mm900ev1b/board.h b/hw/bsp/brtmm90x/boards/mm900ev1b/board.h
new file mode 100644
index 000000000..dfb566289
--- /dev/null
+++ b/hw/bsp/brtmm90x/boards/mm900ev1b/board.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(__FT900__)
+#define GPIO_UART0_TX 48
+#define GPIO_UART0_RX 49
+#define GPIO_ETH_LED0 61
+#define GPIO_ETH_LED1 62
+#define GPIO_REMOTE_WAKEUP_PIN 18
+#define USBD_VBUS_DTC_PIN 3
+#elif defined(__FT930__)
+#define GPIO_UART0_TX 23
+#define GPIO_UART0_RX 22
+#define GPIO_ETH_LED0 4
+#define GPIO_ETH_LED1 5
+#define GPIO_REMOTE_WAKEUP_PIN 12
+#define USBD_VBUS_DTC_PIN 39
+#endif
+
+//#define GPIO_REMOTE_WAKEUP
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
new file mode 100644
index 000000000..010704d92
--- /dev/null
+++ b/hw/bsp/brtmm90x/family.c
@@ -0,0 +1,210 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright 2019 Sony Semiconductor Solutions Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <registers/ft900_registers.h>
+#include <ft900.h>
+#include "bsp/board.h"
+#include "board.h"
+//#include "src/device/dcd.h"
+
+#if TUSB_OPT_DEVICE_ENABLED
+int8_t board_ft90x_vbus(void); // Board specific implementation of VBUS detection for USB device.
+extern void ft90x_usbd_pm_ISR(uint16_t pmcfg); // Interrupt handler for USB device power management
+#endif
+
+#ifdef GPIO_REMOTE_WAKEUP
+void gpio_ISR(void);
+#endif
+void timer_ISR(void);
+volatile unsigned int timer_ms = 0;
+void board_pm_ISR(void);
+
+#define WELCOME_MSG "\x1B[2J\x1B[H" \
+                    "MM900EV1B board\r\n"
+
+// Initialize on-board peripherals : led, button, uart and USB
+void board_init(void)
+{
+	sys_reset_all();
+    // Enable the UART Device.
+    sys_enable(sys_device_uart0);
+    // Set UART0 GPIO functions to UART0_TXD and UART0_RXD.
+    gpio_function(GPIO_UART0_TX, pad_uart0_txd); /* UART0 TXD */
+    gpio_function(GPIO_UART0_RX, pad_uart0_rxd); /* UART0 RXD */
+    uart_open(UART0,                             /* Device */
+              1,                                 /* Prescaler = 1 */
+              UART_DIVIDER_19200_BAUD,           /* Divider = 1302 */
+              uart_data_bits_8,                  /* No. Data Bits */
+              uart_parity_none,                  /* Parity */
+              uart_stop_bits_1);                 /* No. Stop Bits */
+	// Print out a welcome message.
+    // Use sizeof to avoid pulling in strlen unnecessarily.
+    board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG));
+
+#if 1
+    gpio_function(GPIO_ETH_LED0, pad_gpio4); /* ETH LED0 */
+    gpio_dir(GPIO_ETH_LED0, pad_dir_open_drain);
+    gpio_function(GPIO_ETH_LED1, pad_gpio5); /* ETH LED0 */
+    gpio_dir(GPIO_ETH_LED1, pad_dir_output);
+#endif
+	sys_enable(sys_device_timer_wdt);
+	interrupt_attach(interrupt_timers, (int8_t)interrupt_timers, timer_ISR);
+	/* Timer A = 1ms */
+	timer_prescaler(timer_select_a, 1000);
+	timer_init(timer_select_a, 100, timer_direction_down, timer_prescaler_select_on, timer_mode_continuous);
+	timer_enable_interrupt(timer_select_a);
+	timer_start(timer_select_a);
+
+    // Setup VBUS detect GPIO. If the device is connected then this
+    // will set the MASK_SYS_PMCFG_DEV_DETECT_EN bit in PMCFG.
+    gpio_interrupt_disable(USBD_VBUS_DTC_PIN);
+    gpio_function(USBD_VBUS_DTC_PIN, pad_vbus_dtc);
+    gpio_pull(USBD_VBUS_DTC_PIN, pad_pull_pulldown);
+    gpio_dir(USBD_VBUS_DTC_PIN, pad_dir_input);
+
+    interrupt_attach(interrupt_0, (int8_t)interrupt_0, board_pm_ISR);
+
+#ifdef GPIO_REMOTE_WAKEUP
+    //Configuring GPIO pin to wakeup.
+    // Set up the wakeup pin.
+    gpio_dir(GPIO_REMOTE_WAKEUP_PIN, pad_dir_input);
+    gpio_pull(GPIO_REMOTE_WAKEUP_PIN, pad_pull_pullup);
+
+    // Attach an interrupt handler.
+    interrupt_attach(interrupt_gpio, (uint8_t)interrupt_gpio, gpio_ISR);
+    gpio_interrupt_enable(GPIO_REMOTE_WAKEUP_PIN, gpio_int_edge_falling);
+#endif
+
+	uart_disable_interrupt(UART0, uart_interrupt_tx);
+	uart_disable_interrupt(UART0, uart_interrupt_rx);
+
+    // Enable all peripheral interrupts.
+    interrupt_enable_globally();
+
+    TU_LOG1("MM900EV1B board setup complete\r\n");
+};
+
+void timer_ISR(void)
+{
+    if (timer_is_interrupted(timer_select_a))
+    {
+        timer_ms++;
+    }
+}
+
+#ifdef GPIO_REMOTE_WAKEUP
+void gpio_ISR(void)
+{
+    if (gpio_is_interrupted(GPIO_REMOTE_WAKEUP_PIN))
+    {
+    }
+}
+#endif
+
+/* Power management ISR */
+void board_pm_ISR(void)
+{
+    uint16_t pmcfg = SYS->PMCFG_H;
+
+#if defined(__FT930__)
+    if (pmcfg & MASK_SYS_PMCFG_SLAVE_PERI_IRQ_PEND)
+    {
+        // Clear d2xx hw engine wakeup.
+        SYS->PMCFG_H = MASK_SYS_PMCFG_SLAVE_PERI_IRQ_PEND;
+    }
+#endif
+    if (pmcfg & MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND)
+    {
+        // Clear GPIO wakeup pending.
+        SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
+    }
+
+#if defined(__FT900__)
+    // USB device power management interrupts.
+    if (pmcfg & (MASK_SYS_PMCFG_DEV_CONN_DEV |
+              MASK_SYS_PMCFG_DEV_DIS_DEV |
+              MASK_SYS_PMCFG_HOST_RST_DEV |
+              MASK_SYS_PMCFG_HOST_RESUME_DEV)
+    )
+    {
+#if TUSB_OPT_DEVICE_ENABLED
+        ft90x_usbd_pm_ISR(pmcfg);
+#endif
+    }
+#endif
+}
+
+#if TUSB_OPT_DEVICE_ENABLED
+int8_t board_ft90x_vbus(void)
+{
+	return gpio_read(USBD_VBUS_DTC_PIN);
+}
+#endif
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+// Turn LED on or off
+void board_led_write(bool state)
+{
+    gpio_write(GPIO_ETH_LED0, state);
+}
+
+// Get the current state of button
+// a '1' means active (pressed), a '0' means inactive.
+uint32_t board_button_read(void)
+{
+    return 0;
+}
+
+// Get characters from UART
+int board_uart_read(uint8_t *buf, int len)
+{
+    int r = uart_readn(UART0, (uint8_t *)buf, len);
+
+    return r;
+}
+
+// Send characters to UART
+int board_uart_write(void const *buf, int len)
+{
+    int r = uart_writen(UART0, (uint8_t *)buf, len);
+
+    return r;
+}
+
+// Get current milliseconds
+uint32_t board_millis(void)
+{
+    uint32_t safe_ms;
+    
+    CRITICAL_SECTION_BEGIN
+    safe_ms = timer_ms;
+    CRITICAL_SECTION_END
+
+    return safe_ms;
+}
diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
new file mode 100644
index 000000000..57a141506
--- /dev/null
+++ b/hw/bsp/brtmm90x/family.mk
@@ -0,0 +1,35 @@
+
+CROSS_COMPILE = ft32-elf-
+DEPS_SUBMODULES += hw/mcu/bridgetek/ft90x/hardware
+SKIP_NANOLIB = 1
+
+# This is installed at "C:/Program Files(x86)/Bridgetek/FT9xx Toolchain/Toolchain/hardware"
+FT90X_SDK = $(TOP)/hw/mcu/bridgetek/ft90x/hardware
+
+CFLAGS += \
+	-D__FT900__ \
+	-fvar-tracking \
+	-fvar-tracking-assignments \
+	-fmessage-length=0 \
+	-ffunction-sections \
+	-DCFG_TUSB_MCU=OPT_MCU_FT90X 
+
+# lwip/src/core/raw.c:334:43: error: declaration of 'recv' shadows a global declaration
+CFLAGS += -Wno-error=shadow
+CFLAGS:=$(filter-out -Wcast-function-type,$(CFLAGS))
+
+# All source paths should be relative to the top level.
+LDINC += $(FT90X_SDK)/lib/Release
+LIBS += -lft900
+LD_FILE = hw/mcu/bridgetek/ft90x/hardware/scripts/ldscript.ld
+LDFLAGS += $(addprefix -L,$(LDINC)) \
+	-Xlinker --entry=_start \
+	-Wl,-lc
+
+SRC_C += src/portable/bridgetek/ft90x/dcd_ft90x.c 
+
+#SRC_S += hw/mcu/bridgetek/ft90x/hardware/scripts/crt0.S
+
+INC += \
+	$(FT90X_SDK)/include \
+	$(TOP)/$(BOARD_PATH)
diff --git a/hw/mcu/bridgetek/ft90x/Readme.md b/hw/mcu/bridgetek/ft90x/Readme.md
new file mode 100644
index 000000000..e197f182e
--- /dev/null
+++ b/hw/mcu/bridgetek/ft90x/Readme.md
@@ -0,0 +1,6 @@
+# BridgeTek FT9xx MCU
+
+**BridgeTek** provides a hardware abstraction library with software source code for the SDKs for FT9xx software family.
+The pre-built libraries and the source code can be redistributed.
+Registers definition files `<sdk>/include/registers/ft900_registers.h` and included peripheral register definition files have licenses that allow for redistribution.  
+Whole SDK repository is installed as part of the FT9xx Toolchain and can be downloaded from BridgeTek web page `https://www.brtchip.com`
diff --git a/hw/mcu/bridgetek/ft90x/hardware/scripts/crt0.S b/hw/mcu/bridgetek/ft90x/hardware/scripts/crt0.S
new file mode 100644
index 000000000..62fa266ee
--- /dev/null
+++ b/hw/mcu/bridgetek/ft90x/hardware/scripts/crt0.S
@@ -0,0 +1,286 @@
+.equ SYS_REGMSC0CFG_B3  , 0x1001b
+.equ SYS_REGIRQCTL_B3   , 0x100e3
+.equ MAILBOX_MEMORY     , 0x13000
+
+.equ	IS_IMG_SDBL_PRESENT, 0
+.equ	IS_IMG_D2XX_PRESENT, 0
+.equ	IS_IMG_DLOG_PRESENT, 0
+
+.section .crt0
+.global _start
+
+_start:
+# START Interrupt Vector Table [[
+        jmp     __PMSIZE-4         # RESET Vector
+        jmp     interrupt_33	   # Watchdog reset vector
+        jmp     interrupt_0
+        jmp     interrupt_1
+        jmp     interrupt_2
+        jmp     interrupt_3
+        jmp     interrupt_4
+        jmp     interrupt_5
+        jmp     interrupt_6
+        jmp     interrupt_7
+        jmp     interrupt_8
+        jmp     interrupt_9
+        jmp     interrupt_10
+        jmp     interrupt_11
+        jmp     interrupt_12
+        jmp     interrupt_13
+        jmp     interrupt_14
+        jmp     interrupt_15
+        jmp     interrupt_16
+        jmp     interrupt_17
+        jmp     interrupt_18
+        jmp     interrupt_19
+        jmp     interrupt_20
+        jmp     interrupt_21
+        jmp     interrupt_22
+        jmp     interrupt_23
+        jmp     interrupt_24
+        jmp     interrupt_25
+        jmp     interrupt_26
+        jmp     interrupt_27
+        jmp     interrupt_28
+        jmp     interrupt_29
+        jmp     interrupt_30
+        jmp     interrupt_31
+        jmp     __PMSIZE-8				#Interrupt vector 32 (NMI)
+# ]] END Interrupt Vector Table
+
+codestart:
+        jmp    init
+        
+.global _exithook
+_exithook:               # Debugger uses '_exithook' at 0x90 to catch program exit
+        return
+        
+init:
+        # Disable all interrupts
+        ldk     $r0,0x80
+.ifdef __FT930__
+        sta.b   0x10123, $r0
+.else
+        sta.b   0x100e3,$r0
+.endif
+        
+        # Reset all peripherals
+        # lda.l   $r0, 0x10018
+        # bins.l  $r0, $r0, 0x23F  # Set bit 31
+        # sta.l   0x10018, $r0
+        
+        # Initialize DATA by copying from program memory
+        ldk.l   $r0,__data_load_start
+        ldk.l   $r1,__data_load_end
+        ldk.l   $r2,0   # Will use __data after binutils patch
+
+        jmp     .dscopy
+.dsloop:
+        # Copy PM[$r0] to RAM $r2
+        lpmi.l  $r3,$r0,0
+        sti.l   $r2,0,$r3
+        add.l   $r0,$r0,4
+        add.l   $r2,$r2,4
+.dscopy:
+        cmp.l   $r0,$r1
+        jmpc    lt,.dsloop
+
+        # Zero BSS
+        ldk.l   $r0,_bss_start
+        ldk.l   $r2,_end
+        sub.l   $r2,$r2,$r0
+        ldk.l   $r1,0
+        ldk    $r3,32764
+1:
+        cmp    $r2,$r3
+        jmpc   lt,2f
+        memset $r0,$r1,$r3
+        add    $r0,$r0,$r3
+        sub    $r2,$r2,$r3
+        jmp    1b
+2:
+        memset $r0,$r1,$r2
+.ifdef __FT930__
+/*##############################################################*/
+		# copy UserConfig DATA from flash to mailbox memory
+/*##############################################################*/
+        ldk.l   $r0,D2XX_Struct_start  /*start of d2xx config in PM memory */
+        ldk.l   $r1,D2XX_Struct_end /*end of d2xx config in PM memory */
+        ldk.l   $r2,D2XXTEST_UserD2xxConfig /* RAM cache where the d2xx config from PM to be copied*/
+        jmp     .configcopy
+
+.configloop:
+        # Copy PM[$r0] to RAM[$r2]
+        lpmi.l  $r3,$r0,0
+        sti.l   $r2,0,$r3
+        # Increment
+        add.l   $r0,$r0,4
+        add.l   $r2,$r2,4
+.configcopy:
+        cmp.l   $r0,$r1
+        jmpc    lt,.configloop
+
+        ldk.l   $r1,D2XX_Struct_start
+        ldk.l   $r2,D2XX_Struct_end
+        #compute size
+        sub.l   $r2,$r2,$r1
+        ldk.l   $r1,D2XXTEST_UserD2xxConfig
+        ldk.l   $r0,MAILBOX_MEMORY		/* D2xx config from RAM cache to be copied to Mailbox memory */
+        # Copy RAM[$r1] to Mailbox $r0, for $r2 bytes
+        streamouti.b   $r0,$r1,$r2
+/*############################################################*/
+.endif
+        sub.l   $sp,$sp,24  # Space for the caller argument frame
+        call    main
+
+.equ EXITEXIT    , 0x1fffc
+
+.global _exit
+_exit:
+        sta.l   EXITEXIT,$r0    # simulator end of test
+        jmp     _exithook
+
+#_watchdog_isr:
+#        ldk     $sp,__RAMSIZE
+#        jmp     __PMSIZE-4
+
+# Macro to construct the interrupt stub code.
+# it just saves r0, loads r0 with the int vector
+# and branches to interrupt_common.
+
+.macro  inth i=0
+interrupt_\i:
+        push    $r0     # {
+        lda     $r0,(vector_table + 4 * \i)
+        jmp     interrupt_common
+.endm
+
+        inth    0
+        inth    1
+        inth    2
+        inth    3
+        inth    4
+        inth    5
+        inth    6
+        inth    7
+        inth    8
+        inth    9
+        inth    10
+        inth    11
+        inth    12
+        inth    13
+        inth    14
+        inth    15
+        inth    16
+        inth    17
+        inth    18
+        inth    19
+        inth    20
+        inth    21
+        inth    22
+        inth    23
+        inth    24
+        inth    25
+        inth    26
+        inth    27
+        inth    28
+        inth    29
+        inth    30
+        inth    31
+        inth    32
+        inth    33
+
+        # On entry: r0, already saved, holds the handler function
+interrupt_common:
+        push    $r1     # {
+        push    $r2     # {
+        push    $r3     # {
+        push    $r4     # {
+        push    $r5     # {
+        push    $r6     # {
+        push    $r7     # {
+        push    $r8     # {
+        push    $r9     # {
+        push    $r10    # {
+        push    $r11    # {
+        push    $r12    # {
+        push    $cc     # {
+
+        calli   $r0
+
+        pop     $cc     # }
+        pop     $r12    # }
+        pop     $r11    # }
+        pop     $r10    # }
+        pop     $r9     # }
+        pop     $r8     # }
+        pop     $r7     # }
+        pop     $r6     # }
+        pop     $r5     # }
+        pop     $r4     # }
+        pop     $r3     # }
+        pop     $r2     # }
+        pop     $r1     # }
+        pop     $r0     # } matching push in interrupt_0-31 above
+        reti
+
+        # Null function for unassigned interrupt to point at
+.global     nullvector
+nullvector:
+        return
+
+.section .data
+.global vector_table
+	.align (4)			# assembler alignment is in the power of 2 (in this case 2^4)
+vector_table:
+        .rept 34
+                .long   nullvector
+        .endr
+
+
+.section .text
+.global __gxx_personality_sj0
+__gxx_personality_sj0:
+
+
+	.section ._flash_d2xx_config
+.global __pD2XXDefaultConfiguration
+	.align (10)
+
+D2XX_partition_start = .
+
+.if IS_IMG_D2XX_PRESENT
+.ifdef __FT930__
+.include "ft930_d2xx_default_config.inc"
+.else
+.include "ft900_d2xx_default_config.inc"
+.endif
+.endif
+
+D2XX_partition_end = .
+
+	.section ._flash_dlog_partition
+	.align (10)
+.global __dlog_partition
+__dlog_partition:
+dlog_partition_start = .
+.if IS_IMG_DLOG_PRESENT
+	.long	0xF7D1D106
+	.rept  (0x1000-4)
+	.byte	0xFF
+	.endr
+.endif
+dlog_partition_end = .
+
+	.section ._pm
+.global	__sdbl_partition_sizeof
+.global __D2XX_partition_sizeof
+.global __dlog_partition_sizeof
+	.if IS_IMG_SDBL_PRESENT
+__sdbl_partition_sizeof = 0x2000
+	.else
+__sdbl_partition_sizeof = 0
+	.endif
+
+__D2XX_partition_sizeof = D2XX_partition_end - D2XX_partition_start
+__dlog_partition_sizeof = dlog_partition_end - dlog_partition_start
diff --git a/hw/mcu/bridgetek/ft90x/hardware/scripts/ldscript.ld b/hw/mcu/bridgetek/ft90x/hardware/scripts/ldscript.ld
new file mode 100644
index 000000000..d1b4d46cd
--- /dev/null
+++ b/hw/mcu/bridgetek/ft90x/hardware/scripts/ldscript.ld
@@ -0,0 +1,94 @@
+/* Default linker script, for normal executables */
+OUTPUT_FORMAT("elf32-ft32")
+OUTPUT_ARCH(ft32)
+SEARCH_DIR("/data/win8/ft32/ft32-elf/lib");
+/* Allow the command line to override the memory region sizes.  */
+__PMSIZE = DEFINED(__PMSIZE)  ? __PMSIZE : 256K;
+__RAMSIZE = DEFINED(__RAMSIZE) ? __RAMSIZE : 64K;
+MEMORY
+{
+  flash     (rx)   : ORIGIN = 0,        LENGTH = __PMSIZE
+  ram       (rw!x) : ORIGIN = 0x800000, LENGTH = __RAMSIZE
+}
+SECTIONS
+{
+  .text :
+  {
+    *(.text*)
+    *(.strings)
+    *(._pm*)
+    *(.init)
+    *(.fini)
+     _etext = . ;
+    . = ALIGN(4);
+  }  > flash
+  .tors :
+  {
+    ___ctors = . ;
+    *(.ctors)
+    ___ctors_end = . ;
+    ___dtors = . ;
+    *(.dtors)
+    ___dtors_end = . ;
+    . = ALIGN(4);
+  } > ram
+  .data :  AT (ADDR (.text) + SIZEOF (.text))
+  {
+    *(.data)
+    *(.data*)
+    *(.rodata)
+    *(.rodata*)
+     _edata = . ;
+    . = ALIGN(4);
+  }  > ram
+  .bss   SIZEOF(.data) + ADDR(.data) :
+  {
+     _bss_start = . ;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+     _end = . ;
+    . = ALIGN(4);
+  }  > ram
+   __data_load_start = LOADADDR(.data);
+   __data_load_end = __data_load_start + SIZEOF(.data);
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* DWARF 3 */
+  .debug_pubtypes 0 : { *(.debug_pubtypes) }
+  .debug_ranges   0 : { *(.debug_ranges) }
+  /* DWARF Extension.  */
+  .debug_macro    0 : { *(.debug_macro) }
+  .debug_addr     0 : { *(.debug_addr) }
+}
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index a35fc0ac5..638a17814 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -151,6 +151,13 @@
 #elif TU_CHECK_MCU(GD32VF103)
   #define DCD_ATTR_ENDPOINT_MAX   4
 
+//------------- BridgeTek -------------//
+#elif TU_CHECK_MCU(FT90X)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
+#elif TU_CHECK_MCU(FT93X)
+  #define DCD_ATTR_ENDPOINT_MAX   16
+
 #else
   #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define DCD_ATTR_ENDPOINT_MAX   8
diff --git a/src/portable/bridgetek/ft90x/dcd_ft90x.c b/src/portable/bridgetek/ft90x/dcd_ft90x.c
new file mode 100644
index 000000000..ac13f11d1
--- /dev/null
+++ b/src/portable/bridgetek/ft90x/dcd_ft90x.c
@@ -0,0 +1,1101 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+#include "bsp/board.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_FT90X
+
+#define USBD_USE_STREAMS
+
+#include <stdint.h>
+#include <errno.h>
+#include <ft900.h>
+#include <registers/ft900_registers.h>
+
+#include "device/dcd.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+// Board code will determine the state of VBUS from USB host.
+extern int8_t board_ft90x_vbus(void);
+
+// Static array to store an incoming SETUP request for processing by tinyusb.
+static uint8_t _ft90x_setup_packet[8];
+
+struct ft90x_xfer_state
+{
+  volatile int16_t total_size; // Total transfer size in bytes for this transfer.
+  volatile int16_t remain_size; // Total remaining in transfer.
+  volatile uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
+  volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
+
+  uint8_t type; // Endpoint type. Of type USBD_ENDPOINT_TYPE from endpoint descriptor.
+  uint8_t dir; // Endpoint direction. TUSB_DIR_OUT or TUSB_DIR_IN. For control endpoint this is the current direction.
+  uint16_t buff_size; // Actual size of buffer RAM used by endpoint.
+  uint16_t size; // Max packet size for endpoint from endpoint descriptor.
+};
+// Endpoint description array for each endpoint.
+static struct ft90x_xfer_state ep_xfer[USBD_MAX_ENDPOINT_COUNT];
+// USB speed.
+static tusb_speed_t _speed;
+
+// Interrupt handlers.
+void _ft90x_usbd_ISR(void); // Interrupt handler for USB device.
+void ft90x_usbd_pm_ISR(void); // Interrupt handler for USB device for power management (called by board).
+
+// Internal functions forward declarations.
+static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes);
+static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes);
+static void _ft90x_reset_edpts(void);
+static inline void _ft90x_phy_enable(bool en);
+static void _ft90x_usb_speed(void);
+static void _dcd_ft90x_attach(void);
+static void _dcd_ft90x_detach(void) __attribute__((unused));
+static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length);
+static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length);
+
+// Internal functions.
+
+// Manage an OUT transfer from the host.
+// This can be up-to the maximum packet size of the endpoint.
+// Continuation of a transfer beyond the maximum packet size is performed 
+// by the interrupt handler.
+static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
+{
+  //Note: this is called from only the interrupt handler when an OUT transfer is called.
+  uint16_t ep_size = ep_xfer[ep_number].size;
+  (void)ep_size;
+  if (xfer_bytes > ep_size)
+  {
+    xfer_bytes = ep_size;
+  }
+
+  // Wait until the endpoint has finished - it should be complete!
+  //while (!(USBD_EP_SR_REG(ep_number) & MASK_USBD_EPxSR_OPRDY))
+    //;
+
+  // Send the first packet of max packet size
+  xfer_bytes = _ft90x_dusb_out(ep_number, (uint8_t *)buffer, xfer_bytes);
+  if (ep_number == USBD_EP_0)
+  {
+    // Set flags to indicate data ready.
+    USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_OPRDY);
+  }
+  else
+  {
+    USBD_EP_SR_REG(ep_number) = (MASK_USBD_EPxSR_OPRDY);
+  }
+
+  return xfer_bytes;
+}
+
+// Manage an IN transfer to the host.
+// This can be up-to the maximum packet size of the endpoint.
+// Continuation of a transfer beyond the maximum packet size is performed 
+// by the interrupt handler.
+static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
+{
+  //Note: this may be called from the interrupt handler or from normal code.
+  uint8_t end = 0;
+  uint16_t ep_size = ep_xfer[ep_number].size;
+  (void)ep_size;
+  if ((xfer_bytes == 0) || (xfer_bytes < ep_size))
+  {
+    end = 1;
+  }
+  else
+  {
+    xfer_bytes = ep_size;
+  }
+
+  if (ep_number == USBD_EP_0)
+  {
+    // An IN direction SETUP can be interrupted by an OUT packet.
+    // This will result in a STALL generated by the silicon.
+    while (USBD_EP_SR_REG(USBD_EP_0) & MASK_USBD_EP0SR_STALL)
+    {
+      // Clear the STALL and finish the transaction.
+      USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_STALL);
+    }
+  }
+  else
+  {
+    uint8_t sr_reg;
+    // If there is data to transmit then wait until the IN buffer
+    // for the endpoint is empty.
+    do
+    {
+      sr_reg = USBD_EP_SR_REG(ep_number);
+    } while (sr_reg & MASK_USBD_EPxSR_INPRDY);
+    
+  }
+
+  xfer_bytes = _ft90x_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes);
+
+  if (ep_number == USBD_EP_0)
+  {
+    if (end)
+    {
+      // Set flags to indicate data ready and transfer complete.
+      USBD_EP_SR_REG(USBD_EP_0) = MASK_USBD_EP0SR_INPRDY | MASK_USBD_EP0SR_DATAEND;
+    }
+    else
+    {
+      // Set flags to indicate data ready.
+      USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_INPRDY);
+    }
+  }
+  else
+  {
+    // Set flags to indicate data ready.
+    USBD_EP_SR_REG(ep_number) = (MASK_USBD_EPxSR_INPRDY);
+  }
+
+  return xfer_bytes;
+}
+
+// Reset all endpoints to a default state. 
+// Control endpoint enabled and ready. All others disabled.
+static void _ft90x_reset_edpts(void)
+{
+  // Disable all endpoints and remove configuration values.
+    // Clear settings.
+  tu_memclr(ep_xfer, sizeof(ep_xfer));
+  for (int i = 0; i < USBD_MAX_ENDPOINT_COUNT; i++)
+  {
+    // Disable hardware.
+    USBD_EP_CR_REG(i) = 0;
+  }
+  
+  // Setup the control endpoint only.
+#if CFG_TUD_ENDPOINT0_SIZE == 64
+  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_64 << BIT_USBD_EP0_MAX_SIZE);
+#elif CFG_TUD_ENDPOINT0_SIZE == 32
+  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_32 << BIT_USBD_EP0_MAX_SIZE);
+#elif CFG_TUD_ENDPOINT0_SIZE == 16
+  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_16 << BIT_USBD_EP0_MAX_SIZE);
+#elif CFG_TUD_ENDPOINT0_SIZE == 8
+  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_8 << BIT_USBD_EP0_MAX_SIZE);
+#else
+#error "CFG_TUD_ENDPOINT0_SIZE must be defined with a value of 8, 16, 32 or 64."
+#endif
+  // Configure the control endpoint.
+  ep_xfer[USBD_EP_0].size = CFG_TUD_ENDPOINT0_SIZE;
+  ep_xfer[USBD_EP_0].type = TUSB_XFER_CONTROL;
+
+  // Enable interrupts from USB device control.
+  USBD_REG(cmie) = MASK_USBD_CMIE_ALL;
+  // Enable interrupts on EP0.
+  USBD_REG(epie) = (MASK_USBD_EPIE_EP0IE);
+}
+
+// Enable or disable the USB PHY.
+static inline void _ft90x_phy_enable(bool en)
+{
+  if (en)
+    SYS->PMCFG_L |= MASK_SYS_PMCFG_DEV_PHY_EN;
+  else
+    SYS->PMCFG_L &= ~MASK_SYS_PMCFG_DEV_PHY_EN;
+}
+
+// Safely connect to the USB.
+static void _dcd_ft90x_attach(void)
+{
+  uint8_t reg;
+
+  CRITICAL_SECTION_BEGIN
+  // Disable device responses.
+  USBD_REG(faddr) = 0;
+
+  // Reset USB Device.
+  SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_DEV_RESET_ALL;
+  // Disable device connect/disconnect/host reset detection.
+  SYS->PMCFG_H = MASK_SYS_PMCFG_DEV_DIS_DEV;
+  SYS->PMCFG_H = MASK_SYS_PMCFG_DEV_CONN_DEV;
+  SYS->PMCFG_L = SYS->PMCFG_L & (~MASK_SYS_PMCFG_DEV_DETECT_EN);
+
+  // Enable Chip USB device clock/PM configuration.
+  sys_enable(sys_device_usb_device);
+  CRITICAL_SECTION_END;
+
+  // Wait a short time to get started.
+  delayms(1);
+
+  CRITICAL_SECTION_BEGIN
+  // Turn off the device enable bit.
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED
+  USBD_REG(fctrl) = 0;
+#else
+  //Set the full speed only bit if required.
+  USBD_REG(fctrl) = MASK_USBD_FCTRL_MODE_FS_ONLY;
+#endif
+
+  // Clear first reset and suspend interrupts.
+  do
+  {
+    reg = USBD_REG(cmif);
+    USBD_REG(cmif) = reg;
+  } while (reg);
+  // Clear any endpoint interrupts.
+  reg = USBD_REG(epif);
+  USBD_REG(epif) = reg;
+
+  // Disable all interrupts from USB device control before attaching interrupt.
+  USBD_REG(cmie) = 0;
+  CRITICAL_SECTION_END;
+
+  // Enable device connect/disconnect/host reset detection.
+  // Set device detect and remote wakeup enable interrupt enables.
+  SYS->PMCFG_L = SYS->PMCFG_L | MASK_SYS_PMCFG_DEV_DETECT_EN;
+
+#if defined(__FT930__)
+  // Setup VBUS detect
+  SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_USB_VBUS_EN;
+#endif
+}
+
+// Gracefully disconnect from the USB.
+static void _dcd_ft90x_detach(void)
+{
+  // Disable device connect/disconnect/host reset detection.
+  SYS->PMCFG_L = SYS->PMCFG_L & (~MASK_SYS_PMCFG_DEV_DETECT_EN);
+
+#if defined(__FT930__)
+  // Disable VBUS detection.
+  SYS->MSC0CFG = SYS->MSC0CFG & (~MASK_SYS_MSC0CFG_USB_VBUS_EN);
+#endif
+  CRITICAL_SECTION_BEGIN
+  USBD_REG(epie) = 0;
+  USBD_REG(cmie) = 0;
+  CRITICAL_SECTION_END;
+
+  // Disable the USB function.
+  USBD_REG(fctrl) = 0;
+  delayms(1);
+
+  // Disable USB PHY
+  dcd_disconnect(0);
+  delayms(1);
+
+  // Disable Chip USB device clock/PM configuration.
+  sys_disable(sys_device_usb_device);
+
+  // Reset USB Device... Needed for Back voltage D+ to be <400mV
+  SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_DEV_RESET_ALL;
+
+  delayms(1);
+  // Set device detect and remote wakeup enable interrupt enables.
+  SYS->PMCFG_L = SYS->PMCFG_L | MASK_SYS_PMCFG_DEV_DETECT_EN;
+
+#if defined(__FT930__)
+  // Setup VBUS detect
+  SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_USB_VBUS_EN;
+#endif
+}
+
+// Determine the speed of the USB to which we are connected.
+// Set the speed of the PHY accordingly. 
+// High speed can be disabled through CFG_TUSB_RHPORT0_MODE settings.
+static void _ft90x_usb_speed(void)
+{
+	uint8_t  fctrl_val;
+
+	// If USB device function is already enabled then disable it.
+	if (USBD_REG(fctrl) & MASK_USBD_FCTRL_USB_DEV_EN) {
+		USBD_REG(fctrl) = (USBD_REG(fctrl) & (~MASK_USBD_FCTRL_USB_DEV_EN));
+		delayus(200);
+	}
+
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED
+
+	/* Detect high or full speed */
+	fctrl_val = MASK_USBD_FCTRL_USB_DEV_EN;
+#if defined(__FT900__)
+	if (!sys_check_ft900_revB())//if 90x series is rev C
+	{
+		fctrl_val |= MASK_USBD_FCTRL_IMP_PERF;
+	}
+#endif
+	USBD_REG(fctrl) = fctrl_val;
+
+#if defined(__FT930__)
+	delayus(200);
+
+	_speed = (SYS->MSC0CFG & MASK_SYS_MSC0CFG_HIGH_SPED_MODE) ?
+		TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
+#else /* __FT930__ */
+	/* Detection by SOF */
+	while (!(USBD_REG(cmif) & MASK_USBD_CMIF_SOFIRQ));
+	USBD_REG(cmif) = MASK_USBD_CMIF_SOFIRQ;
+	delayus(125 + 5);
+	_speed = (USBD_REG(cmif) & MASK_USBD_CMIF_SOFIRQ) ?
+		TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
+  dcd_event_bus_reset(0, _speed, true);
+
+#endif /* !__FT930__ */
+
+#else /* CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED */
+
+	/* User force set to full speed */
+  _speed = TUSB_SPEED_FULL;
+  fctrl_val =
+			MASK_USBD_FCTRL_USB_DEV_EN | MASK_USBD_FCTRL_MODE_FS_ONLY;
+#if defined(__FT900__)
+	if (!sys_check_ft900_revB())//if 90x series is rev C
+	{
+			fctrl_val |= MASK_USBD_FCTRL_IMP_PERF;
+	}
+#endif
+	USBD_REG(fctrl) = fctrl_val;
+  dcd_event_bus_reset(0, _speed, true);
+	return;
+
+#endif /* CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED */
+}
+
+// Send a buffer to the USB IN FIFO.
+// When the macro USBD_USE_STREAMS is defined this will stream a buffer of data 
+// to the FIFO using the most efficient MCU streamout combination.
+// If streaming is disabled then it will send each byte of the buffer in turn 
+// to the FIFO. The is no reason to not stream.
+// The total number of bytes sent to the FIFO is returned.
+static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length)
+{
+  uint16_t bytes_read = 0;
+  uint16_t buff_size = length;
+  
+#ifdef USBD_USE_STREAMS
+  volatile uint8_t *data_reg;
+
+  data_reg = (uint8_t *)&(USBD->ep[ep_number].epxfifo);
+  if (buff_size)
+  {
+    if (((uint32_t)buffer) % 4 == 0)
+    {
+      uint16_t aligned = buff_size & (~3);
+      uint16_t left = buff_size & 3;
+
+      if (aligned)
+      {
+        __asm__ volatile("streamout.l %0,%1,%2"
+                         :
+                         : "r"(data_reg), "r"(buffer), "r"(aligned));
+        buffer += aligned;
+      }
+      if (left)
+      {
+        __asm__ volatile("streamout.b %0,%1,%2"
+                         :
+                         : "r"(data_reg), "r"(buffer), "r"(left));
+      }
+    }
+    else
+    {
+      __asm__ volatile("streamout.b %0,%1,%2"
+                       :
+                       : "r"(data_reg), "r"(buffer), "r"(buff_size));
+    }
+    bytes_read = buff_size;
+  }
+#else // USBD_USE_STREAMS
+  
+  bytes_read = buff_size;
+  while (buff_size--)
+  {
+    USBD_EP_FIFO_REG(ep_number) = *buffer++;
+  };
+
+#endif // USBD_USE_STREAMS
+
+  return bytes_read;
+}
+
+// Receive a buffer from the USB OUT FIFO.
+// When the macro USBD_USE_STREAMS is defined this will stream from the FIFO
+// to a buffer of data using the most efficient MCU streamin combination.
+// If streaming is disabled then it will receive each byte from the FIFO in turn 
+// to the buffer. The is no reason to not stream.
+// The total number of bytes received from the FIFO is returned.
+static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length)
+{
+#ifdef USBD_USE_STREAMS
+  volatile uint8_t *data_reg;
+#endif // USBD_USE_STREAMS
+  uint16_t bytes_read = 0;
+  uint16_t buff_size = length;
+  
+  if (length > 0)
+  {
+    if (ep_number == USBD_EP_0)
+    {
+      buff_size = USBD_EP_CNT_REG(USBD_EP_0);
+    }
+    else
+    {
+      if (USBD_EP_SR_REG(ep_number) & (MASK_USBD_EPxSR_OPRDY))
+      {
+        buff_size = USBD_EP_CNT_REG(ep_number);
+      }
+    }
+  }
+
+  // Only read as many bytes as we have space for.
+  if (buff_size > length)
+    buff_size = length;
+
+#ifdef USBD_USE_STREAMS
+  data_reg = (uint8_t *)&(USBD->ep[ep_number].epxfifo);
+  if (buff_size)
+  {
+    if ((uint32_t)buffer % 4 == 0)
+    {
+      uint16_t aligned = buff_size & (~3);
+      uint16_t left = buff_size & 3;
+
+      if (aligned)
+      {
+        __asm__ volatile("streamin.l %0,%1,%2"
+                         :
+                         : "r"(buffer), "r"(data_reg), "r"(aligned));
+        buffer += aligned;
+      }
+      if (left)
+      {
+        __asm__ volatile("streamin.b %0,%1,%2"
+                         :
+                         : "r"(buffer), "r"(data_reg), "r"(left));
+      }
+    }
+    else
+    {
+      __asm__ volatile("streamin.b %0,%1,%2"
+                       :
+                       : "r"(buffer), "r"(data_reg), "r"(buff_size));
+    }
+    bytes_read = buff_size;
+  }
+#else // USBD_USE_STREAMS
+
+  bytes_read = buff_size;
+  while (buff_size--)
+  {
+    *buffer++ = USBD_EP_FIFO_REG(ep_number);
+  }
+
+#endif // USBD_USE_STREAMS
+
+  return bytes_read;
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+
+// Initialize controller to device mode
+void dcd_init(uint8_t rhport)
+{
+  TU_LOG2("FT90x initialisation\r\n");
+
+  _dcd_ft90x_attach();
+
+  //_ft90x_reset_edpts(void);//tu_memclr(ep_xfer, sizeof(ep_xfer));
+
+  interrupt_attach(interrupt_usb_device, (int8_t)interrupt_usb_device, _ft90x_usbd_ISR);
+
+  dcd_connect(rhport);
+}
+
+// Enable device interrupt
+void dcd_int_enable(uint8_t rhport)
+{
+  (void)rhport;
+  TU_LOG3("FT90x int enable\r\n");
+
+  // Peripheral devices interrupt enable.
+  interrupt_enable_globally();
+}
+
+// Disable device interrupt
+void dcd_int_disable(uint8_t rhport)
+{
+  (void)rhport;
+  TU_LOG3("FT90x int disable\r\n");
+
+  // Peripheral devices interrupt disable.
+  interrupt_disable_globally();
+}
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void)rhport;
+  (void)dev_addr;
+
+  // Respond with status. There is no checking that the address is in range.
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+
+  // Set the update bit for the address register.
+  dev_addr |= 0x80;
+
+  // Modify the address register within a critical section.
+  CRITICAL_SECTION_BEGIN
+  {
+    USBD_REG(faddr) = dev_addr;
+  }
+  CRITICAL_SECTION_END;
+}
+
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+#if 0 // never called
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+  (void) rhport;
+
+  if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+      request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD )
+  {
+    if (request->bRequest == TUSB_REQ_SET_ADDRESS)
+    {
+    }
+    else if (request->bRequest == TUSB_REQ_SET_CONFIGURATION)
+    {
+    }
+  }
+}
+#endif // 0
+
+// Wake up host
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void)rhport;
+
+  SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
+
+  // Atleast 2 ms of delay needed for RESUME Data K state.
+  delayms(2); 
+
+  SYS->MSC0CFG &= ~MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
+
+  // Enable USB PHY and determine current bus speed.
+  dcd_connect(0);
+}
+
+// Connect by enabling internal pull-up resistor on D+/D-
+void dcd_connect(uint8_t rhport)
+{
+  (void)rhport;
+  TU_LOG2("FT90x connect\r\n");
+
+  CRITICAL_SECTION_BEGIN
+  // Is device connected?
+  if (board_ft90x_vbus())
+  {
+    // Clear/disable address register.
+    USBD_REG(faddr) = 0;
+    _ft90x_phy_enable(true);
+
+    // Determine bus speed and signal speed to tusb.
+    _ft90x_usb_speed();
+  }
+  CRITICAL_SECTION_END;
+  
+  // Restore default endpoint state.
+  _ft90x_reset_edpts();
+}
+
+// Disconnect by disabling internal pull-up resistor on D+/D-
+void dcd_disconnect(uint8_t rhport)
+{
+  (void)rhport;
+  TU_LOG2("FT90x disconnect\r\n");
+
+  // Disable the USB PHY.
+  _ft90x_phy_enable(false);
+}
+
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
+{
+  (void)rhport;
+  uint8_t const ep_number = tu_edpt_number(ep_desc->bEndpointAddress);
+  uint8_t const ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
+  uint8_t const ep_type = ep_desc->bmAttributes.xfer;
+  uint16_t const ep_size = ep_desc->wMaxPacketSize.size;
+  uint16_t ep_buff_size;
+  uint8_t ep_reg_size = USBD_EP_MAX_SIZE_8;
+  uint8_t ep_reg_data = 0;
+  int16_t total_ram;
+
+  TU_LOG2("FT90x endpoint open %d %c\r\n", ep_number, ep_dir?'I':'O');
+
+  // Check that the requested endpoint number is allowable.
+  if (ep_number >= USBD_MAX_ENDPOINT_COUNT)
+  {
+    TU_LOG1("FT90x endpoint not valid: requested %d max %d\r\n", ep_number, USBD_MAX_ENDPOINT_COUNT);
+    return false;
+  }
+
+  // Calculate the physical size of the endpoint as a power of 2. This may be more than
+  // the requested size.
+  while (ep_desc->wMaxPacketSize.size > (8 * (1 << ep_reg_size)))
+  {
+    ep_reg_size++;
+  }
+  if (ep_reg_size > USBD_EP_MAX_SIZE_1024)
+  {
+    TU_LOG1("FT90x endpoint size not valid: requested %d max 1024\r\n", ep_desc->wMaxPacketSize.size);
+    return false;
+  }
+  // Calculate actual amount of buffer RAM used by this endpoint. This may be more than the 
+  // requested size.
+  ep_buff_size = 8 << ep_reg_size;
+
+  if (ep_number > 0)
+  {
+    // Set EP cmd parameters...
+    ep_reg_data |= (ep_reg_size << BIT_USBD_EP_MAX_SIZE);
+
+    if (ep_xfer[ep_number].type != USBD_EP_TYPE_DISABLED)
+    {
+      // This could be because an endpoint has been assigned with the same number.
+      // On FT90x, IN and OUT endpoints may not have the same number. e.g. There 
+      // cannot been an 0x81 and 0x01 endpoint.
+      TU_LOG1("FT90x endpoint %d already assigned\r\n", ep_number);
+      return false;
+    }
+
+    // Check that there is enough buffer RAM to allocate to this new endpoint.
+    // Available buffer RAM depends on the device revision.
+    // The IN and OUT buffer RAM should be the same size.
+    if (ep_dir == USBD_DIR_IN) 
+      total_ram = USBD_RAMTOTAL_IN;
+    else
+      total_ram = USBD_RAMTOTAL_OUT;
+    // Work out how much has been allocated to existing endpoints.
+    // The total RAM allocated shoudl alsyes be a positive number as this
+    // algorithm should not let it go below zero.
+    for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++)
+    {
+      if (ep_xfer[i].type != USBD_EP_TYPE_DISABLED)
+      {
+        if (ep_xfer[i].dir == ep_dir)
+        {
+          total_ram -= ep_xfer[i].buff_size;
+        }
+      }
+    }
+    // The control endpoint is taken into account as well.
+    total_ram -= ep_xfer[0].buff_size;
+    // Make sure we have enough space. The corner case is having zero bytes
+    // free which means that total_ram must be signed as zero bytes free is
+    // allowable.
+    if (total_ram < ep_buff_size)
+    {
+      TU_LOG1("FT90x insufficient buffer RAM for endpoint %d\r\n", ep_number);
+      return false;    
+    }
+
+    // Set the type of this endpoint in the control register.
+    if (ep_type == USBD_EP_BULK)
+      ep_reg_data |= (USBD_EP_DIS_BULK << BIT_USBD_EP_CONTROL_DIS);
+    else if (ep_type == USBD_EP_INT)
+      ep_reg_data |= (USBD_EP_DIS_INT << BIT_USBD_EP_CONTROL_DIS);
+    else if (ep_type == USBD_EP_ISOC)
+      ep_reg_data |= (USBD_EP_DIS_ISO << BIT_USBD_EP_CONTROL_DIS);
+    // Set the direction of this endpoint in the control register.
+    if (ep_dir == USBD_DIR_IN)
+      ep_reg_data |= MASK_USBD_EPxCR_DIR;
+    // Do not perform double buffering.
+    //if (<double buffering flag> != USBD_DB_OFF)
+    //ep_reg_data |= MASK_USBD_EPxCR_DB;
+    // Set the control endpoint for this endpoint.
+    USBD_EP_CR_REG(ep_number) = ep_reg_data;
+    TU_LOG2("FT90x endpoint setting %x\r\n", ep_reg_data);
+  }
+  else
+  {
+    // Set the control register for endpoint zero.
+    USBD_EP_CR_REG(USBD_EP_0) = (ep_reg_size << BIT_USBD_EP0_MAX_SIZE);
+  }
+
+  // Store the endpoint characteristics for later reference.
+  ep_xfer[ep_number].dir = ep_dir;
+  ep_xfer[ep_number].type = ep_type;
+  ep_xfer[ep_number].size = ep_size;
+  ep_xfer[ep_number].buff_size = ep_buff_size;
+
+  CRITICAL_SECTION_BEGIN
+  // Clear register transaction continuation and signalling state.
+  ep_xfer[ep_number].valid = 0;
+  ep_xfer[ep_number].buff_ptr = NULL;
+  ep_xfer[ep_number].total_size = 0;
+  ep_xfer[ep_number].remain_size = 0;
+  CRITICAL_SECTION_END
+
+  return true;
+}
+
+// Close all endpoints.
+void dcd_edpt_close_all(uint8_t rhport)
+{
+  (void)rhport;
+  // Reset the endpoint configurations.
+  _ft90x_reset_edpts();
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+  uint8_t ep_number = tu_edpt_number(ep_addr);
+  uint8_t dir = tu_edpt_dir(ep_addr);
+  uint16_t xfer_bytes;
+  bool status = false;
+
+  // We will attempt to transfer the buffer. If it is less than or equal to the  endpoint
+  // maximum packet size then the whole buffer will be transferred. If it is larger then
+  // the interrupt handler will transfer the remainder.
+  // ep_xfer is used to tell the interrupt handler what to do.
+  // ep_xfer can be used at interrupt level to continue transfers.
+  CRITICAL_SECTION_BEGIN
+  // Transfer currently in progress.
+  if (ep_xfer[ep_number].valid == 0)
+  {
+    status = true;
+
+    ep_xfer[ep_number].total_size = total_bytes;
+    ep_xfer[ep_number].remain_size = total_bytes;
+    ep_xfer[ep_number].buff_ptr = buffer;
+    ep_xfer[ep_number].valid = 1;
+    
+    if (ep_number == USBD_EP_0)
+    {
+      ep_xfer[USBD_EP_0].dir = dir;
+    }
+    else
+    {
+      // Enable the interrupt for this endpoint allowing the interrupt handler to report
+      // continue the transfer and signal completion.
+      USBD_REG(epie) = USBD_REG(epie) | (1 << ep_number);
+    }
+
+    if (dir == TUSB_DIR_IN)
+    {
+      // For IN transfers send the first packet as a starter. Interrupt handler to complete
+      // this if it is larger than one packet.
+      xfer_bytes = _ft90x_edpt_xfer_in(ep_number, buffer, total_bytes);
+
+      ep_xfer[ep_number].buff_ptr += xfer_bytes;
+      ep_xfer[ep_number].remain_size -= xfer_bytes;
+    }
+  }
+  CRITICAL_SECTION_END
+  
+  return status;
+}
+
+// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes)
+{
+  (void)rhport;
+  (void)ep_addr;
+  (void)ff;
+  (void)total_bytes;
+  bool status = false;
+  return status;
+}
+
+// Stall endpoint (non-control endpoint)
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t ep_number = tu_edpt_number(ep_addr);
+  (void)rhport;
+
+  CRITICAL_SECTION_BEGIN
+  if (ep_number == USBD_EP_0)
+  {
+    USBD_EP_CR_REG(USBD_EP_0) = USBD_EP_CR_REG(USBD_EP_0) |
+                              MASK_USBD_EP0CR_SDSTL;
+  }
+  else
+  {
+    USBD_EP_CR_REG(ep_number) = USBD_EP_CR_REG(ep_number) |
+                              MASK_USBD_EPxCR_SDSTL;
+    USBD_EP_SR_REG(ep_number) = MASK_USBD_EPxSR_CLR_TOGGLE |
+                              MASK_USBD_EPxSR_FIFO_FLUSH;
+  }
+  CRITICAL_SECTION_END
+}
+
+// Clear stall (non-control endpoint), data toggle is also reset to DATA0 
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t ep_number = tu_edpt_number(ep_addr);
+  (void)rhport;
+
+  if (ep_number > USBD_EP_0)
+  {
+    CRITICAL_SECTION_BEGIN
+    USBD_EP_CR_REG(ep_number) = USBD_EP_CR_REG(ep_number) &
+                              (~MASK_USBD_EPxCR_SDSTL);
+    USBD_EP_SR_REG(ep_number) = MASK_USBD_EPxSR_CLR_TOGGLE;
+
+    // Allow transfers to restart.
+    ep_xfer[ep_number].valid = 0;
+    ep_xfer[ep_number].remain_size = 0;
+    CRITICAL_SECTION_END
+  }
+}
+
+// Interrupt handling.
+
+void _ft90x_usbd_ISR(void)
+{
+  tud_int_handler(0); // Resolves to dcd_int_handler().
+}
+
+void dcd_int_handler(uint8_t rhport)
+{
+  (void)rhport;
+
+  // Read the Common Interrupt Flag Register.
+  uint8_t cmif = USBD_REG(cmif);
+  // Read the Endpoint Interrupt Flag Register.
+#if defined(__FT930__)
+  // This is 16 bits on FT93x.
+  uint16_t epif = USBD_REG(epif);
+#else
+  // This is 8 bits on FT90x.
+  uint8_t epif = USBD_REG(epif);
+#endif
+
+  if (cmif & MASK_USBD_CMIF_ALL)
+  {
+    // Clear all CMIF bits.
+    USBD_REG(cmif) = MASK_USBD_CMIF_ALL;
+    if (cmif & MASK_USBD_CMIF_PHYIRQ) //Handle PHY interrupt
+    {
+    }
+    if (cmif & MASK_USBD_CMIF_PIDIRQ) //Handle PIDIRQ interrupt
+    {
+    }
+    if (cmif & MASK_USBD_CMIF_CRC16IRQ) //Handle CRC16IRQ interrupt
+    {
+    }
+    if (cmif & MASK_USBD_CMIF_CRC5IRQ) //Handle CRC5 interrupt
+    {
+    }
+    if (cmif & MASK_USBD_CMIF_RSTIRQ) //Handle Reset interrupt
+    {
+      // Reset endpoints to default state.
+      _ft90x_reset_edpts();
+      dcd_event_bus_reset(0, _speed, true);
+    }
+    if (cmif & MASK_USBD_CMIF_SUSIRQ) //Handle Suspend interrupt
+    {
+      dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+    }
+    if (cmif & MASK_USBD_CMIF_RESIRQ) //Handle Resume interrupt
+    {
+      dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+    }
+    if (cmif & MASK_USBD_CMIF_SOFIRQ) //Handle SOF interrupt
+    {
+      dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+    }
+  }
+  // Handle endpoint interrupts.
+  if (epif)
+  {
+    uint16_t xfer_bytes;
+
+    // Check for EP0 interrupts pending.
+    if (epif & MASK_USBD_EPIF_EP0IRQ)
+    {
+      // Clear interrupt register.
+      USBD_REG(epif) = MASK_USBD_EPIF_EP0IRQ;
+
+      // Test for an incoming SETUP request on the control endpoint.
+      if (USBD_EP_SR_REG(USBD_EP_0) & MASK_USBD_EP0SR_SETUP)
+      {
+        // If protocol STALL, End the STALL signalling.
+        if (USBD_EP_CR_REG(USBD_EP_0) & MASK_USBD_EP0CR_SDSTL)
+        {
+          // STALL end.
+          USBD_EP_CR_REG(USBD_EP_0) = USBD_EP_CR_REG(USBD_EP_0) &
+                                      (~MASK_USBD_EP0CR_SDSTL);
+          // Clear STALL send.
+          USBD_EP_SR_REG(USBD_EP_0) = MASK_USBD_EP0SR_STALL;
+        }
+
+        // Host has sent a SETUP packet. Recieve this into the setup packet store.
+        _ft90x_dusb_out(USBD_EP_0, (uint8_t *)_ft90x_setup_packet, sizeof(USB_device_request));
+        
+        // Send the packet to tinyusb.
+        dcd_event_setup_received(0, _ft90x_setup_packet, true);
+
+        // Clear the interrupt that signals a SETUP packet is received.
+        USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_SETUP);
+
+        // Allow new transfers on the control endpoint.
+        ep_xfer[USBD_EP_0].valid = 0;
+        return;
+      }
+      else
+      {
+        // Check for a complete or partially complete transfers on EP0.
+        if (ep_xfer[USBD_EP_0].valid)
+        {
+          xfer_bytes = (uint16_t)ep_xfer[USBD_EP_0].total_size;
+
+          // Transfer incoming data from an OUT packet to the buffer supplied.        
+          if (ep_xfer[USBD_EP_0].dir == TUSB_DIR_OUT)
+          { 
+            xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, (uint8_t *)ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
+          }
+          // Now signal completion of data packet.
+          dcd_event_xfer_complete(0, (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true);
+
+          // Allow new transfers on the control endpoint.
+          ep_xfer[USBD_EP_0].valid = 0;
+        }
+      }
+    }
+    else // !(epif & MASK_USBD_EPIF_EP0IRQ)
+    {
+      // Mask out currently disabled endpoints.
+      epif &= USBD_REG(epie);
+
+      // Handle complete and partially complete transfers for each endpoint.
+      for (uint8_t ep_number = 1; ep_number < USBD_MAX_ENDPOINT_COUNT; ep_number++)
+      {
+        if ((epif & MASK_USBD_EPIF_IRQ(ep_number)) == 0)
+        {
+          // No pending interrupt for this endpoint.
+          continue;
+        }
+
+        if (ep_xfer[ep_number].valid)
+        {
+          xfer_bytes = 0;
+          uint8_t ep_dirmask = (ep_xfer[ep_number].dir ? TUSB_DIR_IN_MASK : 0);
+
+          // Clear interrupt register for this endpoint.
+          USBD_REG(epif) = MASK_USBD_EPIF_IRQ(ep_number);
+
+          // Start or continue an OUT transfer.
+          if (ep_xfer[ep_number].dir == TUSB_DIR_OUT)
+          {
+            xfer_bytes = _ft90x_edpt_xfer_out(ep_number, 
+                            (uint8_t *)ep_xfer[ep_number].buff_ptr, 
+                            (uint16_t)ep_xfer[ep_number].remain_size);
+
+            ep_xfer[ep_number].buff_ptr += xfer_bytes;
+            ep_xfer[ep_number].remain_size -= xfer_bytes;
+          }
+          // continue an IN transfer
+          else // if (ep_xfer[ep_number].dir == TUSB_DIR_IN)
+          {
+            if (ep_xfer[ep_number].remain_size > 0)
+            {
+              xfer_bytes = _ft90x_edpt_xfer_in(ep_number, 
+                            (uint8_t *)ep_xfer[ep_number].buff_ptr, 
+                            (uint16_t)ep_xfer[ep_number].remain_size);
+
+              ep_xfer[ep_number].buff_ptr += xfer_bytes;
+              ep_xfer[ep_number].remain_size -= xfer_bytes;
+            }
+          }
+
+          // When the transfer is complete...
+          if (ep_xfer[ep_number].remain_size == 0)
+          {
+            // Signal tinyUSB.
+            dcd_event_xfer_complete(0, ep_number | ep_dirmask, ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
+
+            // Allow new transfers on this endpoint.
+            ep_xfer[ep_number].valid = 0;
+
+            // Disable the interrupt for this endpoint now it is complete.
+            USBD_REG(epie) = USBD_REG(epie) & (~(1 << ep_number));
+          }
+        }
+      }
+    }
+  }
+}
+
+// Power management interrupt handler. 
+// This handles USB device related power management interrupts only.
+void ft90x_usbd_pm_ISR(void)
+{
+    uint16_t pmcfg = SYS->PMCFG_H;
+
+  // Main interrupt handler is responible for 
+  if (pmcfg & MASK_SYS_PMCFG_DEV_CONN_DEV)
+  {
+      // Signal connection interrupt
+      SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
+      dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+  }
+
+  if (pmcfg & MASK_SYS_PMCFG_DEV_DIS_DEV)
+  {
+      // Signal disconnection interrupt
+      SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
+      dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
+  }
+
+  if (pmcfg & MASK_SYS_PMCFG_HOST_RST_DEV)
+  {
+      // Signal Host Reset interrupt
+      SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
+      dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+  }
+
+  if (pmcfg & MASK_SYS_PMCFG_HOST_RESUME_DEV)
+  {
+      // Signal Host Resume interrupt
+      SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
+      if (!(SYS->MSC0CFG & MASK_SYS_MSC0CFG_DEV_RMWAKEUP))
+      {
+          // If we are driving K-state on Device USB port;
+          // We must maintain the 1ms requirement before resuming the phy
+          dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+      }
+  }
+}
+
+#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a00f3489f..d04cb54f0 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -126,6 +126,10 @@
 // GigaDevice
 #define OPT_MCU_GD32VF103        1600 ///< GigaDevice GD32VF103
 
+// BridgeTek
+#define OPT_MCU_FT90X            1700 ///< BridgeTek FT90x
+#define OPT_MCU_FT93X            1701 ///< BridgeTek FT93x
+
 //--------------------------------------------------------------------+
 // Supported OS
 //--------------------------------------------------------------------+

From 98ab8117d68f05bb36b9aeb857273e896199bc6a Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Tue, 5 Oct 2021 18:20:44 -0700
Subject: [PATCH 0542/2085] USB seems to init ok

---
 .gitmodules                   |  4 ++++
 hw/bsp/raspberrypi4/family.c  | 18 ++++++++++++------
 hw/bsp/raspberrypi4/family.mk | 16 +++++++++-------
 hw/mcu/broadcom               |  1 +
 4 files changed, 26 insertions(+), 13 deletions(-)
 create mode 160000 hw/mcu/broadcom

diff --git a/.gitmodules b/.gitmodules
index 4c86fd55c..95f35d270 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -127,3 +127,7 @@
 [submodule "hw/mcu/gd/nuclei-sdk"]
 	path = hw/mcu/gd/nuclei-sdk
 	url = https://github.com/Nuclei-Software/nuclei-sdk.git
+[submodule "hw/mcu/broadcom"]
+	path = hw/mcu/broadcom
+	url = git@github.com:adafruit/broadcom-peripherals.git
+	branch = main-build
diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c
index 6266d5a35..fe7e429d6 100644
--- a/hw/bsp/raspberrypi4/family.c
+++ b/hw/bsp/raspberrypi4/family.c
@@ -27,8 +27,9 @@
 #include "bsp/board.h"
 #include "board.h"
 
-#include "io.h"
-#include "mmu.h"
+#include "broadcom/io.h"
+#include "broadcom/mmu.h"
+#include "broadcom/vcmailbox.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
@@ -46,9 +47,8 @@ void OTG_FS_IRQHandler(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void print(void) {
-  const char* greeting2 = "hello from cm100\r\n";
-  board_uart_write(greeting2, strlen(greeting2));
+void print(const char* str) {
+  board_uart_write(str, strlen(str));
 }
 
 void board_init(void)
@@ -83,7 +83,7 @@ void board_init(void)
   board_uart_write(greeting, strlen(greeting));
   // gpio_setPinOutputBool(24, false);
   // gpio_setPinOutputBool(25, true);
-  print();
+  // print();
   // gpio_setPinOutputBool(25, false);
   // while (true) {
   // // for (size_t i = 0; i < 5; i++) {
@@ -97,6 +97,12 @@ void board_init(void)
   //   gpio_setPinOutputBool(42, false);
   // }
   // while (1) uart_update();
+
+  // Turn on USB peripheral.
+  print("Turning on USB power\r\n");
+
+  vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true);
+  print("USB power on\r\n");
 }
 
 void board_led_write(bool state)
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
index 1547beee1..b36a83b48 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -2,7 +2,7 @@ UF2_FAMILY_ID = 0x57755a57
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
-MCU_DIR = hw/mcu/broadcom/bcm2711
+MCU_DIR = hw/mcu/broadcom
 
 CC = clang
 
@@ -18,21 +18,23 @@ CFLAGS += \
 
 SRC_C += \
 	src/portable/broadcom/synopsys/dcd_synopsys.c \
-	$(MCU_DIR)/interrupts.c \
-	$(MCU_DIR)/io.c \
-	$(MCU_DIR)/mmu.c
+	$(MCU_DIR)/broadcom/interrupts.c \
+	$(MCU_DIR)/broadcom/io.c \
+	$(MCU_DIR)/broadcom/mmu.c \
+	$(MCU_DIR)/broadcom/vcmailbox.c
 
 CROSS_COMPILE = aarch64-none-elf-
 
 SKIP_NANOLIB = 1
 
-LD_FILE = $(MCU_DIR)/link.ld
+LD_FILE = $(MCU_DIR)/broadcom/link.ld
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include
 
-SRC_S += $(MCU_DIR)/boot.S
+SRC_S += $(MCU_DIR)/broadcom/boot.S
 
 $(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf
 	$(OBJCOPY) -O binary $^ $@
diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom
new file mode 160000
index 000000000..c24e8f689
--- /dev/null
+++ b/hw/mcu/broadcom
@@ -0,0 +1 @@
+Subproject commit c24e8f6898d7cf8e2884eb70dbabd97480526450

From bcecbfdc29f58ac019a36099a8c398650cd27191 Mon Sep 17 00:00:00 2001
From: Gordon McNab <Gordon.McNab@ftdichip.com>
Date: Wed, 6 Oct 2021 09:15:33 +0100
Subject: [PATCH 0543/2085] Modify cdc_msc example for Bridgetek FT90x/FT93x

Add in endpoint definitions for the Bridgetek devices in usb_descriptors.c and allow high speed in tusb_config.h.
---
 examples/device/cdc_msc/src/tusb_config.h     |  3 ++-
 examples/device/cdc_msc/src/usb_descriptors.c | 10 ++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index bf6af06bc..2bf5248bf 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -48,7 +48,8 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X || \
+       CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X )
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 1a89ce561..565a5d60c 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -116,6 +116,16 @@ enum
   #define EPNUM_MSC_OUT     0x05
   #define EPNUM_MSC_IN      0x84
 
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+  // FT9XX don't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x83
+
+  #define EPNUM_MSC_OUT     0x04
+  #define EPNUM_MSC_IN      0x85
+
 #else
   #define EPNUM_CDC_NOTIF   0x81
   #define EPNUM_CDC_OUT     0x02

From 37c5eeb51de532dfbd46ae528d4d99220932d6bd Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@ftdichip.com>
Date: Wed, 6 Oct 2021 16:50:55 +0100
Subject: [PATCH 0544/2085] Rename directories to indicate that FT930 and FT900
 devices are both covered by the same SDK and src/portable code. Board
 makefile includes __FT900__ macro for FT90x and __FT930__ macro for boards
 with FT93x.

---
 hw/bsp/brtmm90x/family.c                           |  6 +++---
 hw/bsp/brtmm90x/family.mk                          | 14 +++++++-------
 hw/mcu/bridgetek/{ft90x => ft9xx}/Readme.md        |  7 ++++---
 .../{ft90x => ft9xx}/hardware/scripts/crt0.S       |  0
 .../{ft90x => ft9xx}/hardware/scripts/ldscript.ld  |  0
 .../{ft90x/dcd_ft90x.c => ft9xx/dcd_ft9xx.c}       |  2 --
 6 files changed, 14 insertions(+), 15 deletions(-)
 rename hw/mcu/bridgetek/{ft90x => ft9xx}/Readme.md (52%)
 rename hw/mcu/bridgetek/{ft90x => ft9xx}/hardware/scripts/crt0.S (100%)
 rename hw/mcu/bridgetek/{ft90x => ft9xx}/hardware/scripts/ldscript.ld (100%)
 rename src/portable/bridgetek/{ft90x/dcd_ft90x.c => ft9xx/dcd_ft9xx.c} (99%)

diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 010704d92..6352f2324 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -28,7 +28,6 @@
 #include <ft900.h>
 #include "bsp/board.h"
 #include "board.h"
-//#include "src/device/dcd.h"
 
 #if TUSB_OPT_DEVICE_ENABLED
 int8_t board_ft90x_vbus(void); // Board specific implementation of VBUS detection for USB device.
@@ -67,16 +66,17 @@ void board_init(void)
 #if 1
     gpio_function(GPIO_ETH_LED0, pad_gpio4); /* ETH LED0 */
     gpio_dir(GPIO_ETH_LED0, pad_dir_open_drain);
-    gpio_function(GPIO_ETH_LED1, pad_gpio5); /* ETH LED0 */
+    gpio_function(GPIO_ETH_LED1, pad_gpio5); /* ETH LED1 */
     gpio_dir(GPIO_ETH_LED1, pad_dir_output);
 #endif
+
 	sys_enable(sys_device_timer_wdt);
-	interrupt_attach(interrupt_timers, (int8_t)interrupt_timers, timer_ISR);
 	/* Timer A = 1ms */
 	timer_prescaler(timer_select_a, 1000);
 	timer_init(timer_select_a, 100, timer_direction_down, timer_prescaler_select_on, timer_mode_continuous);
 	timer_enable_interrupt(timer_select_a);
 	timer_start(timer_select_a);
+	interrupt_attach(interrupt_timers, (int8_t)interrupt_timers, timer_ISR);
 
     // Setup VBUS detect GPIO. If the device is connected then this
     // will set the MASK_SYS_PMCFG_DEV_DETECT_EN bit in PMCFG.
diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index 57a141506..42769c254 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -1,10 +1,10 @@
 
 CROSS_COMPILE = ft32-elf-
-DEPS_SUBMODULES += hw/mcu/bridgetek/ft90x/hardware
+DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/hardware
 SKIP_NANOLIB = 1
 
 # This is installed at "C:/Program Files(x86)/Bridgetek/FT9xx Toolchain/Toolchain/hardware"
-FT90X_SDK = $(TOP)/hw/mcu/bridgetek/ft90x/hardware
+FT9XX_SDK = $(TOP)/hw/mcu/bridgetek/ft9xx/hardware
 
 CFLAGS += \
 	-D__FT900__ \
@@ -19,17 +19,17 @@ CFLAGS += -Wno-error=shadow
 CFLAGS:=$(filter-out -Wcast-function-type,$(CFLAGS))
 
 # All source paths should be relative to the top level.
-LDINC += $(FT90X_SDK)/lib/Release
+LDINC += $(FT9XX_SDK)/lib/Release
 LIBS += -lft900
-LD_FILE = hw/mcu/bridgetek/ft90x/hardware/scripts/ldscript.ld
+LD_FILE = hw/mcu/bridgetek/ft9xx/hardware/scripts/ldscript.ld
 LDFLAGS += $(addprefix -L,$(LDINC)) \
 	-Xlinker --entry=_start \
 	-Wl,-lc
 
-SRC_C += src/portable/bridgetek/ft90x/dcd_ft90x.c 
+SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c 
 
-#SRC_S += hw/mcu/bridgetek/ft90x/hardware/scripts/crt0.S
+#SRC_S += hw/mcu/bridgetek/ft9xx/hardware/scripts/crt0.S
 
 INC += \
-	$(FT90X_SDK)/include \
+	$(FT9XX_SDK)/include \
 	$(TOP)/$(BOARD_PATH)
diff --git a/hw/mcu/bridgetek/ft90x/Readme.md b/hw/mcu/bridgetek/ft9xx/Readme.md
similarity index 52%
rename from hw/mcu/bridgetek/ft90x/Readme.md
rename to hw/mcu/bridgetek/ft9xx/Readme.md
index e197f182e..1db91058c 100644
--- a/hw/mcu/bridgetek/ft90x/Readme.md
+++ b/hw/mcu/bridgetek/ft9xx/Readme.md
@@ -1,6 +1,7 @@
 # BridgeTek FT9xx MCU
 
 **BridgeTek** provides a hardware abstraction library with software source code for the SDKs for FT9xx software family.
-The pre-built libraries and the source code can be redistributed.
-Registers definition files `<sdk>/include/registers/ft900_registers.h` and included peripheral register definition files have licenses that allow for redistribution.  
-Whole SDK repository is installed as part of the FT9xx Toolchain and can be downloaded from BridgeTek web page `https://www.brtchip.com`
+
+Whole SDK repository is installed as part of the FT9xx Toolchain and can be downloaded from BridgeTek web page `https://www.brtchip.com`. 
+
+Registers definition files, and included peripheral register definition files have licenses that allow for redistribution.  
diff --git a/hw/mcu/bridgetek/ft90x/hardware/scripts/crt0.S b/hw/mcu/bridgetek/ft9xx/hardware/scripts/crt0.S
similarity index 100%
rename from hw/mcu/bridgetek/ft90x/hardware/scripts/crt0.S
rename to hw/mcu/bridgetek/ft9xx/hardware/scripts/crt0.S
diff --git a/hw/mcu/bridgetek/ft90x/hardware/scripts/ldscript.ld b/hw/mcu/bridgetek/ft9xx/hardware/scripts/ldscript.ld
similarity index 100%
rename from hw/mcu/bridgetek/ft90x/hardware/scripts/ldscript.ld
rename to hw/mcu/bridgetek/ft9xx/hardware/scripts/ldscript.ld
diff --git a/src/portable/bridgetek/ft90x/dcd_ft90x.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
similarity index 99%
rename from src/portable/bridgetek/ft90x/dcd_ft90x.c
rename to src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index ac13f11d1..69b51fac7 100644
--- a/src/portable/bridgetek/ft90x/dcd_ft90x.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -524,8 +524,6 @@ void dcd_init(uint8_t rhport)
 
   _dcd_ft90x_attach();
 
-  //_ft90x_reset_edpts(void);//tu_memclr(ep_xfer, sizeof(ep_xfer));
-
   interrupt_attach(interrupt_usb_device, (int8_t)interrupt_usb_device, _ft90x_usbd_ISR);
 
   dcd_connect(rhport);

From 9966b8a5d6d755c6b92140d617122acb39948f20 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@ftdichip.com>
Date: Wed, 6 Oct 2021 16:54:52 +0100
Subject: [PATCH 0545/2085] Change author in header to Bridgetek Pte Ltd.

---
 hw/bsp/brtmm90x/boards/mm900ev1b/board.h | 2 +-
 hw/bsp/brtmm90x/family.c                 | 2 +-
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/brtmm90x/boards/mm900ev1b/board.h b/hw/bsp/brtmm90x/boards/mm900ev1b/board.h
index dfb566289..67f61237f 100644
--- a/hw/bsp/brtmm90x/boards/mm900ev1b/board.h
+++ b/hw/bsp/brtmm90x/boards/mm900ev1b/board.h
@@ -1,7 +1,7 @@
 /*
  * The MIT License (MIT)
  *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ * Copyright 2021 Bridgetek Pte Ltd
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 6352f2324..3bd16b817 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -1,7 +1,7 @@
 /* 
  * The MIT License (MIT)
  *
- * Copyright 2019 Sony Semiconductor Solutions Corporation
+ * Copyright 2021 Bridgetek Pte Ltd
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 69b51fac7..6dbef1614 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -1,7 +1,7 @@
 /* 
  * The MIT License (MIT)
  *
- * Copyright (c) 2018, hathach (tinyusb.org)
+ * Copyright 2021 Bridgetek Pte Ltd
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal

From 8c40a74f295d93a62a0e7c8a873b6d7abcce19b1 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@ftdichip.com>
Date: Wed, 6 Oct 2021 17:13:44 +0100
Subject: [PATCH 0546/2085] Sort out board settings.

---
 .../boards/{mm900ev1b => mm900evxb}/board.h        | 14 ++++----------
 hw/bsp/brtmm90x/family.c                           |  6 +++---
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c           |  3 ++-
 3 files changed, 9 insertions(+), 14 deletions(-)
 rename hw/bsp/brtmm90x/boards/{mm900ev1b => mm900evxb}/board.h (85%)

diff --git a/hw/bsp/brtmm90x/boards/mm900ev1b/board.h b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
similarity index 85%
rename from hw/bsp/brtmm90x/boards/mm900ev1b/board.h
rename to hw/bsp/brtmm90x/boards/mm900evxb/board.h
index 67f61237f..57936fda5 100644
--- a/hw/bsp/brtmm90x/boards/mm900ev1b/board.h
+++ b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
@@ -27,27 +27,21 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
+// Note: This definition file covers all MM900EV1B, MM900EV2B, and MM900EV3B boards.
+// Each of these boards has an FT900 device.
+
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-#if defined(__FT900__)
 #define GPIO_UART0_TX 48
 #define GPIO_UART0_RX 49
 #define GPIO_ETH_LED0 61
 #define GPIO_ETH_LED1 62
 #define GPIO_REMOTE_WAKEUP_PIN 18
 #define USBD_VBUS_DTC_PIN 3
-#elif defined(__FT930__)
-#define GPIO_UART0_TX 23
-#define GPIO_UART0_RX 22
-#define GPIO_ETH_LED0 4
-#define GPIO_ETH_LED1 5
-#define GPIO_REMOTE_WAKEUP_PIN 12
-#define USBD_VBUS_DTC_PIN 39
-#endif
 
-//#define GPIO_REMOTE_WAKEUP
+#define GPIO_REMOTE_WAKEUP
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 3bd16b817..ed169655e 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -24,10 +24,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+#include "board.h"
+#include "bsp/board.h"
 #include <registers/ft900_registers.h>
 #include <ft900.h>
-#include "bsp/board.h"
-#include "board.h"
 
 #if TUSB_OPT_DEVICE_ENABLED
 int8_t board_ft90x_vbus(void); // Board specific implementation of VBUS detection for USB device.
@@ -42,7 +42,7 @@ volatile unsigned int timer_ms = 0;
 void board_pm_ISR(void);
 
 #define WELCOME_MSG "\x1B[2J\x1B[H" \
-                    "MM900EV1B board\r\n"
+                    "MM900EVxB board\r\n"
 
 // Initialize on-board peripherals : led, button, uart and USB
 void board_init(void)
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 6dbef1614..9b08702ed 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -24,8 +24,9 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "tusb_option.h"
+#include "board.h"
 #include "bsp/board.h"
+#include "tusb_option.h"
 
 #if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_FT90X
 

From 5e6edecaa3594980198d8f687b3d97979ae85092 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@ftdichip.com>
Date: Thu, 7 Oct 2021 17:00:28 +0100
Subject: [PATCH 0547/2085] Streamline settings for board.

---
 hw/bsp/brtmm90x/family.mk                |  2 +-
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 54 +++++++++++++-----------
 2 files changed, 31 insertions(+), 25 deletions(-)

diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index 42769c254..211f97f1b 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -12,7 +12,7 @@ CFLAGS += \
 	-fvar-tracking-assignments \
 	-fmessage-length=0 \
 	-ffunction-sections \
-	-DCFG_TUSB_MCU=OPT_MCU_FT90X 
+	-DCFG_TUSB_MCU=OPT_MCU_FT90X
 
 # lwip/src/core/raw.c:334:43: error: declaration of 'recv' shadows a global declaration
 CFLAGS += -Wno-error=shadow
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 9b08702ed..09ca2904f 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -24,11 +24,17 @@
  * This file is part of the TinyUSB stack.
  */
 
+/* 
+ * Contains code adapted from Bridgetek Pte Ltd via license terms stated 
+ * in https://brtchip.com/BRTSourceCodeLicenseAgreement
+ */
+
 #include "board.h"
 #include "bsp/board.h"
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_FT90X
+#if TUSB_OPT_DEVICE_ENABLED && \
+  (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X)
 
 #define USBD_USE_STREAMS
 
@@ -250,12 +256,12 @@ static void _dcd_ft90x_attach(void)
 
   CRITICAL_SECTION_BEGIN
   // Turn off the device enable bit.
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED
+#if BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_HIGH_SPEED
   USBD_REG(fctrl) = 0;
-#else
+#else // BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_FULL_SPEED
   //Set the full speed only bit if required.
   USBD_REG(fctrl) = MASK_USBD_FCTRL_MODE_FS_ONLY;
-#endif
+#endif // BOARD_DEVICE_RHPORT_SPEED
 
   // Clear first reset and suspend interrupts.
   do
@@ -301,7 +307,7 @@ static void _dcd_ft90x_detach(void)
   delayms(1);
 
   // Disable USB PHY
-  dcd_disconnect(0);
+  dcd_disconnect(BOARD_DEVICE_RHPORT_NUM);
   delayms(1);
 
   // Disable Chip USB device clock/PM configuration.
@@ -333,7 +339,7 @@ static void _ft90x_usb_speed(void)
 		delayus(200);
 	}
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED
+#if BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_HIGH_SPEED
 
 	/* Detect high or full speed */
 	fctrl_val = MASK_USBD_FCTRL_USB_DEV_EN;
@@ -357,11 +363,11 @@ static void _ft90x_usb_speed(void)
 	delayus(125 + 5);
 	_speed = (USBD_REG(cmif) & MASK_USBD_CMIF_SOFIRQ) ?
 		TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
-  dcd_event_bus_reset(0, _speed, true);
+  dcd_event_bus_reset(BOARD_DEVICE_RHPORT_NUM, _speed, true);
 
 #endif /* !__FT930__ */
 
-#else /* CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED */
+#else // BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_FULL_SPEED
 
 	/* User force set to full speed */
   _speed = TUSB_SPEED_FULL;
@@ -374,10 +380,10 @@ static void _ft90x_usb_speed(void)
 	}
 #endif
 	USBD_REG(fctrl) = fctrl_val;
-  dcd_event_bus_reset(0, _speed, true);
+  dcd_event_bus_reset(BOARD_DEVICE_RHPORT_NUM, _speed, true);
 	return;
 
-#endif /* CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED */
+#endif // BOARD_DEVICE_RHPORT_SPEED
 }
 
 // Send a buffer to the USB IN FIFO.
@@ -557,7 +563,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   (void)dev_addr;
 
   // Respond with status. There is no checking that the address is in range.
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  dcd_edpt_xfer(rhport, tu_edpt_addr(USBD_EP_0, TUSB_DIR_IN), NULL, 0);
 
   // Set the update bit for the address register.
   dev_addr |= 0x80;
@@ -603,7 +609,7 @@ void dcd_remote_wakeup(uint8_t rhport)
   SYS->MSC0CFG &= ~MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
 
   // Enable USB PHY and determine current bus speed.
-  dcd_connect(0);
+  dcd_connect(rhport);
 }
 
 // Connect by enabling internal pull-up resistor on D+/D-
@@ -882,7 +888,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
 void _ft90x_usbd_ISR(void)
 {
-  tud_int_handler(0); // Resolves to dcd_int_handler().
+  tud_int_handler(BOARD_DEVICE_RHPORT_NUM); // Resolves to dcd_int_handler().
 }
 
 void dcd_int_handler(uint8_t rhport)
@@ -920,19 +926,19 @@ void dcd_int_handler(uint8_t rhport)
     {
       // Reset endpoints to default state.
       _ft90x_reset_edpts();
-      dcd_event_bus_reset(0, _speed, true);
+      dcd_event_bus_reset(BOARD_DEVICE_RHPORT_NUM, _speed, true);
     }
     if (cmif & MASK_USBD_CMIF_SUSIRQ) //Handle Suspend interrupt
     {
-      dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_SUSPEND, true);
     }
     if (cmif & MASK_USBD_CMIF_RESIRQ) //Handle Resume interrupt
     {
-      dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_RESUME, true);
     }
     if (cmif & MASK_USBD_CMIF_SOFIRQ) //Handle SOF interrupt
     {
-      dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_SOF, true);
     }
   }
   // Handle endpoint interrupts.
@@ -963,7 +969,7 @@ void dcd_int_handler(uint8_t rhport)
         _ft90x_dusb_out(USBD_EP_0, (uint8_t *)_ft90x_setup_packet, sizeof(USB_device_request));
         
         // Send the packet to tinyusb.
-        dcd_event_setup_received(0, _ft90x_setup_packet, true);
+        dcd_event_setup_received(BOARD_DEVICE_RHPORT_NUM, _ft90x_setup_packet, true);
 
         // Clear the interrupt that signals a SETUP packet is received.
         USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_SETUP);
@@ -985,7 +991,7 @@ void dcd_int_handler(uint8_t rhport)
             xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, (uint8_t *)ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
           }
           // Now signal completion of data packet.
-          dcd_event_xfer_complete(0, (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true);
+          dcd_event_xfer_complete(BOARD_DEVICE_RHPORT_NUM, (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true);
 
           // Allow new transfers on the control endpoint.
           ep_xfer[USBD_EP_0].valid = 0;
@@ -1042,7 +1048,7 @@ void dcd_int_handler(uint8_t rhport)
           if (ep_xfer[ep_number].remain_size == 0)
           {
             // Signal tinyUSB.
-            dcd_event_xfer_complete(0, ep_number | ep_dirmask, ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
+            dcd_event_xfer_complete(BOARD_DEVICE_RHPORT_NUM, ep_number | ep_dirmask, ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
 
             // Allow new transfers on this endpoint.
             ep_xfer[ep_number].valid = 0;
@@ -1067,21 +1073,21 @@ void ft90x_usbd_pm_ISR(void)
   {
       // Signal connection interrupt
       SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
-      dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_RESUME, true);
   }
 
   if (pmcfg & MASK_SYS_PMCFG_DEV_DIS_DEV)
   {
       // Signal disconnection interrupt
       SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
-      dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
+      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_UNPLUGGED, true);
   }
 
   if (pmcfg & MASK_SYS_PMCFG_HOST_RST_DEV)
   {
       // Signal Host Reset interrupt
       SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
-      dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_BUS_RESET, true);
   }
 
   if (pmcfg & MASK_SYS_PMCFG_HOST_RESUME_DEV)
@@ -1092,7 +1098,7 @@ void ft90x_usbd_pm_ISR(void)
       {
           // If we are driving K-state on Device USB port;
           // We must maintain the 1ms requirement before resuming the phy
-          dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+          dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_RESUME, true);
       }
   }
 }

From a8eea9f6a540ef5c6314c400754364e0456002cd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 9 Oct 2021 11:28:55 +0700
Subject: [PATCH 0548/2085] add backward compatible with warnings for
 CFG_TUD_NET

---
 src/tusb_option.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 057bc61c2..cda8c45ce 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -266,7 +266,12 @@
 #endif
 
 #ifndef CFG_TUD_ECM_RNDIS
-  #define CFG_TUD_ECM_RNDIS   0
+  #ifdef CFG_TUD_NET
+    #warning "CFG_TUD_NET is renamed to CFG_TUD_ECM_RNDIS"
+    #define CFG_TUD_ECM_RNDIS   CFG_TUD_NET
+  #else
+    #define CFG_TUD_ECM_RNDIS   0
+  #endif
 #endif
 
 #ifndef CFG_TUD_NCM

From a3a18c9ed33a4d6f2027dc46ab32c62314d1abef Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 9 Oct 2021 19:51:51 +0900
Subject: [PATCH 0549/2085] Change the video image to scrolling color bars.

---
 examples/device/video_capture/src/images.h    | 9339 +++--------------
 examples/device/video_capture/src/main.c      |   74 +-
 .../video_capture/src/usb_descriptors.h       |    8 +-
 hw/bsp/frdm_kl25z/board.mk                    |    3 +-
 4 files changed, 1717 insertions(+), 7707 deletions(-)

diff --git a/examples/device/video_capture/src/images.h b/examples/device/video_capture/src/images.h
index a55353d91..1b13cfe81 100644
--- a/examples/device/video_capture/src/images.h
+++ b/examples/device/video_capture/src/images.h
@@ -1,7690 +1,1651 @@
-static const unsigned char white_128x96_yuv[] = {
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
-};
-static const unsigned char t_128x96_yuv[] = {
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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-  0x7f, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
-};
-static const unsigned char ti_128x96_yuv[] = {
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
-};
-static const unsigned char tin_128x96_yuv[] = {
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x7f,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
-};
-static const unsigned char logo_128x96_yuv[] = {
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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-  0x81, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
-  0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81,
-  0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x80, 0x81, 0x80, 0x80, 0x81, 0x81,
-  0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81,
-  0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x7f, 0x80, 0x81, 0x81,
-  0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
-  0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80,
-  0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81,
-  0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x81, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
-  0x81, 0x81, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
-  0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81,
-  0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x7f, 0x80,
-  0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80,
-  0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81,
-  0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81,
-  0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81,
-  0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
-  0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81,
-  0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80,
-  0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81,
-  0x81, 0x81, 0x81, 0x81, 0x81, 0x80, 0x80, 0x7f, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x81, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81,
-  0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x81,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x7f,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81,
-  0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x81, 0x81, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, 0x81, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-  0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
+static const unsigned char frame_buffer[128 * (96 + 1) * 2] = {
+  /* 0 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 1 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 2 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 3 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 4 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 5 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 6 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 7 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 8 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 9 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 10 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 11 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 12 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 13 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 14 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 15 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 16 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 17 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 18 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 19 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 20 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 21 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 22 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 23 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 24 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 25 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 26 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 27 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 28 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 29 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 30 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 31 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 32 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 33 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 34 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 35 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 36 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 37 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 38 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 39 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 40 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 41 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 42 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 43 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 44 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 45 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 46 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 47 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 48 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 49 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 50 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 51 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 52 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 53 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 54 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 55 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 56 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 57 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 58 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 59 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 60 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 61 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 62 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 63 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 64 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 65 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 66 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 67 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 68 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 69 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 70 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 71 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 72 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 73 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 74 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 75 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 76 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 77 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 78 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 79 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 80 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 81 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 82 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 83 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 84 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 85 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 86 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 87 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 88 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 89 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 90 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 91 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 92 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 93 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 94 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 95 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  /* 96 */
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a, 0xdb, 0x10, 0xdb, 0x8a,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10, 0xbc, 0x9a, 0xbc, 0x10,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a, 0xad, 0x2a, 0xad, 0x1a,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6, 0x4e, 0xd6, 0x4e, 0xe6,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0, 0x3f, 0x66, 0x3f, 0xf0,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76, 0x20, 0xf0, 0x20, 0x76,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
+  0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
 };
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index b76af071a..f0f4df6eb 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -31,7 +31,6 @@
 #include "tusb.h"
 #include "usb_descriptors.h"
 
-#include "images.h"
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
@@ -104,15 +103,54 @@ void tud_resume_cb(void)
 //--------------------------------------------------------------------+
 // USB Video
 //--------------------------------------------------------------------+
-static unsigned char const *frames[] = {
-  white_128x96_yuv, white_128x96_yuv, white_128x96_yuv,
-  t_128x96_yuv, ti_128x96_yuv, tin_128x96_yuv, logo_128x96_yuv,
-  logo_128x96_yuv, logo_128x96_yuv, logo_128x96_yuv, logo_128x96_yuv
-};
-static unsigned current_frame = 0;
+static unsigned frame_num = 0;
 static unsigned tx_busy = 0;
 static unsigned interval_ms = 1000 / FRAME_RATE;
 
+/* YUY2 frame buffer */
+#ifdef CFG_EXAMPLE_VIDEO_READONLY
+#include "images.h"
+#else
+static uint8_t frame_buffer[FRAME_WIDTH * FRAME_HEIGHT * 16 / 8];
+static void fill_color_bar(uint8_t *buffer, unsigned start_position)
+{
+  /* EBU color bars
+   * See also https://stackoverflow.com/questions/6939422 */
+  static uint8_t const bar_color[8][4] = {
+    /*  Y,   U,   Y,   V */
+    { 235, 128, 235, 128}, /* 100% White */
+    { 219,  16, 219, 138}, /* Yellow */
+    { 188, 154, 188,  16}, /* Cyan */
+    { 173,  42, 173,  26}, /* Green */
+    {  78, 214,  78, 230}, /* Magenta */
+    {  63, 102,  63, 240}, /* Red */
+    {  32, 240,  32, 118}, /* Blue */
+    {  16, 128,  16, 128}, /* Black */
+  };
+  uint8_t *p;
+
+  /* Generate the 1st line */
+  uint8_t *end = &buffer[FRAME_WIDTH * 2];
+  unsigned idx = (FRAME_WIDTH / 2 - 1) - (start_position % (FRAME_WIDTH / 2));
+  p = &buffer[idx * 4];
+  for (unsigned i = 0; i < 8; ++i) {
+    for (int j = 0; j < FRAME_WIDTH / (2 * 8); ++j) {
+      memcpy(p, &bar_color[i], 4);
+      p += 4;
+      if (end <= p) {
+        p = buffer;
+      }
+    }
+  }
+  /* Duplicate the 1st line to the others */
+  p = &buffer[FRAME_WIDTH * 2];
+  for (unsigned i = 1; i < FRAME_HEIGHT; ++i) {
+    memcpy(p, buffer, FRAME_WIDTH * 2);
+    p += FRAME_WIDTH * 2;
+  }
+}
+#endif
+
 void video_task(void)
 {
   static unsigned start_ms = 0;
@@ -120,14 +158,20 @@ void video_task(void)
 
   if (!tud_video_n_streaming(0, 0)) {
     already_sent  = 0;
-    current_frame = 0;
+    frame_num     = 0;
     return;
   }
 
   if (!already_sent) {
     already_sent = 1;
     start_ms = board_millis();
-    tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], FRAME_WIDTH * FRAME_HEIGHT * 12/8);
+#ifdef CFG_EXAMPLE_VIDEO_READONLY
+    tud_video_n_frame_xfer(0, 0, (void*)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
+                           FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+#else
+    fill_color_bar(frame_buffer, frame_num);
+    tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+#endif
   }
 
   unsigned cur = board_millis();
@@ -135,7 +179,13 @@ void video_task(void)
   if (tx_busy) return;
   start_ms += interval_ms;
 
-  tud_video_n_frame_xfer(0, 0, (void*)frames[current_frame], FRAME_WIDTH * FRAME_HEIGHT * 12/8);
+#ifdef CFG_EXAMPLE_VIDEO_READONLY
+  tud_video_n_frame_xfer(0, 0, (void*)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
+                         FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+#else
+  fill_color_bar(frame_buffer, frame_num);
+  tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+#endif
 }
 
 void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
@@ -143,9 +193,7 @@ void tud_video_frame_xfer_complete_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx
   (void)ctl_idx; (void)stm_idx;
   tx_busy = 0;
   /* flip buffer */
-  ++current_frame;
-  if (current_frame == sizeof(frames)/sizeof(frames[0]))
-    current_frame = 0;
+  ++frame_num;
 }
 
 int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index e52703b29..403dc56a1 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -61,7 +61,7 @@ enum {
     + 7/* Endpoint */\
   )
 
-/* Windows support YUV2 and NV12
+/* Windows support YUY2 and NV12
  * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
 
 #define TUD_VIDEO_DESC_CS_VS_FMT_YUY2(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
@@ -97,12 +97,12 @@ enum {
           /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
           /*bmaControls(1)*/0), \
         /* Video stream format */ \
-        TUD_VIDEO_DESC_CS_VS_FMT_NV12(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1,\
+        TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
           /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
           /* Video stream frame format */ \
           TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
-              _width * _height * 12, _width * _height * 12 * _fps, \
-              _width * _height * 12, \
+              _width * _height * 16, _width * _height * 16 * _fps, \
+              _width * _height * 16, \
               (10000000/_fps), (10000000/_fps), 10000000, 100000), \
           TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
     /* VS alt 1 */\
diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
index bc9240e55..15bd50eda 100644
--- a/hw/bsp/frdm_kl25z/board.mk
+++ b/hw/bsp/frdm_kl25z/board.mk
@@ -6,7 +6,8 @@ CFLAGS += \
   -mabi=aapcs \
   -mcpu=cortex-m0plus \
   -DCPU_MKL25Z128VLK4 \
-  -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX
+  -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX \
+  -DCFG_EXAMPLE_VIDEO_READONLY
 
 LDFLAGS += \
   -Wl,--defsym,__stack_size__=0x400 \

From b6d09ca7619b2f624cc3ee92a795ba2a9b9d68e9 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 9 Oct 2021 23:02:18 +0900
Subject: [PATCH 0550/2085] Add compile option to allocate video data into
 flash in video_capture example

---
 examples/device/video_capture/.skip.MCU_STM32F1         | 0
 hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk             | 2 +-
 hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk             | 2 +-
 hw/bsp/lpc15/boards/lpcxpresso1549/board.mk             | 1 +
 hw/bsp/lpcxpresso11u37/board.mk                         | 1 +
 hw/bsp/lpcxpresso1347/board.mk                          | 1 +
 hw/bsp/nutiny_nuc126v/board.mk                          | 1 +
 hw/bsp/nutiny_sdk_nuc120/board.mk                       | 1 +
 hw/bsp/samd21/boards/atsamd21_xpro/board.mk             | 2 +-
 hw/bsp/samd21/boards/circuitplayground_express/board.mk | 2 +-
 hw/bsp/samd21/boards/curiosity_nano/board.mk            | 2 +-
 hw/bsp/samd21/boards/feather_m0_express/board.mk        | 2 +-
 hw/bsp/samd21/boards/itsybitsy_m0/board.mk              | 2 +-
 hw/bsp/samd21/boards/luna_d21/board.mk                  | 2 +-
 hw/bsp/samd21/boards/metro_m0_express/board.mk          | 2 +-
 hw/bsp/samd21/boards/seeeduino_xiao/board.mk            | 2 +-
 hw/bsp/saml2x/boards/atsaml21_xpro/board.mk             | 2 +-
 hw/bsp/saml2x/boards/saml22_feather/board.mk            | 2 +-
 hw/bsp/saml2x/boards/sensorwatch_m0/board.mk            | 2 +-
 hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk        | 2 +-
 hw/bsp/stm32f0/boards/stm32f072disco/board.mk           | 2 +-
 hw/bsp/stm32f0/boards/stm32f072eval/board.mk            | 2 +-
 hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk       | 2 +-
 hw/bsp/stm32l0538disco/board.mk                         | 1 +
 24 files changed, 23 insertions(+), 17 deletions(-)
 delete mode 100644 examples/device/video_capture/.skip.MCU_STM32F1

diff --git a/examples/device/video_capture/.skip.MCU_STM32F1 b/examples/device/video_capture/.skip.MCU_STM32F1
deleted file mode 100644
index e69de29bb..000000000
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
index 507db7f00..17dc01cd9 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DCPU_MIMXRT1011DAE5A
+CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
 MCU_VARIANT = MIMXRT1011
 
 # For flash-jlink target
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk
index 17fd25dfe..20c697ea1 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DCPU_MIMXRT1015DAF5A
+CFLAGS += -DCPU_MIMXRT1015DAF5A -DCFG_EXAMPLE_VIDEO_READONLY
 MCU_VARIANT = MIMXRT1015
 
 # For flash-jlink target
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk b/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk
index a3e04cfa1..b00fc71b0 100644
--- a/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/board.mk
@@ -1,3 +1,4 @@
+CFLAGS += -DCFG_EXAMPLE_VIDEO_READONLY
 LD_FILE = $(BOARD_PATH)/lpc1549.ld
 
 JLINK_DEVICE = LPC1549
diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk
index 8fcda51ee..b736eebe1 100644
--- a/hw/bsp/lpcxpresso11u37/board.mk
+++ b/hw/bsp/lpcxpresso11u37/board.mk
@@ -9,6 +9,7 @@ CFLAGS += \
   -DCORE_M0 \
   -D__USE_LPCOPEN \
   -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk
index 0d56a33a6..62135c274 100644
--- a/hw/bsp/lpcxpresso1347/board.mk
+++ b/hw/bsp/lpcxpresso1347/board.mk
@@ -9,6 +9,7 @@ CFLAGS += \
   -DCORE_M3 \
   -D__USE_LPCOPEN \
   -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index 848b19f95..e9df1ed13 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -7,6 +7,7 @@ CFLAGS += \
   -mcpu=cortex-m0 \
   -D__ARM_FEATURE_DSP=0 \
   -DUSE_ASSERT=0 \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -D__CORTEX_SC=0 \
   -DCFG_TUSB_MCU=OPT_MCU_NUC126
 
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index 90b3e91fb..1fde47c5a 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -6,6 +6,7 @@ CFLAGS += \
   -mabi=aapcs-linux \
   -mcpu=cortex-m0 \
   -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_NUC120
 
 # All source paths should be relative to the top level.
diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.mk b/hw/bsp/samd21/boards/atsamd21_xpro/board.mk
index 5cd82735c..4be547a1b 100644
--- a/hw/bsp/samd21/boards/atsamd21_xpro/board.mk
+++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21J18A__
+CFLAGS += -D__SAMD21J18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/samd21j18a_flash.ld
diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.mk b/hw/bsp/samd21/boards/circuitplayground_express/board.mk
index bb426cdaa..d6c9150b3 100644
--- a/hw/bsp/samd21/boards/circuitplayground_express/board.mk
+++ b/hw/bsp/samd21/boards/circuitplayground_express/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.mk b/hw/bsp/samd21/boards/curiosity_nano/board.mk
index ec3217f89..112fb6946 100644
--- a/hw/bsp/samd21/boards/curiosity_nano/board.mk
+++ b/hw/bsp/samd21/boards/curiosity_nano/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G17A__ -DCFG_EXAMPLE_MSC_READONLY
+CFLAGS += -D__SAMD21G17A__ -DCFG_EXAMPLE_MSC_READONLY -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/samd21g17a_flash.ld
diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.mk b/hw/bsp/samd21/boards/feather_m0_express/board.mk
index bb426cdaa..d6c9150b3 100644
--- a/hw/bsp/samd21/boards/feather_m0_express/board.mk
+++ b/hw/bsp/samd21/boards/feather_m0_express/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.mk b/hw/bsp/samd21/boards/itsybitsy_m0/board.mk
index bb426cdaa..d6c9150b3 100644
--- a/hw/bsp/samd21/boards/itsybitsy_m0/board.mk
+++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd21/boards/luna_d21/board.mk b/hw/bsp/samd21/boards/luna_d21/board.mk
index 5beb5e02d..27a634e3a 100644
--- a/hw/bsp/samd21/boards/luna_d21/board.mk
+++ b/hw/bsp/samd21/boards/luna_d21/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/samd21g18a_flash.ld
 
diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.mk b/hw/bsp/samd21/boards/metro_m0_express/board.mk
index bb426cdaa..d6c9150b3 100644
--- a/hw/bsp/samd21/boards/metro_m0_express/board.mk
+++ b/hw/bsp/samd21/boards/metro_m0_express/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.mk b/hw/bsp/samd21/boards/seeeduino_xiao/board.mk
index 54591b3a5..1c888da3a 100644
--- a/hw/bsp/samd21/boards/seeeduino_xiao/board.mk
+++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAMD21G18A__
+CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
 
diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk b/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
index 81b4ecdcb..5b9acb90b 100644
--- a/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
+++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAML21J18B__
+CFLAGS += -D__SAML21J18B__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 SAML_VARIANT = saml21
 
diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.mk b/hw/bsp/saml2x/boards/saml22_feather/board.mk
index 0605dca19..0adfdd62c 100644
--- a/hw/bsp/saml2x/boards/saml22_feather/board.mk
+++ b/hw/bsp/saml2x/boards/saml22_feather/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAML22J18A__
+CFLAGS += -D__SAML22J18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 SAML_VARIANT = saml22
 
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
index 0605dca19..0adfdd62c 100644
--- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -D__SAML22J18A__
+CFLAGS += -D__SAML22J18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 SAML_VARIANT = saml22
 
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
index 9e636cd76..7c0ee40b6 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DSTM32F070xB
+CFLAGS += -DSTM32F070xB -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld
 
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
index 2ef0ee63c..7c72d8f4c 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DSTM32F072xB
+CFLAGS += -DSTM32F072xB -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
 
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
index f7f8c84ee..b625c3ebd 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000
+CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
 
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
index 9c690ca7e..db64b3a3f 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
@@ -1,4 +1,4 @@
-CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
+CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld
diff --git a/hw/bsp/stm32l0538disco/board.mk b/hw/bsp/stm32l0538disco/board.mk
index c46887f14..e19101d64 100644
--- a/hw/bsp/stm32l0538disco/board.mk
+++ b/hw/bsp/stm32l0538disco/board.mk
@@ -13,6 +13,7 @@ CFLAGS += \
   -nostdlib -nostartfiles \
   -DSTM32L053xx \
   -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L0
 
 # mcu driver cause following warnings

From a6723f556d7b302137ca42c7f811d3484f25414a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 11 Oct 2021 12:36:03 +0700
Subject: [PATCH 0551/2085] add ncm.h for magic number

mostly clean up magic number
---
 src/class/cdc/cdc.h        | 69 ++++++++++++++++++--------------------
 src/class/net/ncm.h        | 69 ++++++++++++++++++++++++++++++++++++++
 src/class/net/ncm_device.c | 56 ++++++++++++++++++-------------
 src/class/net/net_device.h |  2 ++
 src/device/usbd.h          |  8 ++---
 5 files changed, 141 insertions(+), 63 deletions(-)
 create mode 100644 src/class/net/ncm.h

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index 52de859ca..e345139ea 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -58,32 +58,32 @@ typedef enum
 /// Communication Interface Subclass Codes
 typedef enum
 {
-  CDC_COMM_SUBCLASS_DIRECT_LINE_CONTROL_MODEL = 0x01  , ///< Direct Line Control Model  [USBPSTN1.2]
-  CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL            , ///< Abstract Control Model  [USBPSTN1.2]
-  CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL           , ///< Telephone Control Model  [USBPSTN1.2]
-  CDC_COMM_SUBCLASS_MULTICHANNEL_CONTROL_MODEL        , ///< Multi-Channel Control Model  [USBISDN1.2]
-  CDC_COMM_SUBCLASS_CAPI_CONTROL_MODEL                , ///< CAPI Control Model  [USBISDN1.2]
-  CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL            , ///< Ethernet Networking Control Model  [USBECM1.2]
-  CDC_COMM_SUBCLASS_ATM_NETWORKING_CONTROL_MODEL      , ///< ATM Networking Control Model  [USBATM1.2]
-  CDC_COMM_SUBCLASS_WIRELESS_HANDSET_CONTROL_MODEL    , ///< Wireless Handset Control Model  [USBWMC1.1]
-  CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT                 , ///< Device Management  [USBWMC1.1]
-  CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL          , ///< Mobile Direct Line Model  [USBWMC1.1]
-  CDC_COMM_SUBCLASS_OBEX                              , ///< OBEX  [USBWMC1.1]
-  CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL          , ///< Ethernet Emulation Model  [USBEEM1.0]
-  CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL               ///< Network Control Model  [USBNCM1.0]
+  CDC_COMM_SUBCLASS_DIRECT_LINE_CONTROL_MODEL      = 0x01 , ///< Direct Line Control Model         [USBPSTN1.2]
+  CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL         = 0x02 , ///< Abstract Control Model            [USBPSTN1.2]
+  CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL        = 0x03 , ///< Telephone Control Model           [USBPSTN1.2]
+  CDC_COMM_SUBCLASS_MULTICHANNEL_CONTROL_MODEL     = 0x04 , ///< Multi-Channel Control Model       [USBISDN1.2]
+  CDC_COMM_SUBCLASS_CAPI_CONTROL_MODEL             = 0x05 , ///< CAPI Control Model                [USBISDN1.2]
+  CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL         = 0x06 , ///< Ethernet Networking Control Model [USBECM1.2]
+  CDC_COMM_SUBCLASS_ATM_NETWORKING_CONTROL_MODEL   = 0x07 , ///< ATM Networking Control Model      [USBATM1.2]
+  CDC_COMM_SUBCLASS_WIRELESS_HANDSET_CONTROL_MODEL = 0x08 , ///< Wireless Handset Control Model    [USBWMC1.1]
+  CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT              = 0x09 , ///< Device Management                 [USBWMC1.1]
+  CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL       = 0x0A , ///< Mobile Direct Line Model          [USBWMC1.1]
+  CDC_COMM_SUBCLASS_OBEX                           = 0x0B , ///< OBEX                              [USBWMC1.1]
+  CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL       = 0x0C , ///< Ethernet Emulation Model          [USBEEM1.0]
+  CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL          = 0x0D   ///< Network Control Model             [USBNCM1.0]
 } cdc_comm_sublcass_type_t;
 
 /// Communication Interface Protocol Codes
 typedef enum
 {
-  CDC_COMM_PROTOCOL_NONE                   = 0x00 , ///< No specific protocol
-  CDC_COMM_PROTOCOL_ATCOMMAND                     , ///< AT Commands: V.250 etc
-  CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101            , ///< AT Commands defined by PCCA-101
-  CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101_AND_ANNEXO , ///< AT Commands defined by PCCA-101 & Annex O
-  CDC_COMM_PROTOCOL_ATCOMMAND_GSM_707             , ///< AT Commands defined by GSM 07.07
-  CDC_COMM_PROTOCOL_ATCOMMAND_3GPP_27007          , ///< AT Commands defined by 3GPP 27.007
-  CDC_COMM_PROTOCOL_ATCOMMAND_CDMA                , ///< AT Commands defined by TIA for CDMA
-  CDC_COMM_PROTOCOL_ETHERNET_EMULATION_MODEL        ///< Ethernet Emulation Model
+  CDC_COMM_PROTOCOL_NONE                          = 0x00 , ///< No specific protocol
+  CDC_COMM_PROTOCOL_ATCOMMAND                     = 0x01 , ///< AT Commands: V.250 etc
+  CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101            = 0x02 , ///< AT Commands defined by PCCA-101
+  CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101_AND_ANNEXO = 0x03 , ///< AT Commands defined by PCCA-101 & Annex O
+  CDC_COMM_PROTOCOL_ATCOMMAND_GSM_707             = 0x04 , ///< AT Commands defined by GSM 07.07
+  CDC_COMM_PROTOCOL_ATCOMMAND_3GPP_27007          = 0x05 , ///< AT Commands defined by 3GPP 27.007
+  CDC_COMM_PROTOCOL_ATCOMMAND_CDMA                = 0x06 , ///< AT Commands defined by TIA for CDMA
+  CDC_COMM_PROTOCOL_ETHERNET_EMULATION_MODEL      = 0x07   ///< Ethernet Emulation Model
 } cdc_comm_protocol_type_t;
 
 //------------- SubType Descriptor in COMM Functional Descriptor -------------//
@@ -124,7 +124,8 @@ typedef enum
 //--------------------------------------------------------------------+
 
 // SUBCLASS code of Data Interface is not used and should/must be zero
-/// Data Interface Protocol Codes
+
+// Data Interface Protocol Codes
 typedef enum{
   CDC_DATA_PROTOCOL_ISDN_BRI                               = 0x30, ///< Physical interface protocol for ISDN BRI
   CDC_DATA_PROTOCOL_HDLC                                   = 0x31, ///< HDLC
@@ -149,7 +150,6 @@ typedef enum
 {
   CDC_REQUEST_SEND_ENCAPSULATED_COMMAND                    = 0x00, ///< is used to issue a command in the format of the supported control protocol of the Communications Class interface
   CDC_REQUEST_GET_ENCAPSULATED_RESPONSE                    = 0x01, ///< is used to request a response in the format of the supported control protocol of the Communications Class interface.
-
   CDC_REQUEST_SET_COMM_FEATURE                             = 0x02,
   CDC_REQUEST_GET_COMM_FEATURE                             = 0x03,
   CDC_REQUEST_CLEAR_COMM_FEATURE                           = 0x04,
@@ -196,21 +196,18 @@ typedef enum
 // Management Elemenent Notification (Notification Endpoint)
 //--------------------------------------------------------------------+
 
-/// Communication Interface Management Element Notification Codes
+/// 6.3 Notification Codes
 typedef enum
 {
-  NETWORK_CONNECTION               = 0x00, ///< This notification allows the device to notify the host about network connection status.
-  RESPONSE_AVAILABLE               = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request.
-
-  AUX_JACK_HOOK_STATE              = 0x08,
-  RING_DETECT                      = 0x09,
-
-  SERIAL_STATE                     = 0x20,
-
-  CALL_STATE_CHANGE                = 0x28,
-  LINE_STATE_CHANGE                = 0x29,
-  CONNECTION_SPEED_CHANGE          = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred
-  MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40,
+  CDC_NOTIF_NETWORK_CONNECTION               = 0x00, ///< This notification allows the device to notify the host about network connection status.
+  CDC_NOTIF_RESPONSE_AVAILABLE               = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request.
+  CDC_NOTIF_AUX_JACK_HOOK_STATE              = 0x08,
+  CDC_NOTIF_RING_DETECT                      = 0x09,
+  CDC_NOTIF_SERIAL_STATE                     = 0x20,
+  CDC_NOTIF_CALL_STATE_CHANGE                = 0x28,
+  CDC_NOTIF_LINE_STATE_CHANGE                = 0x29,
+  CDC_NOTIF_CONNECTION_SPEED_CHANGE          = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred
+  CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40,
 }cdc_notification_request_t;
 
 //--------------------------------------------------------------------+
diff --git a/src/class/net/ncm.h b/src/class/net/ncm.h
new file mode 100644
index 000000000..96ba11fbc
--- /dev/null
+++ b/src/class/net/ncm.h
@@ -0,0 +1,69 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef _TUSB_NCM_H_
+#define _TUSB_NCM_H_
+
+#include "common/tusb_common.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// Table 4.3 Data Class Interface Protocol Codes
+typedef enum
+{
+  NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK = 0x01
+} ncm_data_interface_protocol_code_t;
+
+
+// Table 6.2 Class-Specific Request Codes for Network Control Model subclass
+typedef enum
+{
+  NCM_SET_ETHERNET_MULTICAST_FILTERS               = 0x40,
+  NCM_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x41,
+  NCM_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x42,
+  NCM_SET_ETHERNET_PACKET_FILTER                   = 0x43,
+  NCM_GET_ETHERNET_STATISTIC                       = 0x44,
+  NCM_GET_NTB_PARAMETERS                           = 0x80,
+  NCM_GET_NET_ADDRESS                              = 0x81,
+  NCM_SET_NET_ADDRESS                              = 0x82,
+  NCM_GET_NTB_FORMAT                               = 0x83,
+  NCM_SET_NTB_FORMAT                               = 0x84,
+  NCM_GET_NTB_INPUT_SIZE                           = 0x85,
+  NCM_SET_NTB_INPUT_SIZE                           = 0x86,
+  NCM_GET_MAX_DATAGRAM_SIZE                        = 0x87,
+  NCM_SET_MAX_DATAGRAM_SIZE                        = 0x88,
+  NCM_GET_CRC_MODE                                 = 0x89,
+  NCM_SET_CRC_MODE                                 = 0x8A,
+} ncm_request_code_t;
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 2f7d58f99..3e131a85c 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -38,7 +38,7 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-#define NTH16_SIGNATURE 0x484D434E
+#define NTH16_SIGNATURE      0x484D434E
 #define NDP16_SIGNATURE_NCM0 0x304D434E
 #define NDP16_SIGNATURE_NCM1 0x314D434E
 
@@ -114,13 +114,13 @@ typedef struct
   } report_state;
   bool report_pending;
 
-  uint8_t current_ntb; // Index in transmit_ntb[] that is currently being filled with datagrams
-  uint8_t datagram_count; // Number of datagrams in transmit_ntb[current_ntb]
-  uint16_t next_datagram_offset; // Offset in transmit_ntb[current_ntb].data to place the next datagram
-  uint16_t ntb_in_size; // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE
-  uint8_t max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
+  uint8_t  current_ntb;           // Index in transmit_ntb[] that is currently being filled with datagrams
+  uint8_t  datagram_count;        // Number of datagrams in transmit_ntb[current_ntb]
+  uint16_t next_datagram_offset;  // Offset in transmit_ntb[current_ntb].data to place the next datagram
+  uint16_t ntb_in_size;           // Maximum size of transmitted (IN to host) NTBs; initially CFG_TUD_NCM_IN_NTB_MAX_SIZE
+  uint8_t  max_datagrams_per_ntb; // Maximum number of datagrams per NTB; initially CFG_TUD_NCM_MAX_DATAGRAMS_PER_NTB
 
-  uint16_t nth_sequence; // Sequence number counter for transmitted NTBs
+  uint16_t nth_sequence;          // Sequence number counter for transmitted NTBs
 
   bool transferring;
 
@@ -197,25 +197,33 @@ static void ncm_start_tx(void) {
 }
 
 static struct ecm_notify_struct ncm_notify_connected =
-    {
-        .header = {
-            .bmRequestType = 0xA1,
-            .bRequest = 0 /* NETWORK_CONNECTION aka NetworkConnection */,
-            .wValue = 1 /* Connected */,
-            .wLength = 0,
+{
+    .header = {
+        .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_IN
         },
-    };
+        .bRequest      = CDC_NOTIF_NETWORK_CONNECTION,
+        .wValue        = 1 /* Connected */,
+        .wLength       = 0,
+    },
+};
 
 static struct ecm_notify_struct ncm_notify_speed_change =
-    {
-        .header = {
-            .bmRequestType = 0xA1,
-            .bRequest = 0x2A /* CONNECTION_SPEED_CHANGE aka ConnectionSpeedChange */,
-            .wLength = 8,
+{
+    .header = {
+        .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_IN
         },
-        .downlink = 10000000,
-        .uplink = 10000000,
-    };
+        .bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE,
+        .wLength = 8,
+    },
+    .downlink = 10000000,
+    .uplink = 10000000,
+};
 
 void tud_network_recv_renew(void)
 {
@@ -381,7 +389,7 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     case TUSB_REQ_TYPE_CLASS:
       TU_VERIFY (ncm_interface.itf_num == request->wIndex);
 
-      if (0x80 /* GET_NTB_PARAMETERS */ == request->bRequest)
+      if (NCM_GET_NTB_PARAMETERS == request->bRequest)
       {
         tud_control_xfer(rhport, request, (void*)&ntb_parameters, sizeof(ntb_parameters));
       }
@@ -418,7 +426,9 @@ static void handle_incoming_datagram(uint32_t len)
   ncm_interface.num_datagrams = 0;
   ncm_interface.ndp = ndp;
   for (int i = 0; i < num_datagrams && ndp->datagram[i].wDatagramIndex && ndp->datagram[i].wDatagramLength; i++)
+  {
     ncm_interface.num_datagrams++;
+  }
   
   tud_network_recv_renew();
 }
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index ad369b680..6e294465b 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -34,6 +34,8 @@
 #error "Cannot enable both ECM_RNDIS and NCM network drivers"
 #endif
 
+#include "ncm.h"
+
 /* declared here, NOT in usb_descriptors.c, so that the driver can intelligently ZLP as needed */
 #define CFG_TUD_NET_ENDPOINT_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 7575ef42c..8d02de1ff 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -827,16 +827,16 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110),\
   /* CDC-NCM Union */\
   5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\
-  /* CDC-ECM Functional Descriptor */\
+  /* CDC-NCM Functional Descriptor */\
   13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0, \
-  /* CDC-ECM Functional Descriptor */\
+  /* CDC-NCM Functional Descriptor */\
   6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, \
   /* Endpoint Notification */\
   7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 50,\
   /* CDC Data Interface (default inactive) */\
-  9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 1, 0,\
+  9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK, 0,\
   /* CDC Data Interface (alternative active) */\
-  9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, 1, 0,\
+  9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK, 0,\
   /* Endpoint In */\
   7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\
   /* Endpoint Out */\

From b3bfce2cb7213df3d875133de26321542e7ecf08 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 8 Oct 2021 15:49:56 +0700
Subject: [PATCH 0552/2085] update the descriptor endpoint ISO for nrf5x

---
 .../device/video_capture/src/usb_descriptors.c   | 16 ++++------------
 src/class/video/video_device.c                   |  2 +-
 2 files changed, 5 insertions(+), 13 deletions(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index b0e41b97e..404ffe070 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -77,22 +77,14 @@ uint8_t const * tud_descriptor_device_cb(void)
 
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_LEN)
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
   #define EPNUM_VIDEO_IN    0x83
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_CXD56
-  // SAMG doesn't support a same endpoint number with different direction IN and OUT
-  //    e.g EP1 OUT & EP1 IN cannot exist together
-  #define EPNUM_VIDEO_IN    0x81
-
-#elif CFG_TUSB_MCU == OPT_MCU_CXD56
-  // CXD56 doesn't support a same endpoint number with different direction IN and OUT
-  //    e.g EP1 OUT & EP1 IN cannot exist together
-  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
-  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
-  #define EPNUM_VIDEO_IN    0x81
+#elif TU_CHECK_MCU(NRF5X)
+  // nRF5x ISO can only be endpoint 8
+  #define EPNUM_VIDEO_IN    0x88
 
 #else
   #define EPNUM_VIDEO_IN    0x81
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 12ccbd165..ce34b1b49 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -457,7 +457,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
   void const *end = beg + self->len;
   /* The first descriptor is a video control interface descriptor. */
   void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
-  TU_LOG2("    cur %ld\n", cur - beg);
+  TU_LOG2("    cur %d\n", cur - beg);
   TU_VERIFY(cur < end);
 
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;

From 4d170614dc31c083f8b96add1393156c89670dd7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 11 Oct 2021 23:18:24 +0700
Subject: [PATCH 0553/2085] rename some video constants

---
 examples/device/video_capture/src/main.c      |   2 +-
 .../device/video_capture/src/tusb_config.h    |   7 +-
 .../video_capture/src/usb_descriptors.h       |  66 +++---
 src/class/video/video.h                       | 197 ++++++++++--------
 src/class/video/video_device.c                | 190 ++++++++---------
 5 files changed, 238 insertions(+), 224 deletions(-)

diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index f0f4df6eb..a2d95c8f9 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -202,7 +202,7 @@ int tud_video_commit_cb(uint_fast8_t ctl_idx, uint_fast8_t stm_idx,
   (void)ctl_idx; (void)stm_idx;
   /* convert unit to ms from 100 ns */
   interval_ms = parameters->dwFrameInterval / 10000;
-  return VIDEO_NO_ERROR;
+  return VIDEO_ERROR_NONE;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index 5d2d5470c..4feb6a48a 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -91,16 +91,11 @@
 #endif
 
 //------------- CLASS -------------//
-#define CFG_TUD_CDC              0
-#define CFG_TUD_MSC              0
-#define CFG_TUD_HID              0
-#define CFG_TUD_MIDI             0
-#define CFG_TUD_AUDIO            0
 // The number of video control interfaces
 #define CFG_TUD_VIDEO            1
+
 // The number of video streaming interfaces
 #define CFG_TUD_VIDEO_STREAMING  1
-#define CFG_TUD_VENDOR           0
 
 // video streaming endpoint size
 #define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE  256
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 403dc56a1..340b3f799 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -75,40 +75,38 @@ enum {
 
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, ITF_NUM_TOTAL, _stridx), \
-    /* Video control 0 */ \
-    TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
-      TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
-           /* wTotalLength - bLength */ \
-           TUD_VIDEO_DESC_INPUT_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-           UVC_CLOCK_FREQUENCY, 1), \
-        TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL,\
-                                   VIDEO_TT_COMPOSITE_CONNECTOR, 0, 0), \
-        TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL,\
-                                   VIDEO_TT_STREAMING, 0, 1, 0), \
-    /* Video stream alt. 0 */ \
-    TUD_VIDEO_DESC_STD_VS( 1, 0, 0, 0), \
-      /* Video stream header for without still image capture */ \
-      TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
-          /*wTotalLength - bLength */\
-          TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-          + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
-          + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
-          _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
-          /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
-          /*bmaControls(1)*/0), \
-        /* Video stream format */ \
-        TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
-          /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
-          /* Video stream frame format */ \
-          TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
-              _width * _height * 16, _width * _height * 16 * _fps, \
-              _width * _height * 16, \
-              (10000000/_fps), (10000000/_fps), 10000000, 100000), \
-          TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
-    /* VS alt 1 */\
-    TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \
-      /* EP */ \
-      TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
+  /* Video control 0 */ \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
+    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
+         /* wTotalLength - bLength */ \
+         TUD_VIDEO_DESC_INPUT_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
+         UVC_CLOCK_FREQUENCY, 1), \
+      TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, VIDEO_ETT_COMPOSITE_CONNECTOR, 0, 0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+  /* Video stream alt. 0 */ \
+  TUD_VIDEO_DESC_STD_VS( 1, 0, 0, 0), \
+    /* Video stream header for without still image capture */ \
+    TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+        /*wTotalLength - bLength */\
+        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+        + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+        /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+        /*bmaControls(1)*/0), \
+      /* Video stream format */ \
+      TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /* Video stream frame format */ \
+        TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
+            _width * _height * 16, _width * _height * 16 * _fps, \
+            _width * _height * 16, \
+            (10000000/_fps), (10000000/_fps), 10000000, 100000), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+  /* VS alt 1 */\
+  TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \
+    /* EP */ \
+    TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
 
 
 #endif
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 3c27c8093..8288e4961 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -29,18 +29,20 @@
 
 #include "common/tusb_common.h"
 
+// Table 3-19 Color Matching Descriptor
 typedef enum {
   VIDEO_COLOR_PRIMARIES_UNDEFINED = 0x00,
-  VIDEO_COLOR_PRIMARIES_BT709,
+  VIDEO_COLOR_PRIMARIES_BT709, // sRGB (default)
   VIDEO_COLOR_PRIMARIES_BT470_2M,
   VIDEO_COLOR_PRIMARIES_BT470_2BG,
   VIDEO_COLOR_PRIMARIES_SMPTE170M,
   VIDEO_COLOR_PRIMARIES_SMPTE240M,
 } video_color_primaries_t;
 
+// Table 3-19 Color Matching Descriptor
 typedef enum {
   VIDEO_COLOR_XFER_CH_UNDEFINED = 0x00,
-  VIDEO_COLOR_XFER_CH_BT709,
+  VIDEO_COLOR_XFER_CH_BT709, // default
   VIDEO_COLOR_XFER_CH_BT470_2M,
   VIDEO_COLOR_XFER_CH_BT470_2BG,
   VIDEO_COLOR_XFER_CH_SMPTE170M,
@@ -49,30 +51,31 @@ typedef enum {
   VIDEO_COLOR_XFER_CH_SRGB,
 } video_color_transfer_characteristics_t;
 
+// Table 3-19 Color Matching Descriptor
 typedef enum {
   VIDEO_COLOR_COEF_UNDEFINED = 0x00,
   VIDEO_COLOR_COEF_BT709,
   VIDEO_COLOR_COEF_FCC,
   VIDEO_COLOR_COEF_BT470_2BG,
-  VIDEO_COLOR_COEF_SMPTE170M,
+  VIDEO_COLOR_COEF_SMPTE170M, // BT.601 default
   VIDEO_COLOR_COEF_SMPTE240M,
 } video_color_matrix_coefficients_t;
 
-/* 4.2.1.2 */
+/* 4.2.1.2 Request Error Code Control */
 typedef enum {
-  VIDEO_NO_ERROR = 0, /* The request succeeded. */
-  VIDEO_NOT_READY,
-  VIDEO_WRONG_STATE,
-  VIDEO_POWER,
-  VIDEO_OUT_OF_RANGE,
-  VIDEO_INVALID_UNIT,
-  VIDEO_INVALID_CONTROL,
-  VIDEO_INVALID_REQUEST,
-  VIDEO_INVALID_VALUE_WITHIN_RANGE,
-  VIDEO_UNKNOWN = 0xFF,
+  VIDEO_ERROR_NONE = 0, /* The request succeeded. */
+  VIDEO_ERROR_NOT_READY,
+  VIDEO_ERROR_WRONG_STATE,
+  VIDEO_ERROR_POWER,
+  VIDEO_ERROR_OUT_OF_RANGE,
+  VIDEO_ERROR_INVALID_UNIT,
+  VIDEO_ERROR_INVALID_CONTROL,
+  VIDEO_ERROR_INVALID_REQUEST,
+  VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE,
+  VIDEO_ERROR_UNKNOWN = 0xFF,
 } video_error_code_t;
 
-/* A.2 */
+/* A.2 Interface Subclass */
 typedef enum {
   VIDEO_SUBCLASS_UNDEFINED = 0x00,
   VIDEO_SUBCLASS_CONTROL,
@@ -80,79 +83,86 @@ typedef enum {
   VIDEO_SUBCLASS_INTERFACE_COLLECTION,
 } video_subclass_type_t;
 
-/* A.3 */
+/* A.3 Interface Protocol */
 typedef enum {
-  VIDEO_INT_PROTOCOL_CODE_UNDEF = 0x00,
-  VIDEO_INT_PROTOCOL_CODE_15,
+  VIDEO_ITF_PROTOCOL_UNDEFINED = 0x00,
+  VIDEO_ITF_PROTOCOL_15,
 } video_interface_protocol_code_t;
 
-/* A.5 */
+/* A.5 Class-Specific VideoControl Interface Descriptor Subtypes */
 typedef enum {
-  VIDEO_CS_VC_INTERFACE_VC_DESCRIPTOR_UNDEF = 0x00,
-  VIDEO_CS_VC_INTERFACE_HEADER,
-  VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL,
-  VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL,
-  VIDEO_CS_VC_INTERFACE_SELECTOR_UNIT,
-  VIDEO_CS_VC_INTERFACE_PROCESSING_UNIT,
-  VIDEO_CS_VC_INTERFACE_EXTENSION_UNIT,
-  VIDEO_CS_VC_INTERFACE_ENCODING_UNIT,
-  VIDEO_CS_VC_INTERFACE_MAX,
+  VIDEO_CS_VC_UNDEFINED = 0x00,
+  VIDEO_CS_VC_HEADER,
+  VIDEO_CS_VC_INPUT_TERMINAL,
+  VIDEO_CS_VC_OUTPUT_TERMINAL,
+  VIDEO_CS_VC_SELECTOR_UNIT,
+  VIDEO_CS_VC_PROCESSING_UNIT,
+  VIDEO_CS_VC_EXTENSION_UNIT,
+  VIDEO_CS_VC_ENCODING_UNIT,
+  VIDEO_CS_VC_MAX,
 } video_cs_vc_interface_subtype_t;
 
-/* A.6 */
+/* A.6 Class-Specific VideoStreaming Interface Descriptor Subtypes */
 typedef enum {
-  VIDEO_CS_VS_INTERFACE_VS_DESCRIPTOR_UNDEF = 0x00,
-  VIDEO_CS_VS_INTERFACE_INPUT_HEADER,
-  VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER,
-  VIDEO_CS_VS_INTERFACE_STILL_IMAGE_FRAME,
-  VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED,
-  VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED,
-  VIDEO_CS_VS_INTERFACE_FORMAT_MJPEG,
-  VIDEO_CS_VS_INTERFACE_FRAME_MJPEG,
-  VIDEO_CS_VS_INTERFACE_FORMAT_MPEG2TS      = 0x0A,
-  VIDEO_CS_VS_INTERFACE_FORMAT_DV           = 0x0c,
-  VIDEO_CS_VS_INTERFACE_COLORFORMAT,
-  VIDEO_CS_VS_INTERFACE_FORMAT_FRAME_BASED  = 0x10,
-  VIDEO_CS_VS_INTERFACE_FRAME_FRAME_BASED,
-  VIDEO_CS_VS_INTERFACE_FORMAT_STREAM_BASED,
-  VIDEO_CS_VS_INTERFACE_FORMAT_H264,
-  VIDEO_CS_VS_INTERFACE_FRAME_H264,
-  VIDEO_CS_VS_INTERFACE_FORMAT_H264_SIMULCAST,
-  VIDEO_CS_VS_INTERFACE_FORMAT_VP8,
-  VIDEO_CS_VS_INTERFACE_FRAME_VP8,
-  VIDEO_CS_VS_INTERFACE_FORMAT_VP8_SIMULCAST,
+  VIDEO_CS_VS_UNDEFINED             = 0x00,
+  VIDEO_CS_VS_INPUT_HEADER          = 0x01,
+  VIDEO_CS_VS_OUTPUT_HEADER         = 0x02,
+  VIDEO_CS_VS_STILL_IMAGE_FRAME     = 0x03,
+  VIDEO_CS_VS_FORMAT_UNCOMPRESSED   = 0x04,
+  VIDEO_CS_VS_FRAME_UNCOMPRESSED    = 0x05,
+  VIDEO_CS_VS_FORMAT_MJPEG          = 0x06,
+  VIDEO_CS_VS_FRAME_MJPEG           = 0x07,
+  VIDEO_CS_VS_FORMAT_MPEG2TS        = 0x0A,
+  VIDEO_CS_VS_FORMAT_DV             = 0x0C,
+  VIDEO_CS_VS_COLORFORMAT           = 0x0D,
+  VIDEO_CS_VS_FORMAT_FRAME_BASED    = 0x10,
+  VIDEO_CS_VS_FRAME_FRAME_BASED     = 0x11,
+  VIDEO_CS_VS_FORMAT_STREAM_BASED   = 0x12,
+  VIDEO_CS_VS_FORMAT_H264           = 0x13,
+  VIDEO_CS_VS_FRAME_H264            = 0x14,
+  VIDEO_CS_VS_FORMAT_H264_SIMULCAST = 0x15,
+  VIDEO_CS_VS_FORMAT_VP8            = 0x16,
+  VIDEO_CS_VS_FRAME_VP8             = 0x17,
+  VIDEO_CS_VS_FORMAT_VP8_SIMULCAST  = 0x18,
 } video_cs_vs_interface_subtype_t;
 
-/* A.8 */
+/* A.7. Class-Specific Endpoint Descriptor Subtypes */
 typedef enum {
-  VIDEO_REQUEST_UNDEF = 0x00,
-  VIDEO_REQUEST_SET_CUR,
+  VIDEO_CS_EP_UNDEFINED = 0x00,
+  VIDEO_CS_EP_GENERAL,
+  VIDEO_CS_EP_ENDPOINT,
+  VIDEO_CS_EP_INTERRUPT
+} video_cs_ep_subtype_t;
+
+/* A.8 Class-Specific Request Codes */
+typedef enum {
+  VIDEO_REQUEST_UNDEFINED   = 0x00,
+  VIDEO_REQUEST_SET_CUR     = 0x01,
   VIDEO_REQUEST_SET_CUR_ALL = 0x11,
-  VIDEO_REQUEST_GET = 0x80,
-  VIDEO_REQUEST_GET_CUR,
-  VIDEO_REQUEST_GET_MIN,
-  VIDEO_REQUEST_GET_MAX,
-  VIDEO_REQUEST_GET_RES,
-  VIDEO_REQUEST_GET_LEN,
-  VIDEO_REQUEST_GET_INFO,
-  VIDEO_REQUEST_GET_DEF,
+  VIDEO_REQUEST_GET_CUR     = 0x81,
+  VIDEO_REQUEST_GET_MIN     = 0x82,
+  VIDEO_REQUEST_GET_MAX     = 0x83,
+  VIDEO_REQUEST_GET_RES     = 0x84,
+  VIDEO_REQUEST_GET_LEN     = 0x85,
+  VIDEO_REQUEST_GET_INFO    = 0x86,
+  VIDEO_REQUEST_GET_DEF     = 0x87,
   VIDEO_REQUEST_GET_CUR_ALL = 0x91,
-  VIDEO_REQUEST_GET_MIN_ALL,
-  VIDEO_REQUEST_GET_MAX_ALL,
-  VIDEO_REQUEST_GET_RES_ALL,
+  VIDEO_REQUEST_GET_MIN_ALL = 0x92,
+  VIDEO_REQUEST_GET_MAX_ALL = 0x93,
+  VIDEO_REQUEST_GET_RES_ALL = 0x94,
   VIDEO_REQUEST_GET_DEF_ALL = 0x97
 } video_control_request_t;
 
-/* A.9.1 */
+/* A.9.1 VideoControl Interface Control Selectors */
 typedef enum {
-  VIDEO_VC_CTL_UNDEF = 0x00,
+  VIDEO_VC_CTL_UNDEFINED = 0x00,
   VIDEO_VC_CTL_VIDEO_POWER_MODE,
   VIDEO_VC_CTL_REQUEST_ERROR_CODE,
 } video_interface_control_selector_t;
 
-/* A.9.8 */
+/* A.9.8 VideoStreaming Interface Control Selectors */
 typedef enum {
-  VIDEO_VS_CTL_UNDEF = 0x00,
+  VIDEO_VS_CTL_UNDEFINED = 0x00,
   VIDEO_VS_CTL_PROBE,
   VIDEO_VS_CTL_COMMIT,
   VIDEO_VS_CTL_STILL_PROBE,
@@ -166,20 +176,31 @@ typedef enum {
 
 /* B. Terminal Types */
 typedef enum {
+  // Terminal
   VIDEO_TT_VENDOR_SPECIFIC         = 0x0100,
-  VIDEO_TT_STREAMING,
+  VIDEO_TT_STREAMING               = 0x0101,
+
+  // Input
   VIDEO_ITT_VENDOR_SPECIFIC        = 0x0200,
-  VIDEO_ITT_CAMERA,
-  VIDEO_ITT_MEDIA_TRANSPORT_INPUT,
+  VIDEO_ITT_CAMERA                 = 0x0201,
+  VIDEO_ITT_MEDIA_TRANSPORT_INPUT  = 0x0202,
+
+  // Output
   VIDEO_OTT_VENDOR_SPECIFIC        = 0x0300,
-  VIDEO_OTT_DISPLAY,
-  VIDEO_OTT_MEDIA_TRANSPORT_OUTPUT,
-  VIDEO_TT_EXTERNAL_VENDOR_SPEIFIC = 0x0400,
-  VIDEO_TT_COMPOSITE_CONNECTOR,
-  VIDEO_TT_SVIDEO_CONNECTOR,
-  VIDEO_TT_COMPONENT_CONNECTOR,
+  VIDEO_OTT_DISPLAY                = 0x0301,
+  VIDEO_OTT_MEDIA_TRANSPORT_OUTPUT = 0x0302,
+
+  // External
+  VIDEO_ETT_VENDOR_SPEIFIC         = 0x0400,
+  VIDEO_ETT_COMPOSITE_CONNECTOR    = 0x0401,
+  VIDEO_ETT_SVIDEO_CONNECTOR       = 0x0402,
+  VIDEO_ETT_COMPONENT_CONNECTOR    = 0x0403,
 } video_terminal_type_t;
 
+//--------------------------------------------------------------------+
+// Descriptors
+//--------------------------------------------------------------------+
+
 /* 2.3.4.2 */
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
@@ -369,44 +390,44 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 #define TUD_VIDEO_DESC_IAD(_firstitfs, _nitfs, _stridx) \
   TUD_VIDEO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, \
   _firstitfs, _nitfs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_INTERFACE_COLLECTION, \
-  VIDEO_INT_PROTOCOL_CODE_UNDEF, _stridx
+  VIDEO_ITF_PROTOCOL_UNDEFINED, _stridx
 
 #define TUD_VIDEO_DESC_STD_VC(_itfnum, _nEPs, _stridx) \
   TUD_VIDEO_DESC_STD_VC_LEN, TUSB_DESC_INTERFACE, _itfnum, /* fixed to zero */ 0x00, \
-  _nEPs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_CONTROL, VIDEO_INT_PROTOCOL_CODE_15, _stridx
+  _nEPs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_CONTROL, VIDEO_ITF_PROTOCOL_15, _stridx
 
 /* 3.7.2 */
 #define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, ...)	\
-  TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_HEADER, \
+  TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_HEADER, \
   U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__))), \
   U32_TO_U8S_LE(_clkfreq), TU_ARGS_NUM(__VA_ARGS__), __VA_ARGS__
 
 /* 3.7.2.1 */
 #define TUD_VIDEO_DESC_INPUT_TERM(_tid, _tt, _at, _stridx) \
-  TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL, \
+  TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INPUT_TERMINAL, \
     _tid, U16_TO_U8S_LE(_tt), _at, _stridx
 
 /* 3.7.2.2 */
 #define TUD_VIDEO_DESC_OUTPUT_TERM(_tid, _tt, _at, _srcid, _stridx) \
-  TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INTERFACE_OUTPUT_TERMINAL, \
+  TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_OUTPUT_TERMINAL, \
     _tid, U16_TO_U8S_LE(_tt), _at, _srcid, _stridx
 
 /* 3.9.1 */
 #define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx) \
   TUD_VIDEO_DESC_STD_VS_LEN, TUSB_DESC_INTERFACE, _itfnum, _alt, \
-  _epn, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_STREAMING, VIDEO_INT_PROTOCOL_CODE_15, _stridx
+  _epn, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_STREAMING, VIDEO_ITF_PROTOCOL_15, _stridx
 
 /* 3.9.2.1 */
 #define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, ...) \
   TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \
-  VIDEO_CS_VS_INTERFACE_INPUT_HEADER, _numfmt, \
+  VIDEO_CS_VS_INPUT_HEADER, _numfmt, \
   U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \
   _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
 /* 3.9.2.2 */
 #define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totallen, _ep, _inf, _termlnk, ...) \
   TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \
-  VIDEO_CS_VS_INTERFACE_OUTPUT_HEADER, _numfmt, \
+  VIDEO_CS_VS_OUTPUT_HEADER, _numfmt, \
   U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \
   _ep, _inf, _termlnk, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
@@ -415,13 +436,13 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 
 #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfrmdesc, \
   _guid, _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \
-  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FORMAT_UNCOMPRESSED, \
   _fmtidx, _numfrmdesc, TUD_VIDEO_GUID(_guid), \
   _bitsperpix, _frmidx, _asrx,  _asry, _interlace, _cp
 
 /* Uncompressed 3.1.2 Table 3-3 */
 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \
-  TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \
+  TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, \
   _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
   U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), 0, \
   U32_TO_U8S_LE(_minfrminterval), U32_TO_U8S_LE(_maxfrminterval), U32_TO_U8S_LE(_frmintervalstep)
@@ -429,14 +450,14 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 /* Uncompressed 3.1.2 Table 3-4 */
 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \
   TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \
-  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, \
   _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
   U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
 /* 3.9.2.6 */
 #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(_color, _trns, _mat) \
   TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN, \
-  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_COLORFORMAT, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_COLORFORMAT, \
   _color, _trns, _mat
 
 /* 3.10.1.1 */
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index ce34b1b49..a1f886ed8 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -259,8 +259,8 @@ static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid)
   void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength;
   for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
     tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
-    if ((VIDEO_CS_VC_INTERFACE_INPUT_TERMINAL  <= itf->bDescriptorSubtype
-         && itf->bDescriptorSubtype < VIDEO_CS_VC_INTERFACE_MAX)
+    if ((VIDEO_CS_VC_INPUT_TERMINAL  <= itf->bDescriptorSubtype
+         && itf->bDescriptorSubtype < VIDEO_CS_VC_MAX)
         && itf->bEntityId == entityid) {
       return itf;
     }
@@ -280,14 +280,14 @@ static inline void const* _end_of_streaming_descriptor(void const *desc)
 static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum)
 {
   return (tusb_desc_cs_video_fmt_uncompressed_t const*)
-    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FORMAT_UNCOMPRESSED, fmtnum);
+    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FORMAT_UNCOMPRESSED, fmtnum);
 }
 
 /** Find the first frame descriptor with the specified format number. */
 static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum)
 {
   return (tusb_desc_cs_video_frm_uncompressed_t const*)
-    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_UNCOMPRESSED, frmnum);
+    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, frmnum);
 }
 
 /** Set uniquely determined values to variables that have not been set
@@ -581,27 +581,27 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage,
 {
   switch (request->bRequest) {
   case TUSB_REQ_GET_INTERFACE:
-    if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-    TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+    if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+    TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
     tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[ctl_idx]);
-    if (!vc) return VIDEO_UNKNOWN;
+    if (!vc) return VIDEO_ERROR_UNKNOWN;
     if (tud_control_xfer(rhport, request,
                          (void*)&vc->std.bAlternateSetting,
                          sizeof(vc->std.bAlternateSetting)))
-      return VIDEO_NO_ERROR;
-    return VIDEO_UNKNOWN;
+      return VIDEO_ERROR_NONE;
+    return VIDEO_ERROR_UNKNOWN;
   case TUSB_REQ_SET_INTERFACE:
-    if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-    TU_VERIFY(0 == request->wLength, VIDEO_UNKNOWN);
+    if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+    TU_VERIFY(0 == request->wLength, VIDEO_ERROR_UNKNOWN);
     if (!_close_vc_itf(rhport, &_videod_itf[ctl_idx]))
-      return VIDEO_UNKNOWN;
+      return VIDEO_ERROR_UNKNOWN;
     if (!_open_vc_itf(rhport, &_videod_itf[ctl_idx], request->wValue))
-      return VIDEO_UNKNOWN;
+      return VIDEO_ERROR_UNKNOWN;
     tud_control_status(rhport, request);
-    return VIDEO_NO_ERROR;
+    return VIDEO_ERROR_NONE;
   default: /* Unknown/Unsupported request */
     TU_BREAKPOINT();
-    return VIDEO_INVALID_REQUEST;
+    return VIDEO_ERROR_INVALID_REQUEST;
   }
 }
 
@@ -616,41 +616,41 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage,
     switch (request->bRequest) {
     case VIDEO_REQUEST_SET_CUR:
       if (stage == CONTROL_STAGE_SETUP) {
-        TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+        TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
         if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
-          return VIDEO_UNKNOWN;
+          return VIDEO_ERROR_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
         if (tud_video_power_mode_cb)
           return tud_video_power_mode_cb(ctl_idx, self->power_mode);
       }
-      return VIDEO_NO_ERROR;
+      return VIDEO_ERROR_NONE;
     case VIDEO_REQUEST_GET_CUR:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+      TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
       if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
-        return VIDEO_UNKNOWN;
-      return VIDEO_NO_ERROR;
+        return VIDEO_ERROR_UNKNOWN;
+      return VIDEO_ERROR_NONE;
     case VIDEO_REQUEST_GET_INFO:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+      TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
       if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
-        return VIDEO_UNKNOWN;
-      return VIDEO_NO_ERROR;
+        return VIDEO_ERROR_UNKNOWN;
+      return VIDEO_ERROR_NONE;
     default: break;
     }
     break;
   case VIDEO_VC_CTL_REQUEST_ERROR_CODE:
     switch (request->bRequest) {
     case VIDEO_REQUEST_GET_CUR:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
       if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)))
-        return VIDEO_UNKNOWN;
-      return VIDEO_NO_ERROR;
+        return VIDEO_ERROR_UNKNOWN;
+      return VIDEO_ERROR_NONE;
     case VIDEO_REQUEST_GET_INFO:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
       if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)))
-        return VIDEO_UNKNOWN;
-      return VIDEO_NO_ERROR;
+        return VIDEO_ERROR_UNKNOWN;
+      return VIDEO_ERROR_NONE;
     default: break;
     }
     break;
@@ -658,7 +658,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage,
   }
   /* Unknown/Unsupported request */
   TU_BREAKPOINT();
-  return VIDEO_INVALID_REQUEST;
+  return VIDEO_ERROR_INVALID_REQUEST;
 }
 
 static int handle_video_ctl_req(uint8_t rhport, uint8_t stage,
@@ -675,11 +675,11 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage,
       return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx);
     } else {
       if (!_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id))
-        return VIDEO_INVALID_REQUEST;
-      return VIDEO_INVALID_REQUEST;
+        return VIDEO_ERROR_INVALID_REQUEST;
+      return VIDEO_ERROR_INVALID_REQUEST;
     }
   default:
-    return VIDEO_INVALID_REQUEST;
+    return VIDEO_ERROR_INVALID_REQUEST;
   }
 }
 
@@ -690,24 +690,24 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage,
   videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx];
   switch (request->bRequest) {
   case TUSB_REQ_GET_INTERFACE:
-    if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-    TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+    if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+    TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
     tusb_desc_vs_itf_t const *vs = _get_desc_vs(self);
-    if (!vs) return VIDEO_UNKNOWN;
+    if (!vs) return VIDEO_ERROR_UNKNOWN;
     if (tud_control_xfer(rhport, request,
                          (void*)&vs->std.bAlternateSetting,
                          sizeof(vs->std.bAlternateSetting)))
-      return VIDEO_NO_ERROR;
-    return VIDEO_UNKNOWN;
+      return VIDEO_ERROR_NONE;
+    return VIDEO_ERROR_UNKNOWN;
   case TUSB_REQ_SET_INTERFACE:
-    if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+    if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
     if (!_open_vs_itf(rhport, self, request->wValue))
-      return VIDEO_UNKNOWN;
+      return VIDEO_ERROR_UNKNOWN;
     tud_control_status(rhport, request);
-    return VIDEO_NO_ERROR;
+    return VIDEO_ERROR_NONE;
   default: /* Unknown/Unsupported request */
     TU_BREAKPOINT();
-    return VIDEO_INVALID_REQUEST;
+    return VIDEO_ERROR_INVALID_REQUEST;
   }
 }
 
@@ -722,16 +722,16 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
   case VIDEO_VS_CTL_STREAM_ERROR_CODE:
     switch (request->bRequest) {
     case VIDEO_REQUEST_GET_CUR:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
       /* TODO */
       if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)))
-        return VIDEO_UNKNOWN;
-      return VIDEO_NO_ERROR;
+        return VIDEO_ERROR_UNKNOWN;
+      return VIDEO_ERROR_NONE;
     case VIDEO_REQUEST_GET_INFO:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
       if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)))
-        return VIDEO_UNKNOWN;
-      return VIDEO_NO_ERROR;
+        return VIDEO_ERROR_UNKNOWN;
+      return VIDEO_ERROR_NONE;
     default: break;
     }
     break;
@@ -739,56 +739,56 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
     switch (request->bRequest) {
     case VIDEO_REQUEST_SET_CUR:
       if (stage == CONTROL_STAGE_SETUP) {
-        TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN);
+        TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
         if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
-          return VIDEO_UNKNOWN;
+          return VIDEO_ERROR_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
         if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf))
-          return VIDEO_INVALID_VALUE_WITHIN_RANGE;
+          return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE;
       }
-      return VIDEO_NO_ERROR;
+      return VIDEO_ERROR_NONE;
     case VIDEO_REQUEST_GET_CUR:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+      TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
       if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
-        return VIDEO_NO_ERROR;
-      return VIDEO_UNKNOWN;
+        return VIDEO_ERROR_NONE;
+      return VIDEO_ERROR_UNKNOWN;
     case VIDEO_REQUEST_GET_MIN: {
       video_probe_and_commit_control_t tmp;
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+      TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
       tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
       if (!_negotiate_streaming_parameters(self, false, &tmp))
-        return VIDEO_INVALID_VALUE_WITHIN_RANGE;
+        return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE;
       if (tud_control_xfer(rhport, request, &tmp,
                            sizeof(video_probe_and_commit_control_t)))
-        return VIDEO_NO_ERROR;
-      return VIDEO_UNKNOWN;
+        return VIDEO_ERROR_NONE;
+      return VIDEO_ERROR_UNKNOWN;
     }
     case VIDEO_REQUEST_GET_MAX: {
       video_probe_and_commit_control_t tmp;
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+      TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
       tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
       if (!_negotiate_streaming_parameters(self, true, &tmp))
-        return VIDEO_INVALID_VALUE_WITHIN_RANGE;
+        return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE;
       if (tud_control_xfer(rhport, request, self->ep_buf,
                            sizeof(video_probe_and_commit_control_t)))
-        return VIDEO_NO_ERROR;
-      return VIDEO_UNKNOWN;
+        return VIDEO_ERROR_NONE;
+      return VIDEO_ERROR_UNKNOWN;
     }
     case VIDEO_REQUEST_GET_RES:
-      return VIDEO_UNKNOWN;
+      return VIDEO_ERROR_UNKNOWN;
     case VIDEO_REQUEST_GET_DEF:
-      return VIDEO_UNKNOWN;
+      return VIDEO_ERROR_UNKNOWN;
     case VIDEO_REQUEST_GET_LEN:
-      return VIDEO_UNKNOWN;
+      return VIDEO_ERROR_UNKNOWN;
     case VIDEO_REQUEST_GET_INFO:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+      TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
       if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
-        return VIDEO_NO_ERROR;
-      return VIDEO_UNKNOWN;
+        return VIDEO_ERROR_NONE;
+      return VIDEO_ERROR_UNKNOWN;
     default: break;
     }
     break;
@@ -796,29 +796,29 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
     switch (request->bRequest) {
     case VIDEO_REQUEST_SET_CUR:
       if (stage == CONTROL_STAGE_SETUP) {
-        TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_UNKNOWN);
+        TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
         if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
-          return VIDEO_UNKNOWN;
+          return VIDEO_ERROR_UNKNOWN;
       } else if (stage == CONTROL_STAGE_ACK) {
         if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf))
-          return VIDEO_INVALID_VALUE_WITHIN_RANGE;
+          return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE;
         if (tud_video_commit_cb)
           return tud_video_commit_cb(self->index_vc, self->index_vs,
                                      (video_probe_and_commit_control_t*)self->ep_buf);
       }
-      return VIDEO_NO_ERROR;
+      return VIDEO_ERROR_NONE;
     case VIDEO_REQUEST_GET_CUR:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_VERIFY(request->wLength, VIDEO_UNKNOWN);
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+      TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
       if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
-        return VIDEO_NO_ERROR;
-      return VIDEO_UNKNOWN;
+        return VIDEO_ERROR_NONE;
+      return VIDEO_ERROR_UNKNOWN;
     case VIDEO_REQUEST_GET_INFO:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_NO_ERROR;
-      TU_VERIFY(1 == request->wLength, VIDEO_UNKNOWN);
+      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+      TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
       if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
-        return VIDEO_NO_ERROR;
-      return VIDEO_UNKNOWN;
+        return VIDEO_ERROR_NONE;
+      return VIDEO_ERROR_UNKNOWN;
     default: break;
     }
     break;
@@ -834,7 +834,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
   }
   /* Unknown/Unsupported request */
   TU_BREAKPOINT();
-  return VIDEO_INVALID_REQUEST;
+  return VIDEO_ERROR_INVALID_REQUEST;
 }
 
 static int handle_video_stm_req(uint8_t rhport, uint8_t stage,
@@ -846,12 +846,12 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage,
     return handle_video_stm_std_req(rhport, stage, request, stm_idx);
   case TUSB_REQ_TYPE_CLASS:
     if (TU_U16_HIGH(request->wIndex))
-      return VIDEO_INVALID_REQUEST;
+      return VIDEO_ERROR_INVALID_REQUEST;
     return handle_video_stm_cs_req(rhport, stage, request, stm_idx);
   default:
-    return VIDEO_INVALID_REQUEST;
+    return VIDEO_ERROR_INVALID_REQUEST;
   }
-  return VIDEO_UNKNOWN;
+  return VIDEO_ERROR_UNKNOWN;
 }
 
 //--------------------------------------------------------------------+
@@ -942,9 +942,9 @@ void videod_reset(uint8_t rhport)
 
 uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
 {
-  TU_VERIFY((TUSB_CLASS_VIDEO           == itf_desc->bInterfaceClass) &&
-            (VIDEO_SUBCLASS_CONTROL     == itf_desc->bInterfaceSubClass) &&
-            (VIDEO_INT_PROTOCOL_CODE_15 == itf_desc->bInterfaceProtocol), 0);
+  TU_VERIFY((TUSB_CLASS_VIDEO       == itf_desc->bInterfaceClass) &&
+            (VIDEO_SUBCLASS_CONTROL == itf_desc->bInterfaceSubClass) &&
+            (VIDEO_ITF_PROTOCOL_15  == itf_desc->bInterfaceProtocol), 0);
 
   /* Find available interface */
   videod_interface_t *self = NULL;

From 7afcb1e5d51ebbbbf602840887949dc69b33c5b4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 12 Oct 2021 00:56:20 +0700
Subject: [PATCH 0554/2085] minor code clean up without functionality changes

---
 src/class/video/video_device.c | 507 +++++++++++++++++----------------
 1 file changed, 264 insertions(+), 243 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index a1f886ed8..da190da47 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -1,9 +1,8 @@
 /* 
  * The MIT License (MIT)
  *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- * Copyright (c) 2020 Reinhard Panhuber, Jerzy Kasenberg
  * Copyright (c) 2021 Koji KITAYAMA
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -300,8 +299,7 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   uint_fast8_t fmtnum = param->bFormatIndex;
   TU_ASSERT(fmtnum <= vs->stm.bNumFormats);
   if (!fmtnum) {
-    if (1 < vs->stm.bNumFormats)
-      return true; /* Need to negotiate all variables. */
+    if (1 < vs->stm.bNumFormats) return true; /* Need to negotiate all variables. */
     fmtnum = 1;
     param->bFormatIndex = 1;
   }
@@ -326,8 +324,7 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   uint_fast8_t frmnum = param->bFrameIndex;
   TU_ASSERT(frmnum <= fmt->bNumFrameDescriptors);
   if (!frmnum) {
-    if (1 < fmt->bNumFrameDescriptors)
-      return true;
+    if (1 < fmt->bNumFrameDescriptors) return true;
     frmnum = 1;
     param->bFrameIndex = 1;
   }
@@ -344,8 +341,9 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   uint_fast32_t interval = param->dwFrameInterval;
   if (!interval) {
     if ((1 < frm->bFrameIntervalType) ||
-        ((0 == frm->bFrameIntervalType) && (frm->dwFrameInterval[1] != frm->dwFrameInterval[0])))
+        ((0 == frm->bFrameIntervalType) && (frm->dwFrameInterval[1] != frm->dwFrameInterval[0]))) {
       return true;
+    }
     interval = frm->dwFrameInterval[0];
     param->dwFrameInterval = interval;
   }
@@ -580,28 +578,31 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage,
                                     uint_fast8_t ctl_idx)
 {
   switch (request->bRequest) {
-  case TUSB_REQ_GET_INTERFACE:
-    if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-    TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-    tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[ctl_idx]);
-    if (!vc) return VIDEO_ERROR_UNKNOWN;
-    if (tud_control_xfer(rhport, request,
-                         (void*)&vc->std.bAlternateSetting,
-                         sizeof(vc->std.bAlternateSetting)))
+    case TUSB_REQ_GET_INTERFACE:
+      if (stage == CONTROL_STAGE_SETUP)
+      {
+        TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
+        tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[ctl_idx]);
+        TU_VERIFY(vc, VIDEO_ERROR_UNKNOWN);
+
+        TU_VERIFY(tud_control_xfer(rhport, request, (void*)&vc->std.bAlternateSetting, sizeof(vc->std.bAlternateSetting)),
+                  VIDEO_ERROR_UNKNOWN);
+      }
       return VIDEO_ERROR_NONE;
-    return VIDEO_ERROR_UNKNOWN;
-  case TUSB_REQ_SET_INTERFACE:
-    if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-    TU_VERIFY(0 == request->wLength, VIDEO_ERROR_UNKNOWN);
-    if (!_close_vc_itf(rhport, &_videod_itf[ctl_idx]))
-      return VIDEO_ERROR_UNKNOWN;
-    if (!_open_vc_itf(rhport, &_videod_itf[ctl_idx], request->wValue))
-      return VIDEO_ERROR_UNKNOWN;
-    tud_control_status(rhport, request);
-    return VIDEO_ERROR_NONE;
-  default: /* Unknown/Unsupported request */
-    TU_BREAKPOINT();
-    return VIDEO_ERROR_INVALID_REQUEST;
+
+    case TUSB_REQ_SET_INTERFACE:
+      if (stage == CONTROL_STAGE_SETUP)
+      {
+        TU_VERIFY(0 == request->wLength, VIDEO_ERROR_UNKNOWN);
+        TU_VERIFY(_close_vc_itf(rhport, &_videod_itf[ctl_idx]), VIDEO_ERROR_UNKNOWN);
+        TU_VERIFY(_open_vc_itf(rhport, &_videod_itf[ctl_idx], request->wValue), VIDEO_ERROR_UNKNOWN);
+        tud_control_status(rhport, request);
+      }
+      return VIDEO_ERROR_NONE;
+
+    default: /* Unknown/Unsupported request */
+      TU_BREAKPOINT();
+      return VIDEO_ERROR_INVALID_REQUEST;
   }
 }
 
@@ -610,52 +611,63 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage,
                                    uint_fast8_t ctl_idx)
 {
   videod_interface_t *self = &_videod_itf[ctl_idx];
+
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
-  case VIDEO_VC_CTL_VIDEO_POWER_MODE:
-    switch (request->bRequest) {
-    case VIDEO_REQUEST_SET_CUR:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
-          return VIDEO_ERROR_UNKNOWN;
-      } else if (stage == CONTROL_STAGE_ACK) {
-        if (tud_video_power_mode_cb)
-          return tud_video_power_mode_cb(ctl_idx, self->power_mode);
+    case VIDEO_VC_CTL_VIDEO_POWER_MODE:
+      switch (request->bRequest) {
+        case VIDEO_REQUEST_SET_CUR:
+          if (stage == CONTROL_STAGE_SETUP) {
+            TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)), VIDEO_ERROR_UNKNOWN);
+          } else if (stage == CONTROL_STAGE_ACK) {
+            if (tud_video_power_mode_cb) return tud_video_power_mode_cb(ctl_idx, self->power_mode);
+          }
+          return VIDEO_ERROR_NONE;
+
+        case VIDEO_REQUEST_GET_CUR:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        case VIDEO_REQUEST_GET_INFO:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        default: break;
       }
-      return VIDEO_ERROR_NONE;
-    case VIDEO_REQUEST_GET_CUR:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-      if (!tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)))
-        return VIDEO_ERROR_UNKNOWN;
-      return VIDEO_ERROR_NONE;
-    case VIDEO_REQUEST_GET_INFO:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-      if (!tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
-        return VIDEO_ERROR_UNKNOWN;
-      return VIDEO_ERROR_NONE;
+      break;
+
+    case VIDEO_VC_CTL_REQUEST_ERROR_CODE:
+      switch (request->bRequest) {
+        case VIDEO_REQUEST_GET_CUR:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        case VIDEO_REQUEST_GET_INFO:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        default: break;
+      }
+      break;
+
     default: break;
-    }
-    break;
-  case VIDEO_VC_CTL_REQUEST_ERROR_CODE:
-    switch (request->bRequest) {
-    case VIDEO_REQUEST_GET_CUR:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)))
-        return VIDEO_ERROR_UNKNOWN;
-      return VIDEO_ERROR_NONE;
-    case VIDEO_REQUEST_GET_INFO:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)))
-        return VIDEO_ERROR_UNKNOWN;
-      return VIDEO_ERROR_NONE;
-    default: break;
-    }
-    break;
-  default: break;
   }
+
   /* Unknown/Unsupported request */
   TU_BREAKPOINT();
   return VIDEO_ERROR_INVALID_REQUEST;
@@ -667,19 +679,20 @@ static int handle_video_ctl_req(uint8_t rhport, uint8_t stage,
 {
   uint_fast8_t entity_id;
   switch (request->bmRequestType_bit.type) {
-  case TUSB_REQ_TYPE_STANDARD:
-    return handle_video_ctl_std_req(rhport, stage, request, ctl_idx);
-  case TUSB_REQ_TYPE_CLASS:
-    entity_id = TU_U16_HIGH(request->wIndex);
-    if (!entity_id) {
-      return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx);
-    } else {
-      if (!_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id))
-        return VIDEO_ERROR_INVALID_REQUEST;
+    case TUSB_REQ_TYPE_STANDARD:
+      return handle_video_ctl_std_req(rhport, stage, request, ctl_idx);
+
+    case TUSB_REQ_TYPE_CLASS:
+      entity_id = TU_U16_HIGH(request->wIndex);
+      if (!entity_id) {
+        return handle_video_ctl_cs_req(rhport, stage, request, ctl_idx);
+      } else {
+        TU_VERIFY(_find_desc_entity(_get_desc_vc(&_videod_itf[ctl_idx]), entity_id), VIDEO_ERROR_INVALID_REQUEST);
+        return VIDEO_ERROR_NONE;
+      }
+
+    default:
       return VIDEO_ERROR_INVALID_REQUEST;
-    }
-  default:
-    return VIDEO_ERROR_INVALID_REQUEST;
   }
 }
 
@@ -689,25 +702,27 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage,
 {
   videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx];
   switch (request->bRequest) {
-  case TUSB_REQ_GET_INTERFACE:
-    if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-    TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-    tusb_desc_vs_itf_t const *vs = _get_desc_vs(self);
-    if (!vs) return VIDEO_ERROR_UNKNOWN;
-    if (tud_control_xfer(rhport, request,
-                         (void*)&vs->std.bAlternateSetting,
-                         sizeof(vs->std.bAlternateSetting)))
+    case TUSB_REQ_GET_INTERFACE:
+      if (stage == CONTROL_STAGE_SETUP)
+      {
+        TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
+        tusb_desc_vs_itf_t const *vs = _get_desc_vs(self);
+        TU_VERIFY(vs, VIDEO_ERROR_UNKNOWN);
+        TU_VERIFY(tud_control_xfer(rhport, request, (void*)&vs->std.bAlternateSetting, sizeof(vs->std.bAlternateSetting)), VIDEO_ERROR_UNKNOWN);
+      }
       return VIDEO_ERROR_NONE;
-    return VIDEO_ERROR_UNKNOWN;
-  case TUSB_REQ_SET_INTERFACE:
-    if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-    if (!_open_vs_itf(rhport, self, request->wValue))
-      return VIDEO_ERROR_UNKNOWN;
-    tud_control_status(rhport, request);
-    return VIDEO_ERROR_NONE;
-  default: /* Unknown/Unsupported request */
-    TU_BREAKPOINT();
-    return VIDEO_ERROR_INVALID_REQUEST;
+
+    case TUSB_REQ_SET_INTERFACE:
+      if (stage == CONTROL_STAGE_SETUP)
+      {
+        TU_VERIFY(_open_vs_itf(rhport, self, request->wValue), VIDEO_ERROR_UNKNOWN);
+        tud_control_status(rhport, request);
+      }
+      return VIDEO_ERROR_NONE;
+
+    default: /* Unknown/Unsupported request */
+      TU_BREAKPOINT();
+      return VIDEO_ERROR_INVALID_REQUEST;
   }
 }
 
@@ -717,121 +732,136 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
 {
   (void)rhport;
   videod_streaming_interface_t *self = &_videod_streaming_itf[stm_idx];
+
   /* 4.2.1 Interface Control Request */
   switch (TU_U16_HIGH(request->wValue)) {
-  case VIDEO_VS_CTL_STREAM_ERROR_CODE:
-    switch (request->bRequest) {
-    case VIDEO_REQUEST_GET_CUR:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
+    case VIDEO_VS_CTL_STREAM_ERROR_CODE:
+      switch (request->bRequest) {
+        case VIDEO_REQUEST_GET_CUR:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            /* TODO */
+            TU_VERIFY(tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        case VIDEO_REQUEST_GET_INFO:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        default: break;
+      }
+      break;
+
+    case VIDEO_VS_CTL_PROBE:
+      switch (request->bRequest) {
+        case VIDEO_REQUEST_SET_CUR:
+          if (stage == CONTROL_STAGE_SETUP) {
+            TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)),
+                      VIDEO_ERROR_UNKNOWN);
+          } else if (stage == CONTROL_STAGE_ACK) {
+            TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf),
+                      VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+          }
+          return VIDEO_ERROR_NONE;
+
+        case VIDEO_REQUEST_GET_CUR:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        case VIDEO_REQUEST_GET_MIN:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
+
+            video_probe_and_commit_control_t tmp;
+            tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
+            TU_VERIFY(_negotiate_streaming_parameters(self, false, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            TU_VERIFY(tud_control_xfer(rhport, request, &tmp, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        case VIDEO_REQUEST_GET_MAX:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
+            video_probe_and_commit_control_t tmp;
+            tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
+            TU_VERIFY(_negotiate_streaming_parameters(self, true, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        case VIDEO_REQUEST_GET_RES: return VIDEO_ERROR_UNKNOWN;
+        case VIDEO_REQUEST_GET_DEF: return VIDEO_ERROR_UNKNOWN;
+        case VIDEO_REQUEST_GET_LEN: return VIDEO_ERROR_UNKNOWN;
+
+        case VIDEO_REQUEST_GET_INFO:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        default: break;
+      }
+      break;
+
+    case VIDEO_VS_CTL_COMMIT:
+      switch (request->bRequest) {
+        case VIDEO_REQUEST_SET_CUR:
+          if (stage == CONTROL_STAGE_SETUP) {
+            TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+          } else if (stage == CONTROL_STAGE_ACK) {
+            TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            if (tud_video_commit_cb) {
+              return tud_video_commit_cb(self->index_vc, self->index_vs, (video_probe_and_commit_control_t*)self->ep_buf);
+            }
+          }
+          return VIDEO_ERROR_NONE;
+
+        case VIDEO_REQUEST_GET_CUR:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        case VIDEO_REQUEST_GET_INFO:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
+        default: break;
+      }
+      break;
+
+    case VIDEO_VS_CTL_STILL_PROBE:
+    case VIDEO_VS_CTL_STILL_COMMIT:
+    case VIDEO_VS_CTL_STILL_IMAGE_TRIGGER:
+    case VIDEO_VS_CTL_GENERATE_KEY_FRAME:
+    case VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT:
+    case VIDEO_VS_CTL_SYNCH_DELAY_CONTROL:
       /* TODO */
-      if (!tud_control_xfer(rhport, request, &self->error_code, sizeof(uint8_t)))
-        return VIDEO_ERROR_UNKNOWN;
-      return VIDEO_ERROR_NONE;
-    case VIDEO_REQUEST_GET_INFO:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)))
-        return VIDEO_ERROR_UNKNOWN;
-      return VIDEO_ERROR_NONE;
+      break;
+
     default: break;
-    }
-    break;
-  case VIDEO_VS_CTL_PROBE:
-    switch (request->bRequest) {
-    case VIDEO_REQUEST_SET_CUR:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
-          return VIDEO_ERROR_UNKNOWN;
-      } else if (stage == CONTROL_STAGE_ACK) {
-        if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf))
-          return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE;
-      }
-      return VIDEO_ERROR_NONE;
-    case VIDEO_REQUEST_GET_CUR:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-      if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
-        return VIDEO_ERROR_NONE;
-      return VIDEO_ERROR_UNKNOWN;
-    case VIDEO_REQUEST_GET_MIN: {
-      video_probe_and_commit_control_t tmp;
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-      tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
-      if (!_negotiate_streaming_parameters(self, false, &tmp))
-        return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE;
-      if (tud_control_xfer(rhport, request, &tmp,
-                           sizeof(video_probe_and_commit_control_t)))
-        return VIDEO_ERROR_NONE;
-      return VIDEO_ERROR_UNKNOWN;
-    }
-    case VIDEO_REQUEST_GET_MAX: {
-      video_probe_and_commit_control_t tmp;
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-      tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
-      if (!_negotiate_streaming_parameters(self, true, &tmp))
-        return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE;
-      if (tud_control_xfer(rhport, request, self->ep_buf,
-                           sizeof(video_probe_and_commit_control_t)))
-        return VIDEO_ERROR_NONE;
-      return VIDEO_ERROR_UNKNOWN;
-    }
-    case VIDEO_REQUEST_GET_RES:
-      return VIDEO_ERROR_UNKNOWN;
-    case VIDEO_REQUEST_GET_DEF:
-      return VIDEO_ERROR_UNKNOWN;
-    case VIDEO_REQUEST_GET_LEN:
-      return VIDEO_ERROR_UNKNOWN;
-    case VIDEO_REQUEST_GET_INFO:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-      if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
-        return VIDEO_ERROR_NONE;
-      return VIDEO_ERROR_UNKNOWN;
-    default: break;
-    }
-    break;
-  case VIDEO_VS_CTL_COMMIT:
-    switch (request->bRequest) {
-    case VIDEO_REQUEST_SET_CUR:
-      if (stage == CONTROL_STAGE_SETUP) {
-        TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
-        if (!tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
-          return VIDEO_ERROR_UNKNOWN;
-      } else if (stage == CONTROL_STAGE_ACK) {
-        if (!_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf))
-          return VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE;
-        if (tud_video_commit_cb)
-          return tud_video_commit_cb(self->index_vc, self->index_vs,
-                                     (video_probe_and_commit_control_t*)self->ep_buf);
-      }
-      return VIDEO_ERROR_NONE;
-    case VIDEO_REQUEST_GET_CUR:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-      if (tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)))
-        return VIDEO_ERROR_NONE;
-      return VIDEO_ERROR_UNKNOWN;
-    case VIDEO_REQUEST_GET_INFO:
-      if (stage != CONTROL_STAGE_SETUP) return VIDEO_ERROR_NONE;
-      TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-      if (tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)))
-        return VIDEO_ERROR_NONE;
-      return VIDEO_ERROR_UNKNOWN;
-    default: break;
-    }
-    break;
-  case VIDEO_VS_CTL_STILL_PROBE:
-  case VIDEO_VS_CTL_STILL_COMMIT:
-  case VIDEO_VS_CTL_STILL_IMAGE_TRIGGER:
-  case VIDEO_VS_CTL_GENERATE_KEY_FRAME:
-  case VIDEO_VS_CTL_UPDATE_FRAME_SEGMENT:
-  case VIDEO_VS_CTL_SYNCH_DELAY_CONTROL:
-    /* TODO */
-    break;
-  default: break;
   }
+
   /* Unknown/Unsupported request */
   TU_BREAKPOINT();
   return VIDEO_ERROR_INVALID_REQUEST;
@@ -842,14 +872,14 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage,
                                 uint_fast8_t stm_idx)
 {
   switch (request->bmRequestType_bit.type) {
-  case TUSB_REQ_TYPE_STANDARD:
-    return handle_video_stm_std_req(rhport, stage, request, stm_idx);
-  case TUSB_REQ_TYPE_CLASS:
-    if (TU_U16_HIGH(request->wIndex))
-      return VIDEO_ERROR_INVALID_REQUEST;
-    return handle_video_stm_cs_req(rhport, stage, request, stm_idx);
-  default:
-    return VIDEO_ERROR_INVALID_REQUEST;
+    case TUSB_REQ_TYPE_STANDARD:
+      return handle_video_stm_std_req(rhport, stage, request, stm_idx);
+
+    case TUSB_REQ_TYPE_CLASS:
+      if (TU_U16_HIGH(request->wIndex)) return VIDEO_ERROR_INVALID_REQUEST;
+      return handle_video_stm_cs_req(rhport, stage, request, stm_idx);
+
+    default: return VIDEO_ERROR_INVALID_REQUEST;
   }
   return VIDEO_ERROR_UNKNOWN;
 }
@@ -862,8 +892,7 @@ bool tud_video_n_connected(uint_fast8_t ctl_idx)
 {
   TU_ASSERT(ctl_idx < CFG_TUD_VIDEO);
   videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, 0);
-  if (stm)
-    return true;
+  if (stm) return true;
   return false;
 }
 
@@ -872,8 +901,7 @@ bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
   TU_ASSERT(ctl_idx < CFG_TUD_VIDEO);
   TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING);
   videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx);
-  if (!stm || !stm->desc.ep[0])
-    return false;
+  if (!stm || !stm->desc.ep[0]) return false;
   return true;
 }
 
@@ -881,11 +909,9 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
 {
   TU_ASSERT(ctl_idx < CFG_TUD_VIDEO);
   TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING);
-  if (!buffer || !buffer)
-    return false;
+  if (!buffer || !buffer) return false;
   videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx);
-  if (!stm || !stm->desc.ep[0] || stm->buffer)
-    return false;
+  if (!stm || !stm->desc.ep[0] || stm->buffer) return false;
 
   /* Find EP address */
   void const *desc = _videod_itf[stm->index_vc].beg;
@@ -896,8 +922,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
     ep_addr = _desc_ep_addr(desc + ofs_ep);
     break;
   }
-  if (!ep_addr)
-    return false;
+  if (!ep_addr) return false;
 
   TU_VERIFY( usbd_edpt_claim(0, ep_addr));
   /* update the packet header */
@@ -950,8 +975,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   videod_interface_t *self = NULL;
   uint_fast8_t ctl_idx;
   for (ctl_idx = 0; ctl_idx < CFG_TUD_VIDEO; ++ctl_idx) {
-    if (_videod_itf[ctl_idx].beg)
-      continue;
+    if (_videod_itf[ctl_idx].beg) continue;
     self = &_videod_itf[ctl_idx];
     break;
   }
@@ -961,8 +985,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   self->beg = itf_desc;
   self->len = max_len;
   /*------------- Video Control Interface -------------*/
-  if (!_open_vc_itf(rhport, self, 0))
-    return 0;
+  TU_VERIFY(_open_vc_itf(rhport, self, 0), 0);
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
   uint_fast8_t bInCollection   = vc->ctl.bInCollection;
   /* Find the end of the video interface descriptor */
@@ -971,8 +994,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
     videod_streaming_interface_t *stm = NULL;
     /* find free streaming interface handle */
     for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
-      if (_videod_streaming_itf[i].desc.beg)
-        continue;
+      if (_videod_streaming_itf[i].desc.beg) continue;
       stm = &_videod_streaming_itf[i];
       self->stm[stm_idx] = i;
       break;
@@ -994,9 +1016,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
 {
   int err;
-  if (request->bmRequestType_bit.recipient != TUSB_REQ_RCPT_INTERFACE) {
-    return false;
-  }
+  TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
   uint_fast8_t itfnum = tu_u16_low(request->wIndex);
 
   /* Identify which control interface to use */
@@ -1004,9 +1024,9 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
     void const *desc = _videod_itf[itf].beg;
     if (!desc) continue;
-    if (itfnum == _desc_itfnum(desc))
-      break;
+    if (itfnum == _desc_itfnum(desc)) break;
   }
+
   if (itf < CFG_TUD_VIDEO) {
     err = handle_video_ctl_req(rhport, stage, request, itf);
     _videod_itf[itf].error_code = (uint8_t)err;
@@ -1019,9 +1039,9 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
     videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
     if (!stm->desc.beg) continue;
     void const *desc = _videod_itf[stm->index_vc].beg;
-    if (itfnum == _desc_itfnum(desc + stm->desc.beg))
-      break;
+    if (itfnum == _desc_itfnum(desc + stm->desc.beg)) break;
   }
+
   if (itf < CFG_TUD_VIDEO_STREAMING) {
     err = handle_video_stm_req(rhport, stage, request, itf);
     _videod_streaming_itf[itf].error_code = (uint8_t)err;
@@ -1045,9 +1065,9 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     if (!ep_ofs) continue;
     ctl = &_videod_itf[stm->index_vc];
     void const *desc = ctl->beg;
-    if (ep_addr == _desc_ep_addr(desc + ep_ofs))
-      break;
+    if (ep_addr == _desc_ep_addr(desc + ep_ofs)) break;
   }
+
   TU_ASSERT(itf < CFG_TUD_VIDEO_STREAMING);
   if (stm->offset < stm->bufsize) {
     /* Claim the endpoint */
@@ -1058,8 +1078,9 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     stm->buffer  = NULL;
     stm->bufsize = 0;
     stm->offset  = 0;
-    if (tud_video_frame_xfer_complete_cb)
+    if (tud_video_frame_xfer_complete_cb) {
       tud_video_frame_xfer_complete_cb(stm->index_vc, stm->index_vs);
+    }
   }
   return true;
 }

From 4d9e44e09c768cad57a9bd63bc8c33034a622bf1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 12 Oct 2021 01:12:26 +0700
Subject: [PATCH 0555/2085] more rename

---
 src/class/video/video.h        | 76 +++++++++++++++++-----------------
 src/class/video/video_device.c |  8 ++--
 2 files changed, 42 insertions(+), 42 deletions(-)

diff --git a/src/class/video/video.h b/src/class/video/video.h
index 8288e4961..b24eb0bcc 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -91,39 +91,39 @@ typedef enum {
 
 /* A.5 Class-Specific VideoControl Interface Descriptor Subtypes */
 typedef enum {
-  VIDEO_CS_VC_UNDEFINED = 0x00,
-  VIDEO_CS_VC_HEADER,
-  VIDEO_CS_VC_INPUT_TERMINAL,
-  VIDEO_CS_VC_OUTPUT_TERMINAL,
-  VIDEO_CS_VC_SELECTOR_UNIT,
-  VIDEO_CS_VC_PROCESSING_UNIT,
-  VIDEO_CS_VC_EXTENSION_UNIT,
-  VIDEO_CS_VC_ENCODING_UNIT,
-  VIDEO_CS_VC_MAX,
+  VIDEO_CS_ITF_VC_UNDEFINED = 0x00,
+  VIDEO_CS_ITF_VC_HEADER,
+  VIDEO_CS_ITF_VC_INPUT_TERMINAL,
+  VIDEO_CS_ITF_VC_OUTPUT_TERMINAL,
+  VIDEO_CS_ITF_VC_SELECTOR_UNIT,
+  VIDEO_CS_ITF_VC_PROCESSING_UNIT,
+  VIDEO_CS_ITF_VC_EXTENSION_UNIT,
+  VIDEO_CS_ITF_VC_ENCODING_UNIT,
+  VIDEO_CS_ITF_VC_MAX,
 } video_cs_vc_interface_subtype_t;
 
 /* A.6 Class-Specific VideoStreaming Interface Descriptor Subtypes */
 typedef enum {
-  VIDEO_CS_VS_UNDEFINED             = 0x00,
-  VIDEO_CS_VS_INPUT_HEADER          = 0x01,
-  VIDEO_CS_VS_OUTPUT_HEADER         = 0x02,
-  VIDEO_CS_VS_STILL_IMAGE_FRAME     = 0x03,
-  VIDEO_CS_VS_FORMAT_UNCOMPRESSED   = 0x04,
-  VIDEO_CS_VS_FRAME_UNCOMPRESSED    = 0x05,
-  VIDEO_CS_VS_FORMAT_MJPEG          = 0x06,
-  VIDEO_CS_VS_FRAME_MJPEG           = 0x07,
-  VIDEO_CS_VS_FORMAT_MPEG2TS        = 0x0A,
-  VIDEO_CS_VS_FORMAT_DV             = 0x0C,
-  VIDEO_CS_VS_COLORFORMAT           = 0x0D,
-  VIDEO_CS_VS_FORMAT_FRAME_BASED    = 0x10,
-  VIDEO_CS_VS_FRAME_FRAME_BASED     = 0x11,
-  VIDEO_CS_VS_FORMAT_STREAM_BASED   = 0x12,
-  VIDEO_CS_VS_FORMAT_H264           = 0x13,
-  VIDEO_CS_VS_FRAME_H264            = 0x14,
-  VIDEO_CS_VS_FORMAT_H264_SIMULCAST = 0x15,
-  VIDEO_CS_VS_FORMAT_VP8            = 0x16,
-  VIDEO_CS_VS_FRAME_VP8             = 0x17,
-  VIDEO_CS_VS_FORMAT_VP8_SIMULCAST  = 0x18,
+  VIDEO_CS_ITF_VS_UNDEFINED             = 0x00,
+  VIDEO_CS_ITF_VS_INPUT_HEADER          = 0x01,
+  VIDEO_CS_ITF_VS_OUTPUT_HEADER         = 0x02,
+  VIDEO_CS_ITF_VS_STILL_IMAGE_FRAME     = 0x03,
+  VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED   = 0x04,
+  VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED    = 0x05,
+  VIDEO_CS_ITF_VS_FORMAT_MJPEG          = 0x06,
+  VIDEO_CS_ITF_VS_FRAME_MJPEG           = 0x07,
+  VIDEO_CS_ITF_VS_FORMAT_MPEG2TS        = 0x0A,
+  VIDEO_CS_ITF_VS_FORMAT_DV             = 0x0C,
+  VIDEO_CS_ITF_VS_COLORFORMAT           = 0x0D,
+  VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED    = 0x10,
+  VIDEO_CS_ITF_VS_FRAME_FRAME_BASED     = 0x11,
+  VIDEO_CS_ITF_VS_FORMAT_STREAM_BASED   = 0x12,
+  VIDEO_CS_ITF_VS_FORMAT_H264           = 0x13,
+  VIDEO_CS_ITF_VS_FRAME_H264            = 0x14,
+  VIDEO_CS_ITF_VS_FORMAT_H264_SIMULCAST = 0x15,
+  VIDEO_CS_ITF_VS_FORMAT_VP8            = 0x16,
+  VIDEO_CS_ITF_VS_FRAME_VP8             = 0x17,
+  VIDEO_CS_ITF_VS_FORMAT_VP8_SIMULCAST  = 0x18,
 } video_cs_vs_interface_subtype_t;
 
 /* A.7. Class-Specific Endpoint Descriptor Subtypes */
@@ -398,18 +398,18 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 
 /* 3.7.2 */
 #define TUD_VIDEO_DESC_CS_VC(_bcdUVC, _totallen, _clkfreq, ...)	\
-  TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_HEADER, \
+  TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VC_HEADER, \
   U16_TO_U8S_LE(_bcdUVC), U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VC_LEN + (TU_ARGS_NUM(__VA_ARGS__))), \
   U32_TO_U8S_LE(_clkfreq), TU_ARGS_NUM(__VA_ARGS__), __VA_ARGS__
 
 /* 3.7.2.1 */
 #define TUD_VIDEO_DESC_INPUT_TERM(_tid, _tt, _at, _stridx) \
-  TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_INPUT_TERMINAL, \
+  TUD_VIDEO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VC_INPUT_TERMINAL, \
     _tid, U16_TO_U8S_LE(_tt), _at, _stridx
 
 /* 3.7.2.2 */
 #define TUD_VIDEO_DESC_OUTPUT_TERM(_tid, _tt, _at, _srcid, _stridx) \
-  TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VC_OUTPUT_TERMINAL, \
+  TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VC_OUTPUT_TERMINAL, \
     _tid, U16_TO_U8S_LE(_tt), _at, _srcid, _stridx
 
 /* 3.9.1 */
@@ -420,14 +420,14 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 /* 3.9.2.1 */
 #define TUD_VIDEO_DESC_CS_VS_INPUT(_numfmt, _totallen, _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, ...) \
   TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \
-  VIDEO_CS_VS_INPUT_HEADER, _numfmt, \
+  VIDEO_CS_ITF_VS_INPUT_HEADER, _numfmt, \
   U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_IN_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \
   _ep, _inf, _termlnk, _sticaptmeth, _trgspt, _trgusg, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
 /* 3.9.2.2 */
 #define TUD_VIDEO_DESC_CS_VS_OUTPUT(_numfmt, _totallen, _ep, _inf, _termlnk, ...) \
   TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__)), TUSB_DESC_CS_INTERFACE, \
-  VIDEO_CS_VS_OUTPUT_HEADER, _numfmt, \
+  VIDEO_CS_ITF_VS_OUTPUT_HEADER, _numfmt, \
   U16_TO_U8S_LE((_totallen) + TUD_VIDEO_DESC_CS_VS_OUT_LEN + (_numfmt) * (TU_ARGS_NUM(__VA_ARGS__))), \
   _ep, _inf, _termlnk, (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
@@ -436,13 +436,13 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 
 #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfrmdesc, \
   _guid, _bitsperpix, _frmidx, _asrx, _asry, _interlace, _cp) \
-  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FORMAT_UNCOMPRESSED, \
+  TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED, \
   _fmtidx, _numfrmdesc, TUD_VIDEO_GUID(_guid), \
   _bitsperpix, _frmidx, _asrx,  _asry, _interlace, _cp
 
 /* Uncompressed 3.1.2 Table 3-3 */
 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \
-  TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, \
+  TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, \
   _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
   U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), 0, \
   U32_TO_U8S_LE(_minfrminterval), U32_TO_U8S_LE(_maxfrminterval), U32_TO_U8S_LE(_frmintervalstep)
@@ -450,14 +450,14 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 /* Uncompressed 3.1.2 Table 3-4 */
 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \
   TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \
-  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, \
   _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
   U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
 /* 3.9.2.6 */
 #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(_color, _trns, _mat) \
   TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN, \
-  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_COLORFORMAT, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_COLORFORMAT, \
   _color, _trns, _mat
 
 /* 3.10.1.1 */
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index da190da47..d34fe7b92 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -258,8 +258,8 @@ static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid)
   void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength;
   for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
     tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
-    if ((VIDEO_CS_VC_INPUT_TERMINAL  <= itf->bDescriptorSubtype
-         && itf->bDescriptorSubtype < VIDEO_CS_VC_MAX)
+    if ((VIDEO_CS_ITF_VC_INPUT_TERMINAL  <= itf->bDescriptorSubtype
+         && itf->bDescriptorSubtype < VIDEO_CS_ITF_VC_MAX)
         && itf->bEntityId == entityid) {
       return itf;
     }
@@ -279,14 +279,14 @@ static inline void const* _end_of_streaming_descriptor(void const *desc)
 static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum)
 {
   return (tusb_desc_cs_video_fmt_uncompressed_t const*)
-    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FORMAT_UNCOMPRESSED, fmtnum);
+    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED, fmtnum);
 }
 
 /** Find the first frame descriptor with the specified format number. */
 static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum)
 {
   return (tusb_desc_cs_video_frm_uncompressed_t const*)
-    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_FRAME_UNCOMPRESSED, frmnum);
+    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, frmnum);
 }
 
 /** Set uniquely determined values to variables that have not been set

From 67f1603833261d3d210e55c1e8a872b8d9f98a42 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Tue, 12 Oct 2021 23:35:19 +0900
Subject: [PATCH 0556/2085] Fix a typo

---
 src/class/video/video_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index d34fe7b92..91d3b2b72 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -909,7 +909,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
 {
   TU_ASSERT(ctl_idx < CFG_TUD_VIDEO);
   TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING);
-  if (!buffer || !buffer) return false;
+  if (!buffer || !bufsize) return false;
   videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx);
   if (!stm || !stm->desc.ep[0] || stm->buffer) return false;
 

From 557fa3900a78f1c378c5653d590253ea87450013 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 12 Oct 2021 21:57:34 +0700
Subject: [PATCH 0557/2085] update docs

---
 CONTRIBUTORS.rst | 17 +++++++----------
 README.rst       |  3 ++-
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index 040f40166..33ebef959 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -76,7 +76,8 @@ Notable contributors
 -----------------------------------------------
 
 -  Add new DCD port for NXP Kinetis KL25
--  Add new DCD port for Renesas RX63n with GR-CITRUS board
+-  Add new DCD port for Renesas RX family (RX600, RX700 ..) with GR-CITRUS, RX65n target board
+-  Add new class driver for USB Video Class (UVC 1.5)
 
 
 `Nathan Conrad <https://github.com/pigrew>`__
@@ -94,8 +95,7 @@ Notable contributors
 
 -  Add new DCD port for Nuvoton NUC 120, 121, 125, 126, 505
 -  Add new class driver for USBNET RNDIS, CDC-ECM
--  Add *net\_lwip\_webserver* example for demonstration of usbnet with
-   lwip
+-  Add *net\_lwip\_webserver* example for demonstration of usbnet with lwip
 -  Board support for NuTiny NUC120, NUC121s, NUC125s, NUC126V, NUC505
 -  Improve multiple cdc interfaces API & add cdc\_dual\_ports example
 
@@ -118,10 +118,8 @@ Notable contributors
 ------------------------------------------------
 
 -  Add new class driver for USB Audio Class 2.0 (UAC2)
--  Rework tu\_fifo with unmasked pointer, add DMA support, and constant
-   address support
--  Add new DCD/USBD edpt\_xfer\_fifo() API for optimizing endpoint
-   transfer
+-  Rework tu\_fifo with unmasked pointer, add DMA support, and constant address support
+-  Add new DCD/USBD edpt\_xfer\_fifo() API for optimizing endpoint transfer
 -  Add and greatly improve Isochronous transfer
 -  Add new audio examples: audio\_test and audio\_4\_channel\_mic
 
@@ -130,8 +128,7 @@ Notable contributors
 ------------------------------------------------
 
 -  Add new DCD port for SAMD21 and SAMD51
--  Add new class driver for Musical Instrument Digital Interface
-   (MIDI)
+-  Add new class driver for Musical Instrument Digital Interface (MIDI)
 -  Improve USBD control transfer, MSC, CDC class driver
 -  Board support for Metro M0 & M4 express
 -  Write the excellent porting.md documentation
@@ -178,7 +175,7 @@ Notable contributors
 
 
 `Zixun Li <https://github.com/HiFiPhile>`__
------------------------------------------------
+-------------------------------------------
 
 -  Add new DCD port for Microchip SAMx7x
 -  Add IAR compiler support
diff --git a/README.rst b/README.rst
index 52738da32..055c294f6 100644
--- a/README.rst
+++ b/README.rst
@@ -66,7 +66,8 @@ Supports multiple device configurations by dynamically changing USB descriptors,
 -  Mass Storage Class (MSC): with multiple LUNs
 -  Musical Instrument Digital Interface (MIDI)
 -  Network with RNDIS, CDC-ECM (work in progress)
--  USB Test and Measurement Class (USBTMC)
+-  Test and Measurement Class (USBTMC)
+-  Video class 1.5 (UVC): work in progress
 -  Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file.
 -  `WebUSB <https://github.com/WICG/webusb>`__ with vendor-specific class
 

From b26cc2cc4694d883cc060c03c57d201753b4c72a Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Wed, 13 Oct 2021 00:57:45 +0700
Subject: [PATCH 0558/2085] Add linkermap for size analysis (#1136)

* add NO_LTO option to make
* add linkermap submodule and linkermap target
* add linkermap to ci build
* linkermap doesn't work with esp32sx map file yet
* add note for linkermap target
---
 .github/workflows/build.yml         | 14 +++++++++++++
 .github/workflows/build_esp.yml     | 14 +++++++++++++
 .github/workflows/build_msp430.yml  | 14 +++++++++++++
 .github/workflows/build_renesas.yml | 14 +++++++++++++
 .github/workflows/build_riscv.yml   | 14 +++++++++++++
 docs/reference/getting_started.rst  | 15 +++++++++++---
 examples/rules.mk                   | 31 +++++++++++++++++++----------
 hw/bsp/esp32s2/family.mk            |  5 +----
 8 files changed, 104 insertions(+), 17 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 1ef0bf5ea..b16cf3f87 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -66,6 +66,12 @@ jobs:
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
 
+    - name: Checkout hathach/linkermap
+      uses: actions/checkout@v2
+      with:
+         repository: hathach/linkermap
+         path: linkermap
+
     - name: Checkout pico-sdk
       if: matrix.family == 'rp2040'
       run: |
@@ -95,6 +101,14 @@ jobs:
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
 
+    - name: Linker Map
+      run: |
+        pip install linkermap/
+        for ex in `ls -d examples/device/*/`; do \
+          find ${ex} -name *.map -print -quit | \
+          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        done
+
   # ---------------------------------------
   # Build all no-family (opharned) boards
   # ---------------------------------------
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 93d582361..15071b178 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -30,5 +30,19 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v2
 
+    - name: Checkout hathach/linkermap
+      uses: actions/checkout@v2
+      with:
+         repository: hathach/linkermap
+         path: linkermap
+
     - name: Build
       run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32sx.py ${{ matrix.board }}
+
+    - name: Linker Map
+      run: |
+        pip install linkermap/
+        for ex in `ls -d examples/device/*/`; do \
+          find ${ex} -maxdepth 3 -name *.map -print -quit | \
+          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        done
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index ff2ce72c9..98dc36cd9 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -26,6 +26,12 @@ jobs:
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
+    - name: Checkout hathach/linkermap
+      uses: actions/checkout@v2
+      with:
+         repository: hathach/linkermap
+         path: linkermap
+
     - name: Set Toolchain URL
       run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2
 
@@ -48,3 +54,11 @@ jobs:
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
+
+    - name: Linker Map
+      run: |
+        pip install linkermap/
+        for ex in `ls -d examples/device/*/`; do \
+          find ${ex} -name *.map -print -quit | \
+          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        done
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index ee9ba8289..6eb042d72 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -26,6 +26,12 @@ jobs:
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
+    - name: Checkout hathach/linkermap
+      uses: actions/checkout@v2
+      with:
+         repository: hathach/linkermap
+         path: linkermap
+
     - name: Set Toolchain URL
       run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run
 
@@ -49,3 +55,11 @@ jobs:
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
+
+    - name: Linker Map
+      run: |
+        pip install linkermap/
+        for ex in `ls -d examples/device/*/`; do \
+          find ${ex} -name *.map -print -quit | \
+          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        done
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 78510751c..0c7b2d154 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -27,6 +27,12 @@ jobs:
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
+    - name: Checkout hathach/linkermap
+      uses: actions/checkout@v2
+      with:
+         repository: hathach/linkermap
+         path: linkermap
+
     - name: Set Toolchain URL
       run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v10.1.0-1.1/xpack-riscv-none-embed-gcc-10.1.0-1.1-linux-x64.tar.gz
 
@@ -49,3 +55,11 @@ jobs:
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
+
+    - name: Linker Map
+      run: |
+        pip install linkermap/
+        for ex in `ls -d examples/device/*/`; do \
+          find ${ex} -name *.map -print -quit | \
+          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        done
diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index be2e1b5ea..044792993 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -89,6 +89,15 @@ A MCU can support multiple operational speed. By default, the example build syst
 
    $ make BOARD=stm32f746disco SPEED=full all
 
+Size Analysis
+~~~~~~~~~~~~~
+
+First install `linkermap tool <https://github.com/hathach/linkermap>`_ then ``linkermap`` target can be used to analyze code size. You may want to compile with ``NO_LTO=1`` since -flto merges code across .o files and make it difficult to analyze.
+
+.. code-block::
+
+   $ make BOARD=feather_nrf52840_express NO_LTO=1 all linkermap
+
 Debug
 ^^^^^
 
@@ -153,7 +162,7 @@ Some board use uf2 bootloader for drag & drop in to mass storage device, uf2 can
    $ make BOARD=feather_nrf52840_express all uf2
 
 IAR Support
------------
+^^^^^^^^^^^
 
 IAR Project Connection files are provided to import TinyUSB stack into your project.
 
@@ -171,12 +180,12 @@ IAR Project Connection files are provided to import TinyUSB stack into your proj
    for example `C:\\tinyusb`
 
 Import stack only
-^^^^^^^^^^^^^^^^^
+~~~~~~~~~~~~~~~~~
 
 1. Open `Project -> Add project Connection ...`, click `OK`, choose `tinyusb\\tools\\iar_template.ipcf`.
 
 Run examples
-^^^^^^^^^^^^
+~~~~~~~~~~~~
 
 1. (Python3 is needed) Run `iar_gen.py` to generate .ipcf files of examples:
 
diff --git a/examples/rules.mk b/examples/rules.mk
index 7e494b3d8..92fa4e14d 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -5,12 +5,11 @@
 # Set all as default goal
 .DEFAULT_GOAL := all
 
-# ESP32-SX and RP2040 has its own CMake build system
-ifneq ($(FAMILY),esp32s2)
-ifneq ($(FAMILY),esp32s3)
-ifneq ($(FAMILY),rp2040)
+# ESP32-Sx and RP2040 has its own CMake build system
+ifeq (,$(findstring $(FAMILY),esp32s2 esp32s3 rp2040))
+
 # ---------------------------------------
-# GNU Make build system
+# Compiler Flags
 # ---------------------------------------
 
 # libc
@@ -44,6 +43,12 @@ INC += $(TOP)/src
 
 CFLAGS += $(addprefix -I,$(INC))
 
+# LTO makes it difficult to analyze map file for optimizing size purpose
+# We will run this option in ci
+ifeq ($(NO_LTO),1)
+CFLAGS := $(filter-out -flto,$(CFLAGS))
+endif
+
 LDFLAGS += $(CFLAGS) -Wl,-T,$(TOP)/$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections
 ifneq ($(SKIP_NANOLIB), 1)
 LDFLAGS += -specs=nosys.specs -specs=nano.specs
@@ -67,6 +72,10 @@ $(info LDFLAGS $(LDFLAGS)) $(info )
 $(info ASFLAGS $(ASFLAGS)) $(info )
 endif
 
+# ---------------------------------------
+# Rules
+# ---------------------------------------
+
 all: $(BUILD)/$(PROJECT).bin $(BUILD)/$(PROJECT).hex size
 
 uf2: $(BUILD)/$(PROJECT).uf2
@@ -126,11 +135,17 @@ $(BUILD)/obj/%_asm.o: %.S
 	@echo AS $(notdir $@)
 	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
 
+endif # GNU Make
+
 size: $(BUILD)/$(PROJECT).elf
 	-@echo ''
 	@$(SIZE) $<
 	-@echo ''
 
+# linkermap must be install previously at https://github.com/hathach/linkermap
+linkermap: $(BUILD)/$(PROJECT).elf
+	@linkermap -v $<.map
+
 .PHONY: clean
 clean:
 ifeq ($(CMDEXE),1)
@@ -139,10 +154,6 @@ else
 	$(RM) -rf $(BUILD)
 endif
 
-endif
-endif
-endif # GNU Make
-
 # ---------------------------------------
 # Flash Targets
 # ---------------------------------------
@@ -204,4 +215,4 @@ copy-artifact: $(BIN)
 # Print out the value of a make variable.
 # https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile
 print-%:
-	@echo $* = $($*)
+	@echo $* = $($*)
\ No newline at end of file
diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/esp32s2/family.mk
index fb9b21641..4b9000a6a 100644
--- a/hw/bsp/esp32s2/family.mk
+++ b/hw/bsp/esp32s2/family.mk
@@ -7,14 +7,11 @@ all:
 
 build: all
 
-clean:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) clean
-
 fullclean:
 	if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
 	if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
 
-flash bootloader-flash app-flash erase monitor dfu-flash dfu:
+clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-components size-files:
 	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
 
 uf2: $(BUILD)/$(PROJECT).uf2

From 4ab14867daf1d9df414f1175cbaac70c0d799257 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Tue, 12 Oct 2021 16:47:53 -0700
Subject: [PATCH 0559/2085] Trying to get USB init

---
 hw/bsp/raspberrypi4/family.c                  | 27 +++++-
 hw/bsp/raspberrypi4/family.mk                 |  1 +
 hw/mcu/broadcom                               |  2 +-
 src/portable/broadcom/synopsys/dcd_synopsys.c | 88 ++++++++++---------
 4 files changed, 71 insertions(+), 47 deletions(-)

diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c
index fe7e429d6..ffeb05f9f 100644
--- a/hw/bsp/raspberrypi4/family.c
+++ b/hw/bsp/raspberrypi4/family.c
@@ -27,14 +27,17 @@
 #include "bsp/board.h"
 #include "board.h"
 
+#include "broadcom/interrupts.h"
 #include "broadcom/io.h"
 #include "broadcom/mmu.h"
 #include "broadcom/vcmailbox.h"
 
+uint32_t SystemCoreClock = 700 * 1000 * 1000;
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
+void USB_IRQHandler(void)
 {
   tud_int_handler(0);
 }
@@ -54,6 +57,9 @@ void print(const char* str) {
 void board_init(void)
 {
   gpio_initOutputPinWithPullNone(18);
+  gpio_initOutputPinWithPullNone(19);
+  gpio_initOutputPinWithPullNone(20);
+  gpio_initOutputPinWithPullNone(21);
   gpio_setPinOutputBool(18, true);
   gpio_initOutputPinWithPullNone(42);
   setup_mmu_flat_map();
@@ -72,11 +78,17 @@ void board_init(void)
     }
     gpio_setPinOutputBool(42, true);
     gpio_setPinOutputBool(18, true);
+    gpio_setPinOutputBool(19, true);
+    gpio_setPinOutputBool(20, true);
+    gpio_setPinOutputBool(21, true);
     for (size_t j = 0; j < 1000000; j++) {
       __asm__("nop");
     }
     gpio_setPinOutputBool(42, false);
     gpio_setPinOutputBool(18, false);
+    gpio_setPinOutputBool(19, false);
+    gpio_setPinOutputBool(20, false);
+    gpio_setPinOutputBool(21, false);
   }
   // uart_writeText("hello from io\n");
   // gpio_setPinOutputBool(24, true);
@@ -98,11 +110,18 @@ void board_init(void)
   // }
   // while (1) uart_update();
 
+  printf("hello %d\r\n", 21);
+
   // Turn on USB peripheral.
   print("Turning on USB power\r\n");
 
   vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true);
   print("USB power on\r\n");
+
+  BP_SetPriority(USB_IRQn, 0x00);
+  BP_ClearPendingIRQ(USB_IRQn);
+  BP_EnableIRQ(USB_IRQn);
+  BP_EnableIRQs();
 }
 
 void board_led_write(bool state)
@@ -125,10 +144,12 @@ int board_uart_write(void const * buf, int len)
 {
   for (int i = 0; i < len; i++) {
     const char* cbuf = buf;
+    while (!UART1->STAT_b.TX_READY) {}
     if (cbuf[i] == '\n') {
-      uart_writeByteBlockingActual('\r');
+      UART1->IO = '\r';
+      while (!UART1->STAT_b.TX_READY) {}
     }
-    uart_writeByteBlockingActual(cbuf[i]);
+    UART1->IO = cbuf[i];
   }
   return len;
 }
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
index b36a83b48..0424b2154 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -18,6 +18,7 @@ CFLAGS += \
 
 SRC_C += \
 	src/portable/broadcom/synopsys/dcd_synopsys.c \
+	$(MCU_DIR)/broadcom/gen/interrupt_handlers.c \
 	$(MCU_DIR)/broadcom/interrupts.c \
 	$(MCU_DIR)/broadcom/io.c \
 	$(MCU_DIR)/broadcom/mmu.c \
diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom
index c24e8f689..e5343acda 160000
--- a/hw/mcu/broadcom
+++ b/hw/mcu/broadcom
@@ -1 +1 @@
-Subproject commit c24e8f6898d7cf8e2884eb70dbabd97480526450
+Subproject commit e5343acdad77b8cf4a8d09b732a11ecef17d148a
diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c
index aecae503c..ff4ab9fb6 100644
--- a/src/portable/broadcom/synopsys/dcd_synopsys.c
+++ b/src/portable/broadcom/synopsys/dcd_synopsys.c
@@ -434,60 +434,63 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
+
+static void reset_core(USB_OTG_GlobalTypeDef * usb_otg) {
+  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0) {}
+
+  TU_LOG(2, "    resetting\r\n");
+  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+  TU_LOG(2, "    waiting\r\n");
+  while ((usb_otg->GRSTCTL & (USB_OTG_GRSTCTL_AHBIDL | USB_OTG_GRSTCTL_CSRST)) != USB_OTG_GRSTCTL_AHBIDL) {}
+  TU_LOG(2, "    reset done\r\n");
+}
+
 void dcd_init (uint8_t rhport)
 {
+  printf("test done\r\n");
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
-  TU_LOG(2, "    dcd_init");
+  TU_LOG(2, "    dcd_init\r\n");
+
+  TU_LOG2("Test 123\r\n");
 
   USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
 
-  // No HNP/SRP (no OTG support), program timeout later.
-  if ( rhport == 1 )
-  {
-    // On selected MCUs HS port1 can be used with external PHY via ULPI interface
-#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
-    // deactivate internal PHY
-    usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
 
-    // Init The UTMI Interface
-    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+  // ReadBackReg(&Core->Usb);
+  // Core->Usb.UlpiDriveExternalVbus = 0;
+  // Core->Usb.TsDlinePulseEnable = 0;
+  // WriteThroughReg(&Core->Usb);
 
-    // Select default internal VBUS Indicator and Drive for ULPI
-    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
-#else
-    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-#endif
+  // This sequence is modeled after: https://github.com/Chadderz121/csud/blob/e13b9355d043a9cdd384b335060f1bc0416df61e/source/hcd/dwc/designware20.c#L689
+  usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIEVBUSD);
+  reset_core(usb_otg);
 
-#if defined(USB_HS_PHYC)
-    // Highspeed with embedded UTMI PHYC
+  //   Core->Usb.ModeSelect = UTMI;
+  //   LOG_DEBUG("HCD: Interface: UTMI+.\n");
+  //   Core->Usb.PhyInterface = false;
 
-    // Select UTMI Interface
-    usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
-    usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
+  //   HcdReset();  
+  TU_LOG2("init phy\r\n");
+  usb_otg->GUSBCFG |= (1 << 4); // bit four sets UTMI+ mode
+  usb_otg->GUSBCFG &= ~(1 << 3); // bit three disables phy interface
+  reset_core(usb_otg);
 
-    // Enables control of a High Speed USB PHY
-    USB_HS_PHYCInit();
-#endif
-  } else
-  {
-    // Enable internal PHY
-    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-  }
+  //   LOG_DEBUG("HCD: ULPI FSLS configuration: disabled.\n");
+  //   Core->Usb.UlpiFsls = false;
+  //   Core->Usb.ulpi_clk_sus_m = false;
+  usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_ULPICSM);
 
-  // Reset core after selecting PHY
-  // Wait AHB IDLE, reset then wait until it is cleared
-  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
-
-  TU_LOG(2, "    resetting");
-  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-  TU_LOG(2, "    waiting");
-  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
-
-  TU_LOG(2, "    reset done");
-
-  // Restart PHY clock
-  *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
+  // LOG_DEBUG("HCD: DMA configuration: enabled.\n");
+  // Core->Ahb.DmaEnable = true;
+  // Core->Ahb.DmaRemainderMode = Incremental;
+  usb_otg->GAHBCFG &= ~(1 << 23); // Remainder mode
+  usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
+  
+  //   LOG_DEBUG("HCD: HNP/SRP configuration: HNP, SRP.\n");
+  //   Core->Usb.HnpCapable = true;
+  //   Core->Usb.SrpCapable = true;
+  usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_SRPCAP | USB_OTG_GUSBCFG_HNPCAP;
 
   // Clear all interrupts
   usb_otg->GINTSTS |= usb_otg->GINTSTS;
@@ -509,8 +512,7 @@ void dcd_init (uint8_t rhport)
   set_speed(rhport, TUSB_SPEED_FULL);
   #endif
 
-  // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+  usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
 
   usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST   | USB_OTG_GINTMSK_ENUMDNEM |
       USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM     |

From 5cfe2930012d1dbec85e0923e0eda2d9aec867e6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 13 Oct 2021 17:31:57 +0700
Subject: [PATCH 0560/2085] update changelog and increase version for 0.12.0

---
 CONTRIBUTORS.rst                   |  3 +--
 docs/info/changelog.rst            | 33 +++++++++++++++++++++++++++++-
 docs/reference/getting_started.rst |  2 +-
 src/tusb_option.h                  |  2 +-
 4 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index 121d37789..55a291222 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -177,8 +177,7 @@ Notable contributors
 -  Add new DCD port for Synopsys DesignWare for STM32 L4, F2, F4,
    F7, H7 etc ...
 -  Add new DCD port for TI MSP430
--  Board support for STM32F407 Discovery, STM32H743 Nucleo, pyboard
-   v1.1, msp\_exp430f5529lp etc ...
+-  Board support for STM32F407 Discovery, STM32H743 Nucleo, pyboard v1.1, msp\_exp430f5529lp etc ...
 
 
 `Zixun Li <https://github.com/HiFiPhile>`__
diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index 4325ff2ca..4cb30799c 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -2,6 +2,37 @@
 Changelog
 *********
 
+0.12.0
+======
+
+- add CFG_TUSB_OS_INC_PATH for os include path
+
+Device Controller Driver (DCD)
+------------------------------
+
+- Getting device stack to pass USB Compliance Verification test (chapter9, HID, MSC). Ports are tested:
+  nRF, SAMD 21/51, rp2040, stm32f4, Renesas RX, iMXRT, ESP32-S2/3, Kinetic KL25/32
+- Added dcd_edpt_close_all() for switching configuration
+- [Transdimension] Support dcd_edpt_xfer_fifo() with auto wrap over if fifo buffer is 4K aligned and size is multiple of 4K.
+- [Da146xx] Improve vbus, reset, suspend, resume detection, and remote wakeup.
+
+Device Stack
+------------
+
+- Add new network driver Network Control Model (CDC-NCM), update net_lwip_webserver to work with NCM (need re-configure example)
+- Add new USB Video Class UVC 1.5 driver and video_capture example ((work in progress)
+- Fix potential buffer overflow for HID, bluetooth drivers
+
+Host Controller Driver (HCD)
+----------------------------
+
+No notable changes
+
+Host Stack
+----------
+
+No notable changes
+
 0.11.0 (2021-08-29)
 ===================
 
@@ -26,7 +57,7 @@ Synopsys
 ^^^^^^^^
 
 - Fix Synopsys set address bug which could cause re-enumeration failed
-- Fix for dcd_synopsys driver integer overflow in HS mode (issue #968)
+- Fix dcd_synopsys driver integer overflow in HS mode (issue #968)
 
 nRF5x
 ^^^^^
diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index 044792993..875372c81 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -122,7 +122,7 @@ Logger
 By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols: 
 
 
-* `LOGGER=rtt`: use [Segger RTT protocol](https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/)   
+* `LOGGER=rtt`: use `Segger RTT protocol <https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/>`_
 
   * Cons: requires jlink as the debugger.
   * Pros: work with most if not all MCUs
diff --git a/src/tusb_option.h b/src/tusb_option.h
index b2ebfdf66..e49fc0119 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -28,7 +28,7 @@
 #define _TUSB_OPTION_H_
 
 #define TUSB_VERSION_MAJOR     0
-#define TUSB_VERSION_MINOR     11
+#define TUSB_VERSION_MINOR     12
 #define TUSB_VERSION_REVISION  0
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
 

From 2a795d5fd0e1a18ae5fa2eeb9d47e8769efe663c Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 14 Oct 2021 23:15:35 +0900
Subject: [PATCH 0561/2085] Fix GUID of video compression formats

---
 src/class/video/video.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/class/video/video.h b/src/class/video/video.h
index b24eb0bcc..fa2976611 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -382,10 +382,10 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN   6
 
 /* 2.2 compression formats */
-#define TUD_VIDEO_GUID_YUY2   0x59,0x55,0x59,0x32,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00
-#define TUD_VIDEO_GUID_NV12   0x4E,0x56,0x31,0x32,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00
-#define TUD_VIDEO_GUID_M420   0x4D,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00
-#define TUD_VIDEO_GUID_I420   0x49,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x00,0x80,0x71,0x9B,0x38,0x00,0xAA,0x00
+#define TUD_VIDEO_GUID_YUY2   0x59,0x55,0x59,0x32,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
+#define TUD_VIDEO_GUID_NV12   0x4E,0x56,0x31,0x32,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
+#define TUD_VIDEO_GUID_M420   0x4D,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
+#define TUD_VIDEO_GUID_I420   0x49,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
 
 #define TUD_VIDEO_DESC_IAD(_firstitfs, _nitfs, _stridx) \
   TUD_VIDEO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, \

From 7667299b483feb4afb783d794ea94a149cc5a5b4 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Thu, 14 Oct 2021 12:13:39 -0500
Subject: [PATCH 0562/2085] Remove compiler warning

---
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index f9b4d9b17..28c54c52f 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -242,7 +242,7 @@ static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
   // Update hw endpoint struct with info from hardware
   // after a buff status interrupt
 
-  uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
+  uint32_t __unused buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
   TU_LOG(3, "  Sync BufCtrl: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
 
   // always sync buffer 0

From 06d955538988c3859bf6c5428a38bd8311069ed9 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Thu, 14 Oct 2021 15:20:32 -0500
Subject: [PATCH 0563/2085] More warning cleanup  - physically suppress
 warnings in TinyUSB headers using pragmas so they don't break -Werror
 compilation of external files that include them  - fix compiler warnings in
 rp2040 port  - add cmake method to rp2040 port to allow an external project
 to suppress warnings in TinyUSB itself

---
 hw/bsp/rp2040/family.cmake                   | 25 +++++++++++++++++++-
 src/device/dcd.h                             |  7 ++++++
 src/osal/osal.h                              |  7 ++++++
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 22 ++++++++---------
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  8 +++----
 5 files changed, 53 insertions(+), 16 deletions(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 06b5e9bd6..1aa180ef8 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -77,7 +77,6 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/class/video/video_device.c
 			)
 
-
 	# Base config for host mode; wrapped by SDK's tinyusb_host
 	add_library(tinyusb_host_base INTERFACE)
 	target_sources(tinyusb_host_base INTERFACE
@@ -153,4 +152,28 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		enable_language(C CXX ASM)
 		pico_sdk_init()
 	endfunction()
+
+	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
+	function(suppress_tinyusb_warnings)
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/tusb.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/device/usbd.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-null-dereference")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/device/usbd_control.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion")
+	endfunction()
 endif()
diff --git a/src/device/dcd.h b/src/device/dcd.h
index d43a0dd9a..c042cc708 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -106,7 +106,14 @@ typedef struct TU_ATTR_ALIGNED(4)
 void dcd_init       (uint8_t rhport);
 
 // Interrupt Handler
+#if __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
 void dcd_int_handler(uint8_t rhport);
+#if __GNUC__
+#pragma GCC diagnostic pop
+#endif
 
 // Enable device interrupt
 void dcd_int_enable (uint8_t rhport);
diff --git a/src/osal/osal.h b/src/osal/osal.h
index 28bdf479c..c8131d19d 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -67,6 +67,10 @@ typedef void (*osal_task_func_t)( void * );
 // OSAL Porting API
 //--------------------------------------------------------------------+
 
+#if __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
 //------------- Semaphore -------------//
 static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
 static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
@@ -84,6 +88,9 @@ static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
 static inline bool osal_queue_receive(osal_queue_t qhdl, void* data);
 static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
 static inline bool osal_queue_empty(osal_queue_t qhdl);
+#if __GNUC__
+#pragma GCC diagnostic pop
+#endif
 
 #if 0  // TODO remove subtask related macros later
 // Sub Task
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index a710bd557..4bcc9ca54 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -70,7 +70,7 @@ static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
 static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
 {
   // size must be multiple of 64
-  uint16_t size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
+  uint size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
 
   // double buffered Bulk endpoint
   if ( transfer_type == TUSB_XFER_BULK )
@@ -88,7 +88,7 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
   pico_info("  Alloced %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf);
 
   // Fill in endpoint control register with buffer offset
-  uint32_t const reg = EP_CTRL_ENABLE_BITS | (transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
+  uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint)transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
 
   *ep->endpoint_control = reg;
 }
@@ -177,7 +177,7 @@ static void hw_handle_buff_status(void)
     uint32_t remaining_buffers = usb_hw->buf_status;
     pico_trace("buf_status = 0x%08x\n", remaining_buffers);
     uint bit = 1u;
-    for (uint i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++)
+    for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++)
     {
         if (remaining_buffers & bit)
         {
@@ -365,19 +365,19 @@ void dcd_init (uint8_t rhport)
   dcd_connect(rhport);
 }
 
-void dcd_int_enable(uint8_t rhport)
+void dcd_int_enable(__unused uint8_t rhport)
 {
     assert(rhport == 0);
     irq_set_enabled(USBCTRL_IRQ, true);
 }
 
-void dcd_int_disable(uint8_t rhport)
+void dcd_int_disable(__unused uint8_t rhport)
 {
     assert(rhport == 0);
     irq_set_enabled(USBCTRL_IRQ, false);
 }
 
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
+void dcd_set_address (__unused uint8_t rhport, __unused uint8_t dev_addr)
 {
   assert(rhport == 0);
 
@@ -386,7 +386,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
   hw_endpoint_xfer(0x80, NULL, 0);
 }
 
-void dcd_remote_wakeup(uint8_t rhport)
+void dcd_remote_wakeup(__unused uint8_t rhport)
 {
     pico_info("dcd_remote_wakeup %d\n", rhport);
     assert(rhport == 0);
@@ -394,14 +394,14 @@ void dcd_remote_wakeup(uint8_t rhport)
 }
 
 // disconnect by disabling internal pull-up resistor on D+/D-
-void dcd_disconnect(uint8_t rhport)
+void dcd_disconnect(__unused uint8_t rhport)
 {
   (void) rhport;
   usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
 }
 
 // connect by enabling internal pull-up resistor on D+/D-
-void dcd_connect(uint8_t rhport)
+void dcd_connect(__unused uint8_t rhport)
 {
   (void) rhport;
   usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
@@ -423,7 +423,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
   }
 }
 
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
+bool dcd_edpt_open (__unused uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
     assert(rhport == 0);
     hw_endpoint_init(desc_edpt->bEndpointAddress, desc_edpt->wMaxPacketSize.size, desc_edpt->bmAttributes.xfer);
@@ -438,7 +438,7 @@ void dcd_edpt_close_all (uint8_t rhport)
   reset_non_control_endpoints();
 }
 
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+bool dcd_edpt_xfer(__unused uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
     assert(rhport == 0);
     hw_endpoint_xfer(ep_addr, buffer, total_bytes);
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 28c54c52f..c9e2f6b26 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -38,7 +38,7 @@ const char *ep_dir_string[] = {
         "in",
 };
 
-static inline void _hw_endpoint_lock_update(struct hw_endpoint *ep, int delta) {
+static inline void _hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) {
     // todo add critsec as necessary to prevent issues between worker and IRQ...
     //  note that this is perhaps as simple as disabling IRQs because it would make
     //  sense to have worker and IRQ on same core, however I think using critsec is about equivalent.
@@ -107,7 +107,7 @@ void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_m
 static uint32_t prepare_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
 {
   uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
-  ep->remaining_len -= buflen;
+  ep->remaining_len = (uint16_t)(ep->remaining_len - buflen);
 
   uint32_t buf_ctrl = buflen | USB_BUF_CTRL_AVAIL;
 
@@ -214,7 +214,7 @@ static uint16_t sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
     // sent some data can increase the length we have sent
     assert(!(buf_ctrl & USB_BUF_CTRL_FULL));
 
-    ep->xferred_len += xferred_bytes;
+    ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes);
   }else
   {
     // If we have received some data, so can increase the length
@@ -222,7 +222,7 @@ static uint16_t sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
     assert(buf_ctrl & USB_BUF_CTRL_FULL);
 
     memcpy(ep->user_buf, ep->hw_data_buf + buf_id*64, xferred_bytes);
-    ep->xferred_len += xferred_bytes;
+    ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes);
     ep->user_buf += xferred_bytes;
   }
 

From 7596cb30797c625a0523e0f68ef65296740538e0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 15 Oct 2021 15:54:32 +0700
Subject: [PATCH 0564/2085] update some sense warning from -Wconversion

---
 examples/device/cdc_msc/src/msc_disk.c        | 8 ++++----
 examples/device/cdc_msc/src/usb_descriptors.c | 2 +-
 hw/bsp/board.c                                | 4 ++--
 src/class/cdc/cdc_device.c                    | 2 +-
 src/class/msc/msc_device.c                    | 2 +-
 src/tusb.c                                    | 5 ++---
 6 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index cad2602a2..134bda392 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -194,7 +194,7 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
   uint8_t const* addr = msc_disk[lba] + offset;
   memcpy(buffer, addr, bufsize);
 
-  return bufsize;
+  return (int32_t) bufsize;
 }
 
 bool tud_msc_is_writable_cb (uint8_t lun)
@@ -224,7 +224,7 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
   (void) lba; (void) offset; (void) buffer;
 #endif
 
-  return bufsize;
+  return (int32_t) bufsize;
 }
 
 // Callback invoked when received an SCSI command not in built-in list below
@@ -263,14 +263,14 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
   {
     if(in_xfer)
     {
-      memcpy(buffer, response, resplen);
+      memcpy(buffer, response, (size_t) resplen);
     }else
     {
       // SCSI output
     }
   }
 
-  return resplen;
+  return (int32_t) resplen;
 }
 
 #endif
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 34537b8f0..5e397d15a 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -261,7 +261,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 6a26f55b7..2c18b61b4 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -135,13 +135,13 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
 {
   (void) fhdl;
-  return board_uart_write(buf, count);
+  return board_uart_write(buf, (int) count);
 }
 
 TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 {
   (void) fhdl;
-  return board_uart_read((uint8_t*) buf, count);
+  return board_uart_read((uint8_t*) buf, (int) count);
 }
 
 #endif
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index e622bd616..74c116192 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -229,7 +229,7 @@ void cdcd_init(void)
   {
     cdcd_interface_t* p_cdc = &_cdcd_itf[i];
 
-    p_cdc->wanted_char = -1;
+    p_cdc->wanted_char = (char) -1;
 
     // default line coding is : stop bit = 1, parity = none, data bits = 8
     p_cdc->line_coding.bit_rate  = 115200;
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index c54c4c189..81522be46 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -152,7 +152,7 @@ static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw)
   // invalid block count
   if (block_count == 0) return 0;
 
-  return cbw->total_bytes / block_count;
+  return (uint16_t) (cbw->total_bytes / block_count);
 }
 
 uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
diff --git a/src/tusb.c b/src/tusb.c
index 5c6adad24..fc1936c3d 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -109,9 +109,9 @@ bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed)
 void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id)
 {
   uint8_t const* p_desc = (uint8_t const*) desc_itf;
-  uint16_t len = 0;
+  uint8_t const* desc_end = p_desc + desc_len;
 
-  while( len < desc_len )
+  while( p_desc < desc_end )
   {
     if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
     {
@@ -121,7 +121,6 @@ void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_
       ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id;
     }
 
-    len   += (uint16_t) tu_desc_len(p_desc);
     p_desc = tu_desc_next(p_desc);
   }
 }

From 49aa0b72a8301f21281fa6498af47ac26bcb1bea Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 15 Oct 2021 11:34:26 +0200
Subject: [PATCH 0565/2085] dcd_da146xx: Fix EPIN stall notification handling

Normal TX handler for IN non-0 endpoints is called during
outgoing transfer or just after it was finished.
It may need to fill TX fifo with same data if TX_DONE is present
but ACK_STAT is not.
It may need to fill more data when called during transfer.
But it may also be called when STALL was sent.
In this case TX_DONE is set ACK_STAT is not, just like for packets
that were sent but no ACK was received.
Code was trying to send something again. There was nothing to send
so empty ZLP was scheduled for stalled endpoint.
This ZLP was later send to host where valid response was required.

This change checks if notification was for STALL endpoint and
does not try to fill TX FIFO in that case.
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index a36165343..c4b46ac08 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -632,6 +632,13 @@ static void handle_epx_tx_ev(xfer_ctl_t *xfer)
         return;
       }
     }
+    else if (regs->epc_in & USB_USB_EPC1_REG_USB_STALL_Msk)
+    {
+      // TX_DONE also indicates that STALL packet was just sent, there is
+      // no point to put anything into transmit FIFO. It could result in
+      // empty packet being scheduled.
+      return;
+    }
   }
   if (txs & USB_USB_TXS1_REG_USB_TX_URUN_Msk)
   {

From bf4b133084585d302691e53faf868c0c37b9eaf0 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 15 Oct 2021 11:57:52 +0200
Subject: [PATCH 0566/2085] dcd_da146xx: Drop unexpected data

USB3CV tool verifies MSC device by sending too short or
too long packets.
In case of too long packets (msc_device requested 31 bytes
but incoming data had 32 bytes) extra byte(s) were left in
FIFO resulting in some data mismatch later on.

Now if more data is received in packet that expected extra
bytes are just dropped.
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index c4b46ac08..f15203ee9 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -368,8 +368,8 @@ static void start_rx_packet(xfer_ctl_t *xfer)
     else
     {
       // Other endpoint is using DMA in that direction, fall back to interrupts.
-      // For endpoint size greater then FIFO size enable FIFO level warning interrupt
-      // when FIFO has less then 17 bytes free.
+      // For endpoint size greater than FIFO size enable FIFO level warning interrupt
+      // when FIFO has less than 17 bytes free.
       regs->rxc |= USB_USB_RXC1_REG_USB_RFWL_Msk;
       USB->USB_FWMSK_REG |= 1 << (epnum - 1 + USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos);
     }
@@ -420,7 +420,7 @@ static void start_tx_packet(xfer_ctl_t *xfer)
   regs->txc |= USB_USB_TXC1_REG_USB_TX_EN_Msk;
 }
 
-static void read_rx_fifo(xfer_ctl_t *xfer, uint16_t bytes_in_fifo)
+static uint16_t read_rx_fifo(xfer_ctl_t *xfer, uint16_t bytes_in_fifo)
 {
   EPx_REGS *regs = XFER_REGS(xfer);
   uint16_t remaining = xfer->total_len - xfer->transferred - xfer->last_packet_size;
@@ -433,6 +433,8 @@ static void read_rx_fifo(xfer_ctl_t *xfer, uint16_t bytes_in_fifo)
   for (int i = 0; i < receive_this_time; ++i) buf[i] = regs->rxd;
 
   xfer->last_packet_size += receive_this_time;
+
+  return bytes_in_fifo - receive_this_time;
 }
 
 static void handle_ep0_rx(void)
@@ -562,7 +564,7 @@ static void handle_epx_rx_ev(uint8_t ep)
       // FIFO maybe empty if DMA read it before or it's final iteration and function already read all that was to read.
       if (fifo_bytes > 0)
       {
-        read_rx_fifo(xfer, fifo_bytes);
+        fifo_bytes = read_rx_fifo(xfer, fifo_bytes);
       }
       if (GET_BIT(rxs, USB_USB_RXS1_REG_USB_RX_LAST))
       {
@@ -577,6 +579,13 @@ static void handle_epx_rx_ev(uint8_t ep)
           xfer->transferred += xfer->last_packet_size;
           if (xfer->total_len == xfer->transferred || xfer->last_packet_size < xfer->max_packet_size || xfer->iso)
           {
+            if (fifo_bytes)
+            {
+              // There are extra bytes in the FIFO just flush them
+              regs->rxc |= USB_USB_RXC1_REG_USB_FLUSH_Msk;
+              fifo_bytes = 0;
+            }
+
             dcd_event_xfer_complete(0, xfer->ep_addr, xfer->transferred, XFER_RESULT_SUCCESS, true);
           }
           else

From 9a688224d0b19a7b4d33c8bb767d0486d5b1bccd Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 15 Oct 2021 13:47:49 +0200
Subject: [PATCH 0567/2085] msc examples: Extend serial number to 12 digits

USB3CV tool complains about too short serial number being used
in MSC device.

This just extends serial number to 12 characters, it makes it
easier to analyze USB3CV logs where this unnecessary warning
made output red.

Offending warning:
Serial Number string for MSC device : iSerialNumber = 0x3
Checking iSerialNumber String Descriptor: index = 0x03.
String Descriptor : "123456". (ENGLISH_US)
Using Language ID 0x409
MSC Serial Number length = 14
Invalid MSC Serial Number length : should be >= 26
*************************
Invalid MSC Serial Number length
*************************
*************************
(MSC: 5.1.2) Serial number must be a string, 12 characters or longer
(if the device supports a BOT interface, bInterfaceProtocol = 0x50),
or exactly 12 characters long (if the device supports a CBI interface,
bInterfaceProtocol = 0x00 or 0x01, and has a serial number).
---
 examples/device/cdc_msc/src/usb_descriptors.c          | 2 +-
 examples/device/cdc_msc_freertos/src/usb_descriptors.c | 2 +-
 examples/device/msc_dual_lun/src/usb_descriptors.c     | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 34537b8f0..524c5bfb4 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -232,7 +232,7 @@ char const* string_desc_arr [] =
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  "123456789012",                // 3: Serials, should use chip ID
   "TinyUSB CDC",                 // 4: CDC Interface
   "TinyUSB MSC",                 // 5: MSC Interface
 };
diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
index f3ff305f8..9585822a3 100644
--- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c
+++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
@@ -218,7 +218,7 @@ char const* string_desc_arr [] =
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  "123456789012",                // 3: Serials, should use chip ID
   "TinyUSB CDC",                 // 4: CDC Interface
   "TinyUSB MSC",                 // 5: MSC Interface
 };
diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c
index 7e194ea7a..2afd391af 100644
--- a/examples/device/msc_dual_lun/src/usb_descriptors.c
+++ b/examples/device/msc_dual_lun/src/usb_descriptors.c
@@ -141,7 +141,7 @@ char const* string_desc_arr [] =
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  "123456789012",                // 3: Serials, should use chip ID
 };
 
 static uint16_t _desc_str[32];

From 0b249618b0469529da748e3e5478751cd56acd31 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 15 Oct 2021 17:35:05 +0700
Subject: [PATCH 0568/2085] fix -Wcast-qual

---
 hw/bsp/nrf/family.mk                  | 14 +---------
 src/class/dfu/dfu_device.c            |  2 +-
 src/class/hid/hid_device.c            | 12 ++++----
 src/class/usbtmc/usbtmc_device.c      | 40 ++++++++++++---------------
 src/class/usbtmc/usbtmc_device.h      |  6 ----
 src/class/video/video_device.c        | 19 +++++++------
 src/common/tusb_common.h              |  5 ++--
 src/common/tusb_fifo.c                |  4 +--
 src/device/usbd.c                     | 39 ++++++++++++++------------
 src/portable/nordic/nrf5x/dcd_nrf5x.c |  4 +--
 10 files changed, 64 insertions(+), 81 deletions(-)

diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index d1afd2587..d8283a9e6 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -14,19 +14,7 @@ CFLAGS += \
   -DCONFIG_GPIO_AS_PINRESET
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align
-
-# due to tusb_hal_nrf_power_event
-GCCVERSION = $(firstword $(subst ., ,$(shell arm-none-eabi-gcc -dumpversion)))
-ifeq ($(CMDEXE),1)
-  ifeq ($(shell if $(GCCVERSION) geq 8 echo 1), 1)
-  CFLAGS += -Wno-error=cast-function-type
-  endif
-else
-  ifeq ($(shell expr $(GCCVERSION) \>= 8), 1)
-  CFLAGS += -Wno-error=cast-function-type
-  endif
-endif
+CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
 
 # All source paths should be relative to the top level.
 LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 28abf6e83..ddfa608e4 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -190,7 +190,7 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
   _dfu_ctx.attrs = func_desc->bAttributes;
 
   // CFG_TUD_DFU_XFER_BUFSIZE has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
-  uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16((uint8_t*) func_desc + offsetof(tusb_desc_dfu_functional_t, wTransferSize)) );
+  uint16_t const transfer_size = tu_le16toh( tu_unaligned_read16((uint8_t const*) func_desc + offsetof(tusb_desc_dfu_functional_t, wTransferSize)) );
   TU_ASSERT(transfer_size <= CFG_TUD_DFU_XFER_BUFSIZE, drv_len);
 
   return drv_len;
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 55071a5ce..588b61254 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -206,8 +206,8 @@ uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint1
 
   //------------- HID descriptor -------------//
   p_desc = tu_desc_next(p_desc);
+  TU_ASSERT(HID_DESC_TYPE_HID == tu_desc_type(p_desc), 0);
   p_hid->hid_descriptor = (tusb_hid_descriptor_hid_t const *) p_desc;
-  TU_ASSERT(HID_DESC_TYPE_HID == p_hid->hid_descriptor->bDescriptorType, 0);
 
   //------------- Endpoint Descriptor -------------//
   p_desc = tu_desc_next(p_desc);
@@ -216,10 +216,10 @@ uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint1
   if ( desc_itf->bInterfaceSubClass == HID_SUBCLASS_BOOT ) p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
 
   p_hid->protocol_mode = HID_PROTOCOL_REPORT; // Per Specs: default is report mode
-  p_hid->itf_num   = desc_itf->bInterfaceNumber;
+  p_hid->itf_num       = desc_itf->bInterfaceNumber;
 
   // Use offsetof to avoid pointer to the odd/misaligned address
-  memcpy(&p_hid->report_desc_len, (uint8_t*) p_hid->hid_descriptor + offsetof(tusb_hid_descriptor_hid_t, wReportLength), 2);
+  p_hid->report_desc_len = tu_unaligned_read16((uint8_t const*) p_hid->hid_descriptor + offsetof(tusb_hid_descriptor_hid_t, wReportLength));
 
   // Prepare for output endpoint
   if (p_hid->ep_out)
@@ -256,13 +256,13 @@ bool hidd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
 
       if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_HID)
       {
-        TU_VERIFY(p_hid->hid_descriptor != NULL);
-        TU_VERIFY(tud_control_xfer(rhport, request, (void*) p_hid->hid_descriptor, p_hid->hid_descriptor->bLength));
+        TU_VERIFY(p_hid->hid_descriptor);
+        TU_VERIFY(tud_control_xfer(rhport, request, (void*)(uintptr_t) p_hid->hid_descriptor, p_hid->hid_descriptor->bLength));
       }
       else if (request->bRequest == TUSB_REQ_GET_DESCRIPTOR && desc_type == HID_DESC_TYPE_REPORT)
       {
         uint8_t const * desc_report = tud_hid_descriptor_report_cb(hid_itf);
-        tud_control_xfer(rhport, request, (void*) desc_report, p_hid->report_desc_len);
+        tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_report, p_hid->report_desc_len);
       }
       else
       {
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index c1ee49f45..86495e3fa 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -1,10 +1,3 @@
-/*
- * usbtmc.c
- *
- *  Created on: Sep 9, 2019
- *      Author: nconrad
- */
-
 /*
  * The MIT License (MIT)
  *
@@ -205,7 +198,7 @@ bool tud_usbtmc_transmit_dev_msg_data(
   {
     TU_ASSERT(usbtmc_state.capabilities->bmDevCapabilities.canEndBulkInOnTermChar);
     TU_ASSERT(termCharRequested);
-    TU_ASSERT(((uint8_t*)data)[len-1u] == termChar);
+    TU_ASSERT(((uint8_t const*)data)[len-1u] == termChar);
   }
 #endif
 
@@ -228,7 +221,7 @@ bool tud_usbtmc_transmit_dev_msg_data(
   memcpy((uint8_t*)(usbtmc_state.ep_bulk_in_buf) + headerLen, data, dataLen);
   usbtmc_state.transfer_size_remaining = len - dataLen;
   usbtmc_state.transfer_size_sent = dataLen;
-  usbtmc_state.devInBuffer = (uint8_t*)data + (dataLen);
+  usbtmc_state.devInBuffer = (uint8_t const*) data + (dataLen);
 
   bool stateChanged =
       atomicChangeState(STATE_TX_REQUESTED, (packetLen >= txBufLen) ? STATE_TX_INITIATED : STATE_TX_SHORTED);
@@ -508,13 +501,13 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
     case STATE_ABORTING_BULK_OUT:
       TU_VERIFY(false);
       return false; // Should be stalled by now, shouldn't have received a packet.
+
     case STATE_TX_REQUESTED:
     case STATE_TX_INITIATED:
     case STATE_ABORTING_BULK_IN:
     case STATE_ABORTING_BULK_IN_SHORTED:
     case STATE_ABORTING_BULK_IN_ABORTED:
     default:
-
       TU_VERIFY(false);
     }
   }
@@ -528,16 +521,16 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
 
     case STATE_TX_INITIATED:
       if(usbtmc_state.transfer_size_remaining >=sizeof(usbtmc_state.ep_bulk_in_buf))
-    {
-        // FIXME! This removes const below!
-        TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in,
-            (void*)usbtmc_state.devInBuffer,sizeof(usbtmc_state.ep_bulk_in_buf)));
-        usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf);
-        usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf);
-        usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf);
-    }
-    else // last packet
-    {
+      {
+          // FIXME! This removes const below!
+          TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in,
+              (void*)(uintptr_t) usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf)));
+          usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf);
+          usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf);
+          usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf);
+      }
+      else // last packet
+      {
       size_t packetLen = usbtmc_state.transfer_size_remaining;
       memcpy(usbtmc_state.ep_bulk_in_buf, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining);
         usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.transfer_size_remaining);
@@ -550,15 +543,18 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
         }
       }
       return true;
+
     case STATE_ABORTING_BULK_IN:
       // need to send short packet  (ZLP?)
       TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf,(uint16_t)0u));
       usbtmc_state.state = STATE_ABORTING_BULK_IN_SHORTED;
       return true;
+
     case STATE_ABORTING_BULK_IN_SHORTED:
       /* Done. :)*/
       usbtmc_state.state = STATE_ABORTING_BULK_IN_ABORTED;
-    return true;
+      return true;
+
     default:
       TU_ASSERT(false);
       return false;
@@ -787,7 +783,7 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
     {
       TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface
       TU_VERIFY(request->wLength == sizeof(*(usbtmc_state.capabilities)));
-      TU_VERIFY(tud_control_xfer(rhport, request, (void*)usbtmc_state.capabilities, sizeof(*usbtmc_state.capabilities)));
+      TU_VERIFY(tud_control_xfer(rhport, request, (void*)(uintptr_t) usbtmc_state.capabilities, sizeof(*usbtmc_state.capabilities)));
       return true;
     }
   // USBTMC Optional Requests
diff --git a/src/class/usbtmc/usbtmc_device.h b/src/class/usbtmc/usbtmc_device.h
index 622800315..0549a1569 100644
--- a/src/class/usbtmc/usbtmc_device.h
+++ b/src/class/usbtmc/usbtmc_device.h
@@ -1,9 +1,3 @@
-/*
- * usbtmc_device.h
- *
- *  Created on: Sep 10, 2019
- *      Author: nconrad
- */
 /*
  * The MIT License (MIT)
  *
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 91d3b2b72..cc05a1e07 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -585,8 +585,9 @@ static int handle_video_ctl_std_req(uint8_t rhport, uint8_t stage,
         tusb_desc_vc_itf_t const *vc = _get_desc_vc(&_videod_itf[ctl_idx]);
         TU_VERIFY(vc, VIDEO_ERROR_UNKNOWN);
 
-        TU_VERIFY(tud_control_xfer(rhport, request, (void*)&vc->std.bAlternateSetting, sizeof(vc->std.bAlternateSetting)),
-                  VIDEO_ERROR_UNKNOWN);
+        uint8_t alt_num = vc->std.bAlternateSetting;
+
+        TU_VERIFY(tud_control_xfer(rhport, request, &alt_num, sizeof(alt_num)), VIDEO_ERROR_UNKNOWN);
       }
       return VIDEO_ERROR_NONE;
 
@@ -637,7 +638,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage,
           if (stage == CONTROL_STAGE_SETUP)
           {
             TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
@@ -657,7 +658,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage,
         case VIDEO_REQUEST_GET_INFO:
           if (stage == CONTROL_STAGE_SETUP)
           {
-            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
@@ -708,7 +709,9 @@ static int handle_video_stm_std_req(uint8_t rhport, uint8_t stage,
         TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
         tusb_desc_vs_itf_t const *vs = _get_desc_vs(self);
         TU_VERIFY(vs, VIDEO_ERROR_UNKNOWN);
-        TU_VERIFY(tud_control_xfer(rhport, request, (void*)&vs->std.bAlternateSetting, sizeof(vs->std.bAlternateSetting)), VIDEO_ERROR_UNKNOWN);
+        uint8_t alt_num = vs->std.bAlternateSetting;
+
+        TU_VERIFY(tud_control_xfer(rhport, request, &alt_num, sizeof(alt_num)), VIDEO_ERROR_UNKNOWN);
       }
       return VIDEO_ERROR_NONE;
 
@@ -748,7 +751,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
         case VIDEO_REQUEST_GET_INFO:
           if (stage == CONTROL_STAGE_SETUP)
           {
-            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get, sizeof(_cap_get)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
@@ -808,7 +811,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           if (stage == CONTROL_STAGE_SETUP)
           {
             TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
@@ -842,7 +845,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           if (stage == CONTROL_STAGE_SETUP)
           {
             TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index fc4d3bc62..8dd1dbd49 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -161,7 +161,6 @@ static inline uint8_t tu_log2(uint32_t value)
 #if TUP_ARCH_STRICT_ALIGN
 
 // Rely on compiler to generate correct code for unaligned access
-
 typedef struct { uint16_t val; } TU_ATTR_PACKED tu_unaligned_uint16_t;
 typedef struct { uint32_t val; } TU_ATTR_PACKED tu_unaligned_uint32_t;
 
@@ -227,8 +226,8 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_
 #else
 
 // MCU that could access unaligned memory natively
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32  (const void* mem           ) { return *((uint32_t*) mem);  }
-TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16  (const void* mem           ) { return *((uint16_t*) mem);  }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32  (const void* mem) { return *((uint32_t const *) mem); }
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16  (const void* mem) { return *((uint16_t const *) mem); }
 
 TU_ATTR_ALWAYS_INLINE static inline void     tu_unaligned_write32 (void* mem, uint32_t value ) { *((uint32_t*) mem) = value; }
 TU_ATTR_ALWAYS_INLINE static inline void     tu_unaligned_write16 (void* mem, uint16_t value ) { *((uint16_t*) mem) = value; }
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 11b8fc5f3..564687e02 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -102,7 +102,7 @@ static inline uint16_t _ff_mod(uint16_t idx, uint16_t depth)
 // TODO generalize with configurable 1 byte or 4 byte each read
 static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t len)
 {
-  volatile uint32_t * rx_fifo = (volatile uint32_t *) app_buf;
+  volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf;
 
   // Reading full available 32 bit words from const app address
   uint16_t full_words = len >> 2;
@@ -201,7 +201,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         ff_buf += nLin_4n_bytes;
 
         // There could be odd 1-3 bytes before the wrap-around boundary
-        volatile uint32_t * rx_fifo = (volatile uint32_t *) app_buf;
+        volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf;
         uint8_t rem = nLin_bytes & 0x03;
         if (rem > 0)
         {
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 7be41172b..b4680283f 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -990,21 +990,23 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
     {
       TU_LOG2(" Device\r\n");
 
-      uint16_t len = sizeof(tusb_desc_device_t);
+      void* desc_device = (void*) (uintptr_t) tud_descriptor_device_cb();
 
-      // Only send up to EP0 Packet Size if not addressed and host requested more data
-      // that device descriptor has.
+      // Only response with exactly 1 Packet if: not addressed and host requested more data than device descriptor has.
       // This only happens with the very first get device descriptor and EP0 size = 8 or 16.
       if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed &&
-          ((tusb_control_request_t*) p_request)->wLength > sizeof(tusb_desc_device_t))
+          ((tusb_control_request_t const*) p_request)->wLength > sizeof(tusb_desc_device_t))
       {
-        len = CFG_TUD_ENDPOINT0_SIZE;
-
         // Hack here: we modify the request length to prevent usbd_control response with zlp
-        ((tusb_control_request_t*) p_request)->wLength = CFG_TUD_ENDPOINT0_SIZE;
-      }
+        // since we are responding with 1 packet & less data than wLength.
+        tusb_control_request_t mod_request = *p_request;
+        mod_request.wLength = CFG_TUD_ENDPOINT0_SIZE;
 
-      return tud_control_xfer(rhport, p_request, (void*) tud_descriptor_device_cb(), len);
+        tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE);
+      }else
+      {
+        return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t));
+      }
     }
     break;
 
@@ -1015,10 +1017,11 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       // requested by host if USB > 2.0 ( i.e 2.1 or 3.x )
       if (!tud_descriptor_bos_cb) return false;
 
-      tusb_desc_bos_t const* desc_bos = (tusb_desc_bos_t const*) tud_descriptor_bos_cb();
+      uintptr_t desc_bos = (uintptr_t) tud_descriptor_bos_cb();
+      TU_ASSERT(desc_bos);
 
       // Use offsetof to avoid pointer to the odd/misaligned address
-      uint16_t const total_len = tu_le16toh( tu_unaligned_read16((uint8_t*) desc_bos + offsetof(tusb_desc_bos_t, wTotalLength)) );
+      uint16_t const total_len = tu_le16toh( tu_unaligned_read16((const void*) (desc_bos + offsetof(tusb_desc_bos_t, wTotalLength))) );
 
       return tud_control_xfer(rhport, p_request, (void*) desc_bos, total_len);
     }
@@ -1027,24 +1030,24 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
     case TUSB_DESC_CONFIGURATION:
     case TUSB_DESC_OTHER_SPEED_CONFIG:
     {
-      tusb_desc_configuration_t const* desc_config;
+      uintptr_t desc_config;
 
       if ( desc_type == TUSB_DESC_CONFIGURATION )
       {
         TU_LOG2(" Configuration[%u]\r\n", desc_index);
-        desc_config = (tusb_desc_configuration_t const*) tud_descriptor_configuration_cb(desc_index);
+        desc_config = (uintptr_t) tud_descriptor_configuration_cb(desc_index);
       }else
       {
         // Host only request this after getting Device Qualifier descriptor
         TU_LOG2(" Other Speed Configuration\r\n");
         TU_VERIFY( tud_descriptor_other_speed_configuration_cb );
-        desc_config = (tusb_desc_configuration_t const*) tud_descriptor_other_speed_configuration_cb(desc_index);
+        desc_config = (uintptr_t) tud_descriptor_other_speed_configuration_cb(desc_index);
       }
 
       TU_ASSERT(desc_config);
 
       // Use offsetof to avoid pointer to the odd/misaligned address
-      uint16_t const total_len = tu_le16toh( tu_unaligned_read16((uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) );
+      uint16_t const total_len = tu_le16toh( tu_unaligned_read16((const void*) (desc_config + offsetof(tusb_desc_configuration_t, wTotalLength))) );
 
       return tud_control_xfer(rhport, p_request, (void*) desc_config, total_len);
     }
@@ -1055,11 +1058,11 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       TU_LOG2(" String[%u]\r\n", desc_index);
 
       // String Descriptor always uses the desc set from user
-      uint8_t const* desc_str = (uint8_t const*) tud_descriptor_string_cb(desc_index, p_request->wIndex);
+      uint8_t const* desc_str = (uint8_t const*) tud_descriptor_string_cb(desc_index, tu_le16toh(p_request->wIndex));
       TU_VERIFY(desc_str);
 
       // first byte of descriptor is its size
-      return tud_control_xfer(rhport, p_request, (void*) desc_str, desc_str[0]);
+      return tud_control_xfer(rhport, p_request, (void*) (uintptr_t) desc_str, tu_desc_len(desc_str));
     }
     break;
 
@@ -1073,7 +1076,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       TU_VERIFY(desc_qualifier);
 
       // first byte of descriptor is its size
-      return tud_control_xfer(rhport, p_request, (void*) desc_qualifier, desc_qualifier[0]);
+      return tud_control_xfer(rhport, p_request, (void*) (uintptr_t) desc_qualifier, tu_desc_len(desc_qualifier));
     }
     break;
 
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index f40ba2d4f..06f23f8a5 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -125,7 +125,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
     if (is_in_isr())
     {
       // Called within ISR, use usbd task to defer later
-      usbd_defer_func( (osal_task_func_t) edpt_dma_start, (void*) reg_startep, true );
+      usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true);
       return;
     }
     else
@@ -773,7 +773,7 @@ void dcd_int_handler(uint8_t rhport)
           if ( _dcd.dma_pending )
           {
             // use usbd task to defer later
-            usbd_defer_func( (osal_task_func_t) start_ep0_task, (void*) &NRF_USBD->TASKS_EP0RCVOUT, true );
+            usbd_defer_func((osal_task_func_t) start_ep0_task, (void*) (uintptr_t) &NRF_USBD->TASKS_EP0RCVOUT, true);
           }else
           {
             start_ep0_task(&NRF_USBD->TASKS_EP0RCVOUT);

From 7325dd633536d086491ef057a544760886190cc7 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 16 Oct 2021 12:06:13 +0900
Subject: [PATCH 0569/2085] Change input terminal type to camera

---
 examples/device/video_capture/src/usb_descriptors.h | 9 +++++----
 src/class/video/video.h                             | 8 ++++++++
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 340b3f799..eeaef6bd2 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -48,7 +48,7 @@ enum {
     /* control */\
     + TUD_VIDEO_DESC_STD_VC_LEN\
     + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
-    + TUD_VIDEO_DESC_INPUT_TERM_LEN\
+    + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
     + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
     /* Interface 1, Alternate 0 */\
     + TUD_VIDEO_DESC_STD_VS_LEN\
@@ -79,9 +79,11 @@ enum {
   TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
     TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
          /* wTotalLength - bLength */ \
-         TUD_VIDEO_DESC_INPUT_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
+         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
          UVC_CLOCK_FREQUENCY, 1), \
-      TUD_VIDEO_DESC_INPUT_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, VIDEO_ETT_COMPOSITE_CONNECTOR, 0, 0), \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
+                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
+                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
   TUD_VIDEO_DESC_STD_VS( 1, 0, 0, 0), \
@@ -108,5 +110,4 @@ enum {
     /* EP */ \
     TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
 
-
 #endif
diff --git a/src/class/video/video.h b/src/class/video/video.h
index fa2976611..844746546 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -373,6 +373,7 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 #define TUD_VIDEO_DESC_CS_VC_LEN                  12
 #define TUD_VIDEO_DESC_INPUT_TERM_LEN             8
 #define TUD_VIDEO_DESC_OUTPUT_TERM_LEN            9
+#define TUD_VIDEO_DESC_CAMERA_TERM_LEN            18
 #define TUD_VIDEO_DESC_STD_VS_LEN                 9
 #define TUD_VIDEO_DESC_CS_VS_IN_LEN               13
 #define TUD_VIDEO_DESC_CS_VS_OUT_LEN              9
@@ -412,6 +413,13 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
   TUD_VIDEO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VC_OUTPUT_TERMINAL, \
     _tid, U16_TO_U8S_LE(_tt), _at, _srcid, _stridx
 
+/* 3.7.2.3 */
+#define TUD_VIDEO_DESC_CAMERA_TERM(_tid, _at, _stridx, _focal_min, _focal_max, _focal, _ctls) \
+  TUD_VIDEO_DESC_CAMERA_TERM_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VC_INPUT_TERMINAL, \
+    _tid, U16_TO_U8S_LE(VIDEO_ITT_CAMERA), _at, _stridx, \
+    U16_TO_U8S_LE(_focal_min), U16_TO_U8S_LE(_focal_max), U16_TO_U8S_LE(_focal), 3, \
+    TU_U32_BYTE0(_ctls), TU_U32_BYTE1(_ctls), TU_U32_BYTE2(_ctls)
+
 /* 3.9.1 */
 #define TUD_VIDEO_DESC_STD_VS(_itfnum, _alt, _epn, _stridx) \
   TUD_VIDEO_DESC_STD_VS_LEN, TUSB_DESC_INTERFACE, _itfnum, _alt, \

From a5f516893bbd539f11fb8d1cbb5b6db5a50fc632 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 17 Oct 2021 16:26:27 +0700
Subject: [PATCH 0570/2085] more with -Wcast-qual

---
 examples/device/cdc_msc_freertos/Makefile           |  3 +++
 examples/device/hid_composite_freertos/Makefile     |  3 +++
 examples/device/uac2_headset/src/main.c             | 13 +++++++------
 examples/device/video_capture/src/main.c            |  4 ++--
 examples/device/webusb_serial/src/main.c            |  4 ++--
 examples/make.mk                                    |  3 ++-
 hw/bsp/fomu/fomu.c                                  |  9 +++++++--
 hw/bsp/gd32vf103/family.c                           |  2 +-
 hw/bsp/imxrt/family.c                               |  2 +-
 hw/bsp/lpc15/family.mk                              |  2 +-
 hw/bsp/lpc18/family.mk                              |  2 +-
 hw/bsp/lpc54/family.c                               |  2 +-
 hw/bsp/lpc55/family.c                               |  2 +-
 hw/bsp/mm32/family.mk                               |  2 +-
 hw/bsp/rx/boards/gr_citrus/gr_citrus.c              |  2 +-
 hw/bsp/rx/boards/rx65n_target/rx65n_target.c        |  2 +-
 hw/bsp/samd11/family.mk                             |  3 +++
 hw/bsp/samd21/family.mk                             |  3 +++
 hw/bsp/samd51/family.mk                             |  3 ++-
 hw/bsp/saml2x/family.mk                             |  3 +++
 hw/bsp/stm32f0/family.c                             |  2 +-
 hw/bsp/stm32f0/family.mk                            |  2 +-
 hw/bsp/stm32f4/family.c                             |  2 +-
 hw/bsp/stm32f7/family.c                             |  2 +-
 hw/bsp/stm32h7/family.c                             |  2 +-
 src/class/cdc/cdc_host.c                            |  2 +-
 src/class/msc/msc_host.c                            |  2 +-
 src/device/usbd.c                                   |  2 +-
 src/host/usbh.c                                     |  5 ++---
 src/portable/ehci/ehci.c                            |  6 +++---
 .../nxp/transdimension/dcd_transdimension.c         |  2 +-
 src/portable/renesas/usba/dcd_usba.c                |  4 ++--
 src/portable/st/synopsys/dcd_synopsys.c             |  4 ++--
 src/portable/valentyusb/eptri/dcd_eptri.c           | 12 ++++++------
 34 files changed, 70 insertions(+), 48 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 677dcac9c..a155d6cb7 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -29,6 +29,9 @@ SRC_C += \
 	$(FREERTOS_SRC)/timers.c \
 	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
 
+# Suppress FreeRTOS warnings
+CFLAGS += -Wno-error=cast-qual
+
 # FreeRTOS (lto + Os) linker issue
 LDFLAGS += -Wl,--undefined=vTaskSwitchContext
 
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index 256db3d8c..c9b7abdf5 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -28,6 +28,9 @@ SRC_C += \
 	$(FREERTOS_SRC)/timers.c \
 	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
 
+# Suppress FreeRTOS warnings
+CFLAGS += -Wno-error=cast-qual
+
 # FreeRTOS (lto + Os) linker issue
 LDFLAGS += -Wl,--undefined=vTaskSwitchContext
 
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 790af088f..67e287d3e 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -36,11 +36,12 @@
 
 // List of supported sample rates
 #if defined(__RX__)
-const uint32_t sample_rates[]       = {44100, 48000};
+  const uint32_t sample_rates[] = {44100, 48000};
 #else
-const uint32_t sample_rates[]       = {44100, 48000, 88200, 96000};
+  const uint32_t sample_rates[] = {44100, 48000, 88200, 96000};
 #endif
-uint32_t       current_sample_rate  = 44100;
+
+uint32_t current_sample_rate  = 44100;
 
 #define N_SAMPLE_RATES  TU_ARRAY_SIZE(sample_rates)
 
@@ -202,7 +203,7 @@ static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t
   {
     TU_VERIFY(request->wLength == sizeof(audio_control_cur_4_t));
 
-    current_sample_rate = ((audio_control_cur_4_t *)buf)->bCur;
+    current_sample_rate = ((audio_control_cur_4_t const *)buf)->bCur;
 
     TU_LOG1("Clock set current freq: %d\r\n", current_sample_rate);
 
@@ -264,7 +265,7 @@ static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_req
   {
     TU_VERIFY(request->wLength == sizeof(audio_control_cur_1_t));
 
-    mute[request->bChannelNumber] = ((audio_control_cur_1_t *)buf)->bCur;
+    mute[request->bChannelNumber] = ((audio_control_cur_1_t const *)buf)->bCur;
 
     TU_LOG1("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]);
 
@@ -295,7 +296,7 @@ static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_req
 // Invoked when audio class specific get request received for an entity
 bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request)
 {
-  audio_control_request_t *request = (audio_control_request_t *)p_request;
+  audio_control_request_t const *request = (audio_control_request_t const *)p_request;
 
   if (request->bEntityID == UAC2_ENTITY_CLOCK)
     return tud_audio_clock_get_request(rhport, request);
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index a2d95c8f9..f1d48385f 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -166,7 +166,7 @@ void video_task(void)
     already_sent = 1;
     start_ms = board_millis();
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-    tud_video_n_frame_xfer(0, 0, (void*)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
+    tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t) &frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
                            FRAME_WIDTH * FRAME_HEIGHT * 16/8);
 #else
     fill_color_bar(frame_buffer, frame_num);
@@ -180,7 +180,7 @@ void video_task(void)
   start_ms += interval_ms;
 
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-  tud_video_n_frame_xfer(0, 0, (void*)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
+  tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t) &frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
                          FRAME_WIDTH * FRAME_HEIGHT * 16/8);
 #else
   fill_color_bar(frame_buffer, frame_num);
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index aba4aedff..2716825f8 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -179,7 +179,7 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ
         case VENDOR_REQUEST_WEBUSB:
           // match vendor request in BOS descriptor
           // Get landing page url
-          return tud_control_xfer(rhport, request, (void*) &desc_url, desc_url.bLength);
+          return tud_control_xfer(rhport, request, (void*)(uintptr_t) &desc_url, desc_url.bLength);
 
         case VENDOR_REQUEST_MICROSOFT:
           if ( request->wIndex == 7 )
@@ -188,7 +188,7 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ
             uint16_t total_len;
             memcpy(&total_len, desc_ms_os_20+8, 2);
 
-            return tud_control_xfer(rhport, request, (void*) desc_ms_os_20, total_len);
+            return tud_control_xfer(rhport, request, (void*)(uintptr_t) desc_ms_os_20, total_len);
           }else
           {
             return false;
diff --git a/examples/make.mk b/examples/make.mk
index c894d35f4..774625577 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -104,7 +104,8 @@ CFLAGS += \
   -Wmissing-format-attribute \
   -Wunreachable-code \
   -Wcast-align \
-  -Wcast-function-type
+  -Wcast-function-type \
+  -Wcast-qual
 
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
diff --git a/hw/bsp/fomu/fomu.c b/hw/bsp/fomu/fomu.c
index 25e5e9613..12b7bfd18 100644
--- a/hw/bsp/fomu/fomu.c
+++ b/hw/bsp/fomu/fomu.c
@@ -101,9 +101,14 @@ int board_uart_read(uint8_t* buf, int len)
 int board_uart_write(void const * buf, int len)
 {
   int32_t offset = 0;
+  uint8_t const* buf8 = (uint8_t const*) buf;
   for (offset = 0; offset < len; offset++)
-    if (! (messible_status_read() & CSR_MESSIBLE_STATUS_FULL_OFFSET))
-      messible_in_write(((uint8_t *)buf)[offset]);
+  {
+    if (!(messible_status_read() & CSR_MESSIBLE_STATUS_FULL_OFFSET))
+    {
+      messible_in_write(buf8[offset]);
+    }
+  }
   return len;
 }
 
diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c
index d76fb9a2a..c20732302 100644
--- a/hw/bsp/gd32vf103/family.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -158,7 +158,7 @@ int board_uart_write(void const* buf, int len) {
 #if defined(UART_DEV)
   int txsize = len;
   while (txsize--) {
-    usart_write(UART_DEV, *(uint8_t*)buf);
+    usart_write(UART_DEV, *(uint8_t const*)buf);
     buf++;
   }
   return len;
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 77a224a5e..716681ca9 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -172,7 +172,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
+  LPUART_WriteBlocking(UART_PORT, (uint8_t const*)buf, len);
   return len;
 }
 
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
index e80a3bc51..c7dd3f8be 100644
--- a/hw/bsp/lpc15/family.mk
+++ b/hw/bsp/lpc15/family.mk
@@ -15,7 +15,7 @@ CFLAGS += \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc15xx/lpc_chip_15xx
 
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index 3fed0b45a..79a00cb2d 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -13,7 +13,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC18XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes
+CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
 
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index 4789425a3..4f1199c3a 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -210,7 +210,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  USART_WriteBlocking(UART_DEV, (uint8_t *)buf, len);
+  USART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
   return 0;
 }
 
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index 4fc1f6222..f037a9f5b 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -265,7 +265,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  USART_WriteBlocking(UART_DEV, (uint8_t *)buf, len);
+  USART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
   return len;
 }
 
diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk
index 3273ff870..1a9f51191 100644
--- a/hw/bsp/mm32/family.mk
+++ b/hw/bsp/mm32/family.mk
@@ -14,7 +14,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_MM32F327X 
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized
+CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=cast-qual
 
 SRC_C += \
 	src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c \
diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
index caf5fd6fa..633ddad16 100644
--- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
+++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
@@ -228,7 +228,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const *buf, int len)
 {
-  sci0_buf[0].buf = (uint8_t*)buf;
+  sci0_buf[0].buf = (uint8_t*)(uintptr_t) buf;
   sci0_buf[0].cnt = len;
   SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
   while (SCI0.SCR.BIT.TE) ;
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index 20867455e..ab86bc419 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -273,7 +273,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const *buf, int len)
 {
-  sci_buf[0].buf = (uint8_t*)buf;
+  sci_buf[0].buf = (uint8_t*)(uintptr_t) buf;
   sci_buf[0].cnt = len;
   SCI5.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
   while (SCI5.SCR.BIT.TE) ;
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index 032d11b98..ae55be75b 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -11,6 +11,9 @@ CFLAGS += \
   -DOSC32K_OVERWRITE_CALIBRATION=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD11
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
+
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
 	hw/mcu/microchip/samd11/gcc/gcc/startup_samd11.c \
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index f1b063f2c..208f23789 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -12,6 +12,9 @@ CFLAGS += \
   -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD21
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
+
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
 	hw/mcu/microchip/samd21/gcc/gcc/startup_samd21.c \
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
index f4e260fb1..783bed82a 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd51/family.mk
@@ -13,7 +13,8 @@ CFLAGS += \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD51
 
-CFLAGS += -Wno-error=undef
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index e0f6b2f77..bb1faeb7f 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -13,6 +13,9 @@ CFLAGS += \
   -DCONF_OSC32K_CALIB_ENABLE=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAML22
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
+
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
 	$(MCU_DIR)/gcc/gcc/startup_$(SAML_VARIANT).c \
diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index 68b924432..8de3147e2 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -134,7 +134,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 08cbf5626..39831e154 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -18,7 +18,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F0
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
 
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index cf0cb2b08..31f27fa3f 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -160,7 +160,7 @@ int board_uart_read(uint8_t* buf, int len)
 int board_uart_write(void const * buf, int len)
 {
 #ifdef UART_DEV
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 #else
   (void) buf; (void) len; (void) UartHandle;
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index 2eb737ee3..14e3b2fd9 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -284,7 +284,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index a2116d0bd..84976b4e4 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -237,7 +237,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index e7eaf4d05..f4fb6c1d6 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -105,7 +105,7 @@ bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool i
   uint8_t const ep_out = cdch_data[dev_addr-1].ep_out;
   if ( usbh_edpt_busy(dev_addr, ep_out) ) return false;
 
-  return usbh_edpt_xfer(dev_addr, ep_out, (void *) p_data, length);
+  return usbh_edpt_xfer(dev_addr, ep_out, (void*)(uintptr_t) p_data, length);
 }
 
 bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify)
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 8069353cd..fa6519956 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -263,7 +263,7 @@ bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_
 
   memcpy(cbw.command, &cmd_write10, cbw.cmd_len);
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, (void*) buffer, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb);
 }
 
 #if 0
diff --git a/src/device/usbd.c b/src/device/usbd.c
index b4680283f..6a5210b34 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1002,7 +1002,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
         tusb_control_request_t mod_request = *p_request;
         mod_request.wLength = CFG_TUD_ENDPOINT0_SIZE;
 
-        tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE);
+        return tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE);
       }else
       {
         return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t));
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 2ef936ad0..53e8b9715 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -894,11 +894,10 @@ static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tusb_control_r
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   // TODO not enough buffer to hold configuration descriptor
-  tusb_desc_configuration_t const * desc_config = (tusb_desc_configuration_t const*) _usbh_ctrl_buf;
-  uint16_t total_len;
+  uint8_t const * desc_config = _usbh_ctrl_buf;
 
   // Use offsetof to avoid pointer to the odd/misaligned address
-  memcpy(&total_len, (uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength), 2);
+  uint16_t const total_len = tu_le16toh( tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) );
 
   TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE);
 
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index e3b7499cc..18ddaf31a 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -128,7 +128,7 @@ static inline ehci_qtd_t* qtd_find_free (void);
 static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd);
 static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new);
 static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd);
-static void qtd_init (ehci_qtd_t* p_qtd, void* buffer, uint16_t total_bytes);
+static void qtd_init (ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes);
 
 static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
 static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer);
@@ -392,7 +392,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   ehci_qhd_t* qhd = &ehci_data.control[dev_addr].qhd;
   ehci_qtd_t* td  = &ehci_data.control[dev_addr].qtd;
 
-  qtd_init(td, (void*) setup_packet, 8);
+  qtd_init(td, setup_packet, 8);
   td->pid          = EHCI_PID_SETUP;
   td->int_on_complete = 1;
   td->next.terminate  = 1;
@@ -857,7 +857,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
   }
 }
 
-static void qtd_init(ehci_qtd_t* p_qtd, void* buffer, uint16_t total_bytes)
+static void qtd_init(ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes)
 {
   tu_memclr(p_qtd, sizeof(ehci_qtd_t));
 
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index a7c4545c2..0f58cceb9 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -636,7 +636,7 @@ void dcd_int_handler(uint8_t rhport)
       // 23.10.10.2 Operational model for setup transfers
       dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
 
-      dcd_event_setup_received(rhport, (uint8_t*) &_dcd_data.qhd[0][0].setup_request, true);
+      dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
     }
 
     // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 92e29f9bf..07d3ba898 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -259,7 +259,7 @@ static inline void pipe_wait_for_ready(unsigned num)
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 {
-  hw_fifo_t *reg = (hw_fifo_t*)fifo;
+  volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo;
   uintptr_t addr = (uintptr_t)buf;
   while (len >= 2) {
     reg->u16 = *(const uint16_t *)addr;
@@ -275,7 +275,7 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
 {
   uint8_t *p   = (uint8_t*)buf;
-  uint8_t *reg = (uint8_t*)fifo;  /* byte access is always at base register address */
+  volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
   while (len--) *p++ = *reg;
 }
 
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 85abf940e..29030784b 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -976,7 +976,7 @@ static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_
       if (xfer->ff)
       {
         // Ring buffer
-        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *) rx_fifo, bcnt);
+        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt);
       }
       else
       {
@@ -1096,7 +1096,7 @@ static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OT
           if (xfer->ff)
           {
             usb_fifo_t tx_fifo = FIFO_BASE(rhport, n);
-            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *) tx_fifo, packet_size);
+            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size);
           }
           else
           {
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c
index 89bc7a1ab..837d0c0ce 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.c
+++ b/src/portable/valentyusb/eptri/dcd_eptri.c
@@ -314,13 +314,13 @@ static void dcd_reset(void)
   usb_in_ctrl_write(1 << CSR_USB_IN_CTRL_RESET_OFFSET);
   usb_out_ctrl_write(1 << CSR_USB_OUT_CTRL_RESET_OFFSET);
 
-  memset((void *)rx_buffer, 0, sizeof(rx_buffer));
-  memset((void *)rx_buffer_max, 0, sizeof(rx_buffer_max));
-  memset((void *)rx_buffer_offset, 0, sizeof(rx_buffer_offset));
+  memset((void *)(uintptr_t) rx_buffer, 0, sizeof(rx_buffer));
+  memset((void *)(uintptr_t) rx_buffer_max, 0, sizeof(rx_buffer_max));
+  memset((void *)(uintptr_t) rx_buffer_offset, 0, sizeof(rx_buffer_offset));
 
-  memset((void *)tx_buffer, 0, sizeof(tx_buffer));
-  memset((void *)tx_buffer_max, 0, sizeof(tx_buffer_max));
-  memset((void *)tx_buffer_offset, 0, sizeof(tx_buffer_offset));
+  memset((void *)(uintptr_t) tx_buffer, 0, sizeof(tx_buffer));
+  memset((void *)(uintptr_t) tx_buffer_max, 0, sizeof(tx_buffer_max));
+  memset((void *)(uintptr_t) tx_buffer_offset, 0, sizeof(tx_buffer_offset));
   tx_ep = 0;
   tx_active = false;
 

From 31cd36693502cbeb9537dc280f674f99e4488df9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 17 Oct 2021 17:32:03 +0700
Subject: [PATCH 0571/2085] more -Wcast-qual

---
 hw/bsp/d5035_01/board.mk                 |  3 +++
 hw/bsp/ea4088qs/board.mk                 |  2 +-
 hw/bsp/ea4357/board.mk                   |  2 +-
 hw/bsp/frdm_k32l2b/frdm_k32l2b.c         |  2 +-
 hw/bsp/frdm_kl25z/frdm_kl25z.c           |  2 +-
 hw/bsp/lpcxpresso1769/board.mk           |  2 +-
 hw/bsp/mbed1768/board.mk                 |  2 +-
 hw/bsp/ngx4330/board.mk                  |  2 +-
 hw/bsp/nutiny_nuc121s/board.mk           | 14 +-------------
 hw/bsp/nutiny_nuc126v/board.mk           | 17 +----------------
 hw/bsp/nutiny_sdk_nuc120/board.mk        | 17 +----------------
 hw/bsp/same54xplainedpro/board.mk        |  2 ++
 hw/bsp/same70_qmtech/board.mk            |  2 +-
 hw/bsp/same70_xplained/board.mk          |  2 +-
 hw/bsp/samg55xplained/board.mk           |  2 +-
 hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c |  2 +-
 src/portable/sony/cxd56/dcd_cxd56.c      |  2 +-
 17 files changed, 20 insertions(+), 57 deletions(-)

diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk
index 1d09bd3d4..b7796b9d8 100644
--- a/hw/bsp/d5035_01/board.mk
+++ b/hw/bsp/d5035_01/board.mk
@@ -18,6 +18,9 @@ CFLAGS += \
   -DSVC_Handler=SVCall_Handler \
   -DHWREV=$(HWREV)
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld
 
diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/ea4088qs/board.mk
index c624a5cf2..b325dfeb4 100644
--- a/hw/bsp/ea4088qs/board.mk
+++ b/hw/bsp/ea4088qs/board.mk
@@ -14,7 +14,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC40XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
 
diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
index 86391ab5d..4390d1eda 100644
--- a/hw/bsp/ea4357/board.mk
+++ b/hw/bsp/ea4357/board.mk
@@ -13,7 +13,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes
+CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes  -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 
diff --git a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
index c45095caa..924bb18e9 100644
--- a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
+++ b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
@@ -122,7 +122,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  LPUART_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
+  LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
   return len;
 }
 
diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c
index cdc996bc2..72982ed8a 100644
--- a/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c
@@ -153,7 +153,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  LPSCI_WriteBlocking(UART_PORT, (uint8_t*)buf, len);
+  LPSCI_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
   return len;
 }
 
diff --git a/hw/bsp/lpcxpresso1769/board.mk b/hw/bsp/lpcxpresso1769/board.mk
index b69be39bd..34b4d6dc0 100644
--- a/hw/bsp/lpcxpresso1769/board.mk
+++ b/hw/bsp/lpcxpresso1769/board.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DRTC_EV_SUPPORT=0
 
 # lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 
diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk
index e99df9f08..b0d885866 100644
--- a/hw/bsp/mbed1768/board.mk
+++ b/hw/bsp/mbed1768/board.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DRTC_EV_SUPPORT=0
 
 # startup.c and lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 
diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk
index 04c37feeb..3b193c0a5 100644
--- a/hw/bsp/ngx4330/board.mk
+++ b/hw/bsp/ngx4330/board.mk
@@ -13,7 +13,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index a0a208ca7..ff1d5aa3a 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -16,24 +16,12 @@ LD_FILE = hw/bsp/$(BOARD)/nuc121_flash.ld
 SRC_C += \
   src/portable/nuvoton/nuc121/dcd_nuc121.c \
   hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/system_NUC121.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/adc.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/bpwm.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/clk.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/fmc.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/gpio.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/i2c.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/pdma.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/pwm.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/spi_i2s.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/sys.c \
   hw/mcu/nuvoton/nuc121_125/StdDriver/src/timer.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/uart.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usbd.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_i2c.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_spi.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/usci_uart.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/wdt.c \
-  hw/mcu/nuvoton/nuc121_125/StdDriver/src/wwdt.c
+  hw/mcu/nuvoton/nuc121_125/StdDriver/src/uart.c
 
 SRC_S += \
   hw/mcu/nuvoton/nuc121_125/Device/Nuvoton/NUC121/Source/GCC/startup_NUC121.S
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index e9df1ed13..4f0ebf201 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -17,28 +17,13 @@ LD_FILE = hw/bsp/$(BOARD)/nuc126_flash.ld
 SRC_C += \
   src/portable/nuvoton/nuc121/dcd_nuc121.c \
   hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/system_NUC126.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/acmp.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/adc.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/clk.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/crc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/ebi.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/fmc.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/gpio.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/pdma.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/pwm.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/rtc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/sc.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/scuart.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/spi.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/sys.c \
   hw/mcu/nuvoton/nuc126/StdDriver/src/timer.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/timer_pwm.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/uart.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/usbd.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/usci_spi.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/usci_uart.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/wdt.c \
-  hw/mcu/nuvoton/nuc126/StdDriver/src/wwdt.c
+  hw/mcu/nuvoton/nuc126/StdDriver/src/uart.c
 
 SRC_S += \
   hw/mcu/nuvoton/nuc126/Device/Nuvoton/NUC126/Source/GCC/startup_NUC126.S
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index 1fde47c5a..4d7aac7f5 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -15,26 +15,11 @@ LD_FILE = hw/bsp/nutiny_sdk_nuc120/nuc120_flash.ld
 SRC_C += \
   src/portable/nuvoton/nuc120/dcd_nuc120.c \
   hw/mcu/nuvoton/nuc100_120/Device/Nuvoton/NUC100Series/Source/system_NUC100Series.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/acmp.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/adc.c \
   hw/mcu/nuvoton/nuc100_120/StdDriver/src/clk.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/crc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/fmc.c \
   hw/mcu/nuvoton/nuc100_120/StdDriver/src/gpio.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/i2c.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/i2s.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/pdma.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/ps2.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/pwm.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/rtc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/sc.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/spi.c \
   hw/mcu/nuvoton/nuc100_120/StdDriver/src/sys.c \
   hw/mcu/nuvoton/nuc100_120/StdDriver/src/timer.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/uart.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/usbd.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/wdt.c \
-  hw/mcu/nuvoton/nuc100_120/StdDriver/src/wwdt.c
+  hw/mcu/nuvoton/nuc100_120/StdDriver/src/uart.c
 
 SRC_S += \
   hw/mcu/nuvoton/nuc100_120/Device/Nuvoton/NUC100Series/Source/GCC/startup_NUC100Series.S
diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
index 16ac786d5..2d0d928ff 100644
--- a/hw/bsp/same54xplainedpro/board.mk
+++ b/hw/bsp/same54xplainedpro/board.mk
@@ -15,6 +15,8 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
   -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-qual
 
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld
diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
index 6c84810f3..ba7088e44 100644
--- a/hw/bsp/same70_qmtech/board.mk
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -11,7 +11,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
 
 ASF_DIR = hw/mcu/microchip/same70
 
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index c9bc0cea3..cb2decf50 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -11,7 +11,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
 
 ASF_DIR = hw/mcu/microchip/same70
 
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index aed4de68e..f9396cb30 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMG
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=undef
+CFLAGS += -Wno-error=undef -Wno-error=cast-qual
 
 ASF_DIR = hw/mcu/microchip/samg55
 
diff --git a/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c b/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c
index bab66b550..8c661b602 100644
--- a/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c
+++ b/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c
@@ -257,7 +257,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-  HAL_UART_Transmit(&UartHandle, (uint8_t*) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index cfd74330f..1b8a789a4 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -134,7 +134,7 @@ static int _dcd_setup(FAR struct usbdevclass_driver_s *driver, FAR struct usbdev
   if (usbdcd_driver.setup_processed)
   {
     usbdcd_driver.setup_processed = false;
-    dcd_event_setup_received(0, (uint8_t *) ctrl, true);
+    dcd_event_setup_received(0, (uint8_t const *) ctrl, true);
   }
   else
   {

From 099d3b377fd619e664e60c948e6f73d7276dd81d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 17 Oct 2021 17:33:14 +0700
Subject: [PATCH 0572/2085] add volatile to EPx_REGS for -Wcast-qual

since gcc does difference between volatile struct and member when
casting pointer
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index a36165343..b5c656d94 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -140,7 +140,7 @@ typedef struct
     __IOM uint32_t USB_RXC2_REG;                 /*!< (@ 0x000000DC) Receive Command Register 2    */
     __IOM uint32_t USB_RXC3_REG;                 /*!< (@ 0x000000FC) Receive Command Register 3    */
   };
-} EPx_REGS;
+} volatile EPx_REGS;
 
 #define EP_REGS(first_ep_reg) (EPx_REGS*)(&USB->first_ep_reg)
 

From 826b34a8ac433e089c8522d949def4d8421ca4a2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 18 Oct 2021 00:13:40 +0700
Subject: [PATCH 0573/2085] enable -Wnull-dereference

---
 examples/make.mk                         | 3 ++-
 hw/bsp/samg55xplained/board.mk           | 2 +-
 src/portable/nuvoton/nuc505/dcd_nuc505.c | 7 ++++++-
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/examples/make.mk b/examples/make.mk
index 774625577..793c40aa2 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -105,7 +105,8 @@ CFLAGS += \
   -Wunreachable-code \
   -Wcast-align \
   -Wcast-function-type \
-  -Wcast-qual
+  -Wcast-qual \
+  -Wnull-dereference
 
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index f9396cb30..deff6944c 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMG
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=cast-qual
+CFLAGS += -Wno-error=undef -Wno-error=cast-qual -Wno-error=null-dereference
 
 ASF_DIR = hw/mcu/microchip/samg55
 
diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c
index ea5a8bea5..11d71a285 100644
--- a/src/portable/nuvoton/nuc505/dcd_nuc505.c
+++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c
@@ -144,7 +144,9 @@ static USBD_EP_T *ep_entry(uint8_t ep_addr, bool add)
   enum ep_enum ep_index;
   struct xfer_ctl_t *xfer;
 
-  for (ep_index = PERIPH_EPA, xfer = &xfer_table[PERIPH_EPA], ep = USBD->EP; ep_index < PERIPH_MAX_EP; ep_index++, xfer++, ep++)
+  for (ep_index = PERIPH_EPA, xfer = &xfer_table[PERIPH_EPA], ep = USBD->EP;
+       ep_index < PERIPH_MAX_EP;
+       ep_index++, xfer++, ep++)
   {
     if (add)
     {
@@ -396,6 +398,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
     /* mine the data for the information we need */
     tusb_dir_t dir = tu_edpt_dir(ep_addr);
     USBD_EP_T *ep = ep_entry(ep_addr, false);
+    TU_ASSERT(ep);
     struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
 
     /* store away the information we'll needing now and later */
@@ -457,6 +460,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   if (tu_edpt_number(ep_addr))
   {
     USBD_EP_T *ep = ep_entry(ep_addr, false);
+    TU_ASSERT(ep, );
     ep->EPRSPCTL = (ep->EPRSPCTL & 0xf7) | USBD_EPRSPCTL_HALT_Msk;
   }
   else
@@ -472,6 +476,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   if (tu_edpt_number(ep_addr))
   {
     USBD_EP_T *ep = ep_entry(ep_addr, false);
+    TU_ASSERT(ep, );
     ep->EPRSPCTL = USBD_EPRSPCTL_TOGGLE_Msk;
   }
 }

From a7dd5b616cb95a4e395a148fcd2f761ce23a8faf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 18 Oct 2021 01:11:27 +0700
Subject: [PATCH 0574/2085] fix -Wnull-dereference in midi_device

---
 src/class/midi/midi_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index eb85b668c..edec57846 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -433,6 +433,7 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint
       break;
     }
   }
+  TU_ASSERT(p_midi);
 
   p_midi->itf_num = desc_midi->bInterfaceNumber;
   (void) p_midi->itf_num;

From 6fcf4bee8c1540618b5d8d8709ef76cd2aa1c66f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 18 Oct 2021 11:42:00 +0700
Subject: [PATCH 0575/2085] suppress null-dereference by usbh and lwip

---
 examples/device/net_lwip_webserver/Makefile |  3 ++
 examples/host/cdc_msc_hid/Makefile          |  3 +-
 examples/host/hid_controller/Makefile       |  3 +-
 src/host/usbh.c                             | 48 ++++++++++++---------
 4 files changed, 35 insertions(+), 22 deletions(-)

diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile
index c3e0d8899..5649a172a 100644
--- a/examples/device/net_lwip_webserver/Makefile
+++ b/examples/device/net_lwip_webserver/Makefile
@@ -7,6 +7,9 @@ CFLAGS += \
   -DPBUF_POOL_SIZE=2 \
   -DTCP_WND=2*TCP_MSS \
   -DHTTPD_USE_CUSTOM_FSDATA=0
+  
+# suppress warning caused by lwip
+CFLAGS += -Wno-error=null-dereference
 
 INC += \
   src \
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index 6a2b4d902..0ad9dd856 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -9,7 +9,8 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-CFLAGS += -Wno-error=cast-align
+# TODO: suppress warning caused by host stack
+CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
 
 # TinyUSB Host Stack source
 SRC_C += \
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index 6f59faeee..2595ec4a7 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -12,7 +12,8 @@ EXAMPLE_SOURCE += \
 	
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-CFLAGS += -Wno-error=cast-align
+# TODO: suppress warning caused by host stack
+CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
 
 # TinyUSB Host Stack source
 SRC_C += \
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 53e8b9715..a9c2c201f 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -53,13 +53,39 @@
 // USBH-HCD common data structure
 //--------------------------------------------------------------------+
 
-typedef struct {
-  //------------- port -------------//
+// device0 struct must be strictly a subset of normal device struct
+typedef struct
+{
+  // port
   uint8_t rhport;
   uint8_t hub_addr;
   uint8_t hub_port;
   uint8_t speed;
 
+  volatile struct TU_ATTR_PACKED
+  {
+    uint8_t connected    : 1;
+    uint8_t addressed    : 1;
+    uint8_t configured   : 1;
+    uint8_t suspended    : 1;
+  };
+} usbh_dev0_t;
+
+typedef struct {
+  // port
+  uint8_t rhport;
+  uint8_t hub_addr;
+  uint8_t hub_port;
+  uint8_t speed;
+
+  volatile struct TU_ATTR_PACKED
+  {
+    uint8_t connected    : 1;
+    uint8_t addressed    : 1;
+    uint8_t configured   : 1;
+    uint8_t suspended    : 1;
+  };
+
   //------------- device descriptor -------------//
   uint16_t vid;
   uint16_t pid;
@@ -73,14 +99,6 @@ typedef struct {
   // uint8_t interface_count; // bNumInterfaces alias
 
   //------------- device -------------//
-  struct TU_ATTR_PACKED
-  {
-    uint8_t connected    : 1;
-    uint8_t addressed    : 1;
-    uint8_t configured   : 1;
-    uint8_t suspended    : 1;
-  };
-
   volatile uint8_t state;            // device state, value from enum tusbh_device_state_t
 
   uint8_t itf2drv[16];               // map interface number to driver (0xff is invalid)
@@ -103,16 +121,6 @@ typedef struct {
 
 } usbh_device_t;
 
-typedef struct
-{
-  uint8_t rhport;
-  uint8_t hub_addr;
-  uint8_t hub_port;
-  uint8_t speed;
-
-  volatile uint8_t connected;
-} usbh_dev0_t;
-
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF

From 4fd0ee4eef149237aa58b24e843649b16d5ca1dc Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 16 Oct 2021 15:52:46 +0900
Subject: [PATCH 0576/2085] Implement GET_DEF and GET_LEN handling on
 Probe/Commit entities of streaming interface

---
 src/class/video/video_device.c | 86 +++++++++++++++++++++++++++-------
 1 file changed, 68 insertions(+), 18 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 91d3b2b72..cd6459a18 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -354,21 +354,25 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   return true;
 }
 
-/** Set the minimum or the maximum values to variables which need to negotiate with the host
+/** Set the minimum, maximum or default values to variables which need to negotiate with the host
  *
- * @param[in]     set_max     If true, the maximum values is set, otherwise the minimum value is set.
+ * @param[in]     request     GET_MAX, GET_MIN or GET_DEF
  * @param[in,out] param       Target
  */
-static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *stm, bool set_max,
+static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *stm, uint_fast8_t request,
                                             video_probe_and_commit_control_t *param)
 {
   uint_fast8_t const fmtnum = param->bFormatIndex;
   if (!fmtnum) {
-    if (set_max) {
-      tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
-      param->bFormatIndex   = vs->stm.bNumFormats;
-    } else {
-      param->bFormatIndex   = 1;
+    switch (request) {
+      case VIDEO_REQUEST_GET_MAX:
+        param->bFormatIndex = _get_desc_vs(stm)->stm.bNumFormats;
+        break;
+      case VIDEO_REQUEST_GET_MIN:
+      case VIDEO_REQUEST_GET_DEF:
+        param->bFormatIndex = 1;
+        break;
+      default: return false;
     }
     /* Set the parameters determined by the format  */
     param->wKeyFrameRate    = 1;
@@ -391,7 +395,18 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
     tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
     void const *end = _end_of_streaming_descriptor(vs);
     tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
-    frmnum = set_max ? fmt->bNumFrameDescriptors: 1;
+    switch (request) {
+      case VIDEO_REQUEST_GET_MAX:
+        frmnum = fmt->bNumFrameDescriptors;
+        break;
+      case VIDEO_REQUEST_GET_MIN:
+        frmnum = 1;
+        break;
+      case VIDEO_REQUEST_GET_DEF:
+        frmnum = fmt->bDefaultFrameIndex;
+        break;
+      default: return false;
+    }
     param->bFrameIndex = frmnum;
     /* Set the parameters determined by the frame */
     tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
@@ -406,11 +421,20 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
     tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
 
     uint_fast32_t interval;
-    uint_fast8_t num_intervals = frm->bFrameIntervalType;
-    if (!num_intervals) {
-      interval = set_max ? frm->dwFrameInterval[1]: frm->dwFrameInterval[0];
-    } else {
-      interval = set_max ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[0];
+    switch (request) {
+      case VIDEO_REQUEST_GET_MAX:
+        {
+          uint_fast8_t num_intervals = frm->bFrameIntervalType;
+          interval = num_intervals ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[1];
+        }
+        break;
+      case VIDEO_REQUEST_GET_MIN:
+        interval = frm->dwFrameInterval[0];
+        break;
+      case VIDEO_REQUEST_GET_DEF:
+        interval = frm->dwDefaultFrameInterval;
+        break;
+      default: return false;
     }
     param->dwFrameInterval = interval;
     uint_fast32_t interval_ms = interval / 10000;
@@ -784,7 +808,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
 
             video_probe_and_commit_control_t tmp;
             tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
-            TU_VERIFY(_negotiate_streaming_parameters(self, false, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_MIN, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
             TU_VERIFY(tud_control_xfer(rhport, request, &tmp, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
@@ -795,14 +819,31 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
             video_probe_and_commit_control_t tmp;
             tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
-            TU_VERIFY(_negotiate_streaming_parameters(self, true, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_MAX, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
             TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_RES: return VIDEO_ERROR_UNKNOWN;
-        case VIDEO_REQUEST_GET_DEF: return VIDEO_ERROR_UNKNOWN;
-        case VIDEO_REQUEST_GET_LEN: return VIDEO_ERROR_UNKNOWN;
+        case VIDEO_REQUEST_GET_DEF:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
+            video_probe_and_commit_control_t tmp;
+            tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
+            TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_DEF, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_UNKNOWN;
+
+        case VIDEO_REQUEST_GET_LEN:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(2 == request->wLength, VIDEO_ERROR_UNKNOWN);
+            uint16_t len = sizeof(video_probe_and_commit_control_t);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&len, sizeof(len)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_INFO:
           if (stage == CONTROL_STAGE_SETUP)
@@ -838,6 +879,15 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           }
           return VIDEO_ERROR_NONE;
 
+        case VIDEO_REQUEST_GET_LEN:
+          if (stage == CONTROL_STAGE_SETUP)
+          {
+            TU_VERIFY(2 == request->wLength, VIDEO_ERROR_UNKNOWN);
+            uint16_t len = sizeof(video_probe_and_commit_control_t);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)&len, sizeof(len)), VIDEO_ERROR_UNKNOWN);
+          }
+          return VIDEO_ERROR_NONE;
+
         case VIDEO_REQUEST_GET_INFO:
           if (stage == CONTROL_STAGE_SETUP)
           {

From 3485c82246ce17be1ca9649bb36dfc8b1782e593 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 19 Oct 2021 12:35:35 +0700
Subject: [PATCH 0577/2085] update changelog

---
 docs/info/changelog.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index 4cb30799c..8eec729d6 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -11,10 +11,10 @@ Device Controller Driver (DCD)
 ------------------------------
 
 - Getting device stack to pass USB Compliance Verification test (chapter9, HID, MSC). Ports are tested:
-  nRF, SAMD 21/51, rp2040, stm32f4, Renesas RX, iMXRT, ESP32-S2/3, Kinetic KL25/32
+  nRF, SAMD 21/51, rp2040, stm32f4, Renesas RX, iMXRT, ESP32-S2/3, Kinetic KL25/32, DA146xx
 - Added dcd_edpt_close_all() for switching configuration
 - [Transdimension] Support dcd_edpt_xfer_fifo() with auto wrap over if fifo buffer is 4K aligned and size is multiple of 4K.
-- [Da146xx] Improve vbus, reset, suspend, resume detection, and remote wakeup.
+- [DA146xx] Improve vbus, reset, suspend, resume detection, and remote wakeup.
 
 Device Stack
 ------------

From b3b6b4f785de6916ce352c308108242227ce8a47 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Tue, 19 Oct 2021 21:49:00 +0900
Subject: [PATCH 0578/2085] Update _negotiate_streaming_parameters() to handle
 some requests

---
 src/class/video/video_device.c | 74 +++++++++++++++++++---------------
 1 file changed, 41 insertions(+), 33 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index cd6459a18..3cd25628b 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -354,9 +354,9 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   return true;
 }
 
-/** Set the minimum, maximum or default values to variables which need to negotiate with the host
+/** Set the minimum, maximum, default values or resolutions to variables which need to negotiate with the host
  *
- * @param[in]     request     GET_MAX, GET_MIN or GET_DEF
+ * @param[in]     request     GET_MAX, GET_MIN, GET_RES or GET_DEF
  * @param[in,out] param       Target
  */
 static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *stm, uint_fast8_t request,
@@ -420,27 +420,56 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
     tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
     tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
 
-    uint_fast32_t interval;
+    uint_fast32_t interval, interval_ms;
     switch (request) {
       case VIDEO_REQUEST_GET_MAX:
         {
+          uint_fast32_t min_interval, max_interval;
           uint_fast8_t num_intervals = frm->bFrameIntervalType;
-          interval = num_intervals ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[1];
+          max_interval = num_intervals ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[1];
+          min_interval = frm->dwFrameInterval[0];
+          interval = max_interval;
+          interval_ms = min_interval / 10000;
         }
         break;
       case VIDEO_REQUEST_GET_MIN:
-        interval = frm->dwFrameInterval[0];
+        {
+          uint_fast32_t min_interval, max_interval;
+          uint_fast8_t num_intervals = frm->bFrameIntervalType;
+          max_interval = num_intervals ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[1];
+          min_interval = frm->dwFrameInterval[0];
+          interval = min_interval;
+          interval_ms = max_interval / 10000;
+        }
         break;
       case VIDEO_REQUEST_GET_DEF:
         interval = frm->dwDefaultFrameInterval;
+        interval_ms = interval / 10000;
+        break;
+      case VIDEO_REQUEST_GET_RES:
+        {
+          uint_fast8_t num_intervals = frm->bFrameIntervalType;
+          if (num_intervals) {
+            interval = 0;
+          } else {
+            interval = frm->dwFrameInterval[2];
+            interval_ms = interval / 10000;
+          }
+        }
         break;
       default: return false;
     }
     param->dwFrameInterval = interval;
-    uint_fast32_t interval_ms = interval / 10000;
-    TU_ASSERT(interval_ms);
-    uint_fast32_t frame_size = param->dwMaxVideoFrameSize;
-    param->dwMaxPayloadTransferSize = (frame_size + interval_ms - 1) / interval_ms + 2;
+    if (!interval) {
+      param->dwMaxPayloadTransferSize = 0;
+    } else {
+      uint_fast32_t frame_size = param->dwMaxVideoFrameSize;
+      if (!interval_ms) {
+        param->dwMaxPayloadTransferSize = frame_size + 2;
+      } else {
+        param->dwMaxPayloadTransferSize = (frame_size + interval_ms - 1) / interval_ms + 2;
+      }
+    }
     return true;
   }
   return true;
@@ -802,39 +831,18 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_MIN:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
-            TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-
-            video_probe_and_commit_control_t tmp;
-            tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
-            TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_MIN, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
-            TU_VERIFY(tud_control_xfer(rhport, request, &tmp, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
-          }
-          return VIDEO_ERROR_NONE;
-
         case VIDEO_REQUEST_GET_MAX:
-          if (stage == CONTROL_STAGE_SETUP)
-          {
-            TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
-            video_probe_and_commit_control_t tmp;
-            tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
-            TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_MAX, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
-            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
-          }
-          return VIDEO_ERROR_NONE;
-
-        case VIDEO_REQUEST_GET_RES: return VIDEO_ERROR_UNKNOWN;
+        case VIDEO_REQUEST_GET_RES:
         case VIDEO_REQUEST_GET_DEF:
           if (stage == CONTROL_STAGE_SETUP)
           {
             TU_VERIFY(request->wLength, VIDEO_ERROR_UNKNOWN);
             video_probe_and_commit_control_t tmp;
             tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
-            TU_VERIFY(_negotiate_streaming_parameters(self, VIDEO_REQUEST_GET_DEF, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            TU_VERIFY(_negotiate_streaming_parameters(self, request->bRequest, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
             TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           }
-          return VIDEO_ERROR_UNKNOWN;
+          return VIDEO_ERROR_NONE;
 
         case VIDEO_REQUEST_GET_LEN:
           if (stage == CONTROL_STAGE_SETUP)

From d42b5604ce6ccdd9c5acba009e6a3d95c27ca573 Mon Sep 17 00:00:00 2001
From: Peter Lawrence <12226419+majbthrd@users.noreply.github.com>
Date: Fri, 15 Oct 2021 20:10:19 -0500
Subject: [PATCH 0579/2085] net_lwip_webserver: allow users to enable LWIP_IP6
 if desired

---
 examples/device/net_lwip_webserver/Makefile   | 14 +++++--
 .../device/net_lwip_webserver/src/lwipopts.h  | 12 ++++++
 examples/device/net_lwip_webserver/src/main.c | 40 +++++++++++++------
 lib/networking/dhserver.c                     | 16 ++++----
 lib/networking/dhserver.h                     | 10 ++---
 lib/networking/dnserver.c                     |  2 +-
 lib/networking/dnserver.h                     |  2 +-
 7 files changed, 66 insertions(+), 30 deletions(-)

diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile
index c3e0d8899..03f298cec 100644
--- a/examples/device/net_lwip_webserver/Makefile
+++ b/examples/device/net_lwip_webserver/Makefile
@@ -4,9 +4,8 @@ include ../../../tools/top.mk
 include ../../make.mk
 
 CFLAGS += \
-  -DPBUF_POOL_SIZE=2 \
-  -DTCP_WND=2*TCP_MSS \
-  -DHTTPD_USE_CUSTOM_FSDATA=0
+  -Wno-error=unused-parameter \
+  -Wno-error=unused-variable
 
 INC += \
   src \
@@ -50,6 +49,15 @@ SRC_C += \
   lib/lwip/src/core/ipv4/ip4.c \
   lib/lwip/src/core/ipv4/ip4_addr.c \
   lib/lwip/src/core/ipv4/ip4_frag.c \
+  lib/lwip/src/core/ipv6/dhcp6.c \
+  lib/lwip/src/core/ipv6/ethip6.c \
+  lib/lwip/src/core/ipv6/icmp6.c \
+  lib/lwip/src/core/ipv6/inet6.c \
+  lib/lwip/src/core/ipv6/ip6.c \
+  lib/lwip/src/core/ipv6/ip6_addr.c \
+  lib/lwip/src/core/ipv6/ip6_frag.c \
+  lib/lwip/src/core/ipv6/mld6.c \
+  lib/lwip/src/core/ipv6/nd6.c \
   lib/lwip/src/netif/ethernet.c \
   lib/lwip/src/netif/slipif.c \
   lib/lwip/src/apps/http/httpd.c \
diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h
index 5a8096f50..a215017c7 100644
--- a/examples/device/net_lwip_webserver/src/lwipopts.h
+++ b/examples/device/net_lwip_webserver/src/lwipopts.h
@@ -42,11 +42,14 @@
 #define LWIP_ICMP                       1
 #define LWIP_UDP                        1
 #define LWIP_TCP                        1
+#define LWIP_IPV4                       1
+#define LWIP_IPV6                       0
 #define ETH_PAD_SIZE                    0
 #define LWIP_IP_ACCEPT_UDP_PORT(p)      ((p) == PP_NTOHS(67))
 
 #define TCP_MSS                         (1500 /*mtu*/ - 20 /*iphdr*/ - 20 /*tcphhr*/)
 #define TCP_SND_BUF                     (2 * TCP_MSS)
+#define TCP_WND                         (TCP_MSS)
 
 #define ETHARP_SUPPORT_STATIC_ENTRIES   1
 
@@ -56,4 +59,13 @@
 
 #define LWIP_SINGLE_NETIF               1
 
+#define PBUF_POOL_SIZE                  2
+
+#define HTTPD_USE_CUSTOM_FSDATA         0
+
+#define LWIP_MULTICAST_PING             1
+#define LWIP_BROADCAST_PING             1
+#define LWIP_IPV6_MLD                   0
+#define LWIP_IPV6_SEND_ROUTER_SOLICIT   0
+
 #endif /* __LWIPOPTS_H__ */
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index a5bd2153a..30bb3577b 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -50,8 +50,11 @@ try changing the first byte of tud_network_mac_address[] below from 0x02 to 0x00
 #include "dnserver.h"
 #include "lwip/init.h"
 #include "lwip/timeouts.h"
+#include "lwip/ethip6.h"
 #include "httpd.h"
 
+#define INIT_IP4(a,b,c,d) { PP_HTONL(LWIP_MAKEU32(a,b,c,d)) }
+
 /* lwip context */
 static struct netif netif_data;
 
@@ -64,24 +67,24 @@ static struct pbuf *received_frame;
 const uint8_t tud_network_mac_address[6] = {0x02,0x02,0x84,0x6A,0x96,0x00};
 
 /* network parameters of this MCU */
-static const ip_addr_t ipaddr  = IPADDR4_INIT_BYTES(192, 168, 7, 1);
-static const ip_addr_t netmask = IPADDR4_INIT_BYTES(255, 255, 255, 0);
-static const ip_addr_t gateway = IPADDR4_INIT_BYTES(0, 0, 0, 0);
+static const ip4_addr_t ipaddr  = INIT_IP4(192, 168, 7, 1);
+static const ip4_addr_t netmask = INIT_IP4(255, 255, 255, 0);
+static const ip4_addr_t gateway = INIT_IP4(0, 0, 0, 0);
 
 /* database IP addresses that can be offered to the host; this must be in RAM to store assigned MAC addresses */
 static dhcp_entry_t entries[] =
 {
     /* mac ip address                          lease time */
-    { {0}, IPADDR4_INIT_BYTES(192, 168, 7, 2), 24 * 60 * 60 },
-    { {0}, IPADDR4_INIT_BYTES(192, 168, 7, 3), 24 * 60 * 60 },
-    { {0}, IPADDR4_INIT_BYTES(192, 168, 7, 4), 24 * 60 * 60 },
+    { {0}, INIT_IP4(192, 168, 7, 2), 24 * 60 * 60 },
+    { {0}, INIT_IP4(192, 168, 7, 3), 24 * 60 * 60 },
+    { {0}, INIT_IP4(192, 168, 7, 4), 24 * 60 * 60 },
 };
 
 static const dhcp_config_t dhcp_config =
 {
-    .router = IPADDR4_INIT_BYTES(0, 0, 0, 0),  /* router address (if any) */
+    .router = INIT_IP4(0, 0, 0, 0),            /* router address (if any) */
     .port = 67,                                /* listen port */
-    .dns = IPADDR4_INIT_BYTES(192, 168, 7, 1), /* dns server (if any) */
+    .dns = INIT_IP4(192, 168, 7, 1),           /* dns server (if any) */
     "usb",                                     /* dns suffix */
     TU_ARRAY_SIZE(entries),                    /* num entry */
     entries                                    /* entries */
@@ -108,11 +111,18 @@ static err_t linkoutput_fn(struct netif *netif, struct pbuf *p)
   }
 }
 
-static err_t output_fn(struct netif *netif, struct pbuf *p, const ip_addr_t *addr)
+static err_t ip4_output_fn(struct netif *netif, struct pbuf *p, const ip4_addr_t *addr)
 {
   return etharp_output(netif, p, addr);
 }
 
+#if LWIP_IPV6
+static err_t ip6_output_fn(struct netif *netif, struct pbuf *p, const ip6_addr_t *addr)
+{
+  return ethip6_output(netif, p, addr);
+}
+#endif
+
 static err_t netif_init_cb(struct netif *netif)
 {
   LWIP_ASSERT("netif != NULL", (netif != NULL));
@@ -122,7 +132,10 @@ static err_t netif_init_cb(struct netif *netif)
   netif->name[0] = 'E';
   netif->name[1] = 'X';
   netif->linkoutput = linkoutput_fn;
-  netif->output = output_fn;
+  netif->output = ip4_output_fn;
+#if LWIP_IPV6
+  netif->output_ip6 = ip6_output_fn;
+#endif
   return ERR_OK;
 }
 
@@ -138,11 +151,14 @@ static void init_lwip(void)
   netif->hwaddr[5] ^= 0x01;
 
   netif = netif_add(netif, &ipaddr, &netmask, &gateway, NULL, netif_init_cb, ip_input);
+#if LWIP_IPV6
+  netif_create_ip6_linklocal_address(netif, 1);
+#endif
   netif_set_default(netif);
 }
 
 /* handle any DNS requests from dns-server */
-bool dns_query_proc(const char *name, ip_addr_t *addr)
+bool dns_query_proc(const char *name, ip4_addr_t *addr)
 {
   if (0 == strcmp(name, "tiny.usb"))
   {
@@ -218,7 +234,7 @@ int main(void)
   init_lwip();
   while (!netif_is_up(&netif_data));
   while (dhserv_init(&dhcp_config) != ERR_OK);
-  while (dnserv_init(&ipaddr, 53, dns_query_proc) != ERR_OK);
+  while (dnserv_init(IP_ADDR_ANY, 53, dns_query_proc) != ERR_OK);
   httpd_init();
 
   while (1)
diff --git a/lib/networking/dhserver.c b/lib/networking/dhserver.c
index 9287858ea..590739236 100644
--- a/lib/networking/dhserver.c
+++ b/lib/networking/dhserver.c
@@ -96,19 +96,19 @@ static const dhcp_config_t *config = NULL;
 
 char magic_cookie[] = {0x63,0x82,0x53,0x63};
 
-static ip_addr_t get_ip(const uint8_t *pnt)
+static ip4_addr_t get_ip(const uint8_t *pnt)
 {
-  ip_addr_t result;
+  ip4_addr_t result;
   memcpy(&result, pnt, sizeof(result));
   return result;
 }
 
-static void set_ip(uint8_t *pnt, ip_addr_t value)
+static void set_ip(uint8_t *pnt, ip4_addr_t value)
 {
   memcpy(pnt, &value.addr, sizeof(value.addr));
 }
 
-static dhcp_entry_t *entry_by_ip(ip_addr_t ip)
+static dhcp_entry_t *entry_by_ip(ip4_addr_t ip)
 {
 	int i;
 	for (i = 0; i < config->num_entry; i++)
@@ -162,11 +162,11 @@ uint8_t *find_dhcp_option(uint8_t *attrs, int size, uint8_t attr)
 int fill_options(void *dest,
 	uint8_t msg_type,
 	const char *domain,
-	ip_addr_t dns,
+	ip4_addr_t dns,
 	int lease_time,
-	ip_addr_t serverid,
-	ip_addr_t router,
-	ip_addr_t subnet)
+	ip4_addr_t serverid,
+	ip4_addr_t router,
+	ip4_addr_t subnet)
 {
 	uint8_t *ptr = (uint8_t *)dest;
 	/* ACK message type */
diff --git a/lib/networking/dhserver.h b/lib/networking/dhserver.h
index 0d22461c7..2a0b15854 100644
--- a/lib/networking/dhserver.h
+++ b/lib/networking/dhserver.h
@@ -41,16 +41,16 @@
 
 typedef struct dhcp_entry
 {
-	uint8_t  mac[6];
-	ip_addr_t addr;
-	uint32_t lease;
+	uint8_t    mac[6];
+	ip4_addr_t addr;
+	uint32_t   lease;
 } dhcp_entry_t;
 
 typedef struct dhcp_config
 {
-	ip_addr_t     router;
+	ip4_addr_t    router;
 	uint16_t      port;
-	ip_addr_t     dns;
+	ip4_addr_t    dns;
 	const char   *domain;
 	int           num_entry;
 	dhcp_entry_t *entries;
diff --git a/lib/networking/dnserver.c b/lib/networking/dnserver.c
index 6df0bd0c4..e4e7c3492 100644
--- a/lib/networking/dnserver.c
+++ b/lib/networking/dnserver.c
@@ -136,7 +136,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const
 	dns_header_t *header;
 	static dns_query_t query;
 	struct pbuf *out;
-	ip_addr_t host_addr;
+	ip4_addr_t host_addr;
 	dns_answer_t *answer;
 
 	(void)arg;
diff --git a/lib/networking/dnserver.h b/lib/networking/dnserver.h
index 130991f5f..a062e3aa7 100644
--- a/lib/networking/dnserver.h
+++ b/lib/networking/dnserver.h
@@ -39,7 +39,7 @@
 #include "lwip/udp.h"
 #include "netif/etharp.h"
 
-typedef bool (*dns_query_proc_t)(const char *name, ip_addr_t *addr);
+typedef bool (*dns_query_proc_t)(const char *name, ip4_addr_t *addr);
 
 err_t dnserv_init(const ip_addr_t *bind, uint16_t port, dns_query_proc_t query_proc);
 void  dnserv_free(void);

From 5e437ee1861363e6b02facc5ab814abd67173680 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 22 Oct 2021 15:37:34 +0700
Subject: [PATCH 0580/2085] pi cm4 enumerated as full speed device

---
 examples/device/cdc_msc/src/tusb_config.h     |  3 +-
 src/common/tusb_common.h                      |  4 +-
 src/portable/broadcom/synopsys/dcd_synopsys.c | 59 ++++++++++++++++---
 .../broadcom/synopsys/synopsys_common.h       | 15 ++++-
 4 files changed, 69 insertions(+), 12 deletions(-)

diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index bf6af06bc..a3802f536 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -48,7 +48,8 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X || \
+       CFG_TUSB_MCU == OPT_MCU_BCM2711)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 1899b35cc..9614c12cf 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -337,8 +337,8 @@ void tu_print_var(uint8_t const* buf, uint32_t bufsize)
 #define TU_LOG1               tu_printf
 #define TU_LOG1_MEM           tu_print_mem
 #define TU_LOG1_VAR(_x)       tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
-#define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (uint32_t) (_x) )
-#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (uint32_t) (_x) )
+#define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
+#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
 
 // Log Level 2: Warn
 #if CFG_TUSB_DEBUG >= 2
diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c
index ff4ab9fb6..e70e5d4f3 100644
--- a/src/portable/broadcom/synopsys/dcd_synopsys.c
+++ b/src/portable/broadcom/synopsys/dcd_synopsys.c
@@ -110,6 +110,8 @@
 
 #include "device/dcd.h"
 
+TU_VERIFY_STATIC(sizeof(USB_OTG_GlobalTypeDef) == 0x140, "size is incorrect");
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -340,7 +342,10 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
   dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos);
 }
 
-#if defined(USB_HS_PHYC)
+#if 0
+// From CM4IO xtal to usb hub, may not be correct
+#define HSE_VALUE 24000000
+
 static bool USB_HS_PHYCInit(void)
 {
   USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
@@ -435,6 +440,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 /* Controller API
  *------------------------------------------------------------------*/
 
+TU_ATTR_UNUSED
 static void reset_core(USB_OTG_GlobalTypeDef * usb_otg) {
   while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0) {}
 
@@ -456,6 +462,46 @@ void dcd_init (uint8_t rhport)
 
   USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
 
+#if 1
+  // No VBUS sense
+  usb_otg->GCCFG &= ~(1UL << 21); // USB_OTG_GCCFG_VBDEN
+
+  // B-peripheral session valid override enable
+  usb_otg->GOTGCTL |= (1UL << 6); // USB_OTG_GOTGCTL_BVALOEN
+  usb_otg->GOTGCTL |= (1UL << 7); // USB_OTG_GOTGCTL_BVALOVAL
+
+  // Force device mode
+  usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
+  usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+
+  // deactivate internal PHY
+  usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
+
+  // Init The UTMI Interface
+  usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+
+  // Select default internal VBUS Indicator and Drive for ULPI
+  usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+
+  // Select UTMI Interface
+  usb_otg->GUSBCFG &= ~(1UL << 4); // USB_OTG_GUSBCFG_ULPI_UTMI_SEL
+  usb_otg->GCCFG |= (1UL << 32);   // USB_OTG_GCCFG_PHYHSEN
+
+  // Enables control of a High Speed USB PHY
+  //USB_HS_PHYCInit();
+
+  // Reset core after selecting PHY
+  // Wait AHB IDLE, reset then wait until it is cleared
+//  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
+//  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+//  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
+
+  reset_core(usb_otg);
+
+  // Restart PHY clock
+  *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
+
+#else
 
   // ReadBackReg(&Core->Usb);
   // Core->Usb.UlpiDriveExternalVbus = 0;
@@ -470,7 +516,7 @@ void dcd_init (uint8_t rhport)
   //   LOG_DEBUG("HCD: Interface: UTMI+.\n");
   //   Core->Usb.PhyInterface = false;
 
-  //   HcdReset();  
+  //   HcdReset();
   TU_LOG2("init phy\r\n");
   usb_otg->GUSBCFG |= (1 << 4); // bit four sets UTMI+ mode
   usb_otg->GUSBCFG &= ~(1 << 3); // bit three disables phy interface
@@ -486,12 +532,14 @@ void dcd_init (uint8_t rhport)
   // Core->Ahb.DmaRemainderMode = Incremental;
   usb_otg->GAHBCFG &= ~(1 << 23); // Remainder mode
   usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
-  
+
   //   LOG_DEBUG("HCD: HNP/SRP configuration: HNP, SRP.\n");
   //   Core->Usb.HnpCapable = true;
   //   Core->Usb.SrpCapable = true;
   usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_SRPCAP | USB_OTG_GUSBCFG_HNPCAP;
 
+#endif
+
   // Clear all interrupts
   usb_otg->GINTSTS |= usb_otg->GINTSTS;
 
@@ -506,12 +554,9 @@ void dcd_init (uint8_t rhport)
   // (non zero-length packet), send STALL back and discard.
   dev->DCFG |=  USB_OTG_DCFG_NZLSOHSK;
 
-  #if TUD_OPT_HIGH_SPEED
   set_speed(rhport, TUSB_SPEED_HIGH);
-  #else
-  set_speed(rhport, TUSB_SPEED_FULL);
-  #endif
 
+  // TODO internal phy (full speed)
   usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
 
   usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST   | USB_OTG_GINTMSK_ENUMDNEM |
diff --git a/src/portable/broadcom/synopsys/synopsys_common.h b/src/portable/broadcom/synopsys/synopsys_common.h
index 6f0602fe9..2ec6f4487 100644
--- a/src/portable/broadcom/synopsys/synopsys_common.h
+++ b/src/portable/broadcom/synopsys/synopsys_common.h
@@ -60,12 +60,23 @@ typedef struct
   __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg        Address offset: 02Ch */
   uint32_t Reserved30[2];             /*!< Reserved 030h*/
   __IO uint32_t GCCFG;                /*!< General Purpose IO Register                Address offset: 038h */
-  __IO uint32_t CID;                  /*!< User ID Register                           Address offset: 03Ch */
-  uint32_t  Reserved40[48];           /*!< Reserved 040h-0FFh */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
   __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg             Address offset: 100h */
   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                 Address offset: 0x104 */
 } USB_OTG_GlobalTypeDef;
 
+
+
 /** 
   * @brief __device_Registers
   */

From 35b62810c3a4b8e2924109905334f054425f16ba Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Fri, 22 Oct 2021 09:00:09 -0700
Subject: [PATCH 0581/2085] Update submodule

---
 cortex-a.py                                   | 157 ------------------
 hw/mcu/broadcom                               |   2 +-
 src/portable/broadcom/synopsys/dcd_synopsys.c |  10 +-
 .../broadcom/synopsys/synopsys_common.h       |   6 +-
 4 files changed, 10 insertions(+), 165 deletions(-)
 delete mode 100644 cortex-a.py

diff --git a/cortex-a.py b/cortex-a.py
deleted file mode 100644
index 9de16bae9..000000000
--- a/cortex-a.py
+++ /dev/null
@@ -1,157 +0,0 @@
-class Armv8AException(gdb.Command):
-    def __init__ (self):
-        super (Armv8AException, self).__init__ ("armv8a-exception", gdb.COMMAND_USER)
-    
-    def print_data_abort(self, frame, iss):
-        isv = (iss >> 23) & 0x1
-        sas = (iss >> 21) & 0x3
-        sse = (iss >> 20) & 0x1
-        srt = (iss >> 15) & 0x1f
-        sf = (iss >> 14) & 0x1
-        ar = (iss >> 13) & 0x1
-        vncr = (iss >> 12) & 0x1
-        _set = (iss >> 10) & 0x3
-        fnv = (iss >> 9) & 0x1
-        ea = (iss >> 8) & 0x1
-        cm = (iss >> 7) & 0x1
-        s1ptw = (iss >> 6) & 0x1
-        wnr = (iss >> 5) & 0x1
-        dfsc = iss & 0x1f
-        if isv:
-            # print("isv valid", sas, sse, srt, sf, ar)
-            access_sizes = ("Byte", "Halfword", "Word", "Doubleword")
-            print("Access size:", access_sizes[sas])
-            print("Sign extended:", "Yes" if sse else "No")
-            print("Register:", hex(srt), "64-bit" if sf else "32-bit")
-            print("Acquire/Release:", "Yes" if ar else "No")
-        if dfsc == 0b010000:
-            print("Not on translation table walk")
-            if not fnv:
-                value = int(frame.read_register("FAR_EL2"))
-                print("FAR", hex(value))
-        elif dfsc == 0b000101:
-            print("translation fault level 1")
-        elif dfsc == 0b010001:
-            print("tag check fault")
-        elif dfsc == 0b100001:
-            print("alignment fault")
-        else:
-            print(bin(dfsc))
-        print(vncr, _set, fnv, ea, cm, s1ptw, wnr, dfsc)
-
-    def print_instruction_abort(self, frame, iss):
-        _set = (iss >> 10) & 0x3
-        fnv = (iss >> 9) & 0x1
-        ea = (iss >> 8) & 0x1
-        s1ptw = (iss >> 6) & 0x1
-        ifsc = iss & 0x1f
-        if ifsc == 0b010000:
-            print("Not on translation table walk")
-            if not fnv:
-                value = int(frame.read_register("FAR_EL2"))
-                print("FAR", hex(value))
-        elif ifsc == 0b00101:
-            print("translation fault level 1")
-        elif ifsc == 0b01001:
-            print("access flag fault level 1")
-        # elif dfsc == 0b100001:
-        #     print("alignment fault")
-        else:
-            print(bin(ifsc))
-
-    def invoke (self, arg, from_tty):
-        frame = gdb.selected_frame()
-        value = int(frame.read_register("ESR_EL2"))
-        if value == 0:
-            return None
-        iss2 = (value >> 32) & 0x1ff
-        ec = (value >> 26) & 0x3ff
-        il = (value >> 25) & 0x1
-        iss = value & 0xffffff
-        if ec == 0b000000:
-            print("Unknown fault")
-        elif ec == 0b000001:
-            print("Trapped WF*")
-        elif ec == 0b000011:
-            print("Trapped MCR or MRC")
-        elif ec == 0b000100:
-            print("Trapped MCRR or MRRC")
-        elif ec == 0b000101:
-            print("Trapped MCR or MRC")
-        elif ec == 0b000110:
-            print("Trapped LDC or STC")
-        elif ec == 0b000111:
-            print("Trapped SIMD")
-        elif ec == 0b001000:
-            print("Trapped VMRS")
-        elif ec == 0b001001:
-            print("Trapped pointer authentication")
-        elif ec == 0b001010:
-            print("Trapped LD64B or ST64B*")
-        elif ec == 0b001100:
-            print("Trapped MRRC")
-        elif ec == 0b001101:
-            print("Branch target exception")
-        elif ec == 0b001110:
-            print("Illegal execution state")
-        elif ec == 0b010001:
-            print("SVC instruction")
-        elif ec == 0b010010:
-            print("HVC instruction")
-        elif ec == 0b010011:
-            print("SMC instruction")
-        elif ec == 0b010101:
-            print("SVC instruction")
-        elif ec == 0b010110:
-            print("HVC instruction")
-        elif ec == 0b010111:
-            print("SMC instruction")
-        elif ec == 0b011000:
-            print("Trapped MRS, MRS or system instruction")
-        elif ec == 0b011001:
-            print("Trapped SVE")
-        elif ec == 0b011010:
-            print("Trapped ERET")
-        elif ec == 0b011100:
-            print("Failed pointer authentication")
-        elif ec == 0b100000:
-            print("Instruction abort from lower level")
-        elif ec == 0b100001:
-            print("Instruction abort from same level")
-            self.print_instruction_abort(frame, iss)
-        elif ec == 0b100010:
-            print("PC alignment failure")
-        elif ec == 0b100100:
-            print("Data abort from lower level")
-        elif ec == 0b100101:
-            print("Data abort from same level")
-            self.print_data_abort(frame, iss)
-        elif ec == 0b100110:
-            print("SP alignment fault")
-        elif ec == 0b101000:
-            print("32-bit floating point exception")
-        elif ec == 0b101100:
-            print("64-bit floating point exception")
-        elif ec == 0b101111:
-            print("SError interrupt")
-        elif ec == 0b110000:
-            print("Breakpoint from lower level")
-        elif ec == 0b110001:
-            print("Breakpoint from same level")
-        elif ec == 0b110010:
-            print("Software step from lower level")
-        elif ec == 0b110011:
-            print("Software step from same level")
-        elif ec == 0b110100:
-            print ("Watch point from same level")
-        elif ec == 0b110101:
-            print("Watch point from lower level")
-        elif ec == 0b111000:
-            print("Breakpoint in aarch32 mode")
-        elif ec == 0b111010:
-            print("Vector catch in aarch32")
-        elif ec == 0b111100:
-            print("Brk instruction in aarch64")
-        print(hex(int(value)), iss2, bin(ec), il, iss)
-
-Armv8AException()
diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom
index e5343acda..7a8f4b747 160000
--- a/hw/mcu/broadcom
+++ b/hw/mcu/broadcom
@@ -1 +1 @@
-Subproject commit e5343acdad77b8cf4a8d09b732a11ecef17d148a
+Subproject commit 7a8f4b7471ad4aad2e808b3a4cc88b4c23b529f2
diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c
index e70e5d4f3..32cfd6d2a 100644
--- a/src/portable/broadcom/synopsys/dcd_synopsys.c
+++ b/src/portable/broadcom/synopsys/dcd_synopsys.c
@@ -31,6 +31,8 @@
 
 #include "synopsys_common.h"
 
+#include "broadcom/interrupts.h"
+
 // Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
 // We disable SOF for now until needed later on
 #define USE_SOF     0
@@ -116,10 +118,10 @@ TU_VERIFY_STATIC(sizeof(USB_OTG_GlobalTypeDef) == 0x140, "size is incorrect");
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#define RHPORT_REGS_BASE 0xfe980000
+#define RHPORT_REGS_BASE USB_OTG_GLOBAL_BASE
 
 #define GLOBAL_BASE(_port)     ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE)
-#define DEVICE_BASE(_port)     (USB_OTG_DeviceTypeDef *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE)
+#define DEVICE_BASE(_port)     (USB_OTG_DeviceTypeDef *) (USB_OTG_DEVICE_BASE)
 #define OUT_EP_BASE(_port)     (USB_OTG_OUTEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE)
 #define IN_EP_BASE(_port)      (USB_OTG_INEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE)
 #define FIFO_BASE(_port, _x)   ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
@@ -572,13 +574,13 @@ void dcd_init (uint8_t rhport)
 void dcd_int_enable (uint8_t rhport)
 {
   (void) rhport;
-  // NVIC_EnableIRQ(RHPORT_IRQn);
+  // BP_EnableIRQ(USB_IRQn);
 }
 
 void dcd_int_disable (uint8_t rhport)
 {
   (void) rhport;
-  // NVIC_DisableIRQ(RHPORT_IRQn);
+  // BP_DisableIRQ(USB_IRQn);
 }
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
diff --git a/src/portable/broadcom/synopsys/synopsys_common.h b/src/portable/broadcom/synopsys/synopsys_common.h
index 2ec6f4487..81ce3b4a9 100644
--- a/src/portable/broadcom/synopsys/synopsys_common.h
+++ b/src/portable/broadcom/synopsys/synopsys_common.h
@@ -169,12 +169,12 @@ typedef struct
 /*!< USB registers base address */
 #define USB_OTG_FS_PERIPH_BASE               0x50000000UL
 
-#define USB_OTG_GLOBAL_BASE                  0x00000000UL
-#define USB_OTG_DEVICE_BASE                  0x00000800UL
+// #define USB_OTG_GLOBAL_BASE                  0x00000000UL
+// #define USB_OTG_DEVICE_BASE                  0x00000800UL
 #define USB_OTG_IN_ENDPOINT_BASE             0x00000900UL
 #define USB_OTG_OUT_ENDPOINT_BASE            0x00000B00UL
 #define USB_OTG_EP_REG_SIZE                  0x00000020UL
-#define USB_OTG_HOST_BASE                    0x00000400UL
+// #define USB_OTG_HOST_BASE                    0x00000400UL
 #define USB_OTG_HOST_PORT_BASE               0x00000440UL
 #define USB_OTG_HOST_CHANNEL_BASE            0x00000500UL
 #define USB_OTG_HOST_CHANNEL_SIZE            0x00000020UL

From 2ef200003d06f8e3f19e713cfbc38f474491d4d8 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Fri, 22 Oct 2021 09:31:24 -0700
Subject: [PATCH 0582/2085] Update broadcom library

---
 hw/mcu/broadcom                               | 2 +-
 src/portable/broadcom/synopsys/dcd_synopsys.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom
index 7a8f4b747..55cd6f798 160000
--- a/hw/mcu/broadcom
+++ b/hw/mcu/broadcom
@@ -1 +1 @@
-Subproject commit 7a8f4b7471ad4aad2e808b3a4cc88b4c23b529f2
+Subproject commit 55cd6f798a45cac905d7bf81baa2bcbf7de7c42e
diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c
index 32cfd6d2a..87150f683 100644
--- a/src/portable/broadcom/synopsys/dcd_synopsys.c
+++ b/src/portable/broadcom/synopsys/dcd_synopsys.c
@@ -574,13 +574,13 @@ void dcd_init (uint8_t rhport)
 void dcd_int_enable (uint8_t rhport)
 {
   (void) rhport;
-  // BP_EnableIRQ(USB_IRQn);
+  BP_EnableIRQ(USB_IRQn);
 }
 
 void dcd_int_disable (uint8_t rhport)
 {
   (void) rhport;
-  // BP_DisableIRQ(USB_IRQn);
+  BP_DisableIRQ(USB_IRQn);
 }
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)

From 07c74c76d0bf420c63757af2b66838090c2fd9d3 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Sat, 23 Oct 2021 13:43:46 -0400
Subject: [PATCH 0583/2085] msp430x5xx: Set base of transmit_packet buffer
 earlier to avoid incrementing past unsent data.

---
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index ee85f0a77..6830fd1fa 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -547,6 +547,7 @@ static void transmit_packet(uint8_t ep_num)
   }
 
   // Then actually commit to transmit a packet.
+  uint8_t * base = (xfer->buffer + xfer->queued_len);
   uint16_t remaining = xfer->total_len - xfer->queued_len;
   uint8_t xfer_size = (xfer->max_size < xfer->total_len) ? xfer->max_size : remaining;
 
@@ -560,7 +561,6 @@ static void transmit_packet(uint8_t ep_num)
   if(ep_num == 0)
   {
     volatile uint8_t * ep0in_buf = &USBIEP0BUF;
-    uint8_t * base = (xfer->buffer + xfer->queued_len);
     for(uint16_t i = 0; i < xfer_size; i++)
     {
       ep0in_buf[i] = base[i];
@@ -582,7 +582,6 @@ static void transmit_packet(uint8_t ep_num)
     else
 #endif
     {
-      uint8_t * base = (xfer->buffer + xfer->queued_len);
       for(int i = 0; i < xfer_size; i++)
       {
         ep_buf[i] = base[i];

From 6f5b197a98545c70efeeb4adcad0d41a3d30a57c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 24 Oct 2021 08:44:58 +0700
Subject: [PATCH 0584/2085] indent

---
 src/class/usbtmc/usbtmc_device.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 86495e3fa..6c916d2f3 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -522,21 +522,21 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
     case STATE_TX_INITIATED:
       if(usbtmc_state.transfer_size_remaining >=sizeof(usbtmc_state.ep_bulk_in_buf))
       {
-          // FIXME! This removes const below!
-          TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in,
-              (void*)(uintptr_t) usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf)));
-          usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf);
-          usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf);
-          usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf);
+        // FIXME! This removes const below!
+        TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in,
+            (void*)(uintptr_t) usbtmc_state.devInBuffer, sizeof(usbtmc_state.ep_bulk_in_buf)));
+        usbtmc_state.devInBuffer += sizeof(usbtmc_state.ep_bulk_in_buf);
+        usbtmc_state.transfer_size_remaining -= sizeof(usbtmc_state.ep_bulk_in_buf);
+        usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.ep_bulk_in_buf);
       }
       else // last packet
       {
-      size_t packetLen = usbtmc_state.transfer_size_remaining;
-      memcpy(usbtmc_state.ep_bulk_in_buf, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining);
-        usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.transfer_size_remaining);
-      usbtmc_state.transfer_size_remaining = 0;
-      usbtmc_state.devInBuffer = NULL;
-      TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf,(uint16_t)packetLen));
+        size_t packetLen = usbtmc_state.transfer_size_remaining;
+        memcpy(usbtmc_state.ep_bulk_in_buf, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining);
+          usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.transfer_size_remaining);
+        usbtmc_state.transfer_size_remaining = 0;
+        usbtmc_state.devInBuffer = NULL;
+        TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf, (uint16_t)packetLen) );
         if(((packetLen % USBTMCD_MAX_PACKET_SIZE) != 0) || (packetLen == 0 ))
         {
           usbtmc_state.state = STATE_TX_SHORTED;

From 5af989384bd95dbf16f824bcc48e56f3ea283080 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 24 Oct 2021 13:11:21 +0700
Subject: [PATCH 0585/2085] remove ep descriptor wMaxPacketSize bitfield due to
 endian issue

---
 CONTRIBUTORS.rst                              |  2 +-
 src/class/audio/audio_device.c                | 15 ++++----
 src/class/bth/bth_device.c                    |  8 ++---
 src/class/hid/hid_host.c                      |  2 +-
 src/class/usbtmc/usbtmc_device.c              |  2 +-
 src/class/video/video_device.c                |  6 ++--
 src/common/tusb_common.h                      | 21 +++++------
 src/common/tusb_types.h                       | 35 +++++++++----------
 src/host/usbh.c                               |  2 +-
 src/portable/dialog/da146xx/dcd_da146xx.c     |  2 +-
 src/portable/ehci/ehci.c                      |  2 +-
 src/portable/espressif/esp32sx/dcd_esp32sx.c  |  7 ++--
 src/portable/microchip/samd/dcd_samd.c        |  4 +--
 src/portable/microchip/samg/dcd_samg.c        |  2 +-
 src/portable/microchip/samx7x/dcd_samx7x.c    |  2 +-
 .../mindmotion/mm32/dcd_mm32f327x_otg.c       |  2 +-
 src/portable/nordic/nrf5x/dcd_nrf5x.c         |  2 +-
 src/portable/nuvoton/nuc120/dcd_nuc120.c      |  2 +-
 src/portable/nuvoton/nuc121/dcd_nuc121.c      |  2 +-
 src/portable/nuvoton/nuc505/dcd_nuc505.c      |  2 +-
 src/portable/nxp/khci/dcd_khci.c              |  2 +-
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c      |  5 +--
 .../nxp/transdimension/dcd_transdimension.c   |  2 +-
 src/portable/ohci/ohci.c                      |  2 +-
 src/portable/raspberrypi/rp2040/dcd_rp2040.c  |  2 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c  |  2 +-
 src/portable/renesas/usba/dcd_usba.c          |  2 +-
 src/portable/silabs/efm32/dcd_efm32.c         |  7 ++--
 src/portable/sony/cxd56/dcd_cxd56.c           |  8 +++--
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 12 +++----
 src/portable/st/synopsys/dcd_synopsys.c       |  8 ++---
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c   |  4 +--
 src/tusb.c                                    |  2 +-
 33 files changed, 90 insertions(+), 90 deletions(-)

diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index 55a291222..e3186f086 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -110,7 +110,7 @@ Notable contributors
 `Rafael Silva <https://github.com/perigoso>`__
 ----------------------------------------------
 
--  Add new DCD port for Silabs EFM32GG12 with SLTB009A board
+-  Port DCD Synopsys to support Silabs EFM32GG12 with SLTB009A board
 -  Rewrite documentation in rst and setup for readthedocs
 
 
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index e16771cd3..28b1c1a7c 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1569,20 +1569,21 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
       {
         if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
         {
-          TU_ASSERT(usbd_edpt_open(rhport, (tusb_desc_endpoint_t const *)p_desc));
+          tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+          TU_ASSERT(usbd_edpt_open(rhport, desc_ep));
 
-          uint8_t ep_addr = ((tusb_desc_endpoint_t const *) p_desc)->bEndpointAddress;
+          uint8_t const ep_addr = desc_ep->bEndpointAddress;
 
           //TODO: We need to set EP non busy since this is not taken care of right now in ep_close() - THIS IS A WORKAROUND!
           usbd_edpt_clear_stall(rhport, ep_addr);
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
-          if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && ((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.usage == 0x00)   // Check if usage is data EP
+          if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 0x00)   // Check if usage is data EP
           {
             // Save address
             audio->ep_in = ep_addr;
             audio->ep_in_as_intf_num = itf;
-            audio->ep_in_sz = ((tusb_desc_endpoint_t const *) p_desc)->wMaxPacketSize.size;
+            audio->ep_in_sz = tu_edpt_packet_size(desc_ep);
 
             // If software encoding is enabled, parse for the corresponding parameters - doing this here means only AS interfaces with EPs get scanned for parameters
 #if CFG_TUD_AUDIO_ENABLE_ENCODING
@@ -1616,7 +1617,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             // Save address
             audio->ep_out = ep_addr;
             audio->ep_out_as_intf_num = itf;
-            audio->ep_out_sz = ((tusb_desc_endpoint_t const *) p_desc)->wMaxPacketSize.size;
+            audio->ep_out_sz = tu_edpt_packet_size(desc_ep);
 
 #if CFG_TUD_AUDIO_ENABLE_DECODING
             audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf);
@@ -1635,7 +1636,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
             // In case of asynchronous EP, call Cb after ep_fb is set
-            if (!(((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.sync == 0x01 && audio->ep_fb == 0))
+            if ( !(desc_ep->bmAttributes.sync == 0x01 && audio->ep_fb == 0) )
             {
               if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
             }
@@ -1652,7 +1653,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
           }
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-          if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && ((tusb_desc_endpoint_t const *) p_desc)->bmAttributes.usage == 1)   // Check if usage is explicit data feedback
+          if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1)   // Check if usage is explicit data feedback
           {
             audio->ep_fb = ep_addr;
 
diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index b73f829cc..f445deed2 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -142,14 +142,14 @@ uint16_t btd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_
     dir = tu_edpt_dir(desc_ep->bEndpointAddress);
     _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress;
     // Store endpoint size for alternative
-    _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t)desc_ep->wMaxPacketSize.size;
+    _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep);
 
     desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep);
     TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT, 0);
     dir = tu_edpt_dir(desc_ep->bEndpointAddress);
     _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress;
     // Store endpoint size for alternative
-    _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t)desc_ep->wMaxPacketSize.size;
+    _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep);
     drv_len += iso_alt_itf_size;
 
     for (int i = 1; i < CFG_TUD_BTH_ISO_ALT_COUNT && drv_len + iso_alt_itf_size <= max_len; ++i) {
@@ -170,14 +170,14 @@ uint16_t btd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_
       // Verify that alternative endpoint are same as first ones
       TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT &&
                 _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0);
-      _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t)desc_ep->wMaxPacketSize.size;
+      _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep);
 
       desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep);
       dir = tu_edpt_dir(desc_ep->bEndpointAddress);
       // Verify that alternative endpoint are same as first ones
       TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT &&
                 _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0);
-      _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t)desc_ep->wMaxPacketSize.size;
+      _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep);
       drv_len += iso_alt_itf_size;
     }
   }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index ac260d39b..f19f1ba81 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -307,7 +307,7 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
 
   hid_itf->itf_num   = desc_itf->bInterfaceNumber;
   hid_itf->ep_in     = desc_ep->bEndpointAddress;
-  hid_itf->epin_size = desc_ep->wMaxPacketSize.size;
+  hid_itf->epin_size = tu_edpt_packet_size(desc_ep);
 
   // Assume bNumDescriptors = 1
   hid_itf->report_desc_type = desc_hid->bReportType;
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 6c916d2f3..4bd1edf12 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -280,7 +280,7 @@ uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
       tusb_desc_endpoint_t const *ep_desc = (tusb_desc_endpoint_t const *)p_desc;
       switch(ep_desc->bmAttributes.xfer) {
         case TUSB_XFER_BULK:
-          TU_ASSERT(ep_desc->wMaxPacketSize.size == USBTMCD_MAX_PACKET_SIZE, 0);
+          TU_ASSERT(tu_edpt_packet_size(ep_desc) == USBTMCD_MAX_PACKET_SIZE, 0);
           if (tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN)
           {
             usbtmc_state.ep_bulk_in = ep_desc->bEndpointAddress;
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index d9bd44f61..eeb068197 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -582,11 +582,11 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     TU_ASSERT(cur < end);
     tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur;
     if (!stm->max_payload_transfer_size) {
-      video_probe_and_commit_control_t const *param =
-        (video_probe_and_commit_control_t const*)&stm->ep_buf;
+      video_probe_and_commit_control_t const *param = (video_probe_and_commit_control_t const*)&stm->ep_buf;
       uint_fast32_t max_size = param->dwMaxPayloadTransferSize;
       if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) &&
-          (ep->wMaxPacketSize.size < max_size)) {
+          (tu_edpt_packet_size(ep) < max_size))
+      {
         /* FS must be less than or equal to max packet size */
         return false;
       }
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 8dd1dbd49..fc92654b7 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -38,20 +38,21 @@
 #define TU_MIN(_x, _y)        ( ( (_x) < (_y) ) ? (_x) : (_y) )
 #define TU_MAX(_x, _y)        ( ( (_x) > (_y) ) ? (_x) : (_y) )
 
-#define TU_U16_HIGH(_u16)      ((uint8_t) (((_u16) >> 8) & 0x00ff))
-#define TU_U16_LOW(_u16)       ((uint8_t) ((_u16)       & 0x00ff))
-#define U16_TO_U8S_BE(_u16)    TU_U16_HIGH(_u16), TU_U16_LOW(_u16)
-#define U16_TO_U8S_LE(_u16)    TU_U16_LOW(_u16), TU_U16_HIGH(_u16)
+#define TU_U16_HIGH(_u16)     ((uint8_t) (((_u16) >> 8) & 0x00ff))
+#define TU_U16_LOW(_u16)      ((uint8_t) ((_u16)       & 0x00ff))
+#define U16_TO_U8S_BE(_u16)   TU_U16_HIGH(_u16), TU_U16_LOW(_u16)
+#define U16_TO_U8S_LE(_u16)   TU_U16_LOW(_u16), TU_U16_HIGH(_u16)
 
-#define TU_U32_BYTE3(_u32)     ((uint8_t) ((((uint32_t) _u32) >> 24) & 0x000000ff)) // MSB
-#define TU_U32_BYTE2(_u32)     ((uint8_t) ((((uint32_t) _u32) >> 16) & 0x000000ff))
-#define TU_U32_BYTE1(_u32)     ((uint8_t) ((((uint32_t) _u32) >>  8) & 0x000000ff))
-#define TU_U32_BYTE0(_u32)     ((uint8_t) (((uint32_t)  _u32)        & 0x000000ff)) // LSB
+#define TU_U32_BYTE3(_u32)    ((uint8_t) ((((uint32_t) _u32) >> 24) & 0x000000ff)) // MSB
+#define TU_U32_BYTE2(_u32)    ((uint8_t) ((((uint32_t) _u32) >> 16) & 0x000000ff))
+#define TU_U32_BYTE1(_u32)    ((uint8_t) ((((uint32_t) _u32) >>  8) & 0x000000ff))
+#define TU_U32_BYTE0(_u32)    ((uint8_t) (((uint32_t)  _u32)        & 0x000000ff)) // LSB
 
-#define U32_TO_U8S_BE(_u32)    TU_U32_BYTE3(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE0(_u32)
-#define U32_TO_U8S_LE(_u32)    TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32)
+#define U32_TO_U8S_BE(_u32)   TU_U32_BYTE3(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE0(_u32)
+#define U32_TO_U8S_LE(_u32)   TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32)
 
 #define TU_BIT(n)             (1UL << (n))
+#define TU_GENMASK(h, l)      ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) )
 
 //--------------------------------------------------------------------+
 // Includes
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 897e89b39..233def466 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -349,32 +349,24 @@ TU_VERIFY_STATIC( sizeof(tusb_desc_interface_t) == 9, "size is not correct");
 /// USB Endpoint Descriptor
 typedef struct TU_ATTR_PACKED
 {
-  uint8_t  bLength          ; ///< Size of this descriptor in bytes
-  uint8_t  bDescriptorType  ; ///< ENDPOINT Descriptor Type
+  uint8_t  bLength          ; // Size of this descriptor in bytes
+  uint8_t  bDescriptorType  ; // ENDPOINT Descriptor Type
 
-  uint8_t  bEndpointAddress ; ///< The address of the endpoint on the USB device described by this descriptor. The address is encoded as follows: \n Bit 3...0: The endpoint number \n Bit 6...4: Reserved, reset to zero \n Bit 7: Direction, ignored for control endpoints 0 = OUT endpoint 1 = IN endpoint.
+  uint8_t  bEndpointAddress ; // The address of the endpoint
 
   struct TU_ATTR_PACKED {
-    uint8_t xfer  : 2;
-    uint8_t sync  : 2;
-    uint8_t usage : 2;
+    uint8_t xfer  : 2;        // Control, ISO, Bulk, Interrupt
+    uint8_t sync  : 2;        // None, Asynchronous, Adaptive, Synchronous
+    uint8_t usage : 2;        // Data, Feedback, Implicit feedback
     uint8_t       : 2;
-  } bmAttributes     ; ///< This field describes the endpoint's attributes when it is configured using the bConfigurationValue. \n Bits 1..0: Transfer Type \n- 00 = Control \n- 01 = Isochronous \n- 10 = Bulk \n- 11 = Interrupt \n If not an isochronous endpoint, bits 5..2 are reserved and must be set to zero. If isochronous, they are defined as follows: \n Bits 3..2: Synchronization Type \n- 00 = No Synchronization \n- 01 = Asynchronous \n- 10 = Adaptive \n- 11 = Synchronous \n Bits 5..4: Usage Type \n- 00 = Data endpoint \n- 01 = Feedback endpoint \n- 10 = Implicit feedback Data endpoint \n- 11 = Reserved \n Refer to Chapter 5 of USB 2.0 specification for more information. \n All other bits are reserved and must be reset to zero. Reserved bits must be ignored by the host.
+  } bmAttributes;
 
-  struct TU_ATTR_PACKED {
-#if defined(__CCRX__)
-    //FIXME the original defined bit field has a problem with the CCRX toolchain, so only a size field is defined
-    uint16_t size;
-#else
-    uint16_t size           : 11; ///< Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. \n For isochronous endpoints, this value is used to reserve the bus time in the schedule, required for the per-(micro)frame data payloads. The pipe may, on an ongoing basis, actually use less bandwidth than that reserved. The device reports, if necessary, the actual bandwidth used via its normal, non-USB defined mechanisms. \n For all endpoints, bits 10..0 specify the maximum packet size (in bytes). \n For high-speed isochronous and interrupt endpoints: \n Bits 12..11 specify the number of additional transaction opportunities per microframe: \n- 00 = None (1 transaction per microframe) \n- 01 = 1 additional (2 per microframe) \n- 10 = 2 additional (3 per microframe) \n- 11 = Reserved \n Bits 15..13 are reserved and must be set to zero.
-    uint16_t hs_period_mult : 2;
-    uint16_t TU_RESERVED    : 3;
-#endif
-  }wMaxPacketSize;
-
-  uint8_t  bInterval        ; ///< Interval for polling endpoint for data transfers. Expressed in frames or microframes depending on the device operating speed (i.e., either 1 millisecond or 125 us units). \n- For full-/high-speed isochronous endpoints, this value must be in the range from 1 to 16. The bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \n- For full-/low-speed interrupt endpoints, the value of this field may be from 1 to 255. \n- For high-speed interrupt endpoints, the bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value must be from 1 to 16. \n- For high-speed bulk/control OUT endpoints, the bInterval must specify the maximum NAK rate of the endpoint. A value of 0 indicates the endpoint never NAKs. Other values indicate at most 1 NAK each bInterval number of microframes. This value must be in the range from 0 to 255. \n Refer to Chapter 5 of USB 2.0 specification for more information.
+  uint16_t wMaxPacketSize   ; // Bit 10..0 : max packet size, bit 12..11 additional transaction per highspeed micro-frame
+  uint8_t  bInterval        ; // Polling interval, in frames or microframes depending on the operating speed
 } tusb_desc_endpoint_t;
 
+TU_VERIFY_STATIC( sizeof(tusb_desc_endpoint_t) == 7, "size is not correct");
+
 /// USB Other Speed Configuration Descriptor
 typedef struct TU_ATTR_PACKED
 {
@@ -521,6 +513,11 @@ static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir)
   return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0));
 }
 
+static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep)
+{
+  return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0);
+}
+
 //--------------------------------------------------------------------+
 // Descriptor helper
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index a9c2c201f..f74e7114c 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1172,7 +1172,7 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
     .bDescriptorType  = TUSB_DESC_ENDPOINT,
     .bEndpointAddress = 0,
     .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-    .wMaxPacketSize   = { .size = max_packet_size },
+    .wMaxPacketSize   = max_packet_size,
     .bInterval        = 0
   };
 
diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index c9d1d9b3c..51957829f 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -914,7 +914,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 
   TU_ASSERT(epnum < EP_MAX);
 
-  xfer->max_packet_size = desc_edpt->wMaxPacketSize.size;
+  xfer->max_packet_size = tu_edpt_packet_size(desc_edpt);
   xfer->ep_addr = desc_edpt->bEndpointAddress;
   xfer->data1 = 0;
   xfer->iso = 0;
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 18ddaf31a..e92f8a951 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -802,7 +802,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
   p_qhd->ep_speed           = devtree_info.speed;
   p_qhd->data_toggle_control= (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0;
   p_qhd->head_list_flag     = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static asyn list head
-  p_qhd->max_packet_size    = ep_desc->wMaxPacketSize.size;
+  p_qhd->max_packet_size    = tu_edpt_packet_size(ep_desc);
   p_qhd->fl_ctrl_ep_flag    = ((xfer_type == TUSB_XFER_CONTROL) && (p_qhd->ep_speed != TUSB_SPEED_HIGH))  ? 1 : 0;
   p_qhd->nak_reload         = 0;
 
diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index cfbbab233..c27fc2922 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -256,17 +256,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
   uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
   uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
 
-  TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64);
   TU_ASSERT(epnum < EP_MAX);
 
   xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = desc_edpt->wMaxPacketSize.size;
+  xfer->max_size = tu_edpt_packet_size(desc_edpt);
 
   if (dir == TUSB_DIR_OUT) {
     out_ep[epnum].doepctl |= USB_USBACTEP1_M |
                              desc_edpt->bmAttributes.xfer << USB_EPTYPE1_S |
                              (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_DO_SETD0PID1_M : 0) |
-                             desc_edpt->wMaxPacketSize.size << USB_MPS1_S;
+                             xfer->max_size << USB_MPS1_S;
     USB0.daintmsk |= (1 << (16 + epnum));
   } else {
     // "USB Data FIFOs" section in reference manual
@@ -300,7 +299,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
                             fifo_num << USB_D_TXFNUM1_S |
                             desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S |
                             (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) |
-                            desc_edpt->wMaxPacketSize.size << 0;
+                            xfer->max_size << 0;
 
     USB0.daintmsk |= (1 << (0 + epnum));
 
diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index 526a6fb63..46aabc5aa 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -214,14 +214,14 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   UsbDeviceDescBank* bank = &sram_registers[epnum][dir];
   uint32_t size_value = 0;
   while (size_value < 7) {
-    if (1 << (size_value + 3) == desc_edpt->wMaxPacketSize.size) {
+    if (1 << (size_value + 3) == tu_edpt_packet_size(desc_edpt)) {
       break;
     }
     size_value++;
   }
 
   // unsupported endpoint size
-  if ( size_value == 7 && desc_edpt->wMaxPacketSize.size != 1023 ) return false;
+  if ( size_value == 7 && tu_edpt_packet_size(desc_edpt) != 1023 ) return false;
 
   bank->PCKSIZE.bit.SIZE = size_value;
 
diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c
index 81779c56b..2e9854153 100644
--- a/src/portable/microchip/samg/dcd_samg.c
+++ b/src/portable/microchip/samg/dcd_samg.c
@@ -258,7 +258,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   // Must not already enabled
   TU_ASSERT((UDP->UDP_CSR[epnum] & UDP_CSR_EPEDS_Msk) == 0);
 
-  xfer_epsize_set(&_dcd_xfer[epnum], ep_desc->wMaxPacketSize.size);
+  xfer_epsize_set(&_dcd_xfer[epnum], tu_edpt_packet_size(ep_desc));
 
   // Configure type and enable EP
   csr_write(epnum, UDP_CSR_EPEDS_Msk | UDP_CSR_EPTYPE(ep_desc->bmAttributes.xfer + 4*dir));
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 032547e47..d716e8fed 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -460,7 +460,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   (void) rhport;
   uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(ep_desc->bEndpointAddress);
-  uint16_t const epMaxPktSize = ep_desc->wMaxPacketSize.size;
+  uint16_t const epMaxPktSize = tu_edpt_packet_size(ep_desc);
   tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
   uint8_t fifoSize = 0;                       // FIFO size
   uint16_t defaultEndpointSize = 8;           // Default size of Endpoint
diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
index 6cc0fcac3..a3b69b987 100644
--- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -323,7 +323,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   /* No support for control transfer */
   TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
 
-  ep->max_packet_size = ep_desc->wMaxPacketSize.size;
+  ep->max_packet_size = tu_edpt_packet_size(ep_desc);
   unsigned val = USB_ENDPT_EPCTLDIS_MASK;
   val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
   val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 06f23f8a5..9d7db11b2 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -311,7 +311,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   uint8_t const epnum   = tu_edpt_number(ep_addr);
   uint8_t const dir     = tu_edpt_dir(ep_addr);
 
-  _dcd.xfer[epnum][dir].mps = desc_edpt->wMaxPacketSize.size;
+  _dcd.xfer[epnum][dir].mps = tu_edpt_packet_size(desc_edpt);
 
   if (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS)
   {
diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c
index 7618f288d..0d45090d1 100644
--- a/src/portable/nuvoton/nuc120/dcd_nuc120.c
+++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c
@@ -251,7 +251,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 
   /* mine the data for the information we need */
   int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  int const size = p_endpoint_desc->wMaxPacketSize.size;
+  int const size = tu_edpt_packet_size(p_endpoint_desc);
   tusb_xfer_type_t const type = (tusb_xfer_type_t) p_endpoint_desc->bmAttributes.xfer;
   struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
 
diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index dbc5cd18a..fc7150508 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -279,7 +279,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 
   /* mine the data for the information we need */
   int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  int const size = p_endpoint_desc->wMaxPacketSize.size;
+  int const size = tu_edpt_packet_size(p_endpoint_desc);
   tusb_xfer_type_t const type = (tusb_xfer_type_t) p_endpoint_desc->bmAttributes.xfer;
   struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
 
diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c
index 11d71a285..aefb09f4e 100644
--- a/src/portable/nuvoton/nuc505/dcd_nuc505.c
+++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c
@@ -327,7 +327,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 
   /* mine the data for the information we need */
   int const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  int const size = p_endpoint_desc->wMaxPacketSize.size;
+  int const size = tu_edpt_packet_size(p_endpoint_desc);
   tusb_xfer_type_t const type = p_endpoint_desc->bmAttributes.xfer;
   struct xfer_ctl_t *xfer = &xfer_table[ep - USBD->EP];
 
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index ff1997440..8de924f90 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -346,7 +346,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   /* No support for control transfer */
   TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
 
-  ep->max_packet_size = ep_desc->wMaxPacketSize.size;
+  ep->max_packet_size = tu_edpt_packet_size(ep_desc);
   unsigned val = USB_ENDPT_EPCTLDIS_MASK;
   val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
   val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 2eae6d0f7..0f500a88f 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -311,14 +311,15 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   }
 
   //------------- Realize Endpoint with Max Packet Size -------------//
-  set_ep_size(ep_id, p_endpoint_desc->wMaxPacketSize.size);
+  const uint16_t ep_size = tu_edpt_packet_size(p_endpoint_desc);
+  set_ep_size(ep_id, ep_size);
 
   //------------- first DD prepare -------------//
   dma_desc_t* const dd = &_dcd.dd[ep_id];
   tu_memclr(dd, sizeof(dma_desc_t));
 
   dd->isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
-  dd->max_packet_size = p_endpoint_desc->wMaxPacketSize.size;
+  dd->max_packet_size = ep_size;
   dd->retired = 1; // invalid at first
 
   sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + ep_id, 1, 0);    // clear all endpoint status
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 0f58cceb9..5ac041fbf 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -365,7 +365,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   tu_memclr(p_qhd, sizeof(dcd_qhd_t));
 
   p_qhd->zero_length_termination = 1;
-  p_qhd->max_packet_size         = p_endpoint_desc->wMaxPacketSize.size;
+  p_qhd->max_packet_size         = tu_edpt_packet_size(p_endpoint_desc);
   if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
   {
     p_qhd->iso_mult = 1;
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index bcee34938..daa8075b7 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -412,7 +412,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   }
   TU_ASSERT(p_ed);
 
-  ed_init( p_ed, dev_addr, ep_desc->wMaxPacketSize.size, ep_desc->bEndpointAddress,
+  ed_init( p_ed, dev_addr, tu_edpt_packet_size(ep_desc), ep_desc->bEndpointAddress,
             ep_desc->bmAttributes.xfer, ep_desc->bInterval );
 
   // control of dev0 is used as static async head
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 4bcc9ca54..e084478e0 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -426,7 +426,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
 bool dcd_edpt_open (__unused uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
     assert(rhport == 0);
-    hw_endpoint_init(desc_edpt->bEndpointAddress, desc_edpt->wMaxPacketSize.size, desc_edpt->bmAttributes.xfer);
+    hw_endpoint_init(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), desc_edpt->bmAttributes.xfer);
     return true;
 }
 
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 5e5bb4906..627e957e8 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -454,7 +454,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
     _hw_endpoint_init(ep,
         dev_addr,
         ep_desc->bEndpointAddress,
-        ep_desc->wMaxPacketSize.size,
+        tu_edpt_packet_size(ep_desc),
         ep_desc->bmAttributes.xfer,
         ep_desc->bInterval);
 
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 07d3ba898..ae7d2fd0c 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -695,7 +695,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   const unsigned dir     = tu_edpt_dir(ep_addr);
   const unsigned xfer    = ep_desc->bmAttributes.xfer;
 
-  const unsigned mps = tu_le16toh(ep_desc->wMaxPacketSize.size);
+  const unsigned mps = tu_edpt_packet_size(ep_desc);
   if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
     /* USBa supports up to 256 bytes */
     return false;
diff --git a/src/portable/silabs/efm32/dcd_efm32.c b/src/portable/silabs/efm32/dcd_efm32.c
index 3bef83408..ccae113a3 100644
--- a/src/portable/silabs/efm32/dcd_efm32.c
+++ b/src/portable/silabs/efm32/dcd_efm32.c
@@ -393,18 +393,17 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
   uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
 
-  TU_ASSERT(p_endpoint_desc->wMaxPacketSize.size <= 64);
   TU_ASSERT(epnum < EP_COUNT);
   TU_ASSERT(epnum != 0);
 
   xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = p_endpoint_desc->wMaxPacketSize.size;
+  xfer->max_size = tu_edpt_packet_size(p_endpoint_desc);
 
   if(dir == TUSB_DIR_OUT)
   {
     USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_USBACTEP |
                                 (p_endpoint_desc->bmAttributes.xfer << _USB_DOEP_CTL_EPTYPE_SHIFT) |
-                                (p_endpoint_desc->wMaxPacketSize.size << _USB_DOEP_CTL_MPS_SHIFT);
+                                (xfer->max_size << _USB_DOEP_CTL_MPS_SHIFT);
     USB->DAINTMSK |= (1 << (_USB_DAINTMSK_OUTEPMSK0_SHIFT + epnum));
   }
   else
@@ -417,7 +416,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
                                 (fifo_num << _USB_DIEP_CTL_TXFNUM_SHIFT) |
                                 (p_endpoint_desc->bmAttributes.xfer << _USB_DIEP_CTL_EPTYPE_SHIFT) |
                                 ((p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) ? USB_DIEP_CTL_SETD0PIDEF : 0) |
-                                (p_endpoint_desc->wMaxPacketSize.size << 0);
+                                (xfer->max_size << 0);
 
     USB->DAINTMSK |= (1 << epnum);
 
diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index 1b8a789a4..dfe409383 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -257,6 +257,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
   uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
   uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   uint8_t xfrtype = 0;
+  uint16_t const ep_mps = tu_edpt_packet_size(p_endpoint_desc);
+
   struct usb_epdesc_s epdesc;
 
   if (epnum >= CXD56_EPNUM)
@@ -287,7 +289,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
   usbdcd_driver.req[epnum] = EP_ALLOCREQ(usbdcd_driver.ep[epnum]);
   if (usbdcd_driver.req[epnum] != NULL)
   {
-    usbdcd_driver.req[epnum]->len = p_endpoint_desc->wMaxPacketSize.size;
+    usbdcd_driver.req[epnum]->len = ep_mps;
   }
   else
   {
@@ -300,8 +302,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc)
   epdesc.type = p_endpoint_desc->bDescriptorType;
   epdesc.addr = p_endpoint_desc->bEndpointAddress;
   epdesc.attr = xfrtype;
-  epdesc.mxpacketsize[0] = LSBYTE(p_endpoint_desc->wMaxPacketSize.size);
-  epdesc.mxpacketsize[1] = MSBYTE(p_endpoint_desc->wMaxPacketSize.size);
+  epdesc.mxpacketsize[0] = LSBYTE(ep_mps);
+  epdesc.mxpacketsize[1] = MSBYTE(ep_mps);
   epdesc.interval = p_endpoint_desc->bInterval;
 
   if (EP_CONFIGURE(usbdcd_driver.ep[epnum], &epdesc, false) < 0)
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index ccffa42d7..ca6564d46 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -394,7 +394,7 @@ static const tusb_desc_endpoint_t ep0OUT_desc =
 
   .bEndpointAddress = 0x00,
   .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-  .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
+  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
   .bInterval        = 0
 };
 
@@ -405,7 +405,7 @@ static const tusb_desc_endpoint_t ep0IN_desc =
 
   .bEndpointAddress = 0x80,
   .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-  .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
+  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
   .bInterval        = 0
 };
 
@@ -741,7 +741,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   (void)rhport;
   uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  const uint16_t epMaxPktSize = p_endpoint_desc->wMaxPacketSize.size;
+  const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc);
   uint16_t pma_addr;
   uint32_t wType;
   
@@ -778,19 +778,19 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   // or being double-buffered (bulk endpoints)
   pcd_clear_ep_kind(USB,0);
 
-  pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->wMaxPacketSize.size);
+  pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, epMaxPktSize);
 
   if(dir == TUSB_DIR_IN)
   {
     *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
-    pcd_set_ep_tx_cnt(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
+    pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize);
     pcd_clear_tx_dtog(USB, epnum);
     pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_NAK);
   }
   else
   {
     *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
-    pcd_set_ep_rx_cnt(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
+    pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize);
     pcd_clear_rx_dtog(USB, epnum);
     pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
   }
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 29030784b..4e2bbd076 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -622,10 +622,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   TU_ASSERT(epnum < EP_MAX);
 
   xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = desc_edpt->wMaxPacketSize.size;
+  xfer->max_size = tu_edpt_packet_size(desc_edpt);
   xfer->interval = desc_edpt->bInterval;
 
-  uint16_t const fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // Round up to next full word
+  uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word
 
   if(dir == TUSB_DIR_OUT)
   {
@@ -644,7 +644,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos)        |
         (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos)   |
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
-        (desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos);
+        (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos);
 
     dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
   }
@@ -686,7 +686,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
         (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
         (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
-        (desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos);
+        (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos);
 
     dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
   }
diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index ee85f0a77..7a2a0156f 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -242,7 +242,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   }
 
   xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = desc_edpt->wMaxPacketSize.size;
+  xfer->max_size = tu_edpt_packet_size(desc_edpt);
 
   // Buffer allocation scheme:
   // For simplicity, only single buffer for now, since tinyusb currently waits
@@ -275,7 +275,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   // Also, DBUF got set on OUT EP 2 while debugging. Only OUT EPs seem to be
   // affected at this time. USB RAM directly precedes main RAM; perhaps I'm
   // overwriting registers via buffer overflow w/ my debugging code?
-  ep_regs[SIZXY] = desc_edpt->wMaxPacketSize.size;
+  ep_regs[SIZXY] = tu_edpt_packet_size(desc_edpt);
   ep_regs[BCTX] |= NAK;
   ep_regs[BBAX] = buf_base;
   ep_regs[CNF] &= ~(TOGGLE | STALL | DBUF); // ISO xfers not supported on
diff --git a/src/tusb.c b/src/tusb.c
index fc1936c3d..9583f509d 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -69,7 +69,7 @@ bool tusb_inited(void)
 
 bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed)
 {
-  uint16_t const max_packet_size = tu_le16toh(desc_ep->wMaxPacketSize.size);
+  uint16_t const max_packet_size = tu_edpt_packet_size(desc_ep);
   TU_LOG2("  Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size);
 
   switch (desc_ep->bmAttributes.xfer)

From 109b7a666155eb1b59bf946be7319ac11bc625ea Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 24 Oct 2021 14:39:02 +0700
Subject: [PATCH 0586/2085] more wMaxPacketSize

---
 src/portable/dialog/da146xx/dcd_da146xx.c  | 4 ++--
 src/portable/microchip/samx7x/dcd_samx7x.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 51957829f..311119747 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -256,7 +256,7 @@ static const tusb_desc_endpoint_t ep0OUT_desc =
 
   .bEndpointAddress = 0x00,
   .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-  .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
+  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
   .bInterval        = 0
 };
 
@@ -267,7 +267,7 @@ static const tusb_desc_endpoint_t ep0IN_desc =
 
   .bEndpointAddress = 0x80,
   .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-  .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
+  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
   .bInterval        = 0
 };
 
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index d716e8fed..9e3b43840 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -84,7 +84,7 @@ static xfer_ctl_t xfer_status[EP_MAX];
 static const tusb_desc_endpoint_t ep0_desc =
 {
   .bEndpointAddress = 0x00,
-  .wMaxPacketSize   = { .size = CFG_TUD_ENDPOINT0_SIZE },
+  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
 };
 
 TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, int32_t size)

From 06de6b725c9d1ccadce0905f85335e4708ad1524 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 24 Oct 2021 23:24:46 +0700
Subject: [PATCH 0587/2085] adding generalized dwc2 driver

---
 hw/bsp/stm32f4/family.mk                |    2 +-
 src/device/dcd_attr.h                   |   45 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c   | 1155 ++++++++++++++++++
 src/portable/synopsys/dwc2/dwc2_gd32.h  |   56 +
 src/portable/synopsys/dwc2/dwc2_stm32.h |   72 ++
 src/portable/synopsys/dwc2/dwc2_type.h  | 1471 +++++++++++++++++++++++
 6 files changed, 2792 insertions(+), 9 deletions(-)
 create mode 100644 src/portable/synopsys/dwc2/dcd_dwc2.c
 create mode 100644 src/portable/synopsys/dwc2/dwc2_gd32.h
 create mode 100644 src/portable/synopsys/dwc2/dwc2_stm32.h
 create mode 100644 src/portable/synopsys/dwc2/dwc2_type.h

diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 584d69405..9811d3371 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -21,7 +21,7 @@ CFLAGS += \
 CFLAGS += -Wno-error=cast-align
 
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 44f2cc1d6..3690985c6 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -85,24 +85,53 @@
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- ST -------------//
-#elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \
-      TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4)
-  // F1: F102, F103
-  // L4: L4x2, L4x3
+#elif TU_CHECK_MCU(STM32F0)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(STM32F2) || TU_CHECK_MCU(STM32F4) || TU_CHECK_MCU(STM32F3)
-  // F1: F105, F107 only has 4
-  // L4: L4x5, L4x6 has 6
-  // For most mcu, FS has 4, HS has 6
+#elif TU_CHECK_MCU(STM32F1)
+  #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
+      defined (STM32F107xB) || defined (STM32F107xC)
+    #define DCD_ATTR_ENDPOINT_MAX   4
+    #define DCD_ATTR_DWC2_STM32
+  #else
+    #define DCD_ATTR_ENDPOINT_MAX   8
+  #endif
+
+#elif TU_CHECK_MCU(STM32F2)
+  // FS has 4 ep, HS has 5 ep
   #define DCD_ATTR_ENDPOINT_MAX   6
+  #define DCD_ATTR_DWC2_STM32
+
+#elif TU_CHECK_MCU(STM32F3)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
+#elif TU_CHECK_MCU(STM32F4)
+  // For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
+  #define DCD_ATTR_ENDPOINT_MAX   6
+  #define DCD_ATTR_DWC2_STM32
 
 #elif TU_CHECK_MCU(STM32F7)
   // FS has 6, HS has 9
   #define DCD_ATTR_ENDPOINT_MAX   9
+  #define DCD_ATTR_DWC2_STM32
 
 #elif TU_CHECK_MCU(STM32H7)
   #define DCD_ATTR_ENDPOINT_MAX   9
+  #define DCD_ATTR_DWC2_STM32
+
+#elif TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
+#elif TU_CHECK_MCU(STM32L4)
+  #if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
+      defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
+      defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
+      defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
+    #define DCD_ATTR_ENDPOINT_MAX   6
+    #define DCD_ATTR_DWC2_STM32
+  #else
+    #define DCD_ATTR_ENDPOINT_MAX   8
+  #endif
 
 //------------- Sony -------------//
 #elif TU_CHECK_MCU(CXD56)
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
new file mode 100644
index 000000000..597f4c813
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -0,0 +1,1155 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 William D. Jones
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jan Duempelmann
+ * Copyright (c) 2020 Reinhard Panhuber
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+#include "device/dcd_attr.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(GD32VF103))
+
+#include "dwc2_type.h"
+
+#if defined(DCD_ATTR_DWC2_STM32)
+  #include "dwc2_stm32.h"
+#elif TU_CHECK_MCU(GD32VF103)
+  #include "dwc2_gd32.h"
+#else
+  #error "Unsupported MCUs"
+#endif
+
+#include "device/dcd.h"
+
+// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
+// We disable SOF for now until needed later on
+#define USE_SOF     0
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
+#if TUD_OPT_RHPORT == 0
+#define EP_MAX            EP_MAX_FS
+#define EP_FIFO_SIZE      EP_FIFO_SIZE_FS
+#define RHPORT_REGS_BASE  USB_OTG_FS_PERIPH_BASE
+#define RHPORT_IRQn       OTG_FS_IRQn
+
+#else
+#define EP_MAX            EP_MAX_HS
+#define EP_FIFO_SIZE      EP_FIFO_SIZE_HS
+#define RHPORT_REGS_BASE  USB_OTG_HS_PERIPH_BASE
+#define RHPORT_IRQn       OTG_HS_IRQn
+
+#endif
+
+#define GLOBAL_BASE(_port)     ((dwc2_core_t*) RHPORT_REGS_BASE)
+#define DEVICE_BASE(_port)     ((dwc2_device_t *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE))
+#define OUT_EP_BASE(_port)     ((dwc2_epout_t *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE))
+#define IN_EP_BASE(_port)      ((dwc2_epin_t *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE))
+#define FIFO_BASE(_port, _x)   ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
+
+enum
+{
+  DCD_HIGH_SPEED        = 0, // Highspeed mode
+  DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY)
+  DCD_FULL_SPEED        = 3, // Full speed with internal PHY
+};
+
+static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
+
+typedef struct {
+  uint8_t * buffer;
+  tu_fifo_t * ff;
+  uint16_t total_len;
+  uint16_t max_size;
+  uint8_t interval;
+} xfer_ctl_t;
+
+typedef volatile uint32_t * usb_fifo_t;
+
+xfer_ctl_t xfer_status[EP_MAX][2];
+#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
+
+// EP0 transfers are limited to 1 packet - larger sizes has to be split
+static uint16_t ep0_pending[2];                   // Index determines direction as tusb_dir_t type
+
+// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ
+static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
+static bool _out_ep_closed;                       // Flag to check if RX FIFO size needs an update (reduce its size)
+
+// Calculate the RX FIFO size according to recommendations from reference manual
+static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
+{
+  return 15 + 2*(ep_size/4) + 2*EP_MAX;
+}
+
+static void update_grxfsiz(uint8_t rhport)
+{
+  (void) rhport;
+
+  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+
+  // Determine largest EP size for RX FIFO
+  uint16_t max_epsize = 0;
+  for (uint8_t epnum = 0; epnum < EP_MAX; epnum++)
+  {
+    max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
+  }
+
+  // Update size of RX FIFO
+  usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize);
+}
+
+// Setup the control endpoint 0.
+static void bus_reset(uint8_t rhport)
+{
+  (void) rhport;
+
+  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
+  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+
+  tu_memclr(xfer_status, sizeof(xfer_status));
+  _out_ep_closed = false;
+
+  // clear device address
+  dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
+
+  // 1. NAK for all OUT endpoints
+  for(uint8_t n = 0; n < EP_MAX; n++) {
+    out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+  }
+
+  // 2. Un-mask interrupt bits
+  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
+  dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
+  dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
+
+  // "USB Data FIFOs" section in reference manual
+  // Peripheral FIFO architecture
+  //
+  // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
+  // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
+  // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
+  // configuration done below.
+  //
+  // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
+  // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
+  // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
+  // opened when the host sends an additional command: setInterface. At this point in time
+  // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
+  // an additional memory
+  //
+  // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+  // | IN FIFO 0   |
+  // --------------- (320 or 1024) - 16
+  // | IN FIFO 1   |
+  // --------------- (320 or 1024) - 16 - x
+  // |   . . . .   |
+  // --------------- (320 or 1024) - 16 - x - y - ... - z
+  // | IN FIFO MAX |
+  // ---------------
+  // |    FREE     |
+  // --------------- GRXFSIZ
+  // | OUT FIFO    |
+  // | ( Shared )  |
+  // --------------- 0
+  //
+  // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
+  // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
+  //
+  // - All EP OUT shared a unique OUT FIFO which uses
+  //   - 13 for setup packets + control words (up to 3 setup packets).
+  //   - 1 for global NAK (not required/used here).
+  //   - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is  "2 x (Largest-EPsize/4) + 1"
+  //   - 2 for each used OUT endpoint
+  //
+  //   Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
+  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x EP_MAX = 47  + 2 x EP_MAX
+  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX
+  //
+  //   NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
+  //   of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
+  //
+  //   For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
+  //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
+  //   overwrite this.
+
+  usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
+
+  _allocated_fifo_words_tx = 16;
+
+  // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
+  usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+
+  // Fixed control EP0 size to 64 bytes
+  in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
+  xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
+
+  out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
+
+  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
+}
+
+// Set turn-around timeout according to link speed
+extern uint32_t SystemCoreClock;
+static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed)
+{
+  usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+
+  if ( speed == TUSB_SPEED_HIGH )
+  {
+    // Use fixed 0x09 for Highspeed
+    usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos);
+  }
+  else
+  {
+    // Turnaround timeout depends on the MCU clock
+    uint32_t turnaround;
+
+    if ( SystemCoreClock >= 32000000U )
+      turnaround = 0x6U;
+    else if ( SystemCoreClock >= 27500000U )
+      turnaround = 0x7U;
+    else if ( SystemCoreClock >= 24000000U )
+      turnaround = 0x8U;
+    else if ( SystemCoreClock >= 21800000U )
+      turnaround = 0x9U;
+    else if ( SystemCoreClock >= 20000000U )
+      turnaround = 0xAU;
+    else if ( SystemCoreClock >= 18500000U )
+      turnaround = 0xBU;
+    else if ( SystemCoreClock >= 17200000U )
+      turnaround = 0xCU;
+    else if ( SystemCoreClock >= 16000000U )
+      turnaround = 0xDU;
+    else if ( SystemCoreClock >= 15000000U )
+      turnaround = 0xEU;
+    else
+      turnaround = 0xFU;
+
+    // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
+    usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos);
+  }
+}
+
+static tusb_speed_t get_speed(uint8_t rhport)
+{
+  (void) rhport;
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
+  return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
+}
+
+static void set_speed(uint8_t rhport, tusb_speed_t speed)
+{
+  uint32_t bitvalue;
+
+  if ( rhport == 1 )
+  {
+    bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
+  }
+  else
+  {
+    bitvalue = DCD_FULL_SPEED;
+  }
+
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+
+  // Clear and set speed bits
+  dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos);
+  dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos);
+}
+
+#if defined(USB_HS_PHYC)
+static bool USB_HS_PHYCInit(void)
+{
+  USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
+
+  // Enable LDO
+  usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
+
+  // Wait until LDO ready
+  while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
+
+  uint32_t phyc_pll = 0;
+
+  // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
+  switch ( HSE_VALUE )
+  {
+    case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
+    case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
+    case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
+    case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
+    case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
+    case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
+    default:
+      TU_ASSERT(0);
+  }
+  usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
+
+  // Control the tuning interface of the High Speed PHY
+  // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
+  usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
+
+  // Enable PLL internal PHY
+  usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
+
+  // Original ST code has 2 ms delay for PLL stabilization.
+  // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
+
+  return true;
+}
+#endif
+
+static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
+{
+  (void) rhport;
+
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
+  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+
+  // EP0 is limited to one packet each xfer
+  // We use multiple transaction of xfer->max_size length to get a whole transfer done
+  if(epnum == 0) {
+    xfer_ctl_t * const xfer = XFER_CTL_BASE(epnum, dir);
+    total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
+    ep0_pending[dir] -= total_bytes;
+  }
+
+  // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
+  if(dir == TUSB_DIR_IN) {
+    // A full IN transfer (multiple packets, possibly) triggers XFRC.
+    in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) |
+        ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk);
+
+    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK;
+    // For ISO endpoint set correct odd/even bit for next frame.
+    if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
+    {
+      // Take odd/even bit from frame counter.
+      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
+      in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk);
+    }
+    // Enable fifo empty interrupt only if there are something to put in the fifo.
+    if(total_bytes != 0) {
+      dev->DIEPEMPMSK |= (1 << epnum);
+    }
+  } else {
+    // A full OUT transfer (multiple packets, possibly) triggers XFRC.
+    out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ);
+    out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) |
+        ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk);
+
+    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
+    if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
+    {
+      // Take odd/even bit from frame counter.
+      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
+      out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk);
+    }
+  }
+}
+
+/*------------------------------------------------------------------*/
+/* Controller API
+ *------------------------------------------------------------------*/
+void dcd_init (uint8_t rhport)
+{
+  // Programming model begins in the last section of the chapter on the USB
+  // peripheral in each Reference Manual.
+
+  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+
+  // No HNP/SRP (no OTG support), program timeout later.
+  if ( rhport == 1 )
+  {
+    // On selected MCUs HS port1 can be used with external PHY via ULPI interface
+#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
+    // deactivate internal PHY
+    usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
+
+    // Init The UTMI Interface
+    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+
+    // Select default internal VBUS Indicator and Drive for ULPI
+    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+#else
+    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+#endif
+
+#if defined(USB_HS_PHYC)
+    // Highspeed with embedded UTMI PHYC
+
+    // Select UTMI Interface
+    usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
+    usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
+
+    // Enables control of a High Speed USB PHY
+    USB_HS_PHYCInit();
+#endif
+  } else
+  {
+    // Enable internal PHY
+    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+  }
+
+  // Reset core after selecting PHY
+  // Wait AHB IDLE, reset then wait until it is cleared
+  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
+  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
+  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
+
+  // Restart PHY clock
+  *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
+
+  // Clear all interrupts
+  usb_otg->GINTSTS |= usb_otg->GINTSTS;
+
+  // Required as part of core initialization.
+  // TODO: How should mode mismatch be handled? It will cause
+  // the core to stop working/require reset.
+  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM;
+
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+
+  // If USB host misbehaves during status portion of control xfer
+  // (non zero-length packet), send STALL back and discard.
+  dev->DCFG |=  USB_OTG_DCFG_NZLSOHSK;
+
+  set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
+
+  // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
+  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+
+  usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST   | USB_OTG_GINTMSK_ENUMDNEM |
+      USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM     |
+      USB_OTG_GINTMSK_RXFLVLM  | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0);
+
+  // Enable global interrupt
+  usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+
+  dcd_connect(rhport);
+}
+
+void dcd_int_enable (uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(RHPORT_IRQn);
+}
+
+void dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(RHPORT_IRQn);
+}
+
+void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
+{
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos);
+
+  // Response with status after changing device address
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+
+static void remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+  uint32_t count = SystemCoreClock / 1000;
+  while ( count-- )
+  {
+    __NOP();
+  }
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+
+  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+
+  // set remote wakeup
+  dev->DCTL |= USB_OTG_DCTL_RWUSIG;
+
+  // enable SOF to detect bus resume
+  usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
+  usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+
+  // Per specs: remote wakeup signal bit must be clear within 1-15ms
+  remote_wakeup_delay();
+
+  dev->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dev->DCTL &= ~USB_OTG_DCTL_SDIS;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  (void) rhport;
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dev->DCTL |= USB_OTG_DCTL_SDIS;
+}
+
+
+/*------------------------------------------------------------------*/
+/* DCD Endpoint port
+ *------------------------------------------------------------------*/
+
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
+{
+  (void) rhport;
+
+  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
+  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+
+  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
+  uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
+
+  TU_ASSERT(epnum < EP_MAX);
+
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->max_size = tu_edpt_packet_size(desc_edpt);
+  xfer->interval = desc_edpt->bInterval;
+
+  uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word
+
+  if(dir == TUSB_DIR_OUT)
+  {
+    // Calculate required size of RX FIFO
+    uint16_t const sz = calc_rx_ff_size(4*fifo_size);
+
+    // If size_rx needs to be extended check if possible and if so enlarge it
+    if (usb_otg->GRXFSIZ < sz)
+    {
+      TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
+
+      // Enlarge RX FIFO
+      usb_otg->GRXFSIZ = sz;
+    }
+
+    out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos)        |
+        (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos)   |
+        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
+        (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos);
+
+    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
+  }
+  else
+  {
+    // "USB Data FIFOs" section in reference manual
+    // Peripheral FIFO architecture
+    //
+    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+    // | IN FIFO 0   |
+    // --------------- (320 or 1024) - 16
+    // | IN FIFO 1   |
+    // --------------- (320 or 1024) - 16 - x
+    // |   . . . .   |
+    // --------------- (320 or 1024) - 16 - x - y - ... - z
+    // | IN FIFO MAX |
+    // ---------------
+    // |    FREE     |
+    // --------------- GRXFSIZ
+    // | OUT FIFO    |
+    // | ( Shared )  |
+    // --------------- 0
+    //
+    // In FIFO is allocated by following rules:
+    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
+
+    // Check if free space is available
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4);
+
+    _allocated_fifo_words_tx += fifo_size;
+
+    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
+
+    // DIEPTXF starts at FIFO #1.
+    // Both TXFD and TXSA are in unit of 32-bit words.
+    usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+
+    in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
+        (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
+        (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
+        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
+        (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos);
+
+    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
+  }
+
+  return true;
+}
+
+// Close all non-control endpoints, cancel all pending transfers if any.
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+
+//  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
+  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+
+  // Disable non-control interrupt
+  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
+
+  for(uint8_t n = 1; n < EP_MAX; n++)
+  {
+    // disable OUT endpoint
+    out_ep[n].DOEPCTL = 0;
+    xfer_status[n][TUSB_DIR_OUT].max_size = 0;
+
+    // disable IN endpoint
+    in_ep[n].DIEPCTL = 0;
+    xfer_status[n][TUSB_DIR_IN].max_size = 0;
+  }
+
+  // reset allocated fifo IN
+  _allocated_fifo_words_tx = 16;
+}
+
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->buffer      = buffer;
+  xfer->ff          = NULL;
+  xfer->total_len   = total_bytes;
+
+  // EP0 can only handle one packet
+  if(epnum == 0) {
+    ep0_pending[dir] = total_bytes;
+    // Schedule the first transaction for EP0 transfer
+    edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
+    return true;
+  }
+
+  uint16_t num_packets = (total_bytes / xfer->max_size);
+  uint16_t const short_packet_size = total_bytes % xfer->max_size;
+
+  // Zero-size packet is special case.
+  if(short_packet_size > 0 || (total_bytes == 0)) {
+    num_packets++;
+  }
+
+  // Schedule packets to be sent within interrupt
+  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
+
+  return true;
+}
+
+// The number of bytes has to be given explicitly to allow more flexible control of how many
+// bytes should be written and second to keep the return value free to give back a boolean
+// success message. If total_bytes is too big, the FIFO will copy only what is available
+// into the USB buffer!
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
+  TU_ASSERT(ff->item_size == 1);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->buffer      = NULL;
+  xfer->ff          = ff;
+  xfer->total_len   = total_bytes;
+
+  uint16_t num_packets = (total_bytes / xfer->max_size);
+  uint16_t const short_packet_size = total_bytes % xfer->max_size;
+
+  // Zero-size packet is special case.
+  if(short_packet_size > 0 || (total_bytes == 0)) num_packets++;
+
+  // Schedule packets to be sent within interrupt
+  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
+
+  return true;
+}
+
+static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
+{
+  (void) rhport;
+
+  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
+  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  if(dir == TUSB_DIR_IN) {
+    // Only disable currently enabled non-control endpoint
+    if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){
+      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0);
+    } else {
+      // Stop transmitting packets and NAK IN xfers.
+      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
+      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0);
+
+      // Disable the endpoint.
+      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0);
+      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0);
+      in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD;
+    }
+
+    // Flush the FIFO, and wait until we have confirmed it cleared.
+    usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos);
+    usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
+    while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
+  } else {
+    // Only disable currently enabled non-control endpoint
+    if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){
+      out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0;
+    } else {
+      // Asserting GONAK is required to STALL an OUT endpoint.
+      // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
+      // anyway, and it can't be cleared by user code. If this while loop never
+      // finishes, we have bigger problems than just the stack.
+      dev->DCTL |= USB_OTG_DCTL_SGONAK;
+      while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
+
+      // Ditto here- disable the endpoint.
+      out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0);
+      while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0);
+      out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD;
+
+      // Allow other OUT endpoints to keep receiving.
+      dev->DCTL |= USB_OTG_DCTL_CGONAK;
+    }
+  }
+}
+
+/**
+ * Close an endpoint.
+ */
+void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
+{
+  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  dcd_edpt_disable(rhport, ep_addr, false);
+
+  // Update max_size
+  xfer_status[epnum][dir].max_size = 0;  // max_size = 0 marks a disabled EP - required for changing FIFO allocation
+
+  if (dir == TUSB_DIR_IN)
+  {
+    uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos;
+    uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos;
+    // For now only the last opened endpoint can be closed without fuss.
+    TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
+    _allocated_fifo_words_tx -= fifo_size;
+  }
+  else
+  {
+    _out_ep_closed = true;     // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
+  }
+}
+
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  dcd_edpt_disable(rhport, ep_addr, true);
+}
+
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+
+  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
+  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  // Clear stall and reset data toggle
+  if(dir == TUSB_DIR_IN) {
+    in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
+    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+  } else {
+    out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
+    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+  }
+}
+
+/*------------------------------------------------------------------*/
+
+// Read a single data packet from receive FIFO
+static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
+{
+  (void) rhport;
+
+  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
+
+  // Reading full available 32 bit words from fifo
+  uint16_t full_words = len >> 2;
+  for(uint16_t i = 0; i < full_words; i++) {
+    uint32_t tmp = *rx_fifo;
+    dst[0] = tmp & 0x000000FF;
+    dst[1] = (tmp & 0x0000FF00) >> 8;
+    dst[2] = (tmp & 0x00FF0000) >> 16;
+    dst[3] = (tmp & 0xFF000000) >> 24;
+    dst += 4;
+  }
+
+  // Read the remaining 1-3 bytes from fifo
+  uint8_t bytes_rem = len & 0x03;
+  if(bytes_rem != 0) {
+    uint32_t tmp = *rx_fifo;
+    dst[0] = tmp & 0x000000FF;
+    if(bytes_rem > 1) {
+      dst[1] = (tmp & 0x0000FF00) >> 8;
+    }
+    if(bytes_rem > 2) {
+      dst[2] = (tmp & 0x00FF0000) >> 16;
+    }
+  }
+}
+
+// Write a single data packet to EPIN FIFO
+static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len)
+{
+  (void) rhport;
+
+  usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num);
+
+  // Pushing full available 32 bit words to fifo
+  uint16_t full_words = len >> 2;
+  for(uint16_t i = 0; i < full_words; i++){
+    *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0];
+    src += 4;
+  }
+
+  // Write the remaining 1-3 bytes into fifo
+  uint8_t bytes_rem = len & 0x03;
+  if(bytes_rem){
+    uint32_t tmp_word = 0;
+    tmp_word |= src[0];
+    if(bytes_rem > 1){
+      tmp_word |= src[1] << 8;
+    }
+    if(bytes_rem > 2){
+      tmp_word |= src[2] << 16;
+    }
+    *tx_fifo = tmp_word;
+  }
+}
+
+static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
+  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
+
+  // Pop control word off FIFO
+  uint32_t ctl_word = usb_otg->GRXSTSP;
+  uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos;
+  uint8_t epnum = (ctl_word &  USB_OTG_GRXSTSP_EPNUM_Msk) >>  USB_OTG_GRXSTSP_EPNUM_Pos;
+  uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos;
+
+  switch(pktsts) {
+    case 0x01: // Global OUT NAK (Interrupt)
+      break;
+
+    case 0x02: // Out packet recvd
+    {
+      xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+
+      // Read packet off RxFIFO
+      if (xfer->ff)
+      {
+        // Ring buffer
+        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt);
+      }
+      else
+      {
+        // Linear buffer
+        read_fifo_packet(rhport, xfer->buffer, bcnt);
+
+        // Increment pointer to xfer data
+        xfer->buffer += bcnt;
+      }
+
+      // Truncate transfer length in case of short packet
+      if(bcnt < xfer->max_size) {
+        xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
+        if(epnum == 0) {
+          xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
+          ep0_pending[TUSB_DIR_OUT] = 0;
+        }
+      }
+    }
+    break;
+
+    case 0x03: // Out packet done (Interrupt)
+      break;
+
+    case 0x04: // Setup packet done (Interrupt)
+      out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
+      break;
+
+    case 0x06: // Setup packet recvd
+      // We can receive up to three setup packets in succession, but
+      // only the last one is valid.
+      _setup_packet[0] = (* rx_fifo);
+      _setup_packet[1] = (* rx_fifo);
+      break;
+
+    default: // Invalid
+      TU_BREAKPOINT();
+      break;
+  }
+}
+
+static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t * out_ep) {
+  // DAINT for a given EP clears when DOEPINTx is cleared.
+  // OEPINT will be cleared when DAINT's out bits are cleared.
+  for(uint8_t n = 0; n < EP_MAX; n++) {
+    xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
+
+    if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) {
+      // SETUP packet Setup Phase done.
+      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) {
+        out_ep[n].DOEPINT =  USB_OTG_DOEPINT_STUP;
+        dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
+      }
+
+      // OUT XFER complete
+      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) {
+        out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC;
+
+        // EP0 can only handle one packet
+        if((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
+          // Schedule another packet to be received.
+          edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
+        } else {
+          dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
+        }
+      }
+    }
+  }
+}
+
+static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * in_ep) {
+  // DAINT for a given EP clears when DIEPINTx is cleared.
+  // IEPINT will be cleared when DAINT's out bits are cleared.
+  for ( uint8_t n = 0; n < EP_MAX; n++ )
+  {
+    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
+
+    if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) )
+    {
+      // IN XFER complete (entire xfer).
+      if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC )
+      {
+        in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC;
+
+        // EP0 can only handle one packet
+        if((n == 0) && ep0_pending[TUSB_DIR_IN]) {
+          // Schedule another packet to be transmitted.
+          edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
+        } else {
+          dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+        }
+      }
+
+      // XFER FIFO empty
+      if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
+      {
+        // DIEPINT's TXFE bit is read-only, software cannot clear it.
+        // It will only be cleared by hardware when written bytes is more than
+        // - 64 bytes or
+        // - Half of TX FIFO size (configured by DIEPTXF)
+
+        uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos;
+
+        // Process every single packet (only whole packets can be written to fifo)
+        for(uint16_t i = 0; i < remaining_packets; i++)
+        {
+          uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos;
+
+          // Packet can not be larger than ep max size
+          uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
+
+          // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
+          // EP has to be checked if the buffer can take another WHOLE packet
+          if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break;
+
+          // Push packet to Tx-FIFO
+          if (xfer->ff)
+          {
+            usb_fifo_t tx_fifo = FIFO_BASE(rhport, n);
+            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size);
+          }
+          else
+          {
+            write_fifo_packet(rhport, n, xfer->buffer, packet_size);
+
+            // Increment pointer to xfer data
+            xfer->buffer += packet_size;
+          }
+        }
+
+        // Turn off TXFE if all bytes are written.
+        if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0)
+        {
+          dev->DIEPEMPMSK &= ~(1 << n);
+        }
+      }
+    }
+  }
+}
+
+void dcd_int_handler(uint8_t rhport)
+{
+  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
+  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+
+  uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
+
+  if(int_status & USB_OTG_GINTSTS_USBRST)
+  {
+    // USBRST is start of reset.
+    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST;
+    bus_reset(rhport);
+  }
+
+  if(int_status & USB_OTG_GINTSTS_ENUMDNE)
+  {
+    // ENUMDNE is the end of reset where speed of the link is detected
+
+    usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
+
+    tusb_speed_t const speed = get_speed(rhport);
+
+    set_turnaround(usb_otg, speed);
+    dcd_event_bus_reset(rhport, speed, true);
+  }
+
+  if(int_status & USB_OTG_GINTSTS_USBSUSP)
+  {
+    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP;
+    dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+  }
+
+  if(int_status & USB_OTG_GINTSTS_WKUINT)
+  {
+    usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT;
+    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+  }
+
+  // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection
+  // if(int_status & USB_OTG_GINTSTS_DISCINT)
+
+  if(int_status & USB_OTG_GINTSTS_OTGINT)
+  {
+    // OTG INT bit is read-only
+    uint32_t const otg_int = usb_otg->GOTGINT;
+
+    if (otg_int & USB_OTG_GOTGINT_SEDET)
+    {
+      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+    }
+
+    usb_otg->GOTGINT = otg_int;
+  }
+
+  if(int_status & USB_OTG_GINTSTS_SOF)
+  {
+    usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
+
+    // Disable SOF interrupt since currently only used for remote wakeup detection
+    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM;
+
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+
+  // RxFIFO non-empty interrupt handling.
+  if(int_status & USB_OTG_GINTSTS_RXFLVL)
+  {
+    // RXFLVL bit is read-only
+
+    // Mask out RXFLVL while reading data from FIFO
+    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM;
+
+    // Loop until all available packets were handled
+    do
+    {
+      handle_rxflvl_ints(rhport, out_ep);
+    } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL);
+
+    // Manage RX FIFO size
+    if (_out_ep_closed)
+    {
+      update_grxfsiz(rhport);
+
+      // Disable flag
+      _out_ep_closed = false;
+    }
+
+    usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+  }
+
+  // OUT endpoint interrupt handling.
+  if(int_status & USB_OTG_GINTSTS_OEPINT)
+  {
+    // OEPINT is read-only
+    handle_epout_ints(rhport, dev, out_ep);
+  }
+
+  // IN endpoint interrupt handling.
+  if(int_status & USB_OTG_GINTSTS_IEPINT)
+  {
+    // IEPINT bit read-only
+    handle_epin_ints(rhport, dev, in_ep);
+  }
+
+  //  // Check for Incomplete isochronous IN transfer
+  //  if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
+  //    printf("      IISOIXFR!\r\n");
+  ////    TU_LOG2("      IISOIXFR!\r\n");
+  //  }
+}
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
new file mode 100644
index 000000000..5abbd225f
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -0,0 +1,56 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef DWC2_GD32_H_
+#define DWC2_GD32_H_
+
+// for remote wakeup delay
+#define __NOP()   __asm volatile ("nop")
+
+// These numbers are the same for the whole GD32VF103 family.
+#define OTG_FS_IRQn     86
+#define EP_MAX_FS       4
+#define EP_FIFO_SIZE_FS 1280
+
+// The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
+// Interrupt Controller by Nuclei. It is nearly API compatible to the
+// NVIC used by ARM MCUs.
+#define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL
+
+#define NVIC_EnableIRQ __eclic_enable_interrupt
+#define NVIC_DisableIRQ __eclic_disable_interrupt
+
+static inline void __eclic_enable_interrupt (uint32_t irq) {
+  *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1;
+}
+
+static inline void __eclic_disable_interrupt (uint32_t irq){
+  *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
+}
+
+
+#endif /* DWC2_GD32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
new file mode 100644
index 000000000..efed6d14a
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -0,0 +1,72 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_DWC2_STM32_H_
+#define _TUSB_DWC2_STM32_H_
+
+// EP_MAX       : Max number of bi-directional endpoints including EP0
+// EP_FIFO_SIZE : Size of dedicated USB SRAM
+#if CFG_TUSB_MCU == OPT_MCU_STM32F1
+  #include "stm32f1xx.h"
+  #define EP_MAX_FS       4
+  #define EP_FIFO_SIZE_FS 1280
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F2
+  #include "stm32f2xx.h"
+  #define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
+  #define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F4
+  #include "stm32f4xx.h"
+  #define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
+  #define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
+  #define EP_MAX_HS       USB_OTG_HS_MAX_IN_ENDPOINTS
+  #define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H7
+  #include "stm32h7xx.h"
+  #define EP_MAX_FS       9
+  #define EP_FIFO_SIZE_FS 4096
+  #define EP_MAX_HS       9
+  #define EP_FIFO_SIZE_HS 4096
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
+  #include "stm32f7xx.h"
+  #define EP_MAX_FS       6
+  #define EP_FIFO_SIZE_FS 1280
+  #define EP_MAX_HS       9
+  #define EP_FIFO_SIZE_HS 4096
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
+  #include "stm32l4xx.h"
+  #define EP_MAX_FS       6
+  #define EP_FIFO_SIZE_FS 1280
+
+#else
+  #error "Unsupported MCUs"
+#endif
+
+#endif /* DWC2_STM32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
new file mode 100644
index 000000000..8f48c71eb
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -0,0 +1,1471 @@
+/**
+  * @author  MCD Application Team
+  *          Ha Thach (tinyusb.org)
+  *
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  */
+
+#ifndef _TUSB_DWC2_TYPES_H_
+#define _TUSB_DWC2_TYPES_H_
+
+#include "stdint.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifdef __cplusplus
+  #define   __I   volatile
+#else
+  #define   __I   volatile const
+#endif
+#define     __O   volatile
+#define     __IO  volatile
+#define     __IM  volatile const
+#define     __OM  volatile
+#define     __IOM volatile
+
+#if 0
+// HS PHY
+typedef struct
+{
+
+__IO uint32_t USB_HS_PHYC_PLL;         /*!< This register is used to control the PLL of the HS PHY.                       000h */
+__IO uint32_t Reserved04;              /*!< Reserved                                                                      004h */
+__IO uint32_t Reserved08;              /*!< Reserved                                                                      008h */
+__IO uint32_t USB_HS_PHYC_TUNE;        /*!< This register is used to control the tuning interface of the High Speed PHY.  00Ch */
+__IO uint32_t Reserved10;              /*!< Reserved                                                                      010h */
+__IO uint32_t Reserved14;              /*!< Reserved                                                                      014h */
+__IO uint32_t USB_HS_PHYC_LDO;         /*!< This register is used to control the regulator (LDO).                         018h */
+} USB_HS_PHYC_GlobalTypeDef;
+#endif
+
+// Core
+typedef struct
+{
+ __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
+ __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+ __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+ __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+ __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+ __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+ __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+ __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+ __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+ __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+ __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+ uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+ __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+ __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+ __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
+ __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
+ __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
+ __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+ uint32_t  Reserved6;                /*!< Reserved                                     050h */
+ __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+ __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+ __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+  __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+   uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
+ __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+ __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO              104h-13Ch */
+} dwc2_core_t;
+
+// Host
+typedef struct
+{
+ __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+ __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+ __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+ uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+ __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+ __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+ __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} dwc2_host_t;
+
+// Host Channel
+typedef struct
+{
+ __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+ __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+ __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+ __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+ __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+ __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+ uint32_t Reserved[2];           /*!< Reserved                                      */
+} dwc2_channel_t;
+
+// Device
+typedef struct
+{
+ __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+ __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+ __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+ uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+ __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+ __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+ __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+ __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+ uint32_t  Reserved20;          /*!< Reserved                     820h */
+ uint32_t Reserved9;            /*!< Reserved                     824h */
+ __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+ __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+ __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+ __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+ __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+ __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+ uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+ __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+ uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+ __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} dwc2_device_t;
+
+// Endpoint IN
+typedef struct
+{
+ __IO uint32_t DIEPCTL;       /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04;         /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+ __IO uint32_t DIEPINT;       /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C;         /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DIEPTSIZ;      /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+ __IO uint32_t DIEPDMA;       /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+ __IO uint32_t DTXFSTS;       /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+ uint32_t Reserved18;         /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} dwc2_epin_t;
+
+// Endpoint OUT
+typedef struct
+{
+ __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+ uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+ __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+ uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+ __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+ __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+ uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} dwc2_epout_t;
+
+
+/*!< USB registers base address */
+#define DWC2_GLOBAL_BASE                  0x00000000UL
+#define DWC2_DEVICE_BASE                  0x00000800UL
+#define DWC2_IN_ENDPOINT_BASE             0x00000900UL
+#define DWC2_OUT_ENDPOINT_BASE            0x00000B00UL
+#define DWC2_EP_REG_SIZE                  0x00000020UL
+#define DWC2_HOST_BASE                    0x00000400UL
+#define DWC2_HOST_PORT_BASE               0x00000440UL
+#define DWC2_HOST_CHANNEL_BASE            0x00000500UL
+#define DWC2_HOST_CHANNEL_SIZE            0x00000020UL
+#define DWC2_PCGCCTL_BASE                 0x00000E00UL
+#define DWC2_FIFO_BASE                    0x00001000UL
+#define DWC2_FIFO_SIZE                    0x00001000UL
+
+#if 0
+/******************************************************************************/
+/*                                                                            */
+/*                                 USB_OTG                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos              (0U)                           
+#define USB_OTG_GOTGCTL_SRQSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                  USB_OTG_GOTGCTL_SRQSCS_Msk     /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                 (1U)                           
+#define USB_OTG_GOTGCTL_SRQ_Msk                 (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                     USB_OTG_GOTGCTL_SRQ_Msk        /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos              (8U)                           
+#define USB_OTG_GOTGCTL_HNGSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos               (9U)                           
+#define USB_OTG_GOTGCTL_HNPRQ_Msk               (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                   USB_OTG_GOTGCTL_HNPRQ_Msk      /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos             (10U)                          
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk             (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                 USB_OTG_GOTGCTL_HSHNPEN_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos              (11U)                          
+#define USB_OTG_GOTGCTL_DHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                  USB_OTG_GOTGCTL_DHNPEN_Msk     /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos              (16U)                          
+#define USB_OTG_GOTGCTL_CIDSTS_Msk              (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                  USB_OTG_GOTGCTL_CIDSTS_Msk     /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                (17U)                          
+#define USB_OTG_GOTGCTL_DBCT_Msk                (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                    USB_OTG_GOTGCTL_DBCT_Msk       /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos               (18U)                          
+#define USB_OTG_GOTGCTL_ASVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                   USB_OTG_GOTGCTL_ASVLD_Msk      /*!< A-session valid */
+#define USB_OTG_GOTGCTL_BSVLD_Pos               (19U)                          
+#define USB_OTG_GOTGCTL_BSVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD                   USB_OTG_GOTGCTL_BSVLD_Msk      /*!< B-session valid */
+
+/********************  Bit definition for USB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                (0U)                           
+#define USB_OTG_HCFG_FSLSPCS_Msk                (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                    USB_OTG_HCFG_FSLSPCS_Msk       /*!< FS/LS PHY clock select */
+#define USB_OTG_HCFG_FSLSPCS_0                  (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                  (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                  (2U)                           
+#define USB_OTG_HCFG_FSLSS_Msk                  (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                      USB_OTG_HCFG_FSLSS_Msk         /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                   (0U)                           
+#define USB_OTG_DCFG_DSPD_Msk                   (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                       USB_OTG_DCFG_DSPD_Msk          /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                     (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                     (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos               (2U)                           
+#define USB_OTG_DCFG_NZLSOHSK_Msk               (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                   USB_OTG_DCFG_NZLSOHSK_Msk      /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                    (4U)                           
+#define USB_OTG_DCFG_DAD_Msk                    (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                        USB_OTG_DCFG_DAD_Msk           /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                      (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                      (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                      (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                      (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                      (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                      (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                      (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                  (11U)                          
+#define USB_OTG_DCFG_PFIVL_Msk                  (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                      USB_OTG_DCFG_PFIVL_Msk         /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                    (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                    (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos              (24U)                          
+#define USB_OTG_DCFG_PERSCHIVL_Msk              (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                  USB_OTG_DCFG_PERSCHIVL_Msk     /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos               (0U)                           
+#define USB_OTG_PCGCR_STPPCLK_Msk               (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                   USB_OTG_PCGCR_STPPCLK_Msk      /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos              (1U)                           
+#define USB_OTG_PCGCR_GATEHCLK_Msk              (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                  USB_OTG_PCGCR_GATEHCLK_Msk     /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos               (4U)                           
+#define USB_OTG_PCGCR_PHYSUSP_Msk               (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                   USB_OTG_PCGCR_PHYSUSP_Msk      /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos               (2U)                           
+#define USB_OTG_GOTGINT_SEDET_Msk               (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                   USB_OTG_GOTGINT_SEDET_Msk      /*!< Session end detected */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos             (8U)                           
+#define USB_OTG_GOTGINT_SRSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                 USB_OTG_GOTGINT_SRSSCHG_Msk    /*!< Session request success status change */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos             (9U)                           
+#define USB_OTG_GOTGINT_HNSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                 USB_OTG_GOTGINT_HNSSCHG_Msk    /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos              (17U)                          
+#define USB_OTG_GOTGINT_HNGDET_Msk              (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                  USB_OTG_GOTGINT_HNGDET_Msk     /*!< Host negotiation detected */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos             (18U)                          
+#define USB_OTG_GOTGINT_ADTOCHG_Msk             (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                 USB_OTG_GOTGINT_ADTOCHG_Msk    /*!< A-device timeout change */
+#define USB_OTG_GOTGINT_DBCDNE_Pos              (19U)                          
+#define USB_OTG_GOTGINT_DBCDNE_Msk              (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                  USB_OTG_GOTGINT_DBCDNE_Msk     /*!< Debounce done */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                 (0U)                           
+#define USB_OTG_DCTL_RWUSIG_Msk                 (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                     USB_OTG_DCTL_RWUSIG_Msk        /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                   (1U)                           
+#define USB_OTG_DCTL_SDIS_Msk                   (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                       USB_OTG_DCTL_SDIS_Msk          /*!< Soft disconnect */
+#define USB_OTG_DCTL_GINSTS_Pos                 (2U)                           
+#define USB_OTG_DCTL_GINSTS_Msk                 (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                     USB_OTG_DCTL_GINSTS_Msk        /*!< Global IN NAK status */
+#define USB_OTG_DCTL_GONSTS_Pos                 (3U)                           
+#define USB_OTG_DCTL_GONSTS_Msk                 (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                     USB_OTG_DCTL_GONSTS_Msk        /*!< Global OUT NAK status */
+
+#define USB_OTG_DCTL_TCTL_Pos                   (4U)                           
+#define USB_OTG_DCTL_TCTL_Msk                   (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                       USB_OTG_DCTL_TCTL_Msk          /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                     (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                     (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                     (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                 (7U)                           
+#define USB_OTG_DCTL_SGINAK_Msk                 (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                     USB_OTG_DCTL_SGINAK_Msk        /*!< Set global IN NAK */
+#define USB_OTG_DCTL_CGINAK_Pos                 (8U)                           
+#define USB_OTG_DCTL_CGINAK_Msk                 (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                     USB_OTG_DCTL_CGINAK_Msk        /*!< Clear global IN NAK */
+#define USB_OTG_DCTL_SGONAK_Pos                 (9U)                           
+#define USB_OTG_DCTL_SGONAK_Msk                 (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                     USB_OTG_DCTL_SGONAK_Msk        /*!< Set global OUT NAK */
+#define USB_OTG_DCTL_CGONAK_Pos                 (10U)                          
+#define USB_OTG_DCTL_CGONAK_Msk                 (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                     USB_OTG_DCTL_CGONAK_Msk        /*!< Clear global OUT NAK */
+#define USB_OTG_DCTL_POPRGDNE_Pos               (11U)                          
+#define USB_OTG_DCTL_POPRGDNE_Msk               (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                   USB_OTG_DCTL_POPRGDNE_Msk      /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                  (0U)                           
+#define USB_OTG_HFIR_FRIVL_Msk                  (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                      USB_OTG_HFIR_FRIVL_Msk         /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                 (0U)                           
+#define USB_OTG_HFNUM_FRNUM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                     USB_OTG_HFNUM_FRNUM_Msk        /*!< Frame number */
+#define USB_OTG_HFNUM_FTREM_Pos                 (16U)                          
+#define USB_OTG_HFNUM_FTREM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                     USB_OTG_HFNUM_FTREM_Msk        /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                (0U)                           
+#define USB_OTG_DSTS_SUSPSTS_Msk                (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                    USB_OTG_DSTS_SUSPSTS_Msk       /*!< Suspend status */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                (1U)                           
+#define USB_OTG_DSTS_ENUMSPD_Msk                (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                    USB_OTG_DSTS_ENUMSPD_Msk       /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                  (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                  (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                   (3U)                           
+#define USB_OTG_DSTS_EERR_Msk                   (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                       USB_OTG_DSTS_EERR_Msk          /*!< Erratic error */
+#define USB_OTG_DSTS_FNSOF_Pos                  (8U)                           
+#define USB_OTG_DSTS_FNSOF_Msk                  (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                      USB_OTG_DSTS_FNSOF_Msk         /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                (0U)                           
+#define USB_OTG_GAHBCFG_GINT_Msk                (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                    USB_OTG_GAHBCFG_GINT_Msk       /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)                           
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk             (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                 USB_OTG_GAHBCFG_HBSTLEN_Msk    /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)                           
+#define USB_OTG_GAHBCFG_DMAEN_Msk               (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                   USB_OTG_GAHBCFG_DMAEN_Msk      /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos             (7U)                           
+#define USB_OTG_GAHBCFG_TXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                 USB_OTG_GAHBCFG_TXFELVL_Msk    /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos            (8U)                           
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk            (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                USB_OTG_GAHBCFG_PTXFELVL_Msk   /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos               (0U)                           
+#define USB_OTG_GUSBCFG_TOCAL_Msk               (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                   USB_OTG_GUSBCFG_TOCAL_Msk      /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos              (6U)                           
+#define USB_OTG_GUSBCFG_PHYSEL_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                  USB_OTG_GUSBCFG_PHYSEL_Msk     /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos              (8U)                           
+#define USB_OTG_GUSBCFG_SRPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                  USB_OTG_GUSBCFG_SRPCAP_Msk     /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos              (9U)                           
+#define USB_OTG_GUSBCFG_HNPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                  USB_OTG_GUSBCFG_HNPCAP_Msk     /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                (10U)                          
+#define USB_OTG_GUSBCFG_TRDT_Msk                (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                    USB_OTG_GUSBCFG_TRDT_Msk       /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                  (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                  (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                  (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                  (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos             (15U)                          
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk             (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                 USB_OTG_GUSBCFG_PHYLPCS_Msk    /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos            (17U)                          
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk            (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                USB_OTG_GUSBCFG_ULPIFSLS_Msk   /*!< ULPI FS/LS select */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos              (18U)                          
+#define USB_OTG_GUSBCFG_ULPIAR_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                  USB_OTG_GUSBCFG_ULPIAR_Msk     /*!< ULPI Auto-resume */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos             (19U)                          
+#define USB_OTG_GUSBCFG_ULPICSM_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                 USB_OTG_GUSBCFG_ULPICSM_Msk    /*!< ULPI Clock SuspendM */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos          (20U)                          
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD              USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos          (21U)                          
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI              USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
+#define USB_OTG_GUSBCFG_TSDPS_Pos               (22U)                          
+#define USB_OTG_GUSBCFG_TSDPS_Msk               (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                   USB_OTG_GUSBCFG_TSDPS_Msk      /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                (23U)                          
+#define USB_OTG_GUSBCFG_PCCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                    USB_OTG_GUSBCFG_PCCI_Msk       /*!< Indicator complement */
+#define USB_OTG_GUSBCFG_PTCI_Pos                (24U)                          
+#define USB_OTG_GUSBCFG_PTCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                    USB_OTG_GUSBCFG_PTCI_Msk       /*!< Indicator pass through */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos             (25U)                          
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                 USB_OTG_GUSBCFG_ULPIIPD_Msk    /*!< ULPI interface protect disable */
+#define USB_OTG_GUSBCFG_FHMOD_Pos               (29U)                          
+#define USB_OTG_GUSBCFG_FHMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                   USB_OTG_GUSBCFG_FHMOD_Msk      /*!< Forced host mode */
+#define USB_OTG_GUSBCFG_FDMOD_Pos               (30U)                          
+#define USB_OTG_GUSBCFG_FDMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                   USB_OTG_GUSBCFG_FDMOD_Msk      /*!< Forced peripheral mode */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos              (31U)                          
+#define USB_OTG_GUSBCFG_CTXPKT_Msk              (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                  USB_OTG_GUSBCFG_CTXPKT_Msk     /*!< Corrupt Tx packet */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos               (0U)                           
+#define USB_OTG_GRSTCTL_CSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                   USB_OTG_GRSTCTL_CSRST_Msk      /*!< Core soft reset */
+#define USB_OTG_GRSTCTL_HSRST_Pos               (1U)                           
+#define USB_OTG_GRSTCTL_HSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                   USB_OTG_GRSTCTL_HSRST_Msk      /*!< HCLK soft reset */
+#define USB_OTG_GRSTCTL_FCRST_Pos               (2U)                           
+#define USB_OTG_GRSTCTL_FCRST_Msk               (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                   USB_OTG_GRSTCTL_FCRST_Msk      /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos             (4U)                           
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                 USB_OTG_GRSTCTL_RXFFLSH_Msk    /*!< RxFIFO flush */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos             (5U)                           
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                 USB_OTG_GRSTCTL_TXFFLSH_Msk    /*!< TxFIFO flush */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos              (6U)                           
+#define USB_OTG_GRSTCTL_TXFNUM_Msk              (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                  USB_OTG_GRSTCTL_TXFNUM_Msk     /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos              (30U)                          
+#define USB_OTG_GRSTCTL_DMAREQ_Msk              (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                  USB_OTG_GRSTCTL_DMAREQ_Msk     /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos              (31U)                          
+#define USB_OTG_GRSTCTL_AHBIDL_Msk              (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                  USB_OTG_GRSTCTL_AHBIDL_Msk     /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos               (0U)                           
+#define USB_OTG_DIEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                   USB_OTG_DIEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPMSK_EPDM_Pos                (1U)                           
+#define USB_OTG_DIEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                    USB_OTG_DIEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPMSK_TOM_Pos                 (3U)                           
+#define USB_OTG_DIEPMSK_TOM_Msk                 (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                     USB_OTG_DIEPMSK_TOM_Msk        /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos           (4U)                           
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk           (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK               USB_OTG_DIEPMSK_ITTXFEMSK_Msk  /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos             (5U)                           
+#define USB_OTG_DIEPMSK_INEPNMM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                 USB_OTG_DIEPMSK_INEPNMM_Msk    /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos             (6U)                           
+#define USB_OTG_DIEPMSK_INEPNEM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                 USB_OTG_DIEPMSK_INEPNEM_Msk    /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPMSK_TXFURM_Pos              (8U)                           
+#define USB_OTG_DIEPMSK_TXFURM_Msk              (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                  USB_OTG_DIEPMSK_TXFURM_Msk     /*!< FIFO underrun mask */
+#define USB_OTG_DIEPMSK_BIM_Pos                 (9U)                           
+#define USB_OTG_DIEPMSK_BIM_Msk                 (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                     USB_OTG_DIEPMSK_BIM_Msk        /*!< BNA interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos            (0U)                           
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk            (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                USB_OTG_HPTXSTS_PTXFSAVL_Msk   /*!< Periodic transmit data FIFO space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos             (16U)                          
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                 USB_OTG_HPTXSTS_PTXQSAV_Msk    /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0               (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1               (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2               (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3               (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4               (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5               (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6               (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7               (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos             (24U)                          
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                 USB_OTG_HPTXSTS_PTXQTOP_Msk    /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0               (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1               (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2               (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3               (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4               (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5               (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6               (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7               (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                 (0U)                           
+#define USB_OTG_HAINT_HAINT_Msk                 (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                     USB_OTG_HAINT_HAINT_Msk        /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos               (0U)                           
+#define USB_OTG_DOEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                   USB_OTG_DOEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                (1U)                           
+#define USB_OTG_DOEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                    USB_OTG_DOEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
+#define USB_OTG_DOEPMSK_STUPM_Pos               (3U)                           
+#define USB_OTG_DOEPMSK_STUPM_Msk               (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                   USB_OTG_DOEPMSK_STUPM_Msk      /*!< SETUP phase done mask */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos              (4U)                           
+#define USB_OTG_DOEPMSK_OTEPDM_Msk              (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                  USB_OTG_DOEPMSK_OTEPDM_Msk     /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos             (6U)                           
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                 USB_OTG_DOEPMSK_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos                (8U)                           
+#define USB_OTG_DOEPMSK_OPEM_Msk                (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                    USB_OTG_DOEPMSK_OPEM_Msk       /*!< OUT packet error mask */
+#define USB_OTG_DOEPMSK_BOIM_Pos                (9U)                           
+#define USB_OTG_DOEPMSK_BOIM_Msk                (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                    USB_OTG_DOEPMSK_BOIM_Msk       /*!< BNA interrupt mask */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                (0U)                           
+#define USB_OTG_GINTSTS_CMOD_Msk                (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                    USB_OTG_GINTSTS_CMOD_Msk       /*!< Current mode of operation */
+#define USB_OTG_GINTSTS_MMIS_Pos                (1U)                           
+#define USB_OTG_GINTSTS_MMIS_Msk                (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                    USB_OTG_GINTSTS_MMIS_Msk       /*!< Mode mismatch interrupt */
+#define USB_OTG_GINTSTS_OTGINT_Pos              (2U)                           
+#define USB_OTG_GINTSTS_OTGINT_Msk              (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                  USB_OTG_GINTSTS_OTGINT_Msk     /*!< OTG interrupt */
+#define USB_OTG_GINTSTS_SOF_Pos                 (3U)                           
+#define USB_OTG_GINTSTS_SOF_Msk                 (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                     USB_OTG_GINTSTS_SOF_Msk        /*!< Start of frame */
+#define USB_OTG_GINTSTS_RXFLVL_Pos              (4U)                           
+#define USB_OTG_GINTSTS_RXFLVL_Msk              (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                  USB_OTG_GINTSTS_RXFLVL_Msk     /*!< RxFIFO nonempty */
+#define USB_OTG_GINTSTS_NPTXFE_Pos              (5U)                           
+#define USB_OTG_GINTSTS_NPTXFE_Msk              (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                  USB_OTG_GINTSTS_NPTXFE_Msk     /*!< Nonperiodic TxFIFO empty */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos            (6U)                           
+#define USB_OTG_GINTSTS_GINAKEFF_Msk            (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                USB_OTG_GINTSTS_GINAKEFF_Msk   /*!< Global IN nonperiodic NAK effective */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos          (7U)                           
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk          (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF              USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
+#define USB_OTG_GINTSTS_ESUSP_Pos               (10U)                          
+#define USB_OTG_GINTSTS_ESUSP_Msk               (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                   USB_OTG_GINTSTS_ESUSP_Msk      /*!< Early suspend */
+#define USB_OTG_GINTSTS_USBSUSP_Pos             (11U)                          
+#define USB_OTG_GINTSTS_USBSUSP_Msk             (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                 USB_OTG_GINTSTS_USBSUSP_Msk    /*!< USB suspend */
+#define USB_OTG_GINTSTS_USBRST_Pos              (12U)                          
+#define USB_OTG_GINTSTS_USBRST_Msk              (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                  USB_OTG_GINTSTS_USBRST_Msk     /*!< USB reset */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos             (13U)                          
+#define USB_OTG_GINTSTS_ENUMDNE_Msk             (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                 USB_OTG_GINTSTS_ENUMDNE_Msk    /*!< Enumeration done */
+#define USB_OTG_GINTSTS_ISOODRP_Pos             (14U)                          
+#define USB_OTG_GINTSTS_ISOODRP_Msk             (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                 USB_OTG_GINTSTS_ISOODRP_Msk    /*!< Isochronous OUT packet dropped interrupt */
+#define USB_OTG_GINTSTS_EOPF_Pos                (15U)                          
+#define USB_OTG_GINTSTS_EOPF_Msk                (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                    USB_OTG_GINTSTS_EOPF_Msk       /*!< End of periodic frame interrupt */
+#define USB_OTG_GINTSTS_IEPINT_Pos              (18U)                          
+#define USB_OTG_GINTSTS_IEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                  USB_OTG_GINTSTS_IEPINT_Msk     /*!< IN endpoint interrupt */
+#define USB_OTG_GINTSTS_OEPINT_Pos              (19U)                          
+#define USB_OTG_GINTSTS_OEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                  USB_OTG_GINTSTS_OEPINT_Msk     /*!< OUT endpoint interrupt */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos            (20U)                          
+#define USB_OTG_GINTSTS_IISOIXFR_Msk            (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                USB_OTG_GINTSTS_IISOIXFR_Msk   /*!< Incomplete isochronous IN transfer */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)                          
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos           (22U)                          
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk           (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP               USB_OTG_GINTSTS_DATAFSUSP_Msk  /*!< Data fetch suspended */
+#define USB_OTG_GINTSTS_HPRTINT_Pos             (24U)                          
+#define USB_OTG_GINTSTS_HPRTINT_Msk             (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                 USB_OTG_GINTSTS_HPRTINT_Msk    /*!< Host port interrupt */
+#define USB_OTG_GINTSTS_HCINT_Pos               (25U)                          
+#define USB_OTG_GINTSTS_HCINT_Msk               (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                   USB_OTG_GINTSTS_HCINT_Msk      /*!< Host channels interrupt */
+#define USB_OTG_GINTSTS_PTXFE_Pos               (26U)                          
+#define USB_OTG_GINTSTS_PTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                   USB_OTG_GINTSTS_PTXFE_Msk      /*!< Periodic TxFIFO empty */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos             (28U)                          
+#define USB_OTG_GINTSTS_CIDSCHG_Msk             (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                 USB_OTG_GINTSTS_CIDSCHG_Msk    /*!< Connector ID status change */
+#define USB_OTG_GINTSTS_DISCINT_Pos             (29U)                          
+#define USB_OTG_GINTSTS_DISCINT_Msk             (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                 USB_OTG_GINTSTS_DISCINT_Msk    /*!< Disconnect detected interrupt */
+#define USB_OTG_GINTSTS_SRQINT_Pos              (30U)                          
+#define USB_OTG_GINTSTS_SRQINT_Msk              (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                  USB_OTG_GINTSTS_SRQINT_Msk     /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos              (31U)                          
+#define USB_OTG_GINTSTS_WKUINT_Msk              (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                  USB_OTG_GINTSTS_WKUINT_Msk     /*!< Resume/remote wakeup detected interrupt */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos               (1U)                           
+#define USB_OTG_GINTMSK_MMISM_Msk               (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                   USB_OTG_GINTMSK_MMISM_Msk      /*!< Mode mismatch interrupt mask */
+#define USB_OTG_GINTMSK_OTGINT_Pos              (2U)                           
+#define USB_OTG_GINTMSK_OTGINT_Msk              (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                  USB_OTG_GINTMSK_OTGINT_Msk     /*!< OTG interrupt mask */
+#define USB_OTG_GINTMSK_SOFM_Pos                (3U)                           
+#define USB_OTG_GINTMSK_SOFM_Msk                (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                    USB_OTG_GINTMSK_SOFM_Msk       /*!< Start of frame mask */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos             (4U)                           
+#define USB_OTG_GINTMSK_RXFLVLM_Msk             (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                 USB_OTG_GINTMSK_RXFLVLM_Msk    /*!< Receive FIFO nonempty mask */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos             (5U)                           
+#define USB_OTG_GINTMSK_NPTXFEM_Msk             (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                 USB_OTG_GINTMSK_NPTXFEM_Msk    /*!< Nonperiodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos           (6U)                           
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM               USB_OTG_GINTMSK_GINAKEFFM_Msk  /*!< Global nonperiodic IN NAK effective mask */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos           (7U)                           
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM               USB_OTG_GINTMSK_GONAKEFFM_Msk  /*!< Global OUT NAK effective mask */
+#define USB_OTG_GINTMSK_ESUSPM_Pos              (10U)                          
+#define USB_OTG_GINTMSK_ESUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                  USB_OTG_GINTMSK_ESUSPM_Msk     /*!< Early suspend mask */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos            (11U)                          
+#define USB_OTG_GINTMSK_USBSUSPM_Msk            (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                USB_OTG_GINTMSK_USBSUSPM_Msk   /*!< USB suspend mask */
+#define USB_OTG_GINTMSK_USBRST_Pos              (12U)                          
+#define USB_OTG_GINTMSK_USBRST_Msk              (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                  USB_OTG_GINTMSK_USBRST_Msk     /*!< USB reset mask */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos            (13U)                          
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk            (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                USB_OTG_GINTMSK_ENUMDNEM_Msk   /*!< Enumeration done mask */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos            (14U)                          
+#define USB_OTG_GINTMSK_ISOODRPM_Msk            (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                USB_OTG_GINTMSK_ISOODRPM_Msk   /*!< Isochronous OUT packet dropped interrupt mask */
+#define USB_OTG_GINTMSK_EOPFM_Pos               (15U)                          
+#define USB_OTG_GINTMSK_EOPFM_Msk               (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                   USB_OTG_GINTMSK_EOPFM_Msk      /*!< End of periodic frame interrupt mask */
+#define USB_OTG_GINTMSK_EPMISM_Pos              (17U)                          
+#define USB_OTG_GINTMSK_EPMISM_Msk              (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                  USB_OTG_GINTMSK_EPMISM_Msk     /*!< Endpoint mismatch interrupt mask */
+#define USB_OTG_GINTMSK_IEPINT_Pos              (18U)                          
+#define USB_OTG_GINTMSK_IEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                  USB_OTG_GINTMSK_IEPINT_Msk     /*!< IN endpoints interrupt mask */
+#define USB_OTG_GINTMSK_OEPINT_Pos              (19U)                          
+#define USB_OTG_GINTMSK_OEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                  USB_OTG_GINTMSK_OEPINT_Msk     /*!< OUT endpoints interrupt mask */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos           (20U)                          
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk           (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM               USB_OTG_GINTMSK_IISOIXFRM_Msk  /*!< Incomplete isochronous IN transfer mask */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos     (21U)                          
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk     (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
+#define USB_OTG_GINTMSK_FSUSPM_Pos              (22U)                          
+#define USB_OTG_GINTMSK_FSUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                  USB_OTG_GINTMSK_FSUSPM_Msk     /*!< Data fetch suspended mask */
+#define USB_OTG_GINTMSK_PRTIM_Pos               (24U)                          
+#define USB_OTG_GINTMSK_PRTIM_Msk               (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                   USB_OTG_GINTMSK_PRTIM_Msk      /*!< Host port interrupt mask */
+#define USB_OTG_GINTMSK_HCIM_Pos                (25U)                          
+#define USB_OTG_GINTMSK_HCIM_Msk                (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                    USB_OTG_GINTMSK_HCIM_Msk       /*!< Host channels interrupt mask */
+#define USB_OTG_GINTMSK_PTXFEM_Pos              (26U)                          
+#define USB_OTG_GINTMSK_PTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                  USB_OTG_GINTMSK_PTXFEM_Msk     /*!< Periodic TxFIFO empty mask */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos            (28U)                          
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk            (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                USB_OTG_GINTMSK_CIDSCHGM_Msk   /*!< Connector ID status change mask */
+#define USB_OTG_GINTMSK_DISCINT_Pos             (29U)                          
+#define USB_OTG_GINTMSK_DISCINT_Msk             (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                 USB_OTG_GINTMSK_DISCINT_Msk    /*!< Disconnect detected interrupt mask */
+#define USB_OTG_GINTMSK_SRQIM_Pos               (30U)                          
+#define USB_OTG_GINTMSK_SRQIM_Msk               (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                   USB_OTG_GINTMSK_SRQIM_Msk      /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                (31U)                          
+#define USB_OTG_GINTMSK_WUIM_Msk                (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                    USB_OTG_GINTMSK_WUIM_Msk       /*!< Resume/remote wakeup detected interrupt mask */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                (0U)                           
+#define USB_OTG_DAINT_IEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                    USB_OTG_DAINT_IEPINT_Msk       /*!< IN endpoint interrupt bits */
+#define USB_OTG_DAINT_OEPINT_Pos                (16U)                          
+#define USB_OTG_DAINT_OEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                    USB_OTG_DAINT_OEPINT_Msk       /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos             (0U)                           
+#define USB_OTG_HAINTMSK_HAINTM_Msk             (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                 USB_OTG_HAINTMSK_HAINTM_Msk    /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos               (0U)                           
+#define USB_OTG_GRXSTSP_EPNUM_Msk               (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                   USB_OTG_GRXSTSP_EPNUM_Msk      /*!< IN EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_BCNT_Pos                (4U)                           
+#define USB_OTG_GRXSTSP_BCNT_Msk                (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                    USB_OTG_GRXSTSP_BCNT_Msk       /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                (15U)                          
+#define USB_OTG_GRXSTSP_DPID_Msk                (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                    USB_OTG_GRXSTSP_DPID_Msk       /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos              (17U)                          
+#define USB_OTG_GRXSTSP_PKTSTS_Msk              (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                  USB_OTG_GRXSTSP_PKTSTS_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos               (0U)                           
+#define USB_OTG_DAINTMSK_IEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                   USB_OTG_DAINTMSK_IEPM_Msk      /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos               (16U)                          
+#define USB_OTG_DAINTMSK_OEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                   USB_OTG_DAINTMSK_OEPM_Msk      /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                (0U)                           
+#define USB_OTG_GRXFSIZ_RXFD_Msk                (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                    USB_OTG_GRXFSIZ_RXFD_Msk       /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos             (0U)                           
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk             (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                 USB_OTG_DVBUSDIS_VBUSDT_Msk    /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                     (0U)                           
+#define USB_OTG_NPTXFSA_Msk                     (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                         USB_OTG_NPTXFSA_Msk            /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                      (16U)                          
+#define USB_OTG_NPTXFD_Msk                      (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                          USB_OTG_NPTXFD_Msk             /*!< Nonperiodic TxFIFO depth */
+#define USB_OTG_TX0FSA_Pos                      (0U)                           
+#define USB_OTG_TX0FSA_Msk                      (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                          USB_OTG_TX0FSA_Msk             /*!< Endpoint 0 transmit RAM start address */
+#define USB_OTG_TX0FD_Pos                       (16U)                          
+#define USB_OTG_TX0FD_Msk                       (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                           USB_OTG_TX0FD_Msk              /*!< Endpoint 0 TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos           (0U)                           
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk           (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP               USB_OTG_DVBUSPULSE_DVBUSP_Msk  /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos           (0U)                           
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk           (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV               USB_OTG_GNPTXSTS_NPTXFSAV_Msk  /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos           (16U)                          
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk           (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV               USB_OTG_GNPTXSTS_NPTQXSAV_Msk  /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0             (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1             (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2             (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3             (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4             (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5             (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6             (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7             (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos           (24U)                          
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk           (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP               USB_OTG_GNPTXSTS_NPTXQTOP_Msk  /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0             (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1             (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2             (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3             (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4             (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5             (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6             (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos         (0U)                           
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk         (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN             USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos            (1U)                           
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk            (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                USB_OTG_DTHRCTL_ISOTHREN_Msk   /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos            (2U)                           
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                USB_OTG_DTHRCTL_TXTHRLEN_Msk   /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos             (16U)                          
+#define USB_OTG_DTHRCTL_RXTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                 USB_OTG_DTHRCTL_RXTHREN_Msk    /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos            (17U)                          
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                USB_OTG_DTHRCTL_RXTHRLEN_Msk   /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos               (27U)                          
+#define USB_OTG_DTHRCTL_ARPEN_Msk               (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                   USB_OTG_DTHRCTL_ARPEN_Msk      /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos        (0U)                           
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk        (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM            USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos            (1U)                           
+#define USB_OTG_DEACHINT_IEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                USB_OTG_DEACHINT_IEP1INT_Msk   /*!< IN endpoint 1interrupt bit */
+#define USB_OTG_DEACHINT_OEP1INT_Pos            (17U)                          
+#define USB_OTG_DEACHINT_OEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                USB_OTG_DEACHINT_OEP1INT_Msk   /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos                (16U)                          
+#define USB_OTG_GCCFG_PWRDWN_Msk                (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                    USB_OTG_GCCFG_PWRDWN_Msk       /*!< Power down */
+#define USB_OTG_GCCFG_VBUSASEN_Pos              (18U)                          
+#define USB_OTG_GCCFG_VBUSASEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN                  USB_OTG_GCCFG_VBUSASEN_Msk     /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos              (19U)                          
+#define USB_OTG_GCCFG_VBUSBSEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN                  USB_OTG_GCCFG_VBUSBSEN_Msk     /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos              (20U)                          
+#define USB_OTG_GCCFG_SOFOUTEN_Msk              (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN                  USB_OTG_GCCFG_SOFOUTEN_Msk     /*!< SOF output enable */
+
+/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos        (1U)                           
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM            USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos        (17U)                          
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM            USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos              (0U)                           
+#define USB_OTG_CID_PRODUCT_ID_Msk              (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                  USB_OTG_CID_PRODUCT_ID_Msk     /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos          (0U)                           
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM              USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos           (1U)                           
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM               USB_OTG_DIEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos            (3U)                           
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                USB_OTG_DIEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK          USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos        (5U)                           
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM            USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos        (6U)                           
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM            USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos         (8U)                           
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM             USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos            (9U)                           
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                USB_OTG_DIEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos           (13U)                          
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM               USB_OTG_DIEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                  (0U)                           
+#define USB_OTG_HPRT_PCSTS_Msk                  (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                      USB_OTG_HPRT_PCSTS_Msk         /*!< Port connect status */
+#define USB_OTG_HPRT_PCDET_Pos                  (1U)                           
+#define USB_OTG_HPRT_PCDET_Msk                  (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                      USB_OTG_HPRT_PCDET_Msk         /*!< Port connect detected */
+#define USB_OTG_HPRT_PENA_Pos                   (2U)                           
+#define USB_OTG_HPRT_PENA_Msk                   (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                       USB_OTG_HPRT_PENA_Msk          /*!< Port enable */
+#define USB_OTG_HPRT_PENCHNG_Pos                (3U)                           
+#define USB_OTG_HPRT_PENCHNG_Msk                (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                    USB_OTG_HPRT_PENCHNG_Msk       /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                   (4U)                           
+#define USB_OTG_HPRT_POCA_Msk                   (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                       USB_OTG_HPRT_POCA_Msk          /*!< Port overcurrent active */
+#define USB_OTG_HPRT_POCCHNG_Pos                (5U)                           
+#define USB_OTG_HPRT_POCCHNG_Msk                (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                    USB_OTG_HPRT_POCCHNG_Msk       /*!< Port overcurrent change */
+#define USB_OTG_HPRT_PRES_Pos                   (6U)                           
+#define USB_OTG_HPRT_PRES_Msk                   (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                       USB_OTG_HPRT_PRES_Msk          /*!< Port resume */
+#define USB_OTG_HPRT_PSUSP_Pos                  (7U)                           
+#define USB_OTG_HPRT_PSUSP_Msk                  (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                      USB_OTG_HPRT_PSUSP_Msk         /*!< Port suspend */
+#define USB_OTG_HPRT_PRST_Pos                   (8U)                           
+#define USB_OTG_HPRT_PRST_Msk                   (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                       USB_OTG_HPRT_PRST_Msk          /*!< Port reset */
+
+#define USB_OTG_HPRT_PLSTS_Pos                  (10U)                          
+#define USB_OTG_HPRT_PLSTS_Msk                  (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                      USB_OTG_HPRT_PLSTS_Msk         /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                    (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                    (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                   (12U)                          
+#define USB_OTG_HPRT_PPWR_Msk                   (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                       USB_OTG_HPRT_PPWR_Msk          /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                  (13U)                          
+#define USB_OTG_HPRT_PTCTL_Msk                  (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                      USB_OTG_HPRT_PTCTL_Msk         /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                    (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                    (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                    (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                    (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                   (17U)                          
+#define USB_OTG_HPRT_PSPD_Msk                   (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                       USB_OTG_HPRT_PSPD_Msk          /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                     (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                     (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos          (0U)                           
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM              USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos           (1U)                           
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM               USB_OTG_DOEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos            (3U)                           
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                USB_OTG_DOEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK          USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos        (5U)                           
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM            USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos        (6U)                           
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM            USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos         (8U)                           
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM             USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos            (9U)                           
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                USB_OTG_DOEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos          (12U)                          
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM              USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos           (13U)                          
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM               USB_OTG_DOEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos          (14U)                          
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM              USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos              (0U)                           
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                  USB_OTG_HPTXFSIZ_PTXSA_Msk     /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos              (16U)                          
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                  USB_OTG_HPTXFSIZ_PTXFD_Msk     /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos               (0U)                           
+#define USB_OTG_DIEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                   USB_OTG_DIEPCTL_MPSIZ_Msk      /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos              (15U)                          
+#define USB_OTG_DIEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                  USB_OTG_DIEPCTL_USBAEP_Msk     /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos          (16U)                          
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk          (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID              USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos              (17U)                          
+#define USB_OTG_DIEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                  USB_OTG_DIEPCTL_NAKSTS_Msk     /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos               (18U)                          
+#define USB_OTG_DIEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                   USB_OTG_DIEPCTL_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos               (21U)                          
+#define USB_OTG_DIEPCTL_STALL_Msk               (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                   USB_OTG_DIEPCTL_STALL_Msk      /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos              (22U)                          
+#define USB_OTG_DIEPCTL_TXFNUM_Msk              (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                  USB_OTG_DIEPCTL_TXFNUM_Msk     /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                (26U)                          
+#define USB_OTG_DIEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                    USB_OTG_DIEPCTL_CNAK_Msk       /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                (27U)                          
+#define USB_OTG_DIEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                    USB_OTG_DIEPCTL_SNAK_Msk       /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos             (29U)                          
+#define USB_OTG_DIEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                 USB_OTG_DIEPCTL_SODDFRM_Msk    /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos               (30U)                          
+#define USB_OTG_DIEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                   USB_OTG_DIEPCTL_EPDIS_Msk      /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos               (31U)                          
+#define USB_OTG_DIEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                   USB_OTG_DIEPCTL_EPENA_Msk      /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                (0U)                           
+#define USB_OTG_HCCHAR_MPSIZ_Msk                (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                    USB_OTG_HCCHAR_MPSIZ_Msk       /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                (11U)                          
+#define USB_OTG_HCCHAR_EPNUM_Msk                (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                    USB_OTG_HCCHAR_EPNUM_Msk       /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                  (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                  (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                  (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                  (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                (15U)                          
+#define USB_OTG_HCCHAR_EPDIR_Msk                (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                    USB_OTG_HCCHAR_EPDIR_Msk       /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                (17U)                          
+#define USB_OTG_HCCHAR_LSDEV_Msk                (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                    USB_OTG_HCCHAR_LSDEV_Msk       /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                (18U)                          
+#define USB_OTG_HCCHAR_EPTYP_Msk                (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                    USB_OTG_HCCHAR_EPTYP_Msk       /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                  (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                  (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+                                      
+#define USB_OTG_HCCHAR_MC_Pos                   (20U)                          
+#define USB_OTG_HCCHAR_MC_Msk                   (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                       USB_OTG_HCCHAR_MC_Msk          /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                     (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                     (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                  (22U)                          
+#define USB_OTG_HCCHAR_DAD_Msk                  (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                      USB_OTG_HCCHAR_DAD_Msk         /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                    (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                    (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                    (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                    (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                    (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                    (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                    (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos               (29U)                          
+#define USB_OTG_HCCHAR_ODDFRM_Msk               (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                   USB_OTG_HCCHAR_ODDFRM_Msk      /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                (30U)                          
+#define USB_OTG_HCCHAR_CHDIS_Msk                (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                    USB_OTG_HCCHAR_CHDIS_Msk       /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                (31U)                          
+#define USB_OTG_HCCHAR_CHENA_Msk                (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                    USB_OTG_HCCHAR_CHENA_Msk       /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos              (0U)                           
+#define USB_OTG_HCSPLT_PRTADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                  USB_OTG_HCSPLT_PRTADDR_Msk     /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos              (7U)                           
+#define USB_OTG_HCSPLT_HUBADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                  USB_OTG_HCSPLT_HUBADDR_Msk     /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos              (14U)                          
+#define USB_OTG_HCSPLT_XACTPOS_Msk              (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                  USB_OTG_HCSPLT_XACTPOS_Msk     /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos            (16U)                          
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk            (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                USB_OTG_HCSPLT_COMPLSPLT_Msk   /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos              (31U)                          
+#define USB_OTG_HCSPLT_SPLITEN_Msk              (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                  USB_OTG_HCSPLT_SPLITEN_Msk     /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                  (0U)                           
+#define USB_OTG_HCINT_XFRC_Msk                  (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                      USB_OTG_HCINT_XFRC_Msk         /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                   (1U)                           
+#define USB_OTG_HCINT_CHH_Msk                   (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                       USB_OTG_HCINT_CHH_Msk          /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                (2U)                           
+#define USB_OTG_HCINT_AHBERR_Msk                (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                    USB_OTG_HCINT_AHBERR_Msk       /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                 (3U)                           
+#define USB_OTG_HCINT_STALL_Msk                 (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                     USB_OTG_HCINT_STALL_Msk        /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                   (4U)                           
+#define USB_OTG_HCINT_NAK_Msk                   (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                       USB_OTG_HCINT_NAK_Msk          /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                   (5U)                           
+#define USB_OTG_HCINT_ACK_Msk                   (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                       USB_OTG_HCINT_ACK_Msk          /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                  (6U)                           
+#define USB_OTG_HCINT_NYET_Msk                  (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                      USB_OTG_HCINT_NYET_Msk         /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                 (7U)                           
+#define USB_OTG_HCINT_TXERR_Msk                 (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                     USB_OTG_HCINT_TXERR_Msk        /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                 (8U)                           
+#define USB_OTG_HCINT_BBERR_Msk                 (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                     USB_OTG_HCINT_BBERR_Msk        /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                 (9U)                           
+#define USB_OTG_HCINT_FRMOR_Msk                 (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                     USB_OTG_HCINT_FRMOR_Msk        /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                 (10U)                          
+#define USB_OTG_HCINT_DTERR_Msk                 (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                     USB_OTG_HCINT_DTERR_Msk        /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                (0U)                           
+#define USB_OTG_DIEPINT_XFRC_Msk                (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                    USB_OTG_DIEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos              (1U)                           
+#define USB_OTG_DIEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                  USB_OTG_DIEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                 (3U)                           
+#define USB_OTG_DIEPINT_TOC_Msk                 (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                     USB_OTG_DIEPINT_TOC_Msk        /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos              (4U)                           
+#define USB_OTG_DIEPINT_ITTXFE_Msk              (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                  USB_OTG_DIEPINT_ITTXFE_Msk     /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos              (6U)                           
+#define USB_OTG_DIEPINT_INEPNE_Msk              (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                  USB_OTG_DIEPINT_INEPNE_Msk     /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                (7U)                           
+#define USB_OTG_DIEPINT_TXFE_Msk                (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                    USB_OTG_DIEPINT_TXFE_Msk       /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos          (8U)                           
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk          (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN              USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                 (9U)                           
+#define USB_OTG_DIEPINT_BNA_Msk                 (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                     USB_OTG_DIEPINT_BNA_Msk        /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos           (11U)                          
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk           (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS               USB_OTG_DIEPINT_PKTDRPSTS_Msk  /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                (12U)                          
+#define USB_OTG_DIEPINT_BERR_Msk                (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                    USB_OTG_DIEPINT_BERR_Msk       /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                 (13U)                          
+#define USB_OTG_DIEPINT_NAK_Msk                 (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                     USB_OTG_DIEPINT_NAK_Msk        /*!< NAK interrupt */
+
+/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos              (0U)                           
+#define USB_OTG_HCINTMSK_XFRCM_Msk              (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                  USB_OTG_HCINTMSK_XFRCM_Msk     /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos               (1U)                           
+#define USB_OTG_HCINTMSK_CHHM_Msk               (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                   USB_OTG_HCINTMSK_CHHM_Msk      /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos             (2U)                           
+#define USB_OTG_HCINTMSK_AHBERR_Msk             (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                 USB_OTG_HCINTMSK_AHBERR_Msk    /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos             (3U)                           
+#define USB_OTG_HCINTMSK_STALLM_Msk             (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                 USB_OTG_HCINTMSK_STALLM_Msk    /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos               (4U)                           
+#define USB_OTG_HCINTMSK_NAKM_Msk               (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                   USB_OTG_HCINTMSK_NAKM_Msk      /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos               (5U)                           
+#define USB_OTG_HCINTMSK_ACKM_Msk               (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                   USB_OTG_HCINTMSK_ACKM_Msk      /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos               (6U)                           
+#define USB_OTG_HCINTMSK_NYET_Msk               (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                   USB_OTG_HCINTMSK_NYET_Msk      /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos             (7U)                           
+#define USB_OTG_HCINTMSK_TXERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                 USB_OTG_HCINTMSK_TXERRM_Msk    /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos             (8U)                           
+#define USB_OTG_HCINTMSK_BBERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                 USB_OTG_HCINTMSK_BBERRM_Msk    /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos             (9U)                           
+#define USB_OTG_HCINTMSK_FRMORM_Msk             (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                 USB_OTG_HCINTMSK_FRMORM_Msk    /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos             (10U)                          
+#define USB_OTG_HCINTMSK_DTERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                 USB_OTG_HCINTMSK_DTERRM_Msk    /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos             (0U)                           
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                 USB_OTG_DIEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos             (19U)                          
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                 USB_OTG_DIEPTSIZ_PKTCNT_Msk    /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos             (29U)                          
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk             (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                 USB_OTG_DIEPTSIZ_MULCNT_Msk    /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos               (0U)                           
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk               (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                   USB_OTG_HCTSIZ_XFRSIZ_Msk      /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos               (19U)                          
+#define USB_OTG_HCTSIZ_PKTCNT_Msk               (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                   USB_OTG_HCTSIZ_PKTCNT_Msk      /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos               (31U)                          
+#define USB_OTG_HCTSIZ_DOPING_Msk               (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                   USB_OTG_HCTSIZ_DOPING_Msk      /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                 (29U)                          
+#define USB_OTG_HCTSIZ_DPID_Msk                 (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                     USB_OTG_HCTSIZ_DPID_Msk        /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos             (0U)                           
+#define USB_OTG_DIEPDMA_DMAADDR_Msk             (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                 USB_OTG_DIEPDMA_DMAADDR_Msk    /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos               (0U)                           
+#define USB_OTG_HCDMA_DMAADDR_Msk               (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                   USB_OTG_HCDMA_DMAADDR_Msk      /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos           (0U)                           
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk           (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos            (0U)                           
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                USB_OTG_DIEPTXF_INEPTXSA_Msk   /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos            (16U)                          
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                USB_OTG_DIEPTXF_INEPTXFD_Msk   /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos               (0U)                           
+#define USB_OTG_DOEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos              (15U)                          
+#define USB_OTG_DOEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                  USB_OTG_DOEPCTL_USBAEP_Msk     /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos              (17U)                          
+#define USB_OTG_DOEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                  USB_OTG_DOEPCTL_NAKSTS_Msk     /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM          USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos             (29U)                          
+#define USB_OTG_DOEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                 USB_OTG_DOEPCTL_SODDFRM_Msk    /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos               (18U)                          
+#define USB_OTG_DOEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                   USB_OTG_DOEPCTL_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                (20U)                          
+#define USB_OTG_DOEPCTL_SNPM_Msk                (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                    USB_OTG_DOEPCTL_SNPM_Msk       /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos               (21U)                          
+#define USB_OTG_DOEPCTL_STALL_Msk               (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                   USB_OTG_DOEPCTL_STALL_Msk      /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                (26U)                          
+#define USB_OTG_DOEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                    USB_OTG_DOEPCTL_CNAK_Msk       /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                (27U)                          
+#define USB_OTG_DOEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                    USB_OTG_DOEPCTL_SNAK_Msk       /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos               (30U)                          
+#define USB_OTG_DOEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                   USB_OTG_DOEPCTL_EPDIS_Msk      /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos               (31U)                          
+#define USB_OTG_DOEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                   USB_OTG_DOEPCTL_EPENA_Msk      /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                (0U)                           
+#define USB_OTG_DOEPINT_XFRC_Msk                (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                    USB_OTG_DOEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos              (1U)                           
+#define USB_OTG_DOEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                  USB_OTG_DOEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                (3U)                           
+#define USB_OTG_DOEPINT_STUP_Msk                (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                    USB_OTG_DOEPINT_STUP_Msk       /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos             (4U)                           
+#define USB_OTG_DOEPINT_OTEPDIS_Msk             (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                 USB_OTG_DOEPINT_OTEPDIS_Msk    /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos             (6U)                           
+#define USB_OTG_DOEPINT_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                 USB_OTG_DOEPINT_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                (14U)                          
+#define USB_OTG_DOEPINT_NYET_Msk                (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                    USB_OTG_DOEPINT_NYET_Msk       /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos             (0U)                           
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                 USB_OTG_DOEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos             (19U)                          
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                 USB_OTG_DOEPTSIZ_PKTCNT_Msk    /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos            (29U)                          
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk            (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                USB_OTG_DOEPTSIZ_STUPCNT_Msk   /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0              (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1              (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos             (0U)                           
+#define USB_OTG_PCGCCTL_STOPCLK_Msk             (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                 USB_OTG_PCGCCTL_STOPCLK_Msk    /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos             (1U)                           
+#define USB_OTG_PCGCCTL_GATECLK_Msk             (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                 USB_OTG_PCGCCTL_GATECLK_Msk    /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos             (4U)                           
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk             (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                 USB_OTG_PCGCCTL_PHYSUSP_Msk    /*!<Bit 1 */
+
+/* Legacy define */
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_CHNUM_Pos                       (0U)                           
+#define USB_OTG_CHNUM_Msk                       (0xFUL << USB_OTG_CHNUM_Pos)    /*!< 0x0000000F */
+#define USB_OTG_CHNUM                           USB_OTG_CHNUM_Msk              /*!< Channel number */
+#define USB_OTG_CHNUM_0                         (0x1UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                         (0x2UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                         (0x4UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                         (0x8UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                        (4U)                           
+#define USB_OTG_BCNT_Msk                        (0x7FFUL << USB_OTG_BCNT_Pos)   /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                            USB_OTG_BCNT_Msk               /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                        (15U)                          
+#define USB_OTG_DPID_Msk                        (0x3UL << USB_OTG_DPID_Pos)     /*!< 0x00018000 */
+#define USB_OTG_DPID                            USB_OTG_DPID_Msk               /*!< Data PID */
+#define USB_OTG_DPID_0                          (0x1UL << USB_OTG_DPID_Pos)     /*!< 0x00008000 */
+#define USB_OTG_DPID_1                          (0x2UL << USB_OTG_DPID_Pos)     /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                      (17U)                          
+#define USB_OTG_PKTSTS_Msk                      (0xFUL << USB_OTG_PKTSTS_Pos)   /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                          USB_OTG_PKTSTS_Msk             /*!< Packet status */
+#define USB_OTG_PKTSTS_0                        (0x1UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                        (0x2UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                        (0x4UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                        (0x8UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                       (0U)                           
+#define USB_OTG_EPNUM_Msk                       (0xFUL << USB_OTG_EPNUM_Pos)    /*!< 0x0000000F */
+#define USB_OTG_EPNUM                           USB_OTG_EPNUM_Msk              /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                         (0x1UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                         (0x2UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                         (0x4UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                         (0x8UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                      (21U)                          
+#define USB_OTG_FRMNUM_Msk                      (0xFUL << USB_OTG_FRMNUM_Pos)   /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                          USB_OTG_FRMNUM_Msk             /*!< Frame number */
+#define USB_OTG_FRMNUM_0                        (0x1UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                        (0x2UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                        (0x4UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                        (0x8UL << USB_OTG_FRMNUM_Pos)   /*!< 0x01000000 */
+
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif

From 32742571da065f0a075ac9e7cf8d0f0009f5ea4d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 00:06:57 +0700
Subject: [PATCH 0588/2085] switch gd32 and stm32f4 to use new dwc2 driver

---
 hw/bsp/gd32vf103/family.mk              |    2 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c   |  288 ++-
 src/portable/synopsys/dwc2/dwc2_gd32.h  |    7 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h |   15 +
 src/portable/synopsys/dwc2/dwc2_type.h  | 2578 ++++++++++++-----------
 5 files changed, 1516 insertions(+), 1374 deletions(-)

diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk
index 9148e7f8b..4de23ac17 100644
--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -35,7 +35,7 @@ CFLAGS += \
 CFLAGS += -Wno-error=unused-parameter
 
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \
 	$(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \
 	$(GD32VF103_SDK_DRIVER)/Usb/gd32vf103_usb_hw.c \
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 597f4c813..5811afa5a 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -52,26 +52,11 @@
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
-#if TUD_OPT_RHPORT == 0
-#define EP_MAX            EP_MAX_FS
-#define EP_FIFO_SIZE      EP_FIFO_SIZE_FS
-#define RHPORT_REGS_BASE  USB_OTG_FS_PERIPH_BASE
-#define RHPORT_IRQn       OTG_FS_IRQn
-
-#else
-#define EP_MAX            EP_MAX_HS
-#define EP_FIFO_SIZE      EP_FIFO_SIZE_HS
-#define RHPORT_REGS_BASE  USB_OTG_HS_PERIPH_BASE
-#define RHPORT_IRQn       OTG_HS_IRQn
-
-#endif
-
-#define GLOBAL_BASE(_port)     ((dwc2_core_t*) RHPORT_REGS_BASE)
-#define DEVICE_BASE(_port)     ((dwc2_device_t *) (RHPORT_REGS_BASE + USB_OTG_DEVICE_BASE))
-#define OUT_EP_BASE(_port)     ((dwc2_epout_t *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE))
-#define IN_EP_BASE(_port)      ((dwc2_epin_t *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE))
-#define FIFO_BASE(_port, _x)   ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
+#define GLOBAL_BASE(_port)     ((dwc2_core_t*) DWC2_REG_BASE)
+#define DEVICE_BASE(_port)     ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE))
+#define IN_EP_BASE(_port)      ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
+#define OUT_EP_BASE(_port)     ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
+#define FIFO_BASE(_port, _x)   ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
 
 enum
 {
@@ -139,17 +124,17 @@ static void bus_reset(uint8_t rhport)
   _out_ep_closed = false;
 
   // clear device address
-  dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
+  dev->DCFG &= ~DCFG_DAD_Msk;
 
   // 1. NAK for all OUT endpoints
   for(uint8_t n = 0; n < EP_MAX; n++) {
-    out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
+    out_ep[n].DOEPCTL |= DOEPCTL_SNAK;
   }
 
   // 2. Un-mask interrupt bits
-  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
-  dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
-  dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
+  dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
+  dev->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM;
+  dev->DIEPMSK = DIEPMSK_TOM | DIEPMSK_XFRCM;
 
   // "USB Data FIFOs" section in reference manual
   // Peripheral FIFO architecture
@@ -206,27 +191,27 @@ static void bus_reset(uint8_t rhport)
   _allocated_fifo_words_tx = 16;
 
   // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+  usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
-  in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
+  in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
   xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
 
-  out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
+  out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos);
 
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
+  usb_otg->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
 
 // Set turn-around timeout according to link speed
 extern uint32_t SystemCoreClock;
 static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed)
 {
-  usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
+  usb_otg->GUSBCFG &= ~GUSBCFG_TRDT;
 
   if ( speed == TUSB_SPEED_HIGH )
   {
     // Use fixed 0x09 for Highspeed
-    usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos);
+    usb_otg->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
   }
   else
   {
@@ -255,7 +240,7 @@ static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed)
       turnaround = 0xFU;
 
     // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos);
+    usb_otg->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
   }
 }
 
@@ -263,7 +248,7 @@ static tusb_speed_t get_speed(uint8_t rhport)
 {
   (void) rhport;
   dwc2_device_t * dev = DEVICE_BASE(rhport);
-  uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
+  uint32_t const enum_spd = (dev->DSTS & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos;
   return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
 }
 
@@ -283,8 +268,8 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
   dwc2_device_t * dev = DEVICE_BASE(rhport);
 
   // Clear and set speed bits
-  dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos);
-  dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos);
+  dev->DCFG &= ~(3 << DCFG_DSPD_Pos);
+  dev->DCFG |= (bitvalue << DCFG_DSPD_Pos);
 }
 
 #if defined(USB_HS_PHYC)
@@ -347,16 +332,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
   // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
   if(dir == TUSB_DIR_IN) {
     // A full IN transfer (multiple packets, possibly) triggers XFRC.
-    in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) |
-        ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk);
+    in_ep[epnum].DIEPTSIZ = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
+        ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
 
-    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK;
+    in_ep[epnum].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK;
     // For ISO endpoint set correct odd/even bit for next frame.
-    if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
+    if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
     {
       // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
-      in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk);
+      uint32_t const odd_frame_now = (dev->DSTS & (1u << DSTS_FNSOF_Pos));
+      in_ep[epnum].DIEPCTL |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
     }
     // Enable fifo empty interrupt only if there are something to put in the fifo.
     if(total_bytes != 0) {
@@ -364,16 +349,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
     }
   } else {
     // A full OUT transfer (multiple packets, possibly) triggers XFRC.
-    out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ);
-    out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) |
-        ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk);
+    out_ep[epnum].DOEPTSIZ &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
+    out_ep[epnum].DOEPTSIZ |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
+        ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
 
-    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
-    if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
+    out_ep[epnum].DOEPCTL |= DOEPCTL_EPENA | DOEPCTL_CNAK;
+    if ((out_ep[epnum].DOEPCTL & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
     {
       // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
-      out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk);
+      uint32_t const odd_frame_now = (dev->DSTS & (1u << DSTS_FNSOF_Pos));
+      out_ep[epnum].DOEPCTL |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
     }
   }
 }
@@ -385,7 +370,6 @@ void dcd_init (uint8_t rhport)
 {
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
-
   dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
 
   // No HNP/SRP (no OTG support), program timeout later.
@@ -394,23 +378,23 @@ void dcd_init (uint8_t rhport)
     // On selected MCUs HS port1 can be used with external PHY via ULPI interface
 #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
     // deactivate internal PHY
-    usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
+    usb_otg->GCCFG &= ~GCCFG_PWRDWN;
 
     // Init The UTMI Interface
-    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
+    usb_otg->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
 
     // Select default internal VBUS Indicator and Drive for ULPI
-    usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
+    usb_otg->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
 #else
-    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+    usb_otg->GUSBCFG |= GUSBCFG_PHYSEL;
 #endif
 
 #if defined(USB_HS_PHYC)
     // Highspeed with embedded UTMI PHYC
 
     // Select UTMI Interface
-    usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
-    usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
+    usb_otg->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL;
+    usb_otg->GCCFG |= GCCFG_PHYHSEN;
 
     // Enables control of a High Speed USB PHY
     USB_HS_PHYCInit();
@@ -418,17 +402,17 @@ void dcd_init (uint8_t rhport)
   } else
   {
     // Enable internal PHY
-    usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
+    usb_otg->GUSBCFG |= GUSBCFG_PHYSEL;
   }
 
-  // Reset core after selecting PHY
+  // Reset core after selecting PHYst
   // Wait AHB IDLE, reset then wait until it is cleared
-  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
-  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
+  while ((usb_otg->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {}
+  usb_otg->GRSTCTL |= GRSTCTL_CSRST;
+  while ((usb_otg->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
 
   // Restart PHY clock
-  *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
+  *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0;
 
   // Clear all interrupts
   usb_otg->GINTSTS |= usb_otg->GINTSTS;
@@ -436,25 +420,25 @@ void dcd_init (uint8_t rhport)
   // Required as part of core initialization.
   // TODO: How should mode mismatch be handled? It will cause
   // the core to stop working/require reset.
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM;
+  usb_otg->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM;
 
   dwc2_device_t * dev = DEVICE_BASE(rhport);
 
   // If USB host misbehaves during status portion of control xfer
   // (non zero-length packet), send STALL back and discard.
-  dev->DCFG |=  USB_OTG_DCFG_NZLSOHSK;
+  dev->DCFG |=  DCFG_NZLSOHSK;
 
   set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
 
   // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
+  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= GCCFG_PWRDWN;
 
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST   | USB_OTG_GINTMSK_ENUMDNEM |
-      USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM     |
-      USB_OTG_GINTMSK_RXFLVLM  | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0);
+  usb_otg->GINTMSK |= GINTMSK_USBRST   | GINTMSK_ENUMDNEM |
+      GINTMSK_USBSUSPM | GINTMSK_WUIM     |
+      GINTMSK_RXFLVLM  | (USE_SOF ? GINTMSK_SOFM : 0);
 
   // Enable global interrupt
-  usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
+  usb_otg->GAHBCFG |= GAHBCFG_GINT;
 
   dcd_connect(rhport);
 }
@@ -474,7 +458,7 @@ void dcd_int_disable (uint8_t rhport)
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
   dwc2_device_t * dev = DEVICE_BASE(rhport);
-  dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos);
+  dev->DCFG = (dev->DCFG & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
 
   // Response with status after changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
@@ -498,30 +482,30 @@ void dcd_remote_wakeup(uint8_t rhport)
   dwc2_device_t * dev = DEVICE_BASE(rhport);
 
   // set remote wakeup
-  dev->DCTL |= USB_OTG_DCTL_RWUSIG;
+  dev->DCTL |= DCTL_RWUSIG;
 
   // enable SOF to detect bus resume
-  usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM;
+  usb_otg->GINTSTS = GINTSTS_SOF;
+  usb_otg->GINTMSK |= GINTMSK_SOFM;
 
   // Per specs: remote wakeup signal bit must be clear within 1-15ms
   remote_wakeup_delay();
 
-  dev->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+  dev->DCTL &= ~DCTL_RWUSIG;
 }
 
 void dcd_connect(uint8_t rhport)
 {
   (void) rhport;
   dwc2_device_t * dev = DEVICE_BASE(rhport);
-  dev->DCTL &= ~USB_OTG_DCTL_SDIS;
+  dev->DCTL &= ~DCTL_SDIS;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
   (void) rhport;
   dwc2_device_t * dev = DEVICE_BASE(rhport);
-  dev->DCTL |= USB_OTG_DCTL_SDIS;
+  dev->DCTL |= DCTL_SDIS;
 }
 
 
@@ -563,12 +547,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
       usb_otg->GRXFSIZ = sz;
     }
 
-    out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos)        |
-        (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos)   |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
-        (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos);
+    out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos)        |
+        (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos)   |
+        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
+        (xfer->max_size << DOEPCTL_MPSIZ_Pos);
 
-    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
+    dev->DAINTMSK |= (1 << (DAINTMSK_OEPM_Pos + epnum));
   }
   else
   {
@@ -602,15 +586,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 
     // DIEPTXF starts at FIFO #1.
     // Both TXFD and TXSA are in unit of 32-bit words.
-    usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+    usb_otg->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
-    in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
-        (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
-        (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
-        (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos);
+    in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) |
+        (epnum << DIEPCTL_TXFNUM_Pos) |
+        (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
+        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
+        (xfer->max_size << DIEPCTL_MPSIZ_Pos);
 
-    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
+    dev->DAINTMSK |= (1 << (DAINTMSK_IEPM_Pos + epnum));
   }
 
   return true;
@@ -627,7 +611,7 @@ void dcd_edpt_close_all (uint8_t rhport)
   dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
 
   // Disable non-control interrupt
-  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
+  dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
 
   for(uint8_t n = 1; n < EP_MAX; n++)
   {
@@ -719,42 +703,42 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
 
   if(dir == TUSB_DIR_IN) {
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0);
+    if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & DIEPCTL_EPENA) ){
+      in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
     } else {
       // Stop transmitting packets and NAK IN xfers.
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
-      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0);
+      in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK;
+      while((in_ep[epnum].DIEPINT & DIEPINT_INEPNE) == 0);
 
       // Disable the endpoint.
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0);
-      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0);
-      in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD;
+      in_ep[epnum].DIEPCTL |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+      while((in_ep[epnum].DIEPINT & DIEPINT_EPDISD_Msk) == 0);
+      in_ep[epnum].DIEPINT = DIEPINT_EPDISD;
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
-    usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos);
-    usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
-    while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
+    usb_otg->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos);
+    usb_otg->GRSTCTL |= GRSTCTL_TXFFLSH;
+    while((usb_otg->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0);
   } else {
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){
-      out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0;
+    if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) ){
+      out_ep[epnum].DOEPCTL |= stall ? DOEPCTL_STALL : 0;
     } else {
       // Asserting GONAK is required to STALL an OUT endpoint.
       // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
       // anyway, and it can't be cleared by user code. If this while loop never
       // finishes, we have bigger problems than just the stack.
-      dev->DCTL |= USB_OTG_DCTL_SGONAK;
-      while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
+      dev->DCTL |= DCTL_SGONAK;
+      while((usb_otg->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0);
 
       // Ditto here- disable the endpoint.
-      out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0);
-      while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0);
-      out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD;
+      out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+      while((out_ep[epnum].DOEPINT & DOEPINT_EPDISD_Msk) == 0);
+      out_ep[epnum].DOEPINT = DOEPINT_EPDISD;
 
       // Allow other OUT endpoints to keep receiving.
-      dev->DCTL |= USB_OTG_DCTL_CGONAK;
+      dev->DCTL |= DCTL_CGONAK;
     }
   }
 }
@@ -776,8 +760,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 
   if (dir == TUSB_DIR_IN)
   {
-    uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos;
-    uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos;
+    uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
+    uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
     // For now only the last opened endpoint can be closed without fuss.
     TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
     _allocated_fifo_words_tx -= fifo_size;
@@ -805,11 +789,11 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 
   // Clear stall and reset data toggle
   if(dir == TUSB_DIR_IN) {
-    in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
+    in_ep[epnum].DIEPCTL &= ~DIEPCTL_STALL;
+    in_ep[epnum].DIEPCTL |= DIEPCTL_SD0PID_SEVNFRM;
   } else {
-    out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
-    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
+    out_ep[epnum].DOEPCTL &= ~DOEPCTL_STALL;
+    out_ep[epnum].DOEPCTL |= DOEPCTL_SD0PID_SEVNFRM;
   }
 }
 
@@ -882,9 +866,9 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
 
   // Pop control word off FIFO
   uint32_t ctl_word = usb_otg->GRXSTSP;
-  uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos;
-  uint8_t epnum = (ctl_word &  USB_OTG_GRXSTSP_EPNUM_Msk) >>  USB_OTG_GRXSTSP_EPNUM_Pos;
-  uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos;
+  uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
+  uint8_t epnum = (ctl_word &  GRXSTSP_EPNUM_Msk) >>  GRXSTSP_EPNUM_Pos;
+  uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
 
   switch(pktsts) {
     case 0x01: // Global OUT NAK (Interrupt)
@@ -911,7 +895,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
 
       // Truncate transfer length in case of short packet
       if(bcnt < xfer->max_size) {
-        xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
+        xfer->total_len -= (out_ep[epnum].DOEPTSIZ & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
         if(epnum == 0) {
           xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
           ep0_pending[TUSB_DIR_OUT] = 0;
@@ -924,7 +908,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
       break;
 
     case 0x04: // Setup packet done (Interrupt)
-      out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
+      out_ep[epnum].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos);
       break;
 
     case 0x06: // Setup packet recvd
@@ -946,16 +930,16 @@ static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t
   for(uint8_t n = 0; n < EP_MAX; n++) {
     xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
 
-    if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) {
+    if(dev->DAINT & (1 << (DAINT_OEPINT_Pos + n))) {
       // SETUP packet Setup Phase done.
-      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) {
-        out_ep[n].DOEPINT =  USB_OTG_DOEPINT_STUP;
+      if(out_ep[n].DOEPINT & DOEPINT_STUP) {
+        out_ep[n].DOEPINT =  DOEPINT_STUP;
         dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
       }
 
       // OUT XFER complete
-      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) {
-        out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC;
+      if(out_ep[n].DOEPINT & DOEPINT_XFRC) {
+        out_ep[n].DOEPINT = DOEPINT_XFRC;
 
         // EP0 can only handle one packet
         if((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
@@ -976,12 +960,12 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
   {
     xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
 
-    if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) )
+    if ( dev->DAINT & (1 << (DAINT_IEPINT_Pos + n)) )
     {
       // IN XFER complete (entire xfer).
-      if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC )
+      if ( in_ep[n].DIEPINT & DIEPINT_XFRC )
       {
-        in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC;
+        in_ep[n].DIEPINT = DIEPINT_XFRC;
 
         // EP0 can only handle one packet
         if((n == 0) && ep0_pending[TUSB_DIR_IN]) {
@@ -993,26 +977,26 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
       }
 
       // XFER FIFO empty
-      if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
+      if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
       {
         // DIEPINT's TXFE bit is read-only, software cannot clear it.
         // It will only be cleared by hardware when written bytes is more than
         // - 64 bytes or
         // - Half of TX FIFO size (configured by DIEPTXF)
 
-        uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos;
+        uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
 
         // Process every single packet (only whole packets can be written to fifo)
         for(uint16_t i = 0; i < remaining_packets; i++)
         {
-          uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos;
+          uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
 
           // Packet can not be larger than ep max size
           uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
 
           // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
           // EP has to be checked if the buffer can take another WHOLE packet
-          if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break;
+          if(packet_size > ((in_ep[n].DTXFSTS & DTXFSTS_INEPTFSAV_Msk) << 2)) break;
 
           // Push packet to Tx-FIFO
           if (xfer->ff)
@@ -1030,7 +1014,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
         }
 
         // Turn off TXFE if all bytes are written.
-        if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0)
+        if (((in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0)
         {
           dev->DIEPEMPMSK &= ~(1 << n);
         }
@@ -1048,18 +1032,18 @@ void dcd_int_handler(uint8_t rhport)
 
   uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
 
-  if(int_status & USB_OTG_GINTSTS_USBRST)
+  if(int_status & GINTSTS_USBRST)
   {
     // USBRST is start of reset.
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST;
+    usb_otg->GINTSTS = GINTSTS_USBRST;
     bus_reset(rhport);
   }
 
-  if(int_status & USB_OTG_GINTSTS_ENUMDNE)
+  if(int_status & GINTSTS_ENUMDNE)
   {
     // ENUMDNE is the end of reset where speed of the link is detected
 
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
+    usb_otg->GINTSTS = GINTSTS_ENUMDNE;
 
     tusb_speed_t const speed = get_speed(rhport);
 
@@ -1067,27 +1051,27 @@ void dcd_int_handler(uint8_t rhport)
     dcd_event_bus_reset(rhport, speed, true);
   }
 
-  if(int_status & USB_OTG_GINTSTS_USBSUSP)
+  if(int_status & GINTSTS_USBSUSP)
   {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP;
+    usb_otg->GINTSTS = GINTSTS_USBSUSP;
     dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
   }
 
-  if(int_status & USB_OTG_GINTSTS_WKUINT)
+  if(int_status & GINTSTS_WKUINT)
   {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT;
+    usb_otg->GINTSTS = GINTSTS_WKUINT;
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
   }
 
-  // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection
-  // if(int_status & USB_OTG_GINTSTS_DISCINT)
+  // TODO check GINTSTS_DISCINT for disconnect detection
+  // if(int_status & GINTSTS_DISCINT)
 
-  if(int_status & USB_OTG_GINTSTS_OTGINT)
+  if(int_status & GINTSTS_OTGINT)
   {
     // OTG INT bit is read-only
     uint32_t const otg_int = usb_otg->GOTGINT;
 
-    if (otg_int & USB_OTG_GOTGINT_SEDET)
+    if (otg_int & GOTGINT_SEDET)
     {
       dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
     }
@@ -1095,29 +1079,29 @@ void dcd_int_handler(uint8_t rhport)
     usb_otg->GOTGINT = otg_int;
   }
 
-  if(int_status & USB_OTG_GINTSTS_SOF)
+  if(int_status & GINTSTS_SOF)
   {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
+    usb_otg->GINTSTS = GINTSTS_SOF;
 
     // Disable SOF interrupt since currently only used for remote wakeup detection
-    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM;
+    usb_otg->GINTMSK &= ~GINTMSK_SOFM;
 
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
 
   // RxFIFO non-empty interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_RXFLVL)
+  if(int_status & GINTSTS_RXFLVL)
   {
     // RXFLVL bit is read-only
 
     // Mask out RXFLVL while reading data from FIFO
-    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM;
+    usb_otg->GINTMSK &= ~GINTMSK_RXFLVLM;
 
     // Loop until all available packets were handled
     do
     {
       handle_rxflvl_ints(rhport, out_ep);
-    } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL);
+    } while(usb_otg->GINTSTS & GINTSTS_RXFLVL);
 
     // Manage RX FIFO size
     if (_out_ep_closed)
@@ -1128,25 +1112,25 @@ void dcd_int_handler(uint8_t rhport)
       _out_ep_closed = false;
     }
 
-    usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+    usb_otg->GINTMSK |= GINTMSK_RXFLVLM;
   }
 
   // OUT endpoint interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_OEPINT)
+  if(int_status & GINTSTS_OEPINT)
   {
     // OEPINT is read-only
     handle_epout_ints(rhport, dev, out_ep);
   }
 
   // IN endpoint interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_IEPINT)
+  if(int_status & GINTSTS_IEPINT)
   {
     // IEPINT bit read-only
     handle_epin_ints(rhport, dev, in_ep);
   }
 
   //  // Check for Incomplete isochronous IN transfer
-  //  if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
+  //  if(int_status & GINTSTS_IISOIXFR) {
   //    printf("      IISOIXFR!\r\n");
   ////    TU_LOG2("      IISOIXFR!\r\n");
   //  }
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index 5abbd225f..3ace4d484 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -32,9 +32,10 @@
 #define __NOP()   __asm volatile ("nop")
 
 // These numbers are the same for the whole GD32VF103 family.
-#define OTG_FS_IRQn     86
-#define EP_MAX_FS       4
-#define EP_FIFO_SIZE_FS 1280
+#define RHPORT_IRQn     86
+#define EP_MAX          4
+#define EP_FIFO_SIZE    1280
+#define DWC2_REG_BASE   0x50000000UL
 
 // The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
 // Interrupt Controller by Nuclei. It is nearly API compatible to the
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index efed6d14a..3a5e1a9ac 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -69,4 +69,19 @@
   #error "Unsupported MCUs"
 #endif
 
+// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
+#if TUD_OPT_RHPORT == 0
+  #define EP_MAX            EP_MAX_FS
+  #define EP_FIFO_SIZE      EP_FIFO_SIZE_FS
+  #define DWC2_REG_BASE     USB_OTG_FS_PERIPH_BASE
+  #define RHPORT_IRQn       OTG_FS_IRQn
+
+#else
+  #define EP_MAX            EP_MAX_HS
+  #define EP_FIFO_SIZE      EP_FIFO_SIZE_HS
+  #define DWC2_REG_BASE     USB_OTG_HS_PERIPH_BASE
+  #define RHPORT_IRQn       OTG_HS_IRQn
+
+#endif
+
 #endif /* DWC2_STM32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 8f48c71eb..5f3b4a420 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -39,14 +39,14 @@
 typedef struct
 {
 
-__IO uint32_t USB_HS_PHYC_PLL;         /*!< This register is used to control the PLL of the HS PHY.                       000h */
+__IO uint32_t HS_PHYC_PLL;         /*!< This register is used to control the PLL of the HS PHY.                       000h */
 __IO uint32_t Reserved04;              /*!< Reserved                                                                      004h */
 __IO uint32_t Reserved08;              /*!< Reserved                                                                      008h */
-__IO uint32_t USB_HS_PHYC_TUNE;        /*!< This register is used to control the tuning interface of the High Speed PHY.  00Ch */
+__IO uint32_t HS_PHYC_TUNE;        /*!< This register is used to control the tuning interface of the High Speed PHY.  00Ch */
 __IO uint32_t Reserved10;              /*!< Reserved                                                                      010h */
 __IO uint32_t Reserved14;              /*!< Reserved                                                                      014h */
-__IO uint32_t USB_HS_PHYC_LDO;         /*!< This register is used to control the regulator (LDO).                         018h */
-} USB_HS_PHYC_GlobalTypeDef;
+__IO uint32_t HS_PHYC_LDO;         /*!< This register is used to control the regulator (LDO).                         018h */
+} HS_PHYC_GlobalTypeDef;
 #endif
 
 // Core
@@ -156,7 +156,10 @@ typedef struct
 } dwc2_epout_t;
 
 
-/*!< USB registers base address */
+//--------------------------------------------------------------------+
+// Register Base Address
+//--------------------------------------------------------------------+
+
 #define DWC2_GLOBAL_BASE                  0x00000000UL
 #define DWC2_DEVICE_BASE                  0x00000800UL
 #define DWC2_IN_ENDPOINT_BASE             0x00000900UL
@@ -170,1299 +173,1438 @@ typedef struct
 #define DWC2_FIFO_BASE                    0x00001000UL
 #define DWC2_FIFO_SIZE                    0x00001000UL
 
-#if 0
-/******************************************************************************/
-/*                                                                            */
-/*                                 USB_OTG                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
-#define USB_OTG_GOTGCTL_SRQSCS_Pos              (0U)                           
-#define USB_OTG_GOTGCTL_SRQSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
-#define USB_OTG_GOTGCTL_SRQSCS                  USB_OTG_GOTGCTL_SRQSCS_Msk     /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ_Pos                 (1U)                           
-#define USB_OTG_GOTGCTL_SRQ_Msk                 (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
-#define USB_OTG_GOTGCTL_SRQ                     USB_OTG_GOTGCTL_SRQ_Msk        /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS_Pos              (8U)                           
-#define USB_OTG_GOTGCTL_HNGSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
-#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ_Pos               (9U)                           
-#define USB_OTG_GOTGCTL_HNPRQ_Msk               (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
-#define USB_OTG_GOTGCTL_HNPRQ                   USB_OTG_GOTGCTL_HNPRQ_Msk      /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN_Pos             (10U)                          
-#define USB_OTG_GOTGCTL_HSHNPEN_Msk             (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_GOTGCTL_HSHNPEN                 USB_OTG_GOTGCTL_HSHNPEN_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN_Pos              (11U)                          
-#define USB_OTG_GOTGCTL_DHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
-#define USB_OTG_GOTGCTL_DHNPEN                  USB_OTG_GOTGCTL_DHNPEN_Msk     /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS_Pos              (16U)                          
-#define USB_OTG_GOTGCTL_CIDSTS_Msk              (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
-#define USB_OTG_GOTGCTL_CIDSTS                  USB_OTG_GOTGCTL_CIDSTS_Msk     /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT_Pos                (17U)                          
-#define USB_OTG_GOTGCTL_DBCT_Msk                (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
-#define USB_OTG_GOTGCTL_DBCT                    USB_OTG_GOTGCTL_DBCT_Msk       /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD_Pos               (18U)                          
-#define USB_OTG_GOTGCTL_ASVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
-#define USB_OTG_GOTGCTL_ASVLD                   USB_OTG_GOTGCTL_ASVLD_Msk      /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD_Pos               (19U)                          
-#define USB_OTG_GOTGCTL_BSVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
-#define USB_OTG_GOTGCTL_BSVLD                   USB_OTG_GOTGCTL_BSVLD_Msk      /*!< B-session valid */
+//--------------------------------------------------------------------+
+// Register Bit Definitions
+//--------------------------------------------------------------------+
 
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
+/********************  Bit definition for GOTGCTL register  ********************/
+#define GOTGCTL_SRQSCS_Pos               (0U)
+#define GOTGCTL_SRQSCS_Msk               (0x1UL << GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define GOTGCTL_SRQSCS                   GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define GOTGCTL_SRQ_Pos                  (1U)
+#define GOTGCTL_SRQ_Msk                  (0x1UL << GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define GOTGCTL_SRQ                      GOTGCTL_SRQ_Msk       /*!< Session request */
+#define GOTGCTL_VBVALOEN_Pos             (2U)
+#define GOTGCTL_VBVALOEN_Msk             (0x1UL << GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define GOTGCTL_VBVALOEN                 GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define GOTGCTL_VBVALOVAL_Pos            (3U)
+#define GOTGCTL_VBVALOVAL_Msk            (0x1UL << GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define GOTGCTL_VBVALOVAL                GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define GOTGCTL_AVALOEN_Pos              (4U)
+#define GOTGCTL_AVALOEN_Msk              (0x1UL << GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define GOTGCTL_AVALOEN                  GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define GOTGCTL_AVALOVAL_Pos             (5U)
+#define GOTGCTL_AVALOVAL_Msk             (0x1UL << GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define GOTGCTL_AVALOVAL                 GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define GOTGCTL_BVALOEN_Pos              (6U)
+#define GOTGCTL_BVALOEN_Msk              (0x1UL << GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define GOTGCTL_BVALOEN                  GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define GOTGCTL_BVALOVAL_Pos             (7U)
+#define GOTGCTL_BVALOVAL_Msk             (0x1UL << GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define GOTGCTL_BVALOVAL                 GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define GOTGCTL_HNGSCS_Pos               (8U)
+#define GOTGCTL_HNGSCS_Msk               (0x1UL << GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define GOTGCTL_HNGSCS                   GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define GOTGCTL_HNPRQ_Pos                (9U)
+#define GOTGCTL_HNPRQ_Msk                (0x1UL << GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define GOTGCTL_HNPRQ                    GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define GOTGCTL_HSHNPEN_Pos              (10U)
+#define GOTGCTL_HSHNPEN_Msk              (0x1UL << GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define GOTGCTL_HSHNPEN                  GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define GOTGCTL_DHNPEN_Pos               (11U)
+#define GOTGCTL_DHNPEN_Msk               (0x1UL << GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define GOTGCTL_DHNPEN                   GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define GOTGCTL_EHEN_Pos                 (12U)
+#define GOTGCTL_EHEN_Msk                 (0x1UL << GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define GOTGCTL_EHEN                     GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define GOTGCTL_CIDSTS_Pos               (16U)
+#define GOTGCTL_CIDSTS_Msk               (0x1UL << GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define GOTGCTL_CIDSTS                   GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define GOTGCTL_DBCT_Pos                 (17U)
+#define GOTGCTL_DBCT_Msk                 (0x1UL << GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define GOTGCTL_DBCT                     GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define GOTGCTL_ASVLD_Pos                (18U)
+#define GOTGCTL_ASVLD_Msk                (0x1UL << GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define GOTGCTL_ASVLD                    GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define GOTGCTL_BSESVLD_Pos              (19U)
+#define GOTGCTL_BSESVLD_Msk              (0x1UL << GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define GOTGCTL_BSESVLD                  GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define GOTGCTL_OTGVER_Pos               (20U)
+#define GOTGCTL_OTGVER_Msk               (0x1UL << GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define GOTGCTL_OTGVER                   GOTGCTL_OTGVER_Msk    /*!< OTG version  */
 
-#define USB_OTG_HCFG_FSLSPCS_Pos                (0U)                           
-#define USB_OTG_HCFG_FSLSPCS_Msk                (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
-#define USB_OTG_HCFG_FSLSPCS                    USB_OTG_HCFG_FSLSPCS_Msk       /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0                  (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCFG_FSLSPCS_1                  (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCFG_FSLSS_Pos                  (2U)                           
-#define USB_OTG_HCFG_FSLSS_Msk                  (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCFG_FSLSS                      USB_OTG_HCFG_FSLSS_Msk         /*!< FS- and LS-only support */
+/********************  Bit definition for HCFG register  ********************/
+#define HCFG_FSLSPCS_Pos                 (0U)
+#define HCFG_FSLSPCS_Msk                 (0x3UL << HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define HCFG_FSLSPCS                     HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define HCFG_FSLSPCS_0                   (0x1UL << HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define HCFG_FSLSPCS_1                   (0x2UL << HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define HCFG_FSLSS_Pos                   (2U)
+#define HCFG_FSLSS_Msk                   (0x1UL << HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define HCFG_FSLSS                       HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
 
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
+/********************  Bit definition for DCFG register  ********************/
+#define DCFG_DSPD_Pos                    (0U)
+#define DCFG_DSPD_Msk                    (0x3UL << DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define DCFG_DSPD                        DCFG_DSPD_Msk         /*!< Device speed */
+#define DCFG_DSPD_0                      (0x1UL << DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define DCFG_DSPD_1                      (0x2UL << DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define DCFG_NZLSOHSK_Pos                (2U)
+#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DSPD_Pos                   (0U)                           
-#define USB_OTG_DCFG_DSPD_Msk                   (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
-#define USB_OTG_DCFG_DSPD                       USB_OTG_DCFG_DSPD_Msk          /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                     (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
-#define USB_OTG_DCFG_DSPD_1                     (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCFG_NZLSOHSK_Pos               (2U)                           
-#define USB_OTG_DCFG_NZLSOHSK_Msk               (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
-#define USB_OTG_DCFG_NZLSOHSK                   USB_OTG_DCFG_NZLSOHSK_Msk      /*!< Nonzero-length status OUT handshake */
+#define DCFG_DAD_Pos                     (4U)
+#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define DCFG_DAD                         DCFG_DAD_Msk          /*!< Device address */
+#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos) /*!< 0x00000010 */
+#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos) /*!< 0x00000020 */
+#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos) /*!< 0x00000040 */
+#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos) /*!< 0x00000080 */
+#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos) /*!< 0x00000100 */
+#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos) /*!< 0x00000200 */
+#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos) /*!< 0x00000400 */
 
-#define USB_OTG_DCFG_DAD_Pos                    (4U)                           
-#define USB_OTG_DCFG_DAD_Msk                    (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                        USB_OTG_DCFG_DAD_Msk           /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                      (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
-#define USB_OTG_DCFG_DAD_1                      (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
-#define USB_OTG_DCFG_DAD_2                      (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCFG_DAD_3                      (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
-#define USB_OTG_DCFG_DAD_4                      (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
-#define USB_OTG_DCFG_DAD_5                      (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
-#define USB_OTG_DCFG_DAD_6                      (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+#define DCFG_PFIVL_Pos                   (11U)
+#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define DCFG_PFIVL                       DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
-#define USB_OTG_DCFG_PFIVL_Pos                  (11U)                          
-#define USB_OTG_DCFG_PFIVL_Msk                  (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                      USB_OTG_DCFG_PFIVL_Msk         /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                    (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
-#define USB_OTG_DCFG_PFIVL_1                    (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+#define DCFG_PERSCHIVL_Pos               (24U)
+#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
-#define USB_OTG_DCFG_PERSCHIVL_Pos              (24U)                          
-#define USB_OTG_DCFG_PERSCHIVL_Msk              (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                  USB_OTG_DCFG_PERSCHIVL_Msk     /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0                (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
-#define USB_OTG_DCFG_PERSCHIVL_1                (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+/********************  Bit definition for PCGCR register  ********************/
+#define PCGCR_STPPCLK_Pos                (0U)
+#define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define PCGCR_STPPCLK                    PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define PCGCR_GATEHCLK_Pos               (1U)
+#define PCGCR_GATEHCLK_Msk               (0x1UL << PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define PCGCR_GATEHCLK                   PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define PCGCR_PHYSUSP_Pos                (4U)
+#define PCGCR_PHYSUSP_Msk                (0x1UL << PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define PCGCR_PHYSUSP                    PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
 
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK_Pos               (0U)                           
-#define USB_OTG_PCGCR_STPPCLK_Msk               (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
-#define USB_OTG_PCGCR_STPPCLK                   USB_OTG_PCGCR_STPPCLK_Msk      /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK_Pos              (1U)                           
-#define USB_OTG_PCGCR_GATEHCLK_Msk              (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
-#define USB_OTG_PCGCR_GATEHCLK                  USB_OTG_PCGCR_GATEHCLK_Msk     /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP_Pos               (4U)                           
-#define USB_OTG_PCGCR_PHYSUSP_Msk               (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
-#define USB_OTG_PCGCR_PHYSUSP                   USB_OTG_PCGCR_PHYSUSP_Msk      /*!< PHY suspended */
+/********************  Bit definition for GOTGINT register  ********************/
+#define GOTGINT_SEDET_Pos                (2U)
+#define GOTGINT_SEDET_Msk                (0x1UL << GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define GOTGINT_SEDET                    GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define GOTGINT_SRSSCHG_Pos              (8U)
+#define GOTGINT_SRSSCHG_Msk              (0x1UL << GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define GOTGINT_SRSSCHG                  GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define GOTGINT_HNSSCHG_Pos              (9U)
+#define GOTGINT_HNSSCHG_Msk              (0x1UL << GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define GOTGINT_HNSSCHG                  GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define GOTGINT_HNGDET_Pos               (17U)
+#define GOTGINT_HNGDET_Msk               (0x1UL << GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define GOTGINT_HNGDET                   GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define GOTGINT_ADTOCHG_Pos              (18U)
+#define GOTGINT_ADTOCHG_Msk              (0x1UL << GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define GOTGINT_ADTOCHG                  GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define GOTGINT_DBCDNE_Pos               (19U)
+#define GOTGINT_DBCDNE_Msk               (0x1UL << GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define GOTGINT_DBCDNE                   GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+#define GOTGINT_IDCHNG_Pos               (20U)
+#define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
+#define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */
 
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET_Pos               (2U)                           
-#define USB_OTG_GOTGINT_SEDET_Msk               (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
-#define USB_OTG_GOTGINT_SEDET                   USB_OTG_GOTGINT_SEDET_Msk      /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG_Pos             (8U)                           
-#define USB_OTG_GOTGINT_SRSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
-#define USB_OTG_GOTGINT_SRSSCHG                 USB_OTG_GOTGINT_SRSSCHG_Msk    /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG_Pos             (9U)                           
-#define USB_OTG_GOTGINT_HNSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
-#define USB_OTG_GOTGINT_HNSSCHG                 USB_OTG_GOTGINT_HNSSCHG_Msk    /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET_Pos              (17U)                          
-#define USB_OTG_GOTGINT_HNGDET_Msk              (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
-#define USB_OTG_GOTGINT_HNGDET                  USB_OTG_GOTGINT_HNGDET_Msk     /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG_Pos             (18U)                          
-#define USB_OTG_GOTGINT_ADTOCHG_Msk             (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
-#define USB_OTG_GOTGINT_ADTOCHG                 USB_OTG_GOTGINT_ADTOCHG_Msk    /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE_Pos              (19U)                          
-#define USB_OTG_GOTGINT_DBCDNE_Msk              (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
-#define USB_OTG_GOTGINT_DBCDNE                  USB_OTG_GOTGINT_DBCDNE_Msk     /*!< Debounce done */
+/********************  Bit definition for DCTL register  ********************/
+#define DCTL_RWUSIG_Pos                  (0U)
+#define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define DCTL_RWUSIG                      DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define DCTL_SDIS_Pos                    (1U)
+#define DCTL_SDIS_Msk                    (0x1UL << DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define DCTL_SDIS                        DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define DCTL_GINSTS_Pos                  (2U)
+#define DCTL_GINSTS_Msk                  (0x1UL << DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define DCTL_GINSTS                      DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define DCTL_GONSTS_Pos                  (3U)
+#define DCTL_GONSTS_Msk                  (0x1UL << DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define DCTL_GONSTS                      DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
 
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG_Pos                 (0U)                           
-#define USB_OTG_DCTL_RWUSIG_Msk                 (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
-#define USB_OTG_DCTL_RWUSIG                     USB_OTG_DCTL_RWUSIG_Msk        /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS_Pos                   (1U)                           
-#define USB_OTG_DCTL_SDIS_Msk                   (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCTL_SDIS                       USB_OTG_DCTL_SDIS_Msk          /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS_Pos                 (2U)                           
-#define USB_OTG_DCTL_GINSTS_Msk                 (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
-#define USB_OTG_DCTL_GINSTS                     USB_OTG_DCTL_GINSTS_Msk        /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS_Pos                 (3U)                           
-#define USB_OTG_DCTL_GONSTS_Msk                 (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
-#define USB_OTG_DCTL_GONSTS                     USB_OTG_DCTL_GONSTS_Msk        /*!< Global OUT NAK status */
+#define DCTL_TCTL_Pos                    (4U)
+#define DCTL_TCTL_Msk                    (0x7UL << DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define DCTL_TCTL                        DCTL_TCTL_Msk         /*!< Test control */
+#define DCTL_TCTL_0                      (0x1UL << DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define DCTL_TCTL_1                      (0x2UL << DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define DCTL_TCTL_2                      (0x4UL << DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define DCTL_SGINAK_Pos                  (7U)
+#define DCTL_SGINAK_Msk                  (0x1UL << DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define DCTL_SGINAK                      DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define DCTL_CGINAK_Pos                  (8U)
+#define DCTL_CGINAK_Msk                  (0x1UL << DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define DCTL_CGINAK                      DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define DCTL_SGONAK_Pos                  (9U)
+#define DCTL_SGONAK_Msk                  (0x1UL << DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define DCTL_SGONAK                      DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define DCTL_CGONAK_Pos                  (10U)
+#define DCTL_CGONAK_Msk                  (0x1UL << DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define DCTL_CGONAK                      DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define DCTL_POPRGDNE_Pos                (11U)
+#define DCTL_POPRGDNE_Msk                (0x1UL << DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define DCTL_POPRGDNE                    DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
 
-#define USB_OTG_DCTL_TCTL_Pos                   (4U)                           
-#define USB_OTG_DCTL_TCTL_Msk                   (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
-#define USB_OTG_DCTL_TCTL                       USB_OTG_DCTL_TCTL_Msk          /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                     (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
-#define USB_OTG_DCTL_TCTL_1                     (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
-#define USB_OTG_DCTL_TCTL_2                     (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCTL_SGINAK_Pos                 (7U)                           
-#define USB_OTG_DCTL_SGINAK_Msk                 (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
-#define USB_OTG_DCTL_SGINAK                     USB_OTG_DCTL_SGINAK_Msk        /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK_Pos                 (8U)                           
-#define USB_OTG_DCTL_CGINAK_Msk                 (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
-#define USB_OTG_DCTL_CGINAK                     USB_OTG_DCTL_CGINAK_Msk        /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK_Pos                 (9U)                           
-#define USB_OTG_DCTL_SGONAK_Msk                 (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
-#define USB_OTG_DCTL_SGONAK                     USB_OTG_DCTL_SGONAK_Msk        /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK_Pos                 (10U)                          
-#define USB_OTG_DCTL_CGONAK_Msk                 (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
-#define USB_OTG_DCTL_CGONAK                     USB_OTG_DCTL_CGONAK_Msk        /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE_Pos               (11U)                          
-#define USB_OTG_DCTL_POPRGDNE_Msk               (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
-#define USB_OTG_DCTL_POPRGDNE                   USB_OTG_DCTL_POPRGDNE_Msk      /*!< Power-on programming done */
+/********************  Bit definition for HFIR register  ********************/
+#define HFIR_FRIVL_Pos                   (0U)
+#define HFIR_FRIVL_Msk                   (0xFFFFUL << HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define HFIR_FRIVL                       HFIR_FRIVL_Msk        /*!< Frame interval */
 
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL_Pos                  (0U)                           
-#define USB_OTG_HFIR_FRIVL_Msk                  (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HFIR_FRIVL                      USB_OTG_HFIR_FRIVL_Msk         /*!< Frame interval */
+/********************  Bit definition for HFNUM register  ********************/
+#define HFNUM_FRNUM_Pos                  (0U)
+#define HFNUM_FRNUM_Msk                  (0xFFFFUL << HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define HFNUM_FRNUM                      HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define HFNUM_FTREM_Pos                  (16U)
+#define HFNUM_FTREM_Msk                  (0xFFFFUL << HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define HFNUM_FTREM                      HFNUM_FTREM_Msk       /*!< Frame time remaining */
 
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM_Pos                 (0U)                           
-#define USB_OTG_HFNUM_FRNUM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HFNUM_FRNUM                     USB_OTG_HFNUM_FRNUM_Msk        /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM_Pos                 (16U)                          
-#define USB_OTG_HFNUM_FTREM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_HFNUM_FTREM                     USB_OTG_HFNUM_FTREM_Msk        /*!< Frame time remaining */
+/********************  Bit definition for DSTS register  ********************/
+#define DSTS_SUSPSTS_Pos                 (0U)
+#define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk      /*!< Suspend status   */
 
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS_Pos                (0U)                           
-#define USB_OTG_DSTS_SUSPSTS_Msk                (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
-#define USB_OTG_DSTS_SUSPSTS                    USB_OTG_DSTS_SUSPSTS_Msk       /*!< Suspend status */
+#define DSTS_ENUMSPD_Pos                 (1U)
+#define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define DSTS_ENUMSPD_0                   (0x1UL << DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define DSTS_ENUMSPD_1                   (0x2UL << DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define DSTS_EERR_Pos                    (3U)
+#define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos) /*!< 0x00000008 */
+#define DSTS_EERR                        DSTS_EERR_Msk         /*!< Erratic error     */
+#define DSTS_FNSOF_Pos                   (8U)
+#define DSTS_FNSOF_Msk                   (0x3FFFUL << DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define DSTS_FNSOF                       DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
 
-#define USB_OTG_DSTS_ENUMSPD_Pos                (1U)                           
-#define USB_OTG_DSTS_ENUMSPD_Msk                (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
-#define USB_OTG_DSTS_ENUMSPD                    USB_OTG_DSTS_ENUMSPD_Msk       /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0                  (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DSTS_ENUMSPD_1                  (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
-#define USB_OTG_DSTS_EERR_Pos                   (3U)                           
-#define USB_OTG_DSTS_EERR_Msk                   (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
-#define USB_OTG_DSTS_EERR                       USB_OTG_DSTS_EERR_Msk          /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF_Pos                  (8U)                           
-#define USB_OTG_DSTS_FNSOF_Msk                  (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
-#define USB_OTG_DSTS_FNSOF                      USB_OTG_DSTS_FNSOF_Msk         /*!< Frame number of the received SOF */
+/********************  Bit definition for GAHBCFG register  ********************/
+#define GAHBCFG_GINT_Pos                 (0U)
+#define GAHBCFG_GINT_Msk                 (0x1UL << GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define GAHBCFG_GINT                     GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+#define GAHBCFG_HBSTLEN_Pos              (1U)
+#define GAHBCFG_HBSTLEN_Msk              (0xFUL << GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define GAHBCFG_HBSTLEN                  GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define GAHBCFG_HBSTLEN_0                (0x0UL << GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define GAHBCFG_HBSTLEN_1                (0x1UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define GAHBCFG_HBSTLEN_2                (0x3UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define GAHBCFG_HBSTLEN_3                (0x5UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define GAHBCFG_HBSTLEN_4                (0x7UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define GAHBCFG_DMAEN_Pos                (5U)
+#define GAHBCFG_DMAEN_Msk                (0x1UL << GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define GAHBCFG_DMAEN                    GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define GAHBCFG_TXFELVL_Pos              (7U)
+#define GAHBCFG_TXFELVL_Msk              (0x1UL << GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define GAHBCFG_TXFELVL                  GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define GAHBCFG_PTXFELVL_Pos             (8U)
+#define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
 
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT_Pos                (0U)                           
-#define USB_OTG_GAHBCFG_GINT_Msk                (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
-#define USB_OTG_GAHBCFG_GINT                    USB_OTG_GAHBCFG_GINT_Msk       /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)                           
-#define USB_OTG_GAHBCFG_HBSTLEN_Msk             (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
-#define USB_OTG_GAHBCFG_HBSTLEN                 USB_OTG_GAHBCFG_HBSTLEN_Msk    /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
-#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
-#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
-#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
-#define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)                           
-#define USB_OTG_GAHBCFG_DMAEN_Msk               (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
-#define USB_OTG_GAHBCFG_DMAEN                   USB_OTG_GAHBCFG_DMAEN_Msk      /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL_Pos             (7U)                           
-#define USB_OTG_GAHBCFG_TXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
-#define USB_OTG_GAHBCFG_TXFELVL                 USB_OTG_GAHBCFG_TXFELVL_Msk    /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL_Pos            (8U)                           
-#define USB_OTG_GAHBCFG_PTXFELVL_Msk            (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
-#define USB_OTG_GAHBCFG_PTXFELVL                USB_OTG_GAHBCFG_PTXFELVL_Msk   /*!< Periodic TxFIFO empty level */
+/********************  Bit definition for GUSBCFG register  ********************/
+#define GUSBCFG_TOCAL_Pos                (0U)
+#define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define GUSBCFG_TOCAL_0                  (0x1UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define GUSBCFG_TOCAL_1                  (0x2UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define GUSBCFG_TOCAL_2                  (0x4UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define GUSBCFG_PHYIF_Pos                (3U)
+#define GUSBCFG_PHYIF_Msk                (0x1UL << GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */
+#define GUSBCFG_PHYIF                    GUSBCFG_PHYIF_Msk     /*!< PHY Interface (PHYIf) */
+#define GUSBCFG_ULPI_UTMI_SEL_Pos        (4U)
+#define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */
+#define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
+#define GUSBCFG_PHYSEL_Pos               (6U)
+#define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define GUSBCFG_SRPCAP_Pos               (8U)
+#define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define GUSBCFG_HNPCAP_Pos               (9U)
+#define GUSBCFG_HNPCAP_Msk               (0x1UL << GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define GUSBCFG_HNPCAP                   GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+#define GUSBCFG_TRDT_Pos                 (10U)
+#define GUSBCFG_TRDT_Msk                 (0xFUL << GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define GUSBCFG_TRDT                     GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define GUSBCFG_TRDT_0                   (0x1UL << GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define GUSBCFG_TRDT_1                   (0x2UL << GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define GUSBCFG_TRDT_2                   (0x4UL << GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define GUSBCFG_TRDT_3                   (0x8UL << GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define GUSBCFG_PHYLPCS_Pos              (15U)
+#define GUSBCFG_PHYLPCS_Msk              (0x1UL << GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define GUSBCFG_PHYLPCS                  GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define GUSBCFG_ULPIFSLS_Pos             (17U)
+#define GUSBCFG_ULPIFSLS_Msk             (0x1UL << GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define GUSBCFG_ULPIFSLS                 GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define GUSBCFG_ULPIAR_Pos               (18U)
+#define GUSBCFG_ULPIAR_Msk               (0x1UL << GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define GUSBCFG_ULPIAR                   GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define GUSBCFG_ULPICSM_Pos              (19U)
+#define GUSBCFG_ULPICSM_Msk              (0x1UL << GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define GUSBCFG_ULPICSM                  GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define GUSBCFG_ULPIEVBUSD               GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define GUSBCFG_ULPIEVBUSI               GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define GUSBCFG_TSDPS_Pos                (22U)
+#define GUSBCFG_TSDPS_Msk                (0x1UL << GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define GUSBCFG_TSDPS                    GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define GUSBCFG_PCCI_Pos                 (23U)
+#define GUSBCFG_PCCI_Msk                 (0x1UL << GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define GUSBCFG_PCCI                     GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define GUSBCFG_PTCI_Pos                 (24U)
+#define GUSBCFG_PTCI_Msk                 (0x1UL << GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define GUSBCFG_PTCI                     GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define GUSBCFG_ULPIIPD_Pos              (25U)
+#define GUSBCFG_ULPIIPD_Msk              (0x1UL << GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define GUSBCFG_ULPIIPD                  GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define GUSBCFG_FHMOD_Pos                (29U)
+#define GUSBCFG_FHMOD_Msk                (0x1UL << GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define GUSBCFG_FHMOD                    GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define GUSBCFG_FDMOD_Pos                (30U)
+#define GUSBCFG_FDMOD_Msk                (0x1UL << GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define GUSBCFG_FDMOD                    GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define GUSBCFG_CTXPKT_Pos               (31U)
+#define GUSBCFG_CTXPKT_Msk               (0x1UL << GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define GUSBCFG_CTXPKT                   GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
 
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+/********************  Bit definition for GRSTCTL register  ********************/
+#define GRSTCTL_CSRST_Pos                (0U)
+#define GRSTCTL_CSRST_Msk                (0x1UL << GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define GRSTCTL_CSRST                    GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define GRSTCTL_HSRST_Pos                (1U)
+#define GRSTCTL_HSRST_Msk                (0x1UL << GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define GRSTCTL_HSRST                    GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define GRSTCTL_FCRST_Pos                (2U)
+#define GRSTCTL_FCRST_Msk                (0x1UL << GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define GRSTCTL_FCRST                    GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define GRSTCTL_RXFFLSH_Pos              (4U)
+#define GRSTCTL_RXFFLSH_Msk              (0x1UL << GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define GRSTCTL_RXFFLSH                  GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define GRSTCTL_TXFFLSH_Pos              (5U)
+#define GRSTCTL_TXFFLSH_Msk              (0x1UL << GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define GRSTCTL_TXFFLSH                  GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+#define GRSTCTL_TXFNUM_Pos               (6U)
+#define GRSTCTL_TXFNUM_Msk               (0x1FUL << GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define GRSTCTL_TXFNUM                   GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define GRSTCTL_TXFNUM_0                 (0x01UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define GRSTCTL_TXFNUM_1                 (0x02UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define GRSTCTL_DMAREQ_Pos               (30U)
+#define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define GRSTCTL_AHBIDL_Pos               (31U)
+#define GRSTCTL_AHBIDL_Msk               (0x1UL << GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define GRSTCTL_AHBIDL                   GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
 
-#define USB_OTG_GUSBCFG_TOCAL_Pos               (0U)                           
-#define USB_OTG_GUSBCFG_TOCAL_Msk               (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
-#define USB_OTG_GUSBCFG_TOCAL                   USB_OTG_GUSBCFG_TOCAL_Msk      /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
-#define USB_OTG_GUSBCFG_PHYSEL_Pos              (6U)                           
-#define USB_OTG_GUSBCFG_PHYSEL_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
-#define USB_OTG_GUSBCFG_PHYSEL                  USB_OTG_GUSBCFG_PHYSEL_Msk     /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP_Pos              (8U)                           
-#define USB_OTG_GUSBCFG_SRPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
-#define USB_OTG_GUSBCFG_SRPCAP                  USB_OTG_GUSBCFG_SRPCAP_Msk     /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP_Pos              (9U)                           
-#define USB_OTG_GUSBCFG_HNPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
-#define USB_OTG_GUSBCFG_HNPCAP                  USB_OTG_GUSBCFG_HNPCAP_Msk     /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT_Pos                (10U)                          
-#define USB_OTG_GUSBCFG_TRDT_Msk                (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
-#define USB_OTG_GUSBCFG_TRDT                    USB_OTG_GUSBCFG_TRDT_Msk       /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
-#define USB_OTG_GUSBCFG_TRDT_1                  (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
-#define USB_OTG_GUSBCFG_TRDT_2                  (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
-#define USB_OTG_GUSBCFG_TRDT_3                  (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
-#define USB_OTG_GUSBCFG_PHYLPCS_Pos             (15U)                          
-#define USB_OTG_GUSBCFG_PHYLPCS_Msk             (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 USB_OTG_GUSBCFG_PHYLPCS_Msk    /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS_Pos            (17U)                          
-#define USB_OTG_GUSBCFG_ULPIFSLS_Msk            (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
-#define USB_OTG_GUSBCFG_ULPIFSLS                USB_OTG_GUSBCFG_ULPIFSLS_Msk   /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR_Pos              (18U)                          
-#define USB_OTG_GUSBCFG_ULPIAR_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
-#define USB_OTG_GUSBCFG_ULPIAR                  USB_OTG_GUSBCFG_ULPIAR_Msk     /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM_Pos             (19U)                          
-#define USB_OTG_GUSBCFG_ULPICSM_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
-#define USB_OTG_GUSBCFG_ULPICSM                 USB_OTG_GUSBCFG_ULPICSM_Msk    /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos          (20U)                          
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos          (21U)                          
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS_Pos               (22U)                          
-#define USB_OTG_GUSBCFG_TSDPS_Msk               (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
-#define USB_OTG_GUSBCFG_TSDPS                   USB_OTG_GUSBCFG_TSDPS_Msk      /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI_Pos                (23U)                          
-#define USB_OTG_GUSBCFG_PCCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
-#define USB_OTG_GUSBCFG_PCCI                    USB_OTG_GUSBCFG_PCCI_Msk       /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI_Pos                (24U)                          
-#define USB_OTG_GUSBCFG_PTCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
-#define USB_OTG_GUSBCFG_PTCI                    USB_OTG_GUSBCFG_PTCI_Msk       /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD_Pos             (25U)                          
-#define USB_OTG_GUSBCFG_ULPIIPD_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
-#define USB_OTG_GUSBCFG_ULPIIPD                 USB_OTG_GUSBCFG_ULPIIPD_Msk    /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD_Pos               (29U)                          
-#define USB_OTG_GUSBCFG_FHMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
-#define USB_OTG_GUSBCFG_FHMOD                   USB_OTG_GUSBCFG_FHMOD_Msk      /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD_Pos               (30U)                          
-#define USB_OTG_GUSBCFG_FDMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
-#define USB_OTG_GUSBCFG_FDMOD                   USB_OTG_GUSBCFG_FDMOD_Msk      /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT_Pos              (31U)                          
-#define USB_OTG_GUSBCFG_CTXPKT_Msk              (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                  USB_OTG_GUSBCFG_CTXPKT_Msk     /*!< Corrupt Tx packet */
+/********************  Bit definition for DIEPMSK register  ********************/
+#define DIEPMSK_XFRCM_Pos                (0U)
+#define DIEPMSK_XFRCM_Msk                (0x1UL << DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define DIEPMSK_XFRCM                    DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define DIEPMSK_EPDM_Pos                 (1U)
+#define DIEPMSK_EPDM_Msk                 (0x1UL << DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define DIEPMSK_EPDM                     DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define DIEPMSK_TOM_Pos                  (3U)
+#define DIEPMSK_TOM_Msk                  (0x1UL << DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define DIEPMSK_TOM                      DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define DIEPMSK_ITTXFEMSK_Msk            (0x1UL << DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define DIEPMSK_ITTXFEMSK                DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define DIEPMSK_INEPNMM_Pos              (5U)
+#define DIEPMSK_INEPNMM_Msk              (0x1UL << DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define DIEPMSK_INEPNMM                  DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define DIEPMSK_INEPNEM_Pos              (6U)
+#define DIEPMSK_INEPNEM_Msk              (0x1UL << DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define DIEPMSK_INEPNEM                  DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define DIEPMSK_TXFURM_Pos               (8U)
+#define DIEPMSK_TXFURM_Msk               (0x1UL << DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define DIEPMSK_TXFURM                   DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define DIEPMSK_BIM_Pos                  (9U)
+#define DIEPMSK_BIM_Msk                  (0x1UL << DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define DIEPMSK_BIM                      DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
 
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST_Pos               (0U)                           
-#define USB_OTG_GRSTCTL_CSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
-#define USB_OTG_GRSTCTL_CSRST                   USB_OTG_GRSTCTL_CSRST_Msk      /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST_Pos               (1U)                           
-#define USB_OTG_GRSTCTL_HSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
-#define USB_OTG_GRSTCTL_HSRST                   USB_OTG_GRSTCTL_HSRST_Msk      /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST_Pos               (2U)                           
-#define USB_OTG_GRSTCTL_FCRST_Msk               (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
-#define USB_OTG_GRSTCTL_FCRST                   USB_OTG_GRSTCTL_FCRST_Msk      /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH_Pos             (4U)                           
-#define USB_OTG_GRSTCTL_RXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
-#define USB_OTG_GRSTCTL_RXFFLSH                 USB_OTG_GRSTCTL_RXFFLSH_Msk    /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH_Pos             (5U)                           
-#define USB_OTG_GRSTCTL_TXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
-#define USB_OTG_GRSTCTL_TXFFLSH                 USB_OTG_GRSTCTL_TXFFLSH_Msk    /*!< TxFIFO flush */
+/********************  Bit definition for HPTXSTS register  ********************/
+#define HPTXSTS_PTXFSAVL_Pos             (0U)
+#define HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define HPTXSTS_PTXFSAVL                 HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+#define HPTXSTS_PTXQSAV_Pos              (16U)
+#define HPTXSTS_PTXQSAV_Msk              (0xFFUL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define HPTXSTS_PTXQSAV                  HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define HPTXSTS_PTXQSAV_0                (0x01UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define HPTXSTS_PTXQSAV_1                (0x02UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define HPTXSTS_PTXQSAV_2                (0x04UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define HPTXSTS_PTXQSAV_3                (0x08UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define HPTXSTS_PTXQSAV_4                (0x10UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define HPTXSTS_PTXQSAV_5                (0x20UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define HPTXSTS_PTXQSAV_6                (0x40UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define HPTXSTS_PTXQSAV_7                (0x80UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
 
+#define HPTXSTS_PTXQTOP_Pos              (24U)
+#define HPTXSTS_PTXQTOP_Msk              (0xFFUL << HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define HPTXSTS_PTXQTOP                  HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define HPTXSTS_PTXQTOP_0                (0x01UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define HPTXSTS_PTXQTOP_1                (0x02UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define HPTXSTS_PTXQTOP_2                (0x04UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define HPTXSTS_PTXQTOP_3                (0x08UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define HPTXSTS_PTXQTOP_4                (0x10UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define HPTXSTS_PTXQTOP_5                (0x20UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define HPTXSTS_PTXQTOP_6                (0x40UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define HPTXSTS_PTXQTOP_7                (0x80UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
 
-#define USB_OTG_GRSTCTL_TXFNUM_Pos              (6U)                           
-#define USB_OTG_GRSTCTL_TXFNUM_Msk              (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
-#define USB_OTG_GRSTCTL_TXFNUM                  USB_OTG_GRSTCTL_TXFNUM_Msk     /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GRSTCTL_DMAREQ_Pos              (30U)                          
-#define USB_OTG_GRSTCTL_DMAREQ_Msk              (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
-#define USB_OTG_GRSTCTL_DMAREQ                  USB_OTG_GRSTCTL_DMAREQ_Msk     /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL_Pos              (31U)                          
-#define USB_OTG_GRSTCTL_AHBIDL_Msk              (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
-#define USB_OTG_GRSTCTL_AHBIDL                  USB_OTG_GRSTCTL_AHBIDL_Msk     /*!< AHB master idle */
+/********************  Bit definition for HAINT register  ********************/
+#define HAINT_HAINT_Pos                  (0U)
+#define HAINT_HAINT_Msk                  (0xFFFFUL << HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define HAINT_HAINT                      HAINT_HAINT_Msk       /*!< Channel interrupts */
 
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM_Pos               (0U)                           
-#define USB_OTG_DIEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPMSK_XFRCM                   USB_OTG_DIEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM_Pos                (1U)                           
-#define USB_OTG_DIEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPMSK_EPDM                    USB_OTG_DIEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM_Pos                 (3U)                           
-#define USB_OTG_DIEPMSK_TOM_Msk                 (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPMSK_TOM                     USB_OTG_DIEPMSK_TOM_Msk        /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos           (4U)                           
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk           (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               USB_OTG_DIEPMSK_ITTXFEMSK_Msk  /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM_Pos             (5U)                           
-#define USB_OTG_DIEPMSK_INEPNMM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DIEPMSK_INEPNMM                 USB_OTG_DIEPMSK_INEPNMM_Msk    /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM_Pos             (6U)                           
-#define USB_OTG_DIEPMSK_INEPNEM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPMSK_INEPNEM                 USB_OTG_DIEPMSK_INEPNEM_Msk    /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM_Pos              (8U)                           
-#define USB_OTG_DIEPMSK_TXFURM_Msk              (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPMSK_TXFURM                  USB_OTG_DIEPMSK_TXFURM_Msk     /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM_Pos                 (9U)                           
-#define USB_OTG_DIEPMSK_BIM_Msk                 (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPMSK_BIM                     USB_OTG_DIEPMSK_BIM_Msk        /*!< BNA interrupt mask */
+/********************  Bit definition for DOEPMSK register  ********************/
+#define DOEPMSK_XFRCM_Pos                (0U)
+#define DOEPMSK_XFRCM_Msk                (0x1UL << DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define DOEPMSK_XFRCM                    DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define DOEPMSK_EPDM_Pos                 (1U)
+#define DOEPMSK_EPDM_Msk                 (0x1UL << DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define DOEPMSK_EPDM                     DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define DOEPMSK_AHBERRM_Pos              (2U)
+#define DOEPMSK_AHBERRM_Msk              (0x1UL << DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define DOEPMSK_AHBERRM                  DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask    */
+#define DOEPMSK_STUPM_Pos                (3U)
+#define DOEPMSK_STUPM_Msk                (0x1UL << DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define DOEPMSK_STUPM                    DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define DOEPMSK_OTEPDM_Pos               (4U)
+#define DOEPMSK_OTEPDM_Msk               (0x1UL << DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define DOEPMSK_OTEPDM                   DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define DOEPMSK_OTEPSPRM_Pos             (5U)
+#define DOEPMSK_OTEPSPRM_Msk             (0x1UL << DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define DOEPMSK_OTEPSPRM                 DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define DOEPMSK_B2BSTUP_Pos              (6U)
+#define DOEPMSK_B2BSTUP_Msk              (0x1UL << DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define DOEPMSK_B2BSTUP                  DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define DOEPMSK_OPEM_Pos                 (8U)
+#define DOEPMSK_OPEM_Msk                 (0x1UL << DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define DOEPMSK_OPEM                     DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define DOEPMSK_BOIM_Pos                 (9U)
+#define DOEPMSK_BOIM_Msk                 (0x1UL << DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define DOEPMSK_BOIM                     DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+#define DOEPMSK_BERRM_Pos                (12U)
+#define DOEPMSK_BERRM_Msk                (0x1UL << DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define DOEPMSK_BERRM                    DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
+#define DOEPMSK_NAKM_Pos                 (13U)
+#define DOEPMSK_NAKM_Msk                 (0x1UL << DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define DOEPMSK_NAKM                     DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
+#define DOEPMSK_NYETM_Pos                (14U)
+#define DOEPMSK_NYETM_Msk                (0x1UL << DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define DOEPMSK_NYETM                    DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                           */
 
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL_Pos            (0U)                           
-#define USB_OTG_HPTXSTS_PTXFSAVL_Msk            (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HPTXSTS_PTXFSAVL                USB_OTG_HPTXSTS_PTXFSAVL_Msk   /*!< Periodic transmit data FIFO space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_Pos             (16U)                          
-#define USB_OTG_HPTXSTS_PTXQSAV_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
-#define USB_OTG_HPTXSTS_PTXQSAV                 USB_OTG_HPTXSTS_PTXQSAV_Msk    /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+/********************  Bit definition for GINTSTS register  ********************/
+#define GINTSTS_CMOD_Pos                 (0U)
+#define GINTSTS_CMOD_Msk                 (0x1UL << GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define GINTSTS_CMOD                     GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define GINTSTS_MMIS_Pos                 (1U)
+#define GINTSTS_MMIS_Msk                 (0x1UL << GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define GINTSTS_MMIS                     GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define GINTSTS_OTGINT_Pos               (2U)
+#define GINTSTS_OTGINT_Msk               (0x1UL << GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define GINTSTS_OTGINT                   GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define GINTSTS_SOF_Pos                  (3U)
+#define GINTSTS_SOF_Msk                  (0x1UL << GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define GINTSTS_SOF                      GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define GINTSTS_RXFLVL_Pos               (4U)
+#define GINTSTS_RXFLVL_Msk               (0x1UL << GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define GINTSTS_RXFLVL                   GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define GINTSTS_NPTXFE_Pos               (5U)
+#define GINTSTS_NPTXFE_Msk               (0x1UL << GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define GINTSTS_NPTXFE                   GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define GINTSTS_GINAKEFF_Pos             (6U)
+#define GINTSTS_GINAKEFF_Msk             (0x1UL << GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define GINTSTS_GINAKEFF                 GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define GINTSTS_BOUTNAKEFF_Msk           (0x1UL << GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define GINTSTS_BOUTNAKEFF               GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define GINTSTS_ESUSP_Pos                (10U)
+#define GINTSTS_ESUSP_Msk                (0x1UL << GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define GINTSTS_ESUSP                    GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define GINTSTS_USBSUSP_Pos              (11U)
+#define GINTSTS_USBSUSP_Msk              (0x1UL << GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define GINTSTS_USBSUSP                  GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define GINTSTS_USBRST_Pos               (12U)
+#define GINTSTS_USBRST_Msk               (0x1UL << GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define GINTSTS_USBRST                   GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define GINTSTS_ENUMDNE_Pos              (13U)
+#define GINTSTS_ENUMDNE_Msk              (0x1UL << GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define GINTSTS_ENUMDNE                  GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define GINTSTS_ISOODRP_Pos              (14U)
+#define GINTSTS_ISOODRP_Msk              (0x1UL << GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define GINTSTS_ISOODRP                  GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define GINTSTS_EOPF_Pos                 (15U)
+#define GINTSTS_EOPF_Msk                 (0x1UL << GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define GINTSTS_EOPF                     GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define GINTSTS_IEPINT_Pos               (18U)
+#define GINTSTS_IEPINT_Msk               (0x1UL << GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define GINTSTS_IEPINT                   GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define GINTSTS_OEPINT_Pos               (19U)
+#define GINTSTS_OEPINT_Msk               (0x1UL << GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define GINTSTS_OEPINT                   GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define GINTSTS_IISOIXFR_Pos             (20U)
+#define GINTSTS_IISOIXFR_Msk             (0x1UL << GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define GINTSTS_IISOIXFR                 GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define GINTSTS_PXFR_INCOMPISOOUT        GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define GINTSTS_DATAFSUSP_Pos            (22U)
+#define GINTSTS_DATAFSUSP_Msk            (0x1UL << GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define GINTSTS_DATAFSUSP                GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define GINTSTS_RSTDET_Pos               (23U)
+#define GINTSTS_RSTDET_Msk               (0x1UL << GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define GINTSTS_RSTDET                   GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define GINTSTS_HPRTINT_Pos              (24U)
+#define GINTSTS_HPRTINT_Msk              (0x1UL << GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define GINTSTS_HPRTINT                  GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define GINTSTS_HCINT_Pos                (25U)
+#define GINTSTS_HCINT_Msk                (0x1UL << GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define GINTSTS_HCINT                    GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define GINTSTS_PTXFE_Pos                (26U)
+#define GINTSTS_PTXFE_Msk                (0x1UL << GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define GINTSTS_PTXFE                    GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define GINTSTS_LPMINT_Pos               (27U)
+#define GINTSTS_LPMINT_Msk               (0x1UL << GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define GINTSTS_LPMINT                   GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define GINTSTS_CIDSCHG_Pos              (28U)
+#define GINTSTS_CIDSCHG_Msk              (0x1UL << GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define GINTSTS_CIDSCHG                  GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define GINTSTS_DISCINT_Pos              (29U)
+#define GINTSTS_DISCINT_Msk              (0x1UL << GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define GINTSTS_DISCINT                  GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define GINTSTS_SRQINT_Pos               (30U)
+#define GINTSTS_SRQINT_Msk               (0x1UL << GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define GINTSTS_SRQINT                   GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define GINTSTS_WKUINT_Pos               (31U)
+#define GINTSTS_WKUINT_Msk               (0x1UL << GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define GINTSTS_WKUINT                   GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
 
-#define USB_OTG_HPTXSTS_PTXQTOP_Pos             (24U)                          
-#define USB_OTG_HPTXSTS_PTXQTOP_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP                 USB_OTG_HPTXSTS_PTXQTOP_Msk    /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+/********************  Bit definition for GINTMSK register  ********************/
+#define GINTMSK_MMISM_Pos                (1U)
+#define GINTMSK_MMISM_Msk                (0x1UL << GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define GINTMSK_MMISM                    GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define GINTMSK_OTGINT_Pos               (2U)
+#define GINTMSK_OTGINT_Msk               (0x1UL << GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define GINTMSK_OTGINT                   GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define GINTMSK_SOFM_Pos                 (3U)
+#define GINTMSK_SOFM_Msk                 (0x1UL << GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define GINTMSK_SOFM                     GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define GINTMSK_RXFLVLM_Pos              (4U)
+#define GINTMSK_RXFLVLM_Msk              (0x1UL << GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define GINTMSK_RXFLVLM                  GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define GINTMSK_NPTXFEM_Pos              (5U)
+#define GINTMSK_NPTXFEM_Msk              (0x1UL << GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define GINTMSK_NPTXFEM                  GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define GINTMSK_GINAKEFFM_Pos            (6U)
+#define GINTMSK_GINAKEFFM_Msk            (0x1UL << GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define GINTMSK_GINAKEFFM                GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define GINTMSK_GONAKEFFM_Pos            (7U)
+#define GINTMSK_GONAKEFFM_Msk            (0x1UL << GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define GINTMSK_GONAKEFFM                GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define GINTMSK_ESUSPM_Pos               (10U)
+#define GINTMSK_ESUSPM_Msk               (0x1UL << GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define GINTMSK_ESUSPM                   GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define GINTMSK_USBSUSPM_Pos             (11U)
+#define GINTMSK_USBSUSPM_Msk             (0x1UL << GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define GINTMSK_USBSUSPM                 GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define GINTMSK_USBRST_Pos               (12U)
+#define GINTMSK_USBRST_Msk               (0x1UL << GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define GINTMSK_USBRST                   GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define GINTMSK_ENUMDNEM_Pos             (13U)
+#define GINTMSK_ENUMDNEM_Msk             (0x1UL << GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define GINTMSK_ENUMDNEM                 GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define GINTMSK_ISOODRPM_Pos             (14U)
+#define GINTMSK_ISOODRPM_Msk             (0x1UL << GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define GINTMSK_ISOODRPM                 GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define GINTMSK_EOPFM_Pos                (15U)
+#define GINTMSK_EOPFM_Msk                (0x1UL << GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define GINTMSK_EOPFM                    GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define GINTMSK_EPMISM_Pos               (17U)
+#define GINTMSK_EPMISM_Msk               (0x1UL << GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define GINTMSK_EPMISM                   GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define GINTMSK_IEPINT_Pos               (18U)
+#define GINTMSK_IEPINT_Msk               (0x1UL << GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define GINTMSK_IEPINT                   GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define GINTMSK_OEPINT_Pos               (19U)
+#define GINTMSK_OEPINT_Msk               (0x1UL << GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define GINTMSK_OEPINT                   GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define GINTMSK_IISOIXFRM_Pos            (20U)
+#define GINTMSK_IISOIXFRM_Msk            (0x1UL << GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define GINTMSK_IISOIXFRM                GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define GINTMSK_PXFRM_IISOOXFRM          GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define GINTMSK_FSUSPM_Pos               (22U)
+#define GINTMSK_FSUSPM_Msk               (0x1UL << GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define GINTMSK_FSUSPM                   GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define GINTMSK_RSTDEM_Pos               (23U)
+#define GINTMSK_RSTDEM_Msk               (0x1UL << GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define GINTMSK_RSTDEM                   GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                       */
+#define GINTMSK_PRTIM_Pos                (24U)
+#define GINTMSK_PRTIM_Msk                (0x1UL << GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define GINTMSK_PRTIM                    GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define GINTMSK_HCIM_Pos                 (25U)
+#define GINTMSK_HCIM_Msk                 (0x1UL << GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define GINTMSK_HCIM                     GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define GINTMSK_PTXFEM_Pos               (26U)
+#define GINTMSK_PTXFEM_Msk               (0x1UL << GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define GINTMSK_PTXFEM                   GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define GINTMSK_LPMINTM_Pos              (27U)
+#define GINTMSK_LPMINTM_Msk              (0x1UL << GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define GINTMSK_LPMINTM                  GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define GINTMSK_CIDSCHGM_Pos             (28U)
+#define GINTMSK_CIDSCHGM_Msk             (0x1UL << GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define GINTMSK_CIDSCHGM                 GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define GINTMSK_DISCINT_Pos              (29U)
+#define GINTMSK_DISCINT_Msk              (0x1UL << GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define GINTMSK_DISCINT                  GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define GINTMSK_SRQIM_Pos                (30U)
+#define GINTMSK_SRQIM_Msk                (0x1UL << GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define GINTMSK_SRQIM                    GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define GINTMSK_WUIM_Pos                 (31U)
+#define GINTMSK_WUIM_Msk                 (0x1UL << GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define GINTMSK_WUIM                     GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
 
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT_Pos                 (0U)                           
-#define USB_OTG_HAINT_HAINT_Msk                 (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HAINT_HAINT                     USB_OTG_HAINT_HAINT_Msk        /*!< Channel interrupts */
+/********************  Bit definition for DAINT register  ********************/
+#define DAINT_IEPINT_Pos                 (0U)
+#define DAINT_IEPINT_Msk                 (0xFFFFUL << DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define DAINT_IEPINT                     DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define DAINT_OEPINT_Pos                 (16U)
+#define DAINT_OEPINT_Msk                 (0xFFFFUL << DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define DAINT_OEPINT                     DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
 
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM_Pos               (0U)                           
-#define USB_OTG_DOEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPMSK_XFRCM                   USB_OTG_DOEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM_Pos                (1U)                           
-#define USB_OTG_DOEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPMSK_EPDM                    USB_OTG_DOEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
-#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
-#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
-#define USB_OTG_DOEPMSK_STUPM_Pos               (3U)                           
-#define USB_OTG_DOEPMSK_STUPM_Msk               (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPMSK_STUPM                   USB_OTG_DOEPMSK_STUPM_Msk      /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM_Pos              (4U)                           
-#define USB_OTG_DOEPMSK_OTEPDM_Msk              (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPMSK_OTEPDM                  USB_OTG_DOEPMSK_OTEPDM_Msk     /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          
-#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP_Pos             (6U)                           
-#define USB_OTG_DOEPMSK_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPMSK_B2BSTUP                 USB_OTG_DOEPMSK_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM_Pos                (8U)                           
-#define USB_OTG_DOEPMSK_OPEM_Msk                (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPMSK_OPEM                    USB_OTG_DOEPMSK_OPEM_Msk       /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM_Pos                (9U)                           
-#define USB_OTG_DOEPMSK_BOIM_Msk                (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DOEPMSK_BOIM                    USB_OTG_DOEPMSK_BOIM_Msk       /*!< BNA interrupt mask */
-#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
-#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
-#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
-#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
-#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
-#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
-#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD_Pos                (0U)                           
-#define USB_OTG_GINTSTS_CMOD_Msk                (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
-#define USB_OTG_GINTSTS_CMOD                    USB_OTG_GINTSTS_CMOD_Msk       /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS_Pos                (1U)                           
-#define USB_OTG_GINTSTS_MMIS_Msk                (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
-#define USB_OTG_GINTSTS_MMIS                    USB_OTG_GINTSTS_MMIS_Msk       /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT_Pos              (2U)                           
-#define USB_OTG_GINTSTS_OTGINT_Msk              (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
-#define USB_OTG_GINTSTS_OTGINT                  USB_OTG_GINTSTS_OTGINT_Msk     /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF_Pos                 (3U)                           
-#define USB_OTG_GINTSTS_SOF_Msk                 (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
-#define USB_OTG_GINTSTS_SOF                     USB_OTG_GINTSTS_SOF_Msk        /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL_Pos              (4U)                           
-#define USB_OTG_GINTSTS_RXFLVL_Msk              (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
-#define USB_OTG_GINTSTS_RXFLVL                  USB_OTG_GINTSTS_RXFLVL_Msk     /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE_Pos              (5U)                           
-#define USB_OTG_GINTSTS_NPTXFE_Msk              (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
-#define USB_OTG_GINTSTS_NPTXFE                  USB_OTG_GINTSTS_NPTXFE_Msk     /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF_Pos            (6U)                           
-#define USB_OTG_GINTSTS_GINAKEFF_Msk            (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
-#define USB_OTG_GINTSTS_GINAKEFF                USB_OTG_GINTSTS_GINAKEFF_Msk   /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos          (7U)                           
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk          (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP_Pos               (10U)                          
-#define USB_OTG_GINTSTS_ESUSP_Msk               (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
-#define USB_OTG_GINTSTS_ESUSP                   USB_OTG_GINTSTS_ESUSP_Msk      /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP_Pos             (11U)                          
-#define USB_OTG_GINTSTS_USBSUSP_Msk             (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
-#define USB_OTG_GINTSTS_USBSUSP                 USB_OTG_GINTSTS_USBSUSP_Msk    /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST_Pos              (12U)                          
-#define USB_OTG_GINTSTS_USBRST_Msk              (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
-#define USB_OTG_GINTSTS_USBRST                  USB_OTG_GINTSTS_USBRST_Msk     /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE_Pos             (13U)                          
-#define USB_OTG_GINTSTS_ENUMDNE_Msk             (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
-#define USB_OTG_GINTSTS_ENUMDNE                 USB_OTG_GINTSTS_ENUMDNE_Msk    /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP_Pos             (14U)                          
-#define USB_OTG_GINTSTS_ISOODRP_Msk             (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
-#define USB_OTG_GINTSTS_ISOODRP                 USB_OTG_GINTSTS_ISOODRP_Msk    /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF_Pos                (15U)                          
-#define USB_OTG_GINTSTS_EOPF_Msk                (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
-#define USB_OTG_GINTSTS_EOPF                    USB_OTG_GINTSTS_EOPF_Msk       /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT_Pos              (18U)                          
-#define USB_OTG_GINTSTS_IEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
-#define USB_OTG_GINTSTS_IEPINT                  USB_OTG_GINTSTS_IEPINT_Msk     /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT_Pos              (19U)                          
-#define USB_OTG_GINTSTS_OEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
-#define USB_OTG_GINTSTS_OEPINT                  USB_OTG_GINTSTS_OEPINT_Msk     /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR_Pos            (20U)                          
-#define USB_OTG_GINTSTS_IISOIXFR_Msk            (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
-#define USB_OTG_GINTSTS_IISOIXFR                USB_OTG_GINTSTS_IISOIXFR_Msk   /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)                          
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP_Pos           (22U)                          
-#define USB_OTG_GINTSTS_DATAFSUSP_Msk           (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
-#define USB_OTG_GINTSTS_DATAFSUSP               USB_OTG_GINTSTS_DATAFSUSP_Msk  /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT_Pos             (24U)                          
-#define USB_OTG_GINTSTS_HPRTINT_Msk             (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
-#define USB_OTG_GINTSTS_HPRTINT                 USB_OTG_GINTSTS_HPRTINT_Msk    /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT_Pos               (25U)                          
-#define USB_OTG_GINTSTS_HCINT_Msk               (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
-#define USB_OTG_GINTSTS_HCINT                   USB_OTG_GINTSTS_HCINT_Msk      /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE_Pos               (26U)                          
-#define USB_OTG_GINTSTS_PTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
-#define USB_OTG_GINTSTS_PTXFE                   USB_OTG_GINTSTS_PTXFE_Msk      /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG_Pos             (28U)                          
-#define USB_OTG_GINTSTS_CIDSCHG_Msk             (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
-#define USB_OTG_GINTSTS_CIDSCHG                 USB_OTG_GINTSTS_CIDSCHG_Msk    /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT_Pos             (29U)                          
-#define USB_OTG_GINTSTS_DISCINT_Msk             (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
-#define USB_OTG_GINTSTS_DISCINT                 USB_OTG_GINTSTS_DISCINT_Msk    /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT_Pos              (30U)                          
-#define USB_OTG_GINTSTS_SRQINT_Msk              (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
-#define USB_OTG_GINTSTS_SRQINT                  USB_OTG_GINTSTS_SRQINT_Msk     /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT_Pos              (31U)                          
-#define USB_OTG_GINTSTS_WKUINT_Msk              (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GINTSTS_WKUINT                  USB_OTG_GINTSTS_WKUINT_Msk     /*!< Resume/remote wakeup detected interrupt */
+/********************  Bit definition for HAINTMSK register  ********************/
+#define HAINTMSK_HAINTM_Pos              (0U)
+#define HAINTMSK_HAINTM_Msk              (0xFFFFUL << HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define HAINTMSK_HAINTM                  HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
 
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM_Pos               (1U)                           
-#define USB_OTG_GINTMSK_MMISM_Msk               (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
-#define USB_OTG_GINTMSK_MMISM                   USB_OTG_GINTMSK_MMISM_Msk      /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT_Pos              (2U)                           
-#define USB_OTG_GINTMSK_OTGINT_Msk              (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
-#define USB_OTG_GINTMSK_OTGINT                  USB_OTG_GINTMSK_OTGINT_Msk     /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM_Pos                (3U)                           
-#define USB_OTG_GINTMSK_SOFM_Msk                (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
-#define USB_OTG_GINTMSK_SOFM                    USB_OTG_GINTMSK_SOFM_Msk       /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM_Pos             (4U)                           
-#define USB_OTG_GINTMSK_RXFLVLM_Msk             (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
-#define USB_OTG_GINTMSK_RXFLVLM                 USB_OTG_GINTMSK_RXFLVLM_Msk    /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM_Pos             (5U)                           
-#define USB_OTG_GINTMSK_NPTXFEM_Msk             (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
-#define USB_OTG_GINTMSK_NPTXFEM                 USB_OTG_GINTMSK_NPTXFEM_Msk    /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM_Pos           (6U)                           
-#define USB_OTG_GINTMSK_GINAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
-#define USB_OTG_GINTMSK_GINAKEFFM               USB_OTG_GINTMSK_GINAKEFFM_Msk  /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM_Pos           (7U)                           
-#define USB_OTG_GINTMSK_GONAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
-#define USB_OTG_GINTMSK_GONAKEFFM               USB_OTG_GINTMSK_GONAKEFFM_Msk  /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM_Pos              (10U)                          
-#define USB_OTG_GINTMSK_ESUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GINTMSK_ESUSPM                  USB_OTG_GINTMSK_ESUSPM_Msk     /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM_Pos            (11U)                          
-#define USB_OTG_GINTMSK_USBSUSPM_Msk            (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
-#define USB_OTG_GINTMSK_USBSUSPM                USB_OTG_GINTMSK_USBSUSPM_Msk   /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST_Pos              (12U)                          
-#define USB_OTG_GINTMSK_USBRST_Msk              (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
-#define USB_OTG_GINTMSK_USBRST                  USB_OTG_GINTMSK_USBRST_Msk     /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM_Pos            (13U)                          
-#define USB_OTG_GINTMSK_ENUMDNEM_Msk            (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
-#define USB_OTG_GINTMSK_ENUMDNEM                USB_OTG_GINTMSK_ENUMDNEM_Msk   /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM_Pos            (14U)                          
-#define USB_OTG_GINTMSK_ISOODRPM_Msk            (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
-#define USB_OTG_GINTMSK_ISOODRPM                USB_OTG_GINTMSK_ISOODRPM_Msk   /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM_Pos               (15U)                          
-#define USB_OTG_GINTMSK_EOPFM_Msk               (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
-#define USB_OTG_GINTMSK_EOPFM                   USB_OTG_GINTMSK_EOPFM_Msk      /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM_Pos              (17U)                          
-#define USB_OTG_GINTMSK_EPMISM_Msk              (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
-#define USB_OTG_GINTMSK_EPMISM                  USB_OTG_GINTMSK_EPMISM_Msk     /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT_Pos              (18U)                          
-#define USB_OTG_GINTMSK_IEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
-#define USB_OTG_GINTMSK_IEPINT                  USB_OTG_GINTMSK_IEPINT_Msk     /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT_Pos              (19U)                          
-#define USB_OTG_GINTMSK_OEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
-#define USB_OTG_GINTMSK_OEPINT                  USB_OTG_GINTMSK_OEPINT_Msk     /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM_Pos           (20U)                          
-#define USB_OTG_GINTMSK_IISOIXFRM_Msk           (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
-#define USB_OTG_GINTMSK_IISOIXFRM               USB_OTG_GINTMSK_IISOIXFRM_Msk  /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos     (21U)                          
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk     (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM_Pos              (22U)                          
-#define USB_OTG_GINTMSK_FSUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
-#define USB_OTG_GINTMSK_FSUSPM                  USB_OTG_GINTMSK_FSUSPM_Msk     /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM_Pos               (24U)                          
-#define USB_OTG_GINTMSK_PRTIM_Msk               (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
-#define USB_OTG_GINTMSK_PRTIM                   USB_OTG_GINTMSK_PRTIM_Msk      /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM_Pos                (25U)                          
-#define USB_OTG_GINTMSK_HCIM_Msk                (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
-#define USB_OTG_GINTMSK_HCIM                    USB_OTG_GINTMSK_HCIM_Msk       /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM_Pos              (26U)                          
-#define USB_OTG_GINTMSK_PTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
-#define USB_OTG_GINTMSK_PTXFEM                  USB_OTG_GINTMSK_PTXFEM_Msk     /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM_Pos            (28U)                          
-#define USB_OTG_GINTMSK_CIDSCHGM_Msk            (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
-#define USB_OTG_GINTMSK_CIDSCHGM                USB_OTG_GINTMSK_CIDSCHGM_Msk   /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT_Pos             (29U)                          
-#define USB_OTG_GINTMSK_DISCINT_Msk             (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
-#define USB_OTG_GINTMSK_DISCINT                 USB_OTG_GINTMSK_DISCINT_Msk    /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM_Pos               (30U)                          
-#define USB_OTG_GINTMSK_SRQIM_Msk               (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
-#define USB_OTG_GINTMSK_SRQIM                   USB_OTG_GINTMSK_SRQIM_Msk      /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM_Pos                (31U)                          
-#define USB_OTG_GINTMSK_WUIM_Msk                (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
-#define USB_OTG_GINTMSK_WUIM                    USB_OTG_GINTMSK_WUIM_Msk       /*!< Resume/remote wakeup detected interrupt mask */
+/********************  Bit definition for GRXSTSP register  ********************/
+#define GRXSTSP_EPNUM_Pos                (0U)
+#define GRXSTSP_EPNUM_Msk                (0xFUL << GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define GRXSTSP_EPNUM                    GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define GRXSTSP_BCNT_Pos                 (4U)
+#define GRXSTSP_BCNT_Msk                 (0x7FFUL << GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define GRXSTSP_BCNT                     GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define GRXSTSP_DPID_Pos                 (15U)
+#define GRXSTSP_DPID_Msk                 (0x3UL << GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define GRXSTSP_DPID                     GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define GRXSTSP_PKTSTS_Pos               (17U)
+#define GRXSTSP_PKTSTS_Msk               (0xFUL << GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define GRXSTSP_PKTSTS                   GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
 
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT_Pos                (0U)                           
-#define USB_OTG_DAINT_IEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DAINT_IEPINT                    USB_OTG_DAINT_IEPINT_Msk       /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT_Pos                (16U)                          
-#define USB_OTG_DAINT_OEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DAINT_OEPINT                    USB_OTG_DAINT_OEPINT_Msk       /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM_Pos             (0U)                           
-#define USB_OTG_HAINTMSK_HAINTM_Msk             (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HAINTMSK_HAINTM                 USB_OTG_HAINTMSK_HAINTM_Msk    /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM_Pos               (0U)                           
-#define USB_OTG_GRXSTSP_EPNUM_Msk               (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
-#define USB_OTG_GRXSTSP_EPNUM                   USB_OTG_GRXSTSP_EPNUM_Msk      /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT_Pos                (4U)                           
-#define USB_OTG_GRXSTSP_BCNT_Msk                (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
-#define USB_OTG_GRXSTSP_BCNT                    USB_OTG_GRXSTSP_BCNT_Msk       /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID_Pos                (15U)                          
-#define USB_OTG_GRXSTSP_DPID_Msk                (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
-#define USB_OTG_GRXSTSP_DPID                    USB_OTG_GRXSTSP_DPID_Msk       /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS_Pos              (17U)                          
-#define USB_OTG_GRXSTSP_PKTSTS_Msk              (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
-#define USB_OTG_GRXSTSP_PKTSTS                  USB_OTG_GRXSTSP_PKTSTS_Msk     /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM_Pos               (0U)                           
-#define USB_OTG_DAINTMSK_IEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DAINTMSK_IEPM                   USB_OTG_DAINTMSK_IEPM_Msk      /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM_Pos               (16U)                          
-#define USB_OTG_DAINTMSK_OEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DAINTMSK_OEPM                   USB_OTG_DAINTMSK_OEPM_Msk      /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD_Pos                (0U)                           
-#define USB_OTG_GRXFSIZ_RXFD_Msk                (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_GRXFSIZ_RXFD                    USB_OTG_GRXFSIZ_RXFD_Msk       /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT_Pos             (0U)                           
-#define USB_OTG_DVBUSDIS_VBUSDT_Msk             (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DVBUSDIS_VBUSDT                 USB_OTG_DVBUSDIS_VBUSDT_Msk    /*!< Device VBUS discharge time */
+/********************  Bit definition for DAINTMSK register  ********************/
+#define DAINTMSK_IEPM_Pos                (0U)
+#define DAINTMSK_IEPM_Msk                (0xFFFFUL << DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define DAINTMSK_IEPM                    DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define DAINTMSK_OEPM_Pos                (16U)
+#define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA_Pos                     (0U)                           
-#define USB_OTG_NPTXFSA_Msk                     (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_NPTXFSA                         USB_OTG_NPTXFSA_Msk            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD_Pos                      (16U)                          
-#define USB_OTG_NPTXFD_Msk                      (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_NPTXFD                          USB_OTG_NPTXFD_Msk             /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA_Pos                      (0U)                           
-#define USB_OTG_TX0FSA_Msk                      (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_TX0FSA                          USB_OTG_TX0FSA_Msk             /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD_Pos                       (16U)                          
-#define USB_OTG_TX0FD_Msk                       (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_TX0FD                           USB_OTG_TX0FD_Msk              /*!< Endpoint 0 TxFIFO depth */
 
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP_Pos           (0U)                           
-#define USB_OTG_DVBUSPULSE_DVBUSP_Msk           (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
-#define USB_OTG_DVBUSPULSE_DVBUSP               USB_OTG_DVBUSPULSE_DVBUSP_Msk  /*!< Device VBUS pulsing time */
+#define CHNUM_Pos                        (0U)
+#define CHNUM_Msk                        (0xFUL << CHNUM_Pos)   /*!< 0x0000000F */
+#define CHNUM                            CHNUM_Msk             /*!< Channel number */
+#define CHNUM_0                          (0x1UL << CHNUM_Pos)   /*!< 0x00000001 */
+#define CHNUM_1                          (0x2UL << CHNUM_Pos)   /*!< 0x00000002 */
+#define CHNUM_2                          (0x4UL << CHNUM_Pos)   /*!< 0x00000004 */
+#define CHNUM_3                          (0x8UL << CHNUM_Pos)   /*!< 0x00000008 */
+#define BCNT_Pos                         (4U)
+#define BCNT_Msk                         (0x7FFUL << BCNT_Pos)  /*!< 0x00007FF0 */
+#define BCNT                             BCNT_Msk              /*!< Byte count */
 
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos           (0U)                           
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk           (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_GNPTXSTS_NPTXFSAV               USB_OTG_GNPTXSTS_NPTXFSAV_Msk  /*!< Nonperiodic TxFIFO space available */
+#define DPID_Pos                         (15U)
+#define DPID_Msk                         (0x3UL << DPID_Pos)    /*!< 0x00018000 */
+#define DPID                             DPID_Msk              /*!< Data PID */
+#define DPID_0                           (0x1UL << DPID_Pos)    /*!< 0x00008000 */
+#define DPID_1                           (0x2UL << DPID_Pos)    /*!< 0x00010000 */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos           (16U)                          
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk           (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV               USB_OTG_GNPTXSTS_NPTQXSAV_Msk  /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0             (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1             (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2             (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3             (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4             (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5             (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6             (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7             (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+#define PKTSTS_Pos                       (17U)
+#define PKTSTS_Msk                       (0xFUL << PKTSTS_Pos)  /*!< 0x001E0000 */
+#define PKTSTS                           PKTSTS_Msk            /*!< Packet status */
+#define PKTSTS_0                         (0x1UL << PKTSTS_Pos)  /*!< 0x00020000 */
+#define PKTSTS_1                         (0x2UL << PKTSTS_Pos)  /*!< 0x00040000 */
+#define PKTSTS_2                         (0x4UL << PKTSTS_Pos)  /*!< 0x00080000 */
+#define PKTSTS_3                         (0x8UL << PKTSTS_Pos)  /*!< 0x00100000 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos           (24U)                          
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk           (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP               USB_OTG_GNPTXSTS_NPTXQTOP_Msk  /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0             (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1             (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2             (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3             (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4             (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5             (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6             (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+#define EPNUM_Pos                        (0U)
+#define EPNUM_Msk                        (0xFUL << EPNUM_Pos)   /*!< 0x0000000F */
+#define EPNUM                            EPNUM_Msk             /*!< Endpoint number */
+#define EPNUM_0                          (0x1UL << EPNUM_Pos)   /*!< 0x00000001 */
+#define EPNUM_1                          (0x2UL << EPNUM_Pos)   /*!< 0x00000002 */
+#define EPNUM_2                          (0x4UL << EPNUM_Pos)   /*!< 0x00000004 */
+#define EPNUM_3                          (0x8UL << EPNUM_Pos)   /*!< 0x00000008 */
 
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN_Pos         (0U)                           
-#define USB_OTG_DTHRCTL_NONISOTHREN_Msk         (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
-#define USB_OTG_DTHRCTL_NONISOTHREN             USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN_Pos            (1U)                           
-#define USB_OTG_DTHRCTL_ISOTHREN_Msk            (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
-#define USB_OTG_DTHRCTL_ISOTHREN                USB_OTG_DTHRCTL_ISOTHREN_Msk   /*!< ISO IN endpoint threshold enable */
+#define FRMNUM_Pos                       (21U)
+#define FRMNUM_Msk                       (0xFUL << FRMNUM_Pos)  /*!< 0x01E00000 */
+#define FRMNUM                           FRMNUM_Msk            /*!< Frame number */
+#define FRMNUM_0                         (0x1UL << FRMNUM_Pos)  /*!< 0x00200000 */
+#define FRMNUM_1                         (0x2UL << FRMNUM_Pos)  /*!< 0x00400000 */
+#define FRMNUM_2                         (0x4UL << FRMNUM_Pos)  /*!< 0x00800000 */
+#define FRMNUM_3                         (0x8UL << FRMNUM_Pos)  /*!< 0x01000000 */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN_Pos            (2U)                           
-#define USB_OTG_DTHRCTL_TXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
-#define USB_OTG_DTHRCTL_TXTHRLEN                USB_OTG_DTHRCTL_TXTHRLEN_Msk   /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_DTHRCTL_RXTHREN_Pos             (16U)                          
-#define USB_OTG_DTHRCTL_RXTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
-#define USB_OTG_DTHRCTL_RXTHREN                 USB_OTG_DTHRCTL_RXTHREN_Msk    /*!< Receive threshold enable */
+/********************  Bit definition for GRXFSIZ register  ********************/
+#define GRXFSIZ_RXFD_Pos                 (0U)
+#define GRXFSIZ_RXFD_Msk                 (0xFFFFUL << GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define GRXFSIZ_RXFD                     GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN_Pos            (17U)                          
-#define USB_OTG_DTHRCTL_RXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN                USB_OTG_DTHRCTL_RXTHRLEN_Msk   /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
-#define USB_OTG_DTHRCTL_ARPEN_Pos               (27U)                          
-#define USB_OTG_DTHRCTL_ARPEN_Msk               (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
-#define USB_OTG_DTHRCTL_ARPEN                   USB_OTG_DTHRCTL_ARPEN_Msk      /*!< Arbiter parking enable */
+/********************  Bit definition for DVBUSDIS register  ********************/
+#define DVBUSDIS_VBUSDT_Pos              (0U)
+#define DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
 
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos        (0U)                           
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk        (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM            USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+/********************  Bit definition for OTG register  ********************/
+#define NPTXFSA_Pos                      (0U)
+#define NPTXFSA_Msk                      (0xFFFFUL << NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define NPTXFSA                          NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define NPTXFD_Pos                       (16U)
+#define NPTXFD_Msk                       (0xFFFFUL << NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define NPTXFD                           NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define TX0FSA_Pos                       (0U)
+#define TX0FSA_Msk                       (0xFFFFUL << TX0FSA_Pos) /*!< 0x0000FFFF */
+#define TX0FSA                           TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define TX0FD_Pos                        (16U)
+#define TX0FD_Msk                        (0xFFFFUL << TX0FD_Pos) /*!< 0xFFFF0000 */
+#define TX0FD                            TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
 
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT_Pos            (1U)                           
-#define USB_OTG_DEACHINT_IEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
-#define USB_OTG_DEACHINT_IEP1INT                USB_OTG_DEACHINT_IEP1INT_Msk   /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT_Pos            (17U)                          
-#define USB_OTG_DEACHINT_OEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
-#define USB_OTG_DEACHINT_OEP1INT                USB_OTG_DEACHINT_OEP1INT_Msk   /*!< OUT endpoint 1 interrupt bit */
+/********************  Bit definition for DVBUSPULSE register  ********************/
+#define DVBUSPULSE_DVBUSP_Pos            (0U)
+#define DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define DVBUSPULSE_DVBUSP                DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
 
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN_Pos                (16U)                          
-#define USB_OTG_GCCFG_PWRDWN_Msk                (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
-#define USB_OTG_GCCFG_PWRDWN                    USB_OTG_GCCFG_PWRDWN_Msk       /*!< Power down */
-#define USB_OTG_GCCFG_VBUSASEN_Pos              (18U)                          
-#define USB_OTG_GCCFG_VBUSASEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
-#define USB_OTG_GCCFG_VBUSASEN                  USB_OTG_GCCFG_VBUSASEN_Msk     /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN_Pos              (19U)                          
-#define USB_OTG_GCCFG_VBUSBSEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
-#define USB_OTG_GCCFG_VBUSBSEN                  USB_OTG_GCCFG_VBUSBSEN_Msk     /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN_Pos              (20U)                          
-#define USB_OTG_GCCFG_SOFOUTEN_Msk              (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
-#define USB_OTG_GCCFG_SOFOUTEN                  USB_OTG_GCCFG_SOFOUTEN_Msk     /*!< SOF output enable */
+/********************  Bit definition for GNPTXSTS register  ********************/
+#define GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define GNPTXSTS_NPTXFSAV                GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
 
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos        (1U)                           
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DEACHINTMSK_IEP1INTM            USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos        (17U)                          
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
-#define USB_OTG_DEACHINTMSK_OEP1INTM            USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+#define GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define GNPTXSTS_NPTQXSAV                GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define GNPTXSTS_NPTQXSAV_0              (0x01UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define GNPTXSTS_NPTQXSAV_1              (0x02UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define GNPTXSTS_NPTQXSAV_2              (0x04UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define GNPTXSTS_NPTQXSAV_3              (0x08UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define GNPTXSTS_NPTQXSAV_4              (0x10UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define GNPTXSTS_NPTQXSAV_5              (0x20UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define GNPTXSTS_NPTQXSAV_6              (0x40UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define GNPTXSTS_NPTQXSAV_7              (0x80UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
 
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID_Pos              (0U)                           
-#define USB_OTG_CID_PRODUCT_ID_Msk              (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_CID_PRODUCT_ID                  USB_OTG_CID_PRODUCT_ID_Msk     /*!< Product ID field */
+#define GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define GNPTXSTS_NPTXQTOP                GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define GNPTXSTS_NPTXQTOP_0              (0x01UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define GNPTXSTS_NPTXQTOP_1              (0x02UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define GNPTXSTS_NPTXQTOP_2              (0x04UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define GNPTXSTS_NPTXQTOP_3              (0x08UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define GNPTXSTS_NPTXQTOP_4              (0x10UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define GNPTXSTS_NPTXQTOP_5              (0x20UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define GNPTXSTS_NPTXQTOP_6              (0x40UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
 
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos          (0U)                           
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPEACHMSK1_XFRCM              USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM_Pos           (1U)                           
-#define USB_OTG_DIEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPEACHMSK1_EPDM               USB_OTG_DIEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM_Pos            (3U)                           
-#define USB_OTG_DIEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPEACHMSK1_TOM                USB_OTG_DIEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK          USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos        (5U)                           
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM            USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos        (6U)                           
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM            USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos         (8U)                           
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPEACHMSK1_TXFURM             USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM_Pos            (9U)                           
-#define USB_OTG_DIEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPEACHMSK1_BIM                USB_OTG_DIEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM_Pos           (13U)                          
-#define USB_OTG_DIEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DIEPEACHMSK1_NAKM               USB_OTG_DIEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
+/********************  Bit definition for DTHRCTL register  ********************/
+#define DTHRCTL_NONISOTHREN_Pos          (0U)
+#define DTHRCTL_NONISOTHREN_Msk          (0x1UL << DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define DTHRCTL_NONISOTHREN              DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define DTHRCTL_ISOTHREN_Pos             (1U)
+#define DTHRCTL_ISOTHREN_Msk             (0x1UL << DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define DTHRCTL_ISOTHREN                 DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
 
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS_Pos                  (0U)                           
-#define USB_OTG_HPRT_PCSTS_Msk                  (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
-#define USB_OTG_HPRT_PCSTS                      USB_OTG_HPRT_PCSTS_Msk         /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET_Pos                  (1U)                           
-#define USB_OTG_HPRT_PCDET_Msk                  (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
-#define USB_OTG_HPRT_PCDET                      USB_OTG_HPRT_PCDET_Msk         /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA_Pos                   (2U)                           
-#define USB_OTG_HPRT_PENA_Msk                   (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
-#define USB_OTG_HPRT_PENA                       USB_OTG_HPRT_PENA_Msk          /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG_Pos                (3U)                           
-#define USB_OTG_HPRT_PENCHNG_Msk                (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
-#define USB_OTG_HPRT_PENCHNG                    USB_OTG_HPRT_PENCHNG_Msk       /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA_Pos                   (4U)                           
-#define USB_OTG_HPRT_POCA_Msk                   (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
-#define USB_OTG_HPRT_POCA                       USB_OTG_HPRT_POCA_Msk          /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG_Pos                (5U)                           
-#define USB_OTG_HPRT_POCCHNG_Msk                (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
-#define USB_OTG_HPRT_POCCHNG                    USB_OTG_HPRT_POCCHNG_Msk       /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES_Pos                   (6U)                           
-#define USB_OTG_HPRT_PRES_Msk                   (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
-#define USB_OTG_HPRT_PRES                       USB_OTG_HPRT_PRES_Msk          /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP_Pos                  (7U)                           
-#define USB_OTG_HPRT_PSUSP_Msk                  (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
-#define USB_OTG_HPRT_PSUSP                      USB_OTG_HPRT_PSUSP_Msk         /*!< Port suspend */
-#define USB_OTG_HPRT_PRST_Pos                   (8U)                           
-#define USB_OTG_HPRT_PRST_Msk                   (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
-#define USB_OTG_HPRT_PRST                       USB_OTG_HPRT_PRST_Msk          /*!< Port reset */
+#define DTHRCTL_TXTHRLEN_Pos             (2U)
+#define DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define DTHRCTL_TXTHRLEN                 DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define DTHRCTL_TXTHRLEN_0               (0x001UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define DTHRCTL_TXTHRLEN_1               (0x002UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define DTHRCTL_TXTHRLEN_2               (0x004UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define DTHRCTL_TXTHRLEN_3               (0x008UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define DTHRCTL_TXTHRLEN_4               (0x010UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define DTHRCTL_TXTHRLEN_5               (0x020UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define DTHRCTL_TXTHRLEN_6               (0x040UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define DTHRCTL_TXTHRLEN_7               (0x080UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define DTHRCTL_TXTHRLEN_8               (0x100UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define DTHRCTL_RXTHREN_Pos              (16U)
+#define DTHRCTL_RXTHREN_Msk              (0x1UL << DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define DTHRCTL_RXTHREN                  DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
 
-#define USB_OTG_HPRT_PLSTS_Pos                  (10U)                          
-#define USB_OTG_HPRT_PLSTS_Msk                  (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
-#define USB_OTG_HPRT_PLSTS                      USB_OTG_HPRT_PLSTS_Msk         /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                    (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
-#define USB_OTG_HPRT_PLSTS_1                    (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_HPRT_PPWR_Pos                   (12U)                          
-#define USB_OTG_HPRT_PPWR_Msk                   (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
-#define USB_OTG_HPRT_PPWR                       USB_OTG_HPRT_PPWR_Msk          /*!< Port power */
+#define DTHRCTL_RXTHRLEN_Pos             (17U)
+#define DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define DTHRCTL_RXTHRLEN                 DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define DTHRCTL_RXTHRLEN_0               (0x001UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define DTHRCTL_RXTHRLEN_1               (0x002UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define DTHRCTL_RXTHRLEN_2               (0x004UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define DTHRCTL_RXTHRLEN_3               (0x008UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define DTHRCTL_RXTHRLEN_4               (0x010UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define DTHRCTL_RXTHRLEN_5               (0x020UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define DTHRCTL_RXTHRLEN_6               (0x040UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define DTHRCTL_RXTHRLEN_7               (0x080UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define DTHRCTL_RXTHRLEN_8               (0x100UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define DTHRCTL_ARPEN_Pos                (27U)
+#define DTHRCTL_ARPEN_Msk                (0x1UL << DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define DTHRCTL_ARPEN                    DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
 
-#define USB_OTG_HPRT_PTCTL_Pos                  (13U)                          
-#define USB_OTG_HPRT_PTCTL_Msk                  (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
-#define USB_OTG_HPRT_PTCTL                      USB_OTG_HPRT_PTCTL_Msk         /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                    (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
-#define USB_OTG_HPRT_PTCTL_1                    (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
-#define USB_OTG_HPRT_PTCTL_2                    (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
-#define USB_OTG_HPRT_PTCTL_3                    (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+/********************  Bit definition for DIEPEMPMSK register  ********************/
+#define DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define DIEPEMPMSK_INEPTXFEM             DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
 
-#define USB_OTG_HPRT_PSPD_Pos                   (17U)                          
-#define USB_OTG_HPRT_PSPD_Msk                   (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
-#define USB_OTG_HPRT_PSPD                       USB_OTG_HPRT_PSPD_Msk          /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                     (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
-#define USB_OTG_HPRT_PSPD_1                     (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+/********************  Bit definition for DEACHINT register  ********************/
+#define DEACHINT_IEP1INT_Pos             (1U)
+#define DEACHINT_IEP1INT_Msk             (0x1UL << DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define DEACHINT_IEP1INT                 DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define DEACHINT_OEP1INT_Pos             (17U)
+#define DEACHINT_OEP1INT_Msk             (0x1UL << DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define DEACHINT_OEP1INT                 DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
 
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos          (0U)                           
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPEACHMSK1_XFRCM              USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM_Pos           (1U)                           
-#define USB_OTG_DOEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPEACHMSK1_EPDM               USB_OTG_DOEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM_Pos            (3U)                           
-#define USB_OTG_DOEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPEACHMSK1_TOM                USB_OTG_DOEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK          USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos        (5U)                           
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM            USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos        (6U)                           
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM            USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos         (8U)                           
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPEACHMSK1_TXFURM             USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM_Pos            (9U)                           
-#define USB_OTG_DOEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DOEPEACHMSK1_BIM                USB_OTG_DOEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM_Pos          (12U)                          
-#define USB_OTG_DOEPEACHMSK1_BERRM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
-#define USB_OTG_DOEPEACHMSK1_BERRM              USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM_Pos           (13U)                          
-#define USB_OTG_DOEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPEACHMSK1_NAKM               USB_OTG_DOEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM_Pos          (14U)                          
-#define USB_OTG_DOEPEACHMSK1_NYETM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPEACHMSK1_NYETM              USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+/********************  Bit definition for GCCFG register  ********************/
+#define GCCFG_DCDET_Pos                  (0U)
+#define GCCFG_DCDET_Msk                  (0x1UL << GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define GCCFG_DCDET                      GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define GCCFG_PDET_Pos                   (1U)
+#define GCCFG_PDET_Msk                   (0x1UL << GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define GCCFG_PDET                       GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define GCCFG_SDET_Pos                   (2U)
+#define GCCFG_SDET_Msk                   (0x1UL << GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define GCCFG_SDET                       GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define GCCFG_PS2DET_Pos                 (3U)
+#define GCCFG_PS2DET_Msk                 (0x1UL << GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define GCCFG_PS2DET                     GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define GCCFG_PWRDWN_Pos                 (16U)
+#define GCCFG_PWRDWN_Msk                 (0x1UL << GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define GCCFG_PWRDWN                     GCCFG_PWRDWN_Msk      /*!< Power down */
+#define GCCFG_BCDEN_Pos                  (17U)
+#define GCCFG_BCDEN_Msk                  (0x1UL << GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define GCCFG_BCDEN                      GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define GCCFG_DCDEN_Pos                  (18U)
+#define GCCFG_DCDEN_Msk                  (0x1UL << GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define GCCFG_DCDEN                      GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define GCCFG_PDEN_Pos                   (19U)
+#define GCCFG_PDEN_Msk                   (0x1UL << GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define GCCFG_PDEN                       GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define GCCFG_SDEN_Pos                   (20U)
+#define GCCFG_SDEN_Msk                   (0x1UL << GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define GCCFG_SDEN                       GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define GCCFG_VBDEN_Pos                  (21U)
+#define GCCFG_VBDEN_Msk                  (0x1UL << GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define GCCFG_VBDEN                      GCCFG_VBDEN_Msk       /*!< VBUS mode enable */
+#define GCCFG_OTGIDEN_Pos                (22U)
+#define GCCFG_OTGIDEN_Msk                (0x1UL << GCCFG_OTGIDEN_Pos) /*!< 0x00400000 */
+#define GCCFG_OTGIDEN                    GCCFG_OTGIDEN_Msk     /*!< OTG Id enable */
+#define GCCFG_PHYHSEN_Pos                (23U)
+#define GCCFG_PHYHSEN_Msk                (0x1UL << GCCFG_PHYHSEN_Pos) /*!< 0x00800000 */
+#define GCCFG_PHYHSEN                    GCCFG_PHYHSEN_Msk     /*!< HS PHY enable */
 
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA_Pos              (0U)                           
-#define USB_OTG_HPTXFSIZ_PTXSA_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HPTXFSIZ_PTXSA                  USB_OTG_HPTXFSIZ_PTXSA_Msk     /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD_Pos              (16U)                          
-#define USB_OTG_HPTXFSIZ_PTXFD_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_HPTXFSIZ_PTXFD                  USB_OTG_HPTXFSIZ_PTXFD_Msk     /*!< Host periodic TxFIFO depth */
+/********************  Bit definition for DEACHINTMSK register  ********************/
+#define DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define DEACHINTMSK_IEP1INTM_Msk         (0x1UL << DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define DEACHINTMSK_IEP1INTM             DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define DEACHINTMSK_OEP1INTM_Msk         (0x1UL << DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define DEACHINTMSK_OEP1INTM             DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
 
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ_Pos               (0U)                           
-#define USB_OTG_DIEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_DIEPCTL_MPSIZ                   USB_OTG_DIEPCTL_MPSIZ_Msk      /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP_Pos              (15U)                          
-#define USB_OTG_DIEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define USB_OTG_DIEPCTL_USBAEP                  USB_OTG_DIEPCTL_USBAEP_Msk     /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID_Pos          (16U)                          
-#define USB_OTG_DIEPCTL_EONUM_DPID_Msk          (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
-#define USB_OTG_DIEPCTL_EONUM_DPID              USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS_Pos              (17U)                          
-#define USB_OTG_DIEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define USB_OTG_DIEPCTL_NAKSTS                  USB_OTG_DIEPCTL_NAKSTS_Msk     /*!< NAK status */
+/********************  Bit definition for CID register  ********************/
+#define CID_PRODUCT_ID_Pos               (0U)
+#define CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define CID_PRODUCT_ID                   CID_PRODUCT_ID_Msk    /*!< Product ID field */
 
-#define USB_OTG_DIEPCTL_EPTYP_Pos               (18U)                          
-#define USB_OTG_DIEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_DIEPCTL_EPTYP                   USB_OTG_DIEPCTL_EPTYP_Msk      /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DIEPCTL_STALL_Pos               (21U)                          
-#define USB_OTG_DIEPCTL_STALL_Msk               (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define USB_OTG_DIEPCTL_STALL                   USB_OTG_DIEPCTL_STALL_Msk      /*!< STALL handshake */
+/********************  Bit definition for GLPMCFG register  ********************/
+#define GLPMCFG_LPMEN_Pos                (0U)
+#define GLPMCFG_LPMEN_Msk                (0x1UL << GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define GLPMCFG_LPMEN                    GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define GLPMCFG_LPMACK_Pos               (1U)
+#define GLPMCFG_LPMACK_Msk               (0x1UL << GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define GLPMCFG_LPMACK                   GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define GLPMCFG_BESL_Pos                 (2U)
+#define GLPMCFG_BESL_Msk                 (0xFUL << GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define GLPMCFG_BESL                     GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define GLPMCFG_REMWAKE_Pos              (6U)
+#define GLPMCFG_REMWAKE_Msk              (0x1UL << GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define GLPMCFG_REMWAKE                  GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define GLPMCFG_L1SSEN_Pos               (7U)
+#define GLPMCFG_L1SSEN_Msk               (0x1UL << GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define GLPMCFG_L1SSEN                   GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define GLPMCFG_BESLTHRS_Pos             (8U)
+#define GLPMCFG_BESLTHRS_Msk             (0xFUL << GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define GLPMCFG_BESLTHRS                 GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define GLPMCFG_L1DSEN_Pos               (12U)
+#define GLPMCFG_L1DSEN_Msk               (0x1UL << GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define GLPMCFG_L1DSEN                   GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define GLPMCFG_LPMRSP_Pos               (13U)
+#define GLPMCFG_LPMRSP_Msk               (0x3UL << GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define GLPMCFG_LPMRSP                   GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define GLPMCFG_SLPSTS_Pos               (15U)
+#define GLPMCFG_SLPSTS_Msk               (0x1UL << GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define GLPMCFG_SLPSTS                   GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define GLPMCFG_L1RSMOK_Pos              (16U)
+#define GLPMCFG_L1RSMOK_Msk              (0x1UL << GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define GLPMCFG_L1RSMOK                  GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define GLPMCFG_LPMCHIDX_Pos             (17U)
+#define GLPMCFG_LPMCHIDX_Msk             (0xFUL << GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define GLPMCFG_LPMCHIDX                 GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define GLPMCFG_LPMRCNT_Pos              (21U)
+#define GLPMCFG_LPMRCNT_Msk              (0x7UL << GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define GLPMCFG_LPMRCNT                  GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define GLPMCFG_SNDLPM_Pos               (24U)
+#define GLPMCFG_SNDLPM_Msk               (0x1UL << GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define GLPMCFG_SNDLPM                   GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define GLPMCFG_LPMRCNTSTS               GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define GLPMCFG_ENBESL_Pos               (28U)
+#define GLPMCFG_ENBESL_Msk               (0x1UL << GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define GLPMCFG_ENBESL                   GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
 
-#define USB_OTG_DIEPCTL_TXFNUM_Pos              (22U)                          
-#define USB_OTG_DIEPCTL_TXFNUM_Msk              (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
-#define USB_OTG_DIEPCTL_TXFNUM                  USB_OTG_DIEPCTL_TXFNUM_Msk     /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
-#define USB_OTG_DIEPCTL_CNAK_Pos                (26U)                          
-#define USB_OTG_DIEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define USB_OTG_DIEPCTL_CNAK                    USB_OTG_DIEPCTL_CNAK_Msk       /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK_Pos                (27U)                          
-#define USB_OTG_DIEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define USB_OTG_DIEPCTL_SNAK                    USB_OTG_DIEPCTL_SNAK_Msk       /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM_Pos             (29U)                          
-#define USB_OTG_DIEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_DIEPCTL_SODDFRM                 USB_OTG_DIEPCTL_SODDFRM_Msk    /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS_Pos               (30U)                          
-#define USB_OTG_DIEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_DIEPCTL_EPDIS                   USB_OTG_DIEPCTL_EPDIS_Msk      /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA_Pos               (31U)                          
-#define USB_OTG_DIEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_DIEPCTL_EPENA                   USB_OTG_DIEPCTL_EPENA_Msk      /*!< Endpoint enable */
+/********************  Bit definition for DIEPEACHMSK1 register  ********************/
+#define DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define DIEPEACHMSK1_XFRCM_Msk           (0x1UL << DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define DIEPEACHMSK1_XFRCM               DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define DIEPEACHMSK1_EPDM_Pos            (1U)
+#define DIEPEACHMSK1_EPDM_Msk            (0x1UL << DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define DIEPEACHMSK1_EPDM                DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define DIEPEACHMSK1_TOM_Pos             (3U)
+#define DIEPEACHMSK1_TOM_Msk             (0x1UL << DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define DIEPEACHMSK1_TOM                 DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define DIEPEACHMSK1_ITTXFEMSK           DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define DIEPEACHMSK1_INEPNMM             DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define DIEPEACHMSK1_INEPNEM             DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define DIEPEACHMSK1_TXFURM_Msk          (0x1UL << DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define DIEPEACHMSK1_TXFURM              DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
+#define DIEPEACHMSK1_BIM_Pos             (9U)
+#define DIEPEACHMSK1_BIM_Msk             (0x1UL << DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define DIEPEACHMSK1_BIM                 DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
+#define DIEPEACHMSK1_NAKM_Pos            (13U)
+#define DIEPEACHMSK1_NAKM_Msk            (0x1UL << DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define DIEPEACHMSK1_NAKM                DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
 
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ_Pos                (0U)                           
-#define USB_OTG_HCCHAR_MPSIZ_Msk                (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_HCCHAR_MPSIZ                    USB_OTG_HCCHAR_MPSIZ_Msk       /*!< Maximum packet size */
+/********************  Bit definition for HPRT register  ********************/
+#define HPRT_PCSTS_Pos                   (0U)
+#define HPRT_PCSTS_Msk                   (0x1UL << HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define HPRT_PCSTS                       HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define HPRT_PCDET_Pos                   (1U)
+#define HPRT_PCDET_Msk                   (0x1UL << HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define HPRT_PCDET                       HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define HPRT_PENA_Pos                    (2U)
+#define HPRT_PENA_Msk                    (0x1UL << HPRT_PENA_Pos) /*!< 0x00000004 */
+#define HPRT_PENA                        HPRT_PENA_Msk         /*!< Port enable                */
+#define HPRT_PENCHNG_Pos                 (3U)
+#define HPRT_PENCHNG_Msk                 (0x1UL << HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define HPRT_PENCHNG                     HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define HPRT_POCA_Pos                    (4U)
+#define HPRT_POCA_Msk                    (0x1UL << HPRT_POCA_Pos) /*!< 0x00000010 */
+#define HPRT_POCA                        HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define HPRT_POCCHNG_Pos                 (5U)
+#define HPRT_POCCHNG_Msk                 (0x1UL << HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define HPRT_POCCHNG                     HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define HPRT_PRES_Pos                    (6U)
+#define HPRT_PRES_Msk                    (0x1UL << HPRT_PRES_Pos) /*!< 0x00000040 */
+#define HPRT_PRES                        HPRT_PRES_Msk         /*!< Port resume                */
+#define HPRT_PSUSP_Pos                   (7U)
+#define HPRT_PSUSP_Msk                   (0x1UL << HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define HPRT_PSUSP                       HPRT_PSUSP_Msk        /*!< Port suspend               */
+#define HPRT_PRST_Pos                    (8U)
+#define HPRT_PRST_Msk                    (0x1UL << HPRT_PRST_Pos) /*!< 0x00000100 */
+#define HPRT_PRST                        HPRT_PRST_Msk         /*!< Port reset                 */
 
-#define USB_OTG_HCCHAR_EPNUM_Pos                (11U)                          
-#define USB_OTG_HCCHAR_EPNUM_Msk                (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
-#define USB_OTG_HCCHAR_EPNUM                    USB_OTG_HCCHAR_EPNUM_Msk       /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                  (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
-#define USB_OTG_HCCHAR_EPNUM_1                  (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
-#define USB_OTG_HCCHAR_EPNUM_2                  (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
-#define USB_OTG_HCCHAR_EPNUM_3                  (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCCHAR_EPDIR_Pos                (15U)                          
-#define USB_OTG_HCCHAR_EPDIR_Msk                (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCCHAR_EPDIR                    USB_OTG_HCCHAR_EPDIR_Msk       /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV_Pos                (17U)                          
-#define USB_OTG_HCCHAR_LSDEV_Msk                (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
-#define USB_OTG_HCCHAR_LSDEV                    USB_OTG_HCCHAR_LSDEV_Msk       /*!< Low-speed device */
+#define HPRT_PLSTS_Pos                   (10U)
+#define HPRT_PLSTS_Msk                   (0x3UL << HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define HPRT_PLSTS                       HPRT_PLSTS_Msk        /*!< Port line status           */
+#define HPRT_PLSTS_0                     (0x1UL << HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define HPRT_PLSTS_1                     (0x2UL << HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define HPRT_PPWR_Pos                    (12U)
+#define HPRT_PPWR_Msk                    (0x1UL << HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define HPRT_PPWR                        HPRT_PPWR_Msk         /*!< Port power                 */
 
-#define USB_OTG_HCCHAR_EPTYP_Pos                (18U)                          
-#define USB_OTG_HCCHAR_EPTYP_Msk                (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_HCCHAR_EPTYP                    USB_OTG_HCCHAR_EPTYP_Msk       /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                  (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_HCCHAR_EPTYP_1                  (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
-                                      
-#define USB_OTG_HCCHAR_MC_Pos                   (20U)                          
-#define USB_OTG_HCCHAR_MC_Msk                   (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
-#define USB_OTG_HCCHAR_MC                       USB_OTG_HCCHAR_MC_Msk          /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                     (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
-#define USB_OTG_HCCHAR_MC_1                     (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+#define HPRT_PTCTL_Pos                   (13U)
+#define HPRT_PTCTL_Msk                   (0xFUL << HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define HPRT_PTCTL                       HPRT_PTCTL_Msk        /*!< Port test control          */
+#define HPRT_PTCTL_0                     (0x1UL << HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define HPRT_PTCTL_1                     (0x2UL << HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define HPRT_PTCTL_2                     (0x4UL << HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define HPRT_PTCTL_3                     (0x8UL << HPRT_PTCTL_Pos) /*!< 0x00010000 */
 
-#define USB_OTG_HCCHAR_DAD_Pos                  (22U)                          
-#define USB_OTG_HCCHAR_DAD_Msk                  (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
-#define USB_OTG_HCCHAR_DAD                      USB_OTG_HCCHAR_DAD_Msk         /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                    (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
-#define USB_OTG_HCCHAR_DAD_1                    (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
-#define USB_OTG_HCCHAR_DAD_2                    (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
-#define USB_OTG_HCCHAR_DAD_3                    (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
-#define USB_OTG_HCCHAR_DAD_4                    (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
-#define USB_OTG_HCCHAR_DAD_5                    (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
-#define USB_OTG_HCCHAR_DAD_6                    (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
-#define USB_OTG_HCCHAR_ODDFRM_Pos               (29U)                          
-#define USB_OTG_HCCHAR_ODDFRM_Msk               (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_HCCHAR_ODDFRM                   USB_OTG_HCCHAR_ODDFRM_Msk      /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS_Pos                (30U)                          
-#define USB_OTG_HCCHAR_CHDIS_Msk                (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_HCCHAR_CHDIS                    USB_OTG_HCCHAR_CHDIS_Msk       /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA_Pos                (31U)                          
-#define USB_OTG_HCCHAR_CHENA_Msk                (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCCHAR_CHENA                    USB_OTG_HCCHAR_CHENA_Msk       /*!< Channel enable */
+#define HPRT_PSPD_Pos                    (17U)
+#define HPRT_PSPD_Msk                    (0x3UL << HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define HPRT_PSPD                        HPRT_PSPD_Msk         /*!< Port speed                 */
+#define HPRT_PSPD_0                      (0x1UL << HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define HPRT_PSPD_1                      (0x2UL << HPRT_PSPD_Pos) /*!< 0x00040000 */
 
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+/********************  Bit definition for DOEPEACHMSK1 register  ********************/
+#define DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define DOEPEACHMSK1_XFRCM_Msk           (0x1UL << DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define DOEPEACHMSK1_XFRCM               DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
+#define DOEPEACHMSK1_EPDM_Pos            (1U)
+#define DOEPEACHMSK1_EPDM_Msk            (0x1UL << DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define DOEPEACHMSK1_EPDM                DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
+#define DOEPEACHMSK1_TOM_Pos             (3U)
+#define DOEPEACHMSK1_TOM_Msk             (0x1UL << DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define DOEPEACHMSK1_TOM                 DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
+#define DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define DOEPEACHMSK1_ITTXFEMSK           DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
+#define DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define DOEPEACHMSK1_INEPNMM             DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
+#define DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define DOEPEACHMSK1_INEPNEM             DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
+#define DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define DOEPEACHMSK1_TXFURM_Msk          (0x1UL << DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define DOEPEACHMSK1_TXFURM              DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
+#define DOEPEACHMSK1_BIM_Pos             (9U)
+#define DOEPEACHMSK1_BIM_Msk             (0x1UL << DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define DOEPEACHMSK1_BIM                 DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
+#define DOEPEACHMSK1_BERRM_Pos           (12U)
+#define DOEPEACHMSK1_BERRM_Msk           (0x1UL << DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define DOEPEACHMSK1_BERRM               DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
+#define DOEPEACHMSK1_NAKM_Pos            (13U)
+#define DOEPEACHMSK1_NAKM_Msk            (0x1UL << DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define DOEPEACHMSK1_NAKM                DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
+#define DOEPEACHMSK1_NYETM_Pos           (14U)
+#define DOEPEACHMSK1_NYETM_Msk           (0x1UL << DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define DOEPEACHMSK1_NYETM               DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
 
-#define USB_OTG_HCSPLT_PRTADDR_Pos              (0U)                           
-#define USB_OTG_HCSPLT_PRTADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
-#define USB_OTG_HCSPLT_PRTADDR                  USB_OTG_HCSPLT_PRTADDR_Msk     /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0                (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCSPLT_PRTADDR_1                (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCSPLT_PRTADDR_2                (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCSPLT_PRTADDR_3                (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCSPLT_PRTADDR_4                (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCSPLT_PRTADDR_5                (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCSPLT_PRTADDR_6                (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+/********************  Bit definition for HPTXFSIZ register  ********************/
+#define HPTXFSIZ_PTXSA_Pos               (0U)
+#define HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define HPTXFSIZ_PTXSA                   HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
+#define HPTXFSIZ_PTXFD_Pos               (16U)
+#define HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define HPTXFSIZ_PTXFD                   HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
 
-#define USB_OTG_HCSPLT_HUBADDR_Pos              (7U)                           
-#define USB_OTG_HCSPLT_HUBADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
-#define USB_OTG_HCSPLT_HUBADDR                  USB_OTG_HCSPLT_HUBADDR_Msk     /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0                (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCSPLT_HUBADDR_1                (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCSPLT_HUBADDR_2                (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCSPLT_HUBADDR_3                (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCSPLT_HUBADDR_4                (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
-#define USB_OTG_HCSPLT_HUBADDR_5                (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
-#define USB_OTG_HCSPLT_HUBADDR_6                (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+/********************  Bit definition for DIEPCTL register  ********************/
+#define DIEPCTL_MPSIZ_Pos                (0U)
+#define DIEPCTL_MPSIZ_Msk                (0x7FFUL << DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define DIEPCTL_MPSIZ                    DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
+#define DIEPCTL_USBAEP_Pos               (15U)
+#define DIEPCTL_USBAEP_Msk               (0x1UL << DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define DIEPCTL_USBAEP                   DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
+#define DIEPCTL_EONUM_DPID_Pos           (16U)
+#define DIEPCTL_EONUM_DPID_Msk           (0x1UL << DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define DIEPCTL_EONUM_DPID               DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
+#define DIEPCTL_NAKSTS_Pos               (17U)
+#define DIEPCTL_NAKSTS_Msk               (0x1UL << DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define DIEPCTL_NAKSTS                   DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
 
-#define USB_OTG_HCSPLT_XACTPOS_Pos              (14U)                          
-#define USB_OTG_HCSPLT_XACTPOS_Msk              (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
-#define USB_OTG_HCSPLT_XACTPOS                  USB_OTG_HCSPLT_XACTPOS_Msk     /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0                (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCSPLT_XACTPOS_1                (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCSPLT_COMPLSPLT_Pos            (16U)                          
-#define USB_OTG_HCSPLT_COMPLSPLT_Msk            (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
-#define USB_OTG_HCSPLT_COMPLSPLT                USB_OTG_HCSPLT_COMPLSPLT_Msk   /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN_Pos              (31U)                          
-#define USB_OTG_HCSPLT_SPLITEN_Msk              (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCSPLT_SPLITEN                  USB_OTG_HCSPLT_SPLITEN_Msk     /*!< Split enable */
+#define DIEPCTL_EPTYP_Pos                (18U)
+#define DIEPCTL_EPTYP_Msk                (0x3UL << DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define DIEPCTL_EPTYP                    DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
+#define DIEPCTL_EPTYP_0                  (0x1UL << DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define DIEPCTL_EPTYP_1                  (0x2UL << DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define DIEPCTL_STALL_Pos                (21U)
+#define DIEPCTL_STALL_Msk                (0x1UL << DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define DIEPCTL_STALL                    DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
 
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC_Pos                  (0U)                           
-#define USB_OTG_HCINT_XFRC_Msk                  (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCINT_XFRC                      USB_OTG_HCINT_XFRC_Msk         /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH_Pos                   (1U)                           
-#define USB_OTG_HCINT_CHH_Msk                   (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCINT_CHH                       USB_OTG_HCINT_CHH_Msk          /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR_Pos                (2U)                           
-#define USB_OTG_HCINT_AHBERR_Msk                (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCINT_AHBERR                    USB_OTG_HCINT_AHBERR_Msk       /*!< AHB error */
-#define USB_OTG_HCINT_STALL_Pos                 (3U)                           
-#define USB_OTG_HCINT_STALL_Msk                 (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCINT_STALL                     USB_OTG_HCINT_STALL_Msk        /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK_Pos                   (4U)                           
-#define USB_OTG_HCINT_NAK_Msk                   (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCINT_NAK                       USB_OTG_HCINT_NAK_Msk          /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK_Pos                   (5U)                           
-#define USB_OTG_HCINT_ACK_Msk                   (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCINT_ACK                       USB_OTG_HCINT_ACK_Msk          /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET_Pos                  (6U)                           
-#define USB_OTG_HCINT_NYET_Msk                  (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
-#define USB_OTG_HCINT_NYET                      USB_OTG_HCINT_NYET_Msk         /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR_Pos                 (7U)                           
-#define USB_OTG_HCINT_TXERR_Msk                 (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCINT_TXERR                     USB_OTG_HCINT_TXERR_Msk        /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR_Pos                 (8U)                           
-#define USB_OTG_HCINT_BBERR_Msk                 (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCINT_BBERR                     USB_OTG_HCINT_BBERR_Msk        /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR_Pos                 (9U)                           
-#define USB_OTG_HCINT_FRMOR_Msk                 (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCINT_FRMOR                     USB_OTG_HCINT_FRMOR_Msk        /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR_Pos                 (10U)                          
-#define USB_OTG_HCINT_DTERR_Msk                 (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCINT_DTERR                     USB_OTG_HCINT_DTERR_Msk        /*!< Data toggle error */
+#define DIEPCTL_TXFNUM_Pos               (22U)
+#define DIEPCTL_TXFNUM_Msk               (0xFUL << DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define DIEPCTL_TXFNUM                   DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
+#define DIEPCTL_TXFNUM_0                 (0x1UL << DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define DIEPCTL_TXFNUM_1                 (0x2UL << DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define DIEPCTL_TXFNUM_2                 (0x4UL << DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define DIEPCTL_TXFNUM_3                 (0x8UL << DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define DIEPCTL_CNAK_Pos                 (26U)
+#define DIEPCTL_CNAK_Msk                 (0x1UL << DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define DIEPCTL_CNAK                     DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
+#define DIEPCTL_SNAK_Pos                 (27U)
+#define DIEPCTL_SNAK_Msk                 (0x1UL << DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define DIEPCTL_SNAK                     DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define DIEPCTL_SD0PID_SEVNFRM           DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
+#define DIEPCTL_SODDFRM_Pos              (29U)
+#define DIEPCTL_SODDFRM_Msk              (0x1UL << DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define DIEPCTL_SODDFRM                  DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
+#define DIEPCTL_EPDIS_Pos                (30U)
+#define DIEPCTL_EPDIS_Msk                (0x1UL << DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define DIEPCTL_EPDIS                    DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
+#define DIEPCTL_EPENA_Pos                (31U)
+#define DIEPCTL_EPENA_Msk                (0x1UL << DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define DIEPCTL_EPENA                    DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
 
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC_Pos                (0U)                           
-#define USB_OTG_DIEPINT_XFRC_Msk                (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPINT_XFRC                    USB_OTG_DIEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD_Pos              (1U)                           
-#define USB_OTG_DIEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPINT_EPDISD                  USB_OTG_DIEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
-#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
-#define USB_OTG_DIEPINT_TOC_Pos                 (3U)                           
-#define USB_OTG_DIEPINT_TOC_Msk                 (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPINT_TOC                     USB_OTG_DIEPINT_TOC_Msk        /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE_Pos              (4U)                           
-#define USB_OTG_DIEPINT_ITTXFE_Msk              (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPINT_ITTXFE                  USB_OTG_DIEPINT_ITTXFE_Msk     /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
-#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
-#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
-#define USB_OTG_DIEPINT_INEPNE_Pos              (6U)                           
-#define USB_OTG_DIEPINT_INEPNE_Msk              (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPINT_INEPNE                  USB_OTG_DIEPINT_INEPNE_Msk     /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE_Pos                (7U)                           
-#define USB_OTG_DIEPINT_TXFE_Msk                (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
-#define USB_OTG_DIEPINT_TXFE                    USB_OTG_DIEPINT_TXFE_Msk       /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos          (8U)                           
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk          (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA_Pos                 (9U)                           
-#define USB_OTG_DIEPINT_BNA_Msk                 (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPINT_BNA                     USB_OTG_DIEPINT_BNA_Msk        /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS_Pos           (11U)                          
-#define USB_OTG_DIEPINT_PKTDRPSTS_Msk           (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_DIEPINT_PKTDRPSTS               USB_OTG_DIEPINT_PKTDRPSTS_Msk  /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR_Pos                (12U)                          
-#define USB_OTG_DIEPINT_BERR_Msk                (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
-#define USB_OTG_DIEPINT_BERR                    USB_OTG_DIEPINT_BERR_Msk       /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK_Pos                 (13U)                          
-#define USB_OTG_DIEPINT_NAK_Msk                 (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
-#define USB_OTG_DIEPINT_NAK                     USB_OTG_DIEPINT_NAK_Msk        /*!< NAK interrupt */
+/********************  Bit definition for HCCHAR register  ********************/
+#define HCCHAR_MPSIZ_Pos                 (0U)
+#define HCCHAR_MPSIZ_Msk                 (0x7FFUL << HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define HCCHAR_MPSIZ                     HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
 
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM_Pos              (0U)                           
-#define USB_OTG_HCINTMSK_XFRCM_Msk              (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCINTMSK_XFRCM                  USB_OTG_HCINTMSK_XFRCM_Msk     /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM_Pos               (1U)                           
-#define USB_OTG_HCINTMSK_CHHM_Msk               (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCINTMSK_CHHM                   USB_OTG_HCINTMSK_CHHM_Msk      /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR_Pos             (2U)                           
-#define USB_OTG_HCINTMSK_AHBERR_Msk             (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCINTMSK_AHBERR                 USB_OTG_HCINTMSK_AHBERR_Msk    /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM_Pos             (3U)                           
-#define USB_OTG_HCINTMSK_STALLM_Msk             (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCINTMSK_STALLM                 USB_OTG_HCINTMSK_STALLM_Msk    /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM_Pos               (4U)                           
-#define USB_OTG_HCINTMSK_NAKM_Msk               (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCINTMSK_NAKM                   USB_OTG_HCINTMSK_NAKM_Msk      /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM_Pos               (5U)                           
-#define USB_OTG_HCINTMSK_ACKM_Msk               (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCINTMSK_ACKM                   USB_OTG_HCINTMSK_ACKM_Msk      /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET_Pos               (6U)                           
-#define USB_OTG_HCINTMSK_NYET_Msk               (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
-#define USB_OTG_HCINTMSK_NYET                   USB_OTG_HCINTMSK_NYET_Msk      /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM_Pos             (7U)                           
-#define USB_OTG_HCINTMSK_TXERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCINTMSK_TXERRM                 USB_OTG_HCINTMSK_TXERRM_Msk    /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM_Pos             (8U)                           
-#define USB_OTG_HCINTMSK_BBERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCINTMSK_BBERRM                 USB_OTG_HCINTMSK_BBERRM_Msk    /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM_Pos             (9U)                           
-#define USB_OTG_HCINTMSK_FRMORM_Msk             (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCINTMSK_FRMORM                 USB_OTG_HCINTMSK_FRMORM_Msk    /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM_Pos             (10U)                          
-#define USB_OTG_HCINTMSK_DTERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCINTMSK_DTERRM                 USB_OTG_HCINTMSK_DTERRM_Msk    /*!< Data toggle error mask */
+#define HCCHAR_EPNUM_Pos                 (11U)
+#define HCCHAR_EPNUM_Msk                 (0xFUL << HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define HCCHAR_EPNUM                     HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define HCCHAR_EPNUM_0                   (0x1UL << HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define HCCHAR_EPNUM_1                   (0x2UL << HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define HCCHAR_EPNUM_2                   (0x4UL << HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define HCCHAR_EPNUM_3                   (0x8UL << HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define HCCHAR_EPDIR_Pos                 (15U)
+#define HCCHAR_EPDIR_Msk                 (0x1UL << HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define HCCHAR_EPDIR                     HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define HCCHAR_LSDEV_Pos                 (17U)
+#define HCCHAR_LSDEV_Msk                 (0x1UL << HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define HCCHAR_LSDEV                     HCCHAR_LSDEV_Msk      /*!< Low-speed device */
 
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+#define HCCHAR_EPTYP_Pos                 (18U)
+#define HCCHAR_EPTYP_Msk                 (0x3UL << HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define HCCHAR_EPTYP                     HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define HCCHAR_EPTYP_0                   (0x1UL << HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define HCCHAR_EPTYP_1                   (0x2UL << HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos             (0U)                           
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_DIEPTSIZ_XFRSIZ                 USB_OTG_DIEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT_Pos             (19U)                          
-#define USB_OTG_DIEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_DIEPTSIZ_PKTCNT                 USB_OTG_DIEPTSIZ_PKTCNT_Msk    /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT_Pos             (29U)                          
-#define USB_OTG_DIEPTSIZ_MULCNT_Msk             (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
-#define USB_OTG_DIEPTSIZ_MULCNT                 USB_OTG_DIEPTSIZ_MULCNT_Msk    /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ_Pos               (0U)                           
-#define USB_OTG_HCTSIZ_XFRSIZ_Msk               (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_HCTSIZ_XFRSIZ                   USB_OTG_HCTSIZ_XFRSIZ_Msk      /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT_Pos               (19U)                          
-#define USB_OTG_HCTSIZ_PKTCNT_Msk               (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_HCTSIZ_PKTCNT                   USB_OTG_HCTSIZ_PKTCNT_Msk      /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING_Pos               (31U)                          
-#define USB_OTG_HCTSIZ_DOPING_Msk               (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCTSIZ_DOPING                   USB_OTG_HCTSIZ_DOPING_Msk      /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID_Pos                 (29U)                          
-#define USB_OTG_HCTSIZ_DPID_Msk                 (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
-#define USB_OTG_HCTSIZ_DPID                     USB_OTG_HCTSIZ_DPID_Msk        /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
-#define USB_OTG_HCTSIZ_DPID_1                   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+#define HCCHAR_MC_Pos                    (20U)
+#define HCCHAR_MC_Msk                    (0x3UL << HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define HCCHAR_MC                        HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define HCCHAR_MC_0                      (0x1UL << HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define HCCHAR_MC_1                      (0x2UL << HCCHAR_MC_Pos) /*!< 0x00200000 */
 
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR_Pos             (0U)                           
-#define USB_OTG_DIEPDMA_DMAADDR_Msk             (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_DIEPDMA_DMAADDR                 USB_OTG_DIEPDMA_DMAADDR_Msk    /*!< DMA address */
+#define HCCHAR_DAD_Pos                   (22U)
+#define HCCHAR_DAD_Msk                   (0x7FUL << HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define HCCHAR_DAD                       HCCHAR_DAD_Msk        /*!< Device address */
+#define HCCHAR_DAD_0                     (0x01UL << HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define HCCHAR_DAD_1                     (0x02UL << HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define HCCHAR_DAD_2                     (0x04UL << HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define HCCHAR_DAD_3                     (0x08UL << HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define HCCHAR_DAD_4                     (0x10UL << HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define HCCHAR_DAD_5                     (0x20UL << HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define HCCHAR_DAD_6                     (0x40UL << HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define HCCHAR_ODDFRM_Pos                (29U)
+#define HCCHAR_ODDFRM_Msk                (0x1UL << HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define HCCHAR_ODDFRM                    HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define HCCHAR_CHDIS_Pos                 (30U)
+#define HCCHAR_CHDIS_Msk                 (0x1UL << HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define HCCHAR_CHDIS                     HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define HCCHAR_CHENA_Pos                 (31U)
+#define HCCHAR_CHENA_Msk                 (0x1UL << HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define HCCHAR_CHENA                     HCCHAR_CHENA_Msk      /*!< Channel enable */
 
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR_Pos               (0U)                           
-#define USB_OTG_HCDMA_DMAADDR_Msk               (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_HCDMA_DMAADDR                   USB_OTG_HCDMA_DMAADDR_Msk      /*!< DMA address */
+/********************  Bit definition for HCSPLT register  ********************/
 
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV_Pos           (0U)                           
-#define USB_OTG_DTXFSTS_INEPTFSAV_Msk           (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+#define HCSPLT_PRTADDR_Pos               (0U)
+#define HCSPLT_PRTADDR_Msk               (0x7FUL << HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define HCSPLT_PRTADDR                   HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define HCSPLT_PRTADDR_0                 (0x01UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define HCSPLT_PRTADDR_1                 (0x02UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define HCSPLT_PRTADDR_2                 (0x04UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define HCSPLT_PRTADDR_3                 (0x08UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define HCSPLT_PRTADDR_4                 (0x10UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define HCSPLT_PRTADDR_5                 (0x20UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define HCSPLT_PRTADDR_6                 (0x40UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
 
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA_Pos            (0U)                           
-#define USB_OTG_DIEPTXF_INEPTXSA_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DIEPTXF_INEPTXSA                USB_OTG_DIEPTXF_INEPTXSA_Msk   /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD_Pos            (16U)                          
-#define USB_OTG_DIEPTXF_INEPTXFD_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DIEPTXF_INEPTXFD                USB_OTG_DIEPTXF_INEPTXFD_Msk   /*!< IN endpoint TxFIFO depth */
+#define HCSPLT_HUBADDR_Pos               (7U)
+#define HCSPLT_HUBADDR_Msk               (0x7FUL << HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define HCSPLT_HUBADDR                   HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define HCSPLT_HUBADDR_0                 (0x01UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define HCSPLT_HUBADDR_1                 (0x02UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define HCSPLT_HUBADDR_2                 (0x04UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define HCSPLT_HUBADDR_3                 (0x08UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define HCSPLT_HUBADDR_4                 (0x10UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define HCSPLT_HUBADDR_5                 (0x20UL << HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define HCSPLT_HUBADDR_6                 (0x40UL << HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
 
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+#define HCSPLT_XACTPOS_Pos               (14U)
+#define HCSPLT_XACTPOS_Msk               (0x3UL << HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define HCSPLT_XACTPOS                   HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define HCSPLT_XACTPOS_0                 (0x1UL << HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define HCSPLT_XACTPOS_1                 (0x2UL << HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define HCSPLT_COMPLSPLT_Pos             (16U)
+#define HCSPLT_COMPLSPLT_Msk             (0x1UL << HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define HCSPLT_COMPLSPLT                 HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define HCSPLT_SPLITEN_Pos               (31U)
+#define HCSPLT_SPLITEN_Msk               (0x1UL << HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define HCSPLT_SPLITEN                   HCSPLT_SPLITEN_Msk    /*!< Split enable */
 
-#define USB_OTG_DOEPCTL_MPSIZ_Pos               (0U)                           
-#define USB_OTG_DOEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP_Pos              (15U)                          
-#define USB_OTG_DOEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define USB_OTG_DOEPCTL_USBAEP                  USB_OTG_DOEPCTL_USBAEP_Msk     /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS_Pos              (17U)                          
-#define USB_OTG_DOEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define USB_OTG_DOEPCTL_NAKSTS                  USB_OTG_DOEPCTL_NAKSTS_Msk     /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM          USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM_Pos             (29U)                          
-#define USB_OTG_DOEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_DOEPCTL_SODDFRM                 USB_OTG_DOEPCTL_SODDFRM_Msk    /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP_Pos               (18U)                          
-#define USB_OTG_DOEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_DOEPCTL_EPTYP                   USB_OTG_DOEPCTL_EPTYP_Msk      /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_DOEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DOEPCTL_SNPM_Pos                (20U)                          
-#define USB_OTG_DOEPCTL_SNPM_Msk                (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
-#define USB_OTG_DOEPCTL_SNPM                    USB_OTG_DOEPCTL_SNPM_Msk       /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL_Pos               (21U)                          
-#define USB_OTG_DOEPCTL_STALL_Msk               (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define USB_OTG_DOEPCTL_STALL                   USB_OTG_DOEPCTL_STALL_Msk      /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK_Pos                (26U)                          
-#define USB_OTG_DOEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define USB_OTG_DOEPCTL_CNAK                    USB_OTG_DOEPCTL_CNAK_Msk       /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK_Pos                (27U)                          
-#define USB_OTG_DOEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define USB_OTG_DOEPCTL_SNAK                    USB_OTG_DOEPCTL_SNAK_Msk       /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS_Pos               (30U)                          
-#define USB_OTG_DOEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_DOEPCTL_EPDIS                   USB_OTG_DOEPCTL_EPDIS_Msk      /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA_Pos               (31U)                          
-#define USB_OTG_DOEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_DOEPCTL_EPENA                   USB_OTG_DOEPCTL_EPENA_Msk      /*!< Endpoint enable */
+/********************  Bit definition for HCINT register  ********************/
+#define HCINT_XFRC_Pos                   (0U)
+#define HCINT_XFRC_Msk                   (0x1UL << HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define HCINT_XFRC                       HCINT_XFRC_Msk        /*!< Transfer completed */
+#define HCINT_CHH_Pos                    (1U)
+#define HCINT_CHH_Msk                    (0x1UL << HCINT_CHH_Pos) /*!< 0x00000002 */
+#define HCINT_CHH                        HCINT_CHH_Msk         /*!< Channel halted */
+#define HCINT_AHBERR_Pos                 (2U)
+#define HCINT_AHBERR_Msk                 (0x1UL << HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define HCINT_AHBERR                     HCINT_AHBERR_Msk      /*!< AHB error */
+#define HCINT_STALL_Pos                  (3U)
+#define HCINT_STALL_Msk                  (0x1UL << HCINT_STALL_Pos) /*!< 0x00000008 */
+#define HCINT_STALL                      HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define HCINT_NAK_Pos                    (4U)
+#define HCINT_NAK_Msk                    (0x1UL << HCINT_NAK_Pos) /*!< 0x00000010 */
+#define HCINT_NAK                        HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define HCINT_ACK_Pos                    (5U)
+#define HCINT_ACK_Msk                    (0x1UL << HCINT_ACK_Pos) /*!< 0x00000020 */
+#define HCINT_ACK                        HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define HCINT_NYET_Pos                   (6U)
+#define HCINT_NYET_Msk                   (0x1UL << HCINT_NYET_Pos) /*!< 0x00000040 */
+#define HCINT_NYET                       HCINT_NYET_Msk        /*!< Response received interrupt */
+#define HCINT_TXERR_Pos                  (7U)
+#define HCINT_TXERR_Msk                  (0x1UL << HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define HCINT_TXERR                      HCINT_TXERR_Msk       /*!< Transaction error */
+#define HCINT_BBERR_Pos                  (8U)
+#define HCINT_BBERR_Msk                  (0x1UL << HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define HCINT_BBERR                      HCINT_BBERR_Msk       /*!< Babble error */
+#define HCINT_FRMOR_Pos                  (9U)
+#define HCINT_FRMOR_Msk                  (0x1UL << HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define HCINT_FRMOR                      HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define HCINT_DTERR_Pos                  (10U)
+#define HCINT_DTERR_Msk                  (0x1UL << HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define HCINT_DTERR                      HCINT_DTERR_Msk       /*!< Data toggle error */
 
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC_Pos                (0U)                           
-#define USB_OTG_DOEPINT_XFRC_Msk                (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPINT_XFRC                    USB_OTG_DOEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD_Pos              (1U)                           
-#define USB_OTG_DOEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPINT_EPDISD                  USB_OTG_DOEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
-#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
-#define USB_OTG_DOEPINT_STUP_Pos                (3U)                           
-#define USB_OTG_DOEPINT_STUP_Msk                (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPINT_STUP                    USB_OTG_DOEPINT_STUP_Msk       /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS_Pos             (4U)                           
-#define USB_OTG_DOEPINT_OTEPDIS_Msk             (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPINT_OTEPDIS                 USB_OTG_DOEPINT_OTEPDIS_Msk    /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          
-#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP_Pos             (6U)                           
-#define USB_OTG_DOEPINT_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPINT_B2BSTUP                 USB_OTG_DOEPINT_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
-#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
-#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
-#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
-#define USB_OTG_DOEPINT_NYET_Pos                (14U)                          
-#define USB_OTG_DOEPINT_NYET_Msk                (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPINT_NYET                    USB_OTG_DOEPINT_NYET_Msk       /*!< NYET interrupt */
-#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
-#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
-#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+/********************  Bit definition for DIEPINT register  ********************/
+#define DIEPINT_XFRC_Pos                 (0U)
+#define DIEPINT_XFRC_Msk                 (0x1UL << DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define DIEPINT_XFRC                     DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define DIEPINT_EPDISD_Pos               (1U)
+#define DIEPINT_EPDISD_Msk               (0x1UL << DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define DIEPINT_EPDISD                   DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define DIEPINT_AHBERR_Pos               (2U)
+#define DIEPINT_AHBERR_Msk               (0x1UL << DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define DIEPINT_AHBERR                   DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define DIEPINT_TOC_Pos                  (3U)
+#define DIEPINT_TOC_Msk                  (0x1UL << DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define DIEPINT_TOC                      DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define DIEPINT_ITTXFE_Pos               (4U)
+#define DIEPINT_ITTXFE_Msk               (0x1UL << DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define DIEPINT_ITTXFE                   DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define DIEPINT_INEPNM_Pos               (5U)
+#define DIEPINT_INEPNM_Msk               (0x1UL << DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define DIEPINT_INEPNM                   DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define DIEPINT_INEPNE_Pos               (6U)
+#define DIEPINT_INEPNE_Msk               (0x1UL << DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define DIEPINT_INEPNE                   DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define DIEPINT_TXFE_Pos                 (7U)
+#define DIEPINT_TXFE_Msk                 (0x1UL << DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define DIEPINT_TXFE                     DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define DIEPINT_TXFIFOUDRN_Msk           (0x1UL << DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define DIEPINT_TXFIFOUDRN               DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define DIEPINT_BNA_Pos                  (9U)
+#define DIEPINT_BNA_Msk                  (0x1UL << DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define DIEPINT_BNA                      DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define DIEPINT_PKTDRPSTS_Pos            (11U)
+#define DIEPINT_PKTDRPSTS_Msk            (0x1UL << DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define DIEPINT_PKTDRPSTS                DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define DIEPINT_BERR_Pos                 (12U)
+#define DIEPINT_BERR_Msk                 (0x1UL << DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define DIEPINT_BERR                     DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define DIEPINT_NAK_Pos                  (13U)
+#define DIEPINT_NAK_Msk                  (0x1UL << DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define DIEPINT_NAK                      DIEPINT_NAK_Msk       /*!< NAK interrupt */
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos             (0U)                           
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_DOEPTSIZ_XFRSIZ                 USB_OTG_DOEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT_Pos             (19U)                          
-#define USB_OTG_DOEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_DOEPTSIZ_PKTCNT                 USB_OTG_DOEPTSIZ_PKTCNT_Msk    /*!< Packet count */
+/********************  Bit definition for HCINTMSK register  ********************/
+#define HCINTMSK_XFRCM_Pos               (0U)
+#define HCINTMSK_XFRCM_Msk               (0x1UL << HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define HCINTMSK_XFRCM                   HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define HCINTMSK_CHHM_Pos                (1U)
+#define HCINTMSK_CHHM_Msk                (0x1UL << HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define HCINTMSK_CHHM                    HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define HCINTMSK_AHBERR_Pos              (2U)
+#define HCINTMSK_AHBERR_Msk              (0x1UL << HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define HCINTMSK_AHBERR                  HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define HCINTMSK_STALLM_Pos              (3U)
+#define HCINTMSK_STALLM_Msk              (0x1UL << HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define HCINTMSK_STALLM                  HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define HCINTMSK_NAKM_Pos                (4U)
+#define HCINTMSK_NAKM_Msk                (0x1UL << HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define HCINTMSK_NAKM                    HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define HCINTMSK_ACKM_Pos                (5U)
+#define HCINTMSK_ACKM_Msk                (0x1UL << HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define HCINTMSK_ACKM                    HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define HCINTMSK_NYET_Pos                (6U)
+#define HCINTMSK_NYET_Msk                (0x1UL << HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define HCINTMSK_NYET                    HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define HCINTMSK_TXERRM_Pos              (7U)
+#define HCINTMSK_TXERRM_Msk              (0x1UL << HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define HCINTMSK_TXERRM                  HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define HCINTMSK_BBERRM_Pos              (8U)
+#define HCINTMSK_BBERRM_Msk              (0x1UL << HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define HCINTMSK_BBERRM                  HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define HCINTMSK_FRMORM_Pos              (9U)
+#define HCINTMSK_FRMORM_Msk              (0x1UL << HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define HCINTMSK_FRMORM                  HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define HCINTMSK_DTERRM_Pos              (10U)
+#define HCINTMSK_DTERRM_Msk              (0x1UL << HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define HCINTMSK_DTERRM                  HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT_Pos            (29U)                          
-#define USB_OTG_DOEPTSIZ_STUPCNT_Msk            (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
-#define USB_OTG_DOEPTSIZ_STUPCNT                USB_OTG_DOEPTSIZ_STUPCNT_Msk   /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0              (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1              (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+/********************  Bit definition for DIEPTSIZ register  ********************/
+
+#define DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define DIEPTSIZ_XFRSIZ                  DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define DIEPTSIZ_PKTCNT_Pos              (19U)
+#define DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define DIEPTSIZ_PKTCNT                  DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define DIEPTSIZ_MULCNT_Pos              (29U)
+#define DIEPTSIZ_MULCNT_Msk              (0x3UL << DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define DIEPTSIZ_MULCNT                  DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition for HCTSIZ register  ********************/
+#define HCTSIZ_XFRSIZ_Pos                (0U)
+#define HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define HCTSIZ_XFRSIZ                    HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define HCTSIZ_PKTCNT_Pos                (19U)
+#define HCTSIZ_PKTCNT_Msk                (0x3FFUL << HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define HCTSIZ_PKTCNT                    HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define HCTSIZ_DOPING_Pos                (31U)
+#define HCTSIZ_DOPING_Msk                (0x1UL << HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define HCTSIZ_DOPING                    HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define HCTSIZ_DPID_Pos                  (29U)
+#define HCTSIZ_DPID_Msk                  (0x3UL << HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define HCTSIZ_DPID                      HCTSIZ_DPID_Msk       /*!< Data PID */
+#define HCTSIZ_DPID_0                    (0x1UL << HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define HCTSIZ_DPID_1                    (0x2UL << HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for DIEPDMA register  ********************/
+#define DIEPDMA_DMAADDR_Pos              (0U)
+#define DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define DIEPDMA_DMAADDR                  DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for HCDMA register  ********************/
+#define HCDMA_DMAADDR_Pos                (0U)
+#define HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define HCDMA_DMAADDR                    HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for DTXFSTS register  ********************/
+#define DTXFSTS_INEPTFSAV_Pos            (0U)
+#define DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define DTXFSTS_INEPTFSAV                DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for DIEPTXF register  ********************/
+#define DIEPTXF_INEPTXSA_Pos             (0U)
+#define DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define DIEPTXF_INEPTXSA                 DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define DIEPTXF_INEPTXFD_Pos             (16U)
+#define DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define DIEPTXF_INEPTXFD                 DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for DOEPCTL register  ********************/
+#define DOEPCTL_MPSIZ_Pos                (0U)
+#define DOEPCTL_MPSIZ_Msk                (0x7FFUL << DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define DOEPCTL_MPSIZ                    DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define DOEPCTL_USBAEP_Pos               (15U)
+#define DOEPCTL_USBAEP_Msk               (0x1UL << DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define DOEPCTL_USBAEP                   DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define DOEPCTL_NAKSTS_Pos               (17U)
+#define DOEPCTL_NAKSTS_Msk               (0x1UL << DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define DOEPCTL_NAKSTS                   DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define DOEPCTL_SD0PID_SEVNFRM           DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define DOEPCTL_SODDFRM_Pos              (29U)
+#define DOEPCTL_SODDFRM_Msk              (0x1UL << DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define DOEPCTL_SODDFRM                  DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define DOEPCTL_EPTYP_Pos                (18U)
+#define DOEPCTL_EPTYP_Msk                (0x3UL << DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define DOEPCTL_EPTYP                    DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define DOEPCTL_EPTYP_0                  (0x1UL << DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define DOEPCTL_EPTYP_1                  (0x2UL << DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define DOEPCTL_SNPM_Pos                 (20U)
+#define DOEPCTL_SNPM_Msk                 (0x1UL << DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define DOEPCTL_SNPM                     DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define DOEPCTL_STALL_Pos                (21U)
+#define DOEPCTL_STALL_Msk                (0x1UL << DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define DOEPCTL_STALL                    DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define DOEPCTL_CNAK_Pos                 (26U)
+#define DOEPCTL_CNAK_Msk                 (0x1UL << DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define DOEPCTL_CNAK                     DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define DOEPCTL_SNAK_Pos                 (27U)
+#define DOEPCTL_SNAK_Msk                 (0x1UL << DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define DOEPCTL_SNAK                     DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define DOEPCTL_EPDIS_Pos                (30U)
+#define DOEPCTL_EPDIS_Msk                (0x1UL << DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define DOEPCTL_EPDIS                    DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define DOEPCTL_EPENA_Pos                (31U)
+#define DOEPCTL_EPENA_Msk                (0x1UL << DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define DOEPCTL_EPENA                    DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for DOEPINT register  ********************/
+#define DOEPINT_XFRC_Pos                 (0U)
+#define DOEPINT_XFRC_Msk                 (0x1UL << DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define DOEPINT_XFRC                     DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define DOEPINT_EPDISD_Pos               (1U)
+#define DOEPINT_EPDISD_Msk               (0x1UL << DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define DOEPINT_EPDISD                   DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define DOEPINT_AHBERR_Pos               (2U)
+#define DOEPINT_AHBERR_Msk               (0x1UL << DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define DOEPINT_AHBERR                   DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define DOEPINT_STUP_Pos                 (3U)
+#define DOEPINT_STUP_Msk                 (0x1UL << DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define DOEPINT_STUP                     DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define DOEPINT_OTEPDIS_Pos              (4U)
+#define DOEPINT_OTEPDIS_Msk              (0x1UL << DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define DOEPINT_OTEPDIS                  DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define DOEPINT_OTEPSPR_Pos              (5U)
+#define DOEPINT_OTEPSPR_Msk              (0x1UL << DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define DOEPINT_OTEPSPR                  DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
+#define DOEPINT_B2BSTUP_Pos              (6U)
+#define DOEPINT_B2BSTUP_Msk              (0x1UL << DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define DOEPINT_B2BSTUP                  DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define DOEPINT_OUTPKTERR_Pos            (8U)
+#define DOEPINT_OUTPKTERR_Msk            (0x1UL << DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define DOEPINT_OUTPKTERR                DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define DOEPINT_NAK_Pos                  (13U)
+#define DOEPINT_NAK_Msk                  (0x1UL << DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define DOEPINT_NAK                      DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define DOEPINT_NYET_Pos                 (14U)
+#define DOEPINT_NYET_Msk                 (0x1UL << DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define DOEPINT_NYET                     DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define DOEPINT_STPKTRX_Pos              (15U)
+#define DOEPINT_STPKTRX_Msk              (0x1UL << DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define DOEPINT_STPKTRX                  DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition for DOEPTSIZ register  ********************/
+#define DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define DOEPTSIZ_XFRSIZ                  DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define DOEPTSIZ_PKTCNT_Pos              (19U)
+#define DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define DOEPTSIZ_PKTCNT                  DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define DOEPTSIZ_STUPCNT_Pos             (29U)
+#define DOEPTSIZ_STUPCNT_Msk             (0x3UL << DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define DOEPTSIZ_STUPCNT                 DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK_Pos             (0U)                           
-#define USB_OTG_PCGCCTL_STOPCLK_Msk             (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
-#define USB_OTG_PCGCCTL_STOPCLK                 USB_OTG_PCGCCTL_STOPCLK_Msk    /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK_Pos             (1U)                           
-#define USB_OTG_PCGCCTL_GATECLK_Msk             (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
-#define USB_OTG_PCGCCTL_GATECLK                 USB_OTG_PCGCCTL_GATECLK_Msk    /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP_Pos             (4U)                           
-#define USB_OTG_PCGCCTL_PHYSUSP_Msk             (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 USB_OTG_PCGCCTL_PHYSUSP_Msk    /*!<Bit 1 */
+#define PCGCCTL_STOPCLK_Pos              (0U)
+#define PCGCCTL_STOPCLK_Msk              (0x1UL << PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define PCGCCTL_STOPCLK                  PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define PCGCCTL_GATECLK_Pos              (1U)
+#define PCGCCTL_GATECLK_Msk              (0x1UL << PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define PCGCCTL_GATECLK                  PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define PCGCCTL_PHYSUSP_Pos              (4U)
+#define PCGCCTL_PHYSUSP_Msk              (0x1UL << PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define PCGCCTL_PHYSUSP                  PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
 
-/* Legacy define */
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_CHNUM_Pos                       (0U)                           
-#define USB_OTG_CHNUM_Msk                       (0xFUL << USB_OTG_CHNUM_Pos)    /*!< 0x0000000F */
-#define USB_OTG_CHNUM                           USB_OTG_CHNUM_Msk              /*!< Channel number */
-#define USB_OTG_CHNUM_0                         (0x1UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000001 */
-#define USB_OTG_CHNUM_1                         (0x2UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000002 */
-#define USB_OTG_CHNUM_2                         (0x4UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000004 */
-#define USB_OTG_CHNUM_3                         (0x8UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000008 */
-#define USB_OTG_BCNT_Pos                        (4U)                           
-#define USB_OTG_BCNT_Msk                        (0x7FFUL << USB_OTG_BCNT_Pos)   /*!< 0x00007FF0 */
-#define USB_OTG_BCNT                            USB_OTG_BCNT_Msk               /*!< Byte count */
+/********************  Bit definition for USBPHYC_PLL1 register  ********************/
+#define HS_PHYC_PLL1_PLLEN_Pos                (0U)
+#define HS_PHYC_PLL1_PLLEN_Msk                (0x1UL << HS_PHYC_PLL1_PLLEN_Pos) /*!< 0x00000001 */
+#define HS_PHYC_PLL1_PLLEN                    HS_PHYC_PLL1_PLLEN_Msk     /*!< Enable PLL */
+#define HS_PHYC_PLL1_PLLSEL_Pos               (1U)
+#define HS_PHYC_PLL1_PLLSEL_Msk               (0x7UL << HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x0000000E */
+#define HS_PHYC_PLL1_PLLSEL                   HS_PHYC_PLL1_PLLSEL_Msk    /*!< Controls PHY frequency operation selection */
+#define HS_PHYC_PLL1_PLLSEL_1                 (0x1UL << HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000002 */
+#define HS_PHYC_PLL1_PLLSEL_2                 (0x2UL << HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000004 */
+#define HS_PHYC_PLL1_PLLSEL_3                 (0x4UL << HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000008 */
 
-#define USB_OTG_DPID_Pos                        (15U)                          
-#define USB_OTG_DPID_Msk                        (0x3UL << USB_OTG_DPID_Pos)     /*!< 0x00018000 */
-#define USB_OTG_DPID                            USB_OTG_DPID_Msk               /*!< Data PID */
-#define USB_OTG_DPID_0                          (0x1UL << USB_OTG_DPID_Pos)     /*!< 0x00008000 */
-#define USB_OTG_DPID_1                          (0x2UL << USB_OTG_DPID_Pos)     /*!< 0x00010000 */
+#define HS_PHYC_PLL1_PLLSEL_12MHZ             0x00000000U                                                       /*!< PHY PLL1 input clock frequency 12 MHz   */
+#define HS_PHYC_PLL1_PLLSEL_12_5MHZ           HS_PHYC_PLL1_PLLSEL_1                                         /*!< PHY PLL1 input clock frequency 12.5 MHz */
+#define HS_PHYC_PLL1_PLLSEL_16MHZ             (uint32_t)(HS_PHYC_PLL1_PLLSEL_1 | HS_PHYC_PLL1_PLLSEL_2) /*!< PHY PLL1 input clock frequency 16 MHz   */
+#define HS_PHYC_PLL1_PLLSEL_24MHZ             HS_PHYC_PLL1_PLLSEL_3                                         /*!< PHY PLL1 input clock frequency 24 MHz   */
+#define HS_PHYC_PLL1_PLLSEL_25MHZ             (uint32_t)(HS_PHYC_PLL1_PLLSEL_2 | HS_PHYC_PLL1_PLLSEL_3) /*!< PHY PLL1 input clock frequency 25 MHz   */
 
-#define USB_OTG_PKTSTS_Pos                      (17U)                          
-#define USB_OTG_PKTSTS_Msk                      (0xFUL << USB_OTG_PKTSTS_Pos)   /*!< 0x001E0000 */
-#define USB_OTG_PKTSTS                          USB_OTG_PKTSTS_Msk             /*!< Packet status */
-#define USB_OTG_PKTSTS_0                        (0x1UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00020000 */
-#define USB_OTG_PKTSTS_1                        (0x2UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00040000 */
-#define USB_OTG_PKTSTS_2                        (0x4UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00080000 */
-#define USB_OTG_PKTSTS_3                        (0x8UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00100000 */
+/********************  Bit definition for USBPHYC_LDO register  ********************/
+#define HS_PHYC_LDO_USED_Pos                 (0U)
+#define HS_PHYC_LDO_USED_Msk                 (0x1UL << HS_PHYC_LDO_USED_Pos) /*!< 0x00000001 */
+#define HS_PHYC_LDO_USED                     HS_PHYC_LDO_USED_Msk      /*!< Monitors the usage status of the PHY's LDO   */
+#define HS_PHYC_LDO_STATUS_Pos               (1U)
+#define HS_PHYC_LDO_STATUS_Msk               (0x1UL << HS_PHYC_LDO_STATUS_Pos) /*!< 0x00000002 */
+#define HS_PHYC_LDO_STATUS                   HS_PHYC_LDO_STATUS_Msk    /*!< Monitors the status of the PHY's LDO.        */
+#define HS_PHYC_LDO_DISABLE_Pos              (2U)
+#define HS_PHYC_LDO_DISABLE_Msk              (0x1UL << HS_PHYC_LDO_DISABLE_Pos) /*!< 0x00000004 */
+#define HS_PHYC_LDO_DISABLE                  HS_PHYC_LDO_DISABLE_Msk    /*!< Controls disable of the High Speed PHY's LDO */
 
-#define USB_OTG_EPNUM_Pos                       (0U)                           
-#define USB_OTG_EPNUM_Msk                       (0xFUL << USB_OTG_EPNUM_Pos)    /*!< 0x0000000F */
-#define USB_OTG_EPNUM                           USB_OTG_EPNUM_Msk              /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                         (0x1UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000001 */
-#define USB_OTG_EPNUM_1                         (0x2UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000002 */
-#define USB_OTG_EPNUM_2                         (0x4UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000004 */
-#define USB_OTG_EPNUM_3                         (0x8UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000008 */
-
-#define USB_OTG_FRMNUM_Pos                      (21U)                          
-#define USB_OTG_FRMNUM_Msk                      (0xFUL << USB_OTG_FRMNUM_Pos)   /*!< 0x01E00000 */
-#define USB_OTG_FRMNUM                          USB_OTG_FRMNUM_Msk             /*!< Frame number */
-#define USB_OTG_FRMNUM_0                        (0x1UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00200000 */
-#define USB_OTG_FRMNUM_1                        (0x2UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00400000 */
-#define USB_OTG_FRMNUM_2                        (0x4UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00800000 */
-#define USB_OTG_FRMNUM_3                        (0x8UL << USB_OTG_FRMNUM_Pos)   /*!< 0x01000000 */
-
-#endif
+#define HS_PHYC_LDO_ENABLE_Pos               HS_PHYC_LDO_DISABLE_Pos
+#define HS_PHYC_LDO_ENABLE_Msk               HS_PHYC_LDO_DISABLE_Msk
+#define HS_PHYC_LDO_ENABLE                   HS_PHYC_LDO_DISABLE
 
 #ifdef __cplusplus
  }

From 0e7c103e98b4795d0d2a733421e64a4362f048c9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 00:11:17 +0700
Subject: [PATCH 0589/2085] minor rename

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 124 +++++++++++++-------------
 1 file changed, 62 insertions(+), 62 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 5811afa5a..0be587cb2 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -83,7 +83,7 @@ xfer_ctl_t xfer_status[EP_MAX][2];
 // EP0 transfers are limited to 1 packet - larger sizes has to be split
 static uint16_t ep0_pending[2];                   // Index determines direction as tusb_dir_t type
 
-// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ
+// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from core->GRXFSIZ
 static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
 static bool _out_ep_closed;                       // Flag to check if RX FIFO size needs an update (reduce its size)
 
@@ -97,7 +97,7 @@ static void update_grxfsiz(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = GLOBAL_BASE(rhport);
 
   // Determine largest EP size for RX FIFO
   uint16_t max_epsize = 0;
@@ -107,7 +107,7 @@ static void update_grxfsiz(uint8_t rhport)
   }
 
   // Update size of RX FIFO
-  usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize);
+  core->GRXFSIZ = calc_rx_ff_size(max_epsize);
 }
 
 // Setup the control endpoint 0.
@@ -115,7 +115,7 @@ static void bus_reset(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = GLOBAL_BASE(rhport);
   dwc2_device_t * dev = DEVICE_BASE(rhport);
   dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
   dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
@@ -186,12 +186,12 @@ static void bus_reset(uint8_t rhport)
   //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
   //   overwrite this.
 
-  usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
+  core->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
 
   _allocated_fifo_words_tx = 16;
 
   // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+  core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
   in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
@@ -199,19 +199,19 @@ static void bus_reset(uint8_t rhport)
 
   out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos);
 
-  usb_otg->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT;
+  core->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
 
 // Set turn-around timeout according to link speed
 extern uint32_t SystemCoreClock;
-static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed)
+static void set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
 {
-  usb_otg->GUSBCFG &= ~GUSBCFG_TRDT;
+  core->GUSBCFG &= ~GUSBCFG_TRDT;
 
   if ( speed == TUSB_SPEED_HIGH )
   {
     // Use fixed 0x09 for Highspeed
-    usb_otg->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
+    core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
   }
   else
   {
@@ -240,7 +240,7 @@ static void set_turnaround(dwc2_core_t * usb_otg, tusb_speed_t speed)
       turnaround = 0xFU;
 
     // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    usb_otg->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
+    core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
   }
 }
 
@@ -370,7 +370,7 @@ void dcd_init (uint8_t rhport)
 {
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
-  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = GLOBAL_BASE(rhport);
 
   // No HNP/SRP (no OTG support), program timeout later.
   if ( rhport == 1 )
@@ -378,23 +378,23 @@ void dcd_init (uint8_t rhport)
     // On selected MCUs HS port1 can be used with external PHY via ULPI interface
 #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
     // deactivate internal PHY
-    usb_otg->GCCFG &= ~GCCFG_PWRDWN;
+    core->GCCFG &= ~GCCFG_PWRDWN;
 
     // Init The UTMI Interface
-    usb_otg->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
+    core->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
 
     // Select default internal VBUS Indicator and Drive for ULPI
-    usb_otg->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
+    core->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
 #else
-    usb_otg->GUSBCFG |= GUSBCFG_PHYSEL;
+    core->GUSBCFG |= GUSBCFG_PHYSEL;
 #endif
 
 #if defined(USB_HS_PHYC)
     // Highspeed with embedded UTMI PHYC
 
     // Select UTMI Interface
-    usb_otg->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL;
-    usb_otg->GCCFG |= GCCFG_PHYHSEN;
+    core->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL;
+    core->GCCFG |= GCCFG_PHYHSEN;
 
     // Enables control of a High Speed USB PHY
     USB_HS_PHYCInit();
@@ -402,25 +402,25 @@ void dcd_init (uint8_t rhport)
   } else
   {
     // Enable internal PHY
-    usb_otg->GUSBCFG |= GUSBCFG_PHYSEL;
+    core->GUSBCFG |= GUSBCFG_PHYSEL;
   }
 
   // Reset core after selecting PHYst
   // Wait AHB IDLE, reset then wait until it is cleared
-  while ((usb_otg->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {}
-  usb_otg->GRSTCTL |= GRSTCTL_CSRST;
-  while ((usb_otg->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
+  while ((core->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {}
+  core->GRSTCTL |= GRSTCTL_CSRST;
+  while ((core->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
 
   // Restart PHY clock
   *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0;
 
   // Clear all interrupts
-  usb_otg->GINTSTS |= usb_otg->GINTSTS;
+  core->GINTSTS |= core->GINTSTS;
 
   // Required as part of core initialization.
   // TODO: How should mode mismatch be handled? It will cause
   // the core to stop working/require reset.
-  usb_otg->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM;
+  core->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM;
 
   dwc2_device_t * dev = DEVICE_BASE(rhport);
 
@@ -431,14 +431,14 @@ void dcd_init (uint8_t rhport)
   set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
 
   // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) usb_otg->GCCFG |= GCCFG_PWRDWN;
+  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->GCCFG |= GCCFG_PWRDWN;
 
-  usb_otg->GINTMSK |= GINTMSK_USBRST   | GINTMSK_ENUMDNEM |
-      GINTMSK_USBSUSPM | GINTMSK_WUIM     |
-      GINTMSK_RXFLVLM  | (USE_SOF ? GINTMSK_SOFM : 0);
+  core->GINTMSK |= GINTMSK_USBRST   | GINTMSK_ENUMDNEM |
+                      GINTMSK_USBSUSPM | GINTMSK_WUIM     |
+                      GINTMSK_RXFLVLM  | (USE_SOF ? GINTMSK_SOFM : 0);
 
   // Enable global interrupt
-  usb_otg->GAHBCFG |= GAHBCFG_GINT;
+  core->GAHBCFG |= GAHBCFG_GINT;
 
   dcd_connect(rhport);
 }
@@ -478,15 +478,15 @@ void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = GLOBAL_BASE(rhport);
   dwc2_device_t * dev = DEVICE_BASE(rhport);
 
   // set remote wakeup
   dev->DCTL |= DCTL_RWUSIG;
 
   // enable SOF to detect bus resume
-  usb_otg->GINTSTS = GINTSTS_SOF;
-  usb_otg->GINTMSK |= GINTMSK_SOFM;
+  core->GINTSTS = GINTSTS_SOF;
+  core->GINTMSK |= GINTMSK_SOFM;
 
   // Per specs: remote wakeup signal bit must be clear within 1-15ms
   remote_wakeup_delay();
@@ -517,7 +517,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
   (void) rhport;
 
-  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = GLOBAL_BASE(rhport);
   dwc2_device_t * dev = DEVICE_BASE(rhport);
   dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
   dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
@@ -539,12 +539,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     uint16_t const sz = calc_rx_ff_size(4*fifo_size);
 
     // If size_rx needs to be extended check if possible and if so enlarge it
-    if (usb_otg->GRXFSIZ < sz)
+    if (core->GRXFSIZ < sz)
     {
       TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
 
       // Enlarge RX FIFO
-      usb_otg->GRXFSIZ = sz;
+      core->GRXFSIZ = sz;
     }
 
     out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos)        |
@@ -578,7 +578,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
 
     // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4);
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= EP_FIFO_SIZE/4);
 
     _allocated_fifo_words_tx += fifo_size;
 
@@ -586,7 +586,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 
     // DIEPTXF starts at FIFO #1.
     // Both TXFD and TXSA are in unit of 32-bit words.
-    usb_otg->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+    core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
     in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) |
         (epnum << DIEPCTL_TXFNUM_Pos) |
@@ -605,7 +605,7 @@ void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
 
-//  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+//  dwc2_core_t * core = GLOBAL_BASE(rhport);
   dwc2_device_t * dev = DEVICE_BASE(rhport);
   dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
   dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
@@ -693,7 +693,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
 {
   (void) rhport;
 
-  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = GLOBAL_BASE(rhport);
   dwc2_device_t * dev = DEVICE_BASE(rhport);
   dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
   dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
@@ -717,9 +717,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
-    usb_otg->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos);
-    usb_otg->GRSTCTL |= GRSTCTL_TXFFLSH;
-    while((usb_otg->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0);
+    core->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos);
+    core->GRSTCTL |= GRSTCTL_TXFFLSH;
+    while((core->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0);
   } else {
     // Only disable currently enabled non-control endpoint
     if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) ){
@@ -730,7 +730,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
       // anyway, and it can't be cleared by user code. If this while loop never
       // finishes, we have bigger problems than just the stack.
       dev->DCTL |= DCTL_SGONAK;
-      while((usb_otg->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0);
+      while((core->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0);
 
       // Ditto here- disable the endpoint.
       out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
@@ -748,7 +748,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
  */
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
-  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = GLOBAL_BASE(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
@@ -760,8 +760,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 
   if (dir == TUSB_DIR_IN)
   {
-    uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
-    uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
+    uint16_t const fifo_size = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
+    uint16_t const fifo_start = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
     // For now only the last opened endpoint can be closed without fuss.
     TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
     _allocated_fifo_words_tx -= fifo_size;
@@ -861,11 +861,11 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
 }
 
 static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
-  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = GLOBAL_BASE(rhport);
   usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
 
   // Pop control word off FIFO
-  uint32_t ctl_word = usb_otg->GRXSTSP;
+  uint32_t ctl_word = core->GRXSTSP;
   uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
   uint8_t epnum = (ctl_word &  GRXSTSP_EPNUM_Msk) >>  GRXSTSP_EPNUM_Pos;
   uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
@@ -1025,17 +1025,17 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
 
 void dcd_int_handler(uint8_t rhport)
 {
-  dwc2_core_t * usb_otg = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = GLOBAL_BASE(rhport);
   dwc2_device_t * dev = DEVICE_BASE(rhport);
   dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
   dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
 
-  uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
+  uint32_t const int_status = core->GINTSTS & core->GINTMSK;
 
   if(int_status & GINTSTS_USBRST)
   {
     // USBRST is start of reset.
-    usb_otg->GINTSTS = GINTSTS_USBRST;
+    core->GINTSTS = GINTSTS_USBRST;
     bus_reset(rhport);
   }
 
@@ -1043,23 +1043,23 @@ void dcd_int_handler(uint8_t rhport)
   {
     // ENUMDNE is the end of reset where speed of the link is detected
 
-    usb_otg->GINTSTS = GINTSTS_ENUMDNE;
+    core->GINTSTS = GINTSTS_ENUMDNE;
 
     tusb_speed_t const speed = get_speed(rhport);
 
-    set_turnaround(usb_otg, speed);
+    set_turnaround(core, speed);
     dcd_event_bus_reset(rhport, speed, true);
   }
 
   if(int_status & GINTSTS_USBSUSP)
   {
-    usb_otg->GINTSTS = GINTSTS_USBSUSP;
+    core->GINTSTS = GINTSTS_USBSUSP;
     dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
   }
 
   if(int_status & GINTSTS_WKUINT)
   {
-    usb_otg->GINTSTS = GINTSTS_WKUINT;
+    core->GINTSTS = GINTSTS_WKUINT;
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
   }
 
@@ -1069,22 +1069,22 @@ void dcd_int_handler(uint8_t rhport)
   if(int_status & GINTSTS_OTGINT)
   {
     // OTG INT bit is read-only
-    uint32_t const otg_int = usb_otg->GOTGINT;
+    uint32_t const otg_int = core->GOTGINT;
 
     if (otg_int & GOTGINT_SEDET)
     {
       dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
     }
 
-    usb_otg->GOTGINT = otg_int;
+    core->GOTGINT = otg_int;
   }
 
   if(int_status & GINTSTS_SOF)
   {
-    usb_otg->GINTSTS = GINTSTS_SOF;
+    core->GINTSTS = GINTSTS_SOF;
 
     // Disable SOF interrupt since currently only used for remote wakeup detection
-    usb_otg->GINTMSK &= ~GINTMSK_SOFM;
+    core->GINTMSK &= ~GINTMSK_SOFM;
 
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
@@ -1095,13 +1095,13 @@ void dcd_int_handler(uint8_t rhport)
     // RXFLVL bit is read-only
 
     // Mask out RXFLVL while reading data from FIFO
-    usb_otg->GINTMSK &= ~GINTMSK_RXFLVLM;
+    core->GINTMSK &= ~GINTMSK_RXFLVLM;
 
     // Loop until all available packets were handled
     do
     {
       handle_rxflvl_ints(rhport, out_ep);
-    } while(usb_otg->GINTSTS & GINTSTS_RXFLVL);
+    } while(core->GINTSTS & GINTSTS_RXFLVL);
 
     // Manage RX FIFO size
     if (_out_ep_closed)
@@ -1112,7 +1112,7 @@ void dcd_int_handler(uint8_t rhport)
       _out_ep_closed = false;
     }
 
-    usb_otg->GINTMSK |= GINTMSK_RXFLVLM;
+    core->GINTMSK |= GINTMSK_RXFLVLM;
   }
 
   // OUT endpoint interrupt handling.

From 4ab931a36167f579f556bd3fed4946cf78865646 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 00:16:11 +0700
Subject: [PATCH 0590/2085] more clean up

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 102 +++++++++++++-------------
 1 file changed, 49 insertions(+), 53 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 0be587cb2..aae6e7004 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -44,18 +44,14 @@
 
 #include "device/dcd.h"
 
-// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
-// We disable SOF for now until needed later on
-#define USE_SOF     0
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#define GLOBAL_BASE(_port)     ((dwc2_core_t*) DWC2_REG_BASE)
-#define DEVICE_BASE(_port)     ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE))
-#define IN_EP_BASE(_port)      ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
-#define OUT_EP_BASE(_port)     ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
+#define CORE_REG(_port)     ((dwc2_core_t*) DWC2_REG_BASE)
+#define DEVICE_REG(_port)     ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE))
+#define EPIN_REG(_port)      ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
+#define EPOUT_REG(_port)     ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
 #define FIFO_BASE(_port, _x)   ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
 
 enum
@@ -97,7 +93,7 @@ static void update_grxfsiz(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_core_t * core = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = CORE_REG(rhport);
 
   // Determine largest EP size for RX FIFO
   uint16_t max_epsize = 0;
@@ -115,10 +111,10 @@ static void bus_reset(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_core_t * core = GLOBAL_BASE(rhport);
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
-  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
-  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+  dwc2_core_t   * core   = CORE_REG(rhport);
+  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
+  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   tu_memclr(xfer_status, sizeof(xfer_status));
   _out_ep_closed = false;
@@ -133,8 +129,8 @@ static void bus_reset(uint8_t rhport)
 
   // 2. Un-mask interrupt bits
   dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
-  dev->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM;
-  dev->DIEPMSK = DIEPMSK_TOM | DIEPMSK_XFRCM;
+  dev->DOEPMSK  = DOEPMSK_STUPM | DOEPMSK_XFRCM;
+  dev->DIEPMSK  = DIEPMSK_TOM | DIEPMSK_XFRCM;
 
   // "USB Data FIFOs" section in reference manual
   // Peripheral FIFO architecture
@@ -247,7 +243,7 @@ static void set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
 static tusb_speed_t get_speed(uint8_t rhport)
 {
   (void) rhport;
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_REG(rhport);
   uint32_t const enum_spd = (dev->DSTS & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos;
   return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
 }
@@ -265,7 +261,7 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
     bitvalue = DCD_FULL_SPEED;
   }
 
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_REG(rhport);
 
   // Clear and set speed bits
   dev->DCFG &= ~(3 << DCFG_DSPD_Pos);
@@ -317,9 +313,9 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 {
   (void) rhport;
 
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
-  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
-  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
+  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   // EP0 is limited to one packet each xfer
   // We use multiple transaction of xfer->max_size length to get a whole transfer done
@@ -336,6 +332,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
         ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
 
     in_ep[epnum].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+
     // For ISO endpoint set correct odd/even bit for next frame.
     if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
     {
@@ -370,7 +367,7 @@ void dcd_init (uint8_t rhport)
 {
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
-  dwc2_core_t * core = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = CORE_REG(rhport);
 
   // No HNP/SRP (no OTG support), program timeout later.
   if ( rhport == 1 )
@@ -422,7 +419,7 @@ void dcd_init (uint8_t rhport)
   // the core to stop working/require reset.
   core->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM;
 
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_REG(rhport);
 
   // If USB host misbehaves during status portion of control xfer
   // (non zero-length packet), send STALL back and discard.
@@ -433,9 +430,8 @@ void dcd_init (uint8_t rhport)
   // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
   if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->GCCFG |= GCCFG_PWRDWN;
 
-  core->GINTMSK |= GINTMSK_USBRST   | GINTMSK_ENUMDNEM |
-                      GINTMSK_USBSUSPM | GINTMSK_WUIM     |
-                      GINTMSK_RXFLVLM  | (USE_SOF ? GINTMSK_SOFM : 0);
+  core->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
+                   GINTMSK_WUIM   | GINTMSK_RXFLVLM;
 
   // Enable global interrupt
   core->GAHBCFG |= GAHBCFG_GINT;
@@ -457,7 +453,7 @@ void dcd_int_disable (uint8_t rhport)
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_REG(rhport);
   dev->DCFG = (dev->DCFG & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
 
   // Response with status after changing device address
@@ -478,8 +474,8 @@ void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_core_t * core = GLOBAL_BASE(rhport);
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_core_t   * core = CORE_REG(rhport);
+  dwc2_device_t * dev  = DEVICE_REG(rhport);
 
   // set remote wakeup
   dev->DCTL |= DCTL_RWUSIG;
@@ -497,14 +493,14 @@ void dcd_remote_wakeup(uint8_t rhport)
 void dcd_connect(uint8_t rhport)
 {
   (void) rhport;
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_REG(rhport);
   dev->DCTL &= ~DCTL_SDIS;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
   (void) rhport;
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
+  dwc2_device_t * dev = DEVICE_REG(rhport);
   dev->DCTL |= DCTL_SDIS;
 }
 
@@ -517,10 +513,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
   (void) rhport;
 
-  dwc2_core_t * core = GLOBAL_BASE(rhport);
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
-  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
-  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+  dwc2_core_t   * core   = CORE_REG(rhport);
+  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
+  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
@@ -605,10 +601,10 @@ void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
 
-//  dwc2_core_t * core = GLOBAL_BASE(rhport);
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
-  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
-  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+//  dwc2_core_t * core = CORE_REG(rhport);
+  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
+  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   // Disable non-control interrupt
   dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
@@ -693,10 +689,10 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
 {
   (void) rhport;
 
-  dwc2_core_t * core = GLOBAL_BASE(rhport);
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
-  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
-  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+  dwc2_core_t   * core   = CORE_REG(rhport);
+  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
+  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
@@ -748,7 +744,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
  */
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
-  dwc2_core_t * core = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = CORE_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
@@ -781,8 +777,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
 
-  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
-  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+  dwc2_epout_t * out_ep = EPOUT_REG(rhport);
+  dwc2_epin_t  * in_ep  = EPIN_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
@@ -861,14 +857,14 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
 }
 
 static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
-  dwc2_core_t * core = GLOBAL_BASE(rhport);
+  dwc2_core_t * core = CORE_REG(rhport);
   usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
 
   // Pop control word off FIFO
   uint32_t ctl_word = core->GRXSTSP;
-  uint8_t pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
-  uint8_t epnum = (ctl_word &  GRXSTSP_EPNUM_Msk) >>  GRXSTSP_EPNUM_Pos;
-  uint16_t bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
+  uint8_t pktsts    = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
+  uint8_t epnum     = (ctl_word & GRXSTSP_EPNUM_Msk) >>  GRXSTSP_EPNUM_Pos;
+  uint16_t bcnt     = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
 
   switch(pktsts) {
     case 0x01: // Global OUT NAK (Interrupt)
@@ -1025,10 +1021,10 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
 
 void dcd_int_handler(uint8_t rhport)
 {
-  dwc2_core_t * core = GLOBAL_BASE(rhport);
-  dwc2_device_t * dev = DEVICE_BASE(rhport);
-  dwc2_epout_t * out_ep = OUT_EP_BASE(rhport);
-  dwc2_epin_t * in_ep = IN_EP_BASE(rhport);
+  dwc2_core_t   * core   = CORE_REG(rhport);
+  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
+  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   uint32_t const int_status = core->GINTSTS & core->GINTMSK;
 

From 61c80840c30db790560076fef9808cccc3fdf361 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 00:39:37 +0700
Subject: [PATCH 0591/2085] update dwc int enable/disable

---
 src/portable/synopsys/dwc2/dcd_dwc2.c   | 17 +++++++----------
 src/portable/synopsys/dwc2/dwc2_gd32.h  | 22 +++++++++++++++++-----
 src/portable/synopsys/dwc2/dwc2_stm32.h | 14 ++++++++++++++
 3 files changed, 38 insertions(+), 15 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index aae6e7004..367fc7b56 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -32,6 +32,7 @@
 
 #if TUSB_OPT_DEVICE_ENABLED && (defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(GD32VF103))
 
+#include "device/dcd.h"
 #include "dwc2_type.h"
 
 #if defined(DCD_ATTR_DWC2_STM32)
@@ -42,17 +43,15 @@
   #error "Unsupported MCUs"
 #endif
 
-#include "device/dcd.h"
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#define CORE_REG(_port)     ((dwc2_core_t*) DWC2_REG_BASE)
+#define CORE_REG(_port)       ((dwc2_core_t*) DWC2_REG_BASE)
 #define DEVICE_REG(_port)     ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE))
-#define EPIN_REG(_port)      ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
-#define EPOUT_REG(_port)     ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
-#define FIFO_BASE(_port, _x)   ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
+#define EPIN_REG(_port)       ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
+#define EPOUT_REG(_port)      ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
+#define FIFO_BASE(_port, _x)  ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
 
 enum
 {
@@ -441,14 +440,12 @@ void dcd_init (uint8_t rhport)
 
 void dcd_int_enable (uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_EnableIRQ(RHPORT_IRQn);
+  dcd_dwc2_int_enable(rhport);
 }
 
 void dcd_int_disable (uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_DisableIRQ(RHPORT_IRQn);
+  dcd_dwc2_int_disable(rhport);
 }
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index 3ace4d484..8fe390fd8 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -32,26 +32,38 @@
 #define __NOP()   __asm volatile ("nop")
 
 // These numbers are the same for the whole GD32VF103 family.
-#define RHPORT_IRQn     86
+#define DWC2_REG_BASE   0x50000000UL
 #define EP_MAX          4
 #define EP_FIFO_SIZE    1280
-#define DWC2_REG_BASE   0x50000000UL
+#define RHPORT_IRQn     86
 
 // The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
 // Interrupt Controller by Nuclei. It is nearly API compatible to the
 // NVIC used by ARM MCUs.
 #define ECLIC_INTERRUPT_ENABLE_BASE 0xD2001001UL
 
-#define NVIC_EnableIRQ __eclic_enable_interrupt
-#define NVIC_DisableIRQ __eclic_disable_interrupt
-
+TU_ATTR_ALWAYS_INLINE
 static inline void __eclic_enable_interrupt (uint32_t irq) {
   *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1;
 }
 
+TU_ATTR_ALWAYS_INLINE
 static inline void __eclic_disable_interrupt (uint32_t irq){
   *(volatile uint8_t*)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0;
 }
 
+TU_ATTR_ALWAYS_INLINE
+static inline void dcd_dwc2_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  __eclic_enable_interrupt(RHPORT_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dcd_dwc2_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  __eclic_disable_interrupt(RHPORT_IRQn);
+}
 
 #endif /* DWC2_GD32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 3a5e1a9ac..d99e5502a 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -84,4 +84,18 @@
 
 #endif
 
+TU_ATTR_ALWAYS_INLINE
+static inline void dcd_dwc2_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(RHPORT_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dcd_dwc2_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(RHPORT_IRQn);
+}
+
 #endif /* DWC2_STM32_H_ */

From a0202df920889b57f79560760f6a38632e52c364 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 13:49:59 +0700
Subject: [PATCH 0592/2085] add TU_ARGS_APPLY(), TU_CHECK_MCU() now could check
 list of mcus

---
 src/common/tusb_common.h   | 31 -----------------------------
 src/common/tusb_compiler.h | 40 ++++++++++++++++++++++++++++++++++++++
 src/tusb_option.h          |  9 ++++++++-
 3 files changed, 48 insertions(+), 32 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index fc92654b7..bf9641622 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -235,37 +235,6 @@ TU_ATTR_ALWAYS_INLINE static inline void     tu_unaligned_write16 (void* mem, ui
 
 #endif
 
-/*------------------------------------------------------------------*/
-/* Count number of arguments of __VA_ARGS__
- * - reference https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s
- * - _GET_NTH_ARG() takes args >= N (64) but only expand to Nth one (64th)
- * - _RSEQ_N() is reverse sequential to N to add padding to have
- * Nth position is the same as the number of arguments
- * - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma)
- *------------------------------------------------------------------*/
-#ifndef TU_ARGS_NUM
-
-#define TU_ARGS_NUM(...) 	 _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N())
-
-#define _TU_NARG(...)        _GET_NTH_ARG(__VA_ARGS__)
-#define _GET_NTH_ARG( \
-          _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \
-         _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
-         _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
-         _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \
-         _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
-         _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
-         _61,_62,_63,N,...) N
-#define _RSEQ_N() \
-         62,61,60,                      \
-         59,58,57,56,55,54,53,52,51,50, \
-         49,48,47,46,45,44,43,42,41,40, \
-         39,38,37,36,35,34,33,32,31,30, \
-         29,28,27,26,25,24,23,22,21,20, \
-         19,18,17,16,15,14,13,12,11,10, \
-         9,8,7,6,5,4,3,2,1,0
-#endif
-
 // To be removed
 //------------- Binary constant -------------//
 #if defined(__GNUC__) && !defined(__CC_ARM)
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 3e85939b0..b0999b5d9 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -67,6 +67,46 @@
 #define TU_LITTLE_ENDIAN (0x12u)
 #define TU_BIG_ENDIAN (0x21u)
 
+/*------------------------------------------------------------------*/
+/* Count number of arguments of __VA_ARGS__
+ * - reference https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s
+ * - _GET_NTH_ARG() takes args >= N (64) but only expand to Nth one (64th)
+ * - _RSEQ_N() is reverse sequential to N to add padding to have
+ * Nth position is the same as the number of arguments
+ * - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma)
+ *------------------------------------------------------------------*/
+#define TU_ARGS_NUM(...) 	 _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N())
+
+#define _TU_NARG(...)      _GET_NTH_ARG(__VA_ARGS__)
+#define _GET_NTH_ARG( \
+          _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \
+         _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
+         _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
+         _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \
+         _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
+         _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
+         _61,_62,_63,N,...) N
+#define _RSEQ_N() \
+         62,61,60,                      \
+         59,58,57,56,55,54,53,52,51,50, \
+         49,48,47,46,45,44,43,42,41,40, \
+         39,38,37,36,35,34,33,32,31,30, \
+         29,28,27,26,25,24,23,22,21,20, \
+         19,18,17,16,15,14,13,12,11,10, \
+         9,8,7,6,5,4,3,2,1,0
+
+// Apply an macro X to each of the arguments with an separated of choice
+#define TU_ARGS_APPLY(_X, _s, ...)   TU_XSTRCAT(_TU_ARGS_APPLY_, TU_ARGS_NUM(__VA_ARGS__))(_X, _s, __VA_ARGS__)
+
+#define _TU_ARGS_APPLY_1(_X, _s, _a1)                                    _X(_a1)
+#define _TU_ARGS_APPLY_2(_X, _s, _a1, _a2)                               _X(_a1) _s _X(_a2)
+#define _TU_ARGS_APPLY_3(_X, _s, _a1, _a2, _a3)                          _X(_a1) _s _TU_ARGS_APPLY_2(_X, _s, _a2, _a3)
+#define _TU_ARGS_APPLY_4(_X, _s, _a1, _a2, _a3, _a4)                     _X(_a1) _s _TU_ARGS_APPLY_3(_X, _s, _a2, _a3, _a4)
+#define _TU_ARGS_APPLY_5(_X, _s, _a1, _a2, _a3, _a4, _a5)                _X(_a1) _s _TU_ARGS_APPLY_4(_X, _s, _a2, _a3, _a4, _a5)
+#define _TU_ARGS_APPLY_6(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6)           _X(_a1) _s _TU_ARGS_APPLY_5(_X, _s, _a2, _a3, _a4, _a5, _a6)
+#define _TU_ARGS_APPLY_7(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7)      _X(_a1) _s _TU_ARGS_APPLY_6(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7)
+#define _TU_ARGS_APPLY_8(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7, _a8) _X(_a1) _s _TU_ARGS_APPLY_7(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7, _a8)
+
 //--------------------------------------------------------------------+
 // Compiler porting with Attribute and Endian
 //--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index e49fc0119..89d83472b 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -27,6 +27,8 @@
 #ifndef _TUSB_OPTION_H_
 #define _TUSB_OPTION_H_
 
+#include "common/tusb_compiler.h"
+
 #define TUSB_VERSION_MAJOR     0
 #define TUSB_VERSION_MINOR     12
 #define TUSB_VERSION_REVISION  0
@@ -36,7 +38,6 @@
 // Supported MCUs
 // CFG_TUSB_MCU must be defined to one of following value
 //--------------------------------------------------------------------+
-#define TU_CHECK_MCU(_m)            (CFG_TUSB_MCU == OPT_MCU_##_m)
 
 #define OPT_MCU_NONE                0
 
@@ -126,6 +127,12 @@
 // GigaDevice
 #define OPT_MCU_GD32VF103        1600 ///< GigaDevice GD32VF103
 
+
+// Helper to check if configured MCU is one of listed
+// Apply _TU_CHECK_MCU with || as separator to list of input
+#define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == OPT_MCU_##_m)
+#define TU_CHECK_MCU(...)   TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // Supported OS
 //--------------------------------------------------------------------+

From 9f014b059a2411d23a1a24e9154c89d87739eaaf Mon Sep 17 00:00:00 2001
From: Tod Kurt <todbot@users.noreply.github.com>
Date: Mon, 25 Oct 2021 00:07:59 -0700
Subject: [PATCH 0593/2085] properly handle Program Change and Channel
 Aftertouch messages

---
 src/class/midi/midi_device.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index edec57846..b08b362f9 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -279,6 +279,12 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
         stream->buffer[0] = (cable_num << 4) | msg;
         stream->total = 4;
       }
+      else if ( msg == 0xC || msg == 0xD)
+      {
+        // Channel Voice Messages, two-byte variants (Program Change and Channel Pressure)
+        stream->buffer[0] = (cable_num << 4) | msg;
+        stream->total = 3;
+      }
       else if ( msg == 0xf )
       {
         // System message

From 4ccf60954d184c0530daf800090bd7103aacee86 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 15:51:41 +0700
Subject: [PATCH 0594/2085] moving esp32s2 to dwc2, abstract
 dwc2_set_turnaround()

---
 .../cdc_msc_freertos/src/CMakeLists.txt       |  2 +-
 hw/bsp/gd32vf103/family.mk                    |  3 +-
 src/device/dcd_attr.h                         | 16 +--
 src/portable/synopsys/dwc2/dcd_dwc2.c         | 98 +++++--------------
 src/portable/synopsys/dwc2/dwc2_esp32.h       | 82 ++++++++++++++++
 src/portable/synopsys/dwc2/dwc2_gd32.h        | 37 +++++--
 src/portable/synopsys/dwc2/dwc2_stm32.h       | 83 +++++++++++++---
 src/tusb_option.h                             |  2 +-
 8 files changed, 222 insertions(+), 101 deletions(-)
 create mode 100644 src/portable/synopsys/dwc2/dwc2_esp32.h

diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index 07fc4df89..93ae0686a 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -27,5 +27,5 @@ target_sources(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src/class/net/ncm_device.c"
   "${TOP}/src/class/usbtmc/usbtmc_device.c"
   "${TOP}/src/class/vendor/vendor_device.c"
-  "${TOP}/src/portable/espressif/esp32sx/dcd_esp32sx.c"
+  "${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c"
 )
diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk
index 4de23ac17..49bacdf1b 100644
--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -28,8 +28,7 @@ CFLAGS += \
 	-mstrict-align \
 	-nostdlib -nostartfiles \
 	-DCFG_TUSB_MCU=OPT_MCU_GD32VF103 \
-	-DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP \
-	-DGD32VF103 
+	-DDOWNLOAD_MODE=DOWNLOAD_MODE_FLASHXIP
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 3690985c6..ddec481a8 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -36,13 +36,13 @@
 // - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
 
 //------------- NXP -------------//
-#if   TU_CHECK_MCU(LPC11UXX) || TU_CHECK_MCU(LPC13XX) || TU_CHECK_MCU(LPC15XX)
+#if   TU_CHECK_MCU(LPC11UXX, LPC13XX, LPC15XX)
   #define DCD_ATTR_ENDPOINT_MAX   5
 
-#elif TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+#elif TU_CHECK_MCU(LPC175X_6X, LPC177X_8X, LPC40XX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
-#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX)
+#elif TU_CHECK_MCU(LPC18XX, LPC43XX)
   // TODO USB0 has 6, USB1 has 4
   #define DCD_ATTR_ENDPOINT_MAX   6
 
@@ -60,7 +60,7 @@
 #elif TU_CHECK_MCU(MIMXRT10XX)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(MKL25ZXX) || TU_CHECK_MCU(K32L2BXX)
+#elif TU_CHECK_MCU(MKL25ZXX, K32L2BXX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 #elif TU_CHECK_MCU(MM32F327X)
@@ -72,8 +72,8 @@
   #define DCD_ATTR_ENDPOINT_MAX   9
 
 //------------- Microchip -------------//
-#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \
-      TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22)
+#elif TU_CHECK_MCU(SAMD21, SAMD51, SAME5X) || \
+      TU_CHECK_MCU(SAMD11, SAML21, SAML22)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(SAMG)
@@ -119,7 +119,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   9
   #define DCD_ATTR_DWC2_STM32
 
-#elif TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1)
+#elif TU_CHECK_MCU(STM32L0, STM32L1)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(STM32L4)
@@ -157,7 +157,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   12
 
 //------------- Espressif -------------//
-#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#elif TU_CHECK_MCU(ESP32S2, ESP32S3)
   #define DCD_ATTR_ENDPOINT_MAX   6
 
 //------------- Dialog -------------//
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 367fc7b56..c3773fb8b 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -30,13 +30,16 @@
 #include "tusb_option.h"
 #include "device/dcd_attr.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && (defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(GD32VF103))
+#if TUSB_OPT_DEVICE_ENABLED && \
+    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(ESP32S2, ESP32S3, GD32VF103) )
 
 #include "device/dcd.h"
 #include "dwc2_type.h"
 
 #if defined(DCD_ATTR_DWC2_STM32)
   #include "dwc2_stm32.h"
+#elif TU_CHECK_MCU(ESP32S2, ESP32S3)
+  #include "dwc2_esp32.h"
 #elif TU_CHECK_MCU(GD32VF103)
   #include "dwc2_gd32.h"
 #else
@@ -72,7 +75,7 @@ typedef struct {
 
 typedef volatile uint32_t * usb_fifo_t;
 
-xfer_ctl_t xfer_status[EP_MAX][2];
+xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
 #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
 
 // EP0 transfers are limited to 1 packet - larger sizes has to be split
@@ -85,7 +88,7 @@ static bool _out_ep_closed;                       // Flag to check if RX FIFO si
 // Calculate the RX FIFO size according to recommendations from reference manual
 static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
 {
-  return 15 + 2*(ep_size/4) + 2*EP_MAX;
+  return 15 + 2*(ep_size/4) + 2*DWC2_EP_MAX;
 }
 
 static void update_grxfsiz(uint8_t rhport)
@@ -96,7 +99,7 @@ static void update_grxfsiz(uint8_t rhport)
 
   // Determine largest EP size for RX FIFO
   uint16_t max_epsize = 0;
-  for (uint8_t epnum = 0; epnum < EP_MAX; epnum++)
+  for (uint8_t epnum = 0; epnum < DWC2_EP_MAX; epnum++)
   {
     max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
   }
@@ -122,7 +125,7 @@ static void bus_reset(uint8_t rhport)
   dev->DCFG &= ~DCFG_DAD_Msk;
 
   // 1. NAK for all OUT endpoints
-  for(uint8_t n = 0; n < EP_MAX; n++) {
+  for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
     out_ep[n].DOEPCTL |= DOEPCTL_SNAK;
   }
 
@@ -171,11 +174,11 @@ static void bus_reset(uint8_t rhport)
   //   - 2 for each used OUT endpoint
   //
   //   Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
-  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x EP_MAX = 47  + 2 x EP_MAX
-  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX
+  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x DWC2_EP_MAX = 47  + 2 x DWC2_EP_MAX
+  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x DWC2_EP_MAX = 271 + 2 x DWC2_EP_MAX
   //
   //   NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
-  //   of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
+  //   of the overall picture yet. We will use the worst scenario: largest possible + DWC2_EP_MAX
   //
   //   For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
   //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
@@ -186,7 +189,7 @@ static void bus_reset(uint8_t rhport)
   _allocated_fifo_words_tx = 16;
 
   // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+  core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
   in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
@@ -197,47 +200,6 @@ static void bus_reset(uint8_t rhport)
   core->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
 
-// Set turn-around timeout according to link speed
-extern uint32_t SystemCoreClock;
-static void set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
-{
-  core->GUSBCFG &= ~GUSBCFG_TRDT;
-
-  if ( speed == TUSB_SPEED_HIGH )
-  {
-    // Use fixed 0x09 for Highspeed
-    core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
-  }
-  else
-  {
-    // Turnaround timeout depends on the MCU clock
-    uint32_t turnaround;
-
-    if ( SystemCoreClock >= 32000000U )
-      turnaround = 0x6U;
-    else if ( SystemCoreClock >= 27500000U )
-      turnaround = 0x7U;
-    else if ( SystemCoreClock >= 24000000U )
-      turnaround = 0x8U;
-    else if ( SystemCoreClock >= 21800000U )
-      turnaround = 0x9U;
-    else if ( SystemCoreClock >= 20000000U )
-      turnaround = 0xAU;
-    else if ( SystemCoreClock >= 18500000U )
-      turnaround = 0xBU;
-    else if ( SystemCoreClock >= 17200000U )
-      turnaround = 0xCU;
-    else if ( SystemCoreClock >= 16000000U )
-      turnaround = 0xDU;
-    else if ( SystemCoreClock >= 15000000U )
-      turnaround = 0xEU;
-    else
-      turnaround = 0xFU;
-
-    // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
-  }
-}
 
 static tusb_speed_t get_speed(uint8_t rhport)
 {
@@ -368,6 +330,8 @@ void dcd_init (uint8_t rhport)
   // peripheral in each Reference Manual.
   dwc2_core_t * core = CORE_REG(rhport);
 
+  // check GSNPSID
+
   // No HNP/SRP (no OTG support), program timeout later.
   if ( rhport == 1 )
   {
@@ -422,7 +386,7 @@ void dcd_init (uint8_t rhport)
 
   // If USB host misbehaves during status portion of control xfer
   // (non zero-length packet), send STALL back and discard.
-  dev->DCFG |=  DCFG_NZLSOHSK;
+  dev->DCFG |= DCFG_NZLSOHSK;
 
   set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
 
@@ -457,16 +421,6 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
 
-static void remote_wakeup_delay(void)
-{
-  // try to delay for 1 ms
-  uint32_t count = SystemCoreClock / 1000;
-  while ( count-- )
-  {
-    __NOP();
-  }
-}
-
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
@@ -482,7 +436,7 @@ void dcd_remote_wakeup(uint8_t rhport)
   core->GINTMSK |= GINTMSK_SOFM;
 
   // Per specs: remote wakeup signal bit must be clear within 1-15ms
-  remote_wakeup_delay();
+  dwc2_remote_wakeup_delay();
 
   dev->DCTL &= ~DCTL_RWUSIG;
 }
@@ -518,7 +472,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
 
-  TU_ASSERT(epnum < EP_MAX);
+  TU_ASSERT(epnum < DWC2_EP_MAX);
 
   xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
   xfer->max_size = tu_edpt_packet_size(desc_edpt);
@@ -534,7 +488,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // If size_rx needs to be extended check if possible and if so enlarge it
     if (core->GRXFSIZ < sz)
     {
-      TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
+      TU_ASSERT(sz + _allocated_fifo_words_tx <= DWC2_EP_FIFO_SIZE/4);
 
       // Enlarge RX FIFO
       core->GRXFSIZ = sz;
@@ -571,15 +525,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
 
     // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= EP_FIFO_SIZE/4);
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= DWC2_EP_FIFO_SIZE/4);
 
     _allocated_fifo_words_tx += fifo_size;
 
-    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
+    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, DWC2_EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
 
     // DIEPTXF starts at FIFO #1.
     // Both TXFD and TXSA are in unit of 32-bit words.
-    core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+    core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
     in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) |
         (epnum << DIEPCTL_TXFNUM_Pos) |
@@ -606,7 +560,7 @@ void dcd_edpt_close_all (uint8_t rhport)
   // Disable non-control interrupt
   dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
 
-  for(uint8_t n = 1; n < EP_MAX; n++)
+  for(uint8_t n = 1; n < DWC2_EP_MAX; n++)
   {
     // disable OUT endpoint
     out_ep[n].DOEPCTL = 0;
@@ -756,7 +710,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
     uint16_t const fifo_size = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
     uint16_t const fifo_start = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
     // For now only the last opened endpoint can be closed without fuss.
-    TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
+    TU_ASSERT(fifo_start == DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
     _allocated_fifo_words_tx -= fifo_size;
   }
   else
@@ -920,7 +874,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
 static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t * out_ep) {
   // DAINT for a given EP clears when DOEPINTx is cleared.
   // OEPINT will be cleared when DAINT's out bits are cleared.
-  for(uint8_t n = 0; n < EP_MAX; n++) {
+  for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
     xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
 
     if(dev->DAINT & (1 << (DAINT_OEPINT_Pos + n))) {
@@ -949,7 +903,7 @@ static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t
 static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * in_ep) {
   // DAINT for a given EP clears when DIEPINTx is cleared.
   // IEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < EP_MAX; n++ )
+  for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
   {
     xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
 
@@ -1040,7 +994,7 @@ void dcd_int_handler(uint8_t rhport)
 
     tusb_speed_t const speed = get_speed(rhport);
 
-    set_turnaround(core, speed);
+    dwc2_set_turnaround(core, speed);
     dcd_event_bus_reset(rhport, speed, true);
   }
 
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
new file mode 100644
index 000000000..5e544673d
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -0,0 +1,82 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef _DWC2_ESP32_H_
+#define _DWC2_ESP32_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "esp_intr_alloc.h"
+#include "soc/periph_defs.h"
+//#include "soc/usb_periph.h"
+
+#define DWC2_REG_BASE       0x60080000UL
+#define DWC2_EP_MAX         5             // USB_OUT_EP_NUM
+#define DWC2_EP_FIFO_SIZE   1024
+
+// #define EP_FIFO_NUM 5
+
+static intr_handle_t usb_ih;
+
+static void dcd_int_handler_wrap(void* arg)
+{
+  (void) arg;
+  dcd_int_handler(0);
+}
+
+static inline void dcd_dwc2_int_enable (uint8_t rhport)
+{
+  (void) rhport;
+  esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih);
+}
+
+static inline void dcd_dwc2_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  esp_intr_free(usb_ih);
+}
+
+static inline void dwc2_remote_wakeup_delay(void)
+{
+  vTaskDelay(pdMS_TO_TICKS(1));
+}
+
+static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
+{
+  (void) core;
+  (void) speed;
+
+  // keep the reset value
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DWC2_ESP32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index 8fe390fd8..1ad066720 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -28,14 +28,18 @@
 #ifndef DWC2_GD32_H_
 #define DWC2_GD32_H_
 
-// for remote wakeup delay
-#define __NOP()   __asm volatile ("nop")
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
 
 // These numbers are the same for the whole GD32VF103 family.
-#define DWC2_REG_BASE   0x50000000UL
-#define EP_MAX          4
-#define EP_FIFO_SIZE    1280
-#define RHPORT_IRQn     86
+#define DWC2_REG_BASE       0x50000000UL
+#define DWC2_EP_MAX         4
+#define DWC2_EP_FIFO_SIZE   1280
+#define RHPORT_IRQn         86
+
+extern uint32_t SystemCoreClock;
 
 // The GD32VF103 is a RISC-V MCU, which implements the ECLIC Core-Local
 // Interrupt Controller by Nuclei. It is nearly API compatible to the
@@ -66,4 +70,25 @@ static inline void dcd_dwc2_int_disable (uint8_t rhport)
   __eclic_disable_interrupt(RHPORT_IRQn);
 }
 
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+  uint32_t count = SystemCoreClock / 1000;
+  while ( count-- ) __asm volatile ("nop");
+}
+
+static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
+{
+  (void) core;
+  (void) speed;
+
+  // keep the reset value
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* DWC2_GD32_H_ */
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index d99e5502a..2a6d58e9a 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -24,8 +24,12 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_DWC2_STM32_H_
-#define _TUSB_DWC2_STM32_H_
+#ifndef _DWC2_STM32_H_
+#define _DWC2_STM32_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
 
 // EP_MAX       : Max number of bi-directional endpoints including EP0
 // EP_FIFO_SIZE : Size of dedicated USB SRAM
@@ -71,19 +75,21 @@
 
 // On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
 #if TUD_OPT_RHPORT == 0
-  #define EP_MAX            EP_MAX_FS
-  #define EP_FIFO_SIZE      EP_FIFO_SIZE_FS
-  #define DWC2_REG_BASE     USB_OTG_FS_PERIPH_BASE
-  #define RHPORT_IRQn       OTG_FS_IRQn
+  #define DWC2_REG_BASE       USB_OTG_FS_PERIPH_BASE
+  #define DWC2_EP_MAX         EP_MAX_FS
+  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_FS
+  #define RHPORT_IRQn         OTG_FS_IRQn
 
 #else
-  #define EP_MAX            EP_MAX_HS
-  #define EP_FIFO_SIZE      EP_FIFO_SIZE_HS
-  #define DWC2_REG_BASE     USB_OTG_HS_PERIPH_BASE
-  #define RHPORT_IRQn       OTG_HS_IRQn
+  #define DWC2_REG_BASE       USB_OTG_HS_PERIPH_BASE
+  #define DWC2_EP_MAX         EP_MAX_HS
+  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_HS
+  #define RHPORT_IRQn         OTG_HS_IRQn
 
 #endif
 
+extern uint32_t SystemCoreClock;
+
 TU_ATTR_ALWAYS_INLINE
 static inline void dcd_dwc2_int_enable(uint8_t rhport)
 {
@@ -98,4 +104,59 @@ static inline void dcd_dwc2_int_disable (uint8_t rhport)
   NVIC_DisableIRQ(RHPORT_IRQn);
 }
 
-#endif /* DWC2_STM32_H_ */
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+  uint32_t count = SystemCoreClock / 1000;
+  while ( count-- ) __NOP();
+}
+
+// Set turn-around timeout according to link speed
+static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
+{
+  core->GUSBCFG &= ~GUSBCFG_TRDT;
+
+  if ( speed == TUSB_SPEED_HIGH )
+  {
+    // Use fixed 0x09 for Highspeed
+    core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
+  }
+  else
+  {
+    // Turnaround timeout depends on the MCU clock
+    uint32_t turnaround;
+
+    if ( SystemCoreClock >= 32000000U )
+      turnaround = 0x6U;
+    else if ( SystemCoreClock >= 27500000U )
+      turnaround = 0x7U;
+    else if ( SystemCoreClock >= 24000000U )
+      turnaround = 0x8U;
+    else if ( SystemCoreClock >= 21800000U )
+      turnaround = 0x9U;
+    else if ( SystemCoreClock >= 20000000U )
+      turnaround = 0xAU;
+    else if ( SystemCoreClock >= 18500000U )
+      turnaround = 0xBU;
+    else if ( SystemCoreClock >= 17200000U )
+      turnaround = 0xCU;
+    else if ( SystemCoreClock >= 16000000U )
+      turnaround = 0xDU;
+    else if ( SystemCoreClock >= 15000000U )
+      turnaround = 0xEU;
+    else
+      turnaround = 0xFU;
+
+    // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
+    core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
+  }
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DWC2_STM32_H_ */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 89d83472b..d707c44c7 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -131,7 +131,7 @@
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
 #define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == OPT_MCU_##_m)
-#define TU_CHECK_MCU(...)   TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__)
+#define TU_CHECK_MCU(...)   (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__))
 
 //--------------------------------------------------------------------+
 // Supported OS

From 85e18b9172b266f26ace35c825a9da0f3a32db0b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 15:58:12 +0700
Subject: [PATCH 0595/2085] house keeping

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 112 ++++++++++++++++----------
 1 file changed, 70 insertions(+), 42 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index c3773fb8b..fca5321f7 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -73,8 +73,6 @@ typedef struct {
   uint8_t interval;
 } xfer_ctl_t;
 
-typedef volatile uint32_t * usb_fifo_t;
-
 xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
 #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
 
@@ -586,7 +584,8 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->total_len   = total_bytes;
 
   // EP0 can only handle one packet
-  if(epnum == 0) {
+  if(epnum == 0)
+  {
     ep0_pending[dir] = total_bytes;
     // Schedule the first transaction for EP0 transfer
     edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
@@ -597,9 +596,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   uint16_t const short_packet_size = total_bytes % xfer->max_size;
 
   // Zero-size packet is special case.
-  if(short_packet_size > 0 || (total_bytes == 0)) {
-    num_packets++;
-  }
+  if ( short_packet_size > 0 || (total_bytes == 0) ) num_packets++;
 
   // Schedule packets to be sent within interrupt
   edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
@@ -628,7 +625,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   uint16_t const short_packet_size = total_bytes % xfer->max_size;
 
   // Zero-size packet is special case.
-  if(short_packet_size > 0 || (total_bytes == 0)) num_packets++;
+  if ( short_packet_size > 0 || (total_bytes == 0) ) num_packets++;
 
   // Schedule packets to be sent within interrupt
   edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
@@ -648,40 +645,51 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  if(dir == TUSB_DIR_IN) {
+  if ( dir == TUSB_DIR_IN )
+  {
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & DIEPCTL_EPENA) ){
+    if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & DIEPCTL_EPENA) )
+    {
       in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
-    } else {
+    }
+    else
+    {
       // Stop transmitting packets and NAK IN xfers.
       in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK;
-      while((in_ep[epnum].DIEPINT & DIEPINT_INEPNE) == 0);
+      while ( (in_ep[epnum].DIEPINT & DIEPINT_INEPNE) == 0 ) {}
 
       // Disable the endpoint.
       in_ep[epnum].DIEPCTL |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
-      while((in_ep[epnum].DIEPINT & DIEPINT_EPDISD_Msk) == 0);
+      while ( (in_ep[epnum].DIEPINT & DIEPINT_EPDISD_Msk) == 0 ) {}
+
       in_ep[epnum].DIEPINT = DIEPINT_EPDISD;
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
     core->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos);
     core->GRSTCTL |= GRSTCTL_TXFFLSH;
-    while((core->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0);
-  } else {
+    while ( (core->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0 ) {}
+  }
+  else
+  {
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) ){
+    if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) )
+    {
       out_ep[epnum].DOEPCTL |= stall ? DOEPCTL_STALL : 0;
-    } else {
+    }
+    else
+    {
       // Asserting GONAK is required to STALL an OUT endpoint.
       // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
       // anyway, and it can't be cleared by user code. If this while loop never
       // finishes, we have bigger problems than just the stack.
       dev->DCTL |= DCTL_SGONAK;
-      while((core->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0);
+      while ( (core->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {}
 
       // Ditto here- disable the endpoint.
       out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
-      while((out_ep[epnum].DOEPINT & DOEPINT_EPDISD_Msk) == 0);
+      while ( (out_ep[epnum].DOEPINT & DOEPINT_EPDISD_Msk) == 0 ) {}
+
       out_ep[epnum].DOEPINT = DOEPINT_EPDISD;
 
       // Allow other OUT endpoints to keep receiving.
@@ -735,10 +743,13 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   // Clear stall and reset data toggle
-  if(dir == TUSB_DIR_IN) {
+  if ( dir == TUSB_DIR_IN )
+  {
     in_ep[epnum].DIEPCTL &= ~DIEPCTL_STALL;
     in_ep[epnum].DIEPCTL |= DIEPCTL_SD0PID_SEVNFRM;
-  } else {
+  }
+  else
+  {
     out_ep[epnum].DOEPCTL &= ~DOEPCTL_STALL;
     out_ep[epnum].DOEPCTL |= DOEPCTL_SD0PID_SEVNFRM;
   }
@@ -751,11 +762,12 @@ static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
 {
   (void) rhport;
 
-  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
+  volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0);
 
   // Reading full available 32 bit words from fifo
   uint16_t full_words = len >> 2;
-  for(uint16_t i = 0; i < full_words; i++) {
+  for ( uint16_t i = 0; i < full_words; i++ )
+  {
     uint32_t tmp = *rx_fifo;
     dst[0] = tmp & 0x000000FF;
     dst[1] = (tmp & 0x0000FF00) >> 8;
@@ -766,13 +778,16 @@ static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
 
   // Read the remaining 1-3 bytes from fifo
   uint8_t bytes_rem = len & 0x03;
-  if(bytes_rem != 0) {
+  if ( bytes_rem != 0 )
+  {
     uint32_t tmp = *rx_fifo;
     dst[0] = tmp & 0x000000FF;
-    if(bytes_rem > 1) {
+    if ( bytes_rem > 1 )
+    {
       dst[1] = (tmp & 0x0000FF00) >> 8;
     }
-    if(bytes_rem > 2) {
+    if ( bytes_rem > 2 )
+    {
       dst[2] = (tmp & 0x00FF0000) >> 16;
     }
   }
@@ -783,24 +798,28 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
 {
   (void) rhport;
 
-  usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num);
+  volatile uint32_t * tx_fifo = FIFO_BASE(rhport, fifo_num);
 
   // Pushing full available 32 bit words to fifo
   uint16_t full_words = len >> 2;
-  for(uint16_t i = 0; i < full_words; i++){
+  for ( uint16_t i = 0; i < full_words; i++ )
+  {
     *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0];
     src += 4;
   }
 
   // Write the remaining 1-3 bytes into fifo
   uint8_t bytes_rem = len & 0x03;
-  if(bytes_rem){
+  if ( bytes_rem )
+  {
     uint32_t tmp_word = 0;
     tmp_word |= src[0];
-    if(bytes_rem > 1){
+    if ( bytes_rem > 1 )
+    {
       tmp_word |= src[1] << 8;
     }
-    if(bytes_rem > 2){
+    if ( bytes_rem > 2 )
+    {
       tmp_word |= src[2] << 16;
     }
     *tx_fifo = tmp_word;
@@ -809,7 +828,7 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
 
 static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
   dwc2_core_t * core = CORE_REG(rhport);
-  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
+  volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0);
 
   // Pop control word off FIFO
   uint32_t ctl_word = core->GRXSTSP;
@@ -817,7 +836,8 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
   uint8_t epnum     = (ctl_word & GRXSTSP_EPNUM_Msk) >>  GRXSTSP_EPNUM_Pos;
   uint16_t bcnt     = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
 
-  switch(pktsts) {
+  switch(pktsts)
+  {
     case 0x01: // Global OUT NAK (Interrupt)
       break;
 
@@ -871,28 +891,36 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
   }
 }
 
-static void handle_epout_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epout_t * out_ep) {
+static void handle_epout_ints (uint8_t rhport, dwc2_device_t *dev, dwc2_epout_t *out_ep)
+{
   // DAINT for a given EP clears when DOEPINTx is cleared.
   // OEPINT will be cleared when DAINT's out bits are cleared.
-  for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
-    xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
+  for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
+  {
+    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
 
-    if(dev->DAINT & (1 << (DAINT_OEPINT_Pos + n))) {
+    if ( dev->DAINT & (1 << (DAINT_OEPINT_Pos + n)) )
+    {
       // SETUP packet Setup Phase done.
-      if(out_ep[n].DOEPINT & DOEPINT_STUP) {
-        out_ep[n].DOEPINT =  DOEPINT_STUP;
+      if ( out_ep[n].DOEPINT & DOEPINT_STUP )
+      {
+        out_ep[n].DOEPINT = DOEPINT_STUP;
         dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
       }
 
       // OUT XFER complete
-      if(out_ep[n].DOEPINT & DOEPINT_XFRC) {
+      if ( out_ep[n].DOEPINT & DOEPINT_XFRC )
+      {
         out_ep[n].DOEPINT = DOEPINT_XFRC;
 
         // EP0 can only handle one packet
-        if((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
+        if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] )
+        {
           // Schedule another packet to be received.
           edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
-        } else {
+        }
+        else
+        {
           dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
         }
       }
@@ -948,7 +976,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
           // Push packet to Tx-FIFO
           if (xfer->ff)
           {
-            usb_fifo_t tx_fifo = FIFO_BASE(rhport, n);
+            volatile uint32_t * tx_fifo = FIFO_BASE(rhport, n);
             tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size);
           }
           else

From dbd31895bc234ff6d76d3fe736dc613890ab7acb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 17:04:03 +0700
Subject: [PATCH 0596/2085] change usage of TU_CHECK_MCU() to prevent macro
 conflict

---
 .../audio_4_channel_mic/src/usb_descriptors.c | 12 +--
 .../device/audio_test/src/usb_descriptors.c   |  2 +-
 examples/device/cdc_msc_freertos/src/main.c   |  6 +-
 .../device/cdc_msc_freertos/src/tusb_config.h |  2 +-
 .../device/hid_composite_freertos/src/main.c  |  6 +-
 .../hid_composite_freertos/src/tusb_config.h  |  2 +-
 .../video_capture/src/usb_descriptors.c       |  4 +-
 src/class/msc/msc_device.c                    |  2 +-
 src/common/tusb_compiler.h                    |  2 +-
 src/device/dcd_attr.h                         | 73 +++++++++----------
 src/host/hcd_attr.h                           | 46 ++++++------
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 11 +--
 src/portable/synopsys/dwc2/dcd_dwc2.c         |  6 +-
 src/tusb_option.h                             |  2 +-
 14 files changed, 85 insertions(+), 91 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index b6a5bd5c2..93ae2ea47 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -81,12 +81,12 @@ enum
 
 #define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_FOUR_CH_DESC_LEN)
 
-#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
   #define EPNUM_AUDIO   0x03
 
-#elif TU_CHECK_MCU(NRF5X)
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // nRF5x ISO can only be endpoint 8
   #define EPNUM_AUDIO   0x08
 
@@ -96,11 +96,11 @@ enum
 
 uint8_t const desc_configuration[] =
 {
-    // Interface count, string index, total length, attribute, power in mA
-    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+  // Interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
-    // Interface number, string index, EP Out & EP In address, EP size
-    TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN)
+  // Interface number, string index, EP Out & EP In address, EP size
+  TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_nBytesPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, /*_nBitsUsedPerSample*/ CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX*8, /*_epin*/ 0x80 | EPNUM_AUDIO, /*_epsize*/ CFG_TUD_AUDIO_EP_SZ_IN)
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index 348f5eede..09b2a2d45 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -86,7 +86,7 @@ enum
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
   #define EPNUM_AUDIO   0x03
 
-#elif TU_CHECK_MCU(NRF5X)
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // nRF5x ISO can only be endpoint 8
   #define EPNUM_AUDIO   0x08
 
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 65b7fda3b..2d3426f1d 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -30,7 +30,7 @@
 #include "bsp/board.h"
 #include "tusb.h"
 
-#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   // ESP-IDF need "freertos/" prefix in include path.
   // CFG_TUSB_OS_INC_PATH should be defined accordingly.
   #include "freertos/FreeRTOS.h"
@@ -105,14 +105,14 @@ int main(void)
   (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !( TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) )
+#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   vTaskStartScheduler();
 #endif
 
   return 0;
 }
 
-#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
 void app_main(void)
 {
   main();
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index d4bbdee48..55e84c62d 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -68,7 +68,7 @@
 #define CFG_TUSB_OS               OPT_OS_FREERTOS
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #define CFG_TUSB_OS_INC_PATH    freertos/
 #endif
 
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index b25c71f64..336f5d426 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -31,7 +31,7 @@
 #include "tusb.h"
 #include "usb_descriptors.h"
 
-#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   // ESP-IDF need "freertos/" prefix in include path.
   // CFG_TUSB_OS_INC_PATH should be defined accordingly.
   #include "freertos/FreeRTOS.h"
@@ -105,14 +105,14 @@ int main(void)
   (void) xTaskCreateStatic( hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
-#if !( TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3) )
+#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   vTaskStartScheduler();
 #endif
 
   return 0;
 }
 
-#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
 void app_main(void)
 {
   main();
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index b061dce3f..062f32ac3 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -68,7 +68,7 @@
 #define CFG_TUSB_OS               OPT_OS_FREERTOS
 
 // Espressif IDF requires "freertos/" prefix in include path
-#if TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #define CFG_TUSB_OS_INC_PATH    freertos/
 #endif
 
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 404ffe070..da8ec8e89 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -77,12 +77,12 @@ uint8_t const * tud_descriptor_device_cb(void)
 
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_LEN)
 
-#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
   #define EPNUM_VIDEO_IN    0x83
 
-#elif TU_CHECK_MCU(NRF5X)
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // nRF5x ISO can only be endpoint 8
   #define EPNUM_VIDEO_IN    0x88
 
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 81522be46..dd490dd68 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -617,7 +617,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       }
     }
 
-    #if TU_CHECK_MCU(CXD56)
+    #if TU_CHECK_MCU(OPT_MCU_CXD56)
     // WORKAROUND: cxd56 has its own nuttx usb stack which does not forward Set/ClearFeature(Endpoint) to DCD.
     // There is no way for us to know when EP is un-stall, therefore we will unconditionally un-stall here and
     // hope everything will work
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index b0999b5d9..d3284c62a 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -69,7 +69,7 @@
 
 /*------------------------------------------------------------------*/
 /* Count number of arguments of __VA_ARGS__
- * - reference https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s
+ * - reference https://stackoverflow.com/questions/2124339/c-preprocessor-va-args-number-of-arguments
  * - _GET_NTH_ARG() takes args >= N (64) but only expand to Nth one (64th)
  * - _RSEQ_N() is reverse sequential to N to add padding to have
  * Nth position is the same as the number of arguments
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index ddec481a8..54627eaa0 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -36,59 +36,59 @@
 // - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
 
 //------------- NXP -------------//
-#if   TU_CHECK_MCU(LPC11UXX, LPC13XX, LPC15XX)
+#if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
   #define DCD_ATTR_ENDPOINT_MAX   5
 
-#elif TU_CHECK_MCU(LPC175X_6X, LPC177X_8X, LPC40XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
-#elif TU_CHECK_MCU(LPC18XX, LPC43XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4
   #define DCD_ATTR_ENDPOINT_MAX   6
 
-#elif TU_CHECK_MCU(LPC51UXX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
    #define DCD_ATTR_ENDPOINT_MAX   5
 
-#elif TU_CHECK_MCU(LPC54XXX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
   // TODO USB0 has 5, USB1 has 6
   #define DCD_ATTR_ENDPOINT_MAX   6
 
-#elif TU_CHECK_MCU(LPC55XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
   // TODO USB0 has 5, USB1 has 6
   #define DCD_ATTR_ENDPOINT_MAX   6
 
-#elif TU_CHECK_MCU(MIMXRT10XX)
+#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(MKL25ZXX, K32L2BXX)
+#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
-#elif TU_CHECK_MCU(MM32F327X)
+#elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 //------------- Nordic -------------//
-#elif TU_CHECK_MCU(NRF5X)
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // 8 CBI + 1 ISO
   #define DCD_ATTR_ENDPOINT_MAX   9
 
 //------------- Microchip -------------//
-#elif TU_CHECK_MCU(SAMD21, SAMD51, SAME5X) || \
-      TU_CHECK_MCU(SAMD11, SAML21, SAML22)
+#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
+      TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(SAMG)
+#elif TU_CHECK_MCU(OPT_MCU_SAMG)
   #define DCD_ATTR_ENDPOINT_MAX   6
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
-#elif TU_CHECK_MCU(SAMX7X)
+#elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
   #define DCD_ATTR_ENDPOINT_MAX   10
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- ST -------------//
-#elif TU_CHECK_MCU(STM32F0)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F0)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(STM32F1)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F1)
   #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
       defined (STM32F107xB) || defined (STM32F107xC)
     #define DCD_ATTR_ENDPOINT_MAX   4
@@ -97,32 +97,32 @@
     #define DCD_ATTR_ENDPOINT_MAX   8
   #endif
 
-#elif TU_CHECK_MCU(STM32F2)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F2)
   // FS has 4 ep, HS has 5 ep
   #define DCD_ATTR_ENDPOINT_MAX   6
   #define DCD_ATTR_DWC2_STM32
 
-#elif TU_CHECK_MCU(STM32F3)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F3)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(STM32F4)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F4)
   // For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
   #define DCD_ATTR_ENDPOINT_MAX   6
   #define DCD_ATTR_DWC2_STM32
 
-#elif TU_CHECK_MCU(STM32F7)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F7)
   // FS has 6, HS has 9
   #define DCD_ATTR_ENDPOINT_MAX   9
   #define DCD_ATTR_DWC2_STM32
 
-#elif TU_CHECK_MCU(STM32H7)
+#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
   #define DCD_ATTR_ENDPOINT_MAX   9
   #define DCD_ATTR_DWC2_STM32
 
-#elif TU_CHECK_MCU(STM32L0, STM32L1)
+#elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(STM32L4)
+#elif TU_CHECK_MCU(OPT_MCU_STM32L4)
   #if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
       defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
       defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
@@ -134,53 +134,50 @@
   #endif
 
 //------------- Sony -------------//
-#elif TU_CHECK_MCU(CXD56)
+#elif TU_CHECK_MCU(OPT_MCU_CXD56)
   #define DCD_ATTR_ENDPOINT_MAX   7
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- TI -------------//
-#elif TU_CHECK_MCU(MSP430x5xx)
+#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 //------------- ValentyUSB -------------//
-#elif TU_CHECK_MCU(VALENTYUSB_EPTRI)
+#elif TU_CHECK_MCU(OPT_MCU_VALENTYUSB_EPTRI)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 //------------- Nuvoton -------------//
-#elif TU_CHECK_MCU(NUC121) || TU_CHECK_MCU(NUC126)
+#elif TU_CHECK_MCU(OPT_MCU_NUC121, OPT_MCU_NUC126)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(NUC120)
+#elif TU_CHECK_MCU(OPT_MCU_NUC120)
   #define DCD_ATTR_ENDPOINT_MAX   6
 
-#elif TU_CHECK_MCU(NUC505)
+#elif TU_CHECK_MCU(OPT_MCU_NUC505)
   #define DCD_ATTR_ENDPOINT_MAX   12
 
 //------------- Espressif -------------//
-#elif TU_CHECK_MCU(ESP32S2, ESP32S3)
+#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #define DCD_ATTR_ENDPOINT_MAX   6
 
 //------------- Dialog -------------//
-#elif TU_CHECK_MCU(DA1469X)
+#elif TU_CHECK_MCU(OPT_MCU_DA1469X)
   #define DCD_ATTR_ENDPOINT_MAX   4
 
 //------------- Raspberry Pi -------------//
-#elif TU_CHECK_MCU(RP2040)
+#elif TU_CHECK_MCU(OPT_MCU_RP2040)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 //------------- Silabs -------------//
-#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12)
+#elif TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_EFM32GG11, OPT_MCU_EFM32GG12)
   #define DCD_ATTR_ENDPOINT_MAX   7
 
 //------------- Renesas -------------//
-#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N)
+#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #define DCD_ATTR_ENDPOINT_MAX   10
 
-//#elif TU_CHECK_MCU(MM32F327X)
-//  #define DCD_ATTR_ENDPOINT_MAX not known yet
-
 //------------- GigaDevice -------------//
-#elif TU_CHECK_MCU(GD32VF103)
+#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
   #define DCD_ATTR_ENDPOINT_MAX   4
 
 #else
diff --git a/src/host/hcd_attr.h b/src/host/hcd_attr.h
index 729fc407b..a9bc242d7 100644
--- a/src/host/hcd_attr.h
+++ b/src/host/hcd_attr.h
@@ -34,64 +34,64 @@
 // - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
 
 //------------- NXP -------------//
-#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   #define HCD_ATTR_OHCI
 
-#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #define HCD_ATTR_EHCI_TRANSDIMENSION
 
-#elif TU_CHECK_MCU(LPC54XXX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
   // #define HCD_ATTR_EHCI_NXP_PTD
 
-#elif TU_CHECK_MCU(LPC55XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
   // #define HCD_ATTR_EHCI_NXP_PTD
 
-#elif TU_CHECK_MCU(MIMXRT10XX)
+#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
   #define HCD_ATTR_EHCI_TRANSDIMENSION
 
-#elif TU_CHECK_MCU(MKL25ZXX)
+#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX)
 
 //------------- Microchip -------------//
-#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \
-      TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22)
+#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
+      TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
 
-#elif TU_CHECK_MCU(SAMG)
+#elif TU_CHECK_MCU(OPT_MCU_SAMG)
 
-#elif TU_CHECK_MCU(SAMX7X)
+#elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
 
 //------------- ST -------------//
-#elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \
-      TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1, OPT_MCU_STM32F3) || \
+      TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32L4)
 
-#elif TU_CHECK_MCU(STM32F2) || TU_CHECK_MCU(STM32F4) || TU_CHECK_MCU(STM32F3)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F2, OPT_MCU_STM32F3, OPT_MCU_STM32F4)
 
-#elif TU_CHECK_MCU(STM32F7)
+#elif TU_CHECK_MCU(OPT_MCU_STM32F7)
 
-#elif TU_CHECK_MCU(STM32H7)
+#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
 
 //------------- Sony -------------//
-#elif TU_CHECK_MCU(CXD56)
+#elif TU_CHECK_MCU(OPT_MCU_CXD56)
 
 //------------- Nuvoton -------------//
-#elif TU_CHECK_MCU(NUC505)
+#elif TU_CHECK_MCU(OPT_MCU_NUC505)
 
 //------------- Espressif -------------//
-#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
 
 //------------- Raspberry Pi -------------//
-#elif TU_CHECK_MCU(RP2040)
+#elif TU_CHECK_MCU(OPT_MCU_RP2040)
 
 //------------- Silabs -------------//
-#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12)
+#elif TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_EFM32GG11, OPT_MCU_EFM32GG12)
 
 //------------- Renesas -------------//
-#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N)
+#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
 
-//#elif TU_CHECK_MCU(MM32F327X)
+//#elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
 //  #define DCD_ATTR_ENDPOINT_MAX not known yet
 
 //------------- GigaDevice -------------//
-#elif TU_CHECK_MCU(GD32VF103)
+#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
 
 #else
 //  #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index ca6564d46..933f352a2 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -109,13 +109,10 @@
 #define STM32F1_FSDEV
 #endif
 
-#if (TUSB_OPT_DEVICE_ENABLED) && ( \
-      (CFG_TUSB_MCU == OPT_MCU_STM32F0                          ) || \
-      (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_FSDEV)) || \
-      (CFG_TUSB_MCU == OPT_MCU_STM32F3                          ) || \
-	  (CFG_TUSB_MCU == OPT_MCU_STM32L0                          ) || \
-      (CFG_TUSB_MCU == OPT_MCU_STM32L1                          ) \
-    )
+#if TUSB_OPT_DEVICE_ENABLED && \
+      ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1) || \
+        (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) \
+      )
 
 // In order to reduce the dependance on HAL, we undefine this.
 // Some definitions are copied to our private include file.
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index fca5321f7..7ae10652c 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -31,16 +31,16 @@
 #include "device/dcd_attr.h"
 
 #if TUSB_OPT_DEVICE_ENABLED && \
-    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(ESP32S2, ESP32S3, GD32VF103) )
+    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) )
 
 #include "device/dcd.h"
 #include "dwc2_type.h"
 
 #if defined(DCD_ATTR_DWC2_STM32)
   #include "dwc2_stm32.h"
-#elif TU_CHECK_MCU(ESP32S2, ESP32S3)
+#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #include "dwc2_esp32.h"
-#elif TU_CHECK_MCU(GD32VF103)
+#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
   #include "dwc2_gd32.h"
 #else
   #error "Unsupported MCUs"
diff --git a/src/tusb_option.h b/src/tusb_option.h
index d707c44c7..509ff4a3c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -130,7 +130,7 @@
 
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
-#define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == OPT_MCU_##_m)
+#define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == _m)
 #define TU_CHECK_MCU(...)   (TU_ARGS_APPLY(_TU_CHECK_MCU, ||, __VA_ARGS__))
 
 //--------------------------------------------------------------------+

From 7d0d6f85f2aa9ff228ec76387a3d2d0ebf2580bb Mon Sep 17 00:00:00 2001
From: suda-morris <362953310@qq.com>
Date: Mon, 25 Oct 2021 21:53:14 +0800
Subject: [PATCH 0597/2085] update dcd_esp32sx with correct include list

---
 src/portable/espressif/esp32sx/dcd_esp32sx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index c27fc2922..a9c311324 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -31,7 +31,6 @@
 #if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2) ||  (CFG_TUSB_MCU == OPT_MCU_ESP32S3)) && TUSB_OPT_DEVICE_ENABLED)
 
 // Espressif
-#include "driver/periph_ctrl.h"
 #include "freertos/xtensa_api.h"
 #include "esp_intr_alloc.h"
 #include "esp_log.h"
@@ -39,6 +38,7 @@
 #include "soc/dport_reg.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/usb_periph.h"
+#include "soc/periph_defs.h" // for interrupt source
 
 #include "device/dcd.h"
 

From 460052c8a0b21d715a8206149f8106de0c5c38aa Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Oct 2021 21:20:58 +0700
Subject: [PATCH 0598/2085] spacing

---
 src/portable/synopsys/dwc2/dwc2_gd32.h |    2 -
 src/portable/synopsys/dwc2/dwc2_type.h | 1979 ++++++++++++------------
 2 files changed, 983 insertions(+), 998 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index 1ad066720..db1fb89fd 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -32,8 +32,6 @@
  extern "C" {
 #endif
 
-
-// These numbers are the same for the whole GD32VF103 family.
 #define DWC2_REG_BASE       0x50000000UL
 #define DWC2_EP_MAX         4
 #define DWC2_EP_FIFO_SIZE   1280
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 5f3b4a420..8d12e21ce 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -23,136 +23,124 @@
  extern "C" {
 #endif
 
-#ifdef __cplusplus
-  #define   __I   volatile
-#else
-  #define   __I   volatile const
-#endif
-#define     __O   volatile
-#define     __IO  volatile
-#define     __IM  volatile const
-#define     __OM  volatile
-#define     __IOM volatile
-
 #if 0
 // HS PHY
 typedef struct
 {
-
-__IO uint32_t HS_PHYC_PLL;         /*!< This register is used to control the PLL of the HS PHY.                       000h */
-__IO uint32_t Reserved04;              /*!< Reserved                                                                      004h */
-__IO uint32_t Reserved08;              /*!< Reserved                                                                      008h */
-__IO uint32_t HS_PHYC_TUNE;        /*!< This register is used to control the tuning interface of the High Speed PHY.  00Ch */
-__IO uint32_t Reserved10;              /*!< Reserved                                                                      010h */
-__IO uint32_t Reserved14;              /*!< Reserved                                                                      014h */
-__IO uint32_t HS_PHYC_LDO;         /*!< This register is used to control the regulator (LDO).                         018h */
+  volatile uint32_t HS_PHYC_PLL;         /*!< This register is used to control the PLL of the HS PHY.                       000h */
+  volatile uint32_t Reserved04;          /*!< Reserved                                                                      004h */
+  volatile uint32_t Reserved08;          /*!< Reserved                                                                      008h */
+  volatile uint32_t HS_PHYC_TUNE;        /*!< This register is used to control the tuning interface of the High Speed PHY.  00Ch */
+  volatile uint32_t Reserved10;          /*!< Reserved                                                                      010h */
+  volatile uint32_t Reserved14;          /*!< Reserved                                                                      014h */
+  volatile uint32_t HS_PHYC_LDO;         /*!< This register is used to control the regulator (LDO).                         018h */
 } HS_PHYC_GlobalTypeDef;
 #endif
 
 // Core
 typedef struct
 {
- __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
- __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
- __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
- __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
- __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
- __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
- __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
- __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
- __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
- __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
- __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
- __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
- uint32_t Reserved30[2];             /*!< Reserved                                     030h */
- __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
- __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
- __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
- __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
- __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
- __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
- uint32_t  Reserved6;                /*!< Reserved                                     050h */
- __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
- __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
- __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-  __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
-   uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
- __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
- __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO              104h-13Ch */
+  volatile uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
+  volatile uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  volatile uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  volatile uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  volatile uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  volatile uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  volatile uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  volatile uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  volatile uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  volatile uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  volatile uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  volatile uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+           uint32_t Reserved30[2];        /*!< Reserved                                     030h */
+  volatile uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  volatile uint32_t CID;                  /*!< User ID Register                             03Ch */
+  volatile uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
+  volatile uint32_t GHWCFG1;              /* User HW config1                                044h*/
+  volatile uint32_t GHWCFG2;              /* User HW config2                                048h*/
+  volatile uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+           uint32_t Reserved6;            /*!< Reserved                                     050h */
+  volatile uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  volatile uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  volatile uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+  volatile uint32_t GADPCTL;              /*!< ADP Timer, Control and Status Register       60Ch */
+           uint32_t Reserved43[39];       /*!< Reserved                                058h-0FFh */
+  volatile uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  volatile uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO              104h-13Ch */
 } dwc2_core_t;
 
 // Host
 typedef struct
 {
- __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
- __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
- __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
- uint32_t Reserved40C;           /*!< Reserved                             40Ch */
- __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
- __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
- __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+  volatile uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  volatile uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  volatile uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+           uint32_t Reserved40C;      /*!< Reserved                             40Ch */
+  volatile uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  volatile uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  volatile uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
 } dwc2_host_t;
 
 // Host Channel
 typedef struct
 {
- __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
- __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
- __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
- __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
- __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
- __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
- uint32_t Reserved[2];           /*!< Reserved                                      */
+  volatile uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  volatile uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  volatile uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  volatile uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  volatile uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  volatile uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+           uint32_t Reserved[2];      /*!< Reserved                                      */
 } dwc2_channel_t;
 
 // Device
 typedef struct
 {
- __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
- __IO uint32_t DCTL;            /*!< dev Control Register         804h */
- __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
- uint32_t Reserved0C;           /*!< Reserved                     80Ch */
- __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
- __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
- __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
- __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
- uint32_t  Reserved20;          /*!< Reserved                     820h */
- uint32_t Reserved9;            /*!< Reserved                     824h */
- __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
- __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
- __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
- __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
- __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
- __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
- uint32_t Reserved40;           /*!< dedicated EP mask            840h */
- __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
- uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
- __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+  volatile uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  volatile uint32_t DCTL;            /*!< dev Control Register         804h */
+  volatile uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+          uint32_t Reserved0C;      /*!< Reserved                     80Ch */
+  volatile uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  volatile uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  volatile uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  volatile uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+          uint32_t Reserved20;      /*!< Reserved                     820h */
+          uint32_t Reserved9;       /*!< Reserved                     824h */
+  volatile uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  volatile uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  volatile uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  volatile uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  volatile uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  volatile uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+          uint32_t Reserved40;      /*!< dedicated EP mask            840h */
+  volatile uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+          uint32_t Reserved44[15];  /*!< Reserved                 844-87Ch */
+  volatile uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
 } dwc2_device_t;
 
 // Endpoint IN
 typedef struct
 {
- __IO uint32_t DIEPCTL;       /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
- uint32_t Reserved04;         /*!< Reserved                       900h + (ep_num * 20h) + 04h */
- __IO uint32_t DIEPINT;       /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C;         /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DIEPTSIZ;      /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
- __IO uint32_t DIEPDMA;       /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
- __IO uint32_t DTXFSTS;       /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
- uint32_t Reserved18;         /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+  volatile uint32_t DIEPCTL;       /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+           uint32_t Reserved04;    /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  volatile uint32_t DIEPINT;       /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+           uint32_t Reserved0C;    /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  volatile uint32_t DIEPTSIZ;      /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  volatile uint32_t DIEPDMA;       /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  volatile uint32_t DTXFSTS;       /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+           uint32_t Reserved18;    /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
 } dwc2_epin_t;
 
 // Endpoint OUT
 typedef struct
 {
- __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
- uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
- __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
- uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
- __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
- __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
- uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+  volatile uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+           uint32_t Reserved04;    /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  volatile uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+           uint32_t Reserved0C;    /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  volatile uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  volatile uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+           uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
 } dwc2_epout_t;
 
 
@@ -179,1411 +167,1410 @@ typedef struct
 
 /********************  Bit definition for GOTGCTL register  ********************/
 #define GOTGCTL_SRQSCS_Pos               (0U)
-#define GOTGCTL_SRQSCS_Msk               (0x1UL << GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
-#define GOTGCTL_SRQSCS                   GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define GOTGCTL_SRQSCS_Msk               (0x1UL << GOTGCTL_SRQSCS_Pos)            /*!< 0x00000001 */
+#define GOTGCTL_SRQSCS                   GOTGCTL_SRQSCS_Msk                       /*!< Session request success */
 #define GOTGCTL_SRQ_Pos                  (1U)
-#define GOTGCTL_SRQ_Msk                  (0x1UL << GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
-#define GOTGCTL_SRQ                      GOTGCTL_SRQ_Msk       /*!< Session request */
+#define GOTGCTL_SRQ_Msk                  (0x1UL << GOTGCTL_SRQ_Pos)               /*!< 0x00000002 */
+#define GOTGCTL_SRQ                      GOTGCTL_SRQ_Msk                          /*!< Session request */
 #define GOTGCTL_VBVALOEN_Pos             (2U)
-#define GOTGCTL_VBVALOEN_Msk             (0x1UL << GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
-#define GOTGCTL_VBVALOEN                 GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define GOTGCTL_VBVALOEN_Msk             (0x1UL << GOTGCTL_VBVALOEN_Pos)          /*!< 0x00000004 */
+#define GOTGCTL_VBVALOEN                 GOTGCTL_VBVALOEN_Msk                     /*!< VBUS valid override enable */
 #define GOTGCTL_VBVALOVAL_Pos            (3U)
-#define GOTGCTL_VBVALOVAL_Msk            (0x1UL << GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
-#define GOTGCTL_VBVALOVAL                GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define GOTGCTL_VBVALOVAL_Msk            (0x1UL << GOTGCTL_VBVALOVAL_Pos)         /*!< 0x00000008 */
+#define GOTGCTL_VBVALOVAL                GOTGCTL_VBVALOVAL_Msk                    /*!< VBUS valid override value */
 #define GOTGCTL_AVALOEN_Pos              (4U)
-#define GOTGCTL_AVALOEN_Msk              (0x1UL << GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
-#define GOTGCTL_AVALOEN                  GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define GOTGCTL_AVALOEN_Msk              (0x1UL << GOTGCTL_AVALOEN_Pos)           /*!< 0x00000010 */
+#define GOTGCTL_AVALOEN                  GOTGCTL_AVALOEN_Msk                      /*!< A-peripheral session valid override enable */
 #define GOTGCTL_AVALOVAL_Pos             (5U)
-#define GOTGCTL_AVALOVAL_Msk             (0x1UL << GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
-#define GOTGCTL_AVALOVAL                 GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define GOTGCTL_AVALOVAL_Msk             (0x1UL << GOTGCTL_AVALOVAL_Pos)          /*!< 0x00000020 */
+#define GOTGCTL_AVALOVAL                 GOTGCTL_AVALOVAL_Msk                     /*!< A-peripheral session valid override value */
 #define GOTGCTL_BVALOEN_Pos              (6U)
-#define GOTGCTL_BVALOEN_Msk              (0x1UL << GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
-#define GOTGCTL_BVALOEN                  GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define GOTGCTL_BVALOEN_Msk              (0x1UL << GOTGCTL_BVALOEN_Pos)           /*!< 0x00000040 */
+#define GOTGCTL_BVALOEN                  GOTGCTL_BVALOEN_Msk                      /*!< B-peripheral session valid override enable */
 #define GOTGCTL_BVALOVAL_Pos             (7U)
-#define GOTGCTL_BVALOVAL_Msk             (0x1UL << GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
-#define GOTGCTL_BVALOVAL                 GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define GOTGCTL_BVALOVAL_Msk             (0x1UL << GOTGCTL_BVALOVAL_Pos)          /*!< 0x00000080 */
+#define GOTGCTL_BVALOVAL                 GOTGCTL_BVALOVAL_Msk                     /*!< B-peripheral session valid override value  */
 #define GOTGCTL_HNGSCS_Pos               (8U)
-#define GOTGCTL_HNGSCS_Msk               (0x1UL << GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
-#define GOTGCTL_HNGSCS                   GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define GOTGCTL_HNGSCS_Msk               (0x1UL << GOTGCTL_HNGSCS_Pos)            /*!< 0x00000100 */
+#define GOTGCTL_HNGSCS                   GOTGCTL_HNGSCS_Msk                       /*!< Host set HNP enable */
 #define GOTGCTL_HNPRQ_Pos                (9U)
-#define GOTGCTL_HNPRQ_Msk                (0x1UL << GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
-#define GOTGCTL_HNPRQ                    GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define GOTGCTL_HNPRQ_Msk                (0x1UL << GOTGCTL_HNPRQ_Pos)             /*!< 0x00000200 */
+#define GOTGCTL_HNPRQ                    GOTGCTL_HNPRQ_Msk                        /*!< HNP request */
 #define GOTGCTL_HSHNPEN_Pos              (10U)
-#define GOTGCTL_HSHNPEN_Msk              (0x1UL << GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
-#define GOTGCTL_HSHNPEN                  GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define GOTGCTL_HSHNPEN_Msk              (0x1UL << GOTGCTL_HSHNPEN_Pos)           /*!< 0x00000400 */
+#define GOTGCTL_HSHNPEN                  GOTGCTL_HSHNPEN_Msk                      /*!< Host set HNP enable */
 #define GOTGCTL_DHNPEN_Pos               (11U)
-#define GOTGCTL_DHNPEN_Msk               (0x1UL << GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
-#define GOTGCTL_DHNPEN                   GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define GOTGCTL_DHNPEN_Msk               (0x1UL << GOTGCTL_DHNPEN_Pos)            /*!< 0x00000800 */
+#define GOTGCTL_DHNPEN                   GOTGCTL_DHNPEN_Msk                       /*!< Device HNP enabled */
 #define GOTGCTL_EHEN_Pos                 (12U)
-#define GOTGCTL_EHEN_Msk                 (0x1UL << GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
-#define GOTGCTL_EHEN                     GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define GOTGCTL_EHEN_Msk                 (0x1UL << GOTGCTL_EHEN_Pos)              /*!< 0x00001000 */
+#define GOTGCTL_EHEN                     GOTGCTL_EHEN_Msk                         /*!< Embedded host enable */
 #define GOTGCTL_CIDSTS_Pos               (16U)
-#define GOTGCTL_CIDSTS_Msk               (0x1UL << GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
-#define GOTGCTL_CIDSTS                   GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define GOTGCTL_CIDSTS_Msk               (0x1UL << GOTGCTL_CIDSTS_Pos)            /*!< 0x00010000 */
+#define GOTGCTL_CIDSTS                   GOTGCTL_CIDSTS_Msk                       /*!< Connector ID status */
 #define GOTGCTL_DBCT_Pos                 (17U)
-#define GOTGCTL_DBCT_Msk                 (0x1UL << GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
-#define GOTGCTL_DBCT                     GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define GOTGCTL_DBCT_Msk                 (0x1UL << GOTGCTL_DBCT_Pos)              /*!< 0x00020000 */
+#define GOTGCTL_DBCT                     GOTGCTL_DBCT_Msk                         /*!< Long/short debounce time */
 #define GOTGCTL_ASVLD_Pos                (18U)
-#define GOTGCTL_ASVLD_Msk                (0x1UL << GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
-#define GOTGCTL_ASVLD                    GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define GOTGCTL_ASVLD_Msk                (0x1UL << GOTGCTL_ASVLD_Pos)             /*!< 0x00040000 */
+#define GOTGCTL_ASVLD                    GOTGCTL_ASVLD_Msk                        /*!< A-session valid  */
 #define GOTGCTL_BSESVLD_Pos              (19U)
-#define GOTGCTL_BSESVLD_Msk              (0x1UL << GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
-#define GOTGCTL_BSESVLD                  GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define GOTGCTL_BSESVLD_Msk              (0x1UL << GOTGCTL_BSESVLD_Pos)           /*!< 0x00080000 */
+#define GOTGCTL_BSESVLD                  GOTGCTL_BSESVLD_Msk                      /*!< B-session valid */
 #define GOTGCTL_OTGVER_Pos               (20U)
-#define GOTGCTL_OTGVER_Msk               (0x1UL << GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
-#define GOTGCTL_OTGVER                   GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define GOTGCTL_OTGVER_Msk               (0x1UL << GOTGCTL_OTGVER_Pos)            /*!< 0x00100000 */
+#define GOTGCTL_OTGVER                   GOTGCTL_OTGVER_Msk                       /*!< OTG version  */
 
 /********************  Bit definition for HCFG register  ********************/
 #define HCFG_FSLSPCS_Pos                 (0U)
-#define HCFG_FSLSPCS_Msk                 (0x3UL << HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
-#define HCFG_FSLSPCS                     HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
-#define HCFG_FSLSPCS_0                   (0x1UL << HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
-#define HCFG_FSLSPCS_1                   (0x2UL << HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define HCFG_FSLSPCS_Msk                 (0x3UL << HCFG_FSLSPCS_Pos)              /*!< 0x00000003 */
+#define HCFG_FSLSPCS                     HCFG_FSLSPCS_Msk                         /*!< FS/LS PHY clock select  */
+#define HCFG_FSLSPCS_0                   (0x1UL << HCFG_FSLSPCS_Pos)              /*!< 0x00000001 */
+#define HCFG_FSLSPCS_1                   (0x2UL << HCFG_FSLSPCS_Pos)              /*!< 0x00000002 */
 #define HCFG_FSLSS_Pos                   (2U)
-#define HCFG_FSLSS_Msk                   (0x1UL << HCFG_FSLSS_Pos) /*!< 0x00000004 */
-#define HCFG_FSLSS                       HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+#define HCFG_FSLSS_Msk                   (0x1UL << HCFG_FSLSS_Pos)                /*!< 0x00000004 */
+#define HCFG_FSLSS                       HCFG_FSLSS_Msk                           /*!< FS- and LS-only support */
 
 /********************  Bit definition for DCFG register  ********************/
 #define DCFG_DSPD_Pos                    (0U)
-#define DCFG_DSPD_Msk                    (0x3UL << DCFG_DSPD_Pos) /*!< 0x00000003 */
-#define DCFG_DSPD                        DCFG_DSPD_Msk         /*!< Device speed */
-#define DCFG_DSPD_0                      (0x1UL << DCFG_DSPD_Pos) /*!< 0x00000001 */
-#define DCFG_DSPD_1                      (0x2UL << DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define DCFG_DSPD_Msk                    (0x3UL << DCFG_DSPD_Pos)                 /*!< 0x00000003 */
+#define DCFG_DSPD                        DCFG_DSPD_Msk                            /*!< Device speed */
+#define DCFG_DSPD_0                      (0x1UL << DCFG_DSPD_Pos)                 /*!< 0x00000001 */
+#define DCFG_DSPD_1                      (0x2UL << DCFG_DSPD_Pos)                 /*!< 0x00000002 */
 #define DCFG_NZLSOHSK_Pos                (2U)
-#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
-#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             /*!< 0x00000004 */
+#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        /*!< Nonzero-length status OUT handshake */
 
 #define DCFG_DAD_Pos                     (4U)
-#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define DCFG_DAD                         DCFG_DAD_Msk          /*!< Device address */
-#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos) /*!< 0x00000010 */
-#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos) /*!< 0x00000020 */
-#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos) /*!< 0x00000040 */
-#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos) /*!< 0x00000080 */
-#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos) /*!< 0x00000100 */
-#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos) /*!< 0x00000200 */
-#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos) /*!< 0x00000400 */
+#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 /*!< 0x000007F0 */
+#define DCFG_DAD                         DCFG_DAD_Msk                             /*!< Device address */
+#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 /*!< 0x00000010 */
+#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 /*!< 0x00000020 */
+#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 /*!< 0x00000040 */
+#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 /*!< 0x00000080 */
+#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 /*!< 0x00000100 */
+#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 /*!< 0x00000200 */
+#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 /*!< 0x00000400 */
 
 #define DCFG_PFIVL_Pos                   (11U)
-#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define DCFG_PFIVL                       DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
-#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos) /*!< 0x00000800 */
-#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos) /*!< 0x00001000 */
+#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                /*!< 0x00001800 */
+#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           /*!< Periodic (micro)frame interval */
+#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                /*!< 0x00000800 */
+#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                /*!< 0x00001000 */
 
 #define DCFG_PERSCHIVL_Pos               (24U)
-#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
-#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
-#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            /*!< 0x03000000 */
+#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       /*!< Periodic scheduling interval */
+#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            /*!< 0x01000000 */
+#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            /*!< 0x02000000 */
 
 /********************  Bit definition for PCGCR register  ********************/
 #define PCGCR_STPPCLK_Pos                (0U)
-#define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
-#define PCGCR_STPPCLK                    PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos)             /*!< 0x00000001 */
+#define PCGCR_STPPCLK                    PCGCR_STPPCLK_Msk                        /*!< Stop PHY clock */
 #define PCGCR_GATEHCLK_Pos               (1U)
-#define PCGCR_GATEHCLK_Msk               (0x1UL << PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
-#define PCGCR_GATEHCLK                   PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define PCGCR_GATEHCLK_Msk               (0x1UL << PCGCR_GATEHCLK_Pos)            /*!< 0x00000002 */
+#define PCGCR_GATEHCLK                   PCGCR_GATEHCLK_Msk                       /*!< Gate HCLK */
 #define PCGCR_PHYSUSP_Pos                (4U)
-#define PCGCR_PHYSUSP_Msk                (0x1UL << PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
-#define PCGCR_PHYSUSP                    PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+#define PCGCR_PHYSUSP_Msk                (0x1UL << PCGCR_PHYSUSP_Pos)             /*!< 0x00000010 */
+#define PCGCR_PHYSUSP                    PCGCR_PHYSUSP_Msk                        /*!< PHY suspended */
 
 /********************  Bit definition for GOTGINT register  ********************/
 #define GOTGINT_SEDET_Pos                (2U)
-#define GOTGINT_SEDET_Msk                (0x1UL << GOTGINT_SEDET_Pos) /*!< 0x00000004 */
-#define GOTGINT_SEDET                    GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define GOTGINT_SEDET_Msk                (0x1UL << GOTGINT_SEDET_Pos)             /*!< 0x00000004 */
+#define GOTGINT_SEDET                    GOTGINT_SEDET_Msk                        /*!< Session end detected                   */
 #define GOTGINT_SRSSCHG_Pos              (8U)
-#define GOTGINT_SRSSCHG_Msk              (0x1UL << GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
-#define GOTGINT_SRSSCHG                  GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define GOTGINT_SRSSCHG_Msk              (0x1UL << GOTGINT_SRSSCHG_Pos)           /*!< 0x00000100 */
+#define GOTGINT_SRSSCHG                  GOTGINT_SRSSCHG_Msk                      /*!< Session request success status change  */
 #define GOTGINT_HNSSCHG_Pos              (9U)
-#define GOTGINT_HNSSCHG_Msk              (0x1UL << GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
-#define GOTGINT_HNSSCHG                  GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define GOTGINT_HNSSCHG_Msk              (0x1UL << GOTGINT_HNSSCHG_Pos)           /*!< 0x00000200 */
+#define GOTGINT_HNSSCHG                  GOTGINT_HNSSCHG_Msk                      /*!< Host negotiation success status change */
 #define GOTGINT_HNGDET_Pos               (17U)
-#define GOTGINT_HNGDET_Msk               (0x1UL << GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
-#define GOTGINT_HNGDET                   GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define GOTGINT_HNGDET_Msk               (0x1UL << GOTGINT_HNGDET_Pos)            /*!< 0x00020000 */
+#define GOTGINT_HNGDET                   GOTGINT_HNGDET_Msk                       /*!< Host negotiation detected              */
 #define GOTGINT_ADTOCHG_Pos              (18U)
-#define GOTGINT_ADTOCHG_Msk              (0x1UL << GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
-#define GOTGINT_ADTOCHG                  GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define GOTGINT_ADTOCHG_Msk              (0x1UL << GOTGINT_ADTOCHG_Pos)           /*!< 0x00040000 */
+#define GOTGINT_ADTOCHG                  GOTGINT_ADTOCHG_Msk                      /*!< A-device timeout change                */
 #define GOTGINT_DBCDNE_Pos               (19U)
-#define GOTGINT_DBCDNE_Msk               (0x1UL << GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
-#define GOTGINT_DBCDNE                   GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+#define GOTGINT_DBCDNE_Msk               (0x1UL << GOTGINT_DBCDNE_Pos)            /*!< 0x00080000 */
+#define GOTGINT_DBCDNE                   GOTGINT_DBCDNE_Msk                       /*!< Debounce done                          */
 #define GOTGINT_IDCHNG_Pos               (20U)
-#define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
-#define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk    /*!< Change in ID pin input value           */
+#define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos)            /*!< 0x00100000 */
+#define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk                       /*!< Change in ID pin input value           */
 
 /********************  Bit definition for DCTL register  ********************/
 #define DCTL_RWUSIG_Pos                  (0U)
-#define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos) /*!< 0x00000001 */
-#define DCTL_RWUSIG                      DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos)               /*!< 0x00000001 */
+#define DCTL_RWUSIG                      DCTL_RWUSIG_Msk                          /*!< Remote wakeup signaling */
 #define DCTL_SDIS_Pos                    (1U)
-#define DCTL_SDIS_Msk                    (0x1UL << DCTL_SDIS_Pos) /*!< 0x00000002 */
-#define DCTL_SDIS                        DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define DCTL_SDIS_Msk                    (0x1UL << DCTL_SDIS_Pos)                 /*!< 0x00000002 */
+#define DCTL_SDIS                        DCTL_SDIS_Msk                            /*!< Soft disconnect         */
 #define DCTL_GINSTS_Pos                  (2U)
-#define DCTL_GINSTS_Msk                  (0x1UL << DCTL_GINSTS_Pos) /*!< 0x00000004 */
-#define DCTL_GINSTS                      DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define DCTL_GINSTS_Msk                  (0x1UL << DCTL_GINSTS_Pos)               /*!< 0x00000004 */
+#define DCTL_GINSTS                      DCTL_GINSTS_Msk                          /*!< Global IN NAK status    */
 #define DCTL_GONSTS_Pos                  (3U)
-#define DCTL_GONSTS_Msk                  (0x1UL << DCTL_GONSTS_Pos) /*!< 0x00000008 */
-#define DCTL_GONSTS                      DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+#define DCTL_GONSTS_Msk                  (0x1UL << DCTL_GONSTS_Pos)               /*!< 0x00000008 */
+#define DCTL_GONSTS                      DCTL_GONSTS_Msk                          /*!< Global OUT NAK status   */
 
 #define DCTL_TCTL_Pos                    (4U)
-#define DCTL_TCTL_Msk                    (0x7UL << DCTL_TCTL_Pos) /*!< 0x00000070 */
-#define DCTL_TCTL                        DCTL_TCTL_Msk         /*!< Test control */
-#define DCTL_TCTL_0                      (0x1UL << DCTL_TCTL_Pos) /*!< 0x00000010 */
-#define DCTL_TCTL_1                      (0x2UL << DCTL_TCTL_Pos) /*!< 0x00000020 */
-#define DCTL_TCTL_2                      (0x4UL << DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define DCTL_TCTL_Msk                    (0x7UL << DCTL_TCTL_Pos)                 /*!< 0x00000070 */
+#define DCTL_TCTL                        DCTL_TCTL_Msk                            /*!< Test control */
+#define DCTL_TCTL_0                      (0x1UL << DCTL_TCTL_Pos)                 /*!< 0x00000010 */
+#define DCTL_TCTL_1                      (0x2UL << DCTL_TCTL_Pos)                 /*!< 0x00000020 */
+#define DCTL_TCTL_2                      (0x4UL << DCTL_TCTL_Pos)                 /*!< 0x00000040 */
 #define DCTL_SGINAK_Pos                  (7U)
-#define DCTL_SGINAK_Msk                  (0x1UL << DCTL_SGINAK_Pos) /*!< 0x00000080 */
-#define DCTL_SGINAK                      DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define DCTL_SGINAK_Msk                  (0x1UL << DCTL_SGINAK_Pos)               /*!< 0x00000080 */
+#define DCTL_SGINAK                      DCTL_SGINAK_Msk                          /*!< Set global IN NAK         */
 #define DCTL_CGINAK_Pos                  (8U)
-#define DCTL_CGINAK_Msk                  (0x1UL << DCTL_CGINAK_Pos) /*!< 0x00000100 */
-#define DCTL_CGINAK                      DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define DCTL_CGINAK_Msk                  (0x1UL << DCTL_CGINAK_Pos)               /*!< 0x00000100 */
+#define DCTL_CGINAK                      DCTL_CGINAK_Msk                          /*!< Clear global IN NAK       */
 #define DCTL_SGONAK_Pos                  (9U)
-#define DCTL_SGONAK_Msk                  (0x1UL << DCTL_SGONAK_Pos) /*!< 0x00000200 */
-#define DCTL_SGONAK                      DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define DCTL_SGONAK_Msk                  (0x1UL << DCTL_SGONAK_Pos)               /*!< 0x00000200 */
+#define DCTL_SGONAK                      DCTL_SGONAK_Msk                          /*!< Set global OUT NAK        */
 #define DCTL_CGONAK_Pos                  (10U)
-#define DCTL_CGONAK_Msk                  (0x1UL << DCTL_CGONAK_Pos) /*!< 0x00000400 */
-#define DCTL_CGONAK                      DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define DCTL_CGONAK_Msk                  (0x1UL << DCTL_CGONAK_Pos)               /*!< 0x00000400 */
+#define DCTL_CGONAK                      DCTL_CGONAK_Msk                          /*!< Clear global OUT NAK      */
 #define DCTL_POPRGDNE_Pos                (11U)
-#define DCTL_POPRGDNE_Msk                (0x1UL << DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
-#define DCTL_POPRGDNE                    DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define DCTL_POPRGDNE_Msk                (0x1UL << DCTL_POPRGDNE_Pos)             /*!< 0x00000800 */
+#define DCTL_POPRGDNE                    DCTL_POPRGDNE_Msk                        /*!< Power-on programming done */
 
 /********************  Bit definition for HFIR register  ********************/
 #define HFIR_FRIVL_Pos                   (0U)
-#define HFIR_FRIVL_Msk                   (0xFFFFUL << HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
-#define HFIR_FRIVL                       HFIR_FRIVL_Msk        /*!< Frame interval */
+#define HFIR_FRIVL_Msk                   (0xFFFFUL << HFIR_FRIVL_Pos)             /*!< 0x0000FFFF */
+#define HFIR_FRIVL                       HFIR_FRIVL_Msk                           /*!< Frame interval */
 
 /********************  Bit definition for HFNUM register  ********************/
 #define HFNUM_FRNUM_Pos                  (0U)
-#define HFNUM_FRNUM_Msk                  (0xFFFFUL << HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
-#define HFNUM_FRNUM                      HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define HFNUM_FRNUM_Msk                  (0xFFFFUL << HFNUM_FRNUM_Pos)            /*!< 0x0000FFFF */
+#define HFNUM_FRNUM                      HFNUM_FRNUM_Msk                          /*!< Frame number         */
 #define HFNUM_FTREM_Pos                  (16U)
-#define HFNUM_FTREM_Msk                  (0xFFFFUL << HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
-#define HFNUM_FTREM                      HFNUM_FTREM_Msk       /*!< Frame time remaining */
+#define HFNUM_FTREM_Msk                  (0xFFFFUL << HFNUM_FTREM_Pos)            /*!< 0xFFFF0000 */
+#define HFNUM_FTREM                      HFNUM_FTREM_Msk                          /*!< Frame time remaining */
 
 /********************  Bit definition for DSTS register  ********************/
 #define DSTS_SUSPSTS_Pos                 (0U)
-#define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
-#define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+#define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos)              /*!< 0x00000001 */
+#define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk                         /*!< Suspend status   */
 
 #define DSTS_ENUMSPD_Pos                 (1U)
-#define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
-#define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
-#define DSTS_ENUMSPD_0                   (0x1UL << DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
-#define DSTS_ENUMSPD_1                   (0x2UL << DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos)              /*!< 0x00000006 */
+#define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk                         /*!< Enumerated speed */
+#define DSTS_ENUMSPD_0                   (0x1UL << DSTS_ENUMSPD_Pos)              /*!< 0x00000002 */
+#define DSTS_ENUMSPD_1                   (0x2UL << DSTS_ENUMSPD_Pos)              /*!< 0x00000004 */
 #define DSTS_EERR_Pos                    (3U)
-#define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos) /*!< 0x00000008 */
-#define DSTS_EERR                        DSTS_EERR_Msk         /*!< Erratic error     */
+#define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos)                 /*!< 0x00000008 */
+#define DSTS_EERR                        DSTS_EERR_Msk                            /*!< Erratic error     */
 #define DSTS_FNSOF_Pos                   (8U)
-#define DSTS_FNSOF_Msk                   (0x3FFFUL << DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
-#define DSTS_FNSOF                       DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+#define DSTS_FNSOF_Msk                   (0x3FFFUL << DSTS_FNSOF_Pos)             /*!< 0x003FFF00 */
+#define DSTS_FNSOF                       DSTS_FNSOF_Msk                           /*!< Frame number of the received SOF */
 
 /********************  Bit definition for GAHBCFG register  ********************/
 #define GAHBCFG_GINT_Pos                 (0U)
-#define GAHBCFG_GINT_Msk                 (0x1UL << GAHBCFG_GINT_Pos) /*!< 0x00000001 */
-#define GAHBCFG_GINT                     GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+#define GAHBCFG_GINT_Msk                 (0x1UL << GAHBCFG_GINT_Pos)              /*!< 0x00000001 */
+#define GAHBCFG_GINT                     GAHBCFG_GINT_Msk                         /*!< Global interrupt mask */
 #define GAHBCFG_HBSTLEN_Pos              (1U)
-#define GAHBCFG_HBSTLEN_Msk              (0xFUL << GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
-#define GAHBCFG_HBSTLEN                  GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
-#define GAHBCFG_HBSTLEN_0                (0x0UL << GAHBCFG_HBSTLEN_Pos) /*!< Single */
-#define GAHBCFG_HBSTLEN_1                (0x1UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR */
-#define GAHBCFG_HBSTLEN_2                (0x3UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
-#define GAHBCFG_HBSTLEN_3                (0x5UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
-#define GAHBCFG_HBSTLEN_4                (0x7UL << GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define GAHBCFG_HBSTLEN_Msk              (0xFUL << GAHBCFG_HBSTLEN_Pos)           /*!< 0x0000001E */
+#define GAHBCFG_HBSTLEN                  GAHBCFG_HBSTLEN_Msk                      /*!< Burst length/type */
+#define GAHBCFG_HBSTLEN_0                (0x0UL << GAHBCFG_HBSTLEN_Pos)           /*!< Single */
+#define GAHBCFG_HBSTLEN_1                (0x1UL << GAHBCFG_HBSTLEN_Pos)           /*!< INCR */
+#define GAHBCFG_HBSTLEN_2                (0x3UL << GAHBCFG_HBSTLEN_Pos)           /*!< INCR4 */
+#define GAHBCFG_HBSTLEN_3                (0x5UL << GAHBCFG_HBSTLEN_Pos)           /*!< INCR8 */
+#define GAHBCFG_HBSTLEN_4                (0x7UL << GAHBCFG_HBSTLEN_Pos)           /*!< INCR16 */
 #define GAHBCFG_DMAEN_Pos                (5U)
-#define GAHBCFG_DMAEN_Msk                (0x1UL << GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
-#define GAHBCFG_DMAEN                    GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define GAHBCFG_DMAEN_Msk                (0x1UL << GAHBCFG_DMAEN_Pos)             /*!< 0x00000020 */
+#define GAHBCFG_DMAEN                    GAHBCFG_DMAEN_Msk                        /*!< DMA enable */
 #define GAHBCFG_TXFELVL_Pos              (7U)
-#define GAHBCFG_TXFELVL_Msk              (0x1UL << GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
-#define GAHBCFG_TXFELVL                  GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define GAHBCFG_TXFELVL_Msk              (0x1UL << GAHBCFG_TXFELVL_Pos)           /*!< 0x00000080 */
+#define GAHBCFG_TXFELVL                  GAHBCFG_TXFELVL_Msk                      /*!< TxFIFO empty level */
 #define GAHBCFG_PTXFELVL_Pos             (8U)
-#define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
-#define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+#define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos)          /*!< 0x00000100 */
+#define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk                     /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition for GUSBCFG register  ********************/
 #define GUSBCFG_TOCAL_Pos                (0U)
-#define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
-#define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
-#define GUSBCFG_TOCAL_0                  (0x1UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
-#define GUSBCFG_TOCAL_1                  (0x2UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
-#define GUSBCFG_TOCAL_2                  (0x4UL << GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             /*!< 0x00000007 */
+#define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk                        /*!< FS timeout calibration */
+#define GUSBCFG_TOCAL_0                  (0x1UL << GUSBCFG_TOCAL_Pos)             /*!< 0x00000001 */
+#define GUSBCFG_TOCAL_1                  (0x2UL << GUSBCFG_TOCAL_Pos)             /*!< 0x00000002 */
+#define GUSBCFG_TOCAL_2                  (0x4UL << GUSBCFG_TOCAL_Pos)             /*!< 0x00000004 */
 #define GUSBCFG_PHYIF_Pos                (3U)
-#define GUSBCFG_PHYIF_Msk                (0x1UL << GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */
-#define GUSBCFG_PHYIF                    GUSBCFG_PHYIF_Msk     /*!< PHY Interface (PHYIf) */
+#define GUSBCFG_PHYIF_Msk                (0x1UL << GUSBCFG_PHYIF_Pos)             /*!< 0x00000008 */
+#define GUSBCFG_PHYIF                    GUSBCFG_PHYIF_Msk                        /*!< PHY Interface (PHYIf) */
 #define GUSBCFG_ULPI_UTMI_SEL_Pos        (4U)
-#define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */
-#define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
+#define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos)     /*!< 0x00000010 */
+#define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk                /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
 #define GUSBCFG_PHYSEL_Pos               (6U)
-#define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
-#define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            /*!< 0x00000040 */
+#define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
 #define GUSBCFG_SRPCAP_Pos               (8U)
-#define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
-#define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            /*!< 0x00000100 */
+#define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       /*!< SRP-capable */
 #define GUSBCFG_HNPCAP_Pos               (9U)
-#define GUSBCFG_HNPCAP_Msk               (0x1UL << GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
-#define GUSBCFG_HNPCAP                   GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+#define GUSBCFG_HNPCAP_Msk               (0x1UL << GUSBCFG_HNPCAP_Pos)            /*!< 0x00000200 */
+#define GUSBCFG_HNPCAP                   GUSBCFG_HNPCAP_Msk                       /*!< HNP-capable */
 #define GUSBCFG_TRDT_Pos                 (10U)
-#define GUSBCFG_TRDT_Msk                 (0xFUL << GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
-#define GUSBCFG_TRDT                     GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
-#define GUSBCFG_TRDT_0                   (0x1UL << GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
-#define GUSBCFG_TRDT_1                   (0x2UL << GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
-#define GUSBCFG_TRDT_2                   (0x4UL << GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
-#define GUSBCFG_TRDT_3                   (0x8UL << GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define GUSBCFG_TRDT_Msk                 (0xFUL << GUSBCFG_TRDT_Pos)              /*!< 0x00003C00 */
+#define GUSBCFG_TRDT                     GUSBCFG_TRDT_Msk                         /*!< USB turnaround time */
+#define GUSBCFG_TRDT_0                   (0x1UL << GUSBCFG_TRDT_Pos)              /*!< 0x00000400 */
+#define GUSBCFG_TRDT_1                   (0x2UL << GUSBCFG_TRDT_Pos)              /*!< 0x00000800 */
+#define GUSBCFG_TRDT_2                   (0x4UL << GUSBCFG_TRDT_Pos)              /*!< 0x00001000 */
+#define GUSBCFG_TRDT_3                   (0x8UL << GUSBCFG_TRDT_Pos)              /*!< 0x00002000 */
 #define GUSBCFG_PHYLPCS_Pos              (15U)
-#define GUSBCFG_PHYLPCS_Msk              (0x1UL << GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
-#define GUSBCFG_PHYLPCS                  GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define GUSBCFG_PHYLPCS_Msk              (0x1UL << GUSBCFG_PHYLPCS_Pos)           /*!< 0x00008000 */
+#define GUSBCFG_PHYLPCS                  GUSBCFG_PHYLPCS_Msk                      /*!< PHY Low-power clock select */
 #define GUSBCFG_ULPIFSLS_Pos             (17U)
-#define GUSBCFG_ULPIFSLS_Msk             (0x1UL << GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
-#define GUSBCFG_ULPIFSLS                 GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define GUSBCFG_ULPIFSLS_Msk             (0x1UL << GUSBCFG_ULPIFSLS_Pos)          /*!< 0x00020000 */
+#define GUSBCFG_ULPIFSLS                 GUSBCFG_ULPIFSLS_Msk                     /*!< ULPI FS/LS select               */
 #define GUSBCFG_ULPIAR_Pos               (18U)
-#define GUSBCFG_ULPIAR_Msk               (0x1UL << GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
-#define GUSBCFG_ULPIAR                   GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define GUSBCFG_ULPIAR_Msk               (0x1UL << GUSBCFG_ULPIAR_Pos)            /*!< 0x00040000 */
+#define GUSBCFG_ULPIAR                   GUSBCFG_ULPIAR_Msk                       /*!< ULPI Auto-resume                */
 #define GUSBCFG_ULPICSM_Pos              (19U)
-#define GUSBCFG_ULPICSM_Msk              (0x1UL << GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
-#define GUSBCFG_ULPICSM                  GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define GUSBCFG_ULPICSM_Msk              (0x1UL << GUSBCFG_ULPICSM_Pos)           /*!< 0x00080000 */
+#define GUSBCFG_ULPICSM                  GUSBCFG_ULPICSM_Msk                      /*!< ULPI Clock SuspendM             */
 #define GUSBCFG_ULPIEVBUSD_Pos           (20U)
-#define GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
-#define GUSBCFG_ULPIEVBUSD               GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << GUSBCFG_ULPIEVBUSD_Pos)        /*!< 0x00100000 */
+#define GUSBCFG_ULPIEVBUSD               GUSBCFG_ULPIEVBUSD_Msk                   /*!< ULPI External VBUS Drive        */
 #define GUSBCFG_ULPIEVBUSI_Pos           (21U)
-#define GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
-#define GUSBCFG_ULPIEVBUSI               GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << GUSBCFG_ULPIEVBUSI_Pos)        /*!< 0x00200000 */
+#define GUSBCFG_ULPIEVBUSI               GUSBCFG_ULPIEVBUSI_Msk                   /*!< ULPI external VBUS indicator    */
 #define GUSBCFG_TSDPS_Pos                (22U)
-#define GUSBCFG_TSDPS_Msk                (0x1UL << GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
-#define GUSBCFG_TSDPS                    GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define GUSBCFG_TSDPS_Msk                (0x1UL << GUSBCFG_TSDPS_Pos)             /*!< 0x00400000 */
+#define GUSBCFG_TSDPS                    GUSBCFG_TSDPS_Msk                        /*!< TermSel DLine pulsing selection */
 #define GUSBCFG_PCCI_Pos                 (23U)
-#define GUSBCFG_PCCI_Msk                 (0x1UL << GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
-#define GUSBCFG_PCCI                     GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define GUSBCFG_PCCI_Msk                 (0x1UL << GUSBCFG_PCCI_Pos)              /*!< 0x00800000 */
+#define GUSBCFG_PCCI                     GUSBCFG_PCCI_Msk                         /*!< Indicator complement            */
 #define GUSBCFG_PTCI_Pos                 (24U)
-#define GUSBCFG_PTCI_Msk                 (0x1UL << GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
-#define GUSBCFG_PTCI                     GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define GUSBCFG_PTCI_Msk                 (0x1UL << GUSBCFG_PTCI_Pos)              /*!< 0x01000000 */
+#define GUSBCFG_PTCI                     GUSBCFG_PTCI_Msk                         /*!< Indicator pass through          */
 #define GUSBCFG_ULPIIPD_Pos              (25U)
-#define GUSBCFG_ULPIIPD_Msk              (0x1UL << GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
-#define GUSBCFG_ULPIIPD                  GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define GUSBCFG_ULPIIPD_Msk              (0x1UL << GUSBCFG_ULPIIPD_Pos)           /*!< 0x02000000 */
+#define GUSBCFG_ULPIIPD                  GUSBCFG_ULPIIPD_Msk                      /*!< ULPI interface protect disable  */
 #define GUSBCFG_FHMOD_Pos                (29U)
-#define GUSBCFG_FHMOD_Msk                (0x1UL << GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
-#define GUSBCFG_FHMOD                    GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define GUSBCFG_FHMOD_Msk                (0x1UL << GUSBCFG_FHMOD_Pos)             /*!< 0x20000000 */
+#define GUSBCFG_FHMOD                    GUSBCFG_FHMOD_Msk                        /*!< Forced host mode                */
 #define GUSBCFG_FDMOD_Pos                (30U)
-#define GUSBCFG_FDMOD_Msk                (0x1UL << GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
-#define GUSBCFG_FDMOD                    GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define GUSBCFG_FDMOD_Msk                (0x1UL << GUSBCFG_FDMOD_Pos)             /*!< 0x40000000 */
+#define GUSBCFG_FDMOD                    GUSBCFG_FDMOD_Msk                        /*!< Forced peripheral mode          */
 #define GUSBCFG_CTXPKT_Pos               (31U)
-#define GUSBCFG_CTXPKT_Msk               (0x1UL << GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define GUSBCFG_CTXPKT                   GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define GUSBCFG_CTXPKT_Msk               (0x1UL << GUSBCFG_CTXPKT_Pos)            /*!< 0x80000000 */
+#define GUSBCFG_CTXPKT                   GUSBCFG_CTXPKT_Msk                       /*!< Corrupt Tx packet               */
 
 /********************  Bit definition for GRSTCTL register  ********************/
 #define GRSTCTL_CSRST_Pos                (0U)
-#define GRSTCTL_CSRST_Msk                (0x1UL << GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
-#define GRSTCTL_CSRST                    GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define GRSTCTL_CSRST_Msk                (0x1UL << GRSTCTL_CSRST_Pos)             /*!< 0x00000001 */
+#define GRSTCTL_CSRST                    GRSTCTL_CSRST_Msk                        /*!< Core soft reset          */
 #define GRSTCTL_HSRST_Pos                (1U)
-#define GRSTCTL_HSRST_Msk                (0x1UL << GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
-#define GRSTCTL_HSRST                    GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define GRSTCTL_HSRST_Msk                (0x1UL << GRSTCTL_HSRST_Pos)             /*!< 0x00000002 */
+#define GRSTCTL_HSRST                    GRSTCTL_HSRST_Msk                        /*!< HCLK soft reset          */
 #define GRSTCTL_FCRST_Pos                (2U)
-#define GRSTCTL_FCRST_Msk                (0x1UL << GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
-#define GRSTCTL_FCRST                    GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define GRSTCTL_FCRST_Msk                (0x1UL << GRSTCTL_FCRST_Pos)             /*!< 0x00000004 */
+#define GRSTCTL_FCRST                    GRSTCTL_FCRST_Msk                        /*!< Host frame counter reset */
 #define GRSTCTL_RXFFLSH_Pos              (4U)
-#define GRSTCTL_RXFFLSH_Msk              (0x1UL << GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
-#define GRSTCTL_RXFFLSH                  GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define GRSTCTL_RXFFLSH_Msk              (0x1UL << GRSTCTL_RXFFLSH_Pos)           /*!< 0x00000010 */
+#define GRSTCTL_RXFFLSH                  GRSTCTL_RXFFLSH_Msk                      /*!< RxFIFO flush             */
 #define GRSTCTL_TXFFLSH_Pos              (5U)
-#define GRSTCTL_TXFFLSH_Msk              (0x1UL << GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
-#define GRSTCTL_TXFFLSH                  GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+#define GRSTCTL_TXFFLSH_Msk              (0x1UL << GRSTCTL_TXFFLSH_Pos)           /*!< 0x00000020 */
+#define GRSTCTL_TXFFLSH                  GRSTCTL_TXFFLSH_Msk                      /*!< TxFIFO flush             */
 #define GRSTCTL_TXFNUM_Pos               (6U)
-#define GRSTCTL_TXFNUM_Msk               (0x1FUL << GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
-#define GRSTCTL_TXFNUM                   GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
-#define GRSTCTL_TXFNUM_0                 (0x01UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
-#define GRSTCTL_TXFNUM_1                 (0x02UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
-#define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
-#define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
-#define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define GRSTCTL_TXFNUM_Msk               (0x1FUL << GRSTCTL_TXFNUM_Pos)           /*!< 0x000007C0 */
+#define GRSTCTL_TXFNUM                   GRSTCTL_TXFNUM_Msk                       /*!< TxFIFO number */
+#define GRSTCTL_TXFNUM_0                 (0x01UL << GRSTCTL_TXFNUM_Pos)           /*!< 0x00000040 */
+#define GRSTCTL_TXFNUM_1                 (0x02UL << GRSTCTL_TXFNUM_Pos)           /*!< 0x00000080 */
+#define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           /*!< 0x00000100 */
+#define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           /*!< 0x00000200 */
+#define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           /*!< 0x00000400 */
 #define GRSTCTL_DMAREQ_Pos               (30U)
-#define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
-#define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            /*!< 0x40000000 */
+#define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       /*!< DMA request signal */
 #define GRSTCTL_AHBIDL_Pos               (31U)
-#define GRSTCTL_AHBIDL_Msk               (0x1UL << GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
-#define GRSTCTL_AHBIDL                   GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+#define GRSTCTL_AHBIDL_Msk               (0x1UL << GRSTCTL_AHBIDL_Pos)            /*!< 0x80000000 */
+#define GRSTCTL_AHBIDL                   GRSTCTL_AHBIDL_Msk                       /*!< AHB master idle */
 
 /********************  Bit definition for DIEPMSK register  ********************/
 #define DIEPMSK_XFRCM_Pos                (0U)
-#define DIEPMSK_XFRCM_Msk                (0x1UL << DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define DIEPMSK_XFRCM                    DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define DIEPMSK_XFRCM_Msk                (0x1UL << DIEPMSK_XFRCM_Pos)             /*!< 0x00000001 */
+#define DIEPMSK_XFRCM                    DIEPMSK_XFRCM_Msk                        /*!< Transfer completed interrupt mask                 */
 #define DIEPMSK_EPDM_Pos                 (1U)
-#define DIEPMSK_EPDM_Msk                 (0x1UL << DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define DIEPMSK_EPDM                     DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define DIEPMSK_EPDM_Msk                 (0x1UL << DIEPMSK_EPDM_Pos)              /*!< 0x00000002 */
+#define DIEPMSK_EPDM                     DIEPMSK_EPDM_Msk                         /*!< Endpoint disabled interrupt mask                  */
 #define DIEPMSK_TOM_Pos                  (3U)
-#define DIEPMSK_TOM_Msk                  (0x1UL << DIEPMSK_TOM_Pos) /*!< 0x00000008 */
-#define DIEPMSK_TOM                      DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define DIEPMSK_TOM_Msk                  (0x1UL << DIEPMSK_TOM_Pos)               /*!< 0x00000008 */
+#define DIEPMSK_TOM                      DIEPMSK_TOM_Msk                          /*!< Timeout condition mask (nonisochronous endpoints) */
 #define DIEPMSK_ITTXFEMSK_Pos            (4U)
-#define DIEPMSK_ITTXFEMSK_Msk            (0x1UL << DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define DIEPMSK_ITTXFEMSK                DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define DIEPMSK_ITTXFEMSK_Msk            (0x1UL << DIEPMSK_ITTXFEMSK_Pos)         /*!< 0x00000010 */
+#define DIEPMSK_ITTXFEMSK                DIEPMSK_ITTXFEMSK_Msk                    /*!< IN token received when TxFIFO empty mask          */
 #define DIEPMSK_INEPNMM_Pos              (5U)
-#define DIEPMSK_INEPNMM_Msk              (0x1UL << DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
-#define DIEPMSK_INEPNMM                  DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define DIEPMSK_INEPNMM_Msk              (0x1UL << DIEPMSK_INEPNMM_Pos)           /*!< 0x00000020 */
+#define DIEPMSK_INEPNMM                  DIEPMSK_INEPNMM_Msk                      /*!< IN token received with EP mismatch mask           */
 #define DIEPMSK_INEPNEM_Pos              (6U)
-#define DIEPMSK_INEPNEM_Msk              (0x1UL << DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
-#define DIEPMSK_INEPNEM                  DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define DIEPMSK_INEPNEM_Msk              (0x1UL << DIEPMSK_INEPNEM_Pos)           /*!< 0x00000040 */
+#define DIEPMSK_INEPNEM                  DIEPMSK_INEPNEM_Msk                      /*!< IN endpoint NAK effective mask                    */
 #define DIEPMSK_TXFURM_Pos               (8U)
-#define DIEPMSK_TXFURM_Msk               (0x1UL << DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
-#define DIEPMSK_TXFURM                   DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define DIEPMSK_TXFURM_Msk               (0x1UL << DIEPMSK_TXFURM_Pos)            /*!< 0x00000100 */
+#define DIEPMSK_TXFURM                   DIEPMSK_TXFURM_Msk                       /*!< FIFO underrun mask                                */
 #define DIEPMSK_BIM_Pos                  (9U)
-#define DIEPMSK_BIM_Msk                  (0x1UL << DIEPMSK_BIM_Pos) /*!< 0x00000200 */
-#define DIEPMSK_BIM                      DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+#define DIEPMSK_BIM_Msk                  (0x1UL << DIEPMSK_BIM_Pos)               /*!< 0x00000200 */
+#define DIEPMSK_BIM                      DIEPMSK_BIM_Msk                          /*!< BNA interrupt mask                                */
 
 /********************  Bit definition for HPTXSTS register  ********************/
 #define HPTXSTS_PTXFSAVL_Pos             (0U)
-#define HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
-#define HPTXSTS_PTXFSAVL                 HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+#define HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos)       /*!< 0x0000FFFF */
+#define HPTXSTS_PTXFSAVL                 HPTXSTS_PTXFSAVL_Msk                     /*!< Periodic transmit data FIFO space available     */
 #define HPTXSTS_PTXQSAV_Pos              (16U)
-#define HPTXSTS_PTXQSAV_Msk              (0xFFUL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
-#define HPTXSTS_PTXQSAV                  HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
-#define HPTXSTS_PTXQSAV_0                (0x01UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
-#define HPTXSTS_PTXQSAV_1                (0x02UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
-#define HPTXSTS_PTXQSAV_2                (0x04UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
-#define HPTXSTS_PTXQSAV_3                (0x08UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
-#define HPTXSTS_PTXQSAV_4                (0x10UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
-#define HPTXSTS_PTXQSAV_5                (0x20UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
-#define HPTXSTS_PTXQSAV_6                (0x40UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
-#define HPTXSTS_PTXQSAV_7                (0x80UL << HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+#define HPTXSTS_PTXQSAV_Msk              (0xFFUL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00FF0000 */
+#define HPTXSTS_PTXQSAV                  HPTXSTS_PTXQSAV_Msk                      /*!< Periodic transmit request queue space available */
+#define HPTXSTS_PTXQSAV_0                (0x01UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00010000 */
+#define HPTXSTS_PTXQSAV_1                (0x02UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00020000 */
+#define HPTXSTS_PTXQSAV_2                (0x04UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00040000 */
+#define HPTXSTS_PTXQSAV_3                (0x08UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00080000 */
+#define HPTXSTS_PTXQSAV_4                (0x10UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00100000 */
+#define HPTXSTS_PTXQSAV_5                (0x20UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00200000 */
+#define HPTXSTS_PTXQSAV_6                (0x40UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00400000 */
+#define HPTXSTS_PTXQSAV_7                (0x80UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00800000 */
 
 #define HPTXSTS_PTXQTOP_Pos              (24U)
-#define HPTXSTS_PTXQTOP_Msk              (0xFFUL << HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
-#define HPTXSTS_PTXQTOP                  HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
-#define HPTXSTS_PTXQTOP_0                (0x01UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
-#define HPTXSTS_PTXQTOP_1                (0x02UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
-#define HPTXSTS_PTXQTOP_2                (0x04UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
-#define HPTXSTS_PTXQTOP_3                (0x08UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
-#define HPTXSTS_PTXQTOP_4                (0x10UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
-#define HPTXSTS_PTXQTOP_5                (0x20UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
-#define HPTXSTS_PTXQTOP_6                (0x40UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
-#define HPTXSTS_PTXQTOP_7                (0x80UL << HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+#define HPTXSTS_PTXQTOP_Msk              (0xFFUL << HPTXSTS_PTXQTOP_Pos)          /*!< 0xFF000000 */
+#define HPTXSTS_PTXQTOP                  HPTXSTS_PTXQTOP_Msk                      /*!< Top of the periodic transmit request queue */
+#define HPTXSTS_PTXQTOP_0                (0x01UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x01000000 */
+#define HPTXSTS_PTXQTOP_1                (0x02UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x02000000 */
+#define HPTXSTS_PTXQTOP_2                (0x04UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x04000000 */
+#define HPTXSTS_PTXQTOP_3                (0x08UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x08000000 */
+#define HPTXSTS_PTXQTOP_4                (0x10UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x10000000 */
+#define HPTXSTS_PTXQTOP_5                (0x20UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x20000000 */
+#define HPTXSTS_PTXQTOP_6                (0x40UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x40000000 */
+#define HPTXSTS_PTXQTOP_7                (0x80UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x80000000 */
 
 /********************  Bit definition for HAINT register  ********************/
 #define HAINT_HAINT_Pos                  (0U)
-#define HAINT_HAINT_Msk                  (0xFFFFUL << HAINT_HAINT_Pos) /*!< 0x0000FFFF */
-#define HAINT_HAINT                      HAINT_HAINT_Msk       /*!< Channel interrupts */
+#define HAINT_HAINT_Msk                  (0xFFFFUL << HAINT_HAINT_Pos)            /*!< 0x0000FFFF */
+#define HAINT_HAINT                      HAINT_HAINT_Msk                          /*!< Channel interrupts */
 
 /********************  Bit definition for DOEPMSK register  ********************/
 #define DOEPMSK_XFRCM_Pos                (0U)
-#define DOEPMSK_XFRCM_Msk                (0x1UL << DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define DOEPMSK_XFRCM                    DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define DOEPMSK_XFRCM_Msk                (0x1UL << DOEPMSK_XFRCM_Pos)             /*!< 0x00000001 */
+#define DOEPMSK_XFRCM                    DOEPMSK_XFRCM_Msk                        /*!< Transfer completed interrupt mask */
 #define DOEPMSK_EPDM_Pos                 (1U)
-#define DOEPMSK_EPDM_Msk                 (0x1UL << DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define DOEPMSK_EPDM                     DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define DOEPMSK_EPDM_Msk                 (0x1UL << DOEPMSK_EPDM_Pos)              /*!< 0x00000002 */
+#define DOEPMSK_EPDM                     DOEPMSK_EPDM_Msk                         /*!< Endpoint disabled interrupt mask               */
 #define DOEPMSK_AHBERRM_Pos              (2U)
-#define DOEPMSK_AHBERRM_Msk              (0x1UL << DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
-#define DOEPMSK_AHBERRM                  DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask    */
+#define DOEPMSK_AHBERRM_Msk              (0x1UL << DOEPMSK_AHBERRM_Pos)           /*!< 0x00000004 */
+#define DOEPMSK_AHBERRM                  DOEPMSK_AHBERRM_Msk                      /*!< OUT transaction AHB Error interrupt mask    */
 #define DOEPMSK_STUPM_Pos                (3U)
-#define DOEPMSK_STUPM_Msk                (0x1UL << DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
-#define DOEPMSK_STUPM                    DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define DOEPMSK_STUPM_Msk                (0x1UL << DOEPMSK_STUPM_Pos)             /*!< 0x00000008 */
+#define DOEPMSK_STUPM                    DOEPMSK_STUPM_Msk                        /*!< SETUP phase done mask                          */
 #define DOEPMSK_OTEPDM_Pos               (4U)
-#define DOEPMSK_OTEPDM_Msk               (0x1UL << DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
-#define DOEPMSK_OTEPDM                   DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define DOEPMSK_OTEPDM_Msk               (0x1UL << DOEPMSK_OTEPDM_Pos)            /*!< 0x00000010 */
+#define DOEPMSK_OTEPDM                   DOEPMSK_OTEPDM_Msk                       /*!< OUT token received when endpoint disabled mask */
 #define DOEPMSK_OTEPSPRM_Pos             (5U)
-#define DOEPMSK_OTEPSPRM_Msk             (0x1UL << DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
-#define DOEPMSK_OTEPSPRM                 DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define DOEPMSK_OTEPSPRM_Msk             (0x1UL << DOEPMSK_OTEPSPRM_Pos)          /*!< 0x00000020 */
+#define DOEPMSK_OTEPSPRM                 DOEPMSK_OTEPSPRM_Msk                     /*!< Status Phase Received mask                     */
 #define DOEPMSK_B2BSTUP_Pos              (6U)
-#define DOEPMSK_B2BSTUP_Msk              (0x1UL << DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
-#define DOEPMSK_B2BSTUP                  DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define DOEPMSK_B2BSTUP_Msk              (0x1UL << DOEPMSK_B2BSTUP_Pos)           /*!< 0x00000040 */
+#define DOEPMSK_B2BSTUP                  DOEPMSK_B2BSTUP_Msk                      /*!< Back-to-back SETUP packets received mask       */
 #define DOEPMSK_OPEM_Pos                 (8U)
-#define DOEPMSK_OPEM_Msk                 (0x1UL << DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
-#define DOEPMSK_OPEM                     DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define DOEPMSK_OPEM_Msk                 (0x1UL << DOEPMSK_OPEM_Pos)              /*!< 0x00000100 */
+#define DOEPMSK_OPEM                     DOEPMSK_OPEM_Msk                         /*!< OUT packet error mask                          */
 #define DOEPMSK_BOIM_Pos                 (9U)
-#define DOEPMSK_BOIM_Msk                 (0x1UL << DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
-#define DOEPMSK_BOIM                     DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+#define DOEPMSK_BOIM_Msk                 (0x1UL << DOEPMSK_BOIM_Pos)              /*!< 0x00000200 */
+#define DOEPMSK_BOIM                     DOEPMSK_BOIM_Msk                         /*!< BNA interrupt mask                             */
 #define DOEPMSK_BERRM_Pos                (12U)
-#define DOEPMSK_BERRM_Msk                (0x1UL << DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
-#define DOEPMSK_BERRM                    DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
+#define DOEPMSK_BERRM_Msk                (0x1UL << DOEPMSK_BERRM_Pos)             /*!< 0x00001000 */
+#define DOEPMSK_BERRM                    DOEPMSK_BERRM_Msk                        /*!< Babble error interrupt mask                   */
 #define DOEPMSK_NAKM_Pos                 (13U)
-#define DOEPMSK_NAKM_Msk                 (0x1UL << DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
-#define DOEPMSK_NAKM                     DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
+#define DOEPMSK_NAKM_Msk                 (0x1UL << DOEPMSK_NAKM_Pos)              /*!< 0x00002000 */
+#define DOEPMSK_NAKM                     DOEPMSK_NAKM_Msk                         /*!< OUT Packet NAK interrupt mask                  */
 #define DOEPMSK_NYETM_Pos                (14U)
-#define DOEPMSK_NYETM_Msk                (0x1UL << DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
-#define DOEPMSK_NYETM                    DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                           */
+#define DOEPMSK_NYETM_Msk                (0x1UL << DOEPMSK_NYETM_Pos)             /*!< 0x00004000 */
+#define DOEPMSK_NYETM                    DOEPMSK_NYETM_Msk                        /*!< NYET interrupt mask                           */
 
 /********************  Bit definition for GINTSTS register  ********************/
 #define GINTSTS_CMOD_Pos                 (0U)
-#define GINTSTS_CMOD_Msk                 (0x1UL << GINTSTS_CMOD_Pos) /*!< 0x00000001 */
-#define GINTSTS_CMOD                     GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define GINTSTS_CMOD_Msk                 (0x1UL << GINTSTS_CMOD_Pos)              /*!< 0x00000001 */
+#define GINTSTS_CMOD                     GINTSTS_CMOD_Msk                         /*!< Current mode of operation                      */
 #define GINTSTS_MMIS_Pos                 (1U)
-#define GINTSTS_MMIS_Msk                 (0x1UL << GINTSTS_MMIS_Pos) /*!< 0x00000002 */
-#define GINTSTS_MMIS                     GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define GINTSTS_MMIS_Msk                 (0x1UL << GINTSTS_MMIS_Pos)              /*!< 0x00000002 */
+#define GINTSTS_MMIS                     GINTSTS_MMIS_Msk                         /*!< Mode mismatch interrupt                        */
 #define GINTSTS_OTGINT_Pos               (2U)
-#define GINTSTS_OTGINT_Msk               (0x1UL << GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
-#define GINTSTS_OTGINT                   GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define GINTSTS_OTGINT_Msk               (0x1UL << GINTSTS_OTGINT_Pos)            /*!< 0x00000004 */
+#define GINTSTS_OTGINT                   GINTSTS_OTGINT_Msk                       /*!< OTG interrupt                                  */
 #define GINTSTS_SOF_Pos                  (3U)
-#define GINTSTS_SOF_Msk                  (0x1UL << GINTSTS_SOF_Pos) /*!< 0x00000008 */
-#define GINTSTS_SOF                      GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define GINTSTS_SOF_Msk                  (0x1UL << GINTSTS_SOF_Pos)               /*!< 0x00000008 */
+#define GINTSTS_SOF                      GINTSTS_SOF_Msk                          /*!< Start of frame                                 */
 #define GINTSTS_RXFLVL_Pos               (4U)
-#define GINTSTS_RXFLVL_Msk               (0x1UL << GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
-#define GINTSTS_RXFLVL                   GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define GINTSTS_RXFLVL_Msk               (0x1UL << GINTSTS_RXFLVL_Pos)            /*!< 0x00000010 */
+#define GINTSTS_RXFLVL                   GINTSTS_RXFLVL_Msk                       /*!< RxFIFO nonempty                                */
 #define GINTSTS_NPTXFE_Pos               (5U)
-#define GINTSTS_NPTXFE_Msk               (0x1UL << GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
-#define GINTSTS_NPTXFE                   GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define GINTSTS_NPTXFE_Msk               (0x1UL << GINTSTS_NPTXFE_Pos)            /*!< 0x00000020 */
+#define GINTSTS_NPTXFE                   GINTSTS_NPTXFE_Msk                       /*!< Nonperiodic TxFIFO empty                       */
 #define GINTSTS_GINAKEFF_Pos             (6U)
-#define GINTSTS_GINAKEFF_Msk             (0x1UL << GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
-#define GINTSTS_GINAKEFF                 GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define GINTSTS_GINAKEFF_Msk             (0x1UL << GINTSTS_GINAKEFF_Pos)          /*!< 0x00000040 */
+#define GINTSTS_GINAKEFF                 GINTSTS_GINAKEFF_Msk                     /*!< Global IN nonperiodic NAK effective            */
 #define GINTSTS_BOUTNAKEFF_Pos           (7U)
-#define GINTSTS_BOUTNAKEFF_Msk           (0x1UL << GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
-#define GINTSTS_BOUTNAKEFF               GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define GINTSTS_BOUTNAKEFF_Msk           (0x1UL << GINTSTS_BOUTNAKEFF_Pos)        /*!< 0x00000080 */
+#define GINTSTS_BOUTNAKEFF               GINTSTS_BOUTNAKEFF_Msk                   /*!< Global OUT NAK effective                       */
 #define GINTSTS_ESUSP_Pos                (10U)
-#define GINTSTS_ESUSP_Msk                (0x1UL << GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
-#define GINTSTS_ESUSP                    GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define GINTSTS_ESUSP_Msk                (0x1UL << GINTSTS_ESUSP_Pos)             /*!< 0x00000400 */
+#define GINTSTS_ESUSP                    GINTSTS_ESUSP_Msk                        /*!< Early suspend                                  */
 #define GINTSTS_USBSUSP_Pos              (11U)
-#define GINTSTS_USBSUSP_Msk              (0x1UL << GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
-#define GINTSTS_USBSUSP                  GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define GINTSTS_USBSUSP_Msk              (0x1UL << GINTSTS_USBSUSP_Pos)           /*!< 0x00000800 */
+#define GINTSTS_USBSUSP                  GINTSTS_USBSUSP_Msk                      /*!< USB suspend                                    */
 #define GINTSTS_USBRST_Pos               (12U)
-#define GINTSTS_USBRST_Msk               (0x1UL << GINTSTS_USBRST_Pos) /*!< 0x00001000 */
-#define GINTSTS_USBRST                   GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define GINTSTS_USBRST_Msk               (0x1UL << GINTSTS_USBRST_Pos)            /*!< 0x00001000 */
+#define GINTSTS_USBRST                   GINTSTS_USBRST_Msk                       /*!< USB reset                                      */
 #define GINTSTS_ENUMDNE_Pos              (13U)
-#define GINTSTS_ENUMDNE_Msk              (0x1UL << GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
-#define GINTSTS_ENUMDNE                  GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define GINTSTS_ENUMDNE_Msk              (0x1UL << GINTSTS_ENUMDNE_Pos)           /*!< 0x00002000 */
+#define GINTSTS_ENUMDNE                  GINTSTS_ENUMDNE_Msk                      /*!< Enumeration done                               */
 #define GINTSTS_ISOODRP_Pos              (14U)
-#define GINTSTS_ISOODRP_Msk              (0x1UL << GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
-#define GINTSTS_ISOODRP                  GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define GINTSTS_ISOODRP_Msk              (0x1UL << GINTSTS_ISOODRP_Pos)           /*!< 0x00004000 */
+#define GINTSTS_ISOODRP                  GINTSTS_ISOODRP_Msk                      /*!< Isochronous OUT packet dropped interrupt       */
 #define GINTSTS_EOPF_Pos                 (15U)
-#define GINTSTS_EOPF_Msk                 (0x1UL << GINTSTS_EOPF_Pos) /*!< 0x00008000 */
-#define GINTSTS_EOPF                     GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define GINTSTS_EOPF_Msk                 (0x1UL << GINTSTS_EOPF_Pos)              /*!< 0x00008000 */
+#define GINTSTS_EOPF                     GINTSTS_EOPF_Msk                         /*!< End of periodic frame interrupt                */
 #define GINTSTS_IEPINT_Pos               (18U)
-#define GINTSTS_IEPINT_Msk               (0x1UL << GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
-#define GINTSTS_IEPINT                   GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define GINTSTS_IEPINT_Msk               (0x1UL << GINTSTS_IEPINT_Pos)            /*!< 0x00040000 */
+#define GINTSTS_IEPINT                   GINTSTS_IEPINT_Msk                       /*!< IN endpoint interrupt                          */
 #define GINTSTS_OEPINT_Pos               (19U)
-#define GINTSTS_OEPINT_Msk               (0x1UL << GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
-#define GINTSTS_OEPINT                   GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define GINTSTS_OEPINT_Msk               (0x1UL << GINTSTS_OEPINT_Pos)            /*!< 0x00080000 */
+#define GINTSTS_OEPINT                   GINTSTS_OEPINT_Msk                       /*!< OUT endpoint interrupt                         */
 #define GINTSTS_IISOIXFR_Pos             (20U)
-#define GINTSTS_IISOIXFR_Msk             (0x1UL << GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
-#define GINTSTS_IISOIXFR                 GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define GINTSTS_IISOIXFR_Msk             (0x1UL << GINTSTS_IISOIXFR_Pos)          /*!< 0x00100000 */
+#define GINTSTS_IISOIXFR                 GINTSTS_IISOIXFR_Msk                     /*!< Incomplete isochronous IN transfer             */
 #define GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
 #define GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
-#define GINTSTS_PXFR_INCOMPISOOUT        GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define GINTSTS_PXFR_INCOMPISOOUT        GINTSTS_PXFR_INCOMPISOOUT_Msk            /*!< Incomplete periodic transfer                   */
 #define GINTSTS_DATAFSUSP_Pos            (22U)
-#define GINTSTS_DATAFSUSP_Msk            (0x1UL << GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
-#define GINTSTS_DATAFSUSP                GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define GINTSTS_DATAFSUSP_Msk            (0x1UL << GINTSTS_DATAFSUSP_Pos)         /*!< 0x00400000 */
+#define GINTSTS_DATAFSUSP                GINTSTS_DATAFSUSP_Msk                    /*!< Data fetch suspended                           */
 #define GINTSTS_RSTDET_Pos               (23U)
-#define GINTSTS_RSTDET_Msk               (0x1UL << GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
-#define GINTSTS_RSTDET                   GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define GINTSTS_RSTDET_Msk               (0x1UL << GINTSTS_RSTDET_Pos)            /*!< 0x00800000 */
+#define GINTSTS_RSTDET                   GINTSTS_RSTDET_Msk                       /*!< Reset detected interrupt                       */
 #define GINTSTS_HPRTINT_Pos              (24U)
-#define GINTSTS_HPRTINT_Msk              (0x1UL << GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
-#define GINTSTS_HPRTINT                  GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define GINTSTS_HPRTINT_Msk              (0x1UL << GINTSTS_HPRTINT_Pos)           /*!< 0x01000000 */
+#define GINTSTS_HPRTINT                  GINTSTS_HPRTINT_Msk                      /*!< Host port interrupt                            */
 #define GINTSTS_HCINT_Pos                (25U)
-#define GINTSTS_HCINT_Msk                (0x1UL << GINTSTS_HCINT_Pos) /*!< 0x02000000 */
-#define GINTSTS_HCINT                    GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define GINTSTS_HCINT_Msk                (0x1UL << GINTSTS_HCINT_Pos)             /*!< 0x02000000 */
+#define GINTSTS_HCINT                    GINTSTS_HCINT_Msk                        /*!< Host channels interrupt                        */
 #define GINTSTS_PTXFE_Pos                (26U)
-#define GINTSTS_PTXFE_Msk                (0x1UL << GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
-#define GINTSTS_PTXFE                    GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define GINTSTS_PTXFE_Msk                (0x1UL << GINTSTS_PTXFE_Pos)             /*!< 0x04000000 */
+#define GINTSTS_PTXFE                    GINTSTS_PTXFE_Msk                        /*!< Periodic TxFIFO empty                          */
 #define GINTSTS_LPMINT_Pos               (27U)
-#define GINTSTS_LPMINT_Msk               (0x1UL << GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
-#define GINTSTS_LPMINT                   GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define GINTSTS_LPMINT_Msk               (0x1UL << GINTSTS_LPMINT_Pos)            /*!< 0x08000000 */
+#define GINTSTS_LPMINT                   GINTSTS_LPMINT_Msk                       /*!< LPM interrupt                                  */
 #define GINTSTS_CIDSCHG_Pos              (28U)
-#define GINTSTS_CIDSCHG_Msk              (0x1UL << GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
-#define GINTSTS_CIDSCHG                  GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define GINTSTS_CIDSCHG_Msk              (0x1UL << GINTSTS_CIDSCHG_Pos)           /*!< 0x10000000 */
+#define GINTSTS_CIDSCHG                  GINTSTS_CIDSCHG_Msk                      /*!< Connector ID status change                     */
 #define GINTSTS_DISCINT_Pos              (29U)
-#define GINTSTS_DISCINT_Msk              (0x1UL << GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
-#define GINTSTS_DISCINT                  GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define GINTSTS_DISCINT_Msk              (0x1UL << GINTSTS_DISCINT_Pos)           /*!< 0x20000000 */
+#define GINTSTS_DISCINT                  GINTSTS_DISCINT_Msk                      /*!< Disconnect detected interrupt                  */
 #define GINTSTS_SRQINT_Pos               (30U)
-#define GINTSTS_SRQINT_Msk               (0x1UL << GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
-#define GINTSTS_SRQINT                   GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define GINTSTS_SRQINT_Msk               (0x1UL << GINTSTS_SRQINT_Pos)            /*!< 0x40000000 */
+#define GINTSTS_SRQINT                   GINTSTS_SRQINT_Msk                       /*!< Session request/new session detected interrupt */
 #define GINTSTS_WKUINT_Pos               (31U)
-#define GINTSTS_WKUINT_Msk               (0x1UL << GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
-#define GINTSTS_WKUINT                   GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+#define GINTSTS_WKUINT_Msk               (0x1UL << GINTSTS_WKUINT_Pos)            /*!< 0x80000000 */
+#define GINTSTS_WKUINT                   GINTSTS_WKUINT_Msk                       /*!< Resume/remote wakeup detected interrupt        */
 
 /********************  Bit definition for GINTMSK register  ********************/
 #define GINTMSK_MMISM_Pos                (1U)
-#define GINTMSK_MMISM_Msk                (0x1UL << GINTMSK_MMISM_Pos) /*!< 0x00000002 */
-#define GINTMSK_MMISM                    GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define GINTMSK_MMISM_Msk                (0x1UL << GINTMSK_MMISM_Pos)             /*!< 0x00000002 */
+#define GINTMSK_MMISM                    GINTMSK_MMISM_Msk                        /*!< Mode mismatch interrupt mask                        */
 #define GINTMSK_OTGINT_Pos               (2U)
-#define GINTMSK_OTGINT_Msk               (0x1UL << GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
-#define GINTMSK_OTGINT                   GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define GINTMSK_OTGINT_Msk               (0x1UL << GINTMSK_OTGINT_Pos)            /*!< 0x00000004 */
+#define GINTMSK_OTGINT                   GINTMSK_OTGINT_Msk                       /*!< OTG interrupt mask                                  */
 #define GINTMSK_SOFM_Pos                 (3U)
-#define GINTMSK_SOFM_Msk                 (0x1UL << GINTMSK_SOFM_Pos) /*!< 0x00000008 */
-#define GINTMSK_SOFM                     GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define GINTMSK_SOFM_Msk                 (0x1UL << GINTMSK_SOFM_Pos)              /*!< 0x00000008 */
+#define GINTMSK_SOFM                     GINTMSK_SOFM_Msk                         /*!< Start of frame mask                                 */
 #define GINTMSK_RXFLVLM_Pos              (4U)
-#define GINTMSK_RXFLVLM_Msk              (0x1UL << GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
-#define GINTMSK_RXFLVLM                  GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define GINTMSK_RXFLVLM_Msk              (0x1UL << GINTMSK_RXFLVLM_Pos)           /*!< 0x00000010 */
+#define GINTMSK_RXFLVLM                  GINTMSK_RXFLVLM_Msk                      /*!< Receive FIFO nonempty mask                          */
 #define GINTMSK_NPTXFEM_Pos              (5U)
-#define GINTMSK_NPTXFEM_Msk              (0x1UL << GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
-#define GINTMSK_NPTXFEM                  GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define GINTMSK_NPTXFEM_Msk              (0x1UL << GINTMSK_NPTXFEM_Pos)           /*!< 0x00000020 */
+#define GINTMSK_NPTXFEM                  GINTMSK_NPTXFEM_Msk                      /*!< Nonperiodic TxFIFO empty mask                       */
 #define GINTMSK_GINAKEFFM_Pos            (6U)
-#define GINTMSK_GINAKEFFM_Msk            (0x1UL << GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
-#define GINTMSK_GINAKEFFM                GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define GINTMSK_GINAKEFFM_Msk            (0x1UL << GINTMSK_GINAKEFFM_Pos)         /*!< 0x00000040 */
+#define GINTMSK_GINAKEFFM                GINTMSK_GINAKEFFM_Msk                    /*!< Global nonperiodic IN NAK effective mask            */
 #define GINTMSK_GONAKEFFM_Pos            (7U)
-#define GINTMSK_GONAKEFFM_Msk            (0x1UL << GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
-#define GINTMSK_GONAKEFFM                GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define GINTMSK_GONAKEFFM_Msk            (0x1UL << GINTMSK_GONAKEFFM_Pos)         /*!< 0x00000080 */
+#define GINTMSK_GONAKEFFM                GINTMSK_GONAKEFFM_Msk                    /*!< Global OUT NAK effective mask                       */
 #define GINTMSK_ESUSPM_Pos               (10U)
-#define GINTMSK_ESUSPM_Msk               (0x1UL << GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
-#define GINTMSK_ESUSPM                   GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define GINTMSK_ESUSPM_Msk               (0x1UL << GINTMSK_ESUSPM_Pos)            /*!< 0x00000400 */
+#define GINTMSK_ESUSPM                   GINTMSK_ESUSPM_Msk                       /*!< Early suspend mask                                  */
 #define GINTMSK_USBSUSPM_Pos             (11U)
-#define GINTMSK_USBSUSPM_Msk             (0x1UL << GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
-#define GINTMSK_USBSUSPM                 GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define GINTMSK_USBSUSPM_Msk             (0x1UL << GINTMSK_USBSUSPM_Pos)          /*!< 0x00000800 */
+#define GINTMSK_USBSUSPM                 GINTMSK_USBSUSPM_Msk                     /*!< USB suspend mask                                    */
 #define GINTMSK_USBRST_Pos               (12U)
-#define GINTMSK_USBRST_Msk               (0x1UL << GINTMSK_USBRST_Pos) /*!< 0x00001000 */
-#define GINTMSK_USBRST                   GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define GINTMSK_USBRST_Msk               (0x1UL << GINTMSK_USBRST_Pos)            /*!< 0x00001000 */
+#define GINTMSK_USBRST                   GINTMSK_USBRST_Msk                       /*!< USB reset mask                                      */
 #define GINTMSK_ENUMDNEM_Pos             (13U)
-#define GINTMSK_ENUMDNEM_Msk             (0x1UL << GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
-#define GINTMSK_ENUMDNEM                 GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define GINTMSK_ENUMDNEM_Msk             (0x1UL << GINTMSK_ENUMDNEM_Pos)          /*!< 0x00002000 */
+#define GINTMSK_ENUMDNEM                 GINTMSK_ENUMDNEM_Msk                     /*!< Enumeration done mask                               */
 #define GINTMSK_ISOODRPM_Pos             (14U)
-#define GINTMSK_ISOODRPM_Msk             (0x1UL << GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
-#define GINTMSK_ISOODRPM                 GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define GINTMSK_ISOODRPM_Msk             (0x1UL << GINTMSK_ISOODRPM_Pos)          /*!< 0x00004000 */
+#define GINTMSK_ISOODRPM                 GINTMSK_ISOODRPM_Msk                     /*!< Isochronous OUT packet dropped interrupt mask       */
 #define GINTMSK_EOPFM_Pos                (15U)
-#define GINTMSK_EOPFM_Msk                (0x1UL << GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
-#define GINTMSK_EOPFM                    GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define GINTMSK_EOPFM_Msk                (0x1UL << GINTMSK_EOPFM_Pos)             /*!< 0x00008000 */
+#define GINTMSK_EOPFM                    GINTMSK_EOPFM_Msk                        /*!< End of periodic frame interrupt mask                */
 #define GINTMSK_EPMISM_Pos               (17U)
-#define GINTMSK_EPMISM_Msk               (0x1UL << GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
-#define GINTMSK_EPMISM                   GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define GINTMSK_EPMISM_Msk               (0x1UL << GINTMSK_EPMISM_Pos)            /*!< 0x00020000 */
+#define GINTMSK_EPMISM                   GINTMSK_EPMISM_Msk                       /*!< Endpoint mismatch interrupt mask                    */
 #define GINTMSK_IEPINT_Pos               (18U)
-#define GINTMSK_IEPINT_Msk               (0x1UL << GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
-#define GINTMSK_IEPINT                   GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define GINTMSK_IEPINT_Msk               (0x1UL << GINTMSK_IEPINT_Pos)            /*!< 0x00040000 */
+#define GINTMSK_IEPINT                   GINTMSK_IEPINT_Msk                       /*!< IN endpoints interrupt mask                         */
 #define GINTMSK_OEPINT_Pos               (19U)
-#define GINTMSK_OEPINT_Msk               (0x1UL << GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
-#define GINTMSK_OEPINT                   GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define GINTMSK_OEPINT_Msk               (0x1UL << GINTMSK_OEPINT_Pos)            /*!< 0x00080000 */
+#define GINTMSK_OEPINT                   GINTMSK_OEPINT_Msk                       /*!< OUT endpoints interrupt mask                        */
 #define GINTMSK_IISOIXFRM_Pos            (20U)
-#define GINTMSK_IISOIXFRM_Msk            (0x1UL << GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
-#define GINTMSK_IISOIXFRM                GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define GINTMSK_IISOIXFRM_Msk            (0x1UL << GINTMSK_IISOIXFRM_Pos)         /*!< 0x00100000 */
+#define GINTMSK_IISOIXFRM                GINTMSK_IISOIXFRM_Msk                    /*!< Incomplete isochronous IN transfer mask             */
 #define GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
-#define GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
-#define GINTMSK_PXFRM_IISOOXFRM          GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos)   /*!< 0x00200000 */
+#define GINTMSK_PXFRM_IISOOXFRM          GINTMSK_PXFRM_IISOOXFRM_Msk              /*!< Incomplete periodic transfer mask                   */
 #define GINTMSK_FSUSPM_Pos               (22U)
-#define GINTMSK_FSUSPM_Msk               (0x1UL << GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
-#define GINTMSK_FSUSPM                   GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define GINTMSK_FSUSPM_Msk               (0x1UL << GINTMSK_FSUSPM_Pos)            /*!< 0x00400000 */
+#define GINTMSK_FSUSPM                   GINTMSK_FSUSPM_Msk                       /*!< Data fetch suspended mask                           */
 #define GINTMSK_RSTDEM_Pos               (23U)
-#define GINTMSK_RSTDEM_Msk               (0x1UL << GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
-#define GINTMSK_RSTDEM                   GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                       */
+#define GINTMSK_RSTDEM_Msk               (0x1UL << GINTMSK_RSTDEM_Pos)            /*!< 0x00800000 */
+#define GINTMSK_RSTDEM                   GINTMSK_RSTDEM_Msk                       /*!< Reset detected interrupt mask                       */
 #define GINTMSK_PRTIM_Pos                (24U)
-#define GINTMSK_PRTIM_Msk                (0x1UL << GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
-#define GINTMSK_PRTIM                    GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define GINTMSK_PRTIM_Msk                (0x1UL << GINTMSK_PRTIM_Pos)             /*!< 0x01000000 */
+#define GINTMSK_PRTIM                    GINTMSK_PRTIM_Msk                        /*!< Host port interrupt mask                            */
 #define GINTMSK_HCIM_Pos                 (25U)
-#define GINTMSK_HCIM_Msk                 (0x1UL << GINTMSK_HCIM_Pos) /*!< 0x02000000 */
-#define GINTMSK_HCIM                     GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define GINTMSK_HCIM_Msk                 (0x1UL << GINTMSK_HCIM_Pos)              /*!< 0x02000000 */
+#define GINTMSK_HCIM                     GINTMSK_HCIM_Msk                         /*!< Host channels interrupt mask                        */
 #define GINTMSK_PTXFEM_Pos               (26U)
-#define GINTMSK_PTXFEM_Msk               (0x1UL << GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
-#define GINTMSK_PTXFEM                   GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define GINTMSK_PTXFEM_Msk               (0x1UL << GINTMSK_PTXFEM_Pos)            /*!< 0x04000000 */
+#define GINTMSK_PTXFEM                   GINTMSK_PTXFEM_Msk                       /*!< Periodic TxFIFO empty mask                          */
 #define GINTMSK_LPMINTM_Pos              (27U)
-#define GINTMSK_LPMINTM_Msk              (0x1UL << GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
-#define GINTMSK_LPMINTM                  GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define GINTMSK_LPMINTM_Msk              (0x1UL << GINTMSK_LPMINTM_Pos)           /*!< 0x08000000 */
+#define GINTMSK_LPMINTM                  GINTMSK_LPMINTM_Msk                      /*!< LPM interrupt Mask                                  */
 #define GINTMSK_CIDSCHGM_Pos             (28U)
-#define GINTMSK_CIDSCHGM_Msk             (0x1UL << GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
-#define GINTMSK_CIDSCHGM                 GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define GINTMSK_CIDSCHGM_Msk             (0x1UL << GINTMSK_CIDSCHGM_Pos)          /*!< 0x10000000 */
+#define GINTMSK_CIDSCHGM                 GINTMSK_CIDSCHGM_Msk                     /*!< Connector ID status change mask                     */
 #define GINTMSK_DISCINT_Pos              (29U)
-#define GINTMSK_DISCINT_Msk              (0x1UL << GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
-#define GINTMSK_DISCINT                  GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define GINTMSK_DISCINT_Msk              (0x1UL << GINTMSK_DISCINT_Pos)           /*!< 0x20000000 */
+#define GINTMSK_DISCINT                  GINTMSK_DISCINT_Msk                      /*!< Disconnect detected interrupt mask                  */
 #define GINTMSK_SRQIM_Pos                (30U)
-#define GINTMSK_SRQIM_Msk                (0x1UL << GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
-#define GINTMSK_SRQIM                    GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define GINTMSK_SRQIM_Msk                (0x1UL << GINTMSK_SRQIM_Pos)             /*!< 0x40000000 */
+#define GINTMSK_SRQIM                    GINTMSK_SRQIM_Msk                        /*!< Session request/new session detected interrupt mask */
 #define GINTMSK_WUIM_Pos                 (31U)
-#define GINTMSK_WUIM_Msk                 (0x1UL << GINTMSK_WUIM_Pos) /*!< 0x80000000 */
-#define GINTMSK_WUIM                     GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+#define GINTMSK_WUIM_Msk                 (0x1UL << GINTMSK_WUIM_Pos)              /*!< 0x80000000 */
+#define GINTMSK_WUIM                     GINTMSK_WUIM_Msk                         /*!< Resume/remote wakeup detected interrupt mask        */
 
 /********************  Bit definition for DAINT register  ********************/
 #define DAINT_IEPINT_Pos                 (0U)
-#define DAINT_IEPINT_Msk                 (0xFFFFUL << DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
-#define DAINT_IEPINT                     DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define DAINT_IEPINT_Msk                 (0xFFFFUL << DAINT_IEPINT_Pos)           /*!< 0x0000FFFF */
+#define DAINT_IEPINT                     DAINT_IEPINT_Msk                         /*!< IN endpoint interrupt bits  */
 #define DAINT_OEPINT_Pos                 (16U)
-#define DAINT_OEPINT_Msk                 (0xFFFFUL << DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
-#define DAINT_OEPINT                     DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+#define DAINT_OEPINT_Msk                 (0xFFFFUL << DAINT_OEPINT_Pos)           /*!< 0xFFFF0000 */
+#define DAINT_OEPINT                     DAINT_OEPINT_Msk                         /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition for HAINTMSK register  ********************/
 #define HAINTMSK_HAINTM_Pos              (0U)
-#define HAINTMSK_HAINTM_Msk              (0xFFFFUL << HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
-#define HAINTMSK_HAINTM                  HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+#define HAINTMSK_HAINTM_Msk              (0xFFFFUL << HAINTMSK_HAINTM_Pos)        /*!< 0x0000FFFF */
+#define HAINTMSK_HAINTM                  HAINTMSK_HAINTM_Msk                      /*!< Channel interrupt mask */
 
 /********************  Bit definition for GRXSTSP register  ********************/
 #define GRXSTSP_EPNUM_Pos                (0U)
-#define GRXSTSP_EPNUM_Msk                (0xFUL << GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
-#define GRXSTSP_EPNUM                    GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define GRXSTSP_EPNUM_Msk                (0xFUL << GRXSTSP_EPNUM_Pos)             /*!< 0x0000000F */
+#define GRXSTSP_EPNUM                    GRXSTSP_EPNUM_Msk                        /*!< IN EP interrupt mask bits  */
 #define GRXSTSP_BCNT_Pos                 (4U)
-#define GRXSTSP_BCNT_Msk                 (0x7FFUL << GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
-#define GRXSTSP_BCNT                     GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define GRXSTSP_BCNT_Msk                 (0x7FFUL << GRXSTSP_BCNT_Pos)            /*!< 0x00007FF0 */
+#define GRXSTSP_BCNT                     GRXSTSP_BCNT_Msk                         /*!< OUT EP interrupt mask bits */
 #define GRXSTSP_DPID_Pos                 (15U)
-#define GRXSTSP_DPID_Msk                 (0x3UL << GRXSTSP_DPID_Pos) /*!< 0x00018000 */
-#define GRXSTSP_DPID                     GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define GRXSTSP_DPID_Msk                 (0x3UL << GRXSTSP_DPID_Pos)              /*!< 0x00018000 */
+#define GRXSTSP_DPID                     GRXSTSP_DPID_Msk                         /*!< OUT EP interrupt mask bits */
 #define GRXSTSP_PKTSTS_Pos               (17U)
-#define GRXSTSP_PKTSTS_Msk               (0xFUL << GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
-#define GRXSTSP_PKTSTS                   GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+#define GRXSTSP_PKTSTS_Msk               (0xFUL << GRXSTSP_PKTSTS_Pos)            /*!< 0x001E0000 */
+#define GRXSTSP_PKTSTS                   GRXSTSP_PKTSTS_Msk                       /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for DAINTMSK register  ********************/
 #define DAINTMSK_IEPM_Pos                (0U)
-#define DAINTMSK_IEPM_Msk                (0xFFFFUL << DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
-#define DAINTMSK_IEPM                    DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define DAINTMSK_IEPM_Msk                (0xFFFFUL << DAINTMSK_IEPM_Pos)          /*!< 0x0000FFFF */
+#define DAINTMSK_IEPM                    DAINTMSK_IEPM_Msk                        /*!< IN EP interrupt mask bits */
 #define DAINTMSK_OEPM_Pos                (16U)
-#define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
-#define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+#define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          /*!< 0xFFFF0000 */
+#define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
-
 #define CHNUM_Pos                        (0U)
-#define CHNUM_Msk                        (0xFUL << CHNUM_Pos)   /*!< 0x0000000F */
-#define CHNUM                            CHNUM_Msk             /*!< Channel number */
-#define CHNUM_0                          (0x1UL << CHNUM_Pos)   /*!< 0x00000001 */
-#define CHNUM_1                          (0x2UL << CHNUM_Pos)   /*!< 0x00000002 */
-#define CHNUM_2                          (0x4UL << CHNUM_Pos)   /*!< 0x00000004 */
-#define CHNUM_3                          (0x8UL << CHNUM_Pos)   /*!< 0x00000008 */
+#define CHNUM_Msk                        (0xFUL << CHNUM_Pos)                     /*!< 0x0000000F */
+#define CHNUM                            CHNUM_Msk                                /*!< Channel number */
+#define CHNUM_0                          (0x1UL << CHNUM_Pos)                     /*!< 0x00000001 */
+#define CHNUM_1                          (0x2UL << CHNUM_Pos)                     /*!< 0x00000002 */
+#define CHNUM_2                          (0x4UL << CHNUM_Pos)                     /*!< 0x00000004 */
+#define CHNUM_3                          (0x8UL << CHNUM_Pos)                     /*!< 0x00000008 */
 #define BCNT_Pos                         (4U)
-#define BCNT_Msk                         (0x7FFUL << BCNT_Pos)  /*!< 0x00007FF0 */
-#define BCNT                             BCNT_Msk              /*!< Byte count */
+#define BCNT_Msk                         (0x7FFUL << BCNT_Pos)                    /*!< 0x00007FF0 */
+#define BCNT                             BCNT_Msk                                 /*!< Byte count */
 
 #define DPID_Pos                         (15U)
-#define DPID_Msk                         (0x3UL << DPID_Pos)    /*!< 0x00018000 */
-#define DPID                             DPID_Msk              /*!< Data PID */
-#define DPID_0                           (0x1UL << DPID_Pos)    /*!< 0x00008000 */
-#define DPID_1                           (0x2UL << DPID_Pos)    /*!< 0x00010000 */
+#define DPID_Msk                         (0x3UL << DPID_Pos)                      /*!< 0x00018000 */
+#define DPID                             DPID_Msk                                 /*!< Data PID */
+#define DPID_0                           (0x1UL << DPID_Pos)                      /*!< 0x00008000 */
+#define DPID_1                           (0x2UL << DPID_Pos)                      /*!< 0x00010000 */
 
 #define PKTSTS_Pos                       (17U)
-#define PKTSTS_Msk                       (0xFUL << PKTSTS_Pos)  /*!< 0x001E0000 */
-#define PKTSTS                           PKTSTS_Msk            /*!< Packet status */
-#define PKTSTS_0                         (0x1UL << PKTSTS_Pos)  /*!< 0x00020000 */
-#define PKTSTS_1                         (0x2UL << PKTSTS_Pos)  /*!< 0x00040000 */
-#define PKTSTS_2                         (0x4UL << PKTSTS_Pos)  /*!< 0x00080000 */
-#define PKTSTS_3                         (0x8UL << PKTSTS_Pos)  /*!< 0x00100000 */
+#define PKTSTS_Msk                       (0xFUL << PKTSTS_Pos)                    /*!< 0x001E0000 */
+#define PKTSTS                           PKTSTS_Msk                               /*!< Packet status */
+#define PKTSTS_0                         (0x1UL << PKTSTS_Pos)                    /*!< 0x00020000 */
+#define PKTSTS_1                         (0x2UL << PKTSTS_Pos)                    /*!< 0x00040000 */
+#define PKTSTS_2                         (0x4UL << PKTSTS_Pos)                    /*!< 0x00080000 */
+#define PKTSTS_3                         (0x8UL << PKTSTS_Pos)                    /*!< 0x00100000 */
 
 #define EPNUM_Pos                        (0U)
-#define EPNUM_Msk                        (0xFUL << EPNUM_Pos)   /*!< 0x0000000F */
-#define EPNUM                            EPNUM_Msk             /*!< Endpoint number */
-#define EPNUM_0                          (0x1UL << EPNUM_Pos)   /*!< 0x00000001 */
-#define EPNUM_1                          (0x2UL << EPNUM_Pos)   /*!< 0x00000002 */
-#define EPNUM_2                          (0x4UL << EPNUM_Pos)   /*!< 0x00000004 */
-#define EPNUM_3                          (0x8UL << EPNUM_Pos)   /*!< 0x00000008 */
+#define EPNUM_Msk                        (0xFUL << EPNUM_Pos)                     /*!< 0x0000000F */
+#define EPNUM                            EPNUM_Msk                                /*!< Endpoint number */
+#define EPNUM_0                          (0x1UL << EPNUM_Pos)                     /*!< 0x00000001 */
+#define EPNUM_1                          (0x2UL << EPNUM_Pos)                     /*!< 0x00000002 */
+#define EPNUM_2                          (0x4UL << EPNUM_Pos)                     /*!< 0x00000004 */
+#define EPNUM_3                          (0x8UL << EPNUM_Pos)                     /*!< 0x00000008 */
 
 #define FRMNUM_Pos                       (21U)
-#define FRMNUM_Msk                       (0xFUL << FRMNUM_Pos)  /*!< 0x01E00000 */
-#define FRMNUM                           FRMNUM_Msk            /*!< Frame number */
-#define FRMNUM_0                         (0x1UL << FRMNUM_Pos)  /*!< 0x00200000 */
-#define FRMNUM_1                         (0x2UL << FRMNUM_Pos)  /*!< 0x00400000 */
-#define FRMNUM_2                         (0x4UL << FRMNUM_Pos)  /*!< 0x00800000 */
-#define FRMNUM_3                         (0x8UL << FRMNUM_Pos)  /*!< 0x01000000 */
+#define FRMNUM_Msk                       (0xFUL << FRMNUM_Pos)                    /*!< 0x01E00000 */
+#define FRMNUM                           FRMNUM_Msk                               /*!< Frame number */
+#define FRMNUM_0                         (0x1UL << FRMNUM_Pos)                    /*!< 0x00200000 */
+#define FRMNUM_1                         (0x2UL << FRMNUM_Pos)                    /*!< 0x00400000 */
+#define FRMNUM_2                         (0x4UL << FRMNUM_Pos)                    /*!< 0x00800000 */
+#define FRMNUM_3                         (0x8UL << FRMNUM_Pos)                    /*!< 0x01000000 */
 
 /********************  Bit definition for GRXFSIZ register  ********************/
 #define GRXFSIZ_RXFD_Pos                 (0U)
-#define GRXFSIZ_RXFD_Msk                 (0xFFFFUL << GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
-#define GRXFSIZ_RXFD                     GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+#define GRXFSIZ_RXFD_Msk                 (0xFFFFUL << GRXFSIZ_RXFD_Pos)           /*!< 0x0000FFFF */
+#define GRXFSIZ_RXFD                     GRXFSIZ_RXFD_Msk                         /*!< RxFIFO depth */
 
 /********************  Bit definition for DVBUSDIS register  ********************/
 #define DVBUSDIS_VBUSDT_Pos              (0U)
-#define DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
-#define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+#define DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << DVBUSDIS_VBUSDT_Pos)        /*!< 0x0000FFFF */
+#define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk                      /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
 #define NPTXFSA_Pos                      (0U)
-#define NPTXFSA_Msk                      (0xFFFFUL << NPTXFSA_Pos) /*!< 0x0000FFFF */
-#define NPTXFSA                          NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define NPTXFSA_Msk                      (0xFFFFUL << NPTXFSA_Pos)                /*!< 0x0000FFFF */
+#define NPTXFSA                          NPTXFSA_Msk                              /*!< Nonperiodic transmit RAM start address */
 #define NPTXFD_Pos                       (16U)
-#define NPTXFD_Msk                       (0xFFFFUL << NPTXFD_Pos) /*!< 0xFFFF0000 */
-#define NPTXFD                           NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define NPTXFD_Msk                       (0xFFFFUL << NPTXFD_Pos)                 /*!< 0xFFFF0000 */
+#define NPTXFD                           NPTXFD_Msk                               /*!< Nonperiodic TxFIFO depth               */
 #define TX0FSA_Pos                       (0U)
-#define TX0FSA_Msk                       (0xFFFFUL << TX0FSA_Pos) /*!< 0x0000FFFF */
-#define TX0FSA                           TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define TX0FSA_Msk                       (0xFFFFUL << TX0FSA_Pos)                 /*!< 0x0000FFFF */
+#define TX0FSA                           TX0FSA_Msk                               /*!< Endpoint 0 transmit RAM start address  */
 #define TX0FD_Pos                        (16U)
-#define TX0FD_Msk                        (0xFFFFUL << TX0FD_Pos) /*!< 0xFFFF0000 */
-#define TX0FD                            TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+#define TX0FD_Msk                        (0xFFFFUL << TX0FD_Pos)                  /*!< 0xFFFF0000 */
+#define TX0FD                            TX0FD_Msk                                /*!< Endpoint 0 TxFIFO depth                */
 
 /********************  Bit definition for DVBUSPULSE register  ********************/
 #define DVBUSPULSE_DVBUSP_Pos            (0U)
-#define DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
-#define DVBUSPULSE_DVBUSP                DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+#define DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << DVBUSPULSE_DVBUSP_Pos)       /*!< 0x00000FFF */
+#define DVBUSPULSE_DVBUSP                DVBUSPULSE_DVBUSP_Msk                    /*!< Device VBUS pulsing time */
 
 /********************  Bit definition for GNPTXSTS register  ********************/
 #define GNPTXSTS_NPTXFSAV_Pos            (0U)
-#define GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
-#define GNPTXSTS_NPTXFSAV                GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+#define GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos)      /*!< 0x0000FFFF */
+#define GNPTXSTS_NPTXFSAV                GNPTXSTS_NPTXFSAV_Msk                    /*!< Nonperiodic TxFIFO space available */
 
 #define GNPTXSTS_NPTQXSAV_Pos            (16U)
-#define GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
-#define GNPTXSTS_NPTQXSAV                GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
-#define GNPTXSTS_NPTQXSAV_0              (0x01UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
-#define GNPTXSTS_NPTQXSAV_1              (0x02UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
-#define GNPTXSTS_NPTQXSAV_2              (0x04UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
-#define GNPTXSTS_NPTQXSAV_3              (0x08UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
-#define GNPTXSTS_NPTQXSAV_4              (0x10UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
-#define GNPTXSTS_NPTQXSAV_5              (0x20UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
-#define GNPTXSTS_NPTQXSAV_6              (0x40UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
-#define GNPTXSTS_NPTQXSAV_7              (0x80UL << GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+#define GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00FF0000 */
+#define GNPTXSTS_NPTQXSAV                GNPTXSTS_NPTQXSAV_Msk                    /*!< Nonperiodic transmit request queue space available */
+#define GNPTXSTS_NPTQXSAV_0              (0x01UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00010000 */
+#define GNPTXSTS_NPTQXSAV_1              (0x02UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00020000 */
+#define GNPTXSTS_NPTQXSAV_2              (0x04UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00040000 */
+#define GNPTXSTS_NPTQXSAV_3              (0x08UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00080000 */
+#define GNPTXSTS_NPTQXSAV_4              (0x10UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00100000 */
+#define GNPTXSTS_NPTQXSAV_5              (0x20UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00200000 */
+#define GNPTXSTS_NPTQXSAV_6              (0x40UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00400000 */
+#define GNPTXSTS_NPTQXSAV_7              (0x80UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00800000 */
 
 #define GNPTXSTS_NPTXQTOP_Pos            (24U)
-#define GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
-#define GNPTXSTS_NPTXQTOP                GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
-#define GNPTXSTS_NPTXQTOP_0              (0x01UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
-#define GNPTXSTS_NPTXQTOP_1              (0x02UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
-#define GNPTXSTS_NPTXQTOP_2              (0x04UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
-#define GNPTXSTS_NPTXQTOP_3              (0x08UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
-#define GNPTXSTS_NPTXQTOP_4              (0x10UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
-#define GNPTXSTS_NPTXQTOP_5              (0x20UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
-#define GNPTXSTS_NPTXQTOP_6              (0x40UL << GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+#define GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x7F000000 */
+#define GNPTXSTS_NPTXQTOP                GNPTXSTS_NPTXQTOP_Msk                    /*!< Top of the nonperiodic transmit request queue */
+#define GNPTXSTS_NPTXQTOP_0              (0x01UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x01000000 */
+#define GNPTXSTS_NPTXQTOP_1              (0x02UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x02000000 */
+#define GNPTXSTS_NPTXQTOP_2              (0x04UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x04000000 */
+#define GNPTXSTS_NPTXQTOP_3              (0x08UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x08000000 */
+#define GNPTXSTS_NPTXQTOP_4              (0x10UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x10000000 */
+#define GNPTXSTS_NPTXQTOP_5              (0x20UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x20000000 */
+#define GNPTXSTS_NPTXQTOP_6              (0x40UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x40000000 */
 
 /********************  Bit definition for DTHRCTL register  ********************/
 #define DTHRCTL_NONISOTHREN_Pos          (0U)
-#define DTHRCTL_NONISOTHREN_Msk          (0x1UL << DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
-#define DTHRCTL_NONISOTHREN              DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define DTHRCTL_NONISOTHREN_Msk          (0x1UL << DTHRCTL_NONISOTHREN_Pos)       /*!< 0x00000001 */
+#define DTHRCTL_NONISOTHREN              DTHRCTL_NONISOTHREN_Msk                  /*!< Nonisochronous IN endpoints threshold enable */
 #define DTHRCTL_ISOTHREN_Pos             (1U)
-#define DTHRCTL_ISOTHREN_Msk             (0x1UL << DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
-#define DTHRCTL_ISOTHREN                 DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+#define DTHRCTL_ISOTHREN_Msk             (0x1UL << DTHRCTL_ISOTHREN_Pos)          /*!< 0x00000002 */
+#define DTHRCTL_ISOTHREN                 DTHRCTL_ISOTHREN_Msk                     /*!< ISO IN endpoint threshold enable */
 
 #define DTHRCTL_TXTHRLEN_Pos             (2U)
-#define DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
-#define DTHRCTL_TXTHRLEN                 DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
-#define DTHRCTL_TXTHRLEN_0               (0x001UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
-#define DTHRCTL_TXTHRLEN_1               (0x002UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
-#define DTHRCTL_TXTHRLEN_2               (0x004UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
-#define DTHRCTL_TXTHRLEN_3               (0x008UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
-#define DTHRCTL_TXTHRLEN_4               (0x010UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
-#define DTHRCTL_TXTHRLEN_5               (0x020UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
-#define DTHRCTL_TXTHRLEN_6               (0x040UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
-#define DTHRCTL_TXTHRLEN_7               (0x080UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
-#define DTHRCTL_TXTHRLEN_8               (0x100UL << DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x000007FC */
+#define DTHRCTL_TXTHRLEN                 DTHRCTL_TXTHRLEN_Msk                     /*!< Transmit threshold length */
+#define DTHRCTL_TXTHRLEN_0               (0x001UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000004 */
+#define DTHRCTL_TXTHRLEN_1               (0x002UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000008 */
+#define DTHRCTL_TXTHRLEN_2               (0x004UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000010 */
+#define DTHRCTL_TXTHRLEN_3               (0x008UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000020 */
+#define DTHRCTL_TXTHRLEN_4               (0x010UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000040 */
+#define DTHRCTL_TXTHRLEN_5               (0x020UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000080 */
+#define DTHRCTL_TXTHRLEN_6               (0x040UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000100 */
+#define DTHRCTL_TXTHRLEN_7               (0x080UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000200 */
+#define DTHRCTL_TXTHRLEN_8               (0x100UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000400 */
 #define DTHRCTL_RXTHREN_Pos              (16U)
-#define DTHRCTL_RXTHREN_Msk              (0x1UL << DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
-#define DTHRCTL_RXTHREN                  DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+#define DTHRCTL_RXTHREN_Msk              (0x1UL << DTHRCTL_RXTHREN_Pos)           /*!< 0x00010000 */
+#define DTHRCTL_RXTHREN                  DTHRCTL_RXTHREN_Msk                      /*!< Receive threshold enable */
 
 #define DTHRCTL_RXTHRLEN_Pos             (17U)
-#define DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
-#define DTHRCTL_RXTHRLEN                 DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
-#define DTHRCTL_RXTHRLEN_0               (0x001UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
-#define DTHRCTL_RXTHRLEN_1               (0x002UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
-#define DTHRCTL_RXTHRLEN_2               (0x004UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
-#define DTHRCTL_RXTHRLEN_3               (0x008UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
-#define DTHRCTL_RXTHRLEN_4               (0x010UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
-#define DTHRCTL_RXTHRLEN_5               (0x020UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
-#define DTHRCTL_RXTHRLEN_6               (0x040UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
-#define DTHRCTL_RXTHRLEN_7               (0x080UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
-#define DTHRCTL_RXTHRLEN_8               (0x100UL << DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x03FE0000 */
+#define DTHRCTL_RXTHRLEN                 DTHRCTL_RXTHRLEN_Msk                     /*!< Receive threshold length */
+#define DTHRCTL_RXTHRLEN_0               (0x001UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00020000 */
+#define DTHRCTL_RXTHRLEN_1               (0x002UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00040000 */
+#define DTHRCTL_RXTHRLEN_2               (0x004UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00080000 */
+#define DTHRCTL_RXTHRLEN_3               (0x008UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00100000 */
+#define DTHRCTL_RXTHRLEN_4               (0x010UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00200000 */
+#define DTHRCTL_RXTHRLEN_5               (0x020UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00400000 */
+#define DTHRCTL_RXTHRLEN_6               (0x040UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00800000 */
+#define DTHRCTL_RXTHRLEN_7               (0x080UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x01000000 */
+#define DTHRCTL_RXTHRLEN_8               (0x100UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x02000000 */
 #define DTHRCTL_ARPEN_Pos                (27U)
-#define DTHRCTL_ARPEN_Msk                (0x1UL << DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
-#define DTHRCTL_ARPEN                    DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+#define DTHRCTL_ARPEN_Msk                (0x1UL << DTHRCTL_ARPEN_Pos)             /*!< 0x08000000 */
+#define DTHRCTL_ARPEN                    DTHRCTL_ARPEN_Msk                        /*!< Arbiter parking enable */
 
 /********************  Bit definition for DIEPEMPMSK register  ********************/
 #define DIEPEMPMSK_INEPTXFEM_Pos         (0U)
-#define DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
-#define DIEPEMPMSK_INEPTXFEM             DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos)   /*!< 0x0000FFFF */
+#define DIEPEMPMSK_INEPTXFEM             DIEPEMPMSK_INEPTXFEM_Msk                 /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition for DEACHINT register  ********************/
 #define DEACHINT_IEP1INT_Pos             (1U)
-#define DEACHINT_IEP1INT_Msk             (0x1UL << DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
-#define DEACHINT_IEP1INT                 DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define DEACHINT_IEP1INT_Msk             (0x1UL << DEACHINT_IEP1INT_Pos)          /*!< 0x00000002 */
+#define DEACHINT_IEP1INT                 DEACHINT_IEP1INT_Msk                     /*!< IN endpoint 1interrupt bit   */
 #define DEACHINT_OEP1INT_Pos             (17U)
-#define DEACHINT_OEP1INT_Msk             (0x1UL << DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
-#define DEACHINT_OEP1INT                 DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+#define DEACHINT_OEP1INT_Msk             (0x1UL << DEACHINT_OEP1INT_Pos)          /*!< 0x00020000 */
+#define DEACHINT_OEP1INT                 DEACHINT_OEP1INT_Msk                     /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition for GCCFG register  ********************/
 #define GCCFG_DCDET_Pos                  (0U)
-#define GCCFG_DCDET_Msk                  (0x1UL << GCCFG_DCDET_Pos) /*!< 0x00000001 */
-#define GCCFG_DCDET                      GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define GCCFG_DCDET_Msk                  (0x1UL << GCCFG_DCDET_Pos)               /*!< 0x00000001 */
+#define GCCFG_DCDET                      GCCFG_DCDET_Msk                          /*!< Data contact detection (DCD) status */
 #define GCCFG_PDET_Pos                   (1U)
-#define GCCFG_PDET_Msk                   (0x1UL << GCCFG_PDET_Pos) /*!< 0x00000002 */
-#define GCCFG_PDET                       GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define GCCFG_PDET_Msk                   (0x1UL << GCCFG_PDET_Pos)                /*!< 0x00000002 */
+#define GCCFG_PDET                       GCCFG_PDET_Msk                           /*!< Primary detection (PD) status */
 #define GCCFG_SDET_Pos                   (2U)
-#define GCCFG_SDET_Msk                   (0x1UL << GCCFG_SDET_Pos) /*!< 0x00000004 */
-#define GCCFG_SDET                       GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define GCCFG_SDET_Msk                   (0x1UL << GCCFG_SDET_Pos)                /*!< 0x00000004 */
+#define GCCFG_SDET                       GCCFG_SDET_Msk                           /*!< Secondary detection (SD) status */
 #define GCCFG_PS2DET_Pos                 (3U)
-#define GCCFG_PS2DET_Msk                 (0x1UL << GCCFG_PS2DET_Pos) /*!< 0x00000008 */
-#define GCCFG_PS2DET                     GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define GCCFG_PS2DET_Msk                 (0x1UL << GCCFG_PS2DET_Pos)              /*!< 0x00000008 */
+#define GCCFG_PS2DET                     GCCFG_PS2DET_Msk                         /*!< DM pull-up detection status */
 #define GCCFG_PWRDWN_Pos                 (16U)
-#define GCCFG_PWRDWN_Msk                 (0x1UL << GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
-#define GCCFG_PWRDWN                     GCCFG_PWRDWN_Msk      /*!< Power down */
+#define GCCFG_PWRDWN_Msk                 (0x1UL << GCCFG_PWRDWN_Pos)              /*!< 0x00010000 */
+#define GCCFG_PWRDWN                     GCCFG_PWRDWN_Msk                         /*!< Power down */
 #define GCCFG_BCDEN_Pos                  (17U)
-#define GCCFG_BCDEN_Msk                  (0x1UL << GCCFG_BCDEN_Pos) /*!< 0x00020000 */
-#define GCCFG_BCDEN                      GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define GCCFG_BCDEN_Msk                  (0x1UL << GCCFG_BCDEN_Pos)               /*!< 0x00020000 */
+#define GCCFG_BCDEN                      GCCFG_BCDEN_Msk                          /*!< Battery charging detector (BCD) enable */
 #define GCCFG_DCDEN_Pos                  (18U)
-#define GCCFG_DCDEN_Msk                  (0x1UL << GCCFG_DCDEN_Pos) /*!< 0x00040000 */
-#define GCCFG_DCDEN                      GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define GCCFG_DCDEN_Msk                  (0x1UL << GCCFG_DCDEN_Pos)               /*!< 0x00040000 */
+#define GCCFG_DCDEN                      GCCFG_DCDEN_Msk                          /*!< Data contact detection (DCD) mode enable*/
 #define GCCFG_PDEN_Pos                   (19U)
-#define GCCFG_PDEN_Msk                   (0x1UL << GCCFG_PDEN_Pos) /*!< 0x00080000 */
-#define GCCFG_PDEN                       GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define GCCFG_PDEN_Msk                   (0x1UL << GCCFG_PDEN_Pos)                /*!< 0x00080000 */
+#define GCCFG_PDEN                       GCCFG_PDEN_Msk                           /*!< Primary detection (PD) mode enable*/
 #define GCCFG_SDEN_Pos                   (20U)
-#define GCCFG_SDEN_Msk                   (0x1UL << GCCFG_SDEN_Pos) /*!< 0x00100000 */
-#define GCCFG_SDEN                       GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define GCCFG_SDEN_Msk                   (0x1UL << GCCFG_SDEN_Pos)                /*!< 0x00100000 */
+#define GCCFG_SDEN                       GCCFG_SDEN_Msk                           /*!< Secondary detection (SD) mode enable */
 #define GCCFG_VBDEN_Pos                  (21U)
-#define GCCFG_VBDEN_Msk                  (0x1UL << GCCFG_VBDEN_Pos) /*!< 0x00200000 */
-#define GCCFG_VBDEN                      GCCFG_VBDEN_Msk       /*!< VBUS mode enable */
+#define GCCFG_VBDEN_Msk                  (0x1UL << GCCFG_VBDEN_Pos)               /*!< 0x00200000 */
+#define GCCFG_VBDEN                      GCCFG_VBDEN_Msk                          /*!< VBUS mode enable */
 #define GCCFG_OTGIDEN_Pos                (22U)
-#define GCCFG_OTGIDEN_Msk                (0x1UL << GCCFG_OTGIDEN_Pos) /*!< 0x00400000 */
-#define GCCFG_OTGIDEN                    GCCFG_OTGIDEN_Msk     /*!< OTG Id enable */
+#define GCCFG_OTGIDEN_Msk                (0x1UL << GCCFG_OTGIDEN_Pos)             /*!< 0x00400000 */
+#define GCCFG_OTGIDEN                    GCCFG_OTGIDEN_Msk                        /*!< OTG Id enable */
 #define GCCFG_PHYHSEN_Pos                (23U)
-#define GCCFG_PHYHSEN_Msk                (0x1UL << GCCFG_PHYHSEN_Pos) /*!< 0x00800000 */
-#define GCCFG_PHYHSEN                    GCCFG_PHYHSEN_Msk     /*!< HS PHY enable */
+#define GCCFG_PHYHSEN_Msk                (0x1UL << GCCFG_PHYHSEN_Pos)             /*!< 0x00800000 */
+#define GCCFG_PHYHSEN                    GCCFG_PHYHSEN_Msk                        /*!< HS PHY enable */
 
 /********************  Bit definition for DEACHINTMSK register  ********************/
 #define DEACHINTMSK_IEP1INTM_Pos         (1U)
-#define DEACHINTMSK_IEP1INTM_Msk         (0x1UL << DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
-#define DEACHINTMSK_IEP1INTM             DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define DEACHINTMSK_IEP1INTM_Msk         (0x1UL << DEACHINTMSK_IEP1INTM_Pos)      /*!< 0x00000002 */
+#define DEACHINTMSK_IEP1INTM             DEACHINTMSK_IEP1INTM_Msk                 /*!< IN Endpoint 1 interrupt mask bit  */
 #define DEACHINTMSK_OEP1INTM_Pos         (17U)
-#define DEACHINTMSK_OEP1INTM_Msk         (0x1UL << DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
-#define DEACHINTMSK_OEP1INTM             DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+#define DEACHINTMSK_OEP1INTM_Msk         (0x1UL << DEACHINTMSK_OEP1INTM_Pos)      /*!< 0x00020000 */
+#define DEACHINTMSK_OEP1INTM             DEACHINTMSK_OEP1INTM_Msk                 /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition for CID register  ********************/
 #define CID_PRODUCT_ID_Pos               (0U)
-#define CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
-#define CID_PRODUCT_ID                   CID_PRODUCT_ID_Msk    /*!< Product ID field */
+#define CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos)     /*!< 0xFFFFFFFF */
+#define CID_PRODUCT_ID                   CID_PRODUCT_ID_Msk                       /*!< Product ID field */
 
 /********************  Bit definition for GLPMCFG register  ********************/
 #define GLPMCFG_LPMEN_Pos                (0U)
-#define GLPMCFG_LPMEN_Msk                (0x1UL << GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
-#define GLPMCFG_LPMEN                    GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define GLPMCFG_LPMEN_Msk                (0x1UL << GLPMCFG_LPMEN_Pos)             /*!< 0x00000001 */
+#define GLPMCFG_LPMEN                    GLPMCFG_LPMEN_Msk                        /*!< LPM support enable                                     */
 #define GLPMCFG_LPMACK_Pos               (1U)
-#define GLPMCFG_LPMACK_Msk               (0x1UL << GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
-#define GLPMCFG_LPMACK                   GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define GLPMCFG_LPMACK_Msk               (0x1UL << GLPMCFG_LPMACK_Pos)            /*!< 0x00000002 */
+#define GLPMCFG_LPMACK                   GLPMCFG_LPMACK_Msk                       /*!< LPM Token acknowledge enable                           */
 #define GLPMCFG_BESL_Pos                 (2U)
-#define GLPMCFG_BESL_Msk                 (0xFUL << GLPMCFG_BESL_Pos) /*!< 0x0000003C */
-#define GLPMCFG_BESL                     GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define GLPMCFG_BESL_Msk                 (0xFUL << GLPMCFG_BESL_Pos)              /*!< 0x0000003C */
+#define GLPMCFG_BESL                     GLPMCFG_BESL_Msk                         /*!< BESL value received with last ACKed LPM Token          */
 #define GLPMCFG_REMWAKE_Pos              (6U)
-#define GLPMCFG_REMWAKE_Msk              (0x1UL << GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
-#define GLPMCFG_REMWAKE                  GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define GLPMCFG_REMWAKE_Msk              (0x1UL << GLPMCFG_REMWAKE_Pos)           /*!< 0x00000040 */
+#define GLPMCFG_REMWAKE                  GLPMCFG_REMWAKE_Msk                      /*!< bRemoteWake value received with last ACKed LPM Token   */
 #define GLPMCFG_L1SSEN_Pos               (7U)
-#define GLPMCFG_L1SSEN_Msk               (0x1UL << GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
-#define GLPMCFG_L1SSEN                   GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define GLPMCFG_L1SSEN_Msk               (0x1UL << GLPMCFG_L1SSEN_Pos)            /*!< 0x00000080 */
+#define GLPMCFG_L1SSEN                   GLPMCFG_L1SSEN_Msk                       /*!< L1 shallow sleep enable                                */
 #define GLPMCFG_BESLTHRS_Pos             (8U)
-#define GLPMCFG_BESLTHRS_Msk             (0xFUL << GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
-#define GLPMCFG_BESLTHRS                 GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define GLPMCFG_BESLTHRS_Msk             (0xFUL << GLPMCFG_BESLTHRS_Pos)          /*!< 0x00000F00 */
+#define GLPMCFG_BESLTHRS                 GLPMCFG_BESLTHRS_Msk                     /*!< BESL threshold                                         */
 #define GLPMCFG_L1DSEN_Pos               (12U)
-#define GLPMCFG_L1DSEN_Msk               (0x1UL << GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
-#define GLPMCFG_L1DSEN                   GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define GLPMCFG_L1DSEN_Msk               (0x1UL << GLPMCFG_L1DSEN_Pos)            /*!< 0x00001000 */
+#define GLPMCFG_L1DSEN                   GLPMCFG_L1DSEN_Msk                       /*!< L1 deep sleep enable                                   */
 #define GLPMCFG_LPMRSP_Pos               (13U)
-#define GLPMCFG_LPMRSP_Msk               (0x3UL << GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
-#define GLPMCFG_LPMRSP                   GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define GLPMCFG_LPMRSP_Msk               (0x3UL << GLPMCFG_LPMRSP_Pos)            /*!< 0x00006000 */
+#define GLPMCFG_LPMRSP                   GLPMCFG_LPMRSP_Msk                       /*!< LPM response                                           */
 #define GLPMCFG_SLPSTS_Pos               (15U)
-#define GLPMCFG_SLPSTS_Msk               (0x1UL << GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
-#define GLPMCFG_SLPSTS                   GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define GLPMCFG_SLPSTS_Msk               (0x1UL << GLPMCFG_SLPSTS_Pos)            /*!< 0x00008000 */
+#define GLPMCFG_SLPSTS                   GLPMCFG_SLPSTS_Msk                       /*!< Port sleep status                                      */
 #define GLPMCFG_L1RSMOK_Pos              (16U)
-#define GLPMCFG_L1RSMOK_Msk              (0x1UL << GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
-#define GLPMCFG_L1RSMOK                  GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define GLPMCFG_L1RSMOK_Msk              (0x1UL << GLPMCFG_L1RSMOK_Pos)           /*!< 0x00010000 */
+#define GLPMCFG_L1RSMOK                  GLPMCFG_L1RSMOK_Msk                      /*!< Sleep State Resume OK                                  */
 #define GLPMCFG_LPMCHIDX_Pos             (17U)
-#define GLPMCFG_LPMCHIDX_Msk             (0xFUL << GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
-#define GLPMCFG_LPMCHIDX                 GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define GLPMCFG_LPMCHIDX_Msk             (0xFUL << GLPMCFG_LPMCHIDX_Pos)          /*!< 0x001E0000 */
+#define GLPMCFG_LPMCHIDX                 GLPMCFG_LPMCHIDX_Msk                     /*!< LPM Channel Index                                      */
 #define GLPMCFG_LPMRCNT_Pos              (21U)
-#define GLPMCFG_LPMRCNT_Msk              (0x7UL << GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
-#define GLPMCFG_LPMRCNT                  GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define GLPMCFG_LPMRCNT_Msk              (0x7UL << GLPMCFG_LPMRCNT_Pos)           /*!< 0x00E00000 */
+#define GLPMCFG_LPMRCNT                  GLPMCFG_LPMRCNT_Msk                      /*!< LPM retry count                                        */
 #define GLPMCFG_SNDLPM_Pos               (24U)
-#define GLPMCFG_SNDLPM_Msk               (0x1UL << GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
-#define GLPMCFG_SNDLPM                   GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define GLPMCFG_SNDLPM_Msk               (0x1UL << GLPMCFG_SNDLPM_Pos)            /*!< 0x01000000 */
+#define GLPMCFG_SNDLPM                   GLPMCFG_SNDLPM_Msk                       /*!< Send LPM transaction                                   */
 #define GLPMCFG_LPMRCNTSTS_Pos           (25U)
-#define GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
-#define GLPMCFG_LPMRCNTSTS               GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << GLPMCFG_LPMRCNTSTS_Pos)        /*!< 0x0E000000 */
+#define GLPMCFG_LPMRCNTSTS               GLPMCFG_LPMRCNTSTS_Msk                   /*!< LPM retry count status                                 */
 #define GLPMCFG_ENBESL_Pos               (28U)
-#define GLPMCFG_ENBESL_Msk               (0x1UL << GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
-#define GLPMCFG_ENBESL                   GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+#define GLPMCFG_ENBESL_Msk               (0x1UL << GLPMCFG_ENBESL_Pos)            /*!< 0x10000000 */
+#define GLPMCFG_ENBESL                   GLPMCFG_ENBESL_Msk                       /*!< Enable best effort service latency                     */
 
 /********************  Bit definition for DIEPEACHMSK1 register  ********************/
 #define DIEPEACHMSK1_XFRCM_Pos           (0U)
-#define DIEPEACHMSK1_XFRCM_Msk           (0x1UL << DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define DIEPEACHMSK1_XFRCM               DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define DIEPEACHMSK1_XFRCM_Msk           (0x1UL << DIEPEACHMSK1_XFRCM_Pos)        /*!< 0x00000001 */
+#define DIEPEACHMSK1_XFRCM               DIEPEACHMSK1_XFRCM_Msk                   /*!< Transfer completed interrupt mask                 */
 #define DIEPEACHMSK1_EPDM_Pos            (1U)
-#define DIEPEACHMSK1_EPDM_Msk            (0x1UL << DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define DIEPEACHMSK1_EPDM                DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define DIEPEACHMSK1_EPDM_Msk            (0x1UL << DIEPEACHMSK1_EPDM_Pos)         /*!< 0x00000002 */
+#define DIEPEACHMSK1_EPDM                DIEPEACHMSK1_EPDM_Msk                    /*!< Endpoint disabled interrupt mask                  */
 #define DIEPEACHMSK1_TOM_Pos             (3U)
-#define DIEPEACHMSK1_TOM_Msk             (0x1UL << DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define DIEPEACHMSK1_TOM                 DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define DIEPEACHMSK1_TOM_Msk             (0x1UL << DIEPEACHMSK1_TOM_Pos)          /*!< 0x00000008 */
+#define DIEPEACHMSK1_TOM                 DIEPEACHMSK1_TOM_Msk                     /*!< Timeout condition mask (nonisochronous endpoints) */
 #define DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
-#define DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define DIEPEACHMSK1_ITTXFEMSK           DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos)    /*!< 0x00000010 */
+#define DIEPEACHMSK1_ITTXFEMSK           DIEPEACHMSK1_ITTXFEMSK_Msk               /*!< IN token received when TxFIFO empty mask          */
 #define DIEPEACHMSK1_INEPNMM_Pos         (5U)
-#define DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define DIEPEACHMSK1_INEPNMM             DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << DIEPEACHMSK1_INEPNMM_Pos)      /*!< 0x00000020 */
+#define DIEPEACHMSK1_INEPNMM             DIEPEACHMSK1_INEPNMM_Msk                 /*!< IN token received with EP mismatch mask           */
 #define DIEPEACHMSK1_INEPNEM_Pos         (6U)
-#define DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define DIEPEACHMSK1_INEPNEM             DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << DIEPEACHMSK1_INEPNEM_Pos)      /*!< 0x00000040 */
+#define DIEPEACHMSK1_INEPNEM             DIEPEACHMSK1_INEPNEM_Msk                 /*!< IN endpoint NAK effective mask                    */
 #define DIEPEACHMSK1_TXFURM_Pos          (8U)
-#define DIEPEACHMSK1_TXFURM_Msk          (0x1UL << DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define DIEPEACHMSK1_TXFURM              DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
+#define DIEPEACHMSK1_TXFURM_Msk          (0x1UL << DIEPEACHMSK1_TXFURM_Pos)       /*!< 0x00000100 */
+#define DIEPEACHMSK1_TXFURM              DIEPEACHMSK1_TXFURM_Msk                  /*!< FIFO underrun mask                                */
 #define DIEPEACHMSK1_BIM_Pos             (9U)
-#define DIEPEACHMSK1_BIM_Msk             (0x1UL << DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define DIEPEACHMSK1_BIM                 DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
+#define DIEPEACHMSK1_BIM_Msk             (0x1UL << DIEPEACHMSK1_BIM_Pos)          /*!< 0x00000200 */
+#define DIEPEACHMSK1_BIM                 DIEPEACHMSK1_BIM_Msk                     /*!< BNA interrupt mask                                */
 #define DIEPEACHMSK1_NAKM_Pos            (13U)
-#define DIEPEACHMSK1_NAKM_Msk            (0x1UL << DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define DIEPEACHMSK1_NAKM                DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
+#define DIEPEACHMSK1_NAKM_Msk            (0x1UL << DIEPEACHMSK1_NAKM_Pos)         /*!< 0x00002000 */
+#define DIEPEACHMSK1_NAKM                DIEPEACHMSK1_NAKM_Msk                    /*!< NAK interrupt mask                                */
 
 /********************  Bit definition for HPRT register  ********************/
 #define HPRT_PCSTS_Pos                   (0U)
-#define HPRT_PCSTS_Msk                   (0x1UL << HPRT_PCSTS_Pos) /*!< 0x00000001 */
-#define HPRT_PCSTS                       HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define HPRT_PCSTS_Msk                   (0x1UL << HPRT_PCSTS_Pos)                /*!< 0x00000001 */
+#define HPRT_PCSTS                       HPRT_PCSTS_Msk                           /*!< Port connect status        */
 #define HPRT_PCDET_Pos                   (1U)
-#define HPRT_PCDET_Msk                   (0x1UL << HPRT_PCDET_Pos) /*!< 0x00000002 */
-#define HPRT_PCDET                       HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define HPRT_PCDET_Msk                   (0x1UL << HPRT_PCDET_Pos)                /*!< 0x00000002 */
+#define HPRT_PCDET                       HPRT_PCDET_Msk                           /*!< Port connect detected      */
 #define HPRT_PENA_Pos                    (2U)
-#define HPRT_PENA_Msk                    (0x1UL << HPRT_PENA_Pos) /*!< 0x00000004 */
-#define HPRT_PENA                        HPRT_PENA_Msk         /*!< Port enable                */
+#define HPRT_PENA_Msk                    (0x1UL << HPRT_PENA_Pos)                 /*!< 0x00000004 */
+#define HPRT_PENA                        HPRT_PENA_Msk                            /*!< Port enable                */
 #define HPRT_PENCHNG_Pos                 (3U)
-#define HPRT_PENCHNG_Msk                 (0x1UL << HPRT_PENCHNG_Pos) /*!< 0x00000008 */
-#define HPRT_PENCHNG                     HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define HPRT_PENCHNG_Msk                 (0x1UL << HPRT_PENCHNG_Pos)              /*!< 0x00000008 */
+#define HPRT_PENCHNG                     HPRT_PENCHNG_Msk                         /*!< Port enable/disable change */
 #define HPRT_POCA_Pos                    (4U)
-#define HPRT_POCA_Msk                    (0x1UL << HPRT_POCA_Pos) /*!< 0x00000010 */
-#define HPRT_POCA                        HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define HPRT_POCA_Msk                    (0x1UL << HPRT_POCA_Pos)                 /*!< 0x00000010 */
+#define HPRT_POCA                        HPRT_POCA_Msk                            /*!< Port overcurrent active    */
 #define HPRT_POCCHNG_Pos                 (5U)
-#define HPRT_POCCHNG_Msk                 (0x1UL << HPRT_POCCHNG_Pos) /*!< 0x00000020 */
-#define HPRT_POCCHNG                     HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define HPRT_POCCHNG_Msk                 (0x1UL << HPRT_POCCHNG_Pos)              /*!< 0x00000020 */
+#define HPRT_POCCHNG                     HPRT_POCCHNG_Msk                         /*!< Port overcurrent change    */
 #define HPRT_PRES_Pos                    (6U)
-#define HPRT_PRES_Msk                    (0x1UL << HPRT_PRES_Pos) /*!< 0x00000040 */
-#define HPRT_PRES                        HPRT_PRES_Msk         /*!< Port resume                */
+#define HPRT_PRES_Msk                    (0x1UL << HPRT_PRES_Pos)                 /*!< 0x00000040 */
+#define HPRT_PRES                        HPRT_PRES_Msk                            /*!< Port resume                */
 #define HPRT_PSUSP_Pos                   (7U)
-#define HPRT_PSUSP_Msk                   (0x1UL << HPRT_PSUSP_Pos) /*!< 0x00000080 */
-#define HPRT_PSUSP                       HPRT_PSUSP_Msk        /*!< Port suspend               */
+#define HPRT_PSUSP_Msk                   (0x1UL << HPRT_PSUSP_Pos)                /*!< 0x00000080 */
+#define HPRT_PSUSP                       HPRT_PSUSP_Msk                           /*!< Port suspend               */
 #define HPRT_PRST_Pos                    (8U)
-#define HPRT_PRST_Msk                    (0x1UL << HPRT_PRST_Pos) /*!< 0x00000100 */
-#define HPRT_PRST                        HPRT_PRST_Msk         /*!< Port reset                 */
+#define HPRT_PRST_Msk                    (0x1UL << HPRT_PRST_Pos)                 /*!< 0x00000100 */
+#define HPRT_PRST                        HPRT_PRST_Msk                            /*!< Port reset                 */
 
 #define HPRT_PLSTS_Pos                   (10U)
-#define HPRT_PLSTS_Msk                   (0x3UL << HPRT_PLSTS_Pos) /*!< 0x00000C00 */
-#define HPRT_PLSTS                       HPRT_PLSTS_Msk        /*!< Port line status           */
-#define HPRT_PLSTS_0                     (0x1UL << HPRT_PLSTS_Pos) /*!< 0x00000400 */
-#define HPRT_PLSTS_1                     (0x2UL << HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define HPRT_PLSTS_Msk                   (0x3UL << HPRT_PLSTS_Pos)                /*!< 0x00000C00 */
+#define HPRT_PLSTS                       HPRT_PLSTS_Msk                           /*!< Port line status           */
+#define HPRT_PLSTS_0                     (0x1UL << HPRT_PLSTS_Pos)                /*!< 0x00000400 */
+#define HPRT_PLSTS_1                     (0x2UL << HPRT_PLSTS_Pos)                /*!< 0x00000800 */
 #define HPRT_PPWR_Pos                    (12U)
-#define HPRT_PPWR_Msk                    (0x1UL << HPRT_PPWR_Pos) /*!< 0x00001000 */
-#define HPRT_PPWR                        HPRT_PPWR_Msk         /*!< Port power                 */
+#define HPRT_PPWR_Msk                    (0x1UL << HPRT_PPWR_Pos)                 /*!< 0x00001000 */
+#define HPRT_PPWR                        HPRT_PPWR_Msk                            /*!< Port power                 */
 
 #define HPRT_PTCTL_Pos                   (13U)
-#define HPRT_PTCTL_Msk                   (0xFUL << HPRT_PTCTL_Pos) /*!< 0x0001E000 */
-#define HPRT_PTCTL                       HPRT_PTCTL_Msk        /*!< Port test control          */
-#define HPRT_PTCTL_0                     (0x1UL << HPRT_PTCTL_Pos) /*!< 0x00002000 */
-#define HPRT_PTCTL_1                     (0x2UL << HPRT_PTCTL_Pos) /*!< 0x00004000 */
-#define HPRT_PTCTL_2                     (0x4UL << HPRT_PTCTL_Pos) /*!< 0x00008000 */
-#define HPRT_PTCTL_3                     (0x8UL << HPRT_PTCTL_Pos) /*!< 0x00010000 */
+#define HPRT_PTCTL_Msk                   (0xFUL << HPRT_PTCTL_Pos)                /*!< 0x0001E000 */
+#define HPRT_PTCTL                       HPRT_PTCTL_Msk                           /*!< Port test control          */
+#define HPRT_PTCTL_0                     (0x1UL << HPRT_PTCTL_Pos)                /*!< 0x00002000 */
+#define HPRT_PTCTL_1                     (0x2UL << HPRT_PTCTL_Pos)                /*!< 0x00004000 */
+#define HPRT_PTCTL_2                     (0x4UL << HPRT_PTCTL_Pos)                /*!< 0x00008000 */
+#define HPRT_PTCTL_3                     (0x8UL << HPRT_PTCTL_Pos)                /*!< 0x00010000 */
 
 #define HPRT_PSPD_Pos                    (17U)
-#define HPRT_PSPD_Msk                    (0x3UL << HPRT_PSPD_Pos) /*!< 0x00060000 */
-#define HPRT_PSPD                        HPRT_PSPD_Msk         /*!< Port speed                 */
-#define HPRT_PSPD_0                      (0x1UL << HPRT_PSPD_Pos) /*!< 0x00020000 */
-#define HPRT_PSPD_1                      (0x2UL << HPRT_PSPD_Pos) /*!< 0x00040000 */
+#define HPRT_PSPD_Msk                    (0x3UL << HPRT_PSPD_Pos)                 /*!< 0x00060000 */
+#define HPRT_PSPD                        HPRT_PSPD_Msk                            /*!< Port speed                 */
+#define HPRT_PSPD_0                      (0x1UL << HPRT_PSPD_Pos)                 /*!< 0x00020000 */
+#define HPRT_PSPD_1                      (0x2UL << HPRT_PSPD_Pos)                 /*!< 0x00040000 */
 
 /********************  Bit definition for DOEPEACHMSK1 register  ********************/
 #define DOEPEACHMSK1_XFRCM_Pos           (0U)
-#define DOEPEACHMSK1_XFRCM_Msk           (0x1UL << DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define DOEPEACHMSK1_XFRCM               DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
+#define DOEPEACHMSK1_XFRCM_Msk           (0x1UL << DOEPEACHMSK1_XFRCM_Pos)        /*!< 0x00000001 */
+#define DOEPEACHMSK1_XFRCM               DOEPEACHMSK1_XFRCM_Msk                   /*!< Transfer completed interrupt mask         */
 #define DOEPEACHMSK1_EPDM_Pos            (1U)
-#define DOEPEACHMSK1_EPDM_Msk            (0x1UL << DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define DOEPEACHMSK1_EPDM                DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
+#define DOEPEACHMSK1_EPDM_Msk            (0x1UL << DOEPEACHMSK1_EPDM_Pos)         /*!< 0x00000002 */
+#define DOEPEACHMSK1_EPDM                DOEPEACHMSK1_EPDM_Msk                    /*!< Endpoint disabled interrupt mask          */
 #define DOEPEACHMSK1_TOM_Pos             (3U)
-#define DOEPEACHMSK1_TOM_Msk             (0x1UL << DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define DOEPEACHMSK1_TOM                 DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
+#define DOEPEACHMSK1_TOM_Msk             (0x1UL << DOEPEACHMSK1_TOM_Pos)          /*!< 0x00000008 */
+#define DOEPEACHMSK1_TOM                 DOEPEACHMSK1_TOM_Msk                     /*!< Timeout condition mask                    */
 #define DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
-#define DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define DOEPEACHMSK1_ITTXFEMSK           DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
+#define DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos)    /*!< 0x00000010 */
+#define DOEPEACHMSK1_ITTXFEMSK           DOEPEACHMSK1_ITTXFEMSK_Msk               /*!< IN token received when TxFIFO empty mask  */
 #define DOEPEACHMSK1_INEPNMM_Pos         (5U)
-#define DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define DOEPEACHMSK1_INEPNMM             DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
+#define DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << DOEPEACHMSK1_INEPNMM_Pos)      /*!< 0x00000020 */
+#define DOEPEACHMSK1_INEPNMM             DOEPEACHMSK1_INEPNMM_Msk                 /*!< IN token received with EP mismatch mask   */
 #define DOEPEACHMSK1_INEPNEM_Pos         (6U)
-#define DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define DOEPEACHMSK1_INEPNEM             DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
+#define DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << DOEPEACHMSK1_INEPNEM_Pos)      /*!< 0x00000040 */
+#define DOEPEACHMSK1_INEPNEM             DOEPEACHMSK1_INEPNEM_Msk                 /*!< IN endpoint NAK effective mask            */
 #define DOEPEACHMSK1_TXFURM_Pos          (8U)
-#define DOEPEACHMSK1_TXFURM_Msk          (0x1UL << DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define DOEPEACHMSK1_TXFURM              DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
+#define DOEPEACHMSK1_TXFURM_Msk          (0x1UL << DOEPEACHMSK1_TXFURM_Pos)       /*!< 0x00000100 */
+#define DOEPEACHMSK1_TXFURM              DOEPEACHMSK1_TXFURM_Msk                  /*!< OUT packet error mask                     */
 #define DOEPEACHMSK1_BIM_Pos             (9U)
-#define DOEPEACHMSK1_BIM_Msk             (0x1UL << DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define DOEPEACHMSK1_BIM                 DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
+#define DOEPEACHMSK1_BIM_Msk             (0x1UL << DOEPEACHMSK1_BIM_Pos)          /*!< 0x00000200 */
+#define DOEPEACHMSK1_BIM                 DOEPEACHMSK1_BIM_Msk                     /*!< BNA interrupt mask                        */
 #define DOEPEACHMSK1_BERRM_Pos           (12U)
-#define DOEPEACHMSK1_BERRM_Msk           (0x1UL << DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
-#define DOEPEACHMSK1_BERRM               DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
+#define DOEPEACHMSK1_BERRM_Msk           (0x1UL << DOEPEACHMSK1_BERRM_Pos)        /*!< 0x00001000 */
+#define DOEPEACHMSK1_BERRM               DOEPEACHMSK1_BERRM_Msk                   /*!< Bubble error interrupt mask               */
 #define DOEPEACHMSK1_NAKM_Pos            (13U)
-#define DOEPEACHMSK1_NAKM_Msk            (0x1UL << DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define DOEPEACHMSK1_NAKM                DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
+#define DOEPEACHMSK1_NAKM_Msk            (0x1UL << DOEPEACHMSK1_NAKM_Pos)         /*!< 0x00002000 */
+#define DOEPEACHMSK1_NAKM                DOEPEACHMSK1_NAKM_Msk                    /*!< NAK interrupt mask                        */
 #define DOEPEACHMSK1_NYETM_Pos           (14U)
-#define DOEPEACHMSK1_NYETM_Msk           (0x1UL << DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
-#define DOEPEACHMSK1_NYETM               DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
+#define DOEPEACHMSK1_NYETM_Msk           (0x1UL << DOEPEACHMSK1_NYETM_Pos)        /*!< 0x00004000 */
+#define DOEPEACHMSK1_NYETM               DOEPEACHMSK1_NYETM_Msk                   /*!< NYET interrupt mask                       */
 
 /********************  Bit definition for HPTXFSIZ register  ********************/
 #define HPTXFSIZ_PTXSA_Pos               (0U)
-#define HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
-#define HPTXFSIZ_PTXSA                   HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
+#define HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << HPTXFSIZ_PTXSA_Pos)         /*!< 0x0000FFFF */
+#define HPTXFSIZ_PTXSA                   HPTXFSIZ_PTXSA_Msk                       /*!< Host periodic TxFIFO start address            */
 #define HPTXFSIZ_PTXFD_Pos               (16U)
-#define HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
-#define HPTXFSIZ_PTXFD                   HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
+#define HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << HPTXFSIZ_PTXFD_Pos)         /*!< 0xFFFF0000 */
+#define HPTXFSIZ_PTXFD                   HPTXFSIZ_PTXFD_Msk                       /*!< Host periodic TxFIFO depth                    */
 
 /********************  Bit definition for DIEPCTL register  ********************/
 #define DIEPCTL_MPSIZ_Pos                (0U)
-#define DIEPCTL_MPSIZ_Msk                (0x7FFUL << DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define DIEPCTL_MPSIZ                    DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
+#define DIEPCTL_MPSIZ_Msk                (0x7FFUL << DIEPCTL_MPSIZ_Pos)           /*!< 0x000007FF */
+#define DIEPCTL_MPSIZ                    DIEPCTL_MPSIZ_Msk                        /*!< Maximum packet size              */
 #define DIEPCTL_USBAEP_Pos               (15U)
-#define DIEPCTL_USBAEP_Msk               (0x1UL << DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define DIEPCTL_USBAEP                   DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
+#define DIEPCTL_USBAEP_Msk               (0x1UL << DIEPCTL_USBAEP_Pos)            /*!< 0x00008000 */
+#define DIEPCTL_USBAEP                   DIEPCTL_USBAEP_Msk                       /*!< USB active endpoint              */
 #define DIEPCTL_EONUM_DPID_Pos           (16U)
-#define DIEPCTL_EONUM_DPID_Msk           (0x1UL << DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
-#define DIEPCTL_EONUM_DPID               DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
+#define DIEPCTL_EONUM_DPID_Msk           (0x1UL << DIEPCTL_EONUM_DPID_Pos)        /*!< 0x00010000 */
+#define DIEPCTL_EONUM_DPID               DIEPCTL_EONUM_DPID_Msk                   /*!< Even/odd frame                   */
 #define DIEPCTL_NAKSTS_Pos               (17U)
-#define DIEPCTL_NAKSTS_Msk               (0x1UL << DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define DIEPCTL_NAKSTS                   DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
+#define DIEPCTL_NAKSTS_Msk               (0x1UL << DIEPCTL_NAKSTS_Pos)            /*!< 0x00020000 */
+#define DIEPCTL_NAKSTS                   DIEPCTL_NAKSTS_Msk                       /*!< NAK status                       */
 
 #define DIEPCTL_EPTYP_Pos                (18U)
-#define DIEPCTL_EPTYP_Msk                (0x3UL << DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define DIEPCTL_EPTYP                    DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
-#define DIEPCTL_EPTYP_0                  (0x1UL << DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define DIEPCTL_EPTYP_1                  (0x2UL << DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define DIEPCTL_EPTYP_Msk                (0x3UL << DIEPCTL_EPTYP_Pos)             /*!< 0x000C0000 */
+#define DIEPCTL_EPTYP                    DIEPCTL_EPTYP_Msk                        /*!< Endpoint type                    */
+#define DIEPCTL_EPTYP_0                  (0x1UL << DIEPCTL_EPTYP_Pos)             /*!< 0x00040000 */
+#define DIEPCTL_EPTYP_1                  (0x2UL << DIEPCTL_EPTYP_Pos)             /*!< 0x00080000 */
 #define DIEPCTL_STALL_Pos                (21U)
-#define DIEPCTL_STALL_Msk                (0x1UL << DIEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define DIEPCTL_STALL                    DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
+#define DIEPCTL_STALL_Msk                (0x1UL << DIEPCTL_STALL_Pos)             /*!< 0x00200000 */
+#define DIEPCTL_STALL                    DIEPCTL_STALL_Msk                        /*!< STALL handshake                  */
 
 #define DIEPCTL_TXFNUM_Pos               (22U)
-#define DIEPCTL_TXFNUM_Msk               (0xFUL << DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
-#define DIEPCTL_TXFNUM                   DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
-#define DIEPCTL_TXFNUM_0                 (0x1UL << DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
-#define DIEPCTL_TXFNUM_1                 (0x2UL << DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
-#define DIEPCTL_TXFNUM_2                 (0x4UL << DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
-#define DIEPCTL_TXFNUM_3                 (0x8UL << DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define DIEPCTL_TXFNUM_Msk               (0xFUL << DIEPCTL_TXFNUM_Pos)            /*!< 0x03C00000 */
+#define DIEPCTL_TXFNUM                   DIEPCTL_TXFNUM_Msk                       /*!< TxFIFO number                    */
+#define DIEPCTL_TXFNUM_0                 (0x1UL << DIEPCTL_TXFNUM_Pos)            /*!< 0x00400000 */
+#define DIEPCTL_TXFNUM_1                 (0x2UL << DIEPCTL_TXFNUM_Pos)            /*!< 0x00800000 */
+#define DIEPCTL_TXFNUM_2                 (0x4UL << DIEPCTL_TXFNUM_Pos)            /*!< 0x01000000 */
+#define DIEPCTL_TXFNUM_3                 (0x8UL << DIEPCTL_TXFNUM_Pos)            /*!< 0x02000000 */
 #define DIEPCTL_CNAK_Pos                 (26U)
-#define DIEPCTL_CNAK_Msk                 (0x1UL << DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define DIEPCTL_CNAK                     DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
+#define DIEPCTL_CNAK_Msk                 (0x1UL << DIEPCTL_CNAK_Pos)              /*!< 0x04000000 */
+#define DIEPCTL_CNAK                     DIEPCTL_CNAK_Msk                         /*!< Clear NAK                        */
 #define DIEPCTL_SNAK_Pos                 (27U)
-#define DIEPCTL_SNAK_Msk                 (0x1UL << DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define DIEPCTL_SNAK                     DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define DIEPCTL_SNAK_Msk                 (0x1UL << DIEPCTL_SNAK_Pos)              /*!< 0x08000000 */
+#define DIEPCTL_SNAK                     DIEPCTL_SNAK_Msk                         /*!< Set NAK */
 #define DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
-#define DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define DIEPCTL_SD0PID_SEVNFRM           DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
+#define DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos)    /*!< 0x10000000 */
+#define DIEPCTL_SD0PID_SEVNFRM           DIEPCTL_SD0PID_SEVNFRM_Msk               /*!< Set DATA0 PID                    */
 #define DIEPCTL_SODDFRM_Pos              (29U)
-#define DIEPCTL_SODDFRM_Msk              (0x1UL << DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define DIEPCTL_SODDFRM                  DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
+#define DIEPCTL_SODDFRM_Msk              (0x1UL << DIEPCTL_SODDFRM_Pos)           /*!< 0x20000000 */
+#define DIEPCTL_SODDFRM                  DIEPCTL_SODDFRM_Msk                      /*!< Set odd frame                    */
 #define DIEPCTL_EPDIS_Pos                (30U)
-#define DIEPCTL_EPDIS_Msk                (0x1UL << DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define DIEPCTL_EPDIS                    DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
+#define DIEPCTL_EPDIS_Msk                (0x1UL << DIEPCTL_EPDIS_Pos)             /*!< 0x40000000 */
+#define DIEPCTL_EPDIS                    DIEPCTL_EPDIS_Msk                        /*!< Endpoint disable                 */
 #define DIEPCTL_EPENA_Pos                (31U)
-#define DIEPCTL_EPENA_Msk                (0x1UL << DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define DIEPCTL_EPENA                    DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
+#define DIEPCTL_EPENA_Msk                (0x1UL << DIEPCTL_EPENA_Pos)             /*!< 0x80000000 */
+#define DIEPCTL_EPENA                    DIEPCTL_EPENA_Msk                        /*!< Endpoint enable                  */
 
 /********************  Bit definition for HCCHAR register  ********************/
 #define HCCHAR_MPSIZ_Pos                 (0U)
-#define HCCHAR_MPSIZ_Msk                 (0x7FFUL << HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
-#define HCCHAR_MPSIZ                     HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+#define HCCHAR_MPSIZ_Msk                 (0x7FFUL << HCCHAR_MPSIZ_Pos)            /*!< 0x000007FF */
+#define HCCHAR_MPSIZ                     HCCHAR_MPSIZ_Msk                         /*!< Maximum packet size */
 
 #define HCCHAR_EPNUM_Pos                 (11U)
-#define HCCHAR_EPNUM_Msk                 (0xFUL << HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
-#define HCCHAR_EPNUM                     HCCHAR_EPNUM_Msk      /*!< Endpoint number */
-#define HCCHAR_EPNUM_0                   (0x1UL << HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
-#define HCCHAR_EPNUM_1                   (0x2UL << HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
-#define HCCHAR_EPNUM_2                   (0x4UL << HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
-#define HCCHAR_EPNUM_3                   (0x8UL << HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define HCCHAR_EPNUM_Msk                 (0xFUL << HCCHAR_EPNUM_Pos)              /*!< 0x00007800 */
+#define HCCHAR_EPNUM                     HCCHAR_EPNUM_Msk                         /*!< Endpoint number */
+#define HCCHAR_EPNUM_0                   (0x1UL << HCCHAR_EPNUM_Pos)              /*!< 0x00000800 */
+#define HCCHAR_EPNUM_1                   (0x2UL << HCCHAR_EPNUM_Pos)              /*!< 0x00001000 */
+#define HCCHAR_EPNUM_2                   (0x4UL << HCCHAR_EPNUM_Pos)              /*!< 0x00002000 */
+#define HCCHAR_EPNUM_3                   (0x8UL << HCCHAR_EPNUM_Pos)              /*!< 0x00004000 */
 #define HCCHAR_EPDIR_Pos                 (15U)
-#define HCCHAR_EPDIR_Msk                 (0x1UL << HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
-#define HCCHAR_EPDIR                     HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define HCCHAR_EPDIR_Msk                 (0x1UL << HCCHAR_EPDIR_Pos)              /*!< 0x00008000 */
+#define HCCHAR_EPDIR                     HCCHAR_EPDIR_Msk                         /*!< Endpoint direction */
 #define HCCHAR_LSDEV_Pos                 (17U)
-#define HCCHAR_LSDEV_Msk                 (0x1UL << HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
-#define HCCHAR_LSDEV                     HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+#define HCCHAR_LSDEV_Msk                 (0x1UL << HCCHAR_LSDEV_Pos)              /*!< 0x00020000 */
+#define HCCHAR_LSDEV                     HCCHAR_LSDEV_Msk                         /*!< Low-speed device */
 
 #define HCCHAR_EPTYP_Pos                 (18U)
-#define HCCHAR_EPTYP_Msk                 (0x3UL << HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
-#define HCCHAR_EPTYP                     HCCHAR_EPTYP_Msk      /*!< Endpoint type */
-#define HCCHAR_EPTYP_0                   (0x1UL << HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
-#define HCCHAR_EPTYP_1                   (0x2UL << HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+#define HCCHAR_EPTYP_Msk                 (0x3UL << HCCHAR_EPTYP_Pos)              /*!< 0x000C0000 */
+#define HCCHAR_EPTYP                     HCCHAR_EPTYP_Msk                         /*!< Endpoint type */
+#define HCCHAR_EPTYP_0                   (0x1UL << HCCHAR_EPTYP_Pos)              /*!< 0x00040000 */
+#define HCCHAR_EPTYP_1                   (0x2UL << HCCHAR_EPTYP_Pos)              /*!< 0x00080000 */
 
 #define HCCHAR_MC_Pos                    (20U)
-#define HCCHAR_MC_Msk                    (0x3UL << HCCHAR_MC_Pos) /*!< 0x00300000 */
-#define HCCHAR_MC                        HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
-#define HCCHAR_MC_0                      (0x1UL << HCCHAR_MC_Pos) /*!< 0x00100000 */
-#define HCCHAR_MC_1                      (0x2UL << HCCHAR_MC_Pos) /*!< 0x00200000 */
+#define HCCHAR_MC_Msk                    (0x3UL << HCCHAR_MC_Pos)                 /*!< 0x00300000 */
+#define HCCHAR_MC                        HCCHAR_MC_Msk                            /*!< Multi Count (MC) / Error Count (EC) */
+#define HCCHAR_MC_0                      (0x1UL << HCCHAR_MC_Pos)                 /*!< 0x00100000 */
+#define HCCHAR_MC_1                      (0x2UL << HCCHAR_MC_Pos)                 /*!< 0x00200000 */
 
 #define HCCHAR_DAD_Pos                   (22U)
-#define HCCHAR_DAD_Msk                   (0x7FUL << HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
-#define HCCHAR_DAD                       HCCHAR_DAD_Msk        /*!< Device address */
-#define HCCHAR_DAD_0                     (0x01UL << HCCHAR_DAD_Pos) /*!< 0x00400000 */
-#define HCCHAR_DAD_1                     (0x02UL << HCCHAR_DAD_Pos) /*!< 0x00800000 */
-#define HCCHAR_DAD_2                     (0x04UL << HCCHAR_DAD_Pos) /*!< 0x01000000 */
-#define HCCHAR_DAD_3                     (0x08UL << HCCHAR_DAD_Pos) /*!< 0x02000000 */
-#define HCCHAR_DAD_4                     (0x10UL << HCCHAR_DAD_Pos) /*!< 0x04000000 */
-#define HCCHAR_DAD_5                     (0x20UL << HCCHAR_DAD_Pos) /*!< 0x08000000 */
-#define HCCHAR_DAD_6                     (0x40UL << HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define HCCHAR_DAD_Msk                   (0x7FUL << HCCHAR_DAD_Pos)               /*!< 0x1FC00000 */
+#define HCCHAR_DAD                       HCCHAR_DAD_Msk                           /*!< Device address */
+#define HCCHAR_DAD_0                     (0x01UL << HCCHAR_DAD_Pos)               /*!< 0x00400000 */
+#define HCCHAR_DAD_1                     (0x02UL << HCCHAR_DAD_Pos)               /*!< 0x00800000 */
+#define HCCHAR_DAD_2                     (0x04UL << HCCHAR_DAD_Pos)               /*!< 0x01000000 */
+#define HCCHAR_DAD_3                     (0x08UL << HCCHAR_DAD_Pos)               /*!< 0x02000000 */
+#define HCCHAR_DAD_4                     (0x10UL << HCCHAR_DAD_Pos)               /*!< 0x04000000 */
+#define HCCHAR_DAD_5                     (0x20UL << HCCHAR_DAD_Pos)               /*!< 0x08000000 */
+#define HCCHAR_DAD_6                     (0x40UL << HCCHAR_DAD_Pos)               /*!< 0x10000000 */
 #define HCCHAR_ODDFRM_Pos                (29U)
-#define HCCHAR_ODDFRM_Msk                (0x1UL << HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
-#define HCCHAR_ODDFRM                    HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define HCCHAR_ODDFRM_Msk                (0x1UL << HCCHAR_ODDFRM_Pos)             /*!< 0x20000000 */
+#define HCCHAR_ODDFRM                    HCCHAR_ODDFRM_Msk                        /*!< Odd frame */
 #define HCCHAR_CHDIS_Pos                 (30U)
-#define HCCHAR_CHDIS_Msk                 (0x1UL << HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
-#define HCCHAR_CHDIS                     HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define HCCHAR_CHDIS_Msk                 (0x1UL << HCCHAR_CHDIS_Pos)              /*!< 0x40000000 */
+#define HCCHAR_CHDIS                     HCCHAR_CHDIS_Msk                         /*!< Channel disable */
 #define HCCHAR_CHENA_Pos                 (31U)
-#define HCCHAR_CHENA_Msk                 (0x1UL << HCCHAR_CHENA_Pos) /*!< 0x80000000 */
-#define HCCHAR_CHENA                     HCCHAR_CHENA_Msk      /*!< Channel enable */
+#define HCCHAR_CHENA_Msk                 (0x1UL << HCCHAR_CHENA_Pos)              /*!< 0x80000000 */
+#define HCCHAR_CHENA                     HCCHAR_CHENA_Msk                         /*!< Channel enable */
 
 /********************  Bit definition for HCSPLT register  ********************/
 
 #define HCSPLT_PRTADDR_Pos               (0U)
-#define HCSPLT_PRTADDR_Msk               (0x7FUL << HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
-#define HCSPLT_PRTADDR                   HCSPLT_PRTADDR_Msk    /*!< Port address */
-#define HCSPLT_PRTADDR_0                 (0x01UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
-#define HCSPLT_PRTADDR_1                 (0x02UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
-#define HCSPLT_PRTADDR_2                 (0x04UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
-#define HCSPLT_PRTADDR_3                 (0x08UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
-#define HCSPLT_PRTADDR_4                 (0x10UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
-#define HCSPLT_PRTADDR_5                 (0x20UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
-#define HCSPLT_PRTADDR_6                 (0x40UL << HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+#define HCSPLT_PRTADDR_Msk               (0x7FUL << HCSPLT_PRTADDR_Pos)           /*!< 0x0000007F */
+#define HCSPLT_PRTADDR                   HCSPLT_PRTADDR_Msk                       /*!< Port address */
+#define HCSPLT_PRTADDR_0                 (0x01UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000001 */
+#define HCSPLT_PRTADDR_1                 (0x02UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000002 */
+#define HCSPLT_PRTADDR_2                 (0x04UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000004 */
+#define HCSPLT_PRTADDR_3                 (0x08UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000008 */
+#define HCSPLT_PRTADDR_4                 (0x10UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000010 */
+#define HCSPLT_PRTADDR_5                 (0x20UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000020 */
+#define HCSPLT_PRTADDR_6                 (0x40UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000040 */
 
 #define HCSPLT_HUBADDR_Pos               (7U)
-#define HCSPLT_HUBADDR_Msk               (0x7FUL << HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
-#define HCSPLT_HUBADDR                   HCSPLT_HUBADDR_Msk    /*!< Hub address */
-#define HCSPLT_HUBADDR_0                 (0x01UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
-#define HCSPLT_HUBADDR_1                 (0x02UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
-#define HCSPLT_HUBADDR_2                 (0x04UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
-#define HCSPLT_HUBADDR_3                 (0x08UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
-#define HCSPLT_HUBADDR_4                 (0x10UL << HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
-#define HCSPLT_HUBADDR_5                 (0x20UL << HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
-#define HCSPLT_HUBADDR_6                 (0x40UL << HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+#define HCSPLT_HUBADDR_Msk               (0x7FUL << HCSPLT_HUBADDR_Pos)           /*!< 0x00003F80 */
+#define HCSPLT_HUBADDR                   HCSPLT_HUBADDR_Msk                       /*!< Hub address */
+#define HCSPLT_HUBADDR_0                 (0x01UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00000080 */
+#define HCSPLT_HUBADDR_1                 (0x02UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00000100 */
+#define HCSPLT_HUBADDR_2                 (0x04UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00000200 */
+#define HCSPLT_HUBADDR_3                 (0x08UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00000400 */
+#define HCSPLT_HUBADDR_4                 (0x10UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00000800 */
+#define HCSPLT_HUBADDR_5                 (0x20UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00001000 */
+#define HCSPLT_HUBADDR_6                 (0x40UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00002000 */
 
 #define HCSPLT_XACTPOS_Pos               (14U)
-#define HCSPLT_XACTPOS_Msk               (0x3UL << HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
-#define HCSPLT_XACTPOS                   HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
-#define HCSPLT_XACTPOS_0                 (0x1UL << HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
-#define HCSPLT_XACTPOS_1                 (0x2UL << HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define HCSPLT_XACTPOS_Msk               (0x3UL << HCSPLT_XACTPOS_Pos)            /*!< 0x0000C000 */
+#define HCSPLT_XACTPOS                   HCSPLT_XACTPOS_Msk                       /*!< XACTPOS */
+#define HCSPLT_XACTPOS_0                 (0x1UL << HCSPLT_XACTPOS_Pos)            /*!< 0x00004000 */
+#define HCSPLT_XACTPOS_1                 (0x2UL << HCSPLT_XACTPOS_Pos)            /*!< 0x00008000 */
 #define HCSPLT_COMPLSPLT_Pos             (16U)
-#define HCSPLT_COMPLSPLT_Msk             (0x1UL << HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
-#define HCSPLT_COMPLSPLT                 HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define HCSPLT_COMPLSPLT_Msk             (0x1UL << HCSPLT_COMPLSPLT_Pos)          /*!< 0x00010000 */
+#define HCSPLT_COMPLSPLT                 HCSPLT_COMPLSPLT_Msk                     /*!< Do complete split */
 #define HCSPLT_SPLITEN_Pos               (31U)
-#define HCSPLT_SPLITEN_Msk               (0x1UL << HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
-#define HCSPLT_SPLITEN                   HCSPLT_SPLITEN_Msk    /*!< Split enable */
+#define HCSPLT_SPLITEN_Msk               (0x1UL << HCSPLT_SPLITEN_Pos)            /*!< 0x80000000 */
+#define HCSPLT_SPLITEN                   HCSPLT_SPLITEN_Msk                       /*!< Split enable */
 
 /********************  Bit definition for HCINT register  ********************/
 #define HCINT_XFRC_Pos                   (0U)
-#define HCINT_XFRC_Msk                   (0x1UL << HCINT_XFRC_Pos) /*!< 0x00000001 */
-#define HCINT_XFRC                       HCINT_XFRC_Msk        /*!< Transfer completed */
+#define HCINT_XFRC_Msk                   (0x1UL << HCINT_XFRC_Pos)                /*!< 0x00000001 */
+#define HCINT_XFRC                       HCINT_XFRC_Msk                           /*!< Transfer completed */
 #define HCINT_CHH_Pos                    (1U)
-#define HCINT_CHH_Msk                    (0x1UL << HCINT_CHH_Pos) /*!< 0x00000002 */
-#define HCINT_CHH                        HCINT_CHH_Msk         /*!< Channel halted */
+#define HCINT_CHH_Msk                    (0x1UL << HCINT_CHH_Pos)                 /*!< 0x00000002 */
+#define HCINT_CHH                        HCINT_CHH_Msk                            /*!< Channel halted */
 #define HCINT_AHBERR_Pos                 (2U)
-#define HCINT_AHBERR_Msk                 (0x1UL << HCINT_AHBERR_Pos) /*!< 0x00000004 */
-#define HCINT_AHBERR                     HCINT_AHBERR_Msk      /*!< AHB error */
+#define HCINT_AHBERR_Msk                 (0x1UL << HCINT_AHBERR_Pos)              /*!< 0x00000004 */
+#define HCINT_AHBERR                     HCINT_AHBERR_Msk                         /*!< AHB error */
 #define HCINT_STALL_Pos                  (3U)
-#define HCINT_STALL_Msk                  (0x1UL << HCINT_STALL_Pos) /*!< 0x00000008 */
-#define HCINT_STALL                      HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define HCINT_STALL_Msk                  (0x1UL << HCINT_STALL_Pos)               /*!< 0x00000008 */
+#define HCINT_STALL                      HCINT_STALL_Msk                          /*!< STALL response received interrupt */
 #define HCINT_NAK_Pos                    (4U)
-#define HCINT_NAK_Msk                    (0x1UL << HCINT_NAK_Pos) /*!< 0x00000010 */
-#define HCINT_NAK                        HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define HCINT_NAK_Msk                    (0x1UL << HCINT_NAK_Pos)                 /*!< 0x00000010 */
+#define HCINT_NAK                        HCINT_NAK_Msk                            /*!< NAK response received interrupt */
 #define HCINT_ACK_Pos                    (5U)
-#define HCINT_ACK_Msk                    (0x1UL << HCINT_ACK_Pos) /*!< 0x00000020 */
-#define HCINT_ACK                        HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define HCINT_ACK_Msk                    (0x1UL << HCINT_ACK_Pos)                 /*!< 0x00000020 */
+#define HCINT_ACK                        HCINT_ACK_Msk                            /*!< ACK response received/transmitted interrupt */
 #define HCINT_NYET_Pos                   (6U)
-#define HCINT_NYET_Msk                   (0x1UL << HCINT_NYET_Pos) /*!< 0x00000040 */
-#define HCINT_NYET                       HCINT_NYET_Msk        /*!< Response received interrupt */
+#define HCINT_NYET_Msk                   (0x1UL << HCINT_NYET_Pos)                /*!< 0x00000040 */
+#define HCINT_NYET                       HCINT_NYET_Msk                           /*!< Response received interrupt */
 #define HCINT_TXERR_Pos                  (7U)
-#define HCINT_TXERR_Msk                  (0x1UL << HCINT_TXERR_Pos) /*!< 0x00000080 */
-#define HCINT_TXERR                      HCINT_TXERR_Msk       /*!< Transaction error */
+#define HCINT_TXERR_Msk                  (0x1UL << HCINT_TXERR_Pos)               /*!< 0x00000080 */
+#define HCINT_TXERR                      HCINT_TXERR_Msk                          /*!< Transaction error */
 #define HCINT_BBERR_Pos                  (8U)
-#define HCINT_BBERR_Msk                  (0x1UL << HCINT_BBERR_Pos) /*!< 0x00000100 */
-#define HCINT_BBERR                      HCINT_BBERR_Msk       /*!< Babble error */
+#define HCINT_BBERR_Msk                  (0x1UL << HCINT_BBERR_Pos)               /*!< 0x00000100 */
+#define HCINT_BBERR                      HCINT_BBERR_Msk                          /*!< Babble error */
 #define HCINT_FRMOR_Pos                  (9U)
-#define HCINT_FRMOR_Msk                  (0x1UL << HCINT_FRMOR_Pos) /*!< 0x00000200 */
-#define HCINT_FRMOR                      HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define HCINT_FRMOR_Msk                  (0x1UL << HCINT_FRMOR_Pos)               /*!< 0x00000200 */
+#define HCINT_FRMOR                      HCINT_FRMOR_Msk                          /*!< Frame overrun */
 #define HCINT_DTERR_Pos                  (10U)
-#define HCINT_DTERR_Msk                  (0x1UL << HCINT_DTERR_Pos) /*!< 0x00000400 */
-#define HCINT_DTERR                      HCINT_DTERR_Msk       /*!< Data toggle error */
+#define HCINT_DTERR_Msk                  (0x1UL << HCINT_DTERR_Pos)               /*!< 0x00000400 */
+#define HCINT_DTERR                      HCINT_DTERR_Msk                          /*!< Data toggle error */
 
 /********************  Bit definition for DIEPINT register  ********************/
 #define DIEPINT_XFRC_Pos                 (0U)
-#define DIEPINT_XFRC_Msk                 (0x1UL << DIEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define DIEPINT_XFRC                     DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define DIEPINT_XFRC_Msk                 (0x1UL << DIEPINT_XFRC_Pos)              /*!< 0x00000001 */
+#define DIEPINT_XFRC                     DIEPINT_XFRC_Msk                         /*!< Transfer completed interrupt */
 #define DIEPINT_EPDISD_Pos               (1U)
-#define DIEPINT_EPDISD_Msk               (0x1UL << DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define DIEPINT_EPDISD                   DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define DIEPINT_EPDISD_Msk               (0x1UL << DIEPINT_EPDISD_Pos)            /*!< 0x00000002 */
+#define DIEPINT_EPDISD                   DIEPINT_EPDISD_Msk                       /*!< Endpoint disabled interrupt */
 #define DIEPINT_AHBERR_Pos               (2U)
-#define DIEPINT_AHBERR_Msk               (0x1UL << DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define DIEPINT_AHBERR                   DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define DIEPINT_AHBERR_Msk               (0x1UL << DIEPINT_AHBERR_Pos)            /*!< 0x00000004 */
+#define DIEPINT_AHBERR                   DIEPINT_AHBERR_Msk                       /*!< AHB Error (AHBErr) during an IN transaction */
 #define DIEPINT_TOC_Pos                  (3U)
-#define DIEPINT_TOC_Msk                  (0x1UL << DIEPINT_TOC_Pos) /*!< 0x00000008 */
-#define DIEPINT_TOC                      DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define DIEPINT_TOC_Msk                  (0x1UL << DIEPINT_TOC_Pos)               /*!< 0x00000008 */
+#define DIEPINT_TOC                      DIEPINT_TOC_Msk                          /*!< Timeout condition */
 #define DIEPINT_ITTXFE_Pos               (4U)
-#define DIEPINT_ITTXFE_Msk               (0x1UL << DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
-#define DIEPINT_ITTXFE                   DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define DIEPINT_ITTXFE_Msk               (0x1UL << DIEPINT_ITTXFE_Pos)            /*!< 0x00000010 */
+#define DIEPINT_ITTXFE                   DIEPINT_ITTXFE_Msk                       /*!< IN token received when TxFIFO is empty */
 #define DIEPINT_INEPNM_Pos               (5U)
-#define DIEPINT_INEPNM_Msk               (0x1UL << DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
-#define DIEPINT_INEPNM                   DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define DIEPINT_INEPNM_Msk               (0x1UL << DIEPINT_INEPNM_Pos)            /*!< 0x00000020 */
+#define DIEPINT_INEPNM                   DIEPINT_INEPNM_Msk                       /*!< IN token received with EP mismatch */
 #define DIEPINT_INEPNE_Pos               (6U)
-#define DIEPINT_INEPNE_Msk               (0x1UL << DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
-#define DIEPINT_INEPNE                   DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define DIEPINT_INEPNE_Msk               (0x1UL << DIEPINT_INEPNE_Pos)            /*!< 0x00000040 */
+#define DIEPINT_INEPNE                   DIEPINT_INEPNE_Msk                       /*!< IN endpoint NAK effective */
 #define DIEPINT_TXFE_Pos                 (7U)
-#define DIEPINT_TXFE_Msk                 (0x1UL << DIEPINT_TXFE_Pos) /*!< 0x00000080 */
-#define DIEPINT_TXFE                     DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define DIEPINT_TXFE_Msk                 (0x1UL << DIEPINT_TXFE_Pos)              /*!< 0x00000080 */
+#define DIEPINT_TXFE                     DIEPINT_TXFE_Msk                         /*!< Transmit FIFO empty */
 #define DIEPINT_TXFIFOUDRN_Pos           (8U)
-#define DIEPINT_TXFIFOUDRN_Msk           (0x1UL << DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
-#define DIEPINT_TXFIFOUDRN               DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define DIEPINT_TXFIFOUDRN_Msk           (0x1UL << DIEPINT_TXFIFOUDRN_Pos)        /*!< 0x00000100 */
+#define DIEPINT_TXFIFOUDRN               DIEPINT_TXFIFOUDRN_Msk                   /*!< Transmit Fifo Underrun */
 #define DIEPINT_BNA_Pos                  (9U)
-#define DIEPINT_BNA_Msk                  (0x1UL << DIEPINT_BNA_Pos) /*!< 0x00000200 */
-#define DIEPINT_BNA                      DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define DIEPINT_BNA_Msk                  (0x1UL << DIEPINT_BNA_Pos)               /*!< 0x00000200 */
+#define DIEPINT_BNA                      DIEPINT_BNA_Msk                          /*!< Buffer not available interrupt */
 #define DIEPINT_PKTDRPSTS_Pos            (11U)
-#define DIEPINT_PKTDRPSTS_Msk            (0x1UL << DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
-#define DIEPINT_PKTDRPSTS                DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define DIEPINT_PKTDRPSTS_Msk            (0x1UL << DIEPINT_PKTDRPSTS_Pos)         /*!< 0x00000800 */
+#define DIEPINT_PKTDRPSTS                DIEPINT_PKTDRPSTS_Msk                    /*!< Packet dropped status */
 #define DIEPINT_BERR_Pos                 (12U)
-#define DIEPINT_BERR_Msk                 (0x1UL << DIEPINT_BERR_Pos) /*!< 0x00001000 */
-#define DIEPINT_BERR                     DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define DIEPINT_BERR_Msk                 (0x1UL << DIEPINT_BERR_Pos)              /*!< 0x00001000 */
+#define DIEPINT_BERR                     DIEPINT_BERR_Msk                         /*!< Babble error interrupt */
 #define DIEPINT_NAK_Pos                  (13U)
-#define DIEPINT_NAK_Msk                  (0x1UL << DIEPINT_NAK_Pos) /*!< 0x00002000 */
-#define DIEPINT_NAK                      DIEPINT_NAK_Msk       /*!< NAK interrupt */
+#define DIEPINT_NAK_Msk                  (0x1UL << DIEPINT_NAK_Pos)               /*!< 0x00002000 */
+#define DIEPINT_NAK                      DIEPINT_NAK_Msk                          /*!< NAK interrupt */
 
 /********************  Bit definition for HCINTMSK register  ********************/
 #define HCINTMSK_XFRCM_Pos               (0U)
-#define HCINTMSK_XFRCM_Msk               (0x1UL << HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define HCINTMSK_XFRCM                   HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define HCINTMSK_XFRCM_Msk               (0x1UL << HCINTMSK_XFRCM_Pos)            /*!< 0x00000001 */
+#define HCINTMSK_XFRCM                   HCINTMSK_XFRCM_Msk                       /*!< Transfer completed mask */
 #define HCINTMSK_CHHM_Pos                (1U)
-#define HCINTMSK_CHHM_Msk                (0x1UL << HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
-#define HCINTMSK_CHHM                    HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define HCINTMSK_CHHM_Msk                (0x1UL << HCINTMSK_CHHM_Pos)             /*!< 0x00000002 */
+#define HCINTMSK_CHHM                    HCINTMSK_CHHM_Msk                        /*!< Channel halted mask */
 #define HCINTMSK_AHBERR_Pos              (2U)
-#define HCINTMSK_AHBERR_Msk              (0x1UL << HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
-#define HCINTMSK_AHBERR                  HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define HCINTMSK_AHBERR_Msk              (0x1UL << HCINTMSK_AHBERR_Pos)           /*!< 0x00000004 */
+#define HCINTMSK_AHBERR                  HCINTMSK_AHBERR_Msk                      /*!< AHB error */
 #define HCINTMSK_STALLM_Pos              (3U)
-#define HCINTMSK_STALLM_Msk              (0x1UL << HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
-#define HCINTMSK_STALLM                  HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define HCINTMSK_STALLM_Msk              (0x1UL << HCINTMSK_STALLM_Pos)           /*!< 0x00000008 */
+#define HCINTMSK_STALLM                  HCINTMSK_STALLM_Msk                      /*!< STALL response received interrupt mask */
 #define HCINTMSK_NAKM_Pos                (4U)
-#define HCINTMSK_NAKM_Msk                (0x1UL << HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
-#define HCINTMSK_NAKM                    HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define HCINTMSK_NAKM_Msk                (0x1UL << HCINTMSK_NAKM_Pos)             /*!< 0x00000010 */
+#define HCINTMSK_NAKM                    HCINTMSK_NAKM_Msk                        /*!< NAK response received interrupt mask */
 #define HCINTMSK_ACKM_Pos                (5U)
-#define HCINTMSK_ACKM_Msk                (0x1UL << HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
-#define HCINTMSK_ACKM                    HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define HCINTMSK_ACKM_Msk                (0x1UL << HCINTMSK_ACKM_Pos)             /*!< 0x00000020 */
+#define HCINTMSK_ACKM                    HCINTMSK_ACKM_Msk                        /*!< ACK response received/transmitted interrupt mask */
 #define HCINTMSK_NYET_Pos                (6U)
-#define HCINTMSK_NYET_Msk                (0x1UL << HCINTMSK_NYET_Pos) /*!< 0x00000040 */
-#define HCINTMSK_NYET                    HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define HCINTMSK_NYET_Msk                (0x1UL << HCINTMSK_NYET_Pos)             /*!< 0x00000040 */
+#define HCINTMSK_NYET                    HCINTMSK_NYET_Msk                        /*!< response received interrupt mask */
 #define HCINTMSK_TXERRM_Pos              (7U)
-#define HCINTMSK_TXERRM_Msk              (0x1UL << HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
-#define HCINTMSK_TXERRM                  HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define HCINTMSK_TXERRM_Msk              (0x1UL << HCINTMSK_TXERRM_Pos)           /*!< 0x00000080 */
+#define HCINTMSK_TXERRM                  HCINTMSK_TXERRM_Msk                      /*!< Transaction error mask */
 #define HCINTMSK_BBERRM_Pos              (8U)
-#define HCINTMSK_BBERRM_Msk              (0x1UL << HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
-#define HCINTMSK_BBERRM                  HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define HCINTMSK_BBERRM_Msk              (0x1UL << HCINTMSK_BBERRM_Pos)           /*!< 0x00000100 */
+#define HCINTMSK_BBERRM                  HCINTMSK_BBERRM_Msk                      /*!< Babble error mask */
 #define HCINTMSK_FRMORM_Pos              (9U)
-#define HCINTMSK_FRMORM_Msk              (0x1UL << HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
-#define HCINTMSK_FRMORM                  HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define HCINTMSK_FRMORM_Msk              (0x1UL << HCINTMSK_FRMORM_Pos)           /*!< 0x00000200 */
+#define HCINTMSK_FRMORM                  HCINTMSK_FRMORM_Msk                      /*!< Frame overrun mask */
 #define HCINTMSK_DTERRM_Pos              (10U)
-#define HCINTMSK_DTERRM_Msk              (0x1UL << HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
-#define HCINTMSK_DTERRM                  HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+#define HCINTMSK_DTERRM_Msk              (0x1UL << HCINTMSK_DTERRM_Pos)           /*!< 0x00000400 */
+#define HCINTMSK_DTERRM                  HCINTMSK_DTERRM_Msk                      /*!< Data toggle error mask */
 
 /********************  Bit definition for DIEPTSIZ register  ********************/
 
 #define DIEPTSIZ_XFRSIZ_Pos              (0U)
-#define DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define DIEPTSIZ_XFRSIZ                  DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos)       /*!< 0x0007FFFF */
+#define DIEPTSIZ_XFRSIZ                  DIEPTSIZ_XFRSIZ_Msk                      /*!< Transfer size */
 #define DIEPTSIZ_PKTCNT_Pos              (19U)
-#define DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define DIEPTSIZ_PKTCNT                  DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << DIEPTSIZ_PKTCNT_Pos)         /*!< 0x1FF80000 */
+#define DIEPTSIZ_PKTCNT                  DIEPTSIZ_PKTCNT_Msk                      /*!< Packet count */
 #define DIEPTSIZ_MULCNT_Pos              (29U)
-#define DIEPTSIZ_MULCNT_Msk              (0x3UL << DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
-#define DIEPTSIZ_MULCNT                  DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
-/********************  Bit definition for HCTSIZ register  ********************/
+#define DIEPTSIZ_MULCNT_Msk              (0x3UL << DIEPTSIZ_MULCNT_Pos)           /*!< 0x60000000 */
+#define DIEPTSIZ_MULCNT                  DIEPTSIZ_MULCNT_Msk                      /*!< Packet count */
+                                                                                  /********************  Bit definition for HCTSIZ register  ********************/
 #define HCTSIZ_XFRSIZ_Pos                (0U)
-#define HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define HCTSIZ_XFRSIZ                    HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos)         /*!< 0x0007FFFF */
+#define HCTSIZ_XFRSIZ                    HCTSIZ_XFRSIZ_Msk                        /*!< Transfer size */
 #define HCTSIZ_PKTCNT_Pos                (19U)
-#define HCTSIZ_PKTCNT_Msk                (0x3FFUL << HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define HCTSIZ_PKTCNT                    HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define HCTSIZ_PKTCNT_Msk                (0x3FFUL << HCTSIZ_PKTCNT_Pos)           /*!< 0x1FF80000 */
+#define HCTSIZ_PKTCNT                    HCTSIZ_PKTCNT_Msk                        /*!< Packet count */
 #define HCTSIZ_DOPING_Pos                (31U)
-#define HCTSIZ_DOPING_Msk                (0x1UL << HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
-#define HCTSIZ_DOPING                    HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define HCTSIZ_DOPING_Msk                (0x1UL << HCTSIZ_DOPING_Pos)             /*!< 0x80000000 */
+#define HCTSIZ_DOPING                    HCTSIZ_DOPING_Msk                        /*!< Do PING */
 #define HCTSIZ_DPID_Pos                  (29U)
-#define HCTSIZ_DPID_Msk                  (0x3UL << HCTSIZ_DPID_Pos) /*!< 0x60000000 */
-#define HCTSIZ_DPID                      HCTSIZ_DPID_Msk       /*!< Data PID */
-#define HCTSIZ_DPID_0                    (0x1UL << HCTSIZ_DPID_Pos) /*!< 0x20000000 */
-#define HCTSIZ_DPID_1                    (0x2UL << HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+#define HCTSIZ_DPID_Msk                  (0x3UL << HCTSIZ_DPID_Pos)               /*!< 0x60000000 */
+#define HCTSIZ_DPID                      HCTSIZ_DPID_Msk                          /*!< Data PID */
+#define HCTSIZ_DPID_0                    (0x1UL << HCTSIZ_DPID_Pos)               /*!< 0x20000000 */
+#define HCTSIZ_DPID_1                    (0x2UL << HCTSIZ_DPID_Pos)               /*!< 0x40000000 */
 
 /********************  Bit definition for DIEPDMA register  ********************/
 #define DIEPDMA_DMAADDR_Pos              (0U)
-#define DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define DIEPDMA_DMAADDR                  DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+#define DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos)    /*!< 0xFFFFFFFF */
+#define DIEPDMA_DMAADDR                  DIEPDMA_DMAADDR_Msk                      /*!< DMA address */
 
 /********************  Bit definition for HCDMA register  ********************/
 #define HCDMA_DMAADDR_Pos                (0U)
-#define HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define HCDMA_DMAADDR                    HCDMA_DMAADDR_Msk     /*!< DMA address */
+#define HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos)      /*!< 0xFFFFFFFF */
+#define HCDMA_DMAADDR                    HCDMA_DMAADDR_Msk                        /*!< DMA address */
 
-/********************  Bit definition for DTXFSTS register  ********************/
+                                                                                  /********************  Bit definition for DTXFSTS register  ********************/
 #define DTXFSTS_INEPTFSAV_Pos            (0U)
-#define DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
-#define DTXFSTS_INEPTFSAV                DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+#define DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos)      /*!< 0x0000FFFF */
+#define DTXFSTS_INEPTFSAV                DTXFSTS_INEPTFSAV_Msk                    /*!< IN endpoint TxFIFO space available */
 
-/********************  Bit definition for DIEPTXF register  ********************/
+                                                                                  /********************  Bit definition for DIEPTXF register  ********************/
 #define DIEPTXF_INEPTXSA_Pos             (0U)
-#define DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
-#define DIEPTXF_INEPTXSA                 DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << DIEPTXF_INEPTXSA_Pos)       /*!< 0x0000FFFF */
+#define DIEPTXF_INEPTXSA                 DIEPTXF_INEPTXSA_Msk                     /*!< IN endpoint FIFOx transmit RAM start address */
 #define DIEPTXF_INEPTXFD_Pos             (16U)
-#define DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
-#define DIEPTXF_INEPTXFD                 DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+#define DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << DIEPTXF_INEPTXFD_Pos)       /*!< 0xFFFF0000 */
+#define DIEPTXF_INEPTXFD                 DIEPTXF_INEPTXFD_Msk                     /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition for DOEPCTL register  ********************/
 #define DOEPCTL_MPSIZ_Pos                (0U)
-#define DOEPCTL_MPSIZ_Msk                (0x7FFUL << DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define DOEPCTL_MPSIZ                    DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define DOEPCTL_MPSIZ_Msk                (0x7FFUL << DOEPCTL_MPSIZ_Pos)           /*!< 0x000007FF */
+#define DOEPCTL_MPSIZ                    DOEPCTL_MPSIZ_Msk                        /*!< Maximum packet size */          /*!<Bit 1 */
 #define DOEPCTL_USBAEP_Pos               (15U)
-#define DOEPCTL_USBAEP_Msk               (0x1UL << DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define DOEPCTL_USBAEP                   DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define DOEPCTL_USBAEP_Msk               (0x1UL << DOEPCTL_USBAEP_Pos)            /*!< 0x00008000 */
+#define DOEPCTL_USBAEP                   DOEPCTL_USBAEP_Msk                       /*!< USB active endpoint */
 #define DOEPCTL_NAKSTS_Pos               (17U)
-#define DOEPCTL_NAKSTS_Msk               (0x1UL << DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define DOEPCTL_NAKSTS                   DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define DOEPCTL_NAKSTS_Msk               (0x1UL << DOEPCTL_NAKSTS_Pos)            /*!< 0x00020000 */
+#define DOEPCTL_NAKSTS                   DOEPCTL_NAKSTS_Msk                       /*!< NAK status */
 #define DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
-#define DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define DOEPCTL_SD0PID_SEVNFRM           DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos)    /*!< 0x10000000 */
+#define DOEPCTL_SD0PID_SEVNFRM           DOEPCTL_SD0PID_SEVNFRM_Msk               /*!< Set DATA0 PID */
 #define DOEPCTL_SODDFRM_Pos              (29U)
-#define DOEPCTL_SODDFRM_Msk              (0x1UL << DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define DOEPCTL_SODDFRM                  DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define DOEPCTL_SODDFRM_Msk              (0x1UL << DOEPCTL_SODDFRM_Pos)           /*!< 0x20000000 */
+#define DOEPCTL_SODDFRM                  DOEPCTL_SODDFRM_Msk                      /*!< Set odd frame */
 #define DOEPCTL_EPTYP_Pos                (18U)
-#define DOEPCTL_EPTYP_Msk                (0x3UL << DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define DOEPCTL_EPTYP                    DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
-#define DOEPCTL_EPTYP_0                  (0x1UL << DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define DOEPCTL_EPTYP_1                  (0x2UL << DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define DOEPCTL_EPTYP_Msk                (0x3UL << DOEPCTL_EPTYP_Pos)             /*!< 0x000C0000 */
+#define DOEPCTL_EPTYP                    DOEPCTL_EPTYP_Msk                        /*!< Endpoint type */
+#define DOEPCTL_EPTYP_0                  (0x1UL << DOEPCTL_EPTYP_Pos)             /*!< 0x00040000 */
+#define DOEPCTL_EPTYP_1                  (0x2UL << DOEPCTL_EPTYP_Pos)             /*!< 0x00080000 */
 #define DOEPCTL_SNPM_Pos                 (20U)
-#define DOEPCTL_SNPM_Msk                 (0x1UL << DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
-#define DOEPCTL_SNPM                     DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define DOEPCTL_SNPM_Msk                 (0x1UL << DOEPCTL_SNPM_Pos)              /*!< 0x00100000 */
+#define DOEPCTL_SNPM                     DOEPCTL_SNPM_Msk                         /*!< Snoop mode */
 #define DOEPCTL_STALL_Pos                (21U)
-#define DOEPCTL_STALL_Msk                (0x1UL << DOEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define DOEPCTL_STALL                    DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define DOEPCTL_STALL_Msk                (0x1UL << DOEPCTL_STALL_Pos)             /*!< 0x00200000 */
+#define DOEPCTL_STALL                    DOEPCTL_STALL_Msk                        /*!< STALL handshake */
 #define DOEPCTL_CNAK_Pos                 (26U)
-#define DOEPCTL_CNAK_Msk                 (0x1UL << DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define DOEPCTL_CNAK                     DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define DOEPCTL_CNAK_Msk                 (0x1UL << DOEPCTL_CNAK_Pos)              /*!< 0x04000000 */
+#define DOEPCTL_CNAK                     DOEPCTL_CNAK_Msk                         /*!< Clear NAK */
 #define DOEPCTL_SNAK_Pos                 (27U)
-#define DOEPCTL_SNAK_Msk                 (0x1UL << DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define DOEPCTL_SNAK                     DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define DOEPCTL_SNAK_Msk                 (0x1UL << DOEPCTL_SNAK_Pos)              /*!< 0x08000000 */
+#define DOEPCTL_SNAK                     DOEPCTL_SNAK_Msk                         /*!< Set NAK */
 #define DOEPCTL_EPDIS_Pos                (30U)
-#define DOEPCTL_EPDIS_Msk                (0x1UL << DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define DOEPCTL_EPDIS                    DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define DOEPCTL_EPDIS_Msk                (0x1UL << DOEPCTL_EPDIS_Pos)             /*!< 0x40000000 */
+#define DOEPCTL_EPDIS                    DOEPCTL_EPDIS_Msk                        /*!< Endpoint disable */
 #define DOEPCTL_EPENA_Pos                (31U)
-#define DOEPCTL_EPENA_Msk                (0x1UL << DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define DOEPCTL_EPENA                    DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+#define DOEPCTL_EPENA_Msk                (0x1UL << DOEPCTL_EPENA_Pos)             /*!< 0x80000000 */
+#define DOEPCTL_EPENA                    DOEPCTL_EPENA_Msk                        /*!< Endpoint enable */
 
 /********************  Bit definition for DOEPINT register  ********************/
 #define DOEPINT_XFRC_Pos                 (0U)
-#define DOEPINT_XFRC_Msk                 (0x1UL << DOEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define DOEPINT_XFRC                     DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define DOEPINT_XFRC_Msk                 (0x1UL << DOEPINT_XFRC_Pos)              /*!< 0x00000001 */
+#define DOEPINT_XFRC                     DOEPINT_XFRC_Msk                         /*!< Transfer completed interrupt */
 #define DOEPINT_EPDISD_Pos               (1U)
-#define DOEPINT_EPDISD_Msk               (0x1UL << DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define DOEPINT_EPDISD                   DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define DOEPINT_EPDISD_Msk               (0x1UL << DOEPINT_EPDISD_Pos)            /*!< 0x00000002 */
+#define DOEPINT_EPDISD                   DOEPINT_EPDISD_Msk                       /*!< Endpoint disabled interrupt */
 #define DOEPINT_AHBERR_Pos               (2U)
-#define DOEPINT_AHBERR_Msk               (0x1UL << DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define DOEPINT_AHBERR                   DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define DOEPINT_AHBERR_Msk               (0x1UL << DOEPINT_AHBERR_Pos)            /*!< 0x00000004 */
+#define DOEPINT_AHBERR                   DOEPINT_AHBERR_Msk                       /*!< AHB Error (AHBErr) during an OUT transaction */
 #define DOEPINT_STUP_Pos                 (3U)
-#define DOEPINT_STUP_Msk                 (0x1UL << DOEPINT_STUP_Pos) /*!< 0x00000008 */
-#define DOEPINT_STUP                     DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define DOEPINT_STUP_Msk                 (0x1UL << DOEPINT_STUP_Pos)              /*!< 0x00000008 */
+#define DOEPINT_STUP                     DOEPINT_STUP_Msk                         /*!< SETUP phase done */
 #define DOEPINT_OTEPDIS_Pos              (4U)
-#define DOEPINT_OTEPDIS_Msk              (0x1UL << DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
-#define DOEPINT_OTEPDIS                  DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define DOEPINT_OTEPDIS_Msk              (0x1UL << DOEPINT_OTEPDIS_Pos)           /*!< 0x00000010 */
+#define DOEPINT_OTEPDIS                  DOEPINT_OTEPDIS_Msk                      /*!< OUT token received when endpoint disabled */
 #define DOEPINT_OTEPSPR_Pos              (5U)
-#define DOEPINT_OTEPSPR_Msk              (0x1UL << DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
-#define DOEPINT_OTEPSPR                  DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
+#define DOEPINT_OTEPSPR_Msk              (0x1UL << DOEPINT_OTEPSPR_Pos)           /*!< 0x00000020 */
+#define DOEPINT_OTEPSPR                  DOEPINT_OTEPSPR_Msk                      /*!< Status Phase Received For Control Write */
 #define DOEPINT_B2BSTUP_Pos              (6U)
-#define DOEPINT_B2BSTUP_Msk              (0x1UL << DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
-#define DOEPINT_B2BSTUP                  DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define DOEPINT_B2BSTUP_Msk              (0x1UL << DOEPINT_B2BSTUP_Pos)           /*!< 0x00000040 */
+#define DOEPINT_B2BSTUP                  DOEPINT_B2BSTUP_Msk                      /*!< Back-to-back SETUP packets received */
 #define DOEPINT_OUTPKTERR_Pos            (8U)
-#define DOEPINT_OUTPKTERR_Msk            (0x1UL << DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
-#define DOEPINT_OUTPKTERR                DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define DOEPINT_OUTPKTERR_Msk            (0x1UL << DOEPINT_OUTPKTERR_Pos)         /*!< 0x00000100 */
+#define DOEPINT_OUTPKTERR                DOEPINT_OUTPKTERR_Msk                    /*!< OUT packet error */
 #define DOEPINT_NAK_Pos                  (13U)
-#define DOEPINT_NAK_Msk                  (0x1UL << DOEPINT_NAK_Pos) /*!< 0x00002000 */
-#define DOEPINT_NAK                      DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define DOEPINT_NAK_Msk                  (0x1UL << DOEPINT_NAK_Pos)               /*!< 0x00002000 */
+#define DOEPINT_NAK                      DOEPINT_NAK_Msk                          /*!< NAK Packet is transmitted by the device */
 #define DOEPINT_NYET_Pos                 (14U)
-#define DOEPINT_NYET_Msk                 (0x1UL << DOEPINT_NYET_Pos) /*!< 0x00004000 */
-#define DOEPINT_NYET                     DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define DOEPINT_NYET_Msk                 (0x1UL << DOEPINT_NYET_Pos)              /*!< 0x00004000 */
+#define DOEPINT_NYET                     DOEPINT_NYET_Msk                         /*!< NYET interrupt */
 #define DOEPINT_STPKTRX_Pos              (15U)
-#define DOEPINT_STPKTRX_Msk              (0x1UL << DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
-#define DOEPINT_STPKTRX                  DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+#define DOEPINT_STPKTRX_Msk              (0x1UL << DOEPINT_STPKTRX_Pos)           /*!< 0x00008000 */
+#define DOEPINT_STPKTRX                  DOEPINT_STPKTRX_Msk                      /*!< Setup Packet Received */
 
 /********************  Bit definition for DOEPTSIZ register  ********************/
 #define DOEPTSIZ_XFRSIZ_Pos              (0U)
-#define DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define DOEPTSIZ_XFRSIZ                  DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos)       /*!< 0x0007FFFF */
+#define DOEPTSIZ_XFRSIZ                  DOEPTSIZ_XFRSIZ_Msk                      /*!< Transfer size */
 #define DOEPTSIZ_PKTCNT_Pos              (19U)
-#define DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define DOEPTSIZ_PKTCNT                  DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << DOEPTSIZ_PKTCNT_Pos)         /*!< 0x1FF80000 */
+#define DOEPTSIZ_PKTCNT                  DOEPTSIZ_PKTCNT_Msk                      /*!< Packet count */
 
 #define DOEPTSIZ_STUPCNT_Pos             (29U)
-#define DOEPTSIZ_STUPCNT_Msk             (0x3UL << DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
-#define DOEPTSIZ_STUPCNT                 DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
-#define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
-#define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+#define DOEPTSIZ_STUPCNT_Msk             (0x3UL << DOEPTSIZ_STUPCNT_Pos)          /*!< 0x60000000 */
+#define DOEPTSIZ_STUPCNT                 DOEPTSIZ_STUPCNT_Msk                     /*!< SETUP packet count */
+#define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos)          /*!< 0x20000000 */
+#define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos)          /*!< 0x40000000 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
 #define PCGCCTL_STOPCLK_Pos              (0U)
-#define PCGCCTL_STOPCLK_Msk              (0x1UL << PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
-#define PCGCCTL_STOPCLK                  PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define PCGCCTL_STOPCLK_Msk              (0x1UL << PCGCCTL_STOPCLK_Pos)           /*!< 0x00000001 */
+#define PCGCCTL_STOPCLK                  PCGCCTL_STOPCLK_Msk                      /*!< SETUP packet count */
 #define PCGCCTL_GATECLK_Pos              (1U)
-#define PCGCCTL_GATECLK_Msk              (0x1UL << PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
-#define PCGCCTL_GATECLK                  PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define PCGCCTL_GATECLK_Msk              (0x1UL << PCGCCTL_GATECLK_Pos)           /*!< 0x00000002 */
+#define PCGCCTL_GATECLK                  PCGCCTL_GATECLK_Msk                      /*!<Bit 0 */
 #define PCGCCTL_PHYSUSP_Pos              (4U)
-#define PCGCCTL_PHYSUSP_Msk              (0x1UL << PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
-#define PCGCCTL_PHYSUSP                  PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+#define PCGCCTL_PHYSUSP_Msk              (0x1UL << PCGCCTL_PHYSUSP_Pos)           /*!< 0x00000010 */
+#define PCGCCTL_PHYSUSP                  PCGCCTL_PHYSUSP_Msk                      /*!<Bit 1 */
 
 /********************  Bit definition for USBPHYC_PLL1 register  ********************/
 #define HS_PHYC_PLL1_PLLEN_Pos                (0U)
-#define HS_PHYC_PLL1_PLLEN_Msk                (0x1UL << HS_PHYC_PLL1_PLLEN_Pos) /*!< 0x00000001 */
-#define HS_PHYC_PLL1_PLLEN                    HS_PHYC_PLL1_PLLEN_Msk     /*!< Enable PLL */
+#define HS_PHYC_PLL1_PLLEN_Msk                (0x1UL << HS_PHYC_PLL1_PLLEN_Pos)   /*!< 0x00000001 */
+#define HS_PHYC_PLL1_PLLEN                    HS_PHYC_PLL1_PLLEN_Msk              /*!< Enable PLL */
 #define HS_PHYC_PLL1_PLLSEL_Pos               (1U)
-#define HS_PHYC_PLL1_PLLSEL_Msk               (0x7UL << HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x0000000E */
-#define HS_PHYC_PLL1_PLLSEL                   HS_PHYC_PLL1_PLLSEL_Msk    /*!< Controls PHY frequency operation selection */
-#define HS_PHYC_PLL1_PLLSEL_1                 (0x1UL << HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000002 */
-#define HS_PHYC_PLL1_PLLSEL_2                 (0x2UL << HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000004 */
-#define HS_PHYC_PLL1_PLLSEL_3                 (0x4UL << HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000008 */
+#define HS_PHYC_PLL1_PLLSEL_Msk               (0x7UL << HS_PHYC_PLL1_PLLSEL_Pos)  /*!< 0x0000000E */
+#define HS_PHYC_PLL1_PLLSEL                   HS_PHYC_PLL1_PLLSEL_Msk             /*!< Controls PHY frequency operation selection */
+#define HS_PHYC_PLL1_PLLSEL_1                 (0x1UL << HS_PHYC_PLL1_PLLSEL_Pos)  /*!< 0x00000002 */
+#define HS_PHYC_PLL1_PLLSEL_2                 (0x2UL << HS_PHYC_PLL1_PLLSEL_Pos)  /*!< 0x00000004 */
+#define HS_PHYC_PLL1_PLLSEL_3                 (0x4UL << HS_PHYC_PLL1_PLLSEL_Pos)  /*!< 0x00000008 */
 
 #define HS_PHYC_PLL1_PLLSEL_12MHZ             0x00000000U                                                       /*!< PHY PLL1 input clock frequency 12 MHz   */
 #define HS_PHYC_PLL1_PLLSEL_12_5MHZ           HS_PHYC_PLL1_PLLSEL_1                                         /*!< PHY PLL1 input clock frequency 12.5 MHz */

From 7369d2441d84c3a2b01b53cce56ce4acf667da10 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 00:55:24 +0700
Subject: [PATCH 0599/2085] update dwc2_type

---
 src/portable/synopsys/dwc2/dcd_dwc2.c   |  175 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h |    6 +-
 src/portable/synopsys/dwc2/dwc2_type.h  | 2030 ++++++++++++-----------
 3 files changed, 1119 insertions(+), 1092 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 7ae10652c..b98bd0055 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -30,6 +30,7 @@
 #include "tusb_option.h"
 #include "device/dcd_attr.h"
 
+
 #if TUSB_OPT_DEVICE_ENABLED && \
     ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) )
 
@@ -51,7 +52,7 @@
 //--------------------------------------------------------------------+
 
 #define CORE_REG(_port)       ((dwc2_core_t*) DWC2_REG_BASE)
-#define DEVICE_REG(_port)     ((dwc2_device_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE))
+#define DEVICE_REG(_port)     CORE_REG(_port) //((dwc2_core_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE))
 #define EPIN_REG(_port)       ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
 #define EPOUT_REG(_port)      ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
 #define FIFO_BASE(_port, _x)  ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
@@ -63,6 +64,10 @@ enum
   DCD_FULL_SPEED        = 3, // Full speed with internal PHY
 };
 
+// PHYSEL, ULPISEL
+// UTMI internal HS PHY
+// ULPI external HS PHY
+
 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
 
 typedef struct {
@@ -103,7 +108,7 @@ static void update_grxfsiz(uint8_t rhport)
   }
 
   // Update size of RX FIFO
-  core->GRXFSIZ = calc_rx_ff_size(max_epsize);
+  core->grxfsiz = calc_rx_ff_size(max_epsize);
 }
 
 // Setup the control endpoint 0.
@@ -112,7 +117,7 @@ static void bus_reset(uint8_t rhport)
   (void) rhport;
 
   dwc2_core_t   * core   = CORE_REG(rhport);
-  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_core_t * dev    = DEVICE_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
@@ -120,7 +125,7 @@ static void bus_reset(uint8_t rhport)
   _out_ep_closed = false;
 
   // clear device address
-  dev->DCFG &= ~DCFG_DAD_Msk;
+  dev->dcfg &= ~DCFG_DAD_Msk;
 
   // 1. NAK for all OUT endpoints
   for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
@@ -128,9 +133,9 @@ static void bus_reset(uint8_t rhport)
   }
 
   // 2. Un-mask interrupt bits
-  dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
-  dev->DOEPMSK  = DOEPMSK_STUPM | DOEPMSK_XFRCM;
-  dev->DIEPMSK  = DIEPMSK_TOM | DIEPMSK_XFRCM;
+  dev->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
+  dev->doepmsk  = DOEPMSK_STUPM | DOEPMSK_XFRCM;
+  dev->diepmsk  = DIEPMSK_TOM | DIEPMSK_XFRCM;
 
   // "USB Data FIFOs" section in reference manual
   // Peripheral FIFO architecture
@@ -182,12 +187,12 @@ static void bus_reset(uint8_t rhport)
   //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
   //   overwrite this.
 
-  core->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
+  core->grxfsiz = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
 
   _allocated_fifo_words_tx = 16;
 
   // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  core->DIEPTXF0_HNPTXFSIZ = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+  core->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
   in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
@@ -195,15 +200,15 @@ static void bus_reset(uint8_t rhport)
 
   out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos);
 
-  core->GINTMSK |= GINTMSK_OEPINT | GINTMSK_IEPINT;
+  core->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
 
 
 static tusb_speed_t get_speed(uint8_t rhport)
 {
   (void) rhport;
-  dwc2_device_t * dev = DEVICE_REG(rhport);
-  uint32_t const enum_spd = (dev->DSTS & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos;
+  dwc2_core_t * dev = DEVICE_REG(rhport);
+  uint32_t const enum_spd = (dev->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos;
   return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
 }
 
@@ -220,11 +225,11 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
     bitvalue = DCD_FULL_SPEED;
   }
 
-  dwc2_device_t * dev = DEVICE_REG(rhport);
+  dwc2_core_t * dev = DEVICE_REG(rhport);
 
   // Clear and set speed bits
-  dev->DCFG &= ~(3 << DCFG_DSPD_Pos);
-  dev->DCFG |= (bitvalue << DCFG_DSPD_Pos);
+  dev->dcfg &= ~(3 << DCFG_DSPD_Pos);
+  dev->dcfg |= (bitvalue << DCFG_DSPD_Pos);
 }
 
 #if defined(USB_HS_PHYC)
@@ -272,7 +277,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 {
   (void) rhport;
 
-  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_core_t * dev    = DEVICE_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
@@ -296,12 +301,12 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
     if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
     {
       // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->DSTS & (1u << DSTS_FNSOF_Pos));
+      uint32_t const odd_frame_now = (dev->dsts & (1u << DSTS_FNSOF_Pos));
       in_ep[epnum].DIEPCTL |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
     }
     // Enable fifo empty interrupt only if there are something to put in the fifo.
     if(total_bytes != 0) {
-      dev->DIEPEMPMSK |= (1 << epnum);
+      dev->diepempmsk |= (1 << epnum);
     }
   } else {
     // A full OUT transfer (multiple packets, possibly) triggers XFRC.
@@ -313,7 +318,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
     if ((out_ep[epnum].DOEPCTL & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
     {
       // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->DSTS & (1u << DSTS_FNSOF_Pos));
+      uint32_t const odd_frame_now = (dev->dsts & (1u << DSTS_FNSOF_Pos));
       out_ep[epnum].DOEPCTL |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
     }
   }
@@ -336,23 +341,23 @@ void dcd_init (uint8_t rhport)
     // On selected MCUs HS port1 can be used with external PHY via ULPI interface
 #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
     // deactivate internal PHY
-    core->GCCFG &= ~GCCFG_PWRDWN;
+    core->gccfg &= ~GCCFG_PWRDWN;
 
     // Init The UTMI Interface
-    core->GUSBCFG &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
+    core->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
 
     // Select default internal VBUS Indicator and Drive for ULPI
-    core->GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
+    core->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
 #else
-    core->GUSBCFG |= GUSBCFG_PHYSEL;
+    core->gusbcfg |= GUSBCFG_PHYSEL;
 #endif
 
 #if defined(USB_HS_PHYC)
     // Highspeed with embedded UTMI PHYC
 
     // Select UTMI Interface
-    core->GUSBCFG &= ~GUSBCFG_ULPI_UTMI_SEL;
-    core->GCCFG |= GCCFG_PHYHSEN;
+    core->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL;
+    core->gccfg |= GCCFG_PHYHSEN;
 
     // Enables control of a High Speed USB PHY
     USB_HS_PHYCInit();
@@ -360,42 +365,42 @@ void dcd_init (uint8_t rhport)
   } else
   {
     // Enable internal PHY
-    core->GUSBCFG |= GUSBCFG_PHYSEL;
+    core->gusbcfg |= GUSBCFG_PHYSEL;
   }
 
   // Reset core after selecting PHYst
   // Wait AHB IDLE, reset then wait until it is cleared
-  while ((core->GRSTCTL & GRSTCTL_AHBIDL) == 0U) {}
-  core->GRSTCTL |= GRSTCTL_CSRST;
-  while ((core->GRSTCTL & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
+  while ((core->grstctl & GRSTCTL_AHBIDL) == 0U) {}
+  core->grstctl |= GRSTCTL_CSRST;
+  while ((core->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
 
   // Restart PHY clock
   *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0;
 
   // Clear all interrupts
-  core->GINTSTS |= core->GINTSTS;
+  core->gintsts |= core->gintsts;
 
   // Required as part of core initialization.
   // TODO: How should mode mismatch be handled? It will cause
   // the core to stop working/require reset.
-  core->GINTMSK |= GINTMSK_OTGINT | GINTMSK_MMISM;
+  core->gintmsk |= GINTMSK_OTGINT | GINTMSK_MMISM;
 
-  dwc2_device_t * dev = DEVICE_REG(rhport);
+  dwc2_core_t * dev = DEVICE_REG(rhport);
 
   // If USB host misbehaves during status portion of control xfer
   // (non zero-length packet), send STALL back and discard.
-  dev->DCFG |= DCFG_NZLSOHSK;
+  dev->dcfg |= DCFG_NZLSOHSK;
 
   set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
 
   // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->GCCFG |= GCCFG_PWRDWN;
+  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->gccfg |= GCCFG_PWRDWN;
 
-  core->GINTMSK |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
+  core->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
                    GINTMSK_WUIM   | GINTMSK_RXFLVLM;
 
   // Enable global interrupt
-  core->GAHBCFG |= GAHBCFG_GINT;
+  core->gahbcfg |= GAHBCFG_GINT;
 
   dcd_connect(rhport);
 }
@@ -412,8 +417,8 @@ void dcd_int_disable (uint8_t rhport)
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-  dwc2_device_t * dev = DEVICE_REG(rhport);
-  dev->DCFG = (dev->DCFG & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
+  dwc2_core_t * dev = DEVICE_REG(rhport);
+  dev->dcfg = (dev->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
 
   // Response with status after changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
@@ -424,33 +429,33 @@ void dcd_remote_wakeup(uint8_t rhport)
   (void) rhport;
 
   dwc2_core_t   * core = CORE_REG(rhport);
-  dwc2_device_t * dev  = DEVICE_REG(rhport);
+  dwc2_core_t * dev  = DEVICE_REG(rhport);
 
   // set remote wakeup
-  dev->DCTL |= DCTL_RWUSIG;
+  dev->dctl |= DCTL_RWUSIG;
 
   // enable SOF to detect bus resume
-  core->GINTSTS = GINTSTS_SOF;
-  core->GINTMSK |= GINTMSK_SOFM;
+  core->gintsts = GINTSTS_SOF;
+  core->gintmsk |= GINTMSK_SOFM;
 
   // Per specs: remote wakeup signal bit must be clear within 1-15ms
   dwc2_remote_wakeup_delay();
 
-  dev->DCTL &= ~DCTL_RWUSIG;
+  dev->dctl &= ~DCTL_RWUSIG;
 }
 
 void dcd_connect(uint8_t rhport)
 {
   (void) rhport;
-  dwc2_device_t * dev = DEVICE_REG(rhport);
-  dev->DCTL &= ~DCTL_SDIS;
+  dwc2_core_t * dev = DEVICE_REG(rhport);
+  dev->dctl &= ~DCTL_SDIS;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
   (void) rhport;
-  dwc2_device_t * dev = DEVICE_REG(rhport);
-  dev->DCTL |= DCTL_SDIS;
+  dwc2_core_t * dev = DEVICE_REG(rhport);
+  dev->dctl |= DCTL_SDIS;
 }
 
 
@@ -463,7 +468,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   (void) rhport;
 
   dwc2_core_t   * core   = CORE_REG(rhport);
-  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_core_t * dev    = DEVICE_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
@@ -484,12 +489,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     uint16_t const sz = calc_rx_ff_size(4*fifo_size);
 
     // If size_rx needs to be extended check if possible and if so enlarge it
-    if (core->GRXFSIZ < sz)
+    if (core->grxfsiz < sz)
     {
       TU_ASSERT(sz + _allocated_fifo_words_tx <= DWC2_EP_FIFO_SIZE/4);
 
       // Enlarge RX FIFO
-      core->GRXFSIZ = sz;
+      core->grxfsiz = sz;
     }
 
     out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos)        |
@@ -497,7 +502,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
         (xfer->max_size << DOEPCTL_MPSIZ_Pos);
 
-    dev->DAINTMSK |= (1 << (DAINTMSK_OEPM_Pos + epnum));
+    dev->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum));
   }
   else
   {
@@ -523,7 +528,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
 
     // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->GRXFSIZ <= DWC2_EP_FIFO_SIZE/4);
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->grxfsiz <= DWC2_EP_FIFO_SIZE/4);
 
     _allocated_fifo_words_tx += fifo_size;
 
@@ -531,7 +536,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 
     // DIEPTXF starts at FIFO #1.
     // Both TXFD and TXSA are in unit of 32-bit words.
-    core->DIEPTXF[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+    core->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
     in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) |
         (epnum << DIEPCTL_TXFNUM_Pos) |
@@ -539,7 +544,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
         (xfer->max_size << DIEPCTL_MPSIZ_Pos);
 
-    dev->DAINTMSK |= (1 << (DAINTMSK_IEPM_Pos + epnum));
+    dev->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
   }
 
   return true;
@@ -551,12 +556,12 @@ void dcd_edpt_close_all (uint8_t rhport)
   (void) rhport;
 
 //  dwc2_core_t * core = CORE_REG(rhport);
-  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_core_t * dev    = DEVICE_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   // Disable non-control interrupt
-  dev->DAINTMSK = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
+  dev->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
 
   for(uint8_t n = 1; n < DWC2_EP_MAX; n++)
   {
@@ -638,7 +643,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
   (void) rhport;
 
   dwc2_core_t   * core   = CORE_REG(rhport);
-  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_core_t * dev    = DEVICE_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
@@ -666,9 +671,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
-    core->GRSTCTL |= (epnum << GRSTCTL_TXFNUM_Pos);
-    core->GRSTCTL |= GRSTCTL_TXFFLSH;
-    while ( (core->GRSTCTL & GRSTCTL_TXFFLSH_Msk) != 0 ) {}
+    core->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos);
+    core->grstctl |= GRSTCTL_TXFFLSH;
+    while ( (core->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {}
   }
   else
   {
@@ -683,8 +688,8 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
       // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
       // anyway, and it can't be cleared by user code. If this while loop never
       // finishes, we have bigger problems than just the stack.
-      dev->DCTL |= DCTL_SGONAK;
-      while ( (core->GINTSTS & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {}
+      dev->dctl |= DCTL_SGONAK;
+      while ( (core->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {}
 
       // Ditto here- disable the endpoint.
       out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
@@ -693,7 +698,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
       out_ep[epnum].DOEPINT = DOEPINT_EPDISD;
 
       // Allow other OUT endpoints to keep receiving.
-      dev->DCTL |= DCTL_CGONAK;
+      dev->dctl |= DCTL_CGONAK;
     }
   }
 }
@@ -715,8 +720,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 
   if (dir == TUSB_DIR_IN)
   {
-    uint16_t const fifo_size = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
-    uint16_t const fifo_start = (core->DIEPTXF[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
+    uint16_t const fifo_size = (core->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
+    uint16_t const fifo_start = (core->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
     // For now only the last opened endpoint can be closed without fuss.
     TU_ASSERT(fifo_start == DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
     _allocated_fifo_words_tx -= fifo_size;
@@ -831,7 +836,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
   volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0);
 
   // Pop control word off FIFO
-  uint32_t ctl_word = core->GRXSTSP;
+  uint32_t ctl_word = core->grxstsp;
   uint8_t pktsts    = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
   uint8_t epnum     = (ctl_word & GRXSTSP_EPNUM_Msk) >>  GRXSTSP_EPNUM_Pos;
   uint16_t bcnt     = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
@@ -891,7 +896,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
   }
 }
 
-static void handle_epout_ints (uint8_t rhport, dwc2_device_t *dev, dwc2_epout_t *out_ep)
+static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *out_ep)
 {
   // DAINT for a given EP clears when DOEPINTx is cleared.
   // OEPINT will be cleared when DAINT's out bits are cleared.
@@ -899,7 +904,7 @@ static void handle_epout_ints (uint8_t rhport, dwc2_device_t *dev, dwc2_epout_t
   {
     xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
 
-    if ( dev->DAINT & (1 << (DAINT_OEPINT_Pos + n)) )
+    if ( dev->daint & (1 << (DAINT_OEPINT_Pos + n)) )
     {
       // SETUP packet Setup Phase done.
       if ( out_ep[n].DOEPINT & DOEPINT_STUP )
@@ -928,14 +933,14 @@ static void handle_epout_ints (uint8_t rhport, dwc2_device_t *dev, dwc2_epout_t
   }
 }
 
-static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t * in_ep) {
+static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in_ep) {
   // DAINT for a given EP clears when DIEPINTx is cleared.
   // IEPINT will be cleared when DAINT's out bits are cleared.
   for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
   {
     xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
 
-    if ( dev->DAINT & (1 << (DAINT_IEPINT_Pos + n)) )
+    if ( dev->daint & (1 << (DAINT_IEPINT_Pos + n)) )
     {
       // IN XFER complete (entire xfer).
       if ( in_ep[n].DIEPINT & DIEPINT_XFRC )
@@ -952,7 +957,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
       }
 
       // XFER FIFO empty
-      if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
+      if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dev->diepempmsk & (1 << n)) )
       {
         // DIEPINT's TXFE bit is read-only, software cannot clear it.
         // It will only be cleared by hardware when written bytes is more than
@@ -991,7 +996,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
         // Turn off TXFE if all bytes are written.
         if (((in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0)
         {
-          dev->DIEPEMPMSK &= ~(1 << n);
+          dev->diepempmsk &= ~(1 << n);
         }
       }
     }
@@ -1001,16 +1006,16 @@ static void handle_epin_ints(uint8_t rhport, dwc2_device_t * dev, dwc2_epin_t *
 void dcd_int_handler(uint8_t rhport)
 {
   dwc2_core_t   * core   = CORE_REG(rhport);
-  dwc2_device_t * dev    = DEVICE_REG(rhport);
+  dwc2_core_t * dev    = DEVICE_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
-  uint32_t const int_status = core->GINTSTS & core->GINTMSK;
+  uint32_t const int_status = core->gintsts & core->gintmsk;
 
   if(int_status & GINTSTS_USBRST)
   {
     // USBRST is start of reset.
-    core->GINTSTS = GINTSTS_USBRST;
+    core->gintsts = GINTSTS_USBRST;
     bus_reset(rhport);
   }
 
@@ -1018,7 +1023,7 @@ void dcd_int_handler(uint8_t rhport)
   {
     // ENUMDNE is the end of reset where speed of the link is detected
 
-    core->GINTSTS = GINTSTS_ENUMDNE;
+    core->gintsts = GINTSTS_ENUMDNE;
 
     tusb_speed_t const speed = get_speed(rhport);
 
@@ -1028,13 +1033,13 @@ void dcd_int_handler(uint8_t rhport)
 
   if(int_status & GINTSTS_USBSUSP)
   {
-    core->GINTSTS = GINTSTS_USBSUSP;
+    core->gintsts = GINTSTS_USBSUSP;
     dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
   }
 
   if(int_status & GINTSTS_WKUINT)
   {
-    core->GINTSTS = GINTSTS_WKUINT;
+    core->gintsts = GINTSTS_WKUINT;
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
   }
 
@@ -1044,22 +1049,22 @@ void dcd_int_handler(uint8_t rhport)
   if(int_status & GINTSTS_OTGINT)
   {
     // OTG INT bit is read-only
-    uint32_t const otg_int = core->GOTGINT;
+    uint32_t const otg_int = core->gotgint;
 
     if (otg_int & GOTGINT_SEDET)
     {
       dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
     }
 
-    core->GOTGINT = otg_int;
+    core->gotgint = otg_int;
   }
 
   if(int_status & GINTSTS_SOF)
   {
-    core->GINTSTS = GINTSTS_SOF;
+    core->gotgint = GINTSTS_SOF;
 
     // Disable SOF interrupt since currently only used for remote wakeup detection
-    core->GINTMSK &= ~GINTMSK_SOFM;
+    core->gintmsk &= ~GINTMSK_SOFM;
 
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
@@ -1070,13 +1075,13 @@ void dcd_int_handler(uint8_t rhport)
     // RXFLVL bit is read-only
 
     // Mask out RXFLVL while reading data from FIFO
-    core->GINTMSK &= ~GINTMSK_RXFLVLM;
+    core->gintmsk &= ~GINTMSK_RXFLVLM;
 
     // Loop until all available packets were handled
     do
     {
       handle_rxflvl_ints(rhport, out_ep);
-    } while(core->GINTSTS & GINTSTS_RXFLVL);
+    } while(core->gotgint & GINTSTS_RXFLVL);
 
     // Manage RX FIFO size
     if (_out_ep_closed)
@@ -1087,7 +1092,7 @@ void dcd_int_handler(uint8_t rhport)
       _out_ep_closed = false;
     }
 
-    core->GINTMSK |= GINTMSK_RXFLVLM;
+    core->gintmsk |= GINTMSK_RXFLVLM;
   }
 
   // OUT endpoint interrupt handling.
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 2a6d58e9a..d2ad8abb7 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -115,12 +115,12 @@ static inline void dwc2_remote_wakeup_delay(void)
 // Set turn-around timeout according to link speed
 static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
 {
-  core->GUSBCFG &= ~GUSBCFG_TRDT;
+  core->gusbcfg &= ~GUSBCFG_TRDT;
 
   if ( speed == TUSB_SPEED_HIGH )
   {
     // Use fixed 0x09 for Highspeed
-    core->GUSBCFG |= (0x09 << GUSBCFG_TRDT_Pos);
+    core->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos);
   }
   else
   {
@@ -149,7 +149,7 @@ static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
       turnaround = 0xFU;
 
     // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    core->GUSBCFG |= (turnaround << GUSBCFG_TRDT_Pos);
+    core->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos);
   }
 }
 
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 8d12e21ce..b83ac67f9 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -27,120 +27,142 @@
 // HS PHY
 typedef struct
 {
-  volatile uint32_t HS_PHYC_PLL;         /*!< This register is used to control the PLL of the HS PHY.                       000h */
-  volatile uint32_t Reserved04;          /*!< Reserved                                                                      004h */
-  volatile uint32_t Reserved08;          /*!< Reserved                                                                      008h */
-  volatile uint32_t HS_PHYC_TUNE;        /*!< This register is used to control the tuning interface of the High Speed PHY.  00Ch */
-  volatile uint32_t Reserved10;          /*!< Reserved                                                                      010h */
-  volatile uint32_t Reserved14;          /*!< Reserved                                                                      014h */
-  volatile uint32_t HS_PHYC_LDO;         /*!< This register is used to control the regulator (LDO).                         018h */
+  volatile uint32_t HS_PHYC_PLL;         // This register is used to control the PLL of the HS PHY.                       000h */
+  volatile uint32_t Reserved04;          // Reserved                                                                      004h */
+  volatile uint32_t Reserved08;          // Reserved                                                                      008h */
+  volatile uint32_t HS_PHYC_TUNE;        // This register is used to control the tuning interface of the High Speed PHY.  00Ch */
+  volatile uint32_t Reserved10;          // Reserved                                                                      010h */
+  volatile uint32_t Reserved14;          // Reserved                                                                      014h */
+  volatile uint32_t HS_PHYC_LDO;         // This register is used to control the regulator (LDO).                         018h */
 } HS_PHYC_GlobalTypeDef;
 #endif
 
-// Core
-typedef struct
-{
-  volatile uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
-  volatile uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
-  volatile uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
-  volatile uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
-  volatile uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
-  volatile uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
-  volatile uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
-  volatile uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
-  volatile uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
-  volatile uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
-  volatile uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
-  volatile uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
-           uint32_t Reserved30[2];        /*!< Reserved                                     030h */
-  volatile uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
-  volatile uint32_t CID;                  /*!< User ID Register                             03Ch */
-  volatile uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
-  volatile uint32_t GHWCFG1;              /* User HW config1                                044h*/
-  volatile uint32_t GHWCFG2;              /* User HW config2                                048h*/
-  volatile uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
-           uint32_t Reserved6;            /*!< Reserved                                     050h */
-  volatile uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
-  volatile uint32_t GPWRDN;               /*!< Power Down Register                          058h */
-  volatile uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-  volatile uint32_t GADPCTL;              /*!< ADP Timer, Control and Status Register       60Ch */
-           uint32_t Reserved43[39];       /*!< Reserved                                058h-0FFh */
-  volatile uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
-  volatile uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO              104h-13Ch */
-} dwc2_core_t;
-
-// Host
-typedef struct
-{
-  volatile uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  volatile uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  volatile uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-           uint32_t Reserved40C;      /*!< Reserved                             40Ch */
-  volatile uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  volatile uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  volatile uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} dwc2_host_t;
-
 // Host Channel
 typedef struct
 {
-  volatile uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  volatile uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  volatile uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  volatile uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  volatile uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  volatile uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-           uint32_t Reserved[2];      /*!< Reserved                                      */
+  volatile uint32_t hcchar;           // 500 + 20n Host Channel Characteristics Register
+  volatile uint32_t hcsplt;           // 504 + 20n Host Channel Split Control Register
+  volatile uint32_t hcint;            // 508 + 20n Host Channel Interrupt Register
+  volatile uint32_t hcintmsk;         // 50C + 20n Host Channel Interrupt Mask Register
+  volatile uint32_t hctsiz;           // 510 + 20n Host Channel Transfer Size Register
+  volatile uint32_t hcdma;            // 514 + 20n Host Channel DMA Address Register
+           uint32_t reserved518;      // 518 + 20n
+  volatile uint32_t hcdmab;           // 51C + 20n Host Channel DMA Address Register
 } dwc2_channel_t;
 
-// Device
 typedef struct
 {
-  volatile uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  volatile uint32_t DCTL;            /*!< dev Control Register         804h */
-  volatile uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-          uint32_t Reserved0C;      /*!< Reserved                     80Ch */
-  volatile uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  volatile uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  volatile uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  volatile uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-          uint32_t Reserved20;      /*!< Reserved                     820h */
-          uint32_t Reserved9;       /*!< Reserved                     824h */
-  volatile uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  volatile uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  volatile uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  volatile uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  volatile uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  volatile uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
-          uint32_t Reserved40;      /*!< dedicated EP mask            840h */
-  volatile uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-          uint32_t Reserved44[15];  /*!< Reserved                 844-87Ch */
-  volatile uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} dwc2_device_t;
+  //------------- Core Global -------------//
+  volatile uint32_t gotgctl;              // 000 OTG Control and Status Register
+  volatile uint32_t gotgint;              // 004 OTG Interrupt Register
+  volatile uint32_t gahbcfg;              // 008 AHB Configuration Register
+  volatile uint32_t gusbcfg;              // 00c USB Configuration Register
+  volatile uint32_t grstctl;              // 010 Reset Register
+  volatile uint32_t gintsts;              // 014 Interrupt Register
+  volatile uint32_t gintmsk;              // 018 Interrupt Mask Register
+  volatile uint32_t grxstsr;              // 01c Receive Status Debug Read Register
+  volatile uint32_t grxstsp;              // 020 Receive Status Read/Pop Register
+  volatile uint32_t grxfsiz;              // 024 Receive FIFO Size Register
+union {
+  volatile uint32_t dieptxf0;             // 028 EP0 Tx FIFO Size Register
+  volatile uint32_t gnptxfsiz;            // 028 Non-periodic Transmit FIFO Size Register
+};
+  volatile uint32_t gnptxsts;             // 02c Non-periodic Transmit FIFO/Queue Status Register
+  volatile uint32_t gi2cctl;              // 030 I2C Address Register
+  volatile uint32_t gpvndctl;             // 034 PHY Vendor Control Register
+union {
+  volatile uint32_t ggpio;                // 038 General Purpose IO Register
+  volatile uint32_t gccfg;                // 038 STM32 General Core Configuration
+};
+  volatile uint32_t guid;                 // 03C User ID Register
+  volatile uint32_t gsnpsid;              // 040 Synopsys ID Register
+  volatile uint32_t ghwcfg1;              // 044 User Hardware Configuration 1 Register
+  volatile uint32_t ghwcfg2;              // 048 User Hardware Configuration 2 Register
+  volatile uint32_t ghwcfg3;              // 04C User Hardware Configuration 3 Register
+  volatile uint32_t ghwcfg4;              // 050 User Hardware Configuration 4 Register
+  volatile uint32_t glpmcfg;              // 054 Core LPM Configuration Register
+  volatile uint32_t gpwrdn;               // 058 Power Down Register
+  volatile uint32_t gdfifocfg;            // 05C DFIFO Software Configuration Register
+  volatile uint32_t gadpctl;              // 060 ADP Timer, Control and Status Register
+
+           uint32_t reserved64[39];       // 064..0FF
+  volatile uint32_t hptxfsiz;             // 100 Host Periodic Tx FIFO Size Register
+  volatile uint32_t dieptxf[15];          // 104..13C Device Periodic Transmit FIFO Size Register
+           uint32_t reserved140[176];     // 140..3FC
+
+  //------------- Host -------------//
+  volatile uint32_t hcfg;             // 400 Host Configuration Register
+  volatile uint32_t hfir;             // 404 Host Frame Interval Register
+  volatile uint32_t hfnum;            // 408 Host Frame Number / Frame Remaining
+           uint32_t reserved40c;      // 40C
+  volatile uint32_t hptxsts;          // 410 Host Periodic TX FIFO / Queue Status
+  volatile uint32_t haint;            // 414 Host All Channels Interrupt Register
+  volatile uint32_t haintmsk;         // 418 Host All Channels Interrupt Mask
+  volatile uint32_t hflbaddr;         // 41C Host Frame List Base Address Register
+           uint32_t reserved420[8];   // 420..43C
+  volatile uint32_t hprt;             // 440 Host Port Control and Status
+           uint32_t reserved444[47];  // 444..4FC
+
+  //------------- Host Channel -------------//
+  dwc2_channel_t channel[16];         // 500..6FC Host Channels 0-15
+
+           uint32_t reserved700[64];  // 700..7FC
+
+  //------------- Device -------------//
+  volatile uint32_t dcfg;            // 800 Device Configuration Register
+  volatile uint32_t dctl;            // 804 Device Control Register
+  volatile uint32_t dsts;            // 808 Device Status Register (RO)
+           uint32_t reserved80c;     // 80C
+  volatile uint32_t diepmsk;         // 810 Device IN Endpoint Interrupt Mask
+  volatile uint32_t doepmsk;         // 814 Device OUT Endpoint Interrupt Mask
+  volatile uint32_t daint;           // 818 Device All Endpoints Interrupt
+  volatile uint32_t daintmsk;        // 81C Device All Endpoints Interrupt Mask
+  volatile uint32_t dtknqr1;         // 820 Device IN token sequence learning queue read register1
+  volatile uint32_t dtknqr2;         // 824 Device IN token sequence learning queue read register2
+  volatile uint32_t dvbusdis;        // 828 Device VBUS Discharge Time Register
+  volatile uint32_t dvbuspulse;      // 82C Device VBUS Pulsing Time Register
+  volatile uint32_t dthrctl;         // 830 Device threshold Control
+  volatile uint32_t diepempmsk;      // 834 Device IN Endpoint FIFO Empty Interrupt Mask
+
+  volatile uint32_t deachint;        // 838 Device Each Endpoint Interrupt
+  volatile uint32_t deachmsk;        // 83C Device Each Endpoint Interrupt msk
+  volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask
+  volatile uint32_t doepeachmsk[16]; // 880..8BC Device Each OUT Endpoint mask
+           uint32_t reserved8c0[16]; // 8C0..8FC
+
+  //------------- Device IN Endpoint -------------//
+
+
+  //------------- Device OUT Endpoint -------------//
+} dwc2_core_t;
+
+TU_VERIFY_STATIC(offsetof(dwc2_core_t, hcfg   ) == 0x0400, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_core_t, channel) == 0x0500, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_core_t, dcfg   ) == 0x0800, "incorrect size");
 
 // Endpoint IN
 typedef struct
 {
-  volatile uint32_t DIEPCTL;       /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-           uint32_t Reserved04;    /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  volatile uint32_t DIEPINT;       /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-           uint32_t Reserved0C;    /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  volatile uint32_t DIEPTSIZ;      /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  volatile uint32_t DIEPDMA;       /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  volatile uint32_t DTXFSTS;       /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-           uint32_t Reserved18;    /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+  volatile uint32_t DIEPCTL;       // dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+           uint32_t Reserved04;    // Reserved                       900h + (ep_num * 20h) + 04h */
+  volatile uint32_t DIEPINT;       // dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+           uint32_t Reserved0C;    // Reserved                       900h + (ep_num * 20h) + 0Ch */
+  volatile uint32_t DIEPTSIZ;      // IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  volatile uint32_t DIEPDMA;       // IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  volatile uint32_t DTXFSTS;       // IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+           uint32_t Reserved18;    // Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
 } dwc2_epin_t;
 
 // Endpoint OUT
 typedef struct
 {
-  volatile uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-           uint32_t Reserved04;    /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  volatile uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-           uint32_t Reserved0C;    /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  volatile uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  volatile uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-           uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+  volatile uint32_t DOEPCTL;       // dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+           uint32_t Reserved04;    // Reserved                               B00h + (ep_num * 20h) + 04h */
+  volatile uint32_t DOEPINT;       // dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+           uint32_t Reserved0C;    // Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  volatile uint32_t DOEPTSIZ;      // dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  volatile uint32_t DOEPDMA;       // dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+           uint32_t Reserved18[2]; // Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
 } dwc2_epout_t;
 
 
@@ -167,1427 +189,1427 @@ typedef struct
 
 /********************  Bit definition for GOTGCTL register  ********************/
 #define GOTGCTL_SRQSCS_Pos               (0U)
-#define GOTGCTL_SRQSCS_Msk               (0x1UL << GOTGCTL_SRQSCS_Pos)            /*!< 0x00000001 */
-#define GOTGCTL_SRQSCS                   GOTGCTL_SRQSCS_Msk                       /*!< Session request success */
+#define GOTGCTL_SRQSCS_Msk               (0x1UL << GOTGCTL_SRQSCS_Pos)            // 0x00000001 */
+#define GOTGCTL_SRQSCS                   GOTGCTL_SRQSCS_Msk                       // Session request success */
 #define GOTGCTL_SRQ_Pos                  (1U)
-#define GOTGCTL_SRQ_Msk                  (0x1UL << GOTGCTL_SRQ_Pos)               /*!< 0x00000002 */
-#define GOTGCTL_SRQ                      GOTGCTL_SRQ_Msk                          /*!< Session request */
+#define GOTGCTL_SRQ_Msk                  (0x1UL << GOTGCTL_SRQ_Pos)               // 0x00000002 */
+#define GOTGCTL_SRQ                      GOTGCTL_SRQ_Msk                          // Session request */
 #define GOTGCTL_VBVALOEN_Pos             (2U)
-#define GOTGCTL_VBVALOEN_Msk             (0x1UL << GOTGCTL_VBVALOEN_Pos)          /*!< 0x00000004 */
-#define GOTGCTL_VBVALOEN                 GOTGCTL_VBVALOEN_Msk                     /*!< VBUS valid override enable */
+#define GOTGCTL_VBVALOEN_Msk             (0x1UL << GOTGCTL_VBVALOEN_Pos)          // 0x00000004 */
+#define GOTGCTL_VBVALOEN                 GOTGCTL_VBVALOEN_Msk                     // VBUS valid override enable */
 #define GOTGCTL_VBVALOVAL_Pos            (3U)
-#define GOTGCTL_VBVALOVAL_Msk            (0x1UL << GOTGCTL_VBVALOVAL_Pos)         /*!< 0x00000008 */
-#define GOTGCTL_VBVALOVAL                GOTGCTL_VBVALOVAL_Msk                    /*!< VBUS valid override value */
+#define GOTGCTL_VBVALOVAL_Msk            (0x1UL << GOTGCTL_VBVALOVAL_Pos)         // 0x00000008 */
+#define GOTGCTL_VBVALOVAL                GOTGCTL_VBVALOVAL_Msk                    // VBUS valid override value */
 #define GOTGCTL_AVALOEN_Pos              (4U)
-#define GOTGCTL_AVALOEN_Msk              (0x1UL << GOTGCTL_AVALOEN_Pos)           /*!< 0x00000010 */
-#define GOTGCTL_AVALOEN                  GOTGCTL_AVALOEN_Msk                      /*!< A-peripheral session valid override enable */
+#define GOTGCTL_AVALOEN_Msk              (0x1UL << GOTGCTL_AVALOEN_Pos)           // 0x00000010 */
+#define GOTGCTL_AVALOEN                  GOTGCTL_AVALOEN_Msk                      // A-peripheral session valid override enable */
 #define GOTGCTL_AVALOVAL_Pos             (5U)
-#define GOTGCTL_AVALOVAL_Msk             (0x1UL << GOTGCTL_AVALOVAL_Pos)          /*!< 0x00000020 */
-#define GOTGCTL_AVALOVAL                 GOTGCTL_AVALOVAL_Msk                     /*!< A-peripheral session valid override value */
+#define GOTGCTL_AVALOVAL_Msk             (0x1UL << GOTGCTL_AVALOVAL_Pos)          // 0x00000020 */
+#define GOTGCTL_AVALOVAL                 GOTGCTL_AVALOVAL_Msk                     // A-peripheral session valid override value */
 #define GOTGCTL_BVALOEN_Pos              (6U)
-#define GOTGCTL_BVALOEN_Msk              (0x1UL << GOTGCTL_BVALOEN_Pos)           /*!< 0x00000040 */
-#define GOTGCTL_BVALOEN                  GOTGCTL_BVALOEN_Msk                      /*!< B-peripheral session valid override enable */
+#define GOTGCTL_BVALOEN_Msk              (0x1UL << GOTGCTL_BVALOEN_Pos)           // 0x00000040 */
+#define GOTGCTL_BVALOEN                  GOTGCTL_BVALOEN_Msk                      // B-peripheral session valid override enable */
 #define GOTGCTL_BVALOVAL_Pos             (7U)
-#define GOTGCTL_BVALOVAL_Msk             (0x1UL << GOTGCTL_BVALOVAL_Pos)          /*!< 0x00000080 */
-#define GOTGCTL_BVALOVAL                 GOTGCTL_BVALOVAL_Msk                     /*!< B-peripheral session valid override value  */
+#define GOTGCTL_BVALOVAL_Msk             (0x1UL << GOTGCTL_BVALOVAL_Pos)          // 0x00000080 */
+#define GOTGCTL_BVALOVAL                 GOTGCTL_BVALOVAL_Msk                     // B-peripheral session valid override value  */
 #define GOTGCTL_HNGSCS_Pos               (8U)
-#define GOTGCTL_HNGSCS_Msk               (0x1UL << GOTGCTL_HNGSCS_Pos)            /*!< 0x00000100 */
-#define GOTGCTL_HNGSCS                   GOTGCTL_HNGSCS_Msk                       /*!< Host set HNP enable */
+#define GOTGCTL_HNGSCS_Msk               (0x1UL << GOTGCTL_HNGSCS_Pos)            // 0x00000100 */
+#define GOTGCTL_HNGSCS                   GOTGCTL_HNGSCS_Msk                       // Host set HNP enable */
 #define GOTGCTL_HNPRQ_Pos                (9U)
-#define GOTGCTL_HNPRQ_Msk                (0x1UL << GOTGCTL_HNPRQ_Pos)             /*!< 0x00000200 */
-#define GOTGCTL_HNPRQ                    GOTGCTL_HNPRQ_Msk                        /*!< HNP request */
+#define GOTGCTL_HNPRQ_Msk                (0x1UL << GOTGCTL_HNPRQ_Pos)             // 0x00000200 */
+#define GOTGCTL_HNPRQ                    GOTGCTL_HNPRQ_Msk                        // HNP request */
 #define GOTGCTL_HSHNPEN_Pos              (10U)
-#define GOTGCTL_HSHNPEN_Msk              (0x1UL << GOTGCTL_HSHNPEN_Pos)           /*!< 0x00000400 */
-#define GOTGCTL_HSHNPEN                  GOTGCTL_HSHNPEN_Msk                      /*!< Host set HNP enable */
+#define GOTGCTL_HSHNPEN_Msk              (0x1UL << GOTGCTL_HSHNPEN_Pos)           // 0x00000400 */
+#define GOTGCTL_HSHNPEN                  GOTGCTL_HSHNPEN_Msk                      // Host set HNP enable */
 #define GOTGCTL_DHNPEN_Pos               (11U)
-#define GOTGCTL_DHNPEN_Msk               (0x1UL << GOTGCTL_DHNPEN_Pos)            /*!< 0x00000800 */
-#define GOTGCTL_DHNPEN                   GOTGCTL_DHNPEN_Msk                       /*!< Device HNP enabled */
+#define GOTGCTL_DHNPEN_Msk               (0x1UL << GOTGCTL_DHNPEN_Pos)            // 0x00000800 */
+#define GOTGCTL_DHNPEN                   GOTGCTL_DHNPEN_Msk                       // Device HNP enabled */
 #define GOTGCTL_EHEN_Pos                 (12U)
-#define GOTGCTL_EHEN_Msk                 (0x1UL << GOTGCTL_EHEN_Pos)              /*!< 0x00001000 */
-#define GOTGCTL_EHEN                     GOTGCTL_EHEN_Msk                         /*!< Embedded host enable */
+#define GOTGCTL_EHEN_Msk                 (0x1UL << GOTGCTL_EHEN_Pos)              // 0x00001000 */
+#define GOTGCTL_EHEN                     GOTGCTL_EHEN_Msk                         // Embedded host enable */
 #define GOTGCTL_CIDSTS_Pos               (16U)
-#define GOTGCTL_CIDSTS_Msk               (0x1UL << GOTGCTL_CIDSTS_Pos)            /*!< 0x00010000 */
-#define GOTGCTL_CIDSTS                   GOTGCTL_CIDSTS_Msk                       /*!< Connector ID status */
+#define GOTGCTL_CIDSTS_Msk               (0x1UL << GOTGCTL_CIDSTS_Pos)            // 0x00010000 */
+#define GOTGCTL_CIDSTS                   GOTGCTL_CIDSTS_Msk                       // Connector ID status */
 #define GOTGCTL_DBCT_Pos                 (17U)
-#define GOTGCTL_DBCT_Msk                 (0x1UL << GOTGCTL_DBCT_Pos)              /*!< 0x00020000 */
-#define GOTGCTL_DBCT                     GOTGCTL_DBCT_Msk                         /*!< Long/short debounce time */
+#define GOTGCTL_DBCT_Msk                 (0x1UL << GOTGCTL_DBCT_Pos)              // 0x00020000 */
+#define GOTGCTL_DBCT                     GOTGCTL_DBCT_Msk                         // Long/short debounce time */
 #define GOTGCTL_ASVLD_Pos                (18U)
-#define GOTGCTL_ASVLD_Msk                (0x1UL << GOTGCTL_ASVLD_Pos)             /*!< 0x00040000 */
-#define GOTGCTL_ASVLD                    GOTGCTL_ASVLD_Msk                        /*!< A-session valid  */
+#define GOTGCTL_ASVLD_Msk                (0x1UL << GOTGCTL_ASVLD_Pos)             // 0x00040000 */
+#define GOTGCTL_ASVLD                    GOTGCTL_ASVLD_Msk                        // A-session valid  */
 #define GOTGCTL_BSESVLD_Pos              (19U)
-#define GOTGCTL_BSESVLD_Msk              (0x1UL << GOTGCTL_BSESVLD_Pos)           /*!< 0x00080000 */
-#define GOTGCTL_BSESVLD                  GOTGCTL_BSESVLD_Msk                      /*!< B-session valid */
+#define GOTGCTL_BSESVLD_Msk              (0x1UL << GOTGCTL_BSESVLD_Pos)           // 0x00080000 */
+#define GOTGCTL_BSESVLD                  GOTGCTL_BSESVLD_Msk                      // B-session valid */
 #define GOTGCTL_OTGVER_Pos               (20U)
-#define GOTGCTL_OTGVER_Msk               (0x1UL << GOTGCTL_OTGVER_Pos)            /*!< 0x00100000 */
-#define GOTGCTL_OTGVER                   GOTGCTL_OTGVER_Msk                       /*!< OTG version  */
+#define GOTGCTL_OTGVER_Msk               (0x1UL << GOTGCTL_OTGVER_Pos)            // 0x00100000 */
+#define GOTGCTL_OTGVER                   GOTGCTL_OTGVER_Msk                       // OTG version  */
 
 /********************  Bit definition for HCFG register  ********************/
 #define HCFG_FSLSPCS_Pos                 (0U)
-#define HCFG_FSLSPCS_Msk                 (0x3UL << HCFG_FSLSPCS_Pos)              /*!< 0x00000003 */
-#define HCFG_FSLSPCS                     HCFG_FSLSPCS_Msk                         /*!< FS/LS PHY clock select  */
-#define HCFG_FSLSPCS_0                   (0x1UL << HCFG_FSLSPCS_Pos)              /*!< 0x00000001 */
-#define HCFG_FSLSPCS_1                   (0x2UL << HCFG_FSLSPCS_Pos)              /*!< 0x00000002 */
+#define HCFG_FSLSPCS_Msk                 (0x3UL << HCFG_FSLSPCS_Pos)              // 0x00000003 */
+#define HCFG_FSLSPCS                     HCFG_FSLSPCS_Msk                         // FS/LS PHY clock select  */
+#define HCFG_FSLSPCS_0                   (0x1UL << HCFG_FSLSPCS_Pos)              // 0x00000001 */
+#define HCFG_FSLSPCS_1                   (0x2UL << HCFG_FSLSPCS_Pos)              // 0x00000002 */
 #define HCFG_FSLSS_Pos                   (2U)
-#define HCFG_FSLSS_Msk                   (0x1UL << HCFG_FSLSS_Pos)                /*!< 0x00000004 */
-#define HCFG_FSLSS                       HCFG_FSLSS_Msk                           /*!< FS- and LS-only support */
+#define HCFG_FSLSS_Msk                   (0x1UL << HCFG_FSLSS_Pos)                // 0x00000004 */
+#define HCFG_FSLSS                       HCFG_FSLSS_Msk                           // FS- and LS-only support */
 
 /********************  Bit definition for DCFG register  ********************/
 #define DCFG_DSPD_Pos                    (0U)
-#define DCFG_DSPD_Msk                    (0x3UL << DCFG_DSPD_Pos)                 /*!< 0x00000003 */
-#define DCFG_DSPD                        DCFG_DSPD_Msk                            /*!< Device speed */
-#define DCFG_DSPD_0                      (0x1UL << DCFG_DSPD_Pos)                 /*!< 0x00000001 */
-#define DCFG_DSPD_1                      (0x2UL << DCFG_DSPD_Pos)                 /*!< 0x00000002 */
+#define DCFG_DSPD_Msk                    (0x3UL << DCFG_DSPD_Pos)                 // 0x00000003 */
+#define DCFG_DSPD                        DCFG_DSPD_Msk                            // Device speed */
+#define DCFG_DSPD_0                      (0x1UL << DCFG_DSPD_Pos)                 // 0x00000001 */
+#define DCFG_DSPD_1                      (0x2UL << DCFG_DSPD_Pos)                 // 0x00000002 */
 #define DCFG_NZLSOHSK_Pos                (2U)
-#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             /*!< 0x00000004 */
-#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        /*!< Nonzero-length status OUT handshake */
+#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             // 0x00000004 */
+#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        // Nonzero-length status OUT handshake */
 
 #define DCFG_DAD_Pos                     (4U)
-#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 /*!< 0x000007F0 */
-#define DCFG_DAD                         DCFG_DAD_Msk                             /*!< Device address */
-#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 /*!< 0x00000010 */
-#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 /*!< 0x00000020 */
-#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 /*!< 0x00000040 */
-#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 /*!< 0x00000080 */
-#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 /*!< 0x00000100 */
-#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 /*!< 0x00000200 */
-#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 /*!< 0x00000400 */
+#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 // 0x000007F0 */
+#define DCFG_DAD                         DCFG_DAD_Msk                             // Device address */
+#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 // 0x00000010 */
+#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 // 0x00000020 */
+#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 // 0x00000040 */
+#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 // 0x00000080 */
+#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 // 0x00000100 */
+#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 // 0x00000200 */
+#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 // 0x00000400 */
 
 #define DCFG_PFIVL_Pos                   (11U)
-#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                /*!< 0x00001800 */
-#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           /*!< Periodic (micro)frame interval */
-#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                /*!< 0x00000800 */
-#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                /*!< 0x00001000 */
+#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                // 0x00001800 */
+#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           // Periodic (micro)frame interval */
+#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                // 0x00000800 */
+#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                // 0x00001000 */
 
 #define DCFG_PERSCHIVL_Pos               (24U)
-#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            /*!< 0x03000000 */
-#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       /*!< Periodic scheduling interval */
-#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            /*!< 0x01000000 */
-#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            /*!< 0x02000000 */
+#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            // 0x03000000 */
+#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       // Periodic scheduling interval */
+#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            // 0x01000000 */
+#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            // 0x02000000 */
 
 /********************  Bit definition for PCGCR register  ********************/
 #define PCGCR_STPPCLK_Pos                (0U)
-#define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos)             /*!< 0x00000001 */
-#define PCGCR_STPPCLK                    PCGCR_STPPCLK_Msk                        /*!< Stop PHY clock */
+#define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos)             // 0x00000001 */
+#define PCGCR_STPPCLK                    PCGCR_STPPCLK_Msk                        // Stop PHY clock */
 #define PCGCR_GATEHCLK_Pos               (1U)
-#define PCGCR_GATEHCLK_Msk               (0x1UL << PCGCR_GATEHCLK_Pos)            /*!< 0x00000002 */
-#define PCGCR_GATEHCLK                   PCGCR_GATEHCLK_Msk                       /*!< Gate HCLK */
+#define PCGCR_GATEHCLK_Msk               (0x1UL << PCGCR_GATEHCLK_Pos)            // 0x00000002 */
+#define PCGCR_GATEHCLK                   PCGCR_GATEHCLK_Msk                       // Gate HCLK */
 #define PCGCR_PHYSUSP_Pos                (4U)
-#define PCGCR_PHYSUSP_Msk                (0x1UL << PCGCR_PHYSUSP_Pos)             /*!< 0x00000010 */
-#define PCGCR_PHYSUSP                    PCGCR_PHYSUSP_Msk                        /*!< PHY suspended */
+#define PCGCR_PHYSUSP_Msk                (0x1UL << PCGCR_PHYSUSP_Pos)             // 0x00000010 */
+#define PCGCR_PHYSUSP                    PCGCR_PHYSUSP_Msk                        // PHY suspended */
 
 /********************  Bit definition for GOTGINT register  ********************/
 #define GOTGINT_SEDET_Pos                (2U)
-#define GOTGINT_SEDET_Msk                (0x1UL << GOTGINT_SEDET_Pos)             /*!< 0x00000004 */
-#define GOTGINT_SEDET                    GOTGINT_SEDET_Msk                        /*!< Session end detected                   */
+#define GOTGINT_SEDET_Msk                (0x1UL << GOTGINT_SEDET_Pos)             // 0x00000004 */
+#define GOTGINT_SEDET                    GOTGINT_SEDET_Msk                        // Session end detected                   */
 #define GOTGINT_SRSSCHG_Pos              (8U)
-#define GOTGINT_SRSSCHG_Msk              (0x1UL << GOTGINT_SRSSCHG_Pos)           /*!< 0x00000100 */
-#define GOTGINT_SRSSCHG                  GOTGINT_SRSSCHG_Msk                      /*!< Session request success status change  */
+#define GOTGINT_SRSSCHG_Msk              (0x1UL << GOTGINT_SRSSCHG_Pos)           // 0x00000100 */
+#define GOTGINT_SRSSCHG                  GOTGINT_SRSSCHG_Msk                      // Session request success status change  */
 #define GOTGINT_HNSSCHG_Pos              (9U)
-#define GOTGINT_HNSSCHG_Msk              (0x1UL << GOTGINT_HNSSCHG_Pos)           /*!< 0x00000200 */
-#define GOTGINT_HNSSCHG                  GOTGINT_HNSSCHG_Msk                      /*!< Host negotiation success status change */
+#define GOTGINT_HNSSCHG_Msk              (0x1UL << GOTGINT_HNSSCHG_Pos)           // 0x00000200 */
+#define GOTGINT_HNSSCHG                  GOTGINT_HNSSCHG_Msk                      // Host negotiation success status change */
 #define GOTGINT_HNGDET_Pos               (17U)
-#define GOTGINT_HNGDET_Msk               (0x1UL << GOTGINT_HNGDET_Pos)            /*!< 0x00020000 */
-#define GOTGINT_HNGDET                   GOTGINT_HNGDET_Msk                       /*!< Host negotiation detected              */
+#define GOTGINT_HNGDET_Msk               (0x1UL << GOTGINT_HNGDET_Pos)            // 0x00020000 */
+#define GOTGINT_HNGDET                   GOTGINT_HNGDET_Msk                       // Host negotiation detected              */
 #define GOTGINT_ADTOCHG_Pos              (18U)
-#define GOTGINT_ADTOCHG_Msk              (0x1UL << GOTGINT_ADTOCHG_Pos)           /*!< 0x00040000 */
-#define GOTGINT_ADTOCHG                  GOTGINT_ADTOCHG_Msk                      /*!< A-device timeout change                */
+#define GOTGINT_ADTOCHG_Msk              (0x1UL << GOTGINT_ADTOCHG_Pos)           // 0x00040000 */
+#define GOTGINT_ADTOCHG                  GOTGINT_ADTOCHG_Msk                      // A-device timeout change                */
 #define GOTGINT_DBCDNE_Pos               (19U)
-#define GOTGINT_DBCDNE_Msk               (0x1UL << GOTGINT_DBCDNE_Pos)            /*!< 0x00080000 */
-#define GOTGINT_DBCDNE                   GOTGINT_DBCDNE_Msk                       /*!< Debounce done                          */
+#define GOTGINT_DBCDNE_Msk               (0x1UL << GOTGINT_DBCDNE_Pos)            // 0x00080000 */
+#define GOTGINT_DBCDNE                   GOTGINT_DBCDNE_Msk                       // Debounce done                          */
 #define GOTGINT_IDCHNG_Pos               (20U)
-#define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos)            /*!< 0x00100000 */
-#define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk                       /*!< Change in ID pin input value           */
+#define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos)            // 0x00100000 */
+#define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk                       // Change in ID pin input value           */
 
 /********************  Bit definition for DCTL register  ********************/
 #define DCTL_RWUSIG_Pos                  (0U)
-#define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos)               /*!< 0x00000001 */
-#define DCTL_RWUSIG                      DCTL_RWUSIG_Msk                          /*!< Remote wakeup signaling */
+#define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos)               // 0x00000001 */
+#define DCTL_RWUSIG                      DCTL_RWUSIG_Msk                          // Remote wakeup signaling */
 #define DCTL_SDIS_Pos                    (1U)
-#define DCTL_SDIS_Msk                    (0x1UL << DCTL_SDIS_Pos)                 /*!< 0x00000002 */
-#define DCTL_SDIS                        DCTL_SDIS_Msk                            /*!< Soft disconnect         */
+#define DCTL_SDIS_Msk                    (0x1UL << DCTL_SDIS_Pos)                 // 0x00000002 */
+#define DCTL_SDIS                        DCTL_SDIS_Msk                            // Soft disconnect         */
 #define DCTL_GINSTS_Pos                  (2U)
-#define DCTL_GINSTS_Msk                  (0x1UL << DCTL_GINSTS_Pos)               /*!< 0x00000004 */
-#define DCTL_GINSTS                      DCTL_GINSTS_Msk                          /*!< Global IN NAK status    */
+#define DCTL_GINSTS_Msk                  (0x1UL << DCTL_GINSTS_Pos)               // 0x00000004 */
+#define DCTL_GINSTS                      DCTL_GINSTS_Msk                          // Global IN NAK status    */
 #define DCTL_GONSTS_Pos                  (3U)
-#define DCTL_GONSTS_Msk                  (0x1UL << DCTL_GONSTS_Pos)               /*!< 0x00000008 */
-#define DCTL_GONSTS                      DCTL_GONSTS_Msk                          /*!< Global OUT NAK status   */
+#define DCTL_GONSTS_Msk                  (0x1UL << DCTL_GONSTS_Pos)               // 0x00000008 */
+#define DCTL_GONSTS                      DCTL_GONSTS_Msk                          // Global OUT NAK status   */
 
 #define DCTL_TCTL_Pos                    (4U)
-#define DCTL_TCTL_Msk                    (0x7UL << DCTL_TCTL_Pos)                 /*!< 0x00000070 */
-#define DCTL_TCTL                        DCTL_TCTL_Msk                            /*!< Test control */
-#define DCTL_TCTL_0                      (0x1UL << DCTL_TCTL_Pos)                 /*!< 0x00000010 */
-#define DCTL_TCTL_1                      (0x2UL << DCTL_TCTL_Pos)                 /*!< 0x00000020 */
-#define DCTL_TCTL_2                      (0x4UL << DCTL_TCTL_Pos)                 /*!< 0x00000040 */
+#define DCTL_TCTL_Msk                    (0x7UL << DCTL_TCTL_Pos)                 // 0x00000070 */
+#define DCTL_TCTL                        DCTL_TCTL_Msk                            // Test control */
+#define DCTL_TCTL_0                      (0x1UL << DCTL_TCTL_Pos)                 // 0x00000010 */
+#define DCTL_TCTL_1                      (0x2UL << DCTL_TCTL_Pos)                 // 0x00000020 */
+#define DCTL_TCTL_2                      (0x4UL << DCTL_TCTL_Pos)                 // 0x00000040 */
 #define DCTL_SGINAK_Pos                  (7U)
-#define DCTL_SGINAK_Msk                  (0x1UL << DCTL_SGINAK_Pos)               /*!< 0x00000080 */
-#define DCTL_SGINAK                      DCTL_SGINAK_Msk                          /*!< Set global IN NAK         */
+#define DCTL_SGINAK_Msk                  (0x1UL << DCTL_SGINAK_Pos)               // 0x00000080 */
+#define DCTL_SGINAK                      DCTL_SGINAK_Msk                          // Set global IN NAK         */
 #define DCTL_CGINAK_Pos                  (8U)
-#define DCTL_CGINAK_Msk                  (0x1UL << DCTL_CGINAK_Pos)               /*!< 0x00000100 */
-#define DCTL_CGINAK                      DCTL_CGINAK_Msk                          /*!< Clear global IN NAK       */
+#define DCTL_CGINAK_Msk                  (0x1UL << DCTL_CGINAK_Pos)               // 0x00000100 */
+#define DCTL_CGINAK                      DCTL_CGINAK_Msk                          // Clear global IN NAK       */
 #define DCTL_SGONAK_Pos                  (9U)
-#define DCTL_SGONAK_Msk                  (0x1UL << DCTL_SGONAK_Pos)               /*!< 0x00000200 */
-#define DCTL_SGONAK                      DCTL_SGONAK_Msk                          /*!< Set global OUT NAK        */
+#define DCTL_SGONAK_Msk                  (0x1UL << DCTL_SGONAK_Pos)               // 0x00000200 */
+#define DCTL_SGONAK                      DCTL_SGONAK_Msk                          // Set global OUT NAK        */
 #define DCTL_CGONAK_Pos                  (10U)
-#define DCTL_CGONAK_Msk                  (0x1UL << DCTL_CGONAK_Pos)               /*!< 0x00000400 */
-#define DCTL_CGONAK                      DCTL_CGONAK_Msk                          /*!< Clear global OUT NAK      */
+#define DCTL_CGONAK_Msk                  (0x1UL << DCTL_CGONAK_Pos)               // 0x00000400 */
+#define DCTL_CGONAK                      DCTL_CGONAK_Msk                          // Clear global OUT NAK      */
 #define DCTL_POPRGDNE_Pos                (11U)
-#define DCTL_POPRGDNE_Msk                (0x1UL << DCTL_POPRGDNE_Pos)             /*!< 0x00000800 */
-#define DCTL_POPRGDNE                    DCTL_POPRGDNE_Msk                        /*!< Power-on programming done */
+#define DCTL_POPRGDNE_Msk                (0x1UL << DCTL_POPRGDNE_Pos)             // 0x00000800 */
+#define DCTL_POPRGDNE                    DCTL_POPRGDNE_Msk                        // Power-on programming done */
 
 /********************  Bit definition for HFIR register  ********************/
 #define HFIR_FRIVL_Pos                   (0U)
-#define HFIR_FRIVL_Msk                   (0xFFFFUL << HFIR_FRIVL_Pos)             /*!< 0x0000FFFF */
-#define HFIR_FRIVL                       HFIR_FRIVL_Msk                           /*!< Frame interval */
+#define HFIR_FRIVL_Msk                   (0xFFFFUL << HFIR_FRIVL_Pos)             // 0x0000FFFF */
+#define HFIR_FRIVL                       HFIR_FRIVL_Msk                           // Frame interval */
 
 /********************  Bit definition for HFNUM register  ********************/
 #define HFNUM_FRNUM_Pos                  (0U)
-#define HFNUM_FRNUM_Msk                  (0xFFFFUL << HFNUM_FRNUM_Pos)            /*!< 0x0000FFFF */
-#define HFNUM_FRNUM                      HFNUM_FRNUM_Msk                          /*!< Frame number         */
+#define HFNUM_FRNUM_Msk                  (0xFFFFUL << HFNUM_FRNUM_Pos)            // 0x0000FFFF */
+#define HFNUM_FRNUM                      HFNUM_FRNUM_Msk                          // Frame number         */
 #define HFNUM_FTREM_Pos                  (16U)
-#define HFNUM_FTREM_Msk                  (0xFFFFUL << HFNUM_FTREM_Pos)            /*!< 0xFFFF0000 */
-#define HFNUM_FTREM                      HFNUM_FTREM_Msk                          /*!< Frame time remaining */
+#define HFNUM_FTREM_Msk                  (0xFFFFUL << HFNUM_FTREM_Pos)            // 0xFFFF0000 */
+#define HFNUM_FTREM                      HFNUM_FTREM_Msk                          // Frame time remaining */
 
 /********************  Bit definition for DSTS register  ********************/
 #define DSTS_SUSPSTS_Pos                 (0U)
-#define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos)              /*!< 0x00000001 */
-#define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk                         /*!< Suspend status   */
+#define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos)              // 0x00000001 */
+#define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk                         // Suspend status   */
 
 #define DSTS_ENUMSPD_Pos                 (1U)
-#define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos)              /*!< 0x00000006 */
-#define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk                         /*!< Enumerated speed */
-#define DSTS_ENUMSPD_0                   (0x1UL << DSTS_ENUMSPD_Pos)              /*!< 0x00000002 */
-#define DSTS_ENUMSPD_1                   (0x2UL << DSTS_ENUMSPD_Pos)              /*!< 0x00000004 */
+#define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos)              // 0x00000006 */
+#define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk                         // Enumerated speed */
+#define DSTS_ENUMSPD_0                   (0x1UL << DSTS_ENUMSPD_Pos)              // 0x00000002 */
+#define DSTS_ENUMSPD_1                   (0x2UL << DSTS_ENUMSPD_Pos)              // 0x00000004 */
 #define DSTS_EERR_Pos                    (3U)
-#define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos)                 /*!< 0x00000008 */
-#define DSTS_EERR                        DSTS_EERR_Msk                            /*!< Erratic error     */
+#define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos)                 // 0x00000008 */
+#define DSTS_EERR                        DSTS_EERR_Msk                            // Erratic error     */
 #define DSTS_FNSOF_Pos                   (8U)
-#define DSTS_FNSOF_Msk                   (0x3FFFUL << DSTS_FNSOF_Pos)             /*!< 0x003FFF00 */
-#define DSTS_FNSOF                       DSTS_FNSOF_Msk                           /*!< Frame number of the received SOF */
+#define DSTS_FNSOF_Msk                   (0x3FFFUL << DSTS_FNSOF_Pos)             // 0x003FFF00 */
+#define DSTS_FNSOF                       DSTS_FNSOF_Msk                           // Frame number of the received SOF */
 
 /********************  Bit definition for GAHBCFG register  ********************/
 #define GAHBCFG_GINT_Pos                 (0U)
-#define GAHBCFG_GINT_Msk                 (0x1UL << GAHBCFG_GINT_Pos)              /*!< 0x00000001 */
-#define GAHBCFG_GINT                     GAHBCFG_GINT_Msk                         /*!< Global interrupt mask */
+#define GAHBCFG_GINT_Msk                 (0x1UL << GAHBCFG_GINT_Pos)              // 0x00000001 */
+#define GAHBCFG_GINT                     GAHBCFG_GINT_Msk                         // Global interrupt mask */
 #define GAHBCFG_HBSTLEN_Pos              (1U)
-#define GAHBCFG_HBSTLEN_Msk              (0xFUL << GAHBCFG_HBSTLEN_Pos)           /*!< 0x0000001E */
-#define GAHBCFG_HBSTLEN                  GAHBCFG_HBSTLEN_Msk                      /*!< Burst length/type */
-#define GAHBCFG_HBSTLEN_0                (0x0UL << GAHBCFG_HBSTLEN_Pos)           /*!< Single */
-#define GAHBCFG_HBSTLEN_1                (0x1UL << GAHBCFG_HBSTLEN_Pos)           /*!< INCR */
-#define GAHBCFG_HBSTLEN_2                (0x3UL << GAHBCFG_HBSTLEN_Pos)           /*!< INCR4 */
-#define GAHBCFG_HBSTLEN_3                (0x5UL << GAHBCFG_HBSTLEN_Pos)           /*!< INCR8 */
-#define GAHBCFG_HBSTLEN_4                (0x7UL << GAHBCFG_HBSTLEN_Pos)           /*!< INCR16 */
+#define GAHBCFG_HBSTLEN_Msk              (0xFUL << GAHBCFG_HBSTLEN_Pos)           // 0x0000001E */
+#define GAHBCFG_HBSTLEN                  GAHBCFG_HBSTLEN_Msk                      // Burst length/type */
+#define GAHBCFG_HBSTLEN_0                (0x0UL << GAHBCFG_HBSTLEN_Pos)           // Single */
+#define GAHBCFG_HBSTLEN_1                (0x1UL << GAHBCFG_HBSTLEN_Pos)           // INCR */
+#define GAHBCFG_HBSTLEN_2                (0x3UL << GAHBCFG_HBSTLEN_Pos)           // INCR4 */
+#define GAHBCFG_HBSTLEN_3                (0x5UL << GAHBCFG_HBSTLEN_Pos)           // INCR8 */
+#define GAHBCFG_HBSTLEN_4                (0x7UL << GAHBCFG_HBSTLEN_Pos)           // INCR16 */
 #define GAHBCFG_DMAEN_Pos                (5U)
-#define GAHBCFG_DMAEN_Msk                (0x1UL << GAHBCFG_DMAEN_Pos)             /*!< 0x00000020 */
-#define GAHBCFG_DMAEN                    GAHBCFG_DMAEN_Msk                        /*!< DMA enable */
+#define GAHBCFG_DMAEN_Msk                (0x1UL << GAHBCFG_DMAEN_Pos)             // 0x00000020 */
+#define GAHBCFG_DMAEN                    GAHBCFG_DMAEN_Msk                        // DMA enable */
 #define GAHBCFG_TXFELVL_Pos              (7U)
-#define GAHBCFG_TXFELVL_Msk              (0x1UL << GAHBCFG_TXFELVL_Pos)           /*!< 0x00000080 */
-#define GAHBCFG_TXFELVL                  GAHBCFG_TXFELVL_Msk                      /*!< TxFIFO empty level */
+#define GAHBCFG_TXFELVL_Msk              (0x1UL << GAHBCFG_TXFELVL_Pos)           // 0x00000080 */
+#define GAHBCFG_TXFELVL                  GAHBCFG_TXFELVL_Msk                      // TxFIFO empty level */
 #define GAHBCFG_PTXFELVL_Pos             (8U)
-#define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos)          /*!< 0x00000100 */
-#define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk                     /*!< Periodic TxFIFO empty level */
+#define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos)          // 0x00000100 */
+#define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk                     // Periodic TxFIFO empty level */
 
 /********************  Bit definition for GUSBCFG register  ********************/
 #define GUSBCFG_TOCAL_Pos                (0U)
-#define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             /*!< 0x00000007 */
-#define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk                        /*!< FS timeout calibration */
-#define GUSBCFG_TOCAL_0                  (0x1UL << GUSBCFG_TOCAL_Pos)             /*!< 0x00000001 */
-#define GUSBCFG_TOCAL_1                  (0x2UL << GUSBCFG_TOCAL_Pos)             /*!< 0x00000002 */
-#define GUSBCFG_TOCAL_2                  (0x4UL << GUSBCFG_TOCAL_Pos)             /*!< 0x00000004 */
+#define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             // 0x00000007 */
+#define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk                        // FS timeout calibration */
+#define GUSBCFG_TOCAL_0                  (0x1UL << GUSBCFG_TOCAL_Pos)             // 0x00000001 */
+#define GUSBCFG_TOCAL_1                  (0x2UL << GUSBCFG_TOCAL_Pos)             // 0x00000002 */
+#define GUSBCFG_TOCAL_2                  (0x4UL << GUSBCFG_TOCAL_Pos)             // 0x00000004 */
 #define GUSBCFG_PHYIF_Pos                (3U)
-#define GUSBCFG_PHYIF_Msk                (0x1UL << GUSBCFG_PHYIF_Pos)             /*!< 0x00000008 */
-#define GUSBCFG_PHYIF                    GUSBCFG_PHYIF_Msk                        /*!< PHY Interface (PHYIf) */
+#define GUSBCFG_PHYIF_Msk                (0x1UL << GUSBCFG_PHYIF_Pos)             // 0x00000008 */
+#define GUSBCFG_PHYIF                    GUSBCFG_PHYIF_Msk                        // PHY Interface (PHYIf) */
 #define GUSBCFG_ULPI_UTMI_SEL_Pos        (4U)
-#define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos)     /*!< 0x00000010 */
-#define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk                /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
+#define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos)     // 0x00000010 */
+#define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk                // ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
 #define GUSBCFG_PHYSEL_Pos               (6U)
-#define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            /*!< 0x00000040 */
-#define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            // 0x00000040 */
+#define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
 #define GUSBCFG_SRPCAP_Pos               (8U)
-#define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            /*!< 0x00000100 */
-#define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       /*!< SRP-capable */
+#define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            // 0x00000100 */
+#define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       // SRP-capable */
 #define GUSBCFG_HNPCAP_Pos               (9U)
-#define GUSBCFG_HNPCAP_Msk               (0x1UL << GUSBCFG_HNPCAP_Pos)            /*!< 0x00000200 */
-#define GUSBCFG_HNPCAP                   GUSBCFG_HNPCAP_Msk                       /*!< HNP-capable */
+#define GUSBCFG_HNPCAP_Msk               (0x1UL << GUSBCFG_HNPCAP_Pos)            // 0x00000200 */
+#define GUSBCFG_HNPCAP                   GUSBCFG_HNPCAP_Msk                       // HNP-capable */
 #define GUSBCFG_TRDT_Pos                 (10U)
-#define GUSBCFG_TRDT_Msk                 (0xFUL << GUSBCFG_TRDT_Pos)              /*!< 0x00003C00 */
-#define GUSBCFG_TRDT                     GUSBCFG_TRDT_Msk                         /*!< USB turnaround time */
-#define GUSBCFG_TRDT_0                   (0x1UL << GUSBCFG_TRDT_Pos)              /*!< 0x00000400 */
-#define GUSBCFG_TRDT_1                   (0x2UL << GUSBCFG_TRDT_Pos)              /*!< 0x00000800 */
-#define GUSBCFG_TRDT_2                   (0x4UL << GUSBCFG_TRDT_Pos)              /*!< 0x00001000 */
-#define GUSBCFG_TRDT_3                   (0x8UL << GUSBCFG_TRDT_Pos)              /*!< 0x00002000 */
+#define GUSBCFG_TRDT_Msk                 (0xFUL << GUSBCFG_TRDT_Pos)              // 0x00003C00 */
+#define GUSBCFG_TRDT                     GUSBCFG_TRDT_Msk                         // USB turnaround time */
+#define GUSBCFG_TRDT_0                   (0x1UL << GUSBCFG_TRDT_Pos)              // 0x00000400 */
+#define GUSBCFG_TRDT_1                   (0x2UL << GUSBCFG_TRDT_Pos)              // 0x00000800 */
+#define GUSBCFG_TRDT_2                   (0x4UL << GUSBCFG_TRDT_Pos)              // 0x00001000 */
+#define GUSBCFG_TRDT_3                   (0x8UL << GUSBCFG_TRDT_Pos)              // 0x00002000 */
 #define GUSBCFG_PHYLPCS_Pos              (15U)
-#define GUSBCFG_PHYLPCS_Msk              (0x1UL << GUSBCFG_PHYLPCS_Pos)           /*!< 0x00008000 */
-#define GUSBCFG_PHYLPCS                  GUSBCFG_PHYLPCS_Msk                      /*!< PHY Low-power clock select */
+#define GUSBCFG_PHYLPCS_Msk              (0x1UL << GUSBCFG_PHYLPCS_Pos)           // 0x00008000 */
+#define GUSBCFG_PHYLPCS                  GUSBCFG_PHYLPCS_Msk                      // PHY Low-power clock select */
 #define GUSBCFG_ULPIFSLS_Pos             (17U)
-#define GUSBCFG_ULPIFSLS_Msk             (0x1UL << GUSBCFG_ULPIFSLS_Pos)          /*!< 0x00020000 */
-#define GUSBCFG_ULPIFSLS                 GUSBCFG_ULPIFSLS_Msk                     /*!< ULPI FS/LS select               */
+#define GUSBCFG_ULPIFSLS_Msk             (0x1UL << GUSBCFG_ULPIFSLS_Pos)          // 0x00020000 */
+#define GUSBCFG_ULPIFSLS                 GUSBCFG_ULPIFSLS_Msk                     // ULPI FS/LS select               */
 #define GUSBCFG_ULPIAR_Pos               (18U)
-#define GUSBCFG_ULPIAR_Msk               (0x1UL << GUSBCFG_ULPIAR_Pos)            /*!< 0x00040000 */
-#define GUSBCFG_ULPIAR                   GUSBCFG_ULPIAR_Msk                       /*!< ULPI Auto-resume                */
+#define GUSBCFG_ULPIAR_Msk               (0x1UL << GUSBCFG_ULPIAR_Pos)            // 0x00040000 */
+#define GUSBCFG_ULPIAR                   GUSBCFG_ULPIAR_Msk                       // ULPI Auto-resume                */
 #define GUSBCFG_ULPICSM_Pos              (19U)
-#define GUSBCFG_ULPICSM_Msk              (0x1UL << GUSBCFG_ULPICSM_Pos)           /*!< 0x00080000 */
-#define GUSBCFG_ULPICSM                  GUSBCFG_ULPICSM_Msk                      /*!< ULPI Clock SuspendM             */
+#define GUSBCFG_ULPICSM_Msk              (0x1UL << GUSBCFG_ULPICSM_Pos)           // 0x00080000 */
+#define GUSBCFG_ULPICSM                  GUSBCFG_ULPICSM_Msk                      // ULPI Clock SuspendM             */
 #define GUSBCFG_ULPIEVBUSD_Pos           (20U)
-#define GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << GUSBCFG_ULPIEVBUSD_Pos)        /*!< 0x00100000 */
-#define GUSBCFG_ULPIEVBUSD               GUSBCFG_ULPIEVBUSD_Msk                   /*!< ULPI External VBUS Drive        */
+#define GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << GUSBCFG_ULPIEVBUSD_Pos)        // 0x00100000 */
+#define GUSBCFG_ULPIEVBUSD               GUSBCFG_ULPIEVBUSD_Msk                   // ULPI External VBUS Drive        */
 #define GUSBCFG_ULPIEVBUSI_Pos           (21U)
-#define GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << GUSBCFG_ULPIEVBUSI_Pos)        /*!< 0x00200000 */
-#define GUSBCFG_ULPIEVBUSI               GUSBCFG_ULPIEVBUSI_Msk                   /*!< ULPI external VBUS indicator    */
+#define GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << GUSBCFG_ULPIEVBUSI_Pos)        // 0x00200000 */
+#define GUSBCFG_ULPIEVBUSI               GUSBCFG_ULPIEVBUSI_Msk                   // ULPI external VBUS indicator    */
 #define GUSBCFG_TSDPS_Pos                (22U)
-#define GUSBCFG_TSDPS_Msk                (0x1UL << GUSBCFG_TSDPS_Pos)             /*!< 0x00400000 */
-#define GUSBCFG_TSDPS                    GUSBCFG_TSDPS_Msk                        /*!< TermSel DLine pulsing selection */
+#define GUSBCFG_TSDPS_Msk                (0x1UL << GUSBCFG_TSDPS_Pos)             // 0x00400000 */
+#define GUSBCFG_TSDPS                    GUSBCFG_TSDPS_Msk                        // TermSel DLine pulsing selection */
 #define GUSBCFG_PCCI_Pos                 (23U)
-#define GUSBCFG_PCCI_Msk                 (0x1UL << GUSBCFG_PCCI_Pos)              /*!< 0x00800000 */
-#define GUSBCFG_PCCI                     GUSBCFG_PCCI_Msk                         /*!< Indicator complement            */
+#define GUSBCFG_PCCI_Msk                 (0x1UL << GUSBCFG_PCCI_Pos)              // 0x00800000 */
+#define GUSBCFG_PCCI                     GUSBCFG_PCCI_Msk                         // Indicator complement            */
 #define GUSBCFG_PTCI_Pos                 (24U)
-#define GUSBCFG_PTCI_Msk                 (0x1UL << GUSBCFG_PTCI_Pos)              /*!< 0x01000000 */
-#define GUSBCFG_PTCI                     GUSBCFG_PTCI_Msk                         /*!< Indicator pass through          */
+#define GUSBCFG_PTCI_Msk                 (0x1UL << GUSBCFG_PTCI_Pos)              // 0x01000000 */
+#define GUSBCFG_PTCI                     GUSBCFG_PTCI_Msk                         // Indicator pass through          */
 #define GUSBCFG_ULPIIPD_Pos              (25U)
-#define GUSBCFG_ULPIIPD_Msk              (0x1UL << GUSBCFG_ULPIIPD_Pos)           /*!< 0x02000000 */
-#define GUSBCFG_ULPIIPD                  GUSBCFG_ULPIIPD_Msk                      /*!< ULPI interface protect disable  */
+#define GUSBCFG_ULPIIPD_Msk              (0x1UL << GUSBCFG_ULPIIPD_Pos)           // 0x02000000 */
+#define GUSBCFG_ULPIIPD                  GUSBCFG_ULPIIPD_Msk                      // ULPI interface protect disable  */
 #define GUSBCFG_FHMOD_Pos                (29U)
-#define GUSBCFG_FHMOD_Msk                (0x1UL << GUSBCFG_FHMOD_Pos)             /*!< 0x20000000 */
-#define GUSBCFG_FHMOD                    GUSBCFG_FHMOD_Msk                        /*!< Forced host mode                */
+#define GUSBCFG_FHMOD_Msk                (0x1UL << GUSBCFG_FHMOD_Pos)             // 0x20000000 */
+#define GUSBCFG_FHMOD                    GUSBCFG_FHMOD_Msk                        // Forced host mode                */
 #define GUSBCFG_FDMOD_Pos                (30U)
-#define GUSBCFG_FDMOD_Msk                (0x1UL << GUSBCFG_FDMOD_Pos)             /*!< 0x40000000 */
-#define GUSBCFG_FDMOD                    GUSBCFG_FDMOD_Msk                        /*!< Forced peripheral mode          */
+#define GUSBCFG_FDMOD_Msk                (0x1UL << GUSBCFG_FDMOD_Pos)             // 0x40000000 */
+#define GUSBCFG_FDMOD                    GUSBCFG_FDMOD_Msk                        // Forced peripheral mode          */
 #define GUSBCFG_CTXPKT_Pos               (31U)
-#define GUSBCFG_CTXPKT_Msk               (0x1UL << GUSBCFG_CTXPKT_Pos)            /*!< 0x80000000 */
-#define GUSBCFG_CTXPKT                   GUSBCFG_CTXPKT_Msk                       /*!< Corrupt Tx packet               */
+#define GUSBCFG_CTXPKT_Msk               (0x1UL << GUSBCFG_CTXPKT_Pos)            // 0x80000000 */
+#define GUSBCFG_CTXPKT                   GUSBCFG_CTXPKT_Msk                       // Corrupt Tx packet               */
 
 /********************  Bit definition for GRSTCTL register  ********************/
 #define GRSTCTL_CSRST_Pos                (0U)
-#define GRSTCTL_CSRST_Msk                (0x1UL << GRSTCTL_CSRST_Pos)             /*!< 0x00000001 */
-#define GRSTCTL_CSRST                    GRSTCTL_CSRST_Msk                        /*!< Core soft reset          */
+#define GRSTCTL_CSRST_Msk                (0x1UL << GRSTCTL_CSRST_Pos)             // 0x00000001 */
+#define GRSTCTL_CSRST                    GRSTCTL_CSRST_Msk                        // Core soft reset          */
 #define GRSTCTL_HSRST_Pos                (1U)
-#define GRSTCTL_HSRST_Msk                (0x1UL << GRSTCTL_HSRST_Pos)             /*!< 0x00000002 */
-#define GRSTCTL_HSRST                    GRSTCTL_HSRST_Msk                        /*!< HCLK soft reset          */
+#define GRSTCTL_HSRST_Msk                (0x1UL << GRSTCTL_HSRST_Pos)             // 0x00000002 */
+#define GRSTCTL_HSRST                    GRSTCTL_HSRST_Msk                        // HCLK soft reset          */
 #define GRSTCTL_FCRST_Pos                (2U)
-#define GRSTCTL_FCRST_Msk                (0x1UL << GRSTCTL_FCRST_Pos)             /*!< 0x00000004 */
-#define GRSTCTL_FCRST                    GRSTCTL_FCRST_Msk                        /*!< Host frame counter reset */
+#define GRSTCTL_FCRST_Msk                (0x1UL << GRSTCTL_FCRST_Pos)             // 0x00000004 */
+#define GRSTCTL_FCRST                    GRSTCTL_FCRST_Msk                        // Host frame counter reset */
 #define GRSTCTL_RXFFLSH_Pos              (4U)
-#define GRSTCTL_RXFFLSH_Msk              (0x1UL << GRSTCTL_RXFFLSH_Pos)           /*!< 0x00000010 */
-#define GRSTCTL_RXFFLSH                  GRSTCTL_RXFFLSH_Msk                      /*!< RxFIFO flush             */
+#define GRSTCTL_RXFFLSH_Msk              (0x1UL << GRSTCTL_RXFFLSH_Pos)           // 0x00000010 */
+#define GRSTCTL_RXFFLSH                  GRSTCTL_RXFFLSH_Msk                      // RxFIFO flush             */
 #define GRSTCTL_TXFFLSH_Pos              (5U)
-#define GRSTCTL_TXFFLSH_Msk              (0x1UL << GRSTCTL_TXFFLSH_Pos)           /*!< 0x00000020 */
-#define GRSTCTL_TXFFLSH                  GRSTCTL_TXFFLSH_Msk                      /*!< TxFIFO flush             */
+#define GRSTCTL_TXFFLSH_Msk              (0x1UL << GRSTCTL_TXFFLSH_Pos)           // 0x00000020 */
+#define GRSTCTL_TXFFLSH                  GRSTCTL_TXFFLSH_Msk                      // TxFIFO flush             */
 #define GRSTCTL_TXFNUM_Pos               (6U)
-#define GRSTCTL_TXFNUM_Msk               (0x1FUL << GRSTCTL_TXFNUM_Pos)           /*!< 0x000007C0 */
-#define GRSTCTL_TXFNUM                   GRSTCTL_TXFNUM_Msk                       /*!< TxFIFO number */
-#define GRSTCTL_TXFNUM_0                 (0x01UL << GRSTCTL_TXFNUM_Pos)           /*!< 0x00000040 */
-#define GRSTCTL_TXFNUM_1                 (0x02UL << GRSTCTL_TXFNUM_Pos)           /*!< 0x00000080 */
-#define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           /*!< 0x00000100 */
-#define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           /*!< 0x00000200 */
-#define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           /*!< 0x00000400 */
+#define GRSTCTL_TXFNUM_Msk               (0x1FUL << GRSTCTL_TXFNUM_Pos)           // 0x000007C0 */
+#define GRSTCTL_TXFNUM                   GRSTCTL_TXFNUM_Msk                       // TxFIFO number */
+#define GRSTCTL_TXFNUM_0                 (0x01UL << GRSTCTL_TXFNUM_Pos)           // 0x00000040 */
+#define GRSTCTL_TXFNUM_1                 (0x02UL << GRSTCTL_TXFNUM_Pos)           // 0x00000080 */
+#define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           // 0x00000100 */
+#define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           // 0x00000200 */
+#define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           // 0x00000400 */
 #define GRSTCTL_DMAREQ_Pos               (30U)
-#define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            /*!< 0x40000000 */
-#define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       /*!< DMA request signal */
+#define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            // 0x40000000 */
+#define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       // DMA request signal */
 #define GRSTCTL_AHBIDL_Pos               (31U)
-#define GRSTCTL_AHBIDL_Msk               (0x1UL << GRSTCTL_AHBIDL_Pos)            /*!< 0x80000000 */
-#define GRSTCTL_AHBIDL                   GRSTCTL_AHBIDL_Msk                       /*!< AHB master idle */
+#define GRSTCTL_AHBIDL_Msk               (0x1UL << GRSTCTL_AHBIDL_Pos)            // 0x80000000 */
+#define GRSTCTL_AHBIDL                   GRSTCTL_AHBIDL_Msk                       // AHB master idle */
 
 /********************  Bit definition for DIEPMSK register  ********************/
 #define DIEPMSK_XFRCM_Pos                (0U)
-#define DIEPMSK_XFRCM_Msk                (0x1UL << DIEPMSK_XFRCM_Pos)             /*!< 0x00000001 */
-#define DIEPMSK_XFRCM                    DIEPMSK_XFRCM_Msk                        /*!< Transfer completed interrupt mask                 */
+#define DIEPMSK_XFRCM_Msk                (0x1UL << DIEPMSK_XFRCM_Pos)             // 0x00000001 */
+#define DIEPMSK_XFRCM                    DIEPMSK_XFRCM_Msk                        // Transfer completed interrupt mask                 */
 #define DIEPMSK_EPDM_Pos                 (1U)
-#define DIEPMSK_EPDM_Msk                 (0x1UL << DIEPMSK_EPDM_Pos)              /*!< 0x00000002 */
-#define DIEPMSK_EPDM                     DIEPMSK_EPDM_Msk                         /*!< Endpoint disabled interrupt mask                  */
+#define DIEPMSK_EPDM_Msk                 (0x1UL << DIEPMSK_EPDM_Pos)              // 0x00000002 */
+#define DIEPMSK_EPDM                     DIEPMSK_EPDM_Msk                         // Endpoint disabled interrupt mask                  */
 #define DIEPMSK_TOM_Pos                  (3U)
-#define DIEPMSK_TOM_Msk                  (0x1UL << DIEPMSK_TOM_Pos)               /*!< 0x00000008 */
-#define DIEPMSK_TOM                      DIEPMSK_TOM_Msk                          /*!< Timeout condition mask (nonisochronous endpoints) */
+#define DIEPMSK_TOM_Msk                  (0x1UL << DIEPMSK_TOM_Pos)               // 0x00000008 */
+#define DIEPMSK_TOM                      DIEPMSK_TOM_Msk                          // Timeout condition mask (nonisochronous endpoints) */
 #define DIEPMSK_ITTXFEMSK_Pos            (4U)
-#define DIEPMSK_ITTXFEMSK_Msk            (0x1UL << DIEPMSK_ITTXFEMSK_Pos)         /*!< 0x00000010 */
-#define DIEPMSK_ITTXFEMSK                DIEPMSK_ITTXFEMSK_Msk                    /*!< IN token received when TxFIFO empty mask          */
+#define DIEPMSK_ITTXFEMSK_Msk            (0x1UL << DIEPMSK_ITTXFEMSK_Pos)         // 0x00000010 */
+#define DIEPMSK_ITTXFEMSK                DIEPMSK_ITTXFEMSK_Msk                    // IN token received when TxFIFO empty mask          */
 #define DIEPMSK_INEPNMM_Pos              (5U)
-#define DIEPMSK_INEPNMM_Msk              (0x1UL << DIEPMSK_INEPNMM_Pos)           /*!< 0x00000020 */
-#define DIEPMSK_INEPNMM                  DIEPMSK_INEPNMM_Msk                      /*!< IN token received with EP mismatch mask           */
+#define DIEPMSK_INEPNMM_Msk              (0x1UL << DIEPMSK_INEPNMM_Pos)           // 0x00000020 */
+#define DIEPMSK_INEPNMM                  DIEPMSK_INEPNMM_Msk                      // IN token received with EP mismatch mask           */
 #define DIEPMSK_INEPNEM_Pos              (6U)
-#define DIEPMSK_INEPNEM_Msk              (0x1UL << DIEPMSK_INEPNEM_Pos)           /*!< 0x00000040 */
-#define DIEPMSK_INEPNEM                  DIEPMSK_INEPNEM_Msk                      /*!< IN endpoint NAK effective mask                    */
+#define DIEPMSK_INEPNEM_Msk              (0x1UL << DIEPMSK_INEPNEM_Pos)           // 0x00000040 */
+#define DIEPMSK_INEPNEM                  DIEPMSK_INEPNEM_Msk                      // IN endpoint NAK effective mask                    */
 #define DIEPMSK_TXFURM_Pos               (8U)
-#define DIEPMSK_TXFURM_Msk               (0x1UL << DIEPMSK_TXFURM_Pos)            /*!< 0x00000100 */
-#define DIEPMSK_TXFURM                   DIEPMSK_TXFURM_Msk                       /*!< FIFO underrun mask                                */
+#define DIEPMSK_TXFURM_Msk               (0x1UL << DIEPMSK_TXFURM_Pos)            // 0x00000100 */
+#define DIEPMSK_TXFURM                   DIEPMSK_TXFURM_Msk                       // FIFO underrun mask                                */
 #define DIEPMSK_BIM_Pos                  (9U)
-#define DIEPMSK_BIM_Msk                  (0x1UL << DIEPMSK_BIM_Pos)               /*!< 0x00000200 */
-#define DIEPMSK_BIM                      DIEPMSK_BIM_Msk                          /*!< BNA interrupt mask                                */
+#define DIEPMSK_BIM_Msk                  (0x1UL << DIEPMSK_BIM_Pos)               // 0x00000200 */
+#define DIEPMSK_BIM                      DIEPMSK_BIM_Msk                          // BNA interrupt mask                                */
 
 /********************  Bit definition for HPTXSTS register  ********************/
 #define HPTXSTS_PTXFSAVL_Pos             (0U)
-#define HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos)       /*!< 0x0000FFFF */
-#define HPTXSTS_PTXFSAVL                 HPTXSTS_PTXFSAVL_Msk                     /*!< Periodic transmit data FIFO space available     */
+#define HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << HPTXSTS_PTXFSAVL_Pos)       // 0x0000FFFF */
+#define HPTXSTS_PTXFSAVL                 HPTXSTS_PTXFSAVL_Msk                     // Periodic transmit data FIFO space available     */
 #define HPTXSTS_PTXQSAV_Pos              (16U)
-#define HPTXSTS_PTXQSAV_Msk              (0xFFUL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00FF0000 */
-#define HPTXSTS_PTXQSAV                  HPTXSTS_PTXQSAV_Msk                      /*!< Periodic transmit request queue space available */
-#define HPTXSTS_PTXQSAV_0                (0x01UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00010000 */
-#define HPTXSTS_PTXQSAV_1                (0x02UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00020000 */
-#define HPTXSTS_PTXQSAV_2                (0x04UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00040000 */
-#define HPTXSTS_PTXQSAV_3                (0x08UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00080000 */
-#define HPTXSTS_PTXQSAV_4                (0x10UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00100000 */
-#define HPTXSTS_PTXQSAV_5                (0x20UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00200000 */
-#define HPTXSTS_PTXQSAV_6                (0x40UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00400000 */
-#define HPTXSTS_PTXQSAV_7                (0x80UL << HPTXSTS_PTXQSAV_Pos)          /*!< 0x00800000 */
+#define HPTXSTS_PTXQSAV_Msk              (0xFFUL << HPTXSTS_PTXQSAV_Pos)          // 0x00FF0000 */
+#define HPTXSTS_PTXQSAV                  HPTXSTS_PTXQSAV_Msk                      // Periodic transmit request queue space available */
+#define HPTXSTS_PTXQSAV_0                (0x01UL << HPTXSTS_PTXQSAV_Pos)          // 0x00010000 */
+#define HPTXSTS_PTXQSAV_1                (0x02UL << HPTXSTS_PTXQSAV_Pos)          // 0x00020000 */
+#define HPTXSTS_PTXQSAV_2                (0x04UL << HPTXSTS_PTXQSAV_Pos)          // 0x00040000 */
+#define HPTXSTS_PTXQSAV_3                (0x08UL << HPTXSTS_PTXQSAV_Pos)          // 0x00080000 */
+#define HPTXSTS_PTXQSAV_4                (0x10UL << HPTXSTS_PTXQSAV_Pos)          // 0x00100000 */
+#define HPTXSTS_PTXQSAV_5                (0x20UL << HPTXSTS_PTXQSAV_Pos)          // 0x00200000 */
+#define HPTXSTS_PTXQSAV_6                (0x40UL << HPTXSTS_PTXQSAV_Pos)          // 0x00400000 */
+#define HPTXSTS_PTXQSAV_7                (0x80UL << HPTXSTS_PTXQSAV_Pos)          // 0x00800000 */
 
 #define HPTXSTS_PTXQTOP_Pos              (24U)
-#define HPTXSTS_PTXQTOP_Msk              (0xFFUL << HPTXSTS_PTXQTOP_Pos)          /*!< 0xFF000000 */
-#define HPTXSTS_PTXQTOP                  HPTXSTS_PTXQTOP_Msk                      /*!< Top of the periodic transmit request queue */
-#define HPTXSTS_PTXQTOP_0                (0x01UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x01000000 */
-#define HPTXSTS_PTXQTOP_1                (0x02UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x02000000 */
-#define HPTXSTS_PTXQTOP_2                (0x04UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x04000000 */
-#define HPTXSTS_PTXQTOP_3                (0x08UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x08000000 */
-#define HPTXSTS_PTXQTOP_4                (0x10UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x10000000 */
-#define HPTXSTS_PTXQTOP_5                (0x20UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x20000000 */
-#define HPTXSTS_PTXQTOP_6                (0x40UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x40000000 */
-#define HPTXSTS_PTXQTOP_7                (0x80UL << HPTXSTS_PTXQTOP_Pos)          /*!< 0x80000000 */
+#define HPTXSTS_PTXQTOP_Msk              (0xFFUL << HPTXSTS_PTXQTOP_Pos)          // 0xFF000000 */
+#define HPTXSTS_PTXQTOP                  HPTXSTS_PTXQTOP_Msk                      // Top of the periodic transmit request queue */
+#define HPTXSTS_PTXQTOP_0                (0x01UL << HPTXSTS_PTXQTOP_Pos)          // 0x01000000 */
+#define HPTXSTS_PTXQTOP_1                (0x02UL << HPTXSTS_PTXQTOP_Pos)          // 0x02000000 */
+#define HPTXSTS_PTXQTOP_2                (0x04UL << HPTXSTS_PTXQTOP_Pos)          // 0x04000000 */
+#define HPTXSTS_PTXQTOP_3                (0x08UL << HPTXSTS_PTXQTOP_Pos)          // 0x08000000 */
+#define HPTXSTS_PTXQTOP_4                (0x10UL << HPTXSTS_PTXQTOP_Pos)          // 0x10000000 */
+#define HPTXSTS_PTXQTOP_5                (0x20UL << HPTXSTS_PTXQTOP_Pos)          // 0x20000000 */
+#define HPTXSTS_PTXQTOP_6                (0x40UL << HPTXSTS_PTXQTOP_Pos)          // 0x40000000 */
+#define HPTXSTS_PTXQTOP_7                (0x80UL << HPTXSTS_PTXQTOP_Pos)          // 0x80000000 */
 
 /********************  Bit definition for HAINT register  ********************/
 #define HAINT_HAINT_Pos                  (0U)
-#define HAINT_HAINT_Msk                  (0xFFFFUL << HAINT_HAINT_Pos)            /*!< 0x0000FFFF */
-#define HAINT_HAINT                      HAINT_HAINT_Msk                          /*!< Channel interrupts */
+#define HAINT_HAINT_Msk                  (0xFFFFUL << HAINT_HAINT_Pos)            // 0x0000FFFF */
+#define HAINT_HAINT                      HAINT_HAINT_Msk                          // Channel interrupts */
 
 /********************  Bit definition for DOEPMSK register  ********************/
 #define DOEPMSK_XFRCM_Pos                (0U)
-#define DOEPMSK_XFRCM_Msk                (0x1UL << DOEPMSK_XFRCM_Pos)             /*!< 0x00000001 */
-#define DOEPMSK_XFRCM                    DOEPMSK_XFRCM_Msk                        /*!< Transfer completed interrupt mask */
+#define DOEPMSK_XFRCM_Msk                (0x1UL << DOEPMSK_XFRCM_Pos)             // 0x00000001 */
+#define DOEPMSK_XFRCM                    DOEPMSK_XFRCM_Msk                        // Transfer completed interrupt mask */
 #define DOEPMSK_EPDM_Pos                 (1U)
-#define DOEPMSK_EPDM_Msk                 (0x1UL << DOEPMSK_EPDM_Pos)              /*!< 0x00000002 */
-#define DOEPMSK_EPDM                     DOEPMSK_EPDM_Msk                         /*!< Endpoint disabled interrupt mask               */
+#define DOEPMSK_EPDM_Msk                 (0x1UL << DOEPMSK_EPDM_Pos)              // 0x00000002 */
+#define DOEPMSK_EPDM                     DOEPMSK_EPDM_Msk                         // Endpoint disabled interrupt mask               */
 #define DOEPMSK_AHBERRM_Pos              (2U)
-#define DOEPMSK_AHBERRM_Msk              (0x1UL << DOEPMSK_AHBERRM_Pos)           /*!< 0x00000004 */
-#define DOEPMSK_AHBERRM                  DOEPMSK_AHBERRM_Msk                      /*!< OUT transaction AHB Error interrupt mask    */
+#define DOEPMSK_AHBERRM_Msk              (0x1UL << DOEPMSK_AHBERRM_Pos)           // 0x00000004 */
+#define DOEPMSK_AHBERRM                  DOEPMSK_AHBERRM_Msk                      // OUT transaction AHB Error interrupt mask    */
 #define DOEPMSK_STUPM_Pos                (3U)
-#define DOEPMSK_STUPM_Msk                (0x1UL << DOEPMSK_STUPM_Pos)             /*!< 0x00000008 */
-#define DOEPMSK_STUPM                    DOEPMSK_STUPM_Msk                        /*!< SETUP phase done mask                          */
+#define DOEPMSK_STUPM_Msk                (0x1UL << DOEPMSK_STUPM_Pos)             // 0x00000008 */
+#define DOEPMSK_STUPM                    DOEPMSK_STUPM_Msk                        // SETUP phase done mask                          */
 #define DOEPMSK_OTEPDM_Pos               (4U)
-#define DOEPMSK_OTEPDM_Msk               (0x1UL << DOEPMSK_OTEPDM_Pos)            /*!< 0x00000010 */
-#define DOEPMSK_OTEPDM                   DOEPMSK_OTEPDM_Msk                       /*!< OUT token received when endpoint disabled mask */
+#define DOEPMSK_OTEPDM_Msk               (0x1UL << DOEPMSK_OTEPDM_Pos)            // 0x00000010 */
+#define DOEPMSK_OTEPDM                   DOEPMSK_OTEPDM_Msk                       // OUT token received when endpoint disabled mask */
 #define DOEPMSK_OTEPSPRM_Pos             (5U)
-#define DOEPMSK_OTEPSPRM_Msk             (0x1UL << DOEPMSK_OTEPSPRM_Pos)          /*!< 0x00000020 */
-#define DOEPMSK_OTEPSPRM                 DOEPMSK_OTEPSPRM_Msk                     /*!< Status Phase Received mask                     */
+#define DOEPMSK_OTEPSPRM_Msk             (0x1UL << DOEPMSK_OTEPSPRM_Pos)          // 0x00000020 */
+#define DOEPMSK_OTEPSPRM                 DOEPMSK_OTEPSPRM_Msk                     // Status Phase Received mask                     */
 #define DOEPMSK_B2BSTUP_Pos              (6U)
-#define DOEPMSK_B2BSTUP_Msk              (0x1UL << DOEPMSK_B2BSTUP_Pos)           /*!< 0x00000040 */
-#define DOEPMSK_B2BSTUP                  DOEPMSK_B2BSTUP_Msk                      /*!< Back-to-back SETUP packets received mask       */
+#define DOEPMSK_B2BSTUP_Msk              (0x1UL << DOEPMSK_B2BSTUP_Pos)           // 0x00000040 */
+#define DOEPMSK_B2BSTUP                  DOEPMSK_B2BSTUP_Msk                      // Back-to-back SETUP packets received mask       */
 #define DOEPMSK_OPEM_Pos                 (8U)
-#define DOEPMSK_OPEM_Msk                 (0x1UL << DOEPMSK_OPEM_Pos)              /*!< 0x00000100 */
-#define DOEPMSK_OPEM                     DOEPMSK_OPEM_Msk                         /*!< OUT packet error mask                          */
+#define DOEPMSK_OPEM_Msk                 (0x1UL << DOEPMSK_OPEM_Pos)              // 0x00000100 */
+#define DOEPMSK_OPEM                     DOEPMSK_OPEM_Msk                         // OUT packet error mask                          */
 #define DOEPMSK_BOIM_Pos                 (9U)
-#define DOEPMSK_BOIM_Msk                 (0x1UL << DOEPMSK_BOIM_Pos)              /*!< 0x00000200 */
-#define DOEPMSK_BOIM                     DOEPMSK_BOIM_Msk                         /*!< BNA interrupt mask                             */
+#define DOEPMSK_BOIM_Msk                 (0x1UL << DOEPMSK_BOIM_Pos)              // 0x00000200 */
+#define DOEPMSK_BOIM                     DOEPMSK_BOIM_Msk                         // BNA interrupt mask                             */
 #define DOEPMSK_BERRM_Pos                (12U)
-#define DOEPMSK_BERRM_Msk                (0x1UL << DOEPMSK_BERRM_Pos)             /*!< 0x00001000 */
-#define DOEPMSK_BERRM                    DOEPMSK_BERRM_Msk                        /*!< Babble error interrupt mask                   */
+#define DOEPMSK_BERRM_Msk                (0x1UL << DOEPMSK_BERRM_Pos)             // 0x00001000 */
+#define DOEPMSK_BERRM                    DOEPMSK_BERRM_Msk                        // Babble error interrupt mask                   */
 #define DOEPMSK_NAKM_Pos                 (13U)
-#define DOEPMSK_NAKM_Msk                 (0x1UL << DOEPMSK_NAKM_Pos)              /*!< 0x00002000 */
-#define DOEPMSK_NAKM                     DOEPMSK_NAKM_Msk                         /*!< OUT Packet NAK interrupt mask                  */
+#define DOEPMSK_NAKM_Msk                 (0x1UL << DOEPMSK_NAKM_Pos)              // 0x00002000 */
+#define DOEPMSK_NAKM                     DOEPMSK_NAKM_Msk                         // OUT Packet NAK interrupt mask                  */
 #define DOEPMSK_NYETM_Pos                (14U)
-#define DOEPMSK_NYETM_Msk                (0x1UL << DOEPMSK_NYETM_Pos)             /*!< 0x00004000 */
-#define DOEPMSK_NYETM                    DOEPMSK_NYETM_Msk                        /*!< NYET interrupt mask                           */
+#define DOEPMSK_NYETM_Msk                (0x1UL << DOEPMSK_NYETM_Pos)             // 0x00004000 */
+#define DOEPMSK_NYETM                    DOEPMSK_NYETM_Msk                        // NYET interrupt mask                           */
 
 /********************  Bit definition for GINTSTS register  ********************/
 #define GINTSTS_CMOD_Pos                 (0U)
-#define GINTSTS_CMOD_Msk                 (0x1UL << GINTSTS_CMOD_Pos)              /*!< 0x00000001 */
-#define GINTSTS_CMOD                     GINTSTS_CMOD_Msk                         /*!< Current mode of operation                      */
+#define GINTSTS_CMOD_Msk                 (0x1UL << GINTSTS_CMOD_Pos)              // 0x00000001 */
+#define GINTSTS_CMOD                     GINTSTS_CMOD_Msk                         // Current mode of operation                      */
 #define GINTSTS_MMIS_Pos                 (1U)
-#define GINTSTS_MMIS_Msk                 (0x1UL << GINTSTS_MMIS_Pos)              /*!< 0x00000002 */
-#define GINTSTS_MMIS                     GINTSTS_MMIS_Msk                         /*!< Mode mismatch interrupt                        */
+#define GINTSTS_MMIS_Msk                 (0x1UL << GINTSTS_MMIS_Pos)              // 0x00000002 */
+#define GINTSTS_MMIS                     GINTSTS_MMIS_Msk                         // Mode mismatch interrupt                        */
 #define GINTSTS_OTGINT_Pos               (2U)
-#define GINTSTS_OTGINT_Msk               (0x1UL << GINTSTS_OTGINT_Pos)            /*!< 0x00000004 */
-#define GINTSTS_OTGINT                   GINTSTS_OTGINT_Msk                       /*!< OTG interrupt                                  */
+#define GINTSTS_OTGINT_Msk               (0x1UL << GINTSTS_OTGINT_Pos)            // 0x00000004 */
+#define GINTSTS_OTGINT                   GINTSTS_OTGINT_Msk                       // OTG interrupt                                  */
 #define GINTSTS_SOF_Pos                  (3U)
-#define GINTSTS_SOF_Msk                  (0x1UL << GINTSTS_SOF_Pos)               /*!< 0x00000008 */
-#define GINTSTS_SOF                      GINTSTS_SOF_Msk                          /*!< Start of frame                                 */
+#define GINTSTS_SOF_Msk                  (0x1UL << GINTSTS_SOF_Pos)               // 0x00000008 */
+#define GINTSTS_SOF                      GINTSTS_SOF_Msk                          // Start of frame                                 */
 #define GINTSTS_RXFLVL_Pos               (4U)
-#define GINTSTS_RXFLVL_Msk               (0x1UL << GINTSTS_RXFLVL_Pos)            /*!< 0x00000010 */
-#define GINTSTS_RXFLVL                   GINTSTS_RXFLVL_Msk                       /*!< RxFIFO nonempty                                */
+#define GINTSTS_RXFLVL_Msk               (0x1UL << GINTSTS_RXFLVL_Pos)            // 0x00000010 */
+#define GINTSTS_RXFLVL                   GINTSTS_RXFLVL_Msk                       // RxFIFO nonempty                                */
 #define GINTSTS_NPTXFE_Pos               (5U)
-#define GINTSTS_NPTXFE_Msk               (0x1UL << GINTSTS_NPTXFE_Pos)            /*!< 0x00000020 */
-#define GINTSTS_NPTXFE                   GINTSTS_NPTXFE_Msk                       /*!< Nonperiodic TxFIFO empty                       */
+#define GINTSTS_NPTXFE_Msk               (0x1UL << GINTSTS_NPTXFE_Pos)            // 0x00000020 */
+#define GINTSTS_NPTXFE                   GINTSTS_NPTXFE_Msk                       // Nonperiodic TxFIFO empty                       */
 #define GINTSTS_GINAKEFF_Pos             (6U)
-#define GINTSTS_GINAKEFF_Msk             (0x1UL << GINTSTS_GINAKEFF_Pos)          /*!< 0x00000040 */
-#define GINTSTS_GINAKEFF                 GINTSTS_GINAKEFF_Msk                     /*!< Global IN nonperiodic NAK effective            */
+#define GINTSTS_GINAKEFF_Msk             (0x1UL << GINTSTS_GINAKEFF_Pos)          // 0x00000040 */
+#define GINTSTS_GINAKEFF                 GINTSTS_GINAKEFF_Msk                     // Global IN nonperiodic NAK effective            */
 #define GINTSTS_BOUTNAKEFF_Pos           (7U)
-#define GINTSTS_BOUTNAKEFF_Msk           (0x1UL << GINTSTS_BOUTNAKEFF_Pos)        /*!< 0x00000080 */
-#define GINTSTS_BOUTNAKEFF               GINTSTS_BOUTNAKEFF_Msk                   /*!< Global OUT NAK effective                       */
+#define GINTSTS_BOUTNAKEFF_Msk           (0x1UL << GINTSTS_BOUTNAKEFF_Pos)        // 0x00000080 */
+#define GINTSTS_BOUTNAKEFF               GINTSTS_BOUTNAKEFF_Msk                   // Global OUT NAK effective                       */
 #define GINTSTS_ESUSP_Pos                (10U)
-#define GINTSTS_ESUSP_Msk                (0x1UL << GINTSTS_ESUSP_Pos)             /*!< 0x00000400 */
-#define GINTSTS_ESUSP                    GINTSTS_ESUSP_Msk                        /*!< Early suspend                                  */
+#define GINTSTS_ESUSP_Msk                (0x1UL << GINTSTS_ESUSP_Pos)             // 0x00000400 */
+#define GINTSTS_ESUSP                    GINTSTS_ESUSP_Msk                        // Early suspend                                  */
 #define GINTSTS_USBSUSP_Pos              (11U)
-#define GINTSTS_USBSUSP_Msk              (0x1UL << GINTSTS_USBSUSP_Pos)           /*!< 0x00000800 */
-#define GINTSTS_USBSUSP                  GINTSTS_USBSUSP_Msk                      /*!< USB suspend                                    */
+#define GINTSTS_USBSUSP_Msk              (0x1UL << GINTSTS_USBSUSP_Pos)           // 0x00000800 */
+#define GINTSTS_USBSUSP                  GINTSTS_USBSUSP_Msk                      // USB suspend                                    */
 #define GINTSTS_USBRST_Pos               (12U)
-#define GINTSTS_USBRST_Msk               (0x1UL << GINTSTS_USBRST_Pos)            /*!< 0x00001000 */
-#define GINTSTS_USBRST                   GINTSTS_USBRST_Msk                       /*!< USB reset                                      */
+#define GINTSTS_USBRST_Msk               (0x1UL << GINTSTS_USBRST_Pos)            // 0x00001000 */
+#define GINTSTS_USBRST                   GINTSTS_USBRST_Msk                       // USB reset                                      */
 #define GINTSTS_ENUMDNE_Pos              (13U)
-#define GINTSTS_ENUMDNE_Msk              (0x1UL << GINTSTS_ENUMDNE_Pos)           /*!< 0x00002000 */
-#define GINTSTS_ENUMDNE                  GINTSTS_ENUMDNE_Msk                      /*!< Enumeration done                               */
+#define GINTSTS_ENUMDNE_Msk              (0x1UL << GINTSTS_ENUMDNE_Pos)           // 0x00002000 */
+#define GINTSTS_ENUMDNE                  GINTSTS_ENUMDNE_Msk                      // Enumeration done                               */
 #define GINTSTS_ISOODRP_Pos              (14U)
-#define GINTSTS_ISOODRP_Msk              (0x1UL << GINTSTS_ISOODRP_Pos)           /*!< 0x00004000 */
-#define GINTSTS_ISOODRP                  GINTSTS_ISOODRP_Msk                      /*!< Isochronous OUT packet dropped interrupt       */
+#define GINTSTS_ISOODRP_Msk              (0x1UL << GINTSTS_ISOODRP_Pos)           // 0x00004000 */
+#define GINTSTS_ISOODRP                  GINTSTS_ISOODRP_Msk                      // Isochronous OUT packet dropped interrupt       */
 #define GINTSTS_EOPF_Pos                 (15U)
-#define GINTSTS_EOPF_Msk                 (0x1UL << GINTSTS_EOPF_Pos)              /*!< 0x00008000 */
-#define GINTSTS_EOPF                     GINTSTS_EOPF_Msk                         /*!< End of periodic frame interrupt                */
+#define GINTSTS_EOPF_Msk                 (0x1UL << GINTSTS_EOPF_Pos)              // 0x00008000 */
+#define GINTSTS_EOPF                     GINTSTS_EOPF_Msk                         // End of periodic frame interrupt                */
 #define GINTSTS_IEPINT_Pos               (18U)
-#define GINTSTS_IEPINT_Msk               (0x1UL << GINTSTS_IEPINT_Pos)            /*!< 0x00040000 */
-#define GINTSTS_IEPINT                   GINTSTS_IEPINT_Msk                       /*!< IN endpoint interrupt                          */
+#define GINTSTS_IEPINT_Msk               (0x1UL << GINTSTS_IEPINT_Pos)            // 0x00040000 */
+#define GINTSTS_IEPINT                   GINTSTS_IEPINT_Msk                       // IN endpoint interrupt                          */
 #define GINTSTS_OEPINT_Pos               (19U)
-#define GINTSTS_OEPINT_Msk               (0x1UL << GINTSTS_OEPINT_Pos)            /*!< 0x00080000 */
-#define GINTSTS_OEPINT                   GINTSTS_OEPINT_Msk                       /*!< OUT endpoint interrupt                         */
+#define GINTSTS_OEPINT_Msk               (0x1UL << GINTSTS_OEPINT_Pos)            // 0x00080000 */
+#define GINTSTS_OEPINT                   GINTSTS_OEPINT_Msk                       // OUT endpoint interrupt                         */
 #define GINTSTS_IISOIXFR_Pos             (20U)
-#define GINTSTS_IISOIXFR_Msk             (0x1UL << GINTSTS_IISOIXFR_Pos)          /*!< 0x00100000 */
-#define GINTSTS_IISOIXFR                 GINTSTS_IISOIXFR_Msk                     /*!< Incomplete isochronous IN transfer             */
+#define GINTSTS_IISOIXFR_Msk             (0x1UL << GINTSTS_IISOIXFR_Pos)          // 0x00100000 */
+#define GINTSTS_IISOIXFR                 GINTSTS_IISOIXFR_Msk                     // Incomplete isochronous IN transfer             */
 #define GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
-#define GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
-#define GINTSTS_PXFR_INCOMPISOOUT        GINTSTS_PXFR_INCOMPISOOUT_Msk            /*!< Incomplete periodic transfer                   */
+#define GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << GINTSTS_PXFR_INCOMPISOOUT_Pos) // 0x00200000 */
+#define GINTSTS_PXFR_INCOMPISOOUT        GINTSTS_PXFR_INCOMPISOOUT_Msk            // Incomplete periodic transfer                   */
 #define GINTSTS_DATAFSUSP_Pos            (22U)
-#define GINTSTS_DATAFSUSP_Msk            (0x1UL << GINTSTS_DATAFSUSP_Pos)         /*!< 0x00400000 */
-#define GINTSTS_DATAFSUSP                GINTSTS_DATAFSUSP_Msk                    /*!< Data fetch suspended                           */
+#define GINTSTS_DATAFSUSP_Msk            (0x1UL << GINTSTS_DATAFSUSP_Pos)         // 0x00400000 */
+#define GINTSTS_DATAFSUSP                GINTSTS_DATAFSUSP_Msk                    // Data fetch suspended                           */
 #define GINTSTS_RSTDET_Pos               (23U)
-#define GINTSTS_RSTDET_Msk               (0x1UL << GINTSTS_RSTDET_Pos)            /*!< 0x00800000 */
-#define GINTSTS_RSTDET                   GINTSTS_RSTDET_Msk                       /*!< Reset detected interrupt                       */
+#define GINTSTS_RSTDET_Msk               (0x1UL << GINTSTS_RSTDET_Pos)            // 0x00800000 */
+#define GINTSTS_RSTDET                   GINTSTS_RSTDET_Msk                       // Reset detected interrupt                       */
 #define GINTSTS_HPRTINT_Pos              (24U)
-#define GINTSTS_HPRTINT_Msk              (0x1UL << GINTSTS_HPRTINT_Pos)           /*!< 0x01000000 */
-#define GINTSTS_HPRTINT                  GINTSTS_HPRTINT_Msk                      /*!< Host port interrupt                            */
+#define GINTSTS_HPRTINT_Msk              (0x1UL << GINTSTS_HPRTINT_Pos)           // 0x01000000 */
+#define GINTSTS_HPRTINT                  GINTSTS_HPRTINT_Msk                      // Host port interrupt                            */
 #define GINTSTS_HCINT_Pos                (25U)
-#define GINTSTS_HCINT_Msk                (0x1UL << GINTSTS_HCINT_Pos)             /*!< 0x02000000 */
-#define GINTSTS_HCINT                    GINTSTS_HCINT_Msk                        /*!< Host channels interrupt                        */
+#define GINTSTS_HCINT_Msk                (0x1UL << GINTSTS_HCINT_Pos)             // 0x02000000 */
+#define GINTSTS_HCINT                    GINTSTS_HCINT_Msk                        // Host channels interrupt                        */
 #define GINTSTS_PTXFE_Pos                (26U)
-#define GINTSTS_PTXFE_Msk                (0x1UL << GINTSTS_PTXFE_Pos)             /*!< 0x04000000 */
-#define GINTSTS_PTXFE                    GINTSTS_PTXFE_Msk                        /*!< Periodic TxFIFO empty                          */
+#define GINTSTS_PTXFE_Msk                (0x1UL << GINTSTS_PTXFE_Pos)             // 0x04000000 */
+#define GINTSTS_PTXFE                    GINTSTS_PTXFE_Msk                        // Periodic TxFIFO empty                          */
 #define GINTSTS_LPMINT_Pos               (27U)
-#define GINTSTS_LPMINT_Msk               (0x1UL << GINTSTS_LPMINT_Pos)            /*!< 0x08000000 */
-#define GINTSTS_LPMINT                   GINTSTS_LPMINT_Msk                       /*!< LPM interrupt                                  */
+#define GINTSTS_LPMINT_Msk               (0x1UL << GINTSTS_LPMINT_Pos)            // 0x08000000 */
+#define GINTSTS_LPMINT                   GINTSTS_LPMINT_Msk                       // LPM interrupt                                  */
 #define GINTSTS_CIDSCHG_Pos              (28U)
-#define GINTSTS_CIDSCHG_Msk              (0x1UL << GINTSTS_CIDSCHG_Pos)           /*!< 0x10000000 */
-#define GINTSTS_CIDSCHG                  GINTSTS_CIDSCHG_Msk                      /*!< Connector ID status change                     */
+#define GINTSTS_CIDSCHG_Msk              (0x1UL << GINTSTS_CIDSCHG_Pos)           // 0x10000000 */
+#define GINTSTS_CIDSCHG                  GINTSTS_CIDSCHG_Msk                      // Connector ID status change                     */
 #define GINTSTS_DISCINT_Pos              (29U)
-#define GINTSTS_DISCINT_Msk              (0x1UL << GINTSTS_DISCINT_Pos)           /*!< 0x20000000 */
-#define GINTSTS_DISCINT                  GINTSTS_DISCINT_Msk                      /*!< Disconnect detected interrupt                  */
+#define GINTSTS_DISCINT_Msk              (0x1UL << GINTSTS_DISCINT_Pos)           // 0x20000000 */
+#define GINTSTS_DISCINT                  GINTSTS_DISCINT_Msk                      // Disconnect detected interrupt                  */
 #define GINTSTS_SRQINT_Pos               (30U)
-#define GINTSTS_SRQINT_Msk               (0x1UL << GINTSTS_SRQINT_Pos)            /*!< 0x40000000 */
-#define GINTSTS_SRQINT                   GINTSTS_SRQINT_Msk                       /*!< Session request/new session detected interrupt */
+#define GINTSTS_SRQINT_Msk               (0x1UL << GINTSTS_SRQINT_Pos)            // 0x40000000 */
+#define GINTSTS_SRQINT                   GINTSTS_SRQINT_Msk                       // Session request/new session detected interrupt */
 #define GINTSTS_WKUINT_Pos               (31U)
-#define GINTSTS_WKUINT_Msk               (0x1UL << GINTSTS_WKUINT_Pos)            /*!< 0x80000000 */
-#define GINTSTS_WKUINT                   GINTSTS_WKUINT_Msk                       /*!< Resume/remote wakeup detected interrupt        */
+#define GINTSTS_WKUINT_Msk               (0x1UL << GINTSTS_WKUINT_Pos)            // 0x80000000 */
+#define GINTSTS_WKUINT                   GINTSTS_WKUINT_Msk                       // Resume/remote wakeup detected interrupt        */
 
 /********************  Bit definition for GINTMSK register  ********************/
 #define GINTMSK_MMISM_Pos                (1U)
-#define GINTMSK_MMISM_Msk                (0x1UL << GINTMSK_MMISM_Pos)             /*!< 0x00000002 */
-#define GINTMSK_MMISM                    GINTMSK_MMISM_Msk                        /*!< Mode mismatch interrupt mask                        */
+#define GINTMSK_MMISM_Msk                (0x1UL << GINTMSK_MMISM_Pos)             // 0x00000002 */
+#define GINTMSK_MMISM                    GINTMSK_MMISM_Msk                        // Mode mismatch interrupt mask                        */
 #define GINTMSK_OTGINT_Pos               (2U)
-#define GINTMSK_OTGINT_Msk               (0x1UL << GINTMSK_OTGINT_Pos)            /*!< 0x00000004 */
-#define GINTMSK_OTGINT                   GINTMSK_OTGINT_Msk                       /*!< OTG interrupt mask                                  */
+#define GINTMSK_OTGINT_Msk               (0x1UL << GINTMSK_OTGINT_Pos)            // 0x00000004 */
+#define GINTMSK_OTGINT                   GINTMSK_OTGINT_Msk                       // OTG interrupt mask                                  */
 #define GINTMSK_SOFM_Pos                 (3U)
-#define GINTMSK_SOFM_Msk                 (0x1UL << GINTMSK_SOFM_Pos)              /*!< 0x00000008 */
-#define GINTMSK_SOFM                     GINTMSK_SOFM_Msk                         /*!< Start of frame mask                                 */
+#define GINTMSK_SOFM_Msk                 (0x1UL << GINTMSK_SOFM_Pos)              // 0x00000008 */
+#define GINTMSK_SOFM                     GINTMSK_SOFM_Msk                         // Start of frame mask                                 */
 #define GINTMSK_RXFLVLM_Pos              (4U)
-#define GINTMSK_RXFLVLM_Msk              (0x1UL << GINTMSK_RXFLVLM_Pos)           /*!< 0x00000010 */
-#define GINTMSK_RXFLVLM                  GINTMSK_RXFLVLM_Msk                      /*!< Receive FIFO nonempty mask                          */
+#define GINTMSK_RXFLVLM_Msk              (0x1UL << GINTMSK_RXFLVLM_Pos)           // 0x00000010 */
+#define GINTMSK_RXFLVLM                  GINTMSK_RXFLVLM_Msk                      // Receive FIFO nonempty mask                          */
 #define GINTMSK_NPTXFEM_Pos              (5U)
-#define GINTMSK_NPTXFEM_Msk              (0x1UL << GINTMSK_NPTXFEM_Pos)           /*!< 0x00000020 */
-#define GINTMSK_NPTXFEM                  GINTMSK_NPTXFEM_Msk                      /*!< Nonperiodic TxFIFO empty mask                       */
+#define GINTMSK_NPTXFEM_Msk              (0x1UL << GINTMSK_NPTXFEM_Pos)           // 0x00000020 */
+#define GINTMSK_NPTXFEM                  GINTMSK_NPTXFEM_Msk                      // Nonperiodic TxFIFO empty mask                       */
 #define GINTMSK_GINAKEFFM_Pos            (6U)
-#define GINTMSK_GINAKEFFM_Msk            (0x1UL << GINTMSK_GINAKEFFM_Pos)         /*!< 0x00000040 */
-#define GINTMSK_GINAKEFFM                GINTMSK_GINAKEFFM_Msk                    /*!< Global nonperiodic IN NAK effective mask            */
+#define GINTMSK_GINAKEFFM_Msk            (0x1UL << GINTMSK_GINAKEFFM_Pos)         // 0x00000040 */
+#define GINTMSK_GINAKEFFM                GINTMSK_GINAKEFFM_Msk                    // Global nonperiodic IN NAK effective mask            */
 #define GINTMSK_GONAKEFFM_Pos            (7U)
-#define GINTMSK_GONAKEFFM_Msk            (0x1UL << GINTMSK_GONAKEFFM_Pos)         /*!< 0x00000080 */
-#define GINTMSK_GONAKEFFM                GINTMSK_GONAKEFFM_Msk                    /*!< Global OUT NAK effective mask                       */
+#define GINTMSK_GONAKEFFM_Msk            (0x1UL << GINTMSK_GONAKEFFM_Pos)         // 0x00000080 */
+#define GINTMSK_GONAKEFFM                GINTMSK_GONAKEFFM_Msk                    // Global OUT NAK effective mask                       */
 #define GINTMSK_ESUSPM_Pos               (10U)
-#define GINTMSK_ESUSPM_Msk               (0x1UL << GINTMSK_ESUSPM_Pos)            /*!< 0x00000400 */
-#define GINTMSK_ESUSPM                   GINTMSK_ESUSPM_Msk                       /*!< Early suspend mask                                  */
+#define GINTMSK_ESUSPM_Msk               (0x1UL << GINTMSK_ESUSPM_Pos)            // 0x00000400 */
+#define GINTMSK_ESUSPM                   GINTMSK_ESUSPM_Msk                       // Early suspend mask                                  */
 #define GINTMSK_USBSUSPM_Pos             (11U)
-#define GINTMSK_USBSUSPM_Msk             (0x1UL << GINTMSK_USBSUSPM_Pos)          /*!< 0x00000800 */
-#define GINTMSK_USBSUSPM                 GINTMSK_USBSUSPM_Msk                     /*!< USB suspend mask                                    */
+#define GINTMSK_USBSUSPM_Msk             (0x1UL << GINTMSK_USBSUSPM_Pos)          // 0x00000800 */
+#define GINTMSK_USBSUSPM                 GINTMSK_USBSUSPM_Msk                     // USB suspend mask                                    */
 #define GINTMSK_USBRST_Pos               (12U)
-#define GINTMSK_USBRST_Msk               (0x1UL << GINTMSK_USBRST_Pos)            /*!< 0x00001000 */
-#define GINTMSK_USBRST                   GINTMSK_USBRST_Msk                       /*!< USB reset mask                                      */
+#define GINTMSK_USBRST_Msk               (0x1UL << GINTMSK_USBRST_Pos)            // 0x00001000 */
+#define GINTMSK_USBRST                   GINTMSK_USBRST_Msk                       // USB reset mask                                      */
 #define GINTMSK_ENUMDNEM_Pos             (13U)
-#define GINTMSK_ENUMDNEM_Msk             (0x1UL << GINTMSK_ENUMDNEM_Pos)          /*!< 0x00002000 */
-#define GINTMSK_ENUMDNEM                 GINTMSK_ENUMDNEM_Msk                     /*!< Enumeration done mask                               */
+#define GINTMSK_ENUMDNEM_Msk             (0x1UL << GINTMSK_ENUMDNEM_Pos)          // 0x00002000 */
+#define GINTMSK_ENUMDNEM                 GINTMSK_ENUMDNEM_Msk                     // Enumeration done mask                               */
 #define GINTMSK_ISOODRPM_Pos             (14U)
-#define GINTMSK_ISOODRPM_Msk             (0x1UL << GINTMSK_ISOODRPM_Pos)          /*!< 0x00004000 */
-#define GINTMSK_ISOODRPM                 GINTMSK_ISOODRPM_Msk                     /*!< Isochronous OUT packet dropped interrupt mask       */
+#define GINTMSK_ISOODRPM_Msk             (0x1UL << GINTMSK_ISOODRPM_Pos)          // 0x00004000 */
+#define GINTMSK_ISOODRPM                 GINTMSK_ISOODRPM_Msk                     // Isochronous OUT packet dropped interrupt mask       */
 #define GINTMSK_EOPFM_Pos                (15U)
-#define GINTMSK_EOPFM_Msk                (0x1UL << GINTMSK_EOPFM_Pos)             /*!< 0x00008000 */
-#define GINTMSK_EOPFM                    GINTMSK_EOPFM_Msk                        /*!< End of periodic frame interrupt mask                */
+#define GINTMSK_EOPFM_Msk                (0x1UL << GINTMSK_EOPFM_Pos)             // 0x00008000 */
+#define GINTMSK_EOPFM                    GINTMSK_EOPFM_Msk                        // End of periodic frame interrupt mask                */
 #define GINTMSK_EPMISM_Pos               (17U)
-#define GINTMSK_EPMISM_Msk               (0x1UL << GINTMSK_EPMISM_Pos)            /*!< 0x00020000 */
-#define GINTMSK_EPMISM                   GINTMSK_EPMISM_Msk                       /*!< Endpoint mismatch interrupt mask                    */
+#define GINTMSK_EPMISM_Msk               (0x1UL << GINTMSK_EPMISM_Pos)            // 0x00020000 */
+#define GINTMSK_EPMISM                   GINTMSK_EPMISM_Msk                       // Endpoint mismatch interrupt mask                    */
 #define GINTMSK_IEPINT_Pos               (18U)
-#define GINTMSK_IEPINT_Msk               (0x1UL << GINTMSK_IEPINT_Pos)            /*!< 0x00040000 */
-#define GINTMSK_IEPINT                   GINTMSK_IEPINT_Msk                       /*!< IN endpoints interrupt mask                         */
+#define GINTMSK_IEPINT_Msk               (0x1UL << GINTMSK_IEPINT_Pos)            // 0x00040000 */
+#define GINTMSK_IEPINT                   GINTMSK_IEPINT_Msk                       // IN endpoints interrupt mask                         */
 #define GINTMSK_OEPINT_Pos               (19U)
-#define GINTMSK_OEPINT_Msk               (0x1UL << GINTMSK_OEPINT_Pos)            /*!< 0x00080000 */
-#define GINTMSK_OEPINT                   GINTMSK_OEPINT_Msk                       /*!< OUT endpoints interrupt mask                        */
+#define GINTMSK_OEPINT_Msk               (0x1UL << GINTMSK_OEPINT_Pos)            // 0x00080000 */
+#define GINTMSK_OEPINT                   GINTMSK_OEPINT_Msk                       // OUT endpoints interrupt mask                        */
 #define GINTMSK_IISOIXFRM_Pos            (20U)
-#define GINTMSK_IISOIXFRM_Msk            (0x1UL << GINTMSK_IISOIXFRM_Pos)         /*!< 0x00100000 */
-#define GINTMSK_IISOIXFRM                GINTMSK_IISOIXFRM_Msk                    /*!< Incomplete isochronous IN transfer mask             */
+#define GINTMSK_IISOIXFRM_Msk            (0x1UL << GINTMSK_IISOIXFRM_Pos)         // 0x00100000 */
+#define GINTMSK_IISOIXFRM                GINTMSK_IISOIXFRM_Msk                    // Incomplete isochronous IN transfer mask             */
 #define GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
-#define GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos)   /*!< 0x00200000 */
-#define GINTMSK_PXFRM_IISOOXFRM          GINTMSK_PXFRM_IISOOXFRM_Msk              /*!< Incomplete periodic transfer mask                   */
+#define GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << GINTMSK_PXFRM_IISOOXFRM_Pos)   // 0x00200000 */
+#define GINTMSK_PXFRM_IISOOXFRM          GINTMSK_PXFRM_IISOOXFRM_Msk              // Incomplete periodic transfer mask                   */
 #define GINTMSK_FSUSPM_Pos               (22U)
-#define GINTMSK_FSUSPM_Msk               (0x1UL << GINTMSK_FSUSPM_Pos)            /*!< 0x00400000 */
-#define GINTMSK_FSUSPM                   GINTMSK_FSUSPM_Msk                       /*!< Data fetch suspended mask                           */
+#define GINTMSK_FSUSPM_Msk               (0x1UL << GINTMSK_FSUSPM_Pos)            // 0x00400000 */
+#define GINTMSK_FSUSPM                   GINTMSK_FSUSPM_Msk                       // Data fetch suspended mask                           */
 #define GINTMSK_RSTDEM_Pos               (23U)
-#define GINTMSK_RSTDEM_Msk               (0x1UL << GINTMSK_RSTDEM_Pos)            /*!< 0x00800000 */
-#define GINTMSK_RSTDEM                   GINTMSK_RSTDEM_Msk                       /*!< Reset detected interrupt mask                       */
+#define GINTMSK_RSTDEM_Msk               (0x1UL << GINTMSK_RSTDEM_Pos)            // 0x00800000 */
+#define GINTMSK_RSTDEM                   GINTMSK_RSTDEM_Msk                       // Reset detected interrupt mask                       */
 #define GINTMSK_PRTIM_Pos                (24U)
-#define GINTMSK_PRTIM_Msk                (0x1UL << GINTMSK_PRTIM_Pos)             /*!< 0x01000000 */
-#define GINTMSK_PRTIM                    GINTMSK_PRTIM_Msk                        /*!< Host port interrupt mask                            */
+#define GINTMSK_PRTIM_Msk                (0x1UL << GINTMSK_PRTIM_Pos)             // 0x01000000 */
+#define GINTMSK_PRTIM                    GINTMSK_PRTIM_Msk                        // Host port interrupt mask                            */
 #define GINTMSK_HCIM_Pos                 (25U)
-#define GINTMSK_HCIM_Msk                 (0x1UL << GINTMSK_HCIM_Pos)              /*!< 0x02000000 */
-#define GINTMSK_HCIM                     GINTMSK_HCIM_Msk                         /*!< Host channels interrupt mask                        */
+#define GINTMSK_HCIM_Msk                 (0x1UL << GINTMSK_HCIM_Pos)              // 0x02000000 */
+#define GINTMSK_HCIM                     GINTMSK_HCIM_Msk                         // Host channels interrupt mask                        */
 #define GINTMSK_PTXFEM_Pos               (26U)
-#define GINTMSK_PTXFEM_Msk               (0x1UL << GINTMSK_PTXFEM_Pos)            /*!< 0x04000000 */
-#define GINTMSK_PTXFEM                   GINTMSK_PTXFEM_Msk                       /*!< Periodic TxFIFO empty mask                          */
+#define GINTMSK_PTXFEM_Msk               (0x1UL << GINTMSK_PTXFEM_Pos)            // 0x04000000 */
+#define GINTMSK_PTXFEM                   GINTMSK_PTXFEM_Msk                       // Periodic TxFIFO empty mask                          */
 #define GINTMSK_LPMINTM_Pos              (27U)
-#define GINTMSK_LPMINTM_Msk              (0x1UL << GINTMSK_LPMINTM_Pos)           /*!< 0x08000000 */
-#define GINTMSK_LPMINTM                  GINTMSK_LPMINTM_Msk                      /*!< LPM interrupt Mask                                  */
+#define GINTMSK_LPMINTM_Msk              (0x1UL << GINTMSK_LPMINTM_Pos)           // 0x08000000 */
+#define GINTMSK_LPMINTM                  GINTMSK_LPMINTM_Msk                      // LPM interrupt Mask                                  */
 #define GINTMSK_CIDSCHGM_Pos             (28U)
-#define GINTMSK_CIDSCHGM_Msk             (0x1UL << GINTMSK_CIDSCHGM_Pos)          /*!< 0x10000000 */
-#define GINTMSK_CIDSCHGM                 GINTMSK_CIDSCHGM_Msk                     /*!< Connector ID status change mask                     */
+#define GINTMSK_CIDSCHGM_Msk             (0x1UL << GINTMSK_CIDSCHGM_Pos)          // 0x10000000 */
+#define GINTMSK_CIDSCHGM                 GINTMSK_CIDSCHGM_Msk                     // Connector ID status change mask                     */
 #define GINTMSK_DISCINT_Pos              (29U)
-#define GINTMSK_DISCINT_Msk              (0x1UL << GINTMSK_DISCINT_Pos)           /*!< 0x20000000 */
-#define GINTMSK_DISCINT                  GINTMSK_DISCINT_Msk                      /*!< Disconnect detected interrupt mask                  */
+#define GINTMSK_DISCINT_Msk              (0x1UL << GINTMSK_DISCINT_Pos)           // 0x20000000 */
+#define GINTMSK_DISCINT                  GINTMSK_DISCINT_Msk                      // Disconnect detected interrupt mask                  */
 #define GINTMSK_SRQIM_Pos                (30U)
-#define GINTMSK_SRQIM_Msk                (0x1UL << GINTMSK_SRQIM_Pos)             /*!< 0x40000000 */
-#define GINTMSK_SRQIM                    GINTMSK_SRQIM_Msk                        /*!< Session request/new session detected interrupt mask */
+#define GINTMSK_SRQIM_Msk                (0x1UL << GINTMSK_SRQIM_Pos)             // 0x40000000 */
+#define GINTMSK_SRQIM                    GINTMSK_SRQIM_Msk                        // Session request/new session detected interrupt mask */
 #define GINTMSK_WUIM_Pos                 (31U)
-#define GINTMSK_WUIM_Msk                 (0x1UL << GINTMSK_WUIM_Pos)              /*!< 0x80000000 */
-#define GINTMSK_WUIM                     GINTMSK_WUIM_Msk                         /*!< Resume/remote wakeup detected interrupt mask        */
+#define GINTMSK_WUIM_Msk                 (0x1UL << GINTMSK_WUIM_Pos)              // 0x80000000 */
+#define GINTMSK_WUIM                     GINTMSK_WUIM_Msk                         // Resume/remote wakeup detected interrupt mask        */
 
 /********************  Bit definition for DAINT register  ********************/
 #define DAINT_IEPINT_Pos                 (0U)
-#define DAINT_IEPINT_Msk                 (0xFFFFUL << DAINT_IEPINT_Pos)           /*!< 0x0000FFFF */
-#define DAINT_IEPINT                     DAINT_IEPINT_Msk                         /*!< IN endpoint interrupt bits  */
+#define DAINT_IEPINT_Msk                 (0xFFFFUL << DAINT_IEPINT_Pos)           // 0x0000FFFF */
+#define DAINT_IEPINT                     DAINT_IEPINT_Msk                         // IN endpoint interrupt bits  */
 #define DAINT_OEPINT_Pos                 (16U)
-#define DAINT_OEPINT_Msk                 (0xFFFFUL << DAINT_OEPINT_Pos)           /*!< 0xFFFF0000 */
-#define DAINT_OEPINT                     DAINT_OEPINT_Msk                         /*!< OUT endpoint interrupt bits */
+#define DAINT_OEPINT_Msk                 (0xFFFFUL << DAINT_OEPINT_Pos)           // 0xFFFF0000 */
+#define DAINT_OEPINT                     DAINT_OEPINT_Msk                         // OUT endpoint interrupt bits */
 
 /********************  Bit definition for HAINTMSK register  ********************/
 #define HAINTMSK_HAINTM_Pos              (0U)
-#define HAINTMSK_HAINTM_Msk              (0xFFFFUL << HAINTMSK_HAINTM_Pos)        /*!< 0x0000FFFF */
-#define HAINTMSK_HAINTM                  HAINTMSK_HAINTM_Msk                      /*!< Channel interrupt mask */
+#define HAINTMSK_HAINTM_Msk              (0xFFFFUL << HAINTMSK_HAINTM_Pos)        // 0x0000FFFF */
+#define HAINTMSK_HAINTM                  HAINTMSK_HAINTM_Msk                      // Channel interrupt mask */
 
 /********************  Bit definition for GRXSTSP register  ********************/
 #define GRXSTSP_EPNUM_Pos                (0U)
-#define GRXSTSP_EPNUM_Msk                (0xFUL << GRXSTSP_EPNUM_Pos)             /*!< 0x0000000F */
-#define GRXSTSP_EPNUM                    GRXSTSP_EPNUM_Msk                        /*!< IN EP interrupt mask bits  */
+#define GRXSTSP_EPNUM_Msk                (0xFUL << GRXSTSP_EPNUM_Pos)             // 0x0000000F */
+#define GRXSTSP_EPNUM                    GRXSTSP_EPNUM_Msk                        // IN EP interrupt mask bits  */
 #define GRXSTSP_BCNT_Pos                 (4U)
-#define GRXSTSP_BCNT_Msk                 (0x7FFUL << GRXSTSP_BCNT_Pos)            /*!< 0x00007FF0 */
-#define GRXSTSP_BCNT                     GRXSTSP_BCNT_Msk                         /*!< OUT EP interrupt mask bits */
+#define GRXSTSP_BCNT_Msk                 (0x7FFUL << GRXSTSP_BCNT_Pos)            // 0x00007FF0 */
+#define GRXSTSP_BCNT                     GRXSTSP_BCNT_Msk                         // OUT EP interrupt mask bits */
 #define GRXSTSP_DPID_Pos                 (15U)
-#define GRXSTSP_DPID_Msk                 (0x3UL << GRXSTSP_DPID_Pos)              /*!< 0x00018000 */
-#define GRXSTSP_DPID                     GRXSTSP_DPID_Msk                         /*!< OUT EP interrupt mask bits */
+#define GRXSTSP_DPID_Msk                 (0x3UL << GRXSTSP_DPID_Pos)              // 0x00018000 */
+#define GRXSTSP_DPID                     GRXSTSP_DPID_Msk                         // OUT EP interrupt mask bits */
 #define GRXSTSP_PKTSTS_Pos               (17U)
-#define GRXSTSP_PKTSTS_Msk               (0xFUL << GRXSTSP_PKTSTS_Pos)            /*!< 0x001E0000 */
-#define GRXSTSP_PKTSTS                   GRXSTSP_PKTSTS_Msk                       /*!< OUT EP interrupt mask bits */
+#define GRXSTSP_PKTSTS_Msk               (0xFUL << GRXSTSP_PKTSTS_Pos)            // 0x001E0000 */
+#define GRXSTSP_PKTSTS                   GRXSTSP_PKTSTS_Msk                       // OUT EP interrupt mask bits */
 
 /********************  Bit definition for DAINTMSK register  ********************/
 #define DAINTMSK_IEPM_Pos                (0U)
-#define DAINTMSK_IEPM_Msk                (0xFFFFUL << DAINTMSK_IEPM_Pos)          /*!< 0x0000FFFF */
-#define DAINTMSK_IEPM                    DAINTMSK_IEPM_Msk                        /*!< IN EP interrupt mask bits */
+#define DAINTMSK_IEPM_Msk                (0xFFFFUL << DAINTMSK_IEPM_Pos)          // 0x0000FFFF */
+#define DAINTMSK_IEPM                    DAINTMSK_IEPM_Msk                        // IN EP interrupt mask bits */
 #define DAINTMSK_OEPM_Pos                (16U)
-#define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          /*!< 0xFFFF0000 */
-#define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        /*!< OUT EP interrupt mask bits */
+#define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          // 0xFFFF0000 */
+#define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        // OUT EP interrupt mask bits */
 
 /********************  Bit definition for OTG register  ********************/
 #define CHNUM_Pos                        (0U)
-#define CHNUM_Msk                        (0xFUL << CHNUM_Pos)                     /*!< 0x0000000F */
-#define CHNUM                            CHNUM_Msk                                /*!< Channel number */
-#define CHNUM_0                          (0x1UL << CHNUM_Pos)                     /*!< 0x00000001 */
-#define CHNUM_1                          (0x2UL << CHNUM_Pos)                     /*!< 0x00000002 */
-#define CHNUM_2                          (0x4UL << CHNUM_Pos)                     /*!< 0x00000004 */
-#define CHNUM_3                          (0x8UL << CHNUM_Pos)                     /*!< 0x00000008 */
+#define CHNUM_Msk                        (0xFUL << CHNUM_Pos)                     // 0x0000000F */
+#define CHNUM                            CHNUM_Msk                                // Channel number */
+#define CHNUM_0                          (0x1UL << CHNUM_Pos)                     // 0x00000001 */
+#define CHNUM_1                          (0x2UL << CHNUM_Pos)                     // 0x00000002 */
+#define CHNUM_2                          (0x4UL << CHNUM_Pos)                     // 0x00000004 */
+#define CHNUM_3                          (0x8UL << CHNUM_Pos)                     // 0x00000008 */
 #define BCNT_Pos                         (4U)
-#define BCNT_Msk                         (0x7FFUL << BCNT_Pos)                    /*!< 0x00007FF0 */
-#define BCNT                             BCNT_Msk                                 /*!< Byte count */
+#define BCNT_Msk                         (0x7FFUL << BCNT_Pos)                    // 0x00007FF0 */
+#define BCNT                             BCNT_Msk                                 // Byte count */
 
 #define DPID_Pos                         (15U)
-#define DPID_Msk                         (0x3UL << DPID_Pos)                      /*!< 0x00018000 */
-#define DPID                             DPID_Msk                                 /*!< Data PID */
-#define DPID_0                           (0x1UL << DPID_Pos)                      /*!< 0x00008000 */
-#define DPID_1                           (0x2UL << DPID_Pos)                      /*!< 0x00010000 */
+#define DPID_Msk                         (0x3UL << DPID_Pos)                      // 0x00018000 */
+#define DPID                             DPID_Msk                                 // Data PID */
+#define DPID_0                           (0x1UL << DPID_Pos)                      // 0x00008000 */
+#define DPID_1                           (0x2UL << DPID_Pos)                      // 0x00010000 */
 
 #define PKTSTS_Pos                       (17U)
-#define PKTSTS_Msk                       (0xFUL << PKTSTS_Pos)                    /*!< 0x001E0000 */
-#define PKTSTS                           PKTSTS_Msk                               /*!< Packet status */
-#define PKTSTS_0                         (0x1UL << PKTSTS_Pos)                    /*!< 0x00020000 */
-#define PKTSTS_1                         (0x2UL << PKTSTS_Pos)                    /*!< 0x00040000 */
-#define PKTSTS_2                         (0x4UL << PKTSTS_Pos)                    /*!< 0x00080000 */
-#define PKTSTS_3                         (0x8UL << PKTSTS_Pos)                    /*!< 0x00100000 */
+#define PKTSTS_Msk                       (0xFUL << PKTSTS_Pos)                    // 0x001E0000 */
+#define PKTSTS                           PKTSTS_Msk                               // Packet status */
+#define PKTSTS_0                         (0x1UL << PKTSTS_Pos)                    // 0x00020000 */
+#define PKTSTS_1                         (0x2UL << PKTSTS_Pos)                    // 0x00040000 */
+#define PKTSTS_2                         (0x4UL << PKTSTS_Pos)                    // 0x00080000 */
+#define PKTSTS_3                         (0x8UL << PKTSTS_Pos)                    // 0x00100000 */
 
 #define EPNUM_Pos                        (0U)
-#define EPNUM_Msk                        (0xFUL << EPNUM_Pos)                     /*!< 0x0000000F */
-#define EPNUM                            EPNUM_Msk                                /*!< Endpoint number */
-#define EPNUM_0                          (0x1UL << EPNUM_Pos)                     /*!< 0x00000001 */
-#define EPNUM_1                          (0x2UL << EPNUM_Pos)                     /*!< 0x00000002 */
-#define EPNUM_2                          (0x4UL << EPNUM_Pos)                     /*!< 0x00000004 */
-#define EPNUM_3                          (0x8UL << EPNUM_Pos)                     /*!< 0x00000008 */
+#define EPNUM_Msk                        (0xFUL << EPNUM_Pos)                     // 0x0000000F */
+#define EPNUM                            EPNUM_Msk                                // Endpoint number */
+#define EPNUM_0                          (0x1UL << EPNUM_Pos)                     // 0x00000001 */
+#define EPNUM_1                          (0x2UL << EPNUM_Pos)                     // 0x00000002 */
+#define EPNUM_2                          (0x4UL << EPNUM_Pos)                     // 0x00000004 */
+#define EPNUM_3                          (0x8UL << EPNUM_Pos)                     // 0x00000008 */
 
 #define FRMNUM_Pos                       (21U)
-#define FRMNUM_Msk                       (0xFUL << FRMNUM_Pos)                    /*!< 0x01E00000 */
-#define FRMNUM                           FRMNUM_Msk                               /*!< Frame number */
-#define FRMNUM_0                         (0x1UL << FRMNUM_Pos)                    /*!< 0x00200000 */
-#define FRMNUM_1                         (0x2UL << FRMNUM_Pos)                    /*!< 0x00400000 */
-#define FRMNUM_2                         (0x4UL << FRMNUM_Pos)                    /*!< 0x00800000 */
-#define FRMNUM_3                         (0x8UL << FRMNUM_Pos)                    /*!< 0x01000000 */
+#define FRMNUM_Msk                       (0xFUL << FRMNUM_Pos)                    // 0x01E00000 */
+#define FRMNUM                           FRMNUM_Msk                               // Frame number */
+#define FRMNUM_0                         (0x1UL << FRMNUM_Pos)                    // 0x00200000 */
+#define FRMNUM_1                         (0x2UL << FRMNUM_Pos)                    // 0x00400000 */
+#define FRMNUM_2                         (0x4UL << FRMNUM_Pos)                    // 0x00800000 */
+#define FRMNUM_3                         (0x8UL << FRMNUM_Pos)                    // 0x01000000 */
 
 /********************  Bit definition for GRXFSIZ register  ********************/
 #define GRXFSIZ_RXFD_Pos                 (0U)
-#define GRXFSIZ_RXFD_Msk                 (0xFFFFUL << GRXFSIZ_RXFD_Pos)           /*!< 0x0000FFFF */
-#define GRXFSIZ_RXFD                     GRXFSIZ_RXFD_Msk                         /*!< RxFIFO depth */
+#define GRXFSIZ_RXFD_Msk                 (0xFFFFUL << GRXFSIZ_RXFD_Pos)           // 0x0000FFFF */
+#define GRXFSIZ_RXFD                     GRXFSIZ_RXFD_Msk                         // RxFIFO depth */
 
 /********************  Bit definition for DVBUSDIS register  ********************/
 #define DVBUSDIS_VBUSDT_Pos              (0U)
-#define DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << DVBUSDIS_VBUSDT_Pos)        /*!< 0x0000FFFF */
-#define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk                      /*!< Device VBUS discharge time */
+#define DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << DVBUSDIS_VBUSDT_Pos)        // 0x0000FFFF */
+#define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk                      // Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
 #define NPTXFSA_Pos                      (0U)
-#define NPTXFSA_Msk                      (0xFFFFUL << NPTXFSA_Pos)                /*!< 0x0000FFFF */
-#define NPTXFSA                          NPTXFSA_Msk                              /*!< Nonperiodic transmit RAM start address */
+#define NPTXFSA_Msk                      (0xFFFFUL << NPTXFSA_Pos)                // 0x0000FFFF */
+#define NPTXFSA                          NPTXFSA_Msk                              // Nonperiodic transmit RAM start address */
 #define NPTXFD_Pos                       (16U)
-#define NPTXFD_Msk                       (0xFFFFUL << NPTXFD_Pos)                 /*!< 0xFFFF0000 */
-#define NPTXFD                           NPTXFD_Msk                               /*!< Nonperiodic TxFIFO depth               */
+#define NPTXFD_Msk                       (0xFFFFUL << NPTXFD_Pos)                 // 0xFFFF0000 */
+#define NPTXFD                           NPTXFD_Msk                               // Nonperiodic TxFIFO depth               */
 #define TX0FSA_Pos                       (0U)
-#define TX0FSA_Msk                       (0xFFFFUL << TX0FSA_Pos)                 /*!< 0x0000FFFF */
-#define TX0FSA                           TX0FSA_Msk                               /*!< Endpoint 0 transmit RAM start address  */
+#define TX0FSA_Msk                       (0xFFFFUL << TX0FSA_Pos)                 // 0x0000FFFF */
+#define TX0FSA                           TX0FSA_Msk                               // Endpoint 0 transmit RAM start address  */
 #define TX0FD_Pos                        (16U)
-#define TX0FD_Msk                        (0xFFFFUL << TX0FD_Pos)                  /*!< 0xFFFF0000 */
-#define TX0FD                            TX0FD_Msk                                /*!< Endpoint 0 TxFIFO depth                */
+#define TX0FD_Msk                        (0xFFFFUL << TX0FD_Pos)                  // 0xFFFF0000 */
+#define TX0FD                            TX0FD_Msk                                // Endpoint 0 TxFIFO depth                */
 
 /********************  Bit definition for DVBUSPULSE register  ********************/
 #define DVBUSPULSE_DVBUSP_Pos            (0U)
-#define DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << DVBUSPULSE_DVBUSP_Pos)       /*!< 0x00000FFF */
-#define DVBUSPULSE_DVBUSP                DVBUSPULSE_DVBUSP_Msk                    /*!< Device VBUS pulsing time */
+#define DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << DVBUSPULSE_DVBUSP_Pos)       // 0x00000FFF */
+#define DVBUSPULSE_DVBUSP                DVBUSPULSE_DVBUSP_Msk                    // Device VBUS pulsing time */
 
 /********************  Bit definition for GNPTXSTS register  ********************/
 #define GNPTXSTS_NPTXFSAV_Pos            (0U)
-#define GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos)      /*!< 0x0000FFFF */
-#define GNPTXSTS_NPTXFSAV                GNPTXSTS_NPTXFSAV_Msk                    /*!< Nonperiodic TxFIFO space available */
+#define GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << GNPTXSTS_NPTXFSAV_Pos)      // 0x0000FFFF */
+#define GNPTXSTS_NPTXFSAV                GNPTXSTS_NPTXFSAV_Msk                    // Nonperiodic TxFIFO space available */
 
 #define GNPTXSTS_NPTQXSAV_Pos            (16U)
-#define GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00FF0000 */
-#define GNPTXSTS_NPTQXSAV                GNPTXSTS_NPTQXSAV_Msk                    /*!< Nonperiodic transmit request queue space available */
-#define GNPTXSTS_NPTQXSAV_0              (0x01UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00010000 */
-#define GNPTXSTS_NPTQXSAV_1              (0x02UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00020000 */
-#define GNPTXSTS_NPTQXSAV_2              (0x04UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00040000 */
-#define GNPTXSTS_NPTQXSAV_3              (0x08UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00080000 */
-#define GNPTXSTS_NPTQXSAV_4              (0x10UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00100000 */
-#define GNPTXSTS_NPTQXSAV_5              (0x20UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00200000 */
-#define GNPTXSTS_NPTQXSAV_6              (0x40UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00400000 */
-#define GNPTXSTS_NPTQXSAV_7              (0x80UL << GNPTXSTS_NPTQXSAV_Pos)        /*!< 0x00800000 */
+#define GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00FF0000 */
+#define GNPTXSTS_NPTQXSAV                GNPTXSTS_NPTQXSAV_Msk                    // Nonperiodic transmit request queue space available */
+#define GNPTXSTS_NPTQXSAV_0              (0x01UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00010000 */
+#define GNPTXSTS_NPTQXSAV_1              (0x02UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00020000 */
+#define GNPTXSTS_NPTQXSAV_2              (0x04UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00040000 */
+#define GNPTXSTS_NPTQXSAV_3              (0x08UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00080000 */
+#define GNPTXSTS_NPTQXSAV_4              (0x10UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00100000 */
+#define GNPTXSTS_NPTQXSAV_5              (0x20UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00200000 */
+#define GNPTXSTS_NPTQXSAV_6              (0x40UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00400000 */
+#define GNPTXSTS_NPTQXSAV_7              (0x80UL << GNPTXSTS_NPTQXSAV_Pos)        // 0x00800000 */
 
 #define GNPTXSTS_NPTXQTOP_Pos            (24U)
-#define GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x7F000000 */
-#define GNPTXSTS_NPTXQTOP                GNPTXSTS_NPTXQTOP_Msk                    /*!< Top of the nonperiodic transmit request queue */
-#define GNPTXSTS_NPTXQTOP_0              (0x01UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x01000000 */
-#define GNPTXSTS_NPTXQTOP_1              (0x02UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x02000000 */
-#define GNPTXSTS_NPTXQTOP_2              (0x04UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x04000000 */
-#define GNPTXSTS_NPTXQTOP_3              (0x08UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x08000000 */
-#define GNPTXSTS_NPTXQTOP_4              (0x10UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x10000000 */
-#define GNPTXSTS_NPTXQTOP_5              (0x20UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x20000000 */
-#define GNPTXSTS_NPTXQTOP_6              (0x40UL << GNPTXSTS_NPTXQTOP_Pos)        /*!< 0x40000000 */
+#define GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << GNPTXSTS_NPTXQTOP_Pos)        // 0x7F000000 */
+#define GNPTXSTS_NPTXQTOP                GNPTXSTS_NPTXQTOP_Msk                    // Top of the nonperiodic transmit request queue */
+#define GNPTXSTS_NPTXQTOP_0              (0x01UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x01000000 */
+#define GNPTXSTS_NPTXQTOP_1              (0x02UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x02000000 */
+#define GNPTXSTS_NPTXQTOP_2              (0x04UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x04000000 */
+#define GNPTXSTS_NPTXQTOP_3              (0x08UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x08000000 */
+#define GNPTXSTS_NPTXQTOP_4              (0x10UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x10000000 */
+#define GNPTXSTS_NPTXQTOP_5              (0x20UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x20000000 */
+#define GNPTXSTS_NPTXQTOP_6              (0x40UL << GNPTXSTS_NPTXQTOP_Pos)        // 0x40000000 */
 
 /********************  Bit definition for DTHRCTL register  ********************/
 #define DTHRCTL_NONISOTHREN_Pos          (0U)
-#define DTHRCTL_NONISOTHREN_Msk          (0x1UL << DTHRCTL_NONISOTHREN_Pos)       /*!< 0x00000001 */
-#define DTHRCTL_NONISOTHREN              DTHRCTL_NONISOTHREN_Msk                  /*!< Nonisochronous IN endpoints threshold enable */
+#define DTHRCTL_NONISOTHREN_Msk          (0x1UL << DTHRCTL_NONISOTHREN_Pos)       // 0x00000001 */
+#define DTHRCTL_NONISOTHREN              DTHRCTL_NONISOTHREN_Msk                  // Nonisochronous IN endpoints threshold enable */
 #define DTHRCTL_ISOTHREN_Pos             (1U)
-#define DTHRCTL_ISOTHREN_Msk             (0x1UL << DTHRCTL_ISOTHREN_Pos)          /*!< 0x00000002 */
-#define DTHRCTL_ISOTHREN                 DTHRCTL_ISOTHREN_Msk                     /*!< ISO IN endpoint threshold enable */
+#define DTHRCTL_ISOTHREN_Msk             (0x1UL << DTHRCTL_ISOTHREN_Pos)          // 0x00000002 */
+#define DTHRCTL_ISOTHREN                 DTHRCTL_ISOTHREN_Msk                     // ISO IN endpoint threshold enable */
 
 #define DTHRCTL_TXTHRLEN_Pos             (2U)
-#define DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x000007FC */
-#define DTHRCTL_TXTHRLEN                 DTHRCTL_TXTHRLEN_Msk                     /*!< Transmit threshold length */
-#define DTHRCTL_TXTHRLEN_0               (0x001UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000004 */
-#define DTHRCTL_TXTHRLEN_1               (0x002UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000008 */
-#define DTHRCTL_TXTHRLEN_2               (0x004UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000010 */
-#define DTHRCTL_TXTHRLEN_3               (0x008UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000020 */
-#define DTHRCTL_TXTHRLEN_4               (0x010UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000040 */
-#define DTHRCTL_TXTHRLEN_5               (0x020UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000080 */
-#define DTHRCTL_TXTHRLEN_6               (0x040UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000100 */
-#define DTHRCTL_TXTHRLEN_7               (0x080UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000200 */
-#define DTHRCTL_TXTHRLEN_8               (0x100UL << DTHRCTL_TXTHRLEN_Pos)        /*!< 0x00000400 */
+#define DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << DTHRCTL_TXTHRLEN_Pos)        // 0x000007FC */
+#define DTHRCTL_TXTHRLEN                 DTHRCTL_TXTHRLEN_Msk                     // Transmit threshold length */
+#define DTHRCTL_TXTHRLEN_0               (0x001UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000004 */
+#define DTHRCTL_TXTHRLEN_1               (0x002UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000008 */
+#define DTHRCTL_TXTHRLEN_2               (0x004UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000010 */
+#define DTHRCTL_TXTHRLEN_3               (0x008UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000020 */
+#define DTHRCTL_TXTHRLEN_4               (0x010UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000040 */
+#define DTHRCTL_TXTHRLEN_5               (0x020UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000080 */
+#define DTHRCTL_TXTHRLEN_6               (0x040UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000100 */
+#define DTHRCTL_TXTHRLEN_7               (0x080UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000200 */
+#define DTHRCTL_TXTHRLEN_8               (0x100UL << DTHRCTL_TXTHRLEN_Pos)        // 0x00000400 */
 #define DTHRCTL_RXTHREN_Pos              (16U)
-#define DTHRCTL_RXTHREN_Msk              (0x1UL << DTHRCTL_RXTHREN_Pos)           /*!< 0x00010000 */
-#define DTHRCTL_RXTHREN                  DTHRCTL_RXTHREN_Msk                      /*!< Receive threshold enable */
+#define DTHRCTL_RXTHREN_Msk              (0x1UL << DTHRCTL_RXTHREN_Pos)           // 0x00010000 */
+#define DTHRCTL_RXTHREN                  DTHRCTL_RXTHREN_Msk                      // Receive threshold enable */
 
 #define DTHRCTL_RXTHRLEN_Pos             (17U)
-#define DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x03FE0000 */
-#define DTHRCTL_RXTHRLEN                 DTHRCTL_RXTHRLEN_Msk                     /*!< Receive threshold length */
-#define DTHRCTL_RXTHRLEN_0               (0x001UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00020000 */
-#define DTHRCTL_RXTHRLEN_1               (0x002UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00040000 */
-#define DTHRCTL_RXTHRLEN_2               (0x004UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00080000 */
-#define DTHRCTL_RXTHRLEN_3               (0x008UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00100000 */
-#define DTHRCTL_RXTHRLEN_4               (0x010UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00200000 */
-#define DTHRCTL_RXTHRLEN_5               (0x020UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00400000 */
-#define DTHRCTL_RXTHRLEN_6               (0x040UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x00800000 */
-#define DTHRCTL_RXTHRLEN_7               (0x080UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x01000000 */
-#define DTHRCTL_RXTHRLEN_8               (0x100UL << DTHRCTL_RXTHRLEN_Pos)        /*!< 0x02000000 */
+#define DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << DTHRCTL_RXTHRLEN_Pos)        // 0x03FE0000 */
+#define DTHRCTL_RXTHRLEN                 DTHRCTL_RXTHRLEN_Msk                     // Receive threshold length */
+#define DTHRCTL_RXTHRLEN_0               (0x001UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00020000 */
+#define DTHRCTL_RXTHRLEN_1               (0x002UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00040000 */
+#define DTHRCTL_RXTHRLEN_2               (0x004UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00080000 */
+#define DTHRCTL_RXTHRLEN_3               (0x008UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00100000 */
+#define DTHRCTL_RXTHRLEN_4               (0x010UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00200000 */
+#define DTHRCTL_RXTHRLEN_5               (0x020UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00400000 */
+#define DTHRCTL_RXTHRLEN_6               (0x040UL << DTHRCTL_RXTHRLEN_Pos)        // 0x00800000 */
+#define DTHRCTL_RXTHRLEN_7               (0x080UL << DTHRCTL_RXTHRLEN_Pos)        // 0x01000000 */
+#define DTHRCTL_RXTHRLEN_8               (0x100UL << DTHRCTL_RXTHRLEN_Pos)        // 0x02000000 */
 #define DTHRCTL_ARPEN_Pos                (27U)
-#define DTHRCTL_ARPEN_Msk                (0x1UL << DTHRCTL_ARPEN_Pos)             /*!< 0x08000000 */
-#define DTHRCTL_ARPEN                    DTHRCTL_ARPEN_Msk                        /*!< Arbiter parking enable */
+#define DTHRCTL_ARPEN_Msk                (0x1UL << DTHRCTL_ARPEN_Pos)             // 0x08000000 */
+#define DTHRCTL_ARPEN                    DTHRCTL_ARPEN_Msk                        // Arbiter parking enable */
 
 /********************  Bit definition for DIEPEMPMSK register  ********************/
 #define DIEPEMPMSK_INEPTXFEM_Pos         (0U)
-#define DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos)   /*!< 0x0000FFFF */
-#define DIEPEMPMSK_INEPTXFEM             DIEPEMPMSK_INEPTXFEM_Msk                 /*!< IN EP Tx FIFO empty interrupt mask bits */
+#define DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << DIEPEMPMSK_INEPTXFEM_Pos)   // 0x0000FFFF */
+#define DIEPEMPMSK_INEPTXFEM             DIEPEMPMSK_INEPTXFEM_Msk                 // IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition for DEACHINT register  ********************/
 #define DEACHINT_IEP1INT_Pos             (1U)
-#define DEACHINT_IEP1INT_Msk             (0x1UL << DEACHINT_IEP1INT_Pos)          /*!< 0x00000002 */
-#define DEACHINT_IEP1INT                 DEACHINT_IEP1INT_Msk                     /*!< IN endpoint 1interrupt bit   */
+#define DEACHINT_IEP1INT_Msk             (0x1UL << DEACHINT_IEP1INT_Pos)          // 0x00000002 */
+#define DEACHINT_IEP1INT                 DEACHINT_IEP1INT_Msk                     // IN endpoint 1interrupt bit   */
 #define DEACHINT_OEP1INT_Pos             (17U)
-#define DEACHINT_OEP1INT_Msk             (0x1UL << DEACHINT_OEP1INT_Pos)          /*!< 0x00020000 */
-#define DEACHINT_OEP1INT                 DEACHINT_OEP1INT_Msk                     /*!< OUT endpoint 1 interrupt bit */
+#define DEACHINT_OEP1INT_Msk             (0x1UL << DEACHINT_OEP1INT_Pos)          // 0x00020000 */
+#define DEACHINT_OEP1INT                 DEACHINT_OEP1INT_Msk                     // OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition for GCCFG register  ********************/
 #define GCCFG_DCDET_Pos                  (0U)
-#define GCCFG_DCDET_Msk                  (0x1UL << GCCFG_DCDET_Pos)               /*!< 0x00000001 */
-#define GCCFG_DCDET                      GCCFG_DCDET_Msk                          /*!< Data contact detection (DCD) status */
+#define GCCFG_DCDET_Msk                  (0x1UL << GCCFG_DCDET_Pos)               // 0x00000001 */
+#define GCCFG_DCDET                      GCCFG_DCDET_Msk                          // Data contact detection (DCD) status */
 #define GCCFG_PDET_Pos                   (1U)
-#define GCCFG_PDET_Msk                   (0x1UL << GCCFG_PDET_Pos)                /*!< 0x00000002 */
-#define GCCFG_PDET                       GCCFG_PDET_Msk                           /*!< Primary detection (PD) status */
+#define GCCFG_PDET_Msk                   (0x1UL << GCCFG_PDET_Pos)                // 0x00000002 */
+#define GCCFG_PDET                       GCCFG_PDET_Msk                           // Primary detection (PD) status */
 #define GCCFG_SDET_Pos                   (2U)
-#define GCCFG_SDET_Msk                   (0x1UL << GCCFG_SDET_Pos)                /*!< 0x00000004 */
-#define GCCFG_SDET                       GCCFG_SDET_Msk                           /*!< Secondary detection (SD) status */
+#define GCCFG_SDET_Msk                   (0x1UL << GCCFG_SDET_Pos)                // 0x00000004 */
+#define GCCFG_SDET                       GCCFG_SDET_Msk                           // Secondary detection (SD) status */
 #define GCCFG_PS2DET_Pos                 (3U)
-#define GCCFG_PS2DET_Msk                 (0x1UL << GCCFG_PS2DET_Pos)              /*!< 0x00000008 */
-#define GCCFG_PS2DET                     GCCFG_PS2DET_Msk                         /*!< DM pull-up detection status */
+#define GCCFG_PS2DET_Msk                 (0x1UL << GCCFG_PS2DET_Pos)              // 0x00000008 */
+#define GCCFG_PS2DET                     GCCFG_PS2DET_Msk                         // DM pull-up detection status */
 #define GCCFG_PWRDWN_Pos                 (16U)
-#define GCCFG_PWRDWN_Msk                 (0x1UL << GCCFG_PWRDWN_Pos)              /*!< 0x00010000 */
-#define GCCFG_PWRDWN                     GCCFG_PWRDWN_Msk                         /*!< Power down */
+#define GCCFG_PWRDWN_Msk                 (0x1UL << GCCFG_PWRDWN_Pos)              // 0x00010000 */
+#define GCCFG_PWRDWN                     GCCFG_PWRDWN_Msk                         // Power down */
 #define GCCFG_BCDEN_Pos                  (17U)
-#define GCCFG_BCDEN_Msk                  (0x1UL << GCCFG_BCDEN_Pos)               /*!< 0x00020000 */
-#define GCCFG_BCDEN                      GCCFG_BCDEN_Msk                          /*!< Battery charging detector (BCD) enable */
+#define GCCFG_BCDEN_Msk                  (0x1UL << GCCFG_BCDEN_Pos)               // 0x00020000 */
+#define GCCFG_BCDEN                      GCCFG_BCDEN_Msk                          // Battery charging detector (BCD) enable */
 #define GCCFG_DCDEN_Pos                  (18U)
-#define GCCFG_DCDEN_Msk                  (0x1UL << GCCFG_DCDEN_Pos)               /*!< 0x00040000 */
-#define GCCFG_DCDEN                      GCCFG_DCDEN_Msk                          /*!< Data contact detection (DCD) mode enable*/
+#define GCCFG_DCDEN_Msk                  (0x1UL << GCCFG_DCDEN_Pos)               // 0x00040000 */
+#define GCCFG_DCDEN                      GCCFG_DCDEN_Msk                          // Data contact detection (DCD) mode enable*/
 #define GCCFG_PDEN_Pos                   (19U)
-#define GCCFG_PDEN_Msk                   (0x1UL << GCCFG_PDEN_Pos)                /*!< 0x00080000 */
-#define GCCFG_PDEN                       GCCFG_PDEN_Msk                           /*!< Primary detection (PD) mode enable*/
+#define GCCFG_PDEN_Msk                   (0x1UL << GCCFG_PDEN_Pos)                // 0x00080000 */
+#define GCCFG_PDEN                       GCCFG_PDEN_Msk                           // Primary detection (PD) mode enable*/
 #define GCCFG_SDEN_Pos                   (20U)
-#define GCCFG_SDEN_Msk                   (0x1UL << GCCFG_SDEN_Pos)                /*!< 0x00100000 */
-#define GCCFG_SDEN                       GCCFG_SDEN_Msk                           /*!< Secondary detection (SD) mode enable */
+#define GCCFG_SDEN_Msk                   (0x1UL << GCCFG_SDEN_Pos)                // 0x00100000 */
+#define GCCFG_SDEN                       GCCFG_SDEN_Msk                           // Secondary detection (SD) mode enable */
 #define GCCFG_VBDEN_Pos                  (21U)
-#define GCCFG_VBDEN_Msk                  (0x1UL << GCCFG_VBDEN_Pos)               /*!< 0x00200000 */
-#define GCCFG_VBDEN                      GCCFG_VBDEN_Msk                          /*!< VBUS mode enable */
+#define GCCFG_VBDEN_Msk                  (0x1UL << GCCFG_VBDEN_Pos)               // 0x00200000 */
+#define GCCFG_VBDEN                      GCCFG_VBDEN_Msk                          // VBUS mode enable */
 #define GCCFG_OTGIDEN_Pos                (22U)
-#define GCCFG_OTGIDEN_Msk                (0x1UL << GCCFG_OTGIDEN_Pos)             /*!< 0x00400000 */
-#define GCCFG_OTGIDEN                    GCCFG_OTGIDEN_Msk                        /*!< OTG Id enable */
+#define GCCFG_OTGIDEN_Msk                (0x1UL << GCCFG_OTGIDEN_Pos)             // 0x00400000 */
+#define GCCFG_OTGIDEN                    GCCFG_OTGIDEN_Msk                        // OTG Id enable */
 #define GCCFG_PHYHSEN_Pos                (23U)
-#define GCCFG_PHYHSEN_Msk                (0x1UL << GCCFG_PHYHSEN_Pos)             /*!< 0x00800000 */
-#define GCCFG_PHYHSEN                    GCCFG_PHYHSEN_Msk                        /*!< HS PHY enable */
+#define GCCFG_PHYHSEN_Msk                (0x1UL << GCCFG_PHYHSEN_Pos)             // 0x00800000 */
+#define GCCFG_PHYHSEN                    GCCFG_PHYHSEN_Msk                        // HS PHY enable */
 
 /********************  Bit definition for DEACHINTMSK register  ********************/
 #define DEACHINTMSK_IEP1INTM_Pos         (1U)
-#define DEACHINTMSK_IEP1INTM_Msk         (0x1UL << DEACHINTMSK_IEP1INTM_Pos)      /*!< 0x00000002 */
-#define DEACHINTMSK_IEP1INTM             DEACHINTMSK_IEP1INTM_Msk                 /*!< IN Endpoint 1 interrupt mask bit  */
+#define DEACHINTMSK_IEP1INTM_Msk         (0x1UL << DEACHINTMSK_IEP1INTM_Pos)      // 0x00000002 */
+#define DEACHINTMSK_IEP1INTM             DEACHINTMSK_IEP1INTM_Msk                 // IN Endpoint 1 interrupt mask bit  */
 #define DEACHINTMSK_OEP1INTM_Pos         (17U)
-#define DEACHINTMSK_OEP1INTM_Msk         (0x1UL << DEACHINTMSK_OEP1INTM_Pos)      /*!< 0x00020000 */
-#define DEACHINTMSK_OEP1INTM             DEACHINTMSK_OEP1INTM_Msk                 /*!< OUT Endpoint 1 interrupt mask bit */
+#define DEACHINTMSK_OEP1INTM_Msk         (0x1UL << DEACHINTMSK_OEP1INTM_Pos)      // 0x00020000 */
+#define DEACHINTMSK_OEP1INTM             DEACHINTMSK_OEP1INTM_Msk                 // OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition for CID register  ********************/
 #define CID_PRODUCT_ID_Pos               (0U)
-#define CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos)     /*!< 0xFFFFFFFF */
-#define CID_PRODUCT_ID                   CID_PRODUCT_ID_Msk                       /*!< Product ID field */
+#define CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << CID_PRODUCT_ID_Pos)     // 0xFFFFFFFF */
+#define CID_PRODUCT_ID                   CID_PRODUCT_ID_Msk                       // Product ID field */
 
 /********************  Bit definition for GLPMCFG register  ********************/
 #define GLPMCFG_LPMEN_Pos                (0U)
-#define GLPMCFG_LPMEN_Msk                (0x1UL << GLPMCFG_LPMEN_Pos)             /*!< 0x00000001 */
-#define GLPMCFG_LPMEN                    GLPMCFG_LPMEN_Msk                        /*!< LPM support enable                                     */
+#define GLPMCFG_LPMEN_Msk                (0x1UL << GLPMCFG_LPMEN_Pos)             // 0x00000001 */
+#define GLPMCFG_LPMEN                    GLPMCFG_LPMEN_Msk                        // LPM support enable                                     */
 #define GLPMCFG_LPMACK_Pos               (1U)
-#define GLPMCFG_LPMACK_Msk               (0x1UL << GLPMCFG_LPMACK_Pos)            /*!< 0x00000002 */
-#define GLPMCFG_LPMACK                   GLPMCFG_LPMACK_Msk                       /*!< LPM Token acknowledge enable                           */
+#define GLPMCFG_LPMACK_Msk               (0x1UL << GLPMCFG_LPMACK_Pos)            // 0x00000002 */
+#define GLPMCFG_LPMACK                   GLPMCFG_LPMACK_Msk                       // LPM Token acknowledge enable                           */
 #define GLPMCFG_BESL_Pos                 (2U)
-#define GLPMCFG_BESL_Msk                 (0xFUL << GLPMCFG_BESL_Pos)              /*!< 0x0000003C */
-#define GLPMCFG_BESL                     GLPMCFG_BESL_Msk                         /*!< BESL value received with last ACKed LPM Token          */
+#define GLPMCFG_BESL_Msk                 (0xFUL << GLPMCFG_BESL_Pos)              // 0x0000003C */
+#define GLPMCFG_BESL                     GLPMCFG_BESL_Msk                         // BESL value received with last ACKed LPM Token          */
 #define GLPMCFG_REMWAKE_Pos              (6U)
-#define GLPMCFG_REMWAKE_Msk              (0x1UL << GLPMCFG_REMWAKE_Pos)           /*!< 0x00000040 */
-#define GLPMCFG_REMWAKE                  GLPMCFG_REMWAKE_Msk                      /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define GLPMCFG_REMWAKE_Msk              (0x1UL << GLPMCFG_REMWAKE_Pos)           // 0x00000040 */
+#define GLPMCFG_REMWAKE                  GLPMCFG_REMWAKE_Msk                      // bRemoteWake value received with last ACKed LPM Token   */
 #define GLPMCFG_L1SSEN_Pos               (7U)
-#define GLPMCFG_L1SSEN_Msk               (0x1UL << GLPMCFG_L1SSEN_Pos)            /*!< 0x00000080 */
-#define GLPMCFG_L1SSEN                   GLPMCFG_L1SSEN_Msk                       /*!< L1 shallow sleep enable                                */
+#define GLPMCFG_L1SSEN_Msk               (0x1UL << GLPMCFG_L1SSEN_Pos)            // 0x00000080 */
+#define GLPMCFG_L1SSEN                   GLPMCFG_L1SSEN_Msk                       // L1 shallow sleep enable                                */
 #define GLPMCFG_BESLTHRS_Pos             (8U)
-#define GLPMCFG_BESLTHRS_Msk             (0xFUL << GLPMCFG_BESLTHRS_Pos)          /*!< 0x00000F00 */
-#define GLPMCFG_BESLTHRS                 GLPMCFG_BESLTHRS_Msk                     /*!< BESL threshold                                         */
+#define GLPMCFG_BESLTHRS_Msk             (0xFUL << GLPMCFG_BESLTHRS_Pos)          // 0x00000F00 */
+#define GLPMCFG_BESLTHRS                 GLPMCFG_BESLTHRS_Msk                     // BESL threshold                                         */
 #define GLPMCFG_L1DSEN_Pos               (12U)
-#define GLPMCFG_L1DSEN_Msk               (0x1UL << GLPMCFG_L1DSEN_Pos)            /*!< 0x00001000 */
-#define GLPMCFG_L1DSEN                   GLPMCFG_L1DSEN_Msk                       /*!< L1 deep sleep enable                                   */
+#define GLPMCFG_L1DSEN_Msk               (0x1UL << GLPMCFG_L1DSEN_Pos)            // 0x00001000 */
+#define GLPMCFG_L1DSEN                   GLPMCFG_L1DSEN_Msk                       // L1 deep sleep enable                                   */
 #define GLPMCFG_LPMRSP_Pos               (13U)
-#define GLPMCFG_LPMRSP_Msk               (0x3UL << GLPMCFG_LPMRSP_Pos)            /*!< 0x00006000 */
-#define GLPMCFG_LPMRSP                   GLPMCFG_LPMRSP_Msk                       /*!< LPM response                                           */
+#define GLPMCFG_LPMRSP_Msk               (0x3UL << GLPMCFG_LPMRSP_Pos)            // 0x00006000 */
+#define GLPMCFG_LPMRSP                   GLPMCFG_LPMRSP_Msk                       // LPM response                                           */
 #define GLPMCFG_SLPSTS_Pos               (15U)
-#define GLPMCFG_SLPSTS_Msk               (0x1UL << GLPMCFG_SLPSTS_Pos)            /*!< 0x00008000 */
-#define GLPMCFG_SLPSTS                   GLPMCFG_SLPSTS_Msk                       /*!< Port sleep status                                      */
+#define GLPMCFG_SLPSTS_Msk               (0x1UL << GLPMCFG_SLPSTS_Pos)            // 0x00008000 */
+#define GLPMCFG_SLPSTS                   GLPMCFG_SLPSTS_Msk                       // Port sleep status                                      */
 #define GLPMCFG_L1RSMOK_Pos              (16U)
-#define GLPMCFG_L1RSMOK_Msk              (0x1UL << GLPMCFG_L1RSMOK_Pos)           /*!< 0x00010000 */
-#define GLPMCFG_L1RSMOK                  GLPMCFG_L1RSMOK_Msk                      /*!< Sleep State Resume OK                                  */
+#define GLPMCFG_L1RSMOK_Msk              (0x1UL << GLPMCFG_L1RSMOK_Pos)           // 0x00010000 */
+#define GLPMCFG_L1RSMOK                  GLPMCFG_L1RSMOK_Msk                      // Sleep State Resume OK                                  */
 #define GLPMCFG_LPMCHIDX_Pos             (17U)
-#define GLPMCFG_LPMCHIDX_Msk             (0xFUL << GLPMCFG_LPMCHIDX_Pos)          /*!< 0x001E0000 */
-#define GLPMCFG_LPMCHIDX                 GLPMCFG_LPMCHIDX_Msk                     /*!< LPM Channel Index                                      */
+#define GLPMCFG_LPMCHIDX_Msk             (0xFUL << GLPMCFG_LPMCHIDX_Pos)          // 0x001E0000 */
+#define GLPMCFG_LPMCHIDX                 GLPMCFG_LPMCHIDX_Msk                     // LPM Channel Index                                      */
 #define GLPMCFG_LPMRCNT_Pos              (21U)
-#define GLPMCFG_LPMRCNT_Msk              (0x7UL << GLPMCFG_LPMRCNT_Pos)           /*!< 0x00E00000 */
-#define GLPMCFG_LPMRCNT                  GLPMCFG_LPMRCNT_Msk                      /*!< LPM retry count                                        */
+#define GLPMCFG_LPMRCNT_Msk              (0x7UL << GLPMCFG_LPMRCNT_Pos)           // 0x00E00000 */
+#define GLPMCFG_LPMRCNT                  GLPMCFG_LPMRCNT_Msk                      // LPM retry count                                        */
 #define GLPMCFG_SNDLPM_Pos               (24U)
-#define GLPMCFG_SNDLPM_Msk               (0x1UL << GLPMCFG_SNDLPM_Pos)            /*!< 0x01000000 */
-#define GLPMCFG_SNDLPM                   GLPMCFG_SNDLPM_Msk                       /*!< Send LPM transaction                                   */
+#define GLPMCFG_SNDLPM_Msk               (0x1UL << GLPMCFG_SNDLPM_Pos)            // 0x01000000 */
+#define GLPMCFG_SNDLPM                   GLPMCFG_SNDLPM_Msk                       // Send LPM transaction                                   */
 #define GLPMCFG_LPMRCNTSTS_Pos           (25U)
-#define GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << GLPMCFG_LPMRCNTSTS_Pos)        /*!< 0x0E000000 */
-#define GLPMCFG_LPMRCNTSTS               GLPMCFG_LPMRCNTSTS_Msk                   /*!< LPM retry count status                                 */
+#define GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << GLPMCFG_LPMRCNTSTS_Pos)        // 0x0E000000 */
+#define GLPMCFG_LPMRCNTSTS               GLPMCFG_LPMRCNTSTS_Msk                   // LPM retry count status                                 */
 #define GLPMCFG_ENBESL_Pos               (28U)
-#define GLPMCFG_ENBESL_Msk               (0x1UL << GLPMCFG_ENBESL_Pos)            /*!< 0x10000000 */
-#define GLPMCFG_ENBESL                   GLPMCFG_ENBESL_Msk                       /*!< Enable best effort service latency                     */
+#define GLPMCFG_ENBESL_Msk               (0x1UL << GLPMCFG_ENBESL_Pos)            // 0x10000000 */
+#define GLPMCFG_ENBESL                   GLPMCFG_ENBESL_Msk                       // Enable best effort service latency                     */
 
 /********************  Bit definition for DIEPEACHMSK1 register  ********************/
 #define DIEPEACHMSK1_XFRCM_Pos           (0U)
-#define DIEPEACHMSK1_XFRCM_Msk           (0x1UL << DIEPEACHMSK1_XFRCM_Pos)        /*!< 0x00000001 */
-#define DIEPEACHMSK1_XFRCM               DIEPEACHMSK1_XFRCM_Msk                   /*!< Transfer completed interrupt mask                 */
+#define DIEPEACHMSK1_XFRCM_Msk           (0x1UL << DIEPEACHMSK1_XFRCM_Pos)        // 0x00000001 */
+#define DIEPEACHMSK1_XFRCM               DIEPEACHMSK1_XFRCM_Msk                   // Transfer completed interrupt mask                 */
 #define DIEPEACHMSK1_EPDM_Pos            (1U)
-#define DIEPEACHMSK1_EPDM_Msk            (0x1UL << DIEPEACHMSK1_EPDM_Pos)         /*!< 0x00000002 */
-#define DIEPEACHMSK1_EPDM                DIEPEACHMSK1_EPDM_Msk                    /*!< Endpoint disabled interrupt mask                  */
+#define DIEPEACHMSK1_EPDM_Msk            (0x1UL << DIEPEACHMSK1_EPDM_Pos)         // 0x00000002 */
+#define DIEPEACHMSK1_EPDM                DIEPEACHMSK1_EPDM_Msk                    // Endpoint disabled interrupt mask                  */
 #define DIEPEACHMSK1_TOM_Pos             (3U)
-#define DIEPEACHMSK1_TOM_Msk             (0x1UL << DIEPEACHMSK1_TOM_Pos)          /*!< 0x00000008 */
-#define DIEPEACHMSK1_TOM                 DIEPEACHMSK1_TOM_Msk                     /*!< Timeout condition mask (nonisochronous endpoints) */
+#define DIEPEACHMSK1_TOM_Msk             (0x1UL << DIEPEACHMSK1_TOM_Pos)          // 0x00000008 */
+#define DIEPEACHMSK1_TOM                 DIEPEACHMSK1_TOM_Msk                     // Timeout condition mask (nonisochronous endpoints) */
 #define DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
-#define DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos)    /*!< 0x00000010 */
-#define DIEPEACHMSK1_ITTXFEMSK           DIEPEACHMSK1_ITTXFEMSK_Msk               /*!< IN token received when TxFIFO empty mask          */
+#define DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DIEPEACHMSK1_ITTXFEMSK_Pos)    // 0x00000010 */
+#define DIEPEACHMSK1_ITTXFEMSK           DIEPEACHMSK1_ITTXFEMSK_Msk               // IN token received when TxFIFO empty mask          */
 #define DIEPEACHMSK1_INEPNMM_Pos         (5U)
-#define DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << DIEPEACHMSK1_INEPNMM_Pos)      /*!< 0x00000020 */
-#define DIEPEACHMSK1_INEPNMM             DIEPEACHMSK1_INEPNMM_Msk                 /*!< IN token received with EP mismatch mask           */
+#define DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << DIEPEACHMSK1_INEPNMM_Pos)      // 0x00000020 */
+#define DIEPEACHMSK1_INEPNMM             DIEPEACHMSK1_INEPNMM_Msk                 // IN token received with EP mismatch mask           */
 #define DIEPEACHMSK1_INEPNEM_Pos         (6U)
-#define DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << DIEPEACHMSK1_INEPNEM_Pos)      /*!< 0x00000040 */
-#define DIEPEACHMSK1_INEPNEM             DIEPEACHMSK1_INEPNEM_Msk                 /*!< IN endpoint NAK effective mask                    */
+#define DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << DIEPEACHMSK1_INEPNEM_Pos)      // 0x00000040 */
+#define DIEPEACHMSK1_INEPNEM             DIEPEACHMSK1_INEPNEM_Msk                 // IN endpoint NAK effective mask                    */
 #define DIEPEACHMSK1_TXFURM_Pos          (8U)
-#define DIEPEACHMSK1_TXFURM_Msk          (0x1UL << DIEPEACHMSK1_TXFURM_Pos)       /*!< 0x00000100 */
-#define DIEPEACHMSK1_TXFURM              DIEPEACHMSK1_TXFURM_Msk                  /*!< FIFO underrun mask                                */
+#define DIEPEACHMSK1_TXFURM_Msk          (0x1UL << DIEPEACHMSK1_TXFURM_Pos)       // 0x00000100 */
+#define DIEPEACHMSK1_TXFURM              DIEPEACHMSK1_TXFURM_Msk                  // FIFO underrun mask                                */
 #define DIEPEACHMSK1_BIM_Pos             (9U)
-#define DIEPEACHMSK1_BIM_Msk             (0x1UL << DIEPEACHMSK1_BIM_Pos)          /*!< 0x00000200 */
-#define DIEPEACHMSK1_BIM                 DIEPEACHMSK1_BIM_Msk                     /*!< BNA interrupt mask                                */
+#define DIEPEACHMSK1_BIM_Msk             (0x1UL << DIEPEACHMSK1_BIM_Pos)          // 0x00000200 */
+#define DIEPEACHMSK1_BIM                 DIEPEACHMSK1_BIM_Msk                     // BNA interrupt mask                                */
 #define DIEPEACHMSK1_NAKM_Pos            (13U)
-#define DIEPEACHMSK1_NAKM_Msk            (0x1UL << DIEPEACHMSK1_NAKM_Pos)         /*!< 0x00002000 */
-#define DIEPEACHMSK1_NAKM                DIEPEACHMSK1_NAKM_Msk                    /*!< NAK interrupt mask                                */
+#define DIEPEACHMSK1_NAKM_Msk            (0x1UL << DIEPEACHMSK1_NAKM_Pos)         // 0x00002000 */
+#define DIEPEACHMSK1_NAKM                DIEPEACHMSK1_NAKM_Msk                    // NAK interrupt mask                                */
 
 /********************  Bit definition for HPRT register  ********************/
 #define HPRT_PCSTS_Pos                   (0U)
-#define HPRT_PCSTS_Msk                   (0x1UL << HPRT_PCSTS_Pos)                /*!< 0x00000001 */
-#define HPRT_PCSTS                       HPRT_PCSTS_Msk                           /*!< Port connect status        */
+#define HPRT_PCSTS_Msk                   (0x1UL << HPRT_PCSTS_Pos)                // 0x00000001 */
+#define HPRT_PCSTS                       HPRT_PCSTS_Msk                           // Port connect status        */
 #define HPRT_PCDET_Pos                   (1U)
-#define HPRT_PCDET_Msk                   (0x1UL << HPRT_PCDET_Pos)                /*!< 0x00000002 */
-#define HPRT_PCDET                       HPRT_PCDET_Msk                           /*!< Port connect detected      */
+#define HPRT_PCDET_Msk                   (0x1UL << HPRT_PCDET_Pos)                // 0x00000002 */
+#define HPRT_PCDET                       HPRT_PCDET_Msk                           // Port connect detected      */
 #define HPRT_PENA_Pos                    (2U)
-#define HPRT_PENA_Msk                    (0x1UL << HPRT_PENA_Pos)                 /*!< 0x00000004 */
-#define HPRT_PENA                        HPRT_PENA_Msk                            /*!< Port enable                */
+#define HPRT_PENA_Msk                    (0x1UL << HPRT_PENA_Pos)                 // 0x00000004 */
+#define HPRT_PENA                        HPRT_PENA_Msk                            // Port enable                */
 #define HPRT_PENCHNG_Pos                 (3U)
-#define HPRT_PENCHNG_Msk                 (0x1UL << HPRT_PENCHNG_Pos)              /*!< 0x00000008 */
-#define HPRT_PENCHNG                     HPRT_PENCHNG_Msk                         /*!< Port enable/disable change */
+#define HPRT_PENCHNG_Msk                 (0x1UL << HPRT_PENCHNG_Pos)              // 0x00000008 */
+#define HPRT_PENCHNG                     HPRT_PENCHNG_Msk                         // Port enable/disable change */
 #define HPRT_POCA_Pos                    (4U)
-#define HPRT_POCA_Msk                    (0x1UL << HPRT_POCA_Pos)                 /*!< 0x00000010 */
-#define HPRT_POCA                        HPRT_POCA_Msk                            /*!< Port overcurrent active    */
+#define HPRT_POCA_Msk                    (0x1UL << HPRT_POCA_Pos)                 // 0x00000010 */
+#define HPRT_POCA                        HPRT_POCA_Msk                            // Port overcurrent active    */
 #define HPRT_POCCHNG_Pos                 (5U)
-#define HPRT_POCCHNG_Msk                 (0x1UL << HPRT_POCCHNG_Pos)              /*!< 0x00000020 */
-#define HPRT_POCCHNG                     HPRT_POCCHNG_Msk                         /*!< Port overcurrent change    */
+#define HPRT_POCCHNG_Msk                 (0x1UL << HPRT_POCCHNG_Pos)              // 0x00000020 */
+#define HPRT_POCCHNG                     HPRT_POCCHNG_Msk                         // Port overcurrent change    */
 #define HPRT_PRES_Pos                    (6U)
-#define HPRT_PRES_Msk                    (0x1UL << HPRT_PRES_Pos)                 /*!< 0x00000040 */
-#define HPRT_PRES                        HPRT_PRES_Msk                            /*!< Port resume                */
+#define HPRT_PRES_Msk                    (0x1UL << HPRT_PRES_Pos)                 // 0x00000040 */
+#define HPRT_PRES                        HPRT_PRES_Msk                            // Port resume                */
 #define HPRT_PSUSP_Pos                   (7U)
-#define HPRT_PSUSP_Msk                   (0x1UL << HPRT_PSUSP_Pos)                /*!< 0x00000080 */
-#define HPRT_PSUSP                       HPRT_PSUSP_Msk                           /*!< Port suspend               */
+#define HPRT_PSUSP_Msk                   (0x1UL << HPRT_PSUSP_Pos)                // 0x00000080 */
+#define HPRT_PSUSP                       HPRT_PSUSP_Msk                           // Port suspend               */
 #define HPRT_PRST_Pos                    (8U)
-#define HPRT_PRST_Msk                    (0x1UL << HPRT_PRST_Pos)                 /*!< 0x00000100 */
-#define HPRT_PRST                        HPRT_PRST_Msk                            /*!< Port reset                 */
+#define HPRT_PRST_Msk                    (0x1UL << HPRT_PRST_Pos)                 // 0x00000100 */
+#define HPRT_PRST                        HPRT_PRST_Msk                            // Port reset                 */
 
 #define HPRT_PLSTS_Pos                   (10U)
-#define HPRT_PLSTS_Msk                   (0x3UL << HPRT_PLSTS_Pos)                /*!< 0x00000C00 */
-#define HPRT_PLSTS                       HPRT_PLSTS_Msk                           /*!< Port line status           */
-#define HPRT_PLSTS_0                     (0x1UL << HPRT_PLSTS_Pos)                /*!< 0x00000400 */
-#define HPRT_PLSTS_1                     (0x2UL << HPRT_PLSTS_Pos)                /*!< 0x00000800 */
+#define HPRT_PLSTS_Msk                   (0x3UL << HPRT_PLSTS_Pos)                // 0x00000C00 */
+#define HPRT_PLSTS                       HPRT_PLSTS_Msk                           // Port line status           */
+#define HPRT_PLSTS_0                     (0x1UL << HPRT_PLSTS_Pos)                // 0x00000400 */
+#define HPRT_PLSTS_1                     (0x2UL << HPRT_PLSTS_Pos)                // 0x00000800 */
 #define HPRT_PPWR_Pos                    (12U)
-#define HPRT_PPWR_Msk                    (0x1UL << HPRT_PPWR_Pos)                 /*!< 0x00001000 */
-#define HPRT_PPWR                        HPRT_PPWR_Msk                            /*!< Port power                 */
+#define HPRT_PPWR_Msk                    (0x1UL << HPRT_PPWR_Pos)                 // 0x00001000 */
+#define HPRT_PPWR                        HPRT_PPWR_Msk                            // Port power                 */
 
 #define HPRT_PTCTL_Pos                   (13U)
-#define HPRT_PTCTL_Msk                   (0xFUL << HPRT_PTCTL_Pos)                /*!< 0x0001E000 */
-#define HPRT_PTCTL                       HPRT_PTCTL_Msk                           /*!< Port test control          */
-#define HPRT_PTCTL_0                     (0x1UL << HPRT_PTCTL_Pos)                /*!< 0x00002000 */
-#define HPRT_PTCTL_1                     (0x2UL << HPRT_PTCTL_Pos)                /*!< 0x00004000 */
-#define HPRT_PTCTL_2                     (0x4UL << HPRT_PTCTL_Pos)                /*!< 0x00008000 */
-#define HPRT_PTCTL_3                     (0x8UL << HPRT_PTCTL_Pos)                /*!< 0x00010000 */
+#define HPRT_PTCTL_Msk                   (0xFUL << HPRT_PTCTL_Pos)                // 0x0001E000 */
+#define HPRT_PTCTL                       HPRT_PTCTL_Msk                           // Port test control          */
+#define HPRT_PTCTL_0                     (0x1UL << HPRT_PTCTL_Pos)                // 0x00002000 */
+#define HPRT_PTCTL_1                     (0x2UL << HPRT_PTCTL_Pos)                // 0x00004000 */
+#define HPRT_PTCTL_2                     (0x4UL << HPRT_PTCTL_Pos)                // 0x00008000 */
+#define HPRT_PTCTL_3                     (0x8UL << HPRT_PTCTL_Pos)                // 0x00010000 */
 
 #define HPRT_PSPD_Pos                    (17U)
-#define HPRT_PSPD_Msk                    (0x3UL << HPRT_PSPD_Pos)                 /*!< 0x00060000 */
-#define HPRT_PSPD                        HPRT_PSPD_Msk                            /*!< Port speed                 */
-#define HPRT_PSPD_0                      (0x1UL << HPRT_PSPD_Pos)                 /*!< 0x00020000 */
-#define HPRT_PSPD_1                      (0x2UL << HPRT_PSPD_Pos)                 /*!< 0x00040000 */
+#define HPRT_PSPD_Msk                    (0x3UL << HPRT_PSPD_Pos)                 // 0x00060000 */
+#define HPRT_PSPD                        HPRT_PSPD_Msk                            // Port speed                 */
+#define HPRT_PSPD_0                      (0x1UL << HPRT_PSPD_Pos)                 // 0x00020000 */
+#define HPRT_PSPD_1                      (0x2UL << HPRT_PSPD_Pos)                 // 0x00040000 */
 
 /********************  Bit definition for DOEPEACHMSK1 register  ********************/
 #define DOEPEACHMSK1_XFRCM_Pos           (0U)
-#define DOEPEACHMSK1_XFRCM_Msk           (0x1UL << DOEPEACHMSK1_XFRCM_Pos)        /*!< 0x00000001 */
-#define DOEPEACHMSK1_XFRCM               DOEPEACHMSK1_XFRCM_Msk                   /*!< Transfer completed interrupt mask         */
+#define DOEPEACHMSK1_XFRCM_Msk           (0x1UL << DOEPEACHMSK1_XFRCM_Pos)        // 0x00000001 */
+#define DOEPEACHMSK1_XFRCM               DOEPEACHMSK1_XFRCM_Msk                   // Transfer completed interrupt mask         */
 #define DOEPEACHMSK1_EPDM_Pos            (1U)
-#define DOEPEACHMSK1_EPDM_Msk            (0x1UL << DOEPEACHMSK1_EPDM_Pos)         /*!< 0x00000002 */
-#define DOEPEACHMSK1_EPDM                DOEPEACHMSK1_EPDM_Msk                    /*!< Endpoint disabled interrupt mask          */
+#define DOEPEACHMSK1_EPDM_Msk            (0x1UL << DOEPEACHMSK1_EPDM_Pos)         // 0x00000002 */
+#define DOEPEACHMSK1_EPDM                DOEPEACHMSK1_EPDM_Msk                    // Endpoint disabled interrupt mask          */
 #define DOEPEACHMSK1_TOM_Pos             (3U)
-#define DOEPEACHMSK1_TOM_Msk             (0x1UL << DOEPEACHMSK1_TOM_Pos)          /*!< 0x00000008 */
-#define DOEPEACHMSK1_TOM                 DOEPEACHMSK1_TOM_Msk                     /*!< Timeout condition mask                    */
+#define DOEPEACHMSK1_TOM_Msk             (0x1UL << DOEPEACHMSK1_TOM_Pos)          // 0x00000008 */
+#define DOEPEACHMSK1_TOM                 DOEPEACHMSK1_TOM_Msk                     // Timeout condition mask                    */
 #define DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
-#define DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos)    /*!< 0x00000010 */
-#define DOEPEACHMSK1_ITTXFEMSK           DOEPEACHMSK1_ITTXFEMSK_Msk               /*!< IN token received when TxFIFO empty mask  */
+#define DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << DOEPEACHMSK1_ITTXFEMSK_Pos)    // 0x00000010 */
+#define DOEPEACHMSK1_ITTXFEMSK           DOEPEACHMSK1_ITTXFEMSK_Msk               // IN token received when TxFIFO empty mask  */
 #define DOEPEACHMSK1_INEPNMM_Pos         (5U)
-#define DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << DOEPEACHMSK1_INEPNMM_Pos)      /*!< 0x00000020 */
-#define DOEPEACHMSK1_INEPNMM             DOEPEACHMSK1_INEPNMM_Msk                 /*!< IN token received with EP mismatch mask   */
+#define DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << DOEPEACHMSK1_INEPNMM_Pos)      // 0x00000020 */
+#define DOEPEACHMSK1_INEPNMM             DOEPEACHMSK1_INEPNMM_Msk                 // IN token received with EP mismatch mask   */
 #define DOEPEACHMSK1_INEPNEM_Pos         (6U)
-#define DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << DOEPEACHMSK1_INEPNEM_Pos)      /*!< 0x00000040 */
-#define DOEPEACHMSK1_INEPNEM             DOEPEACHMSK1_INEPNEM_Msk                 /*!< IN endpoint NAK effective mask            */
+#define DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << DOEPEACHMSK1_INEPNEM_Pos)      // 0x00000040 */
+#define DOEPEACHMSK1_INEPNEM             DOEPEACHMSK1_INEPNEM_Msk                 // IN endpoint NAK effective mask            */
 #define DOEPEACHMSK1_TXFURM_Pos          (8U)
-#define DOEPEACHMSK1_TXFURM_Msk          (0x1UL << DOEPEACHMSK1_TXFURM_Pos)       /*!< 0x00000100 */
-#define DOEPEACHMSK1_TXFURM              DOEPEACHMSK1_TXFURM_Msk                  /*!< OUT packet error mask                     */
+#define DOEPEACHMSK1_TXFURM_Msk          (0x1UL << DOEPEACHMSK1_TXFURM_Pos)       // 0x00000100 */
+#define DOEPEACHMSK1_TXFURM              DOEPEACHMSK1_TXFURM_Msk                  // OUT packet error mask                     */
 #define DOEPEACHMSK1_BIM_Pos             (9U)
-#define DOEPEACHMSK1_BIM_Msk             (0x1UL << DOEPEACHMSK1_BIM_Pos)          /*!< 0x00000200 */
-#define DOEPEACHMSK1_BIM                 DOEPEACHMSK1_BIM_Msk                     /*!< BNA interrupt mask                        */
+#define DOEPEACHMSK1_BIM_Msk             (0x1UL << DOEPEACHMSK1_BIM_Pos)          // 0x00000200 */
+#define DOEPEACHMSK1_BIM                 DOEPEACHMSK1_BIM_Msk                     // BNA interrupt mask                        */
 #define DOEPEACHMSK1_BERRM_Pos           (12U)
-#define DOEPEACHMSK1_BERRM_Msk           (0x1UL << DOEPEACHMSK1_BERRM_Pos)        /*!< 0x00001000 */
-#define DOEPEACHMSK1_BERRM               DOEPEACHMSK1_BERRM_Msk                   /*!< Bubble error interrupt mask               */
+#define DOEPEACHMSK1_BERRM_Msk           (0x1UL << DOEPEACHMSK1_BERRM_Pos)        // 0x00001000 */
+#define DOEPEACHMSK1_BERRM               DOEPEACHMSK1_BERRM_Msk                   // Bubble error interrupt mask               */
 #define DOEPEACHMSK1_NAKM_Pos            (13U)
-#define DOEPEACHMSK1_NAKM_Msk            (0x1UL << DOEPEACHMSK1_NAKM_Pos)         /*!< 0x00002000 */
-#define DOEPEACHMSK1_NAKM                DOEPEACHMSK1_NAKM_Msk                    /*!< NAK interrupt mask                        */
+#define DOEPEACHMSK1_NAKM_Msk            (0x1UL << DOEPEACHMSK1_NAKM_Pos)         // 0x00002000 */
+#define DOEPEACHMSK1_NAKM                DOEPEACHMSK1_NAKM_Msk                    // NAK interrupt mask                        */
 #define DOEPEACHMSK1_NYETM_Pos           (14U)
-#define DOEPEACHMSK1_NYETM_Msk           (0x1UL << DOEPEACHMSK1_NYETM_Pos)        /*!< 0x00004000 */
-#define DOEPEACHMSK1_NYETM               DOEPEACHMSK1_NYETM_Msk                   /*!< NYET interrupt mask                       */
+#define DOEPEACHMSK1_NYETM_Msk           (0x1UL << DOEPEACHMSK1_NYETM_Pos)        // 0x00004000 */
+#define DOEPEACHMSK1_NYETM               DOEPEACHMSK1_NYETM_Msk                   // NYET interrupt mask                       */
 
 /********************  Bit definition for HPTXFSIZ register  ********************/
 #define HPTXFSIZ_PTXSA_Pos               (0U)
-#define HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << HPTXFSIZ_PTXSA_Pos)         /*!< 0x0000FFFF */
-#define HPTXFSIZ_PTXSA                   HPTXFSIZ_PTXSA_Msk                       /*!< Host periodic TxFIFO start address            */
+#define HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << HPTXFSIZ_PTXSA_Pos)         // 0x0000FFFF */
+#define HPTXFSIZ_PTXSA                   HPTXFSIZ_PTXSA_Msk                       // Host periodic TxFIFO start address            */
 #define HPTXFSIZ_PTXFD_Pos               (16U)
-#define HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << HPTXFSIZ_PTXFD_Pos)         /*!< 0xFFFF0000 */
-#define HPTXFSIZ_PTXFD                   HPTXFSIZ_PTXFD_Msk                       /*!< Host periodic TxFIFO depth                    */
+#define HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << HPTXFSIZ_PTXFD_Pos)         // 0xFFFF0000 */
+#define HPTXFSIZ_PTXFD                   HPTXFSIZ_PTXFD_Msk                       // Host periodic TxFIFO depth                    */
 
 /********************  Bit definition for DIEPCTL register  ********************/
 #define DIEPCTL_MPSIZ_Pos                (0U)
-#define DIEPCTL_MPSIZ_Msk                (0x7FFUL << DIEPCTL_MPSIZ_Pos)           /*!< 0x000007FF */
-#define DIEPCTL_MPSIZ                    DIEPCTL_MPSIZ_Msk                        /*!< Maximum packet size              */
+#define DIEPCTL_MPSIZ_Msk                (0x7FFUL << DIEPCTL_MPSIZ_Pos)           // 0x000007FF */
+#define DIEPCTL_MPSIZ                    DIEPCTL_MPSIZ_Msk                        // Maximum packet size              */
 #define DIEPCTL_USBAEP_Pos               (15U)
-#define DIEPCTL_USBAEP_Msk               (0x1UL << DIEPCTL_USBAEP_Pos)            /*!< 0x00008000 */
-#define DIEPCTL_USBAEP                   DIEPCTL_USBAEP_Msk                       /*!< USB active endpoint              */
+#define DIEPCTL_USBAEP_Msk               (0x1UL << DIEPCTL_USBAEP_Pos)            // 0x00008000 */
+#define DIEPCTL_USBAEP                   DIEPCTL_USBAEP_Msk                       // USB active endpoint              */
 #define DIEPCTL_EONUM_DPID_Pos           (16U)
-#define DIEPCTL_EONUM_DPID_Msk           (0x1UL << DIEPCTL_EONUM_DPID_Pos)        /*!< 0x00010000 */
-#define DIEPCTL_EONUM_DPID               DIEPCTL_EONUM_DPID_Msk                   /*!< Even/odd frame                   */
+#define DIEPCTL_EONUM_DPID_Msk           (0x1UL << DIEPCTL_EONUM_DPID_Pos)        // 0x00010000 */
+#define DIEPCTL_EONUM_DPID               DIEPCTL_EONUM_DPID_Msk                   // Even/odd frame                   */
 #define DIEPCTL_NAKSTS_Pos               (17U)
-#define DIEPCTL_NAKSTS_Msk               (0x1UL << DIEPCTL_NAKSTS_Pos)            /*!< 0x00020000 */
-#define DIEPCTL_NAKSTS                   DIEPCTL_NAKSTS_Msk                       /*!< NAK status                       */
+#define DIEPCTL_NAKSTS_Msk               (0x1UL << DIEPCTL_NAKSTS_Pos)            // 0x00020000 */
+#define DIEPCTL_NAKSTS                   DIEPCTL_NAKSTS_Msk                       // NAK status                       */
 
 #define DIEPCTL_EPTYP_Pos                (18U)
-#define DIEPCTL_EPTYP_Msk                (0x3UL << DIEPCTL_EPTYP_Pos)             /*!< 0x000C0000 */
-#define DIEPCTL_EPTYP                    DIEPCTL_EPTYP_Msk                        /*!< Endpoint type                    */
-#define DIEPCTL_EPTYP_0                  (0x1UL << DIEPCTL_EPTYP_Pos)             /*!< 0x00040000 */
-#define DIEPCTL_EPTYP_1                  (0x2UL << DIEPCTL_EPTYP_Pos)             /*!< 0x00080000 */
+#define DIEPCTL_EPTYP_Msk                (0x3UL << DIEPCTL_EPTYP_Pos)             // 0x000C0000 */
+#define DIEPCTL_EPTYP                    DIEPCTL_EPTYP_Msk                        // Endpoint type                    */
+#define DIEPCTL_EPTYP_0                  (0x1UL << DIEPCTL_EPTYP_Pos)             // 0x00040000 */
+#define DIEPCTL_EPTYP_1                  (0x2UL << DIEPCTL_EPTYP_Pos)             // 0x00080000 */
 #define DIEPCTL_STALL_Pos                (21U)
-#define DIEPCTL_STALL_Msk                (0x1UL << DIEPCTL_STALL_Pos)             /*!< 0x00200000 */
-#define DIEPCTL_STALL                    DIEPCTL_STALL_Msk                        /*!< STALL handshake                  */
+#define DIEPCTL_STALL_Msk                (0x1UL << DIEPCTL_STALL_Pos)             // 0x00200000 */
+#define DIEPCTL_STALL                    DIEPCTL_STALL_Msk                        // STALL handshake                  */
 
 #define DIEPCTL_TXFNUM_Pos               (22U)
-#define DIEPCTL_TXFNUM_Msk               (0xFUL << DIEPCTL_TXFNUM_Pos)            /*!< 0x03C00000 */
-#define DIEPCTL_TXFNUM                   DIEPCTL_TXFNUM_Msk                       /*!< TxFIFO number                    */
-#define DIEPCTL_TXFNUM_0                 (0x1UL << DIEPCTL_TXFNUM_Pos)            /*!< 0x00400000 */
-#define DIEPCTL_TXFNUM_1                 (0x2UL << DIEPCTL_TXFNUM_Pos)            /*!< 0x00800000 */
-#define DIEPCTL_TXFNUM_2                 (0x4UL << DIEPCTL_TXFNUM_Pos)            /*!< 0x01000000 */
-#define DIEPCTL_TXFNUM_3                 (0x8UL << DIEPCTL_TXFNUM_Pos)            /*!< 0x02000000 */
+#define DIEPCTL_TXFNUM_Msk               (0xFUL << DIEPCTL_TXFNUM_Pos)            // 0x03C00000 */
+#define DIEPCTL_TXFNUM                   DIEPCTL_TXFNUM_Msk                       // TxFIFO number                    */
+#define DIEPCTL_TXFNUM_0                 (0x1UL << DIEPCTL_TXFNUM_Pos)            // 0x00400000 */
+#define DIEPCTL_TXFNUM_1                 (0x2UL << DIEPCTL_TXFNUM_Pos)            // 0x00800000 */
+#define DIEPCTL_TXFNUM_2                 (0x4UL << DIEPCTL_TXFNUM_Pos)            // 0x01000000 */
+#define DIEPCTL_TXFNUM_3                 (0x8UL << DIEPCTL_TXFNUM_Pos)            // 0x02000000 */
 #define DIEPCTL_CNAK_Pos                 (26U)
-#define DIEPCTL_CNAK_Msk                 (0x1UL << DIEPCTL_CNAK_Pos)              /*!< 0x04000000 */
-#define DIEPCTL_CNAK                     DIEPCTL_CNAK_Msk                         /*!< Clear NAK                        */
+#define DIEPCTL_CNAK_Msk                 (0x1UL << DIEPCTL_CNAK_Pos)              // 0x04000000 */
+#define DIEPCTL_CNAK                     DIEPCTL_CNAK_Msk                         // Clear NAK                        */
 #define DIEPCTL_SNAK_Pos                 (27U)
-#define DIEPCTL_SNAK_Msk                 (0x1UL << DIEPCTL_SNAK_Pos)              /*!< 0x08000000 */
-#define DIEPCTL_SNAK                     DIEPCTL_SNAK_Msk                         /*!< Set NAK */
+#define DIEPCTL_SNAK_Msk                 (0x1UL << DIEPCTL_SNAK_Pos)              // 0x08000000 */
+#define DIEPCTL_SNAK                     DIEPCTL_SNAK_Msk                         // Set NAK */
 #define DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
-#define DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos)    /*!< 0x10000000 */
-#define DIEPCTL_SD0PID_SEVNFRM           DIEPCTL_SD0PID_SEVNFRM_Msk               /*!< Set DATA0 PID                    */
+#define DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DIEPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000 */
+#define DIEPCTL_SD0PID_SEVNFRM           DIEPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID                    */
 #define DIEPCTL_SODDFRM_Pos              (29U)
-#define DIEPCTL_SODDFRM_Msk              (0x1UL << DIEPCTL_SODDFRM_Pos)           /*!< 0x20000000 */
-#define DIEPCTL_SODDFRM                  DIEPCTL_SODDFRM_Msk                      /*!< Set odd frame                    */
+#define DIEPCTL_SODDFRM_Msk              (0x1UL << DIEPCTL_SODDFRM_Pos)           // 0x20000000 */
+#define DIEPCTL_SODDFRM                  DIEPCTL_SODDFRM_Msk                      // Set odd frame                    */
 #define DIEPCTL_EPDIS_Pos                (30U)
-#define DIEPCTL_EPDIS_Msk                (0x1UL << DIEPCTL_EPDIS_Pos)             /*!< 0x40000000 */
-#define DIEPCTL_EPDIS                    DIEPCTL_EPDIS_Msk                        /*!< Endpoint disable                 */
+#define DIEPCTL_EPDIS_Msk                (0x1UL << DIEPCTL_EPDIS_Pos)             // 0x40000000 */
+#define DIEPCTL_EPDIS                    DIEPCTL_EPDIS_Msk                        // Endpoint disable                 */
 #define DIEPCTL_EPENA_Pos                (31U)
-#define DIEPCTL_EPENA_Msk                (0x1UL << DIEPCTL_EPENA_Pos)             /*!< 0x80000000 */
-#define DIEPCTL_EPENA                    DIEPCTL_EPENA_Msk                        /*!< Endpoint enable                  */
+#define DIEPCTL_EPENA_Msk                (0x1UL << DIEPCTL_EPENA_Pos)             // 0x80000000 */
+#define DIEPCTL_EPENA                    DIEPCTL_EPENA_Msk                        // Endpoint enable                  */
 
 /********************  Bit definition for HCCHAR register  ********************/
 #define HCCHAR_MPSIZ_Pos                 (0U)
-#define HCCHAR_MPSIZ_Msk                 (0x7FFUL << HCCHAR_MPSIZ_Pos)            /*!< 0x000007FF */
-#define HCCHAR_MPSIZ                     HCCHAR_MPSIZ_Msk                         /*!< Maximum packet size */
+#define HCCHAR_MPSIZ_Msk                 (0x7FFUL << HCCHAR_MPSIZ_Pos)            // 0x000007FF */
+#define HCCHAR_MPSIZ                     HCCHAR_MPSIZ_Msk                         // Maximum packet size */
 
 #define HCCHAR_EPNUM_Pos                 (11U)
-#define HCCHAR_EPNUM_Msk                 (0xFUL << HCCHAR_EPNUM_Pos)              /*!< 0x00007800 */
-#define HCCHAR_EPNUM                     HCCHAR_EPNUM_Msk                         /*!< Endpoint number */
-#define HCCHAR_EPNUM_0                   (0x1UL << HCCHAR_EPNUM_Pos)              /*!< 0x00000800 */
-#define HCCHAR_EPNUM_1                   (0x2UL << HCCHAR_EPNUM_Pos)              /*!< 0x00001000 */
-#define HCCHAR_EPNUM_2                   (0x4UL << HCCHAR_EPNUM_Pos)              /*!< 0x00002000 */
-#define HCCHAR_EPNUM_3                   (0x8UL << HCCHAR_EPNUM_Pos)              /*!< 0x00004000 */
+#define HCCHAR_EPNUM_Msk                 (0xFUL << HCCHAR_EPNUM_Pos)              // 0x00007800 */
+#define HCCHAR_EPNUM                     HCCHAR_EPNUM_Msk                         // Endpoint number */
+#define HCCHAR_EPNUM_0                   (0x1UL << HCCHAR_EPNUM_Pos)              // 0x00000800 */
+#define HCCHAR_EPNUM_1                   (0x2UL << HCCHAR_EPNUM_Pos)              // 0x00001000 */
+#define HCCHAR_EPNUM_2                   (0x4UL << HCCHAR_EPNUM_Pos)              // 0x00002000 */
+#define HCCHAR_EPNUM_3                   (0x8UL << HCCHAR_EPNUM_Pos)              // 0x00004000 */
 #define HCCHAR_EPDIR_Pos                 (15U)
-#define HCCHAR_EPDIR_Msk                 (0x1UL << HCCHAR_EPDIR_Pos)              /*!< 0x00008000 */
-#define HCCHAR_EPDIR                     HCCHAR_EPDIR_Msk                         /*!< Endpoint direction */
+#define HCCHAR_EPDIR_Msk                 (0x1UL << HCCHAR_EPDIR_Pos)              // 0x00008000 */
+#define HCCHAR_EPDIR                     HCCHAR_EPDIR_Msk                         // Endpoint direction */
 #define HCCHAR_LSDEV_Pos                 (17U)
-#define HCCHAR_LSDEV_Msk                 (0x1UL << HCCHAR_LSDEV_Pos)              /*!< 0x00020000 */
-#define HCCHAR_LSDEV                     HCCHAR_LSDEV_Msk                         /*!< Low-speed device */
+#define HCCHAR_LSDEV_Msk                 (0x1UL << HCCHAR_LSDEV_Pos)              // 0x00020000 */
+#define HCCHAR_LSDEV                     HCCHAR_LSDEV_Msk                         // Low-speed device */
 
 #define HCCHAR_EPTYP_Pos                 (18U)
-#define HCCHAR_EPTYP_Msk                 (0x3UL << HCCHAR_EPTYP_Pos)              /*!< 0x000C0000 */
-#define HCCHAR_EPTYP                     HCCHAR_EPTYP_Msk                         /*!< Endpoint type */
-#define HCCHAR_EPTYP_0                   (0x1UL << HCCHAR_EPTYP_Pos)              /*!< 0x00040000 */
-#define HCCHAR_EPTYP_1                   (0x2UL << HCCHAR_EPTYP_Pos)              /*!< 0x00080000 */
+#define HCCHAR_EPTYP_Msk                 (0x3UL << HCCHAR_EPTYP_Pos)              // 0x000C0000 */
+#define HCCHAR_EPTYP                     HCCHAR_EPTYP_Msk                         // Endpoint type */
+#define HCCHAR_EPTYP_0                   (0x1UL << HCCHAR_EPTYP_Pos)              // 0x00040000 */
+#define HCCHAR_EPTYP_1                   (0x2UL << HCCHAR_EPTYP_Pos)              // 0x00080000 */
 
 #define HCCHAR_MC_Pos                    (20U)
-#define HCCHAR_MC_Msk                    (0x3UL << HCCHAR_MC_Pos)                 /*!< 0x00300000 */
-#define HCCHAR_MC                        HCCHAR_MC_Msk                            /*!< Multi Count (MC) / Error Count (EC) */
-#define HCCHAR_MC_0                      (0x1UL << HCCHAR_MC_Pos)                 /*!< 0x00100000 */
-#define HCCHAR_MC_1                      (0x2UL << HCCHAR_MC_Pos)                 /*!< 0x00200000 */
+#define HCCHAR_MC_Msk                    (0x3UL << HCCHAR_MC_Pos)                 // 0x00300000 */
+#define HCCHAR_MC                        HCCHAR_MC_Msk                            // Multi Count (MC) / Error Count (EC) */
+#define HCCHAR_MC_0                      (0x1UL << HCCHAR_MC_Pos)                 // 0x00100000 */
+#define HCCHAR_MC_1                      (0x2UL << HCCHAR_MC_Pos)                 // 0x00200000 */
 
 #define HCCHAR_DAD_Pos                   (22U)
-#define HCCHAR_DAD_Msk                   (0x7FUL << HCCHAR_DAD_Pos)               /*!< 0x1FC00000 */
-#define HCCHAR_DAD                       HCCHAR_DAD_Msk                           /*!< Device address */
-#define HCCHAR_DAD_0                     (0x01UL << HCCHAR_DAD_Pos)               /*!< 0x00400000 */
-#define HCCHAR_DAD_1                     (0x02UL << HCCHAR_DAD_Pos)               /*!< 0x00800000 */
-#define HCCHAR_DAD_2                     (0x04UL << HCCHAR_DAD_Pos)               /*!< 0x01000000 */
-#define HCCHAR_DAD_3                     (0x08UL << HCCHAR_DAD_Pos)               /*!< 0x02000000 */
-#define HCCHAR_DAD_4                     (0x10UL << HCCHAR_DAD_Pos)               /*!< 0x04000000 */
-#define HCCHAR_DAD_5                     (0x20UL << HCCHAR_DAD_Pos)               /*!< 0x08000000 */
-#define HCCHAR_DAD_6                     (0x40UL << HCCHAR_DAD_Pos)               /*!< 0x10000000 */
+#define HCCHAR_DAD_Msk                   (0x7FUL << HCCHAR_DAD_Pos)               // 0x1FC00000 */
+#define HCCHAR_DAD                       HCCHAR_DAD_Msk                           // Device address */
+#define HCCHAR_DAD_0                     (0x01UL << HCCHAR_DAD_Pos)               // 0x00400000 */
+#define HCCHAR_DAD_1                     (0x02UL << HCCHAR_DAD_Pos)               // 0x00800000 */
+#define HCCHAR_DAD_2                     (0x04UL << HCCHAR_DAD_Pos)               // 0x01000000 */
+#define HCCHAR_DAD_3                     (0x08UL << HCCHAR_DAD_Pos)               // 0x02000000 */
+#define HCCHAR_DAD_4                     (0x10UL << HCCHAR_DAD_Pos)               // 0x04000000 */
+#define HCCHAR_DAD_5                     (0x20UL << HCCHAR_DAD_Pos)               // 0x08000000 */
+#define HCCHAR_DAD_6                     (0x40UL << HCCHAR_DAD_Pos)               // 0x10000000 */
 #define HCCHAR_ODDFRM_Pos                (29U)
-#define HCCHAR_ODDFRM_Msk                (0x1UL << HCCHAR_ODDFRM_Pos)             /*!< 0x20000000 */
-#define HCCHAR_ODDFRM                    HCCHAR_ODDFRM_Msk                        /*!< Odd frame */
+#define HCCHAR_ODDFRM_Msk                (0x1UL << HCCHAR_ODDFRM_Pos)             // 0x20000000 */
+#define HCCHAR_ODDFRM                    HCCHAR_ODDFRM_Msk                        // Odd frame */
 #define HCCHAR_CHDIS_Pos                 (30U)
-#define HCCHAR_CHDIS_Msk                 (0x1UL << HCCHAR_CHDIS_Pos)              /*!< 0x40000000 */
-#define HCCHAR_CHDIS                     HCCHAR_CHDIS_Msk                         /*!< Channel disable */
+#define HCCHAR_CHDIS_Msk                 (0x1UL << HCCHAR_CHDIS_Pos)              // 0x40000000 */
+#define HCCHAR_CHDIS                     HCCHAR_CHDIS_Msk                         // Channel disable */
 #define HCCHAR_CHENA_Pos                 (31U)
-#define HCCHAR_CHENA_Msk                 (0x1UL << HCCHAR_CHENA_Pos)              /*!< 0x80000000 */
-#define HCCHAR_CHENA                     HCCHAR_CHENA_Msk                         /*!< Channel enable */
+#define HCCHAR_CHENA_Msk                 (0x1UL << HCCHAR_CHENA_Pos)              // 0x80000000 */
+#define HCCHAR_CHENA                     HCCHAR_CHENA_Msk                         // Channel enable */
 
 /********************  Bit definition for HCSPLT register  ********************/
 
 #define HCSPLT_PRTADDR_Pos               (0U)
-#define HCSPLT_PRTADDR_Msk               (0x7FUL << HCSPLT_PRTADDR_Pos)           /*!< 0x0000007F */
-#define HCSPLT_PRTADDR                   HCSPLT_PRTADDR_Msk                       /*!< Port address */
-#define HCSPLT_PRTADDR_0                 (0x01UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000001 */
-#define HCSPLT_PRTADDR_1                 (0x02UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000002 */
-#define HCSPLT_PRTADDR_2                 (0x04UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000004 */
-#define HCSPLT_PRTADDR_3                 (0x08UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000008 */
-#define HCSPLT_PRTADDR_4                 (0x10UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000010 */
-#define HCSPLT_PRTADDR_5                 (0x20UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000020 */
-#define HCSPLT_PRTADDR_6                 (0x40UL << HCSPLT_PRTADDR_Pos)           /*!< 0x00000040 */
+#define HCSPLT_PRTADDR_Msk               (0x7FUL << HCSPLT_PRTADDR_Pos)           // 0x0000007F */
+#define HCSPLT_PRTADDR                   HCSPLT_PRTADDR_Msk                       // Port address */
+#define HCSPLT_PRTADDR_0                 (0x01UL << HCSPLT_PRTADDR_Pos)           // 0x00000001 */
+#define HCSPLT_PRTADDR_1                 (0x02UL << HCSPLT_PRTADDR_Pos)           // 0x00000002 */
+#define HCSPLT_PRTADDR_2                 (0x04UL << HCSPLT_PRTADDR_Pos)           // 0x00000004 */
+#define HCSPLT_PRTADDR_3                 (0x08UL << HCSPLT_PRTADDR_Pos)           // 0x00000008 */
+#define HCSPLT_PRTADDR_4                 (0x10UL << HCSPLT_PRTADDR_Pos)           // 0x00000010 */
+#define HCSPLT_PRTADDR_5                 (0x20UL << HCSPLT_PRTADDR_Pos)           // 0x00000020 */
+#define HCSPLT_PRTADDR_6                 (0x40UL << HCSPLT_PRTADDR_Pos)           // 0x00000040 */
 
 #define HCSPLT_HUBADDR_Pos               (7U)
-#define HCSPLT_HUBADDR_Msk               (0x7FUL << HCSPLT_HUBADDR_Pos)           /*!< 0x00003F80 */
-#define HCSPLT_HUBADDR                   HCSPLT_HUBADDR_Msk                       /*!< Hub address */
-#define HCSPLT_HUBADDR_0                 (0x01UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00000080 */
-#define HCSPLT_HUBADDR_1                 (0x02UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00000100 */
-#define HCSPLT_HUBADDR_2                 (0x04UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00000200 */
-#define HCSPLT_HUBADDR_3                 (0x08UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00000400 */
-#define HCSPLT_HUBADDR_4                 (0x10UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00000800 */
-#define HCSPLT_HUBADDR_5                 (0x20UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00001000 */
-#define HCSPLT_HUBADDR_6                 (0x40UL << HCSPLT_HUBADDR_Pos)           /*!< 0x00002000 */
+#define HCSPLT_HUBADDR_Msk               (0x7FUL << HCSPLT_HUBADDR_Pos)           // 0x00003F80 */
+#define HCSPLT_HUBADDR                   HCSPLT_HUBADDR_Msk                       // Hub address */
+#define HCSPLT_HUBADDR_0                 (0x01UL << HCSPLT_HUBADDR_Pos)           // 0x00000080 */
+#define HCSPLT_HUBADDR_1                 (0x02UL << HCSPLT_HUBADDR_Pos)           // 0x00000100 */
+#define HCSPLT_HUBADDR_2                 (0x04UL << HCSPLT_HUBADDR_Pos)           // 0x00000200 */
+#define HCSPLT_HUBADDR_3                 (0x08UL << HCSPLT_HUBADDR_Pos)           // 0x00000400 */
+#define HCSPLT_HUBADDR_4                 (0x10UL << HCSPLT_HUBADDR_Pos)           // 0x00000800 */
+#define HCSPLT_HUBADDR_5                 (0x20UL << HCSPLT_HUBADDR_Pos)           // 0x00001000 */
+#define HCSPLT_HUBADDR_6                 (0x40UL << HCSPLT_HUBADDR_Pos)           // 0x00002000 */
 
 #define HCSPLT_XACTPOS_Pos               (14U)
-#define HCSPLT_XACTPOS_Msk               (0x3UL << HCSPLT_XACTPOS_Pos)            /*!< 0x0000C000 */
-#define HCSPLT_XACTPOS                   HCSPLT_XACTPOS_Msk                       /*!< XACTPOS */
-#define HCSPLT_XACTPOS_0                 (0x1UL << HCSPLT_XACTPOS_Pos)            /*!< 0x00004000 */
-#define HCSPLT_XACTPOS_1                 (0x2UL << HCSPLT_XACTPOS_Pos)            /*!< 0x00008000 */
+#define HCSPLT_XACTPOS_Msk               (0x3UL << HCSPLT_XACTPOS_Pos)            // 0x0000C000 */
+#define HCSPLT_XACTPOS                   HCSPLT_XACTPOS_Msk                       // XACTPOS */
+#define HCSPLT_XACTPOS_0                 (0x1UL << HCSPLT_XACTPOS_Pos)            // 0x00004000 */
+#define HCSPLT_XACTPOS_1                 (0x2UL << HCSPLT_XACTPOS_Pos)            // 0x00008000 */
 #define HCSPLT_COMPLSPLT_Pos             (16U)
-#define HCSPLT_COMPLSPLT_Msk             (0x1UL << HCSPLT_COMPLSPLT_Pos)          /*!< 0x00010000 */
-#define HCSPLT_COMPLSPLT                 HCSPLT_COMPLSPLT_Msk                     /*!< Do complete split */
+#define HCSPLT_COMPLSPLT_Msk             (0x1UL << HCSPLT_COMPLSPLT_Pos)          // 0x00010000 */
+#define HCSPLT_COMPLSPLT                 HCSPLT_COMPLSPLT_Msk                     // Do complete split */
 #define HCSPLT_SPLITEN_Pos               (31U)
-#define HCSPLT_SPLITEN_Msk               (0x1UL << HCSPLT_SPLITEN_Pos)            /*!< 0x80000000 */
-#define HCSPLT_SPLITEN                   HCSPLT_SPLITEN_Msk                       /*!< Split enable */
+#define HCSPLT_SPLITEN_Msk               (0x1UL << HCSPLT_SPLITEN_Pos)            // 0x80000000 */
+#define HCSPLT_SPLITEN                   HCSPLT_SPLITEN_Msk                       // Split enable */
 
 /********************  Bit definition for HCINT register  ********************/
 #define HCINT_XFRC_Pos                   (0U)
-#define HCINT_XFRC_Msk                   (0x1UL << HCINT_XFRC_Pos)                /*!< 0x00000001 */
-#define HCINT_XFRC                       HCINT_XFRC_Msk                           /*!< Transfer completed */
+#define HCINT_XFRC_Msk                   (0x1UL << HCINT_XFRC_Pos)                // 0x00000001 */
+#define HCINT_XFRC                       HCINT_XFRC_Msk                           // Transfer completed */
 #define HCINT_CHH_Pos                    (1U)
-#define HCINT_CHH_Msk                    (0x1UL << HCINT_CHH_Pos)                 /*!< 0x00000002 */
-#define HCINT_CHH                        HCINT_CHH_Msk                            /*!< Channel halted */
+#define HCINT_CHH_Msk                    (0x1UL << HCINT_CHH_Pos)                 // 0x00000002 */
+#define HCINT_CHH                        HCINT_CHH_Msk                            // Channel halted */
 #define HCINT_AHBERR_Pos                 (2U)
-#define HCINT_AHBERR_Msk                 (0x1UL << HCINT_AHBERR_Pos)              /*!< 0x00000004 */
-#define HCINT_AHBERR                     HCINT_AHBERR_Msk                         /*!< AHB error */
+#define HCINT_AHBERR_Msk                 (0x1UL << HCINT_AHBERR_Pos)              // 0x00000004 */
+#define HCINT_AHBERR                     HCINT_AHBERR_Msk                         // AHB error */
 #define HCINT_STALL_Pos                  (3U)
-#define HCINT_STALL_Msk                  (0x1UL << HCINT_STALL_Pos)               /*!< 0x00000008 */
-#define HCINT_STALL                      HCINT_STALL_Msk                          /*!< STALL response received interrupt */
+#define HCINT_STALL_Msk                  (0x1UL << HCINT_STALL_Pos)               // 0x00000008 */
+#define HCINT_STALL                      HCINT_STALL_Msk                          // STALL response received interrupt */
 #define HCINT_NAK_Pos                    (4U)
-#define HCINT_NAK_Msk                    (0x1UL << HCINT_NAK_Pos)                 /*!< 0x00000010 */
-#define HCINT_NAK                        HCINT_NAK_Msk                            /*!< NAK response received interrupt */
+#define HCINT_NAK_Msk                    (0x1UL << HCINT_NAK_Pos)                 // 0x00000010 */
+#define HCINT_NAK                        HCINT_NAK_Msk                            // NAK response received interrupt */
 #define HCINT_ACK_Pos                    (5U)
-#define HCINT_ACK_Msk                    (0x1UL << HCINT_ACK_Pos)                 /*!< 0x00000020 */
-#define HCINT_ACK                        HCINT_ACK_Msk                            /*!< ACK response received/transmitted interrupt */
+#define HCINT_ACK_Msk                    (0x1UL << HCINT_ACK_Pos)                 // 0x00000020 */
+#define HCINT_ACK                        HCINT_ACK_Msk                            // ACK response received/transmitted interrupt */
 #define HCINT_NYET_Pos                   (6U)
-#define HCINT_NYET_Msk                   (0x1UL << HCINT_NYET_Pos)                /*!< 0x00000040 */
-#define HCINT_NYET                       HCINT_NYET_Msk                           /*!< Response received interrupt */
+#define HCINT_NYET_Msk                   (0x1UL << HCINT_NYET_Pos)                // 0x00000040 */
+#define HCINT_NYET                       HCINT_NYET_Msk                           // Response received interrupt */
 #define HCINT_TXERR_Pos                  (7U)
-#define HCINT_TXERR_Msk                  (0x1UL << HCINT_TXERR_Pos)               /*!< 0x00000080 */
-#define HCINT_TXERR                      HCINT_TXERR_Msk                          /*!< Transaction error */
+#define HCINT_TXERR_Msk                  (0x1UL << HCINT_TXERR_Pos)               // 0x00000080 */
+#define HCINT_TXERR                      HCINT_TXERR_Msk                          // Transaction error */
 #define HCINT_BBERR_Pos                  (8U)
-#define HCINT_BBERR_Msk                  (0x1UL << HCINT_BBERR_Pos)               /*!< 0x00000100 */
-#define HCINT_BBERR                      HCINT_BBERR_Msk                          /*!< Babble error */
+#define HCINT_BBERR_Msk                  (0x1UL << HCINT_BBERR_Pos)               // 0x00000100 */
+#define HCINT_BBERR                      HCINT_BBERR_Msk                          // Babble error */
 #define HCINT_FRMOR_Pos                  (9U)
-#define HCINT_FRMOR_Msk                  (0x1UL << HCINT_FRMOR_Pos)               /*!< 0x00000200 */
-#define HCINT_FRMOR                      HCINT_FRMOR_Msk                          /*!< Frame overrun */
+#define HCINT_FRMOR_Msk                  (0x1UL << HCINT_FRMOR_Pos)               // 0x00000200 */
+#define HCINT_FRMOR                      HCINT_FRMOR_Msk                          // Frame overrun */
 #define HCINT_DTERR_Pos                  (10U)
-#define HCINT_DTERR_Msk                  (0x1UL << HCINT_DTERR_Pos)               /*!< 0x00000400 */
-#define HCINT_DTERR                      HCINT_DTERR_Msk                          /*!< Data toggle error */
+#define HCINT_DTERR_Msk                  (0x1UL << HCINT_DTERR_Pos)               // 0x00000400 */
+#define HCINT_DTERR                      HCINT_DTERR_Msk                          // Data toggle error */
 
 /********************  Bit definition for DIEPINT register  ********************/
 #define DIEPINT_XFRC_Pos                 (0U)
-#define DIEPINT_XFRC_Msk                 (0x1UL << DIEPINT_XFRC_Pos)              /*!< 0x00000001 */
-#define DIEPINT_XFRC                     DIEPINT_XFRC_Msk                         /*!< Transfer completed interrupt */
+#define DIEPINT_XFRC_Msk                 (0x1UL << DIEPINT_XFRC_Pos)              // 0x00000001 */
+#define DIEPINT_XFRC                     DIEPINT_XFRC_Msk                         // Transfer completed interrupt */
 #define DIEPINT_EPDISD_Pos               (1U)
-#define DIEPINT_EPDISD_Msk               (0x1UL << DIEPINT_EPDISD_Pos)            /*!< 0x00000002 */
-#define DIEPINT_EPDISD                   DIEPINT_EPDISD_Msk                       /*!< Endpoint disabled interrupt */
+#define DIEPINT_EPDISD_Msk               (0x1UL << DIEPINT_EPDISD_Pos)            // 0x00000002 */
+#define DIEPINT_EPDISD                   DIEPINT_EPDISD_Msk                       // Endpoint disabled interrupt */
 #define DIEPINT_AHBERR_Pos               (2U)
-#define DIEPINT_AHBERR_Msk               (0x1UL << DIEPINT_AHBERR_Pos)            /*!< 0x00000004 */
-#define DIEPINT_AHBERR                   DIEPINT_AHBERR_Msk                       /*!< AHB Error (AHBErr) during an IN transaction */
+#define DIEPINT_AHBERR_Msk               (0x1UL << DIEPINT_AHBERR_Pos)            // 0x00000004 */
+#define DIEPINT_AHBERR                   DIEPINT_AHBERR_Msk                       // AHB Error (AHBErr) during an IN transaction */
 #define DIEPINT_TOC_Pos                  (3U)
-#define DIEPINT_TOC_Msk                  (0x1UL << DIEPINT_TOC_Pos)               /*!< 0x00000008 */
-#define DIEPINT_TOC                      DIEPINT_TOC_Msk                          /*!< Timeout condition */
+#define DIEPINT_TOC_Msk                  (0x1UL << DIEPINT_TOC_Pos)               // 0x00000008 */
+#define DIEPINT_TOC                      DIEPINT_TOC_Msk                          // Timeout condition */
 #define DIEPINT_ITTXFE_Pos               (4U)
-#define DIEPINT_ITTXFE_Msk               (0x1UL << DIEPINT_ITTXFE_Pos)            /*!< 0x00000010 */
-#define DIEPINT_ITTXFE                   DIEPINT_ITTXFE_Msk                       /*!< IN token received when TxFIFO is empty */
+#define DIEPINT_ITTXFE_Msk               (0x1UL << DIEPINT_ITTXFE_Pos)            // 0x00000010 */
+#define DIEPINT_ITTXFE                   DIEPINT_ITTXFE_Msk                       // IN token received when TxFIFO is empty */
 #define DIEPINT_INEPNM_Pos               (5U)
-#define DIEPINT_INEPNM_Msk               (0x1UL << DIEPINT_INEPNM_Pos)            /*!< 0x00000020 */
-#define DIEPINT_INEPNM                   DIEPINT_INEPNM_Msk                       /*!< IN token received with EP mismatch */
+#define DIEPINT_INEPNM_Msk               (0x1UL << DIEPINT_INEPNM_Pos)            // 0x00000020 */
+#define DIEPINT_INEPNM                   DIEPINT_INEPNM_Msk                       // IN token received with EP mismatch */
 #define DIEPINT_INEPNE_Pos               (6U)
-#define DIEPINT_INEPNE_Msk               (0x1UL << DIEPINT_INEPNE_Pos)            /*!< 0x00000040 */
-#define DIEPINT_INEPNE                   DIEPINT_INEPNE_Msk                       /*!< IN endpoint NAK effective */
+#define DIEPINT_INEPNE_Msk               (0x1UL << DIEPINT_INEPNE_Pos)            // 0x00000040 */
+#define DIEPINT_INEPNE                   DIEPINT_INEPNE_Msk                       // IN endpoint NAK effective */
 #define DIEPINT_TXFE_Pos                 (7U)
-#define DIEPINT_TXFE_Msk                 (0x1UL << DIEPINT_TXFE_Pos)              /*!< 0x00000080 */
-#define DIEPINT_TXFE                     DIEPINT_TXFE_Msk                         /*!< Transmit FIFO empty */
+#define DIEPINT_TXFE_Msk                 (0x1UL << DIEPINT_TXFE_Pos)              // 0x00000080 */
+#define DIEPINT_TXFE                     DIEPINT_TXFE_Msk                         // Transmit FIFO empty */
 #define DIEPINT_TXFIFOUDRN_Pos           (8U)
-#define DIEPINT_TXFIFOUDRN_Msk           (0x1UL << DIEPINT_TXFIFOUDRN_Pos)        /*!< 0x00000100 */
-#define DIEPINT_TXFIFOUDRN               DIEPINT_TXFIFOUDRN_Msk                   /*!< Transmit Fifo Underrun */
+#define DIEPINT_TXFIFOUDRN_Msk           (0x1UL << DIEPINT_TXFIFOUDRN_Pos)        // 0x00000100 */
+#define DIEPINT_TXFIFOUDRN               DIEPINT_TXFIFOUDRN_Msk                   // Transmit Fifo Underrun */
 #define DIEPINT_BNA_Pos                  (9U)
-#define DIEPINT_BNA_Msk                  (0x1UL << DIEPINT_BNA_Pos)               /*!< 0x00000200 */
-#define DIEPINT_BNA                      DIEPINT_BNA_Msk                          /*!< Buffer not available interrupt */
+#define DIEPINT_BNA_Msk                  (0x1UL << DIEPINT_BNA_Pos)               // 0x00000200 */
+#define DIEPINT_BNA                      DIEPINT_BNA_Msk                          // Buffer not available interrupt */
 #define DIEPINT_PKTDRPSTS_Pos            (11U)
-#define DIEPINT_PKTDRPSTS_Msk            (0x1UL << DIEPINT_PKTDRPSTS_Pos)         /*!< 0x00000800 */
-#define DIEPINT_PKTDRPSTS                DIEPINT_PKTDRPSTS_Msk                    /*!< Packet dropped status */
+#define DIEPINT_PKTDRPSTS_Msk            (0x1UL << DIEPINT_PKTDRPSTS_Pos)         // 0x00000800 */
+#define DIEPINT_PKTDRPSTS                DIEPINT_PKTDRPSTS_Msk                    // Packet dropped status */
 #define DIEPINT_BERR_Pos                 (12U)
-#define DIEPINT_BERR_Msk                 (0x1UL << DIEPINT_BERR_Pos)              /*!< 0x00001000 */
-#define DIEPINT_BERR                     DIEPINT_BERR_Msk                         /*!< Babble error interrupt */
+#define DIEPINT_BERR_Msk                 (0x1UL << DIEPINT_BERR_Pos)              // 0x00001000 */
+#define DIEPINT_BERR                     DIEPINT_BERR_Msk                         // Babble error interrupt */
 #define DIEPINT_NAK_Pos                  (13U)
-#define DIEPINT_NAK_Msk                  (0x1UL << DIEPINT_NAK_Pos)               /*!< 0x00002000 */
-#define DIEPINT_NAK                      DIEPINT_NAK_Msk                          /*!< NAK interrupt */
+#define DIEPINT_NAK_Msk                  (0x1UL << DIEPINT_NAK_Pos)               // 0x00002000 */
+#define DIEPINT_NAK                      DIEPINT_NAK_Msk                          // NAK interrupt */
 
 /********************  Bit definition for HCINTMSK register  ********************/
 #define HCINTMSK_XFRCM_Pos               (0U)
-#define HCINTMSK_XFRCM_Msk               (0x1UL << HCINTMSK_XFRCM_Pos)            /*!< 0x00000001 */
-#define HCINTMSK_XFRCM                   HCINTMSK_XFRCM_Msk                       /*!< Transfer completed mask */
+#define HCINTMSK_XFRCM_Msk               (0x1UL << HCINTMSK_XFRCM_Pos)            // 0x00000001 */
+#define HCINTMSK_XFRCM                   HCINTMSK_XFRCM_Msk                       // Transfer completed mask */
 #define HCINTMSK_CHHM_Pos                (1U)
-#define HCINTMSK_CHHM_Msk                (0x1UL << HCINTMSK_CHHM_Pos)             /*!< 0x00000002 */
-#define HCINTMSK_CHHM                    HCINTMSK_CHHM_Msk                        /*!< Channel halted mask */
+#define HCINTMSK_CHHM_Msk                (0x1UL << HCINTMSK_CHHM_Pos)             // 0x00000002 */
+#define HCINTMSK_CHHM                    HCINTMSK_CHHM_Msk                        // Channel halted mask */
 #define HCINTMSK_AHBERR_Pos              (2U)
-#define HCINTMSK_AHBERR_Msk              (0x1UL << HCINTMSK_AHBERR_Pos)           /*!< 0x00000004 */
-#define HCINTMSK_AHBERR                  HCINTMSK_AHBERR_Msk                      /*!< AHB error */
+#define HCINTMSK_AHBERR_Msk              (0x1UL << HCINTMSK_AHBERR_Pos)           // 0x00000004 */
+#define HCINTMSK_AHBERR                  HCINTMSK_AHBERR_Msk                      // AHB error */
 #define HCINTMSK_STALLM_Pos              (3U)
-#define HCINTMSK_STALLM_Msk              (0x1UL << HCINTMSK_STALLM_Pos)           /*!< 0x00000008 */
-#define HCINTMSK_STALLM                  HCINTMSK_STALLM_Msk                      /*!< STALL response received interrupt mask */
+#define HCINTMSK_STALLM_Msk              (0x1UL << HCINTMSK_STALLM_Pos)           // 0x00000008 */
+#define HCINTMSK_STALLM                  HCINTMSK_STALLM_Msk                      // STALL response received interrupt mask */
 #define HCINTMSK_NAKM_Pos                (4U)
-#define HCINTMSK_NAKM_Msk                (0x1UL << HCINTMSK_NAKM_Pos)             /*!< 0x00000010 */
-#define HCINTMSK_NAKM                    HCINTMSK_NAKM_Msk                        /*!< NAK response received interrupt mask */
+#define HCINTMSK_NAKM_Msk                (0x1UL << HCINTMSK_NAKM_Pos)             // 0x00000010 */
+#define HCINTMSK_NAKM                    HCINTMSK_NAKM_Msk                        // NAK response received interrupt mask */
 #define HCINTMSK_ACKM_Pos                (5U)
-#define HCINTMSK_ACKM_Msk                (0x1UL << HCINTMSK_ACKM_Pos)             /*!< 0x00000020 */
-#define HCINTMSK_ACKM                    HCINTMSK_ACKM_Msk                        /*!< ACK response received/transmitted interrupt mask */
+#define HCINTMSK_ACKM_Msk                (0x1UL << HCINTMSK_ACKM_Pos)             // 0x00000020 */
+#define HCINTMSK_ACKM                    HCINTMSK_ACKM_Msk                        // ACK response received/transmitted interrupt mask */
 #define HCINTMSK_NYET_Pos                (6U)
-#define HCINTMSK_NYET_Msk                (0x1UL << HCINTMSK_NYET_Pos)             /*!< 0x00000040 */
-#define HCINTMSK_NYET                    HCINTMSK_NYET_Msk                        /*!< response received interrupt mask */
+#define HCINTMSK_NYET_Msk                (0x1UL << HCINTMSK_NYET_Pos)             // 0x00000040 */
+#define HCINTMSK_NYET                    HCINTMSK_NYET_Msk                        // response received interrupt mask */
 #define HCINTMSK_TXERRM_Pos              (7U)
-#define HCINTMSK_TXERRM_Msk              (0x1UL << HCINTMSK_TXERRM_Pos)           /*!< 0x00000080 */
-#define HCINTMSK_TXERRM                  HCINTMSK_TXERRM_Msk                      /*!< Transaction error mask */
+#define HCINTMSK_TXERRM_Msk              (0x1UL << HCINTMSK_TXERRM_Pos)           // 0x00000080 */
+#define HCINTMSK_TXERRM                  HCINTMSK_TXERRM_Msk                      // Transaction error mask */
 #define HCINTMSK_BBERRM_Pos              (8U)
-#define HCINTMSK_BBERRM_Msk              (0x1UL << HCINTMSK_BBERRM_Pos)           /*!< 0x00000100 */
-#define HCINTMSK_BBERRM                  HCINTMSK_BBERRM_Msk                      /*!< Babble error mask */
+#define HCINTMSK_BBERRM_Msk              (0x1UL << HCINTMSK_BBERRM_Pos)           // 0x00000100 */
+#define HCINTMSK_BBERRM                  HCINTMSK_BBERRM_Msk                      // Babble error mask */
 #define HCINTMSK_FRMORM_Pos              (9U)
-#define HCINTMSK_FRMORM_Msk              (0x1UL << HCINTMSK_FRMORM_Pos)           /*!< 0x00000200 */
-#define HCINTMSK_FRMORM                  HCINTMSK_FRMORM_Msk                      /*!< Frame overrun mask */
+#define HCINTMSK_FRMORM_Msk              (0x1UL << HCINTMSK_FRMORM_Pos)           // 0x00000200 */
+#define HCINTMSK_FRMORM                  HCINTMSK_FRMORM_Msk                      // Frame overrun mask */
 #define HCINTMSK_DTERRM_Pos              (10U)
-#define HCINTMSK_DTERRM_Msk              (0x1UL << HCINTMSK_DTERRM_Pos)           /*!< 0x00000400 */
-#define HCINTMSK_DTERRM                  HCINTMSK_DTERRM_Msk                      /*!< Data toggle error mask */
+#define HCINTMSK_DTERRM_Msk              (0x1UL << HCINTMSK_DTERRM_Pos)           // 0x00000400 */
+#define HCINTMSK_DTERRM                  HCINTMSK_DTERRM_Msk                      // Data toggle error mask */
 
 /********************  Bit definition for DIEPTSIZ register  ********************/
 
 #define DIEPTSIZ_XFRSIZ_Pos              (0U)
-#define DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos)       /*!< 0x0007FFFF */
-#define DIEPTSIZ_XFRSIZ                  DIEPTSIZ_XFRSIZ_Msk                      /*!< Transfer size */
+#define DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DIEPTSIZ_XFRSIZ_Pos)       // 0x0007FFFF */
+#define DIEPTSIZ_XFRSIZ                  DIEPTSIZ_XFRSIZ_Msk                      // Transfer size */
 #define DIEPTSIZ_PKTCNT_Pos              (19U)
-#define DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << DIEPTSIZ_PKTCNT_Pos)         /*!< 0x1FF80000 */
-#define DIEPTSIZ_PKTCNT                  DIEPTSIZ_PKTCNT_Msk                      /*!< Packet count */
+#define DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << DIEPTSIZ_PKTCNT_Pos)         // 0x1FF80000 */
+#define DIEPTSIZ_PKTCNT                  DIEPTSIZ_PKTCNT_Msk                      // Packet count */
 #define DIEPTSIZ_MULCNT_Pos              (29U)
-#define DIEPTSIZ_MULCNT_Msk              (0x3UL << DIEPTSIZ_MULCNT_Pos)           /*!< 0x60000000 */
-#define DIEPTSIZ_MULCNT                  DIEPTSIZ_MULCNT_Msk                      /*!< Packet count */
+#define DIEPTSIZ_MULCNT_Msk              (0x3UL << DIEPTSIZ_MULCNT_Pos)           // 0x60000000 */
+#define DIEPTSIZ_MULCNT                  DIEPTSIZ_MULCNT_Msk                      // Packet count */
                                                                                   /********************  Bit definition for HCTSIZ register  ********************/
 #define HCTSIZ_XFRSIZ_Pos                (0U)
-#define HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos)         /*!< 0x0007FFFF */
-#define HCTSIZ_XFRSIZ                    HCTSIZ_XFRSIZ_Msk                        /*!< Transfer size */
+#define HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos)         // 0x0007FFFF */
+#define HCTSIZ_XFRSIZ                    HCTSIZ_XFRSIZ_Msk                        // Transfer size */
 #define HCTSIZ_PKTCNT_Pos                (19U)
-#define HCTSIZ_PKTCNT_Msk                (0x3FFUL << HCTSIZ_PKTCNT_Pos)           /*!< 0x1FF80000 */
-#define HCTSIZ_PKTCNT                    HCTSIZ_PKTCNT_Msk                        /*!< Packet count */
+#define HCTSIZ_PKTCNT_Msk                (0x3FFUL << HCTSIZ_PKTCNT_Pos)           // 0x1FF80000 */
+#define HCTSIZ_PKTCNT                    HCTSIZ_PKTCNT_Msk                        // Packet count */
 #define HCTSIZ_DOPING_Pos                (31U)
-#define HCTSIZ_DOPING_Msk                (0x1UL << HCTSIZ_DOPING_Pos)             /*!< 0x80000000 */
-#define HCTSIZ_DOPING                    HCTSIZ_DOPING_Msk                        /*!< Do PING */
+#define HCTSIZ_DOPING_Msk                (0x1UL << HCTSIZ_DOPING_Pos)             // 0x80000000 */
+#define HCTSIZ_DOPING                    HCTSIZ_DOPING_Msk                        // Do PING */
 #define HCTSIZ_DPID_Pos                  (29U)
-#define HCTSIZ_DPID_Msk                  (0x3UL << HCTSIZ_DPID_Pos)               /*!< 0x60000000 */
-#define HCTSIZ_DPID                      HCTSIZ_DPID_Msk                          /*!< Data PID */
-#define HCTSIZ_DPID_0                    (0x1UL << HCTSIZ_DPID_Pos)               /*!< 0x20000000 */
-#define HCTSIZ_DPID_1                    (0x2UL << HCTSIZ_DPID_Pos)               /*!< 0x40000000 */
+#define HCTSIZ_DPID_Msk                  (0x3UL << HCTSIZ_DPID_Pos)               // 0x60000000 */
+#define HCTSIZ_DPID                      HCTSIZ_DPID_Msk                          // Data PID */
+#define HCTSIZ_DPID_0                    (0x1UL << HCTSIZ_DPID_Pos)               // 0x20000000 */
+#define HCTSIZ_DPID_1                    (0x2UL << HCTSIZ_DPID_Pos)               // 0x40000000 */
 
 /********************  Bit definition for DIEPDMA register  ********************/
 #define DIEPDMA_DMAADDR_Pos              (0U)
-#define DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos)    /*!< 0xFFFFFFFF */
-#define DIEPDMA_DMAADDR                  DIEPDMA_DMAADDR_Msk                      /*!< DMA address */
+#define DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << DIEPDMA_DMAADDR_Pos)    // 0xFFFFFFFF */
+#define DIEPDMA_DMAADDR                  DIEPDMA_DMAADDR_Msk                      // DMA address */
 
 /********************  Bit definition for HCDMA register  ********************/
 #define HCDMA_DMAADDR_Pos                (0U)
-#define HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos)      /*!< 0xFFFFFFFF */
-#define HCDMA_DMAADDR                    HCDMA_DMAADDR_Msk                        /*!< DMA address */
+#define HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos)      // 0xFFFFFFFF */
+#define HCDMA_DMAADDR                    HCDMA_DMAADDR_Msk                        // DMA address */
 
                                                                                   /********************  Bit definition for DTXFSTS register  ********************/
 #define DTXFSTS_INEPTFSAV_Pos            (0U)
-#define DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos)      /*!< 0x0000FFFF */
-#define DTXFSTS_INEPTFSAV                DTXFSTS_INEPTFSAV_Msk                    /*!< IN endpoint TxFIFO space available */
+#define DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos)      // 0x0000FFFF */
+#define DTXFSTS_INEPTFSAV                DTXFSTS_INEPTFSAV_Msk                    // IN endpoint TxFIFO space available */
 
                                                                                   /********************  Bit definition for DIEPTXF register  ********************/
 #define DIEPTXF_INEPTXSA_Pos             (0U)
-#define DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << DIEPTXF_INEPTXSA_Pos)       /*!< 0x0000FFFF */
-#define DIEPTXF_INEPTXSA                 DIEPTXF_INEPTXSA_Msk                     /*!< IN endpoint FIFOx transmit RAM start address */
+#define DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << DIEPTXF_INEPTXSA_Pos)       // 0x0000FFFF */
+#define DIEPTXF_INEPTXSA                 DIEPTXF_INEPTXSA_Msk                     // IN endpoint FIFOx transmit RAM start address */
 #define DIEPTXF_INEPTXFD_Pos             (16U)
-#define DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << DIEPTXF_INEPTXFD_Pos)       /*!< 0xFFFF0000 */
-#define DIEPTXF_INEPTXFD                 DIEPTXF_INEPTXFD_Msk                     /*!< IN endpoint TxFIFO depth */
+#define DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << DIEPTXF_INEPTXFD_Pos)       // 0xFFFF0000 */
+#define DIEPTXF_INEPTXFD                 DIEPTXF_INEPTXFD_Msk                     // IN endpoint TxFIFO depth */
 
 /********************  Bit definition for DOEPCTL register  ********************/
 #define DOEPCTL_MPSIZ_Pos                (0U)
-#define DOEPCTL_MPSIZ_Msk                (0x7FFUL << DOEPCTL_MPSIZ_Pos)           /*!< 0x000007FF */
-#define DOEPCTL_MPSIZ                    DOEPCTL_MPSIZ_Msk                        /*!< Maximum packet size */          /*!<Bit 1 */
+#define DOEPCTL_MPSIZ_Msk                (0x7FFUL << DOEPCTL_MPSIZ_Pos)           // 0x000007FF */
+#define DOEPCTL_MPSIZ                    DOEPCTL_MPSIZ_Msk                        // Maximum packet size */          //Bit 1 */
 #define DOEPCTL_USBAEP_Pos               (15U)
-#define DOEPCTL_USBAEP_Msk               (0x1UL << DOEPCTL_USBAEP_Pos)            /*!< 0x00008000 */
-#define DOEPCTL_USBAEP                   DOEPCTL_USBAEP_Msk                       /*!< USB active endpoint */
+#define DOEPCTL_USBAEP_Msk               (0x1UL << DOEPCTL_USBAEP_Pos)            // 0x00008000 */
+#define DOEPCTL_USBAEP                   DOEPCTL_USBAEP_Msk                       // USB active endpoint */
 #define DOEPCTL_NAKSTS_Pos               (17U)
-#define DOEPCTL_NAKSTS_Msk               (0x1UL << DOEPCTL_NAKSTS_Pos)            /*!< 0x00020000 */
-#define DOEPCTL_NAKSTS                   DOEPCTL_NAKSTS_Msk                       /*!< NAK status */
+#define DOEPCTL_NAKSTS_Msk               (0x1UL << DOEPCTL_NAKSTS_Pos)            // 0x00020000 */
+#define DOEPCTL_NAKSTS                   DOEPCTL_NAKSTS_Msk                       // NAK status */
 #define DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
-#define DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos)    /*!< 0x10000000 */
-#define DOEPCTL_SD0PID_SEVNFRM           DOEPCTL_SD0PID_SEVNFRM_Msk               /*!< Set DATA0 PID */
+#define DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << DOEPCTL_SD0PID_SEVNFRM_Pos)    // 0x10000000 */
+#define DOEPCTL_SD0PID_SEVNFRM           DOEPCTL_SD0PID_SEVNFRM_Msk               // Set DATA0 PID */
 #define DOEPCTL_SODDFRM_Pos              (29U)
-#define DOEPCTL_SODDFRM_Msk              (0x1UL << DOEPCTL_SODDFRM_Pos)           /*!< 0x20000000 */
-#define DOEPCTL_SODDFRM                  DOEPCTL_SODDFRM_Msk                      /*!< Set odd frame */
+#define DOEPCTL_SODDFRM_Msk              (0x1UL << DOEPCTL_SODDFRM_Pos)           // 0x20000000 */
+#define DOEPCTL_SODDFRM                  DOEPCTL_SODDFRM_Msk                      // Set odd frame */
 #define DOEPCTL_EPTYP_Pos                (18U)
-#define DOEPCTL_EPTYP_Msk                (0x3UL << DOEPCTL_EPTYP_Pos)             /*!< 0x000C0000 */
-#define DOEPCTL_EPTYP                    DOEPCTL_EPTYP_Msk                        /*!< Endpoint type */
-#define DOEPCTL_EPTYP_0                  (0x1UL << DOEPCTL_EPTYP_Pos)             /*!< 0x00040000 */
-#define DOEPCTL_EPTYP_1                  (0x2UL << DOEPCTL_EPTYP_Pos)             /*!< 0x00080000 */
+#define DOEPCTL_EPTYP_Msk                (0x3UL << DOEPCTL_EPTYP_Pos)             // 0x000C0000 */
+#define DOEPCTL_EPTYP                    DOEPCTL_EPTYP_Msk                        // Endpoint type */
+#define DOEPCTL_EPTYP_0                  (0x1UL << DOEPCTL_EPTYP_Pos)             // 0x00040000 */
+#define DOEPCTL_EPTYP_1                  (0x2UL << DOEPCTL_EPTYP_Pos)             // 0x00080000 */
 #define DOEPCTL_SNPM_Pos                 (20U)
-#define DOEPCTL_SNPM_Msk                 (0x1UL << DOEPCTL_SNPM_Pos)              /*!< 0x00100000 */
-#define DOEPCTL_SNPM                     DOEPCTL_SNPM_Msk                         /*!< Snoop mode */
+#define DOEPCTL_SNPM_Msk                 (0x1UL << DOEPCTL_SNPM_Pos)              // 0x00100000 */
+#define DOEPCTL_SNPM                     DOEPCTL_SNPM_Msk                         // Snoop mode */
 #define DOEPCTL_STALL_Pos                (21U)
-#define DOEPCTL_STALL_Msk                (0x1UL << DOEPCTL_STALL_Pos)             /*!< 0x00200000 */
-#define DOEPCTL_STALL                    DOEPCTL_STALL_Msk                        /*!< STALL handshake */
+#define DOEPCTL_STALL_Msk                (0x1UL << DOEPCTL_STALL_Pos)             // 0x00200000 */
+#define DOEPCTL_STALL                    DOEPCTL_STALL_Msk                        // STALL handshake */
 #define DOEPCTL_CNAK_Pos                 (26U)
-#define DOEPCTL_CNAK_Msk                 (0x1UL << DOEPCTL_CNAK_Pos)              /*!< 0x04000000 */
-#define DOEPCTL_CNAK                     DOEPCTL_CNAK_Msk                         /*!< Clear NAK */
+#define DOEPCTL_CNAK_Msk                 (0x1UL << DOEPCTL_CNAK_Pos)              // 0x04000000 */
+#define DOEPCTL_CNAK                     DOEPCTL_CNAK_Msk                         // Clear NAK */
 #define DOEPCTL_SNAK_Pos                 (27U)
-#define DOEPCTL_SNAK_Msk                 (0x1UL << DOEPCTL_SNAK_Pos)              /*!< 0x08000000 */
-#define DOEPCTL_SNAK                     DOEPCTL_SNAK_Msk                         /*!< Set NAK */
+#define DOEPCTL_SNAK_Msk                 (0x1UL << DOEPCTL_SNAK_Pos)              // 0x08000000 */
+#define DOEPCTL_SNAK                     DOEPCTL_SNAK_Msk                         // Set NAK */
 #define DOEPCTL_EPDIS_Pos                (30U)
-#define DOEPCTL_EPDIS_Msk                (0x1UL << DOEPCTL_EPDIS_Pos)             /*!< 0x40000000 */
-#define DOEPCTL_EPDIS                    DOEPCTL_EPDIS_Msk                        /*!< Endpoint disable */
+#define DOEPCTL_EPDIS_Msk                (0x1UL << DOEPCTL_EPDIS_Pos)             // 0x40000000 */
+#define DOEPCTL_EPDIS                    DOEPCTL_EPDIS_Msk                        // Endpoint disable */
 #define DOEPCTL_EPENA_Pos                (31U)
-#define DOEPCTL_EPENA_Msk                (0x1UL << DOEPCTL_EPENA_Pos)             /*!< 0x80000000 */
-#define DOEPCTL_EPENA                    DOEPCTL_EPENA_Msk                        /*!< Endpoint enable */
+#define DOEPCTL_EPENA_Msk                (0x1UL << DOEPCTL_EPENA_Pos)             // 0x80000000 */
+#define DOEPCTL_EPENA                    DOEPCTL_EPENA_Msk                        // Endpoint enable */
 
 /********************  Bit definition for DOEPINT register  ********************/
 #define DOEPINT_XFRC_Pos                 (0U)
-#define DOEPINT_XFRC_Msk                 (0x1UL << DOEPINT_XFRC_Pos)              /*!< 0x00000001 */
-#define DOEPINT_XFRC                     DOEPINT_XFRC_Msk                         /*!< Transfer completed interrupt */
+#define DOEPINT_XFRC_Msk                 (0x1UL << DOEPINT_XFRC_Pos)              // 0x00000001 */
+#define DOEPINT_XFRC                     DOEPINT_XFRC_Msk                         // Transfer completed interrupt */
 #define DOEPINT_EPDISD_Pos               (1U)
-#define DOEPINT_EPDISD_Msk               (0x1UL << DOEPINT_EPDISD_Pos)            /*!< 0x00000002 */
-#define DOEPINT_EPDISD                   DOEPINT_EPDISD_Msk                       /*!< Endpoint disabled interrupt */
+#define DOEPINT_EPDISD_Msk               (0x1UL << DOEPINT_EPDISD_Pos)            // 0x00000002 */
+#define DOEPINT_EPDISD                   DOEPINT_EPDISD_Msk                       // Endpoint disabled interrupt */
 #define DOEPINT_AHBERR_Pos               (2U)
-#define DOEPINT_AHBERR_Msk               (0x1UL << DOEPINT_AHBERR_Pos)            /*!< 0x00000004 */
-#define DOEPINT_AHBERR                   DOEPINT_AHBERR_Msk                       /*!< AHB Error (AHBErr) during an OUT transaction */
+#define DOEPINT_AHBERR_Msk               (0x1UL << DOEPINT_AHBERR_Pos)            // 0x00000004 */
+#define DOEPINT_AHBERR                   DOEPINT_AHBERR_Msk                       // AHB Error (AHBErr) during an OUT transaction */
 #define DOEPINT_STUP_Pos                 (3U)
-#define DOEPINT_STUP_Msk                 (0x1UL << DOEPINT_STUP_Pos)              /*!< 0x00000008 */
-#define DOEPINT_STUP                     DOEPINT_STUP_Msk                         /*!< SETUP phase done */
+#define DOEPINT_STUP_Msk                 (0x1UL << DOEPINT_STUP_Pos)              // 0x00000008 */
+#define DOEPINT_STUP                     DOEPINT_STUP_Msk                         // SETUP phase done */
 #define DOEPINT_OTEPDIS_Pos              (4U)
-#define DOEPINT_OTEPDIS_Msk              (0x1UL << DOEPINT_OTEPDIS_Pos)           /*!< 0x00000010 */
-#define DOEPINT_OTEPDIS                  DOEPINT_OTEPDIS_Msk                      /*!< OUT token received when endpoint disabled */
+#define DOEPINT_OTEPDIS_Msk              (0x1UL << DOEPINT_OTEPDIS_Pos)           // 0x00000010 */
+#define DOEPINT_OTEPDIS                  DOEPINT_OTEPDIS_Msk                      // OUT token received when endpoint disabled */
 #define DOEPINT_OTEPSPR_Pos              (5U)
-#define DOEPINT_OTEPSPR_Msk              (0x1UL << DOEPINT_OTEPSPR_Pos)           /*!< 0x00000020 */
-#define DOEPINT_OTEPSPR                  DOEPINT_OTEPSPR_Msk                      /*!< Status Phase Received For Control Write */
+#define DOEPINT_OTEPSPR_Msk              (0x1UL << DOEPINT_OTEPSPR_Pos)           // 0x00000020 */
+#define DOEPINT_OTEPSPR                  DOEPINT_OTEPSPR_Msk                      // Status Phase Received For Control Write */
 #define DOEPINT_B2BSTUP_Pos              (6U)
-#define DOEPINT_B2BSTUP_Msk              (0x1UL << DOEPINT_B2BSTUP_Pos)           /*!< 0x00000040 */
-#define DOEPINT_B2BSTUP                  DOEPINT_B2BSTUP_Msk                      /*!< Back-to-back SETUP packets received */
+#define DOEPINT_B2BSTUP_Msk              (0x1UL << DOEPINT_B2BSTUP_Pos)           // 0x00000040 */
+#define DOEPINT_B2BSTUP                  DOEPINT_B2BSTUP_Msk                      // Back-to-back SETUP packets received */
 #define DOEPINT_OUTPKTERR_Pos            (8U)
-#define DOEPINT_OUTPKTERR_Msk            (0x1UL << DOEPINT_OUTPKTERR_Pos)         /*!< 0x00000100 */
-#define DOEPINT_OUTPKTERR                DOEPINT_OUTPKTERR_Msk                    /*!< OUT packet error */
+#define DOEPINT_OUTPKTERR_Msk            (0x1UL << DOEPINT_OUTPKTERR_Pos)         // 0x00000100 */
+#define DOEPINT_OUTPKTERR                DOEPINT_OUTPKTERR_Msk                    // OUT packet error */
 #define DOEPINT_NAK_Pos                  (13U)
-#define DOEPINT_NAK_Msk                  (0x1UL << DOEPINT_NAK_Pos)               /*!< 0x00002000 */
-#define DOEPINT_NAK                      DOEPINT_NAK_Msk                          /*!< NAK Packet is transmitted by the device */
+#define DOEPINT_NAK_Msk                  (0x1UL << DOEPINT_NAK_Pos)               // 0x00002000 */
+#define DOEPINT_NAK                      DOEPINT_NAK_Msk                          // NAK Packet is transmitted by the device */
 #define DOEPINT_NYET_Pos                 (14U)
-#define DOEPINT_NYET_Msk                 (0x1UL << DOEPINT_NYET_Pos)              /*!< 0x00004000 */
-#define DOEPINT_NYET                     DOEPINT_NYET_Msk                         /*!< NYET interrupt */
+#define DOEPINT_NYET_Msk                 (0x1UL << DOEPINT_NYET_Pos)              // 0x00004000 */
+#define DOEPINT_NYET                     DOEPINT_NYET_Msk                         // NYET interrupt */
 #define DOEPINT_STPKTRX_Pos              (15U)
-#define DOEPINT_STPKTRX_Msk              (0x1UL << DOEPINT_STPKTRX_Pos)           /*!< 0x00008000 */
-#define DOEPINT_STPKTRX                  DOEPINT_STPKTRX_Msk                      /*!< Setup Packet Received */
+#define DOEPINT_STPKTRX_Msk              (0x1UL << DOEPINT_STPKTRX_Pos)           // 0x00008000 */
+#define DOEPINT_STPKTRX                  DOEPINT_STPKTRX_Msk                      // Setup Packet Received */
 
 /********************  Bit definition for DOEPTSIZ register  ********************/
 #define DOEPTSIZ_XFRSIZ_Pos              (0U)
-#define DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos)       /*!< 0x0007FFFF */
-#define DOEPTSIZ_XFRSIZ                  DOEPTSIZ_XFRSIZ_Msk                      /*!< Transfer size */
+#define DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << DOEPTSIZ_XFRSIZ_Pos)       // 0x0007FFFF */
+#define DOEPTSIZ_XFRSIZ                  DOEPTSIZ_XFRSIZ_Msk                      // Transfer size */
 #define DOEPTSIZ_PKTCNT_Pos              (19U)
-#define DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << DOEPTSIZ_PKTCNT_Pos)         /*!< 0x1FF80000 */
-#define DOEPTSIZ_PKTCNT                  DOEPTSIZ_PKTCNT_Msk                      /*!< Packet count */
+#define DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << DOEPTSIZ_PKTCNT_Pos)         // 0x1FF80000 */
+#define DOEPTSIZ_PKTCNT                  DOEPTSIZ_PKTCNT_Msk                      // Packet count */
 
 #define DOEPTSIZ_STUPCNT_Pos             (29U)
-#define DOEPTSIZ_STUPCNT_Msk             (0x3UL << DOEPTSIZ_STUPCNT_Pos)          /*!< 0x60000000 */
-#define DOEPTSIZ_STUPCNT                 DOEPTSIZ_STUPCNT_Msk                     /*!< SETUP packet count */
-#define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos)          /*!< 0x20000000 */
-#define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos)          /*!< 0x40000000 */
+#define DOEPTSIZ_STUPCNT_Msk             (0x3UL << DOEPTSIZ_STUPCNT_Pos)          // 0x60000000 */
+#define DOEPTSIZ_STUPCNT                 DOEPTSIZ_STUPCNT_Msk                     // SETUP packet count */
+#define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos)          // 0x20000000 */
+#define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos)          // 0x40000000 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
 #define PCGCCTL_STOPCLK_Pos              (0U)
-#define PCGCCTL_STOPCLK_Msk              (0x1UL << PCGCCTL_STOPCLK_Pos)           /*!< 0x00000001 */
-#define PCGCCTL_STOPCLK                  PCGCCTL_STOPCLK_Msk                      /*!< SETUP packet count */
+#define PCGCCTL_STOPCLK_Msk              (0x1UL << PCGCCTL_STOPCLK_Pos)           // 0x00000001 */
+#define PCGCCTL_STOPCLK                  PCGCCTL_STOPCLK_Msk                      // SETUP packet count */
 #define PCGCCTL_GATECLK_Pos              (1U)
-#define PCGCCTL_GATECLK_Msk              (0x1UL << PCGCCTL_GATECLK_Pos)           /*!< 0x00000002 */
-#define PCGCCTL_GATECLK                  PCGCCTL_GATECLK_Msk                      /*!<Bit 0 */
+#define PCGCCTL_GATECLK_Msk              (0x1UL << PCGCCTL_GATECLK_Pos)           // 0x00000002 */
+#define PCGCCTL_GATECLK                  PCGCCTL_GATECLK_Msk                      //Bit 0 */
 #define PCGCCTL_PHYSUSP_Pos              (4U)
-#define PCGCCTL_PHYSUSP_Msk              (0x1UL << PCGCCTL_PHYSUSP_Pos)           /*!< 0x00000010 */
-#define PCGCCTL_PHYSUSP                  PCGCCTL_PHYSUSP_Msk                      /*!<Bit 1 */
+#define PCGCCTL_PHYSUSP_Msk              (0x1UL << PCGCCTL_PHYSUSP_Pos)           // 0x00000010 */
+#define PCGCCTL_PHYSUSP                  PCGCCTL_PHYSUSP_Msk                      //Bit 1 */
 
 /********************  Bit definition for USBPHYC_PLL1 register  ********************/
 #define HS_PHYC_PLL1_PLLEN_Pos                (0U)
-#define HS_PHYC_PLL1_PLLEN_Msk                (0x1UL << HS_PHYC_PLL1_PLLEN_Pos)   /*!< 0x00000001 */
-#define HS_PHYC_PLL1_PLLEN                    HS_PHYC_PLL1_PLLEN_Msk              /*!< Enable PLL */
+#define HS_PHYC_PLL1_PLLEN_Msk                (0x1UL << HS_PHYC_PLL1_PLLEN_Pos)   // 0x00000001 */
+#define HS_PHYC_PLL1_PLLEN                    HS_PHYC_PLL1_PLLEN_Msk              // Enable PLL */
 #define HS_PHYC_PLL1_PLLSEL_Pos               (1U)
-#define HS_PHYC_PLL1_PLLSEL_Msk               (0x7UL << HS_PHYC_PLL1_PLLSEL_Pos)  /*!< 0x0000000E */
-#define HS_PHYC_PLL1_PLLSEL                   HS_PHYC_PLL1_PLLSEL_Msk             /*!< Controls PHY frequency operation selection */
-#define HS_PHYC_PLL1_PLLSEL_1                 (0x1UL << HS_PHYC_PLL1_PLLSEL_Pos)  /*!< 0x00000002 */
-#define HS_PHYC_PLL1_PLLSEL_2                 (0x2UL << HS_PHYC_PLL1_PLLSEL_Pos)  /*!< 0x00000004 */
-#define HS_PHYC_PLL1_PLLSEL_3                 (0x4UL << HS_PHYC_PLL1_PLLSEL_Pos)  /*!< 0x00000008 */
+#define HS_PHYC_PLL1_PLLSEL_Msk               (0x7UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x0000000E */
+#define HS_PHYC_PLL1_PLLSEL                   HS_PHYC_PLL1_PLLSEL_Msk             // Controls PHY frequency operation selection */
+#define HS_PHYC_PLL1_PLLSEL_1                 (0x1UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x00000002 */
+#define HS_PHYC_PLL1_PLLSEL_2                 (0x2UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x00000004 */
+#define HS_PHYC_PLL1_PLLSEL_3                 (0x4UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x00000008 */
 
-#define HS_PHYC_PLL1_PLLSEL_12MHZ             0x00000000U                                                       /*!< PHY PLL1 input clock frequency 12 MHz   */
-#define HS_PHYC_PLL1_PLLSEL_12_5MHZ           HS_PHYC_PLL1_PLLSEL_1                                         /*!< PHY PLL1 input clock frequency 12.5 MHz */
-#define HS_PHYC_PLL1_PLLSEL_16MHZ             (uint32_t)(HS_PHYC_PLL1_PLLSEL_1 | HS_PHYC_PLL1_PLLSEL_2) /*!< PHY PLL1 input clock frequency 16 MHz   */
-#define HS_PHYC_PLL1_PLLSEL_24MHZ             HS_PHYC_PLL1_PLLSEL_3                                         /*!< PHY PLL1 input clock frequency 24 MHz   */
-#define HS_PHYC_PLL1_PLLSEL_25MHZ             (uint32_t)(HS_PHYC_PLL1_PLLSEL_2 | HS_PHYC_PLL1_PLLSEL_3) /*!< PHY PLL1 input clock frequency 25 MHz   */
+#define HS_PHYC_PLL1_PLLSEL_12MHZ             0x00000000U                                                       // PHY PLL1 input clock frequency 12 MHz   */
+#define HS_PHYC_PLL1_PLLSEL_12_5MHZ           HS_PHYC_PLL1_PLLSEL_1                                         // PHY PLL1 input clock frequency 12.5 MHz */
+#define HS_PHYC_PLL1_PLLSEL_16MHZ             (uint32_t)(HS_PHYC_PLL1_PLLSEL_1 | HS_PHYC_PLL1_PLLSEL_2) // PHY PLL1 input clock frequency 16 MHz   */
+#define HS_PHYC_PLL1_PLLSEL_24MHZ             HS_PHYC_PLL1_PLLSEL_3                                         // PHY PLL1 input clock frequency 24 MHz   */
+#define HS_PHYC_PLL1_PLLSEL_25MHZ             (uint32_t)(HS_PHYC_PLL1_PLLSEL_2 | HS_PHYC_PLL1_PLLSEL_3) // PHY PLL1 input clock frequency 25 MHz   */
 
 /********************  Bit definition for USBPHYC_LDO register  ********************/
 #define HS_PHYC_LDO_USED_Pos                 (0U)
-#define HS_PHYC_LDO_USED_Msk                 (0x1UL << HS_PHYC_LDO_USED_Pos) /*!< 0x00000001 */
-#define HS_PHYC_LDO_USED                     HS_PHYC_LDO_USED_Msk      /*!< Monitors the usage status of the PHY's LDO   */
+#define HS_PHYC_LDO_USED_Msk                 (0x1UL << HS_PHYC_LDO_USED_Pos) // 0x00000001 */
+#define HS_PHYC_LDO_USED                     HS_PHYC_LDO_USED_Msk      // Monitors the usage status of the PHY's LDO   */
 #define HS_PHYC_LDO_STATUS_Pos               (1U)
-#define HS_PHYC_LDO_STATUS_Msk               (0x1UL << HS_PHYC_LDO_STATUS_Pos) /*!< 0x00000002 */
-#define HS_PHYC_LDO_STATUS                   HS_PHYC_LDO_STATUS_Msk    /*!< Monitors the status of the PHY's LDO.        */
+#define HS_PHYC_LDO_STATUS_Msk               (0x1UL << HS_PHYC_LDO_STATUS_Pos) // 0x00000002 */
+#define HS_PHYC_LDO_STATUS                   HS_PHYC_LDO_STATUS_Msk    // Monitors the status of the PHY's LDO.        */
 #define HS_PHYC_LDO_DISABLE_Pos              (2U)
-#define HS_PHYC_LDO_DISABLE_Msk              (0x1UL << HS_PHYC_LDO_DISABLE_Pos) /*!< 0x00000004 */
-#define HS_PHYC_LDO_DISABLE                  HS_PHYC_LDO_DISABLE_Msk    /*!< Controls disable of the High Speed PHY's LDO */
+#define HS_PHYC_LDO_DISABLE_Msk              (0x1UL << HS_PHYC_LDO_DISABLE_Pos) // 0x00000004 */
+#define HS_PHYC_LDO_DISABLE                  HS_PHYC_LDO_DISABLE_Msk    // Controls disable of the High Speed PHY's LDO */
 
 #define HS_PHYC_LDO_ENABLE_Pos               HS_PHYC_LDO_DISABLE_Pos
 #define HS_PHYC_LDO_ENABLE_Msk               HS_PHYC_LDO_DISABLE_Msk

From 8df078dc9e8939969a8b4adb136d4e7fde3e7449 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 11:11:46 +0700
Subject: [PATCH 0600/2085] more rename

---
 src/portable/synopsys/dwc2/dcd_dwc2.c   | 189 +++++++++++-------------
 src/portable/synopsys/dwc2/dwc2_esp32.h |   2 +-
 src/portable/synopsys/dwc2/dwc2_gd32.h  |   2 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h |   2 +-
 src/portable/synopsys/dwc2/dwc2_type.h  |   8 +-
 5 files changed, 97 insertions(+), 106 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index b98bd0055..c0bf655f4 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -51,8 +51,7 @@
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#define CORE_REG(_port)       ((dwc2_core_t*) DWC2_REG_BASE)
-#define DEVICE_REG(_port)     CORE_REG(_port) //((dwc2_core_t*) (DWC2_REG_BASE + DWC2_DEVICE_BASE))
+#define DWC2_REG(_port)       ((dwc2_regs_t*) DWC2_REG_BASE)
 #define EPIN_REG(_port)       ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
 #define EPOUT_REG(_port)      ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
 #define FIFO_BASE(_port, _x)  ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
@@ -98,7 +97,7 @@ static void update_grxfsiz(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_core_t * core = CORE_REG(rhport);
+  dwc2_regs_t * core = DWC2_REG(rhport);
 
   // Determine largest EP size for RX FIFO
   uint16_t max_epsize = 0;
@@ -116,8 +115,7 @@ static void bus_reset(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_core_t   * core   = CORE_REG(rhport);
-  dwc2_core_t * dev    = DEVICE_REG(rhport);
+  dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
@@ -125,7 +123,7 @@ static void bus_reset(uint8_t rhport)
   _out_ep_closed = false;
 
   // clear device address
-  dev->dcfg &= ~DCFG_DAD_Msk;
+  dwc2->dcfg &= ~DCFG_DAD_Msk;
 
   // 1. NAK for all OUT endpoints
   for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
@@ -133,9 +131,9 @@ static void bus_reset(uint8_t rhport)
   }
 
   // 2. Un-mask interrupt bits
-  dev->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
-  dev->doepmsk  = DOEPMSK_STUPM | DOEPMSK_XFRCM;
-  dev->diepmsk  = DIEPMSK_TOM | DIEPMSK_XFRCM;
+  dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
+  dwc2->doepmsk  = DOEPMSK_STUPM | DOEPMSK_XFRCM;
+  dwc2->diepmsk  = DIEPMSK_TOM | DIEPMSK_XFRCM;
 
   // "USB Data FIFOs" section in reference manual
   // Peripheral FIFO architecture
@@ -187,12 +185,12 @@ static void bus_reset(uint8_t rhport)
   //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
   //   overwrite this.
 
-  core->grxfsiz = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
+  dwc2->grxfsiz = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
 
   _allocated_fifo_words_tx = 16;
 
   // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  core->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+  dwc2->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
   in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
@@ -200,15 +198,15 @@ static void bus_reset(uint8_t rhport)
 
   out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos);
 
-  core->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
+  dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
 
 
 static tusb_speed_t get_speed(uint8_t rhport)
 {
   (void) rhport;
-  dwc2_core_t * dev = DEVICE_REG(rhport);
-  uint32_t const enum_spd = (dev->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos;
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  uint32_t const enum_spd = (dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos;
   return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
 }
 
@@ -225,11 +223,11 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
     bitvalue = DCD_FULL_SPEED;
   }
 
-  dwc2_core_t * dev = DEVICE_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
   // Clear and set speed bits
-  dev->dcfg &= ~(3 << DCFG_DSPD_Pos);
-  dev->dcfg |= (bitvalue << DCFG_DSPD_Pos);
+  dwc2->dcfg &= ~(3 << DCFG_DSPD_Pos);
+  dwc2->dcfg |= (bitvalue << DCFG_DSPD_Pos);
 }
 
 #if defined(USB_HS_PHYC)
@@ -277,7 +275,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 {
   (void) rhport;
 
-  dwc2_core_t * dev    = DEVICE_REG(rhport);
+  dwc2_regs_t * dwc2    = DWC2_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
@@ -301,12 +299,12 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
     if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
     {
       // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->dsts & (1u << DSTS_FNSOF_Pos));
+      uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
       in_ep[epnum].DIEPCTL |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
     }
     // Enable fifo empty interrupt only if there are something to put in the fifo.
     if(total_bytes != 0) {
-      dev->diepempmsk |= (1 << epnum);
+      dwc2->diepempmsk |= (1 << epnum);
     }
   } else {
     // A full OUT transfer (multiple packets, possibly) triggers XFRC.
@@ -318,7 +316,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
     if ((out_ep[epnum].DOEPCTL & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
     {
       // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->dsts & (1u << DSTS_FNSOF_Pos));
+      uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
       out_ep[epnum].DOEPCTL |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
     }
   }
@@ -331,7 +329,7 @@ void dcd_init (uint8_t rhport)
 {
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
-  dwc2_core_t * core = CORE_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
   // check GSNPSID
 
@@ -341,23 +339,23 @@ void dcd_init (uint8_t rhport)
     // On selected MCUs HS port1 can be used with external PHY via ULPI interface
 #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
     // deactivate internal PHY
-    core->gccfg &= ~GCCFG_PWRDWN;
+    dwc2->gccfg &= ~GCCFG_PWRDWN;
 
     // Init The UTMI Interface
-    core->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
+    dwc2->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
 
     // Select default internal VBUS Indicator and Drive for ULPI
-    core->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
+    dwc2->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
 #else
-    core->gusbcfg |= GUSBCFG_PHYSEL;
+    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
 #endif
 
 #if defined(USB_HS_PHYC)
     // Highspeed with embedded UTMI PHYC
 
     // Select UTMI Interface
-    core->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL;
-    core->gccfg |= GCCFG_PHYHSEN;
+    dwc2->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL;
+    dwc2->gccfg |= GCCFG_PHYHSEN;
 
     // Enables control of a High Speed USB PHY
     USB_HS_PHYCInit();
@@ -365,42 +363,40 @@ void dcd_init (uint8_t rhport)
   } else
   {
     // Enable internal PHY
-    core->gusbcfg |= GUSBCFG_PHYSEL;
+    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
   }
 
   // Reset core after selecting PHYst
   // Wait AHB IDLE, reset then wait until it is cleared
-  while ((core->grstctl & GRSTCTL_AHBIDL) == 0U) {}
-  core->grstctl |= GRSTCTL_CSRST;
-  while ((core->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
+  while ((dwc2->grstctl & GRSTCTL_AHBIDL) == 0U) {}
+  dwc2->grstctl |= GRSTCTL_CSRST;
+  while ((dwc2->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
 
   // Restart PHY clock
   *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0;
 
   // Clear all interrupts
-  core->gintsts |= core->gintsts;
+  dwc2->gintsts |= dwc2->gintsts;
 
   // Required as part of core initialization.
   // TODO: How should mode mismatch be handled? It will cause
   // the core to stop working/require reset.
-  core->gintmsk |= GINTMSK_OTGINT | GINTMSK_MMISM;
-
-  dwc2_core_t * dev = DEVICE_REG(rhport);
+  dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_MMISM;
 
   // If USB host misbehaves during status portion of control xfer
   // (non zero-length packet), send STALL back and discard.
-  dev->dcfg |= DCFG_NZLSOHSK;
+  dwc2->dcfg |= DCFG_NZLSOHSK;
 
   set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
 
   // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) core->gccfg |= GCCFG_PWRDWN;
+  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->gccfg |= GCCFG_PWRDWN;
 
-  core->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
+  dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
                    GINTMSK_WUIM   | GINTMSK_RXFLVLM;
 
   // Enable global interrupt
-  core->gahbcfg |= GAHBCFG_GINT;
+  dwc2->gahbcfg |= GAHBCFG_GINT;
 
   dcd_connect(rhport);
 }
@@ -417,8 +413,8 @@ void dcd_int_disable (uint8_t rhport)
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-  dwc2_core_t * dev = DEVICE_REG(rhport);
-  dev->dcfg = (dev->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2->dcfg = (dwc2->dcfg & ~DCFG_DAD_Msk) | (dev_addr << DCFG_DAD_Pos);
 
   // Response with status after changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
@@ -428,34 +424,33 @@ void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_core_t   * core = CORE_REG(rhport);
-  dwc2_core_t * dev  = DEVICE_REG(rhport);
+  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 
   // set remote wakeup
-  dev->dctl |= DCTL_RWUSIG;
+  dwc2->dctl |= DCTL_RWUSIG;
 
   // enable SOF to detect bus resume
-  core->gintsts = GINTSTS_SOF;
-  core->gintmsk |= GINTMSK_SOFM;
+  dwc2->gintsts = GINTSTS_SOF;
+  dwc2->gintmsk |= GINTMSK_SOFM;
 
   // Per specs: remote wakeup signal bit must be clear within 1-15ms
   dwc2_remote_wakeup_delay();
 
-  dev->dctl &= ~DCTL_RWUSIG;
+  dwc2->dctl &= ~DCTL_RWUSIG;
 }
 
 void dcd_connect(uint8_t rhport)
 {
   (void) rhport;
-  dwc2_core_t * dev = DEVICE_REG(rhport);
-  dev->dctl &= ~DCTL_SDIS;
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2->dctl &= ~DCTL_SDIS;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
   (void) rhport;
-  dwc2_core_t * dev = DEVICE_REG(rhport);
-  dev->dctl |= DCTL_SDIS;
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2->dctl |= DCTL_SDIS;
 }
 
 
@@ -467,8 +462,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
   (void) rhport;
 
-  dwc2_core_t   * core   = CORE_REG(rhport);
-  dwc2_core_t * dev    = DEVICE_REG(rhport);
+  dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
@@ -489,12 +483,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     uint16_t const sz = calc_rx_ff_size(4*fifo_size);
 
     // If size_rx needs to be extended check if possible and if so enlarge it
-    if (core->grxfsiz < sz)
+    if (dwc2->grxfsiz < sz)
     {
       TU_ASSERT(sz + _allocated_fifo_words_tx <= DWC2_EP_FIFO_SIZE/4);
 
       // Enlarge RX FIFO
-      core->grxfsiz = sz;
+      dwc2->grxfsiz = sz;
     }
 
     out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos)        |
@@ -502,7 +496,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
         (xfer->max_size << DOEPCTL_MPSIZ_Pos);
 
-    dev->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum));
+    dwc2->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum));
   }
   else
   {
@@ -528,7 +522,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
 
     // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + core->grxfsiz <= DWC2_EP_FIFO_SIZE/4);
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= DWC2_EP_FIFO_SIZE/4);
 
     _allocated_fifo_words_tx += fifo_size;
 
@@ -536,7 +530,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 
     // DIEPTXF starts at FIFO #1.
     // Both TXFD and TXSA are in unit of 32-bit words.
-    core->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+    dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
     in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) |
         (epnum << DIEPCTL_TXFNUM_Pos) |
@@ -544,7 +538,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
         (xfer->max_size << DIEPCTL_MPSIZ_Pos);
 
-    dev->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
+    dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
   }
 
   return true;
@@ -555,13 +549,12 @@ void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
 
-//  dwc2_core_t * core = CORE_REG(rhport);
-  dwc2_core_t * dev    = DEVICE_REG(rhport);
+  dwc2_regs_t * dwc2    = DWC2_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   // Disable non-control interrupt
-  dev->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
+  dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
 
   for(uint8_t n = 1; n < DWC2_EP_MAX; n++)
   {
@@ -642,8 +635,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
 {
   (void) rhport;
 
-  dwc2_core_t   * core   = CORE_REG(rhport);
-  dwc2_core_t * dev    = DEVICE_REG(rhport);
+  dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
@@ -671,9 +663,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
-    core->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos);
-    core->grstctl |= GRSTCTL_TXFFLSH;
-    while ( (core->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {}
+    dwc2->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos);
+    dwc2->grstctl |= GRSTCTL_TXFFLSH;
+    while ( (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {}
   }
   else
   {
@@ -688,8 +680,8 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
       // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
       // anyway, and it can't be cleared by user code. If this while loop never
       // finishes, we have bigger problems than just the stack.
-      dev->dctl |= DCTL_SGONAK;
-      while ( (core->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {}
+      dwc2->dctl |= DCTL_SGONAK;
+      while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {}
 
       // Ditto here- disable the endpoint.
       out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
@@ -698,7 +690,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
       out_ep[epnum].DOEPINT = DOEPINT_EPDISD;
 
       // Allow other OUT endpoints to keep receiving.
-      dev->dctl |= DCTL_CGONAK;
+      dwc2->dctl |= DCTL_CGONAK;
     }
   }
 }
@@ -708,7 +700,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
  */
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
-  dwc2_core_t * core = CORE_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
@@ -720,8 +712,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 
   if (dir == TUSB_DIR_IN)
   {
-    uint16_t const fifo_size = (core->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
-    uint16_t const fifo_start = (core->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
+    uint16_t const fifo_size = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
+    uint16_t const fifo_start = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
     // For now only the last opened endpoint can be closed without fuss.
     TU_ASSERT(fifo_start == DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
     _allocated_fifo_words_tx -= fifo_size;
@@ -832,11 +824,11 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
 }
 
 static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
-  dwc2_core_t * core = CORE_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
   volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0);
 
   // Pop control word off FIFO
-  uint32_t ctl_word = core->grxstsp;
+  uint32_t ctl_word = dwc2->grxstsp;
   uint8_t pktsts    = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
   uint8_t epnum     = (ctl_word & GRXSTSP_EPNUM_Msk) >>  GRXSTSP_EPNUM_Pos;
   uint16_t bcnt     = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
@@ -896,7 +888,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
   }
 }
 
-static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *out_ep)
+static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2, dwc2_epout_t *out_ep)
 {
   // DAINT for a given EP clears when DOEPINTx is cleared.
   // OEPINT will be cleared when DAINT's out bits are cleared.
@@ -904,7 +896,7 @@ static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *o
   {
     xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
 
-    if ( dev->daint & (1 << (DAINT_OEPINT_Pos + n)) )
+    if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) )
     {
       // SETUP packet Setup Phase done.
       if ( out_ep[n].DOEPINT & DOEPINT_STUP )
@@ -933,14 +925,14 @@ static void handle_epout_ints (uint8_t rhport, dwc2_core_t *dev, dwc2_epout_t *o
   }
 }
 
-static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in_ep) {
+static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * in_ep) {
   // DAINT for a given EP clears when DIEPINTx is cleared.
   // IEPINT will be cleared when DAINT's out bits are cleared.
   for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
   {
     xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
 
-    if ( dev->daint & (1 << (DAINT_IEPINT_Pos + n)) )
+    if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) )
     {
       // IN XFER complete (entire xfer).
       if ( in_ep[n].DIEPINT & DIEPINT_XFRC )
@@ -957,7 +949,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in
       }
 
       // XFER FIFO empty
-      if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dev->diepempmsk & (1 << n)) )
+      if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) )
       {
         // DIEPINT's TXFE bit is read-only, software cannot clear it.
         // It will only be cleared by hardware when written bytes is more than
@@ -996,7 +988,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in
         // Turn off TXFE if all bytes are written.
         if (((in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0)
         {
-          dev->diepempmsk &= ~(1 << n);
+          dwc2->diepempmsk &= ~(1 << n);
         }
       }
     }
@@ -1005,17 +997,16 @@ static void handle_epin_ints(uint8_t rhport, dwc2_core_t * dev, dwc2_epin_t * in
 
 void dcd_int_handler(uint8_t rhport)
 {
-  dwc2_core_t   * core   = CORE_REG(rhport);
-  dwc2_core_t * dev    = DEVICE_REG(rhport);
+  dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
   dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
-  uint32_t const int_status = core->gintsts & core->gintmsk;
+  uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk;
 
   if(int_status & GINTSTS_USBRST)
   {
     // USBRST is start of reset.
-    core->gintsts = GINTSTS_USBRST;
+    dwc2->gintsts = GINTSTS_USBRST;
     bus_reset(rhport);
   }
 
@@ -1023,23 +1014,23 @@ void dcd_int_handler(uint8_t rhport)
   {
     // ENUMDNE is the end of reset where speed of the link is detected
 
-    core->gintsts = GINTSTS_ENUMDNE;
+    dwc2->gintsts = GINTSTS_ENUMDNE;
 
     tusb_speed_t const speed = get_speed(rhport);
 
-    dwc2_set_turnaround(core, speed);
+    dwc2_set_turnaround(dwc2, speed);
     dcd_event_bus_reset(rhport, speed, true);
   }
 
   if(int_status & GINTSTS_USBSUSP)
   {
-    core->gintsts = GINTSTS_USBSUSP;
+    dwc2->gintsts = GINTSTS_USBSUSP;
     dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
   }
 
   if(int_status & GINTSTS_WKUINT)
   {
-    core->gintsts = GINTSTS_WKUINT;
+    dwc2->gintsts = GINTSTS_WKUINT;
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
   }
 
@@ -1049,22 +1040,22 @@ void dcd_int_handler(uint8_t rhport)
   if(int_status & GINTSTS_OTGINT)
   {
     // OTG INT bit is read-only
-    uint32_t const otg_int = core->gotgint;
+    uint32_t const otg_int = dwc2->gotgint;
 
     if (otg_int & GOTGINT_SEDET)
     {
       dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
     }
 
-    core->gotgint = otg_int;
+    dwc2->gotgint = otg_int;
   }
 
   if(int_status & GINTSTS_SOF)
   {
-    core->gotgint = GINTSTS_SOF;
+    dwc2->gotgint = GINTSTS_SOF;
 
     // Disable SOF interrupt since currently only used for remote wakeup detection
-    core->gintmsk &= ~GINTMSK_SOFM;
+    dwc2->gintmsk &= ~GINTMSK_SOFM;
 
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }
@@ -1075,13 +1066,13 @@ void dcd_int_handler(uint8_t rhport)
     // RXFLVL bit is read-only
 
     // Mask out RXFLVL while reading data from FIFO
-    core->gintmsk &= ~GINTMSK_RXFLVLM;
+    dwc2->gintmsk &= ~GINTMSK_RXFLVLM;
 
     // Loop until all available packets were handled
     do
     {
       handle_rxflvl_ints(rhport, out_ep);
-    } while(core->gotgint & GINTSTS_RXFLVL);
+    } while(dwc2->gotgint & GINTSTS_RXFLVL);
 
     // Manage RX FIFO size
     if (_out_ep_closed)
@@ -1092,21 +1083,21 @@ void dcd_int_handler(uint8_t rhport)
       _out_ep_closed = false;
     }
 
-    core->gintmsk |= GINTMSK_RXFLVLM;
+    dwc2->gintmsk |= GINTMSK_RXFLVLM;
   }
 
   // OUT endpoint interrupt handling.
   if(int_status & GINTSTS_OEPINT)
   {
     // OEPINT is read-only
-    handle_epout_ints(rhport, dev, out_ep);
+    handle_epout_ints(rhport, dwc2, out_ep);
   }
 
   // IN endpoint interrupt handling.
   if(int_status & GINTSTS_IEPINT)
   {
     // IEPINT bit read-only
-    handle_epin_ints(rhport, dev, in_ep);
+    handle_epin_ints(rhport, dwc2, in_ep);
   }
 
   //  // Check for Incomplete isochronous IN transfer
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index 5e544673d..d73ec0504 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -67,7 +67,7 @@ static inline void dwc2_remote_wakeup_delay(void)
   vTaskDelay(pdMS_TO_TICKS(1));
 }
 
-static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
+static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
 {
   (void) core;
   (void) speed;
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index db1fb89fd..f0c7cfb38 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -76,7 +76,7 @@ static inline void dwc2_remote_wakeup_delay(void)
   while ( count-- ) __asm volatile ("nop");
 }
 
-static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
+static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
 {
   (void) core;
   (void) speed;
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index d2ad8abb7..5a0071563 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -113,7 +113,7 @@ static inline void dwc2_remote_wakeup_delay(void)
 }
 
 // Set turn-around timeout according to link speed
-static inline void dwc2_set_turnaround(dwc2_core_t * core, tusb_speed_t speed)
+static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
 {
   core->gusbcfg &= ~GUSBCFG_TRDT;
 
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index b83ac67f9..23d724366 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -134,11 +134,11 @@ union {
 
 
   //------------- Device OUT Endpoint -------------//
-} dwc2_core_t;
+} dwc2_regs_t;
 
-TU_VERIFY_STATIC(offsetof(dwc2_core_t, hcfg   ) == 0x0400, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_core_t, channel) == 0x0500, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_core_t, dcfg   ) == 0x0800, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg   ) == 0x0400, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg   ) == 0x0800, "incorrect size");
 
 // Endpoint IN
 typedef struct

From 3755814f570b8803fad63b727f1f194aeca9e796 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 11:49:59 +0700
Subject: [PATCH 0601/2085] add epin, epout to dwc2 regs

---
 src/portable/synopsys/dwc2/dcd_dwc2.c   | 101 ++++++++++++------------
 src/portable/synopsys/dwc2/dwc2_esp32.h |   4 +-
 src/portable/synopsys/dwc2/dwc2_gd32.h  |   4 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h |   4 +-
 src/portable/synopsys/dwc2/dwc2_type.h  |  83 ++++++++++---------
 5 files changed, 98 insertions(+), 98 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index c0bf655f4..468ce520f 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -31,6 +31,7 @@
 #include "device/dcd_attr.h"
 
 
+
 #if TUSB_OPT_DEVICE_ENABLED && \
     ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) )
 
@@ -52,8 +53,8 @@
 //--------------------------------------------------------------------+
 
 #define DWC2_REG(_port)       ((dwc2_regs_t*) DWC2_REG_BASE)
-#define EPIN_REG(_port)       ((dwc2_epin_t*) (DWC2_REG_BASE + DWC2_IN_ENDPOINT_BASE))
-#define EPOUT_REG(_port)      ((dwc2_epout_t*) (DWC2_REG_BASE + DWC2_OUT_ENDPOINT_BASE))
+#define EPIN_REG(_port)       (DWC2_REG(_port)->epin)
+#define EPOUT_REG(_port)      (DWC2_REG(_port)->epout)
 #define FIFO_BASE(_port, _x)  ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
 
 enum
@@ -127,7 +128,7 @@ static void bus_reset(uint8_t rhport)
 
   // 1. NAK for all OUT endpoints
   for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
-    out_ep[n].DOEPCTL |= DOEPCTL_SNAK;
+    out_ep[n].doepctl |= DOEPCTL_SNAK;
   }
 
   // 2. Un-mask interrupt bits
@@ -193,10 +194,10 @@ static void bus_reset(uint8_t rhport)
   dwc2->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
-  in_ep[0].DIEPCTL &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
+  in_ep[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
   xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
 
-  out_ep[0].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos);
+  out_ep[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
 
   dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
@@ -290,17 +291,17 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
   // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
   if(dir == TUSB_DIR_IN) {
     // A full IN transfer (multiple packets, possibly) triggers XFRC.
-    in_ep[epnum].DIEPTSIZ = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
+    in_ep[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
         ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
 
-    in_ep[epnum].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+    in_ep[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
 
     // For ISO endpoint set correct odd/even bit for next frame.
-    if ((in_ep[epnum].DIEPCTL & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
+    if ((in_ep[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
     {
       // Take odd/even bit from frame counter.
       uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
-      in_ep[epnum].DIEPCTL |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
+      in_ep[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
     }
     // Enable fifo empty interrupt only if there are something to put in the fifo.
     if(total_bytes != 0) {
@@ -308,16 +309,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
     }
   } else {
     // A full OUT transfer (multiple packets, possibly) triggers XFRC.
-    out_ep[epnum].DOEPTSIZ &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
-    out_ep[epnum].DOEPTSIZ |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
+    out_ep[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
+    out_ep[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
         ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
 
-    out_ep[epnum].DOEPCTL |= DOEPCTL_EPENA | DOEPCTL_CNAK;
-    if ((out_ep[epnum].DOEPCTL & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
+    out_ep[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
+    if ((out_ep[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
     {
       // Take odd/even bit from frame counter.
       uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
-      out_ep[epnum].DOEPCTL |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
+      out_ep[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
     }
   }
 }
@@ -403,12 +404,12 @@ void dcd_init (uint8_t rhport)
 
 void dcd_int_enable (uint8_t rhport)
 {
-  dcd_dwc2_int_enable(rhport);
+  dwc2_dcd_int_enable(rhport);
 }
 
 void dcd_int_disable (uint8_t rhport)
 {
-  dcd_dwc2_int_disable(rhport);
+  dwc2_dcd_int_disable(rhport);
 }
 
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
@@ -491,7 +492,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
       dwc2->grxfsiz = sz;
     }
 
-    out_ep[epnum].DOEPCTL |= (1 << DOEPCTL_USBAEP_Pos)        |
+    out_ep[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos)        |
         (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos)   |
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
         (xfer->max_size << DOEPCTL_MPSIZ_Pos);
@@ -532,7 +533,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // Both TXFD and TXSA are in unit of 32-bit words.
     dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
-    in_ep[epnum].DIEPCTL |= (1 << DIEPCTL_USBAEP_Pos) |
+    in_ep[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
         (epnum << DIEPCTL_TXFNUM_Pos) |
         (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
@@ -559,11 +560,11 @@ void dcd_edpt_close_all (uint8_t rhport)
   for(uint8_t n = 1; n < DWC2_EP_MAX; n++)
   {
     // disable OUT endpoint
-    out_ep[n].DOEPCTL = 0;
+    out_ep[n].doepctl = 0;
     xfer_status[n][TUSB_DIR_OUT].max_size = 0;
 
     // disable IN endpoint
-    in_ep[n].DIEPCTL = 0;
+    in_ep[n].diepctl = 0;
     xfer_status[n][TUSB_DIR_IN].max_size = 0;
   }
 
@@ -645,21 +646,21 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
   if ( dir == TUSB_DIR_IN )
   {
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & DIEPCTL_EPENA) )
+    if ( (epnum == 0) || !(in_ep[epnum].diepctl & DIEPCTL_EPENA) )
     {
-      in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
+      in_ep[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
     }
     else
     {
       // Stop transmitting packets and NAK IN xfers.
-      in_ep[epnum].DIEPCTL |= DIEPCTL_SNAK;
-      while ( (in_ep[epnum].DIEPINT & DIEPINT_INEPNE) == 0 ) {}
+      in_ep[epnum].diepctl |= DIEPCTL_SNAK;
+      while ( (in_ep[epnum].diepint & DIEPINT_INEPNE) == 0 ) {}
 
       // Disable the endpoint.
-      in_ep[epnum].DIEPCTL |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
-      while ( (in_ep[epnum].DIEPINT & DIEPINT_EPDISD_Msk) == 0 ) {}
+      in_ep[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+      while ( (in_ep[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {}
 
-      in_ep[epnum].DIEPINT = DIEPINT_EPDISD;
+      in_ep[epnum].diepint = DIEPINT_EPDISD;
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
@@ -670,9 +671,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
   else
   {
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & DOEPCTL_EPENA) )
+    if ( (epnum == 0) || !(out_ep[epnum].doepctl & DOEPCTL_EPENA) )
     {
-      out_ep[epnum].DOEPCTL |= stall ? DOEPCTL_STALL : 0;
+      out_ep[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
     }
     else
     {
@@ -684,10 +685,10 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
       while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {}
 
       // Ditto here- disable the endpoint.
-      out_ep[epnum].DOEPCTL |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
-      while ( (out_ep[epnum].DOEPINT & DOEPINT_EPDISD_Msk) == 0 ) {}
+      out_ep[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+      while ( (out_ep[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {}
 
-      out_ep[epnum].DOEPINT = DOEPINT_EPDISD;
+      out_ep[epnum].doepint = DOEPINT_EPDISD;
 
       // Allow other OUT endpoints to keep receiving.
       dwc2->dctl |= DCTL_CGONAK;
@@ -742,13 +743,13 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   // Clear stall and reset data toggle
   if ( dir == TUSB_DIR_IN )
   {
-    in_ep[epnum].DIEPCTL &= ~DIEPCTL_STALL;
-    in_ep[epnum].DIEPCTL |= DIEPCTL_SD0PID_SEVNFRM;
+    in_ep[epnum].diepctl &= ~DIEPCTL_STALL;
+    in_ep[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM;
   }
   else
   {
-    out_ep[epnum].DOEPCTL &= ~DOEPCTL_STALL;
-    out_ep[epnum].DOEPCTL |= DOEPCTL_SD0PID_SEVNFRM;
+    out_ep[epnum].doepctl &= ~DOEPCTL_STALL;
+    out_ep[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM;
   }
 }
 
@@ -859,7 +860,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
 
       // Truncate transfer length in case of short packet
       if(bcnt < xfer->max_size) {
-        xfer->total_len -= (out_ep[epnum].DOEPTSIZ & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
+        xfer->total_len -= (out_ep[epnum].doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
         if(epnum == 0) {
           xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
           ep0_pending[TUSB_DIR_OUT] = 0;
@@ -872,7 +873,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
       break;
 
     case 0x04: // Setup packet done (Interrupt)
-      out_ep[epnum].DOEPTSIZ |= (3 << DOEPTSIZ_STUPCNT_Pos);
+      out_ep[epnum].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
       break;
 
     case 0x06: // Setup packet recvd
@@ -899,16 +900,16 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2, dwc2_epout_t *
     if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) )
     {
       // SETUP packet Setup Phase done.
-      if ( out_ep[n].DOEPINT & DOEPINT_STUP )
+      if ( out_ep[n].doepint & DOEPINT_STUP )
       {
-        out_ep[n].DOEPINT = DOEPINT_STUP;
+        out_ep[n].doepint = DOEPINT_STUP;
         dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
       }
 
       // OUT XFER complete
-      if ( out_ep[n].DOEPINT & DOEPINT_XFRC )
+      if ( out_ep[n].doepint & DOEPINT_XFRC )
       {
-        out_ep[n].DOEPINT = DOEPINT_XFRC;
+        out_ep[n].doepint = DOEPINT_XFRC;
 
         // EP0 can only handle one packet
         if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] )
@@ -935,9 +936,9 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i
     if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) )
     {
       // IN XFER complete (entire xfer).
-      if ( in_ep[n].DIEPINT & DIEPINT_XFRC )
+      if ( in_ep[n].diepint & DIEPINT_XFRC )
       {
-        in_ep[n].DIEPINT = DIEPINT_XFRC;
+        in_ep[n].diepint = DIEPINT_XFRC;
 
         // EP0 can only handle one packet
         if((n == 0) && ep0_pending[TUSB_DIR_IN]) {
@@ -949,26 +950,26 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i
       }
 
       // XFER FIFO empty
-      if ( (in_ep[n].DIEPINT & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) )
+      if ( (in_ep[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) )
       {
-        // DIEPINT's TXFE bit is read-only, software cannot clear it.
+        // diepint's TXFE bit is read-only, software cannot clear it.
         // It will only be cleared by hardware when written bytes is more than
         // - 64 bytes or
         // - Half of TX FIFO size (configured by DIEPTXF)
 
-        uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
+        uint16_t remaining_packets = (in_ep[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
 
         // Process every single packet (only whole packets can be written to fifo)
         for(uint16_t i = 0; i < remaining_packets; i++)
         {
-          uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
+          uint16_t const remaining_bytes = (in_ep[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
 
           // Packet can not be larger than ep max size
           uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
 
           // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
           // EP has to be checked if the buffer can take another WHOLE packet
-          if(packet_size > ((in_ep[n].DTXFSTS & DTXFSTS_INEPTFSAV_Msk) << 2)) break;
+          if(packet_size > ((in_ep[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) break;
 
           // Push packet to Tx-FIFO
           if (xfer->ff)
@@ -986,7 +987,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i
         }
 
         // Turn off TXFE if all bytes are written.
-        if (((in_ep[n].DIEPTSIZ & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0)
+        if (((in_ep[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0)
         {
           dwc2->diepempmsk &= ~(1 << n);
         }
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index d73ec0504..b8a040041 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -50,13 +50,13 @@ static void dcd_int_handler_wrap(void* arg)
   dcd_int_handler(0);
 }
 
-static inline void dcd_dwc2_int_enable (uint8_t rhport)
+static inline void dwc2_dcd_int_enable (uint8_t rhport)
 {
   (void) rhport;
   esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih);
 }
 
-static inline void dcd_dwc2_int_disable (uint8_t rhport)
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
   (void) rhport;
   esp_intr_free(usb_ih);
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index f0c7cfb38..de3ccb3b0 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -55,14 +55,14 @@ static inline void __eclic_disable_interrupt (uint32_t irq){
 }
 
 TU_ATTR_ALWAYS_INLINE
-static inline void dcd_dwc2_int_enable(uint8_t rhport)
+static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
   __eclic_enable_interrupt(RHPORT_IRQn);
 }
 
 TU_ATTR_ALWAYS_INLINE
-static inline void dcd_dwc2_int_disable (uint8_t rhport)
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
   (void) rhport;
   __eclic_disable_interrupt(RHPORT_IRQn);
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 5a0071563..236936d66 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -91,14 +91,14 @@
 extern uint32_t SystemCoreClock;
 
 TU_ATTR_ALWAYS_INLINE
-static inline void dcd_dwc2_int_enable(uint8_t rhport)
+static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
   NVIC_EnableIRQ(RHPORT_IRQn);
 }
 
 TU_ATTR_ALWAYS_INLINE
-static inline void dcd_dwc2_int_disable (uint8_t rhport)
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
   (void) rhport;
   NVIC_DisableIRQ(RHPORT_IRQn);
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 23d724366..8f011d642 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -40,16 +40,41 @@ typedef struct
 // Host Channel
 typedef struct
 {
-  volatile uint32_t hcchar;           // 500 + 20n Host Channel Characteristics Register
-  volatile uint32_t hcsplt;           // 504 + 20n Host Channel Split Control Register
-  volatile uint32_t hcint;            // 508 + 20n Host Channel Interrupt Register
-  volatile uint32_t hcintmsk;         // 50C + 20n Host Channel Interrupt Mask Register
-  volatile uint32_t hctsiz;           // 510 + 20n Host Channel Transfer Size Register
-  volatile uint32_t hcdma;            // 514 + 20n Host Channel DMA Address Register
-           uint32_t reserved518;      // 518 + 20n
-  volatile uint32_t hcdmab;           // 51C + 20n Host Channel DMA Address Register
+  volatile uint32_t hcchar;           // 500 + 20*ch Host Channel Characteristics Register
+  volatile uint32_t hcsplt;           // 504 + 20*ch Host Channel Split Control Register
+  volatile uint32_t hcint;            // 508 + 20*ch Host Channel Interrupt Register
+  volatile uint32_t hcintmsk;         // 50C + 20*ch Host Channel Interrupt Mask Register
+  volatile uint32_t hctsiz;           // 510 + 20*ch Host Channel Transfer Size Register
+  volatile uint32_t hcdma;            // 514 + 20*ch Host Channel DMA Address Register
+           uint32_t reserved518;      // 518 + 20*ch
+  volatile uint32_t hcdmab;           // 51C + 20*ch Host Channel DMA Address Register
 } dwc2_channel_t;
 
+// Endpoint IN
+typedef struct
+{
+  volatile uint32_t diepctl;       // 900 + 20*ep Device IN Endpoint Control
+           uint32_t reserved04;    // 904
+  volatile uint32_t diepint;       // 908 + 20*ep Device IN Endpoint Interrupt
+           uint32_t reserved0c;    // 90C
+  volatile uint32_t dieptsiz;      // 910 + 20*ep Device IN Endpoint Transfer Size
+  volatile uint32_t diepdma;       // 914 + 20*ep Device IN Endpoint DMA Address
+  volatile uint32_t dtxfsts;       // 918 + 20*ep Device IN Endpoint Tx FIFO Status
+           uint32_t reserved1c;    // 91C
+} dwc2_epin_t;
+
+// Endpoint OUT
+typedef struct
+{
+  volatile uint32_t doepctl;       // B00 + 20*ep Device OUT Endpoint Control
+           uint32_t reserved04;    // B04
+  volatile uint32_t doepint;       // B08 + 20*ep Device OUT Endpoint Interrupt
+           uint32_t reserved0c;    // B0C
+  volatile uint32_t doeptsiz;      // B10 + 20*ep Device OUT Endpoint Transfer Size
+  volatile uint32_t doepdma;       // B14 + 20*ep Device OUT Endpoint DMA Address
+           uint32_t reserved18[2]; // B18..B1C
+} dwc2_epout_t;
+
 typedef struct
 {
   //------------- Core Global -------------//
@@ -123,48 +148,22 @@ union {
   volatile uint32_t dvbuspulse;      // 82C Device VBUS Pulsing Time Register
   volatile uint32_t dthrctl;         // 830 Device threshold Control
   volatile uint32_t diepempmsk;      // 834 Device IN Endpoint FIFO Empty Interrupt Mask
-
   volatile uint32_t deachint;        // 838 Device Each Endpoint Interrupt
   volatile uint32_t deachmsk;        // 83C Device Each Endpoint Interrupt msk
   volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask
   volatile uint32_t doepeachmsk[16]; // 880..8BC Device Each OUT Endpoint mask
            uint32_t reserved8c0[16]; // 8C0..8FC
 
-  //------------- Device IN Endpoint -------------//
-
-
-  //------------- Device OUT Endpoint -------------//
+  //------------- Device Endpoint -------------//
+  dwc2_epin_t  epin[16];               // 900..AFC  IN Endpoints
+  dwc2_epout_t epout[16];              // B00..CFC  OUT Endpoints
 } dwc2_regs_t;
 
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg   ) == 0x0400, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg   ) == 0x0800, "incorrect size");
-
-// Endpoint IN
-typedef struct
-{
-  volatile uint32_t DIEPCTL;       // dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-           uint32_t Reserved04;    // Reserved                       900h + (ep_num * 20h) + 04h */
-  volatile uint32_t DIEPINT;       // dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-           uint32_t Reserved0C;    // Reserved                       900h + (ep_num * 20h) + 0Ch */
-  volatile uint32_t DIEPTSIZ;      // IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  volatile uint32_t DIEPDMA;       // IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  volatile uint32_t DTXFSTS;       // IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-           uint32_t Reserved18;    // Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} dwc2_epin_t;
-
-// Endpoint OUT
-typedef struct
-{
-  volatile uint32_t DOEPCTL;       // dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-           uint32_t Reserved04;    // Reserved                               B00h + (ep_num * 20h) + 04h */
-  volatile uint32_t DOEPINT;       // dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-           uint32_t Reserved0C;    // Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  volatile uint32_t DOEPTSIZ;      // dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  volatile uint32_t DOEPDMA;       // dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-           uint32_t Reserved18[2]; // Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} dwc2_epout_t;
-
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg   ) == 0x400, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x500, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg   ) == 0x800, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin   ) == 0x900, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout  ) == 0xB00, "incorrect size");
 
 //--------------------------------------------------------------------+
 // Register Base Address

From 5e1a0318004d95c6663e494ade76a0581594391e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 12:22:07 +0700
Subject: [PATCH 0602/2085] complete dwc2 regs struct

---
 src/portable/synopsys/dwc2/dcd_dwc2.c  |  16 ++-
 src/portable/synopsys/dwc2/dwc2_type.h | 136 +++++++++++++------------
 2 files changed, 80 insertions(+), 72 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 468ce520f..718773a00 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -30,8 +30,6 @@
 #include "tusb_option.h"
 #include "device/dcd_attr.h"
 
-
-
 #if TUSB_OPT_DEVICE_ENABLED && \
     ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) )
 
@@ -84,7 +82,7 @@ xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
 // EP0 transfers are limited to 1 packet - larger sizes has to be split
 static uint16_t ep0_pending[2];                   // Index determines direction as tusb_dir_t type
 
-// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from core->GRXFSIZ
+// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
 static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
 static bool _out_ep_closed;                       // Flag to check if RX FIFO size needs an update (reduce its size)
 
@@ -98,7 +96,7 @@ static void update_grxfsiz(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_regs_t * core = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
   // Determine largest EP size for RX FIFO
   uint16_t max_epsize = 0;
@@ -108,7 +106,7 @@ static void update_grxfsiz(uint8_t rhport)
   }
 
   // Update size of RX FIFO
-  core->grxfsiz = calc_rx_ff_size(max_epsize);
+  dwc2->grxfsiz = calc_rx_ff_size(max_epsize);
 }
 
 // Setup the control endpoint 0.
@@ -340,7 +338,7 @@ void dcd_init (uint8_t rhport)
     // On selected MCUs HS port1 can be used with external PHY via ULPI interface
 #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
     // deactivate internal PHY
-    dwc2->gccfg &= ~GCCFG_PWRDWN;
+    dwc2->stm32_gccfg &= ~GCCFG_PWRDWN;
 
     // Init The UTMI Interface
     dwc2->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
@@ -356,7 +354,7 @@ void dcd_init (uint8_t rhport)
 
     // Select UTMI Interface
     dwc2->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL;
-    dwc2->gccfg |= GCCFG_PHYHSEN;
+    dwc2->stm32_gccfg |= GCCFG_PHYHSEN;
 
     // Enables control of a High Speed USB PHY
     USB_HS_PHYCInit();
@@ -374,7 +372,7 @@ void dcd_init (uint8_t rhport)
   while ((dwc2->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
 
   // Restart PHY clock
-  *((volatile uint32_t *)(DWC2_REG_BASE + DWC2_PCGCCTL_BASE)) = 0;
+  dwc2->pcgctrl = 0;
 
   // Clear all interrupts
   dwc2->gintsts |= dwc2->gintsts;
@@ -391,7 +389,7 @@ void dcd_init (uint8_t rhport)
   set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
 
   // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->gccfg |= GCCFG_PWRDWN;
+  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->stm32_gccfg |= GCCFG_PWRDWN;
 
   dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
                    GINTMSK_WUIM   | GINTMSK_RXFLVLM;
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 8f011d642..95d043b86 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -78,42 +78,42 @@ typedef struct
 typedef struct
 {
   //------------- Core Global -------------//
-  volatile uint32_t gotgctl;              // 000 OTG Control and Status Register
-  volatile uint32_t gotgint;              // 004 OTG Interrupt Register
-  volatile uint32_t gahbcfg;              // 008 AHB Configuration Register
-  volatile uint32_t gusbcfg;              // 00c USB Configuration Register
-  volatile uint32_t grstctl;              // 010 Reset Register
-  volatile uint32_t gintsts;              // 014 Interrupt Register
-  volatile uint32_t gintmsk;              // 018 Interrupt Mask Register
-  volatile uint32_t grxstsr;              // 01c Receive Status Debug Read Register
-  volatile uint32_t grxstsp;              // 020 Receive Status Read/Pop Register
-  volatile uint32_t grxfsiz;              // 024 Receive FIFO Size Register
+  volatile uint32_t gotgctl;          // 000 OTG Control and Status Register
+  volatile uint32_t gotgint;          // 004 OTG Interrupt Register
+  volatile uint32_t gahbcfg;          // 008 AHB Configuration Register
+  volatile uint32_t gusbcfg;          // 00c USB Configuration Register
+  volatile uint32_t grstctl;          // 010 Reset Register
+  volatile uint32_t gintsts;          // 014 Interrupt Register
+  volatile uint32_t gintmsk;          // 018 Interrupt Mask Register
+  volatile uint32_t grxstsr;          // 01c Receive Status Debug Read Register
+  volatile uint32_t grxstsp;          // 020 Receive Status Read/Pop Register
+  volatile uint32_t grxfsiz;          // 024 Receive FIFO Size Register
 union {
-  volatile uint32_t dieptxf0;             // 028 EP0 Tx FIFO Size Register
-  volatile uint32_t gnptxfsiz;            // 028 Non-periodic Transmit FIFO Size Register
+  volatile uint32_t dieptxf0;         // 028 EP0 Tx FIFO Size Register
+  volatile uint32_t gnptxfsiz;        // 028 Non-periodic Transmit FIFO Size Register
 };
-  volatile uint32_t gnptxsts;             // 02c Non-periodic Transmit FIFO/Queue Status Register
-  volatile uint32_t gi2cctl;              // 030 I2C Address Register
-  volatile uint32_t gpvndctl;             // 034 PHY Vendor Control Register
+  volatile uint32_t gnptxsts;         // 02c Non-periodic Transmit FIFO/Queue Status Register
+  volatile uint32_t gi2cctl;          // 030 I2C Address Register
+  volatile uint32_t gpvndctl;         // 034 PHY Vendor Control Register
 union {
-  volatile uint32_t ggpio;                // 038 General Purpose IO Register
-  volatile uint32_t gccfg;                // 038 STM32 General Core Configuration
+  volatile uint32_t ggpio;            // 038 General Purpose IO Register
+  volatile uint32_t stm32_gccfg;      // 038 STM32 General Core Configuration
 };
-  volatile uint32_t guid;                 // 03C User ID Register
-  volatile uint32_t gsnpsid;              // 040 Synopsys ID Register
-  volatile uint32_t ghwcfg1;              // 044 User Hardware Configuration 1 Register
-  volatile uint32_t ghwcfg2;              // 048 User Hardware Configuration 2 Register
-  volatile uint32_t ghwcfg3;              // 04C User Hardware Configuration 3 Register
-  volatile uint32_t ghwcfg4;              // 050 User Hardware Configuration 4 Register
-  volatile uint32_t glpmcfg;              // 054 Core LPM Configuration Register
-  volatile uint32_t gpwrdn;               // 058 Power Down Register
-  volatile uint32_t gdfifocfg;            // 05C DFIFO Software Configuration Register
-  volatile uint32_t gadpctl;              // 060 ADP Timer, Control and Status Register
+  volatile uint32_t guid;             // 03C User ID Register
+  volatile uint32_t gsnpsid;          // 040 Synopsys ID Register
+  volatile uint32_t ghwcfg1;          // 044 User Hardware Configuration 1 Register
+  volatile uint32_t ghwcfg2;          // 048 User Hardware Configuration 2 Register
+  volatile uint32_t ghwcfg3;          // 04C User Hardware Configuration 3 Register
+  volatile uint32_t ghwcfg4;          // 050 User Hardware Configuration 4 Register
+  volatile uint32_t glpmcfg;          // 054 Core LPM Configuration Register
+  volatile uint32_t gpwrdn;           // 058 Power Down Register
+  volatile uint32_t gdfifocfg;        // 05C DFIFO Software Configuration Register
+  volatile uint32_t gadpctl;          // 060 ADP Timer, Control and Status Register
 
-           uint32_t reserved64[39];       // 064..0FF
-  volatile uint32_t hptxfsiz;             // 100 Host Periodic Tx FIFO Size Register
-  volatile uint32_t dieptxf[15];          // 104..13C Device Periodic Transmit FIFO Size Register
-           uint32_t reserved140[176];     // 140..3FC
+           uint32_t reserved64[39];   // 064..0FF
+  volatile uint32_t hptxfsiz;         // 100 Host Periodic Tx FIFO Size Register
+  volatile uint32_t dieptxf[15];      // 104..13C Device Periodic Transmit FIFO Size Register
+           uint32_t reserved140[176]; // 140..3FF
 
   //------------- Host -------------//
   volatile uint32_t hcfg;             // 400 Host Configuration Register
@@ -124,46 +124,56 @@ union {
   volatile uint32_t haint;            // 414 Host All Channels Interrupt Register
   volatile uint32_t haintmsk;         // 418 Host All Channels Interrupt Mask
   volatile uint32_t hflbaddr;         // 41C Host Frame List Base Address Register
-           uint32_t reserved420[8];   // 420..43C
+           uint32_t reserved420[8];   // 420..43F
   volatile uint32_t hprt;             // 440 Host Port Control and Status
-           uint32_t reserved444[47];  // 444..4FC
+           uint32_t reserved444[47];  // 444..4FF
 
   //------------- Host Channel -------------//
-  dwc2_channel_t channel[16];         // 500..6FC Host Channels 0-15
+  dwc2_channel_t    channel[16];      // 500..6FF Host Channels 0-15
+           uint32_t reserved700[64];  // 700..7FF
 
-           uint32_t reserved700[64];  // 700..7FC
-
-  //------------- Device -------------//
-  volatile uint32_t dcfg;            // 800 Device Configuration Register
-  volatile uint32_t dctl;            // 804 Device Control Register
-  volatile uint32_t dsts;            // 808 Device Status Register (RO)
-           uint32_t reserved80c;     // 80C
-  volatile uint32_t diepmsk;         // 810 Device IN Endpoint Interrupt Mask
-  volatile uint32_t doepmsk;         // 814 Device OUT Endpoint Interrupt Mask
-  volatile uint32_t daint;           // 818 Device All Endpoints Interrupt
-  volatile uint32_t daintmsk;        // 81C Device All Endpoints Interrupt Mask
-  volatile uint32_t dtknqr1;         // 820 Device IN token sequence learning queue read register1
-  volatile uint32_t dtknqr2;         // 824 Device IN token sequence learning queue read register2
-  volatile uint32_t dvbusdis;        // 828 Device VBUS Discharge Time Register
-  volatile uint32_t dvbuspulse;      // 82C Device VBUS Pulsing Time Register
-  volatile uint32_t dthrctl;         // 830 Device threshold Control
-  volatile uint32_t diepempmsk;      // 834 Device IN Endpoint FIFO Empty Interrupt Mask
-  volatile uint32_t deachint;        // 838 Device Each Endpoint Interrupt
-  volatile uint32_t deachmsk;        // 83C Device Each Endpoint Interrupt msk
-  volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask
-  volatile uint32_t doepeachmsk[16]; // 880..8BC Device Each OUT Endpoint mask
-           uint32_t reserved8c0[16]; // 8C0..8FC
+ //------------- Device -------------//
+  volatile uint32_t dcfg;             // 800 Device Configuration Register
+  volatile uint32_t dctl;             // 804 Device Control Register
+  volatile uint32_t dsts;             // 808 Device Status Register (RO)
+           uint32_t reserved80c;      // 80C
+  volatile uint32_t diepmsk;          // 810 Device IN Endpoint Interrupt Mask
+  volatile uint32_t doepmsk;          // 814 Device OUT Endpoint Interrupt Mask
+  volatile uint32_t daint;            // 818 Device All Endpoints Interrupt
+  volatile uint32_t daintmsk;         // 81C Device All Endpoints Interrupt Mask
+  volatile uint32_t dtknqr1;          // 820 Device IN token sequence learning queue read register1
+  volatile uint32_t dtknqr2;          // 824 Device IN token sequence learning queue read register2
+  volatile uint32_t dvbusdis;         // 828 Device VBUS Discharge Time Register
+  volatile uint32_t dvbuspulse;       // 82C Device VBUS Pulsing Time Register
+  volatile uint32_t dthrctl;          // 830 Device threshold Control
+  volatile uint32_t diepempmsk;       // 834 Device IN Endpoint FIFO Empty Interrupt Mask
+  volatile uint32_t deachint;         // 838 Device Each Endpoint Interrupt
+  volatile uint32_t deachmsk;         // 83C Device Each Endpoint Interrupt msk
+  volatile uint32_t diepeachmsk[16];  // 840..87C Device Each IN Endpoint mask
+  volatile uint32_t doepeachmsk[16];  // 880..8BF Device Each OUT Endpoint mask
+           uint32_t reserved8c0[16];  // 8C0..8FF
 
   //------------- Device Endpoint -------------//
-  dwc2_epin_t  epin[16];               // 900..AFC  IN Endpoints
-  dwc2_epout_t epout[16];              // B00..CFC  OUT Endpoints
+  dwc2_epin_t       epin[16];         // 900..AFF  IN Endpoints
+  dwc2_epout_t      epout[16];        // B00..CFF  OUT Endpoints
+           uint32_t reservedd00[64];  // D00..DFF
+
+  //------------- Power Clock -------------//
+  volatile uint32_t pcgctrl;          // E00 Power and Clock Gating Control
+  volatile uint32_t pcgcctl1;         // E04
+           uint32_t reservede08[126]; // E08..FFF
+
+  //------------- FIFOs -------------//
+  volatile uint32_t fifo[16][0x400];  // 1000..FFFF Endpoint FIFO
 } dwc2_regs_t;
 
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg   ) == 0x400, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x500, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg   ) == 0x800, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin   ) == 0x900, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout  ) == 0xB00, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg   ) == 0x0400, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg   ) == 0x0800, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin   ) == 0x0900, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout  ) == 0x0B00, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctrl) == 0x0E00, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
 //--------------------------------------------------------------------+
 // Register Base Address

From 34844c90610763a91c421bc889ffe4a9d988e14a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 12:53:29 +0700
Subject: [PATCH 0603/2085] use dwc2->fifo[]

---
 src/portable/synopsys/dwc2/dcd_dwc2.c  | 14 ++++++++------
 src/portable/synopsys/dwc2/dwc2_type.h |  1 +
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 718773a00..1909f45fd 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -53,7 +53,6 @@
 #define DWC2_REG(_port)       ((dwc2_regs_t*) DWC2_REG_BASE)
 #define EPIN_REG(_port)       (DWC2_REG(_port)->epin)
 #define EPOUT_REG(_port)      (DWC2_REG(_port)->epout)
-#define FIFO_BASE(_port, _x)  ((volatile uint32_t*) (DWC2_REG_BASE + DWC2_FIFO_BASE + (_x) * DWC2_FIFO_SIZE))
 
 enum
 {
@@ -758,7 +757,8 @@ static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
 {
   (void) rhport;
 
-  volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  volatile uint32_t * rx_fifo = dwc2->fifo[0];
 
   // Reading full available 32 bit words from fifo
   uint16_t full_words = len >> 2;
@@ -794,7 +794,8 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
 {
   (void) rhport;
 
-  volatile uint32_t * tx_fifo = FIFO_BASE(rhport, fifo_num);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  volatile uint32_t * tx_fifo = dwc2->fifo[fifo_num];
 
   // Pushing full available 32 bit words to fifo
   uint16_t full_words = len >> 2;
@@ -822,9 +823,10 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
   }
 }
 
-static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep) {
+static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep)
+{
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  volatile uint32_t * rx_fifo = FIFO_BASE(rhport, 0);
+  volatile uint32_t * rx_fifo = dwc2->fifo[0];
 
   // Pop control word off FIFO
   uint32_t ctl_word = dwc2->grxstsp;
@@ -972,7 +974,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i
           // Push packet to Tx-FIFO
           if (xfer->ff)
           {
-            volatile uint32_t * tx_fifo = FIFO_BASE(rhport, n);
+            volatile uint32_t * tx_fifo = dwc2->fifo[n];
             tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size);
           }
           else
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 95d043b86..5669aa88d 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -164,6 +164,7 @@ union {
            uint32_t reservede08[126]; // E08..FFF
 
   //------------- FIFOs -------------//
+  // Word-accessed only using first pointer since it auto shift
   volatile uint32_t fifo[16][0x400];  // 1000..FFFF Endpoint FIFO
 } dwc2_regs_t;
 

From e7655a75673fd444f39185feb4a9a0edf8ac07fe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 13:02:26 +0700
Subject: [PATCH 0604/2085] update the access epout

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 85 +++++++++++++--------------
 1 file changed, 41 insertions(+), 44 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 1909f45fd..11040a6cd 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -52,7 +52,6 @@
 
 #define DWC2_REG(_port)       ((dwc2_regs_t*) DWC2_REG_BASE)
 #define EPIN_REG(_port)       (DWC2_REG(_port)->epin)
-#define EPOUT_REG(_port)      (DWC2_REG(_port)->epout)
 
 enum
 {
@@ -114,8 +113,6 @@ static void bus_reset(uint8_t rhport)
   (void) rhport;
 
   dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
-  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
-  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   tu_memclr(xfer_status, sizeof(xfer_status));
   _out_ep_closed = false;
@@ -125,7 +122,7 @@ static void bus_reset(uint8_t rhport)
 
   // 1. NAK for all OUT endpoints
   for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
-    out_ep[n].doepctl |= DOEPCTL_SNAK;
+    dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
   }
 
   // 2. Un-mask interrupt bits
@@ -191,10 +188,10 @@ static void bus_reset(uint8_t rhport)
   dwc2->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
-  in_ep[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
+  dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
   xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
 
-  out_ep[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+  dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
 
   dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
@@ -274,48 +271,52 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
   (void) rhport;
 
   dwc2_regs_t * dwc2    = DWC2_REG(rhport);
-  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   // EP0 is limited to one packet each xfer
   // We use multiple transaction of xfer->max_size length to get a whole transfer done
-  if(epnum == 0) {
-    xfer_ctl_t * const xfer = XFER_CTL_BASE(epnum, dir);
+  if ( epnum == 0 )
+  {
+    xfer_ctl_t *const xfer = XFER_CTL_BASE(epnum, dir);
     total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
     ep0_pending[dir] -= total_bytes;
   }
 
   // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
-  if(dir == TUSB_DIR_IN) {
+  if ( dir == TUSB_DIR_IN )
+  {
     // A full IN transfer (multiple packets, possibly) triggers XFRC.
     in_ep[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
-        ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
+                            ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
 
     in_ep[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
 
     // For ISO endpoint set correct odd/even bit for next frame.
-    if ((in_ep[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
+    if ( (in_ep[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
     {
       // Take odd/even bit from frame counter.
       uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
       in_ep[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
     }
     // Enable fifo empty interrupt only if there are something to put in the fifo.
-    if(total_bytes != 0) {
+    if ( total_bytes != 0 )
+    {
       dwc2->diepempmsk |= (1 << epnum);
     }
-  } else {
+  }
+  else
+  {
     // A full OUT transfer (multiple packets, possibly) triggers XFRC.
-    out_ep[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
-    out_ep[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
-        ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
+    dwc2->epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
+    dwc2->epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
+                                   ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
 
-    out_ep[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
-    if ((out_ep[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
+    dwc2->epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
+    if ( (dwc2->epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
     {
       // Take odd/even bit from frame counter.
       uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
-      out_ep[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
+      dwc2->epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
     }
   }
 }
@@ -461,7 +462,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   (void) rhport;
 
   dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
-  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
@@ -489,7 +489,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
       dwc2->grxfsiz = sz;
     }
 
-    out_ep[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos)        |
+    dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos)        |
         (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos)   |
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
         (xfer->max_size << DOEPCTL_MPSIZ_Pos);
@@ -548,7 +548,6 @@ void dcd_edpt_close_all (uint8_t rhport)
   (void) rhport;
 
   dwc2_regs_t * dwc2    = DWC2_REG(rhport);
-  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   // Disable non-control interrupt
@@ -557,7 +556,7 @@ void dcd_edpt_close_all (uint8_t rhport)
   for(uint8_t n = 1; n < DWC2_EP_MAX; n++)
   {
     // disable OUT endpoint
-    out_ep[n].doepctl = 0;
+    dwc2->epout[n].doepctl = 0;
     xfer_status[n][TUSB_DIR_OUT].max_size = 0;
 
     // disable IN endpoint
@@ -634,7 +633,6 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
   (void) rhport;
 
   dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
-  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
@@ -668,9 +666,9 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
   else
   {
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(out_ep[epnum].doepctl & DOEPCTL_EPENA) )
+    if ( (epnum == 0) || !(dwc2->epout[epnum].doepctl & DOEPCTL_EPENA) )
     {
-      out_ep[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
+      dwc2->epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
     }
     else
     {
@@ -682,10 +680,10 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
       while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {}
 
       // Ditto here- disable the endpoint.
-      out_ep[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
-      while ( (out_ep[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {}
+      dwc2->epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+      while ( (dwc2->epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {}
 
-      out_ep[epnum].doepint = DOEPINT_EPDISD;
+      dwc2->epout[epnum].doepint = DOEPINT_EPDISD;
 
       // Allow other OUT endpoints to keep receiving.
       dwc2->dctl |= DCTL_CGONAK;
@@ -731,7 +729,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
 
-  dwc2_epout_t * out_ep = EPOUT_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
   dwc2_epin_t  * in_ep  = EPIN_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
@@ -745,8 +743,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   }
   else
   {
-    out_ep[epnum].doepctl &= ~DOEPCTL_STALL;
-    out_ep[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM;
+    dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL;
+    dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM;
   }
 }
 
@@ -823,7 +821,7 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
   }
 }
 
-static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep)
+static void handle_rxflvl_ints(uint8_t rhport)
 {
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
   volatile uint32_t * rx_fifo = dwc2->fifo[0];
@@ -860,7 +858,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep)
 
       // Truncate transfer length in case of short packet
       if(bcnt < xfer->max_size) {
-        xfer->total_len -= (out_ep[epnum].doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
+        xfer->total_len -= (dwc2->epout[epnum].doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
         if(epnum == 0) {
           xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
           ep0_pending[TUSB_DIR_OUT] = 0;
@@ -873,7 +871,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep)
       break;
 
     case 0x04: // Setup packet done (Interrupt)
-      out_ep[epnum].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+      dwc2->epout[epnum].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
       break;
 
     case 0x06: // Setup packet recvd
@@ -889,7 +887,7 @@ static void handle_rxflvl_ints(uint8_t rhport, dwc2_epout_t * out_ep)
   }
 }
 
-static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2, dwc2_epout_t *out_ep)
+static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2)
 {
   // DAINT for a given EP clears when DOEPINTx is cleared.
   // OEPINT will be cleared when DAINT's out bits are cleared.
@@ -900,16 +898,16 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2, dwc2_epout_t *
     if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) )
     {
       // SETUP packet Setup Phase done.
-      if ( out_ep[n].doepint & DOEPINT_STUP )
+      if ( dwc2->epout[n].doepint & DOEPINT_STUP )
       {
-        out_ep[n].doepint = DOEPINT_STUP;
+        dwc2->epout[n].doepint = DOEPINT_STUP;
         dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
       }
 
       // OUT XFER complete
-      if ( out_ep[n].doepint & DOEPINT_XFRC )
+      if ( dwc2->epout[n].doepint & DOEPINT_XFRC )
       {
-        out_ep[n].doepint = DOEPINT_XFRC;
+        dwc2->epout[n].doepint = DOEPINT_XFRC;
 
         // EP0 can only handle one packet
         if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] )
@@ -999,7 +997,6 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i
 void dcd_int_handler(uint8_t rhport)
 {
   dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
-  dwc2_epout_t  * out_ep = EPOUT_REG(rhport);
   dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk;
@@ -1072,7 +1069,7 @@ void dcd_int_handler(uint8_t rhport)
     // Loop until all available packets were handled
     do
     {
-      handle_rxflvl_ints(rhport, out_ep);
+      handle_rxflvl_ints(rhport);
     } while(dwc2->gotgint & GINTSTS_RXFLVL);
 
     // Manage RX FIFO size
@@ -1091,7 +1088,7 @@ void dcd_int_handler(uint8_t rhport)
   if(int_status & GINTSTS_OEPINT)
   {
     // OEPINT is read-only
-    handle_epout_ints(rhport, dwc2, out_ep);
+    handle_epout_ints(rhport, dwc2);
   }
 
   // IN endpoint interrupt handling.

From de413183d4b02a42dc1df798a1f62fb2d164eb60 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 13:07:00 +0700
Subject: [PATCH 0605/2085] use dwc2->epin

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 71 +++++++++++++--------------
 1 file changed, 34 insertions(+), 37 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 11040a6cd..ec1dac66c 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -51,7 +51,6 @@
 //--------------------------------------------------------------------+
 
 #define DWC2_REG(_port)       ((dwc2_regs_t*) DWC2_REG_BASE)
-#define EPIN_REG(_port)       (DWC2_REG(_port)->epin)
 
 enum
 {
@@ -271,7 +270,6 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
   (void) rhport;
 
   dwc2_regs_t * dwc2    = DWC2_REG(rhport);
-  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   // EP0 is limited to one packet each xfer
   // We use multiple transaction of xfer->max_size length to get a whole transfer done
@@ -286,17 +284,17 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
   if ( dir == TUSB_DIR_IN )
   {
     // A full IN transfer (multiple packets, possibly) triggers XFRC.
-    in_ep[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
+    dwc2->epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
                             ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
 
-    in_ep[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+    dwc2->epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
 
     // For ISO endpoint set correct odd/even bit for next frame.
-    if ( (in_ep[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
+    if ( (dwc2->epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
     {
       // Take odd/even bit from frame counter.
       uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
-      in_ep[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
+      dwc2->epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
     }
     // Enable fifo empty interrupt only if there are something to put in the fifo.
     if ( total_bytes != 0 )
@@ -462,7 +460,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   (void) rhport;
 
   dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
-  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
@@ -530,7 +527,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // Both TXFD and TXSA are in unit of 32-bit words.
     dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
-    in_ep[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
+    dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
         (epnum << DIEPCTL_TXFNUM_Pos) |
         (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
@@ -548,7 +545,6 @@ void dcd_edpt_close_all (uint8_t rhport)
   (void) rhport;
 
   dwc2_regs_t * dwc2    = DWC2_REG(rhport);
-  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   // Disable non-control interrupt
   dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
@@ -560,7 +556,7 @@ void dcd_edpt_close_all (uint8_t rhport)
     xfer_status[n][TUSB_DIR_OUT].max_size = 0;
 
     // disable IN endpoint
-    in_ep[n].diepctl = 0;
+    dwc2->epin[n].diepctl = 0;
     xfer_status[n][TUSB_DIR_IN].max_size = 0;
   }
 
@@ -633,7 +629,6 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
   (void) rhport;
 
   dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
-  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
@@ -641,21 +636,21 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
   if ( dir == TUSB_DIR_IN )
   {
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(in_ep[epnum].diepctl & DIEPCTL_EPENA) )
+    if ( (epnum == 0) || !(dwc2->epin[epnum].diepctl & DIEPCTL_EPENA) )
     {
-      in_ep[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
+      dwc2->epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
     }
     else
     {
       // Stop transmitting packets and NAK IN xfers.
-      in_ep[epnum].diepctl |= DIEPCTL_SNAK;
-      while ( (in_ep[epnum].diepint & DIEPINT_INEPNE) == 0 ) {}
+      dwc2->epin[epnum].diepctl |= DIEPCTL_SNAK;
+      while ( (dwc2->epin[epnum].diepint & DIEPINT_INEPNE) == 0 ) {}
 
       // Disable the endpoint.
-      in_ep[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
-      while ( (in_ep[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {}
+      dwc2->epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+      while ( (dwc2->epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {}
 
-      in_ep[epnum].diepint = DIEPINT_EPDISD;
+      dwc2->epin[epnum].diepint = DIEPINT_EPDISD;
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
@@ -730,7 +725,6 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   (void) rhport;
 
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  dwc2_epin_t  * in_ep  = EPIN_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
@@ -738,8 +732,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   // Clear stall and reset data toggle
   if ( dir == TUSB_DIR_IN )
   {
-    in_ep[epnum].diepctl &= ~DIEPCTL_STALL;
-    in_ep[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM;
+    dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL;
+    dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM;
   }
   else
   {
@@ -924,7 +918,8 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2)
   }
 }
 
-static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * in_ep) {
+static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2)
+{
   // DAINT for a given EP clears when DIEPINTx is cleared.
   // IEPINT will be cleared when DAINT's out bits are cleared.
   for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
@@ -934,46 +929,49 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i
     if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) )
     {
       // IN XFER complete (entire xfer).
-      if ( in_ep[n].diepint & DIEPINT_XFRC )
+      if ( dwc2->epin[n].diepint & DIEPINT_XFRC )
       {
-        in_ep[n].diepint = DIEPINT_XFRC;
+        dwc2->epin[n].diepint = DIEPINT_XFRC;
 
         // EP0 can only handle one packet
-        if((n == 0) && ep0_pending[TUSB_DIR_IN]) {
+        if ( (n == 0) && ep0_pending[TUSB_DIR_IN] )
+        {
           // Schedule another packet to be transmitted.
           edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
-        } else {
+        }
+        else
+        {
           dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
         }
       }
 
       // XFER FIFO empty
-      if ( (in_ep[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) )
+      if ( (dwc2->epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) )
       {
         // diepint's TXFE bit is read-only, software cannot clear it.
         // It will only be cleared by hardware when written bytes is more than
         // - 64 bytes or
         // - Half of TX FIFO size (configured by DIEPTXF)
 
-        uint16_t remaining_packets = (in_ep[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
+        uint16_t remaining_packets = (dwc2->epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
 
         // Process every single packet (only whole packets can be written to fifo)
-        for(uint16_t i = 0; i < remaining_packets; i++)
+        for ( uint16_t i = 0; i < remaining_packets; i++ )
         {
-          uint16_t const remaining_bytes = (in_ep[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
+          uint16_t const remaining_bytes = (dwc2->epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
 
           // Packet can not be larger than ep max size
           uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
 
           // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
           // EP has to be checked if the buffer can take another WHOLE packet
-          if(packet_size > ((in_ep[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) break;
+          if ( packet_size > ((dwc2->epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2) ) break;
 
           // Push packet to Tx-FIFO
-          if (xfer->ff)
+          if ( xfer->ff )
           {
-            volatile uint32_t * tx_fifo = dwc2->fifo[n];
-            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size);
+            volatile uint32_t *tx_fifo = dwc2->fifo[n];
+            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size);
           }
           else
           {
@@ -985,7 +983,7 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i
         }
 
         // Turn off TXFE if all bytes are written.
-        if (((in_ep[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0)
+        if ( ((dwc2->epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0 )
         {
           dwc2->diepempmsk &= ~(1 << n);
         }
@@ -997,7 +995,6 @@ static void handle_epin_ints(uint8_t rhport, dwc2_regs_t * dwc2, dwc2_epin_t * i
 void dcd_int_handler(uint8_t rhport)
 {
   dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
-  dwc2_epin_t   * in_ep  = EPIN_REG(rhport);
 
   uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk;
 
@@ -1095,7 +1092,7 @@ void dcd_int_handler(uint8_t rhport)
   if(int_status & GINTSTS_IEPINT)
   {
     // IEPINT bit read-only
-    handle_epin_ints(rhport, dwc2, in_ep);
+    handle_epin_ints(rhport, dwc2);
   }
 
   //  // Check for Incomplete isochronous IN transfer

From 4ebfd00d6741233a3dfcc3a74ee71f593887e847 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 13:33:40 +0700
Subject: [PATCH 0606/2085] clean up

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 146 ++++++++++++++------------
 1 file changed, 80 insertions(+), 66 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index ec1dac66c..15dece1df 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -111,7 +111,7 @@ static void bus_reset(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
   tu_memclr(xfer_status, sizeof(xfer_status));
   _out_ep_closed = false;
@@ -269,7 +269,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 {
   (void) rhport;
 
-  dwc2_regs_t * dwc2    = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
   // EP0 is limited to one packet each xfer
   // We use multiple transaction of xfer->max_size length to get a whole transfer done
@@ -283,18 +283,20 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
   // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
   if ( dir == TUSB_DIR_IN )
   {
+    dwc2_epin_t* epin = dwc2->epin;
+
     // A full IN transfer (multiple packets, possibly) triggers XFRC.
-    dwc2->epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
+    epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
                             ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
 
-    dwc2->epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+    epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
 
     // For ISO endpoint set correct odd/even bit for next frame.
-    if ( (dwc2->epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
+    if ( (epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
     {
       // Take odd/even bit from frame counter.
       uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
-      dwc2->epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
+      epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk);
     }
     // Enable fifo empty interrupt only if there are something to put in the fifo.
     if ( total_bytes != 0 )
@@ -304,17 +306,19 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
   }
   else
   {
+    dwc2_epout_t* epout = dwc2->epout;
+
     // A full OUT transfer (multiple packets, possibly) triggers XFRC.
-    dwc2->epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
-    dwc2->epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
+    epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
+    epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
                                    ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
 
-    dwc2->epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
-    if ( (dwc2->epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
+    epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
+    if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
     {
       // Take odd/even bit from frame counter.
       uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
-      dwc2->epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
+      epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk);
     }
   }
 }
@@ -421,7 +425,7 @@ void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_regs_t* dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
   // set remote wakeup
   dwc2->dctl |= DCTL_RWUSIG;
@@ -459,7 +463,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
   (void) rhport;
 
-  dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
@@ -486,10 +490,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
       dwc2->grxfsiz = sz;
     }
 
-    dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos)        |
-        (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos)   |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
-        (xfer->max_size << DOEPCTL_MPSIZ_Pos);
+    dwc2->epout[epnum].doepctl |= (1 << DOEPCTL_USBAEP_Pos) |
+                                  (desc_edpt->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) |
+                                  (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
+                                  (xfer->max_size << DOEPCTL_MPSIZ_Pos);
 
     dwc2->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum));
   }
@@ -528,10 +532,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
     dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
-        (epnum << DIEPCTL_TXFNUM_Pos) |
-        (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
-        (xfer->max_size << DIEPCTL_MPSIZ_Pos);
+                                 (epnum << DIEPCTL_TXFNUM_Pos) |
+                                 (desc_edpt->bmAttributes.xfer << DIEPCTL_EPTYP_Pos) |
+                                 (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DIEPCTL_SD0PID_SEVNFRM : 0) |
+                                 (xfer->max_size << DIEPCTL_MPSIZ_Pos);
 
     dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
   }
@@ -544,7 +548,7 @@ void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;
 
-  dwc2_regs_t * dwc2    = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
   // Disable non-control interrupt
   dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
@@ -628,29 +632,31 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
 {
   (void) rhport;
 
-  dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
+  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   if ( dir == TUSB_DIR_IN )
   {
+    dwc2_epin_t* epin = dwc2->epin;
+
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(dwc2->epin[epnum].diepctl & DIEPCTL_EPENA) )
+    if ( (epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA) )
     {
-      dwc2->epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
+      epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0);
     }
     else
     {
       // Stop transmitting packets and NAK IN xfers.
-      dwc2->epin[epnum].diepctl |= DIEPCTL_SNAK;
-      while ( (dwc2->epin[epnum].diepint & DIEPINT_INEPNE) == 0 ) {}
+      epin[epnum].diepctl |= DIEPCTL_SNAK;
+      while ( (epin[epnum].diepint & DIEPINT_INEPNE) == 0 ) {}
 
       // Disable the endpoint.
-      dwc2->epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
-      while ( (dwc2->epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {}
+      epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0);
+      while ( (epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0 ) {}
 
-      dwc2->epin[epnum].diepint = DIEPINT_EPDISD;
+      epin[epnum].diepint = DIEPINT_EPDISD;
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
@@ -660,10 +666,12 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
   }
   else
   {
+    dwc2_epout_t* epout = dwc2->epout;
+
     // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(dwc2->epout[epnum].doepctl & DOEPCTL_EPENA) )
+    if ( (epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA) )
     {
-      dwc2->epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
+      epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0;
     }
     else
     {
@@ -675,10 +683,10 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
       while ( (dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0 ) {}
 
       // Ditto here- disable the endpoint.
-      dwc2->epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
-      while ( (dwc2->epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {}
+      epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0);
+      while ( (epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0 ) {}
 
-      dwc2->epout[epnum].doepint = DOEPINT_EPDISD;
+      epout[epnum].doepint = DOEPINT_EPDISD;
 
       // Allow other OUT endpoints to keep receiving.
       dwc2->dctl |= DCTL_CGONAK;
@@ -826,20 +834,20 @@ static void handle_rxflvl_ints(uint8_t rhport)
   uint8_t epnum     = (ctl_word & GRXSTSP_EPNUM_Msk) >>  GRXSTSP_EPNUM_Pos;
   uint16_t bcnt     = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
 
-  switch(pktsts)
+  switch ( pktsts )
   {
-    case 0x01: // Global OUT NAK (Interrupt)
-      break;
+    case 0x01:    // Global OUT NAK (Interrupt)
+    break;
 
-    case 0x02: // Out packet recvd
+    case 0x02:    // Out packet received
     {
-      xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+      xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
 
       // Read packet off RxFIFO
-      if (xfer->ff)
+      if ( xfer->ff )
       {
         // Ring buffer
-        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt);
+        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt);
       }
       else
       {
@@ -851,9 +859,11 @@ static void handle_rxflvl_ints(uint8_t rhport)
       }
 
       // Truncate transfer length in case of short packet
-      if(bcnt < xfer->max_size) {
+      if ( bcnt < xfer->max_size )
+      {
         xfer->total_len -= (dwc2->epout[epnum].doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
-        if(epnum == 0) {
+        if ( epnum == 0 )
+        {
           xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
           ep0_pending[TUSB_DIR_OUT] = 0;
         }
@@ -861,28 +871,30 @@ static void handle_rxflvl_ints(uint8_t rhport)
     }
     break;
 
-    case 0x03: // Out packet done (Interrupt)
-      break;
+    case 0x03:    // Out packet done (Interrupt)
+    break;
 
-    case 0x04: // Setup packet done (Interrupt)
+    case 0x04:    // Setup packet done (Interrupt)
       dwc2->epout[epnum].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
-      break;
+    break;
 
-    case 0x06: // Setup packet recvd
+    case 0x06:    // Setup packet recvd
       // We can receive up to three setup packets in succession, but
       // only the last one is valid.
-      _setup_packet[0] = (* rx_fifo);
-      _setup_packet[1] = (* rx_fifo);
-      break;
+      _setup_packet[0] = (*rx_fifo);
+      _setup_packet[1] = (*rx_fifo);
+    break;
 
-    default: // Invalid
+    default:    // Invalid
       TU_BREAKPOINT();
-      break;
+    break;
   }
 }
 
 static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2)
 {
+  dwc2_epout_t* epout = dwc2->epout;
+
   // DAINT for a given EP clears when DOEPINTx is cleared.
   // OEPINT will be cleared when DAINT's out bits are cleared.
   for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
@@ -892,16 +904,16 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2)
     if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) )
     {
       // SETUP packet Setup Phase done.
-      if ( dwc2->epout[n].doepint & DOEPINT_STUP )
+      if ( epout[n].doepint & DOEPINT_STUP )
       {
-        dwc2->epout[n].doepint = DOEPINT_STUP;
+        epout[n].doepint = DOEPINT_STUP;
         dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
       }
 
       // OUT XFER complete
-      if ( dwc2->epout[n].doepint & DOEPINT_XFRC )
+      if ( epout[n].doepint & DOEPINT_XFRC )
       {
-        dwc2->epout[n].doepint = DOEPINT_XFRC;
+        epout[n].doepint = DOEPINT_XFRC;
 
         // EP0 can only handle one packet
         if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] )
@@ -920,6 +932,8 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2)
 
 static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2)
 {
+  dwc2_epin_t* epin = dwc2->epin;
+
   // DAINT for a given EP clears when DIEPINTx is cleared.
   // IEPINT will be cleared when DAINT's out bits are cleared.
   for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
@@ -929,9 +943,9 @@ static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2)
     if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) )
     {
       // IN XFER complete (entire xfer).
-      if ( dwc2->epin[n].diepint & DIEPINT_XFRC )
+      if ( epin[n].diepint & DIEPINT_XFRC )
       {
-        dwc2->epin[n].diepint = DIEPINT_XFRC;
+        epin[n].diepint = DIEPINT_XFRC;
 
         // EP0 can only handle one packet
         if ( (n == 0) && ep0_pending[TUSB_DIR_IN] )
@@ -946,26 +960,26 @@ static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2)
       }
 
       // XFER FIFO empty
-      if ( (dwc2->epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) )
+      if ( (epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n)) )
       {
         // diepint's TXFE bit is read-only, software cannot clear it.
         // It will only be cleared by hardware when written bytes is more than
         // - 64 bytes or
         // - Half of TX FIFO size (configured by DIEPTXF)
 
-        uint16_t remaining_packets = (dwc2->epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
+        uint16_t remaining_packets = (epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos;
 
         // Process every single packet (only whole packets can be written to fifo)
         for ( uint16_t i = 0; i < remaining_packets; i++ )
         {
-          uint16_t const remaining_bytes = (dwc2->epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
+          uint16_t const remaining_bytes = (epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos;
 
           // Packet can not be larger than ep max size
           uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
 
           // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
           // EP has to be checked if the buffer can take another WHOLE packet
-          if ( packet_size > ((dwc2->epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2) ) break;
+          if ( packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2) ) break;
 
           // Push packet to Tx-FIFO
           if ( xfer->ff )
@@ -983,7 +997,7 @@ static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2)
         }
 
         // Turn off TXFE if all bytes are written.
-        if ( ((dwc2->epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0 )
+        if ( ((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0 )
         {
           dwc2->diepempmsk &= ~(1 << n);
         }
@@ -994,7 +1008,7 @@ static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2)
 
 void dcd_int_handler(uint8_t rhport)
 {
-  dwc2_regs_t   * dwc2   = DWC2_REG(rhport);
+  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
 
   uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk;
 

From 5d05f8758fcf66ac8192eeefea7ff567ac749eb8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 13:36:43 +0700
Subject: [PATCH 0607/2085] more clean up

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 15dece1df..d9e21652e 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -823,7 +823,7 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
   }
 }
 
-static void handle_rxflvl_ints(uint8_t rhport)
+static void handle_rxflvl_irq(uint8_t rhport)
 {
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
   volatile uint32_t * rx_fifo = dwc2->fifo[0];
@@ -891,8 +891,9 @@ static void handle_rxflvl_ints(uint8_t rhport)
   }
 }
 
-static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2)
+static void handle_epout_irq (uint8_t rhport)
 {
+  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
   dwc2_epout_t* epout = dwc2->epout;
 
   // DAINT for a given EP clears when DOEPINTx is cleared.
@@ -930,8 +931,9 @@ static void handle_epout_ints (uint8_t rhport, dwc2_regs_t *dwc2)
   }
 }
 
-static void handle_epin_ints (uint8_t rhport, dwc2_regs_t *dwc2)
+static void handle_epin_irq (uint8_t rhport)
 {
+  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
   dwc2_epin_t* epin = dwc2->epin;
 
   // DAINT for a given EP clears when DIEPINTx is cleared.
@@ -1080,7 +1082,7 @@ void dcd_int_handler(uint8_t rhport)
     // Loop until all available packets were handled
     do
     {
-      handle_rxflvl_ints(rhport);
+      handle_rxflvl_irq(rhport);
     } while(dwc2->gotgint & GINTSTS_RXFLVL);
 
     // Manage RX FIFO size
@@ -1099,14 +1101,14 @@ void dcd_int_handler(uint8_t rhport)
   if(int_status & GINTSTS_OEPINT)
   {
     // OEPINT is read-only
-    handle_epout_ints(rhport, dwc2);
+    handle_epout_irq(rhport);
   }
 
   // IN endpoint interrupt handling.
   if(int_status & GINTSTS_IEPINT)
   {
     // IEPINT bit read-only
-    handle_epin_ints(rhport, dwc2);
+    handle_epin_irq(rhport);
   }
 
   //  // Check for Incomplete isochronous IN transfer

From 68fa9d406495410914b55c50984d5a1b821ee80c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 13:56:56 +0700
Subject: [PATCH 0608/2085] enhance fifo read/write

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 54 ++++++++++-----------------
 1 file changed, 19 insertions(+), 35 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index d9e21652e..67f84a083 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -758,39 +758,29 @@ static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
   (void) rhport;
 
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  volatile uint32_t * rx_fifo = dwc2->fifo[0];
+  volatile const uint32_t * rx_fifo = dwc2->fifo[0];
 
   // Reading full available 32 bit words from fifo
   uint16_t full_words = len >> 2;
-  for ( uint16_t i = 0; i < full_words; i++ )
+  while(full_words--)
   {
-    uint32_t tmp = *rx_fifo;
-    dst[0] = tmp & 0x000000FF;
-    dst[1] = (tmp & 0x0000FF00) >> 8;
-    dst[2] = (tmp & 0x00FF0000) >> 16;
-    dst[3] = (tmp & 0xFF000000) >> 24;
+    tu_unaligned_write32(dst, *rx_fifo);
     dst += 4;
   }
 
   // Read the remaining 1-3 bytes from fifo
-  uint8_t bytes_rem = len & 0x03;
+  uint8_t const bytes_rem = len & 0x03;
   if ( bytes_rem != 0 )
   {
-    uint32_t tmp = *rx_fifo;
-    dst[0] = tmp & 0x000000FF;
-    if ( bytes_rem > 1 )
-    {
-      dst[1] = (tmp & 0x0000FF00) >> 8;
-    }
-    if ( bytes_rem > 2 )
-    {
-      dst[2] = (tmp & 0x00FF0000) >> 16;
-    }
+    uint32_t const tmp = *rx_fifo;
+    dst[0] = tu_u32_byte0(tmp);
+    if ( bytes_rem > 1 ) dst[1] = tu_u32_byte1(tmp);
+    if ( bytes_rem > 2 ) dst[2] = tu_u32_byte2(tmp);
   }
 }
 
 // Write a single data packet to EPIN FIFO
-static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len)
+static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const * src, uint16_t len)
 {
   (void) rhport;
 
@@ -799,26 +789,20 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, u
 
   // Pushing full available 32 bit words to fifo
   uint16_t full_words = len >> 2;
-  for ( uint16_t i = 0; i < full_words; i++ )
+  while(full_words--)
   {
-    *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0];
+    *tx_fifo = tu_unaligned_read32(src);
     src += 4;
   }
 
   // Write the remaining 1-3 bytes into fifo
-  uint8_t bytes_rem = len & 0x03;
+  uint8_t const bytes_rem = len & 0x03;
   if ( bytes_rem )
   {
-    uint32_t tmp_word = 0;
-    tmp_word |= src[0];
-    if ( bytes_rem > 1 )
-    {
-      tmp_word |= src[1] << 8;
-    }
-    if ( bytes_rem > 2 )
-    {
-      tmp_word |= src[2] << 16;
-    }
+    uint32_t tmp_word = src[0];
+    if ( bytes_rem > 1 ) tmp_word |= (src[1] << 8);
+    if ( bytes_rem > 2 ) tmp_word |= (src[2] << 16);
+
     *tx_fifo = tmp_word;
   }
 }
@@ -830,9 +814,9 @@ static void handle_rxflvl_irq(uint8_t rhport)
 
   // Pop control word off FIFO
   uint32_t ctl_word = dwc2->grxstsp;
-  uint8_t pktsts    = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos;
-  uint8_t epnum     = (ctl_word & GRXSTSP_EPNUM_Msk) >>  GRXSTSP_EPNUM_Pos;
-  uint16_t bcnt     = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos;
+  uint8_t  pktsts   = (ctl_word & GRXSTSP_PKTSTS_Msk ) >> GRXSTSP_PKTSTS_Pos;
+  uint8_t  epnum    = (ctl_word & GRXSTSP_EPNUM_Msk  ) >> GRXSTSP_EPNUM_Pos;
+  uint16_t bcnt     = (ctl_word & GRXSTSP_BCNT_Msk   ) >> GRXSTSP_BCNT_Pos;
 
   switch ( pktsts )
   {

From bb5dab5c2e81be277214a6704a8d90e89a5b4759 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 22:48:01 +0700
Subject: [PATCH 0609/2085] add hw config struct

---
 hw/bsp/board.c                         |   2 +-
 src/common/tusb_common.h               |   4 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c  |  92 ++++++++--
 src/portable/synopsys/dwc2/dwc2_type.h | 234 ++++++++++++++++---------
 4 files changed, 240 insertions(+), 92 deletions(-)

diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 2c18b61b4..afacdef9f 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -96,7 +96,7 @@ void board_led_task(void)
 TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
 {
   (void) fhdl;
-  SEGGER_RTT_Write(0, (char*) buf, (int) count);
+  SEGGER_RTT_Write(0, (const char*) buf, (int) count);
   return count;
 }
 
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index bf9641622..e62bcde12 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -303,8 +303,8 @@ void tu_print_var(uint8_t const* buf, uint32_t bufsize)
 #define TU_LOG1               tu_printf
 #define TU_LOG1_MEM           tu_print_mem
 #define TU_LOG1_VAR(_x)       tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
-#define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (uint32_t) (_x) )
-#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (uint32_t) (_x) )
+#define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
+#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
 
 // Log Level 2: Warn
 #if CFG_TUSB_DEBUG >= 2
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 67f84a083..7b02c75cd 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -74,14 +74,14 @@ typedef struct {
 } xfer_ctl_t;
 
 xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
-#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
+#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
 
 // EP0 transfers are limited to 1 packet - larger sizes has to be split
 static uint16_t ep0_pending[2];                   // Index determines direction as tusb_dir_t type
 
 // TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz
 static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
-static bool _out_ep_closed;                       // Flag to check if RX FIFO size needs an update (reduce its size)
+static bool     _out_ep_closed;                   // Flag to check if RX FIFO size needs an update (reduce its size)
 
 // Calculate the RX FIFO size according to recommendations from reference manual
 static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
@@ -120,14 +120,15 @@ static void bus_reset(uint8_t rhport)
   dwc2->dcfg &= ~DCFG_DAD_Msk;
 
   // 1. NAK for all OUT endpoints
-  for(uint8_t n = 0; n < DWC2_EP_MAX; n++) {
+  for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
+  {
     dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
   }
 
   // 2. Un-mask interrupt bits
   dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
   dwc2->doepmsk  = DOEPMSK_STUPM | DOEPMSK_XFRCM;
-  dwc2->diepmsk  = DIEPMSK_TOM | DIEPMSK_XFRCM;
+  dwc2->diepmsk  = DIEPMSK_TOM   | DIEPMSK_XFRCM;
 
   // "USB Data FIFOs" section in reference manual
   // Peripheral FIFO architecture
@@ -188,7 +189,8 @@ static void bus_reset(uint8_t rhport)
 
   // Fixed control EP0 size to 64 bytes
   dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
-  xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
+  xfer_status[0][TUSB_DIR_OUT].max_size = 64;
+  xfer_status[0][TUSB_DIR_IN ].max_size = 64;
 
   dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
 
@@ -210,7 +212,7 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
 
   if ( rhport == 1 )
   {
-    bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
+    bitvalue = (TUSB_SPEED_HIGH == speed ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
   }
   else
   {
@@ -287,7 +289,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 
     // A full IN transfer (multiple packets, possibly) triggers XFRC.
     epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) |
-                            ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
+                           ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk);
 
     epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK;
 
@@ -311,10 +313,11 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
     // A full OUT transfer (multiple packets, possibly) triggers XFRC.
     epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ);
     epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) |
-                                   ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
+                             ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk);
 
     epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK;
-    if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1 )
+    if ( (epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 &&
+         XFER_CTL_BASE(epnum, dir)->interval == 1 )
     {
       // Take odd/even bit from frame counter.
       uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos));
@@ -326,13 +329,82 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
+void print_dwc2_info(dwc2_regs_t * dwc2)
+{
+  dwc2_ghwcfg2_t const * hw_cfg2 = &dwc2->ghwcfg2_bm;
+  dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm;
+  dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm;
+
+  TU_LOG_HEX(1, dwc2->guid);
+  TU_LOG_HEX(1, dwc2->gsnpsid);
+  TU_LOG_HEX(1, dwc2->ghwcfg1);
+
+  // HW configure 2
+  TU_LOG(1, "\r\n");
+  TU_LOG_HEX(1, dwc2->ghwcfg2);
+  TU_LOG_INT(1, hw_cfg2->op_mode                );
+  TU_LOG_INT(1, hw_cfg2->arch                   );
+  TU_LOG_INT(1, hw_cfg2->point2point            );
+  TU_LOG_INT(1, hw_cfg2->hs_phy_type            );
+  TU_LOG_INT(1, hw_cfg2->fs_phy_type            );
+  TU_LOG_INT(1, hw_cfg2->num_dev_ep             );
+  TU_LOG_INT(1, hw_cfg2->num_host_ch            );
+  TU_LOG_INT(1, hw_cfg2->period_channel_support );
+  TU_LOG_INT(1, hw_cfg2->enable_dynamic_fifo    );
+  TU_LOG_INT(1, hw_cfg2->mul_cpu_int            );
+  TU_LOG_INT(1, hw_cfg2->nperiod_tx_q_depth     );
+  TU_LOG_INT(1, hw_cfg2->host_period_tx_q_depth );
+  TU_LOG_INT(1, hw_cfg2->dev_token_q_depth      );
+  TU_LOG_INT(1, hw_cfg2->otg_enable_ic_usb      );
+
+  // HW configure 3
+  TU_LOG(1, "\r\n");
+  TU_LOG_HEX(1, dwc2->ghwcfg3);
+  TU_LOG_INT(1, hw_cfg3->xfer_size_width          );
+  TU_LOG_INT(1, hw_cfg3->packet_size_width        );
+  TU_LOG_INT(1, hw_cfg3->otg_enable               );
+  TU_LOG_INT(1, hw_cfg3->i2c_enable               );
+  TU_LOG_INT(1, hw_cfg3->vendor_ctrl_itf          );
+  TU_LOG_INT(1, hw_cfg3->optional_feature_removed );
+  TU_LOG_INT(1, hw_cfg3->synch_reset              );
+  TU_LOG_INT(1, hw_cfg3->otg_adp_support          );
+  TU_LOG_INT(1, hw_cfg3->otg_enable_hsic          );
+  TU_LOG_INT(1, hw_cfg3->otg_bc_support           );
+  TU_LOG_INT(1, hw_cfg3->lpm_mode                 );
+  TU_LOG_INT(1, hw_cfg3->total_fifo_size          );
+
+  // HW configure 4
+  TU_LOG(1, "\r\n");
+  TU_LOG_HEX(1, dwc2->ghwcfg4);
+  TU_LOG_INT(1, hw_cfg4->num_dev_period_in_ep      );
+  TU_LOG_INT(1, hw_cfg4->power_optimized           );
+  TU_LOG_INT(1, hw_cfg4->ahb_freq_min              );
+  TU_LOG_INT(1, hw_cfg4->hibernation               );
+  TU_LOG_INT(1, hw_cfg4->service_interval_mode     );
+  TU_LOG_INT(1, hw_cfg4->ipg_isoc_en               );
+  TU_LOG_INT(1, hw_cfg4->acg_enable                );
+  TU_LOG_INT(1, hw_cfg4->utmi_phy_data_width       );
+  TU_LOG_INT(1, hw_cfg4->dev_ctrl_ep_num           );
+  TU_LOG_INT(1, hw_cfg4->iddg_filter_enabled       );
+  TU_LOG_INT(1, hw_cfg4->vbus_valid_filter_enabled );
+  TU_LOG_INT(1, hw_cfg4->a_valid_filter_enabled    );
+  TU_LOG_INT(1, hw_cfg4->b_valid_filter_enabled    );
+  TU_LOG_INT(1, hw_cfg4->dedicated_fifos           );
+  TU_LOG_INT(1, hw_cfg4->num_dev_in_eps            );
+  TU_LOG_INT(1, hw_cfg4->dma_desc_enable           );
+  TU_LOG_INT(1, hw_cfg4->dma_dynamic               );
+}
+
 void dcd_init (uint8_t rhport)
 {
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
-  // check GSNPSID
+  // check gsnpsid
+  //TU_LOG_HEX(1, dwc2->gsnpsid);
+
+  print_dwc2_info(dwc2);
 
   // No HNP/SRP (no OTG support), program timeout later.
   if ( rhport == 1 )
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 5669aa88d..58e628970 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -19,6 +19,27 @@
 
 #include "stdint.h"
 
+/* DWC OTG HW Release versions */
+#define DWC2_CORE_REV_2_71a   0x4f54271a
+#define DWC2_CORE_REV_2_72a   0x4f54272a
+#define DWC2_CORE_REV_2_80a   0x4f54280a
+#define DWC2_CORE_REV_2_90a   0x4f54290a
+#define DWC2_CORE_REV_2_91a   0x4f54291a
+#define DWC2_CORE_REV_2_92a   0x4f54292a
+#define DWC2_CORE_REV_2_94a   0x4f54294a
+#define DWC2_CORE_REV_3_00a   0x4f54300a
+#define DWC2_CORE_REV_3_10a   0x4f54310a
+#define DWC2_CORE_REV_4_00a   0x4f54400a
+#define DWC2_CORE_REV_4_20a   0x4f54420a
+#define DWC2_FS_IOT_REV_1_00a 0x5531100a
+#define DWC2_HS_IOT_REV_1_00a 0x5532100a
+#define DWC2_CORE_REV_MASK    0x0000ffff
+
+/* DWC OTG HW Core ID */
+#define DWC2_OTG_ID           0x4f540000
+#define DWC2_FS_IOT_ID        0x55310000
+#define DWC2_HS_IOT_ID        0x55320000
+
 #ifdef __cplusplus
  extern "C" {
 #endif
@@ -37,93 +58,165 @@ typedef struct
 } HS_PHYC_GlobalTypeDef;
 #endif
 
+typedef struct TU_ATTR_PACKED
+{
+  uint32_t op_mode                  : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
+  uint32_t arch                     : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others
+  uint32_t point2point              : 1; // 0: support hub and split | 1: no hub, no split
+  uint32_t hs_phy_type              : 2; // 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI
+  uint32_t fs_phy_type              : 2; // 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI
+  uint32_t num_dev_ep               : 4; // Number of device endpoints (not including EP0)
+  uint32_t num_host_ch              : 4; // Number of host channel
+  uint32_t period_channel_support   : 1; // Support Periodic OUT Host Channel
+  uint32_t enable_dynamic_fifo      : 1; // Dynamic FIFO Sizing Enabled
+  uint32_t mul_cpu_int              : 1; // Multi-Processor Interrupt Enabled
+  uint32_t reserved21               : 1;
+  uint32_t nperiod_tx_q_depth       : 2; // Non-periodic request queue depth: 0 = 2.  1 = 4, 2 = 8
+  uint32_t host_period_tx_q_depth   : 2; // Host periodic request queue depth: 0 = 2.  1 = 4, 2 = 8
+  uint32_t dev_token_q_depth        : 5; // Device IN token sequence learning queue depth: 0-30
+  uint32_t otg_enable_ic_usb        : 1; // IC_USB mode specified for mode of operation
+} dwc2_ghwcfg2_t;
+
+TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED
+{
+  uint32_t xfer_size_width          : 4;  // Transfer size counter in bits = 11 + n (max 19 bits)
+  uint32_t packet_size_width        : 3;  // Packet size counter in bits = 4 + n (max 10 bits)
+  uint32_t otg_enable               : 1;  // 1 is OTG capable
+  uint32_t i2c_enable               : 1;  // I2C interface is available
+  uint32_t vendor_ctrl_itf          : 1;  // Vendor control interface is available
+  uint32_t optional_feature_removed : 1;  // remove User ID, GPIO, SOF toggle & counter
+  uint32_t synch_reset              : 1;  // 0: async reset | 1: synch reset
+  uint32_t otg_adp_support          : 1;  // ADP logic is present along with HSOTG controller
+  uint32_t otg_enable_hsic          : 1;  // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
+  uint32_t otg_bc_support           : 1;  // support battery charger
+  uint32_t lpm_mode                 : 1;  // LPC mode
+  uint32_t total_fifo_size          : 16; // DFIFO depth value in terms of 32-bit words
+}dwc2_ghwcfg3_t;
+
+TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size");
+
+typedef struct TU_ATTR_PACKED
+{
+  uint32_t num_dev_period_in_ep       : 4; // Number of Device Periodic IN Endpoints
+  uint32_t power_optimized            : 1; // Partial Power Down Enabled
+  uint32_t ahb_freq_min               : 1; // 1: minimum of AHB frequency is less than 60 MHz
+  uint32_t hibernation                : 1; // Hibernation feature is enabled
+  uint32_t reserved7                  : 3;
+  uint32_t service_interval_mode      : 1; // Service Interval supported
+  uint32_t ipg_isoc_en                : 1; // IPG ISOC supported
+  uint32_t acg_enable                 : 1; // ACG enabled
+  uint32_t reserved13                 : 1;
+  uint32_t utmi_phy_data_width        : 2; // 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable
+  uint32_t dev_ctrl_ep_num            : 4; // Number of Device control endpoints in addition to EP0
+  uint32_t iddg_filter_enabled        : 1;
+  uint32_t vbus_valid_filter_enabled  : 1;
+  uint32_t a_valid_filter_enabled     : 1;
+  uint32_t b_valid_filter_enabled     : 1;
+  uint32_t dedicated_fifos            : 1; // Dedicated tx fifo for device IN Endpoint is enabled
+  uint32_t num_dev_in_eps             : 4; // Number of Device IN Endpoints including EP0
+  uint32_t dma_desc_enable            : 1; // scatter/gather DMA configuration
+  uint32_t dma_dynamic                : 1; // Dynamic scatter/gather DMA
+}dwc2_ghwcfg4_t;
+
+TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size");
+
 // Host Channel
 typedef struct
 {
-  volatile uint32_t hcchar;           // 500 + 20*ch Host Channel Characteristics Register
-  volatile uint32_t hcsplt;           // 504 + 20*ch Host Channel Split Control Register
-  volatile uint32_t hcint;            // 508 + 20*ch Host Channel Interrupt Register
-  volatile uint32_t hcintmsk;         // 50C + 20*ch Host Channel Interrupt Mask Register
-  volatile uint32_t hctsiz;           // 510 + 20*ch Host Channel Transfer Size Register
-  volatile uint32_t hcdma;            // 514 + 20*ch Host Channel DMA Address Register
+  volatile uint32_t hcchar;           // 500 + 20*ch Host Channel Characteristics
+  volatile uint32_t hcsplt;           // 504 + 20*ch Host Channel Split Control
+  volatile uint32_t hcint;            // 508 + 20*ch Host Channel Interrupt
+  volatile uint32_t hcintmsk;         // 50C + 20*ch Host Channel Interrupt Mask
+  volatile uint32_t hctsiz;           // 510 + 20*ch Host Channel Transfer Size
+  volatile uint32_t hcdma;            // 514 + 20*ch Host Channel DMA Address
            uint32_t reserved518;      // 518 + 20*ch
-  volatile uint32_t hcdmab;           // 51C + 20*ch Host Channel DMA Address Register
+  volatile uint32_t hcdmab;           // 51C + 20*ch Host Channel DMA Address
 } dwc2_channel_t;
 
 // Endpoint IN
 typedef struct
 {
-  volatile uint32_t diepctl;       // 900 + 20*ep Device IN Endpoint Control
-           uint32_t reserved04;    // 904
-  volatile uint32_t diepint;       // 908 + 20*ep Device IN Endpoint Interrupt
-           uint32_t reserved0c;    // 90C
-  volatile uint32_t dieptsiz;      // 910 + 20*ep Device IN Endpoint Transfer Size
-  volatile uint32_t diepdma;       // 914 + 20*ep Device IN Endpoint DMA Address
-  volatile uint32_t dtxfsts;       // 918 + 20*ep Device IN Endpoint Tx FIFO Status
-           uint32_t reserved1c;    // 91C
+  volatile uint32_t diepctl;          // 900 + 20*ep Device IN Endpoint Control
+           uint32_t reserved04;       // 904
+  volatile uint32_t diepint;          // 908 + 20*ep Device IN Endpoint Interrupt
+           uint32_t reserved0c;       // 90C
+  volatile uint32_t dieptsiz;         // 910 + 20*ep Device IN Endpoint Transfer Size
+  volatile uint32_t diepdma;          // 914 + 20*ep Device IN Endpoint DMA Address
+  volatile uint32_t dtxfsts;          // 918 + 20*ep Device IN Endpoint Tx FIFO Status
+           uint32_t reserved1c;       // 91C
 } dwc2_epin_t;
 
 // Endpoint OUT
 typedef struct
 {
-  volatile uint32_t doepctl;       // B00 + 20*ep Device OUT Endpoint Control
-           uint32_t reserved04;    // B04
-  volatile uint32_t doepint;       // B08 + 20*ep Device OUT Endpoint Interrupt
-           uint32_t reserved0c;    // B0C
-  volatile uint32_t doeptsiz;      // B10 + 20*ep Device OUT Endpoint Transfer Size
-  volatile uint32_t doepdma;       // B14 + 20*ep Device OUT Endpoint DMA Address
-           uint32_t reserved18[2]; // B18..B1C
+  volatile uint32_t doepctl;          // B00 + 20*ep Device OUT Endpoint Control
+           uint32_t reserved04;       // B04
+  volatile uint32_t doepint;          // B08 + 20*ep Device OUT Endpoint Interrupt
+           uint32_t reserved0c;       // B0C
+  volatile uint32_t doeptsiz;         // B10 + 20*ep Device OUT Endpoint Transfer Size
+  volatile uint32_t doepdma;          // B14 + 20*ep Device OUT Endpoint DMA Address
+           uint32_t reserved18[2];    // B18..B1C
 } dwc2_epout_t;
 
 typedef struct
 {
   //------------- Core Global -------------//
-  volatile uint32_t gotgctl;          // 000 OTG Control and Status Register
-  volatile uint32_t gotgint;          // 004 OTG Interrupt Register
-  volatile uint32_t gahbcfg;          // 008 AHB Configuration Register
-  volatile uint32_t gusbcfg;          // 00c USB Configuration Register
-  volatile uint32_t grstctl;          // 010 Reset Register
-  volatile uint32_t gintsts;          // 014 Interrupt Register
-  volatile uint32_t gintmsk;          // 018 Interrupt Mask Register
-  volatile uint32_t grxstsr;          // 01c Receive Status Debug Read Register
-  volatile uint32_t grxstsp;          // 020 Receive Status Read/Pop Register
-  volatile uint32_t grxfsiz;          // 024 Receive FIFO Size Register
+  volatile uint32_t gotgctl;          // 000 OTG Control and Status
+  volatile uint32_t gotgint;          // 004 OTG Interrupt
+  volatile uint32_t gahbcfg;          // 008 AHB Configuration
+  volatile uint32_t gusbcfg;          // 00c USB Configuration
+  volatile uint32_t grstctl;          // 010 Reset
+  volatile uint32_t gintsts;          // 014 Interrupt
+  volatile uint32_t gintmsk;          // 018 Interrupt Mask
+  volatile uint32_t grxstsr;          // 01c Receive Status Debug Read
+  volatile uint32_t grxstsp;          // 020 Receive Status Read/Pop
+  volatile uint32_t grxfsiz;          // 024 Receive FIFO Size
 union {
-  volatile uint32_t dieptxf0;         // 028 EP0 Tx FIFO Size Register
-  volatile uint32_t gnptxfsiz;        // 028 Non-periodic Transmit FIFO Size Register
+  volatile uint32_t dieptxf0;         // 028 EP0 Tx FIFO Size
+  volatile uint32_t gnptxfsiz;        // 028 Non-periodic Transmit FIFO Size
 };
-  volatile uint32_t gnptxsts;         // 02c Non-periodic Transmit FIFO/Queue Status Register
-  volatile uint32_t gi2cctl;          // 030 I2C Address Register
-  volatile uint32_t gpvndctl;         // 034 PHY Vendor Control Register
+  volatile uint32_t gnptxsts;         // 02c Non-periodic Transmit FIFO/Queue Status
+  volatile uint32_t gi2cctl;          // 030 I2C Address
+  volatile uint32_t gpvndctl;         // 034 PHY Vendor Control
 union {
-  volatile uint32_t ggpio;            // 038 General Purpose IO Register
+  volatile uint32_t ggpio;            // 038 General Purpose IO
   volatile uint32_t stm32_gccfg;      // 038 STM32 General Core Configuration
 };
-  volatile uint32_t guid;             // 03C User ID Register
-  volatile uint32_t gsnpsid;          // 040 Synopsys ID Register
-  volatile uint32_t ghwcfg1;          // 044 User Hardware Configuration 1 Register
-  volatile uint32_t ghwcfg2;          // 048 User Hardware Configuration 2 Register
-  volatile uint32_t ghwcfg3;          // 04C User Hardware Configuration 3 Register
-  volatile uint32_t ghwcfg4;          // 050 User Hardware Configuration 4 Register
-  volatile uint32_t glpmcfg;          // 054 Core LPM Configuration Register
-  volatile uint32_t gpwrdn;           // 058 Power Down Register
-  volatile uint32_t gdfifocfg;        // 05C DFIFO Software Configuration Register
-  volatile uint32_t gadpctl;          // 060 ADP Timer, Control and Status Register
-
+  volatile uint32_t guid;             // 03C User (Application programmable) ID
+  volatile uint32_t gsnpsid;          // 040 Synopsys ID + Release version
+  volatile uint32_t ghwcfg1;          // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
+union {
+  volatile uint32_t ghwcfg2;          // 048 User Hardware Configuration2
+  dwc2_ghwcfg2_t    ghwcfg2_bm;
+};
+union {
+  volatile uint32_t ghwcfg3;          // 04C User Hardware Configuration3
+  dwc2_ghwcfg3_t    ghwcfg3_bm;
+};
+union {
+  volatile uint32_t ghwcfg4;          // 050 User Hardware Configuration4
+  dwc2_ghwcfg4_t    ghwcfg4_bm;
+};
+  volatile uint32_t glpmcfg;          // 054 Core LPM Configuration
+  volatile uint32_t gpwrdn;           // 058 Power Down
+  volatile uint32_t gdfifocfg;        // 05C DFIFO Software Configuration
+  volatile uint32_t gadpctl;          // 060 ADP Timer, Control and Status
            uint32_t reserved64[39];   // 064..0FF
-  volatile uint32_t hptxfsiz;         // 100 Host Periodic Tx FIFO Size Register
-  volatile uint32_t dieptxf[15];      // 104..13C Device Periodic Transmit FIFO Size Register
+  volatile uint32_t hptxfsiz;         // 100 Host Periodic Tx FIFO Size
+  volatile uint32_t dieptxf[15];      // 104..13C Device Periodic Transmit FIFO Size
            uint32_t reserved140[176]; // 140..3FF
 
   //------------- Host -------------//
-  volatile uint32_t hcfg;             // 400 Host Configuration Register
-  volatile uint32_t hfir;             // 404 Host Frame Interval Register
+  volatile uint32_t hcfg;             // 400 Host Configuration
+  volatile uint32_t hfir;             // 404 Host Frame Interval
   volatile uint32_t hfnum;            // 408 Host Frame Number / Frame Remaining
            uint32_t reserved40c;      // 40C
   volatile uint32_t hptxsts;          // 410 Host Periodic TX FIFO / Queue Status
-  volatile uint32_t haint;            // 414 Host All Channels Interrupt Register
+  volatile uint32_t haint;            // 414 Host All Channels Interrupt
   volatile uint32_t haintmsk;         // 418 Host All Channels Interrupt Mask
-  volatile uint32_t hflbaddr;         // 41C Host Frame List Base Address Register
+  volatile uint32_t hflbaddr;         // 41C Host Frame List Base Address
            uint32_t reserved420[8];   // 420..43F
   volatile uint32_t hprt;             // 440 Host Port Control and Status
            uint32_t reserved444[47];  // 444..4FF
@@ -133,18 +226,18 @@ union {
            uint32_t reserved700[64];  // 700..7FF
 
  //------------- Device -------------//
-  volatile uint32_t dcfg;             // 800 Device Configuration Register
-  volatile uint32_t dctl;             // 804 Device Control Register
-  volatile uint32_t dsts;             // 808 Device Status Register (RO)
+  volatile uint32_t dcfg;             // 800 Device Configuration
+  volatile uint32_t dctl;             // 804 Device Control
+  volatile uint32_t dsts;             // 808 Device Status (RO)
            uint32_t reserved80c;      // 80C
   volatile uint32_t diepmsk;          // 810 Device IN Endpoint Interrupt Mask
   volatile uint32_t doepmsk;          // 814 Device OUT Endpoint Interrupt Mask
   volatile uint32_t daint;            // 818 Device All Endpoints Interrupt
   volatile uint32_t daintmsk;         // 81C Device All Endpoints Interrupt Mask
-  volatile uint32_t dtknqr1;          // 820 Device IN token sequence learning queue read register1
-  volatile uint32_t dtknqr2;          // 824 Device IN token sequence learning queue read register2
-  volatile uint32_t dvbusdis;         // 828 Device VBUS Discharge Time Register
-  volatile uint32_t dvbuspulse;       // 82C Device VBUS Pulsing Time Register
+  volatile uint32_t dtknqr1;          // 820 Device IN token sequence learning queue read1
+  volatile uint32_t dtknqr2;          // 824 Device IN token sequence learning queue read2
+  volatile uint32_t dvbusdis;         // 828 Device VBUS Discharge Time
+  volatile uint32_t dvbuspulse;       // 82C Device VBUS Pulsing Time
   volatile uint32_t dthrctl;          // 830 Device threshold Control
   volatile uint32_t diepempmsk;       // 834 Device IN Endpoint FIFO Empty Interrupt Mask
   volatile uint32_t deachint;         // 838 Device Each Endpoint Interrupt
@@ -176,23 +269,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout  ) == 0x0B00, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctrl) == 0x0E00, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
-//--------------------------------------------------------------------+
-// Register Base Address
-//--------------------------------------------------------------------+
-
-#define DWC2_GLOBAL_BASE                  0x00000000UL
-#define DWC2_DEVICE_BASE                  0x00000800UL
-#define DWC2_IN_ENDPOINT_BASE             0x00000900UL
-#define DWC2_OUT_ENDPOINT_BASE            0x00000B00UL
-#define DWC2_EP_REG_SIZE                  0x00000020UL
-#define DWC2_HOST_BASE                    0x00000400UL
-#define DWC2_HOST_PORT_BASE               0x00000440UL
-#define DWC2_HOST_CHANNEL_BASE            0x00000500UL
-#define DWC2_HOST_CHANNEL_SIZE            0x00000020UL
-#define DWC2_PCGCCTL_BASE                 0x00000E00UL
-#define DWC2_FIFO_BASE                    0x00001000UL
-#define DWC2_FIFO_SIZE                    0x00001000UL
-
 //--------------------------------------------------------------------+
 // Register Bit Definitions
 //--------------------------------------------------------------------+

From 9f1cd1a753400327072973cbf2437f6c51bd5509 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 23:10:26 +0700
Subject: [PATCH 0610/2085] add synopsys id check, rename GCCFG_* to
 STM32_GCCFG-*

---
 src/portable/synopsys/dwc2/dcd_dwc2.c  | 13 ++---
 src/portable/synopsys/dwc2/dwc2_type.h | 72 +++++++++++++-------------
 2 files changed, 43 insertions(+), 42 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 7b02c75cd..58305838f 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -401,8 +401,9 @@ void dcd_init (uint8_t rhport)
   // peripheral in each Reference Manual.
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
-  // check gsnpsid
-  //TU_LOG_HEX(1, dwc2->gsnpsid);
+  // Check Synopsys ID
+  uint32_t const gsnpsid = dwc2->gsnpsid & 0xffff0000u;
+  TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, );
 
   print_dwc2_info(dwc2);
 
@@ -412,7 +413,7 @@ void dcd_init (uint8_t rhport)
     // On selected MCUs HS port1 can be used with external PHY via ULPI interface
 #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
     // deactivate internal PHY
-    dwc2->stm32_gccfg &= ~GCCFG_PWRDWN;
+    dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
 
     // Init The UTMI Interface
     dwc2->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
@@ -428,7 +429,7 @@ void dcd_init (uint8_t rhport)
 
     // Select UTMI Interface
     dwc2->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL;
-    dwc2->stm32_gccfg |= GCCFG_PHYHSEN;
+    dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
 
     // Enables control of a High Speed USB PHY
     USB_HS_PHYCInit();
@@ -463,7 +464,7 @@ void dcd_init (uint8_t rhport)
   set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
 
   // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->stm32_gccfg |= GCCFG_PWRDWN;
+  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
 
   dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
                    GINTMSK_WUIM   | GINTMSK_RXFLVLM;
@@ -546,7 +547,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   xfer->max_size = tu_edpt_packet_size(desc_edpt);
   xfer->interval = desc_edpt->bInterval;
 
-  uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word
+  uint16_t const fifo_size = tu_div_ceil(xfer->max_size, 4);
 
   if(dir == TUSB_DIR_OUT)
   {
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 58e628970..113f99180 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -1051,42 +1051,42 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DEACHINT_OEP1INT                 DEACHINT_OEP1INT_Msk                     // OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition for GCCFG register  ********************/
-#define GCCFG_DCDET_Pos                  (0U)
-#define GCCFG_DCDET_Msk                  (0x1UL << GCCFG_DCDET_Pos)               // 0x00000001 */
-#define GCCFG_DCDET                      GCCFG_DCDET_Msk                          // Data contact detection (DCD) status */
-#define GCCFG_PDET_Pos                   (1U)
-#define GCCFG_PDET_Msk                   (0x1UL << GCCFG_PDET_Pos)                // 0x00000002 */
-#define GCCFG_PDET                       GCCFG_PDET_Msk                           // Primary detection (PD) status */
-#define GCCFG_SDET_Pos                   (2U)
-#define GCCFG_SDET_Msk                   (0x1UL << GCCFG_SDET_Pos)                // 0x00000004 */
-#define GCCFG_SDET                       GCCFG_SDET_Msk                           // Secondary detection (SD) status */
-#define GCCFG_PS2DET_Pos                 (3U)
-#define GCCFG_PS2DET_Msk                 (0x1UL << GCCFG_PS2DET_Pos)              // 0x00000008 */
-#define GCCFG_PS2DET                     GCCFG_PS2DET_Msk                         // DM pull-up detection status */
-#define GCCFG_PWRDWN_Pos                 (16U)
-#define GCCFG_PWRDWN_Msk                 (0x1UL << GCCFG_PWRDWN_Pos)              // 0x00010000 */
-#define GCCFG_PWRDWN                     GCCFG_PWRDWN_Msk                         // Power down */
-#define GCCFG_BCDEN_Pos                  (17U)
-#define GCCFG_BCDEN_Msk                  (0x1UL << GCCFG_BCDEN_Pos)               // 0x00020000 */
-#define GCCFG_BCDEN                      GCCFG_BCDEN_Msk                          // Battery charging detector (BCD) enable */
-#define GCCFG_DCDEN_Pos                  (18U)
-#define GCCFG_DCDEN_Msk                  (0x1UL << GCCFG_DCDEN_Pos)               // 0x00040000 */
-#define GCCFG_DCDEN                      GCCFG_DCDEN_Msk                          // Data contact detection (DCD) mode enable*/
-#define GCCFG_PDEN_Pos                   (19U)
-#define GCCFG_PDEN_Msk                   (0x1UL << GCCFG_PDEN_Pos)                // 0x00080000 */
-#define GCCFG_PDEN                       GCCFG_PDEN_Msk                           // Primary detection (PD) mode enable*/
-#define GCCFG_SDEN_Pos                   (20U)
-#define GCCFG_SDEN_Msk                   (0x1UL << GCCFG_SDEN_Pos)                // 0x00100000 */
-#define GCCFG_SDEN                       GCCFG_SDEN_Msk                           // Secondary detection (SD) mode enable */
-#define GCCFG_VBDEN_Pos                  (21U)
-#define GCCFG_VBDEN_Msk                  (0x1UL << GCCFG_VBDEN_Pos)               // 0x00200000 */
-#define GCCFG_VBDEN                      GCCFG_VBDEN_Msk                          // VBUS mode enable */
-#define GCCFG_OTGIDEN_Pos                (22U)
-#define GCCFG_OTGIDEN_Msk                (0x1UL << GCCFG_OTGIDEN_Pos)             // 0x00400000 */
-#define GCCFG_OTGIDEN                    GCCFG_OTGIDEN_Msk                        // OTG Id enable */
-#define GCCFG_PHYHSEN_Pos                (23U)
-#define GCCFG_PHYHSEN_Msk                (0x1UL << GCCFG_PHYHSEN_Pos)             // 0x00800000 */
-#define GCCFG_PHYHSEN                    GCCFG_PHYHSEN_Msk                        // HS PHY enable */
+#define STM32_GCCFG_DCDET_Pos            (0U)
+#define STM32_GCCFG_DCDET_Msk            (0x1UL << STM32_GCCFG_DCDET_Pos)         // 0x00000001 */
+#define STM32_GCCFG_DCDET                STM32_GCCFG_DCDET_Msk                    // Data contact detection (DCD) status */
+#define STM32_GCCFG_PDET_Pos             (1U)
+#define STM32_GCCFG_PDET_Msk             (0x1UL << STM32_GCCFG_PDET_Pos)          // 0x00000002 */
+#define STM32_GCCFG_PDET                 STM32_GCCFG_PDET_Msk                     // Primary detection (PD) status */
+#define STM32_GCCFG_SDET_Pos             (2U)
+#define STM32_GCCFG_SDET_Msk             (0x1UL << STM32_GCCFG_SDET_Pos)          // 0x00000004 */
+#define STM32_GCCFG_SDET                 STM32_GCCFG_SDET_Msk                     // Secondary detection (SD) status */
+#define STM32_GCCFG_PS2DET_Pos           (3U)
+#define STM32_GCCFG_PS2DET_Msk           (0x1UL << STM32_GCCFG_PS2DET_Pos)        // 0x00000008 */
+#define STM32_GCCFG_PS2DET               STM32_GCCFG_PS2DET_Msk                   // DM pull-up detection status */
+#define STM32_GCCFG_PWRDWN_Pos           (16U)
+#define STM32_GCCFG_PWRDWN_Msk           (0x1UL << STM32_GCCFG_PWRDWN_Pos)        // 0x00010000 */
+#define STM32_GCCFG_PWRDWN               STM32_GCCFG_PWRDWN_Msk                   // Power down */
+#define STM32_GCCFG_BCDEN_Pos            (17U)
+#define STM32_GCCFG_BCDEN_Msk            (0x1UL << STM32_GCCFG_BCDEN_Pos)         // 0x00020000 */
+#define STM32_GCCFG_BCDEN                STM32_GCCFG_BCDEN_Msk                    // Battery charging detector (BCD) enable */
+#define STM32_GCCFG_DCDEN_Pos            (18U)
+#define STM32_GCCFG_DCDEN_Msk            (0x1UL << STM32_GCCFG_DCDEN_Pos)         // 0x00040000 */
+#define STM32_GCCFG_DCDEN                STM32_GCCFG_DCDEN_Msk                    // Data contact detection (DCD) mode enable*/
+#define STM32_GCCFG_PDEN_Pos             (19U)
+#define STM32_GCCFG_PDEN_Msk             (0x1UL << STM32_GCCFG_PDEN_Pos)          // 0x00080000 */
+#define STM32_GCCFG_PDEN                 STM32_GCCFG_PDEN_Msk                     // Primary detection (PD) mode enable*/
+#define STM32_GCCFG_SDEN_Pos             (20U)
+#define STM32_GCCFG_SDEN_Msk             (0x1UL << STM32_GCCFG_SDEN_Pos)          // 0x00100000 */
+#define STM32_GCCFG_SDEN                 STM32_GCCFG_SDEN_Msk                     // Secondary detection (SD) mode enable */
+#define STM32_GCCFG_VBDEN_Pos            (21U)
+#define STM32_GCCFG_VBDEN_Msk            (0x1UL << STM32_GCCFG_VBDEN_Pos)         // 0x00200000 */
+#define STM32_GCCFG_VBDEN                STM32_GCCFG_VBDEN_Msk                    // VBUS mode enable */
+#define STM32_GCCFG_OTGIDEN_Pos          (22U)
+#define STM32_GCCFG_OTGIDEN_Msk          (0x1UL << STM32_GCCFG_OTGIDEN_Pos)       // 0x00400000 */
+#define STM32_GCCFG_OTGIDEN              STM32_GCCFG_OTGIDEN_Msk                  // OTG Id enable */
+#define STM32_GCCFG_PHYHSEN_Pos          (23U)
+#define STM32_GCCFG_PHYHSEN_Msk          (0x1UL << STM32_GCCFG_PHYHSEN_Pos)       // 0x00800000 */
+#define STM32_GCCFG_PHYHSEN              STM32_GCCFG_PHYHSEN_Msk                  // HS PHY enable */
 
 /********************  Bit definition for DEACHINTMSK register  ********************/
 #define DEACHINTMSK_IEP1INTM_Pos         (1U)

From 49aa69a301abfc86e1182d329c1f3b586cdcf204 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Oct 2021 23:57:48 +0700
Subject: [PATCH 0611/2085] update bcm dcd

---
 src/device/dcd_attr.h                         |  2 +-
 src/portable/broadcom/synopsys/dcd_synopsys.c | 18 +++++++++---------
 src/portable/st/synopsys/dcd_synopsys.c       |  2 +-
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 61f31e38a..90f3a526a 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -181,7 +181,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   4
 
 //------------- Broadcom -------------//
-#elif TU_CHECK_MCU(BCM2711)
+#elif TU_CHECK_MCU(OPT_MCU_BCM2711)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 #else
diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c
index 87150f683..041158871 100644
--- a/src/portable/broadcom/synopsys/dcd_synopsys.c
+++ b/src/portable/broadcom/synopsys/dcd_synopsys.c
@@ -37,9 +37,9 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if TUSB_OPT_DEVICE_ENABLED &&                                          \
-    ( (CFG_TUSB_MCU == OPT_MCU_BCM2711 )                           \
-    )
+#if TUSB_OPT_DEVICE_ENABLED &&         \
+    (CFG_TUSB_MCU == OPT_MCU_BCM2711 ) \
+
 
 // EP_MAX       : Max number of bi-directional endpoints including EP0
 // EP_FIFO_SIZE : Size of dedicated USB SRAM
@@ -656,10 +656,10 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   TU_ASSERT(epnum < EP_MAX);
 
   xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = desc_edpt->wMaxPacketSize.size;
+  xfer->max_size = tu_edpt_packet_size(desc_edpt);
   xfer->interval = desc_edpt->bInterval;
 
-  uint16_t const fifo_size = (desc_edpt->wMaxPacketSize.size + 3) / 4; // Round up to next full word
+  uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word
 
   if(dir == TUSB_DIR_OUT)
   {
@@ -678,7 +678,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos)        |
         (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos)   |
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
-        (desc_edpt->wMaxPacketSize.size << USB_OTG_DOEPCTL_MPSIZ_Pos);
+        (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos);
 
     dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
   }
@@ -720,7 +720,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
         (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
         (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
         (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
-        (desc_edpt->wMaxPacketSize.size << USB_OTG_DIEPCTL_MPSIZ_Pos);
+        (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos);
 
     dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
   }
@@ -1010,7 +1010,7 @@ static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_
       if (xfer->ff)
       {
         // Ring buffer
-        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *) rx_fifo, bcnt);
+        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt);
       }
       else
       {
@@ -1130,7 +1130,7 @@ static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OT
           if (xfer->ff)
           {
             usb_fifo_t tx_fifo = FIFO_BASE(rhport, n);
-            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *) tx_fifo, packet_size);
+            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size);
           }
           else
           {
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 4e2bbd076..4782ead8c 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -370,7 +370,7 @@ static bool USB_HS_PHYCInit(void)
 {
   USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
 
-  // Enable LDO
+  // Enable LDO: Note STM32F72/3xx Reference Manual rev 3 June 2018 incorrectly defined this bit as Disabled !!
   usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
 
   // Wait until LDO ready

From 6a658007a5145147bd7435346f3617a7cda589b7 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@ftdichip.com>
Date: Wed, 27 Oct 2021 12:30:51 +0100
Subject: [PATCH 0612/2085] Changes to use ft90x-sdk as submodule or installed
 SDK from toolchain.

---
 hw/bsp/brtmm90x/family.mk                     | 57 ++++++++++++++-----
 .../ft9xx/{hardware => }/scripts/crt0.S       |  0
 .../ft9xx/{hardware => }/scripts/ldscript.ld  |  1 +
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c      | 11 ++--
 4 files changed, 50 insertions(+), 19 deletions(-)
 rename hw/mcu/bridgetek/ft9xx/{hardware => }/scripts/crt0.S (100%)
 rename hw/mcu/bridgetek/ft9xx/{hardware => }/scripts/ldscript.ld (97%)

diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index 211f97f1b..d47f4820c 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -1,11 +1,28 @@
-
+# GCC prefix for FT90X compile tools.
 CROSS_COMPILE = ft32-elf-
-DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/hardware
 SKIP_NANOLIB = 1
 
-# This is installed at "C:/Program Files(x86)/Bridgetek/FT9xx Toolchain/Toolchain/hardware"
-FT9XX_SDK = $(TOP)/hw/mcu/bridgetek/ft9xx/hardware
+# Set to use FT90X prebuilt libraries.
+FT90X_PREBUILT_LIBS = 1
+ifeq ($(FT90X_PREBUILT_LIBS),1)
+# If the FT90X toolchain is installed on Windows systems then the SDK 
+# include files and prebuilt libraries are at: %FT90X_TOOLCHAIN%/hardware
+FT9XX_SDK = $(FT90X_TOOLCHAIN)/hardware
+else
+# The submodule BRTSG-FOSS/ft90x-sdk contains header files and source
+# code for the Bridgetek SDK. This can be used instead of the prebuilt
+# library.
+DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/hardware
+# The SDK can be used to load specific files from the Bridgetek SDK.
+FT9XX_SDK = hw/mcu/bridgetek/ft9xx/hardware/Source
+endif
 
+# Add include files which are within the TinyUSB directory structure.
+INC += \
+	$(TOP)/hw/mcu/bridgetek/ft9xx/hardware/Source/include \
+	$(TOP)/$(BOARD_PATH)
+
+# Add required C Compiler flags for FT90X.
 CFLAGS += \
 	-D__FT900__ \
 	-fvar-tracking \
@@ -16,20 +33,34 @@ CFLAGS += \
 
 # lwip/src/core/raw.c:334:43: error: declaration of 'recv' shadows a global declaration
 CFLAGS += -Wno-error=shadow
-CFLAGS:=$(filter-out -Wcast-function-type,$(CFLAGS))
 
-# All source paths should be relative to the top level.
-LDINC += $(FT9XX_SDK)/lib/Release
-LIBS += -lft900
-LD_FILE = hw/mcu/bridgetek/ft9xx/hardware/scripts/ldscript.ld
+# Add include files outside the TinyUSB structure that are added manually.
+CFLAGS += -I"$(FT9XX_SDK)/include"
+
+# Set Linker flags.
+LD_FILE = hw/mcu/bridgetek/ft9xx/scripts/ldscript.ld
 LDFLAGS += $(addprefix -L,$(LDINC)) \
 	-Xlinker --entry=_start \
 	-Wl,-lc
 
+# Additional Source files for FT90X.
 SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c 
 
-#SRC_S += hw/mcu/bridgetek/ft9xx/hardware/scripts/crt0.S
+# Linker library.
+ifneq ($(FT90X_PREBUILT_LIBS),1)
+# Optionally add in files from the Bridgetek SDK instead of the prebuilt
+# library. These are the minimum required.
+SRC_C += $(FT9XX_SDK)/src/sys.c
+SRC_C += $(FT9XX_SDK)/src/interrupt.c
+SRC_C += $(FT9XX_SDK)/src/delay.c
+SRC_C += $(FT9XX_SDK)/src/timers.c
+SRC_C += $(FT9XX_SDK)/src/uart_simple.c
+SRC_C += $(FT9XX_SDK)/src/gpio.c
+else
+# Or if using the prebuilt libraries add them.
+LDFLAGS += -L"$(FT9XX_SDK)/lib"
+LIBS += -lft900
+endif
 
-INC += \
-	$(FT9XX_SDK)/include \
-	$(TOP)/$(BOARD_PATH)
+# Not required crt0 file for FT90X. Use compiler built-in file.
+#SRC_S += hw/mcu/bridgetek/ft9xx/scripts/crt0.S
diff --git a/hw/mcu/bridgetek/ft9xx/hardware/scripts/crt0.S b/hw/mcu/bridgetek/ft9xx/scripts/crt0.S
similarity index 100%
rename from hw/mcu/bridgetek/ft9xx/hardware/scripts/crt0.S
rename to hw/mcu/bridgetek/ft9xx/scripts/crt0.S
diff --git a/hw/mcu/bridgetek/ft9xx/hardware/scripts/ldscript.ld b/hw/mcu/bridgetek/ft9xx/scripts/ldscript.ld
similarity index 97%
rename from hw/mcu/bridgetek/ft9xx/hardware/scripts/ldscript.ld
rename to hw/mcu/bridgetek/ft9xx/scripts/ldscript.ld
index d1b4d46cd..987c2b2ba 100644
--- a/hw/mcu/bridgetek/ft9xx/hardware/scripts/ldscript.ld
+++ b/hw/mcu/bridgetek/ft9xx/scripts/ldscript.ld
@@ -9,6 +9,7 @@ MEMORY
 {
   flash     (rx)   : ORIGIN = 0,        LENGTH = __PMSIZE
   ram       (rw!x) : ORIGIN = 0x800000, LENGTH = __RAMSIZE
+  ehci_mmap (rw!x) : ORIGIN = 0x811000, LENGTH = 2K
 }
 SECTIONS
 {
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 09ca2904f..3235d0ef1 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -29,20 +29,19 @@
  * in https://brtchip.com/BRTSourceCodeLicenseAgreement
  */
 
+#include <stdint.h>
+#include <ft900.h>
+#include <registers/ft900_registers.h>
+
 #include "board.h"
 #include "bsp/board.h"
 #include "tusb_option.h"
 
 #if TUSB_OPT_DEVICE_ENABLED && \
-  (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X)
+  (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X) 
 
 #define USBD_USE_STREAMS
 
-#include <stdint.h>
-#include <errno.h>
-#include <ft900.h>
-#include <registers/ft900_registers.h>
-
 #include "device/dcd.h"
 
 //--------------------------------------------------------------------+

From 7def38005853df94a61365c52cae27e8cba2cf81 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Oct 2021 12:52:18 +0700
Subject: [PATCH 0613/2085] support bcm2711 on pi4, enhance dcd init with utmi
 and ulpi hs phy

---
 hw/bsp/raspberrypi4/family.mk                 |   8 +-
 hw/bsp/stm32f7/boards/stm32f723disco/board.mk |   3 +
 hw/bsp/stm32f7/family.mk                      |   2 +-
 hw/bsp/stm32h7/family.mk                      |   2 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c         | 162 +++++++++---------
 src/portable/synopsys/dwc2/dwc2_bcm.h         |  72 ++++++++
 src/portable/synopsys/dwc2/dwc2_stm32.h       |  49 +++++-
 src/portable/synopsys/dwc2/dwc2_type.h        |  46 +++--
 8 files changed, 242 insertions(+), 102 deletions(-)
 create mode 100644 src/portable/synopsys/dwc2/dwc2_bcm.h

diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
index 0424b2154..b0326c056 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -16,8 +16,11 @@ CFLAGS += \
 	-mgeneral-regs-only \
 	-DCFG_TUSB_MCU=OPT_MCU_BCM2711
 
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=cast-qual
+
 SRC_C += \
-	src/portable/broadcom/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(MCU_DIR)/broadcom/gen/interrupt_handlers.c \
 	$(MCU_DIR)/broadcom/interrupts.c \
 	$(MCU_DIR)/broadcom/io.c \
@@ -39,3 +42,6 @@ SRC_S += $(MCU_DIR)/broadcom/boot.S
 
 $(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf
 	$(OBJCOPY) -O binary $^ $@
+
+flash: $(BUILD)/kernel8.img
+	@$(CP) $< /home/$(USER)/Documents/code/pi4_tinyusb/boot_cpy
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
index 8f05199d0..66d9ff8fb 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
@@ -10,3 +10,6 @@ SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
 
 # flash target using on-board stlink
 flash: flash-stlink
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f723ie
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index ead0c977a..8482e6dd2 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -34,7 +34,7 @@ endif
 CFLAGS += -Wno-error=shadow -Wno-error=cast-align
 
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index e35e75610..6a257e22d 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -30,7 +30,7 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 
 # All source paths should be relative to the top level.
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 58305838f..0d2766c38 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -31,7 +31,7 @@
 #include "device/dcd_attr.h"
 
 #if TUSB_OPT_DEVICE_ENABLED && \
-    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) )
+    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103, OPT_MCU_BCM2711) )
 
 #include "device/dcd.h"
 #include "dwc2_type.h"
@@ -42,6 +42,8 @@
   #include "dwc2_esp32.h"
 #elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
   #include "dwc2_gd32.h"
+#elif TU_CHECK_MCU(OPT_MCU_BCM2711)
+  #include "dwc2_bcm.h"
 #else
   #error "Unsupported MCUs"
 #endif
@@ -185,7 +187,7 @@ static void bus_reset(uint8_t rhport)
   _allocated_fifo_words_tx = 16;
 
   // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  dwc2->dieptxf0 = (16 << TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+  dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
   dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
@@ -226,47 +228,6 @@ static void set_speed(uint8_t rhport, tusb_speed_t speed)
   dwc2->dcfg |= (bitvalue << DCFG_DSPD_Pos);
 }
 
-#if defined(USB_HS_PHYC)
-static bool USB_HS_PHYCInit(void)
-{
-  USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
-
-  // Enable LDO
-  usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
-
-  // Wait until LDO ready
-  while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
-
-  uint32_t phyc_pll = 0;
-
-  // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
-  switch ( HSE_VALUE )
-  {
-    case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
-    case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
-    case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
-    case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
-    case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
-    case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
-    default:
-      TU_ASSERT(0);
-  }
-  usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
-
-  // Control the tuning interface of the High Speed PHY
-  // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
-  usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
-
-  // Enable PLL internal PHY
-  usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
-
-  // Original ST code has 2 ms delay for PLL stabilization.
-  // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
-
-  return true;
-}
-#endif
-
 static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
 {
   (void) rhport;
@@ -369,7 +330,7 @@ void print_dwc2_info(dwc2_regs_t * dwc2)
   TU_LOG_INT(1, hw_cfg3->synch_reset              );
   TU_LOG_INT(1, hw_cfg3->otg_adp_support          );
   TU_LOG_INT(1, hw_cfg3->otg_enable_hsic          );
-  TU_LOG_INT(1, hw_cfg3->otg_bc_support           );
+  TU_LOG_INT(1, hw_cfg3->battery_charger_support  );
   TU_LOG_INT(1, hw_cfg3->lpm_mode                 );
   TU_LOG_INT(1, hw_cfg3->total_fifo_size          );
 
@@ -395,57 +356,103 @@ void print_dwc2_info(dwc2_regs_t * dwc2)
   TU_LOG_INT(1, hw_cfg4->dma_dynamic               );
 }
 
+static void reset_core(dwc2_regs_t * dwc2)
+{
+  // reset core
+  dwc2->grstctl |= GRSTCTL_CSRST;
+
+  // wait for reset bit is cleared
+  // TODO version 4.20a should wait for RESET DONE mask
+  while (dwc2->grstctl & GRSTCTL_CSRST) { }
+
+  // wait for AHB master IDLE
+  while ( !(dwc2->grstctl & GRSTCTL_AHBIDL) ) { }
+
+  // wait for device mode ?
+}
+
 void dcd_init (uint8_t rhport)
 {
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
-  // Check Synopsys ID
-  uint32_t const gsnpsid = dwc2->gsnpsid & 0xffff0000u;
+  // Check Synopsys ID, failed if controller is not enabled
+  uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
   TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, );
 
   print_dwc2_info(dwc2);
 
-  // No HNP/SRP (no OTG support), program timeout later.
-  if ( rhport == 1 )
+  // Force device mode
+  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
+
+  uint32_t const hs_phy_type = dwc2->ghwcfg2_bm.hs_phy_type;
+
+  if( !TUD_OPT_HIGH_SPEED || hs_phy_type == HS_PHY_TYPE_NONE)
   {
-    // On selected MCUs HS port1 can be used with external PHY via ULPI interface
-#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED
-    // deactivate internal PHY
+    // max speed is full or core does not support highspeed
+    TU_LOG2("Fullspeed PHY init\r\n");
+
+    // Select FS PHY
+    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
+
+    // Reset core after selecting PHY
+    reset_core(dwc2);
+
+    #if defined(DCD_ATTR_DWC2_STM32)
+    // activate FS PHY on stm32
+    dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
+    #endif
+  }else
+  {
+    // Highspeed mode
+
+    #if defined(DCD_ATTR_DWC2_STM32)
+    // Disable STM32 FS PHY
     dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+    #endif
 
-    // Init The UTMI Interface
-    dwc2->gusbcfg &= ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL);
+    uint32_t gusbcfg = dwc2->gusbcfg;
 
-    // Select default internal VBUS Indicator and Drive for ULPI
-    dwc2->gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
-#else
-    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
-#endif
+    // De-select FS PHY
+    gusbcfg &= ~GUSBCFG_PHYSEL;
 
-#if defined(USB_HS_PHYC)
-    // Highspeed with embedded UTMI PHYC
+    if (hs_phy_type == HS_PHY_TYPE_ULPI)
+    {
+      TU_LOG2("Highspeed ULPI PHY init\r\n");
 
-    // Select UTMI Interface
-    dwc2->gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL;
-    dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
+      // Select ULPI
+      gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
 
-    // Enables control of a High Speed USB PHY
-    USB_HS_PHYCInit();
-#endif
-  } else
-  {
-    // Enable internal PHY
-    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
+      // ULPI 8-bit interface, single data rate
+      gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
+
+      // default internal VBUS Indicator and Drive
+      gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
+
+      // Disable FS/LS ULPI
+      gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
+    }else
+    {
+      TU_LOG2("Highspeed UTMI+ PHY init\r\n");
+
+      // Select UTMI+ with 8-bit interface
+      gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
+
+      // Set 16-bit interface if supported
+      if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
+
+      #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC)
+      dwc2_stm32_utmi_phy_init(dwc2);
+      #endif
+    }
+
+    dwc2->gusbcfg = gusbcfg;
+
+    // Reset core after selecting PHY
+    reset_core(dwc2);
   }
 
-  // Reset core after selecting PHYst
-  // Wait AHB IDLE, reset then wait until it is cleared
-  while ((dwc2->grstctl & GRSTCTL_AHBIDL) == 0U) {}
-  dwc2->grstctl |= GRSTCTL_CSRST;
-  while ((dwc2->grstctl & GRSTCTL_CSRST) == GRSTCTL_CSRST) {}
-
   // Restart PHY clock
   dwc2->pcgctrl = 0;
 
@@ -463,9 +470,6 @@ void dcd_init (uint8_t rhport)
 
   set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
 
-  // Enable internal USB transceiver, unless using HS core (port 1) with external PHY.
-  if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
-
   dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
                    GINTMSK_WUIM   | GINTMSK_RXFLVLM;
 
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
new file mode 100644
index 000000000..da1f23ae0
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -0,0 +1,72 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_DWC2_BCM_H_
+#define _TUSB_DWC2_BCM_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "broadcom/interrupts.h"
+
+#define DWC2_REG_BASE       0xFE980000UL
+#define DWC2_EP_MAX         8
+#define DWC2_EP_FIFO_SIZE   4096
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  BP_EnableIRQ(USB_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  BP_DisableIRQ(USB_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+  // TODO implement later
+}
+
+static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
+{
+  // TODO implement later
+  (void) core;
+  (void) speed;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 236936d66..b77cda2ca 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -113,14 +113,14 @@ static inline void dwc2_remote_wakeup_delay(void)
 }
 
 // Set turn-around timeout according to link speed
-static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
+static inline void dwc2_set_turnaround(dwc2_regs_t * dwc2, tusb_speed_t speed)
 {
-  core->gusbcfg &= ~GUSBCFG_TRDT;
+  dwc2->gusbcfg &= ~GUSBCFG_TRDT;
 
   if ( speed == TUSB_SPEED_HIGH )
   {
     // Use fixed 0x09 for Highspeed
-    core->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos);
+    dwc2->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos);
   }
   else
   {
@@ -149,11 +149,52 @@ static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
       turnaround = 0xFU;
 
     // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    core->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos);
+    dwc2->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos);
   }
 }
 
+#if defined(USB_HS_PHYC)
+static inline void dwc2_stm32_utmi_phy_init(dwc2_regs_t * dwc2)
+{
+  USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
 
+  // Enable UTMI HS PHY
+  dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
+
+  // Enable LDO
+  usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
+
+  // Wait until LDO ready
+  while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
+
+  uint32_t phyc_pll = 0;
+
+  // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
+  switch ( HSE_VALUE )
+  {
+    case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
+    case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
+    case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
+    case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
+    case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
+    case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
+    default:
+      TU_ASSERT(false, );
+  }
+  usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
+
+  // Control the tuning interface of the High Speed PHY
+  // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
+  usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
+
+  // Enable PLL internal PHY
+  usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
+
+  // Original ST code has 2 ms delay for PLL stabilization.
+  // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
+}
+
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 113f99180..5ded366d7 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -58,6 +58,13 @@ typedef struct
 } HS_PHYC_GlobalTypeDef;
 #endif
 
+enum {
+  HS_PHY_TYPE_NONE = 0  ,
+  HS_PHY_TYPE_UTMI      , // internal PHY (mostly)
+  HS_PHY_TYPE_ULPI      , // external PHY
+  HS_PHY_TYPE_UTMI_ULPI ,
+};
+
 typedef struct TU_ATTR_PACKED
 {
   uint32_t op_mode                  : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
@@ -90,7 +97,7 @@ typedef struct TU_ATTR_PACKED
   uint32_t synch_reset              : 1;  // 0: async reset | 1: synch reset
   uint32_t otg_adp_support          : 1;  // ADP logic is present along with HSOTG controller
   uint32_t otg_enable_hsic          : 1;  // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC
-  uint32_t otg_bc_support           : 1;  // support battery charger
+  uint32_t battery_charger_support  : 1;  // support battery charger
   uint32_t lpm_mode                 : 1;  // LPC mode
   uint32_t total_fifo_size          : 16; // DFIFO depth value in terms of 32-bit words
 }dwc2_ghwcfg3_t;
@@ -494,6 +501,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos)          // 0x00000100 */
 #define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk                     // Periodic TxFIFO empty level */
 
+#define GSNPSID_ID_MASK			             TU_GENMASK(31, 16)
+
 /********************  Bit definition for GUSBCFG register  ********************/
 #define GUSBCFG_TOCAL_Pos                (0U)
 #define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             // 0x00000007 */
@@ -501,15 +510,16 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GUSBCFG_TOCAL_0                  (0x1UL << GUSBCFG_TOCAL_Pos)             // 0x00000001 */
 #define GUSBCFG_TOCAL_1                  (0x2UL << GUSBCFG_TOCAL_Pos)             // 0x00000002 */
 #define GUSBCFG_TOCAL_2                  (0x4UL << GUSBCFG_TOCAL_Pos)             // 0x00000004 */
-#define GUSBCFG_PHYIF_Pos                (3U)
-#define GUSBCFG_PHYIF_Msk                (0x1UL << GUSBCFG_PHYIF_Pos)             // 0x00000008 */
-#define GUSBCFG_PHYIF                    GUSBCFG_PHYIF_Msk                        // PHY Interface (PHYIf) */
+#define GUSBCFG_PHYIF16_Pos              (3U)
+#define GUSBCFG_PHYIF16_Msk              (0x1UL << GUSBCFG_PHYIF16_Pos)             // 0x00000008 */
+#define GUSBCFG_PHYIF16                  GUSBCFG_PHYIF16_Msk                        // PHY Interface (PHYIf) */
 #define GUSBCFG_ULPI_UTMI_SEL_Pos        (4U)
 #define GUSBCFG_ULPI_UTMI_SEL_Msk        (0x1UL << GUSBCFG_ULPI_UTMI_SEL_Pos)     // 0x00000010 */
 #define GUSBCFG_ULPI_UTMI_SEL            GUSBCFG_ULPI_UTMI_SEL_Msk                // ULPI or UTMI+ Select (ULPI_UTMI_Sel) */
 #define GUSBCFG_PHYSEL_Pos               (6U)
 #define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            // 0x00000040 */
 #define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define GUSBCFG_DDRSEL			             TU_BIT(7)                                // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
 #define GUSBCFG_SRPCAP_Pos               (8U)
 #define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            // 0x00000100 */
 #define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       // SRP-capable */
@@ -587,6 +597,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           // 0x00000100 */
 #define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           // 0x00000200 */
 #define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           // 0x00000400 */
+#define GRSTCTL_CSFTRST_DONE_Pos		     (29)
+#define GRSTCTL_CSFTRST_DONE		         (1u << GRSTCTL_CSFTRST_DONE_Pos)         // Reset Done, only available from v4.20a
 #define GRSTCTL_DMAREQ_Pos               (30U)
 #define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            // 0x40000000 */
 #define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       // DMA request signal */
@@ -898,6 +910,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DAINTMSK_OEPM_Msk                (0xFFFFUL << DAINTMSK_OEPM_Pos)          // 0xFFFF0000 */
 #define DAINTMSK_OEPM                    DAINTMSK_OEPM_Msk                        // OUT EP interrupt mask bits */
 
+#if 0
 /********************  Bit definition for OTG register  ********************/
 #define CHNUM_Pos                        (0U)
 #define CHNUM_Msk                        (0xFUL << CHNUM_Pos)                     // 0x0000000F */
@@ -939,6 +952,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define FRMNUM_1                         (0x2UL << FRMNUM_Pos)                    // 0x00400000 */
 #define FRMNUM_2                         (0x4UL << FRMNUM_Pos)                    // 0x00800000 */
 #define FRMNUM_3                         (0x8UL << FRMNUM_Pos)                    // 0x01000000 */
+#endif
 
 /********************  Bit definition for GRXFSIZ register  ********************/
 #define GRXFSIZ_RXFD_Pos                 (0U)
@@ -951,18 +965,18 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DVBUSDIS_VBUSDT                  DVBUSDIS_VBUSDT_Msk                      // Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define NPTXFSA_Pos                      (0U)
-#define NPTXFSA_Msk                      (0xFFFFUL << NPTXFSA_Pos)                // 0x0000FFFF */
-#define NPTXFSA                          NPTXFSA_Msk                              // Nonperiodic transmit RAM start address */
-#define NPTXFD_Pos                       (16U)
-#define NPTXFD_Msk                       (0xFFFFUL << NPTXFD_Pos)                 // 0xFFFF0000 */
-#define NPTXFD                           NPTXFD_Msk                               // Nonperiodic TxFIFO depth               */
-#define TX0FSA_Pos                       (0U)
-#define TX0FSA_Msk                       (0xFFFFUL << TX0FSA_Pos)                 // 0x0000FFFF */
-#define TX0FSA                           TX0FSA_Msk                               // Endpoint 0 transmit RAM start address  */
-#define TX0FD_Pos                        (16U)
-#define TX0FD_Msk                        (0xFFFFUL << TX0FD_Pos)                  // 0xFFFF0000 */
-#define TX0FD                            TX0FD_Msk                                // Endpoint 0 TxFIFO depth                */
+#define GNPTXFSIZ_NPTXFSA_Pos            (0U)
+#define GNPTXFSIZ_NPTXFSA_Msk            (0xFFFFUL << NPTXFSA_Pos)                // 0x0000FFFF */
+#define GNPTXFSIZ_NPTXFSA                GNPTXFSIZ_NPTXFSA_Msk                    // Nonperiodic transmit RAM start address */
+#define GNPTXFSIZ_NPTXFD_Pos             (16U)
+#define GNPTXFSIZ_NPTXFD_Msk             (0xFFFFUL << NPTXFD_Pos)                 // 0xFFFF0000 */
+#define GNPTXFSIZ_NPTXFD                 GNPTXFSIZ_NPTXFD_Msk                     // Nonperiodic TxFIFO depth               */
+#define DIEPTXF0_TX0FSA_Pos              (0U)
+#define DIEPTXF0_TX0FSA_Msk              (0xFFFFUL << TX0FSA_Pos)                 // 0x0000FFFF */
+#define DIEPTXF0_TX0FSA                  DIEPTXF0_TX0FSA_Msk                      // Endpoint 0 transmit RAM start address  */
+#define DIEPTXF0_TX0FD_Pos               (16U)
+#define DIEPTXF0_TX0FD_Msk               (0xFFFFUL << TX0FD_Pos)                  // 0xFFFF0000 */
+#define DIEPTXF0_TX0FD                   DIEPTXF0_TX0FD_Msk                       // Endpoint 0 TxFIFO depth                */
 
 /********************  Bit definition for DVBUSPULSE register  ********************/
 #define DVBUSPULSE_DVBUSP_Pos            (0U)

From 6c67fc412516950622a13fb34ddc10b64b9b3843 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 29 Oct 2021 00:53:30 +0700
Subject: [PATCH 0614/2085] correctly init hs phy for bcm

---
 examples/device/cdc_msc/src/tusb_config.h     |   5 +-
 .../device/hid_composite/src/tusb_config.h    |   4 +-
 src/common/tusb_types.h                       |   4 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c         | 221 ++++++++++--------
 src/portable/synopsys/dwc2/dwc2_type.h        | 164 ++++++-------
 5 files changed, 208 insertions(+), 190 deletions(-)

diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index a3802f536..499966cb4 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -47,9 +47,8 @@
 // RHPort max operational speed can defined by board.mk
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X || \
-       CFG_TUSB_MCU == OPT_MCU_BCM2711)
+  #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
+      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index 868424e6d..8fa5e5cd4 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -47,8 +47,8 @@
 // RHPort max operational speed can defined by board.mk
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
+  #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
+      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 233def466..5b26f5aec 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -47,8 +47,8 @@
 typedef enum
 {
   TUSB_SPEED_FULL = 0,
-  TUSB_SPEED_LOW     ,
-  TUSB_SPEED_HIGH,
+  TUSB_SPEED_LOW  = 1,
+  TUSB_SPEED_HIGH = 2,
   TUSB_SPEED_INVALID = 0xff,
 }tusb_speed_t;
 
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 0d2766c38..ce9b58e03 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -199,35 +199,6 @@ static void bus_reset(uint8_t rhport)
   dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT;
 }
 
-
-static tusb_speed_t get_speed(uint8_t rhport)
-{
-  (void) rhport;
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  uint32_t const enum_spd = (dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos;
-  return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
-}
-
-static void set_speed(uint8_t rhport, tusb_speed_t speed)
-{
-  uint32_t bitvalue;
-
-  if ( rhport == 1 )
-  {
-    bitvalue = (TUSB_SPEED_HIGH == speed ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
-  }
-  else
-  {
-    bitvalue = DCD_FULL_SPEED;
-  }
-
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-
-  // Clear and set speed bits
-  dwc2->dcfg &= ~(3 << DCFG_DSPD_Pos);
-  dwc2->dcfg |= (bitvalue << DCFG_DSPD_Pos);
-}
-
 static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
 {
   (void) rhport;
@@ -371,6 +342,99 @@ static void reset_core(dwc2_regs_t * dwc2)
   // wait for device mode ?
 }
 
+static bool has_hs_phy(dwc2_regs_t * dwc2)
+{
+  return TUD_OPT_HIGH_SPEED && dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
+}
+
+static void phy_fs_init(dwc2_regs_t * dwc2)
+{
+  TU_LOG1("Fullspeed PHY init\r\n");
+
+  // Select FS PHY
+  dwc2->gusbcfg |= GUSBCFG_PHYSEL;
+
+  // Reset core after selecting PHY
+  reset_core(dwc2);
+
+  // set turn around
+  // The values above are calculated for the minimum AHB frequency of 30 MHz. USB turnaround
+  // time is critical for certification where long cables and 5-Hubs are used, so if
+  // you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
+  // these bits can be programmed to a larger value.
+  dwc2_set_turnaround(dwc2, TUSB_SPEED_FULL);
+
+  // set max speed
+  dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
+
+  #if defined(DCD_ATTR_DWC2_STM32)
+  // activate FS PHY on stm32
+  dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
+  #endif
+}
+
+static void phy_hs_init(dwc2_regs_t * dwc2)
+{
+  uint32_t gusbcfg = dwc2->gusbcfg;
+
+  // De-select FS PHY
+  gusbcfg &= ~GUSBCFG_PHYSEL;
+
+  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI)
+  {
+    TU_LOG1("Highspeed ULPI PHY init\r\n");
+
+    // Select ULPI
+    gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
+
+    // ULPI 8-bit interface, single data rate
+    gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
+
+    // default internal VBUS Indicator and Drive
+    gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
+
+    // Disable FS/LS ULPI
+    gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
+  }else
+  {
+    TU_LOG1("Highspeed UTMI+ PHY init\r\n");
+
+    // Select UTMI+ with 8-bit interface
+    gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
+
+    // Set 16-bit interface if supported
+    if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
+
+    #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC)
+    dwc2_stm32_utmi_phy_init(dwc2);
+    #endif
+  }
+
+  // Apply config
+  dwc2->gusbcfg = gusbcfg;
+
+  #if defined(DCD_ATTR_DWC2_STM32)
+  // Disable STM32 FS PHY
+  dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+  #endif
+
+  // Reset core after selecting PHY
+  reset_core(dwc2);
+
+  // Set turn-around, must after core reset otherwise it will be clear
+  // 9 if UTMI interface is 8-bit, 5 if 16-bit
+  // The values above are calculated for the minimum AHB frequency of 30 MHz. USB turnaround
+  // time is critical for certification where long cables and 5-Hubs are used, so if
+  // you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
+  // these bits can be programmed to a larger value.
+  gusbcfg &= ~GUSBCFG_TRDT_Msk;
+  gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
+  dwc2->gusbcfg = gusbcfg; // Apply config
+
+  // Set max speed
+  dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos);
+}
+
 void dcd_init (uint8_t rhport)
 {
   // Programming model begins in the last section of the chapter on the USB
@@ -386,75 +450,28 @@ void dcd_init (uint8_t rhport)
   // Force device mode
   dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
 
-  uint32_t const hs_phy_type = dwc2->ghwcfg2_bm.hs_phy_type;
-
-  if( !TUD_OPT_HIGH_SPEED || hs_phy_type == HS_PHY_TYPE_NONE)
+  if( !has_hs_phy(dwc2) )
   {
-    // max speed is full or core does not support highspeed
-    TU_LOG2("Fullspeed PHY init\r\n");
-
-    // Select FS PHY
-    dwc2->gusbcfg |= GUSBCFG_PHYSEL;
-
-    // Reset core after selecting PHY
-    reset_core(dwc2);
-
-    #if defined(DCD_ATTR_DWC2_STM32)
-    // activate FS PHY on stm32
-    dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
-    #endif
+    // core does not support highspeed or hs-phy is not present
+    phy_fs_init(dwc2);
   }else
   {
-    // Highspeed mode
-
-    #if defined(DCD_ATTR_DWC2_STM32)
-    // Disable STM32 FS PHY
-    dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
-    #endif
-
-    uint32_t gusbcfg = dwc2->gusbcfg;
-
-    // De-select FS PHY
-    gusbcfg &= ~GUSBCFG_PHYSEL;
-
-    if (hs_phy_type == HS_PHY_TYPE_ULPI)
-    {
-      TU_LOG2("Highspeed ULPI PHY init\r\n");
-
-      // Select ULPI
-      gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
-
-      // ULPI 8-bit interface, single data rate
-      gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
-
-      // default internal VBUS Indicator and Drive
-      gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
-
-      // Disable FS/LS ULPI
-      gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
-    }else
-    {
-      TU_LOG2("Highspeed UTMI+ PHY init\r\n");
-
-      // Select UTMI+ with 8-bit interface
-      gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
-
-      // Set 16-bit interface if supported
-      if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
-
-      #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC)
-      dwc2_stm32_utmi_phy_init(dwc2);
-      #endif
-    }
-
-    dwc2->gusbcfg = gusbcfg;
-
-    // Reset core after selecting PHY
-    reset_core(dwc2);
+    // Highspeed
+    phy_hs_init(dwc2);
   }
 
+	/* Set HS/FS Timeout Calibration to 7 (max available value).
+	 * The number of PHY clocks that the application programs in
+	 * this field is added to the high/full speed interpacket timeout
+	 * duration in the core to account for any additional delays
+	 * introduced by the PHY. This can be required, because the delay
+	 * introduced by the PHY in generating the linestate condition
+	 * can vary from one PHY to another.
+	 */
+  // dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
+
   // Restart PHY clock
-  dwc2->pcgctrl = 0;
+  dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
 
   // Clear all interrupts
   dwc2->gintsts |= dwc2->gintsts;
@@ -468,8 +485,6 @@ void dcd_init (uint8_t rhport)
   // (non zero-length packet), send STALL back and discard.
   dwc2->dcfg |= DCFG_NZLSOHSK;
 
-  set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL);
-
   dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
                    GINTMSK_WUIM   | GINTMSK_RXFLVLM;
 
@@ -1088,9 +1103,23 @@ void dcd_int_handler(uint8_t rhport)
 
     dwc2->gintsts = GINTSTS_ENUMDNE;
 
-    tusb_speed_t const speed = get_speed(rhport);
+    tusb_speed_t speed;
+    switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos)
+    {
+      case DSTS_ENUMSPD_HS:
+        speed = TUSB_SPEED_HIGH;
+      break;
+
+      case DSTS_ENUMSPD_FS_HSPHY:
+      case DSTS_ENUMSPD_FS:
+        speed = TUSB_SPEED_FULL;
+      break;
+
+      case DSTS_ENUMSPD_LS:
+        speed = TUSB_SPEED_LOW;
+      break;
+    }
 
-    dwc2_set_turnaround(dwc2, speed);
     dcd_event_bus_reset(rhport, speed, true);
   }
 
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 5ded366d7..7e472310f 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -259,8 +259,8 @@ union {
            uint32_t reservedd00[64];  // D00..DFF
 
   //------------- Power Clock -------------//
-  volatile uint32_t pcgctrl;          // E00 Power and Clock Gating Control
-  volatile uint32_t pcgcctl1;         // E04
+  volatile uint32_t pcgctl;           // E00 Power and Clock Gating Control
+  volatile uint32_t pcgctl1;          // E04
            uint32_t reservede08[126]; // E08..FFF
 
   //------------- FIFOs -------------//
@@ -273,7 +273,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg   ) == 0x0800, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin   ) == 0x0900, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout  ) == 0x0B00, "incorrect size");
-TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctrl) == 0x0E00, "incorrect size");
+TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctl ) == 0x0E00, "incorrect size");
 TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
 //--------------------------------------------------------------------+
@@ -346,39 +346,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define HCFG_FSLSS_Msk                   (0x1UL << HCFG_FSLSS_Pos)                // 0x00000004 */
 #define HCFG_FSLSS                       HCFG_FSLSS_Msk                           // FS- and LS-only support */
 
-/********************  Bit definition for DCFG register  ********************/
-#define DCFG_DSPD_Pos                    (0U)
-#define DCFG_DSPD_Msk                    (0x3UL << DCFG_DSPD_Pos)                 // 0x00000003 */
-#define DCFG_DSPD                        DCFG_DSPD_Msk                            // Device speed */
-#define DCFG_DSPD_0                      (0x1UL << DCFG_DSPD_Pos)                 // 0x00000001 */
-#define DCFG_DSPD_1                      (0x2UL << DCFG_DSPD_Pos)                 // 0x00000002 */
-#define DCFG_NZLSOHSK_Pos                (2U)
-#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             // 0x00000004 */
-#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        // Nonzero-length status OUT handshake */
-
-#define DCFG_DAD_Pos                     (4U)
-#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 // 0x000007F0 */
-#define DCFG_DAD                         DCFG_DAD_Msk                             // Device address */
-#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 // 0x00000010 */
-#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 // 0x00000020 */
-#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 // 0x00000040 */
-#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 // 0x00000080 */
-#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 // 0x00000100 */
-#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 // 0x00000200 */
-#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 // 0x00000400 */
-
-#define DCFG_PFIVL_Pos                   (11U)
-#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                // 0x00001800 */
-#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           // Periodic (micro)frame interval */
-#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                // 0x00000800 */
-#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                // 0x00001000 */
-
-#define DCFG_PERSCHIVL_Pos               (24U)
-#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            // 0x03000000 */
-#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       // Periodic scheduling interval */
-#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            // 0x01000000 */
-#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            // 0x02000000 */
-
 /********************  Bit definition for PCGCR register  ********************/
 #define PCGCR_STPPCLK_Pos                (0U)
 #define PCGCR_STPPCLK_Msk                (0x1UL << PCGCR_STPPCLK_Pos)             // 0x00000001 */
@@ -413,6 +380,41 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GOTGINT_IDCHNG_Msk               (0x1UL << GOTGINT_IDCHNG_Pos)            // 0x00100000 */
 #define GOTGINT_IDCHNG                   GOTGINT_IDCHNG_Msk                       // Change in ID pin input value           */
 
+/********************  Bit definition for DCFG register  ********************/
+#define DCFG_DSPD_Pos                    (0U)
+#define DCFG_DSPD_Msk                    (0x3UL << DCFG_DSPD_Pos)                 // 0x00000003
+#define DCFG_DSPD_HS                     0    // Highspeed
+#define DCFG_DSPD_FS_HSPHY               1    // Fullspeed on HS PHY
+#define DCFG_DSPD_LS                     2    // Lowspeed
+#define DCFG_DSPD_FS                     3    // Fullspeed on FS PHY
+
+#define DCFG_NZLSOHSK_Pos                (2U)
+#define DCFG_NZLSOHSK_Msk                (0x1UL << DCFG_NZLSOHSK_Pos)             // 0x00000004 */
+#define DCFG_NZLSOHSK                    DCFG_NZLSOHSK_Msk                        // Nonzero-length status OUT handshake */
+
+#define DCFG_DAD_Pos                     (4U)
+#define DCFG_DAD_Msk                     (0x7FUL << DCFG_DAD_Pos)                 // 0x000007F0 */
+#define DCFG_DAD                         DCFG_DAD_Msk                             // Device address */
+#define DCFG_DAD_0                       (0x01UL << DCFG_DAD_Pos)                 // 0x00000010 */
+#define DCFG_DAD_1                       (0x02UL << DCFG_DAD_Pos)                 // 0x00000020 */
+#define DCFG_DAD_2                       (0x04UL << DCFG_DAD_Pos)                 // 0x00000040 */
+#define DCFG_DAD_3                       (0x08UL << DCFG_DAD_Pos)                 // 0x00000080 */
+#define DCFG_DAD_4                       (0x10UL << DCFG_DAD_Pos)                 // 0x00000100 */
+#define DCFG_DAD_5                       (0x20UL << DCFG_DAD_Pos)                 // 0x00000200 */
+#define DCFG_DAD_6                       (0x40UL << DCFG_DAD_Pos)                 // 0x00000400 */
+
+#define DCFG_PFIVL_Pos                   (11U)
+#define DCFG_PFIVL_Msk                   (0x3UL << DCFG_PFIVL_Pos)                // 0x00001800 */
+#define DCFG_PFIVL                       DCFG_PFIVL_Msk                           // Periodic (micro)frame interval */
+#define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                // 0x00000800 */
+#define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                // 0x00001000 */
+
+#define DCFG_PERSCHIVL_Pos               (24U)
+#define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            // 0x03000000 */
+#define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       // Periodic scheduling interval */
+#define DCFG_PERSCHIVL_0                 (0x1UL << DCFG_PERSCHIVL_Pos)            // 0x01000000 */
+#define DCFG_PERSCHIVL_1                 (0x2UL << DCFG_PERSCHIVL_Pos)            // 0x02000000 */
+
 /********************  Bit definition for DCTL register  ********************/
 #define DCTL_RWUSIG_Pos                  (0U)
 #define DCTL_RWUSIG_Msk                  (0x1UL << DCTL_RWUSIG_Pos)               // 0x00000001 */
@@ -466,12 +468,15 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DSTS_SUSPSTS_Pos                 (0U)
 #define DSTS_SUSPSTS_Msk                 (0x1UL << DSTS_SUSPSTS_Pos)              // 0x00000001 */
 #define DSTS_SUSPSTS                     DSTS_SUSPSTS_Msk                         // Suspend status   */
-
 #define DSTS_ENUMSPD_Pos                 (1U)
 #define DSTS_ENUMSPD_Msk                 (0x3UL << DSTS_ENUMSPD_Pos)              // 0x00000006 */
 #define DSTS_ENUMSPD                     DSTS_ENUMSPD_Msk                         // Enumerated speed */
-#define DSTS_ENUMSPD_0                   (0x1UL << DSTS_ENUMSPD_Pos)              // 0x00000002 */
-#define DSTS_ENUMSPD_1                   (0x2UL << DSTS_ENUMSPD_Pos)              // 0x00000004 */
+#define DSTS_ENUMSPD_HS                  0    // Highspeed
+#define DSTS_ENUMSPD_FS_HSPHY            1    // Fullspeed on HS PHY
+#define DSTS_ENUMSPD_LS                  2    // Lowspeed
+#define DSTS_ENUMSPD_FS                  3    // Fullspeed on FS PHY
+
+
 #define DSTS_EERR_Pos                    (3U)
 #define DSTS_EERR_Msk                    (0x1UL << DSTS_EERR_Pos)                 // 0x00000008 */
 #define DSTS_EERR                        DSTS_EERR_Msk                            // Erratic error     */
@@ -501,15 +506,12 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GAHBCFG_PTXFELVL_Msk             (0x1UL << GAHBCFG_PTXFELVL_Pos)          // 0x00000100 */
 #define GAHBCFG_PTXFELVL                 GAHBCFG_PTXFELVL_Msk                     // Periodic TxFIFO empty level */
 
-#define GSNPSID_ID_MASK			             TU_GENMASK(31, 16)
+#define GSNPSID_ID_MASK                 TU_GENMASK(31, 16)
 
 /********************  Bit definition for GUSBCFG register  ********************/
 #define GUSBCFG_TOCAL_Pos                (0U)
 #define GUSBCFG_TOCAL_Msk                (0x7UL << GUSBCFG_TOCAL_Pos)             // 0x00000007 */
 #define GUSBCFG_TOCAL                    GUSBCFG_TOCAL_Msk                        // FS timeout calibration */
-#define GUSBCFG_TOCAL_0                  (0x1UL << GUSBCFG_TOCAL_Pos)             // 0x00000001 */
-#define GUSBCFG_TOCAL_1                  (0x2UL << GUSBCFG_TOCAL_Pos)             // 0x00000002 */
-#define GUSBCFG_TOCAL_2                  (0x4UL << GUSBCFG_TOCAL_Pos)             // 0x00000004 */
 #define GUSBCFG_PHYIF16_Pos              (3U)
 #define GUSBCFG_PHYIF16_Msk              (0x1UL << GUSBCFG_PHYIF16_Pos)             // 0x00000008 */
 #define GUSBCFG_PHYIF16                  GUSBCFG_PHYIF16_Msk                        // PHY Interface (PHYIf) */
@@ -519,7 +521,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GUSBCFG_PHYSEL_Pos               (6U)
 #define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            // 0x00000040 */
 #define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define GUSBCFG_DDRSEL			             TU_BIT(7)                                // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
+#define GUSBCFG_DDRSEL                TU_BIT(7)                                // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
 #define GUSBCFG_SRPCAP_Pos               (8U)
 #define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            // 0x00000100 */
 #define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       // SRP-capable */
@@ -597,8 +599,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GRSTCTL_TXFNUM_2                 (0x04UL << GRSTCTL_TXFNUM_Pos)           // 0x00000100 */
 #define GRSTCTL_TXFNUM_3                 (0x08UL << GRSTCTL_TXFNUM_Pos)           // 0x00000200 */
 #define GRSTCTL_TXFNUM_4                 (0x10UL << GRSTCTL_TXFNUM_Pos)           // 0x00000400 */
-#define GRSTCTL_CSFTRST_DONE_Pos		     (29)
-#define GRSTCTL_CSFTRST_DONE		         (1u << GRSTCTL_CSFTRST_DONE_Pos)         // Reset Done, only available from v4.20a
+#define GRSTCTL_CSFTRST_DONE_Pos       (29)
+#define GRSTCTL_CSFTRST_DONE           (1u << GRSTCTL_CSFTRST_DONE_Pos)         // Reset Done, only available from v4.20a
 #define GRSTCTL_DMAREQ_Pos               (30U)
 #define GRSTCTL_DMAREQ_Msk               (0x1UL << GRSTCTL_DMAREQ_Pos)            // 0x40000000 */
 #define GRSTCTL_DMAREQ                   GRSTCTL_DMAREQ_Msk                       // DMA request signal */
@@ -1672,48 +1674,36 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DOEPTSIZ_STUPCNT_0               (0x1UL << DOEPTSIZ_STUPCNT_Pos)          // 0x20000000 */
 #define DOEPTSIZ_STUPCNT_1               (0x2UL << DOEPTSIZ_STUPCNT_Pos)          // 0x40000000 */
 
-/********************  Bit definition for PCGCCTL register  ********************/
-#define PCGCCTL_STOPCLK_Pos              (0U)
-#define PCGCCTL_STOPCLK_Msk              (0x1UL << PCGCCTL_STOPCLK_Pos)           // 0x00000001 */
-#define PCGCCTL_STOPCLK                  PCGCCTL_STOPCLK_Msk                      // SETUP packet count */
-#define PCGCCTL_GATECLK_Pos              (1U)
-#define PCGCCTL_GATECLK_Msk              (0x1UL << PCGCCTL_GATECLK_Pos)           // 0x00000002 */
-#define PCGCCTL_GATECLK                  PCGCCTL_GATECLK_Msk                      //Bit 0 */
-#define PCGCCTL_PHYSUSP_Pos              (4U)
-#define PCGCCTL_PHYSUSP_Msk              (0x1UL << PCGCCTL_PHYSUSP_Pos)           // 0x00000010 */
-#define PCGCCTL_PHYSUSP                  PCGCCTL_PHYSUSP_Msk                      //Bit 1 */
+/********************  Bit definition for PCGCTL register  ********************/
+#define PCGCTL_IF_DEV_MODE              TU_BIT(31)
+#define PCGCTL_P2HD_PRT_SPD_MASK        (0x3ul << 29)
+#define PCGCTL_P2HD_PRT_SPD_SHIFT       29
+#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK   (0x3ul << 27)
+#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT  27
+#define PCGCTL_MAC_DEV_ADDR_MASK        (0x7ful << 20)
+#define PCGCTL_MAC_DEV_ADDR_SHIFT       20
+#define PCGCTL_MAX_TERMSEL              TU_BIT(19)
+#define PCGCTL_MAX_XCVRSELECT_MASK      (0x3ul << 17)
+#define PCGCTL_MAX_XCVRSELECT_SHIFT     17
+#define PCGCTL_PORT_POWER               TU_BIT(16)
+#define PCGCTL_PRT_CLK_SEL_MASK         (0x3ul << 14)
+#define PCGCTL_PRT_CLK_SEL_SHIFT        14
+#define PCGCTL_ESS_REG_RESTORED         TU_BIT(13)
+#define PCGCTL_EXTND_HIBER_SWITCH       TU_BIT(12)
+#define PCGCTL_EXTND_HIBER_PWRCLMP      TU_BIT(11)
+#define PCGCTL_ENBL_EXTND_HIBER         TU_BIT(10)
+#define PCGCTL_RESTOREMODE              TU_BIT(9)
+#define PCGCTL_RESETAFTSUSP             TU_BIT(8)
+#define PCGCTL_DEEP_SLEEP               TU_BIT(7)
+#define PCGCTL_PHY_IN_SLEEP             TU_BIT(6)
+#define PCGCTL_ENBL_SLEEP_GATING        TU_BIT(5)
+#define PCGCTL_RSTPDWNMODULE            TU_BIT(3)
+#define PCGCTL_PWRCLMP                  TU_BIT(2)
+#define PCGCTL_GATEHCLK                 TU_BIT(1)
+#define PCGCTL_STOPPCLK                 TU_BIT(0)
 
-/********************  Bit definition for USBPHYC_PLL1 register  ********************/
-#define HS_PHYC_PLL1_PLLEN_Pos                (0U)
-#define HS_PHYC_PLL1_PLLEN_Msk                (0x1UL << HS_PHYC_PLL1_PLLEN_Pos)   // 0x00000001 */
-#define HS_PHYC_PLL1_PLLEN                    HS_PHYC_PLL1_PLLEN_Msk              // Enable PLL */
-#define HS_PHYC_PLL1_PLLSEL_Pos               (1U)
-#define HS_PHYC_PLL1_PLLSEL_Msk               (0x7UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x0000000E */
-#define HS_PHYC_PLL1_PLLSEL                   HS_PHYC_PLL1_PLLSEL_Msk             // Controls PHY frequency operation selection */
-#define HS_PHYC_PLL1_PLLSEL_1                 (0x1UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x00000002 */
-#define HS_PHYC_PLL1_PLLSEL_2                 (0x2UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x00000004 */
-#define HS_PHYC_PLL1_PLLSEL_3                 (0x4UL << HS_PHYC_PLL1_PLLSEL_Pos)  // 0x00000008 */
-
-#define HS_PHYC_PLL1_PLLSEL_12MHZ             0x00000000U                                                       // PHY PLL1 input clock frequency 12 MHz   */
-#define HS_PHYC_PLL1_PLLSEL_12_5MHZ           HS_PHYC_PLL1_PLLSEL_1                                         // PHY PLL1 input clock frequency 12.5 MHz */
-#define HS_PHYC_PLL1_PLLSEL_16MHZ             (uint32_t)(HS_PHYC_PLL1_PLLSEL_1 | HS_PHYC_PLL1_PLLSEL_2) // PHY PLL1 input clock frequency 16 MHz   */
-#define HS_PHYC_PLL1_PLLSEL_24MHZ             HS_PHYC_PLL1_PLLSEL_3                                         // PHY PLL1 input clock frequency 24 MHz   */
-#define HS_PHYC_PLL1_PLLSEL_25MHZ             (uint32_t)(HS_PHYC_PLL1_PLLSEL_2 | HS_PHYC_PLL1_PLLSEL_3) // PHY PLL1 input clock frequency 25 MHz   */
-
-/********************  Bit definition for USBPHYC_LDO register  ********************/
-#define HS_PHYC_LDO_USED_Pos                 (0U)
-#define HS_PHYC_LDO_USED_Msk                 (0x1UL << HS_PHYC_LDO_USED_Pos) // 0x00000001 */
-#define HS_PHYC_LDO_USED                     HS_PHYC_LDO_USED_Msk      // Monitors the usage status of the PHY's LDO   */
-#define HS_PHYC_LDO_STATUS_Pos               (1U)
-#define HS_PHYC_LDO_STATUS_Msk               (0x1UL << HS_PHYC_LDO_STATUS_Pos) // 0x00000002 */
-#define HS_PHYC_LDO_STATUS                   HS_PHYC_LDO_STATUS_Msk    // Monitors the status of the PHY's LDO.        */
-#define HS_PHYC_LDO_DISABLE_Pos              (2U)
-#define HS_PHYC_LDO_DISABLE_Msk              (0x1UL << HS_PHYC_LDO_DISABLE_Pos) // 0x00000004 */
-#define HS_PHYC_LDO_DISABLE                  HS_PHYC_LDO_DISABLE_Msk    // Controls disable of the High Speed PHY's LDO */
-
-#define HS_PHYC_LDO_ENABLE_Pos               HS_PHYC_LDO_DISABLE_Pos
-#define HS_PHYC_LDO_ENABLE_Msk               HS_PHYC_LDO_DISABLE_Msk
-#define HS_PHYC_LDO_ENABLE                   HS_PHYC_LDO_DISABLE
+#define PCGCTL1_TIMER                   (0x3ul << 1)
+#define PCGCTL1_GATEEN                  TU_BIT(0)
 
 #ifdef __cplusplus
  }

From 8e95b807f7250ec759389a4b0551f90419d14ac6 Mon Sep 17 00:00:00 2001
From: Matt Johnston <matt@codeconstruct.com.au>
Date: Fri, 29 Oct 2021 12:53:07 +0800
Subject: [PATCH 0615/2085] samd21: Make LED_PIN and BUTTON_PIN optional

Some boards don't have them, just ignore
---
 hw/bsp/samd21/family.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index eb5b55863..10e40e3f0 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -73,12 +73,16 @@ void board_init(void)
   SysTick_Config(CONF_CPU_FREQUENCY / 1000);
 
   // Led init
+#ifdef LED_PIN
   gpio_set_pin_direction(LED_PIN, GPIO_DIRECTION_OUT);
   board_led_write(false);
+#endif
 
   // Button init
+#ifdef BUTTON_PIN
   gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
   gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP);
+#endif
 
 #if CFG_TUSB_OS  == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
@@ -119,12 +123,19 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
+  (void)state;
+#ifdef LED_PIN
   gpio_set_pin_level(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+#endif
 }
 
 uint32_t board_button_read(void)
 {
+#ifdef BUTTON_PIN
   return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
+#else
+  return 0;
+#endif
 }
 
 int board_uart_read(uint8_t* buf, int len)

From 660e8b8c887091e17323c361f25e804a5d06d6df Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 29 Oct 2021 16:08:19 +0700
Subject: [PATCH 0616/2085] skip snpsid check for gd32, abstract phyfs
 turnaround, set max timeout calibration.

still has issue with gd32 with msc (does work with running with rtt as
log).
---
 src/common/tusb_common.h                |   3 +
 src/portable/synopsys/dwc2/dcd_dwc2.c   | 193 ++++++++++++------------
 src/portable/synopsys/dwc2/dwc2_bcm.h   |   7 +-
 src/portable/synopsys/dwc2/dwc2_esp32.h |   8 +-
 src/portable/synopsys/dwc2/dwc2_gd32.h  |   8 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h |  57 +++----
 src/portable/synopsys/dwc2/dwc2_type.h  |  13 +-
 7 files changed, 143 insertions(+), 146 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index e62bcde12..9b9e2b007 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -111,6 +111,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t ui32) { return
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t ui32) { return TU_U32_BYTE1(ui32); }
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t ui32) { return TU_U32_BYTE0(ui32); }
 
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_high16(uint32_t ui32) { return (uint16_t) (ui32 >> 16); }
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_low16 (uint32_t ui32) { return (uint16_t) (ui32 & 0x0000ffffu); }
+
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t ui16) { return TU_U16_HIGH(ui16); }
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t ui16) { return TU_U16_LOW(ui16); }
 
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index ce9b58e03..aad7e45cc 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -54,16 +54,8 @@
 
 #define DWC2_REG(_port)       ((dwc2_regs_t*) DWC2_REG_BASE)
 
-enum
-{
-  DCD_HIGH_SPEED        = 0, // Highspeed mode
-  DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY)
-  DCD_FULL_SPEED        = 3, // Full speed with internal PHY
-};
-
-// PHYSEL, ULPISEL
-// UTMI internal HS PHY
-// ULPI external HS PHY
+// Debug level for DWC2
+#define DWC2_DEBUG    1
 
 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
 
@@ -261,71 +253,73 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
+#if CFG_TUSB_DEBUG >= DWC2_DEBUG
 void print_dwc2_info(dwc2_regs_t * dwc2)
 {
   dwc2_ghwcfg2_t const * hw_cfg2 = &dwc2->ghwcfg2_bm;
   dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm;
   dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm;
 
-  TU_LOG_HEX(1, dwc2->guid);
-  TU_LOG_HEX(1, dwc2->gsnpsid);
-  TU_LOG_HEX(1, dwc2->ghwcfg1);
+  TU_LOG_HEX(DWC2_DEBUG, dwc2->guid);
+  TU_LOG_HEX(DWC2_DEBUG, dwc2->gsnpsid);
+  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg1);
 
   // HW configure 2
-  TU_LOG(1, "\r\n");
-  TU_LOG_HEX(1, dwc2->ghwcfg2);
-  TU_LOG_INT(1, hw_cfg2->op_mode                );
-  TU_LOG_INT(1, hw_cfg2->arch                   );
-  TU_LOG_INT(1, hw_cfg2->point2point            );
-  TU_LOG_INT(1, hw_cfg2->hs_phy_type            );
-  TU_LOG_INT(1, hw_cfg2->fs_phy_type            );
-  TU_LOG_INT(1, hw_cfg2->num_dev_ep             );
-  TU_LOG_INT(1, hw_cfg2->num_host_ch            );
-  TU_LOG_INT(1, hw_cfg2->period_channel_support );
-  TU_LOG_INT(1, hw_cfg2->enable_dynamic_fifo    );
-  TU_LOG_INT(1, hw_cfg2->mul_cpu_int            );
-  TU_LOG_INT(1, hw_cfg2->nperiod_tx_q_depth     );
-  TU_LOG_INT(1, hw_cfg2->host_period_tx_q_depth );
-  TU_LOG_INT(1, hw_cfg2->dev_token_q_depth      );
-  TU_LOG_INT(1, hw_cfg2->otg_enable_ic_usb      );
+  TU_LOG(DWC2_DEBUG, "\r\n");
+  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg2);
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->op_mode                );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->arch                   );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->point2point            );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->hs_phy_type            );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->fs_phy_type            );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_dev_ep             );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->num_host_ch            );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->period_channel_support );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->enable_dynamic_fifo    );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->mul_cpu_int            );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->nperiod_tx_q_depth     );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->host_period_tx_q_depth );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->dev_token_q_depth      );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg2->otg_enable_ic_usb      );
 
   // HW configure 3
-  TU_LOG(1, "\r\n");
-  TU_LOG_HEX(1, dwc2->ghwcfg3);
-  TU_LOG_INT(1, hw_cfg3->xfer_size_width          );
-  TU_LOG_INT(1, hw_cfg3->packet_size_width        );
-  TU_LOG_INT(1, hw_cfg3->otg_enable               );
-  TU_LOG_INT(1, hw_cfg3->i2c_enable               );
-  TU_LOG_INT(1, hw_cfg3->vendor_ctrl_itf          );
-  TU_LOG_INT(1, hw_cfg3->optional_feature_removed );
-  TU_LOG_INT(1, hw_cfg3->synch_reset              );
-  TU_LOG_INT(1, hw_cfg3->otg_adp_support          );
-  TU_LOG_INT(1, hw_cfg3->otg_enable_hsic          );
-  TU_LOG_INT(1, hw_cfg3->battery_charger_support  );
-  TU_LOG_INT(1, hw_cfg3->lpm_mode                 );
-  TU_LOG_INT(1, hw_cfg3->total_fifo_size          );
+  TU_LOG(DWC2_DEBUG, "\r\n");
+  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg3);
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->xfer_size_width          );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->packet_size_width        );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable               );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->i2c_enable               );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->vendor_ctrl_itf          );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->optional_feature_removed );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->synch_reset              );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_adp_support          );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->otg_enable_hsic          );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->battery_charger_support  );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->lpm_mode                 );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg3->total_fifo_size          );
 
   // HW configure 4
-  TU_LOG(1, "\r\n");
-  TU_LOG_HEX(1, dwc2->ghwcfg4);
-  TU_LOG_INT(1, hw_cfg4->num_dev_period_in_ep      );
-  TU_LOG_INT(1, hw_cfg4->power_optimized           );
-  TU_LOG_INT(1, hw_cfg4->ahb_freq_min              );
-  TU_LOG_INT(1, hw_cfg4->hibernation               );
-  TU_LOG_INT(1, hw_cfg4->service_interval_mode     );
-  TU_LOG_INT(1, hw_cfg4->ipg_isoc_en               );
-  TU_LOG_INT(1, hw_cfg4->acg_enable                );
-  TU_LOG_INT(1, hw_cfg4->utmi_phy_data_width       );
-  TU_LOG_INT(1, hw_cfg4->dev_ctrl_ep_num           );
-  TU_LOG_INT(1, hw_cfg4->iddg_filter_enabled       );
-  TU_LOG_INT(1, hw_cfg4->vbus_valid_filter_enabled );
-  TU_LOG_INT(1, hw_cfg4->a_valid_filter_enabled    );
-  TU_LOG_INT(1, hw_cfg4->b_valid_filter_enabled    );
-  TU_LOG_INT(1, hw_cfg4->dedicated_fifos           );
-  TU_LOG_INT(1, hw_cfg4->num_dev_in_eps            );
-  TU_LOG_INT(1, hw_cfg4->dma_desc_enable           );
-  TU_LOG_INT(1, hw_cfg4->dma_dynamic               );
+  TU_LOG(DWC2_DEBUG, "\r\n");
+  TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg4);
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_period_in_ep      );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->power_optimized           );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ahb_freq_min              );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->hibernation               );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->service_interval_mode     );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->ipg_isoc_en               );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->acg_enable                );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->utmi_phy_data_width       );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dev_ctrl_ep_num           );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->iddg_filter_enabled       );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->vbus_valid_filter_enabled );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->a_valid_filter_enabled    );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->b_valid_filter_enabled    );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dedicated_fifos           );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->num_dev_in_eps            );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_desc_enable           );
+  TU_LOG_INT(DWC2_DEBUG, hw_cfg4->dma_dynamic               );
 }
+#endif
 
 static void reset_core(dwc2_regs_t * dwc2)
 {
@@ -342,14 +336,15 @@ static void reset_core(dwc2_regs_t * dwc2)
   // wait for device mode ?
 }
 
-static bool has_hs_phy(dwc2_regs_t * dwc2)
+static bool phy_hs_supported(dwc2_regs_t * dwc2)
 {
+  // note: esp32 incorrect report its hs_phy_type as utmi
   return TUD_OPT_HIGH_SPEED && dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
 }
 
 static void phy_fs_init(dwc2_regs_t * dwc2)
 {
-  TU_LOG1("Fullspeed PHY init\r\n");
+  TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n");
 
   // Select FS PHY
   dwc2->gusbcfg |= GUSBCFG_PHYSEL;
@@ -358,11 +353,11 @@ static void phy_fs_init(dwc2_regs_t * dwc2)
   reset_core(dwc2);
 
   // set turn around
-  // The values above are calculated for the minimum AHB frequency of 30 MHz. USB turnaround
-  // time is critical for certification where long cables and 5-Hubs are used, so if
-  // you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
+  // USB turnaround time is critical for certification where long cables and 5-Hubs are used.
+  // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
   // these bits can be programmed to a larger value.
-  dwc2_set_turnaround(dwc2, TUSB_SPEED_FULL);
+  //TU_LOG_INT(DWC2_DEBUG, (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) >> GUSBCFG_TRDT_Pos );
+  dwc2_phyfs_set_turnaround(dwc2);
 
   // set max speed
   dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
@@ -382,7 +377,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
 
   if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI)
   {
-    TU_LOG1("Highspeed ULPI PHY init\r\n");
+    TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
 
     // Select ULPI
     gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
@@ -397,7 +392,7 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
     gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
   }else
   {
-    TU_LOG1("Highspeed UTMI+ PHY init\r\n");
+    TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n");
 
     // Select UTMI+ with 8-bit interface
     gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
@@ -422,11 +417,8 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
   reset_core(dwc2);
 
   // Set turn-around, must after core reset otherwise it will be clear
-  // 9 if UTMI interface is 8-bit, 5 if 16-bit
-  // The values above are calculated for the minimum AHB frequency of 30 MHz. USB turnaround
-  // time is critical for certification where long cables and 5-Hubs are used, so if
-  // you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
-  // these bits can be programmed to a larger value.
+  // - 9 if using 8-bit PHY interface
+  // - 5 if using 16-bit PHY interface
   gusbcfg &= ~GUSBCFG_TRDT_Msk;
   gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
   dwc2->gusbcfg = gusbcfg; // Apply config
@@ -435,31 +427,45 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
   dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos);
 }
 
+static bool check_dwc2(dwc2_regs_t * dwc2)
+{
+  // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
+#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
+  uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
+  TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);
+#endif
+
+#if CFG_TUSB_DEBUG >= DWC2_DEBUG
+  print_dwc2_info(dwc2);
+#endif
+
+  return true;
+}
+
 void dcd_init (uint8_t rhport)
 {
   // Programming model begins in the last section of the chapter on the USB
   // peripheral in each Reference Manual.
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
-  // Check Synopsys ID, failed if controller is not enabled
-  uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
-  TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID, );
-
-  print_dwc2_info(dwc2);
+  // Check Synopsys ID register, failed if controller clock/power is not enabled
+  TU_VERIFY(check_dwc2(dwc2), );
 
   // Force device mode
   dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
 
-  if( !has_hs_phy(dwc2) )
-  {
-    // core does not support highspeed or hs-phy is not present
-    phy_fs_init(dwc2);
-  }else
+  if( phy_hs_supported(dwc2) )
   {
     // Highspeed
     phy_hs_init(dwc2);
+  }else
+  {
+    // core does not support highspeed or hs-phy is not present
+    phy_fs_init(dwc2);
   }
 
+  TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
+
 	/* Set HS/FS Timeout Calibration to 7 (max available value).
 	 * The number of PHY clocks that the application programs in
 	 * this field is added to the high/full speed interpacket timeout
@@ -468,7 +474,7 @@ void dcd_init (uint8_t rhport)
 	 * introduced by the PHY in generating the linestate condition
 	 * can vary from one PHY to another.
 	 */
-  // dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
+  dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
 
   // Restart PHY clock
   dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
@@ -617,7 +623,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 
     _allocated_fifo_words_tx += fifo_size;
 
-    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, DWC2_EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
+    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %u", fifo_size*4, DWC2_EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
 
     // DIEPTXF starts at FIFO #1.
     // Both TXFD and TXSA are in unit of 32-bit words.
@@ -1110,14 +1116,15 @@ void dcd_int_handler(uint8_t rhport)
         speed = TUSB_SPEED_HIGH;
       break;
 
-      case DSTS_ENUMSPD_FS_HSPHY:
-      case DSTS_ENUMSPD_FS:
-        speed = TUSB_SPEED_FULL;
-      break;
-
       case DSTS_ENUMSPD_LS:
         speed = TUSB_SPEED_LOW;
       break;
+
+      case DSTS_ENUMSPD_FS_HSPHY:
+      case DSTS_ENUMSPD_FS:
+      default:
+        speed = TUSB_SPEED_FULL;
+      break;
     }
 
     dcd_event_bus_reset(rhport, speed, true);
@@ -1204,7 +1211,7 @@ void dcd_int_handler(uint8_t rhport)
   //  // Check for Incomplete isochronous IN transfer
   //  if(int_status & GINTSTS_IISOIXFR) {
   //    printf("      IISOIXFR!\r\n");
-  ////    TU_LOG2("      IISOIXFR!\r\n");
+  ////    TU_LOG(DWC2_DEBUG, "      IISOIXFR!\r\n");
   //  }
 }
 
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index da1f23ae0..c064946cf 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -58,11 +58,10 @@ static inline void dwc2_remote_wakeup_delay(void)
   // TODO implement later
 }
 
-static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
+static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2)
 {
-  // TODO implement later
-  (void) core;
-  (void) speed;
+  (void) dwc2;
+  // do nothing since bcm alwyas use HS PHY
 }
 
 #ifdef __cplusplus
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index b8a040041..af5d5f093 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -67,12 +67,10 @@ static inline void dwc2_remote_wakeup_delay(void)
   vTaskDelay(pdMS_TO_TICKS(1));
 }
 
-static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
+static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2)
 {
-  (void) core;
-  (void) speed;
-
-  // keep the reset value
+  (void) dwc2;
+  // keep the reset value which is 5 on this port
 }
 
 #ifdef __cplusplus
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index de3ccb3b0..15e73ad1e 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -76,12 +76,10 @@ static inline void dwc2_remote_wakeup_delay(void)
   while ( count-- ) __asm volatile ("nop");
 }
 
-static inline void dwc2_set_turnaround(dwc2_regs_t * core, tusb_speed_t speed)
+static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2)
 {
-  (void) core;
-  (void) speed;
-
-  // keep the reset value
+  // use recommeded value 6 by stm32 for mcu with AHB clock > 32Mhz
+  dwc2->gusbcfg = (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) | (6u << GUSBCFG_TRDT_Pos);
 }
 
 
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index b77cda2ca..4d0ed3f0a 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -113,44 +113,33 @@ static inline void dwc2_remote_wakeup_delay(void)
 }
 
 // Set turn-around timeout according to link speed
-static inline void dwc2_set_turnaround(dwc2_regs_t * dwc2, tusb_speed_t speed)
+static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2)
 {
-  dwc2->gusbcfg &= ~GUSBCFG_TRDT;
+  // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
+  uint32_t turnaround;
 
-  if ( speed == TUSB_SPEED_HIGH )
-  {
-    // Use fixed 0x09 for Highspeed
-    dwc2->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos);
-  }
+  if ( SystemCoreClock >= 32000000U )
+    turnaround = 0x6u;
+  else if ( SystemCoreClock >= 27500000U )
+    turnaround = 0x7u;
+  else if ( SystemCoreClock >= 24000000U )
+    turnaround = 0x8u;
+  else if ( SystemCoreClock >= 21800000U )
+    turnaround = 0x9u;
+  else if ( SystemCoreClock >= 20000000U )
+    turnaround = 0xAu;
+  else if ( SystemCoreClock >= 18500000U )
+    turnaround = 0xBu;
+  else if ( SystemCoreClock >= 17200000U )
+    turnaround = 0xCu;
+  else if ( SystemCoreClock >= 16000000U )
+    turnaround = 0xDu;
+  else if ( SystemCoreClock >= 15000000U )
+    turnaround = 0xEu;
   else
-  {
-    // Turnaround timeout depends on the MCU clock
-    uint32_t turnaround;
+    turnaround = 0xFu;
 
-    if ( SystemCoreClock >= 32000000U )
-      turnaround = 0x6U;
-    else if ( SystemCoreClock >= 27500000U )
-      turnaround = 0x7U;
-    else if ( SystemCoreClock >= 24000000U )
-      turnaround = 0x8U;
-    else if ( SystemCoreClock >= 21800000U )
-      turnaround = 0x9U;
-    else if ( SystemCoreClock >= 20000000U )
-      turnaround = 0xAU;
-    else if ( SystemCoreClock >= 18500000U )
-      turnaround = 0xBU;
-    else if ( SystemCoreClock >= 17200000U )
-      turnaround = 0xCU;
-    else if ( SystemCoreClock >= 16000000U )
-      turnaround = 0xDU;
-    else if ( SystemCoreClock >= 15000000U )
-      turnaround = 0xEU;
-    else
-      turnaround = 0xFU;
-
-    // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    dwc2->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos);
-  }
+  dwc2->gusbcfg = (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos);
 }
 
 #if defined(USB_HS_PHYC)
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 7e472310f..7b3db4dd9 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -59,12 +59,19 @@ typedef struct
 #endif
 
 enum {
-  HS_PHY_TYPE_NONE = 0  ,
+  HS_PHY_TYPE_NONE = 0  , // not supported
   HS_PHY_TYPE_UTMI      , // internal PHY (mostly)
   HS_PHY_TYPE_ULPI      , // external PHY
   HS_PHY_TYPE_UTMI_ULPI ,
 };
 
+enum {
+  FS_PHY_TYPE_NONE = 0,  // not supported
+  FS_PHY_TYPE_DEDICATED,
+  FS_PHY_TYPE_UTMI,
+  FS_PHY_TYPE_ULPI,
+};
+
 typedef struct TU_ATTR_PACKED
 {
   uint32_t op_mode                  : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP
@@ -531,10 +538,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GUSBCFG_TRDT_Pos                 (10U)
 #define GUSBCFG_TRDT_Msk                 (0xFUL << GUSBCFG_TRDT_Pos)              // 0x00003C00 */
 #define GUSBCFG_TRDT                     GUSBCFG_TRDT_Msk                         // USB turnaround time */
-#define GUSBCFG_TRDT_0                   (0x1UL << GUSBCFG_TRDT_Pos)              // 0x00000400 */
-#define GUSBCFG_TRDT_1                   (0x2UL << GUSBCFG_TRDT_Pos)              // 0x00000800 */
-#define GUSBCFG_TRDT_2                   (0x4UL << GUSBCFG_TRDT_Pos)              // 0x00001000 */
-#define GUSBCFG_TRDT_3                   (0x8UL << GUSBCFG_TRDT_Pos)              // 0x00002000 */
 #define GUSBCFG_PHYLPCS_Pos              (15U)
 #define GUSBCFG_PHYLPCS_Msk              (0x1UL << GUSBCFG_PHYLPCS_Pos)           // 0x00008000 */
 #define GUSBCFG_PHYLPCS                  GUSBCFG_PHYLPCS_Msk                      // PHY Low-power clock select */

From 19a26729b03bab188746b5e835878530c7bed65d Mon Sep 17 00:00:00 2001
From: Matt Johnston <matt@codeconstruct.com.au>
Date: Fri, 17 Sep 2021 17:56:24 +0800
Subject: [PATCH 0617/2085] Add Adafruit QT Py board

Straight copy of itsybitsy_m0/ with MCU changed to
ATSAMD21E18

LED and button are disabled.
LED is a neopixel so could be added later.
---
 hw/bsp/samd21/boards/qtpy/board.h  |  46 +++++++++
 hw/bsp/samd21/boards/qtpy/board.mk |  11 +++
 hw/bsp/samd21/boards/qtpy/qtpy.ld  | 146 +++++++++++++++++++++++++++++
 3 files changed, 203 insertions(+)
 create mode 100644 hw/bsp/samd21/boards/qtpy/board.h
 create mode 100644 hw/bsp/samd21/boards/qtpy/board.mk
 create mode 100644 hw/bsp/samd21/boards/qtpy/qtpy.ld

diff --git a/hw/bsp/samd21/boards/qtpy/board.h b/hw/bsp/samd21/boards/qtpy/board.h
new file mode 100644
index 000000000..6f8325e49
--- /dev/null
+++ b/hw/bsp/samd21/boards/qtpy/board.h
@@ -0,0 +1,46 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED is neopixel, leave unset for now
+
+// Button is wired to reset
+
+// UART
+#define UART_RX_PIN           8
+#define UART_TX_PIN           7
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/samd21/boards/qtpy/board.mk b/hw/bsp/samd21/boards/qtpy/board.mk
new file mode 100644
index 000000000..6cefa84c3
--- /dev/null
+++ b/hw/bsp/samd21/boards/qtpy/board.mk
@@ -0,0 +1,11 @@
+# For Adafruit QT Py board
+
+CFLAGS += -D__SAMD21E18A__ -DCFG_EXAMPLE_VIDEO_READONLY
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/$(BOARD).ld
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAMD21E18
+
+flash: flash-bossac
diff --git a/hw/bsp/samd21/boards/qtpy/qtpy.ld b/hw/bsp/samd21/boards/qtpy/qtpy.ld
new file mode 100644
index 000000000..f0c93340c
--- /dev/null
+++ b/hw/bsp/samd21/boards/qtpy/qtpy.ld
@@ -0,0 +1,146 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+ENTRY(Reset_Handler)
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+        end = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}

From 9cd5a87c64425b8a7427531735f06f255117aeeb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 30 Oct 2021 20:42:55 +0700
Subject: [PATCH 0618/2085] add support for EFM32GG

merge GG12 GG12 to simply OPT_MCU_EFM32GG
---
 hw/bsp/board_mcu.h                           |   2 +-
 hw/bsp/sltb009a/board.mk                     |   4 +-
 hw/bsp/stm32f4/family.c                      |   7 +
 hw/bsp/stm32h7/boards/stm32h743eval/board.mk |   1 +
 hw/bsp/stm32h7/family.mk                     |  12 +-
 src/device/dcd_attr.h                        |   2 +-
 src/host/hcd_attr.h                          |   2 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c        |  96 +++++++-----
 src/portable/synopsys/dwc2/dwc2_bcm.h        |  17 ++-
 src/portable/synopsys/dwc2/dwc2_esp32.h      |  18 ++-
 src/portable/synopsys/dwc2/dwc2_gd32.h       |  18 ++-
 src/portable/synopsys/dwc2/dwc2_stm32.h      | 147 ++++++++++---------
 src/portable/synopsys/dwc2/dwc2_type.h       |   2 +-
 src/tusb_option.h                            |   2 -
 14 files changed, 204 insertions(+), 126 deletions(-)

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index a4d57597c..c840db89e 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -125,7 +125,7 @@
 #elif CFG_TUSB_MCU == OPT_MCU_RP2040
   #include "pico.h"
   
-#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG || CFG_TUSB_MCU == OPT_MCU_EFM32GG11 || CFG_TUSB_MCU == OPT_MCU_EFM32GG12
+#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG
   #include "em_device.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index e8a24d1bd..7a046b34b 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -8,7 +8,7 @@ CFLAGS += \
   -D__STARTUP_CLEAR_BSS \
   -D__START=main \
   -DEFM32GG12B810F1024GM64 \
-  -DCFG_TUSB_MCU=OPT_MCU_EFM32GG12 
+  -DCFG_TUSB_MCU=OPT_MCU_EFM32GG
 
 # mcu driver cause following warnings
 #CFLAGS += -Wno-error=unused-parameter
@@ -24,7 +24,7 @@ LD_FILE = $(SILABS_CMSIS)/Source/GCC/$(SILABS_FAMILY).ld
 
 SRC_C += \
   $(SILABS_CMSIS)/Source/system_$(SILABS_FAMILY).c \
-  src/portable/silabs/efm32/dcd_efm32.c
+	src/portable/synopsys/dwc2/dcd_dwc2.c
 
 SRC_S += \
   $(SILABS_CMSIS)/Source/GCC/startup_$(SILABS_FAMILY).S
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index 31f27fa3f..82d4957e7 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -36,6 +36,11 @@ void OTG_FS_IRQHandler(void)
   tud_int_handler(0);
 }
 
+void OTG_HS_IRQHandler(void)
+{
+  tud_int_handler(1);
+}
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -134,6 +139,8 @@ void board_init(void)
   // Enable USB OTG clock
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
+//  __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
+
   board_vbus_sense_init();
 }
 
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
index 96d14a795..b768a0ee6 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
@@ -2,6 +2,7 @@ CFLAGS += -DSTM32H743xx -DHSE_VALUE=25000000
 
 # Default is Highspeed port
 PORT ?= 1
+SPEED ?= high
 
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
 LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index 6a257e22d..096d04d0c 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -19,16 +19,22 @@ CFLAGS += \
 	-DBOARD_DEVICE_RHPORT_NUM=$(PORT)
 
 ifeq ($(PORT), 1)
-  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
-  $(info "PORT1 High Speed")
+  ifeq ($(SPEED), high)
+    CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+    $(info "Using OTG_HS in HighSpeed mode")
+  else
+    CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_FULL_SPEED
+    $(info "Using OTG_HS in FullSpeed mode")
+  endif
 else
-  $(info "PORT0 Full Speed")
+  $(info "Using OTG_FS")
 endif
 
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 
 # All source paths should be relative to the top level.
+
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 90f3a526a..70854f9c6 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -169,7 +169,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 //------------- Silabs -------------//
-#elif TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_EFM32GG11, OPT_MCU_EFM32GG12)
+#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
   #define DCD_ATTR_ENDPOINT_MAX   7
 
 //------------- Renesas -------------//
diff --git a/src/host/hcd_attr.h b/src/host/hcd_attr.h
index a9bc242d7..06011c63c 100644
--- a/src/host/hcd_attr.h
+++ b/src/host/hcd_attr.h
@@ -82,7 +82,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_RP2040)
 
 //------------- Silabs -------------//
-#elif TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_EFM32GG11, OPT_MCU_EFM32GG12)
+#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
 
 //------------- Renesas -------------//
 #elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index aad7e45cc..16780cba8 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -31,7 +31,9 @@
 #include "device/dcd_attr.h"
 
 #if TUSB_OPT_DEVICE_ENABLED && \
-    ( defined(DCD_ATTR_DWC2_STM32) || TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103, OPT_MCU_BCM2711) )
+    ( defined(DCD_ATTR_DWC2_STM32) || \
+      TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) || \
+      TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711) )
 
 #include "device/dcd.h"
 #include "dwc2_type.h"
@@ -44,6 +46,8 @@
   #include "dwc2_gd32.h"
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711)
   #include "dwc2_bcm.h"
+#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
+  #include "dwc2_efm32.h"
 #else
   #error "Unsupported MCUs"
 #endif
@@ -260,6 +264,9 @@ void print_dwc2_info(dwc2_regs_t * dwc2)
   dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm;
   dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm;
 
+  TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl);
+  TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
+  TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg);
   TU_LOG_HEX(DWC2_DEBUG, dwc2->guid);
   TU_LOG_HEX(DWC2_DEBUG, dwc2->gsnpsid);
   TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg1);
@@ -349,23 +356,22 @@ static void phy_fs_init(dwc2_regs_t * dwc2)
   // Select FS PHY
   dwc2->gusbcfg |= GUSBCFG_PHYSEL;
 
+  // MCU specific PHY init before reset
+  dwc2_phy_init(dwc2, HS_PHY_TYPE_NONE);
+
   // Reset core after selecting PHY
   reset_core(dwc2);
 
-  // set turn around
   // USB turnaround time is critical for certification where long cables and 5-Hubs are used.
   // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
-  // these bits can be programmed to a larger value.
-  //TU_LOG_INT(DWC2_DEBUG, (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) >> GUSBCFG_TRDT_Pos );
-  dwc2_phyfs_set_turnaround(dwc2);
+  // these bits can be programmed to a larger value. Default is 5
+  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
+
+  // MCU specific PHY update post reset
+  dwc2_phy_update(dwc2, HS_PHY_TYPE_NONE);
 
   // set max speed
   dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
-
-  #if defined(DCD_ATTR_DWC2_STM32)
-  // activate FS PHY on stm32
-  dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
-  #endif
 }
 
 static void phy_hs_init(dwc2_regs_t * dwc2)
@@ -399,19 +405,13 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
 
     // Set 16-bit interface if supported
     if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16;
-
-    #if defined(DCD_ATTR_DWC2_STM32) && defined(USB_HS_PHYC)
-    dwc2_stm32_utmi_phy_init(dwc2);
-    #endif
   }
 
   // Apply config
   dwc2->gusbcfg = gusbcfg;
 
-  #if defined(DCD_ATTR_DWC2_STM32)
-  // Disable STM32 FS PHY
-  dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
-  #endif
+  // mcu specific phy init
+  dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
 
   // Reset core after selecting PHY
   reset_core(dwc2);
@@ -421,7 +421,10 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
   // - 5 if using 16-bit PHY interface
   gusbcfg &= ~GUSBCFG_TRDT_Msk;
   gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
-  dwc2->gusbcfg = gusbcfg; // Apply config
+  dwc2->gusbcfg = gusbcfg;
+
+  // MCU specific PHY update post reset
+  dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
 
   // Set max speed
   dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos);
@@ -429,16 +432,16 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
 
 static bool check_dwc2(dwc2_regs_t * dwc2)
 {
+#if CFG_TUSB_DEBUG >= DWC2_DEBUG
+  print_dwc2_info(dwc2);
+#endif
+
   // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
 #if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
   uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
   TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);
 #endif
 
-#if CFG_TUSB_DEBUG >= DWC2_DEBUG
-  print_dwc2_info(dwc2);
-#endif
-
   return true;
 }
 
@@ -451,8 +454,10 @@ void dcd_init (uint8_t rhport)
   // Check Synopsys ID register, failed if controller clock/power is not enabled
   TU_VERIFY(check_dwc2(dwc2), );
 
-  // Force device mode
-  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
+  dcd_disconnect(rhport);
+
+  // max number of endpoints & total_fifo_size are:
+  // hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size
 
   if( phy_hs_supported(dwc2) )
   {
@@ -464,7 +469,11 @@ void dcd_init (uint8_t rhport)
     phy_fs_init(dwc2);
   }
 
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
+  // Restart PHY clock
+  dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
+
+  // Force device mode
+  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
 
 	/* Set HS/FS Timeout Calibration to 7 (max available value).
 	 * The number of PHY clocks that the application programs in
@@ -476,27 +485,34 @@ void dcd_init (uint8_t rhport)
 	 */
   dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
 
-  // Restart PHY clock
-  dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
-
-  // Clear all interrupts
-  dwc2->gintsts |= dwc2->gintsts;
-
-  // Required as part of core initialization.
-  // TODO: How should mode mismatch be handled? It will cause
-  // the core to stop working/require reset.
-  dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_MMISM;
-
   // If USB host misbehaves during status portion of control xfer
   // (non zero-length packet), send STALL back and discard.
   dwc2->dcfg |= DCFG_NZLSOHSK;
 
-  dwc2->gintmsk |= GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_USBSUSPM |
-                   GINTMSK_WUIM   | GINTMSK_RXFLVLM;
+  // Clear A,B, VBus valid override
+  dwc2->gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN | GOTGCTL_VBVALOEN);
+
+  // Clear all interrupts
+  dwc2->gintsts |= dwc2->gintsts;
+  dwc2->gotgint |= dwc2->gotgint;
+
+  // Required as part of core initialization.
+  // TODO: How should mode mismatch be handled? It will cause
+  // the core to stop working/require reset.
+  dwc2->gintmsk = GINTMSK_OTGINT   | GINTMSK_MMISM  | GINTMSK_RXFLVLM  |
+                  GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM;
 
   // Enable global interrupt
   dwc2->gahbcfg |= GAHBCFG_GINT;
 
+  // make sure we are in device mode
+//  TU_ASSERT(!(dwc2->gintsts & GINTSTS_CMOD), );
+
+//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl);
+//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
+//  TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg);
+//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gahbcfg);
+
   dcd_connect(rhport);
 }
 
@@ -1096,6 +1112,8 @@ void dcd_int_handler(uint8_t rhport)
 
   uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk;
 
+//  TU_LOG_HEX(DWC2_DEBUG, int_status);
+
   if(int_status & GINTSTS_USBRST)
   {
     // USBRST is start of reset.
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index c064946cf..38d10930c 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -51,17 +51,28 @@ static inline void dwc2_dcd_int_disable (uint8_t rhport)
   BP_DisableIRQ(USB_IRQn);
 }
 
-TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_remote_wakeup_delay(void)
 {
   // try to delay for 1 ms
   // TODO implement later
 }
 
-static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2)
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
   (void) dwc2;
-  // do nothing since bcm alwyas use HS PHY
+  (void) hs_phy_type;
+
+  // nothing to do
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+  (void) dwc2;
+  (void) hs_phy_type;
+
+  // nothing to do
 }
 
 #ifdef __cplusplus
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index af5d5f093..78da277d5 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -50,12 +50,14 @@ static void dcd_int_handler_wrap(void* arg)
   dcd_int_handler(0);
 }
 
+TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable (uint8_t rhport)
 {
   (void) rhport;
   esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih);
 }
 
+TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
   (void) rhport;
@@ -67,10 +69,22 @@ static inline void dwc2_remote_wakeup_delay(void)
   vTaskDelay(pdMS_TO_TICKS(1));
 }
 
-static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2)
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
   (void) dwc2;
-  // keep the reset value which is 5 on this port
+  (void) hs_phy_type;
+
+  // nothing to do
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+  (void) dwc2;
+  (void) hs_phy_type;
+
+  // nothing to do
 }
 
 #ifdef __cplusplus
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index 15e73ad1e..f8fa01ee0 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -68,7 +68,6 @@ static inline void dwc2_dcd_int_disable (uint8_t rhport)
   __eclic_disable_interrupt(RHPORT_IRQn);
 }
 
-TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_remote_wakeup_delay(void)
 {
   // try to delay for 1 ms
@@ -76,12 +75,23 @@ static inline void dwc2_remote_wakeup_delay(void)
   while ( count-- ) __asm volatile ("nop");
 }
 
-static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2)
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
-  // use recommeded value 6 by stm32 for mcu with AHB clock > 32Mhz
-  dwc2->gusbcfg = (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) | (6u << GUSBCFG_TRDT_Pos);
+  (void) dwc2;
+  (void) hs_phy_type;
+
+  // nothing to do
 }
 
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+  (void) dwc2;
+  (void) hs_phy_type;
+
+  // nothing to do
+}
 
 #ifdef __cplusplus
 }
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 4d0ed3f0a..469045ac4 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -112,78 +112,91 @@ static inline void dwc2_remote_wakeup_delay(void)
   while ( count-- ) __NOP();
 }
 
-// Set turn-around timeout according to link speed
-static inline void dwc2_phyfs_set_turnaround(dwc2_regs_t * dwc2)
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
 {
-  // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
-  uint32_t turnaround;
-
-  if ( SystemCoreClock >= 32000000U )
-    turnaround = 0x6u;
-  else if ( SystemCoreClock >= 27500000U )
-    turnaround = 0x7u;
-  else if ( SystemCoreClock >= 24000000U )
-    turnaround = 0x8u;
-  else if ( SystemCoreClock >= 21800000U )
-    turnaround = 0x9u;
-  else if ( SystemCoreClock >= 20000000U )
-    turnaround = 0xAu;
-  else if ( SystemCoreClock >= 18500000U )
-    turnaround = 0xBu;
-  else if ( SystemCoreClock >= 17200000U )
-    turnaround = 0xCu;
-  else if ( SystemCoreClock >= 16000000U )
-    turnaround = 0xDu;
-  else if ( SystemCoreClock >= 15000000U )
-    turnaround = 0xEu;
-  else
-    turnaround = 0xFu;
-
-  dwc2->gusbcfg = (dwc2->gusbcfg & GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos);
-}
-
-#if defined(USB_HS_PHYC)
-static inline void dwc2_stm32_utmi_phy_init(dwc2_regs_t * dwc2)
-{
-  USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
-
-  // Enable UTMI HS PHY
-  dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
-
-  // Enable LDO
-  usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
-
-  // Wait until LDO ready
-  while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
-
-  uint32_t phyc_pll = 0;
-
-  // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
-  switch ( HSE_VALUE )
+  if ( hs_phy_type == HS_PHY_TYPE_NONE )
   {
-    case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
-    case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
-    case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
-    case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
-    case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
-    case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
-    default:
-      TU_ASSERT(false, );
+    // Enable on-chip FS PHY
+    dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
+  }else
+  {
+    // Disable FS PHY
+    dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN;
+
+    // Enable on-chip HS PHY
+    if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI)
+    {
+#ifdef USB_HS_PHYC
+      // Enable UTMI HS PHY
+      dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
+
+      // Enable LDO
+      USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
+
+      // Wait until LDO ready
+      while ( 0 == (USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
+
+      uint32_t phyc_pll = 0;
+
+      // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
+      switch ( HSE_VALUE )
+      {
+        case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
+        case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
+        case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
+        case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
+        case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
+        case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
+        default:
+          TU_ASSERT(false, );
+      }
+      USB_HS_PHYC->USB_HS_PHYC_PLL = phyc_pll;
+
+      // Control the tuning interface of the High Speed PHY
+      // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver for F7
+      USB_HS_PHYC->USB_HS_PHYC_TUNE |= 0x00000F13U;
+
+      // Enable PLL internal PHY
+      USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
+#endif
+    }
   }
-  usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
-
-  // Control the tuning interface of the High Speed PHY
-  // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
-  usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
-
-  // Enable PLL internal PHY
-  usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
-
-  // Original ST code has 2 ms delay for PLL stabilization.
-  // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
 }
 
-#endif
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+  // used to set turnaround time for fullspeed, nothing to do in highspeed mode
+  if ( hs_phy_type == HS_PHY_TYPE_NONE )
+  {
+    // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual
+    uint32_t turnaround;
+
+    if ( SystemCoreClock >= 32000000u )
+      turnaround = 0x6u;
+    else if ( SystemCoreClock >= 27500000u )
+      turnaround = 0x7u;
+    else if ( SystemCoreClock >= 24000000u )
+      turnaround = 0x8u;
+    else if ( SystemCoreClock >= 21800000u )
+      turnaround = 0x9u;
+    else if ( SystemCoreClock >= 20000000u )
+      turnaround = 0xAu;
+    else if ( SystemCoreClock >= 18500000u )
+      turnaround = 0xBu;
+    else if ( SystemCoreClock >= 17200000u )
+      turnaround = 0xCu;
+    else if ( SystemCoreClock >= 16000000u )
+      turnaround = 0xDu;
+    else if ( SystemCoreClock >= 15000000u )
+      turnaround = 0xEu;
+    else
+      turnaround = 0xFu;
+
+    dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (turnaround << GUSBCFG_TRDT_Pos);
+  }
+}
 
 #ifdef __cplusplus
 }
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 7b3db4dd9..583a7274a 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -528,7 +528,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GUSBCFG_PHYSEL_Pos               (6U)
 #define GUSBCFG_PHYSEL_Msk               (0x1UL << GUSBCFG_PHYSEL_Pos)            // 0x00000040 */
 #define GUSBCFG_PHYSEL                   GUSBCFG_PHYSEL_Msk                       // USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define GUSBCFG_DDRSEL                TU_BIT(7)                                // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
+#define GUSBCFG_DDRSEL                   TU_BIT(7)                                // Single Data Rate (SDR) or Double Data Rate (DDR) or ULPI interface.
 #define GUSBCFG_SRPCAP_Pos               (8U)
 #define GUSBCFG_SRPCAP_Msk               (0x1UL << GUSBCFG_SRPCAP_Pos)            // 0x00000100 */
 #define GUSBCFG_SRPCAP                   GUSBCFG_SRPCAP_Msk                       // SRP-capable */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index de0279dda..4da07e241 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -113,8 +113,6 @@
 
 // Silabs
 #define OPT_MCU_EFM32GG          1300 ///< Silabs EFM32GG
-#define OPT_MCU_EFM32GG11        1301 ///< Silabs EFM32GG11
-#define OPT_MCU_EFM32GG12        1302 ///< Silabs EFM32GG12
 
 // Renesas RX
 #define OPT_MCU_RX63X            1400 ///< Renesas RX63N/631

From b85a6898af6fb75d5e877d418748a22c92a6d7bf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 30 Oct 2021 20:45:58 +0700
Subject: [PATCH 0619/2085] remove dcd_efm32

---
 src/portable/silabs/efm32/dcd_efm32.c   | 936 ------------------------
 src/portable/synopsys/dwc2/dwc2_efm32.h |  87 +++
 2 files changed, 87 insertions(+), 936 deletions(-)
 delete mode 100644 src/portable/silabs/efm32/dcd_efm32.c
 create mode 100644 src/portable/synopsys/dwc2/dwc2_efm32.h

diff --git a/src/portable/silabs/efm32/dcd_efm32.c b/src/portable/silabs/efm32/dcd_efm32.c
deleted file mode 100644
index ccae113a3..000000000
--- a/src/portable/silabs/efm32/dcd_efm32.c
+++ /dev/null
@@ -1,936 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2021 Rafael Silva (@perigoso)
- * Copyright (c) 2021 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && ( \
-  (CFG_TUSB_MCU == OPT_MCU_EFM32GG) || \
-  (CFG_TUSB_MCU == OPT_MCU_EFM32GG11) || \
-  (CFG_TUSB_MCU == OPT_MCU_EFM32GG12) )
-
-/* Silabs */
-#include "em_device.h"
-
-#include "device/dcd.h"
-
-/* 
- * Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
- * We disable SOF for now until needed later on
- */
-#define USE_SOF     0
-
-/* 
- * Number of endpoints
- * 12 software-configurable endpoints (6 IN, 6 OUT) in addition to endpoint 0
- */
-#define EP_COUNT        7
-
-/* FIFO size in bytes */
-#define EP_FIFO_SIZE    2048
-
-/* Max number of IN EP FIFOs */
-#define EP_FIFO_NUM     7
-
-/* */
-typedef struct {
-    uint8_t *buffer;
-    uint16_t total_len;
-    uint16_t queued_len;
-    uint16_t max_size;
-    bool short_packet;
-} xfer_ctl_t;
-
-static uint32_t _setup_packet[2];
-
-#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
-static xfer_ctl_t xfer_status[EP_COUNT][2];
-
-/* Keep count of how many FIFOs are in use */
-static uint8_t _allocated_fifos = 1; /* FIFO0 is always in use */
-
-static volatile uint32_t* tx_fifo[EP_FIFO_NUM] = {
-  USB->FIFO0D,
-  USB->FIFO1D,
-  USB->FIFO2D,
-  USB->FIFO3D,
-  USB->FIFO4D,
-  USB->FIFO5D,
-  USB->FIFO6D,
-};
-
-/* Register Helpers */
-#define DCTL_WO_BITMASK     (USB_DCTL_CGOUTNAK | USB_DCTL_SGOUTNAK | USB_DCTL_CGNPINNAK | USB_DCTL_SGNPINNAK)
-#define GUSBCFG_WO_BITMASK  (USB_GUSBCFG_CORRUPTTXPKT)
-#define DEPCTL_WO_BITMASK   (USB_DIEP_CTL_CNAK | USB_DIEP_CTL_SNAK | USB_DIEP_CTL_SETD0PIDEF | USB_DIEP_CTL_SETD1PIDOF)
-
-/* Will either return an unused FIFO number, or 0 if all are used. */
-static uint8_t get_free_fifo(void)
-{
-  if(_allocated_fifos < EP_FIFO_NUM) return _allocated_fifos++;
-  return 0;
-}
-
-/*
-static void flush_rx_fifo(void)
-{
-  USB->GRSTCTL = USB_GRSTCTL_RXFFLSH;
-  while(USB->GRSTCTL & USB_GRSTCTL_RXFFLSH);
-} 
-*/
-
-static void flush_tx_fifo(uint8_t fifo_num)
-{
-  USB->GRSTCTL = USB_GRSTCTL_TXFFLSH | (fifo_num << _USB_GRSTCTL_TXFNUM_SHIFT);
-  while(USB->GRSTCTL & USB_GRSTCTL_TXFFLSH);
-}
-
-/* Setup the control endpoint 0. */
-static void bus_reset(void)
-{
-  USB->DOEP0CTL |= USB_DIEP_CTL_SNAK;
-  for(uint8_t i = 0; i < EP_COUNT - 1; i++)
-  {
-    USB->DOEP[i].CTL |= USB_DIEP_CTL_SNAK;
-  }
-  
-  /* reset address */
-  USB->DCFG &= ~_USB_DCFG_DEVADDR_MASK;
-
-  USB->DAINTMSK |= USB_DAINTMSK_OUTEPMSK0 | USB_DAINTMSK_INEPMSK0;
-  USB->DOEPMSK |= USB_DOEPMSK_SETUPMSK | USB_DOEPMSK_XFERCOMPLMSK;
-  USB->DIEPMSK |= USB_DIEPMSK_TIMEOUTMSK | USB_DIEPMSK_XFERCOMPLMSK;
-
-  /* 
-   * - All EP OUT shared a unique OUT FIFO which uses
-   *   * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets).
-   *   * 2 locations for OUT endpoint control words.
-   *   * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
-   *   * 1 location for global NAK (not required/used here).
-   *   * It is recommended to allocate 2 times the largest packet size, therefore
-   *  Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52
-   */
-  flush_tx_fifo(_USB_GRSTCTL_TXFNUM_FALL);  // Flush All
-  USB->GRXFSIZ = 52;
-
-  /* Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) */
-  USB->GNPTXFSIZ = (16 << _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_SHIFT) | (USB->GRXFSIZ & _USB_GNPTXFSIZ_NPTXFSTADDR_MASK);
-
-  /* Ready to receive SETUP packet */
-  USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_SUPCNT_SHIFT);
-
-  USB->GINTMSK |= USB_GINTMSK_IEPINTMSK | USB_GINTMSK_OEPINTMSK;
-}
-
-static void enum_done_processing(void)
-{
-  /* Maximum packet size for EP 0 is set for both directions by writing DIEPCTL */
-  if((USB->DSTS & _USB_DSTS_ENUMSPD_MASK) == USB_DSTS_ENUMSPD_FS)
-  { 
-    /* Full Speed (PHY on 48 MHz) */
-    USB->DOEP0CTL = (USB->DOEP0CTL & ~_USB_DOEP0CTL_MPS_MASK) | _USB_DOEP0CTL_MPS_64B; /* Maximum Packet Size 64 bytes */
-    USB->DOEP0CTL &= ~_USB_DOEP0CTL_STALL_MASK; /* clear Stall */
-    xfer_status[0][TUSB_DIR_OUT].max_size = 64;
-    xfer_status[0][TUSB_DIR_IN].max_size = 64;
-  }
-  else
-  { 
-    /* Low Speed (PHY on 6 MHz) */
-    USB->DOEP0CTL = (USB->DOEP0CTL & ~_USB_DOEP0CTL_MPS_MASK) | _USB_DOEP0CTL_MPS_8B; /* Maximum Packet Size 64 bytes */
-    USB->DOEP0CTL &= ~_USB_DOEP0CTL_STALL_MASK; /* clear Stall */
-    xfer_status[0][TUSB_DIR_OUT].max_size = 8;
-    xfer_status[0][TUSB_DIR_IN].max_size = 8;
-  }
-}
-
-
-/*------------------------------------------------------------------*/
-/* Controller API                                                   */
-/*------------------------------------------------------------------*/
-void dcd_init(uint8_t rhport)
-{
-  (void) rhport;
-
-  /* Reset Core */
-  USB->PCGCCTL &= ~USB_PCGCCTL_STOPPCLK;
-  USB->PCGCCTL &= ~(USB_PCGCCTL_PWRCLMP | USB_PCGCCTL_RSTPDWNMODULE);
-
-  /* Core Soft Reset */
-  USB->GRSTCTL |= USB_GRSTCTL_CSFTRST;
-  while(USB->GRSTCTL & USB_GRSTCTL_CSFTRST);
-
-  while(!(USB->GRSTCTL & USB_GRSTCTL_AHBIDLE));
-
-  /* Enable PHY pins */
-  USB->ROUTE = USB_ROUTE_PHYPEN;
-
-  dcd_disconnect(rhport);
-
-  /* 
-   * Set device speed (Full speed PHY)
-   * Stall on non-zero len status OUT packets (ctrl transfers)
-   * periodic frame interval to 80% 
-   */
-  USB->DCFG = (USB->DCFG & ~(_USB_DCFG_DEVSPD_MASK | _USB_DCFG_PERFRINT_MASK)) | USB_DCFG_DEVSPD_FS | USB_DCFG_NZSTSOUTHSHK;
-  
-  /* Enable Global Interrupts */
-  USB->GAHBCFG = (USB->GAHBCFG & ~_USB_GAHBCFG_HBSTLEN_MASK) | USB_GAHBCFG_GLBLINTRMSK;
-
-  /* Force Device Mode */
-  USB->GUSBCFG = (USB->GUSBCFG & ~(GUSBCFG_WO_BITMASK | USB_GUSBCFG_FORCEHSTMODE)) | USB_GUSBCFG_FORCEDEVMODE;
-
-  /* No Overrides */
-  USB->GOTGCTL &= ~(USB_GOTGCTL_BVALIDOVVAL | USB_GOTGCTL_BVALIDOVEN | USB_GOTGCTL_VBVALIDOVVAL);
-
-  /* Ignore frame numbers on ISO transfers. */
-  USB->DCTL = (USB->DCTL & ~DCTL_WO_BITMASK) | USB_DCTL_IGNRFRMNUM;
-
-  /* Setting SNAKs */
-  USB->DOEP0CTL |= USB_DIEP_CTL_SNAK;
-  for(uint8_t i = 0; i < EP_COUNT - 1; i++)
-  {
-    USB->DOEP[i].CTL |= USB_DIEP_CTL_SNAK;
-  }
-
-  /* D. Interruption masking */
-  /* Disable all device interrupts */
-  USB->DIEPMSK  = 0;
-  USB->DOEPMSK  = 0;
-  USB->DAINTMSK = 0;
-  USB->DIEPEMPMSK = 0;
-  USB->GINTMSK = 0;
-  USB->GOTGINT = ~0U; /* clear OTG ints */
-  USB->GINTSTS = ~0U; /* clear pending ints */
-  USB->GINTMSK = USB_GINTMSK_MODEMISMSK  |
-              #if USE_SOF
-                 USB_GINTMSK_SOFMSK      |
-              #endif
-                 USB_GINTMSK_ERLYSUSPMSK |
-                 USB_GINTMSK_USBSUSPMSK  |
-                 USB_GINTMSK_USBRSTMSK   |
-                 USB_GINTMSK_ENUMDONEMSK |
-                 USB_GINTMSK_RESETDETMSK |
-                 USB_GINTMSK_DISCONNINTMSK;
-
-  NVIC_ClearPendingIRQ(USB_IRQn);
-
-  dcd_connect(rhport);
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  (void) rhport;
-
-  USB->DCFG = (USB->DCFG & ~_USB_DCFG_DEVADDR_MASK) | (dev_addr << _USB_DCFG_DEVADDR_SHIFT);
-
-  /* Response with status after changing device address */
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
-}
-
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-
-  /* connect by enabling internal pull-up resistor on D+/D- */
-  USB->DCTL &= ~(DCTL_WO_BITMASK | USB_DCTL_SFTDISCON);
-}
-
-void dcd_disconnect(uint8_t rhport)
-{
-  (void) rhport;
-
-  /* disconnect by disabling internal pull-up resistor on D+/D- */
-  USB->DCTL = (USB->DCTL & ~(DCTL_WO_BITMASK)) | USB_DCTL_SFTDISCON;
-}
-
-/*------------------------------------------------------------------*/
-/* DCD Endpoint Port                                                */
-/*------------------------------------------------------------------*/
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir = tu_edpt_dir(ep_addr);
-
-  if(dir == TUSB_DIR_IN)
-  {
-    if(epnum == 0)
-    {
-      USB->DIEP0CTL = (USB->DIEP0CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP0CTL_SNAK | USB_DIEP0CTL_STALL;
-
-      flush_tx_fifo(_USB_GRSTCTL_TXFNUM_F0);
-    }
-    else
-    {
-      /* Only disable currently enabled non-control endpoint */
-      if(USB->DIEP[epnum - 1].CTL & USB_DIEP_CTL_EPENA) 
-      {
-        USB->DIEP[epnum - 1].CTL = (USB->DIEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_EPDIS | USB_DIEP_CTL_SNAK | USB_DIEP_CTL_STALL;
-        while(!(USB->DIEP[epnum - 1].INT & USB_DIEP_INT_EPDISBLD));
-        USB->DIEP[epnum - 1].INT |= USB_DIEP_INT_EPDISBLD;
-      }
-      else
-      {
-        USB->DIEP[epnum - 1].CTL = (USB->DIEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_SNAK | USB_DIEP_CTL_STALL;
-      }
-
-      /* Flush the FIFO */
-      uint8_t const fifo_num = ((USB->DIEP[epnum - 1].CTL & _USB_DIEP_CTL_TXFNUM_MASK) >> _USB_DIEP_CTL_TXFNUM_SHIFT);
-      flush_tx_fifo(fifo_num);
-    }
-  }
-  else
-  {
-    if(epnum == 0)
-    {
-      USB->DOEP0CTL = (USB->DOEP0CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP0CTL_STALL;
-    }
-    else
-    {
-      /* Only disable currently enabled non-control endpoint */
-      if(USB->DOEP[epnum - 1].CTL & USB_DIEP_CTL_EPENA) 
-      {
-        /* Asserting GONAK is required to STALL an OUT endpoint. */
-        USB->DCTL |= USB_DCTL_SGOUTNAK;
-        while(!(USB->GINTSTS & USB_GINTSTS_GOUTNAKEFF));
-        
-        /* Disable the endpoint. Note that only STALL and not SNAK is set here. */
-        USB->DOEP[epnum - 1].CTL = (USB->DOEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_EPDIS | USB_DIEP_CTL_STALL;
-        while(USB->DOEP[epnum - 1].INT & USB_DIEP_INT_EPDISBLD);
-        USB->DOEP[epnum - 1].INT |= USB_DIEP_INT_EPDISBLD;
-
-        /* Allow other OUT endpoints to keep receiving. */
-        USB->DCTL |= USB_DCTL_CGOUTNAK;
-      }
-      else
-      {
-        USB->DIEP[epnum - 1].CTL = (USB->DIEP[epnum - 1].CTL & ~DEPCTL_WO_BITMASK) | USB_DIEP_CTL_STALL;
-      }
-    }
-  }
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir = tu_edpt_dir(ep_addr);
-
-  if(dir == TUSB_DIR_IN)
-  {
-    if(epnum == 0)
-    {
-      USB->DIEP0CTL &= ~(DEPCTL_WO_BITMASK | USB_DIEP0CTL_STALL);
-    }
-    else
-    {
-      USB->DIEP[epnum - 1].CTL &= ~(DEPCTL_WO_BITMASK | USB_DIEP_CTL_STALL);
-    
-      /* Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints. */
-      uint8_t eptype = (USB->DIEP[epnum - 1].CTL & _USB_DIEP_CTL_EPTYPE_MASK) >> _USB_DIEP_CTL_EPTYPE_SHIFT;
-
-      if((eptype == _USB_DIEP_CTL_EPTYPE_BULK) || (eptype == _USB_DIEP_CTL_EPTYPE_INT))
-      {
-        USB->DIEP[epnum - 1].CTL |= USB_DIEP_CTL_SETD0PIDEF;
-      }
-    }
-  }
-  else
-  {
-    if(epnum == 0)
-    {
-      USB->DOEP0CTL &= ~(DEPCTL_WO_BITMASK | USB_DOEP0CTL_STALL);
-    }
-    else
-    {
-      USB->DOEP[epnum - 1].CTL &= ~(DEPCTL_WO_BITMASK | USB_DOEP_CTL_STALL);
-    
-      /* Required by USB spec to reset DATA toggle bit to DATA0 on interrupt and bulk endpoints. */
-      uint8_t eptype = (USB->DOEP[epnum - 1].CTL & _USB_DOEP_CTL_EPTYPE_MASK) >> _USB_DOEP_CTL_EPTYPE_SHIFT;
-
-      if((eptype == _USB_DOEP_CTL_EPTYPE_BULK) || (eptype == _USB_DOEP_CTL_EPTYPE_INT))
-      {
-        USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_SETD0PIDEF;
-      }
-    }
-  }
-}
-
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
-{
-  (void)rhport;
-
-  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-
-  TU_ASSERT(epnum < EP_COUNT);
-  TU_ASSERT(epnum != 0);
-
-  xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = tu_edpt_packet_size(p_endpoint_desc);
-
-  if(dir == TUSB_DIR_OUT)
-  {
-    USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_USBACTEP |
-                                (p_endpoint_desc->bmAttributes.xfer << _USB_DOEP_CTL_EPTYPE_SHIFT) |
-                                (xfer->max_size << _USB_DOEP_CTL_MPS_SHIFT);
-    USB->DAINTMSK |= (1 << (_USB_DAINTMSK_OUTEPMSK0_SHIFT + epnum));
-  }
-  else
-  {
-    uint8_t fifo_num = get_free_fifo();
-    TU_ASSERT(fifo_num != 0);
-
-    USB->DIEP[epnum - 1].CTL &= ~(_USB_DIEP_CTL_TXFNUM_MASK | _USB_DIEP_CTL_EPTYPE_MASK | USB_DIEP_CTL_SETD0PIDEF | _USB_DIEP_CTL_MPS_MASK);
-    USB->DIEP[epnum - 1].CTL |= USB_DIEP_CTL_USBACTEP |
-                                (fifo_num << _USB_DIEP_CTL_TXFNUM_SHIFT) |
-                                (p_endpoint_desc->bmAttributes.xfer << _USB_DIEP_CTL_EPTYPE_SHIFT) |
-                                ((p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) ? USB_DIEP_CTL_SETD0PIDEF : 0) |
-                                (xfer->max_size << 0);
-
-    USB->DAINTMSK |= (1 << epnum);
-
-    /* Both TXFD and TXSA are in unit of 32-bit words. */
-    /* IN FIFO 0 was configured during enumeration, hence the "+ 16". */
-    uint16_t const allocated_size = (USB->GRXFSIZ & _USB_GRXFSIZ_RXFDEP_MASK) + 16;
-    uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_FIFO_NUM-1);
-    uint32_t const fifo_offset = allocated_size + fifo_size*(fifo_num-1);
-
-    /* DIEPTXF starts at FIFO #1. */
-    volatile uint32_t* usb_dieptxf = &USB->DIEPTXF1;
-    usb_dieptxf[epnum - 1] = (fifo_size << _USB_DIEPTXF1_INEPNTXFDEP_SHIFT) | fifo_offset;
-  }
-  return true;
-}
-
-void dcd_edpt_close_all (uint8_t rhport)
-{
-  (void) rhport;
-  // TODO implement dcd_edpt_close_all()
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
-{
-  (void)rhport;
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer       = buffer;
-  xfer->total_len    = total_bytes;
-  xfer->queued_len   = 0;
-  xfer->short_packet = false;
-
-  uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint8_t short_packet_size = total_bytes % xfer->max_size;
-
-  // Zero-size packet is special case.
-  if(short_packet_size > 0 || (total_bytes == 0))
-  {
-    num_packets++;
-  }
-
-  // IN and OUT endpoint xfers are interrupt-driven, we just schedule them
-  // here.
-  if(dir == TUSB_DIR_IN)
-  {
-    if(epnum == 0)
-    {
-      // A full IN transfer (multiple packets, possibly) triggers XFRC.
-      USB->DIEP0TSIZ = (num_packets << _USB_DIEP0TSIZ_PKTCNT_SHIFT) | total_bytes;
-      USB->DIEP0CTL |= USB_DIEP0CTL_EPENA | USB_DIEP0CTL_CNAK; // Enable | CNAK
-    }
-    else
-    {
-      // A full IN transfer (multiple packets, possibly) triggers XFRC.
-      USB->DIEP[epnum - 1].TSIZ = (num_packets << _USB_DIEP_TSIZ_PKTCNT_SHIFT) | total_bytes;
-      USB->DIEP[epnum - 1].CTL |= USB_DIEP_CTL_EPENA | USB_DIEP_CTL_CNAK; // Enable | CNAK
-    }
-    
-    // Enable fifo empty interrupt only if there are something to put in the fifo.
-    if(total_bytes != 0)
-    {
-      USB->DIEPEMPMSK |= (1 << epnum);
-    }
-  }
-  else
-  {
-    if(epnum == 0)
-    {
-      // A full IN transfer (multiple packets, possibly) triggers XFRC.
-      USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP0TSIZ_XFERSIZE_MASK) << _USB_DOEP0TSIZ_XFERSIZE_SHIFT);
-      USB->DOEP0CTL |= USB_DOEP0CTL_EPENA | USB_DOEP0CTL_CNAK;
-    }
-    else
-    {
-      // A full IN transfer (multiple packets, possibly) triggers XFRC.
-      USB->DOEP[epnum - 1].TSIZ |= (1 << _USB_DOEP_TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP_TSIZ_XFERSIZE_MASK) << _USB_DOEP_TSIZ_XFERSIZE_SHIFT);
-      USB->DOEP[epnum - 1].CTL |= USB_DOEP_CTL_EPENA | USB_DOEP_CTL_CNAK;
-    }
-  }
-  return true;
-}
-
-/*------------------------------------------------------------------*/
-/* IRQ                                                              */
-/*------------------------------------------------------------------*/
-void dcd_int_enable(uint8_t rhport)
-{
-  (void) rhport;
-
-  NVIC_EnableIRQ(USB_IRQn);
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  (void) rhport;
-
-  NVIC_DisableIRQ(USB_IRQn);
-}
-
-static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size)
-{
-  uint16_t remaining = xfer->total_len - xfer->queued_len;
-  uint16_t to_recv_size;
-
-  if(remaining <= xfer->max_size)
-  {
-    /* Avoid buffer overflow. */
-    to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
-  }
-  else
-  {
-    /* Room for full packet, choose recv_size based on what the microcontroller claims. */
-    to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
-  }
-
-  uint8_t to_recv_rem = to_recv_size % 4;
-  uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem;
-
-  /* Do not assume xfer buffer is aligned. */
-  uint8_t *base = (xfer->buffer + xfer->queued_len);
-
-  /* This for loop always runs at least once- skip if less than 4 bytes to collect. */
-  if(to_recv_size >= 4)
-  {
-    for(uint16_t i = 0; i < to_recv_size_aligned; i += 4)
-    {
-      uint32_t tmp = (*USB->FIFO0D);
-      base[i] = tmp & 0x000000FF;
-      base[i + 1] = (tmp & 0x0000FF00) >> 8;
-      base[i + 2] = (tmp & 0x00FF0000) >> 16;
-      base[i + 3] = (tmp & 0xFF000000) >> 24;
-    }
-  }
-
-  /* Do not read invalid bytes from RX FIFO. */
-  if(to_recv_rem != 0)
-  {
-    uint32_t tmp = (*USB->FIFO0D);
-    uint8_t *last_32b_bound = base + to_recv_size_aligned;
-
-    last_32b_bound[0] = tmp & 0x000000FF;
-    if(to_recv_rem > 1)
-    {
-      last_32b_bound[1] = (tmp & 0x0000FF00) >> 8;
-    }
-    if(to_recv_rem > 2)
-    {
-      last_32b_bound[2] = (tmp & 0x00FF0000) >> 16;
-    }
-  }
-
-  xfer->queued_len += xfer_size;
-
-  /* Per USB spec, a short OUT packet (including length 0) is always */
-  /* indicative of the end of a transfer (at least for ctl, bulk, int). */
-  xfer->short_packet = (xfer_size < xfer->max_size);
-}
-
-static void transmit_packet(xfer_ctl_t *xfer, uint8_t fifo_num)
-{
-  uint16_t remaining;
-  if(fifo_num == 0)
-  {
-    remaining = (USB->DIEP0TSIZ & 0x7FFFFU) >> _USB_DIEP0TSIZ_XFERSIZE_SHIFT;
-  }
-  else
-  {
-    remaining = (USB->DIEP[fifo_num - 1].TSIZ & 0x7FFFFU) >> _USB_DIEP_TSIZ_XFERSIZE_SHIFT;
-  }
-  xfer->queued_len = xfer->total_len - remaining;
-
-  uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining;
-  uint8_t to_xfer_rem = to_xfer_size % 4;
-  uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem;
-
-  /* Buffer might not be aligned to 32b, so we need to force alignment by copying to a temp var. */
-  uint8_t *base = (xfer->buffer + xfer->queued_len);
-
-  /* This for loop always runs at least once- skip if less than 4 bytes to send off. */
-  if(to_xfer_size >= 4)
-  {
-    for(uint16_t i = 0; i < to_xfer_size_aligned; i += 4)
-    {
-      uint32_t tmp = base[i] | (base[i + 1] << 8) | (base[i + 2] << 16) | (base[i + 3] << 24);
-      *tx_fifo[fifo_num] = tmp;
-    }
-  }
-
-  /* Do not read beyond end of buffer if not divisible by 4. */
-  if(to_xfer_rem != 0)
-  {
-    uint32_t tmp = 0;
-    uint8_t *last_32b_bound = base + to_xfer_size_aligned;
-
-    tmp |= last_32b_bound[0];
-    if(to_xfer_rem > 1)
-    {
-      tmp |= (last_32b_bound[1] << 8);
-    }
-    if(to_xfer_rem > 2)
-    {
-      tmp |= (last_32b_bound[2] << 16);
-    }
-
-    *tx_fifo[fifo_num] = tmp;
-  }
-}
-
-static void read_rx_fifo(void)
-{
-  /*
-   * Pop control word off FIFO (completed xfers will have 2 control words,
-   * we only pop one ctl word each interrupt).
-   */
-  uint32_t const ctl_word = USB->GRXSTSP;
-  uint8_t  const pktsts   = (ctl_word & _USB_GRXSTSP_PKTSTS_MASK) >> _USB_GRXSTSP_PKTSTS_SHIFT;
-  uint8_t  const epnum    = (ctl_word & _USB_GRXSTSP_CHNUM_MASK ) >> _USB_GRXSTSP_CHNUM_SHIFT;
-  uint16_t const bcnt     = (ctl_word & _USB_GRXSTSP_BCNT_MASK  ) >> _USB_GRXSTSP_BCNT_SHIFT;
-
-  switch(pktsts)
-  {
-    case 0x01: /* Global OUT NAK (Interrupt) */
-      break;
-
-    case 0x02:
-    { 
-      /* Out packet recvd */
-      xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
-      receive_packet(xfer, bcnt);
-    }
-    break;
-
-    case 0x03:
-      /* Out packet done (Interrupt) */
-      break;
-
-    case 0x04: 
-      /* Step 2: Setup transaction completed (Interrupt) */
-      /* After this event, OEPINT interrupt will occur with SETUP bit set */
-      if(epnum == 0)
-      {
-        USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_SUPCNT_SHIFT);
-      }
-      
-      break;
-
-    case 0x06:
-    { 
-      /* Step1: Setup data packet received */
-
-      /*
-       * We can receive up to three setup packets in succession, but
-       * only the last one is valid. Therefore we just overwrite it
-       */
-      _setup_packet[0] = (*USB->FIFO0D);
-      _setup_packet[1] = (*USB->FIFO0D);
-    }
-    break;
-
-    default: 
-      /* Invalid, breakpoint. */
-      TU_BREAKPOINT();
-      break;
-  }
-}
-
-static void handle_epout_ints(void)
-{
-  // GINTSTS will be cleared with DAINT == 0
-  // DAINT for a given EP clears when DOEPINTx is cleared.
-  // DOEPINT will be cleared when DAINT's out bits are cleared.
-
-  for(uint8_t n = 0; n < EP_COUNT; n++)
-  {
-    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
-
-    if(n == 0)
-    {
-      if(USB->DAINT & (1 << (_USB_DAINT_OUTEPINT0_SHIFT + n)))
-      {
-        // SETUP packet Setup Phase done.
-        if((USB->DOEP0INT & USB_DOEP0INT_SETUP))
-        {
-          USB->DOEP0INT = USB_DOEP0INT_STUPPKTRCVD | USB_DOEP0INT_SETUP; // clear
-          dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
-        }
-
-        // OUT XFER complete (single packet).q
-        if(USB->DOEP0INT & USB_DOEP0INT_XFERCOMPL)
-        {
-          USB->DOEP0INT = USB_DOEP0INT_XFERCOMPL;
-
-          // Transfer complete if short packet or total len is transferred
-          if(xfer->short_packet || (xfer->queued_len == xfer->total_len))
-          {
-            xfer->short_packet = false;
-            dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-          }
-          else
-          {
-            // Schedule another packet to be received.
-            USB->DOEP0TSIZ |= (1 << _USB_DOEP0TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP0TSIZ_XFERSIZE_MASK) << _USB_DOEP0TSIZ_XFERSIZE_SHIFT);
-            USB->DOEP0CTL |= USB_DOEP0CTL_EPENA | USB_DOEP0CTL_CNAK;
-          }
-        }
-      }
-    }
-    else
-    {
-      if(USB->DAINT & (1 << (_USB_DAINT_OUTEPINT0_SHIFT + n)))
-      {
-        // SETUP packet Setup Phase done.
-        if((USB->DOEP[n - 1].INT & USB_DOEP_INT_SETUP))
-        {
-          USB->DOEP[n - 1].INT = USB_DOEP_INT_STUPPKTRCVD | USB_DOEP_INT_SETUP; // clear
-          dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
-        }
-
-        // OUT XFER complete (single packet).q
-        if(USB->DOEP[n - 1].INT & USB_DOEP_INT_XFERCOMPL)
-        {
-          USB->DOEP[n - 1].INT = USB_DOEP_INT_XFERCOMPL;
-
-          // Transfer complete if short packet or total len is transferred
-          if(xfer->short_packet || (xfer->queued_len == xfer->total_len))
-          {
-            xfer->short_packet = false;
-            dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-          }
-          else
-          {
-            // Schedule another packet to be received.
-            USB->DOEP[n - 1].TSIZ |= (1 << _USB_DOEP_TSIZ_PKTCNT_SHIFT) | ((xfer->max_size & _USB_DOEP_TSIZ_XFERSIZE_MASK) << _USB_DOEP_TSIZ_XFERSIZE_SHIFT);
-            USB->DOEP[n - 1].CTL |= USB_DOEP_CTL_EPENA | USB_DOEP_CTL_CNAK;
-          }
-        }
-      }
-    }
-  }
-}
-
-static void handle_epin_ints(void)
-{
-
-  for(uint32_t n = 0; n < EP_COUNT; n++)
-  {
-    xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN];
-
-    if(n == 0)
-    {
-      if(USB->DAINT & (1 << n))
-      {
-        /* IN XFER complete (entire xfer). */
-        if(USB->DIEP0INT & USB_DIEP0INT_XFERCOMPL)
-        {
-          USB->DIEP0INT = USB_DIEP0INT_XFERCOMPL;
-          dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        }
-
-        /* XFER FIFO empty */
-        if(USB->DIEP0INT & USB_DIEP0INT_TXFEMP)
-        {
-          USB->DIEP0INT = USB_DIEP0INT_TXFEMP;
-          transmit_packet(xfer, n);
-
-          /* Turn off TXFE if all bytes are written. */
-          if(xfer->queued_len == xfer->total_len)
-          {
-            USB->DIEPEMPMSK  &= ~(1 << n);
-          }
-        }
-
-        /* XFER Timeout */
-        if(USB->DIEP0INT & USB_DIEP0INT_TIMEOUT)
-        {
-          /* Clear interrupt or enpoint will hang. */
-          USB->DIEP0INT = USB_DIEP0INT_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      if(USB->DAINT & (1 << n))
-      {
-        /* IN XFER complete (entire xfer). */
-        if(USB->DIEP[n - 1].INT & USB_DIEP_INT_XFERCOMPL)
-        {
-          USB->DIEP[n - 1].INT = USB_DIEP_INT_XFERCOMPL;
-          dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        }
-
-        /* XFER FIFO empty */
-        if(USB->DIEP[n - 1].INT & USB_DIEP_INT_TXFEMP)
-        {
-          USB->DIEP[n - 1].INT = USB_DIEP_INT_TXFEMP;
-          transmit_packet(xfer, n);
-
-          /* Turn off TXFE if all bytes are written. */
-          if(xfer->queued_len == xfer->total_len)
-          {
-            USB->DIEPEMPMSK  &= ~(1 << n);
-          }
-        }
-
-        /* XFER Timeout */
-        if(USB->DIEP[n - 1].INT & USB_DIEP_INT_TIMEOUT)
-        {
-          /* Clear interrupt or enpoint will hang. */
-          USB->DIEP[n - 1].INT = USB_DIEP_INT_TIMEOUT;
-        }
-      }
-    }
-  }
-}
-
-void dcd_int_handler(uint8_t rhport)
-{
-  (void) rhport;
-
-  const uint32_t int_status = USB->GINTSTS;
-
-  /* USB Reset */
-  if(int_status & USB_GINTSTS_USBRST)
-  {
-    /* start of reset */
-    USB->GINTSTS = USB_GINTSTS_USBRST;
-    /* FIFOs will be reassigned when the endpoints are reopen */
-    _allocated_fifos = 1;
-    bus_reset();
-  }
-
-  /* Reset detected Interrupt */
-  if(int_status & USB_GINTSTS_RESETDET)
-  {
-    USB->GINTSTS = USB_GINTSTS_RESETDET;
-    bus_reset();
-  }
-
-  /* Enumeration Done */
-  if(int_status & USB_GINTSTS_ENUMDONE)
-  {
-    /* This interrupt is considered the end of reset. */
-    USB->GINTSTS = USB_GINTSTS_ENUMDONE;
-    enum_done_processing();
-    dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
-  }
-
-  /* OTG Interrupt */
-  if(int_status & USB_GINTSTS_OTGINT)
-  {
-    /* OTG INT bit is read-only */
-
-    uint32_t const otg_int = USB->GOTGINT;
-
-    if(otg_int & USB_GOTGINT_SESENDDET)
-    {
-      dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
-    }
-
-    USB->GOTGINT = otg_int;
-  }
-
-  #if USE_SOF
-  if(int_status & USB_GINTSTS_SOF)
-  {
-    USB->GINTSTS = USB_GINTSTS_SOF;
-    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
-  }
-  #endif
-
-  /* RxFIFO Non-Empty */
-  if(int_status & USB_GINTSTS_RXFLVL)
-  {
-    /* RXFLVL bit is read-only */
-
-    /* Mask out RXFLVL while reading data from FIFO */
-    USB->GINTMSK &= ~USB_GINTMSK_RXFLVLMSK;
-    read_rx_fifo();
-    USB->GINTMSK |= USB_GINTMSK_RXFLVLMSK;
-  }
-
-  /* OUT Endpoints Interrupt */
-  if(int_status & USB_GINTMSK_OEPINTMSK)
-  {
-    /* OEPINT is read-only */
-    handle_epout_ints();
-  }
-
-  /* IN Endpoints Interrupt */
-  if(int_status & USB_GINTMSK_IEPINTMSK)
-  {
-    /* IEPINT bit read-only */
-    handle_epin_ints();
-  }
-
-  /* unhandled */
-  USB->GINTSTS |= USB_GINTSTS_CURMOD      |
-                  USB_GINTSTS_MODEMIS     |
-                  USB_GINTSTS_OTGINT      |
-                  USB_GINTSTS_NPTXFEMP    |
-                  USB_GINTSTS_GINNAKEFF   |
-                  USB_GINTSTS_GOUTNAKEFF  |
-                  USB_GINTSTS_ERLYSUSP    |
-                  USB_GINTSTS_USBSUSP     |
-                  USB_GINTSTS_ISOOUTDROP  |
-                  USB_GINTSTS_EOPF        |
-                  USB_GINTSTS_EPMIS       |
-                  USB_GINTSTS_INCOMPISOIN |
-                  USB_GINTSTS_INCOMPLP    |
-                  USB_GINTSTS_FETSUSP     |
-                  USB_GINTSTS_PTXFEMP;
-}
-
-#endif
diff --git a/src/portable/synopsys/dwc2/dwc2_efm32.h b/src/portable/synopsys/dwc2/dwc2_efm32.h
new file mode 100644
index 000000000..ee4c3c715
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_efm32.h
@@ -0,0 +1,87 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Rafael Silva (@perigoso)
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _DWC2_EFM32_H_
+#define _DWC2_EFM32_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "em_device.h"
+
+// EFM32 has custom control register before DWC registers
+#define DWC2_REG_BASE       (USB_BASE + offsetof(USB_TypeDef, GOTGCTL))
+#define DWC2_EP_MAX         7
+#define DWC2_EP_FIFO_SIZE   2048
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USB_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB_IRQn);
+}
+
+static inline void dwc2_remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+//  uint32_t count = SystemCoreClock / 1000;
+//  while ( count-- ) __NOP();
+}
+
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+  (void) dwc2;
+  (void) hs_phy_type;
+
+  // Enable PHY
+  USB->ROUTE = USB_ROUTE_PHYPEN;
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+  (void) dwc2;
+  (void) hs_phy_type;
+
+  // EFM32 Manual: turn around must be 5 (reset & default value)
+  // dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

From 215e0595ab568215a7d0a0c927b076bd02951fa6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 31 Oct 2021 00:09:40 +0700
Subject: [PATCH 0620/2085] change F207 to use new dwc2

---
 hw/bsp/stm32f207nucleo/board.mk                | 2 +-
 hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk | 3 +++
 src/portable/synopsys/dwc2/dcd_dwc2.c          | 6 +++---
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/stm32f207nucleo/board.mk b/hw/bsp/stm32f207nucleo/board.mk
index 2b979f3d8..fa7d28399 100644
--- a/hw/bsp/stm32f207nucleo/board.mk
+++ b/hw/bsp/stm32f207nucleo/board.mk
@@ -21,7 +21,7 @@ CFLAGS += -Wno-error=sign-compare
 LD_FILE = hw/bsp/$(BOARD)/STM32F207ZGTx_FLASH.ld
 
 SRC_C += \
-  src/portable/st/synopsys/dcd_synopsys.c \
+  src/portable/synopsys/dwc2/dcd_dwc2.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
index 2400a4ba7..7710619e5 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
@@ -8,5 +8,8 @@ CFLAGS += \
 LD_FILE = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f767xx.s
 
+# For flash-jlink target
+JLINK_DEVICE = stm32f767zi
+
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 16780cba8..e2a999ac0 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -264,9 +264,9 @@ void print_dwc2_info(dwc2_regs_t * dwc2)
   dwc2_ghwcfg3_t const * hw_cfg3 = &dwc2->ghwcfg3_bm;
   dwc2_ghwcfg4_t const * hw_cfg4 = &dwc2->ghwcfg4_bm;
 
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl);
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
-  TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg);
+//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl);
+//  TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg);
+//  TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg);
   TU_LOG_HEX(DWC2_DEBUG, dwc2->guid);
   TU_LOG_HEX(DWC2_DEBUG, dwc2->gsnpsid);
   TU_LOG_HEX(DWC2_DEBUG, dwc2->ghwcfg1);

From 4ea8f1441dda442d784ee57f39a0adc75bf69e56 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 31 Oct 2021 00:19:17 +0700
Subject: [PATCH 0621/2085] correct freertos port for efm32gg

---
 examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12       | 0
 examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12 | 0
 hw/bsp/sltb009a/board.mk                                   | 6 +-----
 3 files changed, 1 insertion(+), 5 deletions(-)
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12

diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12 b/examples/device/cdc_msc_freertos/.skip.MCU_EFM32GG12
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12 b/examples/device/hid_composite_freertos/.skip.MCU_EFM32GG12
deleted file mode 100644
index e69de29bb..000000000
diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index 7a046b34b..f5c240ca2 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -34,12 +34,8 @@ INC += \
   $(TOP)/$(SILABS_CMSIS)/Include \
   $(TOP)/hw/bsp/$(BOARD)
 
-# For TinyUSB port source
-VENDOR = silabs
-CHIP_FAMILY = efm32
-
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4
+FREERTOS_PORT = ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = EFM32GG12B810F1024

From ba34f420db26faf7d42f574cce0c3b4c0f4ccb38 Mon Sep 17 00:00:00 2001
From: Jean Gressmann <jean@0x42.de>
Date: Sat, 30 Oct 2021 14:39:03 +0200
Subject: [PATCH 0622/2085] Adds support for Adafruit Trinket M0

---
 hw/bsp/samd21/boards/trinket_m0/board.h       |  34 ++++
 hw/bsp/samd21/boards/trinket_m0/board.mk      |   5 +
 hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld | 146 ++++++++++++++++++
 hw/bsp/samd21/family.c                        |  83 ++++++++++
 4 files changed, 268 insertions(+)
 create mode 100644 hw/bsp/samd21/boards/trinket_m0/board.h
 create mode 100644 hw/bsp/samd21/boards/trinket_m0/board.mk
 create mode 100644 hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld

diff --git a/hw/bsp/samd21/boards/trinket_m0/board.h b/hw/bsp/samd21/boards/trinket_m0/board.h
new file mode 100644
index 000000000..c8692e6bd
--- /dev/null
+++ b/hw/bsp/samd21/boards/trinket_m0/board.h
@@ -0,0 +1,34 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Jean Gressmann <jean@0x42.de>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#pragma once
+
+// LED
+#define LED_PIN               10 // PA10
+#define LED_STATE_ON          1
+
+// UART
+#define UART_SERCOM           0
+
diff --git a/hw/bsp/samd21/boards/trinket_m0/board.mk b/hw/bsp/samd21/boards/trinket_m0/board.mk
new file mode 100644
index 000000000..803ffe892
--- /dev/null
+++ b/hw/bsp/samd21/boards/trinket_m0/board.mk
@@ -0,0 +1,5 @@
+CFLAGS += -D__SAMD21E18A__ -DCFG_EXAMPLE_VIDEO_READONLY
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/trinket_m0.ld
+
diff --git a/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld b/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld
new file mode 100644
index 000000000..f0c93340c
--- /dev/null
+++ b/hw/bsp/samd21/boards/trinket_m0/trinket_m0.ld
@@ -0,0 +1,146 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2017 Microchip Technology Inc.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the Licence at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+  rom      (rx)  : ORIGIN = 0x00000000 + 8K, LENGTH = 0x00040000 - 8K
+  ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+ENTRY(Reset_Handler)
+
+/* Section Definitions */
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+    .ARM.exidx :
+    {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+    .relocate : AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+        end = .;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+    _end = . ;
+}
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index 10e40e3f0..3fa6ea7d8 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -44,6 +44,11 @@ void USB_Handler(void)
   tud_int_handler(0);
 }
 
+//--------------------------------------------------------------------+
+// UART support
+//--------------------------------------------------------------------+
+void uart_init(void);
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
@@ -84,6 +89,8 @@ void board_init(void)
   gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULL_DOWN : GPIO_PULL_UP);
 #endif
 
+  uart_init();
+
 #if CFG_TUSB_OS  == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
@@ -138,6 +145,81 @@ uint32_t board_button_read(void)
 #endif
 }
 
+#if defined(UART_SERCOM)
+
+#define BOARD_SERCOM2(n)  SERCOM ## n
+#define BOARD_SERCOM(n) BOARD_SERCOM2(n)
+
+void uart_init(void)
+{
+#if UART_SERCOM == 0
+  gpio_set_pin_function(PIN_PA06, PINMUX_PA06D_SERCOM0_PAD2);
+  gpio_set_pin_function(PIN_PA07, PINMUX_PA07D_SERCOM0_PAD3);
+
+  // setup clock (48MHz)
+  _pm_enable_bus_clock(PM_BUS_APBC, SERCOM0);
+  _gclk_enable_channel(SERCOM0_GCLK_ID_CORE, GCLK_CLKCTRL_GEN_GCLK0_Val);
+
+  SERCOM0->USART.CTRLA.bit.SWRST = 1; /* reset SERCOM & enable config */
+  while(SERCOM0->USART.SYNCBUSY.bit.SWRST);
+
+  SERCOM0->USART.CTRLA.reg  =  /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */
+    SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */
+//    SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */
+    SERCOM_USART_CTRLA_DORD | /* LSB first */
+    SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */
+    SERCOM_USART_CTRLA_RXPO(3) | /* pad 3 */
+    SERCOM_USART_CTRLA_TXPO(1);  /* pad 2 */
+
+  SERCOM0->USART.CTRLB.reg =
+    SERCOM_USART_CTRLB_TXEN | /* tx enabled */
+    SERCOM_USART_CTRLB_RXEN;  /* rx enabled */
+
+  SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(0) | SERCOM_USART_BAUD_FRAC_BAUD(26);
+
+  SERCOM0->USART.CTRLA.bit.ENABLE = 1; /* activate SERCOM */
+  while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */
+#endif
+}
+
+static inline void uart_send_buffer(uint8_t const *text, size_t len)
+{
+  for (size_t i = 0; i < len; ++i) {
+    BOARD_SERCOM(UART_SERCOM)->USART.DATA.reg = text[i];
+    while((BOARD_SERCOM(UART_SERCOM)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
+  }
+}
+
+static inline void uart_send_str(const char* text)
+{
+  while (*text) {
+    BOARD_SERCOM(UART_SERCOM)->USART.DATA.reg = *text++;
+    while((BOARD_SERCOM(UART_SERCOM)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) == 0);
+  }
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  if (len < 0) {
+    uart_send_str(buf);
+  } else {
+    uart_send_buffer(buf, len);
+  }
+  return len;
+}
+
+#else // ! defined(UART_SERCOM)
+void uart_init(void)
+{
+
+}
+
 int board_uart_read(uint8_t* buf, int len)
 {
   (void) buf; (void) len;
@@ -149,6 +231,7 @@ int board_uart_write(void const * buf, int len)
   (void) buf; (void) len;
   return 0;
 }
+#endif
 
 #if CFG_TUSB_OS  == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;

From 5fb16a8f2c2c160e9e3e3c1161b038b6fc421c14 Mon Sep 17 00:00:00 2001
From: Jean Gressmann <jean@0x42.de>
Date: Mon, 1 Nov 2021 18:01:18 +0100
Subject: [PATCH 0623/2085] samd21: enable SysTick only if running w/o OS

---
 hw/bsp/samd21/family.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index 3fa6ea7d8..cead582e9 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -75,7 +75,9 @@ void board_init(void)
   // Update SystemCoreClock since it is hard coded with asf4 and not correct
   // Init 1ms tick timer (samd SystemCoreClock may not correct)
   SystemCoreClock = CONF_CPU_FREQUENCY;
+#if CFG_TUSB_OS  == OPT_OS_NONE
   SysTick_Config(CONF_CPU_FREQUENCY / 1000);
+#endif
 
   // Led init
 #ifdef LED_PIN

From aa682d730123a1191782b1a160ce25ea20580ee6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Nov 2021 13:52:30 +0700
Subject: [PATCH 0624/2085] add fix for stm32l4 (version 3.10a) which generate
 transfer complete when setup recieved and control out data complete

---
 hw/bsp/stm32l476disco/board.mk         |   6 +-
 hw/bsp/stm32l476disco/stm32l476disco.c |   8 +-
 src/device/dcd_attr.h                  |   1 +
 src/portable/synopsys/dwc2/dcd_dwc2.c  | 151 +++++++++++++++++--------
 src/portable/synopsys/dwc2/dwc2_type.h |  11 ++
 5 files changed, 122 insertions(+), 55 deletions(-)

diff --git a/hw/bsp/stm32l476disco/board.mk b/hw/bsp/stm32l476disco/board.mk
index 28824efdc..8d9e267cf 100644
--- a/hw/bsp/stm32l476disco/board.mk
+++ b/hw/bsp/stm32l476disco/board.mk
@@ -21,8 +21,9 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/STM32L476VGTx_FLASH.ld
 
+#src/portable/st/synopsys/dcd_synopsys.c
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -52,5 +53,4 @@ JLINK_DEVICE = stm32l476vg
 STM32Prog = STM32_Programmer_CLI
 
 # flash target using on-board stlink
-flash: $(BUILD)/$(PROJECT).elf
-	$(STM32Prog) --connect port=swd --write $< --go
+flash: flash-stlink
diff --git a/hw/bsp/stm32l476disco/stm32l476disco.c b/hw/bsp/stm32l476disco/stm32l476disco.c
index b18846685..bc1b6c929 100644
--- a/hw/bsp/stm32l476disco/stm32l476disco.c
+++ b/hw/bsp/stm32l476disco/stm32l476disco.c
@@ -186,8 +186,12 @@ void board_init(void)
   /* Enable USB FS Clock */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+//  // Enable VBUS sense (B device) via pin PA9
+//  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+
+  // L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others
+  // Disable VBUS Sense and force device mode
+  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 70854f9c6..952a8b8c8 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -125,6 +125,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_STM32L4)
   #if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
       defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
+      defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
       defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
       defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
     #define DCD_ATTR_ENDPOINT_MAX   6
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index e2a999ac0..83abc635b 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -123,8 +123,8 @@ static void bus_reset(uint8_t rhport)
     dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
   }
 
-  // 2. Un-mask interrupt bits
-  dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
+  // 2. Set up interrupt mask
+  dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
   dwc2->doepmsk  = DOEPMSK_STUPM | DOEPMSK_XFRCM;
   dwc2->diepmsk  = DIEPMSK_TOM   | DIEPMSK_XFRCM;
 
@@ -472,9 +472,6 @@ void dcd_init (uint8_t rhport)
   // Restart PHY clock
   dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
 
-  // Force device mode
-  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
-
 	/* Set HS/FS Timeout Calibration to 7 (max available value).
 	 * The number of PHY clocks that the application programs in
 	 * this field is added to the high/full speed interpacket timeout
@@ -485,13 +482,16 @@ void dcd_init (uint8_t rhport)
 	 */
   dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
 
+  // Force device mode
+  dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD;
+
+  // Clear A override, force B Valid
+  dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL;
+
   // If USB host misbehaves during status portion of control xfer
   // (non zero-length packet), send STALL back and discard.
   dwc2->dcfg |= DCFG_NZLSOHSK;
 
-  // Clear A,B, VBus valid override
-  dwc2->gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN | GOTGCTL_VBVALOEN);
-
   // Clear all interrupts
   dwc2->gintsts |= dwc2->gintsts;
   dwc2->gotgint |= dwc2->gotgint;
@@ -609,7 +609,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
                                   (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) |
                                   (xfer->max_size << DOEPCTL_MPSIZ_Pos);
 
-    dwc2->daintmsk |= (1 << (DAINTMSK_OEPM_Pos + epnum));
+    dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
   }
   else
   {
@@ -696,19 +696,21 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   if(epnum == 0)
   {
     ep0_pending[dir] = total_bytes;
+
     // Schedule the first transaction for EP0 transfer
     edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
-    return true;
   }
+  else
+  {
+    uint16_t num_packets = (total_bytes / xfer->max_size);
+    uint16_t const short_packet_size = total_bytes % xfer->max_size;
 
-  uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint16_t const short_packet_size = total_bytes % xfer->max_size;
+    // Zero-size packet is special case.
+    if ( (short_packet_size > 0) || (total_bytes == 0) ) num_packets++;
 
-  // Zero-size packet is special case.
-  if ( short_packet_size > 0 || (total_bytes == 0) ) num_packets++;
-
-  // Schedule packets to be sent within interrupt
-  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
+    // Schedule packets to be sent within interrupt
+    edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
+  }
 
   return true;
 }
@@ -924,21 +926,49 @@ static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const *
 static void handle_rxflvl_irq(uint8_t rhport)
 {
   dwc2_regs_t * dwc2 = DWC2_REG(rhport);
-  volatile uint32_t * rx_fifo = dwc2->fifo[0];
+  volatile uint32_t const * rx_fifo = dwc2->fifo[0];
 
   // Pop control word off FIFO
-  uint32_t ctl_word = dwc2->grxstsp;
-  uint8_t  pktsts   = (ctl_word & GRXSTSP_PKTSTS_Msk ) >> GRXSTSP_PKTSTS_Pos;
-  uint8_t  epnum    = (ctl_word & GRXSTSP_EPNUM_Msk  ) >> GRXSTSP_EPNUM_Pos;
-  uint16_t bcnt     = (ctl_word & GRXSTSP_BCNT_Msk   ) >> GRXSTSP_BCNT_Pos;
+  uint32_t const ctl_word = dwc2->grxstsp;
+  uint8_t  const pktsts   = (ctl_word & GRXSTSP_PKTSTS_Msk ) >> GRXSTSP_PKTSTS_Pos;
+  uint8_t  const epnum    = (ctl_word & GRXSTSP_EPNUM_Msk  ) >> GRXSTSP_EPNUM_Pos;
+  uint16_t const bcnt     = (ctl_word & GRXSTSP_BCNT_Msk   ) >> GRXSTSP_BCNT_Pos;
+
+  dwc2_epout_t* epout = &dwc2->epout[epnum];
+
+#if CFG_TUSB_DEBUG >= (DWC2_DEBUG + 1)
+  const char * pktsts_str[] =
+  {
+    "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)",
+    "Setup Complete (ISR)", "ASSERT", "Setup Data Received"
+  };
+  TU_LOG_LOCATION();
+  TU_LOG(DWC2_DEBUG, "  EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]);
+  TU_LOG(DWC2_DEBUG, "  daint = %08lX, doepint = %04lX\r\n", dwc2->daint, epout->doepint);
+#endif
 
   switch ( pktsts )
   {
-    case 0x01:    // Global OUT NAK (Interrupt)
+    // Global OUT NAK: do nothign
+    case GRXSTS_PKTSTS_GLOBALOUTNAK: break;
+
+    case GRXSTS_PKTSTS_SETUPRX:
+      // Setup packet received
+
+      // We can receive up to three setup packets in succession, but
+      // only the last one is valid.
+      _setup_packet[0] = (*rx_fifo);
+      _setup_packet[1] = (*rx_fifo);
     break;
 
-    case 0x02:    // Out packet received
+    case GRXSTS_PKTSTS_SETUPDONE:
+      // Setup packet done (Interrupt)
+      epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
+    break;
+
+    case GRXSTS_PKTSTS_OUTRX:
     {
+      // Out packet received
       xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
 
       // Read packet off RxFIFO
@@ -959,7 +989,7 @@ static void handle_rxflvl_irq(uint8_t rhport)
       // Truncate transfer length in case of short packet
       if ( bcnt < xfer->max_size )
       {
-        xfer->total_len -= (dwc2->epout[epnum].doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
+        xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos;
         if ( epnum == 0 )
         {
           xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
@@ -969,18 +999,28 @@ static void handle_rxflvl_irq(uint8_t rhport)
     }
     break;
 
-    case 0x03:    // Out packet done (Interrupt)
-    break;
+    // Out packet done (Interrupt)
+    case GRXSTS_PKTSTS_OUTDONE:
+        // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a
+        // May (or not) be 3.10a specific feature/bug or depending on MCU configuration
+        // XFRC complete is additionally generated when
+        // - setup packet is received
+        // - complete the data stage of control write is complete
+        if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a))
+        {
+          if (epout->doepint & DOEPINT_STPKTRX)
+          {
+            // skip this "no-data" transfer complete event
+            // STPKTRX will be clear later by setup received handler
+            epout->doepint = DOEPINT_XFRC;
+          }
 
-    case 0x04:    // Setup packet done (Interrupt)
-      dwc2->epout[epnum].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos);
-    break;
-
-    case 0x06:    // Setup packet recvd
-      // We can receive up to three setup packets in succession, but
-      // only the last one is valid.
-      _setup_packet[0] = (*rx_fifo);
-      _setup_packet[1] = (*rx_fifo);
+          if (epout->doepint & DOEPINT_OTEPSPR)
+          {
+            // skip this "no-data" transfer complete event
+            epout->doepint = DOEPINT_XFRC | DOEPINT_OTEPSPR;
+          }
+        }
     break;
 
     default:    // Invalid
@@ -992,27 +1032,38 @@ static void handle_rxflvl_irq(uint8_t rhport)
 static void handle_epout_irq (uint8_t rhport)
 {
   dwc2_regs_t *dwc2 = DWC2_REG(rhport);
-  dwc2_epout_t* epout = dwc2->epout;
 
   // DAINT for a given EP clears when DOEPINTx is cleared.
   // OEPINT will be cleared when DAINT's out bits are cleared.
   for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
   {
-    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
-
-    if ( dwc2->daint & (1 << (DAINT_OEPINT_Pos + n)) )
+    if ( dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n) )
     {
+      dwc2_epout_t* epout = &dwc2->epout[n];
+
+      uint32_t const doepint = epout->doepint;
+
       // SETUP packet Setup Phase done.
-      if ( epout[n].doepint & DOEPINT_STUP )
+      if ( doepint & DOEPINT_STUP )
       {
-        epout[n].doepint = DOEPINT_STUP;
-        dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
+        uint32_t clear_flag = DOEPINT_STUP;
+
+        // STPKTRX is only available for version from 3_00a
+        if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a))
+        {
+          clear_flag |= DOEPINT_STPKTRX;
+        }
+
+        epout->doepint = clear_flag;
+        dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
       }
 
       // OUT XFER complete
-      if ( epout[n].doepint & DOEPINT_XFRC )
+      if ( epout->doepint & DOEPINT_XFRC )
       {
-        epout[n].doepint = DOEPINT_XFRC;
+        epout->doepint = DOEPINT_XFRC;
+
+        xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
 
         // EP0 can only handle one packet
         if ( (n == 0) && ep0_pending[TUSB_DIR_OUT] )
@@ -1038,11 +1089,11 @@ static void handle_epin_irq (uint8_t rhport)
   // IEPINT will be cleared when DAINT's out bits are cleared.
   for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
   {
-    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
-
-    if ( dwc2->daint & (1 << (DAINT_IEPINT_Pos + n)) )
+    if ( dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n) )
     {
       // IN XFER complete (entire xfer).
+      xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
+
       if ( epin[n].diepint & DIEPINT_XFRC )
       {
         epin[n].diepint = DIEPINT_XFRC;
@@ -1215,14 +1266,14 @@ void dcd_int_handler(uint8_t rhport)
   // OUT endpoint interrupt handling.
   if(int_status & GINTSTS_OEPINT)
   {
-    // OEPINT is read-only
+    // OEPINT is read-only, clear using DOEPINTn
     handle_epout_irq(rhport);
   }
 
   // IN endpoint interrupt handling.
   if(int_status & GINTSTS_IEPINT)
   {
-    // IEPINT bit read-only
+    // IEPINT bit read-only, clear using DIEPINTn
     handle_epin_irq(rhport);
   }
 
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 583a7274a..6e52ebc7b 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -907,6 +907,17 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define GRXSTSP_PKTSTS_Msk               (0xFUL << GRXSTSP_PKTSTS_Pos)            // 0x001E0000 */
 #define GRXSTSP_PKTSTS                   GRXSTSP_PKTSTS_Msk                       // OUT EP interrupt mask bits */
 
+#define GRXSTS_PKTSTS_GLOBALOUTNAK       1
+#define GRXSTS_PKTSTS_OUTRX              2
+#define GRXSTS_PKTSTS_HCHIN              2
+#define GRXSTS_PKTSTS_OUTDONE            3
+#define GRXSTS_PKTSTS_HCHIN_XFER_COMP    3
+#define GRXSTS_PKTSTS_SETUPDONE          4
+#define GRXSTS_PKTSTS_DATATOGGLEERR      5
+#define GRXSTS_PKTSTS_SETUPRX            6
+#define GRXSTS_PKTSTS_HCHHALTED          7
+
+
 /********************  Bit definition for DAINTMSK register  ********************/
 #define DAINTMSK_IEPM_Pos                (0U)
 #define DAINTMSK_IEPM_Msk                (0xFFFFUL << DAINTMSK_IEPM_Pos)          // 0x0000FFFF */

From b80942987346bc3731fb3b40696065be039d59a9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Nov 2021 14:51:15 +0700
Subject: [PATCH 0625/2085] minor clean up

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 40 +++++++++++++--------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 83abc635b..9750757aa 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -936,16 +936,16 @@ static void handle_rxflvl_irq(uint8_t rhport)
 
   dwc2_epout_t* epout = &dwc2->epout[epnum];
 
-#if CFG_TUSB_DEBUG >= (DWC2_DEBUG + 1)
-  const char * pktsts_str[] =
-  {
-    "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)",
-    "Setup Complete (ISR)", "ASSERT", "Setup Data Received"
-  };
-  TU_LOG_LOCATION();
-  TU_LOG(DWC2_DEBUG, "  EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]);
-  TU_LOG(DWC2_DEBUG, "  daint = %08lX, doepint = %04lX\r\n", dwc2->daint, epout->doepint);
-#endif
+//#if CFG_TUSB_DEBUG >= DWC2_DEBUG
+//  const char * pktsts_str[] =
+//  {
+//    "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)",
+//    "Setup Complete (ISR)", "ASSERT", "Setup Data Received"
+//  };
+//  TU_LOG_LOCATION();
+//  TU_LOG(DWC2_DEBUG, "  EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]);
+//  TU_LOG(DWC2_DEBUG, "  daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint);
+//#endif
 
   switch ( pktsts )
   {
@@ -1008,17 +1008,19 @@ static void handle_rxflvl_irq(uint8_t rhport)
         // - complete the data stage of control write is complete
         if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a))
         {
-          if (epout->doepint & DOEPINT_STPKTRX)
-          {
-            // skip this "no-data" transfer complete event
-            // STPKTRX will be clear later by setup received handler
-            epout->doepint = DOEPINT_XFRC;
-          }
+          uint32_t doepint = epout->doepint;
 
-          if (epout->doepint & DOEPINT_OTEPSPR)
+          if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR))
           {
             // skip this "no-data" transfer complete event
-            epout->doepint = DOEPINT_XFRC | DOEPINT_OTEPSPR;
+            // Note: STPKTRX will be clear later by setup received handler
+            uint32_t clear_flags = DOEPINT_XFRC;
+
+            if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR;
+
+            epout->doepint = clear_flags;
+
+            // TU_LOG(DWC2_DEBUG, "  FIX extra transfer complete on setup/data compete\r\n");
           }
         }
     break;
@@ -1163,8 +1165,6 @@ void dcd_int_handler(uint8_t rhport)
 
   uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk;
 
-//  TU_LOG_HEX(DWC2_DEBUG, int_status);
-
   if(int_status & GINTSTS_USBRST)
   {
     // USBRST is start of reset.

From 7e688947265075afdaa343e69ec29a2b2cac5f33 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Nov 2021 15:15:54 +0700
Subject: [PATCH 0626/2085] grouping stm32L4 family in bsp

---
 .../stm32l476_disco}/STM32L476VGTx_FLASH.ld   |   0
 .../boards/stm32l476_disco/board.h}           | 151 +------
 .../stm32l4/boards/stm32l476_disco/board.mk   |  10 +
 .../stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld   | 200 +++++++++
 .../stm32l4/boards/stm32l4p5_nucleo/board.h   | 137 ++++++
 .../stm32l4/boards/stm32l4p5_nucleo/board.mk  |  10 +
 .../stm32l4r5_nucleo}/STM32L4RXxI_FLASH.ld    |   0
 .../stm32l4/boards/stm32l4r5_nucleo/board.h   | 137 ++++++
 .../stm32l4/boards/stm32l4r5_nucleo/board.mk  |  14 +
 .../stm32l4r5nucleo.c => stm32l4/family.c}    | 139 ++----
 .../board.mk => stm32l4/family.mk}            |  15 +-
 .../stm32l4xx_hal_conf.h                      |   0
 hw/bsp/stm32l476disco/board.mk                |  56 ---
 hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h   | 419 ------------------
 src/portable/synopsys/dwc2/dcd_dwc2.c         |   2 +-
 15 files changed, 561 insertions(+), 729 deletions(-)
 rename hw/bsp/{stm32l476disco => stm32l4/boards/stm32l476_disco}/STM32L476VGTx_FLASH.ld (100%)
 rename hw/bsp/{stm32l476disco/stm32l476disco.c => stm32l4/boards/stm32l476_disco/board.h} (59%)
 create mode 100644 hw/bsp/stm32l4/boards/stm32l476_disco/board.mk
 create mode 100644 hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld
 create mode 100644 hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h
 create mode 100644 hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk
 rename hw/bsp/{stm32l4r5nucleo => stm32l4/boards/stm32l4r5_nucleo}/STM32L4RXxI_FLASH.ld (100%)
 create mode 100644 hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h
 create mode 100644 hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk
 rename hw/bsp/{stm32l4r5nucleo/stm32l4r5nucleo.c => stm32l4/family.c} (55%)
 rename hw/bsp/{stm32l4r5nucleo/board.mk => stm32l4/family.mk} (81%)
 rename hw/bsp/{stm32l476disco => stm32l4}/stm32l4xx_hal_conf.h (100%)
 delete mode 100644 hw/bsp/stm32l476disco/board.mk
 delete mode 100644 hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h

diff --git a/hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32l476disco/STM32L476VGTx_FLASH.ld
rename to hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld
diff --git a/hw/bsp/stm32l476disco/stm32l476disco.c b/hw/bsp/stm32l4/boards/stm32l476_disco/board.h
similarity index 59%
rename from hw/bsp/stm32l476disco/stm32l476disco.c
rename to hw/bsp/stm32l4/boards/stm32l476_disco/board.h
index bc1b6c929..42c657d5e 100644
--- a/hw/bsp/stm32l476disco/stm32l476disco.c
+++ b/hw/bsp/stm32l4/boards/stm32l476_disco/board.h
@@ -1,7 +1,7 @@
 /* 
  * The MIT License (MIT)
  *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,21 +24,12 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#ifndef BOARD_H_
+#define BOARD_H_
 
-#include "stm32l4xx_hal.h"
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
+#ifdef __cplusplus
+ extern "C" {
+#endif
 
 #define LED_PORT              GPIOB
 #define LED_PIN               GPIO_PIN_2
@@ -48,15 +39,16 @@ void OTG_FS_IRQHandler(void)
 #define BUTTON_PIN            GPIO_PIN_0
 #define BUTTON_STATE_ACTIVE   1
 
+#define UART_DEV              USART2
+#define UART_CLK_EN           __HAL_RCC_USART2_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOD
+#define UART_GPIO_AF          GPIO_AF7_USART2
+#define UART_TX_PIN           GPIO_PIN_5
+#define UART_RX_PIN           GPIO_PIN_6
 
-// enable all LED, Button, Uart, USB clock
-static void all_rcc_clk_enable(void)
-{
-  __HAL_RCC_GPIOA_CLK_ENABLE(); // USB D+, D-, Button
-  __HAL_RCC_GPIOB_CLK_ENABLE(); // LED
-  __HAL_RCC_GPIOC_CLK_ENABLE(); // VBUS pin
-}
-
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
 
 /**
   * @brief  System Clock Configuration
@@ -80,7 +72,7 @@ static void all_rcc_clk_enable(void)
   * @param  None
   * @retval None
   */
-static void SystemClock_Config(void)
+static inline void board_clock_init(void)
 {
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_OscInitTypeDef RCC_OscInitStruct;
@@ -131,116 +123,17 @@ static void SystemClock_Config(void)
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 }
 
-void board_init(void)
+static inline void board_vbus_sense_init(void)
 {
-  SystemClock_Config();
-  all_rcc_clk_enable();
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#endif
-
-  /* Enable Power Clock*/
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* Enable USB power on Pwrctrl CR2 register */
-  HAL_PWREx_EnableVddUSB();
-
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  board_led_write(false);
-
-  // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // USB
-  /* Configure DM DP Pins */
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Configure VBUS Pin */
-  GPIO_InitStruct.Pin = GPIO_PIN_11;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-  /* Enable USB FS Clock */
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
-//  // Enable VBUS sense (B device) via pin PA9
-//  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
   // L476Disco use general GPIO PC11 for VBUS sensing instead of dedicated PA9 as others
   // Disable VBUS Sense and force device mode
   USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
 }
 
-//--------------------------------------------------------------------+
-// board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
+#ifdef __cplusplus
+ }
 #endif
 
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32l4/boards/stm32l476_disco/board.mk b/hw/bsp/stm32l4/boards/stm32l476_disco/board.mk
new file mode 100644
index 000000000..e7b8557a5
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l476_disco/board.mk
@@ -0,0 +1,10 @@
+CFLAGS += \
+  -DSTM32L476xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32l476vg
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld
new file mode 100644
index 000000000..c1a490a70
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld
@@ -0,0 +1,200 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32L4P5ZGTx Device from STM32L4PLUS series
+**                      1024Kbytes ROM
+**                      320Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + 0x0001FFFF;	/* end of "SRAM1" Ram type memory */
+
+_Min_Heap_Size = 0x200;	/* required amount of heap  */
+_Min_Stack_Size = 0x400;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 320K
+  ROM	(rx)	: ORIGIN = 0x08000000,	LENGTH = 1024K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM AT> ROM
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h
new file mode 100644
index 000000000..1df389aed
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h
@@ -0,0 +1,137 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_14
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+#define UART_DEV              LPUART1
+#define UART_CLK_EN           __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOG
+#define UART_GPIO_AF          GPIO_AF8_LPUART1
+#define UART_TX_PIN           GPIO_PIN_7
+#define UART_RX_PIN           GPIO_PIN_8
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (MSI)
+  *            SYSCLK(Hz)                     = 120000000
+  *            HCLK(Hz)                       = 120000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 1
+  *            APB2 Prescaler                 = 1
+  *            MSI Frequency(Hz)              = 48000000
+  *            PLL_M                          = 12
+  *            PLL_N                          = 60
+  *            PLL_P                          = 2
+  *            PLL_Q                          = 2
+  *            VDD(V)                         = 3.3
+  *            Main regulator output voltage  = Scale1 mode
+  *            Flash Latency(WS)              = 5
+  *         The USB clock configuration from PLLSAI:
+  *            PLLSAIP                        = 8 FIXME
+  *            PLLSAIN                        = 384 FIXME
+  *            PLLSAIQ                        = 7 FIXME
+  * @param  None
+  * @retval None
+  */
+
+static inline void board_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /* Activate PLL with MSI , stabilizied via PLL by LSE */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = 12;
+  RCC_OscInitStruct.PLL.PLLN = 60;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Enable MSI Auto-calibration through LSE */
+  HAL_RCCEx_EnableMSIPLLMode();
+
+  /* Select MSI output as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select MSI output as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+  clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  // Avoid overshoot and start with HCLK 60 MHz
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
+
+  /* AHB prescaler divider at 1 as second step */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk
new file mode 100644
index 000000000..8252dd838
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk
@@ -0,0 +1,10 @@
+CFLAGS += \
+  -DSTM32L4P5xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32l4p5zg
diff --git a/hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
rename to hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h
new file mode 100644
index 000000000..1df389aed
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h
@@ -0,0 +1,137 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_14
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+#define UART_DEV              LPUART1
+#define UART_CLK_EN           __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOG
+#define UART_GPIO_AF          GPIO_AF8_LPUART1
+#define UART_TX_PIN           GPIO_PIN_7
+#define UART_RX_PIN           GPIO_PIN_8
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (MSI)
+  *            SYSCLK(Hz)                     = 120000000
+  *            HCLK(Hz)                       = 120000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 1
+  *            APB2 Prescaler                 = 1
+  *            MSI Frequency(Hz)              = 48000000
+  *            PLL_M                          = 12
+  *            PLL_N                          = 60
+  *            PLL_P                          = 2
+  *            PLL_Q                          = 2
+  *            VDD(V)                         = 3.3
+  *            Main regulator output voltage  = Scale1 mode
+  *            Flash Latency(WS)              = 5
+  *         The USB clock configuration from PLLSAI:
+  *            PLLSAIP                        = 8 FIXME
+  *            PLLSAIN                        = 384 FIXME
+  *            PLLSAIQ                        = 7 FIXME
+  * @param  None
+  * @retval None
+  */
+
+static inline void board_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /* Activate PLL with MSI , stabilizied via PLL by LSE */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
+  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
+  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
+  RCC_OscInitStruct.PLL.PLLM = 12;
+  RCC_OscInitStruct.PLL.PLLN = 60;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Enable MSI Auto-calibration through LSE */
+  HAL_RCCEx_EnableMSIPLLMode();
+
+  /* Select MSI output as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select MSI output as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+  clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  // Avoid overshoot and start with HCLK 60 MHz
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
+
+  /* AHB prescaler divider at 1 as second step */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk
new file mode 100644
index 000000000..3d7fa227b
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += \
+  -DHSE_VALUE=8000000 \
+  -DSTM32L4R5xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32l4r5zi
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c b/hw/bsp/stm32l4/family.c
similarity index 55%
rename from hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c
rename to hw/bsp/stm32l4/family.c
index 8c661b602..c15be98e5 100644
--- a/hw/bsp/stm32l4r5nucleo/stm32l4r5nucleo.c
+++ b/hw/bsp/stm32l4/family.c
@@ -26,9 +26,9 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
-
 #include "stm32l4xx_hal.h"
+#include "bsp/board.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
@@ -42,119 +42,22 @@ void OTG_FS_IRQHandler(void)
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-#define LED_PORT              GPIOB
-#define LED_PIN               GPIO_PIN_14
-#define LED_STATE_ON          1
-
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
-
-#define UARTx                 LPUART1
-#define UART_GPIO_PORT        GPIOG
-#define UART_GPIO_AF          GPIO_AF8_LPUART1
-#define UART_TX_PIN           GPIO_PIN_7
-#define UART_RX_PIN           GPIO_PIN_8
-
 UART_HandleTypeDef UartHandle;
 
-// enable all LED, Button, Uart, USB clock
-static void all_rcc_clk_enable(void)
-{
-  __HAL_RCC_GPIOA_CLK_ENABLE();  // USB D+, D-
-  __HAL_RCC_GPIOB_CLK_ENABLE();  // LED
-  __HAL_RCC_GPIOC_CLK_ENABLE();  // Button
-  __HAL_RCC_GPIOG_CLK_ENABLE();  // Uart TX, RX
-  __HAL_RCC_LPUART1_CLK_ENABLE(); // LPUart1 module
-}
-
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow :
-  *            System Clock source            = PLL (MSI)
-  *            SYSCLK(Hz)                     = 120000000
-  *            HCLK(Hz)                       = 120000000
-  *            AHB Prescaler                  = 1
-  *            APB1 Prescaler                 = 1
-  *            APB2 Prescaler                 = 1
-  *            MSI Frequency(Hz)              = 48000000
-  *            PLL_M                          = 12
-  *            PLL_N                          = 60
-  *            PLL_P                          = 2
-  *            PLL_Q                          = 2
-  *            VDD(V)                         = 3.3
-  *            Main regulator output voltage  = Scale1 mode
-  *            Flash Latency(WS)              = 5
-  *         The USB clock configuration from PLLSAI:
-  *            PLLSAIP                        = 8 FIXME
-  *            PLLSAIN                        = 384 FIXME
-  *            PLLSAIQ                        = 7 FIXME
-  * @param  None
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-
-  /* Activate PLL with MSI , stabilizied via PLL by LSE */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
-  RCC_OscInitStruct.MSIState = RCC_MSI_ON;
-  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
-  RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
-  RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
-  RCC_OscInitStruct.PLL.PLLM = 12;
-  RCC_OscInitStruct.PLL.PLLN = 60;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = 2;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-  /* Enable MSI Auto-calibration through LSE */
-  HAL_RCCEx_EnableMSIPLLMode();
-
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select MSI output as USB clock source */
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
-  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-  
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
-  clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  // Avoid overshoot and start with HCLK 60 MHz  
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
-
-  /* AHB prescaler divider at 1 as second step */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
-}
-
 void board_init(void)
 {
-  /* Enable Power Clock*/
-  __HAL_RCC_PWR_CLK_ENABLE();
-  /* Enable voltage range 1 boost mode for frequency above 80 Mhz */
-  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
+  board_clock_init();
 
-  /* Set tick interrupt priority, default HAL value is intentionally invalid
-     and that prevents PLL initialization in HAL_RCC_OscConfig() */
-
-  HAL_InitTick((1UL << __NVIC_PRIO_BITS) - 1UL);
-
-  SystemClock_Config();
-  all_rcc_clk_enable();
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  UART_CLK_EN();
 
 #if CFG_TUSB_OS  == OPT_OS_NONE
   // 1ms tick timer
@@ -164,6 +67,15 @@ void board_init(void)
   //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
+  /* Enable USB power on Pwrctrl CR2 register */
+  /* Enable Power Clock*/
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+#if defined(PWR_CR5_R1MODE)
+  /* Enable voltage range 1 boost mode for frequency above 80 Mhz */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
+#endif
+
   /* Enable USB power on Pwrctrl CR2 register */
   HAL_PWREx_EnableVddUSB();
 
@@ -192,7 +104,7 @@ void board_init(void)
   GPIO_InitStruct.Alternate = UART_GPIO_AF;
   HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
 
-  UartHandle.Instance        = UARTx;
+  UartHandle.Instance        = UART_DEV;
   UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
   UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
   UartHandle.Init.StopBits   = UART_STOPBITS_1;
@@ -201,7 +113,7 @@ void board_init(void)
   UartHandle.Init.Mode       = UART_MODE_TX_RX;
   UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
   UartHandle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
-  UartHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  //UartHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
   UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 
   HAL_UART_Init(&UartHandle);
@@ -231,8 +143,7 @@ void board_init(void)
   /* Enable USB FS Clocks */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
-  // Enable VBUS sense (B device) via pin PA9
-  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+  board_vbus_sense_init();
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4/family.mk
similarity index 81%
rename from hw/bsp/stm32l4r5nucleo/board.mk
rename to hw/bsp/stm32l4/family.mk
index 12a291d0a..d6f55e5f9 100644
--- a/hw/bsp/stm32l4r5nucleo/board.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -4,6 +4,8 @@ DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
+include $(TOP)/$(BOARD_PATH)/board.mk
+
 CFLAGS += \
   -flto \
   -mthumb \
@@ -12,18 +14,14 @@ CFLAGS += \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
-  -DHSE_VALUE=8000000 \
-  -DSTM32L4R5xx \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L4
 
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32L4RXxI_FLASH.ld
-
+#src/portable/st/synopsys/dcd_synopsys.c
 SRC_C += \
-	src/portable/st/synopsys/dcd_synopsys.c \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
@@ -34,14 +32,11 @@ SRC_C += \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
 
-SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
-
 INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
+	$(TOP)/$(BOARD_PATH)
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
diff --git a/hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h
similarity index 100%
rename from hw/bsp/stm32l476disco/stm32l4xx_hal_conf.h
rename to hw/bsp/stm32l4/stm32l4xx_hal_conf.h
diff --git a/hw/bsp/stm32l476disco/board.mk b/hw/bsp/stm32l476disco/board.mk
deleted file mode 100644
index 8d9e267cf..000000000
--- a/hw/bsp/stm32l476disco/board.mk
+++ /dev/null
@@ -1,56 +0,0 @@
-ST_FAMILY = l4
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DSTM32L476xx \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32L4
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32L476VGTx_FLASH.ld
-
-#src/portable/st/synopsys/dcd_synopsys.c
-SRC_C += \
-	src/portable/synopsys/dwc2/dcd_dwc2.c \
-	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
-
-SRC_S += \
-	$(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
-
-INC += \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(ST_CMSIS)/Include \
-	$(TOP)/$(ST_HAL_DRIVER)/Inc \
-	$(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = stm32l476vg
-
-# Path to STM32 Cube Programmer CLI, should be added into system path
-STM32Prog = STM32_Programmer_CLI
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h b/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h
deleted file mode 100644
index 470ef1290..000000000
--- a/hw/bsp/stm32l4r5nucleo/stm32l4xx_hal_conf.h
+++ /dev/null
@@ -1,419 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l4xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l4xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L4xx_HAL_CONF_H
-#define __STM32L4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_COMP_MODULE_ENABLED */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_FIREWALL_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-// #define HAL_NOR_MODULE_ENABLED
-// #define HAL_SRAM_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */ 
-#define HAL_GPIO_MODULE_ENABLED
-//#define HAL_I2C_MODULE_ENABLED
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-//#define HAL_LCD_MODULE_ENABLED
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_OPAMP_MODULE_ENABLED */
-//#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED */
-/* #define HAL_RTC_MODULE_ENABLED */
-//#define HAL_SAI_MODULE_ENABLED
-//#define HAL_SD_MODULE_ENABLED
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED */
-/* #define HAL_SWPMI_MODULE_ENABLED */
-/* #define HAL_TIM_MODULE_ENABLED */
-/* #define HAL_TSC_MODULE_ENABLED */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    4000000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
-  *        This internal oscillator is mainly dedicated to provide a high precision clock to
-  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
-  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
-  *        which is subject to manufacturing process variations.
-  */
-#if !defined  (HSI48_VALUE) 
- #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
-                                              The real value my vary depending on manufacturing process variations.*/
-#endif /* HSI48_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  32000U                 /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    32768U /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    5000U  /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for SAI1 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
-  *        frequency.
-  */
-#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
-  #define EXTERNAL_SAI1_CLOCK_VALUE    48000U /*!< Value of the SAI1 External clock source in Hz*/
-#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
-
-/**
-  * @brief External clock source for SAI2 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
-  *        frequency.
-  */
-#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
-  #define EXTERNAL_SAI2_CLOCK_VALUE    48000U /*!< Value of the SAI2 External clock source in Hz*/
-#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            0U /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              0U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
-#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
-#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
-#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
-#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
-#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT               1U */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC                   1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32l4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32l4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
-  #include "stm32l4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32l4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32l4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32l4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "Legacy/stm32l4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l4xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32l4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32l4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32l4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FIREWALL_MODULE_ENABLED
-  #include "stm32l4xx_hal_firewall.h"
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32l4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32l4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32l4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32l4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l4xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32l4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-#include "stm32l4xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32l4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32l4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32l4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32l4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32l4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SWPMI_MODULE_ENABLED
- #include "stm32l4xx_hal_swpmi.h"
-#endif /* HAL_SWPMI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32l4xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32l4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t *file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L4xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 9750757aa..a850d4e15 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -59,7 +59,7 @@
 #define DWC2_REG(_port)       ((dwc2_regs_t*) DWC2_REG_BASE)
 
 // Debug level for DWC2
-#define DWC2_DEBUG    1
+#define DWC2_DEBUG    2
 
 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
 

From 4431ced598ca8ee1f07d6acd7f1424f17755c155 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Nov 2021 16:20:39 +0700
Subject: [PATCH 0627/2085] add L4 to ci, update doc

---
 .github/workflows/build.yml  |  1 +
 README.rst                   |  2 +-
 docs/reference/supported.rst | 39 +++++++++++++++++++++++++++++++-----
 3 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index b16cf3f87..53a1628a0 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -56,6 +56,7 @@ jobs:
         - 'stm32f4'
         - 'stm32f7'
         - 'stm32h7'
+        - 'stm32l4'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v2
diff --git a/README.rst b/README.rst
index 11804ccd1..329c0da53 100644
--- a/README.rst
+++ b/README.rst
@@ -47,7 +47,7 @@ The stack supports the following MCUs:
 - **Renesas:** RX63N, RX65N
 - **Silabs:** EFM32GG12
 - **Sony:** CXD56
-- **ST:** STM32 series: L0, L1, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
+- **ST:** STM32 series: L0, L1, L4, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
 - **TI:** MSP430
 - **ValentyUSB:** eptri
 
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index c8a441f18..ef924adb4 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -305,29 +305,58 @@ Sony
 ST STM32
 --------
 
--  `Adafruit Feather STM32F405 <https://www.adafruit.com/product/4382>`__
--  `Micro Python PyBoard v1.1 <https://store.micropython.org/product/PYBv1.1>`__
--  `STLink-V3 Mini <https://www.st.com/en/development-tools/stlink-v3mini.html>`__
--  `STM32 L035c8 Discovery <https://www.st.com/en/evaluation-tools/32l0538discovery.html>`__
--  `STM32 L4R5zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html>`__
+F0
+^^
 -  `STM32 F070rb Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f070rb.html>`__
 -  `STM32 F072 Evaluation <https://www.st.com/en/evaluation-tools/stm32072b-eval.html>`__
 -  `STM32 F072rb Discovery <https://www.st.com/en/evaluation-tools/32f072bdiscovery.html>`__
+
+F1
+^^
 -  `STM32 F103c8 Blue Pill <https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill>`__
 -  `STM32 F103rc Mini v2.0 <https://stm32-base.org/boards/STM32F103RCT6-STM32-Mini-V2.0>`__
+
+F2
+^^
 -  `STM32 F207zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f207zg.html>`__
+
+F3
+^^
 -  `STM32 F303vc Discovery <https://www.st.com/en/evaluation-tools/stm32f3discovery.html>`__
+
+F4
+^^
+-  `Adafruit Feather STM32F405 <https://www.adafruit.com/product/4382>`__
+-  `Micro Python PyBoard v1.1 <https://store.micropython.org/product/PYBv1.1>`__
 -  `STM32 F401cc Black Pill <https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2>`__
 -  `STM32 F407vg Discovery <https://www.st.com/en/evaluation-tools/stm32f4discovery.html>`__
 -  `STM32 F411ce Black Pill <https://www.adafruit.com/product/4877>`__
 -  `STM32 F411ve Discovery <https://www.st.com/en/evaluation-tools/32f411ediscovery.html>`__
 -  `STM32 F412zg Discovery <https://www.st.com/en/evaluation-tools/32f412gdiscovery.html>`__
 -  `STM32 F412zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f412zg.html>`__
+
+F7
+^^
+
+-  `STLink-V3 Mini <https://www.st.com/en/development-tools/stlink-v3mini.html>`__
 -  `STM32 F723e Discovery <https://www.st.com/en/evaluation-tools/32f723ediscovery.html>`__
 -  `STM32 F746zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f746zg.html>`__
 -  `STM32 F746g Discovery <https://www.st.com/en/evaluation-tools/32f746gdiscovery.html>`__
 -  `STM32 F767zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f767zi.html>`__
 -  `STM32 F769i Discovery <https://www.st.com/en/evaluation-tools/32f769idiscovery.html>`__
+
+L0
+^^
+-  `STM32 L035c8 Discovery <https://www.st.com/en/evaluation-tools/32l0538discovery.html>`__
+
+L4
+^^
+-  `STM32 L476vg Discovery <https://www.st.com/en/evaluation-tools/32l476gdiscovery.html>`__
+-  `STM32 L4P5zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html>`__
+-  `STM32 L4R5zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html>`__
+
+H7
+^^
 -  `STM32 H743zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-h743zi.html>`__
 -  `STM32 H743i Evaluation <https://www.st.com/en/evaluation-tools/stm32h743i-eval.html>`__
 -  `STM32 H745i Discovery <https://www.st.com/en/evaluation-tools/stm32h745i-disco.html>`__

From 1046786acf0ab35bf41009b985f7627d6b859a48 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Nov 2021 18:17:59 +0700
Subject: [PATCH 0628/2085] change broadcom submodule path from git to http

---
 .gitmodules                   | 3 +--
 hw/bsp/raspberrypi4/family.mk | 2 ++
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/.gitmodules b/.gitmodules
index b86245990..79dec144e 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -129,5 +129,4 @@
 	url = https://github.com/hathach/mm32sdk.git
 [submodule "hw/mcu/broadcom"]
 	path = hw/mcu/broadcom
-	url = git@github.com:adafruit/broadcom-peripherals.git
-	branch = main-build
+	url = https://github.com/adafruit/broadcom-peripherals.git
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
index b0326c056..b1d14a6ec 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -43,5 +43,7 @@ SRC_S += $(MCU_DIR)/broadcom/boot.S
 $(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf
 	$(OBJCOPY) -O binary $^ $@
 
+# Copy to kernel to netboot drive or SD card
+# Change destinaation to fit your need
 flash: $(BUILD)/kernel8.img
 	@$(CP) $< /home/$(USER)/Documents/code/pi4_tinyusb/boot_cpy

From 0e733ae14bf4c165abcd27ccb1408927b72a0047 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Nov 2021 21:46:23 +0700
Subject: [PATCH 0629/2085] add pi4 to ci build in build_aarch64

---
 .github/workflows/build_aarch64.yml           | 67 +++++++++++++++++++
 .../workflows/{build.yml => build_arm.yml}    |  0
 .gitmodules                                   |  1 +
 .../device/audio_4_channel_mic/src/main.c     |  2 +-
 examples/device/audio_test/src/main.c         |  2 +-
 .../device/cdc_msc_freertos/.skip.MCU_BCM2711 |  0
 .../hid_composite_freertos/.skip.MCU_BCM2711  |  0
 hw/bsp/raspberrypi4/family.mk                 |  5 +-
 8 files changed, 72 insertions(+), 5 deletions(-)
 create mode 100644 .github/workflows/build_aarch64.yml
 rename .github/workflows/{build.yml => build_arm.yml} (100%)
 create mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_BCM2711
 create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_BCM2711

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
new file mode 100644
index 000000000..0cc7a5de1
--- /dev/null
+++ b/.github/workflows/build_aarch64.yml
@@ -0,0 +1,67 @@
+name: Build AArch64
+
+on:
+  pull_request:
+  push:
+  release:
+    types:
+      - created
+
+jobs:
+  # ---------------------------------------
+  # Build AARCH64 family
+  # ---------------------------------------
+  build-arm:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        family:
+        # Alphabetical order
+        - 'raspberrypi4'
+    steps:
+    - name: Setup Python
+      uses: actions/setup-python@v2
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v2
+
+    - name: Checkout common submodules in lib
+      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
+
+    - name: Checkout hathach/linkermap
+      uses: actions/checkout@v2
+      with:
+         repository: hathach/linkermap
+         path: linkermap
+
+    - name: Set Toolchain URL
+      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz
+
+    - name: Cache Toolchain
+      uses: actions/cache@v2
+      id: cache-toolchain
+      with:
+        path: ~/cache/
+        key: ${{ runner.os }}-21-11-02-${{ env.TOOLCHAIN_URL }}
+
+    - name: Install Toolchain
+      if: steps.cache-toolchain.outputs.cache-hit != 'true'
+      run: |
+        mkdir -p ~/cache/toolchain
+        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
+        tar -C ~/cache/toolchain -xaf toolchain.tar.gz
+
+    - name: Set Toolchain Path
+      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
+
+    - name: Build
+      run: python3 tools/build_family.py ${{ matrix.family }}
+
+    - name: Linker Map
+      run: |
+        pip install linkermap/
+        for ex in `ls -d examples/device/*/`; do \
+          find ${ex} -name *.map -print -quit | \
+          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        done
diff --git a/.github/workflows/build.yml b/.github/workflows/build_arm.yml
similarity index 100%
rename from .github/workflows/build.yml
rename to .github/workflows/build_arm.yml
diff --git a/.gitmodules b/.gitmodules
index 79dec144e..a95e64ee6 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -130,3 +130,4 @@
 [submodule "hw/mcu/broadcom"]
 	path = hw/mcu/broadcom
 	url = https://github.com/adafruit/broadcom-peripherals.git
+	branch = main-build
diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 983b87e5b..d085dd43a 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -141,7 +141,7 @@ void tud_resume_cb(void)
 void audio_task(void)
 {
   // Yet to be filled - e.g. put meas data into TX FIFOs etc.
-  asm("nop");
+  // asm("nop");
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index 9a2fdd3a1..ed13ce993 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -142,7 +142,7 @@ void tud_resume_cb(void)
 void audio_task(void)
 {
   // Yet to be filled - e.g. put meas data into TX FIFOs etc.
-  asm("nop");
+  // asm("nop");
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_BCM2711 b/examples/device/cdc_msc_freertos/.skip.MCU_BCM2711
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_BCM2711 b/examples/device/hid_composite_freertos/.skip.MCU_BCM2711
new file mode 100644
index 000000000..e69de29bb
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
index b1d14a6ec..2e61b9e74 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -1,9 +1,8 @@
-UF2_FAMILY_ID = 0x57755a57
+MCU_DIR = hw/mcu/broadcom
+DEPS_SUBMODULES += $(MCU_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
-MCU_DIR = hw/mcu/broadcom
-
 CC = clang
 
 CFLAGS += \

From 28b177484d15971dc12ec76dfe71ffcae433835a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 2 Nov 2021 22:27:00 +0700
Subject: [PATCH 0630/2085] skip net example for pi4 due to ssize_t conflict

---
 examples/device/net_lwip_webserver/.skip.MCU_BCM2711 | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 examples/device/net_lwip_webserver/.skip.MCU_BCM2711

diff --git a/examples/device/net_lwip_webserver/.skip.MCU_BCM2711 b/examples/device/net_lwip_webserver/.skip.MCU_BCM2711
new file mode 100644
index 000000000..bdc68f5db
--- /dev/null
+++ b/examples/device/net_lwip_webserver/.skip.MCU_BCM2711
@@ -0,0 +1 @@
+tinyusb/lib/lwip/src/include/lwip/arch.h:202:13: error: conflicting types for 'ssize_t'
\ No newline at end of file

From e16506cb52d6d8e8b2a2e2910f10c32a89a6d322 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 3 Nov 2021 12:24:10 +0700
Subject: [PATCH 0631/2085] clean up

---
 hw/bsp/raspberrypi4/family.c          | 17 +++--------------
 hw/bsp/raspberrypi4/family.mk         |  3 +++
 src/portable/synopsys/dwc2/dwc2_bcm.h |  5 +++++
 3 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c
index ffeb05f9f..95b28c6fc 100644
--- a/hw/bsp/raspberrypi4/family.c
+++ b/hw/bsp/raspberrypi4/family.c
@@ -30,10 +30,9 @@
 #include "broadcom/interrupts.h"
 #include "broadcom/io.h"
 #include "broadcom/mmu.h"
+//#include "broadcom/caches.h"
 #include "broadcom/vcmailbox.h"
 
-uint32_t SystemCoreClock = 700 * 1000 * 1000;
-
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -49,11 +48,6 @@ void USB_IRQHandler(void)
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
-
-void print(const char* str) {
-  board_uart_write(str, strlen(str));
-}
-
 void board_init(void)
 {
   gpio_initOutputPinWithPullNone(18);
@@ -63,13 +57,14 @@ void board_init(void)
   gpio_setPinOutputBool(18, true);
   gpio_initOutputPinWithPullNone(42);
   setup_mmu_flat_map();
+//  init_caches();
+
   // gpio_initOutputPinWithPullNone(23);
   // gpio_initOutputPinWithPullNone(24);
   // gpio_initOutputPinWithPullNone(25);
   gpio_setPinOutputBool(18, false);
   uart_init();
   gpio_setPinOutputBool(18, true);
-  const char* greeting = "hello to gdb2\r\n";
   gpio_setPinOutputBool(18, false);
   for (size_t i = 0; i < 5; i++) {
   // while (true) {
@@ -92,7 +87,6 @@ void board_init(void)
   }
   // uart_writeText("hello from io\n");
   // gpio_setPinOutputBool(24, true);
-  board_uart_write(greeting, strlen(greeting));
   // gpio_setPinOutputBool(24, false);
   // gpio_setPinOutputBool(25, true);
   // print();
@@ -110,13 +104,8 @@ void board_init(void)
   // }
   // while (1) uart_update();
 
-  printf("hello %d\r\n", 21);
-
   // Turn on USB peripheral.
-  print("Turning on USB power\r\n");
-
   vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true);
-  print("USB power on\r\n");
 
   BP_SetPriority(USB_IRQn, 0x00);
   BP_ClearPendingIRQ(USB_IRQn);
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
index 2e61b9e74..2a0a87788 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -6,6 +6,7 @@ include $(TOP)/$(BOARD_PATH)/board.mk
 CC = clang
 
 CFLAGS += \
+	-mcpu=cortex-a72 \
 	-Wall \
 	-O0 \
 	-ffreestanding \
@@ -26,6 +27,8 @@ SRC_C += \
 	$(MCU_DIR)/broadcom/mmu.c \
 	$(MCU_DIR)/broadcom/vcmailbox.c
 
+#	$(MCU_DIR)/broadcom/caches.c \
+
 CROSS_COMPILE = aarch64-none-elf-
 
 SKIP_NANOLIB = 1
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index 38d10930c..317e79cf7 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -32,11 +32,16 @@
 #endif
 
 #include "broadcom/interrupts.h"
+//#include "broadcom/caches.h"
 
 #define DWC2_REG_BASE       0xFE980000UL
 #define DWC2_EP_MAX         8
 #define DWC2_EP_FIFO_SIZE   4096
 
+//#define dcache_clean(_addr, _size)              data_clean(_addr, _size)
+//#define dcache_invalidate(_addr, _size)         data_invalidate(_addr, _size)
+//#define dcache_clean_invalidate(_addr, _size)   data_clean_and_invalidate(_addr, _size)
+
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {

From 0faff5a859cfd91f92a9b91f65a1d6a164f0a7be Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 3 Nov 2021 13:13:08 +0700
Subject: [PATCH 0632/2085] update broadcom peripherals to latest

---
 hw/bsp/raspberrypi4/family.c  | 4 ++--
 hw/bsp/raspberrypi4/family.mk | 2 +-
 hw/mcu/broadcom               | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c
index 95b28c6fc..7a7a0e9ff 100644
--- a/hw/bsp/raspberrypi4/family.c
+++ b/hw/bsp/raspberrypi4/family.c
@@ -30,7 +30,7 @@
 #include "broadcom/interrupts.h"
 #include "broadcom/io.h"
 #include "broadcom/mmu.h"
-//#include "broadcom/caches.h"
+#include "broadcom/caches.h"
 #include "broadcom/vcmailbox.h"
 
 //--------------------------------------------------------------------+
@@ -57,7 +57,7 @@ void board_init(void)
   gpio_setPinOutputBool(18, true);
   gpio_initOutputPinWithPullNone(42);
   setup_mmu_flat_map();
-//  init_caches();
+  init_caches();
 
   // gpio_initOutputPinWithPullNone(23);
   // gpio_initOutputPinWithPullNone(24);
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
index 2a0a87788..475cfa4ff 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -25,9 +25,9 @@ SRC_C += \
 	$(MCU_DIR)/broadcom/interrupts.c \
 	$(MCU_DIR)/broadcom/io.c \
 	$(MCU_DIR)/broadcom/mmu.c \
+	$(MCU_DIR)/broadcom/caches.c \
 	$(MCU_DIR)/broadcom/vcmailbox.c
 
-#	$(MCU_DIR)/broadcom/caches.c \
 
 CROSS_COMPILE = aarch64-none-elf-
 
diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom
index 55cd6f798..d126323fc 160000
--- a/hw/mcu/broadcom
+++ b/hw/mcu/broadcom
@@ -1 +1 @@
-Subproject commit 55cd6f798a45cac905d7bf81baa2bcbf7de7c42e
+Subproject commit d126323fc77e81d1f18677a439685a4754ea02aa

From b51d038b656688b6150470d23752a306ee150da3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 4 Nov 2021 12:30:11 +0700
Subject: [PATCH 0633/2085] fix issue with bcm2711 caching issue by ading ISB()
 after dwc2_dcd_int_enable90

also add hwcfg_list for reference
---
 src/portable/synopsys/dwc2/dcd_dwc2.c    |  16 +-
 src/portable/synopsys/dwc2/dwc2_bcm.h    |  10 +-
 src/portable/synopsys/dwc2/hwcfg_list.md | 722 +++++++++++++++++++++++
 3 files changed, 743 insertions(+), 5 deletions(-)
 create mode 100644 src/portable/synopsys/dwc2/hwcfg_list.md

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index a850d4e15..3967f225e 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -56,11 +56,25 @@
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
+// DWC2 registers
 #define DWC2_REG(_port)       ((dwc2_regs_t*) DWC2_REG_BASE)
 
 // Debug level for DWC2
 #define DWC2_DEBUG    2
 
+#ifndef dcache_clean
+#define dcache_clean(_addr, _size)
+#endif
+
+#ifndef dcache_invalidate
+#define dcache_invalidate(_addr, _size)
+#endif
+
+#ifndef dcache_clean_invalidate
+#define dcache_clean_invalidate(_addr, _size)
+#endif
+
+
 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
 
 typedef struct {
@@ -71,7 +85,7 @@ typedef struct {
   uint8_t interval;
 } xfer_ctl_t;
 
-xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
+static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
 #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
 
 // EP0 transfers are limited to 1 packet - larger sizes has to be split
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index 317e79cf7..0263d19ba 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -32,21 +32,22 @@
 #endif
 
 #include "broadcom/interrupts.h"
-//#include "broadcom/caches.h"
+#include "broadcom/caches.h"
 
 #define DWC2_REG_BASE       0xFE980000UL
 #define DWC2_EP_MAX         8
 #define DWC2_EP_FIFO_SIZE   4096
 
-//#define dcache_clean(_addr, _size)              data_clean(_addr, _size)
-//#define dcache_invalidate(_addr, _size)         data_invalidate(_addr, _size)
-//#define dcache_clean_invalidate(_addr, _size)   data_clean_and_invalidate(_addr, _size)
+#define dcache_clean(_addr, _size)              data_clean(_addr, _size)
+#define dcache_invalidate(_addr, _size)         data_invalidate(_addr, _size)
+#define dcache_clean_invalidate(_addr, _size)   data_clean_and_invalidate(_addr, _size)
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
   BP_EnableIRQ(USB_IRQn);
+  __asm__ volatile("isb");
 }
 
 TU_ATTR_ALWAYS_INLINE
@@ -54,6 +55,7 @@ static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
   (void) rhport;
   BP_DisableIRQ(USB_IRQn);
+  __asm__ volatile("isb");
 }
 
 static inline void dwc2_remote_wakeup_delay(void)
diff --git a/src/portable/synopsys/dwc2/hwcfg_list.md b/src/portable/synopsys/dwc2/hwcfg_list.md
new file mode 100644
index 000000000..495a30fd0
--- /dev/null
+++ b/src/portable/synopsys/dwc2/hwcfg_list.md
@@ -0,0 +1,722 @@
+# DWC2 Hardware Configuration Registers
+
+## Broadcom BCM2711 (Pi4)
+
+dwc2->guid = 2708A000
+dwc2->gsnpsid = 4F54280A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 228DDD50
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 2
+hw_cfg2->point2point = 0
+hw_cfg2->hs_phy_type = 1
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 7
+hw_cfg2->num_host_ch = 7
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 0
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = FF000E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 0
+hw_cfg3->vendor_ctrl_itf = 0
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 0
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 0
+hw_cfg3->lpm_mode = 0
+hw_cfg3->total_fifo_size = 4080
+
+dwc2->ghwcfg4 = 1FF00020
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 0
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 0
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 15
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 0
+
+## EFM32GG FS
+
+dwc2->guid = 0
+dwc2->gsnpsid = 4F54330A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 228F5910
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 2
+hw_cfg2->point2point = 0
+hw_cfg2->hs_phy_type = 0
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 6
+hw_cfg2->num_host_ch = 13
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 0
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 1F204E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 0
+hw_cfg3->vendor_ctrl_itf = 0
+hw_cfg3->optional_feature_removed = 1
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 0
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 0
+hw_cfg3->lpm_mode = 0
+hw_cfg3->total_fifo_size = 498
+
+dwc2->ghwcfg4 = 1BF08030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 2
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 13
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 0
+
+## ESP32-S2 Fullspeed
+
+dwc2->guid = 0
+dwc2->gsnpsid = 4F54400A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 224DD930
+hw_cfg2->op_mode = 2
+hw_cfg2->arch = 3
+hw_cfg2->point2point = 0
+hw_cfg2->hs_phy_type = 1
+hw_cfg2->fs_phy_type = 2
+hw_cfg2->num_dev_ep = 6
+hw_cfg2->num_host_ch = 9
+hw_cfg2->period_channel_support = 0
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 1
+hw_cfg2->nperiod_tx_q_depth = 1
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 22
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = C804B5
+hw_cfg3->xfer_size_width = 10
+hw_cfg3->packet_size_width = 5
+hw_cfg3->otg_enable = 0
+hw_cfg3->i2c_enable = 0
+hw_cfg3->vendor_ctrl_itf = 1
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 1
+hw_cfg3->otg_adp_support = 1
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 1
+hw_cfg3->lpm_mode = 0
+hw_cfg3->total_fifo_size = 23130
+
+dwc2->ghwcfg4 = D3F0A030
+hw_cfg4->num_dev_period_in_ep = 10
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 0
+hw_cfg4->hibernation = 1
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 1
+hw_cfg4->acg_enable = 1
+hw_cfg4->utmi_phy_data_width = 1
+hw_cfg4->dev_ctrl_ep_num = 10
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 0
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 0
+hw_cfg4->dedicated_fifos = 0
+hw_cfg4->num_dev_in_eps = 13
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 1
+
+## STM32F407 and STM32F207
+
+STM32F407 and STM32F207 are exactly the same
+
+### STM32F407 Fullspeed
+
+dwc2->guid = 1200
+dwc2->gsnpsid = 4F54281A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 229DCD20
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 0
+hw_cfg2->point2point = 1
+hw_cfg2->hs_phy_type = 0
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 3
+hw_cfg2->num_host_ch = 7
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 1
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 20001E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 1
+hw_cfg3->vendor_ctrl_itf = 0
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 0
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 0
+hw_cfg3->lpm_mode = 0
+hw_cfg3->total_fifo_size = 512
+
+dwc2->ghwcfg4 = FF08030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 2
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 7
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 0
+
+### STM32F407 Highspeed
+
+dwc2->guid = 1100
+dwc2->gsnpsid = 4F54281A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 229ED590
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 2
+hw_cfg2->point2point = 0
+hw_cfg2->hs_phy_type = 2
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 5
+hw_cfg2->num_host_ch = 11
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 1
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 3F403E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 1
+hw_cfg3->vendor_ctrl_itf = 1
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 0
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 0
+hw_cfg3->lpm_mode = 0
+hw_cfg3->total_fifo_size = 1012
+
+dwc2->ghwcfg4 = 17F00030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 0
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 11
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 0
+
+## STM32F411 Fullspeed
+
+dwc2->guid = 1200
+dwc2->gsnpsid = 4F54281A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 229DCD20
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 0
+hw_cfg2->point2point = 1
+hw_cfg2->hs_phy_type = 0
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 3
+hw_cfg2->num_host_ch = 7
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 1
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 20001E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 1
+hw_cfg3->vendor_ctrl_itf = 0
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 0
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 0
+hw_cfg3->lpm_mode = 0
+hw_cfg3->total_fifo_size = 512
+
+dwc2->ghwcfg4 = FF08030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 2
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 7
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 0
+
+## STM32F412 FS
+
+dwc2->guid = 2000
+dwc2->gsnpsid = 4F54320A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 229ED520
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 0
+hw_cfg2->point2point = 1
+hw_cfg2->hs_phy_type = 0
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 5
+hw_cfg2->num_host_ch = 11
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 1
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 200D1E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 1
+hw_cfg3->vendor_ctrl_itf = 0
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 1
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 1
+hw_cfg3->lpm_mode = 1
+hw_cfg3->total_fifo_size = 512
+
+dwc2->ghwcfg4 = 17F08030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 2
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 11
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 0
+
+## STM32F723
+
+### STM32F723 HighSpeed
+
+dwc2->guid = 3100
+dwc2->gsnpsid = 4F54330A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 229FE1D0
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 2
+hw_cfg2->point2point = 0
+hw_cfg2->hs_phy_type = 3
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 8
+hw_cfg2->num_host_ch = 15
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 1
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 3EED2E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 0
+hw_cfg3->vendor_ctrl_itf = 1
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 1
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 1
+hw_cfg3->lpm_mode = 1
+hw_cfg3->total_fifo_size = 1006
+
+dwc2->ghwcfg4 = 23F00030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 0
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 1
+hw_cfg4->dma_desc_enable = 1
+hw_cfg4->dma_dynamic = 0
+
+### STM32F723 Fullspeed
+
+dwc2->guid = 3000
+dwc2->gsnpsid = 4F54330A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 229ED520
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 0
+hw_cfg2->point2point = 1
+hw_cfg2->hs_phy_type = 0
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 5
+hw_cfg2->num_host_ch = 11
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 1
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 200D1E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 1
+hw_cfg3->vendor_ctrl_itf = 0
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 1
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 1
+hw_cfg3->lpm_mode = 1
+hw_cfg3->total_fifo_size = 512
+
+dwc2->ghwcfg4 = 17F08030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 2
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 11
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 0
+
+## STM32F767 FS
+
+dwc2->guid = 2000
+dwc2->gsnpsid = 4F54320A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 229ED520
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 0
+hw_cfg2->point2point = 1
+hw_cfg2->hs_phy_type = 0
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 5
+hw_cfg2->num_host_ch = 11
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 1
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 200D1E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 1
+hw_cfg3->vendor_ctrl_itf = 0
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 1
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 1
+hw_cfg3->lpm_mode = 1
+hw_cfg3->total_fifo_size = 512
+
+dwc2->ghwcfg4 = 17F08030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 2
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 11
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 0
+
+## STM32H743 (both cores HS)
+
+dwc2->guid = 2300
+dwc2->gsnpsid = 4F54330A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 229FE190
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 2
+hw_cfg2->point2point = 0
+hw_cfg2->hs_phy_type = 2
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 8
+hw_cfg2->num_host_ch = 15
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 1
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 3B8D2E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 0
+hw_cfg3->vendor_ctrl_itf = 1
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 1
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 1
+hw_cfg3->lpm_mode = 1
+hw_cfg3->total_fifo_size = 952
+
+dwc2->ghwcfg4 = E3F00030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 0
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 1
+hw_cfg4->dma_desc_enable = 1
+hw_cfg4->dma_dynamic = 1
+
+## STM32L476 FS
+
+dwc2->guid = 2000
+dwc2->gsnpsid = 4F54310A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 229ED520
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 0
+hw_cfg2->point2point = 1
+hw_cfg2->hs_phy_type = 0
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 5
+hw_cfg2->num_host_ch = 11
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 1
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 200D1E8
+hw_cfg3->xfer_size_width = 8
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 1
+hw_cfg3->vendor_ctrl_itf = 0
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 1
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 1
+hw_cfg3->lpm_mode = 1
+hw_cfg3->total_fifo_size = 512
+
+dwc2->ghwcfg4 = 17F08030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 2
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 11
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 0
+
+## GD32VF103 Fullspeed
+
+dwc2->guid = 1000
+dwc2->gsnpsid = 0
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 0
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 0
+hw_cfg2->point2point = 0
+hw_cfg2->hs_phy_type = 0
+hw_cfg2->fs_phy_type = 0
+hw_cfg2->num_dev_ep = 0
+hw_cfg2->num_host_ch = 0
+hw_cfg2->period_channel_support = 0
+hw_cfg2->enable_dynamic_fifo = 0
+hw_cfg2->mul_cpu_int = 0
+hw_cfg2->nperiod_tx_q_depth = 0
+hw_cfg2->host_period_tx_q_depth = 0
+hw_cfg2->dev_token_q_depth = 0
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 0
+hw_cfg3->xfer_size_width = 0
+hw_cfg3->packet_size_width = 0
+hw_cfg3->otg_enable = 0
+hw_cfg3->i2c_enable = 0
+hw_cfg3->vendor_ctrl_itf = 0
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 0
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 0
+hw_cfg3->lpm_mode = 0
+hw_cfg3->total_fifo_size = 0
+
+dwc2->ghwcfg4 = 0
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 0
+hw_cfg4->ahb_freq_min = 0
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 0
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 0
+hw_cfg4->vbus_valid_filter_enabled = 0
+hw_cfg4->a_valid_filter_enabled = 0
+hw_cfg4->b_valid_filter_enabled = 0
+hw_cfg4->dedicated_fifos = 0
+hw_cfg4->num_dev_in_eps = 0
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 0

From 4a8ac71711a70ccb122fdb59d731dc01cfed1464 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 4 Nov 2021 12:31:16 +0700
Subject: [PATCH 0634/2085] Add timer1 on pi4 for blinky

this get usb irq triggered even without ISB() in previous commit
---
 README.rst                    |  6 +--
 hw/bsp/raspberrypi4/family.c  | 77 ++++++++++++-----------------------
 hw/bsp/raspberrypi4/family.mk |  2 +-
 3 files changed, 30 insertions(+), 55 deletions(-)

diff --git a/README.rst b/README.rst
index 329c0da53..1db022fc8 100644
--- a/README.rst
+++ b/README.rst
@@ -35,7 +35,7 @@ The stack supports the following MCUs:
 - **Dialog:** DA1469x
 - **Espressif:** ESP32-S2, ESP32-S3
 - **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAME7x
-- **NordicSemi:** nRF52833, nRF52840
+- **NordicSemi:** nRF52833, nRF52840, nRF5340
 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
 - **NXP:**
 
@@ -45,9 +45,9 @@ The stack supports the following MCUs:
 
 - **Raspberry Pi:** RP2040
 - **Renesas:** RX63N, RX65N
-- **Silabs:** EFM32GG12
+- **Silabs:** EFM32GG
 - **Sony:** CXD56
-- **ST:** STM32 series: L0, L1, L4, F0, F1, F2, F3, F4, F7, H7 both FullSpeed and HighSpeed
+- **ST:** STM32 series: L0, L1, L4, L4+, F0, F1, F2, F3, F4, F7, H7
 - **TI:** MSP430
 - **ValentyUSB:** eptri
 
diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/raspberrypi4/family.c
index 7a7a0e9ff..ba0b2700a 100644
--- a/hw/bsp/raspberrypi4/family.c
+++ b/hw/bsp/raspberrypi4/family.c
@@ -33,6 +33,14 @@
 #include "broadcom/caches.h"
 #include "broadcom/vcmailbox.h"
 
+// LED
+#define LED_PIN               18
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PIN            16
+#define BUTTON_STATE_ACTIVE   0
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -50,63 +58,27 @@ void USB_IRQHandler(void)
 //--------------------------------------------------------------------+
 void board_init(void)
 {
-  gpio_initOutputPinWithPullNone(18);
-  gpio_initOutputPinWithPullNone(19);
-  gpio_initOutputPinWithPullNone(20);
-  gpio_initOutputPinWithPullNone(21);
-  gpio_setPinOutputBool(18, true);
-  gpio_initOutputPinWithPullNone(42);
   setup_mmu_flat_map();
   init_caches();
 
-  // gpio_initOutputPinWithPullNone(23);
-  // gpio_initOutputPinWithPullNone(24);
-  // gpio_initOutputPinWithPullNone(25);
-  gpio_setPinOutputBool(18, false);
+  // LED
+  gpio_initOutputPinWithPullNone(LED_PIN);
+  board_led_write(true);
+
+  // Button
+  // TODO
+
+  // Uart
   uart_init();
-  gpio_setPinOutputBool(18, true);
-  gpio_setPinOutputBool(18, false);
-  for (size_t i = 0; i < 5; i++) {
-  // while (true) {
-    for (size_t j = 0; j < 1000000; j++) {
-      __asm__("nop");
-    }
-    gpio_setPinOutputBool(42, true);
-    gpio_setPinOutputBool(18, true);
-    gpio_setPinOutputBool(19, true);
-    gpio_setPinOutputBool(20, true);
-    gpio_setPinOutputBool(21, true);
-    for (size_t j = 0; j < 1000000; j++) {
-      __asm__("nop");
-    }
-    gpio_setPinOutputBool(42, false);
-    gpio_setPinOutputBool(18, false);
-    gpio_setPinOutputBool(19, false);
-    gpio_setPinOutputBool(20, false);
-    gpio_setPinOutputBool(21, false);
-  }
-  // uart_writeText("hello from io\n");
-  // gpio_setPinOutputBool(24, true);
-  // gpio_setPinOutputBool(24, false);
-  // gpio_setPinOutputBool(25, true);
-  // print();
-  // gpio_setPinOutputBool(25, false);
-  // while (true) {
-  // // for (size_t i = 0; i < 5; i++) {
-  //   for (size_t j = 0; j < 10000000000; j++) {
-  //     __asm__("nop");
-  //   }
-  //   gpio_setPinOutputBool(42, true);
-  //   for (size_t j = 0; j < 10000000000; j++) {
-  //     __asm__("nop");
-  //   }
-  //   gpio_setPinOutputBool(42, false);
-  // }
-  // while (1) uart_update();
 
   // Turn on USB peripheral.
   vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true);
 
+  // Timer 1/1024 second tick
+  SYSTMR->CS_b.M1 = 1;
+  SYSTMR->C1 = SYSTMR->CLO + 977;
+  BP_EnableIRQ(TIMER_1_IRQn);
+
   BP_SetPriority(USB_IRQn, 0x00);
   BP_ClearPendingIRQ(USB_IRQn);
   BP_EnableIRQ(USB_IRQn);
@@ -115,7 +87,7 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  gpio_setPinOutputBool(42, state);
+  gpio_setPinOutputBool(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
 }
 
 uint32_t board_button_read(void)
@@ -145,9 +117,12 @@ int board_uart_write(void const * buf, int len)
 
 #if CFG_TUSB_OS  == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
+
+void TIMER_1_IRQHandler(void)
 {
   system_ticks++;
+  SYSTMR->C1 += 977;
+  SYSTMR->CS_b.M1 = 1;
 }
 
 uint32_t board_millis(void)
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/raspberrypi4/family.mk
index 475cfa4ff..c65070a71 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/raspberrypi4/family.mk
@@ -48,4 +48,4 @@ $(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf
 # Copy to kernel to netboot drive or SD card
 # Change destinaation to fit your need
 flash: $(BUILD)/kernel8.img
-	@$(CP) $< /home/$(USER)/Documents/code/pi4_tinyusb/boot_cpy
+	$(CP) $< /home/$(USER)/Documents/code/pi4_tinyusb/boot_cpy

From 6cfdf697eba5b2af6ea383c2bed52557d7610893 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 4 Nov 2021 12:42:28 +0700
Subject: [PATCH 0635/2085] add hint/question with ISB

---
 src/portable/synopsys/dwc2/dwc2_bcm.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index 0263d19ba..fcec0b0d2 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -47,7 +47,7 @@ static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
   BP_EnableIRQ(USB_IRQn);
-  __asm__ volatile("isb");
+  __asm__ volatile("isb"); // needed if TIMER1 IRQ is not enabled !?
 }
 
 TU_ATTR_ALWAYS_INLINE
@@ -55,7 +55,7 @@ static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
   (void) rhport;
   BP_DisableIRQ(USB_IRQn);
-  __asm__ volatile("isb");
+  __asm__ volatile("isb"); // needed if TIMER1 IRQ is not enabled !?
 }
 
 static inline void dwc2_remote_wakeup_delay(void)

From 8b3708b44f69a50817ffa9e8a5360e587f3e3fe2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 4 Nov 2021 13:57:03 +0700
Subject: [PATCH 0636/2085] rename l4 board to match other convention

---
 .../{stm32l476_disco => stm32l476disco}/STM32L476VGTx_FLASH.ld    | 0
 hw/bsp/stm32l4/boards/{stm32l476_disco => stm32l476disco}/board.h | 0
 .../stm32l4/boards/{stm32l476_disco => stm32l476disco}/board.mk   | 0
 .../{stm32l4p5_nucleo => stm32l4p5nucleo}/STM32L4P5ZGTX_FLASH.ld  | 0
 .../stm32l4/boards/{stm32l4p5_nucleo => stm32l4p5nucleo}/board.h  | 0
 .../stm32l4/boards/{stm32l4p5_nucleo => stm32l4p5nucleo}/board.mk | 0
 .../{stm32l4r5_nucleo => stm32l4r5nucleo}/STM32L4RXxI_FLASH.ld    | 0
 .../stm32l4/boards/{stm32l4r5_nucleo => stm32l4r5nucleo}/board.h  | 0
 .../stm32l4/boards/{stm32l4r5_nucleo => stm32l4r5nucleo}/board.mk | 0
 9 files changed, 0 insertions(+), 0 deletions(-)
 rename hw/bsp/stm32l4/boards/{stm32l476_disco => stm32l476disco}/STM32L476VGTx_FLASH.ld (100%)
 rename hw/bsp/stm32l4/boards/{stm32l476_disco => stm32l476disco}/board.h (100%)
 rename hw/bsp/stm32l4/boards/{stm32l476_disco => stm32l476disco}/board.mk (100%)
 rename hw/bsp/stm32l4/boards/{stm32l4p5_nucleo => stm32l4p5nucleo}/STM32L4P5ZGTX_FLASH.ld (100%)
 rename hw/bsp/stm32l4/boards/{stm32l4p5_nucleo => stm32l4p5nucleo}/board.h (100%)
 rename hw/bsp/stm32l4/boards/{stm32l4p5_nucleo => stm32l4p5nucleo}/board.mk (100%)
 rename hw/bsp/stm32l4/boards/{stm32l4r5_nucleo => stm32l4r5nucleo}/STM32L4RXxI_FLASH.ld (100%)
 rename hw/bsp/stm32l4/boards/{stm32l4r5_nucleo => stm32l4r5nucleo}/board.h (100%)
 rename hw/bsp/stm32l4/boards/{stm32l4r5_nucleo => stm32l4r5nucleo}/board.mk (100%)

diff --git a/hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32l4/boards/stm32l476_disco/STM32L476VGTx_FLASH.ld
rename to hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
diff --git a/hw/bsp/stm32l4/boards/stm32l476_disco/board.h b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
similarity index 100%
rename from hw/bsp/stm32l4/boards/stm32l476_disco/board.h
rename to hw/bsp/stm32l4/boards/stm32l476disco/board.h
diff --git a/hw/bsp/stm32l4/boards/stm32l476_disco/board.mk b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
similarity index 100%
rename from hw/bsp/stm32l4/boards/stm32l476_disco/board.mk
rename to hw/bsp/stm32l4/boards/stm32l476disco/board.mk
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32l4/boards/stm32l4p5_nucleo/STM32L4P5ZGTX_FLASH.ld
rename to hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
similarity index 100%
rename from hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.h
rename to hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
similarity index 100%
rename from hw/bsp/stm32l4/boards/stm32l4p5_nucleo/board.mk
rename to hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32l4/boards/stm32l4r5_nucleo/STM32L4RXxI_FLASH.ld
rename to hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
similarity index 100%
rename from hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.h
rename to hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
similarity index 100%
rename from hw/bsp/stm32l4/boards/stm32l4r5_nucleo/board.mk
rename to hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk

From f90f5ea3699facfd5681c3bf21e0500f169f8f07 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 4 Nov 2021 16:16:51 +0700
Subject: [PATCH 0637/2085] adding g4 family with g474nucleo, able to blink led
 and button

---
 hw/bsp/stm32f7/boards/stm32f746nucleo/board.h |   2 +
 .../stm32g474nucleo/STM32G474RETx_FLASH.ld    | 190 +++++++++
 hw/bsp/stm32g4/boards/stm32g474nucleo/board.h |  95 +++++
 .../stm32g4/boards/stm32g474nucleo/board.mk   |   8 +
 hw/bsp/stm32g4/family.c                       | 173 ++++++++
 hw/bsp/stm32g4/family.mk                      |  44 ++
 hw/bsp/stm32g4/stm32g4xx_hal_conf.h           | 381 ++++++++++++++++++
 src/device/dcd_attr.h                         |   3 +
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |  16 +-
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   |   4 +
 src/tusb_option.h                             |  22 +-
 11 files changed, 927 insertions(+), 11 deletions(-)
 create mode 100644 hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
 create mode 100644 hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
 create mode 100644 hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
 create mode 100644 hw/bsp/stm32g4/family.c
 create mode 100644 hw/bsp/stm32g4/family.mk
 create mode 100644 hw/bsp/stm32g4/stm32g4xx_hal_conf.h

diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
index 093445ede..92c109a72 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
@@ -76,6 +76,8 @@ static inline void board_clock_init(void)
   RCC_OscInitStruct.PLL.PLLQ = 9;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
+  // TODO need to enable usb clock source
+
   /* Activate the OverDrive to reach the 216 MHz Frequency */
   HAL_PWREx_EnableOverDrive();
 
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
new file mode 100644
index 000000000..935d97c87
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
@@ -0,0 +1,190 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by Ac6 System Workbench
+**
+**  Abstract    : Linker script for STM32G474RETx series
+**                512Kbytes FLASH and 160Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of Ac6 nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
+CCMSRAM (xrw)      : ORIGIN = 0x10000000, LENGTH = 32K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
new file mode 100644
index 000000000..8d33373af
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
@@ -0,0 +1,95 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+// UART Enable for STLink VCOM
+#define UART_DEV              LPUART1
+#define UART_CLK_EN           __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF12_LPUART1
+#define UART_TX_PIN           GPIO_PIN_2
+#define UART_RX_PIN           GPIO_PIN_3
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  // Configure the main internal regulator output voltage
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
+
+  // Initializes the CPU, AHB and APB busses clocks
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 85;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  // Initializes the CPU, AHB and APB busses clocks
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
new file mode 100644
index 000000000..1951fcba0
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
@@ -0,0 +1,8 @@
+CFLAGS += -DSTM32G474xx
+
+LD_FILE = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g474xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32g474re
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
new file mode 100644
index 000000000..cddd85af0
--- /dev/null
+++ b/hw/bsp/stm32g4/family.c
@@ -0,0 +1,173 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stm32g4xx_hal.h"
+#include "bsp/board.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void OTG_HS_IRQHandler(void)
+{
+  tud_int_handler(1);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+UART_HandleTypeDef UartHandle;
+
+void board_init(void)
+{
+  board_clock_init();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+
+  UART_CLK_EN();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  GPIO_InitTypeDef  GPIO_InitStruct;
+
+  // LED
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  board_led_write(false);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+#ifdef UART_DEV
+  // UART
+  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull      = GPIO_PULLUP;
+  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle = (UART_HandleTypeDef){
+    .Instance        = UART_DEV,
+    .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+    .Init.WordLength = UART_WORDLENGTH_8B,
+    .Init.StopBits   = UART_STOPBITS_1,
+    .Init.Parity     = UART_PARITY_NONE,
+    .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+    .Init.Mode       = UART_MODE_TX_RX,
+    .Init.OverSampling = UART_OVERSAMPLING_16
+  };
+  HAL_UART_Init(&UartHandle);
+#endif
+
+  // TODO Configure USB GPIOs
+
+  board_vbus_sense_init();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  return len;
+#else
+  (void) buf; (void) len; (void) UartHandle;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler (void)
+{
+  asm("bkpt");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk
new file mode 100644
index 000000000..04222f3bb
--- /dev/null
+++ b/hw/bsp/stm32g4/family.mk
@@ -0,0 +1,44 @@
+UF2_FAMILY_ID = 0x4c71240a
+ST_FAMILY = g4
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32G4
+
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-align
+
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM4F
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32g4/stm32g4xx_hal_conf.h b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h
new file mode 100644
index 000000000..ad5f7dbd4
--- /dev/null
+++ b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h
@@ -0,0 +1,381 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_CONF_H
+#define STM32G4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+  
+#define HAL_MODULE_ENABLED  
+
+  /*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CORDIC_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_DAC_MODULE_ENABLED   */
+/*#define HAL_FDCAN_MODULE_ENABLED   */
+/*#define HAL_FMAC_MODULE_ENABLED   */
+/*#define HAL_HRTIM_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_NAND_MODULE_ENABLED   */
+/*#define HAL_NOR_MODULE_ENABLED   */
+/*#define HAL_OPAMP_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_SRAM_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+  * @brief This is the list of modules where register callback can be used
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS        0U
+#define USE_HAL_COMP_REGISTER_CALLBACKS       0U
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS     0U
+#define USE_HAL_CRYP_REGISTER_CALLBACKS       0U
+#define USE_HAL_DAC_REGISTER_CALLBACKS        0U
+#define USE_HAL_EXTI_REGISTER_CALLBACKS       0U
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS      0U
+#define USE_HAL_FMAC_REGISTER_CALLBACKS       0U
+#define USE_HAL_HRTIM_REGISTER_CALLBACKS      0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS        0U
+#define USE_HAL_I2S_REGISTER_CALLBACKS        0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS       0U
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS      0U
+#define USE_HAL_NAND_REGISTER_CALLBACKS       0U
+#define USE_HAL_NOR_REGISTER_CALLBACKS        0U
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS      0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS        0U
+#define USE_HAL_QSPI_REGISTER_CALLBACKS       0U
+#define USE_HAL_RNG_REGISTER_CALLBACKS        0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS        0U
+#define USE_HAL_SAI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS      0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS        0U
+#define USE_HAL_SRAM_REGISTER_CALLBACKS       0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS        0U
+#define USE_HAL_UART_REGISTER_CALLBACKS       0U
+#define USE_HAL_USART_REGISTER_CALLBACKS      0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS       0U
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    (24000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+  #define HSI48_VALUE   (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz.
+                                               The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+/*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations in voltage and temperature.*/
+#define LSI_VALUE  (32000UL)     /*!< LSI Typical Value in Hz*/    
+#endif /* LSI_VALUE */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  (32768UL)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */     
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    (5000UL)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S and SAI peripherals
+  *        This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    (12288000UL) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+
+#define  VDD_VALUE                   (3300UL) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY           (0UL)    /*!< tick interrupt priority (lowest by default)  */            
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              0U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32g4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32g4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32g4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32g4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32g4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32g4xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+#include "stm32g4xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32g4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32g4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32g4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32g4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32g4xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32g4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+#include "stm32g4xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+#include "stm32g4xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32g4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32g4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32g4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32g4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32g4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32g4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32g4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32g4xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32g4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32g4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+#include "stm32g4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32g4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32g4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32g4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32g4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32g4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32g4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32g4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32g4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32g4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32g4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32g4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 952a8b8c8..1d34b94ba 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -119,6 +119,9 @@
   #define DCD_ATTR_ENDPOINT_MAX   9
   #define DCD_ATTR_DWC2_STM32
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32G4)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 933f352a2..177a7ad2a 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -110,7 +110,7 @@
 #endif
 
 #if TUSB_OPT_DEVICE_ENABLED && \
-      ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1) || \
+      ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4) || \
         (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) \
       )
 
@@ -296,8 +296,10 @@ void dcd_int_enable (uint8_t rhport)
   __ISB();
 #if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
   NVIC_EnableIRQ(USB_IRQn);
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L1
   NVIC_EnableIRQ(USB_LP_IRQn);
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F3
   // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from
   // shared USB/CAN IRQs to separate CAN and USB IRQs.
@@ -320,6 +322,12 @@ void dcd_int_enable (uint8_t rhport)
   NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn);
   NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
   NVIC_EnableIRQ(USBWakeUp_IRQn);
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
+  NVIC_EnableIRQ(USB_HP_IRQn);
+  NVIC_EnableIRQ(USB_LP_IRQn);
+  NVIC_EnableIRQ(USBWakeUp_IRQn);
+
 #else
   #error Unknown arch in USB driver
 #endif
@@ -356,6 +364,12 @@ void dcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn);
   NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
   NVIC_DisableIRQ(USBWakeUp_IRQn);
+
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
+  NVIC_DisableIRQ(USB_HP_IRQn);
+  NVIC_DisableIRQ(USB_LP_IRQn);
+  NVIC_DisableIRQ(USBWakeUp_IRQn);
+
 #else
   #error Unknown arch in USB driver
 #endif
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index eca8bf575..596f7be6c 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -87,6 +87,10 @@
   #include "stm32l1xx.h"
   #define PMA_LENGTH (512u)
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
+  #include "stm32g4xx.h"
+  #define PMA_LENGTH (1024u)
+
 #else
   #error You are using an untested or unimplemented STM32 variant. Please update the driver.
   // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 4da07e241..c1fc8a71c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -68,16 +68,18 @@
 #define OPT_MCU_SAMX7X            207 ///< MicroChip SAME70, S70, V70, V71 family
 
 // STM32
-#define OPT_MCU_STM32F0           300 ///< ST STM32F0
-#define OPT_MCU_STM32F1           301 ///< ST STM32F1
-#define OPT_MCU_STM32F2           302 ///< ST STM32F2
-#define OPT_MCU_STM32F3           303 ///< ST STM32F3
-#define OPT_MCU_STM32F4           304 ///< ST STM32F4
-#define OPT_MCU_STM32F7           305 ///< ST STM32F7
-#define OPT_MCU_STM32H7           306 ///< ST STM32H7
-#define OPT_MCU_STM32L0           307 ///< ST STM32L0
-#define OPT_MCU_STM32L1           308 ///< ST STM32L1
-#define OPT_MCU_STM32L4           309 ///< ST STM32L4
+#define OPT_MCU_STM32F0           300 ///< ST F0
+#define OPT_MCU_STM32F1           301 ///< ST F1
+#define OPT_MCU_STM32F2           302 ///< ST F2
+#define OPT_MCU_STM32F3           303 ///< ST F3
+#define OPT_MCU_STM32F4           304 ///< ST F4
+#define OPT_MCU_STM32F7           305 ///< ST F7
+#define OPT_MCU_STM32H7           306 ///< ST H7
+#define OPT_MCU_STM32L1           308 ///< ST L1
+#define OPT_MCU_STM32L0           307 ///< ST L0
+#define OPT_MCU_STM32L4           309 ///< ST L4
+#define OPT_MCU_STM32G0           310 ///< ST G0
+#define OPT_MCU_STM32G4           311 ///< ST G4
 
 // Sony
 #define OPT_MCU_CXD56             400 ///< SONY CXD56

From 310f287f4476d22f126c9fc2995f6be7e2b64662 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 4 Nov 2021 17:52:55 +0700
Subject: [PATCH 0638/2085] couldn't get g4 usb clock and pin setup just yet.
 Leave it as it is for now

---
 hw/bsp/stm32g4/boards/stm32g474nucleo/board.h | 35 +++++++++++++++++++
 hw/bsp/stm32g4/family.c                       | 21 ++++++++---
 2 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
index 8d33373af..fd9d50183 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
@@ -31,6 +31,10 @@
  extern "C" {
 #endif
 
+// G474RE Nucleo does not has usb connection. We need to manually connect
+// - PA11 for D+, CN10.14
+// - PA12 for D-, CN10.12
+
 // LED
 #define LED_PORT              GPIOA
 #define LED_PIN               GPIO_PIN_5
@@ -49,6 +53,7 @@
 #define UART_TX_PIN           GPIO_PIN_2
 #define UART_RX_PIN           GPIO_PIN_3
 
+
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
@@ -81,6 +86,36 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
+
+#if 0 // TODO need to check if USB clock is enabled
+  /* Enable HSI48 */
+  memset(&RCC_OscInitStruct, 0, sizeof(RCC_OscInitStruct));
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /*Enable CRS Clock*/
+  RCC_CRSInitTypeDef RCC_CRSInitStruct= {0};
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+  /* Set the TRIM[5:0] to the default value */
+  RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+  /* Start automatic synchronization */
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
 }
 
 static inline void board_vbus_sense_init(void)
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index cddd85af0..318f50746 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -31,14 +31,19 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
+void USB_HP_IRQHandler(void)
 {
   tud_int_handler(0);
 }
 
-void OTG_HS_IRQHandler(void)
+void USB_LP_IRQHandler(void)
 {
-  tud_int_handler(1);
+  tud_int_handler(0);
+}
+
+void USBWakeUp_IRQHandler(void)
+{
+  tud_int_handler(0);
 }
 
 //--------------------------------------------------------------------+
@@ -111,7 +116,15 @@ void board_init(void)
   HAL_UART_Init(&UartHandle);
 #endif
 
-  // TODO Configure USB GPIOs
+  // USB Pins TODO double check USB clock and pin setup
+  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+//  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+//  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+//  GPIO_InitStruct.Pull = GPIO_NOPULL;
+//  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+//  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+//
+//  __HAL_RCC_USB_CLK_ENABLE();
 
   board_vbus_sense_init();
 }

From e35bb6341cd3a9b81085969cdce60cb3af9ed57e Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Thu, 4 Nov 2021 21:46:17 +0100
Subject: [PATCH 0639/2085] broadcom/dcd: Fix mynewt build

dcd_synopsys.c included broadcom/interrupts.h before
preprocessor check whether file should be used.

Since mynewt build does not include all folders it resulted in build
error.

Now offending include is moved few lines after preprocessor check.
---
 src/portable/broadcom/synopsys/dcd_synopsys.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c
index 041158871..494bb70ee 100644
--- a/src/portable/broadcom/synopsys/dcd_synopsys.c
+++ b/src/portable/broadcom/synopsys/dcd_synopsys.c
@@ -29,6 +29,10 @@
 
 #include "tusb_option.h"
 
+#if TUSB_OPT_DEVICE_ENABLED &&         \
+    (CFG_TUSB_MCU == OPT_MCU_BCM2711 ) \
+
+
 #include "synopsys_common.h"
 
 #include "broadcom/interrupts.h"
@@ -37,10 +41,6 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if TUSB_OPT_DEVICE_ENABLED &&         \
-    (CFG_TUSB_MCU == OPT_MCU_BCM2711 ) \
-
-
 // EP_MAX       : Max number of bi-directional endpoints including EP0
 // EP_FIFO_SIZE : Size of dedicated USB SRAM
 #if CFG_TUSB_MCU == OPT_MCU_BCM2711

From ec99bec8cba0ba948832c19641468558d59f6289 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Thu, 4 Nov 2021 23:00:05 +0000
Subject: [PATCH 0640/2085] docs: update supported device table

remove known issue #750 from silabs EFM32GG table entry
---
 docs/reference/supported.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index ef924adb4..1c3ef5a07 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -88,7 +88,7 @@ Supported MCUs
 |              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
 |              | RX65N              | |:green_square:|  |                    | |:green_square:|  | |:x:|             |              |
 +--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| Silabs       | EFM32GG12          | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             | #750         |
+| Silabs       | EFM32GG12          | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
 +--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
 | Sony         | CXD56              | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
 +--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+

From a3fc107d94f5126667a51f82b7997a3c629972c4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 5 Nov 2021 11:40:53 +0700
Subject: [PATCH 0641/2085] xmc4500 led blinky, button ok

---
 examples/device/board_test/src/main.c        |   1 +
 hw/bsp/xmc4000/boards/xmc4500_relax/board.h  |  88 ++++++++++++++
 hw/bsp/xmc4000/boards/xmc4500_relax/board.mk |   9 ++
 hw/bsp/xmc4000/family.c                      | 117 +++++++++++++++++++
 hw/bsp/xmc4000/family.mk                     |  37 ++++++
 src/device/dcd_attr.h                        |   4 +
 src/tusb_option.h                            |   3 +
 7 files changed, 259 insertions(+)
 create mode 100644 hw/bsp/xmc4000/boards/xmc4500_relax/board.h
 create mode 100644 hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
 create mode 100644 hw/bsp/xmc4000/family.c
 create mode 100644 hw/bsp/xmc4000/family.mk

diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index c77dd5647..5e28cbb27 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -47,6 +47,7 @@ enum  {
 int main(void)
 {
   board_init();
+  board_led_write(true);
 
   uint32_t start_ms = 0;
   bool led_state = false;
diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h
new file mode 100644
index 000000000..3e2cb9583
--- /dev/null
+++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h
@@ -0,0 +1,88 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PIN               P1_1
+#define LED_STATE_ON          1
+
+#define BUTTON_PIN            P1_14
+#define BUTTON_STATE_ACTIVE   0
+
+//#define UART_DEV              USART6
+//#define UART_CLK_EN           __HAL_RCC_USART6_CLK_ENABLE
+//#define UART_GPIO_AF          GPIO_AF8_USART6
+//
+//#define UART_TX_PORT          GPIOC
+//#define UART_TX_PIN           GPIO_PIN_6
+//
+//#define UART_RX_PORT          GPIOC
+//#define UART_RX_PIN           GPIO_PIN_7
+
+static inline void board_clock_init(void)
+{
+  /* Clock configuration */
+  /* fPLL = 120MHz */
+  /* fSYS = 120MHz */
+  /* fUSBPLL = 192MHz */
+  /* fUSB = 48MHz */
+  const XMC_SCU_CLOCK_CONFIG_t clock_config =
+  {
+    .syspll_config.p_div  = 2,
+    .syspll_config.n_div  = 80,
+    .syspll_config.k_div  = 4,
+    .syspll_config.mode   = XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL,
+    .syspll_config.clksrc = XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP,
+    .enable_oschp         = true,
+    .calibration_mode     = XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY,
+    .fsys_clksrc          = XMC_SCU_CLOCK_SYSCLKSRC_PLL,
+    .fsys_clkdiv          = 1,
+    .fcpu_clkdiv          = 1,
+    .fccu_clkdiv          = 1,
+    .fperipheral_clkdiv   = 1
+  };
+
+  /* Setup settings for USB clock */
+  XMC_SCU_CLOCK_Init(&clock_config);
+
+  XMC_SCU_CLOCK_EnableUsbPll();
+  XMC_SCU_CLOCK_StartUsbPll(2, 64);
+  XMC_SCU_CLOCK_SetUsbClockDivider(4);
+  XMC_SCU_CLOCK_SetUsbClockSource(XMC_SCU_CLOCK_USBCLKSRC_USBPLL);
+  XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_USB);
+}
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
new file mode 100644
index 000000000..a2c2c5aaf
--- /dev/null
+++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
@@ -0,0 +1,9 @@
+MCU_VARIANT = XMC4500
+CFLAGS += \
+  -DXMC4500_F100x1024 \
+
+LD_FILE = $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld
+
+JLINK_DEVICE = XMC4500-1024
+
+flash: flash-jlink
diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c
new file mode 100644
index 000000000..8b5f82f15
--- /dev/null
+++ b/hw/bsp/xmc4000/family.c
@@ -0,0 +1,117 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "xmc_gpio.h"
+#include "xmc_scu.h"
+
+#include "bsp/board.h"
+#include "board.h"
+
+void board_init(void)
+{
+  board_clock_init();
+  SystemCoreClockUpdate();
+
+  // LED
+  XMC_GPIO_CONFIG_t led_cfg;
+  led_cfg.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
+  led_cfg.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH;
+  led_cfg.output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM;
+  XMC_GPIO_Init(LED_PIN, &led_cfg);
+
+  // Button
+  XMC_GPIO_CONFIG_t button_cfg;
+  button_cfg.mode = XMC_GPIO_MODE_INPUT_TRISTATE;
+  XMC_GPIO_Init(BUTTON_PIN, &button_cfg);
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  uint32_t is_high = state ? LED_STATE_ON : (1-LED_STATE_ON);
+
+  XMC_GPIO_SetOutputLevel(LED_PIN, is_high ? XMC_GPIO_OUTPUT_LEVEL_HIGH : XMC_GPIO_OUTPUT_LEVEL_LOW);
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == XMC_GPIO_GetInput(BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+#ifdef UART_DEV
+  for(int i=0;i<len;i++) {
+    buf[i] = uart_getc(uart_inst);
+  }
+  return len;
+#else
+  (void) buf; (void) len;
+  return 0;
+#endif
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+  char const* bufch = (char const*) buf;
+  for(int i=0;i<len;i++) {
+    uart_putc(uart_inst, bufch[i]);
+  }
+  return len;
+#else
+  (void) buf; (void) len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk
new file mode 100644
index 000000000..fc417d41d
--- /dev/null
+++ b/hw/bsp/xmc4000/family.mk
@@ -0,0 +1,37 @@
+UF2_FAMILY_ID = 0x00
+MCU_DIR = hw/mcu/infineon/mtb-xmclib-cat3
+
+#DEPS_SUBMODULES += $(MCU_DIR)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_XMC4000
+
+# mcu driver cause following warnings
+#CFLAGS += -Wno-error=shadow -Wno-error=cast-align
+
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	$(MCU_DIR)/Newlib/syscalls.c \
+	$(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/system_$(MCU_VARIANT).c \
+	$(MCU_DIR)/XMCLib/src/xmc4_gpio.c \
+	$(MCU_DIR)/XMCLib/src/xmc4_scu.c
+
+SRC_S += $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/startup_$(MCU_VARIANT).S
+
+INC += \
+  $(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MCU_DIR)/CMSIS/Core/Include \
+	$(TOP)/$(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Include \
+	$(TOP)/$(MCU_DIR)/XMCLib/inc
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM4F
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 1d34b94ba..15d8ce204 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -188,6 +188,10 @@
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
+//------------- Broadcom -------------//
+#elif TU_CHECK_MCU(OPT_MCU_XMC4000)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
 #else
   #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define DCD_ATTR_ENDPOINT_MAX   8
diff --git a/src/tusb_option.h b/src/tusb_option.h
index c1fc8a71c..e33d5a057 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -130,6 +130,9 @@
 // Broadcom
 #define OPT_MCU_BCM2711          1700 ///< Broadcom BCM2711
 
+// Infineon
+#define OPT_MCU_XMC4000          1800 ///< Infineon XMC4000
+
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
 #define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == _m)

From d9cf49cbfd2e677f30f993257ffd5d1218fe21cf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 5 Nov 2021 12:00:27 +0700
Subject: [PATCH 0642/2085] add xmclib as submodule

---
 .gitmodules                     | 3 +++
 hw/bsp/xmc4000/family.mk        | 2 +-
 hw/mcu/infineon/mtb-xmclib-cat3 | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)
 create mode 160000 hw/mcu/infineon/mtb-xmclib-cat3

diff --git a/.gitmodules b/.gitmodules
index a95e64ee6..5c79ea910 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -131,3 +131,6 @@
 	path = hw/mcu/broadcom
 	url = https://github.com/adafruit/broadcom-peripherals.git
 	branch = main-build
+[submodule "hw/mcu/infineon/mtb-xmclib-cat3"]
+	path = hw/mcu/infineon/mtb-xmclib-cat3
+	url = https://github.com/Infineon/mtb-xmclib-cat3.git
diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk
index fc417d41d..e5b9f7b1a 100644
--- a/hw/bsp/xmc4000/family.mk
+++ b/hw/bsp/xmc4000/family.mk
@@ -1,7 +1,7 @@
 UF2_FAMILY_ID = 0x00
 MCU_DIR = hw/mcu/infineon/mtb-xmclib-cat3
 
-#DEPS_SUBMODULES += $(MCU_DIR)
+DEPS_SUBMODULES += $(MCU_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
diff --git a/hw/mcu/infineon/mtb-xmclib-cat3 b/hw/mcu/infineon/mtb-xmclib-cat3
new file mode 160000
index 000000000..daf5500d0
--- /dev/null
+++ b/hw/mcu/infineon/mtb-xmclib-cat3
@@ -0,0 +1 @@
+Subproject commit daf5500d03cba23e68c2f241c30af79cd9d63880

From d87a897a7bc524139f844a323df4e0679b2deebe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 5 Nov 2021 13:13:21 +0700
Subject: [PATCH 0643/2085] xmc4500 ported, cdc msc example run fine

---
 hw/bsp/xmc4000/family.c                  | 13 ++++
 hw/bsp/xmc4000/family.mk                 |  3 +
 src/portable/synopsys/dwc2/dcd_dwc2.c    |  4 +-
 src/portable/synopsys/dwc2/dwc2_xmc.h    | 87 ++++++++++++++++++++++++
 src/portable/synopsys/dwc2/hwcfg_list.md | 55 +++++++++++++++
 5 files changed, 161 insertions(+), 1 deletion(-)
 create mode 100644 src/portable/synopsys/dwc2/dwc2_xmc.h

diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c
index 8b5f82f15..bf6684736 100644
--- a/hw/bsp/xmc4000/family.c
+++ b/hw/bsp/xmc4000/family.c
@@ -30,6 +30,15 @@
 #include "bsp/board.h"
 #include "board.h"
 
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_0_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
 void board_init(void)
 {
   board_clock_init();
@@ -58,6 +67,10 @@ void board_init(void)
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB0_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
+
+  // USB Power Enable
+  XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0);
+  XMC_SCU_POWER_EnableUsb();
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk
index e5b9f7b1a..0b32bdeb5 100644
--- a/hw/bsp/xmc4000/family.mk
+++ b/hw/bsp/xmc4000/family.mk
@@ -18,6 +18,8 @@ CFLAGS += \
 # mcu driver cause following warnings
 #CFLAGS += -Wno-error=shadow -Wno-error=cast-align
 
+SKIP_NANOLIB = 1
+
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(MCU_DIR)/Newlib/syscalls.c \
@@ -25,6 +27,7 @@ SRC_C += \
 	$(MCU_DIR)/XMCLib/src/xmc4_gpio.c \
 	$(MCU_DIR)/XMCLib/src/xmc4_scu.c
 
+
 SRC_S += $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/startup_$(MCU_VARIANT).S
 
 INC += \
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 3967f225e..44a5f8932 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -33,7 +33,7 @@
 #if TUSB_OPT_DEVICE_ENABLED && \
     ( defined(DCD_ATTR_DWC2_STM32) || \
       TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) || \
-      TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711) )
+      TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711, OPT_MCU_XMC4000) )
 
 #include "device/dcd.h"
 #include "dwc2_type.h"
@@ -48,6 +48,8 @@
   #include "dwc2_bcm.h"
 #elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
   #include "dwc2_efm32.h"
+#elif TU_CHECK_MCU(OPT_MCU_XMC4000)
+  #include "dwc2_xmc.h"
 #else
   #error "Unsupported MCUs"
 #endif
diff --git a/src/portable/synopsys/dwc2/dwc2_xmc.h b/src/portable/synopsys/dwc2/dwc2_xmc.h
new file mode 100644
index 000000000..4e6bebb01
--- /dev/null
+++ b/src/portable/synopsys/dwc2/dwc2_xmc.h
@@ -0,0 +1,87 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Rafael Silva (@perigoso)
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _DWC2_XMC_H_
+#define _DWC2_XMC_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "xmc_device.h"
+
+// XMC has custom control register before DWC registers
+#define DWC2_REG_BASE       USB0_BASE
+#define DWC2_EP_MAX         7
+#define DWC2_EP_FIFO_SIZE   2048
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USB0_0_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void dwc2_dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB0_0_IRQn);
+}
+
+static inline void dwc2_remote_wakeup_delay(void)
+{
+  // try to delay for 1 ms
+//  uint32_t count = SystemCoreClock / 1000;
+//  while ( count-- ) __NOP();
+}
+
+// MCU specific PHY init, called BEFORE core reset
+static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+  (void) dwc2;
+  (void) hs_phy_type;
+
+  // Enable PHY
+  //USB->ROUTE = USB_ROUTE_PHYPEN;
+}
+
+// MCU specific PHY update, it is called AFTER init() and core reset
+static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
+{
+  (void) dwc2;
+  (void) hs_phy_type;
+
+  // XMC Manual: turn around must be 5 (reset & default value)
+  // dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/portable/synopsys/dwc2/hwcfg_list.md b/src/portable/synopsys/dwc2/hwcfg_list.md
index 495a30fd0..b5590da00 100644
--- a/src/portable/synopsys/dwc2/hwcfg_list.md
+++ b/src/portable/synopsys/dwc2/hwcfg_list.md
@@ -720,3 +720,58 @@ hw_cfg4->dedicated_fifos = 0
 hw_cfg4->num_dev_in_eps = 0
 hw_cfg4->dma_desc_enable = 0
 hw_cfg4->dma_dynamic = 0
+
+## XMC4500
+
+dwc2->guid = AEC000
+dwc2->gsnpsid = 4F54292A
+dwc2->ghwcfg1 = 0
+
+dwc2->ghwcfg2 = 228F5930
+hw_cfg2->op_mode = 0
+hw_cfg2->arch = 2
+hw_cfg2->point2point = 1
+hw_cfg2->hs_phy_type = 0
+hw_cfg2->fs_phy_type = 1
+hw_cfg2->num_dev_ep = 6
+hw_cfg2->num_host_ch = 13
+hw_cfg2->period_channel_support = 1
+hw_cfg2->enable_dynamic_fifo = 1
+hw_cfg2->mul_cpu_int = 0
+hw_cfg2->nperiod_tx_q_depth = 2
+hw_cfg2->host_period_tx_q_depth = 2
+hw_cfg2->dev_token_q_depth = 8
+hw_cfg2->otg_enable_ic_usb = 0
+
+dwc2->ghwcfg3 = 27A01E5
+hw_cfg3->xfer_size_width = 5
+hw_cfg3->packet_size_width = 6
+hw_cfg3->otg_enable = 1
+hw_cfg3->i2c_enable = 1
+hw_cfg3->vendor_ctrl_itf = 0
+hw_cfg3->optional_feature_removed = 0
+hw_cfg3->synch_reset = 0
+hw_cfg3->otg_adp_support = 0
+hw_cfg3->otg_enable_hsic = 0
+hw_cfg3->battery_charger_support = 0
+hw_cfg3->lpm_mode = 0
+hw_cfg3->total_fifo_size = 634
+
+dwc2->ghwcfg4 = DBF08030
+hw_cfg4->num_dev_period_in_ep = 0
+hw_cfg4->power_optimized = 1
+hw_cfg4->ahb_freq_min = 1
+hw_cfg4->hibernation = 0
+hw_cfg4->service_interval_mode = 0
+hw_cfg4->ipg_isoc_en = 0
+hw_cfg4->acg_enable = 0
+hw_cfg4->utmi_phy_data_width = 2
+hw_cfg4->dev_ctrl_ep_num = 0
+hw_cfg4->iddg_filter_enabled = 1
+hw_cfg4->vbus_valid_filter_enabled = 1
+hw_cfg4->a_valid_filter_enabled = 1
+hw_cfg4->b_valid_filter_enabled = 1
+hw_cfg4->dedicated_fifos = 1
+hw_cfg4->num_dev_in_eps = 13
+hw_cfg4->dma_desc_enable = 0
+hw_cfg4->dma_dynamic = 1

From 422f439bf73450b9f08ff6fb2bf961205ba1c5f5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 5 Nov 2021 13:18:54 +0700
Subject: [PATCH 0644/2085] update docs

---
 README.rst                   | 1 +
 docs/reference/supported.rst | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/README.rst b/README.rst
index 1db022fc8..60df78ca4 100644
--- a/README.rst
+++ b/README.rst
@@ -34,6 +34,7 @@ The stack supports the following MCUs:
 
 - **Dialog:** DA1469x
 - **Espressif:** ESP32-S2, ESP32-S3
+- **Infineon:** XMC4500
 - **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAME7x
 - **NordicSemi:** nRF52833, nRF52840, nRF5340
 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index ef924adb4..95f3e1da9 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -149,6 +149,14 @@ Espressif ESP32-S2
 -  `ESP32-S2-Kaluga-1 <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit.html>`__
 -  `ESP32-S2-Saola-1 <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html>`__
 
+Infineon
+---------
+
+XMC4000
+^^^^^^^
+
+-  `XMC4500 Relax (Lite) Kit <https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc45_relax_lite_v1/>`__
+
 MicroChip
 ---------
 

From 3fc3e400b0ad91a0f15fe0c45bb924a9b1d65249 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 5 Nov 2021 13:23:31 +0700
Subject: [PATCH 0645/2085] add xmc4000 to ci build

---
 .github/workflows/build_arm.yml | 1 +
 hw/bsp/board_mcu.h              | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 53a1628a0..8db0fe04f 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -57,6 +57,7 @@ jobs:
         - 'stm32f7'
         - 'stm32h7'
         - 'stm32l4'
+        - 'xmc4000'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v2
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index c840db89e..1e2577de0 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -136,6 +136,10 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_MM32F327X
   #include "mm32_device.h"
+
+#elif CFG_TUSB_MCU == OPT_MCU_XMC4000
+  #include "xmc_device.h"
+
 #else
   #error "Missing MCU header"
 #endif

From e692fa9ae4b6c8ff7b66dedbecaf745ae2166851 Mon Sep 17 00:00:00 2001
From: Liam Fraser <liam@raspberrypi.com>
Date: Fri, 5 Nov 2021 09:39:31 +0000
Subject: [PATCH 0646/2085] RP2040 HCD: Move invalid ep->active assert in
 hw_trans_complete. The check for ep->active should only happen if a setup
 packet was just sent. Otherwise the transaction is handled in
 hw_handle_buff_status.

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 627e957e8..768cccc86 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -160,12 +160,11 @@ static void hw_handle_buff_status(void)
 
 static void hw_trans_complete(void)
 {
-  struct hw_endpoint *ep = &epx;
-  assert(ep->active);
-
   if (usb_hw->sie_ctrl & USB_SIE_CTRL_SEND_SETUP_BITS)
   {
     pico_trace("Sent setup packet\n");
+    struct hw_endpoint *ep = &epx;
+    assert(ep->active);
     hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
   }
   else

From ec8ece2c9d0f801d6aa763b964719d375c5441d4 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 5 Nov 2021 12:23:59 +0100
Subject: [PATCH 0647/2085] bth: Update driver to interface association changes

Two interfaces that are required by Bluetooth Primary Controller
do not have IAD according to Bluetooth specification.
Those two interfaces were opened separately in process_set_config().

Later interface association was inferred for BTH (along with other
drivers), since then only one call to open() is place for BTH driver
that should prepare both interfaces at once.

To make it work again btd_open() parses two interfaces at once.
---
 src/class/bth/bth_device.c | 112 +++++++++++++++++++------------------
 1 file changed, 58 insertions(+), 54 deletions(-)

diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index f445deed2..8ef609622 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -112,74 +112,78 @@ uint16_t btd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_
             TUD_BT_APP_SUBCLASS == itf_desc->bInterfaceSubClass &&
             TUD_BT_PROTOCOL_PRIMARY_CONTROLLER == itf_desc->bInterfaceProtocol, 0);
 
-  // Distinguish interface by number of endpoints, as both interface have same class, subclass and protocol
-  if (itf_desc->bNumEndpoints == 3 && max_len >= hci_itf_size)
-  {
-    _btd_itf.itf_num = itf_desc->bInterfaceNumber;
+  TU_ASSERT(itf_desc->bNumEndpoints == 3 && max_len >= hci_itf_size);
 
-    desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+  _btd_itf.itf_num = itf_desc->bInterfaceNumber;
 
-    TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0);
-    TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0);
-    _btd_itf.ep_ev = desc_ep->bEndpointAddress;
+  desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
 
-    // Open endpoint pair
-    TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(desc_ep), 2, TUSB_XFER_BULK, &_btd_itf.ep_acl_out,
-                                  &_btd_itf.ep_acl_in), 0);
+  TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0);
+  TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0);
+  _btd_itf.ep_ev = desc_ep->bEndpointAddress;
 
-    // Prepare for incoming data from host
-    TU_ASSERT(usbd_edpt_xfer(rhport, _btd_itf.ep_acl_out, _btd_itf.epout_buf, CFG_TUD_BTH_DATA_EPSIZE), 0);
+  // Open endpoint pair
+  TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(desc_ep), 2, TUSB_XFER_BULK, &_btd_itf.ep_acl_out,
+                                &_btd_itf.ep_acl_in), 0);
 
-    drv_len = hci_itf_size;
-  }
-  else if (itf_desc->bNumEndpoints == 2 && max_len >= iso_alt_itf_size)
-  {
-    uint8_t dir;
+  itf_desc = (tusb_desc_interface_t const *)tu_desc_next(tu_desc_next(tu_desc_next(desc_ep)));
+
+  // Prepare for incoming data from host
+  TU_ASSERT(usbd_edpt_xfer(rhport, _btd_itf.ep_acl_out, _btd_itf.epout_buf, CFG_TUD_BTH_DATA_EPSIZE), 0);
+
+  drv_len = hci_itf_size;
+
+  // Ensure this is still BT Primary Controller
+  TU_ASSERT(TUSB_CLASS_WIRELESS_CONTROLLER == itf_desc->bInterfaceClass &&
+            TUD_BT_APP_SUBCLASS == itf_desc->bInterfaceSubClass &&
+            TUD_BT_PROTOCOL_PRIMARY_CONTROLLER == itf_desc->bInterfaceProtocol, 0);
+  TU_ASSERT(itf_desc->bNumEndpoints == 2 && max_len >= iso_alt_itf_size + drv_len);
+
+  uint8_t dir;
+
+  desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(itf_desc);
+  TU_ASSERT(itf_desc->bAlternateSetting < CFG_TUD_BTH_ISO_ALT_COUNT, 0);
+  TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT, 0);
+  dir = tu_edpt_dir(desc_ep->bEndpointAddress);
+  _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress;
+  // Store endpoint size for alternative
+  _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep);
+
+  desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep);
+  TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT, 0);
+  dir = tu_edpt_dir(desc_ep->bEndpointAddress);
+  _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress;
+  // Store endpoint size for alternative
+  _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep);
+  drv_len += iso_alt_itf_size;
+
+  for (int i = 1; i < CFG_TUD_BTH_ISO_ALT_COUNT && drv_len + iso_alt_itf_size <= max_len; ++i) {
+    // Make sure rest of alternatives matches
+    itf_desc = (tusb_desc_interface_t const *)tu_desc_next(desc_ep);
+    if (itf_desc->bDescriptorType != TUSB_DESC_INTERFACE ||
+        TUSB_CLASS_WIRELESS_CONTROLLER != itf_desc->bInterfaceClass ||
+        TUD_BT_APP_SUBCLASS != itf_desc->bInterfaceSubClass ||
+        TUD_BT_PROTOCOL_PRIMARY_CONTROLLER != itf_desc->bInterfaceProtocol)
+    {
+      // Not an Iso interface instance
+      break;
+    }
+    TU_ASSERT(itf_desc->bAlternateSetting < CFG_TUD_BTH_ISO_ALT_COUNT, 0);
 
     desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(itf_desc);
-    TU_ASSERT(itf_desc->bAlternateSetting < CFG_TUD_BTH_ISO_ALT_COUNT, 0);
-    TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT, 0);
     dir = tu_edpt_dir(desc_ep->bEndpointAddress);
-    _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress;
-    // Store endpoint size for alternative
+    // Verify that alternative endpoint are same as first ones
+    TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT &&
+              _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0);
     _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep);
 
     desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep);
-    TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT, 0);
     dir = tu_edpt_dir(desc_ep->bEndpointAddress);
-    _btd_itf.ep_voice[dir] = desc_ep->bEndpointAddress;
-    // Store endpoint size for alternative
+    // Verify that alternative endpoint are same as first ones
+    TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT &&
+              _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0);
     _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep);
     drv_len += iso_alt_itf_size;
-
-    for (int i = 1; i < CFG_TUD_BTH_ISO_ALT_COUNT && drv_len + iso_alt_itf_size <= max_len; ++i) {
-      // Make sure rest of alternatives matches
-      itf_desc = (tusb_desc_interface_t const *)tu_desc_next(desc_ep);
-      if (itf_desc->bDescriptorType != TUSB_DESC_INTERFACE ||
-          TUSB_CLASS_WIRELESS_CONTROLLER != itf_desc->bInterfaceClass ||
-          TUD_BT_APP_SUBCLASS != itf_desc->bInterfaceSubClass ||
-          TUD_BT_PROTOCOL_PRIMARY_CONTROLLER != itf_desc->bInterfaceProtocol)
-      {
-        // Not an Iso interface instance
-        break;
-      }
-      TU_ASSERT(itf_desc->bAlternateSetting < CFG_TUD_BTH_ISO_ALT_COUNT, 0);
-
-      desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(itf_desc);
-      dir = tu_edpt_dir(desc_ep->bEndpointAddress);
-      // Verify that alternative endpoint are same as first ones
-      TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT &&
-                _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0);
-      _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep);
-
-      desc_ep = (tusb_desc_endpoint_t const *)tu_desc_next(desc_ep);
-      dir = tu_edpt_dir(desc_ep->bEndpointAddress);
-      // Verify that alternative endpoint are same as first ones
-      TU_ASSERT(desc_ep->bDescriptorType == TUSB_DESC_ENDPOINT &&
-                _btd_itf.ep_voice[dir] == desc_ep->bEndpointAddress, 0);
-      _btd_itf.ep_voice_size[dir][itf_desc->bAlternateSetting] = (uint8_t) tu_edpt_packet_size(desc_ep);
-      drv_len += iso_alt_itf_size;
-    }
   }
 
   return drv_len;

From d20a5b3a0918cdccfccbed6f623ff0e854392c82 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 5 Nov 2021 13:03:31 +0100
Subject: [PATCH 0648/2085] bth: Add IAD to BT descriptor

Bluetooth's specification defines IAD for primary controller.
While it seems that Windows and Linux can leave without this,
there is no reason TinyUSB should not provide it.
---
 src/device/usbd.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/device/usbd.h b/src/device/usbd.h
index 8d02de1ff..ec34817fa 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -763,8 +763,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 #define CFG_TUD_BTH_ISO_ALT_COUNT 0
 #endif
 
-// Length of template descriptor: 30 bytes + number of ISO alternatives * 23
-#define TUD_BTH_DESC_LEN (9 + 7 + 7 + 7 + (CFG_TUD_BTH_ISO_ALT_COUNT) * (9 + 7 + 7))
+// Length of template descriptor: 38 bytes + number of ISO alternatives * 23
+#define TUD_BTH_DESC_LEN (8 + 9 + 7 + 7 + 7 + (CFG_TUD_BTH_ISO_ALT_COUNT) * (9 + 7 + 7))
 
 /* Primary Interface */
 #define TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \
@@ -806,6 +806,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 // Interface number, string index, attributes, event endpoint, event endpoint size, interval, data in, data out, data endpoint size, iso endpoint sizes
 // TODO BTH should also use IAD like CDC for composite device
 #define TUD_BTH_DESCRIPTOR(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size,...) \
+  /* Interface Associate */\
+  8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, 0,\
   TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \
   TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__)
 

From f183d0810bb4570bf569cb08a6644933b8813dff Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 23 Oct 2021 15:14:28 +0900
Subject: [PATCH 0649/2085] Add files for msp432e4

---
 .../msp432e4/boards/msp_exp432e401y/board.h   |  46 +++++
 hw/bsp/msp432e4/family.c                      | 174 ++++++++++++++++++
 hw/bsp/msp432e4/family.mk                     |  48 +++++
 src/device/dcd_attr.h                         |   2 +-
 src/tusb_option.h                             |   1 +
 5 files changed, 270 insertions(+), 1 deletion(-)
 create mode 100644 hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
 create mode 100644 hw/bsp/msp432e4/family.c
 create mode 100644 hw/bsp/msp432e4/family.mk

diff --git a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
new file mode 100644
index 000000000..b449f3ca4
--- /dev/null
+++ b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
@@ -0,0 +1,46 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#define LED_PORT              P1OUT
+#define LED_PIN               BIT0
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           P1IN
+#define BUTTON_PIN            BIT1
+#define BUTTON_STATE_ACTIVE   0
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
new file mode 100644
index 000000000..3bb36042d
--- /dev/null
+++ b/hw/bsp/msp432e4/family.c
@@ -0,0 +1,174 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+#include "board.h"
+#include "msp.h"
+
+/* Frequency of the external crystal oscillator */
+#define XTAL_FREQUENCY   25000000UL
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+void board_init(void)
+{
+  /* Turn off power domains that unused peripherals belong to */
+  SYSCTL->PCCAN  = 0u;
+#ifdef __MCU_HAS_LCD0__
+  SYSCTL->PCLCD  = 0u;
+#endif
+  SYSCTL->PCEMAC = 0u;
+  SYSCTL->PCEPHY = 0u;
+  SYSCTL->PCCCM  = 0u;
+
+  /* --- Setup system clock --- */
+  /* Start power-up process of the main oscillator */
+  SYSCTL->MOSCCTL = SYSCTL_MOSCCTL_OSCRNG;
+  while (!(SYSCTL->RIS & SYSCTL_RIS_MOSCPUPRIS)) ; /* Wait for completion */
+  SYSCTL->MISC = SYSCTL_MISC_MOSCPUPMIS; /* Clear the completion interrupt status */
+  /* Set the main oscillator to PLL reference clock */
+  SYSCTL->RSCLKCFG = SYSCTL_RSCLKCFG_PLLSRC_MOSC;
+  /* PLL freq. = (MOSC freq. / 10) * 96 = 240MHz */
+  SYSCTL->PLLFREQ1 = (4 << SYSCTL_PLLFREQ1_N_S) | (1 << SYSCTL_PLLFREQ1_Q_S);
+  SYSCTL->PLLFREQ0 = (96 << SYSCTL_PLLFREQ0_MINT_S) | SYSCTL_PLLFREQ0_PLLPWR;
+  /* Set BCHT=6, BCE=0, WS=5 for 120MHz system clock */
+  SYSCTL->MEMTIM0 = SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) |
+    SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) | SYSCTL_MEMTIM0_MB1;
+  /* Wait for completion of PLL power-up process */
+  while (!(SYSCTL->RIS & SYSCTL_RIS_PLLLRIS)) ;
+  SYSCTL->MISC = SYSCTL_MISC_PLLLMIS; /* Clear the completion interrupt status */
+  /* Switch the system clock to PLL/4 */
+  SYSCTL->RSCLKCFG = SYSCTL_RSCLKCFG_MEMTIMU | SYSCTL_RSCLKCFG_ACG |
+         SYSCTL_RSCLKCFG_USEPLL | SYSCTL_RSCLKCFG_PLLSRC_MOSC | (1 << SYSCTL_RSCLKCFG_PSYSDIV_S);
+
+  SystemCoreClockUpdate();
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+  /* USR_LED1 PN1 */
+  SYSCTL->RCGCGPIO |= 1u << 12;
+  while (!(SYSCTL->PRGPIO & (1u << 12))) ;
+  GPION->DIR        = 2u;
+  GPION->DEN        = 2u;
+
+  /* USR_SW1 PJ0 */
+  SYSCTL->RCGCGPIO |= 1u << 8;
+  while (!(SYSCTL->PRGPIO & (1u << 8))) ;
+  GPIOJ->PUR        = 1u;
+  GPIOJ->DEN        = 1u;
+
+  /* UART PA0,1 */
+  SYSCTL->RCGCGPIO |= 1u << 0;
+  while (!(SYSCTL->PRGPIO & (1u << 0))) ;
+  GPIOA->AFSEL      = 3u;
+  GPIOA->PCTL       = 0x11u;
+  GPIOA->DEN        = 3u;
+
+  SYSCTL->RCGCUART |= 1u << 0;
+  while (!(SYSCTL->PRUART & (1u << 0))) ;
+  UART0->CTL        = 0;
+  UART0->IBRD       = 8;  /* 8.68056 = 16MHz / (16 * 115200) */
+  UART0->FBRD       = 44; /* 0.6875 = 44/64 -> 115108bps (0.08%) */
+  UART0->LCRH       = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
+  UART0->CC         = UART_CC_CS_PIOSC; /* Set the baud clock to PIOSC */
+  UART0->CTL        = UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN;
+
+  /* USB PB1(VBUS) PL6,7(DP,DM) */
+  SYSCTL->RCGCGPIO |= (1u << 1) | (1u << 10);
+  while (((1u << 1) | (1u << 10)) != (SYSCTL->PRGPIO & ((1u << 1) | (1u << 10)))) ;
+  GPIOB->AMSEL      = 1u << 1;
+  GPIOL->AMSEL      = (1u << 6) | (1u << 7);
+
+  SYSCTL->RCGCUSB   = 1u; /* Open the clock gate for SYSCLK */
+  while (!(SYSCTL->PRUSB & (1u << 0))) ;
+  USB0->CC          = USB_CC_CLKEN | (3u << USB_CC_CLKDIV_S); /* 60MHz = 240MHz / 4 */
+  __DMB(); /* Wait for completion of opening of the clock gate */
+
+  SYSCTL->SRUSB     = 1u;
+  for (int i = 0; i < 16; ++i) __NOP();
+  SYSCTL->SRUSB     = 0u;
+
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  if (state)
+    GPION->DATA |= 2u;
+  else
+    GPION->DATA &= ~2u;
+}
+
+uint32_t board_button_read(void)
+{
+  return (GPIOJ->DATA & 1u) ? 0u : 1u;
+}
+
+int board_uart_read(uint8_t * buf, int len)
+{
+  for (int i = 0; i < len; ++i) {
+    while (UART0->FR & UART_FR_RXFE) ;
+    *buf++ = UART0->DR;
+  }
+  return len;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  uint8_t const *p = (uint8_t const *)buf;
+  for (int i = 0; i < len; ++i) {
+    while (UART0->FR & UART_FR_TXFF) ;
+    UART0->DR = *p++;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0u;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
new file mode 100644
index 000000000..d0ea13456
--- /dev/null
+++ b/hw/bsp/msp432e4/family.mk
@@ -0,0 +1,48 @@
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/ti
+
+CFLAGS += \
+	-flto \
+	-mthumb \
+	-mslow-flash-data \
+	-mabi=aapcs \
+	-mcpu=cortex-m4 \
+	-mfloat-abi=hard \
+	-mfpu=fpv4-sp-d16 \
+	-D__MSP432E401Y__ \
+	-DCFG_TUSB_MCU=OPT_MCU_MSP432E4xx
+
+# All source paths should be relative to the top level.
+LD_FILE = hw/mcu/ti/msp432e4/Source/msp432e401y.ld
+LDINC += $(TOP)/hw/mcu/ti/msp432e4/Include
+LDFLAGS += $(addprefix -L,$(LDINC))
+
+MCU_DIR = hw/mcu/ti/msp432e4
+
+SRC_C += \
+	src/portable/mentor/dcd_musb.c \
+	$(MCU_DIR)/Source/system_msp432e401y.c
+
+INC += \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(MCU_DIR)/Include \
+	$(TOP)/$(BOARD_PATH)
+
+SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM4F
+
+# export for libmsp430.so to same installation
+ifneq ($(OS),Windows_NT)
+export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher))
+endif
+
+# flash target using TI MSP430-Flasher
+# http://www.ti.com/tool/MSP430-FLASHER
+# Please add its installation dir to PATH
+flash: $(BUILD)/$(PROJECT).hex
+	MSP430Flasher -w $< -z [VCC]
+
+# flash target using mspdebug.
+flash-mspdebug: $(BUILD)/$(PROJECT).elf
+	$(MSPDEBUG) tilib "prog $<" --allow-fw-update
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 15d8ce204..1befa89b6 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -143,7 +143,7 @@
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- TI -------------//
-#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx)
+#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx, OPT_MCU_MSP432E4xx)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 //------------- ValentyUSB -------------//
diff --git a/src/tusb_option.h b/src/tusb_option.h
index e33d5a057..aaf4f3657 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -86,6 +86,7 @@
 
 // TI MSP430
 #define OPT_MCU_MSP430x5xx        500 ///< TI MSP430x5xx
+#define OPT_MCU_MSP432E4xx        510 ///< TI MSP432E4xx
 
 // ValentyUSB eptri
 #define OPT_MCU_VALENTYUSB_EPTRI  600 ///< Fomu eptri config

From 50ca0dda2ca4fe32f681f2955c9ec39355e3082e Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 30 Oct 2021 23:41:23 +0900
Subject: [PATCH 0650/2085] Add dcd_musb.c

---
 hw/bsp/msp432e4/family.c            |   2 +
 hw/bsp/msp432e4/family.mk           |  17 +-
 src/portable/mentor/musb/dcd_musb.c | 836 ++++++++++++++++++++++++++++
 3 files changed, 845 insertions(+), 10 deletions(-)
 create mode 100644 src/portable/mentor/musb/dcd_musb.c

diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index 3bb36042d..567d5dc93 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -122,6 +122,8 @@ void board_init(void)
   for (int i = 0; i < 16; ++i) __NOP();
   SYSCTL->SRUSB     = 0u;
 
+  USB0->CC          = USB_CC_CLKEN | (3u << USB_CC_CLKDIV_S); /* 60MHz = 240MHz / 4 */
+  __DMB(); /* Wait for completion of opening of the clock gate */
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
index d0ea13456..aad5c77e8 100644
--- a/hw/bsp/msp432e4/family.mk
+++ b/hw/bsp/msp432e4/family.mk
@@ -11,6 +11,9 @@ CFLAGS += \
 	-D__MSP432E401Y__ \
 	-DCFG_TUSB_MCU=OPT_MCU_MSP432E4xx
 
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=cast-qual -Wno-error=format=
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/mcu/ti/msp432e4/Source/msp432e401y.ld
 LDINC += $(TOP)/hw/mcu/ti/msp432e4/Include
@@ -19,7 +22,7 @@ LDFLAGS += $(addprefix -L,$(LDINC))
 MCU_DIR = hw/mcu/ti/msp432e4
 
 SRC_C += \
-	src/portable/mentor/dcd_musb.c \
+	src/portable/mentor/musb/dcd_musb.c \
 	$(MCU_DIR)/Source/system_msp432e401y.c
 
 INC += \
@@ -37,12 +40,6 @@ ifneq ($(OS),Windows_NT)
 export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher))
 endif
 
-# flash target using TI MSP430-Flasher
-# http://www.ti.com/tool/MSP430-FLASHER
-# Please add its installation dir to PATH
-flash: $(BUILD)/$(PROJECT).hex
-	MSP430Flasher -w $< -z [VCC]
-
-# flash target using mspdebug.
-flash-mspdebug: $(BUILD)/$(PROJECT).elf
-	$(MSPDEBUG) tilib "prog $<" --allow-fw-update
+# For flash-jlink target
+JLINK_DEVICE = MSP432E401Y
+JLINK_IF     = SWD
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
new file mode 100644
index 000000000..f073cd93f
--- /dev/null
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -0,0 +1,836 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Koji KITAYAMA
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_MSP432E4xx
+
+#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
+/* GCC warns that an address may be unaligned, even though
+ * the target CPU has the capability for unaligned memory access. */
+_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
+#endif
+
+#include "device/dcd.h"
+#include "msp.h"
+
+/*------------------------------------------------------------------
+ * MACRO TYPEDEF CONSTANT ENUM DECLARATION
+ *------------------------------------------------------------------*/
+#define REQUEST_TYPE_INVALID  (0xFFu)
+
+typedef struct {
+  uint_fast16_t beg; /* offset of including first element */
+  uint_fast16_t end; /* offset of excluding the last element */
+} free_block_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint16_t TXMAXP;
+  uint8_t  TXCSRL;
+  uint8_t  TXCSRH;
+  uint16_t RXMAXP;
+  uint8_t  RXCSRL;
+  uint8_t  RXCSRH;
+  uint16_t RXCOUNT;
+  uint16_t RESERVED[3];
+} hw_endpoint_t;
+
+typedef union {
+  uint8_t   u8;
+  uint16_t  u16;
+  uint32_t  u32;
+} hw_fifo_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  void      *buf;      /* the start address of a transfer data buffer */
+  uint16_t  length;    /* the number of bytes in the buffer */
+  uint16_t  remaining; /* the number of bytes remaining in the buffer */
+} pipe_state_t;
+
+typedef struct
+{
+  tusb_control_request_t setup_packet;
+  uint16_t     remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
+  int8_t       status_out;
+  pipe_state_t pipe0;
+  pipe_state_t pipe[2][7];
+} dcd_data_t;
+
+/*------------------------------------------------------------------
+ * INTERNAL OBJECT & FUNCTION DECLARATION
+ *------------------------------------------------------------------*/
+static dcd_data_t _dcd;
+
+
+static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr)
+{
+  free_block_t *cur = beg;
+  for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ;
+  return cur;
+}
+
+static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size)
+{
+  free_block_t *p = find_containing_block(blks, blks + num, addr);
+  TU_ASSERT(p != blks + num, -2);
+  if (p->beg == addr) {
+    /* Shrink block */
+    p->beg = addr + size;
+    if (p->beg != p->end) return 0;
+    /* remove block */
+    free_block_t *end = blks + num;
+    while (p + 1 < end) {
+      *p = *(p + 1);
+      ++p;
+    }
+    return -1;
+  } else {
+    /* Split into 2 blocks */
+    free_block_t tmp = {
+      .beg = addr + size,
+      .end = p->end
+    };
+    p->end = addr;
+    if (p->beg == p->end) {
+      if (tmp.beg != tmp.end) {
+        *p = tmp;
+        return 0;
+      }
+      /* remove block */
+      free_block_t *end = blks + num;
+      while (p + 1 < end) {
+        *p = *(p + 1);
+        ++p;
+      }
+      return -1;
+    }
+    if (tmp.beg == tmp.end) return 0;
+    blks[num] = tmp;
+    return 1;
+  }
+}
+
+static inline unsigned free_block_size(free_block_t const *blk)
+{
+  return blk->end - blk->beg;
+}
+
+#if 0
+static inline void print_block_list(free_block_t const *blk, unsigned num)
+{
+  TU_LOG1("*************\n");
+  for (unsigned i = 0; i < num; ++i) {
+    TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end);
+    ++blk;
+  }
+}
+#else
+#define print_block_list(a,b)
+#endif
+
+static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
+{
+  free_block_t free_blocks[2 * (DCD_ATTR_ENDPOINT_MAX - 1)];
+  unsigned num_blocks = 1;
+
+  /* Initialize free memory block list */
+  free_blocks[0].beg = 64 / 8;
+  free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */
+  for (int i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
+    uint_fast16_t addr;
+    int num;
+    USB0->EPIDX = i;
+    addr = USB0->TXFIFOADD;
+    if (addr) {
+      unsigned sz  = USB0->TXFIFOSZ;
+      unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0);
+      num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
+      TU_ASSERT(-2 < num, 0);
+      num_blocks += num;
+      print_block_list(free_blocks, num_blocks);
+    }
+    addr = USB0->RXFIFOADD;
+    if (addr) {
+      unsigned sz  = USB0->RXFIFOSZ;
+      unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0);
+      num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
+      TU_ASSERT(-2 < num, 0);
+      num_blocks += num;
+      print_block_list(free_blocks, num_blocks);
+    }
+  }
+  print_block_list(free_blocks, num_blocks);
+
+  /* Find the best fit memory block */
+  uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3;
+  free_block_t const *min = NULL;
+  uint_fast16_t    min_sz = 0xFFFFu;
+  free_block_t const *end = &free_blocks[num_blocks];
+  for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) {
+    uint_fast16_t sz = free_block_size(cur);
+    if (sz < size_in_8byte_unit) continue;
+    if (size_in_8byte_unit == sz) return cur->beg;
+    if (sz < min_sz) min = cur;
+  }
+  TU_ASSERT(min, 0);
+  return min->beg;
+}
+
+static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1)
+{
+  volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1);
+  return regs + epnum_minus1;
+}
+
+static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
+{
+  volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
+  uintptr_t addr = (uintptr_t)buf;
+  while (len >= 4) {
+    reg->u32 = *(uint32_t const *)addr;
+    addr += 4;
+    len  -= 4;
+  }
+  if (len >= 2) {
+    reg->u16 = *(uint16_t const *)addr;
+    addr += 2;
+    len  -= 2;
+  }
+  if (len) {
+    reg->u8 = *(uint8_t const *)addr;
+  }
+}
+
+static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
+{
+  volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
+  uintptr_t addr = (uintptr_t)buf;
+  while (len >= 4) {
+    *(uint32_t *)addr = reg->u32;
+    addr += 4;
+    len  -= 4;
+  }
+  if (len >= 2) {
+    *(uint32_t *)addr = reg->u16;
+    addr += 2;
+    len  -= 2;
+  }
+  if (len) {
+    *(uint32_t *)addr = reg->u8;
+  }
+}
+
+static void process_setup_packet(uint8_t rhport)
+{
+  uint32_t *p = (void*)&_dcd.setup_packet;
+  p[0]        = USB0->FIFO0_WORD;
+  p[1]        = USB0->FIFO0_WORD;
+
+  _dcd.pipe0.buf       = NULL;
+  _dcd.pipe0.length    = 0;
+  _dcd.pipe0.remaining = 0;
+  dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true);
+
+  const unsigned len    = _dcd.setup_packet.wLength;
+  _dcd.remaining_ctrl   = len;
+  const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType);
+  /* Clear RX FIFO and reverse the transaction direction */
+  if (len && dir_in) USB0->CSRL0 = USB_CSRL0_RXRDYC;
+}
+
+static bool handle_xfer_in(uint_fast8_t ep_addr)
+{
+  unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+  pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
+  const unsigned rem  = pipe->remaining;
+
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+
+  volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
+  const unsigned mps = regs->TXMAXP;
+  const unsigned len = TU_MIN(mps, rem);
+  void          *buf = pipe->buf;
+  // TU_LOG1("   %p mps %d len %d rem %d\n", buf, mps, len, rem);
+  if (len) {
+    pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
+    pipe->buf       = buf + len;
+    pipe->remaining = rem - len;
+  }
+  regs->TXCSRL = USB_TXCSRL1_TXRDY;
+  // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
+  return false;
+}
+
+static bool handle_xfer_out(uint_fast8_t ep_addr)
+{
+  unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+  pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
+  volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
+  // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL);
+
+  TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY);
+
+  const unsigned mps = regs->RXMAXP;
+  const unsigned rem = pipe->remaining;
+  const unsigned vld = regs->RXCOUNT;
+  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
+  void          *buf = pipe->buf;
+  if (len) {
+    pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
+    pipe->buf       = buf + len;
+    pipe->remaining = rem - len;
+  }
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return NULL != buf;
+  }
+  regs->RXCSRL = 0; /* Clear RXRDY bit */
+  return false;
+}
+
+static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+
+  unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+  unsigned dir_in       = tu_edpt_dir(ep_addr);
+
+  pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1];
+  pipe->buf          = buffer;
+  pipe->length       = total_bytes;
+  pipe->remaining    = total_bytes;
+
+  if (dir_in) {
+    handle_xfer_in(ep_addr);
+  } else {
+    volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
+    if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = 0;
+  }
+  return true;
+}
+
+static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+  TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */
+
+  const unsigned req = _dcd.setup_packet.bmRequestType;
+  TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0);
+
+  if (req == REQUEST_TYPE_INVALID || _dcd.status_out) {
+    /* STATUS OUT stage.
+     * MUSB controller automatically handles STATUS OUT packets without
+     * software helps. We do not have to do anything. And STATUS stage
+     * may have already finished and received the next setup packet
+     * without calling this function, so we have no choice but to
+     * invoke the callback function of status packet here. */
+    // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\n", USB0->CSRL0);
+    _dcd.status_out = 0;
+    if (req == REQUEST_TYPE_INVALID) {
+      dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
+    } else {
+      /* The next setup packet has already been received, it aborts
+       * invoking callback function to avoid confusing TUSB stack. */
+      TU_LOG1("Drop CONTROL_STAGE_ACK\n");
+    }
+    return true;
+  }
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+  if (tu_edpt_dir(req) == dir_in) { /* DATA stage */
+    TU_ASSERT(total_bytes <= _dcd.remaining_ctrl);
+    const unsigned rem = _dcd.remaining_ctrl;
+    const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes);
+    if (dir_in) {
+      pipe_write_packet(buffer, &USB0->FIFO0_WORD, len);
+
+      _dcd.pipe0.buf       = buffer + len;
+      _dcd.pipe0.length    = len;
+      _dcd.pipe0.remaining = 0;
+
+      _dcd.remaining_ctrl  = rem - len;
+      if ((len < 64) || (rem == len)) {
+        _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */
+        _dcd.status_out = 1;
+        /* Flush TX FIFO and reverse the transaction direction. */
+        USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND;
+      } else {
+        USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */
+      }
+      // TU_LOG1(" IN USB0->CSRL0 = %x\n", USB0->CSRL0);
+    } else {
+      // TU_LOG1(" OUT USB0->CSRL0 = %x\n", USB0->CSRL0);
+      _dcd.pipe0.buf       = buffer;
+      _dcd.pipe0.length    = len;
+      _dcd.pipe0.remaining = len;
+      USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */
+    }
+  } else if (dir_in) {
+    // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\n", USB0->CSRL0);
+    _dcd.pipe0.buf = NULL;
+    _dcd.pipe0.length    = 0;
+    _dcd.pipe0.remaining = 0;
+    /* Clear RX FIFO and reverse the transaction direction */
+    USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
+  }
+  return true;
+}
+
+static void process_ep0(uint8_t rhport)
+{
+  uint_fast8_t csrl = USB0->CSRL0;
+
+  // TU_LOG1(" EP0 USB0->CSRL0 = %x\n", csrl);
+
+  if (csrl & USB_CSRL0_STALLED) {
+    /* Returned STALL packet to HOST. */
+    USB0->CSRL0 = 0; /* Clear STALL */
+    return;
+  }
+
+  unsigned req = _dcd.setup_packet.bmRequestType;
+  if (csrl & USB_CSRL0_SETEND) {
+    TU_LOG1("   ABORT by the next packets\n");
+    USB0->CSRL0 = USB_CSRL0_SETENDC;
+    if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
+      /* DATA stage was aborted by receiving STATUS or SETUP packet. */
+      _dcd.pipe0.buf = NULL;
+      _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+      dcd_event_xfer_complete(rhport,
+                              req & TUSB_DIR_IN_MASK,
+                              _dcd.pipe0.length - _dcd.pipe0.remaining,
+                              XFER_RESULT_SUCCESS, true);
+    }
+    req = REQUEST_TYPE_INVALID;
+    if (!(csrl & USB_CSRL0_RXRDY)) return; /* Received SETUP packet */
+  }
+
+  if (csrl & USB_CSRL0_RXRDY) {
+    /* Received SETUP or DATA OUT packet */
+    if (req == REQUEST_TYPE_INVALID) {
+      /* SETUP */
+      TU_ASSERT(sizeof(tusb_control_request_t) == USB0->COUNT0,);
+      process_setup_packet(rhport);
+      return;
+    }
+    if (_dcd.pipe0.buf) {
+      /* DATA OUT */
+      const unsigned vld = USB0->COUNT0;
+      const unsigned rem = _dcd.pipe0.remaining;
+      const unsigned len = TU_MIN(TU_MIN(rem, 64), vld);
+      pipe_read_packet(_dcd.pipe0.buf, &USB0->FIFO0_WORD, len);
+
+      _dcd.pipe0.remaining = rem - len;
+      _dcd.remaining_ctrl -= len;
+
+      _dcd.pipe0.buf = NULL;
+      dcd_event_xfer_complete(rhport,
+                              tu_edpt_addr(0, TUSB_DIR_OUT),
+                              _dcd.pipe0.length - _dcd.pipe0.remaining,
+                              XFER_RESULT_SUCCESS, true);
+    }
+    return;
+  }
+
+  /* When CSRL0 is zero, it means that completion of sending a any length packet
+   * or receiving a zero length packet. */
+  if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) {
+    /* STATUS IN */
+    if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) {
+      /* The address must be changed on completion of the control transfer. */
+      USB0->FADDR = (uint8_t)_dcd.setup_packet.wValue;
+    }
+    _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+    dcd_event_xfer_complete(rhport,
+                            tu_edpt_addr(0, TUSB_DIR_IN),
+                            _dcd.pipe0.length - _dcd.pipe0.remaining,
+                            XFER_RESULT_SUCCESS, true);
+    return;
+  }
+  if (_dcd.pipe0.buf) {
+    /* DATA IN */
+    _dcd.pipe0.buf = NULL;
+    dcd_event_xfer_complete(rhport,
+                            tu_edpt_addr(0, TUSB_DIR_IN),
+                            _dcd.pipe0.length - _dcd.pipe0.remaining,
+                            XFER_RESULT_SUCCESS, true);
+  }
+}
+
+static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
+{
+  bool completed;
+  const unsigned dir_in     = tu_edpt_dir(ep_addr);
+  const unsigned epn_minus1 = tu_edpt_number(ep_addr) - 1;
+
+  volatile hw_endpoint_t *regs = edpt_regs(epn_minus1);
+  if (dir_in) {
+    // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL);
+    if (regs->TXCSRL & USB_TXCSRL1_STALLED) {
+      regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN);
+      return;
+    }
+    completed = handle_xfer_in(ep_addr);
+  } else {
+    // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL);
+    if (regs->RXCSRL & USB_RXCSRL1_STALLED) {
+      regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER);
+      return;
+    }
+    completed = handle_xfer_out(ep_addr);
+  }
+
+  if (completed) {
+    pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1];
+    dcd_event_xfer_complete(rhport, ep_addr,
+                            pipe->length - pipe->remaining,
+                            XFER_RESULT_SUCCESS, true);
+  }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+  /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF),
+   * a control transfer state is SETUP or STATUS stage. */
+  _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+  _dcd.status_out = 0;
+  /* When pipe0.buf has not NULL, DATA stage works in progress. */
+  _dcd.pipe0.buf = NULL;
+
+  /* Clear FIFO settings */
+  for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
+    USB0->EPIDX     = i;
+    USB0->TXFIFOSZ  = 0;
+    USB0->TXFIFOADD = 0;
+    USB0->RXFIFOSZ  = 0;
+    USB0->RXFIFOADD = 0;
+  }
+  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+}
+
+/*------------------------------------------------------------------
+ * Device API
+ *------------------------------------------------------------------*/
+
+void dcd_init(uint8_t rhport)
+{
+  (void)rhport;
+  USB0->IE |= USB_IE_SUSPND;
+  NVIC_ClearPendingIRQ(USB0_IRQn);
+
+  dcd_connect(rhport);
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void)rhport;
+  NVIC_EnableIRQ(USB0_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void)rhport;
+  NVIC_DisableIRQ(USB0_IRQn);
+}
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void)rhport;
+  (void)dev_addr;
+  _dcd.pipe0.buf       = NULL;
+  _dcd.pipe0.length    = 0;
+  _dcd.pipe0.remaining = 0;
+  /* Clear RX FIFO to return ACK. */
+  USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND;
+}
+
+// Wake up host
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void)rhport;
+  USB0->POWER |= USB_POWER_RESUME;
+
+  unsigned cnt = SystemCoreClock / 1000;
+  while (cnt--) __NOP();
+
+  USB0->POWER &= ~USB_POWER_RESUME;
+}
+
+// Connect by enabling internal pull-up resistor on D+/D-
+void dcd_connect(uint8_t rhport)
+{
+  (void)rhport;
+  USB0->POWER |= USB_POWER_SOFTCONN;
+}
+
+// Disconnect by disabling internal pull-up resistor on D+/D-
+void dcd_disconnect(uint8_t rhport)
+{
+  (void)rhport;
+  USB0->POWER &= ~USB_POWER_SOFTCONN;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+
+  const unsigned ep_addr = ep_desc->bEndpointAddress;
+  const unsigned epn     = tu_edpt_number(ep_addr);
+  const unsigned dir_in  = tu_edpt_dir(ep_addr);
+  const unsigned xfer    = ep_desc->bmAttributes.xfer;
+  const unsigned mps     = tu_edpt_packet_size(ep_desc);
+
+  TU_ASSERT(epn < DCD_ATTR_ENDPOINT_MAX);
+
+  pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1];
+  pipe->buf       = NULL;
+  pipe->length    = 0;
+  pipe->remaining = 0;
+
+  volatile hw_endpoint_t *regs = edpt_regs(epn - 1);
+  if (dir_in) {
+    regs->TXMAXP = mps;
+    regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0;
+    if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
+      regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
+    else
+      regs->TXCSRL = USB_TXCSRL1_CLRDT;
+  } else {
+    regs->RXMAXP = mps;
+    regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0;
+    if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
+      regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
+    else
+      regs->RXCSRL = USB_RXCSRL1_CLRDT;
+  }
+
+  /* Setup FIFO */
+  int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps));
+  if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3;
+  unsigned addr = find_free_memory(size_in_log2_minus3);
+  TU_ASSERT(addr);
+
+  USB0->EPIDX = epn;
+  if (dir_in) {
+    USB0->TXFIFOADD = addr;
+    USB0->TXFIFOSZ  = size_in_log2_minus3;
+  } else {
+    USB0->RXFIFOADD = addr;
+    USB0->RXFIFOSZ  = size_in_log2_minus3;
+  }
+
+  return true;
+}
+
+void dcd_edpt_close_all(uint8_t rhport)
+{
+  (void) rhport;
+  volatile hw_endpoint_t *regs = (volatile hw_endpoint_t *)(uintptr_t)&USB0->TXMAXP1;
+  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
+    regs->TXMAXP = 0;
+    regs->TXCSRH = 0;
+    if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
+      regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
+    else
+      regs->TXCSRL = USB_TXCSRL1_CLRDT;
+
+    regs->RXMAXP = 0;
+    regs->RXCSRH = 0;
+    if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
+      regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
+    else
+      regs->RXCSRL = USB_RXCSRL1_CLRDT;
+
+    USB0->EPIDX     = i;
+    USB0->TXFIFOSZ  = 0;
+    USB0->TXFIFOADD = 0;
+    USB0->RXFIFOSZ  = 0;
+    USB0->RXFIFOADD = 0;
+  }
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  (void)rhport;
+  unsigned const epn    = tu_edpt_number(ep_addr);
+  unsigned const dir_in = tu_edpt_dir(ep_addr);
+
+  hw_endpoint_t volatile *regs = edpt_regs(epn - 1);
+  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  if (dir_in) {
+    regs->TXMAXP = 0;
+    regs->TXCSRH = 0;
+    if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
+      regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
+    else
+      regs->TXCSRL = USB_TXCSRL1_CLRDT;
+
+    USB0->EPIDX     = epn;
+    USB0->TXFIFOSZ  = 0;
+    USB0->TXFIFOADD = 0;
+  } else {
+    regs->RXMAXP = 0;
+    regs->RXCSRH = 0;
+    if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
+      regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
+    else
+      regs->RXCSRL = USB_RXCSRL1_CLRDT;
+
+    USB0->EPIDX     = epn;
+    USB0->RXFIFOSZ  = 0;
+    USB0->RXFIFOADD = 0;
+  }
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+  bool ret;
+  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+
+  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  if (tu_edpt_number(ep_addr))
+    ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes);
+  else
+    ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  return ret;
+}
+
+// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  (void) rhport;
+  (void) ep_addr;
+  (void) ff;
+  (void) total_bytes;
+  return false;
+}
+
+// Stall endpoint
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void)rhport;
+  unsigned const epn = tu_edpt_number(ep_addr);
+  unsigned const ie  = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  if (0 == epn) {
+    if (!ep_addr) { /* Ignore EP80 */
+      _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+      _dcd.pipe0.buf = NULL;
+      USB0->CSRL0 = USB_CSRL0_STALL;
+    }
+  } else {
+    volatile hw_endpoint_t *regs = edpt_regs(epn - 1);
+    if (tu_edpt_dir(ep_addr)) { /* IN */
+      regs->TXCSRL = USB_TXCSRL1_STALL;
+    } else { /* OUT */
+      TU_ASSERT(!(regs->RXCSRL & USB_RXCSRL1_RXRDY),);
+      regs->RXCSRL = USB_RXCSRL1_STALL;
+    }
+  }
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+}
+
+// clear stall, data toggle is also reset to DATA0
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void)rhport;
+  unsigned const epn = tu_edpt_number(ep_addr);
+  hw_endpoint_t volatile *regs = edpt_regs(epn - 1);
+  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  if (tu_edpt_dir(ep_addr)) { /* IN */
+    regs->TXCSRL = USB_TXCSRL1_CLRDT;
+  } else { /* OUT */
+    regs->RXCSRL = USB_RXCSRL1_CLRDT; 
+  }
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+}
+
+/*-------------------------------------------------------------------
+ * ISR
+ *-------------------------------------------------------------------*/
+void dcd_int_handler(uint8_t rhport)
+{
+  uint_fast8_t is, txis, rxis;
+
+  is   = USB0->IS;   /* read and clear interrupt status */
+  txis = USB0->TXIS; /* read and clear interrupt status */
+  rxis = USB0->RXIS; /* read and clear interrupt status */
+  // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis);
+
+  is &= USB0->IE; /* Clear disabled interrupts */
+  if (is & USB_IS_DISCON) {
+  }
+  if (is & USB_IS_SOF) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+  if (is & USB_IS_RESET) {
+    process_bus_reset(rhport);
+  }
+  if (is & USB_IS_RESUME) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+  }
+  if (is & USB_IS_SUSPEND) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+  }
+
+  txis &= USB0->TXIE; /* Clear disabled interrupts */
+  if (txis & USB_TXIE_EP0) {
+    process_ep0(rhport);
+    txis &= ~TU_BIT(0);
+  }
+  while (txis) {
+    unsigned const num = __builtin_ctz(txis);
+    process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN));
+    txis &= ~TU_BIT(num);
+  }
+  rxis &= USB0->RXIE; /* Clear disabled interrupts */
+  while (rxis) {
+    unsigned const num = __builtin_ctz(rxis);
+    process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT));
+    rxis &= ~TU_BIT(num);
+  }
+}
+
+#endif

From 0b3c8c4a59e993f7f51452b2bd3d0decdc56d6c9 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 4 Nov 2021 22:36:36 +0900
Subject: [PATCH 0651/2085] Implement dcd_edpt_xfer_fifo for dcd_musb

---
 src/class/audio/audio_device.c      |  3 +-
 src/portable/mentor/musb/dcd_musb.c | 66 +++++++++++++++++++++++------
 2 files changed, 55 insertions(+), 14 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 28b1c1a7c..38bfc023b 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -102,7 +102,8 @@
     CFG_TUSB_MCU == OPT_MCU_GD32VF103                             || \
     CFG_TUSB_MCU == OPT_MCU_LPC18XX                               || \
     CFG_TUSB_MCU == OPT_MCU_LPC43XX                               || \
-    CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+    CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX                            || \
+    CFG_TUSB_MCU == OPT_MCU_MSP432E4xx
 #if TUD_AUDIO_PREFER_RING_BUFFER
 #define  USE_LINEAR_BUFFER     0
 #else
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index f073cd93f..5a5aa51bc 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -77,7 +77,8 @@ typedef struct
   uint16_t     remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
   int8_t       status_out;
   pipe_state_t pipe0;
-  pipe_state_t pipe[2][7];
+  pipe_state_t pipe[2][7];   /* pipe[direction][endpoint number - 1] */
+  uint16_t     pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */
 } dcd_data_t;
 
 /*------------------------------------------------------------------
@@ -244,6 +245,30 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
   }
 }
 
+static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir)
+{
+  static const struct {
+    void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
+    void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n);
+    void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len);
+  } ops[] = {
+    /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet},
+    /* IN  */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet},
+  };
+  tu_fifo_buffer_info_t info;
+  ops[dir].tu_fifo_get_info(f, &info);
+  unsigned total_len = len;
+  len = TU_MIN(total_len, info.len_lin);
+  ops[dir].pipe_read_write(info.ptr_lin, fifo, len);
+  unsigned rem = total_len - len;
+  if (rem) {
+    len = TU_MIN(rem, info.len_wrap);
+    ops[dir].pipe_read_write(info.ptr_wrap, fifo, len);
+    rem -= len;
+  }
+  ops[dir].tu_fifo_advance(f, total_len - rem);
+}
+
 static void process_setup_packet(uint8_t rhport)
 {
   uint32_t *p = (void*)&_dcd.setup_packet;
@@ -279,8 +304,12 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
   void          *buf = pipe->buf;
   // TU_LOG1("   %p mps %d len %d rem %d\n", buf, mps, len, rem);
   if (len) {
-    pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
-    pipe->buf       = buf + len;
+    if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
+      pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_IN);
+    } else {
+      pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
+      pipe->buf       = buf + len;
+    }
     pipe->remaining = rem - len;
   }
   regs->TXCSRL = USB_TXCSRL1_TXRDY;
@@ -303,8 +332,12 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
-    pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
-    pipe->buf       = buf + len;
+    if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) {
+      pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_OUT);
+    } else {
+      pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len);
+      pipe->buf       = buf + len;
+    }
     pipe->remaining = rem - len;
   }
   if ((len < mps) || (rem == len)) {
@@ -725,12 +758,13 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
   (void)rhport;
   bool ret;
   // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
-
+  unsigned const epnum = tu_edpt_number(ep_addr);
   unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
-  if (tu_edpt_number(ep_addr))
+  if (epnum) {
+    _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1);
     ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes);
-  else
+  } else
     ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
   return ret;
@@ -739,11 +773,17 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
 bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
 {
-  (void) rhport;
-  (void) ep_addr;
-  (void) ff;
-  (void) total_bytes;
-  return false;
+  (void)rhport;
+  bool ret;
+  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  unsigned const epnum = tu_edpt_number(ep_addr);
+  TU_ASSERT(epnum);
+  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1);
+  ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes);
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  return ret;
 }
 
 // Stall endpoint

From e4520e7aa7a0a585d79b8a345525a67cf2f39ef6 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Fri, 5 Nov 2021 20:14:59 +0900
Subject: [PATCH 0652/2085] Add statements for FreeRTOS

---
 hw/bsp/board_mcu.h       | 3 +++
 hw/bsp/msp432e4/family.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 1e2577de0..ea2f23fe9 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -98,6 +98,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_MSP430x5xx
   #include "msp430.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4xx
+  #include "msp.h"
+
 #elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI
   // no header needed
 
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index 567d5dc93..b20af563b 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -77,6 +77,9 @@ void board_init(void)
   SystemCoreClockUpdate();
 #if CFG_TUSB_OS == OPT_OS_NONE
   SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
   /* USR_LED1 PN1 */

From 23ef8b2c64aea2217254b34a8b34cf7cc6d4e364 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 6 Nov 2021 19:32:15 +0900
Subject: [PATCH 0653/2085] Change the variables for a switch and a LED to
 symbols defined by the macros

---
 .../msp432e4/boards/msp_exp432e401y/board.h   | 12 ++++-----
 hw/bsp/msp432e4/family.c                      | 27 +++++++++----------
 2 files changed, 18 insertions(+), 21 deletions(-)

diff --git a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
index b449f3ca4..3130d663b 100644
--- a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
+++ b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h
@@ -27,13 +27,13 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-#define LED_PORT              P1OUT
-#define LED_PIN               BIT0
-#define LED_STATE_ON          1
+#define CLK_LED               12u
+#define GPIO_LED              GPION
+#define GPIO_LED_PIN          1u
 
-#define BUTTON_PORT           P1IN
-#define BUTTON_PIN            BIT1
-#define BUTTON_STATE_ACTIVE   0
+#define CLK_BUTTON            8u
+#define GPIO_BUTTON           GPIOJ
+#define GPIO_BUTTON_PIN       0u
 
 #ifdef __cplusplus
  extern "C" {
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index b20af563b..7114da693 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -28,9 +28,6 @@
 #include "board.h"
 #include "msp.h"
 
-/* Frequency of the external crystal oscillator */
-#define XTAL_FREQUENCY   25000000UL
-
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -82,17 +79,17 @@ void board_init(void)
   NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
-  /* USR_LED1 PN1 */
-  SYSCTL->RCGCGPIO |= 1u << 12;
-  while (!(SYSCTL->PRGPIO & (1u << 12))) ;
-  GPION->DIR        = 2u;
-  GPION->DEN        = 2u;
+  /* USR_LED1 ON1 */
+  SYSCTL->RCGCGPIO |= TU_BIT(CLK_LED);
+  while (!(SYSCTL->PRGPIO & TU_BIT(CLK_LED))) ;
+  GPIO_LED->DIR     = TU_BIT(GPIO_LED_PIN);
+  GPIO_LED->DEN     = TU_BIT(GPIO_LED_PIN);
 
   /* USR_SW1 PJ0 */
-  SYSCTL->RCGCGPIO |= 1u << 8;
-  while (!(SYSCTL->PRGPIO & (1u << 8))) ;
-  GPIOJ->PUR        = 1u;
-  GPIOJ->DEN        = 1u;
+  SYSCTL->RCGCGPIO |= TU_BIT(CLK_BUTTON);
+  while (!(SYSCTL->PRGPIO & TU_BIT(CLK_BUTTON))) ;
+  GPIO_BUTTON->PUR  = TU_BIT(GPIO_BUTTON_PIN);
+  GPIO_BUTTON->DEN  = TU_BIT(GPIO_BUTTON_PIN);
 
   /* UART PA0,1 */
   SYSCTL->RCGCGPIO |= 1u << 0;
@@ -136,14 +133,14 @@ void board_init(void)
 void board_led_write(bool state)
 {
   if (state)
-    GPION->DATA |= 2u;
+    GPIO_LED->DATA |= TU_BIT(GPIO_LED_PIN);
   else
-    GPION->DATA &= ~2u;
+    GPIO_LED->DATA &= ~TU_BIT(GPIO_LED_PIN);
 }
 
 uint32_t board_button_read(void)
 {
-  return (GPIOJ->DATA & 1u) ? 0u : 1u;
+  return (GPIO_BUTTON->DATA & TU_BIT(GPIO_BUTTON_PIN)) ? 0u : 1u;
 }
 
 int board_uart_read(uint8_t * buf, int len)

From 30d3bf8bec430c235bd0948687613455db8ff3b9 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 6 Nov 2021 23:05:27 +0900
Subject: [PATCH 0654/2085] Update TI driver

---
 hw/mcu/ti | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/ti b/hw/mcu/ti
index ed52d354c..143ed6cc2 160000
--- a/hw/mcu/ti
+++ b/hw/mcu/ti
@@ -1 +1 @@
-Subproject commit ed52d354c99e25a5e9db2376eb5e7058c81c3ebd
+Subproject commit 143ed6cc20a7615d042b03b21e070197d473e6e5

From dd7eb368305ebf3c7e374341e037f1af22ce9e05 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 6 Nov 2021 23:10:11 +0900
Subject: [PATCH 0655/2085] Remove unnecessary lines

---
 hw/bsp/msp432e4/family.mk | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
index aad5c77e8..ee7faa208 100644
--- a/hw/bsp/msp432e4/family.mk
+++ b/hw/bsp/msp432e4/family.mk
@@ -35,11 +35,6 @@ SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
-# export for libmsp430.so to same installation
-ifneq ($(OS),Windows_NT)
-export LD_LIBRARY_PATH=$(dir $(shell which MSP430Flasher))
-endif
-
 # For flash-jlink target
 JLINK_DEVICE = MSP432E401Y
 JLINK_IF     = SWD

From 26461d1efe956f5d23c58546364c6bdbffc246df Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 7 Nov 2021 18:25:11 +0900
Subject: [PATCH 0656/2085] Fix DCD_EVENT_XFER_COMPLETE was signaled, even
 after EP is closed

---
 src/portable/mentor/musb/dcd_musb.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 5a5aa51bc..04139dd78 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -556,6 +556,9 @@ static void process_bus_reset(uint8_t rhport)
   /* When pipe0.buf has not NULL, DATA stage works in progress. */
   _dcd.pipe0.buf = NULL;
 
+  USB0->TXIE = 1; /* Enable only EP0 */
+  USB0->RXIE = 0; 
+
   /* Clear FIFO settings */
   for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
     USB0->EPIDX     = i;
@@ -660,6 +663,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
       regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
     else
       regs->TXCSRL = USB_TXCSRL1_CLRDT;
+    USB0->TXIE |= TU_BIT(epn);
   } else {
     regs->RXMAXP = mps;
     regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0;
@@ -667,6 +671,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
       regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
     else
       regs->RXCSRL = USB_RXCSRL1_CLRDT;
+    USB0->RXIE |= TU_BIT(epn);
   }
 
   /* Setup FIFO */
@@ -693,6 +698,8 @@ void dcd_edpt_close_all(uint8_t rhport)
   volatile hw_endpoint_t *regs = (volatile hw_endpoint_t *)(uintptr_t)&USB0->TXMAXP1;
   unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
+  USB0->TXIE = 1; /* Enable only EP0 */
+  USB0->RXIE = 0; 
   for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
     regs->TXMAXP = 0;
     regs->TXCSRH = 0;
@@ -727,6 +734,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
   if (dir_in) {
+    USB0->TXIE  &= ~TU_BIT(epn);
     regs->TXMAXP = 0;
     regs->TXCSRH = 0;
     if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
@@ -738,6 +746,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
     USB0->TXFIFOSZ  = 0;
     USB0->TXFIFOADD = 0;
   } else {
+    USB0->RXIE  &= ~TU_BIT(epn);
     regs->RXMAXP = 0;
     regs->RXCSRH = 0;
     if (regs->RXCSRL & USB_RXCSRL1_RXRDY)

From 23e6e0ef335fac28dc7731a62cca05f838a78caa Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 7 Nov 2021 13:41:32 +0700
Subject: [PATCH 0657/2085] merge pull request 670 for tm4c123gxl bsp

---
 hw/bsp/board_mcu.h                |   3 +
 hw/bsp/ek-tm4c123gxl/board.mk     |  50 +++++++++
 hw/bsp/ek-tm4c123gxl/tm4c123.ld   |  65 ++++++++++++
 hw/bsp/ek-tm4c123gxl/tm4c123gxl.c | 163 ++++++++++++++++++++++++++++++
 src/tusb_option.h                 |   1 +
 5 files changed, 282 insertions(+)
 create mode 100644 hw/bsp/ek-tm4c123gxl/board.mk
 create mode 100644 hw/bsp/ek-tm4c123gxl/tm4c123.ld
 create mode 100644 hw/bsp/ek-tm4c123gxl/tm4c123gxl.c

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index ea2f23fe9..2928ea657 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -143,6 +143,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_XMC4000
   #include "xmc_device.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_TM4C123
+  #include "TM4C123.h"
+
 #else
   #error "Missing MCU header"
 #endif
diff --git a/hw/bsp/ek-tm4c123gxl/board.mk b/hw/bsp/ek-tm4c123gxl/board.mk
new file mode 100644
index 000000000..f6522dc2c
--- /dev/null
+++ b/hw/bsp/ek-tm4c123gxl/board.mk
@@ -0,0 +1,50 @@
+
+DEPS_SUBMODULES += hw/mcu/ti
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \
+  -uvectors \
+  -DTM4C123GH6PM
+  
+# lpc_types.h cause following errors
+CFLAGS += -Wno-error=strict-prototypes
+
+MCU_DIR=hw/mcu/ti/tm4c123xx/
+
+CMSIS=$(TOP)/hw/mcu/ti/tm4c123xx/CMSIS/5.7.0/CMSIS/Include
+
+TI_HDR=$(TOP)/hw/mcu/ti/tm4c123xx/Include/TM4C123/
+
+# All source paths should be relative to the top level.
+
+LD_FILE = hw/bsp/$(BOARD)/tm4c123.ld
+
+INC += \
+     	$(CMSIS) \
+      $(TI_HDR) \
+      $(TOP)/hw/bsp 
+
+
+SRC_C += \
+         $(MCU_DIR)/Source/system_TM4C123.c \
+         $(MCU_DIR)/Source/GCC/tm4c123_startup.c 
+
+# For TinyUSB port source
+VENDOR = ti
+CHIP_FAMILY = tm4c123xx
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM4F
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1769
+
+# flash using jlink
+flash: $(BUILD)/$(PROJECT).elf
+	openocd -f board/ti_ek-tm4c123gxl.cfg  -c "program $< verify reset exit"
diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123.ld b/hw/bsp/ek-tm4c123gxl/tm4c123.ld
new file mode 100644
index 000000000..e2720a9ac
--- /dev/null
+++ b/hw/bsp/ek-tm4c123gxl/tm4c123.ld
@@ -0,0 +1,65 @@
+ENTRY(Reset_Handler)
+
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0;      /* required amount of heap  */
+_Min_Stack_Size = 0x1000; /* required amount of stack */
+
+
+MEMORY 
+{
+    FLASH(rx) : ORIGIN = 0x00000000, LENGTH = 256K
+    SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+SECTIONS 
+{
+    .text : 
+    {
+        . = ALIGN(4) ;
+        *(.vectors) 
+        *(.text) 
+        *(.text.*)
+        *(.init)
+        *(.fini)
+        *(.rodata)
+        *(.rodata.*)
+        . = ALIGN(4) ; 
+        __end_text = . ; 
+    } >FLASH
+    
+    .data : AT(ADDR(.text) + SIZEOF(.text))
+    {
+        . = ALIGN(4);
+        __start_data = . ; 
+        __la_data = LOADADDR(.data);
+        *(.data) 
+        *(.data.*)
+        . = ALIGN(4);
+        __end_data = . ; 
+
+    } >SRAM
+
+    .bss :
+    {
+        . = ALIGN(4) ;
+        __start_bss = . ;
+        __bss_start__ = __start_bss;
+        *(.bss)
+        *(.bss.*)
+        *(.COMMON) 
+        __end_bss = . ;
+        . = ALIGN(4);
+    }>SRAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >SRAM
+}
diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c
new file mode 100644
index 000000000..d78b0f7e3
--- /dev/null
+++ b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c
@@ -0,0 +1,163 @@
+#include <TM4C123.h>
+#include <board.h>
+
+#define BOARD_UART            UART0
+#define BOARD_UART_PORT       GPIOA
+#define BOARD_BTN_PORT        GPIOF
+#define BOARD_BTN             4
+#define BOARD_BTN_Msk         (1u<<4)
+#define LED_PORT              GPIOF
+#define LED_PIN_RED           1
+#define LED_PIN_BLUE          2
+#define LED_PIN_GREEN         3
+#define LED_STATE_ON          1
+
+static void board_uart_init(void)
+{
+    SYSCTL->RCGCUART |= (1<<0);                		   // Enable the clock to UART0
+  	SYSCTL->RCGCGPIO |= (1<<0);                       // Enable the clock to GPIOA
+
+  	GPIOA->AFSEL |= (1<<1)|(1<<0);                          // Enable the alternate function on pin PA0 & PA1
+  	GPIOA->PCTL |= (1<<0)|(1<<4);                          // Configure the GPIOPCTL register to select UART0 in PA0 and PA1
+  	GPIOA->DEN |= (1<<0)|(1<<1);                          // Enable the digital functionality in PA0 and PA1
+
+	/** BAUDRATE = 9600 bits per second, refer manual for calculation **/
+
+  	UART0->CTL &= ~(1<<0);                             // Disable UART0 by clearing UARTEN bit in the UARTCTL register
+  	UART0->IBRD = 325;                                // Write the integer portion of the BRD to the UARTIRD register
+  	UART0->FBRD = 33;                                // Write the fractional portion of the BRD to the UARTFBRD registerer
+
+  	UART0->LCRH = (0x3<<5);          		        // 8-bit, no parity, 1 stop bit
+  	UART0->CC = 0x0;                               // Configure the UART clock source as system clock
+
+  	UART0->CTL = (1<<0)|(1<<8)|(1<<9);            // UART0 Enable, Transmit Enable, Recieve Enable
+}
+
+static void initialize_board_led(GPIOA_Type* port, uint8_t PinMsk, uint8_t dirmsk)
+{
+    /* Enable PortF Clock */
+    SYSCTL -> RCGCGPIO |= (1<<5) ;
+
+	/* Let the clock stabilize */
+	while(! ((SYSCTL->PRGPIO) & (1<<5)) ) ;
+
+	/* Port Digital Enable */
+	port->DEN |= PinMsk;
+
+	/* Set direction */
+	port->DIR = dirmsk ;
+}
+
+static void board_switch_init(void)
+{
+    GPIOF->DIR &= ~(1<<BOARD_BTN); 
+    GPIOF->PUR |=  (1<<BOARD_BTN); 
+    GPIOF->DEN |=  (1<<BOARD_BTN); 
+}
+
+static void WriteGPIOPin(GPIOA_Type* port, uint8_t PinMsk, bool state)
+{
+    if(state)
+        port->DATA |= PinMsk; 
+    else
+        port->DATA &= ~(PinMsk);
+}
+
+static uint32_t ReadGPIOPin(GPIOA_Type *port, uint8_t pinMsk)
+{
+    return (port -> DATA & pinMsk) ;
+}
+
+void board_init(void)
+{
+    SystemCoreClockUpdate(); 
+ 
+#if CFG_TUSB_OS == OPT_OS_NONE
+    // 1ms tick timer
+    SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+    // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+    NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+    /* Reset USB */ 
+    SYSCTL->SRCR2 |= (1u<<16);
+
+    for (volatile uint8_t i=0; i<20; i++);
+
+    SYSCTL->SRCR2 &= ~(1u<<16);
+
+    /* Open the USB clock gate */
+    SYSCTL->RCGCUSB |= (1<<0);
+
+    /* Power-up USB PLL */
+    SYSCTL->RCC2 &= ~(1u<<14);
+
+    /* USB IO Initialization */
+    SYSCTL->RCGCGPIO |= (1u<<3); 
+    
+    /* Let the clock stabilize */ 
+    while(!(SYSCTL->PRGPIO & (1u<<3))); 
+
+    /* USB IOs to Analog Mode */ 
+    GPIOD->AFSEL &= ~ ( (1u<<4) | (1u<<5) ); 
+    GPIOD->DEN   &= ~ ( (1u<<4) | (1u<<5) ); 
+    GPIOD->AMSEL |=   ( (1u<<4) | (1u<<5) );
+
+    uint8_t leds = (1<<LED_PIN_RED) | (1<<LED_PIN_BLUE) | (1<<LED_PIN_GREEN) ; 
+    uint8_t dirmsk = (1<<LED_PIN_RED) | (1<<LED_PIN_BLUE) | (1<<LED_PIN_GREEN) ; 
+
+    /* Configure GPIO for board LED */
+    initialize_board_led(LED_PORT,leds, dirmsk); 
+
+    /* Configure GPIO for board switch */
+    board_switch_init(); 
+
+    /* Initialize board UART */
+    board_uart_init(); 
+
+}
+
+void board_led_write(bool state)
+{
+    WriteGPIOPin(LED_PORT, (1<<LED_PIN_BLUE), state); 
+}
+
+uint32_t board_button_read(void)
+{
+    return ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk);
+}
+
+int board_uart_write(void const* buf, int len)
+{
+    uint8_t const* data = buf; 
+
+    for(int i=0; i<len; i++)
+    {
+        while((UART0->FR &(1<<5)) != 0);                 // Poll until previous data was shofted out
+        UART0->DR= data[i];                                   // Write UART0 DATA REGISTER 
+    }
+
+    return len;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index aaf4f3657..50a922840 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -87,6 +87,7 @@
 // TI MSP430
 #define OPT_MCU_MSP430x5xx        500 ///< TI MSP430x5xx
 #define OPT_MCU_MSP432E4xx        510 ///< TI MSP432E4xx
+#define OPT_MCU_TM4C123           511 ///< TI Tiva C 123x
 
 // ValentyUSB eptri
 #define OPT_MCU_VALENTYUSB_EPTRI  600 ///< Fomu eptri config

From 91646d039c7dac8e16042c42c2d7197034111aeb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 7 Nov 2021 17:45:16 +0700
Subject: [PATCH 0658/2085] add flash-openocd target. correct ek-tm4c123 button
 state

---
 examples/device/99-tinyusb.rules  |  7 +++++++
 examples/rules.mk                 | 13 ++++++++----
 hw/bsp/ek-tm4c123gxl/board.mk     | 35 +++++++++++--------------------
 hw/bsp/ek-tm4c123gxl/tm4c123gxl.c |  6 +++++-
 4 files changed, 33 insertions(+), 28 deletions(-)

diff --git a/examples/device/99-tinyusb.rules b/examples/device/99-tinyusb.rules
index e6372ed58..d306bada5 100644
--- a/examples/device/99-tinyusb.rules
+++ b/examples/device/99-tinyusb.rules
@@ -12,3 +12,10 @@ ATTRS{idVendor}=="cafe", MODE="0666", GROUP="dialout"
 
 # Rule to blacklist TinyUSB example from being manipulated by ModemManager.
 SUBSYSTEMS=="usb", ATTRS{idVendor}=="cafe", ENV{ID_MM_DEVICE_IGNORE}="1"
+
+# Xplained Pro SamG55 Device
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="2111", MODE="0666", GROUP="users", ENV{ID_MM_DEVICE_IGNORE}="1"
+SUBSYSTEMS=="tty", ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="2111", MODE="0666", GROUP="users", ENV{ID_MM_DEVICE_IGNORE}="1"
+
+# TI Stellaris/Tiva-C Launchpad ICDI
+SUBSYSTEM=="usb", ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00fd", MODE="0666"
diff --git a/examples/rules.mk b/examples/rules.mk
index 92fa4e14d..4cc35cb22 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -158,13 +158,14 @@ endif
 # Flash Targets
 # ---------------------------------------
 
-# Flash binary using Jlink
+# Jlink binary
 ifeq ($(OS),Windows_NT)
   JLINKEXE = JLink.exe
 else
   JLINKEXE = JLinkExe
 endif
 
+# Jlink Interface
 JLINK_IF ?= swd
 
 # Flash using jlink
@@ -177,18 +178,22 @@ flash-jlink: $(BUILD)/$(PROJECT).hex
 	@echo exit >> $(BUILD)/$(BOARD).jlink
 	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
 
-# flash STM32 MCU using stlink with STM32 Cube Programmer CLI
+# Flash STM32 MCU using stlink with STM32 Cube Programmer CLI
 flash-stlink: $(BUILD)/$(PROJECT).elf
 	STM32_Programmer_CLI --connect port=swd --write $< --go
 
-# flash with pyocd
+# Flash using pyocd
 PYOCD_OPTION ?=
 flash-pyocd: $(BUILD)/$(PROJECT).hex
 	pyocd flash -t $(PYOCD_TARGET) $(PYOCD_OPTION) $<
 	pyocd reset -t $(PYOCD_TARGET)
 
-# flash with Black Magic Probe
+# Flash using openocd
+OPENOCD_OPTION ?=
+flash-openocd: $(BUILD)/$(PROJECT).elf
+	openocd $(OPENOCD_OPTION) -c "program $< verify reset exit"
 
+# flash with Black Magic Probe
 # This symlink is created by https://github.com/blacksphere/blackmagic/blob/master/driver/99-blackmagic.rules
 BMP ?= /dev/ttyBmpGdb
 
diff --git a/hw/bsp/ek-tm4c123gxl/board.mk b/hw/bsp/ek-tm4c123gxl/board.mk
index f6522dc2c..368e79f4e 100644
--- a/hw/bsp/ek-tm4c123gxl/board.mk
+++ b/hw/bsp/ek-tm4c123gxl/board.mk
@@ -1,4 +1,3 @@
-
 DEPS_SUBMODULES += hw/mcu/ti
 
 CFLAGS += \
@@ -12,39 +11,29 @@ CFLAGS += \
   -uvectors \
   -DTM4C123GH6PM
   
-# lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
 
 MCU_DIR=hw/mcu/ti/tm4c123xx/
 
-CMSIS=$(TOP)/hw/mcu/ti/tm4c123xx/CMSIS/5.7.0/CMSIS/Include
-
-TI_HDR=$(TOP)/hw/mcu/ti/tm4c123xx/Include/TM4C123/
-
 # All source paths should be relative to the top level.
-
-LD_FILE = hw/bsp/$(BOARD)/tm4c123.ld
+LD_FILE = $(BOARD_PATH)/tm4c123.ld
 
 INC += \
-     	$(CMSIS) \
-      $(TI_HDR) \
-      $(TOP)/hw/bsp 
-
+	$(TOP)/$(MCU_DIR)/CMSIS/5.7.0/CMSIS/Include \
+	$(TOP)/$(MCU_DIR)/Include/TM4C123 \
+	$(TOP)/hw/bsp
 
 SRC_C += \
-         $(MCU_DIR)/Source/system_TM4C123.c \
-         $(MCU_DIR)/Source/GCC/tm4c123_startup.c 
-
-# For TinyUSB port source
-VENDOR = ti
-CHIP_FAMILY = tm4c123xx
+	$(MCU_DIR)/Source/system_TM4C123.c \
+	$(MCU_DIR)/Source/GCC/tm4c123_startup.c
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
 
 # For flash-jlink target
-JLINK_DEVICE = LPC1769
+JLINK_DEVICE = TM4C123GH6PM
 
-# flash using jlink
-flash: $(BUILD)/$(PROJECT).elf
-	openocd -f board/ti_ek-tm4c123gxl.cfg  -c "program $< verify reset exit"
+# flash using openocd
+OPENOCD_OPTION = -f board/ti_ek-tm4c123gxl.cfg
+flash: flash-openocd
diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c
index d78b0f7e3..b370b7577 100644
--- a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c
+++ b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c
@@ -3,9 +3,12 @@
 
 #define BOARD_UART            UART0
 #define BOARD_UART_PORT       GPIOA
+
 #define BOARD_BTN_PORT        GPIOF
 #define BOARD_BTN             4
 #define BOARD_BTN_Msk         (1u<<4)
+#define BUTTON_STATE_ACTIVE   0
+
 #define LED_PORT              GPIOF
 #define LED_PIN_RED           1
 #define LED_PIN_BLUE          2
@@ -125,7 +128,8 @@ void board_led_write(bool state)
 
 uint32_t board_button_read(void)
 {
-    return ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk);
+    uint32_t gpio_value = ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk);
+    return BUTTON_STATE_ACTIVE ? gpio_value : !gpio_value;
 }
 
 int board_uart_write(void const* buf, int len)

From 6fea50f735d00dff23d958eec8cf4a386282c193 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Nov 2021 16:41:08 +0700
Subject: [PATCH 0659/2085] musb work well with tm4c123

---
 hw/bsp/ek-tm4c123gxl/board.mk           |   1 +
 hw/bsp/ek-tm4c123gxl/tm4c123gxl.c       | 183 +++++++++++++-----------
 src/device/dcd_attr.h                   |   5 +-
 src/portable/mentor/musb/dcd_musb.c     |  18 ++-
 src/portable/mentor/musb/musb_msp432e.h |  40 ++++++
 src/portable/mentor/musb/musb_tm4c.h    |  45 ++++++
 src/tusb_option.h                       |   3 +-
 7 files changed, 206 insertions(+), 89 deletions(-)
 create mode 100644 src/portable/mentor/musb/musb_msp432e.h
 create mode 100644 src/portable/mentor/musb/musb_tm4c.h

diff --git a/hw/bsp/ek-tm4c123gxl/board.mk b/hw/bsp/ek-tm4c123gxl/board.mk
index 368e79f4e..9d0d67e1c 100644
--- a/hw/bsp/ek-tm4c123gxl/board.mk
+++ b/hw/bsp/ek-tm4c123gxl/board.mk
@@ -25,6 +25,7 @@ INC += \
 	$(TOP)/hw/bsp
 
 SRC_C += \
+	src/portable/mentor/musb/dcd_musb.c \
 	$(MCU_DIR)/Source/system_TM4C123.c \
 	$(MCU_DIR)/Source/GCC/tm4c123_startup.c
 
diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c
index b370b7577..663fbf127 100644
--- a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c
+++ b/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c
@@ -15,143 +15,156 @@
 #define LED_PIN_GREEN         3
 #define LED_STATE_ON          1
 
-static void board_uart_init(void)
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_Handler(void)
 {
-    SYSCTL->RCGCUART |= (1<<0);                		   // Enable the clock to UART0
-  	SYSCTL->RCGCGPIO |= (1<<0);                       // Enable the clock to GPIOA
-
-  	GPIOA->AFSEL |= (1<<1)|(1<<0);                          // Enable the alternate function on pin PA0 & PA1
-  	GPIOA->PCTL |= (1<<0)|(1<<4);                          // Configure the GPIOPCTL register to select UART0 in PA0 and PA1
-  	GPIOA->DEN |= (1<<0)|(1<<1);                          // Enable the digital functionality in PA0 and PA1
-
-	/** BAUDRATE = 9600 bits per second, refer manual for calculation **/
-
-  	UART0->CTL &= ~(1<<0);                             // Disable UART0 by clearing UARTEN bit in the UARTCTL register
-  	UART0->IBRD = 325;                                // Write the integer portion of the BRD to the UARTIRD register
-  	UART0->FBRD = 33;                                // Write the fractional portion of the BRD to the UARTFBRD registerer
-
-  	UART0->LCRH = (0x3<<5);          		        // 8-bit, no parity, 1 stop bit
-  	UART0->CC = 0x0;                               // Configure the UART clock source as system clock
-
-  	UART0->CTL = (1<<0)|(1<<8)|(1<<9);            // UART0 Enable, Transmit Enable, Recieve Enable
+  tud_int_handler(0);
 }
 
-static void initialize_board_led(GPIOA_Type* port, uint8_t PinMsk, uint8_t dirmsk)
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+static void board_uart_init (void)
 {
-    /* Enable PortF Clock */
-    SYSCTL -> RCGCGPIO |= (1<<5) ;
+  SYSCTL->RCGCUART |= (1 << 0);                // Enable the clock to UART0
+  SYSCTL->RCGCGPIO |= (1 << 0);                // Enable the clock to GPIOA
 
-	/* Let the clock stabilize */
-	while(! ((SYSCTL->PRGPIO) & (1<<5)) ) ;
+  GPIOA->AFSEL |= (1 << 1) | (1 << 0);         // Enable the alternate function on pin PA0 & PA1
+  GPIOA->PCTL |= (1 << 0) | (1 << 4);          // Configure the GPIOPCTL register to select UART0 in PA0 and PA1
+  GPIOA->DEN |= (1 << 0) | (1 << 1);           // Enable the digital functionality in PA0 and PA1
 
-	/* Port Digital Enable */
-	port->DEN |= PinMsk;
+                                               /** BAUDRATE = 9600 bits per second, refer manual for calculation **/
+  UART0->CTL &= ~(1 << 0);                     // Disable UART0 by clearing UARTEN bit in the UARTCTL register
+  UART0->IBRD = 325;                           // Write the integer portion of the BRD to the UARTIRD register
+  UART0->FBRD = 33;                            // Write the fractional portion of the BRD to the UARTFBRD registerer
 
-	/* Set direction */
-	port->DIR = dirmsk ;
+  UART0->LCRH = (0x3 << 5);                    // 8-bit, no parity, 1 stop bit
+  UART0->CC = 0x0;                             // Configure the UART clock source as system clock
+
+  UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Recieve Enable
 }
 
-static void board_switch_init(void)
+static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirmsk)
 {
-    GPIOF->DIR &= ~(1<<BOARD_BTN); 
-    GPIOF->PUR |=  (1<<BOARD_BTN); 
-    GPIOF->DEN |=  (1<<BOARD_BTN); 
+  /* Enable PortF Clock */
+  SYSCTL->RCGCGPIO |= (1 << 5);
+
+  /* Let the clock stabilize */
+  while ( !((SYSCTL->PRGPIO) & (1 << 5)) )
+    ;
+
+  /* Port Digital Enable */
+  port->DEN |= PinMsk;
+
+  /* Set direction */
+  port->DIR = dirmsk;
 }
 
-static void WriteGPIOPin(GPIOA_Type* port, uint8_t PinMsk, bool state)
+static void board_switch_init (void)
 {
-    if(state)
-        port->DATA |= PinMsk; 
-    else
-        port->DATA &= ~(PinMsk);
+  GPIOF->DIR &= ~(1 << BOARD_BTN);
+  GPIOF->PUR |= (1 << BOARD_BTN);
+  GPIOF->DEN |= (1 << BOARD_BTN);
 }
 
-static uint32_t ReadGPIOPin(GPIOA_Type *port, uint8_t pinMsk)
+static void WriteGPIOPin (GPIOA_Type *port, uint8_t PinMsk, bool state)
 {
-    return (port -> DATA & pinMsk) ;
+  if ( state )
+    port->DATA |= PinMsk;
+  else
+    port->DATA &= ~(PinMsk);
 }
 
-void board_init(void)
+static uint32_t ReadGPIOPin (GPIOA_Type *port, uint8_t pinMsk)
 {
-    SystemCoreClockUpdate(); 
- 
+  return (port->DATA & pinMsk);
+}
+
+void board_init (void)
+{
+  SystemCoreClockUpdate();
+
 #if CFG_TUSB_OS == OPT_OS_NONE
-    // 1ms tick timer
-    SysTick_Config(SystemCoreClock / 1000);
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
     // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
     NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
-    /* Reset USB */ 
-    SYSCTL->SRCR2 |= (1u<<16);
+  /* Reset USB */
+  SYSCTL->SRCR2 |= (1u << 16);
 
-    for (volatile uint8_t i=0; i<20; i++);
+  for ( volatile uint8_t i = 0; i < 20; i++ ) {}
 
-    SYSCTL->SRCR2 &= ~(1u<<16);
+  SYSCTL->SRCR2 &= ~(1u << 16);
 
-    /* Open the USB clock gate */
-    SYSCTL->RCGCUSB |= (1<<0);
+  /* Open the USB clock gate */
+  SYSCTL->RCGCUSB |= (1 << 0);
 
-    /* Power-up USB PLL */
-    SYSCTL->RCC2 &= ~(1u<<14);
+  /* Power-up USB PLL */
+  SYSCTL->RCC2 &= ~(1u << 14);
 
-    /* USB IO Initialization */
-    SYSCTL->RCGCGPIO |= (1u<<3); 
-    
-    /* Let the clock stabilize */ 
-    while(!(SYSCTL->PRGPIO & (1u<<3))); 
+  /* USB IO Initialization */
+  SYSCTL->RCGCGPIO |= (1u << 3);
 
-    /* USB IOs to Analog Mode */ 
-    GPIOD->AFSEL &= ~ ( (1u<<4) | (1u<<5) ); 
-    GPIOD->DEN   &= ~ ( (1u<<4) | (1u<<5) ); 
-    GPIOD->AMSEL |=   ( (1u<<4) | (1u<<5) );
+  /* Let the clock stabilize */
+  while ( !(SYSCTL->PRGPIO & (1u << 3)) )
+    ;
 
-    uint8_t leds = (1<<LED_PIN_RED) | (1<<LED_PIN_BLUE) | (1<<LED_PIN_GREEN) ; 
-    uint8_t dirmsk = (1<<LED_PIN_RED) | (1<<LED_PIN_BLUE) | (1<<LED_PIN_GREEN) ; 
+  /* USB IOs to Analog Mode */
+  GPIOD->AFSEL &= ~((1u << 4) | (1u << 5));
+  GPIOD->DEN &= ~((1u << 4) | (1u << 5));
+  GPIOD->AMSEL |= ((1u << 4) | (1u << 5));
 
-    /* Configure GPIO for board LED */
-    initialize_board_led(LED_PORT,leds, dirmsk); 
+  uint8_t leds = (1 << LED_PIN_RED) | (1 << LED_PIN_BLUE) | (1 << LED_PIN_GREEN);
+  uint8_t dirmsk = (1 << LED_PIN_RED) | (1 << LED_PIN_BLUE) | (1 << LED_PIN_GREEN);
 
-    /* Configure GPIO for board switch */
-    board_switch_init(); 
+  /* Configure GPIO for board LED */
+  initialize_board_led(LED_PORT, leds, dirmsk);
 
-    /* Initialize board UART */
-    board_uart_init(); 
+  /* Configure GPIO for board switch */
+  board_switch_init();
+
+  /* Initialize board UART */
+  board_uart_init();
 
 }
 
-void board_led_write(bool state)
+void board_led_write (bool state)
 {
-    WriteGPIOPin(LED_PORT, (1<<LED_PIN_BLUE), state); 
+  WriteGPIOPin(LED_PORT, (1 << LED_PIN_BLUE), state);
 }
 
-uint32_t board_button_read(void)
+uint32_t board_button_read (void)
 {
-    uint32_t gpio_value = ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk);
-    return BUTTON_STATE_ACTIVE ? gpio_value : !gpio_value;
+  uint32_t gpio_value = ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk);
+  return BUTTON_STATE_ACTIVE ? gpio_value : !gpio_value;
 }
 
-int board_uart_write(void const* buf, int len)
+int board_uart_write (void const *buf, int len)
 {
-    uint8_t const* data = buf; 
+  uint8_t const * data = buf;
 
-    for(int i=0; i<len; i++)
-    {
-        while((UART0->FR &(1<<5)) != 0);                 // Poll until previous data was shofted out
-        UART0->DR= data[i];                                   // Write UART0 DATA REGISTER 
-    }
+  for ( int i = 0; i < len; i++ )
+  {
+    while ( (UART0->FR & (1 << 5)) != 0 ) {} // Poll until previous data was shofted out
+    UART0->DR = data[i];                     // Write UART0 DATA REGISTER
+  }
 
-    return len;
+  return len;
 }
 
-int board_uart_read(uint8_t* buf, int len)
+int board_uart_read (uint8_t *buf, int len)
 {
-  (void) buf; (void) len;
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
@@ -159,7 +172,7 @@ void SysTick_Handler (void)
   system_ticks++;
 }
 
-uint32_t board_millis(void)
+uint32_t board_millis (void)
 {
   return system_ticks;
 }
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 1befa89b6..7254f3362 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -143,7 +143,10 @@
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- TI -------------//
-#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx, OPT_MCU_MSP432E4xx)
+#elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+
+#elif TU_CHECK_MCU(OPT_MCU_MSP432E4xx, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 //------------- ValentyUSB -------------//
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 04139dd78..c745b4969 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_MSP432E4xx
+#if TU_CHECK_MCU(OPT_MCU_MSP432E4xx, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
 
 #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
 /* GCC warns that an address may be unaligned, even though
@@ -35,7 +35,21 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
 #endif
 
 #include "device/dcd.h"
-#include "msp.h"
+
+#if TU_CHECK_MCU(OPT_MCU_MSP432E4xx)
+  #include "musb_msp432e.h"
+
+#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+  #include "musb_tm4c.h"
+
+  // HACK generalize later
+  #include "musb_type.h"
+  #define FIFO0_WORD FIFO0
+  #define FIFO1_WORD FIFO1
+
+#else
+  #error "Unsupported MCUs"
+#endif
 
 /*------------------------------------------------------------------
  * MACRO TYPEDEF CONSTANT ENUM DECLARATION
diff --git a/src/portable/mentor/musb/musb_msp432e.h b/src/portable/mentor/musb/musb_msp432e.h
new file mode 100644
index 000000000..fce21de88
--- /dev/null
+++ b/src/portable/mentor/musb/musb_msp432e.h
@@ -0,0 +1,40 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_MUSB_MSP432E_H_
+#define _TUSB_MUSB_MSP432E_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "msp.h"
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/mentor/musb/musb_tm4c.h b/src/portable/mentor/musb/musb_tm4c.h
new file mode 100644
index 000000000..65a1751b0
--- /dev/null
+++ b/src/portable/mentor/musb/musb_tm4c.h
@@ -0,0 +1,45 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_MUSB_TM4C_H_
+#define _TUSB_MUSB_TM4C_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_TM4C123
+  #include "TM4C123.h"
+//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129
+#else
+  #error "Unsupported MCUs"
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 50a922840..246893ddb 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -87,7 +87,8 @@
 // TI MSP430
 #define OPT_MCU_MSP430x5xx        500 ///< TI MSP430x5xx
 #define OPT_MCU_MSP432E4xx        510 ///< TI MSP432E4xx
-#define OPT_MCU_TM4C123           511 ///< TI Tiva C 123x
+#define OPT_MCU_TM4C123           511 ///< TI Tiva-C 123x
+#define OPT_MCU_TM4C129           512 ///< TI Tiva-C 129x
 
 // ValentyUSB eptri
 #define OPT_MCU_VALENTYUSB_EPTRI  600 ///< Fomu eptri config

From f65917f51a3046c828ced5fbb982348542b382a5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Nov 2021 17:24:58 +0700
Subject: [PATCH 0660/2085] rename to simply OPT_MCU_MSP432E4, add msp432e to
 ci

---
 .github/workflows/build_arm.yml     | 1 +
 hw/bsp/board_mcu.h                  | 2 +-
 hw/bsp/msp432e4/family.mk           | 2 +-
 src/class/audio/audio_device.c      | 2 +-
 src/device/dcd_attr.h               | 2 +-
 src/portable/mentor/musb/dcd_musb.c | 4 ++--
 src/tusb_option.h                   | 4 ++--
 7 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 8db0fe04f..cf9246d52 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -45,6 +45,7 @@ jobs:
         - 'lpc54'
         - 'lpc55'
         - 'mm32'
+        - 'msp430e4'
         - 'nrf'
         - 'rp2040'
         - 'samd11'
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 2928ea657..f8b5c061c 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -98,7 +98,7 @@
 #elif CFG_TUSB_MCU == OPT_MCU_MSP430x5xx
   #include "msp430.h"
 
-#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4xx
+#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4
   #include "msp.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
index ee7faa208..b664c4c1b 100644
--- a/hw/bsp/msp432e4/family.mk
+++ b/hw/bsp/msp432e4/family.mk
@@ -9,7 +9,7 @@ CFLAGS += \
 	-mfloat-abi=hard \
 	-mfpu=fpv4-sp-d16 \
 	-D__MSP432E401Y__ \
-	-DCFG_TUSB_MCU=OPT_MCU_MSP432E4xx
+	-DCFG_TUSB_MCU=OPT_MCU_MSP432E4
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=cast-qual -Wno-error=format=
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 38bfc023b..d9f2e284e 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -103,7 +103,7 @@
     CFG_TUSB_MCU == OPT_MCU_LPC18XX                               || \
     CFG_TUSB_MCU == OPT_MCU_LPC43XX                               || \
     CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX                            || \
-    CFG_TUSB_MCU == OPT_MCU_MSP432E4xx
+    CFG_TUSB_MCU == OPT_MCU_MSP432E4
 #if TUD_AUDIO_PREFER_RING_BUFFER
 #define  USE_LINEAR_BUFFER     0
 #else
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 7254f3362..73d592e5c 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -146,7 +146,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(OPT_MCU_MSP432E4xx, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+#elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 //------------- ValentyUSB -------------//
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index c745b4969..4b4c2f9b2 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TU_CHECK_MCU(OPT_MCU_MSP432E4xx, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
 
 #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
 /* GCC warns that an address may be unaligned, even though
@@ -36,7 +36,7 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
 
 #include "device/dcd.h"
 
-#if TU_CHECK_MCU(OPT_MCU_MSP432E4xx)
+#if TU_CHECK_MCU(OPT_MCU_MSP432E4)
   #include "musb_msp432e.h"
 
 #elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129)
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 246893ddb..2edd310fa 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -84,9 +84,9 @@
 // Sony
 #define OPT_MCU_CXD56             400 ///< SONY CXD56
 
-// TI MSP430
+// TI
 #define OPT_MCU_MSP430x5xx        500 ///< TI MSP430x5xx
-#define OPT_MCU_MSP432E4xx        510 ///< TI MSP432E4xx
+#define OPT_MCU_MSP432E4          510 ///< TI MSP432E4xx
 #define OPT_MCU_TM4C123           511 ///< TI Tiva-C 123x
 #define OPT_MCU_TM4C129           512 ///< TI Tiva-C 129x
 

From 17ef1503c8adc96e1874fb4bf497b7fcf6b4808a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Nov 2021 17:37:21 +0700
Subject: [PATCH 0661/2085] move tm4c132 into bsp family, add it into ci

---
 .github/workflows/build_arm.yml               |  1 +
 hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h   | 52 +++++++++++++++++++
 hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk  | 11 ++++
 .../boards}/ek-tm4c123gxl/tm4c123.ld          |  0
 .../tm4c123gxl.c => tm4c123/family.c}         | 19 ++-----
 .../board.mk => tm4c123/family.mk}            | 11 ++--
 6 files changed, 70 insertions(+), 24 deletions(-)
 create mode 100644 hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h
 create mode 100644 hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
 rename hw/bsp/{ => tm4c123/boards}/ek-tm4c123gxl/tm4c123.ld (100%)
 rename hw/bsp/{ek-tm4c123gxl/tm4c123gxl.c => tm4c123/family.c} (91%)
 rename hw/bsp/{ek-tm4c123gxl/board.mk => tm4c123/family.mk} (81%)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index cf9246d52..e4d64826e 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -58,6 +58,7 @@ jobs:
         - 'stm32f7'
         - 'stm32h7'
         - 'stm32l4'
+        - 'tm4c123'
         - 'xmc4000'
     steps:
     - name: Setup Python
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h
new file mode 100644
index 000000000..5732056ae
--- /dev/null
+++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define BOARD_UART            UART0
+#define BOARD_UART_PORT       GPIOA
+
+#define BOARD_BTN_PORT        GPIOF
+#define BOARD_BTN             4
+#define BOARD_BTN_Msk         (1u<<4)
+#define BUTTON_STATE_ACTIVE   0
+
+#define LED_PORT              GPIOF
+#define LED_PIN_RED           1
+#define LED_PIN_BLUE          2
+#define LED_PIN_GREEN         3
+#define LED_STATE_ON          1
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
new file mode 100644
index 000000000..d60365d1d
--- /dev/null
+++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += -DTM4C123GH6PM
+ 
+LD_FILE = $(BOARD_PATH)/tm4c123.ld
+
+# For flash-jlink target
+JLINK_DEVICE = TM4C123GH6PM
+
+# flash using openocd
+OPENOCD_OPTION = -f board/ti_ek-tm4c123gxl.cfg
+
+flash: flash-openocd
diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123.ld b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld
similarity index 100%
rename from hw/bsp/ek-tm4c123gxl/tm4c123.ld
rename to hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld
diff --git a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c b/hw/bsp/tm4c123/family.c
similarity index 91%
rename from hw/bsp/ek-tm4c123gxl/tm4c123gxl.c
rename to hw/bsp/tm4c123/family.c
index 663fbf127..048832dc9 100644
--- a/hw/bsp/ek-tm4c123gxl/tm4c123gxl.c
+++ b/hw/bsp/tm4c123/family.c
@@ -1,19 +1,6 @@
-#include <TM4C123.h>
-#include <board.h>
-
-#define BOARD_UART            UART0
-#define BOARD_UART_PORT       GPIOA
-
-#define BOARD_BTN_PORT        GPIOF
-#define BOARD_BTN             4
-#define BOARD_BTN_Msk         (1u<<4)
-#define BUTTON_STATE_ACTIVE   0
-
-#define LED_PORT              GPIOF
-#define LED_PIN_RED           1
-#define LED_PIN_BLUE          2
-#define LED_PIN_GREEN         3
-#define LED_STATE_ON          1
+#include "TM4C123.h"
+#include "bsp/board.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/ek-tm4c123gxl/board.mk b/hw/bsp/tm4c123/family.mk
similarity index 81%
rename from hw/bsp/ek-tm4c123gxl/board.mk
rename to hw/bsp/tm4c123/family.mk
index 9d0d67e1c..9665a2d7d 100644
--- a/hw/bsp/ek-tm4c123gxl/board.mk
+++ b/hw/bsp/tm4c123/family.mk
@@ -1,5 +1,7 @@
 DEPS_SUBMODULES += hw/mcu/ti
 
+include $(TOP)/$(BOARD_PATH)/board.mk
+
 CFLAGS += \
   -flto \
   -mthumb \
@@ -22,7 +24,7 @@ LD_FILE = $(BOARD_PATH)/tm4c123.ld
 INC += \
 	$(TOP)/$(MCU_DIR)/CMSIS/5.7.0/CMSIS/Include \
 	$(TOP)/$(MCU_DIR)/Include/TM4C123 \
-	$(TOP)/hw/bsp
+	$(TOP)/$(BOARD_PATH)
 
 SRC_C += \
 	src/portable/mentor/musb/dcd_musb.c \
@@ -31,10 +33,3 @@ SRC_C += \
 
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = TM4C123GH6PM
-
-# flash using openocd
-OPENOCD_OPTION = -f board/ti_ek-tm4c123gxl.cfg
-flash: flash-openocd

From d415bd4d7b144f470b8d1c12284abb161ac4dd5f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Nov 2021 17:39:37 +0700
Subject: [PATCH 0662/2085] add missing musb type file

---
 src/portable/mentor/musb/musb_type.h | 2624 ++++++++++++++++++++++++++
 1 file changed, 2624 insertions(+)
 create mode 100644 src/portable/mentor/musb/musb_type.h

diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h
new file mode 100644
index 000000000..8f83305a5
--- /dev/null
+++ b/src/portable/mentor/musb/musb_type.h
@@ -0,0 +1,2624 @@
+/******************************************************************************
+*
+* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+*  Redistributions of source code must retain the above copyright
+*  notice, this list of conditions and the following disclaimer.
+*
+*  Redistributions in binary form must reproduce the above copyright
+*  notice, this list of conditions and the following disclaimer in the
+*  documentation and/or other materials provided with the
+*  distribution.
+*
+*  Neither the name of Texas Instruments Incorporated nor the names of
+*  its contributors may be used to endorse or promote products derived
+*  from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*******************************************************************************/
+
+#ifndef _TUSB_MUSB_TYPE_H_
+#define _TUSB_MUSB_TYPE_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M             0x0000007F  // Function Address
+#define USB_FADDR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP         0x00000080  // Isochronous Update
+#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect
+#define USB_POWER_HSENAB        0x00000020  // High Speed Enable
+#define USB_POWER_HSMODE        0x00000010  // High Speed Enable
+#define USB_POWER_RESET         0x00000008  // RESET Signaling
+#define USB_POWER_RESUME        0x00000004  // RESUME Signaling
+#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode
+#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR          0x00000080  // VBUS Error (OTG only)
+#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST (OTG only)
+#define USB_IS_DISCON           0x00000020  // Session Disconnect (OTG only)
+#define USB_IS_CONN             0x00000010  // Session Connect
+#define USB_IS_SOF              0x00000008  // Start of Frame
+#define USB_IS_BABBLE           0x00000004  // Babble Detected
+#define USB_IS_RESET            0x00000004  // RESET Signaling Detected
+#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected
+#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt (OTG
+                                            // only)
+#define USB_IE_SESREQ           0x00000040  // Enable Session Request (OTG
+                                            // only)
+#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt
+#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt
+#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt
+#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt
+#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
+#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M             0x000007FF  // Frame Number
+#define USB_FRAME_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index
+#define USB_EPIDX_EPIDX_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH         0x00000080  // Force Host Mode
+#define USB_TEST_FIFOACC        0x00000040  // FIFO Access
+#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode
+#define USB_TEST_FORCEHS        0x00000010  // Force High-Speed Mode
+#define USB_TEST_TESTPKT        0x00000008  // Test Packet Mode Enable
+#define USB_TEST_TESTK          0x00000004  // Test_K Mode Enable
+#define USB_TEST_TESTJ          0x00000002  // Test_J Mode Enable
+#define USB_TEST_TESTSE0NAK     0x00000001  // Test_SE0_NAK Test Mode Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO0_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO1_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO2_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO3_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO4_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO5_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO6_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO7_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV          0x00000080  // Device Mode (OTG only)
+#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level (OTG only)
+#define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid
+#define USB_DEVCTL_HOST         0x00000004  // Host Mode
+#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request (OTG only)
+#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CCONF register.
+//
+//*****************************************************************************
+#define USB_CCONF_TXEDMA        0x00000002  // TX Early DMA Enable
+#define USB_CCONF_RXEDMA        0x00000001  // TX Early DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_TXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_TXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_TXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_TXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_TXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_TXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_RXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_RXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_RXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_RXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_RXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_RXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIVBUSCTL_USEEXTVBUSIND                                         \
+                                0x00000002  // Use External VBUS Indicator
+#define USB_ULPIVBUSCTL_USEEXTVBUS                                            \
+                                0x00000001  // Use External VBUS
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGDATA
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGDATA_REGDATA_M                                             \
+                                0x000000FF  // Register Data
+#define USB_ULPIREGDATA_REGDATA_S                                             \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGADDR
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGADDR_ADDR_M  0x000000FF  // Register Address
+#define USB_ULPIREGADDR_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGCTL
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGCTL_RDWR     0x00000004  // Read/Write Control
+#define USB_ULPIREGCTL_REGCMPLT 0x00000002  // Register Access Complete
+#define USB_ULPIREGCTL_REGACC   0x00000001  // Initiate Register Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPINFO register.
+//
+//*****************************************************************************
+#define USB_EPINFO_RXEP_M       0x000000F0  // RX Endpoints
+#define USB_EPINFO_TXEP_M       0x0000000F  // TX Endpoints
+#define USB_EPINFO_RXEP_S       4
+#define USB_EPINFO_TXEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RAMINFO register.
+//
+//*****************************************************************************
+#define USB_RAMINFO_DMACHAN_M   0x000000F0  // DMA Channels
+#define USB_RAMINFO_RAMBITS_M   0x0000000F  // RAM Address Bus Width
+#define USB_RAMINFO_DMACHAN_S   4
+#define USB_RAMINFO_RAMBITS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait
+#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID
+#define USB_CONTIM_WTCON_S      4
+#define USB_CONTIM_WTID_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HSEOF register.
+//
+//*****************************************************************************
+#define USB_HSEOF_HSEOFG_M      0x000000FF  // HIgh-Speed End-of-Frame Gap
+#define USB_HSEOF_HSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR0_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR0_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT0_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
+#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
+#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
+#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
+#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
+#define USB_CSRL0_STALL         0x00000020  // Send Stall
+#define USB_CSRL0_SETEND        0x00000010  // Setup End
+#define USB_CSRL0_ERROR         0x00000010  // Error
+#define USB_CSRL0_DATAEND       0x00000008  // Data End
+#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
+#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
+#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
+#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DISPING       0x00000008  // PING Disable
+#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable
+#define USB_CSRH0_DT            0x00000002  // Data Toggle
+#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count
+#define USB_COUNT0_COUNT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed
+#define USB_TYPE0_SPEED_HIGH    0x00000040  // High
+#define USB_TYPE0_SPEED_FULL    0x00000080  // Full
+#define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL1_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL1_ERROR       0x00000004  // Error
+#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH1_MODE        0x00000020  // Mode
+#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH1_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL1_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL1_OVER        0x00000004  // Overrun
+#define USB_RXCSRL1_ERROR       0x00000004  // Error
+#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH1_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH1_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE1_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL1_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE1_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL1_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL2_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL2_ERROR       0x00000004  // Error
+#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH2_MODE        0x00000020  // Mode
+#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH2_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL2_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL2_ERROR       0x00000004  // Error
+#define USB_RXCSRL2_OVER        0x00000004  // Overrun
+#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH2_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH2_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE2_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL2_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE2_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL2_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL3_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL3_ERROR       0x00000004  // Error
+#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH3_MODE        0x00000020  // Mode
+#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH3_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL3_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL3_ERROR       0x00000004  // Error
+#define USB_RXCSRL3_OVER        0x00000004  // Overrun
+#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH3_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH3_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE3_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL3_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE3_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL3_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL4_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL4_ERROR       0x00000004  // Error
+#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH4_MODE        0x00000020  // Mode
+#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH4_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL4_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL4_OVER        0x00000004  // Overrun
+#define USB_RXCSRL4_ERROR       0x00000004  // Error
+#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH4_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH4_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE4_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL4_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE4_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL4_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL5_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL5_ERROR       0x00000004  // Error
+#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH5_MODE        0x00000020  // Mode
+#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH5_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL5_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL5_ERROR       0x00000004  // Error
+#define USB_RXCSRL5_OVER        0x00000004  // Overrun
+#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH5_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH5_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE5_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL5_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE5_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL5_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL6_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL6_ERROR       0x00000004  // Error
+#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH6_MODE        0x00000020  // Mode
+#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH6_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL6_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL6_ERROR       0x00000004  // Error
+#define USB_RXCSRL6_OVER        0x00000004  // Overrun
+#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH6_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH6_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE6_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL6_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE6_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL6_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL7_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL7_ERROR       0x00000004  // Error
+#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH7_MODE        0x00000020  // Mode
+#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH7_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL7_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL7_ERROR       0x00000004  // Error
+#define USB_RXCSRL7_OVER        0x00000004  // Overrun
+#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH7_DT          0x00000002  // Data Toggle
+#define USB_RXCSRH7_INCOMPRX    0x00000001  // Incomplete RX Transmission
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE7_SPEED_HIGH  0x00000040  // High
+#define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL7_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE7_SPEED_HIGH  0x00000040  // High
+#define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL7_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAINTR register.
+//
+//*****************************************************************************
+#define USB_DMAINTR_CH7         0x00000080  // Channel 7 DMA Interrupt
+#define USB_DMAINTR_CH6         0x00000040  // Channel 6 DMA Interrupt
+#define USB_DMAINTR_CH5         0x00000020  // Channel 5 DMA Interrupt
+#define USB_DMAINTR_CH4         0x00000010  // Channel 4 DMA Interrupt
+#define USB_DMAINTR_CH3         0x00000008  // Channel 3 DMA Interrupt
+#define USB_DMAINTR_CH2         0x00000004  // Channel 2 DMA Interrupt
+#define USB_DMAINTR_CH1         0x00000002  // Channel 1 DMA Interrupt
+#define USB_DMAINTR_CH0         0x00000001  // Channel 0 DMA Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL0 register.
+//
+//*****************************************************************************
+#define USB_DMACTL0_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL0_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL0_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL0_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL0_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL0_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL0_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL0_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL0_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL0_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL0_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL0_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR0 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR0_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR0_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT0
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT0_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT0_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL1 register.
+//
+//*****************************************************************************
+#define USB_DMACTL1_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL1_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL1_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL1_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL1_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL1_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL1_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL1_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL1_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL1_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL1_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL1_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR1 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR1_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR1_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT1_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT1_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL2 register.
+//
+//*****************************************************************************
+#define USB_DMACTL2_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL2_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL2_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL2_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL2_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL2_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL2_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL2_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL2_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL2_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL2_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL2_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR2 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR2_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR2_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT2_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT2_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL3 register.
+//
+//*****************************************************************************
+#define USB_DMACTL3_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL3_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL3_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL3_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL3_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL3_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL3_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL3_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL3_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL3_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL3_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL3_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR3 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR3_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR3_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT3_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT3_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL4 register.
+//
+//*****************************************************************************
+#define USB_DMACTL4_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL4_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL4_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL4_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL4_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL4_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL4_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL4_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL4_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL4_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL4_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL4_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR4 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR4_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR4_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT4_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT4_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL5 register.
+//
+//*****************************************************************************
+#define USB_DMACTL5_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL5_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL5_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL5_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL5_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL5_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL5_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL5_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL5_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL5_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL5_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL5_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR5 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR5_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR5_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT5_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT5_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL6 register.
+//
+//*****************************************************************************
+#define USB_DMACTL6_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL6_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL6_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL6_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL6_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL6_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL6_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL6_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL6_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL6_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL6_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL6_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR6 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR6_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR6_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT6_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT6_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL7 register.
+//
+//*****************************************************************************
+#define USB_DMACTL7_BRSTM_M     0x00000600  // Burst Mode
+#define USB_DMACTL7_BRSTM_ANY   0x00000000  // Bursts of unspecified length
+#define USB_DMACTL7_BRSTM_INC4  0x00000200  // INCR4 or unspecified length
+#define USB_DMACTL7_BRSTM_INC8  0x00000400  // INCR8, INCR4 or unspecified
+                                            // length
+#define USB_DMACTL7_BRSTM_INC16 0x00000600  // INCR16, INCR8, INCR4 or
+                                            // unspecified length
+#define USB_DMACTL7_ERR         0x00000100  // Bus Error Bit
+#define USB_DMACTL7_EP_M        0x000000F0  // Endpoint number
+#define USB_DMACTL7_IE          0x00000008  // DMA Interrupt Enable
+#define USB_DMACTL7_MODE        0x00000004  // DMA Transfer Mode
+#define USB_DMACTL7_DIR         0x00000002  // DMA Direction
+#define USB_DMACTL7_ENABLE      0x00000001  // DMA Transfer Enable
+#define USB_DMACTL7_EP_S        4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR7 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR7_ADDR_M     0xFFFFFFFC  // DMA Address
+#define USB_DMAADDR7_ADDR_S     2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT7_COUNT_M   0xFFFFFFFC  // DMA Count
+#define USB_DMACOUNT7_COUNT_S   2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CTO register.
+//
+//*****************************************************************************
+#define USB_CTO_CCTV_M          0x0000FFFF  // Configurable Chirp Timeout Value
+#define USB_CTO_CCTV_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HHSRTN register.
+//
+//*****************************************************************************
+#define USB_HHSRTN_HHSRTN_M     0x0000FFFF  // HIgh Speed to UTM Operating
+                                            // Delay
+#define USB_HHSRTN_HHSRTN_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HSBT register.
+//
+//*****************************************************************************
+#define USB_HSBT_HSBT_M         0x0000000F  // High Speed Timeout Adder
+#define USB_HSBT_HSBT_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMATTR register.
+//
+//*****************************************************************************
+#define USB_LPMATTR_ENDPT_M     0x0000F000  // Endpoint
+#define USB_LPMATTR_RMTWAK      0x00000100  // Remote Wake
+#define USB_LPMATTR_HIRD_M      0x000000F0  // Host Initiated Resume Duration
+#define USB_LPMATTR_LS_M        0x0000000F  // Link State
+#define USB_LPMATTR_LS_L1       0x00000001  // Sleep State (L1)
+#define USB_LPMATTR_ENDPT_S     12
+#define USB_LPMATTR_HIRD_S      4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMCNTRL register.
+//
+//*****************************************************************************
+#define USB_LPMCNTRL_NAK        0x00000010  // LPM NAK
+#define USB_LPMCNTRL_EN_M       0x0000000C  // LPM Enable
+#define USB_LPMCNTRL_EN_NONE    0x00000000  // LPM and Extended transactions
+                                            // are not supported. In this case,
+                                            // the USB does not respond to LPM
+                                            // transactions and LPM
+                                            // transactions cause a timeout
+#define USB_LPMCNTRL_EN_EXT     0x00000004  // LPM is not supported but
+                                            // extended transactions are
+                                            // supported. In this case, the USB
+                                            // does respond to an LPM
+                                            // transaction with a STALL
+#define USB_LPMCNTRL_EN_LPMEXT  0x0000000C  // The USB supports LPM extended
+                                            // transactions. In this case, the
+                                            // USB responds with a NYET or an
+                                            // ACK as determined by the value
+                                            // of TXLPM and other conditions
+#define USB_LPMCNTRL_RES        0x00000002  // LPM Resume
+#define USB_LPMCNTRL_TXLPM      0x00000001  // Transmit LPM Transaction Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMIM register.
+//
+//*****************************************************************************
+#define USB_LPMIM_ERR           0x00000020  // LPM Error Interrupt Mask
+#define USB_LPMIM_RES           0x00000010  // LPM Resume Interrupt Mask
+#define USB_LPMIM_NC            0x00000008  // LPM NC Interrupt Mask
+#define USB_LPMIM_ACK           0x00000004  // LPM ACK Interrupt Mask
+#define USB_LPMIM_NY            0x00000002  // LPM NY Interrupt Mask
+#define USB_LPMIM_STALL         0x00000001  // LPM STALL Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMRIS register.
+//
+//*****************************************************************************
+#define USB_LPMRIS_ERR          0x00000020  // LPM Interrupt Status
+#define USB_LPMRIS_RES          0x00000010  // LPM Resume Interrupt Status
+#define USB_LPMRIS_NC           0x00000008  // LPM NC Interrupt Status
+#define USB_LPMRIS_ACK          0x00000004  // LPM ACK Interrupt Status
+#define USB_LPMRIS_NY           0x00000002  // LPM NY Interrupt Status
+#define USB_LPMRIS_LPMST        0x00000001  // LPM STALL Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMFADDR register.
+//
+//*****************************************************************************
+#define USB_LPMFADDR_ADDR_M     0x0000007F  // LPM Function Address
+#define USB_LPMFADDR_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
+#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
+#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
+#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
+#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense
+#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable
+#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable
+#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
+                                            // Configuration
+#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
+                                            // (OTG only)
+#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
+                                            // (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMOD_M       0x00000007  // Device Mode
+#define USB_GPCS_DEVMOD_OTG     0x00000000  // Use USB0VBUS and USB0ID pin
+#define USB_GPCS_DEVMOD_HOST    0x00000002  // Force USB0VBUS and USB0ID low
+#define USB_GPCS_DEVMOD_DEV     0x00000003  // Force USB0VBUS and USB0ID high
+#define USB_GPCS_DEVMOD_HOSTVBUS                                              \
+                                0x00000004  // Use USB0VBUS and force USB0ID
+                                            // low
+#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005  // Use USB0VBUS and force USB0ID
+                                            // high
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PP register.
+//
+//*****************************************************************************
+#define USB_PP_ECNT_M           0x0000FF00  // Endpoint Count
+#define USB_PP_USB_M            0x000000C0  // USB Capability
+#define USB_PP_USB_DEVICE       0x00000040  // DEVICE
+#define USB_PP_USB_HOSTDEVICE   0x00000080  // HOST
+#define USB_PP_USB_OTG          0x000000C0  // OTG
+#define USB_PP_ULPI             0x00000020  // ULPI Present
+#define USB_PP_PHY              0x00000010  // PHY Present
+#define USB_PP_TYPE_M           0x0000000F  // Controller Type
+#define USB_PP_TYPE_0           0x00000000  // The first-generation USB
+                                            // controller
+#define USB_PP_TYPE_1           0x00000001  // The second-generation USB
+                                            // controller revision
+#define USB_PP_ECNT_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PC register.
+//
+//*****************************************************************************
+#define USB_PC_ULPIEN           0x00010000  // ULPI Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CC register.
+//
+//*****************************************************************************
+#define USB_CC_CLKEN            0x00000200  // USB Clock Enable
+#define USB_CC_CSD              0x00000100  // Clock Source/Direction
+#define USB_CC_CLKDIV_M         0x0000000F  // PLL Clock Divisor
+#define USB_CC_CLKDIV_S         0
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif

From 1e308dd6c096d9078b3cbe8ff387dcec6e83e71d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Nov 2021 19:18:52 +0700
Subject: [PATCH 0663/2085] reduce CFG_TUD_DFU_XFER_BUFSIZE for max compatible

---
 examples/device/dfu/src/tusb_config.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 66e357021..012d50019 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -80,7 +80,7 @@
 #define CFG_TUD_DFU    1
 
 // DFU buffer size, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
-#define CFG_TUD_DFU_XFER_BUFSIZE    512
+#define CFG_TUD_DFU_XFER_BUFSIZE    ( OPT_MODE_HIGH_SPEED ? 512 : 64 )
 
 #ifdef __cplusplus
  }

From 1c77f9f6694151beca9a490eadf545b30557e9a0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 Nov 2021 20:03:47 +0700
Subject: [PATCH 0664/2085] msp432e4 ci typo, skip dfu example for tm4c123

---
 .github/workflows/build_arm.yml       | 2 +-
 examples/device/dfu/.skip.MCU_TM4C123 | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)
 create mode 100644 examples/device/dfu/.skip.MCU_TM4C123

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index e4d64826e..dc4d9fcfb 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -45,7 +45,7 @@ jobs:
         - 'lpc54'
         - 'lpc55'
         - 'mm32'
-        - 'msp430e4'
+        - 'msp432e4'
         - 'nrf'
         - 'rp2040'
         - 'samd11'
diff --git a/examples/device/dfu/.skip.MCU_TM4C123 b/examples/device/dfu/.skip.MCU_TM4C123
new file mode 100644
index 000000000..6260e6e25
--- /dev/null
+++ b/examples/device/dfu/.skip.MCU_TM4C123
@@ -0,0 +1,4 @@
+LINK _build/ek-tm4c123gxl/dfu.elf
+/home/runner/cache/toolchain/xpack-arm-none-eabi-gcc-10.2.1-1.1/bin/../lib/gcc/arm-none-eabi/10.2.1/../../../../arm-none-eabi/bin/ld: section .ARM.exidx.text._close LMA [0000000000002980,0000000000002987] overlaps section .data LMA [0000000000002980,0000000000002a03]
+collect2: error: ld returned 1 exit status
+make: *** [../../rules.mk:94: _build/ek-tm4c123gxl/dfu.elf] Error 1
\ No newline at end of file

From 12e96ce571e3ca8d9771d4729eb65bd296acb72e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 Nov 2021 12:18:28 +0700
Subject: [PATCH 0665/2085] set DCFG_XCVRDLY when using external ULPI highspeed
 phy

---
 src/portable/synopsys/dwc2/dcd_dwc2.c  | 4 ++++
 src/portable/synopsys/dwc2/dwc2_type.h | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 44a5f8932..30b8aed69 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -444,6 +444,10 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
 
   // Set max speed
   dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos);
+
+  // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
+  // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
+  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dwc2->dcfg |= DCFG_XCVRDLY;
 }
 
 static bool check_dwc2(dwc2_regs_t * dwc2)
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 6e52ebc7b..dbef20314 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -416,6 +416,10 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 #define DCFG_PFIVL_0                     (0x1UL << DCFG_PFIVL_Pos)                // 0x00000800 */
 #define DCFG_PFIVL_1                     (0x2UL << DCFG_PFIVL_Pos)                // 0x00001000 */
 
+#define DCFG_XCVRDLY_Pos                 (14U)
+#define DCFG_XCVRDLY_Msk                 (0x1UL << DCFG_XCVRDLY_Pos)             /*!< 0x00004000 */
+#define DCFG_XCVRDLY                     DCFG_XCVRDLY_Msk                        // Enables delay between xcvr_sel and txvalid during device chirp
+
 #define DCFG_PERSCHIVL_Pos               (24U)
 #define DCFG_PERSCHIVL_Msk               (0x3UL << DCFG_PERSCHIVL_Pos)            // 0x03000000 */
 #define DCFG_PERSCHIVL                   DCFG_PERSCHIVL_Msk                       // Periodic scheduling interval */

From 301d6b413382e6601c6ca54522e207776e2316fb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 17 Nov 2021 09:48:08 +0700
Subject: [PATCH 0666/2085] clean up

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 30b8aed69..bb21b3dcd 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -443,11 +443,15 @@ static void phy_hs_init(dwc2_regs_t * dwc2)
   dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
 
   // Set max speed
-  dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos);
+  uint32_t dcfg = dwc2->dcfg;
+  dcfg &= ~DCFG_DSPD_Msk;
+  dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
 
   // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
   // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
-  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dwc2->dcfg |= DCFG_XCVRDLY;
+  if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY;
+
+  dwc2->dcfg = dcfg;
 }
 
 static bool check_dwc2(dwc2_regs_t * dwc2)

From dac7574c98cc6db1b40c244c5bedb81a2b78d0ca Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 22 Nov 2021 10:52:28 +0700
Subject: [PATCH 0667/2085] use USB_OTG_GLOBAL_BASE instead of hard code value

---
 src/portable/synopsys/dwc2/dwc2_bcm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index fcec0b0d2..353bc21ee 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -34,7 +34,7 @@
 #include "broadcom/interrupts.h"
 #include "broadcom/caches.h"
 
-#define DWC2_REG_BASE       0xFE980000UL
+#define DWC2_REG_BASE       USB_OTG_GLOBAL_BASE
 #define DWC2_EP_MAX         8
 #define DWC2_EP_FIFO_SIZE   4096
 

From 21787ecdd355917db3790be20f35f6f2d5a05a66 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 22 Nov 2021 10:52:53 +0700
Subject: [PATCH 0668/2085] update bcm prph

---
 hw/mcu/broadcom | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom
index d126323fc..5bff1d5e0 160000
--- a/hw/mcu/broadcom
+++ b/hw/mcu/broadcom
@@ -1 +1 @@
-Subproject commit d126323fc77e81d1f18677a439685a4754ea02aa
+Subproject commit 5bff1d5e02c37c38ee1e5cf3f7fe82fdc7e1517e

From 8a18c22c2f7c15b5c7869428877c1e50157d5856 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 22 Nov 2021 10:59:22 +0700
Subject: [PATCH 0669/2085] add BCM_VERSION

---
 hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk
index e69de29bb..897342479 100644
--- a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk
+++ b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk
@@ -0,0 +1 @@
+CFLAGS += -DBCM_VERSION=2711

From 64e6170224d86a41db782d5e23fd4baa7f0bc695 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Mon, 22 Nov 2021 11:26:23 +0700
Subject: [PATCH 0670/2085] Update bug_report.yml

---
 .github/ISSUE_TEMPLATE/bug_report.yml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index 291b22079..624d0ab7a 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -34,7 +34,10 @@ body:
       label: Firmware
       placeholder: |
         e.g examples/device/cdc_msc.
-        If it is custom firmware, please provide links to your minimal sources or as attached files.
+        If it is custom firmware, it is preferably compiled like one in example folder and reviewable for people to comment on. The easiest way is
+        - Fork this repo, checkout a new branch
+        - Add your-own-example based on stock one
+        - Push and post it here.
     validations:
       required: true
 
@@ -49,6 +52,7 @@ body:
     attributes:
       label: How to reproduce ?
       placeholder: |
+        Exact steps in chronological order, details should be specific e.g if you use a command/script to test with, please post it as well.
         1. Go to '...'
         2. Click on '....'
         3. See error      

From e5adc4680547a03ef2d9412305167e5d188dd5d0 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Mon, 22 Nov 2021 11:27:37 +0700
Subject: [PATCH 0671/2085] Update bug_report.yml

---
 .github/ISSUE_TEMPLATE/bug_report.yml | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index 624d0ab7a..fc41d8ff1 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -33,8 +33,7 @@ body:
     attributes:
       label: Firmware
       placeholder: |
-        e.g examples/device/cdc_msc.
-        If it is custom firmware, it is preferably compiled like one in example folder and reviewable for people to comment on. The easiest way is
+        e.g examples/device/cdc_msc. If it is custom firmware, it is preferably compiled like one in example folder and reviewable for people to comment on. The easiest way is
         - Fork this repo, checkout a new branch
         - Add your-own-example based on stock one
         - Push and post it here.

From ba76b2e3395ca3cb5033d70e34a6fa9a6ff7373c Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Mon, 22 Nov 2021 10:33:07 +0000
Subject: [PATCH 0672/2085] Add submodule for ft90x SDK

Add Bridgetek FT90x SDK as submodule.
---
 .gitmodules                      | 3 +++
 hw/mcu/bridgetek/ft9xx/ft90x-sdk | 1 +
 2 files changed, 4 insertions(+)
 create mode 160000 hw/mcu/bridgetek/ft9xx/ft90x-sdk

diff --git a/.gitmodules b/.gitmodules
index 4c86fd55c..e87b8750f 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -127,3 +127,6 @@
 [submodule "hw/mcu/gd/nuclei-sdk"]
 	path = hw/mcu/gd/nuclei-sdk
 	url = https://github.com/Nuclei-Software/nuclei-sdk.git
+[submodule "hw/mcu/bridgetek/ft9xx/ft90x-sdk"]
+	path = hw/mcu/bridgetek/ft9xx/ft90x-sdk
+	url = https://github.com/BRTSG-FOSS/ft90x-sdk
diff --git a/hw/mcu/bridgetek/ft9xx/ft90x-sdk b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
new file mode 160000
index 000000000..a94bec485
--- /dev/null
+++ b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
@@ -0,0 +1 @@
+Subproject commit a94bec4856b7e0f1dfda57307b66e3edb2c5a3c7

From edf3f3501656b010ad4a9e1d0a0d62573dd0b3fb Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Mon, 22 Nov 2021 12:38:04 +0000
Subject: [PATCH 0673/2085] Update ft90x-sdk

Update submodule for FT90X SDK to point to the v2.5.0 release code currently in main.
---
 hw/mcu/bridgetek/ft9xx/ft90x-sdk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/bridgetek/ft9xx/ft90x-sdk b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
index a94bec485..e8122eb6b 160000
--- a/hw/mcu/bridgetek/ft9xx/ft90x-sdk
+++ b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
@@ -1 +1 @@
-Subproject commit a94bec4856b7e0f1dfda57307b66e3edb2c5a3c7
+Subproject commit e8122eb6bd6286a1fe31f175a3e3eb0e7770c3e3

From a994540860306e7da80a6925633f1ac8486fbfd9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 23 Nov 2021 09:36:28 +0700
Subject: [PATCH 0674/2085] fix nrf easy dma race condition

---
 src/class/cdc/cdc_device.c            |  10 +-
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 128 +++++++++++++-------------
 2 files changed, 71 insertions(+), 67 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 74c116192..08f2af253 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -80,7 +80,7 @@ typedef struct
 //--------------------------------------------------------------------+
 CFG_TUSB_MEM_SECTION static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
 
-static void _prep_out_transaction (cdcd_interface_t* p_cdc)
+static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
 {
   uint8_t const rhport = TUD_OPT_RHPORT;
   uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff);
@@ -89,21 +89,23 @@ static void _prep_out_transaction (cdcd_interface_t* p_cdc)
   // TODO Actually we can still carry out the transfer, keeping count of received bytes
   // and slowly move it to the FIFO when read().
   // This pre-check reduces endpoint claiming
-  TU_VERIFY(available >= sizeof(p_cdc->epout_buf), );
+  TU_VERIFY(available >= sizeof(p_cdc->epout_buf));
 
   // claim endpoint
-  TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out), );
+  TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out));
 
   // fifo can be changed before endpoint is claimed
   available = tu_fifo_remaining(&p_cdc->rx_ff);
 
   if ( available >= sizeof(p_cdc->epout_buf) )
   {
-    usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf));
+    return usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf));
   }else
   {
     // Release endpoint since we don't make any transfer
     usbd_edpt_release(rhport, p_cdc->ep_out);
+
+    return false;
   }
 }
 
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 9d7db11b2..b10a29083 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -63,7 +63,7 @@ typedef struct
   uint8_t* buffer;
   uint16_t total_len;
   volatile uint16_t actual_len;
-  uint16_t  mps; // max packet size
+  uint16_t mps; // max packet size
 
   // nRF will auto accept OUT packet after DMA is done
   // indicate packet is already ACK
@@ -84,8 +84,6 @@ static struct
 
   // Number of pending DMA that is started but not handled yet by dcd_int_handler().
   // Since nRF can only carry one DMA can run at a time, this value is normally be either 0 or 1.
-  // However, in critical section with interrupt disabled, the DMA can be finished and added up
-  // until handled by dcd_int_handler() when exiting critical section.
   volatile uint8_t dma_pending;
 }_dcd;
 
@@ -115,67 +113,68 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
 }
 
 // helper to start DMA
+static void start_dma(volatile uint32_t* reg_startep)
+{
+  _dcd.dma_pending = true;
+
+  (*reg_startep) = 1;
+  __ISB(); __DSB();
+
+  // TASKS_EP0STATUS, TASKS_EP0RCVOUT seem to need EasyDMA to be available
+  // However these don't trigger any DMA transfer and got ENDED event subsequently
+  // Therefore dma_pending is corrected right away
+  if ( (reg_startep == &NRF_USBD->TASKS_EP0STATUS) || (reg_startep == &NRF_USBD->TASKS_EP0RCVOUT) )
+  {
+    _dcd.dma_pending = false;
+  }
+}
+
+// only 1 EasyDMA can be active at any time
 // TODO use Cortex M4 LDREX and STREX command (atomic) to have better mutex access to EasyDMA
 // since current implementation does not 100% guarded against race condition
 static void edpt_dma_start(volatile uint32_t* reg_startep)
 {
-  // Only one dma can be active
-  if ( _dcd.dma_pending )
+  // Called in critical section i.e within USB ISR, or USB/Global interrupt disabled
+  if ( is_in_isr() || __get_PRIMASK() || !NVIC_GetEnableIRQ(USBD_IRQn) )
   {
-    if (is_in_isr())
+    if (_dcd.dma_pending)
     {
-      // Called within ISR, use usbd task to defer later
+      //use usbd task to defer later
       usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true);
-      return;
-    }
-    else
+    }else
     {
-      if ( __get_PRIMASK() || !NVIC_GetEnableIRQ(USBD_IRQn) )
-      {
-        // Called in critical section with interrupt disabled. We have to manually check
-        // for the DMA complete by comparing current pending DMA with number of ENDED Events
-        uint32_t ended = 0;
+      start_dma(reg_startep);
+    }
+  }else
+  {
+    // Called in non-critical thread-mode, should be 99% of the time.
+    // Should be safe to blocking wait until previous DMA transfer complete
+    uint8_t const rhport = 0;
+    bool started = false;
+    while(!started)
+    {
+      // LDREX/STREX may be needed in form of std atomic (required C11) or
+      // use osal mutex to guard against multiple core MCUs such as nRF53
+      dcd_int_disable(rhport);
 
-        while ( _dcd.dma_pending > ((uint8_t) ended) )
-        {
-          ended = NRF_USBD->EVENTS_ENDISOIN + NRF_USBD->EVENTS_ENDISOOUT;
-
-          for (uint8_t i=0; i<EP_CBI_COUNT; i++)
-          {
-            ended += NRF_USBD->EVENTS_ENDEPIN[i] + NRF_USBD->EVENTS_ENDEPOUT[i];
-          }
-        }
-      }else
+      if ( !_dcd.dma_pending )
       {
-        // Called in non-critical thread-mode, should be 99% of the time.
-        // Should be safe to blocking wait until previous DMA transfer complete
-        while ( _dcd.dma_pending ) { }
+        start_dma(reg_startep);
+        started = true;
       }
+
+      dcd_int_enable(rhport);
+
+      // osal_yield();
     }
   }
-
-  _dcd.dma_pending++;
-
-  (*reg_startep) = 1;
-  __ISB(); __DSB();
 }
 
 // DMA is complete
 static void edpt_dma_end(void)
 {
   TU_ASSERT(_dcd.dma_pending, );
-  _dcd.dma_pending = 0;
-}
-
-// helper to set TASKS_EP0STATUS / TASKS_EP0RCVOUT since they also need EasyDMA
-// However TASKS_EP0STATUS doesn't trigger any DMA transfer and got ENDED event subsequently
-// Therefore dma_running state will be corrected right away
-void start_ep0_task(volatile uint32_t* reg_task)
-{
-  edpt_dma_start(reg_task);
-
-  // correct the dma_running++ in dma start
-  if (_dcd.dma_pending) _dcd.dma_pending--;
+  _dcd.dma_pending = false;
 }
 
 // helper getting td
@@ -194,7 +193,10 @@ static void xact_out_dma(uint8_t epnum)
   {
     xact_len = NRF_USBD->SIZE.ISOOUT;
     // If ZERO bit is set, ignore ISOOUT length
-    if (xact_len & USBD_SIZE_ISOOUT_ZERO_Msk) xact_len = 0;
+    if (xact_len & USBD_SIZE_ISOOUT_ZERO_Msk)
+    {
+      xact_len = 0;
+    }
     else
     {
       // Trigger DMA move data from Endpoint -> SRAM
@@ -216,8 +218,8 @@ static void xact_out_dma(uint8_t epnum)
     edpt_dma_start(&NRF_USBD->TASKS_STARTEPOUT[epnum]);
   }
 
-  xfer->buffer     += xact_len;
-  xfer->actual_len += xact_len;
+//  xfer->buffer     += xact_len;
+//  xfer->actual_len += xact_len;
 }
 
 // Prepare for a CBI transaction IN, call at the start
@@ -232,7 +234,7 @@ static void xact_in_dma(uint8_t epnum)
   NRF_USBD->EPIN[epnum].PTR    = (uint32_t) xfer->buffer;
   NRF_USBD->EPIN[epnum].MAXCNT = xact_len;
 
-  xfer->buffer += xact_len;
+  //xfer->buffer += xact_len;
 
   edpt_dma_start(&NRF_USBD->TASKS_STARTEPIN[epnum]);
 }
@@ -242,6 +244,7 @@ static void xact_in_dma(uint8_t epnum)
 //--------------------------------------------------------------------+
 void dcd_init (uint8_t rhport)
 {
+  TU_LOG1("dcd init\r\n");
   (void) rhport;
 }
 
@@ -466,7 +469,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   if ( control_status )
   {
     // Status Phase also requires EasyDMA has to be available as well !!!!
-    start_ep0_task(&NRF_USBD->TASKS_EP0STATUS);
+    edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS);
 
     // The nRF doesn't interrupt on status transmit so we queue up a success response.
     dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, is_in_isr());
@@ -476,7 +479,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     if ( epnum == 0 )
     {
       // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA
-      start_ep0_task(&NRF_USBD->TASKS_EP0RCVOUT);
+      edpt_dma_start(&NRF_USBD->TASKS_EP0RCVOUT);
     }else
     {
       if ( xfer->data_received )
@@ -522,7 +525,6 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
     // There maybe data in endpoint fifo already, we need to pull it out
     if ( (dir == TUSB_DIR_OUT) && xfer->data_received )
     {
-      TU_LOG_LOCATION();
       xfer->data_received = false;
       xact_out_dma(epnum);
     }
@@ -717,7 +719,8 @@ void dcd_int_handler(uint8_t rhport)
 
   if ( int_status & EDPT_END_ALL_MASK )
   {
-    // DMA complete move data from SRAM -> Endpoint
+    // DMA complete move data from SRAM <-> Endpoint
+    // Must before endpoint transfer handling
     edpt_dma_end();
   }
 
@@ -732,7 +735,7 @@ void dcd_int_handler(uint8_t rhport)
    *  - Host -> Endpoint
    *      EPDATA (or EP0DATADONE) interrupted, check EPDATASTATUS.EPOUT[i]
    *      to start DMA. For Bulk/Interrupt, this step can occur automatically (without sw),
-   *      which means data may or may not be ready (data_received flag).
+   *      which means data may or may not be ready (out_received flag).
    *  - Endpoint -> RAM
    *      ENDEPOUT[i] interrupted, transaction complete, sw prepare next transaction
    *
@@ -764,20 +767,16 @@ void dcd_int_handler(uint8_t rhport)
       xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
       uint8_t const xact_len = NRF_USBD->EPOUT[epnum].AMOUNT;
 
+      xfer->buffer     += xact_len;
+      xfer->actual_len += xact_len;
+
       // Transfer complete if transaction len < Max Packet Size or total len is transferred
       if ( (epnum != EP_ISO_NUM) && (xact_len == xfer->mps) && (xfer->actual_len < xfer->total_len) )
       {
         if ( epnum == 0 )
         {
           // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA
-          if ( _dcd.dma_pending )
-          {
-            // use usbd task to defer later
-            usbd_defer_func((osal_task_func_t) start_ep0_task, (void*) (uintptr_t) &NRF_USBD->TASKS_EP0RCVOUT, true);
-          }else
-          {
-            start_ep0_task(&NRF_USBD->TASKS_EP0RCVOUT);
-          }
+          edpt_dma_start(&NRF_USBD->TASKS_EP0RCVOUT);
         }else
         {
           // nRF auto accept next Bulk/Interrupt OUT packet
@@ -814,8 +813,10 @@ void dcd_int_handler(uint8_t rhport)
       if ( tu_bit_test(data_status, epnum) || (epnum == 0 && is_control_in) )
       {
         xfer_td_t* xfer = get_td(epnum, TUSB_DIR_IN);
+        uint8_t const xact_len = NRF_USBD->EPIN[epnum].AMOUNT; // MAXCNT
 
-        xfer->actual_len += NRF_USBD->EPIN[epnum].MAXCNT;
+        xfer->buffer     += xact_len;
+        xfer->actual_len += xact_len;
 
         if ( xfer->actual_len < xfer->total_len )
         {
@@ -842,6 +843,7 @@ void dcd_int_handler(uint8_t rhport)
         }else
         {
           // Data overflow !!! Nah, nRF will auto accept next Bulk/Interrupt OUT packet
+          // If USBD is already queued this
           // Mark this endpoint with data received
           xfer->data_received = true;
         }

From 0fc11746c0e6d9f64750e02d1d46d901c11e0373 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 23 Nov 2021 09:46:45 +0700
Subject: [PATCH 0675/2085] clean up

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index b10a29083..bee9fc0b6 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -217,9 +217,6 @@ static void xact_out_dma(uint8_t epnum)
 
     edpt_dma_start(&NRF_USBD->TASKS_STARTEPOUT[epnum]);
   }
-
-//  xfer->buffer     += xact_len;
-//  xfer->actual_len += xact_len;
 }
 
 // Prepare for a CBI transaction IN, call at the start
@@ -234,8 +231,6 @@ static void xact_in_dma(uint8_t epnum)
   NRF_USBD->EPIN[epnum].PTR    = (uint32_t) xfer->buffer;
   NRF_USBD->EPIN[epnum].MAXCNT = xact_len;
 
-  //xfer->buffer += xact_len;
-
   edpt_dma_start(&NRF_USBD->TASKS_STARTEPIN[epnum]);
 }
 
@@ -813,7 +808,7 @@ void dcd_int_handler(uint8_t rhport)
       if ( tu_bit_test(data_status, epnum) || (epnum == 0 && is_control_in) )
       {
         xfer_td_t* xfer = get_td(epnum, TUSB_DIR_IN);
-        uint8_t const xact_len = NRF_USBD->EPIN[epnum].AMOUNT; // MAXCNT
+        uint8_t const xact_len = NRF_USBD->EPIN[epnum].AMOUNT;
 
         xfer->buffer     += xact_len;
         xfer->actual_len += xact_len;
@@ -843,7 +838,6 @@ void dcd_int_handler(uint8_t rhport)
         }else
         {
           // Data overflow !!! Nah, nRF will auto accept next Bulk/Interrupt OUT packet
-          // If USBD is already queued this
           // Mark this endpoint with data received
           xfer->data_received = true;
         }

From c9e9f4785f68c9f9e99c4832af8615847c5fae92 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 23 Nov 2021 09:52:11 +0700
Subject: [PATCH 0676/2085] more clean up

---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index bee9fc0b6..2bcd56b8a 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -82,9 +82,8 @@ static struct
   // +1 for ISO endpoints
   xfer_td_t xfer[EP_CBI_COUNT + 1][2];
 
-  // Number of pending DMA that is started but not handled yet by dcd_int_handler().
-  // Since nRF can only carry one DMA can run at a time, this value is normally be either 0 or 1.
-  volatile uint8_t dma_pending;
+  // nRF can only carry one DMA at a time, this is used to guard the access to EasyDMA
+  volatile bool dma_running;
 }_dcd;
 
 /*------------------------------------------------------------------*/
@@ -115,7 +114,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
 // helper to start DMA
 static void start_dma(volatile uint32_t* reg_startep)
 {
-  _dcd.dma_pending = true;
+  _dcd.dma_running = true;
 
   (*reg_startep) = 1;
   __ISB(); __DSB();
@@ -125,7 +124,7 @@ static void start_dma(volatile uint32_t* reg_startep)
   // Therefore dma_pending is corrected right away
   if ( (reg_startep == &NRF_USBD->TASKS_EP0STATUS) || (reg_startep == &NRF_USBD->TASKS_EP0RCVOUT) )
   {
-    _dcd.dma_pending = false;
+    _dcd.dma_running = false;
   }
 }
 
@@ -137,7 +136,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
   // Called in critical section i.e within USB ISR, or USB/Global interrupt disabled
   if ( is_in_isr() || __get_PRIMASK() || !NVIC_GetEnableIRQ(USBD_IRQn) )
   {
-    if (_dcd.dma_pending)
+    if (_dcd.dma_running)
     {
       //use usbd task to defer later
       usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true);
@@ -157,7 +156,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
       // use osal mutex to guard against multiple core MCUs such as nRF53
       dcd_int_disable(rhport);
 
-      if ( !_dcd.dma_pending )
+      if ( !_dcd.dma_running )
       {
         start_dma(reg_startep);
         started = true;
@@ -173,8 +172,8 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
 // DMA is complete
 static void edpt_dma_end(void)
 {
-  TU_ASSERT(_dcd.dma_pending, );
-  _dcd.dma_pending = false;
+  TU_ASSERT(_dcd.dma_running, );
+  _dcd.dma_running = false;
 }
 
 // helper getting td

From 225e7182707510bc57fb433271a41ccd13c55624 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 25 Nov 2021 17:20:51 +0100
Subject: [PATCH 0677/2085] Update iar project template.

---
 tools/iar_template.ipcf | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index b8e50a1d2..ba54fe057 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -41,7 +41,8 @@
 			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
 		</group>
 		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/net_device.c</path>
+			<path>$TUSB_DIR$/src/class/net/ecm_rndis_device.c</path>
+			<path>$TUSB_DIR$/src/class/net/ncm_device.c</path>
 		</group>
 		<group name="src/class/usbtmc">
 			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
@@ -58,6 +59,9 @@
 			<path>$TUSB_DIR$/src/host/usbh.c</path>
 			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
 		</group>
+		<group name="src/portable/synopsys/dwc2">
+			<path>$TUSB_DIR$/src/portable/synopsys/dwc2/dcd_dwc2.c</path>
+		</group>
 		<group name="src/portable/dialog/da146xx">
 			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
 		</group>
@@ -67,6 +71,9 @@
 		<group name="src/portable/espressif/esp32sx">
 			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
 		</group>
+		<group name="src/portable/mentor/musb">
+			<path>$TUSB_DIR$/src/portable/mentor/musb/dcd_musb.c</path>
+		</group>
 		<group name="src/portable/microchip/samd">
 			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
 		</group>
@@ -116,21 +123,12 @@
 		<group name="src/portable/renesas/usba">
 			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
 		</group>
-		<group name="src/portable/silabs/efm32">
-			<path>$TUSB_DIR$/src/portable/silabs/efm32/dcd_efm32.c</path>
-		</group>
 		<group name="src/portable/sony/cxd56">
 			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
 		</group>
 		<group name="src/portable/st/stm32_fsdev">
 			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
 		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
-		<group name="src/portable/template">
-			<path>$TUSB_DIR$/src/portable/template/dcd_template.c</path>
-		</group>
 		<group name="src/portable/ti/msp430x5xx">
 			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
 		</group>

From 7413b6b02074d806ee2290b53c46ceaa3e76ef42 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 27 Nov 2021 10:25:39 +0900
Subject: [PATCH 0678/2085] Add a compile condition for dcd

---
 src/portable/mentor/musb/dcd_musb.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 4b4c2f9b2..0464eea19 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -26,7 +26,8 @@
 
 #include "tusb_option.h"
 
-#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+#if TUSB_OPT_DEVICE_ENABLED && \
+  TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
 
 #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
 /* GCC warns that an address may be unaligned, even though

From b50cf856b323c4948883a9834d289fe5dd7f67ff Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 28 Nov 2021 16:49:27 +0900
Subject: [PATCH 0679/2085] Add hcd_musb.c

---
 src/portable/mentor/musb/hcd_musb.c | 858 ++++++++++++++++++++++++++++
 1 file changed, 858 insertions(+)
 create mode 100644 src/portable/mentor/musb/hcd_musb.c

diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
new file mode 100644
index 000000000..b4931a793
--- /dev/null
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -0,0 +1,858 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Koji KITAYAMA
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_HOST_ENABLED && \
+  TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+
+#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
+/* GCC warns that an address may be unaligned, even though
+ * the target CPU has the capability for unaligned memory access. */
+_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\"");
+#endif
+
+#include "host/hcd.h"
+
+#if TU_CHECK_MCU(OPT_MCU_MSP432E4)
+  #include "musb_msp432e.h"
+
+#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129)
+  #include "musb_tm4c.h"
+
+  // HACK generalize later
+  #include "musb_type.h"
+  #define FIFO0_WORD FIFO0
+
+#else
+  #error "Unsupported MCUs"
+#endif
+
+#ifndef HCD_ATTR_ENDPOINT_MAX
+# define HCD_ATTR_ENDPOINT_MAX 8
+#endif
+
+/*------------------------------------------------------------------
+ * MACRO TYPEDEF CONSTANT ENUM DECLARATION
+ *------------------------------------------------------------------*/
+#define REQUEST_TYPE_INVALID  (0xFFu)
+
+typedef struct {
+  uint_fast16_t beg; /* offset of including first element */
+  uint_fast16_t end; /* offset of excluding the last element */
+} free_block_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t TXFUNCADDR;
+  uint8_t RESERVED0;
+  uint8_t TXHUBADDR;
+  uint8_t TXHUBPORT;
+  uint8_t RXFUNCADDR;
+  uint8_t RESERVED1;
+  uint8_t RXHUBADDR;
+  uint8_t RXHUBPORT;
+} hw_addr_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint16_t TXMAXP;
+  uint8_t  TXCSRL;
+  uint8_t  TXCSRH;
+  uint16_t RXMAXP;
+  uint8_t  RXCSRL;
+  uint8_t  RXCSRH;
+  uint16_t RXCOUNT;
+  uint8_t  TXTYPE;
+  uint8_t  TXINTERVAL;
+  uint8_t  RXTYPE;
+  uint8_t  RXINTERVAL;
+  uint16_t RESERVED;
+} hw_endpoint_t;
+
+typedef union {
+  uint8_t   u8;
+  uint16_t  u16;
+  uint32_t  u32;
+} hw_fifo_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  void      *buf;      /* the start address of a transfer data buffer */
+  uint16_t  length;    /* the number of bytes in the buffer */
+  uint16_t  remaining; /* the number of bytes remaining in the buffer */
+} pipe_state_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  uint8_t dev;
+  uint8_t ep;
+} pipe_addr_t;
+
+typedef struct
+{
+  bool         need_reset;     /* The device has not been reset after connection. */
+  uint8_t      bmRequestType;
+  uint8_t      ctl_mps[7]; /* EP0 max packet size for each device */
+  pipe_state_t pipe0;
+  pipe_state_t pipe[7][2];   /* pipe[pipe number - 1][direction 0:RX 1:TX] */
+  pipe_addr_t  addr[7][2];   /* addr[pipe number - 1][direction 0:RX 1:TX] */
+} hcd_data_t;
+
+/*------------------------------------------------------------------
+ * INTERNAL OBJECT & FUNCTION DECLARATION
+ *------------------------------------------------------------------*/
+static hcd_data_t _hcd;
+
+static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr)
+{
+  free_block_t *cur = beg;
+  for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ;
+  return cur;
+}
+
+static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size)
+{
+  free_block_t *p = find_containing_block(blks, blks + num, addr);
+  TU_ASSERT(p != blks + num, -2);
+  if (p->beg == addr) {
+    /* Shrink block */
+    p->beg = addr + size;
+    if (p->beg != p->end) return 0;
+    /* remove block */
+    free_block_t *end = blks + num;
+    while (p + 1 < end) {
+      *p = *(p + 1);
+      ++p;
+    }
+    return -1;
+  } else {
+    /* Split into 2 blocks */
+    free_block_t tmp = {
+      .beg = addr + size,
+      .end = p->end
+    };
+    p->end = addr;
+    if (p->beg == p->end) {
+      if (tmp.beg != tmp.end) {
+        *p = tmp;
+        return 0;
+      }
+      /* remove block */
+      free_block_t *end = blks + num;
+      while (p + 1 < end) {
+        *p = *(p + 1);
+        ++p;
+      }
+      return -1;
+    }
+    if (tmp.beg == tmp.end) return 0;
+    blks[num] = tmp;
+    return 1;
+  }
+}
+
+static inline unsigned free_block_size(free_block_t const *blk)
+{
+  return blk->end - blk->beg;
+}
+
+static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
+{
+  free_block_t free_blocks[2 * (HCD_ATTR_ENDPOINT_MAX - 1)];
+  unsigned num_blocks = 1;
+
+  /* Initialize free memory block list */
+  free_blocks[0].beg = 64 / 8;
+  free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */
+  for (int i = 1; i < HCD_ATTR_ENDPOINT_MAX; ++i) {
+    uint_fast16_t addr;
+    int num;
+    USB0->EPIDX = i;
+    addr = USB0->TXFIFOADD;
+    if (addr) {
+      unsigned sz  = USB0->TXFIFOSZ;
+      unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0);
+      num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
+      TU_ASSERT(-2 < num, 0);
+      num_blocks += num;
+    }
+    addr = USB0->RXFIFOADD;
+    if (addr) {
+      unsigned sz  = USB0->RXFIFOSZ;
+      unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0);
+      num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
+      TU_ASSERT(-2 < num, 0);
+      num_blocks += num;
+    }
+  }
+
+  /* Find the best fit memory block */
+  uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3;
+  free_block_t const *min = NULL;
+  uint_fast16_t    min_sz = 0xFFFFu;
+  free_block_t const *end = &free_blocks[num_blocks];
+  for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) {
+    uint_fast16_t sz = free_block_size(cur);
+    if (sz < size_in_8byte_unit) continue;
+    if (size_in_8byte_unit == sz) return cur->beg;
+    if (sz < min_sz) min = cur;
+  }
+  TU_ASSERT(min, 0);
+  return min->beg;
+}
+
+static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1)
+{
+  volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1);
+  return regs + epnum_minus1;
+}
+
+static unsigned find_pipe(uint_fast8_t dev_addr, uint_fast8_t ep_addr)
+{
+  unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1;
+  pipe_addr_t const *p = &_hcd.addr[0][dir_tx];
+  for (unsigned i = 0; i < sizeof(_hcd.addr)/sizeof(_hcd.addr[0]); ++i, p += 2) {
+    if ((dev_addr == p->dev) && (ep_addr == p->ep))
+      return i + 1;
+  }
+  return 0;
+}
+
+static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
+{
+  volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
+  uintptr_t addr = (uintptr_t)buf;
+  while (len >= 4) {
+    reg->u32 = *(uint32_t const *)addr;
+    addr += 4;
+    len  -= 4;
+  }
+  if (len >= 2) {
+    reg->u16 = *(uint16_t const *)addr;
+    addr += 2;
+    len  -= 2;
+  }
+  if (len) {
+    reg->u8 = *(uint8_t const *)addr;
+  }
+}
+
+static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
+{
+  volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
+  uintptr_t addr = (uintptr_t)buf;
+  while (len >= 4) {
+    *(uint32_t *)addr = reg->u32;
+    addr += 4;
+    len  -= 4;
+  }
+  if (len >= 2) {
+    *(uint32_t *)addr = reg->u16;
+    addr += 2;
+    len  -= 2;
+  }
+  if (len) {
+    *(uint32_t *)addr = reg->u8;
+  }
+}
+
+static bool edpt0_xfer_out(void)
+{
+  pipe_state_t *pipe = &_hcd.pipe0;
+  unsigned const rem = pipe->remaining;
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+  unsigned const dev_addr = USB0->TXFUNCADDR0;
+  unsigned const mps = _hcd.ctl_mps[dev_addr];
+  unsigned const len = TU_MIN(rem, mps);
+  void          *buf = pipe->buf;
+  if (len) {
+    pipe_write_packet(buf, &USB0->FIFO0_WORD, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  pipe->remaining = rem - len;
+  USB0->CSRL0 = USB_CSRL0_TXRDY;
+  return false;
+}
+
+static bool edpt0_xfer_in(void)
+{
+  pipe_state_t *pipe = &_hcd.pipe0;
+  unsigned const rem = pipe->remaining;
+  unsigned const dev_addr = USB0->TXFUNCADDR0;
+  unsigned const mps = _hcd.ctl_mps[dev_addr];
+  unsigned const vld = USB0->COUNT0;
+  unsigned const len = TU_MIN(TU_MIN(rem, mps), vld);
+  void          *buf = pipe->buf;
+  if (len) {
+    pipe_read_packet(buf, &USB0->FIFO0_WORD, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  pipe->remaining = rem - len;
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return true;
+  }
+  USB0->CSRL0 = USB_CSRL0_REQPKT;
+  return false;
+}
+
+static bool edpt0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
+{
+  (void)rhport;
+
+  const unsigned req = _hcd.bmRequestType;
+  TU_ASSERT(req != REQUEST_TYPE_INVALID);
+  TU_ASSERT(dev_addr < sizeof(_hcd.ctl_mps));
+
+  USB0->TXFUNCADDR0 = dev_addr;
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+  if (tu_edpt_dir(req) == dir_in) { /* DATA stage */
+    TU_ASSERT(buffer);
+    _hcd.pipe0.buf       = buffer;
+    _hcd.pipe0.length    = buflen;
+    _hcd.pipe0.remaining = buflen;
+    if (dir_in)
+      USB0->CSRL0 = USB_CSRL0_REQPKT;
+    else
+      edpt0_xfer_out();
+  } else { /* STATUS stage */
+    _hcd.pipe0.buf       = NULL;
+    _hcd.pipe0.length    = 0;
+    _hcd.pipe0.remaining = 0;
+    USB0->CSRL0 = USB_CSRL0_STATUS | (dir_in ? USB_CSRL0_REQPKT: USB_CSRL0_TXRDY);
+  }
+  return true;
+}
+
+static bool pipe_xfer_out(uint_fast8_t pipenum)
+{
+  pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][1];
+  unsigned const rem = pipe->remaining;
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+  hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1);
+  unsigned const mps = regs->TXMAXP;
+  unsigned const len = TU_MIN(rem, mps);
+  void          *buf = pipe->buf;
+  if (len) {
+    pipe_write_packet(buf, &USB0->FIFO0_WORD + pipenum, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  pipe->remaining = rem - len;
+  regs->TXCSRL = USB_TXCSRL1_TXRDY;
+  return false;
+}
+
+static bool pipe_xfer_in(uint_fast8_t pipenum)
+{
+  pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][0];
+  volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
+
+  TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY);
+
+  const unsigned mps = regs->RXMAXP;
+  const unsigned rem = pipe->remaining;
+  const unsigned vld = regs->RXCOUNT;
+  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
+  void          *buf = pipe->buf;
+  if (len) {
+    pipe_read_packet(buf, &USB0->FIFO0_WORD + pipenum, len);
+    pipe->buf       = buf + len;
+    pipe->remaining = rem - len;
+  }
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return NULL != buf;
+  }
+  regs->RXCSRL = USB_RXCSRL1_REQPKT;
+  return false;
+}
+
+static bool edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
+{
+  (void)rhport;
+  unsigned const pipenum = find_pipe(dev_addr, ep_addr);
+  unsigned const dir_tx  = tu_edpt_dir(ep_addr) ? 0: 1;
+  pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][dir_tx];
+  pipe->buf          = buffer;
+  pipe->length       = buflen;
+  pipe->remaining    = buflen;
+  if (dir_tx) {
+    pipe_xfer_out(pipenum);
+  } else {
+    volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
+    regs->RXCSRL = USB_RXCSRL1_REQPKT;
+  }
+  return true;
+}
+
+static void process_ep0(uint8_t rhport)
+{
+  (void)rhport;
+
+  uint_fast8_t csrl = USB0->CSRL0;
+  // TU_LOG1(" EP0 CSRL = %x\n", csrl);
+
+  unsigned const dev_addr = USB0->TXFUNCADDR0;
+  unsigned const req = _hcd.bmRequestType;
+  if (csrl & (USB_CSRL0_ERROR | USB_CSRL0_NAKTO | USB_CSRL0_STALLED)) {
+    /* No response / NAK timed out / Stall received */
+    if (csrl & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY))
+      USB0->CSRH0 = USB_CSRH0_FLUSH;
+    USB0->CSRL0 = 0;
+    _hcd.bmRequestType = REQUEST_TYPE_INVALID;
+    uint8_t result = (csrl & USB_CSRL0_STALLED) ? XFER_RESULT_STALLED: XFER_RESULT_FAILED;
+    if (REQUEST_TYPE_INVALID == req) { /* SETUP */
+      uint8_t const ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT);
+      hcd_event_xfer_complete(dev_addr, ep_addr,
+                              _hcd.pipe0.length - _hcd.pipe0.remaining,
+                              result, true);
+    } else if (csrl & USB_CSRL0_STATUS) { /* STATUS */
+      uint8_t const ep_addr = tu_edpt_dir(req) ?
+        tu_edpt_addr(0, TUSB_DIR_OUT): tu_edpt_addr(0, TUSB_DIR_IN);
+      hcd_event_xfer_complete(dev_addr, ep_addr,
+                              _hcd.pipe0.length - _hcd.pipe0.remaining,
+                              result, true);
+    } else { /* DATA */
+      uint8_t const ep_addr = tu_edpt_dir(req) ?
+        tu_edpt_addr(0, TUSB_DIR_IN): tu_edpt_addr(0, TUSB_DIR_OUT);
+      hcd_event_xfer_complete(dev_addr, ep_addr,
+                              _hcd.pipe0.length - _hcd.pipe0.remaining,
+                              result, true);
+    }
+    return;
+  }
+  if (csrl & USB_CSRL0_STATUS) {
+    /* STATUS IN */
+    TU_ASSERT(USB_CSRL0_RXRDY == (csrl & USB_CSRL0_RXRDY),);
+    TU_ASSERT(0 == USB0->COUNT0,);
+    USB0->CSRL0 = 0;
+    _hcd.bmRequestType = REQUEST_TYPE_INVALID;
+    hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_IN),
+                            0, XFER_RESULT_SUCCESS, true);
+    return;
+  }
+  if (csrl & USB_CSRL0_RXRDY) {
+    /* DATA IN */
+    TU_ASSERT(REQUEST_TYPE_INVALID != req,);
+    TU_ASSERT(_hcd.pipe0.buf,);
+    if (edpt0_xfer_in()) {
+      hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_IN),
+                              _hcd.pipe0.length - _hcd.pipe0.remaining,
+                              XFER_RESULT_SUCCESS, true);
+    }
+    return;
+  }
+
+  /* When CSRL0 is zero, it means that completion of sending a any length packet. */
+  if (!_hcd.pipe0.buf) {
+    /* STATUS OUT */
+    TU_ASSERT(REQUEST_TYPE_INVALID != req,);
+    _hcd.bmRequestType = REQUEST_TYPE_INVALID;
+    /* EP address is the reverse direction of DATA stage */
+    uint8_t const ep_addr = tu_edpt_dir(req) ?
+      tu_edpt_addr(0, TUSB_DIR_OUT): tu_edpt_addr(0, TUSB_DIR_IN);
+    hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_SUCCESS, true);
+    return;
+  }
+  if (REQUEST_TYPE_INVALID == req) {
+    /* SETUP */
+    _hcd.bmRequestType = *(uint8_t*)_hcd.pipe0.buf;
+    _hcd.pipe0.buf = NULL;
+    hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_OUT),
+                            8, XFER_RESULT_SUCCESS, true);
+    return;
+  }
+
+  /* DATA OUT */
+  if (edpt0_xfer_out()) {
+    hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_OUT),
+                            _hcd.pipe0.length - _hcd.pipe0.remaining,
+                            XFER_RESULT_SUCCESS, true);
+  }
+}
+
+static void process_pipe_tx(uint8_t rhport, uint_fast8_t pipenum)
+{
+  (void)rhport;
+  bool completed;
+  uint8_t result;
+
+  volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
+  unsigned const csrl = regs->TXCSRL;
+  // TU_LOG1(" TXCSRL%d = %x\n", pipenum, csrl);
+  if (csrl & (USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) {
+    if (csrl & USB_TXCSRL1_TXRDY)
+      regs->TXCSRL = (csrl & ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) | USB_TXCSRL1_FLUSH;
+    else
+      regs->TXCSRL = csrl & ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR);
+    completed = true;
+    result    = (csrl & USB_TXCSRL1_STALLED) ? XFER_RESULT_STALLED: XFER_RESULT_FAILED;
+  } else {
+    completed = pipe_xfer_out(pipenum);
+    result    = XFER_RESULT_SUCCESS;
+  }
+  if (completed) {
+    pipe_addr_t  *addr = &_hcd.addr[pipenum - 1][1];
+    pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][1];
+    hcd_event_xfer_complete(addr->dev, addr->ep,
+                            pipe->length - pipe->remaining,
+                            result, true);
+  }
+}
+
+static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum)
+{
+  (void)rhport;
+  bool completed;
+  uint8_t result;
+
+  volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
+  unsigned const csrl = regs->RXCSRL;
+  // TU_LOG1(" RXCSRL%d = %x\n", pipenum, csrl);
+  if (csrl & (USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) {
+    if (csrl & USB_RXCSRL1_RXRDY)
+      regs->RXCSRL = (csrl & ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) | USB_RXCSRL1_FLUSH;
+    else
+      regs->RXCSRL = csrl & ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR);
+    completed = true;
+    result    = (csrl & USB_RXCSRL1_STALLED) ? XFER_RESULT_STALLED: XFER_RESULT_FAILED;
+  } else {
+    completed = pipe_xfer_in(pipenum);
+    result    = XFER_RESULT_SUCCESS;
+  }
+  if (completed) {
+    pipe_addr_t  *addr = &_hcd.addr[pipenum - 1][0];
+    pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][0];
+    hcd_event_xfer_complete(addr->dev, addr->ep,
+                            pipe->length - pipe->remaining,
+                            result, true);
+  }
+}
+
+/*------------------------------------------------------------------
+ * Host API
+ *------------------------------------------------------------------*/
+
+bool hcd_init(uint8_t rhport)
+{
+  (void)rhport;
+
+  NVIC_ClearPendingIRQ(USB0_IRQn);
+  _hcd.bmRequestType = REQUEST_TYPE_INVALID;
+  USB0->DEVCTL |= USB_DEVCTL_SESSION;
+  USB0->IE = USB_IE_DISCON | USB_IE_CONN | USB_IE_BABBLE | USB_IE_RESUME;
+  return true;
+}
+
+void hcd_int_enable(uint8_t rhport)
+{
+  (void)rhport;
+  NVIC_EnableIRQ(USB0_IRQn);
+}
+
+void hcd_int_disable(uint8_t rhport)
+{
+  (void)rhport;
+  NVIC_DisableIRQ(USB0_IRQn);
+}
+
+uint32_t hcd_frame_number(uint8_t rhport)
+{
+  (void)rhport;
+  /* The device must be reset at least once after connection 
+   * in order to start the frame counter. */
+  if (_hcd.need_reset) hcd_port_reset(rhport);
+  return USB0->FRAME;
+}
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+bool hcd_port_connect_status(uint8_t rhport)
+{
+  (void)rhport;
+  unsigned devctl = USB0->DEVCTL;
+  if (!(devctl & USB_DEVCTL_HOST)) return false;
+  if (devctl & (USB_DEVCTL_LSDEV | USB_DEVCTL_FSDEV)) return true;
+  return false;
+}
+
+void hcd_port_reset(uint8_t rhport)
+{
+  (void)rhport;
+  USB0->POWER |= USB_POWER_HSENAB | USB_POWER_RESET;
+  unsigned cnt = SystemCoreClock / 1000 * 20;
+  while (cnt--) __NOP();
+  USB0->POWER &= ~USB_POWER_RESET;
+  _hcd.need_reset = false;
+}
+
+tusb_speed_t hcd_port_speed_get(uint8_t rhport)
+{
+  (void)rhport;
+  unsigned devctl = USB0->DEVCTL;
+  if (devctl & USB_DEVCTL_LSDEV)      return TUSB_SPEED_LOW;
+  if (!(devctl & USB_DEVCTL_FSDEV))   return TUSB_SPEED_INVALID;
+  if (USB0->POWER & USB_POWER_HSMODE) return TUSB_SPEED_HIGH;
+  return TUSB_SPEED_FULL;
+}
+
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
+{
+  (void)rhport;
+  if (sizeof(_hcd.ctl_mps) <= dev_addr) return;
+
+  unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  _hcd.ctl_mps[dev_addr] = 0;
+  if (!dev_addr) return;
+
+  pipe_addr_t *p = &_hcd.addr[0][0];
+  for (unsigned i = 0; i < sizeof(_hcd.addr)/sizeof(_hcd.addr[0]); ++i) {
+    for (unsigned j = 0; j < 2; ++j, ++p) {
+      if (dev_addr != p->dev) continue;
+      hw_addr_t volatile     *fadr = (hw_addr_t volatile*)&USB0->TXFUNCADDR0 + i + 1;
+      hw_endpoint_t volatile *regs = edpt_regs(i);
+      USB0->EPIDX = i + 1;
+      if (j) {
+        USB0->TXIE      &= ~TU_BIT(i + 1);
+        if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
+          regs->TXCSRL   = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
+        else
+          regs->TXCSRL   = USB_TXCSRL1_CLRDT;
+        regs->TXMAXP     = 0;
+        regs->TXTYPE     = 0;
+        regs->TXINTERVAL = 0;
+        fadr->TXFUNCADDR = 0;
+        fadr->TXHUBADDR  = 0;
+        fadr->TXHUBPORT  = 0;
+        USB0->TXFIFOADD  = 0;
+        USB0->TXFIFOSZ   = 0;
+      } else {
+        USB0->RXIE      &= ~TU_BIT(i + 1);
+        if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
+          regs->RXCSRL   = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
+        else
+          regs->RXCSRL   = USB_RXCSRL1_CLRDT;
+        regs->RXMAXP     = 0;
+        regs->RXTYPE     = 0;
+        regs->RXINTERVAL = 0;
+        fadr->RXFUNCADDR = 0;
+        fadr->RXHUBADDR  = 0;
+        fadr->RXHUBPORT  = 0;
+        USB0->RXFIFOADD  = 0;
+        USB0->RXFIFOSZ   = 0;
+      }
+      p->dev = 0;
+      p->ep  = 0;
+      pipe_state_t *pipe = &_hcd.pipe[i][j];
+      pipe->buf       = NULL;
+      pipe->length    = 0;
+      pipe->remaining = 0;
+    }
+  }
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
+{
+  (void)rhport;
+  pipe_write_packet((void*)(uintptr_t)setup_packet, &USB0->FIFO0_WORD, 8);
+  _hcd.pipe0.buf       = (void*)(uintptr_t)setup_packet;
+  _hcd.pipe0.length    = 8;
+  _hcd.pipe0.remaining = 0;
+  _hcd.bmRequestType   = REQUEST_TYPE_INVALID;
+  USB0->TXFUNCADDR0    = dev_addr;
+  USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_SETUP;
+  return true;
+}
+
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
+{
+  if (sizeof(_hcd.ctl_mps) <= dev_addr) return false;
+  unsigned const ep_addr = ep_desc->bEndpointAddress;
+  unsigned const epn     = tu_edpt_number(ep_addr);
+  if (0 == epn) {
+    _hcd.ctl_mps[dev_addr] = ep_desc->wMaxPacketSize;
+    return true;
+  }
+
+  unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1;
+  /* Find a free pipe */
+  unsigned pipenum = 0;
+  pipe_addr_t *p = &_hcd.addr[0][dir_tx];
+  for (unsigned i = 0; i < sizeof(_hcd.addr)/sizeof(_hcd.addr[0]); ++i, p += 2) {
+    if (0 == p->ep) {
+      p->dev  = dev_addr;
+      p->ep   = ep_addr;
+      pipenum = i + 1;
+      break;
+    }
+  }
+  if (!pipenum) return false;
+
+  unsigned const xfer = ep_desc->bmAttributes.xfer;
+  unsigned const mps  = tu_edpt_packet_size(ep_desc);
+
+  pipe_state_t *pipe = &_hcd.pipe[pipenum - 1][dir_tx];
+  pipe->buf       = NULL;
+  pipe->length    = 0;
+  pipe->remaining = 0;
+
+  uint8_t pipe_type = 0;
+  switch (hcd_port_speed_get(rhport)) {
+    default: return false;
+    case TUSB_SPEED_LOW:  pipe_type |= USB_TXTYPE1_SPEED_LOW;  break;
+    case TUSB_SPEED_FULL: pipe_type |= USB_TXTYPE1_SPEED_FULL; break;
+    case TUSB_SPEED_HIGH: pipe_type |= USB_TXTYPE1_SPEED_HIGH; break;
+  }
+  switch (xfer) {
+    default: return false;
+    case TUSB_XFER_BULK:        pipe_type |= USB_TXTYPE1_PROTO_BULK; break;
+    case TUSB_XFER_INTERRUPT:   pipe_type |= USB_TXTYPE1_PROTO_INT;  break;
+    case TUSB_XFER_ISOCHRONOUS: pipe_type |= USB_TXTYPE1_PROTO_ISOC; break;
+  }
+
+  hw_addr_t volatile     *fadr = (hw_addr_t volatile*)&USB0->TXFUNCADDR0 + pipenum;
+  hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1);
+  if (dir_tx) {
+    fadr->TXFUNCADDR = dev_addr;
+    regs->TXMAXP     = mps;
+    regs->TXTYPE     = pipe_type | epn;
+    regs->TXINTERVAL = ep_desc->bInterval;
+    if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
+      regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH;
+    else
+      regs->TXCSRL = USB_TXCSRL1_CLRDT;
+    USB0->TXIE |= TU_BIT(pipenum);
+  } else {
+    fadr->RXFUNCADDR = dev_addr;
+    regs->RXMAXP     = mps;
+    regs->RXTYPE     = pipe_type | epn;
+    regs->RXINTERVAL = ep_desc->bInterval;
+    if (regs->RXCSRL & USB_RXCSRL1_RXRDY)
+      regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH;
+    else
+      regs->RXCSRL = USB_RXCSRL1_CLRDT;
+    USB0->RXIE |= TU_BIT(pipenum);
+  }
+
+  /* Setup FIFO */
+  int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps));
+  if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3;
+  unsigned addr = find_free_memory(size_in_log2_minus3);
+  TU_ASSERT(addr);
+
+  USB0->EPIDX = pipenum;
+  if (dir_tx) {
+    USB0->TXFIFOADD = addr;
+    USB0->TXFIFOSZ  = size_in_log2_minus3;
+  } else {
+    USB0->RXFIFOADD = addr;
+    USB0->RXFIFOSZ  = size_in_log2_minus3;
+  }
+  return true;
+}
+
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
+{
+  (void)rhport;
+  bool ret = false;
+  if (0 == tu_edpt_number(ep_addr)) {
+    ret = edpt0_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
+  } else {
+    ret = edpt_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
+  }
+  return ret;
+}
+
+// clear stall, data toggle is also reset to DATA0
+bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
+{
+  unsigned const pipenum = find_pipe(dev_addr, ep_addr);
+  if (!pipenum) return false;
+  hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1);
+  unsigned const dir_tx = tu_edpt_dir(ep_addr) ? 0: 1;
+  if (dir_tx)
+    regs->TXCSRL = USB_TXCSRL1_CLRDT;
+  else
+    regs->RXCSRL = USB_RXCSRL1_CLRDT;
+  return true;
+}
+
+/*-------------------------------------------------------------------
+ * ISR
+ *-------------------------------------------------------------------*/
+void hcd_int_handler(uint8_t rhport)
+{
+  uint_fast8_t is, txis, rxis;
+
+  is   = USB0->IS;   /* read and clear interrupt status */
+  txis = USB0->TXIS; /* read and clear interrupt status */
+  rxis = USB0->RXIS; /* read and clear interrupt status */
+  // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis);
+
+  is &= USB0->IE; /* Clear disabled interrupts */
+  if (is & USB_IS_RESUME) {
+  }
+  if (is & USB_IS_CONN) {
+    _hcd.need_reset = true;
+    hcd_event_device_attach(rhport, true);
+  }
+  if (is & USB_IS_DISCON) {
+    hcd_event_device_remove(rhport, true);
+  }
+  if (is & USB_IS_BABBLE) {
+  }
+  txis &= USB0->TXIE; /* Clear disabled interrupts */
+  if (txis & USB_TXIE_EP0) {
+    process_ep0(rhport);
+    txis &= ~TU_BIT(0);
+  }
+  while (txis) {
+    unsigned const num = __builtin_ctz(txis);
+    process_pipe_tx(rhport, num);
+    txis &= ~TU_BIT(num);
+  }
+  rxis &= USB0->RXIE; /* Clear disabled interrupts */
+  while (rxis) {
+    unsigned const num = __builtin_ctz(rxis);
+    process_pipe_rx(rhport, num);
+    rxis &= ~TU_BIT(num);
+  }
+}
+
+#endif

From b3dddc77eb4527372640e1712c9e248b60dd8869 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 29 Nov 2021 00:40:23 +0900
Subject: [PATCH 0680/2085] Add initialization sequence as a HOST

---
 hw/bsp/msp432e4/family.c | 49 +++++++++++++++++++++++++++++++---------
 1 file changed, 38 insertions(+), 11 deletions(-)

diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index 7114da693..262dc1d30 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -33,7 +33,12 @@
 //--------------------------------------------------------------------+
 void USB0_IRQHandler(void)
 {
+#if TUSB_OPT_HOST_ENABLED
+  tuh_int_handler(0);
+#endif
+#if TUSB_OPT_DEVICE_ENABLED
   tud_int_handler(0);
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -42,6 +47,7 @@ void USB0_IRQHandler(void)
 
 void board_init(void)
 {
+  unsigned bits;
   /* Turn off power domains that unused peripherals belong to */
   SYSCTL->PCCAN  = 0u;
 #ifdef __MCU_HAS_LCD0__
@@ -80,20 +86,23 @@ void board_init(void)
 #endif
 
   /* USR_LED1 ON1 */
-  SYSCTL->RCGCGPIO |= TU_BIT(CLK_LED);
-  while (!(SYSCTL->PRGPIO & TU_BIT(CLK_LED))) ;
+  bits              = TU_BIT(CLK_LED);
+  SYSCTL->RCGCGPIO |= bits;
+  while (bits != (SYSCTL->RCGCGPIO & bits)) ;
   GPIO_LED->DIR     = TU_BIT(GPIO_LED_PIN);
   GPIO_LED->DEN     = TU_BIT(GPIO_LED_PIN);
 
   /* USR_SW1 PJ0 */
-  SYSCTL->RCGCGPIO |= TU_BIT(CLK_BUTTON);
-  while (!(SYSCTL->PRGPIO & TU_BIT(CLK_BUTTON))) ;
+  bits              = TU_BIT(CLK_BUTTON);
+  SYSCTL->RCGCGPIO |= bits;
+  while (bits != (SYSCTL->RCGCGPIO & bits)) ;
   GPIO_BUTTON->PUR  = TU_BIT(GPIO_BUTTON_PIN);
   GPIO_BUTTON->DEN  = TU_BIT(GPIO_BUTTON_PIN);
 
   /* UART PA0,1 */
-  SYSCTL->RCGCGPIO |= 1u << 0;
-  while (!(SYSCTL->PRGPIO & (1u << 0))) ;
+  bits              = TU_BIT(0);
+  SYSCTL->RCGCGPIO |= bits;
+  while (bits != (SYSCTL->RCGCGPIO & bits)) ;
   GPIOA->AFSEL      = 3u;
   GPIOA->PCTL       = 0x11u;
   GPIOA->DEN        = 3u;
@@ -107,11 +116,22 @@ void board_init(void)
   UART0->CC         = UART_CC_CS_PIOSC; /* Set the baud clock to PIOSC */
   UART0->CTL        = UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN;
 
-  /* USB PB1(VBUS) PL6,7(DP,DM) */
-  SYSCTL->RCGCGPIO |= (1u << 1) | (1u << 10);
-  while (((1u << 1) | (1u << 10)) != (SYSCTL->PRGPIO & ((1u << 1) | (1u << 10)))) ;
-  GPIOB->AMSEL      = 1u << 1;
-  GPIOL->AMSEL      = (1u << 6) | (1u << 7);
+  /* USB PB0(ID) PB1(VBUS) PL6,7(DP,DM) */
+  bits              = TU_BIT(1) | TU_BIT(10);
+  SYSCTL->RCGCGPIO |= bits;
+  while (bits != (SYSCTL->RCGCGPIO & bits)) ;
+  GPIOB->AMSEL      = TU_BIT(0) | TU_BIT(1);
+  GPIOL->AMSEL      = TU_BIT(6) | TU_BIT(7);
+
+#if TUSB_OPT_HOST_ENABLED
+  /* USB PD6(EPEN) */
+  bits              = TU_BIT(3);
+  SYSCTL->RCGCGPIO |= bits;
+  while (bits != (SYSCTL->RCGCGPIO & bits)) ;
+  GPIOD->AFSEL      = TU_BIT(6);
+  GPIOD->PCTL       = 0x05000000u;
+  GPIOD->DEN        = TU_BIT(6);
+#endif
 
   SYSCTL->RCGCUSB   = 1u; /* Open the clock gate for SYSCLK */
   while (!(SYSCTL->PRUSB & (1u << 0))) ;
@@ -124,6 +144,13 @@ void board_init(void)
 
   USB0->CC          = USB_CC_CLKEN | (3u << USB_CC_CLKDIV_S); /* 60MHz = 240MHz / 4 */
   __DMB(); /* Wait for completion of opening of the clock gate */
+#if TUSB_OPT_HOST_ENABLED
+  USB0->GPCS = USB_GPCS_DEVMOD_OTG;
+  USB0->EPC  = USB_EPC_EPENDE | USB_EPC_EPEN_HIGH;
+#endif
+#if TUSB_OPT_DEVICE_ENABLED
+  USB0->GPCS = USB_GPCS_DEVMOD_DEVVBUS;
+#endif
 }
 
 //--------------------------------------------------------------------+

From ae9a39ec1fec596a7578a137a392b48cdab5ac39 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 29 Nov 2021 00:42:18 +0900
Subject: [PATCH 0681/2085] Add musb driver

---
 examples/host/cdc_msc_hid/Makefile    | 3 ++-
 examples/host/hid_controller/Makefile | 5 +++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index 0ad9dd856..fd68a7849 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -23,6 +23,7 @@ SRC_C += \
 	src/portable/ehci/ehci.c \
 	src/portable/ohci/ohci.c \
 	src/portable/nxp/transdimension/hcd_transdimension.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
+	src/portable/mentor/musb/hcd_musb.c
 
 include ../../rules.mk
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index 2595ec4a7..776cfcb88 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -9,7 +9,7 @@ INC += \
 EXAMPLE_SOURCE += \
 	src/hid_app.c \
 	src/main.c
-	
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 # TODO: suppress warning caused by host stack
@@ -26,6 +26,7 @@ SRC_C += \
 	src/portable/ehci/ehci.c \
 	src/portable/ohci/ohci.c \
 	src/portable/nxp/transdimension/hcd_transdimension.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
+	src/portable/mentor/musb/hcd_musb.c
 
 include ../../rules.mk

From 24614de419f5a7c5871bf6bbd78ec4d01bdca31b Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 29 Nov 2021 00:45:57 +0900
Subject: [PATCH 0682/2085] Fix build errors

---
 examples/host/hid_controller/src/hid_app.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index bbfea8182..582e01959 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -138,6 +138,8 @@ void hid_app_task(void)
 // therefore report_desc = NULL, desc_len = 0
 void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
 {
+  (void)desc_report;
+  (void)desc_len;
   uint16_t vid, pid;
   tuh_vid_pid_get(dev_addr, &vid, &pid);
 

From ab223eb1df187b0fd845fec17b6bf5365216e4f2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 29 Nov 2021 13:07:46 +0700
Subject: [PATCH 0683/2085] correct 32 button in gamepad hid descriptor
 template

---
 src/class/hid/hid_device.h | 64 +++++++++++++++++++-------------------
 1 file changed, 32 insertions(+), 32 deletions(-)

diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 7f67fa9cf..078b67349 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -310,8 +310,8 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
   HID_COLLECTION_END \
 
 // Gamepad Report Descriptor Template
-// with 16 buttons, 2 joysticks and 1 hat/dpad with following layout
-// | X | Y | Z | Rz | Rx | Ry (1 byte each) | hat/DPAD (1 byte) | Button Map (2 bytes) |
+// with 32 buttons, 2 joysticks and 1 hat/dpad with following layout
+// | X | Y | Z | Rz | Rx | Ry (1 byte each) | hat/DPAD (1 byte) | Button Map (4 bytes) |
 #define TUD_HID_REPORT_DESC_GAMEPAD(...) \
   HID_USAGE_PAGE ( HID_USAGE_PAGE_DESKTOP     )                 ,\
   HID_USAGE      ( HID_USAGE_DESKTOP_GAMEPAD  )                 ,\
@@ -319,37 +319,37 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     /* Report ID if any */\
     __VA_ARGS__ \
     /* 8 bit X, Y, Z, Rz, Rx, Ry (min -127, max 127 ) */ \
-    HID_USAGE_PAGE   ( HID_USAGE_PAGE_DESKTOP                 ) ,\
-    HID_USAGE        ( HID_USAGE_DESKTOP_X                    ) ,\
-    HID_USAGE        ( HID_USAGE_DESKTOP_Y                    ) ,\
-    HID_USAGE        ( HID_USAGE_DESKTOP_Z                    ) ,\
-    HID_USAGE        ( HID_USAGE_DESKTOP_RZ                   ) ,\
-    HID_USAGE        ( HID_USAGE_DESKTOP_RX                   ) ,\
-    HID_USAGE        ( HID_USAGE_DESKTOP_RY                   ) ,\
-    HID_LOGICAL_MIN  ( 0x81                                   ) ,\
-    HID_LOGICAL_MAX  ( 0x7f                                   ) ,\
-    HID_REPORT_COUNT ( 6                                      ) ,\
-    HID_REPORT_SIZE  ( 8                                      ) ,\
-    HID_INPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+    HID_USAGE_PAGE     ( HID_USAGE_PAGE_DESKTOP                 ) ,\
+    HID_USAGE          ( HID_USAGE_DESKTOP_X                    ) ,\
+    HID_USAGE          ( HID_USAGE_DESKTOP_Y                    ) ,\
+    HID_USAGE          ( HID_USAGE_DESKTOP_Z                    ) ,\
+    HID_USAGE          ( HID_USAGE_DESKTOP_RZ                   ) ,\
+    HID_USAGE          ( HID_USAGE_DESKTOP_RX                   ) ,\
+    HID_USAGE          ( HID_USAGE_DESKTOP_RY                   ) ,\
+    HID_LOGICAL_MIN    ( 0x81                                   ) ,\
+    HID_LOGICAL_MAX    ( 0x7f                                   ) ,\
+    HID_REPORT_COUNT   ( 6                                      ) ,\
+    HID_REPORT_SIZE    ( 8                                      ) ,\
+    HID_INPUT          ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
     /* 8 bit DPad/Hat Button Map  */ \
-    HID_USAGE_PAGE   ( HID_USAGE_PAGE_DESKTOP                 ) ,\
-    HID_USAGE        ( HID_USAGE_DESKTOP_HAT_SWITCH           ) ,\
-    HID_LOGICAL_MIN  ( 1                                      ) ,\
-    HID_LOGICAL_MAX  ( 8                                      ) ,\
-    HID_PHYSICAL_MIN ( 0                                      ) ,\
-    HID_PHYSICAL_MAX_N ( 315, 2                               ) ,\
-    HID_REPORT_COUNT ( 1                                      ) ,\
-    HID_REPORT_SIZE  ( 8                                      ) ,\
-    HID_INPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
-    /* 16 bit Button Map */ \
-    HID_USAGE_PAGE   ( HID_USAGE_PAGE_BUTTON                  ) ,\
-    HID_USAGE_MIN    ( 1                                      ) ,\
-    HID_USAGE_MAX    ( 32                                     ) ,\
-    HID_LOGICAL_MIN  ( 0                                      ) ,\
-    HID_LOGICAL_MAX  ( 1                                      ) ,\
-    HID_REPORT_COUNT ( 32                                     ) ,\
-    HID_REPORT_SIZE  ( 1                                      ) ,\
-    HID_INPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+    HID_USAGE_PAGE     ( HID_USAGE_PAGE_DESKTOP                 ) ,\
+    HID_USAGE          ( HID_USAGE_DESKTOP_HAT_SWITCH           ) ,\
+    HID_LOGICAL_MIN    ( 1                                      ) ,\
+    HID_LOGICAL_MAX    ( 8                                      ) ,\
+    HID_PHYSICAL_MIN   ( 0                                      ) ,\
+    HID_PHYSICAL_MAX_N ( 315, 2                                 ) ,\
+    HID_REPORT_COUNT   ( 1                                      ) ,\
+    HID_REPORT_SIZE    ( 8                                      ) ,\
+    HID_INPUT          ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+    /* 32 bit Button Map */ \
+    HID_USAGE_PAGE     ( HID_USAGE_PAGE_BUTTON                  ) ,\
+    HID_USAGE_MIN      ( 1                                      ) ,\
+    HID_USAGE_MAX      ( 32                                     ) ,\
+    HID_LOGICAL_MIN    ( 0                                      ) ,\
+    HID_LOGICAL_MAX    ( 1                                      ) ,\
+    HID_REPORT_COUNT   ( 32                                     ) ,\
+    HID_REPORT_SIZE    ( 1                                      ) ,\
+    HID_INPUT          ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
   HID_COLLECTION_END \
 
 // HID Generic Input & Output

From 7ad0af64cc172331413aa634aa28002171fe31ab Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 29 Nov 2021 13:24:10 +0700
Subject: [PATCH 0684/2085] use 4k stack for example with esp32sx

---
 examples/device/cdc_msc_freertos/src/main.c       | 14 ++++++--------
 examples/device/hid_composite_freertos/src/main.c | 14 +++++++-------
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 2d3426f1d..0a1c964ae 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -38,12 +38,17 @@
   #include "freertos/queue.h"
   #include "freertos/task.h"
   #include "freertos/timers.h"
+
+  #define USBD_STACK_SIZE     4096
 #else
   #include "FreeRTOS.h"
   #include "semphr.h"
   #include "queue.h"
   #include "task.h"
   #include "timers.h"
+
+  // Increase stack size when debug log is enabled
+  #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
 //--------------------------------------------------------------------+
@@ -65,14 +70,7 @@ enum  {
 StaticTimer_t blinky_tmdef;
 TimerHandle_t blinky_tm;
 
-// static task for usbd
-// Increase stack size when debug log is enabled
-#if CFG_TUSB_DEBUG
-  #define USBD_STACK_SIZE     (3*configMINIMAL_STACK_SIZE)
-#else
-  #define USBD_STACK_SIZE     (3*configMINIMAL_STACK_SIZE/2)
-#endif
-
+// static task
 StackType_t  usb_device_stack[USBD_STACK_SIZE];
 StaticTask_t usb_device_taskdef;
 
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 336f5d426..1695f968c 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -39,12 +39,18 @@
   #include "freertos/queue.h"
   #include "freertos/task.h"
   #include "freertos/timers.h"
+
+  #define USBD_STACK_SIZE     4096
+
 #else
   #include "FreeRTOS.h"
   #include "semphr.h"
   #include "queue.h"
   #include "task.h"
   #include "timers.h"
+
+  // Increase stack size when debug log is enabled
+  #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
 //--------------------------------------------------------------------+
@@ -66,13 +72,7 @@ enum  {
 StaticTimer_t blinky_tmdef;
 TimerHandle_t blinky_tm;
 
-// static task for usbd
-#if CFG_TUSB_DEBUG
-  #define USBD_STACK_SIZE     (3*configMINIMAL_STACK_SIZE)
-#else
-  #define USBD_STACK_SIZE     (3*configMINIMAL_STACK_SIZE/2)
-#endif
-
+// static task
 StackType_t  usb_device_stack[USBD_STACK_SIZE];
 StaticTask_t usb_device_taskdef;
 

From 33506675c51e11f3b04cc7a0a4f11af244a0ba11 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 30 Nov 2021 00:33:55 +0700
Subject: [PATCH 0685/2085] update supported doc

---
 README.rst                   |  10 +-
 docs/reference/supported.rst | 234 +++++++++++++++++++----------------
 2 files changed, 131 insertions(+), 113 deletions(-)

diff --git a/README.rst b/README.rst
index 60df78ca4..a8ce9399c 100644
--- a/README.rst
+++ b/README.rst
@@ -32,8 +32,10 @@ Supported MCUs
 
 The stack supports the following MCUs:
 
+- **Broadcom:** BCM2837, BCM2711
 - **Dialog:** DA1469x
 - **Espressif:** ESP32-S2, ESP32-S3
+- **GigaDevice:** GD32VF103
 - **Infineon:** XMC4500
 - **MicroChip:** SAMD11, SAMD21, SAMD51, SAME5x, SAMG55, SAML21, SAML22, SAME7x
 - **NordicSemi:** nRF52833, nRF52840, nRF5340
@@ -41,15 +43,15 @@ The stack supports the following MCUs:
 - **NXP:**
 
   - iMX RT Series: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
-  - Kinetis: KL25, K32L2Bxx
+  - Kinetis: KL25, K32L2
   - LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
 
 - **Raspberry Pi:** RP2040
-- **Renesas:** RX63N, RX65N
+- **Renesas:** RX63N, RX65N, RX72N
 - **Silabs:** EFM32GG
 - **Sony:** CXD56
-- **ST:** STM32 series: L0, L1, L4, L4+, F0, F1, F2, F3, F4, F7, H7
-- **TI:** MSP430
+- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, L0, L1, L4, L4+
+- **TI:** MSP430, MSP432E4, TM4C123
 - **ValentyUSB:** eptri
 
 Here is the list of `Supported Devices`_ that can be used with provided examples.
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 1d2b4db51..254a0d95d 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -11,117 +11,120 @@ Supported MCUs
 
    This table is a WIP! the data is not correct, tho if a device is listed, it likely works as a usb full speed device at the least.
 
-+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| Manufacturer | Family             | Device            | Host               | FS                | HS                | Known Issues |
-+==============+====================+===================+====================+===================+===================+==============+
-| Dialog       | DA1469x            | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| Espressif    | ESP32-S2           | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | ESP32-S3           | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| MicroChip    | SAMD11             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | SAMD21             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | SAMD51             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | SAME5x             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | SAMG55             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | SAML21             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | SAML22             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | SAME70,S70,V70,V71 | |:green_square:|  | |:red_square:|     | |:green_square:|  | |:green_square:|  |              |
-+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| NordicSemi   | nRF52833           | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | nRF52840           | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| Nuvoton      | NUC120             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | NUC121/NUC125      | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | NUC126             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | NUC505             | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-+--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| NXP          | iMX   | RT1011     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | RT1015     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | RT1021     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | RT1052     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | RT1062     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | RT1064     | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
-|              +-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | Kinetis KL25       | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              +-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | LPC   | 11u        | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | 13         | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | 15         | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | 17         | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | 18         |                   | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | 40         |                   | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | 43         | |:green_square:|  | |:yellow_square:|  | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | 51u        | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | 54         | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | 55         | |:green_square:|  | |:x:|              | |:green_square:|  |                   |              |
-+--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| Raspberry Pi | RP2040             | |:green_square:|  | |:x:|              | |:green_square:|  |                   |              |
-+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| Renesas      | RX63N              | |:green_square:|  |                    | |:green_square:|  | |:x:|             |              |
-|              +--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              | RX65N              | |:green_square:|  |                    | |:green_square:|  | |:x:|             |              |
-+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| Silabs       | EFM32GG12          | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| Sony         | CXD56              | |:green_square:|  | |:x:|              | |:green_square:|  | |:x:|             |              |
-+--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| ST           | STM32 | L0         | |:green_square:|  |                    | |:green_square:|  |                   |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | F0         | |:green_square:|  |                    | |:green_square:|  |                   |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | F1         | |:green_square:|  |                    | |:green_square:|  |                   |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | F2         | |:green_square:|  |                    | |:green_square:|  |                   |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | F3         | |:green_square:|  |                    | |:green_square:|  |                   |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | F4         | |:green_square:|  |                    | |:green_square:|  |                   |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | F7         | |:green_square:|  |                    | |:green_square:|  |                   |              |
-|              |       +------------+-------------------+--------------------+-------------------+-------------------+--------------+
-|              |       | H7         | |:green_square:|  |                    | |:green_square:|  | |:green_square:|  |              |
-+--------------+-------+------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| TI           | MSP430             | |:green_square:|  |                    | |:green_square:|  |                   |              |
-+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
-| ValentyUSB   | eptri              | |:green_square:|  |                    | |:green_square:|  |                   |              |
-+--------------+--------------------+-------------------+--------------------+-------------------+-------------------+--------------+
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| Manufacturer | Family                | Device               | Host                 | Highspeed            | Driver          | Note         |
++==============+=======================+======================+======================+======================+=================+==============+
+| Broadcom     | BCM2711, BCM2837      | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | dwc2            |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| Dialog       | DA1469x               | |:heavy_check_mark:| | |:x:|                | |:x:|                | da146xx         |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| Espressif    | ESP32 S2, S3          | |:heavy_check_mark:| |                      | |:x:|                | dwc2 or esp32sx |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| GigaDevice   | GD32VF103             | |:heavy_check_mark:| |                      | |:x:|                | dwc2            |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| Infineon     | XMC4500               | |:heavy_check_mark:| |                      | |:x:|                | dwc2            |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| MicroChip    | SAM D11, D21          | |:heavy_check_mark:| |                      | |:x:|                | samd            |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | SAM D51, E5x          | |:heavy_check_mark:| |                      | |:x:|                | samd            |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | SAM G55               | |:heavy_check_mark:| |                      | |:x:|                | samg            |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | SAM L21, L22          | |:heavy_check_mark:| |                      | |:x:|                | samd            |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | SAM E70,S70,V70,V71   | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | samx7x          |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| NordicSemi   | nRF52833, nRF52840    | |:heavy_check_mark:| | |:x:|                | |:x:|                | nrf5x           |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | nRF5340               | |:heavy_check_mark:| | |:x:|                | |:x:|                | nrf5x           |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| Nuvoton      | NUC120                | |:heavy_check_mark:| | |:x:|                | |:x:|                |                 |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | NUC121/NUC125         | |:heavy_check_mark:| | |:x:|                | |:x:|                |                 |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | NUC126                | |:heavy_check_mark:| | |:x:|                | |:x:|                |                 |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | NUC505                | |:heavy_check_mark:| |                      | |:heavy_check_mark:| |                 |              |
++--------------+---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| NXP          | iMXRT   | RT1011      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | RT1015      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | RT1021      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | RT1052      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | RT1062      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | RT1064      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
+|              +---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | Kinetis | KL25        | |:heavy_check_mark:| |                      | |:x:|                |                 |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | K32L2       | |:heavy_check_mark:| |                      | |:x:|                |                 |              |
+|              +---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | LPC     | 11u, 13, 15 | |:heavy_check_mark:| | |:x:|                | |:x:|                | lpc_ip3511      |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | 17, 40      | |:heavy_check_mark:| | |:construction:|     | |:x:|                | lpc17_40        |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | 18, 43      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:x:|                |                 |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | 51u         | |:heavy_check_mark:| | |:x:|                | |:x:|                | lpc_ip3511      |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | 54          | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | lpc_ip3511      |              |
+|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |         | 55          | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | lpc_ip3511      |              |
++--------------+---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| Raspberry Pi | RP2040                | |:heavy_check_mark:| | |:heavy_check_mark:| | |:x:|                | rp2040          |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| Renesas      | RX 63N, 65N, 72N      | |:heavy_check_mark:| | |:x:|                | |:x:|                | usba            |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| Silabs       | EFM32GG12             | |:heavy_check_mark:| |                      | |:x:|                | dwc2            |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| Sony         | CXD56                 | |:heavy_check_mark:| | |:x:|                | |:heavy_check_mark:| | cxd56           |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| ST STM32     | F0                    | |:heavy_check_mark:| | |:x:|                | |:x:|                | stm32_fsdev     |              |
+|              +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | F1 | 102, 103         | |:heavy_check_mark:| | |:x:|                | |:x:|                | stm32_fsdev     |              |
+|              |    +------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |    | 105, 107         | |:heavy_check_mark:| |                      | |:x:|                | dwc2            |              |
+|              +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | F2                    | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | dwc2            |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | F3                    | |:heavy_check_mark:| | |:x:|                | |:x:|                | stm32_fsdev     |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | F4                    | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | dwc2            |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | F7                    | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | dwc2            |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | H7                    | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | dwc2            |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | L0, L1                | |:heavy_check_mark:| | |:x:|                | |:x:|                | stm32_fsdev     |              |
+|              +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | L4 | 4x2, 4x3         | |:heavy_check_mark:| | |:x:|                | |:x:|                | stm32_fsdev     |              |
+|              |    +------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              |    | 4x5, 4x6         | |:heavy_check_mark:| |                      |                      | dwc2            |              |
+|              +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | L4+                   | |:heavy_check_mark:| |                      |                      | dwc2            |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | U5                    | |:construction:|     |                      |                      | dwc2            |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| TI           | MSP430                | |:heavy_check_mark:| | |:x:|                | |:x:|                | msp430x5xx      |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | MSP432E4              | |:heavy_check_mark:| |                      | |:x:|                | musb            |              |
+|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+|              | TM4C123               | |:heavy_check_mark:| |                      | |:x:|                | musb            |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
+| ValentyUSB   | eptri                 | |:heavy_check_mark:| | |:x:|                | |:x:|                | eptri           |              |
++--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
 
 Table Legend
 ------------
 
-================= ===================
-|:x:|             Not available
-|:red_square:|    Not supported
-|:yellow_square:| WIP/partial support
-|:green_square:|  Supported
-================= ===================
+==================== ===================
+|:heavy_check_mark:| Supported
+|:construction:|     WIP/partial support
+|:x:|                Not supported
+==================== ===================
 
 Supported Boards
 ================
@@ -134,6 +137,11 @@ The board support code is only used for self-contained examples and testing. It
 
 The following boards are supported (sorted alphabetically):
 
+Broadcom
+--------
+
+-  `Raspberry Pi CM4 <https://www.raspberrypi.com/products/compute-module-4>`__
+
 Dialog DA146xx
 --------------
 
@@ -143,12 +151,17 @@ Dialog DA146xx
 Espressif ESP32-S2
 ------------------
 
--  Adafruit Feather ESP32-S2
+-  `Adafruit Feather ESP32-S2 <https://www.adafruit.com/product/5000>`__
 -  `Adafruit Magtag 2.9" E-Ink WiFi Display <https://www.adafruit.com/product/4800>`__
 -  `Adafruit Metro ESP32-S2 <https://www.adafruit.com/product/4775>`__
 -  `ESP32-S2-Kaluga-1 <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-esp32-s2-kaluga-1-kit.html>`__
 -  `ESP32-S2-Saola-1 <https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html>`__
 
+GigaDevice
+----------
+
+-  `Sipeed Longan Nano <https://longan.sipeed.com/en/>`__
+
 Infineon
 ---------
 
@@ -243,7 +256,8 @@ iMX RT
 Kinetis
 ^^^^^^^
 
--  `FRDM-KL25Z <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z>`__
+-  `Freedom FRDM-KL25Z <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z>`__
+-  `Freedom FRDM-K32L2B3 <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3>`__
 
 LPC 11-13-15
 ^^^^^^^^^^^^
@@ -374,6 +388,8 @@ TI
 --
 
 -  `MSP430F5529 USB LaunchPad Evaluation Kit <http://www.ti.com/tool/MSP-EXP430F5529LP>`__
+-  `MSP-EXP432E401Y LaunchPad Evaluation Kit <https://www.ti.com/tool/MSP-EXP432E401Y>`__
+-  `TM4C123GXL LaunchPad Evaluation Kit <https://www.ti.com/tool/EK-TM4C123GXL>`__
 
 Tomu
 ----

From 4678a4142e8dff8c0c7b959dd6862eeb9e9d62f1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 30 Nov 2021 00:35:39 +0700
Subject: [PATCH 0686/2085] remove warnings

---
 docs/reference/supported.rst | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 254a0d95d..dfaffe6e3 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -6,11 +6,6 @@ Supported Devices
 Supported MCUs
 ==============
 
-.. admonition:: Warning
-   :class: warning
-
-   This table is a WIP! the data is not correct, tho if a device is listed, it likely works as a usb full speed device at the least.
-
 +--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
 | Manufacturer | Family                | Device               | Host                 | Highspeed            | Driver          | Note         |
 +==============+=======================+======================+======================+======================+=================+==============+

From dba59217da489dc497cbe2b573e7e144d085c869 Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Tue, 30 Nov 2021 17:10:53 +0800
Subject: [PATCH 0687/2085] usbd: supress "statement is unreachable" warning on
 ARMCC

---
 src/device/usbd.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 6a5210b34..0e31f47c7 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -44,6 +44,11 @@
   #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
 
+#ifdef __ARMCC_VERSION
+// Supress "statement is unreachable" warning
+#pragma diag_suppress 111
+#endif
+
 //--------------------------------------------------------------------+
 // Device Data
 //--------------------------------------------------------------------+

From ac20605e3f098687ce40349bbecc9266333d951b Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Tue, 30 Nov 2021 17:11:09 +0800
Subject: [PATCH 0688/2085] Ignore certain compiler options on ARMCC

ARMCC also sets __GNU__ macro, but doesn't support
GCC diagnostic pragmas.
---
 src/common/tusb_compiler.h | 4 +++-
 src/device/dcd.h           | 4 ++--
 src/osal/osal.h            | 4 ++--
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index d3284c62a..38e6a16d0 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -137,9 +137,11 @@
   #define TU_BSWAP16(u16) (__builtin_bswap16(u16))
   #define TU_BSWAP32(u32) (__builtin_bswap32(u32))
 
+	#ifndef __ARMCC_VERSION
   // List of obsolete callback function that is renamed and should not be defined.
   // Put it here since only gcc support this pragma
-  #pragma GCC poison tud_vendor_control_request_cb
+		#pragma GCC poison tud_vendor_control_request_cb
+	#endif
 
 #elif defined(__TI_COMPILER_VERSION__)
   #define TU_ATTR_ALIGNED(Bytes)        __attribute__ ((aligned(Bytes)))
diff --git a/src/device/dcd.h b/src/device/dcd.h
index c042cc708..fbcef40d4 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -106,12 +106,12 @@ typedef struct TU_ATTR_ALIGNED(4)
 void dcd_init       (uint8_t rhport);
 
 // Interrupt Handler
-#if __GNUC__
+#if __GNUC__ && !defined(__ARMCC_VERSION)
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wredundant-decls"
 #endif
 void dcd_int_handler(uint8_t rhport);
-#if __GNUC__
+#if __GNUC__ && !defined(__ARMCC_VERSION)
 #pragma GCC diagnostic pop
 #endif
 
diff --git a/src/osal/osal.h b/src/osal/osal.h
index c8131d19d..9194f80d5 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -67,7 +67,7 @@ typedef void (*osal_task_func_t)( void * );
 // OSAL Porting API
 //--------------------------------------------------------------------+
 
-#if __GNUC__
+#if __GNUC__ && !defined(__ARMCC_VERSION)
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wredundant-decls"
 #endif
@@ -88,7 +88,7 @@ static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
 static inline bool osal_queue_receive(osal_queue_t qhdl, void* data);
 static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
 static inline bool osal_queue_empty(osal_queue_t qhdl);
-#if __GNUC__
+#if __GNUC__ && !defined(__ARMCC_VERSION)
 #pragma GCC diagnostic pop
 #endif
 

From a6929cf03eabe9f4fc0404d7c15b04ee2761945c Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Tue, 30 Nov 2021 17:11:14 +0800
Subject: [PATCH 0689/2085] Add support for Keil RTX4 OS abstraction layer

---
 src/osal/osal.h      |   2 +
 src/osal/osal_rtx4.h | 169 +++++++++++++++++++++++++++++++++++++++++++
 src/tusb_option.h    |   1 +
 3 files changed, 172 insertions(+)
 create mode 100644 src/osal/osal_rtx4.h

diff --git a/src/osal/osal.h b/src/osal/osal.h
index 9194f80d5..b2943cc79 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -57,6 +57,8 @@ typedef void (*osal_task_func_t)( void * );
   #include "osal_pico.h"
 #elif CFG_TUSB_OS == OPT_OS_RTTHREAD
   #include "osal_rtthread.h"
+#elif CFG_TUSB_OS == OPT_OS_RTX4
+  #include "osal_rtx4.h"
 #elif CFG_TUSB_OS == OPT_OS_CUSTOM
   #include "tusb_os_custom.h" // implemented by application
 #else
diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h
new file mode 100644
index 000000000..93d1a7a28
--- /dev/null
+++ b/src/osal/osal_rtx4.h
@@ -0,0 +1,169 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_OSAL_RTX4_H_
+#define _TUSB_OSAL_RTX4_H_
+
+#include <rtl.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// TASK API
+//--------------------------------------------------------------------+
+static inline void osal_task_delay(uint32_t msec)
+{
+  uint16_t hi = msec >> 16;
+  uint16_t lo = msec;
+  while (hi--) {
+    os_dly_wait(0xFFFE);
+  }
+  os_dly_wait(lo);
+}
+
+static inline uint16_t msec2wait(uint32_t msec) {
+  if (msec == OSAL_TIMEOUT_WAIT_FOREVER)
+    return 0xFFFF;
+  else if (msec >= 0xFFFE)
+    return 0xFFFE;
+  else
+    return msec;
+}
+
+//--------------------------------------------------------------------+
+// Semaphore API
+//--------------------------------------------------------------------+
+typedef OS_SEM osal_semaphore_def_t;
+typedef OS_ID osal_semaphore_t;
+
+static inline OS_ID osal_semaphore_create(osal_semaphore_def_t* semdef) {
+  os_sem_init(semdef, 0);
+  return semdef;
+}
+
+static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
+  if ( !in_isr ) {
+    os_sem_send(sem_hdl);
+  } else {
+    isr_sem_send(sem_hdl);
+  }
+	return true;
+}
+
+static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) {
+  return os_sem_wait(sem_hdl, msec2wait(msec)) != OS_R_TMO;
+}
+
+static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
+  // TODO: implement
+}
+
+//--------------------------------------------------------------------+
+// MUTEX API (priority inheritance)
+//--------------------------------------------------------------------+
+typedef OS_MUT osal_mutex_def_t;
+typedef OS_ID osal_mutex_t;
+
+static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
+{
+  os_mut_init(mdef);
+  return mdef;
+}
+
+static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
+{
+  return os_mut_wait(mutex_hdl, msec2wait(msec)) != OS_R_TMO;
+}
+
+static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
+{
+  return os_mut_release(mutex_hdl) == OS_R_OK;
+}
+
+//--------------------------------------------------------------------+
+// QUEUE API
+//--------------------------------------------------------------------+
+
+// role device/host is used by OS NONE for mutex (disable usb isr) only
+#define OSAL_QUEUE_DEF(_role, _name, _depth, _type)   \
+  os_mbx_declare(_name##__mbox, _depth);              \
+  _declare_box(_name##__pool, sizeof(_type), _depth); \
+  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .pool = _name##__pool, .mbox = _name##__mbox };
+  
+
+typedef struct
+{
+  uint16_t depth;
+  uint16_t item_sz;
+  U32* pool;
+  U32* mbox;
+}osal_queue_def_t;
+
+typedef osal_queue_def_t* osal_queue_t;
+
+static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
+{
+  os_mbx_init(qdef->mbox, (qdef->depth + 4) * 4);
+  _init_box(qdef->pool, ((qdef->item_sz+3)/4)*(qdef->depth) + 3, qdef->item_sz);
+  return qdef;
+}
+
+static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
+{
+  void* buf;
+  os_mbx_wait(qhdl->mbox, &buf, 0xFFFF);
+  memcpy(data, buf, qhdl->item_sz);
+  _free_box(qhdl->pool, buf);
+  return true;
+}
+
+static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
+{
+  void* buf = _alloc_box(qhdl->pool);
+  memcpy(buf, data, qhdl->item_sz);
+  if ( !in_isr )
+  {
+    os_mbx_send(qhdl->mbox, buf, 0xFFFF);
+  }
+  else
+  {
+    isr_mbx_send(qhdl->mbox, buf);
+  }
+  return true;
+}
+
+static inline bool osal_queue_empty(osal_queue_t qhdl)
+{
+  return os_mbx_check(qhdl->mbox) == qhdl->depth;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_OSAL_FREERTOS_H_ */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 2edd310fa..dcf1c4614 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -151,6 +151,7 @@
 #define OPT_OS_CUSTOM     4  ///< Custom OS is implemented by application
 #define OPT_OS_PICO       5  ///< Raspberry Pi Pico SDK
 #define OPT_OS_RTTHREAD   6  ///< RT-Thread
+#define OPT_OS_RTX4       7  ///< Keil RTX 4
 
 // Allow to use command line to change the config name/location
 #ifdef CFG_TUSB_CONFIG_FILE

From 06f99c220ef4f53677c5e5354a309cad3b4d11ef Mon Sep 17 00:00:00 2001
From: rppicomidi <rppicomidi@gmail.com>
Date: Fri, 12 Nov 2021 14:58:51 -0800
Subject: [PATCH 0690/2085] implement hcd device close

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 36 ++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 768cccc86..97dae480d 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -64,6 +64,8 @@ enum {
                   USB_SIE_CTRL_PULLDOWN_EN_BITS | USB_SIE_CTRL_EP0_INT_1BUF_BITS
 };
 
+enum { ADDR_INVALID  = 0xFFu };
+
 static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
 {
   uint8_t num = tu_edpt_number(ep_addr);
@@ -346,6 +348,21 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
     }
 }
 
+// return struct hw_endpoint* pointing to the endpoint in the pool or NULL if the dev_addr is not found
+static struct hw_endpoint *_hw_find_first_endpoint(uint8_t dev_addr)
+{
+    struct hw_endpoint *ep = NULL;
+    for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++)
+    {
+        ep = &ep_pool[i];
+        if (ep->dev_addr == dev_addr && ep->configured)
+        {
+            return ep;
+        }
+    }
+    return NULL;
+}
+
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
@@ -412,9 +429,24 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 // Close all opened endpoint belong to this device
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 {
-    (void) rhport;
-    (void) dev_addr;
+    assert(rhport == 0);
+    if (dev_addr == 0)
+        return;
 
+    struct hw_endpoint *ep = _hw_find_first_endpoint(dev_addr);
+    while (ep)
+    {
+        // in case it is an interrupt endpoint, disable it
+        usb_hw_clear->int_ep_ctrl = (1 << (ep->interrupt_num + 1));
+        usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = 0;
+        // unconfigure the endpoint
+        ep->configured = false;
+        *ep->endpoint_control = 0;
+        *ep->buffer_control = 0;
+        hw_endpoint_reset_transfer(ep);
+        ep->dev_addr = ADDR_INVALID; // don't find this one again
+        ep = _hw_find_first_endpoint(dev_addr);
+    }
     pico_trace("hcd_device_close %d\n", dev_addr);
 }
 

From 006522e4375d58bfe01b9745ff7df35fb3d48868 Mon Sep 17 00:00:00 2001
From: rppicomidi <rppicomidi@gmail.com>
Date: Fri, 12 Nov 2021 14:59:19 -0800
Subject: [PATCH 0691/2085] on unplug release device endpoints

---
 src/host/usbh.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index f74e7114c..eca72a1c5 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -546,6 +546,9 @@ void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port
 
       hcd_device_close(rhport, dev_addr);
 
+      // release all endpoints associated with the device
+      tu_memclr(dev->ep_status, sizeof(dev->ep_status));
+
       dev->state = TUSB_DEVICE_STATE_UNPLUG;
     }
   }

From 3e3fe1e429aed7bd0000f49b1ef15f83eb815a19 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 30 Nov 2021 17:36:52 +0700
Subject: [PATCH 0692/2085] improve hcd_device_close() for rp2040

---
 src/host/usbh.c                              |  5 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 52 +++++++-------------
 2 files changed, 21 insertions(+), 36 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index eca72a1c5..b8439addc 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -541,12 +541,11 @@ void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port
         usbh_class_drivers[drv_id].close(dev_addr);
       }
 
-      memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
-      memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
-
       hcd_device_close(rhport, dev_addr);
 
       // release all endpoints associated with the device
+      memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
+      memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
       tu_memclr(dev->ep_status, sizeof(dev->ep_status));
 
       dev->state = TUSB_DEVICE_STATE_UNPLUG;
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 97dae480d..3e80dd872 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -64,8 +64,6 @@ enum {
                   USB_SIE_CTRL_PULLDOWN_EN_BITS | USB_SIE_CTRL_EP0_INT_1BUF_BITS
 };
 
-enum { ADDR_INVALID  = 0xFFu };
-
 static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
 {
   uint8_t num = tu_edpt_number(ep_addr);
@@ -348,21 +346,6 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
     }
 }
 
-// return struct hw_endpoint* pointing to the endpoint in the pool or NULL if the dev_addr is not found
-static struct hw_endpoint *_hw_find_first_endpoint(uint8_t dev_addr)
-{
-    struct hw_endpoint *ep = NULL;
-    for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++)
-    {
-        ep = &ep_pool[i];
-        if (ep->dev_addr == dev_addr && ep->configured)
-        {
-            return ep;
-        }
-    }
-    return NULL;
-}
-
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
@@ -429,25 +412,28 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 // Close all opened endpoint belong to this device
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 {
-    assert(rhport == 0);
-    if (dev_addr == 0)
-        return;
+  pico_trace("hcd_device_close %d\n", dev_addr);
+  (void) rhport;
 
-    struct hw_endpoint *ep = _hw_find_first_endpoint(dev_addr);
-    while (ep)
+  if (dev_addr == 0) return;
+
+  for (size_t i = 1; i < TU_ARRAY_SIZE(ep_pool); i++)
+  {
+    hw_endpoint_t* ep = &ep_pool[i];
+
+    if (ep->dev_addr == dev_addr && ep->configured)
     {
-        // in case it is an interrupt endpoint, disable it
-        usb_hw_clear->int_ep_ctrl = (1 << (ep->interrupt_num + 1));
-        usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = 0;
-        // unconfigure the endpoint
-        ep->configured = false;
-        *ep->endpoint_control = 0;
-        *ep->buffer_control = 0;
-        hw_endpoint_reset_transfer(ep);
-        ep->dev_addr = ADDR_INVALID; // don't find this one again
-        ep = _hw_find_first_endpoint(dev_addr);
+      // in case it is an interrupt endpoint, disable it
+      usb_hw_clear->int_ep_ctrl = (1 << (ep->interrupt_num + 1));
+      usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = 0;
+
+      // unconfigure the endpoint
+      ep->configured = false;
+      *ep->endpoint_control = 0;
+      *ep->buffer_control = 0;
+      hw_endpoint_reset_transfer(ep);
     }
-    pico_trace("hcd_device_close %d\n", dev_addr);
+  }
 }
 
 uint32_t hcd_frame_number(uint8_t rhport)

From 9bccc8068baf6efef0bd040ec5238369c0a03c0f Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Tue, 30 Nov 2021 23:13:20 +0900
Subject: [PATCH 0693/2085] Add register settings to handle a HUB

---
 src/portable/mentor/musb/hcd_musb.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index b4931a793..dc614d074 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -325,7 +325,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_
 {
   (void)rhport;
 
-  const unsigned req = _hcd.bmRequestType;
+  unsigned const req = _hcd.bmRequestType;
   TU_ASSERT(req != REQUEST_TYPE_INVALID);
   TU_ASSERT(dev_addr < sizeof(_hcd.ctl_mps));
 
@@ -453,6 +453,7 @@ static void process_ep0(uint8_t rhport)
     /* STATUS IN */
     TU_ASSERT(USB_CSRL0_RXRDY == (csrl & USB_CSRL0_RXRDY),);
     TU_ASSERT(0 == USB0->COUNT0,);
+    USB0->CSRH0 = USB_CSRH0_FLUSH;
     USB0->CSRL0 = 0;
     _hcd.bmRequestType = REQUEST_TYPE_INVALID;
     hcd_event_xfer_complete(dev_addr, tu_edpt_addr(0, TUSB_DIR_IN),
@@ -694,7 +695,17 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   _hcd.pipe0.buf       = (void*)(uintptr_t)setup_packet;
   _hcd.pipe0.length    = 8;
   _hcd.pipe0.remaining = 0;
-  _hcd.bmRequestType   = REQUEST_TYPE_INVALID;
+
+  hcd_devtree_info_t devtree;
+  hcd_devtree_get_info(dev_addr, &devtree);
+  switch (devtree.speed) {
+    default: return false;
+    case TUSB_SPEED_LOW:  USB0->TYPE0 = USB_TYPE0_SPEED_LOW;  break;
+    case TUSB_SPEED_FULL: USB0->TYPE0 = USB_TYPE0_SPEED_FULL; break;
+    case TUSB_SPEED_HIGH: USB0->TYPE0 = USB_TYPE0_SPEED_HIGH; break;
+  }
+  USB0->TXHUBADDR0     = devtree.hub_addr;
+  USB0->TXHUBPORT0     = devtree.hub_port;
   USB0->TXFUNCADDR0    = dev_addr;
   USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_SETUP;
   return true;
@@ -702,6 +713,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
+  (void)rhport;
   if (sizeof(_hcd.ctl_mps) <= dev_addr) return false;
   unsigned const ep_addr = ep_desc->bEndpointAddress;
   unsigned const epn     = tu_edpt_number(ep_addr);
@@ -733,7 +745,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   pipe->remaining = 0;
 
   uint8_t pipe_type = 0;
-  switch (hcd_port_speed_get(rhport)) {
+  hcd_devtree_info_t devtree;
+  hcd_devtree_get_info(dev_addr, &devtree);
+  switch (devtree.speed) {
     default: return false;
     case TUSB_SPEED_LOW:  pipe_type |= USB_TXTYPE1_SPEED_LOW;  break;
     case TUSB_SPEED_FULL: pipe_type |= USB_TXTYPE1_SPEED_FULL; break;
@@ -750,6 +764,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1);
   if (dir_tx) {
     fadr->TXFUNCADDR = dev_addr;
+    fadr->TXHUBADDR  = devtree.hub_addr;
+    fadr->TXHUBPORT  = devtree.hub_port;
     regs->TXMAXP     = mps;
     regs->TXTYPE     = pipe_type | epn;
     regs->TXINTERVAL = ep_desc->bInterval;
@@ -760,6 +776,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
     USB0->TXIE |= TU_BIT(pipenum);
   } else {
     fadr->RXFUNCADDR = dev_addr;
+    fadr->RXHUBADDR  = devtree.hub_addr;
+    fadr->RXHUBPORT  = devtree.hub_port;
     regs->RXMAXP     = mps;
     regs->RXTYPE     = pipe_type | epn;
     regs->RXINTERVAL = ep_desc->bInterval;

From 0612433eef6e6a7029b314a4a59ef591e72341f5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Dec 2021 12:14:44 +0700
Subject: [PATCH 0694/2085] add chipidea highspeed controller

add warning to transdimension for the rename
---
 examples/host/cdc_msc_hid/Makefile            |   2 -
 hw/bsp/lpc18/family.mk                        |   4 +-
 src/device/dcd_attr.h                         |   2 +
 src/portable/chipidea/ci_hs/ci_hs_type.h      | 136 ++++
 src/portable/chipidea/ci_hs/dcd_ci_hs.c       | 662 ++++++++++++++++++
 src/portable/chipidea/ci_hs/hcd_ci_hs.c       | 117 ++++
 .../nxp/transdimension/dcd_transdimension.c   |   2 +
 .../nxp/transdimension/hcd_transdimension.c   |   2 +
 8 files changed, 924 insertions(+), 3 deletions(-)
 create mode 100644 src/portable/chipidea/ci_hs/ci_hs_type.h
 create mode 100644 src/portable/chipidea/ci_hs/dcd_ci_hs.c
 create mode 100644 src/portable/chipidea/ci_hs/hcd_ci_hs.c

diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index 0ad9dd856..ce0dd1a40 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -20,9 +20,7 @@ SRC_C += \
 	src/host/hub.c \
 	src/host/usbh.c \
 	src/host/usbh_control.c \
-	src/portable/ehci/ehci.c \
 	src/portable/ohci/ohci.c \
-	src/portable/nxp/transdimension/hcd_transdimension.c \
 	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
 
 include ../../rules.mk
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index 79a00cb2d..7aa36abc4 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -18,7 +18,9 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=ca
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx
 
 SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc18xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
 	$(MCU_DIR)/src/clock_18xx_43xx.c \
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 73d592e5c..3c5dadaf4 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -44,6 +44,7 @@
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4
+  #define DCD_ATTR_CONTROLLER_CHIPIDEA_HS
   #define DCD_ATTR_ENDPOINT_MAX   6
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
@@ -58,6 +59,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   6
 
 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
+  #define DCD_ATTR_CONTROLLER_CHIPIDEA_HS
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h
new file mode 100644
index 000000000..402c26334
--- /dev/null
+++ b/src/portable/chipidea/ci_hs/ci_hs_type.h
@@ -0,0 +1,136 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef CI_HS_TYPE_H_
+#define CI_HS_TYPE_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// USBCMD
+enum {
+  USBCMD_RUN_STOP         = TU_BIT(0),
+  USBCMD_RESET            = TU_BIT(1),
+  USBCMD_SETUP_TRIPWIRE   = TU_BIT(13),
+  USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
+// Interrupt Threshold bit 23:16
+};
+
+// PORTSC1
+#define PORTSC1_PORT_SPEED_POS    26
+
+enum {
+  PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0),
+  PORTSC1_FORCE_PORT_RESUME      = TU_BIT(6),
+  PORTSC1_SUSPEND                = TU_BIT(7),
+  PORTSC1_FORCE_FULL_SPEED       = TU_BIT(24),
+  PORTSC1_PORT_SPEED             = TU_BIT(26) | TU_BIT(27)
+};
+
+// OTGSC
+enum {
+  OTGSC_VBUS_DISCHARGE          = TU_BIT(0),
+  OTGSC_VBUS_CHARGE             = TU_BIT(1),
+//  OTGSC_HWASSIST_AUTORESET    = TU_BIT(2),
+  OTGSC_OTG_TERMINATION         = TU_BIT(3), ///< Must set to 1 when OTG go to device mode
+  OTGSC_DATA_PULSING            = TU_BIT(4),
+  OTGSC_ID_PULLUP               = TU_BIT(5),
+//  OTGSC_HWASSIT_DATA_PULSE    = TU_BIT(6),
+//  OTGSC_HWASSIT_BDIS_ACONN    = TU_BIT(7),
+  OTGSC_ID                      = TU_BIT(8), ///< 0 = A device, 1 = B Device
+  OTGSC_A_VBUS_VALID            = TU_BIT(9),
+  OTGSC_A_SESSION_VALID         = TU_BIT(10),
+  OTGSC_B_SESSION_VALID         = TU_BIT(11),
+  OTGSC_B_SESSION_END           = TU_BIT(12),
+  OTGSC_1MS_TOGGLE              = TU_BIT(13),
+  OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14),
+};
+
+// USBMode
+enum {
+  USBMODE_CM_DEVICE = 2,
+  USBMODE_CM_HOST   = 3,
+
+  USBMODE_SLOM = TU_BIT(3),
+  USBMODE_SDIS = TU_BIT(4),
+
+  USBMODE_VBUS_POWER_SELECT = TU_BIT(5), // Need to be enabled for LPC18XX/43XX in host mode
+};
+
+// Device Registers
+typedef struct
+{
+  //------------- ID + HW Parameter Registers-------------//
+  __I  uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
+
+  //------------- Capability Registers-------------//
+  __I  uint8_t  CAPLENGTH;       ///< Capability Registers Length
+  __I  uint8_t  TU_RESERVED[1];
+  __I  uint16_t HCIVERSION;      ///< Host Controller Interface Version
+
+  __I  uint32_t HCSPARAMS;       ///< Host Controller Structural Parameters
+  __I  uint32_t HCCPARAMS;       ///< Host Controller Capability Parameters
+  __I  uint32_t TU_RESERVED[5];
+
+  __I  uint16_t DCIVERSION;      ///< Device Controller Interface Version
+  __I  uint8_t  TU_RESERVED[2];
+
+  __I  uint32_t DCCPARAMS;       ///< Device Controller Capability Parameters
+  __I  uint32_t TU_RESERVED[6];
+
+  //------------- Operational Registers -------------//
+  __IO uint32_t USBCMD;          ///< USB Command Register
+  __IO uint32_t USBSTS;          ///< USB Status Register
+  __IO uint32_t USBINTR;         ///< Interrupt Enable Register
+  __IO uint32_t FRINDEX;         ///< USB Frame Index
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t DEVICEADDR;      ///< Device Address
+  __IO uint32_t ENDPTLISTADDR;   ///< Endpoint List Address
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t BURSTSIZE;       ///< Programmable Burst Size
+  __IO uint32_t TXFILLTUNING;    ///< TX FIFO Fill Tuning
+       uint32_t TU_RESERVED[4];
+  __IO uint32_t ENDPTNAK;        ///< Endpoint NAK
+  __IO uint32_t ENDPTNAKEN;      ///< Endpoint NAK Enable
+  __I  uint32_t TU_RESERVED;
+  __IO uint32_t PORTSC1;         ///< Port Status & Control
+  __I  uint32_t TU_RESERVED[7];
+  __IO uint32_t OTGSC;           ///< On-The-Go Status & control
+  __IO uint32_t USBMODE;         ///< USB Device Mode
+  __IO uint32_t ENDPTSETUPSTAT;  ///< Endpoint Setup Status
+  __IO uint32_t ENDPTPRIME;      ///< Endpoint Prime
+  __IO uint32_t ENDPTFLUSH;      ///< Endpoint Flush
+  __I  uint32_t ENDPTSTAT;       ///< Endpoint Status
+  __IO uint32_t ENDPTCOMPLETE;   ///< Endpoint Complete
+  __IO uint32_t ENDPTCTRL[8];    ///< Endpoint Control 0 - 7
+} dcd_registers_t, hcd_registers_t;
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* CI_HS_TYPE_H_ */
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
new file mode 100644
index 000000000..e531cd842
--- /dev/null
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -0,0 +1,662 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && \
+    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  #include "fsl_device_registers.h"
+  #define INCLUDE_FSL_DEVICE_REGISTERS
+#else
+  // LPCOpen for 18xx & 43xx
+  #include "chip.h"
+#endif
+
+#include "common/tusb_common.h"
+#include "device/dcd.h"
+#include "ci_hs_type.h"
+
+#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
+  #define CleanInvalidateDCache_by_Addr   SCB_CleanInvalidateDCache_by_Addr
+#else
+  #define CleanInvalidateDCache_by_Addr(_addr, _dsize)
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+// ENDPTCTRL
+enum {
+  ENDPTCTRL_STALL          = TU_BIT(0),
+  ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), // used for test only
+  ENDPTCTRL_TOGGLE_RESET   = TU_BIT(6),
+  ENDPTCTRL_ENABLE         = TU_BIT(7)
+};
+
+enum {
+  ENDPTCTRL_TYPE_POS  = 2, // Endpoint type is 2-bit field
+};
+
+// USBSTS, USBINTR
+enum {
+  INTR_USB         = TU_BIT(0),
+  INTR_ERROR       = TU_BIT(1),
+  INTR_PORT_CHANGE = TU_BIT(2),
+  INTR_RESET       = TU_BIT(6),
+  INTR_SOF         = TU_BIT(7),
+  INTR_SUSPEND     = TU_BIT(8),
+  INTR_NAK         = TU_BIT(16)
+};
+
+// Queue Transfer Descriptor
+typedef struct
+{
+  // Word 0: Next QTD Pointer
+  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
+
+  // Word 1: qTQ Token
+  uint32_t                      : 3  ;
+  volatile uint32_t xact_err    : 1  ;
+  uint32_t                      : 1  ;
+  volatile uint32_t buffer_err  : 1  ;
+  volatile uint32_t halted      : 1  ;
+  volatile uint32_t active      : 1  ;
+  uint32_t                      : 2  ;
+  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
+  uint32_t                      : 3  ;
+  uint32_t int_on_complete      : 1  ;
+  volatile uint32_t total_bytes : 15 ;
+  uint32_t                      : 1  ;
+
+  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
+  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
+
+  //--------------------------------------------------------------------+
+  // TD is 32 bytes aligned but occupies only 28 bytes
+  // Therefore there are 4 bytes padding that we can use.
+  //--------------------------------------------------------------------+
+  uint16_t expected_bytes;
+  uint8_t reserved[2];
+} dcd_qtd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
+
+// Queue Head
+typedef struct
+{
+  // Word 0: Capabilities and Characteristics
+  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
+  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
+  uint32_t max_packet_size         : 11 ; ///< Endpoint's wMaxPacketSize
+  uint32_t                         : 2  ;
+  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple�. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
+  uint32_t iso_mult                : 2  ; ///<
+
+  // Word 1: Current qTD Pointer
+  volatile uint32_t qtd_addr;
+
+  // Word 2-9: Transfer Overlay
+  volatile dcd_qtd_t qtd_overlay;
+
+  // Word 10-11: Setup request (control OUT only)
+  volatile tusb_control_request_t setup_request;
+
+  //--------------------------------------------------------------------+
+  // QHD is 64 bytes aligned but occupies only 48 bytes
+  // Therefore there are 16 bytes padding that we can use.
+  //--------------------------------------------------------------------+
+  tu_fifo_t * ff;
+  uint8_t reserved[12];
+} dcd_qhd_t;
+
+TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Variables
+//--------------------------------------------------------------------+
+
+typedef struct
+{
+  dcd_registers_t* regs;  // registers
+  const IRQn_Type irqnum; // IRQ number
+  const uint8_t ep_count; // Max bi-directional Endpoints
+}dcd_controller_t;
+
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  static const dcd_controller_t _dcd_controller[] =
+  {
+    // RT1010 and RT1020 only has 1 USB controller
+    #if FSL_FEATURE_SOC_USBHS_COUNT == 1
+      { .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
+    #else
+      { .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
+      { .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
+    #endif
+  };
+
+#else
+  static const dcd_controller_t _dcd_controller[] =
+  {
+    { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
+    { .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
+  };
+#endif
+
+#define QTD_NEXT_INVALID 0x01
+
+typedef struct {
+  // Must be at 2K alignment
+  // Each endpoint with direction (IN/OUT) occupies a queue head
+  // for portability, TinyUSB only queue 1 TD for each Qhd
+  dcd_qhd_t qhd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64);
+  dcd_qtd_t qtd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
+}dcd_data_t;
+
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
+static dcd_data_t _dcd_data;
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+/// follows LPC43xx User Manual 23.10.3
+static void bus_reset(uint8_t rhport)
+{
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
+  // The reset value for all endpoint types is the control endpoint. If one endpoint
+  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
+  // endpoint type of the unused direction must be changed from the control type to any other
+  // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
+  // for the data PID tracking on the active endpoint.
+  for( uint8_t i=1; i < _dcd_controller[rhport].ep_count; i++)
+  {
+    dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
+  }
+
+  //------------- Clear All Registers -------------//
+  dcd_reg->ENDPTNAK       = dcd_reg->ENDPTNAK;
+  dcd_reg->ENDPTNAKEN     = 0;
+  dcd_reg->USBSTS         = dcd_reg->USBSTS;
+  dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
+  dcd_reg->ENDPTCOMPLETE  = dcd_reg->ENDPTCOMPLETE;
+
+  while (dcd_reg->ENDPTPRIME) {}
+  dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
+  while (dcd_reg->ENDPTFLUSH) {}
+
+  // read reset bit in portsc
+
+  //------------- Queue Head & Queue TD -------------//
+  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
+
+  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
+  _dcd_data.qhd[0][0].zero_length_termination = _dcd_data.qhd[0][1].zero_length_termination = 1;
+  _dcd_data.qhd[0][0].max_packet_size  = _dcd_data.qhd[0][1].max_packet_size  = CFG_TUD_ENDPOINT0_SIZE;
+  _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID;
+
+  _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
+}
+
+void dcd_init(uint8_t rhport)
+{
+  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
+
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
+  // Reset controller
+  dcd_reg->USBCMD |= USBCMD_RESET;
+  while( dcd_reg->USBCMD & USBCMD_RESET ) {}
+
+  // Set mode to device, must be set immediately after reset
+  dcd_reg->USBMODE = USBMODE_CM_DEVICE;
+  dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
+
+#if !TUD_OPT_HIGH_SPEED
+  dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
+#endif
+
+  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+
+  dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
+  dcd_reg->USBSTS  = dcd_reg->USBSTS;
+  dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND;
+
+  dcd_reg->USBCMD &= ~0x00FF0000;     // Interrupt Threshold Interval = 0
+  dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  // Response with status first before changing device address
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->USBCMD |= USBCMD_RUN_STOP;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
+}
+
+//--------------------------------------------------------------------+
+// HELPER
+//--------------------------------------------------------------------+
+
+static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
+{
+  // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the
+  // address to 32-byte boundaries. Buffer must be word aligned
+  CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
+
+  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
+
+  p_qtd->next            = QTD_NEXT_INVALID;
+  p_qtd->active          = 1;
+  p_qtd->total_bytes     = p_qtd->expected_bytes = total_bytes;
+  p_qtd->int_on_complete = true;
+
+  if (data_ptr != NULL)
+  {
+    p_qtd->buffer[0] = (uint32_t) data_ptr;
+
+    uint32_t const bufend = p_qtd->buffer[0] + total_bytes;
+    for(uint8_t i=1; i<5; i++)
+    {
+      uint32_t const next_page = tu_align4k( p_qtd->buffer[i-1] ) + 4096;
+      if ( bufend <= next_page ) break;
+
+      p_qtd->buffer[i] = next_page;
+
+      // TODO page[1] FRAME_N for ISO transfer
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// DCD Endpoint Port
+//--------------------------------------------------------------------+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = tu_edpt_number(ep_addr);
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
+
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
+
+  // flush to abort any primed buffer
+  dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  // data toggle also need to be reset
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
+  dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir  ? 16 : 0));
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+
+  // Must not exceed max endpoint number
+  TU_ASSERT( epnum < _dcd_controller[rhport].ep_count );
+
+  //------------- Prepare Queue Head -------------//
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
+  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
+
+  p_qhd->zero_length_termination = 1;
+  p_qhd->max_packet_size         = tu_edpt_packet_size(p_endpoint_desc);
+  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
+  {
+    p_qhd->iso_mult = 1;
+  }
+
+  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
+
+  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+
+  // Enable EP Control
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
+  uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
+
+  if ( dir == TUSB_DIR_OUT )
+  {
+    dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0xFFFF0000u) | epctrl;
+  }else
+  {
+    dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0x0000FFFFu) | (epctrl << 16);
+  }
+
+  return true;
+}
+
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
+  // Disable all non-control endpoints
+  for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++)
+  {
+    _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1;
+    _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1;
+
+    dcd_reg->ENDPTFLUSH = TU_BIT(epnum) |  TU_BIT(epnum+16);
+    dcd_reg->ENDPTCTRL[epnum] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
+  }
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum  = tu_edpt_number(ep_addr);
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
+
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
+  _dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1;
+
+  // Flush EP
+  uint32_t const flush_mask = TU_BIT(epnum + (dir ? 16 : 0));
+  dcd_reg->ENDPTFLUSH = flush_mask;
+  while(dcd_reg->ENDPTFLUSH & flush_mask);
+
+  // Clear EP enable
+  dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0));
+}
+
+static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
+{
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
+  dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
+
+  p_qhd->qtd_overlay.halted = false;            // clear any previous error
+  p_qhd->qtd_overlay.next   = (uint32_t) p_qtd; // link qtd to qhd
+
+  // flush cache
+  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+
+  if ( epnum == 0 )
+  {
+    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
+    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
+    while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
+  }
+
+  // start transfer
+  dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0));
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
+  dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
+
+  // Prepare qtd
+  qtd_init(p_qtd, buffer, total_bytes);
+
+  // Start qhd transfer
+  p_qhd->ff = NULL;
+  qhd_start_xfer(rhport, epnum, dir);
+
+  return true;
+}
+
+// fifo has to be aligned to 4k boundary
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
+  dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
+
+  tu_fifo_buffer_info_t fifo_info;
+
+  if (dir)
+  {
+    tu_fifo_get_read_info(ff, &fifo_info);
+  } else
+  {
+    tu_fifo_get_write_info(ff, &fifo_info);
+  }
+
+  if ( fifo_info.len_lin >= total_bytes )
+  {
+    // Linear length is enough for this transfer
+    qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes);
+  }
+  else
+  {
+    // linear part is not enough
+
+    // prepare TD up to linear length
+    qtd_init(p_qtd, fifo_info.ptr_lin, fifo_info.len_lin);
+
+    if ( !tu_offset4k((uint32_t) fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff)) )
+    {
+      // If buffer is aligned to 4K & buffer size is multiple of 4K
+      // We can make use of buffer page array to also combine the linear + wrapped length
+      p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
+
+      for(uint8_t i = 1, page = 0; i < 5; i++)
+      {
+        // pick up buffer array where linear ends
+        if (p_qtd->buffer[i] == 0)
+        {
+          p_qtd->buffer[i] = (uint32_t) fifo_info.ptr_wrap + 4096 * page;
+          page++;
+        }
+      }
+
+      CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
+    }
+    else
+    {
+      // TODO we may need to carry the wrapped length after the linear part complete
+      // for now only transfer up to linear part
+    }
+  }
+
+  // Start qhd transfer
+  p_qhd->ff = ff;
+  qhd_start_xfer(rhport, epnum, dir);
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+
+static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir)
+{
+  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
+  dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
+
+  uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
+      ( p_qtd->xact_err || p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
+
+  if ( result != XFER_RESULT_SUCCESS )
+  {
+    dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+    // flush to abort error buffer
+    dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
+  }
+
+  uint16_t const xferred_bytes = p_qtd->expected_bytes - p_qtd->total_bytes;
+
+  if (p_qhd->ff)
+  {
+    if (dir == TUSB_DIR_IN)
+    {
+      tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes);
+    } else
+    {
+      tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
+    }
+  }
+  
+  // only number of bytes in the IOC qtd
+  dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
+}
+
+void dcd_int_handler(uint8_t rhport)
+{
+  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+
+  uint32_t const int_enable = dcd_reg->USBINTR;
+  uint32_t const int_status = dcd_reg->USBSTS & int_enable;
+  dcd_reg->USBSTS = int_status; // Acknowledge handled interrupt
+
+  // disabled interrupt sources
+  if (int_status == 0) return;
+
+  // Set if the port controller enters the full or high-speed operational state.
+  // either from Bus Reset or Suspended state
+	if (int_status & INTR_PORT_CHANGE)
+	{
+	  // TU_LOG2("PortChange %08lx\r\n", dcd_reg->PORTSC1);
+
+	  // Reset interrupt is not enabled, we manually check if Port Change is due
+	  // to connection / disconnection
+	  if ( dcd_reg->USBSTS & INTR_RESET )
+	  {
+	    dcd_reg->USBSTS = INTR_RESET;
+
+	    if (dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS)
+	    {
+	      uint32_t const speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS;
+	      bus_reset(rhport);
+	      dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true);
+	    }else
+	    {
+	      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+	    }
+	  }
+	  else
+	  {
+	    // Triggered by resuming from suspended state
+	    if ( !(dcd_reg->PORTSC1 & PORTSC1_SUSPEND) )
+	    {
+	      dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+	    }
+	  }
+	}
+
+  if (int_status & INTR_SUSPEND)
+  {
+    // TU_LOG2("Suspend %08lx\r\n", dcd_reg->PORTSC1);
+
+    if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
+    {
+      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+      // Skip suspend event if we are not addressed
+      if ((dcd_reg->DEVICEADDR >> 25) & 0x0f)
+      {
+        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+      }
+    }
+  }
+
+  if (int_status & INTR_USB)
+  {
+    // Make sure we read the latest version of _dcd_data.
+    CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+
+    uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
+    dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
+
+    if (dcd_reg->ENDPTSETUPSTAT)
+    {
+      //------------- Set up Received -------------//
+      // 23.10.10.2 Operational model for setup transfers
+      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
+
+      dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
+    }
+
+    // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
+    // nothing to do, we will submit xfer as error to usbd
+    // if (int_status & INTR_ERROR) { }
+
+    if ( edpt_complete )
+    {
+      for(uint8_t epnum = 0; epnum < DCD_ATTR_ENDPOINT_MAX; epnum++)
+      {
+        if ( tu_bit_test(edpt_complete, epnum)    ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_OUT);
+        if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN);
+      }
+    }
+  }
+
+  if (int_status & INTR_SOF)
+  {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+}
+
+#endif
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
new file mode 100644
index 000000000..a62ebf2a3
--- /dev/null
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -0,0 +1,117 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+// Chipidea Highspeed USB IP implement EHCI for host functionality
+
+#if TUSB_OPT_HOST_ENABLED && \
+    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  #include "fsl_device_registers.h"
+#else
+  // LPCOpen for 18xx & 43xx
+  #include "chip.h"
+#endif
+
+#include "common/tusb_common.h"
+#include "ci_hs_type.h"
+#include "portable/ehci/ehci_api.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+// TODO can be merged with dcd_controller_t
+typedef struct
+{
+  uint32_t regs_base;     // registers base
+  const IRQn_Type irqnum; // IRQ number
+}hcd_controller_t;
+
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  static const hcd_controller_t _hcd_controller[] =
+  {
+    // RT1010 and RT1020 only has 1 USB controller
+    #if FSL_FEATURE_SOC_USBHS_COUNT == 1
+      { .regs_base = USB_BASE , .irqnum = USB_OTG1_IRQn }
+    #else
+      { .regs_base = USB1_BASE, .irqnum = USB_OTG1_IRQn },
+      { .regs_base = USB2_BASE, .irqnum = USB_OTG2_IRQn }
+    #endif
+  };
+
+#else
+  static const hcd_controller_t _hcd_controller[] =
+  {
+    { .regs_base = LPC_USB0_BASE, .irqnum = USB0_IRQn },
+    { .regs_base = LPC_USB1_BASE, .irqnum = USB1_IRQn }
+  };
+#endif
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+bool hcd_init(uint8_t rhport)
+{
+  hcd_registers_t* hcd_reg = (hcd_registers_t*) _hcd_controller[rhport].regs_base;
+
+  // Reset controller
+  hcd_reg->USBCMD |= USBCMD_RESET;
+  while( hcd_reg->USBCMD & USBCMD_RESET ) {}
+
+  // Set mode to device, must be set immediately after reset
+#if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
+  // LPC18XX/43XX need to set VBUS Power Select to HIGH
+  // RHPORT1 is fullspeed only (need external PHY for Highspeed)
+  hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
+  if (rhport == 1) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+#else
+  hcd_reg->USBMODE = USBMODE_CM_HOST;
+#endif
+
+  // FIXME force full speed, still have issue with Highspeed enumeration
+  hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+
+  return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD);
+}
+
+void hcd_int_enable(uint8_t rhport)
+{
+  NVIC_EnableIRQ(_hcd_controller[rhport].irqnum);
+}
+
+void hcd_int_disable(uint8_t rhport)
+{
+  NVIC_DisableIRQ(_hcd_controller[rhport].irqnum);
+}
+
+#endif
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 5ac041fbf..f6433293d 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -29,6 +29,8 @@
 #if TUSB_OPT_DEVICE_ENABLED && \
     (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
 
+#warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly"
+
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+
diff --git a/src/portable/nxp/transdimension/hcd_transdimension.c b/src/portable/nxp/transdimension/hcd_transdimension.c
index d216f0728..81ad3152d 100644
--- a/src/portable/nxp/transdimension/hcd_transdimension.c
+++ b/src/portable/nxp/transdimension/hcd_transdimension.c
@@ -31,6 +31,8 @@
 #if TUSB_OPT_HOST_ENABLED && \
     (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
 
+#warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly"
+
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+

From bb7d1fa3bacb08717e8eebc55f81fde7bf810e3a Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Tue, 30 Nov 2021 17:12:56 +0800
Subject: [PATCH 0695/2085] Add support for Allwinner F1Cx00s family

Allwinner F1Cx00s family is a series of SoCs
with Mentor MUSB controller and HS phy. It comes
with a slightly different register space layout,
and some quirks, so it's not multiplexed with
the existing musb support library.

This library currently requires to be compiled
with https://github.com/hongxuyao/F1C100s_with_Keil_RTX4_emWin5
---
 src/device/dcd_attr.h               |    4 +
 src/portable/sunxi/dcd_sunxi_musb.c | 1152 +++++++++++++++++++++++++++
 src/portable/sunxi/musb_def.h       |  615 ++++++++++++++
 src/tusb_option.h                   |    3 +
 4 files changed, 1774 insertions(+)
 create mode 100644 src/portable/sunxi/dcd_sunxi_musb.c
 create mode 100644 src/portable/sunxi/musb_def.h

diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 73d592e5c..0ea46ebe1 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -195,6 +195,10 @@
 #elif TU_CHECK_MCU(OPT_MCU_XMC4000)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
+//------------ Allwinner -------------//
+#elif TU_CHECK_MCU(OPT_MCU_F1C100S)
+  #define DCD_ATTR_ENDPOINT_MAX   4
+
 #else
   #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define DCD_ATTR_ENDPOINT_MAX   8
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
new file mode 100644
index 000000000..bb39d3890
--- /dev/null
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -0,0 +1,1152 @@
+#include <stdint.h>
+#include <F1C100s.h>
+#include <f1c100s-irq.h>
+
+#include <tusb_option.h>
+#include <device/dcd.h>
+#include "musb_def.h"
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+#if !TU_CHECK_MCU(OPT_MCU_F1C100S)
+    #error "Only f1c100s is supported"
+#endif
+
+#define REQUEST_TYPE_INVALID  (0xFFu)
+
+typedef struct {
+  uint_fast16_t beg; /* offset of including first element */
+  uint_fast16_t end; /* offset of excluding the last element */
+} free_block_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  void      *buf;      /* the start address of a transfer data buffer */
+  uint16_t  length;    /* the number of bytes in the buffer */
+  uint16_t  remaining; /* the number of bytes remaining in the buffer */
+} pipe_state_t;
+
+typedef struct
+{
+  tusb_control_request_t setup_packet;
+  uint16_t     remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */
+  int8_t       status_out;
+  pipe_state_t pipe0;
+  pipe_state_t pipe[2][7];   /* pipe[direction][endpoint number - 1] */
+  uint16_t     pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */
+} dcd_data_t;
+
+/*------------------------------------------------------------------
+ * SUNXI FUNCTION
+ *------------------------------------------------------------------*/
+
+static void usb_phy_write(int addr, int data, int len)
+{
+	int j = 0, usbc_bit = 0;
+	void *dest = (void *)USBC_REG_CSR(USBC0_BASE);
+
+	usbc_bit = 1 << (0 * 2);
+	for (j = 0; j < len; j++)
+	{
+		/* set the bit address to be written */
+		USBC_ClrBit_Mask_l(dest, 0xff << 8);
+		USBC_SetBit_Mask_l(dest, (addr + j) << 8);
+
+		USBC_ClrBit_Mask_l(dest, usbc_bit);
+		/* set data bit */
+		if (data & 0x1)
+			USBC_SetBit_Mask_l(dest, 1 << 7);
+		else
+			USBC_ClrBit_Mask_l(dest, 1 << 7);
+
+		USBC_SetBit_Mask_l(dest, usbc_bit);
+
+		USBC_ClrBit_Mask_l(dest, usbc_bit);
+
+		data >>= 1;
+	}
+}
+
+static void USBC_HardwareReset(void)
+{
+  // Reset phy and controller
+  USBC_REG_set_bit_l(USBPHY_CLK_RST_BIT, USBPHY_CLK_REG);
+	USBC_REG_set_bit_l(BUS_RST_USB_BIT, BUS_CLK_RST_REG);
+  osal_task_delay(2);
+
+	USBC_REG_set_bit_l(USBPHY_CLK_GAT_BIT, USBPHY_CLK_REG);
+  USBC_REG_set_bit_l(USBPHY_CLK_RST_BIT, USBPHY_CLK_REG);
+
+	USBC_REG_set_bit_l(BUS_CLK_USB_BIT, BUS_CLK_GATE0_REG);
+	USBC_REG_set_bit_l(BUS_RST_USB_BIT, BUS_CLK_RST_REG);
+}
+
+static void USBC_PhyConfig()
+{
+	/* Regulation 45 ohms */
+	usb_phy_write(0x0c, 0x01, 1);
+
+	/* adjust PHY's magnitude and rate */
+	usb_phy_write(0x20, 0x14, 5);
+
+	/* threshold adjustment disconnect */
+	usb_phy_write(0x2a, 3, 2);
+
+	return;
+}
+
+static void USBC_ConfigFIFO_Base()
+{
+	u32 reg_value;
+
+	/* config usb fifo, 8kb mode */
+	reg_value = USBC_Readl(SUNXI_SRAMC_BASE + 0x04);
+	reg_value &= ~(0x03 << 0);
+	reg_value |= (1 << 0);
+	USBC_Writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
+}
+
+static unsigned int USBC_WakeUp_ClearChangeDetect(unsigned int reg_val)
+{
+	unsigned int temp = reg_val;
+    /* vbus, id, dpdm, these bit is set 1 to clear, so we clear these bit when operate other bits */
+	temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT);
+	temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT);
+	temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT);
+
+	return temp;
+}
+
+static void USBC_EnableDpDmPullUp(void)
+{
+	u32 reg_val = USBC_Readl(USBC_REG_ISCR(USBC0_BASE));
+	reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
+	reg_val |= 3<<USBC_BP_ISCR_VBUS_VALID_SRC;
+	reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+	USBC_Writel(reg_val, USBC_REG_ISCR(USBC0_BASE));
+}
+
+static void USBC_ForceIdToHigh(void)
+{
+	/* first write 00, then write 10 */
+	u32 reg_val = USBC_Readl(USBC_REG_ISCR(USBC0_BASE));
+	reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
+	reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+	USBC_Writel(reg_val, USBC_REG_ISCR(USBC0_BASE));
+}
+
+static void USBC_ForceVbusValidToHigh(void)
+{
+	/* first write 00, then write 11 */
+	u32 reg_val = USBC_Readl(USBC_REG_ISCR(USBC0_BASE));
+	reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
+	reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
+	USBC_Writel(reg_val, USBC_REG_ISCR(USBC0_BASE));
+}
+
+void USBC_SelectBus(u32 io_type, u32 ep_type, u32 ep_index)
+{
+	u32 reg_val = 0;
+
+	reg_val = USBC_Readb(USBC_REG_VEND0(USBC0_BASE));
+	if (io_type == USBC_IO_TYPE_DMA) {
+		if (ep_type == USBC_EP_TYPE_TX) {
+			reg_val |= ((ep_index - 0x01) << 1) << USBC_BP_VEND0_DRQ_SEL;  //drq_sel
+			reg_val |= 0x1<<USBC_BP_VEND0_BUS_SEL;   //io_dma
+		} else {
+			reg_val |= ((ep_index << 1) - 0x01) << USBC_BP_VEND0_DRQ_SEL;
+			reg_val |= 0x1<<USBC_BP_VEND0_BUS_SEL;
+		}
+	} else {
+		//reg_val &= ~(0x1 << USBC_BP_VEND0_DRQ_SEL);  //clear drq_sel, select pio
+		reg_val &= 0x00;  // clear drq_sel, select pio
+	}
+
+	/* in 1667 1673 and later ic, FIFO_BUS_SEL bit(bit24 of reg0x40 for host/device)
+	 * is fixed to 1, the hw guarantee that it's ok for cpu/inner_dma/outer_dma transfer */
+
+//	reg_val |= 0x1<<USBC_BP_VEND0_BUS_SEL;  //for 1663 set 1: enable dma, set 0: enable fifo
+
+	USBC_Writeb(reg_val, USBC_REG_VEND0(USBC0_BASE));
+}
+
+static void USBC_SelectActiveEp(u8 ep_index)
+{
+	USBC_Writeb(ep_index, USBC_REG_EPIND(USBC0_BASE));
+}
+
+static void __USBC_Dev_ep0_SendStall(void)
+{
+	USBC_REG_set_bit_w(USBC_BP_CSR0_D_SEND_STALL, USBC_REG_CSR0(USBC0_BASE));
+}
+
+static void __USBC_Dev_ep0_ClearStall(void)
+{
+	USBC_REG_clear_bit_w(USBC_BP_CSR0_D_SEND_STALL, USBC_REG_CSR0(USBC0_BASE));
+	USBC_REG_clear_bit_w(USBC_BP_CSR0_D_SENT_STALL, USBC_REG_CSR0(USBC0_BASE));
+}
+
+static void USBC_Dev_Ctrl_ClearSetupEnd(void)
+{
+	USBC_REG_set_bit_w(USBC_BP_CSR0_D_SERVICED_SETUP_END, USBC_REG_CSR0(USBC0_BASE));
+}
+
+static void USBC_Dev_SetAddress(u8 address)
+{
+	USBC_Writeb(address, USBC_REG_FADDR(USBC0_BASE));
+}
+
+static void __USBC_Dev_Tx_SendStall(void)
+{
+	//send stall, and fifo is flushed automaticly
+	USBC_REG_set_bit_w(USBC_BP_TXCSR_D_SEND_STALL, USBC_REG_TXCSR(USBC0_BASE));
+}
+static u32 __USBC_Dev_Tx_IsEpStall(void)
+{
+	return USBC_REG_test_bit_w(USBC_BP_TXCSR_D_SENT_STALL, USBC_REG_TXCSR(USBC0_BASE));
+}
+static void __USBC_Dev_Tx_ClearStall(void)
+{
+	u32 reg_val = USBC_Readw(USBC_REG_TXCSR(USBC0_BASE));
+	reg_val &= ~((1 << USBC_BP_TXCSR_D_SENT_STALL)|(1 << USBC_BP_TXCSR_D_SEND_STALL)|(1<<USBC_BP_TXCSR_D_UNDER_RUN));
+  reg_val |= (1 << USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE);
+	USBC_Writew(reg_val, USBC_REG_TXCSR(USBC0_BASE));
+}
+
+static void __USBC_Dev_Rx_SendStall(void)
+{
+	USBC_REG_set_bit_w(USBC_BP_RXCSR_D_SEND_STALL, USBC_REG_RXCSR(USBC0_BASE));
+}
+
+static u32 __USBC_Dev_Rx_IsEpStall(void)
+{
+	return USBC_REG_test_bit_w(USBC_BP_RXCSR_D_SENT_STALL, USBC_REG_RXCSR(USBC0_BASE));
+}
+
+static void __USBC_Dev_Rx_ClearStall(void)
+{
+	u32 reg_val = USBC_Readw(USBC_REG_RXCSR(USBC0_BASE));
+	reg_val &= ~((1 << USBC_BP_RXCSR_D_SENT_STALL)|(1 << USBC_BP_RXCSR_D_SEND_STALL)|(1<<USBC_BP_RXCSR_D_OVERRUN));
+  reg_val |= (1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE);
+	USBC_Writew(reg_val, USBC_REG_RXCSR(USBC0_BASE));
+}
+
+static tusb_speed_t USBC_Dev_QueryTransferMode(void)
+{
+	if (USBC_REG_test_bit_b(USBC_BP_POWER_D_HIGH_SPEED_FLAG, USBC_REG_PCTL(USBC0_BASE)))
+		return TUSB_SPEED_HIGH;
+  else
+		return TUSB_SPEED_FULL;
+}
+
+static void __USBC_Dev_ep0_ReadDataHalf(void)
+{
+	USBC_Writew(1<<USBC_BP_CSR0_D_SERVICED_RX_PKT_READY, USBC_REG_CSR0(USBC0_BASE));
+}
+
+static void __USBC_Dev_ep0_ReadDataComplete(void)
+{
+	USBC_Writew((1<<USBC_BP_CSR0_D_SERVICED_RX_PKT_READY) | (1<<USBC_BP_CSR0_D_DATA_END),
+	USBC_REG_CSR0(USBC0_BASE));
+}
+
+
+static void __USBC_Dev_ep0_WriteDataHalf(void)
+{
+	USBC_Writew(1<<USBC_BP_CSR0_D_TX_PKT_READY, USBC_REG_CSR0(USBC0_BASE));
+}
+
+static void __USBC_Dev_ep0_WriteDataComplete(void)
+{
+	USBC_Writew((1<<USBC_BP_CSR0_D_TX_PKT_READY) | (1<<USBC_BP_CSR0_D_DATA_END),
+	USBC_REG_CSR0(USBC0_BASE));
+}
+
+static void __USBC_Dev_Tx_WriteDataComplete(void)
+{
+	USBC_Writeb((1 << USBC_BP_TXCSR_D_TX_READY), USBC_REG_TXCSR(USBC0_BASE));
+}
+
+static void __USBC_Dev_Rx_ReadDataComplete(void)
+{
+	USBC_Writeb(0, USBC_REG_RXCSR(USBC0_BASE));
+}
+
+static u32 __USBC_Dev_Rx_IsReadDataReady(void)
+{
+	return USBC_REG_test_bit_w(USBC_BP_RXCSR_D_RX_PKT_READY, USBC_REG_RXCSR(USBC0_BASE));
+}
+
+/* open a tx ep's interrupt */
+static void USBC_INT_EnableTxEp(u8 ep_index)
+{
+	USBC_REG_set_bit_w(ep_index, USBC_REG_INTTxE(USBC0_BASE));
+}
+
+/* open a rx ep's interrupt */
+static void USBC_INT_EnableRxEp(u8 ep_index)
+{
+	USBC_REG_set_bit_w(ep_index, USBC_REG_INTRxE(USBC0_BASE));
+}
+
+/* close a tx ep's interrupt */
+static void USBC_INT_DisableTxEp(u8 ep_index)
+{
+	USBC_REG_clear_bit_w(ep_index, USBC_REG_INTTxE(USBC0_BASE));
+}
+
+/* close a rx ep's interrupt */
+static void USBC_INT_DisableRxEp(u8 ep_index)
+{
+	USBC_REG_clear_bit_w(ep_index, USBC_REG_INTRxE(USBC0_BASE));
+}
+
+/*------------------------------------------------------------------
+ * INTERNAL FUNCTION DECLARATION
+ *------------------------------------------------------------------*/
+
+static dcd_data_t _dcd;
+
+static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr)
+{
+  free_block_t *cur = beg;
+  for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ;
+  return cur;
+}
+
+static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size)
+{
+  free_block_t *p = find_containing_block(blks, blks + num, addr);
+  TU_ASSERT(p != blks + num, -2);
+  if (p->beg == addr) {
+    /* Shrink block */
+    p->beg = addr + size;
+    if (p->beg != p->end) return 0;
+    /* remove block */
+    free_block_t *end = blks + num;
+    while (p + 1 < end) {
+      *p = *(p + 1);
+      ++p;
+    }
+    return -1;
+  } else {
+    /* Split into 2 blocks */
+    free_block_t tmp = {
+      .beg = addr + size,
+      .end = p->end
+    };
+    p->end = addr;
+    if (p->beg == p->end) {
+      if (tmp.beg != tmp.end) {
+        *p = tmp;
+        return 0;
+      }
+      /* remove block */
+      free_block_t *end = blks + num;
+      while (p + 1 < end) {
+        *p = *(p + 1);
+        ++p;
+      }
+      return -1;
+    }
+    if (tmp.beg == tmp.end) return 0;
+    blks[num] = tmp;
+    return 1;
+  }
+}
+
+static inline unsigned free_block_size(free_block_t const *blk)
+{
+  return blk->end - blk->beg;
+}
+
+#if 0
+static inline void print_block_list(free_block_t const *blk, unsigned num)
+{
+  TU_LOG1("*************\n");
+  for (unsigned i = 0; i < num; ++i) {
+    TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end);
+    ++blk;
+  }
+}
+#else
+#define print_block_list(a,b)
+#endif
+
+static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
+{
+  free_block_t free_blocks[2 * (DCD_ATTR_ENDPOINT_MAX - 1)];
+  unsigned num_blocks = 1;
+
+  /* Initialize free memory block list */
+  free_blocks[0].beg = 64 / 8;
+  free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */
+  for (int i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
+    uint_fast16_t addr;
+    int num;
+    USBC_SelectActiveEp(i);
+    addr = USBC_Readw(USBC_REG_TXFIFOAD(USBC0_BASE));
+    if (addr) {
+      unsigned sz  = USBC_Readb(USBC_REG_TXFIFOSZ(USBC0_BASE));
+      unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0);
+      num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
+      TU_ASSERT(-2 < num, 0);
+      num_blocks += num;
+      print_block_list(free_blocks, num_blocks);
+    }
+    addr = USBC_Readw(USBC_REG_RXFIFOAD(USBC0_BASE));
+    if (addr) {
+      unsigned sz  = USBC_Readb(USBC_REG_RXFIFOSZ(USBC0_BASE));
+      unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0);
+      num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft);
+      TU_ASSERT(-2 < num, 0);
+      num_blocks += num;
+      print_block_list(free_blocks, num_blocks);
+    }
+  }
+  print_block_list(free_blocks, num_blocks);
+
+  /* Find the best fit memory block */
+  uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3;
+  free_block_t const *min = NULL;
+  uint_fast16_t    min_sz = 0xFFFFu;
+  free_block_t const *end = &free_blocks[num_blocks];
+  for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) {
+    uint_fast16_t sz = free_block_size(cur);
+    if (sz < size_in_8byte_unit) continue;
+    if (size_in_8byte_unit == sz) return cur->beg;
+    if (sz < min_sz) min = cur;
+  }
+  TU_ASSERT(min, 0);
+  return min->beg;
+}
+
+static void pipe_write_packet(void *buff, volatile void *fifo, unsigned cnt)
+{
+ 	u32 len = 0;
+	u32 i32 = 0;
+	u32 i8  = 0;
+	u8  *buf8  = 0;
+	u32 *buf32 = 0;
+
+	//--<1>-- adjust data
+	buf32 = buff;
+	len   = cnt;
+
+	i32 = len >> 2;
+	i8  = len & 0x03;
+
+	//--<2>-- deal with 4byte part
+	while (i32--) {
+		USBC_Writel(*buf32++, fifo);
+	}
+
+	//--<3>-- deal with no 4byte part
+	buf8 = (u8 *)buf32;
+	while (i8--) {
+		USBC_Writeb(*buf8++, fifo);
+	}
+}
+
+static void pipe_read_packet(void *buff, volatile void *fifo, unsigned cnt)
+{
+	u32 len = 0;
+	u32 i32 = 0;
+	u32 i8  = 0;
+	u8  *buf8  = 0;
+	u32 *buf32 = 0;
+
+	//--<1>-- adjust data
+	buf32 = buff;
+	len   = cnt;
+
+	i32 = len >> 2;
+	i8  = len & 0x03;
+
+	//--<2>-- deal with 4byte part
+	while (i32--) {
+		*buf32++ = USBC_Readl(fifo);
+	}
+
+	//--<3>-- deal with no 4byte part
+	buf8 = (u8 *)buf32;
+	while (i8--) {
+		*buf8++ = USBC_Readb(fifo);
+	}
+}
+
+static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir)
+{
+  static const struct {
+    void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
+    void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n);
+    void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len);
+  } ops[] = {
+    /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet},
+    /* IN  */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet},
+  };
+  tu_fifo_buffer_info_t info;
+  ops[dir].tu_fifo_get_info(f, &info);
+  unsigned total_len = len;
+  len = TU_MIN(total_len, info.len_lin);
+  ops[dir].pipe_read_write(info.ptr_lin, fifo, len);
+  unsigned rem = total_len - len;
+  if (rem) {
+    len = TU_MIN(rem, info.len_wrap);
+    ops[dir].pipe_read_write(info.ptr_wrap, fifo, len);
+    rem -= len;
+  }
+  ops[dir].tu_fifo_advance(f, total_len - rem);
+}
+
+/*------------------------------------------------------------------
+ * TRANSFER FUNCTION DECLARATION
+ *------------------------------------------------------------------*/
+
+static void process_setup_packet(uint8_t rhport)
+{
+  uint32_t *p = (void*)&_dcd.setup_packet;
+  p[0]        = USBC_Readl(USBC_REG_EPFIFO0(USBC0_BASE));
+  p[1]        = USBC_Readl(USBC_REG_EPFIFO0(USBC0_BASE));
+
+  _dcd.pipe0.buf       = NULL;
+  _dcd.pipe0.length    = 0;
+  _dcd.pipe0.remaining = 0;
+  dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true);
+
+  const unsigned len    = _dcd.setup_packet.wLength;
+  _dcd.remaining_ctrl   = len;
+  const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType);
+  /* Clear RX FIFO and reverse the transaction direction */
+  if (len && dir_in) __USBC_Dev_ep0_ReadDataHalf();
+}
+
+static bool handle_xfer_in(uint_fast8_t ep_addr)
+{
+  unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+  pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
+  const unsigned rem  = pipe->remaining;
+
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+
+  const unsigned mps = USBC_Readw(USBC_REG_TXMAXP(USBC0_BASE));
+  const unsigned len = TU_MIN(mps, rem);
+  uint8_t          *buf = pipe->buf;
+  // TU_LOG1("   %p mps %d len %d rem %d\n", buf, mps, len, rem);
+  if (len) {
+    volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2));
+    if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
+      pipe_read_write_packet_ff((tu_fifo_t *)buf, addr, len, TUSB_DIR_IN);
+    } else {
+      pipe_write_packet(buf, addr, len);
+      pipe->buf       = buf + len;
+    }
+    pipe->remaining = rem - len;
+  }
+  __USBC_Dev_Tx_WriteDataComplete();
+  // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
+  return false;
+}
+
+static bool handle_xfer_out(uint_fast8_t ep_addr)
+{
+  unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+  pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
+  // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL);
+
+  TU_ASSERT(__USBC_Dev_Rx_IsReadDataReady());
+
+  const unsigned mps = USBC_Readw(USBC_REG_RXMAXP(USBC0_BASE));
+  const unsigned rem = pipe->remaining;
+  const unsigned vld = USBC_Readw(USBC_REG_RXCOUNT(USBC0_BASE));
+  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
+  uint8_t          *buf = pipe->buf;
+  if (len) {
+    volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2));
+    if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) {
+      pipe_read_write_packet_ff((tu_fifo_t *)buf, addr, len, TUSB_DIR_OUT);
+    } else {
+      pipe_read_packet(buf, addr, len);
+      pipe->buf       = buf + len;
+    }
+    pipe->remaining = rem - len;
+    __USBC_Dev_ep0_ReadDataComplete();
+  }
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return NULL != buf;
+  }
+  return false;
+}
+
+static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+
+  unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
+  unsigned dir_in       = tu_edpt_dir(ep_addr);
+
+  pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1];
+  pipe->buf          = buffer;
+  pipe->length       = total_bytes;
+  pipe->remaining    = total_bytes;
+
+  USBC_SelectActiveEp(tu_edpt_number(ep_addr));
+
+  if (dir_in) {
+    handle_xfer_in(ep_addr);
+  } else {
+    if (__USBC_Dev_Rx_IsReadDataReady())
+      __USBC_Dev_Rx_ReadDataComplete();
+  }
+  return true;
+}
+
+static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+  TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */
+
+  const unsigned req = _dcd.setup_packet.bmRequestType;
+  TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0);
+
+  USBC_SelectActiveEp(0);
+
+  if (req == REQUEST_TYPE_INVALID || _dcd.status_out) {
+    /* STATUS OUT stage.
+     * MUSB controller automatically handles STATUS OUT packets without
+     * software helps. We do not have to do anything. And STATUS stage
+     * may have already finished and received the next setup packet
+     * without calling this function, so we have no choice but to
+     * invoke the callback function of status packet here. */
+    // TU_LOG1(" STATUS OUT CSRL0 = %x\n", CSRL0);
+    _dcd.status_out = 0;
+    if (req == REQUEST_TYPE_INVALID) {
+      dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
+    } else {
+      /* The next setup packet has already been received, it aborts
+       * invoking callback function to avoid confusing TUSB stack. */
+      TU_LOG1("Drop CONTROL_STAGE_ACK\n");
+    }
+    return true;
+  }
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+  if (tu_edpt_dir(req) == dir_in) { /* DATA stage */
+    TU_ASSERT(total_bytes <= _dcd.remaining_ctrl);
+    const unsigned rem = _dcd.remaining_ctrl;
+    const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes);
+    if (dir_in) {
+      pipe_write_packet(buffer, (volatile void*) USBC_REG_EPFIFO0(USBC0_BASE), len);
+
+      _dcd.pipe0.buf       = buffer + len;
+      _dcd.pipe0.length    = len;
+      _dcd.pipe0.remaining = 0;
+
+      _dcd.remaining_ctrl  = rem - len;
+      if ((len < 64) || (rem == len)) {
+        _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */
+        _dcd.status_out = 1;
+        /* Flush TX FIFO and reverse the transaction direction. */
+        __USBC_Dev_ep0_WriteDataComplete();
+      } else {
+        __USBC_Dev_ep0_WriteDataHalf();
+      }
+      // TU_LOG1(" IN CSRL0 = %x\n", CSRL0);
+    } else {
+      // TU_LOG1(" OUT CSRL0 = %x\n", CSRL0);
+      _dcd.pipe0.buf       = buffer;
+      _dcd.pipe0.length    = len;
+      _dcd.pipe0.remaining = len;
+      __USBC_Dev_ep0_ReadDataHalf();
+    }
+  } else if (dir_in) {
+    // TU_LOG1(" STATUS IN CSRL0 = %x\n", CSRL0);
+    _dcd.pipe0.buf = NULL;
+    _dcd.pipe0.length    = 0;
+    _dcd.pipe0.remaining = 0;
+    /* Clear RX FIFO and reverse the transaction direction */
+    __USBC_Dev_ep0_ReadDataComplete();
+  }
+  return true;
+}
+
+static void process_ep0(uint8_t rhport)
+{
+  USBC_SelectActiveEp(0);
+  uint_fast8_t csrl = USBC_Readw(USBC_REG_CSR0(USBC0_BASE));
+
+  // TU_LOG1(" EP0 CSRL0 = %x\n", csrl);
+
+  if (csrl & USB_CSRL0_STALLED) {
+    /* Returned STALL packet to HOST. */
+    __USBC_Dev_ep0_ClearStall();
+    return;
+  }
+
+  unsigned req = _dcd.setup_packet.bmRequestType;
+  if (csrl & USB_CSRL0_SETEND) {
+    // TU_LOG1("   ABORT by the next packets\n");
+    USBC_Dev_Ctrl_ClearSetupEnd();
+    if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
+      /* DATA stage was aborted by receiving STATUS or SETUP packet. */
+      _dcd.pipe0.buf = NULL;
+      _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+      dcd_event_xfer_complete(rhport,
+                              req & TUSB_DIR_IN_MASK,
+                              _dcd.pipe0.length - _dcd.pipe0.remaining,
+                              XFER_RESULT_SUCCESS, true);
+    }
+    req = REQUEST_TYPE_INVALID;
+    if (!(csrl & USB_CSRL0_RXRDY)) return; /* Received SETUP packet */
+  }
+
+  if (csrl & USB_CSRL0_RXRDY) {
+    /* Received SETUP or DATA OUT packet */
+    if (req == REQUEST_TYPE_INVALID) {
+      /* SETUP */
+      TU_ASSERT(sizeof(tusb_control_request_t) == USBC_Readw(USBC_REG_COUNT0(USBC0_BASE)),);
+      process_setup_packet(rhport);
+      return;
+    }
+    if (_dcd.pipe0.buf) {
+      /* DATA OUT */
+      const unsigned vld = USBC_Readw(USBC_REG_COUNT0(USBC0_BASE));
+      const unsigned rem = _dcd.pipe0.remaining;
+      const unsigned len = TU_MIN(TU_MIN(rem, 64), vld);
+      pipe_read_packet(_dcd.pipe0.buf, (volatile void*)USBC_REG_EPFIFO0(USBC0_BASE), len);
+
+      _dcd.pipe0.remaining = rem - len;
+      _dcd.remaining_ctrl -= len;
+
+      _dcd.pipe0.buf = NULL;
+      dcd_event_xfer_complete(rhport,
+                              tu_edpt_addr(0, TUSB_DIR_OUT),
+                              _dcd.pipe0.length - _dcd.pipe0.remaining,
+                              XFER_RESULT_SUCCESS, true);
+    }
+    return;
+  }
+
+  /* When CSRL0 is zero, it means that completion of sending a any length packet
+   * or receiving a zero length packet. */
+  if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) {
+    /* STATUS IN */
+    if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) {
+      /* The address must be changed on completion of the control transfer. */
+	  USBC_Dev_SetAddress((uint8_t)_dcd.setup_packet.wValue);
+    }
+    _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+    dcd_event_xfer_complete(rhport,
+                            tu_edpt_addr(0, TUSB_DIR_IN),
+                            _dcd.pipe0.length - _dcd.pipe0.remaining,
+                            XFER_RESULT_SUCCESS, true);
+    return;
+  }
+  if (_dcd.pipe0.buf) {
+    /* DATA IN */
+    _dcd.pipe0.buf = NULL;
+    dcd_event_xfer_complete(rhport,
+                            tu_edpt_addr(0, TUSB_DIR_IN),
+                            _dcd.pipe0.length - _dcd.pipe0.remaining,
+                            XFER_RESULT_SUCCESS, true);
+  }
+}
+
+static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
+{
+  bool completed;
+  const unsigned dir_in     = tu_edpt_dir(ep_addr);
+  const unsigned epn        = tu_edpt_number(ep_addr);
+
+  USBC_SelectActiveEp(epn);
+
+  if (dir_in) {
+    // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL);
+    if (__USBC_Dev_Tx_IsEpStall()) {
+	  __USBC_Dev_Tx_ClearStall();
+      return;
+    }
+    completed = handle_xfer_in(ep_addr);
+  } else {
+    // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL);
+    if (__USBC_Dev_Rx_IsEpStall()) {
+	    __USBC_Dev_Rx_ClearStall();
+      return;
+    }
+    completed = handle_xfer_out(ep_addr);
+  }
+
+  if (completed) {
+    pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1];
+    dcd_event_xfer_complete(rhport, ep_addr,
+                            pipe->length - pipe->remaining,
+                            XFER_RESULT_SUCCESS, true);
+  }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+  /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF),
+   * a control transfer state is SETUP or STATUS stage. */
+  _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+  _dcd.status_out = 0;
+  /* When pipe0.buf has not NULL, DATA stage works in progress. */
+  _dcd.pipe0.buf = NULL;
+
+  USBC_Writew(1, USBC_REG_INTTxE(USBC0_BASE)); /* Enable only EP0 */
+  USBC_Writew(0, USBC_REG_INTRxE(USBC0_BASE));
+
+  dcd_event_bus_reset(rhport, USBC_Dev_QueryTransferMode(), true);
+}
+
+/*------------------------------------------------------------------
+ * Device API
+ *------------------------------------------------------------------*/
+
+static void usb_isr_handler() {
+	dcd_int_handler(0);
+}
+
+void dcd_init(uint8_t rhport)
+{
+  dcd_disconnect(rhport);
+  USBC_HardwareReset();
+  USBC_PhyConfig();
+  USBC_ConfigFIFO_Base();
+  USBC_EnableDpDmPullUp();
+  USBC_ForceIdToHigh(); // Force device mode
+  USBC_ForceVbusValidToHigh();
+  USBC_SelectBus(USBC_IO_TYPE_PIO, 0, 0);
+
+  #if TUD_OPT_HIGH_SPEED
+    USBC_REG_set_bit_b(USBC_BP_POWER_D_HIGH_SPEED_EN, USBC_REG_PCTL(USBC0_BASE));
+  #else
+    USBC_REG_clear_bit_b(USBC_BP_POWER_D_HIGH_SPEED_EN, USBC_REG_PCTL(USBC0_BASE));
+  #endif
+
+  USBC_Writeb((1 << USBC_BP_INTUSBE_EN_SUSPEND)
+    | (1 << USBC_BP_INTUSBE_EN_RESUME)
+    | (1 << USBC_BP_INTUSBE_EN_RESET)
+    | (1 << USBC_BP_INTUSBE_EN_SOF)
+    | (1 << USBC_BP_INTUSBE_EN_DISCONNECT)
+    , USBC_REG_INTUSBE(USBC0_BASE));
+  f1c100s_intc_clear_pend(F1C100S_IRQ_USBOTG);
+  f1c100s_intc_set_isr(F1C100S_IRQ_USBOTG, usb_isr_handler);
+
+  dcd_connect(rhport);
+}
+
+// Connect by enabling internal pull-up resistor on D+/D-
+void dcd_connect(uint8_t rhport)
+{
+  (void)rhport;
+  USBC_REG_set_bit_b(USBC_BP_POWER_D_SOFT_CONNECT, USBC_REG_PCTL(USBC0_BASE));
+}
+
+// Disconnect by disabling internal pull-up resistor on D+/D-
+void dcd_disconnect(uint8_t rhport)
+{
+  (void)rhport;
+  USBC_REG_clear_bit_b(USBC_BP_POWER_D_SOFT_CONNECT, USBC_REG_PCTL(USBC0_BASE));
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void)rhport;
+  f1c100s_intc_enable_irq(F1C100S_IRQ_USBOTG);
+}
+
+static void musb_int_mask()
+{
+  f1c100s_intc_mask_irq(F1C100S_IRQ_USBOTG);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void)rhport;
+  f1c100s_intc_disable_irq(F1C100S_IRQ_USBOTG);
+}
+
+static void musb_int_unmask()
+{
+  f1c100s_intc_unmask_irq(F1C100S_IRQ_USBOTG);
+}
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void)rhport;
+  (void)dev_addr;
+  _dcd.pipe0.buf       = NULL;
+  _dcd.pipe0.length    = 0;
+  _dcd.pipe0.remaining = 0;
+  /* Clear RX FIFO to return ACK. */
+  USBC_SelectActiveEp(0);
+  __USBC_Dev_ep0_ReadDataComplete();
+}
+
+// Wake up host
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void)rhport;
+  USBC_REG_set_bit_b(USBC_BP_POWER_D_RESUME, USBC_REG_PCTL(USBC0_BASE));
+  osal_task_delay(10);
+  USBC_REG_clear_bit_b(USBC_BP_POWER_D_RESUME, USBC_REG_PCTL(USBC0_BASE));
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+
+  uint16_t reg_val;
+
+  const unsigned ep_addr = ep_desc->bEndpointAddress;
+  const unsigned epn     = tu_edpt_number(ep_addr);
+  const unsigned dir_in  = tu_edpt_dir(ep_addr);
+  const unsigned xfer    = ep_desc->bmAttributes.xfer;
+  const unsigned mps     = tu_edpt_packet_size(ep_desc);
+
+  TU_ASSERT(epn < DCD_ATTR_ENDPOINT_MAX);
+
+  pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1];
+  pipe->buf       = NULL;
+  pipe->length    = 0;
+  pipe->remaining = 0;
+
+  musb_int_mask();
+
+  // volatile hw_endpoint_t *regs = edpt_regs(epn - 1);
+  USBC_SelectActiveEp(epn);
+  if (dir_in) {
+    USBC_Writew(mps, USBC_REG_TXMAXP(USBC0_BASE));
+
+    reg_val = (1 << USBC_BP_TXCSR_D_MODE) 
+      | (1 << USBC_BP_TXCSR_D_FLUSH_FIFO)
+      | (1 << USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE);
+    if  (xfer == TUSB_XFER_ISOCHRONOUS)
+      reg_val |= (1 << USBC_BP_TXCSR_D_ISO);
+	  USBC_Writew(reg_val, USBC_REG_TXCSR(USBC0_BASE));
+
+    USBC_INT_EnableTxEp(epn);
+  } else {
+    USBC_Writew(mps, USBC_REG_RXMAXP(USBC0_BASE));
+
+    reg_val = (1 << USBC_BP_RXCSR_D_FLUSH_FIFO)
+      | (1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE);
+    if  (xfer == TUSB_XFER_ISOCHRONOUS)
+      reg_val |= (1 << USBC_BP_RXCSR_D_ISO);
+    USBC_Writew(reg_val, USBC_REG_RXCSR(USBC0_BASE));
+
+    USBC_INT_EnableRxEp(epn);
+  }
+
+  /* Setup FIFO */
+  int size_in_log2_minus3 = 28 - TU_MIN(28, __clz((uint32_t)mps));
+  if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3;
+  unsigned addr = find_free_memory(size_in_log2_minus3);
+  TU_ASSERT(addr);
+
+  if (dir_in) {
+    USBC_Writew(addr, USBC_REG_TXFIFOAD(USBC0_BASE));
+    USBC_Writeb(size_in_log2_minus3, USBC_REG_TXFIFOSZ(USBC0_BASE));
+  } else {
+    USBC_Writew(addr, USBC_REG_RXFIFOAD(USBC0_BASE));
+    USBC_Writeb(size_in_log2_minus3, USBC_REG_RXFIFOSZ(USBC0_BASE));
+  }
+
+  musb_int_unmask();
+
+  return true;
+}
+
+void dcd_edpt_close_all(uint8_t rhport)
+{
+  (void) rhport;
+  musb_int_mask();
+  USBC_Writew(1, USBC_REG_INTTxE(USBC0_BASE)); /* Enable only EP0 */
+  USBC_Writew(0, USBC_REG_INTRxE(USBC0_BASE));
+  for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
+    USBC_SelectActiveEp(i);
+    USBC_Writew(0, USBC_REG_TXMAXP(USBC0_BASE));
+		USBC_Writew((1 << USBC_BP_TXCSR_D_MODE) | (1 << USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_TXCSR_D_FLUSH_FIFO),
+      USBC_REG_TXCSR(USBC0_BASE));
+
+    USBC_Writew(0, USBC_REG_RXMAXP(USBC0_BASE));
+	  USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO), 
+      USBC_REG_RXCSR(USBC0_BASE));
+
+    USBC_Writew(0, USBC_REG_TXFIFOAD(USBC0_BASE));
+    USBC_Writeb(0, USBC_REG_TXFIFOSZ(USBC0_BASE));
+    USBC_Writew(0, USBC_REG_RXFIFOAD(USBC0_BASE));
+    USBC_Writeb(0, USBC_REG_RXFIFOSZ(USBC0_BASE));
+  }
+  musb_int_unmask();
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  (void)rhport;
+  unsigned const epn    = tu_edpt_number(ep_addr);
+  unsigned const dir_in = tu_edpt_dir(ep_addr);
+
+  musb_int_mask();
+  USBC_SelectActiveEp(epn);
+  if (dir_in) {
+    USBC_INT_DisableTxEp(epn);
+    USBC_Writew(0, USBC_REG_TXMAXP(USBC0_BASE));
+		USBC_Writew((1 << USBC_BP_TXCSR_D_MODE) | (1 << USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_TXCSR_D_FLUSH_FIFO),
+      USBC_REG_TXCSR(USBC0_BASE));
+
+    USBC_Writew(0, USBC_REG_TXFIFOAD(USBC0_BASE));
+    USBC_Writeb(0, USBC_REG_TXFIFOSZ(USBC0_BASE));
+  } else {
+    USBC_INT_DisableRxEp(epn);
+    USBC_Writew(0, USBC_REG_RXMAXP(USBC0_BASE));
+	  USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO), 
+      USBC_REG_RXCSR(USBC0_BASE));
+
+    USBC_Writew(0, USBC_REG_RXFIFOAD(USBC0_BASE));
+    USBC_Writeb(0, USBC_REG_RXFIFOSZ(USBC0_BASE));
+  }
+  musb_int_unmask();
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  (void)rhport;
+  bool ret;
+  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  unsigned const epnum = tu_edpt_number(ep_addr);
+  musb_int_mask();
+
+  if (epnum) {
+    _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1);
+    ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes);
+  } else {
+    ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes);
+  }
+  musb_int_unmask();
+  return ret;
+}
+
+// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  (void)rhport;
+  bool ret;
+  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  unsigned const epnum = tu_edpt_number(ep_addr);
+  TU_ASSERT(epnum);
+
+  musb_int_mask();
+  _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1);
+  ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes);
+  musb_int_unmask();
+
+  return ret;
+}
+
+// Stall endpoint
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void)rhport;
+  unsigned const epn = tu_edpt_number(ep_addr);
+  musb_int_mask();
+  USBC_SelectActiveEp(epn);
+  if (0 == epn) {
+    if (!ep_addr) { /* Ignore EP80 */
+      _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID;
+      _dcd.pipe0.buf = NULL;
+      __USBC_Dev_ep0_SendStall();
+    }
+  } else {
+    if (tu_edpt_dir(ep_addr)) { /* IN */
+      __USBC_Dev_Tx_SendStall();
+    } else { /* OUT */
+      TU_ASSERT(!__USBC_Dev_Rx_IsReadDataReady(),);
+      __USBC_Dev_Rx_SendStall();
+    }
+  }
+  musb_int_unmask();
+}
+
+// clear stall, data toggle is also reset to DATA0
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void)rhport;
+  unsigned const epn = tu_edpt_number(ep_addr);
+  musb_int_mask();
+  USBC_SelectActiveEp(epn);
+  if (0 != epn) {
+    if (tu_edpt_dir(ep_addr)) { /* IN */
+      __USBC_Dev_Tx_ClearStall();
+    } else { /* OUT */
+      __USBC_Dev_Rx_ClearStall();
+    }
+  }
+  musb_int_unmask();
+}
+
+
+void dcd_int_handler(uint8_t rhport)
+{
+  uint8_t is;
+  uint16_t txis, rxis;
+
+  is   = USBC_Readb(USBC_REG_INTUSB(USBC0_BASE));   /* read interrupt status */
+  txis = USBC_Readw(USBC_REG_INTTx(USBC0_BASE)); /* read interrupt status */
+  rxis = USBC_Readw(USBC_REG_INTRx(USBC0_BASE)); /* read interrupt status */
+
+  is &= USBC_Readb(USBC_REG_INTUSBE(USBC0_BASE)); /* ignore disabled interrupts */
+  USBC_Writeb(is, USBC_REG_INTUSB(USBC0_BASE)); /* sunxi musb requires a write to interrupt register to clear */
+  if (is & USBC_INTUSB_DISCONNECT) {
+	dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
+  }
+  if (is & USBC_INTUSB_SOF) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+  if (is & USBC_INTUSB_RESET) {
+    /* ep0 FADDR must be 0 when (re)entering peripheral mode */
+    USBC_SelectActiveEp(0);
+    USBC_Dev_SetAddress(0);
+    process_bus_reset(rhport);
+  }
+  if (is & USBC_INTUSB_RESUME) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+  }
+  if (is & USBC_INTUSB_SUSPEND) {
+    dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+  }
+
+  txis &= USBC_Readw(USBC_REG_INTTxE(USBC0_BASE));
+  USBC_Writew(txis, USBC_REG_INTTx(USBC0_BASE));
+  if (txis & USBC_INTTx_FLAG_EP0) {
+    process_ep0(rhport);
+    txis &= ~TU_BIT(0);
+  }
+  while (txis) {
+    unsigned const num = __builtin_ctz(txis);
+    process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN));
+    txis &= ~TU_BIT(num);
+  }
+
+  rxis &= USBC_Readw(USBC_REG_INTRxE(USBC0_BASE));
+  USBC_Writew(rxis, USBC_REG_INTRx(USBC0_BASE));
+  while (rxis) {
+    unsigned const num = __builtin_ctz(rxis);
+    process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT));
+    rxis &= ~TU_BIT(num);
+  }
+}
+
diff --git a/src/portable/sunxi/musb_def.h b/src/portable/sunxi/musb_def.h
new file mode 100644
index 000000000..f55ddab3b
--- /dev/null
+++ b/src/portable/sunxi/musb_def.h
@@ -0,0 +1,615 @@
+#ifndef _TUSB_MUSB_DEF
+#define _TUSB_MUSB_DEF
+
+
+#define  USBC_Readb(reg)	                    (*(volatile unsigned char *)(reg))
+#define  USBC_Readw(reg)	                    (*(volatile unsigned short *)(reg))
+#define  USBC_Readl(reg)	                    (*(volatile unsigned long *)(reg))
+
+#define  USBC_Writeb(value, reg)                (*(volatile unsigned char *)(reg) = (value))
+#define  USBC_Writew(value, reg)	            (*(volatile unsigned short *)(reg) = (value))
+#define  USBC_Writel(value, reg)	            (*(volatile unsigned long *)(reg) = (value))
+
+
+#define USBC_SetBit_Mask_b(reg,mask)	do {																		\
+																				unsigned char _r = USBC_Readb(reg);	\
+																			   _r  |=  (unsigned char)(mask);				\
+																				USBC_Writeb(_r,reg); 								\
+																		}while(0)
+#define USBC_SetBit_Mask_w(reg,mask)	do {																		\
+																				unsigned short _r = USBC_Readw(reg);	\
+																			   _r  |=  (unsigned short)(mask);				\
+																				USBC_Writew(_r,reg); 								\
+																		}while(0)
+#define USBC_SetBit_Mask_l(reg,mask)	do {																		\
+																				unsigned int _r = USBC_Readl(reg);	\
+																			   _r  |=  (unsigned int)(mask);				\
+																				USBC_Writel(_r,reg); 								\
+																		}while(0)
+
+
+#define USBC_ClrBit_Mask_b(reg,mask)	do {																		\
+																				unsigned char _r = USBC_Readb(reg);	\
+																			   _r  &=  (~(unsigned char)(mask));			\
+																				USBC_Writeb(_r,reg); 								\
+																		}while(0);
+#define USBC_ClrBit_Mask_w(reg,mask)	do {																		\
+																				unsigned short _r = USBC_Readw(reg);	\
+																			   _r  &=  (~(unsigned short)(mask));				\
+																				USBC_Writew(_r,reg); 								\
+																		}while(0)
+#define USBC_ClrBit_Mask_l(reg,mask)	do {																		\
+																				unsigned int _r = USBC_Readl(reg);	\
+																			   _r  &=  (~(unsigned int)(mask));				\
+																				USBC_Writel(_r,reg); 								\
+																		}while(0)
+#define  USBC_REG_test_bit_b(bp, reg)         	(USBC_Readb(reg) & (1 << (bp)))
+#define  USBC_REG_test_bit_w(bp, reg)   	    (USBC_Readw(reg) & (1 << (bp)))
+#define  USBC_REG_test_bit_l(bp, reg)   	    (USBC_Readl(reg) & (1 << (bp)))
+
+#define  USBC_REG_set_bit_b(bp, reg) 			(USBC_Writeb((USBC_Readb(reg) | (1 << (bp))) , (reg)))
+#define  USBC_REG_set_bit_w(bp, reg) 	 		(USBC_Writew((USBC_Readw(reg) | (1 << (bp))) , (reg)))
+#define  USBC_REG_set_bit_l(bp, reg) 	 		(USBC_Writel((USBC_Readl(reg) | (1 << (bp))) , (reg)))
+
+#define  USBC_REG_clear_bit_b(bp, reg)	 	 	(USBC_Writeb((USBC_Readb(reg) & (~ (1 << (bp)))) , (reg)))
+#define  USBC_REG_clear_bit_w(bp, reg)	 	 	(USBC_Writew((USBC_Readw(reg) & (~ (1 << (bp)))) , (reg)))
+#define  USBC_REG_clear_bit_l(bp, reg)	 	 	(USBC_Writel((USBC_Readl(reg) & (~ (1 << (bp)))) , (reg)))
+
+#define SW_UDC_EPNUMS 3
+
+#define SUNXI_SRAMC_BASE 0x01c00000
+//---------------------------------------------------------------
+//   reg base
+//---------------------------------------------------------------
+#define  USBC0_BASE                 0x01c13000
+#define  USBC1_BASE                 0x01c14000
+#define  USBC2_BASE                 0x01c1E000
+
+//Some reg whithin musb
+#define USBPHY_CLK_REG 		0x01c200CC
+#define USBPHY_CLK_RST_BIT 0
+#define USBPHY_CLK_GAT_BIT 1
+
+#define BUS_CLK_RST_REG	0x01c202c0 //Bus Clock Reset Register Bit24 : USB CLK RST
+#define BUS_RST_USB_BIT	24
+
+#define BUS_CLK_GATE0_REG	0x01c20060 //Bus Clock Gating Register Bit24 : USB CLK GATE 0: Mask 1 : Pass
+#define BUS_CLK_USB_BIT	24
+
+//#define USB_INTR
+
+#define NDMA_CFG_REG
+//-----------------------------------------------------------------------
+//   musb reg offset
+//-----------------------------------------------------------------------
+
+#define  USBC_REG_o_FADDR		    0x0098
+#define  USBC_REG_o_PCTL		    0x0040
+#define  USBC_REG_o_INTTx		    0x0044
+#define  USBC_REG_o_INTRx		    0x0046
+#define  USBC_REG_o_INTTxE		    0x0048
+#define  USBC_REG_o_INTRxE		    0x004A
+#define  USBC_REG_o_INTUSB		    0x004C
+#define  USBC_REG_o_INTUSBE         0x0050
+#define  USBC_REG_o_FRNUM		    0x0054
+#define  USBC_REG_o_EPIND		    0x0042
+#define  USBC_REG_o_TMCTL		    0x007C
+
+#define  USBC_REG_o_TXMAXP		    0x0080
+#define  USBC_REG_o_CSR0		    0x0082
+#define  USBC_REG_o_TXCSR		    0x0082
+#define  USBC_REG_o_RXMAXP		    0x0084
+#define  USBC_REG_o_RXCSR		    0x0086
+#define  USBC_REG_o_COUNT0		    0x0088
+#define  USBC_REG_o_RXCOUNT		    0x0088
+#define  USBC_REG_o_EP0TYPE		    0x008C
+#define  USBC_REG_o_TXTYPE		    0x008C
+#define  USBC_REG_o_NAKLIMIT0	    0x008D
+#define  USBC_REG_o_TXINTERVAL      0x008D
+#define  USBC_REG_o_RXTYPE		    0x008E
+#define  USBC_REG_o_RXINTERVAL	    0x008F
+
+//#define  USBC_REG_o_CONFIGDATA	0x001F   //
+
+#define  USBC_REG_o_EPFIFO0		    0x0000
+#define  USBC_REG_o_EPFIFO1		    0x0004
+#define  USBC_REG_o_EPFIFO2		    0x0008
+#define  USBC_REG_o_EPFIFO3		    0x000C
+#define  USBC_REG_o_EPFIFO4		    0x0010
+#define  USBC_REG_o_EPFIFO5		    0x0014
+#define  USBC_REG_o_EPFIFOx(n)	    (0x0000 + (n<<2))
+
+#define  USBC_REG_o_DEVCTL		    0x0041
+
+#define  USBC_REG_o_TXFIFOSZ	    0x0090
+#define  USBC_REG_o_RXFIFOSZ	    0x0094
+#define  USBC_REG_o_TXFIFOAD	    0x0092
+#define  USBC_REG_o_RXFIFOAD	    0x0096
+
+#define  USBC_REG_o_VEND0		    0x0043
+#define  USBC_REG_o_VEND1		    0x007D
+#define  USBC_REG_o_VEND3		    0x007E
+
+//#define  USBC_REG_o_PHYCTL		0x006C
+#define  USBC_REG_o_EPINFO		    0x0078
+#define  USBC_REG_o_RAMINFO		    0x0079
+#define  USBC_REG_o_LINKINFO	    0x007A
+#define  USBC_REG_o_VPLEN		    0x007B
+#define  USBC_REG_o_HSEOF		    0x007C
+#define  USBC_REG_o_FSEOF		    0x007D
+#define  USBC_REG_o_LSEOF		    0x007E
+
+//new
+#define  USBC_REG_o_FADDR0          0x0098
+#define  USBC_REG_o_HADDR0          0x009A
+#define  USBC_REG_o_HPORT0          0x009B
+#define  USBC_REG_o_TXFADDRx 		0x0098
+#define  USBC_REG_o_TXHADDRx		0x009A
+#define  USBC_REG_o_TXHPORTx		0x009B
+#define  USBC_REG_o_RXFADDRx		0x009C
+#define  USBC_REG_o_RXHADDRx		0x009E
+#define  USBC_REG_o_RXHPORTx		0x009F
+
+
+#define  USBC_REG_o_RPCOUNT			0x008A
+
+//new
+#define  USBC_REG_o_ISCR            0x0400
+#define  USBC_REG_o_PHYCTL          0x0404
+#define  USBC_REG_o_PHYBIST         0x0408
+#define  USBC_REG_o_PHYTUNE         0x040c
+
+#define  USBC_REG_o_CSR			0x0410
+
+#define USBC_REG_o_PMU_IRQ	 0x0800
+
+//-----------------------------------------------------------------------
+//   registers
+//-----------------------------------------------------------------------
+
+#define  USBC_REG_FADDR(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_FADDR		)
+#define  USBC_REG_PCTL(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_PCTL			)
+#define  USBC_REG_INTTx(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_INTTx		)
+#define  USBC_REG_INTRx(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_INTRx		)
+#define  USBC_REG_INTTxE(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_INTTxE     	)
+#define  USBC_REG_INTRxE(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_INTRxE     	)
+#define  USBC_REG_INTUSB(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_INTUSB     	)
+#define  USBC_REG_INTUSBE(usbc_base_addr)           ((usbc_base_addr) + USBC_REG_o_INTUSBE    	)
+#define  USBC_REG_FRNUM(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_FRNUM      	)
+#define  USBC_REG_EPIND(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_EPIND      	)
+#define  USBC_REG_TMCTL(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_TMCTL      	)
+#define  USBC_REG_TXMAXP(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_TXMAXP     	)
+
+#define  USBC_REG_CSR0(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_CSR0       	)
+#define  USBC_REG_TXCSR(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_TXCSR      	)
+
+#define  USBC_REG_RXMAXP(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_RXMAXP     	)
+#define  USBC_REG_RXCSR(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_RXCSR      	)
+
+#define  USBC_REG_COUNT0(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_COUNT0     	)
+#define  USBC_REG_RXCOUNT(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_RXCOUNT    	)
+
+#define  USBC_REG_EP0TYPE(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_EP0TYPE		)
+#define  USBC_REG_TXTYPE(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_TXTYPE     	)
+
+#define  USBC_REG_NAKLIMIT0(usbc_base_addr)	        ((usbc_base_addr) + USBC_REG_o_NAKLIMIT0  	)
+#define  USBC_REG_TXINTERVAL(usbc_base_addr)        ((usbc_base_addr) + USBC_REG_o_TXINTERVAL	)
+
+#define  USBC_REG_RXTYPE(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_RXTYPE		)
+#define  USBC_REG_RXINTERVAL(usbc_base_addr)	    ((usbc_base_addr) + USBC_REG_o_RXINTERVAL	)
+//#define  USBC_REG_CONFIGDATA(usbc_base_addr)	    ((usbc_base_addr) + USBC_REG_o_CONFIGDATA	)
+#define  USBC_REG_EPFIFO0(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_EPFIFO0		)
+#define  USBC_REG_EPFIFO1(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_EPFIFO1		)
+#define  USBC_REG_EPFIFO2(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_EPFIFO2		)
+#define  USBC_REG_EPFIFO3(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_EPFIFO3		)
+#define  USBC_REG_EPFIFO4(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_EPFIFO4		)
+#define  USBC_REG_EPFIFO5(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_EPFIFO5		)
+#define  USBC_REG_EPFIFOx(usbc_base_addr, n)	    ((usbc_base_addr) + USBC_REG_o_EPFIFOx(n)	)
+#define  USBC_REG_DEVCTL(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_DEVCTL		)
+#define  USBC_REG_TXFIFOSZ(usbc_base_addr)	        ((usbc_base_addr) + USBC_REG_o_TXFIFOSZ		)
+#define  USBC_REG_RXFIFOSZ(usbc_base_addr)	        ((usbc_base_addr) + USBC_REG_o_RXFIFOSZ		)
+#define  USBC_REG_TXFIFOAD(usbc_base_addr)	        ((usbc_base_addr) + USBC_REG_o_TXFIFOAD		)
+#define  USBC_REG_RXFIFOAD(usbc_base_addr)	        ((usbc_base_addr) + USBC_REG_o_RXFIFOAD		)
+#define  USBC_REG_VEND0(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_VEND0		)
+#define  USBC_REG_VEND1(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_VEND1		)
+#define  USBC_REG_EPINFO(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_EPINFO		)
+#define  USBC_REG_RAMINFO(usbc_base_addr)		    ((usbc_base_addr) + USBC_REG_o_RAMINFO		)
+#define  USBC_REG_LINKINFO(usbc_base_addr)	        ((usbc_base_addr) + USBC_REG_o_LINKINFO		)
+#define  USBC_REG_VPLEN(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_VPLEN		)
+#define  USBC_REG_HSEOF(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_HSEOF		)
+#define  USBC_REG_FSEOF(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_FSEOF		)
+#define  USBC_REG_LSEOF(usbc_base_addr)		        ((usbc_base_addr) + USBC_REG_o_LSEOF		)
+
+#define  USBC_REG_FADDR0(usbc_base_addr)            ((usbc_base_addr) + USBC_REG_o_FADDR0		)
+#define  USBC_REG_HADDR0(usbc_base_addr)            ((usbc_base_addr) + USBC_REG_o_HADDR0		)
+#define  USBC_REG_HPORT0(usbc_base_addr)            ((usbc_base_addr) + USBC_REG_o_HPORT0		)
+
+#define  USBC_REG_TXFADDRx(usbc_base_addr, n)		((usbc_base_addr) + USBC_REG_o_TXFADDRx		)
+#define  USBC_REG_TXHADDRx(usbc_base_addr, n)		((usbc_base_addr) + USBC_REG_o_TXHADDRx		)
+#define  USBC_REG_TXHPORTx(usbc_base_addr, n)		((usbc_base_addr) + USBC_REG_o_TXHPORTx		)
+#define  USBC_REG_RXFADDRx(usbc_base_addr, n)		((usbc_base_addr) + USBC_REG_o_RXFADDRx		)
+#define  USBC_REG_RXHADDRx(usbc_base_addr, n)		((usbc_base_addr) + USBC_REG_o_RXHADDRx		)
+#define  USBC_REG_RXHPORTx(usbc_base_addr, n)		((usbc_base_addr) + USBC_REG_o_RXHPORTx		)
+
+#define  USBC_REG_RPCOUNTx(usbc_base_addr, n)	    ((usbc_base_addr) + USBC_REG_o_RPCOUNT		)
+
+#define  USBC_REG_ISCR(usbc_base_addr)	    	    ((usbc_base_addr) + USBC_REG_o_ISCR			)
+#define  USBC_REG_PHYCTL(usbc_base_addr)	        ((usbc_base_addr) + USBC_REG_o_PHYCTL		)
+#define  USBC_REG_PHYBIST(usbc_base_addr)	        ((usbc_base_addr) + USBC_REG_o_PHYBIST		)
+#define  USBC_REG_PHYTUNE(usbc_base_addr)           ((usbc_base_addr) + USBC_REG_o_PHYTUNE		)
+#define  USBC_REG_PMU_IRQ(usbc_base_addr)           ((usbc_base_addr) + USBC_REG_o_PMU_IRQ		)
+#define  USBC_REG_CSR(usbc_base_addr)           ((usbc_base_addr) + USBC_REG_o_CSR)
+//-----------------------------------------------------------------------
+//   bit position
+//-----------------------------------------------------------------------
+
+/* USB Power Control for Host only  */
+#define  USBC_BP_POWER_H_HIGH_SPEED_EN			5
+#define  USBC_BP_POWER_H_HIGH_SPEED_FLAG		4
+#define  USBC_BP_POWER_H_RESET					3
+#define  USBC_BP_POWER_H_RESUME					2
+#define  USBC_BP_POWER_H_SUSPEND				1
+#define  USBC_BP_POWER_H_SUEPEND_EN				0
+
+/* USB Power Control for device only  */
+#define  USBC_BP_POWER_D_ISO_UPDATE_EN			7
+#define  USBC_BP_POWER_D_SOFT_CONNECT			6
+#define  USBC_BP_POWER_D_HIGH_SPEED_EN			5
+#define  USBC_BP_POWER_D_HIGH_SPEED_FLAG		4
+#define  USBC_BP_POWER_D_RESET_FLAG				3
+#define  USBC_BP_POWER_D_RESUME					2
+#define  USBC_BP_POWER_D_SUSPEND				1
+#define  USBC_BP_POWER_D_ENABLE_SUSPENDM		0
+
+/* interrupt flags for ep0 and the Tx ep1~4 */
+#define  USBC_BP_INTTx_FLAG_EP5				    5
+#define  USBC_BP_INTTx_FLAG_EP4				    4
+#define  USBC_BP_INTTx_FLAG_EP3				    3
+#define  USBC_BP_INTTx_FLAG_EP2		    		2
+#define  USBC_BP_INTTx_FLAG_EP1  				1
+#define  USBC_BP_INTTx_FLAG_EP0					0
+
+/* interrupt flags for Rx ep1~4 */
+#define  USBC_BP_INTRx_FLAG_EP5				    5
+#define  USBC_BP_INTRx_FLAG_EP4				    4
+#define  USBC_BP_INTRx_FLAG_EP3				    3
+#define  USBC_BP_INTRx_FLAG_EP2				    2
+#define  USBC_BP_INTRx_FLAG_EP1				    1
+
+/* interrupt enable for Tx ep0~4 */
+#define  USBC_BP_INTTxE_EN_EP5				    5
+#define  USBC_BP_INTTxE_EN_EP4				    4
+#define  USBC_BP_INTTxE_EN_EP3				    3
+#define  USBC_BP_INTTxE_EN_EP2				    2
+#define  USBC_BP_INTTxE_EN_EP1				    1
+#define  USBC_BP_INTTxE_EN_EP0					0
+
+/* interrupt enable for Rx ep1~4 */
+#define  USBC_BP_INTRxE_EN_EP5				    5
+#define  USBC_BP_INTRxE_EN_EP4				    4
+#define  USBC_BP_INTRxE_EN_EP3				    3
+#define  USBC_BP_INTRxE_EN_EP2			    	2
+#define  USBC_BP_INTRxE_EN_EP1  		    	1
+
+/* USB interrupt */
+#define  USBC_BP_INTUSB_VBUS_ERROR				7
+#define  USBC_BP_INTUSB_SESSION_REQ				6
+#define  USBC_BP_INTUSB_DISCONNECT				5
+#define  USBC_BP_INTUSB_CONNECT					4
+#define  USBC_BP_INTUSB_SOF						3
+#define  USBC_BP_INTUSB_RESET					2
+#define  USBC_BP_INTUSB_RESUME					1
+#define  USBC_BP_INTUSB_SUSPEND					0
+
+/* USB interrupt enable */
+#define  USBC_BP_INTUSBE_EN_VBUS_ERROR			7
+#define  USBC_BP_INTUSBE_EN_SESSION_REQ			6
+#define  USBC_BP_INTUSBE_EN_DISCONNECT			5
+#define  USBC_BP_INTUSBE_EN_CONNECT				4
+#define  USBC_BP_INTUSBE_EN_SOF					3
+#define  USBC_BP_INTUSBE_EN_RESET				2
+#define  USBC_BP_INTUSBE_EN_RESUME				1
+#define  USBC_BP_INTUSBE_EN_SUSPEND				0
+
+/* Test Mode Control */
+#define  USBC_BP_TMCTL_FORCE_HOST               7
+#define  USBC_BP_TMCTL_FIFO_ACCESS              6
+#define  USBC_BP_TMCTL_FORCE_FS                 5
+#define  USBC_BP_TMCTL_FORCE_HS                 4
+#define  USBC_BP_TMCTL_TEST_PACKET              3
+#define  USBC_BP_TMCTL_TEST_K                   2
+#define  USBC_BP_TMCTL_TEST_J                   1
+#define  USBC_BP_TMCTL_TEST_SE0_NAK             0
+
+/* Tx Max packet */
+#define  USBC_BP_TXMAXP_PACKET_COUNT            11
+#define  USBC_BP_TXMAXP_MAXIMUM_PAYLOAD         0
+
+/* Control and Status Register for ep0 for Host only */
+#define  USBC_BP_CSR0_H_DisPing 				11
+#define  USBC_BP_CSR0_H_FlushFIFO				8
+#define  USBC_BP_CSR0_H_NAK_Timeout				7
+#define  USBC_BP_CSR0_H_StatusPkt				6
+#define  USBC_BP_CSR0_H_ReqPkt					5
+#define  USBC_BP_CSR0_H_Error					4
+#define  USBC_BP_CSR0_H_SetupPkt				3
+#define  USBC_BP_CSR0_H_RxStall					2
+#define  USBC_BP_CSR0_H_TxPkRdy					1
+#define  USBC_BP_CSR0_H_RxPkRdy					0
+
+/* Control and Status Register for ep0 for device only */
+#define  USBC_BP_CSR0_D_FLUSH_FIFO				8
+#define  USBC_BP_CSR0_D_SERVICED_SETUP_END		7
+#define  USBC_BP_CSR0_D_SERVICED_RX_PKT_READY   6
+#define  USBC_BP_CSR0_D_SEND_STALL				5
+#define  USBC_BP_CSR0_D_SETUP_END				4
+#define  USBC_BP_CSR0_D_DATA_END				3
+#define  USBC_BP_CSR0_D_SENT_STALL				2
+#define  USBC_BP_CSR0_D_TX_PKT_READY			1
+#define  USBC_BP_CSR0_D_RX_PKT_READY			0
+
+/* Tx ep Control and Status Register for Host only */
+#define  USBC_BP_TXCSR_H_AUTOSET				15
+#define  USBC_BP_TXCSR_H_RESERVED				14
+#define  USBC_BP_TXCSR_H_MODE				    13
+#define  USBC_BP_TXCSR_H_DMA_REQ_EN			 	12
+#define  USBC_BP_TXCSR_H_FORCE_DATA_TOGGLE		11
+#define  USBC_BP_TXCSR_H_DMA_REQ_MODE			10
+#define  USBC_BP_TXCSR_H_NAK_TIMEOUT			7
+#define  USBC_BP_TXCSR_H_CLEAR_DATA_TOGGLE		6
+#define  USBC_BP_TXCSR_H_TX_STALL				5
+#define  USBC_BP_TXCSR_H_FLUSH_FIFO				3
+#define  USBC_BP_TXCSR_H_ERROR					2
+#define  USBC_BP_TXCSR_H_FIFO_NOT_EMPTY 		1
+#define  USBC_BP_TXCSR_H_TX_READY				0
+
+/* Tx ep Control and Status Register for Device only */
+#define  USBC_BP_TXCSR_D_AUTOSET				15
+#define  USBC_BP_TXCSR_D_ISO					14
+#define  USBC_BP_TXCSR_D_MODE					13
+#define  USBC_BP_TXCSR_D_DMA_REQ_EN				12
+#define  USBC_BP_TXCSR_D_FORCE_DATA_TOGGLE		11
+#define  USBC_BP_TXCSR_D_DMA_REQ_MODE			10
+#define  USBC_BP_TXCSR_D_INCOMPLETE				7
+#define  USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE		6
+#define  USBC_BP_TXCSR_D_SENT_STALL				5
+#define  USBC_BP_TXCSR_D_SEND_STALL				4
+#define  USBC_BP_TXCSR_D_FLUSH_FIFO				3
+#define  USBC_BP_TXCSR_D_UNDER_RUN				2
+#define  USBC_BP_TXCSR_D_FIFO_NOT_EMPTY 		1
+#define  USBC_BP_TXCSR_D_TX_READY				0
+
+/* Rx Max Packet */
+#define  USBC_BP_RXMAXP_PACKET_COUNT            11
+#define  USBC_BP_RXMAXP_MAXIMUM_PAYLOAD         0
+
+/* Rx ep Control and Status Register for Host only */
+#define  USBC_BP_RXCSR_H_AUTO_CLEAR			    15
+#define  USBC_BP_RXCSR_H_AUTO_REQ			    14
+#define  USBC_BP_RXCSR_H_DMA_REQ_EN			    13
+#define  USBC_BP_RXCSR_H_PID_ERROR			    12
+#define  USBC_BP_RXCSR_H_DMA_REQ_MODE		    11
+
+#define  USBC_BP_RXCSR_H_INCOMPLETE			    8
+#define  USBC_BP_RXCSR_H_CLEAR_DATA_TOGGLE	    7
+#define  USBC_BP_RXCSR_H_RX_STALL			    6
+#define  USBC_BP_RXCSR_H_REQ_PACKET			    5
+#define  USBC_BP_RXCSR_H_FLUSH_FIFO			    4
+#define  USBC_BP_RXCSR_H_NAK_TIMEOUT		    3
+#define  USBC_BP_RXCSR_H_ERROR				    2
+#define  USBC_BP_RXCSR_H_FIFO_FULL			    1
+#define  USBC_BP_RXCSR_H_RX_PKT_READY		    0
+
+/* Rx ep Control and Status Register for Device only */
+#define  USBC_BP_RXCSR_D_AUTO_CLEAR			    15
+#define  USBC_BP_RXCSR_D_ISO				    14
+#define  USBC_BP_RXCSR_D_DMA_REQ_EN			    13
+#define  USBC_BP_RXCSR_D_DISABLE_NYET		    12
+#define  USBC_BP_RXCSR_D_DMA_REQ_MODE		    11
+
+#define  USBC_BP_RXCSR_D_INCOMPLETE			    8
+#define  USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE	    7
+#define  USBC_BP_RXCSR_D_SENT_STALL			    6
+#define  USBC_BP_RXCSR_D_SEND_STALL			    5
+#define  USBC_BP_RXCSR_D_FLUSH_FIFO			    4
+#define  USBC_BP_RXCSR_D_DATA_ERROR			    3
+#define  USBC_BP_RXCSR_D_OVERRUN			    2
+#define  USBC_BP_RXCSR_D_FIFO_FULL			    1
+#define  USBC_BP_RXCSR_D_RX_PKT_READY		    0
+
+/* Tx Type Register for host only */
+#define  USBC_BP_TXTYPE_SPEED	                6              //new
+#define  USBC_BP_TXTYPE_PROROCOL	            4
+#define  USBC_BP_TXTYPE_TARGET_EP_NUM           0
+
+/* Rx Type Register for host only */
+#define  USBC_BP_RXTYPE_SPEED		            6              //new
+#define  USBC_BP_RXTYPE_PROROCOL	            4
+#define  USBC_BP_RXTYPE_TARGET_EP_NUM           0
+
+/* Core Configueation */
+#define  USBC_BP_CONFIGDATA_MPRXE               7
+#define  USBC_BP_CONFIGDATA_MPTXE               6
+#define  USBC_BP_CONFIGDATA_BIGENDIAN		    5
+#define  USBC_BP_CONFIGDATA_HBRXE			    4
+#define  USBC_BP_CONFIGDATA_HBTXE			    3
+#define  USBC_BP_CONFIGDATA_DYNFIFO_SIZING	    2
+#define  USBC_BP_CONFIGDATA_SOFTCONE		    1
+#define  USBC_BP_CONFIGDATA_UTMI_DATAWIDTH	    0
+
+/* OTG Device Control */
+#define  USBC_BP_DEVCTL_B_DEVICE			    7
+#define  USBC_BP_DEVCTL_FS_DEV				    6
+#define  USBC_BP_DEVCTL_LS_DEV				    5
+
+#define  USBC_BP_DEVCTL_VBUS				    3
+#define  USBC_BP_DEVCTL_HOST_MODE			    2
+#define  USBC_BP_DEVCTL_HOST_REQ			    1
+#define  USBC_BP_DEVCTL_SESSION				    0
+
+/* Tx EP FIFO size control */
+#define  USBC_BP_TXFIFOSZ_DPB				    4
+#define  USBC_BP_TXFIFOSZ_SZ				    0
+
+/* Rx EP FIFO size control */
+#define  USBC_BP_RXFIFOSZ_DPB				    4
+#define  USBC_BP_RXFIFOSZ_SZ				    0
+
+/* vendor0 */
+#define  USBC_BP_VEND0_DRQ_SEL				    1
+#define  USBC_BP_VEND0_BUS_SEL				    0
+
+/* hub address */
+#define  USBC_BP_HADDR_MULTI_TT					7
+
+/* Interface Status and Control */
+#define  USBC_BP_ISCR_VBUS_VALID_FROM_DATA		30
+#define  USBC_BP_ISCR_VBUS_VALID_FROM_VBUS		29
+#define  USBC_BP_ISCR_EXT_ID_STATUS				28
+#define  USBC_BP_ISCR_EXT_DM_STATUS				27
+#define  USBC_BP_ISCR_EXT_DP_STATUS				26
+#define  USBC_BP_ISCR_MERGED_VBUS_STATUS		25
+#define  USBC_BP_ISCR_MERGED_ID_STATUS			24
+
+#define  USBC_BP_ISCR_ID_PULLUP_EN				17
+#define  USBC_BP_ISCR_DPDM_PULLUP_EN			16
+#define  USBC_BP_ISCR_FORCE_ID					14
+#define  USBC_BP_ISCR_FORCE_VBUS_VALID			12
+#define  USBC_BP_ISCR_VBUS_VALID_SRC			10
+
+#define  USBC_BP_ISCR_HOSC_EN                 	7
+#define  USBC_BP_ISCR_VBUS_CHANGE_DETECT      	6
+#define  USBC_BP_ISCR_ID_CHANGE_DETECT        	5
+#define  USBC_BP_ISCR_DPDM_CHANGE_DETECT      	4
+#define  USBC_BP_ISCR_IRQ_ENABLE              	3
+#define  USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN   	2
+#define  USBC_BP_ISCR_ID_CHANGE_DETECT_EN     	1
+#define  USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN   	0
+
+
+#define SUNXI_EHCI_AHB_ICHR8_EN		(1 << 10)
+#define SUNXI_EHCI_AHB_INCR4_BURST_EN	(1 << 9)
+#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN	(1 << 8)
+#define SUNXI_EHCI_ULPI_BYPASS_EN	(1 << 0)
+//-----------------------------------------------------------------------
+//   �Զ���
+//-----------------------------------------------------------------------
+
+/* usb��Դ���� */
+#define  USBC_MAX_CTL_NUM                   1
+#define  USBC_MAX_EP_NUM                    3   //ep0~2, ep�ĸ���
+#define  USBC_MAX_FIFO_SIZE                 (2 * 1024)
+
+/* usb OTG mode */
+#define  USBC_OTG_HOST                      0
+#define  USBC_OTG_DEVICE                    1
+
+/* usb device type */
+#define  USBC_DEVICE_HSDEV                  0
+#define  USBC_DEVICE_FSDEV                  1
+#define  USBC_DEVICE_LSDEV                  2
+
+/*  usb transfer type  */
+#define  USBC_TS_TYPE_IDLE                  0
+#define  USBC_TS_TYPE_CTRL                  1
+#define  USBC_TS_TYPE_ISO                   2
+#define  USBC_TS_TYPE_INT                   3
+#define  USBC_TS_TYPE_BULK                  4
+
+/*  usb transfer mode  */
+#define  USBC_TS_MODE_UNKOWN                0
+#define  USBC_TS_MODE_LS                    1
+#define  USBC_TS_MODE_FS                    2
+#define  USBC_TS_MODE_HS                    3
+
+/* usb Vbus status */
+#define  USBC_VBUS_STATUS_BELOW_SESSIONEND                 0
+#define  USBC_VBUS_STATUS_ABOVE_SESSIONEND_BELOW_AVALID    1
+#define  USBC_VBUS_STATUS_ABOVE_AVALID_BELOW_VBUSVALID     2
+#define  USBC_VBUS_STATUS_ABOVE_VBUSVALID                  3
+
+/* usb io type */
+#define  USBC_IO_TYPE_PIO    		        0
+#define  USBC_IO_TYPE_DMA    		        1
+
+/* usb ep type */
+#define  USBC_EP_TYPE_IDLE    		        0
+#define  USBC_EP_TYPE_EP0    		        1
+#define  USBC_EP_TYPE_TX     		        2
+#define  USBC_EP_TYPE_RX     		        3
+
+/* usb id type */
+#define  USBC_ID_TYPE_DISABLE      	        0
+#define  USBC_ID_TYPE_HOST         	        1
+#define  USBC_ID_TYPE_DEVICE       	        2
+
+/* usb vbus valid type */
+#define  USBC_VBUS_TYPE_DISABLE    	        0
+#define  USBC_VBUS_TYPE_LOW       	        1
+#define  USBC_VBUS_TYPE_HIGH       	        2
+
+/* usb a valid source */
+#define  USBC_A_VALID_SOURCE_UTMI_AVALID	0
+#define  USBC_A_VALID_SOURCE_UTMI_VBUS    	1
+
+/* usb device switch */
+#define  USBC_DEVICE_SWITCH_OFF             0
+#define  USBC_DEVICE_SWITCH_ON              1
+
+/* usb fifo config mode */
+#define  USBC_FIFO_MODE_4K                  0
+#define  USBC_FIFO_MODE_8K                  1
+
+/*
+ **************************************************
+ *  usb interrupt mask
+ *
+ **************************************************
+ */
+
+/* interrupt flags for ep0 and the Tx ep1~4 */
+#define  USBC_INTTx_FLAG_EP5				    (1 << USBC_BP_INTTx_FLAG_EP5)
+#define  USBC_INTTx_FLAG_EP4				    (1 << USBC_BP_INTTx_FLAG_EP4)
+#define  USBC_INTTx_FLAG_EP3				    (1 << USBC_BP_INTTx_FLAG_EP3)
+#define  USBC_INTTx_FLAG_EP2		    		(1 << USBC_BP_INTTx_FLAG_EP2)
+#define  USBC_INTTx_FLAG_EP1  				    (1 << USBC_BP_INTTx_FLAG_EP1)
+#define  USBC_INTTx_FLAG_EP0					(1 << USBC_BP_INTTx_FLAG_EP0)
+
+/* interrupt flags for Rx ep1~4 */
+#define  USBC_INTRx_FLAG_EP5				    (1 << USBC_BP_INTRx_FLAG_EP5)
+#define  USBC_INTRx_FLAG_EP4				    (1 << USBC_BP_INTRx_FLAG_EP4)
+#define  USBC_INTRx_FLAG_EP3				    (1 << USBC_BP_INTRx_FLAG_EP3)
+#define  USBC_INTRx_FLAG_EP2				    (1 << USBC_BP_INTRx_FLAG_EP2)
+#define  USBC_INTRx_FLAG_EP1				    (1 << USBC_BP_INTRx_FLAG_EP1)
+
+/* USB interrupt */
+#define  USBC_INTUSB_VBUS_ERROR				    (1 << USBC_BP_INTUSB_VBUS_ERROR)
+#define  USBC_INTUSB_SESSION_REQ				(1 << USBC_BP_INTUSB_SESSION_REQ)
+#define  USBC_INTUSB_DISCONNECT				    (1 << USBC_BP_INTUSB_DISCONNECT)
+#define  USBC_INTUSB_CONNECT					(1 << USBC_BP_INTUSB_CONNECT)
+#define  USBC_INTUSB_SOF						(1 << USBC_BP_INTUSB_SOF)
+#define  USBC_INTUSB_RESET					    (1 << USBC_BP_INTUSB_RESET)
+#define  USBC_INTUSB_RESUME					    (1 << USBC_BP_INTUSB_RESUME)
+#define  USBC_INTUSB_SUSPEND					(1 << USBC_BP_INTUSB_SUSPEND)
+
+#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
+#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
+#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
+#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
+#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
+#define USB_CSRL0_STALL         0x00000020  // Send Stall
+#define USB_CSRL0_SETEND        0x00000010  // Setup End
+#define USB_CSRL0_ERROR         0x00000010  // Error
+#define USB_CSRL0_DATAEND       0x00000008  // Data End
+#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
+#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
+#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
+#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
+
+#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+
+#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+
+#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index dcf1c4614..dbdc83c6b 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -136,6 +136,9 @@
 // Infineon
 #define OPT_MCU_XMC4000          1800 ///< Infineon XMC4000
 
+// Allwinner
+#define OPT_MCU_F1C100S          1900 ///< Allwinner F1C100s family
+
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
 #define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == _m)

From c9d9bfab924244da285895d1d594900e8de303fe Mon Sep 17 00:00:00 2001
From: Sebastien COUDREAU <sebastien.coudreau@fastlite.com>
Date: Wed, 1 Dec 2021 17:10:31 +0100
Subject: [PATCH 0696/2085] Remove unused-parameter errors when LOGGER=SWO

---
 hw/bsp/board.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 6a26f55b7..98addca99 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -126,6 +126,8 @@ TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
 TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 {
   (void) fhdl;
+  (void) buf;
+  (void) count;
   return 0;
 }
 

From 61a9e125db82ed73b56e7111c3b63c85edbf8d0b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Dec 2021 23:19:17 +0700
Subject: [PATCH 0697/2085] more ci abstract

---
 hw/bsp/imxrt/family.mk                       |  4 +-
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h    | 61 ++++++++++++++
 src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h | 57 +++++++++++++
 src/portable/chipidea/ci_hs/ci_hs_type.h     | 80 ++++++++++--------
 src/portable/chipidea/ci_hs/dcd_ci_hs.c      | 86 ++++++--------------
 5 files changed, 189 insertions(+), 99 deletions(-)
 create mode 100644 src/portable/chipidea/ci_hs/ci_hs_imxrt.h
 create mode 100644 src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h

diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index a919d3698..d086d503f 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -28,7 +28,9 @@ LDFLAGS += \
 	-Wl,--defsym,__stack_size__=0x800 \
 
 SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
 	$(MCU_DIR)/system_$(MCU_VARIANT).c \
 	$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
 	$(MCU_DIR)/project_template/clock_config.c \
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
new file mode 100644
index 000000000..3c92dccb6
--- /dev/null
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -0,0 +1,61 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_HS_IMXRT_H_
+#define _CI_HS_IMXRT_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "fsl_device_registers.h"
+
+static const dcd_controller_t _dcd_controller[] =
+{
+  // RT1010 and RT1020 only has 1 USB controller
+  #if FSL_FEATURE_SOC_USBHS_COUNT == 1
+    { .regs = (ci_hs_regs_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
+  #else
+    { .regs = (ci_hs_regs_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
+    { .regs = (ci_hs_regs_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
+  #endif
+};
+
+void dcd_int_enable(uint8_t rhport)
+{
+  NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
new file mode 100644
index 000000000..c4f94820d
--- /dev/null
+++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
@@ -0,0 +1,57 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_HS_LPC18_43_H_
+#define _CI_HS_LPC18_43_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LPCOpen for 18xx & 43xx
+#include "chip.h"
+
+static const dcd_controller_t _dcd_controller[] =
+{
+  { .regs = (ci_hs_regs_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
+  { .regs = (ci_hs_regs_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
+};
+
+void dcd_int_enable(uint8_t rhport)
+{
+  NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h
index 402c26334..772a7e413 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_type.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_type.h
@@ -85,49 +85,57 @@ enum {
 typedef struct
 {
   //------------- ID + HW Parameter Registers-------------//
-  __I  uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
+  volatile uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
 
   //------------- Capability Registers-------------//
-  __I  uint8_t  CAPLENGTH;       ///< Capability Registers Length
-  __I  uint8_t  TU_RESERVED[1];
-  __I  uint16_t HCIVERSION;      ///< Host Controller Interface Version
+  volatile uint8_t  CAPLENGTH;       ///< Capability Registers Length
+  volatile uint8_t  TU_RESERVED[1];
+  volatile uint16_t HCIVERSION;      ///< Host Controller Interface Version
 
-  __I  uint32_t HCSPARAMS;       ///< Host Controller Structural Parameters
-  __I  uint32_t HCCPARAMS;       ///< Host Controller Capability Parameters
-  __I  uint32_t TU_RESERVED[5];
+  volatile uint32_t HCSPARAMS;       ///< Host Controller Structural Parameters
+  volatile uint32_t HCCPARAMS;       ///< Host Controller Capability Parameters
+  volatile uint32_t TU_RESERVED[5];
 
-  __I  uint16_t DCIVERSION;      ///< Device Controller Interface Version
-  __I  uint8_t  TU_RESERVED[2];
+  volatile uint16_t DCIVERSION;      ///< Device Controller Interface Version
+  volatile uint8_t  TU_RESERVED[2];
 
-  __I  uint32_t DCCPARAMS;       ///< Device Controller Capability Parameters
-  __I  uint32_t TU_RESERVED[6];
+  volatile uint32_t DCCPARAMS;       ///< Device Controller Capability Parameters
+  volatile uint32_t TU_RESERVED[6];
 
   //------------- Operational Registers -------------//
-  __IO uint32_t USBCMD;          ///< USB Command Register
-  __IO uint32_t USBSTS;          ///< USB Status Register
-  __IO uint32_t USBINTR;         ///< Interrupt Enable Register
-  __IO uint32_t FRINDEX;         ///< USB Frame Index
-  __I  uint32_t TU_RESERVED;
-  __IO uint32_t DEVICEADDR;      ///< Device Address
-  __IO uint32_t ENDPTLISTADDR;   ///< Endpoint List Address
-  __I  uint32_t TU_RESERVED;
-  __IO uint32_t BURSTSIZE;       ///< Programmable Burst Size
-  __IO uint32_t TXFILLTUNING;    ///< TX FIFO Fill Tuning
-       uint32_t TU_RESERVED[4];
-  __IO uint32_t ENDPTNAK;        ///< Endpoint NAK
-  __IO uint32_t ENDPTNAKEN;      ///< Endpoint NAK Enable
-  __I  uint32_t TU_RESERVED;
-  __IO uint32_t PORTSC1;         ///< Port Status & Control
-  __I  uint32_t TU_RESERVED[7];
-  __IO uint32_t OTGSC;           ///< On-The-Go Status & control
-  __IO uint32_t USBMODE;         ///< USB Device Mode
-  __IO uint32_t ENDPTSETUPSTAT;  ///< Endpoint Setup Status
-  __IO uint32_t ENDPTPRIME;      ///< Endpoint Prime
-  __IO uint32_t ENDPTFLUSH;      ///< Endpoint Flush
-  __I  uint32_t ENDPTSTAT;       ///< Endpoint Status
-  __IO uint32_t ENDPTCOMPLETE;   ///< Endpoint Complete
-  __IO uint32_t ENDPTCTRL[8];    ///< Endpoint Control 0 - 7
-} dcd_registers_t, hcd_registers_t;
+  volatile uint32_t USBCMD;          ///< USB Command Register
+  volatile uint32_t USBSTS;          ///< USB Status Register
+  volatile uint32_t USBINTR;         ///< Interrupt Enable Register
+  volatile uint32_t FRINDEX;         ///< USB Frame Index
+  volatile uint32_t TU_RESERVED;
+  volatile uint32_t DEVICEADDR;      ///< Device Address
+  volatile uint32_t ENDPTLISTADDR;   ///< Endpoint List Address
+  volatile uint32_t TU_RESERVED;
+  volatile uint32_t BURSTSIZE;       ///< Programmable Burst Size
+  volatile uint32_t TXFILLTUNING;    ///< TX FIFO Fill Tuning
+           uint32_t TU_RESERVED[4];
+  volatile uint32_t ENDPTNAK;        ///< Endpoint NAK
+  volatile uint32_t ENDPTNAKEN;      ///< Endpoint NAK Enable
+  volatile uint32_t TU_RESERVED;
+  volatile uint32_t PORTSC1;         ///< Port Status & Control
+  volatile uint32_t TU_RESERVED[7];
+  volatile uint32_t OTGSC;           ///< On-The-Go Status & control
+  volatile uint32_t USBMODE;         ///< USB Device Mode
+  volatile uint32_t ENDPTSETUPSTAT;  ///< Endpoint Setup Status
+  volatile uint32_t ENDPTPRIME;      ///< Endpoint Prime
+  volatile uint32_t ENDPTFLUSH;      ///< Endpoint Flush
+  volatile uint32_t ENDPTSTAT;       ///< Endpoint Status
+  volatile uint32_t ENDPTCOMPLETE;   ///< Endpoint Complete
+  volatile uint32_t ENDPTCTRL[8];    ///< Endpoint Control 0 - 7
+} ci_hs_regs_t, hcd_registers_t;
+
+
+typedef struct
+{
+  ci_hs_regs_t* regs;
+  const uint32_t irqnum;
+  const uint8_t ep_count; // Max bi-directional Endpoints
+}dcd_controller_t;
 
 #ifdef __cplusplus
  }
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index e531cd842..1824aea86 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -25,25 +25,24 @@
  */
 
 #include "tusb_option.h"
+#include "device/dcd_attr.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
+#if TUSB_OPT_DEVICE_ENABLED && defined(DCD_ATTR_CONTROLLER_CHIPIDEA_HS)
 
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-  #include "fsl_device_registers.h"
-  #define INCLUDE_FSL_DEVICE_REGISTERS
-#else
-  // LPCOpen for 18xx & 43xx
-  #include "chip.h"
-#endif
-
-#include "common/tusb_common.h"
 #include "device/dcd.h"
 #include "ci_hs_type.h"
 
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  #include "ci_hs_imxrt.h"
+#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
+  #include "ci_hs_lpc18_43.h"
+#else
+  #error "Unsupported MCUs"
+#endif
+
 #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
   #define CleanInvalidateDCache_by_Addr   SCB_CleanInvalidateDCache_by_Addr
 #else
@@ -144,33 +143,6 @@ TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
 // Variables
 //--------------------------------------------------------------------+
 
-typedef struct
-{
-  dcd_registers_t* regs;  // registers
-  const IRQn_Type irqnum; // IRQ number
-  const uint8_t ep_count; // Max bi-directional Endpoints
-}dcd_controller_t;
-
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-  static const dcd_controller_t _dcd_controller[] =
-  {
-    // RT1010 and RT1020 only has 1 USB controller
-    #if FSL_FEATURE_SOC_USBHS_COUNT == 1
-      { .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
-    #else
-      { .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
-      { .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
-    #endif
-  };
-
-#else
-  static const dcd_controller_t _dcd_controller[] =
-  {
-    { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
-    { .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
-  };
-#endif
-
 #define QTD_NEXT_INVALID 0x01
 
 typedef struct {
@@ -191,7 +163,7 @@ static dcd_data_t _dcd_data;
 /// follows LPC43xx User Manual 23.10.3
 static void bus_reset(uint8_t rhport)
 {
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
 
   // The reset value for all endpoint types is the control endpoint. If one endpoint
   // direction is enabled and the paired endpoint of opposite direction is disabled, then the
@@ -231,7 +203,7 @@ void dcd_init(uint8_t rhport)
 {
   tu_memclr(&_dcd_data, sizeof(dcd_data_t));
 
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
 
   // Reset controller
   dcd_reg->USBCMD |= USBCMD_RESET;
@@ -255,40 +227,30 @@ void dcd_init(uint8_t rhport)
   dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
 }
 
-void dcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
-}
-
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
   // Response with status first before changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
   dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
 }
 
 void dcd_remote_wakeup(uint8_t rhport)
 {
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
   dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME;
 }
 
 void dcd_connect(uint8_t rhport)
 {
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
   dcd_reg->USBCMD |= USBCMD_RUN_STOP;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
   dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
 }
 
@@ -334,7 +296,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   uint8_t const epnum  = tu_edpt_number(ep_addr);
   uint8_t const dir    = tu_edpt_dir(ep_addr);
 
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
   dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
 
   // flush to abort any primed buffer
@@ -347,7 +309,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   // data toggle also need to be reset
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
   dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
   dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir  ? 16 : 0));
 }
@@ -376,7 +338,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
 
   // Enable EP Control
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
 
   uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
 
@@ -393,7 +355,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 
 void dcd_edpt_close_all (uint8_t rhport)
 {
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
 
   // Disable all non-control endpoints
   for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++)
@@ -411,7 +373,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   uint8_t const epnum  = tu_edpt_number(ep_addr);
   uint8_t const dir    = tu_edpt_dir(ep_addr);
 
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
 
   _dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1;
 
@@ -426,7 +388,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 
 static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
 {
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
   dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
   dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
 
@@ -542,7 +504,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
 
   if ( result != XFER_RESULT_SUCCESS )
   {
-    dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+    ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
     // flush to abort error buffer
     dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
   }
@@ -566,7 +528,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
 
 void dcd_int_handler(uint8_t rhport)
 {
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
 
   uint32_t const int_enable = dcd_reg->USBINTR;
   uint32_t const int_status = dcd_reg->USBSTS & int_enable;

From 83dc3e25f002a49f05919c3d8ebac37756641786 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Dec 2021 23:30:09 +0700
Subject: [PATCH 0698/2085] more work to abstract chipidea driver

---
 hw/bsp/ea4357/board.mk                       |  4 ++-
 hw/bsp/ngx4330/board.mk                      |  4 ++-
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h    | 12 +++----
 src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h | 10 +++---
 src/portable/chipidea/ci_hs/ci_hs_type.h     |  8 ++---
 src/portable/chipidea/ci_hs/dcd_ci_hs.c      | 37 +++++++++++---------
 6 files changed, 41 insertions(+), 34 deletions(-)

diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
index 4390d1eda..6f243c6a2 100644
--- a/hw/bsp/ea4357/board.mk
+++ b/hw/bsp/ea4357/board.mk
@@ -21,7 +21,9 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 LD_FILE = hw/bsp/$(BOARD)/lpc4357.ld
 
 SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
 	$(MCU_DIR)/src/clock_18xx_43xx.c \
diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk
index 3b193c0a5..3e901567c 100644
--- a/hw/bsp/ngx4330/board.mk
+++ b/hw/bsp/ngx4330/board.mk
@@ -21,7 +21,9 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
 LD_FILE = hw/bsp/$(BOARD)/ngx4330.ld
 
 SRC_C += \
-	src/portable/nxp/transdimension/dcd_transdimension.c \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
 	$(MCU_DIR)/src/chip_18xx_43xx.c \
 	$(MCU_DIR)/src/clock_18xx_43xx.c \
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index 3c92dccb6..52671509b 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -33,25 +33,25 @@
 
 #include "fsl_device_registers.h"
 
-static const dcd_controller_t _dcd_controller[] =
+static const ci_hs_controller_t _ci_controller[] =
 {
   // RT1010 and RT1020 only has 1 USB controller
   #if FSL_FEATURE_SOC_USBHS_COUNT == 1
-    { .regs = (ci_hs_regs_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
+    { .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
   #else
-    { .regs = (ci_hs_regs_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
-    { .regs = (ci_hs_regs_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
+    { .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
+    { .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
   #endif
 };
 
 void dcd_int_enable(uint8_t rhport)
 {
-  NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
+  NVIC_EnableIRQ(_ci_controller[rhport].irqnum);
 }
 
 void dcd_int_disable(uint8_t rhport)
 {
-  NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
+  NVIC_DisableIRQ(_ci_controller[rhport].irqnum);
 }
 
 #ifdef __cplusplus
diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
index c4f94820d..1d6accded 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
@@ -34,20 +34,20 @@
 // LPCOpen for 18xx & 43xx
 #include "chip.h"
 
-static const dcd_controller_t _dcd_controller[] =
+static const ci_hs_controller_t _ci_controller[] =
 {
-  { .regs = (ci_hs_regs_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
-  { .regs = (ci_hs_regs_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
+  { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
+  { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
 };
 
 void dcd_int_enable(uint8_t rhport)
 {
-  NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
+  NVIC_EnableIRQ(_ci_controller[rhport].irqnum);
 }
 
 void dcd_int_disable(uint8_t rhport)
 {
-  NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
+  NVIC_DisableIRQ(_ci_controller[rhport].irqnum);
 }
 
 #ifdef __cplusplus
diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h
index 772a7e413..810ec15ce 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_type.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_type.h
@@ -132,10 +132,10 @@ typedef struct
 
 typedef struct
 {
-  ci_hs_regs_t* regs;
-  const uint32_t irqnum;
-  const uint8_t ep_count; // Max bi-directional Endpoints
-}dcd_controller_t;
+  uint32_t reg_base;
+  uint32_t irqnum;
+  uint8_t  ep_count; // Max bi-directional Endpoints
+}ci_hs_controller_t;
 
 #ifdef __cplusplus
  }
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 1824aea86..6f28862b7 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -43,6 +43,9 @@
   #error "Unsupported MCUs"
 #endif
 
+
+#define CI_HS_REG(_port)      ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
+
 #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
   #define CleanInvalidateDCache_by_Addr   SCB_CleanInvalidateDCache_by_Addr
 #else
@@ -163,14 +166,14 @@ static dcd_data_t _dcd_data;
 /// follows LPC43xx User Manual 23.10.3
 static void bus_reset(uint8_t rhport)
 {
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
 
   // The reset value for all endpoint types is the control endpoint. If one endpoint
   // direction is enabled and the paired endpoint of opposite direction is disabled, then the
   // endpoint type of the unused direction must be changed from the control type to any other
   // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
   // for the data PID tracking on the active endpoint.
-  for( uint8_t i=1; i < _dcd_controller[rhport].ep_count; i++)
+  for( uint8_t i=1; i < _ci_controller[rhport].ep_count; i++)
   {
     dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
   }
@@ -203,7 +206,7 @@ void dcd_init(uint8_t rhport)
 {
   tu_memclr(&_dcd_data, sizeof(dcd_data_t));
 
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
 
   // Reset controller
   dcd_reg->USBCMD |= USBCMD_RESET;
@@ -232,25 +235,25 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   // Response with status first before changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
   dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
 }
 
 void dcd_remote_wakeup(uint8_t rhport)
 {
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
   dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME;
 }
 
 void dcd_connect(uint8_t rhport)
 {
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
   dcd_reg->USBCMD |= USBCMD_RUN_STOP;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
   dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
 }
 
@@ -296,7 +299,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   uint8_t const epnum  = tu_edpt_number(ep_addr);
   uint8_t const dir    = tu_edpt_dir(ep_addr);
 
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
   dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
 
   // flush to abort any primed buffer
@@ -309,7 +312,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   // data toggle also need to be reset
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
   dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
   dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir  ? 16 : 0));
 }
@@ -320,7 +323,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
 
   // Must not exceed max endpoint number
-  TU_ASSERT( epnum < _dcd_controller[rhport].ep_count );
+  TU_ASSERT( epnum < _ci_controller[rhport].ep_count );
 
   //------------- Prepare Queue Head -------------//
   dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
@@ -338,7 +341,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
 
   // Enable EP Control
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
 
   uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
 
@@ -355,10 +358,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 
 void dcd_edpt_close_all (uint8_t rhport)
 {
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
 
   // Disable all non-control endpoints
-  for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++)
+  for( uint8_t epnum=1; epnum < _ci_controller[rhport].ep_count; epnum++)
   {
     _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1;
     _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1;
@@ -373,7 +376,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   uint8_t const epnum  = tu_edpt_number(ep_addr);
   uint8_t const dir    = tu_edpt_dir(ep_addr);
 
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
 
   _dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1;
 
@@ -388,7 +391,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 
 static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
 {
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
   dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
   dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
 
@@ -504,7 +507,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
 
   if ( result != XFER_RESULT_SUCCESS )
   {
-    ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+    ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
     // flush to abort error buffer
     dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
   }
@@ -528,7 +531,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
 
 void dcd_int_handler(uint8_t rhport)
 {
-  ci_hs_regs_t* dcd_reg = _dcd_controller[rhport].regs;
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
 
   uint32_t const int_enable = dcd_reg->USBINTR;
   uint32_t const int_status = dcd_reg->USBSTS & int_enable;

From 207c60d055dd810525db11666b029f322cbaf9e8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 Dec 2021 00:03:44 +0700
Subject: [PATCH 0699/2085] more chipidea

---
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h    | 19 ++------
 src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h | 20 ++------
 src/portable/chipidea/ci_hs/ci_hs_type.h     |  2 +-
 src/portable/chipidea/ci_hs/dcd_ci_hs.c      | 16 +++++--
 src/portable/chipidea/ci_hs/hcd_ci_hs.c      | 50 +++++---------------
 5 files changed, 35 insertions(+), 72 deletions(-)

diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index 52671509b..78ca5a5a2 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -27,10 +27,6 @@
 #ifndef _CI_HS_IMXRT_H_
 #define _CI_HS_IMXRT_H_
 
-#ifdef __cplusplus
- extern "C" {
-#endif
-
 #include "fsl_device_registers.h"
 
 static const ci_hs_controller_t _ci_controller[] =
@@ -44,18 +40,11 @@ static const ci_hs_controller_t _ci_controller[] =
   #endif
 };
 
-void dcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(_ci_controller[rhport].irqnum);
-}
+#define CI_DCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
+#define CI_DCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
 
-void dcd_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(_ci_controller[rhport].irqnum);
-}
+#define CI_HCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
+#define CI_HCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
 
-#ifdef __cplusplus
- }
-#endif
 
 #endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
index 1d6accded..8c2e7dfa6 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
@@ -27,10 +27,6 @@
 #ifndef _CI_HS_LPC18_43_H_
 #define _CI_HS_LPC18_43_H_
 
-#ifdef __cplusplus
- extern "C" {
-#endif
-
 // LPCOpen for 18xx & 43xx
 #include "chip.h"
 
@@ -40,18 +36,10 @@ static const ci_hs_controller_t _ci_controller[] =
   { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
 };
 
-void dcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(_ci_controller[rhport].irqnum);
-}
+#define CI_DCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
+#define CI_DCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
 
-void dcd_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(_ci_controller[rhport].irqnum);
-}
-
-#ifdef __cplusplus
- }
-#endif
+#define CI_HCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
+#define CI_HCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
 
 #endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h
index 810ec15ce..728a86b86 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_type.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_type.h
@@ -127,7 +127,7 @@ typedef struct
   volatile uint32_t ENDPTSTAT;       ///< Endpoint Status
   volatile uint32_t ENDPTCOMPLETE;   ///< Endpoint Complete
   volatile uint32_t ENDPTCTRL[8];    ///< Endpoint Control 0 - 7
-} ci_hs_regs_t, hcd_registers_t;
+} ci_hs_regs_t;
 
 
 typedef struct
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 6f28862b7..c943396fc 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -43,6 +43,9 @@
   #error "Unsupported MCUs"
 #endif
 
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
 
 #define CI_HS_REG(_port)      ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
 
@@ -52,9 +55,6 @@
   #define CleanInvalidateDCache_by_Addr(_addr, _dsize)
 #endif
 
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
 
 // ENDPTCTRL
 enum {
@@ -230,6 +230,16 @@ void dcd_init(uint8_t rhport)
   dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
 }
 
+void dcd_int_enable(uint8_t rhport)
+{
+  CI_DCD_INT_ENABLE(rhport);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  CI_DCD_INT_DISABLE(rhport);
+}
+
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
   // Response with status first before changing device address
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index a62ebf2a3..3d028bf32 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -34,47 +34,23 @@
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-  #include "fsl_device_registers.h"
-#else
-  // LPCOpen for 18xx & 43xx
-  #include "chip.h"
-#endif
-
 #include "common/tusb_common.h"
-#include "ci_hs_type.h"
 #include "portable/ehci/ehci_api.h"
+#include "ci_hs_type.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  #include "ci_hs_imxrt.h"
+#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
+  #include "ci_hs_lpc18_43.h"
+#else
+  #error "Unsupported MCUs"
+#endif
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-// TODO can be merged with dcd_controller_t
-typedef struct
-{
-  uint32_t regs_base;     // registers base
-  const IRQn_Type irqnum; // IRQ number
-}hcd_controller_t;
-
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-  static const hcd_controller_t _hcd_controller[] =
-  {
-    // RT1010 and RT1020 only has 1 USB controller
-    #if FSL_FEATURE_SOC_USBHS_COUNT == 1
-      { .regs_base = USB_BASE , .irqnum = USB_OTG1_IRQn }
-    #else
-      { .regs_base = USB1_BASE, .irqnum = USB_OTG1_IRQn },
-      { .regs_base = USB2_BASE, .irqnum = USB_OTG2_IRQn }
-    #endif
-  };
-
-#else
-  static const hcd_controller_t _hcd_controller[] =
-  {
-    { .regs_base = LPC_USB0_BASE, .irqnum = USB0_IRQn },
-    { .regs_base = LPC_USB1_BASE, .irqnum = USB1_IRQn }
-  };
-#endif
+#define CI_HS_REG(_port)      ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
 
 //--------------------------------------------------------------------+
 // Controller API
@@ -82,7 +58,7 @@ typedef struct
 
 bool hcd_init(uint8_t rhport)
 {
-  hcd_registers_t* hcd_reg = (hcd_registers_t*) _hcd_controller[rhport].regs_base;
+  ci_hs_regs_t* hcd_reg = CI_HS_REG(rhport);
 
   // Reset controller
   hcd_reg->USBCMD |= USBCMD_RESET;
@@ -106,12 +82,12 @@ bool hcd_init(uint8_t rhport)
 
 void hcd_int_enable(uint8_t rhport)
 {
-  NVIC_EnableIRQ(_hcd_controller[rhport].irqnum);
+  CI_HCD_INT_ENABLE(rhport);
 }
 
 void hcd_int_disable(uint8_t rhport)
 {
-  NVIC_DisableIRQ(_hcd_controller[rhport].irqnum);
+  CI_HCD_INT_DISABLE(rhport);
 }
 
 #endif

From eae4132fbb216329e9a0d8b624baf1c5aad56359 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 Dec 2021 11:31:27 +0700
Subject: [PATCH 0700/2085] update supported doc

---
 docs/reference/supported.rst | 212 +++++++++++++++++------------------
 1 file changed, 101 insertions(+), 111 deletions(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index dfaffe6e3..83cf874da 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -2,124 +2,114 @@
 Supported Devices
 *****************
 
-
 Supported MCUs
 ==============
 
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| Manufacturer | Family                | Device               | Host                 | Highspeed            | Driver          | Note         |
-+==============+=======================+======================+======================+======================+=================+==============+
-| Broadcom     | BCM2711, BCM2837      | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | dwc2            |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| Dialog       | DA1469x               | |:heavy_check_mark:| | |:x:|                | |:x:|                | da146xx         |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| Espressif    | ESP32 S2, S3          | |:heavy_check_mark:| |                      | |:x:|                | dwc2 or esp32sx |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| GigaDevice   | GD32VF103             | |:heavy_check_mark:| |                      | |:x:|                | dwc2            |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| Infineon     | XMC4500               | |:heavy_check_mark:| |                      | |:x:|                | dwc2            |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| MicroChip    | SAM D11, D21          | |:heavy_check_mark:| |                      | |:x:|                | samd            |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | SAM D51, E5x          | |:heavy_check_mark:| |                      | |:x:|                | samd            |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | SAM G55               | |:heavy_check_mark:| |                      | |:x:|                | samg            |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | SAM L21, L22          | |:heavy_check_mark:| |                      | |:x:|                | samd            |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | SAM E70,S70,V70,V71   | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | samx7x          |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| NordicSemi   | nRF52833, nRF52840    | |:heavy_check_mark:| | |:x:|                | |:x:|                | nrf5x           |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | nRF5340               | |:heavy_check_mark:| | |:x:|                | |:x:|                | nrf5x           |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| Nuvoton      | NUC120                | |:heavy_check_mark:| | |:x:|                | |:x:|                |                 |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | NUC121/NUC125         | |:heavy_check_mark:| | |:x:|                | |:x:|                |                 |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | NUC126                | |:heavy_check_mark:| | |:x:|                | |:x:|                |                 |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | NUC505                | |:heavy_check_mark:| |                      | |:heavy_check_mark:| |                 |              |
-+--------------+---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| NXP          | iMXRT   | RT1011      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | RT1015      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | RT1021      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | RT1052      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | RT1062      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | RT1064      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:heavy_check_mark:| |                 |              |
-|              +---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | Kinetis | KL25        | |:heavy_check_mark:| |                      | |:x:|                |                 |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | K32L2       | |:heavy_check_mark:| |                      | |:x:|                |                 |              |
-|              +---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | LPC     | 11u, 13, 15 | |:heavy_check_mark:| | |:x:|                | |:x:|                | lpc_ip3511      |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | 17, 40      | |:heavy_check_mark:| | |:construction:|     | |:x:|                | lpc17_40        |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | 18, 43      | |:heavy_check_mark:| | |:heavy_check_mark:| | |:x:|                |                 |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | 51u         | |:heavy_check_mark:| | |:x:|                | |:x:|                | lpc_ip3511      |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | 54          | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | lpc_ip3511      |              |
-|              |         +-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |         | 55          | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | lpc_ip3511      |              |
-+--------------+---------+-------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| Raspberry Pi | RP2040                | |:heavy_check_mark:| | |:heavy_check_mark:| | |:x:|                | rp2040          |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| Renesas      | RX 63N, 65N, 72N      | |:heavy_check_mark:| | |:x:|                | |:x:|                | usba            |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| Silabs       | EFM32GG12             | |:heavy_check_mark:| |                      | |:x:|                | dwc2            |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| Sony         | CXD56                 | |:heavy_check_mark:| | |:x:|                | |:heavy_check_mark:| | cxd56           |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| ST STM32     | F0                    | |:heavy_check_mark:| | |:x:|                | |:x:|                | stm32_fsdev     |              |
-|              +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | F1 | 102, 103         | |:heavy_check_mark:| | |:x:|                | |:x:|                | stm32_fsdev     |              |
-|              |    +------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |    | 105, 107         | |:heavy_check_mark:| |                      | |:x:|                | dwc2            |              |
-|              +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | F2                    | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | dwc2            |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | F3                    | |:heavy_check_mark:| | |:x:|                | |:x:|                | stm32_fsdev     |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | F4                    | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | dwc2            |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | F7                    | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | dwc2            |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | H7                    | |:heavy_check_mark:| |                      | |:heavy_check_mark:| | dwc2            |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | L0, L1                | |:heavy_check_mark:| | |:x:|                | |:x:|                | stm32_fsdev     |              |
-|              +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | L4 | 4x2, 4x3         | |:heavy_check_mark:| | |:x:|                | |:x:|                | stm32_fsdev     |              |
-|              |    +------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              |    | 4x5, 4x6         | |:heavy_check_mark:| |                      |                      | dwc2            |              |
-|              +----+------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | L4+                   | |:heavy_check_mark:| |                      |                      | dwc2            |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | U5                    | |:construction:|     |                      |                      | dwc2            |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| TI           | MSP430                | |:heavy_check_mark:| | |:x:|                | |:x:|                | msp430x5xx      |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | MSP432E4              | |:heavy_check_mark:| |                      | |:x:|                | musb            |              |
-|              +-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-|              | TM4C123               | |:heavy_check_mark:| |                      | |:x:|                | musb            |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
-| ValentyUSB   | eptri                 | |:heavy_check_mark:| | |:x:|                | |:x:|                | eptri           |              |
-+--------------+-----------------------+----------------------+----------------------+----------------------+-----------------+--------------+
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| Manufacturer | Family                | Device | Host | Highspeed | Driver            | Note         |
++==============+=======================+========+======+===========+===================+==============+
+| Broadcom     | BCM2711, BCM2837      | ✔      |      | ✔         | dwc2              |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| Dialog       | DA1469x               | ✔      | ✖    | ✖         | da146xx           |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| Espressif    | ESP32 S2, S3          | ✔      |      | ✖         | dwc2 or esp32sx   |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| GigaDevice   | GD32VF103             | ✔      |      | ✖         | dwc2              |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| Infineon     | XMC4500               | ✔      |      | ✖         | dwc2              |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| MicroChip    | SAM D11, D21          | ✔      |      | ✖         | samd              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | SAM D51, E5x          | ✔      |      | ✖         | samd              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | SAM G55               | ✔      |      | ✖         | samg              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | SAM L21, L22          | ✔      |      | ✖         | samd              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | SAM E70,S70,V70,V71   | ✔      |      | ✔         | samx7x            |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| NordicSemi   | nRF52833, nRF52840    | ✔      | ✖    | ✖         | nrf5x             |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | nRF5340               | ✔      | ✖    | ✖         | nrf5x             |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| Nuvoton      | NUC120                | ✔      | ✖    | ✖         |                   |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | NUC121/NUC125         | ✔      | ✖    | ✖         |                   |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | NUC126                | ✔      | ✖    | ✖         |                   |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | NUC505                | ✔      |      | ✔         |                   |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| NXP          | iMXRT   | RT10xx      | ✔      | ✔    | ✔         | ci_hs             |              |
+|              +---------+-------------+--------+------+-----------+-------------------+--------------+
+|              | Kinetis | KL25        | ✔      |      | ✖         |                   |              |
+|              |         +-------------+--------+------+-----------+-------------------+--------------+
+|              |         | K32L2       | ✔      |      | ✖         |                   |              |
+|              +---------+-------------+--------+------+-----------+-------------------+--------------+
+|              | LPC     | 11u, 13, 15 | ✔      | ✖    | ✖         | lpc_ip3511        |              |
+|              |         +-------------+--------+------+-----------+-------------------+--------------+
+|              |         | 17, 40      | ✔      | ⚠    | ✖         | lpc17_40          |              |
+|              |         +-------------+--------+------+-----------+-------------------+--------------+
+|              |         | 18, 43      | ✔      | ✔    | ✔         | ci_hs             |              |
+|              |         +-------------+--------+------+-----------+-------------------+--------------+
+|              |         | 51u         | ✔      | ✖    | ✖         | lpc_ip3511        |              |
+|              |         +-------------+--------+------+-----------+-------------------+--------------+
+|              |         | 54          | ✔      |      | ✔         | lpc_ip3511        |              |
+|              |         +-------------+--------+------+-----------+-------------------+--------------+
+|              |         | 55          | ✔      |      | ✔         | lpc_ip3511        |              |
++--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
+| Raspberry Pi | RP2040                | ✔      | ✔    | ✖         | rp2040            |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| Renesas      | RX 63N, 65N, 72N      | ✔      | ✖    | ✖         | usba              |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| Silabs       | EFM32GG12             | ✔      |      | ✖         | dwc2              |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| Sony         | CXD56                 | ✔      | ✖    | ✔         | cxd56             |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| ST STM32     | F0                    | ✔      | ✖    | ✖         | stm32_fsdev       |              |
+|              +----+------------------+--------+------+-----------+-------------------+--------------+
+|              | F1 | 102, 103         | ✔      | ✖    | ✖         | stm32_fsdev       |              |
+|              |    +------------------+--------+------+-----------+-------------------+--------------+
+|              |    | 105, 107         | ✔      |      | ✖         | dwc2              |              |
+|              +----+------------------+--------+------+-----------+-------------------+--------------+
+|              | F2                    | ✔      |      | ✔         | dwc2              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | F3                    | ✔      | ✖    | ✖         | stm32_fsdev       |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | F4                    | ✔      |      | ✔         | dwc2              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | F7                    | ✔      |      | ✔         | dwc2              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | H7                    | ✔      |      | ✔         | dwc2              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | L0, L1                | ✔      | ✖    | ✖         | stm32_fsdev       |              |
+|              +----+------------------+--------+------+-----------+-------------------+--------------+
+|              | L4 | 4x2, 4x3         | ✔      | ✖    | ✖         | stm32_fsdev       |              |
+|              |    +------------------+--------+------+-----------+-------------------+--------------+
+|              |    | 4x5, 4x6         | ✔      |      |           | dwc2              |              |
+|              +----+------------------+--------+------+-----------+-------------------+--------------+
+|              | L4+                   | ✔      |      |           | dwc2              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | U5                    | âš       |      |           | dwc2              |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| TI           | MSP430                | ✔      | ✖    | ✖         | msp430x5xx        |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | MSP432E4              | ✔      |      | ✖         | musb              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | TM4C123               | ✔      |      | ✖         | musb              |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| ValentyUSB   | eptri                 | ✔      | ✖    | ✖         | eptri             |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+
 
 Table Legend
 ------------
 
-==================== ===================
-|:heavy_check_mark:| Supported
-|:construction:|     WIP/partial support
-|:x:|                Not supported
-==================== ===================
+= ===================
+✔ Supported
+âš  WIP/partial support
+✖ Not supported
+= ===================
 
 Supported Boards
 ================

From 369f11fe5c21ca19538e9165100115d34fdc72f4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 Dec 2021 11:50:28 +0700
Subject: [PATCH 0701/2085] fix ci

---
 examples/host/hid_controller/Makefile | 2 --
 1 file changed, 2 deletions(-)

diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index 2595ec4a7..a4eaf0816 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -23,9 +23,7 @@ SRC_C += \
 	src/host/hub.c \
 	src/host/usbh.c \
 	src/host/usbh_control.c \
-	src/portable/ehci/ehci.c \
 	src/portable/ohci/ohci.c \
-	src/portable/nxp/transdimension/hcd_transdimension.c \
 	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
 
 include ../../rules.mk

From 1d1e75236c4bed4346e6ed840869de2c3acf7220 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 Dec 2021 12:02:25 +0700
Subject: [PATCH 0702/2085] temporarily skip s3 build on ci

---
 .github/workflows/build_esp.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 15071b178..57dbf33e3 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -18,7 +18,8 @@ jobs:
         # ESP32-S2
         - 'espressif_saola_1'
         # ESP32-S3
-        - 'espressif_addax_1'
+        #- 'espressif_addax_1'
+        # S3 compile error with "dangerous relocation: call8: call target out of range: memcpy"
 
     steps:
     - name: Setup Python

From 94c35de0d2632574b8833a3310082a7e25aa6dd2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 Dec 2021 13:19:27 +0700
Subject: [PATCH 0703/2085] minor doc update

---
 docs/reference/supported.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 83cf874da..e3cb8c679 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -39,7 +39,7 @@ Supported MCUs
 |              | NUC126                | ✔      | ✖    | ✖         |                   |              |
 |              +-----------------------+--------+------+-----------+-------------------+--------------+
 |              | NUC505                | ✔      |      | ✔         |                   |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
++--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
 | NXP          | iMXRT   | RT10xx      | ✔      | ✔    | ✔         | ci_hs             |              |
 |              +---------+-------------+--------+------+-----------+-------------------+--------------+
 |              | Kinetis | KL25        | ✔      |      | ✖         |                   |              |

From c52c9cda913a828da4d6b2da4df8a0ef1751c425 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Thu, 2 Dec 2021 10:22:24 +0000
Subject: [PATCH 0704/2085] after commit: eae4132 this dependency is no longer
 required

Signed-off-by: Rafael Silva <perigoso@riseup.net>
---
 docs/conf.py          | 1 -
 docs/requirements.txt | 1 -
 2 files changed, 2 deletions(-)

diff --git a/docs/conf.py b/docs/conf.py
index c7a17478f..878b29645 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -21,7 +21,6 @@ extensions = [
     'sphinx.ext.intersphinx',
     'sphinx.ext.todo',
     'sphinx_autodoc_typehints',
-    'sphinxemoji.sphinxemoji',
 ]
 
 templates_path = ['_templates']
diff --git a/docs/requirements.txt b/docs/requirements.txt
index e415ae03e..8ae9ae73b 100644
--- a/docs/requirements.txt
+++ b/docs/requirements.txt
@@ -1,4 +1,3 @@
 sphinx~=3.0
 furo>=2020.12.30.b24
-sphinxemoji>=0.1.8
 sphinx-autodoc-typehints>=1.10

From 81285273a6b5cacace52e74890ff9863a6a92d1a Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 4 Dec 2021 01:18:42 +0900
Subject: [PATCH 0705/2085] Fix memory overrun at pipe_read_packet()

---
 src/portable/mentor/musb/hcd_musb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index dc614d074..acccb7674 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -269,12 +269,12 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
     len  -= 4;
   }
   if (len >= 2) {
-    *(uint32_t *)addr = reg->u16;
+    *(uint16_t *)addr = reg->u16;
     addr += 2;
     len  -= 2;
   }
   if (len) {
-    *(uint32_t *)addr = reg->u8;
+    *(uint8_t *)addr = reg->u8;
   }
 }
 

From 7137a0a92f5623e06d7457aba0eaa65f077010a2 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 4 Dec 2021 01:25:34 +0900
Subject: [PATCH 0706/2085] Fix buffer overrun at pipe_read_packet()

---
 src/portable/mentor/musb/dcd_musb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 4b4c2f9b2..512beff97 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -250,12 +250,12 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
     len  -= 4;
   }
   if (len >= 2) {
-    *(uint32_t *)addr = reg->u16;
+    *(uint16_t *)addr = reg->u16;
     addr += 2;
     len  -= 2;
   }
   if (len) {
-    *(uint32_t *)addr = reg->u8;
+    *(uint8_t *)addr = reg->u8;
   }
 }
 

From dff54d854ddae3ff5c8dc81bac77fd8b50564598 Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Sat, 4 Dec 2021 17:18:39 +0800
Subject: [PATCH 0707/2085] Modify sunxi_musb code

---
 src/portable/sunxi/dcd_sunxi_musb.c | 40 +++++++++++++++++++----------
 1 file changed, 26 insertions(+), 14 deletions(-)

diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index bb39d3890..b13842de1 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -1,8 +1,7 @@
 #include <stdint.h>
-#include <F1C100s.h>
+#include "tusb_option.h"
+#include "osal/osal.h"
 #include <f1c100s-irq.h>
-
-#include <tusb_option.h>
 #include <device/dcd.h>
 #include "musb_def.h"
 
@@ -10,9 +9,7 @@ typedef uint32_t u32;
 typedef uint16_t u16;
 typedef uint8_t u8;
 
-#if !TU_CHECK_MCU(OPT_MCU_F1C100S)
-    #error "Only f1c100s is supported"
-#endif
+#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_F1C100S
 
 #define REQUEST_TYPE_INVALID  (0xFFu)
 
@@ -69,12 +66,22 @@ static void usb_phy_write(int addr, int data, int len)
 	}
 }
 
+static void delay_ms(uint32_t ms)
+{
+#if CFG_TUSB_OS == OPT_OS_NONE
+  int cnt = ms * 1000 * 1000 / 2;
+  while (cnt--) asm("nop");
+#else
+  osal_task_delay(ms);
+#endif
+}
+
 static void USBC_HardwareReset(void)
 {
   // Reset phy and controller
   USBC_REG_set_bit_l(USBPHY_CLK_RST_BIT, USBPHY_CLK_REG);
 	USBC_REG_set_bit_l(BUS_RST_USB_BIT, BUS_CLK_RST_REG);
-  osal_task_delay(2);
+  delay_ms(2);
 
 	USBC_REG_set_bit_l(USBPHY_CLK_GAT_BIT, USBPHY_CLK_REG);
   USBC_REG_set_bit_l(USBPHY_CLK_RST_BIT, USBPHY_CLK_REG);
@@ -83,7 +90,7 @@ static void USBC_HardwareReset(void)
 	USBC_REG_set_bit_l(BUS_RST_USB_BIT, BUS_CLK_RST_REG);
 }
 
-static void USBC_PhyConfig()
+static void USBC_PhyConfig(void)
 {
 	/* Regulation 45 ohms */
 	usb_phy_write(0x0c, 0x01, 1);
@@ -97,7 +104,7 @@ static void USBC_PhyConfig()
 	return;
 }
 
-static void USBC_ConfigFIFO_Base()
+static void USBC_ConfigFIFO_Base(void)
 {
 	u32 reg_value;
 
@@ -507,7 +514,7 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
 
 static void process_setup_packet(uint8_t rhport)
 {
-  uint32_t *p = (void*)&_dcd.setup_packet;
+  uint32_t *p = (uint32_t*)&_dcd.setup_packet;
   p[0]        = USBC_Readl(USBC_REG_EPFIFO0(USBC0_BASE));
   p[1]        = USBC_Readl(USBC_REG_EPFIFO0(USBC0_BASE));
 
@@ -808,7 +815,7 @@ static void process_bus_reset(uint8_t rhport)
  * Device API
  *------------------------------------------------------------------*/
 
-static void usb_isr_handler() {
+static void usb_isr_handler(void) {
 	dcd_int_handler(0);
 }
 
@@ -861,7 +868,7 @@ void dcd_int_enable(uint8_t rhport)
   f1c100s_intc_enable_irq(F1C100S_IRQ_USBOTG);
 }
 
-static void musb_int_mask()
+static void musb_int_mask(void)
 {
   f1c100s_intc_mask_irq(F1C100S_IRQ_USBOTG);
 }
@@ -872,7 +879,7 @@ void dcd_int_disable(uint8_t rhport)
   f1c100s_intc_disable_irq(F1C100S_IRQ_USBOTG);
 }
 
-static void musb_int_unmask()
+static void musb_int_unmask(void)
 {
   f1c100s_intc_unmask_irq(F1C100S_IRQ_USBOTG);
 }
@@ -895,7 +902,7 @@ void dcd_remote_wakeup(uint8_t rhport)
 {
   (void)rhport;
   USBC_REG_set_bit_b(USBC_BP_POWER_D_RESUME, USBC_REG_PCTL(USBC0_BASE));
-  osal_task_delay(10);
+  delay_ms(10);
   USBC_REG_clear_bit_b(USBC_BP_POWER_D_RESUME, USBC_REG_PCTL(USBC0_BASE));
 }
 
@@ -903,6 +910,10 @@ void dcd_remote_wakeup(uint8_t rhport)
 // Endpoint API
 //--------------------------------------------------------------------+
 
+#ifndef __ARMCC_VERSION
+#define __clz __builtin_clz
+#endif
+
 // Configure endpoint's registers according to descriptor
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 {
@@ -1150,3 +1161,4 @@ void dcd_int_handler(uint8_t rhport)
   }
 }
 
+#endif

From 68ca62dfd7e7fe757ba436fee7721520119da92b Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Sat, 4 Dec 2021 18:02:07 +0800
Subject: [PATCH 0708/2085] Add BSP support for F1C100s

---
 examples/rules.mk                             |   5 +
 hw/bsp/f1c100s/README.md                      |  17 +
 hw/bsp/f1c100s/board.h                        |   1 +
 hw/bsp/f1c100s/board.mk                       |  45 +
 hw/bsp/f1c100s/f1c100s.c                      | 130 +++
 hw/mcu/allwinner/f1c100s/f1c100s.ld           | 137 +++
 hw/mcu/allwinner/f1c100s/include/arm32.h      | 150 ++++
 .../allwinner/f1c100s/include/f1c100s-gpio.h  |  66 ++
 .../allwinner/f1c100s/include/f1c100s-irq.h   | 104 +++
 .../allwinner/f1c100s/include/f1c100s-reset.h |  39 +
 .../allwinner/f1c100s/include/f1c100s-util.h  | 139 +++
 .../f1c100s/include/f1c100s/reg-ccu.h         |  55 ++
 .../f1c100s/include/f1c100s/reg-dram.h        |  39 +
 hw/mcu/allwinner/f1c100s/include/io.h         |  57 ++
 hw/mcu/allwinner/f1c100s/include/irqflags.h   | 104 +++
 hw/mcu/allwinner/f1c100s/include/malloc.h     |  35 +
 hw/mcu/allwinner/f1c100s/include/printf.h     |  99 +++
 hw/mcu/allwinner/f1c100s/include/sizes.h      |  42 +
 hw/mcu/allwinner/f1c100s/include/types.h      |  55 ++
 hw/mcu/allwinner/f1c100s/lib/malloc.c         | 834 ++++++++++++++++++
 hw/mcu/allwinner/f1c100s/lib/memcpy.S         | 404 +++++++++
 hw/mcu/allwinner/f1c100s/lib/memset.S         |  79 ++
 hw/mcu/allwinner/f1c100s/lib/printf.c         | 757 ++++++++++++++++
 hw/mcu/allwinner/f1c100s/machine/exception.c  |  76 ++
 .../allwinner/f1c100s/machine/f1c100s-intc.c  | 173 ++++
 hw/mcu/allwinner/f1c100s/machine/start.S      | 313 +++++++
 hw/mcu/allwinner/f1c100s/machine/sys-clock.c  | 124 +++
 .../allwinner/f1c100s/machine/sys-copyself.c  | 111 +++
 hw/mcu/allwinner/f1c100s/machine/sys-dram.c   | 506 +++++++++++
 hw/mcu/allwinner/f1c100s/machine/sys-mmu.c    |  57 ++
 .../allwinner/f1c100s/machine/sys-spi-flash.c | 204 +++++
 hw/mcu/allwinner/f1c100s/machine/sys-uart.c   |  83 ++
 src/portable/sunxi/dcd_sunxi_musb.c           |   5 +-
 33 files changed, 5043 insertions(+), 2 deletions(-)
 create mode 100644 hw/bsp/f1c100s/README.md
 create mode 100644 hw/bsp/f1c100s/board.h
 create mode 100644 hw/bsp/f1c100s/board.mk
 create mode 100644 hw/bsp/f1c100s/f1c100s.c
 create mode 100644 hw/mcu/allwinner/f1c100s/f1c100s.ld
 create mode 100644 hw/mcu/allwinner/f1c100s/include/arm32.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s-gpio.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s-irq.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s-reset.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s-util.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s/reg-ccu.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s/reg-dram.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/io.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/irqflags.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/malloc.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/printf.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/sizes.h
 create mode 100644 hw/mcu/allwinner/f1c100s/include/types.h
 create mode 100644 hw/mcu/allwinner/f1c100s/lib/malloc.c
 create mode 100644 hw/mcu/allwinner/f1c100s/lib/memcpy.S
 create mode 100644 hw/mcu/allwinner/f1c100s/lib/memset.S
 create mode 100644 hw/mcu/allwinner/f1c100s/lib/printf.c
 create mode 100644 hw/mcu/allwinner/f1c100s/machine/exception.c
 create mode 100644 hw/mcu/allwinner/f1c100s/machine/f1c100s-intc.c
 create mode 100644 hw/mcu/allwinner/f1c100s/machine/start.S
 create mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-clock.c
 create mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-copyself.c
 create mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-dram.c
 create mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-mmu.c
 create mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-spi-flash.c
 create mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-uart.c

diff --git a/examples/rules.mk b/examples/rules.mk
index 4cc35cb22..6314380ec 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -182,6 +182,11 @@ flash-jlink: $(BUILD)/$(PROJECT).hex
 flash-stlink: $(BUILD)/$(PROJECT).elf
 	STM32_Programmer_CLI --connect port=swd --write $< --go
 
+flash-xfel: $(BUILD)/$(PROJECT).bin
+	xfel ddr 
+	xfel write 0x80000000 $<
+	xfel exec 0x80000000
+
 # Flash using pyocd
 PYOCD_OPTION ?=
 flash-pyocd: $(BUILD)/$(PROJECT).hex
diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md
new file mode 100644
index 000000000..a4865b925
--- /dev/null
+++ b/hw/bsp/f1c100s/README.md
@@ -0,0 +1,17 @@
+# BSP support for F1Cx00s boards
+
+This folder contains necessary file and scripts to run TinyUSB examples on F1Cx00s boards.
+
+Currently tested on:
+
+* Lichee Pi Nano (F1C100s)
+
+## make flash
+`make flash` will use [xfel](https://github.com/xboot/xfel) to write the code to onchip DDR memory and execute it. It will not write the program to SPI Flash.
+
+To enter FEL mode, you have to press BOOT button, then press RESET once, and release BOOT button. You will find VID/PID=1f3a:efe8 on your PC.
+
+## TODO
+* Test on Tiny200 v2 (F1C200s)
+* Make it able to load .bin directly to SPI Flash and boot
+* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX` high speed MCU check in examples (maybe we should extract the logic?)
\ No newline at end of file
diff --git a/hw/bsp/f1c100s/board.h b/hw/bsp/f1c100s/board.h
new file mode 100644
index 000000000..238ac796d
--- /dev/null
+++ b/hw/bsp/f1c100s/board.h
@@ -0,0 +1 @@
+// Nothing valuable here
\ No newline at end of file
diff --git a/hw/bsp/f1c100s/board.mk b/hw/bsp/f1c100s/board.mk
new file mode 100644
index 000000000..993aa0d24
--- /dev/null
+++ b/hw/bsp/f1c100s/board.mk
@@ -0,0 +1,45 @@
+DEFINES += -D__ARM32_ARCH__=5 -D__ARM926EJS__
+
+CFLAGS += \
+  -ffreestanding \
+  -std=gnu99 \
+  -march=armv5te \
+  -mtune=arm926ej-s \
+  -mfloat-abi=soft \
+  -marm \
+  -mno-thumb-interwork \
+  -Wno-unused-parameter \
+  -Wno-float-equal \
+  -DCFG_TUSB_MCU=OPT_MCU_F1C100S \
+  -Wno-error=cast-align \
+  -Wno-error=address-of-packed-member \
+  $(DEFINES)
+
+LD_FILE = hw/mcu/allwinner/f1c100s/f1c100s.ld
+LDFLAGS += -nostdlib -lgcc
+MCU_DIR = hw/mcu/allwinner/f1c100s
+
+SRC_C += \
+	src/portable/sunxi/dcd_sunxi_musb.c \
+	$(MCU_DIR)/machine/sys-uart.c \
+	$(MCU_DIR)/machine/exception.c \
+	$(MCU_DIR)/machine/sys-clock.c \
+	$(MCU_DIR)/machine/sys-copyself.c \
+	$(MCU_DIR)/machine/sys-dram.c \
+	$(MCU_DIR)/machine/sys-mmu.c \
+	$(MCU_DIR)/machine/sys-spi-flash.c \
+	$(MCU_DIR)/machine/f1c100s-intc.c \
+	$(MCU_DIR)/lib/malloc.c \
+	$(MCU_DIR)/lib/printf.c 
+
+SRC_S += \
+    $(MCU_DIR)/machine/start.S \
+	$(MCU_DIR)/lib/memcpy.S \
+	$(MCU_DIR)/lib/memset.S
+
+INC += \
+	$(TOP)/$(MCU_DIR)/include \
+	$(TOP)/$(BOARD_PATH)
+
+# flash target using on-board stlink
+flash: flash-xfel
diff --git a/hw/bsp/f1c100s/f1c100s.c b/hw/bsp/f1c100s/f1c100s.c
new file mode 100644
index 000000000..6cf18597c
--- /dev/null
+++ b/hw/bsp/f1c100s/f1c100s.c
@@ -0,0 +1,130 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdint.h>
+#include <malloc.h>
+#include <irqflags.h>
+#include <f1c100s-irq.h>
+#include "bsp/board.h"
+#include "board.h"
+
+extern void sys_uart_putc(char c);
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+static void timer_init(void);
+
+void board_init(void)
+{
+  arch_local_irq_disable();
+	do_init_mem_pool();
+  f1c100s_intc_init();
+  timer_init();
+  printf("Timer INIT done\n");
+  arch_local_irq_enable();
+}
+
+// No LED, no button, sorry
+void board_led_write(bool state)
+{
+
+}
+
+uint32_t board_button_read(void)
+{
+  return 0;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  int txsize = len;
+  while (txsize--) {
+    sys_uart_putc(*(uint8_t const*)buf);
+    buf++;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+
+static void timer_handler(void)
+{
+  volatile uint32_t *temp_addr = (uint32_t *)(0x01C20C00 + 0x04);
+
+  /* clear timer */
+  *temp_addr |= 0x01;
+
+  system_ticks++;
+}
+
+static void timer_init(void) {
+  uint32_t temp;
+  volatile uint32_t *temp_addr;
+
+  /* reload value */
+  temp = 12000000 / 1000;
+  temp_addr = (uint32_t *)(0x01C20C00 + 0x14);
+  *temp_addr = temp;
+
+  /* continuous | /2 | 24Mhz |  reload*/
+  temp = (0x00 << 7) | (0x01 << 4) | (0x01 << 2) | (0x00 << 1);
+  temp_addr = (uint32_t *)(0x01C20C00 + 0x10);
+  *temp_addr &= 0xffffff00;
+  *temp_addr |= temp;
+
+  /* open timer irq */
+  temp = 0x01 << 0;
+  temp_addr = (uint32_t *)(0x01C20C00);
+  *temp_addr |= temp;
+
+  /* set init value */
+  temp_addr = (uint32_t *)(0x01C20C00 + 0x18);
+  *temp_addr = 0;
+
+  /* begin run timer */
+  temp = 0x01 << 0;
+  temp_addr = (uint32_t *)(0x01C20C00 + 0x10);
+  *temp_addr |= temp;
+
+  f1c100s_intc_set_isr(F1C100S_IRQ_TIMER0, timer_handler);
+  f1c100s_intc_enable_irq(F1C100S_IRQ_TIMER0);
+}
+#else 
+static void timer_init(void) { }
+#endif
diff --git a/hw/mcu/allwinner/f1c100s/f1c100s.ld b/hw/mcu/allwinner/f1c100s/f1c100s.ld
new file mode 100644
index 000000000..a261618e5
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/f1c100s.ld
@@ -0,0 +1,137 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+STACK_UND_SIZE = 0x10000;
+STACK_ABT_SIZE = 0x10000;
+STACK_IRQ_SIZE = 0x10000;
+STACK_FIQ_SIZE = 0x10000;
+STACK_SRV_SIZE = 0x40000;
+
+MEMORY
+{
+	ram  : org = 0x80000000, len = 8M
+	heap : org = 0x81000000, len = 16M
+}
+
+SECTIONS
+{
+	.bootloader :
+	{
+		PROVIDE(__bootloader_start = .);
+		PROVIDE(__image_start = .);
+		PROVIDE(__text_start = .);
+		*/machine/start.o (.text)
+		*/lib/memcpy.o (.text)
+		*/lib/memset.o (.text)
+		*/machine/sys-uart.o (.text)
+		*/machine/sys-clock.o (.text)
+		*/machine/sys-dram.o (.text)
+		*/machine/sys-mmu.o (.text)
+		*/machine/sys-spi-flash.o (.text)
+		*/machine/sys-copyself.o (.text)
+		PROVIDE(__bootloader_end = .);
+	} > ram
+
+	__bootloader_size = SIZEOF(.bootloader);
+
+	.text :
+	{
+		*/main.o (.text)
+		*(.text*)
+		*(.glue*)
+		*(.note.gnu.build-id)
+		PROVIDE(__text_end = .);
+	} > ram
+
+	.rodata ALIGN(8) :
+	{
+		PROVIDE(__rodata_start = .);
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		PROVIDE(__rodata_end = .);
+	} > ram
+
+	.data_shadow ALIGN(8) :
+	{
+		PROVIDE(__data_shadow_start = .);
+		PROVIDE(__data_shadow_end = (. + SIZEOF(.data)));
+		PROVIDE(__image_end = __data_shadow_end);
+	} > ram
+
+	.data : AT(ADDR(.data_shadow))
+	{
+		PROVIDE(__data_start = .);	
+		*(.data*)
+		. = ALIGN(8);
+  		PROVIDE(__data_end = .);
+	} > ram
+
+	.ARM.exidx ALIGN(8) :
+	{
+		PROVIDE (__exidx_start = .);
+		*(.ARM.exidx*)
+		PROVIDE (__exidx_end = .);
+	} > ram
+
+	.ARM.extab ALIGN(8) :
+	{
+		PROVIDE (__extab_start = .);
+		*(.ARM.extab*)
+		PROVIDE (__extab_end = .);
+	} > ram
+
+	.bss ALIGN(8) (NOLOAD) :
+	{
+		PROVIDE(__bss_start = .);
+		*(.bss*)
+		*(.sbss*)
+		*(COMMON)
+		. = ALIGN(8);
+		PROVIDE(__bss_end = .);
+	} > ram
+
+	.stack ALIGN(8) (NOLOAD) :
+	{
+		PROVIDE(__stack_start = .);
+		PROVIDE(__stack_und_start = .);
+		. += STACK_UND_SIZE;
+		PROVIDE(__stack_und_end = .);
+		. = ALIGN(8);
+		PROVIDE(__stack_abt_start = .);
+		. += STACK_ABT_SIZE;
+		PROVIDE(__stack_abt_end = .);
+		. = ALIGN(8);
+		PROVIDE(__stack_irq_start = .);
+		. += STACK_IRQ_SIZE;
+		PROVIDE(__stack_irq_end = .);
+		. = ALIGN(8);
+		PROVIDE(__stack_fiq_start = .);
+		. += STACK_FIQ_SIZE;
+		PROVIDE(__stack_fiq_end = .);
+		. = ALIGN(8);
+		PROVIDE(__stack_srv_start = .);
+		. += STACK_SRV_SIZE;
+		PROVIDE(__stack_srv_end = .);
+		. = ALIGN(8);
+		PROVIDE(__stack_end = .);
+	} > ram
+
+	.heap ALIGN(8) (NOLOAD) :
+	{
+		PROVIDE(__heap_start = ORIGIN(heap));
+		PROVIDE(__heap_end = ORIGIN(heap) + LENGTH(heap));
+	} > heap
+
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/hw/mcu/allwinner/f1c100s/include/arm32.h b/hw/mcu/allwinner/f1c100s/include/arm32.h
new file mode 100644
index 000000000..a3a254551
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/arm32.h
@@ -0,0 +1,150 @@
+#ifndef __ARM32_H__
+#define __ARM32_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+struct arm_regs_t {
+	uint32_t r[13];
+	uint32_t sp;
+	uint32_t lr;
+	uint32_t pc;
+	uint32_t cpsr;
+};
+
+static inline uint32_t arm32_read_p15_c1(void)
+{
+	uint32_t value;
+
+	__asm__ __volatile__(
+		"mrc p15, 0, %0, c1, c0, 0"
+		: "=r" (value)
+		:
+		: "memory");
+
+	return value;
+}
+
+static inline void arm32_write_p15_c1(uint32_t value)
+{
+	__asm__ __volatile__(
+		"mcr p15, 0, %0, c1, c0, 0"
+		:
+		: "r" (value)
+		: "memory");
+	arm32_read_p15_c1();
+}
+
+static inline void arm32_interrupt_enable(void)
+{
+	uint32_t tmp;
+
+	__asm__ __volatile__(
+		"mrs %0, cpsr\n"
+		"bic %0, %0, #(1<<7)\n"
+		"msr cpsr_cxsf, %0"
+		: "=r" (tmp)
+		:
+		: "memory");
+}
+
+static inline void arm32_interrupt_disable(void)
+{
+	uint32_t tmp;
+
+	__asm__ __volatile__(
+		"mrs %0, cpsr\n"
+		"orr %0, %0, #(1<<7)\n"
+		"msr cpsr_cxsf, %0"
+		: "=r" (tmp)
+		:
+		: "memory");
+}
+
+static inline void arm32_mmu_enable(void)
+{
+	uint32_t value = arm32_read_p15_c1();
+	arm32_write_p15_c1(value | (1 << 0));
+}
+
+static inline void arm32_mmu_disable(void)
+{
+	uint32_t value = arm32_read_p15_c1();
+	arm32_write_p15_c1(value & ~(1 << 0));
+}
+
+static inline void arm32_dcache_enable(void)
+{
+	uint32_t value = arm32_read_p15_c1();
+	arm32_write_p15_c1(value | (1 << 2));
+}
+
+static inline void arm32_dcache_disable(void)
+{
+	uint32_t value = arm32_read_p15_c1();
+	arm32_write_p15_c1(value & ~(1 << 2));
+}
+
+static inline void arm32_icache_enable(void)
+{
+	uint32_t value = arm32_read_p15_c1();
+	arm32_write_p15_c1(value | (1 << 12));
+}
+
+static inline void arm32_icache_disable(void)
+{
+	uint32_t value = arm32_read_p15_c1();
+	arm32_write_p15_c1(value & ~(1 << 12));
+}
+
+static inline uint32_t arm32_smp_processor_id(void)
+{
+	uint32_t tmp;
+
+	__asm__ __volatile__(
+		"mrc p15,0,%0,c0,c0,5\n"
+		"and %0,%0,#0x3\n"
+		: "=r" (tmp)
+		:
+		: "memory");
+	return tmp;
+}
+
+static inline void arm32_ttb_set(uint32_t base)
+{
+	__asm__ __volatile__(
+		"mcr p15, 0, %0, c2, c0, 0"
+		:
+		: "r" (base)
+		: "memory");
+}
+
+static inline void arm32_domain_set(uint32_t domain)
+{
+	__asm__ __volatile__(
+		"mcr p15, 0, %0, c3, c0, 0"
+		:
+		: "r" (domain)
+		: "memory");
+}
+
+static inline void arm32_tlb_invalidate(void)
+{
+	__asm__ __volatile__(
+		"mov r0, #0\n"
+		"mcr p15, 0, r0, c7, c10, 4\n"
+		"mcr p15, 0, r0, c8, c6, 0\n"
+		"mcr p15, 0, r0, c8, c5, 0\n"
+		:
+		:
+		: "r0");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARM32_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s-gpio.h b/hw/mcu/allwinner/f1c100s/include/f1c100s-gpio.h
new file mode 100644
index 000000000..3dbe8bf13
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/f1c100s-gpio.h
@@ -0,0 +1,66 @@
+#ifndef __F1C100S_GPIO_H__
+#define __F1C100S_GPIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define F1C100S_GPIOA0			(0)
+#define F1C100S_GPIOA1			(1)
+#define F1C100S_GPIOA2			(2)
+#define F1C100S_GPIOA3			(3)
+
+#define F1C100S_GPIOC0			(64)
+#define F1C100S_GPIOC1			(65)
+#define F1C100S_GPIOC2			(66)
+#define F1C100S_GPIOC3			(67)
+
+#define F1C100S_GPIOD0			(96)
+#define F1C100S_GPIOD1			(97)
+#define F1C100S_GPIOD2			(98)
+#define F1C100S_GPIOD3			(99)
+#define F1C100S_GPIOD4			(100)
+#define F1C100S_GPIOD5			(101)
+#define F1C100S_GPIOD6			(102)
+#define F1C100S_GPIOD7			(103)
+#define F1C100S_GPIOD8			(104)
+#define F1C100S_GPIOD9			(105)
+#define F1C100S_GPIOD10			(106)
+#define F1C100S_GPIOD11			(107)
+#define F1C100S_GPIOD12			(108)
+#define F1C100S_GPIOD13			(109)
+#define F1C100S_GPIOD14			(110)
+#define F1C100S_GPIOD15			(111)
+#define F1C100S_GPIOD16			(112)
+#define F1C100S_GPIOD17			(113)
+#define F1C100S_GPIOD18			(114)
+#define F1C100S_GPIOD19			(115)
+#define F1C100S_GPIOD20			(116)
+#define F1C100S_GPIOD21			(117)
+
+#define F1C100S_GPIOE0			(128)
+#define F1C100S_GPIOE1			(129)
+#define F1C100S_GPIOE2			(130)
+#define F1C100S_GPIOE3			(131)
+#define F1C100S_GPIOE4			(132)
+#define F1C100S_GPIOE5			(133)
+#define F1C100S_GPIOE6			(134)
+#define F1C100S_GPIOE7			(135)
+#define F1C100S_GPIOE8			(136)
+#define F1C100S_GPIOE9			(137)
+#define F1C100S_GPIOE10			(138)
+#define F1C100S_GPIOE11			(139)
+#define F1C100S_GPIOE12			(140)
+
+#define F1C100S_GPIOF0			(160)
+#define F1C100S_GPIOF1			(161)
+#define F1C100S_GPIOF2			(162)
+#define F1C100S_GPIOF3			(163)
+#define F1C100S_GPIOF4			(164)
+#define F1C100S_GPIOF5			(165)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __F1C100S_GPIO_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s-irq.h b/hw/mcu/allwinner/f1c100s/include/f1c100s-irq.h
new file mode 100644
index 000000000..410d1be93
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/f1c100s-irq.h
@@ -0,0 +1,104 @@
+#ifndef __F1C100S_IRQ_H__
+#define __F1C100S_IRQ_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define F1C100S_IRQ_NMI			(0)
+#define F1C100S_IRQ_UART0		(1)
+#define F1C100S_IRQ_UART1		(2)
+#define F1C100S_IRQ_UART2		(3)
+#define F1C100S_IRQ_SPDIF		(5)
+#define F1C100S_IRQ_CIR			(6)
+#define F1C100S_IRQ_I2C0		(7)
+#define F1C100S_IRQ_I2C1		(8)
+#define F1C100S_IRQ_I2C2		(9)
+#define F1C100S_IRQ_SPI0		(10)
+#define F1C100S_IRQ_SPI1		(11)
+#define F1C100S_IRQ_TIMER0		(13)
+#define F1C100S_IRQ_TIMER1		(14)
+#define F1C100S_IRQ_TIMER2		(15)
+#define F1C100S_IRQ_WDOG		(16)
+#define F1C100S_IRQ_RSB			(17)
+#define F1C100S_IRQ_DMA			(18)
+#define F1C100S_IRQ_TP			(20)
+#define F1C100S_IRQ_AUDIO		(21)
+#define F1C100S_IRQ_LRADC		(22)
+#define F1C100S_IRQ_MMC0		(23)
+#define F1C100S_IRQ_MMC1		(24)
+#define F1C100S_IRQ_USBOTG		(26)
+#define F1C100S_IRQ_TVD			(27)
+#define F1C100S_IRQ_TVE			(28)
+#define F1C100S_IRQ_LCD			(29)
+#define F1C100S_IRQ_DEFE		(30)
+#define F1C100S_IRQ_DEBE		(31)
+#define F1C100S_IRQ_CSI			(32)
+#define F1C100S_IRQ_DEITLA		(33)
+#define F1C100S_IRQ_VE			(34)
+#define F1C100S_IRQ_I2S			(35)
+#define F1C100S_IRQ_GPIOD		(38)
+#define F1C100S_IRQ_GPIOE		(39)
+#define F1C100S_IRQ_GPIOF		(40)
+
+#define F1C100S_IRQ_GPIOD0		(64)
+#define F1C100S_IRQ_GPIOD1		(65)
+#define F1C100S_IRQ_GPIOD2		(66)
+#define F1C100S_IRQ_GPIOD3		(67)
+#define F1C100S_IRQ_GPIOD4		(68)
+#define F1C100S_IRQ_GPIOD5		(69)
+#define F1C100S_IRQ_GPIOD6		(70)
+#define F1C100S_IRQ_GPIOD7		(71)
+#define F1C100S_IRQ_GPIOD8		(72)
+#define F1C100S_IRQ_GPIOD9		(73)
+#define F1C100S_IRQ_GPIOD10		(74)
+#define F1C100S_IRQ_GPIOD11		(75)
+#define F1C100S_IRQ_GPIOD12		(76)
+#define F1C100S_IRQ_GPIOD13		(77)
+#define F1C100S_IRQ_GPIOD14		(78)
+#define F1C100S_IRQ_GPIOD15		(79)
+#define F1C100S_IRQ_GPIOD17		(80)
+#define F1C100S_IRQ_GPIOD18		(81)
+#define F1C100S_IRQ_GPIOD19		(82)
+#define F1C100S_IRQ_GPIOD20		(83)
+#define F1C100S_IRQ_GPIOD21		(84)
+
+#define F1C100S_IRQ_GPIOE0		(96)
+#define F1C100S_IRQ_GPIOE1		(97)
+#define F1C100S_IRQ_GPIOE2		(98)
+#define F1C100S_IRQ_GPIOE3		(99)
+#define F1C100S_IRQ_GPIOE4		(100)
+#define F1C100S_IRQ_GPIOE5		(101)
+#define F1C100S_IRQ_GPIOE6		(102)
+#define F1C100S_IRQ_GPIOE7		(103)
+#define F1C100S_IRQ_GPIOE8		(104)
+#define F1C100S_IRQ_GPIOE9		(105)
+#define F1C100S_IRQ_GPIOE10		(106)
+#define F1C100S_IRQ_GPIOE11		(107)
+#define F1C100S_IRQ_GPIOE12		(108)
+
+#define F1C100S_IRQ_GPIOF0		(128)
+#define F1C100S_IRQ_GPIOF1		(129)
+#define F1C100S_IRQ_GPIOF2		(130)
+#define F1C100S_IRQ_GPIOF3		(131)
+#define F1C100S_IRQ_GPIOF4		(132)
+#define F1C100S_IRQ_GPIOF5		(133)
+
+typedef void (*IRQHandleTypeDef)(void);
+
+uint8_t   f1c100s_intc_get_nirq(void);
+void      f1c100s_intc_dispatch(uint8_t nIRQ);
+void      f1c100s_intc_set_isr(uint8_t nIRQ, IRQHandleTypeDef handle);
+void      f1c100s_intc_enable_irq(uint8_t nIRQ);
+void      f1c100s_intc_disable_irq(uint8_t nIRQ);
+void      f1c100s_intc_unmask_irq(uint8_t nIRQ);
+void      f1c100s_intc_mask_irq(uint8_t nIRQ);
+void      f1c100s_intc_force_irq(uint8_t nIRQ);
+void      f1c100s_intc_clear_pend(uint8_t nIRQ);
+void      f1c100s_intc_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __F1C100S_IRQ_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s-reset.h b/hw/mcu/allwinner/f1c100s/include/f1c100s-reset.h
new file mode 100644
index 000000000..e787a1ac1
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/f1c100s-reset.h
@@ -0,0 +1,39 @@
+#ifndef __F1C100S_RESET_H__
+#define __F1C100S_RESET_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define F1C100S_RESET_DMA			(6)
+#define F1C100S_RESET_SD0			(8)
+#define F1C100S_RESET_SD1			(9)
+#define F1C100S_RESET_SDRAM			(14)
+#define F1C100S_RESET_SPI0			(20)
+#define F1C100S_RESET_SPI1			(21)
+#define F1C100S_RESET_USB_OTG		(24)
+#define F1C100S_RESET_VE			(32)
+#define F1C100S_RESET_LCD			(36)
+#define F1C100S_RESET_DEINTERLACE	(37)
+#define F1C100S_RESET_CSI			(40)
+#define F1C100S_RESET_TVD			(41)
+#define F1C100S_RESET_TVE			(42)
+#define F1C100S_RESET_DEBE			(44)
+#define F1C100S_RESET_DEFE			(46)
+#define F1C100S_RESET_ADDA			(64)
+#define F1C100S_RESET_SPDIF			(65)
+#define F1C100S_RESET_CIR			(66)
+#define F1C100S_RESET_RSB			(67)
+#define F1C100S_RESET_DAUDIO		(76)
+#define F1C100S_RESET_I2C0			(80)
+#define F1C100S_RESET_I2C1			(81)
+#define F1C100S_RESET_I2C2			(82)
+#define F1C100S_RESET_UART0			(84)
+#define F1C100S_RESET_UART1			(85)
+#define F1C100S_RESET_UART2			(86)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __F1C100S_RESET_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s-util.h b/hw/mcu/allwinner/f1c100s/include/f1c100s-util.h
new file mode 100644
index 000000000..cb3829f82
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/f1c100s-util.h
@@ -0,0 +1,139 @@
+// Designed by Hong Xuyao
+
+#ifndef __TARGET_H__
+#define __TARGET_H__
+////////////////////////////////////////////////////////////////////////////////
+#include <stdint.h>
+typedef unsigned long       ubase_t;
+
+#define MEM_PI_SRAM     __attribute__((section("SRAM")))
+
+#define MEM_PI_SUMMARY  __attribute__((section("SUMMARY")))
+
+#define MEM_PI_NOINIT   __attribute__((section("NOINIT"),zero_init))
+
+#define MEM_PI_CPUONLY  __attribute__((section("CPUONLY"),zero_init))
+
+#define MEM_PI_HARDWARE __attribute__((section("HARDWARE"),zero_init,aligned(32)))
+
+#define MEM_PI_NCNB     __attribute__((section("NCNB"),zero_init,aligned(32)))
+
+#define MEM_PI_STACK    __attribute__((section("STACK"),zero_init,aligned(8)))
+
+#define CACHE_ALIGNED   __attribute__((aligned(32)))
+
+#ifndef INLINE
+#define INLINE        __attribute__((always_inline))
+#endif
+
+#ifndef NOINLINE
+#define NOINLINE      __attribute__((noinline))
+#endif
+
+#ifndef NOINLINE_FUNC
+#define NOINLINE_FUNC __attribute__((noinline))
+#endif
+
+#ifndef ALIGN
+#define ALIGN(n)      __attribute__((aligned(n)))
+#endif
+
+#define CPU_SR_DECL   ubase_t cpu_sr
+
+#ifdef __thumb__
+#define __SWITCH_TO_ARM__
+#pragma arm
+#endif
+
+#if 0
+#define CPU_ENTER_CRITICAL()  do{cpu_sr = util_enter_critical();}while(0)
+#else
+#define CPU_ENTER_CRITICAL()  do{cpu_sr = __fast_enter_critical();}while(0)
+static inline ubase_t __fast_enter_critical(void)
+{
+  ubase_t cpu_sr, tmp_sr;
+  __asm volatile {
+    MRS cpu_sr, CPSR
+    ORR tmp_sr, cpu_sr, #0xC0
+    MSR CPSR_c, tmp_sr
+  }
+  return cpu_sr;
+}
+#endif
+
+#if 0
+#define CPU_EXIT_CRITICAL()   do{util_exit_critical(cpu_sr);}while(0)
+#else
+#define CPU_EXIT_CRITICAL()   do{__fast_exit_critical(cpu_sr);}while(0)
+static inline void __fast_exit_critical(ubase_t cpu_sr)
+{
+  __asm volatile {
+    MSR CPSR_c, cpu_sr
+  }
+}
+#endif
+
+static inline unsigned CPU_CLZ16(uint16_t val)
+{
+  __asm volatile {
+    CLZ val, val
+  }
+  return (val - 16);
+}
+
+static inline uint8_t __swap_byte(uint8_t newval, uint8_t volatile* pmem)
+{
+  uint8_t oldval;
+  __asm volatile {
+    SWPB  oldval, newval, [pmem]
+  };
+  return oldval;
+}
+
+static inline uint32_t UTL_REV32(uint32_t val)
+{
+  uint32_t tmpval;
+  __asm volatile {
+    EOR tmpval, val, val, ROR #16
+    MOV tmpval, tmpval, LSR #8
+    BIC tmpval, tmpval, #0xFF00
+    EOR val, tmpval, val, ROR #8
+  }
+  return val;
+}
+
+static inline uint16_t UTL_REV16(uint16_t val)
+{
+  uint32_t tmpval;
+  __asm volatile {
+    LSR tmpval, val, #8
+    ORR val, tmpval, val, LSL #8
+    BIC val, val, #0xFF0000
+  }
+  return val;
+}
+
+#ifdef __SWITCH_TO_ARM__ 
+#undef __SWITCH_TO_ARM__
+#pragma thumb
+#endif
+
+#ifndef COUNTOF
+#define COUNTOF(ar) (sizeof(ar)/sizeof(ar[0]))
+#endif
+/*
+void    util_halt(void);
+void    util_fastloop(ubase_t n);
+ubase_t util_getCPSR(void);
+ubase_t util_enter_critical(void);
+void    util_exit_critical(ubase_t sr);
+void    util_enable_interrupt(void);
+void    util_disable_interrupt(void);
+
+void    target_wdt_setup(void);
+void    target_wdt_feed(void);
+void    target_reset(void);
+*/
+////////////////////////////////////////////////////////////////////////////////
+#endif /* __TARGET_H__ */
+
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-ccu.h b/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-ccu.h
new file mode 100644
index 000000000..1770ad7ff
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-ccu.h
@@ -0,0 +1,55 @@
+#ifndef __F1C100S_REG_CCU_H__
+#define __F1C100S_REG_CCU_H__
+
+#define F1C100S_CCU_BASE		(0x01c20000)
+
+#define CCU_PLL_CPU_CTRL		(0x000)
+#define CCU_PLL_AUDIO_CTRL		(0x008)
+#define CCU_PLL_VIDEO_CTRL		(0x010)
+#define CCU_PLL_VE_CTRL			(0x018)
+#define CCU_PLL_DDR_CTRL		(0x020)
+#define CCU_PLL_PERIPH_CTRL		(0x028)
+#define CCU_CPU_CFG				(0x050)
+#define CCU_AHB_APB_CFG			(0x054)
+
+#define CCU_BUS_CLK_GATE0		(0x060)
+#define CCU_BUS_CLK_GATE1		(0x064)
+#define CCU_BUS_CLK_GATE2		(0x068)
+
+#define CCU_SDMMC0_CLK			(0x088)
+#define CCU_SDMMC1_CLK			(0x08c)
+#define CCU_DAUDIO_CLK			(0x0b0)
+#define CCU_SPDIF_CLK			(0x0b4)
+#define CCU_I2S_CLK				(0x0b8)
+#define CCU_USBPHY_CFG			(0x0cc)
+#define CCU_DRAM_CLK_GATE		(0x100)
+#define CCU_DEBE_CLK			(0x104)
+#define CCU_DEFE_CLK			(0x10c)
+#define CCU_LCD_CLK				(0x118)
+#define CCU_DEINTERLACE_CLK		(0x11c)
+#define CCU_TVE_CLK				(0x120)
+#define CCU_TVD_CLK				(0x124)
+#define CCU_CSI_CLK				(0x134)
+#define CCU_VE_CLK				(0x13c)
+#define CCU_ADDA_CLK			(0x140)
+#define CCU_AVS_CLK				(0x144)
+
+#define CCU_PLL_STABLE_TIME0	(0x200)
+#define CCU_PLL_STABLE_TIME1	(0x204)
+#define CCU_PLL_CPU_BIAS		(0x220)
+#define CCU_PLL_AUDIO_BIAS		(0x224)
+#define CCU_PLL_VIDEO_BIAS		(0x228)
+#define CCU_PLL_VE_BIAS			(0x22c)
+#define CCU_PLL_DDR0_BIAS		(0x230)
+#define CCU_PLL_PERIPH_BIAS		(0x234)
+#define CCU_PLL_CPU_TUN			(0x250)
+#define CCU_PLL_DDR_TUN			(0x260)
+#define CCU_PLL_AUDIO_PAT		(0x284)
+#define CCU_PLL_VIDEO_PAT		(0x288)
+#define CCU_PLL_DDR0_PAT		(0x290)
+
+#define CCU_BUS_SOFT_RST0		(0x2c0)
+#define CCU_BUS_SOFT_RST1		(0x2c4)
+#define CCU_BUS_SOFT_RST3		(0x2d0)
+
+#endif /* __F1C100S_REG_CCU_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-dram.h b/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-dram.h
new file mode 100644
index 000000000..8a0ac3e0e
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-dram.h
@@ -0,0 +1,39 @@
+#ifndef __F1C100S_REG_DRAM_H__
+#define __F1C100S_REG_DRAM_H__
+
+#define F1C100S_DRAM_BASE	(0x01c01000)
+
+#define DRAM_SCONR			(0x00)
+#define DRAM_STMG0R			(0x04)
+#define DRAM_STMG1R			(0x08)
+#define DRAM_SCTLR			(0x0c)
+#define DRAM_SREFR			(0x10)
+#define DRAM_SEXTMR			(0x14)
+#define DRAM_DDLYR			(0x24)
+#define DRAM_DADRR			(0x28)
+#define DRAM_DVALR			(0x2c)
+#define DRAM_DRPTR0			(0x30)
+#define DRAM_DRPTR1			(0x34)
+#define DRAM_DRPTR2			(0x38)
+#define DRAM_DRPTR3			(0x3c)
+#define DRAM_SEFR			(0x40)
+#define DRAM_MAE			(0x44)
+#define DRAM_ASPR			(0x48)
+#define DRAM_SDLY0			(0x4C)
+#define DRAM_SDLY1			(0x50)
+#define DRAM_SDLY2			(0x54)
+#define DRAM_MCR0			(0x100)
+#define DRAM_MCR1			(0x104)
+#define DRAM_MCR2			(0x108)
+#define DRAM_MCR3			(0x10c)
+#define DRAM_MCR4			(0x110)
+#define DRAM_MCR5			(0x114)
+#define DRAM_MCR6			(0x118)
+#define DRAM_MCR7			(0x11c)
+#define DRAM_MCR8			(0x120)
+#define DRAM_MCR9			(0x124)
+#define DRAM_MCR10			(0x128)
+#define DRAM_MCR11			(0x12c)
+#define DRAM_BWCR			(0x140)
+
+#endif /* __F1C100S_REG_DRAM_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/io.h b/hw/mcu/allwinner/f1c100s/include/io.h
new file mode 100644
index 000000000..f0dad1785
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/io.h
@@ -0,0 +1,57 @@
+#ifndef __IO_H__
+#define __IO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <types.h>
+
+static inline u8_t read8(virtual_addr_t addr)
+{
+	return( *((volatile u8_t *)(addr)) );
+}
+
+static inline u16_t read16(virtual_addr_t addr)
+{
+	return( *((volatile u16_t *)(addr)) );
+}
+
+static inline u32_t read32(virtual_addr_t addr)
+{
+	return( *((volatile u32_t *)(addr)) );
+}
+
+static inline u64_t read64(virtual_addr_t addr)
+{
+	return( *((volatile u64_t *)(addr)) );
+}
+
+static inline void write8(virtual_addr_t addr, u8_t value)
+{
+	*((volatile u8_t *)(addr)) = value;
+}
+
+static inline void write16(virtual_addr_t addr, u16_t value)
+{
+	*((volatile u16_t *)(addr)) = value;
+}
+
+static inline void write32(virtual_addr_t addr, u32_t value)
+{
+	*((volatile u32_t *)(addr)) = value;
+}
+
+static inline void write64(virtual_addr_t addr, u64_t value)
+{
+	*((volatile u64_t *)(addr)) = value;
+}
+
+virtual_addr_t phys_to_virt(physical_addr_t phys);
+physical_addr_t virt_to_phys(virtual_addr_t virt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IO_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/irqflags.h b/hw/mcu/allwinner/f1c100s/include/irqflags.h
new file mode 100644
index 000000000..e4ef97cd2
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/irqflags.h
@@ -0,0 +1,104 @@
+#ifndef __ARM32_IRQFLAGS_H__
+#define __ARM32_IRQFLAGS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <types.h>
+
+#if __ARM32_ARCH__ == 5
+
+static inline void arch_local_irq_enable(void)
+{
+	irq_flags_t temp;
+
+	__asm__ __volatile__(
+		"mrs %0, cpsr\n"
+		"bic %0, %0, #(1<<7)\n"
+		"msr cpsr_c, %0"
+		: "=r" (temp)
+		:
+		: "memory", "cc");
+}
+
+static inline void arch_local_irq_disable(void)
+{
+	irq_flags_t temp;
+
+	__asm__ __volatile__(
+		"mrs %0, cpsr\n"
+		"orr %0, %0, #(1<<7)\n"
+		"msr cpsr_c, %0"
+		: "=r" (temp)
+		:
+		: "memory", "cc");
+}
+
+static inline irq_flags_t arch_local_irq_save(void)
+{
+	irq_flags_t flags, temp;
+
+	__asm__ __volatile__(
+		"mrs %0, cpsr\n"
+		"orr %1, %0, #(1<<7)\n"
+		"msr cpsr_c, %1"
+		: "=r" (flags), "=r" (temp)
+		:
+		: "memory", "cc");
+
+	return flags;
+}
+
+static inline void arch_local_irq_restore(irq_flags_t flags)
+{
+	__asm__ __volatile__(
+		"msr cpsr_c, %0"
+		:
+		: "r" (flags)
+		: "memory", "cc");
+}
+#else
+static inline void arch_local_irq_enable(void)
+{
+	__asm__ __volatile__("cpsie i" ::: "memory", "cc");
+}
+
+static inline void arch_local_irq_disable(void)
+{
+	__asm__ __volatile__("cpsid i" ::: "memory", "cc");
+}
+
+static inline irq_flags_t arch_local_irq_save(void)
+{
+	irq_flags_t flags;
+
+	__asm__ __volatile__(
+		"mrs %0, cpsr\n"
+		"cpsid i"
+		: "=r" (flags)
+		:
+		: "memory", "cc");
+	return flags;
+}
+
+static inline void arch_local_irq_restore(irq_flags_t flags)
+{
+	__asm__ __volatile__(
+		"msr cpsr_c, %0"
+		:
+		: "r" (flags)
+		: "memory", "cc");
+}
+#endif
+
+#define local_irq_enable()			do { arch_local_irq_enable(); } while(0)
+#define local_irq_disable()			do { arch_local_irq_disable(); } while(0)
+#define local_irq_save(flags)		do { flags = arch_local_irq_save(); } while(0)
+#define local_irq_restore(flags)	do { arch_local_irq_restore(flags); } while(0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARM32_IRQFLAGS_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/malloc.h b/hw/mcu/allwinner/f1c100s/include/malloc.h
new file mode 100644
index 000000000..6669fe48c
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/malloc.h
@@ -0,0 +1,35 @@
+#ifndef __MALLOC_H__
+#define __MALLOC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <types.h>
+#include <stddef.h>
+#include <string.h>
+#include <assert.h>
+
+void * mm_create(void * mem, size_t bytes);
+void mm_destroy(void * mm);
+void * mm_get_pool(void * mm);
+void * mm_add_pool(void * mm, void * mem, size_t bytes);
+void mm_remove_pool(void * mm, void * pool);
+void * mm_malloc(void * mm, size_t size);
+void * mm_memalign(void * mm, size_t align, size_t size);
+void * mm_realloc(void * mm, void * ptr, size_t size);
+void mm_free(void * mm, void * ptr);
+
+void * malloc(size_t size);
+void * memalign(size_t align, size_t size);
+void * realloc(void * ptr, size_t size);
+void * calloc(size_t nmemb, size_t size);
+void free(void * ptr);
+
+void do_init_mem_pool(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MALLOC_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/printf.h b/hw/mcu/allwinner/f1c100s/include/printf.h
new file mode 100644
index 000000000..632bfc20e
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/printf.h
@@ -0,0 +1,99 @@
+///////////////////////////////////////////////////////////////////////////////
+// \author (c) Marco Paland (info@paland.com)
+//             2014-2018, PALANDesign Hannover, Germany
+//
+// \license The MIT License (MIT)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+// 
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+// 
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on
+//        embedded systems with a very limited resources.
+//        Use this instead of bloated standard/newlib printf.
+//        These routines are thread safe and reentrant!
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#ifndef _PRINTF_H_
+#define _PRINTF_H_
+
+#include <stdarg.h>
+#include <stddef.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Output a character to a custom device like UART, used by the printf() function
+ * This function is declared here only. You have to write your custom implementation somewhere
+ * \param character Character to output
+ */
+void _putchar(char character);
+
+
+/**
+ * Tiny printf implementation
+ * You have to implement _putchar if you use printf()
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are written into the array, not counting the terminating null character
+ */
+int printf(const char* format, ...);
+
+
+/**
+ * Tiny sprintf implementation
+ * Due to security reasons (buffer overflow) YOU SHOULD CONSIDER USING (V)SNPRINTF INSTEAD!
+ * \param buffer A pointer to the buffer where to store the formatted string. MUST be big enough to store the output!
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character
+ */
+int sprintf(char* buffer, const char* format, ...);
+
+
+/**
+ * Tiny snprintf/vsnprintf implementation
+ * \param buffer A pointer to the buffer where to store the formatted string
+ * \param count The maximum number of characters to store in the buffer, including a terminating null character
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character
+ *         If the formatted string is truncated the buffer size (count) is returned
+ */
+int  snprintf(char* buffer, size_t count, const char* format, ...);
+int vsnprintf(char* buffer, size_t count, const char* format, va_list va);
+
+
+/**
+ * printf with output function
+ * You may use this as dynamic alternative to printf() with its fixed _putchar() output
+ * \param out An output function which takes one character and an argument pointer
+ * \param arg An argument pointer for user data passed to output function
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are sent to the output function, not counting the terminating null character
+ */
+int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // _PRINTF_H_
diff --git a/hw/mcu/allwinner/f1c100s/include/sizes.h b/hw/mcu/allwinner/f1c100s/include/sizes.h
new file mode 100644
index 000000000..3edeed503
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/sizes.h
@@ -0,0 +1,42 @@
+#ifndef __SIZES_H__
+#define __SIZES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SZ_16				(0x00000010)
+#define SZ_256				(0x00000100)
+#define SZ_512				(0x00000200)
+
+#define SZ_1K				(0x00000400)
+#define SZ_4K				(0x00001000)
+#define SZ_8K				(0x00002000)
+#define SZ_16K				(0x00004000)
+#define SZ_32K				(0x00008000)
+#define SZ_64K				(0x00010000)
+#define SZ_128K				(0x00020000)
+#define SZ_256K				(0x00040000)
+#define SZ_512K				(0x00080000)
+
+#define SZ_1M				(0x00100000)
+#define SZ_2M				(0x00200000)
+#define SZ_4M				(0x00400000)
+#define SZ_8M				(0x00800000)
+#define SZ_16M				(0x01000000)
+#define SZ_32M				(0x02000000)
+#define SZ_64M				(0x04000000)
+#define SZ_128M				(0x08000000)
+#define SZ_256M				(0x10000000)
+#define SZ_512M				(0x20000000)
+
+#define SZ_1G				(0x40000000)
+#define SZ_2G				(0x80000000)
+
+#define ARRAY_SIZE(array)	( sizeof(array) / sizeof((array)[0]) )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SIZES_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/types.h b/hw/mcu/allwinner/f1c100s/include/types.h
new file mode 100644
index 000000000..61b87b6d7
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/include/types.h
@@ -0,0 +1,55 @@
+#ifndef __ARM32_TYPES_H__
+#define __ARM32_TYPES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef signed char				s8_t;
+typedef unsigned char			u8_t;
+
+typedef signed short			s16_t;
+typedef unsigned short			u16_t;
+
+typedef signed int				s32_t;
+typedef unsigned int			u32_t;
+
+typedef signed long long		s64_t;
+typedef unsigned long long		u64_t;
+
+typedef signed long long		intmax_t;
+typedef unsigned long long		uintmax_t;
+
+typedef signed int				ptrdiff_t;
+typedef signed int				intptr_t;
+typedef unsigned int 			uintptr_t;
+
+typedef unsigned int			size_t;
+typedef signed int				ssize_t;
+
+// typedef signed int				off_t;
+typedef signed long long		loff_t;
+
+typedef signed int				bool_t;
+
+typedef signed int				register_t;
+typedef unsigned int			irq_flags_t;
+
+typedef unsigned int			virtual_addr_t;
+typedef unsigned int			virtual_size_t;
+typedef unsigned int			physical_addr_t;
+typedef unsigned int			physical_size_t;
+
+typedef struct {
+	volatile long counter;
+} atomic_t;
+
+typedef struct {
+	volatile long lock;
+} spinlock_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARM32_TYPES_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/lib/malloc.c b/hw/mcu/allwinner/f1c100s/lib/malloc.c
new file mode 100644
index 000000000..763746a47
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/lib/malloc.c
@@ -0,0 +1,834 @@
+/*
+ * lib/libc/malloc/malloc.c
+ */
+
+#include <malloc.h>
+
+static void * __heap_pool = NULL;
+
+/*
+ * Some macros.
+ */
+#define tlsf_cast(t, exp)		((t)(exp))
+#define tlsf_min(a, b)			((a) < (b) ? (a) : (b))
+#define tlsf_max(a, b)			((a) > (b) ? (a) : (b))
+
+#define tlsf_assert				assert
+#define tlsf_insist(x)			{ tlsf_assert(x); if (!(x)) { status--; } }
+
+#if defined(__ARM64__) || defined(__X64__)
+# define TLSF_64BIT
+#else
+# undef TLSF_64BIT
+#endif
+
+/*
+ * Public constants
+ */
+enum tlsf_public
+{
+	/*
+	 * log2 of number of linear subdivisions of block sizes
+	 */
+	SL_INDEX_COUNT_LOG2 = 5,
+};
+
+/*
+ * Private constants
+ */
+enum tlsf_private
+{
+#if defined(TLSF_64BIT)
+	/*
+	 * All allocation sizes and addresses are aligned to 8 bytes
+	 */
+	ALIGN_SIZE_LOG2 = 3,
+#else
+	/*
+	 * All allocation sizes and addresses are aligned to 4 bytes
+	 */
+	ALIGN_SIZE_LOG2 = 2,
+#endif
+	ALIGN_SIZE = (1 << ALIGN_SIZE_LOG2),
+
+#if defined(TLSF_64BIT)
+	FL_INDEX_MAX = 32,
+#else
+	FL_INDEX_MAX = 30,
+#endif
+	SL_INDEX_COUNT = (1 << SL_INDEX_COUNT_LOG2),
+	FL_INDEX_SHIFT = (SL_INDEX_COUNT_LOG2 + ALIGN_SIZE_LOG2),
+	FL_INDEX_COUNT = (FL_INDEX_MAX - FL_INDEX_SHIFT + 1),
+
+	SMALL_BLOCK_SIZE = (1 << FL_INDEX_SHIFT),
+};
+
+/*
+ * Block header structure
+ */
+typedef struct block_header_t
+{
+	/*
+	 * Points to the previous physical block
+	 */
+	struct block_header_t * prev_phys_block;
+
+	/*
+	 * The size of this block, excluding the block header
+	 */
+	size_t size;
+
+	/*
+	 * Next and previous free blocks
+	 */
+	struct block_header_t * next_free;
+	struct block_header_t * prev_free;
+} block_header_t;
+
+/*
+ * The TLSF control structure.
+ */
+typedef struct control_t
+{
+	/*
+	 * Empty lists point at this block to indicate they are free.
+	 */
+	block_header_t block_null;
+
+	/*
+	 * Bitmaps for free lists.
+	 */
+	unsigned int fl_bitmap;
+	unsigned int sl_bitmap[FL_INDEX_COUNT];
+
+	/*
+	 * Head of free lists.
+	 */
+	block_header_t * blocks[FL_INDEX_COUNT][SL_INDEX_COUNT];
+} control_t;
+
+/*
+ * A type used for casting when doing pointer arithmetic.
+ */
+typedef ptrdiff_t	tlsfptr_t;
+
+/*
+ * Associated constants
+ */
+static const size_t block_header_free_bit = 1 << 0;
+static const size_t block_header_prev_free_bit = 1 << 1;
+static const size_t block_header_overhead = sizeof(size_t);
+static const size_t block_start_offset = offsetof(block_header_t, size) + sizeof(size_t);
+static const size_t block_size_min = sizeof(block_header_t) - sizeof(block_header_t *);
+static const size_t block_size_max = tlsf_cast(size_t, 1) << FL_INDEX_MAX;
+
+#if defined(__GNUC__) && (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)) && defined(__GNUC_PATCHLEVEL__)
+static int tlsf_ffs(unsigned int word)
+{
+	return __builtin_ffs(word) - 1;
+}
+
+static int tlsf_fls(unsigned int word)
+{
+	const int bit = word ? 32 - __builtin_clz(word) : 0;
+	return bit - 1;
+}
+#else
+static int tlsf_fls_generic(unsigned int word)
+{
+	int bit = 32;
+
+	if (!word) bit -= 1;
+	if (!(word & 0xffff0000)) { word <<= 16; bit -= 16; }
+	if (!(word & 0xff000000)) { word <<= 8; bit -= 8; }
+	if (!(word & 0xf0000000)) { word <<= 4; bit -= 4; }
+	if (!(word & 0xc0000000)) { word <<= 2; bit -= 2; }
+	if (!(word & 0x80000000)) { word <<= 1; bit -= 1; }
+
+	return bit;
+}
+
+static int tlsf_ffs(unsigned int word)
+{
+	return tlsf_fls_generic(word & (~word + 1)) - 1;
+}
+
+static int tlsf_fls(unsigned int word)
+{
+	return tlsf_fls_generic(word) - 1;
+}
+#endif
+
+#if defined(TLSF_64BIT)
+static int tlsf_fls_sizet(size_t size)
+{
+	int high = (int)(size >> 32);
+	int bits = 0;
+	if(high)
+	{
+		bits = 32 + tlsf_fls(high);
+	}
+	else
+	{
+		bits = tlsf_fls((int)size & 0xffffffff);
+
+	}
+	return bits;
+}
+#else
+#define tlsf_fls_sizet		tlsf_fls
+#endif
+
+static size_t block_get_size(const block_header_t * block)
+{
+	return block->size & ~(block_header_free_bit | block_header_prev_free_bit);
+}
+
+static void block_set_size(block_header_t * block, size_t size)
+{
+	const size_t oldsize = block->size;
+	block->size = size | (oldsize & (block_header_free_bit | block_header_prev_free_bit));
+}
+
+static int block_is_last(const block_header_t * block)
+{
+	return (0 == block_get_size(block));
+}
+
+static int block_is_free(const block_header_t * block)
+{
+	return tlsf_cast(int, block->size & block_header_free_bit);
+}
+
+static void block_set_free(block_header_t * block)
+{
+	block->size |= block_header_free_bit;
+}
+
+static void block_set_used(block_header_t * block)
+{
+	block->size &= ~block_header_free_bit;
+}
+
+static int block_is_prev_free(const block_header_t * block)
+{
+	return tlsf_cast(int, block->size & block_header_prev_free_bit);
+}
+
+static void block_set_prev_free(block_header_t * block)
+{
+	block->size |= block_header_prev_free_bit;
+}
+
+static void block_set_prev_used(block_header_t * block)
+{
+	block->size &= ~block_header_prev_free_bit;
+}
+
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-align"
+static block_header_t * block_from_ptr(void * ptr)
+{
+	return tlsf_cast(block_header_t *, tlsf_cast(unsigned char*, ptr) - block_start_offset);
+}
+#pragma GCC diagnostic pop
+
+static void * block_to_ptr(block_header_t * block)
+{
+	return tlsf_cast(void *, tlsf_cast(unsigned char*, block) + block_start_offset);
+}
+
+static block_header_t * offset_to_block(void * ptr, size_t size)
+{
+	return tlsf_cast(block_header_t *, tlsf_cast(tlsfptr_t, ptr) + size);
+}
+
+static block_header_t * block_prev(block_header_t * block)
+{
+	return block->prev_phys_block;
+}
+
+static block_header_t * block_next(block_header_t * block)
+{
+	block_header_t * next = offset_to_block(block_to_ptr(block), block_get_size(block) - block_header_overhead);
+	tlsf_assert(!block_is_last(block));
+	return next;
+}
+
+static block_header_t * block_link_next(block_header_t * block)
+{
+	block_header_t * next = block_next(block);
+	next->prev_phys_block = block;
+	return next;
+}
+
+static void block_mark_as_free(block_header_t * block)
+{
+	block_header_t * next = block_link_next(block);
+	block_set_prev_free(next);
+	block_set_free(block);
+}
+
+static void block_mark_as_used(block_header_t * block)
+{
+	block_header_t * next = block_next(block);
+	block_set_prev_used(next);
+	block_set_used(block);
+}
+
+static size_t align_up(size_t x, size_t align)
+{
+	tlsf_assert(0 == (align & (align - 1)) && "must align to a power of two");
+	return (x + (align - 1)) & ~(align - 1);
+}
+
+static size_t align_down(size_t x, size_t align)
+{
+	tlsf_assert(0 == (align & (align - 1)) && "must align to a power of two");
+	return x - (x & (align - 1));
+}
+
+static void * align_ptr(const void * ptr, size_t align)
+{
+	const tlsfptr_t aligned = (tlsf_cast(tlsfptr_t, ptr) + (align - 1)) & ~(align - 1);
+	tlsf_assert(0 == (align & (align - 1)) && "must align to a power of two");
+	return tlsf_cast(void*, aligned);
+}
+
+static size_t adjust_request_size(size_t size, size_t align)
+{
+	size_t adjust = 0;
+	if (size && size < block_size_max)
+	{
+		const size_t aligned = align_up(size, align);
+		adjust = tlsf_max(aligned, block_size_min);
+	}
+	return adjust;
+}
+
+static void mapping_insert(size_t size, int * fli, int * sli)
+{
+	int fl, sl;
+	if (size < SMALL_BLOCK_SIZE)
+	{
+		fl = 0;
+		sl = tlsf_cast(int, size) / (SMALL_BLOCK_SIZE / SL_INDEX_COUNT);
+	}
+	else
+	{
+		fl = tlsf_fls_sizet(size);
+		sl = tlsf_cast(int, size >> (fl - SL_INDEX_COUNT_LOG2)) ^ (1 << SL_INDEX_COUNT_LOG2);
+		fl -= (FL_INDEX_SHIFT - 1);
+	}
+	*fli = fl;
+	*sli = sl;
+}
+
+static void mapping_search(size_t size, int * fli, int * sli)
+{
+	if (size >= (1 << SL_INDEX_COUNT_LOG2))
+	{
+		const size_t round = (1 << (tlsf_fls_sizet(size) - SL_INDEX_COUNT_LOG2)) - 1;
+		size += round;
+	}
+	mapping_insert(size, fli, sli);
+}
+
+static block_header_t * search_suitable_block(control_t * control, int * fli, int * sli)
+{
+	int fl = *fli;
+	int sl = *sli;
+
+	unsigned int sl_map = control->sl_bitmap[fl] & (~0U << sl);
+	if (!sl_map)
+	{
+		const unsigned int fl_map = control->fl_bitmap & (~0U << (fl + 1));
+		if (!fl_map)
+		{
+			return 0;
+		}
+
+		fl = tlsf_ffs(fl_map);
+		*fli = fl;
+		sl_map = control->sl_bitmap[fl];
+	}
+	tlsf_assert(sl_map && "internal error - second level bitmap is null");
+	sl = tlsf_ffs(sl_map);
+	*sli = sl;
+
+	return control->blocks[fl][sl];
+}
+
+static void remove_free_block(control_t * control, block_header_t * block, int fl, int sl)
+{
+	block_header_t * prev = block->prev_free;
+	block_header_t * next = block->next_free;
+	tlsf_assert(prev && "prev_free field can not be null");
+	tlsf_assert(next && "next_free field can not be null");
+	next->prev_free = prev;
+	prev->next_free = next;
+
+	if (control->blocks[fl][sl] == block)
+	{
+		control->blocks[fl][sl] = next;
+
+		if (next == &control->block_null)
+		{
+			control->sl_bitmap[fl] &= ~(1 << sl);
+
+			if (!control->sl_bitmap[fl])
+			{
+				control->fl_bitmap &= ~(1 << fl);
+			}
+		}
+	}
+}
+
+static void insert_free_block(control_t * control, block_header_t * block, int fl, int sl)
+{
+	block_header_t * current = control->blocks[fl][sl];
+	tlsf_assert(current && "free list cannot have a null entry");
+	tlsf_assert(block && "cannot insert a null entry into the free list");
+	block->next_free = current;
+	block->prev_free = &control->block_null;
+	current->prev_free = block;
+
+	tlsf_assert(block_to_ptr(block) == align_ptr(block_to_ptr(block), ALIGN_SIZE) && "block not aligned properly");
+
+	control->blocks[fl][sl] = block;
+	control->fl_bitmap |= (1 << fl);
+	control->sl_bitmap[fl] |= (1 << sl);
+}
+
+static void block_remove(control_t * control, block_header_t * block)
+{
+	int fl, sl;
+	mapping_insert(block_get_size(block), &fl, &sl);
+	remove_free_block(control, block, fl, sl);
+}
+
+static void block_insert(control_t * control, block_header_t * block)
+{
+	int fl, sl;
+	mapping_insert(block_get_size(block), &fl, &sl);
+	insert_free_block(control, block, fl, sl);
+}
+
+static int block_can_split(block_header_t * block, size_t size)
+{
+	return block_get_size(block) >= sizeof(block_header_t) + size;
+}
+
+static block_header_t * block_split(block_header_t * block, size_t size)
+{
+	block_header_t* remaining = offset_to_block(block_to_ptr(block), size - block_header_overhead);
+	const size_t remain_size = block_get_size(block) - (size + block_header_overhead);
+
+	tlsf_assert(block_to_ptr(remaining) == align_ptr(block_to_ptr(remaining), ALIGN_SIZE) && "remaining block not aligned properly");
+
+	tlsf_assert(block_get_size(block) == remain_size + size + block_header_overhead);
+	block_set_size(remaining, remain_size);
+	tlsf_assert(block_get_size(remaining) >= block_size_min && "block split with invalid size");
+
+	block_set_size(block, size);
+	block_mark_as_free(remaining);
+
+	return remaining;
+}
+
+static block_header_t * block_absorb(block_header_t * prev, block_header_t * block)
+{
+	tlsf_assert(!block_is_last(prev) && "previous block can't be last!");
+	prev->size += block_get_size(block) + block_header_overhead;
+	block_link_next(prev);
+	return prev;
+}
+
+static block_header_t * block_merge_prev(control_t * control, block_header_t * block)
+{
+	if (block_is_prev_free(block))
+	{
+		block_header_t* prev = block_prev(block);
+		tlsf_assert(prev && "prev physical block can't be null");
+		tlsf_assert(block_is_free(prev) && "prev block is not free though marked as such");
+		block_remove(control, prev);
+		block = block_absorb(prev, block);
+	}
+
+	return block;
+}
+
+static block_header_t * block_merge_next(control_t * control, block_header_t * block)
+{
+	block_header_t* next = block_next(block);
+	tlsf_assert(next && "next physical block can't be null");
+
+	if (block_is_free(next))
+	{
+		tlsf_assert(!block_is_last(block) && "previous block can't be last!");
+		block_remove(control, next);
+		block = block_absorb(block, next);
+	}
+
+	return block;
+}
+
+static void block_trim_free(control_t * control, block_header_t * block, size_t size)
+{
+	tlsf_assert(block_is_free(block) && "block must be free");
+	if (block_can_split(block, size))
+	{
+		block_header_t* remaining_block = block_split(block, size);
+		block_link_next(block);
+		block_set_prev_free(remaining_block);
+		block_insert(control, remaining_block);
+	}
+}
+
+static void block_trim_used(control_t * control, block_header_t * block, size_t size)
+{
+	tlsf_assert(!block_is_free(block) && "block must be used");
+	if (block_can_split(block, size))
+	{
+		block_header_t* remaining_block = block_split(block, size);
+		block_set_prev_used(remaining_block);
+
+		remaining_block = block_merge_next(control, remaining_block);
+		block_insert(control, remaining_block);
+	}
+}
+
+static block_header_t * block_trim_free_leading(control_t * control, block_header_t * block, size_t size)
+{
+	block_header_t * remaining_block = block;
+	if (block_can_split(block, size))
+	{
+		remaining_block = block_split(block, size - block_header_overhead);
+		block_set_prev_free(remaining_block);
+
+		block_link_next(block);
+		block_insert(control, block);
+	}
+
+	return remaining_block;
+}
+
+static block_header_t * block_locate_free(control_t * control, size_t size)
+{
+	int fl = 0, sl = 0;
+	block_header_t * block = 0;
+
+	if (size)
+	{
+		mapping_search(size, &fl, &sl);
+		block = search_suitable_block(control, &fl, &sl);
+	}
+
+	if (block)
+	{
+		tlsf_assert(block_get_size(block) >= size);
+		remove_free_block(control, block, fl, sl);
+	}
+
+	return block;
+}
+
+static void * block_prepare_used(control_t * control, block_header_t * block, size_t size)
+{
+	void* p = 0;
+	if (block)
+	{
+		block_trim_free(control, block, size);
+		block_mark_as_used(block);
+		p = block_to_ptr(block);
+	}
+	return p;
+}
+
+static void control_construct(control_t * control)
+{
+	int i, j;
+
+	control->block_null.next_free = &control->block_null;
+	control->block_null.prev_free = &control->block_null;
+
+	control->fl_bitmap = 0;
+	for (i = 0; i < FL_INDEX_COUNT; ++i)
+	{
+		control->sl_bitmap[i] = 0;
+		for (j = 0; j < SL_INDEX_COUNT; ++j)
+		{
+			control->blocks[i][j] = &control->block_null;
+		}
+	}
+}
+
+static inline void * tlsf_add_pool(void * tlsf, void * mem, size_t bytes)
+{
+	block_header_t * block;
+	block_header_t * next;
+	const size_t pool_overhead = 2 * block_header_overhead;
+	const size_t pool_bytes = align_down(bytes - pool_overhead, ALIGN_SIZE);
+
+	if (((ptrdiff_t)mem % ALIGN_SIZE) != 0)
+		return 0;
+
+	if (pool_bytes < block_size_min || pool_bytes > block_size_max)
+		return 0;
+
+	block = offset_to_block(mem, -(tlsfptr_t)block_header_overhead);
+	block_set_size(block, pool_bytes);
+	block_set_free(block);
+	block_set_prev_used(block);
+	block_insert(tlsf_cast(control_t*, tlsf), block);
+
+	next = block_link_next(block);
+	block_set_size(next, 0);
+	block_set_used(next);
+	block_set_prev_free(next);
+
+	return mem;
+}
+
+static inline void tlsf_remove_pool(void * tlsf, void * pool)
+{
+	control_t * control = tlsf_cast(control_t *, tlsf);
+	block_header_t * block = offset_to_block(pool, -(int)block_header_overhead);
+	int fl = 0, sl = 0;
+
+	tlsf_assert(block_is_free(block) && "block should be free");
+	tlsf_assert(!block_is_free(block_next(block)) && "next block should not be free");
+	tlsf_assert(block_get_size(block_next(block)) == 0 && "next block size should be zero");
+
+	mapping_insert(block_get_size(block), &fl, &sl);
+	remove_free_block(control, block, fl, sl);
+}
+
+static inline void * tlsf_create(void * mem)
+{
+	if (((tlsfptr_t)mem % ALIGN_SIZE) != 0)
+		return 0;
+
+	control_construct(tlsf_cast(control_t *, mem));
+	return tlsf_cast(void *, mem);
+}
+
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
+static inline void * tlsf_create_with_pool(void * mem, size_t bytes)
+{
+	void * tlsf = tlsf_create(mem);
+	tlsf_add_pool(tlsf, (char *)mem + sizeof(control_t), bytes - sizeof(control_t));
+	return tlsf;
+}
+#pragma GCC diagnostic pop
+
+
+static inline void tlsf_destroy(void * tlsf)
+{
+	(void)tlsf;
+}
+
+static inline void * tlsf_get_pool(void * tlsf)
+{
+	return tlsf_cast(void *, (char *)tlsf + sizeof(control_t));
+}
+
+static inline void * tlsf_malloc(void * tlsf, size_t size)
+{
+	control_t * control = tlsf_cast(control_t *, tlsf);
+	const size_t adjust = adjust_request_size(size, ALIGN_SIZE);
+	block_header_t * block = block_locate_free(control, adjust);
+	return block_prepare_used(control, block, adjust);
+}
+
+static inline void * tlsf_memalign(void * tlsf, size_t align, size_t size)
+{
+	control_t * control = tlsf_cast(control_t *, tlsf);
+	const size_t adjust = adjust_request_size(size, ALIGN_SIZE);
+
+	const size_t gap_minimum = sizeof(block_header_t);
+	const size_t size_with_gap = adjust_request_size(adjust + align + gap_minimum, align);
+
+	const size_t aligned_size = (align <= ALIGN_SIZE) ? adjust : size_with_gap;
+
+	block_header_t* block = block_locate_free(control, aligned_size);
+
+	tlsf_assert(sizeof(block_header_t) == block_size_min + block_header_overhead);
+
+	if (block)
+	{
+		void * ptr = block_to_ptr(block);
+		void * aligned = align_ptr(ptr, align);
+		size_t gap = tlsf_cast(size_t, tlsf_cast(tlsfptr_t, aligned) - tlsf_cast(tlsfptr_t, ptr));
+
+		if (gap && gap < gap_minimum)
+		{
+			const size_t gap_remain = gap_minimum - gap;
+			const size_t offset = tlsf_max(gap_remain, align);
+			const void * next_aligned = tlsf_cast(void *, tlsf_cast(tlsfptr_t, aligned) + offset);
+
+			aligned = align_ptr(next_aligned, align);
+			gap = tlsf_cast(size_t, tlsf_cast(tlsfptr_t, aligned) - tlsf_cast(tlsfptr_t, ptr));
+		}
+
+		if (gap)
+		{
+			tlsf_assert(gap >= gap_minimum && "gap size too small");
+			block = block_trim_free_leading(control, block, gap);
+		}
+	}
+
+	return block_prepare_used(control, block, adjust);
+}
+
+static inline void tlsf_free(void * tlsf, void * ptr)
+{
+	if (ptr)
+	{
+		control_t * control = tlsf_cast(control_t *, tlsf);
+		block_header_t * block = block_from_ptr(ptr);
+		tlsf_assert(!block_is_free(block) && "block already marked as free");
+		block_mark_as_free(block);
+		block = block_merge_prev(control, block);
+		block = block_merge_next(control, block);
+		block_insert(control, block);
+	}
+}
+
+static inline void * tlsf_realloc(void * tlsf, void * ptr, size_t size)
+{
+	control_t * control = tlsf_cast(control_t *, tlsf);
+	void * p = 0;
+
+	if (ptr && size == 0)
+	{
+		tlsf_free(tlsf, ptr);
+	}
+	else if (!ptr)
+	{
+		p = tlsf_malloc(tlsf, size);
+	}
+	else
+	{
+		block_header_t * block = block_from_ptr(ptr);
+		block_header_t * next = block_next(block);
+
+		const size_t cursize = block_get_size(block);
+		const size_t combined = cursize + block_get_size(next) + block_header_overhead;
+		const size_t adjust = adjust_request_size(size, ALIGN_SIZE);
+
+		tlsf_assert(!block_is_free(block) && "block already marked as free");
+
+		if (adjust > cursize && (!block_is_free(next) || adjust > combined))
+		{
+			p = tlsf_malloc(tlsf, size);
+			if (p)
+			{
+				const size_t minsize = tlsf_min(cursize, size);
+				memcpy(p, ptr, minsize);
+				tlsf_free(tlsf, ptr);
+			}
+		}
+		else
+		{
+			if (adjust > cursize)
+			{
+				block_merge_next(control, block);
+				block_mark_as_used(block);
+			}
+
+			block_trim_used(control, block, adjust);
+			p = ptr;
+		}
+	}
+
+	return p;
+}
+
+void * mm_create(void * mem, size_t bytes)
+{
+	return tlsf_create_with_pool(mem, bytes);
+}
+
+void mm_destroy(void * mm)
+{
+	tlsf_destroy(mm);
+}
+
+void * mm_get_pool(void * mm)
+{
+	return tlsf_get_pool(mm);
+}
+
+void * mm_add_pool(void * mm, void * mem, size_t bytes)
+{
+	return tlsf_add_pool(mm, mem, bytes);
+}
+
+void mm_remove_pool(void * mm, void * pool)
+{
+	tlsf_remove_pool(mm, pool);
+}
+
+void * mm_malloc(void * mm, size_t size)
+{
+	return tlsf_malloc(mm, size);
+}
+
+void * mm_memalign(void * mm, size_t align, size_t size)
+{
+	return tlsf_memalign(mm, align, size);
+}
+
+void * mm_realloc(void * mm, void * ptr, size_t size)
+{
+	return tlsf_realloc(mm, ptr, size);
+}
+
+void mm_free(void * mm, void * ptr)
+{
+	tlsf_free(mm, ptr);
+}
+
+void * malloc(size_t size)
+{
+	return tlsf_malloc(__heap_pool, size);
+}
+
+void * memalign(size_t align, size_t size)
+{
+	return tlsf_memalign(__heap_pool, align, size);
+}
+
+void * realloc(void * ptr, size_t size)
+{
+	return tlsf_realloc(__heap_pool, ptr, size);
+}
+
+void * calloc(size_t nmemb, size_t size)
+{
+	void * ptr;
+
+	if((ptr = malloc(nmemb * size)))
+		memset(ptr, 0, nmemb * size);
+
+	return ptr;
+}
+
+void free(void * ptr)
+{
+	tlsf_free(__heap_pool, ptr);
+}
+
+void do_init_mem_pool(void)
+{
+#ifndef __SANDBOX__
+	extern unsigned char __heap_start;
+	extern unsigned char __heap_end;
+	__heap_pool = tlsf_create_with_pool((void *)&__heap_start, (size_t)(&__heap_end - &__heap_start));
+#else
+	static char __heap_buf[SZ_16M];
+	__heap_pool = tlsf_create_with_pool((void *)__heap_buf, (size_t)(sizeof(__heap_buf)));
+#endif
+}
diff --git a/hw/mcu/allwinner/f1c100s/lib/memcpy.S b/hw/mcu/allwinner/f1c100s/lib/memcpy.S
new file mode 100644
index 000000000..f7ed3130c
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/lib/memcpy.S
@@ -0,0 +1,404 @@
+/*
+ * memcpy.S
+ */
+	.text
+
+    .global memcpy
+    .type memcpy, %function
+    .align 4
+
+memcpy:
+	/* determine copy direction */
+	cmp		r1, r0
+	bcc		.Lmemcpy_backwards
+
+	moveq	r0, #0					/* quick abort for len=0 */
+	moveq	pc, lr
+
+	stmdb	sp!, {r0, lr}			/* memcpy() returns dest addr */
+	subs	r2, r2, #4
+	blt		.Lmemcpy_fl4			/* less than 4 bytes */
+	ands	r12, r0, #3
+	bne		.Lmemcpy_fdestul		/* oh unaligned destination addr */
+	ands	r12, r1, #3
+	bne		.Lmemcpy_fsrcul			/* oh unaligned source addr */
+
+.Lmemcpy_ft8:
+	/* we have aligned source and destination */
+	subs	r2, r2, #8
+	blt		.Lmemcpy_fl12			/* less than 12 bytes (4 from above) */
+	subs	r2, r2, #0x14         
+	blt		.Lmemcpy_fl32			/* less than 32 bytes (12 from above) */
+	stmdb	sp!, {r4}				/* borrow r4 */
+
+	/* blat 32 bytes at a time */
+.Lmemcpy_floop32:	
+	ldmia	r1!, {r3, r4, r12, lr}
+	stmia	r0!, {r3, r4, r12, lr}
+	ldmia	r1!, {r3, r4, r12, lr}
+	stmia	r0!, {r3, r4, r12, lr}
+	subs	r2, r2, #0x20         
+	bge		.Lmemcpy_floop32
+
+	cmn		r2, #0x10
+	ldmgeia	r1!, {r3, r4, r12, lr}	/* blat a remaining 16 bytes */
+	stmgeia	r0!, {r3, r4, r12, lr}
+	subge	r2, r2, #0x10         
+	ldmia	sp!, {r4}				/* return r4 */
+
+.Lmemcpy_fl32:
+	adds	r2, r2, #0x14         
+
+	/* blat 12 bytes at a time */
+.Lmemcpy_floop12:
+	ldmgeia	r1!, {r3, r12, lr}
+	stmgeia	r0!, {r3, r12, lr}
+	subges	r2, r2, #0x0c         
+	bge		.Lmemcpy_floop12
+
+.Lmemcpy_fl12:
+	adds	r2, r2, #8
+	blt		.Lmemcpy_fl4
+
+	subs	r2, r2, #4
+	ldrlt	r3, [r1], #4
+	strlt	r3, [r0], #4
+	ldmgeia	r1!, {r3, r12}
+	stmgeia	r0!, {r3, r12}
+	subge	r2, r2, #4
+
+.Lmemcpy_fl4:
+	/* less than 4 bytes to go */
+	adds	r2, r2, #4
+	ldmeqia	sp!, {r0, pc}		/* done */
+
+	/* copy the crud byte at a time */
+	cmp		r2, #2
+	ldrb	r3, [r1], #1
+	strb	r3, [r0], #1
+	ldrgeb	r3, [r1], #1
+	strgeb	r3, [r0], #1
+	ldrgtb	r3, [r1], #1
+	strgtb	r3, [r0], #1
+	ldmia	sp!, {r0, pc}
+
+	/* erg - unaligned destination */
+.Lmemcpy_fdestul:
+	rsb		r12, r12, #4
+	cmp		r12, #2
+
+	/* align destination with byte copies */
+	ldrb	r3, [r1], #1
+	strb	r3, [r0], #1
+	ldrgeb	r3, [r1], #1
+	strgeb	r3, [r0], #1
+	ldrgtb	r3, [r1], #1
+	strgtb	r3, [r0], #1
+	subs	r2, r2, r12
+	blt		.Lmemcpy_fl4		/* less the 4 bytes */
+
+	ands	r12, r1, #3
+	beq		.Lmemcpy_ft8		/* we have an aligned source */
+
+	/* erg - unaligned source */
+	/* This is where it gets nasty ... */
+.Lmemcpy_fsrcul:
+	bic		r1, r1, #3
+	ldr		lr, [r1], #4
+	cmp		r12, #2
+	bgt		.Lmemcpy_fsrcul3
+	beq		.Lmemcpy_fsrcul2
+	cmp		r2, #0x0c
+	blt		.Lmemcpy_fsrcul1loop4
+	sub		r2, r2, #0x0c
+	stmdb	sp!, {r4, r5}
+
+.Lmemcpy_fsrcul1loop16:
+	mov		r3, lr, lsr #8
+	ldmia	r1!, {r4, r5, r12, lr}
+	orr		r3, r3, r4, lsl #24
+	mov		r4, r4, lsr #8
+	orr		r4, r4, r5, lsl #24
+	mov		r5, r5, lsr #8
+	orr		r5, r5, r12, lsl #24
+	mov		r12, r12, lsr #8
+	orr		r12, r12, lr, lsl #24
+	stmia	r0!, {r3-r5, r12}
+	subs	r2, r2, #0x10         
+	bge		.Lmemcpy_fsrcul1loop16
+	ldmia	sp!, {r4, r5}
+	adds	r2, r2, #0x0c         
+	blt		.Lmemcpy_fsrcul1l4
+
+.Lmemcpy_fsrcul1loop4:
+	mov		r12, lr, lsr #8
+	ldr		lr, [r1], #4
+	orr		r12, r12, lr, lsl #24
+	str		r12, [r0], #4
+	subs	r2, r2, #4
+	bge		.Lmemcpy_fsrcul1loop4
+
+.Lmemcpy_fsrcul1l4:
+	sub		r1, r1, #3
+	b		.Lmemcpy_fl4
+
+.Lmemcpy_fsrcul2:
+	cmp		r2, #0x0c
+	blt		.Lmemcpy_fsrcul2loop4
+	sub		r2, r2, #0x0c
+	stmdb	sp!, {r4, r5}
+
+.Lmemcpy_fsrcul2loop16:
+	mov		r3, lr, lsr #16
+	ldmia	r1!, {r4, r5, r12, lr}
+	orr		r3, r3, r4, lsl #16
+	mov		r4, r4, lsr #16
+	orr		r4, r4, r5, lsl #16
+	mov		r5, r5, lsr #16
+	orr		r5, r5, r12, lsl #16
+	mov		r12, r12, lsr #16
+	orr		r12, r12, lr, lsl #16
+	stmia	r0!, {r3-r5, r12}
+	subs	r2, r2, #0x10         
+	bge		.Lmemcpy_fsrcul2loop16
+	ldmia	sp!, {r4, r5}
+	adds	r2, r2, #0x0c         
+	blt		.Lmemcpy_fsrcul2l4
+
+.Lmemcpy_fsrcul2loop4:
+	mov		r12, lr, lsr #16
+	ldr		lr, [r1], #4
+	orr		r12, r12, lr, lsl #16
+	str		r12, [r0], #4
+	subs	r2, r2, #4
+	bge		.Lmemcpy_fsrcul2loop4
+
+.Lmemcpy_fsrcul2l4:
+	sub		r1, r1, #2
+	b		.Lmemcpy_fl4
+
+.Lmemcpy_fsrcul3:
+	cmp		r2, #0x0c
+	blt		.Lmemcpy_fsrcul3loop4
+	sub		r2, r2, #0x0c
+	stmdb	sp!, {r4, r5}
+
+.Lmemcpy_fsrcul3loop16:
+	mov		r3, lr, lsr #24
+	ldmia	r1!, {r4, r5, r12, lr}
+	orr		r3, r3, r4, lsl #8
+	mov		r4, r4, lsr #24
+	orr		r4, r4, r5, lsl #8
+	mov		r5, r5, lsr #24
+	orr		r5, r5, r12, lsl #8
+	mov		r12, r12, lsr #24
+	orr		r12, r12, lr, lsl #8
+	stmia	r0!, {r3-r5, r12}
+	subs	r2, r2, #0x10         
+	bge		.Lmemcpy_fsrcul3loop16
+	ldmia	sp!, {r4, r5}
+	adds	r2, r2, #0x0c         
+	blt		.Lmemcpy_fsrcul3l4
+
+.Lmemcpy_fsrcul3loop4:
+	mov		r12, lr, lsr #24
+	ldr		lr, [r1], #4
+	orr		r12, r12, lr, lsl #8
+	str		r12, [r0], #4
+	subs	r2, r2, #4
+	bge		.Lmemcpy_fsrcul3loop4
+
+.Lmemcpy_fsrcul3l4:
+	sub		r1, r1, #1
+	b		.Lmemcpy_fl4
+
+.Lmemcpy_backwards:
+	add		r1, r1, r2
+	add		r0, r0, r2
+	subs	r2, r2, #4
+	blt		.Lmemcpy_bl4		/* less than 4 bytes */
+	ands	r12, r0, #3
+	bne		.Lmemcpy_bdestul	/* oh unaligned destination addr */
+	ands	r12, r1, #3
+	bne		.Lmemcpy_bsrcul		/* oh unaligned source addr */
+
+.Lmemcpy_bt8:
+	/* we have aligned source and destination */
+	subs	r2, r2, #8
+	blt		.Lmemcpy_bl12		/* less than 12 bytes (4 from above) */
+	stmdb	sp!, {r4, lr}
+	subs	r2, r2, #0x14		/* less than 32 bytes (12 from above) */
+	blt		.Lmemcpy_bl32
+
+	/* blat 32 bytes at a time */
+.Lmemcpy_bloop32:
+	ldmdb	r1!, {r3, r4, r12, lr}
+	stmdb	r0!, {r3, r4, r12, lr}
+	ldmdb	r1!, {r3, r4, r12, lr}
+	stmdb	r0!, {r3, r4, r12, lr}
+	subs	r2, r2, #0x20         
+	bge		.Lmemcpy_bloop32
+
+.Lmemcpy_bl32:
+	cmn	r2, #0x10            
+	ldmgedb	r1!, {r3, r4, r12, lr}	/* blat a remaining 16 bytes */
+	stmgedb	r0!, {r3, r4, r12, lr}
+	subge	r2, r2, #0x10         
+	adds	r2, r2, #0x14         
+	ldmgedb	r1!, {r3, r12, lr}		/* blat a remaining 12 bytes */
+	stmgedb	r0!, {r3, r12, lr}
+	subge	r2, r2, #0x0c         
+	ldmia	sp!, {r4, lr}
+
+.Lmemcpy_bl12:
+	adds	r2, r2, #8
+	blt		.Lmemcpy_bl4
+	subs	r2, r2, #4
+	ldrlt	r3, [r1, #-4]!
+	strlt	r3, [r0, #-4]!
+	ldmgedb	r1!, {r3, r12}
+	stmgedb	r0!, {r3, r12}
+	subge	r2, r2, #4
+
+.Lmemcpy_bl4:
+	/* less than 4 bytes to go */
+	adds	r2, r2, #4
+	moveq	pc, lr
+
+	/* copy the crud byte at a time */
+	cmp		r2, #2
+	ldrb	r3, [r1, #-1]!
+	strb	r3, [r0, #-1]!
+	ldrgeb	r3, [r1, #-1]!
+	strgeb	r3, [r0, #-1]!
+	ldrgtb	r3, [r1, #-1]!
+	strgtb	r3, [r0, #-1]!
+	mov		pc, lr
+
+	/* erg - unaligned destination */
+.Lmemcpy_bdestul:
+	cmp		r12, #2
+
+	/* align destination with byte copies */
+	ldrb	r3, [r1, #-1]!
+	strb	r3, [r0, #-1]!
+	ldrgeb	r3, [r1, #-1]!
+	strgeb	r3, [r0, #-1]!
+	ldrgtb	r3, [r1, #-1]!
+	strgtb	r3, [r0, #-1]!
+	subs	r2, r2, r12
+	blt		.Lmemcpy_bl4		/* less than 4 bytes to go */
+	ands	r12, r1, #3
+	beq		.Lmemcpy_bt8		/* we have an aligned source */
+
+	/* erg - unaligned source */
+	/* This is where it gets nasty ... */
+.Lmemcpy_bsrcul:
+	bic		r1, r1, #3
+	ldr		r3, [r1, #0]
+	cmp		r12, #2
+	blt		.Lmemcpy_bsrcul1
+	beq		.Lmemcpy_bsrcul2
+	cmp		r2, #0x0c
+	blt		.Lmemcpy_bsrcul3loop4
+	sub		r2, r2, #0x0c
+	stmdb	sp!, {r4, r5, lr}
+
+.Lmemcpy_bsrcul3loop16:
+	mov		lr, r3, lsl #8
+	ldmdb	r1!, {r3-r5, r12}
+	orr		lr, lr, r12, lsr #24
+	mov		r12, r12, lsl #8
+	orr		r12, r12, r5, lsr #24
+	mov		r5, r5, lsl #8
+	orr		r5, r5, r4, lsr #24
+	mov		r4, r4, lsl #8
+	orr		r4, r4, r3, lsr #24
+	stmdb	r0!, {r4, r5, r12, lr}
+	subs	r2, r2, #0x10         
+	bge		.Lmemcpy_bsrcul3loop16
+	ldmia	sp!, {r4, r5, lr}
+	adds	r2, r2, #0x0c         
+	blt		.Lmemcpy_bsrcul3l4
+
+.Lmemcpy_bsrcul3loop4:
+	mov		r12, r3, lsl #8
+	ldr		r3, [r1, #-4]!
+	orr		r12, r12, r3, lsr #24
+	str		r12, [r0, #-4]!
+	subs	r2, r2, #4
+	bge		.Lmemcpy_bsrcul3loop4
+
+.Lmemcpy_bsrcul3l4:
+	add		r1, r1, #3
+	b		.Lmemcpy_bl4
+
+.Lmemcpy_bsrcul2:
+	cmp		r2, #0x0c
+	blt		.Lmemcpy_bsrcul2loop4
+	sub		r2, r2, #0x0c
+	stmdb	sp!, {r4, r5, lr}
+
+.Lmemcpy_bsrcul2loop16:
+	mov		lr, r3, lsl #16
+	ldmdb	r1!, {r3-r5, r12}
+	orr		lr, lr, r12, lsr #16
+	mov		r12, r12, lsl #16
+	orr		r12, r12, r5, lsr #16
+	mov		r5, r5, lsl #16
+	orr		r5, r5, r4, lsr #16
+	mov		r4, r4, lsl #16
+	orr		r4, r4, r3, lsr #16
+	stmdb	r0!, {r4, r5, r12, lr}
+	subs	r2, r2, #0x10         
+	bge		.Lmemcpy_bsrcul2loop16
+	ldmia	sp!, {r4, r5, lr}
+	adds	r2, r2, #0x0c         
+	blt		.Lmemcpy_bsrcul2l4
+
+.Lmemcpy_bsrcul2loop4:
+	mov		r12, r3, lsl #16
+	ldr		r3, [r1, #-4]!
+	orr		r12, r12, r3, lsr #16
+	str		r12, [r0, #-4]!
+	subs	r2, r2, #4
+	bge		.Lmemcpy_bsrcul2loop4
+
+.Lmemcpy_bsrcul2l4:
+	add		r1, r1, #2
+	b		.Lmemcpy_bl4
+
+.Lmemcpy_bsrcul1:
+	cmp		r2, #0x0c
+	blt		.Lmemcpy_bsrcul1loop4
+	sub		r2, r2, #0x0c
+	stmdb	sp!, {r4, r5, lr}
+
+.Lmemcpy_bsrcul1loop32:
+	mov		lr, r3, lsl #24
+	ldmdb	r1!, {r3-r5, r12}
+	orr		lr, lr, r12, lsr #8
+	mov		r12, r12, lsl #24
+	orr		r12, r12, r5, lsr #8
+	mov		r5, r5, lsl #24
+	orr		r5, r5, r4, lsr #8
+	mov		r4, r4, lsl #24
+	orr		r4, r4, r3, lsr #8
+	stmdb	r0!, {r4, r5, r12, lr}
+	subs	r2, r2, #0x10         
+	bge		.Lmemcpy_bsrcul1loop32
+	ldmia	sp!, {r4, r5, lr}
+	adds	r2, r2, #0x0c         
+	blt		.Lmemcpy_bsrcul1l4
+
+.Lmemcpy_bsrcul1loop4:
+	mov		r12, r3, lsl #24
+	ldr		r3, [r1, #-4]!
+	orr		r12, r12, r3, lsr #8
+	str		r12, [r0, #-4]!
+	subs	r2, r2, #4
+	bge		.Lmemcpy_bsrcul1loop4
+
+.Lmemcpy_bsrcul1l4:
+	add		r1, r1, #1
+	b		.Lmemcpy_bl4
diff --git a/hw/mcu/allwinner/f1c100s/lib/memset.S b/hw/mcu/allwinner/f1c100s/lib/memset.S
new file mode 100644
index 000000000..3eea2db1e
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/lib/memset.S
@@ -0,0 +1,79 @@
+/*
+ * memcpy.S
+ */
+	.text
+
+    .global memset
+    .type memset, %function
+    .align 4
+
+memset:
+	stmfd	sp!, {r0}				/* remember address for return value */
+	and		r1, r1, #0x000000ff		/* we write bytes */
+
+	cmp		r2, #0x00000004			/* do we have less than 4 bytes */
+	blt		.Lmemset_lessthanfour
+
+	/* first we will word align the address */
+	ands	r3, r0, #0x00000003		/* get the bottom two bits */
+	beq		.Lmemset_addraligned	/* the address is word aligned */
+
+	rsb		r3, r3, #0x00000004
+	sub		r2, r2, r3
+	cmp		r3, #0x00000002
+	strb	r1, [r0], #0x0001		/* set 1 byte */
+	strgeb	r1, [r0], #0x0001		/* set another byte */
+	strgtb	r1, [r0], #0x0001		/* and a third */
+
+	cmp		r2, #0x00000004
+	blt		.Lmemset_lessthanfour
+
+	/* now we must be word aligned */
+.Lmemset_addraligned:
+	orr		r3, r1, r1, lsl #8		/* repeat the byte into a word */
+	orr		r3, r3, r3, lsl #16
+
+	/* we know we have at least 4 bytes ... */
+	cmp		r2, #0x00000020			/* if less than 32 then use words */
+	blt		.Lmemset_lessthan32
+
+	/* we have at least 32 so lets use quad words */
+	stmfd	sp!, {r4-r6}			/* store registers */
+	mov		r4, r3					/* duplicate data */
+	mov		r5, r3
+	mov		r6, r3
+
+.Lmemset_loop16:
+	stmia	r0!, {r3-r6}			/* store 16 bytes */
+	sub		r2, r2, #0x00000010		/* adjust count */
+	cmp		r2, #0x00000010			/* still got at least 16 bytes ? */
+	bgt		.Lmemset_loop16
+
+	ldmfd	sp!, {r4-r6}			/* restore registers */
+
+	/* do we need to set some words as well ? */
+	cmp		r2, #0x00000004
+	blt		.Lmemset_lessthanfour
+
+	/* have either less than 16 or less than 32 depending on route taken */
+.Lmemset_lessthan32:
+
+	/* we have at least 4 bytes so copy as words */
+.Lmemset_loop4:
+	str		r3, [r0], #0x0004
+	sub		r2, r2, #0x0004
+	cmp		r2, #0x00000004
+	bge		.Lmemset_loop4
+
+.Lmemset_lessthanfour:
+	cmp		r2, #0x00000000
+	ldmeqfd	sp!, {r0}
+	moveq	pc, lr					/* zero length so exit */
+
+	cmp		r2, #0x00000002
+	strb	r1, [r0], #0x0001		/* set 1 byte */
+	strgeb	r1, [r0], #0x0001		/* set another byte */
+	strgtb	r1, [r0], #0x0001		/* and a third */
+
+	ldmfd	sp!, {r0}
+	mov		pc, lr					/* exit */
diff --git a/hw/mcu/allwinner/f1c100s/lib/printf.c b/hw/mcu/allwinner/f1c100s/lib/printf.c
new file mode 100644
index 000000000..366bb9c0b
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/lib/printf.c
@@ -0,0 +1,757 @@
+
+///////////////////////////////////////////////////////////////////////////////
+// \author (c) Marco Paland (info@paland.com)
+//             2014-2018, PALANDesign Hannover, Germany
+//
+// \license The MIT License (MIT)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+// 
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+// 
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on
+//        embedded systems with a very limited resources. These routines are thread
+//        safe and reentrant!
+//        Use this instead of the bloated standard/newlib printf cause these use
+//        malloc for printf (and may not be thread safe).
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#include <stdint.h>
+#include "printf.h"
+
+
+// ntoa conversion buffer size, this must be big enough to hold
+// one converted numeric number including padded zeros (dynamically created on stack)
+// 32 byte is a good default
+#define PRINTF_NTOA_BUFFER_SIZE    32U
+
+// ftoa conversion buffer size, this must be big enough to hold
+// one converted float number including padded zeros (dynamically created on stack)
+// 32 byte is a good default
+#define PRINTF_FTOA_BUFFER_SIZE    32U
+
+// define this to support floating point (%f)
+#define PRINTF_SUPPORT_FLOAT
+
+// define this to support long long types (%llu or %p)
+#define PRINTF_SUPPORT_LONG_LONG
+
+// define this to support the ptrdiff_t type (%t)
+// ptrdiff_t is normally defined in <stddef.h> as long or long long type
+#define PRINTF_SUPPORT_PTRDIFF_T
+
+
+///////////////////////////////////////////////////////////////////////////////
+
+// internal flag definitions
+#define FLAGS_ZEROPAD   (1U <<  0U)
+#define FLAGS_LEFT      (1U <<  1U)
+#define FLAGS_PLUS      (1U <<  2U)
+#define FLAGS_SPACE     (1U <<  3U)
+#define FLAGS_HASH      (1U <<  4U)
+#define FLAGS_UPPERCASE (1U <<  5U)
+#define FLAGS_CHAR      (1U <<  6U)
+#define FLAGS_SHORT     (1U <<  7U)
+#define FLAGS_LONG      (1U <<  8U)
+#define FLAGS_LONG_LONG (1U <<  9U)
+#define FLAGS_PRECISION (1U << 10U)
+
+typedef unsigned char bool;
+#ifndef false
+#define false 0
+#endif
+#ifndef true
+#define true (!false)
+#endif
+extern void sys_uart_putc(char c);
+static char last_ch;
+void _putchar(char character)
+{
+	if(character == 0x0a && last_ch != 0x0d)
+	{
+		sys_uart_putc(0x0d);
+	}
+	sys_uart_putc(character);
+
+}
+
+// output function type
+typedef void (*out_fct_type)(char character, void* buffer, size_t idx, size_t maxlen);
+
+
+// wrapper (used as buffer) for output function type
+typedef struct {
+  void  (*fct)(char character, void* arg);
+  void* arg;
+} out_fct_wrap_type;
+
+
+// internal buffer output
+static inline void _out_buffer(char character, void* buffer, size_t idx, size_t maxlen)
+{
+  if (idx < maxlen) {
+    ((char*)buffer)[idx] = character;
+  }
+}
+
+
+// internal null output
+static inline void _out_null(char character, void* buffer, size_t idx, size_t maxlen)
+{
+  (void)character; (void)buffer; (void)idx; (void)maxlen;
+}
+
+
+// internal _putchar wrapper
+static inline void _out_char(char character, void* buffer, size_t idx, size_t maxlen)
+{
+  (void)buffer; (void)idx; (void)maxlen;
+  if (character) {
+    _putchar(character);
+  }
+}
+
+
+// internal output function wrapper
+static inline void _out_fct(char character, void* buffer, size_t idx, size_t maxlen)
+{
+  (void)idx; (void)maxlen;
+  // buffer is the output fct pointer
+  ((out_fct_wrap_type*)buffer)->fct(character, ((out_fct_wrap_type*)buffer)->arg);
+}
+
+
+// internal strlen
+// \return The length of the string (excluding the terminating 0)
+static inline unsigned int _strlen(const char* str)
+{
+  const char* s;
+  for (s = str; *s; ++s);
+  return (unsigned int)(s - str);
+}
+
+
+// internal test if char is a digit (0-9)
+// \return true if char is a digit
+static inline bool _is_digit(char ch)
+{
+  return (ch >= '0') && (ch <= '9');
+}
+
+
+// internal ASCII string to unsigned int conversion
+static unsigned int _atoi(const char** str)
+{
+  unsigned int i = 0U;
+  while (_is_digit(**str)) {
+    i = i * 10U + (unsigned int)(*((*str)++) - '0');
+  }
+  return i;
+}
+
+
+// internal itoa format
+static size_t _ntoa_format(out_fct_type out, char* buffer, size_t idx, size_t maxlen, char* buf, size_t len, bool negative, unsigned int base, unsigned int prec, unsigned int width, unsigned int flags)
+{
+  const size_t start_idx = idx;
+
+  // pad leading zeros
+  while (!(flags & FLAGS_LEFT) && (len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+    buf[len++] = '0';
+  }
+  while (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+    buf[len++] = '0';
+  }
+
+  // handle hash
+  if (flags & FLAGS_HASH) {
+    if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) {
+      len--;
+      if (len && (base == 16U)) {
+        len--;
+      }
+    }
+    if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+      buf[len++] = 'x';
+    }
+    else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+      buf[len++] = 'X';
+    }
+    else if ((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+      buf[len++] = 'b';
+    }
+    if (len < PRINTF_NTOA_BUFFER_SIZE) {
+      buf[len++] = '0';
+    }
+  }
+
+  // handle sign
+  if (len && (len == width) && (negative || (flags & FLAGS_PLUS) || (flags & FLAGS_SPACE))) {
+    len--;
+  }
+  if (len < PRINTF_NTOA_BUFFER_SIZE) {
+    if (negative) {
+      buf[len++] = '-';
+    }
+    else if (flags & FLAGS_PLUS) {
+      buf[len++] = '+';  // ignore the space if the '+' exists
+    }
+    else if (flags & FLAGS_SPACE) {
+      buf[len++] = ' ';
+    }
+  }
+
+  // pad spaces up to given width
+  if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) {
+    for (size_t i = len; i < width; i++) {
+      out(' ', buffer, idx++, maxlen);
+    }
+  }
+
+  // reverse string
+  for (size_t i = 0U; i < len; i++) {
+    out(buf[len - i - 1U], buffer, idx++, maxlen);
+  }
+
+  // append pad spaces up to given width
+  if (flags & FLAGS_LEFT) {
+    while (idx - start_idx < width) {
+      out(' ', buffer, idx++, maxlen);
+    }
+  }
+
+  return idx;
+}
+
+
+// internal itoa for 'long' type
+static size_t _ntoa_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, unsigned long base, unsigned int prec, unsigned int width, unsigned int flags)
+{
+  char buf[PRINTF_NTOA_BUFFER_SIZE];
+  size_t len = 0U;
+
+  // no hash for 0 values
+  if (!value) {
+    flags &= ~FLAGS_HASH;
+  }
+
+  // write if precision != 0 and value is != 0
+  if (!(flags & FLAGS_PRECISION) || value) {
+    do {
+      const char digit = (char)(value % base);
+      buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;
+      value /= base;
+    } while (value && (len < PRINTF_NTOA_BUFFER_SIZE));
+  }
+
+  return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags);
+}
+
+
+// internal itoa for 'long long' type
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+static size_t _ntoa_long_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long long value, bool negative, unsigned long long base, unsigned int prec, unsigned int width, unsigned int flags)
+{
+  char buf[PRINTF_NTOA_BUFFER_SIZE];
+  size_t len = 0U;
+
+  // no hash for 0 values
+  if (!value) {
+    flags &= ~FLAGS_HASH;
+  }
+
+  // write if precision != 0 and value is != 0
+  if (!(flags & FLAGS_PRECISION) || value) {
+    do {
+      const char digit = (char)(value % base);
+      buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;
+      value /= base;
+    } while (value && (len < PRINTF_NTOA_BUFFER_SIZE));
+  }
+
+  return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags);
+}
+#endif  // PRINTF_SUPPORT_LONG_LONG
+
+
+#if defined(PRINTF_SUPPORT_FLOAT)
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wfloat-equal"
+
+static size_t _ftoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags)
+{
+  const size_t start_idx = idx;
+
+  char buf[PRINTF_FTOA_BUFFER_SIZE];
+  size_t len  = 0U;
+  double diff = 0.0;
+
+  // if input is larger than thres_max, revert to exponential
+  const double thres_max = (double)0x7FFFFFFF;
+
+  // powers of 10
+  static const double pow10[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000 };
+
+  // test for negative
+  bool negative = false;
+  if (value < 0) {
+    negative = true;
+    value = 0 - value;
+  }
+
+  // set default precision to 6, if not set explicitly
+  if (!(flags & FLAGS_PRECISION)) {
+    prec = 6U;
+  }
+  // limit precision to 9, cause a prec >= 10 can lead to overflow errors
+  while ((len < PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) {
+    buf[len++] = '0';
+    prec--;
+  }
+
+  int whole = (int)value;
+  double tmp = (value - whole) * pow10[prec];
+  unsigned long frac = (unsigned long)tmp;
+  diff = tmp - frac;
+
+  if (diff > 0.5l) {
+    ++frac;
+    // handle rollover, e.g. case 0.99 with prec 1 is 1.0
+    if (frac >= pow10[prec]) {
+      frac = 0;
+      ++whole;
+    }
+  }
+  else if ((diff == 0.5l) && ((frac == 0U) || (frac & 1U))) {
+    // if halfway, round up if odd, OR if last digit is 0
+    ++frac;
+  }
+
+  // TBD: for very large numbers switch back to native sprintf for exponentials. Anyone want to write code to replace this?
+  // Normal printf behavior is to print EVERY whole number digit which can be 100s of characters overflowing your buffers == bad
+  if (value > thres_max) {
+    return 0U;
+  }
+
+  if (prec == 0U) {
+    diff = value - (double)whole;
+    if (diff > 0.5l) {
+      // greater than 0.5, round up, e.g. 1.6 -> 2
+      ++whole;
+    }
+    else if ((diff == 0.5l) && (whole & 1)) {
+      // exactly 0.5 and ODD, then round up
+      // 1.5 -> 2, but 2.5 -> 2
+      ++whole;
+    }
+  }
+  else {
+    unsigned int count = prec;
+    // now do fractional part, as an unsigned number
+    while (len < PRINTF_FTOA_BUFFER_SIZE) {
+      --count;
+      buf[len++] = (char)(48U + (frac % 10U));
+      if (!(frac /= 10U)) {
+        break;
+      }
+    }
+    // add extra 0s
+    while ((len < PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) {
+      buf[len++] = '0';
+    }
+    if (len < PRINTF_FTOA_BUFFER_SIZE) {
+      // add decimal
+      buf[len++] = '.';
+    }
+  }
+
+  // do whole part, number is reversed
+  while (len < PRINTF_FTOA_BUFFER_SIZE) {
+    buf[len++] = (char)(48 + (whole % 10));
+    if (!(whole /= 10)) {
+      break;
+    }
+  }
+
+  // pad leading zeros
+  while (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_FTOA_BUFFER_SIZE)) {
+    buf[len++] = '0';
+  }
+
+  // handle sign
+  if ((len == width) && (negative || (flags & FLAGS_PLUS) || (flags & FLAGS_SPACE))) {
+    len--;
+  }
+  if (len < PRINTF_FTOA_BUFFER_SIZE) {
+    if (negative) {
+      buf[len++] = '-';
+    }
+    else if (flags & FLAGS_PLUS) {
+      buf[len++] = '+';  // ignore the space if the '+' exists
+    }
+    else if (flags & FLAGS_SPACE) {
+      buf[len++] = ' ';
+    }
+  }
+
+  // pad spaces up to given width
+  if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) {
+    for (size_t i = len; i < width; i++) {
+      out(' ', buffer, idx++, maxlen);
+    }
+  }
+
+  // reverse string
+  for (size_t i = 0U; i < len; i++) {
+    out(buf[len - i - 1U], buffer, idx++, maxlen);
+  }
+
+  // append pad spaces up to given width
+  if (flags & FLAGS_LEFT) {
+    while (idx - start_idx < width) {
+      out(' ', buffer, idx++, maxlen);
+    }
+  }
+
+  return idx;
+}
+#pragma GCC diagnostic pop
+#endif  // PRINTF_SUPPORT_FLOAT
+
+
+// internal vsnprintf
+static int _vsnprintf(out_fct_type out, char* buffer, const size_t maxlen, const char* format, va_list va)
+{
+  unsigned int flags, width, precision, n;
+  size_t idx = 0U;
+
+  if (!buffer) {
+    // use null output function
+    out = _out_null;
+  }
+
+  while (*format)
+  {
+    // format specifier?  %[flags][width][.precision][length]
+    if (*format != '%') {
+      // no
+      out(*format, buffer, idx++, maxlen);
+      format++;
+      continue;
+    }
+    else {
+      // yes, evaluate it
+      format++;
+    }
+
+    // evaluate flags
+    flags = 0U;
+    do {
+      switch (*format) {
+        case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break;
+        case '-': flags |= FLAGS_LEFT;    format++; n = 1U; break;
+        case '+': flags |= FLAGS_PLUS;    format++; n = 1U; break;
+        case ' ': flags |= FLAGS_SPACE;   format++; n = 1U; break;
+        case '#': flags |= FLAGS_HASH;    format++; n = 1U; break;
+        default :                                   n = 0U; break;
+      }
+    } while (n);
+
+    // evaluate width field
+    width = 0U;
+    if (_is_digit(*format)) {
+      width = _atoi(&format);
+    }
+    else if (*format == '*') {
+      const int w = va_arg(va, int);
+      if (w < 0) {
+        flags |= FLAGS_LEFT;    // reverse padding
+        width = (unsigned int)-w;
+      }
+      else {
+        width = (unsigned int)w;
+      }
+      format++;
+    }
+
+    // evaluate precision field
+    precision = 0U;
+    if (*format == '.') {
+      flags |= FLAGS_PRECISION;
+      format++;
+      if (_is_digit(*format)) {
+        precision = _atoi(&format);
+      }
+      else if (*format == '*') {
+        const int prec = (int)va_arg(va, int);
+        precision = prec > 0 ? (unsigned int)prec : 0U;
+        format++;
+      }
+    }
+
+    // evaluate length field
+    switch (*format) {
+      case 'l' :
+        flags |= FLAGS_LONG;
+        format++;
+        if (*format == 'l') {
+          flags |= FLAGS_LONG_LONG;
+          format++;
+        }
+        break;
+      case 'h' :
+        flags |= FLAGS_SHORT;
+        format++;
+        if (*format == 'h') {
+          flags |= FLAGS_CHAR;
+          format++;
+        }
+        break;
+#if defined(PRINTF_SUPPORT_PTRDIFF_T)
+      case 't' :
+        flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+        format++;
+        break;
+#endif
+      case 'j' :
+        flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+        format++;
+        break;
+      case 'z' :
+        flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+        format++;
+        break;
+      default :
+        break;
+    }
+
+    // evaluate specifier
+    switch (*format) {
+      case 'd' :
+      case 'i' :
+      case 'u' :
+      case 'x' :
+      case 'X' :
+      case 'o' :
+      case 'b' : {
+        // set the base
+        unsigned int base;
+        if (*format == 'x' || *format == 'X') {
+          base = 16U;
+        }
+        else if (*format == 'o') {
+          base =  8U;
+        }
+        else if (*format == 'b') {
+          base =  2U;
+        }
+        else {
+          base = 10U;
+          flags &= ~FLAGS_HASH;   // no hash for dec format
+        }
+        // uppercase
+        if (*format == 'X') {
+          flags |= FLAGS_UPPERCASE;
+        }
+
+        // no plus or space flag for u, x, X, o, b
+        if ((*format != 'i') && (*format != 'd')) {
+          flags &= ~(FLAGS_PLUS | FLAGS_SPACE);
+        }
+
+        // ignore '0' flag when precision is given
+        if (flags & FLAGS_PRECISION) {
+          flags &= ~FLAGS_ZEROPAD;
+        }
+
+        // convert the integer
+        if ((*format == 'i') || (*format == 'd')) {
+          // signed
+          if (flags & FLAGS_LONG_LONG) {
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+            const long long value = va_arg(va, long long);
+            idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
+#endif
+          }
+          else if (flags & FLAGS_LONG) {
+            const long value = va_arg(va, long);
+            idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
+          }
+          else {
+            const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) : (flags & FLAGS_SHORT) ? (short int)va_arg(va, int) : va_arg(va, int);
+            idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
+          }
+        }
+        else {
+          // unsigned
+          if (flags & FLAGS_LONG_LONG) {
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+            idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, precision, width, flags);
+#endif
+          }
+          else if (flags & FLAGS_LONG) {
+            idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags);
+          }
+          else {
+            const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char)va_arg(va, unsigned int) : (flags & FLAGS_SHORT) ? (unsigned short int)va_arg(va, unsigned int) : va_arg(va, unsigned int);
+            idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags);
+          }
+        }
+        format++;
+        break;
+      }
+#if defined(PRINTF_SUPPORT_FLOAT)
+      case 'f' :
+      case 'F' :
+        idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags);
+        format++;
+        break;
+#endif  // PRINTF_SUPPORT_FLOAT
+      case 'c' : {
+        unsigned int l = 1U;
+        // pre padding
+        if (!(flags & FLAGS_LEFT)) {
+          while (l++ < width) {
+            out(' ', buffer, idx++, maxlen);
+          }
+        }
+        // char output
+        out((char)va_arg(va, int), buffer, idx++, maxlen);
+        // post padding
+        if (flags & FLAGS_LEFT) {
+          while (l++ < width) {
+            out(' ', buffer, idx++, maxlen);
+          }
+        }
+        format++;
+        break;
+      }
+
+      case 's' : {
+        char* p = va_arg(va, char*);
+        unsigned int l = _strlen(p);
+        // pre padding
+        if (flags & FLAGS_PRECISION) {
+          l = (l < precision ? l : precision);
+        }
+        if (!(flags & FLAGS_LEFT)) {
+          while (l++ < width) {
+            out(' ', buffer, idx++, maxlen);
+          }
+        }
+        // string output
+        while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) {
+          out(*(p++), buffer, idx++, maxlen);
+        }
+        // post padding
+        if (flags & FLAGS_LEFT) {
+          while (l++ < width) {
+            out(' ', buffer, idx++, maxlen);
+          }
+        }
+        format++;
+        break;
+      }
+
+      case 'p' : {
+        width = sizeof(void*) * 2U;
+        flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE;
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+        const bool is_ll = sizeof(uintptr_t) == sizeof(long long);
+        if (is_ll) {
+          idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t)va_arg(va, void*), false, 16U, precision, width, flags);
+        }
+        else {
+#endif
+          idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)((uintptr_t)va_arg(va, void*)), false, 16U, precision, width, flags);
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+        }
+#endif
+        format++;
+        break;
+      }
+
+      case '%' :
+        out('%', buffer, idx++, maxlen);
+        format++;
+        break;
+
+      default :
+        out(*format, buffer, idx++, maxlen);
+        format++;
+        break;
+    }
+  }
+
+  // termination
+  out((char)0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen);
+
+  // return written chars without terminating \0
+  return (int)idx;
+}
+
+
+///////////////////////////////////////////////////////////////////////////////
+
+
+int printf(const char* format, ...)
+{
+  va_list va;
+  va_start(va, format);
+  char buffer[1];
+  const int ret = _vsnprintf(_out_char, buffer, (size_t)-1, format, va);
+  va_end(va);
+  return ret;
+}
+
+
+int sprintf(char* buffer, const char* format, ...)
+{
+  va_list va;
+  va_start(va, format);
+  const int ret = _vsnprintf(_out_buffer, buffer, (size_t)-1, format, va);
+  va_end(va);
+  return ret;
+}
+
+
+int snprintf(char* buffer, size_t count, const char* format, ...)
+{
+  va_list va;
+  va_start(va, format);
+  const int ret = _vsnprintf(_out_buffer, buffer, count, format, va);
+  va_end(va);
+  return ret;
+}
+
+
+int vsnprintf(char* buffer, size_t count, const char* format, va_list va)
+{
+  return _vsnprintf(_out_buffer, buffer, count, format, va);
+}
+
+
+int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...)
+{
+  va_list va;
+  va_start(va, format);
+  out_fct_wrap_type out_fct_wrap = { out, arg };
+  const int ret = _vsnprintf(_out_fct, (char*)&out_fct_wrap, (size_t)-1, format, va);
+  va_end(va);
+  return ret;
+}
diff --git a/hw/mcu/allwinner/f1c100s/machine/exception.c b/hw/mcu/allwinner/f1c100s/machine/exception.c
new file mode 100644
index 000000000..ffc61bf47
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/machine/exception.c
@@ -0,0 +1,76 @@
+/*
+ * exception.c
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ * Official site: http://xboot.org
+ * Mobile phone: +86-18665388956
+ * QQ: 8192542
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <stdio.h>
+#include <arm32.h>
+#include <string.h>
+
+static void show_regs(struct arm_regs_t * regs)
+{
+	int i;
+
+	printf("pc : [<%08lx>] lr : [<%08lx>] cpsr: %08lx\r\n", regs->pc, regs->lr, regs->cpsr);
+	printf("sp : %08lx\r\n", regs->sp);
+	for(i = 12; i >= 0; i--)
+	{
+        printf("r%-2d: %08lx ", i, regs->r[i]);
+	 	if(i % 2 == 0)
+	 		printf("\r\n");
+	 }
+    printf("\r\n");
+}
+
+void arm32_do_undefined_instruction(struct arm_regs_t * regs)
+{
+	//gdbserver_handle_exception(regs);
+}
+
+void arm32_do_software_interrupt(struct arm_regs_t * regs)
+{
+	show_regs(regs);
+	regs->pc += 4;
+}
+
+void arm32_do_prefetch_abort(struct arm_regs_t * regs)
+{
+	show_regs(regs);
+	regs->pc += 4;
+}
+
+void arm32_do_data_abort(struct arm_regs_t * regs)
+{
+	show_regs(regs);
+	regs->pc += 4;
+}
+
+_Noreturn void __fatal_error(const char *msg) {
+    printf("%s\n", msg);
+    while (1);
+}
+
+#ifndef NDEBUG
+_Noreturn void __assert_func(const char *file, int line, const char *func, const char *expr) {
+    //printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line);
+    __fatal_error("Assertion failed");
+}
+#endif
\ No newline at end of file
diff --git a/hw/mcu/allwinner/f1c100s/machine/f1c100s-intc.c b/hw/mcu/allwinner/f1c100s/machine/f1c100s-intc.c
new file mode 100644
index 000000000..2993f0b60
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/machine/f1c100s-intc.c
@@ -0,0 +1,173 @@
+// Originally designed by Hong Xuyao
+
+#include <stdint.h>
+#include <stdio.h>
+#include <f1c100s-irq.h>
+#include <arm32.h>
+
+#define __irq  __attribute__ ((interrupt ("IRQ")))
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+typedef struct {
+  __IO uint32_t INTC_VECTOR_REG;    // 0x00
+  __IO uint32_t INTC_BASE_ADDR_REG; // 0x04
+  uint32_t resv1[1];                // 0x08
+  __IO uint32_t NMI_INT_CTRL_REG;   // 0x0c
+  __IO uint32_t INTC_PEND_REG[2];   // 0x10
+  uint32_t resv2[2];                // 0x18
+  __IO uint32_t INTC_EN_REG[2];     // 0x20
+  uint32_t resv3[2];                // 0x28
+  __IO uint32_t INTC_MASK_REG[2];   // 0x30
+  uint32_t resv4[2];                // 0x38
+  __IO uint32_t INTC_RESP_REG[2];   // 0x40
+  uint32_t resv5[2];                // 0x48
+  __IO uint32_t INTC_FF_REG[2];     // 0x50
+  uint32_t resv6[2];                // 0x58
+  __IO uint32_t INTC_PRIO_REG[4];   // 0x60
+} INTC_TypeDef;
+
+#ifndef COUNTOF
+#define COUNTOF(ar) (sizeof(ar)/sizeof(ar[0]))
+#endif
+
+#define INTC  ((INTC_TypeDef*)0x01C20400)
+
+static IRQHandleTypeDef irq_table[64] __attribute__((used, aligned(32)));
+
+void arm32_do_irq(struct arm_regs_t * regs)
+{
+  uint8_t nIRQ = f1c100s_intc_get_nirq();
+
+  // ForceIRQ flag must be cleared by ISR
+  // Otherwise ISR will be entered repeatedly
+  INTC->INTC_FF_REG[nIRQ / 32] &= ~(1 << nIRQ);
+  // Call the drivers ISR
+  f1c100s_intc_dispatch(nIRQ);
+  // Clear pending at the end of ISR
+  f1c100s_intc_clear_pend(nIRQ);
+}
+
+void arm32_do_fiq(struct arm_regs_t * regs)
+{
+  // Call the drivers ISR
+  f1c100s_intc_dispatch(0);
+  // Clear pending at the end of ISR.
+  f1c100s_intc_clear_pend(0);
+}
+
+/*
+* Read active IRQ number
+* @return: none
+*/
+uint8_t f1c100s_intc_get_nirq(void)
+{
+  return ((INTC->INTC_VECTOR_REG >> 2) & 0x3F);
+}
+
+/*
+* Execute ISR corresponding to IRQ number
+* @nIRQ: IRQ number
+* @return: none
+*/
+void f1c100s_intc_dispatch(uint8_t nIRQ)
+{
+  IRQHandleTypeDef handle = irq_table[nIRQ];
+  if (handle)
+    handle();
+}
+
+/*
+* Set handler function for specified IRQ
+* @nIRQ: IRQ number
+* @handle: Handle function
+* @return: none
+*/
+void f1c100s_intc_set_isr(uint8_t nIRQ, IRQHandleTypeDef handle)
+{
+  if (nIRQ < COUNTOF(irq_table)) {
+    irq_table[nIRQ] = handle;
+  }
+}
+
+/*
+* Enable IRQ
+* @nIRQ: IRQ number
+* @return: none
+*/
+void f1c100s_intc_enable_irq(uint8_t nIRQ)
+{
+  INTC->INTC_EN_REG[nIRQ / 32] |= (1 << (nIRQ % 32));
+}
+
+/*
+* Disable IRQ
+* @nIRQ: IRQ number
+* @return: none
+*/
+void f1c100s_intc_disable_irq(uint8_t nIRQ)
+{
+  INTC->INTC_EN_REG[nIRQ / 32] &= ~(1 << (nIRQ % 32));
+}
+
+/*
+* Mask IRQ
+* @nIRQ: IRQ number
+* @return: none
+*/
+void f1c100s_intc_mask_irq(uint8_t nIRQ)
+{
+  INTC->INTC_MASK_REG[nIRQ / 32] |= (1 << (nIRQ % 32));
+}
+
+/*
+* Unmask IRQ
+* @nIRQ: IRQ number
+* @return: none
+*/
+void f1c100s_intc_unmask_irq(uint8_t nIRQ)
+{
+  INTC->INTC_MASK_REG[nIRQ / 32] &= ~(1 << (nIRQ % 32));
+}
+
+/*
+* Immediately trigger IRQ
+* @nIRQ: IRQ number
+* @return: none
+*/
+void f1c100s_intc_force_irq(uint8_t nIRQ)
+{
+  // This bit is to be cleared in IRQ handler
+  INTC->INTC_FF_REG[nIRQ / 32] = (1 << (nIRQ % 32));
+}
+
+/*
+* Clear pending flag
+* @nIRQ: IRQ number
+* @return: none
+*/
+void f1c100s_intc_clear_pend(uint8_t nIRQ)
+{
+  INTC->INTC_PEND_REG[nIRQ / 32] = (1 << (nIRQ % 32));
+}
+
+
+/*
+* Initialize IRQ module
+* @return: none
+*/
+void f1c100s_intc_init(void)
+{
+  INTC->INTC_EN_REG[0] = INTC->INTC_EN_REG[1] = 0;
+  INTC->INTC_MASK_REG[0] = INTC->INTC_MASK_REG[1] = 0;
+  INTC->INTC_FF_REG[0] = INTC->INTC_FF_REG[1] = 0;
+  INTC->INTC_RESP_REG[0] = INTC->INTC_RESP_REG[1] = 0;
+  INTC->INTC_PEND_REG[0] = INTC->INTC_PEND_REG[1] = ~0UL;
+  INTC->INTC_BASE_ADDR_REG = 0;
+  INTC->NMI_INT_CTRL_REG = 0;
+  for (unsigned int i = 0; i < COUNTOF(irq_table); i++) {
+    irq_table[i] = 0;
+  }
+}
diff --git a/hw/mcu/allwinner/f1c100s/machine/start.S b/hw/mcu/allwinner/f1c100s/machine/start.S
new file mode 100644
index 000000000..1fd7cb1f9
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/machine/start.S
@@ -0,0 +1,313 @@
+/*
+ * start.S
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ * Official site: http://xboot.org
+ * Mobile phone: +86-18665388956
+ * QQ: 8192542
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+/*
+ * Exception vector table
+ */
+.text
+	.arm
+
+	.global	_start
+_start:
+	/* Boot head information for BROM */
+	.long 0xea000016
+	.byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
+	.long 0, __bootloader_size
+	.byte 'S', 'P', 'L', 2
+	.long 0, 0
+	.long 0, 0, 0, 0, 0, 0, 0, 0
+	.long 0, 0, 0, 0, 0, 0, 0, 0	/* 0x40 - boot params, 0x58 - fel boot type, 0x5c - dram size */
+
+_vector:
+	b reset
+	ldr pc, _undefined_instruction
+	ldr pc, _software_interrupt
+	ldr pc, _prefetch_abort
+	ldr pc, _data_abort
+	ldr pc, _not_used
+	ldr pc, _irq
+	ldr pc, _fiq
+
+_undefined_instruction:
+	.word undefined_instruction
+_software_interrupt:
+	.word software_interrupt
+_prefetch_abort:
+	.word prefetch_abort
+_data_abort:
+	.word data_abort
+_not_used:
+	.word not_used
+_irq:
+	.word irq
+_fiq:
+	.word fiq
+
+/*
+ * The actual reset code
+ */
+reset:
+	/* Save boot params to 0x00000040 */
+	ldr r0, =0x00000040
+	str sp, [r0, #0]
+	str lr, [r0, #4]
+	mrs lr, cpsr
+	str lr, [r0, #8]
+	mrc p15, 0, lr, c1, c0, 0
+	str lr, [r0, #12]
+	mrc p15, 0, lr, c1, c0, 0
+	str lr, [r0, #16]
+
+	/* Check boot type just for fel */
+	mov r0, #0x0
+	ldr r1, [r0, #8]
+	ldr r2, =0x4c45462e
+	cmp r1, r2
+	bne 1f
+	ldr r1, =0x1
+	str r1, [r0, #0x58]
+1:	nop
+
+	/* Enter svc mode and mask interrupts */
+	mrs r0, cpsr
+	bic r0, r0, #0x1f
+	orr r0, r0, #0xd3
+	msr cpsr, r0
+
+	/* Set vector to the low address */
+	mrc p15, 0, r0, c1, c0, 0
+	bic r0, #(1<<13)
+	mcr p15, 0, r0, c1, c0, 0
+
+	/* Copy vector to the correct address */
+	adr r0, _vector
+	mrc p15, 0, r2, c1, c0, 0
+	ands r2, r2, #(1 << 13)
+	ldreq r1, =0x00000000
+	ldrne r1, =0xffff0000
+	ldmia r0!, {r2-r8, r10}
+	stmia r1!, {r2-r8, r10}
+	ldmia r0!, {r2-r8, r10}
+	stmia r1!, {r2-r8, r10}
+
+	/* Initial system clock, ddr add uart */
+	bl sys_clock_init
+	bl sys_dram_init
+	bl sys_uart_init
+
+	/* Boot speed up, leave slower sram */
+	adr r0, _start
+	ldr r1, =_start
+	cmp r0, r1
+	beq _speedup
+	ldr r0, =0x81f80000
+	adr r1, _start
+	mov r2, #0x4000
+	bl memcpy
+	ldr r0, =_speedup
+	ldr r1, =_start
+	sub r0, r0, r1
+	ldr r1, =0x81f80000
+	add r0, r0, r1
+	mov pc, r0
+_speedup:
+	nop
+
+	/* Copyself to link address */
+	adr r0, _start
+	ldr r1, =_start
+	cmp r0, r1
+	beq 1f
+	bl sys_copyself
+1:	nop
+
+	/* Initialize stacks */
+	mrs r0, cpsr
+	bic r0, r0, #0x1f
+	orr r1, r0, #0x1b
+	msr cpsr_cxsf, r1
+	ldr sp, _stack_und_end
+
+	bic r0, r0, #0x1f
+	orr r1, r0, #0x17
+	msr cpsr_cxsf, r1
+	ldr sp, _stack_abt_end
+
+	bic r0, r0, #0x1f
+	orr r1, r0, #0x12
+	msr cpsr_cxsf, r1
+	ldr sp, _stack_irq_end
+
+	bic r0, r0, #0x1f
+	orr r1, r0, #0x11
+	msr cpsr_cxsf, r1
+	ldr sp, _stack_fiq_end
+
+	bic r0, r0, #0x1f
+	orr r1, r0, #0x13
+	msr cpsr_cxsf, r1
+	ldr sp, _stack_srv_end
+
+	/* Copy data section */
+	ldr r0, _data_start
+	ldr r1, _data_shadow_start
+	ldr r2, _data_shadow_end
+	sub r2, r2, r1
+	bl memcpy
+
+	/* Clear bss section */
+	ldr r0, _bss_start
+	ldr r2, _bss_end
+	sub r2, r2, r0
+	mov r1, #0
+	bl memset
+
+	/* Call _main */
+	ldr r1, =_main
+	mov pc, r1
+_main:
+	bl main
+	b _main
+
+	.global return_to_fel
+return_to_fel:
+	mov r0, #0x4
+	mov r1, #'e'
+	strb r1, [r0, #0]
+	mov r1, #'G'
+	strb r1, [r0, #1]
+	mov r1, #'O'
+	strb r1, [r0, #2]
+	mov r1, #'N'
+	strb r1, [r0, #3]
+	mov r1, #'.'
+	strb r1, [r0, #4]
+	mov r1, #'F'
+	strb r1, [r0, #5]
+	mov r1, #'E'
+	strb r1, [r0, #6]
+	mov r1, #'L'
+	strb r1, [r0, #7]
+	ldr r0, =0x00000040
+	ldr sp, [r0, #0]
+	ldr lr, [r0, #4]
+	ldr r1, [r0, #16]
+	mcr p15, 0, r1, c1, c0, 0
+	ldr r1, [r0, #12]
+	mcr p15, 0, r1, c1, c0, 0
+	ldr r1, [r0, #8]
+	msr cpsr, r1
+	bx lr
+
+/*
+ * Exception handlers
+ */
+	.align 5
+undefined_instruction:
+	b .
+
+	.align 5
+software_interrupt:
+	b .
+
+	.align 5
+prefetch_abort:
+	b .
+
+	.align 5
+data_abort:
+	b .
+
+	.align 5
+not_used:
+	b .
+
+	.align 5
+irq:
+	ldr sp, _stack_irq_end
+	sub sp, sp, #72
+	stmia sp, {r0 - r12}
+	add r8, sp, #60
+	stmdb r8, {sp, lr}^
+	str lr, [r8, #0]
+	mrs r6, spsr
+	str r6, [r8, #4]
+	str r0, [r8, #8]
+	mov r0, sp
+	bl arm32_do_irq
+	ldmia sp, {r0 - lr}^
+	mov r0, r0
+	ldr lr, [sp, #60]
+	add sp, sp, #72
+	subs pc, lr, #4
+
+	.align 5
+fiq:
+	ldr sp, _stack_irq_end
+	sub sp, sp, #72
+	stmia sp, {r0 - r12}
+	add r8, sp, #60
+	stmdb r8, {sp, lr}^
+	str lr, [r8, #0]
+	mrs r6, spsr
+	str r6, [r8, #4]
+	str r0, [r8, #8]
+	mov r0, sp
+	bl arm32_do_fiq
+	ldmia sp, {r0 - lr}^
+	mov r0, r0
+	ldr lr, [sp, #60]
+	add sp, sp, #72
+	subs pc, lr, #4
+
+/*
+ * The location of section
+ */
+ 	.align 4
+_image_start:
+	.long __image_start
+_image_end:
+	.long __image_end
+_data_shadow_start:
+	.long __data_shadow_start
+_data_shadow_end:
+	.long __data_shadow_end
+_data_start:
+	.long __data_start
+_data_end:
+	.long __data_end
+_bss_start:
+	.long __bss_start
+_bss_end:
+	.long __bss_end
+_stack_und_end:
+	.long __stack_und_end
+_stack_abt_end:
+	.long __stack_abt_end
+_stack_irq_end:
+	.long __stack_irq_end
+_stack_fiq_end:
+	.long __stack_fiq_end
+_stack_srv_end:
+	.long __stack_srv_end
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-clock.c b/hw/mcu/allwinner/f1c100s/machine/sys-clock.c
new file mode 100644
index 000000000..d151dd0c1
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/machine/sys-clock.c
@@ -0,0 +1,124 @@
+/*
+ * sys-clock.c
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ * Official site: http://xboot.org
+ * Mobile phone: +86-18665388956
+ * QQ: 8192542
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+//#include <xboot.h>
+#include <stdint.h>
+#include <f1c100s/reg-ccu.h>
+#include <io.h>
+
+static inline void sdelay(int loops)
+{
+	__asm__ __volatile__ ("1:\n" "subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0"(loops));
+}
+
+static void wait_pll_stable(uint32_t base)
+{
+	uint32_t rval = 0;
+	uint32_t time = 0xfff;
+
+	do {
+		rval = read32(base);
+		time--;
+	} while(time && !(rval & (1 << 28)));
+}
+
+static void clock_set_pll_cpu(uint32_t clk)
+{
+	uint32_t n, k, m, p;
+	uint32_t rval = 0;
+	uint32_t div = 0;
+
+	if(clk > 720000000)
+		clk = 720000000;
+
+	if((clk % 24000000) == 0)
+	{
+		div = clk / 24000000;
+		n = div - 1;
+		k = 0;
+		m = 0;
+		p = 0;
+	}
+	else if((clk % 12000000) == 0)
+	{
+		m = 1;
+		div = clk / 12000000;
+		if((div % 3) == 0)
+			k = 2;
+		else if((div % 4) == 0)
+			k = 3;
+		else
+			k = 1;
+		n = (div / (k + 1)) - 1;
+		p = 0;
+	}
+	else
+	{
+		div = clk / 24000000;
+		n = div - 1;
+		k = 0;
+		m = 0;
+		p = 0;
+	}
+
+	rval = read32(F1C100S_CCU_BASE + CCU_PLL_CPU_CTRL);
+	rval &= ~((0x3 << 16) | (0x1f << 8) | (0x3 << 4) | (0x3 << 0));
+	rval |= (1U << 31) | (p << 16) | (n << 8) | (k << 4) | m;
+	write32(F1C100S_CCU_BASE + CCU_PLL_CPU_CTRL, rval);
+	wait_pll_stable(F1C100S_CCU_BASE + CCU_PLL_CPU_CTRL);
+}
+
+void sys_clock_init(void)
+{
+	uint32_t val;
+
+	write32(F1C100S_CCU_BASE + CCU_PLL_STABLE_TIME0, 0x1ff);
+	write32(F1C100S_CCU_BASE + CCU_PLL_STABLE_TIME1, 0x1ff);
+
+	val = read32(F1C100S_CCU_BASE + CCU_CPU_CFG);
+	val &= ~(0x3 << 16);
+	val |= (0x1 << 16);
+	write32(F1C100S_CCU_BASE + CCU_CPU_CFG, val);
+	sdelay(100);
+
+	write32(F1C100S_CCU_BASE + CCU_PLL_VIDEO_CTRL, 0x81004107);
+	sdelay(100);
+	write32(F1C100S_CCU_BASE + CCU_PLL_PERIPH_CTRL, 0x80041800);
+	sdelay(100);
+	write32(F1C100S_CCU_BASE + CCU_AHB_APB_CFG, 0x00003180);
+	sdelay(100);
+
+	val = read32(F1C100S_CCU_BASE + CCU_DRAM_CLK_GATE);
+	val |= (0x1 << 26) | (0x1 << 24);
+	write32(F1C100S_CCU_BASE + CCU_DRAM_CLK_GATE, val);
+	sdelay(100);
+
+	clock_set_pll_cpu(408000000);
+	val = read32(F1C100S_CCU_BASE + CCU_CPU_CFG);
+	val &= ~(0x3 << 16);
+	val |= (0x2 << 16);
+	write32(F1C100S_CCU_BASE + CCU_CPU_CFG, val);
+	sdelay(100);
+}
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-copyself.c b/hw/mcu/allwinner/f1c100s/machine/sys-copyself.c
new file mode 100644
index 000000000..4116e1265
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/machine/sys-copyself.c
@@ -0,0 +1,111 @@
+/*
+ * sys-copyself.c
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ * Official site: http://xboot.org
+ * Mobile phone: +86-18665388956
+ * QQ: 8192542
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <stdint.h>
+
+extern unsigned char __image_start;
+extern unsigned char __image_end;
+extern void return_to_fel(void);
+extern void sys_mmu_init(void);
+extern void sys_uart_putc(char c);
+extern void sys_spi_flash_init(void);
+extern void sys_spi_flash_exit(void);
+extern void sys_spi_flash_read(int addr, void * buf, int count);
+
+enum {
+	BOOT_DEVICE_FEL	= 0,
+	BOOT_DEVICE_SPI	= 1,
+	BOOT_DEVICE_MMC	= 2,
+};
+
+static int get_boot_device(void)
+{
+	uint32_t * t = (void *)0x00000058;
+
+	if(t[0] == 0x1)
+		return BOOT_DEVICE_FEL;
+	return BOOT_DEVICE_SPI;
+}
+
+void sys_copyself(void)
+{
+	int d = get_boot_device();
+	void * mem;
+	uint32_t size;
+
+	if(d == BOOT_DEVICE_FEL)
+	{
+		sys_uart_putc('B');
+		sys_uart_putc('o');
+		sys_uart_putc('o');
+		sys_uart_putc('t');
+		sys_uart_putc(' ');
+		sys_uart_putc('t');
+		sys_uart_putc('o');
+		sys_uart_putc(' ');
+		sys_uart_putc('F');
+		sys_uart_putc('E');
+		sys_uart_putc('L');
+		sys_uart_putc(' ');
+		sys_uart_putc('m');
+		sys_uart_putc('o');
+		sys_uart_putc('d');
+		sys_uart_putc('e');
+		sys_uart_putc('\r');
+		sys_uart_putc('\n');
+		return_to_fel();
+	}
+	else if(d == BOOT_DEVICE_SPI)
+	{
+		sys_uart_putc('B');
+		sys_uart_putc('o');
+		sys_uart_putc('o');
+		sys_uart_putc('t');
+		sys_uart_putc(' ');
+		sys_uart_putc('t');
+		sys_uart_putc('o');
+		sys_uart_putc(' ');
+		sys_uart_putc('S');
+		sys_uart_putc('P');
+		sys_uart_putc('I');
+		sys_uart_putc(' ');
+		sys_uart_putc('m');
+		sys_uart_putc('o');
+		sys_uart_putc('d');
+		sys_uart_putc('e');
+		sys_uart_putc('\r');
+		sys_uart_putc('\n');
+		mem = (void *)&__image_start;
+		size = &__image_end - &__image_start;
+		sys_mmu_init();
+
+		sys_spi_flash_init();
+		sys_spi_flash_read(0, mem, size);
+		sys_spi_flash_exit();
+	}
+	else if(d == BOOT_DEVICE_MMC)
+	{
+		mem = (void *)&__image_start;
+		size = (&__image_end - &__image_start + 512) >> 9;
+	}
+}
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-dram.c b/hw/mcu/allwinner/f1c100s/machine/sys-dram.c
new file mode 100644
index 000000000..a819520a5
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/machine/sys-dram.c
@@ -0,0 +1,506 @@
+/*
+ * sys-dram.c
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ * Official site: http://xboot.org
+ * Mobile phone: +86-18665388956
+ * QQ: 8192542
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <stdint.h>
+#include <f1c100s/reg-ccu.h>
+#include <f1c100s/reg-dram.h>
+#include <io.h>
+
+#define PLL_DDR_CLK			(156000000)
+#define SDR_T_CAS			(0x2)
+#define SDR_T_RAS			(0x8)
+#define SDR_T_RCD			(0x3)
+#define SDR_T_RP			(0x3)
+#define SDR_T_WR			(0x3)
+#define SDR_T_RFC			(0xd)
+#define SDR_T_XSR			(0xf9)
+#define SDR_T_RC			(0xb)
+#define SDR_T_INIT			(0x8)
+#define SDR_T_INIT_REF		(0x7)
+#define SDR_T_WTR			(0x2)
+#define SDR_T_RRD			(0x2)
+#define SDR_T_XP			(0x0)
+
+enum dram_type_t
+{
+	DRAM_TYPE_SDR	= 0,
+	DRAM_TYPE_DDR	= 1,
+	DRAM_TYPE_MDDR	= 2,
+};
+
+struct dram_para_t
+{
+	uint32_t base;				/* dram base address */
+	uint32_t size;				/* dram size (unit: MByte) */
+	uint32_t clk;				/* dram work clock (unit: MHz) */
+	uint32_t access_mode;		/* 0: interleave mode 1: sequence mode */
+	uint32_t cs_num;			/* dram chip count  1: one chip  2: two chip */
+	uint32_t ddr8_remap;		/* for 8bits data width DDR 0: normal  1: 8bits */
+	enum dram_type_t sdr_ddr;
+	uint32_t bwidth;			/* dram bus width */
+	uint32_t col_width;		/* column address width */
+	uint32_t row_width;		/* row address width */
+	uint32_t bank_size;		/* dram bank count */
+	uint32_t cas;				/* dram cas */
+};
+
+static inline void sdelay(int loops)
+{
+	__asm__ __volatile__ ("1:\n" "subs %0, %1, #1\n"
+		"bne 1b":"=r" (loops):"0"(loops));
+}
+
+static void dram_delay(int ms)
+{
+	sdelay(ms * 2 * 1000);
+}
+
+static int dram_initial(void)
+{
+	unsigned int time = 0xffffff;
+
+	write32(F1C100S_DRAM_BASE + DRAM_SCTLR, read32(F1C100S_DRAM_BASE + DRAM_SCTLR) | 0x1);
+	while((read32(F1C100S_DRAM_BASE + DRAM_SCTLR) & 0x1) && time--)
+	{
+		if(time == 0)
+			return 0;
+	}
+	return 1;
+}
+
+static int dram_delay_scan(void)
+{
+	unsigned int time = 0xffffff;
+
+	write32(F1C100S_DRAM_BASE + DRAM_DDLYR, read32(F1C100S_DRAM_BASE + DRAM_DDLYR) | 0x1);
+	while((read32(F1C100S_DRAM_BASE + DRAM_DDLYR) & 0x1) && time--)
+	{
+		if(time == 0)
+			return 0;
+	}
+	return 1;
+}
+
+static void dram_set_autofresh_cycle(uint32_t clk)
+{
+	uint32_t val = 0;
+	uint32_t row = 0;
+	uint32_t temp = 0;
+
+	row = read32(F1C100S_DRAM_BASE + DRAM_SCONR);
+	row &= 0x1e0;
+	row >>= 0x5;
+
+	if(row == 0xc)
+	{
+		if(clk >= 1000000)
+		{
+			temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
+			while(temp >= (10000000 >> 6))
+			{
+				temp -= (10000000 >> 6);
+				val++;
+			}
+		}
+		else
+		{
+			val = (clk * 499) >> 6;
+		}
+	}
+	else if(row == 0xb)
+	{
+		if(clk >= 1000000)
+		{
+			temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
+			while(temp >= (10000000 >> 7))
+			{
+				temp -= (10000000 >> 7);
+				val++;
+			}
+		}
+		else
+		{
+			val = (clk * 499) >> 5;
+		}
+	}
+	write32(F1C100S_DRAM_BASE + DRAM_SREFR, val);
+}
+
+static int dram_para_setup(struct dram_para_t * para)
+{
+	uint32_t val = 0;
+
+    val = (para->ddr8_remap) |
+    	(0x1 << 1) |
+		((para->bank_size >> 2) << 3) |
+		((para->cs_num >> 1) << 4) |
+		((para->row_width - 1) << 5) |
+		((para->col_width - 1) << 9) |
+		((para->sdr_ddr ? (para->bwidth >> 4) : (para->bwidth >> 5)) << 13) |
+		(para->access_mode << 15) |
+		(para->sdr_ddr << 16);
+
+	write32(F1C100S_DRAM_BASE + DRAM_SCONR, val);
+	write32(F1C100S_DRAM_BASE + DRAM_SCTLR, read32(F1C100S_DRAM_BASE + DRAM_SCTLR) | (0x1 << 19));
+	return dram_initial();
+}
+
+static uint32_t dram_check_delay(uint32_t bwidth)
+{
+	uint32_t dsize;
+	uint32_t i,j;
+	uint32_t num = 0;
+	uint32_t dflag = 0;
+
+	dsize = ((bwidth == 16) ? 4 : 2);
+	for(i = 0; i < dsize; i++)
+	{
+		if(i == 0)
+			dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR0);
+		else if(i == 1)
+			dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR1);
+		else if(i == 2)
+			dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR2);
+		else if(i == 3)
+			dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR3);
+
+		for(j = 0; j < 32; j++)
+		{
+			if(dflag & 0x1)
+				num++;
+			dflag >>= 1;
+		}
+	}
+	return num;
+}
+
+static int sdr_readpipe_scan(void)
+{
+	uint32_t k = 0;
+
+	for(k = 0; k < 32; k++)
+	{
+		write32(0x80000000 + 4 * k, k);
+	}
+	for(k = 0; k < 32; k++)
+	{
+		if(read32(0x80000000 + 4 * k) != k)
+			return 0;
+	}
+	return 1;
+}
+
+static uint32_t sdr_readpipe_select(void)
+{
+	uint32_t value = 0;
+	uint32_t i = 0;
+	for(i = 0; i < 8; i++)
+	{
+		write32(F1C100S_DRAM_BASE + DRAM_SCTLR, (read32(F1C100S_DRAM_BASE + DRAM_SCTLR) & (~(0x7 << 6))) | (i << 6));
+		if(sdr_readpipe_scan())
+		{
+			value = i;
+			return value;
+		}
+	}
+	return value;
+}
+
+static uint32_t dram_check_type(struct dram_para_t * para)
+{
+	uint32_t val = 0;
+	uint32_t times = 0;
+	uint32_t i;
+
+	for(i = 0; i < 8; i++)
+	{
+		val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
+		val &= ~(0x7 << 6);
+		val |= (i << 6);
+		write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
+
+		dram_delay_scan();
+		if(read32(F1C100S_DRAM_BASE + DRAM_DDLYR) & 0x30)
+			times++;
+	}
+
+	if(times == 8)
+	{
+		para->sdr_ddr = DRAM_TYPE_SDR;
+		return 0;
+	}
+	else
+	{
+		para->sdr_ddr = DRAM_TYPE_DDR;
+		return 1;
+	}
+}
+
+static uint32_t dram_scan_readpipe(struct dram_para_t * para)
+{
+	uint32_t i, rp_best = 0, rp_val = 0;
+	uint32_t val = 0;
+	uint32_t readpipe[8];
+
+	if(para->sdr_ddr == DRAM_TYPE_DDR)
+	{
+		for(i = 0; i < 8; i++)
+		{
+			val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
+			val &= ~(0x7 << 6);
+			val |= (i << 6);
+			write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
+			dram_delay_scan();
+			readpipe[i] = 0;
+			if((((read32(F1C100S_DRAM_BASE + DRAM_DDLYR) >> 4) & 0x3) == 0x0) &&
+				(((read32(F1C100S_DRAM_BASE + DRAM_DDLYR) >> 4) & 0x1) == 0x0))
+			{
+				readpipe[i] = dram_check_delay(para->bwidth);
+			}
+			if(rp_val < readpipe[i])
+			{
+				rp_val = readpipe[i];
+				rp_best = i;
+			}
+		}
+		val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
+		val &= ~(0x7 << 6);
+		val |= (rp_best << 6);
+		write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
+		dram_delay_scan();
+	}
+	else
+	{
+		val = read32(F1C100S_DRAM_BASE + DRAM_SCONR);
+		val &= (~(0x1 << 16));
+		val &= (~(0x3 << 13));
+		write32(F1C100S_DRAM_BASE + DRAM_SCONR, val);
+		rp_best = sdr_readpipe_select();
+		val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
+		val &= ~(0x7 << 6);
+		val |= (rp_best << 6);
+		write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
+	}
+	return 0;
+}
+
+static uint32_t dram_get_dram_size(struct dram_para_t * para)
+{
+	uint32_t colflag = 10, rowflag = 13;
+	uint32_t i = 0;
+	uint32_t val1 = 0;
+	uint32_t count = 0;
+	uint32_t addr1, addr2;
+
+	para->col_width = colflag;
+	para->row_width = rowflag;
+	dram_para_setup(para);
+	dram_scan_readpipe(para);
+	for(i = 0; i < 32; i++)
+	{
+		*((uint32_t *)(0x80000200 + i)) = 0x11111111;
+		*((uint32_t *)(0x80000600 + i)) = 0x22222222;
+	}
+	for(i = 0; i < 32; i++)
+	{
+		val1 = *((uint32_t *)(0x80000200 + i));
+		if(val1 == 0x22222222)
+			count++;
+	}
+	if(count == 32)
+	{
+		colflag = 9;
+	}
+	else
+	{
+		colflag = 10;
+	}
+	count = 0;
+	para->col_width = colflag;
+	para->row_width = rowflag;
+	dram_para_setup(para);
+	if(colflag == 10)
+	{
+		addr1 = 0x80400000;
+		addr2 = 0x80c00000;
+	}
+	else
+	{
+		addr1 = 0x80200000;
+		addr2 = 0x80600000;
+	}
+	for(i = 0; i < 32; i++)
+	{
+		*((uint32_t *)(addr1 + i)) = 0x33333333;
+		*((uint32_t *)(addr2 + i)) = 0x44444444;
+	}
+	for(i = 0; i < 32; i++)
+	{
+		val1 = *((uint32_t *)(addr1 + i));
+		if(val1 == 0x44444444)
+		{
+			count++;
+		}
+	}
+	if(count == 32)
+	{
+		rowflag = 12;
+	}
+	else
+	{
+		rowflag = 13;
+	}
+	para->col_width = colflag;
+	para->row_width = rowflag;
+	if(para->row_width != 13)
+	{
+		para->size = 16;
+	}
+	else if(para->col_width == 10)
+	{
+		para->size = 64;
+	}
+	else
+	{
+		para->size = 32;
+	}
+	dram_set_autofresh_cycle(para->clk);
+	para->access_mode = 0;
+	dram_para_setup(para);
+
+	return 0;
+}
+
+static int dram_init(struct dram_para_t * para)
+{
+	uint32_t val = 0;
+	uint32_t i;
+
+	write32(0x01c20800 + 0x24, read32(0x01c20800 + 0x24) | (0x7 << 12));
+	dram_delay(5);
+	if(((para->cas) >> 3) & 0x1)
+	{
+		write32(0x01c20800 + 0x2c4, read32(0x01c20800 + 0x2c4) | (0x1 << 23) | (0x20 << 17));
+	}
+	if((para->clk >= 144) && (para->clk <= 180))
+	{
+		write32(0x01c20800 + 0x2c0, 0xaaa);
+	}
+	if(para->clk >= 180)
+	{
+		write32(0x01c20800 + 0x2c0, 0xfff);
+	}
+	if((para->clk) <= 96)
+	{
+		val = (0x1 << 0) | (0x0 << 4) | (((para->clk * 2) / 12 - 1) << 8) | (0x1u << 31);
+	}
+	else
+	{
+		val = (0x0 << 0) | (0x0 << 4) | (((para->clk * 2) / 24 - 1) << 8) | (0x1u << 31);
+	}
+
+	if(para->cas & (0x1 << 4))
+	{
+		write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xd1303333);
+	}
+	else if(para->cas & (0x1 << 5))
+	{
+		write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xcce06666);
+	}
+	else if(para->cas & (0x1 << 6))
+	{
+		write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xc8909999);
+	}
+	else if(para->cas & (0x1 << 7))
+	{
+		write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xc440cccc);
+	}
+	if(para->cas & (0xf << 4))
+	{
+		val |= 0x1 << 24;
+	}
+	write32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL, val);
+	write32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL, read32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL) | (0x1 << 20));
+	while((read32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL) & (1 << 28)) == 0);
+	dram_delay(5);
+	write32(F1C100S_CCU_BASE + CCU_BUS_CLK_GATE0, read32(F1C100S_CCU_BASE + CCU_BUS_CLK_GATE0) | (0x1 << 14));
+	write32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0, read32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0) & ~(0x1 << 14));
+	for(i = 0; i < 10; i++)
+		continue;
+	write32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0, read32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0) | (0x1 << 14));
+
+	val = read32(0x01c20800 + 0x2c4);
+	(para->sdr_ddr == DRAM_TYPE_DDR) ? (val |= (0x1 << 16)) : (val &= ~(0x1 << 16));
+	write32(0x01c20800 + 0x2c4, val);
+
+	val = (SDR_T_CAS << 0) | (SDR_T_RAS << 3) | (SDR_T_RCD << 7) | (SDR_T_RP << 10) | (SDR_T_WR << 13) | (SDR_T_RFC << 15) | (SDR_T_XSR << 19) | (SDR_T_RC << 28);
+	write32(F1C100S_DRAM_BASE + DRAM_STMG0R, val);
+	val = (SDR_T_INIT << 0) | (SDR_T_INIT_REF << 16) | (SDR_T_WTR << 20) | (SDR_T_RRD << 22) | (SDR_T_XP << 25);
+	write32(F1C100S_DRAM_BASE + DRAM_STMG1R, val);
+	dram_para_setup(para);
+	dram_check_type(para);
+
+	val = read32(0x01c20800 + 0x2c4);
+	(para->sdr_ddr == DRAM_TYPE_DDR) ? (val |= (0x1 << 16)) : (val &= ~(0x1 << 16));
+	write32(0x01c20800 + 0x2c4, val);
+
+	dram_set_autofresh_cycle(para->clk);
+	dram_scan_readpipe(para);
+	dram_get_dram_size(para);
+
+	for(i = 0; i < 128; i++)
+	{
+		*((volatile uint32_t *)(para->base + 4 * i)) = para->base + 4 * i;
+	}
+
+	for(i = 0; i < 128; i++)
+	{
+		if(*((volatile uint32_t *)(para->base + 4 * i)) != (para->base + 4 * i))
+			return 0;
+	}
+	return 1;
+}
+
+void sys_dram_init(void)
+{
+	struct dram_para_t para;
+	uint32_t * dsz = (void *)0x0000005c;
+
+	para.base = 0x80000000;
+	para.size = 32;
+	para.clk = PLL_DDR_CLK / 1000000;
+	para.access_mode = 1;
+	para.cs_num = 1;
+	para.ddr8_remap = 0;
+	para.sdr_ddr = DRAM_TYPE_DDR;
+	para.bwidth = 16;
+	para.col_width = 10;
+	para.row_width = 13;
+	para.bank_size = 4;
+	para.cas = 0x3;
+
+	if((dsz[0] >> 24) == 'X')
+		return;
+	if(dram_init(&para))
+		dsz[0] = (((uint32_t)'X') << 24) | (para.size << 0);
+}
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-mmu.c b/hw/mcu/allwinner/f1c100s/machine/sys-mmu.c
new file mode 100644
index 000000000..3c89c7255
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/machine/sys-mmu.c
@@ -0,0 +1,57 @@
+/*
+ * sys-mmu.c
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ * Official site: http://xboot.org
+ * Mobile phone: +86-18665388956
+ * QQ: 8192542
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <stdint.h>
+#include <io.h>
+#include <sizes.h>
+#include <arm32.h>
+
+static void map_l1_section(uint32_t * ttb, virtual_addr_t virt, physical_addr_t phys, physical_size_t size, int type)
+{
+	physical_size_t i;
+
+	virt >>= 20;
+	phys >>= 20;
+	size >>= 20;
+	type &= 0x3;
+
+	for(i = size; i > 0; i--, virt++, phys++)
+		ttb[virt] = (phys << 20) | (0x3 << 10) | (0x0 << 5) | (type << 2) | (0x2 << 0);
+}
+
+void sys_mmu_init(void)
+{
+	uint32_t * ttb = (uint32_t *)(0x80000000 + SZ_1M * 31);
+
+	map_l1_section(ttb, 0x00000000, 0x00000000, SZ_2G, 0);
+	map_l1_section(ttb, 0x80000000, 0x80000000, SZ_2G, 0);
+	map_l1_section(ttb, 0x80000000, 0x80000000, SZ_1M * 32, 3);
+
+	arm32_ttb_set((uint32_t)(ttb));
+	arm32_tlb_invalidate();
+	arm32_domain_set(0x3);
+	arm32_mmu_enable();
+	arm32_icache_enable();
+	arm32_dcache_enable();
+}
\ No newline at end of file
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-spi-flash.c b/hw/mcu/allwinner/f1c100s/machine/sys-spi-flash.c
new file mode 100644
index 000000000..5c3b0f0aa
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/machine/sys-spi-flash.c
@@ -0,0 +1,204 @@
+/*
+ * sys-spi-flash.c
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ * Official site: http://xboot.org
+ * Mobile phone: +86-18665388956
+ * QQ: 8192542
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <stdint.h>
+#include <types.h>
+#include <string.h>
+#include <io.h>
+
+enum {
+	SPI_GCR	= 0x04,
+	SPI_TCR	= 0x08,
+	SPI_IER	= 0x10,
+	SPI_ISR	= 0x14,
+	SPI_FCR	= 0x18,
+	SPI_FSR	= 0x1c,
+	SPI_WCR	= 0x20,
+	SPI_CCR	= 0x24,
+	SPI_MBC	= 0x30,
+	SPI_MTC	= 0x34,
+	SPI_BCC	= 0x38,
+	SPI_TXD	= 0x200,
+	SPI_RXD	= 0x300,
+};
+
+void sys_spi_flash_init(void)
+{
+	virtual_addr_t addr;
+	uint32_t val;
+
+	/* Config GPIOC0, GPIOC1, GPIOC2 and GPIOC3 */
+	addr = 0x01c20848 + 0x00;
+	val = read32(addr);
+	val &= ~(0xf << ((0 & 0x7) << 2));
+	val |= ((0x2 & 0x7) << ((0 & 0x7) << 2));
+	write32(addr, val);
+
+	val = read32(addr);
+	val &= ~(0xf << ((1 & 0x7) << 2));
+	val |= ((0x2 & 0x7) << ((1 & 0x7) << 2));
+	write32(addr, val);
+
+	val = read32(addr);
+	val &= ~(0xf << ((2 & 0x7) << 2));
+	val |= ((0x2 & 0x7) << ((2 & 0x7) << 2));
+	write32(addr, val);
+
+	val = read32(addr);
+	val &= ~(0xf << ((3 & 0x7) << 2));
+	val |= ((0x2 & 0x7) << ((3 & 0x7) << 2));
+	write32(addr, val);
+
+	/* Deassert spi0 reset */
+	addr = 0x01c202c0;
+	val = read32(addr);
+	val |= (1 << 20);
+	write32(addr, val);
+
+	/* Open the spi0 bus gate */
+	addr = 0x01c20000 + 0x60;
+	val = read32(addr);
+	val |= (1 << 20);
+	write32(addr, val);
+
+	/* Set spi clock rate control register, divided by 4 */
+	addr = 0x01c05000;
+	write32(addr + SPI_CCR, 0x00001001);
+
+	/* Enable spi0 and do a soft reset */
+	addr = 0x01c05000;
+	val = read32(addr + SPI_GCR);
+	val |= (1 << 31) | (1 << 7) | (1 << 1) | (1 << 0);
+	write32(addr + SPI_GCR, val);
+	while(read32(addr + SPI_GCR) & (1 << 31));
+
+	val = read32(addr + SPI_TCR);
+	val &= ~(0x3 << 0);
+	val |= (1 << 6) | (1 << 2);
+	write32(addr + SPI_TCR, val);
+
+	val = read32(addr + SPI_FCR);
+	val |= (1 << 31) | (1 << 15);
+	write32(addr + SPI_FCR, val);
+}
+
+void sys_spi_flash_exit(void)
+{
+	virtual_addr_t addr = 0x01c05000;
+	uint32_t val;
+
+	/* Disable the spi0 controller */
+	val = read32(addr + SPI_GCR);
+	val &= ~((1 << 1) | (1 << 0));
+	write32(addr + SPI_GCR, val);
+}
+
+static void sys_spi_select(void)
+{
+	virtual_addr_t addr = 0x01c05000;
+	uint32_t val;
+
+	val = read32(addr + SPI_TCR);
+	val &= ~((0x3 << 4) | (0x1 << 7));
+	val |= ((0 & 0x3) << 4) | (0x0 << 7);
+	write32(addr + SPI_TCR, val);
+}
+
+static void sys_spi_deselect(void)
+{
+	virtual_addr_t addr = 0x01c05000;
+	uint32_t val;
+
+	val = read32(addr + SPI_TCR);
+	val &= ~((0x3 << 4) | (0x1 << 7));
+	val |= ((0 & 0x3) << 4) | (0x1 << 7);
+	write32(addr + SPI_TCR, val);
+}
+
+static void sys_spi_write_txbuf(uint8_t * buf, int len)
+{
+	virtual_addr_t addr = 0x01c05000;
+	int i;
+
+	if(!buf)
+		len = 0;
+
+	write32(addr + SPI_MTC, len & 0xffffff);
+	write32(addr + SPI_BCC, len & 0xffffff);
+	for(i = 0; i < len; ++i)
+		write8(addr + SPI_TXD, *buf++);
+}
+
+static int sys_spi_transfer(void * txbuf, void * rxbuf, int len)
+{
+	virtual_addr_t addr = 0x01c05000;
+	int count = len;
+	uint8_t * tx = txbuf;
+	uint8_t * rx = rxbuf;
+	uint8_t val;
+	unsigned int n, i;
+
+	while(count > 0)
+	{
+		n = (count <= 64) ? count : 64;
+		write32(addr + SPI_MBC, n);
+		sys_spi_write_txbuf(tx, n);
+		write32(addr + SPI_TCR, read32(addr + SPI_TCR) | (1 << 31));
+
+		while((read32(addr + SPI_FSR) & 0xff) < n);
+		for(i = 0; i < n; i++)
+		{
+			val = read8(addr + SPI_RXD);
+			if(rx)
+				*rx++ = val;
+		}
+
+		if(tx)
+			tx += n;
+		count -= n;
+	}
+	return len;
+}
+
+static int sys_spi_write_then_read(void * txbuf, int txlen, void * rxbuf, int rxlen)
+{
+	if(sys_spi_transfer(txbuf, NULL, txlen) != txlen)
+		return -1;
+	if(sys_spi_transfer(NULL, rxbuf, rxlen) != rxlen)
+		return -1;
+	return 0;
+}
+
+void sys_spi_flash_read(int addr, void * buf, int count)
+{
+	uint8_t tx[4];
+
+	tx[0] = 0x03;
+	tx[1] = (uint8_t)(addr >> 16);
+	tx[2] = (uint8_t)(addr >> 8);
+	tx[3] = (uint8_t)(addr >> 0);
+	sys_spi_select();
+	sys_spi_write_then_read(tx, 4, buf, count);
+	sys_spi_deselect();
+}
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-uart.c b/hw/mcu/allwinner/f1c100s/machine/sys-uart.c
new file mode 100644
index 000000000..0e61627b7
--- /dev/null
+++ b/hw/mcu/allwinner/f1c100s/machine/sys-uart.c
@@ -0,0 +1,83 @@
+/*
+ * sys-uart.c
+ *
+ * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
+ * Official site: http://xboot.org
+ * Mobile phone: +86-18665388956
+ * QQ: 8192542
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <types.h>
+#include <stdint.h>
+#include <io.h>
+
+void sys_uart_init(void)
+{
+	virtual_addr_t addr;
+	uint32_t val;
+
+	/* Config GPIOE1 and GPIOE0 to txd0 and rxd0 */
+	addr = 0x01c20890 + 0x00;
+	val = read32(addr);
+	val &= ~(0xf << ((1 & 0x7) << 2));
+	val |= ((0x5 & 0x7) << ((1 & 0x7) << 2));
+	write32(addr, val);
+
+	val = read32(addr);
+	val &= ~(0xf << ((0 & 0x7) << 2));
+	val |= ((0x5 & 0x7) << ((0 & 0x7) << 2));
+	write32(addr, val);
+
+	/* Open the clock gate for uart0 */
+	addr = 0x01c20068;
+	val = read32(addr);
+	val |= 1 << 20;
+	write32(addr, val);
+
+	/* Deassert uart0 reset */
+	addr = 0x01c202d0;
+	val = read32(addr);
+	val |= 1 << 20;
+	write32(addr, val);
+
+	/* Config uart0 to 115200-8-1-0 */
+	addr = 0x01c25000;
+	write32(addr + 0x04, 0x0);
+	write32(addr + 0x08, 0xf7);
+	write32(addr + 0x10, 0x0);
+	val = read32(addr + 0x0c);
+	val |= (1 << 7);
+	write32(addr + 0x0c, val);
+	write32(addr + 0x00, 0x36 & 0xff);
+	write32(addr + 0x04, (0x36 >> 8) & 0xff);
+	val = read32(addr + 0x0c);
+	val &= ~(1 << 7);
+	write32(addr + 0x0c, val);
+	val = read32(addr + 0x0c);
+	val &= ~0x1f;
+	val |= (0x3 << 0) | (0 << 2) | (0x0 << 3);
+	write32(addr + 0x0c, val);
+}
+
+void sys_uart_putc(char c)
+{
+	virtual_addr_t addr = 0x01c25000;
+
+	while((read32(addr + 0x7c) & (0x1 << 1)) == 0);
+	write32(addr + 0x00, c);
+}
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index b13842de1..71d0b92b2 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -4,6 +4,7 @@
 #include <f1c100s-irq.h>
 #include <device/dcd.h>
 #include "musb_def.h"
+#include "bsp/board.h"
 
 typedef uint32_t u32;
 typedef uint16_t u16;
@@ -69,8 +70,8 @@ static void usb_phy_write(int addr, int data, int len)
 static void delay_ms(uint32_t ms)
 {
 #if CFG_TUSB_OS == OPT_OS_NONE
-  int cnt = ms * 1000 * 1000 / 2;
-  while (cnt--) asm("nop");
+  int now = board_millis();
+  while (board_millis() - now <= ms) asm("nop");
 #else
   osal_task_delay(ms);
 #endif

From 28fb51c180e644cfb0be4b980b71850b19fe2ab9 Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Sat, 4 Dec 2021 18:08:23 +0800
Subject: [PATCH 0709/2085] Add TODO to README

---
 hw/bsp/f1c100s/README.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md
index a4865b925..893b32ea9 100644
--- a/hw/bsp/f1c100s/README.md
+++ b/hw/bsp/f1c100s/README.md
@@ -14,4 +14,5 @@ To enter FEL mode, you have to press BOOT button, then press RESET once, and rel
 ## TODO
 * Test on Tiny200 v2 (F1C200s)
 * Make it able to load .bin directly to SPI Flash and boot
-* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX` high speed MCU check in examples (maybe we should extract the logic?)
\ No newline at end of file
+* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX` high speed MCU check in examples (maybe we should extract the logic?)
+* `cdc_msc` example is not working. Device is only echoing the first character.
\ No newline at end of file

From 48e1f6d8990e450783f4887e41ce58fe0e463953 Mon Sep 17 00:00:00 2001
From: Valentin Milea <valentin.milea@gmail.com>
Date: Sat, 4 Dec 2021 16:04:48 +0200
Subject: [PATCH 0710/2085] Handle the closing of endpoints on RP2040

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 28 ++++++++++++++++----
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  4 ++-
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index e084478e0..8be16ad22 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -83,7 +83,7 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
 
   assert(((uintptr_t )next_buffer_ptr & 0b111111u) == 0);
   uint dpram_offset = hw_data_offset(ep->hw_data_buf);
-  assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX);
+  hard_assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX);
 
   pico_info("  Alloced %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf);
 
@@ -93,7 +93,6 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
   *ep->endpoint_control = reg;
 }
 
-#if 0 // todo unused
 static void _hw_endpoint_close(struct hw_endpoint *ep)
 {
     // Clear hardware registers and then zero the struct
@@ -103,6 +102,22 @@ static void _hw_endpoint_close(struct hw_endpoint *ep)
     *ep->buffer_control = 0;
     // Clear any endpoint state
     memset(ep, 0, sizeof(struct hw_endpoint));
+
+    // Reclaim buffer space if all endpoints are closed
+    bool reclaim_buffers = true;
+    for ( uint8_t i = 1; i < USB_MAX_ENDPOINTS; i++ )
+    {
+        if (hw_endpoint_get_by_num(i, TUSB_DIR_OUT)->hw_data_buf != NULL || hw_endpoint_get_by_num(i, TUSB_DIR_IN)->hw_data_buf != NULL)
+        {
+            reclaim_buffers = false;
+            break;
+        }
+    }
+    if (reclaim_buffers)
+    {
+        pico_info("  reclaim buffer space\n");
+        next_buffer_ptr = &usb_dpram->epx_data[0];
+    }
 }
 
 static void hw_endpoint_close(uint8_t ep_addr)
@@ -110,7 +125,6 @@ static void hw_endpoint_close(uint8_t ep_addr)
     struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
     _hw_endpoint_close(ep);
 }
-#endif
 
 static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type)
 {
@@ -224,6 +238,8 @@ static void reset_non_control_endpoints(void)
 
   // clear non-control hw endpoints
   tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2*sizeof(hw_endpoint_t));
+
+  pico_info("  reclaim buffer space\n");
   next_buffer_ptr = &usb_dpram->epx_data[0];
 }
 
@@ -479,10 +495,12 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
     (void) rhport;
-    (void) ep_addr;
 
-    // usbd.c says: In progress transfers on this EP may be delivered after this call
     pico_trace("dcd_edpt_close %02x\n", ep_addr);
+
+    // usbd.c says: In progress transfers on this EP may be delivered after this call.
+    // If the endpoint is no longer active when the transfer event is delivered, it will be ignored.
+    hw_endpoint_close(ep_addr);
 }
 
 void dcd_int_handler(uint8_t rhport)
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index c9e2f6b26..0a943b676 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -294,7 +294,9 @@ bool hw_endpoint_xfer_continue(struct hw_endpoint *ep)
   // Part way through a transfer
   if (!ep->active)
   {
-    panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string);
+    pico_info("Ignore xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+    _hw_endpoint_lock_update(ep, -1);
+    return false;
   }
 
   // Update EP struct from hardware state

From fa0e4d91f9e22b8c7b8f561fe225116b5f6a14a5 Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Sun, 5 Dec 2021 18:07:35 +0800
Subject: [PATCH 0711/2085] Save current EP before querying other EPs

---
 src/portable/sunxi/dcd_sunxi_musb.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 71d0b92b2..0bb031a80 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -185,6 +185,11 @@ static void USBC_SelectActiveEp(u8 ep_index)
 	USBC_Writeb(ep_index, USBC_REG_EPIND(USBC0_BASE));
 }
 
+static u8 USBC_GetActiveEp(void)
+{
+	return USBC_Readb(USBC_REG_EPIND(USBC0_BASE));
+}
+
 static void __USBC_Dev_ep0_SendStall(void)
 {
 	USBC_REG_set_bit_w(USBC_BP_CSR0_D_SEND_STALL, USBC_REG_CSR0(USBC0_BASE));
@@ -387,6 +392,8 @@ static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
 {
   free_block_t free_blocks[2 * (DCD_ATTR_ENDPOINT_MAX - 1)];
   unsigned num_blocks = 1;
+  /* Backup current EP to restore later */
+  u8 backup_ep = USBC_GetActiveEp();
 
   /* Initialize free memory block list */
   free_blocks[0].beg = 64 / 8;
@@ -416,6 +423,8 @@ static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
   }
   print_block_list(free_blocks, num_blocks);
 
+  USBC_SelectActiveEp(backup_ep);
+
   /* Find the best fit memory block */
   uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3;
   free_block_t const *min = NULL;

From 64b81fd4d316ff8e0390c843bdff236ed4151147 Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Sun, 5 Dec 2021 18:08:01 +0800
Subject: [PATCH 0712/2085] Close all EPs upon reset

---
 src/portable/sunxi/dcd_sunxi_musb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 0bb031a80..2150403a9 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -839,6 +839,7 @@ void dcd_init(uint8_t rhport)
   USBC_ForceIdToHigh(); // Force device mode
   USBC_ForceVbusValidToHigh();
   USBC_SelectBus(USBC_IO_TYPE_PIO, 0, 0);
+  dcd_edpt_close_all(rhport);
 
   #if TUD_OPT_HIGH_SPEED
     USBC_REG_set_bit_b(USBC_BP_POWER_D_HIGH_SPEED_EN, USBC_REG_PCTL(USBC0_BASE));

From 702698ee293727d31efb0c7134a15a261d878cb9 Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Sun, 5 Dec 2021 18:18:41 +0800
Subject: [PATCH 0713/2085] Add FIFO size check

---
 src/portable/sunxi/dcd_sunxi_musb.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 2150403a9..ecc076658 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -388,6 +388,12 @@ static inline void print_block_list(free_block_t const *blk, unsigned num)
 #define print_block_list(a,b)
 #endif
 
+#if CFG_TUSB_MCU == OPT_MCU_F1C100S
+#define USB_FIFO_SIZE_KB 2
+#else
+#error "Unsupported MCU"
+#endif
+
 static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
 {
   free_block_t free_blocks[2 * (DCD_ATTR_ENDPOINT_MAX - 1)];
@@ -397,7 +403,7 @@ static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
 
   /* Initialize free memory block list */
   free_blocks[0].beg = 64 / 8;
-  free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */
+  free_blocks[0].end = (USB_FIFO_SIZE_KB << 10) / 8; /* 2KiB / 8 bytes */
   for (int i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
     uint_fast16_t addr;
     int num;

From f308603a3aeffcf77e83d2cfb1c76a28e543272d Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Sun, 5 Dec 2021 22:31:09 +0800
Subject: [PATCH 0714/2085] Fix a typo that leads to incorrect RX handling

---
 src/portable/sunxi/dcd_sunxi_musb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index ecc076658..420ce1de0 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -598,7 +598,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
       pipe->buf       = buf + len;
     }
     pipe->remaining = rem - len;
-    __USBC_Dev_ep0_ReadDataComplete();
+    __USBC_Dev_Rx_ReadDataComplete();
   }
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;

From 1ffc366aa9bb9c2dda8210956c2ac9a6fbafc88b Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Sun, 5 Dec 2021 22:40:05 +0800
Subject: [PATCH 0715/2085] Change FIFO size to 4KB (not sure)

The datasheet says 2KB FIFO, but accroding to many
code examples, the F1C100s has at least 4KB of FIFO memory.
This is working with cdc_msc example,
but I'm not sure, this should be checked.
---
 src/portable/sunxi/dcd_sunxi_musb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 420ce1de0..e164f2c19 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -389,7 +389,7 @@ static inline void print_block_list(free_block_t const *blk, unsigned num)
 #endif
 
 #if CFG_TUSB_MCU == OPT_MCU_F1C100S
-#define USB_FIFO_SIZE_KB 2
+#define USB_FIFO_SIZE_KB 4
 #else
 #error "Unsupported MCU"
 #endif

From 96979a2c4a43902a3051c678858e788e7ffc8c60 Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Mon, 6 Dec 2021 19:56:27 +0800
Subject: [PATCH 0716/2085] Fix handling of RXRDY bit

---
 src/portable/sunxi/dcd_sunxi_musb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index e164f2c19..be1847b21 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -598,12 +598,12 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
       pipe->buf       = buf + len;
     }
     pipe->remaining = rem - len;
-    __USBC_Dev_Rx_ReadDataComplete();
   }
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return NULL != buf;
   }
+  __USBC_Dev_Rx_ReadDataComplete();
   return false;
 }
 

From ef879e8a8a43dfa34160f50d7f432c3140dec7fa Mon Sep 17 00:00:00 2001
From: Valentin Milea <valentin.milea@gmail.com>
Date: Mon, 6 Dec 2021 18:49:58 +0200
Subject: [PATCH 0717/2085] Support disabling feedback format correction #1234

---
 src/class/audio/audio_device.c |  3 ++-
 src/class/audio/audio_device.h | 10 ++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index d9f2e284e..a461e97c5 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2248,12 +2248,13 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 // Input value feedback has to be in 16.16 format - the format will be converted according to speed settings automatically
+// unless format correction is disabled.
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
 {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
   // Format the feedback value
-#if !TUD_OPT_HIGH_SPEED
+#if !TUD_OPT_HIGH_SPEED && !CFG_TUD_AUDIO_DISABLE_FEEDBACK_FORMAT_CORRECTION
   uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].fb_val;
 
   // For FS format is 10.14
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 5a469523c..731fd6c01 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -186,6 +186,11 @@
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP                    0                             // Feedback - 0 or 1
 #endif
 
+// Disable/enable conversion from 16.16 to 10.14 format on high-speed devices. See tud_audio_n_fb_set().
+#ifndef CFG_TUD_AUDIO_DISABLE_FEEDBACK_FORMAT_CORRECTION
+#define CFG_TUD_AUDIO_DISABLE_FEEDBACK_FORMAT_CORRECTION    0                             // 0 or 1
+#endif
+
 // Audio interrupt control EP size - disabled if 0
 #ifndef CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
 #define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN                     0                             // Audio interrupt control - if required - 6 Bytes according to UAC 2 specification (p. 74)
@@ -458,6 +463,11 @@ TU_ATTR_WEAK bool tud_audio_fb_done_cb(uint8_t rhport);
 // Value will be corrected for FS to 10.14 format automatically.
 // (see Universal Serial Bus Specification Revision 2.0 5.12.4.2).
 // Feedback value will be sent at FB endpoint interval till it's changed.
+//
+// Note that the USB Audio 2.0 driver on Windows 10 is not following the spec and expects 16.16
+// format for FS. You can define CFG_TUD_AUDIO_DISABLE_FEEDBACK_FORMAT_CORRECTION=1 as a workaround
+// to transmit the feedback value unchanged. Be aware that this might break feedback on other hosts,
+// though at least on Linux the ALSA driver will happily accept either format.
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
 static inline bool tud_audio_fb_set(uint32_t feedback);
 #endif

From 03835c818361bb6c5eafd8cb51e8a9bb6b4f16fb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 7 Dec 2021 16:27:48 +0700
Subject: [PATCH 0718/2085] move hcd_musb.c include to family.mk

---
 examples/host/cdc_msc_hid/.only.MCU_MSP432E4    | 0
 examples/host/cdc_msc_hid/.only.MCU_TM4C123     | 0
 examples/host/cdc_msc_hid/Makefile              | 3 +--
 examples/host/hid_controller/.only.MCU_MSP432E4 | 0
 examples/host/hid_controller/.only.MCU_TM4C123  | 0
 examples/host/hid_controller/Makefile           | 3 +--
 hw/bsp/msp432e4/family.mk                       | 1 +
 7 files changed, 3 insertions(+), 4 deletions(-)
 create mode 100644 examples/host/cdc_msc_hid/.only.MCU_MSP432E4
 create mode 100644 examples/host/cdc_msc_hid/.only.MCU_TM4C123
 create mode 100644 examples/host/hid_controller/.only.MCU_MSP432E4
 create mode 100644 examples/host/hid_controller/.only.MCU_TM4C123

diff --git a/examples/host/cdc_msc_hid/.only.MCU_MSP432E4 b/examples/host/cdc_msc_hid/.only.MCU_MSP432E4
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/cdc_msc_hid/.only.MCU_TM4C123 b/examples/host/cdc_msc_hid/.only.MCU_TM4C123
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index 8c8735a56..ce0dd1a40 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -21,7 +21,6 @@ SRC_C += \
 	src/host/usbh.c \
 	src/host/usbh_control.c \
 	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
-	src/portable/mentor/musb/hcd_musb.c
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
 
 include ../../rules.mk
diff --git a/examples/host/hid_controller/.only.MCU_MSP432E4 b/examples/host/hid_controller/.only.MCU_MSP432E4
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/hid_controller/.only.MCU_TM4C123 b/examples/host/hid_controller/.only.MCU_TM4C123
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index 909abe8a6..c58df562b 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -24,7 +24,6 @@ SRC_C += \
 	src/host/usbh.c \
 	src/host/usbh_control.c \
 	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
-	src/portable/mentor/musb/hcd_musb.c
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
 
 include ../../rules.mk
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
index b664c4c1b..e3cb90abc 100644
--- a/hw/bsp/msp432e4/family.mk
+++ b/hw/bsp/msp432e4/family.mk
@@ -23,6 +23,7 @@ MCU_DIR = hw/mcu/ti/msp432e4
 
 SRC_C += \
 	src/portable/mentor/musb/dcd_musb.c \
+	src/portable/mentor/musb/hcd_musb.c \
 	$(MCU_DIR)/Source/system_msp432e401y.c
 
 INC += \

From 8e0400d531bbbb8faf45576a3b5e55be9406cf6b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 7 Dec 2021 16:28:24 +0700
Subject: [PATCH 0719/2085] change uart baudrate for tm4c123 to 115200

---
 hw/bsp/tm4c123/family.c  | 25 ++++++++++++++++++-------
 hw/bsp/tm4c123/family.mk |  1 +
 2 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c
index 048832dc9..449781ce1 100644
--- a/hw/bsp/tm4c123/family.c
+++ b/hw/bsp/tm4c123/family.c
@@ -7,7 +7,13 @@
 //--------------------------------------------------------------------+
 void USB0_Handler(void)
 {
+#if TUSB_OPT_HOST_ENABLED
+  tuh_int_handler(0);
+#endif
+
+#if TUSB_OPT_DEVICE_ENABLED
   tud_int_handler(0);
+#endif
 }
 
 //--------------------------------------------------------------------+
@@ -23,10 +29,12 @@ static void board_uart_init (void)
   GPIOA->PCTL |= (1 << 0) | (1 << 4);          // Configure the GPIOPCTL register to select UART0 in PA0 and PA1
   GPIOA->DEN |= (1 << 0) | (1 << 1);           // Enable the digital functionality in PA0 and PA1
 
-                                               /** BAUDRATE = 9600 bits per second, refer manual for calculation **/
+  // BAUDRATE = 115200, with SystemCoreClock = 50 Mhz refer manual for calculation
+  //  - BRDI = SystemCoreClock / (16* baud)
+  //  - BRDF = int(fraction*64 + 0.5)
   UART0->CTL &= ~(1 << 0);                     // Disable UART0 by clearing UARTEN bit in the UARTCTL register
-  UART0->IBRD = 325;                           // Write the integer portion of the BRD to the UARTIRD register
-  UART0->FBRD = 33;                            // Write the fractional portion of the BRD to the UARTFBRD registerer
+  UART0->IBRD = 27;                            // Write the integer portion of the BRD to the UARTIRD register
+  UART0->FBRD = 8;                             // Write the fractional portion of the BRD to the UARTFBRD registerer
 
   UART0->LCRH = (0x3 << 5);                    // 8-bit, no parity, 1 stop bit
   UART0->CC = 0x0;                             // Configure the UART clock source as system clock
@@ -40,8 +48,7 @@ static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirm
   SYSCTL->RCGCGPIO |= (1 << 5);
 
   /* Let the clock stabilize */
-  while ( !((SYSCTL->PRGPIO) & (1 << 5)) )
-    ;
+  while ( !((SYSCTL->PRGPIO) & (1 << 5)) ) {}
 
   /* Port Digital Enable */
   port->DEN |= PinMsk;
@@ -60,9 +67,13 @@ static void board_switch_init (void)
 static void WriteGPIOPin (GPIOA_Type *port, uint8_t PinMsk, bool state)
 {
   if ( state )
+  {
     port->DATA |= PinMsk;
+  }
   else
+  {
     port->DATA &= ~(PinMsk);
+  }
 }
 
 static uint32_t ReadGPIOPin (GPIOA_Type *port, uint8_t pinMsk)
@@ -99,8 +110,7 @@ void board_init (void)
   SYSCTL->RCGCGPIO |= (1u << 3);
 
   /* Let the clock stabilize */
-  while ( !(SYSCTL->PRGPIO & (1u << 3)) )
-    ;
+  while ( !(SYSCTL->PRGPIO & (1u << 3)) ) {}
 
   /* USB IOs to Analog Mode */
   GPIOD->AFSEL &= ~((1u << 4) | (1u << 5));
@@ -119,6 +129,7 @@ void board_init (void)
   /* Initialize board UART */
   board_uart_init();
 
+  TU_LOG1_INT(SystemCoreClock);
 }
 
 void board_led_write (bool state)
diff --git a/hw/bsp/tm4c123/family.mk b/hw/bsp/tm4c123/family.mk
index 9665a2d7d..751076196 100644
--- a/hw/bsp/tm4c123/family.mk
+++ b/hw/bsp/tm4c123/family.mk
@@ -28,6 +28,7 @@ INC += \
 
 SRC_C += \
 	src/portable/mentor/musb/dcd_musb.c \
+	src/portable/mentor/musb/hcd_musb.c \
 	$(MCU_DIR)/Source/system_TM4C123.c \
 	$(MCU_DIR)/Source/GCC/tm4c123_startup.c
 

From a5251cb86bb35a2da1248e6d32106c694891b02b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 7 Dec 2021 17:14:20 +0700
Subject: [PATCH 0720/2085] skip host ci for tm4c due to sram overflow

---
 examples/host/cdc_msc_hid/.only.MCU_TM4C123    | 0
 examples/host/hid_controller/.only.MCU_TM4C123 | 0
 2 files changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 examples/host/cdc_msc_hid/.only.MCU_TM4C123
 delete mode 100644 examples/host/hid_controller/.only.MCU_TM4C123

diff --git a/examples/host/cdc_msc_hid/.only.MCU_TM4C123 b/examples/host/cdc_msc_hid/.only.MCU_TM4C123
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/hid_controller/.only.MCU_TM4C123 b/examples/host/hid_controller/.only.MCU_TM4C123
deleted file mode 100644
index e69de29bb..000000000

From 36e69b86bf0f95916a66a35874da15fb420296e1 Mon Sep 17 00:00:00 2001
From: Valentin Milea <valentin.milea@gmail.com>
Date: Tue, 7 Dec 2021 15:35:30 +0200
Subject: [PATCH 0721/2085] Remove buffer reclaim logs

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 8be16ad22..3a3bef6a5 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -115,7 +115,6 @@ static void _hw_endpoint_close(struct hw_endpoint *ep)
     }
     if (reclaim_buffers)
     {
-        pico_info("  reclaim buffer space\n");
         next_buffer_ptr = &usb_dpram->epx_data[0];
     }
 }
@@ -239,7 +238,7 @@ static void reset_non_control_endpoints(void)
   // clear non-control hw endpoints
   tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2*sizeof(hw_endpoint_t));
 
-  pico_info("  reclaim buffer space\n");
+  // reclaim buffer space
   next_buffer_ptr = &usb_dpram->epx_data[0];
 }
 

From 75f7fb3d9d267f168bc45fc218e1c443701ff11d Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Tue, 7 Dec 2021 22:53:52 +0800
Subject: [PATCH 0722/2085] Add mksunxi tool to make flashable image

---
 examples/rules.mk                   | 10 +++---
 hw/bsp/f1c100s/board.mk             |  7 ++++-
 hw/mcu/allwinner/f1c100s/f1c100s.ld | 19 ++++++------
 tools/mksunxi.py                    | 48 +++++++++++++++++++++++++++++
 4 files changed, 69 insertions(+), 15 deletions(-)
 create mode 100644 tools/mksunxi.py

diff --git a/examples/rules.mk b/examples/rules.mk
index 6314380ec..55e39f4ed 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -182,10 +182,12 @@ flash-jlink: $(BUILD)/$(PROJECT).hex
 flash-stlink: $(BUILD)/$(PROJECT).elf
 	STM32_Programmer_CLI --connect port=swd --write $< --go
 
-flash-xfel: $(BUILD)/$(PROJECT).bin
-	xfel ddr 
-	xfel write 0x80000000 $<
-	xfel exec 0x80000000
+$(BUILD)/$(PROJECT)-sunxi.bin: $(BUILD)/$(PROJECT).bin
+	$(PYTHON) $(TOP)/tools/mksunxi.py $< $@
+
+flash-xfel: $(BUILD)/$(PROJECT)-sunxi.bin
+	xfel spinor write 0 $<
+	xfel reset
 
 # Flash using pyocd
 PYOCD_OPTION ?=
diff --git a/hw/bsp/f1c100s/board.mk b/hw/bsp/f1c100s/board.mk
index 993aa0d24..9bd9380a7 100644
--- a/hw/bsp/f1c100s/board.mk
+++ b/hw/bsp/f1c100s/board.mk
@@ -41,5 +41,10 @@ INC += \
 	$(TOP)/$(MCU_DIR)/include \
 	$(TOP)/$(BOARD_PATH)
 
-# flash target using on-board stlink
+# flash target using xfel
 flash: flash-xfel
+
+exec: $(BUILD)/$(PROJECT).bin
+	xfel ddr 
+	xfel write 0x80000000 $<
+	xfel exec 0x80000000
\ No newline at end of file
diff --git a/hw/mcu/allwinner/f1c100s/f1c100s.ld b/hw/mcu/allwinner/f1c100s/f1c100s.ld
index a261618e5..43c353bbd 100644
--- a/hw/mcu/allwinner/f1c100s/f1c100s.ld
+++ b/hw/mcu/allwinner/f1c100s/f1c100s.ld
@@ -21,15 +21,15 @@ SECTIONS
 		PROVIDE(__bootloader_start = .);
 		PROVIDE(__image_start = .);
 		PROVIDE(__text_start = .);
-		*/machine/start.o (.text)
-		*/lib/memcpy.o (.text)
-		*/lib/memset.o (.text)
-		*/machine/sys-uart.o (.text)
-		*/machine/sys-clock.o (.text)
-		*/machine/sys-dram.o (.text)
-		*/machine/sys-mmu.o (.text)
-		*/machine/sys-spi-flash.o (.text)
-		*/machine/sys-copyself.o (.text)
+		_build/*/obj/hw/mcu/allwinner/*/machine/start_asm.o (.text)
+		_build/*/obj/hw/mcu/allwinner/*/lib/memcpy_asm.o (.text)
+		_build/*/obj/hw/mcu/allwinner/*/lib/memset_asm.o (.text)
+		_build/*/obj/hw/mcu/allwinner/*/machine/sys-uart.o (.text*)
+		_build/*/obj/hw/mcu/allwinner/*/machine/sys-clock.o (.text*)
+		_build/*/obj/hw/mcu/allwinner/*/machine/sys-dram.o (.text*)
+		_build/*/obj/hw/mcu/allwinner/*/machine/sys-mmu.o (.text*)
+		_build/*/obj/hw/mcu/allwinner/*/machine/sys-spi-flash.o (.text*)
+		_build/*/obj/hw/mcu/allwinner/*/machine/sys-copyself.o (.text*)
 		PROVIDE(__bootloader_end = .);
 	} > ram
 
@@ -37,7 +37,6 @@ SECTIONS
 
 	.text :
 	{
-		*/main.o (.text)
 		*(.text*)
 		*(.glue*)
 		*(.note.gnu.build-id)
diff --git a/tools/mksunxi.py b/tools/mksunxi.py
new file mode 100644
index 000000000..04786f429
--- /dev/null
+++ b/tools/mksunxi.py
@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+import sys
+import struct
+
+def align(num, alignment):
+    if num % alignment != 0:
+        num += (alignment - num % alignment)
+    return num
+
+
+def process_file(input, output):
+    with open(input, 'rb') as fin:
+        content = bytearray(fin.read())
+
+    align_value = 512
+    padded_length = align(len(content), align_value)
+    # pad file to actual length
+    content += b'\x00' * (padded_length - len(content))
+
+    struct_format = '<L8sLL'
+    (instruction, magic, checksum, length) = struct.unpack_from(struct_format, content)
+
+    if magic != b'eGON.BT0':
+        print("Magic is invalid:", magic)
+        return 2
+
+    checksum = 0x5F0A6C39
+    length = align(length, align_value)
+
+    struct.pack_into(struct_format, content, 0, instruction, magic, checksum, length)
+
+    checksum = 0
+    for i in range(0, length, 4):
+        (n, ) = struct.unpack_from('<L', content, i)
+        checksum += n
+        checksum %= 4294967296
+
+    struct.pack_into(struct_format, content, 0, instruction, magic, checksum, length)
+
+    with open(output, 'wb') as fout:
+        fout.write(content)
+    return 0
+
+if __name__ == "__main__":
+    if len(sys.argv) != 3:
+        print("Usage: mksunxi.py input.bin output.bin")
+        exit(1)
+    exit(process_file(sys.argv[1], sys.argv[2]))
\ No newline at end of file

From 43621ab9edda8765a555585e11fee2a9867c4140 Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Tue, 7 Dec 2021 22:58:19 +0800
Subject: [PATCH 0723/2085] Update README

---
 hw/bsp/f1c100s/README.md | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md
index 893b32ea9..cc33ca1f4 100644
--- a/hw/bsp/f1c100s/README.md
+++ b/hw/bsp/f1c100s/README.md
@@ -6,13 +6,13 @@ Currently tested on:
 
 * Lichee Pi Nano (F1C100s)
 
-## make flash
-`make flash` will use [xfel](https://github.com/xboot/xfel) to write the code to onchip DDR memory and execute it. It will not write the program to SPI Flash.
+## Flashing
+There are two options to put your code into the MCU: `flash` and `exec`. Both modes require you to install [xfel](https://github.com/xboot/xfel) tool to your PATH. You must enter FEL mode before any operation can be done. To enter FEL mode, press BOOT button, then press RESET once, and release BOOT button. You will find VID/PID=1f3a:efe8 on your PC.
 
-To enter FEL mode, you have to press BOOT button, then press RESET once, and release BOOT button. You will find VID/PID=1f3a:efe8 on your PC.
+Exec: `make BOARD=f1c100s exec` will just upload the image to the DDR ram and execute it. It will not touch anything in the SPI flash.
+
+Flash: `make BOARD=f1c100s flash` will write the image to SPI flash, and then reset the chip to execute it.
 
 ## TODO
 * Test on Tiny200 v2 (F1C200s)
-* Make it able to load .bin directly to SPI Flash and boot
-* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX` high speed MCU check in examples (maybe we should extract the logic?)
-* `cdc_msc` example is not working. Device is only echoing the first character.
\ No newline at end of file
+* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX` high speed MCU check in examples (maybe we should extract the logic?)
\ No newline at end of file

From cd76193f3c82a4d1cd870f91e5538bebd147e710 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Dec 2021 10:37:46 +0700
Subject: [PATCH 0724/2085] try updating clock configure for g4 nucleo (not
 work yet)

---
 hw/bsp/stm32g4/boards/stm32g474nucleo/board.h | 16 ++++++++++------
 hw/bsp/stm32g4/family.c                       | 14 +++++++-------
 2 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
index fd9d50183..e4088023d 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
@@ -61,18 +61,19 @@ static inline void board_clock_init(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
   // Configure the main internal regulator output voltage
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
 
   // Initializes the CPU, AHB and APB busses clocks
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
   RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
-  RCC_OscInitStruct.PLL.PLLN = 85;
+  RCC_OscInitStruct.PLL.PLLN = 50;
   RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
@@ -84,9 +85,12 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
 
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) ;
+
 #if 0 // TODO need to check if USB clock is enabled
   /* Enable HSI48 */
   memset(&RCC_OscInitStruct, 0, sizeof(RCC_OscInitStruct));
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index 318f50746..461dc61a1 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -118,13 +118,13 @@ void board_init(void)
 
   // USB Pins TODO double check USB clock and pin setup
   // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
-//  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-//  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-//  GPIO_InitStruct.Pull = GPIO_NOPULL;
-//  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-//  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-//
-//  __HAL_RCC_USB_CLK_ENABLE();
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  __HAL_RCC_USB_CLK_ENABLE();
 
   board_vbus_sense_init();
 }

From 527036b1f5a3f0aa3994f62e3ab18fa990a40cf8 Mon Sep 17 00:00:00 2001
From: Yunhao Tian <t123yh@outlook.com>
Date: Wed, 8 Dec 2021 13:39:27 +0800
Subject: [PATCH 0725/2085] Initialize MMU if we are executing from DDR

---
 hw/mcu/allwinner/f1c100s/machine/start.S | 27 ++++++++++++------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/hw/mcu/allwinner/f1c100s/machine/start.S b/hw/mcu/allwinner/f1c100s/machine/start.S
index 1fd7cb1f9..befb22148 100644
--- a/hw/mcu/allwinner/f1c100s/machine/start.S
+++ b/hw/mcu/allwinner/f1c100s/machine/start.S
@@ -111,37 +111,38 @@ reset:
 	ldmia r0!, {r2-r8, r10}
 	stmia r1!, {r2-r8, r10}
 
-	/* Initial system clock, ddr add uart */
+	/* Initial system clock, ddr and uart */
 	bl sys_clock_init
-	bl sys_dram_init
 	bl sys_uart_init
 
-	/* Boot speed up, leave slower sram */
+	/* Check if we are already running from dram */
 	adr r0, _start
 	ldr r1, =_start
 	cmp r0, r1
-	beq _speedup
+	beq _init_mmu
+
+	/* Init dram if not running from dram */
+	bl sys_dram_init
+
+	/* Copy bootloader to faster dram (sram is slower) */
 	ldr r0, =0x81f80000
 	adr r1, _start
 	mov r2, #0x4000
 	bl memcpy
-	ldr r0, =_speedup
+	ldr r0, =_copy_self
 	ldr r1, =_start
 	sub r0, r0, r1
 	ldr r1, =0x81f80000
 	add r0, r0, r1
 	mov pc, r0
-_speedup:
-	nop
-
+_init_mmu:
+	bl sys_mmu_init
+	b 1f
+_copy_self:
 	/* Copyself to link address */
-	adr r0, _start
-	ldr r1, =_start
-	cmp r0, r1
-	beq 1f
 	bl sys_copyself
-1:	nop
 
+1:	nop
 	/* Initialize stacks */
 	mrs r0, cpsr
 	bic r0, r0, #0x1f

From 21db2351fdd3edd560e14d2949b9b0d217a51f93 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Wed, 1 Dec 2021 13:38:20 +0100
Subject: [PATCH 0726/2085] nrf5x: Fix race condition during startup

When NRF5x device is reset by software (after DFU for example),
power event is ready from the beginning.
When power interrupt is triggered before tud_init() finished
USBD_IRQn is enabled before it would be enabled in tud_init().
This in turn may result in BUS RESET event being sent from
USB interrupt to USB task when queue is not initialized yet.
This scenario often happens in Mynewt build where queue creation
takes more time.

To prevent this scenario USBD_IRQn is not enabled in power event
interrupt handler before dcd_init() was called.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 2bcd56b8a..ed597a34f 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -1059,7 +1059,13 @@ void tusb_hal_nrf_power_event (uint32_t event)
 
       // Enable interrupt, priorities should be set by application
       NVIC_ClearPendingIRQ(USBD_IRQn);
-      NVIC_EnableIRQ(USBD_IRQn);
+      // Don't enable USBD interrupt yet, if dcd_init() did not finish yet
+      // Interrupt will be enabled by tud_init(), when USB stack is ready
+      // to handle interrupts.
+      if (tud_inited())
+      {
+        NVIC_EnableIRQ(USBD_IRQn);
+      }
 
       // Wait for HFCLK
       while ( !hfclk_running() ) { }

From 5039a5e54c184d6cc281890b6f328caef116bce7 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 8 Dec 2021 09:34:29 +0000
Subject: [PATCH 0727/2085] Update code to implement changes from upstream
 master

---
 hw/bsp/brtmm90x/family.c                 |  8 ++++++--
 src/device/dcd_attr.h                    |  4 ++--
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 18 +++++++++---------
 3 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index ed169655e..739a8358d 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -63,7 +63,8 @@ void board_init(void)
     // Use sizeof to avoid pulling in strlen unnecessarily.
     board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG));
 
-#if 1
+#if 0
+    // Ethernet LEDs
     gpio_function(GPIO_ETH_LED0, pad_gpio4); /* ETH LED0 */
     gpio_dir(GPIO_ETH_LED0, pad_dir_open_drain);
     gpio_function(GPIO_ETH_LED1, pad_gpio5); /* ETH LED1 */
@@ -192,7 +193,10 @@ int board_uart_read(uint8_t *buf, int len)
 // Send characters to UART
 int board_uart_write(void const *buf, int len)
 {
-    int r = uart_writen(UART0, (uint8_t *)buf, len);
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual" // uart_writen does not have const for buffer parameter.
+    int r = uart_writen(UART0, (uint8_t *)((const void *)buf), len);
+#pragma GCC diagnostic pop
 
     return r;
 }
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index c51940573..21bfbb545 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -198,10 +198,10 @@
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 //------------- BridgeTek -------------//
-#elif TU_CHECK_MCU(FT90X)
+#elif TU_CHECK_MCU(OPT_MCU_FT90X)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
-#elif TU_CHECK_MCU(FT93X)
+#elif TU_CHECK_MCU(OPT_MCU_FT93X)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
 #else
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 3235d0ef1..aa45aa1dd 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -56,10 +56,10 @@ static uint8_t _ft90x_setup_packet[8];
 
 struct ft90x_xfer_state
 {
-  volatile int16_t total_size; // Total transfer size in bytes for this transfer.
-  volatile int16_t remain_size; // Total remaining in transfer.
-  volatile uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
-  volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
+  uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
+  int16_t total_size; // Total transfer size in bytes for this transfer.
+  int16_t remain_size; // Total remaining in transfer.
+  uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
 
   uint8_t type; // Endpoint type. Of type USBD_ENDPOINT_TYPE from endpoint descriptor.
   uint8_t dir; // Endpoint direction. TUSB_DIR_OUT or TUSB_DIR_IN. For control endpoint this is the current direction.
@@ -399,7 +399,7 @@ static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_
 #ifdef USBD_USE_STREAMS
   volatile uint8_t *data_reg;
 
-  data_reg = (uint8_t *)&(USBD->ep[ep_number].epxfifo);
+  data_reg = (volatile uint8_t *)&(USBD->ep[ep_number].epxfifo);
   if (buff_size)
   {
     if (((uint32_t)buffer) % 4 == 0)
@@ -476,7 +476,7 @@ static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len
     buff_size = length;
 
 #ifdef USBD_USE_STREAMS
-  data_reg = (uint8_t *)&(USBD->ep[ep_number].epxfifo);
+  data_reg = (volatile uint8_t *)&(USBD->ep[ep_number].epxfifo);
   if (buff_size)
   {
     if ((uint32_t)buffer % 4 == 0)
@@ -656,7 +656,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
   uint8_t const ep_number = tu_edpt_number(ep_desc->bEndpointAddress);
   uint8_t const ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
   uint8_t const ep_type = ep_desc->bmAttributes.xfer;
-  uint16_t const ep_size = ep_desc->wMaxPacketSize.size;
+  uint16_t const ep_size = tu_edpt_packet_size(ep_desc); // Mask size per packet, bits 10..0.
   uint16_t ep_buff_size;
   uint8_t ep_reg_size = USBD_EP_MAX_SIZE_8;
   uint8_t ep_reg_data = 0;
@@ -673,13 +673,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
 
   // Calculate the physical size of the endpoint as a power of 2. This may be more than
   // the requested size.
-  while (ep_desc->wMaxPacketSize.size > (8 * (1 << ep_reg_size)))
+  while (ep_size > (8 * (1 << ep_reg_size)))
   {
     ep_reg_size++;
   }
   if (ep_reg_size > USBD_EP_MAX_SIZE_1024)
   {
-    TU_LOG1("FT90x endpoint size not valid: requested %d max 1024\r\n", ep_desc->wMaxPacketSize.size);
+    TU_LOG1("FT90x endpoint size not valid: requested %d max 1024\r\n", ep_size);
     return false;
   }
   // Calculate actual amount of buffer RAM used by this endpoint. This may be more than the 

From 45869958f6066fe4d195c62423cba2fec1886cbc Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 8 Dec 2021 10:03:33 +0000
Subject: [PATCH 0728/2085] Add FT9xx to more examples which support High-Speed

---
 examples/device/hid_boot_interface/src/tusb_config.h     | 3 ++-
 examples/device/hid_composite/src/tusb_config.h          | 3 ++-
 examples/device/hid_multiple_interface/src/tusb_config.h | 3 ++-
 examples/device/midi_test/src/tusb_config.h              | 3 ++-
 hw/bsp/brtmm90x/family.c                                 | 3 ++-
 5 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/examples/device/hid_boot_interface/src/tusb_config.h b/examples/device/hid_boot_interface/src/tusb_config.h
index 59fb9962c..1381dd6b2 100644
--- a/examples/device/hid_boot_interface/src/tusb_config.h
+++ b/examples/device/hid_boot_interface/src/tusb_config.h
@@ -48,7 +48,8 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X || \
+       CFG_TUSB_MCU == OPT_MCU_FT90X   || CFG_TUSB_MCU == OPT_MCU_FT93X)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index 8fa5e5cd4..449efbc7e 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -48,7 +48,8 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
-      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711)
+      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) ||\
+      TU_CHECK_MCU(OPT_MCU_FT90X, OPT_MCU_FT93X)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/hid_multiple_interface/src/tusb_config.h b/examples/device/hid_multiple_interface/src/tusb_config.h
index a0aa17a90..c034b086e 100644
--- a/examples/device/hid_multiple_interface/src/tusb_config.h
+++ b/examples/device/hid_multiple_interface/src/tusb_config.h
@@ -48,7 +48,8 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || \
+       CFG_TUSB_MCU == OPT_MCU_FT90X   || CFG_TUSB_MCU == OPT_MCU_FT93X)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/examples/device/midi_test/src/tusb_config.h b/examples/device/midi_test/src/tusb_config.h
index 61b9b6552..a40d7605c 100644
--- a/examples/device/midi_test/src/tusb_config.h
+++ b/examples/device/midi_test/src/tusb_config.h
@@ -48,7 +48,8 @@
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
+       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || \
+       CFG_TUSB_MCU == OPT_MCU_FT90X   || CFG_TUSB_MCU == OPT_MCU_FT93X)
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
   #else
     #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 739a8358d..803a62a95 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -24,8 +24,9 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "board.h"
 #include "bsp/board.h"
+#include "board.h"
+
 #include <registers/ft900_registers.h>
 #include <ft900.h>
 

From fa06bd01c97a3a14215ea145764c09aecaa0dd79 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 8 Dec 2021 10:05:32 +0000
Subject: [PATCH 0729/2085] Merge in upstream changes

Merge upstream changes and expand example support to hid examples.
---
 .vscode/c_cpp_properties.json |  41 ++++++++
 .vscode/launch.json           |  32 +++++++
 .vscode/settings.json         |  17 ++++
 .vscode/tasks.json            | 176 ++++++++++++++++++++++++++++++++++
 examples/make.mk              |   3 +-
 examples/rules.mk             |   4 +-
 6 files changed, 270 insertions(+), 3 deletions(-)
 create mode 100644 .vscode/c_cpp_properties.json
 create mode 100644 .vscode/launch.json
 create mode 100644 .vscode/settings.json
 create mode 100644 .vscode/tasks.json

diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json
new file mode 100644
index 000000000..28d4718b2
--- /dev/null
+++ b/.vscode/c_cpp_properties.json
@@ -0,0 +1,41 @@
+{
+    "configurations": [
+        {
+            "name": "FT900",
+            "includePath": [
+                // Toolchain installed FT90X SDK.
+                "C:/Program Files (x86)/Bridgetek/FT9xx Toolchain/Toolchain/hardware/include",
+                // Submodule for FT90X SDK.
+                //"${workspaceFolder}/hw/mcu/bridgetek/ft9xx/hardware/Source/include",
+                // Board headers.
+                "${workspaceFolder}/hw/bsp/brtmm90x/boards/mm900evxb",
+                // Hardware abstraction headers.
+                "${workspaceFolder}/hw/",
+                // Local header files.
+                ".",
+                "${workspaceFolder}/src",
+                // Example headers.
+                "${workspaceFolder}/examples/device/cdc_msc/src"
+                //"${workspaceFolder}/examples/host/hid_controller/src"
+            ],
+            "defines": [
+                "__FT900__", 
+                "BOARD=mm900evxb",
+                //"FT32_PORT", "FT32_PORT_HEAP=4", // For FreeRTOS
+                "CFG_TUSB_MCU=OPT_MCU_FT90X", // For FT90x
+                //"CFG_TUSB_RHPORT0_MODE=(OPT_MODE_HOST|OPT_MODE_HIGH_SPEED)",
+                //"CFG_TUSB_RHPORT1_MODE=(OPT_MODE_DEVICE|OPT_MODE_HIGH_SPEED)",
+                //"BOARD_DEVICE_RHPORT_NUM=1", 
+                //"BOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED",
+                "CFG_TUSB_DEBUG=0"
+            ],
+            "windowsSdkVersion": "10.0.18362.0",
+            "compilerPath": "C:/Program Files (x86)/Bridgetek/FT9xx Toolchain/Toolchain/tools/bin/ft32-elf-gcc",
+            "cStandard": "c11",
+            "cppStandard": "c++11",
+            "intelliSenseMode": "windows-gcc-x64",
+            "configurationProvider": "ms-vscode.makefile-tools"
+        }
+    ],
+    "version": 4
+}
\ No newline at end of file
diff --git a/.vscode/launch.json b/.vscode/launch.json
new file mode 100644
index 000000000..7aa6e0616
--- /dev/null
+++ b/.vscode/launch.json
@@ -0,0 +1,32 @@
+{
+    // Use IntelliSense to learn about possible attributes.
+    // Hover to view descriptions of existing attributes.
+    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
+    "version": "0.2.0",
+    "configurations": [
+        {
+            "name": "Debug TinyUSB CDC_MSC",
+            "type": "cppdbg",
+            "MIMode": "gdb",
+            "request": "launch",
+            "cwd": "${workspaceFolder}", 
+            "program": "examples/device/program.elf",
+            //"program": "examples/device/cdc_msc/_build/mm900ev1b/cdc_msc.elf",
+            "preLaunchTask": "Build and Program (Memory)",
+            "target": "localhost:9998",
+            "remote": true,
+            "gdbpath": "C:/Program Files (x86)/Bridgetek/FT9xx Toolchain/Toolchain/tools/bin/ft32-elf-gdb.exe",
+            "stopAtEntry": true,
+            "environment": [],
+            "console": "externalTerminal",
+            "miDebuggerPath": "C:/Program Files (x86)/Bridgetek/FT9xx Toolchain/Toolchain/tools/bin/ft32-elf-gdb.exe",
+            //"miDebuggerArgs": "-x lib\\FreeRTOS\\.gdbinit-FreeRTOS-helpers",
+            "miDebuggerServerAddress": "localhost:9998",
+            "launchCompleteCommand": "None",
+            "debugServerPath": "C:\\Users\\gordon.mcnab\\AppData\\Local\\Programs\\Python\\Python37\\python.exe",
+            "debugServerArgs": 
+                "\"C:/Program Files (x86)/Bridgetek/FT9xx Toolchain/Toolchain/utilities/gdb_bridge.py\" live pm",
+            //"rtos": "FreeRTOS",
+        }
+    ]
+}
diff --git a/.vscode/settings.json b/.vscode/settings.json
new file mode 100644
index 000000000..b0aef0cf8
--- /dev/null
+++ b/.vscode/settings.json
@@ -0,0 +1,17 @@
+{
+    "files.associations": {
+        "tusb_option.h": "c",
+        "ft900.h": "c",
+        "ft900_usbd.h": "c",
+        "ft900_registers.h": "c",
+        "ft900_usbd_registers.h": "c",
+        "dcd.h": "c",
+        "stdint.h": "c",
+        "board.h": "c",
+        "ft900_ehci_registers.h": "c",
+        "stdint-gcc.h": "c",
+        "ft900_memctl.h": "c",
+        "stddef.h": "c"
+    },
+    "cmake.configureOnOpen": true
+}
\ No newline at end of file
diff --git a/.vscode/tasks.json b/.vscode/tasks.json
new file mode 100644
index 000000000..459351c4f
--- /dev/null
+++ b/.vscode/tasks.json
@@ -0,0 +1,176 @@
+{
+    "version": "2.0.0",
+
+    "options": {
+        "env": {
+            // Set this to the type of example.
+            // Choices can be "device" or "host".
+            "exampleType": "device",
+            // Set this to the name of the example.
+            // The name is the folder name  in the examples directory.
+            "exampleName": "cdc_msc",
+            // Set this to the name of the board to target.
+            "boardName": "mm900evxb"
+        }
+    },
+
+    "inputs": [
+        {
+          "type": "pickString",
+          "id": "pickExampleName",
+          "description": "Which example project do you want to use?",
+          "options": [
+            "board_test",
+            "cdc_msc",
+            "hid_boot_interface",
+            "hid_composite",
+
+          ],
+          "default": "board_test"
+        },
+        {
+          "type": "pickString",
+          "id": "pickBoardName",
+          "description": "Which board type do you want to use?",
+          "options": [
+              "mm900ev1b",
+              "mm900ev2b",
+              "mm900ev3b"
+          ],
+          "default": "mm900ev1b"
+        }
+    ],
+    
+    "tasks": [
+        {
+            "label": "test env",
+            "type": "shell",
+            "command": "echo",
+            "args": [
+                "$env:exampleName"
+            ],
+            "problemMatcher": []
+        },
+        {
+            "label": "Build and Program (Memory)",
+            "dependsOrder": "sequence",
+            "dependsOn": [
+                "Build Project",
+                "Program Project (Memory)"
+            ],
+            "type": "shell",
+            "options": {
+                "cwd": "${workspaceFolder}"
+            },
+            "command": "copy",
+            "args": [
+                "examples\\$env:exampleType\\$env:exampleName\\_build\\$env:boardName\\$env:exampleName.elf",
+                "examples\\$env:exampleType\\program.elf"
+            ],
+            "problemMatcher": {
+                "pattern": {
+                    "regexp": "^Error:\\s+(.*)$",
+                    "message": 1
+                }
+            }
+        },
+        {
+            "label": "Build Project",
+            "type": "shell",
+            "options": {
+                "cwd": "${workspaceFolder}"
+            },
+            "command": "make.exe",
+            "args": [
+                "-C",
+                "examples\\$env:exampleType\\$env:exampleName",
+                "BOARD=$env:boardName"
+            ],
+            "problemMatcher": [
+                "$gcc"
+            ],
+            "group": {
+                "kind": "build",
+                "isDefault": true
+            }
+        },
+        {
+            "label": "Rebuild Project",
+            "type": "shell",
+            "options": {
+                "cwd": "${workspaceFolder}"
+            },
+            "command": "make.exe",
+            "args": [
+                "-C",
+                "examples\\$env:exampleType\\$env:exampleName",
+                "BOARD=$env:boardName",
+                "-B"
+            ],
+            "problemMatcher": [
+                "$gcc"
+            ],
+            "group": "build"
+        },
+        {
+            "label": "Clean Project",
+            "type": "shell",
+            "options": {
+                "cwd": "${workspaceFolder}"
+            },
+            "command": "make.exe",
+            "args": [
+                "-C",
+                "examples\\$env:exampleType\\$env:exampleName",
+                "BOARD=$env:boardName",
+                "clean"
+            ],
+            "problemMatcher": [
+                "$gcc"
+            ],
+            "group": "build"
+        },
+        {
+            "label": "Program Project (Flash)",
+            "type": "shell",
+            "options": {
+                "cwd": "${workspaceFolder}"
+            },
+            "command": "C:\\Program Files (x86)\\Bridgetek\\FT9xx Toolchain\\Toolchain\\programmer\\dist\\FT900Prog.exe",
+            "args": [
+                "--loadflash",
+                "examples\\$env:exampleType\\$env:exampleName\\_build\\$env:boardName\\$env:exampleName.bin",
+                "--onewire",
+                "--noReset"
+            ],
+            "problemMatcher": {
+                "pattern": {
+                    "regexp": "^Error:\\s+(.*)$",
+                    "message": 1
+                }
+            },
+            "dependsOn": "${defaultBuildTask}"
+        },
+        {
+            "label": "Program Project (Memory)",
+            "type": "shell",
+            "options": {
+                "cwd": "${workspaceFolder}"
+            },
+            "command": "C:\\Program Files (x86)\\Bridgetek\\FT9xx Toolchain\\Toolchain\\programmer\\dist\\FT900Prog.exe",
+            "args": [
+                "--loadpm",
+                "examples\\$env:exampleType\\$env:exampleName\\_build\\$env:boardName\\$env:exampleName.bin",
+                "--onewire",
+                "--noReset"
+            ],
+            "problemMatcher": {
+                "pattern": {
+                    "regexp": "^Error:\\s+(.*)$",
+                    "message": 1
+                }
+            },
+            "dependsOn": "${defaultBuildTask}"
+        }
+    ],
+}
\ No newline at end of file
diff --git a/examples/make.mk b/examples/make.mk
index 793c40aa2..e1cd0af2a 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -104,10 +104,11 @@ CFLAGS += \
   -Wmissing-format-attribute \
   -Wunreachable-code \
   -Wcast-align \
-  -Wcast-function-type \
   -Wcast-qual \
   -Wnull-dereference
 
+#  -Wcast-function-type \
+
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
   CFLAGS += -Og
diff --git a/examples/rules.mk b/examples/rules.mk
index 4cc35cb22..a12a75d60 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -84,7 +84,7 @@ OBJ_DIRS = $(sort $(dir $(OBJ)))
 $(OBJ): | $(OBJ_DIRS)
 $(OBJ_DIRS):
 ifeq ($(CMDEXE),1)
-	@$(MKDIR) $(subst /,\,$@)
+	-@$(MKDIR) $(subst /,\,$@)
 else
 	@$(MKDIR) -p $@
 endif
@@ -207,7 +207,7 @@ debug-bmp: $(BUILD)/$(PROJECT).elf
 
 # Create binary directory
 $(BIN):
-	@$(MKDIR) -p $@
+	-@$(MKDIR) -p $@
 
 # Copy binaries .elf, .bin, .hex, .uf2 to BIN for upload
 # due to large size of combined artifacts, only uf2 is uploaded for now

From ae970ba2e2cc83881c52e66cd79fad5947e5e59e Mon Sep 17 00:00:00 2001
From: Valentin Milea <valentin.milea@gmail.com>
Date: Wed, 8 Dec 2021 12:33:30 +0200
Subject: [PATCH 0730/2085] Handle xfer events before closing EP

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 17 ++++++++---------
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  4 +---
 2 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 3a3bef6a5..42add3167 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -247,6 +247,14 @@ static void dcd_rp2040_irq(void)
     uint32_t const status = usb_hw->ints;
     uint32_t handled = 0;
 
+    // xfer events are handled before setup req. So if a transfer completes immediately
+    // before closing the EP, the events will be delivered in same order.
+    if (status & USB_INTS_BUFF_STATUS_BITS)
+    {
+        handled |= USB_INTS_BUFF_STATUS_BITS;
+        hw_handle_buff_status();
+    }
+
     if (status & USB_INTS_SETUP_REQ_BITS)
     {
         handled |= USB_INTS_SETUP_REQ_BITS;
@@ -260,12 +268,6 @@ static void dcd_rp2040_irq(void)
         usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS;
     }
 
-    if (status & USB_INTS_BUFF_STATUS_BITS)
-    {
-        handled |= USB_INTS_BUFF_STATUS_BITS;
-        hw_handle_buff_status();
-    }
-
 #if FORCE_VBUS_DETECT == 0
     // Since we force VBUS detect On, device will always think it is connected and
     // couldn't distinguish between disconnect and suspend
@@ -496,9 +498,6 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
     (void) rhport;
 
     pico_trace("dcd_edpt_close %02x\n", ep_addr);
-
-    // usbd.c says: In progress transfers on this EP may be delivered after this call.
-    // If the endpoint is no longer active when the transfer event is delivered, it will be ignored.
     hw_endpoint_close(ep_addr);
 }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 0a943b676..9d833e65f 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -294,9 +294,7 @@ bool hw_endpoint_xfer_continue(struct hw_endpoint *ep)
   // Part way through a transfer
   if (!ep->active)
   {
-    pico_info("Ignore xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
-    _hw_endpoint_lock_update(ep, -1);
-    return false;
+    panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
   }
 
   // Update EP struct from hardware state

From 79f1f4e171393397f25e884792ecc33b2480e050 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 8 Dec 2021 11:17:05 +0000
Subject: [PATCH 0731/2085] Revert "Merge in upstream changes"

This reverts commit fa06bd01c97a3a14215ea145764c09aecaa0dd79.
---
 .vscode/c_cpp_properties.json |  41 --------
 .vscode/launch.json           |  32 -------
 .vscode/settings.json         |  17 ----
 .vscode/tasks.json            | 176 ----------------------------------
 examples/make.mk              |   3 +-
 examples/rules.mk             |   4 +-
 6 files changed, 3 insertions(+), 270 deletions(-)
 delete mode 100644 .vscode/c_cpp_properties.json
 delete mode 100644 .vscode/launch.json
 delete mode 100644 .vscode/settings.json
 delete mode 100644 .vscode/tasks.json

diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json
deleted file mode 100644
index 28d4718b2..000000000
--- a/.vscode/c_cpp_properties.json
+++ /dev/null
@@ -1,41 +0,0 @@
-{
-    "configurations": [
-        {
-            "name": "FT900",
-            "includePath": [
-                // Toolchain installed FT90X SDK.
-                "C:/Program Files (x86)/Bridgetek/FT9xx Toolchain/Toolchain/hardware/include",
-                // Submodule for FT90X SDK.
-                //"${workspaceFolder}/hw/mcu/bridgetek/ft9xx/hardware/Source/include",
-                // Board headers.
-                "${workspaceFolder}/hw/bsp/brtmm90x/boards/mm900evxb",
-                // Hardware abstraction headers.
-                "${workspaceFolder}/hw/",
-                // Local header files.
-                ".",
-                "${workspaceFolder}/src",
-                // Example headers.
-                "${workspaceFolder}/examples/device/cdc_msc/src"
-                //"${workspaceFolder}/examples/host/hid_controller/src"
-            ],
-            "defines": [
-                "__FT900__", 
-                "BOARD=mm900evxb",
-                //"FT32_PORT", "FT32_PORT_HEAP=4", // For FreeRTOS
-                "CFG_TUSB_MCU=OPT_MCU_FT90X", // For FT90x
-                //"CFG_TUSB_RHPORT0_MODE=(OPT_MODE_HOST|OPT_MODE_HIGH_SPEED)",
-                //"CFG_TUSB_RHPORT1_MODE=(OPT_MODE_DEVICE|OPT_MODE_HIGH_SPEED)",
-                //"BOARD_DEVICE_RHPORT_NUM=1", 
-                //"BOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED",
-                "CFG_TUSB_DEBUG=0"
-            ],
-            "windowsSdkVersion": "10.0.18362.0",
-            "compilerPath": "C:/Program Files (x86)/Bridgetek/FT9xx Toolchain/Toolchain/tools/bin/ft32-elf-gcc",
-            "cStandard": "c11",
-            "cppStandard": "c++11",
-            "intelliSenseMode": "windows-gcc-x64",
-            "configurationProvider": "ms-vscode.makefile-tools"
-        }
-    ],
-    "version": 4
-}
\ No newline at end of file
diff --git a/.vscode/launch.json b/.vscode/launch.json
deleted file mode 100644
index 7aa6e0616..000000000
--- a/.vscode/launch.json
+++ /dev/null
@@ -1,32 +0,0 @@
-{
-    // Use IntelliSense to learn about possible attributes.
-    // Hover to view descriptions of existing attributes.
-    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
-    "version": "0.2.0",
-    "configurations": [
-        {
-            "name": "Debug TinyUSB CDC_MSC",
-            "type": "cppdbg",
-            "MIMode": "gdb",
-            "request": "launch",
-            "cwd": "${workspaceFolder}", 
-            "program": "examples/device/program.elf",
-            //"program": "examples/device/cdc_msc/_build/mm900ev1b/cdc_msc.elf",
-            "preLaunchTask": "Build and Program (Memory)",
-            "target": "localhost:9998",
-            "remote": true,
-            "gdbpath": "C:/Program Files (x86)/Bridgetek/FT9xx Toolchain/Toolchain/tools/bin/ft32-elf-gdb.exe",
-            "stopAtEntry": true,
-            "environment": [],
-            "console": "externalTerminal",
-            "miDebuggerPath": "C:/Program Files (x86)/Bridgetek/FT9xx Toolchain/Toolchain/tools/bin/ft32-elf-gdb.exe",
-            //"miDebuggerArgs": "-x lib\\FreeRTOS\\.gdbinit-FreeRTOS-helpers",
-            "miDebuggerServerAddress": "localhost:9998",
-            "launchCompleteCommand": "None",
-            "debugServerPath": "C:\\Users\\gordon.mcnab\\AppData\\Local\\Programs\\Python\\Python37\\python.exe",
-            "debugServerArgs": 
-                "\"C:/Program Files (x86)/Bridgetek/FT9xx Toolchain/Toolchain/utilities/gdb_bridge.py\" live pm",
-            //"rtos": "FreeRTOS",
-        }
-    ]
-}
diff --git a/.vscode/settings.json b/.vscode/settings.json
deleted file mode 100644
index b0aef0cf8..000000000
--- a/.vscode/settings.json
+++ /dev/null
@@ -1,17 +0,0 @@
-{
-    "files.associations": {
-        "tusb_option.h": "c",
-        "ft900.h": "c",
-        "ft900_usbd.h": "c",
-        "ft900_registers.h": "c",
-        "ft900_usbd_registers.h": "c",
-        "dcd.h": "c",
-        "stdint.h": "c",
-        "board.h": "c",
-        "ft900_ehci_registers.h": "c",
-        "stdint-gcc.h": "c",
-        "ft900_memctl.h": "c",
-        "stddef.h": "c"
-    },
-    "cmake.configureOnOpen": true
-}
\ No newline at end of file
diff --git a/.vscode/tasks.json b/.vscode/tasks.json
deleted file mode 100644
index 459351c4f..000000000
--- a/.vscode/tasks.json
+++ /dev/null
@@ -1,176 +0,0 @@
-{
-    "version": "2.0.0",
-
-    "options": {
-        "env": {
-            // Set this to the type of example.
-            // Choices can be "device" or "host".
-            "exampleType": "device",
-            // Set this to the name of the example.
-            // The name is the folder name  in the examples directory.
-            "exampleName": "cdc_msc",
-            // Set this to the name of the board to target.
-            "boardName": "mm900evxb"
-        }
-    },
-
-    "inputs": [
-        {
-          "type": "pickString",
-          "id": "pickExampleName",
-          "description": "Which example project do you want to use?",
-          "options": [
-            "board_test",
-            "cdc_msc",
-            "hid_boot_interface",
-            "hid_composite",
-
-          ],
-          "default": "board_test"
-        },
-        {
-          "type": "pickString",
-          "id": "pickBoardName",
-          "description": "Which board type do you want to use?",
-          "options": [
-              "mm900ev1b",
-              "mm900ev2b",
-              "mm900ev3b"
-          ],
-          "default": "mm900ev1b"
-        }
-    ],
-    
-    "tasks": [
-        {
-            "label": "test env",
-            "type": "shell",
-            "command": "echo",
-            "args": [
-                "$env:exampleName"
-            ],
-            "problemMatcher": []
-        },
-        {
-            "label": "Build and Program (Memory)",
-            "dependsOrder": "sequence",
-            "dependsOn": [
-                "Build Project",
-                "Program Project (Memory)"
-            ],
-            "type": "shell",
-            "options": {
-                "cwd": "${workspaceFolder}"
-            },
-            "command": "copy",
-            "args": [
-                "examples\\$env:exampleType\\$env:exampleName\\_build\\$env:boardName\\$env:exampleName.elf",
-                "examples\\$env:exampleType\\program.elf"
-            ],
-            "problemMatcher": {
-                "pattern": {
-                    "regexp": "^Error:\\s+(.*)$",
-                    "message": 1
-                }
-            }
-        },
-        {
-            "label": "Build Project",
-            "type": "shell",
-            "options": {
-                "cwd": "${workspaceFolder}"
-            },
-            "command": "make.exe",
-            "args": [
-                "-C",
-                "examples\\$env:exampleType\\$env:exampleName",
-                "BOARD=$env:boardName"
-            ],
-            "problemMatcher": [
-                "$gcc"
-            ],
-            "group": {
-                "kind": "build",
-                "isDefault": true
-            }
-        },
-        {
-            "label": "Rebuild Project",
-            "type": "shell",
-            "options": {
-                "cwd": "${workspaceFolder}"
-            },
-            "command": "make.exe",
-            "args": [
-                "-C",
-                "examples\\$env:exampleType\\$env:exampleName",
-                "BOARD=$env:boardName",
-                "-B"
-            ],
-            "problemMatcher": [
-                "$gcc"
-            ],
-            "group": "build"
-        },
-        {
-            "label": "Clean Project",
-            "type": "shell",
-            "options": {
-                "cwd": "${workspaceFolder}"
-            },
-            "command": "make.exe",
-            "args": [
-                "-C",
-                "examples\\$env:exampleType\\$env:exampleName",
-                "BOARD=$env:boardName",
-                "clean"
-            ],
-            "problemMatcher": [
-                "$gcc"
-            ],
-            "group": "build"
-        },
-        {
-            "label": "Program Project (Flash)",
-            "type": "shell",
-            "options": {
-                "cwd": "${workspaceFolder}"
-            },
-            "command": "C:\\Program Files (x86)\\Bridgetek\\FT9xx Toolchain\\Toolchain\\programmer\\dist\\FT900Prog.exe",
-            "args": [
-                "--loadflash",
-                "examples\\$env:exampleType\\$env:exampleName\\_build\\$env:boardName\\$env:exampleName.bin",
-                "--onewire",
-                "--noReset"
-            ],
-            "problemMatcher": {
-                "pattern": {
-                    "regexp": "^Error:\\s+(.*)$",
-                    "message": 1
-                }
-            },
-            "dependsOn": "${defaultBuildTask}"
-        },
-        {
-            "label": "Program Project (Memory)",
-            "type": "shell",
-            "options": {
-                "cwd": "${workspaceFolder}"
-            },
-            "command": "C:\\Program Files (x86)\\Bridgetek\\FT9xx Toolchain\\Toolchain\\programmer\\dist\\FT900Prog.exe",
-            "args": [
-                "--loadpm",
-                "examples\\$env:exampleType\\$env:exampleName\\_build\\$env:boardName\\$env:exampleName.bin",
-                "--onewire",
-                "--noReset"
-            ],
-            "problemMatcher": {
-                "pattern": {
-                    "regexp": "^Error:\\s+(.*)$",
-                    "message": 1
-                }
-            },
-            "dependsOn": "${defaultBuildTask}"
-        }
-    ],
-}
\ No newline at end of file
diff --git a/examples/make.mk b/examples/make.mk
index e1cd0af2a..793c40aa2 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -104,11 +104,10 @@ CFLAGS += \
   -Wmissing-format-attribute \
   -Wunreachable-code \
   -Wcast-align \
+  -Wcast-function-type \
   -Wcast-qual \
   -Wnull-dereference
 
-#  -Wcast-function-type \
-
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
   CFLAGS += -Og
diff --git a/examples/rules.mk b/examples/rules.mk
index a12a75d60..4cc35cb22 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -84,7 +84,7 @@ OBJ_DIRS = $(sort $(dir $(OBJ)))
 $(OBJ): | $(OBJ_DIRS)
 $(OBJ_DIRS):
 ifeq ($(CMDEXE),1)
-	-@$(MKDIR) $(subst /,\,$@)
+	@$(MKDIR) $(subst /,\,$@)
 else
 	@$(MKDIR) -p $@
 endif
@@ -207,7 +207,7 @@ debug-bmp: $(BUILD)/$(PROJECT).elf
 
 # Create binary directory
 $(BIN):
-	-@$(MKDIR) -p $@
+	@$(MKDIR) -p $@
 
 # Copy binaries .elf, .bin, .hex, .uf2 to BIN for upload
 # due to large size of combined artifacts, only uf2 is uploaded for now

From bcbcdf87de303a4db1724de2a813b80f13d7d906 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 8 Dec 2021 11:24:39 +0000
Subject: [PATCH 0732/2085] Fix spelling mistakes and verify endpoint
 numbering.

---
 examples/device/cdc_msc/src/usb_descriptors.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 3c3e9c891..09894cf1b 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -118,7 +118,7 @@ enum
   #define EPNUM_MSC_IN      0x84
 
 #elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
-  // FT9XX don't support a same endpoint number with different direction IN and OUT
+  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_NOTIF   0x81
   #define EPNUM_CDC_OUT     0x02

From 21fa7ea468cf34e6d775c92de580796d2c7eec4f Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 8 Dec 2021 13:56:23 +0000
Subject: [PATCH 0733/2085] Correct path for using the ft90x-sdk submodule
 (BRTSG-FOSS / ft90x-sdk). Default to ft90x-sdk instead of pre-built library.

---
 hw/bsp/brtmm90x/family.mk | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index d47f4820c..3933f15cc 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -3,23 +3,24 @@ CROSS_COMPILE = ft32-elf-
 SKIP_NANOLIB = 1
 
 # Set to use FT90X prebuilt libraries.
-FT90X_PREBUILT_LIBS = 1
+FT90X_PREBUILT_LIBS = 0
 ifeq ($(FT90X_PREBUILT_LIBS),1)
 # If the FT90X toolchain is installed on Windows systems then the SDK 
 # include files and prebuilt libraries are at: %FT90X_TOOLCHAIN%/hardware
 FT9XX_SDK = $(FT90X_TOOLCHAIN)/hardware
+INC += $(FT9XX_SDK)/include
 else
 # The submodule BRTSG-FOSS/ft90x-sdk contains header files and source
 # code for the Bridgetek SDK. This can be used instead of the prebuilt
 # library.
-DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/hardware
+DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/ft90x-sdk
 # The SDK can be used to load specific files from the Bridgetek SDK.
-FT9XX_SDK = hw/mcu/bridgetek/ft9xx/hardware/Source
+FT9XX_SDK = hw/mcu/bridgetek/ft9xx/ft90x-sdk/Source
+INC += $(TOP)/$(FT9XX_SDK)/include
 endif
 
 # Add include files which are within the TinyUSB directory structure.
 INC += \
-	$(TOP)/hw/mcu/bridgetek/ft9xx/hardware/Source/include \
 	$(TOP)/$(BOARD_PATH)
 
 # Add required C Compiler flags for FT90X.

From 59dcf2062f77137d0246944ed2279d30a4907627 Mon Sep 17 00:00:00 2001
From: Greg Steiert <greg.steiert@nxp.com>
Date: Wed, 8 Dec 2021 14:31:44 -0800
Subject: [PATCH 0734/2085] adding support for KUIIC board

---
 hw/bsp/kuiic/K32L2B31xxxxA_flash.ld | 217 ++++++++++++++++++++++++++++
 hw/bsp/kuiic/board.h                |  45 ++++++
 hw/bsp/kuiic/board.mk               |  49 +++++++
 hw/bsp/kuiic/kuiic.c                | 203 ++++++++++++++++++++++++++
 4 files changed, 514 insertions(+)
 create mode 100644 hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
 create mode 100644 hw/bsp/kuiic/board.h
 create mode 100644 hw/bsp/kuiic/board.mk
 create mode 100644 hw/bsp/kuiic/kuiic.c

diff --git a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
new file mode 100644
index 000000000..5420ffc00
--- /dev/null
+++ b/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
@@ -0,0 +1,217 @@
+/*
+** ###################################################################
+**     Processors:          K32L2B31VFM0A
+**                          K32L2B31VFT0A
+**                          K32L2B31VLH0A
+**                          K32L2B31VMP0A
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    K32L2B3xRM, Rev.0, July 2019
+**     Version:             rev. 1.0, 2019-07-30
+**     Build:               b190930
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00008000, LENGTH = 0x00000200
+  m_flash_config        (RX)  : ORIGIN = 0x00008400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00008410, LENGTH = 0x00037BF0
+  m_data                (RW)  : ORIGIN = 0x1FFFE000, LENGTH = 0x00008000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  /* reserve MTB memory at the beginning of m_data */
+  .mtb : /* MTB buffer address as defined by the hardware */
+  {
+    . = ALIGN(8);
+    _mtb_start = .;
+    KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+    . = ALIGN(8);
+    _mtb_end = .;
+  } > m_data
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/hw/bsp/kuiic/board.h b/hw/bsp/kuiic/board.h
new file mode 100644
index 000000000..78ad83a2e
--- /dev/null
+++ b/hw/bsp/kuiic/board.h
@@ -0,0 +1,45 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "fsl_device_registers.h"
+
+// LED
+#define LED_PIN_CLOCK         kCLOCK_PortA
+#define LED_GPIO              GPIOA
+#define LED_PORT              PORTA
+#define LED_PIN               2
+#define LED_STATE_ON          1
+
+// UART
+#define UART_PORT             LPUART1
+#define UART_PIN_RX           3u
+#define UART_PIN_TX           0u
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/kuiic/board.mk b/hw/bsp/kuiic/board.mk
new file mode 100644
index 000000000..3a46728f1
--- /dev/null
+++ b/hw/bsp/kuiic/board.mk
@@ -0,0 +1,49 @@
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+DEPS_SUBMODULES += $(SDK_DIR)
+
+CFLAGS += \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0plus \
+  -DCPU_K32L2B31VLH0A \
+  -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter
+
+MCU_DIR = $(SDK_DIR)/devices/K32L2B31A
+
+# All source paths should be relative to the top level.
+LD_FILE = /hw/bsp/$(BOARD)/K32L2B31xxxxA_flash.ld
+
+SRC_C += \
+	src/portable/nxp/khci/dcd_khci.c \
+	$(MCU_DIR)/system_K32L2B31A.c \
+	$(MCU_DIR)/drivers/fsl_clock.c \
+	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
+
+INC += \
+	$(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(SDK_DIR)/CMSIS/Include \
+	$(TOP)/$(SDK_DIR)/drivers/smc \
+	$(TOP)/$(SDK_DIR)/drivers/common \
+	$(TOP)/$(SDK_DIR)/drivers/gpio \
+	$(TOP)/$(SDK_DIR)/drivers/port \
+	$(TOP)/$(SDK_DIR)/drivers/lpuart \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/drivers 
+
+SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM0
+
+# For flash-jlink target
+JLINK_DEVICE = MKL25Z128xxx4
+
+# For flash-pyocd target
+PYOCD_TARGET = K32L2B
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/kuiic/kuiic.c b/hw/bsp/kuiic/kuiic.c
new file mode 100644
index 000000000..737ef3f5c
--- /dev/null
+++ b/hw/bsp/kuiic/kuiic.c
@@ -0,0 +1,203 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ * Copyright (c) 2020, Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../board.h"
+#include "board.h"
+#include "fsl_smc.h"
+#include "fsl_gpio.h"
+#include "fsl_port.h"
+#include "fsl_clock.h"
+#include "fsl_lpuart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SIM_OSC32KSEL_LPO_CLK         3U        /*!< OSC32KSEL select: LPO clock */
+#define SOPT5_LPUART1RXSRC_LPUART_RX  0x00u     /*!<@brief LPUART1 Receive Data Source Select: LPUART_RX pin */
+#define SOPT5_LPUART1TXSRC_LPUART_TX  0x00u     /*!<@brief LPUART1 Transmit Data Source Select: LPUART_TX pin */
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
+    .outSrc          = kMCGLITE_ClkSrcHirc,  /* MCGOUTCLK source is HIRC */
+    .irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+    .ircs            = kMCGLITE_Lirc8M,      /* Slow internal reference (LIRC) 8 MHz clock selected */
+    .fcrdiv          = kMCGLITE_LircDivBy1,  /* Low-frequency Internal Reference Clock Divider: divided by 1 */
+    .lircDiv2        = kMCGLITE_LircDivBy1,  /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
+    .hircEnableInNotHircMode = true,         /* HIRC source is enabled */
+};
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+    .er32kSrc = SIM_OSC32KSEL_LPO_CLK,       /* OSC32KSEL select: LPO clock */
+    .clkdiv1  = 0x10000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
+};
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to HIRC mode. */
+    CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void board_init(void)
+{
+  /* Enable port clocks for GPIO pins */
+  CLOCK_EnableClock(kCLOCK_PortA);
+  CLOCK_EnableClock(kCLOCK_PortB);
+  CLOCK_EnableClock(kCLOCK_PortC);
+  CLOCK_EnableClock(kCLOCK_PortD);
+  CLOCK_EnableClock(kCLOCK_PortE);
+
+  
+  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 1 };
+  GPIO_PinInit(GPIOA, 1U, &led_config);
+  PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio);  
+  led_config.outputLogic = 0;
+  GPIO_PinInit(GPIOA, 2U, &led_config);
+  PORT_SetPinMux(PORTA, 2U, kPORT_MuxAsGpio);
+
+#ifdef BUTTON_PIN
+  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
+  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
+  const port_pin_config_t BUTTON_CFG = {
+    kPORT_PullUp, 
+    kPORT_FastSlewRate, 
+    kPORT_PassiveFilterDisable, 
+    kPORT_LowDriveStrength, 
+    kPORT_MuxAsGpio
+  };
+  PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
+#endif
+
+  /* PORTC3 is configured as LPUART0_RX */
+  PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3);
+  /* PORTA2 (pin 24) is configured as LPUART0_TX */
+  PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
+  
+  SIM->SOPT5 = ((SIM->SOPT5 &
+               /* Mask bits to zero which are setting */
+               (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK)))
+               /* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
+               | SIM_SOPT5_LPUART1TXSRC(SOPT5_LPUART1TXSRC_LPUART_TX)
+               /* LPUART0 Receive Data Source Select: LPUART_RX pin. */
+               | SIM_SOPT5_LPUART1RXSRC(SOPT5_LPUART1RXSRC_LPUART_RX));
+
+  BOARD_BootClockRUN();
+  SystemCoreClockUpdate();
+  CLOCK_SetLpuart1Clock(1);
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  lpuart_config_t uart_config;
+  LPUART_GetDefaultConfig(&uart_config);
+  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
+  uart_config.enableTx = true;
+  uart_config.enableRx = true;
+  LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_McgIrc48MClk));
+
+  // USB
+  CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcIrc48M, 48000000U);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  if (state) {
+    LED_GPIO->PDDR |= GPIO_FIT_REG((1UL << LED_PIN));
+  } else {
+    LED_GPIO->PDDR &= GPIO_FIT_REG(~(1UL << LED_PIN));
+  }
+//  GPIO_PinWrite(GPIOA, 1, state ? LED_STATE_ON : (1-LED_STATE_ON) );
+//  GPIO_PinWrite(GPIOA, 2, state ? (1-LED_STATE_ON) : LED_STATE_ON );
+}
+
+uint32_t board_button_read(void)
+{
+#ifdef BUTTON_PIN
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+#else
+  return 0;
+#endif
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  LPUART_ReadBlocking(UART_PORT, buf, len);
+  return len;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif

From e72a6e90b99bcb4318bed67fbfd5bd5fc52a1d48 Mon Sep 17 00:00:00 2001
From: Greg Steiert <greg.steiert@nxp.com>
Date: Wed, 8 Dec 2021 15:24:14 -0800
Subject: [PATCH 0735/2085] added support for building uf2 file

---
 hw/bsp/kuiic/board.mk | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/kuiic/board.mk b/hw/bsp/kuiic/board.mk
index 3a46728f1..39e9d9deb 100644
--- a/hw/bsp/kuiic/board.mk
+++ b/hw/bsp/kuiic/board.mk
@@ -1,5 +1,8 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+DEPS_SUBMODULES += $(SDK_DIR) tools/uf2
+
+# This board uses TinyUF2 for updates
+UF2_FAMILY_ID = 0x7f83e793
 
 CFLAGS += \
   -mthumb \

From 51acc3e1b90f42ebb80881a143fe36a4ce45821c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 9 Dec 2021 12:42:08 +0700
Subject: [PATCH 0736/2085] update g4 bsp

---
 examples/device/hid_generic_inout/hid_test.py | 32 ++++++++++---------
 hw/bsp/stm32g4/boards/stm32g474nucleo/board.h | 28 ++++++++--------
 .../stm32g4/boards/stm32g474nucleo/board.mk   |  4 ++-
 3 files changed, 34 insertions(+), 30 deletions(-)

diff --git a/examples/device/hid_generic_inout/hid_test.py b/examples/device/hid_generic_inout/hid_test.py
index a42930fb5..21fd3f421 100644
--- a/examples/device/hid_generic_inout/hid_test.py
+++ b/examples/device/hid_generic_inout/hid_test.py
@@ -1,20 +1,22 @@
 # Install python3 HID package https://pypi.org/project/hid/
 import hid
 
-USB_VID = 0xcafe
+# default is TinyUSB (0xcafe), Adafruit (0x239a), RaspberryPi (0x2e8a), Espressif (0x303a) VID
+USB_VID = (0xcafe, 0x239a, 0x2e8a, 0x303a)
 
-print("Openning HID device with VID = 0x%X" % USB_VID)
+print("VID list: " + ", ".join('%02x' % v for v in USB_VID))
 
-for dict in hid.enumerate(USB_VID):
-    print(dict)
-    dev = hid.Device(dict['vendor_id'], dict['product_id'])
-    if dev:
-        while True:
-            # Get input from console and encode to UTF8 for array of chars.
-            # hid generic inout is single report therefore by HIDAPI requirement
-            # it must be preceeded with 0x00 as dummy reportID
-            str_out = b'\x00'
-            str_out += input("Send text to HID Device : ").encode('utf-8')
-            dev.write(str_out)
-            str_in = dev.read(64)
-            print("Received from HID Device:", str_in, '\n')
+for vid in  USB_VID:
+    for dict in hid.enumerate(vid):
+        print(dict)
+        dev = hid.Device(dict['vendor_id'], dict['product_id'])
+        if dev:
+            while True:
+                # Get input from console and encode to UTF8 for array of chars.
+                # hid generic inout is single report therefore by HIDAPI requirement
+                # it must be preceeded with 0x00 as dummy reportID
+                str_out = b'\x00'
+                str_out += input("Send text to HID Device : ").encode('utf-8')
+                dev.write(str_out)
+                str_in = dev.read(64)
+                print("Received from HID Device:", str_in, '\n')
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
index e4088023d..998100cf3 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
@@ -67,28 +67,28 @@ static inline void board_clock_init(void)
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
 
   // Initializes the CPU, AHB and APB busses clocks
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
-  RCC_OscInitStruct.PLL.PLLN = 50;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
-  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState       = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM       = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN       = 50;
+  RCC_OscInitStruct.PLL.PLLP       = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ       = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR       = RCC_PLLR_DIV2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
   // Initializes the CPU, AHB and APB busses clocks
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
 
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+  PeriphClkInit.UsbClockSelection    = RCC_USBCLKSOURCE_HSI48;
   HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) ;
 
 #if 0 // TODO need to check if USB clock is enabled
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
index 1951fcba0..e41edd3b7 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
@@ -1,4 +1,6 @@
-CFLAGS += -DSTM32G474xx
+CFLAGS += \
+	-DSTM32G474xx \
+	-DHSE_VALUE=24000000
 
 LD_FILE = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
 

From 69bdd703c20e4a61892dc2ef217d14700b29dc46 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Dec 2021 17:53:38 +0700
Subject: [PATCH 0737/2085] update doc to include g4

---
 README.rst                   |  2 +-
 docs/reference/supported.rst | 20 +++++++++++++-------
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/README.rst b/README.rst
index a8ce9399c..03219db3f 100644
--- a/README.rst
+++ b/README.rst
@@ -50,7 +50,7 @@ The stack supports the following MCUs:
 - **Renesas:** RX63N, RX65N, RX72N
 - **Silabs:** EFM32GG
 - **Sony:** CXD56
-- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, L0, L1, L4, L4+
+- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G4, L0, L1, L4, L4+
 - **TI:** MSP430, MSP432E4, TM4C123
 - **ValentyUSB:** eptri
 
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index e3cb8c679..a63582dd4 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -82,6 +82,8 @@ Supported MCUs
 |              +-----------------------+--------+------+-----------+-------------------+--------------+
 |              | H7                    | ✔      |      | ✔         | dwc2              |              |
 |              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | G4                    | ✔      | ✖    | ✖         | stm32_fsdev       |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
 |              | L0, L1                | ✔      | ✖    | ✖         | stm32_fsdev       |              |
 |              +----+------------------+--------+------+-----------+-------------------+--------------+
 |              | L4 | 4x2, 4x3         | ✔      | ✖    | ✖         | stm32_fsdev       |              |
@@ -352,6 +354,17 @@ F7
 -  `STM32 F767zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f767zi.html>`__
 -  `STM32 F769i Discovery <https://www.st.com/en/evaluation-tools/32f769idiscovery.html>`__
 
+H7
+^^
+-  `STM32 H743zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-h743zi.html>`__
+-  `STM32 H743i Evaluation <https://www.st.com/en/evaluation-tools/stm32h743i-eval.html>`__
+-  `STM32 H745i Discovery <https://www.st.com/en/evaluation-tools/stm32h745i-disco.html>`__
+-  `Waveshare OpenH743I-C <https://www.waveshare.com/openh743i-c-standard.htm>`__
+
+G4
+^^
+-  `STM32 G474RE Nucleo <https://www.st.com/en/evaluation-tools/nucleo-g474re.html>`__
+
 L0
 ^^
 -  `STM32 L035c8 Discovery <https://www.st.com/en/evaluation-tools/32l0538discovery.html>`__
@@ -362,13 +375,6 @@ L4
 -  `STM32 L4P5zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html>`__
 -  `STM32 L4R5zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html>`__
 
-H7
-^^
--  `STM32 H743zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-h743zi.html>`__
--  `STM32 H743i Evaluation <https://www.st.com/en/evaluation-tools/stm32h743i-eval.html>`__
--  `STM32 H745i Discovery <https://www.st.com/en/evaluation-tools/stm32h745i-disco.html>`__
--  `Waveshare OpenH743I-C <https://www.waveshare.com/openh743i-c-standard.htm>`__
-
 TI
 --
 

From d097178ab06ce665972bc2f3222648784eba2f54 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Dec 2021 17:59:43 +0700
Subject: [PATCH 0738/2085] correct wiring note

---
 hw/bsp/stm32g4/boards/stm32g474nucleo/board.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
index 998100cf3..eab0bd5f0 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
@@ -32,8 +32,8 @@
 #endif
 
 // G474RE Nucleo does not has usb connection. We need to manually connect
-// - PA11 for D+, CN10.14
-// - PA12 for D-, CN10.12
+// - PA12 for D+, CN10.12
+// - PA11 for D-, CN10.14
 
 // LED
 #define LED_PORT              GPIOA

From 8d373b08879ac382c59dcbfb2d351d4af35e3d00 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 15 Dec 2021 12:23:58 +0000
Subject: [PATCH 0739/2085] Update midi_test endpoints and FT9xx code

---
 .../device/midi_test/src/usb_descriptors.c    | 14 ++--
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c      | 64 ++++++++++---------
 2 files changed, 44 insertions(+), 34 deletions(-)

diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c
index bd5a0eeab..8444237c6 100644
--- a/examples/device/midi_test/src/usb_descriptors.c
+++ b/examples/device/midi_test/src/usb_descriptors.c
@@ -83,9 +83,15 @@ enum
 #if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
-  #define EPNUM_MIDI   0x02
+  #define EPNUM_MIDI_OUT   0x02
+  #define EPNUM_MIDI_IN   0x02
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+  // On Bridgetek FT9xx endpoint numbers must be unique...
+  #define EPNUM_MIDI_OUT   0x02
+  #define EPNUM_MIDI_IN   0x03
 #else
-  #define EPNUM_MIDI   0x01
+  #define EPNUM_MIDI_OUT   0x01
+  #define EPNUM_MIDI_IN   0x01
 #endif
 
 uint8_t const desc_fs_configuration[] =
@@ -94,7 +100,7 @@ uint8_t const desc_fs_configuration[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP Out & EP In address, EP size
-  TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI, 0x80 | EPNUM_MIDI, 64)
+  TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI_OUT, (0x80 | EPNUM_MIDI_IN), 64)
 };
 
 #if TUD_OPT_HIGH_SPEED
@@ -104,7 +110,7 @@ uint8_t const desc_hs_configuration[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP Out & EP In address, EP size
-  TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI, 0x80 | EPNUM_MIDI, 512)
+  TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI_OUT, (0x80 | EPNUM_MIDI_IN), 512)
 };
 #endif
 
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index aa45aa1dd..793d40f81 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -56,10 +56,10 @@ static uint8_t _ft90x_setup_packet[8];
 
 struct ft90x_xfer_state
 {
-  uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
-  int16_t total_size; // Total transfer size in bytes for this transfer.
-  int16_t remain_size; // Total remaining in transfer.
-  uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
+  volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
+  volatile int16_t total_size; // Total transfer size in bytes for this transfer.
+  volatile int16_t remain_size; // Total remaining in transfer.
+  volatile uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
 
   uint8_t type; // Endpoint type. Of type USBD_ENDPOINT_TYPE from endpoint descriptor.
   uint8_t dir; // Endpoint direction. TUSB_DIR_OUT or TUSB_DIR_IN. For control endpoint this is the current direction.
@@ -131,6 +131,7 @@ static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
   uint8_t end = 0;
   uint16_t ep_size = ep_xfer[ep_number].size;
   (void)ep_size;
+
   if ((xfer_bytes == 0) || (xfer_bytes < ep_size))
   {
     end = 1;
@@ -186,39 +187,21 @@ static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
   return xfer_bytes;
 }
 
-// Reset all endpoints to a default state. 
-// Control endpoint enabled and ready. All others disabled.
+// Reset all non-control endpoints to a default state. 
+// Control endpoint is always enabled and ready. All others disabled.
 static void _ft90x_reset_edpts(void)
 {
   // Disable all endpoints and remove configuration values.
-    // Clear settings.
-  tu_memclr(ep_xfer, sizeof(ep_xfer));
-  for (int i = 0; i < USBD_MAX_ENDPOINT_COUNT; i++)
+  for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++)
   {
+    // Clear settings.
+    tu_memclr(&ep_xfer[i], sizeof(struct ft90x_xfer_state));
     // Disable hardware.
     USBD_EP_CR_REG(i) = 0;
   }
   
-  // Setup the control endpoint only.
-#if CFG_TUD_ENDPOINT0_SIZE == 64
-  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_64 << BIT_USBD_EP0_MAX_SIZE);
-#elif CFG_TUD_ENDPOINT0_SIZE == 32
-  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_32 << BIT_USBD_EP0_MAX_SIZE);
-#elif CFG_TUD_ENDPOINT0_SIZE == 16
-  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_16 << BIT_USBD_EP0_MAX_SIZE);
-#elif CFG_TUD_ENDPOINT0_SIZE == 8
-  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_8 << BIT_USBD_EP0_MAX_SIZE);
-#else
-#error "CFG_TUD_ENDPOINT0_SIZE must be defined with a value of 8, 16, 32 or 64."
-#endif
-  // Configure the control endpoint.
-  ep_xfer[USBD_EP_0].size = CFG_TUD_ENDPOINT0_SIZE;
-  ep_xfer[USBD_EP_0].type = TUSB_XFER_CONTROL;
-
   // Enable interrupts from USB device control.
   USBD_REG(cmie) = MASK_USBD_CMIE_ALL;
-  // Enable interrupts on EP0.
-  USBD_REG(epie) = (MASK_USBD_EPIE_EP0IE);
 }
 
 // Enable or disable the USB PHY.
@@ -297,12 +280,13 @@ static void _dcd_ft90x_detach(void)
   SYS->MSC0CFG = SYS->MSC0CFG & (~MASK_SYS_MSC0CFG_USB_VBUS_EN);
 #endif
   CRITICAL_SECTION_BEGIN
+  // Disable interrupts from USB.
   USBD_REG(epie) = 0;
   USBD_REG(cmie) = 0;
+  // Turn off the device enable bit.
+  USBD_REG(fctrl) = 0;
   CRITICAL_SECTION_END;
 
-  // Disable the USB function.
-  USBD_REG(fctrl) = 0;
   delayms(1);
 
   // Disable USB PHY
@@ -628,8 +612,28 @@ void dcd_connect(uint8_t rhport)
     // Determine bus speed and signal speed to tusb.
     _ft90x_usb_speed();
   }
-  CRITICAL_SECTION_END;
   
+  // Setup the control endpoint only.
+#if CFG_TUD_ENDPOINT0_SIZE == 64
+  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_64 << BIT_USBD_EP0_MAX_SIZE);
+#elif CFG_TUD_ENDPOINT0_SIZE == 32
+  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_32 << BIT_USBD_EP0_MAX_SIZE);
+#elif CFG_TUD_ENDPOINT0_SIZE == 16
+  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_16 << BIT_USBD_EP0_MAX_SIZE);
+#elif CFG_TUD_ENDPOINT0_SIZE == 8
+  USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_8 << BIT_USBD_EP0_MAX_SIZE);
+#else
+#error "CFG_TUD_ENDPOINT0_SIZE must be defined with a value of 8, 16, 32 or 64."
+#endif
+  CRITICAL_SECTION_END;
+
+  // Configure the control endpoint.
+  ep_xfer[USBD_EP_0].size = CFG_TUD_ENDPOINT0_SIZE;
+  ep_xfer[USBD_EP_0].type = TUSB_XFER_CONTROL;
+
+  // Enable interrupts on EP0.
+  USBD_REG(epie) = (MASK_USBD_EPIE_EP0IE);
+
   // Restore default endpoint state.
   _ft90x_reset_edpts();
 }

From 469ecdd28c0968fc15fe1d69b943d325d9b89d67 Mon Sep 17 00:00:00 2001
From: Greg Steiert <greg.steiert@nxp.com>
Date: Wed, 15 Dec 2021 14:18:27 -0800
Subject: [PATCH 0740/2085] added KUIIC to supported boards list

---
 docs/reference/supported.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index a63582dd4..b8f3ac30d 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -245,6 +245,7 @@ Kinetis
 
 -  `Freedom FRDM-KL25Z <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z>`__
 -  `Freedom FRDM-K32L2B3 <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3>`__
+-  `KUIIC <https://github.com/nxf58843/kuiic>`__
 
 LPC 11-13-15
 ^^^^^^^^^^^^

From 9b2e78c91555f3e50baaf0df30ab18927a65cb65 Mon Sep 17 00:00:00 2001
From: Matt Johnston <matt@codeconstruct.com.au>
Date: Mon, 20 Dec 2021 15:43:16 +0800
Subject: [PATCH 0741/2085] samd21: make uart_init() static

Avoids a linker conflict if programs are using the same function name.
---
 hw/bsp/samd21/family.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index cead582e9..494dc393a 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -47,7 +47,7 @@ void USB_Handler(void)
 //--------------------------------------------------------------------+
 // UART support
 //--------------------------------------------------------------------+
-void uart_init(void);
+static void uart_init(void);
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
@@ -152,7 +152,7 @@ uint32_t board_button_read(void)
 #define BOARD_SERCOM2(n)  SERCOM ## n
 #define BOARD_SERCOM(n) BOARD_SERCOM2(n)
 
-void uart_init(void)
+static void uart_init(void)
 {
 #if UART_SERCOM == 0
   gpio_set_pin_function(PIN_PA06, PINMUX_PA06D_SERCOM0_PAD2);
@@ -217,7 +217,7 @@ int board_uart_write(void const * buf, int len)
 }
 
 #else // ! defined(UART_SERCOM)
-void uart_init(void)
+static void uart_init(void)
 {
 
 }

From 2ab3988d9fd7e5de6c556752709c3519877bdf7b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 20 Dec 2021 23:54:28 +0700
Subject: [PATCH 0742/2085] add s3 devkitm

---
 .../boards/espressif_addax_1/board.cmake      | 10 -----
 .../boards/espressif_s3_devkitm/board.cmake   |  7 +++
 .../boards/espressif_s3_devkitm/board.h       | 43 +++++++++++++++++++
 3 files changed, 50 insertions(+), 10 deletions(-)
 create mode 100644 hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
 create mode 100644 hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h

diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake b/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
index 60f7d19ca..8996ff9dc 100644
--- a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
+++ b/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
@@ -1,16 +1,6 @@
 # Apply board specific content here
 target_include_directories(${COMPONENT_LIB} PRIVATE .)
 
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s3")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s3" FORCE)
-
 target_compile_options(${COMPONENT_TARGET} PUBLIC
   "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
   "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
new file mode 100644
index 000000000..8996ff9dc
--- /dev/null
+++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
@@ -0,0 +1,7 @@
+# Apply board specific content here
+target_include_directories(${COMPONENT_LIB} PRIVATE .)
+
+target_compile_options(${COMPONENT_TARGET} PUBLIC
+  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
+  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
+)
\ No newline at end of file
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h
new file mode 100644
index 000000000..c7940c56e
--- /dev/null
+++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h
@@ -0,0 +1,43 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          48
+
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */

From a4426794594da99093ea1dedf1925f8c22d61e69 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 20 Dec 2021 23:55:04 +0700
Subject: [PATCH 0743/2085] change ci to s3 to espressif_s3_devkitm

---
 .github/workflows/build_esp.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 57dbf33e3..cc56a8b62 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -18,7 +18,7 @@ jobs:
         # ESP32-S2
         - 'espressif_saola_1'
         # ESP32-S3
-        #- 'espressif_addax_1'
+        - 'espressif_s3_devkitm'
         # S3 compile error with "dangerous relocation: call8: call target out of range: memcpy"
 
     steps:

From 63310d72e189d7a6b3424b2c8d2cab9b2189cd6c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 21 Dec 2021 00:04:50 +0700
Subject: [PATCH 0744/2085] skip ci for s3

---
 .github/workflows/build_esp.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index cc56a8b62..1ed76ef4d 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -18,7 +18,7 @@ jobs:
         # ESP32-S2
         - 'espressif_saola_1'
         # ESP32-S3
-        - 'espressif_s3_devkitm'
+        #- 'espressif_s3_devkitm'
         # S3 compile error with "dangerous relocation: call8: call target out of range: memcpy"
 
     steps:

From 311248c8b0976ff4634206dbad5850996e6d3c05 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 21 Dec 2021 00:10:38 +0700
Subject: [PATCH 0745/2085] add s3 devkitc

---
 .../boards/espressif_s3_devkitc/board.cmake   |  7 +++
 .../boards/espressif_s3_devkitc/board.h       | 43 +++++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
 create mode 100644 hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h

diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
new file mode 100644
index 000000000..8996ff9dc
--- /dev/null
+++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
@@ -0,0 +1,7 @@
+# Apply board specific content here
+target_include_directories(${COMPONENT_LIB} PRIVATE .)
+
+target_compile_options(${COMPONENT_TARGET} PUBLIC
+  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
+  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
+)
\ No newline at end of file
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h
new file mode 100644
index 000000000..c7940c56e
--- /dev/null
+++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h
@@ -0,0 +1,43 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define NEOPIXEL_PIN          48
+
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */

From 6de423606fc9d512efb830b198c76f095a182a1c Mon Sep 17 00:00:00 2001
From: Alex Voinea <voinea.dragos.alexandru@gmail.com>
Date: Tue, 21 Dec 2021 18:24:05 +0100
Subject: [PATCH 0746/2085] nucleo-f439zi support

---
 docs/reference/supported.rst                  |   1 +
 .../stm32f439nucleo/STM32F439ZITX_FLASH.ld    | 206 ++++++++
 hw/bsp/stm32f4/boards/stm32f439nucleo/board.h | 108 ++++
 .../stm32f4/boards/stm32f439nucleo/board.mk   |  11 +
 .../stm32f439nucleo/stm32f4xx_hal_conf.h      | 486 ++++++++++++++++++
 5 files changed, 812 insertions(+)
 create mode 100644 hw/bsp/stm32f4/boards/stm32f439nucleo/STM32F439ZITX_FLASH.ld
 create mode 100644 hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
 create mode 100644 hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
 create mode 100644 hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index b8f3ac30d..4dd172dbe 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -344,6 +344,7 @@ F4
 -  `STM32 F411ve Discovery <https://www.st.com/en/evaluation-tools/32f411ediscovery.html>`__
 -  `STM32 F412zg Discovery <https://www.st.com/en/evaluation-tools/32f412gdiscovery.html>`__
 -  `STM32 F412zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f412zg.html>`__
+-  `STM32 F439zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f439zi.html>`__
 
 F7
 ^^
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/STM32F439ZITX_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f439nucleo/STM32F439ZITX_FLASH.ld
new file mode 100644
index 000000000..2dc277c77
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/STM32F439ZITX_FLASH.ld
@@ -0,0 +1,206 @@
+/*
+******************************************************************************
+**
+** @file        : LinkerScript.ld
+**
+** @author      : Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for NUCLEO-F439ZI Board embedding STM32F439ZITx Device from stm32f4 series
+**                      2048Kbytes FLASH
+**                      64Kbytes CCMRAM
+**                      192Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  CCMRAM    (xrw)    : ORIGIN = 0x10000000,   LENGTH = 64K
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 192K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  _siccmram = LOADADDR(.ccmram);
+
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
+  * If initialized variables will be placed in this section,
+  * the startup code needs to be modified to copy the init-values.
+  */
+  .ccmram :
+  {
+    . = ALIGN(4);
+    _sccmram = .;       /* create a global symbol at ccmram start */
+    *(.ccmram)
+    *(.ccmram*)
+
+    . = ALIGN(4);
+    _eccmram = .;       /* create a global symbol at ccmram end */
+  } >CCMRAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
new file mode 100644
index 000000000..e5a822426
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h
@@ -0,0 +1,108 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_14
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART3
+#define UART_GPIO_PORT        GPIOD
+#define UART_GPIO_AF          GPIO_AF7_USART3
+#define UART_TX_PIN           GPIO_PIN_8
+#define UART_RX_PIN           GPIO_PIN_9
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* Enable Power Control clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* The voltage scaling allows optimizing the power consumption when the
+   * device is clocked below the maximum system frequency, to update the
+   * voltage scaling value regarding system frequency refer to product
+   * datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
+  RCC_OscInitStruct.PLL.PLLN = 336;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+   * clocks dividers */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+                                RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+
+  // Enable clocks for LED, Button, Uart
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_USART3_CLK_ENABLE();
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
new file mode 100644
index 000000000..b7b36a8a6
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += -DSTM32F439xx
+
+LD_FILE = $(BOARD_PATH)/STM32F439ZITX_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f439xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f439zi
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h
new file mode 100644
index 000000000..a2c11d717
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h
@@ -0,0 +1,486 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED         
+/* #define HAL_ADC_MODULE_ENABLED      */
+/* #define HAL_CAN_MODULE_ENABLED      */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
+/* #define HAL_CRC_MODULE_ENABLED      */ 
+/* #define HAL_CEC_MODULE_ENABLED      */ 
+/* #define HAL_CRYP_MODULE_ENABLED     */ 
+/* #define HAL_DAC_MODULE_ENABLED      */ 
+/* #define HAL_DCMI_MODULE_ENABLED     */ 
+#define HAL_DMA_MODULE_ENABLED 
+/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_ETH_MODULE_ENABLED      */
+#define HAL_FLASH_MODULE_ENABLED 
+/* #define HAL_NAND_MODULE_ENABLED     */
+/* #define HAL_NOR_MODULE_ENABLED      */
+/* #define HAL_PCCARD_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED     */
+/* #define HAL_SDRAM_MODULE_ENABLED    */
+/* #define HAL_HASH_MODULE_ENABLED     */  
+#define HAL_GPIO_MODULE_ENABLED
+/* #define HAL_EXTI_MODULE_ENABLED     */
+/* #define HAL_I2C_MODULE_ENABLED      */
+/* #define HAL_SMBUS_MODULE_ENABLED    */
+/* #define HAL_I2S_MODULE_ENABLED      */
+/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_LTDC_MODULE_ENABLED     */
+/* #define HAL_DSI_MODULE_ENABLED      */
+#define HAL_PWR_MODULE_ENABLED
+/* #define HAL_QSPI_MODULE_ENABLED     */
+#define HAL_RCC_MODULE_ENABLED      
+/* #define HAL_RNG_MODULE_ENABLED      */
+/* #define HAL_RTC_MODULE_ENABLED      */
+/* #define HAL_SAI_MODULE_ENABLED      */
+/* #define HAL_SD_MODULE_ENABLED       */
+// #define HAL_SPI_MODULE_ENABLED
+/* #define HAL_TIM_MODULE_ENABLED      */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_IRDA_MODULE_ENABLED     */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED     */
+#define HAL_CORTEX_MODULE_ENABLED   
+/* #define HAL_PCD_MODULE_ENABLED      */
+/* #define HAL_HCD_MODULE_ENABLED      */
+/* #define HAL_FMPI2C_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED  */
+/* #define HAL_DFSDM_MODULE_ENABLED    */
+/* #define HAL_LPTIM_MODULE_ENABLED    */
+/* #define HAL_MMC_MODULE_ENABLED      */
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  (32000U)    
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* LAN8742A_PHY_ADDRESS Address*/
+#define LAN8742A_PHY_ADDRESS           0U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01U)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
+
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
+
+#define PHY_ISFR                        ((uint16_t)0x001DU)    /*!< PHY Interrupt Source Flag register Offset   */
+#define PHY_ISFR_INT4                   ((uint16_t)0x000BU)  /*!< PHY Link down inturrupt       */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h" 
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+  
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */      
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+   
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

From 103817b8b61115e67addfbd696b647f00e47cd30 Mon Sep 17 00:00:00 2001
From: Alex Voinea <voinea.dragos.alexandru@gmail.com>
Date: Wed, 22 Dec 2021 22:56:53 +0200
Subject: [PATCH 0747/2085] Fix typo

Oops. Made a typo in 6de423606fc9d512efb830b198c76f095a182a1c
---
 docs/reference/supported.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 4dd172dbe..1f7f395cb 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -344,7 +344,7 @@ F4
 -  `STM32 F411ve Discovery <https://www.st.com/en/evaluation-tools/32f411ediscovery.html>`__
 -  `STM32 F412zg Discovery <https://www.st.com/en/evaluation-tools/32f412gdiscovery.html>`__
 -  `STM32 F412zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f412zg.html>`__
--  `STM32 F439zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f439zi.html>`__
+-  `STM32 F439zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-f439zi.html>`__
 
 F7
 ^^

From 5c5ecea6f17aae16808533aa248671069cdc5fa5 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sun, 26 Dec 2021 22:19:07 +0100
Subject: [PATCH 0748/2085] build system: Changes for xc32 compiler

Three changes are needed to accommodate xc32 compiler build:
- optimized build flag other than -Os
   added CFLAGS_OPTIMIZED that defaults to -Os but can be overridden in boards
- build without -lnosys
   added LIBS_GCC with default libraries that can be changed in boards
- build without LD_FILE specification
   if LD_FILE is empty -Wl,-T options is not added to LDFLAGS
---
 examples/make.mk  |  4 +++-
 examples/rules.mk | 10 ++++++++--
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/examples/make.mk b/examples/make.mk
index 793c40aa2..bed46d02b 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -54,6 +54,8 @@ endif
 #-------------- Cross Compiler  ------------
 # Can be set by board, default to ARM GCC
 CROSS_COMPILE ?= arm-none-eabi-
+# Allow for -Os to be changed by board makefiles in case -Os is not allowed
+CFLAGS_OPTIMIZED ?= -Os
 
 CC = $(CROSS_COMPILE)gcc
 CXX = $(CROSS_COMPILE)g++
@@ -112,7 +114,7 @@ CFLAGS += \
 ifeq ($(DEBUG), 1)
   CFLAGS += -Og
 else
-  CFLAGS += -Os
+  CFLAGS += $(CFLAGS_OPTIMIZED)
 endif
 
 # Log level is mapped to TUSB DEBUG option
diff --git a/examples/rules.mk b/examples/rules.mk
index 4cc35cb22..95a9c9879 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -12,8 +12,10 @@ ifeq (,$(findstring $(FAMILY),esp32s2 esp32s3 rp2040))
 # Compiler Flags
 # ---------------------------------------
 
+LIBS_GCC ?= -lgcc -lm -lnosys
+
 # libc
-LIBS += -lgcc -lm -lnosys
+LIBS += $(LIBS_GCC)
 
 ifneq ($(BOARD), spresense)
 LIBS += -lc
@@ -49,7 +51,11 @@ ifeq ($(NO_LTO),1)
 CFLAGS := $(filter-out -flto,$(CFLAGS))
 endif
 
-LDFLAGS += $(CFLAGS) -Wl,-T,$(TOP)/$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections
+ifneq ($(LD_FILE),)
+LDFLAGS_LD_FILE ?= -Wl,-T,$(TOP)/$(LD_FILE)
+endif
+
+LDFLAGS += $(CFLAGS) $(LDFLAGS_LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections
 ifneq ($(SKIP_NANOLIB), 1)
 LDFLAGS += -specs=nosys.specs -specs=nano.specs
 endif

From 7a596b9e559e9c1b3305906eb9eb6ff707643f75 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sun, 26 Dec 2021 22:32:35 +0100
Subject: [PATCH 0749/2085] Fix Mynewt build for Microchip PIC32MZ devices.

definition of DEBUG breaks Microchip pic32 builds for Mynewt.
When MCU is not VALENTYUSB_EPTRI there is no need to have any
preprocessor definitions.
It may not look like a big deal but for xc32 builds, compiler
automatically force-includes some file that have structure with field name
DEBUG that result in build error in dcd_eptri.c when this file
is not really needed.

Moving DEBUG and LOG_USB few lines down should not break eptri builds.
---
 src/portable/valentyusb/eptri/dcd_eptri.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c
index 837d0c0ce..51fb8b401 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.c
+++ b/src/portable/valentyusb/eptri/dcd_eptri.c
@@ -24,6 +24,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI)
+
 #ifndef DEBUG
 #define DEBUG 0
 #endif
@@ -32,10 +36,6 @@
 #define LOG_USB 0
 #endif
 
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI)
-
 #include "device/dcd.h"
 #include "dcd_eptri.h"
 #include "csr.h"

From a76799b085ae157243ed002f8cf11a2d3eb0c6b9 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 27 Dec 2021 01:22:57 +0900
Subject: [PATCH 0750/2085] Add hcd for Renesas RX

---
 hw/bsp/rx/boards/rx65n_target/rx65n_target.c |   5 +
 hw/bsp/rx/family.mk                          |   1 +
 src/portable/renesas/usba/hcd_usba.c         | 869 +++++++++++++++++++
 3 files changed, 875 insertions(+)
 create mode 100644 src/portable/renesas/usba/hcd_usba.c

diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index ab86bc419..d658ee5dd 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -176,7 +176,12 @@ void INT_Excep_SCI5_RXI5(void)
 //--------------------------------------------------------------------+
 void INT_Excep_USB0_USBI0(void)
 {
+#if TUSB_OPT_HOST_ENABLED
+  tuh_int_handler(0);
+#endif
+#if TUSB_OPT_DEVICE_ENABLED
   tud_int_handler(0);
+#endif
 }
 
 void board_init(void)
diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk
index 5a8281718..aba05812d 100644
--- a/hw/bsp/rx/family.mk
+++ b/hw/bsp/rx/family.mk
@@ -15,6 +15,7 @@ CFLAGS += \
 
 SRC_C += \
 	src/portable/renesas/usba/dcd_usba.c \
+	src/portable/renesas/usba/hcd_usba.c \
 	$(MCU_DIR)/vects.c
 
 INC += \
diff --git a/src/portable/renesas/usba/hcd_usba.c b/src/portable/renesas/usba/hcd_usba.c
new file mode 100644
index 000000000..360a8d75f
--- /dev/null
+++ b/src/portable/renesas/usba/hcd_usba.c
@@ -0,0 +1,869 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Koji Kitayama
+ * Portions copyrighted (c) 2021 Roland Winistoerfer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_HOST_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
+                               CFG_TUSB_MCU == OPT_MCU_RX65X || \
+                               CFG_TUSB_MCU == OPT_MCU_RX72N )
+#include "host/hcd.h"
+#include "iodefine.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+#define SYSTEM_PRCR_PRC1     (1<<1)
+#define SYSTEM_PRCR_PRKEY    (0xA5u<<8)
+
+#define USB_DVSTCTR0_LOW     (1u)
+#define USB_DVSTCTR0_FULL    (2u)
+
+#define USB_FIFOSEL_TX       ((uint16_t)(1u<<5))
+#define USB_FIFOSEL_BIGEND   ((uint16_t)(1u<<8))
+#define USB_FIFOSEL_MBW_8    ((uint16_t)(0u<<10))
+#define USB_FIFOSEL_MBW_16   ((uint16_t)(1u<<10))
+#define USB_IS0_CTSQ         ((uint16_t)(7u))
+#define USB_IS0_DVSQ         ((uint16_t)(7u<<4))
+#define USB_IS0_VALID        ((uint16_t)(1u<<3))
+#define USB_IS0_BRDY         ((uint16_t)(1u<<8))
+#define USB_IS0_NRDY         ((uint16_t)(1u<<9))
+#define USB_IS0_BEMP         ((uint16_t)(1u<<10))
+#define USB_IS0_CTRT         ((uint16_t)(1u<<11))
+#define USB_IS0_DVST         ((uint16_t)(1u<<12))
+#define USB_IS0_SOFR         ((uint16_t)(1u<<13))
+#define USB_IS0_RESM         ((uint16_t)(1u<<14))
+#define USB_IS0_VBINT        ((uint16_t)(1u<<15))
+#define USB_IS1_SACK         ((uint16_t)(1u<<4))
+#define USB_IS1_SIGN         ((uint16_t)(1u<<5))
+#define USB_IS1_EOFERR       ((uint16_t)(1u<<6))
+#define USB_IS1_ATTCH        ((uint16_t)(1u<<11))
+#define USB_IS1_DTCH         ((uint16_t)(1u<<12))
+#define USB_IS1_BCHG         ((uint16_t)(1u<<14))
+#define USB_IS1_OVRCR        ((uint16_t)(1u<<15))
+
+#define USB_IS0_CTSQ_MSK     (7u)
+#define USB_IS0_CTSQ_SETUP   (1u)
+#define USB_IS0_DVSQ_DEF     (1u<<4)
+#define USB_IS0_DVSQ_ADDR    (2u<<4)
+#define USB_IS0_DVSQ_SUSP0   (4u<<4)
+#define USB_IS0_DVSQ_SUSP1   (5u<<4)
+#define USB_IS0_DVSQ_SUSP2   (6u<<4)
+#define USB_IS0_DVSQ_SUSP3   (7u<<4)
+
+#define USB_PIPECTR_PID_MSK   (3u)
+#define USB_PIPECTR_PID_NAK   (0u)
+#define USB_PIPECTR_PID_BUF   (1u)
+#define USB_PIPECTR_PID_STALL (2u)
+#define USB_PIPECTR_CCPL      (1u<<2)
+#define USB_PIPECTR_SQMON     (1u<<6)
+#define USB_PIPECTR_SQCLR     (1u<<8)
+#define USB_PIPECTR_ACLRM     (1u<<9)
+#define USB_PIPECTR_INBUFM    (1u<<14)
+#define USB_PIPECTR_BSTS      (1u<<15)
+
+#define USB_FIFOCTR_DTLN     (0x1FF)
+#define USB_FIFOCTR_FRDY     (1u<<13)
+#define USB_FIFOCTR_BCLR     (1u<<14)
+#define USB_FIFOCTR_BVAL     (1u<<15)
+
+#define USB_PIPECFG_SHTNAK   (1u<<7)
+#define USB_PIPECFG_DBLB     (1u<<9)
+#define USB_PIPECFG_BULK     (1u<<14)
+#define USB_PIPECFG_ISO      (3u<<14)
+#define USB_PIPECFG_INT      (2u<<14)
+
+#define USB_DEVADD_LOW       (1u<<6)
+#define USB_DEVADD_FULL      (2u<<6)
+
+#define FIFO_REQ_CLR         (1u)
+#define FIFO_COMPLETE        (1u<<1)
+
+// Start of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_PACKED_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
+
+typedef struct {
+  union {
+    struct {
+      uint16_t      : 8;
+      uint16_t TRCLR: 1;
+      uint16_t TRENB: 1;
+      uint16_t      : 0;
+    };
+    uint16_t TRE;
+  };
+  uint16_t TRN;
+} reg_pipetre_t;
+
+typedef union {
+  struct {
+    volatile uint16_t u8: 8;
+    volatile uint16_t   : 0;
+  };
+  volatile uint16_t u16;
+} hw_fifo_t;
+
+typedef struct TU_ATTR_PACKED
+{
+  void      *buf;      /* the start address of a transfer data buffer */
+  uint16_t  length;    /* the number of bytes in the buffer */
+  uint16_t  remaining; /* the number of bytes remaining in the buffer */
+  struct {
+    uint32_t ep  : 8;  /* an assigned endpoint address */
+    uint32_t dev : 8;  /* an assigned device address */
+    uint32_t ff  : 1;  /* `buf` is TU_FUFO or POD */
+    uint32_t     : 0;
+  };
+} pipe_state_t;
+
+TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
+TU_ATTR_BIT_FIELD_ORDER_END
+
+typedef struct
+{
+  bool         need_reset; /* The device has not been reset after connection. */
+  pipe_state_t pipe[10];
+  uint8_t ep[4][2][15];   /* a lookup table for a pipe index from an endpoint address */
+  uint8_t      ctl_mps[5]; /* EP0 max packet size for each device */
+} hcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+static hcd_data_t _hcd;
+
+static uint32_t disable_interrupt(void)
+{
+  uint32_t pswi;
+#if defined(__CCRX__)
+  pswi = get_psw() & 0x010000;
+  clrpsw_i();
+#else
+  pswi = __builtin_rx_mvfc(0) & 0x010000;
+  __builtin_rx_clrpsw('I');
+#endif
+  return pswi;
+}
+
+static void enable_interrupt(uint32_t pswi)
+{
+#if defined(__CCRX__)
+  set_psw(get_psw() | pswi);
+#else
+  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
+#endif
+}
+
+static unsigned find_pipe(unsigned xfer)
+{
+  switch (xfer) {
+  case TUSB_XFER_ISOCHRONOUS:
+    for (int i = 1; i <= 2; ++i) {
+      if (0 == _hcd.pipe[i].ep) return  i;
+    }
+    break;
+  case TUSB_XFER_BULK:
+    for (int i = 3; i <= 5; ++i) {
+      if (0 == _hcd.pipe[i].ep) return  i;
+    }
+    for (int i = 1; i <= 1; ++i) {
+      if (0 == _hcd.pipe[i].ep) return  i;
+    }
+    break;
+  case TUSB_XFER_INTERRUPT:
+    for (int i = 6; i <= 9; ++i) {
+      if (0 == _hcd.pipe[i].ep) return  i;
+    }
+    break;
+  default:
+    /* No support for control transfer */
+    break;
+  }
+  return 0;
+}
+
+static volatile uint16_t* get_pipectr(unsigned num)
+{
+  volatile uint16_t *ctr = NULL;
+  if (num) {
+    ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
+    ctr += num - 1;
+  } else {
+    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
+  }
+  return ctr;
+}
+
+static volatile reg_pipetre_t* get_pipetre(unsigned num)
+{
+  volatile reg_pipetre_t* tre = NULL;
+  if ((1 <= num) && (num <= 5)) {
+    tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD;
+    tre += num - 1;
+  }
+  return tre;
+}
+
+static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr)
+{
+  volatile uint16_t *ctr = NULL;
+  const unsigned epn   = tu_edpt_number(ep_addr);
+  if (epn) {
+    const unsigned dir_in = tu_edpt_dir(ep_addr);
+    const unsigned num    = _hcd.ep[dev_addr][dir_in][epn - 1];
+    if (num) {
+      ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
+      ctr += num - 1;
+    }
+  } else {
+    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
+  }
+  return ctr;
+}
+
+static unsigned edpt0_max_packet_size(void)
+{
+  return USB0.DCPMAXP.BIT.MXPS;
+}
+
+static unsigned edpt_max_packet_size(unsigned num)
+{
+  USB0.PIPESEL.WORD = num;
+  return USB0.PIPEMAXP.BIT.MXPS;
+}
+
+static inline void pipe_wait_for_ready(unsigned num)
+{
+  while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
+  while (!USB0.D0FIFOCTR.BIT.FRDY) ;
+}
+
+static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
+{
+  volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
+  uintptr_t addr = (uintptr_t)buf;
+  while (len >= 2) {
+    reg->u16 = *(const uint16_t *)addr;
+    addr += 2;
+    len  -= 2;
+  }
+  if (len) {
+    reg->u8 = *(const uint8_t *)addr;
+    ++addr;
+  }
+}
+
+static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
+{
+  uint8_t *p   = (uint8_t*)buf;
+  volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
+  while (len--) *p++ = *reg;
+}
+
+static bool pipe0_xfer_in(void)
+{
+  pipe_state_t *pipe = &_hcd.pipe[0];
+  const unsigned rem = pipe->remaining;
+
+  const unsigned mps = edpt0_max_packet_size();
+  const unsigned vld = USB0.CFIFOCTR.BIT.DTLN;
+  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
+  void          *buf = pipe->buf;
+  if (len) {
+    USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
+    pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
+  pipe->remaining = rem - len;
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return true;
+  }
+  USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
+  return false;
+}
+
+static bool pipe0_xfer_out(void)
+{
+  pipe_state_t *pipe = &_hcd.pipe[0];
+  const unsigned rem = pipe->remaining;
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+  const unsigned mps = edpt0_max_packet_size();
+  const unsigned len = TU_MIN(mps, rem);
+  void          *buf = pipe->buf;
+  if (len) {
+    pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+  pipe->remaining = rem - len;
+  return false;
+}
+
+static bool pipe_xfer_in(unsigned num)
+{
+  pipe_state_t  *pipe = &_hcd.pipe[num];
+  const unsigned rem  = pipe->remaining;
+
+  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
+  const unsigned mps  = edpt_max_packet_size(num);
+  pipe_wait_for_ready(num);
+  const unsigned vld  = USB0.D0FIFOCTR.BIT.DTLN;
+  const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
+  void          *buf  = pipe->buf;
+  if (len) {
+    pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
+  USB0.D0FIFOSEL.WORD = 0;
+  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  pipe->remaining     = rem - len;
+  if ((len < mps) || (rem == len)) {
+    pipe->buf = NULL;
+    return NULL != buf;
+  }
+  return false;
+}
+
+static bool pipe_xfer_out(unsigned num)
+{
+  pipe_state_t  *pipe = &_hcd.pipe[num];
+  const unsigned rem  = pipe->remaining;
+
+  if (!rem) {
+    pipe->buf = NULL;
+    return true;
+  }
+
+  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
+  const unsigned mps  = edpt_max_packet_size(num);
+  pipe_wait_for_ready(num);
+  const unsigned len  = TU_MIN(rem, mps);
+  void          *buf  = pipe->buf;
+  if (len) {
+    pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
+    pipe->buf = (uint8_t*)buf + len;
+  }
+  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+  USB0.D0FIFOSEL.WORD = 0;
+  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  pipe->remaining = rem - len;
+  return false;
+}
+
+static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+{
+  (void)dev_addr;
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+
+  /* configure fifo direction and access unit settings */
+  if (dir_in) { /* IN, a byte */
+    USB0.CFIFOSEL.WORD  = USB_FIFOSEL_MBW_8;
+    while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
+  } else {       /* OUT, 2 bytes */
+    USB0.CFIFOSEL.WORD  = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
+    while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
+  }
+
+  pipe_state_t *pipe = &_hcd.pipe[0];
+  pipe->ep        = ep_addr;
+  pipe->length    = buflen;
+  pipe->remaining = buflen;
+  if (buflen) {
+    pipe->buf     = buffer;
+    if (!dir_in) { /* OUT */
+      TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
+      pipe0_xfer_out();
+    }
+  } else { /* ZLP */
+    pipe->buf        = NULL;
+    if (!dir_in) { /* OUT */
+      USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+    }
+    if (dir_in == USB0.DCPCFG.BIT.DIR) {
+      TU_ASSERT(USB_PIPECTR_PID_NAK == USB0.DCPCTR.BIT.PID);
+      USB0.DCPCTR.BIT.SQSET = 1;
+      USB0.DCPCFG.BIT.DIR = dir_in ^ 1;
+    }
+  }
+  USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
+  return true;
+}
+
+static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+{
+  const unsigned epn    = tu_edpt_number(ep_addr);
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+  const unsigned num    = _hcd.ep[dev_addr - 1][dir_in][epn - 1];
+
+  TU_ASSERT(num);
+
+  pipe_state_t *pipe  = &_hcd.pipe[num];
+  pipe->buf       = buffer;
+  pipe->length    = buflen;
+  pipe->remaining = buflen;
+  if (!dir_in) { /* OUT */
+    if (buflen) {
+      pipe_xfer_out(num);
+    } else { /* ZLP */
+      USB0.D0FIFOSEL.WORD = num;
+      pipe_wait_for_ready(num);
+      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
+      USB0.D0FIFOSEL.WORD = 0;
+      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+    }
+  } else {
+    volatile uint16_t     *ctr = get_pipectr(num);
+    volatile reg_pipetre_t *pt = get_pipetre(num);
+    if (pt) {
+      const unsigned     mps = edpt_max_packet_size(num);
+      if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
+      pt->TRE   = TU_BIT(8);
+      pt->TRN   = (buflen + mps - 1) / mps;
+      pt->TRENB = 1;
+    }
+    *ctr = USB_PIPECTR_PID_BUF;
+  }
+  return true;
+}
+
+static bool process_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+{
+  const unsigned epn = tu_edpt_number(ep_addr);
+  if (0 == epn) {
+    return process_pipe0_xfer(dev_addr, ep_addr, buffer, buflen);
+  } else {
+    return process_pipe_xfer(dev_addr, ep_addr, buffer, buflen);
+  }
+}
+
+static void process_pipe0_bemp(uint8_t rhport)
+{
+  (void)rhport;
+  bool completed = pipe0_xfer_out();
+  if (completed) {
+    pipe_state_t *pipe = &_hcd.pipe[0];
+    hcd_event_xfer_complete(pipe->dev,
+                            tu_edpt_addr(0, TUSB_DIR_OUT),
+                            pipe->length - pipe->remaining,
+                            XFER_RESULT_SUCCESS, true);
+  }
+}
+
+static void process_pipe_nrdy(uint8_t rhport, unsigned num)
+{
+  (void)rhport;
+  unsigned result;
+  uint16_t volatile *ctr = get_pipectr(num);
+  // TU_LOG1("NRDY %d %x\n", num, *ctr);
+  switch (*ctr & USB_PIPECTR_PID_MSK) {
+    default: return;
+    case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break;
+    case USB_PIPECTR_PID_NAK:   result = XFER_RESULT_FAILED;  break;
+  }
+  pipe_state_t *pipe = &_hcd.pipe[num];
+  hcd_event_xfer_complete(pipe->dev, pipe->ep,
+                          pipe->length - pipe->remaining,
+                          result, true);
+}
+
+static void process_pipe_brdy(uint8_t rhport, unsigned num)
+{
+  (void)rhport;
+  pipe_state_t  *pipe   = &_hcd.pipe[num];
+  const unsigned dir_in = tu_edpt_dir(pipe->ep);
+  bool completed;
+
+  if (dir_in) { /* IN */
+    if (num) {
+      completed = pipe_xfer_in(num);
+    } else {
+      completed = pipe0_xfer_in();
+    }
+  } else {
+    completed = pipe_xfer_out(num);
+  }
+  if (completed) {
+    hcd_event_xfer_complete(pipe->dev, pipe->ep,
+                            pipe->length - pipe->remaining,
+                            XFER_RESULT_SUCCESS, true);
+    //  TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining);
+  }
+}
+
+
+/*------------------------------------------------------------------*/
+/* Host API
+ *------------------------------------------------------------------*/
+bool hcd_init(uint8_t rhport)
+{
+  (void)rhport;
+  /* Enable USB0 */
+  uint32_t pswi = disable_interrupt();
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(USB0) = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+  enable_interrupt(pswi);
+  USB0.SYSCFG.BIT.SCKE = 1;
+  while (!USB0.SYSCFG.BIT.SCKE) ;
+  USB0.SYSCFG.BIT.DPRPU = 0;
+  USB0.SYSCFG.BIT.DRPD = 0;
+  USB0.SYSCFG.BIT.DCFM = 1;
+  USB0.SYSCFG.BIT.DRPD = 1;
+  for (volatile int i = 0; i < 30000; ++i) ;
+  USB0.SYSCFG.BIT.USBE = 1;
+
+  USB.DPUSR0R.BIT.FIXPHY0 = 0u;    /* USB0 Transceiver Output fixed */
+#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
+  USB0.PHYSLEW.LONG = 0x5;
+  IR(PERIB, INTB185) = 0;
+#else
+  IR(USB0, USBI0)   = 0;
+#endif
+
+  /* Setup default control pipe */
+  USB0.DCPCFG.WORD  = USB_PIPECFG_SHTNAK;
+  USB0.DCPMAXP.WORD = 64;
+  USB0.INTENB0.WORD = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP;
+  USB0.INTENB1.WORD = USB_IS1_SACK | USB_IS1_SIGN |
+    USB_IS1_ATTCH | USB_IS1_DTCH;
+  USB0.BEMPENB.WORD = 1;
+  USB0.NRDYENB.WORD = 1;
+  USB0.BRDYENB.WORD = 1;
+  return true;
+}
+
+void hcd_int_enable(uint8_t rhport)
+{
+  (void)rhport;
+#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
+  IEN(PERIB, INTB185) = 1;
+#else
+  IEN(USB0, USBI0) = 1;
+#endif
+}
+
+void hcd_int_disable(uint8_t rhport)
+{
+  (void)rhport;
+#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
+  IEN(PERIB, INTB185) = 0;
+#else
+  IEN(USB0, USBI0) = 0;
+#endif
+}
+
+uint32_t hcd_frame_number(uint8_t rhport)
+{
+  (void)rhport;
+  /* The device must be reset at least once after connection 
+   * in order to start the frame counter. */
+  if (_hcd.need_reset) hcd_port_reset(rhport);
+  return USB0.FRMNUM.BIT.FRNM;
+}
+
+/*--------------------------------------------------------------------+
+ * Port API
+ *--------------------------------------------------------------------+*/
+bool hcd_port_connect_status(uint8_t rhport)
+{
+  (void)rhport;
+  return USB0.INTSTS1.BIT.ATTCH ? true: false;
+}
+
+void hcd_port_reset(uint8_t rhport)
+{
+  USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
+  while (USB0.DCPCTR.BIT.PBUSY) ;
+  hcd_int_disable(rhport);
+  USB0.DVSTCTR0.BIT.UACT   = 0;
+  if (USB0.DCPCTR.BIT.SUREQ)
+    USB0.DCPCTR.BIT.SUREQCLR = 1;
+  hcd_int_enable(rhport);
+  /* Reset should be asserted 10-20ms. */
+  USB0.DVSTCTR0.BIT.USBRST = 1;
+  for (volatile int i = 0; i < 2400000; ++i) ;
+  USB0.DVSTCTR0.BIT.USBRST = 0;
+  USB0.DVSTCTR0.BIT.UACT   = 1;
+  _hcd.need_reset = false;
+}
+
+tusb_speed_t hcd_port_speed_get(uint8_t rhport)
+{
+  (void)rhport;
+  switch (USB0.DVSTCTR0.BIT.RHST) {
+    default: return TUSB_SPEED_INVALID;
+    case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL;
+    case USB_DVSTCTR0_LOW:  return TUSB_SPEED_LOW;
+  }
+}
+
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
+{
+  (void)rhport;
+  uint16_t volatile *ctr;
+  TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */
+  if (!dev_addr) return;
+  _hcd.ctl_mps[dev_addr] = 0;
+  uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0];
+  for (int i = 0; i < 2 * 15; ++i, ++ep) {
+    unsigned num = *ep;
+    if (!num || dev_addr != _hcd.pipe[num].dev) continue;
+
+    ctr  = (uint16_t volatile*)&USB0.PIPE1CTR.WORD + num - 1;
+    *ctr = 0;
+    USB0.NRDYENB.WORD &= ~TU_BIT(num);
+    USB0.BRDYENB.WORD &= ~TU_BIT(num);
+    USB0.PIPESEL.WORD  = num;
+    USB0.PIPECFG.WORD  = 0;
+    USB0.PIPEMAXP.WORD = 0;
+
+    _hcd.pipe[num].ep  = 0;
+    _hcd.pipe[num].dev = 0;
+    *ep                = 0;
+  }
+}
+
+/*--------------------------------------------------------------------+
+ * Endpoints API
+ *--------------------------------------------------------------------+*/
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
+{
+  (void)rhport;
+  //  TU_LOG1("S %d %x\n", dev_addr, USB0.DCPCTR.WORD);
+
+  TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
+  TU_ASSERT(0 == USB0.DCPCTR.BIT.SUREQ);
+
+  USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
+
+  _hcd.pipe[0].buf       = NULL;
+  _hcd.pipe[0].length    = 8;
+  _hcd.pipe[0].remaining = 0;
+  _hcd.pipe[0].dev       = dev_addr;
+
+  while (USB0.DCPCTR.BIT.PBUSY) ;
+  USB0.DCPMAXP.WORD      = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
+
+  /* Set direction in advance for DATA stage */
+  uint8_t const bmRequesttype = setup_packet[0];
+  USB0.DCPCFG.BIT.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
+
+  uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
+  USB0.USBREQ.WORD = tu_htole16(p[0]);
+  USB0.USBVAL      = p[1];
+  USB0.USBINDX     = p[2];
+  USB0.USBLENG     = p[3];
+
+  USB0.DCPCTR.BIT.SUREQ = 1;
+  return true;
+}
+
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void)rhport;
+  TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
+
+  const unsigned ep_addr = ep_desc->bEndpointAddress;
+  const unsigned epn     = tu_edpt_number(ep_addr);
+  const unsigned mps     = tu_edpt_packet_size(ep_desc);
+  if (0 == epn) {
+    USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
+    hcd_devtree_info_t devtree;
+    hcd_devtree_get_info(dev_addr, &devtree);
+    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t)&USB0.DEVADD0.WORD;
+    devadd += dev_addr;
+    while (USB0.DCPCTR.BIT.PBUSY) ;
+    USB0.DCPMAXP.WORD = (dev_addr << 12) | mps;
+    *devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW;
+    _hcd.ctl_mps[dev_addr] = mps;
+    return true;
+  }
+
+  const unsigned dir_in = tu_edpt_dir(ep_addr);
+  const unsigned xfer   = ep_desc->bmAttributes.xfer;
+  if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
+    /* USBa supports up to 256 bytes */
+    return false;
+  }
+  const unsigned num = find_pipe(xfer);
+  if (!num) return false;
+  _hcd.pipe[num].dev = dev_addr;
+  _hcd.pipe[num].ep  = ep_addr;
+  _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num;
+
+  /* setup pipe */
+  hcd_int_disable(rhport);
+  USB0.PIPESEL.WORD  = num;
+  USB0.PIPEMAXP.WORD = (dev_addr << 12) | mps;
+  volatile uint16_t *ctr = get_pipectr(num);
+  *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
+  *ctr = 0;
+  unsigned cfg = ((1 ^ dir_in) << 4) | epn;
+  if (xfer == TUSB_XFER_BULK) {
+    cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB;
+  } else if (xfer == TUSB_XFER_INTERRUPT) {
+    cfg |= USB_PIPECFG_INT;
+  } else {
+    cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
+  }
+  USB0.PIPECFG.WORD  = cfg;
+  USB0.BRDYSTS.WORD  = 0x1FFu ^ TU_BIT(num);
+  USB0.NRDYENB.WORD |= TU_BIT(num);
+  USB0.BRDYENB.WORD |= TU_BIT(num);
+  if (!dir_in) {
+    *ctr = USB_PIPECTR_PID_BUF;
+  }
+  hcd_int_enable(rhport);
+
+  return true;
+}
+
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen)
+{
+  bool r;
+  hcd_int_disable(rhport);
+  // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen);
+  r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen);
+  hcd_int_enable(rhport);
+  return r;
+}
+
+bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
+{
+  uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr);
+  TU_ASSERT(ctr);
+  *ctr = USB_PIPECTR_SQCLR;
+  unsigned const epn = tu_edpt_number(ep_addr);
+  if (!epn) return true;
+
+  if (tu_edpt_dir(ep_addr)) { /* IN */
+    const unsigned num = _hcd.ep[dev_addr - 1][1][epn - 1];
+    hcd_int_disable(0);
+    USB0.PIPESEL.WORD  = num;
+    if (USB0.PIPECFG.BIT.TYPE != 1) {
+      *ctr = USB_PIPECTR_PID_BUF;
+    }
+    hcd_int_enable(0);
+  } else {
+    *ctr = USB_PIPECTR_PID_BUF;
+  }
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void hcd_int_handler(uint8_t rhport)
+{
+  (void)rhport;
+#if defined(__CCRX__)
+  static const int Mod37BitPosition[] = {
+    -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4,
+    7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
+    20, 8, 19, 18};
+#endif
+
+  unsigned is1 = USB0.INTSTS1.WORD;
+  unsigned is0 = USB0.INTSTS0.WORD;
+  /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
+  USB0.INTSTS1.WORD = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1);
+  USB0.INTSTS0.WORD = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0);
+  // TU_LOG1("IS %04x %04x\n", is0, is1);
+  is1 &= USB0.INTENB1.WORD;
+  is0 &= USB0.INTENB0.WORD;
+
+  if (is1 & USB_IS1_SACK) {
+    /* Set DATA1 in advance for the next transfer. */
+    USB0.DCPCTR.BIT.SQSET = 1;
+    hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
+                            tu_edpt_addr(0, TUSB_DIR_OUT),
+                            8, XFER_RESULT_SUCCESS, true);
+  }
+  if (is1 & USB_IS1_SIGN) {
+    hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
+                            tu_edpt_addr(0, TUSB_DIR_OUT),
+                            8, XFER_RESULT_FAILED, true);
+  }
+  if (is1 & USB_IS1_ATTCH) {
+    USB0.DVSTCTR0.BIT.UACT = 1;
+    _hcd.need_reset = true;
+    USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_ATTCH) | USB_IS1_DTCH;
+    hcd_event_device_attach(rhport, true);
+  }
+  if (is1 & USB_IS1_DTCH) {
+    USB0.DVSTCTR0.BIT.UACT = 0;
+    if (USB0.DCPCTR.BIT.SUREQ)
+      USB0.DCPCTR.BIT.SUREQCLR = 1;
+    USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_DTCH) | USB_IS1_ATTCH;
+    hcd_event_device_remove(rhport, true);
+  }
+
+  if (is0 & USB_IS0_BEMP) {
+    const unsigned s = USB0.BEMPSTS.WORD;
+    USB0.BEMPSTS.WORD = 0;
+    if (s & 1) {
+      process_pipe0_bemp(rhport);
+    }
+  }
+  if (is0 & USB_IS0_NRDY) {
+    const unsigned m = USB0.NRDYENB.WORD;
+    unsigned s       = USB0.NRDYSTS.WORD & m;
+    USB0.NRDYSTS.WORD = ~s;
+    while (s) {
+#if defined(__CCRX__)
+      const unsigned num = Mod37BitPosition[(-s & s) % 37];
+#else
+      const unsigned num = __builtin_ctz(s);
+#endif
+      process_pipe_nrdy(rhport, num);
+      s &= ~TU_BIT(num);
+    }
+  }
+  if (is0 & USB_IS0_BRDY) {
+    const unsigned m = USB0.BRDYENB.WORD;
+    unsigned s       = USB0.BRDYSTS.WORD & m;
+    /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
+    USB0.BRDYSTS.WORD = ~s;
+    while (s) {
+#if defined(__CCRX__)
+      const unsigned num = Mod37BitPosition[(-s & s) % 37];
+#else
+      const unsigned num = __builtin_ctz(s);
+#endif
+      process_pipe_brdy(rhport, num);
+      s &= ~TU_BIT(num);
+    }
+  }
+}
+
+#endif

From a750c9c90244e54f95f4b801672c15ad7c7019bc Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 27 Dec 2021 21:28:46 +0900
Subject: [PATCH 0751/2085] Increase stack size

---
 hw/bsp/rx/boards/rx65n_target/r5f565ne.ld | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld b/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld
index 8e5617f23..27914e64f 100644
--- a/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld
+++ b/hw/bsp/rx/boards/rx65n_target/r5f565ne.ld
@@ -1,5 +1,5 @@
-__USTACK_SIZE = 0x00000400;
-__ISTACK_SIZE = 0x00000400;
+__USTACK_SIZE = 0x00000800;
+__ISTACK_SIZE = 0x00000800;
 
 MEMORY
 {

From 2c0fcc2fa7e9eec26211760c9d69dcd564e48f2a Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 27 Dec 2021 21:36:49 +0900
Subject: [PATCH 0752/2085] Add statements for control VBUS

---
 src/portable/renesas/usba/hcd_usba.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/portable/renesas/usba/hcd_usba.c b/src/portable/renesas/usba/hcd_usba.c
index 360a8d75f..2dc7f9394 100644
--- a/src/portable/renesas/usba/hcd_usba.c
+++ b/src/portable/renesas/usba/hcd_usba.c
@@ -538,6 +538,9 @@ bool hcd_init(uint8_t rhport)
   USB0.SYSCFG.BIT.DPRPU = 0;
   USB0.SYSCFG.BIT.DRPD = 0;
   USB0.SYSCFG.BIT.DCFM = 1;
+
+  USB0.DVSTCTR0.BIT.VBUSEN = 1;
+
   USB0.SYSCFG.BIT.DRPD = 1;
   for (volatile int i = 0; i < 30000; ++i) ;
   USB0.SYSCFG.BIT.USBE = 1;

From 745607357b9fc46aafb496f628c60c6fb18af6f9 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 27 Dec 2021 21:51:23 +0900
Subject: [PATCH 0753/2085] Update Renesas RX status

---
 docs/reference/supported.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 1f7f395cb..445643733 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -60,7 +60,7 @@ Supported MCUs
 +--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
 | Raspberry Pi | RP2040                | ✔      | ✔    | ✖         | rp2040            |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Renesas      | RX 63N, 65N, 72N      | ✔      | ✖    | ✖         | usba              |              |
+| Renesas      | RX 63N, 65N, 72N      | ✔      | ✔    | ✖         | usba              |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
 | Silabs       | EFM32GG12             | ✔      |      | ✖         | dwc2              |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+

From 2b8b8a3a97e8e895409104689d16387967648c6d Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 27 Dec 2021 22:55:28 +0900
Subject: [PATCH 0754/2085] Fix hcd_edpt_clear_stall

---
 src/portable/renesas/usba/hcd_usba.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/src/portable/renesas/usba/hcd_usba.c b/src/portable/renesas/usba/hcd_usba.c
index 2dc7f9394..35eb060cd 100644
--- a/src/portable/renesas/usba/hcd_usba.c
+++ b/src/portable/renesas/usba/hcd_usba.c
@@ -765,19 +765,17 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
   uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr);
   TU_ASSERT(ctr);
+
+  const uint32_t pid = *ctr & 0x3;
+  if (pid & 2) {
+    *ctr = pid & 2;
+    *ctr = 0;
+  }
   *ctr = USB_PIPECTR_SQCLR;
   unsigned const epn = tu_edpt_number(ep_addr);
   if (!epn) return true;
 
-  if (tu_edpt_dir(ep_addr)) { /* IN */
-    const unsigned num = _hcd.ep[dev_addr - 1][1][epn - 1];
-    hcd_int_disable(0);
-    USB0.PIPESEL.WORD  = num;
-    if (USB0.PIPECFG.BIT.TYPE != 1) {
-      *ctr = USB_PIPECTR_PID_BUF;
-    }
-    hcd_int_enable(0);
-  } else {
+  if (!tu_edpt_dir(ep_addr)) { /* OUT */
     *ctr = USB_PIPECTR_PID_BUF;
   }
   return true;

From 2d13ecde1bdb94575398b2e0e64e6e50a192fd18 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Dec 2021 18:59:47 +0700
Subject: [PATCH 0755/2085] add allwinnner driver as submodule

---
 .gitmodules                                   |   3 +
 hw/mcu/allwinner                              |   1 +
 hw/mcu/allwinner/f1c100s/f1c100s.ld           | 136 ---
 hw/mcu/allwinner/f1c100s/include/arm32.h      | 150 ----
 .../allwinner/f1c100s/include/f1c100s-gpio.h  |  66 --
 .../allwinner/f1c100s/include/f1c100s-irq.h   | 104 ---
 .../allwinner/f1c100s/include/f1c100s-reset.h |  39 -
 .../allwinner/f1c100s/include/f1c100s-util.h  | 139 ---
 .../f1c100s/include/f1c100s/reg-ccu.h         |  55 --
 .../f1c100s/include/f1c100s/reg-dram.h        |  39 -
 hw/mcu/allwinner/f1c100s/include/io.h         |  57 --
 hw/mcu/allwinner/f1c100s/include/irqflags.h   | 104 ---
 hw/mcu/allwinner/f1c100s/include/malloc.h     |  35 -
 hw/mcu/allwinner/f1c100s/include/printf.h     |  99 ---
 hw/mcu/allwinner/f1c100s/include/sizes.h      |  42 -
 hw/mcu/allwinner/f1c100s/include/types.h      |  55 --
 hw/mcu/allwinner/f1c100s/lib/malloc.c         | 834 ------------------
 hw/mcu/allwinner/f1c100s/lib/memcpy.S         | 404 ---------
 hw/mcu/allwinner/f1c100s/lib/memset.S         |  79 --
 hw/mcu/allwinner/f1c100s/lib/printf.c         | 757 ----------------
 hw/mcu/allwinner/f1c100s/machine/exception.c  |  76 --
 .../allwinner/f1c100s/machine/f1c100s-intc.c  | 173 ----
 hw/mcu/allwinner/f1c100s/machine/start.S      | 314 -------
 hw/mcu/allwinner/f1c100s/machine/sys-clock.c  | 124 ---
 .../allwinner/f1c100s/machine/sys-copyself.c  | 111 ---
 hw/mcu/allwinner/f1c100s/machine/sys-dram.c   | 506 -----------
 hw/mcu/allwinner/f1c100s/machine/sys-mmu.c    |  57 --
 .../allwinner/f1c100s/machine/sys-spi-flash.c | 204 -----
 hw/mcu/allwinner/f1c100s/machine/sys-uart.c   |  83 --
 29 files changed, 4 insertions(+), 4842 deletions(-)
 create mode 160000 hw/mcu/allwinner
 delete mode 100644 hw/mcu/allwinner/f1c100s/f1c100s.ld
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/arm32.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s-gpio.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s-irq.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s-reset.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s-util.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s/reg-ccu.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/f1c100s/reg-dram.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/io.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/irqflags.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/malloc.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/printf.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/sizes.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/include/types.h
 delete mode 100644 hw/mcu/allwinner/f1c100s/lib/malloc.c
 delete mode 100644 hw/mcu/allwinner/f1c100s/lib/memcpy.S
 delete mode 100644 hw/mcu/allwinner/f1c100s/lib/memset.S
 delete mode 100644 hw/mcu/allwinner/f1c100s/lib/printf.c
 delete mode 100644 hw/mcu/allwinner/f1c100s/machine/exception.c
 delete mode 100644 hw/mcu/allwinner/f1c100s/machine/f1c100s-intc.c
 delete mode 100644 hw/mcu/allwinner/f1c100s/machine/start.S
 delete mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-clock.c
 delete mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-copyself.c
 delete mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-dram.c
 delete mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-mmu.c
 delete mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-spi-flash.c
 delete mode 100644 hw/mcu/allwinner/f1c100s/machine/sys-uart.c

diff --git a/.gitmodules b/.gitmodules
index 5c79ea910..4ce5d0f0d 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -134,3 +134,6 @@
 [submodule "hw/mcu/infineon/mtb-xmclib-cat3"]
 	path = hw/mcu/infineon/mtb-xmclib-cat3
 	url = https://github.com/Infineon/mtb-xmclib-cat3.git
+[submodule "hw/mcu/allwinner"]
+	path = hw/mcu/allwinner
+	url = https://github.com/hathach/allwinner_driver.git
diff --git a/hw/mcu/allwinner b/hw/mcu/allwinner
new file mode 160000
index 000000000..c56955e15
--- /dev/null
+++ b/hw/mcu/allwinner
@@ -0,0 +1 @@
+Subproject commit c56955e156b1050a4a8ccf8589555148f00a1bb6
diff --git a/hw/mcu/allwinner/f1c100s/f1c100s.ld b/hw/mcu/allwinner/f1c100s/f1c100s.ld
deleted file mode 100644
index 43c353bbd..000000000
--- a/hw/mcu/allwinner/f1c100s/f1c100s.ld
+++ /dev/null
@@ -1,136 +0,0 @@
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-
-STACK_UND_SIZE = 0x10000;
-STACK_ABT_SIZE = 0x10000;
-STACK_IRQ_SIZE = 0x10000;
-STACK_FIQ_SIZE = 0x10000;
-STACK_SRV_SIZE = 0x40000;
-
-MEMORY
-{
-	ram  : org = 0x80000000, len = 8M
-	heap : org = 0x81000000, len = 16M
-}
-
-SECTIONS
-{
-	.bootloader :
-	{
-		PROVIDE(__bootloader_start = .);
-		PROVIDE(__image_start = .);
-		PROVIDE(__text_start = .);
-		_build/*/obj/hw/mcu/allwinner/*/machine/start_asm.o (.text)
-		_build/*/obj/hw/mcu/allwinner/*/lib/memcpy_asm.o (.text)
-		_build/*/obj/hw/mcu/allwinner/*/lib/memset_asm.o (.text)
-		_build/*/obj/hw/mcu/allwinner/*/machine/sys-uart.o (.text*)
-		_build/*/obj/hw/mcu/allwinner/*/machine/sys-clock.o (.text*)
-		_build/*/obj/hw/mcu/allwinner/*/machine/sys-dram.o (.text*)
-		_build/*/obj/hw/mcu/allwinner/*/machine/sys-mmu.o (.text*)
-		_build/*/obj/hw/mcu/allwinner/*/machine/sys-spi-flash.o (.text*)
-		_build/*/obj/hw/mcu/allwinner/*/machine/sys-copyself.o (.text*)
-		PROVIDE(__bootloader_end = .);
-	} > ram
-
-	__bootloader_size = SIZEOF(.bootloader);
-
-	.text :
-	{
-		*(.text*)
-		*(.glue*)
-		*(.note.gnu.build-id)
-		PROVIDE(__text_end = .);
-	} > ram
-
-	.rodata ALIGN(8) :
-	{
-		PROVIDE(__rodata_start = .);
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-		PROVIDE(__rodata_end = .);
-	} > ram
-
-	.data_shadow ALIGN(8) :
-	{
-		PROVIDE(__data_shadow_start = .);
-		PROVIDE(__data_shadow_end = (. + SIZEOF(.data)));
-		PROVIDE(__image_end = __data_shadow_end);
-	} > ram
-
-	.data : AT(ADDR(.data_shadow))
-	{
-		PROVIDE(__data_start = .);	
-		*(.data*)
-		. = ALIGN(8);
-  		PROVIDE(__data_end = .);
-	} > ram
-
-	.ARM.exidx ALIGN(8) :
-	{
-		PROVIDE (__exidx_start = .);
-		*(.ARM.exidx*)
-		PROVIDE (__exidx_end = .);
-	} > ram
-
-	.ARM.extab ALIGN(8) :
-	{
-		PROVIDE (__extab_start = .);
-		*(.ARM.extab*)
-		PROVIDE (__extab_end = .);
-	} > ram
-
-	.bss ALIGN(8) (NOLOAD) :
-	{
-		PROVIDE(__bss_start = .);
-		*(.bss*)
-		*(.sbss*)
-		*(COMMON)
-		. = ALIGN(8);
-		PROVIDE(__bss_end = .);
-	} > ram
-
-	.stack ALIGN(8) (NOLOAD) :
-	{
-		PROVIDE(__stack_start = .);
-		PROVIDE(__stack_und_start = .);
-		. += STACK_UND_SIZE;
-		PROVIDE(__stack_und_end = .);
-		. = ALIGN(8);
-		PROVIDE(__stack_abt_start = .);
-		. += STACK_ABT_SIZE;
-		PROVIDE(__stack_abt_end = .);
-		. = ALIGN(8);
-		PROVIDE(__stack_irq_start = .);
-		. += STACK_IRQ_SIZE;
-		PROVIDE(__stack_irq_end = .);
-		. = ALIGN(8);
-		PROVIDE(__stack_fiq_start = .);
-		. += STACK_FIQ_SIZE;
-		PROVIDE(__stack_fiq_end = .);
-		. = ALIGN(8);
-		PROVIDE(__stack_srv_start = .);
-		. += STACK_SRV_SIZE;
-		PROVIDE(__stack_srv_end = .);
-		. = ALIGN(8);
-		PROVIDE(__stack_end = .);
-	} > ram
-
-	.heap ALIGN(8) (NOLOAD) :
-	{
-		PROVIDE(__heap_start = ORIGIN(heap));
-		PROVIDE(__heap_end = ORIGIN(heap) + LENGTH(heap));
-	} > heap
-
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
-}
diff --git a/hw/mcu/allwinner/f1c100s/include/arm32.h b/hw/mcu/allwinner/f1c100s/include/arm32.h
deleted file mode 100644
index a3a254551..000000000
--- a/hw/mcu/allwinner/f1c100s/include/arm32.h
+++ /dev/null
@@ -1,150 +0,0 @@
-#ifndef __ARM32_H__
-#define __ARM32_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-struct arm_regs_t {
-	uint32_t r[13];
-	uint32_t sp;
-	uint32_t lr;
-	uint32_t pc;
-	uint32_t cpsr;
-};
-
-static inline uint32_t arm32_read_p15_c1(void)
-{
-	uint32_t value;
-
-	__asm__ __volatile__(
-		"mrc p15, 0, %0, c1, c0, 0"
-		: "=r" (value)
-		:
-		: "memory");
-
-	return value;
-}
-
-static inline void arm32_write_p15_c1(uint32_t value)
-{
-	__asm__ __volatile__(
-		"mcr p15, 0, %0, c1, c0, 0"
-		:
-		: "r" (value)
-		: "memory");
-	arm32_read_p15_c1();
-}
-
-static inline void arm32_interrupt_enable(void)
-{
-	uint32_t tmp;
-
-	__asm__ __volatile__(
-		"mrs %0, cpsr\n"
-		"bic %0, %0, #(1<<7)\n"
-		"msr cpsr_cxsf, %0"
-		: "=r" (tmp)
-		:
-		: "memory");
-}
-
-static inline void arm32_interrupt_disable(void)
-{
-	uint32_t tmp;
-
-	__asm__ __volatile__(
-		"mrs %0, cpsr\n"
-		"orr %0, %0, #(1<<7)\n"
-		"msr cpsr_cxsf, %0"
-		: "=r" (tmp)
-		:
-		: "memory");
-}
-
-static inline void arm32_mmu_enable(void)
-{
-	uint32_t value = arm32_read_p15_c1();
-	arm32_write_p15_c1(value | (1 << 0));
-}
-
-static inline void arm32_mmu_disable(void)
-{
-	uint32_t value = arm32_read_p15_c1();
-	arm32_write_p15_c1(value & ~(1 << 0));
-}
-
-static inline void arm32_dcache_enable(void)
-{
-	uint32_t value = arm32_read_p15_c1();
-	arm32_write_p15_c1(value | (1 << 2));
-}
-
-static inline void arm32_dcache_disable(void)
-{
-	uint32_t value = arm32_read_p15_c1();
-	arm32_write_p15_c1(value & ~(1 << 2));
-}
-
-static inline void arm32_icache_enable(void)
-{
-	uint32_t value = arm32_read_p15_c1();
-	arm32_write_p15_c1(value | (1 << 12));
-}
-
-static inline void arm32_icache_disable(void)
-{
-	uint32_t value = arm32_read_p15_c1();
-	arm32_write_p15_c1(value & ~(1 << 12));
-}
-
-static inline uint32_t arm32_smp_processor_id(void)
-{
-	uint32_t tmp;
-
-	__asm__ __volatile__(
-		"mrc p15,0,%0,c0,c0,5\n"
-		"and %0,%0,#0x3\n"
-		: "=r" (tmp)
-		:
-		: "memory");
-	return tmp;
-}
-
-static inline void arm32_ttb_set(uint32_t base)
-{
-	__asm__ __volatile__(
-		"mcr p15, 0, %0, c2, c0, 0"
-		:
-		: "r" (base)
-		: "memory");
-}
-
-static inline void arm32_domain_set(uint32_t domain)
-{
-	__asm__ __volatile__(
-		"mcr p15, 0, %0, c3, c0, 0"
-		:
-		: "r" (domain)
-		: "memory");
-}
-
-static inline void arm32_tlb_invalidate(void)
-{
-	__asm__ __volatile__(
-		"mov r0, #0\n"
-		"mcr p15, 0, r0, c7, c10, 4\n"
-		"mcr p15, 0, r0, c8, c6, 0\n"
-		"mcr p15, 0, r0, c8, c5, 0\n"
-		:
-		:
-		: "r0");
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ARM32_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s-gpio.h b/hw/mcu/allwinner/f1c100s/include/f1c100s-gpio.h
deleted file mode 100644
index 3dbe8bf13..000000000
--- a/hw/mcu/allwinner/f1c100s/include/f1c100s-gpio.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef __F1C100S_GPIO_H__
-#define __F1C100S_GPIO_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define F1C100S_GPIOA0			(0)
-#define F1C100S_GPIOA1			(1)
-#define F1C100S_GPIOA2			(2)
-#define F1C100S_GPIOA3			(3)
-
-#define F1C100S_GPIOC0			(64)
-#define F1C100S_GPIOC1			(65)
-#define F1C100S_GPIOC2			(66)
-#define F1C100S_GPIOC3			(67)
-
-#define F1C100S_GPIOD0			(96)
-#define F1C100S_GPIOD1			(97)
-#define F1C100S_GPIOD2			(98)
-#define F1C100S_GPIOD3			(99)
-#define F1C100S_GPIOD4			(100)
-#define F1C100S_GPIOD5			(101)
-#define F1C100S_GPIOD6			(102)
-#define F1C100S_GPIOD7			(103)
-#define F1C100S_GPIOD8			(104)
-#define F1C100S_GPIOD9			(105)
-#define F1C100S_GPIOD10			(106)
-#define F1C100S_GPIOD11			(107)
-#define F1C100S_GPIOD12			(108)
-#define F1C100S_GPIOD13			(109)
-#define F1C100S_GPIOD14			(110)
-#define F1C100S_GPIOD15			(111)
-#define F1C100S_GPIOD16			(112)
-#define F1C100S_GPIOD17			(113)
-#define F1C100S_GPIOD18			(114)
-#define F1C100S_GPIOD19			(115)
-#define F1C100S_GPIOD20			(116)
-#define F1C100S_GPIOD21			(117)
-
-#define F1C100S_GPIOE0			(128)
-#define F1C100S_GPIOE1			(129)
-#define F1C100S_GPIOE2			(130)
-#define F1C100S_GPIOE3			(131)
-#define F1C100S_GPIOE4			(132)
-#define F1C100S_GPIOE5			(133)
-#define F1C100S_GPIOE6			(134)
-#define F1C100S_GPIOE7			(135)
-#define F1C100S_GPIOE8			(136)
-#define F1C100S_GPIOE9			(137)
-#define F1C100S_GPIOE10			(138)
-#define F1C100S_GPIOE11			(139)
-#define F1C100S_GPIOE12			(140)
-
-#define F1C100S_GPIOF0			(160)
-#define F1C100S_GPIOF1			(161)
-#define F1C100S_GPIOF2			(162)
-#define F1C100S_GPIOF3			(163)
-#define F1C100S_GPIOF4			(164)
-#define F1C100S_GPIOF5			(165)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __F1C100S_GPIO_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s-irq.h b/hw/mcu/allwinner/f1c100s/include/f1c100s-irq.h
deleted file mode 100644
index 410d1be93..000000000
--- a/hw/mcu/allwinner/f1c100s/include/f1c100s-irq.h
+++ /dev/null
@@ -1,104 +0,0 @@
-#ifndef __F1C100S_IRQ_H__
-#define __F1C100S_IRQ_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define F1C100S_IRQ_NMI			(0)
-#define F1C100S_IRQ_UART0		(1)
-#define F1C100S_IRQ_UART1		(2)
-#define F1C100S_IRQ_UART2		(3)
-#define F1C100S_IRQ_SPDIF		(5)
-#define F1C100S_IRQ_CIR			(6)
-#define F1C100S_IRQ_I2C0		(7)
-#define F1C100S_IRQ_I2C1		(8)
-#define F1C100S_IRQ_I2C2		(9)
-#define F1C100S_IRQ_SPI0		(10)
-#define F1C100S_IRQ_SPI1		(11)
-#define F1C100S_IRQ_TIMER0		(13)
-#define F1C100S_IRQ_TIMER1		(14)
-#define F1C100S_IRQ_TIMER2		(15)
-#define F1C100S_IRQ_WDOG		(16)
-#define F1C100S_IRQ_RSB			(17)
-#define F1C100S_IRQ_DMA			(18)
-#define F1C100S_IRQ_TP			(20)
-#define F1C100S_IRQ_AUDIO		(21)
-#define F1C100S_IRQ_LRADC		(22)
-#define F1C100S_IRQ_MMC0		(23)
-#define F1C100S_IRQ_MMC1		(24)
-#define F1C100S_IRQ_USBOTG		(26)
-#define F1C100S_IRQ_TVD			(27)
-#define F1C100S_IRQ_TVE			(28)
-#define F1C100S_IRQ_LCD			(29)
-#define F1C100S_IRQ_DEFE		(30)
-#define F1C100S_IRQ_DEBE		(31)
-#define F1C100S_IRQ_CSI			(32)
-#define F1C100S_IRQ_DEITLA		(33)
-#define F1C100S_IRQ_VE			(34)
-#define F1C100S_IRQ_I2S			(35)
-#define F1C100S_IRQ_GPIOD		(38)
-#define F1C100S_IRQ_GPIOE		(39)
-#define F1C100S_IRQ_GPIOF		(40)
-
-#define F1C100S_IRQ_GPIOD0		(64)
-#define F1C100S_IRQ_GPIOD1		(65)
-#define F1C100S_IRQ_GPIOD2		(66)
-#define F1C100S_IRQ_GPIOD3		(67)
-#define F1C100S_IRQ_GPIOD4		(68)
-#define F1C100S_IRQ_GPIOD5		(69)
-#define F1C100S_IRQ_GPIOD6		(70)
-#define F1C100S_IRQ_GPIOD7		(71)
-#define F1C100S_IRQ_GPIOD8		(72)
-#define F1C100S_IRQ_GPIOD9		(73)
-#define F1C100S_IRQ_GPIOD10		(74)
-#define F1C100S_IRQ_GPIOD11		(75)
-#define F1C100S_IRQ_GPIOD12		(76)
-#define F1C100S_IRQ_GPIOD13		(77)
-#define F1C100S_IRQ_GPIOD14		(78)
-#define F1C100S_IRQ_GPIOD15		(79)
-#define F1C100S_IRQ_GPIOD17		(80)
-#define F1C100S_IRQ_GPIOD18		(81)
-#define F1C100S_IRQ_GPIOD19		(82)
-#define F1C100S_IRQ_GPIOD20		(83)
-#define F1C100S_IRQ_GPIOD21		(84)
-
-#define F1C100S_IRQ_GPIOE0		(96)
-#define F1C100S_IRQ_GPIOE1		(97)
-#define F1C100S_IRQ_GPIOE2		(98)
-#define F1C100S_IRQ_GPIOE3		(99)
-#define F1C100S_IRQ_GPIOE4		(100)
-#define F1C100S_IRQ_GPIOE5		(101)
-#define F1C100S_IRQ_GPIOE6		(102)
-#define F1C100S_IRQ_GPIOE7		(103)
-#define F1C100S_IRQ_GPIOE8		(104)
-#define F1C100S_IRQ_GPIOE9		(105)
-#define F1C100S_IRQ_GPIOE10		(106)
-#define F1C100S_IRQ_GPIOE11		(107)
-#define F1C100S_IRQ_GPIOE12		(108)
-
-#define F1C100S_IRQ_GPIOF0		(128)
-#define F1C100S_IRQ_GPIOF1		(129)
-#define F1C100S_IRQ_GPIOF2		(130)
-#define F1C100S_IRQ_GPIOF3		(131)
-#define F1C100S_IRQ_GPIOF4		(132)
-#define F1C100S_IRQ_GPIOF5		(133)
-
-typedef void (*IRQHandleTypeDef)(void);
-
-uint8_t   f1c100s_intc_get_nirq(void);
-void      f1c100s_intc_dispatch(uint8_t nIRQ);
-void      f1c100s_intc_set_isr(uint8_t nIRQ, IRQHandleTypeDef handle);
-void      f1c100s_intc_enable_irq(uint8_t nIRQ);
-void      f1c100s_intc_disable_irq(uint8_t nIRQ);
-void      f1c100s_intc_unmask_irq(uint8_t nIRQ);
-void      f1c100s_intc_mask_irq(uint8_t nIRQ);
-void      f1c100s_intc_force_irq(uint8_t nIRQ);
-void      f1c100s_intc_clear_pend(uint8_t nIRQ);
-void      f1c100s_intc_init(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __F1C100S_IRQ_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s-reset.h b/hw/mcu/allwinner/f1c100s/include/f1c100s-reset.h
deleted file mode 100644
index e787a1ac1..000000000
--- a/hw/mcu/allwinner/f1c100s/include/f1c100s-reset.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef __F1C100S_RESET_H__
-#define __F1C100S_RESET_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define F1C100S_RESET_DMA			(6)
-#define F1C100S_RESET_SD0			(8)
-#define F1C100S_RESET_SD1			(9)
-#define F1C100S_RESET_SDRAM			(14)
-#define F1C100S_RESET_SPI0			(20)
-#define F1C100S_RESET_SPI1			(21)
-#define F1C100S_RESET_USB_OTG		(24)
-#define F1C100S_RESET_VE			(32)
-#define F1C100S_RESET_LCD			(36)
-#define F1C100S_RESET_DEINTERLACE	(37)
-#define F1C100S_RESET_CSI			(40)
-#define F1C100S_RESET_TVD			(41)
-#define F1C100S_RESET_TVE			(42)
-#define F1C100S_RESET_DEBE			(44)
-#define F1C100S_RESET_DEFE			(46)
-#define F1C100S_RESET_ADDA			(64)
-#define F1C100S_RESET_SPDIF			(65)
-#define F1C100S_RESET_CIR			(66)
-#define F1C100S_RESET_RSB			(67)
-#define F1C100S_RESET_DAUDIO		(76)
-#define F1C100S_RESET_I2C0			(80)
-#define F1C100S_RESET_I2C1			(81)
-#define F1C100S_RESET_I2C2			(82)
-#define F1C100S_RESET_UART0			(84)
-#define F1C100S_RESET_UART1			(85)
-#define F1C100S_RESET_UART2			(86)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __F1C100S_RESET_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s-util.h b/hw/mcu/allwinner/f1c100s/include/f1c100s-util.h
deleted file mode 100644
index cb3829f82..000000000
--- a/hw/mcu/allwinner/f1c100s/include/f1c100s-util.h
+++ /dev/null
@@ -1,139 +0,0 @@
-// Designed by Hong Xuyao
-
-#ifndef __TARGET_H__
-#define __TARGET_H__
-////////////////////////////////////////////////////////////////////////////////
-#include <stdint.h>
-typedef unsigned long       ubase_t;
-
-#define MEM_PI_SRAM     __attribute__((section("SRAM")))
-
-#define MEM_PI_SUMMARY  __attribute__((section("SUMMARY")))
-
-#define MEM_PI_NOINIT   __attribute__((section("NOINIT"),zero_init))
-
-#define MEM_PI_CPUONLY  __attribute__((section("CPUONLY"),zero_init))
-
-#define MEM_PI_HARDWARE __attribute__((section("HARDWARE"),zero_init,aligned(32)))
-
-#define MEM_PI_NCNB     __attribute__((section("NCNB"),zero_init,aligned(32)))
-
-#define MEM_PI_STACK    __attribute__((section("STACK"),zero_init,aligned(8)))
-
-#define CACHE_ALIGNED   __attribute__((aligned(32)))
-
-#ifndef INLINE
-#define INLINE        __attribute__((always_inline))
-#endif
-
-#ifndef NOINLINE
-#define NOINLINE      __attribute__((noinline))
-#endif
-
-#ifndef NOINLINE_FUNC
-#define NOINLINE_FUNC __attribute__((noinline))
-#endif
-
-#ifndef ALIGN
-#define ALIGN(n)      __attribute__((aligned(n)))
-#endif
-
-#define CPU_SR_DECL   ubase_t cpu_sr
-
-#ifdef __thumb__
-#define __SWITCH_TO_ARM__
-#pragma arm
-#endif
-
-#if 0
-#define CPU_ENTER_CRITICAL()  do{cpu_sr = util_enter_critical();}while(0)
-#else
-#define CPU_ENTER_CRITICAL()  do{cpu_sr = __fast_enter_critical();}while(0)
-static inline ubase_t __fast_enter_critical(void)
-{
-  ubase_t cpu_sr, tmp_sr;
-  __asm volatile {
-    MRS cpu_sr, CPSR
-    ORR tmp_sr, cpu_sr, #0xC0
-    MSR CPSR_c, tmp_sr
-  }
-  return cpu_sr;
-}
-#endif
-
-#if 0
-#define CPU_EXIT_CRITICAL()   do{util_exit_critical(cpu_sr);}while(0)
-#else
-#define CPU_EXIT_CRITICAL()   do{__fast_exit_critical(cpu_sr);}while(0)
-static inline void __fast_exit_critical(ubase_t cpu_sr)
-{
-  __asm volatile {
-    MSR CPSR_c, cpu_sr
-  }
-}
-#endif
-
-static inline unsigned CPU_CLZ16(uint16_t val)
-{
-  __asm volatile {
-    CLZ val, val
-  }
-  return (val - 16);
-}
-
-static inline uint8_t __swap_byte(uint8_t newval, uint8_t volatile* pmem)
-{
-  uint8_t oldval;
-  __asm volatile {
-    SWPB  oldval, newval, [pmem]
-  };
-  return oldval;
-}
-
-static inline uint32_t UTL_REV32(uint32_t val)
-{
-  uint32_t tmpval;
-  __asm volatile {
-    EOR tmpval, val, val, ROR #16
-    MOV tmpval, tmpval, LSR #8
-    BIC tmpval, tmpval, #0xFF00
-    EOR val, tmpval, val, ROR #8
-  }
-  return val;
-}
-
-static inline uint16_t UTL_REV16(uint16_t val)
-{
-  uint32_t tmpval;
-  __asm volatile {
-    LSR tmpval, val, #8
-    ORR val, tmpval, val, LSL #8
-    BIC val, val, #0xFF0000
-  }
-  return val;
-}
-
-#ifdef __SWITCH_TO_ARM__ 
-#undef __SWITCH_TO_ARM__
-#pragma thumb
-#endif
-
-#ifndef COUNTOF
-#define COUNTOF(ar) (sizeof(ar)/sizeof(ar[0]))
-#endif
-/*
-void    util_halt(void);
-void    util_fastloop(ubase_t n);
-ubase_t util_getCPSR(void);
-ubase_t util_enter_critical(void);
-void    util_exit_critical(ubase_t sr);
-void    util_enable_interrupt(void);
-void    util_disable_interrupt(void);
-
-void    target_wdt_setup(void);
-void    target_wdt_feed(void);
-void    target_reset(void);
-*/
-////////////////////////////////////////////////////////////////////////////////
-#endif /* __TARGET_H__ */
-
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-ccu.h b/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-ccu.h
deleted file mode 100644
index 1770ad7ff..000000000
--- a/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-ccu.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef __F1C100S_REG_CCU_H__
-#define __F1C100S_REG_CCU_H__
-
-#define F1C100S_CCU_BASE		(0x01c20000)
-
-#define CCU_PLL_CPU_CTRL		(0x000)
-#define CCU_PLL_AUDIO_CTRL		(0x008)
-#define CCU_PLL_VIDEO_CTRL		(0x010)
-#define CCU_PLL_VE_CTRL			(0x018)
-#define CCU_PLL_DDR_CTRL		(0x020)
-#define CCU_PLL_PERIPH_CTRL		(0x028)
-#define CCU_CPU_CFG				(0x050)
-#define CCU_AHB_APB_CFG			(0x054)
-
-#define CCU_BUS_CLK_GATE0		(0x060)
-#define CCU_BUS_CLK_GATE1		(0x064)
-#define CCU_BUS_CLK_GATE2		(0x068)
-
-#define CCU_SDMMC0_CLK			(0x088)
-#define CCU_SDMMC1_CLK			(0x08c)
-#define CCU_DAUDIO_CLK			(0x0b0)
-#define CCU_SPDIF_CLK			(0x0b4)
-#define CCU_I2S_CLK				(0x0b8)
-#define CCU_USBPHY_CFG			(0x0cc)
-#define CCU_DRAM_CLK_GATE		(0x100)
-#define CCU_DEBE_CLK			(0x104)
-#define CCU_DEFE_CLK			(0x10c)
-#define CCU_LCD_CLK				(0x118)
-#define CCU_DEINTERLACE_CLK		(0x11c)
-#define CCU_TVE_CLK				(0x120)
-#define CCU_TVD_CLK				(0x124)
-#define CCU_CSI_CLK				(0x134)
-#define CCU_VE_CLK				(0x13c)
-#define CCU_ADDA_CLK			(0x140)
-#define CCU_AVS_CLK				(0x144)
-
-#define CCU_PLL_STABLE_TIME0	(0x200)
-#define CCU_PLL_STABLE_TIME1	(0x204)
-#define CCU_PLL_CPU_BIAS		(0x220)
-#define CCU_PLL_AUDIO_BIAS		(0x224)
-#define CCU_PLL_VIDEO_BIAS		(0x228)
-#define CCU_PLL_VE_BIAS			(0x22c)
-#define CCU_PLL_DDR0_BIAS		(0x230)
-#define CCU_PLL_PERIPH_BIAS		(0x234)
-#define CCU_PLL_CPU_TUN			(0x250)
-#define CCU_PLL_DDR_TUN			(0x260)
-#define CCU_PLL_AUDIO_PAT		(0x284)
-#define CCU_PLL_VIDEO_PAT		(0x288)
-#define CCU_PLL_DDR0_PAT		(0x290)
-
-#define CCU_BUS_SOFT_RST0		(0x2c0)
-#define CCU_BUS_SOFT_RST1		(0x2c4)
-#define CCU_BUS_SOFT_RST3		(0x2d0)
-
-#endif /* __F1C100S_REG_CCU_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-dram.h b/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-dram.h
deleted file mode 100644
index 8a0ac3e0e..000000000
--- a/hw/mcu/allwinner/f1c100s/include/f1c100s/reg-dram.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#ifndef __F1C100S_REG_DRAM_H__
-#define __F1C100S_REG_DRAM_H__
-
-#define F1C100S_DRAM_BASE	(0x01c01000)
-
-#define DRAM_SCONR			(0x00)
-#define DRAM_STMG0R			(0x04)
-#define DRAM_STMG1R			(0x08)
-#define DRAM_SCTLR			(0x0c)
-#define DRAM_SREFR			(0x10)
-#define DRAM_SEXTMR			(0x14)
-#define DRAM_DDLYR			(0x24)
-#define DRAM_DADRR			(0x28)
-#define DRAM_DVALR			(0x2c)
-#define DRAM_DRPTR0			(0x30)
-#define DRAM_DRPTR1			(0x34)
-#define DRAM_DRPTR2			(0x38)
-#define DRAM_DRPTR3			(0x3c)
-#define DRAM_SEFR			(0x40)
-#define DRAM_MAE			(0x44)
-#define DRAM_ASPR			(0x48)
-#define DRAM_SDLY0			(0x4C)
-#define DRAM_SDLY1			(0x50)
-#define DRAM_SDLY2			(0x54)
-#define DRAM_MCR0			(0x100)
-#define DRAM_MCR1			(0x104)
-#define DRAM_MCR2			(0x108)
-#define DRAM_MCR3			(0x10c)
-#define DRAM_MCR4			(0x110)
-#define DRAM_MCR5			(0x114)
-#define DRAM_MCR6			(0x118)
-#define DRAM_MCR7			(0x11c)
-#define DRAM_MCR8			(0x120)
-#define DRAM_MCR9			(0x124)
-#define DRAM_MCR10			(0x128)
-#define DRAM_MCR11			(0x12c)
-#define DRAM_BWCR			(0x140)
-
-#endif /* __F1C100S_REG_DRAM_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/io.h b/hw/mcu/allwinner/f1c100s/include/io.h
deleted file mode 100644
index f0dad1785..000000000
--- a/hw/mcu/allwinner/f1c100s/include/io.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef __IO_H__
-#define __IO_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <types.h>
-
-static inline u8_t read8(virtual_addr_t addr)
-{
-	return( *((volatile u8_t *)(addr)) );
-}
-
-static inline u16_t read16(virtual_addr_t addr)
-{
-	return( *((volatile u16_t *)(addr)) );
-}
-
-static inline u32_t read32(virtual_addr_t addr)
-{
-	return( *((volatile u32_t *)(addr)) );
-}
-
-static inline u64_t read64(virtual_addr_t addr)
-{
-	return( *((volatile u64_t *)(addr)) );
-}
-
-static inline void write8(virtual_addr_t addr, u8_t value)
-{
-	*((volatile u8_t *)(addr)) = value;
-}
-
-static inline void write16(virtual_addr_t addr, u16_t value)
-{
-	*((volatile u16_t *)(addr)) = value;
-}
-
-static inline void write32(virtual_addr_t addr, u32_t value)
-{
-	*((volatile u32_t *)(addr)) = value;
-}
-
-static inline void write64(virtual_addr_t addr, u64_t value)
-{
-	*((volatile u64_t *)(addr)) = value;
-}
-
-virtual_addr_t phys_to_virt(physical_addr_t phys);
-physical_addr_t virt_to_phys(virtual_addr_t virt);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __IO_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/irqflags.h b/hw/mcu/allwinner/f1c100s/include/irqflags.h
deleted file mode 100644
index e4ef97cd2..000000000
--- a/hw/mcu/allwinner/f1c100s/include/irqflags.h
+++ /dev/null
@@ -1,104 +0,0 @@
-#ifndef __ARM32_IRQFLAGS_H__
-#define __ARM32_IRQFLAGS_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <types.h>
-
-#if __ARM32_ARCH__ == 5
-
-static inline void arch_local_irq_enable(void)
-{
-	irq_flags_t temp;
-
-	__asm__ __volatile__(
-		"mrs %0, cpsr\n"
-		"bic %0, %0, #(1<<7)\n"
-		"msr cpsr_c, %0"
-		: "=r" (temp)
-		:
-		: "memory", "cc");
-}
-
-static inline void arch_local_irq_disable(void)
-{
-	irq_flags_t temp;
-
-	__asm__ __volatile__(
-		"mrs %0, cpsr\n"
-		"orr %0, %0, #(1<<7)\n"
-		"msr cpsr_c, %0"
-		: "=r" (temp)
-		:
-		: "memory", "cc");
-}
-
-static inline irq_flags_t arch_local_irq_save(void)
-{
-	irq_flags_t flags, temp;
-
-	__asm__ __volatile__(
-		"mrs %0, cpsr\n"
-		"orr %1, %0, #(1<<7)\n"
-		"msr cpsr_c, %1"
-		: "=r" (flags), "=r" (temp)
-		:
-		: "memory", "cc");
-
-	return flags;
-}
-
-static inline void arch_local_irq_restore(irq_flags_t flags)
-{
-	__asm__ __volatile__(
-		"msr cpsr_c, %0"
-		:
-		: "r" (flags)
-		: "memory", "cc");
-}
-#else
-static inline void arch_local_irq_enable(void)
-{
-	__asm__ __volatile__("cpsie i" ::: "memory", "cc");
-}
-
-static inline void arch_local_irq_disable(void)
-{
-	__asm__ __volatile__("cpsid i" ::: "memory", "cc");
-}
-
-static inline irq_flags_t arch_local_irq_save(void)
-{
-	irq_flags_t flags;
-
-	__asm__ __volatile__(
-		"mrs %0, cpsr\n"
-		"cpsid i"
-		: "=r" (flags)
-		:
-		: "memory", "cc");
-	return flags;
-}
-
-static inline void arch_local_irq_restore(irq_flags_t flags)
-{
-	__asm__ __volatile__(
-		"msr cpsr_c, %0"
-		:
-		: "r" (flags)
-		: "memory", "cc");
-}
-#endif
-
-#define local_irq_enable()			do { arch_local_irq_enable(); } while(0)
-#define local_irq_disable()			do { arch_local_irq_disable(); } while(0)
-#define local_irq_save(flags)		do { flags = arch_local_irq_save(); } while(0)
-#define local_irq_restore(flags)	do { arch_local_irq_restore(flags); } while(0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ARM32_IRQFLAGS_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/malloc.h b/hw/mcu/allwinner/f1c100s/include/malloc.h
deleted file mode 100644
index 6669fe48c..000000000
--- a/hw/mcu/allwinner/f1c100s/include/malloc.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef __MALLOC_H__
-#define __MALLOC_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <types.h>
-#include <stddef.h>
-#include <string.h>
-#include <assert.h>
-
-void * mm_create(void * mem, size_t bytes);
-void mm_destroy(void * mm);
-void * mm_get_pool(void * mm);
-void * mm_add_pool(void * mm, void * mem, size_t bytes);
-void mm_remove_pool(void * mm, void * pool);
-void * mm_malloc(void * mm, size_t size);
-void * mm_memalign(void * mm, size_t align, size_t size);
-void * mm_realloc(void * mm, void * ptr, size_t size);
-void mm_free(void * mm, void * ptr);
-
-void * malloc(size_t size);
-void * memalign(size_t align, size_t size);
-void * realloc(void * ptr, size_t size);
-void * calloc(size_t nmemb, size_t size);
-void free(void * ptr);
-
-void do_init_mem_pool(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MALLOC_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/printf.h b/hw/mcu/allwinner/f1c100s/include/printf.h
deleted file mode 100644
index 632bfc20e..000000000
--- a/hw/mcu/allwinner/f1c100s/include/printf.h
+++ /dev/null
@@ -1,99 +0,0 @@
-///////////////////////////////////////////////////////////////////////////////
-// \author (c) Marco Paland (info@paland.com)
-//             2014-2018, PALANDesign Hannover, Germany
-//
-// \license The MIT License (MIT)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy
-// of this software and associated documentation files (the "Software"), to deal
-// in the Software without restriction, including without limitation the rights
-// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-// copies of the Software, and to permit persons to whom the Software is
-// furnished to do so, subject to the following conditions:
-// 
-// The above copyright notice and this permission notice shall be included in
-// all copies or substantial portions of the Software.
-// 
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-// THE SOFTWARE.
-//
-// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on
-//        embedded systems with a very limited resources.
-//        Use this instead of bloated standard/newlib printf.
-//        These routines are thread safe and reentrant!
-//
-///////////////////////////////////////////////////////////////////////////////
-
-#ifndef _PRINTF_H_
-#define _PRINTF_H_
-
-#include <stdarg.h>
-#include <stddef.h>
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/**
- * Output a character to a custom device like UART, used by the printf() function
- * This function is declared here only. You have to write your custom implementation somewhere
- * \param character Character to output
- */
-void _putchar(char character);
-
-
-/**
- * Tiny printf implementation
- * You have to implement _putchar if you use printf()
- * \param format A string that specifies the format of the output
- * \return The number of characters that are written into the array, not counting the terminating null character
- */
-int printf(const char* format, ...);
-
-
-/**
- * Tiny sprintf implementation
- * Due to security reasons (buffer overflow) YOU SHOULD CONSIDER USING (V)SNPRINTF INSTEAD!
- * \param buffer A pointer to the buffer where to store the formatted string. MUST be big enough to store the output!
- * \param format A string that specifies the format of the output
- * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character
- */
-int sprintf(char* buffer, const char* format, ...);
-
-
-/**
- * Tiny snprintf/vsnprintf implementation
- * \param buffer A pointer to the buffer where to store the formatted string
- * \param count The maximum number of characters to store in the buffer, including a terminating null character
- * \param format A string that specifies the format of the output
- * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character
- *         If the formatted string is truncated the buffer size (count) is returned
- */
-int  snprintf(char* buffer, size_t count, const char* format, ...);
-int vsnprintf(char* buffer, size_t count, const char* format, va_list va);
-
-
-/**
- * printf with output function
- * You may use this as dynamic alternative to printf() with its fixed _putchar() output
- * \param out An output function which takes one character and an argument pointer
- * \param arg An argument pointer for user data passed to output function
- * \param format A string that specifies the format of the output
- * \return The number of characters that are sent to the output function, not counting the terminating null character
- */
-int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif // _PRINTF_H_
diff --git a/hw/mcu/allwinner/f1c100s/include/sizes.h b/hw/mcu/allwinner/f1c100s/include/sizes.h
deleted file mode 100644
index 3edeed503..000000000
--- a/hw/mcu/allwinner/f1c100s/include/sizes.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef __SIZES_H__
-#define __SIZES_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SZ_16				(0x00000010)
-#define SZ_256				(0x00000100)
-#define SZ_512				(0x00000200)
-
-#define SZ_1K				(0x00000400)
-#define SZ_4K				(0x00001000)
-#define SZ_8K				(0x00002000)
-#define SZ_16K				(0x00004000)
-#define SZ_32K				(0x00008000)
-#define SZ_64K				(0x00010000)
-#define SZ_128K				(0x00020000)
-#define SZ_256K				(0x00040000)
-#define SZ_512K				(0x00080000)
-
-#define SZ_1M				(0x00100000)
-#define SZ_2M				(0x00200000)
-#define SZ_4M				(0x00400000)
-#define SZ_8M				(0x00800000)
-#define SZ_16M				(0x01000000)
-#define SZ_32M				(0x02000000)
-#define SZ_64M				(0x04000000)
-#define SZ_128M				(0x08000000)
-#define SZ_256M				(0x10000000)
-#define SZ_512M				(0x20000000)
-
-#define SZ_1G				(0x40000000)
-#define SZ_2G				(0x80000000)
-
-#define ARRAY_SIZE(array)	( sizeof(array) / sizeof((array)[0]) )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SIZES_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/include/types.h b/hw/mcu/allwinner/f1c100s/include/types.h
deleted file mode 100644
index 61b87b6d7..000000000
--- a/hw/mcu/allwinner/f1c100s/include/types.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef __ARM32_TYPES_H__
-#define __ARM32_TYPES_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef signed char				s8_t;
-typedef unsigned char			u8_t;
-
-typedef signed short			s16_t;
-typedef unsigned short			u16_t;
-
-typedef signed int				s32_t;
-typedef unsigned int			u32_t;
-
-typedef signed long long		s64_t;
-typedef unsigned long long		u64_t;
-
-typedef signed long long		intmax_t;
-typedef unsigned long long		uintmax_t;
-
-typedef signed int				ptrdiff_t;
-typedef signed int				intptr_t;
-typedef unsigned int 			uintptr_t;
-
-typedef unsigned int			size_t;
-typedef signed int				ssize_t;
-
-// typedef signed int				off_t;
-typedef signed long long		loff_t;
-
-typedef signed int				bool_t;
-
-typedef signed int				register_t;
-typedef unsigned int			irq_flags_t;
-
-typedef unsigned int			virtual_addr_t;
-typedef unsigned int			virtual_size_t;
-typedef unsigned int			physical_addr_t;
-typedef unsigned int			physical_size_t;
-
-typedef struct {
-	volatile long counter;
-} atomic_t;
-
-typedef struct {
-	volatile long lock;
-} spinlock_t;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ARM32_TYPES_H__ */
diff --git a/hw/mcu/allwinner/f1c100s/lib/malloc.c b/hw/mcu/allwinner/f1c100s/lib/malloc.c
deleted file mode 100644
index 763746a47..000000000
--- a/hw/mcu/allwinner/f1c100s/lib/malloc.c
+++ /dev/null
@@ -1,834 +0,0 @@
-/*
- * lib/libc/malloc/malloc.c
- */
-
-#include <malloc.h>
-
-static void * __heap_pool = NULL;
-
-/*
- * Some macros.
- */
-#define tlsf_cast(t, exp)		((t)(exp))
-#define tlsf_min(a, b)			((a) < (b) ? (a) : (b))
-#define tlsf_max(a, b)			((a) > (b) ? (a) : (b))
-
-#define tlsf_assert				assert
-#define tlsf_insist(x)			{ tlsf_assert(x); if (!(x)) { status--; } }
-
-#if defined(__ARM64__) || defined(__X64__)
-# define TLSF_64BIT
-#else
-# undef TLSF_64BIT
-#endif
-
-/*
- * Public constants
- */
-enum tlsf_public
-{
-	/*
-	 * log2 of number of linear subdivisions of block sizes
-	 */
-	SL_INDEX_COUNT_LOG2 = 5,
-};
-
-/*
- * Private constants
- */
-enum tlsf_private
-{
-#if defined(TLSF_64BIT)
-	/*
-	 * All allocation sizes and addresses are aligned to 8 bytes
-	 */
-	ALIGN_SIZE_LOG2 = 3,
-#else
-	/*
-	 * All allocation sizes and addresses are aligned to 4 bytes
-	 */
-	ALIGN_SIZE_LOG2 = 2,
-#endif
-	ALIGN_SIZE = (1 << ALIGN_SIZE_LOG2),
-
-#if defined(TLSF_64BIT)
-	FL_INDEX_MAX = 32,
-#else
-	FL_INDEX_MAX = 30,
-#endif
-	SL_INDEX_COUNT = (1 << SL_INDEX_COUNT_LOG2),
-	FL_INDEX_SHIFT = (SL_INDEX_COUNT_LOG2 + ALIGN_SIZE_LOG2),
-	FL_INDEX_COUNT = (FL_INDEX_MAX - FL_INDEX_SHIFT + 1),
-
-	SMALL_BLOCK_SIZE = (1 << FL_INDEX_SHIFT),
-};
-
-/*
- * Block header structure
- */
-typedef struct block_header_t
-{
-	/*
-	 * Points to the previous physical block
-	 */
-	struct block_header_t * prev_phys_block;
-
-	/*
-	 * The size of this block, excluding the block header
-	 */
-	size_t size;
-
-	/*
-	 * Next and previous free blocks
-	 */
-	struct block_header_t * next_free;
-	struct block_header_t * prev_free;
-} block_header_t;
-
-/*
- * The TLSF control structure.
- */
-typedef struct control_t
-{
-	/*
-	 * Empty lists point at this block to indicate they are free.
-	 */
-	block_header_t block_null;
-
-	/*
-	 * Bitmaps for free lists.
-	 */
-	unsigned int fl_bitmap;
-	unsigned int sl_bitmap[FL_INDEX_COUNT];
-
-	/*
-	 * Head of free lists.
-	 */
-	block_header_t * blocks[FL_INDEX_COUNT][SL_INDEX_COUNT];
-} control_t;
-
-/*
- * A type used for casting when doing pointer arithmetic.
- */
-typedef ptrdiff_t	tlsfptr_t;
-
-/*
- * Associated constants
- */
-static const size_t block_header_free_bit = 1 << 0;
-static const size_t block_header_prev_free_bit = 1 << 1;
-static const size_t block_header_overhead = sizeof(size_t);
-static const size_t block_start_offset = offsetof(block_header_t, size) + sizeof(size_t);
-static const size_t block_size_min = sizeof(block_header_t) - sizeof(block_header_t *);
-static const size_t block_size_max = tlsf_cast(size_t, 1) << FL_INDEX_MAX;
-
-#if defined(__GNUC__) && (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)) && defined(__GNUC_PATCHLEVEL__)
-static int tlsf_ffs(unsigned int word)
-{
-	return __builtin_ffs(word) - 1;
-}
-
-static int tlsf_fls(unsigned int word)
-{
-	const int bit = word ? 32 - __builtin_clz(word) : 0;
-	return bit - 1;
-}
-#else
-static int tlsf_fls_generic(unsigned int word)
-{
-	int bit = 32;
-
-	if (!word) bit -= 1;
-	if (!(word & 0xffff0000)) { word <<= 16; bit -= 16; }
-	if (!(word & 0xff000000)) { word <<= 8; bit -= 8; }
-	if (!(word & 0xf0000000)) { word <<= 4; bit -= 4; }
-	if (!(word & 0xc0000000)) { word <<= 2; bit -= 2; }
-	if (!(word & 0x80000000)) { word <<= 1; bit -= 1; }
-
-	return bit;
-}
-
-static int tlsf_ffs(unsigned int word)
-{
-	return tlsf_fls_generic(word & (~word + 1)) - 1;
-}
-
-static int tlsf_fls(unsigned int word)
-{
-	return tlsf_fls_generic(word) - 1;
-}
-#endif
-
-#if defined(TLSF_64BIT)
-static int tlsf_fls_sizet(size_t size)
-{
-	int high = (int)(size >> 32);
-	int bits = 0;
-	if(high)
-	{
-		bits = 32 + tlsf_fls(high);
-	}
-	else
-	{
-		bits = tlsf_fls((int)size & 0xffffffff);
-
-	}
-	return bits;
-}
-#else
-#define tlsf_fls_sizet		tlsf_fls
-#endif
-
-static size_t block_get_size(const block_header_t * block)
-{
-	return block->size & ~(block_header_free_bit | block_header_prev_free_bit);
-}
-
-static void block_set_size(block_header_t * block, size_t size)
-{
-	const size_t oldsize = block->size;
-	block->size = size | (oldsize & (block_header_free_bit | block_header_prev_free_bit));
-}
-
-static int block_is_last(const block_header_t * block)
-{
-	return (0 == block_get_size(block));
-}
-
-static int block_is_free(const block_header_t * block)
-{
-	return tlsf_cast(int, block->size & block_header_free_bit);
-}
-
-static void block_set_free(block_header_t * block)
-{
-	block->size |= block_header_free_bit;
-}
-
-static void block_set_used(block_header_t * block)
-{
-	block->size &= ~block_header_free_bit;
-}
-
-static int block_is_prev_free(const block_header_t * block)
-{
-	return tlsf_cast(int, block->size & block_header_prev_free_bit);
-}
-
-static void block_set_prev_free(block_header_t * block)
-{
-	block->size |= block_header_prev_free_bit;
-}
-
-static void block_set_prev_used(block_header_t * block)
-{
-	block->size &= ~block_header_prev_free_bit;
-}
-
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wcast-align"
-static block_header_t * block_from_ptr(void * ptr)
-{
-	return tlsf_cast(block_header_t *, tlsf_cast(unsigned char*, ptr) - block_start_offset);
-}
-#pragma GCC diagnostic pop
-
-static void * block_to_ptr(block_header_t * block)
-{
-	return tlsf_cast(void *, tlsf_cast(unsigned char*, block) + block_start_offset);
-}
-
-static block_header_t * offset_to_block(void * ptr, size_t size)
-{
-	return tlsf_cast(block_header_t *, tlsf_cast(tlsfptr_t, ptr) + size);
-}
-
-static block_header_t * block_prev(block_header_t * block)
-{
-	return block->prev_phys_block;
-}
-
-static block_header_t * block_next(block_header_t * block)
-{
-	block_header_t * next = offset_to_block(block_to_ptr(block), block_get_size(block) - block_header_overhead);
-	tlsf_assert(!block_is_last(block));
-	return next;
-}
-
-static block_header_t * block_link_next(block_header_t * block)
-{
-	block_header_t * next = block_next(block);
-	next->prev_phys_block = block;
-	return next;
-}
-
-static void block_mark_as_free(block_header_t * block)
-{
-	block_header_t * next = block_link_next(block);
-	block_set_prev_free(next);
-	block_set_free(block);
-}
-
-static void block_mark_as_used(block_header_t * block)
-{
-	block_header_t * next = block_next(block);
-	block_set_prev_used(next);
-	block_set_used(block);
-}
-
-static size_t align_up(size_t x, size_t align)
-{
-	tlsf_assert(0 == (align & (align - 1)) && "must align to a power of two");
-	return (x + (align - 1)) & ~(align - 1);
-}
-
-static size_t align_down(size_t x, size_t align)
-{
-	tlsf_assert(0 == (align & (align - 1)) && "must align to a power of two");
-	return x - (x & (align - 1));
-}
-
-static void * align_ptr(const void * ptr, size_t align)
-{
-	const tlsfptr_t aligned = (tlsf_cast(tlsfptr_t, ptr) + (align - 1)) & ~(align - 1);
-	tlsf_assert(0 == (align & (align - 1)) && "must align to a power of two");
-	return tlsf_cast(void*, aligned);
-}
-
-static size_t adjust_request_size(size_t size, size_t align)
-{
-	size_t adjust = 0;
-	if (size && size < block_size_max)
-	{
-		const size_t aligned = align_up(size, align);
-		adjust = tlsf_max(aligned, block_size_min);
-	}
-	return adjust;
-}
-
-static void mapping_insert(size_t size, int * fli, int * sli)
-{
-	int fl, sl;
-	if (size < SMALL_BLOCK_SIZE)
-	{
-		fl = 0;
-		sl = tlsf_cast(int, size) / (SMALL_BLOCK_SIZE / SL_INDEX_COUNT);
-	}
-	else
-	{
-		fl = tlsf_fls_sizet(size);
-		sl = tlsf_cast(int, size >> (fl - SL_INDEX_COUNT_LOG2)) ^ (1 << SL_INDEX_COUNT_LOG2);
-		fl -= (FL_INDEX_SHIFT - 1);
-	}
-	*fli = fl;
-	*sli = sl;
-}
-
-static void mapping_search(size_t size, int * fli, int * sli)
-{
-	if (size >= (1 << SL_INDEX_COUNT_LOG2))
-	{
-		const size_t round = (1 << (tlsf_fls_sizet(size) - SL_INDEX_COUNT_LOG2)) - 1;
-		size += round;
-	}
-	mapping_insert(size, fli, sli);
-}
-
-static block_header_t * search_suitable_block(control_t * control, int * fli, int * sli)
-{
-	int fl = *fli;
-	int sl = *sli;
-
-	unsigned int sl_map = control->sl_bitmap[fl] & (~0U << sl);
-	if (!sl_map)
-	{
-		const unsigned int fl_map = control->fl_bitmap & (~0U << (fl + 1));
-		if (!fl_map)
-		{
-			return 0;
-		}
-
-		fl = tlsf_ffs(fl_map);
-		*fli = fl;
-		sl_map = control->sl_bitmap[fl];
-	}
-	tlsf_assert(sl_map && "internal error - second level bitmap is null");
-	sl = tlsf_ffs(sl_map);
-	*sli = sl;
-
-	return control->blocks[fl][sl];
-}
-
-static void remove_free_block(control_t * control, block_header_t * block, int fl, int sl)
-{
-	block_header_t * prev = block->prev_free;
-	block_header_t * next = block->next_free;
-	tlsf_assert(prev && "prev_free field can not be null");
-	tlsf_assert(next && "next_free field can not be null");
-	next->prev_free = prev;
-	prev->next_free = next;
-
-	if (control->blocks[fl][sl] == block)
-	{
-		control->blocks[fl][sl] = next;
-
-		if (next == &control->block_null)
-		{
-			control->sl_bitmap[fl] &= ~(1 << sl);
-
-			if (!control->sl_bitmap[fl])
-			{
-				control->fl_bitmap &= ~(1 << fl);
-			}
-		}
-	}
-}
-
-static void insert_free_block(control_t * control, block_header_t * block, int fl, int sl)
-{
-	block_header_t * current = control->blocks[fl][sl];
-	tlsf_assert(current && "free list cannot have a null entry");
-	tlsf_assert(block && "cannot insert a null entry into the free list");
-	block->next_free = current;
-	block->prev_free = &control->block_null;
-	current->prev_free = block;
-
-	tlsf_assert(block_to_ptr(block) == align_ptr(block_to_ptr(block), ALIGN_SIZE) && "block not aligned properly");
-
-	control->blocks[fl][sl] = block;
-	control->fl_bitmap |= (1 << fl);
-	control->sl_bitmap[fl] |= (1 << sl);
-}
-
-static void block_remove(control_t * control, block_header_t * block)
-{
-	int fl, sl;
-	mapping_insert(block_get_size(block), &fl, &sl);
-	remove_free_block(control, block, fl, sl);
-}
-
-static void block_insert(control_t * control, block_header_t * block)
-{
-	int fl, sl;
-	mapping_insert(block_get_size(block), &fl, &sl);
-	insert_free_block(control, block, fl, sl);
-}
-
-static int block_can_split(block_header_t * block, size_t size)
-{
-	return block_get_size(block) >= sizeof(block_header_t) + size;
-}
-
-static block_header_t * block_split(block_header_t * block, size_t size)
-{
-	block_header_t* remaining = offset_to_block(block_to_ptr(block), size - block_header_overhead);
-	const size_t remain_size = block_get_size(block) - (size + block_header_overhead);
-
-	tlsf_assert(block_to_ptr(remaining) == align_ptr(block_to_ptr(remaining), ALIGN_SIZE) && "remaining block not aligned properly");
-
-	tlsf_assert(block_get_size(block) == remain_size + size + block_header_overhead);
-	block_set_size(remaining, remain_size);
-	tlsf_assert(block_get_size(remaining) >= block_size_min && "block split with invalid size");
-
-	block_set_size(block, size);
-	block_mark_as_free(remaining);
-
-	return remaining;
-}
-
-static block_header_t * block_absorb(block_header_t * prev, block_header_t * block)
-{
-	tlsf_assert(!block_is_last(prev) && "previous block can't be last!");
-	prev->size += block_get_size(block) + block_header_overhead;
-	block_link_next(prev);
-	return prev;
-}
-
-static block_header_t * block_merge_prev(control_t * control, block_header_t * block)
-{
-	if (block_is_prev_free(block))
-	{
-		block_header_t* prev = block_prev(block);
-		tlsf_assert(prev && "prev physical block can't be null");
-		tlsf_assert(block_is_free(prev) && "prev block is not free though marked as such");
-		block_remove(control, prev);
-		block = block_absorb(prev, block);
-	}
-
-	return block;
-}
-
-static block_header_t * block_merge_next(control_t * control, block_header_t * block)
-{
-	block_header_t* next = block_next(block);
-	tlsf_assert(next && "next physical block can't be null");
-
-	if (block_is_free(next))
-	{
-		tlsf_assert(!block_is_last(block) && "previous block can't be last!");
-		block_remove(control, next);
-		block = block_absorb(block, next);
-	}
-
-	return block;
-}
-
-static void block_trim_free(control_t * control, block_header_t * block, size_t size)
-{
-	tlsf_assert(block_is_free(block) && "block must be free");
-	if (block_can_split(block, size))
-	{
-		block_header_t* remaining_block = block_split(block, size);
-		block_link_next(block);
-		block_set_prev_free(remaining_block);
-		block_insert(control, remaining_block);
-	}
-}
-
-static void block_trim_used(control_t * control, block_header_t * block, size_t size)
-{
-	tlsf_assert(!block_is_free(block) && "block must be used");
-	if (block_can_split(block, size))
-	{
-		block_header_t* remaining_block = block_split(block, size);
-		block_set_prev_used(remaining_block);
-
-		remaining_block = block_merge_next(control, remaining_block);
-		block_insert(control, remaining_block);
-	}
-}
-
-static block_header_t * block_trim_free_leading(control_t * control, block_header_t * block, size_t size)
-{
-	block_header_t * remaining_block = block;
-	if (block_can_split(block, size))
-	{
-		remaining_block = block_split(block, size - block_header_overhead);
-		block_set_prev_free(remaining_block);
-
-		block_link_next(block);
-		block_insert(control, block);
-	}
-
-	return remaining_block;
-}
-
-static block_header_t * block_locate_free(control_t * control, size_t size)
-{
-	int fl = 0, sl = 0;
-	block_header_t * block = 0;
-
-	if (size)
-	{
-		mapping_search(size, &fl, &sl);
-		block = search_suitable_block(control, &fl, &sl);
-	}
-
-	if (block)
-	{
-		tlsf_assert(block_get_size(block) >= size);
-		remove_free_block(control, block, fl, sl);
-	}
-
-	return block;
-}
-
-static void * block_prepare_used(control_t * control, block_header_t * block, size_t size)
-{
-	void* p = 0;
-	if (block)
-	{
-		block_trim_free(control, block, size);
-		block_mark_as_used(block);
-		p = block_to_ptr(block);
-	}
-	return p;
-}
-
-static void control_construct(control_t * control)
-{
-	int i, j;
-
-	control->block_null.next_free = &control->block_null;
-	control->block_null.prev_free = &control->block_null;
-
-	control->fl_bitmap = 0;
-	for (i = 0; i < FL_INDEX_COUNT; ++i)
-	{
-		control->sl_bitmap[i] = 0;
-		for (j = 0; j < SL_INDEX_COUNT; ++j)
-		{
-			control->blocks[i][j] = &control->block_null;
-		}
-	}
-}
-
-static inline void * tlsf_add_pool(void * tlsf, void * mem, size_t bytes)
-{
-	block_header_t * block;
-	block_header_t * next;
-	const size_t pool_overhead = 2 * block_header_overhead;
-	const size_t pool_bytes = align_down(bytes - pool_overhead, ALIGN_SIZE);
-
-	if (((ptrdiff_t)mem % ALIGN_SIZE) != 0)
-		return 0;
-
-	if (pool_bytes < block_size_min || pool_bytes > block_size_max)
-		return 0;
-
-	block = offset_to_block(mem, -(tlsfptr_t)block_header_overhead);
-	block_set_size(block, pool_bytes);
-	block_set_free(block);
-	block_set_prev_used(block);
-	block_insert(tlsf_cast(control_t*, tlsf), block);
-
-	next = block_link_next(block);
-	block_set_size(next, 0);
-	block_set_used(next);
-	block_set_prev_free(next);
-
-	return mem;
-}
-
-static inline void tlsf_remove_pool(void * tlsf, void * pool)
-{
-	control_t * control = tlsf_cast(control_t *, tlsf);
-	block_header_t * block = offset_to_block(pool, -(int)block_header_overhead);
-	int fl = 0, sl = 0;
-
-	tlsf_assert(block_is_free(block) && "block should be free");
-	tlsf_assert(!block_is_free(block_next(block)) && "next block should not be free");
-	tlsf_assert(block_get_size(block_next(block)) == 0 && "next block size should be zero");
-
-	mapping_insert(block_get_size(block), &fl, &sl);
-	remove_free_block(control, block, fl, sl);
-}
-
-static inline void * tlsf_create(void * mem)
-{
-	if (((tlsfptr_t)mem % ALIGN_SIZE) != 0)
-		return 0;
-
-	control_construct(tlsf_cast(control_t *, mem));
-	return tlsf_cast(void *, mem);
-}
-
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Warray-bounds"
-static inline void * tlsf_create_with_pool(void * mem, size_t bytes)
-{
-	void * tlsf = tlsf_create(mem);
-	tlsf_add_pool(tlsf, (char *)mem + sizeof(control_t), bytes - sizeof(control_t));
-	return tlsf;
-}
-#pragma GCC diagnostic pop
-
-
-static inline void tlsf_destroy(void * tlsf)
-{
-	(void)tlsf;
-}
-
-static inline void * tlsf_get_pool(void * tlsf)
-{
-	return tlsf_cast(void *, (char *)tlsf + sizeof(control_t));
-}
-
-static inline void * tlsf_malloc(void * tlsf, size_t size)
-{
-	control_t * control = tlsf_cast(control_t *, tlsf);
-	const size_t adjust = adjust_request_size(size, ALIGN_SIZE);
-	block_header_t * block = block_locate_free(control, adjust);
-	return block_prepare_used(control, block, adjust);
-}
-
-static inline void * tlsf_memalign(void * tlsf, size_t align, size_t size)
-{
-	control_t * control = tlsf_cast(control_t *, tlsf);
-	const size_t adjust = adjust_request_size(size, ALIGN_SIZE);
-
-	const size_t gap_minimum = sizeof(block_header_t);
-	const size_t size_with_gap = adjust_request_size(adjust + align + gap_minimum, align);
-
-	const size_t aligned_size = (align <= ALIGN_SIZE) ? adjust : size_with_gap;
-
-	block_header_t* block = block_locate_free(control, aligned_size);
-
-	tlsf_assert(sizeof(block_header_t) == block_size_min + block_header_overhead);
-
-	if (block)
-	{
-		void * ptr = block_to_ptr(block);
-		void * aligned = align_ptr(ptr, align);
-		size_t gap = tlsf_cast(size_t, tlsf_cast(tlsfptr_t, aligned) - tlsf_cast(tlsfptr_t, ptr));
-
-		if (gap && gap < gap_minimum)
-		{
-			const size_t gap_remain = gap_minimum - gap;
-			const size_t offset = tlsf_max(gap_remain, align);
-			const void * next_aligned = tlsf_cast(void *, tlsf_cast(tlsfptr_t, aligned) + offset);
-
-			aligned = align_ptr(next_aligned, align);
-			gap = tlsf_cast(size_t, tlsf_cast(tlsfptr_t, aligned) - tlsf_cast(tlsfptr_t, ptr));
-		}
-
-		if (gap)
-		{
-			tlsf_assert(gap >= gap_minimum && "gap size too small");
-			block = block_trim_free_leading(control, block, gap);
-		}
-	}
-
-	return block_prepare_used(control, block, adjust);
-}
-
-static inline void tlsf_free(void * tlsf, void * ptr)
-{
-	if (ptr)
-	{
-		control_t * control = tlsf_cast(control_t *, tlsf);
-		block_header_t * block = block_from_ptr(ptr);
-		tlsf_assert(!block_is_free(block) && "block already marked as free");
-		block_mark_as_free(block);
-		block = block_merge_prev(control, block);
-		block = block_merge_next(control, block);
-		block_insert(control, block);
-	}
-}
-
-static inline void * tlsf_realloc(void * tlsf, void * ptr, size_t size)
-{
-	control_t * control = tlsf_cast(control_t *, tlsf);
-	void * p = 0;
-
-	if (ptr && size == 0)
-	{
-		tlsf_free(tlsf, ptr);
-	}
-	else if (!ptr)
-	{
-		p = tlsf_malloc(tlsf, size);
-	}
-	else
-	{
-		block_header_t * block = block_from_ptr(ptr);
-		block_header_t * next = block_next(block);
-
-		const size_t cursize = block_get_size(block);
-		const size_t combined = cursize + block_get_size(next) + block_header_overhead;
-		const size_t adjust = adjust_request_size(size, ALIGN_SIZE);
-
-		tlsf_assert(!block_is_free(block) && "block already marked as free");
-
-		if (adjust > cursize && (!block_is_free(next) || adjust > combined))
-		{
-			p = tlsf_malloc(tlsf, size);
-			if (p)
-			{
-				const size_t minsize = tlsf_min(cursize, size);
-				memcpy(p, ptr, minsize);
-				tlsf_free(tlsf, ptr);
-			}
-		}
-		else
-		{
-			if (adjust > cursize)
-			{
-				block_merge_next(control, block);
-				block_mark_as_used(block);
-			}
-
-			block_trim_used(control, block, adjust);
-			p = ptr;
-		}
-	}
-
-	return p;
-}
-
-void * mm_create(void * mem, size_t bytes)
-{
-	return tlsf_create_with_pool(mem, bytes);
-}
-
-void mm_destroy(void * mm)
-{
-	tlsf_destroy(mm);
-}
-
-void * mm_get_pool(void * mm)
-{
-	return tlsf_get_pool(mm);
-}
-
-void * mm_add_pool(void * mm, void * mem, size_t bytes)
-{
-	return tlsf_add_pool(mm, mem, bytes);
-}
-
-void mm_remove_pool(void * mm, void * pool)
-{
-	tlsf_remove_pool(mm, pool);
-}
-
-void * mm_malloc(void * mm, size_t size)
-{
-	return tlsf_malloc(mm, size);
-}
-
-void * mm_memalign(void * mm, size_t align, size_t size)
-{
-	return tlsf_memalign(mm, align, size);
-}
-
-void * mm_realloc(void * mm, void * ptr, size_t size)
-{
-	return tlsf_realloc(mm, ptr, size);
-}
-
-void mm_free(void * mm, void * ptr)
-{
-	tlsf_free(mm, ptr);
-}
-
-void * malloc(size_t size)
-{
-	return tlsf_malloc(__heap_pool, size);
-}
-
-void * memalign(size_t align, size_t size)
-{
-	return tlsf_memalign(__heap_pool, align, size);
-}
-
-void * realloc(void * ptr, size_t size)
-{
-	return tlsf_realloc(__heap_pool, ptr, size);
-}
-
-void * calloc(size_t nmemb, size_t size)
-{
-	void * ptr;
-
-	if((ptr = malloc(nmemb * size)))
-		memset(ptr, 0, nmemb * size);
-
-	return ptr;
-}
-
-void free(void * ptr)
-{
-	tlsf_free(__heap_pool, ptr);
-}
-
-void do_init_mem_pool(void)
-{
-#ifndef __SANDBOX__
-	extern unsigned char __heap_start;
-	extern unsigned char __heap_end;
-	__heap_pool = tlsf_create_with_pool((void *)&__heap_start, (size_t)(&__heap_end - &__heap_start));
-#else
-	static char __heap_buf[SZ_16M];
-	__heap_pool = tlsf_create_with_pool((void *)__heap_buf, (size_t)(sizeof(__heap_buf)));
-#endif
-}
diff --git a/hw/mcu/allwinner/f1c100s/lib/memcpy.S b/hw/mcu/allwinner/f1c100s/lib/memcpy.S
deleted file mode 100644
index f7ed3130c..000000000
--- a/hw/mcu/allwinner/f1c100s/lib/memcpy.S
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * memcpy.S
- */
-	.text
-
-    .global memcpy
-    .type memcpy, %function
-    .align 4
-
-memcpy:
-	/* determine copy direction */
-	cmp		r1, r0
-	bcc		.Lmemcpy_backwards
-
-	moveq	r0, #0					/* quick abort for len=0 */
-	moveq	pc, lr
-
-	stmdb	sp!, {r0, lr}			/* memcpy() returns dest addr */
-	subs	r2, r2, #4
-	blt		.Lmemcpy_fl4			/* less than 4 bytes */
-	ands	r12, r0, #3
-	bne		.Lmemcpy_fdestul		/* oh unaligned destination addr */
-	ands	r12, r1, #3
-	bne		.Lmemcpy_fsrcul			/* oh unaligned source addr */
-
-.Lmemcpy_ft8:
-	/* we have aligned source and destination */
-	subs	r2, r2, #8
-	blt		.Lmemcpy_fl12			/* less than 12 bytes (4 from above) */
-	subs	r2, r2, #0x14         
-	blt		.Lmemcpy_fl32			/* less than 32 bytes (12 from above) */
-	stmdb	sp!, {r4}				/* borrow r4 */
-
-	/* blat 32 bytes at a time */
-.Lmemcpy_floop32:	
-	ldmia	r1!, {r3, r4, r12, lr}
-	stmia	r0!, {r3, r4, r12, lr}
-	ldmia	r1!, {r3, r4, r12, lr}
-	stmia	r0!, {r3, r4, r12, lr}
-	subs	r2, r2, #0x20         
-	bge		.Lmemcpy_floop32
-
-	cmn		r2, #0x10
-	ldmgeia	r1!, {r3, r4, r12, lr}	/* blat a remaining 16 bytes */
-	stmgeia	r0!, {r3, r4, r12, lr}
-	subge	r2, r2, #0x10         
-	ldmia	sp!, {r4}				/* return r4 */
-
-.Lmemcpy_fl32:
-	adds	r2, r2, #0x14         
-
-	/* blat 12 bytes at a time */
-.Lmemcpy_floop12:
-	ldmgeia	r1!, {r3, r12, lr}
-	stmgeia	r0!, {r3, r12, lr}
-	subges	r2, r2, #0x0c         
-	bge		.Lmemcpy_floop12
-
-.Lmemcpy_fl12:
-	adds	r2, r2, #8
-	blt		.Lmemcpy_fl4
-
-	subs	r2, r2, #4
-	ldrlt	r3, [r1], #4
-	strlt	r3, [r0], #4
-	ldmgeia	r1!, {r3, r12}
-	stmgeia	r0!, {r3, r12}
-	subge	r2, r2, #4
-
-.Lmemcpy_fl4:
-	/* less than 4 bytes to go */
-	adds	r2, r2, #4
-	ldmeqia	sp!, {r0, pc}		/* done */
-
-	/* copy the crud byte at a time */
-	cmp		r2, #2
-	ldrb	r3, [r1], #1
-	strb	r3, [r0], #1
-	ldrgeb	r3, [r1], #1
-	strgeb	r3, [r0], #1
-	ldrgtb	r3, [r1], #1
-	strgtb	r3, [r0], #1
-	ldmia	sp!, {r0, pc}
-
-	/* erg - unaligned destination */
-.Lmemcpy_fdestul:
-	rsb		r12, r12, #4
-	cmp		r12, #2
-
-	/* align destination with byte copies */
-	ldrb	r3, [r1], #1
-	strb	r3, [r0], #1
-	ldrgeb	r3, [r1], #1
-	strgeb	r3, [r0], #1
-	ldrgtb	r3, [r1], #1
-	strgtb	r3, [r0], #1
-	subs	r2, r2, r12
-	blt		.Lmemcpy_fl4		/* less the 4 bytes */
-
-	ands	r12, r1, #3
-	beq		.Lmemcpy_ft8		/* we have an aligned source */
-
-	/* erg - unaligned source */
-	/* This is where it gets nasty ... */
-.Lmemcpy_fsrcul:
-	bic		r1, r1, #3
-	ldr		lr, [r1], #4
-	cmp		r12, #2
-	bgt		.Lmemcpy_fsrcul3
-	beq		.Lmemcpy_fsrcul2
-	cmp		r2, #0x0c
-	blt		.Lmemcpy_fsrcul1loop4
-	sub		r2, r2, #0x0c
-	stmdb	sp!, {r4, r5}
-
-.Lmemcpy_fsrcul1loop16:
-	mov		r3, lr, lsr #8
-	ldmia	r1!, {r4, r5, r12, lr}
-	orr		r3, r3, r4, lsl #24
-	mov		r4, r4, lsr #8
-	orr		r4, r4, r5, lsl #24
-	mov		r5, r5, lsr #8
-	orr		r5, r5, r12, lsl #24
-	mov		r12, r12, lsr #8
-	orr		r12, r12, lr, lsl #24
-	stmia	r0!, {r3-r5, r12}
-	subs	r2, r2, #0x10         
-	bge		.Lmemcpy_fsrcul1loop16
-	ldmia	sp!, {r4, r5}
-	adds	r2, r2, #0x0c         
-	blt		.Lmemcpy_fsrcul1l4
-
-.Lmemcpy_fsrcul1loop4:
-	mov		r12, lr, lsr #8
-	ldr		lr, [r1], #4
-	orr		r12, r12, lr, lsl #24
-	str		r12, [r0], #4
-	subs	r2, r2, #4
-	bge		.Lmemcpy_fsrcul1loop4
-
-.Lmemcpy_fsrcul1l4:
-	sub		r1, r1, #3
-	b		.Lmemcpy_fl4
-
-.Lmemcpy_fsrcul2:
-	cmp		r2, #0x0c
-	blt		.Lmemcpy_fsrcul2loop4
-	sub		r2, r2, #0x0c
-	stmdb	sp!, {r4, r5}
-
-.Lmemcpy_fsrcul2loop16:
-	mov		r3, lr, lsr #16
-	ldmia	r1!, {r4, r5, r12, lr}
-	orr		r3, r3, r4, lsl #16
-	mov		r4, r4, lsr #16
-	orr		r4, r4, r5, lsl #16
-	mov		r5, r5, lsr #16
-	orr		r5, r5, r12, lsl #16
-	mov		r12, r12, lsr #16
-	orr		r12, r12, lr, lsl #16
-	stmia	r0!, {r3-r5, r12}
-	subs	r2, r2, #0x10         
-	bge		.Lmemcpy_fsrcul2loop16
-	ldmia	sp!, {r4, r5}
-	adds	r2, r2, #0x0c         
-	blt		.Lmemcpy_fsrcul2l4
-
-.Lmemcpy_fsrcul2loop4:
-	mov		r12, lr, lsr #16
-	ldr		lr, [r1], #4
-	orr		r12, r12, lr, lsl #16
-	str		r12, [r0], #4
-	subs	r2, r2, #4
-	bge		.Lmemcpy_fsrcul2loop4
-
-.Lmemcpy_fsrcul2l4:
-	sub		r1, r1, #2
-	b		.Lmemcpy_fl4
-
-.Lmemcpy_fsrcul3:
-	cmp		r2, #0x0c
-	blt		.Lmemcpy_fsrcul3loop4
-	sub		r2, r2, #0x0c
-	stmdb	sp!, {r4, r5}
-
-.Lmemcpy_fsrcul3loop16:
-	mov		r3, lr, lsr #24
-	ldmia	r1!, {r4, r5, r12, lr}
-	orr		r3, r3, r4, lsl #8
-	mov		r4, r4, lsr #24
-	orr		r4, r4, r5, lsl #8
-	mov		r5, r5, lsr #24
-	orr		r5, r5, r12, lsl #8
-	mov		r12, r12, lsr #24
-	orr		r12, r12, lr, lsl #8
-	stmia	r0!, {r3-r5, r12}
-	subs	r2, r2, #0x10         
-	bge		.Lmemcpy_fsrcul3loop16
-	ldmia	sp!, {r4, r5}
-	adds	r2, r2, #0x0c         
-	blt		.Lmemcpy_fsrcul3l4
-
-.Lmemcpy_fsrcul3loop4:
-	mov		r12, lr, lsr #24
-	ldr		lr, [r1], #4
-	orr		r12, r12, lr, lsl #8
-	str		r12, [r0], #4
-	subs	r2, r2, #4
-	bge		.Lmemcpy_fsrcul3loop4
-
-.Lmemcpy_fsrcul3l4:
-	sub		r1, r1, #1
-	b		.Lmemcpy_fl4
-
-.Lmemcpy_backwards:
-	add		r1, r1, r2
-	add		r0, r0, r2
-	subs	r2, r2, #4
-	blt		.Lmemcpy_bl4		/* less than 4 bytes */
-	ands	r12, r0, #3
-	bne		.Lmemcpy_bdestul	/* oh unaligned destination addr */
-	ands	r12, r1, #3
-	bne		.Lmemcpy_bsrcul		/* oh unaligned source addr */
-
-.Lmemcpy_bt8:
-	/* we have aligned source and destination */
-	subs	r2, r2, #8
-	blt		.Lmemcpy_bl12		/* less than 12 bytes (4 from above) */
-	stmdb	sp!, {r4, lr}
-	subs	r2, r2, #0x14		/* less than 32 bytes (12 from above) */
-	blt		.Lmemcpy_bl32
-
-	/* blat 32 bytes at a time */
-.Lmemcpy_bloop32:
-	ldmdb	r1!, {r3, r4, r12, lr}
-	stmdb	r0!, {r3, r4, r12, lr}
-	ldmdb	r1!, {r3, r4, r12, lr}
-	stmdb	r0!, {r3, r4, r12, lr}
-	subs	r2, r2, #0x20         
-	bge		.Lmemcpy_bloop32
-
-.Lmemcpy_bl32:
-	cmn	r2, #0x10            
-	ldmgedb	r1!, {r3, r4, r12, lr}	/* blat a remaining 16 bytes */
-	stmgedb	r0!, {r3, r4, r12, lr}
-	subge	r2, r2, #0x10         
-	adds	r2, r2, #0x14         
-	ldmgedb	r1!, {r3, r12, lr}		/* blat a remaining 12 bytes */
-	stmgedb	r0!, {r3, r12, lr}
-	subge	r2, r2, #0x0c         
-	ldmia	sp!, {r4, lr}
-
-.Lmemcpy_bl12:
-	adds	r2, r2, #8
-	blt		.Lmemcpy_bl4
-	subs	r2, r2, #4
-	ldrlt	r3, [r1, #-4]!
-	strlt	r3, [r0, #-4]!
-	ldmgedb	r1!, {r3, r12}
-	stmgedb	r0!, {r3, r12}
-	subge	r2, r2, #4
-
-.Lmemcpy_bl4:
-	/* less than 4 bytes to go */
-	adds	r2, r2, #4
-	moveq	pc, lr
-
-	/* copy the crud byte at a time */
-	cmp		r2, #2
-	ldrb	r3, [r1, #-1]!
-	strb	r3, [r0, #-1]!
-	ldrgeb	r3, [r1, #-1]!
-	strgeb	r3, [r0, #-1]!
-	ldrgtb	r3, [r1, #-1]!
-	strgtb	r3, [r0, #-1]!
-	mov		pc, lr
-
-	/* erg - unaligned destination */
-.Lmemcpy_bdestul:
-	cmp		r12, #2
-
-	/* align destination with byte copies */
-	ldrb	r3, [r1, #-1]!
-	strb	r3, [r0, #-1]!
-	ldrgeb	r3, [r1, #-1]!
-	strgeb	r3, [r0, #-1]!
-	ldrgtb	r3, [r1, #-1]!
-	strgtb	r3, [r0, #-1]!
-	subs	r2, r2, r12
-	blt		.Lmemcpy_bl4		/* less than 4 bytes to go */
-	ands	r12, r1, #3
-	beq		.Lmemcpy_bt8		/* we have an aligned source */
-
-	/* erg - unaligned source */
-	/* This is where it gets nasty ... */
-.Lmemcpy_bsrcul:
-	bic		r1, r1, #3
-	ldr		r3, [r1, #0]
-	cmp		r12, #2
-	blt		.Lmemcpy_bsrcul1
-	beq		.Lmemcpy_bsrcul2
-	cmp		r2, #0x0c
-	blt		.Lmemcpy_bsrcul3loop4
-	sub		r2, r2, #0x0c
-	stmdb	sp!, {r4, r5, lr}
-
-.Lmemcpy_bsrcul3loop16:
-	mov		lr, r3, lsl #8
-	ldmdb	r1!, {r3-r5, r12}
-	orr		lr, lr, r12, lsr #24
-	mov		r12, r12, lsl #8
-	orr		r12, r12, r5, lsr #24
-	mov		r5, r5, lsl #8
-	orr		r5, r5, r4, lsr #24
-	mov		r4, r4, lsl #8
-	orr		r4, r4, r3, lsr #24
-	stmdb	r0!, {r4, r5, r12, lr}
-	subs	r2, r2, #0x10         
-	bge		.Lmemcpy_bsrcul3loop16
-	ldmia	sp!, {r4, r5, lr}
-	adds	r2, r2, #0x0c         
-	blt		.Lmemcpy_bsrcul3l4
-
-.Lmemcpy_bsrcul3loop4:
-	mov		r12, r3, lsl #8
-	ldr		r3, [r1, #-4]!
-	orr		r12, r12, r3, lsr #24
-	str		r12, [r0, #-4]!
-	subs	r2, r2, #4
-	bge		.Lmemcpy_bsrcul3loop4
-
-.Lmemcpy_bsrcul3l4:
-	add		r1, r1, #3
-	b		.Lmemcpy_bl4
-
-.Lmemcpy_bsrcul2:
-	cmp		r2, #0x0c
-	blt		.Lmemcpy_bsrcul2loop4
-	sub		r2, r2, #0x0c
-	stmdb	sp!, {r4, r5, lr}
-
-.Lmemcpy_bsrcul2loop16:
-	mov		lr, r3, lsl #16
-	ldmdb	r1!, {r3-r5, r12}
-	orr		lr, lr, r12, lsr #16
-	mov		r12, r12, lsl #16
-	orr		r12, r12, r5, lsr #16
-	mov		r5, r5, lsl #16
-	orr		r5, r5, r4, lsr #16
-	mov		r4, r4, lsl #16
-	orr		r4, r4, r3, lsr #16
-	stmdb	r0!, {r4, r5, r12, lr}
-	subs	r2, r2, #0x10         
-	bge		.Lmemcpy_bsrcul2loop16
-	ldmia	sp!, {r4, r5, lr}
-	adds	r2, r2, #0x0c         
-	blt		.Lmemcpy_bsrcul2l4
-
-.Lmemcpy_bsrcul2loop4:
-	mov		r12, r3, lsl #16
-	ldr		r3, [r1, #-4]!
-	orr		r12, r12, r3, lsr #16
-	str		r12, [r0, #-4]!
-	subs	r2, r2, #4
-	bge		.Lmemcpy_bsrcul2loop4
-
-.Lmemcpy_bsrcul2l4:
-	add		r1, r1, #2
-	b		.Lmemcpy_bl4
-
-.Lmemcpy_bsrcul1:
-	cmp		r2, #0x0c
-	blt		.Lmemcpy_bsrcul1loop4
-	sub		r2, r2, #0x0c
-	stmdb	sp!, {r4, r5, lr}
-
-.Lmemcpy_bsrcul1loop32:
-	mov		lr, r3, lsl #24
-	ldmdb	r1!, {r3-r5, r12}
-	orr		lr, lr, r12, lsr #8
-	mov		r12, r12, lsl #24
-	orr		r12, r12, r5, lsr #8
-	mov		r5, r5, lsl #24
-	orr		r5, r5, r4, lsr #8
-	mov		r4, r4, lsl #24
-	orr		r4, r4, r3, lsr #8
-	stmdb	r0!, {r4, r5, r12, lr}
-	subs	r2, r2, #0x10         
-	bge		.Lmemcpy_bsrcul1loop32
-	ldmia	sp!, {r4, r5, lr}
-	adds	r2, r2, #0x0c         
-	blt		.Lmemcpy_bsrcul1l4
-
-.Lmemcpy_bsrcul1loop4:
-	mov		r12, r3, lsl #24
-	ldr		r3, [r1, #-4]!
-	orr		r12, r12, r3, lsr #8
-	str		r12, [r0, #-4]!
-	subs	r2, r2, #4
-	bge		.Lmemcpy_bsrcul1loop4
-
-.Lmemcpy_bsrcul1l4:
-	add		r1, r1, #1
-	b		.Lmemcpy_bl4
diff --git a/hw/mcu/allwinner/f1c100s/lib/memset.S b/hw/mcu/allwinner/f1c100s/lib/memset.S
deleted file mode 100644
index 3eea2db1e..000000000
--- a/hw/mcu/allwinner/f1c100s/lib/memset.S
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * memcpy.S
- */
-	.text
-
-    .global memset
-    .type memset, %function
-    .align 4
-
-memset:
-	stmfd	sp!, {r0}				/* remember address for return value */
-	and		r1, r1, #0x000000ff		/* we write bytes */
-
-	cmp		r2, #0x00000004			/* do we have less than 4 bytes */
-	blt		.Lmemset_lessthanfour
-
-	/* first we will word align the address */
-	ands	r3, r0, #0x00000003		/* get the bottom two bits */
-	beq		.Lmemset_addraligned	/* the address is word aligned */
-
-	rsb		r3, r3, #0x00000004
-	sub		r2, r2, r3
-	cmp		r3, #0x00000002
-	strb	r1, [r0], #0x0001		/* set 1 byte */
-	strgeb	r1, [r0], #0x0001		/* set another byte */
-	strgtb	r1, [r0], #0x0001		/* and a third */
-
-	cmp		r2, #0x00000004
-	blt		.Lmemset_lessthanfour
-
-	/* now we must be word aligned */
-.Lmemset_addraligned:
-	orr		r3, r1, r1, lsl #8		/* repeat the byte into a word */
-	orr		r3, r3, r3, lsl #16
-
-	/* we know we have at least 4 bytes ... */
-	cmp		r2, #0x00000020			/* if less than 32 then use words */
-	blt		.Lmemset_lessthan32
-
-	/* we have at least 32 so lets use quad words */
-	stmfd	sp!, {r4-r6}			/* store registers */
-	mov		r4, r3					/* duplicate data */
-	mov		r5, r3
-	mov		r6, r3
-
-.Lmemset_loop16:
-	stmia	r0!, {r3-r6}			/* store 16 bytes */
-	sub		r2, r2, #0x00000010		/* adjust count */
-	cmp		r2, #0x00000010			/* still got at least 16 bytes ? */
-	bgt		.Lmemset_loop16
-
-	ldmfd	sp!, {r4-r6}			/* restore registers */
-
-	/* do we need to set some words as well ? */
-	cmp		r2, #0x00000004
-	blt		.Lmemset_lessthanfour
-
-	/* have either less than 16 or less than 32 depending on route taken */
-.Lmemset_lessthan32:
-
-	/* we have at least 4 bytes so copy as words */
-.Lmemset_loop4:
-	str		r3, [r0], #0x0004
-	sub		r2, r2, #0x0004
-	cmp		r2, #0x00000004
-	bge		.Lmemset_loop4
-
-.Lmemset_lessthanfour:
-	cmp		r2, #0x00000000
-	ldmeqfd	sp!, {r0}
-	moveq	pc, lr					/* zero length so exit */
-
-	cmp		r2, #0x00000002
-	strb	r1, [r0], #0x0001		/* set 1 byte */
-	strgeb	r1, [r0], #0x0001		/* set another byte */
-	strgtb	r1, [r0], #0x0001		/* and a third */
-
-	ldmfd	sp!, {r0}
-	mov		pc, lr					/* exit */
diff --git a/hw/mcu/allwinner/f1c100s/lib/printf.c b/hw/mcu/allwinner/f1c100s/lib/printf.c
deleted file mode 100644
index 366bb9c0b..000000000
--- a/hw/mcu/allwinner/f1c100s/lib/printf.c
+++ /dev/null
@@ -1,757 +0,0 @@
-
-///////////////////////////////////////////////////////////////////////////////
-// \author (c) Marco Paland (info@paland.com)
-//             2014-2018, PALANDesign Hannover, Germany
-//
-// \license The MIT License (MIT)
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy
-// of this software and associated documentation files (the "Software"), to deal
-// in the Software without restriction, including without limitation the rights
-// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-// copies of the Software, and to permit persons to whom the Software is
-// furnished to do so, subject to the following conditions:
-// 
-// The above copyright notice and this permission notice shall be included in
-// all copies or substantial portions of the Software.
-// 
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-// THE SOFTWARE.
-//
-// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on
-//        embedded systems with a very limited resources. These routines are thread
-//        safe and reentrant!
-//        Use this instead of the bloated standard/newlib printf cause these use
-//        malloc for printf (and may not be thread safe).
-//
-///////////////////////////////////////////////////////////////////////////////
-
-#include <stdint.h>
-#include "printf.h"
-
-
-// ntoa conversion buffer size, this must be big enough to hold
-// one converted numeric number including padded zeros (dynamically created on stack)
-// 32 byte is a good default
-#define PRINTF_NTOA_BUFFER_SIZE    32U
-
-// ftoa conversion buffer size, this must be big enough to hold
-// one converted float number including padded zeros (dynamically created on stack)
-// 32 byte is a good default
-#define PRINTF_FTOA_BUFFER_SIZE    32U
-
-// define this to support floating point (%f)
-#define PRINTF_SUPPORT_FLOAT
-
-// define this to support long long types (%llu or %p)
-#define PRINTF_SUPPORT_LONG_LONG
-
-// define this to support the ptrdiff_t type (%t)
-// ptrdiff_t is normally defined in <stddef.h> as long or long long type
-#define PRINTF_SUPPORT_PTRDIFF_T
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-// internal flag definitions
-#define FLAGS_ZEROPAD   (1U <<  0U)
-#define FLAGS_LEFT      (1U <<  1U)
-#define FLAGS_PLUS      (1U <<  2U)
-#define FLAGS_SPACE     (1U <<  3U)
-#define FLAGS_HASH      (1U <<  4U)
-#define FLAGS_UPPERCASE (1U <<  5U)
-#define FLAGS_CHAR      (1U <<  6U)
-#define FLAGS_SHORT     (1U <<  7U)
-#define FLAGS_LONG      (1U <<  8U)
-#define FLAGS_LONG_LONG (1U <<  9U)
-#define FLAGS_PRECISION (1U << 10U)
-
-typedef unsigned char bool;
-#ifndef false
-#define false 0
-#endif
-#ifndef true
-#define true (!false)
-#endif
-extern void sys_uart_putc(char c);
-static char last_ch;
-void _putchar(char character)
-{
-	if(character == 0x0a && last_ch != 0x0d)
-	{
-		sys_uart_putc(0x0d);
-	}
-	sys_uart_putc(character);
-
-}
-
-// output function type
-typedef void (*out_fct_type)(char character, void* buffer, size_t idx, size_t maxlen);
-
-
-// wrapper (used as buffer) for output function type
-typedef struct {
-  void  (*fct)(char character, void* arg);
-  void* arg;
-} out_fct_wrap_type;
-
-
-// internal buffer output
-static inline void _out_buffer(char character, void* buffer, size_t idx, size_t maxlen)
-{
-  if (idx < maxlen) {
-    ((char*)buffer)[idx] = character;
-  }
-}
-
-
-// internal null output
-static inline void _out_null(char character, void* buffer, size_t idx, size_t maxlen)
-{
-  (void)character; (void)buffer; (void)idx; (void)maxlen;
-}
-
-
-// internal _putchar wrapper
-static inline void _out_char(char character, void* buffer, size_t idx, size_t maxlen)
-{
-  (void)buffer; (void)idx; (void)maxlen;
-  if (character) {
-    _putchar(character);
-  }
-}
-
-
-// internal output function wrapper
-static inline void _out_fct(char character, void* buffer, size_t idx, size_t maxlen)
-{
-  (void)idx; (void)maxlen;
-  // buffer is the output fct pointer
-  ((out_fct_wrap_type*)buffer)->fct(character, ((out_fct_wrap_type*)buffer)->arg);
-}
-
-
-// internal strlen
-// \return The length of the string (excluding the terminating 0)
-static inline unsigned int _strlen(const char* str)
-{
-  const char* s;
-  for (s = str; *s; ++s);
-  return (unsigned int)(s - str);
-}
-
-
-// internal test if char is a digit (0-9)
-// \return true if char is a digit
-static inline bool _is_digit(char ch)
-{
-  return (ch >= '0') && (ch <= '9');
-}
-
-
-// internal ASCII string to unsigned int conversion
-static unsigned int _atoi(const char** str)
-{
-  unsigned int i = 0U;
-  while (_is_digit(**str)) {
-    i = i * 10U + (unsigned int)(*((*str)++) - '0');
-  }
-  return i;
-}
-
-
-// internal itoa format
-static size_t _ntoa_format(out_fct_type out, char* buffer, size_t idx, size_t maxlen, char* buf, size_t len, bool negative, unsigned int base, unsigned int prec, unsigned int width, unsigned int flags)
-{
-  const size_t start_idx = idx;
-
-  // pad leading zeros
-  while (!(flags & FLAGS_LEFT) && (len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
-    buf[len++] = '0';
-  }
-  while (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
-    buf[len++] = '0';
-  }
-
-  // handle hash
-  if (flags & FLAGS_HASH) {
-    if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) {
-      len--;
-      if (len && (base == 16U)) {
-        len--;
-      }
-    }
-    if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
-      buf[len++] = 'x';
-    }
-    else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
-      buf[len++] = 'X';
-    }
-    else if ((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
-      buf[len++] = 'b';
-    }
-    if (len < PRINTF_NTOA_BUFFER_SIZE) {
-      buf[len++] = '0';
-    }
-  }
-
-  // handle sign
-  if (len && (len == width) && (negative || (flags & FLAGS_PLUS) || (flags & FLAGS_SPACE))) {
-    len--;
-  }
-  if (len < PRINTF_NTOA_BUFFER_SIZE) {
-    if (negative) {
-      buf[len++] = '-';
-    }
-    else if (flags & FLAGS_PLUS) {
-      buf[len++] = '+';  // ignore the space if the '+' exists
-    }
-    else if (flags & FLAGS_SPACE) {
-      buf[len++] = ' ';
-    }
-  }
-
-  // pad spaces up to given width
-  if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) {
-    for (size_t i = len; i < width; i++) {
-      out(' ', buffer, idx++, maxlen);
-    }
-  }
-
-  // reverse string
-  for (size_t i = 0U; i < len; i++) {
-    out(buf[len - i - 1U], buffer, idx++, maxlen);
-  }
-
-  // append pad spaces up to given width
-  if (flags & FLAGS_LEFT) {
-    while (idx - start_idx < width) {
-      out(' ', buffer, idx++, maxlen);
-    }
-  }
-
-  return idx;
-}
-
-
-// internal itoa for 'long' type
-static size_t _ntoa_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, unsigned long base, unsigned int prec, unsigned int width, unsigned int flags)
-{
-  char buf[PRINTF_NTOA_BUFFER_SIZE];
-  size_t len = 0U;
-
-  // no hash for 0 values
-  if (!value) {
-    flags &= ~FLAGS_HASH;
-  }
-
-  // write if precision != 0 and value is != 0
-  if (!(flags & FLAGS_PRECISION) || value) {
-    do {
-      const char digit = (char)(value % base);
-      buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;
-      value /= base;
-    } while (value && (len < PRINTF_NTOA_BUFFER_SIZE));
-  }
-
-  return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags);
-}
-
-
-// internal itoa for 'long long' type
-#if defined(PRINTF_SUPPORT_LONG_LONG)
-static size_t _ntoa_long_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long long value, bool negative, unsigned long long base, unsigned int prec, unsigned int width, unsigned int flags)
-{
-  char buf[PRINTF_NTOA_BUFFER_SIZE];
-  size_t len = 0U;
-
-  // no hash for 0 values
-  if (!value) {
-    flags &= ~FLAGS_HASH;
-  }
-
-  // write if precision != 0 and value is != 0
-  if (!(flags & FLAGS_PRECISION) || value) {
-    do {
-      const char digit = (char)(value % base);
-      buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;
-      value /= base;
-    } while (value && (len < PRINTF_NTOA_BUFFER_SIZE));
-  }
-
-  return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags);
-}
-#endif  // PRINTF_SUPPORT_LONG_LONG
-
-
-#if defined(PRINTF_SUPPORT_FLOAT)
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wfloat-equal"
-
-static size_t _ftoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags)
-{
-  const size_t start_idx = idx;
-
-  char buf[PRINTF_FTOA_BUFFER_SIZE];
-  size_t len  = 0U;
-  double diff = 0.0;
-
-  // if input is larger than thres_max, revert to exponential
-  const double thres_max = (double)0x7FFFFFFF;
-
-  // powers of 10
-  static const double pow10[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000 };
-
-  // test for negative
-  bool negative = false;
-  if (value < 0) {
-    negative = true;
-    value = 0 - value;
-  }
-
-  // set default precision to 6, if not set explicitly
-  if (!(flags & FLAGS_PRECISION)) {
-    prec = 6U;
-  }
-  // limit precision to 9, cause a prec >= 10 can lead to overflow errors
-  while ((len < PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) {
-    buf[len++] = '0';
-    prec--;
-  }
-
-  int whole = (int)value;
-  double tmp = (value - whole) * pow10[prec];
-  unsigned long frac = (unsigned long)tmp;
-  diff = tmp - frac;
-
-  if (diff > 0.5l) {
-    ++frac;
-    // handle rollover, e.g. case 0.99 with prec 1 is 1.0
-    if (frac >= pow10[prec]) {
-      frac = 0;
-      ++whole;
-    }
-  }
-  else if ((diff == 0.5l) && ((frac == 0U) || (frac & 1U))) {
-    // if halfway, round up if odd, OR if last digit is 0
-    ++frac;
-  }
-
-  // TBD: for very large numbers switch back to native sprintf for exponentials. Anyone want to write code to replace this?
-  // Normal printf behavior is to print EVERY whole number digit which can be 100s of characters overflowing your buffers == bad
-  if (value > thres_max) {
-    return 0U;
-  }
-
-  if (prec == 0U) {
-    diff = value - (double)whole;
-    if (diff > 0.5l) {
-      // greater than 0.5, round up, e.g. 1.6 -> 2
-      ++whole;
-    }
-    else if ((diff == 0.5l) && (whole & 1)) {
-      // exactly 0.5 and ODD, then round up
-      // 1.5 -> 2, but 2.5 -> 2
-      ++whole;
-    }
-  }
-  else {
-    unsigned int count = prec;
-    // now do fractional part, as an unsigned number
-    while (len < PRINTF_FTOA_BUFFER_SIZE) {
-      --count;
-      buf[len++] = (char)(48U + (frac % 10U));
-      if (!(frac /= 10U)) {
-        break;
-      }
-    }
-    // add extra 0s
-    while ((len < PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) {
-      buf[len++] = '0';
-    }
-    if (len < PRINTF_FTOA_BUFFER_SIZE) {
-      // add decimal
-      buf[len++] = '.';
-    }
-  }
-
-  // do whole part, number is reversed
-  while (len < PRINTF_FTOA_BUFFER_SIZE) {
-    buf[len++] = (char)(48 + (whole % 10));
-    if (!(whole /= 10)) {
-      break;
-    }
-  }
-
-  // pad leading zeros
-  while (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_FTOA_BUFFER_SIZE)) {
-    buf[len++] = '0';
-  }
-
-  // handle sign
-  if ((len == width) && (negative || (flags & FLAGS_PLUS) || (flags & FLAGS_SPACE))) {
-    len--;
-  }
-  if (len < PRINTF_FTOA_BUFFER_SIZE) {
-    if (negative) {
-      buf[len++] = '-';
-    }
-    else if (flags & FLAGS_PLUS) {
-      buf[len++] = '+';  // ignore the space if the '+' exists
-    }
-    else if (flags & FLAGS_SPACE) {
-      buf[len++] = ' ';
-    }
-  }
-
-  // pad spaces up to given width
-  if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) {
-    for (size_t i = len; i < width; i++) {
-      out(' ', buffer, idx++, maxlen);
-    }
-  }
-
-  // reverse string
-  for (size_t i = 0U; i < len; i++) {
-    out(buf[len - i - 1U], buffer, idx++, maxlen);
-  }
-
-  // append pad spaces up to given width
-  if (flags & FLAGS_LEFT) {
-    while (idx - start_idx < width) {
-      out(' ', buffer, idx++, maxlen);
-    }
-  }
-
-  return idx;
-}
-#pragma GCC diagnostic pop
-#endif  // PRINTF_SUPPORT_FLOAT
-
-
-// internal vsnprintf
-static int _vsnprintf(out_fct_type out, char* buffer, const size_t maxlen, const char* format, va_list va)
-{
-  unsigned int flags, width, precision, n;
-  size_t idx = 0U;
-
-  if (!buffer) {
-    // use null output function
-    out = _out_null;
-  }
-
-  while (*format)
-  {
-    // format specifier?  %[flags][width][.precision][length]
-    if (*format != '%') {
-      // no
-      out(*format, buffer, idx++, maxlen);
-      format++;
-      continue;
-    }
-    else {
-      // yes, evaluate it
-      format++;
-    }
-
-    // evaluate flags
-    flags = 0U;
-    do {
-      switch (*format) {
-        case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break;
-        case '-': flags |= FLAGS_LEFT;    format++; n = 1U; break;
-        case '+': flags |= FLAGS_PLUS;    format++; n = 1U; break;
-        case ' ': flags |= FLAGS_SPACE;   format++; n = 1U; break;
-        case '#': flags |= FLAGS_HASH;    format++; n = 1U; break;
-        default :                                   n = 0U; break;
-      }
-    } while (n);
-
-    // evaluate width field
-    width = 0U;
-    if (_is_digit(*format)) {
-      width = _atoi(&format);
-    }
-    else if (*format == '*') {
-      const int w = va_arg(va, int);
-      if (w < 0) {
-        flags |= FLAGS_LEFT;    // reverse padding
-        width = (unsigned int)-w;
-      }
-      else {
-        width = (unsigned int)w;
-      }
-      format++;
-    }
-
-    // evaluate precision field
-    precision = 0U;
-    if (*format == '.') {
-      flags |= FLAGS_PRECISION;
-      format++;
-      if (_is_digit(*format)) {
-        precision = _atoi(&format);
-      }
-      else if (*format == '*') {
-        const int prec = (int)va_arg(va, int);
-        precision = prec > 0 ? (unsigned int)prec : 0U;
-        format++;
-      }
-    }
-
-    // evaluate length field
-    switch (*format) {
-      case 'l' :
-        flags |= FLAGS_LONG;
-        format++;
-        if (*format == 'l') {
-          flags |= FLAGS_LONG_LONG;
-          format++;
-        }
-        break;
-      case 'h' :
-        flags |= FLAGS_SHORT;
-        format++;
-        if (*format == 'h') {
-          flags |= FLAGS_CHAR;
-          format++;
-        }
-        break;
-#if defined(PRINTF_SUPPORT_PTRDIFF_T)
-      case 't' :
-        flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
-        format++;
-        break;
-#endif
-      case 'j' :
-        flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
-        format++;
-        break;
-      case 'z' :
-        flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
-        format++;
-        break;
-      default :
-        break;
-    }
-
-    // evaluate specifier
-    switch (*format) {
-      case 'd' :
-      case 'i' :
-      case 'u' :
-      case 'x' :
-      case 'X' :
-      case 'o' :
-      case 'b' : {
-        // set the base
-        unsigned int base;
-        if (*format == 'x' || *format == 'X') {
-          base = 16U;
-        }
-        else if (*format == 'o') {
-          base =  8U;
-        }
-        else if (*format == 'b') {
-          base =  2U;
-        }
-        else {
-          base = 10U;
-          flags &= ~FLAGS_HASH;   // no hash for dec format
-        }
-        // uppercase
-        if (*format == 'X') {
-          flags |= FLAGS_UPPERCASE;
-        }
-
-        // no plus or space flag for u, x, X, o, b
-        if ((*format != 'i') && (*format != 'd')) {
-          flags &= ~(FLAGS_PLUS | FLAGS_SPACE);
-        }
-
-        // ignore '0' flag when precision is given
-        if (flags & FLAGS_PRECISION) {
-          flags &= ~FLAGS_ZEROPAD;
-        }
-
-        // convert the integer
-        if ((*format == 'i') || (*format == 'd')) {
-          // signed
-          if (flags & FLAGS_LONG_LONG) {
-#if defined(PRINTF_SUPPORT_LONG_LONG)
-            const long long value = va_arg(va, long long);
-            idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
-#endif
-          }
-          else if (flags & FLAGS_LONG) {
-            const long value = va_arg(va, long);
-            idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
-          }
-          else {
-            const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) : (flags & FLAGS_SHORT) ? (short int)va_arg(va, int) : va_arg(va, int);
-            idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
-          }
-        }
-        else {
-          // unsigned
-          if (flags & FLAGS_LONG_LONG) {
-#if defined(PRINTF_SUPPORT_LONG_LONG)
-            idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, precision, width, flags);
-#endif
-          }
-          else if (flags & FLAGS_LONG) {
-            idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags);
-          }
-          else {
-            const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char)va_arg(va, unsigned int) : (flags & FLAGS_SHORT) ? (unsigned short int)va_arg(va, unsigned int) : va_arg(va, unsigned int);
-            idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags);
-          }
-        }
-        format++;
-        break;
-      }
-#if defined(PRINTF_SUPPORT_FLOAT)
-      case 'f' :
-      case 'F' :
-        idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags);
-        format++;
-        break;
-#endif  // PRINTF_SUPPORT_FLOAT
-      case 'c' : {
-        unsigned int l = 1U;
-        // pre padding
-        if (!(flags & FLAGS_LEFT)) {
-          while (l++ < width) {
-            out(' ', buffer, idx++, maxlen);
-          }
-        }
-        // char output
-        out((char)va_arg(va, int), buffer, idx++, maxlen);
-        // post padding
-        if (flags & FLAGS_LEFT) {
-          while (l++ < width) {
-            out(' ', buffer, idx++, maxlen);
-          }
-        }
-        format++;
-        break;
-      }
-
-      case 's' : {
-        char* p = va_arg(va, char*);
-        unsigned int l = _strlen(p);
-        // pre padding
-        if (flags & FLAGS_PRECISION) {
-          l = (l < precision ? l : precision);
-        }
-        if (!(flags & FLAGS_LEFT)) {
-          while (l++ < width) {
-            out(' ', buffer, idx++, maxlen);
-          }
-        }
-        // string output
-        while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) {
-          out(*(p++), buffer, idx++, maxlen);
-        }
-        // post padding
-        if (flags & FLAGS_LEFT) {
-          while (l++ < width) {
-            out(' ', buffer, idx++, maxlen);
-          }
-        }
-        format++;
-        break;
-      }
-
-      case 'p' : {
-        width = sizeof(void*) * 2U;
-        flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE;
-#if defined(PRINTF_SUPPORT_LONG_LONG)
-        const bool is_ll = sizeof(uintptr_t) == sizeof(long long);
-        if (is_ll) {
-          idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t)va_arg(va, void*), false, 16U, precision, width, flags);
-        }
-        else {
-#endif
-          idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)((uintptr_t)va_arg(va, void*)), false, 16U, precision, width, flags);
-#if defined(PRINTF_SUPPORT_LONG_LONG)
-        }
-#endif
-        format++;
-        break;
-      }
-
-      case '%' :
-        out('%', buffer, idx++, maxlen);
-        format++;
-        break;
-
-      default :
-        out(*format, buffer, idx++, maxlen);
-        format++;
-        break;
-    }
-  }
-
-  // termination
-  out((char)0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen);
-
-  // return written chars without terminating \0
-  return (int)idx;
-}
-
-
-///////////////////////////////////////////////////////////////////////////////
-
-
-int printf(const char* format, ...)
-{
-  va_list va;
-  va_start(va, format);
-  char buffer[1];
-  const int ret = _vsnprintf(_out_char, buffer, (size_t)-1, format, va);
-  va_end(va);
-  return ret;
-}
-
-
-int sprintf(char* buffer, const char* format, ...)
-{
-  va_list va;
-  va_start(va, format);
-  const int ret = _vsnprintf(_out_buffer, buffer, (size_t)-1, format, va);
-  va_end(va);
-  return ret;
-}
-
-
-int snprintf(char* buffer, size_t count, const char* format, ...)
-{
-  va_list va;
-  va_start(va, format);
-  const int ret = _vsnprintf(_out_buffer, buffer, count, format, va);
-  va_end(va);
-  return ret;
-}
-
-
-int vsnprintf(char* buffer, size_t count, const char* format, va_list va)
-{
-  return _vsnprintf(_out_buffer, buffer, count, format, va);
-}
-
-
-int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...)
-{
-  va_list va;
-  va_start(va, format);
-  out_fct_wrap_type out_fct_wrap = { out, arg };
-  const int ret = _vsnprintf(_out_fct, (char*)&out_fct_wrap, (size_t)-1, format, va);
-  va_end(va);
-  return ret;
-}
diff --git a/hw/mcu/allwinner/f1c100s/machine/exception.c b/hw/mcu/allwinner/f1c100s/machine/exception.c
deleted file mode 100644
index ffc61bf47..000000000
--- a/hw/mcu/allwinner/f1c100s/machine/exception.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * exception.c
- *
- * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
- * Official site: http://xboot.org
- * Mobile phone: +86-18665388956
- * QQ: 8192542
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-#include <stdio.h>
-#include <arm32.h>
-#include <string.h>
-
-static void show_regs(struct arm_regs_t * regs)
-{
-	int i;
-
-	printf("pc : [<%08lx>] lr : [<%08lx>] cpsr: %08lx\r\n", regs->pc, regs->lr, regs->cpsr);
-	printf("sp : %08lx\r\n", regs->sp);
-	for(i = 12; i >= 0; i--)
-	{
-        printf("r%-2d: %08lx ", i, regs->r[i]);
-	 	if(i % 2 == 0)
-	 		printf("\r\n");
-	 }
-    printf("\r\n");
-}
-
-void arm32_do_undefined_instruction(struct arm_regs_t * regs)
-{
-	//gdbserver_handle_exception(regs);
-}
-
-void arm32_do_software_interrupt(struct arm_regs_t * regs)
-{
-	show_regs(regs);
-	regs->pc += 4;
-}
-
-void arm32_do_prefetch_abort(struct arm_regs_t * regs)
-{
-	show_regs(regs);
-	regs->pc += 4;
-}
-
-void arm32_do_data_abort(struct arm_regs_t * regs)
-{
-	show_regs(regs);
-	regs->pc += 4;
-}
-
-_Noreturn void __fatal_error(const char *msg) {
-    printf("%s\n", msg);
-    while (1);
-}
-
-#ifndef NDEBUG
-_Noreturn void __assert_func(const char *file, int line, const char *func, const char *expr) {
-    //printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line);
-    __fatal_error("Assertion failed");
-}
-#endif
\ No newline at end of file
diff --git a/hw/mcu/allwinner/f1c100s/machine/f1c100s-intc.c b/hw/mcu/allwinner/f1c100s/machine/f1c100s-intc.c
deleted file mode 100644
index 2993f0b60..000000000
--- a/hw/mcu/allwinner/f1c100s/machine/f1c100s-intc.c
+++ /dev/null
@@ -1,173 +0,0 @@
-// Originally designed by Hong Xuyao
-
-#include <stdint.h>
-#include <stdio.h>
-#include <f1c100s-irq.h>
-#include <arm32.h>
-
-#define __irq  __attribute__ ((interrupt ("IRQ")))
-
-#ifndef __IO
-#define __IO volatile
-#endif
-
-typedef struct {
-  __IO uint32_t INTC_VECTOR_REG;    // 0x00
-  __IO uint32_t INTC_BASE_ADDR_REG; // 0x04
-  uint32_t resv1[1];                // 0x08
-  __IO uint32_t NMI_INT_CTRL_REG;   // 0x0c
-  __IO uint32_t INTC_PEND_REG[2];   // 0x10
-  uint32_t resv2[2];                // 0x18
-  __IO uint32_t INTC_EN_REG[2];     // 0x20
-  uint32_t resv3[2];                // 0x28
-  __IO uint32_t INTC_MASK_REG[2];   // 0x30
-  uint32_t resv4[2];                // 0x38
-  __IO uint32_t INTC_RESP_REG[2];   // 0x40
-  uint32_t resv5[2];                // 0x48
-  __IO uint32_t INTC_FF_REG[2];     // 0x50
-  uint32_t resv6[2];                // 0x58
-  __IO uint32_t INTC_PRIO_REG[4];   // 0x60
-} INTC_TypeDef;
-
-#ifndef COUNTOF
-#define COUNTOF(ar) (sizeof(ar)/sizeof(ar[0]))
-#endif
-
-#define INTC  ((INTC_TypeDef*)0x01C20400)
-
-static IRQHandleTypeDef irq_table[64] __attribute__((used, aligned(32)));
-
-void arm32_do_irq(struct arm_regs_t * regs)
-{
-  uint8_t nIRQ = f1c100s_intc_get_nirq();
-
-  // ForceIRQ flag must be cleared by ISR
-  // Otherwise ISR will be entered repeatedly
-  INTC->INTC_FF_REG[nIRQ / 32] &= ~(1 << nIRQ);
-  // Call the drivers ISR
-  f1c100s_intc_dispatch(nIRQ);
-  // Clear pending at the end of ISR
-  f1c100s_intc_clear_pend(nIRQ);
-}
-
-void arm32_do_fiq(struct arm_regs_t * regs)
-{
-  // Call the drivers ISR
-  f1c100s_intc_dispatch(0);
-  // Clear pending at the end of ISR.
-  f1c100s_intc_clear_pend(0);
-}
-
-/*
-* Read active IRQ number
-* @return: none
-*/
-uint8_t f1c100s_intc_get_nirq(void)
-{
-  return ((INTC->INTC_VECTOR_REG >> 2) & 0x3F);
-}
-
-/*
-* Execute ISR corresponding to IRQ number
-* @nIRQ: IRQ number
-* @return: none
-*/
-void f1c100s_intc_dispatch(uint8_t nIRQ)
-{
-  IRQHandleTypeDef handle = irq_table[nIRQ];
-  if (handle)
-    handle();
-}
-
-/*
-* Set handler function for specified IRQ
-* @nIRQ: IRQ number
-* @handle: Handle function
-* @return: none
-*/
-void f1c100s_intc_set_isr(uint8_t nIRQ, IRQHandleTypeDef handle)
-{
-  if (nIRQ < COUNTOF(irq_table)) {
-    irq_table[nIRQ] = handle;
-  }
-}
-
-/*
-* Enable IRQ
-* @nIRQ: IRQ number
-* @return: none
-*/
-void f1c100s_intc_enable_irq(uint8_t nIRQ)
-{
-  INTC->INTC_EN_REG[nIRQ / 32] |= (1 << (nIRQ % 32));
-}
-
-/*
-* Disable IRQ
-* @nIRQ: IRQ number
-* @return: none
-*/
-void f1c100s_intc_disable_irq(uint8_t nIRQ)
-{
-  INTC->INTC_EN_REG[nIRQ / 32] &= ~(1 << (nIRQ % 32));
-}
-
-/*
-* Mask IRQ
-* @nIRQ: IRQ number
-* @return: none
-*/
-void f1c100s_intc_mask_irq(uint8_t nIRQ)
-{
-  INTC->INTC_MASK_REG[nIRQ / 32] |= (1 << (nIRQ % 32));
-}
-
-/*
-* Unmask IRQ
-* @nIRQ: IRQ number
-* @return: none
-*/
-void f1c100s_intc_unmask_irq(uint8_t nIRQ)
-{
-  INTC->INTC_MASK_REG[nIRQ / 32] &= ~(1 << (nIRQ % 32));
-}
-
-/*
-* Immediately trigger IRQ
-* @nIRQ: IRQ number
-* @return: none
-*/
-void f1c100s_intc_force_irq(uint8_t nIRQ)
-{
-  // This bit is to be cleared in IRQ handler
-  INTC->INTC_FF_REG[nIRQ / 32] = (1 << (nIRQ % 32));
-}
-
-/*
-* Clear pending flag
-* @nIRQ: IRQ number
-* @return: none
-*/
-void f1c100s_intc_clear_pend(uint8_t nIRQ)
-{
-  INTC->INTC_PEND_REG[nIRQ / 32] = (1 << (nIRQ % 32));
-}
-
-
-/*
-* Initialize IRQ module
-* @return: none
-*/
-void f1c100s_intc_init(void)
-{
-  INTC->INTC_EN_REG[0] = INTC->INTC_EN_REG[1] = 0;
-  INTC->INTC_MASK_REG[0] = INTC->INTC_MASK_REG[1] = 0;
-  INTC->INTC_FF_REG[0] = INTC->INTC_FF_REG[1] = 0;
-  INTC->INTC_RESP_REG[0] = INTC->INTC_RESP_REG[1] = 0;
-  INTC->INTC_PEND_REG[0] = INTC->INTC_PEND_REG[1] = ~0UL;
-  INTC->INTC_BASE_ADDR_REG = 0;
-  INTC->NMI_INT_CTRL_REG = 0;
-  for (unsigned int i = 0; i < COUNTOF(irq_table); i++) {
-    irq_table[i] = 0;
-  }
-}
diff --git a/hw/mcu/allwinner/f1c100s/machine/start.S b/hw/mcu/allwinner/f1c100s/machine/start.S
deleted file mode 100644
index befb22148..000000000
--- a/hw/mcu/allwinner/f1c100s/machine/start.S
+++ /dev/null
@@ -1,314 +0,0 @@
-/*
- * start.S
- *
- * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
- * Official site: http://xboot.org
- * Mobile phone: +86-18665388956
- * QQ: 8192542
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-/*
- * Exception vector table
- */
-.text
-	.arm
-
-	.global	_start
-_start:
-	/* Boot head information for BROM */
-	.long 0xea000016
-	.byte 'e', 'G', 'O', 'N', '.', 'B', 'T', '0'
-	.long 0, __bootloader_size
-	.byte 'S', 'P', 'L', 2
-	.long 0, 0
-	.long 0, 0, 0, 0, 0, 0, 0, 0
-	.long 0, 0, 0, 0, 0, 0, 0, 0	/* 0x40 - boot params, 0x58 - fel boot type, 0x5c - dram size */
-
-_vector:
-	b reset
-	ldr pc, _undefined_instruction
-	ldr pc, _software_interrupt
-	ldr pc, _prefetch_abort
-	ldr pc, _data_abort
-	ldr pc, _not_used
-	ldr pc, _irq
-	ldr pc, _fiq
-
-_undefined_instruction:
-	.word undefined_instruction
-_software_interrupt:
-	.word software_interrupt
-_prefetch_abort:
-	.word prefetch_abort
-_data_abort:
-	.word data_abort
-_not_used:
-	.word not_used
-_irq:
-	.word irq
-_fiq:
-	.word fiq
-
-/*
- * The actual reset code
- */
-reset:
-	/* Save boot params to 0x00000040 */
-	ldr r0, =0x00000040
-	str sp, [r0, #0]
-	str lr, [r0, #4]
-	mrs lr, cpsr
-	str lr, [r0, #8]
-	mrc p15, 0, lr, c1, c0, 0
-	str lr, [r0, #12]
-	mrc p15, 0, lr, c1, c0, 0
-	str lr, [r0, #16]
-
-	/* Check boot type just for fel */
-	mov r0, #0x0
-	ldr r1, [r0, #8]
-	ldr r2, =0x4c45462e
-	cmp r1, r2
-	bne 1f
-	ldr r1, =0x1
-	str r1, [r0, #0x58]
-1:	nop
-
-	/* Enter svc mode and mask interrupts */
-	mrs r0, cpsr
-	bic r0, r0, #0x1f
-	orr r0, r0, #0xd3
-	msr cpsr, r0
-
-	/* Set vector to the low address */
-	mrc p15, 0, r0, c1, c0, 0
-	bic r0, #(1<<13)
-	mcr p15, 0, r0, c1, c0, 0
-
-	/* Copy vector to the correct address */
-	adr r0, _vector
-	mrc p15, 0, r2, c1, c0, 0
-	ands r2, r2, #(1 << 13)
-	ldreq r1, =0x00000000
-	ldrne r1, =0xffff0000
-	ldmia r0!, {r2-r8, r10}
-	stmia r1!, {r2-r8, r10}
-	ldmia r0!, {r2-r8, r10}
-	stmia r1!, {r2-r8, r10}
-
-	/* Initial system clock, ddr and uart */
-	bl sys_clock_init
-	bl sys_uart_init
-
-	/* Check if we are already running from dram */
-	adr r0, _start
-	ldr r1, =_start
-	cmp r0, r1
-	beq _init_mmu
-
-	/* Init dram if not running from dram */
-	bl sys_dram_init
-
-	/* Copy bootloader to faster dram (sram is slower) */
-	ldr r0, =0x81f80000
-	adr r1, _start
-	mov r2, #0x4000
-	bl memcpy
-	ldr r0, =_copy_self
-	ldr r1, =_start
-	sub r0, r0, r1
-	ldr r1, =0x81f80000
-	add r0, r0, r1
-	mov pc, r0
-_init_mmu:
-	bl sys_mmu_init
-	b 1f
-_copy_self:
-	/* Copyself to link address */
-	bl sys_copyself
-
-1:	nop
-	/* Initialize stacks */
-	mrs r0, cpsr
-	bic r0, r0, #0x1f
-	orr r1, r0, #0x1b
-	msr cpsr_cxsf, r1
-	ldr sp, _stack_und_end
-
-	bic r0, r0, #0x1f
-	orr r1, r0, #0x17
-	msr cpsr_cxsf, r1
-	ldr sp, _stack_abt_end
-
-	bic r0, r0, #0x1f
-	orr r1, r0, #0x12
-	msr cpsr_cxsf, r1
-	ldr sp, _stack_irq_end
-
-	bic r0, r0, #0x1f
-	orr r1, r0, #0x11
-	msr cpsr_cxsf, r1
-	ldr sp, _stack_fiq_end
-
-	bic r0, r0, #0x1f
-	orr r1, r0, #0x13
-	msr cpsr_cxsf, r1
-	ldr sp, _stack_srv_end
-
-	/* Copy data section */
-	ldr r0, _data_start
-	ldr r1, _data_shadow_start
-	ldr r2, _data_shadow_end
-	sub r2, r2, r1
-	bl memcpy
-
-	/* Clear bss section */
-	ldr r0, _bss_start
-	ldr r2, _bss_end
-	sub r2, r2, r0
-	mov r1, #0
-	bl memset
-
-	/* Call _main */
-	ldr r1, =_main
-	mov pc, r1
-_main:
-	bl main
-	b _main
-
-	.global return_to_fel
-return_to_fel:
-	mov r0, #0x4
-	mov r1, #'e'
-	strb r1, [r0, #0]
-	mov r1, #'G'
-	strb r1, [r0, #1]
-	mov r1, #'O'
-	strb r1, [r0, #2]
-	mov r1, #'N'
-	strb r1, [r0, #3]
-	mov r1, #'.'
-	strb r1, [r0, #4]
-	mov r1, #'F'
-	strb r1, [r0, #5]
-	mov r1, #'E'
-	strb r1, [r0, #6]
-	mov r1, #'L'
-	strb r1, [r0, #7]
-	ldr r0, =0x00000040
-	ldr sp, [r0, #0]
-	ldr lr, [r0, #4]
-	ldr r1, [r0, #16]
-	mcr p15, 0, r1, c1, c0, 0
-	ldr r1, [r0, #12]
-	mcr p15, 0, r1, c1, c0, 0
-	ldr r1, [r0, #8]
-	msr cpsr, r1
-	bx lr
-
-/*
- * Exception handlers
- */
-	.align 5
-undefined_instruction:
-	b .
-
-	.align 5
-software_interrupt:
-	b .
-
-	.align 5
-prefetch_abort:
-	b .
-
-	.align 5
-data_abort:
-	b .
-
-	.align 5
-not_used:
-	b .
-
-	.align 5
-irq:
-	ldr sp, _stack_irq_end
-	sub sp, sp, #72
-	stmia sp, {r0 - r12}
-	add r8, sp, #60
-	stmdb r8, {sp, lr}^
-	str lr, [r8, #0]
-	mrs r6, spsr
-	str r6, [r8, #4]
-	str r0, [r8, #8]
-	mov r0, sp
-	bl arm32_do_irq
-	ldmia sp, {r0 - lr}^
-	mov r0, r0
-	ldr lr, [sp, #60]
-	add sp, sp, #72
-	subs pc, lr, #4
-
-	.align 5
-fiq:
-	ldr sp, _stack_irq_end
-	sub sp, sp, #72
-	stmia sp, {r0 - r12}
-	add r8, sp, #60
-	stmdb r8, {sp, lr}^
-	str lr, [r8, #0]
-	mrs r6, spsr
-	str r6, [r8, #4]
-	str r0, [r8, #8]
-	mov r0, sp
-	bl arm32_do_fiq
-	ldmia sp, {r0 - lr}^
-	mov r0, r0
-	ldr lr, [sp, #60]
-	add sp, sp, #72
-	subs pc, lr, #4
-
-/*
- * The location of section
- */
- 	.align 4
-_image_start:
-	.long __image_start
-_image_end:
-	.long __image_end
-_data_shadow_start:
-	.long __data_shadow_start
-_data_shadow_end:
-	.long __data_shadow_end
-_data_start:
-	.long __data_start
-_data_end:
-	.long __data_end
-_bss_start:
-	.long __bss_start
-_bss_end:
-	.long __bss_end
-_stack_und_end:
-	.long __stack_und_end
-_stack_abt_end:
-	.long __stack_abt_end
-_stack_irq_end:
-	.long __stack_irq_end
-_stack_fiq_end:
-	.long __stack_fiq_end
-_stack_srv_end:
-	.long __stack_srv_end
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-clock.c b/hw/mcu/allwinner/f1c100s/machine/sys-clock.c
deleted file mode 100644
index d151dd0c1..000000000
--- a/hw/mcu/allwinner/f1c100s/machine/sys-clock.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * sys-clock.c
- *
- * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
- * Official site: http://xboot.org
- * Mobile phone: +86-18665388956
- * QQ: 8192542
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-//#include <xboot.h>
-#include <stdint.h>
-#include <f1c100s/reg-ccu.h>
-#include <io.h>
-
-static inline void sdelay(int loops)
-{
-	__asm__ __volatile__ ("1:\n" "subs %0, %1, #1\n"
-		"bne 1b":"=r" (loops):"0"(loops));
-}
-
-static void wait_pll_stable(uint32_t base)
-{
-	uint32_t rval = 0;
-	uint32_t time = 0xfff;
-
-	do {
-		rval = read32(base);
-		time--;
-	} while(time && !(rval & (1 << 28)));
-}
-
-static void clock_set_pll_cpu(uint32_t clk)
-{
-	uint32_t n, k, m, p;
-	uint32_t rval = 0;
-	uint32_t div = 0;
-
-	if(clk > 720000000)
-		clk = 720000000;
-
-	if((clk % 24000000) == 0)
-	{
-		div = clk / 24000000;
-		n = div - 1;
-		k = 0;
-		m = 0;
-		p = 0;
-	}
-	else if((clk % 12000000) == 0)
-	{
-		m = 1;
-		div = clk / 12000000;
-		if((div % 3) == 0)
-			k = 2;
-		else if((div % 4) == 0)
-			k = 3;
-		else
-			k = 1;
-		n = (div / (k + 1)) - 1;
-		p = 0;
-	}
-	else
-	{
-		div = clk / 24000000;
-		n = div - 1;
-		k = 0;
-		m = 0;
-		p = 0;
-	}
-
-	rval = read32(F1C100S_CCU_BASE + CCU_PLL_CPU_CTRL);
-	rval &= ~((0x3 << 16) | (0x1f << 8) | (0x3 << 4) | (0x3 << 0));
-	rval |= (1U << 31) | (p << 16) | (n << 8) | (k << 4) | m;
-	write32(F1C100S_CCU_BASE + CCU_PLL_CPU_CTRL, rval);
-	wait_pll_stable(F1C100S_CCU_BASE + CCU_PLL_CPU_CTRL);
-}
-
-void sys_clock_init(void)
-{
-	uint32_t val;
-
-	write32(F1C100S_CCU_BASE + CCU_PLL_STABLE_TIME0, 0x1ff);
-	write32(F1C100S_CCU_BASE + CCU_PLL_STABLE_TIME1, 0x1ff);
-
-	val = read32(F1C100S_CCU_BASE + CCU_CPU_CFG);
-	val &= ~(0x3 << 16);
-	val |= (0x1 << 16);
-	write32(F1C100S_CCU_BASE + CCU_CPU_CFG, val);
-	sdelay(100);
-
-	write32(F1C100S_CCU_BASE + CCU_PLL_VIDEO_CTRL, 0x81004107);
-	sdelay(100);
-	write32(F1C100S_CCU_BASE + CCU_PLL_PERIPH_CTRL, 0x80041800);
-	sdelay(100);
-	write32(F1C100S_CCU_BASE + CCU_AHB_APB_CFG, 0x00003180);
-	sdelay(100);
-
-	val = read32(F1C100S_CCU_BASE + CCU_DRAM_CLK_GATE);
-	val |= (0x1 << 26) | (0x1 << 24);
-	write32(F1C100S_CCU_BASE + CCU_DRAM_CLK_GATE, val);
-	sdelay(100);
-
-	clock_set_pll_cpu(408000000);
-	val = read32(F1C100S_CCU_BASE + CCU_CPU_CFG);
-	val &= ~(0x3 << 16);
-	val |= (0x2 << 16);
-	write32(F1C100S_CCU_BASE + CCU_CPU_CFG, val);
-	sdelay(100);
-}
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-copyself.c b/hw/mcu/allwinner/f1c100s/machine/sys-copyself.c
deleted file mode 100644
index 4116e1265..000000000
--- a/hw/mcu/allwinner/f1c100s/machine/sys-copyself.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * sys-copyself.c
- *
- * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
- * Official site: http://xboot.org
- * Mobile phone: +86-18665388956
- * QQ: 8192542
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-#include <stdint.h>
-
-extern unsigned char __image_start;
-extern unsigned char __image_end;
-extern void return_to_fel(void);
-extern void sys_mmu_init(void);
-extern void sys_uart_putc(char c);
-extern void sys_spi_flash_init(void);
-extern void sys_spi_flash_exit(void);
-extern void sys_spi_flash_read(int addr, void * buf, int count);
-
-enum {
-	BOOT_DEVICE_FEL	= 0,
-	BOOT_DEVICE_SPI	= 1,
-	BOOT_DEVICE_MMC	= 2,
-};
-
-static int get_boot_device(void)
-{
-	uint32_t * t = (void *)0x00000058;
-
-	if(t[0] == 0x1)
-		return BOOT_DEVICE_FEL;
-	return BOOT_DEVICE_SPI;
-}
-
-void sys_copyself(void)
-{
-	int d = get_boot_device();
-	void * mem;
-	uint32_t size;
-
-	if(d == BOOT_DEVICE_FEL)
-	{
-		sys_uart_putc('B');
-		sys_uart_putc('o');
-		sys_uart_putc('o');
-		sys_uart_putc('t');
-		sys_uart_putc(' ');
-		sys_uart_putc('t');
-		sys_uart_putc('o');
-		sys_uart_putc(' ');
-		sys_uart_putc('F');
-		sys_uart_putc('E');
-		sys_uart_putc('L');
-		sys_uart_putc(' ');
-		sys_uart_putc('m');
-		sys_uart_putc('o');
-		sys_uart_putc('d');
-		sys_uart_putc('e');
-		sys_uart_putc('\r');
-		sys_uart_putc('\n');
-		return_to_fel();
-	}
-	else if(d == BOOT_DEVICE_SPI)
-	{
-		sys_uart_putc('B');
-		sys_uart_putc('o');
-		sys_uart_putc('o');
-		sys_uart_putc('t');
-		sys_uart_putc(' ');
-		sys_uart_putc('t');
-		sys_uart_putc('o');
-		sys_uart_putc(' ');
-		sys_uart_putc('S');
-		sys_uart_putc('P');
-		sys_uart_putc('I');
-		sys_uart_putc(' ');
-		sys_uart_putc('m');
-		sys_uart_putc('o');
-		sys_uart_putc('d');
-		sys_uart_putc('e');
-		sys_uart_putc('\r');
-		sys_uart_putc('\n');
-		mem = (void *)&__image_start;
-		size = &__image_end - &__image_start;
-		sys_mmu_init();
-
-		sys_spi_flash_init();
-		sys_spi_flash_read(0, mem, size);
-		sys_spi_flash_exit();
-	}
-	else if(d == BOOT_DEVICE_MMC)
-	{
-		mem = (void *)&__image_start;
-		size = (&__image_end - &__image_start + 512) >> 9;
-	}
-}
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-dram.c b/hw/mcu/allwinner/f1c100s/machine/sys-dram.c
deleted file mode 100644
index a819520a5..000000000
--- a/hw/mcu/allwinner/f1c100s/machine/sys-dram.c
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- * sys-dram.c
- *
- * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
- * Official site: http://xboot.org
- * Mobile phone: +86-18665388956
- * QQ: 8192542
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-#include <stdint.h>
-#include <f1c100s/reg-ccu.h>
-#include <f1c100s/reg-dram.h>
-#include <io.h>
-
-#define PLL_DDR_CLK			(156000000)
-#define SDR_T_CAS			(0x2)
-#define SDR_T_RAS			(0x8)
-#define SDR_T_RCD			(0x3)
-#define SDR_T_RP			(0x3)
-#define SDR_T_WR			(0x3)
-#define SDR_T_RFC			(0xd)
-#define SDR_T_XSR			(0xf9)
-#define SDR_T_RC			(0xb)
-#define SDR_T_INIT			(0x8)
-#define SDR_T_INIT_REF		(0x7)
-#define SDR_T_WTR			(0x2)
-#define SDR_T_RRD			(0x2)
-#define SDR_T_XP			(0x0)
-
-enum dram_type_t
-{
-	DRAM_TYPE_SDR	= 0,
-	DRAM_TYPE_DDR	= 1,
-	DRAM_TYPE_MDDR	= 2,
-};
-
-struct dram_para_t
-{
-	uint32_t base;				/* dram base address */
-	uint32_t size;				/* dram size (unit: MByte) */
-	uint32_t clk;				/* dram work clock (unit: MHz) */
-	uint32_t access_mode;		/* 0: interleave mode 1: sequence mode */
-	uint32_t cs_num;			/* dram chip count  1: one chip  2: two chip */
-	uint32_t ddr8_remap;		/* for 8bits data width DDR 0: normal  1: 8bits */
-	enum dram_type_t sdr_ddr;
-	uint32_t bwidth;			/* dram bus width */
-	uint32_t col_width;		/* column address width */
-	uint32_t row_width;		/* row address width */
-	uint32_t bank_size;		/* dram bank count */
-	uint32_t cas;				/* dram cas */
-};
-
-static inline void sdelay(int loops)
-{
-	__asm__ __volatile__ ("1:\n" "subs %0, %1, #1\n"
-		"bne 1b":"=r" (loops):"0"(loops));
-}
-
-static void dram_delay(int ms)
-{
-	sdelay(ms * 2 * 1000);
-}
-
-static int dram_initial(void)
-{
-	unsigned int time = 0xffffff;
-
-	write32(F1C100S_DRAM_BASE + DRAM_SCTLR, read32(F1C100S_DRAM_BASE + DRAM_SCTLR) | 0x1);
-	while((read32(F1C100S_DRAM_BASE + DRAM_SCTLR) & 0x1) && time--)
-	{
-		if(time == 0)
-			return 0;
-	}
-	return 1;
-}
-
-static int dram_delay_scan(void)
-{
-	unsigned int time = 0xffffff;
-
-	write32(F1C100S_DRAM_BASE + DRAM_DDLYR, read32(F1C100S_DRAM_BASE + DRAM_DDLYR) | 0x1);
-	while((read32(F1C100S_DRAM_BASE + DRAM_DDLYR) & 0x1) && time--)
-	{
-		if(time == 0)
-			return 0;
-	}
-	return 1;
-}
-
-static void dram_set_autofresh_cycle(uint32_t clk)
-{
-	uint32_t val = 0;
-	uint32_t row = 0;
-	uint32_t temp = 0;
-
-	row = read32(F1C100S_DRAM_BASE + DRAM_SCONR);
-	row &= 0x1e0;
-	row >>= 0x5;
-
-	if(row == 0xc)
-	{
-		if(clk >= 1000000)
-		{
-			temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
-			while(temp >= (10000000 >> 6))
-			{
-				temp -= (10000000 >> 6);
-				val++;
-			}
-		}
-		else
-		{
-			val = (clk * 499) >> 6;
-		}
-	}
-	else if(row == 0xb)
-	{
-		if(clk >= 1000000)
-		{
-			temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
-			while(temp >= (10000000 >> 7))
-			{
-				temp -= (10000000 >> 7);
-				val++;
-			}
-		}
-		else
-		{
-			val = (clk * 499) >> 5;
-		}
-	}
-	write32(F1C100S_DRAM_BASE + DRAM_SREFR, val);
-}
-
-static int dram_para_setup(struct dram_para_t * para)
-{
-	uint32_t val = 0;
-
-    val = (para->ddr8_remap) |
-    	(0x1 << 1) |
-		((para->bank_size >> 2) << 3) |
-		((para->cs_num >> 1) << 4) |
-		((para->row_width - 1) << 5) |
-		((para->col_width - 1) << 9) |
-		((para->sdr_ddr ? (para->bwidth >> 4) : (para->bwidth >> 5)) << 13) |
-		(para->access_mode << 15) |
-		(para->sdr_ddr << 16);
-
-	write32(F1C100S_DRAM_BASE + DRAM_SCONR, val);
-	write32(F1C100S_DRAM_BASE + DRAM_SCTLR, read32(F1C100S_DRAM_BASE + DRAM_SCTLR) | (0x1 << 19));
-	return dram_initial();
-}
-
-static uint32_t dram_check_delay(uint32_t bwidth)
-{
-	uint32_t dsize;
-	uint32_t i,j;
-	uint32_t num = 0;
-	uint32_t dflag = 0;
-
-	dsize = ((bwidth == 16) ? 4 : 2);
-	for(i = 0; i < dsize; i++)
-	{
-		if(i == 0)
-			dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR0);
-		else if(i == 1)
-			dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR1);
-		else if(i == 2)
-			dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR2);
-		else if(i == 3)
-			dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR3);
-
-		for(j = 0; j < 32; j++)
-		{
-			if(dflag & 0x1)
-				num++;
-			dflag >>= 1;
-		}
-	}
-	return num;
-}
-
-static int sdr_readpipe_scan(void)
-{
-	uint32_t k = 0;
-
-	for(k = 0; k < 32; k++)
-	{
-		write32(0x80000000 + 4 * k, k);
-	}
-	for(k = 0; k < 32; k++)
-	{
-		if(read32(0x80000000 + 4 * k) != k)
-			return 0;
-	}
-	return 1;
-}
-
-static uint32_t sdr_readpipe_select(void)
-{
-	uint32_t value = 0;
-	uint32_t i = 0;
-	for(i = 0; i < 8; i++)
-	{
-		write32(F1C100S_DRAM_BASE + DRAM_SCTLR, (read32(F1C100S_DRAM_BASE + DRAM_SCTLR) & (~(0x7 << 6))) | (i << 6));
-		if(sdr_readpipe_scan())
-		{
-			value = i;
-			return value;
-		}
-	}
-	return value;
-}
-
-static uint32_t dram_check_type(struct dram_para_t * para)
-{
-	uint32_t val = 0;
-	uint32_t times = 0;
-	uint32_t i;
-
-	for(i = 0; i < 8; i++)
-	{
-		val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
-		val &= ~(0x7 << 6);
-		val |= (i << 6);
-		write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
-
-		dram_delay_scan();
-		if(read32(F1C100S_DRAM_BASE + DRAM_DDLYR) & 0x30)
-			times++;
-	}
-
-	if(times == 8)
-	{
-		para->sdr_ddr = DRAM_TYPE_SDR;
-		return 0;
-	}
-	else
-	{
-		para->sdr_ddr = DRAM_TYPE_DDR;
-		return 1;
-	}
-}
-
-static uint32_t dram_scan_readpipe(struct dram_para_t * para)
-{
-	uint32_t i, rp_best = 0, rp_val = 0;
-	uint32_t val = 0;
-	uint32_t readpipe[8];
-
-	if(para->sdr_ddr == DRAM_TYPE_DDR)
-	{
-		for(i = 0; i < 8; i++)
-		{
-			val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
-			val &= ~(0x7 << 6);
-			val |= (i << 6);
-			write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
-			dram_delay_scan();
-			readpipe[i] = 0;
-			if((((read32(F1C100S_DRAM_BASE + DRAM_DDLYR) >> 4) & 0x3) == 0x0) &&
-				(((read32(F1C100S_DRAM_BASE + DRAM_DDLYR) >> 4) & 0x1) == 0x0))
-			{
-				readpipe[i] = dram_check_delay(para->bwidth);
-			}
-			if(rp_val < readpipe[i])
-			{
-				rp_val = readpipe[i];
-				rp_best = i;
-			}
-		}
-		val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
-		val &= ~(0x7 << 6);
-		val |= (rp_best << 6);
-		write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
-		dram_delay_scan();
-	}
-	else
-	{
-		val = read32(F1C100S_DRAM_BASE + DRAM_SCONR);
-		val &= (~(0x1 << 16));
-		val &= (~(0x3 << 13));
-		write32(F1C100S_DRAM_BASE + DRAM_SCONR, val);
-		rp_best = sdr_readpipe_select();
-		val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
-		val &= ~(0x7 << 6);
-		val |= (rp_best << 6);
-		write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
-	}
-	return 0;
-}
-
-static uint32_t dram_get_dram_size(struct dram_para_t * para)
-{
-	uint32_t colflag = 10, rowflag = 13;
-	uint32_t i = 0;
-	uint32_t val1 = 0;
-	uint32_t count = 0;
-	uint32_t addr1, addr2;
-
-	para->col_width = colflag;
-	para->row_width = rowflag;
-	dram_para_setup(para);
-	dram_scan_readpipe(para);
-	for(i = 0; i < 32; i++)
-	{
-		*((uint32_t *)(0x80000200 + i)) = 0x11111111;
-		*((uint32_t *)(0x80000600 + i)) = 0x22222222;
-	}
-	for(i = 0; i < 32; i++)
-	{
-		val1 = *((uint32_t *)(0x80000200 + i));
-		if(val1 == 0x22222222)
-			count++;
-	}
-	if(count == 32)
-	{
-		colflag = 9;
-	}
-	else
-	{
-		colflag = 10;
-	}
-	count = 0;
-	para->col_width = colflag;
-	para->row_width = rowflag;
-	dram_para_setup(para);
-	if(colflag == 10)
-	{
-		addr1 = 0x80400000;
-		addr2 = 0x80c00000;
-	}
-	else
-	{
-		addr1 = 0x80200000;
-		addr2 = 0x80600000;
-	}
-	for(i = 0; i < 32; i++)
-	{
-		*((uint32_t *)(addr1 + i)) = 0x33333333;
-		*((uint32_t *)(addr2 + i)) = 0x44444444;
-	}
-	for(i = 0; i < 32; i++)
-	{
-		val1 = *((uint32_t *)(addr1 + i));
-		if(val1 == 0x44444444)
-		{
-			count++;
-		}
-	}
-	if(count == 32)
-	{
-		rowflag = 12;
-	}
-	else
-	{
-		rowflag = 13;
-	}
-	para->col_width = colflag;
-	para->row_width = rowflag;
-	if(para->row_width != 13)
-	{
-		para->size = 16;
-	}
-	else if(para->col_width == 10)
-	{
-		para->size = 64;
-	}
-	else
-	{
-		para->size = 32;
-	}
-	dram_set_autofresh_cycle(para->clk);
-	para->access_mode = 0;
-	dram_para_setup(para);
-
-	return 0;
-}
-
-static int dram_init(struct dram_para_t * para)
-{
-	uint32_t val = 0;
-	uint32_t i;
-
-	write32(0x01c20800 + 0x24, read32(0x01c20800 + 0x24) | (0x7 << 12));
-	dram_delay(5);
-	if(((para->cas) >> 3) & 0x1)
-	{
-		write32(0x01c20800 + 0x2c4, read32(0x01c20800 + 0x2c4) | (0x1 << 23) | (0x20 << 17));
-	}
-	if((para->clk >= 144) && (para->clk <= 180))
-	{
-		write32(0x01c20800 + 0x2c0, 0xaaa);
-	}
-	if(para->clk >= 180)
-	{
-		write32(0x01c20800 + 0x2c0, 0xfff);
-	}
-	if((para->clk) <= 96)
-	{
-		val = (0x1 << 0) | (0x0 << 4) | (((para->clk * 2) / 12 - 1) << 8) | (0x1u << 31);
-	}
-	else
-	{
-		val = (0x0 << 0) | (0x0 << 4) | (((para->clk * 2) / 24 - 1) << 8) | (0x1u << 31);
-	}
-
-	if(para->cas & (0x1 << 4))
-	{
-		write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xd1303333);
-	}
-	else if(para->cas & (0x1 << 5))
-	{
-		write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xcce06666);
-	}
-	else if(para->cas & (0x1 << 6))
-	{
-		write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xc8909999);
-	}
-	else if(para->cas & (0x1 << 7))
-	{
-		write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xc440cccc);
-	}
-	if(para->cas & (0xf << 4))
-	{
-		val |= 0x1 << 24;
-	}
-	write32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL, val);
-	write32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL, read32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL) | (0x1 << 20));
-	while((read32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL) & (1 << 28)) == 0);
-	dram_delay(5);
-	write32(F1C100S_CCU_BASE + CCU_BUS_CLK_GATE0, read32(F1C100S_CCU_BASE + CCU_BUS_CLK_GATE0) | (0x1 << 14));
-	write32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0, read32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0) & ~(0x1 << 14));
-	for(i = 0; i < 10; i++)
-		continue;
-	write32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0, read32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0) | (0x1 << 14));
-
-	val = read32(0x01c20800 + 0x2c4);
-	(para->sdr_ddr == DRAM_TYPE_DDR) ? (val |= (0x1 << 16)) : (val &= ~(0x1 << 16));
-	write32(0x01c20800 + 0x2c4, val);
-
-	val = (SDR_T_CAS << 0) | (SDR_T_RAS << 3) | (SDR_T_RCD << 7) | (SDR_T_RP << 10) | (SDR_T_WR << 13) | (SDR_T_RFC << 15) | (SDR_T_XSR << 19) | (SDR_T_RC << 28);
-	write32(F1C100S_DRAM_BASE + DRAM_STMG0R, val);
-	val = (SDR_T_INIT << 0) | (SDR_T_INIT_REF << 16) | (SDR_T_WTR << 20) | (SDR_T_RRD << 22) | (SDR_T_XP << 25);
-	write32(F1C100S_DRAM_BASE + DRAM_STMG1R, val);
-	dram_para_setup(para);
-	dram_check_type(para);
-
-	val = read32(0x01c20800 + 0x2c4);
-	(para->sdr_ddr == DRAM_TYPE_DDR) ? (val |= (0x1 << 16)) : (val &= ~(0x1 << 16));
-	write32(0x01c20800 + 0x2c4, val);
-
-	dram_set_autofresh_cycle(para->clk);
-	dram_scan_readpipe(para);
-	dram_get_dram_size(para);
-
-	for(i = 0; i < 128; i++)
-	{
-		*((volatile uint32_t *)(para->base + 4 * i)) = para->base + 4 * i;
-	}
-
-	for(i = 0; i < 128; i++)
-	{
-		if(*((volatile uint32_t *)(para->base + 4 * i)) != (para->base + 4 * i))
-			return 0;
-	}
-	return 1;
-}
-
-void sys_dram_init(void)
-{
-	struct dram_para_t para;
-	uint32_t * dsz = (void *)0x0000005c;
-
-	para.base = 0x80000000;
-	para.size = 32;
-	para.clk = PLL_DDR_CLK / 1000000;
-	para.access_mode = 1;
-	para.cs_num = 1;
-	para.ddr8_remap = 0;
-	para.sdr_ddr = DRAM_TYPE_DDR;
-	para.bwidth = 16;
-	para.col_width = 10;
-	para.row_width = 13;
-	para.bank_size = 4;
-	para.cas = 0x3;
-
-	if((dsz[0] >> 24) == 'X')
-		return;
-	if(dram_init(&para))
-		dsz[0] = (((uint32_t)'X') << 24) | (para.size << 0);
-}
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-mmu.c b/hw/mcu/allwinner/f1c100s/machine/sys-mmu.c
deleted file mode 100644
index 3c89c7255..000000000
--- a/hw/mcu/allwinner/f1c100s/machine/sys-mmu.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * sys-mmu.c
- *
- * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
- * Official site: http://xboot.org
- * Mobile phone: +86-18665388956
- * QQ: 8192542
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <stdint.h>
-#include <io.h>
-#include <sizes.h>
-#include <arm32.h>
-
-static void map_l1_section(uint32_t * ttb, virtual_addr_t virt, physical_addr_t phys, physical_size_t size, int type)
-{
-	physical_size_t i;
-
-	virt >>= 20;
-	phys >>= 20;
-	size >>= 20;
-	type &= 0x3;
-
-	for(i = size; i > 0; i--, virt++, phys++)
-		ttb[virt] = (phys << 20) | (0x3 << 10) | (0x0 << 5) | (type << 2) | (0x2 << 0);
-}
-
-void sys_mmu_init(void)
-{
-	uint32_t * ttb = (uint32_t *)(0x80000000 + SZ_1M * 31);
-
-	map_l1_section(ttb, 0x00000000, 0x00000000, SZ_2G, 0);
-	map_l1_section(ttb, 0x80000000, 0x80000000, SZ_2G, 0);
-	map_l1_section(ttb, 0x80000000, 0x80000000, SZ_1M * 32, 3);
-
-	arm32_ttb_set((uint32_t)(ttb));
-	arm32_tlb_invalidate();
-	arm32_domain_set(0x3);
-	arm32_mmu_enable();
-	arm32_icache_enable();
-	arm32_dcache_enable();
-}
\ No newline at end of file
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-spi-flash.c b/hw/mcu/allwinner/f1c100s/machine/sys-spi-flash.c
deleted file mode 100644
index 5c3b0f0aa..000000000
--- a/hw/mcu/allwinner/f1c100s/machine/sys-spi-flash.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * sys-spi-flash.c
- *
- * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
- * Official site: http://xboot.org
- * Mobile phone: +86-18665388956
- * QQ: 8192542
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <stdint.h>
-#include <types.h>
-#include <string.h>
-#include <io.h>
-
-enum {
-	SPI_GCR	= 0x04,
-	SPI_TCR	= 0x08,
-	SPI_IER	= 0x10,
-	SPI_ISR	= 0x14,
-	SPI_FCR	= 0x18,
-	SPI_FSR	= 0x1c,
-	SPI_WCR	= 0x20,
-	SPI_CCR	= 0x24,
-	SPI_MBC	= 0x30,
-	SPI_MTC	= 0x34,
-	SPI_BCC	= 0x38,
-	SPI_TXD	= 0x200,
-	SPI_RXD	= 0x300,
-};
-
-void sys_spi_flash_init(void)
-{
-	virtual_addr_t addr;
-	uint32_t val;
-
-	/* Config GPIOC0, GPIOC1, GPIOC2 and GPIOC3 */
-	addr = 0x01c20848 + 0x00;
-	val = read32(addr);
-	val &= ~(0xf << ((0 & 0x7) << 2));
-	val |= ((0x2 & 0x7) << ((0 & 0x7) << 2));
-	write32(addr, val);
-
-	val = read32(addr);
-	val &= ~(0xf << ((1 & 0x7) << 2));
-	val |= ((0x2 & 0x7) << ((1 & 0x7) << 2));
-	write32(addr, val);
-
-	val = read32(addr);
-	val &= ~(0xf << ((2 & 0x7) << 2));
-	val |= ((0x2 & 0x7) << ((2 & 0x7) << 2));
-	write32(addr, val);
-
-	val = read32(addr);
-	val &= ~(0xf << ((3 & 0x7) << 2));
-	val |= ((0x2 & 0x7) << ((3 & 0x7) << 2));
-	write32(addr, val);
-
-	/* Deassert spi0 reset */
-	addr = 0x01c202c0;
-	val = read32(addr);
-	val |= (1 << 20);
-	write32(addr, val);
-
-	/* Open the spi0 bus gate */
-	addr = 0x01c20000 + 0x60;
-	val = read32(addr);
-	val |= (1 << 20);
-	write32(addr, val);
-
-	/* Set spi clock rate control register, divided by 4 */
-	addr = 0x01c05000;
-	write32(addr + SPI_CCR, 0x00001001);
-
-	/* Enable spi0 and do a soft reset */
-	addr = 0x01c05000;
-	val = read32(addr + SPI_GCR);
-	val |= (1 << 31) | (1 << 7) | (1 << 1) | (1 << 0);
-	write32(addr + SPI_GCR, val);
-	while(read32(addr + SPI_GCR) & (1 << 31));
-
-	val = read32(addr + SPI_TCR);
-	val &= ~(0x3 << 0);
-	val |= (1 << 6) | (1 << 2);
-	write32(addr + SPI_TCR, val);
-
-	val = read32(addr + SPI_FCR);
-	val |= (1 << 31) | (1 << 15);
-	write32(addr + SPI_FCR, val);
-}
-
-void sys_spi_flash_exit(void)
-{
-	virtual_addr_t addr = 0x01c05000;
-	uint32_t val;
-
-	/* Disable the spi0 controller */
-	val = read32(addr + SPI_GCR);
-	val &= ~((1 << 1) | (1 << 0));
-	write32(addr + SPI_GCR, val);
-}
-
-static void sys_spi_select(void)
-{
-	virtual_addr_t addr = 0x01c05000;
-	uint32_t val;
-
-	val = read32(addr + SPI_TCR);
-	val &= ~((0x3 << 4) | (0x1 << 7));
-	val |= ((0 & 0x3) << 4) | (0x0 << 7);
-	write32(addr + SPI_TCR, val);
-}
-
-static void sys_spi_deselect(void)
-{
-	virtual_addr_t addr = 0x01c05000;
-	uint32_t val;
-
-	val = read32(addr + SPI_TCR);
-	val &= ~((0x3 << 4) | (0x1 << 7));
-	val |= ((0 & 0x3) << 4) | (0x1 << 7);
-	write32(addr + SPI_TCR, val);
-}
-
-static void sys_spi_write_txbuf(uint8_t * buf, int len)
-{
-	virtual_addr_t addr = 0x01c05000;
-	int i;
-
-	if(!buf)
-		len = 0;
-
-	write32(addr + SPI_MTC, len & 0xffffff);
-	write32(addr + SPI_BCC, len & 0xffffff);
-	for(i = 0; i < len; ++i)
-		write8(addr + SPI_TXD, *buf++);
-}
-
-static int sys_spi_transfer(void * txbuf, void * rxbuf, int len)
-{
-	virtual_addr_t addr = 0x01c05000;
-	int count = len;
-	uint8_t * tx = txbuf;
-	uint8_t * rx = rxbuf;
-	uint8_t val;
-	unsigned int n, i;
-
-	while(count > 0)
-	{
-		n = (count <= 64) ? count : 64;
-		write32(addr + SPI_MBC, n);
-		sys_spi_write_txbuf(tx, n);
-		write32(addr + SPI_TCR, read32(addr + SPI_TCR) | (1 << 31));
-
-		while((read32(addr + SPI_FSR) & 0xff) < n);
-		for(i = 0; i < n; i++)
-		{
-			val = read8(addr + SPI_RXD);
-			if(rx)
-				*rx++ = val;
-		}
-
-		if(tx)
-			tx += n;
-		count -= n;
-	}
-	return len;
-}
-
-static int sys_spi_write_then_read(void * txbuf, int txlen, void * rxbuf, int rxlen)
-{
-	if(sys_spi_transfer(txbuf, NULL, txlen) != txlen)
-		return -1;
-	if(sys_spi_transfer(NULL, rxbuf, rxlen) != rxlen)
-		return -1;
-	return 0;
-}
-
-void sys_spi_flash_read(int addr, void * buf, int count)
-{
-	uint8_t tx[4];
-
-	tx[0] = 0x03;
-	tx[1] = (uint8_t)(addr >> 16);
-	tx[2] = (uint8_t)(addr >> 8);
-	tx[3] = (uint8_t)(addr >> 0);
-	sys_spi_select();
-	sys_spi_write_then_read(tx, 4, buf, count);
-	sys_spi_deselect();
-}
diff --git a/hw/mcu/allwinner/f1c100s/machine/sys-uart.c b/hw/mcu/allwinner/f1c100s/machine/sys-uart.c
deleted file mode 100644
index 0e61627b7..000000000
--- a/hw/mcu/allwinner/f1c100s/machine/sys-uart.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * sys-uart.c
- *
- * Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
- * Official site: http://xboot.org
- * Mobile phone: +86-18665388956
- * QQ: 8192542
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <types.h>
-#include <stdint.h>
-#include <io.h>
-
-void sys_uart_init(void)
-{
-	virtual_addr_t addr;
-	uint32_t val;
-
-	/* Config GPIOE1 and GPIOE0 to txd0 and rxd0 */
-	addr = 0x01c20890 + 0x00;
-	val = read32(addr);
-	val &= ~(0xf << ((1 & 0x7) << 2));
-	val |= ((0x5 & 0x7) << ((1 & 0x7) << 2));
-	write32(addr, val);
-
-	val = read32(addr);
-	val &= ~(0xf << ((0 & 0x7) << 2));
-	val |= ((0x5 & 0x7) << ((0 & 0x7) << 2));
-	write32(addr, val);
-
-	/* Open the clock gate for uart0 */
-	addr = 0x01c20068;
-	val = read32(addr);
-	val |= 1 << 20;
-	write32(addr, val);
-
-	/* Deassert uart0 reset */
-	addr = 0x01c202d0;
-	val = read32(addr);
-	val |= 1 << 20;
-	write32(addr, val);
-
-	/* Config uart0 to 115200-8-1-0 */
-	addr = 0x01c25000;
-	write32(addr + 0x04, 0x0);
-	write32(addr + 0x08, 0xf7);
-	write32(addr + 0x10, 0x0);
-	val = read32(addr + 0x0c);
-	val |= (1 << 7);
-	write32(addr + 0x0c, val);
-	write32(addr + 0x00, 0x36 & 0xff);
-	write32(addr + 0x04, (0x36 >> 8) & 0xff);
-	val = read32(addr + 0x0c);
-	val &= ~(1 << 7);
-	write32(addr + 0x0c, val);
-	val = read32(addr + 0x0c);
-	val &= ~0x1f;
-	val |= (0x3 << 0) | (0 << 2) | (0x0 << 3);
-	write32(addr + 0x0c, val);
-}
-
-void sys_uart_putc(char c)
-{
-	virtual_addr_t addr = 0x01c25000;
-
-	while((read32(addr + 0x7c) & (0x1 << 1)) == 0);
-	write32(addr + 0x00, c);
-}

From b943a53b1066e8a736eb7a32e42af6324a208718 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Dec 2021 19:04:08 +0700
Subject: [PATCH 0756/2085] update allwinner submodule

---
 hw/mcu/allwinner | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/allwinner b/hw/mcu/allwinner
index c56955e15..8e5e89e8e 160000
--- a/hw/mcu/allwinner
+++ b/hw/mcu/allwinner
@@ -1 +1 @@
-Subproject commit c56955e156b1050a4a8ccf8589555148f00a1bb6
+Subproject commit 8e5e89e8e132c0fd90e72d5422e5d3d68232b756

From 84e2f6e0e144614b306f68416958f8f662c8cb46 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Dec 2021 19:12:41 +0700
Subject: [PATCH 0757/2085] skip freertos example for f1c100s

---
 examples/device/cdc_msc_freertos/.skip.MCU_F1C100S       | 0
 examples/device/hid_composite_freertos/.skip.MCU_F1C100S | 0
 hw/bsp/f1c100s/f1c100s.c                                 | 2 +-
 3 files changed, 1 insertion(+), 1 deletion(-)
 create mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_F1C100S
 create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_F1C100S

diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_F1C100S b/examples/device/cdc_msc_freertos/.skip.MCU_F1C100S
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_F1C100S b/examples/device/hid_composite_freertos/.skip.MCU_F1C100S
new file mode 100644
index 000000000..e69de29bb
diff --git a/hw/bsp/f1c100s/f1c100s.c b/hw/bsp/f1c100s/f1c100s.c
index 6cf18597c..d45072ecb 100644
--- a/hw/bsp/f1c100s/f1c100s.c
+++ b/hw/bsp/f1c100s/f1c100s.c
@@ -49,7 +49,7 @@ void board_init(void)
   arch_local_irq_enable();
 }
 
-// No LED, no button, sorry
+// No LED, no button
 void board_led_write(bool state)
 {
 

From 5f280b30290e540f24d55fdd3e0dd46efa251547 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Dec 2021 19:22:39 +0700
Subject: [PATCH 0758/2085] add license to dcd file, slightly update readme

---
 hw/bsp/f1c100s/README.md            |  6 ++++--
 hw/bsp/f1c100s/board.mk             |  4 +++-
 src/osal/osal_rtx4.h                |  1 +
 src/portable/sunxi/dcd_sunxi_musb.c | 27 +++++++++++++++++++++++++++
 src/portable/sunxi/musb_def.h       | 27 +++++++++++++++++++++++++++
 5 files changed, 62 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md
index cc33ca1f4..325044716 100644
--- a/hw/bsp/f1c100s/README.md
+++ b/hw/bsp/f1c100s/README.md
@@ -4,9 +4,11 @@ This folder contains necessary file and scripts to run TinyUSB examples on F1Cx0
 
 Currently tested on:
 
-* Lichee Pi Nano (F1C100s)
+- Lichee Pi Nano (F1C100s)
+- [Widora Tiny200 v2 (also called MangoPi-R3c)](https://mangopi.org/tiny200)
 
 ## Flashing
+
 There are two options to put your code into the MCU: `flash` and `exec`. Both modes require you to install [xfel](https://github.com/xboot/xfel) tool to your PATH. You must enter FEL mode before any operation can be done. To enter FEL mode, press BOOT button, then press RESET once, and release BOOT button. You will find VID/PID=1f3a:efe8 on your PC.
 
 Exec: `make BOARD=f1c100s exec` will just upload the image to the DDR ram and execute it. It will not touch anything in the SPI flash.
@@ -14,5 +16,5 @@ Exec: `make BOARD=f1c100s exec` will just upload the image to the DDR ram and ex
 Flash: `make BOARD=f1c100s flash` will write the image to SPI flash, and then reset the chip to execute it.
 
 ## TODO
-* Test on Tiny200 v2 (F1C200s)
+
 * Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX` high speed MCU check in examples (maybe we should extract the logic?)
\ No newline at end of file
diff --git a/hw/bsp/f1c100s/board.mk b/hw/bsp/f1c100s/board.mk
index 9bd9380a7..5fe26a9ea 100644
--- a/hw/bsp/f1c100s/board.mk
+++ b/hw/bsp/f1c100s/board.mk
@@ -1,3 +1,5 @@
+DEPS_SUBMODULES += hw/mcu/allwinner
+
 DEFINES += -D__ARM32_ARCH__=5 -D__ARM926EJS__
 
 CFLAGS += \
@@ -33,7 +35,7 @@ SRC_C += \
 	$(MCU_DIR)/lib/printf.c 
 
 SRC_S += \
-    $(MCU_DIR)/machine/start.S \
+  $(MCU_DIR)/machine/start.S \
 	$(MCU_DIR)/lib/memcpy.S \
 	$(MCU_DIR)/lib/memset.S
 
diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h
index 93d1a7a28..32d7782d9 100644
--- a/src/osal/osal_rtx4.h
+++ b/src/osal/osal_rtx4.h
@@ -1,6 +1,7 @@
 /* 
  * The MIT License (MIT)
  *
+ * Copyright (c) 2021 Tian Yunhao (t123yh)
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index be1847b21..3d39248c1 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -1,3 +1,30 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Tian Yunhao (t123yh)
+ * Copyright (c) 2021 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
 #include <stdint.h>
 #include "tusb_option.h"
 #include "osal/osal.h"
diff --git a/src/portable/sunxi/musb_def.h b/src/portable/sunxi/musb_def.h
index f55ddab3b..e0c8a5e20 100644
--- a/src/portable/sunxi/musb_def.h
+++ b/src/portable/sunxi/musb_def.h
@@ -1,3 +1,30 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Tian Yunhao (t123yh)
+ * Copyright (c) 2021 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
 #ifndef _TUSB_MUSB_DEF
 #define _TUSB_MUSB_DEF
 

From adb848f75489ea6a9fa27be8c7c53cfa0679af91 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Dec 2021 19:40:55 +0700
Subject: [PATCH 0759/2085] update docs

---
 CONTRIBUTORS.rst                    | 6 ++++++
 README.rst                          | 1 +
 src/portable/sunxi/dcd_sunxi_musb.c | 1 +
 src/portable/sunxi/musb_def.h       | 1 +
 4 files changed, 9 insertions(+)

diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index e3186f086..05d088ee7 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -153,6 +153,12 @@ Notable contributors
 -  Add new class driver for DFU Runtime
 
 
+`Tian Yunhao <https://github.com/t123yh>`__
+-------------------------------------------
+
+-  Add new DCD port for Allwinner F1C100S/F1C200S
+-  Add support for osal_rtx4
+
 `Timon Skerutsch <https://github.com/PTS93>`__
 ----------------------------------------------
 
diff --git a/README.rst b/README.rst
index 03219db3f..7f1eff8b4 100644
--- a/README.rst
+++ b/README.rst
@@ -32,6 +32,7 @@ Supported MCUs
 
 The stack supports the following MCUs:
 
+- **Allwinner:** F1C100s/F1C200s
 - **Broadcom:** BCM2837, BCM2711
 - **Dialog:** DA1469x
 - **Espressif:** ESP32-S2, ESP32-S3
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 3d39248c1..89464c5b2 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -1,6 +1,7 @@
 /*
  * The MIT License (MIT)
  *
+ * Copyright (c) 2021 Koji KITAYAMA
  * Copyright (c) 2021 Tian Yunhao (t123yh)
  * Copyright (c) 2021 Ha Thach (tinyusb.org)
  *
diff --git a/src/portable/sunxi/musb_def.h b/src/portable/sunxi/musb_def.h
index e0c8a5e20..602b4f113 100644
--- a/src/portable/sunxi/musb_def.h
+++ b/src/portable/sunxi/musb_def.h
@@ -1,6 +1,7 @@
 /*
  * The MIT License (MIT)
  *
+ * Copyright (c) 2021 Koji KITAYAMA
  * Copyright (c) 2021 Tian Yunhao (t123yh)
  * Copyright (c) 2021 Ha Thach (tinyusb.org)
  *

From c5d2c82cbbabf02cef16c2da565867f63900f69b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 30 Dec 2021 20:59:53 +0700
Subject: [PATCH 0760/2085] fix unreachable warnings with keil

---
 src/device/usbd.c | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 0e31f47c7..448114303 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -44,11 +44,6 @@
   #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
 
-#ifdef __ARMCC_VERSION
-// Supress "statement is unreachable" warning
-#pragma diag_suppress 111
-#endif
-
 //--------------------------------------------------------------------+
 // Device Data
 //--------------------------------------------------------------------+
@@ -1013,7 +1008,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
         return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t));
       }
     }
-    break;
+    // break; // unreachable
 
     case TUSB_DESC_BOS:
     {
@@ -1030,7 +1025,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
       return tud_control_xfer(rhport, p_request, (void*) desc_bos, total_len);
     }
-    break;
+    // break; // unreachable
 
     case TUSB_DESC_CONFIGURATION:
     case TUSB_DESC_OTHER_SPEED_CONFIG:
@@ -1056,7 +1051,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
       return tud_control_xfer(rhport, p_request, (void*) desc_config, total_len);
     }
-    break;
+    // break; // unreachable
 
     case TUSB_DESC_STRING:
     {
@@ -1069,7 +1064,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       // first byte of descriptor is its size
       return tud_control_xfer(rhport, p_request, (void*) (uintptr_t) desc_str, tu_desc_len(desc_str));
     }
-    break;
+    // break; // unreachable
 
     case TUSB_DESC_DEVICE_QUALIFIER:
     {
@@ -1083,7 +1078,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
       // first byte of descriptor is its size
       return tud_control_xfer(rhport, p_request, (void*) (uintptr_t) desc_qualifier, tu_desc_len(desc_qualifier));
     }
-    break;
+    // break; // unreachable
 
     default: return false;
   }

From 2f69649bb6a2dcd583b52005dc946e08580323fd Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sun, 26 Dec 2021 21:50:48 +0100
Subject: [PATCH 0761/2085] Add register file for Microchip PIC32MZ

---
 .../microchip/pic32mz/usbhs_registers.h       | 931 ++++++++++++++++++
 1 file changed, 931 insertions(+)
 create mode 100644 src/portable/microchip/pic32mz/usbhs_registers.h

diff --git a/src/portable/microchip/pic32mz/usbhs_registers.h b/src/portable/microchip/pic32mz/usbhs_registers.h
new file mode 100644
index 000000000..757e3f083
--- /dev/null
+++ b/src/portable/microchip/pic32mz/usbhs_registers.h
@@ -0,0 +1,931 @@
+/*******************************************************************************
+* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries.
+*
+* Subject to your compliance with these terms, you may use Microchip software
+* and any derivatives exclusively with Microchip products. It is your
+* responsibility to comply with third party license terms applicable to your
+* use of third party software (including open source software) that may
+* accompany Microchip software.
+*
+* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
+* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
+* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
+* PARTICULAR PURPOSE.
+*
+* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
+* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
+* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
+* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
+* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
+* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+*******************************************************************************/
+/*******************************************************************************
+  USBHS Peripheral Library Register Defintions 
+
+  File Name:
+    usbhs_registers.h
+
+  Summary:
+    USBHS PLIB Register Defintions
+
+  Description:
+    This file contains the constants and defintions which are required by the
+    the USBHS library.
+*******************************************************************************/
+
+#ifndef __USBHS_REGISTERS_H__
+#define __USBHS_REGISTERS_H__
+
+#include <p32xxxx.h>
+#include <stdint.h>
+
+/*****************************************
+ * Module Register Offsets.
+ *****************************************/
+
+#define USBHS_REG_FADDR         0x000
+#define USBHS_REG_POWER         0x001
+#define USBHS_REG_INTRTX        0x002
+#define USBHS_REG_INTRRX        0x004
+#define USBHS_REG_INTRTXE       0x006
+#define USBHS_REG_INTRRXE       0x008
+#define USBHS_REG_INTRUSB       0x00A 
+#define USBHS_REG_INTRUSBE      0x00B 
+#define USBHS_REG_FRAME         0x00C
+#define USBHS_REG_INDEX         0x00E
+#define USBHS_REG_TESTMODE      0x00F
+
+/*******************************************************
+ * Endpoint Control Status Registers (CSR). These values 
+ * should be added to either the 0x10 to access the
+ * register through Indexed CSR. To access the actual 
+ * CSR, see ahead in this header file.
+ ******************************************************/
+
+#define USBHS_REG_EP_TXMAXP     0x000
+#define USBHS_REG_EP_CSR0L      0x002
+#define USBHS_REG_EP_CSR0H      0x003
+#define USBHS_REG_EP_TXCSRL     0x002
+#define USBHS_REG_EP_TXCSRH     0x003
+#define USBHS_REG_EP_RXMAXP     0x004
+#define USBHS_REG_EP_RXCSRL     0x006
+#define USBHS_REG_EP_RXCSRH     0x007
+#define USBHS_REG_EP_COUNT0     0x008
+#define USBHS_REG_EP_RXCOUNT    0x008
+#define USBHS_REG_EP_TYPE0      0x01A
+#define USBHS_REG_EP_TXTYPE     0x01A
+#define USBHS_REG_EP_NAKLIMIT0  0x01B
+#define USBHS_REG_EP_TXINTERVAL 0x01B
+#define USBHS_REG_EP_RXTYPE     0x01C
+#define USBHS_REG_EP_RXINTERVAL 0x01D
+#define USBHS_REG_EP_CONFIGDATA 0x01F
+#define USBHS_REG_EP_FIFOSIZE   0x01F
+
+#define USBHS_HOST_EP0_SETUPKT_SET 0x8
+#define USBHS_HOST_EP0_TXPKTRDY_SET 0x2
+#define USBHS_SOFT_RST_NRST_SET 0x1
+#define USBHS_SOFT_RST_NRSTX_SET 0x2
+#define USBHS_EP0_DEVICE_SERVICED_RXPKTRDY 0x40
+#define USBHS_EP0_DEVICE_DATAEND 0x08
+#define USBHS_EP0_DEVICE_TXPKTRDY 0x02
+#define USBHS_EP0_HOST_STATUS_STAGE_START 0x40
+#define USBHS_EP0_HOST_REQPKT 0x20
+#define USBHS_EP0_HOST_TXPKTRDY 0x02
+#define USBHS_EP0_HOST_RXPKTRDY 0x01
+#define USBHS_EP_DEVICE_TX_SENT_STALL 0x20
+#define USBHS_EP_DEVICE_TX_SEND_STALL 0x10
+#define USBHS_EP_DEVICE_RX_SENT_STALL 0x40
+#define USBHS_EP_DEVICE_RX_SEND_STALL 0x20
+
+/* FADDR - Device Function Address */
+typedef union 
+{
+    struct __attribute__((packed)) 
+    {
+        unsigned FUNC:7;
+        unsigned :1;
+    };
+
+    uint8_t w;  
+
+} __USBHS_FADDR_t;
+
+/* POWER - Control Resume and Suspend signalling */
+typedef union 
+{
+    struct __attribute__((packed))
+    {
+        unsigned SUSPEN:1;
+        unsigned SUSPMODE:1;
+        unsigned RESUME:1;
+        unsigned RESET:1;
+        unsigned HSMODE:1;
+        unsigned HSEN:1;
+        unsigned SOFTCONN:1;
+        unsigned ISOUPD:1;
+    };
+    struct
+    {   
+        uint8_t w;
+    };
+
+} __USBHS_POWER_t;
+
+/* INTRTXE - Transmit endpoint interrupt enable */
+typedef union 
+{
+    struct __attribute__((packed))
+    {
+        unsigned EP0IE:1;
+        unsigned EP1TXIE:1;
+        unsigned EP2TXIE:1;
+        unsigned EP3TXIE:1;
+        unsigned EP4TXIE:1;
+        unsigned EP5TXIE:1;
+        unsigned EP6TXIE:1;
+        unsigned EP7TXIE:1;
+        unsigned :8;
+    };
+    struct
+    {
+        uint16_t    w;
+    };
+
+} __USBHS_INTRTXE_t;
+
+/* INTRRXE - Receive endpoint interrupt enable */
+typedef union 
+{
+    struct __attribute__((packed))
+    {
+        unsigned :1;
+        unsigned EP1RXIE:1;
+        unsigned EP2RXIE:1;
+        unsigned EP3RXIE:1;
+        unsigned EP4RXIE:1;
+        unsigned EP5RXIE:1;
+        unsigned EP6RXIE:1;
+        unsigned EP7RXIE:1;
+        unsigned :8;
+    };
+    struct
+    {
+        uint16_t    w;
+    };
+
+} __USBHS_INTRRXE_t;
+
+/* INTRUSBE - General USB Interrupt enable */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned SUSPIE:1;
+        unsigned RESUMEIE:1;
+        unsigned RESETIE:1;
+        unsigned SOFIE:1;
+        unsigned CONNIE:1;
+        unsigned DISCONIE:1;
+        unsigned SESSRQIE:1;
+        unsigned VBUSERRIE:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_INTRUSBE_t;
+
+/* FRAME - Frame number */
+typedef union 
+{
+    struct __attribute__((packed))
+    {
+        unsigned RFRMNUM:11;
+        unsigned :5;
+    };
+    struct
+    {
+        uint16_t w;
+    };
+
+} __USBHS_FRAME_t;
+
+/* INDEX - Endpoint index */
+typedef union 
+{
+    struct __attribute__((packed))
+    {
+        unsigned ENDPOINT:4;
+        unsigned :4;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_INDEX_t;
+
+/* TESTMODE - Test mode register */
+typedef union 
+{
+    struct __attribute__((packed))
+    {
+        unsigned NAK:1;
+        unsigned TESTJ:1;
+        unsigned TESTK:1;
+        unsigned PACKET:1;
+        unsigned FORCEHS:1;
+        unsigned FORCEFS:1;
+        unsigned FIFOACC:1;
+        unsigned FORCEHST:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_TESTMODE_t;
+
+/* COUNT0 - Indicates the amount of data received in endpoint 0 */ 
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXCNT:7;
+        unsigned :1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_COUNT0_t;
+
+/* TYPE0 - Operating speed of target device */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned :6;
+        unsigned SPEED:2;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_TYPE0_t;
+
+/* DEVCTL - Module control register */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned SESSION:1;
+        unsigned HOSTREQ:1;
+        unsigned HOSTMODE:1;
+        unsigned VBUS:2;
+        unsigned LSDEV:1;
+        unsigned FSDEV:1;
+        unsigned BDEV:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_DEVCTL_t;
+
+/* CSR0L Device - Endpoint Device Mode Control Status Register */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXPKTRDY:1;
+        unsigned TXPKTRDY:1;
+        unsigned SENTSTALL:1;
+        unsigned DATAEND:1;
+        unsigned SETUPEND:1;
+        unsigned SENDSTALL:1;
+        unsigned SVCRPR:1;
+        unsigned SVSSETEND:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_CSR0L_DEVICE_t;
+
+/* CSR0L Host - Endpoint Host Mode Control Status Register */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXPKTRDY:1;
+        unsigned TXPKTRDY:1;
+        unsigned RXSTALL:1;
+        unsigned SETUPPKT:1;
+        unsigned ERROR:1;
+        unsigned REQPKT:1;
+        unsigned STATPKT:1;
+        unsigned NAKTMOUT:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_CSR0L_HOST_t;
+
+/* TXCSRL Device - Endpoint Transmit Control Status Register Low */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned TXPKTRDY:1;
+        unsigned FIFOONE:1;
+        unsigned UNDERRUN:1;
+        unsigned FLUSH:1;
+        unsigned SENDSTALL:1;
+        unsigned SENTSTALL:1;
+        unsigned CLRDT:1;
+        unsigned INCOMPTX:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_TXCSRL_DEVICE_t;
+
+/* TXCSRL Host - Endpoint Transmit Control Status Register Low */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned TXPKTRDY:1;
+        unsigned FIFONE:1;
+        unsigned ERROR:1;
+        unsigned FLUSH:1;
+        unsigned SETUPPKT:1;
+        unsigned RXSTALL:1;
+        unsigned CLRDT:1;
+        unsigned INCOMPTX:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_TXCSRL_HOST_t;
+
+/* TXCSRH Device - Endpoint Transmit Control Status Register High */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned :2;
+        unsigned DMAREQMD:1;
+        unsigned FRCDATTG:1;
+        unsigned DMAREQENL:1;
+        unsigned MODE:1;
+        unsigned ISO:1;
+        unsigned AUTOSET:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_TXCSRH_DEVICE_t;
+
+/* TXCSRH Host - Endpoint Transmit Control Status Register High */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned DATATGGL:1;
+        unsigned DTWREN:1;
+        unsigned DMAREQMD:1;
+        unsigned FRCDATTG:1;
+        unsigned DMAREQEN:1;
+        unsigned MODE:1;
+        unsigned :1;
+        unsigned AUOTSET:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_TXCSRH_HOST_t;
+
+/* CSR0H Device - Endpoint 0 Control Status Register High */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned FLSHFIFO:1;
+        unsigned :7;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_CSR0H_DEVICE_t;
+
+/* CSR0H Host - Endpoint 0 Control Status Register High */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned FLSHFIFO:1;
+        unsigned DATATGGL:1;
+        unsigned DTWREN:1;
+        unsigned DISPING:1;
+        unsigned :4;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_CSR0H_HOST_t;
+
+/* RXMAXP - Receive Endpoint Max packet size. */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXMAXP:11;
+        unsigned MULT:5;
+    };
+    struct
+    {
+        uint16_t w;
+    };
+
+} __USBHS_RXMAXP_t;
+
+/* RXCSRL Device - Receive endpoint Control Status Register */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXPKTRDY:1;
+        unsigned FIFOFULL:1;
+        unsigned OVERRUN:1;
+        unsigned DATAERR:1;
+        unsigned FLUSH:1;
+        unsigned SENDSTALL:1;
+        unsigned SENTSTALL:1;
+        unsigned CLRDT:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_RXCSRL_DEVICE_t;
+
+/* RXCSRL Host - Receive endpoint Control Status Register */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXPKTRDY:1;
+        unsigned FIFOFULL:1;
+        unsigned ERROR:1;
+        unsigned DERRNAKT:1;
+        unsigned FLUSH:1;
+        unsigned REQPKT:1;
+        unsigned RXSTALL:1;
+        unsigned CLRDT:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_RXCSRL_HOST_t;
+
+/* RXCSRH Device - Receive endpoint Control Status Register */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned INCOMPRX:1;
+        unsigned :2;
+        unsigned DMAREQMODE:1;
+        unsigned DISNYET:1;
+        unsigned DMAREQEN:1;
+        unsigned ISO:1;
+        unsigned AUTOCLR:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_RXCSRH_DEVICE_t;
+
+/* RXCSRH Host - Receive endpoint Control Status Register */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned INCOMPRX:1;
+        unsigned DATATGGL:1;
+        unsigned DATATWEN:1;
+        unsigned DMAREQMD:1;
+        unsigned PIDERR:1;
+        unsigned DMAREQEN:1;
+        unsigned AUTORQ:1;
+        unsigned AUOTCLR:1;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_RXCSRH_HOST_t;
+
+/* RXCOUNT - Amount of data pending in RX FIFO */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXCNT:14;
+        unsigned :2;
+    };
+    struct
+    {
+        uint16_t w;
+    };
+
+} __USBHS_RXCOUNT_t;
+
+/* TXTYPE - Specifies the target transmit endpoint */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned TEP:4;
+        unsigned PROTOCOL:2;
+        unsigned SPEED:2;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_TXTYPE_t;
+
+/* RXTYPE - Specifies the target receive endpoint */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned TEP:4;
+        unsigned PROTOCOL:2;
+        unsigned SPEED:2;
+    };
+    struct
+    {
+        uint8_t w;
+    };
+
+} __USBHS_RXTYPE_t;
+
+/* TXINTERVAL - Defines the polling interval */
+typedef struct
+{
+    uint8_t TXINTERV;
+
+} __USBHS_TXINTERVAL_t;
+
+/* RXINTERVAL - Defines the polling interval */
+typedef struct
+{
+    uint8_t RXINTERV;
+
+} __USBHS_RXINTERVAL_t;
+
+/* TXMAXP - Maximum amount of data that can be transferred through a TX endpoint
+ * */
+
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned TXMAXP:11;
+        unsigned MULT:5;
+    };
+    uint16_t w;
+
+} __USBHS_TXMAXP_t;  
+
+/* TXFIFOSZ - Size of the transmit endpoint FIFO */
+typedef struct __attribute__((packed))
+{
+    unsigned TXFIFOSZ:4;
+    unsigned TXDPB:1;
+    unsigned :3;
+
+} __USBHS_TXFIFOSZ_t;
+
+/* RXFIFOSZ - Size of the receive endpoint FIFO */
+typedef struct __attribute__((packed))
+{
+    unsigned RXFIFOSZ:4;
+    unsigned RXDPB:1;
+    unsigned :3;
+
+} __USBHS_RXFIFOSZ_t;
+
+/* TXFIFOADD - Start address of the transmit endpoint FIFO */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned TXFIFOAD:13;
+        unsigned :3;
+    };
+    uint16_t w;
+
+} __USBHS_TXFIFOADD_t;
+
+/* RXFIFOADD - Start address of the receive endpoint FIFO */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXFIFOAD:13;
+        unsigned :3;
+    };
+    uint16_t w;
+
+} __USBHS_RXFIFOADD_t;
+
+/* SOFTRST - Asserts NRSTO and NRSTOX */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned NRST:1;
+        unsigned NRSTX:1;
+        unsigned :6;
+    };
+    uint8_t w;
+
+} __USBHS_SOFTRST_t;
+
+/* TXFUNCADDR - Target address of transmit endpoint */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned TXFADDR:7;
+        unsigned :1;
+    };
+    uint8_t w;
+
+} __USBHS_TXFUNCADDR_t;
+
+/* RXFUNCADDR - Target address of receive endpoint */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXFADDR:7;
+        unsigned :1;
+    };
+    uint8_t w;
+
+} __USBHS_RXFUNCADDR_t;
+
+/* TXHUBADDR - Address of the hub to which the target transmit device endpoint
+ * is connected */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned TXHUBADDR:7;
+        unsigned MULTTRAN:1;
+    };
+    uint8_t w;
+
+} __USBHS_TXHUBADDR_t;
+
+/* RXHUBADDR - Address of the hub to which the target receive device endpoint is
+ * connected */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXHUBADDR:7;
+        unsigned MULTTRAN:1;
+    };
+    uint8_t w;
+
+} __USBHS_RXHUBADDR_t;
+
+/* TXHUBPORT - Address of the hub to which the target transmit device endpoint
+ * is connected. */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned TXHUBPRT:7;
+        unsigned :1;
+    };
+
+    uint8_t w;
+
+} __USBHS_TXHUBPORT_t;
+
+/* RXHUBPORT - Address of the hub to which the target receive device endpoint
+ * is connected. */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned RXHUBPRT:7;
+        unsigned :1;
+    };
+
+    uint8_t w;
+
+} __USBHS_RXHUBPORT_t;
+
+/* DMACONTROL - Configures a DMA channel */
+typedef union
+{
+    struct __attribute__((packed))
+    {
+        unsigned DMAEN:1;
+        unsigned DMADIR:1;
+        unsigned DMAMODE:1;
+        unsigned DMAIE:1;
+        unsigned DMAEP:4;
+        unsigned DMAERR:1;
+        unsigned DMABRSTM:2;
+        unsigned:21;
+    };
+
+    uint32_t w;
+
+} __USBHS_DMACNTL_t;
+
+/* Endpoint Control and Status Register Set */    
+typedef struct __attribute__((packed))
+{
+    volatile __USBHS_TXMAXP_t TXMAXPbits;
+    union
+    {
+        struct
+        {
+            union
+            {
+                volatile __USBHS_CSR0L_DEVICE_t CSR0L_DEVICEbits;
+                volatile __USBHS_CSR0L_HOST_t CSR0L_HOSTbits;
+            };
+            union
+            {
+                volatile __USBHS_CSR0H_DEVICE_t CSR0H_DEVICEbits;
+                volatile __USBHS_CSR0H_HOST_t CSR0H_HOSTbits;
+            };
+        };
+
+        struct
+        {
+            union
+            {
+                volatile __USBHS_TXCSRL_DEVICE_t TXCSRL_DEVICEbits;
+                volatile __USBHS_TXCSRL_HOST_t TXCSRL_HOSTbits;
+            };
+
+            union
+            {
+                volatile __USBHS_TXCSRH_DEVICE_t TXCSRH_DEVICEbits;
+                volatile __USBHS_TXCSRH_HOST_t TXCSRH_HOSTbits;
+            };
+        };
+    };
+
+    volatile __USBHS_RXMAXP_t RXMAXPbits;
+
+    union
+    {
+        volatile __USBHS_RXCSRL_DEVICE_t RXCSRL_DEVICEbits;
+        volatile __USBHS_RXCSRL_HOST_t RXCSRL_HOSTbits;
+    };
+
+    union
+    {
+        volatile __USBHS_RXCSRH_DEVICE_t RXCSRH_DEVICEbits;
+        volatile __USBHS_RXCSRH_HOST_t RXCSRH_HOSTbits;
+    };
+
+    union
+    {
+        volatile __USBHS_COUNT0_t COUNT0bits;
+        volatile __USBHS_RXCOUNT_t RXCOUNTbits;
+    };
+
+    union
+    {
+        volatile __USBHS_TYPE0_t TYPE0bits;
+        volatile __USBHS_TXTYPE_t TXTYPEbits;
+    };
+
+    union
+    {
+        volatile uint8_t NAKLIMIT0;
+        volatile __USBHS_TXINTERVAL_t TXINTERVALbits;
+    };
+
+    volatile __USBHS_RXTYPE_t RXTYPEbits;
+    volatile __USBHS_RXINTERVAL_t RXINTERVALbits;
+    unsigned :8;
+    union
+    {
+        volatile uint8_t CONFIGDATA;
+        volatile uint8_t FIFOSIZE;
+    };
+
+} __USBHS_EPCSR_t;
+
+/* Set of registers that configure the multi-point option */
+typedef struct __attribute__((packed))
+{
+    volatile __USBHS_TXFUNCADDR_t TXFUNCADDRbits;
+    unsigned :8;
+    volatile __USBHS_TXHUBADDR_t TXHUBADDRbits;
+    volatile __USBHS_TXHUBPORT_t TXHUBPORTbits;
+    volatile __USBHS_RXFUNCADDR_t RXFUNCADDRbits;
+    unsigned :8;
+    volatile __USBHS_RXHUBADDR_t RXHUBADDRbits;
+    volatile __USBHS_RXHUBPORT_t RXHUBPORTbits;
+
+} __USBHS_TARGET_ADDR_t;
+
+/* Set of registers that configure the DMA channel */
+typedef struct __attribute__((packed))
+{
+    volatile __USBHS_DMACNTL_t DMACNTLbits;
+    volatile uint32_t DMAADDR;
+    volatile uint32_t DMACOUNT;
+    volatile uint32_t pad;
+} __USBHS_DMA_CHANNEL_t;
+
+/* USBHS module register set */
+typedef struct __attribute__((aligned(4),packed))
+{
+    volatile __USBHS_FADDR_t    FADDRbits;
+    volatile __USBHS_POWER_t    POWERbits;
+    volatile uint16_t           INTRTX;
+    volatile uint16_t           INTRRX;
+    volatile __USBHS_INTRTXE_t  INTRTXEbits;
+    volatile __USBHS_INTRRXE_t  INTRRXEbits;
+    volatile uint8_t            INTRUSB;
+    volatile __USBHS_INTRUSBE_t INTRUSBEbits;
+    volatile __USBHS_FRAME_t    FRAMEbits;
+    volatile __USBHS_INDEX_t    INDEXbits;
+    volatile __USBHS_TESTMODE_t TESTMODEbits;
+    volatile __USBHS_EPCSR_t    INDEXED_EPCSR;
+    volatile uint32_t           FIFO[16];
+    volatile __USBHS_DEVCTL_t   DEVCTLbits;
+    volatile uint8_t            MISC;
+    volatile __USBHS_TXFIFOSZ_t TXFIFOSZbits;
+    volatile __USBHS_RXFIFOSZ_t RXFIFOSZbits;
+
+    volatile __USBHS_TXFIFOADD_t   TXFIFOADDbits;
+    volatile __USBHS_RXFIFOADD_t   RXFIFOADDbits;
+    
+    volatile uint32_t   VCONTROL;
+    volatile uint16_t   HWVERS;
+    volatile uint8_t    padding1[10];
+    volatile uint8_t    EPINFO;
+    volatile uint8_t    RAMINFO;
+    volatile uint8_t    LINKINFO;
+    volatile uint8_t    VPLEN;
+    volatile uint8_t    HS_EOF1;
+    volatile uint8_t    FS_EOF1;
+    volatile uint8_t    LS_EOF1;
+
+    volatile __USBHS_SOFTRST_t    SOFTRSTbits;
+
+    volatile __USBHS_TARGET_ADDR_t  TADDR[16];
+    volatile __USBHS_EPCSR_t        EPCSR[16];
+    volatile uint32_t               DMA_INTR;
+    volatile __USBHS_DMA_CHANNEL_t  DMA_CHANNEL[8]; 
+    volatile uint32_t               RQPKTXOUNT[16];
+
+} usbhs_registers_t;
+
+#endif

From 5f9e361f5cf2a8946b5bc4002dd7f5adac856f6c Mon Sep 17 00:00:00 2001
From: Meco Man <920369182@qq.com>
Date: Sun, 2 Jan 2022 02:06:53 -0500
Subject: [PATCH 0762/2085] [rt-thread] add rt-thread os in readme

---
 README.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.rst b/README.rst
index 03219db3f..faeef3663 100644
--- a/README.rst
+++ b/README.rst
@@ -90,6 +90,7 @@ TinyUSB is completely thread-safe by pushing all Interrupt Service Request (ISR)
 
 - **No OS**
 - **FreeRTOS**
+- **RT-Thread** (https://github.com/tfx2001/tinyusb)
 - **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its [own repo](https://github.com/hathach/mynewt-tinyusb-example)
 
 Local Docs

From a79ffeb7643bb9c7e7af69f29fe2cfe7ded837d8 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Wed, 5 Jan 2022 13:47:01 -0800
Subject: [PATCH 0763/2085] Add Raspberry Pi Zero W and Zero 2 W

These are different Broadcom chips. The peripherals are essentially
the same. The main differences are:
* The CPU(s)
* The interrupt controller
* The peripheral base address (but not the peripherals that we use)
---
 .../boards/raspberrypi_cm4/board.h            |  0
 .../bcm2835/boards/raspberrypi_cm4/board.mk   |  9 +++++
 .../bcm2835/boards/raspberrypi_zero2w/board.h | 38 +++++++++++++++++++
 .../boards/raspberrypi_zero2w/board.mk        |  9 +++++
 .../bcm2835/boards/raspberrypi_zero_w/board.h | 38 +++++++++++++++++++
 .../boards/raspberrypi_zero_w/board.mk        |  7 ++++
 hw/bsp/{raspberrypi4 => bcm2835}/family.c     | 32 +++++++++++-----
 hw/bsp/{raspberrypi4 => bcm2835}/family.mk    | 24 ++++--------
 .../boards/raspberrypi_cm4/board.mk           |  1 -
 hw/mcu/broadcom                               |  2 +-
 src/device/dcd_attr.h                         |  2 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c         |  5 ++-
 src/portable/synopsys/dwc2/dwc2_bcm.h         |  3 +-
 src/tusb_option.h                             |  2 +
 14 files changed, 139 insertions(+), 33 deletions(-)
 rename hw/bsp/{raspberrypi4 => bcm2835}/boards/raspberrypi_cm4/board.h (100%)
 create mode 100644 hw/bsp/bcm2835/boards/raspberrypi_cm4/board.mk
 create mode 100644 hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.h
 create mode 100644 hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.mk
 create mode 100644 hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.h
 create mode 100644 hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.mk
 rename hw/bsp/{raspberrypi4 => bcm2835}/family.c (82%)
 rename hw/bsp/{raspberrypi4 => bcm2835}/family.mk (61%)
 delete mode 100644 hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk

diff --git a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h b/hw/bsp/bcm2835/boards/raspberrypi_cm4/board.h
similarity index 100%
rename from hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.h
rename to hw/bsp/bcm2835/boards/raspberrypi_cm4/board.h
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_cm4/board.mk b/hw/bsp/bcm2835/boards/raspberrypi_cm4/board.mk
new file mode 100644
index 000000000..b4fa3dff6
--- /dev/null
+++ b/hw/bsp/bcm2835/boards/raspberrypi_cm4/board.mk
@@ -0,0 +1,9 @@
+CFLAGS += -mcpu=cortex-a72 \
+          -DBCM_VERSION=2711 \
+          -DCFG_TUSB_MCU=OPT_MCU_BCM2711
+
+CROSS_COMPILE = aarch64-none-elf-
+
+SUFFIX = 8
+
+INC += $(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.h b/hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.h
new file mode 100644
index 000000000..1d3565d5c
--- /dev/null
+++ b/hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.h
@@ -0,0 +1,38 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.mk b/hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.mk
new file mode 100644
index 000000000..f43e12e35
--- /dev/null
+++ b/hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.mk
@@ -0,0 +1,9 @@
+CFLAGS += -mcpu=cortex-a53 \
+          -DBCM_VERSION=2837 \
+          -DCFG_TUSB_MCU=OPT_MCU_BCM2837
+
+CROSS_COMPILE = aarch64-none-elf-
+
+SUFFIX = 8
+
+INC += $(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.h b/hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.h
new file mode 100644
index 000000000..1d3565d5c
--- /dev/null
+++ b/hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.h
@@ -0,0 +1,38 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.mk b/hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.mk
new file mode 100644
index 000000000..79d7096ce
--- /dev/null
+++ b/hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.mk
@@ -0,0 +1,7 @@
+CFLAGS += -mcpu=arm1176jzf-s \
+          -DBCM_VERSION=2835 \
+          -DCFG_TUSB_MCU=OPT_MCU_BCM2835
+
+CROSS_COMPILE = arm-none-eabi-
+
+SUFFIX = 
diff --git a/hw/bsp/raspberrypi4/family.c b/hw/bsp/bcm2835/family.c
similarity index 82%
rename from hw/bsp/raspberrypi4/family.c
rename to hw/bsp/bcm2835/family.c
index ba0b2700a..f7a11fb49 100644
--- a/hw/bsp/raspberrypi4/family.c
+++ b/hw/bsp/bcm2835/family.c
@@ -27,8 +27,9 @@
 #include "bsp/board.h"
 #include "board.h"
 
+#include "broadcom/cpu.h"
+#include "broadcom/gpio.h"
 #include "broadcom/interrupts.h"
-#include "broadcom/io.h"
 #include "broadcom/mmu.h"
 #include "broadcom/caches.h"
 #include "broadcom/vcmailbox.h"
@@ -37,9 +38,8 @@
 #define LED_PIN               18
 #define LED_STATE_ON          1
 
-// Button
-#define BUTTON_PIN            16
-#define BUTTON_STATE_ACTIVE   0
+// UART TX
+#define UART_TX_PIN           14
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
@@ -62,14 +62,26 @@ void board_init(void)
   init_caches();
 
   // LED
-  gpio_initOutputPinWithPullNone(LED_PIN);
+  gpio_set_function(LED_PIN, GPIO_FUNCTION_OUTPUT);
+  gpio_set_pull(LED_PIN, BP_PULL_NONE);
   board_led_write(true);
 
-  // Button
-  // TODO
-
   // Uart
-  uart_init();
+  COMPLETE_MEMORY_READS;
+  AUX->ENABLES_b.UART_1 = true;
+
+  UART1->IER = 0;
+  UART1->CNTL = 0;
+  UART1->LCR_b.DATA_SIZE = UART1_LCR_DATA_SIZE_MODE_8BIT;
+  UART1->MCR = 0;
+  UART1->IER = 0;
+
+  uint32_t source_clock = vcmailbox_get_clock_rate_measured(VCMAILBOX_CLOCK_CORE);
+  UART1->BAUD = ((source_clock / (115200 * 8)) - 1);
+  UART1->CNTL |= UART1_CNTL_TX_ENABLE_Msk;
+  COMPLETE_MEMORY_READS;
+
+  gpio_set_function(UART_TX_PIN, GPIO_FUNCTION_ALT5);
 
   // Turn on USB peripheral.
   vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true);
@@ -87,7 +99,7 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  gpio_setPinOutputBool(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  gpio_set_value(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
 }
 
 uint32_t board_button_read(void)
diff --git a/hw/bsp/raspberrypi4/family.mk b/hw/bsp/bcm2835/family.mk
similarity index 61%
rename from hw/bsp/raspberrypi4/family.mk
rename to hw/bsp/bcm2835/family.mk
index c65070a71..6de97f584 100644
--- a/hw/bsp/raspberrypi4/family.mk
+++ b/hw/bsp/bcm2835/family.mk
@@ -3,18 +3,14 @@ DEPS_SUBMODULES += $(MCU_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
-CC = clang
-
 CFLAGS += \
-	-mcpu=cortex-a72 \
 	-Wall \
 	-O0 \
 	-ffreestanding \
 	-nostdlib \
 	-nostartfiles \
-	-std=c17 \
 	-mgeneral-regs-only \
-	-DCFG_TUSB_MCU=OPT_MCU_BCM2711
+	-std=c17
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=cast-qual
@@ -22,30 +18,26 @@ CFLAGS += -Wno-error=cast-qual
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(MCU_DIR)/broadcom/gen/interrupt_handlers.c \
+	$(MCU_DIR)/broadcom/gpio.c \
 	$(MCU_DIR)/broadcom/interrupts.c \
-	$(MCU_DIR)/broadcom/io.c \
 	$(MCU_DIR)/broadcom/mmu.c \
 	$(MCU_DIR)/broadcom/caches.c \
 	$(MCU_DIR)/broadcom/vcmailbox.c
 
-
-CROSS_COMPILE = aarch64-none-elf-
-
 SKIP_NANOLIB = 1
 
-LD_FILE = $(MCU_DIR)/broadcom/link.ld
+LD_FILE = $(MCU_DIR)/broadcom/link$(SUFFIX).ld
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include
+	$(TOP)/$(MCU_DIR)
 
-SRC_S += $(MCU_DIR)/broadcom/boot.S
+SRC_S += $(MCU_DIR)/broadcom/boot$(SUFFIX).S
 
-$(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf
+$(BUILD)/kernel$(SUFFIX).img: $(BUILD)/$(PROJECT).elf
 	$(OBJCOPY) -O binary $^ $@
 
 # Copy to kernel to netboot drive or SD card
 # Change destinaation to fit your need
-flash: $(BUILD)/kernel8.img
-	$(CP) $< /home/$(USER)/Documents/code/pi4_tinyusb/boot_cpy
+flash: $(BUILD)/kernel$(SUFFIX).img
+	@$(CP) $< /home/$(USER)/Documents/code/pi_tinyusb/boot_cpy
diff --git a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk b/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk
deleted file mode 100644
index 897342479..000000000
--- a/hw/bsp/raspberrypi4/boards/raspberrypi_cm4/board.mk
+++ /dev/null
@@ -1 +0,0 @@
-CFLAGS += -DBCM_VERSION=2711
diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom
index 5bff1d5e0..083700860 160000
--- a/hw/mcu/broadcom
+++ b/hw/mcu/broadcom
@@ -1 +1 @@
-Subproject commit 5bff1d5e02c37c38ee1e5cf3f7fe82fdc7e1517e
+Subproject commit 08370086080759ed54ac1136d62d2ad24c6fa267
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 3c5dadaf4..feba82ea9 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -190,7 +190,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   4
 
 //------------- Broadcom -------------//
-#elif TU_CHECK_MCU(OPT_MCU_BCM2711)
+#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
   #define DCD_ATTR_ENDPOINT_MAX   8
 
 //------------- Broadcom -------------//
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index bb21b3dcd..188611743 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -33,7 +33,8 @@
 #if TUSB_OPT_DEVICE_ENABLED && \
     ( defined(DCD_ATTR_DWC2_STM32) || \
       TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) || \
-      TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711, OPT_MCU_XMC4000) )
+      TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711, OPT_MCU_BCM2835) || \
+      TU_CHECK_MCU(OPT_MCU_BCM2837, OPT_MCU_XMC4000) )
 
 #include "device/dcd.h"
 #include "dwc2_type.h"
@@ -44,7 +45,7 @@
   #include "dwc2_esp32.h"
 #elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
   #include "dwc2_gd32.h"
-#elif TU_CHECK_MCU(OPT_MCU_BCM2711)
+#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
   #include "dwc2_bcm.h"
 #elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
   #include "dwc2_efm32.h"
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index 353bc21ee..14194e754 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -31,6 +31,7 @@
  extern "C" {
 #endif
 
+#include "broadcom/defines.h"
 #include "broadcom/interrupts.h"
 #include "broadcom/caches.h"
 
@@ -47,7 +48,6 @@ static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
   (void) rhport;
   BP_EnableIRQ(USB_IRQn);
-  __asm__ volatile("isb"); // needed if TIMER1 IRQ is not enabled !?
 }
 
 TU_ATTR_ALWAYS_INLINE
@@ -55,7 +55,6 @@ static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
   (void) rhport;
   BP_DisableIRQ(USB_IRQn);
-  __asm__ volatile("isb"); // needed if TIMER1 IRQ is not enabled !?
 }
 
 static inline void dwc2_remote_wakeup_delay(void)
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 2edd310fa..c7c7b2454 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -132,6 +132,8 @@
 
 // Broadcom
 #define OPT_MCU_BCM2711          1700 ///< Broadcom BCM2711
+#define OPT_MCU_BCM2835          1701 ///< Broadcom BCM2835
+#define OPT_MCU_BCM2837          1702 ///< Broadcom BCM2837
 
 // Infineon
 #define OPT_MCU_XMC4000          1800 ///< Infineon XMC4000

From 84e2df51be5961177a63c6842a4130bb9b8978ac Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Wed, 5 Jan 2022 14:11:39 -0800
Subject: [PATCH 0764/2085] Split by compiler for testing

---
 .github/workflows/build_aarch64.yml           |   2 +-
 .github/workflows/build_arm.yml               |   3 +-
 .../boards/raspberrypi_zero_w}/board.h        |   0
 .../boards/raspberrypi_zero_w/board.mk        |   2 -
 hw/bsp/{bcm2835 => broadcom_32bit}/family.c   |   0
 hw/bsp/{bcm2835 => broadcom_32bit}/family.mk  |   2 +
 .../boards/raspberrypi_cm4}/board.h           |   0
 .../boards/raspberrypi_cm4/board.mk           |   6 -
 .../boards/raspberrypi_zero2w}/board.h        |   0
 .../boards/raspberrypi_zero2w/board.mk        |   6 -
 hw/bsp/broadcom_64bit/family.c                | 156 ++++++++++++++++++
 hw/bsp/broadcom_64bit/family.mk               |  46 ++++++
 12 files changed, 207 insertions(+), 16 deletions(-)
 rename hw/bsp/{bcm2835/boards/raspberrypi_cm4 => broadcom_32bit/boards/raspberrypi_zero_w}/board.h (100%)
 rename hw/bsp/{bcm2835 => broadcom_32bit}/boards/raspberrypi_zero_w/board.mk (78%)
 rename hw/bsp/{bcm2835 => broadcom_32bit}/family.c (100%)
 rename hw/bsp/{bcm2835 => broadcom_32bit}/family.mk (96%)
 rename hw/bsp/{bcm2835/boards/raspberrypi_zero2w => broadcom_64bit/boards/raspberrypi_cm4}/board.h (100%)
 rename hw/bsp/{bcm2835 => broadcom_64bit}/boards/raspberrypi_cm4/board.mk (51%)
 rename hw/bsp/{bcm2835/boards/raspberrypi_zero_w => broadcom_64bit/boards/raspberrypi_zero2w}/board.h (100%)
 rename hw/bsp/{bcm2835 => broadcom_64bit}/boards/raspberrypi_zero2w/board.mk (51%)
 create mode 100644 hw/bsp/broadcom_64bit/family.c
 create mode 100644 hw/bsp/broadcom_64bit/family.mk

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 0cc7a5de1..8cf7852b9 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -18,7 +18,7 @@ jobs:
       matrix:
         family:
         # Alphabetical order
-        - 'raspberrypi4'
+        - 'broadcom_64bit'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v2
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index dc4d9fcfb..177f1076e 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -39,6 +39,7 @@ jobs:
       matrix:
         family:
         # Alphabetical order
+        - 'broadcom_32bit'
         - 'imxrt'
         - 'lpc15'
         - 'lpc18'
@@ -114,7 +115,7 @@ jobs:
         done
 
   # ---------------------------------------
-  # Build all no-family (opharned) boards
+  # Build all no-family (orphaned) boards
   # ---------------------------------------
   build-board:
     runs-on: ubuntu-latest
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_cm4/board.h b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
similarity index 100%
rename from hw/bsp/bcm2835/boards/raspberrypi_cm4/board.h
rename to hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.mk b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
similarity index 78%
rename from hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.mk
rename to hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
index 79d7096ce..52e9e45c4 100644
--- a/hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.mk
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
@@ -2,6 +2,4 @@ CFLAGS += -mcpu=arm1176jzf-s \
           -DBCM_VERSION=2835 \
           -DCFG_TUSB_MCU=OPT_MCU_BCM2835
 
-CROSS_COMPILE = arm-none-eabi-
-
 SUFFIX = 
diff --git a/hw/bsp/bcm2835/family.c b/hw/bsp/broadcom_32bit/family.c
similarity index 100%
rename from hw/bsp/bcm2835/family.c
rename to hw/bsp/broadcom_32bit/family.c
diff --git a/hw/bsp/bcm2835/family.mk b/hw/bsp/broadcom_32bit/family.mk
similarity index 96%
rename from hw/bsp/bcm2835/family.mk
rename to hw/bsp/broadcom_32bit/family.mk
index 6de97f584..4ff574744 100644
--- a/hw/bsp/bcm2835/family.mk
+++ b/hw/bsp/broadcom_32bit/family.mk
@@ -12,6 +12,8 @@ CFLAGS += \
 	-mgeneral-regs-only \
 	-std=c17
 
+CROSS_COMPILE = arm-none-eabi-
+
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=cast-qual
 
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
similarity index 100%
rename from hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.h
rename to hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_cm4/board.mk b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
similarity index 51%
rename from hw/bsp/bcm2835/boards/raspberrypi_cm4/board.mk
rename to hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
index b4fa3dff6..5706b8318 100644
--- a/hw/bsp/bcm2835/boards/raspberrypi_cm4/board.mk
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
@@ -1,9 +1,3 @@
 CFLAGS += -mcpu=cortex-a72 \
           -DBCM_VERSION=2711 \
           -DCFG_TUSB_MCU=OPT_MCU_BCM2711
-
-CROSS_COMPILE = aarch64-none-elf-
-
-SUFFIX = 8
-
-INC += $(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
similarity index 100%
rename from hw/bsp/bcm2835/boards/raspberrypi_zero_w/board.h
rename to hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
diff --git a/hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.mk b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
similarity index 51%
rename from hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.mk
rename to hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
index f43e12e35..3060b0571 100644
--- a/hw/bsp/bcm2835/boards/raspberrypi_zero2w/board.mk
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
@@ -1,9 +1,3 @@
 CFLAGS += -mcpu=cortex-a53 \
           -DBCM_VERSION=2837 \
           -DCFG_TUSB_MCU=OPT_MCU_BCM2837
-
-CROSS_COMPILE = aarch64-none-elf-
-
-SUFFIX = 8
-
-INC += $(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include
diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c
new file mode 100644
index 000000000..f7a11fb49
--- /dev/null
+++ b/hw/bsp/broadcom_64bit/family.c
@@ -0,0 +1,156 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+#include "board.h"
+
+#include "broadcom/cpu.h"
+#include "broadcom/gpio.h"
+#include "broadcom/interrupts.h"
+#include "broadcom/mmu.h"
+#include "broadcom/caches.h"
+#include "broadcom/vcmailbox.h"
+
+// LED
+#define LED_PIN               18
+#define LED_STATE_ON          1
+
+// UART TX
+#define UART_TX_PIN           14
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+void board_init(void)
+{
+  setup_mmu_flat_map();
+  init_caches();
+
+  // LED
+  gpio_set_function(LED_PIN, GPIO_FUNCTION_OUTPUT);
+  gpio_set_pull(LED_PIN, BP_PULL_NONE);
+  board_led_write(true);
+
+  // Uart
+  COMPLETE_MEMORY_READS;
+  AUX->ENABLES_b.UART_1 = true;
+
+  UART1->IER = 0;
+  UART1->CNTL = 0;
+  UART1->LCR_b.DATA_SIZE = UART1_LCR_DATA_SIZE_MODE_8BIT;
+  UART1->MCR = 0;
+  UART1->IER = 0;
+
+  uint32_t source_clock = vcmailbox_get_clock_rate_measured(VCMAILBOX_CLOCK_CORE);
+  UART1->BAUD = ((source_clock / (115200 * 8)) - 1);
+  UART1->CNTL |= UART1_CNTL_TX_ENABLE_Msk;
+  COMPLETE_MEMORY_READS;
+
+  gpio_set_function(UART_TX_PIN, GPIO_FUNCTION_ALT5);
+
+  // Turn on USB peripheral.
+  vcmailbox_set_power_state(VCMAILBOX_DEVICE_USB_HCD, true);
+
+  // Timer 1/1024 second tick
+  SYSTMR->CS_b.M1 = 1;
+  SYSTMR->C1 = SYSTMR->CLO + 977;
+  BP_EnableIRQ(TIMER_1_IRQn);
+
+  BP_SetPriority(USB_IRQn, 0x00);
+  BP_ClearPendingIRQ(USB_IRQn);
+  BP_EnableIRQ(USB_IRQn);
+  BP_EnableIRQs();
+}
+
+void board_led_write(bool state)
+{
+  gpio_set_value(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return 0;
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  for (int i = 0; i < len; i++) {
+    const char* cbuf = buf;
+    while (!UART1->STAT_b.TX_READY) {}
+    if (cbuf[i] == '\n') {
+      UART1->IO = '\r';
+      while (!UART1->STAT_b.TX_READY) {}
+    }
+    UART1->IO = cbuf[i];
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void TIMER_1_IRQHandler(void)
+{
+  system_ticks++;
+  SYSTMR->C1 += 977;
+  SYSTMR->CS_b.M1 = 1;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler (void)
+{
+  // asm("bkpt");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/broadcom_64bit/family.mk b/hw/bsp/broadcom_64bit/family.mk
new file mode 100644
index 000000000..723926734
--- /dev/null
+++ b/hw/bsp/broadcom_64bit/family.mk
@@ -0,0 +1,46 @@
+MCU_DIR = hw/mcu/broadcom
+DEPS_SUBMODULES += $(MCU_DIR)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+	-Wall \
+	-O0 \
+	-ffreestanding \
+	-nostdlib \
+	-nostartfiles \
+	-mgeneral-regs-only \
+	-std=c17
+
+CROSS_COMPILE = aarch64-none-elf-
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=cast-qual
+
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	$(MCU_DIR)/broadcom/gen/interrupt_handlers.c \
+	$(MCU_DIR)/broadcom/gpio.c \
+	$(MCU_DIR)/broadcom/interrupts.c \
+	$(MCU_DIR)/broadcom/mmu.c \
+	$(MCU_DIR)/broadcom/caches.c \
+	$(MCU_DIR)/broadcom/vcmailbox.c
+
+SKIP_NANOLIB = 1
+
+LD_FILE = $(MCU_DIR)/broadcom/link8.ld
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core_A/Include
+
+SRC_S += $(MCU_DIR)/broadcom/boot8.S
+
+$(BUILD)/kernel8.img: $(BUILD)/$(PROJECT).elf
+	$(OBJCOPY) -O binary $^ $@
+
+# Copy to kernel to netboot drive or SD card
+# Change destinaation to fit your need
+flash: $(BUILD)/kernel8.img
+	@$(CP) $< /home/$(USER)/Documents/code/pi_tinyusb/boot_cpy

From 4fe0a30ec7bf254c839a76da9be3a2968d1690db Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Wed, 5 Jan 2022 14:33:24 -0800
Subject: [PATCH 0765/2085] Skip net and freertos examples

---
 examples/device/cdc_msc_freertos/.skip.MCU_BCM2835       | 0
 examples/device/cdc_msc_freertos/.skip.MCU_BCM2837       | 0
 examples/device/hid_composite_freertos/.skip.MCU_BCM2835 | 0
 examples/device/hid_composite_freertos/.skip.MCU_BCM2837 | 0
 examples/device/net_lwip_webserver/.skip.MCU_BCM2835     | 1 +
 examples/device/net_lwip_webserver/.skip.MCU_BCM2837     | 1 +
 hw/bsp/board_mcu.h                                       | 5 ++++-
 tools/build_family.py                                    | 2 +-
 8 files changed, 7 insertions(+), 2 deletions(-)
 create mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_BCM2835
 create mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_BCM2837
 create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_BCM2835
 create mode 100644 examples/device/hid_composite_freertos/.skip.MCU_BCM2837
 create mode 100644 examples/device/net_lwip_webserver/.skip.MCU_BCM2835
 create mode 100644 examples/device/net_lwip_webserver/.skip.MCU_BCM2837

diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_BCM2835 b/examples/device/cdc_msc_freertos/.skip.MCU_BCM2835
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_BCM2837 b/examples/device/cdc_msc_freertos/.skip.MCU_BCM2837
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_BCM2835 b/examples/device/hid_composite_freertos/.skip.MCU_BCM2835
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_BCM2837 b/examples/device/hid_composite_freertos/.skip.MCU_BCM2837
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_BCM2835 b/examples/device/net_lwip_webserver/.skip.MCU_BCM2835
new file mode 100644
index 000000000..bdc68f5db
--- /dev/null
+++ b/examples/device/net_lwip_webserver/.skip.MCU_BCM2835
@@ -0,0 +1 @@
+tinyusb/lib/lwip/src/include/lwip/arch.h:202:13: error: conflicting types for 'ssize_t'
\ No newline at end of file
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_BCM2837 b/examples/device/net_lwip_webserver/.skip.MCU_BCM2837
new file mode 100644
index 000000000..bdc68f5db
--- /dev/null
+++ b/examples/device/net_lwip_webserver/.skip.MCU_BCM2837
@@ -0,0 +1 @@
+tinyusb/lib/lwip/src/include/lwip/arch.h:202:13: error: conflicting types for 'ssize_t'
\ No newline at end of file
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index f8b5c061c..b911e1e53 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -32,7 +32,7 @@
 
 //--------------------------------------------------------------------+
 // Low Level MCU header include. TinyUSB stack and example should be
-// platform independent and mostly doens't need to include this file.
+// platform independent and mostly doesn't need to include this file.
 // However there are still certain situation where this file is needed:
 // - FreeRTOSConfig.h to set up correct clock and NVIC interrupts for ARM Cortex
 // - SWO logging for Cortex M with ITM_SendChar() / ITM_ReceiveChar()
@@ -146,6 +146,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_TM4C123
   #include "TM4C123.h"
 
+#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
+  // no header needed
+
 #else
   #error "Missing MCU header"
 #endif
diff --git a/tools/build_family.py b/tools/build_family.py
index 4195c259b..ccbcfa3f8 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -38,7 +38,7 @@ all_examples.sort()
 # If family are not specified in arguments, build all
 all_families = []
 for entry in os.scandir("hw/bsp"):
-    if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name != "esp32s2" and entry.name != "esp32s3":
+    if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name not in ("esp32s2", "esp32s3"):
         all_families.append(entry.name)
             
 filter_with_input(all_families)

From 7b27b8f498a185d8a7c1bea5dac8f43e7030ebd7 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Wed, 5 Jan 2022 15:44:23 -0800
Subject: [PATCH 0766/2085] Unify skip and only logic for build scripts

And switch to a single file that can include mcu, family or board.
---
 .gitignore                                    |  2 +
 .../audio_4_channel_mic/.skip.MCU_SAMD11      |  0
 .../audio_4_channel_mic/.skip.MCU_SAME5X      |  0
 .../device/audio_4_channel_mic/.skip.MCU_SAMG |  0
 examples/device/audio_4_channel_mic/skip.txt  |  3 +
 examples/device/audio_test/.skip.MCU_SAMD11   |  0
 examples/device/audio_test/.skip.MCU_SAME5X   |  0
 examples/device/audio_test/.skip.MCU_SAMG     |  0
 examples/device/audio_test/skip.txt           |  3 +
 examples/device/cdc_msc/.skip.MCU_SAMD11      |  0
 examples/device/cdc_msc/skip.txt              |  1 +
 .../device/cdc_msc_freertos/.skip.MCU_BCM2711 |  0
 .../device/cdc_msc_freertos/.skip.MCU_BCM2835 |  0
 .../device/cdc_msc_freertos/.skip.MCU_BCM2837 |  0
 .../device/cdc_msc_freertos/.skip.MCU_CXD56   |  0
 .../cdc_msc_freertos/.skip.MCU_GD32VF103      |  0
 .../cdc_msc_freertos/.skip.MCU_MKL25ZXX       |  0
 .../cdc_msc_freertos/.skip.MCU_MSP430x5xx     |  0
 .../device/cdc_msc_freertos/.skip.MCU_RP2040  |  0
 .../device/cdc_msc_freertos/.skip.MCU_SAMD11  |  0
 .../device/cdc_msc_freertos/.skip.MCU_SAMX7X  |  0
 .../.skip.MCU_VALENTYUSB_EPTRI                |  0
 examples/device/cdc_msc_freertos/skip.txt     | 10 +++
 examples/device/dfu/.skip.MCU_TM4C123         |  4 --
 examples/device/dfu/skip.txt                  |  1 +
 .../dynamic_configuration/.skip.MCU_SAMD11    |  0
 .../device/dynamic_configuration/skip.txt     |  1 +
 .../hid_composite_freertos/.skip.MCU_BCM2711  |  0
 .../hid_composite_freertos/.skip.MCU_BCM2835  |  0
 .../hid_composite_freertos/.skip.MCU_BCM2837  |  0
 .../hid_composite_freertos/.skip.MCU_CXD56    |  0
 .../.skip.MCU_GD32VF103                       |  0
 .../.skip.MCU_MSP430x5xx                      |  0
 .../hid_composite_freertos/.skip.MCU_RP2040   |  0
 .../hid_composite_freertos/.skip.MCU_SAMD11   |  0
 .../hid_composite_freertos/.skip.MCU_SAMX7X   |  0
 .../.skip.MCU_VALENTYUSB_EPTRI                |  0
 .../device/hid_composite_freertos/skip.txt    |  9 +++
 .../device/msc_dual_lun/.skip.MCU_MKL25ZXX    |  0
 examples/device/msc_dual_lun/.skip.MCU_SAMD11 |  0
 examples/device/msc_dual_lun/skip.txt         |  2 +
 .../net_lwip_webserver/.skip.MCU_BCM2711      |  1 -
 .../net_lwip_webserver/.skip.MCU_BCM2835      |  1 -
 .../net_lwip_webserver/.skip.MCU_BCM2837      |  1 -
 .../net_lwip_webserver/.skip.MCU_LPC11UXX     |  0
 .../net_lwip_webserver/.skip.MCU_LPC13XX      |  0
 .../net_lwip_webserver/.skip.MCU_MKL25ZXX     |  0
 .../net_lwip_webserver/.skip.MCU_MSP430x5xx   |  1 -
 .../net_lwip_webserver/.skip.MCU_NUC121       |  0
 .../net_lwip_webserver/.skip.MCU_SAMD11       |  0
 .../net_lwip_webserver/.skip.MCU_STM32L0      |  0
 examples/device/net_lwip_webserver/skip.txt   | 10 +++
 .../device/uac2_headset/.skip.MCU_LPC11UXX    |  0
 .../device/uac2_headset/.skip.MCU_LPC13XX     |  0
 examples/device/uac2_headset/.skip.MCU_NUC121 |  0
 examples/device/uac2_headset/.skip.MCU_SAMD11 |  0
 examples/device/uac2_headset/.skip.MCU_SAME5X |  0
 examples/device/uac2_headset/.skip.MCU_SAMG   |  0
 examples/device/uac2_headset/skip.txt         |  6 ++
 .../device/video_capture/.skip.MCU_MSP430x5xx |  1 -
 .../device/video_capture/.skip.MCU_SAMD11     |  0
 examples/device/video_capture/skip.txt        |  2 +
 .../host/cdc_msc_hid/.only.MCU_LPC175X_6X     |  0
 .../host/cdc_msc_hid/.only.MCU_LPC177X_8X     |  0
 examples/host/cdc_msc_hid/.only.MCU_LPC18XX   |  0
 examples/host/cdc_msc_hid/.only.MCU_LPC40XX   |  0
 examples/host/cdc_msc_hid/.only.MCU_LPC43XX   |  0
 .../host/cdc_msc_hid/.only.MCU_MIMXRT10XX     |  0
 examples/host/cdc_msc_hid/.only.MCU_MSP432E4  |  0
 examples/host/cdc_msc_hid/.only.MCU_RP2040    |  0
 examples/host/cdc_msc_hid/only.txt            |  8 +++
 .../host/hid_controller/.only.MCU_LPC175X_6X  |  0
 .../host/hid_controller/.only.MCU_LPC177X_8X  |  0
 .../host/hid_controller/.only.MCU_LPC18XX     |  0
 .../host/hid_controller/.only.MCU_LPC40XX     |  0
 .../host/hid_controller/.only.MCU_LPC43XX     |  0
 .../host/hid_controller/.only.MCU_MIMXRT10XX  |  0
 .../host/hid_controller/.only.MCU_MSP432E4    |  0
 examples/host/hid_controller/.only.MCU_RP2040 |  0
 examples/host/hid_controller/only.txt         |  8 +++
 .../.skip.device.net_lwip_webserver           |  0
 tools/build_board.py                          | 31 +---------
 tools/build_esp32sx.py                        |  7 +--
 tools/build_family.py                         | 44 +------------
 tools/build_utils.py                          | 61 +++++++++++++++++++
 85 files changed, 136 insertions(+), 82 deletions(-)
 delete mode 100644 examples/device/audio_4_channel_mic/.skip.MCU_SAMD11
 delete mode 100644 examples/device/audio_4_channel_mic/.skip.MCU_SAME5X
 delete mode 100644 examples/device/audio_4_channel_mic/.skip.MCU_SAMG
 create mode 100644 examples/device/audio_4_channel_mic/skip.txt
 delete mode 100644 examples/device/audio_test/.skip.MCU_SAMD11
 delete mode 100644 examples/device/audio_test/.skip.MCU_SAME5X
 delete mode 100644 examples/device/audio_test/.skip.MCU_SAMG
 create mode 100644 examples/device/audio_test/skip.txt
 delete mode 100644 examples/device/cdc_msc/.skip.MCU_SAMD11
 create mode 100644 examples/device/cdc_msc/skip.txt
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_BCM2711
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_BCM2835
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_BCM2837
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_CXD56
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_GD32VF103
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_MKL25ZXX
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_MSP430x5xx
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_RP2040
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_SAMD11
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_SAMX7X
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_VALENTYUSB_EPTRI
 create mode 100644 examples/device/cdc_msc_freertos/skip.txt
 delete mode 100644 examples/device/dfu/.skip.MCU_TM4C123
 create mode 100644 examples/device/dfu/skip.txt
 delete mode 100644 examples/device/dynamic_configuration/.skip.MCU_SAMD11
 create mode 100644 examples/device/dynamic_configuration/skip.txt
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_BCM2711
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_BCM2835
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_BCM2837
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_CXD56
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_GD32VF103
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_MSP430x5xx
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_RP2040
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_SAMD11
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_SAMX7X
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_VALENTYUSB_EPTRI
 create mode 100644 examples/device/hid_composite_freertos/skip.txt
 delete mode 100644 examples/device/msc_dual_lun/.skip.MCU_MKL25ZXX
 delete mode 100644 examples/device/msc_dual_lun/.skip.MCU_SAMD11
 create mode 100644 examples/device/msc_dual_lun/skip.txt
 delete mode 100644 examples/device/net_lwip_webserver/.skip.MCU_BCM2711
 delete mode 100644 examples/device/net_lwip_webserver/.skip.MCU_BCM2835
 delete mode 100644 examples/device/net_lwip_webserver/.skip.MCU_BCM2837
 delete mode 100644 examples/device/net_lwip_webserver/.skip.MCU_LPC11UXX
 delete mode 100644 examples/device/net_lwip_webserver/.skip.MCU_LPC13XX
 delete mode 100644 examples/device/net_lwip_webserver/.skip.MCU_MKL25ZXX
 delete mode 100644 examples/device/net_lwip_webserver/.skip.MCU_MSP430x5xx
 delete mode 100644 examples/device/net_lwip_webserver/.skip.MCU_NUC121
 delete mode 100644 examples/device/net_lwip_webserver/.skip.MCU_SAMD11
 delete mode 100644 examples/device/net_lwip_webserver/.skip.MCU_STM32L0
 create mode 100644 examples/device/net_lwip_webserver/skip.txt
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_LPC11UXX
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_LPC13XX
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_NUC121
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_SAMD11
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_SAME5X
 delete mode 100644 examples/device/uac2_headset/.skip.MCU_SAMG
 create mode 100644 examples/device/uac2_headset/skip.txt
 delete mode 100644 examples/device/video_capture/.skip.MCU_MSP430x5xx
 delete mode 100644 examples/device/video_capture/.skip.MCU_SAMD11
 create mode 100644 examples/device/video_capture/skip.txt
 delete mode 100644 examples/host/cdc_msc_hid/.only.MCU_LPC175X_6X
 delete mode 100644 examples/host/cdc_msc_hid/.only.MCU_LPC177X_8X
 delete mode 100644 examples/host/cdc_msc_hid/.only.MCU_LPC18XX
 delete mode 100644 examples/host/cdc_msc_hid/.only.MCU_LPC40XX
 delete mode 100644 examples/host/cdc_msc_hid/.only.MCU_LPC43XX
 delete mode 100644 examples/host/cdc_msc_hid/.only.MCU_MIMXRT10XX
 delete mode 100644 examples/host/cdc_msc_hid/.only.MCU_MSP432E4
 delete mode 100644 examples/host/cdc_msc_hid/.only.MCU_RP2040
 create mode 100644 examples/host/cdc_msc_hid/only.txt
 delete mode 100644 examples/host/hid_controller/.only.MCU_LPC175X_6X
 delete mode 100644 examples/host/hid_controller/.only.MCU_LPC177X_8X
 delete mode 100644 examples/host/hid_controller/.only.MCU_LPC18XX
 delete mode 100644 examples/host/hid_controller/.only.MCU_LPC40XX
 delete mode 100644 examples/host/hid_controller/.only.MCU_LPC43XX
 delete mode 100644 examples/host/hid_controller/.only.MCU_MIMXRT10XX
 delete mode 100644 examples/host/hid_controller/.only.MCU_MSP432E4
 delete mode 100644 examples/host/hid_controller/.only.MCU_RP2040
 create mode 100644 examples/host/hid_controller/only.txt
 delete mode 100644 hw/bsp/samd21/boards/curiosity_nano/.skip.device.net_lwip_webserver
 create mode 100644 tools/build_utils.py

diff --git a/.gitignore b/.gitignore
index f7adff4c9..87a5faa80 100644
--- a/.gitignore
+++ b/.gitignore
@@ -26,3 +26,5 @@ cov-int
 # cppcheck build directories
 *-build-dir
 /_bin/
+__pycache__
+
diff --git a/examples/device/audio_4_channel_mic/.skip.MCU_SAMD11 b/examples/device/audio_4_channel_mic/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/audio_4_channel_mic/.skip.MCU_SAME5X b/examples/device/audio_4_channel_mic/.skip.MCU_SAME5X
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/audio_4_channel_mic/.skip.MCU_SAMG b/examples/device/audio_4_channel_mic/.skip.MCU_SAMG
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/audio_4_channel_mic/skip.txt b/examples/device/audio_4_channel_mic/skip.txt
new file mode 100644
index 000000000..ae9b57f1f
--- /dev/null
+++ b/examples/device/audio_4_channel_mic/skip.txt
@@ -0,0 +1,3 @@
+mcu:SAMD11
+mcu:SAME5X
+mcu:SAMG
\ No newline at end of file
diff --git a/examples/device/audio_test/.skip.MCU_SAMD11 b/examples/device/audio_test/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/audio_test/.skip.MCU_SAME5X b/examples/device/audio_test/.skip.MCU_SAME5X
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/audio_test/.skip.MCU_SAMG b/examples/device/audio_test/.skip.MCU_SAMG
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/audio_test/skip.txt b/examples/device/audio_test/skip.txt
new file mode 100644
index 000000000..ae9b57f1f
--- /dev/null
+++ b/examples/device/audio_test/skip.txt
@@ -0,0 +1,3 @@
+mcu:SAMD11
+mcu:SAME5X
+mcu:SAMG
\ No newline at end of file
diff --git a/examples/device/cdc_msc/.skip.MCU_SAMD11 b/examples/device/cdc_msc/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc/skip.txt b/examples/device/cdc_msc/skip.txt
new file mode 100644
index 000000000..d844feae8
--- /dev/null
+++ b/examples/device/cdc_msc/skip.txt
@@ -0,0 +1 @@
+mcu:SAMD11
\ No newline at end of file
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_BCM2711 b/examples/device/cdc_msc_freertos/.skip.MCU_BCM2711
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_BCM2835 b/examples/device/cdc_msc_freertos/.skip.MCU_BCM2835
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_BCM2837 b/examples/device/cdc_msc_freertos/.skip.MCU_BCM2837
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_CXD56 b/examples/device/cdc_msc_freertos/.skip.MCU_CXD56
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_GD32VF103 b/examples/device/cdc_msc_freertos/.skip.MCU_GD32VF103
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_MKL25ZXX b/examples/device/cdc_msc_freertos/.skip.MCU_MKL25ZXX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_MSP430x5xx b/examples/device/cdc_msc_freertos/.skip.MCU_MSP430x5xx
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_RP2040 b/examples/device/cdc_msc_freertos/.skip.MCU_RP2040
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_SAMD11 b/examples/device/cdc_msc_freertos/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_SAMX7X b/examples/device/cdc_msc_freertos/.skip.MCU_SAMX7X
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_VALENTYUSB_EPTRI b/examples/device/cdc_msc_freertos/.skip.MCU_VALENTYUSB_EPTRI
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt
new file mode 100644
index 000000000..7137b78af
--- /dev/null
+++ b/examples/device/cdc_msc_freertos/skip.txt
@@ -0,0 +1,10 @@
+mcu:CXD56
+mcu:MSP430x5xx
+mcu:SAMD11
+mcu:VALENTYUSB_EPTRI
+mcu:MKL25ZXX
+mcu:RP2040
+mcu:SAMX7X
+mcu:GD32VF103
+family:broadcom_64bit
+family:broadcom_32bit
\ No newline at end of file
diff --git a/examples/device/dfu/.skip.MCU_TM4C123 b/examples/device/dfu/.skip.MCU_TM4C123
deleted file mode 100644
index 6260e6e25..000000000
--- a/examples/device/dfu/.skip.MCU_TM4C123
+++ /dev/null
@@ -1,4 +0,0 @@
-LINK _build/ek-tm4c123gxl/dfu.elf
-/home/runner/cache/toolchain/xpack-arm-none-eabi-gcc-10.2.1-1.1/bin/../lib/gcc/arm-none-eabi/10.2.1/../../../../arm-none-eabi/bin/ld: section .ARM.exidx.text._close LMA [0000000000002980,0000000000002987] overlaps section .data LMA [0000000000002980,0000000000002a03]
-collect2: error: ld returned 1 exit status
-make: *** [../../rules.mk:94: _build/ek-tm4c123gxl/dfu.elf] Error 1
\ No newline at end of file
diff --git a/examples/device/dfu/skip.txt b/examples/device/dfu/skip.txt
new file mode 100644
index 000000000..2c9d94902
--- /dev/null
+++ b/examples/device/dfu/skip.txt
@@ -0,0 +1 @@
+mcu:TM4C123
\ No newline at end of file
diff --git a/examples/device/dynamic_configuration/.skip.MCU_SAMD11 b/examples/device/dynamic_configuration/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/dynamic_configuration/skip.txt b/examples/device/dynamic_configuration/skip.txt
new file mode 100644
index 000000000..d844feae8
--- /dev/null
+++ b/examples/device/dynamic_configuration/skip.txt
@@ -0,0 +1 @@
+mcu:SAMD11
\ No newline at end of file
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_BCM2711 b/examples/device/hid_composite_freertos/.skip.MCU_BCM2711
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_BCM2835 b/examples/device/hid_composite_freertos/.skip.MCU_BCM2835
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_BCM2837 b/examples/device/hid_composite_freertos/.skip.MCU_BCM2837
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_CXD56 b/examples/device/hid_composite_freertos/.skip.MCU_CXD56
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_GD32VF103 b/examples/device/hid_composite_freertos/.skip.MCU_GD32VF103
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_MSP430x5xx b/examples/device/hid_composite_freertos/.skip.MCU_MSP430x5xx
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_RP2040 b/examples/device/hid_composite_freertos/.skip.MCU_RP2040
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_SAMD11 b/examples/device/hid_composite_freertos/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_SAMX7X b/examples/device/hid_composite_freertos/.skip.MCU_SAMX7X
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_VALENTYUSB_EPTRI b/examples/device/hid_composite_freertos/.skip.MCU_VALENTYUSB_EPTRI
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt
new file mode 100644
index 000000000..e64187fd4
--- /dev/null
+++ b/examples/device/hid_composite_freertos/skip.txt
@@ -0,0 +1,9 @@
+mcu:CXD56
+mcu:MSP430x5xx
+mcu:SAMD11
+mcu:VALENTYUSB_EPTRI
+mcu:RP2040
+mcu:SAMX7X
+mcu:GD32VF103
+family:broadcom_64bit
+family:broadcom_32bit
\ No newline at end of file
diff --git a/examples/device/msc_dual_lun/.skip.MCU_MKL25ZXX b/examples/device/msc_dual_lun/.skip.MCU_MKL25ZXX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/msc_dual_lun/.skip.MCU_SAMD11 b/examples/device/msc_dual_lun/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/msc_dual_lun/skip.txt b/examples/device/msc_dual_lun/skip.txt
new file mode 100644
index 000000000..3549c702a
--- /dev/null
+++ b/examples/device/msc_dual_lun/skip.txt
@@ -0,0 +1,2 @@
+mcu:SAMD11
+mcu:MKL25ZXX
\ No newline at end of file
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_BCM2711 b/examples/device/net_lwip_webserver/.skip.MCU_BCM2711
deleted file mode 100644
index bdc68f5db..000000000
--- a/examples/device/net_lwip_webserver/.skip.MCU_BCM2711
+++ /dev/null
@@ -1 +0,0 @@
-tinyusb/lib/lwip/src/include/lwip/arch.h:202:13: error: conflicting types for 'ssize_t'
\ No newline at end of file
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_BCM2835 b/examples/device/net_lwip_webserver/.skip.MCU_BCM2835
deleted file mode 100644
index bdc68f5db..000000000
--- a/examples/device/net_lwip_webserver/.skip.MCU_BCM2835
+++ /dev/null
@@ -1 +0,0 @@
-tinyusb/lib/lwip/src/include/lwip/arch.h:202:13: error: conflicting types for 'ssize_t'
\ No newline at end of file
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_BCM2837 b/examples/device/net_lwip_webserver/.skip.MCU_BCM2837
deleted file mode 100644
index bdc68f5db..000000000
--- a/examples/device/net_lwip_webserver/.skip.MCU_BCM2837
+++ /dev/null
@@ -1 +0,0 @@
-tinyusb/lib/lwip/src/include/lwip/arch.h:202:13: error: conflicting types for 'ssize_t'
\ No newline at end of file
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_LPC11UXX b/examples/device/net_lwip_webserver/.skip.MCU_LPC11UXX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_LPC13XX b/examples/device/net_lwip_webserver/.skip.MCU_LPC13XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_MKL25ZXX b/examples/device/net_lwip_webserver/.skip.MCU_MKL25ZXX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_MSP430x5xx b/examples/device/net_lwip_webserver/.skip.MCU_MSP430x5xx
deleted file mode 100644
index 17600f062..000000000
--- a/examples/device/net_lwip_webserver/.skip.MCU_MSP430x5xx
+++ /dev/null
@@ -1 +0,0 @@
-too many warnings for 16-bit integer overflow
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_NUC121 b/examples/device/net_lwip_webserver/.skip.MCU_NUC121
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_SAMD11 b/examples/device/net_lwip_webserver/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/net_lwip_webserver/.skip.MCU_STM32L0 b/examples/device/net_lwip_webserver/.skip.MCU_STM32L0
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt
new file mode 100644
index 000000000..68761b058
--- /dev/null
+++ b/examples/device/net_lwip_webserver/skip.txt
@@ -0,0 +1,10 @@
+mcu:LPC11UXX
+mcu:LPC13XX
+mcu:MSP430x5xx
+mcu:NUC121
+mcu:SAMD11
+mcu:STM32L0
+mcu:MKL25ZXX
+family:broadcom_64bit
+family:broadcom_32bit
+board:curiosity_nano
\ No newline at end of file
diff --git a/examples/device/uac2_headset/.skip.MCU_LPC11UXX b/examples/device/uac2_headset/.skip.MCU_LPC11UXX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_LPC13XX b/examples/device/uac2_headset/.skip.MCU_LPC13XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_NUC121 b/examples/device/uac2_headset/.skip.MCU_NUC121
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_SAMD11 b/examples/device/uac2_headset/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_SAME5X b/examples/device/uac2_headset/.skip.MCU_SAME5X
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/.skip.MCU_SAMG b/examples/device/uac2_headset/.skip.MCU_SAMG
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/uac2_headset/skip.txt b/examples/device/uac2_headset/skip.txt
new file mode 100644
index 000000000..9471822a4
--- /dev/null
+++ b/examples/device/uac2_headset/skip.txt
@@ -0,0 +1,6 @@
+mcu:LPC11UXX
+mcu:LPC13XX
+mcu:NUC121
+mcu:SAMD11
+mcu:SAME5X
+mcu:SAMG
\ No newline at end of file
diff --git a/examples/device/video_capture/.skip.MCU_MSP430x5xx b/examples/device/video_capture/.skip.MCU_MSP430x5xx
deleted file mode 100644
index 17600f062..000000000
--- a/examples/device/video_capture/.skip.MCU_MSP430x5xx
+++ /dev/null
@@ -1 +0,0 @@
-too many warnings for 16-bit integer overflow
diff --git a/examples/device/video_capture/.skip.MCU_SAMD11 b/examples/device/video_capture/.skip.MCU_SAMD11
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/video_capture/skip.txt b/examples/device/video_capture/skip.txt
new file mode 100644
index 000000000..892a8c6a7
--- /dev/null
+++ b/examples/device/video_capture/skip.txt
@@ -0,0 +1,2 @@
+mcu:MSP430x5xx
+mcu:SAMD11
\ No newline at end of file
diff --git a/examples/host/cdc_msc_hid/.only.MCU_LPC175X_6X b/examples/host/cdc_msc_hid/.only.MCU_LPC175X_6X
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/cdc_msc_hid/.only.MCU_LPC177X_8X b/examples/host/cdc_msc_hid/.only.MCU_LPC177X_8X
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/cdc_msc_hid/.only.MCU_LPC18XX b/examples/host/cdc_msc_hid/.only.MCU_LPC18XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/cdc_msc_hid/.only.MCU_LPC40XX b/examples/host/cdc_msc_hid/.only.MCU_LPC40XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/cdc_msc_hid/.only.MCU_LPC43XX b/examples/host/cdc_msc_hid/.only.MCU_LPC43XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/cdc_msc_hid/.only.MCU_MIMXRT10XX b/examples/host/cdc_msc_hid/.only.MCU_MIMXRT10XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/cdc_msc_hid/.only.MCU_MSP432E4 b/examples/host/cdc_msc_hid/.only.MCU_MSP432E4
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/cdc_msc_hid/.only.MCU_RP2040 b/examples/host/cdc_msc_hid/.only.MCU_RP2040
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
new file mode 100644
index 000000000..db9a337e5
--- /dev/null
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -0,0 +1,8 @@
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MIMXRT10XX
+mcu:RP2040
+mcu:MSP432E4
\ No newline at end of file
diff --git a/examples/host/hid_controller/.only.MCU_LPC175X_6X b/examples/host/hid_controller/.only.MCU_LPC175X_6X
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/hid_controller/.only.MCU_LPC177X_8X b/examples/host/hid_controller/.only.MCU_LPC177X_8X
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/hid_controller/.only.MCU_LPC18XX b/examples/host/hid_controller/.only.MCU_LPC18XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/hid_controller/.only.MCU_LPC40XX b/examples/host/hid_controller/.only.MCU_LPC40XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/hid_controller/.only.MCU_LPC43XX b/examples/host/hid_controller/.only.MCU_LPC43XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/hid_controller/.only.MCU_MIMXRT10XX b/examples/host/hid_controller/.only.MCU_MIMXRT10XX
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/hid_controller/.only.MCU_MSP432E4 b/examples/host/hid_controller/.only.MCU_MSP432E4
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/hid_controller/.only.MCU_RP2040 b/examples/host/hid_controller/.only.MCU_RP2040
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
new file mode 100644
index 000000000..db9a337e5
--- /dev/null
+++ b/examples/host/hid_controller/only.txt
@@ -0,0 +1,8 @@
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MIMXRT10XX
+mcu:RP2040
+mcu:MSP432E4
\ No newline at end of file
diff --git a/hw/bsp/samd21/boards/curiosity_nano/.skip.device.net_lwip_webserver b/hw/bsp/samd21/boards/curiosity_nano/.skip.device.net_lwip_webserver
deleted file mode 100644
index e69de29bb..000000000
diff --git a/tools/build_board.py b/tools/build_board.py
index 9397c754f..b2a80c680 100644
--- a/tools/build_board.py
+++ b/tools/build_board.py
@@ -4,6 +4,8 @@ import sys
 import subprocess
 import time
 
+import build_utils
+
 SUCCEEDED = "\033[32msucceeded\033[0m"
 FAILED = "\033[31mfailed\033[0m"
 SKIPPED = "\033[33mskipped\033[0m"
@@ -50,7 +52,7 @@ def build_board(example, board):
     sram_size = "-"
 
     # Check if board is skipped
-    if skip_example(example, board):
+    if build_utils.skip_example(example, board):
         success = SKIPPED
         skip_count += 1
         print(build_format.format(example, board, success, '-', flash_size, sram_size))
@@ -82,33 +84,6 @@ def build_size(example, board):
     sram_size = int(size_list[1]) + int(size_list[2])
     return (flash_size, sram_size)
 
-def skip_example(example, board):
-    ex_dir = 'examples/' + example
-    board_mk = 'hw/bsp/{}/board.mk'.format(board)
-    with open(board_mk) as mk:
-        mk_contents = mk.read()
-
-        # Skip all OPT_MCU_NONE these are WIP port
-        if '-DCFG_TUSB_MCU=OPT_MCU_NONE' in mk_contents:
-            return 1
-
-        # Skip if CFG_TUSB_MCU in board.mk to match skip file
-        for skip_file in glob.iglob(ex_dir + '/.skip.MCU_*'):
-            mcu_cflag = '-DCFG_TUSB_MCU=OPT_' + os.path.basename(skip_file).split('.')[2]
-            if mcu_cflag in mk_contents:
-                return 1
-
-        # Build only list, if exists only these MCU are built
-        only_list = list(glob.iglob(ex_dir + '/.only.MCU_*'))
-        if len(only_list) > 0:
-            for only_file in only_list:
-                mcu_cflag = '-DCFG_TUSB_MCU=OPT_' + os.path.basename(only_file).split('.')[2]
-                if mcu_cflag in mk_contents:
-                    return 0
-            return 1
-
-    return 0
-
 print(build_separator)
 print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
 
diff --git a/tools/build_esp32sx.py b/tools/build_esp32sx.py
index 91953f080..2947a0a6b 100644
--- a/tools/build_esp32sx.py
+++ b/tools/build_esp32sx.py
@@ -4,6 +4,8 @@ import sys
 import subprocess
 import time
 
+import build_utils
+
 SUCCEEDED = "\033[32msucceeded\033[0m"
 FAILED = "\033[31mfailed\033[0m"
 SKIPPED = "\033[33mskipped\033[0m"
@@ -51,7 +53,7 @@ def build_board(example, board):
     sram_size = "-"
 
     # Check if board is skipped
-    if skip_example(example, board):
+    if build_utils.skip_example(example, board):
         success = SKIPPED
         skip_count += 1
         print(build_format.format(example, board, success, '-', flash_size, sram_size))
@@ -83,9 +85,6 @@ def build_size(example, board):
     sram_size = int(size_list[1]) + int(size_list[2])
     return (flash_size, sram_size)
 
-def skip_example(example, board):
-    return 0
-
 print(build_separator)
 print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
 print(build_separator)
diff --git a/tools/build_family.py b/tools/build_family.py
index ccbcfa3f8..4094d07db 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -4,6 +4,8 @@ import sys
 import subprocess
 import time
 
+import build_utils
+
 SUCCEEDED = "\033[32msucceeded\033[0m"
 FAILED = "\033[31mfailed\033[0m"
 SKIPPED = "\033[33mskipped\033[0m"
@@ -62,7 +64,7 @@ def build_board(example, board):
     sram_size = "-"
 
     # Check if board is skipped
-    if skip_example(example, board):
+    if build_utils.skip_example(example, board):
         success = SKIPPED
         skip_count += 1
         print(build_format.format(example, board, success, '-', flash_size, sram_size))
@@ -95,46 +97,6 @@ def build_size(example, board):
     sram_size = int(size_list[1]) + int(size_list[2])
     return (flash_size, sram_size)
 
-def skip_example(example, board):
-    ex_dir = 'examples/' + example
-    
-    # Check if example is skipped by family or board directory
-    skip_file = ".skip." + example.replace('/', '.');
-    if os.path.isfile("hw/bsp/{}/{}".format(family, skip_file)) or os.path.isfile("hw/bsp/{}/boards/{}/{}".format(family, board, skip_file)):
-        return 1
-
-    # Otherwise check if mcu is excluded by example directory
-
-    # family CMake
-    family_mk = 'hw/bsp/{}/family.cmake'.format(family)
-
-    # family.mk
-    if not os.path.exists(family_mk):
-        family_mk = 'hw/bsp/{}/family.mk'.format(family)
-
-    with open(family_mk) as mk:
-        mk_contents = mk.read()
-
-        # Skip all OPT_MCU_NONE these are WIP port
-        if 'CFG_TUSB_MCU=OPT_MCU_NONE' in mk_contents:
-            return 1
-
-        # Skip if CFG_TUSB_MCU in family.mk to match skip file
-        for skip_file in glob.iglob(ex_dir + '/.skip.MCU_*'):
-            mcu_cflag = 'CFG_TUSB_MCU=OPT_' + os.path.basename(skip_file).split('.')[2]
-            if mcu_cflag in mk_contents:
-                return 1
-
-        # Build only list, if exists only these MCU are built
-        only_list = list(glob.iglob(ex_dir + '/.only.MCU_*'))
-        if len(only_list) > 0:
-            for only_file in only_list:
-                mcu_cflag = 'CFG_TUSB_MCU=OPT_' + os.path.basename(only_file).split('.')[2]
-                if mcu_cflag in mk_contents:
-                    return 0
-            return 1
-    return 0
-
 print(build_separator)
 print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
 
diff --git a/tools/build_utils.py b/tools/build_utils.py
new file mode 100644
index 000000000..299fffa4d
--- /dev/null
+++ b/tools/build_utils.py
@@ -0,0 +1,61 @@
+import pathlib
+
+def skip_example(example, board):
+    ex_dir = pathlib.Path('examples/') / example
+    bsp = pathlib.Path("hw/bsp")
+
+    board_dir = list(bsp.glob("*/boards/" + board))
+    if not board_dir:
+        # Skip unknown boards
+        return True
+
+    board_dir = list(board_dir)[0]
+    
+    family_dir = board_dir.parent.parent
+    family = family_dir.name
+
+    # family CMake
+    family_mk = family_dir / "family.cmake"
+
+    # family.mk
+    if not family_mk.exists():
+        family_mk = family_dir / "family.mk"
+
+    mk_contents = family_mk.read_text()
+
+    # Find the mcu
+    if "CFG_TUSB_MCU=OPT_MCU_" not in mk_contents:
+        board_mk = board_dir / "board.cmake"
+        if not board_mk.exists():
+            board_mk = board_dir / "board.mk"
+
+        mk_contents = board_mk.read_text()
+
+    for token in mk_contents.split():
+        if "CFG_TUSB_MCU=OPT_MCU_" in token:
+            # Strip " because cmake files has them.
+            token = token.strip("\"")
+            _, opt_mcu = token.split("=")
+            mcu = opt_mcu[len("OPT_MCU_"):]
+
+    # Skip all OPT_MCU_NONE these are WIP port
+    if mcu == "NONE":
+        return True
+
+    skip_file = ex_dir / "skip.txt"
+    only_file = ex_dir / "only.txt"
+
+    if skip_file.exists() and only_file.exists():
+        raise RuntimeError("Only have a skip or only file. Not both.")
+    elif skip_file.exists():
+        skips = skip_file.read_text().split()
+        return ("mcu:" + mcu in skips or
+                "board:" + board in skips or
+                "family:" + family in skips)
+    elif only_file.exists():
+        onlys = only_file.read_text().split()
+        return not ("mcu:" + mcu in onlys or
+                    "board:" + board in onlys or
+                    "family:" + family in onlys)
+
+    return False

From 47218eeb674789db9dbd9b8b305c6390c3e00577 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Wed, 5 Jan 2022 16:07:17 -0800
Subject: [PATCH 0767/2085] No exceptions on broadcom. Add parens to if

---
 hw/bsp/broadcom_32bit/family.mk  |  1 +
 src/class/usbtmc/usbtmc_device.c | 18 ++++++++++--------
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/hw/bsp/broadcom_32bit/family.mk b/hw/bsp/broadcom_32bit/family.mk
index 4ff574744..98744c5d0 100644
--- a/hw/bsp/broadcom_32bit/family.mk
+++ b/hw/bsp/broadcom_32bit/family.mk
@@ -10,6 +10,7 @@ CFLAGS += \
 	-nostdlib \
 	-nostartfiles \
 	-mgeneral-regs-only \
+	-fno-exceptions \
 	-std=c17
 
 CROSS_COMPILE = arm-none-eabi-
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 4bd1edf12..26be987cf 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -235,17 +235,19 @@ void usbtmcd_init_cb(void)
   usbtmc_state.capabilities = tud_usbtmc_get_capabilities_cb();
 #ifndef NDEBUG
 # if CFG_TUD_USBTMC_ENABLE_488
-    if(usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger)
-      TU_ASSERT(&tud_usbtmc_msg_trigger_cb != NULL,);
-      // Per USB488 spec: table 8
-      TU_ASSERT(!usbtmc_state.capabilities->bmIntfcCapabilities.listenOnly,);
-      TU_ASSERT(!usbtmc_state.capabilities->bmIntfcCapabilities.talkOnly,);
+  if (usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger) {
+    TU_ASSERT(&tud_usbtmc_msg_trigger_cb != NULL,);
+  }
+  // Per USB488 spec: table 8
+  TU_ASSERT(!usbtmc_state.capabilities->bmIntfcCapabilities.listenOnly,);
+  TU_ASSERT(!usbtmc_state.capabilities->bmIntfcCapabilities.talkOnly,);
 # endif
-    if(usbtmc_state.capabilities->bmIntfcCapabilities.supportsIndicatorPulse)
-      TU_ASSERT(&tud_usbtmc_indicator_pulse_cb != NULL,);
+  if (usbtmc_state.capabilities->bmIntfcCapabilities.supportsIndicatorPulse) {
+    TU_ASSERT(&tud_usbtmc_indicator_pulse_cb != NULL,);
+  }
 #endif
 
-    usbtmcLock = osal_mutex_create(&usbtmcLockBuffer);
+  usbtmcLock = osal_mutex_create(&usbtmcLockBuffer);
 }
 
 uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)

From bed8913107efeb4b38d80f5cc4caef2fd351b57f Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Wed, 5 Jan 2022 16:17:19 -0800
Subject: [PATCH 0768/2085] Skip dfu and usbtmc on pi zero

---
 examples/device/dfu/skip.txt    | 3 ++-
 examples/device/usbtmc/skip.txt | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)
 create mode 100644 examples/device/usbtmc/skip.txt

diff --git a/examples/device/dfu/skip.txt b/examples/device/dfu/skip.txt
index 2c9d94902..9ac346bad 100644
--- a/examples/device/dfu/skip.txt
+++ b/examples/device/dfu/skip.txt
@@ -1 +1,2 @@
-mcu:TM4C123
\ No newline at end of file
+mcu:TM4C123
+mcu:BCM2835
diff --git a/examples/device/usbtmc/skip.txt b/examples/device/usbtmc/skip.txt
new file mode 100644
index 000000000..a43106cf0
--- /dev/null
+++ b/examples/device/usbtmc/skip.txt
@@ -0,0 +1 @@
+mcu:BCM2835

From 44406a8940a96bbe03e103a4f4895ec19183941f Mon Sep 17 00:00:00 2001
From: EmergReanimator <emerg.reanimator@gmail.com>
Date: Thu, 6 Jan 2022 09:56:45 +0100
Subject: [PATCH 0769/2085] Enable breakpoints for ARM8M (e.g. cortex-m33)

---
 src/common/tusb_verify.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 56ba8bcd1..8fef11dc7 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -37,31 +37,31 @@
  * manipulation that you are told to stay away.
  *
  * This contains macros for both VERIFY and ASSERT:
- * 
+ *
  *   VERIFY: Used when there is an error condition which is not the
  *           fault of the MCU. For example, bounds checking on data
  *           sent to the micro over USB should use this function.
  *           Another example is checking for buffer overflows, where
  *           returning from the active function causes a NAK.
- * 
+ *
  *   ASSERT: Used for error conditions that are caused by MCU firmware
  *           bugs. This is used to discover bugs in the code more
  *           quickly. One example would be adding assertions in library
  *           function calls to confirm a function's (untainted)
  *           parameters are valid.
- * 
+ *
  * The difference in behavior is that ASSERT triggers a breakpoint while
  * verify does not.
  *
  *   #define TU_VERIFY(cond)                  if(cond) return false;
  *   #define TU_VERIFY(cond,ret)              if(cond) return ret;
- *   
+ *
  *   #define TU_VERIFY_HDLR(cond,handler)     if(cond) {handler; return false;}
  *   #define TU_VERIFY_HDLR(cond,ret,handler) if(cond) {handler; return ret;}
  *
  *   #define TU_ASSERT(cond)                  if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return false;}
  *   #define TU_ASSERT(cond,ret)              if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return ret;}
- *  
+ *
  *------------------------------------------------------------------*/
 
 #ifdef __cplusplus
@@ -81,8 +81,8 @@
   #define _MESS_FAILED() do {} while (0)
 #endif
 
-// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
-#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)
   #define TU_BREAKPOINT() do                                                                                \
   {                                                                                                         \
     volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \

From 13015a17a4f40ffdd7a5e38c54f9e1370b167335 Mon Sep 17 00:00:00 2001
From: "Man, Jianting (Meco)" <920369182@qq.com>
Date: Thu, 6 Jan 2022 12:40:08 -0500
Subject: [PATCH 0770/2085] Update README.rst

---
 README.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index faeef3663..b72436390 100644
--- a/README.rst
+++ b/README.rst
@@ -90,7 +90,7 @@ TinyUSB is completely thread-safe by pushing all Interrupt Service Request (ISR)
 
 - **No OS**
 - **FreeRTOS**
-- **RT-Thread** (https://github.com/tfx2001/tinyusb)
+- **RT-Thread** (https://github.com/RT-Thread/rt-thread)
 - **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its [own repo](https://github.com/hathach/mynewt-tinyusb-example)
 
 Local Docs

From a284e438f1952315631f354dee2b30b264afb324 Mon Sep 17 00:00:00 2001
From: Valentin Milea <valentin.milea@gmail.com>
Date: Fri, 7 Jan 2022 15:02:52 +0200
Subject: [PATCH 0771/2085] Disable feedback format correction by default #1234

---
 src/class/audio/audio_device.c |  6 ++----
 src/class/audio/audio_device.h | 22 +++++++++++-----------
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index a461e97c5..5ffc9b0dc 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2247,14 +2247,12 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
-// Input value feedback has to be in 16.16 format - the format will be converted according to speed settings automatically
-// unless format correction is disabled.
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
 {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
   // Format the feedback value
-#if !TUD_OPT_HIGH_SPEED && !CFG_TUD_AUDIO_DISABLE_FEEDBACK_FORMAT_CORRECTION
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION && !TUD_OPT_HIGH_SPEED
   uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].fb_val;
 
   // For FS format is 10.14
@@ -2264,7 +2262,7 @@ bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
   // 4th byte is needed to work correctly with MS Windows
   *fb = 0;
 #else
-  // For HS format is 16.16 as originally demanded
+  // Send value as-is, caller will choose the appropriate format
   _audiod_fct[func_id].fb_val = feedback;
 #endif
 
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 731fd6c01..f406cf281 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -186,9 +186,9 @@
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP                    0                             // Feedback - 0 or 1
 #endif
 
-// Disable/enable conversion from 16.16 to 10.14 format on high-speed devices. See tud_audio_n_fb_set().
-#ifndef CFG_TUD_AUDIO_DISABLE_FEEDBACK_FORMAT_CORRECTION
-#define CFG_TUD_AUDIO_DISABLE_FEEDBACK_FORMAT_CORRECTION    0                             // 0 or 1
+// Enable/disable conversion from 16.16 to 10.14 format on full-speed devices. See tud_audio_n_fb_set().
+#ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION     0                             // 0 or 1
 #endif
 
 // Audio interrupt control EP size - disabled if 0
@@ -459,15 +459,15 @@ TU_ATTR_WEAK bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_byte
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 TU_ATTR_WEAK bool tud_audio_fb_done_cb(uint8_t rhport);
-// User code should call this function with feedback value in 16.16 format for FS and HS.
-// Value will be corrected for FS to 10.14 format automatically.
-// (see Universal Serial Bus Specification Revision 2.0 5.12.4.2).
-// Feedback value will be sent at FB endpoint interval till it's changed.
+
+// This function is used to provide data rate feedback from an asynchronous sink. Feedback value will be sent at FB endpoint interval till it's changed.
 //
-// Note that the USB Audio 2.0 driver on Windows 10 is not following the spec and expects 16.16
-// format for FS. You can define CFG_TUD_AUDIO_DISABLE_FEEDBACK_FORMAT_CORRECTION=1 as a workaround
-// to transmit the feedback value unchanged. Be aware that this might break feedback on other hosts,
-// though at least on Linux the ALSA driver will happily accept either format.
+// The feedback format is specified to be 16.16 for HS and 10.14 for FS devices (see Universal Serial Bus Specification Revision 2.0 5.12.4.2). By default,
+// the choice of format is left to the caller and feedback argument is sent as-is. If CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION is set, then tinyusb
+// expects 16.16 format and handles the conversion to 10.14 on FS.
+//
+// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the 
+// driver can work with either format. So a good compromise is to keep format correction disabled and stick to 16.16 format.
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
 static inline bool tud_audio_fb_set(uint32_t feedback);
 #endif

From 340309561dbf10f17798dc74731e9804e892e0f4 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sun, 26 Dec 2021 22:37:27 +0100
Subject: [PATCH 0772/2085] Add driver for PIC32MZ MCUs

Device-only driver for PIC32MZ MCUs.
---
 src/device/dcd_attr.h                        |   4 +
 src/portable/microchip/pic32mz/dcd_pic32mz.c | 737 +++++++++++++++++++
 src/tusb_option.h                            |   1 +
 3 files changed, 742 insertions(+)
 create mode 100644 src/portable/microchip/pic32mz/dcd_pic32mz.c

diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index 3c5dadaf4..bd8994fd8 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -86,6 +86,10 @@
   #define DCD_ATTR_ENDPOINT_MAX   10
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
+#elif TU_CHECK_MCU(OPT_MCU_PIC32MZ)
+  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+
 //------------- ST -------------//
 #elif TU_CHECK_MCU(OPT_MCU_STM32F0)
   #define DCD_ATTR_ENDPOINT_MAX   8
diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c
new file mode 100644
index 000000000..323d01a71
--- /dev/null
+++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c
@@ -0,0 +1,737 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_PIC32MZ
+
+#include <common/tusb_common.h>
+#include <device/dcd.h>
+
+#include <xc.h>
+#include "usbhs_registers.h"
+
+#define USB_REGS  ((usbhs_registers_t *) (_USB_BASE_ADDRESS))
+
+// Maximum number of endpoints, could be trimmed down in tusb_config to reduce RAM usage.
+#ifndef EP_MAX
+#define EP_MAX            8
+#endif
+
+
+typedef enum {
+  EP0_STAGE_NONE,
+  EP0_STAGE_SETUP_IN_DATA,
+  EP0_STAGE_SETUP_OUT_NO_DATA,
+  EP0_STAGE_SETUP_OUT_DATA,
+  EP0_STAGE_DATA_IN,
+  EP0_STAGE_DATA_IN_LAST_PACKET_FILLED,
+  EP0_STAGE_DATA_IN_SENT,
+  EP0_STAGE_DATA_OUT,
+  EP0_STAGE_DATA_OUT_COMPLETE,
+  EP0_STAGE_STATUS_IN,
+  EP0_STAGE_ADDRESS_CHANGE,
+} ep0_stage_t;
+
+typedef struct {
+  uint8_t * buffer;
+  // Total length of current transfer
+  uint16_t total_len;
+  // Bytes transferred so far
+  uint16_t transferred;
+  uint16_t max_packet_size;
+  uint16_t fifo_size;
+  // Packet size sent or received so far. It is used to modify transferred field
+  // after ACK is received or when filling ISO endpoint with size larger then
+  // FIFO size.
+  uint16_t last_packet_size;
+  uint8_t ep_addr;
+} xfer_ctl_t;
+
+static struct
+{
+  // Current FIFO RAM address used for FIFO allocation
+  uint16_t fifo_addr_top;
+  // EP0 transfer stage
+  ep0_stage_t ep0_stage;
+  // Device address
+  uint8_t dev_addr;
+  xfer_ctl_t xfer_status[EP_MAX][2];
+} _dcd;
+
+// Two endpoint 0 descriptor definition for unified dcd_edpt_open()
+static tusb_desc_endpoint_t const ep0OUT_desc =
+{
+  .bLength          = sizeof(tusb_desc_endpoint_t),
+  .bDescriptorType  = TUSB_DESC_ENDPOINT,
+
+  .bEndpointAddress = 0x00,
+  .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
+  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
+  .bInterval        = 0
+};
+
+static tusb_desc_endpoint_t const ep0IN_desc =
+{
+  .bLength          = sizeof(tusb_desc_endpoint_t),
+  .bDescriptorType  = TUSB_DESC_ENDPOINT,
+
+  .bEndpointAddress = 0x80,
+  .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
+  .wMaxPacketSize   = CFG_TUD_ENDPOINT0_SIZE,
+  .bInterval        = 0
+};
+
+#define XFER_CTL_BASE(_ep, _dir) &_dcd.xfer_status[_ep][_dir]
+
+static void ep0_set_stage(ep0_stage_t stage)
+{
+  _dcd.ep0_stage = stage;
+}
+
+static ep0_stage_t ep0_get_stage(void)
+{
+  return _dcd.ep0_stage;
+}
+
+/*------------------------------------------------------------------*/
+/* Controller API
+ *------------------------------------------------------------------*/
+void dcd_init(uint8_t rhport)
+{
+  // Disable endpoint interrupts for now
+  USB_REGS->INTRRXEbits.w = 0;
+  USB_REGS->INTRTXEbits.w = 0;
+  // Enable Reset/Suspend/Resume interrupts only
+  USB_REGS->INTRUSBEbits.w = 7;
+
+  dcd_connect(rhport);
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+
+  USBCRCONbits.USBIE = 1;
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+
+  USBCRCONbits.USBIE = 0;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  (void) rhport;
+
+  ep0_set_stage(EP0_STAGE_ADDRESS_CHANGE);
+  // Store address it will be used later after status stage is done
+  _dcd.dev_addr = dev_addr;
+  // Confirm packet now, address will be set when status stage is detected
+  USB_REGS->EPCSR[0].CSR0L_DEVICEbits.w = (USBHS_EP0_DEVICE_SERVICED_RXPKTRDY | USBHS_EP0_DEVICE_DATAEND);
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+
+  USB_REGS->POWERbits.RESUME = 1;
+#if CFG_TUSB_OS != OPT_OS_NONE
+  osal_task_delay(10);
+#endif
+  USB_REGS->POWERbits.RESUME = 0;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+
+  USB_REGS->POWERbits.HSEN = TUD_OPT_HIGH_SPEED ? 1 : 0;
+  USB_REGS->POWERbits.SOFTCONN = 1;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  (void) rhport;
+
+  USB_REGS->POWERbits.SOFTCONN = 1;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
+{
+  return (_CP0_GET_STATUS() & (_CP0_STATUS_EXL_MASK | _CP0_STATUS_IPL_MASK)) != 0;
+}
+
+static void epn_rx_configure(uint8_t endpoint, uint16_t endpointSize,
+                             uint16_t fifoAddress, uint8_t fifoSize,
+                             uint32_t transferType)
+{
+  uint8_t old_index = USB_REGS->INDEXbits.ENDPOINT;
+
+  // Select endpoint register set (same register address is used for all endpoints.
+  USB_REGS->INDEXbits.ENDPOINT = endpoint;
+
+  // Configure the Endpoint size
+  USB_REGS->INDEXED_EPCSR.RXMAXPbits.RXMAXP = endpointSize;
+
+  // Set up the fifo address.
+  USB_REGS->RXFIFOADDbits.RXFIFOAD = fifoAddress;
+
+  // Resets the endpoint data toggle to 0
+  USB_REGS->INDEXED_EPCSR.RXCSRL_DEVICEbits.CLRDT = 1;
+
+  // Set up the FIFO size
+  USB_REGS->RXFIFOSZbits.RXFIFOSZ = fifoSize;
+
+  USB_REGS->INDEXED_EPCSR.RXCSRH_DEVICEbits.ISO = transferType == 1 ? 1 : 0;
+  // Disable NYET Handshakes for interrupt endpoints
+  USB_REGS->INDEXED_EPCSR.RXCSRH_DEVICEbits.DISNYET = transferType == 3 ? 1 : 0;
+
+  // Restore the index register.
+  USB_REGS->INDEXbits.ENDPOINT = old_index;
+
+  // Enable the endpoint interrupt.
+  USB_REGS->INTRRXEbits.w |= (1 << endpoint);
+}
+
+static void epn_tx_configure(uint8_t endpoint, uint16_t endpointSize,
+                             uint16_t fifoAddress, uint8_t fifoSize,
+                             uint32_t transferType)
+{
+  uint8_t old_index = USB_REGS->INDEXbits.ENDPOINT;
+
+  // Select endpoint register set (same register address is used for all endpoints.
+  USB_REGS->INDEXbits.ENDPOINT = endpoint;
+
+  // Configure the Endpoint size
+  USB_REGS->INDEXED_EPCSR.TXMAXPbits.TXMAXP = endpointSize;
+
+  // Set up the fifo address
+  USB_REGS->TXFIFOADDbits.TXFIFOAD = fifoAddress;
+
+  // Resets the endpoint data toggle to 0
+  USB_REGS->INDEXED_EPCSR.TXCSRL_DEVICEbits.CLRDT = 1;
+
+  // Set up the FIFO size
+  USB_REGS->TXFIFOSZbits.TXFIFOSZ = fifoSize;
+
+  USB_REGS->INDEXED_EPCSR.TXCSRH_DEVICEbits.ISO = 1 == transferType ? 1 : 0;
+
+  // Restore the index register
+  USB_REGS->INDEXbits.ENDPOINT = old_index;
+
+  // Enable the interrupt
+  USB_REGS->INTRTXEbits.w |=  (1 << endpoint);
+}
+
+static void tx_fifo_write(uint8_t endpoint, uint8_t const * buffer, size_t count)
+{
+  size_t i;
+  volatile uint8_t * fifo_reg;
+
+  fifo_reg = (volatile uint8_t *) (&USB_REGS->FIFO[endpoint]);
+
+  for (i = 0; i < count; i++)
+  {
+    *fifo_reg = buffer[i];
+  }
+}
+
+static int rx_fifo_read(uint8_t epnum, uint8_t * buffer)
+{
+  uint32_t i;
+  uint32_t count;
+  volatile uint8_t * fifo_reg;
+
+  fifo_reg = (volatile uint8_t *) (&USB_REGS->FIFO[epnum]);
+
+  count = USB_REGS->EPCSR[epnum].RXCOUNTbits.RXCNT;
+
+  for (i = 0; i < count; i++)
+  {
+    buffer[i] = fifo_reg[i & 3];
+  }
+
+  return count;
+}
+
+static void xfer_complete(xfer_ctl_t * xfer, uint8_t result, bool in_isr)
+{
+  dcd_event_xfer_complete(0, xfer->ep_addr, xfer->transferred, result, in_isr);
+}
+
+static void ep0_fill_tx(xfer_ctl_t * xfer_in)
+{
+  uint16_t left = xfer_in->total_len - xfer_in->transferred;
+
+  if (left)
+  {
+    xfer_in->last_packet_size = tu_min16(xfer_in->max_packet_size, left);
+    tx_fifo_write(0, xfer_in->buffer + xfer_in->transferred, xfer_in->last_packet_size);
+    xfer_in->transferred += xfer_in->last_packet_size;
+    left = xfer_in->total_len - xfer_in->transferred;
+  }
+
+  if (xfer_in->last_packet_size < xfer_in->max_packet_size || left == 0)
+  {
+    switch (ep0_get_stage())
+    {
+      case EP0_STAGE_SETUP_IN_DATA:
+      case EP0_STAGE_DATA_IN:
+      case EP0_STAGE_DATA_IN_SENT:
+        ep0_set_stage(EP0_STAGE_DATA_IN_LAST_PACKET_FILLED);
+        USB_REGS->EPCSR[0].CSR0L_DEVICEbits.TXPKTRDY = 1;
+        break;
+      case EP0_STAGE_SETUP_OUT_NO_DATA:
+        ep0_set_stage(EP0_STAGE_STATUS_IN);
+        USB_REGS->EPCSR[0].CSR0L_DEVICEbits.w = (USBHS_EP0_DEVICE_SERVICED_RXPKTRDY | USBHS_EP0_DEVICE_DATAEND);
+        break;
+      case EP0_STAGE_DATA_OUT_COMPLETE:
+        ep0_set_stage(EP0_STAGE_STATUS_IN);
+        USB_REGS->EPCSR[0].CSR0L_DEVICEbits.w = (USBHS_EP0_DEVICE_SERVICED_RXPKTRDY | USBHS_EP0_DEVICE_DATAEND);
+        break;
+      default:
+        break;
+    }
+  }
+  else
+  {
+    switch (ep0_get_stage())
+    {
+      case EP0_STAGE_SETUP_IN_DATA:
+        ep0_set_stage(EP0_STAGE_DATA_IN);
+        // fall through
+      case EP0_STAGE_DATA_IN:
+        USB_REGS->EPCSR[0].CSR0L_DEVICEbits.TXPKTRDY = 1;
+        break;
+      default:
+        break;
+    }
+  }
+}
+
+static void epn_fill_tx(xfer_ctl_t * xfer_in, uint8_t epnum)
+{
+  uint16_t left = xfer_in->total_len - xfer_in->transferred;
+  if (left)
+  {
+    xfer_in->last_packet_size = tu_min16(xfer_in->max_packet_size, left);
+    tx_fifo_write(epnum, xfer_in->buffer + xfer_in->transferred, xfer_in->last_packet_size);
+  }
+  USB_REGS->EPCSR[epnum].TXCSRL_DEVICEbits.TXPKTRDY = 1;
+}
+
+static bool ep0_xfer(xfer_ctl_t * xfer, int dir)
+{
+  if (dir == TUSB_DIR_OUT)
+  {
+    if (xfer->total_len)
+    {
+      switch (_dcd.ep0_stage)
+      {
+        case EP0_STAGE_DATA_OUT_COMPLETE:
+        case EP0_STAGE_SETUP_OUT_DATA:
+          ep0_set_stage(EP0_STAGE_DATA_OUT);
+          USB_REGS->EPCSR[0].CSR0L_DEVICEbits.SVCRPR = 1;
+          break;
+        default:
+          TU_ASSERT(0);
+      }
+    }
+    else
+    {
+      switch (_dcd.ep0_stage)
+      {
+        case EP0_STAGE_DATA_IN_SENT:
+          ep0_set_stage(EP0_STAGE_NONE);
+          // fall through
+        case EP0_STAGE_NONE:
+          xfer_complete(xfer, XFER_RESULT_SUCCESS, true);
+          break;
+        default:
+          break;
+      }
+    }
+  }
+  else // IN
+  {
+    ep0_fill_tx(xfer);
+  }
+
+  return true;
+}
+
+/*------------------------------------------------------------------*/
+/* DCD Endpoint port
+ *------------------------------------------------------------------*/
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
+{
+  (void) rhport;
+  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
+  uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+
+  TU_ASSERT(epnum < EP_MAX);
+
+  xfer->max_packet_size = tu_edpt_packet_size(desc_edpt);
+  xfer->fifo_size = xfer->max_packet_size;
+  xfer->ep_addr = desc_edpt->bEndpointAddress;
+
+  if (epnum != 0)
+  {
+    if (dir == TUSB_DIR_OUT)
+    {
+      epn_rx_configure(epnum, xfer->max_packet_size, _dcd.fifo_addr_top, __builtin_ctz(xfer->fifo_size) - 3, desc_edpt->bmAttributes.xfer);
+      _dcd.fifo_addr_top += (xfer->fifo_size + 7) >> 3;
+    }
+    else
+    {
+      epn_tx_configure(epnum, xfer->max_packet_size, _dcd.fifo_addr_top, __builtin_ctz(xfer->fifo_size) - 3, desc_edpt->bmAttributes.xfer);
+      _dcd.fifo_addr_top += (xfer->fifo_size + 7) >> 3;
+    }
+  }
+  return true;
+}
+
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+
+  // Reserve EP0 FIFO address
+  _dcd.fifo_addr_top = 64 >> 3;
+  for (int i = 1; i < EP_MAX; ++i)
+  {
+    tu_memclr(&_dcd.xfer_status[i], sizeof(_dcd.xfer_status[i]));
+  }
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  (void) ep_addr;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
+  (void) rhport;
+
+  xfer->buffer = buffer;
+  xfer->total_len = total_bytes;
+  xfer->last_packet_size = 0;
+  xfer->transferred = 0;
+
+  if (epnum == 0)
+  {
+    return ep0_xfer(xfer, dir);
+  }
+  if (dir == TUSB_DIR_OUT)
+  {
+    USB_REGS->INTRRXEbits.w |= (1u << epnum);
+  }
+  else // IN
+  {
+    epn_fill_tx(xfer, epnum);
+  }
+
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  (void) rhport;
+
+  if (epnum == 0)
+  {
+    USB_REGS->EPCSR[0].CSR0L_DEVICEbits.SENDSTALL = 1;
+  }
+  else
+  {
+    if (dir == TUSB_DIR_OUT)
+    {
+      USB_REGS->EPCSR[epnum].RXCSRL_DEVICEbits.SENDSTALL = 1;
+    }
+    else
+    {
+      USB_REGS->EPCSR[epnum].TXCSRL_DEVICEbits.SENDSTALL = 1;
+    }
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  (void) rhport;
+
+  if (epnum == 0)
+  {
+    USB_REGS->EPCSR[0].CSR0L_DEVICEbits.SENDSTALL = 0;
+  }
+  else
+  {
+    if (dir == TUSB_DIR_OUT)
+    {
+      USB_REGS->EPCSR[epnum].RXCSRL_DEVICEbits.w &= ~(USBHS_EP_DEVICE_RX_SENT_STALL | USBHS_EP_DEVICE_RX_SEND_STALL);
+      USB_REGS->EPCSR[epnum].RXCSRL_DEVICEbits.CLRDT = 1;
+    }
+    else
+    {
+      USB_REGS->EPCSR[epnum].TXCSRL_DEVICEbits.w &= ~(USBHS_EP_DEVICE_TX_SENT_STALL | USBHS_EP_DEVICE_TX_SEND_STALL);
+      USB_REGS->EPCSR[epnum].TXCSRL_DEVICEbits.CLRDT = 1;
+    }
+  }
+}
+
+/*------------------------------------------------------------------*/
+/* Interrupt Handler
+ *------------------------------------------------------------------*/
+
+static void ep0_handle_rx(void)
+{
+  int transferred;
+  xfer_ctl_t * xfer = XFER_CTL_BASE(0, TUSB_DIR_OUT);
+
+  TU_ASSERT(xfer->buffer,);
+
+  transferred = rx_fifo_read(0, xfer->buffer + xfer->transferred);
+  xfer->transferred += transferred;
+  if (transferred < xfer->max_packet_size || xfer->transferred == xfer->total_len)
+  {
+    ep0_set_stage(EP0_STAGE_DATA_OUT_COMPLETE);
+    xfer_complete(xfer, XFER_RESULT_SUCCESS, true);
+  }
+  else
+  {
+    USB_REGS->EPCSR[0].CSR0L_DEVICEbits.SVCRPR = 1;
+  }
+}
+
+static void epn_handle_rx_int(uint8_t epnum)
+{
+  uint8_t ep_status;
+  int transferred;
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+
+  ep_status = USB_REGS->EPCSR[epnum].RXCSRL_DEVICEbits.w;
+  if (ep_status & USBHS_EP_DEVICE_RX_SENT_STALL)
+  {
+    USB_REGS->EPCSR[epnum].RXCSRL_DEVICEbits.w &= ~USBHS_EP_DEVICE_RX_SENT_STALL;
+  }
+
+  if (ep_status & USBHS_EP0_HOST_RXPKTRDY)
+  {
+    TU_ASSERT(xfer->buffer != NULL,);
+
+    transferred = rx_fifo_read(epnum, xfer->buffer + xfer->transferred);
+    USB_REGS->EPCSR[epnum].RXCSRL_HOSTbits.RXPKTRDY = 0;
+    xfer->transferred += transferred;
+    if (transferred < xfer->max_packet_size || xfer->transferred == xfer->total_len)
+    {
+      xfer_complete(xfer, XFER_RESULT_SUCCESS, true);
+    }
+  }
+}
+
+static void epn_handle_tx_int(uint8_t epnum)
+{
+  uint8_t ep_status = USB_REGS->EPCSR[epnum].TXCSRL_DEVICEbits.w;
+  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
+
+  if (ep_status & USBHS_EP_DEVICE_TX_SENT_STALL)
+  {
+    USB_REGS->EPCSR[epnum].TXCSRL_DEVICEbits.w &= ~USBHS_EP_DEVICE_TX_SENT_STALL;
+  }
+  else
+  {
+    xfer->transferred += xfer->last_packet_size;
+    if (xfer->last_packet_size < xfer->max_packet_size || xfer->transferred == xfer->total_len)
+    {
+      xfer->last_packet_size = 0;
+      xfer_complete(xfer, XFER_RESULT_SUCCESS, true);
+    }
+    else
+    {
+      epn_fill_tx(xfer, epnum);
+    }
+  }
+}
+
+static void ep0_handle_int(void)
+{
+  __USBHS_CSR0L_DEVICE_t  ep0_status;
+  union {
+    tusb_control_request_t request;
+    uint32_t setup_buffer[2];
+  } setup_packet;
+  xfer_ctl_t * xfer_in = XFER_CTL_BASE(0, TUSB_DIR_IN);
+  uint8_t old_index = USB_REGS->INDEXbits.ENDPOINT;
+
+  // Select EP0 registers
+  USB_REGS->INDEXbits.ENDPOINT = 0;
+
+  ep0_status = USB_REGS->EPCSR[0].CSR0L_DEVICEbits;
+
+  if (ep0_status.SENTSTALL)
+  {
+    // Stall was sent. Reset the endpoint 0 state.
+    // Clear the sent stall bit.
+    ep0_set_stage(EP0_STAGE_NONE);
+    USB_REGS->EPCSR[0].CSR0L_DEVICEbits.SENTSTALL = 0;
+  }
+
+  if (ep0_status.SETUPEND)
+  {
+    // This means the current control transfer end prematurely. We don't
+    // need to end any transfers. The device layer will manage the
+    // premature transfer end. We clear the SetupEnd bit and reset the
+    // driver control transfer state machine to waiting for next setup
+    // packet from host.
+    USB_REGS->EPCSR[0].CSR0L_DEVICEbits.SVSSETEND = 1;
+    ep0_set_stage(EP0_STAGE_NONE);
+  }
+
+  if (ep0_status.RXPKTRDY)
+  {
+    switch (ep0_get_stage())
+    {
+      default:
+        // Data arrived at unexpected state, this must be setup stage packet after all.
+        // Fall through
+      case EP0_STAGE_NONE:
+        // This means we were expecting a SETUP packet and we got one.
+        setup_packet.setup_buffer[0] = USB_REGS->FIFO[0];
+        setup_packet.setup_buffer[1] = USB_REGS->FIFO[0];
+        if (setup_packet.request.bmRequestType_bit.direction == TUSB_DIR_OUT)
+        {
+          // SVCRPR is not set yet, it will be set later when out xfer is started
+          // Till then NAKs will hold incommint data
+          ep0_set_stage(setup_packet.request.wLength == 0 ? EP0_STAGE_SETUP_OUT_NO_DATA : EP0_STAGE_SETUP_OUT_DATA);
+        }
+        else
+        {
+          USB_REGS->EPCSR[0].CSR0L_DEVICEbits.SVCRPR = 1;
+          ep0_set_stage(EP0_STAGE_SETUP_IN_DATA);
+        }
+        dcd_event_setup_received(0, &setup_packet.request.bmRequestType, true);
+        break;
+      case EP0_STAGE_DATA_OUT:
+        ep0_handle_rx();
+        break;
+    }
+  }
+  else
+  {
+    switch (ep0_get_stage())
+    {
+      case EP0_STAGE_STATUS_IN:
+        // Status was just sent, this concludes request, notify client
+        ep0_set_stage(EP0_STAGE_NONE);
+        xfer_complete(xfer_in, XFER_RESULT_SUCCESS, true);
+        break;
+      case EP0_STAGE_DATA_IN:
+        // Packet sent, fill more data
+        ep0_fill_tx(xfer_in);
+        break;
+      case EP0_STAGE_DATA_IN_LAST_PACKET_FILLED:
+        ep0_set_stage(EP0_STAGE_DATA_IN_SENT);
+        xfer_complete(xfer_in, XFER_RESULT_SUCCESS, true);
+        break;
+      case EP0_STAGE_ADDRESS_CHANGE:
+        // Status stage after set address request finished, address can be changed
+        USB_REGS->FADDRbits.FUNC = _dcd.dev_addr;
+        ep0_set_stage(EP0_STAGE_NONE);
+        break;
+      default:
+        break;
+    }
+  }
+  // Restore register index
+  USB_REGS->INDEXbits.ENDPOINT = old_index;
+}
+
+void dcd_int_handler(uint8_t rhport)
+{
+  int i;
+  uint8_t mask;
+  __USBCSR2bits_t csr2_bits;
+  uint16_t rxints = USB_REGS->INTRRX;
+  uint16_t txints = USB_REGS->INTRTX;
+  csr2_bits = USBCSR2bits;
+  (void) rhport;
+
+  IFS4CLR = _IFS4_USBIF_MASK;
+
+  if (csr2_bits.SOFIF && csr2_bits.SOFIE)
+  {
+    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+  }
+  if (csr2_bits.RESETIF)
+  {
+    dcd_edpt_open(0, &ep0OUT_desc);
+    dcd_edpt_open(0, &ep0IN_desc);
+    dcd_event_bus_reset(0, USB_REGS->POWERbits.HSMODE ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true);
+  }
+  if (csr2_bits.SUSPIF)
+  {
+    dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+  }
+  if (csr2_bits.RESUMEIF)
+  {
+    dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+  }
+  // INTRTX has bit for EP0
+  if (txints & 1)
+  {
+    txints ^= 1;
+    ep0_handle_int();
+  }
+  for (mask = 0x02, i = 1; rxints != 0 && mask != 0; mask <<= 1, ++i)
+  {
+    if (rxints & mask)
+    {
+      rxints ^= mask;
+      epn_handle_rx_int(i);
+    }
+  }
+  for (mask = 0x02, i = 1; txints != 0 && mask != 0; mask <<= 1, ++i)
+  {
+    if (txints & mask)
+    {
+      txints ^= mask;
+      epn_handle_tx_int(i);
+    }
+  }
+}
+
+#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 2edd310fa..4f16a3c1a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -66,6 +66,7 @@
 #define OPT_MCU_SAML22            205 ///< MicroChip SAML22
 #define OPT_MCU_SAML21            206 ///< MicroChip SAML21
 #define OPT_MCU_SAMX7X            207 ///< MicroChip SAME70, S70, V70, V71 family
+#define OPT_MCU_PIC32MZ           220 ///< MicroChip PIC32MZ family
 
 // STM32
 #define OPT_MCU_STM32F0           300 ///< ST F0

From fff4a248bea532f34b5cc27dfc64b7f85c5bef73 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sun, 26 Dec 2021 22:43:45 +0100
Subject: [PATCH 0773/2085] Add BSPs for Microchip PIC32MZ MCUs

Two boards from Olimex are added:
olimex_hmz144  with PIC32MZ2048EFM144
olimex_emz64.c with PIC32MZ2048EFH064

Both can be programmed with Segger JLINK probe using ICSP
interface. (JTAG not tested but could also work but header
is not mounted).
---
 hw/bsp/pic32mz/boards/olimex_emz64/board.mk   |   5 +
 .../boards/olimex_emz64/olimex_emz64.c        | 144 ++++++++++++++++++
 hw/bsp/pic32mz/boards/olimex_hmz144/board.mk  |   5 +
 .../boards/olimex_hmz144/olimex_hmz144.c      | 142 +++++++++++++++++
 hw/bsp/pic32mz/family.c                       | 110 +++++++++++++
 hw/bsp/pic32mz/family.mk                      |  20 +++
 6 files changed, 426 insertions(+)
 create mode 100644 hw/bsp/pic32mz/boards/olimex_emz64/board.mk
 create mode 100644 hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
 create mode 100644 hw/bsp/pic32mz/boards/olimex_hmz144/board.mk
 create mode 100644 hw/bsp/pic32mz/boards/olimex_hmz144/olimex_hmz144.c
 create mode 100644 hw/bsp/pic32mz/family.c
 create mode 100644 hw/bsp/pic32mz/family.mk

diff --git a/hw/bsp/pic32mz/boards/olimex_emz64/board.mk b/hw/bsp/pic32mz/boards/olimex_emz64/board.mk
new file mode 100644
index 000000000..3df5ed92b
--- /dev/null
+++ b/hw/bsp/pic32mz/boards/olimex_emz64/board.mk
@@ -0,0 +1,5 @@
+JLINK_DEVICE=PIC32MZ2048EFH064
+JLINK_IF=ICSP
+
+CFLAGS += \
+  -mprocessor=32MZ2048EFH064 \
diff --git a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
new file mode 100644
index 000000000..0f6dc37e2
--- /dev/null
+++ b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
@@ -0,0 +1,144 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <xc.h>
+#include "tusb.h"
+
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=ON
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#pragma config POSCMOD = EC
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 2 -> 200mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_2
+#pragma config FUSBIDIO=1
+#pragma config WINDIS=NORMAL
+#pragma config WDTSPGM=1
+#pragma config WDTPS=15
+#pragma config FWDTEN=OFF
+
+void button_init(void)
+{
+  // RB12 - button
+  // ANSELB B12 not analog
+  ANSELBCLR = TU_BIT(12);
+  // TRISB B12 input
+  TRISBSET = TU_BIT(12);
+  // Pull-up
+  CNPUBSET = TU_BIT(12);
+}
+
+void led_init(void)
+{
+  // RB8 - LED
+  // ANASELB RB8 not analog
+  ANSELBCLR = TU_BIT(8);
+  // TRISH RH2 input
+  TRISBCLR = TU_BIT(8);
+  // Initial value 0, LED off
+  LATBCLR = TU_BIT(8);
+}
+
+void uart_init(void)
+{
+  // RD4/RD0 Uart4 TX/RX
+  // ANSELD - not present on 64 pin device
+
+  /* Unlock system for PPS configuration */
+  SYSKEY = 0x00000000;
+  SYSKEY = 0xAA996655;
+  SYSKEY = 0x556699AA;
+  CFGCONbits.IOLOCK = 0;
+
+  // PPS Input Remapping
+  // U4RX -> RD0
+  U4RXR = 3;
+
+  // PPS Output Remapping
+  // RD4 -> U4TX
+  RPD4R = 2;
+
+  // Lock back the system after PPS configuration
+  CFGCONbits.IOLOCK = 1;
+  SYSKEY = 0x00000000;
+
+  // UART4
+  // High speed mode
+  // 8 bits, no parity, no RTS/CTS, no flow control
+  U4MODE = 0x0;
+
+  // Enable UART2 Receiver and Transmitter
+  U4STASET = (_U4STA_UTXEN_MASK | _U4STA_URXEN_MASK | _U4STA_UTXISEL1_MASK);
+
+  // BAUD Rate register Setup
+  U4BRG = 100000000 / (16 * 115200) + 1;
+
+  // Disable Interrupts
+  IEC4CLR = _IEC5_U4EIE_MASK | _IEC5_U4RXIE_MASK | _IEC5_U4TXIE_MASK;
+
+  // Turn ON UART2
+  U4MODESET = _U4MODE_ON_MASK;
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  if (state)
+  {
+    LATBSET = TU_BIT(8);
+  }
+  else
+  {
+    LATBCLR = TU_BIT(8);
+  }
+}
+
+uint32_t board_button_read(void)
+{
+  return (PORTB >> 12) & 1;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  int i = len;
+  uint8_t const * data = buf;
+  while (i--)
+  {
+    while (U4STAbits.UTXBF) ;
+    U4TXREG = *data++;
+  }
+  return len;
+}
diff --git a/hw/bsp/pic32mz/boards/olimex_hmz144/board.mk b/hw/bsp/pic32mz/boards/olimex_hmz144/board.mk
new file mode 100644
index 000000000..a43b62d32
--- /dev/null
+++ b/hw/bsp/pic32mz/boards/olimex_hmz144/board.mk
@@ -0,0 +1,5 @@
+JLINK_DEVICE=PIC32MZ2048EFM144
+JLINK_IF=ICSP
+
+CFLAGS += \
+  -mprocessor=32MZ2048EFM144 \
diff --git a/hw/bsp/pic32mz/boards/olimex_hmz144/olimex_hmz144.c b/hw/bsp/pic32mz/boards/olimex_hmz144/olimex_hmz144.c
new file mode 100644
index 000000000..4ecbe75a1
--- /dev/null
+++ b/hw/bsp/pic32mz/boards/olimex_hmz144/olimex_hmz144.c
@@ -0,0 +1,142 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <xc.h>
+#include "tusb.h"
+
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=ON
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#pragma config POSCMOD = HS
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 2 -> 200mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_2
+#pragma config FUSBIDIO=1
+#pragma config WINDIS=NORMAL
+#pragma config WDTSPGM=1
+#pragma config WDTPS=15
+#pragma config FWDTEN=OFF
+
+void button_init(void)
+{
+  // RB12 - button
+  // ANSELB B12 not analog
+  ANSELBCLR = TU_BIT(12);
+  // TRISB B12 input
+  TRISBSET = TU_BIT(12);
+}
+
+void led_init(void)
+{
+  // RH2 - LED
+  // ANASELH no analog function on RH2
+  // TRISH RH2 input
+  TRISHCLR = TU_BIT(2);
+  // Initial value 0, LED off
+  LATHCLR = TU_BIT(2);
+}
+
+void uart_init(void)
+{
+  // RE8/RE9 Uart2 TX/RX
+  // ANSELE - TX/RX not analog
+  ANSELECLR = TU_BIT(8) | TU_BIT(9);
+
+  /* Unlock system for PPS configuration */
+  SYSKEY = 0x00000000;
+  SYSKEY = 0xAA996655;
+  SYSKEY = 0x556699AA;
+  CFGCONbits.IOLOCK = 0;
+
+  // PPS Input Remapping
+  // U2RX -> RE9
+  U2RXR = 13;
+
+  // PPS Output Remapping
+  // RE8 -> U2TX
+  RPE8R = 2;
+
+  // Lock back the system after PPS configuration
+  CFGCONbits.IOLOCK = 1;
+  SYSKEY = 0x00000000;
+
+  // UART2
+  // High speed mode
+  // 8 bits, no parity, no RTS/CTS, no flow control
+  U2MODE = 0x0;
+
+  // Enable UART2 Receiver and Transmitter
+  U2STASET = (_U2STA_UTXEN_MASK | _U2STA_URXEN_MASK | _U2STA_UTXISEL1_MASK);
+
+  // BAUD Rate register Setup
+  U2BRG = 100000000 / (16 * 115200) + 1;
+
+  // Disable Interrupts
+  IEC4CLR = _IEC4_U2EIE_MASK | _IEC4_U2RXIE_MASK | _IEC4_U2TXIE_MASK;
+
+  // Turn ON UART2
+  U2MODESET = _U2MODE_ON_MASK;
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  if (state)
+  {
+    LATHSET = TU_BIT(2);
+  }
+  else
+  {
+    LATHCLR = TU_BIT(2);
+  }
+}
+
+uint32_t board_button_read(void)
+{
+  return (PORTB >> 12) & 1;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  int i = len;
+  uint8_t const * data = buf;
+  while (i--)
+  {
+    while (U2STAbits.UTXBF) ;
+    U2TXREG = *data++;
+  }
+  return len;
+}
diff --git a/hw/bsp/pic32mz/family.c b/hw/bsp/pic32mz/family.c
new file mode 100644
index 000000000..786f04978
--- /dev/null
+++ b/hw/bsp/pic32mz/family.c
@@ -0,0 +1,110 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <xc.h>
+#include "tusb.h"
+
+void __attribute__((interrupt(IPL2AUTO), vector(_USB_VECTOR), no_fpu))
+USBD_IRQHandler(void)
+{
+  IFS4CLR = _IFS4_USBIF_MASK;
+  tud_int_handler(0);
+}
+
+TU_ATTR_WEAK void button_init(void)
+{
+}
+
+TU_ATTR_WEAK void led_init(void)
+{
+}
+
+TU_ATTR_WEAK void uart_init(void)
+{
+}
+
+void board_init(void)
+{
+  button_init();
+  led_init();
+  uart_init();
+
+  // Force device mode by overriding USB ID and settings it to 1
+  USBCRCONbits.PHYIDEN = 0;
+  USBCRCONbits.USBIDVAL = 1;
+  USBCRCONbits.USBIDOVEN = 1;
+
+  // set interrupt priority (must much IPL2AUTO)
+  IPC33CLR = _IPC33_USBIP_MASK;
+  IPC33SET = (2 << _IPC33_USBIP_POSITION);
+  // set interrupt subpriority
+  IPC33CLR = _IPC33_USBIS_MASK;
+  IPC33SET = (0 << _IPC33_USBIS_POSITION);
+
+  USBCRCONbits.USBIE = 0;
+  IFS4CLR = _IFS4_USBIF_MASK;
+  IEC4SET = _IEC4_USBIE_MASK;
+
+  __builtin_enable_interrupts();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+TU_ATTR_WEAK void board_led_write(bool state)
+{
+  (void) state;
+}
+
+TU_ATTR_WEAK uint32_t board_button_read(void)
+{
+  return 0;
+}
+
+TU_ATTR_WEAK int board_uart_read(uint8_t * buf, int len)
+{
+  (void) buf;
+  (void) len;
+
+  return 0;
+}
+
+TU_ATTR_WEAK int board_uart_write(void const * buf, int len)
+{
+  (void) buf;
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+uint32_t board_millis(void)
+{
+  // COUNTER is system clock (200MHz / 2 = 100MHz) convert to ms)
+  return _CP0_GET_COUNT() / (100000000 / 1000);
+}
+#endif
diff --git a/hw/bsp/pic32mz/family.mk b/hw/bsp/pic32mz/family.mk
new file mode 100644
index 000000000..48e08689f
--- /dev/null
+++ b/hw/bsp/pic32mz/family.mk
@@ -0,0 +1,20 @@
+CROSS_COMPILE = xc32-
+CFLAGS_OPTIMIZED = -O2
+LIBS_GCC = -lgcc -lm
+SKIP_NANOLIB = 1
+
+CFLAGS = \
+  -std=c99 \
+  -DCFG_TUSB_MCU=OPT_MCU_PIC32MZ
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+SRC_C += \
+	src/portable/microchip/pic32mz/dcd_pic32mz.c \
+
+INC += \
+	$(TOP)/hw/mcu/microchip/pic32mz \
+	$(TOP)/$(BOARD_PATH) \
+
+# flash target using jlink
+flash: flash-jlink

From c5d825450ab35f11bf9370b5cacc21706d3d0780 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 13 Jan 2022 00:24:56 +0900
Subject: [PATCH 0774/2085] Fix dwFrameIntervalStep and dwMaxFrameInterval

dwMaxFrameInterval minus dwMinFrameInterval should be evenly divisible by
dwFrameIntervalStep.
---
 examples/device/video_capture/src/usb_descriptors.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index eeaef6bd2..23511c909 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -103,7 +103,7 @@ enum {
         TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
             _width * _height * 16, _width * _height * 16 * _fps, \
             _width * _height * 16, \
-            (10000000/_fps), (10000000/_fps), 10000000, 100000), \
+            (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
         TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
   /* VS alt 1 */\
   TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \

From 3db9cf354795603dd815aa4b85995f52bf9fc530 Mon Sep 17 00:00:00 2001
From: Liam Fraser <liam@raspberrypi.com>
Date: Thu, 13 Jan 2022 13:42:28 +0000
Subject: [PATCH 0775/2085] Fix family_support.cmake to use new skip.txt and
 only.txt files for skipping mcus

---
 hw/bsp/family_support.cmake | 55 ++++++++++++++++++++++++++++---------
 1 file changed, 42 insertions(+), 13 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index af0e00b2d..a8cc1f363 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -11,23 +11,52 @@ if (NOT TARGET _family_support_marker)
 
     function(family_filter RESULT DIR)
         get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
-        file(GLOB ONLYS "${DIR}/.only.MCU_*")
-        if (ONLYS)
+
+        if (EXISTS "${DIR}/only.txt")
+            file(READ "${DIR}/only.txt" ONLYS)
+            # Replace newlines with semicolon so that it is treated as a list by CMake
+            string(REPLACE "\n" ";" ONLYS_LINES ${ONLYS})
+            # For each mcu
             foreach(MCU IN LISTS FAMILY_MCUS)
-                if (EXISTS ${DIR}/.only.MCU_${MCU})
-                    set(${RESULT} 1 PARENT_SCOPE)
-                    return()
-                endif()
+                # For each line in only.txt
+                foreach(_line ${ONLYS_LINES})
+                    # If mcu:xxx exists for this mcu then include
+                    if (${_line} STREQUAL "mcu:${MCU}")
+                        set(${RESULT} 1 PARENT_SCOPE)
+                        return()
+                    endif()
+                endforeach()
             endforeach()
+
+            # Didn't find it in only file so don't build
+            set(${RESULT} 0 PARENT_SCOPE)
+
+        elseif (EXISTS "${DIR}/skip.txt")
+            file(READ "${DIR}/skip.txt" SKIPS)
+            # Replace newlines with semicolon so that it is treated as a list by CMake
+            string(REPLACE "\n" ";" SKIPS_LINES ${SKIPS})
+            # For each mcu
+            foreach(MCU IN LISTS FAMILY_MCUS)
+                # For each line in only.txt
+                foreach(_line ${SKIPS_LINES})
+                    # If mcu:xxx exists for this mcu then skip
+                    if (${_line} STREQUAL "mcu:${MCU}")
+                        set(${RESULT} 0 PARENT_SCOPE)
+                        return()
+                    endif()
+                endforeach()
+            endforeach()
+
+            # Didn't find in skip file so build
+            set(${RESULT} 1 PARENT_SCOPE)
+
         else()
-            foreach(MCU IN LISTS FAMILY_MCUS)
-                if (EXISTS ${DIR}/.skip.MCU_${MCU})
-                    set(${RESULT} 0 PARENT_SCOPE)
-                    return()
-                endif()
-            endforeach()
+
+            # Didn't find skip or only file so build
+            set(${RESULT} 1 PARENT_SCOPE)
+
         endif()
-        set(${RESULT} 1 PARENT_SCOPE)
+
     endfunction()
 
     function(family_add_subdirectory DIR)

From da44fe3fc91ad643ec3892cc01a68eb52ed3dc5e Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 14 Jan 2022 09:44:38 +0100
Subject: [PATCH 0776/2085] nrf5x: Fix EP OUT race conditions

When dcd_edpt_xfer() starts new transfer two separate problems were observed.
For both problems stream of OUT packets was pouring from host.

First problem was that total_len and actual_len were not atomic.
In case where incoming OUT packets are less (63) than MPS (64), actual_len and total_len
are set 63.
Then transfer complete from USBD is called that will schedule next 64 bytes transfer.
At that point incoming packet would start DMA if there is place in RAM, normally
it does not happen since actual_len == total_len.
If packets arrives and interrupt is raised after total_len is set (64) but actual_len is still 63 from
previous transfer, interrupt code sees that there is place in ram (1 byte) and transfer this 1 byte
to buffer that was already filled with previous packet.
To remedy this USB interrupt is blocked during transfer setup.

Second problem can happen when dcd_edpt_xfer setups xfer->total_len and actual_len correctly
but then context switch happens before xfer->data_received is checked.
If during this time two packets arrive one will be copied to RAM second will stay in endpoint with
data_received set to 1.
Then when xfer_edpt_xfer() checks data_receive flag it starts DMA again overwriting data.
To remedy this, data_received is checked together with check if data was already transferred.
If transfer was complete, there is no need to start DMA yet.
In such case data_received will be handled in same place by next xfer_edpt_xfer() correctly.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index ed597a34f..db3b06ee4 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -453,9 +453,11 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 
   xfer_td_t* xfer = get_td(epnum, dir);
 
+  dcd_int_disable(rhport);
   xfer->buffer     = buffer;
   xfer->total_len  = total_bytes;
   xfer->actual_len = 0;
+  dcd_int_enable(rhport);
 
   // Control endpoint with zero-length packet and opposite direction to 1st request byte --> status stage
   bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir(NRF_USBD->BMREQUESTTYPE));
@@ -476,7 +478,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
       edpt_dma_start(&NRF_USBD->TASKS_EP0RCVOUT);
     }else
     {
-      if ( xfer->data_received )
+      if ( xfer->data_received && xfer->total_len > xfer->actual_len)
       {
         // Data is already received previously
         // start DMA to copy to SRAM

From 45fb60e883b62a550420d88426e443d0a2e7dd45 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 16 Jan 2022 12:12:57 +0700
Subject: [PATCH 0777/2085] update format correction with actual bus speed

---
 src/class/audio/audio_device.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 5ffc9b0dc..d21980060 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2252,18 +2252,23 @@ bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
   // Format the feedback value
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION && !TUD_OPT_HIGH_SPEED
-  uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].fb_val;
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION
+  if ( TUSB_SPEED_FULL == tud_speed_get() )
+  {
+    uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].fb_val;
 
-  // For FS format is 10.14
-  *(fb++) = (feedback >> 2) & 0xFF;
-  *(fb++) = (feedback >> 10) & 0xFF;
-  *(fb++) = (feedback >> 18) & 0xFF;
-  // 4th byte is needed to work correctly with MS Windows
-  *fb = 0;
+    // For FS format is 10.14
+    *(fb++) = (feedback >> 2) & 0xFF;
+    *(fb++) = (feedback >> 10) & 0xFF;
+    *(fb++) = (feedback >> 18) & 0xFF;
+    // 4th byte is needed to work correctly with MS Windows
+    *fb = 0;
+  }else
 #else
-  // Send value as-is, caller will choose the appropriate format
-  _audiod_fct[func_id].fb_val = feedback;
+  {
+    // Send value as-is, caller will choose the appropriate format
+    _audiod_fct[func_id].fb_val = feedback;
+  }
 #endif
 
   // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value

From e635c16de089953e305e94cba8524cb6f3aeae6f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 16 Jan 2022 13:12:27 +0700
Subject: [PATCH 0778/2085] fix esp ci build with IDF version 5

---
 hw/bsp/esp32s2/boards/esp32s2.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/bsp/esp32s2/boards/esp32s2.c b/hw/bsp/esp32s2/boards/esp32s2.c
index 358c0c803..77754908e 100644
--- a/hw/bsp/esp32s2/boards/esp32s2.c
+++ b/hw/bsp/esp32s2/boards/esp32s2.c
@@ -98,7 +98,11 @@ static void configure_pins(usb_hal_context_t *usb)
         esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
       } else {
         esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
+#if ESP_IDF_VERSION_MAJOR > 4
+        if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT)) {
+#else
         if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH)) {
+#endif
           gpio_ll_input_enable(&GPIO, iopin->pin);
         }
       }

From e1e457761656a489aded7039ad173351e2e6a7c2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 16 Jan 2022 13:24:36 +0700
Subject: [PATCH 0779/2085] more ci fix

---
 hw/bsp/esp32s2/boards/esp32s2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/esp32s2/boards/esp32s2.c b/hw/bsp/esp32s2/boards/esp32s2.c
index 77754908e..de4b1e5ba 100644
--- a/hw/bsp/esp32s2/boards/esp32s2.c
+++ b/hw/bsp/esp32s2/boards/esp32s2.c
@@ -70,7 +70,7 @@ void board_init(void)
 #endif
 
   // Button
-  gpio_pad_select_gpio(BUTTON_PIN);
+  esp_rom_gpio_pad_select_gpio(BUTTON_PIN);
   gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
   gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
 

From cb57f047e762c32c94e376b9f5c172d6b5b92f5b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 16 Jan 2022 13:26:50 +0700
Subject: [PATCH 0780/2085] update for s3

---
 hw/bsp/esp32s2/boards/esp32s2.c | 5 +++--
 hw/bsp/esp32s3/boards/esp32s3.c | 9 +++++++--
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/esp32s2/boards/esp32s2.c b/hw/bsp/esp32s2/boards/esp32s2.c
index de4b1e5ba..a81181672 100644
--- a/hw/bsp/esp32s2/boards/esp32s2.c
+++ b/hw/bsp/esp32s2/boards/esp32s2.c
@@ -99,10 +99,11 @@ static void configure_pins(usb_hal_context_t *usb)
       } else {
         esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
 #if ESP_IDF_VERSION_MAJOR > 4
-        if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT)) {
+        if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT))
 #else
-        if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH)) {
+        if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH))
 #endif
+        {
           gpio_ll_input_enable(&GPIO, iopin->pin);
         }
       }
diff --git a/hw/bsp/esp32s3/boards/esp32s3.c b/hw/bsp/esp32s3/boards/esp32s3.c
index 358c0c803..a81181672 100644
--- a/hw/bsp/esp32s3/boards/esp32s3.c
+++ b/hw/bsp/esp32s3/boards/esp32s3.c
@@ -70,7 +70,7 @@ void board_init(void)
 #endif
 
   // Button
-  gpio_pad_select_gpio(BUTTON_PIN);
+  esp_rom_gpio_pad_select_gpio(BUTTON_PIN);
   gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
   gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
 
@@ -98,7 +98,12 @@ static void configure_pins(usb_hal_context_t *usb)
         esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
       } else {
         esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
-        if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH)) {
+#if ESP_IDF_VERSION_MAJOR > 4
+        if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT))
+#else
+        if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH))
+#endif
+        {
           gpio_ll_input_enable(&GPIO, iopin->pin);
         }
       }

From c722133671a632d6baf60506bd93c3c6d1ed6435 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 16 Jan 2022 15:38:23 +0700
Subject: [PATCH 0781/2085] change OPT_MCU_PIC32MZ to value of 1900

---
 src/tusb_option.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 4f16a3c1a..351eeab88 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -66,7 +66,6 @@
 #define OPT_MCU_SAML22            205 ///< MicroChip SAML22
 #define OPT_MCU_SAML21            206 ///< MicroChip SAML21
 #define OPT_MCU_SAMX7X            207 ///< MicroChip SAME70, S70, V70, V71 family
-#define OPT_MCU_PIC32MZ           220 ///< MicroChip PIC32MZ family
 
 // STM32
 #define OPT_MCU_STM32F0           300 ///< ST F0
@@ -137,6 +136,9 @@
 // Infineon
 #define OPT_MCU_XMC4000          1800 ///< Infineon XMC4000
 
+// PIC
+#define OPT_MCU_PIC32MZ          1900 ///< MicroChip PIC32MZ family
+
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
 #define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == _m)

From 1a7de71e7999d028c3a03079c5908d0943f0586d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 17 Jan 2022 12:15:54 +0700
Subject: [PATCH 0782/2085] correct link in rst

---
 README.rst | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/README.rst b/README.rst
index b72436390..4946e997e 100644
--- a/README.rst
+++ b/README.rst
@@ -74,7 +74,7 @@ Supports multiple device configurations by dynamically changing USB descriptors,
 -  Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file.
 -  `WebUSB <https://github.com/WICG/webusb>`__ with vendor-specific class
 
-If you have a special requirement, `usbd_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. Here is how the RPi team added their reset interface [raspberrypi/pico-sdk#197](https://github.com/raspberrypi/pico-sdk/pull/197)
+If you have a special requirement, `usbd_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. Here is how the RPi team added their reset interface `raspberrypi/pico-sdk#197 <https://github.com/raspberrypi/pico-sdk/pull/197>`_
 
 Host Stack
 ==========
@@ -90,8 +90,8 @@ TinyUSB is completely thread-safe by pushing all Interrupt Service Request (ISR)
 
 - **No OS**
 - **FreeRTOS**
-- **RT-Thread** (https://github.com/RT-Thread/rt-thread)
-- **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its [own repo](https://github.com/hathach/mynewt-tinyusb-example)
+- `RT-Thread <https://github.com/RT-Thread/rt-thread>`_
+- **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its `own repo <https://github.com/hathach/mynewt-tinyusb-example>`_
 
 Local Docs
 ==========

From ec01428820ae5ea35bb559adf4894c4e816b7651 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Mon, 17 Jan 2022 08:50:11 +0100
Subject: [PATCH 0783/2085] ft9xx: Fix Mynewt build

Includes were moved few lines down to restore build with Mynewt build system.
---
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 793d40f81..d46723caa 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -29,16 +29,17 @@
  * in https://brtchip.com/BRTSourceCodeLicenseAgreement
  */
 
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && \
+  (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X) 
+
 #include <stdint.h>
 #include <ft900.h>
 #include <registers/ft900_registers.h>
 
 #include "board.h"
 #include "bsp/board.h"
-#include "tusb_option.h"
-
-#if TUSB_OPT_DEVICE_ENABLED && \
-  (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X) 
 
 #define USBD_USE_STREAMS
 

From 168c7095e849e448cb7d3b755ea3b6e236f502ed Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sun, 16 Jan 2022 16:13:21 +0100
Subject: [PATCH 0784/2085] pic32mz: Fix remote_wakeup without OS

Remote wakeup requires 10ms of delay when RESUME bit
is toggled.
It was covered for OS build.
For non-OS build simple delay based on board_millis() is
used to wait required amount of time.
Without this remote wakup may not work.
---
 src/portable/microchip/pic32mz/dcd_pic32mz.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c
index 323d01a71..740e5edbb 100644
--- a/src/portable/microchip/pic32mz/dcd_pic32mz.c
+++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c
@@ -163,6 +163,10 @@ void dcd_remote_wakeup(uint8_t rhport)
   USB_REGS->POWERbits.RESUME = 1;
 #if CFG_TUSB_OS != OPT_OS_NONE
   osal_task_delay(10);
+#else
+  // TODO: Wait in non blocking mode
+  unsigned cnt = 2000;
+  while (cnt--) __asm__("nop");
 #endif
   USB_REGS->POWERbits.RESUME = 0;
 }

From 45d56915d157b4c38949a148391dcd10c19b50a5 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sun, 16 Jan 2022 16:16:00 +0100
Subject: [PATCH 0785/2085] pic32/olimex boards: Fix active state of button

Buttons for olimex_emz64 and olimex_hmz144 should be set
to active low in board configuration.
---
 hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c   | 4 ++--
 hw/bsp/pic32mz/boards/olimex_hmz144/olimex_hmz144.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
index 0f6dc37e2..e47ec5f31 100644
--- a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
+++ b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
@@ -63,7 +63,7 @@ void led_init(void)
   // RB8 - LED
   // ANASELB RB8 not analog
   ANSELBCLR = TU_BIT(8);
-  // TRISH RH2 input
+  // TRISH RH2 output
   TRISBCLR = TU_BIT(8);
   // Initial value 0, LED off
   LATBCLR = TU_BIT(8);
@@ -128,7 +128,7 @@ void board_led_write(bool state)
 
 uint32_t board_button_read(void)
 {
-  return (PORTB >> 12) & 1;
+  return ((PORTB >> 12) & 1) == 0;
 }
 
 int board_uart_write(void const * buf, int len)
diff --git a/hw/bsp/pic32mz/boards/olimex_hmz144/olimex_hmz144.c b/hw/bsp/pic32mz/boards/olimex_hmz144/olimex_hmz144.c
index 4ecbe75a1..93a8da5fb 100644
--- a/hw/bsp/pic32mz/boards/olimex_hmz144/olimex_hmz144.c
+++ b/hw/bsp/pic32mz/boards/olimex_hmz144/olimex_hmz144.c
@@ -60,7 +60,7 @@ void led_init(void)
 {
   // RH2 - LED
   // ANASELH no analog function on RH2
-  // TRISH RH2 input
+  // TRISH RH2 output
   TRISHCLR = TU_BIT(2);
   // Initial value 0, LED off
   LATHCLR = TU_BIT(2);
@@ -126,7 +126,7 @@ void board_led_write(bool state)
 
 uint32_t board_button_read(void)
 {
-  return (PORTB >> 12) & 1;
+  return ((PORTB >> 12) & 1) == 0;
 }
 
 int board_uart_write(void const * buf, int len)

From f4725120a42edc853aa6db87c1d21b2ffc401a92 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Tue, 11 Jan 2022 10:45:36 +0100
Subject: [PATCH 0786/2085] nrf5x: Request HFXO via OS

Mynewt (similar to Soft Device) has its own reference counting for
HFXO oscillator.
So far TinyUSB requested HFXO when VBUS was detected and stopped when
VBUS was removed.
But with Mynewt running HFXO can be stopped when other interested parties
don't require HFXO anymore. This results in very difficult to track
USB transmission errors.

This change enables Mynewt specific HFXO management in Soft Device fashion.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index ed597a34f..49e352d39 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -38,6 +38,10 @@
 #include "device/usbd.h"
 #include "device/usbd_pvt.h" // to use defer function helper
 
+#if CFG_TUSB_OS == OPT_OS_MYNEWT
+#include "mcu/mcu.h"
+#endif
+
 /*------------------------------------------------------------------*/
 /* MACRO TYPEDEF CONSTANT ENUM
  *------------------------------------------------------------------*/
@@ -891,6 +895,11 @@ static bool hfclk_running(void)
 
 static void hfclk_enable(void)
 {
+#if CFG_TUSB_OS == OPT_OS_MYNEWT
+  usb_clock_request();
+  return;
+#else
+
   // already running, nothing to do
   if ( hfclk_running() ) return;
 
@@ -904,10 +913,16 @@ static void hfclk_enable(void)
 
   nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
   nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTART);
+#endif
 }
 
 static void hfclk_disable(void)
 {
+#if CFG_TUSB_OS == OPT_OS_MYNEWT
+  usb_clock_release();
+  return;
+#else
+
 #ifdef SOFTDEVICE_PRESENT
   if ( is_sd_enabled() )
   {
@@ -917,6 +932,7 @@ static void hfclk_disable(void)
 #endif
 
   nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
+#endif
 }
 
 // Power & Clock Peripheral on nRF5x to manage USB

From 161ba73c8b01c6de637309fbfc8c6dcea58c9d06 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 19 Jan 2022 10:17:39 +0700
Subject: [PATCH 0787/2085] fix locked mutex when fifo is full

---
 src/common/tusb_fifo.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 564687e02..0d35405db 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -741,21 +741,28 @@ bool tu_fifo_write(tu_fifo_t* f, const void * data)
 {
   _ff_lock(f->mutex_wr);
 
-  uint16_t w = f->wr_idx;
+  bool ret;
+  uint16_t const w = f->wr_idx;
 
-  if ( _tu_fifo_full(f, w, f->rd_idx) && !f->overwritable ) return false;
+  if ( _tu_fifo_full(f, w, f->rd_idx) && !f->overwritable )
+  {
+    ret = false;
+  }else
+  {
+    uint16_t wRel = get_relative_pointer(f, w);
 
-  uint16_t wRel = get_relative_pointer(f, w);
+    // Write data
+    _ff_push(f, data, wRel);
 
-  // Write data
-  _ff_push(f, data, wRel);
+    // Advance pointer
+    f->wr_idx = advance_pointer(f, w, 1);
 
-  // Advance pointer
-  f->wr_idx = advance_pointer(f, w, 1);
+    ret = true;
+  }
 
   _ff_unlock(f->mutex_wr);
 
-  return true;
+  return ret;
 }
 
 /******************************************************************************/

From af9a3f646cecd8895f488a8bc3b3c39838b55296 Mon Sep 17 00:00:00 2001
From: email <{ID}+{username}@users.noreply.github.com>
Date: Wed, 19 Jan 2022 09:00:32 +0100
Subject: [PATCH 0788/2085] fix idfgh-6508: return type in tu_fifo_peek_n()

https://github.com/espressif/esp-idf/issues/8161
---
 src/common/tusb_fifo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 0d35405db..183c9c6fc 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -716,7 +716,7 @@ bool tu_fifo_peek(tu_fifo_t* f, void * p_buffer)
 uint16_t tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n)
 {
   _ff_lock(f->mutex_rd);
-  bool ret = _tu_fifo_peek_n(f, p_buffer, n, f->wr_idx, f->rd_idx, TU_FIFO_COPY_INC);
+  uint16_t ret = _tu_fifo_peek_n(f, p_buffer, n, f->wr_idx, f->rd_idx, TU_FIFO_COPY_INC);
   _ff_unlock(f->mutex_rd);
   return ret;
 }

From 980ffe3b4e41ce5e43c3e8ae13f605f7d7b50b7f Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 14 Jan 2022 09:14:49 +0100
Subject: [PATCH 0789/2085] nrf5x: Fix DMA access race condition

In multi-thread mode starting DMA in thread mode was
prone to race condition resulting in infinite loop.
It may happen on single core CPU with strict priority based
tasks scheduler where ready high prio task never yields to
ready low prio task (Mynewt).

Sequence that failed (T1 - low priority task, T2 - high priority task)
- T1 called start_dma()
- T1 set _dcd.dma_running (DMA not started yet, context switch happens)
- T2 took CPU and saw that _dcd.dma_running is set, so waits for _dcd.dma_running to be 0
- T1 never gets CPU again, DMA is not started T2 waits forever

OSAL mutex resolves problem of DMA starting from thread-context.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 6b2cd83fd..e70565a02 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -79,6 +79,9 @@ typedef struct
 
 } xfer_td_t;
 
+static osal_mutex_def_t dcd_mutex_def;
+static osal_mutex_t dcd_mutex;
+
 // Data for managing dcd
 static struct
 {
@@ -154,6 +157,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
     // Should be safe to blocking wait until previous DMA transfer complete
     uint8_t const rhport = 0;
     bool started = false;
+    osal_mutex_lock(dcd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
     while(!started)
     {
       // LDREX/STREX may be needed in form of std atomic (required C11) or
@@ -170,6 +174,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
 
       // osal_yield();
     }
+    osal_mutex_unlock(dcd_mutex);
   }
 }
 
@@ -243,6 +248,7 @@ static void xact_in_dma(uint8_t epnum)
 void dcd_init (uint8_t rhport)
 {
   TU_LOG1("dcd init\r\n");
+  dcd_mutex = osal_mutex_create(&dcd_mutex_def);
   (void) rhport;
 }
 

From 36b6ed8ff9035ad0c2e75de92e08799dc3a4b7ed Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 14 Jan 2022 09:44:38 +0100
Subject: [PATCH 0790/2085] nrf5x: Fix EP OUT race conditions in OS build

When two tasks entered dcd_edpt_xfer() it was possible that
first disabled interrupt to setup total_len and actual_len
but second task for another endpoint enabled interrupt
between total_len and actual_len resulting in race
condition with interrupt, hence mutex is added on top of interrupt being blocked.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index e70565a02..024ea0d90 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -463,11 +463,17 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 
   xfer_td_t* xfer = get_td(epnum, dir);
 
-  dcd_int_disable(rhport);
+  if (!is_in_isr()) {
+    osal_mutex_lock(dcd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+    dcd_int_disable(rhport);
+  }
   xfer->buffer     = buffer;
   xfer->total_len  = total_bytes;
   xfer->actual_len = 0;
-  dcd_int_enable(rhport);
+  if (!is_in_isr()) {
+    dcd_int_enable(rhport);
+    osal_mutex_unlock(dcd_mutex);
+  }
 
   // Control endpoint with zero-length packet and opposite direction to 1st request byte --> status stage
   bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir(NRF_USBD->BMREQUESTTYPE));

From 3b66bbf6d5a1122a67b970288713febc740dbe49 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 19 Jan 2022 19:12:21 +0700
Subject: [PATCH 0791/2085] enable ci build for RX65X host example

update comment for unit not ready 3a-00 additional sense
---
 examples/device/cdc_msc/src/msc_disk.c | 1 +
 examples/host/cdc_msc_hid/only.txt     | 3 ++-
 examples/host/hid_controller/only.txt  | 3 ++-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index 134bda392..3076192af 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -142,6 +142,7 @@ bool tud_msc_test_unit_ready_cb(uint8_t lun)
 
   // RAM disk is ready until ejected
   if (ejected) {
+    // Additional Sense 3A-00 is NOT_FOUND
     tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3a, 0x00);
     return false;
   }
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index db9a337e5..7fe4e3f5c 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -5,4 +5,5 @@ mcu:LPC40XX
 mcu:LPC43XX
 mcu:MIMXRT10XX
 mcu:RP2040
-mcu:MSP432E4
\ No newline at end of file
+mcu:MSP432E4
+mcu:RX65X
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index db9a337e5..7fe4e3f5c 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -5,4 +5,5 @@ mcu:LPC40XX
 mcu:LPC43XX
 mcu:MIMXRT10XX
 mcu:RP2040
-mcu:MSP432E4
\ No newline at end of file
+mcu:MSP432E4
+mcu:RX65X

From d069ea1421eace1768157e76c44164262ed9a1e6 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Wed, 25 Aug 2021 10:41:07 +0200
Subject: [PATCH 0792/2085] vendor: Add tx callback

Other drivers already have notification about data sent.
It allows batter control in application on vendor
protocol level.
---
 src/class/vendor/vendor_device.c | 1 +
 src/class/vendor/vendor_device.h | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 8a4ca1d2e..02a4220be 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -247,6 +247,7 @@ bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
   }
   else if ( ep_addr == p_itf->ep_in )
   {
+    if (tud_vendor_tx_cb) tud_vendor_tx_cb(itf, xferred_bytes);
     // Send complete, try to send more if possible
     maybe_transmit(p_itf);
   }
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index d71c2a3e9..75cb77f5b 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -71,6 +71,8 @@ static inline uint32_t tud_vendor_write_available (void);
 
 // Invoked when received new data
 TU_ATTR_WEAK void tud_vendor_rx_cb(uint8_t itf);
+// Invoked when last rx transfer finished
+TU_ATTR_WEAK void tud_vendor_tx_cb(uint8_t itf, uint32_t sent_bytes);
 
 //--------------------------------------------------------------------+
 // Inline Functions

From 4ca22156845162b69410a47a2b43e03ac552b9f3 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Wed, 25 Aug 2021 10:57:35 +0200
Subject: [PATCH 0793/2085] vendor: Add tx flush functionality

So far tud_vendor_n_write() always flushed data.
It requires to have whole vendor packed constructed
before in one buffer.

With this change data do get flushed when endpoint size
is filled on write, when there is no enough data to
fill endpoint data is not sent and subsequent calls to
write functions can add more bytes.

Vendor code needs to call tud_vendor_n_flush() when packet is
ready to be sent.
---
 src/class/vendor/vendor_device.c | 16 +++++++++++++---
 src/class/vendor/vendor_device.h |  7 +++++++
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 02a4220be..586822f39 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -113,7 +113,7 @@ void tud_vendor_n_read_flush (uint8_t itf)
 //--------------------------------------------------------------------+
 // Write API
 //--------------------------------------------------------------------+
-static bool maybe_transmit(vendord_interface_t* p_itf)
+static uint16_t maybe_transmit(vendord_interface_t* p_itf)
 {
   // skip if previous transfer not complete
   TU_VERIFY( !usbd_edpt_busy(TUD_OPT_RHPORT, p_itf->ep_in) );
@@ -123,14 +123,24 @@ static bool maybe_transmit(vendord_interface_t* p_itf)
   {
     TU_ASSERT( usbd_edpt_xfer(TUD_OPT_RHPORT, p_itf->ep_in, p_itf->epin_buf, count) );
   }
-  return true;
+  return count;
 }
 
 uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize)
 {
   vendord_interface_t* p_itf = &_vendord_itf[itf];
   uint16_t ret = tu_fifo_write_n(&p_itf->tx_ff, buffer, bufsize);
-  maybe_transmit(p_itf);
+  if (tu_fifo_count(&p_itf->tx_ff) >= CFG_TUD_VENDOR_EPSIZE) {
+    maybe_transmit(p_itf);
+  }
+  return ret;
+}
+
+uint32_t tud_vendor_n_flush (uint8_t itf)
+{
+  vendord_interface_t* p_itf = &_vendord_itf[itf];
+  uint32_t ret = maybe_transmit(p_itf);
+
   return ret;
 }
 
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index 75cb77f5b..4a873e5fc 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -52,6 +52,7 @@ uint32_t tud_vendor_n_write_available (uint8_t itf);
 
 static inline
 uint32_t tud_vendor_n_write_str       (uint8_t itf, char const* str);
+uint32_t tud_vendor_n_flush           (uint8_t itf);
 
 //--------------------------------------------------------------------+
 // Application API (Single Port)
@@ -64,6 +65,7 @@ static inline void     tud_vendor_read_flush      (void);
 static inline uint32_t tud_vendor_write           (void const* buffer, uint32_t bufsize);
 static inline uint32_t tud_vendor_write_str       (char const* str);
 static inline uint32_t tud_vendor_write_available (void);
+static inline uint32_t tud_vendor_flush           (void);
 
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
@@ -123,6 +125,11 @@ static inline uint32_t tud_vendor_write_available (void)
   return tud_vendor_n_write_available(0);
 }
 
+static inline uint32_t tud_vendor_flush (void)
+{
+  return tud_vendor_n_flush(0);
+}
+
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+

From ae4d901d8351437c499cecef349b84af4bb6c239 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 20 Jan 2022 09:55:25 +0100
Subject: [PATCH 0794/2085] dcd_da1469x: Fix over-run/under-run mask

Bit mask enabling/disabling over-run/unde-run was shifted
by one nibble, so interrupt was never enabled.
It did not force any issue as this situation could only
happen on ISO endpoints without DMA.
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 311119747..5713f5cca 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -935,13 +935,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     if (dir == TUSB_DIR_OUT)
     {
       regs->epc_out = epnum | USB_USB_EPC1_REG_USB_EP_EN_Msk | iso_mask;
-      USB->USB_RXMSK_REG |= 0x101 << (epnum - 1);
+      USB->USB_RXMSK_REG |= 0x11 << (epnum - 1);
       REG_SET_BIT(USB_MAMSK_REG, USB_M_RX_EV);
     }
     else
     {
       regs->epc_in = epnum | USB_USB_EPC1_REG_USB_EP_EN_Msk | iso_mask;
-      USB->USB_TXMSK_REG |= 0x101 << (epnum - 1);
+      USB->USB_TXMSK_REG |= 0x11 << (epnum - 1);
       REG_SET_BIT(USB_MAMSK_REG, USB_M_TX_EV);
     }
   }
@@ -982,7 +982,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
     {
       regs->rxc = USB_USB_RXC1_REG_USB_FLUSH_Msk;
       regs->epc_out = 0;
-      USB->USB_RXMSK_REG &= ~(0x101 << (epnum - 1));
+      USB->USB_RXMSK_REG &= ~(0x11 << (epnum - 1));
       // Release DMA if needed
       if (_dcd.dma_ep[TUSB_DIR_OUT] == epnum)
       {
@@ -994,7 +994,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
     {
       regs->txc = USB_USB_TXC1_REG_USB_FLUSH_Msk;
       regs->epc_in = 0;
-      USB->USB_TXMSK_REG &= ~(0x101 << (epnum - 1));
+      USB->USB_TXMSK_REG &= ~(0x11 << (epnum - 1));
       // Release DMA if needed
       if (_dcd.dma_ep[TUSB_DIR_IN] == epnum)
       {

From 7b078367e82fae8ef4ec094f6db9e584db82f06a Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 20 Jan 2022 09:58:40 +0100
Subject: [PATCH 0795/2085] dcd_da1469x: Re-enable RX after resume

Going to suspend states disable reception on non-0 RX endpoints.

Now when USB resume condition is detected, all RX endpoints
with pending transfers are resumed.
---
 src/portable/dialog/da146xx/dcd_da146xx.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 5713f5cca..02fad8165 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -733,6 +733,15 @@ static void handle_alt_ev(void)
       set_nfsr(NFSR_NODE_OPERATIONAL);
       USB->USB_ALTMSK_REG = USB_USB_ALTMSK_REG_USB_M_RESET_Msk |
                             USB_USB_ALTMSK_REG_USB_M_SD3_Msk;
+      // Re-enable reception of endpoint with pending transfer
+      for (int epnum = 1; epnum <= 3; ++epnum)
+      {
+        xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+        if (xfer->total_len > xfer->transferred)
+        {
+          start_rx_packet(xfer);
+        }
+      }
       dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
     }
   }

From a80f23711eefb8d59f76bc70183705d7c368de64 Mon Sep 17 00:00:00 2001
From: Iain Sharp <sharpie7@users.noreply.github.com>
Date: Mon, 24 Jan 2022 20:56:13 +0000
Subject: [PATCH 0796/2085] Some platforms require SDKs and use of cmake

---
 docs/reference/getting_started.rst | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index 875372c81..7f2c03faa 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -52,6 +52,8 @@ Some TinyUSB examples also requires external submodule libraries in ``/lib`` suc
 
 In addition, MCU driver submodule is also needed to provide low-level MCU peripheral's driver. Luckily, it will be fetched if needed when you run the ``make`` to build your board.
 
+Some modules will also require a module-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples.
+
 Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``/examples/device/99-tinyusb.rules`` file to /etc/udev/rules.d/ then run ``sudo udevadm control --reload-rules && sudo udevadm trigger`` is good enough.
 
 Build
@@ -63,6 +65,8 @@ To build example, first change directory to an example folder.
 
    $ cd examples/device/cdc_msc
 
+Some modules (e.g. RP2040 and ESP32s2) require the project makefiles to be customized using CMake. If necessary apply any setup steps for the platform's SDK.
+
 Then compile with ``make BOARD=[board_name] all``\ , for example
 
 .. code-block::

From 578a12328290592aa315f13339cbbd7d31a6bafd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Jan 2022 12:59:53 +0700
Subject: [PATCH 0797/2085] fix mynewt build sunxi

---
 src/portable/sunxi/dcd_sunxi_musb.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 89464c5b2..cf93c9bc4 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -28,6 +28,9 @@
 
 #include <stdint.h>
 #include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_F1C100S
+
 #include "osal/osal.h"
 #include <f1c100s-irq.h>
 #include <device/dcd.h>
@@ -38,7 +41,6 @@ typedef uint32_t u32;
 typedef uint16_t u16;
 typedef uint8_t u8;
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_F1C100S
 
 #define REQUEST_TYPE_INVALID  (0xFFu)
 

From 6085999e2be6974bfb59475213331ba21a7b5872 Mon Sep 17 00:00:00 2001
From: "Man, Jianting (Meco)" <920369182@qq.com>
Date: Wed, 26 Jan 2022 20:08:34 -0500
Subject: [PATCH 0798/2085] add rt-thread's tinyusb repo address

---
 README.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index f21cd9bca..8cf4a98da 100644
--- a/README.rst
+++ b/README.rst
@@ -91,7 +91,7 @@ TinyUSB is completely thread-safe by pushing all Interrupt Service Request (ISR)
 
 - **No OS**
 - **FreeRTOS**
-- `RT-Thread <https://github.com/RT-Thread/rt-thread>`_
+- `RT-Thread <https://github.com/RT-Thread/rt-thread>`_: `repo <https://github.com/RT-Thread-packages/tinyusb>`_
 - **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its `own repo <https://github.com/hathach/mynewt-tinyusb-example>`_
 
 Local Docs

From a4bc6075cef1685ecc896730e704400b35e2392a Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 21 Nov 2021 16:17:50 +0900
Subject: [PATCH 0799/2085] Add HCD functions for KL25Z

---
 hw/bsp/frdm_kl25z/frdm_kl25z.c   |   5 +
 src/portable/nxp/khci/hcd_khci.c | 475 +++++++++++++++++++++++++++++++
 2 files changed, 480 insertions(+)
 create mode 100644 src/portable/nxp/khci/hcd_khci.c

diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c
index 72982ed8a..2930ed56e 100644
--- a/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c
@@ -39,7 +39,12 @@
 //--------------------------------------------------------------------+
 void USB0_IRQHandler(void)
 {
+#if TUSB_OPT_HOST_ENABLED
+  tuh_int_handler(0);
+#endif
+#if TUSB_OPT_DEVICE_ENABLED
   tud_int_handler(0);
+#endif
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
new file mode 100644
index 000000000..877c4813b
--- /dev/null
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -0,0 +1,475 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_HOST_ENABLED && ( \
+      ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \
+    )
+
+#include "fsl_device_registers.h"
+#define KHCI        USB0
+
+#include "host/hcd.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+enum {
+  TOK_PID_OUT   = 0x1u,
+  TOK_PID_IN    = 0x9u,
+  TOK_PID_SETUP = 0xDu,
+  TOK_PID_DATA0 = 0x3u,
+  TOK_PID_DATA1 = 0xbu,
+  TOK_PID_ACK   = 0x2u,
+  TOK_PID_STALL = 0xeu,
+  TOK_PID_NAK   = 0xau,
+  TOK_PID_BUSTO = 0x0u,
+  TOK_PID_ERR   = 0xfu,
+};
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t head;
+    struct {
+      union {
+        struct {
+               uint16_t           :  2;
+          __IO uint16_t tok_pid   :  4;
+               uint16_t data      :  1;
+          __IO uint16_t own       :  1;
+               uint16_t           :  8;
+        };
+        struct {
+               uint16_t           :  2;
+               uint16_t bdt_stall :  1;
+               uint16_t dts       :  1;
+               uint16_t ninc      :  1;
+               uint16_t keep      :  1;
+               uint16_t           : 10;
+        };
+      };
+      __IO uint16_t bc : 10;
+           uint16_t    :  6;
+    };
+  };
+  uint8_t *addr;
+}buffer_descriptor_t;
+
+TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t state;
+    struct {
+      uint32_t max_packet_size :11;
+      uint32_t                 : 5;
+      uint32_t odd             : 1;
+      uint32_t                 :15;
+    };
+  };
+  uint16_t length;
+  uint16_t remaining;
+} endpoint_state_t;
+
+TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
+
+typedef struct TU_ATTR_PACKED
+{
+  uint8_t  dev_addr;
+  uint8_t  ep_addr;
+  uint16_t max_packet_size;
+  union {
+    uint8_t flags;
+    struct {
+      uint8_t data : 1;
+      uint8_t xfer : 2;
+      uint8_t      : 0;
+    };
+  };
+} pipe_state_t;
+
+
+typedef struct
+{
+  union {
+    /* [#EP][OUT,IN][EVEN,ODD] */
+    buffer_descriptor_t bdt[16][2][2];
+    uint16_t            bda[512];
+  };
+  endpoint_state_t endpoint[2];
+  pipe_state_t pipe[HCD_MAX_XFER];
+} hcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+// BDT(Buffer Descriptor Table) must be 256-byte aligned
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd;
+
+TU_VERIFY_STATIC( sizeof(_hcd.bdt) == 512, "size is not correct" );
+
+static pipe_state_t *find_pipe(uint8_t dev_addr, uint8_t ep_addr)
+{
+  /* Find the target pipe */
+  pipe_state_t *p   = _hcd.pipe;
+  pipe_state_t *end = p + HCD_MAX_XFER;
+  for (;p != end; ++p) {
+    if ((p->dev_addr == dev_addr) && (p->ep_addr != ep_addr))
+      return p;
+  }
+  return NULL;
+}
+
+static int prepare_packets(uint8_t rhport, uint_fast8_t dir_in, uint8_t* buffer, uint_fast16_t total_bytes)
+{
+  (void)rhport;
+  const unsigned dir_tx   = dir_in ? 0 : 1;
+  endpoint_state_t    *ep = &_hcd.endpoint[dir_tx];
+  buffer_descriptor_t *bd = &_hcd.bdt[0][dir_tx][ep->odd];
+  TU_ASSERT(0 == bd->own, 0);
+
+  ep->length    = total_bytes;
+  ep->remaining = total_bytes;
+
+  int num_pkts = 0; /* The number of prepared packets */
+  const unsigned mps = ep->max_packet_size;
+  if (total_bytes > mps) {
+    buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
+    /* When total_bytes is greater than the max packet size,
+     * it prepares to the next transfer to avoid NAK in advance. */
+    next->bc   = total_bytes >= 2 * mps ? mps: total_bytes - mps;
+    next->addr = buffer + mps;
+    next->own  = 1;
+    ++num_pkts;
+  }
+  bd->bc   = total_bytes >= mps ? mps: total_bytes;
+  bd->addr = buffer;
+  __DSB();
+  bd->own  = 1; /* This bit must be set last */
+  ++num_pkts;
+  return num_pkts;
+}
+
+static void process_tokdne(uint8_t rhport)
+{
+  (void)rhport;
+  const unsigned s = KHCI->STAT;
+  KHCI->ISTAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
+
+  uint8_t const epnum  = (s >> USB_STAT_ENDP_SHIFT);
+  TU_ASSERT(0 == epnum,);
+  uint8_t const dir_in = (s & USB_STAT_TX_MASK) ? TUSB_DIR_OUT: TUSB_DIR_IN;
+  unsigned const odd   = (s & USB_STAT_ODD_MASK) ? 1 : 0;
+
+  buffer_descriptor_t *bd = (buffer_descriptor_t *)&_hcd.bda[s];
+  endpoint_state_t    *ep = &_hcd.endpoint[s >> 3];
+
+  /* fetch status before discarded by the next steps */
+  const unsigned pid = bd->tok_pid;
+
+  /* reset values for a next transfer */
+  bd->bdt_stall = 0;
+  bd->dts       = 1;
+  bd->ninc      = 0;
+  bd->keep      = 0;
+  /* Update the odd variable to prepare for the next transfer */
+  ep->odd       = odd ^ 1;
+
+  const unsigned bc = bd->bc;
+  const unsigned remaining = ep->remaining - bc;
+  if ((TOK_PID_DATA0 == pid) || (TOK_PID_DATA1 == pid) || (TOK_PID_ACK == pid)) {
+    /* Go on the next packet transfer */
+    if (remaining && bc == ep->max_packet_size) {
+      ep->remaining = remaining;
+      const int next_remaining = remaining - ep->max_packet_size;
+      if (next_remaining > 0) {
+        /* Prepare to the after next transfer */
+        bd->addr += ep->max_packet_size * 2;
+        bd->bc    = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
+        __DSB();
+        bd->own   = 1; /* This bit must be set last */
+        while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
+        KHCI->TOKEN = KHCI->TOKEN; /* Queue the same token as the last */
+      }
+      return;
+    }
+  }
+  const unsigned length = ep->length;
+  xfer_result_t result;
+  switch (pid) {
+    default:
+      result = XFER_RESULT_SUCCESS;
+      break;
+    case TOK_PID_STALL:
+      result = XFER_RESULT_STALLED;
+      break;
+    case TOK_PID_NAK:
+    case TOK_PID_ERR:
+    case TOK_PID_BUSTO:
+      result = XFER_RESULT_FAILED;
+      break;
+  }
+  hcd_event_xfer_complete(KHCI->ADDR & USB_ADDR_ADDR_MASK,
+                          tu_edpt_addr(KHCI->TOKEN & USB_TOKEN_TOKENENDPT_MASK, dir_in),
+                          length - remaining, result, true);
+}
+
+static void process_attach(uint8_t rhport)
+{
+  unsigned ctl = KHCI->CTL;
+  if (!(ctl & USB_CTL_JSTATE_MASK)) {
+    /* The attached device is a low speed device. */
+    KHCI->ADDR = USB_ADDR_LSEN_MASK;
+    KHCI->ENDPOINT[0].ENDPT = USB_ENDPT_HOSTWOHUB_MASK;
+  }
+  hcd_event_device_attach(rhport, true);
+}
+
+/*------------------------------------------------------------------*/
+/* Host API
+ *------------------------------------------------------------------*/
+bool hcd_init(uint8_t rhport)
+{
+  (void)rhport;
+
+  KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
+  while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
+
+  tu_memclr(&_hcd, sizeof(_hcd));
+  KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
+  KHCI->BDTPAGE1 = (uint8_t)((uintptr_t)_hcd.bdt >>  8);
+  KHCI->BDTPAGE2 = (uint8_t)((uintptr_t)_hcd.bdt >> 16);
+  KHCI->BDTPAGE3 = (uint8_t)((uintptr_t)_hcd.bdt >> 24);
+
+  KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
+  KHCI->CTL     |= USB_CTL_ODDRST_MASK;
+  for (unsigned i = 0; i < 16; ++i) {
+    KHCI->ENDPOINT[i].ENDPT = 0;
+  }
+  const endpoint_state_t ep0 = {
+    .max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
+    .odd             = 0,
+    .length          = 0,
+    .remaining       = 0,
+  };
+  _hcd.endpoint[0] = ep0;
+  _hcd.endpoint[1] = ep0;
+  KHCI->CTL &= ~USB_CTL_ODDRST_MASK;
+
+  KHCI->SOFTHLD = 74; /* for 64-byte packets */
+  KHCI->CTL     = USB_CTL_HOSTMODEEN_MASK | USB_CTL_SE0_MASK;
+  KHCI->USBCTRL = USB_USBCTRL_PDE_MASK;
+
+  NVIC_ClearPendingIRQ(USB0_IRQn);
+  KHCI->INTEN = USB_INTEN_ATTACHEN_MASK;
+  return true;
+}
+
+void hcd_int_enable(uint8_t rhport)
+{
+  (void)rhport;
+  NVIC_EnableIRQ(USB0_IRQn);
+}
+
+void hcd_int_disable(uint8_t rhport)
+{
+  (void)rhport;
+  NVIC_DisableIRQ(USB0_IRQn);
+}
+
+uint32_t hcd_frame_number(uint8_t rhport)
+{
+  (void)rhport;
+  uint32_t frmnum = KHCI->FRMNUML;
+  frmnum |= KHCI->FRMNUMH << 8u;
+  return frmnum;
+}
+
+/*--------------------------------------------------------------------+
+ * Port API
+ *--------------------------------------------------------------------+ */
+bool hcd_port_connect_status(uint8_t rhport)
+{
+  (void)rhport;
+  return false;
+}
+
+void hcd_port_reset(uint8_t rhport)
+{
+  (void)rhport;
+  KHCI->CTL &= ~USB_CTL_USBENSOFEN_MASK;
+  KHCI->CTL |= USB_CTL_RESET_MASK;
+  unsigned cnt = SystemCoreClock / 100;
+  while (cnt--) __NOP();
+  KHCI->CTL &= ~USB_CTL_RESET_MASK;
+  KHCI->CTL |= USB_CTL_USBENSOFEN_MASK;
+}
+
+tusb_speed_t hcd_port_speed_get(uint8_t rhport)
+{
+  (void)rhport;
+  tusb_speed_t speed = TUSB_SPEED_FULL;
+  const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  if (KHCI->ADDR & USB_ADDR_LSEN_MASK)
+    speed = TUSB_SPEED_LOW;
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  return speed;
+}
+
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
+{
+  (void)rhport;
+  pipe_state_t *p   = _hcd.pipe;
+  pipe_state_t *end = p + HCD_MAX_XFER;
+  for (;p != end; ++p) {
+    if (p->dev_addr == dev_addr)
+      tu_memclr(p, sizeof(*p));
+  }
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
+{
+  (void)rhport;
+  const unsigned rx_odd = _hcd.endpoint[0].odd;
+  const unsigned tx_odd = _hcd.endpoint[1].odd;
+  TU_ASSERT(0 == _hcd.bdt[0][0][tx_odd].own);
+
+  const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+
+  _hcd.bdt[0][0][rx_odd    ].data = 1;
+  _hcd.bdt[0][0][rx_odd ^ 1].data = 0;
+  _hcd.bdt[0][1][tx_odd    ].data = 0;
+  _hcd.bdt[0][1][tx_odd ^ 1].data = 1;
+
+  unsigned hostwohub = KHCI->ENDPOINT[0].ENDPT & USB_ENDPT_HOSTWOHUB_MASK;
+  KHCI->ENDPOINT[0].ENDPT = hostwohub |
+    USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
+  bool ret = false;
+  if (prepare_packets(rhport, TUSB_DIR_OUT, (void*)(uintptr_t)setup_packet, 8)) {
+    KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | dev_addr;
+    while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
+    KHCI->TOKEN = (TOK_PID_SETUP << USB_TOKEN_TOKENPID_SHIFT);
+    ret = true;
+  }
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  return ret;
+}
+
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void)rhport;
+  /* Find a free pipe */
+  pipe_state_t *p   = _hcd.pipe;
+  pipe_state_t *end = p + HCD_MAX_XFER;
+  for (;p < end && p->dev_addr; ++p) ;
+  if (p == end) return false;
+  p->dev_addr        = dev_addr;
+  p->ep_addr         = ep_desc->bEndpointAddress;
+  p->max_packet_size = ep_desc->wMaxPacketSize;
+  p->xfer            = ep_desc->bmAttributes.xfer;
+  p->data            = 0;
+  return true;
+}
+
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
+{
+  (void)rhport;
+  const unsigned dir_in   = tu_edpt_dir(ep_addr);
+  const unsigned odd      = _hcd.endpoint[dir_in ^ 1].odd;
+  buffer_descriptor_t *bd = _hcd.bdt[0][dir_in ^ 1];
+  TU_ASSERT(0 == bd[odd].own);
+
+  unsigned flags = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
+  if (tu_edpt_number(ep_addr)) {
+    pipe_state_t *p = find_pipe(dev_addr, ep_addr);
+    if (!p) return false;
+    bd[odd    ].data = p->data;
+    bd[odd ^ 1].data = p->data ^ 1;
+    bd[odd ^ 1].own  = 0;
+    flags |= USB_ENDPT_EPCTLDIS_MASK;
+    /* Disable retry for a interrupt transfer.  */
+    if (TUSB_XFER_INTERRUPT == p->xfer)
+      flags |= USB_ENDPT_RETRYDIS_MASK;
+  }
+  unsigned hostwohub = KHCI->ENDPOINT[0].ENDPT & USB_ENDPT_HOSTWOHUB_MASK;
+  KHCI->ENDPOINT[0].ENDPT = hostwohub | flags;
+  int num_pkts = prepare_packets(rhport, dir_in, buffer, buflen);
+  if (!num_pkts) return false;
+  KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | dev_addr;
+  const unsigned token = tu_edpt_number(ep_addr) |
+    ((dir_in ? TOK_PID_IN: TOK_PID_OUT) << USB_TOKEN_TOKENPID_SHIFT);
+  const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  do {
+    while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
+    KHCI->TOKEN = token;
+  } while (--num_pkts);
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  return true;
+}
+
+bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
+{
+  if (!tu_edpt_number(ep_addr)) return true;
+  pipe_state_t *p = find_pipe(dev_addr, ep_addr);
+  if (!p) return false;
+  p->data = 0; /* Reset data toggle */
+  return true;
+}
+
+/*--------------------------------------------------------------------+
+ * ISR
+ *--------------------------------------------------------------------+*/
+void hcd_int_handler(uint8_t rhport)
+{
+  uint32_t is  = KHCI->ISTAT;
+  uint32_t msk = KHCI->INTEN;
+
+  /* clear disabled interrupts */
+  KHCI->ISTAT = is & ~msk;
+  is &= msk;
+
+  if (is & USB_ISTAT_ATTACH_MASK) {
+    process_attach(rhport);
+  }
+  if (is & USB_ISTAT_STALL_MASK) {
+    KHCI->ISTAT = USB_ISTAT_STALL_MASK;
+  }
+  if (is & USB_ISTAT_TOKDNE_MASK) {
+    process_tokdne(rhport);
+  }
+}
+
+#endif

From cdab869472e18d393d43769c8a087ff1e69deb02 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 29 Dec 2021 21:45:32 +0900
Subject: [PATCH 0800/2085] Fix handling control transfer

---
 src/portable/nxp/khci/hcd_khci.c | 135 ++++++++++++++++++++-----------
 1 file changed, 90 insertions(+), 45 deletions(-)

diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 877c4813b..937d69f9b 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -88,10 +88,9 @@ typedef struct TU_ATTR_PACKED
   union {
     uint32_t state;
     struct {
-      uint32_t max_packet_size :11;
-      uint32_t                 : 5;
-      uint32_t odd             : 1;
-      uint32_t                 :15;
+      uint32_t pipenum:16;
+      uint32_t odd    : 1;
+      uint32_t        : 0;
     };
   };
   uint16_t length;
@@ -125,6 +124,7 @@ typedef struct
   };
   endpoint_state_t endpoint[2];
   pipe_state_t pipe[HCD_MAX_XFER];
+  bool         need_reset;     /* The device has not been reset after connection. */
 } hcd_data_t;
 
 //--------------------------------------------------------------------+
@@ -135,31 +135,34 @@ CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd;
 
 TU_VERIFY_STATIC( sizeof(_hcd.bdt) == 512, "size is not correct" );
 
-static pipe_state_t *find_pipe(uint8_t dev_addr, uint8_t ep_addr)
+int find_pipe(uint8_t dev_addr, uint8_t ep_addr)
 {
   /* Find the target pipe */
-  pipe_state_t *p   = _hcd.pipe;
-  pipe_state_t *end = p + HCD_MAX_XFER;
-  for (;p != end; ++p) {
-    if ((p->dev_addr == dev_addr) && (p->ep_addr != ep_addr))
-      return p;
+  int num;
+  if (0 == tu_edpt_number(ep_addr)) ep_addr = 0;
+  for (num = 0; num < HCD_MAX_XFER; ++num) {
+    pipe_state_t *p = &_hcd.pipe[num];
+    if ((p->dev_addr == dev_addr) && (p->ep_addr == ep_addr))
+      return num;
   }
-  return NULL;
+  return -1;
 }
 
-static int prepare_packets(uint8_t rhport, uint_fast8_t dir_in, uint8_t* buffer, uint_fast16_t total_bytes)
+static int prepare_packets(int pipenum,
+                           uint_fast8_t dir_in, uint8_t* buffer,
+                           uint_fast16_t total_bytes)
 {
-  (void)rhport;
   const unsigned dir_tx   = dir_in ? 0 : 1;
   endpoint_state_t    *ep = &_hcd.endpoint[dir_tx];
   buffer_descriptor_t *bd = &_hcd.bdt[0][dir_tx][ep->odd];
   TU_ASSERT(0 == bd->own, 0);
 
+  ep->pipenum   = pipenum;
   ep->length    = total_bytes;
   ep->remaining = total_bytes;
 
   int num_pkts = 0; /* The number of prepared packets */
-  const unsigned mps = ep->max_packet_size;
+  const unsigned mps = _hcd.pipe[pipenum].max_packet_size;
   if (total_bytes > mps) {
     buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
     /* When total_bytes is greater than the max packet size,
@@ -174,6 +177,7 @@ static int prepare_packets(uint8_t rhport, uint_fast8_t dir_in, uint8_t* buffer,
   __DSB();
   bd->own  = 1; /* This bit must be set last */
   ++num_pkts;
+  // TU_LOG1("BD pipe=%d %d %lx %x\n", pipenum, num_pkts, bd->head, (uintptr_t)bd->addr);
   return num_pkts;
 }
 
@@ -182,12 +186,13 @@ static void process_tokdne(uint8_t rhport)
   (void)rhport;
   const unsigned s = KHCI->STAT;
   KHCI->ISTAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
-
   uint8_t const epnum  = (s >> USB_STAT_ENDP_SHIFT);
   TU_ASSERT(0 == epnum,);
   uint8_t const dir_in = (s & USB_STAT_TX_MASK) ? TUSB_DIR_OUT: TUSB_DIR_IN;
   unsigned const odd   = (s & USB_STAT_ODD_MASK) ? 1 : 0;
 
+  // TU_LOG1("TOKDNE %x\n", s);
+
   buffer_descriptor_t *bd = (buffer_descriptor_t *)&_hcd.bda[s];
   endpoint_state_t    *ep = &_hcd.endpoint[s >> 3];
 
@@ -204,19 +209,24 @@ static void process_tokdne(uint8_t rhport)
 
   const unsigned bc = bd->bc;
   const unsigned remaining = ep->remaining - bc;
+  pipe_state_t *pipe = &_hcd.pipe[ep->pipenum];
+
+  // TU_LOG1("  pid %x bc %x remaining %d\n", pid, bc, remaining);
   if ((TOK_PID_DATA0 == pid) || (TOK_PID_DATA1 == pid) || (TOK_PID_ACK == pid)) {
     /* Go on the next packet transfer */
-    if (remaining && bc == ep->max_packet_size) {
+    if (remaining && bc == pipe->max_packet_size) {
       ep->remaining = remaining;
-      const int next_remaining = remaining - ep->max_packet_size;
+      const int next_remaining = remaining - pipe->max_packet_size;
       if (next_remaining > 0) {
         /* Prepare to the after next transfer */
-        bd->addr += ep->max_packet_size * 2;
-        bd->bc    = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
+        bd->addr += pipe->max_packet_size * 2;
+        bd->bc    = next_remaining > pipe->max_packet_size ? pipe->max_packet_size: next_remaining;
         __DSB();
         bd->own   = 1; /* This bit must be set last */
         while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
         KHCI->TOKEN = KHCI->TOKEN; /* Queue the same token as the last */
+      } else if (dir_in) {
+        KHCI->TOKEN = KHCI->TOKEN;
       }
       return;
     }
@@ -236,7 +246,7 @@ static void process_tokdne(uint8_t rhport)
       result = XFER_RESULT_FAILED;
       break;
   }
-  hcd_event_xfer_complete(KHCI->ADDR & USB_ADDR_ADDR_MASK,
+  hcd_event_xfer_complete(pipe->dev_addr,
                           tu_edpt_addr(KHCI->TOKEN & USB_TOKEN_TOKENENDPT_MASK, dir_in),
                           length - remaining, result, true);
 }
@@ -252,6 +262,21 @@ static void process_attach(uint8_t rhport)
   hcd_event_device_attach(rhport, true);
 }
 
+static void process_bus_reset(uint8_t rhport)
+{
+  KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
+  KHCI->CTL     &= ~USB_CTL_USBENSOFEN_MASK;
+  KHCI->ADDR     = 0;
+  KHCI->ENDPOINT[0].ENDPT = 0;
+
+  hcd_event_device_remove(rhport, true);
+
+  buffer_descriptor_t *bd = _hcd.bdt[0][0];
+  for (unsigned i = 0; i < 2; ++i, ++bd) {
+    bd->head = 0;
+  }
+}
+
 /*------------------------------------------------------------------*/
 /* Host API
  *------------------------------------------------------------------*/
@@ -273,14 +298,6 @@ bool hcd_init(uint8_t rhport)
   for (unsigned i = 0; i < 16; ++i) {
     KHCI->ENDPOINT[i].ENDPT = 0;
   }
-  const endpoint_state_t ep0 = {
-    .max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
-    .odd             = 0,
-    .length          = 0,
-    .remaining       = 0,
-  };
-  _hcd.endpoint[0] = ep0;
-  _hcd.endpoint[1] = ep0;
   KHCI->CTL &= ~USB_CTL_ODDRST_MASK;
 
   KHCI->SOFTHLD = 74; /* for 64-byte packets */
@@ -288,7 +305,8 @@ bool hcd_init(uint8_t rhport)
   KHCI->USBCTRL = USB_USBCTRL_PDE_MASK;
 
   NVIC_ClearPendingIRQ(USB0_IRQn);
-  KHCI->INTEN = USB_INTEN_ATTACHEN_MASK;
+  KHCI->INTEN = USB_INTEN_ATTACHEN_MASK | USB_INTEN_TOKDNEEN_MASK |
+    USB_INTEN_USBRSTEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
   return true;
 }
 
@@ -307,9 +325,12 @@ void hcd_int_disable(uint8_t rhport)
 uint32_t hcd_frame_number(uint8_t rhport)
 {
   (void)rhport;
+  /* The device must be reset at least once after connection 
+   * in order to start the frame counter. */
+  if (_hcd.need_reset) hcd_port_reset(rhport);
   uint32_t frmnum = KHCI->FRMNUML;
   frmnum |= KHCI->FRMNUMH << 8u;
-  return frmnum;
+   return frmnum;
 }
 
 /*--------------------------------------------------------------------+
@@ -318,6 +339,8 @@ uint32_t hcd_frame_number(uint8_t rhport)
 bool hcd_port_connect_status(uint8_t rhport)
 {
   (void)rhport;
+  if (KHCI->ISTAT & USB_ISTAT_ATTACH_MASK)
+    return true;
   return false;
 }
 
@@ -330,6 +353,7 @@ void hcd_port_reset(uint8_t rhport)
   while (cnt--) __NOP();
   KHCI->CTL &= ~USB_CTL_RESET_MASK;
   KHCI->CTL |= USB_CTL_USBENSOFEN_MASK;
+  _hcd.need_reset = false;
 }
 
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
@@ -347,8 +371,8 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 {
   (void)rhport;
-  pipe_state_t *p   = _hcd.pipe;
-  pipe_state_t *end = p + HCD_MAX_XFER;
+  pipe_state_t *p   = &_hcd.pipe[0];
+  pipe_state_t *end = &_hcd.pipe[HCD_MAX_XFER];
   for (;p != end; ++p) {
     if (p->dev_addr == dev_addr)
       tu_memclr(p, sizeof(*p));
@@ -361,10 +385,14 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void)rhport;
+  // TU_LOG1("SETUP %u\n", dev_addr);
   const unsigned rx_odd = _hcd.endpoint[0].odd;
   const unsigned tx_odd = _hcd.endpoint[1].odd;
   TU_ASSERT(0 == _hcd.bdt[0][0][tx_odd].own);
 
+  int num = find_pipe(dev_addr, 0);
+  if (num < 0) return false;
+
   const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
 
@@ -377,26 +405,31 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   KHCI->ENDPOINT[0].ENDPT = hostwohub |
     USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
   bool ret = false;
-  if (prepare_packets(rhport, TUSB_DIR_OUT, (void*)(uintptr_t)setup_packet, 8)) {
+  if (prepare_packets(num, TUSB_DIR_OUT, (void*)(uintptr_t)setup_packet, 8)) {
     KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | dev_addr;
     while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
     KHCI->TOKEN = (TOK_PID_SETUP << USB_TOKEN_TOKENPID_SHIFT);
     ret = true;
   }
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
+
   return ret;
 }
 
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
   (void)rhport;
+  uint8_t const ep_addr = ep_desc->bEndpointAddress;
+  // TU_LOG1("O %u %x\n", dev_addr, ep_addr);
   /* Find a free pipe */
-  pipe_state_t *p   = _hcd.pipe;
-  pipe_state_t *end = p + HCD_MAX_XFER;
-  for (;p < end && p->dev_addr; ++p) ;
-  if (p == end) return false;
+  pipe_state_t *p = &_hcd.pipe[0];
+  if (dev_addr || ep_addr) {
+    pipe_state_t *end = &_hcd.pipe[HCD_MAX_XFER];
+    for (++p; p < end && (p->dev_addr || p->ep_addr); ++p) ;
+    if (p == end) return false;
+  }
   p->dev_addr        = dev_addr;
-  p->ep_addr         = ep_desc->bEndpointAddress;
+  p->ep_addr         = ep_addr;
   p->max_packet_size = ep_desc->wMaxPacketSize;
   p->xfer            = ep_desc->bmAttributes.xfer;
   p->data            = 0;
@@ -406,15 +439,18 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
   (void)rhport;
+  // TU_LOG1("X %u %x %d\n", dev_addr, ep_addr, buflen);
   const unsigned dir_in   = tu_edpt_dir(ep_addr);
   const unsigned odd      = _hcd.endpoint[dir_in ^ 1].odd;
   buffer_descriptor_t *bd = _hcd.bdt[0][dir_in ^ 1];
   TU_ASSERT(0 == bd[odd].own);
 
+  int num = find_pipe(dev_addr, ep_addr);
+  if (num < 0) return false;
+
   unsigned flags = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
   if (tu_edpt_number(ep_addr)) {
-    pipe_state_t *p = find_pipe(dev_addr, ep_addr);
-    if (!p) return false;
+    pipe_state_t *p  = &_hcd.pipe[num];
     bd[odd    ].data = p->data;
     bd[odd ^ 1].data = p->data ^ 1;
     bd[odd ^ 1].own  = 0;
@@ -425,7 +461,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   }
   unsigned hostwohub = KHCI->ENDPOINT[0].ENDPT & USB_ENDPT_HOSTWOHUB_MASK;
   KHCI->ENDPOINT[0].ENDPT = hostwohub | flags;
-  int num_pkts = prepare_packets(rhport, dir_in, buffer, buflen);
+  int num_pkts = prepare_packets(num, dir_in, buffer, buflen);
   if (!num_pkts) return false;
   KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | dev_addr;
   const unsigned token = tu_edpt_number(ep_addr) |
@@ -435,7 +471,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   do {
     while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
     KHCI->TOKEN = token;
-  } while (--num_pkts);
+  } while (--num_pkts && !dir_in);
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
   return true;
 }
@@ -443,8 +479,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
   if (!tu_edpt_number(ep_addr)) return true;
-  pipe_state_t *p = find_pipe(dev_addr, ep_addr);
-  if (!p) return false;
+  int num = find_pipe(dev_addr, ep_addr);
+  if (num < 0) return false;
+  pipe_state_t *p = &_hcd.pipe[num];
   p->data = 0; /* Reset data toggle */
   return true;
 }
@@ -457,13 +494,21 @@ void hcd_int_handler(uint8_t rhport)
   uint32_t is  = KHCI->ISTAT;
   uint32_t msk = KHCI->INTEN;
 
+  // TU_LOG1("S %lx\n", is);
+
   /* clear disabled interrupts */
-  KHCI->ISTAT = is & ~msk;
+  KHCI->ISTAT = is & ~msk & ~USB_ISTAT_TOKDNE_MASK;
   is &= msk;
 
   if (is & USB_ISTAT_ATTACH_MASK) {
+    KHCI->INTEN = (msk & ~USB_INTEN_ATTACHEN_MASK) | USB_INTEN_USBRSTEN_MASK;
+    _hcd.need_reset = true;
     process_attach(rhport);
   }
+  if (is & USB_ISTAT_USBRST_MASK) {
+    KHCI->INTEN = (msk & ~USB_INTEN_USBRSTEN_MASK) | USB_INTEN_ATTACHEN_MASK;
+    process_bus_reset(rhport);
+  }
   if (is & USB_ISTAT_STALL_MASK) {
     KHCI->ISTAT = USB_ISTAT_STALL_MASK;
   }

From cc06a3585e9f499bd2412f4f88e5d785e8e1a23f Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 10 Jan 2022 23:50:32 +0900
Subject: [PATCH 0801/2085] Add handling for NAK response

---
 src/portable/nxp/khci/hcd_khci.c | 357 ++++++++++++++++++++-----------
 1 file changed, 230 insertions(+), 127 deletions(-)

diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 937d69f9b..ddc6e9992 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -93,12 +93,11 @@ typedef struct TU_ATTR_PACKED
       uint32_t        : 0;
     };
   };
+  uint8_t *buffer;
   uint16_t length;
   uint16_t remaining;
 } endpoint_state_t;
 
-TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
-
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  dev_addr;
@@ -112,19 +111,24 @@ typedef struct TU_ATTR_PACKED
       uint8_t      : 0;
     };
   };
+  uint8_t *buffer;
+  uint16_t length;
+  uint16_t remaining;
 } pipe_state_t;
 
 
 typedef struct
 {
   union {
-    /* [#EP][OUT,IN][EVEN,ODD] */
-    buffer_descriptor_t bdt[16][2][2];
-    uint16_t            bda[512];
+    /* [OUT,IN][EVEN,ODD] */
+    buffer_descriptor_t bdt[2][2];
+    uint16_t            bda[2*2];
   };
   endpoint_state_t endpoint[2];
-  pipe_state_t pipe[HCD_MAX_XFER];
-  bool         need_reset;     /* The device has not been reset after connection. */
+  pipe_state_t pipe[HCD_MAX_XFER * 2];
+  uint32_t     in_progress; /* Bitmap. Each bit indicates that a transfer of the corresponding pipe is in progress */
+  uint32_t     pending;     /* Bitmap. Each bit indicates that a transfer of the corresponding pipe will be resume the next frame */
+  bool         need_reset;  /* The device has not been reset after connection. */
 } hcd_data_t;
 
 //--------------------------------------------------------------------+
@@ -132,15 +136,13 @@ typedef struct
 //--------------------------------------------------------------------+
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd;
-
-TU_VERIFY_STATIC( sizeof(_hcd.bdt) == 512, "size is not correct" );
+//CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _rx_buf[1024];
 
 int find_pipe(uint8_t dev_addr, uint8_t ep_addr)
 {
   /* Find the target pipe */
   int num;
-  if (0 == tu_edpt_number(ep_addr)) ep_addr = 0;
-  for (num = 0; num < HCD_MAX_XFER; ++num) {
+  for (num = 0; num < HCD_MAX_XFER * 2; ++num) {
     pipe_state_t *p = &_hcd.pipe[num];
     if ((p->dev_addr == dev_addr) && (p->ep_addr == ep_addr))
       return num;
@@ -148,37 +150,129 @@ int find_pipe(uint8_t dev_addr, uint8_t ep_addr)
   return -1;
 }
 
-static int prepare_packets(int pipenum,
-                           uint_fast8_t dir_in, uint8_t* buffer,
-                           uint_fast16_t total_bytes)
+static int prepare_packets(int pipenum)
 {
-  const unsigned dir_tx   = dir_in ? 0 : 1;
-  endpoint_state_t    *ep = &_hcd.endpoint[dir_tx];
-  buffer_descriptor_t *bd = &_hcd.bdt[0][dir_tx][ep->odd];
-  TU_ASSERT(0 == bd->own, 0);
+  pipe_state_t *pipe      = &_hcd.pipe[pipenum];
+  unsigned const dir_tx   = tu_edpt_dir(pipe->ep_addr) ? 0 : 1;
+  endpoint_state_t *ep    = &_hcd.endpoint[dir_tx];
+  unsigned const odd      = ep->odd;
+  buffer_descriptor_t *bd = _hcd.bdt[dir_tx];
+  TU_ASSERT(0 == bd[odd].own, -1);
 
-  ep->pipenum   = pipenum;
-  ep->length    = total_bytes;
-  ep->remaining = total_bytes;
+  // TU_LOG1("  %p dir %d odd %d data %d\n", &bd[odd], dir_tx, odd, pipe->data);
 
-  int num_pkts = 0; /* The number of prepared packets */
-  const unsigned mps = _hcd.pipe[pipenum].max_packet_size;
-  if (total_bytes > mps) {
-    buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
+  ep->pipenum = pipenum;
+
+  bd[odd    ].data      = pipe->data;
+  bd[odd ^ 1].data      = pipe->data ^ 1;
+  bd[odd ^ 1].own       = 0;
+  /* reset values for a next transfer */
+
+  int num_tokens = 0; /* The number of prepared packets */
+  unsigned const mps = pipe->max_packet_size;
+  unsigned const rem = pipe->remaining;
+  if (rem > mps) {
     /* When total_bytes is greater than the max packet size,
      * it prepares to the next transfer to avoid NAK in advance. */
-    next->bc   = total_bytes >= 2 * mps ? mps: total_bytes - mps;
-    next->addr = buffer + mps;
-    next->own  = 1;
-    ++num_pkts;
+    bd[odd ^ 1].bc   = rem >= 2 * mps ? mps: rem - mps;
+    bd[odd ^ 1].addr = pipe->buffer + mps;
+    bd[odd ^ 1].own  = 1;
+    if (dir_tx) ++num_tokens;
   }
-  bd->bc   = total_bytes >= mps ? mps: total_bytes;
-  bd->addr = buffer;
+  bd[odd].bc   = rem >= mps ? mps: rem;
+  bd[odd].addr = pipe->buffer;
   __DSB();
-  bd->own  = 1; /* This bit must be set last */
-  ++num_pkts;
-  // TU_LOG1("BD pipe=%d %d %lx %x\n", pipenum, num_pkts, bd->head, (uintptr_t)bd->addr);
-  return num_pkts;
+  bd[odd].own  = 1; /* This bit must be set last */
+  ++num_tokens;
+  return num_tokens;
+}
+
+static int select_next_pipenum(int pipenum)
+{
+  unsigned wip  = _hcd.in_progress & ~_hcd.pending;
+  if (!wip) return -1;
+  unsigned msk  = TU_GENMASK(31, pipenum);
+  int      next = __builtin_ctz(wip & msk);
+  if (next) return next;
+  msk  = TU_GENMASK(pipenum, 0);
+  next = __builtin_ctz(wip & msk);
+  return next;
+}
+
+/* When transfer is completed, return true. */
+static bool continue_transfer(int pipenum, buffer_descriptor_t *bd)
+{
+  pipe_state_t *pipe = &_hcd.pipe[pipenum];
+  unsigned const bc  = bd->bc;
+  unsigned const rem = pipe->remaining - bc;
+
+  pipe->remaining = rem;
+  if (rem && bc == pipe->max_packet_size) {
+    int const next_rem = rem - pipe->max_packet_size;
+    if (next_rem > 0) {
+      /* Prepare to the after next transfer */
+      bd->addr += pipe->max_packet_size * 2;
+      bd->bc    = next_rem > pipe->max_packet_size ? pipe->max_packet_size: next_rem;
+      __DSB();
+      bd->own   = 1; /* This bit must be set last */
+      while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
+      KHCI->TOKEN = KHCI->TOKEN; /* Queue the same token as the last */
+    } else if (TUSB_DIR_IN == tu_edpt_dir(pipe->ep_addr)) { /* IN */
+      while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
+      KHCI->TOKEN = KHCI->TOKEN;
+    }
+    return true;
+  }
+  pipe->data = bd->data ^ 1;
+  return false;
+}
+
+static bool resume_transfer(int pipenum)
+{
+  int num_tokens = prepare_packets(pipenum);
+  TU_ASSERT(0 <= num_tokens);
+
+  const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
+  pipe_state_t *pipe = &_hcd.pipe[pipenum];
+
+  unsigned flags = KHCI->ENDPOINT[0].ENDPT & USB_ENDPT_HOSTWOHUB_MASK;
+  flags |= USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
+  switch (pipe->xfer) {
+  case TUSB_XFER_CONTROL:
+    flags |= USB_ENDPT_EPHSHK_MASK;
+    break;
+  case TUSB_XFER_ISOCHRONOUS:
+    flags |= USB_ENDPT_EPCTLDIS_MASK | USB_ENDPT_RETRYDIS_MASK;
+    break;
+  default:
+    flags |= USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPCTLDIS_MASK | USB_ENDPT_RETRYDIS_MASK;
+    break;
+  }
+  // TU_LOG1("  resume pipenum %d flags %x\n", pipenum, flags);
+
+  KHCI->ENDPOINT[0].ENDPT = flags;
+  KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | pipe->dev_addr;
+
+  unsigned const token = tu_edpt_number(pipe->ep_addr) |
+    ((tu_edpt_dir(pipe->ep_addr) ? TOK_PID_IN: TOK_PID_OUT) << USB_TOKEN_TOKENPID_SHIFT);
+  do {
+    while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
+    KHCI->TOKEN = token;
+  } while (--num_tokens);
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
+  return true;
+}
+
+static void suspend_transfer(int pipenum, buffer_descriptor_t *bd)
+{
+  pipe_state_t *pipe = &_hcd.pipe[pipenum];
+  pipe->buffer  = bd->addr;
+  pipe->data    = bd->data;
+  if (TUSB_XFER_INTERRUPT == pipe->xfer) {
+    _hcd.pending |= TU_BIT(pipenum);
+    KHCI->INTEN |= USB_ISTAT_SOFTOK_MASK;
+  }
 }
 
 static void process_tokdne(uint8_t rhport)
@@ -186,13 +280,9 @@ static void process_tokdne(uint8_t rhport)
   (void)rhport;
   const unsigned s = KHCI->STAT;
   KHCI->ISTAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
-  uint8_t const epnum  = (s >> USB_STAT_ENDP_SHIFT);
-  TU_ASSERT(0 == epnum,);
   uint8_t const dir_in = (s & USB_STAT_TX_MASK) ? TUSB_DIR_OUT: TUSB_DIR_IN;
   unsigned const odd   = (s & USB_STAT_ODD_MASK) ? 1 : 0;
 
-  // TU_LOG1("TOKDNE %x\n", s);
-
   buffer_descriptor_t *bd = (buffer_descriptor_t *)&_hcd.bda[s];
   endpoint_state_t    *ep = &_hcd.endpoint[s >> 3];
 
@@ -207,48 +297,40 @@ static void process_tokdne(uint8_t rhport)
   /* Update the odd variable to prepare for the next transfer */
   ep->odd       = odd ^ 1;
 
-  const unsigned bc = bd->bc;
-  const unsigned remaining = ep->remaining - bc;
-  pipe_state_t *pipe = &_hcd.pipe[ep->pipenum];
+  int pipenum = ep->pipenum;
+  int next_pipenum;
+  // TU_LOG1("TOKDNE %x PID %x pipe %d\n", s, pid, pipenum);
 
-  // TU_LOG1("  pid %x bc %x remaining %d\n", pid, bc, remaining);
-  if ((TOK_PID_DATA0 == pid) || (TOK_PID_DATA1 == pid) || (TOK_PID_ACK == pid)) {
-    /* Go on the next packet transfer */
-    if (remaining && bc == pipe->max_packet_size) {
-      ep->remaining = remaining;
-      const int next_remaining = remaining - pipe->max_packet_size;
-      if (next_remaining > 0) {
-        /* Prepare to the after next transfer */
-        bd->addr += pipe->max_packet_size * 2;
-        bd->bc    = next_remaining > pipe->max_packet_size ? pipe->max_packet_size: next_remaining;
-        __DSB();
-        bd->own   = 1; /* This bit must be set last */
-        while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
-        KHCI->TOKEN = KHCI->TOKEN; /* Queue the same token as the last */
-      } else if (dir_in) {
-        KHCI->TOKEN = KHCI->TOKEN;
-      }
-      return;
-    }
-  }
-  const unsigned length = ep->length;
   xfer_result_t result;
   switch (pid) {
     default:
+      if (continue_transfer(pipenum, bd))
+        return;
       result = XFER_RESULT_SUCCESS;
       break;
-    case TOK_PID_STALL:
-      result = XFER_RESULT_STALLED;
-      break;
     case TOK_PID_NAK:
     case TOK_PID_ERR:
+      suspend_transfer(pipenum, bd);
+      next_pipenum = select_next_pipenum(pipenum);
+      if (0 <= next_pipenum)
+        resume_transfer(next_pipenum);
+      return;
+    case TOK_PID_STALL:
+      result = XFER_RESULT_STALLED;
+      break;
     case TOK_PID_BUSTO:
       result = XFER_RESULT_FAILED;
       break;
   }
+  _hcd.in_progress  &= ~TU_BIT(pipenum);
+  pipe_state_t *pipe = &_hcd.pipe[ep->pipenum];
   hcd_event_xfer_complete(pipe->dev_addr,
                           tu_edpt_addr(KHCI->TOKEN & USB_TOKEN_TOKENENDPT_MASK, dir_in),
-                          length - remaining, result, true);
+                          pipe->length - pipe->remaining,
+                          result, true);
+  next_pipenum = select_next_pipenum(pipenum);
+  if (0 <= next_pipenum)
+    resume_transfer(next_pipenum);
 }
 
 static void process_attach(uint8_t rhport)
@@ -264,6 +346,7 @@ static void process_attach(uint8_t rhport)
 
 static void process_bus_reset(uint8_t rhport)
 {
+  KHCI->ISTAT    = USB_ISTAT_TOKDNE_MASK;
   KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
   KHCI->CTL     &= ~USB_CTL_USBENSOFEN_MASK;
   KHCI->ADDR     = 0;
@@ -271,7 +354,9 @@ static void process_bus_reset(uint8_t rhport)
 
   hcd_event_device_remove(rhport, true);
 
-  buffer_descriptor_t *bd = _hcd.bdt[0][0];
+  _hcd.in_progress = 0;
+  _hcd.pending     = 0;
+  buffer_descriptor_t *bd = &_hcd.bdt[0][0];
   for (unsigned i = 0; i < 2; ++i, ++bd) {
     bd->head = 0;
   }
@@ -301,12 +386,15 @@ bool hcd_init(uint8_t rhport)
   KHCI->CTL &= ~USB_CTL_ODDRST_MASK;
 
   KHCI->SOFTHLD = 74; /* for 64-byte packets */
+  // KHCI->SOFTHLD = 144; /* for low speed 8-byte packets */
   KHCI->CTL     = USB_CTL_HOSTMODEEN_MASK | USB_CTL_SE0_MASK;
   KHCI->USBCTRL = USB_USBCTRL_PDE_MASK;
 
   NVIC_ClearPendingIRQ(USB0_IRQn);
   KHCI->INTEN = USB_INTEN_ATTACHEN_MASK | USB_INTEN_TOKDNEEN_MASK |
     USB_INTEN_USBRSTEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
+  KHCI->ERREN = 0xff;
+
   return true;
 }
 
@@ -371,12 +459,15 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 {
   (void)rhport;
+  const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  NVIC_DisableIRQ(USB0_IRQn);
   pipe_state_t *p   = &_hcd.pipe[0];
-  pipe_state_t *end = &_hcd.pipe[HCD_MAX_XFER];
+  pipe_state_t *end = &_hcd.pipe[HCD_MAX_XFER * 2];
   for (;p != end; ++p) {
     if (p->dev_addr == dev_addr)
       tu_memclr(p, sizeof(*p));
   }
+  if (ie) NVIC_EnableIRQ(USB0_IRQn);
 }
 
 //--------------------------------------------------------------------+
@@ -386,34 +477,30 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 {
   (void)rhport;
   // TU_LOG1("SETUP %u\n", dev_addr);
-  const unsigned rx_odd = _hcd.endpoint[0].odd;
-  const unsigned tx_odd = _hcd.endpoint[1].odd;
-  TU_ASSERT(0 == _hcd.bdt[0][0][tx_odd].own);
+  TU_ASSERT(0 == (_hcd.in_progress & TU_BIT(0)));
 
-  int num = find_pipe(dev_addr, 0);
-  if (num < 0) return false;
+  int pipenum = find_pipe(dev_addr, 0);
+  if (pipenum < 0) return false;
 
-  const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
-  NVIC_DisableIRQ(USB0_IRQn);
+  pipe_state_t *pipe = &_hcd.pipe[pipenum];
+  pipe[0].data       = 0;
+  pipe[0].buffer     = (uint8_t*)(uintptr_t)setup_packet;
+  pipe[0].length     = 8;
+  pipe[0].remaining  = 8;
+  pipe[1].data       = 1;
 
-  _hcd.bdt[0][0][rx_odd    ].data = 1;
-  _hcd.bdt[0][0][rx_odd ^ 1].data = 0;
-  _hcd.bdt[0][1][tx_odd    ].data = 0;
-  _hcd.bdt[0][1][tx_odd ^ 1].data = 1;
+  if (1 != prepare_packets(pipenum))
+    return false;
+
+  _hcd.in_progress |= TU_BIT(pipenum);
 
   unsigned hostwohub = KHCI->ENDPOINT[0].ENDPT & USB_ENDPT_HOSTWOHUB_MASK;
   KHCI->ENDPOINT[0].ENDPT = hostwohub |
     USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
-  bool ret = false;
-  if (prepare_packets(num, TUSB_DIR_OUT, (void*)(uintptr_t)setup_packet, 8)) {
-    KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | dev_addr;
-    while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
-    KHCI->TOKEN = (TOK_PID_SETUP << USB_TOKEN_TOKENPID_SHIFT);
-    ret = true;
-  }
-  if (ie) NVIC_EnableIRQ(USB0_IRQn);
-
-  return ret;
+  KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | dev_addr;
+  while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
+  KHCI->TOKEN = (TOK_PID_SETUP << USB_TOKEN_TOKENPID_SHIFT);
+  return true;
 }
 
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
@@ -423,9 +510,10 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   // TU_LOG1("O %u %x\n", dev_addr, ep_addr);
   /* Find a free pipe */
   pipe_state_t *p = &_hcd.pipe[0];
+  pipe_state_t *end = &_hcd.pipe[HCD_MAX_XFER * 2];
   if (dev_addr || ep_addr) {
-    pipe_state_t *end = &_hcd.pipe[HCD_MAX_XFER];
-    for (++p; p < end && (p->dev_addr || p->ep_addr); ++p) ;
+    p += 2;
+    for (; p < end && (p->dev_addr || p->ep_addr); ++p) ;
     if (p == end) return false;
   }
   p->dev_addr        = dev_addr;
@@ -433,45 +521,39 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   p->max_packet_size = ep_desc->wMaxPacketSize;
   p->xfer            = ep_desc->bmAttributes.xfer;
   p->data            = 0;
+  if (!ep_addr) {
+    /* Open one more pipe for Control IN transfer */
+    TU_ASSERT(TUSB_XFER_CONTROL == p->xfer);
+    pipe_state_t *q = p + 1;
+    TU_ASSERT(!q->dev_addr && !q->ep_addr);
+    q->dev_addr        = dev_addr;
+    q->ep_addr         = tu_edpt_addr(0, TUSB_DIR_IN);
+    q->max_packet_size = ep_desc->wMaxPacketSize;
+    q->xfer            = ep_desc->bmAttributes.xfer;
+    q->data            = 1;
+  }
   return true;
 }
 
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
   (void)rhport;
-  // TU_LOG1("X %u %x %d\n", dev_addr, ep_addr, buflen);
-  const unsigned dir_in   = tu_edpt_dir(ep_addr);
-  const unsigned odd      = _hcd.endpoint[dir_in ^ 1].odd;
-  buffer_descriptor_t *bd = _hcd.bdt[0][dir_in ^ 1];
-  TU_ASSERT(0 == bd[odd].own);
+  // TU_LOG1("X %u %x %x %d\n", dev_addr, ep_addr, (uintptr_t)buffer, buflen);
 
-  int num = find_pipe(dev_addr, ep_addr);
-  if (num < 0) return false;
+  int pipenum = find_pipe(dev_addr, ep_addr);
+  TU_ASSERT(0 <= pipenum);
 
-  unsigned flags = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
-  if (tu_edpt_number(ep_addr)) {
-    pipe_state_t *p  = &_hcd.pipe[num];
-    bd[odd    ].data = p->data;
-    bd[odd ^ 1].data = p->data ^ 1;
-    bd[odd ^ 1].own  = 0;
-    flags |= USB_ENDPT_EPCTLDIS_MASK;
-    /* Disable retry for a interrupt transfer.  */
-    if (TUSB_XFER_INTERRUPT == p->xfer)
-      flags |= USB_ENDPT_RETRYDIS_MASK;
-  }
-  unsigned hostwohub = KHCI->ENDPOINT[0].ENDPT & USB_ENDPT_HOSTWOHUB_MASK;
-  KHCI->ENDPOINT[0].ENDPT = hostwohub | flags;
-  int num_pkts = prepare_packets(num, dir_in, buffer, buflen);
-  if (!num_pkts) return false;
-  KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | dev_addr;
-  const unsigned token = tu_edpt_number(ep_addr) |
-    ((dir_in ? TOK_PID_IN: TOK_PID_OUT) << USB_TOKEN_TOKENPID_SHIFT);
-  const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
+  TU_ASSERT(0 == (_hcd.in_progress & TU_BIT(pipenum)));
+  unsigned const ie  = NVIC_GetEnableIRQ(USB0_IRQn);
+  unsigned const wip = _hcd.in_progress;
   NVIC_DisableIRQ(USB0_IRQn);
-  do {
-    while (KHCI->CTL & USB_CTL_TXSUSPENDTOKENBUSY_MASK) ;
-    KHCI->TOKEN = token;
-  } while (--num_pkts && !dir_in);
+  pipe_state_t *pipe = &_hcd.pipe[pipenum];
+  pipe->buffer       = buffer;
+  pipe->length       = buflen;
+  pipe->remaining    = buflen;
+  _hcd.in_progress   = wip | TU_BIT(pipenum);
+  if (0 == (wip & ~_hcd.pending))
+    resume_transfer(pipenum);
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
   return true;
 }
@@ -497,21 +579,42 @@ void hcd_int_handler(uint8_t rhport)
   // TU_LOG1("S %lx\n", is);
 
   /* clear disabled interrupts */
-  KHCI->ISTAT = is & ~msk & ~USB_ISTAT_TOKDNE_MASK;
+  KHCI->ISTAT = (is & ~msk & ~USB_ISTAT_TOKDNE_MASK) | USB_ISTAT_SOFTOK_MASK;
   is &= msk;
 
+  if (is & USB_ISTAT_ERROR_MASK) {
+    unsigned err = KHCI->ERRSTAT;
+    if (err) {
+      TU_LOG1(" ERR %x\n", err);
+      KHCI->ERRSTAT = err;
+    } else {
+      KHCI->INTEN &= ~USB_ISTAT_ERROR_MASK;
+    }
+  }
+
+  if (is & USB_ISTAT_USBRST_MASK) {
+    KHCI->INTEN = (msk & ~USB_INTEN_USBRSTEN_MASK) | USB_INTEN_ATTACHEN_MASK;
+    process_bus_reset(rhport);
+    return;
+  }
   if (is & USB_ISTAT_ATTACH_MASK) {
     KHCI->INTEN = (msk & ~USB_INTEN_ATTACHEN_MASK) | USB_INTEN_USBRSTEN_MASK;
     _hcd.need_reset = true;
     process_attach(rhport);
-  }
-  if (is & USB_ISTAT_USBRST_MASK) {
-    KHCI->INTEN = (msk & ~USB_INTEN_USBRSTEN_MASK) | USB_INTEN_ATTACHEN_MASK;
-    process_bus_reset(rhport);
+    return;
   }
   if (is & USB_ISTAT_STALL_MASK) {
     KHCI->ISTAT = USB_ISTAT_STALL_MASK;
   }
+  if (is & USB_ISTAT_SOFTOK_MASK) {
+    msk &= ~USB_ISTAT_SOFTOK_MASK;
+    KHCI->INTEN = msk;
+    if (_hcd.pending) {
+      int pipenum = __builtin_ctz(_hcd.pending);
+      _hcd.pending = 0;
+      resume_transfer(pipenum);
+    }
+  }
   if (is & USB_ISTAT_TOKDNE_MASK) {
     process_tokdne(rhport);
   }

From 60a0be82da93b653d55b9a62b0d80cd58f47a869 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 27 Jan 2022 22:25:36 +0900
Subject: [PATCH 0802/2085] Change hcd_edpt_xfer to send at the next SOF

---
 src/portable/nxp/khci/hcd_khci.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index ddc6e9992..133d65a66 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -268,7 +268,7 @@ static void suspend_transfer(int pipenum, buffer_descriptor_t *bd)
 {
   pipe_state_t *pipe = &_hcd.pipe[pipenum];
   pipe->buffer  = bd->addr;
-  pipe->data    = bd->data;
+  pipe->data    = bd->data ^ 1;
   if (TUSB_XFER_INTERRUPT == pipe->xfer) {
     _hcd.pending |= TU_BIT(pipenum);
     KHCI->INTEN |= USB_ISTAT_SOFTOK_MASK;
@@ -309,7 +309,6 @@ static void process_tokdne(uint8_t rhport)
       result = XFER_RESULT_SUCCESS;
       break;
     case TOK_PID_NAK:
-    case TOK_PID_ERR:
       suspend_transfer(pipenum, bd);
       next_pipenum = select_next_pipenum(pipenum);
       if (0 <= next_pipenum)
@@ -318,6 +317,7 @@ static void process_tokdne(uint8_t rhport)
     case TOK_PID_STALL:
       result = XFER_RESULT_STALLED;
       break;
+    case TOK_PID_ERR: /* mismatch toggle bit */
     case TOK_PID_BUSTO:
       result = XFER_RESULT_FAILED;
       break;
@@ -535,6 +535,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   return true;
 }
 
+/* The address of buffer must be aligned to 4 byte boundary. And it must be at least 4 bytes long.
+ * DMA writes data in 4 byte unit */
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
   (void)rhport;
@@ -545,15 +547,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
   TU_ASSERT(0 == (_hcd.in_progress & TU_BIT(pipenum)));
   unsigned const ie  = NVIC_GetEnableIRQ(USB0_IRQn);
-  unsigned const wip = _hcd.in_progress;
   NVIC_DisableIRQ(USB0_IRQn);
   pipe_state_t *pipe = &_hcd.pipe[pipenum];
   pipe->buffer       = buffer;
   pipe->length       = buflen;
   pipe->remaining    = buflen;
-  _hcd.in_progress   = wip | TU_BIT(pipenum);
-  if (0 == (wip & ~_hcd.pending))
-    resume_transfer(pipenum);
+  _hcd.in_progress  |= TU_BIT(pipenum);
+  _hcd.pending      |= TU_BIT(pipenum); /* Send at the next Frame */
+  KHCI->INTEN |= USB_ISTAT_SOFTOK_MASK;
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
   return true;
 }

From d7cbfaaa0a83570c5094ae84262ee9ce83856aae Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 27 Jan 2022 22:26:51 +0900
Subject: [PATCH 0803/2085] Add hcd into source list

---
 hw/bsp/frdm_kl25z/board.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
index 15bd50eda..3585b8b03 100644
--- a/hw/bsp/frdm_kl25z/board.mk
+++ b/hw/bsp/frdm_kl25z/board.mk
@@ -23,6 +23,7 @@ LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld
 
 SRC_C += \
 	src/portable/nxp/khci/dcd_khci.c \
+	src/portable/nxp/khci/hcd_khci.c \
 	$(MCU_DIR)/system_MKL25Z4.c \
 	$(MCU_DIR)/project_template/clock_config.c \
 	$(MCU_DIR)/drivers/fsl_clock.c \

From 03d2e32dc15adf9ee28772dfaecc52fac940f0d9 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 27 Jan 2022 23:38:19 +0900
Subject: [PATCH 0804/2085] Fix handling for pending transfers

---
 src/portable/nxp/khci/hcd_khci.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 133d65a66..92ec04d4a 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -269,7 +269,8 @@ static void suspend_transfer(int pipenum, buffer_descriptor_t *bd)
   pipe_state_t *pipe = &_hcd.pipe[pipenum];
   pipe->buffer  = bd->addr;
   pipe->data    = bd->data ^ 1;
-  if (TUSB_XFER_INTERRUPT == pipe->xfer) {
+  if ((TUSB_XFER_INTERRUPT == pipe->xfer) ||
+      (TUSB_XFER_BULK == pipe->xfer)) {
     _hcd.pending |= TU_BIT(pipenum);
     KHCI->INTEN |= USB_ISTAT_SOFTOK_MASK;
   }
@@ -613,7 +614,8 @@ void hcd_int_handler(uint8_t rhport)
     if (_hcd.pending) {
       int pipenum = __builtin_ctz(_hcd.pending);
       _hcd.pending = 0;
-      resume_transfer(pipenum);
+      if (!(is & USB_ISTAT_TOKDNE_MASK))
+        resume_transfer(pipenum);
     }
   }
   if (is & USB_ISTAT_TOKDNE_MASK) {

From ce7a8fed36dc61ef488f1c75a9c810681c7dcde9 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Fri, 28 Jan 2022 01:18:44 +0900
Subject: [PATCH 0805/2085] Add a partial support mark to KL25

---
 docs/reference/supported.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 445643733..7c5402d93 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -42,7 +42,7 @@ Supported MCUs
 +--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
 | NXP          | iMXRT   | RT10xx      | ✔      | ✔    | ✔         | ci_hs             |              |
 |              +---------+-------------+--------+------+-----------+-------------------+--------------+
-|              | Kinetis | KL25        | ✔      |      | ✖         |                   |              |
+|              | Kinetis | KL25        | ✔      | ⚠     | ✖         |                   |              |
 |              |         +-------------+--------+------+-----------+-------------------+--------------+
 |              |         | K32L2       | ✔      |      | ✖         |                   |              |
 |              +---------+-------------+--------+------+-----------+-------------------+--------------+

From 453ba529a6db41ad9e0e8cbfdedfcb48b059693e Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Fri, 28 Jan 2022 14:02:34 +1030
Subject: [PATCH 0806/2085] OHCI: Fix array out of bounds issue

If using a USB hub, a request outside the array size can occur

Original line:
https://github.com/hathach/tinyusb/blob/ffb257ac17f162bc5a4c26596d7a1e954db98aa5/src/portable/ohci/ohci.h#L162

It can happen in a few places but one such example is here:
https://github.com/hathach/tinyusb/blob/ffb257ac17f162bc5a4c26596d7a1e954db98aa5/src/portable/ohci/ohci.c#L460

ie. if HUB address is 5, this would be an array index out of bounds on control endpoints as `CFG_TUH_DEVICE_MAX+1` is only 5.

This fix just includes num of hubs in the reserve array size.

Fixing locally fixed this issue.
---
 src/portable/ohci/ohci.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index cd90aa45a..8db097b06 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -159,7 +159,7 @@ typedef struct TU_ATTR_ALIGNED(256)
   struct {
     ohci_ed_t ed;
     ohci_gtd_t gtd;
-  }control[CFG_TUH_DEVICE_MAX+1];
+  }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
 
   //  ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
   ohci_ed_t ed_pool[HCD_MAX_ENDPOINT];

From e1f0c484c628fd9f2b66ef517a2fda9ace75dce0 Mon Sep 17 00:00:00 2001
From: Roland <info@winformatik.ch>
Date: Tue, 1 Feb 2022 23:45:52 +0100
Subject: [PATCH 0807/2085] Modifications for CCRX toolchain

---
 src/common/tusb_compiler.h           | 6 +++++-
 src/portable/renesas/usba/dcd_usba.c | 8 ++++++--
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 38e6a16d0..8f1de7162 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -75,7 +75,11 @@
  * Nth position is the same as the number of arguments
  * - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma)
  *------------------------------------------------------------------*/
-#define TU_ARGS_NUM(...) 	 _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N())
+#if !defined(__CCRX__)
+#define TU_ARGS_NUM(...)   _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N())
+#else
+#define TU_ARGS_NUM(...)   _TU_NARG(_0, __VA_ARGS__,_RSEQ_N())
+#endif
 
 #define _TU_NARG(...)      _GET_NTH_ARG(__VA_ARGS__)
 #define _GET_NTH_ARG( \
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index ae7d2fd0c..70a9f41e6 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -494,7 +494,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
       while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
     }
   } else {
+#if defined(__CCRX__)
+    __evenaccess volatile reg_pipetre_t *pt = get_pipetre(num);
+#else
     volatile reg_pipetre_t *pt = get_pipetre(num);
+#endif
     if (pt) {
       const unsigned     mps = edpt_max_packet_size(num);
       volatile uint16_t *ctr = get_pipectr(num);
@@ -715,11 +719,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   *ctr = 0;
   unsigned cfg = (dir << 4) | epn;
   if (xfer == TUSB_XFER_BULK) {
-    cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB;
+    cfg |= (USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB);
   } else if (xfer == TUSB_XFER_INTERRUPT) {
     cfg |= USB_PIPECFG_INT;
   } else {
-    cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
+    cfg |= (USB_PIPECFG_ISO | USB_PIPECFG_DBLB);
   }
   USB0.PIPECFG.WORD  = cfg;
   USB0.BRDYSTS.WORD  = 0x1FFu ^ TU_BIT(num);

From 2df57d2be0ad5e42ab0fbdb132d1921ca190632c Mon Sep 17 00:00:00 2001
From: Jay Beavers <jay@tolttechnologies.com>
Date: Wed, 9 Feb 2022 08:19:01 -0800
Subject: [PATCH 0808/2085] Nit spelling correction

---
 hw/bsp/family_support.cmake | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index a8cc1f363..ee29caba7 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -2,7 +2,7 @@ if (NOT TARGET _family_support_marker)
     add_library(_family_support_marker INTERFACE)
 
     if (NOT FAMILY)
-        message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the camke command line")
+        message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line")
     endif()
 
     if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)

From 678c415beab60adff9ff2f125ad6b7f418bbcaaf Mon Sep 17 00:00:00 2001
From: Zenithal <i@zenithal.me>
Date: Thu, 10 Feb 2022 22:30:31 +0800
Subject: [PATCH 0809/2085] readme: fix typo

---
 README.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index 8cf4a98da..5b994c357 100644
--- a/README.rst
+++ b/README.rst
@@ -65,7 +65,7 @@ Supports multiple device configurations by dynamically changing USB descriptors,
 -  Audio Class 2.0 (UAC2)
 -  Bluetooth Host Controller Interface (BTH HCI)
 -  Communication Device Class (CDC)
--  Device Firmware Update (DFU): DFU mode (WIP) and Runtinme
+-  Device Firmware Update (DFU): DFU mode (WIP) and Runtime
 -  Human Interface Device (HID): Generic (In & Out), Keyboard, Mouse, Gamepad etc ...
 -  Mass Storage Class (MSC): with multiple LUNs
 -  Musical Instrument Digital Interface (MIDI)

From 456c06aa5ee2440cd2c96800be41e7c63c34ae58 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 14 Feb 2022 18:17:49 +0700
Subject: [PATCH 0810/2085] add tud_msc_request_sense_cb() as weak callback

set default error sense to NOT READY, Medium not present
---
 src/class/msc/msc_device.c | 59 ++++++++++++++++++++++----------------
 src/class/msc/msc_device.h |  3 ++
 2 files changed, 38 insertions(+), 24 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 97837b114..8f4fc9356 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -239,6 +239,12 @@ bool tud_msc_set_sense(uint8_t lun, uint8_t sense_key, uint8_t add_sense_code, u
   return true;
 }
 
+static inline void set_default_error_sense(uint8_t lun)
+{
+  // default sense is NOT READY, MEDIUM NOT PRESENT
+  tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3A, 0x00);
+}
+
 //--------------------------------------------------------------------+
 // USBD Driver API
 //--------------------------------------------------------------------+
@@ -406,7 +412,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         return false;
       }
 
-      TU_LOG(MSC_DEBUG, "  SCSI Command: %s\r\n", tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
+      TU_LOG(MSC_DEBUG, "  SCSI Command [Lun%u]: %s\r\n", p_cbw->lun, tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
       //TU_LOG_MEM(MSC_DEBUG, p_cbw, xferred_bytes, 2);
 
       p_csw->signature    = MSC_CSW_SIGNATURE;
@@ -473,7 +479,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           if ( resplen < 0 )
           {
             // unsupported command
-            TU_LOG(MSC_DEBUG, "  SCSI unsupported command\r\n");
+            TU_LOG(MSC_DEBUG, "  SCSI unsupported or failed command\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
           }
           else if (resplen == 0)
@@ -508,7 +514,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     break;
 
     case MSC_STAGE_DATA:
-      TU_LOG(MSC_DEBUG, "  SCSI Data\r\n");
+      TU_LOG(MSC_DEBUG, "  SCSI Data [Lun%u]\r\n", p_cbw->lun);
       //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2);
 
       if (SCSI_CMD_READ_10 == p_cbw->command[0])
@@ -569,7 +575,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       // Wait for the Status phase to complete
       if( (ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t)) )
       {
-        TU_LOG(MSC_DEBUG, "  SCSI Status = %u\r\n", p_csw->status);
+        TU_LOG(MSC_DEBUG, "  SCSI Status [Lun%u] = %u\r\n", p_cbw->lun, p_csw->status);
         // TU_LOG_MEM(MSC_DEBUG, p_csw, xferred_bytes, 2);
 
         // Invoke complete callback if defined
@@ -654,8 +660,8 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         // Failed status response
         resplen = - 1;
 
-        // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
-        if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
+        // set default sense if not set by callback
+        if ( p_msc->sense_key == 0 ) set_default_error_sense(lun);
       }
     break;
 
@@ -670,8 +676,8 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
           // Failed status response
           resplen = - 1;
 
-          // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
-          if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
+          // set default sense if not set by callback
+          if ( p_msc->sense_key == 0 ) set_default_error_sense(lun);
         }
       }
     break;
@@ -691,13 +697,13 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       {
         resplen = -1;
 
-        // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
-        if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
+        // set default sense if not set by callback
+        if ( p_msc->sense_key == 0 ) set_default_error_sense(lun);
       }else
       {
         scsi_read_capacity10_resp_t read_capa10;
 
-        read_capa10.last_lba = tu_htonl(block_count-1);
+        read_capa10.last_lba   = tu_htonl(block_count-1);
         read_capa10.block_size = tu_htonl(block_size);
 
         resplen = sizeof(read_capa10);
@@ -727,8 +733,8 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       {
         resplen = -1;
 
-        // If sense key is not set by callback, default to Logical Unit Not Ready, Cause Not Reportable
-        if ( p_msc->sense_key == 0 ) tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x04, 0x00);
+        // set default sense if not set by callback
+        if ( p_msc->sense_key == 0 ) set_default_error_sense(lun);
       }else
       {
         read_fmt_capa.block_num = tu_htonl(block_count);
@@ -765,10 +771,10 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
     {
       scsi_mode_sense6_resp_t mode_resp =
       {
-          .data_len = 3,
-          .medium_type = 0,
-          .write_protected = false,
-          .reserved = 0,
+          .data_len             = 3,
+          .medium_type          = 0,
+          .write_protected      = false,
+          .reserved             = 0,
           .block_descriptor_len = 0  // no block descriptor are included
       };
 
@@ -789,12 +795,11 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
     {
       scsi_sense_fixed_resp_t sense_rsp =
       {
-          .response_code = 0x70,
+          .response_code = 0x70, // current, fixed format
           .valid         = 1
       };
 
-      sense_rsp.add_sense_len = sizeof(scsi_sense_fixed_resp_t) - 8;
-
+      sense_rsp.add_sense_len       = sizeof(scsi_sense_fixed_resp_t) - 8;
       sense_rsp.sense_key           = p_msc->sense_key;
       sense_rsp.add_sense_code      = p_msc->add_sense_code;
       sense_rsp.add_sense_qualifier = p_msc->add_sense_qualifier;
@@ -802,6 +807,12 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       resplen = sizeof(sense_rsp);
       memcpy(buffer, &sense_rsp, resplen);
 
+      // request sense callback could overwrite the sense data
+      if (tud_msc_request_sense_cb)
+      {
+        resplen = tud_msc_request_sense_cb(lun, buffer, bufsize);
+      }
+
       // Clear sense data after copy
       tud_msc_set_sense(lun, 0, 0, 0);
     }
@@ -835,8 +846,8 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
     // negative means error -> endpoint is stalled & status in CSW set to failed
     TU_LOG(MSC_DEBUG, "  tud_msc_read10_cb() return -1\r\n");
 
-    // Sense = Flash not ready for access
-    tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00);
+    // set sense
+    set_default_error_sense(p_cbw->lun);
 
     fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
   }
@@ -900,8 +911,8 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
     // update actual byte before failed
     p_msc->xferred_len += xferred_bytes;
 
-    // Sense = Flash not ready for access
-    tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_MEDIUM_ERROR, 0x33, 0x00);
+    // Set sense
+    set_default_error_sense(p_cbw->lun);
 
     fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
   }else
diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h
index d32694340..5839b168d 100644
--- a/src/class/msc/msc_device.h
+++ b/src/class/msc/msc_device.h
@@ -131,6 +131,9 @@ TU_ATTR_WEAK uint8_t tud_msc_get_maxlun_cb(void);
 // - Start = 1 : active mode, if load_eject = 1 : load disk storage
 TU_ATTR_WEAK bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject);
 
+// Invoked when received REQUEST_SENSE
+TU_ATTR_WEAK int32_t tud_msc_request_sense_cb(uint8_t lun, void* buffer, uint16_t bufsize);
+
 // Invoked when Read10 command is complete
 TU_ATTR_WEAK void tud_msc_read10_complete_cb(uint8_t lun);
 

From 391edc7afb06359c7064752b1374550d1b526901 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Feb 2022 22:40:08 +0700
Subject: [PATCH 0811/2085] msc example response PREVENT_ALLOW_MEDIUM_REMOVAL
 command as unsupported command

LUN1 of msc_disk_dual will be set to not ready to simulate medium not
present (e.g SD card removed)
---
 examples/device/cdc_msc/src/msc_disk.c        |  5 -----
 .../device/cdc_msc_freertos/src/msc_disk.c    |  5 -----
 .../dynamic_configuration/src/msc_disk.c      |  5 -----
 .../device/msc_dual_lun/src/msc_disk_dual.c   | 22 ++++---------------
 src/class/msc/msc_device.c                    |  2 +-
 5 files changed, 5 insertions(+), 34 deletions(-)

diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index 3076192af..e67e381ce 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -243,11 +243,6 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
 
   switch (scsi_cmd[0])
   {
-    case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
-      // Host is about to read/write etc ... better not to disconnect disk
-      resplen = 0;
-    break;
-
     default:
       // Set Sense = Invalid Command Operation
       tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c
index b9205f0c2..a895f4738 100644
--- a/examples/device/cdc_msc_freertos/src/msc_disk.c
+++ b/examples/device/cdc_msc_freertos/src/msc_disk.c
@@ -221,11 +221,6 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
 
   switch (scsi_cmd[0])
   {
-    case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
-      // Host is about to read/write etc ... better not to disconnect disk
-      resplen = 0;
-    break;
-
     default:
       // Set Sense = Invalid Command Operation
       tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c
index b9205f0c2..a895f4738 100644
--- a/examples/device/dynamic_configuration/src/msc_disk.c
+++ b/examples/device/dynamic_configuration/src/msc_disk.c
@@ -221,11 +221,6 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
 
   switch (scsi_cmd[0])
   {
-    case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
-      // Host is about to read/write etc ... better not to disconnect disk
-      resplen = 0;
-    break;
-
     default:
       // Set Sense = Invalid Command Operation
       tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c
index 18d3ca0d7..37446ebc3 100644
--- a/examples/device/msc_dual_lun/src/msc_disk_dual.c
+++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c
@@ -28,6 +28,9 @@
 
 #if CFG_TUD_MSC
 
+// When button is pressed, LUN1 will be set to not ready to simulate
+// medium not present (e.g SD card removed)
+
 // Some MCU doesn't have enough 8KB SRAM to store the whole disk
 // We will use Flash as read-only disk with board that has
 // CFG_EXAMPLE_MSC_READONLY defined
@@ -227,7 +230,7 @@ void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16
 // return true allowing host to read/write this LUN e.g SD card inserted
 bool tud_msc_test_unit_ready_cb(uint8_t lun)
 {
-  (void) lun;
+  if ( lun == 1 && board_button_read() ) return false;
 
   return true; // RAM disk is always ready
 }
@@ -320,23 +323,6 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
 
   switch (scsi_cmd[0])
   {
-    case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
-      // Host is about to read/write etc ... better not to disconnect disk
-      resplen = 0;
-    break;
-
-    case SCSI_CMD_START_STOP_UNIT:
-      // Host try to eject/safe remove/poweroff us. We could safely disconnect with disk storage, or go into lower power
-      /* scsi_start_stop_unit_t const * start_stop = (scsi_start_stop_unit_t const *) scsi_cmd;
-        // Start bit = 0 : low power mode, if load_eject = 1 : unmount disk storage as well
-        // Start bit = 1 : Ready mode, if load_eject = 1 : mount disk storage
-        start_stop->start;
-        start_stop->load_eject;
-       */
-       resplen = 0;
-    break;
-
-
     default:
       // Set Sense = Invalid Command Operation
       tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 8f4fc9356..70ce1d352 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -209,7 +209,7 @@ TU_ATTR_UNUSED static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
   { .key = SCSI_CMD_MODE_SELECT_6                , .data = "Mode_Select 6" },
   { .key = SCSI_CMD_MODE_SENSE_6                 , .data = "Mode_Sense 6" },
   { .key = SCSI_CMD_START_STOP_UNIT              , .data = "Start Stop Unit" },
-  { .key = SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL , .data = "Prevent Allow Medium Removal" },
+  { .key = SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL , .data = "Prevent/Allow Medium Removal" },
   { .key = SCSI_CMD_READ_CAPACITY_10             , .data = "Read Capacity10" },
   { .key = SCSI_CMD_REQUEST_SENSE                , .data = "Request Sense" },
   { .key = SCSI_CMD_READ_FORMAT_CAPACITY         , .data = "Read Format Capacity" },

From 46f4f7ff491e5a45229f9d35653fd29578b9e7db Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Feb 2022 22:53:23 +0700
Subject: [PATCH 0812/2085] minor rename set sense function

---
 src/class/msc/msc_device.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 70ce1d352..e09a2b11a 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -239,7 +239,7 @@ bool tud_msc_set_sense(uint8_t lun, uint8_t sense_key, uint8_t add_sense_code, u
   return true;
 }
 
-static inline void set_default_error_sense(uint8_t lun)
+static inline void set_sense_medium_not_present(uint8_t lun)
 {
   // default sense is NOT READY, MEDIUM NOT PRESENT
   tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3A, 0x00);
@@ -661,7 +661,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         resplen = - 1;
 
         // set default sense if not set by callback
-        if ( p_msc->sense_key == 0 ) set_default_error_sense(lun);
+        if ( p_msc->sense_key == 0 ) set_sense_medium_not_present(lun);
       }
     break;
 
@@ -677,7 +677,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
           resplen = - 1;
 
           // set default sense if not set by callback
-          if ( p_msc->sense_key == 0 ) set_default_error_sense(lun);
+          if ( p_msc->sense_key == 0 ) set_sense_medium_not_present(lun);
         }
       }
     break;
@@ -698,7 +698,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         resplen = -1;
 
         // set default sense if not set by callback
-        if ( p_msc->sense_key == 0 ) set_default_error_sense(lun);
+        if ( p_msc->sense_key == 0 ) set_sense_medium_not_present(lun);
       }else
       {
         scsi_read_capacity10_resp_t read_capa10;
@@ -734,7 +734,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         resplen = -1;
 
         // set default sense if not set by callback
-        if ( p_msc->sense_key == 0 ) set_default_error_sense(lun);
+        if ( p_msc->sense_key == 0 ) set_sense_medium_not_present(lun);
       }else
       {
         read_fmt_capa.block_num = tu_htonl(block_count);
@@ -847,7 +847,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
     TU_LOG(MSC_DEBUG, "  tud_msc_read10_cb() return -1\r\n");
 
     // set sense
-    set_default_error_sense(p_cbw->lun);
+    set_sense_medium_not_present(p_cbw->lun);
 
     fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
   }
@@ -912,7 +912,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
     p_msc->xferred_len += xferred_bytes;
 
     // Set sense
-    set_default_error_sense(p_cbw->lun);
+    set_sense_medium_not_present(p_cbw->lun);
 
     fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
   }else

From a72d0245fa33e05a4b3fc44efd5e6bf2560722c6 Mon Sep 17 00:00:00 2001
From: NexusXe <andastrike@gmail.com>
Date: Wed, 16 Feb 2022 08:29:20 -0600
Subject: [PATCH 0813/2085] Fix link to supported boards

It used to point to `boards.md`, which doesn't exist.
---
 docs/reference/getting_started.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index 875372c81..77155cd67 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -37,7 +37,7 @@ It is relatively simple to incorporate tinyusb to your (existing) project
 Examples
 --------
 
-For your convenience, TinyUSB contains a handful of examples for both host and device with/without RTOS to quickly test the functionality as well as demonstrate how API() should be used. Most examples will work on most of `the supported Boards <boards.md>`_. Firstly we need to ``git clone`` if not already
+For your convenience, TinyUSB contains a handful of examples for both host and device with/without RTOS to quickly test the functionality as well as demonstrate how API() should be used. Most examples will work on most of `the supported Boards <supported.rst>`_. Firstly we need to ``git clone`` if not already
 
 .. code-block::
 

From ada7a23ddc7d429b447d34785ffec2c230d75b1d Mon Sep 17 00:00:00 2001
From: NexusXe <andastrike@gmail.com>
Date: Wed, 16 Feb 2022 08:33:06 -0600
Subject: [PATCH 0814/2085] Fix capitalization

---
 docs/reference/getting_started.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index 77155cd67..4a53626cd 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -37,7 +37,7 @@ It is relatively simple to incorporate tinyusb to your (existing) project
 Examples
 --------
 
-For your convenience, TinyUSB contains a handful of examples for both host and device with/without RTOS to quickly test the functionality as well as demonstrate how API() should be used. Most examples will work on most of `the supported Boards <supported.rst>`_. Firstly we need to ``git clone`` if not already
+For your convenience, TinyUSB contains a handful of examples for both host and device with/without RTOS to quickly test the functionality as well as demonstrate how API() should be used. Most examples will work on most of `the supported boards <supported.rst>`_. Firstly we need to ``git clone`` if not already
 
 .. code-block::
 

From a53e83665eb3d5aa70794e1648e45f644a35b994 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Feb 2022 12:12:42 +0700
Subject: [PATCH 0815/2085] fix HID_REPORT_ID_N()

---
 src/class/hid/hid.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 9265a2ede..20a5dd7f9 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -645,7 +645,7 @@ enum {
 #define HID_REPORT_SIZE_N(x, n)   HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_SIZE, RI_TYPE_GLOBAL, n)
 
 #define HID_REPORT_ID(x)          HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_ID, RI_TYPE_GLOBAL, 1),
-#define HID_REPORT_ID_N(x)        HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_ID, RI_TYPE_GLOBAL, n),
+#define HID_REPORT_ID_N(x, n)     HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_ID, RI_TYPE_GLOBAL, n),
 
 #define HID_REPORT_COUNT(x)       HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_COUNT, RI_TYPE_GLOBAL, 1)
 #define HID_REPORT_COUNT_N(x, n)  HID_REPORT_ITEM(x, RI_GLOBAL_REPORT_COUNT, RI_TYPE_GLOBAL, n)

From 52645fcc1b6f00d4bf6b211a5425addf7d3a1e8c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Feb 2022 13:07:21 +0700
Subject: [PATCH 0816/2085] fix build with latest esp idf

---
 examples/device/cdc_msc_freertos/src/CMakeLists.txt       | 4 ++++
 examples/device/hid_composite_freertos/src/CMakeLists.txt | 4 ++++
 hw/bsp/esp32s2/boards/esp32s2.c                           | 2 +-
 hw/bsp/esp32s2/family.mk                                  | 1 +
 hw/bsp/esp32s3/boards/esp32s3.c                           | 2 +-
 src/osal/osal_freertos.h                                  | 4 +++-
 src/osal/osal_rtx4.h                                      | 2 +-
 7 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index 93ae0686a..9216e2b49 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -13,6 +13,10 @@ target_include_directories(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src"
 )
 
+target_compile_definitions(${COMPONENT_TARGET} PUBLIC
+  ESP_PLATFORM
+)
+
 target_sources(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src/tusb.c"
   "${TOP}/src/common/tusb_fifo.c"
diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt
index 6f156379f..5d9fc74d3 100644
--- a/examples/device/hid_composite_freertos/src/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt
@@ -13,6 +13,10 @@ target_include_directories(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src"
 )
 
+target_compile_definitions(${COMPONENT_TARGET} PUBLIC
+  ESP_PLATFORM
+)
+
 target_sources(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src/tusb.c"
   "${TOP}/src/common/tusb_fifo.c"
diff --git a/hw/bsp/esp32s2/boards/esp32s2.c b/hw/bsp/esp32s2/boards/esp32s2.c
index a81181672..03ae9e366 100644
--- a/hw/bsp/esp32s2/boards/esp32s2.c
+++ b/hw/bsp/esp32s2/boards/esp32s2.c
@@ -32,8 +32,8 @@
 #include "hal/usb_hal.h"
 #include "soc/usb_periph.h"
 
-#include "driver/periph_ctrl.h"
 #include "driver/rmt.h"
+#include "esp_private/periph_ctrl.h"
 
 #ifdef NEOPIXEL_PIN
 #include "led_strip.h"
diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/esp32s2/family.mk
index 4b9000a6a..b95098e15 100644
--- a/hw/bsp/esp32s2/family.mk
+++ b/hw/bsp/esp32s2/family.mk
@@ -10,6 +10,7 @@ build: all
 fullclean:
 	if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
 	if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
 
 clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-components size-files:
 	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
diff --git a/hw/bsp/esp32s3/boards/esp32s3.c b/hw/bsp/esp32s3/boards/esp32s3.c
index a81181672..03ae9e366 100644
--- a/hw/bsp/esp32s3/boards/esp32s3.c
+++ b/hw/bsp/esp32s3/boards/esp32s3.c
@@ -32,8 +32,8 @@
 #include "hal/usb_hal.h"
 #include "soc/usb_periph.h"
 
-#include "driver/periph_ctrl.h"
 #include "driver/rmt.h"
+#include "esp_private/periph_ctrl.h"
 
 #ifdef NEOPIXEL_PIN
 #include "led_strip.h"
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 4573e01f5..aa102b15c 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -68,6 +68,7 @@ static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
     BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken);
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+    // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7
     if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
 #else
     portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
@@ -151,6 +152,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
     BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken);
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+    // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7
     if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
 #else
     portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
@@ -169,4 +171,4 @@ static inline bool osal_queue_empty(osal_queue_t qhdl)
  }
 #endif
 
-#endif /* _TUSB_OSAL_FREERTOS_H_ */
+#endif
diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h
index 32d7782d9..f7e88e322 100644
--- a/src/osal/osal_rtx4.h
+++ b/src/osal/osal_rtx4.h
@@ -167,4 +167,4 @@ static inline bool osal_queue_empty(osal_queue_t qhdl)
  }
 #endif
 
-#endif /* _TUSB_OSAL_FREERTOS_H_ */
+#endif

From e188117823f0406cfd8fa65e1e0e3a35019c96f2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Feb 2022 16:30:21 +0700
Subject: [PATCH 0817/2085] more esp build fix

---
 hw/bsp/esp32s2/boards/esp32s2.c | 7 ++++++-
 hw/bsp/esp32s3/boards/esp32s3.c | 7 ++++++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/esp32s2/boards/esp32s2.c b/hw/bsp/esp32s2/boards/esp32s2.c
index 03ae9e366..a7ca82deb 100644
--- a/hw/bsp/esp32s2/boards/esp32s2.c
+++ b/hw/bsp/esp32s2/boards/esp32s2.c
@@ -33,7 +33,12 @@
 #include "soc/usb_periph.h"
 
 #include "driver/rmt.h"
-#include "esp_private/periph_ctrl.h"
+
+#if ESP_IDF_VERSION_MAJOR > 4
+  #include "esp_private/periph_ctrl.h"
+#else
+  #include "driver/periph_ctrl.h"
+#endif
 
 #ifdef NEOPIXEL_PIN
 #include "led_strip.h"
diff --git a/hw/bsp/esp32s3/boards/esp32s3.c b/hw/bsp/esp32s3/boards/esp32s3.c
index 03ae9e366..a7ca82deb 100644
--- a/hw/bsp/esp32s3/boards/esp32s3.c
+++ b/hw/bsp/esp32s3/boards/esp32s3.c
@@ -33,7 +33,12 @@
 #include "soc/usb_periph.h"
 
 #include "driver/rmt.h"
-#include "esp_private/periph_ctrl.h"
+
+#if ESP_IDF_VERSION_MAJOR > 4
+  #include "esp_private/periph_ctrl.h"
+#else
+  #include "driver/periph_ctrl.h"
+#endif
 
 #ifdef NEOPIXEL_PIN
 #include "led_strip.h"

From d7495975914645d147b7b9752df9e3bab7bdcfb6 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Tue, 22 Feb 2022 18:10:09 -0800
Subject: [PATCH 0818/2085] Add dual role (concurrent) example

This reads HID devices over host and then translates that to ASCII
and sends it over CDC device.
---
 examples/host/hid_to_cdc/CMakeLists.txt       |  28 ++
 examples/host/hid_to_cdc/Makefile             |  20 ++
 examples/host/hid_to_cdc/only.txt             |   1 +
 examples/host/hid_to_cdc/src/main.c           | 291 ++++++++++++++++++
 examples/host/hid_to_cdc/src/tusb_config.h    | 163 ++++++++++
 .../host/hid_to_cdc/src/usb_descriptors.c     | 266 ++++++++++++++++
 hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk   |   3 +
 hw/bsp/imxrt/family.c                         |  23 +-
 hw/bsp/imxrt/family.mk                        |   7 +
 9 files changed, 799 insertions(+), 3 deletions(-)
 create mode 100644 examples/host/hid_to_cdc/CMakeLists.txt
 create mode 100644 examples/host/hid_to_cdc/Makefile
 create mode 100644 examples/host/hid_to_cdc/only.txt
 create mode 100644 examples/host/hid_to_cdc/src/main.c
 create mode 100644 examples/host/hid_to_cdc/src/tusb_config.h
 create mode 100644 examples/host/hid_to_cdc/src/usb_descriptors.c

diff --git a/examples/host/hid_to_cdc/CMakeLists.txt b/examples/host/hid_to_cdc/CMakeLists.txt
new file mode 100644
index 000000000..abc4d91da
--- /dev/null
+++ b/examples/host/hid_to_cdc/CMakeLists.txt
@@ -0,0 +1,28 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/host/hid_to_cdc/Makefile b/examples/host/hid_to_cdc/Makefile
new file mode 100644
index 000000000..b62a383eb
--- /dev/null
+++ b/examples/host/hid_to_cdc/Makefile
@@ -0,0 +1,20 @@
+include ../../../tools/top.mk
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
+
+SRC_C += \
+	src/class/hid/hid_host.c \
+	src/host/hub.c \
+	src/host/usbh.c \
+	src/host/usbh_control.c
+
+include ../../rules.mk
diff --git a/examples/host/hid_to_cdc/only.txt b/examples/host/hid_to_cdc/only.txt
new file mode 100644
index 000000000..87bf09f24
--- /dev/null
+++ b/examples/host/hid_to_cdc/only.txt
@@ -0,0 +1 @@
+board:mimxrt1060_evk
diff --git a/examples/host/hid_to_cdc/src/main.c b/examples/host/hid_to_cdc/src/main.c
new file mode 100644
index 000000000..e11f34cc2
--- /dev/null
+++ b/examples/host/hid_to_cdc/src/main.c
@@ -0,0 +1,291 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+// This example runs both host and device concurrently. The USB host looks for
+// any HID device with reports that are 8 bytes long and then assumes they are
+// keyboard reports. It translates the keypresses of the reports to ASCII and
+// transmits it over CDC to the device's host.
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+void led_blinking_task(void);
+void cdc_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+  tusb_init();
+
+  while (1)
+  {
+    tud_task(); // tinyusb device task
+    tuh_task(); // tinyusb host task
+    led_blinking_task();
+
+    cdc_task();
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+  (void) remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// Host callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device with hid interface is mounted
+// Report descriptor is also available for use. tuh_hid_parse_report_descriptor()
+// can be used to parse common/simple enough descriptor.
+// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
+// therefore report_desc = NULL, desc_len = 0
+void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
+{
+  (void)desc_report;
+  (void)desc_len;
+  uint16_t vid, pid;
+  tuh_vid_pid_get(dev_addr, &vid, &pid);
+
+  printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance);
+  printf("VID = %04x, PID = %04x\r\n", vid, pid);
+
+  // Receive any report and treat it like a keyboard.
+  // tuh_hid_report_received_cb() will be invoked when report is available
+  if ( !tuh_hid_receive_report(dev_addr, instance) )
+  {
+    printf("Error: cannot request to receive report\r\n");
+  }
+}
+
+// Invoked when device with hid interface is un-mounted
+void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
+{
+  printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+}
+
+const char* numbers = "0123456789";
+
+// Uncomment if you use colemak and need to remap keys (like @tannewt.)
+// const uint8_t colemak[77] = {
+//    0,  0,  0,  0,  0,  0,  0, 22,
+//    9, 23,  7,  0, 24, 17,  8, 12,
+//    0, 14, 28, 51,  0, 19, 21, 10,
+//   15,  0,  0,  0, 13,  0,  0,  0,
+//    0,  0,  0,  0,  0,  0,  0,  0,
+//    0,  0,  0,  0,  0,  0,  0,  0,
+//    0,  0,  0, 18,  0,  0,  0,  0,
+//    0,  0,  0,  0,  0,  0,  0,  0,
+//    0,  0,  0,  0,  0,  0,  0,  0,
+//    0,  0,  0,  0,  0
+// };
+
+// This is the reverse mapping of the US key layout in Adafruit_CircuitPython_HID.
+const char* ascii = "\0\0\0\0abcdefghijklmnopqrstuvwxyz1234567890\n\x1b\x08\t -=[]\\\x00;\'`,./\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x7f";
+const char* shifted = "\0\0\0\0ABCDEFGHIJKLMNOPQRSTUVWXYZ!@#$%^&*()\0\0\0\0\0_+{}|\0:\"~<>?\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0";
+// Bitmask of pressed keys. We use the current modifier state.
+uint32_t last_state[8];
+
+// Invoked when received report from device via interrupt endpoint
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
+{
+  if (len != 8 && len < 10) {
+    tud_cdc_write("report len: ", 12);
+    tud_cdc_write(numbers + len, 1);
+    tud_cdc_write("\r\n", 2);
+    tud_cdc_write_flush();
+  }
+  if (len != 8) {
+    // Don't request a new report for a wrong sized endpoint.
+    return;
+  }
+  uint8_t modifiers = report[0];
+  bool flush = false;
+  for (int i = 2; i < 8; i++) {
+    if (report[i] == 0) {
+      continue;
+    }
+    uint8_t down = report[i];
+    uint32_t mask = 1 << (down % 32);
+    bool was_down = (last_state[down / 32] & mask) != 0;
+    // Only map keycodes 0 - 76.
+    if (!was_down && down < 77) {
+      const char* layer = ascii;
+      // Check shift bits
+      if ((modifiers & 0x22) != 0) {
+        layer = shifted;
+      }
+      // Map the key code for Colemak layout so @tannewt can type.
+      // uint8_t colemak_key_code = colemak[down];
+      // if (colemak_key_code != 0) {
+      //   down = colemak_key_code;
+      // }
+      char c = layer[down];
+      if (c == '\0') {
+        continue;
+      }
+      if (c == '\n') {
+        tud_cdc_write("\r", 1);
+      }
+      tud_cdc_write(&c, 1);
+      flush = true;
+    }
+  }
+  if (flush) {
+    tud_cdc_write_flush();
+  }
+  // Now update last_state
+  memset(last_state, 0, 8 * sizeof(uint32_t));
+  for (int i = 2; i < 8; i++) {
+    if (report[i] == 0) {
+      continue;
+    }
+    uint8_t down = report[i];
+    last_state[down / 32] |= 1 << (down % 32);
+  }
+  // continue to request to receive report
+  if ( !tuh_hid_receive_report(dev_addr, instance) )
+  {
+    printf("Error: cannot request to receive report\r\n");
+  }
+}
+
+
+
+//--------------------------------------------------------------------+
+// USB CDC
+//--------------------------------------------------------------------+
+void cdc_task(void)
+{
+  // connected() check for DTR bit
+  // Most but not all terminal client set this when making connection
+  // if ( tud_cdc_connected() )
+  {
+    // connected and there are data available
+    if ( tud_cdc_available() )
+    {
+      // read datas
+      char buf[64];
+      uint32_t count = tud_cdc_read(buf, sizeof(buf));
+      (void) count;
+
+      // Echo back
+      // Note: Skip echo by commenting out write() and write_flush()
+      // for throughput test e.g
+      //    $ dd if=/dev/zero of=/dev/ttyACM0 count=10000
+      tud_cdc_write(buf, count);
+      tud_cdc_write_flush();
+    }
+  }
+}
+
+// Invoked when cdc when line state changed e.g connected/disconnected
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
+{
+  (void) itf;
+  (void) rts;
+
+  // TODO set some indicator
+  if ( dtr )
+  {
+    // Terminal connected
+  }else
+  {
+    // Terminal disconnected
+  }
+}
+
+// Invoked when CDC interface received data from host
+void tud_cdc_rx_cb(uint8_t itf)
+{
+  (void) itf;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/host/hid_to_cdc/src/tusb_config.h b/examples/host/hid_to_cdc/src/tusb_config.h
new file mode 100644
index 000000000..9a35ffc30
--- /dev/null
+++ b/examples/host/hid_to_cdc/src/tusb_config.h
@@ -0,0 +1,163 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by board.mk
+#ifndef CFG_TUSB_MCU
+  #error CFG_TUSB_MCU must be defined
+#endif
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_DEVICE_RHPORT_NUM
+  #define BOARD_DEVICE_RHPORT_NUM     0
+#endif
+
+// RHPort number used for device can be defined by board.mk, default to port 1
+#ifndef BOARD_HOST_RHPORT_NUM
+  #define BOARD_HOST_RHPORT_NUM     1
+#endif
+
+// RHPort max operational speed can defined by board.mk
+// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+#ifndef BOARD_DEVICE_RHPORT_SPEED
+  #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
+      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) ||\
+      TU_CHECK_MCU(OPT_MCU_FT90X, OPT_MCU_FT93X)
+    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
+  #else
+    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
+  #endif
+#endif
+
+// RHPort max operational speed can defined by board.mk
+// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+#ifndef BOARD_HOST_RHPORT_SPEED
+  #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
+      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) ||\
+      TU_CHECK_MCU(OPT_MCU_FT90X, OPT_MCU_FT93X)
+    #define BOARD_HOST_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
+  #else
+    #define BOARD_HOST_RHPORT_SPEED   OPT_MODE_FULL_SPEED
+  #endif
+#endif
+
+// Device mode with rhport and speed defined by board.mk
+#if   BOARD_DEVICE_RHPORT_NUM == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#elif BOARD_DEVICE_RHPORT_NUM == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#else
+  #error "Incorrect RHPort configuration"
+#endif
+
+// Device mode with rhport and speed defined by board.mk
+#if   BOARD_HOST_RHPORT_NUM == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_HOST | BOARD_HOST_RHPORT_SPEED)
+#elif BOARD_HOST_RHPORT_NUM == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_HOST | BOARD_HOST_RHPORT_SPEED)
+#else
+  #error "Incorrect RHPort configuration"
+#endif
+
+// This example doesn't use an RTOS
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS               OPT_OS_NONE
+#endif
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC              1
+#define CFG_TUD_MSC              0
+#define CFG_TUD_HID              0
+#define CFG_TUD_MIDI             0
+#define CFG_TUD_VENDOR           0
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+//--------------------------------------------------------------------
+// HOST CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#define CFG_TUH_HUB                 1
+#define CFG_TUH_CDC                 0
+#define CFG_TUH_MSC                 0
+#define CFG_TUH_VENDOR              0
+
+// max device support (excluding hub device)
+#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
+
+//------------- HID -------------//
+#define CFG_TUH_HID                  4
+#define CFG_TUH_HID_EPIN_BUFSIZE    64
+#define CFG_TUH_HID_EPOUT_BUFSIZE   64
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/host/hid_to_cdc/src/usb_descriptors.c b/examples/host/hid_to_cdc/src/usb_descriptors.c
new file mode 100644
index 000000000..7dd73937c
--- /dev/null
+++ b/examples/host/hid_to_cdc/src/usb_descriptors.c
@@ -0,0 +1,266 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]         HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+                           _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
+
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+  .bLength            = sizeof(tusb_desc_device_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE,
+  .bcdUSB             = USB_BCD,
+
+  // Use Interface Association Descriptor (IAD) for CDC
+  // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+  .bDeviceClass       = TUSB_CLASS_MISC,
+  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+  .idVendor           = USB_VID,
+  .idProduct          = USB_PID,
+  .bcdDevice          = 0x0100,
+
+  .iManufacturer      = 0x01,
+  .iProduct           = 0x02,
+  .iSerialNumber      = 0x03,
+
+  .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+  return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+enum
+{
+  ITF_NUM_CDC = 0,
+  ITF_NUM_CDC_DATA,
+  ITF_NUM_MSC,
+  ITF_NUM_TOTAL
+};
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x82
+
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
+  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x83
+
+#elif CFG_TUSB_MCU == OPT_MCU_CXD56
+  // CXD56 doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number
+  // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN)
+  #define EPNUM_CDC_NOTIF   0x83
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x81
+
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x83
+
+#else
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x82
+
+#endif
+
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
+
+// full speed configuration
+uint8_t const desc_fs_configuration[] =
+{
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
+
+// high speed configuration
+uint8_t const desc_hs_configuration[] =
+{
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
+};
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier =
+{
+  .bLength            = sizeof(tusb_desc_device_qualifier_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
+  .bcdUSB             = USB_BCD,
+
+  .bDeviceClass       = TUSB_CLASS_MISC,
+  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+  .bNumConfigurations = 0x01,
+  .bReserved          = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void)
+{
+  return (uint8_t const*) &desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
+
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ?  desc_hs_configuration : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] =
+{
+  (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+  "TinyUSB",                     // 1: Manufacturer
+  "TinyUSB Device",              // 2: Product
+  "123456789012",                // 3: Serials, should use chip ID
+  "TinyUSB CDC",                 // 4: CDC Interface
+};
+
+static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
+{
+  (void) langid;
+
+  uint8_t chr_count;
+
+  if ( index == 0)
+  {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  }else
+  {
+    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+
+    const char* str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = (uint8_t) strlen(str);
+    if ( chr_count > 31 ) chr_count = 31;
+
+    // Convert ASCII string into UTF-16
+    for(uint8_t i=0; i<chr_count; i++)
+    {
+      _desc_str[1+i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+
+  return _desc_str;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
index d0498dbb1..b14b2a6b9 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
@@ -7,5 +7,8 @@ JLINK_DEVICE = MIMXRT1062xxx6A
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1060
 
+BOARD_DEVICE_RHPORT_NUM = 1
+BOARD_HOST_RHPORT_NUM = 0
+
 # flash using pyocd
 flash: flash-pyocd
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 716681ca9..03be3b3dc 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -99,12 +99,12 @@ void board_init(void)
   CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
 
   // USB1
-//  CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
-//  CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
+  CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
+  CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
 
   USBPHY_Type* usb_phy;
 
-  // RT105x RT106x have dual USB controller. TODO support USB2
+  // RT105x RT106x have dual USB controller.
 #ifdef USBPHY1
   usb_phy = USBPHY1;
 #else
@@ -122,6 +122,23 @@ void board_init(void)
   phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
   phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
   usb_phy->TX = phytx;
+
+  // RT105x RT106x have dual USB controller.
+#ifdef USBPHY2
+  usb_phy = USBPHY2;
+
+  // Enable PHY support for Low speed device + LS via FS Hub
+  usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+  // Enable all power for normal operation
+  usb_phy->PWD = 0;
+
+  // TX Timing
+  phytx = usb_phy->TX;
+  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+  usb_phy->TX = phytx;
+#endif
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index d086d503f..0bf4a0d15 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -15,6 +15,13 @@ CFLAGS += \
   -DXIP_BOOT_HEADER_ENABLE=1 \
   -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX
 
+ifdef BOARD_DEVICE_RHPORT_NUM
+CFLAGS += -DBOARD_DEVICE_RHPORT_NUM=$(BOARD_DEVICE_RHPORT_NUM)
+endif
+ifdef BOARD_HOST_RHPORT_NUM
+CFLAGS += -DBOARD_HOST_RHPORT_NUM=$(BOARD_HOST_RHPORT_NUM)
+endif
+
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough=
 

From 9ba1ba8fa13dc63a3075f41c4944f22ea12021e6 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Tue, 22 Feb 2022 18:39:02 -0800
Subject: [PATCH 0819/2085] Guard clock setup for USB2

---
 hw/bsp/imxrt/family.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 03be3b3dc..a811a7e40 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -98,10 +98,6 @@ void board_init(void)
   CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
   CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
 
-  // USB1
-  CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
-  CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
-
   USBPHY_Type* usb_phy;
 
   // RT105x RT106x have dual USB controller.
@@ -125,6 +121,10 @@ void board_init(void)
 
   // RT105x RT106x have dual USB controller.
 #ifdef USBPHY2
+  // USB1
+  CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
+  CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
+
   usb_phy = USBPHY2;
 
   // Enable PHY support for Low speed device + LS via FS Hub

From 566e3abcea0b987a832116d0a48bde5890bdee3d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 23 Feb 2022 11:55:57 +0700
Subject: [PATCH 0820/2085] increase version, update doc for release

---
 CONTRIBUTORS.rst        | 13 ++++++++++---
 docs/info/changelog.rst | 40 ++++++++++++++++++++++++++++++++++++++++
 src/tusb_option.h       |  2 +-
 3 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index 05d088ee7..5726169f8 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -18,6 +18,12 @@ Notable contributors
 -  Design the project logo
 
 
+`Gordon McNab <https://github.com/ftdigdm>`__
+---------------------------------------------
+
+-  Add new DCD port for Bridgetek FT90x and FT93x
+
+
 `Ha Thach <https://github.com/hathach>`__
 -----------------------------------------
 
@@ -53,6 +59,7 @@ Notable contributors
 -----------------------------------------------
 
 -  Add new DCD port for Dialog DA1469x
+-  Add new DCD port for PIC32MZ
 -  Add new class driver for Bluetooth HCI
 -  Add ISO transfer for STM32 Synopsys, Nordic nRF, Dialog DA1469x
 -  Improve Audio driver and add uac2\_headset example
@@ -81,11 +88,11 @@ Notable contributors
 `Koji KITAYAMA <https://github.com/kkitayam>`__
 -----------------------------------------------
 
--  Add new DCD port for NXP Kinetis KL25
--  Add new DCD port for Renesas RX family (RX600, RX700 ..) with GR-CITRUS, RX65n target board
+-  Add new DCD and HCD port for NXP Kinetis KL25
+-  Add new DCD and HCD port for Renesas RX family (RX600, RX700 ..) with GR-CITRUS, RX65n target board
+-  Add new DCD and HCD port for Mentor musb with MSP432E4
 -  Add new class driver for USB Video Class (UVC 1.5)
 
-
 `Nathan Conrad <https://github.com/pigrew>`__
 ---------------------------------------------
 
diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index 8eec729d6..bd6712b93 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -2,6 +2,46 @@
 Changelog
 *********
 
+0.13.0
+======
+
+- [tu_fifo] Fix locked mutex when full, and return type in peek_n()
+
+Controller Driver (DCD & HCD)
+-----------------------------
+
+- [DWC2] Generalize synopsys dwc2 with synopsys/dwc2 which support both FS and HS phy (UTMI and ULPI) for various MCUs.
+  - Broadcom 28/27xx on raspberrypi SBC
+  - Silicon Labs EFM32
+  - Espressif ESP32 Sx
+  - GigaDevice GD32
+  - ST STM32
+  - Infineon XMC
+- [KL25] Add new HCD for NXP KL25
+- [MUSB] Add new DCD and HCD for Mentor musb with TI MSP432E4
+- [F1C100s] Add new DCD for Allwinner F1C100s family
+- [PIC32MZ] Add new DCD for PIC32MZ
+- [nRF] Fix/Enhance varous race condtion with: EASY DMA, request HFXO, EPOUT
+- [ChipIdea] rename Transdimension to more popular ChipIdea Highspeed, 
+- [RP2040] various update/fix for hcd/dcd
+- [FT9XX] new DCD port for Bridgetek FT90x and FT93x devices
+- [DA1469X] Fix resume
+- [OHCI] Fix device array out of bound
+
+Note: legacy drivers such as st/synopsys, nxp/transdimension are still present in this release but won't recieve more update and could be removed in the future.
+
+Device Stack
+------------
+
+- [Audio] Support disabling feedback format correction (16.16 <-> 10.14 format)
+- [MSC] Add tud_msc_request_sense_cb() callback, change most default sense error to medium not present (0x02, 0x3A, 0x00)
+- [Video] Fix video_capture example fails enumeration when 8FPS
+
+Host Stack
+----------
+
+No notable changes
+
 0.12.0
 ======
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index c78fc471e..cb49c85ce 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -30,7 +30,7 @@
 #include "common/tusb_compiler.h"
 
 #define TUSB_VERSION_MAJOR     0
-#define TUSB_VERSION_MINOR     12
+#define TUSB_VERSION_MINOR     13
 #define TUSB_VERSION_REVISION  0
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
 

From c0a65ba0f62287cb7b5091a263656fdb26a140e9 Mon Sep 17 00:00:00 2001
From: Charlie Birks <charlie@daft.games>
Date: Wed, 23 Feb 2022 12:25:01 +0000
Subject: [PATCH 0821/2085] Support interrupt OUT in RP2040 HCD

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 3e80dd872..4ffad75a0 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -328,9 +328,11 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
         // endpoint number / direction
         // preamble
         uint32_t reg = dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB);
-        // Assert the interrupt endpoint is IN_TO_HOST
-        // TODO Interrupt can also be OUT
-        assert(dir == TUSB_DIR_IN);
+
+        if (dir == TUSB_DIR_OUT)
+        {
+            reg |= USB_ADDR_ENDP1_INTEP_DIR_BITS;
+        }
 
         if (need_pre(dev_addr))
         {

From 83b638f2305c50945670d2e1dd5eb91eeff7c3c8 Mon Sep 17 00:00:00 2001
From: Charlie Birks <charlie@daft.games>
Date: Wed, 23 Feb 2022 13:03:20 +0000
Subject: [PATCH 0822/2085] Open OUT endpoint for HID host

---
 src/class/hid/hid_host.c | 29 ++++++++++++++++++-----------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index f19f1ba81..1e13ccc7c 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -286,28 +286,35 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   hidh_device_t* hid_dev = get_dev(dev_addr);
   TU_ASSERT(hid_dev->inst_count < CFG_TUH_HID, 0);
 
-  //------------- Endpoint Descriptor -------------//
+  hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count);  
+
+  //------------- Endpoint Descriptors -------------//
   p_desc = tu_desc_next(p_desc);
   tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-  TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
 
-  // first endpoint may be OUT, skip to IN endpoint
-  // TODO also open endpoint OUT
-  if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_OUT)
+  for(int i = 0; i < desc_itf->bNumEndpoints; i++)
   {
+    TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
+    TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep) );
+
+    if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
+    {
+      hid_itf->ep_in     = desc_ep->bEndpointAddress;
+      hid_itf->epin_size = tu_edpt_packet_size(desc_ep);
+    }
+    else
+    {
+      hid_itf->ep_out     = desc_ep->bEndpointAddress;
+      hid_itf->epout_size = tu_edpt_packet_size(desc_ep);
+    }
+
     p_desc = tu_desc_next(p_desc);
     desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-    TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
   }
 
-  TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep) );
-
-  hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count);
   hid_dev->inst_count++;
 
   hid_itf->itf_num   = desc_itf->bInterfaceNumber;
-  hid_itf->ep_in     = desc_ep->bEndpointAddress;
-  hid_itf->epin_size = tu_edpt_packet_size(desc_ep);
 
   // Assume bNumDescriptors = 1
   hid_itf->report_desc_type = desc_hid->bReportType;

From 81e33477ea2d2a4f056d8d9c4cacfbbd7a4bc8e8 Mon Sep 17 00:00:00 2001
From: Alexandre Perrin <alexandreperr@gmail.com>
Date: Wed, 23 Feb 2022 18:27:52 +0100
Subject: [PATCH 0823/2085] Fix CPP compilation with IAR

IAR defines __STDC_VERSION__ in cpp as well.
Which causes TU_VERIFY_STATIC to be defined as _Static_assert
instead of cpp's static_assert.

This reorders __cplusplus__ to be first, then to fallback to
__STDC_VERSION__ if not CPP.
---
 src/common/tusb_compiler.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 38e6a16d0..93af44115 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -51,10 +51,10 @@
 #endif
 
 // Compile-time Assert
-#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
-  #define TU_VERIFY_STATIC   _Static_assert
-#elif defined (__cplusplus) && __cplusplus >= 201103L
+#if defined (__cplusplus) && __cplusplus >= 201103L
   #define TU_VERIFY_STATIC   static_assert
+#elif defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
+  #define TU_VERIFY_STATIC   _Static_assert
 #elif defined(__CCRX__)
   #define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT(Line, __LINE__)[(const_expr) ? 1 : 0];
 #else

From a8d6e823951a758829b53199de25a4ff2ce14494 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Feb 2022 17:36:05 +0700
Subject: [PATCH 0824/2085] enhance dual role examples

---
 examples/host/hid_to_cdc/only.txt           |   1 +
 examples/host/hid_to_cdc/src/main.c         | 154 +++++++++++---------
 hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk |   3 +
 src/class/hid/hid.h                         |   5 +-
 4 files changed, 97 insertions(+), 66 deletions(-)

diff --git a/examples/host/hid_to_cdc/only.txt b/examples/host/hid_to_cdc/only.txt
index 87bf09f24..78d94e3ce 100644
--- a/examples/host/hid_to_cdc/only.txt
+++ b/examples/host/hid_to_cdc/only.txt
@@ -1 +1,2 @@
 board:mimxrt1060_evk
+board:mimxrt1064_evk
diff --git a/examples/host/hid_to_cdc/src/main.c b/examples/host/hid_to_cdc/src/main.c
index e11f34cc2..cdf5d264e 100644
--- a/examples/host/hid_to_cdc/src/main.c
+++ b/examples/host/hid_to_cdc/src/main.c
@@ -39,6 +39,26 @@
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
 
+// uncomment if you are using colemak layout
+// #define KEYBOARD_COLEMAK
+
+#ifdef KEYBOARD_COLEMAK
+const uint8_t colemak[128] = {
+  0  ,  0,  0,  0,  0,  0,  0, 22,
+  9  , 23,  7,  0, 24, 17,  8, 12,
+  0  , 14, 28, 51,  0, 19, 21, 10,
+  15 ,  0,  0,  0, 13,  0,  0,  0,
+  0  ,  0,  0,  0,  0,  0,  0,  0,
+  0  ,  0,  0,  0,  0,  0,  0,  0,
+  0  ,  0,  0, 18,  0,  0,  0,  0,
+  0  ,  0,  0,  0,  0,  0,  0,  0,
+  0  ,  0,  0,  0,  0,  0,  0,  0,
+  0  ,  0,  0,  0,  0,  0,  0,  0
+};
+#endif
+
+static uint8_t const keycode2ascii[128][2] =  { HID_KEYCODE_TO_ASCII };
+
 /* Blink pattern
  * - 250 ms  : device not mounted
  * - 1000 ms : device mounted
@@ -137,85 +157,89 @@ void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
   printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
 }
 
-const char* numbers = "0123456789";
+// keycodes from last report to check if key is holding or newly pressed
+uint8_t last_keycodes[6] = {0};
 
-// Uncomment if you use colemak and need to remap keys (like @tannewt.)
-// const uint8_t colemak[77] = {
-//    0,  0,  0,  0,  0,  0,  0, 22,
-//    9, 23,  7,  0, 24, 17,  8, 12,
-//    0, 14, 28, 51,  0, 19, 21, 10,
-//   15,  0,  0,  0, 13,  0,  0,  0,
-//    0,  0,  0,  0,  0,  0,  0,  0,
-//    0,  0,  0,  0,  0,  0,  0,  0,
-//    0,  0,  0, 18,  0,  0,  0,  0,
-//    0,  0,  0,  0,  0,  0,  0,  0,
-//    0,  0,  0,  0,  0,  0,  0,  0,
-//    0,  0,  0,  0,  0
-// };
+// look up new key in previous keys
+static inline bool key_in_last_report(const uint8_t key_arr[6], uint8_t keycode)
+{
+  for(uint8_t i=0; i<6; i++)
+  {
+    if (key_arr[i] == keycode) return true;
+  }
 
-// This is the reverse mapping of the US key layout in Adafruit_CircuitPython_HID.
-const char* ascii = "\0\0\0\0abcdefghijklmnopqrstuvwxyz1234567890\n\x1b\x08\t -=[]\\\x00;\'`,./\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x7f";
-const char* shifted = "\0\0\0\0ABCDEFGHIJKLMNOPQRSTUVWXYZ!@#$%^&*()\0\0\0\0\0_+{}|\0:\"~<>?\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0";
-// Bitmask of pressed keys. We use the current modifier state.
-uint32_t last_state[8];
+  return false;
+}
 
 // Invoked when received report from device via interrupt endpoint
 void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
 {
-  if (len != 8 && len < 10) {
-    tud_cdc_write("report len: ", 12);
-    tud_cdc_write(numbers + len, 1);
-    tud_cdc_write("\r\n", 2);
+  if (len != 8)
+  {
+    char ch_num;
+
+    tud_cdc_write_str("incorrect report len: ");
+
+    if ( len > 10 )
+    {
+      ch_num = '0' + (len / 10);
+      tud_cdc_write(&ch_num, 1);
+      len = len % 10;
+    }
+
+    ch_num = '0' + len;
+    tud_cdc_write(&ch_num, 1);
+
+    tud_cdc_write_str("\r\n");
     tud_cdc_write_flush();
-  }
-  if (len != 8) {
+
     // Don't request a new report for a wrong sized endpoint.
     return;
   }
-  uint8_t modifiers = report[0];
+
+  uint8_t const modifiers = report[0];
   bool flush = false;
-  for (int i = 2; i < 8; i++) {
-    if (report[i] == 0) {
-      continue;
-    }
-    uint8_t down = report[i];
-    uint32_t mask = 1 << (down % 32);
-    bool was_down = (last_state[down / 32] & mask) != 0;
-    // Only map keycodes 0 - 76.
-    if (!was_down && down < 77) {
-      const char* layer = ascii;
-      // Check shift bits
-      if ((modifiers & 0x22) != 0) {
-        layer = shifted;
+
+  for (int i = 2; i < 8; i++)
+  {
+    uint8_t keycode = report[i];
+
+    if (keycode)
+    {
+      if ( key_in_last_report(last_keycodes, keycode) )
+      {
+        // exist in previous report means the current key is holding
+        // do nothing
+      }else
+      {
+        // not existed in previous report means the current key is pressed
+        // Only print keycodes 0 - 128.
+        if (keycode < 128)
+        {
+          // remap the key code for Colemak layout so @tannewt can type.
+          #ifdef KEYBOARD_COLEMAK
+          uint8_t colemak_key_code = colemak[keycode];
+          if (colemak_key_code != 0) keycode = colemak_key_code;
+          #endif
+
+          bool const is_shift = modifiers & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
+          char c = keycode2ascii[keycode][is_shift ? 1 : 0];
+          if (c)
+          {
+            if (c == '\n') tud_cdc_write("\r", 1);
+            tud_cdc_write(&c, 1);
+            flush = true;
+          }
+        }
       }
-      // Map the key code for Colemak layout so @tannewt can type.
-      // uint8_t colemak_key_code = colemak[down];
-      // if (colemak_key_code != 0) {
-      //   down = colemak_key_code;
-      // }
-      char c = layer[down];
-      if (c == '\0') {
-        continue;
-      }
-      if (c == '\n') {
-        tud_cdc_write("\r", 1);
-      }
-      tud_cdc_write(&c, 1);
-      flush = true;
     }
   }
-  if (flush) {
-    tud_cdc_write_flush();
-  }
-  // Now update last_state
-  memset(last_state, 0, 8 * sizeof(uint32_t));
-  for (int i = 2; i < 8; i++) {
-    if (report[i] == 0) {
-      continue;
-    }
-    uint8_t down = report[i];
-    last_state[down / 32] |= 1 << (down % 32);
-  }
+
+  if (flush) tud_cdc_write_flush();
+
+  // save current report
+  memcpy(last_keycodes, report+2, 6);
+
   // continue to request to receive report
   if ( !tuh_hid_receive_report(dev_addr, instance) )
   {
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
index 586d74fe5..2b479719f 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
@@ -7,5 +7,8 @@ JLINK_DEVICE = MIMXRT1064xxx6A
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1064
 
+BOARD_DEVICE_RHPORT_NUM = 1
+BOARD_HOST_RHPORT_NUM = 0
+
 # flash using pyocd
 flash: flash-pyocd
diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 20a5dd7f9..940454bd9 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -1106,7 +1106,10 @@ enum
     {'8'   , 0      }, /* 0x60 */ \
     {'9'   , 0      }, /* 0x61 */ \
     {'0'   , 0      }, /* 0x62 */ \
-    {'0'   , 0      }, /* 0x63 */ \
+    {'.'   , 0      }, /* 0x63 */ \
+    {0     , 0      }, /* 0x64 */ \
+    {0     , 0      }, /* 0x65 */ \
+    {0     , 0      }, /* 0x66 */ \
     {'='   , '='    }, /* 0x67 */ \
 
 

From 4a5a53b3b88fcd2f5ec7f1f94eb07c27cb1e9bec Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 23 Feb 2022 18:42:32 +0700
Subject: [PATCH 0825/2085] improve rphort management for usbd

---
 src/class/cdc/cdc_rndis_host.c      | 10 ++++++
 src/device/usbd.c                   | 28 ++++++++++-----
 src/device/usbd_pvt.h               |  2 ++
 src/host/usbh.c                     | 14 +++++++-
 src/host/usbh_classdriver.h         |  2 ++
 src/osal/osal.h                     | 56 +++++++++--------------------
 src/osal/osal_freertos.h            |  2 +-
 src/osal/osal_mynewt.h              |  2 +-
 src/osal/osal_none.h                | 41 +++++----------------
 src/osal/osal_pico.h                |  2 +-
 src/osal/osal_rtthread.h            |  2 +-
 src/osal/osal_rtx4.h                |  2 +-
 src/portable/sony/cxd56/dcd_cxd56.c |  3 +-
 13 files changed, 78 insertions(+), 88 deletions(-)

diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c
index cc4ffd1cf..d41cf91ac 100644
--- a/src/class/cdc/cdc_rndis_host.c
+++ b/src/class/cdc/cdc_rndis_host.c
@@ -35,6 +35,16 @@
 #include "cdc_host.h"
 #include "cdc_rndis_host.h"
 
+#if 0  // TODO remove subtask related macros later
+// Sub Task
+#define OSAL_SUBTASK_BEGIN
+#define OSAL_SUBTASK_END                    return TUSB_ERROR_NONE;
+
+#define STASK_RETURN(_error)                return _error;
+#define STASK_INVOKE(_subtask, _status)     (_status) = _subtask
+#define STASK_ASSERT(_cond)                 TU_VERIFY(_cond, TUSB_ERROR_OSAL_TASK_FAILED)
+#endif
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 448114303..37ca9822f 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -269,11 +269,12 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 // DCD Event
 //--------------------------------------------------------------------+
 
-static bool _usbd_initialized = false;
+enum { RHPORT_INVALID = 0xFFu };
+static uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // OPT_MODE_DEVICE is used by OS NONE for mutex (disable usb isr)
-OSAL_QUEUE_DEF(OPT_MODE_DEVICE, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
+OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
 static osal_queue_t _usbd_q;
 
 // Mutex for claiming endpoint, only needed when using with preempted RTOS
@@ -376,21 +377,21 @@ bool tud_remote_wakeup(void)
 {
   // only wake up host if this feature is supported and enabled and we are suspended
   TU_VERIFY (_usbd_dev.suspended && _usbd_dev.remote_wakeup_support && _usbd_dev.remote_wakeup_en );
-  dcd_remote_wakeup(TUD_OPT_RHPORT);
+  dcd_remote_wakeup(_usbd_rhport);
   return true;
 }
 
 bool tud_disconnect(void)
 {
   TU_VERIFY(dcd_disconnect);
-  dcd_disconnect(TUD_OPT_RHPORT);
+  dcd_disconnect(_usbd_rhport);
   return true;
 }
 
 bool tud_connect(void)
 {
   TU_VERIFY(dcd_connect);
-  dcd_connect(TUD_OPT_RHPORT);
+  dcd_connect(_usbd_rhport);
   return true;
 }
 
@@ -399,13 +400,13 @@ bool tud_connect(void)
 //--------------------------------------------------------------------+
 bool tud_inited(void)
 {
-  return _usbd_initialized;
+  return _usbd_rhport != RHPORT_INVALID;
 }
 
 bool tud_init (uint8_t rhport)
 {
   // skip if already initialized
-  if (_usbd_initialized) return _usbd_initialized;
+  if ( tud_inited() ) return true;
 
   TU_LOG2("USBD init\r\n");
 
@@ -439,7 +440,7 @@ bool tud_init (uint8_t rhport)
   dcd_init(rhport);
   dcd_int_enable(rhport);
 
-  _usbd_initialized = true;
+  _usbd_rhport = rhport;
 
   return true;
 }
@@ -1173,6 +1174,17 @@ void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_
 // USBD API For Class Driver
 //--------------------------------------------------------------------+
 
+void usbd_int_set(bool enabled)
+{
+  if (enabled)
+  {
+    dcd_int_enable(_usbd_rhport);
+  }else
+  {
+    dcd_int_disable(_usbd_rhport);
+  }
+}
+
 // Parse consecutive endpoint descriptors (IN & OUT)
 bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in)
 {
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 7607b9895..dae95cebb 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -58,6 +58,8 @@ usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR
 
 typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 
+void usbd_int_set(bool enabled);
+
 //--------------------------------------------------------------------+
 // USBD Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index b8439addc..9854b75a3 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -215,7 +215,7 @@ CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUH_DEVICE_MAX + CFG_TUH_HU
 
 // Event queue
 // role device/host is used by OS NONE for mutex (disable usb isr)
-OSAL_QUEUE_DEF(OPT_MODE_HOST, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
+OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
 
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
@@ -434,6 +434,18 @@ uint8_t* usbh_get_enum_buf(void)
   return _usbh_ctrl_buf;
 }
 
+void usbh_int_set(bool enabled)
+{
+  // TODO all host controller
+  if (enabled)
+  {
+    hcd_int_enable(TUH_OPT_RHPORT);
+  }else
+  {
+    hcd_int_disable(TUH_OPT_RHPORT);
+  }
+}
+
 //--------------------------------------------------------------------+
 // HCD Event Handler
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index 8bc2622aa..2f9957cc6 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -57,6 +57,8 @@ uint8_t usbh_get_rhport(uint8_t dev_addr);
 
 uint8_t* usbh_get_enum_buf(void);
 
+void usbh_int_set(bool enabled);
+
 //--------------------------------------------------------------------+
 // USBH Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/osal/osal.h b/src/osal/osal.h
index b2943cc79..7111bbdb2 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -31,9 +31,6 @@
  extern "C" {
 #endif
 
-/** \addtogroup group_osal
- *  @{ */
-
 #include "common/tusb_common.h"
 
 // Return immediately
@@ -67,47 +64,26 @@ typedef void (*osal_task_func_t)( void * );
 
 //--------------------------------------------------------------------+
 // OSAL Porting API
+// Should be implemented as static inline function in osal_port.h header
+/*
+    static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
+    static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
+    static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec);
+    static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed
+
+    static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef);
+    static inline bool osal_mutex_lock (osal_mutex_t sem_hdl, uint32_t msec);
+    static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl);
+
+    static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
+    static inline bool osal_queue_receive(osal_queue_t qhdl, void* data);
+    static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
+    static inline bool osal_queue_empty(osal_queue_t qhdl);
+*/
 //--------------------------------------------------------------------+
 
-#if __GNUC__ && !defined(__ARMCC_VERSION)
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wredundant-decls"
-#endif
-//------------- Semaphore -------------//
-static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
-static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
-static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec);
-
-static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed
-
-//------------- Mutex -------------//
-static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef);
-static inline bool osal_mutex_lock (osal_mutex_t sem_hdl, uint32_t msec);
-static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl);
-
-//------------- Queue -------------//
-static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
-static inline bool osal_queue_receive(osal_queue_t qhdl, void* data);
-static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
-static inline bool osal_queue_empty(osal_queue_t qhdl);
-#if __GNUC__ && !defined(__ARMCC_VERSION)
-#pragma GCC diagnostic pop
-#endif
-
-#if 0  // TODO remove subtask related macros later
-// Sub Task
-#define OSAL_SUBTASK_BEGIN
-#define OSAL_SUBTASK_END                    return TUSB_ERROR_NONE;
-
-#define STASK_RETURN(_error)                return _error;
-#define STASK_INVOKE(_subtask, _status)     (_status) = _subtask
-#define STASK_ASSERT(_cond)                 TU_VERIFY(_cond, TUSB_ERROR_OSAL_TASK_FAILED)
-#endif
-
 #ifdef __cplusplus
  }
 #endif
 
-/** @} */
-
 #endif /* _TUSB_OSAL_H_ */
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index aa102b15c..69a026df5 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -115,7 +115,7 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 //--------------------------------------------------------------------+
 
 // role device/host is used by OS NONE for mutex (disable usb isr) only
-#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
   static _type _name##_##buf[_depth];\
   osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
 
diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h
index 6882329c1..78a257cd6 100644
--- a/src/osal/osal_mynewt.h
+++ b/src/osal/osal_mynewt.h
@@ -96,7 +96,7 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 //--------------------------------------------------------------------+
 
 // role device/host is used by OS NONE for mutex (disable usb isr) only
-#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
   static _type _name##_##buf[_depth];\
   static struct os_event _name##_##evbuf[_depth];\
   osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .evbuf =  _name##_##evbuf};\
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index a1f997cf2..e1dd95c34 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -103,59 +103,34 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 //--------------------------------------------------------------------+
 #include "common/tusb_fifo.h"
 
-// extern to avoid including dcd.h and hcd.h
-#if TUSB_OPT_DEVICE_ENABLED
-extern void dcd_int_disable(uint8_t rhport);
-extern void dcd_int_enable(uint8_t rhport);
-#endif
-
-#if TUSB_OPT_HOST_ENABLED
-extern void hcd_int_disable(uint8_t rhport);
-extern void hcd_int_enable(uint8_t rhport);
-#endif
-
 typedef struct
 {
-    uint8_t role; // device or host
-    tu_fifo_t ff;
+  void (*interrupt_set)(bool);
+  tu_fifo_t ff;
 }osal_queue_def_t;
 
 typedef osal_queue_def_t* osal_queue_t;
 
 // role device/host is used by OS NONE for mutex (disable usb isr) only
-#define OSAL_QUEUE_DEF(_role, _name, _depth, _type)       \
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type)    \
   uint8_t _name##_buf[_depth*sizeof(_type)];              \
   osal_queue_def_t _name = {                              \
-    .role = _role,                                        \
+    .interrupt_set = _int_set,                            \
     .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \
   }
 
 // lock queue by disable USB interrupt
 static inline void _osal_q_lock(osal_queue_t qhdl)
 {
-  (void) qhdl;
-
-#if TUSB_OPT_DEVICE_ENABLED
-  if (qhdl->role == OPT_MODE_DEVICE) dcd_int_disable(TUD_OPT_RHPORT);
-#endif
-
-#if TUSB_OPT_HOST_ENABLED
-  if (qhdl->role == OPT_MODE_HOST) hcd_int_disable(TUH_OPT_RHPORT);
-#endif
+  // disable dcd/hcd interrupt
+  qhdl->interrupt_set(false);
 }
 
 // unlock queue
 static inline void _osal_q_unlock(osal_queue_t qhdl)
 {
-  (void) qhdl;
-
-#if TUSB_OPT_DEVICE_ENABLED
-  if (qhdl->role == OPT_MODE_DEVICE) dcd_int_enable(TUD_OPT_RHPORT);
-#endif
-
-#if TUSB_OPT_HOST_ENABLED
-  if (qhdl->role == OPT_MODE_HOST) hcd_int_enable(TUH_OPT_RHPORT);
-#endif
+  // enable dcd/hcd interrupt
+  qhdl->interrupt_set(true);
 }
 
 static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h
index 1c3366e01..4843d6450 100644
--- a/src/osal/osal_pico.h
+++ b/src/osal/osal_pico.h
@@ -114,7 +114,7 @@ typedef struct
 typedef osal_queue_def_t* osal_queue_t;
 
 // role device/host is used by OS NONE for mutex (disable usb isr) only
-#define OSAL_QUEUE_DEF(_role, _name, _depth, _type)       \
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type)       \
   uint8_t _name##_buf[_depth*sizeof(_type)];              \
   osal_queue_def_t _name = {                              \
     .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \
diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index d5c062ac1..0845175b8 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -90,7 +90,7 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
 //--------------------------------------------------------------------+
 
 // role device/host is used by OS NONE for mutex (disable usb isr) only
-#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
     static _type _name##_##buf[_depth]; \
     osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
 
diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h
index f7e88e322..1856a5d9a 100644
--- a/src/osal/osal_rtx4.h
+++ b/src/osal/osal_rtx4.h
@@ -111,7 +111,7 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 //--------------------------------------------------------------------+
 
 // role device/host is used by OS NONE for mutex (disable usb isr) only
-#define OSAL_QUEUE_DEF(_role, _name, _depth, _type)   \
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type)   \
   os_mbx_declare(_name##__mbox, _depth);              \
   _declare_box(_name##__pool, sizeof(_type), _depth); \
   osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .pool = _name##__pool, .mbox = _name##__mbox };
diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index dfe409383..f2a20accb 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -33,12 +33,13 @@
 #include <nuttx/arch.h>
 
 #include "device/dcd.h"
+#include "device/usbd_pvt.h"
 
 #define CXD56_EPNUM (7)
 #define CXD56_SETUP_QUEUE_DEPTH (4)
 #define CXD56_MAX_DATA_OUT_SIZE (64)
 
-OSAL_QUEUE_DEF(OPT_MODE_DEVICE, _setup_queue_def, CXD56_SETUP_QUEUE_DEPTH, struct usb_ctrlreq_s);
+OSAL_QUEUE_DEF(usbd_int_set, _setup_queue_def, CXD56_SETUP_QUEUE_DEPTH, struct usb_ctrlreq_s);
 
 struct usbdcd_driver_s
 {

From d10326cb4e0f48a05bc39c6f51b7b0fb29427cc9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 23 Feb 2022 21:46:40 +0700
Subject: [PATCH 0826/2085] rename TUSB_OPT_DEVICE_ENABLED to CFG_TUD_ENABLED

TUSB_OPT_DEVICE_ENABLED still usable for backward compatible
---
 hw/bsp/board.h                                       | 2 +-
 hw/bsp/brtmm90x/family.c                             | 6 +++---
 hw/bsp/d5035_01/d5035_01.c                           | 2 +-
 hw/bsp/da14695_dk_usb/da14695_dk_usb.c               | 2 +-
 hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c               | 4 ++--
 hw/bsp/frdm_kl25z/frdm_kl25z.c                       | 2 +-
 hw/bsp/lpcxpresso1769/lpcxpresso1769.c               | 2 +-
 hw/bsp/mbed1768/mbed1768.c                           | 2 +-
 hw/bsp/msp432e4/family.c                             | 4 ++--
 hw/bsp/nrf/family.c                                  | 2 +-
 hw/bsp/rp2040/family.c                               | 2 +-
 hw/bsp/rx/boards/rx65n_target/rx65n_target.c         | 2 +-
 hw/bsp/same54xplainedpro/same54xplainedpro.c         | 2 +-
 hw/bsp/tm4c123/family.c                              | 2 +-
 src/class/audio/audio_device.c                       | 4 ++--
 src/class/bth/bth_device.c                           | 2 +-
 src/class/cdc/cdc_device.c                           | 2 +-
 src/class/dfu/dfu_device.c                           | 2 +-
 src/class/dfu/dfu_rt_device.c                        | 2 +-
 src/class/hid/hid_device.c                           | 2 +-
 src/class/midi/midi_device.c                         | 2 +-
 src/class/msc/msc_device.c                           | 2 +-
 src/class/net/ecm_rndis_device.c                     | 2 +-
 src/class/net/ncm_device.c                           | 2 +-
 src/class/usbtmc/usbtmc_device.c                     | 2 +-
 src/class/vendor/vendor_device.c                     | 2 +-
 src/class/video/video_device.c                       | 2 +-
 src/device/usbd.c                                    | 2 +-
 src/device/usbd_control.c                            | 2 +-
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c             | 2 +-
 src/portable/broadcom/synopsys/dcd_synopsys.c        | 2 +-
 src/portable/chipidea/ci_hs/dcd_ci_hs.c              | 2 +-
 src/portable/dialog/da146xx/dcd_da146xx.c            | 2 +-
 src/portable/espressif/esp32sx/dcd_esp32sx.c         | 2 +-
 src/portable/mentor/musb/dcd_musb.c                  | 2 +-
 src/portable/microchip/pic32mz/dcd_pic32mz.c         | 2 +-
 src/portable/microchip/samd/dcd_samd.c               | 2 +-
 src/portable/microchip/samx7x/dcd_samx7x.c           | 2 +-
 src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c     | 2 +-
 src/portable/nordic/nrf5x/dcd_nrf5x.c                | 2 +-
 src/portable/nuvoton/nuc120/dcd_nuc120.c             | 2 +-
 src/portable/nuvoton/nuc121/dcd_nuc121.c             | 2 +-
 src/portable/nuvoton/nuc505/dcd_nuc505.c             | 2 +-
 src/portable/nxp/khci/dcd_khci.c                     | 2 +-
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c             | 2 +-
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c         | 2 +-
 src/portable/nxp/transdimension/dcd_transdimension.c | 2 +-
 src/portable/raspberrypi/rp2040/dcd_rp2040.c         | 2 +-
 src/portable/renesas/usba/dcd_usba.c                 | 2 +-
 src/portable/sony/cxd56/dcd_cxd56.c                  | 2 +-
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c        | 2 +-
 src/portable/st/synopsys/dcd_synopsys.c              | 2 +-
 src/portable/sunxi/dcd_sunxi_musb.c                  | 2 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c                | 2 +-
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c          | 2 +-
 src/portable/valentyusb/eptri/dcd_eptri.c            | 2 +-
 src/tusb.c                                           | 8 ++++----
 src/tusb.h                                           | 2 +-
 src/tusb_option.h                                    | 5 ++++-
 59 files changed, 70 insertions(+), 67 deletions(-)

diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index 782e0939c..b4e0cb298 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -120,7 +120,7 @@ static inline void board_delay(uint32_t ms)
   uint32_t start_ms = board_millis();
   while (board_millis() - start_ms < ms)
   {
-    #if TUSB_OPT_DEVICE_ENABLED
+    #if CFG_TUD_ENABLED
     // take chance to run usb background
     tud_task();
     #endif
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 803a62a95..6b3c1f56c 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -30,7 +30,7 @@
 #include <registers/ft900_registers.h>
 #include <ft900.h>
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
 int8_t board_ft90x_vbus(void); // Board specific implementation of VBUS detection for USB device.
 extern void ft90x_usbd_pm_ISR(uint16_t pmcfg); // Interrupt handler for USB device power management
 #endif
@@ -152,14 +152,14 @@ void board_pm_ISR(void)
               MASK_SYS_PMCFG_HOST_RESUME_DEV)
     )
     {
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
         ft90x_usbd_pm_ISR(pmcfg);
 #endif
     }
 #endif
 }
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
 int8_t board_ft90x_vbus(void)
 {
 	return gpio_read(USBD_VBUS_DTC_PIN);
diff --git a/hw/bsp/d5035_01/d5035_01.c b/hw/bsp/d5035_01/d5035_01.c
index 5685ff16f..f356851f7 100644
--- a/hw/bsp/d5035_01/d5035_01.c
+++ b/hw/bsp/d5035_01/d5035_01.c
@@ -270,7 +270,7 @@ void board_init(void)
 #endif
 
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
 #if CFG_TUSB_DEBUG >= 2
 	uart_send_str(BOARD_NAME " USB device enabled\n");
 #endif
diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
index 95fe70d01..a4d996810 100644
--- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
@@ -73,7 +73,7 @@ void board_init(void)
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   // This board is USB powered there is no need to monitor
   // VBUS line.  Notify driver that VBUS is present.
   tusb_vbus_changed(true);
diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
index 0441c000c..13113fb95 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
+++ b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
@@ -36,7 +36,7 @@ void USB_IRQHandler(void)
   tud_int_handler(0);
 }
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
 // DA146xx driver function that must be called whenever VBUS changes
 extern void tusb_vbus_changed(bool present);
 
@@ -85,7 +85,7 @@ void board_init(void)
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   // Setup interrupt for both connect and disconnect
   CRG_TOP->VBUS_IRQ_MASK_REG = CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk |
                                CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk;
diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c
index 2930ed56e..5f2a5b23d 100644
--- a/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c
@@ -42,7 +42,7 @@ void USB0_IRQHandler(void)
 #if TUSB_OPT_HOST_ENABLED
   tuh_int_handler(0);
 #endif
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   tud_int_handler(0);
 #endif
 }
diff --git a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
index 101cc8a4c..e62544390 100644
--- a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
+++ b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
@@ -156,7 +156,7 @@ void board_init(void)
 //    0x1B // Host + Device + OTG + AHB
   };
 
-  uint32_t const clk_en = TUSB_OPT_DEVICE_ENABLED ? USBCLK_DEVCIE : USBCLK_HOST;
+  uint32_t const clk_en = CFG_TUD_ENABLED ? USBCLK_DEVCIE : USBCLK_HOST;
 
   LPC_USB->OTGClkCtrl = clk_en;
   while ( (LPC_USB->OTGClkSt & clk_en) != clk_en );
diff --git a/hw/bsp/mbed1768/mbed1768.c b/hw/bsp/mbed1768/mbed1768.c
index 5495ed166..85dffde77 100644
--- a/hw/bsp/mbed1768/mbed1768.c
+++ b/hw/bsp/mbed1768/mbed1768.c
@@ -130,7 +130,7 @@ void board_init(void)
 //    0x1B // Host + Device + OTG + AHB
   };
 
-  uint32_t const clk_en = TUSB_OPT_DEVICE_ENABLED ? USBCLK_DEVCIE : USBCLK_HOST;
+  uint32_t const clk_en = CFG_TUD_ENABLED ? USBCLK_DEVCIE : USBCLK_HOST;
 
   LPC_USB->OTGClkCtrl = clk_en;
   while ( (LPC_USB->OTGClkSt & clk_en) != clk_en );
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index 262dc1d30..d553b362e 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -36,7 +36,7 @@ void USB0_IRQHandler(void)
 #if TUSB_OPT_HOST_ENABLED
   tuh_int_handler(0);
 #endif
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   tud_int_handler(0);
 #endif
 }
@@ -148,7 +148,7 @@ void board_init(void)
   USB0->GPCS = USB_GPCS_DEVMOD_OTG;
   USB0->EPC  = USB_EPC_EPENDE | USB_EPC_EPEN_HIGH;
 #endif
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   USB0->GPCS = USB_GPCS_DEVMOD_DEVVBUS;
 #endif
 }
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index ed742daaf..a07332d4c 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -100,7 +100,7 @@ void board_init(void)
   nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler);
 
   //------------- USB -------------//
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   // Priorities 0, 1, 4 (nRF52) are reserved for SoftDevice
   // 2 is highest for application
   NVIC_SetPriority(USBD_IRQn, 2);
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 10ead2776..6d0f7ed38 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -138,7 +138,7 @@ void board_init(void)
 #endif
 
   // todo probably set up device mode?
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
 
 #endif
 
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index d658ee5dd..56bf575b2 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -179,7 +179,7 @@ void INT_Excep_USB0_USBI0(void)
 #if TUSB_OPT_HOST_ENABLED
   tuh_int_handler(0);
 #endif
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   tud_int_handler(0);
 #endif
 }
diff --git a/hw/bsp/same54xplainedpro/same54xplainedpro.c b/hw/bsp/same54xplainedpro/same54xplainedpro.c
index 4c38fc6eb..ba1eec38b 100644
--- a/hw/bsp/same54xplainedpro/same54xplainedpro.c
+++ b/hw/bsp/same54xplainedpro/same54xplainedpro.c
@@ -223,7 +223,7 @@ void board_init(void)
 #endif
 
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
 #if CFG_TUSB_DEBUG >= 2
 	uart_send_str(BOARD_NAME " USB device enabled\n");
 #endif
diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c
index 449781ce1..1e19e7f43 100644
--- a/hw/bsp/tm4c123/family.c
+++ b/hw/bsp/tm4c123/family.c
@@ -11,7 +11,7 @@ void USB0_Handler(void)
   tuh_int_handler(0);
 #endif
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   tud_int_handler(0);
 #endif
 }
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index d21980060..06979b09e 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -50,7 +50,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_AUDIO)
+#if (CFG_TUD_ENABLED && CFG_TUD_AUDIO)
 
 //--------------------------------------------------------------------+
 // INCLUDE
@@ -2291,4 +2291,4 @@ uint8_t audiod_get_audio_fct_idx(audiod_function_t * audio)
   return 0;
 }
 
-#endif //TUSB_OPT_DEVICE_ENABLED && CFG_TUD_AUDIO
+#endif //CFG_TUD_ENABLED && CFG_TUD_AUDIO
diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index 8ef609622..f40bfbd0d 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_BTH)
+#if (CFG_TUD_ENABLED && CFG_TUD_BTH)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 08f2af253..2b9b84e7a 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_CDC)
+#if (CFG_TUD_ENABLED && CFG_TUD_CDC)
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index ddfa608e4..8d859d2ee 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_DFU)
+#if (CFG_TUD_ENABLED && CFG_TUD_DFU)
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/class/dfu/dfu_rt_device.c b/src/class/dfu/dfu_rt_device.c
index afee2aa1f..b9cd6096b 100644
--- a/src/class/dfu/dfu_rt_device.c
+++ b/src/class/dfu/dfu_rt_device.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_DFU_RUNTIME)
+#if (CFG_TUD_ENABLED && CFG_TUD_DFU_RUNTIME)
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 588b61254..562ca7f36 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_HID)
+#if (CFG_TUD_ENABLED && CFG_TUD_HID)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index b08b362f9..2ce1376bd 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_MIDI)
+#if (CFG_TUD_ENABLED && CFG_TUD_MIDI)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index e09a2b11a..318947a67 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_MSC)
+#if (CFG_TUD_ENABLED && CFG_TUD_MSC)
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index c6cd388e3..f6b318058 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_ECM_RNDIS )
+#if ( CFG_TUD_ENABLED && CFG_TUD_ECM_RNDIS )
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 3e131a85c..1987337f8 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -28,7 +28,7 @@
 
 #include "tusb_option.h"
 
-#if ( TUSB_OPT_DEVICE_ENABLED && CFG_TUD_NCM )
+#if ( CFG_TUD_ENABLED && CFG_TUD_NCM )
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 26be987cf..b02b07575 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -68,7 +68,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_USBTMC)
+#if (CFG_TUD_ENABLED && CFG_TUD_USBTMC)
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 8a4ca1d2e..394b39b27 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_VENDOR)
+#if (CFG_TUD_ENABLED && CFG_TUD_VENDOR)
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index eeb068197..91718f205 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_VIDEO && CFG_TUD_VIDEO_STREAMING)
+#if (CFG_TUD_ENABLED && CFG_TUD_VIDEO && CFG_TUD_VIDEO_STREAMING)
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 37ca9822f..e6861ee0a 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
 
 #include "tusb.h"
 #include "device/usbd.h"
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 7a8244699..4f4108090 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
 
 #include "tusb.h"
 #include "device/usbd_pvt.h"
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index d46723caa..791f6cf60 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -31,7 +31,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && \
+#if CFG_TUD_ENABLED && \
   (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X) 
 
 #include <stdint.h>
diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c
index 494bb70ee..c4881ee50 100644
--- a/src/portable/broadcom/synopsys/dcd_synopsys.c
+++ b/src/portable/broadcom/synopsys/dcd_synopsys.c
@@ -29,7 +29,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED &&         \
+#if CFG_TUD_ENABLED &&         \
     (CFG_TUSB_MCU == OPT_MCU_BCM2711 ) \
 
 
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index c943396fc..ffb2ebd16 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -27,7 +27,7 @@
 #include "tusb_option.h"
 #include "device/dcd_attr.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && defined(DCD_ATTR_CONTROLLER_CHIPIDEA_HS)
+#if CFG_TUD_ENABLED && defined(DCD_ATTR_CONTROLLER_CHIPIDEA_HS)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 02fad8165..919249a09 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_DA1469X
+#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_DA1469X
 
 #include "mcu/mcu.h"
 
diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index a9c311324..99cd08e4d 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -28,7 +28,7 @@
 
 #include "tusb_option.h"
 
-#if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2) ||  (CFG_TUSB_MCU == OPT_MCU_ESP32S3)) && TUSB_OPT_DEVICE_ENABLED)
+#if (((CFG_TUSB_MCU == OPT_MCU_ESP32S2) ||  (CFG_TUSB_MCU == OPT_MCU_ESP32S3)) && CFG_TUD_ENABLED)
 
 // Espressif
 #include "freertos/xtensa_api.h"
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index f6e05e134..71414e737 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && \
+#if CFG_TUD_ENABLED && \
   TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
 
 #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c
index 740e5edbb..7d48f755b 100644
--- a/src/portable/microchip/pic32mz/dcd_pic32mz.c
+++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_PIC32MZ
+#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_PIC32MZ
 
 #include <common/tusb_common.h>
 #include <device/dcd.h>
diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index 46aabc5aa..c4ee6f2f5 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && \
+#if CFG_TUD_ENABLED && \
     (CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
      CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
      CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21)
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 9e3b43840..a82f29a88 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMX7X
+#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMX7X
 
 #include "device/dcd.h"
 #include "sam.h"
diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
index a3b69b987..1edcd8458 100644
--- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MM32F327X )
+#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MM32F327X )
 
 #include "reg_usb_otg_fs.h"
 #include "mm32_device.h"
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 024ea0d90..bc145eaa4 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_NRF5X
+#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_NRF5X
 
 #include "nrf.h"
 #include "nrf_clock.h"
diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c
index 0d45090d1..694766613 100644
--- a/src/portable/nuvoton/nuc120/dcd_nuc120.c
+++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c
@@ -35,7 +35,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_NUC120)
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_NUC120)
 
 #include "device/dcd.h"
 #include "NUC100Series.h"
diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index fc7150508..88d514bce 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -35,7 +35,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && ( (CFG_TUSB_MCU == OPT_MCU_NUC121) || (CFG_TUSB_MCU == OPT_MCU_NUC126) )
+#if CFG_TUD_ENABLED && ( (CFG_TUSB_MCU == OPT_MCU_NUC121) || (CFG_TUSB_MCU == OPT_MCU_NUC126) )
 
 #include "device/dcd.h"
 #include "NuMicro.h"
diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c
index aefb09f4e..498977561 100644
--- a/src/portable/nuvoton/nuc505/dcd_nuc505.c
+++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c
@@ -35,7 +35,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_NUC505)
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_NUC505)
 
 #include "device/dcd.h"
 #include "NUC505Series.h"
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 8de924f90..4c7737103 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && ( \
+#if CFG_TUD_ENABLED && ( \
       ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \
     )
 
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 0f500a88f..d2cce2db3 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && \
+#if CFG_TUD_ENABLED && \
     (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
 
 #include "device/dcd.h"
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 1bdf72d6d..55d872dc0 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -34,7 +34,7 @@
  * - LPC54114
  * - LPC55s69
  */
-#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_LPC11UXX || \
+#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_LPC11UXX || \
                                  CFG_TUSB_MCU == OPT_MCU_LPC13XX  || \
                                  CFG_TUSB_MCU == OPT_MCU_LPC15XX  || \
                                  CFG_TUSB_MCU == OPT_MCU_LPC51UXX || \
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index f6433293d..9f5979ab4 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && \
+#if CFG_TUD_ENABLED && \
     (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
 
 #warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly"
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 42add3167..915822798 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_RP2040
+#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_RP2040
 
 #include "pico.h"
 #include "rp2040_usb.h"
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index ae7d2fd0c..eb3541af4 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -31,7 +31,7 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
+#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
                                  CFG_TUSB_MCU == OPT_MCU_RX65X || \
                                  CFG_TUSB_MCU == OPT_MCU_RX72N )
 #include "device/dcd.h"
diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index f2a20accb..fbea03b1d 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_CXD56
+#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_CXD56
 
 #include <errno.h>
 #include <nuttx/usb/usbdev.h>
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 177a7ad2a..f201a02cf 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -109,7 +109,7 @@
 #define STM32F1_FSDEV
 #endif
 
-#if TUSB_OPT_DEVICE_ENABLED && \
+#if CFG_TUD_ENABLED && \
       ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4) || \
         (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) \
       )
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index 4782ead8c..d7f659340 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -45,7 +45,7 @@
 #define STM32L4_SYNOPSYS
 #endif
 
-#if TUSB_OPT_DEVICE_ENABLED &&                                          \
+#if CFG_TUD_ENABLED &&                                          \
     ( (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \
        CFG_TUSB_MCU == OPT_MCU_STM32F2                               || \
        CFG_TUSB_MCU == OPT_MCU_STM32F4                               || \
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index cf93c9bc4..447069f88 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -29,7 +29,7 @@
 #include <stdint.h>
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_F1C100S
+#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_F1C100S
 
 #include "osal/osal.h"
 #include <f1c100s-irq.h>
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 188611743..86dc760c8 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -30,7 +30,7 @@
 #include "tusb_option.h"
 #include "device/dcd_attr.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && \
+#if CFG_TUD_ENABLED && \
     ( defined(DCD_ATTR_DWC2_STM32) || \
       TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) || \
       TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711, OPT_MCU_BCM2835) || \
diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index 3b91f2798..c3b3b2403 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MSP430x5xx )
+#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MSP430x5xx )
 
 #include "msp430.h"
 #include "device/dcd.h"
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c
index 51fb8b401..dfadfdcb3 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.c
+++ b/src/portable/valentyusb/eptri/dcd_eptri.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_DEVICE_ENABLED && (CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI)
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI)
 
 #ifndef DEBUG
 #define DEBUG 0
diff --git a/src/tusb.c b/src/tusb.c
index 9583f509d..cad434a92 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -26,18 +26,18 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_HOST_ENABLED || TUSB_OPT_DEVICE_ENABLED
+#if TUSB_OPT_HOST_ENABLED || CFG_TUD_ENABLED
 
 #include "tusb.h"
 
 // TODO clean up
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
 #include "device/usbd_pvt.h"
 #endif
 
 bool tusb_init(void)
 {
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   TU_ASSERT ( tud_init(TUD_OPT_RHPORT) ); // init device stack
 #endif
 
@@ -52,7 +52,7 @@ bool tusb_inited(void)
 {
   bool ret = false;
 
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   ret = ret || tud_inited();
 #endif
 
diff --git a/src/tusb.h b/src/tusb.h
index 0d29e106c..2ffc1f681 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -61,7 +61,7 @@
 #endif
 
 //------------- DEVICE -------------//
-#if TUSB_OPT_DEVICE_ENABLED
+#if CFG_TUD_ENABLED
   #include "device/usbd.h"
 
   #if CFG_TUD_HID
diff --git a/src/tusb_option.h b/src/tusb_option.h
index cb49c85ce..0e88c1507 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -215,7 +215,10 @@
 #define TUD_OPT_HIGH_SPEED      ( (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HIGH_SPEED )
 #endif
 
-#define TUSB_OPT_DEVICE_ENABLED ( TUD_OPT_RHPORT >= 0 )
+#define CFG_TUD_ENABLED ( TUD_OPT_RHPORT >= 0 )
+
+// For backward compatible
+#define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED
 
 //--------------------------------------------------------------------+
 // COMMON OPTIONS

From 31aa077cb0b345464548b9cb2e2913227348a969 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 23 Feb 2022 21:49:11 +0700
Subject: [PATCH 0827/2085] rename TUSB_OPT_HOST_ENABLED to CFG_TUH_ENABLED

---
 hw/bsp/frdm_kl25z/frdm_kl25z.c                  |  2 +-
 hw/bsp/lpcxpresso1769/lpcxpresso1769.c          |  2 +-
 hw/bsp/mbed1768/mbed1768.c                      |  2 +-
 hw/bsp/msp432e4/family.c                        |  6 +++---
 hw/bsp/rp2040/family.c                          |  2 +-
 hw/bsp/rx/boards/rx65n_target/rx65n_target.c    |  2 +-
 hw/bsp/tm4c123/family.c                         |  2 +-
 src/class/cdc/cdc_host.c                        |  2 +-
 src/class/cdc/cdc_rndis_host.c                  |  2 +-
 src/class/hid/hid_host.c                        |  2 +-
 src/class/msc/msc_host.c                        |  2 +-
 src/class/vendor/vendor_host.c                  |  2 +-
 src/host/hcd.h                                  |  2 +-
 src/host/hub.c                                  |  2 +-
 src/host/usbh.c                                 |  2 +-
 src/host/usbh_control.c                         |  2 +-
 src/osal/osal_pico.h                            |  2 +-
 src/portable/chipidea/ci_hs/hcd_ci_hs.c         |  2 +-
 src/portable/ehci/ehci.c                        |  2 +-
 src/portable/mentor/musb/hcd_musb.c             |  2 +-
 src/portable/nxp/khci/hcd_khci.c                |  2 +-
 src/portable/nxp/lpc17_40/hcd_lpc17_40.c        |  2 +-
 .../nxp/transdimension/hcd_transdimension.c     |  2 +-
 src/portable/ohci/ohci.c                        |  2 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c    |  2 +-
 src/portable/raspberrypi/rp2040/rp2040_usb.c    |  2 +-
 src/portable/raspberrypi/rp2040/rp2040_usb.h    |  2 +-
 src/portable/renesas/usba/hcd_usba.c            |  2 +-
 src/tusb.c                                      |  6 +++---
 src/tusb.h                                      |  2 +-
 src/tusb_option.h                               | 17 ++++++++---------
 31 files changed, 42 insertions(+), 43 deletions(-)

diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c
index 5f2a5b23d..8d93fdbaa 100644
--- a/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c
@@ -39,7 +39,7 @@
 //--------------------------------------------------------------------+
 void USB0_IRQHandler(void)
 {
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   tuh_int_handler(0);
 #endif
 #if CFG_TUD_ENABLED
diff --git a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
index e62544390..b82e5ffe0 100644
--- a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
+++ b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
@@ -161,7 +161,7 @@ void board_init(void)
   LPC_USB->OTGClkCtrl = clk_en;
   while ( (LPC_USB->OTGClkSt & clk_en) != clk_en );
 
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   // set portfunc to host !!!
   LPC_USB->StCtrl = 0x3; // should be 1
 #endif
diff --git a/hw/bsp/mbed1768/mbed1768.c b/hw/bsp/mbed1768/mbed1768.c
index 85dffde77..7c2b37016 100644
--- a/hw/bsp/mbed1768/mbed1768.c
+++ b/hw/bsp/mbed1768/mbed1768.c
@@ -135,7 +135,7 @@ void board_init(void)
   LPC_USB->OTGClkCtrl = clk_en;
   while ( (LPC_USB->OTGClkSt & clk_en) != clk_en );
 
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   // set portfunc to host !!!
   LPC_USB->StCtrl = 0x3; // should be 1
 #endif
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index d553b362e..3d2d4085e 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -33,7 +33,7 @@
 //--------------------------------------------------------------------+
 void USB0_IRQHandler(void)
 {
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   tuh_int_handler(0);
 #endif
 #if CFG_TUD_ENABLED
@@ -123,7 +123,7 @@ void board_init(void)
   GPIOB->AMSEL      = TU_BIT(0) | TU_BIT(1);
   GPIOL->AMSEL      = TU_BIT(6) | TU_BIT(7);
 
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   /* USB PD6(EPEN) */
   bits              = TU_BIT(3);
   SYSCTL->RCGCGPIO |= bits;
@@ -144,7 +144,7 @@ void board_init(void)
 
   USB0->CC          = USB_CC_CLKEN | (3u << USB_CC_CLKDIV_S); /* 60MHz = 240MHz / 4 */
   __DMB(); /* Wait for completion of opening of the clock gate */
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   USB0->GPCS = USB_GPCS_DEVMOD_OTG;
   USB0->EPC  = USB_EPC_EPENDE | USB_EPC_EPEN_HIGH;
 #endif
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 6d0f7ed38..fa63dadf5 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -142,7 +142,7 @@ void board_init(void)
 
 #endif
 
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   // set portfunc to host !!!
 #endif
 }
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index 56bf575b2..f189e40e4 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -176,7 +176,7 @@ void INT_Excep_SCI5_RXI5(void)
 //--------------------------------------------------------------------+
 void INT_Excep_USB0_USBI0(void)
 {
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   tuh_int_handler(0);
 #endif
 #if CFG_TUD_ENABLED
diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c
index 1e19e7f43..b0947d6c4 100644
--- a/hw/bsp/tm4c123/family.c
+++ b/hw/bsp/tm4c123/family.c
@@ -7,7 +7,7 @@
 //--------------------------------------------------------------------+
 void USB0_Handler(void)
 {
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   tuh_int_handler(0);
 #endif
 
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index f4fb6c1d6..c18234db4 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_CDC)
+#if (CFG_TUH_ENABLED && CFG_TUH_CDC)
 
 #include "host/usbh.h"
 #include "host/usbh_classdriver.h"
diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c
index d41cf91ac..8f28f51ac 100644
--- a/src/class/cdc/cdc_rndis_host.c
+++ b/src/class/cdc/cdc_rndis_host.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_CDC && CFG_TUH_CDC_RNDIS)
+#if (CFG_TUH_ENABLED && CFG_TUH_CDC && CFG_TUH_CDC_RNDIS)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index f19f1ba81..542ed5772 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_HID)
+#if (CFG_TUH_ENABLED && CFG_TUH_HID)
 
 #include "host/usbh.h"
 #include "host/usbh_classdriver.h"
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index fa6519956..a49a10522 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_HOST_ENABLED & CFG_TUH_MSC
+#if CFG_TUH_ENABLED & CFG_TUH_MSC
 
 #include "host/usbh.h"
 #include "host/usbh_classdriver.h"
diff --git a/src/class/vendor/vendor_host.c b/src/class/vendor/vendor_host.c
index 1e28e9af4..dbea1228d 100644
--- a/src/class/vendor/vendor_host.c
+++ b/src/class/vendor/vendor_host.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_VENDOR)
+#if (CFG_TUH_ENABLED && CFG_TUH_VENDOR)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/host/hcd.h b/src/host/hcd.h
index eb53d2e80..054fd9647 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -82,7 +82,7 @@ typedef struct
 
 } hcd_event_t;
 
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
 // Max number of endpoints per device
 enum {
   // TODO better computation
diff --git a/src/host/hub.c b/src/host/hub.c
index fd4dbd04a..53eb1d521 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_HUB)
+#if (CFG_TUH_ENABLED && CFG_TUH_HUB)
 
 #include "usbh.h"
 #include "usbh_classdriver.h"
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 9854b75a3..e29ce1e54 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
 
 #include "tusb.h"
 #include "host/usbh.h"
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index 9204576ac..d034eec7f 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
 
 #include "tusb.h"
 #include "usbh_classdriver.h"
diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h
index 4843d6450..70432d22b 100644
--- a/src/osal/osal_pico.h
+++ b/src/osal/osal_pico.h
@@ -100,7 +100,7 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 //--------------------------------------------------------------------+
 #include "common/tusb_fifo.h"
 
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
 extern void hcd_int_disable(uint8_t rhport);
 extern void hcd_int_enable(uint8_t rhport);
 #endif
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 3d028bf32..0754b477e 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -28,7 +28,7 @@
 
 // Chipidea Highspeed USB IP implement EHCI for host functionality
 
-#if TUSB_OPT_HOST_ENABLED && \
+#if CFG_TUH_ENABLED && \
     (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index e92f8a951..6b86cb2b2 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -26,7 +26,7 @@
 
 #include "host/hcd_attr.h"
 
-#if TUSB_OPT_HOST_ENABLED && defined(HCD_ATTR_EHCI_TRANSDIMENSION)
+#if CFG_TUH_ENABLED && defined(HCD_ATTR_EHCI_TRANSDIMENSION)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index acccb7674..3bfd65b45 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_HOST_ENABLED && \
+#if CFG_TUH_ENABLED && \
   TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
 
 #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED)
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 92ec04d4a..fc0875cfe 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_HOST_ENABLED && ( \
+#if CFG_TUH_ENABLED && ( \
       ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \
     )
 
diff --git a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
index 1c1faed94..ad9ed59b4 100644
--- a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_HOST_ENABLED && \
+#if CFG_TUH_ENABLED && \
     (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
 
 #include "chip.h"
diff --git a/src/portable/nxp/transdimension/hcd_transdimension.c b/src/portable/nxp/transdimension/hcd_transdimension.c
index 81ad3152d..2d0830981 100644
--- a/src/portable/nxp/transdimension/hcd_transdimension.c
+++ b/src/portable/nxp/transdimension/hcd_transdimension.c
@@ -28,7 +28,7 @@
 
 // NXP Trans-Dimension USB IP implement EHCI for host functionality
 
-#if TUSB_OPT_HOST_ENABLED && \
+#if CFG_TUH_ENABLED && \
     (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
 
 #warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly"
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index daa8075b7..8860f27a2 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -26,7 +26,7 @@
 
 #include "host/hcd_attr.h"
 
-#if TUSB_OPT_HOST_ENABLED && defined(HCD_ATTR_OHCI)
+#if CFG_TUH_ENABLED && defined(HCD_ATTR_OHCI)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 3e80dd872..b6fbdb200 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_HOST_ENABLED && CFG_TUSB_MCU == OPT_MCU_RP2040
+#if CFG_TUH_ENABLED && CFG_TUSB_MCU == OPT_MCU_RP2040
 
 #include "pico.h"
 #include "rp2040_usb.h"
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 9d833e65f..293cefaf6 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -87,7 +87,7 @@ void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_m
             *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
             // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz)
             // Don't need delay in host mode as host is in charge
-#if !TUSB_OPT_HOST_ENABLED
+#if !CFG_TUH_ENABLED
             __asm volatile (
                     "b 1f\n"
                     "1: b 1f\n"
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index a9cf1dd07..da1933ddd 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -56,7 +56,7 @@ typedef struct hw_endpoint
     // Interrupt, bulk, etc
     uint8_t transfer_type;
     
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
     // Only needed for host
     uint8_t dev_addr;
 
diff --git a/src/portable/renesas/usba/hcd_usba.c b/src/portable/renesas/usba/hcd_usba.c
index 35eb060cd..ebb682342 100644
--- a/src/portable/renesas/usba/hcd_usba.c
+++ b/src/portable/renesas/usba/hcd_usba.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_HOST_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
+#if CFG_TUH_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
                                CFG_TUSB_MCU == OPT_MCU_RX65X || \
                                CFG_TUSB_MCU == OPT_MCU_RX72N )
 #include "host/hcd.h"
diff --git a/src/tusb.c b/src/tusb.c
index cad434a92..03fe43104 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if TUSB_OPT_HOST_ENABLED || CFG_TUD_ENABLED
+#if CFG_TUH_ENABLED || CFG_TUD_ENABLED
 
 #include "tusb.h"
 
@@ -41,7 +41,7 @@ bool tusb_init(void)
   TU_ASSERT ( tud_init(TUD_OPT_RHPORT) ); // init device stack
 #endif
 
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   TU_ASSERT( tuh_init(TUH_OPT_RHPORT) ); // init host stack
 #endif
 
@@ -56,7 +56,7 @@ bool tusb_inited(void)
   ret = ret || tud_inited();
 #endif
 
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   ret = ret || tuh_inited();
 #endif
 
diff --git a/src/tusb.h b/src/tusb.h
index 2ffc1f681..549f00b43 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -39,7 +39,7 @@
 #include "common/tusb_fifo.h"
 
 //------------- HOST -------------//
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   #include "host/usbh.h"
 
   #if CFG_TUH_HID
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 0e88c1507..714c6ed9e 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -187,12 +187,10 @@
 #define OPT_MODE_LOW_SPEED    0x10 ///< Max Low Speed
 #define OPT_MODE_HIGH_SPEED   0x20 ///< Max High Speed
 
-
 #ifndef CFG_TUSB_RHPORT0_MODE
   #define CFG_TUSB_RHPORT0_MODE OPT_MODE_NONE
 #endif
 
-
 #ifndef CFG_TUSB_RHPORT1_MODE
   #define CFG_TUSB_RHPORT1_MODE OPT_MODE_NONE
 #endif
@@ -203,22 +201,23 @@
 #endif
 
 // Which roothub port is configured as host
-#define TUH_OPT_RHPORT          ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST) ? 1 : -1) )
-#define TUSB_OPT_HOST_ENABLED   ( TUH_OPT_RHPORT >= 0 )
+#define TUH_OPT_RHPORT      ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST) ? 1 : -1) )
+#define CFG_TUH_ENABLED     ( TUH_OPT_RHPORT >= 0 )
 
 // Which roothub port is configured as device
-#define TUD_OPT_RHPORT          ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE) ? 1 : -1) )
+#define TUD_OPT_RHPORT      ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE) ? 1 : -1) )
 
 #if TUD_OPT_RHPORT == 0
-#define TUD_OPT_HIGH_SPEED      ( (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HIGH_SPEED )
+#define TUD_OPT_HIGH_SPEED  ( (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HIGH_SPEED )
 #else
-#define TUD_OPT_HIGH_SPEED      ( (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HIGH_SPEED )
+#define TUD_OPT_HIGH_SPEED  ( (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HIGH_SPEED )
 #endif
 
 #define CFG_TUD_ENABLED ( TUD_OPT_RHPORT >= 0 )
 
 // For backward compatible
 #define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED
+#define TUSB_OPT_HOST_ENABLED   CFG_TUH_ENABLED
 
 //--------------------------------------------------------------------+
 // COMMON OPTIONS
@@ -316,7 +315,7 @@
 //--------------------------------------------------------------------
 // HOST OPTIONS
 //--------------------------------------------------------------------
-#if TUSB_OPT_HOST_ENABLED
+#if CFG_TUH_ENABLED
   #ifndef CFG_TUH_DEVICE_MAX
     #define CFG_TUH_DEVICE_MAX 1
   #endif
@@ -324,7 +323,7 @@
   #ifndef CFG_TUH_ENUMERATION_BUFSIZE
     #define CFG_TUH_ENUMERATION_BUFSIZE 256
   #endif
-#endif // TUSB_OPT_HOST_ENABLED
+#endif // CFG_TUH_ENABLED
 
 //------------- CLASS -------------//
 

From a8af609dfef0f82ce22e6f0bf48146b4b2433633 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Feb 2022 13:00:05 +0700
Subject: [PATCH 0828/2085] auto detect max rhport speed based on mcu

---
 .../audio_4_channel_mic/src/tusb_config.h     |  4 --
 examples/device/audio_test/src/tusb_config.h  |  4 --
 .../device/cdc_dual_ports/src/tusb_config.h   |  9 +---
 examples/device/cdc_msc/src/tusb_config.h     | 10 +---
 examples/device/dfu/src/tusb_config.h         |  9 +---
 examples/device/dfu_runtime/src/tusb_config.h |  9 +---
 .../dynamic_configuration/src/tusb_config.h   |  9 +---
 .../hid_boot_interface/src/tusb_config.h      | 10 +---
 .../device/hid_composite/src/tusb_config.h    | 10 +---
 .../hid_composite_freertos/src/tusb_config.h  |  9 +---
 .../hid_generic_inout/src/tusb_config.h       |  9 +---
 .../hid_multiple_interface/src/tusb_config.h  | 10 +---
 examples/device/midi_test/src/tusb_config.h   | 10 +---
 .../device/msc_dual_lun/src/tusb_config.h     |  9 +---
 .../net_lwip_webserver/src/tusb_config.h      |  9 +---
 .../device/uac2_headset/src/tusb_config.h     |  8 ++--
 examples/device/usbtmc/src/tusb_config.h      |  9 +---
 .../device/video_capture/src/tusb_config.h    |  9 +---
 .../device/webusb_serial/src/tusb_config.h    |  9 +---
 src/device/dcd_attr.h                         | 33 ++++++++-----
 src/device/usbd.h                             |  8 ++--
 src/tusb_option.h                             | 47 ++++++++++++-------
 22 files changed, 90 insertions(+), 163 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index 44be5a0d7..023faa7e2 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -39,11 +39,7 @@ extern "C" {
 #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-#define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
-#else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE
-#endif
 
 #ifndef CFG_TUSB_OS
 #define CFG_TUSB_OS                 OPT_OS_NONE
diff --git a/examples/device/audio_test/src/tusb_config.h b/examples/device/audio_test/src/tusb_config.h
index 683a1a567..9b8514265 100644
--- a/examples/device/audio_test/src/tusb_config.h
+++ b/examples/device/audio_test/src/tusb_config.h
@@ -39,11 +39,7 @@ extern "C" {
 #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-#define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
-#else
 #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE
-#endif
 
 #ifndef CFG_TUSB_OS
 #define CFG_TUSB_OS                 OPT_OS_NONE
diff --git a/examples/device/cdc_dual_ports/src/tusb_config.h b/examples/device/cdc_dual_ports/src/tusb_config.h
index ff8535d1a..f93606092 100644
--- a/examples/device/cdc_dual_ports/src/tusb_config.h
+++ b/examples/device/cdc_dual_ports/src/tusb_config.h
@@ -45,14 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index e74e80541..6507cef19 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -45,15 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
-      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) ||\
-      TU_CHECK_MCU(OPT_MCU_FT90X, OPT_MCU_FT93X)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 012d50019..d4779b2e1 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -27,14 +27,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/dfu_runtime/src/tusb_config.h b/examples/device/dfu_runtime/src/tusb_config.h
index bdae1d2e9..e15ae7997 100644
--- a/examples/device/dfu_runtime/src/tusb_config.h
+++ b/examples/device/dfu_runtime/src/tusb_config.h
@@ -27,14 +27,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/dynamic_configuration/src/tusb_config.h b/examples/device/dynamic_configuration/src/tusb_config.h
index 23073faf3..ddc295dcc 100644
--- a/examples/device/dynamic_configuration/src/tusb_config.h
+++ b/examples/device/dynamic_configuration/src/tusb_config.h
@@ -45,14 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/hid_boot_interface/src/tusb_config.h b/examples/device/hid_boot_interface/src/tusb_config.h
index 1381dd6b2..1c8fa40b2 100644
--- a/examples/device/hid_boot_interface/src/tusb_config.h
+++ b/examples/device/hid_boot_interface/src/tusb_config.h
@@ -45,15 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || CFG_TUSB_MCU == OPT_MCU_SAMX7X || \
-       CFG_TUSB_MCU == OPT_MCU_FT90X   || CFG_TUSB_MCU == OPT_MCU_FT93X)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index 449efbc7e..d0f2b513f 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -45,15 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
-      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) ||\
-      TU_CHECK_MCU(OPT_MCU_FT90X, OPT_MCU_FT93X)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index 062f32ac3..7522bd714 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -45,14 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/hid_generic_inout/src/tusb_config.h b/examples/device/hid_generic_inout/src/tusb_config.h
index 1b8b91c41..9db50269c 100644
--- a/examples/device/hid_generic_inout/src/tusb_config.h
+++ b/examples/device/hid_generic_inout/src/tusb_config.h
@@ -45,14 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/hid_multiple_interface/src/tusb_config.h b/examples/device/hid_multiple_interface/src/tusb_config.h
index c034b086e..32e8c2843 100644
--- a/examples/device/hid_multiple_interface/src/tusb_config.h
+++ b/examples/device/hid_multiple_interface/src/tusb_config.h
@@ -45,15 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || \
-       CFG_TUSB_MCU == OPT_MCU_FT90X   || CFG_TUSB_MCU == OPT_MCU_FT93X)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/midi_test/src/tusb_config.h b/examples/device/midi_test/src/tusb_config.h
index a40d7605c..967c71403 100644
--- a/examples/device/midi_test/src/tusb_config.h
+++ b/examples/device/midi_test/src/tusb_config.h
@@ -45,15 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56 || \
-       CFG_TUSB_MCU == OPT_MCU_FT90X   || CFG_TUSB_MCU == OPT_MCU_FT93X)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/msc_dual_lun/src/tusb_config.h b/examples/device/msc_dual_lun/src/tusb_config.h
index 44da21e54..f617f5a4c 100644
--- a/examples/device/msc_dual_lun/src/tusb_config.h
+++ b/examples/device/msc_dual_lun/src/tusb_config.h
@@ -45,14 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h
index 114961cb7..b1b48598b 100644
--- a/examples/device/net_lwip_webserver/src/tusb_config.h
+++ b/examples/device/net_lwip_webserver/src/tusb_config.h
@@ -45,14 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index e8d93f56a..3b2f7df48 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -42,10 +42,10 @@ extern "C" {
 #error CFG_TUSB_MCU must be defined
 #endif
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-#define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
-#else
-#define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE
+// RHPort max operational speed can defined by board.mk
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
+#ifndef BOARD_DEVICE_RHPORT_SPEED
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 #ifndef CFG_TUSB_OS
diff --git a/examples/device/usbtmc/src/tusb_config.h b/examples/device/usbtmc/src/tusb_config.h
index a192d0dbc..5b2215be5 100644
--- a/examples/device/usbtmc/src/tusb_config.h
+++ b/examples/device/usbtmc/src/tusb_config.h
@@ -27,14 +27,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index 4feb6a48a..3a079e66b 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -40,14 +40,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/examples/device/webusb_serial/src/tusb_config.h b/examples/device/webusb_serial/src/tusb_config.h
index 26b81b389..f5e4694e3 100644
--- a/examples/device/webusb_serial/src/tusb_config.h
+++ b/examples/device/webusb_serial/src/tusb_config.h
@@ -45,14 +45,9 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_DEVICE_RHPORT_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
-  #endif
+  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
diff --git a/src/device/dcd_attr.h b/src/device/dcd_attr.h
index e16a5ccca..e14a3f134 100644
--- a/src/device/dcd_attr.h
+++ b/src/device/dcd_attr.h
@@ -33,7 +33,8 @@
 // - ENDPOINT_MAX: max (logical) number of endpoint
 // - ENDPOINT_EXCLUSIVE_NUMBER: endpoint number with different direction IN and OUT aren't allowed,
 //                              e.g EP1 OUT & EP1 IN cannot exist together
-// - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
+// - RHPORT_HIGHSPEED: mask to indicate which port support highspeed mode (without external PHY)
+//                     bit0 for port0 and so on.
 
 //------------- NXP -------------//
 #if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
@@ -45,7 +46,8 @@
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4
   #define DCD_ATTR_CONTROLLER_CHIPIDEA_HS
-  #define DCD_ATTR_ENDPOINT_MAX   6
+  #define DCD_ATTR_ENDPOINT_MAX     6
+  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01 // Port0 HS, Port1 FS
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
    #define DCD_ATTR_ENDPOINT_MAX   5
@@ -60,7 +62,8 @@
 
 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
   #define DCD_ATTR_CONTROLLER_CHIPIDEA_HS
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define DCD_ATTR_ENDPOINT_MAX     8
+  #define DCD_ATTR_RHPORT_HIGHSPEED 0x03 // Port0 HS, Port1 HS
 
 #elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
   #define DCD_ATTR_ENDPOINT_MAX   16
@@ -83,7 +86,8 @@
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
 #elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
-  #define DCD_ATTR_ENDPOINT_MAX   10
+  #define DCD_ATTR_ENDPOINT_MAX     10
+  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
 #elif TU_CHECK_MCU(OPT_MCU_PIC32MZ)
@@ -145,7 +149,8 @@
 
 //------------- Sony -------------//
 #elif TU_CHECK_MCU(OPT_MCU_CXD56)
-  #define DCD_ATTR_ENDPOINT_MAX   7
+  #define DCD_ATTR_ENDPOINT_MAX     7
+  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
   #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- TI -------------//
@@ -167,7 +172,8 @@
   #define DCD_ATTR_ENDPOINT_MAX   6
 
 #elif TU_CHECK_MCU(OPT_MCU_NUC505)
-  #define DCD_ATTR_ENDPOINT_MAX   12
+  #define DCD_ATTR_ENDPOINT_MAX     12
+  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
 
 //------------- Espressif -------------//
 #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
@@ -195,7 +201,8 @@
 
 //------------- Broadcom -------------//
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define DCD_ATTR_ENDPOINT_MAX     8
+  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
 
 //------------- Broadcom -------------//
 #elif TU_CHECK_MCU(OPT_MCU_XMC4000)
@@ -203,10 +210,12 @@
 
 //------------- BridgeTek -------------//
 #elif TU_CHECK_MCU(OPT_MCU_FT90X)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define DCD_ATTR_ENDPOINT_MAX     8
+  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
 
 #elif TU_CHECK_MCU(OPT_MCU_FT93X)
-  #define DCD_ATTR_ENDPOINT_MAX   16
+  #define DCD_ATTR_ENDPOINT_MAX     16
+  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
 
 //------------ Allwinner -------------//
 #elif TU_CHECK_MCU(OPT_MCU_F1C100S)
@@ -218,8 +227,8 @@
 #endif
 
 // Default to fullspeed if not defined
-//#ifndef PORT_HIGHSPEED
-//  #define DCD_ATTR_PORT_HIGHSPEED 0x00
-//#endif
+#ifndef DCD_ATTR_RHPORT_HIGHSPEED
+  #define DCD_ATTR_RHPORT_HIGHSPEED 0x00
+#endif
 
 #endif
diff --git a/src/device/usbd.h b/src/device/usbd.h
index ec34817fa..b2bf8ba9d 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -453,7 +453,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -502,7 +502,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -550,7 +550,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
   /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
@@ -558,7 +558,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 //   Calculate wMaxPacketSize of Endpoints
 #define TUD_AUDIO_EP_SIZE(_maxFrequency, _nBytesPerSample, _nChannels) \
-    ((((_maxFrequency + ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 7999 : 999)) / ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels)
+    ((((_maxFrequency + (TUD_OPT_HIGH_SPEED ? 7999 : 999)) / (TUD_OPT_HIGH_SPEED ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels)
 
 
 //--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 714c6ed9e..5d104e31c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -172,20 +172,24 @@
   #include "tusb_config.h"
 #endif
 
+#include "device/dcd_attr.h"
+
 //--------------------------------------------------------------------
 // RootHub Mode Configuration
 // CFG_TUSB_RHPORTx_MODE contains operation mode and speed for that port
 //--------------------------------------------------------------------
 
-// Lower 4-bit is operational mode
-#define OPT_MODE_NONE         0x00 ///< Disabled
-#define OPT_MODE_DEVICE       0x01 ///< Device Mode
-#define OPT_MODE_HOST         0x02 ///< Host Mode
+// Low byte is operational mode
+#define OPT_MODE_NONE           0x0000 ///< Disabled
+#define OPT_MODE_DEVICE         0x0001 ///< Device Mode
+#define OPT_MODE_HOST           0x0002 ///< Host Mode
 
-// Higher 4-bit is max operational speed (corresponding to tusb_speed_t)
-#define OPT_MODE_FULL_SPEED   0x00 ///< Max Full Speed
-#define OPT_MODE_LOW_SPEED    0x10 ///< Max Low Speed
-#define OPT_MODE_HIGH_SPEED   0x20 ///< Max High Speed
+// High byte is max operational speed (corresponding to tusb_speed_t)
+#define OPT_MODE_DEFAULT_SPEED  0x0000 ///< Default (max) speed supported by MCU
+#define OPT_MODE_LOW_SPEED      0x0100 ///< Low Speed
+#define OPT_MODE_FULL_SPEED     0x0200 ///< Full Speed
+#define OPT_MODE_HIGH_SPEED     0x0400 ///< High Speed
+#define OPT_MODE_SPEED_MASK     0xff00
 
 #ifndef CFG_TUSB_RHPORT0_MODE
   #define CFG_TUSB_RHPORT0_MODE OPT_MODE_NONE
@@ -200,20 +204,27 @@
   #error "TinyUSB currently does not support same modes on more than 1 roothub port"
 #endif
 
-// Which roothub port is configured as host
-#define TUH_OPT_RHPORT      ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST) ? 1 : -1) )
-#define CFG_TUH_ENABLED     ( TUH_OPT_RHPORT >= 0 )
+//------------- Roothub as Device -------------//
 
-// Which roothub port is configured as device
-#define TUD_OPT_RHPORT      ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE) ? 1 : -1) )
-
-#if TUD_OPT_RHPORT == 0
-#define TUD_OPT_HIGH_SPEED  ( (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HIGH_SPEED )
+#if (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE
+  #define TUD_RHPORT_MODE  (CFG_TUSB_RHPORT0_MODE)
+  #define TUD_OPT_RHPORT   0
+#elif (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE
+  #define TUD_RHPORT_MODE  (CFG_TUSB_RHPORT1_MODE)
+  #define TUD_OPT_RHPORT   1
 #else
-#define TUD_OPT_HIGH_SPEED  ( (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HIGH_SPEED )
+  #define TUD_RHPORT_MODE   OPT_MODE_NONE
+  #define TUD_OPT_RHPORT   -1
 #endif
 
-#define CFG_TUD_ENABLED ( TUD_OPT_RHPORT >= 0 )
+#define CFG_TUD_ENABLED     ( TUD_RHPORT_MODE & OPT_MODE_DEVICE )
+#define TUD_OPT_HIGH_SPEED  ( (TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK) ? (TUD_RHPORT_MODE & OPT_MODE_HIGH_SPEED) : (DCD_ATTR_RHPORT_HIGHSPEED & (1 << TUD_OPT_RHPORT)) )
+
+// CFG_TUD_SPEED    OPT_MODE_HIGH_SPEED
+
+//------------- Roothub as Host -------------//
+#define TUH_OPT_RHPORT      ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST) ? 1 : -1) )
+#define CFG_TUH_ENABLED     ( TUH_OPT_RHPORT >= 0 )
 
 // For backward compatible
 #define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED

From 99ad3ae2ca9d4db79b2ac92a6991ebdc3dfb94a3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Feb 2022 13:45:51 +0700
Subject: [PATCH 0829/2085] rename and move dcd_attr.h to tusb_mcu_attr.h

---
 src/{device/dcd_attr.h => common/tusb_mcu_attr.h} | 4 ++--
 src/device/dcd.h                                  | 1 -
 src/portable/chipidea/ci_hs/dcd_ci_hs.c           | 1 -
 src/portable/synopsys/dwc2/dcd_dwc2.c             | 1 -
 src/tusb_option.h                                 | 2 +-
 5 files changed, 3 insertions(+), 6 deletions(-)
 rename src/{device/dcd_attr.h => common/tusb_mcu_attr.h} (99%)

diff --git a/src/device/dcd_attr.h b/src/common/tusb_mcu_attr.h
similarity index 99%
rename from src/device/dcd_attr.h
rename to src/common/tusb_mcu_attr.h
index e14a3f134..c10869d21 100644
--- a/src/device/dcd_attr.h
+++ b/src/common/tusb_mcu_attr.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef TUSB_DCD_ATTR_H_
-#define TUSB_DCD_ATTR_H_
+#ifndef TUSB_MCU_ATTR_H_
+#define TUSB_MCU_ATTR_H_
 
 #include "tusb_option.h"
 
diff --git a/src/device/dcd.h b/src/device/dcd.h
index fbcef40d4..4e725c95a 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -30,7 +30,6 @@
 #include "common/tusb_common.h"
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
-#include "dcd_attr.h"
 
 #ifdef __cplusplus
  extern "C" {
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index ffb2ebd16..6361fe629 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -25,7 +25,6 @@
  */
 
 #include "tusb_option.h"
-#include "device/dcd_attr.h"
 
 #if CFG_TUD_ENABLED && defined(DCD_ATTR_CONTROLLER_CHIPIDEA_HS)
 
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 86dc760c8..ecbc36fb9 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -28,7 +28,6 @@
  */
 
 #include "tusb_option.h"
-#include "device/dcd_attr.h"
 
 #if CFG_TUD_ENABLED && \
     ( defined(DCD_ATTR_DWC2_STM32) || \
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 5d104e31c..6a3638461 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -172,7 +172,7 @@
   #include "tusb_config.h"
 #endif
 
-#include "device/dcd_attr.h"
+#include "common/tusb_mcu_attr.h"
 
 //--------------------------------------------------------------------
 // RootHub Mode Configuration

From 309540473bc2985d83212b9da0527c7500ba2a66 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Feb 2022 22:26:35 +0700
Subject: [PATCH 0830/2085] minor house keeping

---
 src/class/msc/msc_host.c |  2 +-
 src/common/tusb_error.h  |  2 ++
 src/device/usbd.c        |  4 +---
 src/host/usbh.c          |  1 +
 src/tusb.c               |  2 ++
 src/tusb_option.h        | 15 +++++++++++++--
 6 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index a49a10522..e4239e375 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED & CFG_TUH_MSC
+#if CFG_TUH_ENABLED && CFG_TUH_MSC
 
 #include "host/usbh.h"
 #include "host/usbh_classdriver.h"
diff --git a/src/common/tusb_error.h b/src/common/tusb_error.h
index d7ad8c318..42541acd6 100644
--- a/src/common/tusb_error.h
+++ b/src/common/tusb_error.h
@@ -64,6 +64,8 @@ typedef enum
 #if CFG_TUSB_DEBUG
 /// Enum to String for debugging purposes. Only available if \ref CFG_TUSB_DEBUG > 0
 extern char const* const tusb_strerr[TUSB_ERROR_COUNT];
+extern char const* const tusb_speed_str[];
+
 #endif
 
 #ifdef __cplusplus
diff --git a/src/device/usbd.c b/src/device/usbd.c
index e6861ee0a..c20bab76b 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -332,8 +332,6 @@ static char const* const _tusb_std_request_str[] =
   "Synch Frame"
 };
 
-static char const* const _tusb_speed_str[] = { "Full", "Low", "High" };
-
 // for usbd_control to print the name of control complete driver
 void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
 {
@@ -509,7 +507,7 @@ void tud_task (void)
     switch ( event.event_id )
     {
       case DCD_EVENT_BUS_RESET:
-        TU_LOG2(": %s Speed\r\n", _tusb_speed_str[event.bus_reset.speed]);
+        TU_LOG2(": %s Speed\r\n", tusb_speed_str[event.bus_reset.speed]);
         usbd_reset(event.rhport);
         _usbd_dev.speed = event.bus_reset.speed;
       break;
diff --git a/src/host/usbh.c b/src/host/usbh.c
index e29ce1e54..ce0ccc3cb 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -709,6 +709,7 @@ static bool enum_new_device(hcd_event_t* event)
     if ( !hcd_port_connect_status(_dev0.rhport) ) return true;
 
     _dev0.speed = hcd_port_speed_get(_dev0.rhport );
+    TU_LOG2("%s Speed\r\n", tusb_speed_str[_dev0.speed]);
 
     enum_request_addr0_device_desc();
   }
diff --git a/src/tusb.c b/src/tusb.c
index 03fe43104..a30221059 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -163,6 +163,8 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf,
 
 char const* const tusb_strerr[TUSB_ERROR_COUNT] = { ERROR_TABLE(ERROR_STRING) };
 
+char const* const tusb_speed_str[] = { "Full", "Low", "High" };
+
 static void dump_str_line(uint8_t const* buf, uint16_t count)
 {
   tu_printf("  |");
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 6a3638461..5bf336438 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -223,8 +223,19 @@
 // CFG_TUD_SPEED    OPT_MODE_HIGH_SPEED
 
 //------------- Roothub as Host -------------//
-#define TUH_OPT_RHPORT      ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST) ? 1 : -1) )
-#define CFG_TUH_ENABLED     ( TUH_OPT_RHPORT >= 0 )
+
+#if (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST
+  #define TUH_RHPORT_MODE  (CFG_TUSB_RHPORT0_MODE)
+  #define TUH_OPT_RHPORT   0
+#elif (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST
+  #define TUH_RHPORT_MODE  (CFG_TUSB_RHPORT1_MODE)
+  #define TUH_OPT_RHPORT   1
+#else
+  #define TUH_RHPORT_MODE   OPT_MODE_NONE
+  #define TUH_OPT_RHPORT   -1
+#endif
+
+#define CFG_TUH_ENABLED     ( TUH_RHPORT_MODE & OPT_MODE_HOST )
 
 // For backward compatible
 #define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED

From 89115253da3ef55d59367977b8103a5e321e56aa Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Feb 2022 22:45:05 +0700
Subject: [PATCH 0831/2085] internal symbol rename

---
 src/common/tusb_mcu_attr.h |  28 ++++++----
 src/host/hcd.h             |   1 -
 src/host/hcd_attr.h        | 105 -------------------------------------
 src/portable/ehci/ehci.c   |   6 +--
 src/portable/ohci/ohci.c   |   2 +-
 5 files changed, 23 insertions(+), 119 deletions(-)
 delete mode 100644 src/host/hcd_attr.h

diff --git a/src/common/tusb_mcu_attr.h b/src/common/tusb_mcu_attr.h
index c10869d21..e3393ad04 100644
--- a/src/common/tusb_mcu_attr.h
+++ b/src/common/tusb_mcu_attr.h
@@ -27,14 +27,13 @@
 #ifndef TUSB_MCU_ATTR_H_
 #define TUSB_MCU_ATTR_H_
 
-#include "tusb_option.h"
-
-// Attribute includes
-// - ENDPOINT_MAX: max (logical) number of endpoint
-// - ENDPOINT_EXCLUSIVE_NUMBER: endpoint number with different direction IN and OUT aren't allowed,
-//                              e.g EP1 OUT & EP1 IN cannot exist together
-// - RHPORT_HIGHSPEED: mask to indicate which port support highspeed mode (without external PHY)
-//                     bit0 for port0 and so on.
+/* Attribute includes
+ * - ENDPOINT_MAX: max (logical) number of endpoint
+ * - ENDPOINT_EXCLUSIVE_NUMBER: endpoint number with different direction IN and OUT aren't allowed,
+ *                              e.g EP1 OUT & EP1 IN cannot exist together
+ * - RHPORT_HIGHSPEED: mask to indicate which port support highspeed mode (without external PHY)
+ *                     bit0 for port0 and so on.
+ */
 
 //------------- NXP -------------//
 #if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
@@ -42,6 +41,7 @@
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   #define DCD_ATTR_ENDPOINT_MAX   16
+  #define HCD_ATTR_OHCI
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4
@@ -49,6 +49,8 @@
   #define DCD_ATTR_ENDPOINT_MAX     6
   #define DCD_ATTR_RHPORT_HIGHSPEED 0x01 // Port0 HS, Port1 FS
 
+  #define HCD_ATTR_EHCI
+
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
    #define DCD_ATTR_ENDPOINT_MAX   5
 
@@ -65,6 +67,8 @@
   #define DCD_ATTR_ENDPOINT_MAX     8
   #define DCD_ATTR_RHPORT_HIGHSPEED 0x03 // Port0 HS, Port1 HS
 
+  #define HCD_ATTR_EHCI
+
 #elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
   #define DCD_ATTR_ENDPOINT_MAX   16
 
@@ -221,7 +225,13 @@
 #elif TU_CHECK_MCU(OPT_MCU_F1C100S)
   #define DCD_ATTR_ENDPOINT_MAX   4
 
-#else
+#endif
+
+//--------------------------------------------------------------------+
+// Default Values
+//--------------------------------------------------------------------+
+
+#ifndef DCD_ATTR_ENDPOINT_MAX
   #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define DCD_ATTR_ENDPOINT_MAX   8
 #endif
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 054fd9647..80500f048 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -30,7 +30,6 @@
 #include "common/tusb_common.h"
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
-#include "hcd_attr.h"
 
 #ifdef __cplusplus
  extern "C" {
diff --git a/src/host/hcd_attr.h b/src/host/hcd_attr.h
deleted file mode 100644
index 06011c63c..000000000
--- a/src/host/hcd_attr.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef TUSB_HCD_ATTR_H_
-#define TUSB_HCD_ATTR_H_
-
-#include "tusb_option.h"
-
-// Attribute includes
-// - ENDPOINT_MAX: max (logical) number of endpoint
-// - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
-
-//------------- NXP -------------//
-#if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
-  #define HCD_ATTR_OHCI
-
-#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
-  #define HCD_ATTR_EHCI_TRANSDIMENSION
-
-#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
-  // #define HCD_ATTR_EHCI_NXP_PTD
-
-#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
-  // #define HCD_ATTR_EHCI_NXP_PTD
-
-#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
-  #define HCD_ATTR_EHCI_TRANSDIMENSION
-
-#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX)
-
-//------------- Microchip -------------//
-#elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
-      TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
-
-#elif TU_CHECK_MCU(OPT_MCU_SAMG)
-
-#elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
-
-//------------- ST -------------//
-#elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1, OPT_MCU_STM32F3) || \
-      TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32L4)
-
-#elif TU_CHECK_MCU(OPT_MCU_STM32F2, OPT_MCU_STM32F3, OPT_MCU_STM32F4)
-
-#elif TU_CHECK_MCU(OPT_MCU_STM32F7)
-
-#elif TU_CHECK_MCU(OPT_MCU_STM32H7)
-
-//------------- Sony -------------//
-#elif TU_CHECK_MCU(OPT_MCU_CXD56)
-
-//------------- Nuvoton -------------//
-#elif TU_CHECK_MCU(OPT_MCU_NUC505)
-
-//------------- Espressif -------------//
-#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-
-//------------- Raspberry Pi -------------//
-#elif TU_CHECK_MCU(OPT_MCU_RP2040)
-
-//------------- Silabs -------------//
-#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
-
-//------------- Renesas -------------//
-#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
-
-//#elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
-//  #define DCD_ATTR_ENDPOINT_MAX not known yet
-
-//------------- GigaDevice -------------//
-#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
-
-#else
-//  #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
-#endif
-
-// Default to fullspeed if not defined
-//#ifndef PORT_HIGHSPEED
-//  #define DCD_ATTR_PORT_HIGHSPEED 0x00
-//#endif
-
-#endif
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 6b86cb2b2..419601245 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -24,9 +24,9 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "host/hcd_attr.h"
+#include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && defined(HCD_ATTR_EHCI_TRANSDIMENSION)
+#if CFG_TUH_ENABLED && defined(HCD_ATTR_EHCI)
 
 //--------------------------------------------------------------------+
 // INCLUDE
@@ -45,7 +45,7 @@
 #define EHCI_DBG     2
 
 // Framelist size as small as possible to save SRAM
-#ifdef HCD_ATTR_EHCI_TRANSDIMENSION
+#ifdef HCD_ATTR_EHCI
   // NXP Transdimension: 8 elements
   #define FRAMELIST_SIZE_BIT_VALUE      7u
   #define FRAMELIST_SIZE_USBCMD_VALUE   (((FRAMELIST_SIZE_BIT_VALUE &  3) << EHCI_USBCMD_POS_FRAMELIST_SIZE) | \
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 8860f27a2..c9e1061f9 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "host/hcd_attr.h"
+#include "tusb_option.h"
 
 #if CFG_TUH_ENABLED && defined(HCD_ATTR_OHCI)
 

From 0997589c45a7c4dd96da0d9bce37f771520e34c6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Feb 2022 23:04:39 +0700
Subject: [PATCH 0832/2085] more symbol rename

---
 src/common/tusb_mcu_attr.h              | 6 +++---
 src/portable/chipidea/ci_hs/dcd_ci_hs.c | 2 +-
 src/portable/ehci/ehci.c                | 2 +-
 src/tusb_option.h                       | 2 --
 4 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/common/tusb_mcu_attr.h b/src/common/tusb_mcu_attr.h
index e3393ad04..0341dd1bf 100644
--- a/src/common/tusb_mcu_attr.h
+++ b/src/common/tusb_mcu_attr.h
@@ -27,7 +27,7 @@
 #ifndef TUSB_MCU_ATTR_H_
 #define TUSB_MCU_ATTR_H_
 
-/* Attribute includes
+/* USB Controller Attributes for Device, Host or MCU (both)
  * - ENDPOINT_MAX: max (logical) number of endpoint
  * - ENDPOINT_EXCLUSIVE_NUMBER: endpoint number with different direction IN and OUT aren't allowed,
  *                              e.g EP1 OUT & EP1 IN cannot exist together
@@ -45,7 +45,7 @@
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4
-  #define DCD_ATTR_CONTROLLER_CHIPIDEA_HS
+  #define MCU_ATTR_CONTROLLER_CHIPIDEA_HS
   #define DCD_ATTR_ENDPOINT_MAX     6
   #define DCD_ATTR_RHPORT_HIGHSPEED 0x01 // Port0 HS, Port1 FS
 
@@ -63,7 +63,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   6
 
 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
-  #define DCD_ATTR_CONTROLLER_CHIPIDEA_HS
+  #define MCU_ATTR_CONTROLLER_CHIPIDEA_HS
   #define DCD_ATTR_ENDPOINT_MAX     8
   #define DCD_ATTR_RHPORT_HIGHSPEED 0x03 // Port0 HS, Port1 HS
 
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 6361fe629..21087681c 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && defined(DCD_ATTR_CONTROLLER_CHIPIDEA_HS)
+#if CFG_TUD_ENABLED && defined(MCU_ATTR_CONTROLLER_CHIPIDEA_HS)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 419601245..5b42ece48 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -45,7 +45,7 @@
 #define EHCI_DBG     2
 
 // Framelist size as small as possible to save SRAM
-#ifdef HCD_ATTR_EHCI
+#ifdef MCU_ATTR_CONTROLLER_CHIPIDEA_HS
   // NXP Transdimension: 8 elements
   #define FRAMELIST_SIZE_BIT_VALUE      7u
   #define FRAMELIST_SIZE_USBCMD_VALUE   (((FRAMELIST_SIZE_BIT_VALUE &  3) << EHCI_USBCMD_POS_FRAMELIST_SIZE) | \
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 5bf336438..5cc362f1a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -220,8 +220,6 @@
 #define CFG_TUD_ENABLED     ( TUD_RHPORT_MODE & OPT_MODE_DEVICE )
 #define TUD_OPT_HIGH_SPEED  ( (TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK) ? (TUD_RHPORT_MODE & OPT_MODE_HIGH_SPEED) : (DCD_ATTR_RHPORT_HIGHSPEED & (1 << TUD_OPT_RHPORT)) )
 
-// CFG_TUD_SPEED    OPT_MODE_HIGH_SPEED
-
 //------------- Roothub as Host -------------//
 
 #if (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST

From 1482a415240171b7ff2bd2ee0f123635dd15f9a4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Feb 2022 23:16:40 +0700
Subject: [PATCH 0833/2085] fix uac2_headset build

---
 examples/device/uac2_headset/src/tusb_config.h | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index 3b2f7df48..2a1189a79 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -42,11 +42,7 @@ extern "C" {
 #error CFG_TUSB_MCU must be defined
 #endif
 
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
+#define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE
 
 #ifndef CFG_TUSB_OS
 #define CFG_TUSB_OS                 OPT_OS_NONE

From 8eeda60bd0e81fb3fe7211014ab672b23dc847a3 Mon Sep 17 00:00:00 2001
From: iabdalkader <i.abdalkader@gmail.com>
Date: Fri, 25 Feb 2022 05:54:41 +0200
Subject: [PATCH 0834/2085] Set the standard inquiry response additional length
 field.

* The standard inquiry response additional length field needs to be set to
the length in bytes of the remaining standard inquiry data (i.e. N - 5),
otherwise the kernel driver issues a warning about short inquiry response..
---
 src/class/msc/msc_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index e09a2b11a..0c18b0ced 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -753,6 +753,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
           .is_removable         = 1,
           .version              = 2,
           .response_data_format = 2,
+          .additional_length    = sizeof(scsi_inquiry_resp_t) - 5,
       };
 
       // vendor_id, product_id, product_rev is space padded string

From 39fdbc8ffca3cb0a610ce4140e1d527beb47ad3d Mon Sep 17 00:00:00 2001
From: Tom Peterson <topeters@etcconnect.com>
Date: Fri, 25 Feb 2022 12:39:09 -0600
Subject: [PATCH 0835/2085] Updated the clearing of the status register bits to
 use a straight '=', rather than an '|='.  Use of the latter caused an extra,
 unwanted read of the status register before the write-to-clear operation,
 which, in some cases, allowed new status bits to assert (relative to the
 initial read of the status register two statements earlier), and then be
 cleared blindly and unconditionally during the write-back.  This had the
 potential (and, in my case, observed) effect of dropping the handling of an
 enabled interrupt.  Ultimately, the system would lock up in a busy state,
 with no hope of clearing the condition.  See Issue #1339 for more
 information.

---
 src/portable/ehci/ehci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index e92f8a951..9b998cda6 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -657,7 +657,7 @@ void hcd_int_handler(uint8_t rhport)
   uint32_t int_status = regs->status;
   int_status &= regs->inten;
   
-  regs->status |= int_status; // Acknowledge handled interrupt
+  regs->status = int_status; // Acknowledge handled interrupt
 
   if (int_status == 0) return;
 

From c06ecbef0ce7cb286dce85d2329a02c513e2c61b Mon Sep 17 00:00:00 2001
From: Tom Peterson <topeters@etcconnect.com>
Date: Fri, 25 Feb 2022 16:49:55 -0600
Subject: [PATCH 0836/2085] The IAR compilier does not resolve references to
 fields in the anonymous structs defined within the usbh_dev0_t and
 usbh_device_t structs as they are defined.  The problem seems to relate to
 the placement of the 'volatile' keyword at the struct level.  I fixed the
 problem by removing the 'volatile' from the struct level, and instead placing
 it on each of the field declarations within the structs.

---
 src/host/usbh.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index b8439addc..e925a01fe 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -62,12 +62,12 @@ typedef struct
   uint8_t hub_port;
   uint8_t speed;
 
-  volatile struct TU_ATTR_PACKED
+  struct TU_ATTR_PACKED
   {
-    uint8_t connected    : 1;
-    uint8_t addressed    : 1;
-    uint8_t configured   : 1;
-    uint8_t suspended    : 1;
+    volatile uint8_t connected    : 1;
+    volatile uint8_t addressed    : 1;
+    volatile uint8_t configured   : 1;
+    volatile uint8_t suspended    : 1;
   };
 } usbh_dev0_t;
 
@@ -78,12 +78,12 @@ typedef struct {
   uint8_t hub_port;
   uint8_t speed;
 
-  volatile struct TU_ATTR_PACKED
+  struct TU_ATTR_PACKED
   {
-    uint8_t connected    : 1;
-    uint8_t addressed    : 1;
-    uint8_t configured   : 1;
-    uint8_t suspended    : 1;
+    volatile uint8_t connected    : 1;
+    volatile uint8_t addressed    : 1;
+    volatile uint8_t configured   : 1;
+    volatile uint8_t suspended    : 1;
   };
 
   //------------- device descriptor -------------//

From bc63f59af2e75e4fc93715ac88a2a8360f09d69a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 26 Feb 2022 15:18:51 +0700
Subject: [PATCH 0837/2085] mcu specific rename

---
 src/common/{tusb_mcu_attr.h => tusb_mcu.h} | 34 ++++++++++++++++---
 src/portable/chipidea/ci_hs/dcd_ci_hs.c    |  2 +-
 src/portable/ehci/ehci.c                   |  2 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c      |  2 +-
 src/tusb_option.h                          | 39 ++++++++--------------
 5 files changed, 46 insertions(+), 33 deletions(-)
 rename src/common/{tusb_mcu_attr.h => tusb_mcu.h} (91%)

diff --git a/src/common/tusb_mcu_attr.h b/src/common/tusb_mcu.h
similarity index 91%
rename from src/common/tusb_mcu_attr.h
rename to src/common/tusb_mcu.h
index 0341dd1bf..1f1aeb462 100644
--- a/src/common/tusb_mcu_attr.h
+++ b/src/common/tusb_mcu.h
@@ -24,8 +24,22 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef TUSB_MCU_ATTR_H_
-#define TUSB_MCU_ATTR_H_
+#ifndef TUSB_MCU_H_
+#define TUSB_MCU_H_
+
+//--------------------------------------------------------------------+
+// Port Specific
+// TUP stand for TinyUSB Port (can be renamed)
+//--------------------------------------------------------------------+
+
+//------------- Unaligned Memory Access -------------//
+
+// ARMv7+ (M3-M7, M23-M33) can access unaligned memory
+#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
+  #define TUP_ARCH_STRICT_ALIGN   0
+#else
+  #define TUP_ARCH_STRICT_ALIGN   1
+#endif
 
 /* USB Controller Attributes for Device, Host or MCU (both)
  * - ENDPOINT_MAX: max (logical) number of endpoint
@@ -45,7 +59,7 @@
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4
-  #define MCU_ATTR_CONTROLLER_CHIPIDEA_HS
+  #define TUP_USBIP_CHIPIDEA_HS
   #define DCD_ATTR_ENDPOINT_MAX     6
   #define DCD_ATTR_RHPORT_HIGHSPEED 0x01 // Port0 HS, Port1 FS
 
@@ -63,7 +77,7 @@
   #define DCD_ATTR_ENDPOINT_MAX   6
 
 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
-  #define MCU_ATTR_CONTROLLER_CHIPIDEA_HS
+  #define TUP_USBIP_CHIPIDEA_HS
   #define DCD_ATTR_ENDPOINT_MAX     8
   #define DCD_ATTR_RHPORT_HIGHSPEED 0x03 // Port0 HS, Port1 HS
 
@@ -106,6 +120,8 @@
   #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
       defined (STM32F107xB) || defined (STM32F107xC)
     #define DCD_ATTR_ENDPOINT_MAX   4
+
+    #define TUP_USBIP_DWC2
     #define DCD_ATTR_DWC2_STM32
   #else
     #define DCD_ATTR_ENDPOINT_MAX   8
@@ -114,6 +130,8 @@
 #elif TU_CHECK_MCU(OPT_MCU_STM32F2)
   // FS has 4 ep, HS has 5 ep
   #define DCD_ATTR_ENDPOINT_MAX   6
+
+  #define TUP_USBIP_DWC2
   #define DCD_ATTR_DWC2_STM32
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F3)
@@ -122,15 +140,21 @@
 #elif TU_CHECK_MCU(OPT_MCU_STM32F4)
   // For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
   #define DCD_ATTR_ENDPOINT_MAX   6
+
+  #define TUP_USBIP_DWC2
   #define DCD_ATTR_DWC2_STM32
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F7)
   // FS has 6, HS has 9
   #define DCD_ATTR_ENDPOINT_MAX   9
+
+  #define TUP_USBIP_DWC2
   #define DCD_ATTR_DWC2_STM32
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
   #define DCD_ATTR_ENDPOINT_MAX   9
+
+  #define TUP_USBIP_DWC2
   #define DCD_ATTR_DWC2_STM32
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
@@ -146,6 +170,8 @@
       defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
       defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
     #define DCD_ATTR_ENDPOINT_MAX   6
+
+    #define TUP_USBIP_DWC2
     #define DCD_ATTR_DWC2_STM32
   #else
     #define DCD_ATTR_ENDPOINT_MAX   8
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 21087681c..726c7a517 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && defined(MCU_ATTR_CONTROLLER_CHIPIDEA_HS)
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_HS)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 5b42ece48..ac873455b 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -45,7 +45,7 @@
 #define EHCI_DBG     2
 
 // Framelist size as small as possible to save SRAM
-#ifdef MCU_ATTR_CONTROLLER_CHIPIDEA_HS
+#ifdef TUP_USBIP_CHIPIDEA_HS
   // NXP Transdimension: 8 elements
   #define FRAMELIST_SIZE_BIT_VALUE      7u
   #define FRAMELIST_SIZE_USBCMD_VALUE   (((FRAMELIST_SIZE_BIT_VALUE &  3) << EHCI_USBCMD_POS_FRAMELIST_SIZE) | \
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index ecbc36fb9..377f0f44e 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -30,7 +30,7 @@
 #include "tusb_option.h"
 
 #if CFG_TUD_ENABLED && \
-    ( defined(DCD_ATTR_DWC2_STM32) || \
+    ( defined(TUP_USBIP_DWC2) || \
       TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) || \
       TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711, OPT_MCU_BCM2835) || \
       TU_CHECK_MCU(OPT_MCU_BCM2837, OPT_MCU_XMC4000) )
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 5cc362f1a..3c2207c26 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -172,7 +172,7 @@
   #include "tusb_config.h"
 #endif
 
-#include "common/tusb_mcu_attr.h"
+#include "common/tusb_mcu.h"
 
 //--------------------------------------------------------------------
 // RootHub Mode Configuration
@@ -239,6 +239,18 @@
 #define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED
 #define TUSB_OPT_HOST_ENABLED   CFG_TUH_ENABLED
 
+// TODO move later
+// TUP_MCU_STRICT_ALIGN will overwrite TUP_ARCH_STRICT_ALIGN.
+// In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler
+// to generate unaligned access code.
+// LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM
+#if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX)
+  #define TUP_MCU_STRICT_ALIGN   1
+#else
+  #define TUP_MCU_STRICT_ALIGN   0
+#endif
+
+
 //--------------------------------------------------------------------+
 // COMMON OPTIONS
 //--------------------------------------------------------------------+
@@ -371,31 +383,6 @@
 #define CFG_TUH_VENDOR 0
 #endif
 
-//--------------------------------------------------------------------+
-// Port Specific
-// TUP stand for TinyUSB Port (can be renamed)
-//--------------------------------------------------------------------+
-
-//------------- Unaligned Memory -------------//
-
-// ARMv7+ (M3-M7, M23-M33) can access unaligned memory
-#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
-  #define TUP_ARCH_STRICT_ALIGN   0
-#else
-  #define TUP_ARCH_STRICT_ALIGN   1
-#endif
-
-// TUP_MCU_STRICT_ALIGN will overwrite TUP_ARCH_STRICT_ALIGN.
-// In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler
-// to generate unaligned access code.
-// LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM
-#if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX)
-  #define TUP_MCU_STRICT_ALIGN   1
-#else
-  #define TUP_MCU_STRICT_ALIGN   0
-#endif
-
-
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------

From 11c89d43abec5a37856e3f026b23ab26c33a656a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 26 Feb 2022 17:03:54 +0700
Subject: [PATCH 0838/2085] more internal rename

---
 src/common/tusb_mcu.h                         | 160 +++++++++---------
 src/device/dcd.h                              |   2 +-
 src/portable/chipidea/ci_hs/dcd_ci_hs.c       |   6 +-
 src/portable/ehci/ehci.c                      |   2 +-
 src/portable/mentor/musb/dcd_musb.c           |  10 +-
 .../nxp/transdimension/dcd_transdimension.c   |   6 +-
 src/portable/ohci/ohci.c                      |   2 +-
 src/portable/sunxi/dcd_sunxi_musb.c           |   8 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c         |   2 +-
 src/tusb_option.h                             |   2 +-
 10 files changed, 101 insertions(+), 99 deletions(-)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 1f1aeb462..b4e023165 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -51,117 +51,119 @@
 
 //------------- NXP -------------//
 #if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
-  #define DCD_ATTR_ENDPOINT_MAX   5
+  #define TUP_DCD_ENDPOINT_MAX   5
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
-  #define DCD_ATTR_ENDPOINT_MAX   16
-  #define HCD_ATTR_OHCI
+  #define TUP_DCD_ENDPOINT_MAX   16
+  #define TUP_USBIP_OHCI
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4
   #define TUP_USBIP_CHIPIDEA_HS
-  #define DCD_ATTR_ENDPOINT_MAX     6
-  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01 // Port0 HS, Port1 FS
+  #define TUP_USBIP_EHCI
+
+  #define TUP_DCD_ENDPOINT_MAX     6
+  #define TUP_RHPORT_HIGHSPEED 0x01 // Port0 HS, Port1 FS
 
-  #define HCD_ATTR_EHCI
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
-   #define DCD_ATTR_ENDPOINT_MAX   5
+   #define TUP_DCD_ENDPOINT_MAX   5
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
   // TODO USB0 has 5, USB1 has 6
-  #define DCD_ATTR_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_MAX   6
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
   // TODO USB0 has 5, USB1 has 6
-  #define DCD_ATTR_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_MAX   6
 
 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
   #define TUP_USBIP_CHIPIDEA_HS
-  #define DCD_ATTR_ENDPOINT_MAX     8
-  #define DCD_ATTR_RHPORT_HIGHSPEED 0x03 // Port0 HS, Port1 HS
+  #define TUP_USBIP_EHCI
+
+  #define TUP_DCD_ENDPOINT_MAX     8
+  #define TUP_RHPORT_HIGHSPEED 0x03 // Port0 HS, Port1 HS
 
-  #define HCD_ATTR_EHCI
 
 #elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
-  #define DCD_ATTR_ENDPOINT_MAX   16
+  #define TUP_DCD_ENDPOINT_MAX   16
 
 #elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
-  #define DCD_ATTR_ENDPOINT_MAX   16
+  #define TUP_DCD_ENDPOINT_MAX   16
 
 //------------- Nordic -------------//
 #elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // 8 CBI + 1 ISO
-  #define DCD_ATTR_ENDPOINT_MAX   9
+  #define TUP_DCD_ENDPOINT_MAX   9
 
 //------------- Microchip -------------//
 #elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
       TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(OPT_MCU_SAMG)
-  #define DCD_ATTR_ENDPOINT_MAX   6
-  #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+  #define TUP_DCD_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
 #elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
-  #define DCD_ATTR_ENDPOINT_MAX     10
-  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
-  #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+  #define TUP_DCD_ENDPOINT_MAX     10
+  #define TUP_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
 #elif TU_CHECK_MCU(OPT_MCU_PIC32MZ)
-  #define DCD_ATTR_ENDPOINT_MAX   8
-  #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- ST -------------//
 #elif TU_CHECK_MCU(OPT_MCU_STM32F0)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F1)
   #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
       defined (STM32F107xB) || defined (STM32F107xC)
-    #define DCD_ATTR_ENDPOINT_MAX   4
-
     #define TUP_USBIP_DWC2
-    #define DCD_ATTR_DWC2_STM32
+    #define TUP_USBIP_DWC2_STM32
+
+    #define TUP_DCD_ENDPOINT_MAX   4
   #else
-    #define DCD_ATTR_ENDPOINT_MAX   8
+    #define TUP_DCD_ENDPOINT_MAX   8
   #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F2)
-  // FS has 4 ep, HS has 5 ep
-  #define DCD_ATTR_ENDPOINT_MAX   6
-
   #define TUP_USBIP_DWC2
-  #define DCD_ATTR_DWC2_STM32
+  #define TUP_USBIP_DWC2_STM32
+
+  // FS has 4 ep, HS has 5 ep
+  #define TUP_DCD_ENDPOINT_MAX   6
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F3)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F4)
-  // For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
-  #define DCD_ATTR_ENDPOINT_MAX   6
-
   #define TUP_USBIP_DWC2
-  #define DCD_ATTR_DWC2_STM32
+  #define TUP_USBIP_DWC2_STM32
+
+  // For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
+  #define TUP_DCD_ENDPOINT_MAX   6
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F7)
-  // FS has 6, HS has 9
-  #define DCD_ATTR_ENDPOINT_MAX   9
-
   #define TUP_USBIP_DWC2
-  #define DCD_ATTR_DWC2_STM32
+  #define TUP_USBIP_DWC2_STM32
+
+  // FS has 6, HS has 9
+  #define TUP_DCD_ENDPOINT_MAX   9
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
-  #define DCD_ATTR_ENDPOINT_MAX   9
-
   #define TUP_USBIP_DWC2
-  #define DCD_ATTR_DWC2_STM32
+  #define TUP_USBIP_DWC2_STM32
+
+  #define TUP_DCD_ENDPOINT_MAX   9
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L4)
   #if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
@@ -169,87 +171,87 @@
       defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
       defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
       defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-    #define DCD_ATTR_ENDPOINT_MAX   6
-
     #define TUP_USBIP_DWC2
-    #define DCD_ATTR_DWC2_STM32
+    #define TUP_USBIP_DWC2_STM32
+
+    #define TUP_DCD_ENDPOINT_MAX   6
   #else
-    #define DCD_ATTR_ENDPOINT_MAX   8
+    #define TUP_DCD_ENDPOINT_MAX   8
   #endif
 
 //------------- Sony -------------//
 #elif TU_CHECK_MCU(OPT_MCU_CXD56)
-  #define DCD_ATTR_ENDPOINT_MAX     7
-  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
-  #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+  #define TUP_DCD_ENDPOINT_MAX     7
+  #define TUP_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- TI -------------//
 #elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX   8
 
 //------------- ValentyUSB -------------//
 #elif TU_CHECK_MCU(OPT_MCU_VALENTYUSB_EPTRI)
-  #define DCD_ATTR_ENDPOINT_MAX   16
+  #define TUP_DCD_ENDPOINT_MAX   16
 
 //------------- Nuvoton -------------//
 #elif TU_CHECK_MCU(OPT_MCU_NUC121, OPT_MCU_NUC126)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX   8
 
 #elif TU_CHECK_MCU(OPT_MCU_NUC120)
-  #define DCD_ATTR_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_MAX   6
 
 #elif TU_CHECK_MCU(OPT_MCU_NUC505)
-  #define DCD_ATTR_ENDPOINT_MAX     12
-  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_MAX     12
+  #define TUP_RHPORT_HIGHSPEED 0x01
 
 //------------- Espressif -------------//
 #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-  #define DCD_ATTR_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_MAX   6
 
 //------------- Dialog -------------//
 #elif TU_CHECK_MCU(OPT_MCU_DA1469X)
-  #define DCD_ATTR_ENDPOINT_MAX   4
+  #define TUP_DCD_ENDPOINT_MAX   4
 
 //------------- Raspberry Pi -------------//
 #elif TU_CHECK_MCU(OPT_MCU_RP2040)
-  #define DCD_ATTR_ENDPOINT_MAX   16
+  #define TUP_DCD_ENDPOINT_MAX   16
 
 //------------- Silabs -------------//
 #elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
-  #define DCD_ATTR_ENDPOINT_MAX   7
+  #define TUP_DCD_ENDPOINT_MAX   7
 
 //------------- Renesas -------------//
 #elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
-  #define DCD_ATTR_ENDPOINT_MAX   10
+  #define TUP_DCD_ENDPOINT_MAX   10
 
 //------------- GigaDevice -------------//
 #elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
-  #define DCD_ATTR_ENDPOINT_MAX   4
+  #define TUP_DCD_ENDPOINT_MAX   4
 
 //------------- Broadcom -------------//
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
-  #define DCD_ATTR_ENDPOINT_MAX     8
-  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_MAX     8
+  #define TUP_RHPORT_HIGHSPEED 0x01
 
 //------------- Broadcom -------------//
 #elif TU_CHECK_MCU(OPT_MCU_XMC4000)
-  #define DCD_ATTR_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX   8
 
 //------------- BridgeTek -------------//
 #elif TU_CHECK_MCU(OPT_MCU_FT90X)
-  #define DCD_ATTR_ENDPOINT_MAX     8
-  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_MAX     8
+  #define TUP_RHPORT_HIGHSPEED 0x01
 
 #elif TU_CHECK_MCU(OPT_MCU_FT93X)
-  #define DCD_ATTR_ENDPOINT_MAX     16
-  #define DCD_ATTR_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_MAX     16
+  #define TUP_RHPORT_HIGHSPEED 0x01
 
 //------------ Allwinner -------------//
 #elif TU_CHECK_MCU(OPT_MCU_F1C100S)
-  #define DCD_ATTR_ENDPOINT_MAX   4
+  #define TUP_DCD_ENDPOINT_MAX   4
 
 #endif
 
@@ -257,14 +259,14 @@
 // Default Values
 //--------------------------------------------------------------------+
 
-#ifndef DCD_ATTR_ENDPOINT_MAX
-  #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
-  #define DCD_ATTR_ENDPOINT_MAX   8
+#ifndef TUP_DCD_ENDPOINT_MAX
+  #warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
+  #define TUP_DCD_ENDPOINT_MAX   8
 #endif
 
 // Default to fullspeed if not defined
-#ifndef DCD_ATTR_RHPORT_HIGHSPEED
-  #define DCD_ATTR_RHPORT_HIGHSPEED 0x00
+#ifndef TUP_RHPORT_HIGHSPEED
+  #define TUP_RHPORT_HIGHSPEED 0x00
 #endif
 
 #endif
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 4e725c95a..8efbc90ef 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -40,7 +40,7 @@
 //--------------------------------------------------------------------+
 
 #ifndef CFG_TUD_ENDPPOINT_MAX
-  #define CFG_TUD_ENDPPOINT_MAX   DCD_ATTR_ENDPOINT_MAX
+  #define CFG_TUD_ENDPPOINT_MAX   TUP_DCD_ENDPOINT_MAX
 #endif
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 726c7a517..32c2fc029 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -151,8 +151,8 @@ typedef struct {
   // Must be at 2K alignment
   // Each endpoint with direction (IN/OUT) occupies a queue head
   // for portability, TinyUSB only queue 1 TD for each Qhd
-  dcd_qhd_t qhd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64);
-  dcd_qtd_t qtd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
+  dcd_qhd_t qhd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64);
+  dcd_qtd_t qtd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
 }dcd_data_t;
 
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
@@ -619,7 +619,7 @@ void dcd_int_handler(uint8_t rhport)
 
     if ( edpt_complete )
     {
-      for(uint8_t epnum = 0; epnum < DCD_ATTR_ENDPOINT_MAX; epnum++)
+      for(uint8_t epnum = 0; epnum < TUP_DCD_ENDPOINT_MAX; epnum++)
       {
         if ( tu_bit_test(edpt_complete, epnum)    ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_OUT);
         if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN);
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index ac873455b..acfc561fe 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && defined(HCD_ATTR_EHCI)
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_EHCI)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 71414e737..d36585592 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -170,13 +170,13 @@ static inline void print_block_list(free_block_t const *blk, unsigned num)
 
 static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
 {
-  free_block_t free_blocks[2 * (DCD_ATTR_ENDPOINT_MAX - 1)];
+  free_block_t free_blocks[2 * (TUP_DCD_ENDPOINT_MAX - 1)];
   unsigned num_blocks = 1;
 
   /* Initialize free memory block list */
   free_blocks[0].beg = 64 / 8;
   free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */
-  for (int i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
+  for (int i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
     uint_fast16_t addr;
     int num;
     USB0->EPIDX = i;
@@ -575,7 +575,7 @@ static void process_bus_reset(uint8_t rhport)
   USB0->RXIE = 0; 
 
   /* Clear FIFO settings */
-  for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
+  for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
     USB0->EPIDX     = i;
     USB0->TXFIFOSZ  = 0;
     USB0->TXFIFOADD = 0;
@@ -663,7 +663,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   const unsigned xfer    = ep_desc->bmAttributes.xfer;
   const unsigned mps     = tu_edpt_packet_size(ep_desc);
 
-  TU_ASSERT(epn < DCD_ATTR_ENDPOINT_MAX);
+  TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX);
 
   pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1];
   pipe->buf       = NULL;
@@ -715,7 +715,7 @@ void dcd_edpt_close_all(uint8_t rhport)
   NVIC_DisableIRQ(USB0_IRQn);
   USB0->TXIE = 1; /* Enable only EP0 */
   USB0->RXIE = 0; 
-  for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
+  for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
     regs->TXMAXP = 0;
     regs->TXCSRH = 0;
     if (regs->TXCSRL & USB_TXCSRL1_TXRDY)
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 9f5979ab4..108baf99d 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -179,8 +179,8 @@ typedef struct {
   // Must be at 2K alignment
   // Each endpoint with direction (IN/OUT) occupies a queue head
   // for portability, TinyUSB only queue 1 TD for each Qhd
-  dcd_qhd_t qhd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64);
-  dcd_qtd_t qtd[DCD_ATTR_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
+  dcd_qhd_t qhd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64);
+  dcd_qtd_t qtd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
 }dcd_data_t;
 
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
@@ -647,7 +647,7 @@ void dcd_int_handler(uint8_t rhport)
 
     if ( edpt_complete )
     {
-      for(uint8_t epnum = 0; epnum < DCD_ATTR_ENDPOINT_MAX; epnum++)
+      for(uint8_t epnum = 0; epnum < TUP_DCD_ENDPOINT_MAX; epnum++)
       {
         if ( tu_bit_test(edpt_complete, epnum)    ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_OUT);
         if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN);
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index c9e1061f9..cb4e6dc4a 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && defined(HCD_ATTR_OHCI)
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_OHCI)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 447069f88..27514339b 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -426,7 +426,7 @@ static inline void print_block_list(free_block_t const *blk, unsigned num)
 
 static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
 {
-  free_block_t free_blocks[2 * (DCD_ATTR_ENDPOINT_MAX - 1)];
+  free_block_t free_blocks[2 * (TUP_DCD_ENDPOINT_MAX - 1)];
   unsigned num_blocks = 1;
   /* Backup current EP to restore later */
   u8 backup_ep = USBC_GetActiveEp();
@@ -434,7 +434,7 @@ static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3)
   /* Initialize free memory block list */
   free_blocks[0].beg = 64 / 8;
   free_blocks[0].end = (USB_FIFO_SIZE_KB << 10) / 8; /* 2KiB / 8 bytes */
-  for (int i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
+  for (int i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
     uint_fast16_t addr;
     int num;
     USBC_SelectActiveEp(i);
@@ -974,7 +974,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   const unsigned xfer    = ep_desc->bmAttributes.xfer;
   const unsigned mps     = tu_edpt_packet_size(ep_desc);
 
-  TU_ASSERT(epn < DCD_ATTR_ENDPOINT_MAX);
+  TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX);
 
   pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1];
   pipe->buf       = NULL;
@@ -1033,7 +1033,7 @@ void dcd_edpt_close_all(uint8_t rhport)
   musb_int_mask();
   USBC_Writew(1, USBC_REG_INTTxE(USBC0_BASE)); /* Enable only EP0 */
   USBC_Writew(0, USBC_REG_INTRxE(USBC0_BASE));
-  for (unsigned i = 1; i < DCD_ATTR_ENDPOINT_MAX; ++i) {
+  for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
     USBC_SelectActiveEp(i);
     USBC_Writew(0, USBC_REG_TXMAXP(USBC0_BASE));
 		USBC_Writew((1 << USBC_BP_TXCSR_D_MODE) | (1 << USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_TXCSR_D_FLUSH_FIFO),
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 377f0f44e..a765bc275 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -38,7 +38,7 @@
 #include "device/dcd.h"
 #include "dwc2_type.h"
 
-#if defined(DCD_ATTR_DWC2_STM32)
+#if defined(TUP_USBIP_DWC2_STM32)
   #include "dwc2_stm32.h"
 #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #include "dwc2_esp32.h"
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 3c2207c26..25e536787 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -218,7 +218,7 @@
 #endif
 
 #define CFG_TUD_ENABLED     ( TUD_RHPORT_MODE & OPT_MODE_DEVICE )
-#define TUD_OPT_HIGH_SPEED  ( (TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK) ? (TUD_RHPORT_MODE & OPT_MODE_HIGH_SPEED) : (DCD_ATTR_RHPORT_HIGHSPEED & (1 << TUD_OPT_RHPORT)) )
+#define TUD_OPT_HIGH_SPEED  ( (TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK) ? (TUD_RHPORT_MODE & OPT_MODE_HIGH_SPEED) : (TUP_RHPORT_HIGHSPEED & (1 << TUD_OPT_RHPORT)) )
 
 //------------- Roothub as Host -------------//
 

From a4ba3f2891bad76cb3188159ac8e8dc223175230 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 26 Feb 2022 17:13:06 +0700
Subject: [PATCH 0839/2085] add TUP_USBIP_DWC2

---
 src/common/tusb_mcu.h                 | 111 ++++++++++++++------------
 src/portable/synopsys/dwc2/dcd_dwc2.c |   6 +-
 2 files changed, 59 insertions(+), 58 deletions(-)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index b4e023165..5fc504437 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -51,10 +51,10 @@
 
 //------------- NXP -------------//
 #if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
-  #define TUP_DCD_ENDPOINT_MAX   5
+  #define TUP_DCD_ENDPOINT_MAX    5
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
-  #define TUP_DCD_ENDPOINT_MAX   16
+  #define TUP_DCD_ENDPOINT_MAX    16
   #define TUP_USBIP_OHCI
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
@@ -62,8 +62,8 @@
   #define TUP_USBIP_CHIPIDEA_HS
   #define TUP_USBIP_EHCI
 
-  #define TUP_DCD_ENDPOINT_MAX     6
-  #define TUP_RHPORT_HIGHSPEED 0x01 // Port0 HS, Port1 FS
+  #define TUP_DCD_ENDPOINT_MAX    6
+  #define TUP_RHPORT_HIGHSPEED    0x01 // Port0 HS, Port1 FS
 
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
@@ -71,52 +71,52 @@
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
   // TODO USB0 has 5, USB1 has 6
-  #define TUP_DCD_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_MAX    6
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
   // TODO USB0 has 5, USB1 has 6
-  #define TUP_DCD_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_MAX    6
 
 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
   #define TUP_USBIP_CHIPIDEA_HS
   #define TUP_USBIP_EHCI
 
-  #define TUP_DCD_ENDPOINT_MAX     8
-  #define TUP_RHPORT_HIGHSPEED 0x03 // Port0 HS, Port1 HS
+  #define TUP_DCD_ENDPOINT_MAX    8
+  #define TUP_RHPORT_HIGHSPEED    0x03 // Port0 HS, Port1 HS
 
 
 #elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
-  #define TUP_DCD_ENDPOINT_MAX   16
+  #define TUP_DCD_ENDPOINT_MAX    16
 
 #elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
-  #define TUP_DCD_ENDPOINT_MAX   16
+  #define TUP_DCD_ENDPOINT_MAX    16
 
 //------------- Nordic -------------//
 #elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // 8 CBI + 1 ISO
-  #define TUP_DCD_ENDPOINT_MAX   9
+  #define TUP_DCD_ENDPOINT_MAX    9
 
 //------------- Microchip -------------//
 #elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
       TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_SAMG)
-  #define TUP_DCD_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_MAX    6
   #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
 #elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
-  #define TUP_DCD_ENDPOINT_MAX     10
-  #define TUP_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_MAX    10
+  #define TUP_RHPORT_HIGHSPEED    0x01
   #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
 #elif TU_CHECK_MCU(OPT_MCU_PIC32MZ)
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- ST -------------//
 #elif TU_CHECK_MCU(OPT_MCU_STM32F0)
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F1)
   #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
@@ -124,9 +124,9 @@
     #define TUP_USBIP_DWC2
     #define TUP_USBIP_DWC2_STM32
 
-    #define TUP_DCD_ENDPOINT_MAX   4
+    #define TUP_DCD_ENDPOINT_MAX  4
   #else
-    #define TUP_DCD_ENDPOINT_MAX   8
+    #define TUP_DCD_ENDPOINT_MAX  8
   #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F2)
@@ -134,36 +134,36 @@
   #define TUP_USBIP_DWC2_STM32
 
   // FS has 4 ep, HS has 5 ep
-  #define TUP_DCD_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_MAX    6
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F3)
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F4)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32
 
   // For most mcu, FS has 4, HS has 6. TODO 446/469/479 HS has 9
-  #define TUP_DCD_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_MAX    6
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F7)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32
 
   // FS has 6, HS has 9
-  #define TUP_DCD_ENDPOINT_MAX   9
+  #define TUP_DCD_ENDPOINT_MAX    9
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32
 
-  #define TUP_DCD_ENDPOINT_MAX   9
+  #define TUP_DCD_ENDPOINT_MAX    9
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L4)
   #if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
@@ -174,84 +174,89 @@
     #define TUP_USBIP_DWC2
     #define TUP_USBIP_DWC2_STM32
 
-    #define TUP_DCD_ENDPOINT_MAX   6
+    #define TUP_DCD_ENDPOINT_MAX  6
   #else
-    #define TUP_DCD_ENDPOINT_MAX   8
+    #define TUP_DCD_ENDPOINT_MAX  8
   #endif
 
 //------------- Sony -------------//
 #elif TU_CHECK_MCU(OPT_MCU_CXD56)
-  #define TUP_DCD_ENDPOINT_MAX     7
-  #define TUP_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_MAX    7
+  #define TUP_RHPORT_HIGHSPEED    0x01
   #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- TI -------------//
 #elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx)
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX    8
 
 //------------- ValentyUSB -------------//
 #elif TU_CHECK_MCU(OPT_MCU_VALENTYUSB_EPTRI)
-  #define TUP_DCD_ENDPOINT_MAX   16
+  #define TUP_DCD_ENDPOINT_MAX    16
 
 //------------- Nuvoton -------------//
 #elif TU_CHECK_MCU(OPT_MCU_NUC121, OPT_MCU_NUC126)
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_NUC120)
-  #define TUP_DCD_ENDPOINT_MAX   6
+  #define TUP_DCD_ENDPOINT_MAX    6
 
 #elif TU_CHECK_MCU(OPT_MCU_NUC505)
-  #define TUP_DCD_ENDPOINT_MAX     12
-  #define TUP_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_MAX    12
+  #define TUP_RHPORT_HIGHSPEED    0x01
 
 //------------- Espressif -------------//
 #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-  #define TUP_DCD_ENDPOINT_MAX   6
+  #define TUP_USBIP_DWC2
+  #define TUP_DCD_ENDPOINT_MAX    6
 
 //------------- Dialog -------------//
 #elif TU_CHECK_MCU(OPT_MCU_DA1469X)
-  #define TUP_DCD_ENDPOINT_MAX   4
+  #define TUP_DCD_ENDPOINT_MAX    4
 
 //------------- Raspberry Pi -------------//
 #elif TU_CHECK_MCU(OPT_MCU_RP2040)
-  #define TUP_DCD_ENDPOINT_MAX   16
+  #define TUP_DCD_ENDPOINT_MAX    16
 
 //------------- Silabs -------------//
 #elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
-  #define TUP_DCD_ENDPOINT_MAX   7
+  #define TUP_USBIP_DWC2
+  #define TUP_DCD_ENDPOINT_MAX    7
 
 //------------- Renesas -------------//
 #elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
-  #define TUP_DCD_ENDPOINT_MAX   10
+  #define TUP_DCD_ENDPOINT_MAX    10
 
 //------------- GigaDevice -------------//
 #elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
-  #define TUP_DCD_ENDPOINT_MAX   4
+  #define TUP_USBIP_DWC2
+  #define TUP_DCD_ENDPOINT_MAX    4
 
 //------------- Broadcom -------------//
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
-  #define TUP_DCD_ENDPOINT_MAX     8
-  #define TUP_RHPORT_HIGHSPEED 0x01
+  #define TUP_USBIP_DWC2
+  #define TUP_DCD_ENDPOINT_MAX    8
+  #define TUP_RHPORT_HIGHSPEED    0x01
 
 //------------- Broadcom -------------//
 #elif TU_CHECK_MCU(OPT_MCU_XMC4000)
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_USBIP_DWC2
+  #define TUP_DCD_ENDPOINT_MAX    8
 
 //------------- BridgeTek -------------//
 #elif TU_CHECK_MCU(OPT_MCU_FT90X)
-  #define TUP_DCD_ENDPOINT_MAX     8
-  #define TUP_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_MAX    8
+  #define TUP_RHPORT_HIGHSPEED    0x01
 
 #elif TU_CHECK_MCU(OPT_MCU_FT93X)
-  #define TUP_DCD_ENDPOINT_MAX     16
-  #define TUP_RHPORT_HIGHSPEED 0x01
+  #define TUP_DCD_ENDPOINT_MAX    16
+  #define TUP_RHPORT_HIGHSPEED    0x01
 
 //------------ Allwinner -------------//
 #elif TU_CHECK_MCU(OPT_MCU_F1C100S)
-  #define TUP_DCD_ENDPOINT_MAX   4
+  #define TUP_DCD_ENDPOINT_MAX    4
 
 #endif
 
@@ -261,12 +266,12 @@
 
 #ifndef TUP_DCD_ENDPOINT_MAX
   #warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
-  #define TUP_DCD_ENDPOINT_MAX   8
+  #define TUP_DCD_ENDPOINT_MAX    8
 #endif
 
 // Default to fullspeed if not defined
 #ifndef TUP_RHPORT_HIGHSPEED
-  #define TUP_RHPORT_HIGHSPEED 0x00
+  #define TUP_RHPORT_HIGHSPEED    0x00
 #endif
 
 #endif
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index a765bc275..c71f38d2d 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -29,11 +29,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && \
-    ( defined(TUP_USBIP_DWC2) || \
-      TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_GD32VF103) || \
-      TU_CHECK_MCU(OPT_MCU_EFM32GG, OPT_MCU_BCM2711, OPT_MCU_BCM2835) || \
-      TU_CHECK_MCU(OPT_MCU_BCM2837, OPT_MCU_XMC4000) )
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
 
 #include "device/dcd.h"
 #include "dwc2_type.h"

From 2fe3a925fbee91c1b5d8515c9fba25e5bd8b87a6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 26 Feb 2022 17:34:29 +0700
Subject: [PATCH 0840/2085] add highspeed detect for f723/730/733

---
 src/common/tusb_mcu.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 5fc504437..465e33ec7 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -153,6 +153,11 @@
   // FS has 6, HS has 9
   #define TUP_DCD_ENDPOINT_MAX    9
 
+  // MCU with on-chip HS Phy
+  #if defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F733xx)
+    #define TUP_RHPORT_HIGHSPEED  0x02 // Port 0: FS, Port 1: HS
+  #endif
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32

From 1d29817139c473971ce239bbc2cb5924de4a644e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 1 Mar 2022 23:55:53 +0700
Subject: [PATCH 0841/2085] start to add pio usb (host) support

run as proof of concept
---
 examples/host/cdc_msc_hid/CMakeLists.txt     |   2 +-
 examples/host/cdc_msc_hid/src/tusb_config.h  |   7 +-
 hw/bsp/rp2040/family.c                       |   3 +
 hw/bsp/rp2040/family.cmake                   |  20 +-
 lib/Pico-PIO-USB                             |   1 +
 src/host/hcd.h                               |  13 +-
 src/host/usbh.c                              |  12 +-
 src/host/usbh_control.c                      |   9 +-
 src/portable/raspberrypi/pio/hcd_pio.c       | 237 +++++++++++++++++++
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |   9 +-
 10 files changed, 300 insertions(+), 13 deletions(-)
 create mode 160000 lib/Pico-PIO-USB
 create mode 100644 src/portable/raspberrypi/pio/hcd_pio.c

diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 0a99bc3a9..95c07339e 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
\ No newline at end of file
+family_configure_host_example(${PROJECT})
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index bc6c68e5b..abbe474c2 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -42,7 +42,9 @@
 #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
   #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
 #else
-  #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
+  //#define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
+ // rp2040: port0 is native, port 1 for PIO-USB
+ #define CFG_TUSB_RHPORT1_MODE       OPT_MODE_HOST
 #endif
 
 #ifndef CFG_TUSB_OS
@@ -71,6 +73,9 @@
 // CONFIGURATION
 //--------------------------------------------------------------------
 
+#define CFG_TUH_RPI_PIO            1
+//#define CFG_TUSB_RPI_PIO_INC_PATH   1
+
 // Size of buffer to hold descriptors and other data used for enumeration
 #define CFG_TUH_ENUMERATION_BUFSIZE 256
 
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index fa63dadf5..dcf38b6ec 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -127,6 +127,9 @@ void board_init(void)
 #ifndef BUTTON_BOOTSEL
 #endif
 
+  // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb
+  set_sys_clock_khz(120000, true);
+
 #if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
   bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_TX_PIN, GPIO_FUNC_UART));
   uart_inst = uart_get_instance(UART_DEV);
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 1aa180ef8..ddb34bf7d 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -89,13 +89,27 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/class/hid/hid_host.c
 			${TOP}/src/class/msc/msc_host.c
 			${TOP}/src/class/vendor/vendor_host.c
+
+			${TOP}/src/portable/raspberrypi/pio/hcd_pio.c
+			${TOP}/lib/Pico-PIO-USB/pio_usb.c
+			${TOP}/lib/Pico-PIO-USB/usb_crc.c
 			)
 
-	# Sometimes have to do host specific actions in mostly
-	# common functions
+	# Sometimes have to do host specific actions in mostly common functions
 	target_compile_definitions(tinyusb_host_base INTERFACE
 			RP2040_USB_HOST_MODE=1
 	)
+	
+	# config for host pio
+	target_link_libraries(tinyusb_host_base INTERFACE
+	   hardware_dma
+	   hardware_pio
+	   pico_multicore
+	   )
+	   
+	target_include_directories(tinyusb_host_base INTERFACE
+	   ${TOP}/lib/Pico-PIO-USB
+	   )
 
 	add_library(tinyusb_bsp INTERFACE)
 	target_sources(tinyusb_bsp INTERFACE
@@ -151,6 +165,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		_family_initialize_project(${PROJECT} ${DIR})
 		enable_language(C CXX ASM)
 		pico_sdk_init()
+    pico_generate_pio_header(tinyusb_host_base ${TOP}/lib/Pico-PIO-USB/usb_tx.pio)
+    pico_generate_pio_header(tinyusb_host_base ${TOP}/lib/Pico-PIO-USB/usb_rx.pio)
 	endfunction()
 
 	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
new file mode 160000
index 000000000..7d6729900
--- /dev/null
+++ b/lib/Pico-PIO-USB
@@ -0,0 +1 @@
+Subproject commit 7d672990011695892da523cb0ac29a2c7243a4c9
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 80500f048..9d10104f3 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -143,9 +143,20 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
 // Endpoints API
 //--------------------------------------------------------------------+
 
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
+// Open an endpoint
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
+
+// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
+
+// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
+
+// Optional: some controllers are capable of carry out the whole Control Transfer (setup, data, status)
+// without help of USBH.
+bool hcd_edpt_control_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8], uint8_t* data) TU_ATTR_WEAK;
+
+// clear stall, data toggle is also reset to DATA0
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 130aba40e..ea0a0809d 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -358,12 +358,12 @@ void tuh_task(void)
       case HCD_EVENT_DEVICE_ATTACH:
         // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
         // one device before enumerating another one.
-        TU_LOG2("USBH DEVICE ATTACH\r\n");
+        TU_LOG2("[rh%d] USBH DEVICE ATTACH\r\n", event.rhport);
         enum_new_device(&event);
       break;
 
       case HCD_EVENT_DEVICE_REMOVE:
-        TU_LOG2("USBH DEVICE REMOVED\r\n");
+        TU_LOG2("[rh%d] USBH DEVICE REMOVED\r\n", event.rhport);
         process_device_unplugged(event.rhport, event.connection.hub_addr, event.connection.hub_port);
 
         #if CFG_TUH_HUB
@@ -703,7 +703,9 @@ static bool enum_new_device(hcd_event_t* event)
   if (_dev0.hub_addr == 0)
   {
     // wait until device is stable TODO non blocking
+    hcd_port_reset(_dev0.rhport);
     osal_task_delay(RESET_DELAY);
+    hcd_port_reset_end( _dev0.rhport);
 
     // device unplugged while delaying
     if ( !hcd_port_connect_status(_dev0.rhport) ) return true;
@@ -772,13 +774,17 @@ static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_r
   TU_ASSERT( tu_desc_type(desc_device) == TUSB_DESC_DEVICE );
 
   // Reset device again before Set Address
+  // reset port after 8 byte descriptor
   TU_LOG2("Port reset \r\n");
 
   if (_dev0.hub_addr == 0)
   {
+#if !CFG_TUH_RPI_PIO // skip this reset for pio-usb
     // connected directly to roothub
-    hcd_port_reset( _dev0.rhport ); // reset port after 8 byte descriptor
+    hcd_port_reset(_dev0.rhport);
     osal_task_delay(RESET_DELAY);
+    hcd_port_reset_end(_dev0.rhport);
+#endif
 
     enum_request_set_addr();
   }
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index d034eec7f..1c73d6626 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -71,7 +71,14 @@ bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
   TU_LOG2("\r\n");
 
   // Send setup packet
-  TU_ASSERT( hcd_setup_send(rhport, dev_addr, (uint8_t const*) &_ctrl_xfer.request) );
+  if ( hcd_edpt_control_xfer )
+  {
+    _ctrl_xfer.stage = STAGE_ACK;
+    TU_ASSERT( hcd_edpt_control_xfer(rhport, dev_addr, (uint8_t const*) &_ctrl_xfer.request, buffer) );
+  }else
+  {
+    TU_ASSERT( hcd_setup_send(rhport, dev_addr, (uint8_t const*) &_ctrl_xfer.request) );
+  }
 
   return true;
 }
diff --git a/src/portable/raspberrypi/pio/hcd_pio.c b/src/portable/raspberrypi/pio/hcd_pio.c
new file mode 100644
index 000000000..74df49e0d
--- /dev/null
+++ b/src/portable/raspberrypi/pio/hcd_pio.c
@@ -0,0 +1,237 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && CFG_TUH_RPI_PIO
+
+#include "pico.h"
+#include "hardware/pio.h"
+#include "pio_usb.h"
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "osal/osal.h"
+
+#include "host/hcd.h"
+#include "host/usbh.h"
+
+#define RHPORT_OFFSET     1
+#define RHPORT_PIO(_x)    ((_x)-RHPORT_OFFSET)
+
+
+static usb_device_t *_test_usb_device = NULL;
+static pio_usb_configuration_t pio_host_config = PIO_USB_DEFAULT_CONFIG;
+
+extern root_port_t root_port[PIO_USB_ROOT_PORT_CNT];
+extern usb_device_t usb_device[PIO_USB_DEVICE_CNT];
+extern pio_port_t pio_port[1];
+extern root_port_t root_port[PIO_USB_ROOT_PORT_CNT];
+extern endpoint_t ep_pool[PIO_USB_EP_POOL_CNT];
+
+
+extern port_pin_status_t get_port_pin_status( root_port_t *port);
+extern void configure_fullspeed_host( pio_port_t *pp, const pio_usb_configuration_t *c, root_port_t *port);
+extern void configure_lowspeed_host( pio_port_t *pp, const pio_usb_configuration_t *c, root_port_t *port);
+
+extern void control_setup_transfer( const pio_port_t *pp, uint8_t device_address, uint8_t *tx_data_address, uint8_t tx_data_len);
+extern int control_in_protocol( usb_device_t *device, uint8_t *tx_data, uint16_t tx_length, uint8_t *rx_buffer, uint16_t request_length);
+extern int control_out_protocol( usb_device_t *device, uint8_t *setup_data, uint16_t setup_length, uint8_t *out_data, uint16_t out_length);
+
+extern void update_packet_crc16(usb_setup_packet_t * packet);
+
+//--------------------------------------------------------------------+
+// HCD API
+//--------------------------------------------------------------------+
+bool hcd_init(uint8_t rhport)
+{
+  // To run USB SOF interrupt in core1, create alarm pool in core1.
+  pio_host_config.alarm_pool = (void*)alarm_pool_create(2, 1);
+  _test_usb_device = pio_usb_host_init(&pio_host_config);
+
+  return true;
+}
+
+void hcd_port_reset(uint8_t rhport)
+{
+  rhport = RHPORT_PIO(rhport);
+
+  pio_port_t *pp = &pio_port[0];
+  root_port_t *root = &root_port[rhport];
+
+  pio_sm_set_pins_with_mask(pp->pio_usb_tx, pp->sm_tx, (0b00 << root->pin_dp),
+                            (0b11u << root->pin_dp));
+  pio_sm_set_pindirs_with_mask(pp->pio_usb_tx, pp->sm_tx, (0b11u << root->pin_dp),
+                               (0b11u << root->pin_dp));
+}
+
+void hcd_port_reset_end(uint8_t rhport)
+{
+  rhport = RHPORT_PIO(rhport);
+
+  pio_port_t *pp = &pio_port[0];
+  root_port_t *root = &root_port[rhport];
+
+  pio_sm_set_pindirs_with_mask(pp->pio_usb_tx, pp->sm_tx, (0b00u << root->pin_dp),
+                               (0b11u << root->pin_dp));
+
+  busy_wait_us(100);
+
+  // TODO slow speed
+  bool fullspeed_flag = true;
+
+  if (fullspeed_flag && get_port_pin_status(root) == PORT_PIN_FS_IDLE) {
+    root->root_device = &usb_device[0];
+    if (!root->root_device->connected) {
+      configure_fullspeed_host(pp, &pio_host_config, root);
+      root->root_device->is_fullspeed = true;
+      root->root_device->is_root = true;
+      root->root_device->connected = true;
+      root->root_device->root = root;
+      root->root_device->event = EVENT_CONNECT;
+    }
+  } else if (!fullspeed_flag && get_port_pin_status(root) == PORT_PIN_LS_IDLE) {
+    root->root_device = &usb_device[0];
+    if (!root->root_device->connected) {
+      configure_lowspeed_host(pp, &pio_host_config, root);
+      root->root_device->is_fullspeed = false;
+      root->root_device->is_root = true;
+      root->root_device->connected = true;
+      root->root_device->root = root;
+      root->root_device->event = EVENT_CONNECT;
+    }
+  }
+}
+
+bool hcd_port_connect_status(uint8_t rhport)
+{
+  root_port_t* port = &root_port[0];
+  bool dp = gpio_get(port->pin_dp);
+  bool dm = gpio_get(port->pin_dm);
+  return dp || dm;
+}
+
+tusb_speed_t hcd_port_speed_get(uint8_t rhport)
+{
+  // TODO determine link speed
+  return TUSB_SPEED_FULL;
+}
+
+// Close all opened endpoint belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
+{
+}
+
+uint32_t hcd_frame_number(uint8_t rhport)
+{
+  return 0;
+}
+
+void hcd_int_enable(uint8_t rhport)
+{
+}
+
+void hcd_int_disable(uint8_t rhport)
+{
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
+{
+  rhport = RHPORT_PIO(rhport);
+
+  usb_device[0].event = EVENT_NONE;
+  usb_device[0].address = dev_addr;
+
+  return true;
+}
+
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
+{
+  (void) rhport;
+
+  return true;
+}
+
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
+{
+  (void) rhport;
+  return false;
+}
+
+bool hcd_edpt_control_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8], uint8_t* data)
+{
+  int ret;
+  rhport = RHPORT_PIO(rhport);
+
+  uint16_t const len = ((tusb_control_request_t const*) setup_packet)->wLength;
+
+  usb_setup_packet_t pio_setup = { USB_SYNC, USB_PID_DATA0 };
+  memcpy(&pio_setup.request_type, setup_packet, 8);
+  update_packet_crc16(&pio_setup);
+
+  if (setup_packet[0] & TUSB_DIR_IN_MASK)
+  {
+    ret = control_in_protocol(&usb_device[0], (uint8_t*) &pio_setup, sizeof(pio_setup), data, len);
+  }else
+  {
+    ret = control_out_protocol(&usb_device[0], (uint8_t*) &pio_setup, sizeof(pio_setup), data, len);
+  }
+
+  // TODO current pio is blocking
+  hcd_event_xfer_complete(dev_addr, 0, 0, ret ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS, false);
+
+  return ret == 0;
+}
+
+
+//bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
+//{
+//    // EPX is shared, so multiple device addresses and endpoint addresses share that
+//    // so if any transfer is active on epx, we are busy. Interrupt endpoints have their own
+//    // EPX so ep->active will only be busy if there is a pending transfer on that interrupt endpoint
+//    // on that device
+//    pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\n", dev_addr, ep_addr);
+//    struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
+//    assert(ep);
+//    bool busy = ep->active;
+//    pico_trace("busy == %d\n", busy);
+//    return busy;
+//}
+
+bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
+{
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return true;
+}
+
+#endif
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index b6fbdb200..75acefb65 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && CFG_TUSB_MCU == OPT_MCU_RP2040
+#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO
 
 #include "pico.h"
 #include "rp2040_usb.h"
@@ -40,7 +40,8 @@
 #include "host/hcd.h"
 #include "host/usbh.h"
 
-#define ROOT_PORT 0
+// port 0 is native USB port, other is counted as software PIO
+#define RHPORT_NATIVE 0
 
 //--------------------------------------------------------------------+
 // Low level rp2040 controller functions
@@ -185,11 +186,11 @@ static void hcd_rp2040_irq(void)
         
         if (dev_speed())
         {
-            hcd_event_device_attach(ROOT_PORT, true);
+            hcd_event_device_attach(RHPORT_NATIVE, true);
         }
         else
         {
-            hcd_event_device_remove(ROOT_PORT, true);
+            hcd_event_device_remove(RHPORT_NATIVE, true);
         }
 
         // Clear speed change interrupt

From df4c614597157b540e0936a4555c6a1ba3ac487c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Mar 2022 00:00:11 +0700
Subject: [PATCH 0842/2085] update pio usb submodule

---
 .gitmodules      | 3 +++
 lib/Pico-PIO-USB | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/.gitmodules b/.gitmodules
index fb551060a..9a5d89d00 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -140,3 +140,6 @@
 [submodule "hw/mcu/allwinner"]
 	path = hw/mcu/allwinner
 	url = https://github.com/hathach/allwinner_driver.git
+[submodule "lib/Pico-PIO-USB"]
+	path = lib/Pico-PIO-USB
+	url = https://github.com/hathach/Pico-PIO-USB.git
diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 7d6729900..ee20881ac 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 7d672990011695892da523cb0ac29a2c7243a4c9
+Subproject commit ee20881ac8abc515df5e0cfe8851c7c21c47a0ef

From d3ed76902eaf52a61f19d88c941045ea1fc5b808 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Mar 2022 00:06:13 +0700
Subject: [PATCH 0843/2085] clean up

---
 examples/host/cdc_msc_hid/src/tusb_config.h | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index abbe474c2..e957b2cde 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -39,12 +39,17 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
+#define CFG_TUH_RPI_PIO            1
+//#define CFG_TUSB_RPI_PIO_INC_PATH   1
+
+
 #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
   #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
+#elif CFG_TUH_RPI_PIO
+  // rp2040: port0 is native, port 1 for PIO-USB
+  #define CFG_TUSB_RHPORT1_MODE       OPT_MODE_HOST
 #else
-  //#define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
- // rp2040: port0 is native, port 1 for PIO-USB
- #define CFG_TUSB_RHPORT1_MODE       OPT_MODE_HOST
+  #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
 #endif
 
 #ifndef CFG_TUSB_OS
@@ -73,9 +78,6 @@
 // CONFIGURATION
 //--------------------------------------------------------------------
 
-#define CFG_TUH_RPI_PIO            1
-//#define CFG_TUSB_RPI_PIO_INC_PATH   1
-
 // Size of buffer to hold descriptors and other data used for enumeration
 #define CFG_TUH_ENUMERATION_BUFSIZE 256
 

From 1b338b288c3e1b91f8b2b77ef3305142188f922e Mon Sep 17 00:00:00 2001
From: caleb crome <caleb@crome.org>
Date: Tue, 1 Mar 2022 17:24:28 -0800
Subject: [PATCH 0844/2085] in TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR, _nitfs
 should be 3.

I believe that there is a mistake in the definition of TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR.  The nitfs in the audio descriptor is always 3 regardless of ITF_NUM_TOTAL.
---
 examples/device/uac2_headset/src/usb_descriptors.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index d9510ea4f..342b4fac1 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -86,7 +86,7 @@ enum
 
 #define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin) \
     /* Standard Interface Association Descriptor (IAD) */\
-    TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ ITF_NUM_TOTAL, /*_stridx*/ 0x00),\
+    TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ 3, /*_stridx*/ 0x00),\
     /* Standard AC Interface Descriptor(4.7.1) */\
     TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
     /* Class-Specific AC Interface Header Descriptor(4.7.2) */\

From 918f3e9caec1e5566feac9214b7142b950a3d27c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Mar 2022 12:22:20 +0700
Subject: [PATCH 0845/2085] minor rename

---
 examples/host/cdc_msc_hid/src/tusb_config.h  |  4 ++--
 src/host/usbh.c                              |  2 +-
 src/portable/raspberrypi/pio/hcd_pio.c       |  2 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |  2 +-
 src/tusb_option.h                            | 11 ++++++++---
 5 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index e957b2cde..80ee8cb01 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -39,13 +39,13 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-#define CFG_TUH_RPI_PIO            1
+#define CFG_TUH_RPI_PIO_USB            1
 //#define CFG_TUSB_RPI_PIO_INC_PATH   1
 
 
 #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
   #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
-#elif CFG_TUH_RPI_PIO
+#elif CFG_TUH_RPI_PIO_USB
   // rp2040: port0 is native, port 1 for PIO-USB
   #define CFG_TUSB_RHPORT1_MODE       OPT_MODE_HOST
 #else
diff --git a/src/host/usbh.c b/src/host/usbh.c
index ea0a0809d..1f2a19527 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -779,7 +779,7 @@ static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_r
 
   if (_dev0.hub_addr == 0)
   {
-#if !CFG_TUH_RPI_PIO // skip this reset for pio-usb
+#if !CFG_TUH_RPI_PIO_USB // skip this reset for pio-usb
     // connected directly to roothub
     hcd_port_reset(_dev0.rhport);
     osal_task_delay(RESET_DELAY);
diff --git a/src/portable/raspberrypi/pio/hcd_pio.c b/src/portable/raspberrypi/pio/hcd_pio.c
index 74df49e0d..71645bd45 100644
--- a/src/portable/raspberrypi/pio/hcd_pio.c
+++ b/src/portable/raspberrypi/pio/hcd_pio.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && CFG_TUH_RPI_PIO
+#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && CFG_TUH_RPI_PIO_USB
 
 #include "pico.h"
 #include "hardware/pio.h"
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 75acefb65..53b372fcb 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO
+#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUH_RPI_PIO_USB
 
 #include "pico.h"
 #include "rp2040_usb.h"
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 25e536787..44cdaa3a6 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -252,7 +252,7 @@
 
 
 //--------------------------------------------------------------------+
-// COMMON OPTIONS
+// Common Options (Default)
 //--------------------------------------------------------------------+
 
 // Debug enable to print out error message
@@ -280,7 +280,7 @@
 #endif
 
 //--------------------------------------------------------------------
-// DEVICE OPTIONS
+// Device Options (Default)
 //--------------------------------------------------------------------
 
 #ifndef CFG_TUD_ENDPOINT0_SIZE
@@ -345,7 +345,7 @@
 #endif
 
 //--------------------------------------------------------------------
-// HOST OPTIONS
+// Host Options (Default)
 //--------------------------------------------------------------------
 #if CFG_TUH_ENABLED
   #ifndef CFG_TUH_DEVICE_MAX
@@ -383,6 +383,11 @@
 #define CFG_TUH_VENDOR 0
 #endif
 
+// Enable PIO-USB software host controller
+#ifndef CFG_TUH_RPI_PIO_USB
+#define CFG_TUH_RPI_PIO_USB 0
+#endif
+
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------

From 635fb9dcdd08c736a4b0161381068b51ef4c140e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Mar 2022 12:33:47 +0700
Subject: [PATCH 0846/2085] try to fix ci

---
 src/portable/ehci/ehci.c                     | 4 ++--
 src/portable/mentor/musb/hcd_musb.c          | 5 +++++
 src/portable/ohci/ohci.c                     | 5 +++++
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 5 +++++
 src/portable/renesas/usba/hcd_usba.c         | 5 +++++
 5 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index e2d51dc4b..31e348360 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -160,15 +160,15 @@ void hcd_port_reset(uint8_t rhport)
   regs->portsc = portsc;
 }
 
-#if 0
 void hcd_port_reset_end(uint8_t rhport)
 {
   (void) rhport;
 
+#if 0
   ehci_registers_t* regs = ehci_data.regs;
   regs->portsc_bm.port_reset = 0;
-}
 #endif
+}
 
 bool hcd_port_connect_status(uint8_t rhport)
 {
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 3bfd65b45..85e18e3aa 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -617,6 +617,11 @@ void hcd_port_reset(uint8_t rhport)
   _hcd.need_reset = false;
 }
 
+void hcd_port_reset_end(uint8_t rhport)
+{
+  (void) rhport;
+}
+
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   (void)rhport;
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index cb4e6dc4a..db087716f 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -216,6 +216,11 @@ void hcd_port_reset(uint8_t hostid)
   OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK;
 }
 
+void hcd_port_reset_end(uint8_t rhport)
+{
+  (void) rhport;
+}
+
 bool hcd_port_connect_status(uint8_t hostid)
 {
   (void) hostid;
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 53b372fcb..7bbf00efe 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -387,6 +387,11 @@ void hcd_port_reset(uint8_t rhport)
     // TODO: Nothing to do here yet. Perhaps need to reset some state?
 }
 
+void hcd_port_reset_end(uint8_t rhport)
+{
+  (void) rhport;
+}
+
 bool hcd_port_connect_status(uint8_t rhport)
 {
     pico_trace("hcd_port_connect_status\n");
diff --git a/src/portable/renesas/usba/hcd_usba.c b/src/portable/renesas/usba/hcd_usba.c
index ebb682342..5246ecb94 100644
--- a/src/portable/renesas/usba/hcd_usba.c
+++ b/src/portable/renesas/usba/hcd_usba.c
@@ -620,6 +620,11 @@ void hcd_port_reset(uint8_t rhport)
   _hcd.need_reset = false;
 }
 
+void hcd_port_reset_end(uint8_t rhport)
+{
+  (void) rhport;
+}
+
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   (void)rhport;

From d4d7d35afbfe831b20ba83c2689c678361bfb709 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Mar 2022 13:24:51 +0700
Subject: [PATCH 0847/2085] checkout pio-usb

---
 .github/workflows/build_arm.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 177f1076e..085274eb5 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -82,6 +82,7 @@ jobs:
       run: |
         git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
         echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
+        git submodule update --init lib/Pico-PIO-USB
 
     - name: Set Toolchain URL
       run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz

From fa62d5abc9b1cede44a8e0630d8a28c90cdcdd00 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Mar 2022 21:57:29 +0700
Subject: [PATCH 0848/2085] got interrupt endpoint working

---
 lib/Pico-PIO-USB                       |  2 +-
 src/portable/raspberrypi/pio/hcd_pio.c | 41 ++++++++++++++++++++++++--
 2 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index ee20881ac..92268187f 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit ee20881ac8abc515df5e0cfe8851c7c21c47a0ef
+Subproject commit 92268187f3b0490a43d139ed2cb598b06258011f
diff --git a/src/portable/raspberrypi/pio/hcd_pio.c b/src/portable/raspberrypi/pio/hcd_pio.c
index 71645bd45..8d1903f85 100644
--- a/src/portable/raspberrypi/pio/hcd_pio.c
+++ b/src/portable/raspberrypi/pio/hcd_pio.c
@@ -167,8 +167,45 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 {
   rhport = RHPORT_PIO(rhport);
 
-  usb_device[0].event = EVENT_NONE;
-  usb_device[0].address = dev_addr;
+  usb_device_t *device = &usb_device[0];
+
+  static uint8_t ep_id_idx; // TODO remove later
+
+  if (ep_desc->bEndpointAddress == 0)
+  {
+    device->event = EVENT_NONE;
+    device->address = dev_addr;
+
+    ep_id_idx = 0;
+  }else  if (ep_desc->bmAttributes.xfer == TUSB_XFER_INTERRUPT) // only support interrupt endpoint
+  {
+    endpoint_t *ep = NULL;
+    for ( int ep_pool_idx = 0; ep_pool_idx < PIO_USB_EP_POOL_CNT; ep_pool_idx++ )
+    {
+      if ( ep_pool[ep_pool_idx].ep_num == 0 )
+      {
+        ep = &ep_pool[ep_pool_idx];
+        device->endpoint_id[ep_id_idx] = ep_pool_idx + 1;
+        ep_id_idx++;
+
+        ep->data_id = 0;
+        ep->ep_num = ep_desc->bEndpointAddress;
+        ep->interval = ep_desc->bInterval;
+        ep->interval_counter = 0;
+        ep->size = (uint8_t) tu_edpt_packet_size(ep_desc);
+        ep->attr = EP_ATTR_INTERRUPT;
+
+        break;
+      }
+    }
+
+//    TU_LOG1_INT(device->connected);
+//    TU_LOG1_INT(device->root);
+//    TU_LOG1_INT(device->is_root);
+//    TU_LOG1_INT(device->is_fullspeed);
+//
+//    TU_LOG1_INT(ep_id_idx);
+  }
 
   return true;
 }

From 2cd73ca60234748a15b74a2c346778fcb4f4ee61 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Thu, 3 Mar 2022 16:53:22 -0800
Subject: [PATCH 0849/2085] Add host string descriptor functions

Plus typo fixes, GCC11 array bounds fix, snprintf for malloc-free
debug and pragmas for alignment checks.
---
 src/common/tusb_common.h                     |  2 +-
 src/host/usbh.c                              | 57 +++++++++++++++++++-
 src/host/usbh.h                              | 12 +++++
 src/portable/chipidea/ci_hs/hcd_ci_hs.c      |  1 +
 src/portable/ehci/ehci.c                     |  3 ++
 src/portable/ehci/ehci.h                     |  4 +-
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  3 ++
 7 files changed, 78 insertions(+), 4 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 9b9e2b007..80bb40f77 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -349,7 +349,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
   }
 
   // not found return the key value in hex
-  sprintf(not_found, "0x%08lX", (unsigned long) key);
+  snprintf(not_found, sizeof(not_found), "0x%08lX", (unsigned long) key);
 
   return not_found;
 }
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 130aba40e..a3c6c3a04 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -258,6 +258,60 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
   return true;
 }
 
+uint8_t tuh_i_manufacturer_get(uint8_t dev_addr) {
+  TU_VERIFY(tuh_mounted(dev_addr));
+  usbh_device_t const* dev = get_device(dev_addr);
+
+  return dev->i_manufacturer;
+}
+
+uint8_t tuh_i_serial_get(uint8_t dev_addr) {
+  TU_VERIFY(tuh_mounted(dev_addr));
+  usbh_device_t const* dev = get_device(dev_addr);
+
+  return dev->i_serial;
+}
+
+uint8_t tuh_i_product_get(uint8_t dev_addr) {
+  TU_VERIFY(tuh_mounted(dev_addr));
+  usbh_device_t const* dev = get_device(dev_addr);
+
+  return dev->i_product;
+}
+
+static tuh_complete_cb_t string_get_cb;
+
+static bool string_get_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result) {
+  if (string_get_cb != NULL) {
+    TU_LOG2("string get done %d\r\n", result);
+    string_get_cb(result);
+  }
+  string_get_cb = NULL;
+  return true;
+}
+
+bool tuh_string_get(uint8_t dev_addr, uint8_t string_index, uint16_t* buf, size_t len, tuh_complete_cb_t complete_cb) {
+  if (string_get_cb != NULL) {
+    return false;
+  }
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_STANDARD,
+      .direction = TUSB_DIR_IN
+    },
+    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+    .wValue   = TUSB_DESC_STRING << 8 | string_index,
+    .wIndex   = 0,
+    .wLength  = len * sizeof(uint16_t)
+  };
+  string_get_cb = complete_cb;
+  TU_ASSERT( tuh_control_xfer(dev_addr, &request, buf, string_get_complete) );
+  return true;
+}
+
 tusb_speed_t tuh_speed_get (uint8_t dev_addr)
 {
   return (tusb_speed_t) (dev_addr ? get_device(dev_addr)->speed : _dev0.speed);
@@ -561,6 +615,7 @@ void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port
       tu_memclr(dev->ep_status, sizeof(dev->ep_status));
 
       dev->state = TUSB_DEVICE_STATE_UNPLUG;
+      dev->configured = false;
     }
   }
 }
@@ -609,7 +664,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
 
 //--------------------------------------------------------------------+
 // Enumeration Process
-// is a lengthy process with a seires of control transfer to configure
+// is a lengthy process with a series of control transfer to configure
 // newly attached device. Each step is handled by a function in this
 // section
 // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 8411cad28..98e83fc3c 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -38,6 +38,7 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+typedef bool (*tuh_complete_cb_t)(xfer_result_t result);
 typedef bool (*tuh_control_complete_cb_t)(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 
 //--------------------------------------------------------------------+
@@ -58,6 +59,17 @@ extern void hcd_int_handler(uint8_t rhport);
 #define tuh_int_handler   hcd_int_handler
 
 bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid);
+
+// Gets the string indices for common device descriptor data.
+uint8_t tuh_i_manufacturer_get(uint8_t dev_addr);
+uint8_t tuh_i_serial_get(uint8_t dev_addr);
+uint8_t tuh_i_product_get(uint8_t dev_addr);
+
+// Reads the string descriptor at the string index into the buffer. This is the
+// full response so the first entry is the length and the constant 0x03 for
+// string descriptor type.
+bool tuh_string_get(uint8_t dev_addr, uint8_t string_index, uint16_t* buf, size_t len, tuh_complete_cb_t complete_cb);
+
 tusb_speed_t tuh_speed_get(uint8_t dev_addr);
 
 // Check if device is connected and configured
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 0754b477e..221721b0f 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -35,6 +35,7 @@
 // INCLUDE
 //--------------------------------------------------------------------+
 #include "common/tusb_common.h"
+#include "host/hcd.h"
 #include "portable/ehci/ehci_api.h"
 #include "ci_hs_type.h"
 
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index e2d51dc4b..6723e99e9 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -189,7 +189,10 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
       prev = list_next(prev) )
   {
     // TODO check type for ISO iTD and siTD
+    #pragma GCC diagnostic push
+    #pragma GCC diagnostic ignored "-Wcast-align"
     ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev);
+    #pragma GCC diagnostic pop
     if ( qhd->dev_addr == dev_addr )
     {
       // TODO deactive all TD, wait for QHD to inactive before removal
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index c2bee67a5..ff9ae12e7 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -101,8 +101,8 @@ typedef struct
 
 	// Word 2: qTQ Token
 	volatile uint32_t ping_err             : 1  ; ///< For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator
-	volatile uint32_t non_hs_split_state   : 1  ; ///< Used by HC to track the state of slipt transaction
-	volatile uint32_t non_hs_missed_uframe : 1  ; ///< HC misses a complete slip transaction
+	volatile uint32_t non_hs_split_state   : 1  ; ///< Used by HC to track the state of split transaction
+	volatile uint32_t non_hs_missed_uframe : 1  ; ///< HC misses a complete split transaction
 	volatile uint32_t xact_err             : 1  ; ///< Error (Timeout, CRC, Bad PID ... )
 	volatile uint32_t babble_err           : 1  ; ///< Babble detected, also set Halted bit to 1
 	volatile uint32_t buffer_err           : 1  ; ///< Data overrun/underrun error
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 293cefaf6..be02493f0 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -58,8 +58,11 @@ void rp2040_usb_init(void)
   unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
 
   // Clear any previous state just in case
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
   memset(usb_hw, 0, sizeof(*usb_hw));
   memset(usb_dpram, 0, sizeof(*usb_dpram));
+#pragma GCC diagnostic pop
 
   // Mux the controller to the onboard usb phy
   usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;

From eb6b5d1219562e417d879c6d13e0a19eef169ad7 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Thu, 3 Mar 2022 21:57:44 -0800
Subject: [PATCH 0850/2085] Unused ok

---
 src/host/usbh.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index a3c6c3a04..a61f40910 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -282,8 +282,9 @@ uint8_t tuh_i_product_get(uint8_t dev_addr) {
 static tuh_complete_cb_t string_get_cb;
 
 static bool string_get_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result) {
+  (void) dev_addr;
+  (void) request;
   if (string_get_cb != NULL) {
-    TU_LOG2("string get done %d\r\n", result);
     string_get_cb(result);
   }
   string_get_cb = NULL;

From f72da8ee7d7082f9c2f1d796cfb03dcdd1c6d673 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 14:45:26 +0700
Subject: [PATCH 0851/2085] fix build with esp32s2, also use dwc2 for esp
 example

---
 examples/device/hid_composite_freertos/src/CMakeLists.txt | 2 +-
 src/portable/espressif/esp32sx/dcd_esp32sx.c              | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt
index 5d9fc74d3..25da8fcd7 100644
--- a/examples/device/hid_composite_freertos/src/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt
@@ -31,5 +31,5 @@ target_sources(${COMPONENT_TARGET} PUBLIC
   "${TOP}/src/class/net/ncm_device.c"
   "${TOP}/src/class/usbtmc/usbtmc_device.c"
   "${TOP}/src/class/vendor/vendor_device.c"
-  "${TOP}/src/portable/espressif/esp32sx/dcd_esp32sx.c"
+  "${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c"
 )
diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index 99cd08e4d..bd8805dd3 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -34,7 +34,6 @@
 #include "freertos/xtensa_api.h"
 #include "esp_intr_alloc.h"
 #include "esp_log.h"
-#include "driver/gpio.h"
 #include "soc/dport_reg.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/usb_periph.h"

From c0195fc6270394a489faf29fe8fc42dff48bcff1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 14:48:29 +0700
Subject: [PATCH 0852/2085] skip pyocd reset after flash

---
 examples/rules.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/rules.mk b/examples/rules.mk
index 97f6956fa..538dffbcf 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -199,7 +199,7 @@ flash-xfel: $(BUILD)/$(PROJECT)-sunxi.bin
 PYOCD_OPTION ?=
 flash-pyocd: $(BUILD)/$(PROJECT).hex
 	pyocd flash -t $(PYOCD_TARGET) $(PYOCD_OPTION) $<
-	pyocd reset -t $(PYOCD_TARGET)
+	#pyocd reset -t $(PYOCD_TARGET)
 
 # Flash using openocd
 OPENOCD_OPTION ?=

From 96165a1950140c585db4b739709d079228c3320a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 17:07:04 +0700
Subject: [PATCH 0853/2085] rename HCD_MAX_XFER to CFG_TUH_ENDPOINT_MAX

minor clean up
---
 src/host/hcd.h                               | 26 ++++++++++----------
 src/host/hub.c                               |  2 +-
 src/portable/ehci/ehci.c                     | 13 ++++++----
 src/portable/nxp/khci/hcd_khci.c             |  8 +++---
 src/portable/ohci/ohci.c                     |  4 +--
 src/portable/ohci/ohci.h                     |  4 ++-
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  1 +
 7 files changed, 32 insertions(+), 26 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 80500f048..d50fc2d60 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -35,6 +35,19 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Configuration
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUH_ENDPOINT_MAX
+  #define CFG_TUH_ENDPOINT_MAX   (CFG_TUH_DEVICE_MAX*(CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3))
+//  #ifdef TUP_HCD_ENDPOINT_MAX
+//    #define CFG_TUH_ENDPPOINT_MAX   TUP_HCD_ENDPOINT_MAX
+//  #else
+//    #define
+//  #endif
+#endif
+
  //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -81,17 +94,6 @@ typedef struct
 
 } hcd_event_t;
 
-#if CFG_TUH_ENABLED
-// Max number of endpoints per device
-enum {
-  // TODO better computation
-  HCD_MAX_ENDPOINT = CFG_TUH_DEVICE_MAX*(CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3),
-  HCD_MAX_XFER     = HCD_MAX_ENDPOINT*2,
-};
-
-//#define HCD_MAX_ENDPOINT 16
-//#define HCD_MAX_XFER 16
-
 typedef struct {
   uint8_t rhport;
   uint8_t hub_addr;
@@ -99,8 +101,6 @@ typedef struct {
   uint8_t speed;
 } hcd_devtree_info_t;
 
-#endif
-
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
diff --git a/src/host/hub.c b/src/host/hub.c
index 53eb1d521..1fec8b892 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -54,7 +54,7 @@ static inline hub_interface_t* get_itf(uint8_t dev_addr)
   return &hub_data[dev_addr-1-CFG_TUH_DEVICE_MAX];
 }
 
-#if CFG_TUSB_DEBUG
+#if CFG_TUSB_DEBUG >= 2
 static char const* const _hub_feature_str[] =
 {
   [HUB_FEATURE_PORT_CONNECTION          ] = "PORT_CONNECTION",
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 6723e99e9..bc0b7b89a 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -58,6 +58,8 @@
 
 #define FRAMELIST_SIZE                  (1024 >> FRAMELIST_SIZE_BIT_VALUE)
 
+#define HCD_MAX_XFER      CFG_TUH_ENDPOINT_MAX
+
 typedef struct
 {
   ehci_link_t period_framelist[FRAMELIST_SIZE];
@@ -73,7 +75,7 @@ typedef struct
     ehci_qtd_t qtd;
   }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
 
-  ehci_qhd_t qhd_pool[HCD_MAX_ENDPOINT];
+  ehci_qhd_t qhd_pool[CFG_TUH_ENDPOINT_MAX];
   ehci_qtd_t qtd_pool[HCD_MAX_XFER] TU_ATTR_ALIGNED(32);
 
   ehci_registers_t* regs;
@@ -189,6 +191,7 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
       prev = list_next(prev) )
   {
     // TODO check type for ISO iTD and siTD
+    // TODO Suppress cast-align warning
     #pragma GCC diagnostic push
     #pragma GCC diagnostic ignored "-Wcast-align"
     ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev);
@@ -477,7 +480,7 @@ static void async_advance_isr(uint8_t rhport)
   (void) rhport;
 
   ehci_qhd_t* qhd_pool = ehci_data.qhd_pool;
-  for(uint32_t i = 0; i < HCD_MAX_ENDPOINT; i++)
+  for(uint32_t i = 0; i < CFG_TUH_ENDPOINT_MAX; i++)
   {
     if ( qhd_pool[i].removing )
     {
@@ -545,7 +548,7 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms)
   // TODO abstract max loop guard for period
   while( !next_item.terminate &&
       !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) &&
-      max_loop < (HCD_MAX_ENDPOINT + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUH_DEVICE_MAX)
+      max_loop < (CFG_TUH_ENDPOINT_MAX + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUH_DEVICE_MAX)
   {
     switch ( next_item.type )
     {
@@ -717,7 +720,7 @@ void hcd_int_handler(uint8_t rhport)
 //------------- queue head helper -------------//
 static inline ehci_qhd_t* qhd_find_free (void)
 {
-  for (uint32_t i=0; i<HCD_MAX_ENDPOINT; i++)
+  for (uint32_t i=0; i<CFG_TUH_ENDPOINT_MAX; i++)
   {
     if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i];
   }
@@ -734,7 +737,7 @@ static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr)
 {
   ehci_qhd_t* qhd_pool = ehci_data.qhd_pool;
 
-  for(uint32_t i=0; i<HCD_MAX_ENDPOINT; i++)
+  for(uint32_t i=0; i<CFG_TUH_ENDPOINT_MAX; i++)
   {
     if ( (qhd_pool[i].dev_addr == dev_addr) &&
           ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) )
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index fc0875cfe..0f5fa6275 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -125,7 +125,7 @@ typedef struct
     uint16_t            bda[2*2];
   };
   endpoint_state_t endpoint[2];
-  pipe_state_t pipe[HCD_MAX_XFER * 2];
+  pipe_state_t pipe[CFG_TUH_ENDPOINT_MAX * 2];
   uint32_t     in_progress; /* Bitmap. Each bit indicates that a transfer of the corresponding pipe is in progress */
   uint32_t     pending;     /* Bitmap. Each bit indicates that a transfer of the corresponding pipe will be resume the next frame */
   bool         need_reset;  /* The device has not been reset after connection. */
@@ -142,7 +142,7 @@ int find_pipe(uint8_t dev_addr, uint8_t ep_addr)
 {
   /* Find the target pipe */
   int num;
-  for (num = 0; num < HCD_MAX_XFER * 2; ++num) {
+  for (num = 0; num < CFG_TUH_ENDPOINT_MAX * 2; ++num) {
     pipe_state_t *p = &_hcd.pipe[num];
     if ((p->dev_addr == dev_addr) && (p->ep_addr == ep_addr))
       return num;
@@ -463,7 +463,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
   const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
   pipe_state_t *p   = &_hcd.pipe[0];
-  pipe_state_t *end = &_hcd.pipe[HCD_MAX_XFER * 2];
+  pipe_state_t *end = &_hcd.pipe[CFG_TUH_ENDPOINT_MAX * 2];
   for (;p != end; ++p) {
     if (p->dev_addr == dev_addr)
       tu_memclr(p, sizeof(*p));
@@ -511,7 +511,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   // TU_LOG1("O %u %x\n", dev_addr, ep_addr);
   /* Find a free pipe */
   pipe_state_t *p = &_hcd.pipe[0];
-  pipe_state_t *end = &_hcd.pipe[HCD_MAX_XFER * 2];
+  pipe_state_t *end = &_hcd.pipe[CFG_TUH_ENDPOINT_MAX * 2];
   if (dev_addr || ep_addr) {
     p += 2;
     for (; p < end && (p->dev_addr || p->ep_addr); ++p) ;
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index cb4e6dc4a..c82b9352c 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -313,7 +313,7 @@ static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
 
   ohci_ed_t* ed_pool = ohci_data.ed_pool;
 
-  for(uint32_t i=0; i<HCD_MAX_ENDPOINT; i++)
+  for(uint32_t i=0; i<CFG_TUH_ENDPOINT_MAX; i++)
   {
     if ( (ed_pool[i].dev_addr == dev_addr) &&
           ep_addr == tu_edpt_addr(ed_pool[i].ep_number, ed_pool[i].pid == PID_IN) )
@@ -329,7 +329,7 @@ static ohci_ed_t * ed_find_free(void)
 {
   ohci_ed_t* ed_pool = ohci_data.ed_pool;
 
-  for(uint8_t i = 0; i < HCD_MAX_ENDPOINT; i++)
+  for(uint8_t i = 0; i < CFG_TUH_ENDPOINT_MAX; i++)
   {
     if ( !ed_pool[i].used ) return &ed_pool[i];
   }
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index 8db097b06..a1d74580b 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -42,6 +42,8 @@ enum {
   OHCI_MAX_ITD = 4
 };
 
+#define HCD_MAX_XFER      CFG_TUH_ENDPOINT_MAX
+
 //--------------------------------------------------------------------+
 // OHCI Data Structure
 //--------------------------------------------------------------------+
@@ -162,7 +164,7 @@ typedef struct TU_ATTR_ALIGNED(256)
   }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
 
   //  ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
-  ohci_ed_t ed_pool[HCD_MAX_ENDPOINT];
+  ohci_ed_t ed_pool[CFG_TUH_ENDPOINT_MAX];
   ohci_gtd_t gtd_pool[HCD_MAX_XFER];
 
   volatile uint16_t frame_number_hi;
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index be02493f0..9c3e5d011 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -58,6 +58,7 @@ void rp2040_usb_init(void)
   unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
 
   // Clear any previous state just in case
+  // TODO Suppress warning array-bounds with gcc11
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Warray-bounds"
   memset(usb_hw, 0, sizeof(*usb_hw));

From 039b235ca4e8c7b2d201a32a7b1d156ac81382b3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 17:16:14 +0700
Subject: [PATCH 0854/2085] adding new libusb api example

---
 examples/host/CMakeLists.txt               |  1 +
 examples/host/libusb_api/CMakeLists.txt    | 27 ++++++
 examples/host/libusb_api/Makefile          | 28 +++++++
 examples/host/libusb_api/only.txt          |  9 ++
 examples/host/libusb_api/src/main.c        | 98 ++++++++++++++++++++++
 examples/host/libusb_api/src/tusb_config.h | 94 +++++++++++++++++++++
 6 files changed, 257 insertions(+)
 create mode 100644 examples/host/libusb_api/CMakeLists.txt
 create mode 100644 examples/host/libusb_api/Makefile
 create mode 100644 examples/host/libusb_api/only.txt
 create mode 100644 examples/host/libusb_api/src/main.c
 create mode 100644 examples/host/libusb_api/src/tusb_config.h

diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt
index 5c63ec0c0..38db6c6cc 100644
--- a/examples/host/CMakeLists.txt
+++ b/examples/host/CMakeLists.txt
@@ -8,3 +8,4 @@ family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
 # family_add_subdirectory will filter what to actually add based on selected FAMILY
 family_add_subdirectory(cdc_msc_hid)
 family_add_subdirectory(hid_controller)
+family_add_subdirectory(libusb_api)
diff --git a/examples/host/libusb_api/CMakeLists.txt b/examples/host/libusb_api/CMakeLists.txt
new file mode 100644
index 000000000..bff281a8c
--- /dev/null
+++ b/examples/host/libusb_api/CMakeLists.txt
@@ -0,0 +1,27 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/host/libusb_api/Makefile b/examples/host/libusb_api/Makefile
new file mode 100644
index 000000000..c59369ffa
--- /dev/null
+++ b/examples/host/libusb_api/Makefile
@@ -0,0 +1,28 @@
+include ../../../tools/top.mk
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += \
+	src/main.c
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+# TODO: suppress warning caused by host stack
+CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
+
+# TinyUSB Host Stack source
+SRC_C += \
+	src/class/cdc/cdc_host.c \
+	src/class/hid/hid_host.c \
+	src/class/msc/msc_host.c \
+	src/host/hub.c \
+	src/host/usbh.c \
+	src/host/usbh_control.c \
+	src/portable/ohci/ohci.c \
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+
+include ../../rules.mk
diff --git a/examples/host/libusb_api/only.txt b/examples/host/libusb_api/only.txt
new file mode 100644
index 000000000..7fe4e3f5c
--- /dev/null
+++ b/examples/host/libusb_api/only.txt
@@ -0,0 +1,9 @@
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MIMXRT10XX
+mcu:RP2040
+mcu:MSP432E4
+mcu:RX65X
diff --git a/examples/host/libusb_api/src/main.c b/examples/host/libusb_api/src/main.c
new file mode 100644
index 000000000..810f8e762
--- /dev/null
+++ b/examples/host/libusb_api/src/main.c
@@ -0,0 +1,98 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* This example current worked and tested with following controller
+ * - Sony DualShock 4 [CUH-ZCT2x] VID = 0x054c, PID = 0x09cc
+ */
+
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+void led_blinking_task(void);
+
+extern void cdc_task(void);
+extern void hid_app_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  printf("TinyUSB Host HID Controller Example\r\n");
+  printf("Note: Events only displayed for explictly supported controllers\r\n");
+
+  tusb_init();
+
+  while (1)
+  {
+    // tinyusb host task
+    tuh_task();
+    led_blinking_task();
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted (configured)
+void tuh_mount_cb (uint8_t dev_addr)
+{
+  printf("Device attached, address = %d\r\n", dev_addr);
+}
+
+/// Invoked when device is unmounted (bus reset/unplugged)
+void tuh_umount_cb(uint8_t dev_addr)
+{
+  printf("Device removed, address = %d\r\n", dev_addr);
+}
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  const uint32_t interval_ms = 1000;
+  static uint32_t start_ms = 0;
+
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  start_ms += interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/host/libusb_api/src/tusb_config.h b/examples/host/libusb_api/src/tusb_config.h
new file mode 100644
index 000000000..234eca402
--- /dev/null
+++ b/examples/host/libusb_api/src/tusb_config.h
@@ -0,0 +1,94 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+  #error CFG_TUSB_MCU must be defined
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
+#else
+  #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS                 OPT_OS_NONE
+#endif
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+// only hub class is enabled
+#define CFG_TUH_HUB                 1
+
+// max device support (excluding hub device)
+// 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1)
+
+#define CFG_TUH_ENDPOINT_MAX       8
+
+//------------- HID -------------//
+
+#define CFG_TUH_HID_EP_BUFSIZE      64
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */

From 3a7d1cfead0d3147425c305d778723a505900d48 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 17:26:21 +0700
Subject: [PATCH 0855/2085] minor cleanup

---
 examples/host/libusb_api/src/main.c | 10 +++++++---
 src/host/usbh.c                     | 13 +++++--------
 2 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/examples/host/libusb_api/src/main.c b/examples/host/libusb_api/src/main.c
index 810f8e762..07dae1dc6 100644
--- a/examples/host/libusb_api/src/main.c
+++ b/examples/host/libusb_api/src/main.c
@@ -40,9 +40,6 @@
 //--------------------------------------------------------------------+
 void led_blinking_task(void);
 
-extern void cdc_task(void);
-extern void hid_app_task(void);
-
 /*------------- MAIN -------------*/
 int main(void)
 {
@@ -67,10 +64,17 @@ int main(void)
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
 
+void print_device_descriptor(uint8_t dev_addr)
+{
+  printf("Device Descriptor:\r\n");
+
+}
+
 // Invoked when device is mounted (configured)
 void tuh_mount_cb (uint8_t dev_addr)
 {
   printf("Device attached, address = %d\r\n", dev_addr);
+  print_device_descriptor(dev_addr);
 }
 
 /// Invoked when device is unmounted (bus reset/unplugged)
diff --git a/src/host/usbh.c b/src/host/usbh.c
index a61f40910..d655ee7ca 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -37,11 +37,6 @@
 // USBH Configuration
 //--------------------------------------------------------------------+
 
-// TODO remove,update
-#ifndef CFG_TUH_EP_MAX
-#define CFG_TUH_EP_MAX          9
-#endif
-
 #ifndef CFG_TUH_TASK_QUEUE_SZ
 #define CFG_TUH_TASK_QUEUE_SZ   16
 #endif
@@ -72,7 +67,7 @@ typedef struct
 } usbh_dev0_t;
 
 typedef struct {
-  // port
+  // port, must be same layout as usbh_dev0_t
   uint8_t rhport;
   uint8_t hub_addr;
   uint8_t hub_port;
@@ -102,7 +97,7 @@ typedef struct {
   volatile uint8_t state;            // device state, value from enum tusbh_device_state_t
 
   uint8_t itf2drv[16];               // map interface number to driver (0xff is invalid)
-  uint8_t ep2drv[CFG_TUH_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid )
+  uint8_t ep2drv[CFG_TUH_ENDPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid )
 
   struct TU_ATTR_PACKED
   {
@@ -111,7 +106,7 @@ typedef struct {
     volatile bool claimed : 1;
 
     // TODO merge ep2drv here, 4-bit should be sufficient
-  }ep_status[CFG_TUH_EP_MAX][2];
+  }ep_status[CFG_TUH_ENDPOINT_MAX][2];
 
   // Mutex for claiming endpoint, only needed when using with preempted RTOS
 #if CFG_TUSB_OS != OPT_OS_NONE
@@ -344,6 +339,8 @@ bool tuh_init(uint8_t rhport)
 
   TU_LOG2("USBH init\r\n");
 
+  TU_LOG2_INT(sizeof(usbh_device_t));
+
   tu_memclr(_usbh_devices, sizeof(_usbh_devices));
   tu_memclr(&_dev0, sizeof(_dev0));
 

From e08a875d52792c03e1e7cd114f0f3f7013c36210 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 19:26:54 +0700
Subject: [PATCH 0856/2085] add tuh_descriptor_get() and
 tuh_descriptor_device_get()

---
 src/common/tusb_common.h |  1 +
 src/device/usbd.c        |  1 +
 src/host/usbh.c          | 64 ++++++++++++++++++++--------------------
 src/host/usbh.h          | 39 ++++++++++++++----------
 4 files changed, 58 insertions(+), 47 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 80bb40f77..26865805e 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -38,6 +38,7 @@
 #define TU_MIN(_x, _y)        ( ( (_x) < (_y) ) ? (_x) : (_y) )
 #define TU_MAX(_x, _y)        ( ( (_x) > (_y) ) ? (_x) : (_y) )
 
+#define TU_U16(_high, _low)   ((uint16_t) (((_high) << 8) | (_low)))
 #define TU_U16_HIGH(_u16)     ((uint8_t) (((_u16) >> 8) & 0x00ff))
 #define TU_U16_LOW(_u16)      ((uint8_t) ((_u16)       & 0x00ff))
 #define U16_TO_U8S_BE(_u16)   TU_U16_HIGH(_u16), TU_U16_LOW(_u16)
diff --git a/src/device/usbd.c b/src/device/usbd.c
index c20bab76b..7926689b7 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -407,6 +407,7 @@ bool tud_init (uint8_t rhport)
   if ( tud_inited() ) return true;
 
   TU_LOG2("USBD init\r\n");
+  TU_LOG2_INT(sizeof(usbd_device_t));
 
   tu_varclr(&_usbd_dev);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index d655ee7ca..4c3bda4b0 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -96,7 +96,7 @@ typedef struct {
   //------------- device -------------//
   volatile uint8_t state;            // device state, value from enum tusbh_device_state_t
 
-  uint8_t itf2drv[16];               // map interface number to driver (0xff is invalid)
+  uint8_t itf2drv[8];               // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUH_ENDPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid )
 
   struct TU_ATTR_PACKED
@@ -253,6 +253,34 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
   return true;
 }
 
+
+bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index,
+                        void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+{
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_STANDARD,
+      .direction = TUSB_DIR_IN
+    },
+    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+    .wValue   = tu_htole16( TU_U16(type, index) ),
+    .wIndex   = 0,
+    .wLength  = len
+  };
+
+  TU_ASSERT( tuh_control_xfer(daddr, &request, buffer, complete_cb) );
+
+  return true;
+}
+
+bool tuh_descriptor_device_get(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+{
+  return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb);
+}
+
 uint8_t tuh_i_manufacturer_get(uint8_t dev_addr) {
   TU_VERIFY(tuh_mounted(dev_addr));
   usbh_device_t const* dev = get_device(dev_addr);
@@ -338,7 +366,6 @@ bool tuh_init(uint8_t rhport)
   if (_usbh_initialized) return _usbh_initialized;
 
   TU_LOG2("USBH init\r\n");
-
   TU_LOG2_INT(sizeof(usbh_device_t));
 
   tu_memclr(_usbh_devices, sizeof(_usbh_devices));
@@ -785,23 +812,10 @@ static bool enum_request_addr0_device_desc(void)
   uint8_t const addr0 = 0;
   TU_ASSERT( usbh_edpt_control_open(addr0, 8) );
 
-  //------------- Get first 8 bytes of device descriptor to get Control Endpoint Size -------------//
+  // Get first 8 bytes of device descriptor for Control Endpoint size
   TU_LOG2("Get 8 byte of Device Descriptor\r\n");
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
-    },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = TUSB_DESC_DEVICE << 8,
-    .wIndex   = 0,
-    .wLength  = 8
-  };
-  TU_ASSERT( tuh_control_xfer(addr0, &request, _usbh_ctrl_buf, enum_get_addr0_device_desc_complete) );
 
+  TU_ASSERT(tuh_descriptor_device_get(addr0, _usbh_ctrl_buf, 8, enum_get_addr0_device_desc_complete));
   return true;
 }
 
@@ -909,22 +923,8 @@ static bool enum_set_address_complete(uint8_t dev_addr, tusb_control_request_t c
 
   // Get full device descriptor
   TU_LOG2("Get Device Descriptor\r\n");
-  tusb_control_request_t const new_request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
-    },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = TUSB_DESC_DEVICE << 8,
-    .wIndex   = 0,
-    .wLength  = sizeof(tusb_desc_device_t)
-  };
-
-  TU_ASSERT(tuh_control_xfer(new_addr, &new_request, _usbh_ctrl_buf, enum_get_device_desc_complete));
 
+  TU_ASSERT(tuh_descriptor_device_get(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), enum_get_device_desc_complete));
   return true;
 }
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 98e83fc3c..9af139283 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -39,7 +39,7 @@
 //--------------------------------------------------------------------+
 
 typedef bool (*tuh_complete_cb_t)(xfer_result_t result);
-typedef bool (*tuh_control_complete_cb_t)(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+typedef bool (*tuh_control_complete_cb_t)(uint8_t daddr, tusb_control_request_t const * request, xfer_result_t result);
 
 //--------------------------------------------------------------------+
 // APPLICATION API
@@ -58,40 +58,49 @@ void tuh_task(void);
 extern void hcd_int_handler(uint8_t rhport);
 #define tuh_int_handler   hcd_int_handler
 
-bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid);
+//------------- descriptors -------------//
+
+// Get an descriptor
+bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index,
+                        void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+
+// Get device descriptor
+bool tuh_descriptor_device_get(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+
+bool tuh_vid_pid_get(uint8_t daddr, uint16_t* vid, uint16_t* pid);
 
 // Gets the string indices for common device descriptor data.
-uint8_t tuh_i_manufacturer_get(uint8_t dev_addr);
-uint8_t tuh_i_serial_get(uint8_t dev_addr);
-uint8_t tuh_i_product_get(uint8_t dev_addr);
+uint8_t tuh_i_manufacturer_get(uint8_t daddr);
+uint8_t tuh_i_serial_get(uint8_t daddr);
+uint8_t tuh_i_product_get(uint8_t daddr);
 
 // Reads the string descriptor at the string index into the buffer. This is the
 // full response so the first entry is the length and the constant 0x03 for
 // string descriptor type.
-bool tuh_string_get(uint8_t dev_addr, uint8_t string_index, uint16_t* buf, size_t len, tuh_complete_cb_t complete_cb);
+bool tuh_string_get(uint8_t daddr, uint8_t string_index, uint16_t* buf, size_t len, tuh_complete_cb_t complete_cb);
 
-tusb_speed_t tuh_speed_get(uint8_t dev_addr);
+tusb_speed_t tuh_speed_get(uint8_t daddr);
 
 // Check if device is connected and configured
-bool tuh_mounted(uint8_t dev_addr);
+bool tuh_mounted(uint8_t daddr);
 
 // Check if device is suspended
-static inline bool tuh_suspended(uint8_t dev_addr)
+static inline bool tuh_suspended(uint8_t daddr)
 {
   // TODO implement suspend & resume on host
-  (void) dev_addr;
+  (void) daddr;
   return false;
 }
 
 // Check if device is ready to communicate with
 TU_ATTR_ALWAYS_INLINE
-static inline bool tuh_ready(uint8_t dev_addr)
+static inline bool tuh_ready(uint8_t daddr)
 {
-  return tuh_mounted(dev_addr) && !tuh_suspended(dev_addr);
+  return tuh_mounted(daddr) && !tuh_suspended(daddr);
 }
 
 // Carry out control transfer
-bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
+bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
 
 //--------------------------------------------------------------------+
 // APPLICATION CALLBACK
@@ -99,10 +108,10 @@ bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
 //TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device);
 
 // Invoked when device is mounted (configured)
-TU_ATTR_WEAK void tuh_mount_cb (uint8_t dev_addr);
+TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);
 
 /// Invoked when device is unmounted (bus reset/unplugged)
-TU_ATTR_WEAK void tuh_umount_cb(uint8_t dev_addr);
+TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
 
 #ifdef __cplusplus
  }

From 032e2c292997f4f8fe58239fcca535bb53ed2348 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 19:28:53 +0700
Subject: [PATCH 0857/2085] add CFG_TUH_INTERFACE_MAX config

---
 src/host/usbh.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 4c3bda4b0..7a994e104 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -41,6 +41,10 @@
 #define CFG_TUH_TASK_QUEUE_SZ   16
 #endif
 
+#ifndef CFG_TUH_INTERFACE_MAX
+#define CFG_TUH_INTERFACE_MAX   8
+#endif
+
 // Debug level of USBD
 #define USBH_DBG_LVL   2
 
@@ -96,7 +100,7 @@ typedef struct {
   //------------- device -------------//
   volatile uint8_t state;            // device state, value from enum tusbh_device_state_t
 
-  uint8_t itf2drv[8];               // map interface number to driver (0xff is invalid)
+  uint8_t itf2drv[CFG_TUH_INTERFACE_MAX];  // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUH_ENDPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid )
 
   struct TU_ATTR_PACKED
@@ -665,7 +669,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
 {
   usbh_device_t* dev = get_device(dev_addr);
 
-  for(itf_num++; itf_num < sizeof(dev->itf2drv); itf_num++)
+  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++)
   {
     // continue with next valid interface
     // TODO skip IAD binding interface such as CDCs
@@ -680,7 +684,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
   }
 
   // all interface are configured
-  if (itf_num == sizeof(dev->itf2drv))
+  if (itf_num == CFG_TUH_INTERFACE_MAX)
   {
     // Invoke callback if available
     if (tuh_mount_cb) tuh_mount_cb(dev_addr);

From 7480c2e46b10faa0cbdac5c9db803dbb1597cd34 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 21:04:52 +0700
Subject: [PATCH 0858/2085] correct qhd and qtd count for ehci/ohci

---
 src/host/hcd.h           | 2 +-
 src/portable/ehci/ehci.c | 7 ++++---
 src/portable/ohci/ohci.c | 6 +++---
 src/portable/ohci/ohci.h | 5 +++--
 4 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index d50fc2d60..9819f5f2a 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -40,7 +40,7 @@
 //--------------------------------------------------------------------+
 
 #ifndef CFG_TUH_ENDPOINT_MAX
-  #define CFG_TUH_ENDPOINT_MAX   (CFG_TUH_DEVICE_MAX*(CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3))
+  #define CFG_TUH_ENDPOINT_MAX   (CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3)
 //  #ifdef TUP_HCD_ENDPOINT_MAX
 //    #define CFG_TUH_ENDPPOINT_MAX   TUP_HCD_ENDPOINT_MAX
 //  #else
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index bc0b7b89a..2220474d7 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -58,7 +58,8 @@
 
 #define FRAMELIST_SIZE                  (1024 >> FRAMELIST_SIZE_BIT_VALUE)
 
-#define HCD_MAX_XFER      CFG_TUH_ENDPOINT_MAX
+#define QHD_MAX      (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX)
+#define QTD_MAX      QHD_MAX
 
 typedef struct
 {
@@ -76,7 +77,7 @@ typedef struct
   }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
 
   ehci_qhd_t qhd_pool[CFG_TUH_ENDPOINT_MAX];
-  ehci_qtd_t qtd_pool[HCD_MAX_XFER] TU_ATTR_ALIGNED(32);
+  ehci_qtd_t qtd_pool[QTD_MAX] TU_ATTR_ALIGNED(32);
 
   ehci_registers_t* regs;
 
@@ -752,7 +753,7 @@ static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr)
 //------------- TD helper -------------//
 static inline ehci_qtd_t* qtd_find_free(void)
 {
-  for (uint32_t i=0; i<HCD_MAX_XFER; i++)
+  for (uint32_t i=0; i<QTD_MAX; i++)
   {
     if ( !ehci_data.qtd_pool[i].used ) return &ehci_data.qtd_pool[i];
   }
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index c82b9352c..e09382241 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -313,7 +313,7 @@ static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
 
   ohci_ed_t* ed_pool = ohci_data.ed_pool;
 
-  for(uint32_t i=0; i<CFG_TUH_ENDPOINT_MAX; i++)
+  for(uint32_t i=0; i<ED_MAX; i++)
   {
     if ( (ed_pool[i].dev_addr == dev_addr) &&
           ep_addr == tu_edpt_addr(ed_pool[i].ep_number, ed_pool[i].pid == PID_IN) )
@@ -329,7 +329,7 @@ static ohci_ed_t * ed_find_free(void)
 {
   ohci_ed_t* ed_pool = ohci_data.ed_pool;
 
-  for(uint8_t i = 0; i < CFG_TUH_ENDPOINT_MAX; i++)
+  for(uint8_t i = 0; i < ED_MAX; i++)
   {
     if ( !ed_pool[i].used ) return &ed_pool[i];
   }
@@ -368,7 +368,7 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
 
 static ohci_gtd_t * gtd_find_free(void)
 {
-  for(uint8_t i=0; i < HCD_MAX_XFER; i++)
+  for(uint8_t i=0; i < GTD_MAX; i++)
   {
     if ( !ohci_data.gtd_pool[i].used ) return &ohci_data.gtd_pool[i];
   }
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index a1d74580b..d45555ded 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -42,7 +42,8 @@ enum {
   OHCI_MAX_ITD = 4
 };
 
-#define HCD_MAX_XFER      CFG_TUH_ENDPOINT_MAX
+#define ED_MAX       (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX)
+#define GTD_MAX      ED_MAX
 
 //--------------------------------------------------------------------+
 // OHCI Data Structure
@@ -165,7 +166,7 @@ typedef struct TU_ATTR_ALIGNED(256)
 
   //  ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
   ohci_ed_t ed_pool[CFG_TUH_ENDPOINT_MAX];
-  ohci_gtd_t gtd_pool[HCD_MAX_XFER];
+  ohci_gtd_t gtd_pool[GTD_MAX];
 
   volatile uint16_t frame_number_hi;
 

From 2bdf4d811aaa08841e9a5bdf6bbfe338e45acff6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 21:14:59 +0700
Subject: [PATCH 0859/2085] add tuh_descriptor_configuration_get()

---
 src/host/usbh.c | 45 ++++++++++-----------------------------------
 src/host/usbh.h |  3 +++
 2 files changed, 13 insertions(+), 35 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 7a994e104..96d2cccd3 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -285,6 +285,11 @@ bool tuh_descriptor_device_get(uint8_t daddr, void* buffer, uint16_t len, tuh_co
   return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb);
 }
 
+bool tuh_descriptor_configuration_get(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+{
+  return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb);
+}
+
 uint8_t tuh_i_manufacturer_get(uint8_t dev_addr) {
   TU_VERIFY(tuh_mounted(dev_addr));
   usbh_device_t const* dev = get_device(dev_addr);
@@ -948,23 +953,9 @@ static bool enum_get_device_desc_complete(uint8_t dev_addr, tusb_control_request
 
 //  if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
 
-  TU_LOG2("Get 9 bytes of Configuration Descriptor\r\n");
-  tusb_control_request_t const new_request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
-    },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = (TUSB_DESC_CONFIGURATION << 8) | (CONFIG_NUM - 1),
-    .wIndex   = 0,
-    .wLength  = 9
-  };
-
-  TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, _usbh_ctrl_buf, enum_get_9byte_config_desc_complete) );
-
+  // Get 9-byte for total length
+  TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n");
+  TU_ASSERT( tuh_descriptor_configuration_get(dev_addr, 0, _usbh_ctrl_buf, 9, enum_get_9byte_config_desc_complete) );
   return true;
 }
 
@@ -982,24 +973,8 @@ static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tusb_control_r
   TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE);
 
   // Get full configuration descriptor
-  TU_LOG2("Get Configuration Descriptor\r\n");
-  tusb_control_request_t const new_request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
-    },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = (TUSB_DESC_CONFIGURATION << 8) | (CONFIG_NUM - 1),
-    .wIndex   = 0,
-    .wLength  = total_len
-
-  };
-
-  TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, _usbh_ctrl_buf, enum_get_config_desc_complete) );
-
+  TU_LOG2("Get Configuration[0] Descriptor\r\n");
+  TU_ASSERT( tuh_descriptor_configuration_get(dev_addr, 0, _usbh_ctrl_buf, total_len, enum_get_config_desc_complete) );
   return true;
 }
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 9af139283..6926fce8a 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -67,6 +67,9 @@ bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index,
 // Get device descriptor
 bool tuh_descriptor_device_get(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
+// Get configuration descriptor
+bool tuh_descriptor_configuration_get(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+
 bool tuh_vid_pid_get(uint8_t daddr, uint16_t* vid, uint16_t* pid);
 
 // Gets the string indices for common device descriptor data.

From 15ced09bb2c19663670e2f3a268155b5ecc6e72d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 21:41:27 +0700
Subject: [PATCH 0860/2085] add tuh_configuration_set()

---
 src/host/usbh.c | 116 +++++++++++++++++++++++-------------------------
 src/host/usbh.h |  52 +++++++++++++---------
 2 files changed, 86 insertions(+), 82 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 96d2cccd3..ec607a1b6 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -257,9 +257,26 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
   return true;
 }
 
+tusb_speed_t tuh_speed_get (uint8_t dev_addr)
+{
+  return (tusb_speed_t) (dev_addr ? get_device(dev_addr)->speed : _dev0.speed);
+}
 
-bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index,
-                        void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+#if CFG_TUSB_OS == OPT_OS_NONE
+void osal_task_delay(uint32_t msec)
+{
+  (void) msec;
+
+  const uint32_t start = hcd_frame_number(TUH_OPT_RHPORT);
+  while ( ( hcd_frame_number(TUH_OPT_RHPORT) - start ) < msec ) {}
+}
+#endif
+
+//--------------------------------------------------------------------+
+// Descriptors
+//--------------------------------------------------------------------+
+
+bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
 {
   tusb_control_request_t const request =
   {
@@ -272,7 +289,7 @@ bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index,
     .bRequest = TUSB_REQ_GET_DESCRIPTOR,
     .wValue   = tu_htole16( TU_U16(type, index) ),
     .wIndex   = 0,
-    .wLength  = len
+    .wLength  = tu_htole16(len)
   };
 
   TU_ASSERT( tuh_control_xfer(daddr, &request, buffer, complete_cb) );
@@ -290,6 +307,27 @@ bool tuh_descriptor_configuration_get(uint8_t daddr, uint8_t index, void* buffer
   return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb);
 }
 
+bool tuh_descriptor_string_get(uint8_t daddr, uint16_t language_id, uint8_t index,
+                               void* buf, uint16_t len, tuh_control_complete_cb_t complete_cb)
+{
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_STANDARD,
+      .direction = TUSB_DIR_IN
+    },
+    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+    .wValue   = tu_htole16( TU_U16(TUSB_DESC_STRING, index) ),
+    .wIndex   = tu_htole16(language_id),
+    .wLength  = tu_htole16(len)
+  };
+
+  TU_ASSERT( tuh_control_xfer(daddr, &request, buf, complete_cb) );
+  return true;
+}
+
 uint8_t tuh_i_manufacturer_get(uint8_t dev_addr) {
   TU_VERIFY(tuh_mounted(dev_addr));
   usbh_device_t const* dev = get_device(dev_addr);
@@ -311,55 +349,27 @@ uint8_t tuh_i_product_get(uint8_t dev_addr) {
   return dev->i_product;
 }
 
-static tuh_complete_cb_t string_get_cb;
-
-static bool string_get_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result) {
-  (void) dev_addr;
-  (void) request;
-  if (string_get_cb != NULL) {
-    string_get_cb(result);
-  }
-  string_get_cb = NULL;
-  return true;
-}
-
-bool tuh_string_get(uint8_t dev_addr, uint8_t string_index, uint16_t* buf, size_t len, tuh_complete_cb_t complete_cb) {
-  if (string_get_cb != NULL) {
-    return false;
-  }
+bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_control_complete_cb_t complete_cb)
+{
+  TU_LOG2("Set Configuration = %d\r\n", config_num);
   tusb_control_request_t const request =
   {
     .bmRequestType_bit =
     {
       .recipient = TUSB_REQ_RCPT_DEVICE,
       .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
+      .direction = TUSB_DIR_OUT
     },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = TUSB_DESC_STRING << 8 | string_index,
+    .bRequest = TUSB_REQ_SET_CONFIGURATION,
+    .wValue   = tu_htole16(config_num),
     .wIndex   = 0,
-    .wLength  = len * sizeof(uint16_t)
+    .wLength  = 0
   };
-  string_get_cb = complete_cb;
-  TU_ASSERT( tuh_control_xfer(dev_addr, &request, buf, string_get_complete) );
+
+  TU_ASSERT( tuh_control_xfer(daddr, &request, NULL, complete_cb) );
   return true;
 }
 
-tusb_speed_t tuh_speed_get (uint8_t dev_addr)
-{
-  return (tusb_speed_t) (dev_addr ? get_device(dev_addr)->speed : _dev0.speed);
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-void osal_task_delay(uint32_t msec)
-{
-  (void) msec;
-
-  const uint32_t start = hcd_frame_number(TUH_OPT_RHPORT);
-  while ( ( hcd_frame_number(TUH_OPT_RHPORT) - start ) < msec ) {}
-}
-#endif
-
 //--------------------------------------------------------------------+
 // CLASS-USBD API (don't require to verify parameters)
 //--------------------------------------------------------------------+
@@ -903,7 +913,7 @@ static bool enum_request_set_addr(void)
       .direction = TUSB_DIR_OUT
     },
     .bRequest = TUSB_REQ_SET_ADDRESS,
-    .wValue   = new_addr,
+    .wValue   = tu_htole16(new_addr),
     .wIndex   = 0,
     .wLength  = 0
   };
@@ -954,8 +964,9 @@ static bool enum_get_device_desc_complete(uint8_t dev_addr, tusb_control_request
 //  if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
 
   // Get 9-byte for total length
+  uint8_t const config_idx = CONFIG_NUM - 1;
   TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n");
-  TU_ASSERT( tuh_descriptor_configuration_get(dev_addr, 0, _usbh_ctrl_buf, 9, enum_get_9byte_config_desc_complete) );
+  TU_ASSERT( tuh_descriptor_configuration_get(dev_addr, config_idx, _usbh_ctrl_buf, 9, enum_get_9byte_config_desc_complete) );
   return true;
 }
 
@@ -973,8 +984,9 @@ static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tusb_control_r
   TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE);
 
   // Get full configuration descriptor
+  uint8_t const config_idx = CONFIG_NUM - 1;
   TU_LOG2("Get Configuration[0] Descriptor\r\n");
-  TU_ASSERT( tuh_descriptor_configuration_get(dev_addr, 0, _usbh_ctrl_buf, total_len, enum_get_config_desc_complete) );
+  TU_ASSERT( tuh_descriptor_configuration_get(dev_addr, config_idx, _usbh_ctrl_buf, total_len, enum_get_config_desc_complete) );
   return true;
 }
 
@@ -987,23 +999,7 @@ static bool enum_get_config_desc_complete(uint8_t dev_addr, tusb_control_request
   // Driver open aren't allowed to make any usb transfer yet
   TU_ASSERT( parse_configuration_descriptor(dev_addr, (tusb_desc_configuration_t*) _usbh_ctrl_buf) );
 
-  TU_LOG2("Set Configuration = %d\r\n", CONFIG_NUM);
-  tusb_control_request_t const new_request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = TUSB_REQ_SET_CONFIGURATION,
-    .wValue   = CONFIG_NUM,
-    .wIndex   = 0,
-    .wLength  = 0
-  };
-
-  TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, NULL, enum_set_config_complete) );
-
+  TU_ASSERT( tuh_configuration_set(dev_addr, CONFIG_NUM, enum_set_config_complete) );
   return true;
 }
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 6926fce8a..a10d6df0e 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -58,36 +58,15 @@ void tuh_task(void);
 extern void hcd_int_handler(uint8_t rhport);
 #define tuh_int_handler   hcd_int_handler
 
-//------------- descriptors -------------//
-
-// Get an descriptor
-bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index,
-                        void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
-
-// Get device descriptor
-bool tuh_descriptor_device_get(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
-
-// Get configuration descriptor
-bool tuh_descriptor_configuration_get(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
-
 bool tuh_vid_pid_get(uint8_t daddr, uint16_t* vid, uint16_t* pid);
 
-// Gets the string indices for common device descriptor data.
-uint8_t tuh_i_manufacturer_get(uint8_t daddr);
-uint8_t tuh_i_serial_get(uint8_t daddr);
-uint8_t tuh_i_product_get(uint8_t daddr);
-
-// Reads the string descriptor at the string index into the buffer. This is the
-// full response so the first entry is the length and the constant 0x03 for
-// string descriptor type.
-bool tuh_string_get(uint8_t daddr, uint8_t string_index, uint16_t* buf, size_t len, tuh_complete_cb_t complete_cb);
-
 tusb_speed_t tuh_speed_get(uint8_t daddr);
 
 // Check if device is connected and configured
 bool tuh_mounted(uint8_t daddr);
 
 // Check if device is suspended
+TU_ATTR_ALWAYS_INLINE
 static inline bool tuh_suspended(uint8_t daddr)
 {
   // TODO implement suspend & resume on host
@@ -105,6 +84,35 @@ static inline bool tuh_ready(uint8_t daddr)
 // Carry out control transfer
 bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
 
+// Set Configuration
+// config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
+bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_control_complete_cb_t complete_cb);
+
+//------------- descriptors -------------//
+
+// Get an descriptor
+bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index,
+                        void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+
+// Get device descriptor
+bool tuh_descriptor_device_get(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+
+// Get configuration descriptor
+bool tuh_descriptor_configuration_get(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+
+// Get string descriptor
+// Reads the string descriptor at the string index into the buffer. This is the
+// full response so the first entry is the length and the constant 0x03 for
+// string descriptor type.
+bool tuh_descriptor_string_get(uint8_t daddr, uint16_t language_id, uint8_t index,
+                               void* buf, uint16_t len, tuh_control_complete_cb_t complete_cb);
+
+
+// Gets the string indices for common device descriptor data.
+uint8_t tuh_i_manufacturer_get(uint8_t daddr);
+uint8_t tuh_i_serial_get(uint8_t daddr);
+uint8_t tuh_i_product_get(uint8_t daddr);
+
 //--------------------------------------------------------------------+
 // APPLICATION CALLBACK
 //--------------------------------------------------------------------+

From 271f905521edfdcfc5649bbe6906f3d3c6d4b10f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 22:23:56 +0700
Subject: [PATCH 0861/2085] add
 tuh_descriptor_string_manufacturer/produce/serial_get

---
 src/host/usbh.c | 47 +++++++++++++++++++++++++----------------------
 src/host/usbh.h | 16 ++++++++--------
 2 files changed, 33 insertions(+), 30 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index ec607a1b6..241231c1e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -86,10 +86,11 @@ typedef struct {
   };
 
   //------------- device descriptor -------------//
+  uint8_t  ep0_size;
+
   uint16_t vid;
   uint16_t pid;
 
-  uint8_t  ep0_size;
   uint8_t  i_manufacturer;
   uint8_t  i_product;
   uint8_t  i_serial;
@@ -248,7 +249,6 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
   *vid = *pid = 0;
 
   TU_VERIFY(tuh_mounted(dev_addr));
-
   usbh_device_t const* dev = get_device(dev_addr);
 
   *vid = dev->vid;
@@ -308,7 +308,7 @@ bool tuh_descriptor_configuration_get(uint8_t daddr, uint8_t index, void* buffer
 }
 
 bool tuh_descriptor_string_get(uint8_t daddr, uint16_t language_id, uint8_t index,
-                               void* buf, uint16_t len, tuh_control_complete_cb_t complete_cb)
+                               void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
 {
   tusb_control_request_t const request =
   {
@@ -324,29 +324,32 @@ bool tuh_descriptor_string_get(uint8_t daddr, uint16_t language_id, uint8_t inde
     .wLength  = tu_htole16(len)
   };
 
-  TU_ASSERT( tuh_control_xfer(daddr, &request, buf, complete_cb) );
+  TU_ASSERT( tuh_control_xfer(daddr, &request, buffer, complete_cb) );
   return true;
 }
 
-uint8_t tuh_i_manufacturer_get(uint8_t dev_addr) {
-  TU_VERIFY(tuh_mounted(dev_addr));
-  usbh_device_t const* dev = get_device(dev_addr);
-
-  return dev->i_manufacturer;
+// Get manufacturer string descriptor
+bool tuh_descriptor_string_manufacturer_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+{
+  TU_VERIFY(tuh_mounted(daddr));
+  usbh_device_t const* dev = get_device(daddr);
+  return tuh_descriptor_string_get(daddr, language_id, dev->i_manufacturer, buffer, len, complete_cb);
 }
 
-uint8_t tuh_i_serial_get(uint8_t dev_addr) {
-  TU_VERIFY(tuh_mounted(dev_addr));
-  usbh_device_t const* dev = get_device(dev_addr);
-
-  return dev->i_serial;
+// Get product string descriptor
+bool tuh_descriptor_string_product_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+{
+  TU_VERIFY(tuh_mounted(daddr));
+  usbh_device_t const* dev = get_device(daddr);
+  return tuh_descriptor_string_get(daddr, language_id, dev->i_product, buffer, len, complete_cb);
 }
 
-uint8_t tuh_i_product_get(uint8_t dev_addr) {
-  TU_VERIFY(tuh_mounted(dev_addr));
-  usbh_device_t const* dev = get_device(dev_addr);
-
-  return dev->i_product;
+// Get serial string descriptor
+bool tuh_descriptor_string_serial_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+{
+  TU_VERIFY(tuh_mounted(daddr));
+  usbh_device_t const* dev = get_device(daddr);
+  return tuh_descriptor_string_get(daddr, language_id, dev->i_serial, buffer, len, complete_cb);
 }
 
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_control_complete_cb_t complete_cb)
@@ -957,9 +960,9 @@ static bool enum_get_device_desc_complete(uint8_t dev_addr, tusb_control_request
 
   dev->vid            = desc_device->idVendor;
   dev->pid            = desc_device->idProduct;
-  dev->i_manufacturer = desc_device->iManufacturer;
-  dev->i_product      = desc_device->iProduct;
-  dev->i_serial       = desc_device->iSerialNumber;
+//  dev->i_manufacturer = desc_device->iManufacturer;
+//  dev->i_product      = desc_device->iProduct;
+//  dev->i_serial       = desc_device->iSerialNumber;
 
 //  if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index a10d6df0e..1aef603a0 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -101,17 +101,17 @@ bool tuh_descriptor_device_get(uint8_t daddr, void* buffer, uint16_t len, tuh_co
 bool tuh_descriptor_configuration_get(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
 // Get string descriptor
-// Reads the string descriptor at the string index into the buffer. This is the
-// full response so the first entry is the length and the constant 0x03 for
-// string descriptor type.
 bool tuh_descriptor_string_get(uint8_t daddr, uint16_t language_id, uint8_t index,
-                               void* buf, uint16_t len, tuh_control_complete_cb_t complete_cb);
+                               void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
+// Get manufacturer string descriptor
+bool tuh_descriptor_string_manufacturer_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
-// Gets the string indices for common device descriptor data.
-uint8_t tuh_i_manufacturer_get(uint8_t daddr);
-uint8_t tuh_i_serial_get(uint8_t daddr);
-uint8_t tuh_i_product_get(uint8_t daddr);
+// Get product string descriptor
+bool tuh_descriptor_string_product_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+
+// Get serial string descriptor
+bool tuh_descriptor_string_serial_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
 //--------------------------------------------------------------------+
 // APPLICATION CALLBACK

From b9a6cd8b6163e79d42ba3b56515579f6c1d5f3b2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 22:25:50 +0700
Subject: [PATCH 0862/2085] rename example

---
 examples/host/CMakeLists.txt                             | 1 -
 examples/host/{libusb_api => bare_api}/CMakeLists.txt    | 0
 examples/host/{libusb_api => bare_api}/Makefile          | 0
 examples/host/{libusb_api => bare_api}/only.txt          | 0
 examples/host/{libusb_api => bare_api}/src/main.c        | 0
 examples/host/{libusb_api => bare_api}/src/tusb_config.h | 0
 6 files changed, 1 deletion(-)
 rename examples/host/{libusb_api => bare_api}/CMakeLists.txt (100%)
 rename examples/host/{libusb_api => bare_api}/Makefile (100%)
 rename examples/host/{libusb_api => bare_api}/only.txt (100%)
 rename examples/host/{libusb_api => bare_api}/src/main.c (100%)
 rename examples/host/{libusb_api => bare_api}/src/tusb_config.h (100%)

diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt
index 38db6c6cc..5c63ec0c0 100644
--- a/examples/host/CMakeLists.txt
+++ b/examples/host/CMakeLists.txt
@@ -8,4 +8,3 @@ family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
 # family_add_subdirectory will filter what to actually add based on selected FAMILY
 family_add_subdirectory(cdc_msc_hid)
 family_add_subdirectory(hid_controller)
-family_add_subdirectory(libusb_api)
diff --git a/examples/host/libusb_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
similarity index 100%
rename from examples/host/libusb_api/CMakeLists.txt
rename to examples/host/bare_api/CMakeLists.txt
diff --git a/examples/host/libusb_api/Makefile b/examples/host/bare_api/Makefile
similarity index 100%
rename from examples/host/libusb_api/Makefile
rename to examples/host/bare_api/Makefile
diff --git a/examples/host/libusb_api/only.txt b/examples/host/bare_api/only.txt
similarity index 100%
rename from examples/host/libusb_api/only.txt
rename to examples/host/bare_api/only.txt
diff --git a/examples/host/libusb_api/src/main.c b/examples/host/bare_api/src/main.c
similarity index 100%
rename from examples/host/libusb_api/src/main.c
rename to examples/host/bare_api/src/main.c
diff --git a/examples/host/libusb_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
similarity index 100%
rename from examples/host/libusb_api/src/tusb_config.h
rename to examples/host/bare_api/src/tusb_config.h

From 56c2d4b666856dedd9ced301d8a273c55ee2afd6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Mar 2022 22:31:48 +0700
Subject: [PATCH 0863/2085] fix naming, and build

---
 examples/host/bare_api/src/main.c |  2 +-
 src/host/usbh.h                   |  1 -
 src/portable/ehci/ehci.c          | 10 +++++-----
 src/portable/ohci/ohci.h          |  2 +-
 4 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 07dae1dc6..b6b1527c0 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -66,8 +66,8 @@ int main(void)
 
 void print_device_descriptor(uint8_t dev_addr)
 {
+  (void) dev_addr;
   printf("Device Descriptor:\r\n");
-
 }
 
 // Invoked when device is mounted (configured)
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 1aef603a0..9465d1d1b 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -38,7 +38,6 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-typedef bool (*tuh_complete_cb_t)(xfer_result_t result);
 typedef bool (*tuh_control_complete_cb_t)(uint8_t daddr, tusb_control_request_t const * request, xfer_result_t result);
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 2220474d7..8d420f26a 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -76,7 +76,7 @@ typedef struct
     ehci_qtd_t qtd;
   }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
 
-  ehci_qhd_t qhd_pool[CFG_TUH_ENDPOINT_MAX];
+  ehci_qhd_t qhd_pool[QHD_MAX];
   ehci_qtd_t qtd_pool[QTD_MAX] TU_ATTR_ALIGNED(32);
 
   ehci_registers_t* regs;
@@ -481,7 +481,7 @@ static void async_advance_isr(uint8_t rhport)
   (void) rhport;
 
   ehci_qhd_t* qhd_pool = ehci_data.qhd_pool;
-  for(uint32_t i = 0; i < CFG_TUH_ENDPOINT_MAX; i++)
+  for(uint32_t i = 0; i < QHD_MAX; i++)
   {
     if ( qhd_pool[i].removing )
     {
@@ -549,7 +549,7 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms)
   // TODO abstract max loop guard for period
   while( !next_item.terminate &&
       !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) &&
-      max_loop < (CFG_TUH_ENDPOINT_MAX + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUH_DEVICE_MAX)
+      max_loop < (QHD_MAX + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUH_DEVICE_MAX)
   {
     switch ( next_item.type )
     {
@@ -721,7 +721,7 @@ void hcd_int_handler(uint8_t rhport)
 //------------- queue head helper -------------//
 static inline ehci_qhd_t* qhd_find_free (void)
 {
-  for (uint32_t i=0; i<CFG_TUH_ENDPOINT_MAX; i++)
+  for (uint32_t i=0; i<QHD_MAX; i++)
   {
     if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i];
   }
@@ -738,7 +738,7 @@ static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr)
 {
   ehci_qhd_t* qhd_pool = ehci_data.qhd_pool;
 
-  for(uint32_t i=0; i<CFG_TUH_ENDPOINT_MAX; i++)
+  for(uint32_t i=0; i<QHD_MAX; i++)
   {
     if ( (qhd_pool[i].dev_addr == dev_addr) &&
           ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) )
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index d45555ded..9fc954c8f 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -165,7 +165,7 @@ typedef struct TU_ATTR_ALIGNED(256)
   }control[CFG_TUH_DEVICE_MAX+CFG_TUH_HUB+1];
 
   //  ochi_itd_t itd[OHCI_MAX_ITD]; // itd requires alignment of 32
-  ohci_ed_t ed_pool[CFG_TUH_ENDPOINT_MAX];
+  ohci_ed_t ed_pool[ED_MAX];
   ohci_gtd_t gtd_pool[GTD_MAX];
 
   volatile uint16_t frame_number_hi;

From 4642cb8d0a968823d1b5ae89086d4d3507f50dc5 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Fri, 4 Mar 2022 15:35:32 +0000
Subject: [PATCH 0864/2085] documentatio: fix bad supported dev table format

---
 docs/reference/supported.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 7c5402d93..7ce982713 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -42,7 +42,7 @@ Supported MCUs
 +--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
 | NXP          | iMXRT   | RT10xx      | ✔      | ✔    | ✔         | ci_hs             |              |
 |              +---------+-------------+--------+------+-----------+-------------------+--------------+
-|              | Kinetis | KL25        | ✔      | ⚠     | ✖         |                   |              |
+|              | Kinetis | KL25        | ✔      | ⚠    | ✖         |                   |              |
 |              |         +-------------+--------+------+-----------+-------------------+--------------+
 |              |         | K32L2       | ✔      |      | ✖         |                   |              |
 |              +---------+-------------+--------+------+-----------+-------------------+--------------+

From f291243121ef35e88c16c47a259213d455c4a401 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Fri, 4 Mar 2022 11:38:02 -0800
Subject: [PATCH 0865/2085] Fix string descriptor fetch

---
 src/host/usbh.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 241231c1e..192979ce6 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -333,6 +333,9 @@ bool tuh_descriptor_string_manufacturer_get(uint8_t daddr, uint16_t language_id,
 {
   TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
+  if (dev->i_manufacturer == 0) {
+    return false;
+  }
   return tuh_descriptor_string_get(daddr, language_id, dev->i_manufacturer, buffer, len, complete_cb);
 }
 
@@ -341,6 +344,9 @@ bool tuh_descriptor_string_product_get(uint8_t daddr, uint16_t language_id, void
 {
   TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
+  if (dev->i_product == 0) {
+    return false;
+  }
   return tuh_descriptor_string_get(daddr, language_id, dev->i_product, buffer, len, complete_cb);
 }
 
@@ -349,6 +355,9 @@ bool tuh_descriptor_string_serial_get(uint8_t daddr, uint16_t language_id, void*
 {
   TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
+  if (dev->i_serial == 0) {
+    return false;
+  }
   return tuh_descriptor_string_get(daddr, language_id, dev->i_serial, buffer, len, complete_cb);
 }
 
@@ -960,9 +969,9 @@ static bool enum_get_device_desc_complete(uint8_t dev_addr, tusb_control_request
 
   dev->vid            = desc_device->idVendor;
   dev->pid            = desc_device->idProduct;
-//  dev->i_manufacturer = desc_device->iManufacturer;
-//  dev->i_product      = desc_device->iProduct;
-//  dev->i_serial       = desc_device->iSerialNumber;
+  dev->i_manufacturer = desc_device->iManufacturer;
+  dev->i_product      = desc_device->iProduct;
+  dev->i_serial       = desc_device->iSerialNumber;
 
 //  if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
 

From 2bef4410f9ca71e60ce4072cca02ca6b544c0caa Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sat, 5 Mar 2022 17:07:04 +0100
Subject: [PATCH 0866/2085] Add stm32wb cmsis and hal driver submodules from ST

---
 .gitmodules                    | 6 ++++++
 hw/mcu/st/cmsis_device_wb      | 1 +
 hw/mcu/st/stm32wbxx_hal_driver | 1 +
 3 files changed, 8 insertions(+)
 create mode 160000 hw/mcu/st/cmsis_device_wb
 create mode 160000 hw/mcu/st/stm32wbxx_hal_driver

diff --git a/.gitmodules b/.gitmodules
index fb551060a..21bbf08c0 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -97,6 +97,12 @@
 [submodule "hw/mcu/st/stm32l5xx_hal_driver"]
 	path = hw/mcu/st/stm32l5xx_hal_driver
 	url = https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git
+[submodule "hw/mcu/st/cmsis_device_wb"]
+	path = hw/mcu/st/cmsis_device_wb
+	url = https://github.com/STMicroelectronics/cmsis_device_wb.git
+[submodule "hw/mcu/st/stm32wbxx_hal_driver"]
+	path = hw/mcu/st/stm32wbxx_hal_driver
+	url = https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git
 [submodule "lib/sct_neopixel"]
 	path = lib/sct_neopixel
 	url = https://github.com/gsteiert/sct_neopixel
diff --git a/hw/mcu/st/cmsis_device_wb b/hw/mcu/st/cmsis_device_wb
new file mode 160000
index 000000000..9c5d1920d
--- /dev/null
+++ b/hw/mcu/st/cmsis_device_wb
@@ -0,0 +1 @@
+Subproject commit 9c5d1920dd9fabbe2548e10561d63db829bb744f
diff --git a/hw/mcu/st/stm32wbxx_hal_driver b/hw/mcu/st/stm32wbxx_hal_driver
new file mode 160000
index 000000000..2c5f06638
--- /dev/null
+++ b/hw/mcu/st/stm32wbxx_hal_driver
@@ -0,0 +1 @@
+Subproject commit 2c5f06638be516c1b772f768456ba637f077bac8

From 65bf5ddb1bfe87719fc612d1eae44087b87e682a Mon Sep 17 00:00:00 2001
From: QianHao <929254256@qq.com>
Date: Mon, 7 Mar 2022 08:04:49 +0000
Subject: [PATCH 0867/2085] Modify the wrong macro definition code

---
 src/portable/synopsys/dwc2/dwc2_type.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index dbef20314..7fa2028eb 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -986,16 +986,16 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo   ) == 0x1000, "incorrect size");
 
 /********************  Bit definition for OTG register  ********************/
 #define GNPTXFSIZ_NPTXFSA_Pos            (0U)
-#define GNPTXFSIZ_NPTXFSA_Msk            (0xFFFFUL << NPTXFSA_Pos)                // 0x0000FFFF */
+#define GNPTXFSIZ_NPTXFSA_Msk            (0xFFFFUL << GNPTXFSIZ_NPTXFSA_Pos)                // 0x0000FFFF */
 #define GNPTXFSIZ_NPTXFSA                GNPTXFSIZ_NPTXFSA_Msk                    // Nonperiodic transmit RAM start address */
 #define GNPTXFSIZ_NPTXFD_Pos             (16U)
-#define GNPTXFSIZ_NPTXFD_Msk             (0xFFFFUL << NPTXFD_Pos)                 // 0xFFFF0000 */
+#define GNPTXFSIZ_NPTXFD_Msk             (0xFFFFUL << GNPTXFSIZ_NPTXFD_Pos)                 // 0xFFFF0000 */
 #define GNPTXFSIZ_NPTXFD                 GNPTXFSIZ_NPTXFD_Msk                     // Nonperiodic TxFIFO depth               */
 #define DIEPTXF0_TX0FSA_Pos              (0U)
-#define DIEPTXF0_TX0FSA_Msk              (0xFFFFUL << TX0FSA_Pos)                 // 0x0000FFFF */
+#define DIEPTXF0_TX0FSA_Msk              (0xFFFFUL << DIEPTXF0_TX0FSA_Pos)                 // 0x0000FFFF */
 #define DIEPTXF0_TX0FSA                  DIEPTXF0_TX0FSA_Msk                      // Endpoint 0 transmit RAM start address  */
 #define DIEPTXF0_TX0FD_Pos               (16U)
-#define DIEPTXF0_TX0FD_Msk               (0xFFFFUL << TX0FD_Pos)                  // 0xFFFF0000 */
+#define DIEPTXF0_TX0FD_Msk               (0xFFFFUL << DIEPTXF0_TX0FD_Pos)                  // 0xFFFF0000 */
 #define DIEPTXF0_TX0FD                   DIEPTXF0_TX0FD_Msk                       // Endpoint 0 TxFIFO depth                */
 
 /********************  Bit definition for DVBUSPULSE register  ********************/

From a18ac842298d3742dc7044bd0db5c2351a4219a8 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sat, 5 Mar 2022 17:09:04 +0100
Subject: [PATCH 0868/2085] Add support for STM32WB mcu

---
 src/common/tusb_mcu.h                                |  3 +++
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c        | 10 +++++++++-
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h |  7 +++++++
 src/tusb_option.h                                    |  1 +
 4 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 465e33ec7..8eb4ad475 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -184,6 +184,9 @@
     #define TUP_DCD_ENDPOINT_MAX  8
   #endif
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32WB)
+#define TUP_DCD_ENDPOINT_MAX    8
+
 //------------- Sony -------------//
 #elif TU_CHECK_MCU(OPT_MCU_CXD56)
   #define TUP_DCD_ENDPOINT_MAX    7
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index f201a02cf..4fd189188 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -110,7 +110,7 @@
 #endif
 
 #if CFG_TUD_ENABLED && \
-      ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4) || \
+      ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4, OPT_MCU_STM32WB) || \
         (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) \
       )
 
@@ -328,6 +328,10 @@ void dcd_int_enable (uint8_t rhport)
   NVIC_EnableIRQ(USB_LP_IRQn);
   NVIC_EnableIRQ(USBWakeUp_IRQn);
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
+  NVIC_EnableIRQ(USB_HP_IRQn);
+  NVIC_EnableIRQ(USB_LP_IRQn);
+
 #else
   #error Unknown arch in USB driver
 #endif
@@ -370,6 +374,10 @@ void dcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USB_LP_IRQn);
   NVIC_DisableIRQ(USBWakeUp_IRQn);
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
+  NVIC_DisableIRQ(USB_HP_IRQn);
+  NVIC_DisableIRQ(USB_LP_IRQn);
+
 #else
   #error Unknown arch in USB driver
 #endif
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 596f7be6c..bffae4500 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -91,6 +91,13 @@
   #include "stm32g4xx.h"
   #define PMA_LENGTH (1024u)
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
+  #include "stm32wbxx.h"
+  #define PMA_LENGTH (1024u)
+  /* ST provided header has incorrect value */
+  #undef USB_PMAADDR
+  #define USB_PMAADDR USB1_PMAADDR
+
 #else
   #error You are using an untested or unimplemented STM32 variant. Please update the driver.
   // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 25e536787..3f404872a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -80,6 +80,7 @@
 #define OPT_MCU_STM32L4           309 ///< ST L4
 #define OPT_MCU_STM32G0           310 ///< ST G0
 #define OPT_MCU_STM32G4           311 ///< ST G4
+#define OPT_MCU_STM32WB           312 ///< ST WB
 
 // Sony
 #define OPT_MCU_CXD56             400 ///< SONY CXD56

From 76c8d4d95b78ae479ce21e8780c50c733ac18829 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sat, 5 Mar 2022 17:12:01 +0100
Subject: [PATCH 0869/2085] Add support for nucleo-wb55rg

---
 hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h | 122 ++++++
 .../stm32wb/boards/stm32wb55nucleo/board.mk   |   9 +
 .../stm32wb55nucleo/stm32wb55xx_flash_cm4.ld  | 171 +++++++++
 hw/bsp/stm32wb/family.c                       | 190 ++++++++++
 hw/bsp/stm32wb/family.mk                      |  44 +++
 hw/bsp/stm32wb/stm32wbxx_hal_conf.h           | 349 ++++++++++++++++++
 6 files changed, 885 insertions(+)
 create mode 100644 hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h
 create mode 100644 hw/bsp/stm32wb/boards/stm32wb55nucleo/board.mk
 create mode 100644 hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
 create mode 100644 hw/bsp/stm32wb/family.c
 create mode 100644 hw/bsp/stm32wb/family.mk
 create mode 100644 hw/bsp/stm32wb/stm32wbxx_hal_conf.h

diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h
new file mode 100644
index 000000000..f42c7d6dd
--- /dev/null
+++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h
@@ -0,0 +1,122 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_4
+#define BUTTON_STATE_ACTIVE   0
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART1
+#define UART_CLK_EN           __HAL_RCC_USART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOB
+#define UART_GPIO_AF          GPIO_AF7_USART1
+#define UART_TX_PIN           GPIO_PIN_6
+#define UART_RX_PIN           GPIO_PIN_7
+
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  // Initializes the CPU, AHB and APB busses clocks
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState       = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM       = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN       = 24;
+  RCC_OscInitStruct.PLL.PLLP       = RCC_PLLP_DIV4;
+  RCC_OscInitStruct.PLL.PLLQ       = RCC_PLLQ_DIV4;
+  RCC_OscInitStruct.PLL.PLLR       = RCC_PLLR_DIV3;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  // Initializes the CPU, AHB and APB busses clocks
+  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInit.UsbClockSelection    = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) ;
+
+#if 0 // TODO need to check if USB clock is enabled
+  /* Enable HSI48 */
+  memset(&RCC_OscInitStruct, 0, sizeof(RCC_OscInitStruct));
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /*Enable CRS Clock*/
+  RCC_CRSInitTypeDef RCC_CRSInitStruct= {0};
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+  /* Set the TRIM[5:0] to the default value */
+  RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+  /* Start automatic synchronization */
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.mk b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.mk
new file mode 100644
index 000000000..d6adc6b63
--- /dev/null
+++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.mk
@@ -0,0 +1,9 @@
+CFLAGS += \
+	-DSTM32WB55xx
+
+LD_FILE = $(BOARD_PATH)/stm32wb55xx_flash_cm4.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32wb55xx_cm4.s
+
+# For flash-jlink target
+JLINK_DEVICE = STM32WB55RG
diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
new file mode 100644
index 000000000..660f30161
--- /dev/null
+++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
@@ -0,0 +1,171 @@
+/**
+*****************************************************************************
+**
+**  File        : stm32wb55xx_flash_cm4.ld
+**
+**  Abstract    : System Workbench Minimal System calls file
+**
+** 		          For more information about which c-functions
+**                need which of these lowlevel functions
+**                please consult the Newlib libc-manual
+**
+**  Environment : System Workbench for MCU
+**
+**  Distribution: The file is distributed “as is,� without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20030000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x400;      /* required amount of heap  */
+_Min_Stack_Size = 0x1000;   /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)                 : ORIGIN = 0x08000000, LENGTH = 512K
+RAM1 (xrw)                 : ORIGIN = 0x20000008, LENGTH = 0x2FFF8
+RAM_SHARED (xrw)           : ORIGIN = 0x20030000, LENGTH = 10K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM1 AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0       : { *(.ARM.attributes) }
+   MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
+   MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
+   MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
+}
+
+
diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c
new file mode 100644
index 000000000..1ed38308b
--- /dev/null
+++ b/hw/bsp/stm32wb/family.c
@@ -0,0 +1,190 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stm32wbxx_hal.h"
+#include "bsp/board.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_HP_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void USB_LP_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+UART_HandleTypeDef UartHandle;
+
+void board_init(void)
+{
+  board_clock_init();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+
+  UART_CLK_EN();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  GPIO_InitTypeDef  GPIO_InitStruct;
+
+  // LED
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+#if 0
+  // MCO configuration for System clock value verification PA8 will have SYSCLK / 2
+  GPIO_InitStruct.Pin = 8;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_2);
+#endif
+
+  board_led_write(false);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+#ifdef UART_DEV
+  // UART
+  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull      = GPIO_PULLUP;
+  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle = (UART_HandleTypeDef){
+    .Instance        = UART_DEV,
+    .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+    .Init.WordLength = UART_WORDLENGTH_8B,
+    .Init.StopBits   = UART_STOPBITS_1,
+    .Init.Parity     = UART_PARITY_NONE,
+    .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+    .Init.Mode       = UART_MODE_TX_RX,
+    .Init.OverSampling = UART_OVERSAMPLING_16
+  };
+  HAL_UART_Init(&UartHandle);
+#endif
+
+  // USB Pins TODO double check USB clock and pin setup
+  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  HAL_PWREx_EnableVddUSB();
+  __HAL_RCC_USB_CLK_ENABLE();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  return len;
+#else
+  (void) buf; (void) len; (void) UartHandle;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler (void)
+{
+  asm("bkpt");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/stm32wb/family.mk b/hw/bsp/stm32wb/family.mk
new file mode 100644
index 000000000..f85c5badd
--- /dev/null
+++ b/hw/bsp/stm32wb/family.mk
@@ -0,0 +1,44 @@
+UF2_FAMILY_ID = 0x70d16653
+ST_FAMILY = wb
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32WB
+
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=cast-align -Wno-unused-parameter
+
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM4F
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32wb/stm32wbxx_hal_conf.h b/hw/bsp/stm32wb/stm32wbxx_hal_conf.h
new file mode 100644
index 000000000..754c94ed9
--- /dev/null
+++ b/hw/bsp/stm32wb/stm32wbxx_hal_conf.h
@@ -0,0 +1,349 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32WBxx_HAL_CONF_H
+#define __STM32WBxx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_HSEM_MODULE_ENABLED   */
+/*#define HAL_IPCC_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_PKA_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+/*#define HAL_CRYP_MODULE_ENABLED  */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS       0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS      0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS      0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS       0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS      0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS     0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS       0u
+#define USE_HAL_PKA_REGISTER_CALLBACKS       0u
+#define USE_HAL_QSPI_REGISTER_CALLBACKS      0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS       0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS       0u
+#define USE_HAL_SAI_REGISTER_CALLBACKS       0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS     0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS       0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS       0u
+#define USE_HAL_TSC_REGISTER_CALLBACKS       0u
+#define USE_HAL_UART_REGISTER_CALLBACKS      0u
+#define USE_HAL_USART_REGISTER_CALLBACKS     0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS      0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    32000000U             /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI1) value.
+  */
+#if !defined  (LSI1_VALUE)
+ #define LSI1_VALUE  ((uint32_t)32000)       /*!< LSI1 Typical Value in Hz*/
+#endif /* LSI1_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief Internal Low Speed oscillator (LSI2) value.
+  */
+#if !defined  (LSI2_VALUE)
+ #define LSI2_VALUE  ((uint32_t)32000)       /*!< LSI2 Typical Value in Hz*/
+#endif /* LSI2_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Internal Multiple Speed oscillator (HSI48) default value.
+  *        This value is the default HSI48 range value after Reset.
+  */
+#if !defined (HSI48_VALUE)
+  #define HSI48_VALUE    ((uint32_t)48000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI48_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U      /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+  *        frequency.
+  */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)2097000) /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+
+#define  VDD_VALUE                    3300U   /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U      /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1
+#define  INSTRUCTION_CACHE_ENABLE     1
+#define  DATA_CACHE_ENABLE            1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32wbxx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32wbxx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32wbxx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32wbxx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32wbxx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32wbxx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32wbxx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32wbxx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32wbxx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IPCC_MODULE_ENABLED
+ #include "stm32wbxx_hal_ipcc.h"
+#endif /* HAL_IPCC_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32wbxx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32wbxx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+  #include "stm32wbxx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+  #include "stm32wbxx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32wbxx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32wbxx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U
+ #include "stm32wbxx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32wbxx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+  #include "stm32wbxx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32wbxx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32wbxx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32wbxx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32wbxx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32wbxx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32wbxx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+  #include "stm32wbxx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32wbxx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32wbxx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32wbxx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32WBxx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

From 61615203fde586211854e531a5c6a88da5c8ea4a Mon Sep 17 00:00:00 2001
From: Szymon Janc <szymon.janc@codecoup.pl>
Date: Mon, 7 Mar 2022 15:33:27 +0100
Subject: [PATCH 0870/2085] Add missing releases to Mynewt repository.yml

This make it possible to setup Mynewt project with latest releases.
---
 repository.yml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/repository.yml b/repository.yml
index 21d092373..aaec10eb7 100644
--- a/repository.yml
+++ b/repository.yml
@@ -9,7 +9,9 @@ repo.versions:
     "0.10.0": "0.10.0"
     "0.10.1": "0.10.1"
     "0.11.0": "0.11.0"
+    "0.12.0": "0.12.0"
+    "0.13.0": "0.13.0"
 
     "0-dev": "0.0.0"        # master
-    "0-latest": "0.11.0"     # latest stable release
+    "0-latest": "0.13.0"    # latest stable release
 

From ce60e98f6da2030f8fe8c8b6c63a7a33019e6c74 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Mar 2022 23:00:11 +0700
Subject: [PATCH 0871/2085] remove broadcom/synopssy (repalced by
 synopsys/dwc2)

---
 src/portable/broadcom/synopsys/dcd_synopsys.c | 1267 --------------
 .../broadcom/synopsys/synopsys_common.h       | 1476 -----------------
 2 files changed, 2743 deletions(-)
 delete mode 100644 src/portable/broadcom/synopsys/dcd_synopsys.c
 delete mode 100644 src/portable/broadcom/synopsys/synopsys_common.h

diff --git a/src/portable/broadcom/synopsys/dcd_synopsys.c b/src/portable/broadcom/synopsys/dcd_synopsys.c
deleted file mode 100644
index c4881ee50..000000000
--- a/src/portable/broadcom/synopsys/dcd_synopsys.c
+++ /dev/null
@@ -1,1267 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2018 Scott Shawcroft, 2019 William D. Jones for Adafruit Industries
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- * Copyright (c) 2020 Jan Duempelmann
- * Copyright (c) 2020 Reinhard Panhuber
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if CFG_TUD_ENABLED &&         \
-    (CFG_TUSB_MCU == OPT_MCU_BCM2711 ) \
-
-
-#include "synopsys_common.h"
-
-#include "broadcom/interrupts.h"
-
-// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
-// We disable SOF for now until needed later on
-#define USE_SOF     0
-
-// EP_MAX       : Max number of bi-directional endpoints including EP0
-// EP_FIFO_SIZE : Size of dedicated USB SRAM
-#if CFG_TUSB_MCU == OPT_MCU_BCM2711
-// #include "bcm2711.h"
-#define EP_MAX_FS       8
-#define EP_FIFO_SIZE_FS 4096
-#define EP_MAX_HS       8
-#define EP_FIFO_SIZE_HS 4096
-#else
-#error "Unsupported MCUs"
-#endif
-
-#define EP_MAX 8
-#define EP_FIFO_SIZE 4096
-
-// Info on values here: https://github.com/torvalds/linux/blob/79160a603bdb51916226caf4a6616cc4e1c58a58/Documentation/devicetree/bindings/usb/dwc2.yaml
-
-// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm283x.dtsi
-// usb: usb@7e980000 {
-//   compatible = "brcm,bcm2835-usb";
-//   reg = <0x7e980000 0x10000>;
-//   interrupts = <1 9>;
-//   #address-cells = <1>;
-//   #size-cells = <0>;
-//   clocks = <&clk_usb>;
-//   clock-names = "otg";
-//   phys = <&usbphy>;
-//   phy-names = "usb2-phy";
-// };
-
-// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi
-// SPDX-License-Identifier: GPL-2.0
-// &usb {
-//   dr_mode = "otg";
-//   g-rx-fifo-size = <256>;
-//   g-np-tx-fifo-size = <32>;
-  
-//    * According to dwc2 the sum of all device EP
-//    * fifo sizes shouldn't exceed 3776 bytes.
-   
-//   g-tx-fifo-size = <256 256 512 512 512 768 768>;
-// };
-
-// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm2711-rpi.dtsi
-// &usb {
-//   /* Enable the FIQ support */
-//   reg = <0x7e980000 0x10000>,
-//         <0x7e00b200 0x200>;
-//   interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
-//          <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-//   status = "disabled";
-// };
-
-// From: https://github.com/raspberrypi/linux/blob/rpi-5.10.y/arch/arm/boot/dts/bcm2711.dtsi
-// &usb {
-//   interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-// };
-
-// From: https://github.com/torvalds/linux/blob/1d597682d3e669ec7021aa33d088ed3d136a5149/drivers/usb/dwc2/params.c
-// static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
-// {
-//   struct dwc2_core_params *p = &hsotg->params;
-
-//   p->host_rx_fifo_size = 774;
-//   p->max_transfer_size = 65535;
-//   p->max_packet_count = 511;
-//   p->ahbcfg = 0x10;
-// }
-
-#include "device/dcd.h"
-
-TU_VERIFY_STATIC(sizeof(USB_OTG_GlobalTypeDef) == 0x140, "size is incorrect");
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
-
-#define RHPORT_REGS_BASE USB_OTG_GLOBAL_BASE
-
-#define GLOBAL_BASE(_port)     ((USB_OTG_GlobalTypeDef*) RHPORT_REGS_BASE)
-#define DEVICE_BASE(_port)     (USB_OTG_DeviceTypeDef *) (USB_OTG_DEVICE_BASE)
-#define OUT_EP_BASE(_port)     (USB_OTG_OUTEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_OUT_ENDPOINT_BASE)
-#define IN_EP_BASE(_port)      (USB_OTG_INEndpointTypeDef *) (RHPORT_REGS_BASE + USB_OTG_IN_ENDPOINT_BASE)
-#define FIFO_BASE(_port, _x)   ((volatile uint32_t *) (RHPORT_REGS_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE))
-
-enum
-{
-  DCD_HIGH_SPEED        = 0, // Highspeed mode
-  DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY)
-  DCD_FULL_SPEED        = 3, // Full speed with internal PHY
-};
-
-static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
-
-typedef struct {
-  uint8_t * buffer;
-  tu_fifo_t * ff;
-  uint16_t total_len;
-  uint16_t max_size;
-  uint8_t interval;
-} xfer_ctl_t;
-
-typedef volatile uint32_t * usb_fifo_t;
-
-xfer_ctl_t xfer_status[EP_MAX][2];
-#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
-
-// EP0 transfers are limited to 1 packet - larger sizes has to be split
-static uint16_t ep0_pending[2];                   // Index determines direction as tusb_dir_t type
-
-// TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ
-static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
-static bool _out_ep_closed;                       // Flag to check if RX FIFO size needs an update (reduce its size)
-
-// Calculate the RX FIFO size according to recommendations from reference manual
-static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
-{
-  return 15 + 2*(ep_size/4) + 2*EP_MAX;
-}
-
-static void update_grxfsiz(uint8_t rhport)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-
-  // Determine largest EP size for RX FIFO
-  uint16_t max_epsize = 0;
-  for (uint8_t epnum = 0; epnum < EP_MAX; epnum++)
-  {
-    max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
-  }
-
-  // Update size of RX FIFO
-  usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize);
-}
-
-// Setup the control endpoint 0.
-static void bus_reset(uint8_t rhport)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  tu_memclr(xfer_status, sizeof(xfer_status));
-  _out_ep_closed = false;
-
-  // clear device address
-  dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk;
-
-  // 1. NAK for all OUT endpoints
-  for(uint8_t n = 0; n < EP_MAX; n++) {
-    out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
-  }
-
-  // 2. Un-mask interrupt bits
-  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
-  dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
-  dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM;
-
-  // "USB Data FIFOs" section in reference manual
-  // Peripheral FIFO architecture
-  //
-  // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start.
-  // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located
-  // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard
-  // configuration done below.
-  //
-  // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed.
-  // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a
-  // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually
-  // opened when the host sends an additional command: setInterface. At this point in time
-  // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size
-  // an additional memory
-  //
-  // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-  // | IN FIFO 0   |
-  // --------------- (320 or 1024) - 16
-  // | IN FIFO 1   |
-  // --------------- (320 or 1024) - 16 - x
-  // |   . . . .   |
-  // --------------- (320 or 1024) - 16 - x - y - ... - z
-  // | IN FIFO MAX |
-  // ---------------
-  // |    FREE     |
-  // --------------- GRXFSIZ
-  // | OUT FIFO    |
-  // | ( Shared )  |
-  // --------------- 0
-  //
-  // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
-  // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
-  //
-  // - All EP OUT shared a unique OUT FIFO which uses
-  //   - 13 for setup packets + control words (up to 3 setup packets).
-  //   - 1 for global NAK (not required/used here).
-  //   - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is  "2 x (Largest-EPsize/4) + 1"
-  //   - 2 for each used OUT endpoint
-  //
-  //   Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
-  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x EP_MAX = 47  + 2 x EP_MAX
-  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX
-  //
-  //   NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
-  //   of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX
-  //
-  //   For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
-  //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
-  //   overwrite this.
-
-  #if TUD_OPT_HIGH_SPEED
-  usb_otg->GRXFSIZ = calc_rx_ff_size(512);
-  #else
-  usb_otg->GRXFSIZ = calc_rx_ff_size(64);
-  #endif
-
-  _allocated_fifo_words_tx = 16;
-
-  // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
-
-  // Fixed control EP0 size to 64 bytes
-  in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos);
-  xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64;
-
-  out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
-
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT;
-}
-
-// Set turn-around timeout according to link speed
-extern uint32_t SystemCoreClock;
-static void set_turnaround(USB_OTG_GlobalTypeDef * usb_otg, tusb_speed_t speed)
-{
-  usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-
-  if ( speed == TUSB_SPEED_HIGH )
-  {
-    // Use fixed 0x09 for Highspeed
-    usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos);
-  }
-  else
-  {
-    // Turnaround timeout depends on the MCU clock
-    uint32_t turnaround;
-
-    if ( SystemCoreClock >= 32000000U )
-      turnaround = 0x6U;
-    else if ( SystemCoreClock >= 27500000U )
-      turnaround = 0x7U;
-    else if ( SystemCoreClock >= 24000000U )
-      turnaround = 0x8U;
-    else if ( SystemCoreClock >= 21800000U )
-      turnaround = 0x9U;
-    else if ( SystemCoreClock >= 20000000U )
-      turnaround = 0xAU;
-    else if ( SystemCoreClock >= 18500000U )
-      turnaround = 0xBU;
-    else if ( SystemCoreClock >= 17200000U )
-      turnaround = 0xCU;
-    else if ( SystemCoreClock >= 16000000U )
-      turnaround = 0xDU;
-    else if ( SystemCoreClock >= 15000000U )
-      turnaround = 0xEU;
-    else
-      turnaround = 0xFU;
-
-    // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
-    usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos);
-  }
-}
-
-static tusb_speed_t get_speed(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos;
-  return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
-}
-
-static void set_speed(uint8_t rhport, tusb_speed_t speed)
-{
-  uint32_t bitvalue;
-
-  if ( rhport == 1 )
-  {
-    bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS);
-  }
-  else
-  {
-    bitvalue = DCD_FULL_SPEED;
-  }
-
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-
-  // Clear and set speed bits
-  dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos);
-  dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos);
-}
-
-#if 0
-// From CM4IO xtal to usb hub, may not be correct
-#define HSE_VALUE 24000000
-
-static bool USB_HS_PHYCInit(void)
-{
-  USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
-
-  // Enable LDO
-  usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
-
-  // Wait until LDO ready
-  while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
-
-  uint32_t phyc_pll = 0;
-
-  // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
-  switch ( HSE_VALUE )
-  {
-    case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ   ; break;
-    case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
-    case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ   ; break;
-    case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ   ; break;
-    case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ   ; break;
-    case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk     ; break; // Value not defined in header
-    default:
-      TU_ASSERT(0);
-  }
-  usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
-
-  // Control the tuning interface of the High Speed PHY
-  // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
-  usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
-
-  // Enable PLL internal PHY
-  usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
-
-  // Original ST code has 2 ms delay for PLL stabilization.
-  // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
-
-  return true;
-}
-#endif
-
-static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes)
-{
-  (void) rhport;
-
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  // EP0 is limited to one packet each xfer
-  // We use multiple transaction of xfer->max_size length to get a whole transfer done
-  if(epnum == 0) {
-    xfer_ctl_t * const xfer = XFER_CTL_BASE(epnum, dir);
-    total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
-    ep0_pending[dir] -= total_bytes;
-  }
-
-  // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here.
-  if(dir == TUSB_DIR_IN) {
-    // A full IN transfer (multiple packets, possibly) triggers XFRC.
-    in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) |
-        ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk);
-
-    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK;
-    // For ISO endpoint set correct odd/even bit for next frame.
-    if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
-    {
-      // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
-      in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk);
-    }
-    // Enable fifo empty interrupt only if there are something to put in the fifo.
-    if(total_bytes != 0) {
-      dev->DIEPEMPMSK |= (1 << epnum);
-    }
-  } else {
-    // A full OUT transfer (multiple packets, possibly) triggers XFRC.
-    out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ);
-    out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) |
-        ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk);
-
-    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK;
-    if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1)
-    {
-      // Take odd/even bit from frame counter.
-      uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos));
-      out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk);
-    }
-  }
-}
-
-/*------------------------------------------------------------------*/
-/* Controller API
- *------------------------------------------------------------------*/
-
-TU_ATTR_UNUSED
-static void reset_core(USB_OTG_GlobalTypeDef * usb_otg) {
-  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0) {}
-
-  TU_LOG(2, "    resetting\r\n");
-  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-  TU_LOG(2, "    waiting\r\n");
-  while ((usb_otg->GRSTCTL & (USB_OTG_GRSTCTL_AHBIDL | USB_OTG_GRSTCTL_CSRST)) != USB_OTG_GRSTCTL_AHBIDL) {}
-  TU_LOG(2, "    reset done\r\n");
-}
-
-void dcd_init (uint8_t rhport)
-{
-  printf("test done\r\n");
-  // Programming model begins in the last section of the chapter on the USB
-  // peripheral in each Reference Manual.
-  TU_LOG(2, "    dcd_init\r\n");
-
-  TU_LOG2("Test 123\r\n");
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-
-#if 1
-  // No VBUS sense
-  usb_otg->GCCFG &= ~(1UL << 21); // USB_OTG_GCCFG_VBDEN
-
-  // B-peripheral session valid override enable
-  usb_otg->GOTGCTL |= (1UL << 6); // USB_OTG_GOTGCTL_BVALOEN
-  usb_otg->GOTGCTL |= (1UL << 7); // USB_OTG_GOTGCTL_BVALOVAL
-
-  // Force device mode
-  usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
-  usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
-
-  // deactivate internal PHY
-  usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN;
-
-  // Init The UTMI Interface
-  usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
-
-  // Select default internal VBUS Indicator and Drive for ULPI
-  usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
-
-  // Select UTMI Interface
-  usb_otg->GUSBCFG &= ~(1UL << 4); // USB_OTG_GUSBCFG_ULPI_UTMI_SEL
-  usb_otg->GCCFG |= (1UL << 32);   // USB_OTG_GCCFG_PHYHSEN
-
-  // Enables control of a High Speed USB PHY
-  //USB_HS_PHYCInit();
-
-  // Reset core after selecting PHY
-  // Wait AHB IDLE, reset then wait until it is cleared
-//  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) {}
-//  usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
-//  while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) {}
-
-  reset_core(usb_otg);
-
-  // Restart PHY clock
-  *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0;
-
-#else
-
-  // ReadBackReg(&Core->Usb);
-  // Core->Usb.UlpiDriveExternalVbus = 0;
-  // Core->Usb.TsDlinePulseEnable = 0;
-  // WriteThroughReg(&Core->Usb);
-
-  // This sequence is modeled after: https://github.com/Chadderz121/csud/blob/e13b9355d043a9cdd384b335060f1bc0416df61e/source/hcd/dwc/designware20.c#L689
-  usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIEVBUSD);
-  reset_core(usb_otg);
-
-  //   Core->Usb.ModeSelect = UTMI;
-  //   LOG_DEBUG("HCD: Interface: UTMI+.\n");
-  //   Core->Usb.PhyInterface = false;
-
-  //   HcdReset();
-  TU_LOG2("init phy\r\n");
-  usb_otg->GUSBCFG |= (1 << 4); // bit four sets UTMI+ mode
-  usb_otg->GUSBCFG &= ~(1 << 3); // bit three disables phy interface
-  reset_core(usb_otg);
-
-  //   LOG_DEBUG("HCD: ULPI FSLS configuration: disabled.\n");
-  //   Core->Usb.UlpiFsls = false;
-  //   Core->Usb.ulpi_clk_sus_m = false;
-  usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_ULPICSM);
-
-  // LOG_DEBUG("HCD: DMA configuration: enabled.\n");
-  // Core->Ahb.DmaEnable = true;
-  // Core->Ahb.DmaRemainderMode = Incremental;
-  usb_otg->GAHBCFG &= ~(1 << 23); // Remainder mode
-  usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
-
-  //   LOG_DEBUG("HCD: HNP/SRP configuration: HNP, SRP.\n");
-  //   Core->Usb.HnpCapable = true;
-  //   Core->Usb.SrpCapable = true;
-  usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_SRPCAP | USB_OTG_GUSBCFG_HNPCAP;
-
-#endif
-
-  // Clear all interrupts
-  usb_otg->GINTSTS |= usb_otg->GINTSTS;
-
-  // Required as part of core initialization.
-  // TODO: How should mode mismatch be handled? It will cause
-  // the core to stop working/require reset.
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM;
-
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-
-  // If USB host misbehaves during status portion of control xfer
-  // (non zero-length packet), send STALL back and discard.
-  dev->DCFG |=  USB_OTG_DCFG_NZLSOHSK;
-
-  set_speed(rhport, TUSB_SPEED_HIGH);
-
-  // TODO internal phy (full speed)
-  usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN;
-
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST   | USB_OTG_GINTMSK_ENUMDNEM |
-      USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM     |
-      USB_OTG_GINTMSK_RXFLVLM  | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0);
-
-  // Enable global interrupt
-  usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
-
-  dcd_connect(rhport);
-}
-
-void dcd_int_enable (uint8_t rhport)
-{
-  (void) rhport;
-  BP_EnableIRQ(USB_IRQn);
-}
-
-void dcd_int_disable (uint8_t rhport)
-{
-  (void) rhport;
-  BP_DisableIRQ(USB_IRQn);
-}
-
-void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
-{
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos);
-
-  // Response with status after changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-}
-
-static void remote_wakeup_delay(void)
-{
-  // try to delay for 1 ms
-  uint32_t count = SystemCoreClock / 1000;
-  while ( count-- )
-  {
-    // __NOP();
-  }
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-
-  // set remote wakeup
-  dev->DCTL |= USB_OTG_DCTL_RWUSIG;
-
-  // enable SOF to detect bus resume
-  usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
-  usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM;
-
-  // Per specs: remote wakeup signal bit must be clear within 1-15ms
-  remote_wakeup_delay();
-
-  dev->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-}
-
-void dcd_connect(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  dev->DCTL &= ~USB_OTG_DCTL_SDIS;
-}
-
-void dcd_disconnect(uint8_t rhport)
-{
-  (void) rhport;
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  dev->DCTL |= USB_OTG_DCTL_SDIS;
-}
-
-
-/*------------------------------------------------------------------*/
-/* DCD Endpoint port
- *------------------------------------------------------------------*/
-
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
-
-  TU_ASSERT(epnum < EP_MAX);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->max_size = tu_edpt_packet_size(desc_edpt);
-  xfer->interval = desc_edpt->bInterval;
-
-  uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word
-
-  if(dir == TUSB_DIR_OUT)
-  {
-    // Calculate required size of RX FIFO
-    uint16_t const sz = calc_rx_ff_size(4*fifo_size);
-
-    // If size_rx needs to be extended check if possible and if so enlarge it
-    if (usb_otg->GRXFSIZ < sz)
-    {
-      TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE/4);
-
-      // Enlarge RX FIFO
-      usb_otg->GRXFSIZ = sz;
-    }
-
-    out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos)        |
-        (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos)   |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) |
-        (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos);
-
-    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum));
-  }
-  else
-  {
-    // "USB Data FIFOs" section in reference manual
-    // Peripheral FIFO architecture
-    //
-    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-    // | IN FIFO 0   |
-    // --------------- (320 or 1024) - 16
-    // | IN FIFO 1   |
-    // --------------- (320 or 1024) - 16 - x
-    // |   . . . .   |
-    // --------------- (320 or 1024) - 16 - x - y - ... - z
-    // | IN FIFO MAX |
-    // ---------------
-    // |    FREE     |
-    // --------------- GRXFSIZ
-    // | OUT FIFO    |
-    // | ( Shared )  |
-    // --------------- 0
-    //
-    // In FIFO is allocated by following rules:
-    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
-
-    // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE/4);
-
-    _allocated_fifo_words_tx += fifo_size;
-
-    TU_LOG(2, "    Allocated %u bytes at offset %u", fifo_size*4, EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
-
-    // DIEPTXF starts at FIFO #1.
-    // Both TXFD and TXSA are in unit of 32-bit words.
-    usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
-
-    in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) |
-        (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) |
-        (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) |
-        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) |
-        (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos);
-
-    dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum));
-  }
-
-  return true;
-}
-
-// Close all non-control endpoints, cancel all pending transfers if any.
-void dcd_edpt_close_all (uint8_t rhport)
-{
-  (void) rhport;
-
-//  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  // Disable non-control interrupt
-  dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos);
-
-  for(uint8_t n = 1; n < EP_MAX; n++)
-  {
-    // disable OUT endpoint
-    out_ep[n].DOEPCTL = 0;
-    xfer_status[n][TUSB_DIR_OUT].max_size = 0;
-
-    // disable IN endpoint
-    in_ep[n].DIEPCTL = 0;
-    xfer_status[n][TUSB_DIR_IN].max_size = 0;
-  }
-
-  // reset allocated fifo IN
-  _allocated_fifo_words_tx = 16;
-}
-
-bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer      = buffer;
-  xfer->ff          = NULL;
-  xfer->total_len   = total_bytes;
-
-  // EP0 can only handle one packet
-  if(epnum == 0) {
-    ep0_pending[dir] = total_bytes;
-    // Schedule the first transaction for EP0 transfer
-    edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]);
-    return true;
-  }
-
-  uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint16_t const short_packet_size = total_bytes % xfer->max_size;
-
-  // Zero-size packet is special case.
-  if(short_packet_size > 0 || (total_bytes == 0)) {
-    num_packets++;
-  }
-
-  // Schedule packets to be sent within interrupt
-  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
-
-  return true;
-}
-
-// The number of bytes has to be given explicitly to allow more flexible control of how many
-// bytes should be written and second to keep the return value free to give back a boolean
-// success message. If total_bytes is too big, the FIFO will copy only what is available
-// into the USB buffer!
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
-  // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
-  TU_ASSERT(ff->item_size == 1);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
-  xfer->buffer      = NULL;
-  xfer->ff          = ff;
-  xfer->total_len   = total_bytes;
-
-  uint16_t num_packets = (total_bytes / xfer->max_size);
-  uint16_t const short_packet_size = total_bytes % xfer->max_size;
-
-  // Zero-size packet is special case.
-  if(short_packet_size > 0 || (total_bytes == 0)) num_packets++;
-
-  // Schedule packets to be sent within interrupt
-  edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes);
-
-  return true;
-}
-
-static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
-{
-  (void) rhport;
-
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  if(dir == TUSB_DIR_IN) {
-    // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA) ){
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0);
-    } else {
-      // Stop transmitting packets and NAK IN xfers.
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
-      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0);
-
-      // Disable the endpoint.
-      in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0);
-      while((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0);
-      in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD;
-    }
-
-    // Flush the FIFO, and wait until we have confirmed it cleared.
-    usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos);
-    usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
-    while((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
-  } else {
-    // Only disable currently enabled non-control endpoint
-    if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){
-      out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0;
-    } else {
-      // Asserting GONAK is required to STALL an OUT endpoint.
-      // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
-      // anyway, and it can't be cleared by user code. If this while loop never
-      // finishes, we have bigger problems than just the stack.
-      dev->DCTL |= USB_OTG_DCTL_SGONAK;
-      while((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
-
-      // Ditto here- disable the endpoint.
-      out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0);
-      while((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0);
-      out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD;
-
-      // Allow other OUT endpoints to keep receiving.
-      dev->DCTL |= USB_OTG_DCTL_CGONAK;
-    }
-  }
-}
-
-/**
- * Close an endpoint.
- */
-void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
-{
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  dcd_edpt_disable(rhport, ep_addr, false);
-
-  // Update max_size
-  xfer_status[epnum][dir].max_size = 0;  // max_size = 0 marks a disabled EP - required for changing FIFO allocation
-
-  if (dir == TUSB_DIR_IN)
-  {
-    uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos;
-    uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos;
-    // For now only the last opened endpoint can be closed without fuss.
-    TU_ASSERT(fifo_start == EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
-    _allocated_fifo_words_tx -= fifo_size;
-  }
-  else
-  {
-    _out_ep_closed = true;     // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty
-  }
-}
-
-void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  dcd_edpt_disable(rhport, ep_addr, true);
-}
-
-void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
-{
-  (void) rhport;
-
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  // Clear stall and reset data toggle
-  if(dir == TUSB_DIR_IN) {
-    in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-    in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
-  } else {
-    out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
-    out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
-  }
-}
-
-/*------------------------------------------------------------------*/
-
-// Read a single data packet from receive FIFO
-static void read_fifo_packet(uint8_t rhport, uint8_t * dst, uint16_t len)
-{
-  (void) rhport;
-
-  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
-
-  // Reading full available 32 bit words from fifo
-  uint16_t full_words = len >> 2;
-  for(uint16_t i = 0; i < full_words; i++) {
-    uint32_t tmp = *rx_fifo;
-    dst[0] = tmp & 0x000000FF;
-    dst[1] = (tmp & 0x0000FF00) >> 8;
-    dst[2] = (tmp & 0x00FF0000) >> 16;
-    dst[3] = (tmp & 0xFF000000) >> 24;
-    dst += 4;
-  }
-
-  // Read the remaining 1-3 bytes from fifo
-  uint8_t bytes_rem = len & 0x03;
-  if(bytes_rem != 0) {
-    uint32_t tmp = *rx_fifo;
-    dst[0] = tmp & 0x000000FF;
-    if(bytes_rem > 1) {
-      dst[1] = (tmp & 0x0000FF00) >> 8;
-    }
-    if(bytes_rem > 2) {
-      dst[2] = (tmp & 0x00FF0000) >> 16;
-    }
-  }
-}
-
-// Write a single data packet to EPIN FIFO
-static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t * src, uint16_t len)
-{
-  (void) rhport;
-
-  usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num);
-
-  // Pushing full available 32 bit words to fifo
-  uint16_t full_words = len >> 2;
-  for(uint16_t i = 0; i < full_words; i++){
-    *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0];
-    src += 4;
-  }
-
-  // Write the remaining 1-3 bytes into fifo
-  uint8_t bytes_rem = len & 0x03;
-  if(bytes_rem){
-    uint32_t tmp_word = 0;
-    tmp_word |= src[0];
-    if(bytes_rem > 1){
-      tmp_word |= src[1] << 8;
-    }
-    if(bytes_rem > 2){
-      tmp_word |= src[2] << 16;
-    }
-    *tx_fifo = tmp_word;
-  }
-}
-
-static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef * out_ep) {
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0);
-
-  // Pop control word off FIFO
-  uint32_t ctl_word = usb_otg->GRXSTSP;
-  uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos;
-  uint8_t epnum = (ctl_word &  USB_OTG_GRXSTSP_EPNUM_Msk) >>  USB_OTG_GRXSTSP_EPNUM_Pos;
-  uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos;
-
-  switch(pktsts) {
-    case 0x01: // Global OUT NAK (Interrupt)
-      break;
-
-    case 0x02: // Out packet recvd
-    {
-      xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
-
-      // Read packet off RxFIFO
-      if (xfer->ff)
-      {
-        // Ring buffer
-        tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t) rx_fifo, bcnt);
-      }
-      else
-      {
-        // Linear buffer
-        read_fifo_packet(rhport, xfer->buffer, bcnt);
-
-        // Increment pointer to xfer data
-        xfer->buffer += bcnt;
-      }
-
-      // Truncate transfer length in case of short packet
-      if(bcnt < xfer->max_size) {
-        xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos;
-        if(epnum == 0) {
-          xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
-          ep0_pending[TUSB_DIR_OUT] = 0;
-        }
-      }
-    }
-    break;
-
-    case 0x03: // Out packet done (Interrupt)
-      break;
-
-    case 0x04: // Setup packet done (Interrupt)
-      out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
-      break;
-
-    case 0x06: // Setup packet recvd
-      // We can receive up to three setup packets in succession, but
-      // only the last one is valid.
-      _setup_packet[0] = (* rx_fifo);
-      _setup_packet[1] = (* rx_fifo);
-      break;
-
-    default: // Invalid
-      TU_BREAKPOINT();
-      break;
-  }
-}
-
-static void handle_epout_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_OUTEndpointTypeDef * out_ep) {
-  // DAINT for a given EP clears when DOEPINTx is cleared.
-  // OEPINT will be cleared when DAINT's out bits are cleared.
-  for(uint8_t n = 0; n < EP_MAX; n++) {
-    xfer_ctl_t * xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
-
-    if(dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) {
-      // SETUP packet Setup Phase done.
-      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) {
-        out_ep[n].DOEPINT =  USB_OTG_DOEPINT_STUP;
-        dcd_event_setup_received(rhport, (uint8_t*) &_setup_packet[0], true);
-      }
-
-      // OUT XFER complete
-      if(out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) {
-        out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC;
-
-        // EP0 can only handle one packet
-        if((n == 0) && ep0_pending[TUSB_DIR_OUT]) {
-          // Schedule another packet to be received.
-          edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]);
-        } else {
-          dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        }
-      }
-    }
-  }
-}
-
-static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef * dev, USB_OTG_INEndpointTypeDef * in_ep) {
-  // DAINT for a given EP clears when DIEPINTx is cleared.
-  // IEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < EP_MAX; n++ )
-  {
-    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN);
-
-    if ( dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n)) )
-    {
-      // IN XFER complete (entire xfer).
-      if ( in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC )
-      {
-        in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC;
-
-        // EP0 can only handle one packet
-        if((n == 0) && ep0_pending[TUSB_DIR_IN]) {
-          // Schedule another packet to be transmitted.
-          edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]);
-        } else {
-          dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
-        }
-      }
-
-      // XFER FIFO empty
-      if ( (in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n)) )
-      {
-        // DIEPINT's TXFE bit is read-only, software cannot clear it.
-        // It will only be cleared by hardware when written bytes is more than
-        // - 64 bytes or
-        // - Half of TX FIFO size (configured by DIEPTXF)
-
-        uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos;
-
-        // Process every single packet (only whole packets can be written to fifo)
-        for(uint16_t i = 0; i < remaining_packets; i++)
-        {
-          uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos;
-
-          // Packet can not be larger than ep max size
-          uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size);
-
-          // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current
-          // EP has to be checked if the buffer can take another WHOLE packet
-          if(packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) break;
-
-          // Push packet to Tx-FIFO
-          if (xfer->ff)
-          {
-            usb_fifo_t tx_fifo = FIFO_BASE(rhport, n);
-            tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t) tx_fifo, packet_size);
-          }
-          else
-          {
-            write_fifo_packet(rhport, n, xfer->buffer, packet_size);
-
-            // Increment pointer to xfer data
-            xfer->buffer += packet_size;
-          }
-        }
-
-        // Turn off TXFE if all bytes are written.
-        if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0)
-        {
-          dev->DIEPEMPMSK &= ~(1 << n);
-        }
-      }
-    }
-  }
-}
-
-void dcd_int_handler(uint8_t rhport)
-{
-  USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport);
-  USB_OTG_DeviceTypeDef * dev = DEVICE_BASE(rhport);
-  USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE(rhport);
-  USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE(rhport);
-
-  uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK;
-
-  if(int_status & USB_OTG_GINTSTS_USBRST)
-  {
-    // USBRST is start of reset.
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST;
-    bus_reset(rhport);
-  }
-
-  if(int_status & USB_OTG_GINTSTS_ENUMDNE)
-  {
-    // ENUMDNE is the end of reset where speed of the link is detected
-
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE;
-
-    tusb_speed_t const speed = get_speed(rhport);
-
-    set_turnaround(usb_otg, speed);
-    dcd_event_bus_reset(rhport, speed, true);
-  }
-
-  if(int_status & USB_OTG_GINTSTS_USBSUSP)
-  {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP;
-    dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-  }
-
-  if(int_status & USB_OTG_GINTSTS_WKUINT)
-  {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT;
-    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-  }
-
-  // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection
-  // if(int_status & USB_OTG_GINTSTS_DISCINT)
-
-  if(int_status & USB_OTG_GINTSTS_OTGINT)
-  {
-    // OTG INT bit is read-only
-    uint32_t const otg_int = usb_otg->GOTGINT;
-
-    if (otg_int & USB_OTG_GOTGINT_SEDET)
-    {
-      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-    }
-
-    usb_otg->GOTGINT = otg_int;
-  }
-
-  if(int_status & USB_OTG_GINTSTS_SOF)
-  {
-    usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF;
-
-    // Disable SOF interrupt since currently only used for remote wakeup detection
-    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM;
-
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-  }
-
-  // RxFIFO non-empty interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_RXFLVL)
-  {
-    // RXFLVL bit is read-only
-
-    // Mask out RXFLVL while reading data from FIFO
-    usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM;
-
-    // Loop until all available packets were handled
-    do
-    {
-      handle_rxflvl_ints(rhport, out_ep);
-    } while(usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL);
-
-    // Manage RX FIFO size
-    if (_out_ep_closed)
-    {
-      update_grxfsiz(rhport);
-
-      // Disable flag
-      _out_ep_closed = false;
-    }
-
-    usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
-  }
-
-  // OUT endpoint interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_OEPINT)
-  {
-    // OEPINT is read-only
-    handle_epout_ints(rhport, dev, out_ep);
-  }
-
-  // IN endpoint interrupt handling.
-  if(int_status & USB_OTG_GINTSTS_IEPINT)
-  {
-    // IEPINT bit read-only
-    handle_epin_ints(rhport, dev, in_ep);
-  }
-
-  //  // Check for Incomplete isochronous IN transfer
-  //  if(int_status & USB_OTG_GINTSTS_IISOIXFR) {
-  //    printf("      IISOIXFR!\r\n");
-  ////    TU_LOG2("      IISOIXFR!\r\n");
-  //  }
-}
-
-#endif
diff --git a/src/portable/broadcom/synopsys/synopsys_common.h b/src/portable/broadcom/synopsys/synopsys_common.h
deleted file mode 100644
index 81ce3b4a9..000000000
--- a/src/portable/broadcom/synopsys/synopsys_common.h
+++ /dev/null
@@ -1,1476 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    synopsys_common.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device USB OTG peripheral Header File. 
-  *          This file contains the USB OTG peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32F1xx devices.
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for the USB OTG peripheral
-  *           - The Peripheral's registers declarations and bits definition
-  *           - Macros to access the peripheral's registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-#include "stdint.h"
-
-#pragma once
-
-#ifdef __cplusplus
-  #define   __I   volatile
-#else
-  #define   __I   volatile const
-#endif
-#define     __O   volatile
-#define     __IO  volatile
-#define     __IM  volatile const
-#define     __OM  volatile
-#define     __IOM volatile
-
-/** 
-  * @brief __USB_OTG_Core_register
-  */
-
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register       Address offset: 000h */
-  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                Address offset: 004h */
-  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register           Address offset: 008h */
-  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register           Address offset: 00Ch */
-  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                       Address offset: 010h */
-  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                   Address offset: 014h */
-  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register              Address offset: 018h */
-  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register               Address offset: 01Ch */
-  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register         Address offset: 020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                 Address offset: 024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register  Address offset: 028h */
-  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg        Address offset: 02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved 030h*/
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                Address offset: 038h */
-  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
-  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
-  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
-  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
-  uint32_t  Reserved6;                /*!< Reserved                                     050h */
-  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
-  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
-  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
-   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
-    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg             Address offset: 100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                 Address offset: 0x104 */
-} USB_OTG_GlobalTypeDef;
-
-
-
-/** 
-  * @brief __device_Registers
-  */
-
-typedef struct 
-{
-  __IO uint32_t DCFG;                 /*!< dev Configuration Register                 Address offset: 800h*/
-  __IO uint32_t DCTL;                 /*!< dev Control Register                       Address offset: 804h*/
-  __IO uint32_t DSTS;                 /*!< dev Status Register (RO)                   Address offset: 808h*/
-  uint32_t Reserved0C;                /*!< Reserved 80Ch*/
-  __IO uint32_t DIEPMSK;              /*!< dev IN Endpoint Mask                       Address offset: 810h*/
-  __IO uint32_t DOEPMSK;              /*!< dev OUT Endpoint Mask                      Address offset: 814h*/
-  __IO uint32_t DAINT;                /*!< dev All Endpoints Itr Reg                  Address offset: 818h*/
-  __IO uint32_t DAINTMSK;             /*!< dev All Endpoints Itr Mask                 Address offset: 81Ch*/
-  uint32_t  Reserved20;               /*!< Reserved 820h*/
-  uint32_t Reserved9;                 /*!< Reserved 824h*/
-  __IO uint32_t DVBUSDIS;             /*!< dev VBUS discharge Register                Address offset: 828h*/
-  __IO uint32_t DVBUSPULSE;           /*!< dev VBUS Pulse Register                    Address offset: 82Ch*/
-  __IO uint32_t DTHRCTL;              /*!< dev thr                                    Address offset: 830h*/
-  __IO uint32_t DIEPEMPMSK;           /*!< dev empty msk                              Address offset: 834h*/
-  __IO uint32_t DEACHINT;             /*!< dedicated EP interrupt                     Address offset: 838h*/
-  __IO uint32_t DEACHMSK;             /*!< dedicated EP msk                           Address offset: 83Ch*/  
-  uint32_t Reserved40;                /*!< dedicated EP mask                          Address offset: 840h*/
-  __IO uint32_t DINEP1MSK;            /*!< dedicated EP mask                          Address offset: 844h*/
-  uint32_t  Reserved44[15];           /*!< Reserved 844-87Ch*/
-  __IO uint32_t DOUTEP1MSK;           /*!< dedicated EP msk                           Address offset: 884h*/
-} USB_OTG_DeviceTypeDef;
-
-/** 
-  * @brief __IN_Endpoint-Specific_Register
-  */
-
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;              /*!< dev IN Endpoint Control Reg                900h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;                /*!< Reserved                                   900h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DIEPINT;              /*!< dev IN Endpoint Itr Reg                    900h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;                /*!< Reserved                                   900h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DIEPTSIZ;             /*!< IN Endpoint Txfer Size                     900h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DIEPDMA;              /*!< IN Endpoint DMA Address Reg                900h + (ep_num * 20h) + 14h*/
-  __IO uint32_t DTXFSTS;              /*!< IN Endpoint Tx FIFO Status Reg             900h + (ep_num * 20h) + 18h*/
-  uint32_t Reserved18;                /*!< Reserved                                   900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
-} USB_OTG_INEndpointTypeDef;
-
-/** 
-  * @brief __OUT_Endpoint-Specific_Registers
-  */
-
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;              /*!< dev OUT Endpoint Control Reg               B00h + (ep_num * 20h) + 00h*/
-  uint32_t Reserved04;                /*!< Reserved                                   B00h + (ep_num * 20h) + 04h*/
-  __IO uint32_t DOEPINT;              /*!< dev OUT Endpoint Itr Reg                   B00h + (ep_num * 20h) + 08h*/
-  uint32_t Reserved0C;                /*!< Reserved                                   B00h + (ep_num * 20h) + 0Ch*/
-  __IO uint32_t DOEPTSIZ;             /*!< dev OUT Endpoint Txfer Size                B00h + (ep_num * 20h) + 10h*/
-  __IO uint32_t DOEPDMA;              /*!< dev OUT Endpoint DMA Address               B00h + (ep_num * 20h) + 14h*/
-  uint32_t Reserved18[2];             /*!< Reserved                                   B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
-} USB_OTG_OUTEndpointTypeDef;
-
-/** 
-  * @brief __Host_Mode_Register_Structures
-  */
-
-typedef struct 
-{
-  __IO uint32_t HCFG;                 /*!< Host Configuration Register    400h*/
-  __IO uint32_t HFIR;                 /*!< Host Frame Interval Register   404h*/
-  __IO uint32_t HFNUM;                /*!< Host Frame Nbr/Frame Remaining 408h*/
-  uint32_t Reserved40C;               /*!< Reserved                       40Ch*/
-  __IO uint32_t HPTXSTS;              /*!< Host Periodic Tx FIFO/ Queue Status 410h*/
-  __IO uint32_t HAINT;                /*!< Host All Channels Interrupt Register 414h*/
-  __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask 418h*/
-} USB_OTG_HostTypeDef;
-
-/** 
-  * @brief __Host_Channel_Specific_Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t HCCHAR;
-  __IO uint32_t HCSPLT;
-  __IO uint32_t HCINT;
-  __IO uint32_t HCINTMSK;
-  __IO uint32_t HCTSIZ;
-  __IO uint32_t HCDMA;
-  uint32_t Reserved[2];
-} USB_OTG_HostChannelTypeDef;
-
-/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
-
-// #define USB_OTG_GLOBAL_BASE                  0x00000000UL
-// #define USB_OTG_DEVICE_BASE                  0x00000800UL
-#define USB_OTG_IN_ENDPOINT_BASE             0x00000900UL
-#define USB_OTG_OUT_ENDPOINT_BASE            0x00000B00UL
-#define USB_OTG_EP_REG_SIZE                  0x00000020UL
-// #define USB_OTG_HOST_BASE                    0x00000400UL
-#define USB_OTG_HOST_PORT_BASE               0x00000440UL
-#define USB_OTG_HOST_CHANNEL_BASE            0x00000500UL
-#define USB_OTG_HOST_CHANNEL_SIZE            0x00000020UL
-#define USB_OTG_PCGCCTL_BASE                 0x00000E00UL
-#define USB_OTG_FIFO_BASE                    0x00001000UL
-#define USB_OTG_FIFO_SIZE                    0x00001000UL
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 USB_OTG                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
-#define USB_OTG_GOTGCTL_SRQSCS_Pos              (0U)                           
-#define USB_OTG_GOTGCTL_SRQSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
-#define USB_OTG_GOTGCTL_SRQSCS                  USB_OTG_GOTGCTL_SRQSCS_Msk     /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ_Pos                 (1U)                           
-#define USB_OTG_GOTGCTL_SRQ_Msk                 (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
-#define USB_OTG_GOTGCTL_SRQ                     USB_OTG_GOTGCTL_SRQ_Msk        /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS_Pos              (8U)                           
-#define USB_OTG_GOTGCTL_HNGSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
-#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ_Pos               (9U)                           
-#define USB_OTG_GOTGCTL_HNPRQ_Msk               (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
-#define USB_OTG_GOTGCTL_HNPRQ                   USB_OTG_GOTGCTL_HNPRQ_Msk      /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN_Pos             (10U)                          
-#define USB_OTG_GOTGCTL_HSHNPEN_Msk             (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_GOTGCTL_HSHNPEN                 USB_OTG_GOTGCTL_HSHNPEN_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN_Pos              (11U)                          
-#define USB_OTG_GOTGCTL_DHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
-#define USB_OTG_GOTGCTL_DHNPEN                  USB_OTG_GOTGCTL_DHNPEN_Msk     /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS_Pos              (16U)                          
-#define USB_OTG_GOTGCTL_CIDSTS_Msk              (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
-#define USB_OTG_GOTGCTL_CIDSTS                  USB_OTG_GOTGCTL_CIDSTS_Msk     /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT_Pos                (17U)                          
-#define USB_OTG_GOTGCTL_DBCT_Msk                (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
-#define USB_OTG_GOTGCTL_DBCT                    USB_OTG_GOTGCTL_DBCT_Msk       /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD_Pos               (18U)                          
-#define USB_OTG_GOTGCTL_ASVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
-#define USB_OTG_GOTGCTL_ASVLD                   USB_OTG_GOTGCTL_ASVLD_Msk      /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD_Pos               (19U)                          
-#define USB_OTG_GOTGCTL_BSVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
-#define USB_OTG_GOTGCTL_BSVLD                   USB_OTG_GOTGCTL_BSVLD_Msk      /*!< B-session valid */
-
-/********************  Bit definition for USB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS_Pos                (0U)                           
-#define USB_OTG_HCFG_FSLSPCS_Msk                (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
-#define USB_OTG_HCFG_FSLSPCS                    USB_OTG_HCFG_FSLSPCS_Msk       /*!< FS/LS PHY clock select */
-#define USB_OTG_HCFG_FSLSPCS_0                  (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCFG_FSLSPCS_1                  (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCFG_FSLSS_Pos                  (2U)                           
-#define USB_OTG_HCFG_FSLSS_Msk                  (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCFG_FSLSS                      USB_OTG_HCFG_FSLSS_Msk         /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD_Pos                   (0U)                           
-#define USB_OTG_DCFG_DSPD_Msk                   (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
-#define USB_OTG_DCFG_DSPD                       USB_OTG_DCFG_DSPD_Msk          /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                     (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
-#define USB_OTG_DCFG_DSPD_1                     (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCFG_NZLSOHSK_Pos               (2U)                           
-#define USB_OTG_DCFG_NZLSOHSK_Msk               (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
-#define USB_OTG_DCFG_NZLSOHSK                   USB_OTG_DCFG_NZLSOHSK_Msk      /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD_Pos                    (4U)                           
-#define USB_OTG_DCFG_DAD_Msk                    (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                        USB_OTG_DCFG_DAD_Msk           /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                      (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
-#define USB_OTG_DCFG_DAD_1                      (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
-#define USB_OTG_DCFG_DAD_2                      (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCFG_DAD_3                      (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
-#define USB_OTG_DCFG_DAD_4                      (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
-#define USB_OTG_DCFG_DAD_5                      (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
-#define USB_OTG_DCFG_DAD_6                      (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
-
-#define USB_OTG_DCFG_PFIVL_Pos                  (11U)                          
-#define USB_OTG_DCFG_PFIVL_Msk                  (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                      USB_OTG_DCFG_PFIVL_Msk         /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                    (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
-#define USB_OTG_DCFG_PFIVL_1                    (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
-
-#define USB_OTG_DCFG_PERSCHIVL_Pos              (24U)                          
-#define USB_OTG_DCFG_PERSCHIVL_Msk              (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                  USB_OTG_DCFG_PERSCHIVL_Msk     /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0                (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
-#define USB_OTG_DCFG_PERSCHIVL_1                (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK_Pos               (0U)                           
-#define USB_OTG_PCGCR_STPPCLK_Msk               (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
-#define USB_OTG_PCGCR_STPPCLK                   USB_OTG_PCGCR_STPPCLK_Msk      /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK_Pos              (1U)                           
-#define USB_OTG_PCGCR_GATEHCLK_Msk              (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
-#define USB_OTG_PCGCR_GATEHCLK                  USB_OTG_PCGCR_GATEHCLK_Msk     /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP_Pos               (4U)                           
-#define USB_OTG_PCGCR_PHYSUSP_Msk               (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
-#define USB_OTG_PCGCR_PHYSUSP                   USB_OTG_PCGCR_PHYSUSP_Msk      /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET_Pos               (2U)                           
-#define USB_OTG_GOTGINT_SEDET_Msk               (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
-#define USB_OTG_GOTGINT_SEDET                   USB_OTG_GOTGINT_SEDET_Msk      /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG_Pos             (8U)                           
-#define USB_OTG_GOTGINT_SRSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
-#define USB_OTG_GOTGINT_SRSSCHG                 USB_OTG_GOTGINT_SRSSCHG_Msk    /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG_Pos             (9U)                           
-#define USB_OTG_GOTGINT_HNSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
-#define USB_OTG_GOTGINT_HNSSCHG                 USB_OTG_GOTGINT_HNSSCHG_Msk    /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET_Pos              (17U)                          
-#define USB_OTG_GOTGINT_HNGDET_Msk              (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
-#define USB_OTG_GOTGINT_HNGDET                  USB_OTG_GOTGINT_HNGDET_Msk     /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG_Pos             (18U)                          
-#define USB_OTG_GOTGINT_ADTOCHG_Msk             (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
-#define USB_OTG_GOTGINT_ADTOCHG                 USB_OTG_GOTGINT_ADTOCHG_Msk    /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE_Pos              (19U)                          
-#define USB_OTG_GOTGINT_DBCDNE_Msk              (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
-#define USB_OTG_GOTGINT_DBCDNE                  USB_OTG_GOTGINT_DBCDNE_Msk     /*!< Debounce done */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG_Pos                 (0U)                           
-#define USB_OTG_DCTL_RWUSIG_Msk                 (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
-#define USB_OTG_DCTL_RWUSIG                     USB_OTG_DCTL_RWUSIG_Msk        /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS_Pos                   (1U)                           
-#define USB_OTG_DCTL_SDIS_Msk                   (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCTL_SDIS                       USB_OTG_DCTL_SDIS_Msk          /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS_Pos                 (2U)                           
-#define USB_OTG_DCTL_GINSTS_Msk                 (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
-#define USB_OTG_DCTL_GINSTS                     USB_OTG_DCTL_GINSTS_Msk        /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS_Pos                 (3U)                           
-#define USB_OTG_DCTL_GONSTS_Msk                 (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
-#define USB_OTG_DCTL_GONSTS                     USB_OTG_DCTL_GONSTS_Msk        /*!< Global OUT NAK status */
-
-#define USB_OTG_DCTL_TCTL_Pos                   (4U)                           
-#define USB_OTG_DCTL_TCTL_Msk                   (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
-#define USB_OTG_DCTL_TCTL                       USB_OTG_DCTL_TCTL_Msk          /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                     (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
-#define USB_OTG_DCTL_TCTL_1                     (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
-#define USB_OTG_DCTL_TCTL_2                     (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCTL_SGINAK_Pos                 (7U)                           
-#define USB_OTG_DCTL_SGINAK_Msk                 (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
-#define USB_OTG_DCTL_SGINAK                     USB_OTG_DCTL_SGINAK_Msk        /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK_Pos                 (8U)                           
-#define USB_OTG_DCTL_CGINAK_Msk                 (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
-#define USB_OTG_DCTL_CGINAK                     USB_OTG_DCTL_CGINAK_Msk        /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK_Pos                 (9U)                           
-#define USB_OTG_DCTL_SGONAK_Msk                 (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
-#define USB_OTG_DCTL_SGONAK                     USB_OTG_DCTL_SGONAK_Msk        /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK_Pos                 (10U)                          
-#define USB_OTG_DCTL_CGONAK_Msk                 (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
-#define USB_OTG_DCTL_CGONAK                     USB_OTG_DCTL_CGONAK_Msk        /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE_Pos               (11U)                          
-#define USB_OTG_DCTL_POPRGDNE_Msk               (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
-#define USB_OTG_DCTL_POPRGDNE                   USB_OTG_DCTL_POPRGDNE_Msk      /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL_Pos                  (0U)                           
-#define USB_OTG_HFIR_FRIVL_Msk                  (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HFIR_FRIVL                      USB_OTG_HFIR_FRIVL_Msk         /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM_Pos                 (0U)                           
-#define USB_OTG_HFNUM_FRNUM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HFNUM_FRNUM                     USB_OTG_HFNUM_FRNUM_Msk        /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM_Pos                 (16U)                          
-#define USB_OTG_HFNUM_FTREM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_HFNUM_FTREM                     USB_OTG_HFNUM_FTREM_Msk        /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS_Pos                (0U)                           
-#define USB_OTG_DSTS_SUSPSTS_Msk                (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
-#define USB_OTG_DSTS_SUSPSTS                    USB_OTG_DSTS_SUSPSTS_Msk       /*!< Suspend status */
-
-#define USB_OTG_DSTS_ENUMSPD_Pos                (1U)                           
-#define USB_OTG_DSTS_ENUMSPD_Msk                (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
-#define USB_OTG_DSTS_ENUMSPD                    USB_OTG_DSTS_ENUMSPD_Msk       /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0                  (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DSTS_ENUMSPD_1                  (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
-#define USB_OTG_DSTS_EERR_Pos                   (3U)                           
-#define USB_OTG_DSTS_EERR_Msk                   (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
-#define USB_OTG_DSTS_EERR                       USB_OTG_DSTS_EERR_Msk          /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF_Pos                  (8U)                           
-#define USB_OTG_DSTS_FNSOF_Msk                  (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
-#define USB_OTG_DSTS_FNSOF                      USB_OTG_DSTS_FNSOF_Msk         /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT_Pos                (0U)                           
-#define USB_OTG_GAHBCFG_GINT_Msk                (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
-#define USB_OTG_GAHBCFG_GINT                    USB_OTG_GAHBCFG_GINT_Msk       /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)                           
-#define USB_OTG_GAHBCFG_HBSTLEN_Msk             (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
-#define USB_OTG_GAHBCFG_HBSTLEN                 USB_OTG_GAHBCFG_HBSTLEN_Msk    /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
-#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
-#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
-#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
-#define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)                           
-#define USB_OTG_GAHBCFG_DMAEN_Msk               (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
-#define USB_OTG_GAHBCFG_DMAEN                   USB_OTG_GAHBCFG_DMAEN_Msk      /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL_Pos             (7U)                           
-#define USB_OTG_GAHBCFG_TXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
-#define USB_OTG_GAHBCFG_TXFELVL                 USB_OTG_GAHBCFG_TXFELVL_Msk    /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL_Pos            (8U)                           
-#define USB_OTG_GAHBCFG_PTXFELVL_Msk            (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
-#define USB_OTG_GAHBCFG_PTXFELVL                USB_OTG_GAHBCFG_PTXFELVL_Msk   /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL_Pos               (0U)                           
-#define USB_OTG_GUSBCFG_TOCAL_Msk               (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
-#define USB_OTG_GUSBCFG_TOCAL                   USB_OTG_GUSBCFG_TOCAL_Msk      /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
-#define USB_OTG_GUSBCFG_TOCAL_1                 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
-#define USB_OTG_GUSBCFG_TOCAL_2                 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
-#define USB_OTG_GUSBCFG_PHYSEL_Pos              (6U)                           
-#define USB_OTG_GUSBCFG_PHYSEL_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
-#define USB_OTG_GUSBCFG_PHYSEL                  USB_OTG_GUSBCFG_PHYSEL_Msk     /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP_Pos              (8U)                           
-#define USB_OTG_GUSBCFG_SRPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
-#define USB_OTG_GUSBCFG_SRPCAP                  USB_OTG_GUSBCFG_SRPCAP_Msk     /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP_Pos              (9U)                           
-#define USB_OTG_GUSBCFG_HNPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
-#define USB_OTG_GUSBCFG_HNPCAP                  USB_OTG_GUSBCFG_HNPCAP_Msk     /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT_Pos                (10U)                          
-#define USB_OTG_GUSBCFG_TRDT_Msk                (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
-#define USB_OTG_GUSBCFG_TRDT                    USB_OTG_GUSBCFG_TRDT_Msk       /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                  (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
-#define USB_OTG_GUSBCFG_TRDT_1                  (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
-#define USB_OTG_GUSBCFG_TRDT_2                  (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
-#define USB_OTG_GUSBCFG_TRDT_3                  (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
-#define USB_OTG_GUSBCFG_PHYLPCS_Pos             (15U)                          
-#define USB_OTG_GUSBCFG_PHYLPCS_Msk             (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
-#define USB_OTG_GUSBCFG_PHYLPCS                 USB_OTG_GUSBCFG_PHYLPCS_Msk    /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS_Pos            (17U)                          
-#define USB_OTG_GUSBCFG_ULPIFSLS_Msk            (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
-#define USB_OTG_GUSBCFG_ULPIFSLS                USB_OTG_GUSBCFG_ULPIFSLS_Msk   /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR_Pos              (18U)                          
-#define USB_OTG_GUSBCFG_ULPIAR_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
-#define USB_OTG_GUSBCFG_ULPIAR                  USB_OTG_GUSBCFG_ULPIAR_Msk     /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM_Pos             (19U)                          
-#define USB_OTG_GUSBCFG_ULPICSM_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
-#define USB_OTG_GUSBCFG_ULPICSM                 USB_OTG_GUSBCFG_ULPICSM_Msk    /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos          (20U)                          
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD              USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos          (21U)                          
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI              USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS_Pos               (22U)                          
-#define USB_OTG_GUSBCFG_TSDPS_Msk               (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
-#define USB_OTG_GUSBCFG_TSDPS                   USB_OTG_GUSBCFG_TSDPS_Msk      /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI_Pos                (23U)                          
-#define USB_OTG_GUSBCFG_PCCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
-#define USB_OTG_GUSBCFG_PCCI                    USB_OTG_GUSBCFG_PCCI_Msk       /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI_Pos                (24U)                          
-#define USB_OTG_GUSBCFG_PTCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
-#define USB_OTG_GUSBCFG_PTCI                    USB_OTG_GUSBCFG_PTCI_Msk       /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD_Pos             (25U)                          
-#define USB_OTG_GUSBCFG_ULPIIPD_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
-#define USB_OTG_GUSBCFG_ULPIIPD                 USB_OTG_GUSBCFG_ULPIIPD_Msk    /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD_Pos               (29U)                          
-#define USB_OTG_GUSBCFG_FHMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
-#define USB_OTG_GUSBCFG_FHMOD                   USB_OTG_GUSBCFG_FHMOD_Msk      /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD_Pos               (30U)                          
-#define USB_OTG_GUSBCFG_FDMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
-#define USB_OTG_GUSBCFG_FDMOD                   USB_OTG_GUSBCFG_FDMOD_Msk      /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT_Pos              (31U)                          
-#define USB_OTG_GUSBCFG_CTXPKT_Msk              (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                  USB_OTG_GUSBCFG_CTXPKT_Msk     /*!< Corrupt Tx packet */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST_Pos               (0U)                           
-#define USB_OTG_GRSTCTL_CSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
-#define USB_OTG_GRSTCTL_CSRST                   USB_OTG_GRSTCTL_CSRST_Msk      /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST_Pos               (1U)                           
-#define USB_OTG_GRSTCTL_HSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
-#define USB_OTG_GRSTCTL_HSRST                   USB_OTG_GRSTCTL_HSRST_Msk      /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST_Pos               (2U)                           
-#define USB_OTG_GRSTCTL_FCRST_Msk               (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
-#define USB_OTG_GRSTCTL_FCRST                   USB_OTG_GRSTCTL_FCRST_Msk      /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH_Pos             (4U)                           
-#define USB_OTG_GRSTCTL_RXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
-#define USB_OTG_GRSTCTL_RXFFLSH                 USB_OTG_GRSTCTL_RXFFLSH_Msk    /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH_Pos             (5U)                           
-#define USB_OTG_GRSTCTL_TXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
-#define USB_OTG_GRSTCTL_TXFFLSH                 USB_OTG_GRSTCTL_TXFFLSH_Msk    /*!< TxFIFO flush */
-
-
-#define USB_OTG_GRSTCTL_TXFNUM_Pos              (6U)                           
-#define USB_OTG_GRSTCTL_TXFNUM_Msk              (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
-#define USB_OTG_GRSTCTL_TXFNUM                  USB_OTG_GRSTCTL_TXFNUM_Msk     /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GRSTCTL_DMAREQ_Pos              (30U)                          
-#define USB_OTG_GRSTCTL_DMAREQ_Msk              (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
-#define USB_OTG_GRSTCTL_DMAREQ                  USB_OTG_GRSTCTL_DMAREQ_Msk     /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL_Pos              (31U)                          
-#define USB_OTG_GRSTCTL_AHBIDL_Msk              (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
-#define USB_OTG_GRSTCTL_AHBIDL                  USB_OTG_GRSTCTL_AHBIDL_Msk     /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM_Pos               (0U)                           
-#define USB_OTG_DIEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPMSK_XFRCM                   USB_OTG_DIEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM_Pos                (1U)                           
-#define USB_OTG_DIEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPMSK_EPDM                    USB_OTG_DIEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM_Pos                 (3U)                           
-#define USB_OTG_DIEPMSK_TOM_Msk                 (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPMSK_TOM                     USB_OTG_DIEPMSK_TOM_Msk        /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos           (4U)                           
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk           (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPMSK_ITTXFEMSK               USB_OTG_DIEPMSK_ITTXFEMSK_Msk  /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM_Pos             (5U)                           
-#define USB_OTG_DIEPMSK_INEPNMM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DIEPMSK_INEPNMM                 USB_OTG_DIEPMSK_INEPNMM_Msk    /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM_Pos             (6U)                           
-#define USB_OTG_DIEPMSK_INEPNEM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPMSK_INEPNEM                 USB_OTG_DIEPMSK_INEPNEM_Msk    /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM_Pos              (8U)                           
-#define USB_OTG_DIEPMSK_TXFURM_Msk              (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPMSK_TXFURM                  USB_OTG_DIEPMSK_TXFURM_Msk     /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM_Pos                 (9U)                           
-#define USB_OTG_DIEPMSK_BIM_Msk                 (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPMSK_BIM                     USB_OTG_DIEPMSK_BIM_Msk        /*!< BNA interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL_Pos            (0U)                           
-#define USB_OTG_HPTXSTS_PTXFSAVL_Msk            (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HPTXSTS_PTXFSAVL                USB_OTG_HPTXSTS_PTXFSAVL_Msk   /*!< Periodic transmit data FIFO space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_Pos             (16U)                          
-#define USB_OTG_HPTXSTS_PTXQSAV_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
-#define USB_OTG_HPTXSTS_PTXQSAV                 USB_OTG_HPTXSTS_PTXQSAV_Msk    /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0               (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1               (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2               (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3               (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4               (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5               (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6               (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7               (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP_Pos             (24U)                          
-#define USB_OTG_HPTXSTS_PTXQTOP_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP                 USB_OTG_HPTXSTS_PTXQTOP_Msk    /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0               (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1               (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2               (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3               (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4               (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5               (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6               (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7               (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT_Pos                 (0U)                           
-#define USB_OTG_HAINT_HAINT_Msk                 (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HAINT_HAINT                     USB_OTG_HAINT_HAINT_Msk        /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM_Pos               (0U)                           
-#define USB_OTG_DOEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPMSK_XFRCM                   USB_OTG_DOEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM_Pos                (1U)                           
-#define USB_OTG_DOEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPMSK_EPDM                    USB_OTG_DOEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
-#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
-#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
-#define USB_OTG_DOEPMSK_STUPM_Pos               (3U)                           
-#define USB_OTG_DOEPMSK_STUPM_Msk               (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPMSK_STUPM                   USB_OTG_DOEPMSK_STUPM_Msk      /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM_Pos              (4U)                           
-#define USB_OTG_DOEPMSK_OTEPDM_Msk              (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPMSK_OTEPDM                  USB_OTG_DOEPMSK_OTEPDM_Msk     /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          
-#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP_Pos             (6U)                           
-#define USB_OTG_DOEPMSK_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPMSK_B2BSTUP                 USB_OTG_DOEPMSK_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM_Pos                (8U)                           
-#define USB_OTG_DOEPMSK_OPEM_Msk                (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPMSK_OPEM                    USB_OTG_DOEPMSK_OPEM_Msk       /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM_Pos                (9U)                           
-#define USB_OTG_DOEPMSK_BOIM_Msk                (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DOEPMSK_BOIM                    USB_OTG_DOEPMSK_BOIM_Msk       /*!< BNA interrupt mask */
-#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
-#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
-#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
-#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
-#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
-#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
-#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD_Pos                (0U)                           
-#define USB_OTG_GINTSTS_CMOD_Msk                (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
-#define USB_OTG_GINTSTS_CMOD                    USB_OTG_GINTSTS_CMOD_Msk       /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS_Pos                (1U)                           
-#define USB_OTG_GINTSTS_MMIS_Msk                (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
-#define USB_OTG_GINTSTS_MMIS                    USB_OTG_GINTSTS_MMIS_Msk       /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT_Pos              (2U)                           
-#define USB_OTG_GINTSTS_OTGINT_Msk              (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
-#define USB_OTG_GINTSTS_OTGINT                  USB_OTG_GINTSTS_OTGINT_Msk     /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF_Pos                 (3U)                           
-#define USB_OTG_GINTSTS_SOF_Msk                 (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
-#define USB_OTG_GINTSTS_SOF                     USB_OTG_GINTSTS_SOF_Msk        /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL_Pos              (4U)                           
-#define USB_OTG_GINTSTS_RXFLVL_Msk              (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
-#define USB_OTG_GINTSTS_RXFLVL                  USB_OTG_GINTSTS_RXFLVL_Msk     /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE_Pos              (5U)                           
-#define USB_OTG_GINTSTS_NPTXFE_Msk              (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
-#define USB_OTG_GINTSTS_NPTXFE                  USB_OTG_GINTSTS_NPTXFE_Msk     /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF_Pos            (6U)                           
-#define USB_OTG_GINTSTS_GINAKEFF_Msk            (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
-#define USB_OTG_GINTSTS_GINAKEFF                USB_OTG_GINTSTS_GINAKEFF_Msk   /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos          (7U)                           
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk          (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
-#define USB_OTG_GINTSTS_BOUTNAKEFF              USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP_Pos               (10U)                          
-#define USB_OTG_GINTSTS_ESUSP_Msk               (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
-#define USB_OTG_GINTSTS_ESUSP                   USB_OTG_GINTSTS_ESUSP_Msk      /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP_Pos             (11U)                          
-#define USB_OTG_GINTSTS_USBSUSP_Msk             (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
-#define USB_OTG_GINTSTS_USBSUSP                 USB_OTG_GINTSTS_USBSUSP_Msk    /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST_Pos              (12U)                          
-#define USB_OTG_GINTSTS_USBRST_Msk              (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
-#define USB_OTG_GINTSTS_USBRST                  USB_OTG_GINTSTS_USBRST_Msk     /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE_Pos             (13U)                          
-#define USB_OTG_GINTSTS_ENUMDNE_Msk             (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
-#define USB_OTG_GINTSTS_ENUMDNE                 USB_OTG_GINTSTS_ENUMDNE_Msk    /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP_Pos             (14U)                          
-#define USB_OTG_GINTSTS_ISOODRP_Msk             (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
-#define USB_OTG_GINTSTS_ISOODRP                 USB_OTG_GINTSTS_ISOODRP_Msk    /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF_Pos                (15U)                          
-#define USB_OTG_GINTSTS_EOPF_Msk                (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
-#define USB_OTG_GINTSTS_EOPF                    USB_OTG_GINTSTS_EOPF_Msk       /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT_Pos              (18U)                          
-#define USB_OTG_GINTSTS_IEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
-#define USB_OTG_GINTSTS_IEPINT                  USB_OTG_GINTSTS_IEPINT_Msk     /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT_Pos              (19U)                          
-#define USB_OTG_GINTSTS_OEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
-#define USB_OTG_GINTSTS_OEPINT                  USB_OTG_GINTSTS_OEPINT_Msk     /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR_Pos            (20U)                          
-#define USB_OTG_GINTSTS_IISOIXFR_Msk            (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
-#define USB_OTG_GINTSTS_IISOIXFR                USB_OTG_GINTSTS_IISOIXFR_Msk   /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)                          
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP_Pos           (22U)                          
-#define USB_OTG_GINTSTS_DATAFSUSP_Msk           (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
-#define USB_OTG_GINTSTS_DATAFSUSP               USB_OTG_GINTSTS_DATAFSUSP_Msk  /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT_Pos             (24U)                          
-#define USB_OTG_GINTSTS_HPRTINT_Msk             (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
-#define USB_OTG_GINTSTS_HPRTINT                 USB_OTG_GINTSTS_HPRTINT_Msk    /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT_Pos               (25U)                          
-#define USB_OTG_GINTSTS_HCINT_Msk               (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
-#define USB_OTG_GINTSTS_HCINT                   USB_OTG_GINTSTS_HCINT_Msk      /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE_Pos               (26U)                          
-#define USB_OTG_GINTSTS_PTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
-#define USB_OTG_GINTSTS_PTXFE                   USB_OTG_GINTSTS_PTXFE_Msk      /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG_Pos             (28U)                          
-#define USB_OTG_GINTSTS_CIDSCHG_Msk             (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
-#define USB_OTG_GINTSTS_CIDSCHG                 USB_OTG_GINTSTS_CIDSCHG_Msk    /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT_Pos             (29U)                          
-#define USB_OTG_GINTSTS_DISCINT_Msk             (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
-#define USB_OTG_GINTSTS_DISCINT                 USB_OTG_GINTSTS_DISCINT_Msk    /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT_Pos              (30U)                          
-#define USB_OTG_GINTSTS_SRQINT_Msk              (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
-#define USB_OTG_GINTSTS_SRQINT                  USB_OTG_GINTSTS_SRQINT_Msk     /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT_Pos              (31U)                          
-#define USB_OTG_GINTSTS_WKUINT_Msk              (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GINTSTS_WKUINT                  USB_OTG_GINTSTS_WKUINT_Msk     /*!< Resume/remote wakeup detected interrupt */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM_Pos               (1U)                           
-#define USB_OTG_GINTMSK_MMISM_Msk               (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
-#define USB_OTG_GINTMSK_MMISM                   USB_OTG_GINTMSK_MMISM_Msk      /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT_Pos              (2U)                           
-#define USB_OTG_GINTMSK_OTGINT_Msk              (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
-#define USB_OTG_GINTMSK_OTGINT                  USB_OTG_GINTMSK_OTGINT_Msk     /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM_Pos                (3U)                           
-#define USB_OTG_GINTMSK_SOFM_Msk                (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
-#define USB_OTG_GINTMSK_SOFM                    USB_OTG_GINTMSK_SOFM_Msk       /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM_Pos             (4U)                           
-#define USB_OTG_GINTMSK_RXFLVLM_Msk             (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
-#define USB_OTG_GINTMSK_RXFLVLM                 USB_OTG_GINTMSK_RXFLVLM_Msk    /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM_Pos             (5U)                           
-#define USB_OTG_GINTMSK_NPTXFEM_Msk             (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
-#define USB_OTG_GINTMSK_NPTXFEM                 USB_OTG_GINTMSK_NPTXFEM_Msk    /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM_Pos           (6U)                           
-#define USB_OTG_GINTMSK_GINAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
-#define USB_OTG_GINTMSK_GINAKEFFM               USB_OTG_GINTMSK_GINAKEFFM_Msk  /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM_Pos           (7U)                           
-#define USB_OTG_GINTMSK_GONAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
-#define USB_OTG_GINTMSK_GONAKEFFM               USB_OTG_GINTMSK_GONAKEFFM_Msk  /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM_Pos              (10U)                          
-#define USB_OTG_GINTMSK_ESUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GINTMSK_ESUSPM                  USB_OTG_GINTMSK_ESUSPM_Msk     /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM_Pos            (11U)                          
-#define USB_OTG_GINTMSK_USBSUSPM_Msk            (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
-#define USB_OTG_GINTMSK_USBSUSPM                USB_OTG_GINTMSK_USBSUSPM_Msk   /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST_Pos              (12U)                          
-#define USB_OTG_GINTMSK_USBRST_Msk              (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
-#define USB_OTG_GINTMSK_USBRST                  USB_OTG_GINTMSK_USBRST_Msk     /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM_Pos            (13U)                          
-#define USB_OTG_GINTMSK_ENUMDNEM_Msk            (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
-#define USB_OTG_GINTMSK_ENUMDNEM                USB_OTG_GINTMSK_ENUMDNEM_Msk   /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM_Pos            (14U)                          
-#define USB_OTG_GINTMSK_ISOODRPM_Msk            (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
-#define USB_OTG_GINTMSK_ISOODRPM                USB_OTG_GINTMSK_ISOODRPM_Msk   /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM_Pos               (15U)                          
-#define USB_OTG_GINTMSK_EOPFM_Msk               (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
-#define USB_OTG_GINTMSK_EOPFM                   USB_OTG_GINTMSK_EOPFM_Msk      /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM_Pos              (17U)                          
-#define USB_OTG_GINTMSK_EPMISM_Msk              (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
-#define USB_OTG_GINTMSK_EPMISM                  USB_OTG_GINTMSK_EPMISM_Msk     /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT_Pos              (18U)                          
-#define USB_OTG_GINTMSK_IEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
-#define USB_OTG_GINTMSK_IEPINT                  USB_OTG_GINTMSK_IEPINT_Msk     /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT_Pos              (19U)                          
-#define USB_OTG_GINTMSK_OEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
-#define USB_OTG_GINTMSK_OEPINT                  USB_OTG_GINTMSK_OEPINT_Msk     /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM_Pos           (20U)                          
-#define USB_OTG_GINTMSK_IISOIXFRM_Msk           (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
-#define USB_OTG_GINTMSK_IISOIXFRM               USB_OTG_GINTMSK_IISOIXFRM_Msk  /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos     (21U)                          
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk     (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM_Pos              (22U)                          
-#define USB_OTG_GINTMSK_FSUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
-#define USB_OTG_GINTMSK_FSUSPM                  USB_OTG_GINTMSK_FSUSPM_Msk     /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM_Pos               (24U)                          
-#define USB_OTG_GINTMSK_PRTIM_Msk               (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
-#define USB_OTG_GINTMSK_PRTIM                   USB_OTG_GINTMSK_PRTIM_Msk      /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM_Pos                (25U)                          
-#define USB_OTG_GINTMSK_HCIM_Msk                (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
-#define USB_OTG_GINTMSK_HCIM                    USB_OTG_GINTMSK_HCIM_Msk       /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM_Pos              (26U)                          
-#define USB_OTG_GINTMSK_PTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
-#define USB_OTG_GINTMSK_PTXFEM                  USB_OTG_GINTMSK_PTXFEM_Msk     /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM_Pos            (28U)                          
-#define USB_OTG_GINTMSK_CIDSCHGM_Msk            (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
-#define USB_OTG_GINTMSK_CIDSCHGM                USB_OTG_GINTMSK_CIDSCHGM_Msk   /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT_Pos             (29U)                          
-#define USB_OTG_GINTMSK_DISCINT_Msk             (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
-#define USB_OTG_GINTMSK_DISCINT                 USB_OTG_GINTMSK_DISCINT_Msk    /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM_Pos               (30U)                          
-#define USB_OTG_GINTMSK_SRQIM_Msk               (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
-#define USB_OTG_GINTMSK_SRQIM                   USB_OTG_GINTMSK_SRQIM_Msk      /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM_Pos                (31U)                          
-#define USB_OTG_GINTMSK_WUIM_Msk                (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
-#define USB_OTG_GINTMSK_WUIM                    USB_OTG_GINTMSK_WUIM_Msk       /*!< Resume/remote wakeup detected interrupt mask */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT_Pos                (0U)                           
-#define USB_OTG_DAINT_IEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DAINT_IEPINT                    USB_OTG_DAINT_IEPINT_Msk       /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT_Pos                (16U)                          
-#define USB_OTG_DAINT_OEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DAINT_OEPINT                    USB_OTG_DAINT_OEPINT_Msk       /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM_Pos             (0U)                           
-#define USB_OTG_HAINTMSK_HAINTM_Msk             (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HAINTMSK_HAINTM                 USB_OTG_HAINTMSK_HAINTM_Msk    /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM_Pos               (0U)                           
-#define USB_OTG_GRXSTSP_EPNUM_Msk               (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
-#define USB_OTG_GRXSTSP_EPNUM                   USB_OTG_GRXSTSP_EPNUM_Msk      /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT_Pos                (4U)                           
-#define USB_OTG_GRXSTSP_BCNT_Msk                (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
-#define USB_OTG_GRXSTSP_BCNT                    USB_OTG_GRXSTSP_BCNT_Msk       /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID_Pos                (15U)                          
-#define USB_OTG_GRXSTSP_DPID_Msk                (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
-#define USB_OTG_GRXSTSP_DPID                    USB_OTG_GRXSTSP_DPID_Msk       /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS_Pos              (17U)                          
-#define USB_OTG_GRXSTSP_PKTSTS_Msk              (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
-#define USB_OTG_GRXSTSP_PKTSTS                  USB_OTG_GRXSTSP_PKTSTS_Msk     /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM_Pos               (0U)                           
-#define USB_OTG_DAINTMSK_IEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DAINTMSK_IEPM                   USB_OTG_DAINTMSK_IEPM_Msk      /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM_Pos               (16U)                          
-#define USB_OTG_DAINTMSK_OEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DAINTMSK_OEPM                   USB_OTG_DAINTMSK_OEPM_Msk      /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD_Pos                (0U)                           
-#define USB_OTG_GRXFSIZ_RXFD_Msk                (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_GRXFSIZ_RXFD                    USB_OTG_GRXFSIZ_RXFD_Msk       /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT_Pos             (0U)                           
-#define USB_OTG_DVBUSDIS_VBUSDT_Msk             (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DVBUSDIS_VBUSDT                 USB_OTG_DVBUSDIS_VBUSDT_Msk    /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA_Pos                     (0U)                           
-#define USB_OTG_NPTXFSA_Msk                     (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_NPTXFSA                         USB_OTG_NPTXFSA_Msk            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD_Pos                      (16U)                          
-#define USB_OTG_NPTXFD_Msk                      (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_NPTXFD                          USB_OTG_NPTXFD_Msk             /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA_Pos                      (0U)                           
-#define USB_OTG_TX0FSA_Msk                      (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_TX0FSA                          USB_OTG_TX0FSA_Msk             /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD_Pos                       (16U)                          
-#define USB_OTG_TX0FD_Msk                       (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_TX0FD                           USB_OTG_TX0FD_Msk              /*!< Endpoint 0 TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP_Pos           (0U)                           
-#define USB_OTG_DVBUSPULSE_DVBUSP_Msk           (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
-#define USB_OTG_DVBUSPULSE_DVBUSP               USB_OTG_DVBUSPULSE_DVBUSP_Msk  /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos           (0U)                           
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk           (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_GNPTXSTS_NPTXFSAV               USB_OTG_GNPTXSTS_NPTXFSAV_Msk  /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos           (16U)                          
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk           (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV               USB_OTG_GNPTXSTS_NPTQXSAV_Msk  /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0             (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1             (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2             (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3             (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4             (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5             (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6             (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7             (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos           (24U)                          
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk           (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP               USB_OTG_GNPTXSTS_NPTXQTOP_Msk  /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0             (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1             (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2             (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3             (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4             (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5             (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6             (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN_Pos         (0U)                           
-#define USB_OTG_DTHRCTL_NONISOTHREN_Msk         (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
-#define USB_OTG_DTHRCTL_NONISOTHREN             USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN_Pos            (1U)                           
-#define USB_OTG_DTHRCTL_ISOTHREN_Msk            (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
-#define USB_OTG_DTHRCTL_ISOTHREN                USB_OTG_DTHRCTL_ISOTHREN_Msk   /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN_Pos            (2U)                           
-#define USB_OTG_DTHRCTL_TXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
-#define USB_OTG_DTHRCTL_TXTHRLEN                USB_OTG_DTHRCTL_TXTHRLEN_Msk   /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_DTHRCTL_RXTHREN_Pos             (16U)                          
-#define USB_OTG_DTHRCTL_RXTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
-#define USB_OTG_DTHRCTL_RXTHREN                 USB_OTG_DTHRCTL_RXTHREN_Msk    /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN_Pos            (17U)                          
-#define USB_OTG_DTHRCTL_RXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN                USB_OTG_DTHRCTL_RXTHRLEN_Msk   /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1              (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2              (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3              (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4              (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5              (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
-#define USB_OTG_DTHRCTL_ARPEN_Pos               (27U)                          
-#define USB_OTG_DTHRCTL_ARPEN_Msk               (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
-#define USB_OTG_DTHRCTL_ARPEN                   USB_OTG_DTHRCTL_ARPEN_Msk      /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos        (0U)                           
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk        (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM            USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT_Pos            (1U)                           
-#define USB_OTG_DEACHINT_IEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
-#define USB_OTG_DEACHINT_IEP1INT                USB_OTG_DEACHINT_IEP1INT_Msk   /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT_Pos            (17U)                          
-#define USB_OTG_DEACHINT_OEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
-#define USB_OTG_DEACHINT_OEP1INT                USB_OTG_DEACHINT_OEP1INT_Msk   /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN_Pos                (16U)                          
-#define USB_OTG_GCCFG_PWRDWN_Msk                (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
-#define USB_OTG_GCCFG_PWRDWN                    USB_OTG_GCCFG_PWRDWN_Msk       /*!< Power down */
-#define USB_OTG_GCCFG_VBUSASEN_Pos              (18U)                          
-#define USB_OTG_GCCFG_VBUSASEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
-#define USB_OTG_GCCFG_VBUSASEN                  USB_OTG_GCCFG_VBUSASEN_Msk     /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN_Pos              (19U)                          
-#define USB_OTG_GCCFG_VBUSBSEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
-#define USB_OTG_GCCFG_VBUSBSEN                  USB_OTG_GCCFG_VBUSBSEN_Msk     /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN_Pos              (20U)                          
-#define USB_OTG_GCCFG_SOFOUTEN_Msk              (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
-#define USB_OTG_GCCFG_SOFOUTEN                  USB_OTG_GCCFG_SOFOUTEN_Msk     /*!< SOF output enable */
-
-/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos        (1U)                           
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DEACHINTMSK_IEP1INTM            USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos        (17U)                          
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
-#define USB_OTG_DEACHINTMSK_OEP1INTM            USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID_Pos              (0U)                           
-#define USB_OTG_CID_PRODUCT_ID_Msk              (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_CID_PRODUCT_ID                  USB_OTG_CID_PRODUCT_ID_Msk     /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos          (0U)                           
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPEACHMSK1_XFRCM              USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM_Pos           (1U)                           
-#define USB_OTG_DIEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPEACHMSK1_EPDM               USB_OTG_DIEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM_Pos            (3U)                           
-#define USB_OTG_DIEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPEACHMSK1_TOM                USB_OTG_DIEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK          USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos        (5U)                           
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM            USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos        (6U)                           
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM            USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos         (8U)                           
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPEACHMSK1_TXFURM             USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM_Pos            (9U)                           
-#define USB_OTG_DIEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPEACHMSK1_BIM                USB_OTG_DIEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM_Pos           (13U)                          
-#define USB_OTG_DIEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DIEPEACHMSK1_NAKM               USB_OTG_DIEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS_Pos                  (0U)                           
-#define USB_OTG_HPRT_PCSTS_Msk                  (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
-#define USB_OTG_HPRT_PCSTS                      USB_OTG_HPRT_PCSTS_Msk         /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET_Pos                  (1U)                           
-#define USB_OTG_HPRT_PCDET_Msk                  (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
-#define USB_OTG_HPRT_PCDET                      USB_OTG_HPRT_PCDET_Msk         /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA_Pos                   (2U)                           
-#define USB_OTG_HPRT_PENA_Msk                   (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
-#define USB_OTG_HPRT_PENA                       USB_OTG_HPRT_PENA_Msk          /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG_Pos                (3U)                           
-#define USB_OTG_HPRT_PENCHNG_Msk                (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
-#define USB_OTG_HPRT_PENCHNG                    USB_OTG_HPRT_PENCHNG_Msk       /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA_Pos                   (4U)                           
-#define USB_OTG_HPRT_POCA_Msk                   (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
-#define USB_OTG_HPRT_POCA                       USB_OTG_HPRT_POCA_Msk          /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG_Pos                (5U)                           
-#define USB_OTG_HPRT_POCCHNG_Msk                (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
-#define USB_OTG_HPRT_POCCHNG                    USB_OTG_HPRT_POCCHNG_Msk       /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES_Pos                   (6U)                           
-#define USB_OTG_HPRT_PRES_Msk                   (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
-#define USB_OTG_HPRT_PRES                       USB_OTG_HPRT_PRES_Msk          /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP_Pos                  (7U)                           
-#define USB_OTG_HPRT_PSUSP_Msk                  (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
-#define USB_OTG_HPRT_PSUSP                      USB_OTG_HPRT_PSUSP_Msk         /*!< Port suspend */
-#define USB_OTG_HPRT_PRST_Pos                   (8U)                           
-#define USB_OTG_HPRT_PRST_Msk                   (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
-#define USB_OTG_HPRT_PRST                       USB_OTG_HPRT_PRST_Msk          /*!< Port reset */
-
-#define USB_OTG_HPRT_PLSTS_Pos                  (10U)                          
-#define USB_OTG_HPRT_PLSTS_Msk                  (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
-#define USB_OTG_HPRT_PLSTS                      USB_OTG_HPRT_PLSTS_Msk         /*!< Port line status */
-#define USB_OTG_HPRT_PLSTS_0                    (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
-#define USB_OTG_HPRT_PLSTS_1                    (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_HPRT_PPWR_Pos                   (12U)                          
-#define USB_OTG_HPRT_PPWR_Msk                   (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
-#define USB_OTG_HPRT_PPWR                       USB_OTG_HPRT_PPWR_Msk          /*!< Port power */
-
-#define USB_OTG_HPRT_PTCTL_Pos                  (13U)                          
-#define USB_OTG_HPRT_PTCTL_Msk                  (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
-#define USB_OTG_HPRT_PTCTL                      USB_OTG_HPRT_PTCTL_Msk         /*!< Port test control */
-#define USB_OTG_HPRT_PTCTL_0                    (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
-#define USB_OTG_HPRT_PTCTL_1                    (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
-#define USB_OTG_HPRT_PTCTL_2                    (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
-#define USB_OTG_HPRT_PTCTL_3                    (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
-
-#define USB_OTG_HPRT_PSPD_Pos                   (17U)                          
-#define USB_OTG_HPRT_PSPD_Msk                   (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
-#define USB_OTG_HPRT_PSPD                       USB_OTG_HPRT_PSPD_Msk          /*!< Port speed */
-#define USB_OTG_HPRT_PSPD_0                     (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
-#define USB_OTG_HPRT_PSPD_1                     (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos          (0U)                           
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPEACHMSK1_XFRCM              USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM_Pos           (1U)                           
-#define USB_OTG_DOEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPEACHMSK1_EPDM               USB_OTG_DOEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM_Pos            (3U)                           
-#define USB_OTG_DOEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPEACHMSK1_TOM                USB_OTG_DOEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK          USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos        (5U)                           
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM            USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos        (6U)                           
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM            USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos         (8U)                           
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPEACHMSK1_TXFURM             USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM_Pos            (9U)                           
-#define USB_OTG_DOEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DOEPEACHMSK1_BIM                USB_OTG_DOEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM_Pos          (12U)                          
-#define USB_OTG_DOEPEACHMSK1_BERRM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
-#define USB_OTG_DOEPEACHMSK1_BERRM              USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM_Pos           (13U)                          
-#define USB_OTG_DOEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPEACHMSK1_NAKM               USB_OTG_DOEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM_Pos          (14U)                          
-#define USB_OTG_DOEPEACHMSK1_NYETM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPEACHMSK1_NYETM              USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA_Pos              (0U)                           
-#define USB_OTG_HPTXFSIZ_PTXSA_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HPTXFSIZ_PTXSA                  USB_OTG_HPTXFSIZ_PTXSA_Msk     /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD_Pos              (16U)                          
-#define USB_OTG_HPTXFSIZ_PTXFD_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_HPTXFSIZ_PTXFD                  USB_OTG_HPTXFSIZ_PTXFD_Msk     /*!< Host periodic TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ_Pos               (0U)                           
-#define USB_OTG_DIEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_DIEPCTL_MPSIZ                   USB_OTG_DIEPCTL_MPSIZ_Msk      /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP_Pos              (15U)                          
-#define USB_OTG_DIEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define USB_OTG_DIEPCTL_USBAEP                  USB_OTG_DIEPCTL_USBAEP_Msk     /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID_Pos          (16U)                          
-#define USB_OTG_DIEPCTL_EONUM_DPID_Msk          (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
-#define USB_OTG_DIEPCTL_EONUM_DPID              USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS_Pos              (17U)                          
-#define USB_OTG_DIEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define USB_OTG_DIEPCTL_NAKSTS                  USB_OTG_DIEPCTL_NAKSTS_Msk     /*!< NAK status */
-
-#define USB_OTG_DIEPCTL_EPTYP_Pos               (18U)                          
-#define USB_OTG_DIEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_DIEPCTL_EPTYP                   USB_OTG_DIEPCTL_EPTYP_Msk      /*!< Endpoint type */
-#define USB_OTG_DIEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_DIEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DIEPCTL_STALL_Pos               (21U)                          
-#define USB_OTG_DIEPCTL_STALL_Msk               (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define USB_OTG_DIEPCTL_STALL                   USB_OTG_DIEPCTL_STALL_Msk      /*!< STALL handshake */
-
-#define USB_OTG_DIEPCTL_TXFNUM_Pos              (22U)                          
-#define USB_OTG_DIEPCTL_TXFNUM_Msk              (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
-#define USB_OTG_DIEPCTL_TXFNUM                  USB_OTG_DIEPCTL_TXFNUM_Msk     /*!< TxFIFO number */
-#define USB_OTG_DIEPCTL_TXFNUM_0                (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
-#define USB_OTG_DIEPCTL_CNAK_Pos                (26U)                          
-#define USB_OTG_DIEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define USB_OTG_DIEPCTL_CNAK                    USB_OTG_DIEPCTL_CNAK_Msk       /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK_Pos                (27U)                          
-#define USB_OTG_DIEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define USB_OTG_DIEPCTL_SNAK                    USB_OTG_DIEPCTL_SNAK_Msk       /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM_Pos             (29U)                          
-#define USB_OTG_DIEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_DIEPCTL_SODDFRM                 USB_OTG_DIEPCTL_SODDFRM_Msk    /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS_Pos               (30U)                          
-#define USB_OTG_DIEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_DIEPCTL_EPDIS                   USB_OTG_DIEPCTL_EPDIS_Msk      /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA_Pos               (31U)                          
-#define USB_OTG_DIEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_DIEPCTL_EPENA                   USB_OTG_DIEPCTL_EPENA_Msk      /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ_Pos                (0U)                           
-#define USB_OTG_HCCHAR_MPSIZ_Msk                (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_HCCHAR_MPSIZ                    USB_OTG_HCCHAR_MPSIZ_Msk       /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM_Pos                (11U)                          
-#define USB_OTG_HCCHAR_EPNUM_Msk                (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
-#define USB_OTG_HCCHAR_EPNUM                    USB_OTG_HCCHAR_EPNUM_Msk       /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                  (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
-#define USB_OTG_HCCHAR_EPNUM_1                  (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
-#define USB_OTG_HCCHAR_EPNUM_2                  (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
-#define USB_OTG_HCCHAR_EPNUM_3                  (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCCHAR_EPDIR_Pos                (15U)                          
-#define USB_OTG_HCCHAR_EPDIR_Msk                (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCCHAR_EPDIR                    USB_OTG_HCCHAR_EPDIR_Msk       /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV_Pos                (17U)                          
-#define USB_OTG_HCCHAR_LSDEV_Msk                (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
-#define USB_OTG_HCCHAR_LSDEV                    USB_OTG_HCCHAR_LSDEV_Msk       /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP_Pos                (18U)                          
-#define USB_OTG_HCCHAR_EPTYP_Msk                (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_HCCHAR_EPTYP                    USB_OTG_HCCHAR_EPTYP_Msk       /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                  (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_HCCHAR_EPTYP_1                  (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
-                                      
-#define USB_OTG_HCCHAR_MC_Pos                   (20U)                          
-#define USB_OTG_HCCHAR_MC_Msk                   (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
-#define USB_OTG_HCCHAR_MC                       USB_OTG_HCCHAR_MC_Msk          /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                     (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
-#define USB_OTG_HCCHAR_MC_1                     (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
-
-#define USB_OTG_HCCHAR_DAD_Pos                  (22U)                          
-#define USB_OTG_HCCHAR_DAD_Msk                  (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
-#define USB_OTG_HCCHAR_DAD                      USB_OTG_HCCHAR_DAD_Msk         /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                    (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
-#define USB_OTG_HCCHAR_DAD_1                    (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
-#define USB_OTG_HCCHAR_DAD_2                    (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
-#define USB_OTG_HCCHAR_DAD_3                    (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
-#define USB_OTG_HCCHAR_DAD_4                    (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
-#define USB_OTG_HCCHAR_DAD_5                    (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
-#define USB_OTG_HCCHAR_DAD_6                    (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
-#define USB_OTG_HCCHAR_ODDFRM_Pos               (29U)                          
-#define USB_OTG_HCCHAR_ODDFRM_Msk               (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_HCCHAR_ODDFRM                   USB_OTG_HCCHAR_ODDFRM_Msk      /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS_Pos                (30U)                          
-#define USB_OTG_HCCHAR_CHDIS_Msk                (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_HCCHAR_CHDIS                    USB_OTG_HCCHAR_CHDIS_Msk       /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA_Pos                (31U)                          
-#define USB_OTG_HCCHAR_CHENA_Msk                (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCCHAR_CHENA                    USB_OTG_HCCHAR_CHENA_Msk       /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR_Pos              (0U)                           
-#define USB_OTG_HCSPLT_PRTADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
-#define USB_OTG_HCSPLT_PRTADDR                  USB_OTG_HCSPLT_PRTADDR_Msk     /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0                (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCSPLT_PRTADDR_1                (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCSPLT_PRTADDR_2                (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCSPLT_PRTADDR_3                (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCSPLT_PRTADDR_4                (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCSPLT_PRTADDR_5                (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCSPLT_PRTADDR_6                (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
-
-#define USB_OTG_HCSPLT_HUBADDR_Pos              (7U)                           
-#define USB_OTG_HCSPLT_HUBADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
-#define USB_OTG_HCSPLT_HUBADDR                  USB_OTG_HCSPLT_HUBADDR_Msk     /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0                (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCSPLT_HUBADDR_1                (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCSPLT_HUBADDR_2                (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCSPLT_HUBADDR_3                (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCSPLT_HUBADDR_4                (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
-#define USB_OTG_HCSPLT_HUBADDR_5                (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
-#define USB_OTG_HCSPLT_HUBADDR_6                (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
-
-#define USB_OTG_HCSPLT_XACTPOS_Pos              (14U)                          
-#define USB_OTG_HCSPLT_XACTPOS_Msk              (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
-#define USB_OTG_HCSPLT_XACTPOS                  USB_OTG_HCSPLT_XACTPOS_Msk     /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0                (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCSPLT_XACTPOS_1                (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCSPLT_COMPLSPLT_Pos            (16U)                          
-#define USB_OTG_HCSPLT_COMPLSPLT_Msk            (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
-#define USB_OTG_HCSPLT_COMPLSPLT                USB_OTG_HCSPLT_COMPLSPLT_Msk   /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN_Pos              (31U)                          
-#define USB_OTG_HCSPLT_SPLITEN_Msk              (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCSPLT_SPLITEN                  USB_OTG_HCSPLT_SPLITEN_Msk     /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC_Pos                  (0U)                           
-#define USB_OTG_HCINT_XFRC_Msk                  (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCINT_XFRC                      USB_OTG_HCINT_XFRC_Msk         /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH_Pos                   (1U)                           
-#define USB_OTG_HCINT_CHH_Msk                   (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCINT_CHH                       USB_OTG_HCINT_CHH_Msk          /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR_Pos                (2U)                           
-#define USB_OTG_HCINT_AHBERR_Msk                (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCINT_AHBERR                    USB_OTG_HCINT_AHBERR_Msk       /*!< AHB error */
-#define USB_OTG_HCINT_STALL_Pos                 (3U)                           
-#define USB_OTG_HCINT_STALL_Msk                 (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCINT_STALL                     USB_OTG_HCINT_STALL_Msk        /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK_Pos                   (4U)                           
-#define USB_OTG_HCINT_NAK_Msk                   (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCINT_NAK                       USB_OTG_HCINT_NAK_Msk          /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK_Pos                   (5U)                           
-#define USB_OTG_HCINT_ACK_Msk                   (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCINT_ACK                       USB_OTG_HCINT_ACK_Msk          /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET_Pos                  (6U)                           
-#define USB_OTG_HCINT_NYET_Msk                  (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
-#define USB_OTG_HCINT_NYET                      USB_OTG_HCINT_NYET_Msk         /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR_Pos                 (7U)                           
-#define USB_OTG_HCINT_TXERR_Msk                 (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCINT_TXERR                     USB_OTG_HCINT_TXERR_Msk        /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR_Pos                 (8U)                           
-#define USB_OTG_HCINT_BBERR_Msk                 (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCINT_BBERR                     USB_OTG_HCINT_BBERR_Msk        /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR_Pos                 (9U)                           
-#define USB_OTG_HCINT_FRMOR_Msk                 (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCINT_FRMOR                     USB_OTG_HCINT_FRMOR_Msk        /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR_Pos                 (10U)                          
-#define USB_OTG_HCINT_DTERR_Msk                 (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCINT_DTERR                     USB_OTG_HCINT_DTERR_Msk        /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC_Pos                (0U)                           
-#define USB_OTG_DIEPINT_XFRC_Msk                (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPINT_XFRC                    USB_OTG_DIEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD_Pos              (1U)                           
-#define USB_OTG_DIEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPINT_EPDISD                  USB_OTG_DIEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
-#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
-#define USB_OTG_DIEPINT_TOC_Pos                 (3U)                           
-#define USB_OTG_DIEPINT_TOC_Msk                 (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPINT_TOC                     USB_OTG_DIEPINT_TOC_Msk        /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE_Pos              (4U)                           
-#define USB_OTG_DIEPINT_ITTXFE_Msk              (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPINT_ITTXFE                  USB_OTG_DIEPINT_ITTXFE_Msk     /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
-#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
-#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
-#define USB_OTG_DIEPINT_INEPNE_Pos              (6U)                           
-#define USB_OTG_DIEPINT_INEPNE_Msk              (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPINT_INEPNE                  USB_OTG_DIEPINT_INEPNE_Msk     /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE_Pos                (7U)                           
-#define USB_OTG_DIEPINT_TXFE_Msk                (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
-#define USB_OTG_DIEPINT_TXFE                    USB_OTG_DIEPINT_TXFE_Msk       /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos          (8U)                           
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk          (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPINT_TXFIFOUDRN              USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA_Pos                 (9U)                           
-#define USB_OTG_DIEPINT_BNA_Msk                 (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPINT_BNA                     USB_OTG_DIEPINT_BNA_Msk        /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS_Pos           (11U)                          
-#define USB_OTG_DIEPINT_PKTDRPSTS_Msk           (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_DIEPINT_PKTDRPSTS               USB_OTG_DIEPINT_PKTDRPSTS_Msk  /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR_Pos                (12U)                          
-#define USB_OTG_DIEPINT_BERR_Msk                (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
-#define USB_OTG_DIEPINT_BERR                    USB_OTG_DIEPINT_BERR_Msk       /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK_Pos                 (13U)                          
-#define USB_OTG_DIEPINT_NAK_Msk                 (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
-#define USB_OTG_DIEPINT_NAK                     USB_OTG_DIEPINT_NAK_Msk        /*!< NAK interrupt */
-
-/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM_Pos              (0U)                           
-#define USB_OTG_HCINTMSK_XFRCM_Msk              (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCINTMSK_XFRCM                  USB_OTG_HCINTMSK_XFRCM_Msk     /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM_Pos               (1U)                           
-#define USB_OTG_HCINTMSK_CHHM_Msk               (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCINTMSK_CHHM                   USB_OTG_HCINTMSK_CHHM_Msk      /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR_Pos             (2U)                           
-#define USB_OTG_HCINTMSK_AHBERR_Msk             (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCINTMSK_AHBERR                 USB_OTG_HCINTMSK_AHBERR_Msk    /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM_Pos             (3U)                           
-#define USB_OTG_HCINTMSK_STALLM_Msk             (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCINTMSK_STALLM                 USB_OTG_HCINTMSK_STALLM_Msk    /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM_Pos               (4U)                           
-#define USB_OTG_HCINTMSK_NAKM_Msk               (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCINTMSK_NAKM                   USB_OTG_HCINTMSK_NAKM_Msk      /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM_Pos               (5U)                           
-#define USB_OTG_HCINTMSK_ACKM_Msk               (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCINTMSK_ACKM                   USB_OTG_HCINTMSK_ACKM_Msk      /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET_Pos               (6U)                           
-#define USB_OTG_HCINTMSK_NYET_Msk               (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
-#define USB_OTG_HCINTMSK_NYET                   USB_OTG_HCINTMSK_NYET_Msk      /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM_Pos             (7U)                           
-#define USB_OTG_HCINTMSK_TXERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCINTMSK_TXERRM                 USB_OTG_HCINTMSK_TXERRM_Msk    /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM_Pos             (8U)                           
-#define USB_OTG_HCINTMSK_BBERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCINTMSK_BBERRM                 USB_OTG_HCINTMSK_BBERRM_Msk    /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM_Pos             (9U)                           
-#define USB_OTG_HCINTMSK_FRMORM_Msk             (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCINTMSK_FRMORM                 USB_OTG_HCINTMSK_FRMORM_Msk    /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM_Pos             (10U)                          
-#define USB_OTG_HCINTMSK_DTERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCINTMSK_DTERRM                 USB_OTG_HCINTMSK_DTERRM_Msk    /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos             (0U)                           
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_DIEPTSIZ_XFRSIZ                 USB_OTG_DIEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT_Pos             (19U)                          
-#define USB_OTG_DIEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_DIEPTSIZ_PKTCNT                 USB_OTG_DIEPTSIZ_PKTCNT_Msk    /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT_Pos             (29U)                          
-#define USB_OTG_DIEPTSIZ_MULCNT_Msk             (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
-#define USB_OTG_DIEPTSIZ_MULCNT                 USB_OTG_DIEPTSIZ_MULCNT_Msk    /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ_Pos               (0U)                           
-#define USB_OTG_HCTSIZ_XFRSIZ_Msk               (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_HCTSIZ_XFRSIZ                   USB_OTG_HCTSIZ_XFRSIZ_Msk      /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT_Pos               (19U)                          
-#define USB_OTG_HCTSIZ_PKTCNT_Msk               (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_HCTSIZ_PKTCNT                   USB_OTG_HCTSIZ_PKTCNT_Msk      /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING_Pos               (31U)                          
-#define USB_OTG_HCTSIZ_DOPING_Msk               (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCTSIZ_DOPING                   USB_OTG_HCTSIZ_DOPING_Msk      /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID_Pos                 (29U)                          
-#define USB_OTG_HCTSIZ_DPID_Msk                 (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
-#define USB_OTG_HCTSIZ_DPID                     USB_OTG_HCTSIZ_DPID_Msk        /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
-#define USB_OTG_HCTSIZ_DPID_1                   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR_Pos             (0U)                           
-#define USB_OTG_DIEPDMA_DMAADDR_Msk             (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_DIEPDMA_DMAADDR                 USB_OTG_DIEPDMA_DMAADDR_Msk    /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR_Pos               (0U)                           
-#define USB_OTG_HCDMA_DMAADDR_Msk               (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_HCDMA_DMAADDR                   USB_OTG_HCDMA_DMAADDR_Msk      /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV_Pos           (0U)                           
-#define USB_OTG_DTXFSTS_INEPTFSAV_Msk           (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA_Pos            (0U)                           
-#define USB_OTG_DIEPTXF_INEPTXSA_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DIEPTXF_INEPTXSA                USB_OTG_DIEPTXF_INEPTXSA_Msk   /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD_Pos            (16U)                          
-#define USB_OTG_DIEPTXF_INEPTXFD_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DIEPTXF_INEPTXFD                USB_OTG_DIEPTXF_INEPTXFD_Msk   /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ_Pos               (0U)                           
-#define USB_OTG_DOEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP_Pos              (15U)                          
-#define USB_OTG_DOEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define USB_OTG_DOEPCTL_USBAEP                  USB_OTG_DOEPCTL_USBAEP_Msk     /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS_Pos              (17U)                          
-#define USB_OTG_DOEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define USB_OTG_DOEPCTL_NAKSTS                  USB_OTG_DOEPCTL_NAKSTS_Msk     /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM          USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM_Pos             (29U)                          
-#define USB_OTG_DOEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_DOEPCTL_SODDFRM                 USB_OTG_DOEPCTL_SODDFRM_Msk    /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP_Pos               (18U)                          
-#define USB_OTG_DOEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_DOEPCTL_EPTYP                   USB_OTG_DOEPCTL_EPTYP_Msk      /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_DOEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DOEPCTL_SNPM_Pos                (20U)                          
-#define USB_OTG_DOEPCTL_SNPM_Msk                (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
-#define USB_OTG_DOEPCTL_SNPM                    USB_OTG_DOEPCTL_SNPM_Msk       /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL_Pos               (21U)                          
-#define USB_OTG_DOEPCTL_STALL_Msk               (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define USB_OTG_DOEPCTL_STALL                   USB_OTG_DOEPCTL_STALL_Msk      /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK_Pos                (26U)                          
-#define USB_OTG_DOEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define USB_OTG_DOEPCTL_CNAK                    USB_OTG_DOEPCTL_CNAK_Msk       /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK_Pos                (27U)                          
-#define USB_OTG_DOEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define USB_OTG_DOEPCTL_SNAK                    USB_OTG_DOEPCTL_SNAK_Msk       /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS_Pos               (30U)                          
-#define USB_OTG_DOEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_DOEPCTL_EPDIS                   USB_OTG_DOEPCTL_EPDIS_Msk      /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA_Pos               (31U)                          
-#define USB_OTG_DOEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_DOEPCTL_EPENA                   USB_OTG_DOEPCTL_EPENA_Msk      /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC_Pos                (0U)                           
-#define USB_OTG_DOEPINT_XFRC_Msk                (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPINT_XFRC                    USB_OTG_DOEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD_Pos              (1U)                           
-#define USB_OTG_DOEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPINT_EPDISD                  USB_OTG_DOEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
-#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
-#define USB_OTG_DOEPINT_STUP_Pos                (3U)                           
-#define USB_OTG_DOEPINT_STUP_Msk                (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPINT_STUP                    USB_OTG_DOEPINT_STUP_Msk       /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS_Pos             (4U)                           
-#define USB_OTG_DOEPINT_OTEPDIS_Msk             (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPINT_OTEPDIS                 USB_OTG_DOEPINT_OTEPDIS_Msk    /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          
-#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP_Pos             (6U)                           
-#define USB_OTG_DOEPINT_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPINT_B2BSTUP                 USB_OTG_DOEPINT_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
-#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
-#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
-#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
-#define USB_OTG_DOEPINT_NYET_Pos                (14U)                          
-#define USB_OTG_DOEPINT_NYET_Msk                (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPINT_NYET                    USB_OTG_DOEPINT_NYET_Msk       /*!< NYET interrupt */
-#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
-#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
-#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos             (0U)                           
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_DOEPTSIZ_XFRSIZ                 USB_OTG_DOEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT_Pos             (19U)                          
-#define USB_OTG_DOEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_DOEPTSIZ_PKTCNT                 USB_OTG_DOEPTSIZ_PKTCNT_Msk    /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT_Pos            (29U)                          
-#define USB_OTG_DOEPTSIZ_STUPCNT_Msk            (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
-#define USB_OTG_DOEPTSIZ_STUPCNT                USB_OTG_DOEPTSIZ_STUPCNT_Msk   /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0              (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1              (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK_Pos             (0U)                           
-#define USB_OTG_PCGCCTL_STOPCLK_Msk             (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
-#define USB_OTG_PCGCCTL_STOPCLK                 USB_OTG_PCGCCTL_STOPCLK_Msk    /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK_Pos             (1U)                           
-#define USB_OTG_PCGCCTL_GATECLK_Msk             (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
-#define USB_OTG_PCGCCTL_GATECLK                 USB_OTG_PCGCCTL_GATECLK_Msk    /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP_Pos             (4U)                           
-#define USB_OTG_PCGCCTL_PHYSUSP_Msk             (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
-#define USB_OTG_PCGCCTL_PHYSUSP                 USB_OTG_PCGCCTL_PHYSUSP_Msk    /*!<Bit 1 */
-
-/* Legacy define */
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_CHNUM_Pos                       (0U)                           
-#define USB_OTG_CHNUM_Msk                       (0xFUL << USB_OTG_CHNUM_Pos)    /*!< 0x0000000F */
-#define USB_OTG_CHNUM                           USB_OTG_CHNUM_Msk              /*!< Channel number */
-#define USB_OTG_CHNUM_0                         (0x1UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000001 */
-#define USB_OTG_CHNUM_1                         (0x2UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000002 */
-#define USB_OTG_CHNUM_2                         (0x4UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000004 */
-#define USB_OTG_CHNUM_3                         (0x8UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000008 */
-#define USB_OTG_BCNT_Pos                        (4U)                           
-#define USB_OTG_BCNT_Msk                        (0x7FFUL << USB_OTG_BCNT_Pos)   /*!< 0x00007FF0 */
-#define USB_OTG_BCNT                            USB_OTG_BCNT_Msk               /*!< Byte count */
-
-#define USB_OTG_DPID_Pos                        (15U)                          
-#define USB_OTG_DPID_Msk                        (0x3UL << USB_OTG_DPID_Pos)     /*!< 0x00018000 */
-#define USB_OTG_DPID                            USB_OTG_DPID_Msk               /*!< Data PID */
-#define USB_OTG_DPID_0                          (0x1UL << USB_OTG_DPID_Pos)     /*!< 0x00008000 */
-#define USB_OTG_DPID_1                          (0x2UL << USB_OTG_DPID_Pos)     /*!< 0x00010000 */
-
-#define USB_OTG_PKTSTS_Pos                      (17U)                          
-#define USB_OTG_PKTSTS_Msk                      (0xFUL << USB_OTG_PKTSTS_Pos)   /*!< 0x001E0000 */
-#define USB_OTG_PKTSTS                          USB_OTG_PKTSTS_Msk             /*!< Packet status */
-#define USB_OTG_PKTSTS_0                        (0x1UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00020000 */
-#define USB_OTG_PKTSTS_1                        (0x2UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00040000 */
-#define USB_OTG_PKTSTS_2                        (0x4UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00080000 */
-#define USB_OTG_PKTSTS_3                        (0x8UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00100000 */
-
-#define USB_OTG_EPNUM_Pos                       (0U)                           
-#define USB_OTG_EPNUM_Msk                       (0xFUL << USB_OTG_EPNUM_Pos)    /*!< 0x0000000F */
-#define USB_OTG_EPNUM                           USB_OTG_EPNUM_Msk              /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                         (0x1UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000001 */
-#define USB_OTG_EPNUM_1                         (0x2UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000002 */
-#define USB_OTG_EPNUM_2                         (0x4UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000004 */
-#define USB_OTG_EPNUM_3                         (0x8UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000008 */
-
-#define USB_OTG_FRMNUM_Pos                      (21U)                          
-#define USB_OTG_FRMNUM_Msk                      (0xFUL << USB_OTG_FRMNUM_Pos)   /*!< 0x01E00000 */
-#define USB_OTG_FRMNUM                          USB_OTG_FRMNUM_Msk             /*!< Frame number */
-#define USB_OTG_FRMNUM_0                        (0x1UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00200000 */
-#define USB_OTG_FRMNUM_1                        (0x2UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00400000 */
-#define USB_OTG_FRMNUM_2                        (0x4UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00800000 */
-#define USB_OTG_FRMNUM_3                        (0x8UL << USB_OTG_FRMNUM_Pos)   /*!< 0x01000000 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

From 707a633de3b4f47cf00396e16adb7946fa127880 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Mar 2022 23:03:37 +0700
Subject: [PATCH 0872/2085] added dcd_sof_enable(), tud_sof_isr_set()

make number of interface configurable (default to 8)
CFG_TUD_INTERFACE_MAX
---
 src/device/dcd.h  | 15 +++++++++++++++
 src/device/usbd.c | 18 ++++++++++++++++--
 src/device/usbd.h |  6 ++++++
 src/tusb_option.h |  4 ++++
 4 files changed, 41 insertions(+), 2 deletions(-)

diff --git a/src/device/dcd.h b/src/device/dcd.h
index 8efbc90ef..3eac6711f 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -77,6 +77,11 @@ typedef struct TU_ATTR_ALIGNED(4)
       tusb_speed_t speed;
     } bus_reset;
 
+    // SOF
+    struct {
+      uint32_t frame_count;
+    }sof;
+
     // SETUP_RECEIVED
     tusb_control_request_t setup_received;
 
@@ -132,6 +137,9 @@ void dcd_connect(uint8_t rhport) TU_ATTR_WEAK;
 // Disconnect by disabling internal pull-up resistor on D+/D-
 void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK;
 
+// Enable/Disable Start-of-frame interrupt. Default is disabled
+void dcd_sof_enable(uint8_t rhport, bool en);
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
@@ -185,6 +193,13 @@ extern void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool
 // helper to send transfer complete event
 extern void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr);
 
+static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr)
+{
+  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SOF };
+  event.sof.frame_count = frame_count;
+  dcd_event_handler(&event, in_isr);
+}
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 7926689b7..8662d5b84 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -67,7 +67,7 @@ typedef struct
   volatile uint8_t cfg_num; // current active configuration (0x00 is not configured)
   uint8_t speed;
 
-  uint8_t itf2drv[16];     // map interface number to driver (0xff is invalid)
+  uint8_t itf2drv[CFG_TUD_INTERFACE_MAX];   // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid )
 
   struct TU_ATTR_PACKED
@@ -269,6 +269,8 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 // DCD Event
 //--------------------------------------------------------------------+
 
+static tud_sof_isr_t _sof_isr = NULL;
+
 enum { RHPORT_INVALID = 0xFFu };
 static uint8_t _usbd_rhport = RHPORT_INVALID;
 
@@ -393,6 +395,12 @@ bool tud_connect(void)
   return true;
 }
 
+void tud_sof_isr_set(tud_sof_isr_t sof_isr)
+{
+  _sof_isr = sof_isr;
+  dcd_sof_enable(_usbd_rhport, _sof_isr != NULL);
+}
+
 //--------------------------------------------------------------------+
 // USBD Task
 //--------------------------------------------------------------------+
@@ -435,11 +443,13 @@ bool tud_init (uint8_t rhport)
     driver->init();
   }
 
+  _usbd_rhport = rhport;
+  _sof_isr = NULL;
+
   // Init device controller driver
   dcd_init(rhport);
   dcd_int_enable(rhport);
 
-  _usbd_rhport = rhport;
 
   return true;
 }
@@ -1121,11 +1131,15 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
     break;
 
     case DCD_EVENT_SOF:
+      // SOF Handler
+      if (_sof_isr) _sof_isr(event->sof.frame_count);
+
       // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup
       // which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational
       if ( _usbd_dev.suspended )
       {
         _usbd_dev.suspended = 0;
+
         dcd_event_t const event_resume = { .rhport = event->rhport, .event_id = DCD_EVENT_RESUME };
         osal_queue_send(_usbd_q, &event_resume, in_isr);
       }
diff --git a/src/device/usbd.h b/src/device/usbd.h
index b2bf8ba9d..72401a7e9 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -33,6 +33,8 @@
 extern "C" {
 #endif
 
+typedef void (*tud_sof_isr_t) (uint32_t frame_count);
+
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+
@@ -84,6 +86,10 @@ bool tud_disconnect(void);
 // Return false on unsupported MCUs
 bool tud_connect(void);
 
+// Set Start-of-frame (1ms interval) IRQ handler
+// NULL means disabled, frame_count may not be supported on mcus
+void tud_sof_isr_set(tud_sof_isr_t sof_isr);
+
 // Carry out Data and Status stage of control transfer
 // - If len = 0, it is equivalent to sending status only
 // - If len > wLength : it will be truncated
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 25e536787..9c8c274b1 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -287,6 +287,10 @@
   #define CFG_TUD_ENDPOINT0_SIZE  64
 #endif
 
+#ifndef CFG_TUD_INTERFACE_MAX
+  #define CFG_TUD_INTERFACE_MAX   8
+#endif
+
 #ifndef CFG_TUD_CDC
   #define CFG_TUD_CDC             0
 #endif

From 85dbcf5473f8f5d914c4c468715c5381ab2a6603 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Mar 2022 23:04:47 +0700
Subject: [PATCH 0873/2085] implement dcd_sof_enable() for rp2040

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 23 ++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 915822798..f7b105b6e 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -247,6 +247,12 @@ static void dcd_rp2040_irq(void)
     uint32_t const status = usb_hw->ints;
     uint32_t handled = 0;
 
+    if (status & USB_INTF_DEV_SOF_BITS)
+    {
+      handled |= USB_INTF_DEV_SOF_BITS;
+      dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true);
+    }
+
     // xfer events are handled before setup req. So if a transfer completes immediately
     // before closing the EP, the events will be delivered in same order.
     if (status & USB_INTS_BUFF_STATUS_BITS)
@@ -424,6 +430,23 @@ void dcd_connect(__unused uint8_t rhport)
   usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+
+  uint32_t inte = usb_hw->inte;
+
+  if (en)
+  {
+    inte |= USB_INTS_DEV_SOF_BITS;
+  }else
+  {
+    inte &= ~USB_INTS_DEV_SOF_BITS;
+  }
+
+  usb_hw->inte = inte;
+}
+
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port
  *------------------------------------------------------------------*/

From 606f932d92322a71960f51148ecc91eaf29bf507 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Mar 2022 23:05:05 +0700
Subject: [PATCH 0874/2085] added dcd_sof_enable() stubs for all other ports

---
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c             | 7 +++++++
 src/portable/chipidea/ci_hs/dcd_ci_hs.c              | 8 ++++++++
 src/portable/dialog/da146xx/dcd_da146xx.c            | 8 ++++++++
 src/portable/espressif/esp32sx/dcd_esp32sx.c         | 8 ++++++++
 src/portable/mentor/musb/dcd_musb.c                  | 8 ++++++++
 src/portable/microchip/pic32mz/dcd_pic32mz.c         | 8 ++++++++
 src/portable/microchip/samd/dcd_samd.c               | 8 ++++++++
 src/portable/microchip/samg/dcd_samg.c               | 8 ++++++++
 src/portable/microchip/samx7x/dcd_samx7x.c           | 8 ++++++++
 src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c     | 8 ++++++++
 src/portable/nordic/nrf5x/dcd_nrf5x.c                | 8 ++++++++
 src/portable/nuvoton/nuc120/dcd_nuc120.c             | 8 ++++++++
 src/portable/nuvoton/nuc121/dcd_nuc121.c             | 8 ++++++++
 src/portable/nuvoton/nuc505/dcd_nuc505.c             | 8 ++++++++
 src/portable/nxp/khci/dcd_khci.c                     | 8 ++++++++
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c             | 8 ++++++++
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c         | 8 ++++++++
 src/portable/nxp/transdimension/dcd_transdimension.c | 8 ++++++++
 src/portable/renesas/usba/dcd_usba.c                 | 8 ++++++++
 src/portable/sony/cxd56/dcd_cxd56.c                  | 8 ++++++++
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c        | 8 ++++++++
 src/portable/st/synopsys/dcd_synopsys.c              | 7 +++++++
 src/portable/sunxi/dcd_sunxi_musb.c                  | 8 ++++++++
 src/portable/synopsys/dwc2/dcd_dwc2.c                | 7 +++++++
 src/portable/template/dcd_template.c                 | 8 ++++++++
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c          | 8 ++++++++
 src/portable/valentyusb/eptri/dcd_eptri.c            | 7 +++++++
 27 files changed, 212 insertions(+)

diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 791f6cf60..3c3cb63b8 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -649,6 +649,13 @@ void dcd_disconnect(uint8_t rhport)
   _ft90x_phy_enable(false);
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
 
 //--------------------------------------------------------------------+
 // Endpoint API
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 32c2fc029..41d2f1870 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -266,6 +266,14 @@ void dcd_disconnect(uint8_t rhport)
   dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // HELPER
 //--------------------------------------------------------------------+
diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 919249a09..0bb8b6e41 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -882,6 +882,14 @@ void dcd_disconnect(uint8_t rhport)
   REG_CLR_BIT(USB_MCTRL_REG, USB_NAT);
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
 {
   return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0;
diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index bd8805dd3..a30fca0d8 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -240,6 +240,14 @@ void dcd_disconnect(uint8_t rhport)
   USB0.dctl |= USB_SFTDISCON_M;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index d36585592..0ba53d4d0 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -648,6 +648,14 @@ void dcd_disconnect(uint8_t rhport)
   USB0->POWER &= ~USB_POWER_SOFTCONN;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c
index 7d48f755b..db93644b1 100644
--- a/src/portable/microchip/pic32mz/dcd_pic32mz.c
+++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c
@@ -186,6 +186,14 @@ void dcd_disconnect(uint8_t rhport)
   USB_REGS->POWERbits.SOFTCONN = 1;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
 {
   return (_CP0_GET_STATUS() & (_CP0_STATUS_EXL_MASK | _CP0_STATUS_IPL_MASK)) != 0;
diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index c4ee6f2f5..5ae5a554b 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -180,6 +180,14 @@ void dcd_connect(uint8_t rhport)
    USB->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c
index 2e9854153..814e680fb 100644
--- a/src/portable/microchip/samg/dcd_samg.c
+++ b/src/portable/microchip/samg/dcd_samg.c
@@ -210,6 +210,14 @@ void dcd_disconnect(uint8_t rhport)
   UDP->UDP_TXVC = UDP_TXVC_TXVDIS_Msk;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index a82f29a88..7507c0f69 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -191,6 +191,14 @@ void dcd_disconnect(uint8_t rhport)
   USB_REG->DEVCTRL &=~(DEVCTRL_ADDEN | DEVCTRL_UADD);
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 static tusb_speed_t get_speed(void)
 {
   switch (USB_REG->SR & SR_SPEED) {
diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
index 1edcd8458..39b09db68 100644
--- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -305,6 +305,14 @@ void dcd_disconnect(uint8_t rhport)
   USB_OTG_FS->CTL      = 0;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index bc145eaa4..430d8eded 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -307,6 +307,14 @@ void dcd_connect(uint8_t rhport)
   NRF_USBD->USBPULLUP = 1;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c
index 694766613..2fdc05f36 100644
--- a/src/portable/nuvoton/nuc120/dcd_nuc120.c
+++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c
@@ -497,4 +497,12 @@ void dcd_connect(uint8_t rhport)
   usb_attach();
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 #endif
diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index 88d514bce..a56b5f8e8 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -551,4 +551,12 @@ void dcd_connect(uint8_t rhport)
   usb_attach();
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 #endif
diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c
index 498977561..886720e33 100644
--- a/src/portable/nuvoton/nuc505/dcd_nuc505.c
+++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c
@@ -720,4 +720,12 @@ void dcd_connect(uint8_t rhport)
   usb_attach();
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 #endif
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 4c7737103..13eb105cd 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -328,6 +328,14 @@ void dcd_disconnect(uint8_t rhport)
   KHCI->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index d2cce2db3..0894a5eeb 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -228,6 +228,14 @@ void dcd_disconnect(uint8_t rhport)
   sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 0);
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // CONTROL HELPER
 //--------------------------------------------------------------------+
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 55d872dc0..09ebf3b0d 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -277,6 +277,14 @@ void dcd_disconnect(uint8_t rhport)
   dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_CONNECT_MASK;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // DCD Endpoint Port
 //--------------------------------------------------------------------+
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 108baf99d..2347e1dae 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -294,6 +294,14 @@ void dcd_disconnect(uint8_t rhport)
   dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // HELPER
 //--------------------------------------------------------------------+
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/usba/dcd_usba.c
index 330f65348..fa87c9f4d 100644
--- a/src/portable/renesas/usba/dcd_usba.c
+++ b/src/portable/renesas/usba/dcd_usba.c
@@ -687,6 +687,14 @@ void dcd_disconnect(uint8_t rhport)
   USB0.SYSCFG.BIT.DPRPU = 0;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index fbea03b1d..6aa0efb21 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -247,6 +247,14 @@ void dcd_disconnect(uint8_t rhport)
   DEV_DISCONNECT(usbdev);
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index f201a02cf..836711974 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -287,6 +287,14 @@ void dcd_connect(uint8_t rhport)
 }
 #endif
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 // Enable device interrupt
 void dcd_int_enable (uint8_t rhport)
 {
diff --git a/src/portable/st/synopsys/dcd_synopsys.c b/src/portable/st/synopsys/dcd_synopsys.c
index d7f659340..2fc3adb4f 100644
--- a/src/portable/st/synopsys/dcd_synopsys.c
+++ b/src/portable/st/synopsys/dcd_synopsys.c
@@ -602,6 +602,13 @@ void dcd_disconnect(uint8_t rhport)
   dev->DCTL |= USB_OTG_DCTL_SDIS;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
 
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 27514339b..a0be846a5 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -909,6 +909,14 @@ void dcd_disconnect(uint8_t rhport)
   USBC_REG_clear_bit_b(USBC_BP_POWER_D_SOFT_CONNECT, USBC_REG_PCTL(USBC0_BASE));
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 void dcd_int_enable(uint8_t rhport)
 {
   (void)rhport;
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index c71f38d2d..37712d2d9 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -588,6 +588,13 @@ void dcd_disconnect(uint8_t rhport)
   dwc2->dctl |= DCTL_SDIS;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
 
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port
diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c
index 977369300..26b5dce9d 100644
--- a/src/portable/template/dcd_template.c
+++ b/src/portable/template/dcd_template.c
@@ -82,6 +82,14 @@ void dcd_disconnect(uint8_t rhport)
   (void) rhport;
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index c3b3b2403..605c13b4a 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -222,6 +222,14 @@ void dcd_disconnect(uint8_t rhport)
   dcd_int_enable(rhport);
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c
index dfadfdcb3..e368b5f39 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.c
+++ b/src/portable/valentyusb/eptri/dcd_eptri.c
@@ -401,6 +401,13 @@ void dcd_disconnect(uint8_t rhport)
   usb_pullup_out_write(0);
 }
 
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
 
 //--------------------------------------------------------------------+
 // DCD Endpoint Port

From 6b2ea2bd1dbf05ae9fb04546b532df293521ccfb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 8 Mar 2022 13:52:20 +0700
Subject: [PATCH 0875/2085] fix issue 1359

---
 src/tusb_option.h | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 25e536787..b613eec44 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -207,18 +207,23 @@
 //------------- Roothub as Device -------------//
 
 #if (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE
-  #define TUD_RHPORT_MODE  (CFG_TUSB_RHPORT0_MODE)
-  #define TUD_OPT_RHPORT   0
+  #define TUD_RHPORT_MODE     (CFG_TUSB_RHPORT0_MODE)
+  #define TUD_OPT_RHPORT      0
 #elif (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE
-  #define TUD_RHPORT_MODE  (CFG_TUSB_RHPORT1_MODE)
-  #define TUD_OPT_RHPORT   1
+  #define TUD_RHPORT_MODE     (CFG_TUSB_RHPORT1_MODE)
+  #define TUD_OPT_RHPORT      1
 #else
-  #define TUD_RHPORT_MODE   OPT_MODE_NONE
-  #define TUD_OPT_RHPORT   -1
+  #define TUD_RHPORT_MODE     OPT_MODE_NONE
+  #define TUD_OPT_RHPORT      -1
 #endif
 
-#define CFG_TUD_ENABLED     ( TUD_RHPORT_MODE & OPT_MODE_DEVICE )
-#define TUD_OPT_HIGH_SPEED  ( (TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK) ? (TUD_RHPORT_MODE & OPT_MODE_HIGH_SPEED) : (TUP_RHPORT_HIGHSPEED & (1 << TUD_OPT_RHPORT)) )
+#define CFG_TUD_ENABLED       (TUD_RHPORT_MODE & OPT_MODE_DEVICE)
+
+#if CFG_TUD_ENABLED
+  #define TUD_OPT_HIGH_SPEED  ((TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK) ? (TUD_RHPORT_MODE & OPT_MODE_HIGH_SPEED) : (TUP_RHPORT_HIGHSPEED & (1 << TUD_OPT_RHPORT)))
+#else
+  #define TUD_OPT_HIGH_SPEED  0
+#endif
 
 //------------- Roothub as Host -------------//
 

From db9d97c9473f29ad59a87d641e6d41a27a00f332 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Mar 2022 11:03:29 +0700
Subject: [PATCH 0876/2085] add tuh_descriptor_hid_report_get()

---
 examples/host/bare_api/src/main.c | 48 ++++++++++++++++++++++++++-----
 src/class/hid/hid_host.c          | 17 +----------
 src/host/usbh.c                   | 22 ++++++++++++++
 src/host/usbh.h                   |  3 ++
 4 files changed, 67 insertions(+), 23 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index b6b1527c0..2fe5999bc 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -64,23 +64,57 @@ int main(void)
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
 
-void print_device_descriptor(uint8_t dev_addr)
+uint8_t usb_buf[256] TU_ATTR_ALIGNED(4);
+
+tusb_desc_device_t desc_device;
+
+bool print_device_descriptor(uint8_t daddr, tusb_control_request_t const * request, xfer_result_t result)
 {
-  (void) dev_addr;
+  (void) request;
+
+  if ( XFER_RESULT_SUCCESS != result )
+  {
+    printf("Failed to get device descriptor\r\n");
+    return false;
+  }
+
+  printf("Rhport %u Device %u: ID %04x:%04x\r\n", 0, daddr, desc_device.idVendor, desc_device.idProduct);
   printf("Device Descriptor:\r\n");
+  printf("  bLength             %u\r\n", desc_device.bLength);
+  printf("  bDescriptorType     %u\r\n", desc_device.bDescriptorType);
+  printf("  bcdUSB              %04x\r\n", desc_device.bcdUSB);
+
+  printf("  bDeviceClass        %u\r\n", desc_device.bDeviceClass);
+  printf("  bDeviceSubClass     %u\r\n", desc_device.bDeviceSubClass);
+  printf("  bDeviceProtocol     %u\r\n", desc_device.bDeviceProtocol);
+  printf("  bMaxPacketSize0     %u\r\n", desc_device.bMaxPacketSize0);
+
+  printf("  idVendor            0x%04x\r\n", desc_device.idVendor);
+  printf("  idProduct           0x%04x\r\n", desc_device.idProduct);
+  printf("  bcdDevice           %04x\r\n", desc_device.bcdDevice);
+
+  printf("  iManufacturer       %u\r\n", desc_device.iManufacturer);
+  printf("  iProduct            %u\r\n", desc_device.iProduct);
+  printf("  iSerialNumber       %u\r\n", desc_device.iSerialNumber);
+
+  printf("  bNumConfigurations  %u\r\n", desc_device.bNumConfigurations);
+
+  return true;
 }
 
 // Invoked when device is mounted (configured)
-void tuh_mount_cb (uint8_t dev_addr)
+void tuh_mount_cb (uint8_t daddr)
 {
-  printf("Device attached, address = %d\r\n", dev_addr);
-  print_device_descriptor(dev_addr);
+  printf("Device attached, address = %d\r\n", daddr);
+
+  // get device descriptor
+  tuh_descriptor_device_get(daddr, &desc_device, 18, print_device_descriptor);
 }
 
 /// Invoked when device is unmounted (bus reset/unplugged)
-void tuh_umount_cb(uint8_t dev_addr)
+void tuh_umount_cb(uint8_t daddr)
 {
-  printf("Device removed, address = %d\r\n", dev_addr);
+  printf("Device removed, address = %d\r\n", daddr);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 9190642c6..32bb775b0 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -409,22 +409,7 @@ static bool config_get_report_desc(uint8_t dev_addr, tusb_control_request_t cons
     config_driver_mount_complete(dev_addr, instance, NULL, 0);
   }else
   {
-    TU_LOG2("HID Get Report Descriptor\r\n");
-    tusb_control_request_t const new_request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_STANDARD,
-        .direction = TUSB_DIR_IN
-      },
-      .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-      .wValue   = tu_u16(hid_itf->report_desc_type, 0),
-      .wIndex   = itf_num,
-      .wLength  = hid_itf->report_desc_len
-    };
-
-    TU_ASSERT(tuh_control_xfer(dev_addr, &new_request, usbh_get_enum_buf(), config_get_report_desc_complete));
+    TU_ASSERT(tuh_descriptor_hid_report_get(dev_addr, itf_num, hid_itf->report_desc_type, usbh_get_enum_buf(), hid_itf->report_desc_len, config_get_report_desc_complete));
   }
 
   return true;
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 192979ce6..b047179c5 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -299,6 +299,7 @@ bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer
 
 bool tuh_descriptor_device_get(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
 {
+  len = tu_min16(len, sizeof(tusb_desc_device_t));
   return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb);
 }
 
@@ -361,6 +362,27 @@ bool tuh_descriptor_string_serial_get(uint8_t daddr, uint16_t language_id, void*
   return tuh_descriptor_string_get(daddr, language_id, dev->i_serial, buffer, len, complete_cb);
 }
 
+// Get HID report descriptor
+bool tuh_descriptor_hid_report_get(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+{
+  TU_LOG2("HID Get Report Descriptor\r\n");
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_STANDARD,
+      .direction = TUSB_DIR_IN
+    },
+    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+    .wValue   = tu_htole16(TU_U16(desc_type, 0)),
+    .wIndex   = itf_num,
+    .wLength  = len
+  };
+
+  return tuh_control_xfer(daddr, &request, buffer, complete_cb);
+}
+
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_control_complete_cb_t complete_cb)
 {
   TU_LOG2("Set Configuration = %d\r\n", config_num);
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 9465d1d1b..6fea2fac5 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -112,6 +112,9 @@ bool tuh_descriptor_string_product_get(uint8_t daddr, uint16_t language_id, void
 // Get serial string descriptor
 bool tuh_descriptor_string_serial_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
+// Get HID report descriptor
+bool tuh_descriptor_hid_report_get(uint8_t daddr, uint8_t itf_num, uint8_t desc_type,  void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+
 //--------------------------------------------------------------------+
 // APPLICATION CALLBACK
 //--------------------------------------------------------------------+

From f920e1c17102cac04b20ad3908efff24d96d8e7c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Mar 2022 11:21:13 +0700
Subject: [PATCH 0877/2085] rename host descriptor function

---
 examples/host/bare_api/src/main.c |  2 +-
 src/class/hid/hid_host.c          |  2 +-
 src/host/usbh.c                   | 28 ++++++++++++++--------------
 src/host/usbh.h                   | 14 +++++++-------
 4 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 2fe5999bc..5f8f886c8 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -108,7 +108,7 @@ void tuh_mount_cb (uint8_t daddr)
   printf("Device attached, address = %d\r\n", daddr);
 
   // get device descriptor
-  tuh_descriptor_device_get(daddr, &desc_device, 18, print_device_descriptor);
+  tuh_descriptor_get_device(daddr, &desc_device, 18, print_device_descriptor);
 }
 
 /// Invoked when device is unmounted (bus reset/unplugged)
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 32bb775b0..323debe69 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -409,7 +409,7 @@ static bool config_get_report_desc(uint8_t dev_addr, tusb_control_request_t cons
     config_driver_mount_complete(dev_addr, instance, NULL, 0);
   }else
   {
-    TU_ASSERT(tuh_descriptor_hid_report_get(dev_addr, itf_num, hid_itf->report_desc_type, usbh_get_enum_buf(), hid_itf->report_desc_len, config_get_report_desc_complete));
+    TU_ASSERT(tuh_descriptor_get_hid_report(dev_addr, itf_num, hid_itf->report_desc_type, usbh_get_enum_buf(), hid_itf->report_desc_len, config_get_report_desc_complete));
   }
 
   return true;
diff --git a/src/host/usbh.c b/src/host/usbh.c
index b047179c5..74c763552 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -297,18 +297,18 @@ bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer
   return true;
 }
 
-bool tuh_descriptor_device_get(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
 {
   len = tu_min16(len, sizeof(tusb_desc_device_t));
   return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb);
 }
 
-bool tuh_descriptor_configuration_get(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
 {
   return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb);
 }
 
-bool tuh_descriptor_string_get(uint8_t daddr, uint16_t language_id, uint8_t index,
+bool tuh_descriptor_get_string(uint8_t daddr, uint16_t language_id, uint8_t index,
                                void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
 {
   tusb_control_request_t const request =
@@ -330,40 +330,40 @@ bool tuh_descriptor_string_get(uint8_t daddr, uint16_t language_id, uint8_t inde
 }
 
 // Get manufacturer string descriptor
-bool tuh_descriptor_string_manufacturer_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
 {
   TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
   if (dev->i_manufacturer == 0) {
     return false;
   }
-  return tuh_descriptor_string_get(daddr, language_id, dev->i_manufacturer, buffer, len, complete_cb);
+  return tuh_descriptor_get_string(daddr, language_id, dev->i_manufacturer, buffer, len, complete_cb);
 }
 
 // Get product string descriptor
-bool tuh_descriptor_string_product_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
 {
   TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
   if (dev->i_product == 0) {
     return false;
   }
-  return tuh_descriptor_string_get(daddr, language_id, dev->i_product, buffer, len, complete_cb);
+  return tuh_descriptor_get_string(daddr, language_id, dev->i_product, buffer, len, complete_cb);
 }
 
 // Get serial string descriptor
-bool tuh_descriptor_string_serial_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
 {
   TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
   if (dev->i_serial == 0) {
     return false;
   }
-  return tuh_descriptor_string_get(daddr, language_id, dev->i_serial, buffer, len, complete_cb);
+  return tuh_descriptor_get_string(daddr, language_id, dev->i_serial, buffer, len, complete_cb);
 }
 
 // Get HID report descriptor
-bool tuh_descriptor_hid_report_get(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
 {
   TU_LOG2("HID Get Report Descriptor\r\n");
   tusb_control_request_t const request =
@@ -868,7 +868,7 @@ static bool enum_request_addr0_device_desc(void)
   // Get first 8 bytes of device descriptor for Control Endpoint size
   TU_LOG2("Get 8 byte of Device Descriptor\r\n");
 
-  TU_ASSERT(tuh_descriptor_device_get(addr0, _usbh_ctrl_buf, 8, enum_get_addr0_device_desc_complete));
+  TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, enum_get_addr0_device_desc_complete));
   return true;
 }
 
@@ -977,7 +977,7 @@ static bool enum_set_address_complete(uint8_t dev_addr, tusb_control_request_t c
   // Get full device descriptor
   TU_LOG2("Get Device Descriptor\r\n");
 
-  TU_ASSERT(tuh_descriptor_device_get(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), enum_get_device_desc_complete));
+  TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), enum_get_device_desc_complete));
   return true;
 }
 
@@ -1000,7 +1000,7 @@ static bool enum_get_device_desc_complete(uint8_t dev_addr, tusb_control_request
   // Get 9-byte for total length
   uint8_t const config_idx = CONFIG_NUM - 1;
   TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n");
-  TU_ASSERT( tuh_descriptor_configuration_get(dev_addr, config_idx, _usbh_ctrl_buf, 9, enum_get_9byte_config_desc_complete) );
+  TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, 9, enum_get_9byte_config_desc_complete) );
   return true;
 }
 
@@ -1020,7 +1020,7 @@ static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tusb_control_r
   // Get full configuration descriptor
   uint8_t const config_idx = CONFIG_NUM - 1;
   TU_LOG2("Get Configuration[0] Descriptor\r\n");
-  TU_ASSERT( tuh_descriptor_configuration_get(dev_addr, config_idx, _usbh_ctrl_buf, total_len, enum_get_config_desc_complete) );
+  TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, total_len, enum_get_config_desc_complete) );
   return true;
 }
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 6fea2fac5..31d63d6a7 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -94,26 +94,26 @@ bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index,
                         void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
 // Get device descriptor
-bool tuh_descriptor_device_get(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
 // Get configuration descriptor
-bool tuh_descriptor_configuration_get(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
 // Get string descriptor
-bool tuh_descriptor_string_get(uint8_t daddr, uint16_t language_id, uint8_t index,
+bool tuh_descriptor_get_string(uint8_t daddr, uint16_t language_id, uint8_t index,
                                void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
 // Get manufacturer string descriptor
-bool tuh_descriptor_string_manufacturer_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
 // Get product string descriptor
-bool tuh_descriptor_string_product_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
 // Get serial string descriptor
-bool tuh_descriptor_string_serial_get(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
 // Get HID report descriptor
-bool tuh_descriptor_hid_report_get(uint8_t daddr, uint8_t itf_num, uint8_t desc_type,  void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
 
 //--------------------------------------------------------------------+
 // APPLICATION CALLBACK

From 2f593e767c28ac5b789a5def2221620c1a2e58b8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Mar 2022 12:26:56 +0700
Subject: [PATCH 0878/2085] update use of mutex for host

---
 src/device/usbd.c |  2 +-
 src/host/usbh.c   | 96 +++++++++++++++++++++++++++--------------------
 src/tusb_option.h |  3 ++
 3 files changed, 59 insertions(+), 42 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 7926689b7..b14b5e0fc 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -273,7 +273,7 @@ enum { RHPORT_INVALID = 0xFFu };
 static uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
-// OPT_MODE_DEVICE is used by OS NONE for mutex (disable usb isr)
+// usbd_int_set() is used as mutex in OS NONE config
 OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
 static osal_queue_t _usbd_q;
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 74c763552..59fcb4da3 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -112,13 +112,6 @@ typedef struct {
 
     // TODO merge ep2drv here, 4-bit should be sufficient
   }ep_status[CFG_TUH_ENDPOINT_MAX][2];
-
-  // Mutex for claiming endpoint, only needed when using with preempted RTOS
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_def_t mutexdef;
-  osal_mutex_t mutex;
-#endif
-
 } usbh_device_t;
 
 
@@ -204,6 +197,9 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
+// sum of end device + hub
+#define TOTAL_DEVICES   (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB)
+
 static bool _usbh_initialized = false;
 
 // Device with address = 0 for enumeration
@@ -211,14 +207,43 @@ static usbh_dev0_t _dev0;
 
 // all devices excluding zero-address
 // hub address start from CFG_TUH_DEVICE_MAX+1
-CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUH_DEVICE_MAX + CFG_TUH_HUB];
+// TODO: hub can has its own simpler struct to save memory
+CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[TOTAL_DEVICES];
+
+// Mutex for claiming endpoint, only needed when using with preempted RTOS
+#if TUSB_OPT_MUTEX
+
+static osal_mutex_def_t _usbh_mutexdef[TOTAL_DEVICES];
+static osal_mutex_t _usbh_mutex[TOTAL_DEVICES];
+
+static inline void lock_device(uint8_t daddr)
+{
+  // addr0 is always available
+  if (daddr) return;
+  osal_mutex_lock(&_usbh_mutex[daddr-1], OSAL_TIMEOUT_WAIT_FOREVER);
+}
+
+static inline void unlock_device(uint8_t daddr)
+{
+  // addr0 is always available
+  if (daddr) return;
+  osal_mutex_unlock(&_usbh_mutex[daddr-1]);
+}
+
+#else
+
+#define lock_device(_addr)
+#define unlock_device(_addr)
+
+#endif
 
 // Event queue
-// role device/host is used by OS NONE for mutex (disable usb isr)
+// usbh_int_set is used as mutex in OS NONE config
 OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
+static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
 //------------- Helper Function -------------//
 
@@ -408,6 +433,13 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_control_comple
 // CLASS-USBD API (don't require to verify parameters)
 //--------------------------------------------------------------------+
 
+static void clear_device(usbh_device_t* dev)
+{
+  tu_memclr(dev, sizeof(usbh_device_t));
+  memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
+  memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
+}
+
 bool tuh_inited(void)
 {
   return _usbh_initialized;
@@ -421,25 +453,22 @@ bool tuh_init(uint8_t rhport)
   TU_LOG2("USBH init\r\n");
   TU_LOG2_INT(sizeof(usbh_device_t));
 
-  tu_memclr(_usbh_devices, sizeof(_usbh_devices));
-  tu_memclr(&_dev0, sizeof(_dev0));
-
   //------------- Enumeration & Reporter Task init -------------//
   _usbh_q = osal_queue_create( &_usbh_qdef );
   TU_ASSERT(_usbh_q != NULL);
 
   //------------- Semaphore, Mutex for Control Pipe -------------//
-  for(uint8_t i=0; i<TU_ARRAY_SIZE(_usbh_devices); i++)
+  tu_memclr(&_dev0, sizeof(_dev0));
+  tu_memclr(_usbh_devices, sizeof(_usbh_devices));
+
+  for(uint8_t i=0; i<TOTAL_DEVICES; i++)
   {
-    usbh_device_t * dev = &_usbh_devices[i];
+    clear_device(&_usbh_devices[i]);
 
-#if CFG_TUSB_OS != OPT_OS_NONE
-    dev->mutex = osal_mutex_create(&dev->mutexdef);
-    TU_ASSERT(dev->mutex);
+#if TUSB_OPT_MUTEX
+    _usbh_mutex[i] = osal_mutex_create(&_usbh_mutexdef[i]);
+    TU_ASSERT(_usbh_mutex[i]);
 #endif
-
-    memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
-    memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
   }
 
   // Class drivers init
@@ -686,14 +715,7 @@ void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port
       }
 
       hcd_device_close(rhport, dev_addr);
-
-      // release all endpoints associated with the device
-      memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
-      memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
-      tu_memclr(dev->ep_status, sizeof(dev->ep_status));
-
-      dev->state = TUSB_DEVICE_STATE_UNPLUG;
-      dev->configured = false;
+      clear_device(dev);
     }
   }
 }
@@ -1161,11 +1183,9 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
 
   usbh_device_t* dev = get_device(dev_addr);
 
-#if CFG_TUSB_OS != OPT_OS_NONE
   // pre-check to help reducing mutex lock
   TU_VERIFY((dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 0));
-  osal_mutex_lock(dev->mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-#endif
+  lock_device(dev_addr);
 
   // can only claim the endpoint if it is not busy and not claimed yet.
   bool const ret = (dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 0);
@@ -1174,9 +1194,7 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
     dev->ep_status[epnum][dir].claimed = 1;
   }
 
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_unlock(dev->mutex);
-#endif
+  unlock_device(dev_addr);
 
   return ret;
 }
@@ -1189,9 +1207,7 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
 
   usbh_device_t* dev = get_device(dev_addr);
 
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_lock(dev->mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-#endif
+  lock_device(dev_addr);
 
   // can only release the endpoint if it is claimed and not busy
   bool const ret = (dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 1);
@@ -1200,9 +1216,7 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
     dev->ep_status[epnum][dir].claimed = 0;
   }
 
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_unlock(dev->mutex);
-#endif
+  unlock_device(dev_addr);
 
   return ret;
 }
diff --git a/src/tusb_option.h b/src/tusb_option.h
index afd69c38b..e5351b1c4 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -285,6 +285,9 @@
   #define CFG_TUSB_OS_INC_PATH
 #endif
 
+// mutex is only needed for RTOS
+#define TUSB_OPT_MUTEX    (CFG_TUSB_OS != OPT_OS_NONE)
+
 //--------------------------------------------------------------------
 // DEVICE OPTIONS
 //--------------------------------------------------------------------

From 708f05668d681439e521379e281d087d1910a0f3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Mar 2022 16:42:51 +0700
Subject: [PATCH 0879/2085] add tusb_debug.h remove tusb_error.h

move debug utils to new header
---
 src/class/cdc/cdc_host.c       |   4 +-
 src/class/cdc/cdc_rndis_host.h |   2 +-
 src/class/vendor/vendor_host.h |  12 +--
 src/common/tusb_common.h       | 134 +------------------------
 src/common/tusb_debug.h        | 174 +++++++++++++++++++++++++++++++++
 src/common/tusb_error.h        |  77 ---------------
 src/common/tusb_verify.h       |  28 ------
 src/device/usbd.c              |  21 +---
 src/host/usbh.c                |  13 ++-
 src/host/usbh_control.c        |   7 +-
 src/tusb.c                     |  22 ++++-
 11 files changed, 220 insertions(+), 274 deletions(-)
 create mode 100644 src/common/tusb_debug.h
 delete mode 100644 src/common/tusb_error.h

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index c18234db4..2787cd201 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -100,7 +100,7 @@ bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool i
 {
   (void) is_notify;
   TU_VERIFY( tuh_cdc_mounted(dev_addr) );
-  TU_VERIFY( p_data != NULL && length, TUSB_ERROR_INVALID_PARA);
+  TU_VERIFY( p_data != NULL && length);
 
   uint8_t const ep_out = cdch_data[dev_addr-1].ep_out;
   if ( usbh_edpt_busy(dev_addr, ep_out) ) return false;
@@ -112,7 +112,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
 {
   (void) is_notify;
   TU_VERIFY( tuh_cdc_mounted(dev_addr) );
-  TU_VERIFY( p_buffer != NULL && length, TUSB_ERROR_INVALID_PARA);
+  TU_VERIFY( p_buffer != NULL && length );
 
   uint8_t const ep_in = cdch_data[dev_addr-1].ep_in;
   if ( usbh_edpt_busy(dev_addr, ep_in) ) return false;
diff --git a/src/class/cdc/cdc_rndis_host.h b/src/class/cdc/cdc_rndis_host.h
index 170cb3b0e..447cc4e97 100644
--- a/src/class/cdc/cdc_rndis_host.h
+++ b/src/class/cdc/cdc_rndis_host.h
@@ -50,7 +50,7 @@ typedef struct {
 }rndish_data_t;
 
 void rndish_init(void);
-tusb_error_t rndish_open_subtask(uint8_t dev_addr, cdch_data_t *p_cdc);
+bool rndish_open_subtask(uint8_t dev_addr, cdch_data_t *p_cdc);
 void rndish_xfer_isr(cdch_data_t *p_cdc, pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes);
 void rndish_close(uint8_t dev_addr);
 
diff --git a/src/class/vendor/vendor_host.h b/src/class/vendor/vendor_host.h
index 07fa56c61..65223fbca 100644
--- a/src/class/vendor/vendor_host.h
+++ b/src/class/vendor/vendor_host.h
@@ -49,16 +49,16 @@ static inline bool tusbh_custom_is_mounted(uint8_t dev_addr, uint16_t vendor_id,
   return false;
 }
 
-tusb_error_t tusbh_custom_read(uint8_t dev_addr, uint16_t vendor_id, uint16_t product_id, void * p_buffer, uint16_t length);
-tusb_error_t tusbh_custom_write(uint8_t dev_addr, uint16_t vendor_id, uint16_t product_id, void const * p_data, uint16_t length);
+bool tusbh_custom_read(uint8_t dev_addr, uint16_t vendor_id, uint16_t product_id, void * p_buffer, uint16_t length);
+bool tusbh_custom_write(uint8_t dev_addr, uint16_t vendor_id, uint16_t product_id, void const * p_data, uint16_t length);
 
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
-void         cush_init(void);
-tusb_error_t cush_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length);
-void         cush_isr(pipe_handle_t pipe_hdl, xfer_result_t event);
-void         cush_close(uint8_t dev_addr);
+void cush_init(void);
+bool cush_open_subtask(uint8_t dev_addr, tusb_desc_interface_t const *p_interface_desc, uint16_t *p_length);
+void cush_isr(pipe_handle_t pipe_hdl, xfer_result_t event);
+void cush_close(uint8_t dev_addr);
 
 #ifdef __cplusplus
  }
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 26865805e..34f3bb8f7 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -71,8 +71,8 @@
 #include "tusb_compiler.h"
 #include "tusb_verify.h"
 #include "tusb_types.h"
+#include "tusb_debug.h"
 
-#include "tusb_error.h"   // TODO remove
 #include "tusb_timeout.h" // TODO remove
 
 //--------------------------------------------------------------------+
@@ -268,138 +268,6 @@ TU_ATTR_ALWAYS_INLINE static inline void     tu_unaligned_write16 (void* mem, ui
             + TU_BIN8(dlsb))
 #endif
 
-//--------------------------------------------------------------------+
-// Debug Function
-//--------------------------------------------------------------------+
-
-// CFG_TUSB_DEBUG for debugging
-// 0 : no debug
-// 1 : print error
-// 2 : print warning
-// 3 : print info
-#if CFG_TUSB_DEBUG
-
-void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
-
-#ifdef CFG_TUSB_DEBUG_PRINTF
-  extern int CFG_TUSB_DEBUG_PRINTF(const char *format, ...);
-  #define tu_printf    CFG_TUSB_DEBUG_PRINTF
-#else
-  #define tu_printf    printf
-#endif
-
-static inline
-void tu_print_var(uint8_t const* buf, uint32_t bufsize)
-{
-  for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
-}
-
-// Log with Level
-#define TU_LOG(n, ...)        TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
-#define TU_LOG_MEM(n, ...)    TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
-#define TU_LOG_VAR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _VAR)(__VA_ARGS__)
-#define TU_LOG_INT(n, ...)    TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
-#define TU_LOG_HEX(n, ...)    TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
-#define TU_LOG_LOCATION()     tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
-#define TU_LOG_FAILED()       tu_printf("%s: %d: Failed\r\n", __PRETTY_FUNCTION__, __LINE__)
-
-// Log Level 1: Error
-#define TU_LOG1               tu_printf
-#define TU_LOG1_MEM           tu_print_mem
-#define TU_LOG1_VAR(_x)       tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
-#define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
-#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
-
-// Log Level 2: Warn
-#if CFG_TUSB_DEBUG >= 2
-  #define TU_LOG2             TU_LOG1
-  #define TU_LOG2_MEM         TU_LOG1_MEM
-  #define TU_LOG2_VAR         TU_LOG1_VAR
-  #define TU_LOG2_INT         TU_LOG1_INT
-  #define TU_LOG2_HEX         TU_LOG1_HEX
-#endif
-
-// Log Level 3: Info
-#if CFG_TUSB_DEBUG >= 3
-  #define TU_LOG3             TU_LOG1
-  #define TU_LOG3_MEM         TU_LOG1_MEM
-  #define TU_LOG3_VAR         TU_LOG1_VAR
-  #define TU_LOG3_INT         TU_LOG1_INT
-  #define TU_LOG3_HEX         TU_LOG1_HEX
-#endif
-
-typedef struct
-{
-  uint32_t key;
-  const char* data;
-} tu_lookup_entry_t;
-
-typedef struct
-{
-  uint16_t count;
-  tu_lookup_entry_t const* items;
-} tu_lookup_table_t;
-
-static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
-{
-  static char not_found[11];
-
-  for(uint16_t i=0; i<p_table->count; i++)
-  {
-    if (p_table->items[i].key == key) return p_table->items[i].data;
-  }
-
-  // not found return the key value in hex
-  snprintf(not_found, sizeof(not_found), "0x%08lX", (unsigned long) key);
-
-  return not_found;
-}
-
-#endif // CFG_TUSB_DEBUG
-
-#ifndef TU_LOG
-#define TU_LOG(n, ...)
-#define TU_LOG_MEM(n, ...)
-#define TU_LOG_VAR(n, ...)
-#define TU_LOG_INT(n, ...)
-#define TU_LOG_HEX(n, ...)
-#define TU_LOG_LOCATION()
-#define TU_LOG_FAILED()
-#endif
-
-// TODO replace all TU_LOGn with TU_LOG(n)
-
-#define TU_LOG0(...)
-#define TU_LOG0_MEM(...)
-#define TU_LOG0_VAR(...)
-#define TU_LOG0_INT(...)
-#define TU_LOG0_HEX(...)
-
-
-#ifndef TU_LOG1
-  #define TU_LOG1(...)
-  #define TU_LOG1_MEM(...)
-  #define TU_LOG1_VAR(...)
-  #define TU_LOG1_INT(...)
-  #define TU_LOG1_HEX(...)
-#endif
-
-#ifndef TU_LOG2
-  #define TU_LOG2(...)
-  #define TU_LOG2_MEM(...)
-  #define TU_LOG2_VAR(...)
-  #define TU_LOG2_INT(...)
-  #define TU_LOG2_HEX(...)
-#endif
-
-#ifndef TU_LOG3
-  #define TU_LOG3(...)
-  #define TU_LOG3_MEM(...)
-  #define TU_LOG3_VAR(...)
-  #define TU_LOG3_INT(...)
-  #define TU_LOG3_HEX(...)
-#endif
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
new file mode 100644
index 000000000..647e8a8db
--- /dev/null
+++ b/src/common/tusb_debug.h
@@ -0,0 +1,174 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_DEBUG_H_
+#define _TUSB_DEBUG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Debug
+//--------------------------------------------------------------------+
+
+// CFG_TUSB_DEBUG for debugging
+// 0 : no debug
+// 1 : print error
+// 2 : print warning
+// 3 : print info
+#if CFG_TUSB_DEBUG
+
+// Enum to String for debugging purposes
+#if CFG_TUSB_DEBUG >= 2
+extern char const* const tu_str_speed[];
+extern char const* const tu_str_std_request[];
+#endif
+
+void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
+
+#ifdef CFG_TUSB_DEBUG_PRINTF
+  extern int CFG_TUSB_DEBUG_PRINTF(const char *format, ...);
+  #define tu_printf    CFG_TUSB_DEBUG_PRINTF
+#else
+  #define tu_printf    printf
+#endif
+
+static inline void tu_print_var(uint8_t const* buf, uint32_t bufsize)
+{
+  for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
+}
+
+// Log with Level
+#define TU_LOG(n, ...)        TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
+#define TU_LOG_MEM(n, ...)    TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
+#define TU_LOG_VAR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _VAR)(__VA_ARGS__)
+#define TU_LOG_INT(n, ...)    TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
+#define TU_LOG_HEX(n, ...)    TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
+#define TU_LOG_LOCATION()     tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
+#define TU_LOG_FAILED()       tu_printf("%s: %d: Failed\r\n", __PRETTY_FUNCTION__, __LINE__)
+
+// Log Level 1: Error
+#define TU_LOG1               tu_printf
+#define TU_LOG1_MEM           tu_print_mem
+#define TU_LOG1_VAR(_x)       tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
+#define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
+#define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
+
+// Log Level 2: Warn
+#if CFG_TUSB_DEBUG >= 2
+  #define TU_LOG2             TU_LOG1
+  #define TU_LOG2_MEM         TU_LOG1_MEM
+  #define TU_LOG2_VAR         TU_LOG1_VAR
+  #define TU_LOG2_INT         TU_LOG1_INT
+  #define TU_LOG2_HEX         TU_LOG1_HEX
+#endif
+
+// Log Level 3: Info
+#if CFG_TUSB_DEBUG >= 3
+  #define TU_LOG3             TU_LOG1
+  #define TU_LOG3_MEM         TU_LOG1_MEM
+  #define TU_LOG3_VAR         TU_LOG1_VAR
+  #define TU_LOG3_INT         TU_LOG1_INT
+  #define TU_LOG3_HEX         TU_LOG1_HEX
+#endif
+
+typedef struct
+{
+  uint32_t key;
+  const char* data;
+} tu_lookup_entry_t;
+
+typedef struct
+{
+  uint16_t count;
+  tu_lookup_entry_t const* items;
+} tu_lookup_table_t;
+
+static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
+{
+  static char not_found[11];
+
+  for(uint16_t i=0; i<p_table->count; i++)
+  {
+    if (p_table->items[i].key == key) return p_table->items[i].data;
+  }
+
+  // not found return the key value in hex
+  snprintf(not_found, sizeof(not_found), "0x%08lX", (unsigned long) key);
+
+  return not_found;
+}
+
+#endif // CFG_TUSB_DEBUG
+
+#ifndef TU_LOG
+  #define TU_LOG(n, ...)
+  #define TU_LOG_MEM(n, ...)
+  #define TU_LOG_VAR(n, ...)
+  #define TU_LOG_INT(n, ...)
+  #define TU_LOG_HEX(n, ...)
+  #define TU_LOG_LOCATION()
+  #define TU_LOG_FAILED()
+#endif
+
+// TODO replace all TU_LOGn with TU_LOG(n)
+
+#define TU_LOG0(...)
+#define TU_LOG0_MEM(...)
+#define TU_LOG0_VAR(...)
+#define TU_LOG0_INT(...)
+#define TU_LOG0_HEX(...)
+
+#ifndef TU_LOG1
+  #define TU_LOG1(...)
+  #define TU_LOG1_MEM(...)
+  #define TU_LOG1_VAR(...)
+  #define TU_LOG1_INT(...)
+  #define TU_LOG1_HEX(...)
+#endif
+
+#ifndef TU_LOG2
+  #define TU_LOG2(...)
+  #define TU_LOG2_MEM(...)
+  #define TU_LOG2_VAR(...)
+  #define TU_LOG2_INT(...)
+  #define TU_LOG2_HEX(...)
+#endif
+
+#ifndef TU_LOG3
+  #define TU_LOG3(...)
+  #define TU_LOG3_MEM(...)
+  #define TU_LOG3_VAR(...)
+  #define TU_LOG3_INT(...)
+  #define TU_LOG3_HEX(...)
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_DEBUG_H_ */
diff --git a/src/common/tusb_error.h b/src/common/tusb_error.h
deleted file mode 100644
index 42541acd6..000000000
--- a/src/common/tusb_error.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/** \ingroup Group_Common
- *  \defgroup Group_Error Error Codes
- *  @{ */
-
-#ifndef _TUSB_ERRORS_H_
-#define _TUSB_ERRORS_H_
-
-#include "tusb_option.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define ERROR_ENUM(x) x,
-#define ERROR_STRING(x) #x,
-
-#define ERROR_TABLE(ENTRY) \
-    ENTRY(TUSB_ERROR_NONE                            )\
-    ENTRY(TUSB_ERROR_INVALID_PARA                    )\
-    ENTRY(TUSB_ERROR_DEVICE_NOT_READY                )\
-    ENTRY(TUSB_ERROR_INTERFACE_IS_BUSY               )\
-    ENTRY(TUSB_ERROR_HCD_OPEN_PIPE_FAILED            )\
-    ENTRY(TUSB_ERROR_OSAL_TIMEOUT                    )\
-    ENTRY(TUSB_ERROR_CDCH_DEVICE_NOT_MOUNTED         )\
-    ENTRY(TUSB_ERROR_MSCH_DEVICE_NOT_MOUNTED         )\
-    ENTRY(TUSB_ERROR_NOT_SUPPORTED                   )\
-    ENTRY(TUSB_ERROR_NOT_ENOUGH_MEMORY               )\
-    ENTRY(TUSB_ERROR_FAILED                          )\
-
-/// \brief Error Code returned
-/// TODO obsolete and to be remove
-typedef enum
-{
-  ERROR_TABLE(ERROR_ENUM)
-  TUSB_ERROR_COUNT
-}tusb_error_t;
-
-#if CFG_TUSB_DEBUG
-/// Enum to String for debugging purposes. Only available if \ref CFG_TUSB_DEBUG > 0
-extern char const* const tusb_strerr[TUSB_ERROR_COUNT];
-extern char const* const tusb_speed_str[];
-
-#endif
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_ERRORS_H_ */
-
-/**  @} */
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 8fef11dc7..f4a08ce2f 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -74,10 +74,8 @@
 
 #if CFG_TUSB_DEBUG
   #include <stdio.h>
-  #define _MESS_ERR(_err)   tu_printf("%s %d: failed, error = %s\r\n", __func__, __LINE__, tusb_strerr[_err])
   #define _MESS_FAILED()    tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__)
 #else
-  #define _MESS_ERR(_err) do {} while (0)
   #define _MESS_FAILED() do {} while (0)
 #endif
 
@@ -144,32 +142,6 @@
 #define TU_ASSERT(...)             GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS,UNUSED)(__VA_ARGS__)
 #endif
 
-// TODO remove TU_ASSERT_ERR() later
-
-/*------------- Generator for TU_VERIFY_ERR and TU_VERIFY_ERR_HDLR -------------*/
-#define TU_VERIFY_ERR_DEF2(_error, _handler)  do               \
-{                                                              \
-  uint32_t _err = (uint32_t)(_error);                          \
-  if ( 0 != _err ) { _MESS_ERR(_err); _handler; return _err; } \
-} while(0)
-
-#define TU_VERIFY_ERR_DEF3(_error, _handler, _ret) do          \
-{                                                              \
-  uint32_t _err = (uint32_t)(_error);                          \
-  if ( 0 != _err ) { _MESS_ERR(_err); _handler; return _ret; } \
-} while(0)
-
-/*------------------------------------------------------------------*/
-/* ASSERT Error
- * basically TU_VERIFY Error with TU_BREAKPOINT() as handler
- *------------------------------------------------------------------*/
-#define ASSERT_ERR_1ARGS(_error)         TU_VERIFY_ERR_DEF2(_error, TU_BREAKPOINT())
-#define ASSERT_ERR_2ARGS(_error, _ret)   TU_VERIFY_ERR_DEF3(_error, TU_BREAKPOINT(), _ret)
-
-#ifndef TU_ASSERT_ERR
-#define TU_ASSERT_ERR(...)         GET_3RD_ARG(__VA_ARGS__, ASSERT_ERR_2ARGS, ASSERT_ERR_1ARGS,UNUSED)(__VA_ARGS__)
-#endif
-
 /*------------------------------------------------------------------*/
 /* ASSERT HDLR
  *------------------------------------------------------------------*/
diff --git a/src/device/usbd.c b/src/device/usbd.c
index b14b5e0fc..fc66f83c6 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -315,23 +315,6 @@ static char const* const _usbd_event_str[DCD_EVENT_COUNT] =
   "Func Call"
 };
 
-static char const* const _tusb_std_request_str[] =
-{
-  "Get Status"        ,
-  "Clear Feature"     ,
-  "Reserved"          ,
-  "Set Feature"       ,
-  "Reserved"          ,
-  "Set Address"       ,
-  "Get Descriptor"    ,
-  "Set Descriptor"    ,
-  "Get Configuration" ,
-  "Set Configuration" ,
-  "Get Interface"     ,
-  "Set Interface"     ,
-  "Synch Frame"
-};
-
 // for usbd_control to print the name of control complete driver
 void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
 {
@@ -508,7 +491,7 @@ void tud_task (void)
     switch ( event.event_id )
     {
       case DCD_EVENT_BUS_RESET:
-        TU_LOG2(": %s Speed\r\n", tusb_speed_str[event.bus_reset.speed]);
+        TU_LOG2(": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]);
         usbd_reset(event.rhport);
         _usbd_dev.speed = event.bus_reset.speed;
       break;
@@ -650,7 +633,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
 #if CFG_TUSB_DEBUG >= 2
   if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME)
   {
-    TU_LOG2("  %s", _tusb_std_request_str[p_request->bRequest]);
+    TU_LOG2("  %s", tu_str_std_request[p_request->bRequest]);
     if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG2("\r\n");
   }
 #endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 59fcb4da3..5d167408a 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -259,6 +259,7 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
 
 // from usbh_control.c
+extern bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
 extern bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
 //--------------------------------------------------------------------+
@@ -297,6 +298,16 @@ void osal_task_delay(uint32_t msec)
 }
 #endif
 
+
+bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
+{
+  TU_LOG2("[%u:%u] %s: ", usbh_get_rhport(dev_addr), dev_addr, request->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[request->bRequest] : "Unknown Request");
+  TU_LOG2_VAR(request);
+  TU_LOG2("\r\n");
+
+  return usbh_control_xfer(dev_addr, request, buffer, complete_cb);
+}
+
 //--------------------------------------------------------------------+
 // Descriptors
 //--------------------------------------------------------------------+
@@ -864,7 +875,7 @@ static bool enum_new_device(hcd_event_t* event)
     if ( !hcd_port_connect_status(_dev0.rhport) ) return true;
 
     _dev0.speed = hcd_port_speed_get(_dev0.rhport );
-    TU_LOG2("%s Speed\r\n", tusb_speed_str[_dev0.speed]);
+    TU_LOG2("%s Speed\r\n", tu_str_speed[_dev0.speed]);
 
     enum_request_addr0_device_desc();
   }
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index d034eec7f..5f4fcf52f 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -33,6 +33,7 @@
 
 enum
 {
+  STAGE_IDLE,
   STAGE_SETUP,
   STAGE_DATA,
   STAGE_ACK
@@ -56,7 +57,7 @@ static usbh_control_xfer_t _ctrl_xfer;
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
-bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
+bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
 {
   // TODO need to claim the endpoint first
   const uint8_t rhport = usbh_get_rhport(dev_addr);
@@ -66,10 +67,6 @@ bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
   _ctrl_xfer.stage       = STAGE_SETUP;
   _ctrl_xfer.complete_cb = complete_cb;
 
-  TU_LOG2("Control Setup (addr = %u): ", dev_addr);
-  TU_LOG2_VAR(request);
-  TU_LOG2("\r\n");
-
   // Send setup packet
   TU_ASSERT( hcd_setup_send(rhport, dev_addr, (uint8_t const*) &_ctrl_xfer.request) );
 
diff --git a/src/tusb.c b/src/tusb.c
index a30221059..c6c04262c 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -161,9 +161,27 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf,
 #if CFG_TUSB_DEBUG
 #include <ctype.h>
 
-char const* const tusb_strerr[TUSB_ERROR_COUNT] = { ERROR_TABLE(ERROR_STRING) };
+#if CFG_TUSB_DEBUG >= 2
 
-char const* const tusb_speed_str[] = { "Full", "Low", "High" };
+char const* const tu_str_speed[] = { "Full", "Low", "High" };
+char const* const tu_str_std_request[] =
+{
+  "Get Status"        ,
+  "Clear Feature"     ,
+  "Reserved"          ,
+  "Set Feature"       ,
+  "Reserved"          ,
+  "Set Address"       ,
+  "Get Descriptor"    ,
+  "Set Descriptor"    ,
+  "Get Configuration" ,
+  "Set Configuration" ,
+  "Get Interface"     ,
+  "Set Interface"     ,
+  "Synch Frame"
+};
+
+#endif
 
 static void dump_str_line(uint8_t const* buf, uint16_t count)
 {

From a5fb20533cc1c9e0ed155083c1bbcb3e7be75e67 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Mar 2022 17:17:27 +0700
Subject: [PATCH 0880/2085] adding tusb_private.h to implement common edpt
 claim

---
 src/common/tusb_common.h  | 13 ---------
 src/common/tusb_private.h | 61 +++++++++++++++++++++++++++++++++++++++
 src/device/usbd.c         |  4 +++
 src/host/usbh.c           | 41 +++++++++-----------------
 src/tusb.c                | 25 ++++++++++++++++
 src/tusb.h                |  4 ---
 6 files changed, 104 insertions(+), 44 deletions(-)
 create mode 100644 src/common/tusb_private.h

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 34f3bb8f7..58591f0be 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -75,19 +75,6 @@
 
 #include "tusb_timeout.h" // TODO remove
 
-//--------------------------------------------------------------------+
-// Internal Helper used by Host and Device Stack
-//--------------------------------------------------------------------+
-
-// Check if endpoint descriptor is valid per USB specs
-bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed);
-
-// Bind all endpoint of a interface descriptor to class driver
-void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
-
-// Calculate total length of n interfaces (depending on IAD)
-uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len);
-
 //--------------------------------------------------------------------+
 // Internal Inline Functions
 //--------------------------------------------------------------------+
diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
new file mode 100644
index 000000000..5315c352f
--- /dev/null
+++ b/src/common/tusb_private.h
@@ -0,0 +1,61 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef _TUSB_PRIVATE_H_
+#define _TUSB_PRIVATE_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+typedef struct TU_ATTR_PACKED
+{
+  volatile uint8_t busy    : 1;
+  volatile uint8_t stalled : 1;
+  volatile uint8_t claimed : 1;
+}tu_edpt_state_t;
+
+//--------------------------------------------------------------------+
+// Internal Helper used by Host and Device Stack
+//--------------------------------------------------------------------+
+
+// Check if endpoint descriptor is valid per USB specs
+bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed);
+
+// Bind all endpoint of a interface descriptor to class driver
+void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
+
+// Calculate total length of n interfaces (depending on IAD)
+uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len);
+
+bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_PRIVATE_H_ */
diff --git a/src/device/usbd.c b/src/device/usbd.c
index fc66f83c6..4b37e8bd9 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -29,6 +29,8 @@
 #if CFG_TUD_ENABLED
 
 #include "tusb.h"
+#include "common/tusb_private.h"
+
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
 #include "device/dcd.h"
@@ -70,6 +72,8 @@ typedef struct
   uint8_t itf2drv[16];     // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid )
 
+  // TODO 4-bit should be sufficient for ep2drv if we want to save half its bytes
+
   struct TU_ATTR_PACKED
   {
     volatile bool busy    : 1;
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 5d167408a..319031f5b 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -29,6 +29,8 @@
 #if CFG_TUH_ENABLED
 
 #include "tusb.h"
+#include "common/tusb_private.h"
+
 #include "host/usbh.h"
 #include "host/usbh_classdriver.h"
 #include "hub.h"
@@ -104,14 +106,7 @@ typedef struct {
   uint8_t itf2drv[CFG_TUH_INTERFACE_MAX];  // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUH_ENDPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid )
 
-  struct TU_ATTR_PACKED
-  {
-    volatile bool busy    : 1;
-    volatile bool stalled : 1;
-    volatile bool claimed : 1;
-
-    // TODO merge ep2drv here, 4-bit should be sufficient
-  }ep_status[CFG_TUH_ENDPOINT_MAX][2];
+  tu_edpt_state_t ep_status[CFG_TUH_ENDPOINT_MAX][2];
 } usbh_device_t;
 
 
@@ -1189,25 +1184,19 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
 // TODO has some duplication code with device, refactor later
 bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
 {
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  // addr0 is always available
+  if (dev_addr == 0) return true;
 
-  usbh_device_t* dev = get_device(dev_addr);
+  usbh_device_t* dev        = get_device(dev_addr);
+  uint8_t const epnum       = tu_edpt_number(ep_addr);
+  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
-  // pre-check to help reducing mutex lock
-  TU_VERIFY((dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 0));
-  lock_device(dev_addr);
-
-  // can only claim the endpoint if it is not busy and not claimed yet.
-  bool const ret = (dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 0);
-  if (ret)
-  {
-    dev->ep_status[epnum][dir].claimed = 1;
-  }
-
-  unlock_device(dev_addr);
-
-  return ret;
+#if TUSB_OPT_MUTEX
+  return tu_edpt_claim(ep_state, &_usbh_mutex[dev_addr-1]);
+#else
+  return tu_edpt_claim(ep_state, NULL);
+#endif
 }
 
 // TODO has some duplication code with device, refactor later
@@ -1299,6 +1288,4 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
   return dev->ep_status[epnum][dir].busy;
 }
 
-
-
 #endif
diff --git a/src/tusb.c b/src/tusb.c
index c6c04262c..6ed2a3c05 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -29,6 +29,7 @@
 #if CFG_TUH_ENABLED || CFG_TUD_ENABLED
 
 #include "tusb.h"
+#include "common/tusb_private.h"
 
 // TODO clean up
 #if CFG_TUD_ENABLED
@@ -67,6 +68,30 @@ bool tusb_inited(void)
 // Internal Helper for both Host and Device stack
 //--------------------------------------------------------------------+
 
+bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
+{
+  (void) mutex;
+
+#if TUSB_OPT_MUTEX
+  // pre-check to help reducing mutex lock
+  TU_VERIFY((ep_state->busy == 0) && (ep_state->claimed == 0));
+  osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+#endif
+
+  // can only claim the endpoint if it is not busy and not claimed yet.
+  bool const available = (ep_state->busy == 0) && (ep_state->claimed == 0);
+  if (available)
+  {
+    ep_state->claimed = 1;
+  }
+
+#if TUSB_OPT_MUTEX
+  osal_mutex_unlock(mutex);
+#endif
+
+  return available;
+}
+
 bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed)
 {
   uint16_t const max_packet_size = tu_edpt_packet_size(desc_ep);
diff --git a/src/tusb.h b/src/tusb.h
index 549f00b43..222855fcb 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -117,8 +117,6 @@
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
-/** \ingroup group_application_api
- *  @{ */
 
 // Initialize device/host stack
 // Note: when using with RTOS, this should be called after scheduler/kernel is started.
@@ -131,8 +129,6 @@ bool tusb_inited(void);
 // TODO
 // bool tusb_teardown(void);
 
-/** @} */
-
 #ifdef __cplusplus
  }
 #endif

From 110879074f3785c07bf3f125e26a2bbaa51897e4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Mar 2022 17:26:55 +0700
Subject: [PATCH 0881/2085] implement tu_edpt_release()

---
 src/common/tusb_private.h |  4 ++++
 src/host/usbh.c           | 26 +++++++++++---------------
 src/tusb.c                | 22 ++++++++++++++++++++++
 3 files changed, 37 insertions(+), 15 deletions(-)

diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
index 5315c352f..b34506f65 100644
--- a/src/common/tusb_private.h
+++ b/src/common/tusb_private.h
@@ -52,8 +52,12 @@ void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* p_des
 // Calculate total length of n interfaces (depending on IAD)
 uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len);
 
+// Claim an endpoint with provided mutex
 bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
 
+// Release an endpoint with provided mutex
+bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 319031f5b..8206c06a4 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1202,23 +1202,19 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
 // TODO has some duplication code with device, refactor later
 bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
 {
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  // addr0 is always available
+  if (dev_addr == 0) return true;
 
-  usbh_device_t* dev = get_device(dev_addr);
+  usbh_device_t* dev        = get_device(dev_addr);
+  uint8_t const epnum       = tu_edpt_number(ep_addr);
+  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
-  lock_device(dev_addr);
-
-  // can only release the endpoint if it is claimed and not busy
-  bool const ret = (dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 1);
-  if (ret)
-  {
-    dev->ep_status[epnum][dir].claimed = 0;
-  }
-
-  unlock_device(dev_addr);
-
-  return ret;
+#if TUSB_OPT_MUTEX
+  return tu_edpt_release(ep_state, &_usbh_mutex[dev_addr-1]);
+#else
+  return tu_edpt_release(ep_state, NULL);
+#endif
 }
 
 // TODO has some duplication code with device, refactor later
diff --git a/src/tusb.c b/src/tusb.c
index 6ed2a3c05..c86bdd891 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -92,6 +92,28 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
   return available;
 }
 
+bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
+{
+  (void) mutex;
+
+#if TUSB_OPT_MUTEX
+  osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+#endif
+
+  // can only release the endpoint if it is claimed and not busy
+  bool const ret = (ep_state->claimed == 1) && (ep_state->busy == 0);
+  if (ret)
+  {
+    ep_state->claimed = 0;
+  }
+
+#if TUSB_OPT_MUTEX
+  osal_mutex_unlock(mutex);
+#endif
+
+  return ret;
+}
+
 bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed)
 {
   uint16_t const max_packet_size = tu_edpt_packet_size(desc_ep);

From d56cde33ef66985b5d3cb087f87cf8bc1a2b111d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Mar 2022 17:34:12 +0700
Subject: [PATCH 0882/2085] refactor usbd to also use common endpoint
 claim/release

---
 src/device/usbd.c | 65 +++++++++++++----------------------------------
 src/host/usbh.c   |  7 ++---
 2 files changed, 21 insertions(+), 51 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 4b37e8bd9..7ab2660f4 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -69,19 +69,10 @@ typedef struct
   volatile uint8_t cfg_num; // current active configuration (0x00 is not configured)
   uint8_t speed;
 
-  uint8_t itf2drv[16];     // map interface number to driver (0xff is invalid)
-  uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid )
+  uint8_t itf2drv[16];                      // map interface number to driver (0xff is invalid)
+  uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid ), can use only 4-bit each
 
-  // TODO 4-bit should be sufficient for ep2drv if we want to save half its bytes
-
-  struct TU_ATTR_PACKED
-  {
-    volatile bool busy    : 1;
-    volatile bool stalled : 1;
-    volatile bool claimed : 1;
-
-    // TODO merge ep2drv here, 4-bit should be sufficient
-  }ep_status[CFG_TUD_ENDPPOINT_MAX][2];
+  tu_edpt_state_t ep_status[CFG_TUD_ENDPPOINT_MAX][2];
 
 }usbd_device_t;
 
@@ -1229,52 +1220,30 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr)
   // TODO add this check later, also make sure we don't starve an out endpoint while suspending
   // TU_VERIFY(tud_ready());
 
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const epnum       = tu_edpt_number(ep_addr);
+  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir];
 
-#if CFG_TUSB_OS != OPT_OS_NONE
-  // pre-check to help reducing mutex lock
-  TU_VERIFY((_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0));
-  osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+#if TUSB_OPT_MUTEX
+  return tu_edpt_claim(ep_state, _usbd_mutex);
+#else
+  return tu_edpt_claim(ep_state, NULL);
 #endif
-
-  // can only claim the endpoint if it is not busy and not claimed yet.
-  bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0);
-  if (ret)
-  {
-    _usbd_dev.ep_status[epnum][dir].claimed = 1;
-  }
-
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_unlock(_usbd_mutex);
-#endif
-
-  return ret;
 }
 
 bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
 
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const epnum       = tu_edpt_number(ep_addr);
+  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir];
 
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+#if TUSB_OPT_MUTEX
+  return tu_edpt_release(ep_state, _usbd_mutex);
+#else
+  return tu_edpt_release(ep_state, NULL);
 #endif
-
-  // can only release the endpoint if it is claimed and not busy
-  bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 1);
-  if (ret)
-  {
-    _usbd_dev.ep_status[epnum][dir].claimed = 0;
-  }
-
-#if CFG_TUSB_OS != OPT_OS_NONE
-  osal_mutex_unlock(_usbd_mutex);
-#endif
-
-  return ret;
 }
 
 bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 8206c06a4..69ec081fd 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -104,9 +104,10 @@ typedef struct {
   volatile uint8_t state;            // device state, value from enum tusbh_device_state_t
 
   uint8_t itf2drv[CFG_TUH_INTERFACE_MAX];  // map interface number to driver (0xff is invalid)
-  uint8_t ep2drv[CFG_TUH_ENDPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid )
+  uint8_t ep2drv[CFG_TUH_ENDPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid ), can use only 4-bit each
 
   tu_edpt_state_t ep_status[CFG_TUH_ENDPOINT_MAX][2];
+
 } usbh_device_t;
 
 
@@ -1193,7 +1194,7 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
   tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
 #if TUSB_OPT_MUTEX
-  return tu_edpt_claim(ep_state, &_usbh_mutex[dev_addr-1]);
+  return tu_edpt_claim(ep_state, _usbh_mutex[dev_addr-1]);
 #else
   return tu_edpt_claim(ep_state, NULL);
 #endif
@@ -1211,7 +1212,7 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
   tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
 #if TUSB_OPT_MUTEX
-  return tu_edpt_release(ep_state, &_usbh_mutex[dev_addr-1]);
+  return tu_edpt_release(ep_state, _usbh_mutex[dev_addr-1]);
 #else
   return tu_edpt_release(ep_state, NULL);
 #endif

From 0e5e644d27a722f7a95fcd5f049770094fb02cd6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Mar 2022 17:51:35 +0700
Subject: [PATCH 0883/2085] minor clean up

---
 src/host/usbh.c         | 2 +-
 src/host/usbh_control.c | 8 +++-----
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 69ec081fd..808ef1299 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -561,7 +561,7 @@ void tuh_task(void)
         else
         {
           usbh_device_t* dev = get_device(event.dev_addr);
-          dev->ep_status[epnum][ep_dir].busy = false;
+          dev->ep_status[epnum][ep_dir].busy    = 0;
           dev->ep_status[epnum][ep_dir].claimed = 0;
 
           if ( 0 == epnum )
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index 5f4fcf52f..f311cc257 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -50,9 +50,6 @@ typedef struct
 
 static usbh_control_xfer_t _ctrl_xfer;
 
-//CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
-//static uint8_t _tuh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
@@ -76,6 +73,7 @@ bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
 static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
 {
   TU_LOG2("\r\n");
+  _ctrl_xfer.stage = STAGE_IDLE;
   if (_ctrl_xfer.complete_cb) _ctrl_xfer.complete_cb(dev_addr, &_ctrl_xfer.request, result);
 }
 
@@ -90,7 +88,7 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
 
   if (XFER_RESULT_SUCCESS != result)
   {
-    TU_LOG2("Control failed: result = %d\r\n", result);
+    TU_LOG2("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED");
 
     // terminate transfer if any stage failed
     _xfer_complete(dev_addr, result);
@@ -113,7 +111,7 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
 
         if (request->wLength)
         {
-          TU_LOG2("Control data (addr = %u):\r\n", dev_addr);
+          TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
           TU_LOG2_MEM(_ctrl_xfer.buffer, request->wLength, 2);
         }
 

From 97636eff8e855c1f901477ca7914c0eca5024432 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Mar 2022 00:36:49 +0700
Subject: [PATCH 0884/2085] more clean up

---
 src/host/usbh.c | 251 ++++++++++++++++++++++--------------------------
 1 file changed, 115 insertions(+), 136 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 808ef1299..aec97cf2a 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -65,10 +65,10 @@ typedef struct
 
   struct TU_ATTR_PACKED
   {
-    volatile uint8_t connected    : 1;
-    volatile uint8_t addressed    : 1;
-    volatile uint8_t configured   : 1;
-    volatile uint8_t suspended    : 1;
+    volatile uint8_t connected  : 1;
+    volatile uint8_t addressed  : 1;
+    volatile uint8_t configured : 1;
+    volatile uint8_t suspended  : 1;
   };
 } usbh_dev0_t;
 
@@ -81,10 +81,10 @@ typedef struct {
 
   struct TU_ATTR_PACKED
   {
-    volatile uint8_t connected    : 1;
-    volatile uint8_t addressed    : 1;
-    volatile uint8_t configured   : 1;
-    volatile uint8_t suspended    : 1;
+    volatile uint8_t connected  : 1;
+    volatile uint8_t addressed  : 1;
+    volatile uint8_t configured : 1;
+    volatile uint8_t suspended  : 1;
   };
 
   //------------- device descriptor -------------//
@@ -208,29 +208,8 @@ CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[TOTAL_DEVICES];
 
 // Mutex for claiming endpoint, only needed when using with preempted RTOS
 #if TUSB_OPT_MUTEX
-
 static osal_mutex_def_t _usbh_mutexdef[TOTAL_DEVICES];
 static osal_mutex_t _usbh_mutex[TOTAL_DEVICES];
-
-static inline void lock_device(uint8_t daddr)
-{
-  // addr0 is always available
-  if (daddr) return;
-  osal_mutex_lock(&_usbh_mutex[daddr-1], OSAL_TIMEOUT_WAIT_FOREVER);
-}
-
-static inline void unlock_device(uint8_t daddr)
-{
-  // addr0 is always available
-  if (daddr) return;
-  osal_mutex_unlock(&_usbh_mutex[daddr-1]);
-}
-
-#else
-
-#define lock_device(_addr)
-#define unlock_device(_addr)
-
 #endif
 
 // Event queue
@@ -769,6 +748,113 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
   }
 }
 
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
+{
+  // addr0 is always available
+  if (dev_addr == 0) return true;
+
+  usbh_device_t* dev        = get_device(dev_addr);
+  uint8_t const epnum       = tu_edpt_number(ep_addr);
+  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
+
+#if TUSB_OPT_MUTEX
+  return tu_edpt_claim(ep_state, _usbh_mutex[dev_addr-1]);
+#else
+  return tu_edpt_claim(ep_state, NULL);
+#endif
+}
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
+{
+  // addr0 is always available
+  if (dev_addr == 0) return true;
+
+  usbh_device_t* dev        = get_device(dev_addr);
+  uint8_t const epnum       = tu_edpt_number(ep_addr);
+  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
+
+#if TUSB_OPT_MUTEX
+  return tu_edpt_release(ep_state, _usbh_mutex[dev_addr-1]);
+#else
+  return tu_edpt_release(ep_state, NULL);
+#endif
+}
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  usbh_device_t* dev = get_device(dev_addr);
+
+  TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
+
+  // Attempt to transfer on a busy endpoint, sound like an race condition !
+  TU_ASSERT(dev->ep_status[epnum][dir].busy == 0);
+
+  // Set busy first since the actual transfer can be complete before hcd_edpt_xfer()
+  // could return and USBH task can preempt and clear the busy
+  dev->ep_status[epnum][dir].busy = true;
+
+  if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
+  {
+    TU_LOG2("OK\r\n");
+    return true;
+  }else
+  {
+    // HCD error, mark endpoint as ready to allow next transfer
+    dev->ep_status[epnum][dir].busy = false;
+    dev->ep_status[epnum][dir].claimed = 0;
+    TU_LOG2("failed\r\n");
+    TU_BREAKPOINT();
+    return false;
+  }
+}
+
+static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
+{
+  TU_LOG2("Open EP0 with Size = %u (addr = %u)\r\n", max_packet_size, dev_addr);
+
+  tusb_desc_endpoint_t ep0_desc =
+  {
+    .bLength          = sizeof(tusb_desc_endpoint_t),
+    .bDescriptorType  = TUSB_DESC_ENDPOINT,
+    .bEndpointAddress = 0,
+    .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
+    .wMaxPacketSize   = max_packet_size,
+    .bInterval        = 0
+  };
+
+  return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc);
+}
+
+bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
+{
+  usbh_device_t* dev = get_device(dev_addr);
+  TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) dev->speed));
+
+  return hcd_edpt_open(rhport, dev_addr, desc_ep);
+}
+
+bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  usbh_device_t* dev = get_device(dev_addr);
+
+  return dev->ep_status[epnum][dir].busy;
+}
+
 //--------------------------------------------------------------------+
 // Enumeration Process
 // is a lengthy process with a series of control transfer to configure
@@ -1178,111 +1264,4 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
   return true;
 }
 
-//--------------------------------------------------------------------+
-// Endpoint API
-//--------------------------------------------------------------------+
-
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
-{
-  // addr0 is always available
-  if (dev_addr == 0) return true;
-
-  usbh_device_t* dev        = get_device(dev_addr);
-  uint8_t const epnum       = tu_edpt_number(ep_addr);
-  uint8_t const dir         = tu_edpt_dir(ep_addr);
-  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
-
-#if TUSB_OPT_MUTEX
-  return tu_edpt_claim(ep_state, _usbh_mutex[dev_addr-1]);
-#else
-  return tu_edpt_claim(ep_state, NULL);
-#endif
-}
-
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
-{
-  // addr0 is always available
-  if (dev_addr == 0) return true;
-
-  usbh_device_t* dev        = get_device(dev_addr);
-  uint8_t const epnum       = tu_edpt_number(ep_addr);
-  uint8_t const dir         = tu_edpt_dir(ep_addr);
-  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
-
-#if TUSB_OPT_MUTEX
-  return tu_edpt_release(ep_state, _usbh_mutex[dev_addr-1]);
-#else
-  return tu_edpt_release(ep_state, NULL);
-#endif
-}
-
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  usbh_device_t* dev = get_device(dev_addr);
-
-  TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
-
-  // Attempt to transfer on a busy endpoint, sound like an race condition !
-  TU_ASSERT(dev->ep_status[epnum][dir].busy == 0);
-
-  // Set busy first since the actual transfer can be complete before hcd_edpt_xfer()
-  // could return and USBH task can preempt and clear the busy
-  dev->ep_status[epnum][dir].busy = true;
-
-  if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
-  {
-    TU_LOG2("OK\r\n");
-    return true;
-  }else
-  {
-    // HCD error, mark endpoint as ready to allow next transfer
-    dev->ep_status[epnum][dir].busy = false;
-    dev->ep_status[epnum][dir].claimed = 0;
-    TU_LOG2("failed\r\n");
-    TU_BREAKPOINT();
-    return false;
-  }
-}
-
-static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
-{
-  TU_LOG2("Open EP0 with Size = %u (addr = %u)\r\n", max_packet_size, dev_addr);
-
-  tusb_desc_endpoint_t ep0_desc =
-  {
-    .bLength          = sizeof(tusb_desc_endpoint_t),
-    .bDescriptorType  = TUSB_DESC_ENDPOINT,
-    .bEndpointAddress = 0,
-    .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-    .wMaxPacketSize   = max_packet_size,
-    .bInterval        = 0
-  };
-
-  return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc);
-}
-
-bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
-{
-  usbh_device_t* dev = get_device(dev_addr);
-  TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) dev->speed));
-
-  return hcd_edpt_open(rhport, dev_addr, desc_ep);
-}
-
-bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  usbh_device_t* dev = get_device(dev_addr);
-
-  return dev->ep_status[epnum][dir].busy;
-}
-
 #endif

From 22f682c37879a38aa662c2205d411b2246d0639c Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Wed, 9 Mar 2022 15:22:31 -0800
Subject: [PATCH 0885/2085] Add host example that prints out info of connected
 devices

---
 examples/host/device_info/CMakeLists.txt    |  27 +++
 examples/host/device_info/Makefile          |  28 ++++
 examples/host/device_info/only.txt          |   9 +
 examples/host/device_info/src/main.c        | 175 ++++++++++++++++++++
 examples/host/device_info/src/tusb_config.h |  96 +++++++++++
 5 files changed, 335 insertions(+)
 create mode 100644 examples/host/device_info/CMakeLists.txt
 create mode 100644 examples/host/device_info/Makefile
 create mode 100644 examples/host/device_info/only.txt
 create mode 100644 examples/host/device_info/src/main.c
 create mode 100644 examples/host/device_info/src/tusb_config.h

diff --git a/examples/host/device_info/CMakeLists.txt b/examples/host/device_info/CMakeLists.txt
new file mode 100644
index 000000000..bff281a8c
--- /dev/null
+++ b/examples/host/device_info/CMakeLists.txt
@@ -0,0 +1,27 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/host/device_info/Makefile b/examples/host/device_info/Makefile
new file mode 100644
index 000000000..c59369ffa
--- /dev/null
+++ b/examples/host/device_info/Makefile
@@ -0,0 +1,28 @@
+include ../../../tools/top.mk
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += \
+	src/main.c
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+# TODO: suppress warning caused by host stack
+CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
+
+# TinyUSB Host Stack source
+SRC_C += \
+	src/class/cdc/cdc_host.c \
+	src/class/hid/hid_host.c \
+	src/class/msc/msc_host.c \
+	src/host/hub.c \
+	src/host/usbh.c \
+	src/host/usbh_control.c \
+	src/portable/ohci/ohci.c \
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+
+include ../../rules.mk
diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt
new file mode 100644
index 000000000..7fe4e3f5c
--- /dev/null
+++ b/examples/host/device_info/only.txt
@@ -0,0 +1,9 @@
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MIMXRT10XX
+mcu:RP2040
+mcu:MSP432E4
+mcu:RX65X
diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c
new file mode 100644
index 000000000..45b616af0
--- /dev/null
+++ b/examples/host/device_info/src/main.c
@@ -0,0 +1,175 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Scott Shawcroft for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* This example prints out info about the enumerated devices. */
+
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+void led_blinking_task(void);
+
+static xfer_result_t _get_string_result;
+
+static bool _transfer_done_cb(uint8_t daddr, tusb_control_request_t const *request, xfer_result_t result) {
+    (void)daddr;
+    (void)request;
+    _get_string_result = result;
+    return true;
+}
+
+static void _convert_utf16le_to_utf8(const uint16_t *utf16, size_t utf16_len, uint8_t *utf8, size_t utf8_len) {
+    // TODO: Check for runover.
+    (void)utf8_len;
+    // Get the UTF-16 length out of the data itself.
+
+    for (size_t i = 0; i < utf16_len; i++) {
+        uint16_t chr = utf16[i];
+        if (chr < 0x80) {
+            *utf8++ = chr & 0xff;
+        } else if (chr < 0x800) {
+            *utf8++ = (uint8_t)(0xC0 | (chr >> 6 & 0x1F));
+            *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
+        } else {
+            // TODO: Verify surrogate.
+            *utf8++ = (uint8_t)(0xE0 | (chr >> 12 & 0x0F));
+            *utf8++ = (uint8_t)(0x80 | (chr >> 6 & 0x3F));
+            *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
+        }
+        // TODO: Handle UTF-16 code points that take two entries.
+    }
+}
+
+// Count how many bytes a utf-16-le encoded string will take in utf-8.
+static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
+    size_t total_bytes = 0;
+    for (size_t i = 0; i < len; i++) {
+        uint16_t chr = buf[i];
+        if (chr < 0x80) {
+            total_bytes += 1;
+        } else if (chr < 0x800) {
+            total_bytes += 2;
+        } else {
+            total_bytes += 3;
+        }
+        // TODO: Handle UTF-16 code points that take two entries.
+    }
+    return total_bytes;
+}
+
+static void _wait_and_convert(uint16_t *temp_buf, size_t buf_len) {
+    while (_get_string_result == 0xff) {
+        tuh_task();
+    }
+    size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
+    size_t utf8_len = _count_utf8_bytes(temp_buf + 1, utf16_len);
+    _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
+    ((uint8_t*) temp_buf)[utf8_len] = '\0';
+}
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  printf("TinyUSB Host Device Info Example\r\n");
+
+  tusb_init();
+
+  uint32_t interval_ms = 5000;
+  uint32_t start_time = 0;
+
+  while (1)
+  {
+    // tinyusb host task
+    tuh_task();
+    led_blinking_task();
+
+    if (board_millis() - start_time < interval_ms) {
+      continue;
+    }
+    start_time = board_millis();
+    // Brute force check every device address to see if it is active.
+    for (int i = 1; i < CFG_TUH_DEVICE_MAX + CFG_TUH_HUB + 1; i++) {
+      if (!tuh_ready(i)) {
+        continue;
+      }
+      uint16_t vid;
+      uint16_t pid;
+      tuh_vid_pid_get(i, &vid, &pid);
+      printf("%d vid %04x pid %04x\r\n", i, vid, pid);
+
+      _get_string_result = 0xff;
+      uint16_t temp_buf[127];
+      if (tuh_descriptor_string_serial_get(i, 0, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
+        _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
+        printf("Serial: %s\r\n", (const char*) temp_buf);
+      }
+
+      _get_string_result = 0xff;
+      temp_buf[0] = 0;
+      if (tuh_descriptor_string_product_get(i, 0, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
+        _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
+        printf("Product: %s\r\n", (const char*) temp_buf);
+      }
+
+      _get_string_result = 0xff;
+      temp_buf[0] = 0;
+      if (tuh_descriptor_string_manufacturer_get(i, 0, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
+        _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
+        printf("Manufacturer: %s\r\n", (const char*) temp_buf);
+      }
+    }
+    printf("\n");
+  }
+
+  return 0;
+}
+
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  const uint32_t interval_ms = 1000;
+  static uint32_t start_ms = 0;
+
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  start_ms += interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/host/device_info/src/tusb_config.h b/examples/host/device_info/src/tusb_config.h
new file mode 100644
index 000000000..6b413e46f
--- /dev/null
+++ b/examples/host/device_info/src/tusb_config.h
@@ -0,0 +1,96 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+  #error CFG_TUSB_MCU must be defined
+#endif
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+  #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
+#else
+  #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS                 OPT_OS_NONE
+#endif
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+// only hub class is enabled
+#define CFG_TUH_HUB                 1
+
+// max device support (excluding hub device)
+// 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1)
+
+#define CFG_TUH_ENDPOINT_MAX       8
+
+#define CFG_TUH_TASK_QUEUE_SZ       64
+
+//------------- HID -------------//
+
+#define CFG_TUH_HID_EP_BUFSIZE      64
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */

From b05401a5ab788a9b1a56bdb79b74e49b6909339f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Mar 2022 11:59:51 +0700
Subject: [PATCH 0886/2085] merge control stage host and device value

---
 src/common/tusb_types.h |  1 +
 src/host/usbh_control.c | 22 +++++++---------------
 2 files changed, 8 insertions(+), 15 deletions(-)

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 5b26f5aec..f998eabfb 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -265,6 +265,7 @@ typedef enum
 
 enum
 {
+  CONTROL_STAGE_IDLE,
   CONTROL_STAGE_SETUP,
   CONTROL_STAGE_DATA,
   CONTROL_STAGE_ACK
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index f311cc257..741b0723a 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -31,14 +31,6 @@
 #include "tusb.h"
 #include "usbh_classdriver.h"
 
-enum
-{
-  STAGE_IDLE,
-  STAGE_SETUP,
-  STAGE_DATA,
-  STAGE_ACK
-};
-
 typedef struct
 {
   tusb_control_request_t request TU_ATTR_ALIGNED(4);
@@ -61,7 +53,7 @@ bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
 
   _ctrl_xfer.request     = (*request);
   _ctrl_xfer.buffer      = buffer;
-  _ctrl_xfer.stage       = STAGE_SETUP;
+  _ctrl_xfer.stage       = CONTROL_STAGE_SETUP;
   _ctrl_xfer.complete_cb = complete_cb;
 
   // Send setup packet
@@ -73,7 +65,7 @@ bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
 static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
 {
   TU_LOG2("\r\n");
-  _ctrl_xfer.stage = STAGE_IDLE;
+  _ctrl_xfer.stage = CONTROL_STAGE_IDLE;
   if (_ctrl_xfer.complete_cb) _ctrl_xfer.complete_cb(dev_addr, &_ctrl_xfer.request, result);
 }
 
@@ -96,8 +88,8 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
   {
     switch(_ctrl_xfer.stage)
     {
-      case STAGE_SETUP:
-        _ctrl_xfer.stage = STAGE_DATA;
+      case CONTROL_STAGE_SETUP:
+        _ctrl_xfer.stage = CONTROL_STAGE_DATA;
         if (request->wLength)
         {
           // DATA stage: initial data toggle is always 1
@@ -106,8 +98,8 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
         }
         __attribute__((fallthrough));
 
-      case STAGE_DATA:
-        _ctrl_xfer.stage = STAGE_ACK;
+      case CONTROL_STAGE_DATA:
+        _ctrl_xfer.stage = CONTROL_STAGE_ACK;
 
         if (request->wLength)
         {
@@ -119,7 +111,7 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
         hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
       break;
 
-      case STAGE_ACK:
+      case CONTROL_STAGE_ACK:
         _xfer_complete(dev_addr, result);
       break;
 

From 5e9f522b9ad1c9c9b905101c364d0728d4895d5b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Mar 2022 12:56:15 +0700
Subject: [PATCH 0887/2085] refactor host control xfer

---
 src/host/usbh.c         | 30 +++++++++++++++++++++---------
 src/host/usbh_control.c | 16 ++++++----------
 2 files changed, 27 insertions(+), 19 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index aec97cf2a..9a2bc86a8 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -55,6 +55,7 @@
 //--------------------------------------------------------------------+
 
 // device0 struct must be strictly a subset of normal device struct
+// TODO refactor later
 typedef struct
 {
   // port
@@ -70,6 +71,8 @@ typedef struct
     volatile uint8_t configured : 1;
     volatile uint8_t suspended  : 1;
   };
+
+  uint8_t control_stage;  // state of control transfer
 } usbh_dev0_t;
 
 typedef struct {
@@ -87,12 +90,13 @@ typedef struct {
     volatile uint8_t suspended  : 1;
   };
 
-  //------------- device descriptor -------------//
-  uint8_t  ep0_size;
+  uint8_t control_stage;  // state of control transfer
 
+  //------------- device descriptor -------------//
   uint16_t vid;
   uint16_t pid;
 
+  uint8_t  ep0_size;
   uint8_t  i_manufacturer;
   uint8_t  i_product;
   uint8_t  i_serial;
@@ -234,8 +238,8 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
 
 // from usbh_control.c
-extern bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
-extern bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+extern bool usbh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
+extern uint8_t usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, uint8_t* stage, xfer_result_t result, uint32_t xferred_bytes);
 
 //--------------------------------------------------------------------+
 // PUBLIC API (Parameter Verification is required)
@@ -274,13 +278,21 @@ void osal_task_delay(uint32_t msec)
 #endif
 
 
-bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
+bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
 {
-  TU_LOG2("[%u:%u] %s: ", usbh_get_rhport(dev_addr), dev_addr, request->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[request->bRequest] : "Unknown Request");
+  TU_LOG2("[%u:%u] %s: ", usbh_get_rhport(daddr), daddr, request->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[request->bRequest] : "Unknown Request");
   TU_LOG2_VAR(request);
   TU_LOG2("\r\n");
 
-  return usbh_control_xfer(dev_addr, request, buffer, complete_cb);
+  if (daddr)
+  {
+    get_device(daddr)->control_stage = CONTROL_STAGE_SETUP;
+  }else
+  {
+    _dev0.control_stage = CONTROL_STAGE_SETUP;
+  }
+
+  return usbh_control_xfer(daddr, request, buffer, complete_cb);
 }
 
 //--------------------------------------------------------------------+
@@ -535,7 +547,7 @@ void tuh_task(void)
         {
           // device 0 only has control endpoint
           TU_ASSERT(epnum == 0, );
-          usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+          usbh_control_xfer_cb(event.dev_addr, ep_addr, &_dev0.control_stage, event.xfer_complete.result, event.xfer_complete.len);
         }
         else
         {
@@ -545,7 +557,7 @@ void tuh_task(void)
 
           if ( 0 == epnum )
           {
-            usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+            usbh_control_xfer_cb(event.dev_addr, ep_addr, &dev->control_stage, event.xfer_complete.result, event.xfer_complete.len);
           }else
           {
             uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index 741b0723a..88287a47b 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -34,8 +34,6 @@
 typedef struct
 {
   tusb_control_request_t request TU_ATTR_ALIGNED(4);
-
-  uint8_t stage;
   uint8_t* buffer;
   tuh_control_complete_cb_t complete_cb;
 } usbh_control_xfer_t;
@@ -53,7 +51,6 @@ bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
 
   _ctrl_xfer.request     = (*request);
   _ctrl_xfer.buffer      = buffer;
-  _ctrl_xfer.stage       = CONTROL_STAGE_SETUP;
   _ctrl_xfer.complete_cb = complete_cb;
 
   // Send setup packet
@@ -65,17 +62,15 @@ bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request,
 static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
 {
   TU_LOG2("\r\n");
-  _ctrl_xfer.stage = CONTROL_STAGE_IDLE;
   if (_ctrl_xfer.complete_cb) _ctrl_xfer.complete_cb(dev_addr, &_ctrl_xfer.request, result);
 }
 
-bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, uint8_t* stage, xfer_result_t result, uint32_t xferred_bytes)
 {
   (void) ep_addr;
   (void) xferred_bytes;
 
   const uint8_t rhport = usbh_get_rhport(dev_addr);
-
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
   if (XFER_RESULT_SUCCESS != result)
@@ -83,13 +78,14 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
     TU_LOG2("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED");
 
     // terminate transfer if any stage failed
+    *stage = CONTROL_STAGE_IDLE;
     _xfer_complete(dev_addr, result);
   }else
   {
-    switch(_ctrl_xfer.stage)
+    switch(*stage)
     {
       case CONTROL_STAGE_SETUP:
-        _ctrl_xfer.stage = CONTROL_STAGE_DATA;
+        *stage = CONTROL_STAGE_DATA;
         if (request->wLength)
         {
           // DATA stage: initial data toggle is always 1
@@ -99,8 +95,7 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
         __attribute__((fallthrough));
 
       case CONTROL_STAGE_DATA:
-        _ctrl_xfer.stage = CONTROL_STAGE_ACK;
-
+        *stage = CONTROL_STAGE_ACK;
         if (request->wLength)
         {
           TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
@@ -112,6 +107,7 @@ bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t resu
       break;
 
       case CONTROL_STAGE_ACK:
+        *stage = CONTROL_STAGE_IDLE;
         _xfer_complete(dev_addr, result);
       break;
 

From b9ca301527040458bd369cf967732a76d5139222 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Mar 2022 13:19:15 +0700
Subject: [PATCH 0888/2085] remove obsolete device state

---
 src/common/tusb_types.h |  8 --------
 src/host/hcd.h          |  3 ++-
 src/host/usbh.c         | 36 ++++++++++++++++--------------------
 3 files changed, 18 insertions(+), 29 deletions(-)

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index f998eabfb..da164145b 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -223,14 +223,6 @@ enum {
 
 #define TUSB_DESC_CONFIG_POWER_MA(x)  ((x)/2)
 
-/// Device State TODO remove
-typedef enum
-{
-  TUSB_DEVICE_STATE_UNPLUG = 0  ,
-  TUSB_DEVICE_STATE_CONFIGURED  ,
-  TUSB_DEVICE_STATE_SUSPENDED   ,
-}tusb_device_state_t;
-
 typedef enum
 {
   XFER_RESULT_SUCCESS,
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 9819f5f2a..c40bea64c 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -94,7 +94,8 @@ typedef struct
 
 } hcd_event_t;
 
-typedef struct {
+typedef struct
+{
   uint8_t rhport;
   uint8_t hub_addr;
   uint8_t hub_port;
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 9a2bc86a8..07baeee96 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -82,6 +82,7 @@ typedef struct {
   uint8_t hub_port;
   uint8_t speed;
 
+  // Device State
   struct TU_ATTR_PACKED
   {
     volatile uint8_t connected  : 1;
@@ -92,7 +93,7 @@ typedef struct {
 
   uint8_t control_stage;  // state of control transfer
 
-  //------------- device descriptor -------------//
+  // Device Descriptor
   uint16_t vid;
   uint16_t pid;
 
@@ -101,12 +102,10 @@ typedef struct {
   uint8_t  i_product;
   uint8_t  i_serial;
 
-  //------------- configuration descriptor -------------//
+  // Configuration Descriptor
   // uint8_t interface_count; // bNumInterfaces alias
 
-  //------------- device -------------//
-  volatile uint8_t state;            // device state, value from enum tusbh_device_state_t
-
+  // Endpoint & Interface
   uint8_t itf2drv[CFG_TUH_INTERFACE_MAX];  // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUH_ENDPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid ), can use only 4-bit each
 
@@ -685,9 +684,8 @@ void hcd_event_device_remove(uint8_t hostid, bool in_isr)
 }
 
 
-// a device unplugged on hostid, hub_addr, hub_port
-// return true if found and unmounted device, false if cannot find
-void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
+// a device unplugged from rhport:hub_addr:hub_port
+static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
 {
   //------------- find the all devices (star-network) under port that is unplugged -------------//
   // TODO mark as disconnected in ISR, also handle dev0
@@ -700,7 +698,7 @@ void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port
     if (dev->rhport == rhport   &&
         (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr == 0 & hub_port == 0 means roothub
         (hub_port == 0 || dev->hub_port == hub_port) &&
-        dev->state    != TUSB_DEVICE_STATE_UNPLUG)
+        dev->connected)
     {
       // Invoke callback before close driver
       if (tuh_umount_cb) tuh_umount_cb(dev_addr);
@@ -729,7 +727,7 @@ static uint8_t get_new_address(bool is_hub)
   for (uint8_t i=0; i < count; i++)
   {
     uint8_t const addr = start + i;
-    if (get_device(addr)->state == TUSB_DEVICE_STATE_UNPLUG) return addr;
+    if (!get_device(addr)->connected) return addr;
   }
   return ADDR_INVALID;
 }
@@ -951,17 +949,17 @@ static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request
 
   return true;
 }
-#endif
+#endif // hub
 
 static bool enum_new_device(hcd_event_t* event)
 {
-  _dev0.rhport   = event->rhport; // TODO refractor integrate to device_pool
+  _dev0.rhport   = event->rhport;
   _dev0.hub_addr = event->connection.hub_addr;
   _dev0.hub_port = event->connection.hub_port;
 
-  //------------- connected/disconnected directly with roothub -------------//
   if (_dev0.hub_addr == 0)
   {
+    // connected/disconnected directly with roothub
     // wait until device is stable TODO non blocking
     osal_task_delay(RESET_DELAY);
 
@@ -974,14 +972,14 @@ static bool enum_new_device(hcd_event_t* event)
     enum_request_addr0_device_desc();
   }
 #if CFG_TUH_HUB
-  //------------- connected/disconnected via hub -------------//
   else
   {
+    // connected/disconnected via external hub
     // wait until device is stable
     osal_task_delay(RESET_DELAY);
     TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete) );
   }
-#endif // CFG_TUH_HUB
+#endif // hub
 
   return true;
 }
@@ -994,7 +992,6 @@ static bool enum_request_addr0_device_desc(void)
 
   // Get first 8 bytes of device descriptor for Control Endpoint size
   TU_LOG2("Get 8 byte of Device Descriptor\r\n");
-
   TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, enum_get_addr0_device_desc_complete));
   return true;
 }
@@ -1024,7 +1021,7 @@ static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_r
   if (_dev0.hub_addr == 0)
   {
     // connected directly to roothub
-    hcd_port_reset( _dev0.rhport ); // reset port after 8 byte descriptor
+    hcd_port_reset( _dev0.rhport );
     osal_task_delay(RESET_DELAY);
 
     enum_request_set_addr();
@@ -1040,14 +1037,13 @@ static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_r
 
     TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status1_complete) );
   }
-#endif
+#endif // hub
 
   return true;
 }
 
 static bool enum_request_set_addr(void)
 {
-  uint8_t const addr0 = 0;
   tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
 
   // Get new address
@@ -1079,6 +1075,7 @@ static bool enum_request_set_addr(void)
     .wLength  = 0
   };
 
+  uint8_t const addr0 = 0;
   TU_ASSERT( tuh_control_xfer(addr0, &new_request, NULL, enum_set_address_complete) );
 
   return true;
@@ -1172,7 +1169,6 @@ static bool enum_set_config_complete(uint8_t dev_addr, tusb_control_request_t co
   TU_LOG2("Device configured\r\n");
   usbh_device_t* dev = get_device(dev_addr);
   dev->configured = 1;
-  dev->state = TUSB_DEVICE_STATE_CONFIGURED;
 
   // Start the Set Configuration process for interfaces (itf = DRVID_INVALID)
   // Since driver can perform control transfer within its set_config, this is done asynchronously.

From 171d021ab56960f8d7e222faa263168ead0f9d6a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Mar 2022 22:22:05 +0700
Subject: [PATCH 0889/2085] refactor and integrate usbh control xfer back to
 usbh.c

fix enumeration with hub when reset port before set address
---
 src/device/usbd_pvt.h       |   2 +-
 src/host/usbh.c             | 447 +++++++++++++++++++++++-------------
 src/host/usbh_classdriver.h |   1 +
 src/host/usbh_control.c     |  82 ++-----
 src/osal/osal_none.h        |   2 +-
 5 files changed, 317 insertions(+), 217 deletions(-)

diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index dae95cebb..29753451e 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -80,7 +80,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 // If caller does not make any transfer, it must release endpoint for others.
 bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr);
 
-// Release an endpoint without submitting a transfer
+// Release claimed endpoint without submitting a transfer
 bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr);
 
 // Check if endpoint is busy transferring
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 07baeee96..3d9db70fa 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -72,7 +72,6 @@ typedef struct
     volatile uint8_t suspended  : 1;
   };
 
-  uint8_t control_stage;  // state of control transfer
 } usbh_dev0_t;
 
 typedef struct {
@@ -91,13 +90,12 @@ typedef struct {
     volatile uint8_t suspended  : 1;
   };
 
-  uint8_t control_stage;  // state of control transfer
-
   // Device Descriptor
+  uint8_t  ep0_size;
+
   uint16_t vid;
   uint16_t pid;
 
-  uint8_t  ep0_size;
   uint8_t  i_manufacturer;
   uint8_t  i_product;
   uint8_t  i_serial;
@@ -113,6 +111,14 @@ typedef struct {
 
 } usbh_device_t;
 
+typedef struct
+{
+  tusb_control_request_t request TU_ATTR_ALIGNED(4);
+  uint8_t* buffer;
+  tuh_control_complete_cb_t complete_cb;
+
+  uint8_t daddr;
+} usbh_control_xfer_t;
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
@@ -211,8 +217,24 @@ CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[TOTAL_DEVICES];
 
 // Mutex for claiming endpoint, only needed when using with preempted RTOS
 #if TUSB_OPT_MUTEX
-static osal_mutex_def_t _usbh_mutexdef[TOTAL_DEVICES];
-static osal_mutex_t _usbh_mutex[TOTAL_DEVICES];
+static osal_mutex_def_t _usbh_mutexdef;
+static osal_mutex_t _usbh_mutex;
+
+TU_ATTR_ALWAYS_INLINE static inline void usbh_lock(void)
+{
+  osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void usbh_unlock(void)
+{
+  osal_mutex_unlock(_usbh_mutex);
+}
+
+#else
+
+#define usbh_lock()
+#define usbh_unlock()
+
 #endif
 
 // Event queue
@@ -223,6 +245,15 @@ static osal_queue_t _usbh_q;
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
 static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
+// Control transfer: since most controller does not support multiple control transfer
+// on multiple devices concurrently. And control transfer is not used much except enumeration
+// We will only execute control transfer one at a time.
+struct
+{
+  usbh_control_xfer_t xfer;
+  uint8_t stage;
+}_ctrl_xfer;
+
 //------------- Helper Function -------------//
 
 TU_ATTR_ALWAYS_INLINE
@@ -235,10 +266,7 @@ static inline usbh_device_t* get_device(uint8_t dev_addr)
 static bool enum_new_device(hcd_event_t* event);
 static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port);
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
-
-// from usbh_control.c
-extern bool usbh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
-extern uint8_t usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, uint8_t* stage, xfer_result_t result, uint32_t xferred_bytes);
+static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
 //--------------------------------------------------------------------+
 // PUBLIC API (Parameter Verification is required)
@@ -276,24 +304,6 @@ void osal_task_delay(uint32_t msec)
 }
 #endif
 
-
-bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
-{
-  TU_LOG2("[%u:%u] %s: ", usbh_get_rhport(daddr), daddr, request->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[request->bRequest] : "Unknown Request");
-  TU_LOG2_VAR(request);
-  TU_LOG2("\r\n");
-
-  if (daddr)
-  {
-    get_device(daddr)->control_stage = CONTROL_STAGE_SETUP;
-  }else
-  {
-    _dev0.control_stage = CONTROL_STAGE_SETUP;
-  }
-
-  return usbh_control_xfer(daddr, request, buffer, complete_cb);
-}
-
 //--------------------------------------------------------------------+
 // Descriptors
 //--------------------------------------------------------------------+
@@ -449,26 +459,30 @@ bool tuh_init(uint8_t rhport)
 
   TU_LOG2("USBH init\r\n");
   TU_LOG2_INT(sizeof(usbh_device_t));
+  TU_LOG2_INT(sizeof(hcd_event_t));
+  TU_LOG2_INT(sizeof(usbh_control_xfer_t));
 
-  //------------- Enumeration & Reporter Task init -------------//
+  // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
   TU_ASSERT(_usbh_q != NULL);
 
-  //------------- Semaphore, Mutex for Control Pipe -------------//
+#if TUSB_OPT_MUTEX
+  // Mutex
+  _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
+  TU_ASSERT(_usbh_mutex);
+#endif
+
+  // Device
   tu_memclr(&_dev0, sizeof(_dev0));
   tu_memclr(_usbh_devices, sizeof(_usbh_devices));
+  tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer));
 
   for(uint8_t i=0; i<TOTAL_DEVICES; i++)
   {
     clear_device(&_usbh_devices[i]);
-
-#if TUSB_OPT_MUTEX
-    _usbh_mutex[i] = osal_mutex_create(&_usbh_mutexdef[i]);
-    TU_ASSERT(_usbh_mutex[i]);
-#endif
   }
 
-  // Class drivers init
+  // Class drivers
   for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
   {
     TU_LOG2("%s init\r\n", usbh_class_drivers[drv_id].name);
@@ -546,7 +560,7 @@ void tuh_task(void)
         {
           // device 0 only has control endpoint
           TU_ASSERT(epnum == 0, );
-          usbh_control_xfer_cb(event.dev_addr, ep_addr, &_dev0.control_stage, event.xfer_complete.result, event.xfer_complete.len);
+          usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
         }
         else
         {
@@ -556,7 +570,7 @@ void tuh_task(void)
 
           if ( 0 == epnum )
           {
-            usbh_control_xfer_cb(event.dev_addr, ep_addr, &dev->control_stage, event.xfer_complete.result, event.xfer_complete.len);
+            usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
           }else
           {
             uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
@@ -683,81 +697,6 @@ void hcd_event_device_remove(uint8_t hostid, bool in_isr)
   hcd_event_handler(&event, in_isr);
 }
 
-
-// a device unplugged from rhport:hub_addr:hub_port
-static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
-{
-  //------------- find the all devices (star-network) under port that is unplugged -------------//
-  // TODO mark as disconnected in ISR, also handle dev0
-  for ( uint8_t dev_id = 0; dev_id < TU_ARRAY_SIZE(_usbh_devices); dev_id++ )
-  {
-    usbh_device_t* dev = &_usbh_devices[dev_id];
-    uint8_t const dev_addr = dev_id+1;
-
-    // TODO Hub multiple level
-    if (dev->rhport == rhport   &&
-        (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr == 0 & hub_port == 0 means roothub
-        (hub_port == 0 || dev->hub_port == hub_port) &&
-        dev->connected)
-    {
-      // Invoke callback before close driver
-      if (tuh_umount_cb) tuh_umount_cb(dev_addr);
-
-      // Close class driver
-      for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
-      {
-        TU_LOG2("%s close\r\n", usbh_class_drivers[drv_id].name);
-        usbh_class_drivers[drv_id].close(dev_addr);
-      }
-
-      hcd_device_close(rhport, dev_addr);
-      clear_device(dev);
-    }
-  }
-}
-
-//--------------------------------------------------------------------+
-// INTERNAL HELPER
-//--------------------------------------------------------------------+
-static uint8_t get_new_address(bool is_hub)
-{
-  uint8_t const start = (is_hub ? CFG_TUH_DEVICE_MAX : 0) + 1;
-  uint8_t const count = (is_hub ? CFG_TUH_HUB : CFG_TUH_DEVICE_MAX);
-
-  for (uint8_t i=0; i < count; i++)
-  {
-    uint8_t const addr = start + i;
-    if (!get_device(addr)->connected) return addr;
-  }
-  return ADDR_INVALID;
-}
-
-void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
-{
-  usbh_device_t* dev = get_device(dev_addr);
-
-  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++)
-  {
-    // continue with next valid interface
-    // TODO skip IAD binding interface such as CDCs
-    uint8_t const drv_id = dev->itf2drv[itf_num];
-    if (drv_id != DRVID_INVALID)
-    {
-      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
-      TU_LOG2("%s set config: itf = %u\r\n", driver->name, itf_num);
-      driver->set_config(dev_addr, itf_num);
-      break;
-    }
-  }
-
-  // all interface are configured
-  if (itf_num == CFG_TUH_INTERFACE_MAX)
-  {
-    // Invoke callback if available
-    if (tuh_mount_cb) tuh_mount_cb(dev_addr);
-  }
-}
-
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
@@ -774,7 +713,7 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
   tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
 #if TUSB_OPT_MUTEX
-  return tu_edpt_claim(ep_state, _usbh_mutex[dev_addr-1]);
+  return tu_edpt_claim(ep_state, _usbh_mutex);
 #else
   return tu_edpt_claim(ep_state, NULL);
 #endif
@@ -792,7 +731,7 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
   tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
 #if TUSB_OPT_MUTEX
-  return tu_edpt_release(ep_state, _usbh_mutex[dev_addr-1]);
+  return tu_edpt_release(ep_state, _usbh_mutex);
 #else
   return tu_edpt_release(ep_state, NULL);
 #endif
@@ -865,6 +804,183 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
   return dev->ep_status[epnum][dir].busy;
 }
 
+//--------------------------------------------------------------------+
+// Control transfer
+//--------------------------------------------------------------------+
+
+bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
+{
+  // pre-check to help reducing mutex lock
+  TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
+
+  usbh_lock();
+
+  bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
+  if (is_idle) _ctrl_xfer.stage = CONTROL_STAGE_SETUP;
+
+  usbh_unlock();
+
+  TU_VERIFY(is_idle);
+
+  const uint8_t rhport = usbh_get_rhport(daddr);
+
+  TU_LOG2("[%u:%u] %s: ", rhport, daddr, request->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[request->bRequest] : "Unknown Request");
+  TU_LOG2_VAR(request);
+  TU_LOG2("\r\n");
+
+  _ctrl_xfer.xfer.request     = (*request);
+  _ctrl_xfer.xfer.buffer      = buffer;
+  _ctrl_xfer.xfer.complete_cb = complete_cb;
+  _ctrl_xfer.xfer.daddr       = daddr;
+
+  return hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.xfer.request);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void set_control_xfer_stage(uint8_t stage)
+{
+  usbh_lock();
+  _ctrl_xfer.stage = stage;
+  usbh_unlock();
+}
+
+static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
+{
+  TU_LOG2("\r\n");
+
+  usbh_lock();
+  _ctrl_xfer.stage = CONTROL_STAGE_IDLE;
+  usbh_unlock();
+
+  if (_ctrl_xfer.xfer.complete_cb) _ctrl_xfer.xfer.complete_cb(dev_addr, &_ctrl_xfer.xfer.request, result);
+}
+
+static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+{
+  (void) ep_addr;
+  (void) xferred_bytes;
+
+  const uint8_t rhport = usbh_get_rhport(dev_addr);
+  tusb_control_request_t const * request = &_ctrl_xfer.xfer.request;
+
+  if (XFER_RESULT_SUCCESS != result)
+  {
+    TU_LOG2("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED");
+
+    // terminate transfer if any stage failed
+    _xfer_complete(dev_addr, result);
+  }else
+  {
+    switch(_ctrl_xfer.stage)
+    {
+      case CONTROL_STAGE_SETUP:
+        if (request->wLength)
+        {
+          // DATA stage: initial data toggle is always 1
+          set_control_xfer_stage(CONTROL_STAGE_DATA);
+          return hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.xfer.buffer, request->wLength);
+        }
+        __attribute__((fallthrough));
+
+      case CONTROL_STAGE_DATA:
+        if (request->wLength)
+        {
+          TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
+          TU_LOG2_MEM(_ctrl_xfer.xfer.buffer, request->wLength, 2);
+        }
+
+        // ACK stage: toggle is always 1
+        set_control_xfer_stage(CONTROL_STAGE_ACK);
+        hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
+      break;
+
+      case CONTROL_STAGE_ACK:
+        _xfer_complete(dev_addr, result);
+      break;
+
+      default: return false;
+    }
+  }
+
+  return true;
+}
+
+// a device unplugged from rhport:hub_addr:hub_port
+static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
+{
+  //------------- find the all devices (star-network) under port that is unplugged -------------//
+  // TODO mark as disconnected in ISR, also handle dev0
+  for ( uint8_t dev_id = 0; dev_id < TU_ARRAY_SIZE(_usbh_devices); dev_id++ )
+  {
+    usbh_device_t* dev = &_usbh_devices[dev_id];
+    uint8_t const dev_addr = dev_id+1;
+
+    // TODO Hub multiple level
+    if (dev->rhport == rhport   &&
+        (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr == 0 & hub_port == 0 means roothub
+        (hub_port == 0 || dev->hub_port == hub_port) &&
+        dev->connected)
+    {
+      // Invoke callback before close driver
+      if (tuh_umount_cb) tuh_umount_cb(dev_addr);
+
+      // Close class driver
+      for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+      {
+        TU_LOG2("%s close\r\n", usbh_class_drivers[drv_id].name);
+        usbh_class_drivers[drv_id].close(dev_addr);
+      }
+
+      hcd_device_close(rhport, dev_addr);
+      clear_device(dev);
+      // abort on-going control xfer if any
+      if (_ctrl_xfer.xfer.daddr == dev_addr) set_control_xfer_stage(CONTROL_STAGE_IDLE);
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// INTERNAL HELPER
+//--------------------------------------------------------------------+
+
+static uint8_t get_new_address(bool is_hub)
+{
+  uint8_t const start = (is_hub ? CFG_TUH_DEVICE_MAX : 0) + 1;
+  uint8_t const count = (is_hub ? CFG_TUH_HUB : CFG_TUH_DEVICE_MAX);
+
+  for (uint8_t i=0; i < count; i++)
+  {
+    uint8_t const addr = start + i;
+    if (!get_device(addr)->connected) return addr;
+  }
+  return ADDR_INVALID;
+}
+
+void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
+{
+  usbh_device_t* dev = get_device(dev_addr);
+
+  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++)
+  {
+    // continue with next valid interface
+    // TODO skip IAD binding interface such as CDCs
+    uint8_t const drv_id = dev->itf2drv[itf_num];
+    if (drv_id != DRVID_INVALID)
+    {
+      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+      TU_LOG2("%s set config: itf = %u\r\n", driver->name, itf_num);
+      driver->set_config(dev_addr, itf_num);
+      break;
+    }
+  }
+
+  // all interface are configured
+  if (itf_num == CFG_TUH_INTERFACE_MAX)
+  {
+    // Invoke callback if available
+    if (tuh_mount_cb) tuh_mount_cb(dev_addr);
+  }
+}
+
 //--------------------------------------------------------------------+
 // Enumeration Process
 // is a lengthy process with a series of control transfer to configure
@@ -886,43 +1002,16 @@ static bool enum_set_config_complete            (uint8_t dev_addr, tusb_control_
 static bool parse_configuration_descriptor      (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
 
 #if CFG_TUH_HUB
-static bool enum_hub_clear_reset0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
-{
-  (void) dev_addr; (void) request;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-  enum_request_addr0_device_desc();
-  return true;
-}
 
-static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
-{
-  (void) dev_addr; (void) request;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
+// Enum sequence:
+// New device (reset on the way) -> Get Status 0 -> Clear Reset 0 -> Get 8byte Device Descriptor
+//   -> Port Reset 1 -> reset delay -> Get Status 1 -> Clear Reset 1 -> queue hub interrupt endpoint
 
-  enum_request_set_addr();
-
-  // done with hub, waiting for next data on status pipe
-  (void) hub_status_pipe_queue( _dev0.hub_addr );
-
-  return true;
-}
-
-static bool enum_hub_get_status1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
-{
-  (void) dev_addr; (void) request;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  hub_port_status_response_t port_status;
-  memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
-
-  // Acknowledge Port Reset Change if Reset Successful
-  if (port_status.change.reset)
-  {
-    TU_ASSERT( hub_port_clear_feature(_dev0.hub_addr, _dev0.hub_port, HUB_FEATURE_PORT_RESET_CHANGE, enum_hub_clear_reset1_complete) );
-  }
-
-  return true;
-}
+static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_hub_clear_reset0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_hub_set_reset1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_hub_get_status1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 
 static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
@@ -949,6 +1038,57 @@ static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request
 
   return true;
 }
+
+static bool enum_hub_clear_reset0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+  (void) dev_addr; (void) request;
+  TU_ASSERT(XFER_RESULT_SUCCESS == result);
+  enum_request_addr0_device_desc();
+  return true;
+}
+
+static bool enum_hub_set_reset1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+  (void) dev_addr; (void) request;
+  TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+  osal_task_delay(RESET_DELAY);
+
+  TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status1_complete) );
+
+  return true;
+}
+
+static bool enum_hub_get_status1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+  (void) dev_addr; (void) request;
+  TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+  hub_port_status_response_t port_status;
+  memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
+
+  // Acknowledge Port Reset Change if Reset Successful
+  if (port_status.change.reset)
+  {
+    TU_ASSERT( hub_port_clear_feature(_dev0.hub_addr, _dev0.hub_port, HUB_FEATURE_PORT_RESET_CHANGE, enum_hub_clear_reset1_complete) );
+  }
+
+  return true;
+}
+
+static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+  (void) dev_addr; (void) request;
+  TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+  enum_request_set_addr();
+
+  // done with hub, waiting for next data on status pipe
+  (void) hub_status_pipe_queue( _dev0.hub_addr );
+
+  return true;
+}
+
 #endif // hub
 
 static bool enum_new_device(hcd_event_t* event)
@@ -1030,12 +1170,7 @@ static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_r
   else
   {
     // after RESET_DELAY the hub_port_reset() already complete
-    TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, NULL) );
-    osal_task_delay(RESET_DELAY);
-
-    tuh_task(); // FIXME temporarily to clean up port_reset control transfer
-
-    TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status1_complete) );
+    TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, enum_hub_set_reset1_complete) );
   }
 #endif // hub
 
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index 2f9957cc6..0435eae70 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -73,6 +73,7 @@ bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_
 // If caller does not make any transfer, it must release endpoint for others.
 bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
 
+// Release claimed endpoint without submitting a transfer
 bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr);
 
 // Check if endpoint transferring is complete
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
index 88287a47b..38f03a8d2 100644
--- a/src/host/usbh_control.c
+++ b/src/host/usbh_control.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED
+#if CFG_TUH_ENABLED && 0
 
 #include "tusb.h"
 #include "usbh_classdriver.h"
@@ -36,86 +36,50 @@ typedef struct
   tusb_control_request_t request TU_ATTR_ALIGNED(4);
   uint8_t* buffer;
   tuh_control_complete_cb_t complete_cb;
+
+  uint8_t daddr;
 } usbh_control_xfer_t;
 
-static usbh_control_xfer_t _ctrl_xfer;
+static usbh_control_xfer_t _xfer;
+static uint8_t _stage = CONTROL_STAGE_IDLE;
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
+uint8_t usbh_control_xfer_stage(void)
+{
+  return _stage;
+}
+
 bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
 {
   // TODO need to claim the endpoint first
   const uint8_t rhport = usbh_get_rhport(dev_addr);
 
-  _ctrl_xfer.request     = (*request);
-  _ctrl_xfer.buffer      = buffer;
-  _ctrl_xfer.complete_cb = complete_cb;
+  _ctrl_xfer.xfer.daddr       = dev_addr;
+  _ctrl_xfer.xfer.request     = (*request);
+  _ctrl_xfer.xfer.buffer      = buffer;
+  _ctrl_xfer.xfer.complete_cb = complete_cb;
+
+  _stage = CONTROL_STAGE_SETUP;
 
   // Send setup packet
-  TU_ASSERT( hcd_setup_send(rhport, dev_addr, (uint8_t const*) &_ctrl_xfer.request) );
+  TU_ASSERT( hcd_setup_send(rhport, dev_addr, (uint8_t const*) &_ctrl_xfer.xfer.request) );
 
   return true;
 }
 
+void usbh_control_xfer_abort(uint8_t dev_addr)
+{
+  if (_ctrl_xfer.xfer.daddr == dev_addr) _stage = CONTROL_STAGE_IDLE;
+}
+
 static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
 {
   TU_LOG2("\r\n");
-  if (_ctrl_xfer.complete_cb) _ctrl_xfer.complete_cb(dev_addr, &_ctrl_xfer.request, result);
+  if (_ctrl_xfer.xfer.complete_cb) _ctrl_xfer.xfer.complete_cb(dev_addr, &_ctrl_xfer.xfer.request, result);
 }
 
-bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, uint8_t* stage, xfer_result_t result, uint32_t xferred_bytes)
-{
-  (void) ep_addr;
-  (void) xferred_bytes;
-
-  const uint8_t rhport = usbh_get_rhport(dev_addr);
-  tusb_control_request_t const * request = &_ctrl_xfer.request;
-
-  if (XFER_RESULT_SUCCESS != result)
-  {
-    TU_LOG2("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED");
-
-    // terminate transfer if any stage failed
-    *stage = CONTROL_STAGE_IDLE;
-    _xfer_complete(dev_addr, result);
-  }else
-  {
-    switch(*stage)
-    {
-      case CONTROL_STAGE_SETUP:
-        *stage = CONTROL_STAGE_DATA;
-        if (request->wLength)
-        {
-          // DATA stage: initial data toggle is always 1
-          hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
-          return true;
-        }
-        __attribute__((fallthrough));
-
-      case CONTROL_STAGE_DATA:
-        *stage = CONTROL_STAGE_ACK;
-        if (request->wLength)
-        {
-          TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
-          TU_LOG2_MEM(_ctrl_xfer.buffer, request->wLength, 2);
-        }
-
-        // ACK stage: toggle is always 1
-        hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
-      break;
-
-      case CONTROL_STAGE_ACK:
-        *stage = CONTROL_STAGE_IDLE;
-        _xfer_complete(dev_addr, result);
-      break;
-
-      default: return false;
-    }
-  }
-
-  return true;
-}
 
 #endif
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index e1dd95c34..4217f0422 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -111,7 +111,7 @@ typedef struct
 
 typedef osal_queue_def_t* osal_queue_t;
 
-// role device/host is used by OS NONE for mutex (disable usb isr) only
+// _int_set is used as mutex in OS NONE (disable/enable USB ISR)
 #define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type)    \
   uint8_t _name##_buf[_depth*sizeof(_type)];              \
   osal_queue_def_t _name = {                              \

From 66c933fb61ee01ba640f39a9328b4892d16bb225 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Mar 2022 23:16:59 +0700
Subject: [PATCH 0890/2085] fix enumeration issue when plugging hub with
 multiple devices attached

---
 src/host/hub.c  |   4 +-
 src/host/hub.h  |   2 +-
 src/host/usbh.c | 121 ++++++++++++++++++++++++++----------------------
 src/host/usbh.h |   3 +-
 4 files changed, 70 insertions(+), 60 deletions(-)

diff --git a/src/host/hub.c b/src/host/hub.c
index 1fec8b892..4c375c290 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -189,7 +189,7 @@ void hub_close(uint8_t dev_addr)
   if (p_hub->ep_in) tu_memclr(p_hub, sizeof( hub_interface_t));
 }
 
-bool hub_status_pipe_queue(uint8_t dev_addr)
+bool hub_edpt_status_xfer(uint8_t dev_addr)
 {
   hub_interface_t* hub_itf = get_itf(dev_addr);
   return usbh_edpt_xfer(dev_addr, hub_itf->ep_in, &hub_itf->status_change, 1);
@@ -324,7 +324,7 @@ static bool connection_get_status_complete (uint8_t dev_addr, tusb_control_reque
 
     // prepare for next hub status
     // TODO continue with status_change, or maybe we can do it again with status
-    hub_status_pipe_queue(dev_addr);
+    hub_edpt_status_xfer(dev_addr);
   }
 
   return true;
diff --git a/src/host/hub.h b/src/host/hub.h
index c4d544193..6d81f6773 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -176,7 +176,7 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, t
 
 bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_complete_cb_t complete_cb);
 bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_complete_cb_t complete_cb);
-bool hub_status_pipe_queue(uint8_t dev_addr);
+bool hub_edpt_status_xfer(uint8_t dev_addr);
 
 //--------------------------------------------------------------------+
 // Internal Class Driver API
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 3d9db70fa..01675cddd 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -543,7 +543,7 @@ void tuh_task(void)
         if ( event.connection.hub_addr != 0)
         {
           // done with hub, waiting for next data on status pipe
-          (void) hub_status_pipe_queue( event.connection.hub_addr );
+          (void) hub_edpt_status_xfer( event.connection.hub_addr );
         }
         #endif
       break;
@@ -904,6 +904,10 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
   return true;
 }
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 // a device unplugged from rhport:hub_addr:hub_port
 static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
 {
@@ -938,49 +942,6 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
   }
 }
 
-//--------------------------------------------------------------------+
-// INTERNAL HELPER
-//--------------------------------------------------------------------+
-
-static uint8_t get_new_address(bool is_hub)
-{
-  uint8_t const start = (is_hub ? CFG_TUH_DEVICE_MAX : 0) + 1;
-  uint8_t const count = (is_hub ? CFG_TUH_HUB : CFG_TUH_DEVICE_MAX);
-
-  for (uint8_t i=0; i < count; i++)
-  {
-    uint8_t const addr = start + i;
-    if (!get_device(addr)->connected) return addr;
-  }
-  return ADDR_INVALID;
-}
-
-void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
-{
-  usbh_device_t* dev = get_device(dev_addr);
-
-  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++)
-  {
-    // continue with next valid interface
-    // TODO skip IAD binding interface such as CDCs
-    uint8_t const drv_id = dev->itf2drv[itf_num];
-    if (drv_id != DRVID_INVALID)
-    {
-      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
-      TU_LOG2("%s set config: itf = %u\r\n", driver->name, itf_num);
-      driver->set_config(dev_addr, itf_num);
-      break;
-    }
-  }
-
-  // all interface are configured
-  if (itf_num == CFG_TUH_INTERFACE_MAX)
-  {
-    // Invoke callback if available
-    if (tuh_mount_cb) tuh_mount_cb(dev_addr);
-  }
-}
-
 //--------------------------------------------------------------------+
 // Enumeration Process
 // is a lengthy process with a series of control transfer to configure
@@ -991,9 +952,9 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
 //--------------------------------------------------------------------+
 
 static bool enum_request_addr0_device_desc(void);
-static bool enum_request_set_addr(void);
-
 static bool enum_get_addr0_device_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+
+static bool enum_request_set_addr(void);
 static bool enum_set_address_complete           (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 static bool enum_get_device_desc_complete       (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 static bool enum_get_9byte_config_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
@@ -1001,6 +962,9 @@ static bool enum_get_config_desc_complete       (uint8_t dev_addr, tusb_control_
 static bool enum_set_config_complete            (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
 static bool parse_configuration_descriptor      (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
 
+static uint8_t get_new_address(bool is_hub);
+static void enum_full_complete(void);
+
 #if CFG_TUH_HUB
 
 // Enum sequence:
@@ -1015,7 +979,7 @@ static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tusb_control_reques
 
 static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
-  (void) dev_addr; (void) request;
+  (void) request;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   hub_port_status_response_t port_status;
@@ -1024,7 +988,8 @@ static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request
   if ( !port_status.status.connection )
   {
     // device unplugged while delaying, nothing else to do, queue hub status
-    return hub_status_pipe_queue(dev_addr);
+    enum_full_complete();
+    return false;
   }
 
   _dev0.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH :
@@ -1083,9 +1048,6 @@ static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tusb_control_reques
 
   enum_request_set_addr();
 
-  // done with hub, waiting for next data on status pipe
-  (void) hub_status_pipe_queue( _dev0.hub_addr );
-
   return true;
 }
 
@@ -1144,11 +1106,8 @@ static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_r
 
   if (XFER_RESULT_SUCCESS != result)
   {
-#if CFG_TUH_HUB
-    // TODO remove, waiting for next data on status pipe
-    if (_dev0.hub_addr != 0) hub_status_pipe_queue(_dev0.hub_addr);
-#endif
-
+    // stop enumeration, maybe we could retry this
+    enum_full_complete();
     return false;
   }
 
@@ -1407,4 +1366,54 @@ static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configura
   return true;
 }
 
+void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
+{
+  usbh_device_t* dev = get_device(dev_addr);
+
+  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++)
+  {
+    // continue with next valid interface
+    // TODO skip IAD binding interface such as CDCs
+    uint8_t const drv_id = dev->itf2drv[itf_num];
+    if (drv_id != DRVID_INVALID)
+    {
+      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+      TU_LOG2("%s set config: itf = %u\r\n", driver->name, itf_num);
+      driver->set_config(dev_addr, itf_num);
+      break;
+    }
+  }
+
+  // all interface are configured
+  if (itf_num == CFG_TUH_INTERFACE_MAX)
+  {
+    enum_full_complete();
+
+    // Invoke callback if available
+    if (tuh_mount_cb) tuh_mount_cb(dev_addr);
+  }
+}
+
+static void enum_full_complete(void)
+{
+#if CFG_TUH_HUB
+  // get next hub status
+  if (_dev0.hub_addr) hub_edpt_status_xfer(_dev0.hub_addr);
+#endif
+
+}
+
+static uint8_t get_new_address(bool is_hub)
+{
+  uint8_t const start = (is_hub ? CFG_TUH_DEVICE_MAX : 0) + 1;
+  uint8_t const count = (is_hub ? CFG_TUH_HUB : CFG_TUH_DEVICE_MAX);
+
+  for (uint8_t i=0; i < count; i++)
+  {
+    uint8_t const addr = start + i;
+    if (!get_device(addr)->connected) return addr;
+  }
+  return ADDR_INVALID;
+}
+
 #endif
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 31d63d6a7..eec2ed702 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -80,7 +80,8 @@ static inline bool tuh_ready(uint8_t daddr)
   return tuh_mounted(daddr) && !tuh_suspended(daddr);
 }
 
-// Carry out control transfer
+// Carry out a control transfer
+// true on success, false if there is on-going control trasnfer
 bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
 
 // Set Configuration

From 951ece17e1e26c297f3c05807271ab1ba56a2ada Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 10 Mar 2022 23:20:12 +0700
Subject: [PATCH 0891/2085] fix build warning

---
 src/host/usbh.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 01675cddd..11bf2f997 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -979,7 +979,7 @@ static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tusb_control_reques
 
 static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
 {
-  (void) request;
+  (void) dev_addr; (void) request;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   hub_port_status_response_t port_status;

From 37960990a5fb0a42a5faa19230f0051efaa4e6c0 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Thu, 10 Mar 2022 11:01:44 -0800
Subject: [PATCH 0892/2085] Print speed. Don't crash if string get fails

---
 examples/host/device_info/src/main.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c
index 45b616af0..e6149db89 100644
--- a/examples/host/device_info/src/main.c
+++ b/examples/host/device_info/src/main.c
@@ -90,6 +90,10 @@ static void _wait_and_convert(uint16_t *temp_buf, size_t buf_len) {
     while (_get_string_result == 0xff) {
         tuh_task();
     }
+    if (_get_string_result != XFER_RESULT_SUCCESS) {
+        temp_buf[0] = 0;
+        return;
+    }
     size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
     size_t utf8_len = _count_utf8_bytes(temp_buf + 1, utf16_len);
     _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
@@ -128,6 +132,21 @@ int main(void)
       tuh_vid_pid_get(i, &vid, &pid);
       printf("%d vid %04x pid %04x\r\n", i, vid, pid);
 
+      tusb_speed_t speed = tuh_speed_get(i);
+      switch (speed) {
+        case TUSB_SPEED_FULL:
+          printf("Full speed\r\n");
+          break;
+        case TUSB_SPEED_LOW:
+          printf("Low speed\r\n");
+          break;
+        case TUSB_SPEED_HIGH:
+          printf("High speed\r\n");
+          break;
+        default:
+          break;
+      }
+
       _get_string_result = 0xff;
       uint16_t temp_buf[127];
       if (tuh_descriptor_string_serial_get(i, 0, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {

From a715077b1079993f4cd01bbf54b8166a6612b29b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Mar 2022 09:57:35 +0700
Subject: [PATCH 0893/2085] remove usbh_control.c

---
 examples/host/bare_api/Makefile       |  1 -
 examples/host/cdc_msc_hid/Makefile    |  1 -
 examples/host/hid_controller/Makefile |  1 -
 examples/host/hid_to_cdc/Makefile     |  3 +-
 hw/bsp/rp2040/family.cmake            |  1 -
 src/host/usbh_control.c               | 85 ---------------------------
 6 files changed, 1 insertion(+), 91 deletions(-)
 delete mode 100644 src/host/usbh_control.c

diff --git a/examples/host/bare_api/Makefile b/examples/host/bare_api/Makefile
index c59369ffa..13e14df53 100644
--- a/examples/host/bare_api/Makefile
+++ b/examples/host/bare_api/Makefile
@@ -21,7 +21,6 @@ SRC_C += \
 	src/class/msc/msc_host.c \
 	src/host/hub.c \
 	src/host/usbh.c \
-	src/host/usbh_control.c \
 	src/portable/ohci/ohci.c \
 	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
 
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index ce0dd1a40..272acbac8 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -19,7 +19,6 @@ SRC_C += \
 	src/class/msc/msc_host.c \
 	src/host/hub.c \
 	src/host/usbh.c \
-	src/host/usbh_control.c \
 	src/portable/ohci/ohci.c \
 	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
 
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index c58df562b..06dc56914 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -22,7 +22,6 @@ SRC_C += \
 	src/class/msc/msc_host.c \
 	src/host/hub.c \
 	src/host/usbh.c \
-	src/host/usbh_control.c \
 	src/portable/ohci/ohci.c \
 	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
 
diff --git a/examples/host/hid_to_cdc/Makefile b/examples/host/hid_to_cdc/Makefile
index b62a383eb..3fe9b0888 100644
--- a/examples/host/hid_to_cdc/Makefile
+++ b/examples/host/hid_to_cdc/Makefile
@@ -14,7 +14,6 @@ CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
 SRC_C += \
 	src/class/hid/hid_host.c \
 	src/host/hub.c \
-	src/host/usbh.c \
-	src/host/usbh_control.c
+	src/host/usbh.c
 
 include ../../rules.mk
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 1aa180ef8..e832c0756 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -83,7 +83,6 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
 			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
 			${TOP}/src/host/usbh.c
-			${TOP}/src/host/usbh_control.c
 			${TOP}/src/host/hub.c
 			${TOP}/src/class/cdc/cdc_host.c
 			${TOP}/src/class/hid/hid_host.c
diff --git a/src/host/usbh_control.c b/src/host/usbh_control.c
deleted file mode 100644
index 38f03a8d2..000000000
--- a/src/host/usbh_control.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if CFG_TUH_ENABLED && 0
-
-#include "tusb.h"
-#include "usbh_classdriver.h"
-
-typedef struct
-{
-  tusb_control_request_t request TU_ATTR_ALIGNED(4);
-  uint8_t* buffer;
-  tuh_control_complete_cb_t complete_cb;
-
-  uint8_t daddr;
-} usbh_control_xfer_t;
-
-static usbh_control_xfer_t _xfer;
-static uint8_t _stage = CONTROL_STAGE_IDLE;
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-uint8_t usbh_control_xfer_stage(void)
-{
-  return _stage;
-}
-
-bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
-{
-  // TODO need to claim the endpoint first
-  const uint8_t rhport = usbh_get_rhport(dev_addr);
-
-  _ctrl_xfer.xfer.daddr       = dev_addr;
-  _ctrl_xfer.xfer.request     = (*request);
-  _ctrl_xfer.xfer.buffer      = buffer;
-  _ctrl_xfer.xfer.complete_cb = complete_cb;
-
-  _stage = CONTROL_STAGE_SETUP;
-
-  // Send setup packet
-  TU_ASSERT( hcd_setup_send(rhport, dev_addr, (uint8_t const*) &_ctrl_xfer.xfer.request) );
-
-  return true;
-}
-
-void usbh_control_xfer_abort(uint8_t dev_addr)
-{
-  if (_ctrl_xfer.xfer.daddr == dev_addr) _stage = CONTROL_STAGE_IDLE;
-}
-
-static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
-{
-  TU_LOG2("\r\n");
-  if (_ctrl_xfer.xfer.complete_cb) _ctrl_xfer.xfer.complete_cb(dev_addr, &_ctrl_xfer.xfer.request, result);
-}
-
-
-#endif

From 6b5490ced687ba44ede9a0dd1dd62b4b67eedf59 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Mar 2022 13:12:36 +0700
Subject: [PATCH 0894/2085] merge device_info into bare_api example

---
 examples/host/bare_api/src/main.c           | 123 +++++++++++--
 examples/host/device_info/CMakeLists.txt    |  27 ---
 examples/host/device_info/Makefile          |  28 ---
 examples/host/device_info/only.txt          |   9 -
 examples/host/device_info/src/main.c        | 194 --------------------
 examples/host/device_info/src/tusb_config.h |  96 ----------
 src/host/usbh.c                             |   4 +-
 7 files changed, 107 insertions(+), 374 deletions(-)
 delete mode 100644 examples/host/device_info/CMakeLists.txt
 delete mode 100644 examples/host/device_info/Makefile
 delete mode 100644 examples/host/device_info/only.txt
 delete mode 100644 examples/host/device_info/src/main.c
 delete mode 100644 examples/host/device_info/src/tusb_config.h

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 5f8f886c8..73e97c390 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -46,8 +46,6 @@ int main(void)
   board_init();
 
   printf("TinyUSB Host HID Controller Example\r\n");
-  printf("Note: Events only displayed for explictly supported controllers\r\n");
-
   tusb_init();
 
   while (1)
@@ -64,10 +62,74 @@ int main(void)
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
 
-uint8_t usb_buf[256] TU_ATTR_ALIGNED(4);
+// English
+#define LANGUAGE_ID 0x0409
 
+//uint8_t usb_buf[256] TU_ATTR_ALIGNED(4);
 tusb_desc_device_t desc_device;
 
+static volatile xfer_result_t _get_string_result;
+
+static bool _transfer_done_cb(uint8_t daddr, tusb_control_request_t const *request, xfer_result_t result) {
+    (void)daddr;
+    (void)request;
+    _get_string_result = result;
+    return true;
+}
+
+static void _convert_utf16le_to_utf8(const uint16_t *utf16, size_t utf16_len, uint8_t *utf8, size_t utf8_len) {
+    // TODO: Check for runover.
+    (void)utf8_len;
+    // Get the UTF-16 length out of the data itself.
+
+    for (size_t i = 0; i < utf16_len; i++) {
+        uint16_t chr = utf16[i];
+        if (chr < 0x80) {
+            *utf8++ = chr & 0xff;
+        } else if (chr < 0x800) {
+            *utf8++ = (uint8_t)(0xC0 | (chr >> 6 & 0x1F));
+            *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
+        } else {
+            // TODO: Verify surrogate.
+            *utf8++ = (uint8_t)(0xE0 | (chr >> 12 & 0x0F));
+            *utf8++ = (uint8_t)(0x80 | (chr >> 6 & 0x3F));
+            *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
+        }
+        // TODO: Handle UTF-16 code points that take two entries.
+    }
+}
+
+// Count how many bytes a utf-16-le encoded string will take in utf-8.
+static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
+    size_t total_bytes = 0;
+    for (size_t i = 0; i < len; i++) {
+        uint16_t chr = buf[i];
+        if (chr < 0x80) {
+            total_bytes += 1;
+        } else if (chr < 0x800) {
+            total_bytes += 2;
+        } else {
+            total_bytes += 3;
+        }
+        // TODO: Handle UTF-16 code points that take two entries.
+    }
+    return total_bytes;
+}
+
+static void _wait_and_convert(uint16_t *temp_buf, size_t buf_len) {
+    while (_get_string_result == 0xff) {
+        tuh_task();
+    }
+    if (_get_string_result != XFER_RESULT_SUCCESS) {
+        temp_buf[0] = 0;
+        return;
+    }
+    size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
+    size_t utf8_len = _count_utf8_bytes(temp_buf + 1, utf16_len);
+    _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
+    ((uint8_t*) temp_buf)[utf8_len] = '\0';
+}
+
 bool print_device_descriptor(uint8_t daddr, tusb_control_request_t const * request, xfer_result_t result)
 {
   (void) request;
@@ -78,26 +140,49 @@ bool print_device_descriptor(uint8_t daddr, tusb_control_request_t const * reque
     return false;
   }
 
-  printf("Rhport %u Device %u: ID %04x:%04x\r\n", 0, daddr, desc_device.idVendor, desc_device.idProduct);
+  printf("Device %u: ID %04x:%04x\r\n", daddr, desc_device.idVendor, desc_device.idProduct);
   printf("Device Descriptor:\r\n");
-  printf("  bLength             %u\r\n", desc_device.bLength);
-  printf("  bDescriptorType     %u\r\n", desc_device.bDescriptorType);
-  printf("  bcdUSB              %04x\r\n", desc_device.bcdUSB);
+  printf("  bLength             %u\r\n"     , desc_device.bLength);
+  printf("  bDescriptorType     %u\r\n"     , desc_device.bDescriptorType);
+  printf("  bcdUSB              %04x\r\n"   , desc_device.bcdUSB);
+  printf("  bDeviceClass        %u\r\n"     , desc_device.bDeviceClass);
+  printf("  bDeviceSubClass     %u\r\n"     , desc_device.bDeviceSubClass);
+  printf("  bDeviceProtocol     %u\r\n"     , desc_device.bDeviceProtocol);
+  printf("  bMaxPacketSize0     %u\r\n"     , desc_device.bMaxPacketSize0);
+  printf("  idVendor            0x%04x\r\n" , desc_device.idVendor);
+  printf("  idProduct           0x%04x\r\n" , desc_device.idProduct);
+  printf("  bcdDevice           %04x\r\n"   , desc_device.bcdDevice);
 
-  printf("  bDeviceClass        %u\r\n", desc_device.bDeviceClass);
-  printf("  bDeviceSubClass     %u\r\n", desc_device.bDeviceSubClass);
-  printf("  bDeviceProtocol     %u\r\n", desc_device.bDeviceProtocol);
-  printf("  bMaxPacketSize0     %u\r\n", desc_device.bMaxPacketSize0);
+  _get_string_result = 0xff;
+  uint16_t temp_buf[128];
 
-  printf("  idVendor            0x%04x\r\n", desc_device.idVendor);
-  printf("  idProduct           0x%04x\r\n", desc_device.idProduct);
-  printf("  bcdDevice           %04x\r\n", desc_device.bcdDevice);
+  printf("  iManufacturer       %u     "     , desc_device.iManufacturer);
+  temp_buf[0] = 0;
+  if (tuh_descriptor_get_manufacturer_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
+    _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
+    printf((const char*) temp_buf);
+  }
+  printf("\r\n");
 
-  printf("  iManufacturer       %u\r\n", desc_device.iManufacturer);
-  printf("  iProduct            %u\r\n", desc_device.iProduct);
-  printf("  iSerialNumber       %u\r\n", desc_device.iSerialNumber);
+  printf("  iProduct            %u     "     , desc_device.iProduct);
+  _get_string_result = 0xff;
+  temp_buf[0] = 0;
+  if (tuh_descriptor_get_product_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
+    _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
+    printf((const char*) temp_buf);
+  }
+  printf("\r\n");
 
-  printf("  bNumConfigurations  %u\r\n", desc_device.bNumConfigurations);
+  printf("  iSerialNumber       %u     "     , desc_device.iSerialNumber);
+  _get_string_result = 0xff;
+  temp_buf[0] = 0;
+  if (tuh_descriptor_get_serial_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
+    _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
+    printf((const char*) temp_buf);
+  }
+  printf("\r\n");
+
+  printf("  bNumConfigurations  %u\r\n"     , desc_device.bNumConfigurations);
 
   return true;
 }
@@ -107,7 +192,7 @@ void tuh_mount_cb (uint8_t daddr)
 {
   printf("Device attached, address = %d\r\n", daddr);
 
-  // get device descriptor
+  // Get Device Descriptor
   tuh_descriptor_get_device(daddr, &desc_device, 18, print_device_descriptor);
 }
 
diff --git a/examples/host/device_info/CMakeLists.txt b/examples/host/device_info/CMakeLists.txt
deleted file mode 100644
index bff281a8c..000000000
--- a/examples/host/device_info/CMakeLists.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-cmake_minimum_required(VERSION 3.5)
-
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
-
-# gets PROJECT name for the example
-family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-
-project(${PROJECT})
-
-# Checks this example is valid for the family and initializes the project
-family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
-
-add_executable(${PROJECT})
-
-# Example source
-target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        )
-
-# Example include
-target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
-
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/host/device_info/Makefile b/examples/host/device_info/Makefile
deleted file mode 100644
index c59369ffa..000000000
--- a/examples/host/device_info/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-include ../../../tools/top.mk
-include ../../make.mk
-
-INC += \
-	src \
-	$(TOP)/hw \
-
-# Example source
-EXAMPLE_SOURCE += \
-	src/main.c
-
-SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
-
-# TODO: suppress warning caused by host stack
-CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
-
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/host/usbh_control.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
-include ../../rules.mk
diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt
deleted file mode 100644
index 7fe4e3f5c..000000000
--- a/examples/host/device_info/only.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-mcu:LPC175X_6X
-mcu:LPC177X_8X
-mcu:LPC18XX
-mcu:LPC40XX
-mcu:LPC43XX
-mcu:MIMXRT10XX
-mcu:RP2040
-mcu:MSP432E4
-mcu:RX65X
diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c
deleted file mode 100644
index e6149db89..000000000
--- a/examples/host/device_info/src/main.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2022 Scott Shawcroft for Adafruit Industries
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-/* This example prints out info about the enumerated devices. */
-
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-
-#include "bsp/board.h"
-#include "tusb.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF PROTYPES
-//--------------------------------------------------------------------+
-void led_blinking_task(void);
-
-static xfer_result_t _get_string_result;
-
-static bool _transfer_done_cb(uint8_t daddr, tusb_control_request_t const *request, xfer_result_t result) {
-    (void)daddr;
-    (void)request;
-    _get_string_result = result;
-    return true;
-}
-
-static void _convert_utf16le_to_utf8(const uint16_t *utf16, size_t utf16_len, uint8_t *utf8, size_t utf8_len) {
-    // TODO: Check for runover.
-    (void)utf8_len;
-    // Get the UTF-16 length out of the data itself.
-
-    for (size_t i = 0; i < utf16_len; i++) {
-        uint16_t chr = utf16[i];
-        if (chr < 0x80) {
-            *utf8++ = chr & 0xff;
-        } else if (chr < 0x800) {
-            *utf8++ = (uint8_t)(0xC0 | (chr >> 6 & 0x1F));
-            *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
-        } else {
-            // TODO: Verify surrogate.
-            *utf8++ = (uint8_t)(0xE0 | (chr >> 12 & 0x0F));
-            *utf8++ = (uint8_t)(0x80 | (chr >> 6 & 0x3F));
-            *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
-        }
-        // TODO: Handle UTF-16 code points that take two entries.
-    }
-}
-
-// Count how many bytes a utf-16-le encoded string will take in utf-8.
-static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
-    size_t total_bytes = 0;
-    for (size_t i = 0; i < len; i++) {
-        uint16_t chr = buf[i];
-        if (chr < 0x80) {
-            total_bytes += 1;
-        } else if (chr < 0x800) {
-            total_bytes += 2;
-        } else {
-            total_bytes += 3;
-        }
-        // TODO: Handle UTF-16 code points that take two entries.
-    }
-    return total_bytes;
-}
-
-static void _wait_and_convert(uint16_t *temp_buf, size_t buf_len) {
-    while (_get_string_result == 0xff) {
-        tuh_task();
-    }
-    if (_get_string_result != XFER_RESULT_SUCCESS) {
-        temp_buf[0] = 0;
-        return;
-    }
-    size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
-    size_t utf8_len = _count_utf8_bytes(temp_buf + 1, utf16_len);
-    _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
-    ((uint8_t*) temp_buf)[utf8_len] = '\0';
-}
-
-/*------------- MAIN -------------*/
-int main(void)
-{
-  board_init();
-
-  printf("TinyUSB Host Device Info Example\r\n");
-
-  tusb_init();
-
-  uint32_t interval_ms = 5000;
-  uint32_t start_time = 0;
-
-  while (1)
-  {
-    // tinyusb host task
-    tuh_task();
-    led_blinking_task();
-
-    if (board_millis() - start_time < interval_ms) {
-      continue;
-    }
-    start_time = board_millis();
-    // Brute force check every device address to see if it is active.
-    for (int i = 1; i < CFG_TUH_DEVICE_MAX + CFG_TUH_HUB + 1; i++) {
-      if (!tuh_ready(i)) {
-        continue;
-      }
-      uint16_t vid;
-      uint16_t pid;
-      tuh_vid_pid_get(i, &vid, &pid);
-      printf("%d vid %04x pid %04x\r\n", i, vid, pid);
-
-      tusb_speed_t speed = tuh_speed_get(i);
-      switch (speed) {
-        case TUSB_SPEED_FULL:
-          printf("Full speed\r\n");
-          break;
-        case TUSB_SPEED_LOW:
-          printf("Low speed\r\n");
-          break;
-        case TUSB_SPEED_HIGH:
-          printf("High speed\r\n");
-          break;
-        default:
-          break;
-      }
-
-      _get_string_result = 0xff;
-      uint16_t temp_buf[127];
-      if (tuh_descriptor_string_serial_get(i, 0, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
-        _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
-        printf("Serial: %s\r\n", (const char*) temp_buf);
-      }
-
-      _get_string_result = 0xff;
-      temp_buf[0] = 0;
-      if (tuh_descriptor_string_product_get(i, 0, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
-        _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
-        printf("Product: %s\r\n", (const char*) temp_buf);
-      }
-
-      _get_string_result = 0xff;
-      temp_buf[0] = 0;
-      if (tuh_descriptor_string_manufacturer_get(i, 0, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
-        _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
-        printf("Manufacturer: %s\r\n", (const char*) temp_buf);
-      }
-    }
-    printf("\n");
-  }
-
-  return 0;
-}
-
-
-//--------------------------------------------------------------------+
-// Blinking Task
-//--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
-  const uint32_t interval_ms = 1000;
-  static uint32_t start_ms = 0;
-
-  static bool led_state = false;
-
-  // Blink every interval ms
-  if ( board_millis() - start_ms < interval_ms) return; // not enough time
-  start_ms += interval_ms;
-
-  board_led_write(led_state);
-  led_state = 1 - led_state; // toggle
-}
diff --git a/examples/host/device_info/src/tusb_config.h b/examples/host/device_info/src/tusb_config.h
deleted file mode 100644
index 6b413e46f..000000000
--- a/examples/host/device_info/src/tusb_config.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#ifndef _TUSB_CONFIG_H_
-#define _TUSB_CONFIG_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//--------------------------------------------------------------------
-// COMMON CONFIGURATION
-//--------------------------------------------------------------------
-
-// defined by compiler flags for flexibility
-#ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-  #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
-#else
-  #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
-#endif
-
-#ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS                 OPT_OS_NONE
-#endif
-
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
-
-/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
- * Tinyusb use follows macros to declare transferring memory so that they can be put
- * into those specific section.
- * e.g
- * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
- * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
- */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
-#endif
-
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
-#endif
-
-//--------------------------------------------------------------------
-// CONFIGURATION
-//--------------------------------------------------------------------
-
-// Size of buffer to hold descriptors and other data used for enumeration
-#define CFG_TUH_ENUMERATION_BUFSIZE 256
-
-// only hub class is enabled
-#define CFG_TUH_HUB                 1
-
-// max device support (excluding hub device)
-// 1 hub typically has 4 ports
-#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1)
-
-#define CFG_TUH_ENDPOINT_MAX       8
-
-#define CFG_TUH_TASK_QUEUE_SZ       64
-
-//------------- HID -------------//
-
-#define CFG_TUH_HID_EP_BUFSIZE      64
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_CONFIG_H_ */
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 11bf2f997..617aff79a 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -535,7 +535,7 @@ void tuh_task(void)
       break;
 
       case HCD_EVENT_DEVICE_REMOVE:
-        TU_LOG2("USBH DEVICE REMOVED\r\n");
+        TU_LOG2("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
         process_device_unplugged(event.rhport, event.connection.hub_addr, event.connection.hub_port);
 
         #if CFG_TUH_HUB
@@ -924,6 +924,8 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
         (hub_port == 0 || dev->hub_port == hub_port) &&
         dev->connected)
     {
+      TU_LOG2("  Address = %u\r\n", dev_addr);
+
       // Invoke callback before close driver
       if (tuh_umount_cb) tuh_umount_cb(dev_addr);
 

From bcdeb386cc4d3afb3d7213c961e4611e511c4e97 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Mar 2022 21:57:55 +0700
Subject: [PATCH 0895/2085] rework usbh control xfer

- change API of tuh_control_xfer and its callback
- rename tuh_control_complete_cb_t to tuh_control_xfer_cb_t
- add user argument to control callback
- migrate usbh and hub
---
 examples/host/bare_api/src/main.c |  16 +-
 src/class/cdc/cdc_host.c          |   2 +-
 src/class/cdc/cdc_host.h          |   6 +-
 src/host/hub.c                    | 148 +++++++++------
 src/host/hub.h                    |   8 +-
 src/host/usbh.c                   | 292 +++++++++++++++++-------------
 src/host/usbh.h                   |  70 ++++---
 7 files changed, 315 insertions(+), 227 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 73e97c390..6888d13a2 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -70,9 +70,9 @@ tusb_desc_device_t desc_device;
 
 static volatile xfer_result_t _get_string_result;
 
-static bool _transfer_done_cb(uint8_t daddr, tusb_control_request_t const *request, xfer_result_t result) {
+static bool _transfer_done_cb(uint8_t daddr, tuh_control_xfer_t const *xfer, xfer_result_t result) {
     (void)daddr;
-    (void)request;
+    (void)xfer;
     _get_string_result = result;
     return true;
 }
@@ -130,9 +130,9 @@ static void _wait_and_convert(uint16_t *temp_buf, size_t buf_len) {
     ((uint8_t*) temp_buf)[utf8_len] = '\0';
 }
 
-bool print_device_descriptor(uint8_t daddr, tusb_control_request_t const * request, xfer_result_t result)
+bool print_device_descriptor(uint8_t daddr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) request;
+  (void) xfer;
 
   if ( XFER_RESULT_SUCCESS != result )
   {
@@ -158,7 +158,7 @@ bool print_device_descriptor(uint8_t daddr, tusb_control_request_t const * reque
 
   printf("  iManufacturer       %u     "     , desc_device.iManufacturer);
   temp_buf[0] = 0;
-  if (tuh_descriptor_get_manufacturer_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
+  if (tuh_descriptor_get_manufacturer_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb, 0)) {
     _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
     printf((const char*) temp_buf);
   }
@@ -167,7 +167,7 @@ bool print_device_descriptor(uint8_t daddr, tusb_control_request_t const * reque
   printf("  iProduct            %u     "     , desc_device.iProduct);
   _get_string_result = 0xff;
   temp_buf[0] = 0;
-  if (tuh_descriptor_get_product_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
+  if (tuh_descriptor_get_product_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb, 0)) {
     _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
     printf((const char*) temp_buf);
   }
@@ -176,7 +176,7 @@ bool print_device_descriptor(uint8_t daddr, tusb_control_request_t const * reque
   printf("  iSerialNumber       %u     "     , desc_device.iSerialNumber);
   _get_string_result = 0xff;
   temp_buf[0] = 0;
-  if (tuh_descriptor_get_serial_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb)) {
+  if (tuh_descriptor_get_serial_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb, 0)) {
     _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
     printf((const char*) temp_buf);
   }
@@ -193,7 +193,7 @@ void tuh_mount_cb (uint8_t daddr)
   printf("Device attached, address = %d\r\n", daddr);
 
   // Get Device Descriptor
-  tuh_descriptor_get_device(daddr, &desc_device, 18, print_device_descriptor);
+  tuh_descriptor_get_device(daddr, &desc_device, 18, print_device_descriptor, 0);
 }
 
 /// Invoked when device is unmounted (bus reset/unplugged)
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 2787cd201..6a29f3f43 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -120,7 +120,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
   return usbh_edpt_xfer(dev_addr, ep_in, p_buffer, length);
 }
 
-bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_complete_cb_t complete_cb)
+bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_xfer_cb_t complete_cb)
 {
   cdch_data_t const * p_cdc = get_itf(dev_addr);
   tusb_control_request_t const request =
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 0d435138b..67162a0ca 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -42,14 +42,14 @@
  * \defgroup   CDC_Serial_Host Host
  * @{ */
 
-bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_complete_cb_t complete_cb);
+bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_xfer_cb_t complete_cb);
 
-static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_control_complete_cb_t complete_cb)
+static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_control_xfer_cb_t complete_cb)
 {
   return tuh_cdc_set_control_line_state(dev_addr, true, true, complete_cb);
 }
 
-static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_control_complete_cb_t complete_cb)
+static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_control_xfer_cb_t complete_cb)
 {
   return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb);
 }
diff --git a/src/host/hub.c b/src/host/hub.c
index 4c375c290..a0cf7b7e5 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -77,71 +77,92 @@ static char const* const _hub_feature_str[] =
 //--------------------------------------------------------------------+
 // HUB
 //--------------------------------------------------------------------+
-bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb)
+bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_xfer_cb_t complete_cb)
 {
-  tusb_control_request_t const request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_OTHER,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_OTHER,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HUB_REQUEST_CLEAR_FEATURE,
+      .wValue   = feature,
+      .wIndex   = hub_port,
+      .wLength  = 0
     },
-    .bRequest = HUB_REQUEST_CLEAR_FEATURE,
-    .wValue   = feature,
-    .wIndex   = hub_port,
-    .wLength  = 0
+
+    .buffer      = NULL,
+    .complete_cb = complete_cb,
+    .user_arg    = 0
   };
 
   TU_LOG2("HUB Clear Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port);
-  TU_ASSERT( tuh_control_xfer(hub_addr, &request, NULL, complete_cb) );
+  TU_ASSERT( tuh_control_xfer(hub_addr, &xfer) );
   return true;
 }
 
-bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb)
+bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_xfer_cb_t complete_cb)
 {
-  tusb_control_request_t const request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_OTHER,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_OTHER,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HUB_REQUEST_SET_FEATURE,
+      .wValue   = feature,
+      .wIndex   = hub_port,
+      .wLength  = 0
     },
-    .bRequest = HUB_REQUEST_SET_FEATURE,
-    .wValue   = feature,
-    .wIndex   = hub_port,
-    .wLength  = 0
+
+    .buffer      = NULL,
+    .complete_cb = complete_cb,
+    .user_arg    = 0
   };
 
   TU_LOG2("HUB Set Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port);
-  TU_ASSERT( tuh_control_xfer(hub_addr, &request, NULL, complete_cb) );
+  TU_ASSERT( tuh_control_xfer(hub_addr, &xfer) );
   return true;
 }
 
-bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_complete_cb_t complete_cb)
+bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_xfer_cb_t complete_cb)
 {
   return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb);
 }
 
-bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_complete_cb_t complete_cb)
+bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_xfer_cb_t complete_cb)
 {
-  tusb_control_request_t const request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_OTHER,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_IN
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_OTHER,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_IN
+      },
+      .bRequest = HUB_REQUEST_GET_STATUS,
+      .wValue   = 0,
+      .wIndex   = hub_port,
+      .wLength  = 4
     },
-    .bRequest = HUB_REQUEST_GET_STATUS,
-    .wValue   = 0,
-    .wIndex   = hub_port,
-    .wLength  = 4
+
+    .buffer      = resp,
+    .complete_cb = complete_cb,
+    .user_arg    = 0
   };
 
   TU_LOG2("HUB Get Port Status: addr = %u port = %u\r\n", hub_addr, hub_port);
-  TU_ASSERT( tuh_control_xfer( hub_addr, &request, resp, complete_cb) );
+  TU_ASSERT( tuh_control_xfer( hub_addr, &xfer) );
   return true;
 }
 
@@ -200,8 +221,8 @@ bool hub_edpt_status_xfer(uint8_t dev_addr)
 // Set Configure
 //--------------------------------------------------------------------+
 
-static bool config_set_port_power (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool config_port_power_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
 
 bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
@@ -209,28 +230,35 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
   TU_ASSERT(itf_num == p_hub->itf_num);
 
   // Get Hub Descriptor
-  tusb_control_request_t const request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_IN
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_DEVICE,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_IN
+      },
+      .bRequest = HUB_REQUEST_GET_DESCRIPTOR,
+      .wValue   = 0,
+      .wIndex   = 0,
+      .wLength  = sizeof(descriptor_hub_desc_t)
     },
-    .bRequest = HUB_REQUEST_GET_DESCRIPTOR,
-    .wValue   = 0,
-    .wIndex   = 0,
-    .wLength  = sizeof(descriptor_hub_desc_t)
+
+    .buffer      = _hub_buffer,
+    .complete_cb = config_set_port_power,
+    .user_arg    = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &request, _hub_buffer, config_set_port_power) );
+  TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
 
   return true;
 }
 
-static bool config_set_port_power (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) request;
+  (void) xfer;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
@@ -246,12 +274,12 @@ static bool config_set_port_power (uint8_t dev_addr, tusb_control_request_t cons
   return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete);
 }
 
-static bool config_port_power_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
    hub_interface_t* p_hub = get_itf(dev_addr);
 
-  if (request->wIndex == p_hub->port_count)
+  if (xfer->request.wIndex == p_hub->port_count)
   {
     // All ports are power -> queue notification status endpoint and
     // complete the SET CONFIGURATION
@@ -261,7 +289,7 @@ static bool config_port_power_complete (uint8_t dev_addr, tusb_control_request_t
   }else
   {
     // power next port
-    uint8_t const hub_port = (uint8_t) (request->wIndex + 1);
+    uint8_t const hub_port = (uint8_t) (xfer->request.wIndex + 1);
     return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete);
   }
 
@@ -272,9 +300,9 @@ static bool config_port_power_complete (uint8_t dev_addr, tusb_control_request_t
 // Connection Changes
 //--------------------------------------------------------------------+
 
-static bool connection_get_status_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool connection_clear_conn_change_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool connection_port_reset_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
 
 // callback as response of interrupt endpoint polling
 bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
@@ -302,12 +330,12 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   return true;
 }
 
-static bool connection_get_status_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
-  uint8_t const port_num = (uint8_t) request->wIndex;
+  uint8_t const port_num = (uint8_t) xfer->request.wIndex;
 
   // Connection change
   if (p_hub->port_status.change.connection)
@@ -330,12 +358,12 @@ static bool connection_get_status_complete (uint8_t dev_addr, tusb_control_reque
   return true;
 }
 
-static bool connection_clear_conn_change_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
-  uint8_t const port_num = (uint8_t) request->wIndex;
+  uint8_t const port_num = (uint8_t) xfer->request.wIndex;
 
   if ( p_hub->port_status.status.connection )
   {
@@ -361,12 +389,12 @@ static bool connection_clear_conn_change_complete (uint8_t dev_addr, tusb_contro
   return true;
 }
 
-static bool connection_port_reset_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
 
   // hub_interface_t* p_hub = get_itf(dev_addr);
-  uint8_t const port_num = (uint8_t) request->wIndex;
+  uint8_t const port_num = (uint8_t) xfer->request.wIndex;
 
   // submit attach event
   hcd_event_t event =
diff --git a/src/host/hub.h b/src/host/hub.h
index 6d81f6773..a5d8704d3 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -171,11 +171,11 @@ typedef struct {
 
 TU_VERIFY_STATIC( sizeof(hub_port_status_response_t) == 4, "size is not correct");
 
-bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb);
-bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb);
+bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_xfer_cb_t complete_cb);
+bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_xfer_cb_t complete_cb);
 
-bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_complete_cb_t complete_cb);
-bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_complete_cb_t complete_cb);
+bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_xfer_cb_t complete_cb);
+bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_xfer_cb_t complete_cb);
 bool hub_edpt_status_xfer(uint8_t dev_addr);
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 617aff79a..a8692c8e5 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -111,15 +111,6 @@ typedef struct {
 
 } usbh_device_t;
 
-typedef struct
-{
-  tusb_control_request_t request TU_ATTR_ALIGNED(4);
-  uint8_t* buffer;
-  tuh_control_complete_cb_t complete_cb;
-
-  uint8_t daddr;
-} usbh_control_xfer_t;
-
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -250,7 +241,8 @@ static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 // We will only execute control transfer one at a time.
 struct
 {
-  usbh_control_xfer_t xfer;
+  tuh_control_xfer_t xfer;
+  uint8_t daddr;  // device address that is transferring
   uint8_t stage;
 }_ctrl_xfer;
 
@@ -308,132 +300,165 @@ void osal_task_delay(uint32_t msec)
 // Descriptors
 //--------------------------------------------------------------------+
 
-bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
+                        tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
-  tusb_control_request_t const request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_DEVICE,
+        .type      = TUSB_REQ_TYPE_STANDARD,
+        .direction = TUSB_DIR_IN
+      },
+      .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+      .wValue   = tu_htole16( TU_U16(type, index) ),
+      .wIndex   = 0,
+      .wLength  = tu_htole16(len)
     },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = tu_htole16( TU_U16(type, index) ),
-    .wIndex   = 0,
-    .wLength  = tu_htole16(len)
+
+    .buffer      = buffer,
+    .complete_cb = complete_cb,
+    .user_arg    = user_arg
   };
 
-  TU_ASSERT( tuh_control_xfer(daddr, &request, buffer, complete_cb) );
-
-  return true;
+  return tuh_control_xfer(daddr, &xfer);
 }
 
-bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
+                               tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   len = tu_min16(len, sizeof(tusb_desc_device_t));
-  return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb);
+  return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb, user_arg);
 }
 
-bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len,
+                                      tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
-  return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb);
+  return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb, user_arg);
 }
 
-bool tuh_descriptor_get_string(uint8_t daddr, uint16_t language_id, uint8_t index,
-                               void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_string(uint8_t daddr, uint16_t language_id, uint8_t index, void* buffer, uint16_t len,
+                               tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
-  tusb_control_request_t const request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_DEVICE,
+        .type      = TUSB_REQ_TYPE_STANDARD,
+        .direction = TUSB_DIR_IN
+      },
+      .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+      .wValue   = tu_htole16( TU_U16(TUSB_DESC_STRING, index) ),
+      .wIndex   = tu_htole16(language_id),
+      .wLength  = tu_htole16(len)
     },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = tu_htole16( TU_U16(TUSB_DESC_STRING, index) ),
-    .wIndex   = tu_htole16(language_id),
-    .wLength  = tu_htole16(len)
+
+    .buffer      = buffer,
+    .complete_cb = complete_cb,
+    .user_arg    = user_arg
   };
 
-  TU_ASSERT( tuh_control_xfer(daddr, &request, buffer, complete_cb) );
-  return true;
+  return tuh_control_xfer(daddr, &xfer);
 }
 
 // Get manufacturer string descriptor
-bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
+                                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
   if (dev->i_manufacturer == 0) {
     return false;
   }
-  return tuh_descriptor_get_string(daddr, language_id, dev->i_manufacturer, buffer, len, complete_cb);
+  return tuh_descriptor_get_string(daddr, language_id, dev->i_manufacturer, buffer, len, complete_cb, user_arg);
 }
 
 // Get product string descriptor
-bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
+                                       tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
   if (dev->i_product == 0) {
     return false;
   }
-  return tuh_descriptor_get_string(daddr, language_id, dev->i_product, buffer, len, complete_cb);
+  return tuh_descriptor_get_string(daddr, language_id, dev->i_product, buffer, len, complete_cb, user_arg);
 }
 
 // Get serial string descriptor
-bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
+                                      tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
   if (dev->i_serial == 0) {
     return false;
   }
-  return tuh_descriptor_get_string(daddr, language_id, dev->i_serial, buffer, len, complete_cb);
+  return tuh_descriptor_get_string(daddr, language_id, dev->i_serial, buffer, len, complete_cb, user_arg);
 }
 
 // Get HID report descriptor
-bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb)
+bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, void* buffer, uint16_t len,
+                                   tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   TU_LOG2("HID Get Report Descriptor\r\n");
-  tusb_control_request_t const request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_IN
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_STANDARD,
+        .direction = TUSB_DIR_IN
+      },
+      .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+      .wValue   = tu_htole16(TU_U16(desc_type, 0)),
+      .wIndex   = itf_num,
+      .wLength  = len
     },
-    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-    .wValue   = tu_htole16(TU_U16(desc_type, 0)),
-    .wIndex   = itf_num,
-    .wLength  = len
+
+    .buffer      = buffer,
+    .complete_cb = complete_cb,
+    .user_arg    = user_arg
   };
 
-  return tuh_control_xfer(daddr, &request, buffer, complete_cb);
+  return tuh_control_xfer(daddr, &xfer);
 }
 
-bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_control_complete_cb_t complete_cb)
+bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
+                           tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   TU_LOG2("Set Configuration = %d\r\n", config_num);
-  tusb_control_request_t const request =
+
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_OUT
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_DEVICE,
+        .type      = TUSB_REQ_TYPE_STANDARD,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = TUSB_REQ_SET_CONFIGURATION,
+      .wValue   = tu_htole16(config_num),
+      .wIndex   = 0,
+      .wLength  = 0
     },
-    .bRequest = TUSB_REQ_SET_CONFIGURATION,
-    .wValue   = tu_htole16(config_num),
-    .wIndex   = 0,
-    .wLength  = 0
+
+    .buffer      = NULL,
+    .complete_cb = complete_cb,
+    .user_arg    = user_arg
   };
 
-  TU_ASSERT( tuh_control_xfer(daddr, &request, NULL, complete_cb) );
-  return true;
+  return tuh_control_xfer(daddr, &xfer);
 }
 
 //--------------------------------------------------------------------+
@@ -460,7 +485,7 @@ bool tuh_init(uint8_t rhport)
   TU_LOG2("USBH init\r\n");
   TU_LOG2_INT(sizeof(usbh_device_t));
   TU_LOG2_INT(sizeof(hcd_event_t));
-  TU_LOG2_INT(sizeof(usbh_control_xfer_t));
+  TU_LOG2_INT(sizeof(tuh_control_xfer_t));
 
   // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -808,7 +833,7 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
 // Control transfer
 //--------------------------------------------------------------------+
 
-bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
+bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer)
 {
   // pre-check to help reducing mutex lock
   TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
@@ -824,16 +849,13 @@ bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, voi
 
   const uint8_t rhport = usbh_get_rhport(daddr);
 
-  TU_LOG2("[%u:%u] %s: ", rhport, daddr, request->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[request->bRequest] : "Unknown Request");
-  TU_LOG2_VAR(request);
+  TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->request.bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->request.bRequest] : "Unknown Request");
+  TU_LOG2_VAR(&xfer->request);
   TU_LOG2("\r\n");
 
-  _ctrl_xfer.xfer.request     = (*request);
-  _ctrl_xfer.xfer.buffer      = buffer;
-  _ctrl_xfer.xfer.complete_cb = complete_cb;
-  _ctrl_xfer.xfer.daddr       = daddr;
-
-  return hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.xfer.request);
+  _ctrl_xfer.daddr = daddr;
+  _ctrl_xfer.xfer = (*xfer);
+  return hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.xfer.request);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void set_control_xfer_stage(uint8_t stage)
@@ -851,7 +873,12 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
   _ctrl_xfer.stage = CONTROL_STAGE_IDLE;
   usbh_unlock();
 
-  if (_ctrl_xfer.xfer.complete_cb) _ctrl_xfer.xfer.complete_cb(dev_addr, &_ctrl_xfer.xfer.request, result);
+  if (_ctrl_xfer.xfer.complete_cb)
+  {
+    // duplicate xfer since user can execute control transfer within callback
+    tuh_control_xfer_t const xfer_temp = _ctrl_xfer.xfer;
+    _ctrl_xfer.xfer.complete_cb(dev_addr, &xfer_temp, result);
+  }
 }
 
 static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
@@ -939,7 +966,7 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
       hcd_device_close(rhport, dev_addr);
       clear_device(dev);
       // abort on-going control xfer if any
-      if (_ctrl_xfer.xfer.daddr == dev_addr) set_control_xfer_stage(CONTROL_STAGE_IDLE);
+      if (_ctrl_xfer.daddr == dev_addr) set_control_xfer_stage(CONTROL_STAGE_IDLE);
     }
   }
 }
@@ -954,14 +981,14 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
 //--------------------------------------------------------------------+
 
 static bool enum_request_addr0_device_desc(void);
-static bool enum_get_addr0_device_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_get_addr0_device_desc_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
 
 static bool enum_request_set_addr(void);
-static bool enum_set_address_complete           (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool enum_get_device_desc_complete       (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool enum_get_9byte_config_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool enum_get_config_desc_complete       (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool enum_set_config_complete            (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_set_address_complete           (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool enum_get_device_desc_complete       (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool enum_get_9byte_config_desc_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool enum_get_config_desc_complete       (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool enum_set_config_complete            (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
 static bool parse_configuration_descriptor      (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
 
 static uint8_t get_new_address(bool is_hub);
@@ -973,15 +1000,15 @@ static void enum_full_complete(void);
 // New device (reset on the way) -> Get Status 0 -> Clear Reset 0 -> Get 8byte Device Descriptor
 //   -> Port Reset 1 -> reset delay -> Get Status 1 -> Clear Reset 1 -> queue hub interrupt endpoint
 
-static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool enum_hub_clear_reset0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool enum_hub_set_reset1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool enum_hub_get_status1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_hub_get_status0_complete  (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool enum_hub_clear_reset0_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool enum_hub_set_reset1_complete   (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool enum_hub_get_status1_complete  (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool enum_hub_clear_reset1_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
 
-static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_hub_get_status0_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) dev_addr; (void) request;
+  (void) dev_addr; (void) xfer;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   hub_port_status_response_t port_status;
@@ -1006,17 +1033,17 @@ static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request
   return true;
 }
 
-static bool enum_hub_clear_reset0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_hub_clear_reset0_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) dev_addr; (void) request;
+  (void) dev_addr; (void) xfer;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
   enum_request_addr0_device_desc();
   return true;
 }
 
-static bool enum_hub_set_reset1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_hub_set_reset1_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) dev_addr; (void) request;
+  (void) dev_addr; (void) xfer;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   osal_task_delay(RESET_DELAY);
@@ -1026,9 +1053,9 @@ static bool enum_hub_set_reset1_complete(uint8_t dev_addr, tusb_control_request_
   return true;
 }
 
-static bool enum_hub_get_status1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_hub_get_status1_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) dev_addr; (void) request;
+  (void) dev_addr; (void) xfer;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   hub_port_status_response_t port_status;
@@ -1043,9 +1070,9 @@ static bool enum_hub_get_status1_complete(uint8_t dev_addr, tusb_control_request
   return true;
 }
 
-static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) dev_addr; (void) request;
+  (void) dev_addr; (void) xfer;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   enum_request_set_addr();
@@ -1096,14 +1123,14 @@ static bool enum_request_addr0_device_desc(void)
 
   // Get first 8 bytes of device descriptor for Control Endpoint size
   TU_LOG2("Get 8 byte of Device Descriptor\r\n");
-  TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, enum_get_addr0_device_desc_complete));
+  TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, enum_get_addr0_device_desc_complete, 0));
   return true;
 }
 
 // After Get Device Descriptor of Address 0
-static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) request;
+  (void) xfer;
   TU_ASSERT(0 == dev_addr);
 
   if (XFER_RESULT_SUCCESS != result)
@@ -1157,33 +1184,40 @@ static bool enum_request_set_addr(void)
   new_dev->connected = 1;
   new_dev->ep0_size  = desc_device->bMaxPacketSize0;
 
-  tusb_control_request_t const new_request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_STANDARD,
-      .direction = TUSB_DIR_OUT
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_DEVICE,
+        .type      = TUSB_REQ_TYPE_STANDARD,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = TUSB_REQ_SET_ADDRESS,
+      .wValue   = tu_htole16(new_addr),
+      .wIndex   = 0,
+      .wLength  = 0
     },
-    .bRequest = TUSB_REQ_SET_ADDRESS,
-    .wValue   = tu_htole16(new_addr),
-    .wIndex   = 0,
-    .wLength  = 0
+
+    .buffer      = NULL,
+    .complete_cb = enum_set_address_complete,
+    .user_arg    = 0
   };
 
   uint8_t const addr0 = 0;
-  TU_ASSERT( tuh_control_xfer(addr0, &new_request, NULL, enum_set_address_complete) );
+  TU_ASSERT( tuh_control_xfer(addr0, &xfer) );
 
   return true;
 }
 
 // After SET_ADDRESS is complete
-static bool enum_set_address_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_set_address_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
   TU_ASSERT(0 == dev_addr);
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
-  uint8_t const new_addr = (uint8_t const) request->wValue;
+  uint8_t const new_addr = (uint8_t const) xfer->request.wValue;
 
   usbh_device_t* new_dev = get_device(new_addr);
   new_dev->addressed = 1;
@@ -1197,13 +1231,13 @@ static bool enum_set_address_complete(uint8_t dev_addr, tusb_control_request_t c
   // Get full device descriptor
   TU_LOG2("Get Device Descriptor\r\n");
 
-  TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), enum_get_device_desc_complete));
+  TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), enum_get_device_desc_complete, 0));
   return true;
 }
 
-static bool enum_get_device_desc_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_get_device_desc_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) request;
+  (void) xfer;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
@@ -1220,13 +1254,13 @@ static bool enum_get_device_desc_complete(uint8_t dev_addr, tusb_control_request
   // Get 9-byte for total length
   uint8_t const config_idx = CONFIG_NUM - 1;
   TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n");
-  TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, 9, enum_get_9byte_config_desc_complete) );
+  TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, 9, enum_get_9byte_config_desc_complete, 0) );
   return true;
 }
 
-static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) request;
+  (void) xfer;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   // TODO not enough buffer to hold configuration descriptor
@@ -1240,26 +1274,26 @@ static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tusb_control_r
   // Get full configuration descriptor
   uint8_t const config_idx = CONFIG_NUM - 1;
   TU_LOG2("Get Configuration[0] Descriptor\r\n");
-  TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, total_len, enum_get_config_desc_complete) );
+  TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, total_len, enum_get_config_desc_complete, 0) );
   return true;
 }
 
-static bool enum_get_config_desc_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_get_config_desc_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) request;
+  (void) xfer;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   // Parse configuration & set up drivers
   // Driver open aren't allowed to make any usb transfer yet
   TU_ASSERT( parse_configuration_descriptor(dev_addr, (tusb_desc_configuration_t*) _usbh_ctrl_buf) );
 
-  TU_ASSERT( tuh_configuration_set(dev_addr, CONFIG_NUM, enum_set_config_complete) );
+  TU_ASSERT( tuh_configuration_set(dev_addr, CONFIG_NUM, enum_set_config_complete, 0) );
   return true;
 }
 
-static bool enum_set_config_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool enum_set_config_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) request;
+  (void) xfer;
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
   TU_LOG2("Device configured\r\n");
diff --git a/src/host/usbh.h b/src/host/usbh.h
index eec2ed702..d836d9593 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -38,7 +38,19 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-typedef bool (*tuh_control_complete_cb_t)(uint8_t daddr, tusb_control_request_t const * request, xfer_result_t result);
+// forward declaration
+struct tuh_control_xfer_s;
+typedef struct tuh_control_xfer_s tuh_control_xfer_t;
+
+typedef bool (*tuh_control_xfer_cb_t)(uint8_t daddr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+
+struct tuh_control_xfer_s
+{
+  tusb_control_request_t request TU_ATTR_ALIGNED(4);
+  uint8_t* buffer;
+  tuh_control_xfer_cb_t complete_cb;
+  uintptr_t user_arg;
+};
 
 //--------------------------------------------------------------------+
 // APPLICATION API
@@ -81,40 +93,54 @@ static inline bool tuh_ready(uint8_t daddr)
 }
 
 // Carry out a control transfer
-// true on success, false if there is on-going control trasnfer
-bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
+// true on success, false if there is on-going control transfer
+// Note: function is blocking if complete callback is NULL
+bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer);
+
+// Carry out a control transfer
+// true on success, false if there is on-going control transfer
+// Note: function is blocking if complete callback is NULL
+//bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer,
+//                       tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Set Configuration
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
-bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_control_complete_cb_t complete_cb);
+bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
+                           tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 //------------- descriptors -------------//
 
 // Get an descriptor
-bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index,
-                        void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
+                        tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get device descriptor
-bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
+                               tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get configuration descriptor
-bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
-
-// Get string descriptor
-bool tuh_descriptor_get_string(uint8_t daddr, uint16_t language_id, uint8_t index,
-                               void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
-
-// Get manufacturer string descriptor
-bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
-
-// Get product string descriptor
-bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
-
-// Get serial string descriptor
-bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len,
+                                      tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get HID report descriptor
-bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, void* buffer, uint16_t len, tuh_control_complete_cb_t complete_cb);
+bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, void* buffer, uint16_t len,
+                                   tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+
+// Get string descriptor
+bool tuh_descriptor_get_string(uint8_t daddr, uint16_t language_id, uint8_t index, void* buffer, uint16_t len,
+                               tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+
+// Get manufacturer string descriptor
+bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
+                                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+
+// Get product string descriptor
+bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
+                                       tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+
+// Get serial string descriptor
+bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
+                                      tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 //--------------------------------------------------------------------+
 // APPLICATION CALLBACK

From ec28593ce56a9a1726cfe8a43f6a8c421fd3916b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 11 Mar 2022 22:13:57 +0700
Subject: [PATCH 0896/2085] update hid,msc to new usbh control API

---
 examples/host/cdc_msc_hid/src/main.c |  27 +++--
 src/class/cdc/cdc_host.c             |  29 ++++--
 src/class/hid/hid_host.c             | 148 ++++++++++++++++-----------
 src/class/msc/msc_host.c             |  33 +++---
 4 files changed, 139 insertions(+), 98 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index a14be05ea..0fc7ef146 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -71,20 +71,6 @@ int main(void)
 #if CFG_TUH_CDC
 CFG_TUSB_MEM_SECTION static char serial_in_buffer[64] = { 0 };
 
-void tuh_mount_cb(uint8_t dev_addr)
-{
-  // application set-up
-  printf("A device with address %d is mounted\r\n", dev_addr);
-
-  tuh_cdc_receive(dev_addr, serial_in_buffer, sizeof(serial_in_buffer), true); // schedule first transfer
-}
-
-void tuh_umount_cb(uint8_t dev_addr)
-{
-  // application tear-down
-  printf("A device with address %d is unmounted \r\n", dev_addr);
-}
-
 // invoked ISR context
 void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes)
 {
@@ -109,6 +95,19 @@ void cdc_task(void)
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
 
+void tuh_mount_cb(uint8_t dev_addr)
+{
+  // application set-up
+  printf("A device with address %d is mounted\r\n", dev_addr);
+}
+
+void tuh_umount_cb(uint8_t dev_addr)
+{
+  // application tear-down
+  printf("A device with address %d is unmounted \r\n", dev_addr);
+}
+
+
 //--------------------------------------------------------------------+
 // Blinking Task
 //--------------------------------------------------------------------+
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 6a29f3f43..8ca3dfbcb 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -123,22 +123,29 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
 bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_xfer_cb_t complete_cb)
 {
   cdch_data_t const * p_cdc = get_itf(dev_addr);
-  tusb_control_request_t const request =
+
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
+      .wValue   = (rts ? 2 : 0) | (dtr ? 1 : 0),
+      .wIndex   = p_cdc->itf_num,
+      .wLength  = 0
     },
-    .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
-    .wValue   = (rts ? 2 : 0) | (dtr ? 1 : 0),
-    .wIndex   = p_cdc->itf_num,
-    .wLength  = 0
+
+    .buffer      = NULL,
+    .complete_cb = complete_cb,
+    .user_arg    = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &request, NULL, complete_cb) );
-  return true;
+  return tuh_control_xfer(dev_addr, &xfer);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 323debe69..4de3551c2 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -103,13 +103,13 @@ uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
   return hid_itf->protocol_mode;
 }
 
-static bool set_protocol_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
 {
-  uint8_t const itf_num     = (uint8_t) request->wIndex;
+  uint8_t const itf_num     = (uint8_t) xfer->request.wIndex;
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
-  if (XFER_RESULT_SUCCESS == result) hid_itf->protocol_mode = (uint8_t) request->wValue;
+  if (XFER_RESULT_SUCCESS == result) hid_itf->protocol_mode = (uint8_t) xfer->request.wValue;
 
   if (tuh_hid_set_protocol_complete_cb)
   {
@@ -126,37 +126,44 @@ bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
 
   TU_LOG2("HID Set Protocol = %d\r\n", protocol);
 
-  tusb_control_request_t const request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
+      .wValue   = protocol,
+      .wIndex   = hid_itf->itf_num,
+      .wLength  = 0
     },
-    .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
-    .wValue   = protocol,
-    .wIndex   = hid_itf->itf_num,
-    .wLength  = 0
+
+    .buffer      = NULL,
+    .complete_cb = set_protocol_complete,
+    .user_arg    = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &request, NULL, set_protocol_complete) );
+  TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
   return true;
 }
 
-static bool set_report_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool set_report_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
 {
   TU_LOG2("HID Set Report complete\r\n");
 
   if (tuh_hid_set_report_complete_cb)
   {
-    uint8_t const itf_num     = (uint8_t) request->wIndex;
+    uint8_t const itf_num     = (uint8_t) xfer->request.wIndex;
     uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
 
-    uint8_t const report_type = tu_u16_high(request->wValue);
-    uint8_t const report_id   = tu_u16_low(request->wValue);
+    uint8_t const report_type = tu_u16_high(xfer->request.wValue);
+    uint8_t const report_id   = tu_u16_low(xfer->request.wValue);
 
-    tuh_hid_set_report_complete_cb(dev_addr, instance, report_id, report_type, (result == XFER_RESULT_SUCCESS) ? request->wLength : 0);
+    tuh_hid_set_report_complete_cb(dev_addr, instance, report_id, report_type, (result == XFER_RESULT_SUCCESS) ? xfer->request.wLength : 0);
   }
 
   return true;
@@ -167,21 +174,28 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
   TU_LOG2("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len);
 
-  tusb_control_request_t const request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_REPORT,
+      .wValue   = tu_u16(report_type, report_id),
+      .wIndex   = hid_itf->itf_num,
+      .wLength  = len
     },
-    .bRequest = HID_REQ_CONTROL_SET_REPORT,
-    .wValue   = tu_u16(report_type, report_id),
-    .wIndex   = hid_itf->itf_num,
-    .wLength  = len
+
+    .buffer      = report,
+    .complete_cb = set_report_complete,
+    .user_arg    = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &request, report, set_report_complete) );
+  TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
   return true;
 }
 
@@ -256,9 +270,9 @@ void hidh_close(uint8_t dev_addr)
 // Enumeration
 //--------------------------------------------------------------------+
 
-static bool config_set_protocol             (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool config_get_report_desc          (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
-static bool config_get_report_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool config_set_protocol             (uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result);
+static bool config_get_report_desc          (uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result);
+static bool config_get_report_desc_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result);
 
 static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
 
@@ -337,65 +351,79 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
 
   // SET IDLE request, device can stall if not support this request
   TU_LOG2("HID Set Idle \r\n");
-  tusb_control_request_t const request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_IDLE,
+      .wValue   = idle_rate,
+      .wIndex   = itf_num,
+      .wLength  = 0
     },
-    .bRequest = HID_REQ_CONTROL_SET_IDLE,
-    .wValue   = idle_rate,
-    .wIndex   = itf_num,
-    .wLength  = 0
+
+    .buffer      = NULL,
+    .complete_cb = (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? config_set_protocol : config_get_report_desc,
+    .user_arg    = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &request, NULL, (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? config_set_protocol : config_get_report_desc) );
+  TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
 
   return true;
 }
 
 // Force device to work in BOOT protocol
-static bool config_set_protocol(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool config_set_protocol(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
 {
   // Stall is a valid response for SET_IDLE, therefore we could ignore its result
   (void) result;
 
-  uint8_t const itf_num     = (uint8_t) request->wIndex;
+  uint8_t const itf_num     = (uint8_t) xfer->request.wIndex;
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
   TU_LOG2("HID Set Protocol to Boot Mode\r\n");
   hid_itf->protocol_mode = HID_PROTOCOL_BOOT;
-  tusb_control_request_t const new_request =
+  tuh_control_xfer_t const new_xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
+      .wValue   = HID_PROTOCOL_BOOT,
+      .wIndex   = hid_itf->itf_num,
+      .wLength  = 0
     },
-    .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
-    .wValue   = HID_PROTOCOL_BOOT,
-    .wIndex   = hid_itf->itf_num,
-    .wLength  = 0
+
+    .buffer      = NULL,
+    .complete_cb = config_get_report_desc,
+    .user_arg    = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, NULL, config_get_report_desc) );
+  TU_ASSERT( tuh_control_xfer(dev_addr, &new_xfer) );
   return true;
 }
 
-static bool config_get_report_desc(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool config_get_report_desc(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
 {
   // We can be here after SET_IDLE or SET_PROTOCOL (boot device)
   // Trigger assert if result is not successful with set protocol
-  if ( request->bRequest != HID_REQ_CONTROL_SET_IDLE )
+  if ( xfer->request.bRequest != HID_REQ_CONTROL_SET_IDLE )
   {
     TU_ASSERT(result == XFER_RESULT_SUCCESS);
   }
 
-  uint8_t const itf_num     = (uint8_t) request->wIndex;
+  uint8_t const itf_num     = (uint8_t) xfer->request.wIndex;
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
@@ -409,21 +437,21 @@ static bool config_get_report_desc(uint8_t dev_addr, tusb_control_request_t cons
     config_driver_mount_complete(dev_addr, instance, NULL, 0);
   }else
   {
-    TU_ASSERT(tuh_descriptor_get_hid_report(dev_addr, itf_num, hid_itf->report_desc_type, usbh_get_enum_buf(), hid_itf->report_desc_len, config_get_report_desc_complete));
+    TU_ASSERT(tuh_descriptor_get_hid_report(dev_addr, itf_num, hid_itf->report_desc_type, usbh_get_enum_buf(), hid_itf->report_desc_len, config_get_report_desc_complete, 0));
   }
 
   return true;
 }
 
-static bool config_get_report_desc_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool config_get_report_desc_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
 {
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
 
-  uint8_t const itf_num      = (uint8_t) request->wIndex;
+  uint8_t const itf_num      = (uint8_t) xfer->request.wIndex;
   uint8_t const instance     = get_instance_id_by_itfnum(dev_addr, itf_num);
 
   uint8_t const* desc_report = usbh_get_enum_buf();
-  uint16_t const desc_len    = request->wLength;
+  uint16_t const desc_len    = xfer->request.wLength;
 
   config_driver_mount_complete(dev_addr, instance, desc_report, desc_len);
 
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index e4239e375..c009e5088 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -358,7 +358,7 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 // MSC Enumeration
 //--------------------------------------------------------------------+
 
-static bool config_get_maxlun_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result);
 static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
@@ -405,27 +405,34 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
 
   //------------- Get Max Lun -------------//
   TU_LOG2("MSC Get Max Lun\r\n");
-  tusb_control_request_t request =
+  tuh_control_xfer_t const xfer =
   {
-    .bmRequestType_bit =
+    .request =
     {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_IN
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_IN
+      },
+      .bRequest = MSC_REQ_GET_MAX_LUN,
+      .wValue   = 0,
+      .wIndex   = itf_num,
+      .wLength  = 1
     },
-    .bRequest = MSC_REQ_GET_MAX_LUN,
-    .wValue   = 0,
-    .wIndex   = itf_num,
-    .wLength  = 1
+
+    .buffer      = &p_msc->max_lun,
+    .complete_cb = config_get_maxlun_complete,
+    .user_arg    = 0
   };
-  TU_ASSERT(tuh_control_xfer(dev_addr, &request, &p_msc->max_lun, config_get_maxlun_complete));
+  TU_ASSERT(tuh_control_xfer(dev_addr, &xfer));
 
   return true;
 }
 
-static bool config_get_maxlun_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
 {
-  (void) request;
+  (void) xfer;
 
   msch_interface_t* p_msc = get_itf(dev_addr);
 

From a5a565f7eb85c4d1ad43d74b1baf1f61dcf0a5b5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 12 Mar 2022 14:20:57 +0700
Subject: [PATCH 0897/2085] rework usbh enumeration process using user arg from
 control transfer as state

---
 src/host/hub.c  |  30 ++--
 src/host/hub.h  |  31 +++-
 src/host/usbh.c | 456 ++++++++++++++++++++++--------------------------
 3 files changed, 251 insertions(+), 266 deletions(-)

diff --git a/src/host/hub.c b/src/host/hub.c
index a0cf7b7e5..c1909cb5c 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -77,7 +77,8 @@ static char const* const _hub_feature_str[] =
 //--------------------------------------------------------------------+
 // HUB
 //--------------------------------------------------------------------+
-bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_xfer_cb_t complete_cb)
+bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
+                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   tuh_control_xfer_t const xfer =
   {
@@ -97,7 +98,7 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
 
     .buffer      = NULL,
     .complete_cb = complete_cb,
-    .user_arg    = 0
+    .user_arg    = user_arg
   };
 
   TU_LOG2("HUB Clear Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port);
@@ -105,7 +106,8 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
   return true;
 }
 
-bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_xfer_cb_t complete_cb)
+bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
+                          tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   tuh_control_xfer_t const xfer =
   {
@@ -125,7 +127,7 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, t
 
     .buffer      = NULL,
     .complete_cb = complete_cb,
-    .user_arg    = 0
+    .user_arg    = user_arg
   };
 
   TU_LOG2("HUB Set Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port);
@@ -133,12 +135,8 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, t
   return true;
 }
 
-bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_xfer_cb_t complete_cb)
-{
-  return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb);
-}
-
-bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_xfer_cb_t complete_cb)
+bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
+                         tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   tuh_control_xfer_t const xfer =
   {
@@ -158,7 +156,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_con
 
     .buffer      = resp,
     .complete_cb = complete_cb,
-    .user_arg    = 0
+    .user_arg    = user_arg
   };
 
   TU_LOG2("HUB Get Port Status: addr = %u port = %u\r\n", hub_addr, hub_port);
@@ -271,7 +269,7 @@ static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const *
 
   // Set Port Power to be able to detect connection, starting with port 1
   uint8_t const hub_port = 1;
-  return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete);
+  return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
 }
 
 static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
@@ -290,7 +288,7 @@ static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t con
   {
     // power next port
     uint8_t const hub_port = (uint8_t) (xfer->request.wIndex + 1);
-    return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete);
+    return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
   }
 
   return true;
@@ -320,7 +318,7 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   {
     if ( tu_bit_test(p_hub->status_change, port) )
     {
-      hub_port_get_status(dev_addr, port, &p_hub->port_status, connection_get_status_complete);
+      hub_port_get_status(dev_addr, port, &p_hub->port_status, connection_get_status_complete, 0);
       break;
     }
   }
@@ -344,7 +342,7 @@ static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t
     //TU_VERIFY(port_status.status_current.port_power && port_status.status_current.port_enable, );
 
     // Acknowledge Port Connection Change
-    hub_port_clear_feature(dev_addr, port_num, HUB_FEATURE_PORT_CONNECTION_CHANGE, connection_clear_conn_change_complete);
+    hub_port_clear_feature(dev_addr, port_num, HUB_FEATURE_PORT_CONNECTION_CHANGE, connection_clear_conn_change_complete, 0);
   }else
   {
     // Other changes are: Enable, Suspend, Over Current, Reset, L1 state
@@ -368,7 +366,7 @@ static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control
   if ( p_hub->port_status.status.connection )
   {
     // Reset port if attach event
-    hub_port_reset(dev_addr, port_num, connection_port_reset_complete);
+    hub_port_reset(dev_addr, port_num, connection_port_reset_complete, 0);
   }else
   {
     // submit detach event
diff --git a/src/host/hub.h b/src/host/hub.h
index a5d8704d3..30cf3dd1c 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -171,13 +171,36 @@ typedef struct {
 
 TU_VERIFY_STATIC( sizeof(hub_port_status_response_t) == 4, "size is not correct");
 
-bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_xfer_cb_t complete_cb);
-bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_xfer_cb_t complete_cb);
+// Clear feature
+bool hub_port_clear_feature (uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
+                             tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
-bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_xfer_cb_t complete_cb);
-bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_xfer_cb_t complete_cb);
+// Set feature
+bool hub_port_set_feature   (uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
+                             tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+
+// Get port status
+bool hub_port_get_status    (uint8_t hub_addr, uint8_t hub_port, void* resp,
+                             tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+
+// Get status from Interrupt endpoint
 bool hub_edpt_status_xfer(uint8_t dev_addr);
 
+// Reset a port
+static inline bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port,
+                                  tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+{
+  return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb, user_arg);
+}
+
+// Clear Reset Change
+static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port,
+                                               tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+{
+  return hub_port_clear_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET_CHANGE, complete_cb, user_arg);
+}
+
+
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index a8692c8e5..6c38c525e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -974,114 +974,216 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
 //--------------------------------------------------------------------+
 // Enumeration Process
 // is a lengthy process with a series of control transfer to configure
-// newly attached device. Each step is handled by a function in this
-// section
-// TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
+// newly attached device.
+// NOTE: due to the shared _usbh_ctrl_buf, we must complete enumerating
 // one device before enumerating another one.
 //--------------------------------------------------------------------+
 
-static bool enum_request_addr0_device_desc(void);
-static bool enum_get_addr0_device_desc_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+enum {
+  ENUM_IDLE,
+  ENUM_RESET_1,         // 1st reset when attached
+  //ENUM_HUB_GET_STATUS_1,
+  ENUM_HUB_CLEAR_RESET_1,
+  ENUM_ADDR0_DEVICE_DESC,
+  ENUM_RESET_2,         // 2nd reset before set address
+  ENUM_HUB_GET_STATUS_2,
+  ENUM_HUB_CLEAR_RESET_2,
+  ENUM_SET_ADDR,
+
+  ENUM_GET_DEVICE_DESC,
+  ENUM_GET_9BYTE_CONFIG_DESC,
+  ENUM_GET_FULL_CONFIG_DESC,
+  ENUM_SET_CONFIG,
+  ENUM_CONFIG_DRIVER
+};
 
 static bool enum_request_set_addr(void);
-static bool enum_set_address_complete           (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool enum_get_device_desc_complete       (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool enum_get_9byte_config_desc_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool enum_get_config_desc_complete       (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool enum_set_config_complete            (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
 static bool parse_configuration_descriptor      (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
-
-static uint8_t get_new_address(bool is_hub);
 static void enum_full_complete(void);
 
-#if CFG_TUH_HUB
-
-// Enum sequence:
-// New device (reset on the way) -> Get Status 0 -> Clear Reset 0 -> Get 8byte Device Descriptor
-//   -> Port Reset 1 -> reset delay -> Get Status 1 -> Clear Reset 1 -> queue hub interrupt endpoint
-
-static bool enum_hub_get_status0_complete  (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool enum_hub_clear_reset0_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool enum_hub_set_reset1_complete   (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool enum_hub_get_status1_complete  (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool enum_hub_clear_reset1_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-
-static bool enum_hub_get_status0_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
+// process device enumeration
+static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
 {
-  (void) dev_addr; (void) xfer;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  hub_port_status_response_t port_status;
-  memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
-
-  if ( !port_status.status.connection )
+  if (XFER_RESULT_SUCCESS != result)
   {
-    // device unplugged while delaying, nothing else to do, queue hub status
+    // stop enumeration, maybe we could retry this
     enum_full_complete();
     return false;
   }
 
-  _dev0.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH :
-                (port_status.status.low_speed ) ? TUSB_SPEED_LOW  : TUSB_SPEED_FULL;
+  uint32_t const state = (uint32_t) xfer->user_arg;
 
-  // Acknowledge Port Reset Change
-  if (port_status.change.reset)
+  switch(state)
   {
-    hub_port_clear_feature(_dev0.hub_addr, _dev0.hub_port, HUB_FEATURE_PORT_RESET_CHANGE, enum_hub_clear_reset0_complete);
+#if CFG_TUH_HUB
+    //case ENUM_HUB_GET_STATUS_1: break;
+
+    case ENUM_HUB_CLEAR_RESET_1:
+    {
+      hub_port_status_response_t port_status;
+      memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
+
+      if ( !port_status.status.connection )
+      {
+        // device unplugged while delaying, nothing else to do
+        enum_full_complete();
+        return false;
+      }
+
+      _dev0.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH :
+                    (port_status.status.low_speed ) ? TUSB_SPEED_LOW  : TUSB_SPEED_FULL;
+
+      // Acknowledge Port Reset Change
+      if (port_status.change.reset)
+      {
+        hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_ADDR0_DEVICE_DESC);
+      }
+    }
+    break;
+
+    case ENUM_HUB_GET_STATUS_2:
+      osal_task_delay(RESET_DELAY);
+      TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_2) );
+    break;
+
+    case ENUM_HUB_CLEAR_RESET_2:
+    {
+      hub_port_status_response_t port_status;
+      memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
+
+      // Acknowledge Port Reset Change if Reset Successful
+      if (port_status.change.reset)
+      {
+        TU_ASSERT( hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_SET_ADDR) );
+      }
+    }
+    break;
+#endif
+
+    case ENUM_ADDR0_DEVICE_DESC:
+    {
+      // TODO probably doesn't need to open/close each enumeration
+      uint8_t const addr0 = 0;
+      TU_ASSERT( usbh_edpt_control_open(addr0, 8) );
+
+      // Get first 8 bytes of device descriptor for Control Endpoint size
+      TU_LOG2("Get 8 byte of Device Descriptor\r\n");
+      TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, process_enumeration, ENUM_SET_ADDR));
+    }
+    break;
+
+    case ENUM_RESET_2:
+      // Reset device again before Set Address
+      TU_LOG2("Port reset \r\n");
+      if (_dev0.hub_addr == 0)
+      {
+        // connected directly to roothub
+        hcd_port_reset( _dev0.rhport );
+        osal_task_delay(RESET_DELAY);
+
+        // TODO: fall through to SET ADDRESS, refactor later
+      }
+      #if CFG_TUH_HUB
+      else
+      {
+        // after RESET_DELAY the hub_port_reset() already complete
+        TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_HUB_GET_STATUS_2) );
+        break;
+      }
+      __attribute__((fallthrough));
+      #endif
+
+    case ENUM_SET_ADDR:
+      enum_request_set_addr();
+    break;
+
+    case ENUM_GET_DEVICE_DESC:
+    {
+      uint8_t const new_addr = (uint8_t const) xfer->request.wValue;
+
+      usbh_device_t* new_dev = get_device(new_addr);
+      new_dev->addressed = 1;
+
+      // TODO close device 0, may not be needed
+      hcd_device_close(_dev0.rhport, 0);
+
+      // open control pipe for new address
+      TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size) );
+
+      // Get full device descriptor
+      TU_LOG2("Get Device Descriptor\r\n");
+      TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC));
+    }
+    break;
+
+    case ENUM_GET_9BYTE_CONFIG_DESC:
+    {
+      tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+      usbh_device_t* dev = get_device(dev_addr);
+
+      dev->vid            = desc_device->idVendor;
+      dev->pid            = desc_device->idProduct;
+      dev->i_manufacturer = desc_device->iManufacturer;
+      dev->i_product      = desc_device->iProduct;
+      dev->i_serial       = desc_device->iSerialNumber;
+
+    //  if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
+
+      // Get 9-byte for total length
+      uint8_t const config_idx = CONFIG_NUM - 1;
+      TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n");
+      TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC) );
+    }
+    break;
+
+    case ENUM_GET_FULL_CONFIG_DESC:
+    {
+      uint8_t const * desc_config = _usbh_ctrl_buf;
+
+      // Use offsetof to avoid pointer to the odd/misaligned address
+      uint16_t const total_len = tu_le16toh( tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) );
+
+      // TODO not enough buffer to hold configuration descriptor
+      TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE);
+
+      // Get full configuration descriptor
+      uint8_t const config_idx = CONFIG_NUM - 1;
+      TU_LOG2("Get Configuration[0] Descriptor\r\n");
+      TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, total_len, process_enumeration, ENUM_SET_CONFIG) );
+    }
+    break;
+
+    case ENUM_SET_CONFIG:
+      // Parse configuration & set up drivers
+      // Driver open aren't allowed to make any usb transfer yet
+      TU_ASSERT( parse_configuration_descriptor(dev_addr, (tusb_desc_configuration_t*) _usbh_ctrl_buf) );
+
+      TU_ASSERT( tuh_configuration_set(dev_addr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER) );
+    break;
+
+    case ENUM_CONFIG_DRIVER:
+    {
+      TU_LOG2("Device configured\r\n");
+      usbh_device_t* dev = get_device(dev_addr);
+      dev->configured = 1;
+
+      // Start the Set Configuration process for interfaces (itf = DRVID_INVALID)
+      // Since driver can perform control transfer within its set_config, this is done asynchronously.
+      // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete()
+      // TODO use separated API instead of using DRVID_INVALID
+      usbh_driver_set_config_complete(dev_addr, DRVID_INVALID);
+    }
+    break;
+
+    default:
+      // stop enumeration if unknown state
+      enum_full_complete();
+    break;
   }
 
   return true;
 }
 
-static bool enum_hub_clear_reset0_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
-{
-  (void) dev_addr; (void) xfer;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-  enum_request_addr0_device_desc();
-  return true;
-}
-
-static bool enum_hub_set_reset1_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
-{
-  (void) dev_addr; (void) xfer;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  osal_task_delay(RESET_DELAY);
-
-  TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status1_complete) );
-
-  return true;
-}
-
-static bool enum_hub_get_status1_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
-{
-  (void) dev_addr; (void) xfer;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  hub_port_status_response_t port_status;
-  memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
-
-  // Acknowledge Port Reset Change if Reset Successful
-  if (port_status.change.reset)
-  {
-    TU_ASSERT( hub_port_clear_feature(_dev0.hub_addr, _dev0.hub_port, HUB_FEATURE_PORT_RESET_CHANGE, enum_hub_clear_reset1_complete) );
-  }
-
-  return true;
-}
-
-static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
-{
-  (void) dev_addr; (void) xfer;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  enum_request_set_addr();
-
-  return true;
-}
-
-#endif // hub
-
 static bool enum_new_device(hcd_event_t* event)
 {
   _dev0.rhport   = event->rhport;
@@ -1100,7 +1202,14 @@ static bool enum_new_device(hcd_event_t* event)
     _dev0.speed = hcd_port_speed_get(_dev0.rhport );
     TU_LOG2("%s Speed\r\n", tu_str_speed[_dev0.speed]);
 
-    enum_request_addr0_device_desc();
+    //enum_request_addr0_device_desc();
+    tuh_control_xfer_t const xfer =
+    {
+      .complete_cb = process_enumeration,
+      .user_arg    = ENUM_ADDR0_DEVICE_DESC
+    };
+    process_enumeration(0, &xfer, XFER_RESULT_SUCCESS);
+
   }
 #if CFG_TUH_HUB
   else
@@ -1108,61 +1217,27 @@ static bool enum_new_device(hcd_event_t* event)
     // connected/disconnected via external hub
     // wait until device is stable
     osal_task_delay(RESET_DELAY);
-    TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete) );
+
+    // ENUM_HUB_GET_STATUS
+    //TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete, 0) );
+    TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_1) );
   }
 #endif // hub
 
   return true;
 }
 
-static bool enum_request_addr0_device_desc(void)
+static uint8_t get_new_address(bool is_hub)
 {
-  // TODO probably doesn't need to open/close each enumeration
-  uint8_t const addr0 = 0;
-  TU_ASSERT( usbh_edpt_control_open(addr0, 8) );
+  uint8_t const start = (is_hub ? CFG_TUH_DEVICE_MAX : 0) + 1;
+  uint8_t const count = (is_hub ? CFG_TUH_HUB : CFG_TUH_DEVICE_MAX);
 
-  // Get first 8 bytes of device descriptor for Control Endpoint size
-  TU_LOG2("Get 8 byte of Device Descriptor\r\n");
-  TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, enum_get_addr0_device_desc_complete, 0));
-  return true;
-}
-
-// After Get Device Descriptor of Address 0
-static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
-{
-  (void) xfer;
-  TU_ASSERT(0 == dev_addr);
-
-  if (XFER_RESULT_SUCCESS != result)
+  for (uint8_t i=0; i < count; i++)
   {
-    // stop enumeration, maybe we could retry this
-    enum_full_complete();
-    return false;
+    uint8_t const addr = start + i;
+    if (!get_device(addr)->connected) return addr;
   }
-
-  tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
-  TU_ASSERT( tu_desc_type(desc_device) == TUSB_DESC_DEVICE );
-
-  // Reset device again before Set Address
-  TU_LOG2("Port reset \r\n");
-
-  if (_dev0.hub_addr == 0)
-  {
-    // connected directly to roothub
-    hcd_port_reset( _dev0.rhport );
-    osal_task_delay(RESET_DELAY);
-
-    enum_request_set_addr();
-  }
-#if CFG_TUH_HUB
-  else
-  {
-    // after RESET_DELAY the hub_port_reset() already complete
-    TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, enum_hub_set_reset1_complete) );
-  }
-#endif // hub
-
-  return true;
+  return ADDR_INVALID;
 }
 
 static bool enum_request_set_addr(void)
@@ -1201,8 +1276,8 @@ static bool enum_request_set_addr(void)
     },
 
     .buffer      = NULL,
-    .complete_cb = enum_set_address_complete,
-    .user_arg    = 0
+    .complete_cb = process_enumeration,
+    .user_arg    = ENUM_GET_DEVICE_DESC
   };
 
   uint8_t const addr0 = 0;
@@ -1211,104 +1286,6 @@ static bool enum_request_set_addr(void)
   return true;
 }
 
-// After SET_ADDRESS is complete
-static bool enum_set_address_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
-{
-  TU_ASSERT(0 == dev_addr);
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  uint8_t const new_addr = (uint8_t const) xfer->request.wValue;
-
-  usbh_device_t* new_dev = get_device(new_addr);
-  new_dev->addressed = 1;
-
-  // TODO close device 0, may not be needed
-  hcd_device_close(_dev0.rhport, 0);
-
-  // open control pipe for new address
-  TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size) );
-
-  // Get full device descriptor
-  TU_LOG2("Get Device Descriptor\r\n");
-
-  TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), enum_get_device_desc_complete, 0));
-  return true;
-}
-
-static bool enum_get_device_desc_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
-{
-  (void) xfer;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
-  usbh_device_t* dev = get_device(dev_addr);
-
-  dev->vid            = desc_device->idVendor;
-  dev->pid            = desc_device->idProduct;
-  dev->i_manufacturer = desc_device->iManufacturer;
-  dev->i_product      = desc_device->iProduct;
-  dev->i_serial       = desc_device->iSerialNumber;
-
-//  if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
-
-  // Get 9-byte for total length
-  uint8_t const config_idx = CONFIG_NUM - 1;
-  TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n");
-  TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, 9, enum_get_9byte_config_desc_complete, 0) );
-  return true;
-}
-
-static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
-{
-  (void) xfer;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  // TODO not enough buffer to hold configuration descriptor
-  uint8_t const * desc_config = _usbh_ctrl_buf;
-
-  // Use offsetof to avoid pointer to the odd/misaligned address
-  uint16_t const total_len = tu_le16toh( tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) );
-
-  TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE);
-
-  // Get full configuration descriptor
-  uint8_t const config_idx = CONFIG_NUM - 1;
-  TU_LOG2("Get Configuration[0] Descriptor\r\n");
-  TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, total_len, enum_get_config_desc_complete, 0) );
-  return true;
-}
-
-static bool enum_get_config_desc_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
-{
-  (void) xfer;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  // Parse configuration & set up drivers
-  // Driver open aren't allowed to make any usb transfer yet
-  TU_ASSERT( parse_configuration_descriptor(dev_addr, (tusb_desc_configuration_t*) _usbh_ctrl_buf) );
-
-  TU_ASSERT( tuh_configuration_set(dev_addr, CONFIG_NUM, enum_set_config_complete, 0) );
-  return true;
-}
-
-static bool enum_set_config_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
-{
-  (void) xfer;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  TU_LOG2("Device configured\r\n");
-  usbh_device_t* dev = get_device(dev_addr);
-  dev->configured = 1;
-
-  // Start the Set Configuration process for interfaces (itf = DRVID_INVALID)
-  // Since driver can perform control transfer within its set_config, this is done asynchronously.
-  // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete()
-  // TODO use separated API instead of using DRVID_INVALID
-  usbh_driver_set_config_complete(dev_addr, DRVID_INVALID);
-
-  return true;
-}
-
 static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
 {
   usbh_device_t* dev = get_device(dev_addr);
@@ -1439,17 +1416,4 @@ static void enum_full_complete(void)
 
 }
 
-static uint8_t get_new_address(bool is_hub)
-{
-  uint8_t const start = (is_hub ? CFG_TUH_DEVICE_MAX : 0) + 1;
-  uint8_t const count = (is_hub ? CFG_TUH_HUB : CFG_TUH_DEVICE_MAX);
-
-  for (uint8_t i=0; i < count; i++)
-  {
-    uint8_t const addr = start + i;
-    if (!get_device(addr)->connected) return addr;
-  }
-  return ADDR_INVALID;
-}
-
 #endif

From ac4483a7c53cd35b61b59cf69168e31ceac977a1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 12 Mar 2022 14:26:48 +0700
Subject: [PATCH 0898/2085] misplace fallthrough

---
 src/host/usbh.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 6c38c525e..16366b33f 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1090,8 +1090,8 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t const * xfe
         TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_HUB_GET_STATUS_2) );
         break;
       }
-      __attribute__((fallthrough));
       #endif
+      __attribute__((fallthrough));
 
     case ENUM_SET_ADDR:
       enum_request_set_addr();

From 56695569e7d9ebf39ffb2152aba4b4b9f0801d2d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 12 Mar 2022 14:28:24 +0700
Subject: [PATCH 0899/2085] minor changes

---
 src/host/usbh.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 16366b33f..7485bb065 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1011,8 +1011,7 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t const * xfe
     return false;
   }
 
-  uint32_t const state = (uint32_t) xfer->user_arg;
-
+  uintptr_t const state = xfer->user_arg;
   switch(state)
   {
 #if CFG_TUH_HUB

From 228e185a1535ed61d3b5eee6219ad1af1b637f4a Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Sat, 12 Mar 2022 16:58:37 +0700
Subject: [PATCH 0900/2085] Update bug_report.yml

---
 .github/ISSUE_TEMPLATE/bug_report.yml | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index fc41d8ff1..c0b520e35 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -60,11 +60,12 @@ body:
 
   - type: textarea
     attributes:
-      label: Debug Log
+      label: Debug Log as txt file
       placeholder: |
-        TinyUSB debug log where the issue occurred as attached txt file, best with comments to explain the actual events.
-
-        Note: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. 
+        Attach your debug log txt file here, where the issue occurred, best with comments to explain the actual events.
+        
+        Note1: Please DO NOT paste your lengthy log contents here since it hurts the readibility.
+        Note2: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. 
         More information can be found at [example's readme](https://github.com/hathach/tinyusb/blob/master/docs/getting_started.md)
     validations:
       required: false

From 2929afe2fa2fc8425dcd1390cb3119bb1bd3b42b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 13 Mar 2022 17:45:46 +0700
Subject: [PATCH 0901/2085] add synchronous (blocking) support for usbh control
 transfer

- add synchronous version of all get descriptor API
- update bare example to use sync API for string descriptor
- change order of index, language_id in tuh_descriptor_get_string() to
match similar API of libusb
- add index to tuh_descriptor_get_hid_report()
---
 examples/host/bare_api/src/main.c |  43 +++-----
 src/class/hid/hid_host.c          |   2 +-
 src/common/tusb_types.h           |   2 +
 src/host/usbh.c                   | 172 +++++++++++++++++++++++-------
 src/host/usbh.h                   |  98 ++++++++++++-----
 src/tusb_option.h                 |   2 +-
 6 files changed, 224 insertions(+), 95 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 6888d13a2..9e6209991 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -66,17 +66,9 @@ int main(void)
 #define LANGUAGE_ID 0x0409
 
 //uint8_t usb_buf[256] TU_ATTR_ALIGNED(4);
+TU_ATTR_ALIGNED(4)
 tusb_desc_device_t desc_device;
 
-static volatile xfer_result_t _get_string_result;
-
-static bool _transfer_done_cb(uint8_t daddr, tuh_control_xfer_t const *xfer, xfer_result_t result) {
-    (void)daddr;
-    (void)xfer;
-    _get_string_result = result;
-    return true;
-}
-
 static void _convert_utf16le_to_utf8(const uint16_t *utf16, size_t utf16_len, uint8_t *utf8, size_t utf8_len) {
     // TODO: Check for runover.
     (void)utf8_len;
@@ -116,14 +108,7 @@ static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
     return total_bytes;
 }
 
-static void _wait_and_convert(uint16_t *temp_buf, size_t buf_len) {
-    while (_get_string_result == 0xff) {
-        tuh_task();
-    }
-    if (_get_string_result != XFER_RESULT_SUCCESS) {
-        temp_buf[0] = 0;
-        return;
-    }
+static void utf16_to_utf8(uint16_t *temp_buf, size_t buf_len) {
     size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
     size_t utf8_len = _count_utf8_bytes(temp_buf + 1, utf16_len);
     _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
@@ -153,31 +138,29 @@ bool print_device_descriptor(uint8_t daddr, tuh_control_xfer_t const * xfer, xfe
   printf("  idProduct           0x%04x\r\n" , desc_device.idProduct);
   printf("  bcdDevice           %04x\r\n"   , desc_device.bcdDevice);
 
-  _get_string_result = 0xff;
+  uint32_t timeout_ms = 10;
   uint16_t temp_buf[128];
 
   printf("  iManufacturer       %u     "     , desc_device.iManufacturer);
-  temp_buf[0] = 0;
-  if (tuh_descriptor_get_manufacturer_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb, 0)) {
-    _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), timeout_ms) )
+  {
+    utf16_to_utf8(temp_buf, TU_ARRAY_SIZE(temp_buf));
     printf((const char*) temp_buf);
   }
   printf("\r\n");
 
   printf("  iProduct            %u     "     , desc_device.iProduct);
-  _get_string_result = 0xff;
-  temp_buf[0] = 0;
-  if (tuh_descriptor_get_product_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb, 0)) {
-    _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), timeout_ms))
+  {
+    utf16_to_utf8(temp_buf, TU_ARRAY_SIZE(temp_buf));
     printf((const char*) temp_buf);
   }
   printf("\r\n");
 
   printf("  iSerialNumber       %u     "     , desc_device.iSerialNumber);
-  _get_string_result = 0xff;
-  temp_buf[0] = 0;
-  if (tuh_descriptor_get_serial_string(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), _transfer_done_cb, 0)) {
-    _wait_and_convert(temp_buf, TU_ARRAY_SIZE(temp_buf));
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), timeout_ms))
+  {
+    utf16_to_utf8(temp_buf, TU_ARRAY_SIZE(temp_buf));
     printf((const char*) temp_buf);
   }
   printf("\r\n");
@@ -192,7 +175,7 @@ void tuh_mount_cb (uint8_t daddr)
 {
   printf("Device attached, address = %d\r\n", daddr);
 
-  // Get Device Descriptor
+  // Get Device Descriptor using asynchronous API
   tuh_descriptor_get_device(daddr, &desc_device, 18, print_device_descriptor, 0);
 }
 
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 4de3551c2..a825858ab 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -437,7 +437,7 @@ static bool config_get_report_desc(uint8_t dev_addr, tuh_control_xfer_t const *
     config_driver_mount_complete(dev_addr, instance, NULL, 0);
   }else
   {
-    TU_ASSERT(tuh_descriptor_get_hid_report(dev_addr, itf_num, hid_itf->report_desc_type, usbh_get_enum_buf(), hid_itf->report_desc_len, config_get_report_desc_complete, 0));
+    TU_ASSERT(tuh_descriptor_get_hid_report(dev_addr, itf_num, hid_itf->report_desc_type, 0, usbh_get_enum_buf(), hid_itf->report_desc_len, config_get_report_desc_complete, 0));
   }
 
   return true;
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index da164145b..e2fa17532 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -228,6 +228,8 @@ typedef enum
   XFER_RESULT_SUCCESS,
   XFER_RESULT_FAILED,
   XFER_RESULT_STALLED,
+  XFER_RESULT_TIMEOUT,
+  XFER_RESULT_INVALID
 }xfer_result_t;
 
 enum // TODO remove
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 7485bb065..c7dfaddf6 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -243,7 +243,7 @@ struct
 {
   tuh_control_xfer_t xfer;
   uint8_t daddr;  // device address that is transferring
-  uint8_t stage;
+  volatile uint8_t stage;
 }_ctrl_xfer;
 
 //------------- Helper Function -------------//
@@ -300,8 +300,8 @@ void osal_task_delay(uint32_t msec)
 // Descriptors
 //--------------------------------------------------------------------+
 
-bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
-                        tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
+                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   tuh_control_xfer_t const xfer =
   {
@@ -315,7 +315,7 @@ bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer
       },
       .bRequest = TUSB_REQ_GET_DESCRIPTOR,
       .wValue   = tu_htole16( TU_U16(type, index) ),
-      .wIndex   = 0,
+      .wIndex   = tu_htole16(language_id),
       .wLength  = tu_htole16(len)
     },
 
@@ -327,6 +327,12 @@ bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer
   return tuh_control_xfer(daddr, &xfer);
 }
 
+bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
+                        tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+{
+  return _get_descriptor(daddr, type, index, 0x0000, buffer, len, complete_cb, user_arg);
+}
+
 bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
                                tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
@@ -340,31 +346,12 @@ bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer
   return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb, user_arg);
 }
 
-bool tuh_descriptor_get_string(uint8_t daddr, uint16_t language_id, uint8_t index, void* buffer, uint16_t len,
+//------------- String Descriptor -------------//
+
+bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
                                tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
-  tuh_control_xfer_t const xfer =
-  {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_DEVICE,
-        .type      = TUSB_REQ_TYPE_STANDARD,
-        .direction = TUSB_DIR_IN
-      },
-      .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-      .wValue   = tu_htole16( TU_U16(TUSB_DESC_STRING, index) ),
-      .wIndex   = tu_htole16(language_id),
-      .wLength  = tu_htole16(len)
-    },
-
-    .buffer      = buffer,
-    .complete_cb = complete_cb,
-    .user_arg    = user_arg
-  };
-
-  return tuh_control_xfer(daddr, &xfer);
+  return _get_descriptor(daddr, TUSB_DESC_STRING, index, language_id, buffer, len, complete_cb, user_arg);
 }
 
 // Get manufacturer string descriptor
@@ -376,7 +363,7 @@ bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id,
   if (dev->i_manufacturer == 0) {
     return false;
   }
-  return tuh_descriptor_get_string(daddr, language_id, dev->i_manufacturer, buffer, len, complete_cb, user_arg);
+  return tuh_descriptor_get_string(daddr, dev->i_manufacturer, language_id, buffer, len, complete_cb, user_arg);
 }
 
 // Get product string descriptor
@@ -388,7 +375,7 @@ bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void
   if (dev->i_product == 0) {
     return false;
   }
-  return tuh_descriptor_get_string(daddr, language_id, dev->i_product, buffer, len, complete_cb, user_arg);
+  return tuh_descriptor_get_string(daddr, dev->i_product, language_id, buffer, len, complete_cb, user_arg);
 }
 
 // Get serial string descriptor
@@ -400,11 +387,11 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void*
   if (dev->i_serial == 0) {
     return false;
   }
-  return tuh_descriptor_get_string(daddr, language_id, dev->i_serial, buffer, len, complete_cb, user_arg);
+  return tuh_descriptor_get_string(daddr, dev->i_serial, language_id, buffer, len, complete_cb, user_arg);
 }
 
 // Get HID report descriptor
-bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, void* buffer, uint16_t len,
+bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
                                    tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   TU_LOG2("HID Get Report Descriptor\r\n");
@@ -419,8 +406,8 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
         .direction = TUSB_DIR_IN
       },
       .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-      .wValue   = tu_htole16(TU_U16(desc_type, 0)),
-      .wIndex   = itf_num,
+      .wValue   = tu_htole16(TU_U16(desc_type, index)),
+      .wIndex   = tu_htole16((uint16_t) itf_num),
       .wLength  = len
     },
 
@@ -461,6 +448,58 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
   return tuh_control_xfer(daddr, &xfer);
 }
 
+//--------------------------------------------------------------------+
+// Asynchronous
+//--------------------------------------------------------------------+
+
+#define _CONTROL_SYNC_API(_async_func, _timeout, ...) \
+  (void) _timeout; \
+  xfer_result_t result = XFER_RESULT_INVALID;\
+  /* TODO use timeout to wait */ \
+  TU_VERIFY(_async_func(__VA_ARGS__, NULL, (uintptr_t) &result), XFER_RESULT_TIMEOUT); \
+  return (uint8_t) result
+
+uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms)
+{
+  _CONTROL_SYNC_API(tuh_descriptor_get, timeout_ms, daddr, type, index, buffer, len);
+}
+
+uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len, uint8_t timeout_ms)
+{
+  len = tu_min16(len, sizeof(tusb_desc_device_t));
+  return tuh_descriptor_get_sync(daddr, TUSB_DESC_DEVICE, 0, buffer, len, timeout_ms);
+}
+
+uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms)
+{
+  return tuh_descriptor_get_sync(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, timeout_ms);
+}
+
+uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms)
+{
+  _CONTROL_SYNC_API(tuh_descriptor_get_hid_report, timeout_ms, daddr, itf_num, desc_type, index, buffer, len);
+}
+
+uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms)
+{
+  _CONTROL_SYNC_API(tuh_descriptor_get_string, timeout_ms, daddr, index, language_id, buffer, len);
+}
+
+uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms)
+{
+  _CONTROL_SYNC_API(tuh_descriptor_get_manufacturer_string, timeout_ms, daddr, language_id, buffer, len);
+}
+
+uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms)
+{
+  _CONTROL_SYNC_API(tuh_descriptor_get_product_string, timeout_ms, daddr, language_id, buffer, len);
+}
+
+uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms)
+{
+  _CONTROL_SYNC_API(tuh_descriptor_get_serial_string, timeout_ms, daddr, language_id, buffer, len);
+}
+
 //--------------------------------------------------------------------+
 // CLASS-USBD API (don't require to verify parameters)
 //--------------------------------------------------------------------+
@@ -833,11 +872,22 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
 // Control transfer
 //--------------------------------------------------------------------+
 
+static bool _control_blocking_complete_cb(uint8_t daddr, tuh_control_xfer_t const * xfer, xfer_result_t result)
+{
+  (void) daddr;
+
+  // update result
+  *((xfer_result_t*) xfer->user_arg) = result;
+
+  return true;
+}
+
 bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer)
 {
   // pre-check to help reducing mutex lock
   TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
 
+  // TODO probably better to use semaphore as resource management than mutex
   usbh_lock();
 
   bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
@@ -855,7 +905,52 @@ bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer)
 
   _ctrl_xfer.daddr = daddr;
   _ctrl_xfer.xfer = (*xfer);
-  return hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.xfer.request);
+
+  if (xfer->complete_cb)
+  {
+    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.xfer.request) );
+  }else
+  {
+    // user_arg must point to xfer_result_t to hold result
+    TU_VERIFY(xfer->user_arg);
+
+    // blocking if complete callback is not provided
+    // change callback to internal blocking, and result as user argument
+    volatile xfer_result_t* result = (volatile xfer_result_t*) xfer->user_arg;
+
+    _ctrl_xfer.xfer.complete_cb = _control_blocking_complete_cb;
+    *result = XFER_RESULT_INVALID;
+
+    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.xfer.request) );
+
+    while ((*result) == XFER_RESULT_INVALID)
+    {
+      // only need to call task if not preempted RTOS
+      #if CFG_TUSB_OS == OPT_OS_NONE || CFG_TUSB_OS == OPT_OS_PICO
+      tuh_task();
+      #endif
+
+      // TODO probably some timeout to prevent hanged
+    }
+  }
+
+  return true;
+}
+
+uint8_t tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t const* xfer, uint32_t timeout_ms)
+{
+  (void) timeout_ms;
+
+  xfer_result_t result = XFER_RESULT_INVALID;
+  tuh_control_xfer_t xfer_sync = (*xfer);
+
+  xfer_sync.complete_cb = NULL;
+  xfer_sync.user_arg = (uintptr_t) &result;
+
+  // TODO use timeout to wait
+  TU_VERIFY(tuh_control_xfer(daddr, &xfer_sync), XFER_RESULT_TIMEOUT);
+
+  return result;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void set_control_xfer_stage(uint8_t stage)
@@ -869,15 +964,16 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
 {
   TU_LOG2("\r\n");
 
+  // duplicate xfer since user can execute control transfer within callback
+  tuh_control_xfer_t const xfer_temp = _ctrl_xfer.xfer;
+
   usbh_lock();
   _ctrl_xfer.stage = CONTROL_STAGE_IDLE;
   usbh_unlock();
 
-  if (_ctrl_xfer.xfer.complete_cb)
+  if (xfer_temp.complete_cb)
   {
-    // duplicate xfer since user can execute control transfer within callback
-    tuh_control_xfer_t const xfer_temp = _ctrl_xfer.xfer;
-    _ctrl_xfer.xfer.complete_cb(dev_addr, &xfer_temp, result);
+    xfer_temp.complete_cb(dev_addr, &xfer_temp, result);
   }
 }
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index d836d9593..3bd40c50d 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -52,6 +52,18 @@ struct tuh_control_xfer_s
   uintptr_t user_arg;
 };
 
+//--------------------------------------------------------------------+
+// APPLICATION CALLBACK
+//--------------------------------------------------------------------+
+
+//TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device);
+
+// Invoked when device is mounted (configured)
+TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);
+
+/// Invoked when device is unmounted (bus reset/unplugged)
+TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
+
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
@@ -93,65 +105,101 @@ static inline bool tuh_ready(uint8_t daddr)
 }
 
 // Carry out a control transfer
-// true on success, false if there is on-going control transfer
-// Note: function is blocking if complete callback is NULL
+// true on success, false if there is on-going control transfer or incorrect parameters
+// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
 bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer);
 
-// Carry out a control transfer
-// true on success, false if there is on-going control transfer
-// Note: function is blocking if complete callback is NULL
-//bool tuh_control_xfer (uint8_t daddr, tusb_control_request_t const* request, void* buffer,
-//                       tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+// Sync (blocking) version of tuh_control_xfer()
+// return transfer result
+uint8_t tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t const* xfer, uint32_t timeout_ms);
 
-// Set Configuration
+// Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
+// true on success, false if there is on-going control transfer or incorrect parameters
+// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
-//------------- descriptors -------------//
+//--------------------------------------------------------------------+
+// Descriptors Asynchronous (non-blocking)
+//--------------------------------------------------------------------+
 
-// Get an descriptor
+// Get an descriptor (control transfer)
+// true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
                         tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
-// Get device descriptor
+// Get device descriptor (control transfer)
+// true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
                                tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
-// Get configuration descriptor
+// Get configuration descriptor (control transfer)
+// true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len,
                                       tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
-// Get HID report descriptor
-bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, void* buffer, uint16_t len,
+// Get HID report descriptor (control transfer)
+// true on success, false if there is on-going control transfer or incorrect parameters
+bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
                                    tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
-// Get string descriptor
-bool tuh_descriptor_get_string(uint8_t daddr, uint16_t language_id, uint8_t index, void* buffer, uint16_t len,
+// Get string descriptor (control transfer)
+// true on success, false if there is on-going control transfer or incorrect parameters
+// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
+bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
                                tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
-// Get manufacturer string descriptor
+// Get manufacturer string descriptor (control transfer)
+// true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
                                             tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
-// Get product string descriptor
+// Get product string descriptor (control transfer)
+// true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
                                        tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
-// Get serial string descriptor
+// Get serial string descriptor (control transfer)
+// true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
                                       tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 //--------------------------------------------------------------------+
-// APPLICATION CALLBACK
+// Descriptors Synchronous (blocking)
 //--------------------------------------------------------------------+
-//TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device);
 
-// Invoked when device is mounted (configured)
-TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);
+// Sync (blocking) version of tuh_descriptor_get()
+// return transfer result
+uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms);
 
-/// Invoked when device is unmounted (bus reset/unplugged)
-TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
+// Sync (blocking) version of tuh_descriptor_get_device()
+// return transfer result
+uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len, uint8_t timeout_ms);
+
+// Sync (blocking) version of tuh_descriptor_get_configuration()
+// return transfer result
+uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms);
+
+// Sync (blocking) version of tuh_descriptor_get_hid_report()
+// return transfer result
+uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms);
+
+// Sync (blocking) version of tuh_descriptor_get_string()
+// return transfer result
+uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
+
+// Sync (blocking) version of tuh_descriptor_get_manufacturer_string()
+// return transfer result
+uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
+
+// Sync (blocking) version of tuh_descriptor_get_product_string()
+// return transfer result
+uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
+
+// Sync (blocking) version of tuh_descriptor_get_serial_string()
+// return transfer result
+uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
 
 #ifdef __cplusplus
  }
diff --git a/src/tusb_option.h b/src/tusb_option.h
index e5351b1c4..0352faaed 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -285,7 +285,7 @@
   #define CFG_TUSB_OS_INC_PATH
 #endif
 
-// mutex is only needed for RTOS
+// mutex is only needed for RTOS TODO also required with multiple core MCUs
 #define TUSB_OPT_MUTEX    (CFG_TUSB_OS != OPT_OS_NONE)
 
 //--------------------------------------------------------------------

From f212899b54740479eff225d89432d88f0a14f17e Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Mon, 14 Mar 2022 20:40:33 +0100
Subject: [PATCH 0902/2085] Add SOF callback function for feedback value
 determination in uac - wip!

---
 src/class/audio/audio_device.c        | 83 +++++++++++++++++++++++++++
 src/class/audio/audio_device.h        | 23 +++++++-
 src/device/usbd.c                     | 22 ++++++-
 src/device/usbd_pvt.h                 |  5 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c | 32 +++++++++--
 5 files changed, 156 insertions(+), 9 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 06979b09e..0828f2e6f 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -306,6 +306,13 @@ typedef struct
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
   uint32_t fb_val;                                                              // Feedback value for asynchronous mode (in 16.16 format).
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+  uint8_t n_frames;                                                            // Number of (micro)frames used to estimate feedback value
+  uint8_t n_frames_current;                                                    // Current (micro)frame number
+  uint32_t feeback_param_factor;                                               // TODO: Set this value within some new tud_audio_set_feedback_params_fm_fs function as feeback_param_factor = f_s / (f_cpu * n_frames)!
+#endif
+
 #endif
 #endif
 
@@ -421,6 +428,10 @@ static inline uint8_t tu_desc_subtype(void const* desc)
 }
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+static bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
+#endif
+
 bool tud_audio_n_mounted(uint8_t func_id)
 {
   TU_VERIFY(func_id < CFG_TUD_AUDIO);
@@ -1658,6 +1669,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
           {
             audio->ep_fb = ep_addr;
 
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+            usbd_sof_enable(rhport, true);       // Enable SOF interrupt
+            audio->n_frames_current = 0;
+#endif
+
             // Invoke callback after ep_out is set
             if (audio->ep_out != 0)
             {
@@ -1682,6 +1698,23 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     p_desc = tu_desc_next(p_desc);
   }
 
+  // Disable SOF interrupt if no driver has any enabled feedback EP
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+
+  bool disable = true;
+
+  for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
+    {
+      if (_audiod_fct[i].ep_fb != 0)
+      {
+        disable = false;
+      }
+    }
+
+  if (disable) usbd_sof_enable(rhport, false);
+
+#endif
+
   tud_control_status(rhport, p_request);
 
   return true;
@@ -1970,6 +2003,52 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
   return false;
 }
 
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+bool tud_audio_set_feedback_params_fm_fs(uint8_t func_id, uint32_t f_m, uint32_t f_s)
+{
+  audiod_function_t* audio = &_audiod_fct[func_id];
+  uint8_t n_frame = 1;    // TODO: finalize that
+  audio->n_frames = n_frame;
+  audio->feeback_param_factor = f_s / f_m / n_frame;    // TODO: Check the 16.16 precision!
+  return true;
+}
+#endif
+
+void audiod_sof (uint8_t rhport, uint32_t frame_count)
+{
+  (void) rhport;
+  (void) frame_count;
+
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+
+  // Determine feedback value - The feedback method is described in 5.12.4.2 of the USB 2.0 spec
+  // Boiled down, the feedback value Ff = n_samples / (micro)frame.
+  // Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_cpu) frames need to be measured, where K = 10 for full speed and K = 13 for high speed, f_s is the sampling frequency e.g. 48 kHz and f_cpu is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
+  // The update interval in the (4.10.2.1) Feedback Endpoint Descriptor must be less or equal to 2^(K - P), where P = min( ceil(log2(f_cpu / f_s)), K)
+  // Ff = n_cycles / n_frames * f_s / f_cpu in 16.16 format, where n_cycles are the number of CPU cycles within n_frames
+
+  // Iterate over audio functions and set feedback value
+  for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
+    {
+      audiod_function_t* audio = &_audiod_fct[i];
+
+      if (audio->ep_fb != 0)
+      {
+        audio->n_frames_current++;
+        if (audio->n_frames_current == audio->n_frames)
+        {
+          uint32_t n_cylces = tud_audio_n_get_fm_n_cycles_cb(rhport, audio->ep_fb);
+          uint32_t feedback = n_cylces * audio->feeback_param_factor;
+
+          tud_audio_n_fb_set(i, feedback);
+          audio->n_frames_current = 0;
+        }
+      }
+    }
+
+#endif
+}
+
 bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_request_t const * p_request, void* data, uint16_t len)
 {
   // Handles only sending of data not receiving
@@ -2247,7 +2326,11 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+static bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
+#else
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
+#endif
 {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index f406cf281..c9d711a36 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -191,6 +191,11 @@
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION     0                             // 0 or 1
 #endif
 
+// Determine feedback value within SOF ISR within audio driver - if disabled the user has to call tud_audio_n_fb_set() with a suitable feedback value on its own. If done within audio driver SOF ISR, tud_audio_n_fb_set() is disabled for user
+#ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR    1                             // 0 or 1
+#endif
+
 // Audio interrupt control EP size - disabled if 0
 #ifndef CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
 #define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN                     0                             // Audio interrupt control - if required - 6 Bytes according to UAC 2 specification (p. 74)
@@ -468,8 +473,23 @@ TU_ATTR_WEAK bool tud_audio_fb_done_cb(uint8_t rhport);
 //
 // Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the 
 // driver can work with either format. So a good compromise is to keep format correction disabled and stick to 16.16 format.
+
+// Feedback value can be determined from within the SOF ISR of the audio driver. This should reduce jitter. If the feature is used, the user can not set the feedback value.
+# if !CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
 static inline bool tud_audio_fb_set(uint32_t feedback);
+# else
+
+// This callback function is called once the feedback value needs to be updated within the SOF ISR in the audio class. To determine the feedback value, some
+// parameters need to be given. The user must implement this callback function and provide the current cycle count of the master clock.
+// The feedback endpoint number can be used to identify the correct audio function in case multiple audio functions were defined.
+TU_ATTR_WEAK uint32_t tud_audio_n_get_fm_n_cycles_cb(uint8_t rhport, uint8_t ep_fb);
+
+// f_m : Main clock frequency in Hz i.e. master clock to which sample clock is locked
+// f_s : Current sample rate in Hz
+bool tud_audio_set_feedback_params_fm_fs(uint8_t func_id, uint32_t f_m, uint32_t f_s);
+#endif
+
 #endif
 
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
@@ -611,7 +631,7 @@ static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t l
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && !CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
 static inline bool tud_audio_fb_set(uint32_t feedback)
 {
   return tud_audio_n_fb_set(0, feedback);
@@ -626,6 +646,7 @@ void     audiod_reset          (uint8_t rhport);
 uint16_t audiod_open           (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     audiod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 bool     audiod_xfer_cb        (uint8_t rhport, uint8_t edpt_addr, xfer_result_t result, uint32_t xferred_bytes);
+void     audiod_sof            (uint8_t rhport, uint32_t frame_count);
 
 #ifdef __cplusplus
 }
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 8662d5b84..170342072 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -139,7 +139,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = audiod_open,
     .control_xfer_cb  = audiod_control_xfer_cb,
     .xfer_cb          = audiod_xfer_cb,
-    .sof              = NULL
+    .sof              = audiod_sof
   },
   #endif
 
@@ -612,7 +612,7 @@ void tud_task (void)
         for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ )
         {
           usbd_class_driver_t const * driver = get_driver(i);
-          if ( driver->sof ) driver->sof(event.rhport);
+          if ( driver->sof ) driver->sof(event.rhport, event.sof.frame_count);
         }
       break;
 
@@ -1131,7 +1131,18 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
     break;
 
     case DCD_EVENT_SOF:
-      // SOF Handler
+      // SOF driver handler in ISR context
+      for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
+      {
+        usbd_class_driver_t const * driver = get_driver(i);
+        if (driver->sof)
+        {
+          driver->sof(event->rhport, event->sof.frame_count);
+          // TU_LOG2("%s sof\r\n", driver->name); // too demanding
+        }
+      }
+
+      // SOF user handler in ISR context
       if (_sof_isr) _sof_isr(event->sof.frame_count);
 
       // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup
@@ -1441,4 +1452,9 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   return;
 }
 
+void usbd_sof_enable(uint8_t rhport, bool en)
+{
+  dcd_sof_enable(rhport, en);
+}
+
 #endif
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index dae95cebb..f9fb543df 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -48,7 +48,7 @@ typedef struct
   uint16_t (* open             ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len);
   bool     (* control_xfer_cb  ) (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
   bool     (* xfer_cb          ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-  void     (* sof              ) (uint8_t rhport); /* optional */
+  void     (* sof              ) (uint8_t rhport, uint32_t frame_count); /* optional */
 } usbd_class_driver_t;
 
 // Invoked when initializing device stack to get additional class drivers.
@@ -102,6 +102,9 @@ bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr)
   return !usbd_edpt_busy(rhport, ep_addr) && !usbd_edpt_stalled(rhport, ep_addr);
 }
 
+// Enable SOF interrupt
+void usbd_sof_enable(uint8_t rhport, bool en);
+
 /*------------------------------------------------------------------*/
 /* Helper
  *------------------------------------------------------------------*/
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 37712d2d9..d92b17703 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -93,6 +93,9 @@ static uint16_t ep0_pending[2];                   // Index determines direction
 static uint16_t _allocated_fifo_words_tx;         // TX FIFO size in words (IN EPs)
 static bool     _out_ep_closed;                   // Flag to check if RX FIFO size needs an update (reduce its size)
 
+// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
+static bool _sof_en;
+
 // Calculate the RX FIFO size according to recommendations from reference manual
 static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
 {
@@ -126,6 +129,8 @@ static void bus_reset(uint8_t rhport)
   tu_memclr(xfer_status, sizeof(xfer_status));
   _out_ep_closed = false;
 
+  _sof_en = false;
+
   // clear device address
   dwc2->dcfg &= ~DCFG_DAD_Msk;
 
@@ -588,12 +593,23 @@ void dcd_disconnect(uint8_t rhport)
   dwc2->dctl |= DCTL_SDIS;
 }
 
+// Be advised: audio, video and possibly other iso-ep classes use dcd_sof_enable() to enable/disable its corresponding ISR on purpose!
 void dcd_sof_enable(uint8_t rhport, bool en)
 {
   (void) rhport;
-  (void) en;
+  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
 
-  // TODO implement later
+  _sof_en = en;
+
+  if (en)
+  {
+    dwc2->gintsts = GINTSTS_SOF;
+    dwc2->gintmsk |= GINTMSK_SOFM;
+  }
+  else
+  {
+    dwc2->gintmsk &= ~GINTMSK_SOFM;
+  }
 }
 
 /*------------------------------------------------------------------*/
@@ -1258,8 +1274,16 @@ void dcd_int_handler(uint8_t rhport)
   {
     dwc2->gotgint = GINTSTS_SOF;
 
-    // Disable SOF interrupt since currently only used for remote wakeup detection
-    dwc2->gintmsk &= ~GINTMSK_SOFM;
+    if (_sof_en)
+    {
+      uint32_t frame = (dwc2->dsts & (USB_OTG_DSTS_FNSOF)) >> 8;
+      dcd_event_sof(rhport, frame, true);
+    }
+    else
+    {
+      // Disable SOF interrupt if SOF was not explicitly enabled. SOF was used for remote wakeup detection
+      dwc2->gintmsk &= ~GINTMSK_SOFM;
+    }
 
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
   }

From c9b444e771e138ee50ed8cbff67d895722b46008 Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Tue, 15 Mar 2022 20:30:31 +0100
Subject: [PATCH 0903/2085] Implement 16.16 fixed point feedback value
 calculation

---
 src/class/audio/audio_device.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 0828f2e6f..5ca95658e 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -310,7 +310,8 @@ typedef struct
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
   uint8_t n_frames;                                                            // Number of (micro)frames used to estimate feedback value
   uint8_t n_frames_current;                                                    // Current (micro)frame number
-  uint32_t feeback_param_factor;                                               // TODO: Set this value within some new tud_audio_set_feedback_params_fm_fs function as feeback_param_factor = f_s / (f_cpu * n_frames)!
+  uint32_t feeback_param_factor_N;                                             // Numerator of feedback parameter coefficient
+  uint32_t feeback_param_factor_D;                                             // Denominator of feedback parameter coefficient
 #endif
 
 #endif
@@ -2004,12 +2005,16 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 }
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+// f_s max is 2^19-1 = 524287 Hz
+// n_frames_min is ceil(2^10 * f_s / f_m) for full speed and ceil(2^13 * f_s / f_m) for high speed
+// f_m max is 2^29/(1 ms * n_frames) for full speed and 2^29/(125 us * n_frames) for high speed
 bool tud_audio_set_feedback_params_fm_fs(uint8_t func_id, uint32_t f_m, uint32_t f_s)
 {
   audiod_function_t* audio = &_audiod_fct[func_id];
   uint8_t n_frame = 1;    // TODO: finalize that
   audio->n_frames = n_frame;
-  audio->feeback_param_factor = f_s / f_m / n_frame;    // TODO: Check the 16.16 precision!
+  audio->feeback_param_factor_N = f_s << 13;
+  audio->feeback_param_factor_D = f_m * n_frame;
   return true;
 }
 #endif
@@ -2023,7 +2028,7 @@ void audiod_sof (uint8_t rhport, uint32_t frame_count)
 
   // Determine feedback value - The feedback method is described in 5.12.4.2 of the USB 2.0 spec
   // Boiled down, the feedback value Ff = n_samples / (micro)frame.
-  // Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_cpu) frames need to be measured, where K = 10 for full speed and K = 13 for high speed, f_s is the sampling frequency e.g. 48 kHz and f_cpu is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
+  // Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_m) frames need to be measured, where K = 10 for full speed and K = 13 for high speed, f_s is the sampling frequency e.g. 48 kHz and f_cpu is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
   // The update interval in the (4.10.2.1) Feedback Endpoint Descriptor must be less or equal to 2^(K - P), where P = min( ceil(log2(f_cpu / f_s)), K)
   // Ff = n_cycles / n_frames * f_s / f_cpu in 16.16 format, where n_cycles are the number of CPU cycles within n_frames
 
@@ -2038,7 +2043,7 @@ void audiod_sof (uint8_t rhport, uint32_t frame_count)
         if (audio->n_frames_current == audio->n_frames)
         {
           uint32_t n_cylces = tud_audio_n_get_fm_n_cycles_cb(rhport, audio->ep_fb);
-          uint32_t feedback = n_cylces * audio->feeback_param_factor;
+          uint32_t feedback = (n_cylces << 3) * audio->feeback_param_factor_N / audio->feeback_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
 
           tud_audio_n_fb_set(i, feedback);
           audio->n_frames_current = 0;

From 90502739c34b8cbcf37229031eb4f575c33311fa Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Tue, 15 Mar 2022 20:45:06 +0100
Subject: [PATCH 0904/2085] Fix cycle count calculation

---
 src/class/audio/audio_device.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 5ca95658e..1dbeb7643 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -310,6 +310,7 @@ typedef struct
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
   uint8_t n_frames;                                                            // Number of (micro)frames used to estimate feedback value
   uint8_t n_frames_current;                                                    // Current (micro)frame number
+  uint32_t n_cycles_old;                                                       // Old cycle count
   uint32_t feeback_param_factor_N;                                             // Numerator of feedback parameter coefficient
   uint32_t feeback_param_factor_D;                                             // Denominator of feedback parameter coefficient
 #endif
@@ -1673,6 +1674,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
             usbd_sof_enable(rhport, true);       // Enable SOF interrupt
             audio->n_frames_current = 0;
+            audio->n_cycles_old = 0;
 #endif
 
             // Invoke callback after ep_out is set
@@ -2043,10 +2045,11 @@ void audiod_sof (uint8_t rhport, uint32_t frame_count)
         if (audio->n_frames_current == audio->n_frames)
         {
           uint32_t n_cylces = tud_audio_n_get_fm_n_cycles_cb(rhport, audio->ep_fb);
-          uint32_t feedback = (n_cylces << 3) * audio->feeback_param_factor_N / audio->feeback_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
+          uint32_t feedback = ((n_cylces - audio->n_cycles_old) << 3) * audio->feeback_param_factor_N / audio->feeback_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
 
           tud_audio_n_fb_set(i, feedback);
           audio->n_frames_current = 0;
+          audio->n_cycles_old = n_cylces;
         }
       }
     }

From fd2ea2605e67673d4264b56649612b34fa93807d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Mar 2022 10:55:18 +0700
Subject: [PATCH 0905/2085] fix  -Wnull-dereference warnings

---
 src/host/usbh.c | 86 +++++++++++++++++++++++++++----------------------
 src/host/usbh.h |  4 +++
 2 files changed, 51 insertions(+), 39 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index c7dfaddf6..418642891 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -251,7 +251,7 @@ struct
 TU_ATTR_ALWAYS_INLINE
 static inline usbh_device_t* get_device(uint8_t dev_addr)
 {
-  TU_ASSERT(dev_addr, NULL);
+  TU_VERIFY(dev_addr > 0 && dev_addr <= TOTAL_DEVICES, NULL);
   return &_usbh_devices[dev_addr-1];
 }
 
@@ -265,15 +265,15 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
 //--------------------------------------------------------------------+
 bool tuh_mounted(uint8_t dev_addr)
 {
-  return get_device(dev_addr)->configured;
+  usbh_device_t* dev = get_device(dev_addr);
+  TU_VERIFY(dev);
+  return dev->configured;
 }
 
 bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
 {
-  *vid = *pid = 0;
-
-  TU_VERIFY(tuh_mounted(dev_addr));
   usbh_device_t const* dev = get_device(dev_addr);
+  TU_VERIFY(dev && dev->configured);
 
   *vid = dev->vid;
   *pid = dev->pid;
@@ -283,7 +283,8 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
 
 tusb_speed_t tuh_speed_get (uint8_t dev_addr)
 {
-  return (tusb_speed_t) (dev_addr ? get_device(dev_addr)->speed : _dev0.speed);
+  usbh_device_t* dev = get_device(dev_addr);
+  return (tusb_speed_t) (dev ? get_device(dev_addr)->speed : _dev0.speed);
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -358,11 +359,8 @@ bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_i
 bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
                                             tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
-  TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
-  if (dev->i_manufacturer == 0) {
-    return false;
-  }
+  TU_VERIFY(dev && dev->i_manufacturer);
   return tuh_descriptor_get_string(daddr, dev->i_manufacturer, language_id, buffer, len, complete_cb, user_arg);
 }
 
@@ -370,11 +368,8 @@ bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id,
 bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
                                        tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
-  TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
-  if (dev->i_product == 0) {
-    return false;
-  }
+  TU_VERIFY(dev && dev->i_product);
   return tuh_descriptor_get_string(daddr, dev->i_product, language_id, buffer, len, complete_cb, user_arg);
 }
 
@@ -382,11 +377,8 @@ bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void
 bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
                                       tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
-  TU_VERIFY(tuh_mounted(daddr));
   usbh_device_t const* dev = get_device(daddr);
-  if (dev->i_serial == 0) {
-    return false;
-  }
+  TU_VERIFY(dev && dev->i_serial);
   return tuh_descriptor_get_string(daddr, dev->i_serial, language_id, buffer, len, complete_cb, user_arg);
 }
 
@@ -629,6 +621,8 @@ void tuh_task(void)
         else
         {
           usbh_device_t* dev = get_device(event.dev_addr);
+          TU_ASSERT(dev, );
+
           dev->ep_status[epnum][ep_dir].busy    = 0;
           dev->ep_status[epnum][ep_dir].claimed = 0;
 
@@ -662,7 +656,8 @@ void tuh_task(void)
 
 uint8_t usbh_get_rhport(uint8_t dev_addr)
 {
-  return (dev_addr == 0) ? _dev0.rhport : get_device(dev_addr)->rhport;
+  usbh_device_t* dev = get_device(dev_addr);
+  return dev ? dev->rhport : _dev0.rhport;
 }
 
 uint8_t* usbh_get_enum_buf(void)
@@ -688,10 +683,10 @@ void usbh_int_set(bool enabled)
 
 void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info)
 {
-  if (dev_addr)
-  {
-    usbh_device_t const* dev = get_device(dev_addr);
+  usbh_device_t const* dev = get_device(dev_addr);
 
+  if (dev)
+  {
     devtree_info->rhport   = dev->rhport;
     devtree_info->hub_addr = dev->hub_addr;
     devtree_info->hub_port = dev->hub_port;
@@ -768,10 +763,11 @@ void hcd_event_device_remove(uint8_t hostid, bool in_isr)
 // TODO has some duplication code with device, refactor later
 bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
 {
-  // addr0 is always available
-  if (dev_addr == 0) return true;
-
   usbh_device_t* dev        = get_device(dev_addr);
+
+  // addr0 only use tuh_control_xfer
+  TU_ASSERT(dev);
+
   uint8_t const epnum       = tu_edpt_number(ep_addr);
   uint8_t const dir         = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
@@ -804,11 +800,12 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
 // TODO has some duplication code with device, refactor later
 bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
+  usbh_device_t* dev = get_device(dev_addr);
+  TU_VERIFY(dev);
+
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  usbh_device_t* dev = get_device(dev_addr);
-
   TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
@@ -827,7 +824,7 @@ bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_
     // HCD error, mark endpoint as ready to allow next transfer
     dev->ep_status[epnum][dir].busy = false;
     dev->ep_status[epnum][dir].claimed = 0;
-    TU_LOG2("failed\r\n");
+    TU_LOG1("failed\r\n");
     TU_BREAKPOINT();
     return false;
   }
@@ -852,9 +849,7 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
 
 bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
 {
-  usbh_device_t* dev = get_device(dev_addr);
-  TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) dev->speed));
-
+  TU_ASSERT( tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr)) );
   return hcd_edpt_open(rhport, dev_addr, desc_ep);
 }
 
@@ -864,6 +859,7 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   usbh_device_t* dev = get_device(dev_addr);
+  TU_VERIFY(dev);
 
   return dev->ep_status[epnum][dir].busy;
 }
@@ -1094,7 +1090,7 @@ enum {
 };
 
 static bool enum_request_set_addr(void);
-static bool parse_configuration_descriptor      (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
+static bool parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
 static void enum_full_complete(void);
 
 // process device enumeration
@@ -1194,9 +1190,10 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t const * xfe
 
     case ENUM_GET_DEVICE_DESC:
     {
-      uint8_t const new_addr = (uint8_t const) xfer->request.wValue;
+      uint8_t const new_addr = (uint8_t) tu_le16toh(xfer->request.wValue);
 
       usbh_device_t* new_dev = get_device(new_addr);
+      TU_ASSERT(new_dev);
       new_dev->addressed = 1;
 
       // TODO close device 0, may not be needed
@@ -1215,6 +1212,7 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t const * xfe
     {
       tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
       usbh_device_t* dev = get_device(dev_addr);
+      TU_ASSERT(dev);
 
       dev->vid            = desc_device->idVendor;
       dev->pid            = desc_device->idProduct;
@@ -1260,6 +1258,8 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t const * xfe
     {
       TU_LOG2("Device configured\r\n");
       usbh_device_t* dev = get_device(dev_addr);
+      TU_ASSERT(dev);
+
       dev->configured = 1;
 
       // Start the Set Configuration process for interfaces (itf = DRVID_INVALID)
@@ -1324,13 +1324,21 @@ static bool enum_new_device(hcd_event_t* event)
 
 static uint8_t get_new_address(bool is_hub)
 {
-  uint8_t const start = (is_hub ? CFG_TUH_DEVICE_MAX : 0) + 1;
-  uint8_t const count = (is_hub ? CFG_TUH_HUB : CFG_TUH_DEVICE_MAX);
-
-  for (uint8_t i=0; i < count; i++)
+  uint8_t start;
+  uint8_t end;
+  if ( is_hub )
   {
-    uint8_t const addr = start + i;
-    if (!get_device(addr)->connected) return addr;
+    start = CFG_TUH_DEVICE_MAX;
+    end   = start + CFG_TUH_HUB;
+  }else
+  {
+    start = 0;
+    end   = start + CFG_TUH_DEVICE_MAX;
+  }
+
+  for ( uint8_t idx = start; idx < end; idx++)
+  {
+    if (!_usbh_devices[idx].connected) return (idx+1);
   }
   return ADDR_INVALID;
 }
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 3bd40c50d..fc0590190 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -201,6 +201,10 @@ uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_
 // return transfer result
 uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 #ifdef __cplusplus
  }
 #endif

From 92ac041869b79aba6948e6440bbfc51ba77130ac Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Wed, 16 Mar 2022 07:13:38 +0100
Subject: [PATCH 0906/2085] Add todos and comments

---
 src/class/audio/audio_device.c |  2 ++
 src/device/usbd.c              | 12 +++++++-----
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 1dbeb7643..37bf76135 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2047,6 +2047,8 @@ void audiod_sof (uint8_t rhport, uint32_t frame_count)
           uint32_t n_cylces = tud_audio_n_get_fm_n_cycles_cb(rhport, audio->ep_fb);
           uint32_t feedback = ((n_cylces - audio->n_cycles_old) << 3) * audio->feeback_param_factor_N / audio->feeback_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
 
+          // TODO: Implement fast computation in case n_frames * f_s / f_m is a power of two
+
           tud_audio_n_fb_set(i, feedback);
           audio->n_frames_current = 0;
           audio->n_cycles_old = n_cylces;
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 6170c2bda..96ac19c8d 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -587,11 +587,12 @@ void tud_task (void)
 
       case DCD_EVENT_SOF:
         TU_LOG2("\r\n");
-        for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ )
-        {
-          usbd_class_driver_t const * driver = get_driver(i);
-          if ( driver->sof ) driver->sof(event.rhport, event.sof.frame_count);
-        }
+        // TODO: Should this really be done here in the queue? How to distinguish the calls here from those SOF events which should be handled directly in the ISR routine? If we do it like this, the SOF routines get called two time right now, once in the ISR context and once again here
+//        for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ )
+//        {
+//          usbd_class_driver_t const * driver = get_driver(i);
+//          if ( driver->sof ) driver->sof(event.rhport, event.sof.frame_count);
+//        }
       break;
 
       case USBD_EVENT_FUNC_CALL:
@@ -1410,6 +1411,7 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_sof_enable(uint8_t rhport, bool en)
 {
+  // TODO: Check needed if all drivers including the user sof_cb does not need an active SOF ISR any more. Only if all drivers switched off SOF calls the SOF interrupt may be disabled
   dcd_sof_enable(rhport, en);
 }
 

From 9fde8f2d9e311afc6ea3707f1ac3b245e0816a4c Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Wed, 16 Mar 2022 07:53:47 +0100
Subject: [PATCH 0907/2085] Fix DSTS_FNSOF in dwc2.c

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index d92b17703..ccc16d643 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -1276,7 +1276,7 @@ void dcd_int_handler(uint8_t rhport)
 
     if (_sof_en)
     {
-      uint32_t frame = (dwc2->dsts & (USB_OTG_DSTS_FNSOF)) >> 8;
+      uint32_t frame = (dwc2->dsts & (DSTS_FNSOF)) >> 8;
       dcd_event_sof(rhport, frame, true);
     }
     else

From ceac9d64c07b95d2c34263386e212e5480cda97c Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Wed, 16 Mar 2022 08:05:31 +0100
Subject: [PATCH 0908/2085] Disable
 CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR

By default disable
CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR such that
current examples still work.
---
 src/class/audio/audio_device.c | 2 +-
 src/class/audio/audio_device.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 37bf76135..f0cab4d93 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -430,7 +430,7 @@ static inline uint8_t tu_desc_subtype(void const* desc)
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
 static bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
 #endif
 
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index c9d711a36..eba8a6488 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -193,7 +193,7 @@
 
 // Determine feedback value within SOF ISR within audio driver - if disabled the user has to call tud_audio_n_fb_set() with a suitable feedback value on its own. If done within audio driver SOF ISR, tud_audio_n_fb_set() is disabled for user
 #ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR    1                             // 0 or 1
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR    0                             // 0 or 1
 #endif
 
 // Audio interrupt control EP size - disabled if 0

From 98d4ed05845e3a2efb32b0817d635457698b8cc9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Mar 2022 15:12:59 +0700
Subject: [PATCH 0909/2085] update hid host to use new control xfer for set
 config

---
 src/class/hid/hid_host.c | 211 +++++++++++++++++++--------------------
 src/class/msc/msc_host.c |   2 +-
 src/host/usbh.c          |  10 +-
 3 files changed, 108 insertions(+), 115 deletions(-)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index a825858ab..6bcd2f5d3 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -119,11 +119,9 @@ static bool set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t const * x
   return true;
 }
 
-bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
-{
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-  TU_VERIFY(hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE);
 
+static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protocol, tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+{
   TU_LOG2("HID Set Protocol = %d\r\n", protocol);
 
   tuh_control_xfer_t const xfer =
@@ -138,19 +136,27 @@ bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
       },
       .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
       .wValue   = protocol,
-      .wIndex   = hid_itf->itf_num,
+      .wIndex   = itf_num,
       .wLength  = 0
     },
 
     .buffer      = NULL,
-    .complete_cb = set_protocol_complete,
-    .user_arg    = 0
+    .complete_cb = complete_cb,
+    .user_arg    = user_arg
   };
 
   TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
   return true;
 }
 
+bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
+{
+  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  TU_VERIFY(hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE);
+
+  return _hidh_set_protocol(dev_addr, hid_itf->itf_num, protocol, set_protocol_complete, 0);
+}
+
 static bool set_report_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
 {
   TU_LOG2("HID Set Report complete\r\n");
@@ -199,6 +205,36 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
   return true;
 }
 
+static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate, tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+{
+  // SET IDLE request, device can stall if not support this request
+  TU_LOG2("HID Set Idle \r\n");
+  tuh_control_xfer_t const xfer =
+  {
+    .request =
+    {
+      .bmRequestType_bit =
+      {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = HID_REQ_CONTROL_SET_IDLE,
+      .wValue   = idle_rate,
+      .wIndex   = itf_num,
+      .wLength  = 0
+    },
+
+    .buffer      = NULL,
+    .complete_cb = complete_cb,
+    .user_arg    = user_arg
+  };
+
+  TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
+
+  return true;
+}
+
 //--------------------------------------------------------------------+
 // Interrupt Endpoint API
 //--------------------------------------------------------------------+
@@ -270,12 +306,6 @@ void hidh_close(uint8_t dev_addr)
 // Enumeration
 //--------------------------------------------------------------------+
 
-static bool config_set_protocol             (uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result);
-static bool config_get_report_desc          (uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result);
-static bool config_get_report_desc_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result);
-
-static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
-
 bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
   (void) max_len;
@@ -341,123 +371,88 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   return true;
 }
 
+//--------------------------------------------------------------------+
+// Set Configure
+//--------------------------------------------------------------------+
+
+enum {
+  CONFG_SET_IDLE,
+  CONFIG_SET_PROTOCOL,
+  CONFIG_GET_REPORT_DESC,
+  CONFIG_COMPLETE
+};
+
+static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
+static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result);
+
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
-  uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  tuh_control_xfer_t xfer;
+  xfer.request.wIndex = tu_htole16((uint16_t) itf_num);
+  xfer.user_arg = CONFG_SET_IDLE;
 
-  // Idle rate = 0 mean only report when there is changes
-  uint16_t const idle_rate = 0;
-
-  // SET IDLE request, device can stall if not support this request
-  TU_LOG2("HID Set Idle \r\n");
-  tuh_control_xfer_t const xfer =
-  {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = HID_REQ_CONTROL_SET_IDLE,
-      .wValue   = idle_rate,
-      .wIndex   = itf_num,
-      .wLength  = 0
-    },
-
-    .buffer      = NULL,
-    .complete_cb = (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? config_set_protocol : config_get_report_desc,
-    .user_arg    = 0
-  };
-
-  TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
-
-  return true;
+  // start the set config process
+  return process_set_config(dev_addr, &xfer, XFER_RESULT_SUCCESS);
 }
 
-// Force device to work in BOOT protocol
-static bool config_set_protocol(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
+static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
 {
   // Stall is a valid response for SET_IDLE, therefore we could ignore its result
-  (void) result;
-
-  uint8_t const itf_num     = (uint8_t) xfer->request.wIndex;
-  uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-
-  TU_LOG2("HID Set Protocol to Boot Mode\r\n");
-  hid_itf->protocol_mode = HID_PROTOCOL_BOOT;
-  tuh_control_xfer_t const new_xfer =
-  {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
-      .wValue   = HID_PROTOCOL_BOOT,
-      .wIndex   = hid_itf->itf_num,
-      .wLength  = 0
-    },
-
-    .buffer      = NULL,
-    .complete_cb = config_get_report_desc,
-    .user_arg    = 0
-  };
-
-  TU_ASSERT( tuh_control_xfer(dev_addr, &new_xfer) );
-  return true;
-}
-
-static bool config_get_report_desc(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
-{
-  // We can be here after SET_IDLE or SET_PROTOCOL (boot device)
-  // Trigger assert if result is not successful with set protocol
   if ( xfer->request.bRequest != HID_REQ_CONTROL_SET_IDLE )
   {
     TU_ASSERT(result == XFER_RESULT_SUCCESS);
   }
 
-  uint8_t const itf_num     = (uint8_t) xfer->request.wIndex;
+  uintptr_t const state     = xfer->user_arg;
+  uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->request.wIndex);
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
-  // Get Report Descriptor if possible
-  // using usbh enumeration buffer since report descriptor can be very long
-  if( hid_itf->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE )
+  switch(state)
   {
-    TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", hid_itf->report_desc_len);
+    case CONFG_SET_IDLE:
+    {
+      // Idle rate = 0 mean only report when there is changes
+      const uint16_t idle_rate = 0;
+      const uintptr_t next_state = (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC;
+      TU_VERIFY( _hidh_set_idle(dev_addr, itf_num, idle_rate, process_set_config, next_state) );
+    }
+    break;
 
-    // Driver is mounted without report descriptor
-    config_driver_mount_complete(dev_addr, instance, NULL, 0);
-  }else
-  {
-    TU_ASSERT(tuh_descriptor_get_hid_report(dev_addr, itf_num, hid_itf->report_desc_type, 0, usbh_get_enum_buf(), hid_itf->report_desc_len, config_get_report_desc_complete, 0));
+    case CONFIG_SET_PROTOCOL:
+      TU_VERIFY(_hidh_set_protocol(dev_addr, hid_itf->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC));
+    break;
+
+    case CONFIG_GET_REPORT_DESC:
+      // Get Report Descriptor if possible
+      // using usbh enumeration buffer since report descriptor can be very long
+      if( hid_itf->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE )
+      {
+        TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", hid_itf->report_desc_len);
+
+        // Driver is mounted without report descriptor
+        config_driver_mount_complete(dev_addr, instance, NULL, 0);
+      }else
+      {
+        TU_ASSERT(tuh_descriptor_get_hid_report(dev_addr, itf_num, hid_itf->report_desc_type, 0, usbh_get_enum_buf(), hid_itf->report_desc_len, process_set_config, CONFIG_COMPLETE));
+      }
+      break;
+
+    case CONFIG_COMPLETE:
+    {
+      uint8_t const* desc_report = usbh_get_enum_buf();
+      uint16_t const desc_len    = xfer->request.wLength;
+
+      config_driver_mount_complete(dev_addr, instance, desc_report, desc_len);
+    }
+    break;
+
+    default: break;
   }
 
   return true;
 }
 
-static bool config_get_report_desc_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
-{
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
-
-  uint8_t const itf_num      = (uint8_t) xfer->request.wIndex;
-  uint8_t const instance     = get_instance_id_by_itfnum(dev_addr, itf_num);
-
-  uint8_t const* desc_report = usbh_get_enum_buf();
-  uint16_t const desc_len    = xfer->request.wLength;
-
-  config_driver_mount_complete(dev_addr, instance, desc_report, desc_len);
-
-  return true;
-}
-
 static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
 {
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index c009e5088..b3af65942 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -483,7 +483,7 @@ static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw
   // Capacity response field: Block size and Last LBA are both Big-Endian
   scsi_read_capacity10_resp_t* resp = (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer);
   p_msc->capacity[cbw->lun].block_count = tu_ntohl(resp->last_lba) + 1;
-  p_msc->capacity[cbw->lun].block_size = tu_ntohl(resp->block_size);
+  p_msc->capacity[cbw->lun].block_size  = tu_ntohl(resp->block_size);
 
   // Mark enumeration is complete
   p_msc->mounted = true;
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 418642891..83bca2205 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1297,12 +1297,10 @@ static bool enum_new_device(hcd_event_t* event)
     _dev0.speed = hcd_port_speed_get(_dev0.rhport );
     TU_LOG2("%s Speed\r\n", tu_str_speed[_dev0.speed]);
 
-    //enum_request_addr0_device_desc();
-    tuh_control_xfer_t const xfer =
-    {
-      .complete_cb = process_enumeration,
-      .user_arg    = ENUM_ADDR0_DEVICE_DESC
-    };
+    // start the enumeration process
+    tuh_control_xfer_t xfer;
+    xfer.user_arg = ENUM_ADDR0_DEVICE_DESC;
+
     process_enumeration(0, &xfer, XFER_RESULT_SUCCESS);
 
   }

From 68bfd048a54d1ff2def4cb1ee5285eacdb55f143 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Mar 2022 12:53:52 +0700
Subject: [PATCH 0910/2085] change tuh_control_xfer_t struct

---
 src/class/cdc/cdc_host.c |  30 ++++---
 src/class/hid/hid_host.c | 115 +++++++++++++------------
 src/class/msc/msc_host.c |  30 ++++---
 src/host/hub.c           | 130 +++++++++++++++-------------
 src/host/usbh.c          | 182 ++++++++++++++++++++++++---------------
 src/host/usbh.h          |  27 ++++--
 6 files changed, 292 insertions(+), 222 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 8ca3dfbcb..9838df818 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -124,22 +124,24 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_co
 {
   cdch_data_t const * p_cdc = get_itf(dev_addr);
 
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
+    .wValue   = (rts ? 2 : 0) | (dtr ? 1 : 0),
+    .wIndex   = p_cdc->itf_num,
+    .wLength  = 0
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
-      .wValue   = (rts ? 2 : 0) | (dtr ? 1 : 0),
-      .wIndex   = p_cdc->itf_num,
-      .wLength  = 0
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
     .user_arg    = 0
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 6bcd2f5d3..8c1a5ebc9 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -105,11 +105,11 @@ uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
 
 static bool set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
 {
-  uint8_t const itf_num     = (uint8_t) xfer->request.wIndex;
+  uint8_t const itf_num     = (uint8_t) xfer->setup->wIndex;
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
-  if (XFER_RESULT_SUCCESS == result) hid_itf->protocol_mode = (uint8_t) xfer->request.wValue;
+  if (XFER_RESULT_SUCCESS == result) hid_itf->protocol_mode = (uint8_t) xfer->setup->wValue;
 
   if (tuh_hid_set_protocol_complete_cb)
   {
@@ -124,22 +124,24 @@ static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protoc
 {
   TU_LOG2("HID Set Protocol = %d\r\n", protocol);
 
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
+    .wValue   = protocol,
+    .wIndex   = itf_num,
+    .wLength  = 0
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = HID_REQ_CONTROL_SET_PROTOCOL,
-      .wValue   = protocol,
-      .wIndex   = itf_num,
-      .wLength  = 0
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
     .user_arg    = user_arg
@@ -163,13 +165,13 @@ static bool set_report_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfe
 
   if (tuh_hid_set_report_complete_cb)
   {
-    uint8_t const itf_num     = (uint8_t) xfer->request.wIndex;
+    uint8_t const itf_num     = (uint8_t) xfer->setup->wIndex;
     uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
 
-    uint8_t const report_type = tu_u16_high(xfer->request.wValue);
-    uint8_t const report_id   = tu_u16_low(xfer->request.wValue);
+    uint8_t const report_type = tu_u16_high(xfer->setup->wValue);
+    uint8_t const report_id   = tu_u16_low(xfer->setup->wValue);
 
-    tuh_hid_set_report_complete_cb(dev_addr, instance, report_id, report_type, (result == XFER_RESULT_SUCCESS) ? xfer->request.wLength : 0);
+    tuh_hid_set_report_complete_cb(dev_addr, instance, report_id, report_type, (result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0);
   }
 
   return true;
@@ -180,22 +182,24 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
   TU_LOG2("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len);
 
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = HID_REQ_CONTROL_SET_REPORT,
+    .wValue   = tu_u16(report_type, report_id),
+    .wIndex   = hid_itf->itf_num,
+    .wLength  = len
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = HID_REQ_CONTROL_SET_REPORT,
-      .wValue   = tu_u16(report_type, report_id),
-      .wIndex   = hid_itf->itf_num,
-      .wLength  = len
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = report,
     .complete_cb = set_report_complete,
     .user_arg    = 0
@@ -209,22 +213,24 @@ static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate
 {
   // SET IDLE request, device can stall if not support this request
   TU_LOG2("HID Set Idle \r\n");
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = HID_REQ_CONTROL_SET_IDLE,
+    .wValue   = idle_rate,
+    .wIndex   = itf_num,
+    .wLength  = 0
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = HID_REQ_CONTROL_SET_IDLE,
-      .wValue   = idle_rate,
-      .wIndex   = itf_num,
-      .wLength  = 0
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
     .user_arg    = user_arg
@@ -387,24 +393,27 @@ static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer
 
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
+  tusb_control_request_t request;
+  request.wIndex = tu_htole16((uint16_t) itf_num);
+
   tuh_control_xfer_t xfer;
-  xfer.request.wIndex = tu_htole16((uint16_t) itf_num);
+  xfer.setup = &request;
   xfer.user_arg = CONFG_SET_IDLE;
 
-  // start the set config process
+  // fake request to start the set config process
   return process_set_config(dev_addr, &xfer, XFER_RESULT_SUCCESS);
 }
 
 static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
 {
   // Stall is a valid response for SET_IDLE, therefore we could ignore its result
-  if ( xfer->request.bRequest != HID_REQ_CONTROL_SET_IDLE )
+  if ( xfer->setup->bRequest != HID_REQ_CONTROL_SET_IDLE )
   {
     TU_ASSERT(result == XFER_RESULT_SUCCESS);
   }
 
   uintptr_t const state     = xfer->user_arg;
-  uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->request.wIndex);
+  uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
@@ -441,7 +450,7 @@ static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer
     case CONFIG_COMPLETE:
     {
       uint8_t const* desc_report = usbh_get_enum_buf();
-      uint16_t const desc_len    = xfer->request.wLength;
+      uint16_t const desc_len    = xfer->setup->wLength;
 
       config_driver_mount_complete(dev_addr, instance, desc_report, desc_len);
     }
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index b3af65942..d8910db0f 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -405,22 +405,24 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
 
   //------------- Get Max Lun -------------//
   TU_LOG2("MSC Get Max Lun\r\n");
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_IN
+    },
+    .bRequest = MSC_REQ_GET_MAX_LUN,
+    .wValue   = 0,
+    .wIndex   = itf_num,
+    .wLength  = 1
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_IN
-      },
-      .bRequest = MSC_REQ_GET_MAX_LUN,
-      .wValue   = 0,
-      .wIndex   = itf_num,
-      .wLength  = 1
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = &p_msc->max_lun,
     .complete_cb = config_get_maxlun_complete,
     .user_arg    = 0
diff --git a/src/host/hub.c b/src/host/hub.c
index c1909cb5c..6ce9e4cc6 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -80,22 +80,24 @@ static char const* const _hub_feature_str[] =
 bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
                             tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_OTHER,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = HUB_REQUEST_CLEAR_FEATURE,
+    .wValue   = feature,
+    .wIndex   = hub_port,
+    .wLength  = 0
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_OTHER,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = HUB_REQUEST_CLEAR_FEATURE,
-      .wValue   = feature,
-      .wIndex   = hub_port,
-      .wLength  = 0
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
     .user_arg    = user_arg
@@ -109,22 +111,24 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
 bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
                           tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_OTHER,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = HUB_REQUEST_SET_FEATURE,
+    .wValue   = feature,
+    .wIndex   = hub_port,
+    .wLength  = 0
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_OTHER,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = HUB_REQUEST_SET_FEATURE,
-      .wValue   = feature,
-      .wIndex   = hub_port,
-      .wLength  = 0
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
     .user_arg    = user_arg
@@ -138,22 +142,24 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
 bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
                          tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_OTHER,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_IN
+    },
+    .bRequest = HUB_REQUEST_GET_STATUS,
+    .wValue   = 0,
+    .wIndex   = hub_port,
+    .wLength  = 4
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_OTHER,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_IN
-      },
-      .bRequest = HUB_REQUEST_GET_STATUS,
-      .wValue   = 0,
-      .wIndex   = hub_port,
-      .wLength  = 4
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = resp,
     .complete_cb = complete_cb,
     .user_arg    = user_arg
@@ -228,22 +234,24 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
   TU_ASSERT(itf_num == p_hub->itf_num);
 
   // Get Hub Descriptor
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_IN
+    },
+    .bRequest = HUB_REQUEST_GET_DESCRIPTOR,
+    .wValue   = 0,
+    .wIndex   = 0,
+    .wLength  = sizeof(descriptor_hub_desc_t)
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_DEVICE,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_IN
-      },
-      .bRequest = HUB_REQUEST_GET_DESCRIPTOR,
-      .wValue   = 0,
-      .wIndex   = 0,
-      .wLength  = sizeof(descriptor_hub_desc_t)
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = _hub_buffer,
     .complete_cb = config_set_port_power,
     .user_arg    = 0
@@ -277,7 +285,7 @@ static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t con
   TU_ASSERT(XFER_RESULT_SUCCESS == result);
    hub_interface_t* p_hub = get_itf(dev_addr);
 
-  if (xfer->request.wIndex == p_hub->port_count)
+  if (xfer->setup->wIndex == p_hub->port_count)
   {
     // All ports are power -> queue notification status endpoint and
     // complete the SET CONFIGURATION
@@ -287,7 +295,7 @@ static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t con
   }else
   {
     // power next port
-    uint8_t const hub_port = (uint8_t) (xfer->request.wIndex + 1);
+    uint8_t const hub_port = (uint8_t) (xfer->setup->wIndex + 1);
     return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
   }
 
@@ -333,7 +341,7 @@ static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
-  uint8_t const port_num = (uint8_t) xfer->request.wIndex;
+  uint8_t const port_num = (uint8_t) xfer->setup->wIndex;
 
   // Connection change
   if (p_hub->port_status.change.connection)
@@ -361,7 +369,7 @@ static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
-  uint8_t const port_num = (uint8_t) xfer->request.wIndex;
+  uint8_t const port_num = (uint8_t) xfer->setup->wIndex;
 
   if ( p_hub->port_status.status.connection )
   {
@@ -392,7 +400,7 @@ static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
 
   // hub_interface_t* p_hub = get_itf(dev_addr);
-  uint8_t const port_num = (uint8_t) xfer->request.wIndex;
+  uint8_t const port_num = (uint8_t) xfer->setup->wIndex;
 
   // submit attach event
   hcd_event_t event =
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 83bca2205..d2d819ec2 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -109,6 +109,10 @@ typedef struct {
 
   tu_edpt_state_t ep_status[CFG_TUH_ENDPOINT_MAX][2];
 
+#if CFG_TUH_BARE
+
+#endif
+
 } usbh_device_t;
 
 //--------------------------------------------------------------------+
@@ -241,7 +245,11 @@ static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 // We will only execute control transfer one at a time.
 struct
 {
-  tuh_control_xfer_t xfer;
+  tusb_control_request_t request TU_ATTR_ALIGNED(4);
+  uint8_t* buffer;
+  tuh_control_xfer_cb_t complete_cb;
+  uintptr_t user_arg;
+
   uint8_t daddr;  // device address that is transferring
   volatile uint8_t stage;
 }_ctrl_xfer;
@@ -304,22 +312,24 @@ void osal_task_delay(uint32_t msec)
 static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
                             tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_STANDARD,
+      .direction = TUSB_DIR_IN
+    },
+    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+    .wValue   = tu_htole16( TU_U16(type, index) ),
+    .wIndex   = tu_htole16(language_id),
+    .wLength  = tu_htole16(len)
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_DEVICE,
-        .type      = TUSB_REQ_TYPE_STANDARD,
-        .direction = TUSB_DIR_IN
-      },
-      .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-      .wValue   = tu_htole16( TU_U16(type, index) ),
-      .wIndex   = tu_htole16(language_id),
-      .wLength  = tu_htole16(len)
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = buffer,
     .complete_cb = complete_cb,
     .user_arg    = user_arg
@@ -387,22 +397,24 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
                                    tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   TU_LOG2("HID Get Report Descriptor\r\n");
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_STANDARD,
+      .direction = TUSB_DIR_IN
+    },
+    .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+    .wValue   = tu_htole16(TU_U16(desc_type, index)),
+    .wIndex   = tu_htole16((uint16_t) itf_num),
+    .wLength  = len
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_STANDARD,
-        .direction = TUSB_DIR_IN
-      },
-      .bRequest = TUSB_REQ_GET_DESCRIPTOR,
-      .wValue   = tu_htole16(TU_U16(desc_type, index)),
-      .wIndex   = tu_htole16((uint16_t) itf_num),
-      .wLength  = len
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = buffer,
     .complete_cb = complete_cb,
     .user_arg    = user_arg
@@ -416,22 +428,24 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
 {
   TU_LOG2("Set Configuration = %d\r\n", config_num);
 
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_STANDARD,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = TUSB_REQ_SET_CONFIGURATION,
+    .wValue   = tu_htole16(config_num),
+    .wIndex   = 0,
+    .wLength  = 0
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_DEVICE,
-        .type      = TUSB_REQ_TYPE_STANDARD,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = TUSB_REQ_SET_CONFIGURATION,
-      .wValue   = tu_htole16(config_num),
-      .wIndex   = 0,
-      .wLength  = 0
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
     .user_arg    = user_arg
@@ -895,16 +909,19 @@ bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer)
 
   const uint8_t rhport = usbh_get_rhport(daddr);
 
-  TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->request.bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->request.bRequest] : "Unknown Request");
-  TU_LOG2_VAR(&xfer->request);
+  TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request");
+  TU_LOG2_VAR(&xfer->setup);
   TU_LOG2("\r\n");
 
-  _ctrl_xfer.daddr = daddr;
-  _ctrl_xfer.xfer = (*xfer);
+  _ctrl_xfer.daddr       = daddr;
+  _ctrl_xfer.request     = (*xfer->setup);
+  _ctrl_xfer.buffer      = xfer->buffer;
+  _ctrl_xfer.complete_cb = xfer->complete_cb;
+  _ctrl_xfer.user_arg    = xfer->user_arg;
 
   if (xfer->complete_cb)
   {
-    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.xfer.request) );
+    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
   }else
   {
     // user_arg must point to xfer_result_t to hold result
@@ -914,10 +931,10 @@ bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer)
     // change callback to internal blocking, and result as user argument
     volatile xfer_result_t* result = (volatile xfer_result_t*) xfer->user_arg;
 
-    _ctrl_xfer.xfer.complete_cb = _control_blocking_complete_cb;
+    _ctrl_xfer.complete_cb = _control_blocking_complete_cb;
     *result = XFER_RESULT_INVALID;
 
-    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.xfer.request) );
+    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
 
     while ((*result) == XFER_RESULT_INVALID)
     {
@@ -961,7 +978,16 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
   TU_LOG2("\r\n");
 
   // duplicate xfer since user can execute control transfer within callback
-  tuh_control_xfer_t const xfer_temp = _ctrl_xfer.xfer;
+  tusb_control_request_t const request = _ctrl_xfer.request;
+  tuh_control_xfer_t const xfer_temp =
+  {
+    .ep_addr     = 0,
+    .setup       = &request,
+    .actual_len  = 0,
+    .buffer      = _ctrl_xfer.buffer,
+    .complete_cb = _ctrl_xfer.complete_cb,
+    .user_arg    = _ctrl_xfer.user_arg
+  };
 
   usbh_lock();
   _ctrl_xfer.stage = CONTROL_STAGE_IDLE;
@@ -979,7 +1005,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
   (void) xferred_bytes;
 
   const uint8_t rhport = usbh_get_rhport(dev_addr);
-  tusb_control_request_t const * request = &_ctrl_xfer.xfer.request;
+  tusb_control_request_t const * request = &_ctrl_xfer.request;
 
   if (XFER_RESULT_SUCCESS != result)
   {
@@ -996,7 +1022,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
         {
           // DATA stage: initial data toggle is always 1
           set_control_xfer_stage(CONTROL_STAGE_DATA);
-          return hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.xfer.buffer, request->wLength);
+          return hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
         }
         __attribute__((fallthrough));
 
@@ -1004,7 +1030,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
         if (request->wLength)
         {
           TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
-          TU_LOG2_MEM(_ctrl_xfer.xfer.buffer, request->wLength, 2);
+          TU_LOG2_MEM(_ctrl_xfer.buffer, request->wLength, 2);
         }
 
         // ACK stage: toggle is always 1
@@ -1190,7 +1216,7 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t const * xfe
 
     case ENUM_GET_DEVICE_DESC:
     {
-      uint8_t const new_addr = (uint8_t) tu_le16toh(xfer->request.wValue);
+      uint8_t const new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue);
 
       usbh_device_t* new_dev = get_device(new_addr);
       TU_ASSERT(new_dev);
@@ -1320,6 +1346,12 @@ static bool enum_new_device(hcd_event_t* event)
   return true;
 }
 
+TU_ATTR_ALWAYS_INLINE
+static inline bool is_hub_addr(uint8_t daddr)
+{
+  return daddr > CFG_TUH_DEVICE_MAX;
+}
+
 static uint8_t get_new_address(bool is_hub)
 {
   uint8_t start;
@@ -1360,22 +1392,24 @@ static bool enum_request_set_addr(void)
   new_dev->connected = 1;
   new_dev->ep0_size  = desc_device->bMaxPacketSize0;
 
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_STANDARD,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = TUSB_REQ_SET_ADDRESS,
+    .wValue   = tu_htole16(new_addr),
+    .wIndex   = 0,
+    .wLength  = 0
+  };
+
   tuh_control_xfer_t const xfer =
   {
-    .request =
-    {
-      .bmRequestType_bit =
-      {
-        .recipient = TUSB_REQ_RCPT_DEVICE,
-        .type      = TUSB_REQ_TYPE_STANDARD,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = TUSB_REQ_SET_ADDRESS,
-      .wValue   = tu_htole16(new_addr),
-      .wIndex   = 0,
-      .wLength  = 0
-    },
-
+    .ep_addr     = 0,
+    .setup       = &request,
     .buffer      = NULL,
     .complete_cb = process_enumeration,
     .user_arg    = ENUM_GET_DEVICE_DESC
@@ -1503,8 +1537,14 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
   {
     enum_full_complete();
 
-    // Invoke callback if available
-    if (tuh_mount_cb) tuh_mount_cb(dev_addr);
+#if CFG_TUH_HUB
+    // skip device mount callback for hub
+    if ( !is_hub_addr(dev_addr) )
+#endif
+    {
+      // Invoke callback if available
+      if (tuh_mount_cb) tuh_mount_cb(dev_addr);
+    }
   }
 }
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index fc0590190..7dffcb453 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -46,7 +46,10 @@ typedef bool (*tuh_control_xfer_cb_t)(uint8_t daddr, tuh_control_xfer_t const *
 
 struct tuh_control_xfer_s
 {
-  tusb_control_request_t request TU_ATTR_ALIGNED(4);
+  uint8_t ep_addr;
+  tusb_control_request_t const* setup;
+  uint32_t actual_len;
+
   uint8_t* buffer;
   tuh_control_xfer_cb_t complete_cb;
   uintptr_t user_arg;
@@ -104,14 +107,16 @@ static inline bool tuh_ready(uint8_t daddr)
   return tuh_mounted(daddr) && !tuh_suspended(daddr);
 }
 
+//--------------------------------------------------------------------+
+// Endpoint Asynchronous (non-blocking)
+//--------------------------------------------------------------------+
+
 // Carry out a control transfer
 // true on success, false if there is on-going control transfer or incorrect parameters
 // Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
-bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer);
+bool tuh_control_xfer(uint8_t daddr, tuh_control_xfer_t const* xfer);
 
-// Sync (blocking) version of tuh_control_xfer()
-// return transfer result
-uint8_t tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t const* xfer, uint32_t timeout_ms);
+//bool tuh_edpt_xfer(uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
 
 // Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
@@ -120,6 +125,14 @@ uint8_t tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t const* xfer, uin
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
+//--------------------------------------------------------------------+
+// Endpoint Synchronous (blocking)
+//--------------------------------------------------------------------+
+
+// Sync (blocking) version of tuh_control_xfer()
+// return transfer result
+uint8_t tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t const* xfer, uint32_t timeout_ms);
+
 //--------------------------------------------------------------------+
 // Descriptors Asynchronous (non-blocking)
 //--------------------------------------------------------------------+
@@ -201,10 +214,6 @@ uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_
 // return transfer result
 uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
 
-//--------------------------------------------------------------------+
-//
-//--------------------------------------------------------------------+
-
 #ifdef __cplusplus
  }
 #endif

From 6df420f7f31b4fbf9b95987211e9ed9fef58ac00 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Mar 2022 16:24:43 +0700
Subject: [PATCH 0911/2085] move result into transfer struct

---
 examples/host/bare_api/src/main.c |  6 ++----
 src/class/hid/hid_host.c          | 20 +++++++++++---------
 src/class/msc/msc_host.c          |  8 +++-----
 src/host/hub.c                    | 31 +++++++++++++++----------------
 src/host/usbh.c                   | 26 +++++++++++++-------------
 src/host/usbh.h                   |  6 +++++-
 6 files changed, 49 insertions(+), 48 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 9e6209991..8da7f6a0c 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -115,11 +115,9 @@ static void utf16_to_utf8(uint16_t *temp_buf, size_t buf_len) {
     ((uint8_t*) temp_buf)[utf8_len] = '\0';
 }
 
-bool print_device_descriptor(uint8_t daddr, tuh_control_xfer_t const * xfer, xfer_result_t result)
+bool print_device_descriptor(uint8_t daddr, tuh_control_xfer_t const * xfer)
 {
-  (void) xfer;
-
-  if ( XFER_RESULT_SUCCESS != result )
+  if ( XFER_RESULT_SUCCESS != xfer->result )
   {
     printf("Failed to get device descriptor\r\n");
     return false;
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 8c1a5ebc9..564b927e2 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -103,13 +103,13 @@ uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
   return hid_itf->protocol_mode;
 }
 
-static bool set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
+static bool set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer)
 {
   uint8_t const itf_num     = (uint8_t) xfer->setup->wIndex;
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
-  if (XFER_RESULT_SUCCESS == result) hid_itf->protocol_mode = (uint8_t) xfer->setup->wValue;
+  if (XFER_RESULT_SUCCESS == xfer->result) hid_itf->protocol_mode = (uint8_t) xfer->setup->wValue;
 
   if (tuh_hid_set_protocol_complete_cb)
   {
@@ -159,7 +159,7 @@ bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
   return _hidh_set_protocol(dev_addr, hid_itf->itf_num, protocol, set_protocol_complete, 0);
 }
 
-static bool set_report_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
+static bool set_report_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer)
 {
   TU_LOG2("HID Set Report complete\r\n");
 
@@ -171,7 +171,8 @@ static bool set_report_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfe
     uint8_t const report_type = tu_u16_high(xfer->setup->wValue);
     uint8_t const report_id   = tu_u16_low(xfer->setup->wValue);
 
-    tuh_hid_set_report_complete_cb(dev_addr, instance, report_id, report_type, (result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0);
+    tuh_hid_set_report_complete_cb(dev_addr, instance, report_id, report_type,
+                                   (xfer->result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0);
   }
 
   return true;
@@ -389,7 +390,7 @@ enum {
 };
 
 static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
-static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result);
+static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer);
 
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
@@ -397,19 +398,20 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
   tuh_control_xfer_t xfer;
+  xfer.result = XFER_RESULT_SUCCESS;
   xfer.setup = &request;
   xfer.user_arg = CONFG_SET_IDLE;
 
-  // fake request to start the set config process
-  return process_set_config(dev_addr, &xfer, XFER_RESULT_SUCCESS);
+  // fake request to kick-off the set config process
+  return process_set_config(dev_addr, &xfer);
 }
 
-static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
+static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer)
 {
   // Stall is a valid response for SET_IDLE, therefore we could ignore its result
   if ( xfer->setup->bRequest != HID_REQ_CONTROL_SET_IDLE )
   {
-    TU_ASSERT(result == XFER_RESULT_SUCCESS);
+    TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
   }
 
   uintptr_t const state     = xfer->user_arg;
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index d8910db0f..ca1080eba 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -358,7 +358,7 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 // MSC Enumeration
 //--------------------------------------------------------------------+
 
-static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result);
+static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
 static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
@@ -432,14 +432,12 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer,  xfer_result_t result)
+static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
 {
-  (void) xfer;
-
   msch_interface_t* p_msc = get_itf(dev_addr);
 
   // STALL means zero
-  p_msc->max_lun = (XFER_RESULT_SUCCESS == result) ? _msch_buffer[0] : 0;
+  p_msc->max_lun = (XFER_RESULT_SUCCESS == xfer->result) ? _msch_buffer[0] : 0;
   p_msc->max_lun++; // MAX LUN is minus 1 by specs
 
   // TODO multiple LUN support
diff --git a/src/host/hub.c b/src/host/hub.c
index 6ce9e4cc6..5255fdf7c 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -225,8 +225,8 @@ bool hub_edpt_status_xfer(uint8_t dev_addr)
 // Set Configure
 //--------------------------------------------------------------------+
 
-static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
+static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
 
 bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
@@ -262,10 +262,9 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
+static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
 {
-  (void) xfer;
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
+  TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
 
@@ -280,9 +279,9 @@ static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const *
   return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
 }
 
-static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
+static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
 {
-  TU_ASSERT(XFER_RESULT_SUCCESS == result);
+  TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result);
    hub_interface_t* p_hub = get_itf(dev_addr);
 
   if (xfer->setup->wIndex == p_hub->port_count)
@@ -306,9 +305,9 @@ static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t con
 // Connection Changes
 //--------------------------------------------------------------------+
 
-static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
-static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
+static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
+static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
 
 // callback as response of interrupt endpoint polling
 bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
@@ -336,9 +335,9 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   return true;
 }
 
-static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
+static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
 {
-  TU_ASSERT(result == XFER_RESULT_SUCCESS);
+  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
   uint8_t const port_num = (uint8_t) xfer->setup->wIndex;
@@ -364,9 +363,9 @@ static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t
   return true;
 }
 
-static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
+static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
 {
-  TU_ASSERT(result == XFER_RESULT_SUCCESS);
+  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
   uint8_t const port_num = (uint8_t) xfer->setup->wIndex;
@@ -395,9 +394,9 @@ static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control
   return true;
 }
 
-static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
+static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
 {
-  TU_ASSERT(result == XFER_RESULT_SUCCESS);
+  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
 
   // hub_interface_t* p_hub = get_itf(dev_addr);
   uint8_t const port_num = (uint8_t) xfer->setup->wIndex;
diff --git a/src/host/usbh.c b/src/host/usbh.c
index d2d819ec2..00afe609f 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -882,12 +882,12 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
 // Control transfer
 //--------------------------------------------------------------------+
 
-static bool _control_blocking_complete_cb(uint8_t daddr, tuh_control_xfer_t const * xfer, xfer_result_t result)
+static bool _control_blocking_complete_cb(uint8_t daddr, tuh_control_xfer_t const * xfer)
 {
   (void) daddr;
 
   // update result
-  *((xfer_result_t*) xfer->user_arg) = result;
+  *((xfer_result_t*) xfer->user_arg) = xfer->result;
 
   return true;
 }
@@ -924,19 +924,17 @@ bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer)
     TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
   }else
   {
-    // user_arg must point to xfer_result_t to hold result
-    TU_VERIFY(xfer->user_arg);
-
     // blocking if complete callback is not provided
     // change callback to internal blocking, and result as user argument
-    volatile xfer_result_t* result = (volatile xfer_result_t*) xfer->user_arg;
+    volatile xfer_result_t result = XFER_RESULT_INVALID;
 
+    // use user_arg to point to xfer_result_t
+    _ctrl_xfer.user_arg    = (uintptr_t) &result;
     _ctrl_xfer.complete_cb = _control_blocking_complete_cb;
-    *result = XFER_RESULT_INVALID;
 
     TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
 
-    while ((*result) == XFER_RESULT_INVALID)
+    while (result == XFER_RESULT_INVALID)
     {
       // only need to call task if not preempted RTOS
       #if CFG_TUSB_OS == OPT_OS_NONE || CFG_TUSB_OS == OPT_OS_PICO
@@ -982,6 +980,7 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
   tuh_control_xfer_t const xfer_temp =
   {
     .ep_addr     = 0,
+    .result      = result,
     .setup       = &request,
     .actual_len  = 0,
     .buffer      = _ctrl_xfer.buffer,
@@ -995,7 +994,7 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
 
   if (xfer_temp.complete_cb)
   {
-    xfer_temp.complete_cb(dev_addr, &xfer_temp, result);
+    xfer_temp.complete_cb(dev_addr, &xfer_temp);
   }
 }
 
@@ -1120,9 +1119,9 @@ static bool parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configur
 static void enum_full_complete(void);
 
 // process device enumeration
-static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t const * xfer, xfer_result_t result)
+static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t const * xfer)
 {
-  if (XFER_RESULT_SUCCESS != result)
+  if (XFER_RESULT_SUCCESS != xfer->result)
   {
     // stop enumeration, maybe we could retry this
     enum_full_complete();
@@ -1323,11 +1322,12 @@ static bool enum_new_device(hcd_event_t* event)
     _dev0.speed = hcd_port_speed_get(_dev0.rhport );
     TU_LOG2("%s Speed\r\n", tu_str_speed[_dev0.speed]);
 
-    // start the enumeration process
+    // fake transfer to kick-off the enumeration process
     tuh_control_xfer_t xfer;
+    xfer.result   = XFER_RESULT_SUCCESS;
     xfer.user_arg = ENUM_ADDR0_DEVICE_DESC;
 
-    process_enumeration(0, &xfer, XFER_RESULT_SUCCESS);
+    process_enumeration(0, &xfer);
 
   }
 #if CFG_TUH_HUB
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 7dffcb453..a2372ad01 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -42,15 +42,19 @@
 struct tuh_control_xfer_s;
 typedef struct tuh_control_xfer_s tuh_control_xfer_t;
 
-typedef bool (*tuh_control_xfer_cb_t)(uint8_t daddr, tuh_control_xfer_t const * xfer, xfer_result_t result);
+typedef bool (*tuh_control_xfer_cb_t)(uint8_t daddr, tuh_control_xfer_t const * xfer);
 
 struct tuh_control_xfer_s
 {
   uint8_t ep_addr;
+  xfer_result_t result;
+
   tusb_control_request_t const* setup;
   uint32_t actual_len;
 
   uint8_t* buffer;
+
+
   tuh_control_xfer_cb_t complete_cb;
   uintptr_t user_arg;
 };

From deab8c276a41577eef3d4f4bd3663a5e1860a76a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Mar 2022 16:53:54 +0700
Subject: [PATCH 0912/2085] remove const in xfer callback

---
 src/class/hid/hid_host.c |  8 ++++----
 src/class/msc/msc_host.c |  4 ++--
 src/host/hub.c           | 20 ++++++++++----------
 src/host/usbh.c          | 11 +++++++----
 src/host/usbh.h          |  4 ++--
 5 files changed, 25 insertions(+), 22 deletions(-)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 564b927e2..45090d193 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -103,7 +103,7 @@ uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
   return hid_itf->protocol_mode;
 }
 
-static bool set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer)
+static bool set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   uint8_t const itf_num     = (uint8_t) xfer->setup->wIndex;
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
@@ -159,7 +159,7 @@ bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
   return _hidh_set_protocol(dev_addr, hid_itf->itf_num, protocol, set_protocol_complete, 0);
 }
 
-static bool set_report_complete(uint8_t dev_addr, tuh_control_xfer_t const * xfer)
+static bool set_report_complete(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   TU_LOG2("HID Set Report complete\r\n");
 
@@ -390,7 +390,7 @@ enum {
 };
 
 static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
-static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer);
+static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer);
 
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
@@ -406,7 +406,7 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
   return process_set_config(dev_addr, &xfer);
 }
 
-static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t const * xfer)
+static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   // Stall is a valid response for SET_IDLE, therefore we could ignore its result
   if ( xfer->setup->bRequest != HID_REQ_CONTROL_SET_IDLE )
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index ca1080eba..0a3deb2c9 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -358,7 +358,7 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 // MSC Enumeration
 //--------------------------------------------------------------------+
 
-static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
+static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
 static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
@@ -432,7 +432,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
+static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
 
diff --git a/src/host/hub.c b/src/host/hub.c
index 5255fdf7c..75596d748 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -225,8 +225,8 @@ bool hub_edpt_status_xfer(uint8_t dev_addr)
 // Set Configure
 //--------------------------------------------------------------------+
 
-static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
-static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
+static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
 
 bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
@@ -262,7 +262,7 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
+static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result);
 
@@ -279,7 +279,7 @@ static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t const *
   return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
 }
 
-static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
+static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result);
    hub_interface_t* p_hub = get_itf(dev_addr);
@@ -305,9 +305,9 @@ static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t con
 // Connection Changes
 //--------------------------------------------------------------------+
 
-static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
-static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
-static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer);
+static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
 
 // callback as response of interrupt endpoint polling
 bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
@@ -335,7 +335,7 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   return true;
 }
 
-static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
+static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
 
@@ -363,7 +363,7 @@ static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t
   return true;
 }
 
-static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
+static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
 
@@ -394,7 +394,7 @@ static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control
   return true;
 }
 
-static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t const * xfer)
+static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 00afe609f..09b4c0487 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -882,7 +882,7 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
 // Control transfer
 //--------------------------------------------------------------------+
 
-static bool _control_blocking_complete_cb(uint8_t daddr, tuh_control_xfer_t const * xfer)
+static bool _control_blocking_complete_cb(uint8_t daddr, tuh_control_xfer_t* xfer)
 {
   (void) daddr;
 
@@ -943,12 +943,15 @@ bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer)
 
       // TODO probably some timeout to prevent hanged
     }
+
+    // update result
+    //xfer->result = result;
   }
 
   return true;
 }
 
-uint8_t tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t const* xfer, uint32_t timeout_ms)
+bool tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t* xfer, uint32_t timeout_ms)
 {
   (void) timeout_ms;
 
@@ -977,7 +980,7 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
 
   // duplicate xfer since user can execute control transfer within callback
   tusb_control_request_t const request = _ctrl_xfer.request;
-  tuh_control_xfer_t const xfer_temp =
+  tuh_control_xfer_t xfer_temp =
   {
     .ep_addr     = 0,
     .result      = result,
@@ -1119,7 +1122,7 @@ static bool parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configur
 static void enum_full_complete(void);
 
 // process device enumeration
-static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t const * xfer)
+static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   if (XFER_RESULT_SUCCESS != xfer->result)
   {
diff --git a/src/host/usbh.h b/src/host/usbh.h
index a2372ad01..e5f86d73d 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -42,7 +42,7 @@
 struct tuh_control_xfer_s;
 typedef struct tuh_control_xfer_s tuh_control_xfer_t;
 
-typedef bool (*tuh_control_xfer_cb_t)(uint8_t daddr, tuh_control_xfer_t const * xfer);
+typedef bool (*tuh_control_xfer_cb_t)(uint8_t daddr, tuh_control_xfer_t* xfer);
 
 struct tuh_control_xfer_s
 {
@@ -135,7 +135,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
 
 // Sync (blocking) version of tuh_control_xfer()
 // return transfer result
-uint8_t tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t const* xfer, uint32_t timeout_ms);
+bool tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t * xfer, uint32_t timeout_ms);
 
 //--------------------------------------------------------------------+
 // Descriptors Asynchronous (non-blocking)

From 66942b814b6e24ecfe7db567b29f2e1d114071c1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Mar 2022 16:55:29 +0700
Subject: [PATCH 0913/2085] change return type of callback to void

---
 src/class/hid/hid_host.c | 35 ++++++++++++++--------------
 src/class/msc/msc_host.c |  6 ++---
 src/host/hub.c           | 50 +++++++++++++++++-----------------------
 src/host/usbh.c          | 43 +++++++++++++++-------------------
 src/host/usbh.h          |  2 +-
 5 files changed, 60 insertions(+), 76 deletions(-)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 45090d193..7986ffc1a 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -103,20 +103,21 @@ uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
   return hid_itf->protocol_mode;
 }
 
-static bool set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
-  uint8_t const itf_num     = (uint8_t) xfer->setup->wIndex;
+  uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
 
-  if (XFER_RESULT_SUCCESS == xfer->result) hid_itf->protocol_mode = (uint8_t) xfer->setup->wValue;
+  if (XFER_RESULT_SUCCESS == xfer->result)
+  {
+    hid_itf->protocol_mode = (uint8_t) tu_le16toh(xfer->setup->wValue);
+  }
 
   if (tuh_hid_set_protocol_complete_cb)
   {
     tuh_hid_set_protocol_complete_cb(dev_addr, instance, hid_itf->protocol_mode);
   }
-
-  return true;
 }
 
 
@@ -159,13 +160,13 @@ bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
   return _hidh_set_protocol(dev_addr, hid_itf->itf_num, protocol, set_protocol_complete, 0);
 }
 
-static bool set_report_complete(uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void set_report_complete(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   TU_LOG2("HID Set Report complete\r\n");
 
   if (tuh_hid_set_report_complete_cb)
   {
-    uint8_t const itf_num     = (uint8_t) xfer->setup->wIndex;
+    uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
     uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
 
     uint8_t const report_type = tu_u16_high(xfer->setup->wValue);
@@ -174,8 +175,6 @@ static bool set_report_complete(uint8_t dev_addr, tuh_control_xfer_t* xfer)
     tuh_hid_set_report_complete_cb(dev_addr, instance, report_id, report_type,
                                    (xfer->result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0);
   }
-
-  return true;
 }
 
 bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, void* report, uint16_t len)
@@ -390,7 +389,7 @@ enum {
 };
 
 static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
-static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer);
 
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
@@ -403,15 +402,17 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
   xfer.user_arg = CONFG_SET_IDLE;
 
   // fake request to kick-off the set config process
-  return process_set_config(dev_addr, &xfer);
+  process_set_config(dev_addr, &xfer);
+
+  return true;
 }
 
-static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   // Stall is a valid response for SET_IDLE, therefore we could ignore its result
   if ( xfer->setup->bRequest != HID_REQ_CONTROL_SET_IDLE )
   {
-    TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
+    TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
   }
 
   uintptr_t const state     = xfer->user_arg;
@@ -426,12 +427,12 @@ static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer)
       // Idle rate = 0 mean only report when there is changes
       const uint16_t idle_rate = 0;
       const uintptr_t next_state = (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC;
-      TU_VERIFY( _hidh_set_idle(dev_addr, itf_num, idle_rate, process_set_config, next_state) );
+      _hidh_set_idle(dev_addr, itf_num, idle_rate, process_set_config, next_state);
     }
     break;
 
     case CONFIG_SET_PROTOCOL:
-      TU_VERIFY(_hidh_set_protocol(dev_addr, hid_itf->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC));
+      _hidh_set_protocol(dev_addr, hid_itf->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC);
     break;
 
     case CONFIG_GET_REPORT_DESC:
@@ -445,7 +446,7 @@ static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer)
         config_driver_mount_complete(dev_addr, instance, NULL, 0);
       }else
       {
-        TU_ASSERT(tuh_descriptor_get_hid_report(dev_addr, itf_num, hid_itf->report_desc_type, 0, usbh_get_enum_buf(), hid_itf->report_desc_len, process_set_config, CONFIG_COMPLETE));
+        tuh_descriptor_get_hid_report(dev_addr, itf_num, hid_itf->report_desc_type, 0, usbh_get_enum_buf(), hid_itf->report_desc_len, process_set_config, CONFIG_COMPLETE);
       }
       break;
 
@@ -460,8 +461,6 @@ static bool process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 
     default: break;
   }
-
-  return true;
 }
 
 static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 0a3deb2c9..ca51d63fa 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -358,7 +358,7 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 // MSC Enumeration
 //--------------------------------------------------------------------+
 
-static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
 static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
@@ -432,7 +432,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
 
@@ -444,8 +444,6 @@ static bool config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t* xf
   TU_LOG2("SCSI Test Unit Ready\r\n");
   uint8_t const lun = 0;
   tuh_msc_test_unit_ready(dev_addr, lun, config_test_unit_ready_complete);
-
-  return true;
 }
 
 static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
diff --git a/src/host/hub.c b/src/host/hub.c
index 75596d748..9f17b7eda 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -225,8 +225,8 @@ bool hub_edpt_status_xfer(uint8_t dev_addr)
 // Set Configure
 //--------------------------------------------------------------------+
 
-static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t* xfer);
-static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
 
 bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
@@ -262,9 +262,9 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
-  TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result);
+  TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result, );
 
   hub_interface_t* p_hub = get_itf(dev_addr);
 
@@ -276,38 +276,36 @@ static bool config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 
   // Set Port Power to be able to detect connection, starting with port 1
   uint8_t const hub_port = 1;
-  return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
+  hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
 }
 
-static bool config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
-  TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result);
+  TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result, );
    hub_interface_t* p_hub = get_itf(dev_addr);
 
   if (xfer->setup->wIndex == p_hub->port_count)
   {
     // All ports are power -> queue notification status endpoint and
     // complete the SET CONFIGURATION
-    TU_ASSERT( usbh_edpt_xfer(dev_addr, p_hub->ep_in, &p_hub->status_change, 1) );
+    TU_ASSERT( usbh_edpt_xfer(dev_addr, p_hub->ep_in, &p_hub->status_change, 1), );
 
     usbh_driver_set_config_complete(dev_addr, p_hub->itf_num);
   }else
   {
     // power next port
     uint8_t const hub_port = (uint8_t) (xfer->setup->wIndex + 1);
-    return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
+    hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
   }
-
-  return true;
 }
 
 //--------------------------------------------------------------------+
 // Connection Changes
 //--------------------------------------------------------------------+
 
-static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
-static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
-static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
 
 // callback as response of interrupt endpoint polling
 bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
@@ -335,12 +333,12 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   return true;
 }
 
-static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
-  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
+  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
 
   hub_interface_t* p_hub = get_itf(dev_addr);
-  uint8_t const port_num = (uint8_t) xfer->setup->wIndex;
+  uint8_t const port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
 
   // Connection change
   if (p_hub->port_status.change.connection)
@@ -359,16 +357,14 @@ static bool connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t
     // TODO continue with status_change, or maybe we can do it again with status
     hub_edpt_status_xfer(dev_addr);
   }
-
-  return true;
 }
 
-static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
-  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
+  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
 
   hub_interface_t* p_hub = get_itf(dev_addr);
-  uint8_t const port_num = (uint8_t) xfer->setup->wIndex;
+  uint8_t const port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
 
   if ( p_hub->port_status.status.connection )
   {
@@ -390,16 +386,14 @@ static bool connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control
 
     hcd_event_handler(&event, false);
   }
-
-  return true;
 }
 
-static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
-  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS);
+  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
 
   // hub_interface_t* p_hub = get_itf(dev_addr);
-  uint8_t const port_num = (uint8_t) xfer->setup->wIndex;
+  uint8_t const port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
 
   // submit attach event
   hcd_event_t event =
@@ -414,8 +408,6 @@ static bool connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t
   };
 
   hcd_event_handler(&event, false);
-
-  return true;
 }
 
 #endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 09b4c0487..3ab72ac0e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -882,14 +882,11 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
 // Control transfer
 //--------------------------------------------------------------------+
 
-static bool _control_blocking_complete_cb(uint8_t daddr, tuh_control_xfer_t* xfer)
+static void _control_blocking_complete_cb(uint8_t daddr, tuh_control_xfer_t* xfer)
 {
   (void) daddr;
-
   // update result
   *((xfer_result_t*) xfer->user_arg) = xfer->result;
-
-  return true;
 }
 
 bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer)
@@ -1122,13 +1119,13 @@ static bool parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configur
 static void enum_full_complete(void);
 
 // process device enumeration
-static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 {
   if (XFER_RESULT_SUCCESS != xfer->result)
   {
     // stop enumeration, maybe we could retry this
     enum_full_complete();
-    return false;
+    return;
   }
 
   uintptr_t const state = xfer->user_arg;
@@ -1146,7 +1143,7 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
       {
         // device unplugged while delaying, nothing else to do
         enum_full_complete();
-        return false;
+        return;
       }
 
       _dev0.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH :
@@ -1162,7 +1159,7 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 
     case ENUM_HUB_GET_STATUS_2:
       osal_task_delay(RESET_DELAY);
-      TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_2) );
+      TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_2), );
     break;
 
     case ENUM_HUB_CLEAR_RESET_2:
@@ -1173,7 +1170,7 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
       // Acknowledge Port Reset Change if Reset Successful
       if (port_status.change.reset)
       {
-        TU_ASSERT( hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_SET_ADDR) );
+        TU_ASSERT( hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_SET_ADDR), );
       }
     }
     break;
@@ -1183,11 +1180,11 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
     {
       // TODO probably doesn't need to open/close each enumeration
       uint8_t const addr0 = 0;
-      TU_ASSERT( usbh_edpt_control_open(addr0, 8) );
+      TU_ASSERT( usbh_edpt_control_open(addr0, 8), );
 
       // Get first 8 bytes of device descriptor for Control Endpoint size
       TU_LOG2("Get 8 byte of Device Descriptor\r\n");
-      TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, process_enumeration, ENUM_SET_ADDR));
+      TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, process_enumeration, ENUM_SET_ADDR), );
     }
     break;
 
@@ -1206,7 +1203,7 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
       else
       {
         // after RESET_DELAY the hub_port_reset() already complete
-        TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_HUB_GET_STATUS_2) );
+        TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, process_enumeration, ENUM_HUB_GET_STATUS_2), );
         break;
       }
       #endif
@@ -1221,18 +1218,18 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
       uint8_t const new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue);
 
       usbh_device_t* new_dev = get_device(new_addr);
-      TU_ASSERT(new_dev);
+      TU_ASSERT(new_dev, );
       new_dev->addressed = 1;
 
       // TODO close device 0, may not be needed
       hcd_device_close(_dev0.rhport, 0);
 
       // open control pipe for new address
-      TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size) );
+      TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size), );
 
       // Get full device descriptor
       TU_LOG2("Get Device Descriptor\r\n");
-      TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC));
+      TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC), );
     }
     break;
 
@@ -1240,7 +1237,7 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
     {
       tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
       usbh_device_t* dev = get_device(dev_addr);
-      TU_ASSERT(dev);
+      TU_ASSERT(dev, );
 
       dev->vid            = desc_device->idVendor;
       dev->pid            = desc_device->idProduct;
@@ -1253,7 +1250,7 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
       // Get 9-byte for total length
       uint8_t const config_idx = CONFIG_NUM - 1;
       TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n");
-      TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC) );
+      TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC), );
     }
     break;
 
@@ -1265,28 +1262,28 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
       uint16_t const total_len = tu_le16toh( tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) );
 
       // TODO not enough buffer to hold configuration descriptor
-      TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE);
+      TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE, );
 
       // Get full configuration descriptor
       uint8_t const config_idx = CONFIG_NUM - 1;
       TU_LOG2("Get Configuration[0] Descriptor\r\n");
-      TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, total_len, process_enumeration, ENUM_SET_CONFIG) );
+      TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, total_len, process_enumeration, ENUM_SET_CONFIG), );
     }
     break;
 
     case ENUM_SET_CONFIG:
       // Parse configuration & set up drivers
       // Driver open aren't allowed to make any usb transfer yet
-      TU_ASSERT( parse_configuration_descriptor(dev_addr, (tusb_desc_configuration_t*) _usbh_ctrl_buf) );
+      TU_ASSERT( parse_configuration_descriptor(dev_addr, (tusb_desc_configuration_t*) _usbh_ctrl_buf), );
 
-      TU_ASSERT( tuh_configuration_set(dev_addr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER) );
+      TU_ASSERT( tuh_configuration_set(dev_addr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER), );
     break;
 
     case ENUM_CONFIG_DRIVER:
     {
       TU_LOG2("Device configured\r\n");
       usbh_device_t* dev = get_device(dev_addr);
-      TU_ASSERT(dev);
+      TU_ASSERT(dev, );
 
       dev->configured = 1;
 
@@ -1303,8 +1300,6 @@ static bool process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
       enum_full_complete();
     break;
   }
-
-  return true;
 }
 
 static bool enum_new_device(hcd_event_t* event)
diff --git a/src/host/usbh.h b/src/host/usbh.h
index e5f86d73d..ec6be67dc 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -42,7 +42,7 @@
 struct tuh_control_xfer_s;
 typedef struct tuh_control_xfer_s tuh_control_xfer_t;
 
-typedef bool (*tuh_control_xfer_cb_t)(uint8_t daddr, tuh_control_xfer_t* xfer);
+typedef void (*tuh_control_xfer_cb_t)(uint8_t daddr, tuh_control_xfer_t* xfer);
 
 struct tuh_control_xfer_s
 {

From 1ee699d49d6da7ce8b92cde1636e34ed90ff6396 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Mar 2022 16:56:56 +0700
Subject: [PATCH 0914/2085] update example

---
 examples/host/bare_api/src/main.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 8da7f6a0c..3f0b9ef22 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -115,12 +115,12 @@ static void utf16_to_utf8(uint16_t *temp_buf, size_t buf_len) {
     ((uint8_t*) temp_buf)[utf8_len] = '\0';
 }
 
-bool print_device_descriptor(uint8_t daddr, tuh_control_xfer_t const * xfer)
+void print_device_descriptor(uint8_t daddr, tuh_control_xfer_t* xfer)
 {
   if ( XFER_RESULT_SUCCESS != xfer->result )
   {
     printf("Failed to get device descriptor\r\n");
-    return false;
+    return;
   }
 
   printf("Device %u: ID %04x:%04x\r\n", daddr, desc_device.idVendor, desc_device.idProduct);
@@ -164,8 +164,6 @@ bool print_device_descriptor(uint8_t daddr, tuh_control_xfer_t const * xfer)
   printf("\r\n");
 
   printf("  bNumConfigurations  %u\r\n"     , desc_device.bNumConfigurations);
-
-  return true;
 }
 
 // Invoked when device is mounted (configured)

From 8aedb2ff37901d2d08c28308e2527d73ab179f5c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Mar 2022 17:25:53 +0700
Subject: [PATCH 0915/2085] slightly change the signature of tuh_control_xfer

---
 src/class/cdc/cdc_host.c |  2 +-
 src/class/hid/hid_host.c |  6 +++---
 src/class/msc/msc_host.c |  2 +-
 src/host/hub.c           |  8 ++++----
 src/host/usbh.c          | 10 +++++-----
 src/host/usbh.h          |  4 +---
 6 files changed, 15 insertions(+), 17 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 9838df818..7ae8af77a 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -138,7 +138,7 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_co
     .wLength  = 0
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 7986ffc1a..65fccd32a 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -139,7 +139,7 @@ static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protoc
     .wLength  = 0
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -196,7 +196,7 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
     .wLength  = len
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -227,7 +227,7 @@ static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate
     .wLength  = 0
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index ca51d63fa..fea587386 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -419,7 +419,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
     .wLength  = 1
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
diff --git a/src/host/hub.c b/src/host/hub.c
index 9f17b7eda..36f27398f 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -94,7 +94,7 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
     .wLength  = 0
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -125,7 +125,7 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
     .wLength  = 0
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -156,7 +156,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
     .wLength  = 4
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -248,7 +248,7 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
     .wLength  = sizeof(descriptor_hub_desc_t)
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 3ab72ac0e..2d01c9144 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -326,7 +326,7 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
     .wLength  = tu_htole16(len)
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -411,7 +411,7 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
     .wLength  = len
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -442,7 +442,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
     .wLength  = 0
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -889,7 +889,7 @@ static void _control_blocking_complete_cb(uint8_t daddr, tuh_control_xfer_t* xfe
   *((xfer_result_t*) xfer->user_arg) = xfer->result;
 }
 
-bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t const* xfer)
+bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t* xfer)
 {
   // pre-check to help reducing mutex lock
   TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
@@ -1404,7 +1404,7 @@ static bool enum_request_set_addr(void)
     .wLength  = 0
   };
 
-  tuh_control_xfer_t const xfer =
+  tuh_control_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
diff --git a/src/host/usbh.h b/src/host/usbh.h
index ec6be67dc..801938a39 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -53,8 +53,6 @@ struct tuh_control_xfer_s
   uint32_t actual_len;
 
   uint8_t* buffer;
-
-
   tuh_control_xfer_cb_t complete_cb;
   uintptr_t user_arg;
 };
@@ -118,7 +116,7 @@ static inline bool tuh_ready(uint8_t daddr)
 // Carry out a control transfer
 // true on success, false if there is on-going control transfer or incorrect parameters
 // Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
-bool tuh_control_xfer(uint8_t daddr, tuh_control_xfer_t const* xfer);
+bool tuh_control_xfer(uint8_t daddr, tuh_control_xfer_t* xfer);
 
 //bool tuh_edpt_xfer(uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
 

From 102b99a0e8b30a03bae917028fd064ff1480275b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Mar 2022 20:48:32 +0700
Subject: [PATCH 0916/2085] add actual_len supported

---
 src/host/usbh.c | 46 ++++++++++++++++++++++++++--------------------
 src/host/usbh.h |  8 ++++----
 2 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 2d01c9144..96dd390b0 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -250,6 +250,7 @@ struct
   tuh_control_xfer_cb_t complete_cb;
   uintptr_t user_arg;
 
+  volatile uint16_t actual_len;
   uint8_t daddr;  // device address that is transferring
   volatile uint8_t stage;
 }_ctrl_xfer;
@@ -306,7 +307,7 @@ void osal_task_delay(uint32_t msec)
 #endif
 
 //--------------------------------------------------------------------+
-// Descriptors
+// Descriptors Async
 //--------------------------------------------------------------------+
 
 static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
@@ -455,7 +456,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
 }
 
 //--------------------------------------------------------------------+
-// Asynchronous
+// Descriptor Sync
 //--------------------------------------------------------------------+
 
 #define _CONTROL_SYNC_API(_async_func, _timeout, ...) \
@@ -903,13 +904,13 @@ bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t* xfer)
   usbh_unlock();
 
   TU_VERIFY(is_idle);
-
   const uint8_t rhport = usbh_get_rhport(daddr);
 
   TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request");
   TU_LOG2_VAR(&xfer->setup);
   TU_LOG2("\r\n");
 
+  _ctrl_xfer.actual_len  = 0;
   _ctrl_xfer.daddr       = daddr;
   _ctrl_xfer.request     = (*xfer->setup);
   _ctrl_xfer.buffer      = xfer->buffer;
@@ -941,8 +942,15 @@ bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t* xfer)
       // TODO probably some timeout to prevent hanged
     }
 
-    // update result
-    //xfer->result = result;
+    // update xfer result
+    xfer->result = result;
+    if ( xfer->user_arg )
+    {
+      // if user_arg is not NULL, it is also updated
+      *((xfer_result_t*) xfer->user_arg) = result;
+    }
+
+    xfer->actual_len = _ctrl_xfer.actual_len;
   }
 
   return true;
@@ -952,19 +960,16 @@ bool tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t* xfer, uint32_t tim
 {
   (void) timeout_ms;
 
-  xfer_result_t result = XFER_RESULT_INVALID;
-  tuh_control_xfer_t xfer_sync = (*xfer);
-
-  xfer_sync.complete_cb = NULL;
-  xfer_sync.user_arg = (uintptr_t) &result;
+  // clear callback for sync
+  xfer->complete_cb = NULL;
 
   // TODO use timeout to wait
-  TU_VERIFY(tuh_control_xfer(daddr, &xfer_sync), XFER_RESULT_TIMEOUT);
+  TU_VERIFY(tuh_control_xfer(daddr, xfer));
 
-  return result;
+  return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void set_control_xfer_stage(uint8_t stage)
+TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
 {
   usbh_lock();
   _ctrl_xfer.stage = stage;
@@ -982,7 +987,7 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
     .ep_addr     = 0,
     .result      = result,
     .setup       = &request,
-    .actual_len  = 0,
+    .actual_len  = (uint32_t) _ctrl_xfer.actual_len,
     .buffer      = _ctrl_xfer.buffer,
     .complete_cb = _ctrl_xfer.complete_cb,
     .user_arg    = _ctrl_xfer.user_arg
@@ -1001,7 +1006,6 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
 static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
 {
   (void) ep_addr;
-  (void) xferred_bytes;
 
   const uint8_t rhport = usbh_get_rhport(dev_addr);
   tusb_control_request_t const * request = &_ctrl_xfer.request;
@@ -1020,20 +1024,22 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
         if (request->wLength)
         {
           // DATA stage: initial data toggle is always 1
-          set_control_xfer_stage(CONTROL_STAGE_DATA);
+          _set_control_xfer_stage(CONTROL_STAGE_DATA);
           return hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
         }
         __attribute__((fallthrough));
 
       case CONTROL_STAGE_DATA:
-        if (request->wLength)
+        if (xferred_bytes)
         {
           TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
-          TU_LOG2_MEM(_ctrl_xfer.buffer, request->wLength, 2);
+          TU_LOG2_MEM(_ctrl_xfer.buffer, xferred_bytes, 2);
         }
 
+        _ctrl_xfer.actual_len = xferred_bytes;
+
         // ACK stage: toggle is always 1
-        set_control_xfer_stage(CONTROL_STAGE_ACK);
+        _set_control_xfer_stage(CONTROL_STAGE_ACK);
         hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
       break;
 
@@ -1083,7 +1089,7 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
       hcd_device_close(rhport, dev_addr);
       clear_device(dev);
       // abort on-going control xfer if any
-      if (_ctrl_xfer.daddr == dev_addr) set_control_xfer_stage(CONTROL_STAGE_IDLE);
+      if (_ctrl_xfer.daddr == dev_addr) _set_control_xfer_stage(CONTROL_STAGE_IDLE);
     }
   }
 }
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 801938a39..e6897d8d8 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -50,7 +50,7 @@ struct tuh_control_xfer_s
   xfer_result_t result;
 
   tusb_control_request_t const* setup;
-  uint32_t actual_len;
+  uint32_t actual_len; // excluding setup packet
 
   uint8_t* buffer;
   tuh_control_xfer_cb_t complete_cb;
@@ -115,7 +115,8 @@ static inline bool tuh_ready(uint8_t daddr)
 
 // Carry out a control transfer
 // true on success, false if there is on-going control transfer or incorrect parameters
-// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
+// Note: blocking if complete callback is NULL. In this case 'xfer->result' will be updated
+//       and if 'user_arg' point to a xfer_result_t variable, it will be updated as well.
 bool tuh_control_xfer(uint8_t daddr, tuh_control_xfer_t* xfer);
 
 //bool tuh_edpt_xfer(uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
@@ -123,7 +124,6 @@ bool tuh_control_xfer(uint8_t daddr, tuh_control_xfer_t* xfer);
 // Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
 // true on success, false if there is on-going control transfer or incorrect parameters
-// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
 
@@ -132,7 +132,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
 //--------------------------------------------------------------------+
 
 // Sync (blocking) version of tuh_control_xfer()
-// return transfer result
+// xfer contents will be updated to reflect the transfer
 bool tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t * xfer, uint32_t timeout_ms);
 
 //--------------------------------------------------------------------+

From 55428d7dd215eb2e69a1f654ccc4730525b509d6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Mar 2022 20:52:16 +0700
Subject: [PATCH 0917/2085] rename tuh_control_xfer_t to tuh_xfer_t

---
 examples/host/bare_api/src/main.c |  2 +-
 src/class/cdc/cdc_host.c          |  4 +--
 src/class/cdc/cdc_host.h          |  6 ++---
 src/class/hid/hid_host.c          | 20 +++++++-------
 src/class/msc/msc_host.c          |  6 ++---
 src/host/hub.c                    | 34 ++++++++++++------------
 src/host/hub.h                    | 10 +++----
 src/host/usbh.c                   | 44 +++++++++++++++----------------
 src/host/usbh.h                   | 32 +++++++++++-----------
 9 files changed, 79 insertions(+), 79 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 3f0b9ef22..feb94a6fe 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -115,7 +115,7 @@ static void utf16_to_utf8(uint16_t *temp_buf, size_t buf_len) {
     ((uint8_t*) temp_buf)[utf8_len] = '\0';
 }
 
-void print_device_descriptor(uint8_t daddr, tuh_control_xfer_t* xfer)
+void print_device_descriptor(uint8_t daddr, tuh_xfer_t* xfer)
 {
   if ( XFER_RESULT_SUCCESS != xfer->result )
   {
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 7ae8af77a..a811eb667 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -120,7 +120,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
   return usbh_edpt_xfer(dev_addr, ep_in, p_buffer, length);
 }
 
-bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_xfer_cb_t complete_cb)
+bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb)
 {
   cdch_data_t const * p_cdc = get_itf(dev_addr);
 
@@ -138,7 +138,7 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_co
     .wLength  = 0
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 67162a0ca..33dbd2efb 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -42,14 +42,14 @@
  * \defgroup   CDC_Serial_Host Host
  * @{ */
 
-bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_xfer_cb_t complete_cb);
+bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb);
 
-static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_control_xfer_cb_t complete_cb)
+static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_xfer_cb_t complete_cb)
 {
   return tuh_cdc_set_control_line_state(dev_addr, true, true, complete_cb);
 }
 
-static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_control_xfer_cb_t complete_cb)
+static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_xfer_cb_t complete_cb)
 {
   return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb);
 }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 65fccd32a..705b73c67 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -103,7 +103,7 @@ uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
   return hid_itf->protocol_mode;
 }
 
-static void set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void set_protocol_complete(uint8_t dev_addr, tuh_xfer_t* xfer)
 {
   uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
@@ -121,7 +121,7 @@ static void set_protocol_complete(uint8_t dev_addr, tuh_control_xfer_t* xfer)
 }
 
 
-static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protocol, tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   TU_LOG2("HID Set Protocol = %d\r\n", protocol);
 
@@ -139,7 +139,7 @@ static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protoc
     .wLength  = 0
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -160,7 +160,7 @@ bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
   return _hidh_set_protocol(dev_addr, hid_itf->itf_num, protocol, set_protocol_complete, 0);
 }
 
-static void set_report_complete(uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void set_report_complete(uint8_t dev_addr, tuh_xfer_t* xfer)
 {
   TU_LOG2("HID Set Report complete\r\n");
 
@@ -196,7 +196,7 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
     .wLength  = len
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -209,7 +209,7 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
   return true;
 }
 
-static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate, tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   // SET IDLE request, device can stall if not support this request
   TU_LOG2("HID Set Idle \r\n");
@@ -227,7 +227,7 @@ static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate
     .wLength  = 0
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -389,14 +389,14 @@ enum {
 };
 
 static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
-static void process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void process_set_config(uint8_t dev_addr, tuh_xfer_t* xfer);
 
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
   tusb_control_request_t request;
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
-  tuh_control_xfer_t xfer;
+  tuh_xfer_t xfer;
   xfer.result = XFER_RESULT_SUCCESS;
   xfer.setup = &request;
   xfer.user_arg = CONFG_SET_IDLE;
@@ -407,7 +407,7 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-static void process_set_config(uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void process_set_config(uint8_t dev_addr, tuh_xfer_t* xfer)
 {
   // Stall is a valid response for SET_IDLE, therefore we could ignore its result
   if ( xfer->setup->bRequest != HID_REQ_CONTROL_SET_IDLE )
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index fea587386..789ae9c1a 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -358,7 +358,7 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 // MSC Enumeration
 //--------------------------------------------------------------------+
 
-static void config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void config_get_maxlun_complete (uint8_t dev_addr, tuh_xfer_t* xfer);
 static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
@@ -419,7 +419,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
     .wLength  = 1
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -432,7 +432,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-static void config_get_maxlun_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void config_get_maxlun_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
 
diff --git a/src/host/hub.c b/src/host/hub.c
index 36f27398f..03cf0ecb4 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -78,7 +78,7 @@ static char const* const _hub_feature_str[] =
 // HUB
 //--------------------------------------------------------------------+
 bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
-                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                            tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   tusb_control_request_t const request =
   {
@@ -94,7 +94,7 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
     .wLength  = 0
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -109,7 +109,7 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
 }
 
 bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
-                          tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                          tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   tusb_control_request_t const request =
   {
@@ -125,7 +125,7 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
     .wLength  = 0
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -140,7 +140,7 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
 }
 
 bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
-                         tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                         tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   tusb_control_request_t const request =
   {
@@ -156,7 +156,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
     .wLength  = 4
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -225,8 +225,8 @@ bool hub_edpt_status_xfer(uint8_t dev_addr)
 // Set Configure
 //--------------------------------------------------------------------+
 
-static void config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t* xfer);
-static void config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void config_set_port_power (uint8_t dev_addr, tuh_xfer_t* xfer);
+static void config_port_power_complete (uint8_t dev_addr, tuh_xfer_t* xfer);
 
 bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
@@ -248,7 +248,7 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
     .wLength  = sizeof(descriptor_hub_desc_t)
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -262,7 +262,7 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-static void config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void config_set_port_power (uint8_t dev_addr, tuh_xfer_t* xfer)
 {
   TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result, );
 
@@ -279,7 +279,7 @@ static void config_set_port_power (uint8_t dev_addr, tuh_control_xfer_t* xfer)
   hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
 }
 
-static void config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void config_port_power_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
 {
   TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result, );
    hub_interface_t* p_hub = get_itf(dev_addr);
@@ -303,9 +303,9 @@ static void config_port_power_complete (uint8_t dev_addr, tuh_control_xfer_t* xf
 // Connection Changes
 //--------------------------------------------------------------------+
 
-static void connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
-static void connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
-static void connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer);
+static void connection_get_status_complete (uint8_t dev_addr, tuh_xfer_t* xfer);
+static void connection_clear_conn_change_complete (uint8_t dev_addr, tuh_xfer_t* xfer);
+static void connection_port_reset_complete (uint8_t dev_addr, tuh_xfer_t* xfer);
 
 // callback as response of interrupt endpoint polling
 bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
@@ -333,7 +333,7 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   return true;
 }
 
-static void connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void connection_get_status_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
 
@@ -359,7 +359,7 @@ static void connection_get_status_complete (uint8_t dev_addr, tuh_control_xfer_t
   }
 }
 
-static void connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void connection_clear_conn_change_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
 
@@ -388,7 +388,7 @@ static void connection_clear_conn_change_complete (uint8_t dev_addr, tuh_control
   }
 }
 
-static void connection_port_reset_complete (uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void connection_port_reset_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
 
diff --git a/src/host/hub.h b/src/host/hub.h
index 30cf3dd1c..e5e22102a 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -173,29 +173,29 @@ TU_VERIFY_STATIC( sizeof(hub_port_status_response_t) == 4, "size is not correct"
 
 // Clear feature
 bool hub_port_clear_feature (uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
-                             tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                             tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Set feature
 bool hub_port_set_feature   (uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
-                             tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                             tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get port status
 bool hub_port_get_status    (uint8_t hub_addr, uint8_t hub_port, void* resp,
-                             tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                             tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get status from Interrupt endpoint
 bool hub_edpt_status_xfer(uint8_t dev_addr);
 
 // Reset a port
 static inline bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port,
-                                  tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb, user_arg);
 }
 
 // Clear Reset Change
 static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port,
-                                               tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                               tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   return hub_port_clear_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET_CHANGE, complete_cb, user_arg);
 }
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 96dd390b0..534f2458b 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -247,7 +247,7 @@ struct
 {
   tusb_control_request_t request TU_ATTR_ALIGNED(4);
   uint8_t* buffer;
-  tuh_control_xfer_cb_t complete_cb;
+  tuh_xfer_cb_t complete_cb;
   uintptr_t user_arg;
 
   volatile uint16_t actual_len;
@@ -311,7 +311,7 @@ void osal_task_delay(uint32_t msec)
 //--------------------------------------------------------------------+
 
 static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
-                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                            tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   tusb_control_request_t const request =
   {
@@ -327,7 +327,7 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
     .wLength  = tu_htole16(len)
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -340,20 +340,20 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
 }
 
 bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
-                        tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                        tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   return _get_descriptor(daddr, type, index, 0x0000, buffer, len, complete_cb, user_arg);
 }
 
 bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
-                               tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   len = tu_min16(len, sizeof(tusb_desc_device_t));
   return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb, user_arg);
 }
 
 bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len,
-                                      tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb, user_arg);
 }
@@ -361,14 +361,14 @@ bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer
 //------------- String Descriptor -------------//
 
 bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
-                               tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   return _get_descriptor(daddr, TUSB_DESC_STRING, index, language_id, buffer, len, complete_cb, user_arg);
 }
 
 // Get manufacturer string descriptor
 bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                            tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   usbh_device_t const* dev = get_device(daddr);
   TU_VERIFY(dev && dev->i_manufacturer);
@@ -377,7 +377,7 @@ bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id,
 
 // Get product string descriptor
 bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                       tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                       tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   usbh_device_t const* dev = get_device(daddr);
   TU_VERIFY(dev && dev->i_product);
@@ -386,7 +386,7 @@ bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void
 
 // Get serial string descriptor
 bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                      tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   usbh_device_t const* dev = get_device(daddr);
   TU_VERIFY(dev && dev->i_serial);
@@ -395,7 +395,7 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void*
 
 // Get HID report descriptor
 bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
-                                   tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                   tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   TU_LOG2("HID Get Report Descriptor\r\n");
   tusb_control_request_t const request =
@@ -412,7 +412,7 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
     .wLength  = len
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -425,7 +425,7 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
 }
 
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
-                           tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg)
+                           tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
 {
   TU_LOG2("Set Configuration = %d\r\n", config_num);
 
@@ -443,7 +443,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
     .wLength  = 0
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
@@ -531,7 +531,7 @@ bool tuh_init(uint8_t rhport)
   TU_LOG2("USBH init\r\n");
   TU_LOG2_INT(sizeof(usbh_device_t));
   TU_LOG2_INT(sizeof(hcd_event_t));
-  TU_LOG2_INT(sizeof(tuh_control_xfer_t));
+  TU_LOG2_INT(sizeof(tuh_xfer_t));
 
   // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -883,14 +883,14 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
 // Control transfer
 //--------------------------------------------------------------------+
 
-static void _control_blocking_complete_cb(uint8_t daddr, tuh_control_xfer_t* xfer)
+static void _control_blocking_complete_cb(uint8_t daddr, tuh_xfer_t* xfer)
 {
   (void) daddr;
   // update result
   *((xfer_result_t*) xfer->user_arg) = xfer->result;
 }
 
-bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t* xfer)
+bool tuh_control_xfer (uint8_t daddr, tuh_xfer_t* xfer)
 {
   // pre-check to help reducing mutex lock
   TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
@@ -956,7 +956,7 @@ bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t* xfer)
   return true;
 }
 
-bool tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t* xfer, uint32_t timeout_ms)
+bool tuh_control_xfer_sync(uint8_t daddr, tuh_xfer_t* xfer, uint32_t timeout_ms)
 {
   (void) timeout_ms;
 
@@ -982,7 +982,7 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
 
   // duplicate xfer since user can execute control transfer within callback
   tusb_control_request_t const request = _ctrl_xfer.request;
-  tuh_control_xfer_t xfer_temp =
+  tuh_xfer_t xfer_temp =
   {
     .ep_addr     = 0,
     .result      = result,
@@ -1125,7 +1125,7 @@ static bool parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configur
 static void enum_full_complete(void);
 
 // process device enumeration
-static void process_enumeration(uint8_t dev_addr, tuh_control_xfer_t* xfer)
+static void process_enumeration(uint8_t dev_addr, tuh_xfer_t* xfer)
 {
   if (XFER_RESULT_SUCCESS != xfer->result)
   {
@@ -1327,7 +1327,7 @@ static bool enum_new_device(hcd_event_t* event)
     TU_LOG2("%s Speed\r\n", tu_str_speed[_dev0.speed]);
 
     // fake transfer to kick-off the enumeration process
-    tuh_control_xfer_t xfer;
+    tuh_xfer_t xfer;
     xfer.result   = XFER_RESULT_SUCCESS;
     xfer.user_arg = ENUM_ADDR0_DEVICE_DESC;
 
@@ -1410,7 +1410,7 @@ static bool enum_request_set_addr(void)
     .wLength  = 0
   };
 
-  tuh_control_xfer_t xfer =
+  tuh_xfer_t xfer =
   {
     .ep_addr     = 0,
     .setup       = &request,
diff --git a/src/host/usbh.h b/src/host/usbh.h
index e6897d8d8..73fe2e08f 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -39,12 +39,12 @@
 //--------------------------------------------------------------------+
 
 // forward declaration
-struct tuh_control_xfer_s;
-typedef struct tuh_control_xfer_s tuh_control_xfer_t;
+struct tuh_xfer_s;
+typedef struct tuh_xfer_s tuh_xfer_t;
 
-typedef void (*tuh_control_xfer_cb_t)(uint8_t daddr, tuh_control_xfer_t* xfer);
+typedef void (*tuh_xfer_cb_t)(uint8_t daddr, tuh_xfer_t* xfer);
 
-struct tuh_control_xfer_s
+struct tuh_xfer_s
 {
   uint8_t ep_addr;
   xfer_result_t result;
@@ -53,7 +53,7 @@ struct tuh_control_xfer_s
   uint32_t actual_len; // excluding setup packet
 
   uint8_t* buffer;
-  tuh_control_xfer_cb_t complete_cb;
+  tuh_xfer_cb_t complete_cb;
   uintptr_t user_arg;
 };
 
@@ -117,7 +117,7 @@ static inline bool tuh_ready(uint8_t daddr)
 // true on success, false if there is on-going control transfer or incorrect parameters
 // Note: blocking if complete callback is NULL. In this case 'xfer->result' will be updated
 //       and if 'user_arg' point to a xfer_result_t variable, it will be updated as well.
-bool tuh_control_xfer(uint8_t daddr, tuh_control_xfer_t* xfer);
+bool tuh_control_xfer(uint8_t daddr, tuh_xfer_t* xfer);
 
 //bool tuh_edpt_xfer(uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
 
@@ -125,7 +125,7 @@ bool tuh_control_xfer(uint8_t daddr, tuh_control_xfer_t* xfer);
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
-                           tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                           tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 //--------------------------------------------------------------------+
 // Endpoint Synchronous (blocking)
@@ -133,7 +133,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
 
 // Sync (blocking) version of tuh_control_xfer()
 // xfer contents will be updated to reflect the transfer
-bool tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t * xfer, uint32_t timeout_ms);
+bool tuh_control_xfer_sync(uint8_t daddr, tuh_xfer_t * xfer, uint32_t timeout_ms);
 
 //--------------------------------------------------------------------+
 // Descriptors Asynchronous (non-blocking)
@@ -142,43 +142,43 @@ bool tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t * xfer, uint32_t ti
 // Get an descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
-                        tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                        tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get device descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
-                               tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get configuration descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len,
-                                      tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get HID report descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
-                                   tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                                   tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get string descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 // Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
 bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
-                               tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get manufacturer string descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                            tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                                            tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get product string descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                       tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                                       tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 // Get serial string descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                      tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
 
 //--------------------------------------------------------------------+
 // Descriptors Synchronous (blocking)

From 9dd2f11f4a08c337096776eacd919faec3cc939e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Mar 2022 21:20:20 +0700
Subject: [PATCH 0918/2085] add CFG_TUH_API_EDPT_XFER to enable generic edpt
 xfer

---
 examples/host/bare_api/src/tusb_config.h |  8 ++--
 src/host/usbh.c                          | 47 ++++++++++++++++--------
 src/host/usbh.h                          |  8 +++-
 src/tusb_option.h                        |  4 ++
 4 files changed, 46 insertions(+), 21 deletions(-)

diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index 234eca402..9b789290d 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -81,11 +81,11 @@
 // 1 hub typically has 4 ports
 #define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1)
 
-#define CFG_TUH_ENDPOINT_MAX       8
+// Max endpoint per device
+#define CFG_TUH_ENDPOINT_MAX        8
 
-//------------- HID -------------//
-
-#define CFG_TUH_HID_EP_BUFSIZE      64
+// Enable tuh_edpt_xfer() API
+#define CFG_TUH_API_EDPT_XFER       1
 
 #ifdef __cplusplus
  }
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 534f2458b..689634ecd 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -109,8 +109,15 @@ typedef struct {
 
   tu_edpt_state_t ep_status[CFG_TUH_ENDPOINT_MAX][2];
 
-#if CFG_TUH_BARE
-
+#if CFG_TUH_API_EDPT_XFER
+//  struct
+//  {
+//    uint8_t* buffer;
+//    tuh_xfer_cb_t complete_cb;
+//    uintptr_t user_arg;
+//
+//    volatile uint16_t actual_len;
+//  }ep_xfer;
 #endif
 
 } usbh_device_t;
@@ -240,6 +247,16 @@ static osal_queue_t _usbh_q;
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
 static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
+//// internal version of tuh_xfer_t
+//typedef struct
+//{
+//  uint8_t* buffer;
+//  tuh_xfer_cb_t complete_cb;
+//  uintptr_t user_arg;
+//
+//  volatile uint16_t actual_len;
+//}usbh_xfer_t;
+
 // Control transfer: since most controller does not support multiple control transfer
 // on multiple devices concurrently. And control transfer is not used much except enumeration
 // We will only execute control transfer one at a time.
@@ -890,6 +907,19 @@ static void _control_blocking_complete_cb(uint8_t daddr, tuh_xfer_t* xfer)
   *((xfer_result_t*) xfer->user_arg) = xfer->result;
 }
 
+bool tuh_control_xfer_sync(uint8_t daddr, tuh_xfer_t* xfer, uint32_t timeout_ms)
+{
+  (void) timeout_ms;
+
+  // clear callback for sync
+  xfer->complete_cb = NULL;
+
+  // TODO use timeout to wait
+  TU_VERIFY(tuh_control_xfer(daddr, xfer));
+
+  return true;
+}
+
 bool tuh_control_xfer (uint8_t daddr, tuh_xfer_t* xfer)
 {
   // pre-check to help reducing mutex lock
@@ -956,19 +986,6 @@ bool tuh_control_xfer (uint8_t daddr, tuh_xfer_t* xfer)
   return true;
 }
 
-bool tuh_control_xfer_sync(uint8_t daddr, tuh_xfer_t* xfer, uint32_t timeout_ms)
-{
-  (void) timeout_ms;
-
-  // clear callback for sync
-  xfer->complete_cb = NULL;
-
-  // TODO use timeout to wait
-  TU_VERIFY(tuh_control_xfer(daddr, xfer));
-
-  return true;
-}
-
 TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
 {
   usbh_lock();
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 73fe2e08f..2021545ba 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -113,13 +113,17 @@ static inline bool tuh_ready(uint8_t daddr)
 // Endpoint Asynchronous (non-blocking)
 //--------------------------------------------------------------------+
 
-// Carry out a control transfer
+// Submit a control transfer
 // true on success, false if there is on-going control transfer or incorrect parameters
 // Note: blocking if complete callback is NULL. In this case 'xfer->result' will be updated
 //       and if 'user_arg' point to a xfer_result_t variable, it will be updated as well.
 bool tuh_control_xfer(uint8_t daddr, tuh_xfer_t* xfer);
 
-//bool tuh_edpt_xfer(uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
+// Submit a bulk/interrupt transfer
+// true on success, false if there is on-going control transfer or incorrect parameters
+// Note: blocking if complete callback is NULL. In this case 'xfer->result' will be updated
+//       and if 'user_arg' point to a xfer_result_t variable, it will be updated as well.
+bool tuh_edpt_xfer(uint8_t daddr, tuh_xfer_t* xfer);
 
 // Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 0352faaed..bd87a953c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -392,6 +392,10 @@
 #define CFG_TUH_VENDOR 0
 #endif
 
+#ifndef CFG_TUH_API_EDPT_XFER
+#define CFG_TUH_API_EDPT_XFER 0
+#endif
+
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------

From f89ff939d8088135cedaa4e4f3885f88d1670529 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 17 Mar 2022 22:37:51 +0700
Subject: [PATCH 0919/2085] rename user_arg to user_data

---
 src/class/cdc/cdc_host.c |  2 +-
 src/class/hid/hid_host.c | 18 ++++----
 src/class/msc/msc_host.c |  2 +-
 src/host/hub.c           | 14 +++---
 src/host/hub.h           | 14 +++---
 src/host/usbh.c          | 93 ++++++++++++++++++++++------------------
 src/host/usbh.h          | 37 ++++++++--------
 7 files changed, 95 insertions(+), 85 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index a811eb667..2795750ed 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -144,7 +144,7 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xf
     .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
-    .user_arg    = 0
+    .user_data    = 0
   };
 
   return tuh_control_xfer(dev_addr, &xfer);
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 705b73c67..0ad917815 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -121,7 +121,7 @@ static void set_protocol_complete(uint8_t dev_addr, tuh_xfer_t* xfer)
 }
 
 
-static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   TU_LOG2("HID Set Protocol = %d\r\n", protocol);
 
@@ -145,7 +145,7 @@ static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protoc
     .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
-    .user_arg    = user_arg
+    .user_data   = user_data
   };
 
   TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
@@ -202,14 +202,14 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
     .setup       = &request,
     .buffer      = report,
     .complete_cb = set_report_complete,
-    .user_arg    = 0
+    .user_data   = 0
   };
 
   TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
   return true;
 }
 
-static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   // SET IDLE request, device can stall if not support this request
   TU_LOG2("HID Set Idle \r\n");
@@ -233,7 +233,7 @@ static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate
     .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
-    .user_arg    = user_arg
+    .user_data   = user_data
   };
 
   TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
@@ -397,9 +397,9 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
   tuh_xfer_t xfer;
-  xfer.result = XFER_RESULT_SUCCESS;
-  xfer.setup = &request;
-  xfer.user_arg = CONFG_SET_IDLE;
+  xfer.result    = XFER_RESULT_SUCCESS;
+  xfer.setup     = &request;
+  xfer.user_data = CONFG_SET_IDLE;
 
   // fake request to kick-off the set config process
   process_set_config(dev_addr, &xfer);
@@ -415,7 +415,7 @@ static void process_set_config(uint8_t dev_addr, tuh_xfer_t* xfer)
     TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
   }
 
-  uintptr_t const state     = xfer->user_arg;
+  uintptr_t const state     = xfer->user_data;
   uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
   hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 789ae9c1a..5a34f2d56 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -425,7 +425,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
     .setup       = &request,
     .buffer      = &p_msc->max_lun,
     .complete_cb = config_get_maxlun_complete,
-    .user_arg    = 0
+    .user_data    = 0
   };
   TU_ASSERT(tuh_control_xfer(dev_addr, &xfer));
 
diff --git a/src/host/hub.c b/src/host/hub.c
index 03cf0ecb4..ac24988d8 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -78,7 +78,7 @@ static char const* const _hub_feature_str[] =
 // HUB
 //--------------------------------------------------------------------+
 bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
-                            tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                            tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   tusb_control_request_t const request =
   {
@@ -100,7 +100,7 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
     .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
-    .user_arg    = user_arg
+    .user_data   = user_data
   };
 
   TU_LOG2("HUB Clear Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port);
@@ -109,7 +109,7 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
 }
 
 bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
-                          tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                          tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   tusb_control_request_t const request =
   {
@@ -131,7 +131,7 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
     .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
-    .user_arg    = user_arg
+    .user_data   = user_data
   };
 
   TU_LOG2("HUB Set Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port);
@@ -140,7 +140,7 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
 }
 
 bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
-                         tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                         tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   tusb_control_request_t const request =
   {
@@ -162,7 +162,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
     .setup       = &request,
     .buffer      = resp,
     .complete_cb = complete_cb,
-    .user_arg    = user_arg
+    .user_data   = user_data
   };
 
   TU_LOG2("HUB Get Port Status: addr = %u port = %u\r\n", hub_addr, hub_port);
@@ -254,7 +254,7 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
     .setup       = &request,
     .buffer      = _hub_buffer,
     .complete_cb = config_set_port_power,
-    .user_arg    = 0
+    .user_data    = 0
   };
 
   TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
diff --git a/src/host/hub.h b/src/host/hub.h
index e5e22102a..390740e1f 100644
--- a/src/host/hub.h
+++ b/src/host/hub.h
@@ -173,31 +173,31 @@ TU_VERIFY_STATIC( sizeof(hub_port_status_response_t) == 4, "size is not correct"
 
 // Clear feature
 bool hub_port_clear_feature (uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
-                             tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                             tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Set feature
 bool hub_port_set_feature   (uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
-                             tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                             tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Get port status
 bool hub_port_get_status    (uint8_t hub_addr, uint8_t hub_port, void* resp,
-                             tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                             tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Get status from Interrupt endpoint
 bool hub_edpt_status_xfer(uint8_t dev_addr);
 
 // Reset a port
 static inline bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port,
-                                  tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb, user_arg);
+  return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb, user_data);
 }
 
 // Clear Reset Change
 static inline bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port,
-                                               tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                               tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  return hub_port_clear_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET_CHANGE, complete_cb, user_arg);
+  return hub_port_clear_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET_CHANGE, complete_cb, user_data);
 }
 
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 689634ecd..69543854d 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -110,14 +110,14 @@ typedef struct {
   tu_edpt_state_t ep_status[CFG_TUH_ENDPOINT_MAX][2];
 
 #if CFG_TUH_API_EDPT_XFER
-//  struct
-//  {
-//    uint8_t* buffer;
-//    tuh_xfer_cb_t complete_cb;
-//    uintptr_t user_arg;
-//
-//    volatile uint16_t actual_len;
-//  }ep_xfer;
+  struct
+  {
+    uint8_t* buffer;
+    tuh_xfer_cb_t complete_cb;
+    uintptr_t user_data;
+    uint16_t buflen;
+    volatile uint16_t actual_len;
+  }ep_xfer;
 #endif
 
 } usbh_device_t;
@@ -252,7 +252,7 @@ static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 //{
 //  uint8_t* buffer;
 //  tuh_xfer_cb_t complete_cb;
-//  uintptr_t user_arg;
+//  uintptr_t user_data;
 //
 //  volatile uint16_t actual_len;
 //}usbh_xfer_t;
@@ -265,7 +265,7 @@ struct
   tusb_control_request_t request TU_ATTR_ALIGNED(4);
   uint8_t* buffer;
   tuh_xfer_cb_t complete_cb;
-  uintptr_t user_arg;
+  uintptr_t user_data;
 
   volatile uint16_t actual_len;
   uint8_t daddr;  // device address that is transferring
@@ -328,7 +328,7 @@ void osal_task_delay(uint32_t msec)
 //--------------------------------------------------------------------+
 
 static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
-                            tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                            tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   tusb_control_request_t const request =
   {
@@ -350,69 +350,69 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
     .setup       = &request,
     .buffer      = buffer,
     .complete_cb = complete_cb,
-    .user_arg    = user_arg
+    .user_data   = user_data
   };
 
   return tuh_control_xfer(daddr, &xfer);
 }
 
 bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
-                        tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                        tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  return _get_descriptor(daddr, type, index, 0x0000, buffer, len, complete_cb, user_arg);
+  return _get_descriptor(daddr, type, index, 0x0000, buffer, len, complete_cb, user_data);
 }
 
 bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   len = tu_min16(len, sizeof(tusb_desc_device_t));
-  return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb, user_arg);
+  return tuh_descriptor_get(daddr, TUSB_DESC_DEVICE, 0, buffer, len, complete_cb, user_data);
 }
 
 bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len,
-                                      tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb, user_arg);
+  return tuh_descriptor_get(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, complete_cb, user_data);
 }
 
 //------------- String Descriptor -------------//
 
 bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  return _get_descriptor(daddr, TUSB_DESC_STRING, index, language_id, buffer, len, complete_cb, user_arg);
+  return _get_descriptor(daddr, TUSB_DESC_STRING, index, language_id, buffer, len, complete_cb, user_data);
 }
 
 // Get manufacturer string descriptor
 bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                            tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                            tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   usbh_device_t const* dev = get_device(daddr);
   TU_VERIFY(dev && dev->i_manufacturer);
-  return tuh_descriptor_get_string(daddr, dev->i_manufacturer, language_id, buffer, len, complete_cb, user_arg);
+  return tuh_descriptor_get_string(daddr, dev->i_manufacturer, language_id, buffer, len, complete_cb, user_data);
 }
 
 // Get product string descriptor
 bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                       tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                       tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   usbh_device_t const* dev = get_device(daddr);
   TU_VERIFY(dev && dev->i_product);
-  return tuh_descriptor_get_string(daddr, dev->i_product, language_id, buffer, len, complete_cb, user_arg);
+  return tuh_descriptor_get_string(daddr, dev->i_product, language_id, buffer, len, complete_cb, user_data);
 }
 
 // Get serial string descriptor
 bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                      tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   usbh_device_t const* dev = get_device(daddr);
   TU_VERIFY(dev && dev->i_serial);
-  return tuh_descriptor_get_string(daddr, dev->i_serial, language_id, buffer, len, complete_cb, user_arg);
+  return tuh_descriptor_get_string(daddr, dev->i_serial, language_id, buffer, len, complete_cb, user_data);
 }
 
 // Get HID report descriptor
 bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
-                                   tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   TU_LOG2("HID Get Report Descriptor\r\n");
   tusb_control_request_t const request =
@@ -435,14 +435,14 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
     .setup       = &request,
     .buffer      = buffer,
     .complete_cb = complete_cb,
-    .user_arg    = user_arg
+    .user_data   = user_data
   };
 
   return tuh_control_xfer(daddr, &xfer);
 }
 
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
-                           tuh_xfer_cb_t complete_cb, uintptr_t user_arg)
+                           tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   TU_LOG2("Set Configuration = %d\r\n", config_num);
 
@@ -466,7 +466,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
     .setup       = &request,
     .buffer      = NULL,
     .complete_cb = complete_cb,
-    .user_arg    = user_arg
+    .user_data   = user_data
   };
 
   return tuh_control_xfer(daddr, &xfer);
@@ -904,7 +904,7 @@ static void _control_blocking_complete_cb(uint8_t daddr, tuh_xfer_t* xfer)
 {
   (void) daddr;
   // update result
-  *((xfer_result_t*) xfer->user_arg) = xfer->result;
+  *((xfer_result_t*) xfer->user_data) = xfer->result;
 }
 
 bool tuh_control_xfer_sync(uint8_t daddr, tuh_xfer_t* xfer, uint32_t timeout_ms)
@@ -945,7 +945,7 @@ bool tuh_control_xfer (uint8_t daddr, tuh_xfer_t* xfer)
   _ctrl_xfer.request     = (*xfer->setup);
   _ctrl_xfer.buffer      = xfer->buffer;
   _ctrl_xfer.complete_cb = xfer->complete_cb;
-  _ctrl_xfer.user_arg    = xfer->user_arg;
+  _ctrl_xfer.user_data   = xfer->user_data;
 
   if (xfer->complete_cb)
   {
@@ -956,8 +956,8 @@ bool tuh_control_xfer (uint8_t daddr, tuh_xfer_t* xfer)
     // change callback to internal blocking, and result as user argument
     volatile xfer_result_t result = XFER_RESULT_INVALID;
 
-    // use user_arg to point to xfer_result_t
-    _ctrl_xfer.user_arg    = (uintptr_t) &result;
+    // use user_data to point to xfer_result_t
+    _ctrl_xfer.user_data   = (uintptr_t) &result;
     _ctrl_xfer.complete_cb = _control_blocking_complete_cb;
 
     TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
@@ -974,10 +974,10 @@ bool tuh_control_xfer (uint8_t daddr, tuh_xfer_t* xfer)
 
     // update xfer result
     xfer->result = result;
-    if ( xfer->user_arg )
+    if ( xfer->user_data )
     {
-      // if user_arg is not NULL, it is also updated
-      *((xfer_result_t*) xfer->user_arg) = result;
+      // if user_data is not NULL, it is also updated
+      *((xfer_result_t*) xfer->user_data) = result;
     }
 
     xfer->actual_len = _ctrl_xfer.actual_len;
@@ -1007,7 +1007,7 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
     .actual_len  = (uint32_t) _ctrl_xfer.actual_len,
     .buffer      = _ctrl_xfer.buffer,
     .complete_cb = _ctrl_xfer.complete_cb,
-    .user_arg    = _ctrl_xfer.user_arg
+    .user_data   = _ctrl_xfer.user_data
   };
 
   usbh_lock();
@@ -1075,6 +1075,15 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 //
 //--------------------------------------------------------------------+
 
+bool tuh_edpt_xfer(uint8_t daddr, tuh_xfer_t* xfer)
+{
+  return true;
+}
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 // a device unplugged from rhport:hub_addr:hub_port
 static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
 {
@@ -1151,7 +1160,7 @@ static void process_enumeration(uint8_t dev_addr, tuh_xfer_t* xfer)
     return;
   }
 
-  uintptr_t const state = xfer->user_arg;
+  uintptr_t const state = xfer->user_data;
   switch(state)
   {
 #if CFG_TUH_HUB
@@ -1345,8 +1354,8 @@ static bool enum_new_device(hcd_event_t* event)
 
     // fake transfer to kick-off the enumeration process
     tuh_xfer_t xfer;
-    xfer.result   = XFER_RESULT_SUCCESS;
-    xfer.user_arg = ENUM_ADDR0_DEVICE_DESC;
+    xfer.result    = XFER_RESULT_SUCCESS;
+    xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
 
     process_enumeration(0, &xfer);
 
@@ -1433,7 +1442,7 @@ static bool enum_request_set_addr(void)
     .setup       = &request,
     .buffer      = NULL,
     .complete_cb = process_enumeration,
-    .user_arg    = ENUM_GET_DEVICE_DESC
+    .user_data   = ENUM_GET_DEVICE_DESC
   };
 
   uint8_t const addr0 = 0;
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 2021545ba..30868d2f2 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -47,14 +47,15 @@ typedef void (*tuh_xfer_cb_t)(uint8_t daddr, tuh_xfer_t* xfer);
 struct tuh_xfer_s
 {
   uint8_t ep_addr;
-  xfer_result_t result;
-
-  tusb_control_request_t const* setup;
-  uint32_t actual_len; // excluding setup packet
-
+  tusb_control_request_t const* setup; // pointer to setup packet if control transfer
+  uint32_t buflen;
   uint8_t* buffer;
   tuh_xfer_cb_t complete_cb;
-  uintptr_t user_arg;
+  uintptr_t user_data;
+
+  // will be updated when transfer is complete
+  xfer_result_t result;
+  uint32_t actual_len; // excluding setup packet
 };
 
 //--------------------------------------------------------------------+
@@ -116,20 +117,20 @@ static inline bool tuh_ready(uint8_t daddr)
 // Submit a control transfer
 // true on success, false if there is on-going control transfer or incorrect parameters
 // Note: blocking if complete callback is NULL. In this case 'xfer->result' will be updated
-//       and if 'user_arg' point to a xfer_result_t variable, it will be updated as well.
+//       and if 'user_data' point to a xfer_result_t variable, it will be updated as well.
 bool tuh_control_xfer(uint8_t daddr, tuh_xfer_t* xfer);
 
 // Submit a bulk/interrupt transfer
 // true on success, false if there is on-going control transfer or incorrect parameters
 // Note: blocking if complete callback is NULL. In this case 'xfer->result' will be updated
-//       and if 'user_arg' point to a xfer_result_t variable, it will be updated as well.
+//       and if 'user_data' point to a xfer_result_t variable, it will be updated as well.
 bool tuh_edpt_xfer(uint8_t daddr, tuh_xfer_t* xfer);
 
 // Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
-                           tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                           tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 //--------------------------------------------------------------------+
 // Endpoint Synchronous (blocking)
@@ -146,43 +147,43 @@ bool tuh_control_xfer_sync(uint8_t daddr, tuh_xfer_t * xfer, uint32_t timeout_ms
 // Get an descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
-                        tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                        tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Get device descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_device(uint8_t daddr, void* buffer, uint16_t len,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Get configuration descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer, uint16_t len,
-                                      tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Get HID report descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
-                                   tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Get string descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
-// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
+// Blocking if complete callback is NULL, in this case 'user_data' must contain xfer_result_t variable
 bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
-                               tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                               tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Get manufacturer string descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                            tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                                            tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Get product string descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                       tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                                       tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Get serial string descriptor (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
 bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len,
-                                      tuh_xfer_cb_t complete_cb, uintptr_t user_arg);
+                                      tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 //--------------------------------------------------------------------+
 // Descriptors Synchronous (blocking)

From c063ab49443924afec43a295871205ed61535622 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Mar 2022 00:56:51 +0700
Subject: [PATCH 0920/2085] try to fix ci

---
 src/host/usbh.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 69543854d..6808a24a1 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -268,7 +268,7 @@ struct
   uintptr_t user_data;
 
   volatile uint16_t actual_len;
-  uint8_t daddr;  // device address that is transferring
+  uint8_t daddr;  // transferring device
   volatile uint8_t stage;
 }_ctrl_xfer;
 
@@ -548,7 +548,7 @@ bool tuh_init(uint8_t rhport)
   TU_LOG2("USBH init\r\n");
   TU_LOG2_INT(sizeof(usbh_device_t));
   TU_LOG2_INT(sizeof(hcd_event_t));
-  TU_LOG2_INT(sizeof(tuh_xfer_t));
+  TU_LOG2_INT(sizeof(_ctrl_xfer));
 
   // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -1077,6 +1077,8 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 
 bool tuh_edpt_xfer(uint8_t daddr, tuh_xfer_t* xfer)
 {
+  (void) daddr;
+  (void) xfer;
   return true;
 }
 

From 85c6d6d37d3696680b650e211ef8dd279b1f9f26 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Mar 2022 12:51:12 +0700
Subject: [PATCH 0921/2085] minor update for control xfer

---
 src/host/usbh.c | 66 +++++++++++++++++++++++++++----------------------
 1 file changed, 36 insertions(+), 30 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 6808a24a1..a45ab8efa 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -110,14 +110,14 @@ typedef struct {
   tu_edpt_state_t ep_status[CFG_TUH_ENDPOINT_MAX][2];
 
 #if CFG_TUH_API_EDPT_XFER
-  struct
-  {
-    uint8_t* buffer;
-    tuh_xfer_cb_t complete_cb;
-    uintptr_t user_data;
-    uint16_t buflen;
-    volatile uint16_t actual_len;
-  }ep_xfer;
+//  struct
+//  {
+//    uint8_t* buffer;
+//    tuh_xfer_cb_t complete_cb;
+//    uintptr_t user_data;
+//    uint16_t buflen;
+//    volatile uint16_t actual_len;
+//  }ep_xfer[[]];
 #endif
 
 } usbh_device_t;
@@ -247,16 +247,6 @@ static osal_queue_t _usbh_q;
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
 static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
-//// internal version of tuh_xfer_t
-//typedef struct
-//{
-//  uint8_t* buffer;
-//  tuh_xfer_cb_t complete_cb;
-//  uintptr_t user_data;
-//
-//  volatile uint16_t actual_len;
-//}usbh_xfer_t;
-
 // Control transfer: since most controller does not support multiple control transfer
 // on multiple devices concurrently. And control transfer is not used much except enumeration
 // We will only execute control transfer one at a time.
@@ -267,9 +257,9 @@ struct
   tuh_xfer_cb_t complete_cb;
   uintptr_t user_data;
 
-  volatile uint16_t actual_len;
-  uint8_t daddr;  // transferring device
+  uint8_t daddr;
   volatile uint8_t stage;
+  volatile uint16_t actual_len;
 }_ctrl_xfer;
 
 //------------- Helper Function -------------//
@@ -298,6 +288,8 @@ bool tuh_mounted(uint8_t dev_addr)
 
 bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
 {
+  *vid = *pid = 0;
+
   usbh_device_t const* dev = get_device(dev_addr);
   TU_VERIFY(dev && dev->configured);
 
@@ -327,6 +319,8 @@ void osal_task_delay(uint32_t msec)
 // Descriptors Async
 //--------------------------------------------------------------------+
 
+// generic helper to get a descriptor
+// if blocking, user_data could be pointed to xfer_result
 static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
                             tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
@@ -353,7 +347,15 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
     .user_data   = user_data
   };
 
-  return tuh_control_xfer(daddr, &xfer);
+  bool const ret = tuh_control_xfer(daddr, &xfer);
+
+  // if blocking, user_data could be pointed to xfer_result
+  if ( !complete_cb && user_data )
+  {
+    *((xfer_result_t*) user_data) = xfer.result;
+  }
+
+  return ret;
 }
 
 bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
@@ -411,6 +413,7 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void*
 }
 
 // Get HID report descriptor
+// if blocking, user_data could be pointed to xfer_result
 bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
                                    tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
@@ -438,7 +441,15 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
     .user_data   = user_data
   };
 
-  return tuh_control_xfer(daddr, &xfer);
+  bool const ret = tuh_control_xfer(daddr, &xfer);
+
+  // if blocking, user_data could be pointed to xfer_result
+  if ( !complete_cb && user_data )
+  {
+    *((xfer_result_t*) user_data) = xfer.result;
+  }
+
+  return ret;
 }
 
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
@@ -549,6 +560,7 @@ bool tuh_init(uint8_t rhport)
   TU_LOG2_INT(sizeof(usbh_device_t));
   TU_LOG2_INT(sizeof(hcd_event_t));
   TU_LOG2_INT(sizeof(_ctrl_xfer));
+  TU_LOG2_INT(sizeof(tuh_xfer_t));
 
   // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -972,14 +984,8 @@ bool tuh_control_xfer (uint8_t daddr, tuh_xfer_t* xfer)
       // TODO probably some timeout to prevent hanged
     }
 
-    // update xfer result
-    xfer->result = result;
-    if ( xfer->user_data )
-    {
-      // if user_data is not NULL, it is also updated
-      *((xfer_result_t*) xfer->user_data) = result;
-    }
-
+    // update transfer result
+    xfer->result     = result;
     xfer->actual_len = _ctrl_xfer.actual_len;
   }
 

From 2ff8978dde779607ddf01ba8e9d8dfeb70bfbd03 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Mar 2022 13:38:30 +0700
Subject: [PATCH 0922/2085] update sync API, move timeout into xfer struct

remove tuh_control_xfer_sync()
---
 examples/host/bare_api/src/main.c |  7 ++---
 src/host/usbh.c                   | 51 +++++++++++--------------------
 src/host/usbh.h                   | 48 ++++++++++++++---------------
 3 files changed, 44 insertions(+), 62 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index feb94a6fe..b472c40c4 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -136,11 +136,10 @@ void print_device_descriptor(uint8_t daddr, tuh_xfer_t* xfer)
   printf("  idProduct           0x%04x\r\n" , desc_device.idProduct);
   printf("  bcdDevice           %04x\r\n"   , desc_device.bcdDevice);
 
-  uint32_t timeout_ms = 10;
   uint16_t temp_buf[128];
 
   printf("  iManufacturer       %u     "     , desc_device.iManufacturer);
-  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), timeout_ms) )
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf)) )
   {
     utf16_to_utf8(temp_buf, TU_ARRAY_SIZE(temp_buf));
     printf((const char*) temp_buf);
@@ -148,7 +147,7 @@ void print_device_descriptor(uint8_t daddr, tuh_xfer_t* xfer)
   printf("\r\n");
 
   printf("  iProduct            %u     "     , desc_device.iProduct);
-  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), timeout_ms))
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf)))
   {
     utf16_to_utf8(temp_buf, TU_ARRAY_SIZE(temp_buf));
     printf((const char*) temp_buf);
@@ -156,7 +155,7 @@ void print_device_descriptor(uint8_t daddr, tuh_xfer_t* xfer)
   printf("\r\n");
 
   printf("  iSerialNumber       %u     "     , desc_device.iSerialNumber);
-  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf), timeout_ms))
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf)))
   {
     utf16_to_utf8(temp_buf, TU_ARRAY_SIZE(temp_buf));
     printf((const char*) temp_buf);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index a45ab8efa..c801707d9 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -487,52 +487,49 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
 // Descriptor Sync
 //--------------------------------------------------------------------+
 
-#define _CONTROL_SYNC_API(_async_func, _timeout, ...) \
-  (void) _timeout; \
+#define _CONTROL_SYNC_API(_async_func, ...) \
   xfer_result_t result = XFER_RESULT_INVALID;\
-  /* TODO use timeout to wait */ \
   TU_VERIFY(_async_func(__VA_ARGS__, NULL, (uintptr_t) &result), XFER_RESULT_TIMEOUT); \
   return (uint8_t) result
 
-uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms)
+uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len)
 {
-  _CONTROL_SYNC_API(tuh_descriptor_get, timeout_ms, daddr, type, index, buffer, len);
+  _CONTROL_SYNC_API(tuh_descriptor_get, daddr, type, index, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len, uint8_t timeout_ms)
+uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len)
 {
-  len = tu_min16(len, sizeof(tusb_desc_device_t));
-  return tuh_descriptor_get_sync(daddr, TUSB_DESC_DEVICE, 0, buffer, len, timeout_ms);
+  _CONTROL_SYNC_API(tuh_descriptor_get_device, daddr, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms)
+uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len)
 {
-  return tuh_descriptor_get_sync(daddr, TUSB_DESC_CONFIGURATION, index, buffer, len, timeout_ms);
+  _CONTROL_SYNC_API(tuh_descriptor_get_configuration, daddr, index, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms)
+uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len)
 {
-  _CONTROL_SYNC_API(tuh_descriptor_get_hid_report, timeout_ms, daddr, itf_num, desc_type, index, buffer, len);
+  _CONTROL_SYNC_API(tuh_descriptor_get_hid_report, daddr, itf_num, desc_type, index, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms)
+uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len)
 {
-  _CONTROL_SYNC_API(tuh_descriptor_get_string, timeout_ms, daddr, index, language_id, buffer, len);
+  _CONTROL_SYNC_API(tuh_descriptor_get_string, daddr, index, language_id, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms)
+uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len)
 {
-  _CONTROL_SYNC_API(tuh_descriptor_get_manufacturer_string, timeout_ms, daddr, language_id, buffer, len);
+  _CONTROL_SYNC_API(tuh_descriptor_get_manufacturer_string, daddr, language_id, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms)
+uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len)
 {
-  _CONTROL_SYNC_API(tuh_descriptor_get_product_string, timeout_ms, daddr, language_id, buffer, len);
+  _CONTROL_SYNC_API(tuh_descriptor_get_product_string, daddr, language_id, buffer, len);
 }
 
-uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms)
+uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len)
 {
-  _CONTROL_SYNC_API(tuh_descriptor_get_serial_string, timeout_ms, daddr, language_id, buffer, len);
+  _CONTROL_SYNC_API(tuh_descriptor_get_serial_string, daddr, language_id, buffer, len);
 }
 
 //--------------------------------------------------------------------+
@@ -919,19 +916,7 @@ static void _control_blocking_complete_cb(uint8_t daddr, tuh_xfer_t* xfer)
   *((xfer_result_t*) xfer->user_data) = xfer->result;
 }
 
-bool tuh_control_xfer_sync(uint8_t daddr, tuh_xfer_t* xfer, uint32_t timeout_ms)
-{
-  (void) timeout_ms;
-
-  // clear callback for sync
-  xfer->complete_cb = NULL;
-
-  // TODO use timeout to wait
-  TU_VERIFY(tuh_control_xfer(daddr, xfer));
-
-  return true;
-}
-
+// TODO timeout_ms is not supported yet
 bool tuh_control_xfer (uint8_t daddr, tuh_xfer_t* xfer)
 {
   // pre-check to help reducing mutex lock
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 30868d2f2..21ef86d5d 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -46,16 +46,23 @@ typedef void (*tuh_xfer_cb_t)(uint8_t daddr, tuh_xfer_t* xfer);
 
 struct tuh_xfer_s
 {
+  uint8_t daddr;
   uint8_t ep_addr;
-  tusb_control_request_t const* setup; // pointer to setup packet if control transfer
-  uint32_t buflen;
+
+  xfer_result_t result;
+  uint32_t actual_len; // excluding setup packet
+
+  union
+  {
+    tusb_control_request_t const* setup; // setup packet if control transfer
+    uint32_t buflen;                     // length if not control transfer
+  };
+
   uint8_t* buffer;
   tuh_xfer_cb_t complete_cb;
   uintptr_t user_data;
 
-  // will be updated when transfer is complete
-  xfer_result_t result;
-  uint32_t actual_len; // excluding setup packet
+  uint32_t timeout_ms;
 };
 
 //--------------------------------------------------------------------+
@@ -116,14 +123,13 @@ static inline bool tuh_ready(uint8_t daddr)
 
 // Submit a control transfer
 // true on success, false if there is on-going control transfer or incorrect parameters
-// Note: blocking if complete callback is NULL. In this case 'xfer->result' will be updated
-//       and if 'user_data' point to a xfer_result_t variable, it will be updated as well.
+// Note: blocking if complete callback is NULL.
+//       xfer contents will be updated to reflect the result
 bool tuh_control_xfer(uint8_t daddr, tuh_xfer_t* xfer);
 
 // Submit a bulk/interrupt transfer
 // true on success, false if there is on-going control transfer or incorrect parameters
-// Note: blocking if complete callback is NULL. In this case 'xfer->result' will be updated
-//       and if 'user_data' point to a xfer_result_t variable, it will be updated as well.
+// Note: blocking if complete callback is NULL.
 bool tuh_edpt_xfer(uint8_t daddr, tuh_xfer_t* xfer);
 
 // Set Configuration (control transfer)
@@ -132,14 +138,6 @@ bool tuh_edpt_xfer(uint8_t daddr, tuh_xfer_t* xfer);
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
                            tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
-//--------------------------------------------------------------------+
-// Endpoint Synchronous (blocking)
-//--------------------------------------------------------------------+
-
-// Sync (blocking) version of tuh_control_xfer()
-// xfer contents will be updated to reflect the transfer
-bool tuh_control_xfer_sync(uint8_t daddr, tuh_xfer_t * xfer, uint32_t timeout_ms);
-
 //--------------------------------------------------------------------+
 // Descriptors Asynchronous (non-blocking)
 //--------------------------------------------------------------------+
@@ -191,35 +189,35 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void*
 
 // Sync (blocking) version of tuh_descriptor_get()
 // return transfer result
-uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms);
+uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len);
 
 // Sync (blocking) version of tuh_descriptor_get_device()
 // return transfer result
-uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len, uint8_t timeout_ms);
+uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len);
 
 // Sync (blocking) version of tuh_descriptor_get_configuration()
 // return transfer result
-uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms);
+uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len);
 
 // Sync (blocking) version of tuh_descriptor_get_hid_report()
 // return transfer result
-uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len, uint8_t timeout_ms);
+uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len);
 
 // Sync (blocking) version of tuh_descriptor_get_string()
 // return transfer result
-uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
+uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len);
 
 // Sync (blocking) version of tuh_descriptor_get_manufacturer_string()
 // return transfer result
-uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
+uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len);
 
 // Sync (blocking) version of tuh_descriptor_get_product_string()
 // return transfer result
-uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
+uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len);
 
 // Sync (blocking) version of tuh_descriptor_get_serial_string()
 // return transfer result
-uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, uint8_t timeout_ms);
+uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len);
 
 #ifdef __cplusplus
  }

From 8750e3b57756e4377bb737c578e2742b653c314c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Mar 2022 16:39:35 +0700
Subject: [PATCH 0923/2085] move daddr into xfer struct

---
 examples/host/bare_api/src/main.c |  4 +-
 src/class/cdc/cdc_host.c          |  3 +-
 src/class/hid/hid_host.c          | 53 +++++++++++++----------
 src/class/msc/msc_host.c          | 12 +++---
 src/host/hub.c                    | 70 +++++++++++++++++-------------
 src/host/usbh.c                   | 71 ++++++++++++++++++-------------
 src/host/usbh.h                   | 18 ++++----
 7 files changed, 132 insertions(+), 99 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index b472c40c4..e2e0f4ff3 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -115,7 +115,7 @@ static void utf16_to_utf8(uint16_t *temp_buf, size_t buf_len) {
     ((uint8_t*) temp_buf)[utf8_len] = '\0';
 }
 
-void print_device_descriptor(uint8_t daddr, tuh_xfer_t* xfer)
+void print_device_descriptor(tuh_xfer_t* xfer)
 {
   if ( XFER_RESULT_SUCCESS != xfer->result )
   {
@@ -123,6 +123,8 @@ void print_device_descriptor(uint8_t daddr, tuh_xfer_t* xfer)
     return;
   }
 
+  uint8_t const daddr = xfer->daddr;
+
   printf("Device %u: ID %04x:%04x\r\n", daddr, desc_device.idVendor, desc_device.idProduct);
   printf("Device Descriptor:\r\n");
   printf("  bLength             %u\r\n"     , desc_device.bLength);
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 2795750ed..f946974e8 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -140,6 +140,7 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xf
 
   tuh_xfer_t xfer =
   {
+    .daddr       = dev_addr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
@@ -147,7 +148,7 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xf
     .user_data    = 0
   };
 
-  return tuh_control_xfer(dev_addr, &xfer);
+  return tuh_control_xfer(&xfer);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 0ad917815..fa99b37fe 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -103,11 +103,12 @@ uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
   return hid_itf->protocol_mode;
 }
 
-static void set_protocol_complete(uint8_t dev_addr, tuh_xfer_t* xfer)
+static void set_protocol_complete(tuh_xfer_t* xfer)
 {
   uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  uint8_t const daddr       = xfer->daddr;
+  uint8_t const instance    = get_instance_id_by_itfnum(daddr, itf_num);
+  hidh_interface_t* hid_itf = get_instance(daddr, instance);
 
   if (XFER_RESULT_SUCCESS == xfer->result)
   {
@@ -116,7 +117,7 @@ static void set_protocol_complete(uint8_t dev_addr, tuh_xfer_t* xfer)
 
   if (tuh_hid_set_protocol_complete_cb)
   {
-    tuh_hid_set_protocol_complete_cb(dev_addr, instance, hid_itf->protocol_mode);
+    tuh_hid_set_protocol_complete_cb(daddr, instance, hid_itf->protocol_mode);
   }
 }
 
@@ -141,6 +142,7 @@ static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protoc
 
   tuh_xfer_t xfer =
   {
+    .daddr       = dev_addr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
@@ -148,7 +150,7 @@ static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protoc
     .user_data   = user_data
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
+  TU_ASSERT( tuh_control_xfer(&xfer) );
   return true;
 }
 
@@ -160,19 +162,19 @@ bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
   return _hidh_set_protocol(dev_addr, hid_itf->itf_num, protocol, set_protocol_complete, 0);
 }
 
-static void set_report_complete(uint8_t dev_addr, tuh_xfer_t* xfer)
+static void set_report_complete(tuh_xfer_t* xfer)
 {
   TU_LOG2("HID Set Report complete\r\n");
 
   if (tuh_hid_set_report_complete_cb)
   {
     uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-    uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
+    uint8_t const instance    = get_instance_id_by_itfnum(xfer->daddr, itf_num);
 
     uint8_t const report_type = tu_u16_high(xfer->setup->wValue);
     uint8_t const report_id   = tu_u16_low(xfer->setup->wValue);
 
-    tuh_hid_set_report_complete_cb(dev_addr, instance, report_id, report_type,
+    tuh_hid_set_report_complete_cb(xfer->daddr, instance, report_id, report_type,
                                    (xfer->result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0);
   }
 }
@@ -198,6 +200,7 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
 
   tuh_xfer_t xfer =
   {
+    .daddr       = dev_addr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = report,
@@ -205,7 +208,7 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
     .user_data   = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
+  TU_ASSERT( tuh_control_xfer(&xfer) );
   return true;
 }
 
@@ -229,6 +232,7 @@ static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate
 
   tuh_xfer_t xfer =
   {
+    .daddr       = dev_addr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
@@ -236,7 +240,7 @@ static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate
     .user_data   = user_data
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
+  TU_ASSERT( tuh_control_xfer(&xfer) );
 
   return true;
 }
@@ -389,7 +393,7 @@ enum {
 };
 
 static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
-static void process_set_config(uint8_t dev_addr, tuh_xfer_t* xfer);
+static void process_set_config(tuh_xfer_t* xfer);
 
 bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
@@ -397,17 +401,18 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
   tuh_xfer_t xfer;
+  xfer.daddr     = dev_addr;
   xfer.result    = XFER_RESULT_SUCCESS;
   xfer.setup     = &request;
   xfer.user_data = CONFG_SET_IDLE;
 
   // fake request to kick-off the set config process
-  process_set_config(dev_addr, &xfer);
+  process_set_config(&xfer);
 
   return true;
 }
 
-static void process_set_config(uint8_t dev_addr, tuh_xfer_t* xfer)
+static void process_set_config(tuh_xfer_t* xfer)
 {
   // Stall is a valid response for SET_IDLE, therefore we could ignore its result
   if ( xfer->setup->bRequest != HID_REQ_CONTROL_SET_IDLE )
@@ -415,10 +420,12 @@ static void process_set_config(uint8_t dev_addr, tuh_xfer_t* xfer)
     TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
   }
 
-  uintptr_t const state     = xfer->user_data;
-  uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t const instance    = get_instance_id_by_itfnum(dev_addr, itf_num);
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  uintptr_t const state = xfer->user_data;
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t const daddr   = xfer->daddr;
+
+  uint8_t const instance    = get_instance_id_by_itfnum(daddr, itf_num);
+  hidh_interface_t* hid_itf = get_instance(daddr, instance);
 
   switch(state)
   {
@@ -427,12 +434,12 @@ static void process_set_config(uint8_t dev_addr, tuh_xfer_t* xfer)
       // Idle rate = 0 mean only report when there is changes
       const uint16_t idle_rate = 0;
       const uintptr_t next_state = (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC;
-      _hidh_set_idle(dev_addr, itf_num, idle_rate, process_set_config, next_state);
+      _hidh_set_idle(daddr, itf_num, idle_rate, process_set_config, next_state);
     }
     break;
 
     case CONFIG_SET_PROTOCOL:
-      _hidh_set_protocol(dev_addr, hid_itf->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC);
+      _hidh_set_protocol(daddr, hid_itf->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC);
     break;
 
     case CONFIG_GET_REPORT_DESC:
@@ -443,19 +450,19 @@ static void process_set_config(uint8_t dev_addr, tuh_xfer_t* xfer)
         TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", hid_itf->report_desc_len);
 
         // Driver is mounted without report descriptor
-        config_driver_mount_complete(dev_addr, instance, NULL, 0);
+        config_driver_mount_complete(daddr, instance, NULL, 0);
       }else
       {
-        tuh_descriptor_get_hid_report(dev_addr, itf_num, hid_itf->report_desc_type, 0, usbh_get_enum_buf(), hid_itf->report_desc_len, process_set_config, CONFIG_COMPLETE);
+        tuh_descriptor_get_hid_report(daddr, itf_num, hid_itf->report_desc_type, 0, usbh_get_enum_buf(), hid_itf->report_desc_len, process_set_config, CONFIG_COMPLETE);
       }
       break;
 
     case CONFIG_COMPLETE:
     {
       uint8_t const* desc_report = usbh_get_enum_buf();
-      uint16_t const desc_len    = xfer->setup->wLength;
+      uint16_t const desc_len    = tu_le16toh(xfer->setup->wLength);
 
-      config_driver_mount_complete(dev_addr, instance, desc_report, desc_len);
+      config_driver_mount_complete(daddr, instance, desc_report, desc_len);
     }
     break;
 
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 5a34f2d56..06af781f5 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -358,7 +358,7 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 // MSC Enumeration
 //--------------------------------------------------------------------+
 
-static void config_get_maxlun_complete (uint8_t dev_addr, tuh_xfer_t* xfer);
+static void config_get_maxlun_complete (tuh_xfer_t* xfer);
 static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
 static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
@@ -421,20 +421,22 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
 
   tuh_xfer_t xfer =
   {
+    .daddr       = dev_addr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = &p_msc->max_lun,
     .complete_cb = config_get_maxlun_complete,
     .user_data    = 0
   };
-  TU_ASSERT(tuh_control_xfer(dev_addr, &xfer));
+  TU_ASSERT(tuh_control_xfer(&xfer));
 
   return true;
 }
 
-static void config_get_maxlun_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
+static void config_get_maxlun_complete (tuh_xfer_t* xfer)
 {
-  msch_interface_t* p_msc = get_itf(dev_addr);
+  uint8_t const daddr = xfer->daddr;
+  msch_interface_t* p_msc = get_itf(daddr);
 
   // STALL means zero
   p_msc->max_lun = (XFER_RESULT_SUCCESS == xfer->result) ? _msch_buffer[0] : 0;
@@ -443,7 +445,7 @@ static void config_get_maxlun_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
   // TODO multiple LUN support
   TU_LOG2("SCSI Test Unit Ready\r\n");
   uint8_t const lun = 0;
-  tuh_msc_test_unit_ready(dev_addr, lun, config_test_unit_ready_complete);
+  tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete);
 }
 
 static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
diff --git a/src/host/hub.c b/src/host/hub.c
index ac24988d8..da4f6fe3a 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -96,6 +96,7 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
 
   tuh_xfer_t xfer =
   {
+    .daddr       = hub_addr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
@@ -104,7 +105,7 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
   };
 
   TU_LOG2("HUB Clear Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port);
-  TU_ASSERT( tuh_control_xfer(hub_addr, &xfer) );
+  TU_ASSERT( tuh_control_xfer(&xfer) );
   return true;
 }
 
@@ -127,6 +128,7 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
 
   tuh_xfer_t xfer =
   {
+    .daddr       = hub_addr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
@@ -135,7 +137,7 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
   };
 
   TU_LOG2("HUB Set Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port);
-  TU_ASSERT( tuh_control_xfer(hub_addr, &xfer) );
+  TU_ASSERT( tuh_control_xfer(&xfer) );
   return true;
 }
 
@@ -158,6 +160,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
 
   tuh_xfer_t xfer =
   {
+    .daddr       = hub_addr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = resp,
@@ -166,7 +169,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
   };
 
   TU_LOG2("HUB Get Port Status: addr = %u port = %u\r\n", hub_addr, hub_port);
-  TU_ASSERT( tuh_control_xfer( hub_addr, &xfer) );
+  TU_ASSERT( tuh_control_xfer(&xfer) );
   return true;
 }
 
@@ -225,8 +228,8 @@ bool hub_edpt_status_xfer(uint8_t dev_addr)
 // Set Configure
 //--------------------------------------------------------------------+
 
-static void config_set_port_power (uint8_t dev_addr, tuh_xfer_t* xfer);
-static void config_port_power_complete (uint8_t dev_addr, tuh_xfer_t* xfer);
+static void config_set_port_power (tuh_xfer_t* xfer);
+static void config_port_power_complete (tuh_xfer_t* xfer);
 
 bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
@@ -250,6 +253,7 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
 
   tuh_xfer_t xfer =
   {
+    .daddr       = dev_addr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = _hub_buffer,
@@ -257,16 +261,17 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
     .user_data    = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(dev_addr, &xfer) );
+  TU_ASSERT( tuh_control_xfer(&xfer) );
 
   return true;
 }
 
-static void config_set_port_power (uint8_t dev_addr, tuh_xfer_t* xfer)
+static void config_set_port_power (tuh_xfer_t* xfer)
 {
   TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result, );
 
-  hub_interface_t* p_hub = get_itf(dev_addr);
+  uint8_t const daddr = xfer->daddr;
+  hub_interface_t* p_hub = get_itf(daddr);
 
   // only use number of ports in hub descriptor
   descriptor_hub_desc_t const* desc_hub = (descriptor_hub_desc_t const*) _hub_buffer;
@@ -276,26 +281,28 @@ static void config_set_port_power (uint8_t dev_addr, tuh_xfer_t* xfer)
 
   // Set Port Power to be able to detect connection, starting with port 1
   uint8_t const hub_port = 1;
-  hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
+  hub_port_set_feature(daddr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
 }
 
-static void config_port_power_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
+static void config_port_power_complete (tuh_xfer_t* xfer)
 {
   TU_ASSERT(XFER_RESULT_SUCCESS == xfer->result, );
-   hub_interface_t* p_hub = get_itf(dev_addr);
+
+  uint8_t const daddr = xfer->daddr;
+  hub_interface_t* p_hub = get_itf(daddr);
 
   if (xfer->setup->wIndex == p_hub->port_count)
   {
     // All ports are power -> queue notification status endpoint and
     // complete the SET CONFIGURATION
-    TU_ASSERT( usbh_edpt_xfer(dev_addr, p_hub->ep_in, &p_hub->status_change, 1), );
+    TU_ASSERT( usbh_edpt_xfer(daddr, p_hub->ep_in, &p_hub->status_change, 1), );
 
-    usbh_driver_set_config_complete(dev_addr, p_hub->itf_num);
+    usbh_driver_set_config_complete(daddr, p_hub->itf_num);
   }else
   {
     // power next port
     uint8_t const hub_port = (uint8_t) (xfer->setup->wIndex + 1);
-    hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
+    hub_port_set_feature(daddr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete, 0);
   }
 }
 
@@ -303,9 +310,9 @@ static void config_port_power_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
 // Connection Changes
 //--------------------------------------------------------------------+
 
-static void connection_get_status_complete (uint8_t dev_addr, tuh_xfer_t* xfer);
-static void connection_clear_conn_change_complete (uint8_t dev_addr, tuh_xfer_t* xfer);
-static void connection_port_reset_complete (uint8_t dev_addr, tuh_xfer_t* xfer);
+static void connection_get_status_complete (tuh_xfer_t* xfer);
+static void connection_clear_conn_change_complete (tuh_xfer_t* xfer);
+static void connection_port_reset_complete (tuh_xfer_t* xfer);
 
 // callback as response of interrupt endpoint polling
 bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
@@ -333,11 +340,12 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   return true;
 }
 
-static void connection_get_status_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
+static void connection_get_status_complete (tuh_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
 
-  hub_interface_t* p_hub = get_itf(dev_addr);
+  uint8_t const daddr = xfer->daddr;
+  hub_interface_t* p_hub = get_itf(daddr);
   uint8_t const port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
 
   // Connection change
@@ -347,7 +355,7 @@ static void connection_get_status_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
     //TU_VERIFY(port_status.status_current.port_power && port_status.status_current.port_enable, );
 
     // Acknowledge Port Connection Change
-    hub_port_clear_feature(dev_addr, port_num, HUB_FEATURE_PORT_CONNECTION_CHANGE, connection_clear_conn_change_complete, 0);
+    hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_CONNECTION_CHANGE, connection_clear_conn_change_complete, 0);
   }else
   {
     // Other changes are: Enable, Suspend, Over Current, Reset, L1 state
@@ -355,31 +363,32 @@ static void connection_get_status_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
 
     // prepare for next hub status
     // TODO continue with status_change, or maybe we can do it again with status
-    hub_edpt_status_xfer(dev_addr);
+    hub_edpt_status_xfer(daddr);
   }
 }
 
-static void connection_clear_conn_change_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
+static void connection_clear_conn_change_complete (tuh_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
 
-  hub_interface_t* p_hub = get_itf(dev_addr);
+  uint8_t const daddr = xfer->daddr;
+  hub_interface_t* p_hub = get_itf(daddr);
   uint8_t const port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
 
   if ( p_hub->port_status.status.connection )
   {
     // Reset port if attach event
-    hub_port_reset(dev_addr, port_num, connection_port_reset_complete, 0);
+    hub_port_reset(daddr, port_num, connection_port_reset_complete, 0);
   }else
   {
     // submit detach event
     hcd_event_t event =
     {
-      .rhport     = usbh_get_rhport(dev_addr),
+      .rhport     = usbh_get_rhport(daddr),
       .event_id   = HCD_EVENT_DEVICE_REMOVE,
       .connection =
        {
-         .hub_addr = dev_addr,
+         .hub_addr = daddr,
          .hub_port = port_num
        }
     };
@@ -388,21 +397,22 @@ static void connection_clear_conn_change_complete (uint8_t dev_addr, tuh_xfer_t*
   }
 }
 
-static void connection_port_reset_complete (uint8_t dev_addr, tuh_xfer_t* xfer)
+static void connection_port_reset_complete (tuh_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
 
-  // hub_interface_t* p_hub = get_itf(dev_addr);
+  uint8_t const daddr = xfer->daddr;
+  // hub_interface_t* p_hub = get_itf(daddr);
   uint8_t const port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
 
   // submit attach event
   hcd_event_t event =
   {
-    .rhport     = usbh_get_rhport(dev_addr),
+    .rhport     = usbh_get_rhport(daddr),
     .event_id   = HCD_EVENT_DEVICE_ATTACH,
     .connection =
     {
-      .hub_addr = dev_addr,
+      .hub_addr = daddr,
       .hub_port = port_num
     }
   };
diff --git a/src/host/usbh.c b/src/host/usbh.c
index c801707d9..36774d3dc 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -340,6 +340,7 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
 
   tuh_xfer_t xfer =
   {
+    .daddr       = daddr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = buffer,
@@ -347,7 +348,7 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
     .user_data   = user_data
   };
 
-  bool const ret = tuh_control_xfer(daddr, &xfer);
+  bool const ret = tuh_control_xfer(&xfer);
 
   // if blocking, user_data could be pointed to xfer_result
   if ( !complete_cb && user_data )
@@ -434,6 +435,7 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
 
   tuh_xfer_t xfer =
   {
+    .daddr       = daddr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = buffer,
@@ -441,7 +443,7 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
     .user_data   = user_data
   };
 
-  bool const ret = tuh_control_xfer(daddr, &xfer);
+  bool const ret = tuh_control_xfer(&xfer);
 
   // if blocking, user_data could be pointed to xfer_result
   if ( !complete_cb && user_data )
@@ -473,6 +475,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
 
   tuh_xfer_t xfer =
   {
+    .daddr       = daddr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
@@ -480,7 +483,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
     .user_data   = user_data
   };
 
-  return tuh_control_xfer(daddr, &xfer);
+  return tuh_control_xfer(&xfer);
 }
 
 //--------------------------------------------------------------------+
@@ -909,24 +912,38 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
 // Control transfer
 //--------------------------------------------------------------------+
 
-static void _control_blocking_complete_cb(uint8_t daddr, tuh_xfer_t* xfer)
+static void _control_blocking_complete_cb(tuh_xfer_t* xfer)
 {
-  (void) daddr;
   // update result
   *((xfer_result_t*) xfer->user_data) = xfer->result;
 }
 
 // TODO timeout_ms is not supported yet
-bool tuh_control_xfer (uint8_t daddr, tuh_xfer_t* xfer)
+bool tuh_control_xfer (tuh_xfer_t* xfer)
 {
+  // EP0 with setup packet
+  TU_VERIFY(xfer->ep_addr == 0 && xfer->setup);
+
   // pre-check to help reducing mutex lock
   TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
 
+  uint8_t const daddr = xfer->daddr;
+
   // TODO probably better to use semaphore as resource management than mutex
   usbh_lock();
 
   bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
-  if (is_idle) _ctrl_xfer.stage = CONTROL_STAGE_SETUP;
+  if (is_idle)
+  {
+    _ctrl_xfer.stage       = CONTROL_STAGE_SETUP;
+    _ctrl_xfer.daddr       = daddr;
+    _ctrl_xfer.actual_len  = 0;
+
+    _ctrl_xfer.request     = (*xfer->setup);
+    _ctrl_xfer.buffer      = xfer->buffer;
+    _ctrl_xfer.complete_cb = xfer->complete_cb;
+    _ctrl_xfer.user_data   = xfer->user_data;
+  }
 
   usbh_unlock();
 
@@ -937,13 +954,6 @@ bool tuh_control_xfer (uint8_t daddr, tuh_xfer_t* xfer)
   TU_LOG2_VAR(&xfer->setup);
   TU_LOG2("\r\n");
 
-  _ctrl_xfer.actual_len  = 0;
-  _ctrl_xfer.daddr       = daddr;
-  _ctrl_xfer.request     = (*xfer->setup);
-  _ctrl_xfer.buffer      = xfer->buffer;
-  _ctrl_xfer.complete_cb = xfer->complete_cb;
-  _ctrl_xfer.user_data   = xfer->user_data;
-
   if (xfer->complete_cb)
   {
     TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
@@ -984,7 +994,7 @@ TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
   usbh_unlock();
 }
 
-static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
+static void _xfer_complete(uint8_t daddr, xfer_result_t result)
 {
   TU_LOG2("\r\n");
 
@@ -992,6 +1002,7 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
   tusb_control_request_t const request = _ctrl_xfer.request;
   tuh_xfer_t xfer_temp =
   {
+    .daddr       = daddr,
     .ep_addr     = 0,
     .result      = result,
     .setup       = &request,
@@ -1007,7 +1018,7 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
 
   if (xfer_temp.complete_cb)
   {
-    xfer_temp.complete_cb(dev_addr, &xfer_temp);
+    xfer_temp.complete_cb(&xfer_temp);
   }
 }
 
@@ -1066,9 +1077,8 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 //
 //--------------------------------------------------------------------+
 
-bool tuh_edpt_xfer(uint8_t daddr, tuh_xfer_t* xfer)
+bool tuh_edpt_xfer(tuh_xfer_t* xfer)
 {
-  (void) daddr;
   (void) xfer;
   return true;
 }
@@ -1144,7 +1154,7 @@ static bool parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configur
 static void enum_full_complete(void);
 
 // process device enumeration
-static void process_enumeration(uint8_t dev_addr, tuh_xfer_t* xfer)
+static void process_enumeration(tuh_xfer_t* xfer)
 {
   if (XFER_RESULT_SUCCESS != xfer->result)
   {
@@ -1153,7 +1163,9 @@ static void process_enumeration(uint8_t dev_addr, tuh_xfer_t* xfer)
     return;
   }
 
+  uint8_t const daddr = xfer->daddr;
   uintptr_t const state = xfer->user_data;
+
   switch(state)
   {
 #if CFG_TUH_HUB
@@ -1261,7 +1273,7 @@ static void process_enumeration(uint8_t dev_addr, tuh_xfer_t* xfer)
     case ENUM_GET_9BYTE_CONFIG_DESC:
     {
       tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
-      usbh_device_t* dev = get_device(dev_addr);
+      usbh_device_t* dev = get_device(daddr);
       TU_ASSERT(dev, );
 
       dev->vid            = desc_device->idVendor;
@@ -1275,7 +1287,7 @@ static void process_enumeration(uint8_t dev_addr, tuh_xfer_t* xfer)
       // Get 9-byte for total length
       uint8_t const config_idx = CONFIG_NUM - 1;
       TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n");
-      TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC), );
+      TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC), );
     }
     break;
 
@@ -1292,22 +1304,22 @@ static void process_enumeration(uint8_t dev_addr, tuh_xfer_t* xfer)
       // Get full configuration descriptor
       uint8_t const config_idx = CONFIG_NUM - 1;
       TU_LOG2("Get Configuration[0] Descriptor\r\n");
-      TU_ASSERT( tuh_descriptor_get_configuration(dev_addr, config_idx, _usbh_ctrl_buf, total_len, process_enumeration, ENUM_SET_CONFIG), );
+      TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len, process_enumeration, ENUM_SET_CONFIG), );
     }
     break;
 
     case ENUM_SET_CONFIG:
       // Parse configuration & set up drivers
       // Driver open aren't allowed to make any usb transfer yet
-      TU_ASSERT( parse_configuration_descriptor(dev_addr, (tusb_desc_configuration_t*) _usbh_ctrl_buf), );
+      TU_ASSERT( parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf), );
 
-      TU_ASSERT( tuh_configuration_set(dev_addr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER), );
+      TU_ASSERT( tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER), );
     break;
 
     case ENUM_CONFIG_DRIVER:
     {
       TU_LOG2("Device configured\r\n");
-      usbh_device_t* dev = get_device(dev_addr);
+      usbh_device_t* dev = get_device(daddr);
       TU_ASSERT(dev, );
 
       dev->configured = 1;
@@ -1316,7 +1328,7 @@ static void process_enumeration(uint8_t dev_addr, tuh_xfer_t* xfer)
       // Since driver can perform control transfer within its set_config, this is done asynchronously.
       // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete()
       // TODO use separated API instead of using DRVID_INVALID
-      usbh_driver_set_config_complete(dev_addr, DRVID_INVALID);
+      usbh_driver_set_config_complete(daddr, DRVID_INVALID);
     }
     break;
 
@@ -1347,10 +1359,11 @@ static bool enum_new_device(hcd_event_t* event)
 
     // fake transfer to kick-off the enumeration process
     tuh_xfer_t xfer;
+    xfer.daddr     = 0;
     xfer.result    = XFER_RESULT_SUCCESS;
     xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
 
-    process_enumeration(0, &xfer);
+    process_enumeration(&xfer);
 
   }
 #if CFG_TUH_HUB
@@ -1431,6 +1444,7 @@ static bool enum_request_set_addr(void)
 
   tuh_xfer_t xfer =
   {
+    .daddr       = 0, // dev0
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
@@ -1438,8 +1452,7 @@ static bool enum_request_set_addr(void)
     .user_data   = ENUM_GET_DEVICE_DESC
   };
 
-  uint8_t const addr0 = 0;
-  TU_ASSERT( tuh_control_xfer(addr0, &xfer) );
+  TU_ASSERT( tuh_control_xfer(&xfer) );
 
   return true;
 }
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 21ef86d5d..f79c5cdc8 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -42,7 +42,7 @@
 struct tuh_xfer_s;
 typedef struct tuh_xfer_s tuh_xfer_t;
 
-typedef void (*tuh_xfer_cb_t)(uint8_t daddr, tuh_xfer_t* xfer);
+typedef void (*tuh_xfer_cb_t)(tuh_xfer_t* xfer);
 
 struct tuh_xfer_s
 {
@@ -54,7 +54,7 @@ struct tuh_xfer_s
 
   union
   {
-    tusb_control_request_t const* setup; // setup packet if control transfer
+    tusb_control_request_t const* setup; // setup packet pointer if control transfer
     uint32_t buflen;                     // length if not control transfer
   };
 
@@ -62,7 +62,7 @@ struct tuh_xfer_s
   tuh_xfer_cb_t complete_cb;
   uintptr_t user_data;
 
-  uint32_t timeout_ms;
+  uint32_t timeout_ms; // place holder, not supported yet
 };
 
 //--------------------------------------------------------------------+
@@ -118,19 +118,17 @@ static inline bool tuh_ready(uint8_t daddr)
 }
 
 //--------------------------------------------------------------------+
-// Endpoint Asynchronous (non-blocking)
+// Transfer API
 //--------------------------------------------------------------------+
 
 // Submit a control transfer
-// true on success, false if there is on-going control transfer or incorrect parameters
-// Note: blocking if complete callback is NULL.
-//       xfer contents will be updated to reflect the result
-bool tuh_control_xfer(uint8_t daddr, tuh_xfer_t* xfer);
+// Note: blocking if complete callback is NULL, in this case xfer contents will be updated to reflect the result
+bool tuh_control_xfer(tuh_xfer_t* xfer);
 
 // Submit a bulk/interrupt transfer
-// true on success, false if there is on-going control transfer or incorrect parameters
+// xfer memory must exist until transfer is complete.
 // Note: blocking if complete callback is NULL.
-bool tuh_edpt_xfer(uint8_t daddr, tuh_xfer_t* xfer);
+bool tuh_edpt_xfer(tuh_xfer_t* xfer);
 
 // Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1

From 9ae0304b1ecd8d10f96a39c5c88a43d6b7c43681 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Mar 2022 18:04:25 +0700
Subject: [PATCH 0924/2085] move code around

---
 src/host/usbh.c | 1109 +++++++++++++++++++++++------------------------
 1 file changed, 553 insertions(+), 556 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 36774d3dc..8aa9c4a16 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -110,14 +110,7 @@ typedef struct {
   tu_edpt_state_t ep_status[CFG_TUH_ENDPOINT_MAX][2];
 
 #if CFG_TUH_API_EDPT_XFER
-//  struct
-//  {
-//    uint8_t* buffer;
-//    tuh_xfer_cb_t complete_cb;
-//    uintptr_t user_data;
-//    uint16_t buflen;
-//    volatile uint16_t actual_len;
-//  }ep_xfer[[]];
+  // ep_xfer[];
 #endif
 
 } usbh_device_t;
@@ -315,6 +308,558 @@ void osal_task_delay(uint32_t msec)
 }
 #endif
 
+//--------------------------------------------------------------------+
+// CLASS-USBD API (don't require to verify parameters)
+//--------------------------------------------------------------------+
+
+static void clear_device(usbh_device_t* dev)
+{
+  tu_memclr(dev, sizeof(usbh_device_t));
+  memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
+  memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
+}
+
+bool tuh_inited(void)
+{
+  return _usbh_initialized;
+}
+
+bool tuh_init(uint8_t rhport)
+{
+  // skip if already initialized
+  if (_usbh_initialized) return _usbh_initialized;
+
+  TU_LOG2("USBH init\r\n");
+  TU_LOG2_INT(sizeof(usbh_device_t));
+  TU_LOG2_INT(sizeof(hcd_event_t));
+  TU_LOG2_INT(sizeof(_ctrl_xfer));
+  TU_LOG2_INT(sizeof(tuh_xfer_t));
+
+  // Event queue
+  _usbh_q = osal_queue_create( &_usbh_qdef );
+  TU_ASSERT(_usbh_q != NULL);
+
+#if TUSB_OPT_MUTEX
+  // Mutex
+  _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
+  TU_ASSERT(_usbh_mutex);
+#endif
+
+  // Device
+  tu_memclr(&_dev0, sizeof(_dev0));
+  tu_memclr(_usbh_devices, sizeof(_usbh_devices));
+  tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer));
+
+  for(uint8_t i=0; i<TOTAL_DEVICES; i++)
+  {
+    clear_device(&_usbh_devices[i]);
+  }
+
+  // Class drivers
+  for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+  {
+    TU_LOG2("%s init\r\n", usbh_class_drivers[drv_id].name);
+    usbh_class_drivers[drv_id].init();
+  }
+
+  TU_ASSERT(hcd_init(rhport));
+  hcd_int_enable(rhport);
+
+  _usbh_initialized = true;
+  return true;
+}
+
+/* USB Host Driver task
+ * This top level thread manages all host controller event and delegates events to class-specific drivers.
+ * This should be called periodically within the mainloop or rtos thread.
+ *
+   @code
+    int main(void)
+    {
+      application_init();
+      tusb_init();
+
+      while(1) // the mainloop
+      {
+        application_code();
+        tuh_task(); // tinyusb host task
+      }
+    }
+    @endcode
+ */
+void tuh_task(void)
+{
+  // Skip if stack is not initialized
+  if ( !tusb_inited() ) return;
+
+  // Loop until there is no more events in the queue
+  while (1)
+  {
+    hcd_event_t event;
+    if ( !osal_queue_receive(_usbh_q, &event) ) return;
+
+    switch (event.event_id)
+    {
+      case HCD_EVENT_DEVICE_ATTACH:
+        // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
+        // one device before enumerating another one.
+        TU_LOG2("USBH DEVICE ATTACH\r\n");
+        enum_new_device(&event);
+      break;
+
+      case HCD_EVENT_DEVICE_REMOVE:
+        TU_LOG2("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
+        process_device_unplugged(event.rhport, event.connection.hub_addr, event.connection.hub_port);
+
+        #if CFG_TUH_HUB
+        // TODO remove
+        if ( event.connection.hub_addr != 0)
+        {
+          // done with hub, waiting for next data on status pipe
+          (void) hub_edpt_status_xfer( event.connection.hub_addr );
+        }
+        #endif
+      break;
+
+      case HCD_EVENT_XFER_COMPLETE:
+      {
+        uint8_t const ep_addr = event.xfer_complete.ep_addr;
+        uint8_t const epnum   = tu_edpt_number(ep_addr);
+        uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
+
+        TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
+
+        if (event.dev_addr == 0)
+        {
+          // device 0 only has control endpoint
+          TU_ASSERT(epnum == 0, );
+          usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+        }
+        else
+        {
+          usbh_device_t* dev = get_device(event.dev_addr);
+          TU_ASSERT(dev, );
+
+          dev->ep_status[epnum][ep_dir].busy    = 0;
+          dev->ep_status[epnum][ep_dir].claimed = 0;
+
+          if ( 0 == epnum )
+          {
+            usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+          }else
+          {
+            uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
+            TU_ASSERT(drv_id < USBH_CLASS_DRIVER_COUNT, );
+
+            TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
+            usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+          }
+        }
+      }
+      break;
+
+      case USBH_EVENT_FUNC_CALL:
+        if ( event.func_call.func ) event.func_call.func(event.func_call.param);
+      break;
+
+      default: break;
+    }
+  }
+}
+
+//--------------------------------------------------------------------+
+// Control transfer
+//--------------------------------------------------------------------+
+
+static void _control_blocking_complete_cb(tuh_xfer_t* xfer)
+{
+  // update result
+  *((xfer_result_t*) xfer->user_data) = xfer->result;
+}
+
+// TODO timeout_ms is not supported yet
+bool tuh_control_xfer (tuh_xfer_t* xfer)
+{
+  // EP0 with setup packet
+  TU_VERIFY(xfer->ep_addr == 0 && xfer->setup);
+
+  // pre-check to help reducing mutex lock
+  TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
+
+  uint8_t const daddr = xfer->daddr;
+
+  // TODO probably better to use semaphore as resource management than mutex
+  usbh_lock();
+
+  bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
+  if (is_idle)
+  {
+    _ctrl_xfer.stage       = CONTROL_STAGE_SETUP;
+    _ctrl_xfer.daddr       = daddr;
+    _ctrl_xfer.actual_len  = 0;
+
+    _ctrl_xfer.request     = (*xfer->setup);
+    _ctrl_xfer.buffer      = xfer->buffer;
+    _ctrl_xfer.complete_cb = xfer->complete_cb;
+    _ctrl_xfer.user_data   = xfer->user_data;
+  }
+
+  usbh_unlock();
+
+  TU_VERIFY(is_idle);
+  const uint8_t rhport = usbh_get_rhport(daddr);
+
+  TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request");
+  TU_LOG2_VAR(&xfer->setup);
+  TU_LOG2("\r\n");
+
+  if (xfer->complete_cb)
+  {
+    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
+  }else
+  {
+    // blocking if complete callback is not provided
+    // change callback to internal blocking, and result as user argument
+    volatile xfer_result_t result = XFER_RESULT_INVALID;
+
+    // use user_data to point to xfer_result_t
+    _ctrl_xfer.user_data   = (uintptr_t) &result;
+    _ctrl_xfer.complete_cb = _control_blocking_complete_cb;
+
+    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
+
+    while (result == XFER_RESULT_INVALID)
+    {
+      // only need to call task if not preempted RTOS
+      #if CFG_TUSB_OS == OPT_OS_NONE || CFG_TUSB_OS == OPT_OS_PICO
+      tuh_task();
+      #endif
+
+      // TODO probably some timeout to prevent hanged
+    }
+
+    // update transfer result
+    xfer->result     = result;
+    xfer->actual_len = _ctrl_xfer.actual_len;
+  }
+
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
+{
+  usbh_lock();
+  _ctrl_xfer.stage = stage;
+  usbh_unlock();
+}
+
+static void _xfer_complete(uint8_t daddr, xfer_result_t result)
+{
+  TU_LOG2("\r\n");
+
+  // duplicate xfer since user can execute control transfer within callback
+  tusb_control_request_t const request = _ctrl_xfer.request;
+  tuh_xfer_t xfer_temp =
+  {
+    .daddr       = daddr,
+    .ep_addr     = 0,
+    .result      = result,
+    .setup       = &request,
+    .actual_len  = (uint32_t) _ctrl_xfer.actual_len,
+    .buffer      = _ctrl_xfer.buffer,
+    .complete_cb = _ctrl_xfer.complete_cb,
+    .user_data   = _ctrl_xfer.user_data
+  };
+
+  usbh_lock();
+  _ctrl_xfer.stage = CONTROL_STAGE_IDLE;
+  usbh_unlock();
+
+  if (xfer_temp.complete_cb)
+  {
+    xfer_temp.complete_cb(&xfer_temp);
+  }
+}
+
+static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+{
+  (void) ep_addr;
+
+  const uint8_t rhport = usbh_get_rhport(dev_addr);
+  tusb_control_request_t const * request = &_ctrl_xfer.request;
+
+  if (XFER_RESULT_SUCCESS != result)
+  {
+    TU_LOG2("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED");
+
+    // terminate transfer if any stage failed
+    _xfer_complete(dev_addr, result);
+  }else
+  {
+    switch(_ctrl_xfer.stage)
+    {
+      case CONTROL_STAGE_SETUP:
+        if (request->wLength)
+        {
+          // DATA stage: initial data toggle is always 1
+          _set_control_xfer_stage(CONTROL_STAGE_DATA);
+          return hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
+        }
+        __attribute__((fallthrough));
+
+      case CONTROL_STAGE_DATA:
+        if (xferred_bytes)
+        {
+          TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
+          TU_LOG2_MEM(_ctrl_xfer.buffer, xferred_bytes, 2);
+        }
+
+        _ctrl_xfer.actual_len = xferred_bytes;
+
+        // ACK stage: toggle is always 1
+        _set_control_xfer_stage(CONTROL_STAGE_ACK);
+        hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
+      break;
+
+      case CONTROL_STAGE_ACK:
+        _xfer_complete(dev_addr, result);
+      break;
+
+      default: return false;
+    }
+  }
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool tuh_edpt_xfer(tuh_xfer_t* xfer)
+{
+  TU_VERIFY(xfer->daddr && xfer->ep_addr);
+
+
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// USBH API For Class Driver
+//--------------------------------------------------------------------+
+
+uint8_t usbh_get_rhport(uint8_t dev_addr)
+{
+  usbh_device_t* dev = get_device(dev_addr);
+  return dev ? dev->rhport : _dev0.rhport;
+}
+
+uint8_t* usbh_get_enum_buf(void)
+{
+  return _usbh_ctrl_buf;
+}
+
+void usbh_int_set(bool enabled)
+{
+  // TODO all host controller
+  if (enabled)
+  {
+    hcd_int_enable(TUH_OPT_RHPORT);
+  }else
+  {
+    hcd_int_disable(TUH_OPT_RHPORT);
+  }
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
+{
+  usbh_device_t* dev = get_device(dev_addr);
+
+  // addr0 only use tuh_control_xfer
+  TU_ASSERT(dev);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
+
+#if TUSB_OPT_MUTEX
+  return tu_edpt_claim(ep_state, _usbh_mutex);
+#else
+  return tu_edpt_claim(ep_state, NULL);
+#endif
+}
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
+{
+  // addr0 is always available
+  if (dev_addr == 0) return true;
+
+  usbh_device_t* dev        = get_device(dev_addr);
+  uint8_t const epnum       = tu_edpt_number(ep_addr);
+  uint8_t const dir         = tu_edpt_dir(ep_addr);
+  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
+
+#if TUSB_OPT_MUTEX
+  return tu_edpt_release(ep_state, _usbh_mutex);
+#else
+  return tu_edpt_release(ep_state, NULL);
+#endif
+}
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  usbh_device_t* dev = get_device(dev_addr);
+  TU_VERIFY(dev);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
+
+  // Attempt to transfer on a busy endpoint, sound like an race condition !
+  TU_ASSERT(dev->ep_status[epnum][dir].busy == 0);
+
+  // Set busy first since the actual transfer can be complete before hcd_edpt_xfer()
+  // could return and USBH task can preempt and clear the busy
+  dev->ep_status[epnum][dir].busy = true;
+
+  if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
+  {
+    TU_LOG2("OK\r\n");
+    return true;
+  }else
+  {
+    // HCD error, mark endpoint as ready to allow next transfer
+    dev->ep_status[epnum][dir].busy = false;
+    dev->ep_status[epnum][dir].claimed = 0;
+    TU_LOG1("failed\r\n");
+    TU_BREAKPOINT();
+    return false;
+  }
+}
+
+static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
+{
+  TU_LOG2("Open EP0 with Size = %u (addr = %u)\r\n", max_packet_size, dev_addr);
+
+  tusb_desc_endpoint_t ep0_desc =
+  {
+    .bLength          = sizeof(tusb_desc_endpoint_t),
+    .bDescriptorType  = TUSB_DESC_ENDPOINT,
+    .bEndpointAddress = 0,
+    .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
+    .wMaxPacketSize   = max_packet_size,
+    .bInterval        = 0
+  };
+
+  return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc);
+}
+
+bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
+{
+  TU_ASSERT( tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr)) );
+  return hcd_edpt_open(rhport, dev_addr, desc_ep);
+}
+
+bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  usbh_device_t* dev = get_device(dev_addr);
+  TU_VERIFY(dev);
+
+  return dev->ep_status[epnum][dir].busy;
+}
+
+//--------------------------------------------------------------------+
+// HCD Event Handler
+//--------------------------------------------------------------------+
+
+void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info)
+{
+  usbh_device_t const* dev = get_device(dev_addr);
+
+  if (dev)
+  {
+    devtree_info->rhport   = dev->rhport;
+    devtree_info->hub_addr = dev->hub_addr;
+    devtree_info->hub_port = dev->hub_port;
+    devtree_info->speed    = dev->speed;
+  }else
+  {
+    devtree_info->rhport   = _dev0.rhport;
+    devtree_info->hub_addr = _dev0.hub_addr;
+    devtree_info->hub_port = _dev0.hub_port;
+    devtree_info->speed    = _dev0.speed;
+  }
+}
+
+void hcd_event_handler(hcd_event_t const* event, bool in_isr)
+{
+  switch (event->event_id)
+  {
+    default:
+      osal_queue_send(_usbh_q, event, in_isr);
+    break;
+  }
+}
+
+void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
+{
+  hcd_event_t event =
+  {
+    .rhport   = 0, // TODO correct rhport
+    .event_id = HCD_EVENT_XFER_COMPLETE,
+    .dev_addr = dev_addr,
+    .xfer_complete =
+    {
+      .ep_addr = ep_addr,
+      .result  = result,
+      .len     = xferred_bytes
+    }
+  };
+
+  hcd_event_handler(&event, in_isr);
+}
+
+void hcd_event_device_attach(uint8_t rhport, bool in_isr)
+{
+  hcd_event_t event =
+  {
+    .rhport   = rhport,
+    .event_id = HCD_EVENT_DEVICE_ATTACH
+  };
+
+  event.connection.hub_addr = 0;
+  event.connection.hub_port = 0;
+
+  hcd_event_handler(&event, in_isr);
+}
+
+void hcd_event_device_remove(uint8_t hostid, bool in_isr)
+{
+  hcd_event_t event =
+  {
+    .rhport   = hostid,
+    .event_id = HCD_EVENT_DEVICE_REMOVE
+  };
+
+  event.connection.hub_addr = 0;
+  event.connection.hub_port = 0;
+
+  hcd_event_handler(&event, in_isr);
+}
+
 //--------------------------------------------------------------------+
 // Descriptors Async
 //--------------------------------------------------------------------+
@@ -535,554 +1080,6 @@ uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_i
   _CONTROL_SYNC_API(tuh_descriptor_get_serial_string, daddr, language_id, buffer, len);
 }
 
-//--------------------------------------------------------------------+
-// CLASS-USBD API (don't require to verify parameters)
-//--------------------------------------------------------------------+
-
-static void clear_device(usbh_device_t* dev)
-{
-  tu_memclr(dev, sizeof(usbh_device_t));
-  memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
-  memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
-}
-
-bool tuh_inited(void)
-{
-  return _usbh_initialized;
-}
-
-bool tuh_init(uint8_t rhport)
-{
-  // skip if already initialized
-  if (_usbh_initialized) return _usbh_initialized;
-
-  TU_LOG2("USBH init\r\n");
-  TU_LOG2_INT(sizeof(usbh_device_t));
-  TU_LOG2_INT(sizeof(hcd_event_t));
-  TU_LOG2_INT(sizeof(_ctrl_xfer));
-  TU_LOG2_INT(sizeof(tuh_xfer_t));
-
-  // Event queue
-  _usbh_q = osal_queue_create( &_usbh_qdef );
-  TU_ASSERT(_usbh_q != NULL);
-
-#if TUSB_OPT_MUTEX
-  // Mutex
-  _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
-  TU_ASSERT(_usbh_mutex);
-#endif
-
-  // Device
-  tu_memclr(&_dev0, sizeof(_dev0));
-  tu_memclr(_usbh_devices, sizeof(_usbh_devices));
-  tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer));
-
-  for(uint8_t i=0; i<TOTAL_DEVICES; i++)
-  {
-    clear_device(&_usbh_devices[i]);
-  }
-
-  // Class drivers
-  for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
-  {
-    TU_LOG2("%s init\r\n", usbh_class_drivers[drv_id].name);
-    usbh_class_drivers[drv_id].init();
-  }
-
-  TU_ASSERT(hcd_init(rhport));
-  hcd_int_enable(rhport);
-
-  _usbh_initialized = true;
-  return true;
-}
-
-/* USB Host Driver task
- * This top level thread manages all host controller event and delegates events to class-specific drivers.
- * This should be called periodically within the mainloop or rtos thread.
- *
-   @code
-    int main(void)
-    {
-      application_init();
-      tusb_init();
-
-      while(1) // the mainloop
-      {
-        application_code();
-        tuh_task(); // tinyusb host task
-      }
-    }
-    @endcode
- */
-void tuh_task(void)
-{
-  // Skip if stack is not initialized
-  if ( !tusb_inited() ) return;
-
-  // Loop until there is no more events in the queue
-  while (1)
-  {
-    hcd_event_t event;
-    if ( !osal_queue_receive(_usbh_q, &event) ) return;
-
-    switch (event.event_id)
-    {
-      case HCD_EVENT_DEVICE_ATTACH:
-        // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
-        // one device before enumerating another one.
-        TU_LOG2("USBH DEVICE ATTACH\r\n");
-        enum_new_device(&event);
-      break;
-
-      case HCD_EVENT_DEVICE_REMOVE:
-        TU_LOG2("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
-        process_device_unplugged(event.rhport, event.connection.hub_addr, event.connection.hub_port);
-
-        #if CFG_TUH_HUB
-        // TODO remove
-        if ( event.connection.hub_addr != 0)
-        {
-          // done with hub, waiting for next data on status pipe
-          (void) hub_edpt_status_xfer( event.connection.hub_addr );
-        }
-        #endif
-      break;
-
-      case HCD_EVENT_XFER_COMPLETE:
-      {
-        uint8_t const ep_addr = event.xfer_complete.ep_addr;
-        uint8_t const epnum   = tu_edpt_number(ep_addr);
-        uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
-
-        TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
-
-        if (event.dev_addr == 0)
-        {
-          // device 0 only has control endpoint
-          TU_ASSERT(epnum == 0, );
-          usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
-        }
-        else
-        {
-          usbh_device_t* dev = get_device(event.dev_addr);
-          TU_ASSERT(dev, );
-
-          dev->ep_status[epnum][ep_dir].busy    = 0;
-          dev->ep_status[epnum][ep_dir].claimed = 0;
-
-          if ( 0 == epnum )
-          {
-            usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
-          }else
-          {
-            uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
-            TU_ASSERT(drv_id < USBH_CLASS_DRIVER_COUNT, );
-
-            TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
-            usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
-          }
-        }
-      }
-      break;
-
-      case USBH_EVENT_FUNC_CALL:
-        if ( event.func_call.func ) event.func_call.func(event.func_call.param);
-      break;
-
-      default: break;
-    }
-  }
-}
-
-//--------------------------------------------------------------------+
-// USBH API For Class Driver
-//--------------------------------------------------------------------+
-
-uint8_t usbh_get_rhport(uint8_t dev_addr)
-{
-  usbh_device_t* dev = get_device(dev_addr);
-  return dev ? dev->rhport : _dev0.rhport;
-}
-
-uint8_t* usbh_get_enum_buf(void)
-{
-  return _usbh_ctrl_buf;
-}
-
-void usbh_int_set(bool enabled)
-{
-  // TODO all host controller
-  if (enabled)
-  {
-    hcd_int_enable(TUH_OPT_RHPORT);
-  }else
-  {
-    hcd_int_disable(TUH_OPT_RHPORT);
-  }
-}
-
-//--------------------------------------------------------------------+
-// HCD Event Handler
-//--------------------------------------------------------------------+
-
-void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info)
-{
-  usbh_device_t const* dev = get_device(dev_addr);
-
-  if (dev)
-  {
-    devtree_info->rhport   = dev->rhport;
-    devtree_info->hub_addr = dev->hub_addr;
-    devtree_info->hub_port = dev->hub_port;
-    devtree_info->speed    = dev->speed;
-  }else
-  {
-    devtree_info->rhport   = _dev0.rhport;
-    devtree_info->hub_addr = _dev0.hub_addr;
-    devtree_info->hub_port = _dev0.hub_port;
-    devtree_info->speed    = _dev0.speed;
-  }
-}
-
-void hcd_event_handler(hcd_event_t const* event, bool in_isr)
-{
-  switch (event->event_id)
-  {
-    default:
-      osal_queue_send(_usbh_q, event, in_isr);
-    break;
-  }
-}
-
-void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
-{
-  hcd_event_t event =
-  {
-    .rhport   = 0, // TODO correct rhport
-    .event_id = HCD_EVENT_XFER_COMPLETE,
-    .dev_addr = dev_addr,
-    .xfer_complete =
-    {
-      .ep_addr = ep_addr,
-      .result  = result,
-      .len     = xferred_bytes
-    }
-  };
-
-  hcd_event_handler(&event, in_isr);
-}
-
-void hcd_event_device_attach(uint8_t rhport, bool in_isr)
-{
-  hcd_event_t event =
-  {
-    .rhport   = rhport,
-    .event_id = HCD_EVENT_DEVICE_ATTACH
-  };
-
-  event.connection.hub_addr = 0;
-  event.connection.hub_port = 0;
-
-  hcd_event_handler(&event, in_isr);
-}
-
-void hcd_event_device_remove(uint8_t hostid, bool in_isr)
-{
-  hcd_event_t event =
-  {
-    .rhport   = hostid,
-    .event_id = HCD_EVENT_DEVICE_REMOVE
-  };
-
-  event.connection.hub_addr = 0;
-  event.connection.hub_port = 0;
-
-  hcd_event_handler(&event, in_isr);
-}
-
-//--------------------------------------------------------------------+
-// Endpoint API
-//--------------------------------------------------------------------+
-
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
-{
-  usbh_device_t* dev        = get_device(dev_addr);
-
-  // addr0 only use tuh_control_xfer
-  TU_ASSERT(dev);
-
-  uint8_t const epnum       = tu_edpt_number(ep_addr);
-  uint8_t const dir         = tu_edpt_dir(ep_addr);
-  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
-
-#if TUSB_OPT_MUTEX
-  return tu_edpt_claim(ep_state, _usbh_mutex);
-#else
-  return tu_edpt_claim(ep_state, NULL);
-#endif
-}
-
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
-{
-  // addr0 is always available
-  if (dev_addr == 0) return true;
-
-  usbh_device_t* dev        = get_device(dev_addr);
-  uint8_t const epnum       = tu_edpt_number(ep_addr);
-  uint8_t const dir         = tu_edpt_dir(ep_addr);
-  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
-
-#if TUSB_OPT_MUTEX
-  return tu_edpt_release(ep_state, _usbh_mutex);
-#else
-  return tu_edpt_release(ep_state, NULL);
-#endif
-}
-
-// TODO has some duplication code with device, refactor later
-bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  usbh_device_t* dev = get_device(dev_addr);
-  TU_VERIFY(dev);
-
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
-
-  // Attempt to transfer on a busy endpoint, sound like an race condition !
-  TU_ASSERT(dev->ep_status[epnum][dir].busy == 0);
-
-  // Set busy first since the actual transfer can be complete before hcd_edpt_xfer()
-  // could return and USBH task can preempt and clear the busy
-  dev->ep_status[epnum][dir].busy = true;
-
-  if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
-  {
-    TU_LOG2("OK\r\n");
-    return true;
-  }else
-  {
-    // HCD error, mark endpoint as ready to allow next transfer
-    dev->ep_status[epnum][dir].busy = false;
-    dev->ep_status[epnum][dir].claimed = 0;
-    TU_LOG1("failed\r\n");
-    TU_BREAKPOINT();
-    return false;
-  }
-}
-
-static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
-{
-  TU_LOG2("Open EP0 with Size = %u (addr = %u)\r\n", max_packet_size, dev_addr);
-
-  tusb_desc_endpoint_t ep0_desc =
-  {
-    .bLength          = sizeof(tusb_desc_endpoint_t),
-    .bDescriptorType  = TUSB_DESC_ENDPOINT,
-    .bEndpointAddress = 0,
-    .bmAttributes     = { .xfer = TUSB_XFER_CONTROL },
-    .wMaxPacketSize   = max_packet_size,
-    .bInterval        = 0
-  };
-
-  return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc);
-}
-
-bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
-{
-  TU_ASSERT( tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr)) );
-  return hcd_edpt_open(rhport, dev_addr, desc_ep);
-}
-
-bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  usbh_device_t* dev = get_device(dev_addr);
-  TU_VERIFY(dev);
-
-  return dev->ep_status[epnum][dir].busy;
-}
-
-//--------------------------------------------------------------------+
-// Control transfer
-//--------------------------------------------------------------------+
-
-static void _control_blocking_complete_cb(tuh_xfer_t* xfer)
-{
-  // update result
-  *((xfer_result_t*) xfer->user_data) = xfer->result;
-}
-
-// TODO timeout_ms is not supported yet
-bool tuh_control_xfer (tuh_xfer_t* xfer)
-{
-  // EP0 with setup packet
-  TU_VERIFY(xfer->ep_addr == 0 && xfer->setup);
-
-  // pre-check to help reducing mutex lock
-  TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
-
-  uint8_t const daddr = xfer->daddr;
-
-  // TODO probably better to use semaphore as resource management than mutex
-  usbh_lock();
-
-  bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
-  if (is_idle)
-  {
-    _ctrl_xfer.stage       = CONTROL_STAGE_SETUP;
-    _ctrl_xfer.daddr       = daddr;
-    _ctrl_xfer.actual_len  = 0;
-
-    _ctrl_xfer.request     = (*xfer->setup);
-    _ctrl_xfer.buffer      = xfer->buffer;
-    _ctrl_xfer.complete_cb = xfer->complete_cb;
-    _ctrl_xfer.user_data   = xfer->user_data;
-  }
-
-  usbh_unlock();
-
-  TU_VERIFY(is_idle);
-  const uint8_t rhport = usbh_get_rhport(daddr);
-
-  TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request");
-  TU_LOG2_VAR(&xfer->setup);
-  TU_LOG2("\r\n");
-
-  if (xfer->complete_cb)
-  {
-    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
-  }else
-  {
-    // blocking if complete callback is not provided
-    // change callback to internal blocking, and result as user argument
-    volatile xfer_result_t result = XFER_RESULT_INVALID;
-
-    // use user_data to point to xfer_result_t
-    _ctrl_xfer.user_data   = (uintptr_t) &result;
-    _ctrl_xfer.complete_cb = _control_blocking_complete_cb;
-
-    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
-
-    while (result == XFER_RESULT_INVALID)
-    {
-      // only need to call task if not preempted RTOS
-      #if CFG_TUSB_OS == OPT_OS_NONE || CFG_TUSB_OS == OPT_OS_PICO
-      tuh_task();
-      #endif
-
-      // TODO probably some timeout to prevent hanged
-    }
-
-    // update transfer result
-    xfer->result     = result;
-    xfer->actual_len = _ctrl_xfer.actual_len;
-  }
-
-  return true;
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
-{
-  usbh_lock();
-  _ctrl_xfer.stage = stage;
-  usbh_unlock();
-}
-
-static void _xfer_complete(uint8_t daddr, xfer_result_t result)
-{
-  TU_LOG2("\r\n");
-
-  // duplicate xfer since user can execute control transfer within callback
-  tusb_control_request_t const request = _ctrl_xfer.request;
-  tuh_xfer_t xfer_temp =
-  {
-    .daddr       = daddr,
-    .ep_addr     = 0,
-    .result      = result,
-    .setup       = &request,
-    .actual_len  = (uint32_t) _ctrl_xfer.actual_len,
-    .buffer      = _ctrl_xfer.buffer,
-    .complete_cb = _ctrl_xfer.complete_cb,
-    .user_data   = _ctrl_xfer.user_data
-  };
-
-  usbh_lock();
-  _ctrl_xfer.stage = CONTROL_STAGE_IDLE;
-  usbh_unlock();
-
-  if (xfer_temp.complete_cb)
-  {
-    xfer_temp.complete_cb(&xfer_temp);
-  }
-}
-
-static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
-  (void) ep_addr;
-
-  const uint8_t rhport = usbh_get_rhport(dev_addr);
-  tusb_control_request_t const * request = &_ctrl_xfer.request;
-
-  if (XFER_RESULT_SUCCESS != result)
-  {
-    TU_LOG2("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED");
-
-    // terminate transfer if any stage failed
-    _xfer_complete(dev_addr, result);
-  }else
-  {
-    switch(_ctrl_xfer.stage)
-    {
-      case CONTROL_STAGE_SETUP:
-        if (request->wLength)
-        {
-          // DATA stage: initial data toggle is always 1
-          _set_control_xfer_stage(CONTROL_STAGE_DATA);
-          return hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
-        }
-        __attribute__((fallthrough));
-
-      case CONTROL_STAGE_DATA:
-        if (xferred_bytes)
-        {
-          TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
-          TU_LOG2_MEM(_ctrl_xfer.buffer, xferred_bytes, 2);
-        }
-
-        _ctrl_xfer.actual_len = xferred_bytes;
-
-        // ACK stage: toggle is always 1
-        _set_control_xfer_stage(CONTROL_STAGE_ACK);
-        hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
-      break;
-
-      case CONTROL_STAGE_ACK:
-        _xfer_complete(dev_addr, result);
-      break;
-
-      default: return false;
-    }
-  }
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-//
-//--------------------------------------------------------------------+
-
-bool tuh_edpt_xfer(tuh_xfer_t* xfer)
-{
-  (void) xfer;
-  return true;
-}
-
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+

From ba1185bf28331da718cca38e6598361889fce54d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Mar 2022 22:22:21 +0700
Subject: [PATCH 0925/2085] implement tuh_edpt_xfer() for non-control

---
 examples/host/bare_api/src/main.c | 193 ++++++++++++++++--------------
 src/class/hid/hid_host.c          |   8 +-
 src/host/usbh.c                   | 104 +++++++++++-----
 src/host/usbh.h                   |  10 +-
 src/host/usbh_classdriver.h       |  12 +-
 5 files changed, 201 insertions(+), 126 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index e2e0f4ff3..06ae03ecb 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -40,6 +40,8 @@
 //--------------------------------------------------------------------+
 void led_blinking_task(void);
 
+static void print_utf16(uint16_t *temp_buf, size_t buf_len);
+
 /*------------- MAIN -------------*/
 int main(void)
 {
@@ -65,10 +67,108 @@ int main(void)
 // English
 #define LANGUAGE_ID 0x0409
 
-//uint8_t usb_buf[256] TU_ATTR_ALIGNED(4);
-TU_ATTR_ALIGNED(4)
 tusb_desc_device_t desc_device;
 
+//void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
+//{
+//  uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
+//  uint8_t const* p_desc   = tu_desc_next(desc_cfg);
+//}
+
+void print_device_descriptor(tuh_xfer_t* xfer)
+{
+  if ( XFER_RESULT_SUCCESS != xfer->result )
+  {
+    printf("Failed to get device descriptor\r\n");
+    return;
+  }
+
+  uint8_t const daddr = xfer->daddr;
+
+  printf("Device %u: ID %04x:%04x\r\n", daddr, desc_device.idVendor, desc_device.idProduct);
+  printf("Device Descriptor:\r\n");
+  printf("  bLength             %u\r\n"     , desc_device.bLength);
+  printf("  bDescriptorType     %u\r\n"     , desc_device.bDescriptorType);
+  printf("  bcdUSB              %04x\r\n"   , desc_device.bcdUSB);
+  printf("  bDeviceClass        %u\r\n"     , desc_device.bDeviceClass);
+  printf("  bDeviceSubClass     %u\r\n"     , desc_device.bDeviceSubClass);
+  printf("  bDeviceProtocol     %u\r\n"     , desc_device.bDeviceProtocol);
+  printf("  bMaxPacketSize0     %u\r\n"     , desc_device.bMaxPacketSize0);
+  printf("  idVendor            0x%04x\r\n" , desc_device.idVendor);
+  printf("  idProduct           0x%04x\r\n" , desc_device.idProduct);
+  printf("  bcdDevice           %04x\r\n"   , desc_device.bcdDevice);
+
+  // Get String descriptor using Sync API
+  uint16_t temp_buf[128];
+
+  printf("  iManufacturer       %u     "     , desc_device.iManufacturer);
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf)) )
+  {
+    print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf));
+  }
+  printf("\r\n");
+
+  printf("  iProduct            %u     "     , desc_device.iProduct);
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf)))
+  {
+    print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf));
+  }
+  printf("\r\n");
+
+  printf("  iSerialNumber       %u     "     , desc_device.iSerialNumber);
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf)))
+  {
+    print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf));
+  }
+  printf("\r\n");
+
+  printf("  bNumConfigurations  %u\r\n"     , desc_device.bNumConfigurations);
+
+  // Get configuration descriptor with sync API
+//  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf)) )
+//  {
+//    parse_config_descriptor(daddr, (tusb_desc_configuration_t*) temp_buf);
+//  }
+}
+
+// Invoked when device is mounted (configured)
+void tuh_mount_cb (uint8_t daddr)
+{
+  printf("Device attached, address = %d\r\n", daddr);
+
+  // Get Device Descriptor sync API
+  // TODO: invoking control trannsfer now has issue with mounting hub with multiple devices attached, fix later
+  tuh_descriptor_get_device(daddr, &desc_device, 18, print_device_descriptor, 0);
+}
+
+/// Invoked when device is unmounted (bus reset/unplugged)
+void tuh_umount_cb(uint8_t daddr)
+{
+  printf("Device removed, address = %d\r\n", daddr);
+}
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  const uint32_t interval_ms = 1000;
+  static uint32_t start_ms = 0;
+
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  start_ms += interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
+
+//--------------------------------------------------------------------+
+// Helper
+//--------------------------------------------------------------------+
+
 static void _convert_utf16le_to_utf8(const uint16_t *utf16, size_t utf16_len, uint8_t *utf8, size_t utf8_len) {
     // TODO: Check for runover.
     (void)utf8_len;
@@ -108,94 +208,11 @@ static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
     return total_bytes;
 }
 
-static void utf16_to_utf8(uint16_t *temp_buf, size_t buf_len) {
+static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
     size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
     size_t utf8_len = _count_utf8_bytes(temp_buf + 1, utf16_len);
     _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
     ((uint8_t*) temp_buf)[utf8_len] = '\0';
-}
-
-void print_device_descriptor(tuh_xfer_t* xfer)
-{
-  if ( XFER_RESULT_SUCCESS != xfer->result )
-  {
-    printf("Failed to get device descriptor\r\n");
-    return;
-  }
-
-  uint8_t const daddr = xfer->daddr;
-
-  printf("Device %u: ID %04x:%04x\r\n", daddr, desc_device.idVendor, desc_device.idProduct);
-  printf("Device Descriptor:\r\n");
-  printf("  bLength             %u\r\n"     , desc_device.bLength);
-  printf("  bDescriptorType     %u\r\n"     , desc_device.bDescriptorType);
-  printf("  bcdUSB              %04x\r\n"   , desc_device.bcdUSB);
-  printf("  bDeviceClass        %u\r\n"     , desc_device.bDeviceClass);
-  printf("  bDeviceSubClass     %u\r\n"     , desc_device.bDeviceSubClass);
-  printf("  bDeviceProtocol     %u\r\n"     , desc_device.bDeviceProtocol);
-  printf("  bMaxPacketSize0     %u\r\n"     , desc_device.bMaxPacketSize0);
-  printf("  idVendor            0x%04x\r\n" , desc_device.idVendor);
-  printf("  idProduct           0x%04x\r\n" , desc_device.idProduct);
-  printf("  bcdDevice           %04x\r\n"   , desc_device.bcdDevice);
-
-  uint16_t temp_buf[128];
-
-  printf("  iManufacturer       %u     "     , desc_device.iManufacturer);
-  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf)) )
-  {
-    utf16_to_utf8(temp_buf, TU_ARRAY_SIZE(temp_buf));
-    printf((const char*) temp_buf);
-  }
-  printf("\r\n");
-
-  printf("  iProduct            %u     "     , desc_device.iProduct);
-  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf)))
-  {
-    utf16_to_utf8(temp_buf, TU_ARRAY_SIZE(temp_buf));
-    printf((const char*) temp_buf);
-  }
-  printf("\r\n");
-
-  printf("  iSerialNumber       %u     "     , desc_device.iSerialNumber);
-  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, TU_ARRAY_SIZE(temp_buf)))
-  {
-    utf16_to_utf8(temp_buf, TU_ARRAY_SIZE(temp_buf));
-    printf((const char*) temp_buf);
-  }
-  printf("\r\n");
-
-  printf("  bNumConfigurations  %u\r\n"     , desc_device.bNumConfigurations);
-}
-
-// Invoked when device is mounted (configured)
-void tuh_mount_cb (uint8_t daddr)
-{
-  printf("Device attached, address = %d\r\n", daddr);
-
-  // Get Device Descriptor using asynchronous API
-  tuh_descriptor_get_device(daddr, &desc_device, 18, print_device_descriptor, 0);
-}
-
-/// Invoked when device is unmounted (bus reset/unplugged)
-void tuh_umount_cb(uint8_t daddr)
-{
-  printf("Device removed, address = %d\r\n", daddr);
-}
-
-//--------------------------------------------------------------------+
-// Blinking Task
-//--------------------------------------------------------------------+
-void led_blinking_task(void)
-{
-  const uint32_t interval_ms = 1000;
-  static uint32_t start_ms = 0;
-
-  static bool led_state = false;
-
-  // Blink every interval ms
-  if ( board_millis() - start_ms < interval_ms) return; // not enough time
-  start_ms += interval_ms;
-
-  board_led_write(led_state);
-  led_state = 1 - led_state; // toggle
+
+    printf((char*)temp_buf);
 }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index fa99b37fe..2bdd1db79 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -256,7 +256,13 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance)
   // claim endpoint
   TU_VERIFY( usbh_edpt_claim(dev_addr, hid_itf->ep_in) );
 
-  return usbh_edpt_xfer(dev_addr, hid_itf->ep_in, hid_itf->epin_buf, hid_itf->epin_size);
+  if ( !usbh_edpt_xfer(dev_addr, hid_itf->ep_in, hid_itf->epin_buf, hid_itf->epin_size) )
+  {
+    usbh_edpt_claim(dev_addr, hid_itf->ep_in);
+    return false;
+  }
+
+  return true;
 }
 
 //bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t instance)
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 8aa9c4a16..497badfde 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -82,8 +82,7 @@ typedef struct {
   uint8_t speed;
 
   // Device State
-  struct TU_ATTR_PACKED
-  {
+  struct TU_ATTR_PACKED {
     volatile uint8_t connected  : 1;
     volatile uint8_t addressed  : 1;
     volatile uint8_t configured : 1;
@@ -110,7 +109,11 @@ typedef struct {
   tu_edpt_state_t ep_status[CFG_TUH_ENDPOINT_MAX][2];
 
 #if CFG_TUH_API_EDPT_XFER
-  // ep_xfer[];
+  // TODO array can be CFG_TUH_ENDPOINT_MAX-1
+  struct {
+    tuh_xfer_cb_t complete_cb;
+    uintptr_t user_data;
+  }ep_callback[CFG_TUH_ENDPOINT_MAX][2];
 #endif
 
 } usbh_device_t;
@@ -227,6 +230,8 @@ TU_ATTR_ALWAYS_INLINE static inline void usbh_unlock(void)
 
 #else
 
+#define _usbh_mutex   NULL
+
 #define usbh_lock()
 #define usbh_unlock()
 
@@ -449,10 +454,38 @@ void tuh_task(void)
           }else
           {
             uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
-            TU_ASSERT(drv_id < USBH_CLASS_DRIVER_COUNT, );
+            if(drv_id < USBH_CLASS_DRIVER_COUNT)
+            {
+              TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
+              usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+            }
+            else
+            {
+#if CFG_TUH_API_EDPT_XFER
+              tuh_xfer_cb_t complete_cb = dev->ep_callback[epnum][ep_dir].complete_cb;
+              if ( complete_cb )
+              {
+                tuh_xfer_t xfer =
+                {
+                  .daddr       = event.dev_addr,
+                  .ep_addr     = ep_addr,
+                  .result      = event.xfer_complete.result,
+                  .actual_len  = event.xfer_complete.len,
+                  .buflen      = 0,    // not available
+                  .buffer      = NULL, // not available
+                  .complete_cb = complete_cb,
+                  .user_data   = dev->ep_callback[epnum][ep_dir].user_data
+                };
 
-            TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
-            usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+                complete_cb(&xfer);
+              }else
+#endif
+              {
+                // no driver/callback responsible for this transfer
+                TU_ASSERT(false, );
+              }
+
+            }
           }
         }
       }
@@ -638,9 +671,18 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 
 bool tuh_edpt_xfer(tuh_xfer_t* xfer)
 {
-  TU_VERIFY(xfer->daddr && xfer->ep_addr);
+  uint8_t const daddr   = xfer->daddr;
+  uint8_t const ep_addr = xfer->ep_addr;
 
+  TU_VERIFY(daddr && ep_addr);
 
+  TU_VERIFY(usbh_edpt_claim(daddr, ep_addr));
+
+  if ( !usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, xfer->buflen, xfer->complete_cb, xfer->user_data) )
+  {
+    usbh_edpt_release(daddr, ep_addr);
+    return false;
+  }
 
   return true;
 }
@@ -687,50 +729,50 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
-
-#if TUSB_OPT_MUTEX
-  return tu_edpt_claim(ep_state, _usbh_mutex);
-#else
-  return tu_edpt_claim(ep_state, NULL);
-#endif
+  return tu_edpt_claim(&dev->ep_status[epnum][dir], _usbh_mutex);
 }
 
 // TODO has some duplication code with device, refactor later
 bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
 {
-  // addr0 is always available
-  if (dev_addr == 0) return true;
+  usbh_device_t* dev = get_device(dev_addr);
 
-  usbh_device_t* dev        = get_device(dev_addr);
-  uint8_t const epnum       = tu_edpt_number(ep_addr);
-  uint8_t const dir         = tu_edpt_dir(ep_addr);
-  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
+  // addr0 only use tuh_control_xfer
+  TU_ASSERT(dev);
 
-#if TUSB_OPT_MUTEX
-  return tu_edpt_release(ep_state, _usbh_mutex);
-#else
-  return tu_edpt_release(ep_state, NULL);
-#endif
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  return tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex);
 }
 
 // TODO has some duplication code with device, refactor later
-bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes,
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
+  (void) complete_cb;
+  (void) user_data;
+
   usbh_device_t* dev = get_device(dev_addr);
   TU_VERIFY(dev);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
+  tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
   TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
-  TU_ASSERT(dev->ep_status[epnum][dir].busy == 0);
+  TU_ASSERT(ep_state->busy == 0);
 
   // Set busy first since the actual transfer can be complete before hcd_edpt_xfer()
   // could return and USBH task can preempt and clear the busy
-  dev->ep_status[epnum][dir].busy = true;
+  ep_state->busy = 1;
+
+#if CFG_TUH_API_EDPT_XFER
+  dev->ep_callback[epnum][dir].complete_cb = complete_cb;
+  dev->ep_callback[epnum][dir].user_data   = user_data;
+#endif
 
   if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
   {
@@ -739,9 +781,9 @@ bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_
   }else
   {
     // HCD error, mark endpoint as ready to allow next transfer
-    dev->ep_status[epnum][dir].busy = false;
-    dev->ep_status[epnum][dir].claimed = 0;
-    TU_LOG1("failed\r\n");
+    ep_state->busy    = 0;
+    ep_state->claimed = 0;
+    TU_LOG1("Failed\r\n");
     TU_BREAKPOINT();
     return false;
   }
diff --git a/src/host/usbh.h b/src/host/usbh.h
index f79c5cdc8..772c4cfd6 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -44,25 +44,27 @@ typedef struct tuh_xfer_s tuh_xfer_t;
 
 typedef void (*tuh_xfer_cb_t)(tuh_xfer_t* xfer);
 
+// Note: layout and order of this will be changed in near future
+// it is advised to initialize it using member name
 struct tuh_xfer_s
 {
   uint8_t daddr;
   uint8_t ep_addr;
 
   xfer_result_t result;
-  uint32_t actual_len; // excluding setup packet
+  uint32_t actual_len;      // excluding setup packet
 
   union
   {
     tusb_control_request_t const* setup; // setup packet pointer if control transfer
-    uint32_t buflen;                     // length if not control transfer
+    uint32_t buflen;        // expected length if not control transfer (not available in callback)
   };
 
-  uint8_t* buffer;
+  uint8_t* buffer;           // not available in callback if not control transfer
   tuh_xfer_cb_t complete_cb;
   uintptr_t user_data;
 
-  uint32_t timeout_ms; // place holder, not supported yet
+  // uint32_t timeout_ms;    // place holder, not supported yet
 };
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index 0435eae70..30e97535d 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -66,8 +66,16 @@ void usbh_int_set(bool enabled);
 // Open an endpoint
 bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
 
-// Submit a usb transfer
-bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
+// Submit a usb transfer with callback support, require CFG_TUH_API_EDPT_XFER
+bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes,
+                                  tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+TU_ATTR_ALWAYS_INLINE
+static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  return usbh_edpt_xfer_with_callback(dev_addr, ep_addr, buffer, total_bytes, NULL, 0);
+}
+
 
 // Claim an endpoint before submitting a transfer.
 // If caller does not make any transfer, it must release endpoint for others.

From 4795cca04ac60d58fbc78d554cd7af7039cd310a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Mar 2022 00:43:31 +0700
Subject: [PATCH 0926/2085] add parse config descriptor to example

move usbh_edpt_open() to public API, remove rhport from its signature
---
 examples/host/bare_api/src/main.c | 154 +++++++++++++++++++++++++-----
 src/class/cdc/cdc_host.c          |   5 +-
 src/class/hid/hid.h               |   2 +-
 src/class/hid/hid_host.c          |   3 +-
 src/class/msc/msc_host.c          |   3 +-
 src/host/hub.c                    |   4 +-
 src/host/usbh.c                   |  11 ++-
 src/host/usbh.h                   |  14 ++-
 src/host/usbh_classdriver.h       |   3 -
 src/portable/ehci/ehci.c          |  25 ++++-
 src/tusb.h                        |   2 +
 11 files changed, 180 insertions(+), 46 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 06ae03ecb..3b23dd43b 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -35,12 +35,19 @@
 #include "bsp/board.h"
 #include "tusb.h"
 
+// English
+#define LANGUAGE_ID 0x0409
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
 void led_blinking_task(void);
 
 static void print_utf16(uint16_t *temp_buf, size_t buf_len);
+void print_device_descriptor(tuh_xfer_t* xfer);
+void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
+
+tusb_desc_device_t desc_device;
 
 /*------------- MAIN -------------*/
 int main(void)
@@ -60,21 +67,28 @@ int main(void)
   return 0;
 }
 
+/*------------- TinyUSB Callbacks -------------*/
+
+// Invoked when device is mounted (configured)
+void tuh_mount_cb (uint8_t daddr)
+{
+  printf("Device attached, address = %d\r\n", daddr);
+
+  // Get Device Descriptor sync API
+  // TODO: invoking control trannsfer now has issue with mounting hub with multiple devices attached, fix later
+  tuh_descriptor_get_device(daddr, &desc_device, 18, print_device_descriptor, 0);
+}
+
+/// Invoked when device is unmounted (bus reset/unplugged)
+void tuh_umount_cb(uint8_t daddr)
+{
+  printf("Device removed, address = %d\r\n", daddr);
+}
+
 //--------------------------------------------------------------------+
-// TinyUSB Callbacks
+// Device Descriptor
 //--------------------------------------------------------------------+
 
-// English
-#define LANGUAGE_ID 0x0409
-
-tusb_desc_device_t desc_device;
-
-//void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
-//{
-//  uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
-//  uint8_t const* p_desc   = tu_desc_next(desc_cfg);
-//}
-
 void print_device_descriptor(tuh_xfer_t* xfer)
 {
   if ( XFER_RESULT_SUCCESS != xfer->result )
@@ -125,28 +139,118 @@ void print_device_descriptor(tuh_xfer_t* xfer)
   printf("  bNumConfigurations  %u\r\n"     , desc_device.bNumConfigurations);
 
   // Get configuration descriptor with sync API
-//  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf)) )
-//  {
-//    parse_config_descriptor(daddr, (tusb_desc_configuration_t*) temp_buf);
-//  }
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf)) )
+  {
+    parse_config_descriptor(daddr, (tusb_desc_configuration_t*) temp_buf);
+  }
 }
 
-// Invoked when device is mounted (configured)
-void tuh_mount_cb (uint8_t daddr)
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+// count total length of an interface
+uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len);
+
+void open_hid_interface(uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
-  printf("Device attached, address = %d\r\n", daddr);
+  // len = interface + hid + n*endpoints
+  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
 
-  // Get Device Descriptor sync API
-  // TODO: invoking control trannsfer now has issue with mounting hub with multiple devices attached, fix later
-  tuh_descriptor_get_device(daddr, &desc_device, 18, print_device_descriptor, 0);
+  // corrupted descriptor
+  if (max_len < drv_len) return;
+
+  uint8_t const *p_desc = (uint8_t const *) desc_itf;
+
+  // HID descriptor
+  p_desc = tu_desc_next(p_desc);
+
+  // Endpoint descriptor
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+
+  for(int i = 0; i < desc_itf->bNumEndpoints; i++)
+  {
+    if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) return;
+
+    if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
+    {
+      //usbh_edpt_open(rhport, dev_addr, desc_ep);
+    }
+  }
 }
 
-/// Invoked when device is unmounted (bus reset/unplugged)
-void tuh_umount_cb(uint8_t daddr)
+// simple configuration parser to open and listen to HID Endpoint IN
+void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
 {
-  printf("Device removed, address = %d\r\n", daddr);
+  uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
+  uint8_t const* p_desc   = tu_desc_next(desc_cfg);
+
+  // parse each interfaces
+  while( p_desc < desc_end )
+  {
+    uint8_t assoc_itf_count = 1;
+
+    // Class will always starts with Interface Association (if any) and then Interface descriptor
+    if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
+    {
+      tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
+      assoc_itf_count = desc_iad->bInterfaceCount;
+
+      p_desc = tu_desc_next(p_desc); // next to Interface
+    }
+
+    // must be interface from now
+    if( TUSB_DESC_INTERFACE != tu_desc_type(p_desc) ) return;
+    tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
+
+    uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
+
+    // probably corrupted descriptor
+    if(drv_len < sizeof(tusb_desc_interface_t)) return;
+
+    // only open and listen to HID endpoint IN
+    if (desc_itf->bInterfaceClass == TUSB_CLASS_HID)
+    {
+      open_hid_interface(dev_addr, desc_itf, drv_len);
+    }
+
+    // next Interface or IAD descriptor
+    p_desc += drv_len;
+  }
 }
 
+uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len)
+{
+  uint8_t const* p_desc = (uint8_t const*) desc_itf;
+  uint16_t len = 0;
+
+  while (itf_count--)
+  {
+    // Next on interface desc
+    len += tu_desc_len(desc_itf);
+    p_desc = tu_desc_next(p_desc);
+
+    while (len < max_len)
+    {
+      // return on IAD regardless of itf count
+      if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len;
+
+      if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
+           ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 )
+      {
+        break;
+      }
+
+      len += tu_desc_len(p_desc);
+      p_desc = tu_desc_next(p_desc);
+    }
+  }
+
+  return len;
+}
+
+
 //--------------------------------------------------------------------+
 // Blinking Task
 //--------------------------------------------------------------------+
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index f946974e8..82cf911cf 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -161,6 +161,7 @@ void cdch_init(void)
 
 bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
+  (void) rhport;
   (void) max_len;
 
   // Only support ACM subclass
@@ -196,7 +197,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
     // notification endpoint
     tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
 
-    TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep) );
+    TU_ASSERT( usbh_edpt_open(dev_addr, desc_ep) );
     p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
     drv_len += tu_desc_len(p_desc);
@@ -217,7 +218,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
       tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
       TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
 
-      TU_ASSERT(usbh_edpt_open(rhport, dev_addr, desc_ep));
+      TU_ASSERT(usbh_edpt_open(dev_addr, desc_ep));
 
       if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
       {
diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 940454bd9..44a464be1 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -43,7 +43,7 @@
 /** \defgroup ClassDriver_HID_Common Common Definitions
  *  @{ */
 
- /// USB HID Descriptor
+/// USB HID Descriptor
 typedef struct TU_ATTR_PACKED
 {
   uint8_t  bLength;         /**< Numeric expression that is the total size of the HID descriptor */
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 2bdd1db79..2280e87b4 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -324,6 +324,7 @@ void hidh_close(uint8_t dev_addr)
 
 bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
+  (void) rhport;
   (void) max_len;
 
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass);
@@ -355,7 +356,7 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   for(int i = 0; i < desc_itf->bNumEndpoints; i++)
   {
     TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
-    TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep) );
+    TU_ASSERT( usbh_edpt_open(dev_addr, desc_ep) );
 
     if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
     {
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 06af781f5..4033cc429 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -365,6 +365,7 @@ static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw
 
 bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
+  (void) rhport;
   TU_VERIFY (MSC_SUBCLASS_SCSI == desc_itf->bInterfaceSubClass &&
              MSC_PROTOCOL_BOT  == desc_itf->bInterfaceProtocol);
 
@@ -378,7 +379,7 @@ bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   for(uint32_t i=0; i<2; i++)
   {
     TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
-    TU_ASSERT(usbh_edpt_open(rhport, dev_addr, ep_desc));
+    TU_ASSERT(usbh_edpt_open(dev_addr, ep_desc));
 
     if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
     {
diff --git a/src/host/hub.c b/src/host/hub.c
index da4f6fe3a..b4d369aca 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -183,6 +183,8 @@ void hub_init(void)
 
 bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
+  (void) rhport;
+
   TU_VERIFY(TUSB_CLASS_HUB == itf_desc->bInterfaceClass &&
             0              == itf_desc->bInterfaceSubClass);
 
@@ -199,7 +201,7 @@ bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf
   TU_ASSERT(TUSB_DESC_ENDPOINT  == desc_ep->bDescriptorType &&
             TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0);
   
-  TU_ASSERT(usbh_edpt_open(rhport, dev_addr, desc_ep));
+  TU_ASSERT(usbh_edpt_open(dev_addr, desc_ep));
 
   hub_interface_t* p_hub = get_itf(dev_addr);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 497badfde..466e5decd 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -806,10 +806,11 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
   return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc);
 }
 
-bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
+bool usbh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
 {
   TU_ASSERT( tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr)) );
-  return hcd_edpt_open(rhport, dev_addr, desc_ep);
+
+  return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep);
 }
 
 bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
@@ -1189,7 +1190,7 @@ enum {
 };
 
 static bool enum_request_set_addr(void);
-static bool parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
+static bool _parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
 static void enum_full_complete(void);
 
 // process device enumeration
@@ -1350,7 +1351,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
     case ENUM_SET_CONFIG:
       // Parse configuration & set up drivers
       // Driver open aren't allowed to make any usb transfer yet
-      TU_ASSERT( parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf), );
+      TU_ASSERT( _parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf), );
 
       TU_ASSERT( tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER), );
     break;
@@ -1496,7 +1497,7 @@ static bool enum_request_set_addr(void)
   return true;
 }
 
-static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
+static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
 {
   usbh_device_t* dev = get_device(dev_addr);
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 772c4cfd6..a2df0153e 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -44,8 +44,10 @@ typedef struct tuh_xfer_s tuh_xfer_t;
 
 typedef void (*tuh_xfer_cb_t)(tuh_xfer_t* xfer);
 
-// Note: layout and order of this will be changed in near future
+// Note1: layout and order of this will be changed in near future
 // it is advised to initialize it using member name
+// Note2: not all field is available/meaningful in callback, some info is not saved by
+// usbh to save SRAM
 struct tuh_xfer_s
 {
   uint8_t daddr;
@@ -124,14 +126,18 @@ static inline bool tuh_ready(uint8_t daddr)
 //--------------------------------------------------------------------+
 
 // Submit a control transfer
-// Note: blocking if complete callback is NULL, in this case xfer contents will be updated to reflect the result
+//  - async: complete callback invoked when finished.
+//  - sync : blocking if complete callback is NULL.
 bool tuh_control_xfer(tuh_xfer_t* xfer);
 
 // Submit a bulk/interrupt transfer
-// xfer memory must exist until transfer is complete.
-// Note: blocking if complete callback is NULL.
+//  - async: complete callback invoked when finished.
+//  - sync : blocking if complete callback is NULL.
 bool tuh_edpt_xfer(tuh_xfer_t* xfer);
 
+// Open an endpoint
+bool usbh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
+
 // Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
 // true on success, false if there is on-going control transfer or incorrect parameters
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index 30e97535d..c156afea0 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -63,9 +63,6 @@ void usbh_int_set(bool enabled);
 // USBH Endpoint API
 //--------------------------------------------------------------------+
 
-// Open an endpoint
-bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
-
 // Submit a usb transfer with callback support, require CFG_TUH_API_EDPT_XFER
 bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data);
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 8d420f26a..665f2380b 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -656,6 +656,26 @@ static void xfer_error_isr(uint8_t hostid)
   }
 }
 
+#if CFG_TUSB_DEBUG >= EHCI_DBG
+
+static inline void print_portsc(ehci_registers_t* regs)
+{
+  TU_LOG_HEX(EHCI_DBG, regs->portsc);
+  TU_LOG(EHCI_DBG, "  Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status);
+  TU_LOG(EHCI_DBG, "  Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change);
+  TU_LOG(EHCI_DBG, "  Port Enabled          : %u\r\n", regs->portsc_bm.port_enabled);
+  TU_LOG(EHCI_DBG, "  Port Enabled Change   : %u\r\n", regs->portsc_bm.port_enable_change);
+
+  TU_LOG(EHCI_DBG, "  Port Reset            : %u\r\n", regs->portsc_bm.port_reset);
+  TU_LOG(EHCI_DBG, "  Port Power            : %u\r\n", regs->portsc_bm.port_power);
+}
+
+#else
+
+#define print_portsc(_reg)
+
+#endif
+
 //------------- Host Controller Driver's Interrupt Handler -------------//
 void hcd_int_handler(uint8_t rhport)
 {
@@ -675,9 +695,8 @@ void hcd_int_handler(uint8_t rhport)
 
   if (int_status & EHCI_INT_MASK_PORT_CHANGE)
   {
-    uint32_t port_status = regs->portsc & EHCI_PORTSC_MASK_ALL;
-
-    TU_LOG_HEX(EHCI_DBG, regs->portsc);
+    uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_ALL;
+    print_portsc(regs);
 
     if (regs->portsc_bm.connect_status_change)
     {
diff --git a/src/tusb.h b/src/tusb.h
index 222855fcb..b776d7d01 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -38,6 +38,8 @@
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
 
+#include "class/hid/hid.h"
+
 //------------- HOST -------------//
 #if CFG_TUH_ENABLED
   #include "host/usbh.h"

From a4b976f095ae36ab90cfc5394211598626ff895e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Mar 2022 14:57:43 +0700
Subject: [PATCH 0927/2085] get bare example working with hid device

---
 examples/host/bare_api/src/main.c | 86 +++++++++++++++++++++++++++++--
 1 file changed, 83 insertions(+), 3 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 3b23dd43b..3f3d1d488 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -49,6 +49,11 @@ void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const*
 
 tusb_desc_device_t desc_device;
 
+#define BUF_COUNT   4
+
+uint8_t buf_pool[BUF_COUNT][64];
+uint8_t buf_owner[BUF_COUNT] = { 0 }; // device address that owns buffer
+
 /*------------- MAIN -------------*/
 int main(void)
 {
@@ -139,7 +144,7 @@ void print_device_descriptor(tuh_xfer_t* xfer)
   printf("  bNumConfigurations  %u\r\n"     , desc_device.bNumConfigurations);
 
   // Get configuration descriptor with sync API
-  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf)) )
+  if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf)))
   {
     parse_config_descriptor(daddr, (tusb_desc_configuration_t*) temp_buf);
   }
@@ -150,10 +155,60 @@ void print_device_descriptor(tuh_xfer_t* xfer)
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
+// get an buffer from pool
+uint8_t* get_hid_buf(uint8_t daddr)
+{
+  for(size_t i=0; i<BUF_COUNT; i++)
+  {
+    if (buf_owner[i] == 0)
+    {
+      buf_owner[i] = daddr;
+      return buf_pool[i];
+    }
+  }
+
+  // out of memory, increase BUF_COUNT
+  return NULL;
+}
+
+// free all buffer owned by device
+void free_hid_buf(uint8_t daddr)
+{
+  for(size_t i=0; i<BUF_COUNT; i++)
+  {
+    if (buf_owner[i] == daddr) buf_owner[i] = 0;
+  }
+}
+
+void hid_report_received(tuh_xfer_t* xfer)
+{
+  // Note: not all field in xfer is available for use (i.e filled by tinyusb stack) in callback to save sram
+  // For instance, xfer->buffer is NULL. We have used user_data to store buffer when submitted callback
+  uint8_t* buf = (uint8_t*) xfer->user_data;
+
+  if (xfer->result == XFER_RESULT_SUCCESS)
+  {
+    printf("[dev %u: ep %02x] HID Report:", xfer->daddr, xfer->ep_addr);
+    for(uint32_t i=0; i<xfer->actual_len; i++)
+    {
+      if (i%16 == 0) printf("\r\n  ");
+      printf("%02X ", buf[i]);
+    }
+    printf("\r\n");
+  }
+
+  // continue to submit transfer, with updated buffer
+  // other field remain the same
+  xfer->buflen = 64;
+  xfer->buffer = buf;
+
+  tuh_edpt_xfer(xfer);
+}
+
 // count total length of an interface
 uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len);
 
-void open_hid_interface(uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
+void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
   // len = interface + hid + n*endpoints
   uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
@@ -165,8 +220,11 @@ void open_hid_interface(uint8_t dev_addr, tusb_desc_interface_t const *desc_itf,
 
   // HID descriptor
   p_desc = tu_desc_next(p_desc);
+  tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc;
+  if(HID_DESC_TYPE_HID != desc_hid->bDescriptorType) return;
 
   // Endpoint descriptor
+  p_desc = tu_desc_next(p_desc);
   tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
 
   for(int i = 0; i < desc_itf->bNumEndpoints; i++)
@@ -175,8 +233,30 @@ void open_hid_interface(uint8_t dev_addr, tusb_desc_interface_t const *desc_itf,
 
     if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
     {
-      //usbh_edpt_open(rhport, dev_addr, desc_ep);
+      // skip if failed to open endpoint
+      if ( ! usbh_edpt_open(daddr, desc_ep) ) return;
+
+      uint8_t* buf = get_hid_buf(daddr);
+      if (!buf) return; // out of memory
+
+      tuh_xfer_t xfer =
+      {
+        .daddr       = daddr,
+        .ep_addr     = desc_ep->bEndpointAddress,
+        .buflen      = 64,
+        .buffer      = buf,
+        .complete_cb = hid_report_received,
+        .user_data   = (uintptr_t) buf, // since buffer is not available in callback, use user data to store the buffer
+      };
+
+      // submit transfer for this EP
+      tuh_edpt_xfer(&xfer);
+
+      printf("Listen to [dev %u: ep %02x]\r\n", daddr, desc_ep->bEndpointAddress);
     }
+
+    p_desc = tu_desc_next(p_desc);
+    desc_ep = (tusb_desc_endpoint_t const *) p_desc;
   }
 }
 

From 821be65b034bd69210834ae7400527149cb66e43 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Mar 2022 14:59:31 +0700
Subject: [PATCH 0928/2085] rename usbh_edpt_open() to tuh_edpt_open()

---
 examples/host/bare_api/src/main.c | 2 +-
 src/class/cdc/cdc_host.c          | 4 ++--
 src/class/hid/hid_host.c          | 2 +-
 src/class/msc/msc_host.c          | 2 +-
 src/host/hub.c                    | 2 +-
 src/host/usbh.c                   | 2 +-
 src/host/usbh.h                   | 4 ++--
 7 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 3f3d1d488..fa50c7af3 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -234,7 +234,7 @@ void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, ui
     if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
     {
       // skip if failed to open endpoint
-      if ( ! usbh_edpt_open(daddr, desc_ep) ) return;
+      if ( ! tuh_edpt_open(daddr, desc_ep) ) return;
 
       uint8_t* buf = get_hid_buf(daddr);
       if (!buf) return; // out of memory
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 82cf911cf..044085e81 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -197,7 +197,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
     // notification endpoint
     tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
 
-    TU_ASSERT( usbh_edpt_open(dev_addr, desc_ep) );
+    TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) );
     p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
     drv_len += tu_desc_len(p_desc);
@@ -218,7 +218,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
       tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
       TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
 
-      TU_ASSERT(usbh_edpt_open(dev_addr, desc_ep));
+      TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep));
 
       if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
       {
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 2280e87b4..ce3d1598c 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -356,7 +356,7 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   for(int i = 0; i < desc_itf->bNumEndpoints; i++)
   {
     TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
-    TU_ASSERT( usbh_edpt_open(dev_addr, desc_ep) );
+    TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) );
 
     if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
     {
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 4033cc429..c54a63f37 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -379,7 +379,7 @@ bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   for(uint32_t i=0; i<2; i++)
   {
     TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
-    TU_ASSERT(usbh_edpt_open(dev_addr, ep_desc));
+    TU_ASSERT(tuh_edpt_open(dev_addr, ep_desc));
 
     if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
     {
diff --git a/src/host/hub.c b/src/host/hub.c
index b4d369aca..9e546f6f7 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -201,7 +201,7 @@ bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf
   TU_ASSERT(TUSB_DESC_ENDPOINT  == desc_ep->bDescriptorType &&
             TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0);
   
-  TU_ASSERT(usbh_edpt_open(dev_addr, desc_ep));
+  TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep));
 
   hub_interface_t* p_hub = get_itf(dev_addr);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 466e5decd..f534070de 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -806,7 +806,7 @@ static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
   return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc);
 }
 
-bool usbh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
+bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
 {
   TU_ASSERT( tu_edpt_validate(desc_ep, tuh_speed_get(dev_addr)) );
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index a2df0153e..e883ac90b 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -135,8 +135,8 @@ bool tuh_control_xfer(tuh_xfer_t* xfer);
 //  - sync : blocking if complete callback is NULL.
 bool tuh_edpt_xfer(tuh_xfer_t* xfer);
 
-// Open an endpoint
-bool usbh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
+// Open an non-control endpoint
+bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
 
 // Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1

From a270d8d6236124244f5a1447d57b35f4cfa4909c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Mar 2022 15:06:12 +0700
Subject: [PATCH 0929/2085] move code around

---
 examples/host/bare_api/src/main.c | 232 ++++++++++++++++--------------
 1 file changed, 123 insertions(+), 109 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index fa50c7af3..eb3f7d8d7 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -37,6 +37,13 @@
 
 // English
 #define LANGUAGE_ID 0x0409
+#define BUF_COUNT   4
+
+
+tusb_desc_device_t desc_device;
+
+uint8_t buf_pool[BUF_COUNT][64];
+uint8_t buf_owner[BUF_COUNT] = { 0 }; // device address that owns buffer
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
@@ -47,12 +54,8 @@ static void print_utf16(uint16_t *temp_buf, size_t buf_len);
 void print_device_descriptor(tuh_xfer_t* xfer);
 void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
 
-tusb_desc_device_t desc_device;
-
-#define BUF_COUNT   4
-
-uint8_t buf_pool[BUF_COUNT][64];
-uint8_t buf_owner[BUF_COUNT] = { 0 }; // device address that owns buffer
+uint8_t* get_hid_buf(uint8_t daddr);
+void free_hid_buf(uint8_t daddr);
 
 /*------------- MAIN -------------*/
 int main(void)
@@ -88,6 +91,7 @@ void tuh_mount_cb (uint8_t daddr)
 void tuh_umount_cb(uint8_t daddr)
 {
   printf("Device removed, address = %d\r\n", daddr);
+  free_hid_buf(daddr);
 }
 
 //--------------------------------------------------------------------+
@@ -150,115 +154,14 @@ void print_device_descriptor(tuh_xfer_t* xfer)
   }
 }
 
-
 //--------------------------------------------------------------------+
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
-// get an buffer from pool
-uint8_t* get_hid_buf(uint8_t daddr)
-{
-  for(size_t i=0; i<BUF_COUNT; i++)
-  {
-    if (buf_owner[i] == 0)
-    {
-      buf_owner[i] = daddr;
-      return buf_pool[i];
-    }
-  }
-
-  // out of memory, increase BUF_COUNT
-  return NULL;
-}
-
-// free all buffer owned by device
-void free_hid_buf(uint8_t daddr)
-{
-  for(size_t i=0; i<BUF_COUNT; i++)
-  {
-    if (buf_owner[i] == daddr) buf_owner[i] = 0;
-  }
-}
-
-void hid_report_received(tuh_xfer_t* xfer)
-{
-  // Note: not all field in xfer is available for use (i.e filled by tinyusb stack) in callback to save sram
-  // For instance, xfer->buffer is NULL. We have used user_data to store buffer when submitted callback
-  uint8_t* buf = (uint8_t*) xfer->user_data;
-
-  if (xfer->result == XFER_RESULT_SUCCESS)
-  {
-    printf("[dev %u: ep %02x] HID Report:", xfer->daddr, xfer->ep_addr);
-    for(uint32_t i=0; i<xfer->actual_len; i++)
-    {
-      if (i%16 == 0) printf("\r\n  ");
-      printf("%02X ", buf[i]);
-    }
-    printf("\r\n");
-  }
-
-  // continue to submit transfer, with updated buffer
-  // other field remain the same
-  xfer->buflen = 64;
-  xfer->buffer = buf;
-
-  tuh_edpt_xfer(xfer);
-}
-
 // count total length of an interface
 uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len);
 
-void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
-{
-  // len = interface + hid + n*endpoints
-  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
-
-  // corrupted descriptor
-  if (max_len < drv_len) return;
-
-  uint8_t const *p_desc = (uint8_t const *) desc_itf;
-
-  // HID descriptor
-  p_desc = tu_desc_next(p_desc);
-  tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc;
-  if(HID_DESC_TYPE_HID != desc_hid->bDescriptorType) return;
-
-  // Endpoint descriptor
-  p_desc = tu_desc_next(p_desc);
-  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-
-  for(int i = 0; i < desc_itf->bNumEndpoints; i++)
-  {
-    if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) return;
-
-    if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
-    {
-      // skip if failed to open endpoint
-      if ( ! tuh_edpt_open(daddr, desc_ep) ) return;
-
-      uint8_t* buf = get_hid_buf(daddr);
-      if (!buf) return; // out of memory
-
-      tuh_xfer_t xfer =
-      {
-        .daddr       = daddr,
-        .ep_addr     = desc_ep->bEndpointAddress,
-        .buflen      = 64,
-        .buffer      = buf,
-        .complete_cb = hid_report_received,
-        .user_data   = (uintptr_t) buf, // since buffer is not available in callback, use user data to store the buffer
-      };
-
-      // submit transfer for this EP
-      tuh_edpt_xfer(&xfer);
-
-      printf("Listen to [dev %u: ep %02x]\r\n", daddr, desc_ep->bEndpointAddress);
-    }
-
-    p_desc = tu_desc_next(p_desc);
-    desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-  }
-}
+void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
 
 // simple configuration parser to open and listen to HID Endpoint IN
 void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
@@ -330,6 +233,117 @@ uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_
   return len;
 }
 
+//--------------------------------------------------------------------+
+// HID Interface
+//--------------------------------------------------------------------+
+
+void hid_report_received(tuh_xfer_t* xfer);
+
+void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
+{
+  // len = interface + hid + n*endpoints
+  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
+
+  // corrupted descriptor
+  if (max_len < drv_len) return;
+
+  uint8_t const *p_desc = (uint8_t const *) desc_itf;
+
+  // HID descriptor
+  p_desc = tu_desc_next(p_desc);
+  tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc;
+  if(HID_DESC_TYPE_HID != desc_hid->bDescriptorType) return;
+
+  // Endpoint descriptor
+  p_desc = tu_desc_next(p_desc);
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+
+  for(int i = 0; i < desc_itf->bNumEndpoints; i++)
+  {
+    if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) return;
+
+    if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
+    {
+      // skip if failed to open endpoint
+      if ( ! tuh_edpt_open(daddr, desc_ep) ) return;
+
+      uint8_t* buf = get_hid_buf(daddr);
+      if (!buf) return; // out of memory
+
+      tuh_xfer_t xfer =
+      {
+        .daddr       = daddr,
+        .ep_addr     = desc_ep->bEndpointAddress,
+        .buflen      = 64,
+        .buffer      = buf,
+        .complete_cb = hid_report_received,
+        .user_data   = (uintptr_t) buf, // since buffer is not available in callback, use user data to store the buffer
+      };
+
+      // submit transfer for this EP
+      tuh_edpt_xfer(&xfer);
+
+      printf("Listen to [dev %u: ep %02x]\r\n", daddr, desc_ep->bEndpointAddress);
+    }
+
+    p_desc = tu_desc_next(p_desc);
+    desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+  }
+}
+
+void hid_report_received(tuh_xfer_t* xfer)
+{
+  // Note: not all field in xfer is available for use (i.e filled by tinyusb stack) in callback to save sram
+  // For instance, xfer->buffer is NULL. We have used user_data to store buffer when submitted callback
+  uint8_t* buf = (uint8_t*) xfer->user_data;
+
+  if (xfer->result == XFER_RESULT_SUCCESS)
+  {
+    printf("[dev %u: ep %02x] HID Report:", xfer->daddr, xfer->ep_addr);
+    for(uint32_t i=0; i<xfer->actual_len; i++)
+    {
+      if (i%16 == 0) printf("\r\n  ");
+      printf("%02X ", buf[i]);
+    }
+    printf("\r\n");
+  }
+
+  // continue to submit transfer, with updated buffer
+  // other field remain the same
+  xfer->buflen = 64;
+  xfer->buffer = buf;
+
+  tuh_edpt_xfer(xfer);
+}
+
+//--------------------------------------------------------------------+
+// Buffer helper
+//--------------------------------------------------------------------+
+
+// get an buffer from pool
+uint8_t* get_hid_buf(uint8_t daddr)
+{
+  for(size_t i=0; i<BUF_COUNT; i++)
+  {
+    if (buf_owner[i] == 0)
+    {
+      buf_owner[i] = daddr;
+      return buf_pool[i];
+    }
+  }
+
+  // out of memory, increase BUF_COUNT
+  return NULL;
+}
+
+// free all buffer owned by device
+void free_hid_buf(uint8_t daddr)
+{
+  for(size_t i=0; i<BUF_COUNT; i++)
+  {
+    if (buf_owner[i] == daddr) buf_owner[i] = 0;
+  }
+}
 
 //--------------------------------------------------------------------+
 // Blinking Task
@@ -350,7 +364,7 @@ void led_blinking_task(void)
 }
 
 //--------------------------------------------------------------------+
-// Helper
+// String Descriptor Helper
 //--------------------------------------------------------------------+
 
 static void _convert_utf16le_to_utf8(const uint16_t *utf16, size_t utf16_len, uint8_t *utf8, size_t utf8_len) {

From fdfde8883ff6d929f44706d1fd3ee3cec8702bac Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Sat, 19 Mar 2022 13:37:54 +0100
Subject: [PATCH 0930/2085] Implement power of two, shift, and float
 calculation

---
 src/class/audio/audio_device.c | 68 ++++++++++++++++++++++++++++------
 src/class/audio/audio_device.h |  4 +-
 src/common/tusb_common.h       | 10 +++++
 3 files changed, 69 insertions(+), 13 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index f0cab4d93..a815f7557 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -308,11 +308,15 @@ typedef struct
   uint32_t fb_val;                                                              // Feedback value for asynchronous mode (in 16.16 format).
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
-  uint8_t n_frames;                                                            // Number of (micro)frames used to estimate feedback value
-  uint8_t n_frames_current;                                                    // Current (micro)frame number
-  uint32_t n_cycles_old;                                                       // Old cycle count
-  uint32_t feeback_param_factor_N;                                             // Numerator of feedback parameter coefficient
-  uint32_t feeback_param_factor_D;                                             // Denominator of feedback parameter coefficient
+  uint8_t n_frames;                                                             // Number of (micro)frames used to estimate feedback value
+  uint8_t n_frames_current;                                                     // Current (micro)frame number
+  uint32_t n_cycles_old;                                                        // Old cycle count
+  union {
+    uint32_t i;
+    float    f;
+  } feedback_param_factor_N;                                                    // Numerator of feedback parameter coefficient
+  uint32_t feedback_param_factor_D;                                             // Denominator of feedback parameter coefficient
+  uint32_t * feedback_param_p_cycle_count;                                      // Pointer to cycle counter
 #endif
 
 #endif
@@ -2010,14 +2014,39 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 // f_s max is 2^19-1 = 524287 Hz
 // n_frames_min is ceil(2^10 * f_s / f_m) for full speed and ceil(2^13 * f_s / f_m) for high speed
 // f_m max is 2^29/(1 ms * n_frames) for full speed and 2^29/(125 us * n_frames) for high speed
-bool tud_audio_set_feedback_params_fm_fs(uint8_t func_id, uint32_t f_m, uint32_t f_s)
+bool tud_audio_set_feedback_params_fm_fs(uint8_t func_id, uint32_t f_m, uint32_t f_s, uint32_t * p_cycle_count, bool use_float)
 {
   audiod_function_t* audio = &_audiod_fct[func_id];
+  audio->feedback_param_p_cycle_count = p_cycle_count;
   uint8_t n_frame = 1;    // TODO: finalize that
   audio->n_frames = n_frame;
-  audio->feeback_param_factor_N = f_s << 13;
-  audio->feeback_param_factor_D = f_m * n_frame;
+
+
+
+  // Check if parameters reduce to a power of two shift i.e. is n_f * f_m / f_s a power of two?
+  if ((f_m % f_s) == 0 && tu_is_power_of_two(n_frame * f_m / f_s))
+  {
+    audio->feedback_param_factor_N.i = 0;                                                 // zero marks power of two option
+    audio->feedback_param_factor_D = 16 - tu_log2(n_frame * f_m / f_s);
+  }
+  else
+  {
+    // Next best option is to use float if a FPU is available - this has to be enabled by the user
+    if (use_float)
+    {
+      audio->feedback_param_factor_N.f = (float)f_s / n_frame / f_m * (1 << 16);
+      audio->feedback_param_factor_D = 0;                                                 // non zero marks float option
+    }
+    else
+    {
+      // Neither a power of two or floats - use fixed point number
+      audio->feedback_param_factor_N.i = f_s << 13;
+      audio->feedback_param_factor_D = f_m * n_frame;
+    }
+  }
+
   return true;
+
 }
 #endif
 
@@ -2044,10 +2073,27 @@ void audiod_sof (uint8_t rhport, uint32_t frame_count)
         audio->n_frames_current++;
         if (audio->n_frames_current == audio->n_frames)
         {
-          uint32_t n_cylces = tud_audio_n_get_fm_n_cycles_cb(rhport, audio->ep_fb);
-          uint32_t feedback = ((n_cylces - audio->n_cycles_old) << 3) * audio->feeback_param_factor_N / audio->feeback_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
+          uint32_t n_cylces = *audio->feedback_param_p_cycle_count;
+          uint32_t feedback;
 
-          // TODO: Implement fast computation in case n_frames * f_s / f_m is a power of two
+          if (audio->feedback_param_factor_N.i == 0)
+          {
+            // Power of two shift
+            feedback = n_cylces << audio->feedback_param_factor_D;
+          }
+          else
+          {
+            if (audio->feedback_param_factor_D == 0)
+            {
+              // Float computation
+              feedback = (uint32_t)(n_cylces * audio->feedback_param_factor_N.f);
+            }
+            else
+            {
+              // Fixed point computation
+              feedback = ((n_cylces - audio->n_cycles_old) << 3) * audio->feedback_param_factor_N.i / audio->feedback_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
+            }
+          }
 
           tud_audio_n_fb_set(i, feedback);
           audio->n_frames_current = 0;
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index eba8a6488..3645bda46 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -193,7 +193,7 @@
 
 // Determine feedback value within SOF ISR within audio driver - if disabled the user has to call tud_audio_n_fb_set() with a suitable feedback value on its own. If done within audio driver SOF ISR, tud_audio_n_fb_set() is disabled for user
 #ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR    0                             // 0 or 1
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR    1                             // 0 or 1
 #endif
 
 // Audio interrupt control EP size - disabled if 0
@@ -487,7 +487,7 @@ TU_ATTR_WEAK uint32_t tud_audio_n_get_fm_n_cycles_cb(uint8_t rhport, uint8_t ep_
 
 // f_m : Main clock frequency in Hz i.e. master clock to which sample clock is locked
 // f_s : Current sample rate in Hz
-bool tud_audio_set_feedback_params_fm_fs(uint8_t func_id, uint32_t f_m, uint32_t f_s);
+bool tud_audio_set_feedback_params_fm_fs(uint8_t func_id, uint32_t f_m, uint32_t f_s, uint32_t * p_cycle_count, bool use_float);
 #endif
 
 #endif
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 58591f0be..bcdf8933a 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -149,6 +149,16 @@ static inline uint8_t tu_log2(uint32_t value)
   return result;
 }
 
+//static inline uint8_t tu_log2(uint32_t value)
+//{
+//   return sizeof(uint32_t) * CHAR_BIT - __builtin_clz(x) - 1;
+//}
+
+static inline bool tu_is_power_of_two(uint32_t value)
+{
+   return (value != 0) && ((value & (value - 1)) == 0);
+}
+
 //------------- Unaligned Access -------------//
 #if TUP_ARCH_STRICT_ALIGN
 

From ff2dc0a5471c3166a1995cc2abb5f42a8a9ab035 Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Sun, 20 Mar 2022 11:21:33 +0100
Subject: [PATCH 0931/2085] Streamline feedback calc, find fb interval from
 descriptors, inc. checks

---
 src/class/audio/audio_device.c | 195 ++++++++++++++++++---------------
 src/class/audio/audio_device.h |  28 ++++-
 2 files changed, 135 insertions(+), 88 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index a815f7557..b97155823 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -305,18 +305,29 @@ typedef struct
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-  uint32_t fb_val;                                                              // Feedback value for asynchronous mode (in 16.16 format).
+#if !CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+  uint32_t fb_val;                                                                        // Feedback value for asynchronous mode (in 16.16 format).
+#endif
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
-  uint8_t n_frames;                                                             // Number of (micro)frames used to estimate feedback value
-  uint8_t n_frames_current;                                                     // Current (micro)frame number
-  uint32_t n_cycles_old;                                                        // Old cycle count
-  union {
-    uint32_t i;
-    float    f;
-  } feedback_param_factor_N;                                                    // Numerator of feedback parameter coefficient
-  uint32_t feedback_param_factor_D;                                             // Denominator of feedback parameter coefficient
-  uint32_t * feedback_param_p_cycle_count;                                      // Pointer to cycle counter
+  volatile uint32_t fb_val;                                                               // Feedback value for asynchronous mode (in 16.16 format).
+  uint8_t fb_n_frames;                                                                    // Number of (micro)frames used to estimate feedback value
+  volatile uint8_t fb_n_frames_current;                                                   // Current (micro)frame number
+  volatile uint32_t fb_n_cycles_old;                                                      // Old cycle count
+  uint32_t * fb_param_p_cycle_count;                                                      // Pointer to cycle counter
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT
+  uint8_t fb_power_of_two_val;
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT
+  float fb_float_val;
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT
+  uint64_t fb_param_factor_N;                                                       // Numerator of feedback parameter coefficient
+  uint64_t fb_param_factor_D;                                                       // Denominator of feedback parameter coefficient
+#endif
 #endif
 
 #endif
@@ -1527,7 +1538,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
       tu_fifo_clear(&audio->tx_supp_ff[cnt]);
     }
 #endif
-    
+
     // Invoke callback - can be used to stop data sampling
     if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
 
@@ -1560,7 +1571,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     // Close corresponding feedback EP
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
     usbd_edpt_close(rhport, audio->ep_fb);
-    audio->ep_fb = 0;                           // Necessary?
+    audio->ep_fb = 0;
 #endif
   }
 #endif
@@ -1677,8 +1688,9 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
             usbd_sof_enable(rhport, true);       // Enable SOF interrupt
-            audio->n_frames_current = 0;
-            audio->n_cycles_old = 0;
+            audio->fb_n_frames = desc_ep->bInterval;
+            audio->fb_n_frames_current = 0;
+            audio->fb_n_cycles_old = 0;
 #endif
 
             // Invoke callback after ep_out is set
@@ -1711,12 +1723,12 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   bool disable = true;
 
   for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
+  {
+    if (_audiod_fct[i].ep_fb != 0)
     {
-      if (_audiod_fct[i].ep_fb != 0)
-      {
-        disable = false;
-      }
+      disable = false;
     }
+  }
 
   if (disable) usbd_sof_enable(rhport, false);
 
@@ -2011,40 +2023,56 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 }
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
-// f_s max is 2^19-1 = 524287 Hz
-// n_frames_min is ceil(2^10 * f_s / f_m) for full speed and ceil(2^13 * f_s / f_m) for high speed
-// f_m max is 2^29/(1 ms * n_frames) for full speed and 2^29/(125 us * n_frames) for high speed
-bool tud_audio_set_feedback_params_fm_fs(uint8_t func_id, uint32_t f_m, uint32_t f_s, uint32_t * p_cycle_count, bool use_float)
+
+// This function must be called from the user within the tud_audio_set_itf_cb(rhport, p_request) callback function, where p_request needs to be checked as
+// uint8_t const itf = tu_u16_low(p_request->wIndex);
+// uint8_t const alt = tu_u16_low(p_request->wValue);
+// such that tud_audio_set_fb_params() gets called with the parameters corresponding to the defined interface and alternate setting
+// Also, start the main clock cycle counter (or reset its value) within tud_audio_set_itf_cb()
+TU_ATTR_WEAK bool tud_audio_set_fb_params(uint8_t func_id, uint32_t f_m, uint32_t f_s, uint32_t * p_cycle_count)
 {
   audiod_function_t* audio = &_audiod_fct[func_id];
-  audio->feedback_param_p_cycle_count = p_cycle_count;
-  uint8_t n_frame = 1;    // TODO: finalize that
-  audio->n_frames = n_frame;
+  audio->fb_param_p_cycle_count = p_cycle_count;
 
+  // Check if frame interval is within sane limits
+  // The interval value audio->fb_n_frames was taken from the descriptors within audiod_set_interface()
 
-
-  // Check if parameters reduce to a power of two shift i.e. is n_f * f_m / f_s a power of two?
-  if ((f_m % f_s) == 0 && tu_is_power_of_two(n_frame * f_m / f_s))
+  // n_frames_min is ceil(2^10 * f_s / f_m) for full speed and ceil(2^13 * f_s / f_m) for high speed - this lower limit ensures the measures feedback value has sufficient precision
+  if ((TUSB_SPEED_FULL == tud_speed_get() && ((2^10 * f_s / f_m) + 1) > audio->fb_n_frames) || (TUSB_SPEED_HIGH == tud_speed_get() && ((2^13 * f_s / f_m) + 1) > audio->fb_n_frames))
   {
-    audio->feedback_param_factor_N.i = 0;                                                 // zero marks power of two option
-    audio->feedback_param_factor_D = 16 - tu_log2(n_frame * f_m / f_s);
+    TU_LOG2("  UAC2 feedback interval too small\r\n"); TU_BREAKPOINT(); return false;
   }
-  else
+
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT
+  // Check if parameters really allow for a power of two division
+  if ((f_m % f_s) != 0 || !tu_is_power_of_two(audio->fb_n_frames * f_m / f_s))
   {
-    // Next best option is to use float if a FPU is available - this has to be enabled by the user
-    if (use_float)
-    {
-      audio->feedback_param_factor_N.f = (float)f_s / n_frame / f_m * (1 << 16);
-      audio->feedback_param_factor_D = 0;                                                 // non zero marks float option
-    }
-    else
-    {
-      // Neither a power of two or floats - use fixed point number
-      audio->feedback_param_factor_N.i = f_s << 13;
-      audio->feedback_param_factor_D = f_m * n_frame;
-    }
+    TU_LOG2("  FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT not possible!\r\n"); TU_BREAKPOINT(); return false;
   }
 
+  audio->fb_power_of_two_val = 16 - tu_log2(audio->fb_n_frames * f_m / f_s);
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT
+  audio->fb_float_val = (float)f_s / audio->fb_n_frames / f_m * (1 << 16);
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT
+
+  // f_s max is 2^19-1 = 524287 Hz
+  // f_m max is 2^29/(1 ms * n_frames) for full speed and 2^29/(125 us * n_frames) for high speed, this means for f_m fitting in an uint32, n_frames must be < 125 for full speed and < 1000 for high speed (1000 does not fit into uint8 so the maximum possible value cannot even be reached by UAC2 - we don't need to check for it)
+
+  if ((f_s > (2^19)-1) || (TUSB_SPEED_FULL == tud_speed_get() && (audio->fb_n_frames > 125)))
+  {
+    // If this check fails, not every thing is lost - you need to re-evaluate the scaling factors of the parameters such that the numbers fit into uint64 again. feedback = n_cycles * S_c / (n_frames * S_n) * f_s * S_s / (f_m * S_m). In the end S_c*S_s / (S_n * S_m) = 2^16 for a 16.16 fixed point precision. If you find something, define your own function of tud_audio_set_feedback_params_fm_fs() and audiod_sof() and use your values
+    TU_LOG2("  FEEDBACK_DETERMINATION_MODE_FIXED_POINT not possible!\r\n"); TU_BREAKPOINT(); return false;
+  }
+
+  audio->fb_param_factor_N = (uint64_t)f_s << 13;
+  audio->fb_param_factor_D = (uint64_t)f_m * audio->fb_n_frames;
+#endif
+
   return true;
 
 }
@@ -2053,54 +2081,47 @@ bool tud_audio_set_feedback_params_fm_fs(uint8_t func_id, uint32_t f_m, uint32_t
 void audiod_sof (uint8_t rhport, uint32_t frame_count)
 {
   (void) rhport;
-  (void) frame_count;
+  (void) frame_count;         // frame_count is not used since some devices may not provide the frame count value
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
 
   // Determine feedback value - The feedback method is described in 5.12.4.2 of the USB 2.0 spec
   // Boiled down, the feedback value Ff = n_samples / (micro)frame.
-  // Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_m) frames need to be measured, where K = 10 for full speed and K = 13 for high speed, f_s is the sampling frequency e.g. 48 kHz and f_cpu is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
-  // The update interval in the (4.10.2.1) Feedback Endpoint Descriptor must be less or equal to 2^(K - P), where P = min( ceil(log2(f_cpu / f_s)), K)
-  // Ff = n_cycles / n_frames * f_s / f_cpu in 16.16 format, where n_cycles are the number of CPU cycles within n_frames
+  // Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_m) frames need to be measured, where K = 10 for full speed and K = 13 for high speed, f_s is the sampling frequency e.g. 48 kHz and f_m is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
+  // The update interval in the (4.10.2.1) Feedback Endpoint Descriptor must be less or equal to 2^(K - P), where P = min( ceil(log2(f_m / f_s)), K)
+  // feedback = n_cycles / n_frames * f_s / f_m in 16.16 format, where n_cycles are the number of main clock cycles within fb_n_frames
 
   // Iterate over audio functions and set feedback value
   for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
+  {
+    audiod_function_t* audio = &_audiod_fct[i];
+
+    if (audio->ep_fb != 0)
     {
-      audiod_function_t* audio = &_audiod_fct[i];
-
-      if (audio->ep_fb != 0)
+      audio->fb_n_frames_current++;
+      if (audio->fb_n_frames_current == audio->fb_n_frames)
       {
-        audio->n_frames_current++;
-        if (audio->n_frames_current == audio->n_frames)
-        {
-          uint32_t n_cylces = *audio->feedback_param_p_cycle_count;
-          uint32_t feedback;
+        uint32_t n_cylces = *audio->fb_param_p_cycle_count;
+        uint32_t feedback;
 
-          if (audio->feedback_param_factor_N.i == 0)
-          {
-            // Power of two shift
-            feedback = n_cylces << audio->feedback_param_factor_D;
-          }
-          else
-          {
-            if (audio->feedback_param_factor_D == 0)
-            {
-              // Float computation
-              feedback = (uint32_t)(n_cylces * audio->feedback_param_factor_N.f);
-            }
-            else
-            {
-              // Fixed point computation
-              feedback = ((n_cylces - audio->n_cycles_old) << 3) * audio->feedback_param_factor_N.i / audio->feedback_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
-            }
-          }
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT
+        feedback = (n_cylces - audio->fb_n_cycles_old) << audio->fb_power_of_two_val;
+#endif
 
-          tud_audio_n_fb_set(i, feedback);
-          audio->n_frames_current = 0;
-          audio->n_cycles_old = n_cylces;
-        }
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT
+        feedback = (uint32_t)((float)(n_cylces - audio->fb_n_cycles_old) * audio->fb_float_val);
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT
+        feedback = ((n_cylces - audio->fb_n_cycles_old) << 3) * audio->fb_param_factor_N / audio->fb_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
+#endif
+
+        tud_audio_n_fb_set(i, feedback);
+        audio->fb_n_frames_current = 0;
+        audio->fb_n_cycles_old = n_cylces;
       }
     }
+  }
 
 #endif
 }
@@ -2299,6 +2320,16 @@ static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id)
 // Currently, only AS interfaces with an EP (in or out) are supposed to be parsed for!
 static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * p_desc, uint8_t const * p_desc_end, uint8_t const as_itf)
 {
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
+  if (as_itf != audio->ep_in_as_intf_num && as_itf != audio->ep_out_as_intf_num) return;           // Abort, this interface has no EP, this driver does not support this currently
+#endif
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_EP_OUT
+  if (as_itf != audio->ep_in_as_intf_num) return;
+#endif
+#if !CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
+  if (as_itf != audio->ep_out_as_intf_num) return;
+#endif
+
   p_desc = tu_desc_next(p_desc);    // Exclude standard AS interface descriptor of current alternate interface descriptor
 
   while (p_desc < p_desc_end)
@@ -2309,16 +2340,6 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
     // Look for a Class-Specific AS Interface Descriptor(4.9.2) to verify format type and format and also to get number of physical channels
     if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_AS_GENERAL)
     {
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
-      if (as_itf != audio->ep_in_as_intf_num && as_itf != audio->ep_out_as_intf_num) break;           // Abort loop, this interface has no EP, this driver does not support this currently
-#endif
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_EP_OUT
-      if (as_itf != audio->ep_in_as_intf_num) break;
-#endif
-#if !CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
-      if (as_itf != audio->ep_out_as_intf_num) break;
-#endif
-
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
       if (as_itf == audio->ep_in_as_intf_num)
       {
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 3645bda46..f1bb084d6 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -196,6 +196,25 @@
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR    1                             // 0 or 1
 #endif
 
+// Feeback calculation mode
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT     1
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT                  2
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT            3
+
+#ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE
+#error You must tell the driver the feedback determination mode! Possible choices are: CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT, CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT, or CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT!
+#endif
+
+#ifdef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE
+#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT)
+#error Unknown CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE. Possible choices are: CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT, CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT, or CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT!
+#endif
+#endif
+
+#endif
+
 // Audio interrupt control EP size - disabled if 0
 #ifndef CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
 #define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN                     0                             // Audio interrupt control - if required - 6 Bytes according to UAC 2 specification (p. 74)
@@ -487,7 +506,14 @@ TU_ATTR_WEAK uint32_t tud_audio_n_get_fm_n_cycles_cb(uint8_t rhport, uint8_t ep_
 
 // f_m : Main clock frequency in Hz i.e. master clock to which sample clock is locked
 // f_s : Current sample rate in Hz
-bool tud_audio_set_feedback_params_fm_fs(uint8_t func_id, uint32_t f_m, uint32_t f_s, uint32_t * p_cycle_count, bool use_float);
+// p_cycle_count : Pointer to main clock cycle counter register where the current count can be read from (e.g. a timer register)
+
+// This function must be called from the user within the tud_audio_set_itf_cb(rhport, p_request) callback function, where p_request needs to be checked as
+// uint8_t const itf = tu_u16_low(p_request->wIndex);
+// uint8_t const alt = tu_u16_low(p_request->wValue);
+// such that tud_audio_set_fb_params() gets called with the parameters corresponding to the defined interface and alternate setting
+// Also, start the main clock cycle counter (or reset its value) within tud_audio_set_itf_cb()
+TU_ATTR_WEAK bool tud_audio_set_fb_params(uint8_t func_id, uint32_t f_m, uint32_t f_s, uint32_t * p_cycle_count);
 #endif
 
 #endif

From 5aba4642707e8885b9d10837ac60fb0724d3503f Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Sun, 20 Mar 2022 12:04:10 +0100
Subject: [PATCH 0932/2085] Add magic checks

---
 src/class/audio/audio_device.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index b97155823..386e0ba21 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2116,6 +2116,16 @@ void audiod_sof (uint8_t rhport, uint32_t frame_count)
         feedback = ((n_cylces - audio->fb_n_cycles_old) << 3) * audio->fb_param_factor_N / audio->fb_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
 #endif
 
+        // Buffer count checks ?
+
+        // Magic checks
+        if (feedback > 2949166){        // 45.0007 in 16.16 format
+          feedback = 2949166;
+        }
+        if ( feedback < 2883630) {      // 44.0007 in 16.16 format
+          feedback = 2883630;
+        }
+
         tud_audio_n_fb_set(i, feedback);
         audio->fb_n_frames_current = 0;
         audio->fb_n_cycles_old = n_cylces;

From 8ffdbfebce56c709b1c2c2396498e9fc32555a77 Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Sun, 20 Mar 2022 12:08:27 +0100
Subject: [PATCH 0933/2085] Streamline call of tud_audio_set_itf_cb() within
 audiod_set_interface()

---
 src/class/audio/audio_device.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 386e0ba21..434bfdcc6 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1631,7 +1631,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
 #endif
             // Invoke callback - can be used to trigger data sampling if not already running
-            if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+//            if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
 
             // Schedule first transmit if alternate interface is not zero i.e. streaming is disabled - in case no sample data is available a ZLP is loaded
             // It is necessary to trigger this here since the refill is done with an RX FIFO empty interrupt which can only trigger if something was in there
@@ -1665,10 +1665,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
             // In case of asynchronous EP, call Cb after ep_fb is set
-            if ( !(desc_ep->bmAttributes.sync == 0x01 && audio->ep_fb == 0) )
-            {
-              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
-            }
+//            if ( !(desc_ep->bmAttributes.sync == 0x01 && audio->ep_fb == 0) )
+//            {
+//              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+//            }
 #else
             // Invoke callback
             if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
@@ -1693,11 +1693,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             audio->fb_n_cycles_old = 0;
 #endif
 
-            // Invoke callback after ep_out is set
-            if (audio->ep_out != 0)
-            {
-              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
-            }
+//            // Invoke callback after ep_out is set
+//            if (audio->ep_out != 0)
+//            {
+//              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+//            }
           }
 #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -1709,6 +1709,9 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
       TU_VERIFY(foundEPs == nEps);
 
+      // Invoke one callback for a final set interface
+      if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+
       // We are done - abort loop
       break;
     }
@@ -2118,7 +2121,7 @@ void audiod_sof (uint8_t rhport, uint32_t frame_count)
 
         // Buffer count checks ?
 
-        // Magic checks
+        // Magic checks - where are they from?
         if (feedback > 2949166){        // 45.0007 in 16.16 format
           feedback = 2949166;
         }

From 5cd67baf15aa24c5f5eae18b9f9615e3af807704 Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Sun, 20 Mar 2022 12:57:53 +0100
Subject: [PATCH 0934/2085] Disable SOF ISR feedback calcuation by default s.t.
 examples still work

---
 src/class/audio/audio_device.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index f1bb084d6..e5eaed9c7 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -193,7 +193,7 @@
 
 // Determine feedback value within SOF ISR within audio driver - if disabled the user has to call tud_audio_n_fb_set() with a suitable feedback value on its own. If done within audio driver SOF ISR, tud_audio_n_fb_set() is disabled for user
 #ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR    1                             // 0 or 1
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR    0                             // 0 or 1
 #endif
 
 // Feeback calculation mode

From fccbcfc88977ebdfb1448f6787cb052cfa949788 Mon Sep 17 00:00:00 2001
From: Greg Davill <greg.davill@gmail.com>
Date: Mon, 21 Mar 2022 10:01:11 +1030
Subject: [PATCH 0935/2085] Add WCH CH32V307 port

Add WCH mcu submodule
Add CH32V307V-R1-1v0 bsp
---
 .gitmodules                                   |   3 +
 .../ch32v307/boards/CH32V307V-R1-1v0/board.mk |   3 +
 .../boards/CH32V307V-R1-1v0/debug_uart.c      | 110 +++
 .../boards/CH32V307V-R1-1v0/debug_uart.h      |  31 +
 hw/bsp/ch32v307/ch32v30x_conf.h               |  43 +
 hw/bsp/ch32v307/ch32v30x_it.c                 |  49 ++
 hw/bsp/ch32v307/ch32v30x_it.h                 |  18 +
 hw/bsp/ch32v307/core_riscv.h                  | 384 +++++++++
 hw/bsp/ch32v307/family.c                      | 160 ++++
 hw/bsp/ch32v307/family.mk                     |  62 ++
 hw/bsp/ch32v307/system_ch32v30x.c             | 776 ++++++++++++++++++
 hw/bsp/ch32v307/system_ch32v30x.h             |  30 +
 hw/mcu/wch/ch32v307                           |   1 +
 src/common/tusb_mcu.h                         |   4 +
 .../wch/ch32v307/usb_ch32_usbhs_reg.h         | 345 ++++++++
 src/portable/wch/ch32v307/usb_dc_usbhs.c      | 388 +++++++++
 src/tusb_option.h                             |   3 +
 17 files changed, 2410 insertions(+)
 create mode 100644 hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk
 create mode 100644 hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c
 create mode 100644 hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h
 create mode 100644 hw/bsp/ch32v307/ch32v30x_conf.h
 create mode 100644 hw/bsp/ch32v307/ch32v30x_it.c
 create mode 100644 hw/bsp/ch32v307/ch32v30x_it.h
 create mode 100644 hw/bsp/ch32v307/core_riscv.h
 create mode 100644 hw/bsp/ch32v307/family.c
 create mode 100644 hw/bsp/ch32v307/family.mk
 create mode 100644 hw/bsp/ch32v307/system_ch32v30x.c
 create mode 100644 hw/bsp/ch32v307/system_ch32v30x.h
 create mode 160000 hw/mcu/wch/ch32v307
 create mode 100644 src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h
 create mode 100644 src/portable/wch/ch32v307/usb_dc_usbhs.c

diff --git a/.gitmodules b/.gitmodules
index 21bbf08c0..fd2b75cb8 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -146,3 +146,6 @@
 [submodule "hw/mcu/allwinner"]
 	path = hw/mcu/allwinner
 	url = https://github.com/hathach/allwinner_driver.git
+[submodule "hw/mcu/wch/ch32v307"]
+	path = hw/mcu/wch/ch32v307
+	url = https://github.com/openwch/ch32v307.git
diff --git a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk
new file mode 100644
index 000000000..f71def2c7
--- /dev/null
+++ b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk
@@ -0,0 +1,3 @@
+LINKER_SCRIPTS = $(CH32V307_SDK_SRC)/Ld
+
+LD_FILE = $(LINKER_SCRIPTS)/Link.ld # CH32V307
diff --git a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c
new file mode 100644
index 000000000..416782d0e
--- /dev/null
+++ b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c
@@ -0,0 +1,110 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "debug_uart.h"
+#include <ch32v30x.h>
+
+
+#define UART_RINGBUFFER_SIZE_TX 64
+#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
+
+static char tx_buf[UART_RINGBUFFER_SIZE_TX];
+static unsigned int tx_produce;
+static volatile unsigned int tx_consume;
+
+void USART1_IRQHandler(void) __attribute__((naked));
+void USART1_IRQHandler(void) { 
+      __asm volatile ("call USART1_IRQHandler_impl; mret");
+}
+
+__attribute__((used)) void USART1_IRQHandler_impl(void)
+{
+	if(USART_GetITStatus(USART1, USART_IT_TC) != RESET)
+    {
+        USART_ClearITPendingBit(USART1, USART_IT_TC);
+
+		if(tx_consume != tx_produce) {
+			USART_SendData(USART1, tx_buf[tx_consume]);
+			tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
+		}
+    }
+
+}
+
+void uart_write(char c)
+{
+	unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
+	
+    NVIC_DisableIRQ(USART1_IRQn);
+    if((tx_consume != tx_produce) || (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)) {
+		tx_buf[tx_produce] = c;
+		tx_produce = tx_produce_next;
+	} else {
+		USART_SendData(USART1, c);
+	}
+    NVIC_EnableIRQ(USART1_IRQn);
+}
+
+
+void uart_sync(void)
+{
+	while(tx_consume != tx_produce);
+}
+
+
+void USART_Printf_Init(uint32_t baudrate)
+{
+    GPIO_InitTypeDef  GPIO_InitStructure;
+    USART_InitTypeDef USART_InitStructure;
+
+	tx_produce = 0;
+	tx_consume = 0;
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    USART_InitStructure.USART_BaudRate = baudrate;
+    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    USART_InitStructure.USART_Parity = USART_Parity_No;
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Tx;
+
+    USART_Init(USART1, &USART_InitStructure);
+    USART_ITConfig(USART1, USART_IT_TC, ENABLE);
+    USART_Cmd(USART1, ENABLE);
+
+    NVIC_InitTypeDef  NVIC_InitStructure = {0};
+    NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
diff --git a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h
new file mode 100644
index 000000000..4348438bb
--- /dev/null
+++ b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h
@@ -0,0 +1,31 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdint.h>
+
+void uart_write(char c);
+void uart_sync(void);
+void USART_Printf_Init(uint32_t baudrate);
diff --git a/hw/bsp/ch32v307/ch32v30x_conf.h b/hw/bsp/ch32v307/ch32v30x_conf.h
new file mode 100644
index 000000000..399feaf68
--- /dev/null
+++ b/hw/bsp/ch32v307/ch32v30x_conf.h
@@ -0,0 +1,43 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_conf.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Library configuration file.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/ 
+#ifndef __CH32V30x_CONF_H
+#define __CH32V30x_CONF_H
+
+#include "ch32v30x_adc.h"
+#include "ch32v30x_bkp.h"
+#include "ch32v30x_can.h"
+#include "ch32v30x_crc.h"
+#include "ch32v30x_dac.h"
+#include "ch32v30x_dbgmcu.h"
+#include "ch32v30x_dma.h"
+#include "ch32v30x_exti.h"
+#include "ch32v30x_flash.h"
+#include "ch32v30x_fsmc.h"
+#include "ch32v30x_gpio.h"
+#include "ch32v30x_i2c.h"
+#include "ch32v30x_iwdg.h"
+#include "ch32v30x_pwr.h"
+#include "ch32v30x_rcc.h"
+#include "ch32v30x_rtc.h"
+#include "ch32v30x_sdio.h"
+#include "ch32v30x_spi.h"
+#include "ch32v30x_tim.h"
+#include "ch32v30x_usart.h"
+#include "ch32v30x_wwdg.h"
+#include "ch32v30x_it.h"
+#include "ch32v30x_misc.h"
+
+
+#endif /* __CH32V30x_CONF_H */
+
+
+	
+	
+	
diff --git a/hw/bsp/ch32v307/ch32v30x_it.c b/hw/bsp/ch32v307/ch32v30x_it.c
new file mode 100644
index 000000000..d348dd989
--- /dev/null
+++ b/hw/bsp/ch32v307/ch32v30x_it.c
@@ -0,0 +1,49 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Main Interrupt Service Routines.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#include "ch32v30x_it.h"
+
+void NMI_Handler(void) __attribute__((naked));
+void HardFault_Handler(void) __attribute__((naked));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handle(void){
+      __asm volatile ("call NMI_Handler_impl; mret");
+}
+
+__attribute__((used)) void NMI_Handler_impl(void)
+{
+
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void){
+      __asm volatile ("call HardFault_Handler_impl; mret");
+}
+
+__attribute__((used)) void HardFault_Handler_impl(void)
+{
+  while (1)
+  {
+  }
+}
+
+
diff --git a/hw/bsp/ch32v307/ch32v30x_it.h b/hw/bsp/ch32v307/ch32v30x_it.h
new file mode 100644
index 000000000..6475c5f11
--- /dev/null
+++ b/hw/bsp/ch32v307/ch32v30x_it.h
@@ -0,0 +1,18 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains the headers of the interrupt handlers.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CH32V30x_IT_H
+#define __CH32V30x_IT_H
+
+#include "debug.h"
+
+
+#endif /* __CH32V30x_IT_H */
+
+
diff --git a/hw/bsp/ch32v307/core_riscv.h b/hw/bsp/ch32v307/core_riscv.h
new file mode 100644
index 000000000..2e94ec683
--- /dev/null
+++ b/hw/bsp/ch32v307/core_riscv.h
@@ -0,0 +1,384 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : core_riscv.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : RISC-V Core Peripheral Access Layer Header File for CH32V30x
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __CORE_RISCV_H__
+#define __CORE_RISCV_H__
+
+/* IO definitions */
+#ifdef __cplusplus
+  #define     __I     volatile                /* defines 'read only' permissions */
+#else
+  #define     __I     volatile const          /* defines 'read only' permissions */
+#endif
+#define     __O     volatile                  /* defines 'write only' permissions */
+#define     __IO    volatile                  /* defines 'read / write' permissions */
+
+/* Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef __I uint64_t vuc64;  /* Read Only */
+typedef __I uint32_t vuc32;  /* Read Only */
+typedef __I uint16_t vuc16;  /* Read Only */
+typedef __I uint8_t vuc8;   /* Read Only */
+
+typedef const uint64_t uc64;  /* Read Only */
+typedef const uint32_t uc32;  /* Read Only */
+typedef const uint16_t uc16;  /* Read Only */
+typedef const uint8_t uc8;   /* Read Only */
+
+typedef __I int64_t vsc64;  /* Read Only */
+typedef __I int32_t vsc32;  /* Read Only */
+typedef __I int16_t vsc16;  /* Read Only */
+typedef __I int8_t vsc8;   /* Read Only */
+
+typedef const int64_t sc64;  /* Read Only */
+typedef const int32_t sc32;  /* Read Only */
+typedef const int16_t sc16;  /* Read Only */
+typedef const int8_t sc8;   /* Read Only */
+
+typedef __IO uint64_t  vu64;
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef uint64_t  u64;
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef __IO int64_t  vs64;
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef int64_t  s64;
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+#define   RV_STATIC_INLINE  static  inline
+
+/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
+typedef struct{
+  __I  uint32_t ISR[8];
+  __I  uint32_t IPR[8];
+  __IO uint32_t ITHRESDR;
+  __IO uint32_t RESERVED;
+  __IO uint32_t CFGR;
+  __I  uint32_t GISR;
+  uint8_t VTFIDR[4];
+  uint8_t RESERVED0[12];
+  __IO uint32_t VTFADDR[4];
+  uint8_t RESERVED1[0x90];
+  __O  uint32_t IENR[8];
+  uint8_t RESERVED2[0x60];
+  __O  uint32_t IRER[8];
+  uint8_t RESERVED3[0x60];
+  __O  uint32_t IPSR[8];
+  uint8_t RESERVED4[0x60];
+  __O  uint32_t IPRR[8];
+  uint8_t RESERVED5[0x60];
+  __IO uint32_t IACTR[8];
+  uint8_t RESERVED6[0xE0];
+  __IO uint8_t IPRIOR[256];
+  uint8_t RESERVED7[0x810];
+  __IO uint32_t SCTLR;
+}PFIC_Type;
+
+/* memory mapped structure for SysTick */
+typedef struct
+{
+    __IO u32 CTLR;
+    __IO u32 SR;
+    __IO u64 CNT;
+    __IO u64 CMP;
+}SysTick_Type;
+
+
+#define PFIC            ((PFIC_Type *) 0xE000E000 )
+#define NVIC            PFIC
+#define NVIC_KEY1       ((uint32_t)0xFA050000)
+#define	NVIC_KEY2				((uint32_t)0xBCAF0000)
+#define	NVIC_KEY3				((uint32_t)0xBEEF0000)
+
+#define SysTick         ((SysTick_Type *) 0xE000F000)
+
+
+/*********************************************************************
+ * @fn      __enable_irq
+ *
+ * @brief   Enable Global Interrupt
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __enable_irq(void)
+{
+  __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
+}
+
+/*********************************************************************
+ * @fn      __disable_irq
+ *
+ * @brief   Disable Global Interrupt
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __disable_irq(void)
+{
+  __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
+}
+
+/*********************************************************************
+ * @fn      __NOP
+ *
+ * @brief   nop
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __NOP(void)
+{
+  __asm volatile ("nop");
+}
+
+/*********************************************************************
+ * @fn      NVIC_EnableIRQ
+ *
+ * @brief   Enable Interrupt
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_DisableIRQ
+ *
+ * @brief   Disable Interrupt
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetStatusIRQ
+ *
+ * @brief   Get Interrupt Enable State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Enable
+ *          0 - Interrupt Disable
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetPendingIRQ
+ *
+ * @brief   Get Interrupt Pending State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Pending Enable
+ *          0 - Interrupt Pending Disable
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetPendingIRQ
+ *
+ * @brief   Set Interrupt Pending
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_ClearPendingIRQ
+ *
+ * @brief   Clear Interrupt Pending
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetActive
+ *
+ * @brief   Get Interrupt Active State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Active
+ *          0 - Interrupt No Active
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetPriority
+ *
+ * @brief   Set Interrupt Priority
+ *
+ * @param   IRQn - Interrupt Numbers
+ *          priority -
+ *              bit7 - pre-emption priority
+ *              bit6~bit4 - subpriority
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
+{
+  NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
+}
+
+/*********************************************************************
+ * @fn      __WFI
+ *
+ * @brief   Wait for Interrupt
+ *
+ * @return  None
+ */
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
+{
+  NVIC->SCTLR &= ~(1<<3);	// wfi
+  asm volatile ("wfi");
+}
+
+/*********************************************************************
+ * @fn      __WFE
+ *
+ * @brief   Wait for Events
+ *
+ * @return  None
+ */
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
+{
+  uint32_t t;
+
+  t = NVIC->SCTLR;
+  NVIC->SCTLR |= (1<<3)|(1<<5);		// (wfi->wfe)+(__sev)
+  NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
+  asm volatile ("wfi");
+  asm volatile ("wfi");
+}
+
+/*********************************************************************
+ * @fn      SetVTFIRQ
+ *
+ * @brief   Set VTF Interrupt
+ *
+ * @param   add - VTF interrupt service function base address.
+ *          IRQn -Interrupt Numbers
+ *          num - VTF Interrupt Numbers
+ *          NewState - DISABLE or ENABLE
+ * @return  None
+ */
+RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
+  if(num > 3)  return ;
+
+  if (NewState != DISABLE)
+  {
+      NVIC->VTFIDR[num] = IRQn;
+      NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
+  }
+  else{
+      NVIC->VTFIDR[num] = IRQn;
+      NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
+  }
+}
+
+/*********************************************************************
+ * @fn      NVIC_SystemReset
+ *
+ * @brief   Initiate a system reset request
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SystemReset(void)
+{
+  NVIC->CFGR = NVIC_KEY3|(1<<7);
+}
+
+
+/* Core_Exported_Functions */  
+extern uint32_t __get_FFLAGS(void);
+extern void __set_FFLAGS(uint32_t value);
+extern uint32_t __get_FRM(void);
+extern void __set_FRM(uint32_t value);
+extern uint32_t __get_FCSR(void);
+extern void __set_FCSR(uint32_t value);
+extern uint32_t __get_MSTATUS(void);
+extern void __set_MSTATUS(uint32_t value);
+extern uint32_t __get_MISA(void);
+extern void __set_MISA(uint32_t value);
+extern uint32_t __get_MIE(void);
+extern void __set_MIE(uint32_t value);
+extern uint32_t __get_MTVEC(void);
+extern void __set_MTVEC(uint32_t value);
+extern uint32_t __get_MSCRATCH(void);
+extern void __set_MSCRATCH(uint32_t value);
+extern uint32_t __get_MEPC(void);
+extern void __set_MEPC(uint32_t value);
+extern uint32_t __get_MCAUSE(void);
+extern void __set_MCAUSE(uint32_t value);
+extern uint32_t __get_MTVAL(void);
+extern void __set_MTVAL(uint32_t value);
+extern uint32_t __get_MIP(void);
+extern void __set_MIP(uint32_t value);
+extern uint32_t __get_MCYCLE(void);
+extern void __set_MCYCLE(uint32_t value);
+extern uint32_t __get_MCYCLEH(void);
+extern void __set_MCYCLEH(uint32_t value);
+extern uint32_t __get_MINSTRET(void);
+extern void __set_MINSTRET(uint32_t value);
+extern uint32_t __get_MINSTRETH(void);
+extern void __set_MINSTRETH(uint32_t value);
+extern uint32_t __get_MVENDORID(void);
+extern uint32_t __get_MARCHID(void);
+extern uint32_t __get_MIMPID(void);
+extern uint32_t __get_MHARTID(void);
+extern uint32_t __get_SP(void);
+
+
+#endif
+
+
+
+
+
diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
new file mode 100644
index 000000000..ea1c252c4
--- /dev/null
+++ b/hw/bsp/ch32v307/family.c
@@ -0,0 +1,160 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stdio.h"
+#include "debug_uart.h"
+#include "ch32v30x.h"
+
+#include "../board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+
+void USBHS_IRQHandler(void) __attribute__((naked));
+void USBHS_IRQHandler(void) { 
+        __asm volatile ("call USBHS_IRQHandler_impl; mret");
+}
+
+__attribute__ ((used)) void USBHS_IRQHandler_impl(void) { 
+  tud_int_handler(0); 
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+uint32_t SysTick_Config(uint32_t ticks)
+{
+    NVIC_EnableIRQ(SysTicK_IRQn);
+    SysTick->CTLR=0;
+    SysTick->SR=0;
+    SysTick->CNT=0;
+    SysTick->CMP=ticks-1;
+    SysTick->CTLR=0xF;
+    return 0;
+}
+
+void board_init(void) {
+
+  /* Disable interrupts during init */
+  __disable_irq();
+
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+
+	USART_Printf_Init(115200);
+
+  RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
+  RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);
+  RCC_USBHSConfig(RCC_USBPLL_Div2);
+  RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M);
+  RCC_USBHSPHYPLLALIVEcmd(ENABLE);
+  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE);
+
+  GPIO_InitTypeDef GPIO_InitStructure = {0};
+
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+  /* Enable interrupts globaly */
+  __enable_irq();
+
+  board_delay(2);
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+
+volatile uint32_t system_ticks = 0;
+
+/* Small workaround to support HW stack save/restore */
+void SysTick_Handler(void) __attribute__((naked));
+void SysTick_Handler(void) { 
+      __asm volatile ("call SysTick_Handler_impl; mret");
+}
+
+__attribute__((used)) void SysTick_Handler_impl(void) { 
+  SysTick->SR=0;
+  system_ticks++;
+}
+
+uint32_t board_millis(void) { return system_ticks; }
+
+#endif
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state) {
+  (void) state;
+
+  GPIO_WriteBit(GPIOC, GPIO_Pin_0, state);
+}
+
+uint32_t board_button_read(void) {
+  return false;
+}
+
+int board_uart_read(uint8_t* buf, int len) {
+  (void)buf;
+  (void)len;
+  return 0;
+}
+
+int board_uart_write(void const* buf, int len) {
+  int txsize = len;
+  while (txsize--) {
+    uart_write(*(uint8_t const*)buf);
+    buf++;
+  }
+  return len;
+}
+
+
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief  Reports the name of the source file and the source line number
+ *         where the assert_param error has occurred.
+ * @param  file: pointer to the source file name
+ * @param  line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(char* file, uint32_t line) {
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line
+     number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line)
+   */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
new file mode 100644
index 000000000..dfb4853d9
--- /dev/null
+++ b/hw/bsp/ch32v307/family.mk
@@ -0,0 +1,62 @@
+# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
+#CROSS_COMPILE ?= riscv32-unknown-elf-
+
+# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
+CROSS_COMPILE ?= riscv-none-embed-
+
+# Submodules
+CH32V307_SDK = hw/mcu/wch/ch32v307
+DEPS_SUBMODULES += $(CH32V307_SDK)
+
+# WCH-SDK paths
+CH32V307_SDK_SRC = $(CH32V307_SDK)/EVT/EXAM/SRC
+CH32V307_SDK_SRC_TOP = $(TOP)/$(CH32V307_SDK_SRC)
+CH32V307_STARTUP_ASM = $(CH32V307_SDK_SRC)/Startup
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+SKIP_NANOLIB = 1
+
+CFLAGS += \
+	-flto \
+	-march=rv32imac \
+	-mabi=ilp32 \
+	-msmall-data-limit=8 \
+	-mno-save-restore -Os \
+	-fmessage-length=0 \
+	-fsigned-char \
+	-ffunction-sections \
+	-fdata-sections \
+	-nostdlib -nostartfiles \
+	-DCFG_TUSB_MCU=OPT_MCU_CH32VF307 \
+	-Xlinker --gc-sections \
+    -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+
+LDFLAGS += \
+  -Xlinker --gc-sections --specs=nano.specs --specs=nosys.specs
+
+SRC_C += \
+	src/portable/wch/ch32v307/usb_dc_usbhs.c \
+	$(CH32V307_SDK_SRC_TOP)/Core/core_riscv.c \
+	$(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_gpio.c \
+	$(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_misc.c \
+	$(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_rcc.c \
+	$(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_usart.c 
+	
+SRC_S += \
+	$(CH32V307_STARTUP_ASM)/startup_ch32v30x_D8C.S 
+
+INC += \
+	src/portable/wch/ch32v307 \
+	$(TOP)/$(BOARD_PATH)/.. \
+	$(TOP)/$(BOARD_PATH) \
+	$(CH32V307_SDK_SRC_TOP)/Peripheral/inc \
+	$(CH32V307_SDK_SRC_TOP)/Debug \
+	$(CH32V307_SDK_SRC_TOP)
+
+# For freeRTOS port source
+FREERTOS_PORT = RISC-V
+
+# flash target ROM bootloader
+flash: $(BUILD)/$(PROJECT).elf
+	openocd -f wch-riscv.cfg  -c init -c halt  -c "program  $<  0x08000000"  -c reset -c exit
diff --git a/hw/bsp/ch32v307/system_ch32v30x.c b/hw/bsp/ch32v307/system_ch32v30x.c
new file mode 100644
index 000000000..12b18d7b8
--- /dev/null
+++ b/hw/bsp/ch32v307/system_ch32v30x.c
@@ -0,0 +1,776 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Source File.
+*                      For HSE = 8Mhz
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*********************************************************************************/
+#include "ch32v30x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+// #define SYSCLK_FREQ_HSE    HSE_VALUE
+/* #define SYSCLK_FREQ_24MHz  24000000  */ 
+//#define SYSCLK_FREQ_48MHz  48000000
+/* #define SYSCLK_FREQ_56MHz  56000000  */  
+//#define SYSCLK_FREQ_72MHz  72000000
+//#define SYSCLK_FREQ_96MHz  96000000
+//#define SYSCLK_FREQ_120MHz  120000000
+#define SYSCLK_FREQ_144MHz  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;          /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /* System Clock Frequency (Core Clock) */
+
+#elif defined SYSCLK_FREQ_96MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz;        /* System Clock Frequency (Core Clock) */
+
+#else /* HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;                /* System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+
+#elif defined SYSCLK_FREQ_96MHz
+  static void SetSysClockTo96(void);
+#elif defined SYSCLK_FREQ_120MHz
+  static void SetSysClockTo120(void);
+#elif defined SYSCLK_FREQ_144MHz
+  static void SetSysClockTo144(void);
+
+#endif
+
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+
+#ifdef CH32V30x_D8C
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR0 &= (uint32_t)0xF0FF0000;
+#endif 
+
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+
+#ifdef CH32V30x_D8C
+  RCC->CTLR &= (uint32_t)0xEBFFFFFF;
+  RCC->INTR = 0x00FF0000;
+  RCC->CFGR2 = 0x00000000;
+#else
+  RCC->INTR = 0x009F0000;   
+#endif   
+  SetSysClock();
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08: 
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC; 
+      pllmull = ( pllmull >> 18) + 2;
+
+#ifdef CH32V30x_D8
+          if(pllmull == 17) pllmull = 18;
+#else
+          if(pllmull == 2) pllmull = 18;
+          if(pllmull == 15){
+              pllmull = 13;  /* *6.5 */
+              Pll_6_5 = 1;
+          }
+          if(pllmull == 16) pllmull = 15;
+          if(pllmull == 17) pllmull = 16;
+#endif
+
+      if (pllsource == 0x00)
+      {
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {    
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+ 
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;  
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#elif defined SYSCLK_FREQ_96MHz
+  SetSysClockTo96();
+#elif defined SYSCLK_FREQ_120MHz
+  SetSysClockTo120();
+#elif defined SYSCLK_FREQ_144MHz
+  SetSysClockTo144();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+    */
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+        /* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_24MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo24
+ *
+ * @brief   Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN);
+#endif
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_48MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo48
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo56
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo72
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo96
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo120
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_144MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo144
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+#ifdef CH32V30x_D8
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+#else
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN);
+#endif
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#endif
diff --git a/hw/bsp/ch32v307/system_ch32v30x.h b/hw/bsp/ch32v307/system_ch32v30x.h
new file mode 100644
index 000000000..0e0ef4e51
--- /dev/null
+++ b/hw/bsp/ch32v307/system_ch32v30x.h
@@ -0,0 +1,30 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Header File.
+* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+* SPDX-License-Identifier: Apache-2.0
+*******************************************************************************/
+#ifndef __SYSTEM_CH32V30x_H 
+#define __SYSTEM_CH32V30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V30x_SYSTEM_H */
+
+
+
diff --git a/hw/mcu/wch/ch32v307 b/hw/mcu/wch/ch32v307
new file mode 160000
index 000000000..17761f5cf
--- /dev/null
+++ b/hw/mcu/wch/ch32v307
@@ -0,0 +1 @@
+Subproject commit 17761f5cf9dbbf2dcf665b7c04934188add20082
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 8eb4ad475..84d629eac 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -266,6 +266,10 @@
 #elif TU_CHECK_MCU(OPT_MCU_F1C100S)
   #define TUP_DCD_ENDPOINT_MAX    4
 
+//------------- WCH -------------//
+#elif TU_CHECK_MCU(OPT_MCU_CH32VF307)
+  #define TUP_DCD_ENDPOINT_MAX    8
+
 #endif
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h b/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h
new file mode 100644
index 000000000..1b7c0e791
--- /dev/null
+++ b/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h
@@ -0,0 +1,345 @@
+#ifndef _USB_CH32_USBHS_REG_H
+#define _USB_CH32_USBHS_REG_H
+
+#include <ch32v30x.h>
+
+/******************* GLOBAL ******************/
+
+// USB CONTROL
+#define USBHS_CONTROL_OFFSET 0x00
+#define USBHS_DMA_EN         (1 << 0)
+#define USBHS_ALL_CLR        (1 << 1)
+#define USBHS_FORCE_RST      (1 << 2)
+#define USBHS_INT_BUSY_EN    (1 << 3)
+#define USBHS_DEV_PU_EN      (1 << 4)
+#define USBHS_SPEED_MASK     (3 << 5)
+#define USBHS_FULL_SPEED     (0 << 5)
+#define USBHS_HIGH_SPEED     (1 << 5)
+#define USBHS_LOW_SPEED      (2 << 5)
+#define USBHS_HOST_MODE      (1 << 7)
+
+// USB_INT_EN
+#define USBHS_INT_EN_OFFSET 0x02
+#define USBHS_BUS_RST_EN    (1 << 0)
+#define USBHS_DETECT_EN     (1 << 0)
+#define USBHS_TRANSFER_EN   (1 << 1)
+#define USBHS_SUSPEND_EN    (1 << 2)
+#define USBHS_SOF_ACT_EN    (1 << 3)
+#define USBHS_FIFO_OV_EN    (1 << 4)
+#define USBHS_SETUP_ACT_EN  (1 << 5)
+#define USBHS_ISO_ACT_EN    (1 << 6)
+#define USBHS_DEV_NAK_EN    (1 << 7)
+
+// USB DEV AD
+#define USBHS_DEV_AD_OFFSET 0x03
+// USB FRAME_NO
+#define USBHS_FRAME_NO_OFFSET 0x04
+// USB SUSPEND
+#define USBHS_SUSPEND_OFFSET    0x06
+#define USBHS_DEV_REMOTE_WAKEUP (1 << 2)
+#define USBHS_LINESTATE_MASK    (2 << 4) /* Read Only */
+
+// RESERVED0
+
+// USB SPEED TYPE
+#define USBHS_SPEED_TYPE_OFFSET 0x08
+#define USBSPEED_MASK           (0x03)
+
+// USB_MIS_ST
+#define USBHS_MIS_ST_OFFSET 0x09
+#define USBHS_SPLIT_CAN     (1 << 0)
+#define USBHS_ATTACH        (1 << 1)
+#define USBHS_SUSPEND       (1 << 2)
+#define USBHS_BUS_RESET     (1 << 3)
+#define USBHS_R_FIFO_RDY    (1 << 4)
+#define USBHS_SIE_FREE      (1 << 5)
+#define USBHS_SOF_ACT       (1 << 6)
+#define USBHS_SOF_PRES      (1 << 7)
+
+// INT_FLAG
+#define USBHS_INT_FLAG_OFFSET 0x0A
+#define USBHS_BUS_RST_FLAG    (1 << 0)
+#define USBHS_DETECT_FLAG     (1 << 0)
+#define USBHS_TRANSFER_FLAG   (1 << 1)
+#define USBHS_SUSPEND_FLAG    (1 << 2)
+#define USBHS_HST_SOF_FLAG    (1 << 3)
+#define USBHS_FIFO_OV_FLAG    (1 << 4)
+#define USBHS_SETUP_FLAG      (1 << 5)
+#define USBHS_ISO_ACT_FLAG    (1 << 6)
+
+// INT_ST
+#define USBHS_INT_ST_OFFSET  0x0B
+#define USBHS_DEV_UIS_IS_NAK (1 << 7)
+#define USBHS_DEV_UIS_TOG_OK (1 << 6)
+#define MASK_UIS_TOKEN       (3 << 4)
+#define MASK_UIS_ENDP        (0x0F)
+#define MASK_UIS_H_RES       (0x0F)
+
+#define USBHS_TOGGLE_OK (0x40)
+#define USBHS_HOST_RES  (0x0f)
+
+//USB_RX_LEN
+#define USBHS_RX_LEN_OFFSET 0x0C
+/******************* DEVICE ******************/
+
+//UEP_CONFIG
+#define USBHS_UEP_CONFIG_OFFSET 0x10
+#define USBHS_EP0_T_EN          (1 << 0)
+#define USBHS_EP0_R_EN          (1 << 16)
+
+#define USBHS_EP1_T_EN (1 << 1)
+#define USBHS_EP1_R_EN (1 << 17)
+
+#define USBHS_EP2_T_EN (1 << 2)
+#define USBHS_EP2_R_EN (1 << 18)
+
+#define USBHS_EP3_T_EN (1 << 3)
+#define USBHS_EP3_R_EN (1 << 19)
+
+#define USBHS_EP4_T_EN (1 << 4)
+#define USBHS_EP4_R_EN (1 << 20)
+
+#define USBHS_EP5_T_EN (1 << 5)
+#define USBHS_EP5_R_EN (1 << 21)
+
+#define USBHS_EP6_T_EN (1 << 6)
+#define USBHS_EP6_R_EN (1 << 22)
+
+#define USBHS_EP7_T_EN (1 << 7)
+#define USBHS_EP7_R_EN (1 << 23)
+
+#define USBHS_EP8_T_EN (1 << 8)
+#define USBHS_EP8_R_EN (1 << 24)
+
+#define USBHS_EP9_T_EN (1 << 9)
+#define USBHS_EP9_R_EN (1 << 25)
+
+#define USBHS_EP10_T_EN (1 << 10)
+#define USBHS_EP10_R_EN (1 << 26)
+
+#define USBHS_EP11_T_EN (1 << 11)
+#define USBHS_EP11_R_EN (1 << 27)
+
+#define USBHS_EP12_T_EN (1 << 12)
+#define USBHS_EP12_R_EN (1 << 28)
+
+#define USBHS_EP13_T_EN (1 << 13)
+#define USBHS_EP13_R_EN (1 << 29)
+
+#define USBHS_EP14_T_EN (1 << 14)
+#define USBHS_EP14_R_EN (1 << 30)
+
+#define USBHS_EP15_T_EN (1 << 15)
+#define USBHS_EP15_R_EN (1 << 31)
+
+//UEP_TYPE
+#define USBHS_UEP_TYPE_OFFSET 0x14
+#define USBHS_EP0_T_TYP       (1 << 0)
+#define USBHS_EP0_R_TYP       (1 << 16)
+
+#define USBHS_EP1_T_TYP (1 << 1)
+#define USBHS_EP1_R_TYP (1 << 17)
+
+#define USBHS_EP2_T_TYP (1 << 2)
+#define USBHS_EP2_R_TYP (1 << 18)
+
+#define USBHS_EP3_T_TYP (1 << 3)
+#define USBHS_EP3_R_TYP (1 << 19)
+
+#define USBHS_EP4_T_TYP (1 << 4)
+#define USBHS_EP4_R_TYP (1 << 20)
+
+#define USBHS_EP5_T_TYP (1 << 5)
+#define USBHS_EP5_R_TYP (1 << 21)
+
+#define USBHS_EP6_T_TYP (1 << 6)
+#define USBHS_EP6_R_TYP (1 << 22)
+
+#define USBHS_EP7_T_TYP (1 << 7)
+#define USBHS_EP7_R_TYP (1 << 23)
+
+#define USBHS_EP8_T_TYP (1 << 8)
+#define USBHS_EP8_R_TYP (1 << 24)
+
+#define USBHS_EP9_T_TYP (1 << 8)
+#define USBHS_EP9_R_TYP (1 << 25)
+
+#define USBHS_EP10_T_TYP (1 << 10)
+#define USBHS_EP10_R_TYP (1 << 26)
+
+#define USBHS_EP11_T_TYP (1 << 11)
+#define USBHS_EP11_R_TYP (1 << 27)
+
+#define USBHS_EP12_T_TYP (1 << 12)
+#define USBHS_EP12_R_TYP (1 << 28)
+
+#define USBHS_EP13_T_TYP (1 << 13)
+#define USBHS_EP13_R_TYP (1 << 29)
+
+#define USBHS_EP14_T_TYP (1 << 14)
+#define USBHS_EP14_R_TYP (1 << 30)
+
+#define USBHS_EP15_T_TYP (1 << 15)
+#define USBHS_EP15_R_TYP (1 << 31)
+
+/* BUF_MOD UEP1~15 */
+#define USBHS_BUF_MOD_OFFSET  0x18
+#define USBHS_EP0_BUF_MOD     (1 << 0)
+#define USBHS_EP0_ISO_BUF_MOD (1 << 16)
+
+#define USBHS_EP1_BUF_MOD     (1 << 1)
+#define USBHS_EP1_ISO_BUF_MOD (1 << 17)
+
+#define USBHS_EP2_BUF_MOD     (1 << 2)
+#define USBHS_EP2_ISO_BUF_MOD (1 << 18)
+
+#define USBHS_EP3_BUF_MOD     (1 << 3)
+#define USBHS_EP3_ISO_BUF_MOD (1 << 19)
+
+#define USBHS_EP4_BUF_MOD     (1 << 4)
+#define USBHS_EP4_ISO_BUF_MOD (1 << 20)
+
+#define USBHS_EP5_BUF_MOD     (1 << 5)
+#define USBHS_EP5_ISO_BUF_MOD (1 << 21)
+
+#define USBHS_EP6_BUF_MOD     (1 << 6)
+#define USBHS_EP6_ISO_BUF_MOD (1 << 22)
+
+#define USBHS_EP7_BUF_MOD     (1 << 7)
+#define USBHS_EP7_ISO_BUF_MOD (1 << 23)
+
+#define USBHS_EP8_BUF_MOD     (1 << 8)
+#define USBHS_EP8_ISO_BUF_MOD (1 << 24)
+
+#define USBHS_EP9_BUF_MOD     (1 << 9)
+#define USBHS_EP9_ISO_BUF_MOD (1 << 25)
+
+#define USBHS_EP10_BUF_MOD     (1 << 10)
+#define USBHS_EP10_ISO_BUF_MOD (1 << 26)
+
+#define USBHS_EP11_BUF_MOD     (1 << 11)
+#define USBHS_EP11_ISO_BUF_MOD (1 << 27)
+
+#define USBHS_EP12_BUF_MOD     (1 << 12)
+#define USBHS_EP12_ISO_BUF_MOD (1 << 28)
+
+#define USBHS_EP13_BUF_MOD     (1 << 13)
+#define USBHS_EP13_ISO_BUF_MOD (1 << 29)
+
+#define USBHS_EP14_BUF_MOD     (1 << 14)
+#define USBHS_EP14_ISO_BUF_MOD (1 << 30)
+
+#define USBHS_EP15_BUF_MOD     (1 << 15)
+#define USBHS_EP15_ISO_BUF_MOD (1 << 31)
+//USBHS_EPn_T_EN  USBHS_EPn_R_EN  USBHS_EPn_BUF_MOD  锟斤拷锟斤拷锟斤拷锟斤拷UEPn_DMA为锟斤拷始锟斤拷�锟缴碉拷锟斤拷锟斤拷锟斤拷锟�
+//      0               0               x            锟剿点被锟斤拷锟矫�拷未锟矫碉拷UEPn_*_DMA锟斤拷锟斤拷锟斤拷锟斤拷
+//      1               0               0            锟斤拷锟秸�拷OUT锟斤拷锟斤拷锟斤拷锟斤拷锟阶碉拷�为UEPn_RX_DMA
+//      1               0               1            bUEPn_RX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA锟斤拷bUEPn_RX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA
+//      0               1               0            锟斤拷锟斤拷(IN)锟斤拷锟斤拷锟斤拷锟阶碉拷�为UEPn_TX_DMA锟斤拷
+//      0               1               1            bUEPn_TX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA锟斤拷bUEPn_TX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA
+
+/* USB0_DMA */
+#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address
+
+/* USBX_RX_DMA */
+#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address
+
+#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address
+
+#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address
+
+#define USBHS_UEPx_T_LEN_OFFSET(n)   (0xD8 + 4 * (n)) // endpoint x DMA buffer address
+#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address
+#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address
+
+// UEPn_T_LEN
+#define USBHS_EP_T_LEN_MASK (0x7FF)
+
+//UEPn_TX_CTRL
+#define USBHS_EP_T_RES_MASK  (3 << 0)
+#define USBHS_EP_T_RES_ACK   (0 << 0)
+#define USBHS_EP_T_RES_NYET  (1 << 0)
+#define USBHS_EP_T_RES_NAK   (2 << 0)
+#define USBHS_EP_T_RES_STALL (3 << 0)
+
+#define USBHS_EP_T_TOG_MASK (3 << 3)
+#define USBHS_EP_T_TOG_0    (0 << 3)
+#define USBHS_EP_T_TOG_1    (1 << 3)
+#define USBHS_EP_T_TOG_2    (2 << 3)
+#define USBHS_EP_T_TOG_M    (3 << 3)
+
+#define USBHS_EP_T_AUTOTOG (1 << 5)
+
+//UEPn_RX_CTRL
+#define USBHS_EP_R_RES_MASK  (3 << 0)
+#define USBHS_EP_R_RES_ACK   (0 << 0)
+#define USBHS_EP_R_RES_NYET  (1 << 0)
+#define USBHS_EP_R_RES_NAK   (2 << 0)
+#define USBHS_EP_R_RES_STALL (3 << 0)
+
+#define USBHS_EP_R_TOG_MASK (3 << 3)
+#define USBHS_EP_R_TOG_0    (0 << 3)
+#define USBHS_EP_R_TOG_1    (1 << 3)
+#define USBHS_EP_R_TOG_2    (2 << 3)
+#define USBHS_EP_R_TOG_M    (3 << 3)
+
+#define USBHS_EP_R_AUTOTOG (1 << 5)
+
+#define USBHS_TOG_MATCH (1 << 6)
+
+/******************* HOST ******************/
+// USB HOST_CTRL
+#define USBHS_SEND_BUS_RESET   (1 << 0)
+#define USBHS_SEND_BUS_SUSPEND (1 << 1)
+#define USBHS_SEND_BUS_RESUME  (1 << 2)
+#define USBHS_REMOTE_WAKE      (1 << 3)
+#define USBHS_PHY_SUSPENDM     (1 << 4)
+#define USBHS_UH_SOFT_FREE     (1 << 6)
+#define USBHS_SEND_SOF_EN      (1 << 7)
+
+//UH_CONFIG
+#define USBHS_HOST_TX_EN (1 << 3)
+#define USBHS_HOST_RX_EN (1 << 18)
+
+// HOST_EP_TYPE
+#define USBHS_ENDP_TX_ISO (1 << 3)
+#define USBHS_ENDP_RX_ISO (1 << (16 + 2))
+
+// R32_UH_EP_PID
+#define USBHS_HOST_MASK_TOKEN (0x0f)
+#define USBHS_HOST_MASK_ENDP  (0x0f << 4)
+
+//R8_UH_RX_CTRL
+#define USBHS_EP_R_RES_MASK  (3 << 0)
+#define USBHS_EP_R_RES_ACK   (0 << 0)
+#define USBHS_EP_R_RES_NYET  (1 << 0)
+#define USBHS_EP_R_RES_NAK   (2 << 0)
+#define USBHS_EP_R_RES_STALL (3 << 0)
+
+#define USBHS_UH_R_RES_NO   (1 << 2)
+#define USBHS_UH_R_TOG_1    (1 << 3)
+#define USBHS_UH_R_TOG_2    (2 << 3)
+#define USBHS_UH_R_TOG_3    (3 << 3)
+#define USBHS_UH_R_TOG_AUTO (1 << 5)
+#define USBHS_UH_R_DATA_NO  (1 << 6)
+//R8_UH_TX_CTRL
+#define USBHS_UH_T_RES_MASK  (3 << 0)
+#define USBHS_UH_T_RES_ACK   (0 << 0)
+#define USBHS_UH_T_RES_NYET  (1 << 0)
+#define USBHS_UH_T_RES_NAK   (2 << 0)
+#define USBHS_UH_T_RES_STALL (3 << 0)
+
+#define USBHS_UH_T_RES_NO   (1 << 2)
+#define USBHS_UH_T_TOG_1    (1 << 3)
+#define USBHS_UH_T_TOG_2    (2 << 3)
+#define USBHS_UH_T_TOG_3    (3 << 3)
+#define USBHS_UH_T_TOG_AUTO (1 << 5)
+#define USBHS_UH_T_DATA_NO  (1 << 6)
+
+// 00: OUT, 01:SOF, 10:IN, 11:SETUP
+#define PID_OUT   0
+#define PID_SOF   1
+#define PID_IN    2
+#define PID_SETUP 3
+
+#endif
diff --git a/src/portable/wch/ch32v307/usb_dc_usbhs.c b/src/portable/wch/ch32v307/usb_dc_usbhs.c
new file mode 100644
index 000000000..32645dc5f
--- /dev/null
+++ b/src/portable/wch/ch32v307/usb_dc_usbhs.c
@@ -0,0 +1,388 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Greg Davill 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32VF307)
+#include "device/dcd.h"
+
+#include "usb_ch32_usbhs_reg.h"
+#include "core_riscv.h"
+
+// Max number of bi-directional endpoints including EP0
+#define EP_MAX 16
+
+typedef struct {
+    uint8_t *buffer;
+    // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API
+    uint16_t total_len;
+    uint16_t queued_len;
+    uint16_t max_size;
+    bool short_packet;
+} xfer_ctl_t;
+
+#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
+static xfer_ctl_t xfer_status[EP_MAX][2];
+
+#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2)
+#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4)
+#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4)
+#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2)
+
+#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1))
+#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1))
+
+/* Endpoint Buffer */
+__attribute__((aligned(4))) uint8_t setup[8];           // ep0(64)
+__attribute__((aligned(4))) uint8_t EP0_DatabufHD[64];  // ep0(64)
+
+volatile uint8_t mps_over_flag = 0;
+volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01;
+
+void dcd_init(uint8_t rhport) {
+    (void)rhport;
+
+    memset(&xfer_status, 0, sizeof(xfer_status));
+
+    // usb_dc_low_level_init();
+
+    USBHSD->HOST_CTRL = 0x00;
+    USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM;
+
+    USBHSD->CONTROL = 0;
+#if 1
+    USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
+#else
+    USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED;
+#endif
+
+    USBHSD->INT_EN = 0;
+    USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN;
+
+    /* ALL endpoint enable */
+    USBHSD->ENDP_CONFIG = 0xffffffff;
+
+    USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
+    USBHSD->ENDP_TYPE = 0x00;
+    USBHSD->BUF_MODE = 0x00;
+
+    USBHSD->UEP0_MAX_LEN = 64;
+
+    USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD;
+
+    USBHSD->UEP0_TX_LEN = 0;
+    USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK;
+    USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
+
+    for (int ep = 1; ep < EP_MAX; ep++) {
+        EP_TX_LEN(ep) = 0;
+        EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK;
+        EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
+
+        EP_RX_MAX_LEN(ep) = 512;
+    }
+
+    USBHSD->DEV_AD = 0;
+    USBHSD->CONTROL |= USBHS_DEV_PU_EN;
+}
+
+void dcd_int_enable(uint8_t rhport) {
+    (void)rhport;
+
+    NVIC_EnableIRQ(USBHS_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport) {
+    (void)rhport;
+
+    NVIC_DisableIRQ(USBHS_IRQn);
+}
+
+void dcd_edpt_close_all(uint8_t rhport) {
+    (void)rhport;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+    (void)dev_addr;
+
+    // Response with zlp status
+    dcd_edpt_xfer(rhport, 0x80, NULL, 0);
+}
+
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
+    (void)rhport;
+
+    if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+        request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+        request->bRequest == TUSB_REQ_SET_ADDRESS) {
+        USBHSD->DEV_AD = (uint8_t)request->wValue;
+    }
+
+    EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK;
+    EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK;
+}
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) {
+    (void)rhport;
+
+    uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
+    uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
+
+    TU_ASSERT(epnum < EP_MAX);
+
+    xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
+    xfer->max_size = tu_edpt_packet_size(desc_edpt);
+
+    if (epnum != 0) {
+        if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) {
+            EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK;
+        } else {
+            EP_TX_LEN(epnum) = 0;
+            EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
+        }
+    }
+
+    return true;
+}
+
+int usbd_ep_close(const uint8_t ep) {
+    (void)ep;
+
+    return 0;
+}
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+    (void)rhport;
+
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    uint8_t const dir = tu_edpt_dir(ep_addr);
+
+    if (epnum == 0) {
+        if (dir == TUSB_DIR_OUT) {
+            USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL;
+        } else {
+            USBHSD->UEP0_TX_LEN = 0;
+            USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL;
+        }
+    } else {
+        if (dir == TUSB_DIR_OUT) {
+            EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL;
+
+        } else {
+            EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL;
+        }
+    }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+    (void)rhport;
+
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    uint8_t const dir = tu_edpt_dir(ep_addr);
+
+    if (epnum == 0) {
+        if (dir == TUSB_DIR_OUT) {
+            USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
+        } else {
+        }
+    } else {
+        if (dir == TUSB_DIR_OUT) {
+            EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK;
+
+        } else {
+            EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK;
+        }
+    }
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) {
+    (void)rhport;
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    uint8_t const dir = tu_edpt_dir(ep_addr);
+
+    xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
+    xfer->buffer = buffer;
+    // xfer->ff           = NULL; // TODO support dcd_edpt_xfer_fifo API
+    xfer->total_len = total_bytes;
+    xfer->queued_len = 0;
+    xfer->short_packet = false;
+
+    // uint16_t num_packets = (total_bytes / xfer->max_size);
+    uint16_t short_packet_size = total_bytes % (xfer->max_size + 1);
+
+    // Zero-size packet is special case.
+    if (short_packet_size == 0 || (total_bytes == 0)) {
+        xfer->short_packet = true;
+    }
+
+    if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
+        if (!total_bytes) {
+            xfer->short_packet = true;
+            if (epnum == 0) {
+                USBHSD->UEP0_TX_LEN = 0;
+                USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
+                USBHS_Dev_Endp0_Tog ^= 1;
+            } else {
+                EP_TX_LEN(epnum) = 0;
+                EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
+            }
+        } else {
+            if (epnum == 0) {
+                xfer->queued_len += short_packet_size;
+                memcpy(&EP0_DatabufHD[0], buffer, short_packet_size);
+
+                USBHSD->UEP0_TX_LEN = short_packet_size;
+                USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
+                USBHS_Dev_Endp0_Tog ^= 1;
+            } else {
+                xfer->queued_len += short_packet_size;
+                
+                EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer;
+                USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum);
+                EP_TX_LEN(epnum) = short_packet_size;
+                EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
+            }
+        }
+    } else { /* TUSB_DIR_OUT */
+        if (epnum == 0) {
+            uint32_t read_count = USBHSD->RX_LEN;
+            read_count = TU_MIN(read_count, total_bytes);
+
+            if ((total_bytes == 8)) {
+                read_count = 8;
+                memcpy(buffer, &EP0_DatabufHD[0], 8);
+            } else {
+                memcpy(buffer, &EP0_DatabufHD[0], read_count);
+            }
+        } else {
+            EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer;
+            USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum);
+        }
+
+        // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes);
+    }
+    return true;
+}
+
+
+static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) {
+    // xfer->queued_len = xfer->total_len - remaining;
+
+    uint16_t remaining = xfer->total_len - xfer->queued_len;
+    uint16_t to_recv_size;
+
+    if (remaining <= xfer->max_size) {
+        // Avoid buffer overflow.
+        to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
+    } else {
+        // Room for full packet, choose recv_size based on what the microcontroller
+        // claims.
+        to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
+    }
+
+    if (to_recv_size) {
+    }
+
+    xfer->queued_len += xfer_size;
+
+    // Per USB spec, a short OUT packet (including length 0) is always
+    // indicative of the end of a transfer (at least for ctl, bulk, int).
+    xfer->short_packet = (xfer_size < xfer->max_size);
+}
+
+void dcd_int_handler(uint8_t rhport) {
+    (void)rhport;
+
+    uint32_t end_num, rx_token;
+    uint8_t intflag = 0;
+
+    intflag = USBHSD->INT_FG;
+
+    if (intflag & USBHS_TRANSFER_FLAG) {
+
+        end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP;
+        rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03;
+
+        uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0);
+
+        xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp));
+
+        if (rx_token == PID_OUT) {
+            uint16_t rx_len = USBHSD->RX_LEN;
+
+            receive_packet(xfer, rx_len);
+
+            if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
+                xfer->short_packet = false;
+
+                dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+            }
+
+            if (end_num == 0) {
+                USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
+            }
+
+        } else if (rx_token == PID_IN) {
+            if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
+                xfer->short_packet = false;
+                xfer->total_len = 0;
+                dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+
+                EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK;
+
+                if (end_num == 0) {
+                }
+            } else {
+                dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len);
+            }
+        }
+
+        USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */
+    } else if (intflag & USBHS_SETUP_FLAG) {
+        USBHS_Dev_Endp0_Tog = 1;
+        dcd_event_setup_received(0, EP0_DatabufHD, true);
+        
+        USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
+    } else if (intflag & USBHS_DETECT_FLAG) {
+        USBHS_Dev_Endp0_Tog = 1;
+
+        xfer_status[0][TUSB_DIR_OUT].max_size = 64;
+        xfer_status[0][TUSB_DIR_IN].max_size = 64;
+
+        dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true);
+
+        USBHSD->DEV_AD = 0;
+        USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
+
+        USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */
+    } else if (intflag & USBHS_SUSPEND_FLAG) {
+        dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND };
+        dcd_event_handler(&event, true);
+
+        USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */
+    }
+}
+
+#endif
\ No newline at end of file
diff --git a/src/tusb_option.h b/src/tusb_option.h
index bd87a953c..ffeec2241 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -149,6 +149,9 @@
 // Allwinner
 #define OPT_MCU_F1C100S          2100 ///< Allwinner F1C100s family
 
+// WCH
+#define OPT_MCU_CH32VF307        2200 ///< WCH CH32V307 config
+
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
 #define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == _m)

From 1d254be1a48264f906c5bbc50c4eca56eea063df Mon Sep 17 00:00:00 2001
From: Greg Davill <greg.davill@gmail.com>
Date: Tue, 22 Mar 2022 16:03:53 +1030
Subject: [PATCH 0936/2085] Increase stack size to 4096 bytes

---
 hw/bsp/ch32v307/Link.ld                       | 170 ++++++++++++++++++
 .../ch32v307/boards/CH32V307V-R1-1v0/board.mk |   2 +-
 2 files changed, 171 insertions(+), 1 deletion(-)
 create mode 100644 hw/bsp/ch32v307/Link.ld

diff --git a/hw/bsp/ch32v307/Link.ld b/hw/bsp/ch32v307/Link.ld
new file mode 100644
index 000000000..af7c06615
--- /dev/null
+++ b/hw/bsp/ch32v307/Link.ld
@@ -0,0 +1,170 @@
+ENTRY( _start )
+
+__stack_size = 4096;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{
+	FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K
+	RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+
+SECTIONS
+{
+
+	.init :
+	{
+		_sinit = .;
+		. = ALIGN(4);
+		KEEP(*(SORT_NONE(.init)))
+		. = ALIGN(4);
+		_einit = .;
+	} >FLASH AT>FLASH
+
+  .vector :
+  {
+      *(.vector);
+	  . = ALIGN(64);
+  } >FLASH AT>FLASH
+
+	.text :
+	{
+		. = ALIGN(4);
+		*(.text)
+		*(.text.*)
+		*(.rodata)
+		*(.rodata*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.gnu.linkonce.t.*)
+		. = ALIGN(4);
+	} >FLASH AT>FLASH 
+
+	.fini :
+	{
+		KEEP(*(SORT_NONE(.fini)))
+		. = ALIGN(4);
+	} >FLASH AT>FLASH
+
+	PROVIDE( _etext = . );
+	PROVIDE( _eitcm = . );	
+
+	.preinit_array  :
+	{
+	  PROVIDE_HIDDEN (__preinit_array_start = .);
+	  KEEP (*(.preinit_array))
+	  PROVIDE_HIDDEN (__preinit_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.init_array     :
+	{
+	  PROVIDE_HIDDEN (__init_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+	  PROVIDE_HIDDEN (__init_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.fini_array     :
+	{
+	  PROVIDE_HIDDEN (__fini_array_start = .);
+	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+	  PROVIDE_HIDDEN (__fini_array_end = .);
+	} >FLASH AT>FLASH 
+	
+	.ctors          :
+	{
+	  /* gcc uses crtbegin.o to find the start of
+	     the constructors, so we make sure it is
+	     first.  Because this is a wildcard, it
+	     doesn't matter if the user does not
+	     actually link against crtbegin.o; the
+	     linker won't look for a file to match a
+	     wildcard.  The wildcard also means that it
+	     doesn't matter which directory crtbegin.o
+	     is in.  */
+	  KEEP (*crtbegin.o(.ctors))
+	  KEEP (*crtbegin?.o(.ctors))
+	  /* We don't want to include the .ctor section from
+	     the crtend.o file until after the sorted ctors.
+	     The .ctor section from the crtend file contains the
+	     end of ctors marker and it must be last */
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+	  KEEP (*(SORT(.ctors.*)))
+	  KEEP (*(.ctors))
+	} >FLASH AT>FLASH 
+	
+	.dtors          :
+	{
+	  KEEP (*crtbegin.o(.dtors))
+	  KEEP (*crtbegin?.o(.dtors))
+	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+	  KEEP (*(SORT(.dtors.*)))
+	  KEEP (*(.dtors))
+	} >FLASH AT>FLASH 
+
+	.dalign :
+	{
+		. = ALIGN(4);
+		PROVIDE(_data_vma = .);
+	} >RAM AT>FLASH	
+
+	.dlalign :
+	{
+		. = ALIGN(4); 
+		PROVIDE(_data_lma = .);
+	} >FLASH AT>FLASH
+
+	.data :
+	{
+    	*(.gnu.linkonce.r.*)
+    	*(.data .data.*)
+    	*(.gnu.linkonce.d.*)
+		. = ALIGN(8);
+    	PROVIDE( __global_pointer$ = . + 0x800 );
+    	*(.sdata .sdata.*)
+		*(.sdata2.*)
+    	*(.gnu.linkonce.s.*)
+    	. = ALIGN(8);
+    	*(.srodata.cst16)
+    	*(.srodata.cst8)
+    	*(.srodata.cst4)
+    	*(.srodata.cst2)
+    	*(.srodata .srodata.*)
+    	. = ALIGN(4);
+		PROVIDE( _edata = .);
+	} >RAM AT>FLASH
+
+	.bss :
+	{
+		. = ALIGN(4);
+		PROVIDE( _sbss = .);
+  	    *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+		*(.bss*)
+     	*(.gnu.linkonce.b.*)		
+		*(COMMON*)
+		. = ALIGN(4);
+		PROVIDE( _ebss = .);
+	} >RAM AT>FLASH
+
+	PROVIDE( _end = _ebss);
+	PROVIDE( end = . );
+
+    .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );    
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+        __freertos_irq_stack_top = .;
+    } >RAM 
+
+}
+
+
+
diff --git a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk
index f71def2c7..a7c359588 100644
--- a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk
+++ b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk
@@ -1,3 +1,3 @@
-LINKER_SCRIPTS = $(CH32V307_SDK_SRC)/Ld
+LINKER_SCRIPTS = $(BOARD_PATH)/../..
 
 LD_FILE = $(LINKER_SCRIPTS)/Link.ld # CH32V307

From ac058a4c4553a237b297812be712a9c8dce0069a Mon Sep 17 00:00:00 2001
From: Greg Davill <greg.davill@gmail.com>
Date: Tue, 22 Mar 2022 22:32:53 +1030
Subject: [PATCH 0937/2085] Add ch32v307 to build workflow

---
 .github/workflows/build_riscv.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 0c7b2d154..4ac265da3 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -15,6 +15,7 @@ jobs:
       matrix:
         family:
         # Alphabetical order
+        - 'ch32v307'
         - 'fomu'
         - 'gd32vf103'
     steps:

From d828d203fcdc9f6839330e1007a331f740224ab8 Mon Sep 17 00:00:00 2001
From: Greg Davill <greg.davill@gmail.com>
Date: Tue, 22 Mar 2022 23:29:09 +1030
Subject: [PATCH 0938/2085] Skip freertos for ch32v307

---
 examples/device/cdc_msc_freertos/skip.txt       | 1 +
 examples/device/hid_composite_freertos/skip.txt | 1 +
 2 files changed, 2 insertions(+)

diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt
index 7137b78af..edb8a34aa 100644
--- a/examples/device/cdc_msc_freertos/skip.txt
+++ b/examples/device/cdc_msc_freertos/skip.txt
@@ -6,5 +6,6 @@ mcu:MKL25ZXX
 mcu:RP2040
 mcu:SAMX7X
 mcu:GD32VF103
+mcu:CH32V307
 family:broadcom_64bit
 family:broadcom_32bit
\ No newline at end of file
diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt
index e64187fd4..b12de1a90 100644
--- a/examples/device/hid_composite_freertos/skip.txt
+++ b/examples/device/hid_composite_freertos/skip.txt
@@ -5,5 +5,6 @@ mcu:VALENTYUSB_EPTRI
 mcu:RP2040
 mcu:SAMX7X
 mcu:GD32VF103
+mcu:CH32V307
 family:broadcom_64bit
 family:broadcom_32bit
\ No newline at end of file

From a09c1648f56580bcdb59b08af255442d9240281c Mon Sep 17 00:00:00 2001
From: Greg Davill <greg.davill@gmail.com>
Date: Tue, 22 Mar 2022 23:31:20 +1030
Subject: [PATCH 0939/2085] Fix typo

---
 hw/bsp/ch32v307/family.mk                | 2 +-
 src/common/tusb_mcu.h                    | 2 +-
 src/portable/wch/ch32v307/usb_dc_usbhs.c | 2 +-
 src/tusb_option.h                        | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index dfb4853d9..ef2af26e6 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -28,7 +28,7 @@ CFLAGS += \
 	-ffunction-sections \
 	-fdata-sections \
 	-nostdlib -nostartfiles \
-	-DCFG_TUSB_MCU=OPT_MCU_CH32VF307 \
+	-DCFG_TUSB_MCU=OPT_MCU_CH32V307 \
 	-Xlinker --gc-sections \
     -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
 
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 84d629eac..9de092e34 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -267,7 +267,7 @@
   #define TUP_DCD_ENDPOINT_MAX    4
 
 //------------- WCH -------------//
-#elif TU_CHECK_MCU(OPT_MCU_CH32VF307)
+#elif TU_CHECK_MCU(OPT_MCU_CH32V307)
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #endif
diff --git a/src/portable/wch/ch32v307/usb_dc_usbhs.c b/src/portable/wch/ch32v307/usb_dc_usbhs.c
index 32645dc5f..3a2c9979e 100644
--- a/src/portable/wch/ch32v307/usb_dc_usbhs.c
+++ b/src/portable/wch/ch32v307/usb_dc_usbhs.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32VF307)
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307)
 #include "device/dcd.h"
 
 #include "usb_ch32_usbhs_reg.h"
diff --git a/src/tusb_option.h b/src/tusb_option.h
index ffeec2241..28bf8a60d 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -150,7 +150,7 @@
 #define OPT_MCU_F1C100S          2100 ///< Allwinner F1C100s family
 
 // WCH
-#define OPT_MCU_CH32VF307        2200 ///< WCH CH32V307 config
+#define OPT_MCU_CH32V307        2200 ///< WCH CH32V307 config
 
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input

From 325923b6c61d0a914a0c6f78e650c6b85fbd13d2 Mon Sep 17 00:00:00 2001
From: Greg Davill <greg.davill@gmail.com>
Date: Tue, 22 Mar 2022 23:40:54 +1030
Subject: [PATCH 0940/2085] Update comments about endpoint buffer modes

---
 src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h b/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h
index 1b7c0e791..5a2c1fbc9 100644
--- a/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h
+++ b/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h
@@ -231,12 +231,12 @@
 
 #define USBHS_EP15_BUF_MOD     (1 << 15)
 #define USBHS_EP15_ISO_BUF_MOD (1 << 31)
-//USBHS_EPn_T_EN  USBHS_EPn_R_EN  USBHS_EPn_BUF_MOD  锟斤拷锟斤拷锟斤拷锟斤拷UEPn_DMA为锟斤拷始锟斤拷�锟缴碉拷锟斤拷锟斤拷锟斤拷锟�
-//      0               0               x            锟剿点被锟斤拷锟矫�拷未锟矫碉拷UEPn_*_DMA锟斤拷锟斤拷锟斤拷锟斤拷
-//      1               0               0            锟斤拷锟秸�拷OUT锟斤拷锟斤拷锟斤拷锟斤拷锟阶碉拷�为UEPn_RX_DMA
-//      1               0               1            bUEPn_RX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA锟斤拷bUEPn_RX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA
-//      0               1               0            锟斤拷锟斤拷(IN)锟斤拷锟斤拷锟斤拷锟阶碉拷�为UEPn_TX_DMA锟斤拷
-//      0               1               1            bUEPn_TX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA锟斤拷bUEPn_TX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA
+//USBHS_EPn_T_EN  USBHS_EPn_R_EN  USBHS_EPn_BUF_MOD  Description: Arrange from low to high with UEPn_DMA as the starting address
+//      0               0               x            The endpoint is disabled and the UEPn_*_DMA buffers are not used.
+//      1               0               0            The first address of the receive (OUT) buffer is UEPn_RX_DMA
+//      1               0               1            RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA
+//      0               1               0            The first address of the transmit (IN) buffer is UEPn_TX_DMA.
+//      0               1               1            RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA
 
 /* USB0_DMA */
 #define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address

From cdb8a1a2a1dd863f35fd91d58c18ec83115f9326 Mon Sep 17 00:00:00 2001
From: Greg Davill <greg.davill@gmail.com>
Date: Wed, 23 Mar 2022 00:00:06 +1030
Subject: [PATCH 0941/2085] Clean up driver

---
 src/common/tusb_mcu.h                    |  2 +-
 src/portable/wch/ch32v307/usb_dc_usbhs.c | 10 ++++------
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 9de092e34..fb0cdd361 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -268,7 +268,7 @@
 
 //------------- WCH -------------//
 #elif TU_CHECK_MCU(OPT_MCU_CH32V307)
-  #define TUP_DCD_ENDPOINT_MAX    8
+  #define TUP_DCD_ENDPOINT_MAX    16
 
 #endif
 
diff --git a/src/portable/wch/ch32v307/usb_dc_usbhs.c b/src/portable/wch/ch32v307/usb_dc_usbhs.c
index 3a2c9979e..e647389ee 100644
--- a/src/portable/wch/ch32v307/usb_dc_usbhs.c
+++ b/src/portable/wch/ch32v307/usb_dc_usbhs.c
@@ -56,10 +56,8 @@ static xfer_ctl_t xfer_status[EP_MAX][2];
 #define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1))
 
 /* Endpoint Buffer */
-__attribute__((aligned(4))) uint8_t setup[8];           // ep0(64)
-__attribute__((aligned(4))) uint8_t EP0_DatabufHD[64];  // ep0(64)
+TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64];  // ep0(64)
 
-volatile uint8_t mps_over_flag = 0;
 volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01;
 
 void dcd_init(uint8_t rhport) {
@@ -67,15 +65,15 @@ void dcd_init(uint8_t rhport) {
 
     memset(&xfer_status, 0, sizeof(xfer_status));
 
-    // usb_dc_low_level_init();
-
     USBHSD->HOST_CTRL = 0x00;
     USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM;
 
     USBHSD->CONTROL = 0;
-#if 1
+
+#if (BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_HIGH_SPEED)
     USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
 #else
+    #error OPT_MODE_FULL_SPEED not currently supported on CH32V307
     USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED;
 #endif
 

From 46fb850e02ae5010e0f7209775e1f5392112efa4 Mon Sep 17 00:00:00 2001
From: Greg Davill <greg.davill@gmail.com>
Date: Wed, 23 Mar 2022 00:06:51 +1030
Subject: [PATCH 0942/2085] Update support table

---
 docs/reference/supported.rst | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 7ce982713..aebee2c29 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -102,6 +102,8 @@ Supported MCUs
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
 | ValentyUSB   | eptri                 | ✔      | ✖    | ✖         | eptri             |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
+| WCH          | CH32V307              | ✔      | ✖    | ✔         | ch32v307          |              |
++--------------+-----------------------+--------+------+-----------+-------------------+--------------+
 
 
 Table Legend
@@ -388,3 +390,8 @@ Tomu
 ----
 
 -  `Fomu <https://www.crowdsupply.com/sutajio-kosagi/fomu>`__
+
+WCH
+---
+
+- `CH32V307V-R1-1v0 <https://lcsc.com/product-detail/Development-Boards-Kits_WCH-Jiangsu-Qin-Heng-CH32V307V-EVT-R1_C2943980.html>`

From 7d395c674ca083a245df0601c8a6d392c75b34e8 Mon Sep 17 00:00:00 2001
From: Greg Davill <greg.davill@gmail.com>
Date: Wed, 23 Mar 2022 00:46:44 +1030
Subject: [PATCH 0943/2085] Update supported table

---
 docs/reference/supported.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index aebee2c29..7543e44ab 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -102,7 +102,7 @@ Supported MCUs
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
 | ValentyUSB   | eptri                 | ✔      | ✖    | ✖         | eptri             |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| WCH          | CH32V307              | ✔      | ✖    | ✔         | ch32v307          |              |
+| WCH          | CH32V307              | ✔      |      | ✔         | ch32v307          |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
 
 

From 735300b53cf519b58576b3746ec48ae163df327f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Mar 2022 12:47:32 +0700
Subject: [PATCH 0944/2085] remove cxd56 __pycache-_ folder

---
 .../tools/__pycache__/xmodem.cpython-36.pyc     | Bin 15257 -> 0 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 hw/mcu/sony/cxd56/tools/__pycache__/xmodem.cpython-36.pyc

diff --git a/hw/mcu/sony/cxd56/tools/__pycache__/xmodem.cpython-36.pyc b/hw/mcu/sony/cxd56/tools/__pycache__/xmodem.cpython-36.pyc
deleted file mode 100644
index cfa917f71d3dbe945ac710d5b292db2daa36426e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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From 65b6b79e9954c4b8edceea040aba1a8fd80e975c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 29 Mar 2022 16:53:45 +0700
Subject: [PATCH 0945/2085] clean up and comment out tud_sof_isr_set

---
 src/device/usbd.c     | 61 +++++++++++++++++++------------------------
 src/device/usbd.h     |  2 +-
 src/device/usbd_pvt.h |  2 +-
 src/tusb_option.h     |  2 +-
 4 files changed, 30 insertions(+), 37 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 96ac19c8d..8ab67c8de 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -98,7 +98,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = cdcd_open,
     .control_xfer_cb  = cdcd_control_xfer_cb,
     .xfer_cb          = cdcd_xfer_cb,
-    .sof              = NULL
+    .sof_isr          = NULL
   },
   #endif
 
@@ -110,7 +110,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = mscd_open,
     .control_xfer_cb  = mscd_control_xfer_cb,
     .xfer_cb          = mscd_xfer_cb,
-    .sof              = NULL
+    .sof_isr          = NULL
   },
   #endif
 
@@ -122,7 +122,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = hidd_open,
     .control_xfer_cb  = hidd_control_xfer_cb,
     .xfer_cb          = hidd_xfer_cb,
-    .sof              = NULL
+    .sof_isr          = NULL
   },
   #endif
 
@@ -134,7 +134,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = audiod_open,
     .control_xfer_cb  = audiod_control_xfer_cb,
     .xfer_cb          = audiod_xfer_cb,
-    .sof              = audiod_sof
+    .sof_isr          = audiod_sof
   },
   #endif
 
@@ -146,7 +146,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = videod_open,
     .control_xfer_cb  = videod_control_xfer_cb,
     .xfer_cb          = videod_xfer_cb,
-    .sof              = NULL
+    .sof_isr          = NULL
   },
   #endif
 
@@ -158,7 +158,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .reset            = midid_reset,
     .control_xfer_cb  = midid_control_xfer_cb,
     .xfer_cb          = midid_xfer_cb,
-    .sof              = NULL
+    .sof_isr          = NULL
   },
   #endif
 
@@ -170,7 +170,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = vendord_open,
     .control_xfer_cb  = tud_vendor_control_xfer_cb,
     .xfer_cb          = vendord_xfer_cb,
-    .sof              = NULL
+    .sof_isr              = NULL
   },
   #endif
 
@@ -182,7 +182,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = usbtmcd_open_cb,
     .control_xfer_cb  = usbtmcd_control_xfer_cb,
     .xfer_cb          = usbtmcd_xfer_cb,
-    .sof              = NULL
+    .sof_isr          = NULL
   },
   #endif
 
@@ -194,7 +194,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = dfu_rtd_open,
     .control_xfer_cb  = dfu_rtd_control_xfer_cb,
     .xfer_cb          = NULL,
-    .sof              = NULL
+    .sof_isr          = NULL
   },
   #endif
 
@@ -206,7 +206,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = dfu_moded_open,
     .control_xfer_cb  = dfu_moded_control_xfer_cb,
     .xfer_cb          = NULL,
-    .sof              = NULL
+    .sof_isr          = NULL
   },
   #endif
 
@@ -218,7 +218,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = netd_open,
     .control_xfer_cb  = netd_control_xfer_cb,
     .xfer_cb          = netd_xfer_cb,
-    .sof              = NULL,
+    .sof_isr              = NULL,
   },
   #endif
 
@@ -230,7 +230,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = btd_open,
     .control_xfer_cb  = btd_control_xfer_cb,
     .xfer_cb          = btd_xfer_cb,
-    .sof              = NULL
+    .sof_isr          = NULL
   },
   #endif
 };
@@ -264,7 +264,7 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 // DCD Event
 //--------------------------------------------------------------------+
 
-static tud_sof_isr_t _sof_isr = NULL;
+//static tud_sof_isr_t _sof_isr = NULL;
 
 enum { RHPORT_INVALID = 0xFFu };
 static uint8_t _usbd_rhport = RHPORT_INVALID;
@@ -373,11 +373,11 @@ bool tud_connect(void)
   return true;
 }
 
-void tud_sof_isr_set(tud_sof_isr_t sof_isr)
-{
-  _sof_isr = sof_isr;
-  dcd_sof_enable(_usbd_rhport, _sof_isr != NULL);
-}
+//void tud_sof_isr_set(tud_sof_isr_t sof_isr)
+//{
+//  _sof_isr = sof_isr;
+//  dcd_sof_enable(_usbd_rhport, _sof_isr != NULL);
+//}
 
 //--------------------------------------------------------------------+
 // USBD Task
@@ -422,7 +422,7 @@ bool tud_init (uint8_t rhport)
   }
 
   _usbd_rhport = rhport;
-  _sof_isr = NULL;
+  //_sof_isr = NULL;
 
   // Init device controller driver
   dcd_init(rhport);
@@ -585,21 +585,12 @@ void tud_task (void)
         }
       break;
 
-      case DCD_EVENT_SOF:
-        TU_LOG2("\r\n");
-        // TODO: Should this really be done here in the queue? How to distinguish the calls here from those SOF events which should be handled directly in the ISR routine? If we do it like this, the SOF routines get called two time right now, once in the ISR context and once again here
-//        for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ )
-//        {
-//          usbd_class_driver_t const * driver = get_driver(i);
-//          if ( driver->sof ) driver->sof(event.rhport, event.sof.frame_count);
-//        }
-      break;
-
       case USBD_EVENT_FUNC_CALL:
         TU_LOG2("\r\n");
         if ( event.func_call.func ) event.func_call.func(event.func_call.param);
       break;
 
+      case DCD_EVENT_SOF:
       default:
         TU_BREAKPOINT();
       break;
@@ -1114,15 +1105,14 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
       for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
       {
         usbd_class_driver_t const * driver = get_driver(i);
-        if (driver->sof)
+        if (driver->sof_isr)
         {
-          driver->sof(event->rhport, event->sof.frame_count);
-          // TU_LOG2("%s sof\r\n", driver->name); // too demanding
+          driver->sof_isr(event->rhport, event->sof.frame_count);
         }
       }
 
       // SOF user handler in ISR context
-      if (_sof_isr) _sof_isr(event->sof.frame_count);
+      // if (_sof_isr) _sof_isr(event->sof.frame_count);
 
       // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup
       // which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational
@@ -1133,6 +1123,8 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
         dcd_event_t const event_resume = { .rhport = event->rhport, .event_id = DCD_EVENT_RESUME };
         osal_queue_send(_usbd_q, &event_resume, in_isr);
       }
+
+      // skip osal queue for SOF in usbd task
     break;
 
     default:
@@ -1411,7 +1403,8 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_sof_enable(uint8_t rhport, bool en)
 {
-  // TODO: Check needed if all drivers including the user sof_cb does not need an active SOF ISR any more. Only if all drivers switched off SOF calls the SOF interrupt may be disabled
+  // TODO: Check needed if all drivers including the user sof_cb does not need an active SOF ISR any more.
+  // Only if all drivers switched off SOF calls the SOF interrupt may be disabled
   dcd_sof_enable(rhport, en);
 }
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 72401a7e9..d485d8711 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -88,7 +88,7 @@ bool tud_connect(void);
 
 // Set Start-of-frame (1ms interval) IRQ handler
 // NULL means disabled, frame_count may not be supported on mcus
-void tud_sof_isr_set(tud_sof_isr_t sof_isr);
+// void tud_sof_isr_set(tud_sof_isr_t sof_isr);
 
 // Carry out Data and Status stage of control transfer
 // - If len = 0, it is equivalent to sending status only
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 144736a46..603ffc936 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -48,7 +48,7 @@ typedef struct
   uint16_t (* open             ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len);
   bool     (* control_xfer_cb  ) (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
   bool     (* xfer_cb          ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-  void     (* sof              ) (uint8_t rhport, uint32_t frame_count); /* optional */
+  void     (* sof_isr          ) (uint8_t rhport, uint32_t frame_count); // optional
 } usbd_class_driver_t;
 
 // Invoked when initializing device stack to get additional class drivers.
diff --git a/src/tusb_option.h b/src/tusb_option.h
index b3c3f4c5e..e1e418f89 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -297,7 +297,7 @@
 #endif
 
 #ifndef CFG_TUD_INTERFACE_MAX
-  #define CFG_TUD_INTERFACE_MAX   8
+  #define CFG_TUD_INTERFACE_MAX   16
 #endif
 
 #ifndef CFG_TUD_CDC

From e2f0aef93b246368e1f6bdf101604e73d252801a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 30 Mar 2022 16:41:55 +0700
Subject: [PATCH 0946/2085] make use pio_usb_port_reset_start/end

---
 hw/bsp/rp2040/family.cmake             |  1 +
 src/portable/raspberrypi/pio/hcd_pio.c | 10 ++--------
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 23ea893b7..b56ee6a6d 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -91,6 +91,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 
 			${TOP}/src/portable/raspberrypi/pio/hcd_pio.c
 			${TOP}/lib/Pico-PIO-USB/pio_usb.c
+			${TOP}/lib/Pico-PIO-USB/pio_usb_port.c
 			${TOP}/lib/Pico-PIO-USB/usb_crc.c
 			)
 
diff --git a/src/portable/raspberrypi/pio/hcd_pio.c b/src/portable/raspberrypi/pio/hcd_pio.c
index 8d1903f85..e4a4e2450 100644
--- a/src/portable/raspberrypi/pio/hcd_pio.c
+++ b/src/portable/raspberrypi/pio/hcd_pio.c
@@ -53,8 +53,6 @@ extern pio_port_t pio_port[1];
 extern root_port_t root_port[PIO_USB_ROOT_PORT_CNT];
 extern endpoint_t ep_pool[PIO_USB_EP_POOL_CNT];
 
-
-extern port_pin_status_t get_port_pin_status( root_port_t *port);
 extern void configure_fullspeed_host( pio_port_t *pp, const pio_usb_configuration_t *c, root_port_t *port);
 extern void configure_lowspeed_host( pio_port_t *pp, const pio_usb_configuration_t *c, root_port_t *port);
 
@@ -83,10 +81,7 @@ void hcd_port_reset(uint8_t rhport)
   pio_port_t *pp = &pio_port[0];
   root_port_t *root = &root_port[rhport];
 
-  pio_sm_set_pins_with_mask(pp->pio_usb_tx, pp->sm_tx, (0b00 << root->pin_dp),
-                            (0b11u << root->pin_dp));
-  pio_sm_set_pindirs_with_mask(pp->pio_usb_tx, pp->sm_tx, (0b11u << root->pin_dp),
-                               (0b11u << root->pin_dp));
+  pio_usb_port_reset_start(root, pp);
 }
 
 void hcd_port_reset_end(uint8_t rhport)
@@ -96,8 +91,7 @@ void hcd_port_reset_end(uint8_t rhport)
   pio_port_t *pp = &pio_port[0];
   root_port_t *root = &root_port[rhport];
 
-  pio_sm_set_pindirs_with_mask(pp->pio_usb_tx, pp->sm_tx, (0b00u << root->pin_dp),
-                               (0b11u << root->pin_dp));
+  pio_usb_port_reset_end(root, pp);
 
   busy_wait_us(100);
 

From 95801bf5cc4afa27f9b54c33e74aa74689074a97 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Wed, 30 Mar 2022 14:15:34 +0100
Subject: [PATCH 0947/2085] Update requirements.txt

---
 docs/requirements.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/requirements.txt b/docs/requirements.txt
index 8ae9ae73b..15022e147 100644
--- a/docs/requirements.txt
+++ b/docs/requirements.txt
@@ -1,3 +1,4 @@
 sphinx~=3.0
 furo>=2020.12.30.b24
 sphinx-autodoc-typehints>=1.10
+jinja2==3.0.3

From e94d11a5b39cae08f39722eaa5f6ac4d527a329b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 31 Mar 2022 12:56:53 +0700
Subject: [PATCH 0948/2085] implement pio_usb_irq_handler

---
 lib/Pico-PIO-USB                       |  2 +-
 src/portable/raspberrypi/pio/hcd_pio.c | 26 +++++++++++++++++++++++---
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 92268187f..4220c05dc 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 92268187f3b0490a43d139ed2cb598b06258011f
+Subproject commit 4220c05dc6b7ab7b4db33e5e05bb66be7b6c7156
diff --git a/src/portable/raspberrypi/pio/hcd_pio.c b/src/portable/raspberrypi/pio/hcd_pio.c
index e4a4e2450..254acf1d2 100644
--- a/src/portable/raspberrypi/pio/hcd_pio.c
+++ b/src/portable/raspberrypi/pio/hcd_pio.c
@@ -101,7 +101,7 @@ void hcd_port_reset_end(uint8_t rhport)
   if (fullspeed_flag && get_port_pin_status(root) == PORT_PIN_FS_IDLE) {
     root->root_device = &usb_device[0];
     if (!root->root_device->connected) {
-      configure_fullspeed_host(pp, &pio_host_config, root);
+//      configure_fullspeed_host(pp, &pio_host_config, root);
       root->root_device->is_fullspeed = true;
       root->root_device->is_root = true;
       root->root_device->connected = true;
@@ -111,7 +111,7 @@ void hcd_port_reset_end(uint8_t rhport)
   } else if (!fullspeed_flag && get_port_pin_status(root) == PORT_PIN_LS_IDLE) {
     root->root_device = &usb_device[0];
     if (!root->root_device->connected) {
-      configure_lowspeed_host(pp, &pio_host_config, root);
+//      configure_lowspeed_host(pp, &pio_host_config, root);
       root->root_device->is_fullspeed = false;
       root->root_device->is_root = true;
       root->root_device->connected = true;
@@ -217,6 +217,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   return false;
 }
 
+
 bool hcd_edpt_control_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8], uint8_t* data)
 {
   int ret;
@@ -242,7 +243,6 @@ bool hcd_edpt_control_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t const setup
   return ret == 0;
 }
 
-
 //bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
 //{
 //    // EPX is shared, so multiple device addresses and endpoint addresses share that
@@ -265,4 +265,24 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
   return true;
 }
 
+// IRQ Handler
+void pio_usb_irq_handler(uint8_t root_id)
+{
+  root_port_t* port = PIO_USB(root_id);
+
+  if ( port->ints & PIO_USB_INTS_CONNECT_BITS )
+  {
+    hcd_event_device_attach(root_id+1, true);
+
+    port->ints &= ~PIO_USB_INTS_CONNECT_BITS;
+  }
+
+  if ( port->ints & PIO_USB_INTS_DISCONNECT_BITS )
+  {
+    hcd_event_device_remove(root_id+1, true);
+
+    port->ints &= ~PIO_USB_INTS_DISCONNECT_BITS;
+  }
+}
+
 #endif

From 75bca96bc630b98723c9f4bbb4958dac22ac594d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Apr 2022 16:01:24 +0700
Subject: [PATCH 0949/2085] pio usb control work well including stall response

---
 src/host/hcd.h                         |   4 -
 src/host/usbh.c                        |  16 ++--
 src/portable/raspberrypi/pio/hcd_pio.c | 118 +++++++++++++++----------
 3 files changed, 78 insertions(+), 60 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 0e18351fc..9b41f2447 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -153,10 +153,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
 
-// Optional: some controllers are capable of carry out the whole Control Transfer (setup, data, status)
-// without help of USBH.
-bool hcd_edpt_control_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8], uint8_t* data) TU_ATTR_WEAK;
-
 // clear stall, data toggle is also reset to DATA0
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index b388a4c08..520ef4c7d 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -543,19 +543,12 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
   const uint8_t rhport = usbh_get_rhport(daddr);
 
   TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request");
-  TU_LOG2_VAR(&xfer->setup);
+  TU_LOG2_VAR(xfer->setup);
   TU_LOG2("\r\n");
 
   if (xfer->complete_cb)
   {
-    if ( hcd_edpt_control_xfer )
-    {
-      _ctrl_xfer.stage = CONTROL_STAGE_ACK;
-      TU_ASSERT( hcd_edpt_control_xfer(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request, _ctrl_xfer.buffer) );
-    }else
-    {
-      TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
-    }
+    TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
   }else
   {
     // blocking if complete callback is not provided
@@ -643,7 +636,8 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
         {
           // DATA stage: initial data toggle is always 1
           _set_control_xfer_stage(CONTROL_STAGE_DATA);
-          return hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
+          TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) );
+          return true;
         }
         __attribute__((fallthrough));
 
@@ -658,7 +652,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 
         // ACK stage: toggle is always 1
         _set_control_xfer_stage(CONTROL_STAGE_ACK);
-        hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
+        TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0) );
       break;
 
       case CONTROL_STAGE_ACK:
diff --git a/src/portable/raspberrypi/pio/hcd_pio.c b/src/portable/raspberrypi/pio/hcd_pio.c
index 254acf1d2..4eff490c8 100644
--- a/src/portable/raspberrypi/pio/hcd_pio.c
+++ b/src/portable/raspberrypi/pio/hcd_pio.c
@@ -53,15 +53,6 @@ extern pio_port_t pio_port[1];
 extern root_port_t root_port[PIO_USB_ROOT_PORT_CNT];
 extern endpoint_t ep_pool[PIO_USB_EP_POOL_CNT];
 
-extern void configure_fullspeed_host( pio_port_t *pp, const pio_usb_configuration_t *c, root_port_t *port);
-extern void configure_lowspeed_host( pio_port_t *pp, const pio_usb_configuration_t *c, root_port_t *port);
-
-extern void control_setup_transfer( const pio_port_t *pp, uint8_t device_address, uint8_t *tx_data_address, uint8_t tx_data_len);
-extern int control_in_protocol( usb_device_t *device, uint8_t *tx_data, uint16_t tx_length, uint8_t *rx_buffer, uint16_t request_length);
-extern int control_out_protocol( usb_device_t *device, uint8_t *setup_data, uint16_t setup_length, uint8_t *out_data, uint16_t out_length);
-
-extern void update_packet_crc16(usb_setup_packet_t * packet);
-
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
@@ -157,12 +148,15 @@ void hcd_int_disable(uint8_t rhport)
 // Endpoint API
 //--------------------------------------------------------------------+
 
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
 {
   rhport = RHPORT_PIO(rhport);
 
   usb_device_t *device = &usb_device[0];
 
+  return pio_usb_endpoint_open(rhport, dev_addr, (uint8_t const*) desc_ep);
+
+#if 0
   static uint8_t ep_id_idx; // TODO remove later
 
   if (ep_desc->bEndpointAddress == 0)
@@ -202,45 +196,19 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   }
 
   return true;
+#endif
 }
 
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
-  (void) rhport;
-
-  return true;
+  rhport = RHPORT_PIO(rhport);
+  return pio_usb_endpoint_transfer(rhport, dev_addr, ep_addr, buffer, buflen);
 }
 
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
-  (void) rhport;
-  return false;
-}
-
-
-bool hcd_edpt_control_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8], uint8_t* data)
-{
-  int ret;
   rhport = RHPORT_PIO(rhport);
-
-  uint16_t const len = ((tusb_control_request_t const*) setup_packet)->wLength;
-
-  usb_setup_packet_t pio_setup = { USB_SYNC, USB_PID_DATA0 };
-  memcpy(&pio_setup.request_type, setup_packet, 8);
-  update_packet_crc16(&pio_setup);
-
-  if (setup_packet[0] & TUSB_DIR_IN_MASK)
-  {
-    ret = control_in_protocol(&usb_device[0], (uint8_t*) &pio_setup, sizeof(pio_setup), data, len);
-  }else
-  {
-    ret = control_out_protocol(&usb_device[0], (uint8_t*) &pio_setup, sizeof(pio_setup), data, len);
-  }
-
-  // TODO current pio is blocking
-  hcd_event_xfer_complete(dev_addr, 0, 0, ret ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS, false);
-
-  return ret == 0;
+  return pio_usb_endpoint_send_setup(rhport, dev_addr, setup_packet);
 }
 
 //bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
@@ -265,23 +233,83 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
   return true;
 }
 
+void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* port, uint32_t flag)
+{
+  volatile uint32_t* ep_reg;
+  xfer_result_t result;
+
+  if ( flag == PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
+  {
+    ep_reg = &port->ep_complete;
+    result = XFER_RESULT_SUCCESS;
+  }
+  else if ( flag == PIO_USB_INTS_ENDPOINT_ERROR_BITS )
+  {
+    ep_reg = &port->ep_error;
+    result = XFER_RESULT_FAILED;
+  }
+  else if ( flag == PIO_USB_INTS_ENDPOINT_STALLED_BITS )
+  {
+    ep_reg = &port->ep_stalled;
+    result = XFER_RESULT_STALLED;
+  }
+  else
+  {
+    // something wrong
+    return;
+  }
+
+  const uint32_t ep_all = *ep_reg;
+
+  for(uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++)
+  {
+    uint32_t const mask = (1u << ep_idx);
+
+    if (ep_all & mask)
+    {
+      endpoint_t* ep = PIO_USB_EP(ep_idx);
+      hcd_event_xfer_complete(ep->dev_addr, ep->ep_num, ep->actual_len, result, true);
+    }
+  }
+
+  // clear all
+  (*ep_reg) &= ~ep_all;
+}
+
 // IRQ Handler
-void pio_usb_irq_handler(uint8_t root_id)
+void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id)
 {
   root_port_t* port = PIO_USB(root_id);
 
   if ( port->ints & PIO_USB_INTS_CONNECT_BITS )
   {
-    hcd_event_device_attach(root_id+1, true);
-
     port->ints &= ~PIO_USB_INTS_CONNECT_BITS;
+
+    hcd_event_device_attach(root_id+1, true);
   }
 
   if ( port->ints & PIO_USB_INTS_DISCONNECT_BITS )
   {
-    hcd_event_device_remove(root_id+1, true);
-
     port->ints &= ~PIO_USB_INTS_DISCONNECT_BITS;
+    hcd_event_device_remove(root_id+1, true);
+  }
+
+  if ( port->ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
+  {
+    port->ints &= ~PIO_USB_INTS_ENDPOINT_COMPLETE_BITS;
+    handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_COMPLETE_BITS);
+  }
+
+  if ( port->ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS )
+  {
+    port->ints &= ~PIO_USB_INTS_ENDPOINT_ERROR_BITS;
+    handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_ERROR_BITS);
+  }
+
+  if ( port->ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS )
+  {
+    port->ints &= ~PIO_USB_INTS_ENDPOINT_STALLED_BITS;
+    handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_STALLED_BITS);
   }
 }
 

From 817227a850d4942cf48ede675325d635e2e7b3d5 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Fri, 1 Apr 2022 10:05:14 +0100
Subject: [PATCH 0950/2085] Add WCH CH32V307 to readme supported list

---
 README.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.rst b/README.rst
index 5b994c357..755bd97e9 100644
--- a/README.rst
+++ b/README.rst
@@ -54,6 +54,7 @@ The stack supports the following MCUs:
 - **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G4, L0, L1, L4, L4+
 - **TI:** MSP430, MSP432E4, TM4C123
 - **ValentyUSB:** eptri
+- **WCH:** CH32V307
 
 Here is the list of `Supported Devices`_ that can be used with provided examples.
 

From e6e3dfedc815007d07ea455df04569604d87a856 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Apr 2022 16:34:36 +0700
Subject: [PATCH 0951/2085] hid example work well

---
 lib/Pico-PIO-USB                       |  2 +-
 src/class/hid/hid_host.c               |  2 +-
 src/host/usbh.c                        |  2 +-
 src/portable/raspberrypi/pio/hcd_pio.c | 42 --------------------------
 4 files changed, 3 insertions(+), 45 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 4220c05dc..650130ab3 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 4220c05dc6b7ab7b4db33e5e05bb66be7b6c7156
+Subproject commit 650130ab312e0dc9337dc52cccf34d35875abdf7
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index ce3d1598c..2573f5a6b 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -329,7 +329,7 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
 
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass);
 
-  TU_LOG2("HID opening Interface %u (addr = %u)\r\n", desc_itf->bInterfaceNumber, dev_addr);
+  TU_LOG2("[%u] HID opening Interface %u\r\n", dev_addr, desc_itf->bInterfaceNumber);
 
   // len = interface + hid + n*endpoints
   uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 520ef4c7d..c127ef310 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -792,7 +792,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
 
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
 {
-  TU_LOG2("Open EP0 with Size = %u (addr = %u)\r\n", max_packet_size, dev_addr);
+  TU_LOG2("[%u] Open EP0 with Size = %u\r\n", dev_addr, max_packet_size);
 
   tusb_desc_endpoint_t ep0_desc =
   {
diff --git a/src/portable/raspberrypi/pio/hcd_pio.c b/src/portable/raspberrypi/pio/hcd_pio.c
index 4eff490c8..037ebc132 100644
--- a/src/portable/raspberrypi/pio/hcd_pio.c
+++ b/src/portable/raspberrypi/pio/hcd_pio.c
@@ -155,48 +155,6 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   usb_device_t *device = &usb_device[0];
 
   return pio_usb_endpoint_open(rhport, dev_addr, (uint8_t const*) desc_ep);
-
-#if 0
-  static uint8_t ep_id_idx; // TODO remove later
-
-  if (ep_desc->bEndpointAddress == 0)
-  {
-    device->event = EVENT_NONE;
-    device->address = dev_addr;
-
-    ep_id_idx = 0;
-  }else  if (ep_desc->bmAttributes.xfer == TUSB_XFER_INTERRUPT) // only support interrupt endpoint
-  {
-    endpoint_t *ep = NULL;
-    for ( int ep_pool_idx = 0; ep_pool_idx < PIO_USB_EP_POOL_CNT; ep_pool_idx++ )
-    {
-      if ( ep_pool[ep_pool_idx].ep_num == 0 )
-      {
-        ep = &ep_pool[ep_pool_idx];
-        device->endpoint_id[ep_id_idx] = ep_pool_idx + 1;
-        ep_id_idx++;
-
-        ep->data_id = 0;
-        ep->ep_num = ep_desc->bEndpointAddress;
-        ep->interval = ep_desc->bInterval;
-        ep->interval_counter = 0;
-        ep->size = (uint8_t) tu_edpt_packet_size(ep_desc);
-        ep->attr = EP_ATTR_INTERRUPT;
-
-        break;
-      }
-    }
-
-//    TU_LOG1_INT(device->connected);
-//    TU_LOG1_INT(device->root);
-//    TU_LOG1_INT(device->is_root);
-//    TU_LOG1_INT(device->is_fullspeed);
-//
-//    TU_LOG1_INT(ep_id_idx);
-  }
-
-  return true;
-#endif
 }
 
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)

From db6cba6a7bdf82f8c131fa2c521b86b10b4d053e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Apr 2022 16:38:41 +0700
Subject: [PATCH 0952/2085] rename pio to pio_usb

---
 hw/bsp/rp2040/family.cmake                                      | 2 +-
 .../raspberrypi/{pio/hcd_pio.c => pio_usb/hcd_pio_usb.c}        | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename src/portable/raspberrypi/{pio/hcd_pio.c => pio_usb/hcd_pio_usb.c} (100%)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index b56ee6a6d..4cec645a2 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -89,7 +89,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/class/msc/msc_host.c
 			${TOP}/src/class/vendor/vendor_host.c
 
-			${TOP}/src/portable/raspberrypi/pio/hcd_pio.c
+			${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
 			${TOP}/lib/Pico-PIO-USB/pio_usb.c
 			${TOP}/lib/Pico-PIO-USB/pio_usb_port.c
 			${TOP}/lib/Pico-PIO-USB/usb_crc.c
diff --git a/src/portable/raspberrypi/pio/hcd_pio.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
similarity index 100%
rename from src/portable/raspberrypi/pio/hcd_pio.c
rename to src/portable/raspberrypi/pio_usb/hcd_pio_usb.c

From c25f835aea838f935893fdef6352fab938e11d4b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Apr 2022 23:31:43 +0700
Subject: [PATCH 0953/2085] update to use pio hw endpoint

---
 hw/bsp/rp2040/family.cmake                     | 3 ++-
 lib/Pico-PIO-USB                               | 2 +-
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 2 +-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 4cec645a2..275ec9e6b 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -91,7 +91,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 
 			${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
 			${TOP}/lib/Pico-PIO-USB/pio_usb.c
-			${TOP}/lib/Pico-PIO-USB/pio_usb_port.c
+			${TOP}/lib/Pico-PIO-USB/pio_usb_host.c
+			${TOP}/lib/Pico-PIO-USB/pio_usb_hw.c
 			${TOP}/lib/Pico-PIO-USB/usb_crc.c
 			)
 
diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 650130ab3..72f91ac9c 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 650130ab312e0dc9337dc52cccf34d35875abdf7
+Subproject commit 72f91ac9cdaf532eacfbe9534420341b13480441
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 037ebc132..09407851d 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -225,7 +225,7 @@ void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* port, uint3
 
     if (ep_all & mask)
     {
-      endpoint_t* ep = PIO_USB_EP(ep_idx);
+      pio_hw_endpoint_t* ep = PIO_USB_HW_EP(ep_idx);
       hcd_event_xfer_complete(ep->dev_addr, ep->ep_num, ep->actual_len, result, true);
     }
   }

From f881e77e66ea92506fefb69a24324f6c2274aab9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 2 Apr 2022 19:19:00 +0700
Subject: [PATCH 0954/2085] extracting hw root port

---
 lib/Pico-PIO-USB                               | 2 +-
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 6 ++----
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 72f91ac9c..ea48fc073 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 72f91ac9cdaf532eacfbe9534420341b13480441
+Subproject commit ea48fc073ce28e3870a71e8019b08a02bde8ebf9
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 09407851d..1fe7a0d6e 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -50,8 +50,6 @@ static pio_usb_configuration_t pio_host_config = PIO_USB_DEFAULT_CONFIG;
 extern root_port_t root_port[PIO_USB_ROOT_PORT_CNT];
 extern usb_device_t usb_device[PIO_USB_DEVICE_CNT];
 extern pio_port_t pio_port[1];
-extern root_port_t root_port[PIO_USB_ROOT_PORT_CNT];
-extern endpoint_t ep_pool[PIO_USB_EP_POOL_CNT];
 
 //--------------------------------------------------------------------+
 // HCD API
@@ -191,7 +189,7 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
   return true;
 }
 
-void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* port, uint32_t flag)
+void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_t* port, uint32_t flag)
 {
   volatile uint32_t* ep_reg;
   xfer_result_t result;
@@ -237,7 +235,7 @@ void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* port, uint3
 // IRQ Handler
 void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id)
 {
-  root_port_t* port = PIO_USB(root_id);
+  pio_hw_root_port_t* port = PIO_USB_HW_RPORT(root_id);
 
   if ( port->ints & PIO_USB_INTS_CONNECT_BITS )
   {

From f6851cf18764a615f83bb782973bb3ea25e9089c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 3 Apr 2022 00:17:58 +0700
Subject: [PATCH 0955/2085] clean up hcd pio

---
 lib/Pico-PIO-USB                              |  2 +-
 .../raspberrypi/pio_usb/hcd_pio_usb.c         | 60 +++----------------
 2 files changed, 10 insertions(+), 52 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index ea48fc073..7d8df447c 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit ea48fc073ce28e3870a71e8019b08a02bde8ebf9
+Subproject commit 7d8df447c4c5d0515f2ab9f10b28ac92d7cc78df
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 1fe7a0d6e..dc52870e9 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -43,14 +43,8 @@
 #define RHPORT_OFFSET     1
 #define RHPORT_PIO(_x)    ((_x)-RHPORT_OFFSET)
 
-
-static usb_device_t *_test_usb_device = NULL;
 static pio_usb_configuration_t pio_host_config = PIO_USB_DEFAULT_CONFIG;
 
-extern root_port_t root_port[PIO_USB_ROOT_PORT_CNT];
-extern usb_device_t usb_device[PIO_USB_DEVICE_CNT];
-extern pio_port_t pio_port[1];
-
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
@@ -58,7 +52,7 @@ bool hcd_init(uint8_t rhport)
 {
   // To run USB SOF interrupt in core1, create alarm pool in core1.
   pio_host_config.alarm_pool = (void*)alarm_pool_create(2, 1);
-  _test_usb_device = pio_usb_host_init(&pio_host_config);
+  (void) pio_usb_host_init(&pio_host_config);
 
   return true;
 }
@@ -66,56 +60,23 @@ bool hcd_init(uint8_t rhport)
 void hcd_port_reset(uint8_t rhport)
 {
   rhport = RHPORT_PIO(rhport);
-
-  pio_port_t *pp = &pio_port[0];
-  root_port_t *root = &root_port[rhport];
-
-  pio_usb_port_reset_start(root, pp);
+  pio_usb_hw_port_reset_start(rhport);
 }
 
 void hcd_port_reset_end(uint8_t rhport)
 {
   rhport = RHPORT_PIO(rhport);
-
-  pio_port_t *pp = &pio_port[0];
-  root_port_t *root = &root_port[rhport];
-
-  pio_usb_port_reset_end(root, pp);
-
-  busy_wait_us(100);
-
-  // TODO slow speed
-  bool fullspeed_flag = true;
-
-  if (fullspeed_flag && get_port_pin_status(root) == PORT_PIN_FS_IDLE) {
-    root->root_device = &usb_device[0];
-    if (!root->root_device->connected) {
-//      configure_fullspeed_host(pp, &pio_host_config, root);
-      root->root_device->is_fullspeed = true;
-      root->root_device->is_root = true;
-      root->root_device->connected = true;
-      root->root_device->root = root;
-      root->root_device->event = EVENT_CONNECT;
-    }
-  } else if (!fullspeed_flag && get_port_pin_status(root) == PORT_PIN_LS_IDLE) {
-    root->root_device = &usb_device[0];
-    if (!root->root_device->connected) {
-//      configure_lowspeed_host(pp, &pio_host_config, root);
-      root->root_device->is_fullspeed = false;
-      root->root_device->is_root = true;
-      root->root_device->connected = true;
-      root->root_device->root = root;
-      root->root_device->event = EVENT_CONNECT;
-    }
-  }
+  pio_usb_hw_port_reset_end(rhport);
 }
 
 bool hcd_port_connect_status(uint8_t rhport)
 {
-  root_port_t* port = &root_port[0];
-  bool dp = gpio_get(port->pin_dp);
-  bool dm = gpio_get(port->pin_dm);
-  return dp || dm;
+  rhport = RHPORT_PIO(rhport);
+
+  pio_hw_root_port_t *root = PIO_USB_HW_RPORT(rhport);
+  port_pin_status_t line_state = pio_hw_get_line_state(root);
+
+  return line_state != PORT_PIN_SE0;
 }
 
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
@@ -149,9 +110,6 @@ void hcd_int_disable(uint8_t rhport)
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
 {
   rhport = RHPORT_PIO(rhport);
-
-  usb_device_t *device = &usb_device[0];
-
   return pio_usb_endpoint_open(rhport, dev_addr, (uint8_t const*) desc_ep);
 }
 

From 7ea75d3c09d1afd4db5374c89f715d8ff6c1d414 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 3 Apr 2022 20:44:16 +0700
Subject: [PATCH 0956/2085] use pio usb host init

---
 lib/Pico-PIO-USB                               | 2 +-
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 7d8df447c..b507f95de 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 7d8df447c4c5d0515f2ab9f10b28ac92d7cc78df
+Subproject commit b507f95de457d5dc14fb15fd6481ef748c6e3342
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index dc52870e9..c2ac2c706 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -50,9 +50,8 @@ static pio_usb_configuration_t pio_host_config = PIO_USB_DEFAULT_CONFIG;
 //--------------------------------------------------------------------+
 bool hcd_init(uint8_t rhport)
 {
-  // To run USB SOF interrupt in core1, create alarm pool in core1.
-  pio_host_config.alarm_pool = (void*)alarm_pool_create(2, 1);
-  (void) pio_usb_host_init(&pio_host_config);
+  // To run USB SOF interrupt in core1, call this init in core1
+  pio_usb_host_controller_init(&pio_host_config);
 
   return true;
 }

From d7d7e61f3437076a38ec031f2dc4cef38c8c831b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 3 Apr 2022 22:48:08 +0700
Subject: [PATCH 0957/2085] correct pio usb speed, and close device

---
 lib/Pico-PIO-USB                               | 2 +-
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index b507f95de..650ef75f0 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit b507f95de457d5dc14fb15fd6481ef748c6e3342
+Subproject commit 650ef75f0d8a4020a7ddc2ccee1ee0f3237ab760
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index c2ac2c706..839087957 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -81,12 +81,15 @@ bool hcd_port_connect_status(uint8_t rhport)
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   // TODO determine link speed
-  return TUSB_SPEED_FULL;
+  rhport = RHPORT_PIO(rhport);
+  return PIO_USB_HW_RPORT(rhport)->is_fullspeed ? TUSB_SPEED_FULL : TUSB_SPEED_LOW;
 }
 
 // Close all opened endpoint belong to this device
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 {
+  rhport = RHPORT_PIO(rhport);
+  pio_usb_host_close_device(rhport, dev_addr);
 }
 
 uint32_t hcd_frame_number(uint8_t rhport)

From d97c1546957059cfb3063b95d5287e2729f7f79a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 5 Apr 2022 00:04:47 +0700
Subject: [PATCH 0958/2085] add need_pre for pio usb, but not work out well

---
 lib/Pico-PIO-USB                               | 2 +-
 src/host/usbh.c                                | 4 ++--
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 6 +++++-
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 650ef75f0..4993f4a1d 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 650ef75f0d8a4020a7ddc2ccee1ee0f3237ab760
+Subproject commit 4993f4a1df03c8af13c8091052a6274e8c333bc0
diff --git a/src/host/usbh.c b/src/host/usbh.c
index c127ef310..47c462012 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -642,7 +642,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
         __attribute__((fallthrough));
 
       case CONTROL_STAGE_DATA:
-        if (xferred_bytes)
+        if (request->wLength)
         {
           TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
           TU_LOG2_MEM(_ctrl_xfer.buffer, xferred_bytes, 2);
@@ -1301,7 +1301,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
       TU_ASSERT(new_dev, );
       new_dev->addressed = 1;
 
-      // TODO close device 0, may not be needed
+      // Close device 0
       hcd_device_close(_dev0.rhport, 0);
 
       // open control pipe for new address
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 839087957..c2ef54b9e 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -111,8 +111,12 @@ void hcd_int_disable(uint8_t rhport)
 
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
 {
+  hcd_devtree_info_t dev_tree;
+  hcd_devtree_get_info(dev_addr, &dev_tree);
+  bool const need_pre = (dev_tree.hub_addr && dev_tree.speed == TUSB_SPEED_LOW);
+
   rhport = RHPORT_PIO(rhport);
-  return pio_usb_endpoint_open(rhport, dev_addr, (uint8_t const*) desc_ep);
+  return pio_usb_endpoint_open(rhport, dev_addr, (uint8_t const*) desc_ep, need_pre);
 }
 
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)

From d5d4909c20f581ef2046932191f487c001d59ca3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 8 Apr 2022 13:36:05 +0700
Subject: [PATCH 0959/2085] proof of concpet that device pio-usb work with host
 pio-usb

---
 examples/device/hid_boot_interface/src/main.c |  4 +++
 .../hid_boot_interface/src/tusb_config.h      |  3 ++
 examples/host/cdc_msc_hid/src/tusb_config.h   |  1 +
 hw/bsp/rp2040/family.cmake                    | 32 ++++++++-----------
 src/portable/raspberrypi/rp2040/dcd_rp2040.c  |  2 +-
 src/tusb_option.h                             |  6 +++-
 6 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index e5e2f6856..ed7f235b7 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -31,6 +31,8 @@
 #include "tusb.h"
 #include "usb_descriptors.h"
 
+#include "pio_usb.h"
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
@@ -59,6 +61,8 @@ int main(void)
 
   while (1)
   {
+    pio_usb_device_task();
+
     tud_task(); // tinyusb device task
     led_blinking_task();
 
diff --git a/examples/device/hid_boot_interface/src/tusb_config.h b/examples/device/hid_boot_interface/src/tusb_config.h
index 1c8fa40b2..d4f67e7ba 100644
--- a/examples/device/hid_boot_interface/src/tusb_config.h
+++ b/examples/device/hid_boot_interface/src/tusb_config.h
@@ -39,6 +39,9 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
+// Use raspberry pio-usb for device
+#define CFG_TUD_RPI_PIO_USB            1
+
 // RHPort number used for device can be defined by board.mk, default to port 0
 #ifndef BOARD_DEVICE_RHPORT_NUM
   #define BOARD_DEVICE_RHPORT_NUM     0
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 80ee8cb01..9d083c771 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -39,6 +39,7 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
+// Use raspberry pio-usb for host
 #define CFG_TUH_RPI_PIO_USB            1
 //#define CFG_TUSB_RPI_PIO_INC_PATH   1
 
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 275ec9e6b..b186fc78e 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -29,12 +29,17 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	target_sources(tinyusb_common_base INTERFACE
 			${TOP}/src/tusb.c
 			${TOP}/src/common/tusb_fifo.c
+			${TOP}/lib/Pico-PIO-USB/pio_usb.c
+			${TOP}/lib/Pico-PIO-USB/pio_usb_host.c
+			${TOP}/lib/Pico-PIO-USB/pio_usb_hw.c
+			${TOP}/lib/Pico-PIO-USB/usb_crc.c
 			)
 
 	target_include_directories(tinyusb_common_base INTERFACE
 			${TOP}/src
 			${TOP}/src/common
 			${TOP}/hw
+			${TOP}/lib/Pico-PIO-USB
 			)
 
 	target_link_libraries(tinyusb_common_base INTERFACE
@@ -42,6 +47,10 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			hardware_irq
 			hardware_resets
 			pico_sync
+	    # for usb-pio
+	    hardware_dma
+	    hardware_pio
+	    pico_multicore
 			)
 
 	set(TINYUSB_DEBUG_LEVEL 0)
@@ -60,6 +69,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	add_library(tinyusb_device_base INTERFACE)
 	target_sources(tinyusb_device_base INTERFACE
 			${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+		  ${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
 			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
 			${TOP}/src/device/usbd.c
 			${TOP}/src/device/usbd_control.c
@@ -88,12 +98,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/class/hid/hid_host.c
 			${TOP}/src/class/msc/msc_host.c
 			${TOP}/src/class/vendor/vendor_host.c
-
-			${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
-			${TOP}/lib/Pico-PIO-USB/pio_usb.c
-			${TOP}/lib/Pico-PIO-USB/pio_usb_host.c
-			${TOP}/lib/Pico-PIO-USB/pio_usb_hw.c
-			${TOP}/lib/Pico-PIO-USB/usb_crc.c
+		  ${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
 			)
 
 	# Sometimes have to do host specific actions in mostly common functions
@@ -101,17 +106,6 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			RP2040_USB_HOST_MODE=1
 	)
 	
-	# config for host pio
-	target_link_libraries(tinyusb_host_base INTERFACE
-	   hardware_dma
-	   hardware_pio
-	   pico_multicore
-	   )
-	   
-	target_include_directories(tinyusb_host_base INTERFACE
-	   ${TOP}/lib/Pico-PIO-USB
-	   )
-
 	add_library(tinyusb_bsp INTERFACE)
 	target_sources(tinyusb_bsp INTERFACE
 			${TOP}/hw/bsp/rp2040/family.c
@@ -166,8 +160,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		_family_initialize_project(${PROJECT} ${DIR})
 		enable_language(C CXX ASM)
 		pico_sdk_init()
-    pico_generate_pio_header(tinyusb_host_base ${TOP}/lib/Pico-PIO-USB/usb_tx.pio)
-    pico_generate_pio_header(tinyusb_host_base ${TOP}/lib/Pico-PIO-USB/usb_rx.pio)
+    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/usb_tx.pio)
+    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/usb_rx.pio)
 	endfunction()
 
 	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 915822798..2d77ad4f9 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_RP2040
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUD_RPI_PIO_USB
 
 #include "pico.h"
 #include "rp2040_usb.h"
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 61cc283c4..5636b34fe 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -239,7 +239,7 @@
   #define TUH_OPT_RHPORT   -1
 #endif
 
-#define CFG_TUH_ENABLED     ( TUH_RHPORT_MODE & OPT_MODE_HOST )
+#define CFG_TUH_ENABLED     (TUH_RHPORT_MODE & OPT_MODE_HOST)
 
 // For backward compatible
 #define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED
@@ -398,6 +398,10 @@
 #define CFG_TUH_RPI_PIO_USB 0
 #endif
 
+#ifndef CFG_TUD_RPI_PIO_USB
+#define CFG_TUD_RPI_PIO_USB 0
+#endif
+
 
 //------------------------------------------------------------------
 // Configuration Validation

From 7094ff7125b6961d52eaca0e3b8d42f3b57a1ee9 Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Sat, 9 Apr 2022 16:36:26 +0200
Subject: [PATCH 0960/2085] Introduce 3 fb calc options: NO_SOF_BY_USER,
 SOF_BY_AUDIO_D, SOF_BY_USER

---
 src/class/audio/audio_device.c | 84 ++++++++++++++++++++++++----------
 src/class/audio/audio_device.h | 70 ++++++++++++++++++++++------
 2 files changed, 117 insertions(+), 37 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 434bfdcc6..2e2653e48 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -305,11 +305,12 @@ typedef struct
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-#if !CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER
   uint32_t fb_val;                                                                        // Feedback value for asynchronous mode (in 16.16 format).
+  uint8_t fb_n_frames;                                                                    // Number of (micro)frames used to estimate feedback value
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
   volatile uint32_t fb_val;                                                               // Feedback value for asynchronous mode (in 16.16 format).
   uint8_t fb_n_frames;                                                                    // Number of (micro)frames used to estimate feedback value
   volatile uint8_t fb_n_frames_current;                                                   // Current (micro)frame number
@@ -328,10 +329,15 @@ typedef struct
   uint64_t fb_param_factor_N;                                                       // Numerator of feedback parameter coefficient
   uint64_t fb_param_factor_D;                                                       // Denominator of feedback parameter coefficient
 #endif
+#endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER
+  volatile uint32_t fb_val;                                                               // Feedback value for asynchronous mode (in 16.16 format).
+  uint8_t fb_n_frames;                                                                    // Number of (micro)frames used to estimate feedback value
 #endif
 
-#endif
-#endif
+#endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
   tu_fifo_t ep_in_ff;
@@ -445,7 +451,7 @@ static inline uint8_t tu_desc_subtype(void const* desc)
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER)
 static bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
 #endif
 
@@ -1572,6 +1578,8 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
     usbd_edpt_close(rhport, audio->ep_fb);
     audio->ep_fb = 0;
+    audio->fb_n_frames = 0;
+
 #endif
   }
 #endif
@@ -1631,7 +1639,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
 #endif
             // Invoke callback - can be used to trigger data sampling if not already running
-//            if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+            //            if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
 
             // Schedule first transmit if alternate interface is not zero i.e. streaming is disabled - in case no sample data is available a ZLP is loaded
             // It is necessary to trigger this here since the refill is done with an RX FIFO empty interrupt which can only trigger if something was in there
@@ -1665,10 +1673,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
             // In case of asynchronous EP, call Cb after ep_fb is set
-//            if ( !(desc_ep->bmAttributes.sync == 0x01 && audio->ep_fb == 0) )
-//            {
-//              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
-//            }
+            //            if ( !(desc_ep->bmAttributes.sync == 0x01 && audio->ep_fb == 0) )
+            //            {
+            //              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+            //            }
 #else
             // Invoke callback
             if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
@@ -1685,19 +1693,22 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
           if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1)   // Check if usage is explicit data feedback
           {
             audio->ep_fb = ep_addr;
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
-            usbd_sof_enable(rhport, true);       // Enable SOF interrupt
             audio->fb_n_frames = desc_ep->bInterval;
+
+#if ((CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER) || (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER))
+            usbd_sof_enable(rhport, true);       // Enable SOF interrupt
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
             audio->fb_n_frames_current = 0;
             audio->fb_n_cycles_old = 0;
 #endif
 
-//            // Invoke callback after ep_out is set
-//            if (audio->ep_out != 0)
-//            {
-//              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
-//            }
+            //            // Invoke callback after ep_out is set
+            //            if (audio->ep_out != 0)
+            //            {
+            //              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
+            //            }
           }
 #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -1721,7 +1732,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   }
 
   // Disable SOF interrupt if no driver has any enabled feedback EP
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && ((CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER) || (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER))
 
   bool disable = true;
 
@@ -2025,7 +2036,14 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
   return false;
 }
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && ((CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER) || (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER))
+uint8_t tud_audio_n_get_fb_n_frames(uint8_t func_id)
+{
+  return _audiod_fct[func_id].fb_n_frames;
+}
+#endif
+
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER)
 
 // This function must be called from the user within the tud_audio_set_itf_cb(rhport, p_request) callback function, where p_request needs to be checked as
 // uint8_t const itf = tu_u16_low(p_request->wIndex);
@@ -2081,12 +2099,14 @@ TU_ATTR_WEAK bool tud_audio_set_fb_params(uint8_t func_id, uint32_t f_m, uint32_
 }
 #endif
 
-void audiod_sof (uint8_t rhport, uint32_t frame_count)
+TU_ATTR_WEAK void audiod_sof (uint8_t rhport, uint32_t frame_count)
 {
   (void) rhport;
   (void) frame_count;         // frame_count is not used since some devices may not provide the frame count value
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+
+#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER)
 
   // Determine feedback value - The feedback method is described in 5.12.4.2 of the USB 2.0 spec
   // Boiled down, the feedback value Ff = n_samples / (micro)frame.
@@ -2136,7 +2156,23 @@ void audiod_sof (uint8_t rhport, uint32_t frame_count)
     }
   }
 
-#endif
+#endif // (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER)
+
+#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER)
+  // Iterate over audio functions and call callback function
+  for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
+  {
+    audiod_function_t* audio = &_audiod_fct[i];
+
+    if (audio->ep_fb != 0)
+    {
+      tud_audio_sof_isr_cb(i, frame_count);
+    }
+  }
+
+#endif // (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER)
+
+#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 }
 
 bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_request_t const * p_request, void* data, uint16_t len)
@@ -2416,7 +2452,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
 static bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
 #else
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index e5eaed9c7..e8721cf27 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -191,13 +191,24 @@
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION     0                             // 0 or 1
 #endif
 
+// Possible options for determination of feedback value
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER                 1         // Feedback value must be determined by the user itself and set by use of tud_audio_n_fb_set(). The feedback value may be determined e.g. from some fill status of some FIFO buffer. Advantage: No ISR interrupt is enabled, hence the CPU need not to handle an ISR every 1ms or 125us and thus less CPU load, disadvantage: typically a larger FIFO is needed to compensate for jitter (e.g. 8 frames), i.e. a larger delay is introduced.
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER            2         // Feedback value is calculated within the audio driver by use of SOF interrupt. The driver needs information about the master clock f_m from which the audio sample frequency f_s is derived, f_s itself, and the cycle count of f_m at time of the SOF interrupt (e.g. by use of a hardware counter) - see tud_audio_set_fb_params(). Advantage: Reduced jitter in the feedback value computation, hence, the receive FIFO can be smaller (e.g. 2 frames) and thus a smaller delay is possible, disadvantage: higher CPU load due to SOF ISR handling every frame i.e. 1ms or 125us. This option is a great starting point to try the SOF ISR option but depending on your hardware setup (performance of the CPU) it might not work. If so, figure out why and use the next option. (The most critical point is the reading of the cycle counter value of f_m. It is read from within the SOF ISR - see: audiod_sof() -, hence, the ISR must has a high priority such that no software dependent "random" delay i.e. jitter is introduced).
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER                    3         // Feedback value is determined by the user by use of SOF interrupt. The user may use tud_audio_sof_isr_cb() which is called every SOF (of course only invoked when an alternate interface other than zero was set). The number of frames used to determine the feedback value for the currently active alternate setting can be get by tud_audio_get_fb_n_frames(). The feedback value must be set by use of tud_audio_n_fb_set().
+
 // Determine feedback value within SOF ISR within audio driver - if disabled the user has to call tud_audio_n_fb_set() with a suitable feedback value on its own. If done within audio driver SOF ISR, tud_audio_n_fb_set() is disabled for user
-#ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR    0                             // 0 or 1
+#ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION
+#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION                                CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER
+#endif
+
+#ifdef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION
+#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER)
+#error Unknown CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION. Possible choices are: CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER, CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER, or CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER!
+#endif
 #endif
 
 // Feeback calculation mode
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
 
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT     1
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT                  2
@@ -484,6 +495,8 @@ TU_ATTR_WEAK bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_byte
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 TU_ATTR_WEAK bool tud_audio_fb_done_cb(uint8_t rhport);
 
+#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER)
+
 // This function is used to provide data rate feedback from an asynchronous sink. Feedback value will be sent at FB endpoint interval till it's changed.
 //
 // The feedback format is specified to be 16.16 for HS and 10.14 for FS devices (see Universal Serial Bus Specification Revision 2.0 5.12.4.2). By default,
@@ -494,15 +507,16 @@ TU_ATTR_WEAK bool tud_audio_fb_done_cb(uint8_t rhport);
 // driver can work with either format. So a good compromise is to keep format correction disabled and stick to 16.16 format.
 
 // Feedback value can be determined from within the SOF ISR of the audio driver. This should reduce jitter. If the feature is used, the user can not set the feedback value.
-# if !CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
 static inline bool tud_audio_fb_set(uint32_t feedback);
-# else
 
-// This callback function is called once the feedback value needs to be updated within the SOF ISR in the audio class. To determine the feedback value, some
-// parameters need to be given. The user must implement this callback function and provide the current cycle count of the master clock.
-// The feedback endpoint number can be used to identify the correct audio function in case multiple audio functions were defined.
-TU_ATTR_WEAK uint32_t tud_audio_n_get_fm_n_cycles_cb(uint8_t rhport, uint8_t ep_fb);
+uint8_t tud_audio_n_get_fb_n_frames(uint8_t func_id);
+static inline uint8_t tud_audio_get_fb_n_frames();
+
+#endif // (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER)
+
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
 
 // f_m : Main clock frequency in Hz i.e. master clock to which sample clock is locked
 // f_s : Current sample rate in Hz
@@ -513,10 +527,34 @@ TU_ATTR_WEAK uint32_t tud_audio_n_get_fm_n_cycles_cb(uint8_t rhport, uint8_t ep_
 // uint8_t const alt = tu_u16_low(p_request->wValue);
 // such that tud_audio_set_fb_params() gets called with the parameters corresponding to the defined interface and alternate setting
 // Also, start the main clock cycle counter (or reset its value) within tud_audio_set_itf_cb()
-TU_ATTR_WEAK bool tud_audio_set_fb_params(uint8_t func_id, uint32_t f_m, uint32_t f_s, uint32_t * p_cycle_count);
-#endif
+bool tud_audio_set_fb_params(uint8_t func_id, uint32_t f_m, uint32_t f_s, uint32_t * p_cycle_count);
 
-#endif
+#endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
+
+#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER)
+
+// This function is used to provide data rate feedback from an asynchronous sink. Feedback value will be sent at FB endpoint interval till it's changed.
+//
+// The feedback format is specified to be 16.16 for HS and 10.14 for FS devices (see Universal Serial Bus Specification Revision 2.0 5.12.4.2). By default,
+// the choice of format is left to the caller and feedback argument is sent as-is. If CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION is set, then tinyusb
+// expects 16.16 format and handles the conversion to 10.14 on FS.
+//
+// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the
+// driver can work with either format. So a good compromise is to keep format correction disabled and stick to 16.16 format.
+
+// Feedback value can be determined from within the SOF ISR of the audio driver. This should reduce jitter. If the feature is used, the user can not set the feedback value.
+
+bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
+static inline bool tud_audio_fb_set(uint32_t feedback);
+
+uint8_t tud_audio_n_get_fb_n_frames(uint8_t func_id);
+static inline uint8_t tud_audio_get_fb_n_frames();
+
+TU_ATTR_WEAK void tud_audio_sof_isr_cb(uint8_t func_id, uint32_t frame);
+
+#endif // (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER)
+
+#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
 TU_ATTR_WEAK bool tud_audio_int_ctr_done_cb(uint8_t rhport, uint16_t n_bytes_copied);
@@ -657,11 +695,17 @@ static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t l
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && !CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_WITHIN_SOF_ISR
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && ((CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER) || (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER))
 static inline bool tud_audio_fb_set(uint32_t feedback)
 {
   return tud_audio_n_fb_set(0, feedback);
 }
+
+static inline uint8_t tud_audio_get_fb_n_frames()
+{
+  return tud_audio_n_get_fb_n_frames(0);
+}
+
 #endif
 
 //--------------------------------------------------------------------+

From cc5a4720e5c1295eacf02c7b81fc4454f29cfaa4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 14 Apr 2022 21:51:49 +0700
Subject: [PATCH 0961/2085] catch up with pio lib

---
 .../hid_boot_interface/src/tusb_config.h      |   3 +
 hw/bsp/rp2040/family.cmake                    |   5 +-
 lib/Pico-PIO-USB                              |   2 +-
 .../raspberrypi/pio_usb/dcd_pio_usb.c         | 234 ++++++++++++++++++
 .../raspberrypi/pio_usb/hcd_pio_usb.c         |  28 +--
 5 files changed, 254 insertions(+), 18 deletions(-)
 create mode 100644 src/portable/raspberrypi/pio_usb/dcd_pio_usb.c

diff --git a/examples/device/hid_boot_interface/src/tusb_config.h b/examples/device/hid_boot_interface/src/tusb_config.h
index d4f67e7ba..c8bb8a807 100644
--- a/examples/device/hid_boot_interface/src/tusb_config.h
+++ b/examples/device/hid_boot_interface/src/tusb_config.h
@@ -41,6 +41,9 @@
 
 // Use raspberry pio-usb for device
 #define CFG_TUD_RPI_PIO_USB            1
+#if CFG_TUD_RPI_PIO_USB
+#define BOARD_DEVICE_RHPORT_NUM 1
+#endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
 #ifndef BOARD_DEVICE_RHPORT_NUM
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index b186fc78e..d872c35ea 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -31,6 +31,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/common/tusb_fifo.c
 			${TOP}/lib/Pico-PIO-USB/pio_usb.c
 			${TOP}/lib/Pico-PIO-USB/pio_usb_host.c
+			${TOP}/lib/Pico-PIO-USB/pio_usb_device.c
 			${TOP}/lib/Pico-PIO-USB/pio_usb_hw.c
 			${TOP}/lib/Pico-PIO-USB/usb_crc.c
 			)
@@ -69,8 +70,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	add_library(tinyusb_device_base INTERFACE)
 	target_sources(tinyusb_device_base INTERFACE
 			${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c
-		  ${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
 			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
+		  ${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
 			${TOP}/src/device/usbd.c
 			${TOP}/src/device/usbd_control.c
 			${TOP}/src/class/audio/audio_device.c
@@ -92,13 +93,13 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	target_sources(tinyusb_host_base INTERFACE
 			${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
 			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
+		  ${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
 			${TOP}/src/host/usbh.c
 			${TOP}/src/host/hub.c
 			${TOP}/src/class/cdc/cdc_host.c
 			${TOP}/src/class/hid/hid_host.c
 			${TOP}/src/class/msc/msc_host.c
 			${TOP}/src/class/vendor/vendor_host.c
-		  ${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
 			)
 
 	# Sometimes have to do host specific actions in mostly common functions
diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 4993f4a1d..84a00b976 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 4993f4a1df03c8af13c8091052a6274e8c333bc0
+Subproject commit 84a00b976041d8c34cf660fda6fa88198c9721dc
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
new file mode 100644
index 000000000..08d8b6086
--- /dev/null
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -0,0 +1,234 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && CFG_TUD_RPI_PIO_USB
+
+#include "pico.h"
+#include "hardware/pio.h"
+#include "pio_usb.h"
+
+#include "device/dcd.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+#define RHPORT_OFFSET     1
+#define RHPORT_PIO(_x)    ((_x)-RHPORT_OFFSET)
+
+static uint8_t new_addr = 0;
+
+//-------------  -------------//
+static usb_device_t *usb_device = NULL;
+static usb_descriptor_buffers_t desc;
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+
+// Initialize controller to device mode
+void dcd_init (uint8_t rhport)
+{
+  (void) rhport;
+
+  static pio_usb_configuration_t config = PIO_USB_DEFAULT_CONFIG;
+  usb_device = pio_usb_device_init(&config, &desc);
+}
+
+// Enable device interrupt
+void dcd_int_enable (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Disable device interrupt
+void dcd_int_disable (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
+{
+  // store addr, will update crc5 lut when status is complete
+  new_addr = dev_addr;
+
+  dcd_edpt_xfer(rhport, 0x80, NULL, 0);
+}
+
+// Wake up host
+void dcd_remote_wakeup (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Connect by enabling internal pull-up resistor on D+/D-
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Disconnect by disabling internal pull-up resistor on D+/D-
+void dcd_disconnect(uint8_t rhport)
+{
+  (void) rhport;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+  (void) ep_desc;
+  return false;
+}
+
+void dcd_edpt_close_all (uint8_t rhport)
+{
+  (void) rhport;
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  return pio_usb_device_endpoint_transfer(pio_rhport, ep_addr, buffer, total_bytes);
+}
+
+// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+  (void) rhport;
+  (void) ep_addr;
+  (void) ff;
+  (void) total_bytes;
+  return false;
+}
+
+// Stall endpoint
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  (void) ep_addr;
+}
+
+// clear stall, data toggle is also reset to DATA0
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  (void) ep_addr;
+}
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+extern void update_ep0_crc5_lut(uint8_t addr);
+
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_t* port, uint32_t flag)
+{
+  volatile uint32_t* ep_reg;
+  xfer_result_t result;
+
+  if ( flag == PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
+  {
+    ep_reg = &port->ep_complete;
+    result = XFER_RESULT_SUCCESS;
+  }
+  else if ( flag == PIO_USB_INTS_ENDPOINT_ERROR_BITS )
+  {
+    ep_reg = &port->ep_error;
+    result = XFER_RESULT_FAILED;
+  }
+  else if ( flag == PIO_USB_INTS_ENDPOINT_STALLED_BITS )
+  {
+    ep_reg = &port->ep_stalled;
+    result = XFER_RESULT_STALLED;
+  }
+  else
+  {
+    // something wrong
+    return;
+  }
+
+  const uint32_t ep_all = *ep_reg;
+
+  for(uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++)
+  {
+    uint32_t const mask = (1u << ep_idx);
+
+    if (ep_all & mask)
+    {
+      pio_hw_endpoint_t* ep = PIO_USB_HW_EP(ep_idx);
+      uint8_t const tu_rhport = port - PIO_USB_HW_RPORT(0) + 1;
+
+      // address is changed, update crc5 lut
+      if (new_addr && ep->ep_num == 0x80 && ep->actual_len == 0)
+      {
+        update_ep0_crc5_lut(new_addr);
+        new_addr = 0;
+      }
+
+      dcd_event_xfer_complete(tu_rhport, ep->ep_num, ep->actual_len, result, true);
+    }
+  }
+
+  // clear all
+  (*ep_reg) &= ~ep_all;
+}
+
+// IRQ Handler
+void __no_inline_not_in_flash_func(pio_usb_device_irq_handler)(uint8_t root_id)
+{
+  uint8_t const tu_rhport = root_id + 1;
+  pio_hw_root_port_t* port = PIO_USB_HW_RPORT(root_id);
+  uint32_t const ints = port->ints;
+
+  if (ints & PIO_USB_INTS_RESET_END_BITS)
+  {
+    new_addr = 0;
+    dcd_event_bus_reset(tu_rhport, TUSB_SPEED_FULL, true);
+  }
+
+  if (ints & PIO_USB_INTS_SETUP_REQ_BITS)
+  {
+    dcd_event_setup_received(tu_rhport, port->setup_packet, true);
+  }
+
+  if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
+  {
+    handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_COMPLETE_BITS);
+  }
+
+  // clear all
+  port->ints &= ~ints;
+}
+
+#endif
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index c2ef54b9e..4bd318448 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -116,19 +116,19 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   bool const need_pre = (dev_tree.hub_addr && dev_tree.speed == TUSB_SPEED_LOW);
 
   rhport = RHPORT_PIO(rhport);
-  return pio_usb_endpoint_open(rhport, dev_addr, (uint8_t const*) desc_ep, need_pre);
+  return pio_usb_host_endpoint_open(rhport, dev_addr, (uint8_t const*) desc_ep, need_pre);
 }
 
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
   rhport = RHPORT_PIO(rhport);
-  return pio_usb_endpoint_transfer(rhport, dev_addr, ep_addr, buffer, buflen);
+  return pio_usb_host_endpoint_transfer(rhport, dev_addr, ep_addr, buffer, buflen);
 }
 
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   rhport = RHPORT_PIO(rhport);
-  return pio_usb_endpoint_send_setup(rhport, dev_addr, setup_packet);
+  return pio_usb_host_send_setup(rhport, dev_addr, setup_packet);
 }
 
 //bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
@@ -153,7 +153,7 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
   return true;
 }
 
-void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_t* port, uint32_t flag)
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_t* port, uint32_t flag)
 {
   volatile uint32_t* ep_reg;
   xfer_result_t result;
@@ -200,37 +200,35 @@ void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_t* port
 void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id)
 {
   pio_hw_root_port_t* port = PIO_USB_HW_RPORT(root_id);
+  uint32_t const ints = port->ints;
 
-  if ( port->ints & PIO_USB_INTS_CONNECT_BITS )
+  if ( ints & PIO_USB_INTS_CONNECT_BITS )
   {
-    port->ints &= ~PIO_USB_INTS_CONNECT_BITS;
-
     hcd_event_device_attach(root_id+1, true);
   }
 
-  if ( port->ints & PIO_USB_INTS_DISCONNECT_BITS )
+  if ( ints & PIO_USB_INTS_DISCONNECT_BITS )
   {
-    port->ints &= ~PIO_USB_INTS_DISCONNECT_BITS;
     hcd_event_device_remove(root_id+1, true);
   }
 
-  if ( port->ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
+  if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
   {
-    port->ints &= ~PIO_USB_INTS_ENDPOINT_COMPLETE_BITS;
     handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_COMPLETE_BITS);
   }
 
-  if ( port->ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS )
+  if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS )
   {
-    port->ints &= ~PIO_USB_INTS_ENDPOINT_ERROR_BITS;
     handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_ERROR_BITS);
   }
 
-  if ( port->ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS )
+  if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS )
   {
-    port->ints &= ~PIO_USB_INTS_ENDPOINT_STALLED_BITS;
     handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_STALLED_BITS);
   }
+
+  // clear all
+  port->ints &= ~ints;
 }
 
 #endif

From 05bfc1a9eba9fc901c35bdd1844cf962c5732310 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 15 Apr 2022 01:04:12 +0700
Subject: [PATCH 0962/2085] pio device works well

---
 examples/device/hid_boot_interface/src/main.c |  2 -
 lib/Pico-PIO-USB                              |  2 +-
 .../raspberrypi/pio_usb/dcd_pio_usb.c         | 45 +++++++------------
 3 files changed, 18 insertions(+), 31 deletions(-)

diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index ed7f235b7..031b17a2e 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -61,8 +61,6 @@ int main(void)
 
   while (1)
   {
-    pio_usb_device_task();
-
     tud_task(); // tinyusb device task
     led_blinking_task();
 
diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 84a00b976..d2b37b42b 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 84a00b976041d8c34cf660fda6fa88198c9721dc
+Subproject commit d2b37b42befb6c761433b3c164c59a049721762f
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index 08d8b6086..dc9cbb45b 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -41,8 +41,6 @@
 #define RHPORT_OFFSET     1
 #define RHPORT_PIO(_x)    ((_x)-RHPORT_OFFSET)
 
-static uint8_t new_addr = 0;
-
 //-------------  -------------//
 static usb_device_t *usb_device = NULL;
 static usb_descriptor_buffers_t desc;
@@ -75,10 +73,12 @@ void dcd_int_disable (uint8_t rhport)
 // Receive Set Address request, mcu port must also include status IN response
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-  // store addr, will update crc5 lut when status is complete
-  new_addr = dev_addr;
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
 
-  dcd_edpt_xfer(rhport, 0x80, NULL, 0);
+  // must be called before queuing status
+  pio_usb_device_set_address(pio_rhport, dev_addr);
+
+  pio_usb_device_endpoint_transfer(pio_rhport, 0x80, NULL, 0);
 }
 
 // Wake up host
@@ -104,11 +104,10 @@ void dcd_disconnect(uint8_t rhport)
 //--------------------------------------------------------------------+
 
 // Configure endpoint's registers according to descriptor
-bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
 {
-  (void) rhport;
-  (void) ep_desc;
-  return false;
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
+  return pio_usb_device_endpoint_open(pio_rhport, (uint8_t const*) desc_ep);
 }
 
 void dcd_edpt_close_all (uint8_t rhport)
@@ -119,19 +118,19 @@ void dcd_edpt_close_all (uint8_t rhport)
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
-  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_device_endpoint_transfer(pio_rhport, ep_addr, buffer, total_bytes);
 }
 
 // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
-  (void) rhport;
-  (void) ep_addr;
-  (void) ff;
-  (void) total_bytes;
-  return false;
-}
+//bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+//{
+//  (void) rhport;
+//  (void) ep_addr;
+//  (void) ff;
+//  (void) total_bytes;
+//  return false;
+//}
 
 // Stall endpoint
 void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
@@ -150,7 +149,6 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
-extern void update_ep0_crc5_lut(uint8_t addr);
 
 static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_t* port, uint32_t flag)
 {
@@ -188,14 +186,6 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_
     {
       pio_hw_endpoint_t* ep = PIO_USB_HW_EP(ep_idx);
       uint8_t const tu_rhport = port - PIO_USB_HW_RPORT(0) + 1;
-
-      // address is changed, update crc5 lut
-      if (new_addr && ep->ep_num == 0x80 && ep->actual_len == 0)
-      {
-        update_ep0_crc5_lut(new_addr);
-        new_addr = 0;
-      }
-
       dcd_event_xfer_complete(tu_rhport, ep->ep_num, ep->actual_len, result, true);
     }
   }
@@ -213,7 +203,6 @@ void __no_inline_not_in_flash_func(pio_usb_device_irq_handler)(uint8_t root_id)
 
   if (ints & PIO_USB_INTS_RESET_END_BITS)
   {
-    new_addr = 0;
     dcd_event_bus_reset(tu_rhport, TUSB_SPEED_FULL, true);
   }
 

From 00a0e3f21ba588f892022159e435938b48305b99 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 15 Apr 2022 20:14:47 +0700
Subject: [PATCH 0963/2085] update lib pio

---
 lib/Pico-PIO-USB | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index d2b37b42b..ed84b4de8 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit d2b37b42befb6c761433b3c164c59a049721762f
+Subproject commit ed84b4de88e7c22bb56cb53bf85f1a2c5dd8b8fc

From b5a9537eea81bd6ffd8d575dbd2b5823c2fc1f0e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 16 Apr 2022 01:19:51 +0700
Subject: [PATCH 0964/2085] support pio dcd endpiont stall

---
 lib/Pico-PIO-USB                               | 2 +-
 src/portable/raspberrypi/pio_usb/dcd_pio_usb.c | 7 +++++--
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index ed84b4de8..d6712cad5 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit ed84b4de88e7c22bb56cb53bf85f1a2c5dd8b8fc
+Subproject commit d6712cad5bfbddb25647974f0d583596e703c06f
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index dc9cbb45b..7744a11cd 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -136,14 +136,17 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
-  (void) ep_addr;
+  pio_hw_endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
+  ep->stalled = true;
 }
 
 // clear stall, data toggle is also reset to DATA0
 void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
-  (void) ep_addr;
+  pio_hw_endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
+  ep->data_id = 0;
+  ep->stalled = false;
 }
 
 //--------------------------------------------------------------------+

From 11f0ffd9a833f4ea9b28fd12f4dff03e9bb99331 Mon Sep 17 00:00:00 2001
From: Reinhard Panhuber <panhuber_reinhard@gmx.at>
Date: Sat, 16 Apr 2022 14:47:42 +0200
Subject: [PATCH 0965/2085] Generalize feedback value min and max

---
 src/class/audio/audio_device.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 2e2653e48..b0a49fb04 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -312,6 +312,8 @@ typedef struct
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
   volatile uint32_t fb_val;                                                               // Feedback value for asynchronous mode (in 16.16 format).
+  uint32_t fb_val_min;                                                                    // Maximum allowed feedback value according to UAC2 FMT-2.0 section 2.3.1.1.
+  uint32_t fb_val_max;                                                                    // Maximum allowed feedback value according to UAC2 FMT-2.0 section 2.3.1.1.
   uint8_t fb_n_frames;                                                                    // Number of (micro)frames used to estimate feedback value
   volatile uint8_t fb_n_frames_current;                                                   // Current (micro)frame number
   volatile uint32_t fb_n_cycles_old;                                                      // Old cycle count
@@ -2094,6 +2096,9 @@ TU_ATTR_WEAK bool tud_audio_set_fb_params(uint8_t func_id, uint32_t f_m, uint32_
   audio->fb_param_factor_D = (uint64_t)f_m * audio->fb_n_frames;
 #endif
 
+  audio->fb_val_min = ((TUSB_SPEED_FULL == tud_speed_get() ? (f_s/1000) : (f_s/8000)) - 1) << 16;   // Minimal value in 16.16 format for full speed (1ms per frame) or high speed (125 us per frame)
+  audio->fb_val_max = ((TUSB_SPEED_FULL == tud_speed_get() ? (f_s/1000) : (f_s/8000)) + 1) << 16;   // Maximum value in 16.16 format
+
   return true;
 
 }
@@ -2139,16 +2144,18 @@ TU_ATTR_WEAK void audiod_sof (uint8_t rhport, uint32_t frame_count)
         feedback = ((n_cylces - audio->fb_n_cycles_old) << 3) * audio->fb_param_factor_N / audio->fb_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
 #endif
 
-        // Buffer count checks ?
+        // For Windows: https://docs.microsoft.com/en-us/windows-hardware/drivers/audio/usb-2-0-audio-drivers
+        // The size of isochronous packets created by the device must be within the limits specified in FMT-2.0 section 2.3.1.1. This means that the deviation of actual packet size from nominal size must not exceed +/- one audio slot (audio slot = channel count samples).
 
-        // Magic checks - where are they from?
-        if (feedback > 2949166){        // 45.0007 in 16.16 format
-          feedback = 2949166;
+        if (feedback > audio->fb_val_max){
+          feedback = audio->fb_val_max;
         }
-        if ( feedback < 2883630) {      // 44.0007 in 16.16 format
-          feedback = 2883630;
+        if ( feedback < audio->fb_val_min) {
+          feedback = audio->fb_val_min;
         }
 
+        // Buffer count checks ?
+
         tud_audio_n_fb_set(i, feedback);
         audio->fb_n_frames_current = 0;
         audio->fb_n_cycles_old = n_cylces;

From 16c13bc110fb0959e704b417706dd303afc69981 Mon Sep 17 00:00:00 2001
From: Skyler Mansfield <skyler.mansfield.21@gmail.com>
Date: Sun, 17 Apr 2022 01:16:49 +0100
Subject: [PATCH 0966/2085] tusb_types: Added descriptive strings for edpt_dir
 and edpt_type

---
 src/common/tusb_types.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index e2fa17532..7eab396ef 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -513,6 +513,16 @@ static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep)
   return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0);
 }
 
+static inline const char *tu_edpt_dir_str(tusb_dir_t dir) {
+  static const char *str[] = {"out", "in"};
+  return str[dir];
+}
+
+static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) {
+  static const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
+  return str[t];
+}
+
 //--------------------------------------------------------------------+
 // Descriptor helper
 //--------------------------------------------------------------------+

From 35668fc523c7c972bf91f32dbb3b50ad8b4f3c74 Mon Sep 17 00:00:00 2001
From: Skyler Mansfield <skyler.mansfield.21@gmail.com>
Date: Sun, 17 Apr 2022 01:30:03 +0100
Subject: [PATCH 0967/2085] hcd_rp2040: Add bulk in/out+interrupt out support.
 Added support for allocating hw_endpoints for non-interrupt endpoints. Allow
 endpoints to be used in either direction by updating bit checks.

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 33 +++++++++++++-------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 234bea203..0c7a5220d 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -139,16 +139,20 @@ static void hw_handle_buff_status(void)
     for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++)
     {
         // EPX is bit 0
-        // IEP1 is bit 2
-        // IEP2 is bit 4
-        // IEP3 is bit 6
+        // IEP1 IN  is bit 2
+        // IEP1 OUT is bit 3
+        // IEP2 IN  is bit 4
+        // IEP2 OUT is bit 5
+        // IEP3 IN  is bit 6
+        // IEP3 OUT is bit 7
         // etc
-        bit = 1 << (i*2);
-
-        if (remaining_buffers & bit)
-        {
-            remaining_buffers &= ~bit;
-            _handle_buff_status_bit(bit, &ep_pool[i]);
+        for(int j = 0; j < 2; j++){
+            bit = 1 << (i*2+j);
+            if (remaining_buffers & bit)
+            {
+                remaining_buffers &= ~bit;
+                _handle_buff_status_bit(bit, &ep_pool[i]);
+            }
         }
     }
 
@@ -259,10 +263,10 @@ static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
 {
     struct hw_endpoint *ep = NULL;
 
-    if (transfer_type == TUSB_XFER_INTERRUPT)
+    if (transfer_type != TUSB_XFER_CONTROL)
     {
         ep = _next_free_interrupt_ep();
-        pico_info("Allocate interrupt ep %d\n", ep->interrupt_num);
+        pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num);
         assert(ep);
         ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
         ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
@@ -320,8 +324,9 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
     pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
     ep->configured = true;
 
-    if (bmInterval)
+    if (ep != &epx)
     {
+        // Endpoint has its own addr_endp and interrupt bits to be setup!
         // This is an interrupt endpoint
         // so need to set up interrupt endpoint address control register with:
         // device address
@@ -492,6 +497,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     // Get appropriate ep. Either EPX or interrupt endpoint
     struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
     assert(ep);
+    // Should we maybe be able to check if endpt is busy/active instead?
+    if(ep->active)
+        return false;
 
     // Control endpoint can change direction 0x00 <-> 0x80
     if ( ep_addr != ep->ep_addr )
@@ -535,6 +543,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 
     // Configure EP0 struct with setup info for the trans complete
     struct hw_endpoint *ep = _hw_endpoint_allocate(0);
+    assert(ep == &epx);
 
     // EP0 out
     _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);

From a32cb1bb93ce986af9ed83f5d378c26bb4df2b1e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 18 Apr 2022 17:49:21 +0700
Subject: [PATCH 0968/2085] clean up pio driver

---
 lib/Pico-PIO-USB                              |  2 +-
 src/device/dcd.h                              | 32 ++++++++++++++---
 src/device/usbd.c                             | 36 ++-----------------
 src/device/usbd.h                             |  2 +-
 .../raspberrypi/pio_usb/dcd_pio_usb.c         |  7 ++--
 .../raspberrypi/pio_usb/hcd_pio_usb.c         |  6 ++--
 6 files changed, 39 insertions(+), 46 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index d6712cad5..98e3feefc 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit d6712cad5bfbddb25647974f0d583596e703c06f
+Subproject commit 98e3feefcd1c7218bced0ea2ea35530fd1b550e4
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 8efbc90ef..bc68c9be6 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -174,16 +174,40 @@ void dcd_edpt_clear_stall     (uint8_t rhport, uint8_t ep_addr);
 extern void dcd_event_handler(dcd_event_t const * event, bool in_isr);
 
 // helper to send bus signal event
-extern void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr);
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr)
+{
+  dcd_event_t event = { .rhport = rhport, .event_id = eid };
+  dcd_event_handler(&event, in_isr);
+}
 
 // helper to send bus reset event
-extern void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr);
+TU_ATTR_ALWAYS_INLINE static inline  void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr)
+{
+  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET };
+  event.bus_reset.speed = speed;
+  dcd_event_handler(&event, in_isr);
+}
 
 // helper to send setup received
-extern void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr);
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr)
+{
+  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED };
+  memcpy(&event.setup_received, setup, 8);
+
+  dcd_event_handler(&event, in_isr);
+}
 
 // helper to send transfer complete event
-extern void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr);
+TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr)
+{
+  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE };
+
+  event.xfer_complete.ep_addr = ep_addr;
+  event.xfer_complete.len     = xferred_bytes;
+  event.xfer_complete.result  = result;
+
+  dcd_event_handler(&event, in_isr);
+}
 
 #ifdef __cplusplus
  }
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 7ab2660f4..8d5d54b86 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -265,7 +265,7 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 //--------------------------------------------------------------------+
 
 enum { RHPORT_INVALID = 0xFFu };
-static uint8_t _usbd_rhport = RHPORT_INVALID;
+static volatile uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // usbd_int_set() is used as mutex in OS NONE config
@@ -1065,7 +1065,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 //--------------------------------------------------------------------+
 // DCD Event Handler
 //--------------------------------------------------------------------+
-void dcd_event_handler(dcd_event_t const * event, bool in_isr)
+void __no_inline_not_in_flash_func(dcd_event_handler)(dcd_event_t const * event, bool in_isr)
 {
   switch (event->event_id)
   {
@@ -1115,38 +1115,6 @@ void dcd_event_handler(dcd_event_t const * event, bool in_isr)
   }
 }
 
-void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr)
-{
-  dcd_event_t event = { .rhport = rhport, .event_id = eid };
-  dcd_event_handler(&event, in_isr);
-}
-
-void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr)
-{
-  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET };
-  event.bus_reset.speed = speed;
-  dcd_event_handler(&event, in_isr);
-}
-
-void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr)
-{
-  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED };
-  memcpy(&event.setup_received, setup, 8);
-
-  dcd_event_handler(&event, in_isr);
-}
-
-void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr)
-{
-  dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE };
-
-  event.xfer_complete.ep_addr = ep_addr;
-  event.xfer_complete.len     = xferred_bytes;
-  event.xfer_complete.result  = result;
-
-  dcd_event_handler(&event, in_isr);
-}
-
 //--------------------------------------------------------------------+
 // USBD API For Class Driver
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd.h b/src/device/usbd.h
index b2bf8ba9d..32c82e75a 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -46,7 +46,7 @@ bool tud_inited(void);
 // Task function should be called in main/rtos loop
 void tud_task (void);
 
-// Check if there is pending events need proccessing by tud_task()
+// Check if there is pending events need processing by tud_task()
 bool tud_task_event_ready(void);
 
 // Interrupt handler, name alias to DCD
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index 7744a11cd..38867ea1c 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -78,7 +78,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
   // must be called before queuing status
   pio_usb_device_set_address(pio_rhport, dev_addr);
 
-  pio_usb_device_endpoint_transfer(pio_rhport, 0x80, NULL, 0);
+  dcd_edpt_xfer(rhport, 0x80, NULL, 0);
 }
 
 // Wake up host
@@ -118,8 +118,9 @@ void dcd_edpt_close_all (uint8_t rhport)
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
-  uint8_t const pio_rhport = RHPORT_PIO(rhport);
-  return pio_usb_device_endpoint_transfer(pio_rhport, ep_addr, buffer, total_bytes);
+  (void) rhport;
+  pio_hw_endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
+  return pio_usb_endpoint_transfer(ep, buffer, total_bytes);
 }
 
 // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 4bd318448..e311f16d0 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -51,7 +51,7 @@ static pio_usb_configuration_t pio_host_config = PIO_USB_DEFAULT_CONFIG;
 bool hcd_init(uint8_t rhport)
 {
   // To run USB SOF interrupt in core1, call this init in core1
-  pio_usb_host_controller_init(&pio_host_config);
+  pio_usb_host_init(&pio_host_config);
 
   return true;
 }
@@ -59,13 +59,13 @@ bool hcd_init(uint8_t rhport)
 void hcd_port_reset(uint8_t rhport)
 {
   rhport = RHPORT_PIO(rhport);
-  pio_usb_hw_port_reset_start(rhport);
+  pio_usb_host_port_reset_start(rhport);
 }
 
 void hcd_port_reset_end(uint8_t rhport)
 {
   rhport = RHPORT_PIO(rhport);
-  pio_usb_hw_port_reset_end(rhport);
+  pio_usb_host_port_reset_end(rhport);
 }
 
 bool hcd_port_connect_status(uint8_t rhport)

From 52190e7308c723df952c8bfced25f70d333e22fe Mon Sep 17 00:00:00 2001
From: Nikitarc <rtk@adastra-soft.com>
Date: Tue, 19 Apr 2022 21:53:00 +0200
Subject: [PATCH 0969/2085] Update dwc2_stm32.h

Support STM32H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
---
 src/portable/synopsys/dwc2/dwc2_stm32.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 469045ac4..c4a4d310f 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -56,6 +56,11 @@
   #define EP_FIFO_SIZE_FS 4096
   #define EP_MAX_HS       9
   #define EP_FIFO_SIZE_HS 4096
+  #if (! defined USB2_OTG_FS)
+    // H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
+    // USB_OTG_FS_PERIPH_BASE and OTG_FS_IRQn not defined
+    #define USB_OTG_FS_PERIPH_BASE  USB1_OTG_HS_PERIPH_BASE
+    #define OTG_FS_IRQn             OTG_HS_IRQn
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
   #include "stm32f7xx.h"

From a90839688c11338451729838e45ae3aaa58864fe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 20 Apr 2022 13:25:38 +0700
Subject: [PATCH 0970/2085] add msec timeout to osal_queue_receive(),
 tud_task() and tuh_task() both pending for event queue with timeout of 1 ms

---
 src/device/usbd.c                   |  3 +-
 src/host/usbh.c                     |  2 +-
 src/osal/osal.h                     | 22 +++++++--------
 src/osal/osal_freertos.h            | 29 ++++++++++---------
 src/osal/osal_mynewt.h              | 22 ++++++++-------
 src/osal/osal_none.h                | 28 +++++++++---------
 src/osal/osal_pico.h                | 44 +++++++++++++++--------------
 src/osal/osal_rtthread.h            | 28 +++++++++---------
 src/osal/osal_rtx4.h                | 28 +++++++++---------
 src/portable/sony/cxd56/dcd_cxd56.c |  2 +-
 src/tusb_option.h                   |  2 +-
 11 files changed, 109 insertions(+), 101 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 7ab2660f4..36b9c7cff 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -475,8 +475,7 @@ void tud_task (void)
   while (1)
   {
     dcd_event_t event;
-
-    if ( !osal_queue_receive(_usbd_q, &event) ) return;
+    if ( !osal_queue_receive(_usbd_q, &event, 1) ) return;
 
 #if CFG_TUSB_DEBUG >= 2
     if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG2("\r\n"); // extra line for setup
diff --git a/src/host/usbh.c b/src/host/usbh.c
index f534070de..ad90a1b1b 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -401,7 +401,7 @@ void tuh_task(void)
   while (1)
   {
     hcd_event_t event;
-    if ( !osal_queue_receive(_usbh_q, &event) ) return;
+    if ( !osal_queue_receive(_usbh_q, &event, 1) ) return;
 
     switch (event.event_id)
     {
diff --git a/src/osal/osal.h b/src/osal/osal.h
index 7111bbdb2..9d11866df 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -66,19 +66,19 @@ typedef void (*osal_task_func_t)( void * );
 // OSAL Porting API
 // Should be implemented as static inline function in osal_port.h header
 /*
-    static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
-    static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
-    static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec);
-    static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed
+   osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
+   bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
+   bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec);
+   void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed
 
-    static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef);
-    static inline bool osal_mutex_lock (osal_mutex_t sem_hdl, uint32_t msec);
-    static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl);
+   osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef);
+   bool osal_mutex_lock (osal_mutex_t sem_hdl, uint32_t msec);
+   bool osal_mutex_unlock(osal_mutex_t mutex_hdl);
 
-    static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
-    static inline bool osal_queue_receive(osal_queue_t qhdl, void* data);
-    static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
-    static inline bool osal_queue_empty(osal_queue_t qhdl);
+   osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
+   bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec);
+   bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
+   bool osal_queue_empty(osal_queue_t qhdl);
 */
 //--------------------------------------------------------------------+
 
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 69a026df5..c3a0756e1 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -40,7 +40,7 @@ extern "C" {
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-static inline void osal_task_delay(uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 {
   vTaskDelay( pdMS_TO_TICKS(msec) );
 }
@@ -51,12 +51,12 @@ static inline void osal_task_delay(uint32_t msec)
 typedef StaticSemaphore_t osal_semaphore_def_t;
 typedef SemaphoreHandle_t osal_semaphore_t;
 
-static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
 {
   return xSemaphoreCreateBinaryStatic(semdef);
 }
 
-static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
 {
   if ( !in_isr )
   {
@@ -78,13 +78,13 @@ static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
   }
 }
 
-static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
 {
   uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? portMAX_DELAY : pdMS_TO_TICKS(msec);
   return xSemaphoreTake(sem_hdl, ticks);
 }
 
-static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl)
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl)
 {
   xQueueReset(sem_hdl);
 }
@@ -95,17 +95,17 @@ static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl)
 typedef StaticSemaphore_t osal_mutex_def_t;
 typedef SemaphoreHandle_t osal_mutex_t;
 
-static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
   return xSemaphoreCreateMutexStatic(mdef);
 }
 
-static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
 {
   return osal_semaphore_wait(mutex_hdl, msec);
 }
 
-static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 {
   return xSemaphoreGive(mutex_hdl);
 }
@@ -114,7 +114,7 @@ static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 // QUEUE API
 //--------------------------------------------------------------------+
 
-// role device/host is used by OS NONE for mutex (disable usb isr) only
+// _int_set is not used with an RTOS
 #define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
   static _type _name##_##buf[_depth];\
   osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
@@ -130,17 +130,18 @@ typedef struct
 
 typedef QueueHandle_t osal_queue_t;
 
-static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
   return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
 }
 
-static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
 {
-  return xQueueReceive(qhdl, data, portMAX_DELAY);
+  uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? portMAX_DELAY : pdMS_TO_TICKS(msec);
+  return xQueueReceive(qhdl, data, ticks);
 }
 
-static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
 {
   if ( !in_isr )
   {
@@ -162,7 +163,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
   }
 }
 
-static inline bool osal_queue_empty(osal_queue_t qhdl)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
 {
   return uxQueueMessagesWaiting(qhdl) == 0;
 }
diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h
index 78a257cd6..b8ea2087c 100644
--- a/src/osal/osal_mynewt.h
+++ b/src/osal/osal_mynewt.h
@@ -36,7 +36,7 @@
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-static inline void osal_task_delay(uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 {
   os_time_delay( os_time_ms_to_ticks32(msec) );
 }
@@ -47,18 +47,18 @@ static inline void osal_task_delay(uint32_t msec)
 typedef struct os_sem  osal_semaphore_def_t;
 typedef struct os_sem* osal_semaphore_t;
 
-static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
 {
   return (os_sem_init(semdef, 0) == OS_OK) ? (osal_semaphore_t) semdef : NULL;
 }
 
-static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
 {
   (void) in_isr;
   return os_sem_release(sem_hdl) == OS_OK;
 }
 
-static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec)
 {
   uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec);
   return os_sem_pend(sem_hdl, ticks) == OS_OK;
@@ -75,18 +75,18 @@ static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
 typedef struct os_mutex osal_mutex_def_t;
 typedef struct os_mutex* osal_mutex_t;
 
-static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
   return (os_mutex_init(mdef) == OS_OK) ? (osal_mutex_t) mdef : NULL;
 }
 
-static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec)
 {
   uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec);
   return os_mutex_pend(mutex_hdl, ticks) == OS_OK;
 }
 
-static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 {
   return os_mutex_release(mutex_hdl) == OS_OK;
 }
@@ -116,7 +116,7 @@ typedef struct
 
 typedef osal_queue_def_t* osal_queue_t;
 
-static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
   if ( OS_OK != os_mempool_init(&qdef->mpool, qdef->depth, qdef->item_sz, qdef->buf, "usbd queue") ) return NULL;
   if ( OS_OK != os_mempool_init(&qdef->epool, qdef->depth, sizeof(struct os_event), qdef->evbuf, "usbd evqueue") ) return NULL;
@@ -125,8 +125,10 @@ static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
   return (osal_queue_t) qdef;
 }
 
-static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
 {
+  (void) msec; // os_eventq_get() does not take timeout, always behave as msec = WAIT_FOREVER
+
   struct os_event* ev;
   ev = os_eventq_get(&qhdl->evq);
 
@@ -161,7 +163,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
   return true;
 }
 
-static inline bool osal_queue_empty(osal_queue_t qhdl)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
 {
   return STAILQ_EMPTY(&qhdl->evq.evq_list);
 }
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 4217f0422..9c80e4548 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -46,13 +46,13 @@ typedef struct
 
 typedef osal_semaphore_def_t* osal_semaphore_t;
 
-static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
 {
   semdef->count = 0;
   return semdef;
 }
 
-static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
 {
   (void) in_isr;
   sem_hdl->count++;
@@ -60,7 +60,7 @@ static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
 }
 
 // TODO blocking for now
-static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
 {
   (void) msec;
 
@@ -70,7 +70,7 @@ static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
   return true;
 }
 
-static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
 {
   sem_hdl->count = 0;
 }
@@ -82,18 +82,18 @@ static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
 typedef osal_semaphore_def_t osal_mutex_def_t;
 typedef osal_semaphore_t osal_mutex_t;
 
-static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
   mdef->count = 1;
   return mdef;
 }
 
-static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
 {
   return osal_semaphore_wait(mutex_hdl, msec);
 }
 
-static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 {
   return osal_semaphore_post(mutex_hdl, false);
 }
@@ -120,27 +120,29 @@ typedef osal_queue_def_t* osal_queue_t;
   }
 
 // lock queue by disable USB interrupt
-static inline void _osal_q_lock(osal_queue_t qhdl)
+TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl)
 {
   // disable dcd/hcd interrupt
   qhdl->interrupt_set(false);
 }
 
 // unlock queue
-static inline void _osal_q_unlock(osal_queue_t qhdl)
+TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl)
 {
   // enable dcd/hcd interrupt
   qhdl->interrupt_set(true);
 }
 
-static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
   tu_fifo_clear(&qdef->ff);
   return (osal_queue_t) qdef;
 }
 
-static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
 {
+  (void) msec; // not used, always behave as msec = 0
+
   _osal_q_lock(qhdl);
   bool success = tu_fifo_read(&qhdl->ff, data);
   _osal_q_unlock(qhdl);
@@ -148,7 +150,7 @@ static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
   return success;
 }
 
-static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
 {
   if (!in_isr) {
     _osal_q_lock(qhdl);
@@ -165,7 +167,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
   return success;
 }
 
-static inline bool osal_queue_empty(osal_queue_t qhdl)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
 {
   // Skip queue lock/unlock since this function is primarily called
   // with interrupt disabled before going into low power mode
diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h
index 70432d22b..abef286b4 100644
--- a/src/osal/osal_pico.h
+++ b/src/osal/osal_pico.h
@@ -39,7 +39,7 @@
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-static inline void osal_task_delay(uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 {
   sleep_ms(msec);
 }
@@ -49,25 +49,25 @@ static inline void osal_task_delay(uint32_t msec)
 //--------------------------------------------------------------------+
 typedef struct semaphore osal_semaphore_def_t, *osal_semaphore_t;
 
-static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
 {
   sem_init(semdef, 0, 255);
   return semdef;
 }
 
-static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
 {
   (void) in_isr;
   sem_release(sem_hdl);
   return true;
 }
 
-static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
 {
   return sem_acquire_timeout_ms(sem_hdl, msec);
 }
 
-static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
 {
   sem_reset(sem_hdl, 0);
 }
@@ -78,21 +78,21 @@ static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
 //--------------------------------------------------------------------+
 typedef struct mutex osal_mutex_def_t, *osal_mutex_t;
 
-static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
-    mutex_init(mdef);
-    return mdef;
+  mutex_init(mdef);
+  return mdef;
 }
 
-static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
 {
-    return mutex_enter_timeout_ms(mutex_hdl, msec);
+  return mutex_enter_timeout_ms(mutex_hdl, msec);
 }
 
-static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 {
-    mutex_exit(mutex_hdl);
-    return true;
+  mutex_exit(mutex_hdl);
+  return true;
 }
 
 //--------------------------------------------------------------------+
@@ -121,26 +121,28 @@ typedef osal_queue_def_t* osal_queue_t;
   }
 
 // lock queue by disable USB interrupt
-static inline void _osal_q_lock(osal_queue_t qhdl)
+TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl)
 {
-    critical_section_enter_blocking(&qhdl->critsec);
+  critical_section_enter_blocking(&qhdl->critsec);
 }
 
 // unlock queue
-static inline void _osal_q_unlock(osal_queue_t qhdl)
+TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl)
 {
-    critical_section_exit(&qhdl->critsec);
+  critical_section_exit(&qhdl->critsec);
 }
 
-static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
   critical_section_init(&qdef->critsec);
   tu_fifo_clear(&qdef->ff);
   return (osal_queue_t) qdef;
 }
 
-static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
 {
+  (void) msec; // not used, always behave as msec = 0
+
   // TODO: revisit... docs say that mutexes are never used from IRQ context,
   //  however osal_queue_recieve may be. therefore my assumption is that
   //  the fifo mutex is not populated for queues used from an IRQ context
@@ -153,7 +155,7 @@ static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
   return success;
 }
 
-static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
 {
   // TODO: revisit... docs say that mutexes are never used from IRQ context,
   //  however osal_queue_recieve may be. therefore my assumption is that
@@ -170,7 +172,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
   return success;
 }
 
-static inline bool osal_queue_empty(osal_queue_t qhdl)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
 {
   // TODO: revisit; whether this is true or not currently, tu_fifo_empty is a single
   //  volatile read.
diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index 0845175b8..a790a5e27 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -37,7 +37,7 @@ extern "C" {
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-static inline void osal_task_delay(uint32_t msec) {
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
   rt_thread_mdelay(msec);
 }
 
@@ -47,22 +47,22 @@ static inline void osal_task_delay(uint32_t msec) {
 typedef struct rt_semaphore osal_semaphore_def_t;
 typedef rt_sem_t osal_semaphore_t;
 
-static inline osal_semaphore_t
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t
 osal_semaphore_create(osal_semaphore_def_t *semdef) {
     rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_FIFO);
     return semdef;
 }
 
-static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
     (void) in_isr;
     return rt_sem_release(sem_hdl) == RT_EOK;
 }
 
-static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
     return rt_sem_take(sem_hdl, rt_tick_from_millisecond(msec)) == RT_EOK;
 }
 
-static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
     // TODO: implement
 }
 
@@ -72,16 +72,16 @@ static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
 typedef struct rt_mutex osal_mutex_def_t;
 typedef rt_mutex_t osal_mutex_t;
 
-static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
     rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_FIFO);
     return mdef;
 }
 
-static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
     return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond(msec)) == RT_EOK;
 }
 
-static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
     return rt_mutex_release(mutex_hdl) == RT_EOK;
 }
 
@@ -104,22 +104,24 @@ typedef struct {
 
 typedef rt_mq_t osal_queue_t;
 
-static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) {
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) {
     rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz,
                qdef->item_sz * qdef->depth, RT_IPC_FLAG_FIFO);
     return &(qdef->sq);
 }
 
-static inline bool osal_queue_receive(osal_queue_t qhdl, void *data) {
-    return rt_mq_recv(qhdl, data, qhdl->msg_size, RT_WAITING_FOREVER) == RT_EOK;
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void *data, uint32_t msec) {
+
+    rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec));
+    return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) == RT_EOK;
 }
 
-static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
     (void) in_isr;
     return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK;
 }
 
-static inline bool osal_queue_empty(osal_queue_t qhdl) {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
     return (qhdl->entry) == 0;
 }
 
diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h
index 1856a5d9a..dea1c12c8 100644
--- a/src/osal/osal_rtx4.h
+++ b/src/osal/osal_rtx4.h
@@ -37,7 +37,7 @@ extern "C" {
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
-static inline void osal_task_delay(uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 {
   uint16_t hi = msec >> 16;
   uint16_t lo = msec;
@@ -47,7 +47,7 @@ static inline void osal_task_delay(uint32_t msec)
   os_dly_wait(lo);
 }
 
-static inline uint16_t msec2wait(uint32_t msec) {
+TU_ATTR_ALWAYS_INLINE static inline uint16_t msec2wait(uint32_t msec) {
   if (msec == OSAL_TIMEOUT_WAIT_FOREVER)
     return 0xFFFF;
   else if (msec >= 0xFFFE)
@@ -62,12 +62,12 @@ static inline uint16_t msec2wait(uint32_t msec) {
 typedef OS_SEM osal_semaphore_def_t;
 typedef OS_ID osal_semaphore_t;
 
-static inline OS_ID osal_semaphore_create(osal_semaphore_def_t* semdef) {
+TU_ATTR_ALWAYS_INLINE static inline OS_ID osal_semaphore_create(osal_semaphore_def_t* semdef) {
   os_sem_init(semdef, 0);
   return semdef;
 }
 
-static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
   if ( !in_isr ) {
     os_sem_send(sem_hdl);
   } else {
@@ -76,11 +76,11 @@ static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
 	return true;
 }
 
-static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) {
   return os_sem_wait(sem_hdl, msec2wait(msec)) != OS_R_TMO;
 }
 
-static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
   // TODO: implement
 }
 
@@ -90,18 +90,18 @@ static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
 typedef OS_MUT osal_mutex_def_t;
 typedef OS_ID osal_mutex_t;
 
-static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
   os_mut_init(mdef);
   return mdef;
 }
 
-static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
 {
   return os_mut_wait(mutex_hdl, msec2wait(msec)) != OS_R_TMO;
 }
 
-static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
 {
   return os_mut_release(mutex_hdl) == OS_R_OK;
 }
@@ -127,23 +127,23 @@ typedef struct
 
 typedef osal_queue_def_t* osal_queue_t;
 
-static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
   os_mbx_init(qdef->mbox, (qdef->depth + 4) * 4);
   _init_box(qdef->pool, ((qdef->item_sz+3)/4)*(qdef->depth) + 3, qdef->item_sz);
   return qdef;
 }
 
-static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
 {
   void* buf;
-  os_mbx_wait(qhdl->mbox, &buf, 0xFFFF);
+  os_mbx_wait(qhdl->mbox, &buf, msec2wait(msec));
   memcpy(data, buf, qhdl->item_sz);
   _free_box(qhdl->pool, buf);
   return true;
 }
 
-static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
 {
   void* buf = _alloc_box(qhdl->pool);
   memcpy(buf, data, qhdl->item_sz);
@@ -158,7 +158,7 @@ static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in
   return true;
 }
 
-static inline bool osal_queue_empty(osal_queue_t qhdl)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
 {
   return os_mbx_check(qhdl->mbox) == qhdl->depth;
 }
diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c
index fbea03b1d..d3154e58f 100644
--- a/src/portable/sony/cxd56/dcd_cxd56.c
+++ b/src/portable/sony/cxd56/dcd_cxd56.c
@@ -363,7 +363,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
 
     if (usbdcd_driver.setup_processed)
     {
-      if (osal_queue_receive(usbdcd_driver.setup_queue, &ctrl))
+      if (osal_queue_receive(usbdcd_driver.setup_queue, &ctrl, 100))
       {
         usbdcd_driver.setup_processed = false;
         dcd_event_setup_received(0, (uint8_t *)&ctrl, false);
diff --git a/src/tusb_option.h b/src/tusb_option.h
index bd87a953c..9cacedd4c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -286,7 +286,7 @@
 #endif
 
 // mutex is only needed for RTOS TODO also required with multiple core MCUs
-#define TUSB_OPT_MUTEX    (CFG_TUSB_OS != OPT_OS_NONE)
+#define TUSB_OPT_MUTEX      (CFG_TUSB_OS != OPT_OS_NONE)
 
 //--------------------------------------------------------------------
 // DEVICE OPTIONS

From 669e36d674d4b67b56127d8b41928a6dd3bdca7b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 20 Apr 2022 14:37:42 +0700
Subject: [PATCH 0971/2085] fix freertos issue when 1 tick > 1 ms

---
 examples/device/cdc_msc_freertos/src/main.c |  6 ++----
 src/osal/osal_freertos.h                    | 20 ++++++++++++++++----
 2 files changed, 18 insertions(+), 8 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 0a1c964ae..c0fc722f4 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -132,6 +132,8 @@ void usb_device_task(void* param)
   {
     // tinyusb device task
     tud_task();
+
+    tud_cdc_write_flush();
   }
 }
 
@@ -194,12 +196,8 @@ void cdc_task(void* params)
         // for throughput test e.g
         //    $ dd if=/dev/zero of=/dev/ttyACM0 count=10000
         tud_cdc_write(buf, count);
-        tud_cdc_write_flush();
       }
     }
-
-    // For ESP32-S2 this delay is essential to allow idle how to run and reset wdt
-    vTaskDelay(pdMS_TO_TICKS(10));
   }
 }
 
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index c3a0756e1..52db336f5 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -37,6 +37,20 @@
 extern "C" {
 #endif
 
+TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec)
+{
+  if (msec == OSAL_TIMEOUT_WAIT_FOREVER) return portMAX_DELAY;
+  if (msec == 0) return 0;
+
+  uint32_t ticks = pdMS_TO_TICKS(msec);
+
+  // configTICK_RATE_HZ is less than 1000 and 1 tick > 1 ms
+  // we still need to delay at least 1 tick
+  if (ticks == 0) ticks =1 ;
+
+  return ticks;
+}
+
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
@@ -80,8 +94,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t se
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
 {
-  uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? portMAX_DELAY : pdMS_TO_TICKS(msec);
-  return xSemaphoreTake(sem_hdl, ticks);
+  return xSemaphoreTake(sem_hdl, _osal_ms2tick(msec));
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl)
@@ -137,8 +150,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
 {
-  uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? portMAX_DELAY : pdMS_TO_TICKS(msec);
-  return xQueueReceive(qhdl, data, ticks);
+  return xQueueReceive(qhdl, data, _osal_ms2tick(msec));
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)

From ccafb42c8261d8304fce0af46c0ddc3adf6da56f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 20 Apr 2022 14:40:55 +0700
Subject: [PATCH 0972/2085] disable blank issues, add online docs link

---
 .github/ISSUE_TEMPLATE/config.yml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml
index 735a5ef22..28fd27467 100644
--- a/.github/ISSUE_TEMPLATE/config.yml
+++ b/.github/ISSUE_TEMPLATE/config.yml
@@ -1,4 +1,8 @@
+blank_issues_enabled: false
 contact_links:
   - name: TinyUSB Discussion
     url: https://github.com/hathach/tinyusb/discussions
     about: If you have other questions or need help, post it here.
+  - name: TinyUSB Docs
+    url: https://docs.tinyusb.org/
+    about: Online documentation

From c422b9ef419d4abc52b8c1e95ba4577ac6ae6a8c Mon Sep 17 00:00:00 2001
From: Nikitarc <rtk@adastra-soft.com>
Date: Wed, 20 Apr 2022 11:29:03 +0200
Subject: [PATCH 0973/2085] Update dwc2_stm32.h

Add missing #endif
---
 src/portable/synopsys/dwc2/dwc2_stm32.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index c4a4d310f..d54bf1fd7 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -61,6 +61,7 @@
     // USB_OTG_FS_PERIPH_BASE and OTG_FS_IRQn not defined
     #define USB_OTG_FS_PERIPH_BASE  USB1_OTG_HS_PERIPH_BASE
     #define OTG_FS_IRQn             OTG_HS_IRQn
+  #endif
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
   #include "stm32f7xx.h"

From b034c18077ef1350f2678f245ed1b885e9be79fc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 20 Apr 2022 18:29:41 +0700
Subject: [PATCH 0974/2085] add tud_task_ext(), tuh_task_ext() as exteneded
 version that take timeout and in_isr

also allow exit tud_task,tuh_task after processing all events for
running other background task for user
---
 examples/device/cdc_msc_freertos/src/main.c |  3 +++
 src/common/tusb_verify.h                    | 10 +++++-----
 src/device/usbd.c                           | 11 +++++++++--
 src/device/usbd.h                           | 11 ++++++++++-
 src/host/usbh.c                             | 11 +++++++++--
 src/host/usbh.h                             | 19 ++++++++++++++-----
 6 files changed, 50 insertions(+), 15 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index c0fc722f4..0d40782ef 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -198,6 +198,9 @@ void cdc_task(void* params)
         tud_cdc_write(buf, count);
       }
     }
+
+    // For ESP32-Sx this delay is essential to allow idle how to run and reset watchdog
+    vTaskDelay(1);
   }
 }
 
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index f4a08ce2f..568bac8cc 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -99,8 +99,8 @@
  *------------------------------------------------------------------*/
 
 // Helper to implement optional parameter for TU_VERIFY Macro family
-#define GET_3RD_ARG(arg1, arg2, arg3, ...)        arg3
-#define GET_4TH_ARG(arg1, arg2, arg3, arg4, ...)  arg4
+#define _GET_3RD_ARG(arg1, arg2, arg3, ...)        arg3
+#define _GET_4TH_ARG(arg1, arg2, arg3, arg4, ...)  arg4
 
 /*------------- Generator for TU_VERIFY and TU_VERIFY_HDLR -------------*/
 #define TU_VERIFY_DEFINE(_cond, _handler, _ret)  do            \
@@ -116,7 +116,7 @@
 #define TU_VERIFY_1ARGS(_cond)                         TU_VERIFY_DEFINE(_cond, , false)
 #define TU_VERIFY_2ARGS(_cond, _ret)                   TU_VERIFY_DEFINE(_cond, , _ret)
 
-#define TU_VERIFY(...)                   GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, UNUSED)(__VA_ARGS__)
+#define TU_VERIFY(...)                   _GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, UNUSED)(__VA_ARGS__)
 
 
 /*------------------------------------------------------------------*/
@@ -127,7 +127,7 @@
 #define TU_VERIFY_HDLR_2ARGS(_cond, _handler)           TU_VERIFY_DEFINE(_cond, _handler, false)
 #define TU_VERIFY_HDLR_3ARGS(_cond, _handler, _ret)     TU_VERIFY_DEFINE(_cond, _handler, _ret)
 
-#define TU_VERIFY_HDLR(...)              GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_HDLR_3ARGS, TU_VERIFY_HDLR_2ARGS,UNUSED)(__VA_ARGS__)
+#define TU_VERIFY_HDLR(...)              _GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_HDLR_3ARGS, TU_VERIFY_HDLR_2ARGS,UNUSED)(__VA_ARGS__)
 
 /*------------------------------------------------------------------*/
 /* ASSERT
@@ -139,7 +139,7 @@
 #define ASSERT_2ARGS(_cond, _ret)      TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), _ret)
 
 #ifndef TU_ASSERT
-#define TU_ASSERT(...)             GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS,UNUSED)(__VA_ARGS__)
+#define TU_ASSERT(...)             _GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS,UNUSED)(__VA_ARGS__)
 #endif
 
 /*------------------------------------------------------------------*/
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 36b9c7cff..167a053e2 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -466,8 +466,10 @@ bool tud_task_event_ready(void)
     }
     @endcode
  */
-void tud_task (void)
+void tud_task_ext(uint32_t timeout_ms, bool in_isr)
 {
+  (void) in_isr; // not implemented yet
+
   // Skip if stack is not initialized
   if ( !tusb_inited() ) return;
 
@@ -475,7 +477,7 @@ void tud_task (void)
   while (1)
   {
     dcd_event_t event;
-    if ( !osal_queue_receive(_usbd_q, &event, 1) ) return;
+    if ( !osal_queue_receive(_usbd_q, &event, timeout_ms) ) return;
 
 #if CFG_TUSB_DEBUG >= 2
     if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG2("\r\n"); // extra line for setup
@@ -592,6 +594,11 @@ void tud_task (void)
         TU_BREAKPOINT();
       break;
     }
+
+#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
+    // return if there is no more events, for application to run other background
+    if (osal_queue_empty(_usbd_q)) return;
+#endif
   }
 }
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index b2bf8ba9d..30373abb9 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -43,8 +43,17 @@ bool tud_init (uint8_t rhport);
 // Check if device stack is already initialized
 bool tud_inited(void);
 
+// Task function should be called in main/rtos loop, extended version of tud_task()
+// - timeout_ms: millisecond to wait, zero = no wait, 0xFFFFFFFF = wait forever
+// - in_isr: if function is called in ISR
+void tud_task_ext(uint32_t timeout_ms, bool in_isr);
+
 // Task function should be called in main/rtos loop
-void tud_task (void);
+TU_ATTR_ALWAYS_INLINE static inline
+void tud_task (void)
+{
+  tud_task_ext(OSAL_TIMEOUT_WAIT_FOREVER, false);
+}
 
 // Check if there is pending events need proccessing by tud_task()
 bool tud_task_event_ready(void);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index ad90a1b1b..80d176142 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -392,8 +392,10 @@ bool tuh_init(uint8_t rhport)
     }
     @endcode
  */
-void tuh_task(void)
+void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
 {
+  (void) in_isr; // not implemented yet
+
   // Skip if stack is not initialized
   if ( !tusb_inited() ) return;
 
@@ -401,7 +403,7 @@ void tuh_task(void)
   while (1)
   {
     hcd_event_t event;
-    if ( !osal_queue_receive(_usbh_q, &event, 1) ) return;
+    if ( !osal_queue_receive(_usbh_q, &event, timeout_ms) ) return;
 
     switch (event.event_id)
     {
@@ -497,6 +499,11 @@ void tuh_task(void)
 
       default: break;
     }
+
+#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
+    // return if there is no more events, for application to run other background
+    if (osal_queue_empty(_usbh_q)) return;
+#endif
   }
 }
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index e883ac90b..1580717fd 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -91,8 +91,17 @@ bool tuh_init(uint8_t rhport);
 // Check if host stack is already initialized
 bool tuh_inited(void);
 
+// Task function should be called in main/rtos loop, extended version of tuh_task()
+// - timeout_ms: millisecond to wait, zero = no wait, 0xFFFFFFFF = wait forever
+// - in_isr: if function is called in ISR
+void tuh_task_ext(uint32_t timeout_ms, bool in_isr);
+
 // Task function should be called in main/rtos loop
-void tuh_task(void);
+TU_ATTR_ALWAYS_INLINE static inline
+void tuh_task(void)
+{
+  tuh_task_ext(OSAL_TIMEOUT_WAIT_FOREVER, false);
+}
 
 // Interrupt handler, name alias to HCD
 extern void hcd_int_handler(uint8_t rhport);
@@ -106,8 +115,8 @@ tusb_speed_t tuh_speed_get(uint8_t daddr);
 bool tuh_mounted(uint8_t daddr);
 
 // Check if device is suspended
-TU_ATTR_ALWAYS_INLINE
-static inline bool tuh_suspended(uint8_t daddr)
+TU_ATTR_ALWAYS_INLINE static inline
+bool tuh_suspended(uint8_t daddr)
 {
   // TODO implement suspend & resume on host
   (void) daddr;
@@ -115,8 +124,8 @@ static inline bool tuh_suspended(uint8_t daddr)
 }
 
 // Check if device is ready to communicate with
-TU_ATTR_ALWAYS_INLINE
-static inline bool tuh_ready(uint8_t daddr)
+TU_ATTR_ALWAYS_INLINE static inline
+bool tuh_ready(uint8_t daddr)
 {
   return tuh_mounted(daddr) && !tuh_suspended(daddr);
 }

From 6a022c73dbf1551a441fafbea3a27c1a9951816f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 20 Apr 2022 18:35:38 +0700
Subject: [PATCH 0975/2085] add note for tud_task() behavior in freertos
 example

---
 examples/device/cdc_msc_freertos/src/main.c       | 5 +++--
 examples/device/hid_composite_freertos/src/main.c | 4 +++-
 src/device/usbd.h                                 | 2 +-
 src/host/usbh.h                                   | 2 +-
 4 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 0d40782ef..0492f2724 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -130,10 +130,10 @@ void usb_device_task(void* param)
   // RTOS forever loop
   while (1)
   {
-    // tinyusb device task
+    // put this thread to waiting state until there is new events
     tud_task();
 
-    tud_cdc_write_flush();
+    // following code only run if tud_task() process at least 1 event
   }
 }
 
@@ -196,6 +196,7 @@ void cdc_task(void* params)
         // for throughput test e.g
         //    $ dd if=/dev/zero of=/dev/ttyACM0 count=10000
         tud_cdc_write(buf, count);
+        tud_cdc_write_flush();
       }
     }
 
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 1695f968c..317b64611 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -132,8 +132,10 @@ void usb_device_task(void* param)
   // RTOS forever loop
   while (1)
   {
-    // tinyusb device task
+    // put this thread to waiting state until there is new events
     tud_task();
+
+    // following code only run if tud_task() process at least 1 event
   }
 }
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 30373abb9..583962611 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -52,7 +52,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr);
 TU_ATTR_ALWAYS_INLINE static inline
 void tud_task (void)
 {
-  tud_task_ext(OSAL_TIMEOUT_WAIT_FOREVER, false);
+  tud_task_ext(UINT32_MAX, false);
 }
 
 // Check if there is pending events need proccessing by tud_task()
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 1580717fd..c6d36fb7f 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -100,7 +100,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr);
 TU_ATTR_ALWAYS_INLINE static inline
 void tuh_task(void)
 {
-  tuh_task_ext(OSAL_TIMEOUT_WAIT_FOREVER, false);
+  tuh_task_ext(UINT32_MAX, false);
 }
 
 // Interrupt handler, name alias to HCD

From 87572871d586856242c1fa44b1532a09e624162d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 20 Apr 2022 18:52:15 +0700
Subject: [PATCH 0976/2085] update example for better cdc echo

---
 examples/device/cdc_msc_freertos/src/main.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 0492f2724..a5e907199 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -134,6 +134,7 @@ void usb_device_task(void* param)
     tud_task();
 
     // following code only run if tud_task() process at least 1 event
+    tud_cdc_write_flush();
   }
 }
 
@@ -183,7 +184,7 @@ void cdc_task(void* params)
     // if ( tud_cdc_connected() )
     {
       // There are data available
-      if ( tud_cdc_available() )
+      while ( tud_cdc_available() )
       {
         uint8_t buf[64];
 
@@ -196,8 +197,9 @@ void cdc_task(void* params)
         // for throughput test e.g
         //    $ dd if=/dev/zero of=/dev/ttyACM0 count=10000
         tud_cdc_write(buf, count);
-        tud_cdc_write_flush();
       }
+
+      tud_cdc_write_flush();
     }
 
     // For ESP32-Sx this delay is essential to allow idle how to run and reset watchdog

From 328039058ef1c654246304a3a0acbee724278b85 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 21 Apr 2022 01:45:03 +0700
Subject: [PATCH 0977/2085] update lib pio

---
 lib/Pico-PIO-USB | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 98e3feefc..d15fffd95 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 98e3feefcd1c7218bced0ea2ea35530fd1b550e4
+Subproject commit d15fffd950018c60cba5c98d676a4fafaeea2648

From 12debd7763bfc6f55566e5f4f8c982a55f206815 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 22 Apr 2022 01:06:17 +0700
Subject: [PATCH 0978/2085] keep up with pio usb

---
 hw/bsp/rp2040/family.cmake                     |  1 -
 lib/Pico-PIO-USB                               |  2 +-
 src/common/tusb_debug.h                        |  4 ++++
 src/portable/raspberrypi/pio_usb/dcd_pio_usb.c | 10 +++++-----
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c |  4 ++--
 5 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index d872c35ea..70e18293f 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -32,7 +32,6 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/lib/Pico-PIO-USB/pio_usb.c
 			${TOP}/lib/Pico-PIO-USB/pio_usb_host.c
 			${TOP}/lib/Pico-PIO-USB/pio_usb_device.c
-			${TOP}/lib/Pico-PIO-USB/pio_usb_hw.c
 			${TOP}/lib/Pico-PIO-USB/usb_crc.c
 			)
 
diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index d15fffd95..f656d703f 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit d15fffd950018c60cba5c98d676a4fafaeea2648
+Subproject commit f656d703f3cee1e589eebb6606e204f59afb5611
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 647e8a8db..1ea2c19f5 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -65,6 +65,7 @@ static inline void tu_print_var(uint8_t const* buf, uint32_t bufsize)
 // Log with Level
 #define TU_LOG(n, ...)        TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
 #define TU_LOG_MEM(n, ...)    TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
+#define TU_LOG_ARR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _ARR)(__VA_ARGS__)
 #define TU_LOG_VAR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _VAR)(__VA_ARGS__)
 #define TU_LOG_INT(n, ...)    TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
 #define TU_LOG_HEX(n, ...)    TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
@@ -74,6 +75,7 @@ static inline void tu_print_var(uint8_t const* buf, uint32_t bufsize)
 // Log Level 1: Error
 #define TU_LOG1               tu_printf
 #define TU_LOG1_MEM           tu_print_mem
+#define TU_LOG1_ARR(_x, _n)   tu_print_var((uint8_t const*)(_x), _n)
 #define TU_LOG1_VAR(_x)       tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
 #define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
 #define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
@@ -82,6 +84,7 @@ static inline void tu_print_var(uint8_t const* buf, uint32_t bufsize)
 #if CFG_TUSB_DEBUG >= 2
   #define TU_LOG2             TU_LOG1
   #define TU_LOG2_MEM         TU_LOG1_MEM
+  #define TU_LOG2_ARR         TU_LOG1_ARR
   #define TU_LOG2_VAR         TU_LOG1_VAR
   #define TU_LOG2_INT         TU_LOG1_INT
   #define TU_LOG2_HEX         TU_LOG1_HEX
@@ -91,6 +94,7 @@ static inline void tu_print_var(uint8_t const* buf, uint32_t bufsize)
 #if CFG_TUSB_DEBUG >= 3
   #define TU_LOG3             TU_LOG1
   #define TU_LOG3_MEM         TU_LOG1_MEM
+  #define TU_LOG3_ARR         TU_LOG1_ARR
   #define TU_LOG3_VAR         TU_LOG1_VAR
   #define TU_LOG3_INT         TU_LOG1_INT
   #define TU_LOG3_HEX         TU_LOG1_HEX
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index 38867ea1c..1cb850654 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -119,8 +119,8 @@ void dcd_edpt_close_all (uint8_t rhport)
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
   (void) rhport;
-  pio_hw_endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
-  return pio_usb_endpoint_transfer(ep, buffer, total_bytes);
+  endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
+  return pio_usb_ll_endpoint_transfer(ep, buffer, total_bytes);
 }
 
 // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
@@ -137,7 +137,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
-  pio_hw_endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
+  endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
   ep->stalled = true;
 }
 
@@ -145,7 +145,7 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
-  pio_hw_endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
+  endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
   ep->data_id = 0;
   ep->stalled = false;
 }
@@ -188,7 +188,7 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_
 
     if (ep_all & mask)
     {
-      pio_hw_endpoint_t* ep = PIO_USB_HW_EP(ep_idx);
+      endpoint_t* ep = PIO_USB_HW_EP(ep_idx);
       uint8_t const tu_rhport = port - PIO_USB_HW_RPORT(0) + 1;
       dcd_event_xfer_complete(tu_rhport, ep->ep_num, ep->actual_len, result, true);
     }
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index e311f16d0..2615b2356 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -73,7 +73,7 @@ bool hcd_port_connect_status(uint8_t rhport)
   rhport = RHPORT_PIO(rhport);
 
   pio_hw_root_port_t *root = PIO_USB_HW_RPORT(rhport);
-  port_pin_status_t line_state = pio_hw_get_line_state(root);
+  port_pin_status_t line_state = pio_usb_ll_get_line_state(root);
 
   return line_state != PORT_PIN_SE0;
 }
@@ -187,7 +187,7 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_
 
     if (ep_all & mask)
     {
-      pio_hw_endpoint_t* ep = PIO_USB_HW_EP(ep_idx);
+      endpoint_t* ep = PIO_USB_HW_EP(ep_idx);
       hcd_event_xfer_complete(ep->dev_addr, ep->ep_num, ep->actual_len, result, true);
     }
   }

From 2f9b9a31be9d511d0bbb99671a2f5e7818cf8a55 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 22 Apr 2022 18:23:38 +0700
Subject: [PATCH 0979/2085] more with pio usb

---
 lib/Pico-PIO-USB                              |  2 +-
 .../raspberrypi/pio_usb/dcd_pio_usb.c         | 29 ++++++++++---------
 .../raspberrypi/pio_usb/hcd_pio_usb.c         | 13 +++++----
 3 files changed, 23 insertions(+), 21 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index f656d703f..496454021 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit f656d703f3cee1e589eebb6606e204f59afb5611
+Subproject commit 496454021deab00e1c425a6eb70009666fa036b3
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index 1cb850654..d73419fe3 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -31,6 +31,7 @@
 #include "pico.h"
 #include "hardware/pio.h"
 #include "pio_usb.h"
+#include "pio_usb_ll.h"
 
 #include "device/dcd.h"
 
@@ -119,7 +120,7 @@ void dcd_edpt_close_all (uint8_t rhport)
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
   (void) rhport;
-  endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
+  endpoint_t *ep = pio_usb_device_get_endpoint_by_address(ep_addr);
   return pio_usb_ll_endpoint_transfer(ep, buffer, total_bytes);
 }
 
@@ -137,7 +138,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
-  endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
+  endpoint_t *ep = pio_usb_device_get_endpoint_by_address(ep_addr);
   ep->stalled = true;
 }
 
@@ -145,7 +146,7 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
-  endpoint_t *ep = pio_usb_device_get_ep(ep_addr);
+  endpoint_t *ep = pio_usb_device_get_endpoint_by_address(ep_addr);
   ep->data_id = 0;
   ep->stalled = false;
 }
@@ -154,24 +155,24 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 //
 //--------------------------------------------------------------------+
 
-static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_t* port, uint32_t flag)
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rport, uint32_t flag)
 {
   volatile uint32_t* ep_reg;
   xfer_result_t result;
 
   if ( flag == PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
   {
-    ep_reg = &port->ep_complete;
+    ep_reg = &rport->ep_complete;
     result = XFER_RESULT_SUCCESS;
   }
   else if ( flag == PIO_USB_INTS_ENDPOINT_ERROR_BITS )
   {
-    ep_reg = &port->ep_error;
+    ep_reg = &rport->ep_error;
     result = XFER_RESULT_FAILED;
   }
   else if ( flag == PIO_USB_INTS_ENDPOINT_STALLED_BITS )
   {
-    ep_reg = &port->ep_stalled;
+    ep_reg = &rport->ep_stalled;
     result = XFER_RESULT_STALLED;
   }
   else
@@ -188,8 +189,8 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_
 
     if (ep_all & mask)
     {
-      endpoint_t* ep = PIO_USB_HW_EP(ep_idx);
-      uint8_t const tu_rhport = port - PIO_USB_HW_RPORT(0) + 1;
+      endpoint_t* ep = PIO_USB_ENDPOINT(ep_idx);
+      uint8_t const tu_rhport = rport - PIO_USB_ROOT_PORT(0) + 1;
       dcd_event_xfer_complete(tu_rhport, ep->ep_num, ep->actual_len, result, true);
     }
   }
@@ -202,8 +203,8 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_
 void __no_inline_not_in_flash_func(pio_usb_device_irq_handler)(uint8_t root_id)
 {
   uint8_t const tu_rhport = root_id + 1;
-  pio_hw_root_port_t* port = PIO_USB_HW_RPORT(root_id);
-  uint32_t const ints = port->ints;
+  root_port_t* rport = PIO_USB_ROOT_PORT(root_id);
+  uint32_t const ints = rport->ints;
 
   if (ints & PIO_USB_INTS_RESET_END_BITS)
   {
@@ -212,16 +213,16 @@ void __no_inline_not_in_flash_func(pio_usb_device_irq_handler)(uint8_t root_id)
 
   if (ints & PIO_USB_INTS_SETUP_REQ_BITS)
   {
-    dcd_event_setup_received(tu_rhport, port->setup_packet, true);
+    dcd_event_setup_received(tu_rhport, rport->setup_packet, true);
   }
 
   if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
   {
-    handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_COMPLETE_BITS);
+    handle_endpoint_irq(rport, PIO_USB_INTS_ENDPOINT_COMPLETE_BITS);
   }
 
   // clear all
-  port->ints &= ~ints;
+  rport->ints &= ~ints;
 }
 
 #endif
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 2615b2356..f881716ec 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -31,6 +31,7 @@
 #include "pico.h"
 #include "hardware/pio.h"
 #include "pio_usb.h"
+#include "pio_usb_ll.h"
 
 //--------------------------------------------------------------------+
 // INCLUDE
@@ -72,8 +73,8 @@ bool hcd_port_connect_status(uint8_t rhport)
 {
   rhport = RHPORT_PIO(rhport);
 
-  pio_hw_root_port_t *root = PIO_USB_HW_RPORT(rhport);
-  port_pin_status_t line_state = pio_usb_ll_get_line_state(root);
+  root_port_t *root = PIO_USB_ROOT_PORT(rhport);
+  port_pin_status_t line_state = pio_usb_bus_get_line_state(root);
 
   return line_state != PORT_PIN_SE0;
 }
@@ -82,7 +83,7 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   // TODO determine link speed
   rhport = RHPORT_PIO(rhport);
-  return PIO_USB_HW_RPORT(rhport)->is_fullspeed ? TUSB_SPEED_FULL : TUSB_SPEED_LOW;
+  return PIO_USB_ROOT_PORT(rhport)->is_fullspeed ? TUSB_SPEED_FULL : TUSB_SPEED_LOW;
 }
 
 // Close all opened endpoint belong to this device
@@ -153,7 +154,7 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
   return true;
 }
 
-static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_t* port, uint32_t flag)
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* port, uint32_t flag)
 {
   volatile uint32_t* ep_reg;
   xfer_result_t result;
@@ -187,7 +188,7 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_
 
     if (ep_all & mask)
     {
-      endpoint_t* ep = PIO_USB_HW_EP(ep_idx);
+      endpoint_t* ep = PIO_USB_ENDPOINT(ep_idx);
       hcd_event_xfer_complete(ep->dev_addr, ep->ep_num, ep->actual_len, result, true);
     }
   }
@@ -199,7 +200,7 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(pio_hw_root_port_
 // IRQ Handler
 void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id)
 {
-  pio_hw_root_port_t* port = PIO_USB_HW_RPORT(root_id);
+  root_port_t* port = PIO_USB_ROOT_PORT(root_id);
   uint32_t const ints = port->ints;
 
   if ( ints & PIO_USB_INTS_CONNECT_BITS )

From 3a1c7339cd54cc03233c2337e95403260992738f Mon Sep 17 00:00:00 2001
From: Grant Slater <git@firefishy.com>
Date: Sun, 24 Apr 2022 16:48:49 +0100
Subject: [PATCH 0980/2085] Replace actions/setup-ruby with replacement
 ruby/setup-ruby

---
 .github/workflows/build_arm.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 177f1076e..fc5eec1df 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -15,7 +15,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
     - name: Setup Ruby
-      uses: actions/setup-ruby@v1
+      uses: ruby/setup-ruby@v1
       with:
         ruby-version: '2.7'
 

From 35d1a71ed7d3b3ea42b4d38c7cdc85233b815348 Mon Sep 17 00:00:00 2001
From: Grant Slater <git@firefishy.com>
Date: Sun, 24 Apr 2022 16:49:29 +0100
Subject: [PATCH 0981/2085] GH Update to actions/checkout@v3

---
 .github/workflows/build_aarch64.yml | 4 ++--
 .github/workflows/build_arm.yml     | 8 ++++----
 .github/workflows/build_esp.yml     | 4 ++--
 .github/workflows/build_msp430.yml  | 4 ++--
 .github/workflows/build_renesas.yml | 4 ++--
 .github/workflows/build_riscv.yml   | 4 ++--
 .github/workflows/trigger.yml       | 2 +-
 7 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 8cf7852b9..1720ba592 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -24,13 +24,13 @@ jobs:
       uses: actions/setup-python@v2
 
     - name: Checkout TinyUSB
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
 
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
 
     - name: Checkout hathach/linkermap
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
       with:
          repository: hathach/linkermap
          path: linkermap
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index fc5eec1df..133671f82 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -20,7 +20,7 @@ jobs:
         ruby-version: '2.7'
 
     - name: Checkout TinyUSB
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
 
     - name: Unit Tests
       run: |
@@ -66,13 +66,13 @@ jobs:
       uses: actions/setup-python@v2
 
     - name: Checkout TinyUSB
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
 
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
 
     - name: Checkout hathach/linkermap
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
       with:
          repository: hathach/linkermap
          path: linkermap
@@ -135,7 +135,7 @@ jobs:
       uses: actions/setup-python@v2
 
     - name: Checkout TinyUSB
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
 
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 1ed76ef4d..6a46773b2 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -29,10 +29,10 @@ jobs:
       run: docker pull espressif/idf:latest
 
     - name: Checkout TinyUSB
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
 
     - name: Checkout hathach/linkermap
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
       with:
          repository: hathach/linkermap
          path: linkermap
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 98dc36cd9..6a468ab04 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -21,13 +21,13 @@ jobs:
       uses: actions/setup-python@v2
 
     - name: Checkout TinyUSB
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
 
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
     - name: Checkout hathach/linkermap
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
       with:
          repository: hathach/linkermap
          path: linkermap
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 6eb042d72..50618ff6b 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -21,13 +21,13 @@ jobs:
       uses: actions/setup-python@v2
 
     - name: Checkout TinyUSB
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
 
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
     - name: Checkout hathach/linkermap
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
       with:
          repository: hathach/linkermap
          path: linkermap
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 0c7b2d154..2d670138d 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -22,13 +22,13 @@ jobs:
       uses: actions/setup-python@v2
 
     - name: Checkout TinyUSB
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
 
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
     - name: Checkout hathach/linkermap
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
       with:
          repository: hathach/linkermap
          path: linkermap
diff --git a/.github/workflows/trigger.yml b/.github/workflows/trigger.yml
index 40750a2f9..780d6f4f3 100644
--- a/.github/workflows/trigger.yml
+++ b/.github/workflows/trigger.yml
@@ -22,7 +22,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
     - name: Checkout code
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
 
     - name: Push to tinyusb_src
       run: |

From 15c01f20ecdb3b9ff184f2311e65e95e4cd8e5cd Mon Sep 17 00:00:00 2001
From: Nikitarc <rtk@adastra-soft.com>
Date: Mon, 25 Apr 2022 14:06:15 +0200
Subject: [PATCH 0982/2085] Update tusb_option.h

Makes ISO compiler happy
---
 src/tusb_option.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index bd87a953c..66313419a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -27,6 +27,9 @@
 #ifndef _TUSB_OPTION_H_
 #define _TUSB_OPTION_H_
 
+// To avoid GCC compiler warnings when -pedantic option is used (strict ISO C)
+typedef int make_iso_compilers_happy ;
+
 #include "common/tusb_compiler.h"
 
 #define TUSB_VERSION_MAJOR     0

From 26a25279bc7196d93ca074203ac35260298df472 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Apr 2022 00:35:16 +0700
Subject: [PATCH 0983/2085] follow pio usb changes

---
 lib/Pico-PIO-USB                              |  2 +-
 .../raspberrypi/pio_usb/dcd_pio_usb.c         | 11 ++---
 .../raspberrypi/pio_usb/hcd_pio_usb.c         | 40 ++++++++++---------
 3 files changed, 27 insertions(+), 26 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 496454021..d2c70ae7b 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 496454021deab00e1c425a6eb70009666fa036b3
+Subproject commit d2c70ae7b6a122027b7c5c9aa4769fab19e8e886
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index d73419fe3..09be69afa 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -74,11 +74,8 @@ void dcd_int_disable (uint8_t rhport)
 // Receive Set Address request, mcu port must also include status IN response
 void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
 {
-  uint8_t const pio_rhport = RHPORT_PIO(rhport);
-
   // must be called before queuing status
-  pio_usb_device_set_address(pio_rhport, dev_addr);
-
+  pio_usb_device_set_address(dev_addr);
   dcd_edpt_xfer(rhport, 0x80, NULL, 0);
 }
 
@@ -107,8 +104,8 @@ void dcd_disconnect(uint8_t rhport)
 // Configure endpoint's registers according to descriptor
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
 {
-  uint8_t const pio_rhport = RHPORT_PIO(rhport);
-  return pio_usb_device_endpoint_open(pio_rhport, (uint8_t const*) desc_ep);
+  (void) rhport;
+  return pio_usb_device_endpoint_open((uint8_t const*) desc_ep);
 }
 
 void dcd_edpt_close_all (uint8_t rhport)
@@ -121,7 +118,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 {
   (void) rhport;
   endpoint_t *ep = pio_usb_device_get_endpoint_by_address(ep_addr);
-  return pio_usb_ll_endpoint_transfer(ep, buffer, total_bytes);
+  return pio_usb_ll_transfer_start(ep, buffer, total_bytes);
 }
 
 // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index f881716ec..2b3d72df8 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -59,21 +59,21 @@ bool hcd_init(uint8_t rhport)
 
 void hcd_port_reset(uint8_t rhport)
 {
-  rhport = RHPORT_PIO(rhport);
-  pio_usb_host_port_reset_start(rhport);
+  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  pio_usb_host_port_reset_start(pio_rhport);
 }
 
 void hcd_port_reset_end(uint8_t rhport)
 {
-  rhport = RHPORT_PIO(rhport);
-  pio_usb_host_port_reset_end(rhport);
+  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  pio_usb_host_port_reset_end(pio_rhport);
 }
 
 bool hcd_port_connect_status(uint8_t rhport)
 {
-  rhport = RHPORT_PIO(rhport);
+  uint8_t pio_rhport = RHPORT_PIO(rhport);
 
-  root_port_t *root = PIO_USB_ROOT_PORT(rhport);
+  root_port_t *root = PIO_USB_ROOT_PORT(pio_rhport);
   port_pin_status_t line_state = pio_usb_bus_get_line_state(root);
 
   return line_state != PORT_PIN_SE0;
@@ -82,28 +82,31 @@ bool hcd_port_connect_status(uint8_t rhport)
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   // TODO determine link speed
-  rhport = RHPORT_PIO(rhport);
-  return PIO_USB_ROOT_PORT(rhport)->is_fullspeed ? TUSB_SPEED_FULL : TUSB_SPEED_LOW;
+  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  return PIO_USB_ROOT_PORT(pio_rhport)->is_fullspeed ? TUSB_SPEED_FULL : TUSB_SPEED_LOW;
 }
 
 // Close all opened endpoint belong to this device
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 {
-  rhport = RHPORT_PIO(rhport);
-  pio_usb_host_close_device(rhport, dev_addr);
+  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  pio_usb_host_close_device(pio_rhport, dev_addr);
 }
 
 uint32_t hcd_frame_number(uint8_t rhport)
 {
+  (void) rhport;
   return 0;
 }
 
 void hcd_int_enable(uint8_t rhport)
 {
+  (void) rhport;
 }
 
 void hcd_int_disable(uint8_t rhport)
 {
+  (void) rhport;
 }
 
 //--------------------------------------------------------------------+
@@ -116,20 +119,20 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   hcd_devtree_get_info(dev_addr, &dev_tree);
   bool const need_pre = (dev_tree.hub_addr && dev_tree.speed == TUSB_SPEED_LOW);
 
-  rhport = RHPORT_PIO(rhport);
-  return pio_usb_host_endpoint_open(rhport, dev_addr, (uint8_t const*) desc_ep, need_pre);
+  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const*) desc_ep, need_pre);
 }
 
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
-  rhport = RHPORT_PIO(rhport);
-  return pio_usb_host_endpoint_transfer(rhport, dev_addr, ep_addr, buffer, buflen);
+  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen);
 }
 
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
-  rhport = RHPORT_PIO(rhport);
-  return pio_usb_host_send_setup(rhport, dev_addr, setup_packet);
+  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  return pio_usb_host_send_setup(pio_rhport, dev_addr, setup_packet);
 }
 
 //bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
@@ -200,17 +203,18 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* port
 // IRQ Handler
 void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id)
 {
+  uint8_t const tu_rhport = root_id + 1;
   root_port_t* port = PIO_USB_ROOT_PORT(root_id);
   uint32_t const ints = port->ints;
 
   if ( ints & PIO_USB_INTS_CONNECT_BITS )
   {
-    hcd_event_device_attach(root_id+1, true);
+    hcd_event_device_attach(tu_rhport, true);
   }
 
   if ( ints & PIO_USB_INTS_DISCONNECT_BITS )
   {
-    hcd_event_device_remove(root_id+1, true);
+    hcd_event_device_remove(tu_rhport, true);
   }
 
   if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )

From 4d11c658fffa810f271fdafb6453eff1f2b77b3f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Apr 2022 13:08:03 +0700
Subject: [PATCH 0984/2085] improve pio usb endpoint handler

---
 .../raspberrypi/pio_usb/dcd_pio_usb.c         | 38 +++++----------
 .../raspberrypi/pio_usb/hcd_pio_usb.c         | 46 +++++--------------
 2 files changed, 23 insertions(+), 61 deletions(-)

diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index 09be69afa..77f34238a 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -152,32 +152,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 //
 //--------------------------------------------------------------------+
 
-static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rport, uint32_t flag)
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rport, xfer_result_t result, volatile uint32_t* ep_reg)
 {
-  volatile uint32_t* ep_reg;
-  xfer_result_t result;
-
-  if ( flag == PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
-  {
-    ep_reg = &rport->ep_complete;
-    result = XFER_RESULT_SUCCESS;
-  }
-  else if ( flag == PIO_USB_INTS_ENDPOINT_ERROR_BITS )
-  {
-    ep_reg = &rport->ep_error;
-    result = XFER_RESULT_FAILED;
-  }
-  else if ( flag == PIO_USB_INTS_ENDPOINT_STALLED_BITS )
-  {
-    ep_reg = &rport->ep_stalled;
-    result = XFER_RESULT_STALLED;
-  }
-  else
-  {
-    // something wrong
-    return;
-  }
-
   const uint32_t ep_all = *ep_reg;
 
   for(uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++)
@@ -215,7 +191,17 @@ void __no_inline_not_in_flash_func(pio_usb_device_irq_handler)(uint8_t root_id)
 
   if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
   {
-    handle_endpoint_irq(rport, PIO_USB_INTS_ENDPOINT_COMPLETE_BITS);
+    handle_endpoint_irq(rport, XFER_RESULT_SUCCESS, &rport->ep_complete);
+  }
+
+  if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS )
+  {
+    handle_endpoint_irq(rport, XFER_RESULT_STALLED, &rport->ep_stalled);
+  }
+
+  if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS )
+  {
+    handle_endpoint_irq(rport, XFER_RESULT_FAILED, &rport->ep_error);
   }
 
   // clear all
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 2b3d72df8..8101fb2d3 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -157,32 +157,8 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
   return true;
 }
 
-static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* port, uint32_t flag)
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* port, xfer_result_t result, volatile uint32_t* ep_reg)
 {
-  volatile uint32_t* ep_reg;
-  xfer_result_t result;
-
-  if ( flag == PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
-  {
-    ep_reg = &port->ep_complete;
-    result = XFER_RESULT_SUCCESS;
-  }
-  else if ( flag == PIO_USB_INTS_ENDPOINT_ERROR_BITS )
-  {
-    ep_reg = &port->ep_error;
-    result = XFER_RESULT_FAILED;
-  }
-  else if ( flag == PIO_USB_INTS_ENDPOINT_STALLED_BITS )
-  {
-    ep_reg = &port->ep_stalled;
-    result = XFER_RESULT_STALLED;
-  }
-  else
-  {
-    // something wrong
-    return;
-  }
-
   const uint32_t ep_all = *ep_reg;
 
   for(uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++)
@@ -204,8 +180,8 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* port
 void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id)
 {
   uint8_t const tu_rhport = root_id + 1;
-  root_port_t* port = PIO_USB_ROOT_PORT(root_id);
-  uint32_t const ints = port->ints;
+  root_port_t* rport = PIO_USB_ROOT_PORT(root_id);
+  uint32_t const ints = rport->ints;
 
   if ( ints & PIO_USB_INTS_CONNECT_BITS )
   {
@@ -219,21 +195,21 @@ void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id)
 
   if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
   {
-    handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_COMPLETE_BITS);
-  }
-
-  if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS )
-  {
-    handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_ERROR_BITS);
+    handle_endpoint_irq(rport, XFER_RESULT_SUCCESS, &rport->ep_complete);
   }
 
   if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS )
   {
-    handle_endpoint_irq(port, PIO_USB_INTS_ENDPOINT_STALLED_BITS);
+    handle_endpoint_irq(rport, XFER_RESULT_STALLED, &rport->ep_stalled);
+  }
+
+  if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS )
+  {
+    handle_endpoint_irq(rport, XFER_RESULT_FAILED, &rport->ep_error);
   }
 
   // clear all
-  port->ints &= ~ints;
+  rport->ints &= ~ints;
 }
 
 #endif

From 455bddddcd051acd6d62bca97783be04fc508e96 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Apr 2022 18:47:09 +0700
Subject: [PATCH 0985/2085] minor clean up

---
 lib/Pico-PIO-USB                               | 2 +-
 src/portable/raspberrypi/pio_usb/dcd_pio_usb.c | 9 ++++-----
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 3 ++-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index d2c70ae7b..125753a97 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit d2c70ae7b6a122027b7c5c9aa4769fab19e8e886
+Subproject commit 125753a9783bc1724a185770b04f83c4ebd4b6c5
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index 77f34238a..3daa39a8b 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -152,7 +152,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 //
 //--------------------------------------------------------------------+
 
-static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rport, xfer_result_t result, volatile uint32_t* ep_reg)
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(uint8_t tu_rhport, xfer_result_t result, volatile uint32_t* ep_reg)
 {
   const uint32_t ep_all = *ep_reg;
 
@@ -163,7 +163,6 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rpor
     if (ep_all & mask)
     {
       endpoint_t* ep = PIO_USB_ENDPOINT(ep_idx);
-      uint8_t const tu_rhport = rport - PIO_USB_ROOT_PORT(0) + 1;
       dcd_event_xfer_complete(tu_rhport, ep->ep_num, ep->actual_len, result, true);
     }
   }
@@ -191,17 +190,17 @@ void __no_inline_not_in_flash_func(pio_usb_device_irq_handler)(uint8_t root_id)
 
   if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
   {
-    handle_endpoint_irq(rport, XFER_RESULT_SUCCESS, &rport->ep_complete);
+    handle_endpoint_irq(tu_rhport, XFER_RESULT_SUCCESS, &rport->ep_complete);
   }
 
   if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS )
   {
-    handle_endpoint_irq(rport, XFER_RESULT_STALLED, &rport->ep_stalled);
+    handle_endpoint_irq(tu_rhport, XFER_RESULT_STALLED, &rport->ep_stalled);
   }
 
   if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS )
   {
-    handle_endpoint_irq(rport, XFER_RESULT_FAILED, &rport->ep_error);
+    handle_endpoint_irq(tu_rhport, XFER_RESULT_FAILED, &rport->ep_error);
   }
 
   // clear all
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 8101fb2d3..f6caabb54 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -157,8 +157,9 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
   return true;
 }
 
-static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* port, xfer_result_t result, volatile uint32_t* ep_reg)
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rport, xfer_result_t result, volatile uint32_t* ep_reg)
 {
+  (void) rport;
   const uint32_t ep_all = *ep_reg;
 
   for(uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++)

From fd827a80a9f3b1e482cc8b1609c055cbad252b37 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Apr 2022 01:09:30 +0700
Subject: [PATCH 0986/2085] everything work great

---
 lib/Pico-PIO-USB | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 125753a97..aecced02e 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 125753a9783bc1724a185770b04f83c4ebd4b6c5
+Subproject commit aecced02e756f3a35805cacdd9be25976b6dd978

From 4a661dead0899cb154325a8257d19281f2536af3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Apr 2022 17:57:52 +0700
Subject: [PATCH 0987/2085] add TU_ATTR_FAST_FUNC for rp2040 __not_in_flash()
 section

---
 examples/device/hid_boot_interface/src/main.c | 2 --
 hw/bsp/rp2040/family.cmake                    | 2 +-
 src/common/tusb_mcu.h                         | 7 +++++++
 src/device/usbd.c                             | 3 ++-
 4 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 031b17a2e..e5e2f6856 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -31,8 +31,6 @@
 #include "tusb.h"
 #include "usb_descriptors.h"
 
-#include "pio_usb.h"
-
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 70e18293f..bb146d085 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -47,7 +47,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			hardware_irq
 			hardware_resets
 			pico_sync
-	    # for usb-pio
+      # for usb-pio
 	    hardware_dma
 	    hardware_pio
 	    pico_multicore
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 8eb4ad475..c1cf2a810 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -228,6 +228,8 @@
 #elif TU_CHECK_MCU(OPT_MCU_RP2040)
   #define TUP_DCD_ENDPOINT_MAX    16
 
+  #define TU_ATTR_FAST_FUNC   __attribute__((section(".time_critical.tinyusb")))
+
 //------------- Silabs -------------//
 #elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
   #define TUP_USBIP_DWC2
@@ -282,4 +284,9 @@
   #define TUP_RHPORT_HIGHSPEED    0x00
 #endif
 
+// fast function, normally mean placing function in SRAM
+#ifndef TU_ATTR_FAST_FUNC
+  #define TU_ATTR_FAST_FUNC
+#endif
+
 #endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 12b4071af..4c2cd3abd 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1071,7 +1071,8 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 //--------------------------------------------------------------------+
 // DCD Event Handler
 //--------------------------------------------------------------------+
-void __no_inline_not_in_flash_func(dcd_event_handler)(dcd_event_t const * event, bool in_isr)
+TU_ATTR_FAST_FUNC
+void dcd_event_handler(dcd_event_t const * event, bool in_isr)
 {
   switch (event->event_id)
   {

From ae5490e5a5cd8650a45578b4ac70dbe89b002fb1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Apr 2022 20:52:56 +0700
Subject: [PATCH 0988/2085] clean up

---
 examples/device/hid_boot_interface/src/tusb_config.h | 6 ++----
 examples/host/cdc_msc_hid/src/tusb_config.h          | 7 +++----
 src/common/tusb_debug.h                              | 6 +++---
 src/device/usbd.c                                    | 2 +-
 src/host/usbh.c                                      | 6 +++---
 src/portable/raspberrypi/pio_usb/dcd_pio_usb.c       | 1 -
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c       | 1 -
 7 files changed, 12 insertions(+), 17 deletions(-)

diff --git a/examples/device/hid_boot_interface/src/tusb_config.h b/examples/device/hid_boot_interface/src/tusb_config.h
index c8bb8a807..8bc85b722 100644
--- a/examples/device/hid_boot_interface/src/tusb_config.h
+++ b/examples/device/hid_boot_interface/src/tusb_config.h
@@ -40,10 +40,8 @@
 #endif
 
 // Use raspberry pio-usb for device
-#define CFG_TUD_RPI_PIO_USB            1
-#if CFG_TUD_RPI_PIO_USB
-#define BOARD_DEVICE_RHPORT_NUM 1
-#endif
+// #define CFG_TUD_RPI_PIO_USB     1
+// #define BOARD_DEVICE_RHPORT_NUM 1
 
 // RHPort number used for device can be defined by board.mk, default to port 0
 #ifndef BOARD_DEVICE_RHPORT_NUM
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 9d083c771..e9e68cf5a 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -40,13 +40,12 @@
 #endif
 
 // Use raspberry pio-usb for host
-#define CFG_TUH_RPI_PIO_USB            1
-//#define CFG_TUSB_RPI_PIO_INC_PATH   1
-
+// #define CFG_TUH_RPI_PIO_USB            1
+// #define CFG_TUH_RPI_PIO_USB            1
 
 #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
   #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
-#elif CFG_TUH_RPI_PIO_USB
+#elif defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB
   // rp2040: port0 is native, port 1 for PIO-USB
   #define CFG_TUSB_RHPORT1_MODE       OPT_MODE_HOST
 #else
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 1ea2c19f5..ac5bee6ec 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -57,7 +57,7 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
   #define tu_printf    printf
 #endif
 
-static inline void tu_print_var(uint8_t const* buf, uint32_t bufsize)
+static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 {
   for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
 }
@@ -75,8 +75,8 @@ static inline void tu_print_var(uint8_t const* buf, uint32_t bufsize)
 // Log Level 1: Error
 #define TU_LOG1               tu_printf
 #define TU_LOG1_MEM           tu_print_mem
-#define TU_LOG1_ARR(_x, _n)   tu_print_var((uint8_t const*)(_x), _n)
-#define TU_LOG1_VAR(_x)       tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
+#define TU_LOG1_ARR(_x, _n)   tu_print_arr((uint8_t const*)(_x), _n)
+#define TU_LOG1_VAR(_x)       tu_print_arr((uint8_t const*)(_x), sizeof(*(_x)))
 #define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
 #define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 4c2cd3abd..e545e8056 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -265,7 +265,7 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 //--------------------------------------------------------------------+
 
 enum { RHPORT_INVALID = 0xFFu };
-static volatile uint8_t _usbd_rhport = RHPORT_INVALID;
+static uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // usbd_int_set() is used as mutex in OS NONE config
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 4df60626a..a0d9d83d3 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -410,7 +410,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
       case HCD_EVENT_DEVICE_ATTACH:
         // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
         // one device before enumerating another one.
-        TU_LOG2("[rh%d] USBH DEVICE ATTACH\r\n", event.rhport);
+        TU_LOG2("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
         enum_new_device(&event);
       break;
 
@@ -799,7 +799,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
 
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
 {
-  TU_LOG2("[%u] Open EP0 with Size = %u\r\n", dev_addr, max_packet_size);
+  TU_LOG2("[%u:%u] Open EP0 with Size = %u\r\n", usbh_get_rhport(dev_addr), dev_addr, max_packet_size);
 
   tusb_desc_endpoint_t ep0_desc =
   {
@@ -1279,7 +1279,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
       if (_dev0.hub_addr == 0)
       {
         // connected directly to roothub
-#if !CFG_TUH_RPI_PIO_USB // skip this reset for pio-usb
+#if !CFG_TUH_RPI_PIO_USB // FIXME skip this reset for pio-usb
         hcd_port_reset( _dev0.rhport );
         osal_task_delay(RESET_DELAY);
         hcd_port_reset_end(_dev0.rhport);
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index 3daa39a8b..fb10087b5 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -29,7 +29,6 @@
 #if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && CFG_TUD_RPI_PIO_USB
 
 #include "pico.h"
-#include "hardware/pio.h"
 #include "pio_usb.h"
 #include "pio_usb_ll.h"
 
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index f6caabb54..3c7378561 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -29,7 +29,6 @@
 #if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && CFG_TUH_RPI_PIO_USB
 
 #include "pico.h"
-#include "hardware/pio.h"
 #include "pio_usb.h"
 #include "pio_usb_ll.h"
 

From a72d4e2462757d596bf35e0e805100a930111d6b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Apr 2022 20:54:21 +0700
Subject: [PATCH 0989/2085] make hcd_event_handler() fastfunc, and force inline
 other helper

---
 src/host/hcd.h  | 42 +++++++++++++++++++++++++++++++++++++++---
 src/host/usbh.c | 48 +-----------------------------------------------
 2 files changed, 40 insertions(+), 50 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 9b41f2447..036394c72 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -171,13 +171,49 @@ extern void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_i
 extern void hcd_event_handler(hcd_event_t const* event, bool in_isr);
 
 // Helper to send device attach event
-extern void hcd_event_device_attach(uint8_t rhport, bool in_isr);
+TU_ATTR_ALWAYS_INLINE static inline
+void hcd_event_device_attach(uint8_t rhport, bool in_isr)
+{
+  hcd_event_t event;
+  event.rhport              = rhport;
+  event.event_id            = HCD_EVENT_DEVICE_ATTACH;
+  event.connection.hub_addr = 0;
+  event.connection.hub_port = 0;
+  hcd_event_handler(&event, in_isr);
+}
 
 // Helper to send device removal event
-extern void hcd_event_device_remove(uint8_t rhport, bool in_isr);
+TU_ATTR_ALWAYS_INLINE static inline
+void hcd_event_device_remove(uint8_t rhport, bool in_isr)
+{
+  hcd_event_t event;
+  event.rhport              = rhport;
+  event.event_id            = HCD_EVENT_DEVICE_REMOVE;
+  event.connection.hub_addr = 0;
+  event.connection.hub_port = 0;
+
+  hcd_event_handler(&event, in_isr);
+}
 
 // Helper to send USB transfer event
-extern void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr);
+TU_ATTR_ALWAYS_INLINE static inline
+void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
+{
+  hcd_event_t event =
+  {
+    .rhport   = 0, // TODO correct rhport
+    .event_id = HCD_EVENT_XFER_COMPLETE,
+    .dev_addr = dev_addr,
+    .xfer_complete =
+    {
+      .ep_addr = ep_addr,
+      .result  = result,
+      .len     = xferred_bytes
+    }
+  };
+
+  hcd_event_handler(&event, in_isr);
+}
 
 #ifdef __cplusplus
  }
diff --git a/src/host/usbh.c b/src/host/usbh.c
index a0d9d83d3..99ba964d2 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -855,7 +855,7 @@ void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info)
   }
 }
 
-void hcd_event_handler(hcd_event_t const* event, bool in_isr)
+TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
 {
   switch (event->event_id)
   {
@@ -865,52 +865,6 @@ void hcd_event_handler(hcd_event_t const* event, bool in_isr)
   }
 }
 
-void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
-{
-  hcd_event_t event =
-  {
-    .rhport   = 0, // TODO correct rhport
-    .event_id = HCD_EVENT_XFER_COMPLETE,
-    .dev_addr = dev_addr,
-    .xfer_complete =
-    {
-      .ep_addr = ep_addr,
-      .result  = result,
-      .len     = xferred_bytes
-    }
-  };
-
-  hcd_event_handler(&event, in_isr);
-}
-
-void hcd_event_device_attach(uint8_t rhport, bool in_isr)
-{
-  hcd_event_t event =
-  {
-    .rhport   = rhport,
-    .event_id = HCD_EVENT_DEVICE_ATTACH
-  };
-
-  event.connection.hub_addr = 0;
-  event.connection.hub_port = 0;
-
-  hcd_event_handler(&event, in_isr);
-}
-
-void hcd_event_device_remove(uint8_t hostid, bool in_isr)
-{
-  hcd_event_t event =
-  {
-    .rhport   = hostid,
-    .event_id = HCD_EVENT_DEVICE_REMOVE
-  };
-
-  event.connection.hub_addr = 0;
-  event.connection.hub_port = 0;
-
-  hcd_event_handler(&event, in_isr);
-}
-
 //--------------------------------------------------------------------+
 // Descriptors Async
 //--------------------------------------------------------------------+

From 85dcb737749576d1c2946f3993b964c59974f38c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Apr 2022 18:00:30 +0700
Subject: [PATCH 0990/2085] more clean up

---
 lib/Pico-PIO-USB                               | 2 +-
 src/device/usbd.c                              | 3 +--
 src/host/usbh.c                                | 9 +++++----
 src/portable/raspberrypi/pio_usb/dcd_pio_usb.c | 1 +
 4 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index aecced02e..6f76de3c0 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit aecced02e756f3a35805cacdd9be25976b6dd978
+Subproject commit 6f76de3c0fb4679afc9f953cd4fec0637ebd2f15
diff --git a/src/device/usbd.c b/src/device/usbd.c
index e545e8056..1dd1a352e 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1071,8 +1071,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 //--------------------------------------------------------------------+
 // DCD Event Handler
 //--------------------------------------------------------------------+
-TU_ATTR_FAST_FUNC
-void dcd_event_handler(dcd_event_t const * event, bool in_isr)
+TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr)
 {
   switch (event->event_id)
   {
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 99ba964d2..74ffb5c38 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1139,7 +1139,7 @@ enum {
   //ENUM_HUB_GET_STATUS_1,
   ENUM_HUB_CLEAR_RESET_1,
   ENUM_ADDR0_DEVICE_DESC,
-  ENUM_RESET_2,         // 2nd reset before set address
+  ENUM_RESET_2,         // 2nd reset before set address (not used)
   ENUM_HUB_GET_STATUS_2,
   ENUM_HUB_CLEAR_RESET_2,
   ENUM_SET_ADDR,
@@ -1227,17 +1227,17 @@ static void process_enumeration(tuh_xfer_t* xfer)
     }
     break;
 
+#if 0
     case ENUM_RESET_2:
+      // XXX note used by now, but may be needed for some devices !?
       // Reset device again before Set Address
-      TU_LOG2("Port reset \r\n");
+      TU_LOG2("Port reset2 \r\n");
       if (_dev0.hub_addr == 0)
       {
         // connected directly to roothub
-#if !CFG_TUH_RPI_PIO_USB // FIXME skip this reset for pio-usb
         hcd_port_reset( _dev0.rhport );
         osal_task_delay(RESET_DELAY);
         hcd_port_reset_end(_dev0.rhport);
-#endif
         // TODO: fall through to SET ADDRESS, refactor later
       }
       #if CFG_TUH_HUB
@@ -1249,6 +1249,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
       }
       #endif
       __attribute__((fallthrough));
+#endif
 
     case ENUM_SET_ADDR:
       enum_request_set_addr();
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index fb10087b5..1bc5594d8 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -135,6 +135,7 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
   endpoint_t *ep = pio_usb_device_get_endpoint_by_address(ep_addr);
+  ep->has_transfer = false;
   ep->stalled = true;
 }
 

From 608577e05c9f2e2e8831d8819090ed376d08284b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 29 Apr 2022 18:05:50 +0700
Subject: [PATCH 0991/2085] update pio

---
 lib/Pico-PIO-USB | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 6f76de3c0..7e147ad44 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 6f76de3c0fb4679afc9f953cd4fec0637ebd2f15
+Subproject commit 7e147ad44dbd5038590449418b26fb867024db6c

From 0b30a10ab3c2f1fdcf4fae8f530c80bf5cffaf96 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 29 Apr 2022 22:24:36 +0700
Subject: [PATCH 0992/2085] configure hid_to_cdc example to build with rp2040
 with pio usb as host

---
 examples/host/hid_to_cdc/CMakeLists.txt    |   3 +-
 examples/host/hid_to_cdc/only.txt          |   1 +
 examples/host/hid_to_cdc/src/main.c        | 213 ++++++++++-----------
 examples/host/hid_to_cdc/src/tusb_config.h |  12 +-
 hw/bsp/rp2040/family.cmake                 |  56 ++++--
 lib/Pico-PIO-USB                           |   2 +-
 src/host/usbh.c                            |   2 +-
 7 files changed, 148 insertions(+), 141 deletions(-)

diff --git a/examples/host/hid_to_cdc/CMakeLists.txt b/examples/host/hid_to_cdc/CMakeLists.txt
index abc4d91da..ff9f58c4c 100644
--- a/examples/host/hid_to_cdc/CMakeLists.txt
+++ b/examples/host/hid_to_cdc/CMakeLists.txt
@@ -25,4 +25,5 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
+family_configure_host_example(${PROJECT})
diff --git a/examples/host/hid_to_cdc/only.txt b/examples/host/hid_to_cdc/only.txt
index 78d94e3ce..6ee8e3fde 100644
--- a/examples/host/hid_to_cdc/only.txt
+++ b/examples/host/hid_to_cdc/only.txt
@@ -1,2 +1,3 @@
 board:mimxrt1060_evk
 board:mimxrt1064_evk
+mcu:RP2040
diff --git a/examples/host/hid_to_cdc/src/main.c b/examples/host/hid_to_cdc/src/main.c
index cdf5d264e..f0e78887b 100644
--- a/examples/host/hid_to_cdc/src/main.c
+++ b/examples/host/hid_to_cdc/src/main.c
@@ -73,12 +73,14 @@ enum  {
 static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
 void led_blinking_task(void);
-void cdc_task(void);
 
 /*------------- MAIN -------------*/
 int main(void)
 {
   board_init();
+
+  printf("TinyUSB Host HID <-> Device CDC Example\r\n");
+
   tusb_init();
 
   while (1)
@@ -86,15 +88,13 @@ int main(void)
     tud_task(); // tinyusb device task
     tuh_task(); // tinyusb host task
     led_blinking_task();
-
-    cdc_task();
   }
 
   return 0;
 }
 
 //--------------------------------------------------------------------+
-// Device callbacks
+// Device CDC
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
@@ -124,8 +124,20 @@ void tud_resume_cb(void)
   blink_interval_ms = BLINK_MOUNTED;
 }
 
+// Invoked when CDC interface received data from host
+void tud_cdc_rx_cb(uint8_t itf)
+{
+  (void) itf;
+
+  char buf[64];
+  uint32_t count = tud_cdc_read(buf, sizeof(buf));
+
+  // TODO control LED on keyboard of host stack
+  (void) count;
+}
+
 //--------------------------------------------------------------------+
-// Host callbacks
+// Host HID
 //--------------------------------------------------------------------+
 
 // Invoked when device with hid interface is mounted
@@ -137,169 +149,138 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
 {
   (void)desc_report;
   (void)desc_len;
+
+  // Interface protocol (hid_interface_protocol_enum_t)
+  const char* protocol_str[] = { "None", "Keyboard", "Mouse" };
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+
   uint16_t vid, pid;
   tuh_vid_pid_get(dev_addr, &vid, &pid);
 
-  printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance);
-  printf("VID = %04x, PID = %04x\r\n", vid, pid);
+  printf("[%04x:%04x][%u] HID Interface instance = %d, Protocol = %s\r\n", vid, pid, dev_addr, instance, protocol_str[itf_protocol]);
 
-  // Receive any report and treat it like a keyboard.
+  // Receive report from boot keyboard & mouse only
   // tuh_hid_report_received_cb() will be invoked when report is available
-  if ( !tuh_hid_receive_report(dev_addr, instance) )
+  if (itf_protocol == HID_ITF_PROTOCOL_KEYBOARD || itf_protocol == HID_ITF_PROTOCOL_MOUSE)
   {
-    printf("Error: cannot request to receive report\r\n");
+    if ( !tuh_hid_receive_report(dev_addr, instance) )
+    {
+      printf("Error: cannot request report\r\n");
+    }
   }
 }
 
 // Invoked when device with hid interface is un-mounted
 void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
 {
-  printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+  printf("[%u] HID Interface instance = %d is unmounted\r\n", dev_addr, instance);
 }
 
 // keycodes from last report to check if key is holding or newly pressed
 uint8_t last_keycodes[6] = {0};
 
 // look up new key in previous keys
-static inline bool key_in_last_report(const uint8_t key_arr[6], uint8_t keycode)
+static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode)
 {
   for(uint8_t i=0; i<6; i++)
   {
-    if (key_arr[i] == keycode) return true;
+    if (report->keycode[i] == keycode)  return true;
   }
 
   return false;
 }
 
-// Invoked when received report from device via interrupt endpoint
-void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
+
+// convert hid keycode to ascii and print via usb device CDC (ignore non-printable)
+static void process_kbd_report(hid_keyboard_report_t const *report)
 {
-  if (len != 8)
-  {
-    char ch_num;
-
-    tud_cdc_write_str("incorrect report len: ");
-
-    if ( len > 10 )
-    {
-      ch_num = '0' + (len / 10);
-      tud_cdc_write(&ch_num, 1);
-      len = len % 10;
-    }
-
-    ch_num = '0' + len;
-    tud_cdc_write(&ch_num, 1);
-
-    tud_cdc_write_str("\r\n");
-    tud_cdc_write_flush();
-
-    // Don't request a new report for a wrong sized endpoint.
-    return;
-  }
-
-  uint8_t const modifiers = report[0];
+  static hid_keyboard_report_t prev_report = { 0, 0, {0} }; // previous report to check key released
   bool flush = false;
 
-  for (int i = 2; i < 8; i++)
+  for(uint8_t i=0; i<6; i++)
   {
-    uint8_t keycode = report[i];
-
-    if (keycode)
+    uint8_t keycode = report->keycode[i];
+    if ( keycode )
     {
-      if ( key_in_last_report(last_keycodes, keycode) )
+      if ( find_key_in_report(&prev_report, keycode) )
       {
         // exist in previous report means the current key is holding
-        // do nothing
       }else
       {
         // not existed in previous report means the current key is pressed
-        // Only print keycodes 0 - 128.
-        if (keycode < 128)
-        {
-          // remap the key code for Colemak layout so @tannewt can type.
-          #ifdef KEYBOARD_COLEMAK
-          uint8_t colemak_key_code = colemak[keycode];
-          if (colemak_key_code != 0) keycode = colemak_key_code;
-          #endif
 
-          bool const is_shift = modifiers & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
-          char c = keycode2ascii[keycode][is_shift ? 1 : 0];
-          if (c)
-          {
-            if (c == '\n') tud_cdc_write("\r", 1);
-            tud_cdc_write(&c, 1);
-            flush = true;
-          }
+        // remap the key code for Colemak layout
+        #ifdef KEYBOARD_COLEMAK
+        uint8_t colemak_key_code = colemak[keycode];
+        if (colemak_key_code != 0) keycode = colemak_key_code;
+        #endif
+
+        bool const is_shift = report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
+        uint8_t ch = keycode2ascii[keycode][is_shift ? 1 : 0];
+
+        if (ch)
+        {
+          if (ch == '\n') tud_cdc_write("\r", 1);
+          tud_cdc_write(&ch, 1);
+          flush = true;
         }
       }
     }
+    // TODO example skips key released
   }
 
   if (flush) tud_cdc_write_flush();
 
-  // save current report
-  memcpy(last_keycodes, report+2, 6);
+  prev_report = *report;
+}
+
+// send mouse report to usb device CDC
+static void process_mouse_report(hid_mouse_report_t const * report)
+{
+  static hid_mouse_report_t prev_report = { 0 };
+
+  char tempbuf[32];
+  int count;
+
+  //------------- button state  -------------//
+  //uint8_t button_changed_mask = report->buttons ^ prev_report.buttons;
+  char l = report->buttons & MOUSE_BUTTON_LEFT   ? 'L' : '-';
+  char m = report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-';
+  char r = report->buttons & MOUSE_BUTTON_RIGHT  ? 'R' : '-';
+
+  count = sprintf(tempbuf, " %c%c%c %d %d %d\r\n", l, m, r, report->x, report->y, report->wheel);
+
+  tud_cdc_write(tempbuf, count);
+  tud_cdc_write_flush();
+}
+
+// Invoked when received report from device via interrupt endpoint
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
+{
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+
+  switch(itf_protocol)
+  {
+    case HID_ITF_PROTOCOL_KEYBOARD:
+      process_kbd_report( (hid_keyboard_report_t const*) report );
+    break;
+
+    case HID_ITF_PROTOCOL_MOUSE:
+      process_mouse_report( (hid_mouse_report_t const*) report );
+    break;
+
+    default: break;
+  }
 
   // continue to request to receive report
   if ( !tuh_hid_receive_report(dev_addr, instance) )
   {
-    printf("Error: cannot request to receive report\r\n");
+    printf("Error: cannot request report\r\n");
   }
 }
 
-
-
 //--------------------------------------------------------------------+
-// USB CDC
-//--------------------------------------------------------------------+
-void cdc_task(void)
-{
-  // connected() check for DTR bit
-  // Most but not all terminal client set this when making connection
-  // if ( tud_cdc_connected() )
-  {
-    // connected and there are data available
-    if ( tud_cdc_available() )
-    {
-      // read datas
-      char buf[64];
-      uint32_t count = tud_cdc_read(buf, sizeof(buf));
-      (void) count;
-
-      // Echo back
-      // Note: Skip echo by commenting out write() and write_flush()
-      // for throughput test e.g
-      //    $ dd if=/dev/zero of=/dev/ttyACM0 count=10000
-      tud_cdc_write(buf, count);
-      tud_cdc_write_flush();
-    }
-  }
-}
-
-// Invoked when cdc when line state changed e.g connected/disconnected
-void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
-{
-  (void) itf;
-  (void) rts;
-
-  // TODO set some indicator
-  if ( dtr )
-  {
-    // Terminal connected
-  }else
-  {
-    // Terminal disconnected
-  }
-}
-
-// Invoked when CDC interface received data from host
-void tud_cdc_rx_cb(uint8_t itf)
-{
-  (void) itf;
-}
-
-//--------------------------------------------------------------------+
-// BLINKING TASK
+// Blinking Task
 //--------------------------------------------------------------------+
 void led_blinking_task(void)
 {
diff --git a/examples/host/hid_to_cdc/src/tusb_config.h b/examples/host/hid_to_cdc/src/tusb_config.h
index 9a35ffc30..0fa4899a9 100644
--- a/examples/host/hid_to_cdc/src/tusb_config.h
+++ b/examples/host/hid_to_cdc/src/tusb_config.h
@@ -49,6 +49,9 @@
   #define BOARD_HOST_RHPORT_NUM     1
 #endif
 
+// Use raspberry pio-usb for host
+#define CFG_TUH_RPI_PIO_USB            1
+
 // RHPort max operational speed can defined by board.mk
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
 #ifndef BOARD_DEVICE_RHPORT_SPEED
@@ -124,10 +127,6 @@
 
 //------------- CLASS -------------//
 #define CFG_TUD_CDC              1
-#define CFG_TUD_MSC              0
-#define CFG_TUD_HID              0
-#define CFG_TUD_MIDI             0
-#define CFG_TUD_VENDOR           0
 
 // CDC FIFO size of TX and RX
 #define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
@@ -144,14 +143,9 @@
 #define CFG_TUH_ENUMERATION_BUFSIZE 256
 
 #define CFG_TUH_HUB                 1
-#define CFG_TUH_CDC                 0
-#define CFG_TUH_MSC                 0
-#define CFG_TUH_VENDOR              0
-
 // max device support (excluding hub device)
 #define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
 
-//------------- HID -------------//
 #define CFG_TUH_HID                  4
 #define CFG_TUH_HID_EPIN_BUFSIZE    64
 #define CFG_TUH_HID_EPOUT_BUFSIZE   64
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index bb146d085..c3ea077bb 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -23,23 +23,20 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		set(PICO_TINYUSB_PATH ${TOP})
 	endif()
 
+  #------------------------------------
 	# Base config for both device and host; wrapped by SDK's tinyusb_common
+	#------------------------------------
 	add_library(tinyusb_common_base INTERFACE)
-	
+
 	target_sources(tinyusb_common_base INTERFACE
 			${TOP}/src/tusb.c
 			${TOP}/src/common/tusb_fifo.c
-			${TOP}/lib/Pico-PIO-USB/pio_usb.c
-			${TOP}/lib/Pico-PIO-USB/pio_usb_host.c
-			${TOP}/lib/Pico-PIO-USB/pio_usb_device.c
-			${TOP}/lib/Pico-PIO-USB/usb_crc.c
 			)
 
 	target_include_directories(tinyusb_common_base INTERFACE
 			${TOP}/src
 			${TOP}/src/common
 			${TOP}/hw
-			${TOP}/lib/Pico-PIO-USB
 			)
 
 	target_link_libraries(tinyusb_common_base INTERFACE
@@ -47,10 +44,6 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			hardware_irq
 			hardware_resets
 			pico_sync
-      # for usb-pio
-	    hardware_dma
-	    hardware_pio
-	    pico_multicore
 			)
 
 	set(TINYUSB_DEBUG_LEVEL 0)
@@ -65,7 +58,35 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
 	)
 
+  #------------------------------------
+  # PIO USB for both host and device
+  #------------------------------------
+  add_library(tinyusb_pio_usb_base INTERFACE)
+
+	target_sources(tinyusb_pio_usb_base INTERFACE
+			${TOP}/lib/Pico-PIO-USB/pio_usb.c
+			${TOP}/lib/Pico-PIO-USB/pio_usb_host.c
+			${TOP}/lib/Pico-PIO-USB/pio_usb_device.c
+			${TOP}/lib/Pico-PIO-USB/usb_crc.c
+			)
+
+	target_include_directories(tinyusb_pio_usb_base INTERFACE
+			${TOP}/lib/Pico-PIO-USB
+			)
+
+	target_link_libraries(tinyusb_pio_usb_base INTERFACE
+	    hardware_dma
+	    hardware_pio
+	    pico_multicore
+			)
+
+	target_compile_definitions(tinyusb_pio_usb_base INTERFACE
+			PIO_USB_USE_TINYUSB
+	)
+
+  #------------------------------------
 	# Base config for device mode; wrapped by SDK's tinyusb_device
+	#------------------------------------
 	add_library(tinyusb_device_base INTERFACE)
 	target_sources(tinyusb_device_base INTERFACE
 			${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -87,7 +108,9 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			${TOP}/src/class/video/video_device.c
 			)
 
+	#------------------------------------
 	# Base config for host mode; wrapped by SDK's tinyusb_host
+	#------------------------------------
 	add_library(tinyusb_host_base INTERFACE)
 	target_sources(tinyusb_host_base INTERFACE
 			${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -105,7 +128,10 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	target_compile_definitions(tinyusb_host_base INTERFACE
 			RP2040_USB_HOST_MODE=1
 	)
-	
+
+	#------------------------------------
+	# BSP & Additions
+	#------------------------------------
 	add_library(tinyusb_bsp INTERFACE)
 	target_sources(tinyusb_bsp INTERFACE
 			${TOP}/hw/bsp/rp2040/family.c
@@ -139,6 +165,10 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	  )
 	endif()
 
+	#------------------------------------
+	# Functions
+	#------------------------------------
+
 	function(family_configure_target TARGET)
 		pico_add_extra_outputs(${TARGET})
 		pico_enable_stdio_uart(${TARGET} 1)
@@ -147,12 +177,12 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 
 	function(family_configure_device_example TARGET)
 		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device)
+		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_pio_usb_base)
 	endfunction()
 
 	function(family_configure_host_example TARGET)
 		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
+		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host tinyusb_pio_usb_base)
 	endfunction()
 
 	function(family_initialize_project PROJECT DIR)
diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 7e147ad44..1ab409f13 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 7e147ad44dbd5038590449418b26fb867024db6c
+Subproject commit 1ab409f13bd888b8f1f7c9bf3bd7269d1ccc1c79
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 74ffb5c38..e0e41a8d1 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -630,7 +630,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 
   if (XFER_RESULT_SUCCESS != result)
   {
-    TU_LOG2("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED");
+    TU_LOG1("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED");
 
     // terminate transfer if any stage failed
     _xfer_complete(dev_addr, result);

From c289438b75af9b256a954c6a9293a21825c53e04 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 29 Apr 2022 23:03:52 +0700
Subject: [PATCH 0993/2085] fix ci build

---
 examples/host/hid_to_cdc/src/main.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/examples/host/hid_to_cdc/src/main.c b/examples/host/hid_to_cdc/src/main.c
index f0e78887b..cc811cd71 100644
--- a/examples/host/hid_to_cdc/src/main.c
+++ b/examples/host/hid_to_cdc/src/main.c
@@ -237,8 +237,6 @@ static void process_kbd_report(hid_keyboard_report_t const *report)
 // send mouse report to usb device CDC
 static void process_mouse_report(hid_mouse_report_t const * report)
 {
-  static hid_mouse_report_t prev_report = { 0 };
-
   char tempbuf[32];
   int count;
 

From d51743a21cb23f7e0c81844f12bba08420a52a29 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sun, 1 May 2022 14:04:36 +0200
Subject: [PATCH 0994/2085] Add TU_BREAKPOINT for mips architecture

_mips is provided by xc32-gcc
---
 src/common/tusb_verify.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 568bac8cc..a52a6d269 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -90,6 +90,9 @@
 #elif defined(__riscv)
   #define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0)
 
+#elif defined(_mips)
+  #define TU_BREAKPOINT() do { __asm("sdbbp 0"); } while (0)
+
 #else
   #define TU_BREAKPOINT() do {} while (0)
 #endif

From c145777e0eb6b9add414504dd8cf4ec7da6cc61a Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sun, 1 May 2022 14:14:42 +0200
Subject: [PATCH 0995/2085] dcd_pic32: Add asserts transfer sanity check

TU_ASSERTS added to detect transfer inconsistency.
---
 src/portable/microchip/pic32mz/dcd_pic32mz.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c
index 7d48f755b..1683d95b4 100644
--- a/src/portable/microchip/pic32mz/dcd_pic32mz.c
+++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c
@@ -530,6 +530,7 @@ static void ep0_handle_rx(void)
 
   transferred = rx_fifo_read(0, xfer->buffer + xfer->transferred);
   xfer->transferred += transferred;
+  TU_ASSERT(xfer->transferred <= xfer->total_len,);
   if (transferred < xfer->max_packet_size || xfer->transferred == xfer->total_len)
   {
     ep0_set_stage(EP0_STAGE_DATA_OUT_COMPLETE);
@@ -560,6 +561,7 @@ static void epn_handle_rx_int(uint8_t epnum)
     transferred = rx_fifo_read(epnum, xfer->buffer + xfer->transferred);
     USB_REGS->EPCSR[epnum].RXCSRL_HOSTbits.RXPKTRDY = 0;
     xfer->transferred += transferred;
+    TU_ASSERT(xfer->transferred <= xfer->total_len,);
     if (transferred < xfer->max_packet_size || xfer->transferred == xfer->total_len)
     {
       xfer_complete(xfer, XFER_RESULT_SUCCESS, true);
@@ -579,6 +581,7 @@ static void epn_handle_tx_int(uint8_t epnum)
   else
   {
     xfer->transferred += xfer->last_packet_size;
+    TU_ASSERT(xfer->transferred <= xfer->total_len,);
     if (xfer->last_packet_size < xfer->max_packet_size || xfer->transferred == xfer->total_len)
     {
       xfer->last_packet_size = 0;

From e49cad84e2798ddd4ee49d3684ce7b414d30ccb2 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Sun, 1 May 2022 14:18:53 +0200
Subject: [PATCH 0996/2085] dcd_pic32: Fix memory overwrite in incoming data

When transfer was finished rx_fifo_read() read all that
was to read RXPKTRDY was cleared allowing next packet to
be received.
Then xfer_complete was called.
Interrupt for OUT endpoint was left enable, that would not
be a problem if data was handled fast and new transfer was
scheduled.
For MSC when host sends a lot of data this interrupt that was
enabled could cause epn_handle_rx_int() to be called after
transfer was completed and next was not scheduled yet.
Without TU_ASSERT that was added to detect this, incoming
data was written past buffer provided by user code resulting
in random memory corruption.

This just blocks RX interrupt when transfer is finished,
and also only unmasked rx interrupts are handled.
---
 src/portable/microchip/pic32mz/dcd_pic32mz.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c
index 1683d95b4..2103d41fb 100644
--- a/src/portable/microchip/pic32mz/dcd_pic32mz.c
+++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c
@@ -564,6 +564,7 @@ static void epn_handle_rx_int(uint8_t epnum)
     TU_ASSERT(xfer->transferred <= xfer->total_len,);
     if (transferred < xfer->max_packet_size || xfer->transferred == xfer->total_len)
     {
+      USB_REGS->INTRRXEbits.w &= ~(1u << epnum);
       xfer_complete(xfer, XFER_RESULT_SUCCESS, true);
     }
   }
@@ -692,7 +693,7 @@ void dcd_int_handler(uint8_t rhport)
   int i;
   uint8_t mask;
   __USBCSR2bits_t csr2_bits;
-  uint16_t rxints = USB_REGS->INTRRX;
+  uint16_t rxints = USB_REGS->INTRRX & USB_REGS->INTRRXEbits.w;
   uint16_t txints = USB_REGS->INTRTX;
   csr2_bits = USBCSR2bits;
   (void) rhport;

From f452ab745ef953d74704bc5429ff16a80a5b325a Mon Sep 17 00:00:00 2001
From: Pascal Speck <info@iktek.de>
Date: Tue, 3 May 2022 09:52:10 +0200
Subject: [PATCH 0997/2085] overwrite grstctl on edpt_disable

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index c71f38d2d..01b74d05e 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -796,7 +796,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
-    dwc2->grstctl |= (epnum << GRSTCTL_TXFNUM_Pos);
+    dwc2->grstctl = (epnum << GRSTCTL_TXFNUM_Pos);
     dwc2->grstctl |= GRSTCTL_TXFFLSH;
     while ( (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {}
   }

From f19d913b5d67ecf1b4f4d84c9d9a5880376f5a21 Mon Sep 17 00:00:00 2001
From: caleb crome <caleb@crome.org>
Date: Thu, 5 May 2022 14:36:02 -0700
Subject: [PATCH 0998/2085] set irq priority for freertos

---
 hw/bsp/imxrt/family.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index a811a7e40..8d34d4b9f 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -51,7 +51,10 @@ void board_init(void)
   SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-//  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#ifdef USB_OTG2_IRQn
+  NVIC_SetPriority(USB_OTG2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
 #endif
 
   // LED

From 79b5ab822ec1a17d6bfe88f6135613ba50acedbd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 6 May 2022 17:22:52 +0700
Subject: [PATCH 0999/2085] fix incorrect total number of interface

---
 examples/host/hid_to_cdc/src/usb_descriptors.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/examples/host/hid_to_cdc/src/usb_descriptors.c b/examples/host/hid_to_cdc/src/usb_descriptors.c
index 7dd73937c..e55899f65 100644
--- a/examples/host/hid_to_cdc/src/usb_descriptors.c
+++ b/examples/host/hid_to_cdc/src/usb_descriptors.c
@@ -81,7 +81,6 @@ enum
 {
   ITF_NUM_CDC = 0,
   ITF_NUM_CDC_DATA,
-  ITF_NUM_MSC,
   ITF_NUM_TOTAL
 };
 

From 26ee62222290abf016ff4eb801d1289e05e595a1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 10 May 2022 12:51:48 +0700
Subject: [PATCH 1000/2085] move pio usb files to src

---
 hw/bsp/rp2040/family.cmake | 14 +++++++-------
 lib/Pico-PIO-USB           |  2 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index c3ea077bb..f51976d39 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -64,14 +64,14 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
   add_library(tinyusb_pio_usb_base INTERFACE)
 
 	target_sources(tinyusb_pio_usb_base INTERFACE
-			${TOP}/lib/Pico-PIO-USB/pio_usb.c
-			${TOP}/lib/Pico-PIO-USB/pio_usb_host.c
-			${TOP}/lib/Pico-PIO-USB/pio_usb_device.c
-			${TOP}/lib/Pico-PIO-USB/usb_crc.c
+			${TOP}/lib/Pico-PIO-USB/src/pio_usb.c
+			${TOP}/lib/Pico-PIO-USB/src/pio_usb_host.c
+			${TOP}/lib/Pico-PIO-USB/src/pio_usb_device.c
+			${TOP}/lib/Pico-PIO-USB/src/usb_crc.c
 			)
 
 	target_include_directories(tinyusb_pio_usb_base INTERFACE
-			${TOP}/lib/Pico-PIO-USB
+			${TOP}/lib/Pico-PIO-USB/src
 			)
 
 	target_link_libraries(tinyusb_pio_usb_base INTERFACE
@@ -190,8 +190,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		_family_initialize_project(${PROJECT} ${DIR})
 		enable_language(C CXX ASM)
 		pico_sdk_init()
-    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/usb_tx.pio)
-    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/usb_rx.pio)
+    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/src/usb_tx.pio)
+    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/src/usb_rx.pio)
 	endfunction()
 
 	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 1ab409f13..d2c6c4592 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 1ab409f13bd888b8f1f7c9bf3bd7269d1ccc1c79
+Subproject commit d2c6c459277816466cc087a5e27f41d2ce257f46

From e3b57cea05b5e023bba7472bf8c583d4adc29e3e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 10 May 2022 13:01:28 +0700
Subject: [PATCH 1001/2085] rename host/hid_to_cdc to
 dual/host_hid_to_device_cdc

---
 .../hid_to_cdc => dual/host_hid_to_device_cdc}/CMakeLists.txt     | 0
 .../{host/hid_to_cdc => dual/host_hid_to_device_cdc}/Makefile     | 0
 .../{host/hid_to_cdc => dual/host_hid_to_device_cdc}/only.txt     | 0
 .../{host/hid_to_cdc => dual/host_hid_to_device_cdc}/src/main.c   | 0
 .../hid_to_cdc => dual/host_hid_to_device_cdc}/src/tusb_config.h  | 0
 .../host_hid_to_device_cdc}/src/usb_descriptors.c                 | 0
 6 files changed, 0 insertions(+), 0 deletions(-)
 rename examples/{host/hid_to_cdc => dual/host_hid_to_device_cdc}/CMakeLists.txt (100%)
 rename examples/{host/hid_to_cdc => dual/host_hid_to_device_cdc}/Makefile (100%)
 rename examples/{host/hid_to_cdc => dual/host_hid_to_device_cdc}/only.txt (100%)
 rename examples/{host/hid_to_cdc => dual/host_hid_to_device_cdc}/src/main.c (100%)
 rename examples/{host/hid_to_cdc => dual/host_hid_to_device_cdc}/src/tusb_config.h (100%)
 rename examples/{host/hid_to_cdc => dual/host_hid_to_device_cdc}/src/usb_descriptors.c (100%)

diff --git a/examples/host/hid_to_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
similarity index 100%
rename from examples/host/hid_to_cdc/CMakeLists.txt
rename to examples/dual/host_hid_to_device_cdc/CMakeLists.txt
diff --git a/examples/host/hid_to_cdc/Makefile b/examples/dual/host_hid_to_device_cdc/Makefile
similarity index 100%
rename from examples/host/hid_to_cdc/Makefile
rename to examples/dual/host_hid_to_device_cdc/Makefile
diff --git a/examples/host/hid_to_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt
similarity index 100%
rename from examples/host/hid_to_cdc/only.txt
rename to examples/dual/host_hid_to_device_cdc/only.txt
diff --git a/examples/host/hid_to_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
similarity index 100%
rename from examples/host/hid_to_cdc/src/main.c
rename to examples/dual/host_hid_to_device_cdc/src/main.c
diff --git a/examples/host/hid_to_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
similarity index 100%
rename from examples/host/hid_to_cdc/src/tusb_config.h
rename to examples/dual/host_hid_to_device_cdc/src/tusb_config.h
diff --git a/examples/host/hid_to_cdc/src/usb_descriptors.c b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
similarity index 100%
rename from examples/host/hid_to_cdc/src/usb_descriptors.c
rename to examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c

From 993f7b6a2c0b325683ebb4f7dc5b0039d92c1eab Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 10 May 2022 13:15:07 +0700
Subject: [PATCH 1002/2085] include dual examples to ci

---
 tools/build_board.py  | 11 +++++------
 tools/build_family.py | 11 +++++------
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/tools/build_board.py b/tools/build_board.py
index b2a80c680..4d895329a 100644
--- a/tools/build_board.py
+++ b/tools/build_board.py
@@ -28,12 +28,11 @@ def filter_with_input(mylist):
 
 # If examples are not specified in arguments, build all
 all_examples = []
-for entry in os.scandir("examples/device"):
-    if entry.is_dir():
-        all_examples.append("device/" + entry.name)
-for entry in os.scandir("examples/host"):
-    if entry.is_dir():
-        all_examples.append("host/" + entry.name)
+for dir1 in os.scandir("examples"):
+    if dir1.is_dir():
+        for entry in os.scandir(dir1.path):
+            if entry.is_dir():
+                all_examples.append(dir1.name + '/' + entry.name)
 filter_with_input(all_examples)
 all_examples.sort()
 
diff --git a/tools/build_family.py b/tools/build_family.py
index 4094d07db..095ca4ff7 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -28,12 +28,11 @@ def filter_with_input(mylist):
 
 # If examples are not specified in arguments, build all
 all_examples = []
-for entry in os.scandir("examples/device"):
-    if entry.is_dir():
-        all_examples.append("device/" + entry.name)
-for entry in os.scandir("examples/host"):
-    if entry.is_dir():
-        all_examples.append("host/" + entry.name)
+for dir1 in os.scandir("examples"):
+    if dir1.is_dir():
+        for entry in os.scandir(dir1.path):
+            if entry.is_dir():
+                all_examples.append(dir1.name + '/' + entry.name)
 filter_with_input(all_examples)
 all_examples.sort()
 

From 717a47412548923123141503749f721184222cf0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 10 May 2022 21:56:47 +0700
Subject: [PATCH 1003/2085] move pio-usb init to
 family_configure_pio_usb_example() to stay compatible

---
 examples/dual/host_hid_to_device_cdc/CMakeLists.txt |  1 +
 examples/host/bare_api/CMakeLists.txt               |  5 ++++-
 examples/host/cdc_msc_hid/CMakeLists.txt            |  3 +++
 examples/host/hid_controller/CMakeLists.txt         |  5 ++++-
 hw/bsp/rp2040/family.cmake                          | 13 +++++++++----
 5 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index ff9f58c4c..bf3e042d1 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -27,3 +27,4 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
 family_configure_host_example(${PROJECT})
+family_configure_pio_usb_example(${PROJECT})
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index bff281a8c..e2e8d4fd5 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -24,4 +24,7 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
\ No newline at end of file
+family_configure_host_example(${PROJECT})
+
+# For rp2040, un-comment to enable pico-pio-usb
+# family_configure_pio_usb_example(${PROJECT})
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 95c07339e..ca0f8e48a 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -27,3 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
+
+# For rp2040, un-comment to enable pico-pio-usb
+# family_configure_pio_usb_example(${PROJECT})
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index aaf8bc34f..60678fc1c 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -25,4 +25,7 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
\ No newline at end of file
+family_configure_host_example(${PROJECT})
+
+# For rp2040, un-comment to enable pico-pio-usb
+# family_configure_pio_usb_example(${PROJECT})
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index f51976d39..06ca74988 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -177,12 +177,19 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 
 	function(family_configure_device_example TARGET)
 		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_pio_usb_base)
+		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device)
 	endfunction()
 
 	function(family_configure_host_example TARGET)
 		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host tinyusb_pio_usb_base)
+		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
+	endfunction()
+
+	function(family_configure_pio_usb_example TARGET)
+		family_configure_target(${TARGET})
+		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_pio_usb_base)
+    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/src/usb_tx.pio)
+    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/src/usb_rx.pio)
 	endfunction()
 
 	function(family_initialize_project PROJECT DIR)
@@ -190,8 +197,6 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		_family_initialize_project(${PROJECT} ${DIR})
 		enable_language(C CXX ASM)
 		pico_sdk_init()
-    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/src/usb_tx.pio)
-    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/src/usb_rx.pio)
 	endfunction()
 
 	# This method must be called from the project scope to suppress known warnings in TinyUSB source files

From 35b77a4a81b62da0558630a7148fb3934faa4391 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 10 May 2022 22:14:00 +0700
Subject: [PATCH 1004/2085] cmake lib rename

---
 .../dual/host_hid_to_device_cdc/CMakeLists.txt     |  2 +-
 examples/host/bare_api/CMakeLists.txt              |  2 +-
 examples/host/cdc_msc_hid/CMakeLists.txt           |  2 +-
 examples/host/hid_controller/CMakeLists.txt        |  2 +-
 hw/bsp/rp2040/family.cmake                         | 14 +++++++-------
 5 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index bf3e042d1..24ebfdec3 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -27,4 +27,4 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
 family_configure_host_example(${PROJECT})
-family_configure_pio_usb_example(${PROJECT})
+family_configure_pico_pio_usb_example(${PROJECT})
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index e2e8d4fd5..607ef22eb 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -27,4 +27,4 @@ target_include_directories(${PROJECT} PUBLIC
 family_configure_host_example(${PROJECT})
 
 # For rp2040, un-comment to enable pico-pio-usb
-# family_configure_pio_usb_example(${PROJECT})
+# family_configure_pico_pio_usb_example(${PROJECT})
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index ca0f8e48a..214e9f2e7 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -29,4 +29,4 @@ target_include_directories(${PROJECT} PUBLIC
 family_configure_host_example(${PROJECT})
 
 # For rp2040, un-comment to enable pico-pio-usb
-# family_configure_pio_usb_example(${PROJECT})
+# family_configure_pico_pio_usb_example(${PROJECT})
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index 60678fc1c..6227e0790 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -28,4 +28,4 @@ target_include_directories(${PROJECT} PUBLIC
 family_configure_host_example(${PROJECT})
 
 # For rp2040, un-comment to enable pico-pio-usb
-# family_configure_pio_usb_example(${PROJECT})
+# family_configure_pico_pio_usb_example(${PROJECT})
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 06ca74988..f52274c15 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -61,26 +61,26 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
   #------------------------------------
   # PIO USB for both host and device
   #------------------------------------
-  add_library(tinyusb_pio_usb_base INTERFACE)
+  add_library(pico_pio_usb INTERFACE)
 
-	target_sources(tinyusb_pio_usb_base INTERFACE
+	target_sources(pico_pio_usb INTERFACE
 			${TOP}/lib/Pico-PIO-USB/src/pio_usb.c
 			${TOP}/lib/Pico-PIO-USB/src/pio_usb_host.c
 			${TOP}/lib/Pico-PIO-USB/src/pio_usb_device.c
 			${TOP}/lib/Pico-PIO-USB/src/usb_crc.c
 			)
 
-	target_include_directories(tinyusb_pio_usb_base INTERFACE
+	target_include_directories(pico_pio_usb INTERFACE
 			${TOP}/lib/Pico-PIO-USB/src
 			)
 
-	target_link_libraries(tinyusb_pio_usb_base INTERFACE
+	target_link_libraries(pico_pio_usb INTERFACE
 	    hardware_dma
 	    hardware_pio
 	    pico_multicore
 			)
 
-	target_compile_definitions(tinyusb_pio_usb_base INTERFACE
+	target_compile_definitions(pico_pio_usb INTERFACE
 			PIO_USB_USE_TINYUSB
 	)
 
@@ -185,9 +185,9 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
 	endfunction()
 
-	function(family_configure_pio_usb_example TARGET)
+	function(family_configure_pico_pio_usb_example TARGET)
 		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_pio_usb_base)
+		target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_pio_usb)
     pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/src/usb_tx.pio)
     pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/src/usb_rx.pio)
 	endfunction()

From 8473ca16fb74edcb32a050ef087d5f30f50c599b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 10 May 2022 22:56:06 +0700
Subject: [PATCH 1005/2085] clean up

---
 .../dual/host_hid_to_device_cdc/src/main.c     |  3 ---
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 18 ++++++++++--------
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index cc811cd71..c05d65c9e 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -176,9 +176,6 @@ void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
   printf("[%u] HID Interface instance = %d is unmounted\r\n", dev_addr, instance);
 }
 
-// keycodes from last report to check if key is holding or newly pressed
-uint8_t last_keycodes[6] = {0};
-
 // look up new key in previous keys
 static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode)
 {
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 3c7378561..1b2d29331 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -50,6 +50,8 @@ static pio_usb_configuration_t pio_host_config = PIO_USB_DEFAULT_CONFIG;
 //--------------------------------------------------------------------+
 bool hcd_init(uint8_t rhport)
 {
+  (void) rhport;
+
   // To run USB SOF interrupt in core1, call this init in core1
   pio_usb_host_init(&pio_host_config);
 
@@ -58,19 +60,19 @@ bool hcd_init(uint8_t rhport)
 
 void hcd_port_reset(uint8_t rhport)
 {
-  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_port_reset_start(pio_rhport);
 }
 
 void hcd_port_reset_end(uint8_t rhport)
 {
-  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_port_reset_end(pio_rhport);
 }
 
 bool hcd_port_connect_status(uint8_t rhport)
 {
-  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
 
   root_port_t *root = PIO_USB_ROOT_PORT(pio_rhport);
   port_pin_status_t line_state = pio_usb_bus_get_line_state(root);
@@ -81,14 +83,14 @@ bool hcd_port_connect_status(uint8_t rhport)
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   // TODO determine link speed
-  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return PIO_USB_ROOT_PORT(pio_rhport)->is_fullspeed ? TUSB_SPEED_FULL : TUSB_SPEED_LOW;
 }
 
 // Close all opened endpoint belong to this device
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 {
-  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_close_device(pio_rhport, dev_addr);
 }
 
@@ -118,19 +120,19 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   hcd_devtree_get_info(dev_addr, &dev_tree);
   bool const need_pre = (dev_tree.hub_addr && dev_tree.speed == TUSB_SPEED_LOW);
 
-  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const*) desc_ep, need_pre);
 }
 
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
-  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen);
 }
 
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
-  uint8_t pio_rhport = RHPORT_PIO(rhport);
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_host_send_setup(pio_rhport, dev_addr, setup_packet);
 }
 

From 8bd923f5f17fd124f9b479df031ecb82cd6cc2d9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 11 May 2022 00:37:45 +0700
Subject: [PATCH 1006/2085] sync with pio usb

---
 lib/Pico-PIO-USB | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index d2c6c4592..9d2b7dae4 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit d2c6c459277816466cc087a5e27f41d2ce257f46
+Subproject commit 9d2b7dae4261e0f6a336a125972e16aab65be722

From f09df55ab986deea6d2df1168b1ad6f8eddd2ff1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 11 May 2022 15:40:02 +0700
Subject: [PATCH 1007/2085] clean up example

---
 .../dual/host_hid_to_device_cdc/src/main.c    | 28 +++++++++++--------
 lib/Pico-PIO-USB                              |  2 +-
 2 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index c05d65c9e..3e5724451 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -23,10 +23,8 @@
  *
  */
 
-// This example runs both host and device concurrently. The USB host looks for
-// any HID device with reports that are 8 bytes long and then assumes they are
-// keyboard reports. It translates the keypresses of the reports to ASCII and
-// transmits it over CDC to the device's host.
+// This example runs both host and device concurrently. The USB host receive
+// reports from HID device and print it out over USB Device CDC interface.
 
 #include <stdlib.h>
 #include <stdio.h>
@@ -157,7 +155,11 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
   uint16_t vid, pid;
   tuh_vid_pid_get(dev_addr, &vid, &pid);
 
-  printf("[%04x:%04x][%u] HID Interface instance = %d, Protocol = %s\r\n", vid, pid, dev_addr, instance, protocol_str[itf_protocol]);
+  char tempbuf[256];
+  int count = sprintf(tempbuf, "[%04x:%04x][%u] HID Interface instance = %d, Protocol = %s\r\n", vid, pid, dev_addr, instance, protocol_str[itf_protocol]);
+
+  tud_cdc_write(tempbuf, count);
+  tud_cdc_write_flush();
 
   // Receive report from boot keyboard & mouse only
   // tuh_hid_report_received_cb() will be invoked when report is available
@@ -165,7 +167,7 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
   {
     if ( !tuh_hid_receive_report(dev_addr, instance) )
     {
-      printf("Error: cannot request report\r\n");
+      tud_cdc_write_str("Error: cannot request report\r\n");
     }
   }
 }
@@ -173,7 +175,10 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
 // Invoked when device with hid interface is un-mounted
 void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
 {
-  printf("[%u] HID Interface instance = %d is unmounted\r\n", dev_addr, instance);
+  char tempbuf[256];
+  int count = sprintf(tempbuf, "[%u] HID Interface instance = %d is unmounted\r\n", dev_addr, instance);
+  tud_cdc_write(tempbuf, count);
+  tud_cdc_write_flush();
 }
 
 // look up new key in previous keys
@@ -234,16 +239,14 @@ static void process_kbd_report(hid_keyboard_report_t const *report)
 // send mouse report to usb device CDC
 static void process_mouse_report(hid_mouse_report_t const * report)
 {
-  char tempbuf[32];
-  int count;
-
   //------------- button state  -------------//
   //uint8_t button_changed_mask = report->buttons ^ prev_report.buttons;
   char l = report->buttons & MOUSE_BUTTON_LEFT   ? 'L' : '-';
   char m = report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-';
   char r = report->buttons & MOUSE_BUTTON_RIGHT  ? 'R' : '-';
 
-  count = sprintf(tempbuf, " %c%c%c %d %d %d\r\n", l, m, r, report->x, report->y, report->wheel);
+  char tempbuf[32];
+  int count = sprintf(tempbuf, "%c%c%c %d %d %d\r\n", l, m, r, report->x, report->y, report->wheel);
 
   tud_cdc_write(tempbuf, count);
   tud_cdc_write_flush();
@@ -252,6 +255,7 @@ static void process_mouse_report(hid_mouse_report_t const * report)
 // Invoked when received report from device via interrupt endpoint
 void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len)
 {
+  (void) len;
   uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
 
   switch(itf_protocol)
@@ -270,7 +274,7 @@ void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t cons
   // continue to request to receive report
   if ( !tuh_hid_receive_report(dev_addr, instance) )
   {
-    printf("Error: cannot request report\r\n");
+    tud_cdc_write_str("Error: cannot request report\r\n");
   }
 }
 
diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
index 9d2b7dae4..53ec09168 160000
--- a/lib/Pico-PIO-USB
+++ b/lib/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 9d2b7dae4261e0f6a336a125972e16aab65be722
+Subproject commit 53ec09168c5a3cd30d8dcb577fa97dc328d769d4

From c5ba1ea8c17a379beb47d9689e85e2ce6e67206f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 13 May 2022 22:54:47 +0700
Subject: [PATCH 1008/2085] changes proposal to audio feedback computation

---
 src/class/audio/audio_device.c | 251 ++++++++++++++-------------------
 src/class/audio/audio_device.h | 102 ++++----------
 src/common/tusb_common.h       |   6 -
 src/device/usbd.c              |   6 +-
 src/device/usbd.h              |   2 +-
 5 files changed, 136 insertions(+), 231 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index b0a49fb04..c3a252a2c 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -261,6 +261,13 @@ osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
 #endif
 #endif
 
+enum {
+  FEEDBACK_COMPUTE_DISABLED,
+  FEEDBACK_COMPUTE_FLOAT,
+  FEEDBACK_COMPUTE_FIXED,
+  FEEDBACK_COMPUTE_POWER_OF_2,
+};
+
 typedef struct
 {
   uint8_t rhport;
@@ -305,38 +312,22 @@ typedef struct
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER
-  uint32_t fb_val;                                                                        // Feedback value for asynchronous mode (in 16.16 format).
-  uint8_t fb_n_frames;                                                                    // Number of (micro)frames used to estimate feedback value
-#endif
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
-  volatile uint32_t fb_val;                                                               // Feedback value for asynchronous mode (in 16.16 format).
-  uint32_t fb_val_min;                                                                    // Maximum allowed feedback value according to UAC2 FMT-2.0 section 2.3.1.1.
-  uint32_t fb_val_max;                                                                    // Maximum allowed feedback value according to UAC2 FMT-2.0 section 2.3.1.1.
-  uint8_t fb_n_frames;                                                                    // Number of (micro)frames used to estimate feedback value
-  volatile uint8_t fb_n_frames_current;                                                   // Current (micro)frame number
-  volatile uint32_t fb_n_cycles_old;                                                      // Old cycle count
-  uint32_t * fb_param_p_cycle_count;                                                      // Pointer to cycle counter
+  uint32_t fb_val;                      // Feedback value for asynchronous mode (in 16.16 format).
+  uint8_t fb_n_frames;                  // Number of (micro)frames used to estimate feedback value
+  uint8_t fb_n_frames_shift;
+  uint8_t fb_compute_method;
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT
+  uint32_t fb_val_min;                  // Maximum allowed feedback value according to UAC2 FMT-2.0 section 2.3.1.1.
+  uint32_t fb_val_max;                  // Maximum allowed feedback value according to UAC2 FMT-2.0 section 2.3.1.1.
+
+  // should be union
   uint8_t fb_power_of_two_val;
-#endif
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT
   float fb_float_val;
-#endif
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT
-  uint64_t fb_param_factor_N;                                                       // Numerator of feedback parameter coefficient
-  uint64_t fb_param_factor_D;                                                       // Denominator of feedback parameter coefficient
-#endif
-#endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER
-  volatile uint32_t fb_val;                                                               // Feedback value for asynchronous mode (in 16.16 format).
-  uint8_t fb_n_frames;                                                                    // Number of (micro)frames used to estimate feedback value
-#endif
+  uint32_t fb_param_factor_N;
+  uint32_t fb_param_factor_D;
 
 #endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -453,8 +444,8 @@ static inline uint8_t tu_desc_subtype(void const* desc)
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER)
-static bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
 #endif
 
 bool tud_audio_n_mounted(uint8_t func_id)
@@ -1695,16 +1686,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
           if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1)   // Check if usage is explicit data feedback
           {
             audio->ep_fb = ep_addr;
-            audio->fb_n_frames = desc_ep->bInterval;
+            audio->fb_n_frames = 1 << (desc_ep->bInterval -1);
+            audio->fb_n_frames_shift = desc_ep->bInterval -1;
 
-#if ((CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER) || (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER))
-            usbd_sof_enable(rhport, true);       // Enable SOF interrupt
-#endif
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
-            audio->fb_n_frames_current = 0;
-            audio->fb_n_cycles_old = 0;
-#endif
+            // Enable SOF interrupt if callback is implemented
+            if (tud_audio_sof_isr) usbd_sof_enable(rhport, true);
 
             //            // Invoke callback after ep_out is set
             //            if (audio->ep_out != 0)
@@ -1725,6 +1711,24 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
       // Invoke one callback for a final set interface
       if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
 
+      // Prepare feedback computation if callback is available
+      if (tud_audio_feedback_params_cb)
+      {
+        uint32_t sample_freq = 0;
+        uint32_t mclk_freq = 0;
+        uint8_t fixed_point = 0;
+        tud_audio_feedback_params_cb(func_id, alt, &sample_freq, &mclk_freq, &fixed_point);
+
+        if ( sample_freq == 0 || mclk_freq == 0 )
+        {
+          audio->fb_compute_method = FEEDBACK_COMPUTE_DISABLED;
+        }else
+        {
+          audio->fb_compute_method = fixed_point ? FEEDBACK_COMPUTE_FIXED : FEEDBACK_COMPUTE_FLOAT;
+          set_fb_params(audio, sample_freq, mclk_freq);
+        }
+      }
+
       // We are done - abort loop
       break;
     }
@@ -1734,22 +1738,17 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   }
 
   // Disable SOF interrupt if no driver has any enabled feedback EP
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && ((CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER) || (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER))
-
   bool disable = true;
-
   for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
   {
     if (_audiod_fct[i].ep_fb != 0)
     {
       disable = false;
+      break;
     }
   }
-
   if (disable) usbd_sof_enable(rhport, false);
 
-#endif
-
   tud_control_status(rhport, p_request);
 
   return true;
@@ -2022,7 +2021,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     // Transmission of feedback EP finished
     if (_audiod_fct[func_id].ep_fb == ep_addr)
     {
-      if (tud_audio_fb_done_cb) TU_VERIFY(tud_audio_fb_done_cb(rhport));
+      if (tud_audio_fb_done_cb) tud_audio_fb_done_cb(func_id);
 
       // Schedule a transmit with the new value if EP is not busy 
       if (!usbd_edpt_busy(rhport, _audiod_fct[func_id].ep_fb))
@@ -2038,81 +2037,93 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
   return false;
 }
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && ((CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER) || (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER))
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 uint8_t tud_audio_n_get_fb_n_frames(uint8_t func_id)
 {
   return _audiod_fct[func_id].fb_n_frames;
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER)
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
-// This function must be called from the user within the tud_audio_set_itf_cb(rhport, p_request) callback function, where p_request needs to be checked as
-// uint8_t const itf = tu_u16_low(p_request->wIndex);
-// uint8_t const alt = tu_u16_low(p_request->wValue);
-// such that tud_audio_set_fb_params() gets called with the parameters corresponding to the defined interface and alternate setting
-// Also, start the main clock cycle counter (or reset its value) within tud_audio_set_itf_cb()
-TU_ATTR_WEAK bool tud_audio_set_fb_params(uint8_t func_id, uint32_t f_m, uint32_t f_s, uint32_t * p_cycle_count)
+static bool set_fb_params(audiod_function_t* audio, uint32_t f_s, uint32_t f_m)
 {
-  audiod_function_t* audio = &_audiod_fct[func_id];
-  audio->fb_param_p_cycle_count = p_cycle_count;
-
   // Check if frame interval is within sane limits
   // The interval value audio->fb_n_frames was taken from the descriptors within audiod_set_interface()
 
-  // n_frames_min is ceil(2^10 * f_s / f_m) for full speed and ceil(2^13 * f_s / f_m) for high speed - this lower limit ensures the measures feedback value has sufficient precision
-  if ((TUSB_SPEED_FULL == tud_speed_get() && ((2^10 * f_s / f_m) + 1) > audio->fb_n_frames) || (TUSB_SPEED_HIGH == tud_speed_get() && ((2^13 * f_s / f_m) + 1) > audio->fb_n_frames))
+  // n_frames_min is ceil(2^10 * f_s / f_m) for full speed and ceil(2^13 * f_s / f_m) for high speed
+  // this lower limit ensures the measures feedback value has sufficient precision
+  uint32_t const k = (TUSB_SPEED_FULL == tud_speed_get()) ? 10 : 13;
+  if ( (((1UL << k) * f_s / f_m) + 1) > audio->fb_n_frames )
   {
-    TU_LOG2("  UAC2 feedback interval too small\r\n"); TU_BREAKPOINT(); return false;
+    TU_LOG1("  UAC2 feedback interval too small\r\n"); TU_BREAKPOINT(); return false;
   }
 
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT
   // Check if parameters really allow for a power of two division
-  if ((f_m % f_s) != 0 || !tu_is_power_of_two(audio->fb_n_frames * f_m / f_s))
+  if ((f_m % f_s) == 0 && tu_is_power_of_two(f_m / f_s))
   {
-    TU_LOG2("  FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT not possible!\r\n"); TU_BREAKPOINT(); return false;
+    audio->fb_compute_method = FEEDBACK_COMPUTE_POWER_OF_2;
+    audio->fb_power_of_two_val = 16 - audio->fb_n_frames_shift - tu_log2(f_m / f_s);
+  }else if ( audio->fb_compute_method == FEEDBACK_COMPUTE_FLOAT)
+  {
+    audio->fb_float_val = (float)f_s / f_m * (1UL << (16 - audio->fb_n_frames_shift));
+  }else
+  {
+    audio->fb_param_factor_N = f_s;
+    audio->fb_param_factor_D = f_m;
   }
 
-  audio->fb_power_of_two_val = 16 - tu_log2(audio->fb_n_frames * f_m / f_s);
-#endif
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT
-  audio->fb_float_val = (float)f_s / audio->fb_n_frames / f_m * (1 << 16);
-#endif
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT
-
-  // f_s max is 2^19-1 = 524287 Hz
-  // f_m max is 2^29/(1 ms * n_frames) for full speed and 2^29/(125 us * n_frames) for high speed, this means for f_m fitting in an uint32, n_frames must be < 125 for full speed and < 1000 for high speed (1000 does not fit into uint8 so the maximum possible value cannot even be reached by UAC2 - we don't need to check for it)
-
-  if ((f_s > (2^19)-1) || (TUSB_SPEED_FULL == tud_speed_get() && (audio->fb_n_frames > 125)))
-  {
-    // If this check fails, not every thing is lost - you need to re-evaluate the scaling factors of the parameters such that the numbers fit into uint64 again. feedback = n_cycles * S_c / (n_frames * S_n) * f_s * S_s / (f_m * S_m). In the end S_c*S_s / (S_n * S_m) = 2^16 for a 16.16 fixed point precision. If you find something, define your own function of tud_audio_set_feedback_params_fm_fs() and audiod_sof() and use your values
-    TU_LOG2("  FEEDBACK_DETERMINATION_MODE_FIXED_POINT not possible!\r\n"); TU_BREAKPOINT(); return false;
-  }
-
-  audio->fb_param_factor_N = (uint64_t)f_s << 13;
-  audio->fb_param_factor_D = (uint64_t)f_m * audio->fb_n_frames;
-#endif
-
-  audio->fb_val_min = ((TUSB_SPEED_FULL == tud_speed_get() ? (f_s/1000) : (f_s/8000)) - 1) << 16;   // Minimal value in 16.16 format for full speed (1ms per frame) or high speed (125 us per frame)
-  audio->fb_val_max = ((TUSB_SPEED_FULL == tud_speed_get() ? (f_s/1000) : (f_s/8000)) + 1) << 16;   // Maximum value in 16.16 format
+  // Minimal/Maximum value in 16.16 format for full speed (1ms per frame) or high speed (125 us per frame)
+  uint32_t const frame_div = (TUSB_SPEED_FULL == tud_speed_get()) ? 1000 : 8000;
+  audio->fb_val_min = (f_s/frame_div - 1) << 16;
+  audio->fb_val_max = (f_s/frame_div + 1) << 16;
 
   return true;
-
 }
 #endif
 
-TU_ATTR_WEAK void audiod_sof (uint8_t rhport, uint32_t frame_count)
+uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
+{
+  audiod_function_t* audio = &_audiod_fct[func_id];
+  uint32_t feedback;
+
+  switch (audio->fb_compute_method)
+  {
+    case FEEDBACK_COMPUTE_POWER_OF_2:
+      feedback = cycles << audio->fb_power_of_two_val;
+    break;
+
+    case FEEDBACK_COMPUTE_FLOAT:
+      feedback = (uint32_t) ((float) cylces * audio->fb_float_val);
+    break;
+
+    case FEEDBACK_COMPUTE_FIXED:
+    {
+      uint64_t fb64 = (((uint64_t) cycles) * audio->fb_param_factor_N) << (16 - audio->fb_n_frames_shift);
+      feedback = (uint32_t) (fb64 / audio->fb_param_factor_D);
+    }
+    break;
+
+    default: return 0;
+  }
+
+  // For Windows: https://docs.microsoft.com/en-us/windows-hardware/drivers/audio/usb-2-0-audio-drivers
+  // The size of isochronous packets created by the device must be within the limits specified in FMT-2.0 section 2.3.1.1.
+  // This means that the deviation of actual packet size from nominal size must not exceed +/- one audio slot
+  // (audio slot = channel count samples).
+  if ( feedback > audio->fb_val_max ) feedback = audio->fb_val_max;
+  if ( feedback < audio->fb_val_min ) feedback = audio->fb_val_min;
+
+  tud_audio_n_fb_set(func_id, feedback);
+
+  return feedback;
+}
+
+void audiod_sof_isr (uint8_t rhport, uint32_t frame_count)
 {
   (void) rhport;
-  (void) frame_count;         // frame_count is not used since some devices may not provide the frame count value
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-
-#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER)
-
   // Determine feedback value - The feedback method is described in 5.12.4.2 of the USB 2.0 spec
   // Boiled down, the feedback value Ff = n_samples / (micro)frame.
   // Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_m) frames need to be measured, where K = 10 for full speed and K = 13 for high speed, f_s is the sampling frequency e.g. 48 kHz and f_m is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
@@ -2126,59 +2137,13 @@ TU_ATTR_WEAK void audiod_sof (uint8_t rhport, uint32_t frame_count)
 
     if (audio->ep_fb != 0)
     {
-      audio->fb_n_frames_current++;
-      if (audio->fb_n_frames_current == audio->fb_n_frames)
+      uint32_t const interval = (1UL << audio->fb_n_frames);
+      if ( 0 == (frame_count & (interval-1)) )
       {
-        uint32_t n_cylces = *audio->fb_param_p_cycle_count;
-        uint32_t feedback;
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT
-        feedback = (n_cylces - audio->fb_n_cycles_old) << audio->fb_power_of_two_val;
-#endif
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT
-        feedback = (uint32_t)((float)(n_cylces - audio->fb_n_cycles_old) * audio->fb_float_val);
-#endif
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT
-        feedback = ((n_cylces - audio->fb_n_cycles_old) << 3) * audio->fb_param_factor_N / audio->fb_param_factor_D;          // feeback_param_factor_N has scaling factor of 13 bits, n_cycles 3 and feeback_param_factor_D 1, hence 16.16 precision
-#endif
-
-        // For Windows: https://docs.microsoft.com/en-us/windows-hardware/drivers/audio/usb-2-0-audio-drivers
-        // The size of isochronous packets created by the device must be within the limits specified in FMT-2.0 section 2.3.1.1. This means that the deviation of actual packet size from nominal size must not exceed +/- one audio slot (audio slot = channel count samples).
-
-        if (feedback > audio->fb_val_max){
-          feedback = audio->fb_val_max;
-        }
-        if ( feedback < audio->fb_val_min) {
-          feedback = audio->fb_val_min;
-        }
-
-        // Buffer count checks ?
-
-        tud_audio_n_fb_set(i, feedback);
-        audio->fb_n_frames_current = 0;
-        audio->fb_n_cycles_old = n_cylces;
+        if(tud_audio_sof_isr) tud_audio_sof_isr(i, frame_count);
       }
     }
   }
-
-#endif // (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER)
-
-#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER)
-  // Iterate over audio functions and call callback function
-  for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
-  {
-    audiod_function_t* audio = &_audiod_fct[i];
-
-    if (audio->ep_fb != 0)
-    {
-      tud_audio_sof_isr_cb(i, frame_count);
-    }
-  }
-
-#endif // (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER)
-
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 }
 
@@ -2459,11 +2424,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
-static bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
-#else
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
-#endif
 {
   TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
 
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index e8721cf27..9ed7d1da4 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -191,41 +191,6 @@
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION     0                             // 0 or 1
 #endif
 
-// Possible options for determination of feedback value
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER                 1         // Feedback value must be determined by the user itself and set by use of tud_audio_n_fb_set(). The feedback value may be determined e.g. from some fill status of some FIFO buffer. Advantage: No ISR interrupt is enabled, hence the CPU need not to handle an ISR every 1ms or 125us and thus less CPU load, disadvantage: typically a larger FIFO is needed to compensate for jitter (e.g. 8 frames), i.e. a larger delay is introduced.
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER            2         // Feedback value is calculated within the audio driver by use of SOF interrupt. The driver needs information about the master clock f_m from which the audio sample frequency f_s is derived, f_s itself, and the cycle count of f_m at time of the SOF interrupt (e.g. by use of a hardware counter) - see tud_audio_set_fb_params(). Advantage: Reduced jitter in the feedback value computation, hence, the receive FIFO can be smaller (e.g. 2 frames) and thus a smaller delay is possible, disadvantage: higher CPU load due to SOF ISR handling every frame i.e. 1ms or 125us. This option is a great starting point to try the SOF ISR option but depending on your hardware setup (performance of the CPU) it might not work. If so, figure out why and use the next option. (The most critical point is the reading of the cycle counter value of f_m. It is read from within the SOF ISR - see: audiod_sof() -, hence, the ISR must has a high priority such that no software dependent "random" delay i.e. jitter is introduced).
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER                    3         // Feedback value is determined by the user by use of SOF interrupt. The user may use tud_audio_sof_isr_cb() which is called every SOF (of course only invoked when an alternate interface other than zero was set). The number of frames used to determine the feedback value for the currently active alternate setting can be get by tud_audio_get_fb_n_frames(). The feedback value must be set by use of tud_audio_n_fb_set().
-
-// Determine feedback value within SOF ISR within audio driver - if disabled the user has to call tud_audio_n_fb_set() with a suitable feedback value on its own. If done within audio driver SOF ISR, tud_audio_n_fb_set() is disabled for user
-#ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION                                CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER
-#endif
-
-#ifdef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION
-#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER)
-#error Unknown CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION. Possible choices are: CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER, CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER, or CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER!
-#endif
-#endif
-
-// Feeback calculation mode
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
-
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT     1
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT                  2
-#define CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT            3
-
-#ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE
-#error You must tell the driver the feedback determination mode! Possible choices are: CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT, CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT, or CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT!
-#endif
-
-#ifdef CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE
-#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE != CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT)
-#error Unknown CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE. Possible choices are: CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_POWER_OF_TWO_SHIFT, CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FLOAT, or CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_MODE_FIXED_POINT!
-#endif
-#endif
-
-#endif
-
 // Audio interrupt control EP size - disabled if 0
 #ifndef CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
 #define CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN                     0                             // Audio interrupt control - if required - 6 Bytes according to UAC 2 specification (p. 74)
@@ -493,9 +458,14 @@ TU_ATTR_WEAK bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_byte
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-TU_ATTR_WEAK bool tud_audio_fb_done_cb(uint8_t rhport);
+TU_ATTR_WEAK void tud_audio_fb_done_cb(uint8_t func_id);
 
-#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER)
+
+// determined by the user itself and set by use of tud_audio_n_fb_set(). The feedback value may be determined e.g. from some fill status of some FIFO buffer. Advantage: No ISR interrupt is enabled, hence the CPU need not to handle an ISR every 1ms or 125us and thus less CPU load, disadvantage: typically a larger FIFO is needed to compensate for jitter (e.g. 8 frames), i.e. a larger delay is introduced.
+
+// Feedback value is calculated within the audio driver by use of SOF interrupt. The driver needs information about the master clock f_m from which the audio sample frequency f_s is derived, f_s itself, and the cycle count of f_m at time of the SOF interrupt (e.g. by use of a hardware counter) - see tud_audio_set_fb_params(). Advantage: Reduced jitter in the feedback value computation, hence, the receive FIFO can be smaller (e.g. 2 frames) and thus a smaller delay is possible, disadvantage: higher CPU load due to SOF ISR handling every frame i.e. 1ms or 125us. This option is a great starting point to try the SOF ISR option but depending on your hardware setup (performance of the CPU) it might not work. If so, figure out why and use the next option. (The most critical point is the reading of the cycle counter value of f_m. It is read from within the SOF ISR - see: audiod_sof() -, hence, the ISR must has a high priority such that no software dependent "random" delay i.e. jitter is introduced).
+
+// Feedback value is determined by the user by use of SOF interrupt. The user may use tud_audio_sof_isr() which is called every SOF (of course only invoked when an alternate interface other than zero was set). The number of frames used to determine the feedback value for the currently active alternate setting can be get by tud_audio_get_fb_n_frames(). The feedback value must be set by use of tud_audio_n_fb_set().
 
 // This function is used to provide data rate feedback from an asynchronous sink. Feedback value will be sent at FB endpoint interval till it's changed.
 //
@@ -508,41 +478,11 @@ TU_ATTR_WEAK bool tud_audio_fb_done_cb(uint8_t rhport);
 
 // Feedback value can be determined from within the SOF ISR of the audio driver. This should reduce jitter. If the feature is used, the user can not set the feedback value.
 
-bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
-static inline bool tud_audio_fb_set(uint32_t feedback);
-
-uint8_t tud_audio_n_get_fb_n_frames(uint8_t func_id);
-static inline uint8_t tud_audio_get_fb_n_frames();
-
-#endif // (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER)
-
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
-
-// f_m : Main clock frequency in Hz i.e. master clock to which sample clock is locked
-// f_s : Current sample rate in Hz
-// p_cycle_count : Pointer to main clock cycle counter register where the current count can be read from (e.g. a timer register)
-
-// This function must be called from the user within the tud_audio_set_itf_cb(rhport, p_request) callback function, where p_request needs to be checked as
-// uint8_t const itf = tu_u16_low(p_request->wIndex);
-// uint8_t const alt = tu_u16_low(p_request->wValue);
-// such that tud_audio_set_fb_params() gets called with the parameters corresponding to the defined interface and alternate setting
-// Also, start the main clock cycle counter (or reset its value) within tud_audio_set_itf_cb()
-bool tud_audio_set_fb_params(uint8_t func_id, uint32_t f_m, uint32_t f_s, uint32_t * p_cycle_count);
-
-#endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_AUDIO_DRIVER
-
-#if (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER)
-
-// This function is used to provide data rate feedback from an asynchronous sink. Feedback value will be sent at FB endpoint interval till it's changed.
-//
-// The feedback format is specified to be 16.16 for HS and 10.14 for FS devices (see Universal Serial Bus Specification Revision 2.0 5.12.4.2). By default,
-// the choice of format is left to the caller and feedback argument is sent as-is. If CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION is set, then tinyusb
-// expects 16.16 format and handles the conversion to 10.14 on FS.
-//
-// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the
-// driver can work with either format. So a good compromise is to keep format correction disabled and stick to 16.16 format.
-
-// Feedback value can be determined from within the SOF ISR of the audio driver. This should reduce jitter. If the feature is used, the user can not set the feedback value.
+// Determine feedback value - The feedback method is described in 5.12.4.2 of the USB 2.0 spec
+// Boiled down, the feedback value Ff = n_samples / (micro)frame.
+// Since an accuracy of less than 1 Sample / second is desired, at least n_frames = ceil(2^K * f_s / f_m) frames need to be measured, where K = 10 for full speed and K = 13 for high speed, f_s is the sampling frequency e.g. 48 kHz and f_m is the cpu clock frequency e.g. 100 MHz (or any other master clock whose clock count is available and locked to f_s)
+// The update interval in the (4.10.2.1) Feedback Endpoint Descriptor must be less or equal to 2^(K - P), where P = min( ceil(log2(f_m / f_s)), K)
+// feedback = n_cycles / n_frames * f_s / f_m in 16.16 format, where n_cycles are the number of main clock cycles within fb_n_frames
 
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
 static inline bool tud_audio_fb_set(uint32_t feedback);
@@ -550,9 +490,18 @@ static inline bool tud_audio_fb_set(uint32_t feedback);
 uint8_t tud_audio_n_get_fb_n_frames(uint8_t func_id);
 static inline uint8_t tud_audio_get_fb_n_frames();
 
-TU_ATTR_WEAK void tud_audio_sof_isr_cb(uint8_t func_id, uint32_t frame);
+// Update feedback value with passed cycles since last time this update function is called.
+// Typically called within tud_audio_sof_isr(). Required tud_audio_feedback_params_cb() is implemented
+// This function will also call tud_audio_feedback_set()
+// return feedback value in 16.16 for reference (0 for error)
+uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles);
 
-#endif // (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER)
+// mclk_freq   : Main clock frequency in Hz i.e. master clock to which sample clock is locked
+// sample_freq : sample frequency in Hz
+// fixed_point : 0 float (default), 1 fixed point (for mcu without FPU)
+TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, uint32_t* sample_freq, uint32_t* mclk_freq, uint8_t* fixed_point);
+
+TU_ATTR_WEAK void tud_audio_sof_isr(uint8_t func_id, uint32_t frame);
 
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
@@ -695,7 +644,8 @@ static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t l
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP && ((CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_NO_SOF_BY_USER) || (CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION == CFG_TUD_AUDIO_ENABLE_FEEDBACK_DETERMINATION_OPTION_SOF_BY_USER))
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+
 static inline bool tud_audio_fb_set(uint32_t feedback)
 {
   return tud_audio_n_fb_set(0, feedback);
@@ -716,7 +666,7 @@ void     audiod_reset          (uint8_t rhport);
 uint16_t audiod_open           (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
 bool     audiod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
 bool     audiod_xfer_cb        (uint8_t rhport, uint8_t edpt_addr, xfer_result_t result, uint32_t xferred_bytes);
-void     audiod_sof            (uint8_t rhport, uint32_t frame_count);
+void     audiod_sof_isr        (uint8_t rhport, uint32_t frame_count);
 
 #ifdef __cplusplus
 }
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index bcdf8933a..b1ee40a1a 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -134,12 +134,6 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { retur
 //------------- Mathematics -------------//
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d -1)/d; }
 
-/// inclusive range checking TODO remove
-TU_ATTR_ALWAYS_INLINE static inline bool tu_within(uint32_t lower, uint32_t value, uint32_t upper)
-{
-  return (lower <= value) && (value <= upper);
-}
-
 // log2 of a value is its MSB's position
 // TODO use clz TODO remove
 static inline uint8_t tu_log2(uint32_t value)
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 8ab67c8de..b32cee813 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -69,7 +69,7 @@ typedef struct
   volatile uint8_t cfg_num; // current active configuration (0x00 is not configured)
   uint8_t speed;
 
-  uint8_t itf2drv[16];                      // map interface number to driver (0xff is invalid)
+  uint8_t itf2drv[CFG_TUD_INTERFACE_MAX];   // map interface number to driver (0xff is invalid)
   uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid ), can use only 4-bit each
 
   tu_edpt_state_t ep_status[CFG_TUD_ENDPPOINT_MAX][2];
@@ -134,7 +134,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = audiod_open,
     .control_xfer_cb  = audiod_control_xfer_cb,
     .xfer_cb          = audiod_xfer_cb,
-    .sof_isr          = audiod_sof
+    .sof_isr          = audiod_sof_isr
   },
   #endif
 
@@ -170,7 +170,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = vendord_open,
     .control_xfer_cb  = tud_vendor_control_xfer_cb,
     .xfer_cb          = vendord_xfer_cb,
-    .sof_isr              = NULL
+    .sof_isr          = NULL
   },
   #endif
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index d485d8711..30a27c5ee 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -33,7 +33,7 @@
 extern "C" {
 #endif
 
-typedef void (*tud_sof_isr_t) (uint32_t frame_count);
+// typedef void (*tud_sof_isr_t) (uint32_t frame_count);
 
 //--------------------------------------------------------------------+
 // Application API

From 20b810d25b60f3ab1b2ec58186bbb739b6b5c9b7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 13 May 2022 23:01:06 +0700
Subject: [PATCH 1009/2085] fix ci build

---
 src/class/audio/audio_device.c | 7 ++++++-
 src/class/audio/audio_device.h | 3 ++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index c3a252a2c..a81ddc53e 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1708,6 +1708,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
       TU_VERIFY(foundEPs == nEps);
 
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
       // Invoke one callback for a final set interface
       if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
 
@@ -1728,6 +1729,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
           set_fb_params(audio, sample_freq, mclk_freq);
         }
       }
+#endif
 
       // We are done - abort loop
       break;
@@ -1737,6 +1739,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     p_desc = tu_desc_next(p_desc);
   }
 
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
   // Disable SOF interrupt if no driver has any enabled feedback EP
   bool disable = true;
   for(uint8_t i=0; i < CFG_TUD_AUDIO; i++)
@@ -1748,6 +1751,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     }
   }
   if (disable) usbd_sof_enable(rhport, false);
+#endif
 
   tud_control_status(rhport, p_request);
 
@@ -2080,7 +2084,6 @@ static bool set_fb_params(audiod_function_t* audio, uint32_t f_s, uint32_t f_m)
 
   return true;
 }
-#endif
 
 uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
 {
@@ -2118,10 +2121,12 @@ uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
 
   return feedback;
 }
+#endif
 
 void audiod_sof_isr (uint8_t rhport, uint32_t frame_count)
 {
   (void) rhport;
+  (void) frame_count;
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
   // Determine feedback value - The feedback method is described in 5.12.4.2 of the USB 2.0 spec
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 9ed7d1da4..22394aaca 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -490,6 +490,8 @@ static inline bool tud_audio_fb_set(uint32_t feedback);
 uint8_t tud_audio_n_get_fb_n_frames(uint8_t func_id);
 static inline uint8_t tud_audio_get_fb_n_frames();
 
+#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+
 // Update feedback value with passed cycles since last time this update function is called.
 // Typically called within tud_audio_sof_isr(). Required tud_audio_feedback_params_cb() is implemented
 // This function will also call tud_audio_feedback_set()
@@ -503,7 +505,6 @@ TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf,
 
 TU_ATTR_WEAK void tud_audio_sof_isr(uint8_t func_id, uint32_t frame);
 
-#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
 TU_ATTR_WEAK bool tud_audio_int_ctr_done_cb(uint8_t rhport, uint16_t n_bytes_copied);

From be2a51316cd708a99899732acf43920537b97526 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 16 May 2022 13:29:12 +0700
Subject: [PATCH 1010/2085] remove pico-usb fork

---
 .gitmodules | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/.gitmodules b/.gitmodules
index e1489d303..21bbf08c0 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -146,6 +146,3 @@
 [submodule "hw/mcu/allwinner"]
 	path = hw/mcu/allwinner
 	url = https://github.com/hathach/allwinner_driver.git
-[submodule "lib/Pico-PIO-USB"]
-	path = lib/Pico-PIO-USB
-	url = https://github.com/hathach/Pico-PIO-USB.git

From 4586d8f119f779d1ef5f937e5c79e0ea2c84579c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 16 May 2022 13:44:06 +0700
Subject: [PATCH 1011/2085] add upstream Pico-PIO-USB

---
 .github/workflows/build_arm.yml  |  2 +-
 .gitmodules                      |  3 +++
 hw/bsp/rp2040/family.cmake       | 18 +++++++++++-------
 hw/mcu/raspberry_pi/Pico-PIO-USB |  1 +
 4 files changed, 16 insertions(+), 8 deletions(-)
 create mode 160000 hw/mcu/raspberry_pi/Pico-PIO-USB

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 085274eb5..bec879a93 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -82,7 +82,7 @@ jobs:
       run: |
         git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
         echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
-        git submodule update --init lib/Pico-PIO-USB
+        git submodule update --init hw/mcu/raspberry_pi/Pico-PIO-USB
 
     - name: Set Toolchain URL
       run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz
diff --git a/.gitmodules b/.gitmodules
index 21bbf08c0..044ac24ec 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -146,3 +146,6 @@
 [submodule "hw/mcu/allwinner"]
 	path = hw/mcu/allwinner
 	url = https://github.com/hathach/allwinner_driver.git
+[submodule "hw/mcu/raspberry_pi/Pico-PIO-USB"]
+	path = hw/mcu/raspberry_pi/Pico-PIO-USB
+	url = https://github.com/sekigon-gonnoc/Pico-PIO-USB.git
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index f52274c15..17ae3de9b 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -63,15 +63,19 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
   #------------------------------------
   add_library(pico_pio_usb INTERFACE)
 
+  if (NOT DEFINED PICO_PIO_USB_PATH)
+    set(PICO_PIO_USB_PATH "${TOP}/hw/mcu/raspberry_pi/Pico-PIO-USB")
+  endif()
+
 	target_sources(pico_pio_usb INTERFACE
-			${TOP}/lib/Pico-PIO-USB/src/pio_usb.c
-			${TOP}/lib/Pico-PIO-USB/src/pio_usb_host.c
-			${TOP}/lib/Pico-PIO-USB/src/pio_usb_device.c
-			${TOP}/lib/Pico-PIO-USB/src/usb_crc.c
+			${PICO_PIO_USB_PATH}/src/pio_usb.c
+			${PICO_PIO_USB_PATH}/src/pio_usb_host.c
+			${PICO_PIO_USB_PATH}/src/pio_usb_device.c
+			${PICO_PIO_USB_PATH}/src/usb_crc.c
 			)
 
 	target_include_directories(pico_pio_usb INTERFACE
-			${TOP}/lib/Pico-PIO-USB/src
+			${PICO_PIO_USB_PATH}/src
 			)
 
 	target_link_libraries(pico_pio_usb INTERFACE
@@ -188,8 +192,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	function(family_configure_pico_pio_usb_example TARGET)
 		family_configure_target(${TARGET})
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_pio_usb)
-    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/src/usb_tx.pio)
-    pico_generate_pio_header(tinyusb_common_base ${TOP}/lib/Pico-PIO-USB/src/usb_rx.pio)
+    pico_generate_pio_header(tinyusb_common_base ${PICO_PIO_USB_PATH}/src/usb_tx.pio)
+    pico_generate_pio_header(tinyusb_common_base ${PICO_PIO_USB_PATH}/src/usb_rx.pio)
 	endfunction()
 
 	function(family_initialize_project PROJECT DIR)
diff --git a/hw/mcu/raspberry_pi/Pico-PIO-USB b/hw/mcu/raspberry_pi/Pico-PIO-USB
new file mode 160000
index 000000000..2a9fefd6c
--- /dev/null
+++ b/hw/mcu/raspberry_pi/Pico-PIO-USB
@@ -0,0 +1 @@
+Subproject commit 2a9fefd6ccf42e5d8570ae83fdc54c9c875ebdd1

From e0e9426c2a912c2c405da602b1bf8d75d16f92e7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 16 May 2022 16:00:15 +0700
Subject: [PATCH 1012/2085] print addres of mouse input

---
 examples/dual/host_hid_to_device_cdc/src/main.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index 3e5724451..62ecb2c3f 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -156,7 +156,7 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
   tuh_vid_pid_get(dev_addr, &vid, &pid);
 
   char tempbuf[256];
-  int count = sprintf(tempbuf, "[%04x:%04x][%u] HID Interface instance = %d, Protocol = %s\r\n", vid, pid, dev_addr, instance, protocol_str[itf_protocol]);
+  int count = sprintf(tempbuf, "[%04x:%04x][%u] HID Interface%u, Protocol = %s\r\n", vid, pid, dev_addr, instance, protocol_str[itf_protocol]);
 
   tud_cdc_write(tempbuf, count);
   tud_cdc_write_flush();
@@ -176,7 +176,7 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
 void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
 {
   char tempbuf[256];
-  int count = sprintf(tempbuf, "[%u] HID Interface instance = %d is unmounted\r\n", dev_addr, instance);
+  int count = sprintf(tempbuf, "[%u] HID Interface%u is unmounted\r\n", dev_addr, instance);
   tud_cdc_write(tempbuf, count);
   tud_cdc_write_flush();
 }
@@ -194,8 +194,9 @@ static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8
 
 
 // convert hid keycode to ascii and print via usb device CDC (ignore non-printable)
-static void process_kbd_report(hid_keyboard_report_t const *report)
+static void process_kbd_report(uint8_t dev_addr, hid_keyboard_report_t const *report)
 {
+  (void) dev_addr;
   static hid_keyboard_report_t prev_report = { 0, 0, {0} }; // previous report to check key released
   bool flush = false;
 
@@ -237,7 +238,7 @@ static void process_kbd_report(hid_keyboard_report_t const *report)
 }
 
 // send mouse report to usb device CDC
-static void process_mouse_report(hid_mouse_report_t const * report)
+static void process_mouse_report(uint8_t dev_addr, hid_mouse_report_t const * report)
 {
   //------------- button state  -------------//
   //uint8_t button_changed_mask = report->buttons ^ prev_report.buttons;
@@ -246,7 +247,7 @@ static void process_mouse_report(hid_mouse_report_t const * report)
   char r = report->buttons & MOUSE_BUTTON_RIGHT  ? 'R' : '-';
 
   char tempbuf[32];
-  int count = sprintf(tempbuf, "%c%c%c %d %d %d\r\n", l, m, r, report->x, report->y, report->wheel);
+  int count = sprintf(tempbuf, "[%u] %c%c%c %d %d %d\r\n", dev_addr, l, m, r, report->x, report->y, report->wheel);
 
   tud_cdc_write(tempbuf, count);
   tud_cdc_write_flush();
@@ -261,11 +262,11 @@ void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t cons
   switch(itf_protocol)
   {
     case HID_ITF_PROTOCOL_KEYBOARD:
-      process_kbd_report( (hid_keyboard_report_t const*) report );
+      process_kbd_report(dev_addr, (hid_keyboard_report_t const*) report );
     break;
 
     case HID_ITF_PROTOCOL_MOUSE:
-      process_mouse_report( (hid_mouse_report_t const*) report );
+      process_mouse_report(dev_addr, (hid_mouse_report_t const*) report );
     break;
 
     default: break;

From 5766c9ac4ed3525b3223ad0751f871b08a1bb5fb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 19 May 2022 13:44:10 +0700
Subject: [PATCH 1013/2085] rename tud_audio_sof_isr() to
 tud_audio_feedback_interval_isr()

- also add interval_log2 to isr callback
- also rename other variables
---
 src/class/audio/audio_device.c | 37 +++++++++++++++++-----------------
 src/class/audio/audio_device.h |  4 +++-
 2 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index a81ddc53e..db8bbb819 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -326,8 +326,8 @@ typedef struct
 
   float fb_float_val;
 
-  uint32_t fb_param_factor_N;
-  uint32_t fb_param_factor_D;
+  uint32_t fb_sample_freq;
+  uint32_t fb_mclk_freq;
 
 #endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -1686,11 +1686,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
           if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1)   // Check if usage is explicit data feedback
           {
             audio->ep_fb = ep_addr;
-            audio->fb_n_frames = 1 << (desc_ep->bInterval -1);
+            audio->fb_n_frames = 1U << (desc_ep->bInterval -1); // TODO correctly set USB frame interval for SOF (not micro-frame)
             audio->fb_n_frames_shift = desc_ep->bInterval -1;
 
             // Enable SOF interrupt if callback is implemented
-            if (tud_audio_sof_isr) usbd_sof_enable(rhport, true);
+            if (tud_audio_feedback_interval_isr) usbd_sof_enable(rhport, true);
 
             //            // Invoke callback after ep_out is set
             //            if (audio->ep_out != 0)
@@ -2050,7 +2050,7 @@ uint8_t tud_audio_n_get_fb_n_frames(uint8_t func_id)
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
-static bool set_fb_params(audiod_function_t* audio, uint32_t f_s, uint32_t f_m)
+static bool set_fb_params(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq)
 {
   // Check if frame interval is within sane limits
   // The interval value audio->fb_n_frames was taken from the descriptors within audiod_set_interface()
@@ -2058,29 +2058,29 @@ static bool set_fb_params(audiod_function_t* audio, uint32_t f_s, uint32_t f_m)
   // n_frames_min is ceil(2^10 * f_s / f_m) for full speed and ceil(2^13 * f_s / f_m) for high speed
   // this lower limit ensures the measures feedback value has sufficient precision
   uint32_t const k = (TUSB_SPEED_FULL == tud_speed_get()) ? 10 : 13;
-  if ( (((1UL << k) * f_s / f_m) + 1) > audio->fb_n_frames )
+  if ( (((1UL << k) * sample_freq / mclk_freq) + 1) > audio->fb_n_frames )
   {
     TU_LOG1("  UAC2 feedback interval too small\r\n"); TU_BREAKPOINT(); return false;
   }
 
   // Check if parameters really allow for a power of two division
-  if ((f_m % f_s) == 0 && tu_is_power_of_two(f_m / f_s))
+  if ((mclk_freq % sample_freq) == 0 && tu_is_power_of_two(mclk_freq / sample_freq))
   {
     audio->fb_compute_method = FEEDBACK_COMPUTE_POWER_OF_2;
-    audio->fb_power_of_two_val = 16 - audio->fb_n_frames_shift - tu_log2(f_m / f_s);
+    audio->fb_power_of_two_val = 16 - audio->fb_n_frames_shift - tu_log2(mclk_freq / sample_freq);
   }else if ( audio->fb_compute_method == FEEDBACK_COMPUTE_FLOAT)
   {
-    audio->fb_float_val = (float)f_s / f_m * (1UL << (16 - audio->fb_n_frames_shift));
+    audio->fb_float_val = (float)sample_freq / mclk_freq * (1UL << (16 - audio->fb_n_frames_shift));
   }else
   {
-    audio->fb_param_factor_N = f_s;
-    audio->fb_param_factor_D = f_m;
+    audio->fb_sample_freq = sample_freq;
+    audio->fb_mclk_freq = mclk_freq;
   }
 
   // Minimal/Maximum value in 16.16 format for full speed (1ms per frame) or high speed (125 us per frame)
   uint32_t const frame_div = (TUSB_SPEED_FULL == tud_speed_get()) ? 1000 : 8000;
-  audio->fb_val_min = (f_s/frame_div - 1) << 16;
-  audio->fb_val_max = (f_s/frame_div + 1) << 16;
+  audio->fb_val_min = (sample_freq/frame_div - 1) << 16;
+  audio->fb_val_max = (sample_freq/frame_div + 1) << 16;
 
   return true;
 }
@@ -2093,7 +2093,7 @@ uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
   switch (audio->fb_compute_method)
   {
     case FEEDBACK_COMPUTE_POWER_OF_2:
-      feedback = cycles << audio->fb_power_of_two_val;
+      feedback = (cycles << audio->fb_power_of_two_val);
     break;
 
     case FEEDBACK_COMPUTE_FLOAT:
@@ -2102,8 +2102,8 @@ uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
 
     case FEEDBACK_COMPUTE_FIXED:
     {
-      uint64_t fb64 = (((uint64_t) cycles) * audio->fb_param_factor_N) << (16 - audio->fb_n_frames_shift);
-      feedback = (uint32_t) (fb64 / audio->fb_param_factor_D);
+      uint64_t fb64 = (((uint64_t) cycles) * audio->fb_sample_freq) << (16 - audio->fb_n_frames_shift);
+      feedback = (uint32_t) (fb64 / audio->fb_mclk_freq);
     }
     break;
 
@@ -2142,10 +2142,11 @@ void audiod_sof_isr (uint8_t rhport, uint32_t frame_count)
 
     if (audio->ep_fb != 0)
     {
-      uint32_t const interval = (1UL << audio->fb_n_frames);
+      // TODO hs need to be adjusted to frame (SOF event is not generated for micro-frame)
+      uint32_t const interval = (1UL << audio->fb_n_frames_shift);
       if ( 0 == (frame_count & (interval-1)) )
       {
-        if(tud_audio_sof_isr) tud_audio_sof_isr(i, frame_count);
+        if(tud_audio_feedback_interval_isr) tud_audio_feedback_interval_isr(i, frame_count, audio->fb_n_frames_shift);
       }
     }
   }
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 22394aaca..e6d3b74e6 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -503,7 +503,9 @@ uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles);
 // fixed_point : 0 float (default), 1 fixed point (for mcu without FPU)
 TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, uint32_t* sample_freq, uint32_t* mclk_freq, uint8_t* fixed_point);
 
-TU_ATTR_WEAK void tud_audio_sof_isr(uint8_t func_id, uint32_t frame);
+// Callback in ISR context, invoked periodically according to feedback endpoint bInterval.
+// Could be used to compute and update feedback value
+TU_ATTR_WEAK void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_log2);
 
 
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN

From e5113a1cfc25c0e5e7e75c2644ed91d252391c28 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 19 May 2022 16:05:55 +0700
Subject: [PATCH 1014/2085] prototype for feedback method

---
 src/class/audio/audio_device.c | 21 +++++++--------------
 src/class/audio/audio_device.h | 28 ++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+), 14 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index db8bbb819..1dce6a664 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -261,13 +261,6 @@ osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
 #endif
 #endif
 
-enum {
-  FEEDBACK_COMPUTE_DISABLED,
-  FEEDBACK_COMPUTE_FLOAT,
-  FEEDBACK_COMPUTE_FIXED,
-  FEEDBACK_COMPUTE_POWER_OF_2,
-};
-
 typedef struct
 {
   uint8_t rhport;
@@ -1722,10 +1715,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
         if ( sample_freq == 0 || mclk_freq == 0 )
         {
-          audio->fb_compute_method = FEEDBACK_COMPUTE_DISABLED;
+          audio->fb_compute_method = AUDIO_FEEDBACK_METHOD_DISABLED;
         }else
         {
-          audio->fb_compute_method = fixed_point ? FEEDBACK_COMPUTE_FIXED : FEEDBACK_COMPUTE_FLOAT;
+          audio->fb_compute_method = fixed_point ? AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED : AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT;
           set_fb_params(audio, sample_freq, mclk_freq);
         }
       }
@@ -2066,9 +2059,9 @@ static bool set_fb_params(audiod_function_t* audio, uint32_t sample_freq, uint32
   // Check if parameters really allow for a power of two division
   if ((mclk_freq % sample_freq) == 0 && tu_is_power_of_two(mclk_freq / sample_freq))
   {
-    audio->fb_compute_method = FEEDBACK_COMPUTE_POWER_OF_2;
+    audio->fb_compute_method = AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2;
     audio->fb_power_of_two_val = 16 - audio->fb_n_frames_shift - tu_log2(mclk_freq / sample_freq);
-  }else if ( audio->fb_compute_method == FEEDBACK_COMPUTE_FLOAT)
+  }else if ( audio->fb_compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT)
   {
     audio->fb_float_val = (float)sample_freq / mclk_freq * (1UL << (16 - audio->fb_n_frames_shift));
   }else
@@ -2092,15 +2085,15 @@ uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
 
   switch (audio->fb_compute_method)
   {
-    case FEEDBACK_COMPUTE_POWER_OF_2:
+    case AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2:
       feedback = (cycles << audio->fb_power_of_two_val);
     break;
 
-    case FEEDBACK_COMPUTE_FLOAT:
+    case AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT:
       feedback = (uint32_t) ((float) cylces * audio->fb_float_val);
     break;
 
-    case FEEDBACK_COMPUTE_FIXED:
+    case AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED:
     {
       uint64_t fb64 = (((uint64_t) cycles) * audio->fb_sample_freq) << (16 - audio->fb_n_frames_shift);
       feedback = (uint32_t) (fb64 / audio->fb_mclk_freq);
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index e6d3b74e6..da4a45eee 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -498,6 +498,34 @@ static inline uint8_t tud_audio_get_fb_n_frames();
 // return feedback value in 16.16 for reference (0 for error)
 uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles);
 
+enum {
+  AUDIO_FEEDBACK_METHOD_DISABLED,
+  AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED,
+  AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT,
+  AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2,
+  AUDIO_FEEDBACK_METHOD_FIFO_COUNT_FIXED,
+  AUDIO_FEEDBACK_METHOD_FIFO_COUNT_FLOAT
+};
+
+typedef struct {
+  uint8_t method;
+  union {
+    struct {
+        uint32_t sample_freq;
+        uint32_t mclk_freq;
+    }frequency;
+
+    struct {
+        uint32_t nominal;
+        uint32_t threshold;
+        // variation etc ..
+    }fifo_count;
+  };
+}audio_feedback_params_t;
+
+
+// TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param);
+
 // mclk_freq   : Main clock frequency in Hz i.e. master clock to which sample clock is locked
 // sample_freq : sample frequency in Hz
 // fixed_point : 0 float (default), 1 fixed point (for mcu without FPU)

From 26c4d4b328ca93d0db5d8d7842a315cbde4d9f5a Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Fri, 20 May 2022 17:25:30 -0500
Subject: [PATCH 1015/2085] Minor cleanup of RP2040 code post addition of
 Pico-PIO_USB

* Removed some compiler warnings, and cleaned out unnecessary warning suppression from CMake suppress_tinyusb_warnings()
* Made explicit family_configure_dual_usb_example() for DUAL mode examples as family_configure_target() may not generally be called multiple times for the same target

* Renamed library pico_pio_usb to tinyusb_picio_pio_usb to be clearer and avoid conflict if someone already has a pico_pio_usb in their project
* Added family_add_pico_pio_usb() method for adding Pico-PIO_SUB support to an existing example
* Allowed tinyusb_pico_pio_usb to be added to regular apps using the Pico SDK
---
 .../device/net_lwip_webserver/src/lwipopts.h  |   2 +
 examples/dual/CMakeLists.txt                  |  12 ++
 .../host_hid_to_device_cdc/CMakeLists.txt     |   4 +-
 examples/host/bare_api/CMakeLists.txt         |   2 +-
 examples/host/cdc_msc_hid/CMakeLists.txt      |   2 +-
 examples/host/hid_controller/CMakeLists.txt   |   2 +-
 hw/bsp/rp2040/family.c                        |   2 +
 hw/bsp/rp2040/family.cmake                    | 154 +++++++++---------
 src/portable/raspberrypi/rp2040/hcd_rp2040.c  |   4 +
 src/portable/raspberrypi/rp2040/rp2040_usb.c  |   2 +-
 10 files changed, 106 insertions(+), 80 deletions(-)
 create mode 100644 examples/dual/CMakeLists.txt

diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h
index a215017c7..639619f63 100644
--- a/examples/device/net_lwip_webserver/src/lwipopts.h
+++ b/examples/device/net_lwip_webserver/src/lwipopts.h
@@ -49,7 +49,9 @@
 
 #define TCP_MSS                         (1500 /*mtu*/ - 20 /*iphdr*/ - 20 /*tcphhr*/)
 #define TCP_SND_BUF                     (2 * TCP_MSS)
+#ifndef TCP_WND
 #define TCP_WND                         (TCP_MSS)
+#endif
 
 #define ETHARP_SUPPORT_STATIC_ENTRIES   1
 
diff --git a/examples/dual/CMakeLists.txt b/examples/dual/CMakeLists.txt
new file mode 100644
index 000000000..d2f9a42f0
--- /dev/null
+++ b/examples/dual/CMakeLists.txt
@@ -0,0 +1,12 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
+
+project(tinyusb_dual_examples)
+family_initialize_project(tinyusb_dual_examples ${CMAKE_CURRENT_LIST_DIR})
+if (FAMILY STREQUAL "rp2040" AND NOT TARGET tinyusb_pico_pio_usb)
+    message("Skipping dual host/device mode examples as Pico-PIO-USB is not available")
+else()
+    # family_add_subdirectory will filter what to actually add based on selected FAMILY
+    family_add_subdirectory(host_hid_to_device_cdc)
+endif()
diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index 24ebfdec3..ea4e087e3 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -25,6 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
-family_configure_host_example(${PROJECT})
-family_configure_pico_pio_usb_example(${PROJECT})
+family_configure_dual_usb_example(${PROJECT})
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 607ef22eb..bc04b01a7 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -27,4 +27,4 @@ target_include_directories(${PROJECT} PUBLIC
 family_configure_host_example(${PROJECT})
 
 # For rp2040, un-comment to enable pico-pio-usb
-# family_configure_pico_pio_usb_example(${PROJECT})
+# family_add_pico_pio_usb(${PROJECT})
\ No newline at end of file
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 214e9f2e7..c4a4d8e63 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -29,4 +29,4 @@ target_include_directories(${PROJECT} PUBLIC
 family_configure_host_example(${PROJECT})
 
 # For rp2040, un-comment to enable pico-pio-usb
-# family_configure_pico_pio_usb_example(${PROJECT})
+# family_add_pico_pio_usb(${PROJECT})
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index 6227e0790..6153d399a 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -28,4 +28,4 @@ target_include_directories(${PROJECT} PUBLIC
 family_configure_host_example(${PROJECT})
 
 # For rp2040, un-comment to enable pico-pio-usb
-# family_configure_pico_pio_usb_example(${PROJECT})
+# family_add_pico_pio_usb(${PROJECT})
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index dcf38b6ec..8de1c1aab 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -127,8 +127,10 @@ void board_init(void)
 #ifndef BUTTON_BOOTSEL
 #endif
 
+#if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
   // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb
   set_sys_clock_khz(120000, true);
+#endif
 
 #if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
   bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_TX_PIN, GPIO_FUNC_UART));
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 17ae3de9b..df3a6a91e 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -23,7 +23,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		set(PICO_TINYUSB_PATH ${TOP})
 	endif()
 
-  #------------------------------------
+	#------------------------------------
 	# Base config for both device and host; wrapped by SDK's tinyusb_common
 	#------------------------------------
 	add_library(tinyusb_common_base INTERFACE)
@@ -50,7 +50,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	if (CMAKE_BUILD_TYPE STREQUAL "Debug")
 		message("Compiling TinyUSB with CFG_TUSB_DEBUG=1")
 		set(TINYUSB_DEBUG_LEVEL 1)
-	endif ()
+	endif()
 	
 	target_compile_definitions(tinyusb_common_base INTERFACE
 			CFG_TUSB_MCU=OPT_MCU_RP2040
@@ -58,44 +58,13 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
 	)
 
-  #------------------------------------
-  # PIO USB for both host and device
-  #------------------------------------
-  add_library(pico_pio_usb INTERFACE)
-
-  if (NOT DEFINED PICO_PIO_USB_PATH)
-    set(PICO_PIO_USB_PATH "${TOP}/hw/mcu/raspberry_pi/Pico-PIO-USB")
-  endif()
-
-	target_sources(pico_pio_usb INTERFACE
-			${PICO_PIO_USB_PATH}/src/pio_usb.c
-			${PICO_PIO_USB_PATH}/src/pio_usb_host.c
-			${PICO_PIO_USB_PATH}/src/pio_usb_device.c
-			${PICO_PIO_USB_PATH}/src/usb_crc.c
-			)
-
-	target_include_directories(pico_pio_usb INTERFACE
-			${PICO_PIO_USB_PATH}/src
-			)
-
-	target_link_libraries(pico_pio_usb INTERFACE
-	    hardware_dma
-	    hardware_pio
-	    pico_multicore
-			)
-
-	target_compile_definitions(pico_pio_usb INTERFACE
-			PIO_USB_USE_TINYUSB
-	)
-
-  #------------------------------------
+	#------------------------------------
 	# Base config for device mode; wrapped by SDK's tinyusb_device
 	#------------------------------------
 	add_library(tinyusb_device_base INTERFACE)
 	target_sources(tinyusb_device_base INTERFACE
 			${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c
 			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
-		  ${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
 			${TOP}/src/device/usbd.c
 			${TOP}/src/device/usbd_control.c
 			${TOP}/src/class/audio/audio_device.c
@@ -119,7 +88,6 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	target_sources(tinyusb_host_base INTERFACE
 			${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
 			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
-		  ${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
 			${TOP}/src/host/usbh.c
 			${TOP}/src/host/hub.c
 			${TOP}/src/class/cdc/cdc_host.c
@@ -140,8 +108,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	target_sources(tinyusb_bsp INTERFACE
 			${TOP}/hw/bsp/rp2040/family.c
 			)
-#	target_include_directories(tinyusb_bsp INTERFACE
-#			${TOP}/hw/bsp/rp2040)
+	#	target_include_directories(tinyusb_bsp INTERFACE
+	#			${TOP}/hw/bsp/rp2040)
 
 	# tinyusb_additions will hold our extra settings for examples
 	add_library(tinyusb_additions INTERFACE)
@@ -151,22 +119,22 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	)
 
 	if(DEFINED LOG)
-	  target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG} )
+		target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG})
 	endif()
 
 	if(LOGGER STREQUAL "rtt")
-	  target_compile_definitions(tinyusb_additions INTERFACE
-		LOGGER_RTT
-		SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
-	  )
+		target_compile_definitions(tinyusb_additions INTERFACE
+				LOGGER_RTT
+				SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
+		)
 
-	  target_sources(tinyusb_additions INTERFACE
-		${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
-	  )
+		target_sources(tinyusb_additions INTERFACE
+				${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+		)
 
-	  target_include_directories(tinyusb_additions INTERFACE
-		${TOP}/lib/SEGGER_RTT/RTT
-	  )
+		target_include_directories(tinyusb_additions INTERFACE
+				${TOP}/lib/SEGGER_RTT/RTT
+		)
 	endif()
 
 	#------------------------------------
@@ -189,41 +157,81 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
 	endfunction()
 
-	function(family_configure_pico_pio_usb_example TARGET)
-		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_pio_usb)
-    pico_generate_pio_header(tinyusb_common_base ${PICO_PIO_USB_PATH}/src/usb_tx.pio)
-    pico_generate_pio_header(tinyusb_common_base ${PICO_PIO_USB_PATH}/src/usb_rx.pio)
+	function(family_add_pico_pio_usb TARGET)
+		target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb)
 	endfunction()
 
+	function(family_configure_dual_usb_example TARGET)
+		family_configure_target(${TARGET})
+		# require tinyusb_pico_pio_usb
+		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb )
+	endfunction()
+
+	function(check_and_add_pico_pio_usb_support)
+		# check for pico_generate_pio_header (as depending on environment we may be called before SDK is
+		# initialized in which case it isn't available yet), and only do the initialization once
+		if (COMMAND pico_generate_pio_header AND NOT TARGET tinyusb_pico_pio_usb)
+			#------------------------------------
+			# PIO USB for both host and device
+			#------------------------------------
+
+			if (NOT DEFINED PICO_PIO_USB_PATH)
+				set(PICO_PIO_USB_PATH "${TOP}/hw/mcu/raspberry_pi/Pico-PIO-USB")
+			endif()
+
+			if (EXISTS ${PICO_PIO_USB_PATH}/src/pio_usb.c)
+				add_library(tinyusb_pico_pio_usb INTERFACE)
+				target_sources(tinyusb_device_base INTERFACE
+						${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+						)
+				target_sources(tinyusb_host_base INTERFACE
+						${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+						)
+
+				target_sources(tinyusb_pico_pio_usb INTERFACE
+						${PICO_PIO_USB_PATH}/src/pio_usb.c
+						${PICO_PIO_USB_PATH}/src/pio_usb_host.c
+						${PICO_PIO_USB_PATH}/src/pio_usb_device.c
+						${PICO_PIO_USB_PATH}/src/usb_crc.c
+						)
+
+				target_include_directories(tinyusb_pico_pio_usb INTERFACE
+						${PICO_PIO_USB_PATH}/src
+						)
+
+				target_link_libraries(tinyusb_pico_pio_usb INTERFACE
+						hardware_dma
+						hardware_pio
+						pico_multicore
+						)
+
+				target_compile_definitions(tinyusb_pico_pio_usb INTERFACE
+						PIO_USB_USE_TINYUSB
+						)
+
+				pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_tx.pio)
+				pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_rx.pio)
+			endif()
+		endif()
+	endfunction()
+
+	# Try to add Pico-PIO_USB support now for the case where this file is included directly
+	# after Pico SDK initialization, but without using the family_ functions (as is the case
+	# when included by the SDK itself)
+	check_and_add_pico_pio_usb_support()
+
 	function(family_initialize_project PROJECT DIR)
 		# call the original version of this function from family_common.cmake
 		_family_initialize_project(${PROJECT} ${DIR})
 		enable_language(C CXX ASM)
 		pico_sdk_init()
+
+		# now re-check for adding Pico-PIO_USB support now SDK is definitely available
+		check_and_add_pico_pio_usb_support()
 	endfunction()
 
 	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
 	function(suppress_tinyusb_warnings)
-		set_source_files_properties(
-				${PICO_TINYUSB_PATH}/src/tusb.c
-				PROPERTIES
-				COMPILE_FLAGS "-Wno-conversion")
-		set_source_files_properties(
-				${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
-				PROPERTIES
-				COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual")
-		set_source_files_properties(
-				${PICO_TINYUSB_PATH}/src/device/usbd.c
-				PROPERTIES
-				COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-null-dereference")
-		set_source_files_properties(
-				${PICO_TINYUSB_PATH}/src/device/usbd_control.c
-				PROPERTIES
-				COMPILE_FLAGS "-Wno-conversion")
-		set_source_files_properties(
-				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
-				PROPERTIES
-				COMPILE_FLAGS "-Wno-conversion")
+		# there are currently no warnings to suppress, however this function must still exist
 	endfunction()
 endif()
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 5164035aa..54c27ffe3 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -537,7 +537,11 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
     (void) rhport;
 
     // Copy data into setup packet buffer
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Warray-bounds"
+#pragma GCC diagnostic ignored "-Wstringop-overflow"
     memcpy((void*)&usbh_dpram->setup_packet[0], setup_packet, 8);
+#pragma GCC diagnostic pop
 
     // Configure EP0 struct with setup info for the trans complete
     struct hw_endpoint *ep = _hw_endpoint_allocate(0);
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 9c3e5d011..c93199fd0 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -58,9 +58,9 @@ void rp2040_usb_init(void)
   unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
 
   // Clear any previous state just in case
-  // TODO Suppress warning array-bounds with gcc11
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Warray-bounds"
+#pragma GCC diagnostic ignored "-Wstringop-overflow"
   memset(usb_hw, 0, sizeof(*usb_hw));
   memset(usb_dpram, 0, sizeof(*usb_dpram));
 #pragma GCC diagnostic pop

From 16c0eb0d2f2e2afe551d7bd239cb8092df7b2128 Mon Sep 17 00:00:00 2001
From: Sven <sknebel@users.noreply.github.com>
Date: Tue, 24 May 2022 21:45:35 +0200
Subject: [PATCH 1016/2085] fix links in docs

changed markdown formatting to rst formatting
---
 docs/reference/index.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/reference/index.rst b/docs/reference/index.rst
index fcff03590..292fb1a93 100644
--- a/docs/reference/index.rst
+++ b/docs/reference/index.rst
@@ -25,7 +25,7 @@ Supports multiple device configurations by dynamically changing usb descriptors.
 -  Vendor-specific class support with generic In & Out endpoints. Can be used with MS OS 2.0 compatible descriptor to load winUSB driver without INF file.
 -  `WebUSB <https://github.com/WICG/webusb>`__ with vendor-specific class
 
-If you have special need, `usbd_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. Here is how RPi team add their reset interface [raspberrypi/pico-sdk#197](https://github.com/raspberrypi/pico-sdk/pull/197)
+If you have special need, `usbd_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. Here is how RPi team add their reset interface `raspberrypi/pico-sdk#197 <https://github.com/raspberrypi/pico-sdk/pull/197>`__
 
 Host Stack
 ==========
@@ -41,7 +41,7 @@ TinyUSB is completely thread-safe by pushing all ISR events into a central queue
 
 - **No OS**
 - **FreeRTOS**
-- **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its [own repo](https://github.com/hathach/mynewt-tinyusb-example)
+- **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its `own repo <https://github.com/hathach/mynewt-tinyusb-example>`__
 
 License
 =======

From 15aa593790311d6e279f01ba764a1a96d282a78b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 May 2022 12:27:31 +0700
Subject: [PATCH 1017/2085] wrap feedback and compute to its own struct/union

---
 src/class/audio/audio_device.c | 132 +++++++++++++++++----------------
 src/class/audio/audio_device.h |  28 ++-----
 2 files changed, 78 insertions(+), 82 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 1dce6a664..e967e8c3f 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -306,21 +306,29 @@ typedef struct
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
-  uint32_t fb_val;                      // Feedback value for asynchronous mode (in 16.16 format).
-  uint8_t fb_n_frames;                  // Number of (micro)frames used to estimate feedback value
-  uint8_t fb_n_frames_shift;
-  uint8_t fb_compute_method;
+  struct {
+    uint32_t value;     // Feedback value for asynchronous mode (in 16.16 format).
+    uint32_t min_value; // min value according to UAC2 FMT-2.0 section 2.3.1.1.
+    uint32_t max_value; // max value according to UAC2 FMT-2.0 section 2.3.1.1.
 
-  uint32_t fb_val_min;                  // Maximum allowed feedback value according to UAC2 FMT-2.0 section 2.3.1.1.
-  uint32_t fb_val_max;                  // Maximum allowed feedback value according to UAC2 FMT-2.0 section 2.3.1.1.
+    uint8_t frame_shift; // bInterval-1 in unit of frame (FS), micro-frame (HS)
+    uint8_t compute_method;
 
-  // should be union
-  uint8_t fb_power_of_two_val;
+    union {
+      uint8_t power_of_2; // pre-computed power of 2 shift
+      float float_const;  // pre-computed float constant
 
-  float fb_float_val;
+      struct {
+        uint32_t sample_freq;
+        uint32_t mclk_freq;
+      }fixed;
 
-  uint32_t fb_sample_freq;
-  uint32_t fb_mclk_freq;
+//      struct {
+//
+//      }fifo_count;
+    }compute;
+
+  } feedback;
 
 #endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -437,10 +445,6 @@ static inline uint8_t tu_desc_subtype(void const* desc)
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
-#endif
-
 bool tud_audio_n_mounted(uint8_t func_id)
 {
   TU_VERIFY(func_id < CFG_TUD_AUDIO);
@@ -1059,7 +1063,7 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 static inline bool audiod_fb_send(uint8_t rhport, audiod_function_t *audio)
 {
-  return usbd_edpt_xfer(rhport, audio->ep_fb, (uint8_t *) &audio->fb_val, 4);
+  return usbd_edpt_xfer(rhport, audio->ep_fb, (uint8_t *) &audio->feedback.value, 4);
 }
 #endif
 
@@ -1564,8 +1568,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
     usbd_edpt_close(rhport, audio->ep_fb);
     audio->ep_fb = 0;
-    audio->fb_n_frames = 0;
-
+    tu_memclr(&audio->feedback, sizeof(audio->feedback));
 #endif
   }
 #endif
@@ -1679,8 +1682,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
           if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1)   // Check if usage is explicit data feedback
           {
             audio->ep_fb = ep_addr;
-            audio->fb_n_frames = 1U << (desc_ep->bInterval -1); // TODO correctly set USB frame interval for SOF (not micro-frame)
-            audio->fb_n_frames_shift = desc_ep->bInterval -1;
+            audio->feedback.frame_shift = desc_ep->bInterval -1;
 
             // Enable SOF interrupt if callback is implemented
             if (tud_audio_feedback_interval_isr) usbd_sof_enable(rhport, true);
@@ -1708,18 +1710,26 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
       // Prepare feedback computation if callback is available
       if (tud_audio_feedback_params_cb)
       {
-        uint32_t sample_freq = 0;
-        uint32_t mclk_freq = 0;
-        uint8_t fixed_point = 0;
-        tud_audio_feedback_params_cb(func_id, alt, &sample_freq, &mclk_freq, &fixed_point);
+        audio_feedback_params_t fb_param;
 
-        if ( sample_freq == 0 || mclk_freq == 0 )
+        tud_audio_feedback_params_cb(func_id, alt, &fb_param);
+        audio->feedback.compute_method = fb_param.method;
+
+        switch(fb_param.method)
         {
-          audio->fb_compute_method = AUDIO_FEEDBACK_METHOD_DISABLED;
-        }else
-        {
-          audio->fb_compute_method = fixed_point ? AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED : AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT;
-          set_fb_params(audio, sample_freq, mclk_freq);
+          case AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED:
+          case AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT:
+          case AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2:
+            set_fb_params_freq(audio, fb_param.frequency.sample_freq, fb_param.frequency.mclk_freq);
+          break;
+
+          case AUDIO_FEEDBACK_METHOD_FIFO_COUNT_FIXED:
+          case AUDIO_FEEDBACK_METHOD_FIFO_COUNT_FLOAT:
+            // TODO feedback by fifo count
+          break;
+
+          // nothing to do
+          default: break;
         }
       }
 #endif
@@ -2035,23 +2045,18 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 }
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-uint8_t tud_audio_n_get_fb_n_frames(uint8_t func_id)
-{
-  return _audiod_fct[func_id].fb_n_frames;
-}
-#endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-
-static bool set_fb_params(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq)
+static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq)
 {
   // Check if frame interval is within sane limits
-  // The interval value audio->fb_n_frames was taken from the descriptors within audiod_set_interface()
+  // The interval value n_frames was taken from the descriptors within audiod_set_interface()
 
   // n_frames_min is ceil(2^10 * f_s / f_m) for full speed and ceil(2^13 * f_s / f_m) for high speed
   // this lower limit ensures the measures feedback value has sufficient precision
   uint32_t const k = (TUSB_SPEED_FULL == tud_speed_get()) ? 10 : 13;
-  if ( (((1UL << k) * sample_freq / mclk_freq) + 1) > audio->fb_n_frames )
+  uint32_t const n_frame = (1UL << audio->feedback.frame_shift);
+
+  if ( (((1UL << k) * sample_freq / mclk_freq) + 1) > n_frame )
   {
     TU_LOG1("  UAC2 feedback interval too small\r\n"); TU_BREAKPOINT(); return false;
   }
@@ -2059,21 +2064,23 @@ static bool set_fb_params(audiod_function_t* audio, uint32_t sample_freq, uint32
   // Check if parameters really allow for a power of two division
   if ((mclk_freq % sample_freq) == 0 && tu_is_power_of_two(mclk_freq / sample_freq))
   {
-    audio->fb_compute_method = AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2;
-    audio->fb_power_of_two_val = 16 - audio->fb_n_frames_shift - tu_log2(mclk_freq / sample_freq);
-  }else if ( audio->fb_compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT)
+    audio->feedback.compute_method     = AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2;
+    audio->feedback.compute.power_of_2 = 16 - audio->feedback.frame_shift - tu_log2(mclk_freq / sample_freq);
+  }
+  else if ( audio->feedback.compute_method == AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT)
   {
-    audio->fb_float_val = (float)sample_freq / mclk_freq * (1UL << (16 - audio->fb_n_frames_shift));
-  }else
+    audio->feedback.compute.float_const = (float)sample_freq / mclk_freq * (1UL << (16 - audio->feedback.frame_shift));
+  }
+  else
   {
-    audio->fb_sample_freq = sample_freq;
-    audio->fb_mclk_freq = mclk_freq;
+    audio->feedback.compute.fixed.sample_freq = sample_freq;
+    audio->feedback.compute.fixed.mclk_freq = mclk_freq;
   }
 
   // Minimal/Maximum value in 16.16 format for full speed (1ms per frame) or high speed (125 us per frame)
-  uint32_t const frame_div = (TUSB_SPEED_FULL == tud_speed_get()) ? 1000 : 8000;
-  audio->fb_val_min = (sample_freq/frame_div - 1) << 16;
-  audio->fb_val_max = (sample_freq/frame_div + 1) << 16;
+  uint32_t const frame_div  = (TUSB_SPEED_FULL == tud_speed_get()) ? 1000 : 8000;
+  audio->feedback.min_value = (sample_freq/frame_div - 1) << 16;
+  audio->feedback.max_value = (sample_freq/frame_div + 1) << 16;
 
   return true;
 }
@@ -2083,20 +2090,20 @@ uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
   audiod_function_t* audio = &_audiod_fct[func_id];
   uint32_t feedback;
 
-  switch (audio->fb_compute_method)
+  switch (audio->feedback.compute_method)
   {
     case AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2:
-      feedback = (cycles << audio->fb_power_of_two_val);
+      feedback = (cycles << audio->feedback.compute.power_of_2);
     break;
 
     case AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT:
-      feedback = (uint32_t) ((float) cylces * audio->fb_float_val);
+      feedback = (uint32_t) ((float) cycles * audio->feedback.compute.float_const);
     break;
 
     case AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED:
     {
-      uint64_t fb64 = (((uint64_t) cycles) * audio->fb_sample_freq) << (16 - audio->fb_n_frames_shift);
-      feedback = (uint32_t) (fb64 / audio->fb_mclk_freq);
+      uint64_t fb64 = (((uint64_t) cycles) * audio->feedback.compute.fixed.sample_freq) << (16 - audio->feedback.frame_shift);
+      feedback = (uint32_t) (fb64 / audio->feedback.compute.fixed.mclk_freq);
     }
     break;
 
@@ -2107,8 +2114,8 @@ uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
   // The size of isochronous packets created by the device must be within the limits specified in FMT-2.0 section 2.3.1.1.
   // This means that the deviation of actual packet size from nominal size must not exceed +/- one audio slot
   // (audio slot = channel count samples).
-  if ( feedback > audio->fb_val_max ) feedback = audio->fb_val_max;
-  if ( feedback < audio->fb_val_min ) feedback = audio->fb_val_min;
+  if ( feedback > audio->feedback.max_value ) feedback = audio->feedback.max_value;
+  if ( feedback < audio->feedback.min_value ) feedback = audio->feedback.min_value;
 
   tud_audio_n_fb_set(func_id, feedback);
 
@@ -2135,11 +2142,12 @@ void audiod_sof_isr (uint8_t rhport, uint32_t frame_count)
 
     if (audio->ep_fb != 0)
     {
-      // TODO hs need to be adjusted to frame (SOF event is not generated for micro-frame)
-      uint32_t const interval = (1UL << audio->fb_n_frames_shift);
+      // HS shift need to be adjusted since SOF event is generated for frame only
+      uint8_t const hs_adjust = (TUSB_SPEED_HIGH == tud_speed_get()) ? 3 : 0;
+      uint32_t const interval = 1UL << (audio->feedback.frame_shift - hs_adjust);
       if ( 0 == (frame_count & (interval-1)) )
       {
-        if(tud_audio_feedback_interval_isr) tud_audio_feedback_interval_isr(i, frame_count, audio->fb_n_frames_shift);
+        if(tud_audio_feedback_interval_isr) tud_audio_feedback_interval_isr(i, frame_count, audio->feedback.frame_shift);
       }
     }
   }
@@ -2431,7 +2439,7 @@ bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION
   if ( TUSB_SPEED_FULL == tud_speed_get() )
   {
-    uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].fb_val;
+    uint8_t * fb = (uint8_t *) &_audiod_fct[func_id].feedback.value;
 
     // For FS format is 10.14
     *(fb++) = (feedback >> 2) & 0xFF;
@@ -2443,7 +2451,7 @@ bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
 #else
   {
     // Send value as-is, caller will choose the appropriate format
-    _audiod_fct[func_id].fb_val = feedback;
+    _audiod_fct[func_id].feedback.value = feedback;
   }
 #endif
 
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index da4a45eee..09de8e9a8 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -487,11 +487,6 @@ TU_ATTR_WEAK void tud_audio_fb_done_cb(uint8_t func_id);
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback);
 static inline bool tud_audio_fb_set(uint32_t feedback);
 
-uint8_t tud_audio_n_get_fb_n_frames(uint8_t func_id);
-static inline uint8_t tud_audio_get_fb_n_frames();
-
-#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-
 // Update feedback value with passed cycles since last time this update function is called.
 // Typically called within tud_audio_sof_isr(). Required tud_audio_feedback_params_cb() is implemented
 // This function will also call tud_audio_feedback_set()
@@ -511,8 +506,8 @@ typedef struct {
   uint8_t method;
   union {
     struct {
-        uint32_t sample_freq;
-        uint32_t mclk_freq;
+        uint32_t sample_freq; //  sample frequency in Hz
+        uint32_t mclk_freq;   // Main clock frequency in Hz i.e. master clock to which sample clock is based on
     }frequency;
 
     struct {
@@ -523,18 +518,16 @@ typedef struct {
   };
 }audio_feedback_params_t;
 
-
-// TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param);
-
-// mclk_freq   : Main clock frequency in Hz i.e. master clock to which sample clock is locked
-// sample_freq : sample frequency in Hz
-// fixed_point : 0 float (default), 1 fixed point (for mcu without FPU)
-TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, uint32_t* sample_freq, uint32_t* mclk_freq, uint8_t* fixed_point);
+// Invoked when needed to set feedback parameters
+TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param);
 
 // Callback in ISR context, invoked periodically according to feedback endpoint bInterval.
 // Could be used to compute and update feedback value
-TU_ATTR_WEAK void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_log2);
+// frame_number  : current SOF count
+// interval_shift: number of bit shift i.e log2(interval) from Feedback endpoint descriptor
+TU_ATTR_WEAK void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift);
 
+#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
 TU_ATTR_WEAK bool tud_audio_int_ctr_done_cb(uint8_t rhport, uint16_t n_bytes_copied);
@@ -682,11 +675,6 @@ static inline bool tud_audio_fb_set(uint32_t feedback)
   return tud_audio_n_fb_set(0, feedback);
 }
 
-static inline uint8_t tud_audio_get_fb_n_frames()
-{
-  return tud_audio_n_get_fb_n_frames(0);
-}
-
 #endif
 
 //--------------------------------------------------------------------+

From f76c7526c950eb7ddd8e8e6ad3f6c95f8785b267 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Fri, 27 May 2022 11:54:28 -0400
Subject: [PATCH 1018/2085] Remove lib/Pico-PIO-USB, which has moved to
 hw/mcu/raspberry_pi/Pico-PIO-USB.

---
 lib/Pico-PIO-USB | 1 -
 1 file changed, 1 deletion(-)
 delete mode 160000 lib/Pico-PIO-USB

diff --git a/lib/Pico-PIO-USB b/lib/Pico-PIO-USB
deleted file mode 160000
index 53ec09168..000000000
--- a/lib/Pico-PIO-USB
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 53ec09168c5a3cd30d8dcb577fa97dc328d769d4

From dce2ad4ffb33fe884429e0c241b1957b3cd6c453 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 27 May 2022 23:11:25 +0700
Subject: [PATCH 1019/2085] adding feedback fifo count (WIP)

---
 src/class/audio/audio_device.c | 47 +++++++++++++++++++---------------
 src/class/audio/audio_device.h |  9 +++----
 2 files changed, 31 insertions(+), 25 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index e967e8c3f..31851e00c 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -323,9 +323,10 @@ typedef struct
         uint32_t mclk_freq;
       }fixed;
 
-//      struct {
-//
-//      }fifo_count;
+      struct {
+        uint32_t nominal_value;
+        uint32_t threshold_bytes;
+      }fifo_count;
     }compute;
 
   } feedback;
@@ -1715,17 +1716,28 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
         tud_audio_feedback_params_cb(func_id, alt, &fb_param);
         audio->feedback.compute_method = fb_param.method;
 
+        // Minimal/Maximum value in 16.16 format for full speed (1ms per frame) or high speed (125 us per frame)
+        uint32_t const frame_div  = (TUSB_SPEED_FULL == tud_speed_get()) ? 1000 : 8000;
+        audio->feedback.min_value = (fb_param.sample_freq/frame_div - 1) << 16;
+        audio->feedback.max_value = (fb_param.sample_freq/frame_div + 1) << 16;
+
         switch(fb_param.method)
         {
           case AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED:
           case AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT:
           case AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2:
-            set_fb_params_freq(audio, fb_param.frequency.sample_freq, fb_param.frequency.mclk_freq);
+            set_fb_params_freq(audio, fb_param.sample_freq, fb_param.frequency.mclk_freq);
           break;
 
           case AUDIO_FEEDBACK_METHOD_FIFO_COUNT_FIXED:
           case AUDIO_FEEDBACK_METHOD_FIFO_COUNT_FLOAT:
-            // TODO feedback by fifo count
+          {
+            uint64_t fb64 = ((uint64_t) fb_param.sample_freq) << 16;
+            audio->feedback.compute.fifo_count.nominal_value = (uint32_t) (fb64 / frame_div);
+            audio->feedback.compute.fifo_count.threshold_bytes = fb_param.fifo_count.threshold_bytes;
+
+            tud_audio_fb_set(audio->feedback.compute.fifo_count.nominal_value);
+          }
           break;
 
           // nothing to do
@@ -1972,14 +1984,14 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
   (void) xferred_bytes;
 
   // Search for interface belonging to given end point address and proceed as required
-  uint8_t func_id;
-  for (func_id = 0; func_id < CFG_TUD_AUDIO; func_id++)
+  for (uint8_t func_id = 0; func_id < CFG_TUD_AUDIO; func_id++)
   {
+    audiod_function_t* audio = &_audiod_fct[func_id];
 
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
 
     // Data transmission of control interrupt finished
-    if (_audiod_fct[func_id].ep_int_ctr == ep_addr)
+    if (audio->ep_int_ctr == ep_addr)
     {
       // According to USB2 specification, maximum payload of interrupt EP is 8 bytes on low speed, 64 bytes on full speed, and 1024 bytes on high speed (but only if an alternate interface other than 0 is used - see specification p. 49)
       // In case there is nothing to send we have to return a NAK - this is taken care of by PHY ???
@@ -1996,7 +2008,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
 
     // Data transmission of audio packet finished
-    if (_audiod_fct[func_id].ep_in == ep_addr && _audiod_fct[func_id].alt_setting != 0)
+    if (audio->ep_in == ep_addr && audio->alt_setting != 0)
     {
       // USB 2.0, section 5.6.4, third paragraph, states "An isochronous endpoint must specify its required bus access period. However, an isochronous endpoint must be prepared to handle poll rates faster than the one specified."
       // That paragraph goes on to say "An isochronous IN endpoint must return a zero-length packet whenever data is requested at a faster interval than the specified interval and data is not available."
@@ -2007,7 +2019,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
       // This is the only place where we can fill something into the EPs buffer!
 
       // Load new data
-      TU_VERIFY(audiod_tx_done_cb(rhport, &_audiod_fct[func_id]));
+      TU_VERIFY(audiod_tx_done_cb(rhport, audio));
 
       // Transmission of ZLP is done by audiod_tx_done_cb()
       return true;
@@ -2017,24 +2029,24 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
 
     // New audio packet received
-    if (_audiod_fct[func_id].ep_out == ep_addr)
+    if (audio->ep_out == ep_addr)
     {
-      TU_VERIFY(audiod_rx_done_cb(rhport, &_audiod_fct[func_id], (uint16_t) xferred_bytes));
+      TU_VERIFY(audiod_rx_done_cb(rhport, audio, (uint16_t) xferred_bytes));
       return true;
     }
 
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
     // Transmission of feedback EP finished
-    if (_audiod_fct[func_id].ep_fb == ep_addr)
+    if (audio->ep_fb == ep_addr)
     {
       if (tud_audio_fb_done_cb) tud_audio_fb_done_cb(func_id);
 
       // Schedule a transmit with the new value if EP is not busy 
-      if (!usbd_edpt_busy(rhport, _audiod_fct[func_id].ep_fb))
+      if (!usbd_edpt_busy(rhport, audio->ep_fb))
       {
         // Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent
-        return audiod_fb_send(rhport, &_audiod_fct[func_id]);
+        return audiod_fb_send(rhport, audio);
       }
     }
 #endif
@@ -2077,11 +2089,6 @@ static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, u
     audio->feedback.compute.fixed.mclk_freq = mclk_freq;
   }
 
-  // Minimal/Maximum value in 16.16 format for full speed (1ms per frame) or high speed (125 us per frame)
-  uint32_t const frame_div  = (TUSB_SPEED_FULL == tud_speed_get()) ? 1000 : 8000;
-  audio->feedback.min_value = (sample_freq/frame_div - 1) << 16;
-  audio->feedback.max_value = (sample_freq/frame_div + 1) << 16;
-
   return true;
 }
 
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 09de8e9a8..c44b4cc30 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -504,16 +504,15 @@ enum {
 
 typedef struct {
   uint8_t method;
+  uint32_t sample_freq;   //  sample frequency in Hz
+
   union {
     struct {
-        uint32_t sample_freq; //  sample frequency in Hz
-        uint32_t mclk_freq;   // Main clock frequency in Hz i.e. master clock to which sample clock is based on
+      uint32_t mclk_freq; // Main clock frequency in Hz i.e. master clock to which sample clock is based on
     }frequency;
 
     struct {
-        uint32_t nominal;
-        uint32_t threshold;
-        // variation etc ..
+      uint32_t threshold_bytes; // minimum number of bytes received to be considered as filled/ready
     }fifo_count;
   };
 }audio_feedback_params_t;

From a87ccee74392922761a0d6379b91ef50098aab01 Mon Sep 17 00:00:00 2001
From: Leon Loeser <info@leon-loeser.de>
Date: Sat, 28 May 2022 19:48:20 +0200
Subject: [PATCH 1020/2085] Fix printf long int compiler error

---
 examples/device/uac2_headset/src/main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 67e287d3e..bbaacd975 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -156,7 +156,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
   {
     if (request->bRequest == AUDIO_CS_REQ_CUR)
     {
-      TU_LOG1("Clock get current freq %u\r\n", current_sample_rate);
+      TU_LOG1("Clock get current freq %lu\r\n", current_sample_rate);
 
       audio_control_cur_4_t curf = { tu_htole32(current_sample_rate) };
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
@@ -205,7 +205,7 @@ static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t
 
     current_sample_rate = ((audio_control_cur_4_t const *)buf)->bCur;
 
-    TU_LOG1("Clock set current freq: %d\r\n", current_sample_rate);
+    TU_LOG1("Clock set current freq: %ld\r\n", current_sample_rate);
 
     return true;
   }

From 688a3a0cc2ba23c671df453257fdf3e601934588 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sun, 29 May 2022 13:58:10 +0930
Subject: [PATCH 1021/2085] Fix non-trivial designated initializers compile
 error

---
 src/host/hcd.h | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 036394c72..5d61dcd88 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -204,13 +204,11 @@ void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred
     .rhport   = 0, // TODO correct rhport
     .event_id = HCD_EVENT_XFER_COMPLETE,
     .dev_addr = dev_addr,
-    .xfer_complete =
-    {
-      .ep_addr = ep_addr,
-      .result  = result,
-      .len     = xferred_bytes
-    }
   };
+  event.xfer_complete.ep_addr = ep_addr;
+  event.xfer_complete.result = result;
+  event.xfer_complete.len = xferred_bytes;
+
 
   hcd_event_handler(&event, in_isr);
 }

From 9e30ec4f160e4816e3c43a0590e6c58832a66cac Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sun, 29 May 2022 13:58:50 +0930
Subject: [PATCH 1022/2085] Hub: Retry port status transfer if failed

---
 src/host/hub.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/host/hub.c b/src/host/hub.c
index 9e546f6f7..5c0fd9166 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -169,7 +169,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
   };
 
   TU_LOG2("HUB Get Port Status: addr = %u port = %u\r\n", hub_addr, hub_port);
-  TU_ASSERT( tuh_control_xfer(&xfer) );
+  TU_VERIFY( tuh_control_xfer(&xfer) );
   return true;
 }
 
@@ -332,7 +332,11 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   {
     if ( tu_bit_test(p_hub->status_change, port) )
     {
-      hub_port_get_status(dev_addr, port, &p_hub->port_status, connection_get_status_complete, 0);
+      if (hub_port_get_status(dev_addr, port, &p_hub->port_status, connection_get_status_complete, 0) == false)
+      {
+        //Hub status control transfer failed, retry
+        hub_edpt_status_xfer(dev_addr);
+      }
       break;
     }
   }

From b7c8cb3c41ba0fc7f9c0db9379d5c65871f6374d Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sun, 29 May 2022 14:00:36 +0930
Subject: [PATCH 1023/2085] Hub: Unplug downstream devices on non-root hub
 disconnect

---
 src/host/usbh.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index e0e41a8d1..af2ad0575 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1107,6 +1107,12 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
     {
       TU_LOG2("  Address = %u\r\n", dev_addr);
 
+      // If the device itself is a usb hub, unplug downstream devices.
+      if (dev_addr > CFG_TUH_DEVICE_MAX)
+      {
+        process_device_unplugged(rhport, dev_addr, 0);
+      }
+
       // Invoke callback before close driver
       if (tuh_umount_cb) tuh_umount_cb(dev_addr);
 

From 731ac3d3d60daf4831f2e9491a45d30cc2492d5b Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Mon, 30 May 2022 14:01:57 -0400
Subject: [PATCH 1024/2085] msp430x5xx: Add fix for possible bug in
 msp430-elf-gcc 9.3.0.

---
 src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
index c3b3b2403..f1d350dcc 100644
--- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
+++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c
@@ -623,7 +623,18 @@ void dcd_int_handler(uint8_t rhport)
     handle_setup_packet();
   }
 
-  uint16_t curr_vector = USBVECINT;
+  // Workaround possible bug in MSP430 GCC 9.3.0 where volatile variable
+  // USBVECINT is read from twice when only once is intended. The second
+  // (garbage) read seems to be triggered by certain switch statement
+  // configurations.
+  uint16_t curr_vector;
+  #if __GNUC__ > 9 || (__GNUC__ == 9 && __GNUC_MINOR__ > 2)
+    asm volatile ("mov %1, %0"
+                  : "=r" (curr_vector)
+                  : "m" (USBVECINT));
+  #else
+    curr_vector = USBVECINT;
+  #endif
 
   switch(curr_vector)
   {

From f2926670cc4e495e025b0838fed5b44d27e4cd43 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 May 2022 20:26:37 +0700
Subject: [PATCH 1025/2085] comment out fifo count method for now

---
 src/class/audio/audio_device.c | 18 ++++++++++--------
 src/class/audio/audio_device.h |  7 +++++--
 2 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 31851e00c..01a42f34f 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -305,13 +305,12 @@ typedef struct
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-
   struct {
-    uint32_t value;     // Feedback value for asynchronous mode (in 16.16 format).
-    uint32_t min_value; // min value according to UAC2 FMT-2.0 section 2.3.1.1.
-    uint32_t max_value; // max value according to UAC2 FMT-2.0 section 2.3.1.1.
+    uint32_t value;       // Feedback value for asynchronous mode (in 16.16 format).
+    uint32_t min_value;   // min value according to UAC2 FMT-2.0 section 2.3.1.1.
+    uint32_t max_value;   // max value according to UAC2 FMT-2.0 section 2.3.1.1.
 
-    uint8_t frame_shift; // bInterval-1 in unit of frame (FS), micro-frame (HS)
+    uint8_t frame_shift;  // bInterval-1 in unit of frame (FS), micro-frame (HS)
     uint8_t compute_method;
 
     union {
@@ -323,15 +322,17 @@ typedef struct
         uint32_t mclk_freq;
       }fixed;
 
+#if 0 // implement later
       struct {
         uint32_t nominal_value;
         uint32_t threshold_bytes;
       }fifo_count;
+#endif
     }compute;
 
   } feedback;
-
 #endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
@@ -1729,8 +1730,8 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             set_fb_params_freq(audio, fb_param.sample_freq, fb_param.frequency.mclk_freq);
           break;
 
-          case AUDIO_FEEDBACK_METHOD_FIFO_COUNT_FIXED:
-          case AUDIO_FEEDBACK_METHOD_FIFO_COUNT_FLOAT:
+          #if 0 // implement later
+          case AUDIO_FEEDBACK_METHOD_FIFO_COUNT:
           {
             uint64_t fb64 = ((uint64_t) fb_param.sample_freq) << 16;
             audio->feedback.compute.fifo_count.nominal_value = (uint32_t) (fb64 / frame_div);
@@ -1739,6 +1740,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             tud_audio_fb_set(audio->feedback.compute.fifo_count.nominal_value);
           }
           break;
+          #endif
 
           // nothing to do
           default: break;
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index c44b4cc30..13f24fb62 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -498,8 +498,9 @@ enum {
   AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED,
   AUDIO_FEEDBACK_METHOD_FREQUENCY_FLOAT,
   AUDIO_FEEDBACK_METHOD_FREQUENCY_POWER_OF_2,
-  AUDIO_FEEDBACK_METHOD_FIFO_COUNT_FIXED,
-  AUDIO_FEEDBACK_METHOD_FIFO_COUNT_FLOAT
+
+  // impelemnt later
+  // AUDIO_FEEDBACK_METHOD_FIFO_COUNT
 };
 
 typedef struct {
@@ -511,9 +512,11 @@ typedef struct {
       uint32_t mclk_freq; // Main clock frequency in Hz i.e. master clock to which sample clock is based on
     }frequency;
 
+#if 0 // implement later
     struct {
       uint32_t threshold_bytes; // minimum number of bytes received to be considered as filled/ready
     }fifo_count;
+#endif
   };
 }audio_feedback_params_t;
 

From e384d16d576089daa3a5c993ead06cffb7a50cbe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 May 2022 21:52:54 +0700
Subject: [PATCH 1026/2085] clean up tud_audio_set_itf_cb() invocation

---
 src/class/audio/audio_device.c | 20 +-------------------
 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 01a42f34f..a2801e299 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1629,8 +1629,6 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 #endif
 
 #endif
-            // Invoke callback - can be used to trigger data sampling if not already running
-            //            if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
 
             // Schedule first transmit if alternate interface is not zero i.e. streaming is disabled - in case no sample data is available a ZLP is loaded
             // It is necessary to trigger this here since the refill is done with an RX FIFO empty interrupt which can only trigger if something was in there
@@ -1662,16 +1660,6 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 #endif
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-            // In case of asynchronous EP, call Cb after ep_fb is set
-            //            if ( !(desc_ep->bmAttributes.sync == 0x01 && audio->ep_fb == 0) )
-            //            {
-            //              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
-            //            }
-#else
-            // Invoke callback
-            if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
-#endif
             // Prepare for incoming data
 #if USE_LINEAR_BUFFER_RX
             TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false);
@@ -1688,12 +1676,6 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
             // Enable SOF interrupt if callback is implemented
             if (tud_audio_feedback_interval_isr) usbd_sof_enable(rhport, true);
-
-            //            // Invoke callback after ep_out is set
-            //            if (audio->ep_out != 0)
-            //            {
-            //              if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
-            //            }
           }
 #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -1705,10 +1687,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
       TU_VERIFY(foundEPs == nEps);
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
       // Invoke one callback for a final set interface
       if (tud_audio_set_itf_cb) TU_VERIFY(tud_audio_set_itf_cb(rhport, p_request));
 
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
       // Prepare feedback computation if callback is available
       if (tud_audio_feedback_params_cb)
       {

From 6e7cd220dc60b176e0096f4a5818376ea84a7e15 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Jun 2022 13:18:24 +0700
Subject: [PATCH 1027/2085] grstctl set fifo + flush in one assign

---
 src/portable/synopsys/dwc2/dcd_dwc2.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 01b74d05e..556bcaf65 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -796,8 +796,7 @@ static void dcd_edpt_disable (uint8_t rhport, uint8_t ep_addr, bool stall)
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
-    dwc2->grstctl = (epnum << GRSTCTL_TXFNUM_Pos);
-    dwc2->grstctl |= GRSTCTL_TXFFLSH;
+    dwc2->grstctl = ((epnum << GRSTCTL_TXFNUM_Pos) | GRSTCTL_TXFFLSH);
     while ( (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) != 0 ) {}
   }
   else

From ea8a9e024983441c4b2cb5ee27acf7953a2b607e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Jun 2022 15:10:05 +0700
Subject: [PATCH 1028/2085] remove cmake compile macro for net example (use
 lwipopts.h instead)

---
 examples/device/net_lwip_webserver/CMakeLists.txt | 6 ------
 examples/device/net_lwip_webserver/src/lwipopts.h | 2 --
 2 files changed, 8 deletions(-)

diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 7500f6e9e..8e3f0f5a8 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -69,12 +69,6 @@ if (EXISTS ${TOP}/lib/lwip/src)
             ${TOP}/lib/networking/rndis_reports.c
             )
 
-    target_compile_definitions(${PROJECT} PUBLIC
-            PBUF_POOL_SIZE=2
-            TCP_WND=2*TCP_MSS
-            HTTPD_USE_CUSTOM_FSDATA=0
-            )
-
     # Configure compilation flags and libraries for the example... see the corresponding function
     # in hw/bsp/FAMILY/family.cmake for details.
     family_configure_device_example(${PROJECT})
diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h
index 639619f63..a215017c7 100644
--- a/examples/device/net_lwip_webserver/src/lwipopts.h
+++ b/examples/device/net_lwip_webserver/src/lwipopts.h
@@ -49,9 +49,7 @@
 
 #define TCP_MSS                         (1500 /*mtu*/ - 20 /*iphdr*/ - 20 /*tcphhr*/)
 #define TCP_SND_BUF                     (2 * TCP_MSS)
-#ifndef TCP_WND
 #define TCP_WND                         (TCP_MSS)
-#endif
 
 #define ETHARP_SUPPORT_STATIC_ENTRIES   1
 

From 54d7790e8b9efd95bb0affb243b23a189ea06684 Mon Sep 17 00:00:00 2001
From: tfx2001 <tfx2001@outlook.com>
Date: Wed, 1 Jun 2022 21:25:36 +0800
Subject: [PATCH 1029/2085] fix compile error

---
 src/osal/osal_rtthread.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index a790a5e27..f8452bfb2 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -49,7 +49,7 @@ typedef rt_sem_t osal_semaphore_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t
 osal_semaphore_create(osal_semaphore_def_t *semdef) {
-    rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_FIFO);
+    rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_PRIO);
     return semdef;
 }
 
@@ -59,7 +59,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t se
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
-    return rt_sem_take(sem_hdl, rt_tick_from_millisecond(msec)) == RT_EOK;
+    return rt_sem_take(sem_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
@@ -73,12 +73,12 @@ typedef struct rt_mutex osal_mutex_def_t;
 typedef rt_mutex_t osal_mutex_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
-    rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_FIFO);
+    rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_PRIO);
     return mdef;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
-    return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond(msec)) == RT_EOK;
+    return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond((rt_int32_t) msec)) == RT_EOK;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
@@ -106,13 +106,13 @@ typedef rt_mq_t osal_queue_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) {
     rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz,
-               qdef->item_sz * qdef->depth, RT_IPC_FLAG_FIFO);
+               qdef->item_sz * qdef->depth, RT_IPC_FLAG_PRIO);
     return &(qdef->sq);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void *data, uint32_t msec) {
 
-    rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec));
+    rt_tick_t tick = rt_tick_from_millisecond((rt_int32_t) msec);
     return rt_mq_recv(qhdl, data, qhdl->msg_size, tick) == RT_EOK;
 }
 

From 99c1585ed215cb5ee2e27a41c54310d144e0ee6c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Jun 2022 23:53:40 +0700
Subject: [PATCH 1030/2085] rename board specific macro for example

- BOARD_DEVICE/HOST_RHPORT_NUM to  BOARD_TUD/H_RHPORT
- BOARD_DEVICE/HOST_RHPORT_SPEED to  BOARD_TUD/H_MAX_SPEED
---
 .../device/cdc_dual_ports/src/tusb_config.h   | 16 +++---
 examples/device/cdc_msc/src/tusb_config.h     | 54 ++++++++++++-------
 .../device/cdc_msc_freertos/src/tusb_config.h | 18 +++----
 examples/device/dfu/src/tusb_config.h         | 16 +++---
 examples/device/dfu_runtime/src/tusb_config.h | 16 +++---
 .../dynamic_configuration/src/tusb_config.h   | 16 +++---
 .../hid_boot_interface/src/tusb_config.h      | 18 +++----
 .../device/hid_composite/src/tusb_config.h    | 16 +++---
 .../hid_composite_freertos/src/tusb_config.h  | 16 +++---
 .../hid_generic_inout/src/tusb_config.h       | 16 +++---
 .../hid_multiple_interface/src/tusb_config.h  | 16 +++---
 examples/device/midi_test/src/tusb_config.h   | 16 +++---
 .../device/msc_dual_lun/src/tusb_config.h     | 16 +++---
 .../net_lwip_webserver/src/tusb_config.h      | 16 +++---
 examples/device/usbtmc/src/tusb_config.h      | 16 +++---
 .../device/video_capture/src/tusb_config.h    | 16 +++---
 .../device/webusb_serial/src/tusb_config.h    | 16 +++---
 .../host_hid_to_device_cdc/src/tusb_config.h  | 36 ++++++-------
 hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk   |  4 +-
 hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk   |  4 +-
 hw/bsp/imxrt/family.mk                        |  8 +--
 hw/bsp/lpc54/family.mk                        |  2 +-
 hw/bsp/lpc55/family.mk                        |  4 +-
 hw/bsp/stm32f7/family.c                       |  4 +-
 hw/bsp/stm32f7/family.mk                      |  6 +--
 hw/bsp/stm32h7/family.c                       |  4 +-
 hw/bsp/stm32h7/family.mk                      |  6 +--
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c      | 42 +++++++--------
 src/tusb_option.h                             |  2 +
 29 files changed, 226 insertions(+), 210 deletions(-)

diff --git a/examples/device/cdc_dual_ports/src/tusb_config.h b/examples/device/cdc_dual_ports/src/tusb_config.h
index f93606092..037fc8290 100644
--- a/examples/device/cdc_dual_ports/src/tusb_config.h
+++ b/examples/device/cdc_dual_ports/src/tusb_config.h
@@ -40,21 +40,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index 6507cef19..3849ad4d0 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -39,31 +39,45 @@
   #error CFG_TUSB_MCU must be defined
 #endif
 
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
-#endif
-
 // This example doesn't use an RTOS
 #ifndef CFG_TUSB_OS
 #define CFG_TUSB_OS               OPT_OS_NONE
 #endif
 
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+// Default to max (auto) speed for MCU with internal HighSpeed PHY
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+// Device mode with rhport and speed defined by board.mk
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#else
+  #error "Incorrect RHPort configuration"
+#endif
+
+
+
+// Device max speed, default is max speed that hardware controller could support without external PHY
+// BOARD_TUD_MAX_SPEED can be used to change value (e.g for board features external PHY).
+#ifdef BOARD_TUD_MAX_SPEED
+  #define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+#else
+  #define CFG_TUD_MAX_SPEED     OPT_MODE_DEFAULT_SPEED
+#endif
+
+
 // CFG_TUSB_DEBUG is defined by compiler in DEBUG build
 // #define CFG_TUSB_DEBUG           0
 
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index 55e84c62d..d8eeda07d 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -40,26 +40,26 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
-#ifndef BOARD_DEVICE_RHPORT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
   #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
        CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
+    #define BOARD_TUD_MAX_SPEED   OPT_MODE_HIGH_SPEED
   #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
+    #define BOARD_TUD_MAX_SPEED   OPT_MODE_FULL_SPEED
   #endif
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index d4779b2e1..924ede47a 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -22,21 +22,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/dfu_runtime/src/tusb_config.h b/examples/device/dfu_runtime/src/tusb_config.h
index e15ae7997..f31c9c970 100644
--- a/examples/device/dfu_runtime/src/tusb_config.h
+++ b/examples/device/dfu_runtime/src/tusb_config.h
@@ -22,21 +22,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/dynamic_configuration/src/tusb_config.h b/examples/device/dynamic_configuration/src/tusb_config.h
index ddc295dcc..333b62e03 100644
--- a/examples/device/dynamic_configuration/src/tusb_config.h
+++ b/examples/device/dynamic_configuration/src/tusb_config.h
@@ -40,21 +40,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/hid_boot_interface/src/tusb_config.h b/examples/device/hid_boot_interface/src/tusb_config.h
index 8bc85b722..e3c50aa3f 100644
--- a/examples/device/hid_boot_interface/src/tusb_config.h
+++ b/examples/device/hid_boot_interface/src/tusb_config.h
@@ -41,24 +41,24 @@
 
 // Use raspberry pio-usb for device
 // #define CFG_TUD_RPI_PIO_USB     1
-// #define BOARD_DEVICE_RHPORT_NUM 1
+// #define BOARD_TUD_RHPORT 1
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index d0f2b513f..1a9223f5b 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -40,21 +40,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index 7522bd714..8fd6498e6 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -40,21 +40,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/hid_generic_inout/src/tusb_config.h b/examples/device/hid_generic_inout/src/tusb_config.h
index 9db50269c..e5ae4b0cc 100644
--- a/examples/device/hid_generic_inout/src/tusb_config.h
+++ b/examples/device/hid_generic_inout/src/tusb_config.h
@@ -40,21 +40,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/hid_multiple_interface/src/tusb_config.h b/examples/device/hid_multiple_interface/src/tusb_config.h
index 32e8c2843..766b8e518 100644
--- a/examples/device/hid_multiple_interface/src/tusb_config.h
+++ b/examples/device/hid_multiple_interface/src/tusb_config.h
@@ -40,21 +40,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/midi_test/src/tusb_config.h b/examples/device/midi_test/src/tusb_config.h
index 967c71403..a7673245e 100644
--- a/examples/device/midi_test/src/tusb_config.h
+++ b/examples/device/midi_test/src/tusb_config.h
@@ -40,21 +40,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/msc_dual_lun/src/tusb_config.h b/examples/device/msc_dual_lun/src/tusb_config.h
index f617f5a4c..2778e61b0 100644
--- a/examples/device/msc_dual_lun/src/tusb_config.h
+++ b/examples/device/msc_dual_lun/src/tusb_config.h
@@ -40,21 +40,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h
index b1b48598b..5042c0e5d 100644
--- a/examples/device/net_lwip_webserver/src/tusb_config.h
+++ b/examples/device/net_lwip_webserver/src/tusb_config.h
@@ -40,21 +40,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/usbtmc/src/tusb_config.h b/examples/device/usbtmc/src/tusb_config.h
index 5b2215be5..0b2df291a 100644
--- a/examples/device/usbtmc/src/tusb_config.h
+++ b/examples/device/usbtmc/src/tusb_config.h
@@ -22,21 +22,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index 3a079e66b..85bf80a64 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -35,21 +35,21 @@
 //--------------------------------------------------------------------
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/device/webusb_serial/src/tusb_config.h b/examples/device/webusb_serial/src/tusb_config.h
index f5e4694e3..eab1d6387 100644
--- a/examples/device/webusb_serial/src/tusb_config.h
+++ b/examples/device/webusb_serial/src/tusb_config.h
@@ -40,21 +40,21 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_DEVICE_RHPORT_SPEED
-  #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_DEFAULT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
+  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
index 0fa4899a9..9a8f31da0 100644
--- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
+++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
@@ -40,13 +40,13 @@
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_DEVICE_RHPORT_NUM
-  #define BOARD_DEVICE_RHPORT_NUM     0
+#ifndef BOARD_TUD_RHPORT
+  #define BOARD_TUD_RHPORT     0
 #endif
 
 // RHPort number used for device can be defined by board.mk, default to port 1
-#ifndef BOARD_HOST_RHPORT_NUM
-  #define BOARD_HOST_RHPORT_NUM     1
+#ifndef BOARD_TUH_RHPORT
+  #define BOARD_TUH_RHPORT     1
 #endif
 
 // Use raspberry pio-usb for host
@@ -54,42 +54,42 @@
 
 // RHPort max operational speed can defined by board.mk
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
-#ifndef BOARD_DEVICE_RHPORT_SPEED
+#ifndef BOARD_TUD_MAX_SPEED
   #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
       TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) ||\
       TU_CHECK_MCU(OPT_MCU_FT90X, OPT_MCU_FT93X)
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
+    #define BOARD_TUD_MAX_SPEED   OPT_MODE_HIGH_SPEED
   #else
-    #define BOARD_DEVICE_RHPORT_SPEED   OPT_MODE_FULL_SPEED
+    #define BOARD_TUD_MAX_SPEED   OPT_MODE_FULL_SPEED
   #endif
 #endif
 
 // RHPort max operational speed can defined by board.mk
 // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
-#ifndef BOARD_HOST_RHPORT_SPEED
+#ifndef BOARD_TUH_MAX_SPEED
   #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
       TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) ||\
       TU_CHECK_MCU(OPT_MCU_FT90X, OPT_MCU_FT93X)
-    #define BOARD_HOST_RHPORT_SPEED   OPT_MODE_HIGH_SPEED
+    #define BOARD_TUH_MAX_SPEED   OPT_MODE_HIGH_SPEED
   #else
-    #define BOARD_HOST_RHPORT_SPEED   OPT_MODE_FULL_SPEED
+    #define BOARD_TUH_MAX_SPEED   OPT_MODE_FULL_SPEED
   #endif
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_DEVICE_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
-#elif BOARD_DEVICE_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
+#if   BOARD_TUD_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
+#elif BOARD_TUD_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
 
 // Device mode with rhport and speed defined by board.mk
-#if   BOARD_HOST_RHPORT_NUM == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_HOST | BOARD_HOST_RHPORT_SPEED)
-#elif BOARD_HOST_RHPORT_NUM == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_HOST | BOARD_HOST_RHPORT_SPEED)
+#if   BOARD_TUH_RHPORT == 0
+  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_HOST | BOARD_TUH_MAX_SPEED)
+#elif BOARD_TUH_RHPORT == 1
+  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_HOST | BOARD_TUH_MAX_SPEED)
 #else
   #error "Incorrect RHPort configuration"
 #endif
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
index b14b2a6b9..d21063c99 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
@@ -7,8 +7,8 @@ JLINK_DEVICE = MIMXRT1062xxx6A
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1060
 
-BOARD_DEVICE_RHPORT_NUM = 1
-BOARD_HOST_RHPORT_NUM = 0
+BOARD_TUD_RHPORT = 1
+BOARD_TUH_RHPORT = 0
 
 # flash using pyocd
 flash: flash-pyocd
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
index 2b479719f..00b574c52 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
@@ -7,8 +7,8 @@ JLINK_DEVICE = MIMXRT1064xxx6A
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1064
 
-BOARD_DEVICE_RHPORT_NUM = 1
-BOARD_HOST_RHPORT_NUM = 0
+BOARD_TUD_RHPORT = 1
+BOARD_TUH_RHPORT = 0
 
 # flash using pyocd
 flash: flash-pyocd
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 0bf4a0d15..c81e67eb6 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -15,11 +15,11 @@ CFLAGS += \
   -DXIP_BOOT_HEADER_ENABLE=1 \
   -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX
 
-ifdef BOARD_DEVICE_RHPORT_NUM
-CFLAGS += -DBOARD_DEVICE_RHPORT_NUM=$(BOARD_DEVICE_RHPORT_NUM)
+ifdef BOARD_TUD_RHPORT
+CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT)
 endif
-ifdef BOARD_HOST_RHPORT_NUM
-CFLAGS += -DBOARD_HOST_RHPORT_NUM=$(BOARD_HOST_RHPORT_NUM)
+ifdef BOARD_TUH_RHPORT
+CFLAGS += -DBOARD_TUH_RHPORT=$(BOARD_TUH_RHPORT)
 endif
 
 # mcu driver cause following warnings
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index 600df6fd0..39111d1ad 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -15,7 +15,7 @@ CFLAGS += \
 
 ifeq ($(PORT), 1)
   $(info "PORT1 High Speed")
-  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
 
   # LPC55 Highspeed Port1 can only write to USB_SRAM region
   CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index 4e8d65ce9..1af1d076e 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -16,11 +16,11 @@ CFLAGS += \
   -mfpu=fpv5-sp-d16 \
   -DCFG_TUSB_MCU=OPT_MCU_LPC55XX \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
-  -DBOARD_DEVICE_RHPORT_NUM=$(PORT)
+  -DBOARD_TUD_RHPORT=$(PORT)
 
 ifeq ($(PORT), 1)
   $(info "PORT1 High Speed")
-  CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
 
   # LPC55 Highspeed Port1 can only write to USB_SRAM region
   CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index 14e3b2fd9..425e6e1bc 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -125,7 +125,7 @@ void board_init(void)
   UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
   HAL_UART_Init(&UartHandle);
 
-#if BOARD_DEVICE_RHPORT_NUM == 0
+#if BOARD_TUD_RHPORT == 0
   // OTG_FS
 
   /* Configure DM DP Pins */
@@ -258,7 +258,7 @@ void board_init(void)
   USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD;
   USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
 
-#endif // BOARD_DEVICE_RHPORT_NUM
+#endif // BOARD_TUD_RHPORT
 
 }
 
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index 8482e6dd2..b8a5d7ead 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -16,14 +16,14 @@ CFLAGS += \
   -mfpu=fpv5-d16 \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F7 \
-  -DBOARD_DEVICE_RHPORT_NUM=$(PORT)
+  -DBOARD_TUD_RHPORT=$(PORT)
 
 ifeq ($(PORT), 1)
   ifeq ($(SPEED), high)
-    CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+    CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
     $(info "Using OTG_HS in HighSpeed mode")
   else
-    CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_FULL_SPEED
+    CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
     $(info "Using OTG_HS in FullSpeed mode")
   endif
 else
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 84976b4e4..3964f427a 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -122,7 +122,7 @@ void board_init(void)
   UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
   HAL_UART_Init(&UartHandle);
 
-#if BOARD_DEVICE_RHPORT_NUM == 0
+#if BOARD_TUD_RHPORT == 0
   // Despite being call USB2_OTG
   // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
   // PA9 VUSB, PA10 ID, PA11 DM, PA12 DP
@@ -166,7 +166,7 @@ void board_init(void)
   USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
 #endif // vbus sense
 
-#elif BOARD_DEVICE_RHPORT_NUM == 1
+#elif BOARD_TUD_RHPORT == 1
   // Despite being call USB2_OTG
   // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
 
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index 096d04d0c..a1cd93b27 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -16,14 +16,14 @@ CFLAGS += \
   -mfpu=fpv5-d16 \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32H7 \
-	-DBOARD_DEVICE_RHPORT_NUM=$(PORT)
+	-DBOARD_TUD_RHPORT=$(PORT)
 
 ifeq ($(PORT), 1)
   ifeq ($(SPEED), high)
-    CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+    CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
     $(info "Using OTG_HS in HighSpeed mode")
   else
-    CFLAGS += -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_FULL_SPEED
+    CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
     $(info "Using OTG_HS in FullSpeed mode")
   endif
 else
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 3c3cb63b8..7a65cf5d0 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -239,12 +239,12 @@ static void _dcd_ft90x_attach(void)
 
   CRITICAL_SECTION_BEGIN
   // Turn off the device enable bit.
-#if BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_HIGH_SPEED
+#if BOARD_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED
   USBD_REG(fctrl) = 0;
-#else // BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_FULL_SPEED
+#else // BOARD_TUD_MAX_SPEED == OPT_MODE_FULL_SPEED
   //Set the full speed only bit if required.
   USBD_REG(fctrl) = MASK_USBD_FCTRL_MODE_FS_ONLY;
-#endif // BOARD_DEVICE_RHPORT_SPEED
+#endif // BOARD_TUD_MAX_SPEED
 
   // Clear first reset and suspend interrupts.
   do
@@ -291,7 +291,7 @@ static void _dcd_ft90x_detach(void)
   delayms(1);
 
   // Disable USB PHY
-  dcd_disconnect(BOARD_DEVICE_RHPORT_NUM);
+  dcd_disconnect(BOARD_TUD_RHPORT);
   delayms(1);
 
   // Disable Chip USB device clock/PM configuration.
@@ -323,7 +323,7 @@ static void _ft90x_usb_speed(void)
 		delayus(200);
 	}
 
-#if BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_HIGH_SPEED
+#if BOARD_TUD_MAX_SPEED == OPT_MODE_HIGH_SPEED
 
 	/* Detect high or full speed */
 	fctrl_val = MASK_USBD_FCTRL_USB_DEV_EN;
@@ -347,11 +347,11 @@ static void _ft90x_usb_speed(void)
 	delayus(125 + 5);
 	_speed = (USBD_REG(cmif) & MASK_USBD_CMIF_SOFIRQ) ?
 		TUSB_SPEED_HIGH : TUSB_SPEED_FULL;
-  dcd_event_bus_reset(BOARD_DEVICE_RHPORT_NUM, _speed, true);
+  dcd_event_bus_reset(BOARD_TUD_RHPORT, _speed, true);
 
 #endif /* !__FT930__ */
 
-#else // BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_FULL_SPEED
+#else // BOARD_TUD_MAX_SPEED == OPT_MODE_FULL_SPEED
 
 	/* User force set to full speed */
   _speed = TUSB_SPEED_FULL;
@@ -364,10 +364,10 @@ static void _ft90x_usb_speed(void)
 	}
 #endif
 	USBD_REG(fctrl) = fctrl_val;
-  dcd_event_bus_reset(BOARD_DEVICE_RHPORT_NUM, _speed, true);
+  dcd_event_bus_reset(BOARD_TUD_RHPORT, _speed, true);
 	return;
 
-#endif // BOARD_DEVICE_RHPORT_SPEED
+#endif // BOARD_TUD_MAX_SPEED
 }
 
 // Send a buffer to the USB IN FIFO.
@@ -899,7 +899,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
 void _ft90x_usbd_ISR(void)
 {
-  tud_int_handler(BOARD_DEVICE_RHPORT_NUM); // Resolves to dcd_int_handler().
+  tud_int_handler(BOARD_TUD_RHPORT); // Resolves to dcd_int_handler().
 }
 
 void dcd_int_handler(uint8_t rhport)
@@ -937,19 +937,19 @@ void dcd_int_handler(uint8_t rhport)
     {
       // Reset endpoints to default state.
       _ft90x_reset_edpts();
-      dcd_event_bus_reset(BOARD_DEVICE_RHPORT_NUM, _speed, true);
+      dcd_event_bus_reset(BOARD_TUD_RHPORT, _speed, true);
     }
     if (cmif & MASK_USBD_CMIF_SUSIRQ) //Handle Suspend interrupt
     {
-      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_SUSPEND, true);
+      dcd_event_bus_signal(BOARD_TUD_RHPORT, DCD_EVENT_SUSPEND, true);
     }
     if (cmif & MASK_USBD_CMIF_RESIRQ) //Handle Resume interrupt
     {
-      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_RESUME, true);
+      dcd_event_bus_signal(BOARD_TUD_RHPORT, DCD_EVENT_RESUME, true);
     }
     if (cmif & MASK_USBD_CMIF_SOFIRQ) //Handle SOF interrupt
     {
-      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_SOF, true);
+      dcd_event_bus_signal(BOARD_TUD_RHPORT, DCD_EVENT_SOF, true);
     }
   }
   // Handle endpoint interrupts.
@@ -980,7 +980,7 @@ void dcd_int_handler(uint8_t rhport)
         _ft90x_dusb_out(USBD_EP_0, (uint8_t *)_ft90x_setup_packet, sizeof(USB_device_request));
         
         // Send the packet to tinyusb.
-        dcd_event_setup_received(BOARD_DEVICE_RHPORT_NUM, _ft90x_setup_packet, true);
+        dcd_event_setup_received(BOARD_TUD_RHPORT, _ft90x_setup_packet, true);
 
         // Clear the interrupt that signals a SETUP packet is received.
         USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_SETUP);
@@ -1002,7 +1002,7 @@ void dcd_int_handler(uint8_t rhport)
             xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, (uint8_t *)ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
           }
           // Now signal completion of data packet.
-          dcd_event_xfer_complete(BOARD_DEVICE_RHPORT_NUM, (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true);
+          dcd_event_xfer_complete(BOARD_TUD_RHPORT, (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true);
 
           // Allow new transfers on the control endpoint.
           ep_xfer[USBD_EP_0].valid = 0;
@@ -1059,7 +1059,7 @@ void dcd_int_handler(uint8_t rhport)
           if (ep_xfer[ep_number].remain_size == 0)
           {
             // Signal tinyUSB.
-            dcd_event_xfer_complete(BOARD_DEVICE_RHPORT_NUM, ep_number | ep_dirmask, ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
+            dcd_event_xfer_complete(BOARD_TUD_RHPORT, ep_number | ep_dirmask, ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
 
             // Allow new transfers on this endpoint.
             ep_xfer[ep_number].valid = 0;
@@ -1084,21 +1084,21 @@ void ft90x_usbd_pm_ISR(void)
   {
       // Signal connection interrupt
       SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
-      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_RESUME, true);
+      dcd_event_bus_signal(BOARD_TUD_RHPORT, DCD_EVENT_RESUME, true);
   }
 
   if (pmcfg & MASK_SYS_PMCFG_DEV_DIS_DEV)
   {
       // Signal disconnection interrupt
       SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
-      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_UNPLUGGED, true);
+      dcd_event_bus_signal(BOARD_TUD_RHPORT, DCD_EVENT_UNPLUGGED, true);
   }
 
   if (pmcfg & MASK_SYS_PMCFG_HOST_RST_DEV)
   {
       // Signal Host Reset interrupt
       SYS->PMCFG_H = MASK_SYS_PMCFG_PM_GPIO_IRQ_PEND;
-      dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_BUS_RESET, true);
+      dcd_event_bus_signal(BOARD_TUD_RHPORT, DCD_EVENT_BUS_RESET, true);
   }
 
   if (pmcfg & MASK_SYS_PMCFG_HOST_RESUME_DEV)
@@ -1109,7 +1109,7 @@ void ft90x_usbd_pm_ISR(void)
       {
           // If we are driving K-state on Device USB port;
           // We must maintain the 1ms requirement before resuming the phy
-          dcd_event_bus_signal(BOARD_DEVICE_RHPORT_NUM, DCD_EVENT_RESUME, true);
+          dcd_event_bus_signal(BOARD_TUD_RHPORT, DCD_EVENT_RESUME, true);
       }
   }
 }
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 3b054fc78..ce22a8a6a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -221,7 +221,9 @@ typedef int make_iso_compilers_happy ;
   #define TUD_OPT_RHPORT      -1
 #endif
 
+#ifndef CFG_TUD_ENABLED
 #define CFG_TUD_ENABLED       (TUD_RHPORT_MODE & OPT_MODE_DEVICE)
+#endif
 
 #if CFG_TUD_ENABLED
   #define TUD_OPT_HIGH_SPEED  ((TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK) ? (TUD_RHPORT_MODE & OPT_MODE_HIGH_SPEED) : (TUP_RHPORT_HIGHSPEED & (1 << TUD_OPT_RHPORT)))

From 0ee74a71e27b86b89ca737f50a8e2c09753a3875 Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Mon, 7 Mar 2022 14:09:08 +0000
Subject: [PATCH 1031/2085] add renesas fsp submodule

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 .gitmodules        | 3 +++
 hw/mcu/renesas/fsp | 1 +
 2 files changed, 4 insertions(+)
 create mode 160000 hw/mcu/renesas/fsp

diff --git a/.gitmodules b/.gitmodules
index 044ac24ec..08ce4f447 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -149,3 +149,6 @@
 [submodule "hw/mcu/raspberry_pi/Pico-PIO-USB"]
 	path = hw/mcu/raspberry_pi/Pico-PIO-USB
 	url = https://github.com/sekigon-gonnoc/Pico-PIO-USB.git
+[submodule "hw/mcu/renesas/fsp"]
+	path = hw/mcu/renesas/fsp
+	url = https://github.com/renesas/fsp
diff --git a/hw/mcu/renesas/fsp b/hw/mcu/renesas/fsp
new file mode 160000
index 000000000..8dc14709f
--- /dev/null
+++ b/hw/mcu/renesas/fsp
@@ -0,0 +1 @@
+Subproject commit 8dc14709f2a6518b43f71efad70d900b7718d9f1

From f2e8a60e6d910170bf514087e1de24088d712ba8 Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Tue, 8 Mar 2022 15:29:58 +0000
Subject: [PATCH 1032/2085] add .vscode to gitignore

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 .gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.gitignore b/.gitignore
index 87a5faa80..4a12f6ab7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -13,6 +13,7 @@ latex
 .env
 .settings/
 .idea/
+.vscode/
 .gdb_history
 /examples/*/*/build*
 test_old/

From dcadbf3364778814c8a0e7e73481d12e8687f1bd Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Tue, 8 Mar 2022 16:05:29 +0000
Subject: [PATCH 1033/2085] rename renesas driver to link

	link was chosen according to the name for the usb core on datasheets, LINK core

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 docs/reference/supported.rst                              | 6 +++---
 hw/bsp/rx/family.mk                                       | 4 ++--
 src/portable/renesas/{usba/dcd_usba.c => link/dcd_link.c} | 0
 src/portable/renesas/{usba/hcd_usba.c => link/hcd_link.c} | 0
 4 files changed, 5 insertions(+), 5 deletions(-)
 rename src/portable/renesas/{usba/dcd_usba.c => link/dcd_link.c} (100%)
 rename src/portable/renesas/{usba/hcd_usba.c => link/hcd_link.c} (100%)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 7ce982713..3c1b94623 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -59,9 +59,9 @@ Supported MCUs
 |              |         | 55          | ✔      |      | ✔         | lpc_ip3511        |              |
 +--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
 | Raspberry Pi | RP2040                | ✔      | ✔    | ✖         | rp2040            |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
-| Renesas      | RX 63N, 65N, 72N      | ✔      | ✔    | ✖         | usba              |              |
-+--------------+-----------------------+--------+------+-----------+-------------------+--------------+
++--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
+| Renesas      | RX  | 63N, 65N, 72N   | ✔      | ✔    | ✖         | link              |              |
++--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
 | Silabs       | EFM32GG12             | ✔      |      | ✖         | dwc2              |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
 | Sony         | CXD56                 | ✔      | ✖    | ✔         | cxd56             |              |
diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk
index aba05812d..22b9031b3 100644
--- a/hw/bsp/rx/family.mk
+++ b/hw/bsp/rx/family.mk
@@ -14,8 +14,8 @@ CFLAGS += \
   -DSSIZE_MAX=__INT_MAX__
 
 SRC_C += \
-	src/portable/renesas/usba/dcd_usba.c \
-	src/portable/renesas/usba/hcd_usba.c \
+	src/portable/renesas/link/dcd_link.c \
+	src/portable/renesas/link/hcd_link.c \
 	$(MCU_DIR)/vects.c
 
 INC += \
diff --git a/src/portable/renesas/usba/dcd_usba.c b/src/portable/renesas/link/dcd_link.c
similarity index 100%
rename from src/portable/renesas/usba/dcd_usba.c
rename to src/portable/renesas/link/dcd_link.c
diff --git a/src/portable/renesas/usba/hcd_usba.c b/src/portable/renesas/link/hcd_link.c
similarity index 100%
rename from src/portable/renesas/usba/hcd_usba.c
rename to src/portable/renesas/link/hcd_link.c

From 03777f4a467c7ff7e0e764cfcf79d04235a2659d Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Wed, 9 Mar 2022 11:52:39 +0000
Subject: [PATCH 1034/2085] generalize renesas LINK core driver

	create local register access struct and move mcu specific code
	in preparation of support for other mcu families that use the LINK usb core

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 hw/bsp/rx/boards/gr_citrus/gr_citrus.c       |    5 +
 hw/bsp/rx/boards/rx65n_target/rx65n_target.c |    5 +
 src/portable/renesas/link/dcd_link.c         |  357 ++--
 src/portable/renesas/link/hcd_link.c         |  421 ++---
 src/portable/renesas/link/link_rx.h          |   76 +
 src/portable/renesas/link/link_type.h        | 1658 ++++++++++++++++++
 6 files changed, 2034 insertions(+), 488 deletions(-)
 create mode 100644 src/portable/renesas/link/link_rx.h
 create mode 100644 src/portable/renesas/link/link_type.h

diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
index 633ddad16..9bd9399f6 100644
--- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
+++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
@@ -201,6 +201,11 @@ void board_init(void)
   IEN(SCI0, RXI0) = 1;
   IEN(SCI0, TXI0) = 1;
   IEN(SCI0, TEI0) = 1;
+
+  /* Enable USB0 */
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(USB0) = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index f189e40e4..3c729ad50 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -248,6 +248,11 @@ void board_init(void)
   IEN(ICU,GROUPBL0)  = 1;
   EN(SCI5, TEI5)     = 1;
 
+  /* Enable USB0 */
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(USB0) = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+
   /* setup USBI0 interrupt. */
   IR(USB0, USBI0)  = 0;
   IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c
index fa87c9f4d..3aeda9e4c 100644
--- a/src/portable/renesas/link/dcd_link.c
+++ b/src/portable/renesas/link/dcd_link.c
@@ -31,79 +31,29 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
-                                 CFG_TUSB_MCU == OPT_MCU_RX65X || \
-                                 CFG_TUSB_MCU == OPT_MCU_RX72N )
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N)
+
 #include "device/dcd.h"
-#include "iodefine.h"
+#include "link_type.h"
+
+#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+#include "link_rx.h"
+#else
+#error "Unsupported MCU"
+#endif
 
 //--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+// MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
-#define SYSTEM_PRCR_PRC1     (1<<1)
-#define SYSTEM_PRCR_PRKEY    (0xA5u<<8)
 
-#define USB_FIFOSEL_TX       ((uint16_t)(1u<<5))
-#define USB_FIFOSEL_BIGEND   ((uint16_t)(1u<<8))
-#define USB_FIFOSEL_MBW_8    ((uint16_t)(0u<<10))
-#define USB_FIFOSEL_MBW_16   ((uint16_t)(1u<<10))
-#define USB_IS0_CTSQ         ((uint16_t)(7u))
-#define USB_IS0_DVSQ         ((uint16_t)(7u<<4))
-#define USB_IS0_VALID        ((uint16_t)(1u<<3))
-#define USB_IS0_BRDY         ((uint16_t)(1u<<8))
-#define USB_IS0_NRDY         ((uint16_t)(1u<<9))
-#define USB_IS0_BEMP         ((uint16_t)(1u<<10))
-#define USB_IS0_CTRT         ((uint16_t)(1u<<11))
-#define USB_IS0_DVST         ((uint16_t)(1u<<12))
-#define USB_IS0_SOFR         ((uint16_t)(1u<<13))
-#define USB_IS0_RESM         ((uint16_t)(1u<<14))
-#define USB_IS0_VBINT        ((uint16_t)(1u<<15))
-#define USB_IS1_SACK         ((uint16_t)(1u<<4))
-#define USB_IS1_SIGN         ((uint16_t)(1u<<5))
-#define USB_IS1_EOFERR       ((uint16_t)(1u<<6))
-#define USB_IS1_ATTCH        ((uint16_t)(1u<<11))
-#define USB_IS1_DTCH         ((uint16_t)(1u<<12))
-#define USB_IS1_BCHG         ((uint16_t)(1u<<14))
-#define USB_IS1_OVRCR        ((uint16_t)(1u<<15))
+/* LINK core registers */
+#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE)
 
-#define USB_IS0_CTSQ_MSK     (7u)
-#define USB_IS0_CTSQ_SETUP   (1u)
-#define USB_IS0_DVSQ_DEF     (1u<<4)
-#define USB_IS0_DVSQ_ADDR    (2u<<4)
-#define USB_IS0_DVSQ_SUSP0   (4u<<4)
-#define USB_IS0_DVSQ_SUSP1   (5u<<4)
-#define USB_IS0_DVSQ_SUSP2   (6u<<4)
-#define USB_IS0_DVSQ_SUSP3   (7u<<4)
-
-#define USB_PIPECTR_PID_NAK   (0u)
-#define USB_PIPECTR_PID_BUF   (1u)
-#define USB_PIPECTR_PID_STALL (2u)
-#define USB_PIPECTR_CCPL      (1u<<2)
-#define USB_PIPECTR_SQMON     (1u<<6)
-#define USB_PIPECTR_SQCLR     (1u<<8)
-#define USB_PIPECTR_ACLRM     (1u<<9)
-#define USB_PIPECTR_INBUFM    (1u<<14)
-#define USB_PIPECTR_BSTS      (1u<<15)
-
-#define USB_FIFOCTR_DTLN     (0x1FF)
-#define USB_FIFOCTR_FRDY     (1u<<13)
-#define USB_FIFOCTR_BCLR     (1u<<14)
-#define USB_FIFOCTR_BVAL     (1u<<15)
-
-#define USB_PIPECFG_SHTNAK   (1u<<7)
-#define USB_PIPECFG_DBLB     (1u<<9)
-#define USB_PIPECFG_BULK     (1u<<14)
-#define USB_PIPECFG_ISO      (3u<<14)
-#define USB_PIPECFG_INT      (2u<<14)
-
-#define FIFO_REQ_CLR         (1u)
-#define FIFO_COMPLETE        (1u<<1)
-
-// Start of definition of packed structs (used by the CCRX toolchain)
+/* Start of definition of packed structs (used by the CCRX toolchain) */
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
-typedef struct {
+typedef struct TU_ATTR_PACKED {
   union {
     struct {
       uint16_t      : 8;
@@ -116,7 +66,7 @@ typedef struct {
   uint16_t TRN;
 } reg_pipetre_t;
 
-typedef union {
+typedef union TU_ATTR_PACKED {
   struct {
     volatile uint16_t u8: 8;
     volatile uint16_t   : 0;
@@ -150,28 +100,6 @@ typedef struct
 //--------------------------------------------------------------------+
 static dcd_data_t _dcd;
 
-static uint32_t disable_interrupt(void)
-{
-  uint32_t pswi;
-#if defined(__CCRX__)
-  pswi = get_psw() & 0x010000;
-  clrpsw_i();
-#else
-  pswi = __builtin_rx_mvfc(0) & 0x010000;
-  __builtin_rx_clrpsw('I');
-#endif
-  return pswi;
-}
-
-static void enable_interrupt(uint32_t pswi)
-{
-#if defined(__CCRX__)
-  set_psw(get_psw() | pswi);
-#else
-  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
-#endif
-}
-
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
@@ -202,22 +130,18 @@ static unsigned find_pipe(unsigned xfer)
 
 static volatile uint16_t* get_pipectr(unsigned num)
 {
-  volatile uint16_t *ctr = NULL;
   if (num) {
-    ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
-    ctr += num - 1;
+    return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]);
   } else {
-    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
+    return (volatile uint16_t*)&(LINK_REG->DCPCTR);
   }
-  return ctr;
 }
 
 static volatile reg_pipetre_t* get_pipetre(unsigned num)
 {
   volatile reg_pipetre_t* tre = NULL;
   if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD;
-    tre += num - 1;
+    tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E);
   }
   return tre;
 }
@@ -225,36 +149,31 @@ static volatile reg_pipetre_t* get_pipetre(unsigned num)
 static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
 {
   (void)rhport;
-  volatile uint16_t *ctr = NULL;
-  const unsigned epn   = tu_edpt_number(ep_addr);
+  const unsigned epn = tu_edpt_number(ep_addr);
   if (epn) {
     const unsigned dir = tu_edpt_dir(ep_addr);
     const unsigned num = _dcd.ep[dir][epn];
-    if (num) {
-      ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
-      ctr += num - 1;
-    }
+    return get_pipectr(num);
   } else {
-    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
+    return get_pipectr(0);
   }
-  return ctr;
 }
 
 static unsigned edpt0_max_packet_size(void)
 {
-  return USB0.DCPMAXP.BIT.MXPS;
+  return LINK_REG->DCPMAXP_b.MXPS;
 }
 
 static unsigned edpt_max_packet_size(unsigned num)
 {
-  USB0.PIPESEL.WORD = num;
-  return USB0.PIPEMAXP.WORD;
+  LINK_REG->PIPESEL = num;
+  return LINK_REG->PIPEMAXP;
 }
 
 static inline void pipe_wait_for_ready(unsigned num)
 {
-  while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
-  while (!USB0.D0FIFOCTR.BIT.FRDY) ;
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ;
+  while (!LINK_REG->D0FIFOCTR_b.FRDY) ;
 }
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -316,13 +235,14 @@ static bool pipe0_xfer_in(void)
   void          *buf = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
+      pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
-  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+  if (len < mps)
+    LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL;
   pipe->remaining = rem - len;
   return false;
 }
@@ -333,18 +253,19 @@ static bool pipe0_xfer_out(void)
   const unsigned rem = pipe->remaining;
 
   const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = USB0.CFIFOCTR.BIT.DTLN;
+  const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN;
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.CFIFO.WORD, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
+      pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
-  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
+  if (len < mps)
+    LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
@@ -363,22 +284,23 @@ static bool pipe_xfer_in(unsigned num)
     return true;
   }
 
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
+  LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
   const unsigned len  = TU_MIN(rem, mps);
   void          *buf  = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
+      pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
-  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  if (len < mps)
+    LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
+  LINK_REG->D0FIFOSEL = 0;
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   return false;
 }
@@ -388,24 +310,25 @@ static bool pipe_xfer_out(unsigned num)
   pipe_state_t  *pipe = &_dcd.pipe[num];
   const unsigned rem  = pipe->remaining;
 
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
+  LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_8;
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
-  const unsigned vld  = USB0.D0FIFOCTR.BIT.DTLN;
+  const unsigned vld  = LINK_REG->D0FIFOCTR_b.DTLN;
   const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf  = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&USB0.D0FIFO.WORD, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
+      pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
-  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  pipe->remaining     = rem - len;
+  if (len < mps)
+    LINK_REG->D0FIFOCTR = USB_FIFOCTR_BCLR;
+  LINK_REG->D0FIFOSEL = 0;
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return NULL != buf;
@@ -416,13 +339,13 @@ static bool pipe_xfer_out(unsigned num)
 static void process_setup_packet(uint8_t rhport)
 {
   uint16_t setup_packet[4];
-  if (0 == (USB0.INTSTS0.WORD & USB_IS0_VALID)) return;
-  USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
-  setup_packet[0] = tu_le16toh(USB0.USBREQ.WORD);
-  setup_packet[1] = USB0.USBVAL;
-  setup_packet[2] = USB0.USBINDX;
-  setup_packet[3] = USB0.USBLENG;
-  USB0.INTSTS0.WORD = ~USB_IS0_VALID;
+  if (0 == (LINK_REG->INTSTS0 & USB_IS0_VALID)) return;
+  LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
+  setup_packet[0] = tu_le16toh(LINK_REG->USBREQ);
+  setup_packet[1] = LINK_REG->USBVAL;
+  setup_packet[2] = LINK_REG->USBINDX;
+  setup_packet[3] = LINK_REG->USBLENG;
+  LINK_REG->INTSTS0 = ~USB_IS0_VALID;
   dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
 }
 
@@ -430,7 +353,7 @@ static void process_status_completion(uint8_t rhport)
 {
   uint8_t ep_addr;
   /* Check the data stage direction */
-  if (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) {
+  if (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) {
     /* IN transfer. */
     ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
   } else {
@@ -444,11 +367,12 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
 {
   /* configure fifo direction and access unit settings */
   if (ep_addr) { /* IN, 2 bytes */
-    USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
-    while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
-  } else {       /* OUT, a byte */
-    USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8;
-    while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
+    LINK_REG->CFIFOSEL =
+      USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
+    while (!(LINK_REG->CFIFOSEL & USB_FIFOSEL_TX)) ;
+  } else { /* OUT, a byte */
+    LINK_REG->CFIFOSEL = USB_FIFOSEL_MBW_8;
+    while (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) ;
   }
 
   pipe_state_t *pipe = &_dcd.pipe[0];
@@ -458,14 +382,14 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
   if (total_bytes) {
     pipe->buf     = buffer;
     if (ep_addr) { /* IN */
-      TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
+      TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80));
       pipe0_xfer_in();
     }
-    USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
+    LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF;
   } else {
     /* ZLP */
     pipe->buf        = NULL;
-    USB0.DCPCTR.WORD = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
+    LINK_REG->DCPCTR = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
   }
   return true;
 }
@@ -487,11 +411,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
     if (total_bytes) {
       pipe_xfer_in(num);
     } else { /* ZLP */
-      USB0.D0FIFOSEL.WORD = num;
+      LINK_REG->D0FIFOSEL = num;
       pipe_wait_for_ready(num);
-      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-      USB0.D0FIFOSEL.WORD = 0;
-      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+      LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
+      LINK_REG->D0FIFOSEL = 0;
+      while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
     }
   } else {
 #if defined(__CCRX__)
@@ -558,18 +482,18 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
 
 static void process_bus_reset(uint8_t rhport)
 {
-  USB0.BEMPENB.WORD   = 1;
-  USB0.BRDYENB.WORD   = 1;
-  USB0.CFIFOCTR.WORD  = USB_FIFOCTR_BCLR;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  USB0.D1FIFOSEL.WORD = 0;
-  while (USB0.D1FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1CTR.WORD));
-  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t)(&USB0.PIPE1TRE.WORD));
+  LINK_REG->BEMPENB = 1;
+  LINK_REG->BRDYENB = 1;
+  LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
+  LINK_REG->D0FIFOSEL = 0;
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  LINK_REG->D1FIFOSEL = 0;
+  while (LINK_REG->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_CTR[0]));
+  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_TR[0].E));
   for (int i = 1; i <= 5; ++i) {
-    USB0.PIPESEL.WORD  = i;
-    USB0.PIPECFG.WORD  = 0;
+    LINK_REG->PIPESEL = i;
+    LINK_REG->PIPECFG = 0;
     *ctr = USB_PIPECTR_ACLRM;
     *ctr = 0;
     ++ctr;
@@ -577,8 +501,8 @@ static void process_bus_reset(uint8_t rhport)
     tre += 2;
   }
   for (int i = 6; i <= 9; ++i) {
-    USB0.PIPESEL.WORD  = i;
-    USB0.PIPECFG.WORD  = 0;
+    LINK_REG->PIPESEL = i;
+    LINK_REG->PIPECFG = 0;
     *ctr = USB_PIPECTR_ACLRM;
     *ctr = 0;
     ++ctr;
@@ -589,7 +513,7 @@ static void process_bus_reset(uint8_t rhport)
 
 static void process_set_address(uint8_t rhport)
 {
-  const uint32_t addr = USB0.USBADDR.BIT.USBADDR;
+  const uint32_t addr = LINK_REG->USBADDR_b.USBADDR;
   if (!addr) return;
   const tusb_control_request_t setup_packet = {
 #if defined(__CCRX__)
@@ -611,56 +535,39 @@ static void process_set_address(uint8_t rhport)
 void dcd_init(uint8_t rhport)
 {
   (void)rhport;
-  /* Enable USB0 */
-  uint32_t pswi = disable_interrupt();
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(USB0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  enable_interrupt(pswi);
-  USB0.SYSCFG.BIT.SCKE = 1;
-  while (!USB0.SYSCFG.BIT.SCKE) ;
-  USB0.SYSCFG.BIT.DRPD = 0;
-  USB0.SYSCFG.BIT.DCFM = 0;
-  USB0.SYSCFG.BIT.USBE = 1;
 
-  USB.DPUSR0R.BIT.FIXPHY0 = 0u;    /* USB0 Transceiver Output fixed */
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  USB0.PHYSLEW.LONG = 0x5;
-  IR(PERIB, INTB185) = 0;
-#else
-  IR(USB0, USBI0)   = 0;
-#endif
+  LINK_REG->SYSCFG_b.SCKE = 1;
+  while (!LINK_REG->SYSCFG_b.SCKE) ;
+  LINK_REG->SYSCFG_b.DRPD = 0;
+  LINK_REG->SYSCFG_b.DCFM = 0;
+  LINK_REG->SYSCFG_b.USBE = 1;
+
+  // MCU specific PHY init
+  link_phy_init();
+
+  LINK_REG->PHYSLEW = 0x5;
+  LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
 
   /* Setup default control pipe */
-  USB0.DCPMAXP.BIT.MXPS  = 64;
-  USB0.INTENB0.WORD = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP |
-    USB_IS0_DVST | USB_IS0_CTRT | (USE_SOF ? USB_IS0_SOFR: 0) | USB_IS0_RESM;
-  USB0.BEMPENB.WORD = 1;
-  USB0.BRDYENB.WORD = 1;
+  LINK_REG->DCPMAXP_b.MXPS = 64;
+  LINK_REG->INTENB0 = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP | USB_IS0_DVST | USB_IS0_CTRT |
+          (USE_SOF ? USB_IS0_SOFR : 0) | USB_IS0_RESM;
+  LINK_REG->BEMPENB = 1;
+  LINK_REG->BRDYENB = 1;
 
-  if (USB0.INTSTS0.BIT.VBSTS) {
+  if (LINK_REG->INTSTS0_b.VBSTS) {
     dcd_connect(rhport);
   }
 }
 
 void dcd_int_enable(uint8_t rhport)
 {
-  (void)rhport;
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  IEN(PERIB, INTB185) = 1;
-#else
-  IEN(USB0, USBI0) = 1;
-#endif
+  link_int_enable(rhport);
 }
 
 void dcd_int_disable(uint8_t rhport)
 {
-  (void)rhport;
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  IEN(PERIB, INTB185) = 0;
-#else
-  IEN(USB0, USBI0) = 0;
-#endif
+  link_int_disable(rhport);
 }
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
@@ -672,19 +579,19 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void)rhport;
-  USB0.DVSTCTR0.BIT.WKUP = 1;
+  LINK_REG->DVSTCTR0_b.WKUP = 1;
 }
 
 void dcd_connect(uint8_t rhport)
 {
   (void)rhport;
-  USB0.SYSCFG.BIT.DPRPU = 1;
+  LINK_REG->SYSCFG_b.DPRPU = 1;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
   (void)rhport;
-  USB0.SYSCFG.BIT.DPRPU = 0;
+  LINK_REG->SYSCFG_b.DPRPU = 0;
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -720,8 +627,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   /* setup pipe */
   dcd_int_disable(rhport);
-  USB0.PIPESEL.WORD  = num;
-  USB0.PIPEMAXP.WORD = mps;
+  LINK_REG->PIPESEL = num;
+  LINK_REG->PIPEMAXP = mps;
   volatile uint16_t *ctr = get_pipectr(num);
   *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
   *ctr = 0;
@@ -733,13 +640,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   } else {
     cfg |= (USB_PIPECFG_ISO | USB_PIPECFG_DBLB);
   }
-  USB0.PIPECFG.WORD  = cfg;
-  USB0.BRDYSTS.WORD  = 0x1FFu ^ TU_BIT(num);
-  USB0.BRDYENB.WORD |= TU_BIT(num);
+  LINK_REG->PIPECFG = cfg;
+  LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  LINK_REG->BRDYENB |= TU_BIT(num);
   if (dir || (xfer != TUSB_XFER_BULK)) {
     *ctr = USB_PIPECTR_PID_BUF;
   }
-  // TU_LOG1("O %d %x %x\r\n", USB0.PIPESEL.WORD, USB0.PIPECFG.WORD, USB0.PIPEMAXP.WORD);
+  // TU_LOG1("O %d %x %x\r\n", LINK_REG->PIPESEL, LINK_REG->PIPECFG, LINK_REG->PIPEMAXP);
   dcd_int_enable(rhport);
 
   return true;
@@ -764,11 +671,11 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   const unsigned dir = tu_edpt_dir(ep_addr);
   const unsigned num = _dcd.ep[dir][epn];
 
-  USB0.BRDYENB.WORD &= ~TU_BIT(num);
+  LINK_REG->BRDYENB &= ~TU_BIT(num);
   volatile uint16_t *ctr = get_pipectr(num);
   *ctr = 0;
-  USB0.PIPESEL.WORD = num;
-  USB0.PIPECFG.WORD = 0;
+  LINK_REG->PIPESEL = num;
+  LINK_REG->PIPECFG = 0;
   _dcd.pipe[num].ep = 0;
   _dcd.ep[dir][epn] = 0;
 }
@@ -815,8 +722,8 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
     *ctr = USB_PIPECTR_PID_BUF;
   } else {
     const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
-    USB0.PIPESEL.WORD  = num;
-    if (USB0.PIPECFG.BIT.TYPE != 1) {
+    LINK_REG->PIPESEL = num;
+    if (LINK_REG->PIPECFG_b.TYPE != 1) {
       *ctr = USB_PIPECTR_PID_BUF;
     }
   }
@@ -830,11 +737,11 @@ void dcd_int_handler(uint8_t rhport)
 {
   (void)rhport;
 
-  unsigned is0 = USB0.INTSTS0.WORD;
+  unsigned is0 = LINK_REG->INTSTS0;
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  USB0.INTSTS0.WORD = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID;
+  LINK_REG->INTSTS0 = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID;
   if (is0 & USB_IS0_VBINT) {
-    if (USB0.INTSTS0.BIT.VBSTS) {
+    if (LINK_REG->INTSTS0_b.VBSTS) {
       dcd_connect(rhport);
     } else {
       dcd_disconnect(rhport);
@@ -843,14 +750,14 @@ void dcd_int_handler(uint8_t rhport)
   if (is0 & USB_IS0_RESM) {
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
 #if (0==USE_SOF)
-    USB0.INTENB0.BIT.SOFE = 0;
+    LINK_REG->INTENB0_b.SOFE = 0;
 #endif
   }
-  if ((is0 & USB_IS0_SOFR) && USB0.INTENB0.BIT.SOFE) {
+  if ((is0 & USB_IS0_SOFR) && LINK_REG->INTENB0_b.SOFE) {
     // USBD will exit suspended mode when SOF event is received
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-#if (0==USE_SOF)
-    USB0.INTENB0.BIT.SOFE = 0;
+#if (0 == USE_SOF)
+    LINK_REG->INTENB0_b.SOFE = 0;
 #endif
   }
   if (is0 & USB_IS0_DVST) {
@@ -867,7 +774,7 @@ void dcd_int_handler(uint8_t rhport)
     case USB_IS0_DVSQ_SUSP3:
        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
 #if (0==USE_SOF)
-       USB0.INTENB0.BIT.SOFE = 1;
+      LINK_REG->INTENB0_b.SOFE = 1;
 #endif
     default:
       break;
@@ -883,17 +790,17 @@ void dcd_int_handler(uint8_t rhport)
     }
   }
   if (is0 & USB_IS0_BEMP) {
-    const unsigned s = USB0.BEMPSTS.WORD;
-    USB0.BEMPSTS.WORD = 0;
+    const unsigned s = LINK_REG->BEMPSTS;
+    LINK_REG->BEMPSTS = 0;
     if (s & 1) {
       process_pipe0_bemp(rhport);
     }
   }
   if (is0 & USB_IS0_BRDY) {
-    const unsigned m = USB0.BRDYENB.WORD;
-    unsigned s       = USB0.BRDYSTS.WORD & m;
+    const unsigned m = LINK_REG->BRDYENB;
+    unsigned s = LINK_REG->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    USB0.BRDYSTS.WORD = ~s;
+    LINK_REG->BRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       static const int Mod37BitPosition[] = {
diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c
index 5246ecb94..46a4aae8f 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/link/hcd_link.c
@@ -27,86 +27,28 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
-                               CFG_TUSB_MCU == OPT_MCU_RX65X || \
-                               CFG_TUSB_MCU == OPT_MCU_RX72N )
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N)
+
 #include "host/hcd.h"
-#include "iodefine.h"
+#include "link_type.h"
+
+#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+#include "link_rx.h"
+#else
+#error "Unsupported MCU"
+#endif
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
-#define SYSTEM_PRCR_PRC1     (1<<1)
-#define SYSTEM_PRCR_PRKEY    (0xA5u<<8)
 
-#define USB_DVSTCTR0_LOW     (1u)
-#define USB_DVSTCTR0_FULL    (2u)
+/* LINK core registers */
+#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE)
 
-#define USB_FIFOSEL_TX       ((uint16_t)(1u<<5))
-#define USB_FIFOSEL_BIGEND   ((uint16_t)(1u<<8))
-#define USB_FIFOSEL_MBW_8    ((uint16_t)(0u<<10))
-#define USB_FIFOSEL_MBW_16   ((uint16_t)(1u<<10))
-#define USB_IS0_CTSQ         ((uint16_t)(7u))
-#define USB_IS0_DVSQ         ((uint16_t)(7u<<4))
-#define USB_IS0_VALID        ((uint16_t)(1u<<3))
-#define USB_IS0_BRDY         ((uint16_t)(1u<<8))
-#define USB_IS0_NRDY         ((uint16_t)(1u<<9))
-#define USB_IS0_BEMP         ((uint16_t)(1u<<10))
-#define USB_IS0_CTRT         ((uint16_t)(1u<<11))
-#define USB_IS0_DVST         ((uint16_t)(1u<<12))
-#define USB_IS0_SOFR         ((uint16_t)(1u<<13))
-#define USB_IS0_RESM         ((uint16_t)(1u<<14))
-#define USB_IS0_VBINT        ((uint16_t)(1u<<15))
-#define USB_IS1_SACK         ((uint16_t)(1u<<4))
-#define USB_IS1_SIGN         ((uint16_t)(1u<<5))
-#define USB_IS1_EOFERR       ((uint16_t)(1u<<6))
-#define USB_IS1_ATTCH        ((uint16_t)(1u<<11))
-#define USB_IS1_DTCH         ((uint16_t)(1u<<12))
-#define USB_IS1_BCHG         ((uint16_t)(1u<<14))
-#define USB_IS1_OVRCR        ((uint16_t)(1u<<15))
-
-#define USB_IS0_CTSQ_MSK     (7u)
-#define USB_IS0_CTSQ_SETUP   (1u)
-#define USB_IS0_DVSQ_DEF     (1u<<4)
-#define USB_IS0_DVSQ_ADDR    (2u<<4)
-#define USB_IS0_DVSQ_SUSP0   (4u<<4)
-#define USB_IS0_DVSQ_SUSP1   (5u<<4)
-#define USB_IS0_DVSQ_SUSP2   (6u<<4)
-#define USB_IS0_DVSQ_SUSP3   (7u<<4)
-
-#define USB_PIPECTR_PID_MSK   (3u)
-#define USB_PIPECTR_PID_NAK   (0u)
-#define USB_PIPECTR_PID_BUF   (1u)
-#define USB_PIPECTR_PID_STALL (2u)
-#define USB_PIPECTR_CCPL      (1u<<2)
-#define USB_PIPECTR_SQMON     (1u<<6)
-#define USB_PIPECTR_SQCLR     (1u<<8)
-#define USB_PIPECTR_ACLRM     (1u<<9)
-#define USB_PIPECTR_INBUFM    (1u<<14)
-#define USB_PIPECTR_BSTS      (1u<<15)
-
-#define USB_FIFOCTR_DTLN     (0x1FF)
-#define USB_FIFOCTR_FRDY     (1u<<13)
-#define USB_FIFOCTR_BCLR     (1u<<14)
-#define USB_FIFOCTR_BVAL     (1u<<15)
-
-#define USB_PIPECFG_SHTNAK   (1u<<7)
-#define USB_PIPECFG_DBLB     (1u<<9)
-#define USB_PIPECFG_BULK     (1u<<14)
-#define USB_PIPECFG_ISO      (3u<<14)
-#define USB_PIPECFG_INT      (2u<<14)
-
-#define USB_DEVADD_LOW       (1u<<6)
-#define USB_DEVADD_FULL      (2u<<6)
-
-#define FIFO_REQ_CLR         (1u)
-#define FIFO_COMPLETE        (1u<<1)
-
-// Start of definition of packed structs (used by the CCRX toolchain)
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
-typedef struct {
+typedef struct TU_ATTR_PACKED {
   union {
     struct {
       uint16_t      : 8;
@@ -119,7 +61,7 @@ typedef struct {
   uint16_t TRN;
 } reg_pipetre_t;
 
-typedef union {
+typedef union TU_ATTR_PACKED {
   struct {
     volatile uint16_t u8: 8;
     volatile uint16_t   : 0;
@@ -127,8 +69,7 @@ typedef union {
   volatile uint16_t u16;
 } hw_fifo_t;
 
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   void      *buf;      /* the start address of a transfer data buffer */
   uint16_t  length;    /* the number of bytes in the buffer */
   uint16_t  remaining; /* the number of bytes remaining in the buffer */
@@ -156,28 +97,6 @@ typedef struct
 //--------------------------------------------------------------------+
 static hcd_data_t _hcd;
 
-static uint32_t disable_interrupt(void)
-{
-  uint32_t pswi;
-#if defined(__CCRX__)
-  pswi = get_psw() & 0x010000;
-  clrpsw_i();
-#else
-  pswi = __builtin_rx_mvfc(0) & 0x010000;
-  __builtin_rx_clrpsw('I');
-#endif
-  return pswi;
-}
-
-static void enable_interrupt(uint32_t pswi)
-{
-#if defined(__CCRX__)
-  set_psw(get_psw() | pswi);
-#else
-  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
-#endif
-}
-
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
@@ -208,58 +127,49 @@ static unsigned find_pipe(unsigned xfer)
 
 static volatile uint16_t* get_pipectr(unsigned num)
 {
-  volatile uint16_t *ctr = NULL;
   if (num) {
-    ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
-    ctr += num - 1;
+    return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]);
   } else {
-    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
+    return (volatile uint16_t*)&(LINK_REG->DCPCTR);
   }
-  return ctr;
 }
 
 static volatile reg_pipetre_t* get_pipetre(unsigned num)
 {
   volatile reg_pipetre_t* tre = NULL;
   if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD;
-    tre += num - 1;
+    tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E);
   }
   return tre;
 }
 
 static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr)
 {
-  volatile uint16_t *ctr = NULL;
-  const unsigned epn   = tu_edpt_number(ep_addr);
+  const unsigned epn = tu_edpt_number(ep_addr);
   if (epn) {
     const unsigned dir_in = tu_edpt_dir(ep_addr);
-    const unsigned num    = _hcd.ep[dev_addr][dir_in][epn - 1];
-    if (num) {
-      ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
-      ctr += num - 1;
-    }
+    const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1];
+    return get_pipectr(num);
   } else {
-    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
+    return get_pipectr(0);
   }
-  return ctr;
 }
 
 static unsigned edpt0_max_packet_size(void)
 {
-  return USB0.DCPMAXP.BIT.MXPS;
+  return LINK_REG->DCPMAXP_b.MXPS;
 }
 
 static unsigned edpt_max_packet_size(unsigned num)
 {
-  USB0.PIPESEL.WORD = num;
-  return USB0.PIPEMAXP.BIT.MXPS;
+  LINK_REG->PIPESEL = num;
+  return LINK_REG->PIPEMAXP_b.MXPS;
 }
 
 static inline void pipe_wait_for_ready(unsigned num)
 {
-  while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
-  while (!USB0.D0FIFOCTR.BIT.FRDY) ;
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ;
+  while (!LINK_REG->D0FIFOCTR_b.FRDY) ;
 }
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -290,21 +200,22 @@ static bool pipe0_xfer_in(void)
   const unsigned rem = pipe->remaining;
 
   const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = USB0.CFIFOCTR.BIT.DTLN;
+  const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN;
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
-    USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
-    pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
+    LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
+    pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
+  if (len < mps)
+    LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return true;
   }
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
+  LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF;
   return false;
 }
 
@@ -320,10 +231,11 @@ static bool pipe0_xfer_out(void)
   const unsigned len = TU_MIN(mps, rem);
   void          *buf = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
+    pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+  if (len < mps)
+    LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL;
   pipe->remaining = rem - len;
   return false;
 }
@@ -333,20 +245,21 @@ static bool pipe_xfer_in(unsigned num)
   pipe_state_t  *pipe = &_hcd.pipe[num];
   const unsigned rem  = pipe->remaining;
 
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
+  LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_8;
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
-  const unsigned vld  = USB0.D0FIFOCTR.BIT.DTLN;
+  const unsigned vld  = LINK_REG->D0FIFOCTR_b.DTLN;
   const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
+    pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  pipe->remaining     = rem - len;
+  if (len < mps)
+    LINK_REG->D0FIFOCTR = USB_FIFOCTR_BCLR;
+  LINK_REG->D0FIFOSEL = 0;
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return NULL != buf;
@@ -364,18 +277,19 @@ static bool pipe_xfer_out(unsigned num)
     return true;
   }
 
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
+  LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
   const unsigned len  = TU_MIN(rem, mps);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
+    pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  if (len < mps)
+    LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
+  LINK_REG->D0FIFOSEL = 0;
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   return false;
 }
@@ -387,11 +301,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
 
   /* configure fifo direction and access unit settings */
   if (dir_in) { /* IN, a byte */
-    USB0.CFIFOSEL.WORD  = USB_FIFOSEL_MBW_8;
-    while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
-  } else {       /* OUT, 2 bytes */
-    USB0.CFIFOSEL.WORD  = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
-    while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
+    LINK_REG->CFIFOSEL = USB_FIFOSEL_MBW_8;
+    while (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) ;
+  } else { /* OUT, 2 bytes */
+    LINK_REG->CFIFOSEL =
+      USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
+    while (!(LINK_REG->CFIFOSEL & USB_FIFOSEL_TX)) ;
   }
 
   pipe_state_t *pipe = &_hcd.pipe[0];
@@ -401,25 +316,25 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
   if (buflen) {
     pipe->buf     = buffer;
     if (!dir_in) { /* OUT */
-      TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
+      TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80));
       pipe0_xfer_out();
     }
   } else { /* ZLP */
     pipe->buf        = NULL;
     if (!dir_in) { /* OUT */
-      USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+      LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL;
     }
-    if (dir_in == USB0.DCPCFG.BIT.DIR) {
-      TU_ASSERT(USB_PIPECTR_PID_NAK == USB0.DCPCTR.BIT.PID);
-      USB0.DCPCTR.BIT.SQSET = 1;
-      USB0.DCPCFG.BIT.DIR = dir_in ^ 1;
+    if (dir_in == LINK_REG->DCPCFG_b.DIR) {
+      TU_ASSERT(USB_PIPECTR_PID_NAK == LINK_REG->DCPCTR_b.PID);
+      LINK_REG->DCPCTR_b.SQSET = 1;
+      LINK_REG->DCPCFG_b.DIR = dir_in ^ 1;
     }
   }
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
+  LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF;
   return true;
 }
 
-static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen)
 {
   const unsigned epn    = tu_edpt_number(ep_addr);
   const unsigned dir_in = tu_edpt_dir(ep_addr);
@@ -435,11 +350,11 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, u
     if (buflen) {
       pipe_xfer_out(num);
     } else { /* ZLP */
-      USB0.D0FIFOSEL.WORD = num;
+      LINK_REG->D0FIFOSEL = num;
       pipe_wait_for_ready(num);
-      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-      USB0.D0FIFOSEL.WORD = 0;
-      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+      LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
+      LINK_REG->D0FIFOSEL = 0;
+      while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
     }
   } else {
     volatile uint16_t     *ctr = get_pipectr(num);
@@ -520,69 +435,51 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
   }
 }
 
-
 /*------------------------------------------------------------------*/
 /* Host API
  *------------------------------------------------------------------*/
 bool hcd_init(uint8_t rhport)
 {
   (void)rhport;
-  /* Enable USB0 */
-  uint32_t pswi = disable_interrupt();
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(USB0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  enable_interrupt(pswi);
-  USB0.SYSCFG.BIT.SCKE = 1;
-  while (!USB0.SYSCFG.BIT.SCKE) ;
-  USB0.SYSCFG.BIT.DPRPU = 0;
-  USB0.SYSCFG.BIT.DRPD = 0;
-  USB0.SYSCFG.BIT.DCFM = 1;
 
-  USB0.DVSTCTR0.BIT.VBUSEN = 1;
+  LINK_REG->SYSCFG_b.SCKE = 1;
+  while (!LINK_REG->SYSCFG_b.SCKE) ;
+  LINK_REG->SYSCFG_b.DPRPU = 0;
+  LINK_REG->SYSCFG_b.DRPD = 0;
+  LINK_REG->SYSCFG_b.DCFM = 1;
 
-  USB0.SYSCFG.BIT.DRPD = 1;
+  LINK_REG->DVSTCTR0_b.VBUSEN = 1;
+
+  LINK_REG->SYSCFG_b.DRPD = 1;
   for (volatile int i = 0; i < 30000; ++i) ;
-  USB0.SYSCFG.BIT.USBE = 1;
+  LINK_REG->SYSCFG_b.USBE = 1;
 
-  USB.DPUSR0R.BIT.FIXPHY0 = 0u;    /* USB0 Transceiver Output fixed */
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  USB0.PHYSLEW.LONG = 0x5;
-  IR(PERIB, INTB185) = 0;
-#else
-  IR(USB0, USBI0)   = 0;
-#endif
+  // MCU specific PHY init
+  link_phy_init();
+
+  LINK_REG->PHYSLEW = 0x5;
+  LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
 
   /* Setup default control pipe */
-  USB0.DCPCFG.WORD  = USB_PIPECFG_SHTNAK;
-  USB0.DCPMAXP.WORD = 64;
-  USB0.INTENB0.WORD = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP;
-  USB0.INTENB1.WORD = USB_IS1_SACK | USB_IS1_SIGN |
-    USB_IS1_ATTCH | USB_IS1_DTCH;
-  USB0.BEMPENB.WORD = 1;
-  USB0.NRDYENB.WORD = 1;
-  USB0.BRDYENB.WORD = 1;
+  LINK_REG->DCPCFG = USB_PIPECFG_SHTNAK;
+  LINK_REG->DCPMAXP = 64;
+  LINK_REG->INTENB0 = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP;
+  LINK_REG->INTENB1 = USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH;
+  LINK_REG->BEMPENB = 1;
+  LINK_REG->NRDYENB = 1;
+  LINK_REG->BRDYENB = 1;
+
   return true;
 }
 
 void hcd_int_enable(uint8_t rhport)
 {
-  (void)rhport;
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  IEN(PERIB, INTB185) = 1;
-#else
-  IEN(USB0, USBI0) = 1;
-#endif
+  link_int_enable(rhport);
 }
 
 void hcd_int_disable(uint8_t rhport)
 {
-  (void)rhport;
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  IEN(PERIB, INTB185) = 0;
-#else
-  IEN(USB0, USBI0) = 0;
-#endif
+  link_int_disable(rhport);
 }
 
 uint32_t hcd_frame_number(uint8_t rhport)
@@ -591,7 +488,7 @@ uint32_t hcd_frame_number(uint8_t rhport)
   /* The device must be reset at least once after connection 
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
-  return USB0.FRMNUM.BIT.FRNM;
+  return LINK_REG->FRMNUM_b.FRNM;
 }
 
 /*--------------------------------------------------------------------+
@@ -600,23 +497,23 @@ uint32_t hcd_frame_number(uint8_t rhport)
 bool hcd_port_connect_status(uint8_t rhport)
 {
   (void)rhport;
-  return USB0.INTSTS1.BIT.ATTCH ? true: false;
+  return LINK_REG->INTSTS1_b.ATTCH ? true : false;
 }
 
 void hcd_port_reset(uint8_t rhport)
 {
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
-  while (USB0.DCPCTR.BIT.PBUSY) ;
+  LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
+  while (LINK_REG->DCPCTR_b.PBUSY) ;
   hcd_int_disable(rhport);
-  USB0.DVSTCTR0.BIT.UACT   = 0;
-  if (USB0.DCPCTR.BIT.SUREQ)
-    USB0.DCPCTR.BIT.SUREQCLR = 1;
+  LINK_REG->DVSTCTR0_b.UACT = 0;
+  if (LINK_REG->DCPCTR_b.SUREQ)
+    LINK_REG->DCPCTR_b.SUREQCLR = 1;
   hcd_int_enable(rhport);
   /* Reset should be asserted 10-20ms. */
-  USB0.DVSTCTR0.BIT.USBRST = 1;
+  LINK_REG->DVSTCTR0_b.USBRST = 1;
   for (volatile int i = 0; i < 2400000; ++i) ;
-  USB0.DVSTCTR0.BIT.USBRST = 0;
-  USB0.DVSTCTR0.BIT.UACT   = 1;
+  LINK_REG->DVSTCTR0_b.USBRST = 0;
+  LINK_REG->DVSTCTR0_b.UACT = 1;
   _hcd.need_reset = false;
 }
 
@@ -628,7 +525,7 @@ void hcd_port_reset_end(uint8_t rhport)
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   (void)rhport;
-  switch (USB0.DVSTCTR0.BIT.RHST) {
+  switch (LINK_REG->DVSTCTR0_b.RHST) {
     default: return TUSB_SPEED_INVALID;
     case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL;
     case USB_DVSTCTR0_LOW:  return TUSB_SPEED_LOW;
@@ -647,13 +544,13 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
     unsigned num = *ep;
     if (!num || dev_addr != _hcd.pipe[num].dev) continue;
 
-    ctr  = (uint16_t volatile*)&USB0.PIPE1CTR.WORD + num - 1;
+    ctr = (uint16_t volatile*)&LINK_REG->PIPE_CTR[num - 1];
     *ctr = 0;
-    USB0.NRDYENB.WORD &= ~TU_BIT(num);
-    USB0.BRDYENB.WORD &= ~TU_BIT(num);
-    USB0.PIPESEL.WORD  = num;
-    USB0.PIPECFG.WORD  = 0;
-    USB0.PIPEMAXP.WORD = 0;
+    LINK_REG->NRDYENB &= ~TU_BIT(num);
+    LINK_REG->BRDYENB &= ~TU_BIT(num);
+    LINK_REG->PIPESEL = num;
+    LINK_REG->PIPECFG = 0;
+    LINK_REG->PIPEMAXP = 0;
 
     _hcd.pipe[num].ep  = 0;
     _hcd.pipe[num].dev = 0;
@@ -667,36 +564,36 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void)rhport;
-  //  TU_LOG1("S %d %x\n", dev_addr, USB0.DCPCTR.WORD);
+  //  TU_LOG1("S %d %x\n", dev_addr, LINK_REG->DCPCTR);
 
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
-  TU_ASSERT(0 == USB0.DCPCTR.BIT.SUREQ);
+  TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ);
 
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
+  LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
 
-  _hcd.pipe[0].buf       = NULL;
-  _hcd.pipe[0].length    = 8;
+  _hcd.pipe[0].buf = NULL;
+  _hcd.pipe[0].length = 8;
   _hcd.pipe[0].remaining = 0;
-  _hcd.pipe[0].dev       = dev_addr;
+  _hcd.pipe[0].dev = dev_addr;
 
-  while (USB0.DCPCTR.BIT.PBUSY) ;
-  USB0.DCPMAXP.WORD      = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
+  while (LINK_REG->DCPCTR_b.PBUSY) ;
+  LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
 
   /* Set direction in advance for DATA stage */
   uint8_t const bmRequesttype = setup_packet[0];
-  USB0.DCPCFG.BIT.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
+  LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
 
   uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
-  USB0.USBREQ.WORD = tu_htole16(p[0]);
-  USB0.USBVAL      = p[1];
-  USB0.USBINDX     = p[2];
-  USB0.USBLENG     = p[3];
+  LINK_REG->USBREQ = tu_htole16(p[0]);
+  LINK_REG->USBVAL = p[1];
+  LINK_REG->USBINDX = p[2];
+  LINK_REG->USBLENG = p[3];
 
-  USB0.DCPCTR.BIT.SUREQ = 1;
+  LINK_REG->DCPCTR_b.SUREQ = 1;
   return true;
 }
 
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc)
 {
   (void)rhport;
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
@@ -705,13 +602,13 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   const unsigned epn     = tu_edpt_number(ep_addr);
   const unsigned mps     = tu_edpt_packet_size(ep_desc);
   if (0 == epn) {
-    USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
+    LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
     hcd_devtree_info_t devtree;
     hcd_devtree_get_info(dev_addr, &devtree);
-    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t)&USB0.DEVADD0.WORD;
+    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0];
     devadd += dev_addr;
-    while (USB0.DCPCTR.BIT.PBUSY) ;
-    USB0.DCPMAXP.WORD = (dev_addr << 12) | mps;
+    while (LINK_REG->DCPCTR_b.PBUSY) ;
+    LINK_REG->DCPMAXP = (dev_addr << 12) | mps;
     *devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW;
     _hcd.ctl_mps[dev_addr] = mps;
     return true;
@@ -731,8 +628,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 
   /* setup pipe */
   hcd_int_disable(rhport);
-  USB0.PIPESEL.WORD  = num;
-  USB0.PIPEMAXP.WORD = (dev_addr << 12) | mps;
+  LINK_REG->PIPESEL = num;
+  LINK_REG->PIPEMAXP = (dev_addr << 12) | mps;
   volatile uint16_t *ctr = get_pipectr(num);
   *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
   *ctr = 0;
@@ -744,10 +641,10 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   } else {
     cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
   }
-  USB0.PIPECFG.WORD  = cfg;
-  USB0.BRDYSTS.WORD  = 0x1FFu ^ TU_BIT(num);
-  USB0.NRDYENB.WORD |= TU_BIT(num);
-  USB0.BRDYENB.WORD |= TU_BIT(num);
+  LINK_REG->PIPECFG = cfg;
+  LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  LINK_REG->NRDYENB |= TU_BIT(num);
+  LINK_REG->BRDYENB |= TU_BIT(num);
   if (!dir_in) {
     *ctr = USB_PIPECTR_PID_BUF;
   }
@@ -799,52 +696,50 @@ void hcd_int_handler(uint8_t rhport)
     20, 8, 19, 18};
 #endif
 
-  unsigned is1 = USB0.INTSTS1.WORD;
-  unsigned is0 = USB0.INTSTS0.WORD;
+  unsigned is1 = LINK_REG->INTSTS1;
+  unsigned is0 = LINK_REG->INTSTS0;
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  USB0.INTSTS1.WORD = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1);
-  USB0.INTSTS0.WORD = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0);
+  LINK_REG->INTSTS1 = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1);
+  LINK_REG->INTSTS0 = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0);
   // TU_LOG1("IS %04x %04x\n", is0, is1);
-  is1 &= USB0.INTENB1.WORD;
-  is0 &= USB0.INTENB0.WORD;
+  is1 &= LINK_REG->INTENB1;
+  is0 &= LINK_REG->INTENB0;
 
   if (is1 & USB_IS1_SACK) {
     /* Set DATA1 in advance for the next transfer. */
-    USB0.DCPCTR.BIT.SQSET = 1;
-    hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
-                            tu_edpt_addr(0, TUSB_DIR_OUT),
-                            8, XFER_RESULT_SUCCESS, true);
+    LINK_REG->DCPCTR_b.SQSET = 1;
+    hcd_event_xfer_complete(
+      LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
   }
   if (is1 & USB_IS1_SIGN) {
-    hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
-                            tu_edpt_addr(0, TUSB_DIR_OUT),
-                            8, XFER_RESULT_FAILED, true);
+    hcd_event_xfer_complete(
+      LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
   }
   if (is1 & USB_IS1_ATTCH) {
-    USB0.DVSTCTR0.BIT.UACT = 1;
+    LINK_REG->DVSTCTR0_b.UACT = 1;
     _hcd.need_reset = true;
-    USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_ATTCH) | USB_IS1_DTCH;
+    LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~USB_IS1_ATTCH) | USB_IS1_DTCH;
     hcd_event_device_attach(rhport, true);
   }
   if (is1 & USB_IS1_DTCH) {
-    USB0.DVSTCTR0.BIT.UACT = 0;
-    if (USB0.DCPCTR.BIT.SUREQ)
-      USB0.DCPCTR.BIT.SUREQCLR = 1;
-    USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_DTCH) | USB_IS1_ATTCH;
+    LINK_REG->DVSTCTR0_b.UACT = 0;
+    if (LINK_REG->DCPCTR_b.SUREQ)
+      LINK_REG->DCPCTR_b.SUREQCLR = 1;
+    LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~USB_IS1_DTCH) | USB_IS1_ATTCH;
     hcd_event_device_remove(rhport, true);
   }
 
   if (is0 & USB_IS0_BEMP) {
-    const unsigned s = USB0.BEMPSTS.WORD;
-    USB0.BEMPSTS.WORD = 0;
+    const unsigned s = LINK_REG->BEMPSTS;
+    LINK_REG->BEMPSTS = 0;
     if (s & 1) {
       process_pipe0_bemp(rhport);
     }
   }
   if (is0 & USB_IS0_NRDY) {
-    const unsigned m = USB0.NRDYENB.WORD;
-    unsigned s       = USB0.NRDYSTS.WORD & m;
-    USB0.NRDYSTS.WORD = ~s;
+    const unsigned m = LINK_REG->NRDYENB;
+    unsigned s = LINK_REG->NRDYSTS & m;
+    LINK_REG->NRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       const unsigned num = Mod37BitPosition[(-s & s) % 37];
@@ -856,10 +751,10 @@ void hcd_int_handler(uint8_t rhport)
     }
   }
   if (is0 & USB_IS0_BRDY) {
-    const unsigned m = USB0.BRDYENB.WORD;
-    unsigned s       = USB0.BRDYSTS.WORD & m;
+    const unsigned m = LINK_REG->BRDYENB;
+    unsigned s = LINK_REG->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    USB0.BRDYSTS.WORD = ~s;
+    LINK_REG->BRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       const unsigned num = Mod37BitPosition[(-s & s) % 37];
diff --git a/src/portable/renesas/link/link_rx.h b/src/portable/renesas/link/link_rx.h
new file mode 100644
index 000000000..b15084bb3
--- /dev/null
+++ b/src/portable/renesas/link/link_rx.h
@@ -0,0 +1,76 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Koji Kitayama
+ * Portions copyrighted (c) 2021 Roland Winistoerfer
+ * Copyright (c) 2022 Rafael Silva (@perigoso)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _LINK_RX_H_
+#define _LINK_RX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "link_type.h"
+
+#include "iodefine.h"
+
+#define LINK_REG_BASE (0x000A0000)
+
+static inline void link_int_enable(uint8_t rhport)
+{
+	(void) rhport;
+#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
+	IEN(PERIB, INTB185) = 1;
+#else
+	IEN(USB0, USBI0) = 1;
+#endif
+}
+
+static inline void link_int_disable(uint8_t rhport)
+{
+	(void) rhport;
+#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
+	IEN(PERIB, INTB185) = 0;
+#else
+	IEN(USB0, USBI0) = 0;
+#endif
+}
+
+// MCU specific PHY init
+static inline void link_phy_init(void)
+{
+#if (CFG_TUSB_MCU == OPT_MCU_RX72N)
+	IR(PERIB, INTB185) = 0;
+#else
+	IR(USB0, USBI0) = 0;
+#endif
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LINK_RX_H_ */
diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/link/link_type.h
new file mode 100644
index 000000000..33cf7879e
--- /dev/null
+++ b/src/portable/renesas/link/link_type.h
@@ -0,0 +1,1658 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Rafael Silva (@perigoso)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_LINK_TYPE_H_
+#define _TUSB_LINK_TYPE_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+#define USB_DVSTCTR0_LOW  (1u)
+#define USB_DVSTCTR0_FULL (2u)
+
+#define USB_FIFOSEL_TX	   ((uint16_t) (1u << 5))
+#define USB_FIFOSEL_BIGEND ((uint16_t) (1u << 8))
+#define USB_FIFOSEL_MBW_8  ((uint16_t) (0u << 10))
+#define USB_FIFOSEL_MBW_16 ((uint16_t) (1u << 10))
+#define USB_IS0_CTSQ	   ((uint16_t) (7u))
+#define USB_IS0_DVSQ	   ((uint16_t) (7u << 4))
+#define USB_IS0_VALID	   ((uint16_t) (1u << 3))
+#define USB_IS0_BRDY	   ((uint16_t) (1u << 8))
+#define USB_IS0_NRDY	   ((uint16_t) (1u << 9))
+#define USB_IS0_BEMP	   ((uint16_t) (1u << 10))
+#define USB_IS0_CTRT	   ((uint16_t) (1u << 11))
+#define USB_IS0_DVST	   ((uint16_t) (1u << 12))
+#define USB_IS0_SOFR	   ((uint16_t) (1u << 13))
+#define USB_IS0_RESM	   ((uint16_t) (1u << 14))
+#define USB_IS0_VBINT	   ((uint16_t) (1u << 15))
+#define USB_IS1_SACK	   ((uint16_t) (1u << 4))
+#define USB_IS1_SIGN	   ((uint16_t) (1u << 5))
+#define USB_IS1_EOFERR	   ((uint16_t) (1u << 6))
+#define USB_IS1_ATTCH	   ((uint16_t) (1u << 11))
+#define USB_IS1_DTCH	   ((uint16_t) (1u << 12))
+#define USB_IS1_BCHG	   ((uint16_t) (1u << 14))
+#define USB_IS1_OVRCR	   ((uint16_t) (1u << 15))
+
+#define USB_IS0_CTSQ_MSK   (7u)
+#define USB_IS0_CTSQ_SETUP (1u)
+#define USB_IS0_DVSQ_DEF   (1u << 4)
+#define USB_IS0_DVSQ_ADDR  (2u << 4)
+#define USB_IS0_DVSQ_SUSP0 (4u << 4)
+#define USB_IS0_DVSQ_SUSP1 (5u << 4)
+#define USB_IS0_DVSQ_SUSP2 (6u << 4)
+#define USB_IS0_DVSQ_SUSP3 (7u << 4)
+
+#define USB_PIPECTR_PID_MSK   (3u)
+#define USB_PIPECTR_PID_NAK   (0u)
+#define USB_PIPECTR_PID_BUF   (1u)
+#define USB_PIPECTR_PID_STALL (2u)
+#define USB_PIPECTR_CCPL      (1u << 2)
+#define USB_PIPECTR_SQMON     (1u << 6)
+#define USB_PIPECTR_SQCLR     (1u << 8)
+#define USB_PIPECTR_ACLRM     (1u << 9)
+#define USB_PIPECTR_INBUFM    (1u << 14)
+#define USB_PIPECTR_BSTS      (1u << 15)
+
+#define USB_FIFOCTR_DTLN (0x1FF)
+#define USB_FIFOCTR_FRDY (1u << 13)
+#define USB_FIFOCTR_BCLR (1u << 14)
+#define USB_FIFOCTR_BVAL (1u << 15)
+
+#define USB_PIPECFG_SHTNAK (1u << 7)
+#define USB_PIPECFG_DBLB   (1u << 9)
+#define USB_PIPECFG_BULK   (1u << 14)
+#define USB_PIPECFG_ISO	   (3u << 14)
+#define USB_PIPECFG_INT	   (2u << 14)
+
+#define FIFO_REQ_CLR  (1u)
+#define FIFO_COMPLETE (1u << 1)
+
+#define USB_DEVADD_LOW	(1u << 6)
+#define USB_DEVADD_FULL (2u << 6)
+
+/*--------------------------------------------------------------------*/
+/* Register Definitions                                           */
+/*--------------------------------------------------------------------*/
+
+/* Start of definition of packed structs (used by the CCRX toolchain) */
+TU_ATTR_PACKED_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
+
+typedef struct TU_ATTR_PACKED {
+	union {
+		volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
+
+		struct {
+			uint16_t : 8;
+			volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
+			volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
+			uint16_t : 6;
+		} E_b;
+	};
+
+	union {
+		volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */
+
+		struct {
+			volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */
+		} N_b;
+	};
+} LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */
+
+TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size");
+
+/* LINK_REG Structure */
+typedef struct TU_ATTR_PACKED {
+	union {
+		volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
+
+		struct {
+			volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */
+			uint16_t : 2;
+			volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */
+			volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
+			volatile uint16_t DRPD : 1;  /* [5..5] D+/D- Line Resistor Control */
+			volatile uint16_t DCFM : 1;  /* [6..6] Controller Function Select */
+			uint16_t : 1;
+			volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */
+			uint16_t : 1;
+			volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */
+			uint16_t : 5;
+		} SYSCFG_b;
+	};
+
+	union {
+		volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */
+
+		struct {
+			volatile uint16_t
+				BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
+			uint16_t : 12;
+		} BUSWAIT_b;
+	};
+
+	union {
+		volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */
+
+		struct {
+			volatile const uint16_t LNST : 2;  /* [1..0] USB Data Line Status Monitor */
+			volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */
+			uint16_t : 2;
+			volatile const uint16_t
+				SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
+			volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */
+			uint16_t : 7;
+			volatile const uint16_t
+				OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
+		} SYSSTS0_b;
+	};
+
+	union {
+		volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */
+
+		struct {
+			volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
+			uint16_t : 15;
+		} PLLSTA_b;
+	};
+
+	union {
+		volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */
+
+		struct {
+			volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */
+			uint16_t : 1;
+			volatile uint16_t UACT : 1;    /* [4..4] USB Bus Enable */
+			volatile uint16_t RESUME : 1;  /* [5..5] Resume Output */
+			volatile uint16_t USBRST : 1;  /* [6..6] USB Bus Reset Output */
+			volatile uint16_t RWUPE : 1;   /* [7..7] Wakeup Detection Enable */
+			volatile uint16_t WKUP : 1;    /* [8..8] Wakeup Output */
+			volatile uint16_t VBUSEN : 1;  /* [9..9] USB_VBUSEN Output Pin Control */
+			volatile uint16_t EXICEN : 1;  /* [10..10] USB_EXICEN Output Pin Control */
+			volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */
+			uint16_t : 4;
+		} DVSTCTR0_b;
+	};
+	volatile const uint16_t RESERVED;
+
+	union {
+		volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */
+
+		struct {
+			volatile uint16_t UTST : 4; /* [3..0] Test Mode */
+			uint16_t : 12;
+		} TESTMODE_b;
+	};
+	volatile const uint16_t RESERVED1;
+	volatile const uint32_t RESERVED2;
+
+	union {
+		volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */
+
+		struct {
+			union {
+				volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */
+				volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */
+			};
+
+			union {
+				volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */
+
+				struct {
+					volatile const uint8_t RESERVED3;
+					volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */
+				};
+			};
+		};
+	};
+
+	union {
+		volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */
+
+		struct {
+			union {
+				volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */
+				volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */
+			};
+
+			union {
+				volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */
+
+				struct {
+					volatile const uint8_t RESERVED4;
+					volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */
+				};
+			};
+		};
+	};
+
+	union {
+		volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */
+
+		struct {
+			union {
+				volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */
+				volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */
+			};
+
+			union {
+				volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */
+
+				struct {
+					volatile const uint8_t RESERVED5;
+					volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */
+				};
+			};
+		};
+	};
+
+	union {
+		volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */
+
+		struct {
+			volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */
+			uint16_t : 1;
+			volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */
+			uint16_t : 2;
+			volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */
+			uint16_t : 1;
+			volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */
+			uint16_t : 2;
+			volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
+			volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+		} CFIFOSEL_b;
+	};
+
+	union {
+		volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */
+
+		struct {
+			volatile const uint16_t
+				DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+			uint16_t : 1;
+			volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
+			volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+			volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+		} CFIFOCTR_b;
+	};
+	volatile const uint32_t RESERVED6;
+
+	union {
+		volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */
+
+		struct {
+			volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
+			uint16_t : 4;
+			volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
+			uint16_t : 1;
+			volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
+			volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
+			volatile uint16_t
+				DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
+			volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
+			volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+		} D0FIFOSEL_b;
+	};
+
+	union {
+		volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */
+
+		struct {
+			volatile const uint16_t
+				DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+			uint16_t : 1;
+			volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
+			volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+			volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+		} D0FIFOCTR_b;
+	};
+
+	union {
+		volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */
+
+		struct {
+			volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
+			uint16_t : 4;
+			volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
+			uint16_t : 1;
+			volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
+			volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
+			volatile uint16_t
+				DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
+			volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
+			volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+		} D1FIFOSEL_b;
+	};
+
+	union {
+		volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */
+
+		struct {
+			volatile const uint16_t
+				DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+			uint16_t : 1;
+			volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
+			volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+			volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+		} D1FIFOCTR_b;
+	};
+
+	union {
+		volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
+
+		struct {
+			uint16_t : 8;
+			volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
+			volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
+			volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
+			volatile uint16_t CTRE : 1;  /* [11..11] Control Transfer Stage Transition Interrupt Enable */
+			volatile uint16_t DVSE : 1;  /* [12..12] Device State Transition Interrupt Enable */
+			volatile uint16_t SOFE : 1;  /* [13..13] Frame Number Update Interrupt Enable */
+			volatile uint16_t RSME : 1;  /* [14..14] Resume Interrupt Enable */
+			volatile uint16_t VBSE : 1;  /* [15..15] VBUS Interrupt Enable */
+		} INTENB0_b;
+	};
+
+	union {
+		volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */
+
+		struct {
+			volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */
+			uint16_t : 3;
+			volatile uint16_t SACKE : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Enable */
+			volatile uint16_t SIGNE : 1;   /* [5..5] Setup Transaction Error Interrupt Enable */
+			volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */
+			uint16_t : 4;
+			volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */
+			volatile uint16_t DTCHE : 1;  /* [12..12] Disconnection Detection Interrupt Enable */
+			uint16_t : 1;
+			volatile uint16_t BCHGE : 1;  /* [14..14] USB Bus Change Interrupt Enable */
+			volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */
+		} INTENB1_b;
+	};
+	volatile const uint16_t RESERVED7;
+
+	union {
+		volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */
+
+		struct {
+			volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */
+			uint16_t : 6;
+		} BRDYENB_b;
+	};
+
+	union {
+		volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */
+
+		struct {
+			volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */
+			volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */
+			uint16_t : 6;
+		} NRDYENB_b;
+	};
+
+	union {
+		volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */
+
+		struct {
+			volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */
+			volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */
+			volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */
+			volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */
+			volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */
+			volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */
+			volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */
+			volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */
+			volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */
+			volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */
+			uint16_t : 6;
+		} BEMPENB_b;
+	};
+
+	union {
+		volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */
+
+		struct {
+			uint16_t : 4;
+			volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */
+			volatile uint16_t INTL : 1;	     /* [5..5] Interrupt Output Sense Select */
+			volatile uint16_t BRDYM : 1;	     /* [6..6] BRDY Interrupt Status Clear Timing */
+			uint16_t : 1;
+			volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */
+			uint16_t : 7;
+		} SOFCFG_b;
+	};
+
+	union {
+		volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */
+
+		struct {
+			volatile uint16_t DIRPD : 1;	/* [0..0] Power-Down Control */
+			volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */
+			uint16_t : 1;
+			volatile uint16_t CDPEN : 1;  /* [3..3] Charging Downstream Port Enable */
+			volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */
+			uint16_t : 2;
+			volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */
+			uint16_t : 1;
+			volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */
+			uint16_t : 3;
+			volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */
+		} PHYSET_b;
+	};
+
+	union {
+		volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */
+
+		struct {
+			volatile const uint16_t CTSQ : 3;  /* [2..0] Control Transfer Stage */
+			volatile uint16_t VALID : 1;	   /* [3..3] USB Request Reception */
+			volatile const uint16_t DVSQ : 3;  /* [6..4] Device State */
+			volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */
+			volatile const uint16_t BRDY : 1;  /* [8..8] Buffer Ready Interrupt Status */
+			volatile const uint16_t NRDY : 1;  /* [9..9] Buffer Not Ready Interrupt Status */
+			volatile const uint16_t BEMP : 1;  /* [10..10] Buffer Empty Interrupt Status */
+			volatile uint16_t CTRT : 1;	   /* [11..11] Control Transfer Stage Transition Interrupt Status */
+			volatile uint16_t DVST : 1;	   /* [12..12] Device State Transition Interrupt Status */
+			volatile uint16_t SOFR : 1;	   /* [13..13] Frame Number Refresh Interrupt Status */
+			volatile uint16_t RESM : 1;	   /* [14..14] Resume Interrupt Status */
+			volatile uint16_t VBINT : 1;	   /* [15..15] VBUS Interrupt Status */
+		} INTSTS0_b;
+	};
+
+	union {
+		volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */
+
+		struct {
+			volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */
+			uint16_t : 3;
+			volatile uint16_t SACK : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Status */
+			volatile uint16_t SIGN : 1;   /* [5..5] Setup Transaction Error Interrupt Status */
+			volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */
+			uint16_t : 1;
+			volatile uint16_t LPMEND : 1;	/* [8..8] LPM Transaction End Interrupt Status */
+			volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */
+			uint16_t : 1;
+			volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */
+			volatile uint16_t DTCH : 1;  /* [12..12] USB Disconnection Detection Interrupt Status */
+			uint16_t : 1;
+			volatile uint16_t BCHG : 1;  /* [14..14] USB Bus Change Interrupt Status */
+			volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */
+		} INTSTS1_b;
+	};
+	volatile const uint16_t RESERVED8;
+
+	union {
+		volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */
+
+		struct {
+			volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */
+			uint16_t : 6;
+		} BRDYSTS_b;
+	};
+
+	union {
+		volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */
+
+		struct {
+			volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */
+			volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */
+			uint16_t : 6;
+		} NRDYSTS_b;
+	};
+
+	union {
+		volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */
+
+		struct {
+			volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */
+			volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */
+			volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */
+			volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */
+			volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */
+			volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */
+			volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */
+			volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */
+			volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */
+			volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */
+			uint16_t : 6;
+		} BEMPSTS_b;
+	};
+
+	union {
+		volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */
+
+		struct {
+			volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */
+			uint16_t : 3;
+			volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */
+			volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */
+		} FRMNUM_b;
+	};
+
+	union {
+		volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */
+
+		struct {
+			volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */
+			uint16_t : 12;
+			volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */
+		} UFRMNUM_b;
+	};
+
+	union {
+		volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */
+
+		struct {
+			volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */
+			uint16_t : 1;
+			volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */
+			uint16_t : 5;
+		} USBADDR_b;
+	};
+	volatile const uint16_t RESERVED9;
+
+	union {
+		volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */
+
+		struct {
+			volatile uint16_t
+				BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
+			volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
+		} USBREQ_b;
+	};
+
+	union {
+		volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */
+
+		struct {
+			volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */
+		} USBVAL_b;
+	};
+
+	union {
+		volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */
+
+		struct {
+			volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */
+		} USBINDX_b;
+	};
+
+	union {
+		volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */
+
+		struct {
+			volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */
+		} USBLENG_b;
+	};
+
+	union {
+		volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */
+
+		struct {
+			uint16_t : 4;
+			volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */
+			uint16_t : 2;
+			volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
+			volatile uint16_t CNTMD : 1;  /* [8..8] Continuous Transfer Mode */
+			uint16_t : 7;
+		} DCPCFG_b;
+	};
+
+	union {
+		volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */
+
+		struct {
+			volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */
+			uint16_t : 5;
+			volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
+		} DCPMAXP_b;
+	};
+
+	union {
+		volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */
+
+		struct {
+			volatile uint16_t PID : 2;  /* [1..0] Response PID */
+			volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */
+			uint16_t : 2;
+			volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
+			volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */
+			volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
+			volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
+			uint16_t : 2;
+			volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */
+			uint16_t : 2;
+			volatile uint16_t SUREQ : 1;	  /* [14..14] Setup Token Transmission */
+			volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */
+		} DCPCTR_b;
+	};
+	volatile const uint16_t RESERVED10;
+
+	union {
+		volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */
+
+		struct {
+			volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
+			uint16_t : 12;
+		} PIPESEL_b;
+	};
+	volatile const uint16_t RESERVED11;
+
+	union {
+		volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */
+
+		struct {
+			volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */
+			volatile uint16_t DIR : 1;   /* [4..4] Transfer Direction */
+			uint16_t : 2;
+			volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
+			uint16_t : 1;
+			volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */
+			volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */
+			uint16_t : 3;
+			volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */
+		} PIPECFG_b;
+	};
+	volatile const uint16_t RESERVED12;
+
+	union {
+		volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
+
+		struct {
+			volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */
+			uint16_t : 3;
+			volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
+		} PIPEMAXP_b;
+	};
+
+	union {
+		volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */
+
+		struct {
+			volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */
+			uint16_t : 9;
+			volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */
+			uint16_t : 3;
+		} PIPEPERI_b;
+	};
+
+	union {
+		volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */
+
+		struct {
+			volatile uint16_t PID : 2; /* [1..0] Response PID */
+			uint16_t : 3;
+			volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
+			volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */
+			volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
+			volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
+			volatile uint16_t ACLRM : 1;	   /* [9..9] Auto Buffer Clear Mode */
+			volatile uint16_t ATREPM : 1;	   /* [10..10] Auto Response Mode */
+			uint16_t : 1;
+			volatile const uint16_t CSSTS : 1;  /* [12..12] CSSTS Status */
+			volatile uint16_t CSCLR : 1;	    /* [13..13] CSPLIT Status Clear */
+			volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */
+			volatile const uint16_t BSTS : 1;   /* [15..15] Buffer Status */
+		} PIPE_CTR_b[9];
+	};
+	volatile const uint16_t RESERVED13;
+	volatile const uint32_t RESERVED14[3];
+	volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */
+	volatile const uint32_t RESERVED15[3];
+
+	union {
+		volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */
+
+		struct {
+			volatile uint16_t RPDME0 : 1;	/* [0..0] D- Pin Pull-Down Control */
+			volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */
+			volatile uint16_t
+				IDMSINKE0 : 1;		/* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
+			volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
+			volatile uint16_t
+				IDPSINKE0 : 1;		/* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
+			volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
+			uint16_t : 1;
+			volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
+			volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */
+			volatile const uint16_t PDDETSTS0 : 1;	/* [9..9] D+ Pin 0.6 V Input Detection Status */
+			uint16_t : 6;
+		} USBBCCTRL0_b;
+	};
+	volatile const uint16_t RESERVED16;
+	volatile const uint32_t RESERVED17[4];
+
+	union {
+		volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */
+
+		struct {
+			volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
+			uint16_t : 15;
+		} UCKSEL_b;
+	};
+	volatile const uint16_t RESERVED18;
+	volatile const uint32_t RESERVED19;
+
+	union {
+		volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */
+
+		struct {
+			volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */
+			uint16_t : 6;
+			volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */
+			uint16_t : 8;
+		} USBMC_b;
+	};
+	volatile const uint16_t RESERVED20;
+
+	union {
+		volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
+
+		struct {
+			uint16_t : 6;
+			volatile uint16_t USBSPD : 2;  /* [7..6] Transfer Speed of Communication Target Device */
+			volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
+			volatile uint16_t UPPHUB : 4;  /* [14..11] Communication Target Connecting Hub Register */
+			uint16_t : 1;
+		} DEVADD_b[10];
+	};
+	volatile const uint32_t RESERVED21[3];
+
+	union {
+		volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */
+
+		struct {
+			volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */
+			volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
+			volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
+			volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */
+			uint32_t : 28;
+		} PHYSLEW_b;
+	};
+	volatile const uint32_t RESERVED22[3];
+
+	union {
+		volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
+
+		struct {
+			uint16_t : 7;
+			volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
+			uint16_t : 8;
+		} LPCTRL_b;
+	};
+
+	union {
+		volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
+
+		struct {
+			uint16_t : 14;
+			volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
+			uint16_t : 1;
+		} LPSTS_b;
+	};
+	volatile const uint32_t RESERVED23[15];
+
+	union {
+		volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */
+
+		struct {
+			volatile uint16_t IDPSRCE : 1;	/* [0..0] IDPSRC Control */
+			volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */
+			volatile uint16_t VDPSRCE : 1;	/* [2..2] VDPSRC Control */
+			volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */
+			volatile uint16_t VDMSRCE : 1;	/* [4..4] VDMSRC Control */
+			volatile uint16_t DCPMODE : 1;	/* [5..5] DCP Mode Control */
+			uint16_t : 2;
+			volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
+			volatile const uint16_t PDDETSTS : 1;  /* [9..9] PDDET Status */
+			uint16_t : 6;
+		} BCCTRL_b;
+	};
+	volatile const uint16_t RESERVED24;
+
+	union {
+		volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */
+
+		struct {
+			volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */
+			volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */
+			volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */
+			volatile const uint16_t
+				DVSQ : 4;	       /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
+			volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */
+			uint16_t : 2;
+			volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */
+			uint16_t : 1;
+		} PL1CTRL1_b;
+	};
+
+	union {
+		volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
+
+		struct {
+			uint16_t : 8;
+			volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
+			volatile uint16_t RWEMON : 1;  /* [12..12] RWE Value Monitor */
+			uint16_t : 3;
+		} PL1CTRL2_b;
+	};
+
+	union {
+		volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */
+
+		struct {
+			volatile uint16_t L1REQ : 1;	      /* [0..0] L1 Transition Request */
+			volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
+			uint16_t : 13;
+		} HL1CTRL1_b;
+	};
+
+	union {
+		volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */
+
+		struct {
+			volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */
+			uint16_t : 4;
+			volatile uint16_t HIRD : 4;  /* [11..8] LPM Token HIRD */
+			volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */
+			uint16_t : 2;
+			volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */
+		} HL1CTRL2_b;
+	};
+	volatile const uint32_t RESERVED25[5];
+
+	union {
+		volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
+
+		struct {
+			uint32_t : 20;
+			volatile const uint32_t
+				DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
+			volatile const uint32_t
+				DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
+			uint32_t : 1;
+			volatile const uint32_t
+				DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
+			uint32_t : 8;
+		} DPUSR0R_b;
+	};
+
+	union {
+		volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
+
+		struct {
+			uint32_t : 4;
+			volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
+			volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
+			uint32_t : 1;
+			volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */
+			uint32_t : 12;
+			volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */
+			volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
+			uint32_t : 1;
+			volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
+			uint32_t : 8;
+		} DPUSR1R_b;
+	};
+
+	union {
+		volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
+
+		struct {
+			volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */
+			volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */
+			uint16_t : 2;
+			volatile const uint16_t
+				DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
+			volatile const uint16_t
+				DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
+			uint16_t : 2;
+			volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */
+			volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */
+			uint16_t : 6;
+		} DPUSR2R_b;
+	};
+
+	union {
+		volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
+
+		struct {
+			volatile uint16_t FIXPHY : 1;	/* [0..0] USB Transceiver Control Fix */
+			volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
+			uint16_t : 14;
+		} DPUSRCR_b;
+	};
+	volatile const uint32_t RESERVED26[165];
+
+	union {
+		volatile uint32_t
+			DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */
+
+		struct {
+			volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */
+			volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */
+			uint32_t : 1;
+			volatile uint32_t DRPD0 : 1;   /* [3..3] D+/D- Pull-Down Resistor Control */
+			volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */
+			uint32_t : 11;
+			volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
+			volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */
+			uint32_t : 2;
+			volatile const uint32_t
+				DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
+			volatile const uint32_t
+				DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
+			uint32_t : 1;
+			volatile const uint32_t
+				DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
+			uint32_t : 8;
+		} DPUSR0R_FS_b;
+	};
+
+	union {
+		volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */
+
+		struct {
+			volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */
+			volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */
+			uint32_t : 2;
+			volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */
+			volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */
+			uint32_t : 1;
+			volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */
+			uint32_t : 8;
+			volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */
+			volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */
+			uint32_t : 2;
+			volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */
+			volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
+			uint32_t : 1;
+			volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
+			uint32_t : 8;
+		} DPUSR1R_FS_b;
+	};
+} LINK_REG_t; /* Size = 1032 (0x408) */
+
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG) == 0x00000000, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT) == 0x00000002, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0) == 0x00000004, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA) == 0x00000006, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0) == 0x00000008, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE) == 0x0000000C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO) == 0x00000014, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO) == 0x00000018, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO) == 0x0000001C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL) == 0x00000020, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR) == 0x00000022, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL) == 0x00000028, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR) == 0x0000002A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL) == 0x0000002C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR) == 0x0000002E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0) == 0x00000030, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1) == 0x00000032, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB) == 0x00000036, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB) == 0x00000038, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB) == 0x0000003A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG) == 0x0000003C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET) == 0x0000003E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0) == 0x00000040, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1) == 0x00000042, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS) == 0x00000046, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS) == 0x00000048, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS) == 0x0000004A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM) == 0x0000004C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM) == 0x0000004E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR) == 0x00000050, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ) == 0x00000054, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL) == 0x00000056, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX) == 0x00000058, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG) == 0x0000005A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG) == 0x0000005C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP) == 0x0000005E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR) == 0x00000060, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL) == 0x00000064, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG) == 0x00000068, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP) == 0x0000006C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI) == 0x0000006E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR) == 0x00000070, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR) == 0x00000090, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0) == 0x000000B0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL) == 0x000000C4, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC) == 0x000000CC, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD) == 0x000000D0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW) == 0x000000F0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL) == 0x00000100, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS) == 0x00000102, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL) == 0x00000140, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1) == 0x00000144, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2) == 0x00000146, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1) == 0x00000148, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2) == 0x0000014A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R) == 0x00000160, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R) == 0x00000164, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R) == 0x00000168, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR) == 0x0000016A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS) == 0x00000400, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS) == 0x00000404, "incorrect offset");
+
+TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
+	TU_ATTR_BIT_FIELD_ORDER_END
+
+/*--------------------------------------------------------------------*/
+/* Register Bit Definitions                                           */
+/*--------------------------------------------------------------------*/
+
+/* PIPE_TR */
+/* E */
+#define LINK_REG_PIPE_TR_E_TRENB_Pos (9UL)     /* TRENB (Bit 9) */
+#define LINK_REG_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_TR_E_TRCLR_Pos (8UL)     /* TRCLR (Bit 8) */
+#define LINK_REG_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */
+/* N */
+#define LINK_REG_PIPE_TR_N_TRNCNT_Pos (0UL)	 /* TRNCNT (Bit 0) */
+#define LINK_REG_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */
+
+/* LINK_REG */
+/* SYSCFG */
+#define LINK_REG_SYSCFG_SCKE_Pos  (10UL)    /* SCKE (Bit 10) */
+#define LINK_REG_SYSCFG_SCKE_Msk  (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_CNEN_Pos  (8UL)	    /* CNEN (Bit 8) */
+#define LINK_REG_SYSCFG_CNEN_Msk  (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_DCFM_Pos  (6UL)	    /* DCFM (Bit 6) */
+#define LINK_REG_SYSCFG_DCFM_Msk  (0x40UL)  /* DCFM (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_DRPD_Pos  (5UL)	    /* DRPD (Bit 5) */
+#define LINK_REG_SYSCFG_DRPD_Msk  (0x20UL)  /* DRPD (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_DPRPU_Pos (4UL)	    /* DPRPU (Bit 4) */
+#define LINK_REG_SYSCFG_DPRPU_Msk (0x10UL)  /* DPRPU (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_DMRPU_Pos (3UL)	    /* DMRPU (Bit 3) */
+#define LINK_REG_SYSCFG_DMRPU_Msk (0x8UL)   /* DMRPU (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_USBE_Pos  (0UL)	    /* USBE (Bit 0) */
+#define LINK_REG_SYSCFG_USBE_Msk  (0x1UL)   /* USBE (Bitfield-Mask: 0x01) */
+/* BUSWAIT */
+#define LINK_REG_BUSWAIT_BWAIT_Pos (0UL)   /* BWAIT (Bit 0) */
+#define LINK_REG_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */
+/* SYSSTS0 */
+#define LINK_REG_SYSSTS0_OVCMON_Pos (14UL)     /* OVCMON (Bit 14) */
+#define LINK_REG_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */
+#define LINK_REG_SYSSTS0_HTACT_Pos  (6UL)      /* HTACT (Bit 6) */
+#define LINK_REG_SYSSTS0_HTACT_Msk  (0x40UL)   /* HTACT (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSSTS0_SOFEA_Pos  (5UL)      /* SOFEA (Bit 5) */
+#define LINK_REG_SYSSTS0_SOFEA_Msk  (0x20UL)   /* SOFEA (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSSTS0_IDMON_Pos  (2UL)      /* IDMON (Bit 2) */
+#define LINK_REG_SYSSTS0_IDMON_Msk  (0x4UL)    /* IDMON (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSSTS0_LNST_Pos   (0UL)      /* LNST (Bit 0) */
+#define LINK_REG_SYSSTS0_LNST_Msk   (0x3UL)    /* LNST (Bitfield-Mask: 0x03) */
+/* PLLSTA */
+#define LINK_REG_PLLSTA_PLLLOCK_Pos (0UL)   /* PLLLOCK (Bit 0) */
+#define LINK_REG_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */
+/* DVSTCTR0 */
+#define LINK_REG_DVSTCTR0_HNPBTOA_Pos (11UL)	/* HNPBTOA (Bit 11) */
+#define LINK_REG_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_EXICEN_Pos  (10UL)	/* EXICEN (Bit 10) */
+#define LINK_REG_DVSTCTR0_EXICEN_Msk  (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_VBUSEN_Pos  (9UL)	/* VBUSEN (Bit 9) */
+#define LINK_REG_DVSTCTR0_VBUSEN_Msk  (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_WKUP_Pos    (8UL)	/* WKUP (Bit 8) */
+#define LINK_REG_DVSTCTR0_WKUP_Msk    (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_RWUPE_Pos   (7UL)	/* RWUPE (Bit 7) */
+#define LINK_REG_DVSTCTR0_RWUPE_Msk   (0x80UL)	/* RWUPE (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_USBRST_Pos  (6UL)	/* USBRST (Bit 6) */
+#define LINK_REG_DVSTCTR0_USBRST_Msk  (0x40UL)	/* USBRST (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_RESUME_Pos  (5UL)	/* RESUME (Bit 5) */
+#define LINK_REG_DVSTCTR0_RESUME_Msk  (0x20UL)	/* RESUME (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_UACT_Pos    (4UL)	/* UACT (Bit 4) */
+#define LINK_REG_DVSTCTR0_UACT_Msk    (0x10UL)	/* UACT (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_RHST_Pos    (0UL)	/* RHST (Bit 0) */
+#define LINK_REG_DVSTCTR0_RHST_Msk    (0x7UL)	/* RHST (Bitfield-Mask: 0x07) */
+/* TESTMODE */
+#define LINK_REG_TESTMODE_UTST_Pos (0UL)   /* UTST (Bit 0) */
+#define LINK_REG_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */
+/* CFIFOSEL */
+#define LINK_REG_CFIFOSEL_RCNT_Pos    (15UL)	 /* RCNT (Bit 15) */
+#define LINK_REG_CFIFOSEL_RCNT_Msk    (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOSEL_REW_Pos     (14UL)	 /* REW (Bit 14) */
+#define LINK_REG_CFIFOSEL_REW_Msk     (0x4000UL) /* REW (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOSEL_MBW_Pos     (10UL)	 /* MBW (Bit 10) */
+#define LINK_REG_CFIFOSEL_MBW_Msk     (0xc00UL)	 /* MBW (Bitfield-Mask: 0x03) */
+#define LINK_REG_CFIFOSEL_BIGEND_Pos  (8UL)	 /* BIGEND (Bit 8) */
+#define LINK_REG_CFIFOSEL_BIGEND_Msk  (0x100UL)	 /* BIGEND (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOSEL_ISEL_Pos    (5UL)	 /* ISEL (Bit 5) */
+#define LINK_REG_CFIFOSEL_ISEL_Msk    (0x20UL)	 /* ISEL (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOSEL_CURPIPE_Pos (0UL)	 /* CURPIPE (Bit 0) */
+#define LINK_REG_CFIFOSEL_CURPIPE_Msk (0xfUL)	 /* CURPIPE (Bitfield-Mask: 0x0f) */
+/* CFIFOCTR */
+#define LINK_REG_CFIFOCTR_BVAL_Pos (15UL)     /* BVAL (Bit 15) */
+#define LINK_REG_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOCTR_BCLR_Pos (14UL)     /* BCLR (Bit 14) */
+#define LINK_REG_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOCTR_FRDY_Pos (13UL)     /* FRDY (Bit 13) */
+#define LINK_REG_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOCTR_DTLN_Pos (0UL)      /* DTLN (Bit 0) */
+#define LINK_REG_CFIFOCTR_DTLN_Msk (0xfffUL)  /* DTLN (Bitfield-Mask: 0xfff) */
+/* D0FIFOSEL */
+#define LINK_REG_D0FIFOSEL_RCNT_Pos    (15UL)	  /* RCNT (Bit 15) */
+#define LINK_REG_D0FIFOSEL_RCNT_Msk    (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOSEL_REW_Pos     (14UL)	  /* REW (Bit 14) */
+#define LINK_REG_D0FIFOSEL_REW_Msk     (0x4000UL) /* REW (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOSEL_DCLRM_Pos   (13UL)	  /* DCLRM (Bit 13) */
+#define LINK_REG_D0FIFOSEL_DCLRM_Msk   (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOSEL_DREQE_Pos   (12UL)	  /* DREQE (Bit 12) */
+#define LINK_REG_D0FIFOSEL_DREQE_Msk   (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOSEL_MBW_Pos     (10UL)	  /* MBW (Bit 10) */
+#define LINK_REG_D0FIFOSEL_MBW_Msk     (0xc00UL)  /* MBW (Bitfield-Mask: 0x03) */
+#define LINK_REG_D0FIFOSEL_BIGEND_Pos  (8UL)	  /* BIGEND (Bit 8) */
+#define LINK_REG_D0FIFOSEL_BIGEND_Msk  (0x100UL)  /* BIGEND (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOSEL_CURPIPE_Pos (0UL)	  /* CURPIPE (Bit 0) */
+#define LINK_REG_D0FIFOSEL_CURPIPE_Msk (0xfUL)	  /* CURPIPE (Bitfield-Mask: 0x0f) */
+/* D0FIFOCTR */
+#define LINK_REG_D0FIFOCTR_BVAL_Pos (15UL)     /* BVAL (Bit 15) */
+#define LINK_REG_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOCTR_BCLR_Pos (14UL)     /* BCLR (Bit 14) */
+#define LINK_REG_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOCTR_FRDY_Pos (13UL)     /* FRDY (Bit 13) */
+#define LINK_REG_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOCTR_DTLN_Pos (0UL)      /* DTLN (Bit 0) */
+#define LINK_REG_D0FIFOCTR_DTLN_Msk (0xfffUL)  /* DTLN (Bitfield-Mask: 0xfff) */
+/* D1FIFOSEL */
+#define LINK_REG_D1FIFOSEL_RCNT_Pos    (15UL)	  /* RCNT (Bit 15) */
+#define LINK_REG_D1FIFOSEL_RCNT_Msk    (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOSEL_REW_Pos     (14UL)	  /* REW (Bit 14) */
+#define LINK_REG_D1FIFOSEL_REW_Msk     (0x4000UL) /* REW (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOSEL_DCLRM_Pos   (13UL)	  /* DCLRM (Bit 13) */
+#define LINK_REG_D1FIFOSEL_DCLRM_Msk   (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOSEL_DREQE_Pos   (12UL)	  /* DREQE (Bit 12) */
+#define LINK_REG_D1FIFOSEL_DREQE_Msk   (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOSEL_MBW_Pos     (10UL)	  /* MBW (Bit 10) */
+#define LINK_REG_D1FIFOSEL_MBW_Msk     (0xc00UL)  /* MBW (Bitfield-Mask: 0x03) */
+#define LINK_REG_D1FIFOSEL_BIGEND_Pos  (8UL)	  /* BIGEND (Bit 8) */
+#define LINK_REG_D1FIFOSEL_BIGEND_Msk  (0x100UL)  /* BIGEND (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOSEL_CURPIPE_Pos (0UL)	  /* CURPIPE (Bit 0) */
+#define LINK_REG_D1FIFOSEL_CURPIPE_Msk (0xfUL)	  /* CURPIPE (Bitfield-Mask: 0x0f) */
+/* D1FIFOCTR */
+#define LINK_REG_D1FIFOCTR_BVAL_Pos (15UL)     /* BVAL (Bit 15) */
+#define LINK_REG_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOCTR_BCLR_Pos (14UL)     /* BCLR (Bit 14) */
+#define LINK_REG_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOCTR_FRDY_Pos (13UL)     /* FRDY (Bit 13) */
+#define LINK_REG_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOCTR_DTLN_Pos (0UL)      /* DTLN (Bit 0) */
+#define LINK_REG_D1FIFOCTR_DTLN_Msk (0xfffUL)  /* DTLN (Bitfield-Mask: 0xfff) */
+/* INTENB0 */
+#define LINK_REG_INTENB0_VBSE_Pos  (15UL)     /* VBSE (Bit 15) */
+#define LINK_REG_INTENB0_VBSE_Msk  (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_RSME_Pos  (14UL)     /* RSME (Bit 14) */
+#define LINK_REG_INTENB0_RSME_Msk  (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_SOFE_Pos  (13UL)     /* SOFE (Bit 13) */
+#define LINK_REG_INTENB0_SOFE_Msk  (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_DVSE_Pos  (12UL)     /* DVSE (Bit 12) */
+#define LINK_REG_INTENB0_DVSE_Msk  (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_CTRE_Pos  (11UL)     /* CTRE (Bit 11) */
+#define LINK_REG_INTENB0_CTRE_Msk  (0x800UL)  /* CTRE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_BEMPE_Pos (10UL)     /* BEMPE (Bit 10) */
+#define LINK_REG_INTENB0_BEMPE_Msk (0x400UL)  /* BEMPE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_NRDYE_Pos (9UL)      /* NRDYE (Bit 9) */
+#define LINK_REG_INTENB0_NRDYE_Msk (0x200UL)  /* NRDYE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_BRDYE_Pos (8UL)      /* BRDYE (Bit 8) */
+#define LINK_REG_INTENB0_BRDYE_Msk (0x100UL)  /* BRDYE (Bitfield-Mask: 0x01) */
+/* INTENB1 */
+#define LINK_REG_INTENB1_OVRCRE_Pos	(15UL)	   /* OVRCRE (Bit 15) */
+#define LINK_REG_INTENB1_OVRCRE_Msk	(0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_BCHGE_Pos	(14UL)	   /* BCHGE (Bit 14) */
+#define LINK_REG_INTENB1_BCHGE_Msk	(0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_DTCHE_Pos	(12UL)	   /* DTCHE (Bit 12) */
+#define LINK_REG_INTENB1_DTCHE_Msk	(0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_ATTCHE_Pos	(11UL)	   /* ATTCHE (Bit 11) */
+#define LINK_REG_INTENB1_ATTCHE_Msk	(0x800UL)  /* ATTCHE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_EOFERRE_Pos	(6UL)	   /* EOFERRE (Bit 6) */
+#define LINK_REG_INTENB1_EOFERRE_Msk	(0x40UL)   /* EOFERRE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_SIGNE_Pos	(5UL)	   /* SIGNE (Bit 5) */
+#define LINK_REG_INTENB1_SIGNE_Msk	(0x20UL)   /* SIGNE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_SACKE_Pos	(4UL)	   /* SACKE (Bit 4) */
+#define LINK_REG_INTENB1_SACKE_Msk	(0x10UL)   /* SACKE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_PDDETINTE0_Pos (0UL)	   /* PDDETINTE0 (Bit 0) */
+#define LINK_REG_INTENB1_PDDETINTE0_Msk (0x1UL)	   /* PDDETINTE0 (Bitfield-Mask: 0x01) */
+/* BRDYENB */
+#define LINK_REG_BRDYENB_PIPEBRDYE_Pos (0UL)   /* PIPEBRDYE (Bit 0) */
+#define LINK_REG_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */
+/* NRDYENB */
+#define LINK_REG_NRDYENB_PIPENRDYE_Pos (0UL)   /* PIPENRDYE (Bit 0) */
+#define LINK_REG_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */
+/* BEMPENB */
+#define LINK_REG_BEMPENB_PIPEBEMPE_Pos (0UL)   /* PIPEBEMPE (Bit 0) */
+#define LINK_REG_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */
+/* SOFCFG */
+#define LINK_REG_SOFCFG_TRNENSEL_Pos (8UL)     /* TRNENSEL (Bit 8) */
+#define LINK_REG_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */
+#define LINK_REG_SOFCFG_BRDYM_Pos    (6UL)     /* BRDYM (Bit 6) */
+#define LINK_REG_SOFCFG_BRDYM_Msk    (0x40UL)  /* BRDYM (Bitfield-Mask: 0x01) */
+#define LINK_REG_SOFCFG_INTL_Pos     (5UL)     /* INTL (Bit 5) */
+#define LINK_REG_SOFCFG_INTL_Msk     (0x20UL)  /* INTL (Bitfield-Mask: 0x01) */
+#define LINK_REG_SOFCFG_EDGESTS_Pos  (4UL)     /* EDGESTS (Bit 4) */
+#define LINK_REG_SOFCFG_EDGESTS_Msk  (0x10UL)  /* EDGESTS (Bitfield-Mask: 0x01) */
+/* PHYSET */
+#define LINK_REG_PHYSET_HSEB_Pos     (15UL)	/* HSEB (Bit 15) */
+#define LINK_REG_PHYSET_HSEB_Msk     (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSET_REPSTART_Pos (11UL)	/* REPSTART (Bit 11) */
+#define LINK_REG_PHYSET_REPSTART_Msk (0x800UL)	/* REPSTART (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSET_REPSEL_Pos   (8UL)	/* REPSEL (Bit 8) */
+#define LINK_REG_PHYSET_REPSEL_Msk   (0x300UL)	/* REPSEL (Bitfield-Mask: 0x03) */
+#define LINK_REG_PHYSET_CLKSEL_Pos   (4UL)	/* CLKSEL (Bit 4) */
+#define LINK_REG_PHYSET_CLKSEL_Msk   (0x30UL)	/* CLKSEL (Bitfield-Mask: 0x03) */
+#define LINK_REG_PHYSET_CDPEN_Pos    (3UL)	/* CDPEN (Bit 3) */
+#define LINK_REG_PHYSET_CDPEN_Msk    (0x8UL)	/* CDPEN (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSET_PLLRESET_Pos (1UL)	/* PLLRESET (Bit 1) */
+#define LINK_REG_PHYSET_PLLRESET_Msk (0x2UL)	/* PLLRESET (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSET_DIRPD_Pos    (0UL)	/* DIRPD (Bit 0) */
+#define LINK_REG_PHYSET_DIRPD_Msk    (0x1UL)	/* DIRPD (Bitfield-Mask: 0x01) */
+/* INTSTS0 */
+#define LINK_REG_INTSTS0_VBINT_Pos (15UL)     /* VBINT (Bit 15) */
+#define LINK_REG_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_RESM_Pos  (14UL)     /* RESM (Bit 14) */
+#define LINK_REG_INTSTS0_RESM_Msk  (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_SOFR_Pos  (13UL)     /* SOFR (Bit 13) */
+#define LINK_REG_INTSTS0_SOFR_Msk  (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_DVST_Pos  (12UL)     /* DVST (Bit 12) */
+#define LINK_REG_INTSTS0_DVST_Msk  (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_CTRT_Pos  (11UL)     /* CTRT (Bit 11) */
+#define LINK_REG_INTSTS0_CTRT_Msk  (0x800UL)  /* CTRT (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_BEMP_Pos  (10UL)     /* BEMP (Bit 10) */
+#define LINK_REG_INTSTS0_BEMP_Msk  (0x400UL)  /* BEMP (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_NRDY_Pos  (9UL)      /* NRDY (Bit 9) */
+#define LINK_REG_INTSTS0_NRDY_Msk  (0x200UL)  /* NRDY (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_BRDY_Pos  (8UL)      /* BRDY (Bit 8) */
+#define LINK_REG_INTSTS0_BRDY_Msk  (0x100UL)  /* BRDY (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_VBSTS_Pos (7UL)      /* VBSTS (Bit 7) */
+#define LINK_REG_INTSTS0_VBSTS_Msk (0x80UL)   /* VBSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_DVSQ_Pos  (4UL)      /* DVSQ (Bit 4) */
+#define LINK_REG_INTSTS0_DVSQ_Msk  (0x70UL)   /* DVSQ (Bitfield-Mask: 0x07) */
+#define LINK_REG_INTSTS0_VALID_Pos (3UL)      /* VALID (Bit 3) */
+#define LINK_REG_INTSTS0_VALID_Msk (0x8UL)    /* VALID (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_CTSQ_Pos  (0UL)      /* CTSQ (Bit 0) */
+#define LINK_REG_INTSTS0_CTSQ_Msk  (0x7UL)    /* CTSQ (Bitfield-Mask: 0x07) */
+/* INTSTS1 */
+#define LINK_REG_INTSTS1_OVRCR_Pos     (15UL)	  /* OVRCR (Bit 15) */
+#define LINK_REG_INTSTS1_OVRCR_Msk     (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_BCHG_Pos      (14UL)	  /* BCHG (Bit 14) */
+#define LINK_REG_INTSTS1_BCHG_Msk      (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_DTCH_Pos      (12UL)	  /* DTCH (Bit 12) */
+#define LINK_REG_INTSTS1_DTCH_Msk      (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_ATTCH_Pos     (11UL)	  /* ATTCH (Bit 11) */
+#define LINK_REG_INTSTS1_ATTCH_Msk     (0x800UL)  /* ATTCH (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_L1RSMEND_Pos  (9UL)	  /* L1RSMEND (Bit 9) */
+#define LINK_REG_INTSTS1_L1RSMEND_Msk  (0x200UL)  /* L1RSMEND (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_LPMEND_Pos    (8UL)	  /* LPMEND (Bit 8) */
+#define LINK_REG_INTSTS1_LPMEND_Msk    (0x100UL)  /* LPMEND (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_EOFERR_Pos    (6UL)	  /* EOFERR (Bit 6) */
+#define LINK_REG_INTSTS1_EOFERR_Msk    (0x40UL)	  /* EOFERR (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_SIGN_Pos      (5UL)	  /* SIGN (Bit 5) */
+#define LINK_REG_INTSTS1_SIGN_Msk      (0x20UL)	  /* SIGN (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_SACK_Pos      (4UL)	  /* SACK (Bit 4) */
+#define LINK_REG_INTSTS1_SACK_Msk      (0x10UL)	  /* SACK (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_PDDETINT0_Pos (0UL)	  /* PDDETINT0 (Bit 0) */
+#define LINK_REG_INTSTS1_PDDETINT0_Msk (0x1UL)	  /* PDDETINT0 (Bitfield-Mask: 0x01) */
+/* BRDYSTS */
+#define LINK_REG_BRDYSTS_PIPEBRDY_Pos (0UL)   /* PIPEBRDY (Bit 0) */
+#define LINK_REG_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */
+/* NRDYSTS */
+#define LINK_REG_NRDYSTS_PIPENRDY_Pos (0UL)   /* PIPENRDY (Bit 0) */
+#define LINK_REG_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */
+/* BEMPSTS */
+#define LINK_REG_BEMPSTS_PIPEBEMP_Pos (0UL)   /* PIPEBEMP (Bit 0) */
+#define LINK_REG_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */
+/* FRMNUM */
+#define LINK_REG_FRMNUM_OVRN_Pos (15UL)	    /* OVRN (Bit 15) */
+#define LINK_REG_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */
+#define LINK_REG_FRMNUM_CRCE_Pos (14UL)	    /* CRCE (Bit 14) */
+#define LINK_REG_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */
+#define LINK_REG_FRMNUM_FRNM_Pos (0UL)	    /* FRNM (Bit 0) */
+#define LINK_REG_FRMNUM_FRNM_Msk (0x7ffUL)  /* FRNM (Bitfield-Mask: 0x7ff) */
+/* UFRMNUM */
+#define LINK_REG_UFRMNUM_DVCHG_Pos (15UL)     /* DVCHG (Bit 15) */
+#define LINK_REG_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */
+#define LINK_REG_UFRMNUM_UFRNM_Pos (0UL)      /* UFRNM (Bit 0) */
+#define LINK_REG_UFRMNUM_UFRNM_Msk (0x7UL)    /* UFRNM (Bitfield-Mask: 0x07) */
+/* USBADDR */
+#define LINK_REG_USBADDR_STSRECOV0_Pos (8UL)	 /* STSRECOV0 (Bit 8) */
+#define LINK_REG_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */
+#define LINK_REG_USBADDR_USBADDR_Pos   (0UL)	 /* USBADDR (Bit 0) */
+#define LINK_REG_USBADDR_USBADDR_Msk   (0x7fUL)	 /* USBADDR (Bitfield-Mask: 0x7f) */
+/* USBREQ */
+#define LINK_REG_USBREQ_BREQUEST_Pos	  (8UL)	     /* BREQUEST (Bit 8) */
+#define LINK_REG_USBREQ_BREQUEST_Msk	  (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */
+#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos (0UL)	     /* BMREQUESTTYPE (Bit 0) */
+#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk (0xffUL)   /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */
+/* USBVAL */
+#define LINK_REG_USBVAL_WVALUE_Pos (0UL)      /* WVALUE (Bit 0) */
+#define LINK_REG_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */
+/* USBINDX */
+#define LINK_REG_USBINDX_WINDEX_Pos (0UL)      /* WINDEX (Bit 0) */
+#define LINK_REG_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */
+/* USBLENG */
+#define LINK_REG_USBLENG_WLENGTH_Pos (0UL)	/* WLENGTH (Bit 0) */
+#define LINK_REG_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */
+/* DCPCFG */
+#define LINK_REG_DCPCFG_CNTMD_Pos  (8UL)     /* CNTMD (Bit 8) */
+#define LINK_REG_DCPCFG_CNTMD_Msk  (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCFG_SHTNAK_Pos (7UL)     /* SHTNAK (Bit 7) */
+#define LINK_REG_DCPCFG_SHTNAK_Msk (0x80UL)  /* SHTNAK (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCFG_DIR_Pos	   (4UL)     /* DIR (Bit 4) */
+#define LINK_REG_DCPCFG_DIR_Msk	   (0x10UL)  /* DIR (Bitfield-Mask: 0x01) */
+/* DCPMAXP */
+#define LINK_REG_DCPMAXP_DEVSEL_Pos (12UL)     /* DEVSEL (Bit 12) */
+#define LINK_REG_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */
+#define LINK_REG_DCPMAXP_MXPS_Pos   (0UL)      /* MXPS (Bit 0) */
+#define LINK_REG_DCPMAXP_MXPS_Msk   (0x7fUL)   /* MXPS (Bitfield-Mask: 0x7f) */
+/* DCPCTR */
+#define LINK_REG_DCPCTR_BSTS_Pos     (15UL)	/* BSTS (Bit 15) */
+#define LINK_REG_DCPCTR_BSTS_Msk     (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_SUREQ_Pos    (14UL)	/* SUREQ (Bit 14) */
+#define LINK_REG_DCPCTR_SUREQ_Msk    (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_SUREQCLR_Pos (11UL)	/* SUREQCLR (Bit 11) */
+#define LINK_REG_DCPCTR_SUREQCLR_Msk (0x800UL)	/* SUREQCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_SQCLR_Pos    (8UL)	/* SQCLR (Bit 8) */
+#define LINK_REG_DCPCTR_SQCLR_Msk    (0x100UL)	/* SQCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_SQSET_Pos    (7UL)	/* SQSET (Bit 7) */
+#define LINK_REG_DCPCTR_SQSET_Msk    (0x80UL)	/* SQSET (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_SQMON_Pos    (6UL)	/* SQMON (Bit 6) */
+#define LINK_REG_DCPCTR_SQMON_Msk    (0x40UL)	/* SQMON (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_PBUSY_Pos    (5UL)	/* PBUSY (Bit 5) */
+#define LINK_REG_DCPCTR_PBUSY_Msk    (0x20UL)	/* PBUSY (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_CCPL_Pos     (2UL)	/* CCPL (Bit 2) */
+#define LINK_REG_DCPCTR_CCPL_Msk     (0x4UL)	/* CCPL (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_PID_Pos	     (0UL)	/* PID (Bit 0) */
+#define LINK_REG_DCPCTR_PID_Msk	     (0x3UL)	/* PID (Bitfield-Mask: 0x03) */
+/* PIPESEL */
+#define LINK_REG_PIPESEL_PIPESEL_Pos (0UL)   /* PIPESEL (Bit 0) */
+#define LINK_REG_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */
+/* PIPECFG */
+#define LINK_REG_PIPECFG_TYPE_Pos   (14UL)     /* TYPE (Bit 14) */
+#define LINK_REG_PIPECFG_TYPE_Msk   (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */
+#define LINK_REG_PIPECFG_BFRE_Pos   (10UL)     /* BFRE (Bit 10) */
+#define LINK_REG_PIPECFG_BFRE_Msk   (0x400UL)  /* BFRE (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPECFG_DBLB_Pos   (9UL)      /* DBLB (Bit 9) */
+#define LINK_REG_PIPECFG_DBLB_Msk   (0x200UL)  /* DBLB (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPECFG_SHTNAK_Pos (7UL)      /* SHTNAK (Bit 7) */
+#define LINK_REG_PIPECFG_SHTNAK_Msk (0x80UL)   /* SHTNAK (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPECFG_DIR_Pos    (4UL)      /* DIR (Bit 4) */
+#define LINK_REG_PIPECFG_DIR_Msk    (0x10UL)   /* DIR (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPECFG_EPNUM_Pos  (0UL)      /* EPNUM (Bit 0) */
+#define LINK_REG_PIPECFG_EPNUM_Msk  (0xfUL)    /* EPNUM (Bitfield-Mask: 0x0f) */
+/* PIPEMAXP */
+#define LINK_REG_PIPEMAXP_DEVSEL_Pos (12UL)	/* DEVSEL (Bit 12) */
+#define LINK_REG_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */
+#define LINK_REG_PIPEMAXP_MXPS_Pos   (0UL)	/* MXPS (Bit 0) */
+#define LINK_REG_PIPEMAXP_MXPS_Msk   (0x1ffUL)	/* MXPS (Bitfield-Mask: 0x1ff) */
+/* PIPEPERI */
+#define LINK_REG_PIPEPERI_IFIS_Pos (12UL)     /* IFIS (Bit 12) */
+#define LINK_REG_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPEPERI_IITV_Pos (0UL)      /* IITV (Bit 0) */
+#define LINK_REG_PIPEPERI_IITV_Msk (0x7UL)    /* IITV (Bitfield-Mask: 0x07) */
+/* PIPE_CTR */
+#define LINK_REG_PIPE_CTR_BSTS_Pos   (15UL)	/* BSTS (Bit 15) */
+#define LINK_REG_PIPE_CTR_BSTS_Msk   (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_INBUFM_Pos (14UL)	/* INBUFM (Bit 14) */
+#define LINK_REG_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_CSCLR_Pos  (13UL)	/* CSCLR (Bit 13) */
+#define LINK_REG_PIPE_CTR_CSCLR_Msk  (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_CSSTS_Pos  (12UL)	/* CSSTS (Bit 12) */
+#define LINK_REG_PIPE_CTR_CSSTS_Msk  (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_ATREPM_Pos (10UL)	/* ATREPM (Bit 10) */
+#define LINK_REG_PIPE_CTR_ATREPM_Msk (0x400UL)	/* ATREPM (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_ACLRM_Pos  (9UL)	/* ACLRM (Bit 9) */
+#define LINK_REG_PIPE_CTR_ACLRM_Msk  (0x200UL)	/* ACLRM (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_SQCLR_Pos  (8UL)	/* SQCLR (Bit 8) */
+#define LINK_REG_PIPE_CTR_SQCLR_Msk  (0x100UL)	/* SQCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_SQSET_Pos  (7UL)	/* SQSET (Bit 7) */
+#define LINK_REG_PIPE_CTR_SQSET_Msk  (0x80UL)	/* SQSET (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_SQMON_Pos  (6UL)	/* SQMON (Bit 6) */
+#define LINK_REG_PIPE_CTR_SQMON_Msk  (0x40UL)	/* SQMON (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_PBUSY_Pos  (5UL)	/* PBUSY (Bit 5) */
+#define LINK_REG_PIPE_CTR_PBUSY_Msk  (0x20UL)	/* PBUSY (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_PID_Pos    (0UL)	/* PID (Bit 0) */
+#define LINK_REG_PIPE_CTR_PID_Msk    (0x3UL)	/* PID (Bitfield-Mask: 0x03) */
+/* DEVADD */
+#define LINK_REG_DEVADD_UPPHUB_Pos  (11UL)     /* UPPHUB (Bit 11) */
+#define LINK_REG_DEVADD_UPPHUB_Msk  (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */
+#define LINK_REG_DEVADD_HUBPORT_Pos (8UL)      /* HUBPORT (Bit 8) */
+#define LINK_REG_DEVADD_HUBPORT_Msk (0x700UL)  /* HUBPORT (Bitfield-Mask: 0x07) */
+#define LINK_REG_DEVADD_USBSPD_Pos  (6UL)      /* USBSPD (Bit 6) */
+#define LINK_REG_DEVADD_USBSPD_Msk  (0xc0UL)   /* USBSPD (Bitfield-Mask: 0x03) */
+/* USBBCCTRL0 */
+#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos  (9UL)     /* PDDETSTS0 (Bit 9) */
+#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk  (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL)     /* CHGDETSTS0 (Bit 8) */
+#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_BATCHGE0_Pos   (7UL)     /* BATCHGE0 (Bit 7) */
+#define LINK_REG_USBBCCTRL0_BATCHGE0_Msk   (0x80UL)  /* BATCHGE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_VDMSRCE0_Pos   (5UL)     /* VDMSRCE0 (Bit 5) */
+#define LINK_REG_USBBCCTRL0_VDMSRCE0_Msk   (0x20UL)  /* VDMSRCE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_IDPSINKE0_Pos  (4UL)     /* IDPSINKE0 (Bit 4) */
+#define LINK_REG_USBBCCTRL0_IDPSINKE0_Msk  (0x10UL)  /* IDPSINKE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_VDPSRCE0_Pos   (3UL)     /* VDPSRCE0 (Bit 3) */
+#define LINK_REG_USBBCCTRL0_VDPSRCE0_Msk   (0x8UL)   /* VDPSRCE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_IDMSINKE0_Pos  (2UL)     /* IDMSINKE0 (Bit 2) */
+#define LINK_REG_USBBCCTRL0_IDMSINKE0_Msk  (0x4UL)   /* IDMSINKE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_IDPSRCE0_Pos   (1UL)     /* IDPSRCE0 (Bit 1) */
+#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk   (0x2UL)   /* IDPSRCE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_RPDME0_Pos	   (0UL)     /* RPDME0 (Bit 0) */
+#define LINK_REG_USBBCCTRL0_RPDME0_Msk	   (0x1UL)   /* RPDME0 (Bitfield-Mask: 0x01) */
+/* UCKSEL */
+#define LINK_REG_UCKSEL_UCKSELC_Pos (0UL)   /* UCKSELC (Bit 0) */
+#define LINK_REG_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */
+/* USBMC */
+#define LINK_REG_USBMC_VDCEN_Pos   (7UL)    /* VDCEN (Bit 7) */
+#define LINK_REG_USBMC_VDCEN_Msk   (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBMC_VDDUSBE_Pos (0UL)    /* VDDUSBE (Bit 0) */
+#define LINK_REG_USBMC_VDDUSBE_Msk (0x1UL)  /* VDDUSBE (Bitfield-Mask: 0x01) */
+/* PHYSLEW */
+#define LINK_REG_PHYSLEW_SLEWF01_Pos (3UL)   /* SLEWF01 (Bit 3) */
+#define LINK_REG_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSLEW_SLEWF00_Pos (2UL)   /* SLEWF00 (Bit 2) */
+#define LINK_REG_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSLEW_SLEWR01_Pos (1UL)   /* SLEWR01 (Bit 1) */
+#define LINK_REG_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSLEW_SLEWR00_Pos (0UL)   /* SLEWR00 (Bit 0) */
+#define LINK_REG_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */
+/* LPCTRL */
+#define LINK_REG_LPCTRL_HWUPM_Pos (7UL)	   /* HWUPM (Bit 7) */
+#define LINK_REG_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */
+/* LPSTS */
+#define LINK_REG_LPSTS_SUSPENDM_Pos (14UL)     /* SUSPENDM (Bit 14) */
+#define LINK_REG_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */
+/* BCCTRL */
+#define LINK_REG_BCCTRL_PDDETSTS_Pos  (9UL)	/* PDDETSTS (Bit 9) */
+#define LINK_REG_BCCTRL_PDDETSTS_Msk  (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_CHGDETSTS_Pos (8UL)	/* CHGDETSTS (Bit 8) */
+#define LINK_REG_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_DCPMODE_Pos   (5UL)	/* DCPMODE (Bit 5) */
+#define LINK_REG_BCCTRL_DCPMODE_Msk   (0x20UL)	/* DCPMODE (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_VDMSRCE_Pos   (4UL)	/* VDMSRCE (Bit 4) */
+#define LINK_REG_BCCTRL_VDMSRCE_Msk   (0x10UL)	/* VDMSRCE (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_IDPSINKE_Pos  (3UL)	/* IDPSINKE (Bit 3) */
+#define LINK_REG_BCCTRL_IDPSINKE_Msk  (0x8UL)	/* IDPSINKE (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_VDPSRCE_Pos   (2UL)	/* VDPSRCE (Bit 2) */
+#define LINK_REG_BCCTRL_VDPSRCE_Msk   (0x4UL)	/* VDPSRCE (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_IDMSINKE_Pos  (1UL)	/* IDMSINKE (Bit 1) */
+#define LINK_REG_BCCTRL_IDMSINKE_Msk  (0x2UL)	/* IDMSINKE (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_IDPSRCE_Pos   (0UL)	/* IDPSRCE (Bit 0) */
+#define LINK_REG_BCCTRL_IDPSRCE_Msk   (0x1UL)	/* IDPSRCE (Bitfield-Mask: 0x01) */
+/* PL1CTRL1 */
+#define LINK_REG_PL1CTRL1_L1EXTMD_Pos  (14UL)	  /* L1EXTMD (Bit 14) */
+#define LINK_REG_PL1CTRL1_L1EXTMD_Msk  (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */
+#define LINK_REG_PL1CTRL1_HIRDTHR_Pos  (8UL)	  /* HIRDTHR (Bit 8) */
+#define LINK_REG_PL1CTRL1_HIRDTHR_Msk  (0xf00UL)  /* HIRDTHR (Bitfield-Mask: 0x0f) */
+#define LINK_REG_PL1CTRL1_DVSQ_Pos     (4UL)	  /* DVSQ (Bit 4) */
+#define LINK_REG_PL1CTRL1_DVSQ_Msk     (0xf0UL)	  /* DVSQ (Bitfield-Mask: 0x0f) */
+#define LINK_REG_PL1CTRL1_L1NEGOMD_Pos (3UL)	  /* L1NEGOMD (Bit 3) */
+#define LINK_REG_PL1CTRL1_L1NEGOMD_Msk (0x8UL)	  /* L1NEGOMD (Bitfield-Mask: 0x01) */
+#define LINK_REG_PL1CTRL1_L1RESPMD_Pos (1UL)	  /* L1RESPMD (Bit 1) */
+#define LINK_REG_PL1CTRL1_L1RESPMD_Msk (0x6UL)	  /* L1RESPMD (Bitfield-Mask: 0x03) */
+#define LINK_REG_PL1CTRL1_L1RESPEN_Pos (0UL)	  /* L1RESPEN (Bit 0) */
+#define LINK_REG_PL1CTRL1_L1RESPEN_Msk (0x1UL)	  /* L1RESPEN (Bitfield-Mask: 0x01) */
+/* PL1CTRL2 */
+#define LINK_REG_PL1CTRL2_RWEMON_Pos  (12UL)	 /* RWEMON (Bit 12) */
+#define LINK_REG_PL1CTRL2_RWEMON_Msk  (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */
+#define LINK_REG_PL1CTRL2_HIRDMON_Pos (8UL)	 /* HIRDMON (Bit 8) */
+#define LINK_REG_PL1CTRL2_HIRDMON_Msk (0xf00UL)	 /* HIRDMON (Bitfield-Mask: 0x0f) */
+/* HL1CTRL1 */
+#define LINK_REG_HL1CTRL1_L1STATUS_Pos (1UL)   /* L1STATUS (Bit 1) */
+#define LINK_REG_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */
+#define LINK_REG_HL1CTRL1_L1REQ_Pos    (0UL)   /* L1REQ (Bit 0) */
+#define LINK_REG_HL1CTRL1_L1REQ_Msk    (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */
+/* HL1CTRL2 */
+#define LINK_REG_HL1CTRL2_BESL_Pos   (15UL)	/* BESL (Bit 15) */
+#define LINK_REG_HL1CTRL2_BESL_Msk   (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */
+#define LINK_REG_HL1CTRL2_L1RWE_Pos  (12UL)	/* L1RWE (Bit 12) */
+#define LINK_REG_HL1CTRL2_L1RWE_Msk  (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */
+#define LINK_REG_HL1CTRL2_HIRD_Pos   (8UL)	/* HIRD (Bit 8) */
+#define LINK_REG_HL1CTRL2_HIRD_Msk   (0xf00UL)	/* HIRD (Bitfield-Mask: 0x0f) */
+#define LINK_REG_HL1CTRL2_L1ADDR_Pos (0UL)	/* L1ADDR (Bit 0) */
+#define LINK_REG_HL1CTRL2_L1ADDR_Msk (0xfUL)	/* L1ADDR (Bitfield-Mask: 0x0f) */
+/* DPUSR0R */
+#define LINK_REG_DPUSR0R_DVBSTSHM_Pos (23UL)	   /* DVBSTSHM (Bit 23) */
+#define LINK_REG_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_DOVCBHM_Pos  (21UL)	   /* DOVCBHM (Bit 21) */
+#define LINK_REG_DPUSR0R_DOVCBHM_Msk  (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_DOVCAHM_Pos  (20UL)	   /* DOVCAHM (Bit 20) */
+#define LINK_REG_DPUSR0R_DOVCAHM_Msk  (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */
+/* DPUSR1R */
+#define LINK_REG_DPUSR1R_DVBSTSH_Pos  (23UL)	   /* DVBSTSH (Bit 23) */
+#define LINK_REG_DPUSR1R_DVBSTSH_Msk  (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_DOVCBH_Pos   (21UL)	   /* DOVCBH (Bit 21) */
+#define LINK_REG_DPUSR1R_DOVCBH_Msk   (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_DOVCAH_Pos   (20UL)	   /* DOVCAH (Bit 20) */
+#define LINK_REG_DPUSR1R_DOVCAH_Msk   (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_DVBSTSHE_Pos (7UL)	   /* DVBSTSHE (Bit 7) */
+#define LINK_REG_DPUSR1R_DVBSTSHE_Msk (0x80UL)	   /* DVBSTSHE (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_DOVCBHE_Pos  (5UL)	   /* DOVCBHE (Bit 5) */
+#define LINK_REG_DPUSR1R_DOVCBHE_Msk  (0x20UL)	   /* DOVCBHE (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_DOVCAHE_Pos  (4UL)	   /* DOVCAHE (Bit 4) */
+#define LINK_REG_DPUSR1R_DOVCAHE_Msk  (0x10UL)	   /* DOVCAHE (Bitfield-Mask: 0x01) */
+/* DPUSR2R */
+#define LINK_REG_DPUSR2R_DMINTE_Pos (9UL)     /* DMINTE (Bit 9) */
+#define LINK_REG_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR2R_DPINTE_Pos (8UL)     /* DPINTE (Bit 8) */
+#define LINK_REG_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR2R_DMVAL_Pos  (5UL)     /* DMVAL (Bit 5) */
+#define LINK_REG_DPUSR2R_DMVAL_Msk  (0x20UL)  /* DMVAL (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR2R_DPVAL_Pos  (4UL)     /* DPVAL (Bit 4) */
+#define LINK_REG_DPUSR2R_DPVAL_Msk  (0x10UL)  /* DPVAL (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR2R_DMINT_Pos  (1UL)     /* DMINT (Bit 1) */
+#define LINK_REG_DPUSR2R_DMINT_Msk  (0x2UL)   /* DMINT (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR2R_DPINT_Pos  (0UL)     /* DPINT (Bit 0) */
+#define LINK_REG_DPUSR2R_DPINT_Msk  (0x1UL)   /* DPINT (Bitfield-Mask: 0x01) */
+/* DPUSRCR */
+#define LINK_REG_DPUSRCR_FIXPHYPD_Pos (1UL)   /* FIXPHYPD (Bit 1) */
+#define LINK_REG_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSRCR_FIXPHY_Pos   (0UL)   /* FIXPHY (Bit 0) */
+#define LINK_REG_DPUSRCR_FIXPHY_Msk   (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */
+/* DPUSR0R_FS */
+#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos (23UL)	     /* DVBSTS0 (Bit 23) */
+#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos	(21UL)	     /* DOVCB0 (Bit 21) */
+#define LINK_REG_DPUSR0R_FS_DOVCB0_Msk	(0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_DOVCA0_Pos	(20UL)	     /* DOVCA0 (Bit 20) */
+#define LINK_REG_DPUSR0R_FS_DOVCA0_Msk	(0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_DM0_Pos	(17UL)	     /* DM0 (Bit 17) */
+#define LINK_REG_DPUSR0R_FS_DM0_Msk	(0x20000UL)  /* DM0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_DP0_Pos	(16UL)	     /* DP0 (Bit 16) */
+#define LINK_REG_DPUSR0R_FS_DP0_Msk	(0x10000UL)  /* DP0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_FIXPHY0_Pos (4UL)	     /* FIXPHY0 (Bit 4) */
+#define LINK_REG_DPUSR0R_FS_FIXPHY0_Msk (0x10UL)     /* FIXPHY0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_DRPD0_Pos	(3UL)	     /* DRPD0 (Bit 3) */
+#define LINK_REG_DPUSR0R_FS_DRPD0_Msk	(0x8UL)	     /* DRPD0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_RPUE0_Pos	(1UL)	     /* RPUE0 (Bit 1) */
+#define LINK_REG_DPUSR0R_FS_RPUE0_Msk	(0x2UL)	     /* RPUE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_SRPC0_Pos	(0UL)	     /* SRPC0 (Bit 0) */
+#define LINK_REG_DPUSR0R_FS_SRPC0_Msk	(0x1UL)	     /* SRPC0 (Bitfield-Mask: 0x01) */
+/* DPUSR1R_FS */
+#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos	  (23UL)       /* DVBINT0 (Bit 23) */
+#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk	  (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos  (21UL)       /* DOVRCRB0 (Bit 21) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Msk  (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Pos  (20UL)       /* DOVRCRA0 (Bit 20) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Msk  (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DMINT0_Pos	  (17UL)       /* DMINT0 (Bit 17) */
+#define LINK_REG_DPUSR1R_FS_DMINT0_Msk	  (0x20000UL)  /* DMINT0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DPINT0_Pos	  (16UL)       /* DPINT0 (Bit 16) */
+#define LINK_REG_DPUSR1R_FS_DPINT0_Msk	  (0x10000UL)  /* DPINT0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DVBSE0_Pos	  (7UL)	       /* DVBSE0 (Bit 7) */
+#define LINK_REG_DPUSR1R_FS_DVBSE0_Msk	  (0x80UL)     /* DVBSE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Pos (5UL)	       /* DOVRCRBE0 (Bit 5) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL)     /* DOVRCRBE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Pos (4UL)	       /* DOVRCRAE0 (Bit 4) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL)     /* DOVRCRAE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DMINTE0_Pos	  (1UL)	       /* DMINTE0 (Bit 1) */
+#define LINK_REG_DPUSR1R_FS_DMINTE0_Msk	  (0x2UL)      /* DMINTE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos	  (0UL)	       /* DPINTE0 (Bit 0) */
+#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk	  (0x1UL)      /* DPINTE0 (Bitfield-Mask: 0x01) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_LINK_TYPE_H_ */

From 2a17a7e8f851c1a29d7e06ff520d15f36b7a652c Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Wed, 9 Mar 2022 12:14:55 +0000
Subject: [PATCH 1035/2085] rework make freertos port handling

	this allows ports to specify a freertos port outside the FreeRTOS-Kernel lib directory, which would otherwise not be possible

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 examples/device/cdc_msc_freertos/Makefile       | 7 ++++---
 examples/device/hid_composite_freertos/Makefile | 7 ++++---
 hw/bsp/d5035_01/board.mk                        | 2 +-
 hw/bsp/da14695_dk_usb/board.mk                  | 2 +-
 hw/bsp/da1469x_dk_pro/board.mk                  | 2 +-
 hw/bsp/ea4088qs/board.mk                        | 2 +-
 hw/bsp/ea4357/board.mk                          | 2 +-
 hw/bsp/fomu/family.mk                           | 2 +-
 hw/bsp/frdm_k32l2b/board.mk                     | 2 +-
 hw/bsp/frdm_kl25z/board.mk                      | 2 +-
 hw/bsp/gd32vf103/family.mk                      | 2 +-
 hw/bsp/imxrt/family.mk                          | 2 +-
 hw/bsp/kuiic/board.mk                           | 2 +-
 hw/bsp/lpc15/family.mk                          | 2 +-
 hw/bsp/lpc18/family.mk                          | 2 +-
 hw/bsp/lpc54/family.mk                          | 2 +-
 hw/bsp/lpc55/family.mk                          | 2 +-
 hw/bsp/lpcxpresso11u37/board.mk                 | 2 +-
 hw/bsp/lpcxpresso11u68/board.mk                 | 2 +-
 hw/bsp/lpcxpresso1347/board.mk                  | 2 +-
 hw/bsp/lpcxpresso1769/board.mk                  | 2 +-
 hw/bsp/lpcxpresso51u68/board.mk                 | 2 +-
 hw/bsp/mbed1768/board.mk                        | 2 +-
 hw/bsp/mm32/family.mk                           | 2 +-
 hw/bsp/msp432e4/family.mk                       | 2 +-
 hw/bsp/ngx4330/board.mk                         | 2 +-
 hw/bsp/nrf/family.mk                            | 2 +-
 hw/bsp/nutiny_nuc121s/board.mk                  | 2 +-
 hw/bsp/nutiny_nuc125s/board.mk                  | 2 +-
 hw/bsp/nutiny_nuc126v/board.mk                  | 2 +-
 hw/bsp/nutiny_sdk_nuc120/board.mk               | 2 +-
 hw/bsp/nutiny_sdk_nuc505/board.mk               | 2 +-
 hw/bsp/rx/boards/gr_citrus/board.mk             | 2 +-
 hw/bsp/rx/boards/rx65n_target/board.mk          | 2 +-
 hw/bsp/samd11/family.mk                         | 2 +-
 hw/bsp/samd21/family.mk                         | 2 +-
 hw/bsp/samd51/family.mk                         | 2 +-
 hw/bsp/same54xplainedpro/board.mk               | 2 +-
 hw/bsp/same70_qmtech/board.mk                   | 2 +-
 hw/bsp/same70_xplained/board.mk                 | 2 +-
 hw/bsp/samg55xplained/board.mk                  | 2 +-
 hw/bsp/saml2x/family.mk                         | 2 +-
 hw/bsp/sltb009a/board.mk                        | 2 +-
 hw/bsp/stm32f0/family.mk                        | 2 +-
 hw/bsp/stm32f1/family.mk                        | 2 +-
 hw/bsp/stm32f207nucleo/board.mk                 | 2 +-
 hw/bsp/stm32f303disco/board.mk                  | 2 +-
 hw/bsp/stm32f4/family.mk                        | 2 +-
 hw/bsp/stm32f7/family.mk                        | 2 +-
 hw/bsp/stm32g4/family.mk                        | 2 +-
 hw/bsp/stm32h7/family.mk                        | 2 +-
 hw/bsp/stm32l0538disco/board.mk                 | 2 +-
 hw/bsp/stm32l4/family.mk                        | 2 +-
 hw/bsp/stm32wb/family.mk                        | 2 +-
 hw/bsp/tm4c123/family.mk                        | 2 +-
 hw/bsp/xmc4000/family.mk                        | 2 +-
 56 files changed, 62 insertions(+), 60 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index a155d6cb7..368bc8cfa 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -4,14 +4,15 @@ include ../../../tools/top.mk
 include ../../make.mk
 
 FREERTOS_SRC = lib/FreeRTOS-Kernel
+FREERTOS_PORT_PATH = lib/FreeRTOS-Kernel/portable/GCC
 
 INC += \
 	src \
 	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
-	$(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)
-	
+	$(TOP)/$(FREERTOS_PORT)
+
 # Example source
 EXAMPLE_SOURCE = \
 	src/freertos_hook.c \
@@ -27,7 +28,7 @@ SRC_C += \
 	$(FREERTOS_SRC)/queue.c \
 	$(FREERTOS_SRC)/tasks.c \
 	$(FREERTOS_SRC)/timers.c \
-	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c))
 
 # Suppress FreeRTOS warnings
 CFLAGS += -Wno-error=cast-qual
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index c9b7abdf5..f2e0210ae 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -4,20 +4,21 @@ include ../../../tools/top.mk
 include ../../make.mk
 
 FREERTOS_SRC = lib/FreeRTOS-Kernel
+FREERTOS_PORT_PATH = lib/FreeRTOS-Kernel/portable/GCC
 
 INC += \
 	src \
 	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
-	$(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)	
+	$(TOP)/$(FREERTOS_PORT)
 
 # Example source
 EXAMPLE_SOURCE = \
 	src/freertos_hook.c \
 	src/main.c \
 	src/usb_descriptors.c
-	
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 # FreeRTOS source, all files in port folder
@@ -26,7 +27,7 @@ SRC_C += \
 	$(FREERTOS_SRC)/queue.c \
 	$(FREERTOS_SRC)/tasks.c \
 	$(FREERTOS_SRC)/timers.c \
-	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c))
 
 # Suppress FreeRTOS warnings
 CFLAGS += -Wno-error=cast-qual
diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk
index b7796b9d8..cefd8c935 100644
--- a/hw/bsp/d5035_01/board.mk
+++ b/hw/bsp/d5035_01/board.mk
@@ -52,7 +52,7 @@ INC += \
 	$(TOP)/hw/mcu/microchip/same51/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = ATSAME51J19
diff --git a/hw/bsp/da14695_dk_usb/board.mk b/hw/bsp/da14695_dk_usb/board.mk
index e969c79c2..2ca7f8529 100644
--- a/hw/bsp/da14695_dk_usb/board.mk
+++ b/hw/bsp/da14695_dk_usb/board.mk
@@ -31,7 +31,7 @@ INC += \
 	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM33_NTZ/non_secure
 
 # For flash-jlink target
 JLINK_DEVICE = DA14695
diff --git a/hw/bsp/da1469x_dk_pro/board.mk b/hw/bsp/da1469x_dk_pro/board.mk
index 980fc422f..d9dd5cd65 100644
--- a/hw/bsp/da1469x_dk_pro/board.mk
+++ b/hw/bsp/da1469x_dk_pro/board.mk
@@ -31,7 +31,7 @@ INC += \
 	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM33_NTZ/non_secure
 
 # For flash-jlink target
 JLINK_DEVICE = DA14699
diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/ea4088qs/board.mk
index b325dfeb4..54195b20c 100644
--- a/hw/bsp/ea4088qs/board.mk
+++ b/hw/bsp/ea4088qs/board.mk
@@ -37,7 +37,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = LPC4088
diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
index 6f243c6a2..4556e98f6 100644
--- a/hw/bsp/ea4357/board.mk
+++ b/hw/bsp/ea4357/board.mk
@@ -39,7 +39,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc/config_43xx
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = LPC4357_M4
diff --git a/hw/bsp/fomu/family.mk b/hw/bsp/fomu/family.mk
index 165535c6b..8f8f3d011 100644
--- a/hw/bsp/fomu/family.mk
+++ b/hw/bsp/fomu/family.mk
@@ -19,7 +19,7 @@ INC += \
 	$(TOP)/$(FAMILY_PATH)/include
 
 # For freeRTOS port source
-FREERTOS_PORT = RISC-V
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RISC-V
 
 # flash using dfu-util
 $(BUILD)/$(PROJECT).dfu: $(BUILD)/$(PROJECT).bin
diff --git a/hw/bsp/frdm_k32l2b/board.mk b/hw/bsp/frdm_k32l2b/board.mk
index 56df553da..407e5805d 100644
--- a/hw/bsp/frdm_k32l2b/board.mk
+++ b/hw/bsp/frdm_k32l2b/board.mk
@@ -39,7 +39,7 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = MKL25Z128xxx4
diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
index 3585b8b03..0a2ddad9f 100644
--- a/hw/bsp/frdm_kl25z/board.mk
+++ b/hw/bsp/frdm_kl25z/board.mk
@@ -40,7 +40,7 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_MKL25Z4.S
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = MKL25Z128xxx4
diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk
index 49bacdf1b..c0c144f5c 100644
--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -57,7 +57,7 @@ INC += \
 	$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include/Usb
 
 # For freeRTOS port source
-FREERTOS_PORT = RISC-V
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RISC-V
 
 # For flash-jlink target
 JLINK_IF = jtag
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 0bf4a0d15..850e54202 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -59,5 +59,5 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7/r0p1
 
diff --git a/hw/bsp/kuiic/board.mk b/hw/bsp/kuiic/board.mk
index 39e9d9deb..94646dbde 100644
--- a/hw/bsp/kuiic/board.mk
+++ b/hw/bsp/kuiic/board.mk
@@ -40,7 +40,7 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = MKL25Z128xxx4
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
index c7dd3f8be..fee0e0106 100644
--- a/hw/bsp/lpc15/family.mk
+++ b/hw/bsp/lpc15/family.mk
@@ -36,4 +36,4 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index 7aa36abc4..8ba05c9c9 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -34,4 +34,4 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc/config_18xx
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index 600df6fd0..3c1059eff 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -51,4 +51,4 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index 4e8d65ce9..94e7fea41 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -64,4 +64,4 @@ SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM33_NTZ/non_secure
diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk
index b736eebe1..97ac6c01a 100644
--- a/hw/bsp/lpcxpresso11u37/board.mk
+++ b/hw/bsp/lpcxpresso11u37/board.mk
@@ -36,7 +36,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = LPC11U37/401
diff --git a/hw/bsp/lpcxpresso11u68/board.mk b/hw/bsp/lpcxpresso11u68/board.mk
index 922414f82..9647b8b8f 100644
--- a/hw/bsp/lpcxpresso11u68/board.mk
+++ b/hw/bsp/lpcxpresso11u68/board.mk
@@ -32,7 +32,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = LPC11U68
diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk
index 62135c274..38679a66f 100644
--- a/hw/bsp/lpcxpresso1347/board.mk
+++ b/hw/bsp/lpcxpresso1347/board.mk
@@ -36,7 +36,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = LPC1347
diff --git a/hw/bsp/lpcxpresso1769/board.mk b/hw/bsp/lpcxpresso1769/board.mk
index 34b4d6dc0..ecafccc49 100644
--- a/hw/bsp/lpcxpresso1769/board.mk
+++ b/hw/bsp/lpcxpresso1769/board.mk
@@ -34,7 +34,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = LPC1769
diff --git a/hw/bsp/lpcxpresso51u68/board.mk b/hw/bsp/lpcxpresso51u68/board.mk
index 98bef6758..6e39bbcad 100644
--- a/hw/bsp/lpcxpresso51u68/board.mk
+++ b/hw/bsp/lpcxpresso51u68/board.mk
@@ -43,7 +43,7 @@ SRC_S += $(MCU_DIR)/gcc/startup_LPC51U68.S
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 JLINK_DEVICE = LPC51U68
 PYOCD_TARGET = LPC51U68
diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk
index b0d885866..a65d6eacb 100644
--- a/hw/bsp/mbed1768/board.mk
+++ b/hw/bsp/mbed1768/board.mk
@@ -34,7 +34,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = LPC1768
diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk
index 1a9f51191..c1147b4e9 100644
--- a/hw/bsp/mm32/family.mk
+++ b/hw/bsp/mm32/family.mk
@@ -30,7 +30,7 @@ INC += \
 	$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
 
 # flash target using on-board
 flash: flash-jlink
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
index e3cb90abc..7f823b1aa 100644
--- a/hw/bsp/msp432e4/family.mk
+++ b/hw/bsp/msp432e4/family.mk
@@ -34,7 +34,7 @@ INC += \
 SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = MSP432E401Y
diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk
index 3e901567c..26f8ae760 100644
--- a/hw/bsp/ngx4330/board.mk
+++ b/hw/bsp/ngx4330/board.mk
@@ -37,7 +37,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc/config_43xx
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = LPC4330
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index d8283a9e6..c79d7e654 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -42,7 +42,7 @@ SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_$(MCU_VARIANT).S
 ASFLAGS += -D__HEAP_SIZE=0
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = $(MCU_VARIANT)_xxaa
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index ff1d5aa3a..da0226afe 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -32,7 +32,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC121SC2AE
diff --git a/hw/bsp/nutiny_nuc125s/board.mk b/hw/bsp/nutiny_nuc125s/board.mk
index bb56e42ab..32cb56df1 100644
--- a/hw/bsp/nutiny_nuc125s/board.mk
+++ b/hw/bsp/nutiny_nuc125s/board.mk
@@ -28,7 +28,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC125SC2AE
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index 4f0ebf201..d24fdb6e2 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -34,7 +34,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc126/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC126VG4AE
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index 4d7aac7f5..b06d4873e 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -30,7 +30,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc100_120/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC120LE3
diff --git a/hw/bsp/nutiny_sdk_nuc505/board.mk b/hw/bsp/nutiny_sdk_nuc505/board.mk
index e8514347e..357cdec51 100644
--- a/hw/bsp/nutiny_sdk_nuc505/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc505/board.mk
@@ -39,7 +39,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc505/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = NUC505YO13Y
diff --git a/hw/bsp/rx/boards/gr_citrus/board.mk b/hw/bsp/rx/boards/gr_citrus/board.mk
index 0eba94610..4f2770725 100644
--- a/hw/bsp/rx/boards/gr_citrus/board.mk
+++ b/hw/bsp/rx/boards/gr_citrus/board.mk
@@ -11,7 +11,7 @@ MCU_DIR = hw/mcu/renesas/rx/rx63n
 LD_FILE = $(BOARD_PATH)/r5f5631fd.ld
 
 # For freeRTOS port source
-FREERTOS_PORT = RX600
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RX600
 
 # For flash-jlink target
 JLINK_DEVICE = R5F5631F
diff --git a/hw/bsp/rx/boards/rx65n_target/board.mk b/hw/bsp/rx/boards/rx65n_target/board.mk
index fc76d79fa..18c7d354d 100644
--- a/hw/bsp/rx/boards/rx65n_target/board.mk
+++ b/hw/bsp/rx/boards/rx65n_target/board.mk
@@ -12,7 +12,7 @@ MCU_DIR = hw/mcu/renesas/rx/rx65n
 LD_FILE = $(BOARD_PATH)/r5f565ne.ld
 
 # For freeRTOS port source
-FREERTOS_PORT = RX600
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RX600
 
 # For flash-jlink target
 JLINK_DEVICE = R5F565NE
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index ae55be75b..fcc163c02 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -37,4 +37,4 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd11/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index 208f23789..a4935e442 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -37,7 +37,7 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd21/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
index 783bed82a..aa3af5318 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd51/family.mk
@@ -38,7 +38,7 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd51/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
index 2d0d928ff..7d7ede0f0 100644
--- a/hw/bsp/same54xplainedpro/board.mk
+++ b/hw/bsp/same54xplainedpro/board.mk
@@ -38,7 +38,7 @@ INC += \
 	$(TOP)/hw/mcu/microchip/same54/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = ATSAME54P20
diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
index ba7088e44..5f53004ed 100644
--- a/hw/bsp/same70_qmtech/board.mk
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -44,7 +44,7 @@ INC += \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM7
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7
 
 # For flash-jlink target
 JLINK_DEVICE = SAME70N19B
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index cb2decf50..138e27b44 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -44,7 +44,7 @@ INC += \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM7
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7
 
 # For flash-jlink target
 JLINK_DEVICE = SAME70Q21B
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index deff6944c..1d228239e 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -42,7 +42,7 @@ INC += \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = ATSAMG55J19
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index bb1faeb7f..958b271ad 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -39,7 +39,7 @@ INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index f5c240ca2..a5011cce2 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -35,7 +35,7 @@ INC += \
   $(TOP)/hw/bsp/$(BOARD)
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = EFM32GG12B810F1024
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 39831e154..75d14d22c 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -37,4 +37,4 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index 3fb2e6e70..a9c6f4ec4 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -35,7 +35,7 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f103c8
diff --git a/hw/bsp/stm32f207nucleo/board.mk b/hw/bsp/stm32f207nucleo/board.mk
index fa7d28399..f418c6c04 100644
--- a/hw/bsp/stm32f207nucleo/board.mk
+++ b/hw/bsp/stm32f207nucleo/board.mk
@@ -39,7 +39,7 @@ INC += \
   $(TOP)/hw/bsp/$(BOARD)
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f207zg
diff --git a/hw/bsp/stm32f303disco/board.mk b/hw/bsp/stm32f303disco/board.mk
index 9dd27a857..371aba0f3 100644
--- a/hw/bsp/stm32f303disco/board.mk
+++ b/hw/bsp/stm32f303disco/board.mk
@@ -40,7 +40,7 @@ INC += \
   $(TOP)/hw/bsp/$(BOARD)
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f303vc
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 9811d3371..48cf1427b 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -37,7 +37,7 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index 8482e6dd2..59e421180 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -51,4 +51,4 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7/r0p1
diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk
index 04222f3bb..72993bc66 100644
--- a/hw/bsp/stm32g4/family.mk
+++ b/hw/bsp/stm32g4/family.mk
@@ -38,7 +38,7 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index 096d04d0c..d2dda3c1b 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -53,5 +53,5 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM7/r0p1
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7/r0p1
 
diff --git a/hw/bsp/stm32l0538disco/board.mk b/hw/bsp/stm32l0538disco/board.mk
index e19101d64..434c94ef2 100644
--- a/hw/bsp/stm32l0538disco/board.mk
+++ b/hw/bsp/stm32l0538disco/board.mk
@@ -41,7 +41,7 @@ INC += \
   $(TOP)/hw/bsp/$(BOARD)
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = STM32L053R8
diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index d6f55e5f9..59d214673 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -39,7 +39,7 @@ INC += \
 	$(TOP)/$(BOARD_PATH)
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32wb/family.mk b/hw/bsp/stm32wb/family.mk
index f85c5badd..66f8ff4e2 100644
--- a/hw/bsp/stm32wb/family.mk
+++ b/hw/bsp/stm32wb/family.mk
@@ -38,7 +38,7 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/tm4c123/family.mk b/hw/bsp/tm4c123/family.mk
index 751076196..73b65f00c 100644
--- a/hw/bsp/tm4c123/family.mk
+++ b/hw/bsp/tm4c123/family.mk
@@ -33,4 +33,4 @@ SRC_C += \
 	$(MCU_DIR)/Source/GCC/tm4c123_startup.c
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk
index 0b32bdeb5..134098dac 100644
--- a/hw/bsp/xmc4000/family.mk
+++ b/hw/bsp/xmc4000/family.mk
@@ -37,4 +37,4 @@ INC += \
 	$(TOP)/$(MCU_DIR)/XMCLib/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM4F
+FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F

From a936bafb8c1e0c6f125fdae90ffe57bf0deed57c Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Wed, 9 Mar 2022 12:19:45 +0000
Subject: [PATCH 1036/2085] add support for renesas ra family of mcus

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 src/common/tusb_mcu.h                |  2 +-
 src/portable/renesas/link/dcd_link.c |  5 ++-
 src/portable/renesas/link/hcd_link.c |  5 ++-
 src/portable/renesas/link/link_ra.h  | 64 ++++++++++++++++++++++++++++
 src/tusb_option.h                    |  2 +
 5 files changed, 75 insertions(+), 3 deletions(-)
 create mode 100644 src/portable/renesas/link/link_ra.h

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index c1cf2a810..5daa37f04 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -236,7 +236,7 @@
   #define TUP_DCD_ENDPOINT_MAX    7
 
 //------------- Renesas -------------//
-#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N, OPT_MCU_RAXXX)
   #define TUP_DCD_ENDPOINT_MAX    10
 
 //------------- GigaDevice -------------//
diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c
index 3aeda9e4c..19fbfe293 100644
--- a/src/portable/renesas/link/dcd_link.c
+++ b/src/portable/renesas/link/dcd_link.c
@@ -31,13 +31,16 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N)
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \
+			CFG_TUSB_MCU == OPT_MCU_RAXXX)
 
 #include "device/dcd.h"
 #include "link_type.h"
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
 #include "link_rx.h"
+#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
+#include "link_ra.h"
 #else
 #error "Unsupported MCU"
 #endif
diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c
index 46a4aae8f..2ada28105 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/link/hcd_link.c
@@ -27,13 +27,16 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N)
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \
+			CFG_TUSB_MCU == OPT_MCU_RAXXX)
 
 #include "host/hcd.h"
 #include "link_type.h"
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
 #include "link_rx.h"
+#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
+#include "link_ra.h"
 #else
 #error "Unsupported MCU"
 #endif
diff --git a/src/portable/renesas/link/link_ra.h b/src/portable/renesas/link/link_ra.h
new file mode 100644
index 000000000..b42def368
--- /dev/null
+++ b/src/portable/renesas/link/link_ra.h
@@ -0,0 +1,64 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Rafael Silva (@perigoso)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _LINK_RA_H_
+#define _LINK_RA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "link_type.h"
+
+/* renesas fsp api */
+#include "bsp_api.h"
+
+#define LINK_REG_BASE (0x40090000)
+
+TU_ATTR_ALWAYS_INLINE
+static inline void link_int_enable(uint8_t rhport)
+{
+	(void) rhport;
+	NVIC_EnableIRQ(TU_IRQn);
+}
+
+TU_ATTR_ALWAYS_INLINE
+static inline void link_int_disable(uint8_t rhport)
+{
+	(void) rhport;
+	NVIC_DisableIRQ(TU_IRQn);
+}
+
+// MCU specific PHY init
+static inline void link_phy_init(void)
+{
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LINK_RA_H_ */
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 3b054fc78..16bdedce5 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -127,6 +127,8 @@ typedef int make_iso_compilers_happy ;
 #define OPT_MCU_RX63X            1400 ///< Renesas RX63N/631
 #define OPT_MCU_RX65X            1401 ///< Renesas RX65N/RX651
 #define OPT_MCU_RX72N            1402 ///< Renesas RX72N
+#define OPT_MCU_RAXXX            1403 ///< Renesas RAxxx families
+
 
 // Mind Motion
 #define OPT_MCU_MM32F327X        1500 ///< Mind Motion MM32F327

From 0bf0e0b35f55e6906daeeb3615aa1e35503ee8e6 Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Wed, 9 Mar 2022 12:22:18 +0000
Subject: [PATCH 1037/2085] add renesas ra mcu family to supported devices docs

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 README.rst                   | 6 +++++-
 docs/reference/supported.rst | 2 ++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index 5b994c357..0877c14d1 100644
--- a/README.rst
+++ b/README.rst
@@ -48,7 +48,11 @@ The stack supports the following MCUs:
   - LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
 
 - **Raspberry Pi:** RP2040
-- **Renesas:** RX63N, RX65N, RX72N
+- **Renesas:**
+
+	- RX Series: 63N, 65N, 72N
+	- RA Series: RA2A1, RA2E1, RA2E2, RA2l1, RA4E1, RA4M1, RA4M2, RA4M3, RA4W1, RA6E1, RA6M1, RA6M2, RA6M3, RA6M4, RA6M5, RA6T1, RA6T2
+
 - **Silabs:** EFM32GG
 - **Sony:** CXD56
 - **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G4, L0, L1, L4, L4+
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 3c1b94623..02da501eb 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -61,6 +61,8 @@ Supported MCUs
 | Raspberry Pi | RP2040                | ✔      | ✔    | ✖         | rp2040            |              |
 +--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
 | Renesas      | RX  | 63N, 65N, 72N   | ✔      | ✔    | ✖         | link              |              |
+|              +-----+-----------------+--------+------+-----------+-------------------+--------------+
+|              | RA  | XXX             | ✔      | ✔    |           | link              |              |
 +--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
 | Silabs       | EFM32GG12             | ✔      |      | ✖         | dwc2              |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+

From 4c89776a275b9ae002d5f1dfe5a30fe538bae27e Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Wed, 9 Mar 2022 12:58:15 +0000
Subject: [PATCH 1038/2085] add renesas ek-ra4m3 board port

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 .github/workflows/build_arm.yml               |   1 +
 hw/bsp/board_mcu.h                            |   5 +-
 hw/bsp/ra/boards/ek_ra4m3/board.mk            |  15 +
 hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c          | 210 +++++++
 hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.ld         | 575 ++++++++++++++++++
 hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_cfg.h   |  35 ++
 .../boards/ek_ra4m3/fsp_cfg/bsp_clock_cfg.h   |  27 +
 .../ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h     | 260 ++++++++
 .../ra/boards/ek_ra4m3/fsp_cfg/r_ioport_cfg.h |   7 +
 .../ra/boards/ek_ra4m3/fsp_cfg/vector_data.h  |   5 +
 hw/bsp/ra/family.mk                           |  55 ++
 11 files changed, 1194 insertions(+), 1 deletion(-)
 create mode 100644 hw/bsp/ra/boards/ek_ra4m3/board.mk
 create mode 100644 hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
 create mode 100755 hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.ld
 create mode 100755 hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_cfg.h
 create mode 100644 hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_clock_cfg.h
 create mode 100644 hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
 create mode 100755 hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/r_ioport_cfg.h
 create mode 100644 hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/vector_data.h
 create mode 100644 hw/bsp/ra/family.mk

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 5a796a49b..935e83141 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -48,6 +48,7 @@ jobs:
         - 'mm32'
         - 'msp432e4'
         - 'nrf'
+        - 'ra'
         - 'rp2040'
         - 'samd11'
         - 'samd21'
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index b911e1e53..c8dccd3c5 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -127,13 +127,16 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_RP2040
   #include "pico.h"
-  
+
 #elif CFG_TUSB_MCU == OPT_MCU_EFM32GG
   #include "em_device.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X
   // no header needed
 
+#elif CFG_TUSB_MCU == OPT_MCU_RAXXX
+  #include "bsp_api.h"
+
 #elif CFG_TUSB_MCU == OPT_MCU_GD32VF103
   #include "gd32vf103.h"
 
diff --git a/hw/bsp/ra/boards/ek_ra4m3/board.mk b/hw/bsp/ra/boards/ek_ra4m3/board.mk
new file mode 100644
index 000000000..19f293e54
--- /dev/null
+++ b/hw/bsp/ra/boards/ek_ra4m3/board.mk
@@ -0,0 +1,15 @@
+CFLAGS += \
+	-mcpu=cortex-m33 \
+	-mfloat-abi=hard \
+	-mfpu=fpv5-sp-d16 \
+	-DCFG_TUSB_MCU=OPT_MCU_RAXXX
+
+FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m3
+FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m3_ek
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/ek_ra4m3.ld
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA4M3AF
+JLINK_IF     = SWD
diff --git a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
new file mode 100644
index 000000000..d79d7b425
--- /dev/null
+++ b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
@@ -0,0 +1,210 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Rafael Silva
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdio.h>
+
+#include "bsp/board.h"
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "r_ioport_api.h"
+#include "renesas.h"
+
+/* Key code for writing PRCR register. */
+#define BSP_PRV_PRCR_KEY	 (0xA500U)
+#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
+#define BSP_PRV_PRCR_LOCK	 ((BSP_PRV_PRCR_KEY) | 0x0U)
+
+#define SW1  (BSP_IO_PORT_00_PIN_05)
+#define SW2  (BSP_IO_PORT_00_PIN_06)
+#define LED1 (BSP_IO_PORT_04_PIN_15)
+#define LED3 (BSP_IO_PORT_04_PIN_00)
+#define LED2 (BSP_IO_PORT_04_PIN_04)
+
+/* ISR prototypes */
+void usbfs_interrupt_handler(void);
+void usbfs_resume_handler(void);
+void usbfs_d0fifo_handler(void);
+void usbfs_d1fifo_handler(void);
+
+BSP_DONT_REMOVE const
+	fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
+		[0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
+		[1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
+		[2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
+		[3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
+};
+const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
+	[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
+	[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
+	[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
+	[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
+};
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+	{.pin = BSP_IO_PORT_04_PIN_07,
+	 .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+	{.pin = BSP_IO_PORT_05_PIN_00,
+	 .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+	{.pin = BSP_IO_PORT_05_PIN_01,
+	 .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+	{.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+	{.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+	{.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+	{.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
+	{.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+	.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
+	.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void usbfs_interrupt_handler(void)
+{
+	IRQn_Type irq = R_FSP_CurrentIrqGet();
+	R_BSP_IrqStatusClear(irq);
+
+	tud_int_handler(0);
+}
+void usbfs_resume_handler(void)
+{
+	IRQn_Type irq = R_FSP_CurrentIrqGet();
+	R_BSP_IrqStatusClear(irq);
+
+	tud_int_handler(0);
+}
+void usbfs_d0fifo_handler(void)
+{
+	IRQn_Type irq = R_FSP_CurrentIrqGet();
+	R_BSP_IrqStatusClear(irq);
+
+	tud_int_handler(0);
+}
+void usbfs_d1fifo_handler(void)
+{
+	IRQn_Type irq = R_FSP_CurrentIrqGet();
+	R_BSP_IrqStatusClear(irq);
+
+	tud_int_handler(0);
+}
+
+void board_init(void)
+{
+	/* Configure pins. */
+	R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+
+	/* Enable USB_BASE */
+	R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
+	R_MSTP->MSTPCRB &= ~(1U << 11U);
+	R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
+
+#if CFG_TUSB_OS  == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+	/* Init systick */
+  	SysTick_Config(SystemCoreClock / 1000);
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+	R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
+	R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
+	R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
+}
+
+uint32_t board_button_read(void)
+{
+	bsp_io_level_t lvl;
+	R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
+	return lvl;
+}
+
+int board_uart_read(uint8_t *buf, int len)
+{
+	(void) buf;
+	(void) len;
+	return 0;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+	(void) buf;
+	(void) len;
+	return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+	system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+	return system_ticks;
+}
+#else
+#endif
+
+int close(int fd)
+{
+	(void) fd;
+	return -1;
+}
+int fstat(int fd, void *pstat)
+{
+	(void) fd;
+	(void) pstat;
+	return 0;
+}
+off_t lseek(int fd, off_t pos, int whence)
+{
+	(void) fd;
+	(void) pos;
+	(void) whence;
+	return 0;
+}
+int isatty(int fd)
+{
+	(void) fd;
+	return 1;
+}
diff --git a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.ld b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.ld
new file mode 100755
index 000000000..5bc335cb4
--- /dev/null
+++ b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.ld
@@ -0,0 +1,575 @@
+/* generated memory regions file - do not edit */
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x20000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x100000;
+DATA_FLASH_START = 0x08000000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x0100A100;
+OPTION_SETTING_LENGTH = 0x100;
+OPTION_SETTING_S_START = 0x0100A200;
+OPTION_SETTING_S_LENGTH = 0x100;
+ID_CODE_START = 0x00000000;
+ID_CODE_LENGTH = 0x0;
+SDRAM_START = 0x90000000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x4000000;
+OSPI_DEVICE_0_START = 0x68000000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x70000000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+/*
+    Linker File for Renesas FSP
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* This is a non-secure project if the OPTION_SETTING region is non-zero and it does not start at the base address for
+ * secure option settings (meaning the secure option settings were already allocated in the secure project). */
+__TZ_NS_PROJECT = LENGTH(OPTION_SETTING) && DEFINED(OPTION_SETTING_S_START) && (ABSOLUTE(OPTION_SETTING_START_S) != ORIGIN(OPTION_SETTING));
+
+/* This is a secure project if the option setting base address matches the option setting base address for secure
+ * option settings. This is also set for flat projects because the CPU runs in secure mode for flat projects.
+ * This is not defined for projects that do not support TrustZone. */
+__TZ_S_PROJECT = LENGTH(OPTION_SETTING) && DEFINED(OPTION_SETTING_S_START) && (ABSOLUTE(OPTION_SETTING_START_S) == ORIGIN(OPTION_SETTING));
+
+/* If a flat (secure) project has defined RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = __TZ_S_PROJECT && DEFINED(RAM_NS_BUFFER_LENGTH);
+
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+/* Define memory regions. */
+MEMORY
+{
+  FLASH (rx)      : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH
+  RAM (rwx)       : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+  DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+  QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+  OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  SDRAM (rwx)     : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+  OPTION_SETTING (r): ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+  OPTION_SETTING_S (r): ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+  ID_CODE (rx)    : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+OPTION_SETTING_START_NS = 0x0100A180;
+OPTION_SETTING_START_S = 0x0100A100;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ *   __ospi_device_0_start__
+ *   __ospi_device_0_end__
+ *   __ospi_device_0_code_size__
+ *   __ospi_device_0_region_max_size__
+ *   __ospi_device_0_region_start_address__
+ *   __ospi_device_0_region_end_address__
+ *   __ospi_device_1_start__
+ *   __ospi_device_1_end__
+ *   __ospi_device_1_code_size__
+ *   __ospi_device_1_region_max_size__
+ *   __ospi_device_1_region_start_address__
+ *   __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        __tz_FLASH_S = ABSOLUTE(FLASH_START);
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+
+        /* ROM Registers start at address 0x00000400 */
+        . = __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = __ROM_Start + 0x500;
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    __tz_RAM_S = ORIGIN(RAM);
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+
+    /* TrustZone Secure Gateway Stubs Section. */
+    .gnu.sgstubs : ALIGN (1024)
+    {
+        . = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+        __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+        _start_sg = .;
+        *(.gnu.sgstubs*)
+        . = ALIGN(32);
+        _end_sg = .;
+    } > FLASH
+
+    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(32768);
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
+    .qspi_non_retentive : AT (__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+    /* OSPI_DEVICE_0 section to be downloaded via debugger */
+    .OSPI_DEVICE_0 :
+    {
+        __ospi_device_0_start__ = .;
+        KEEP(*(.ospi_device_0*))
+        KEEP(*(.code_in_ospi_device_0*))
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__);
+    .ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__)
+    {
+        __ospi_device_0_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_0_non_retentive*))
+        __ospi_device_0_non_retentive_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+    /* OSPI_DEVICE_1 section to be downloaded via debugger */
+    .OSPI_DEVICE_1 :
+    {
+        __ospi_device_1_start__ = .;
+        KEEP(*(.ospi_device_1*))
+        KEEP(*(.code_in_ospi_device_1*))
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__);
+    .ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__)
+    {
+        __ospi_device_1_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_1_non_retentive*))
+        __ospi_device_1_non_retentive_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+    .ns_buffer (NOLOAD):
+    {
+        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+        KEEP(*(.ns_buffer*))
+    } > RAM
+
+    /* Data flash. */
+    .data_flash :
+    {
+        . = ORIGIN(DATA_FLASH);
+        __tz_DATA_FLASH_S = .;
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+
+        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+    } > DATA_FLASH
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_S = ORIGIN(SDRAM);
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_N = __SDRAM_End;
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_N = __ID_Code_End;
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING);
+
+    .option_setting :
+    {
+        __OPTION_SETTING_Start = .;
+        KEEP(*(.option_setting_ofs0))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_Start + 0x10 : __OPTION_SETTING_Start;
+        KEEP(*(.option_setting_dualsel))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_Start + 0x34 : __OPTION_SETTING_Start;
+        KEEP(*(.option_setting_sas))
+        __OPTION_SETTING_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_N = OPTION_SETTING_START_NS;
+
+    .option_setting_ns :
+    {
+        __OPTION_SETTING_NS_Start = .;
+        KEEP(*(.option_setting_ofs1))
+        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_banksel))
+        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps0))
+        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps1))
+        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps2))
+        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps0))
+        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps1))
+        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps2))
+        __OPTION_SETTING_NS_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+    .option_setting_s :
+    {
+        __OPTION_SETTING_S_Start = .;
+        KEEP(*(.option_setting_ofs1_sec))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sec))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec0))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec1))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec2))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec0))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec1))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec2))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs1_sel))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sel))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel0))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel1))
+        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel2))
+        __OPTION_SETTING_S_End = .;
+    } > OPTION_SETTING_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_cfg.h
new file mode 100755
index 000000000..a84d81e8d
--- /dev/null
+++ b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_cfg.h
@@ -0,0 +1,35 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+
+#include "board.h"
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+
+#undef RA_NOT_DEFINED
+#define BSP_CFG_RTOS (0)
+#if defined(_RA_BOOT_IMAGE)
+#define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV	      (3300)
+#define BSP_CFG_STACK_MAIN_BYTES      (0x400)
+#define BSP_CFG_HEAP_BYTES	      (0x400)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT		      (0)
+#define BSP_CFG_ERROR_LOG	      (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT     ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE	(0)
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE		(0)
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(1)
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..4f490f340
--- /dev/null
+++ b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,27 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+
+#define BSP_CFG_CLOCKS_SECURE	(0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ		(24000000)			   /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY	(2)				   /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE	(BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV		(BSP_CLOCKS_PLL_DIV_3)		   /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL		BSP_CLOCKS_PLL_MUL_24_0		   /* PLL Mul x24.0 */
+#define BSP_CFG_PLL2_SOURCE	(BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV	(BSP_CLOCKS_PLL_DIV_3)		   /* PLL2 Div /3 */
+#define BSP_CFG_PLL2_MUL	BSP_CLOCKS_PLL_MUL_24_0		   /* PLL2 Mul x24.0 */
+#define BSP_CFG_CLOCK_SOURCE	(BSP_CLOCKS_SOURCE_CLOCK_PLL)	   /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE	(BSP_CLOCKS_CLOCK_DISABLED)	   /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE	(BSP_CLOCKS_SOURCE_CLOCK_PLL2)	   /* UCLK Src: PLL2 */
+#define BSP_CFG_ICLK_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_2)	   /* ICLK Div /2 */
+#define BSP_CFG_PCLKA_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_2)	   /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_4)	   /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_4)	   /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_2)	   /* PCLKD Div /2 */
+#define BSP_CFG_FCLK_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_4)	   /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_1)	   /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV		(BSP_CLOCKS_USB_CLOCK_DIV_4)	   /* UCLK Div /4 */
+
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..0449bb4bc
--- /dev/null
+++ b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
@@ -0,0 +1,260 @@
+/* generated configuration header file through renesas e2 studio */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_info.h"
+
+#define BSP_CFG_MCU_PART_SERIES (4)
+#define BSP_MCU_R7FA4M3AF3CFB
+#define BSP_ROM_SIZE_BYTES	  (1048576)
+#define BSP_RAM_SIZE_BYTES	  (131072)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (144)
+
+#define BSP_MCU_GROUP_RA4M3 (1)
+#define BSP_LOCO_HZ	    (32768)
+#define BSP_MOCO_HZ	    (8000000)
+#define BSP_SUB_CLOCK_HZ    (32768)
+#if BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+#define BSP_HOCO_HZ (18000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+#define BSP_HOCO_HZ (20000000)
+#else
+#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+
+#define BSP_CFG_FLL_ENABLE (0)
+
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES	(112U)
+#define BSP_MCU_VBATT_SUPPORT		(1)
+
+#if defined(_RA_TZ_SECURE)
+#define BSP_TZ_SECURE_BUILD    (1)
+#define BSP_TZ_NONSECURE_BUILD (0)
+#elif defined(_RA_TZ_NONSECURE)
+#define BSP_TZ_SECURE_BUILD    (0)
+#define BSP_TZ_NONSECURE_BUILD (1)
+#else
+#define BSP_TZ_SECURE_BUILD    (0)
+#define BSP_TZ_NONSECURE_BUILD (0)
+#endif
+
+/* TrustZone Settings */
+#define BSP_TZ_CFG_INIT_SECURE_ONLY   (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+#define BSP_TZ_CFG_SKIP_INIT	      (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
+
+/* CMSIS TrustZone Settings */
+#define SCB_CSR_AIRCR_INIT	   (1)
+#define SCB_AIRCR_BFHFNMINS_VAL	   (0)
+#define SCB_AIRCR_SYSRESETREQS_VAL (1)
+#define SCB_AIRCR_PRIS_VAL	   (0)
+#define TZ_FPU_NS_USAGE		   (1)
+#define SCB_NSACR_CP10_11_VAL	   (3U)
+
+#define FPU_FPCCR_TS_VAL	(1U)
+#define FPU_FPCCR_CLRONRETS_VAL (1)
+
+#define FPU_FPCCR_CLRONRET_VAL (1)
+
+/* The C-Cache line size that is configured during startup. */
+#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
+
+/* Type 1 Peripheral Security Attribution */
+
+/* Peripheral Security Attribution Register (PSAR) Settings */
+#define BSP_TZ_CFG_PSARB                                                                                             \
+	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ |   \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ |   \
+	 (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ |             \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */
+#define BSP_TZ_CFG_PSARC                                                                                             \
+	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ |     \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ |  \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */
+#define BSP_TZ_CFG_PSARD                                                                                               \
+	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ |     \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ |     \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ |                \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ |     \
+	 0xffae07f0) /* Unused */
+#define BSP_TZ_CFG_PSARE                                                                                             \
+	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ |    \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ |   \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+	 (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ |              \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ |              \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ |              \
+	 (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */
+#define BSP_TZ_CFG_MSSAR                                                                                              \
+	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+	 0xfffffffc) /* Unused */
+
+/* Type 2 Peripheral Security Attribution */
+
+/* Security attribution for Cache registers. */
+#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+
+/* Security attribution for RSTSRn registers. */
+#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+
+/* Security attribution for registers of LVD channels. */
+#define BSP_TZ_CFG_LVDSAR                                              \
+	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+	 0xFFFFFFFCU)
+
+/* Security attribution for LPM registers. */
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+/* Deep Standby Interrupt Factor Security Attribution Register. */
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+
+/* Security attribution for CGC registers. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for Battery Backup registers. */
+#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+
+/* Security attribution for registers for IRQ channels. */
+#define BSP_TZ_CFG_ICUSARA                                                                                                    \
+	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ |                                                       \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ |                                                       \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ |                                                       \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ |                                                       \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ |                                                       \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ |                                                       \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ |                                                       \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ |                                                       \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ |                                                       \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ |   \
+	 (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ |                                                     \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ |                                                     \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U)
+
+/* Security attribution for NMI registers. */
+#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+
+/* Security attribution for registers for DMAC channels */
+#define BSP_TZ_CFG_ICUSARC                                               \
+	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U)
+
+/* Security attribution registers for SELSR0. */
+#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+
+/* Security attribution registers for WUPEN0. */
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+
+/* Security attribution registers for WUPEN1. */
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+
+/* Set DTCSTSAR if the Secure program uses the DTC. */
+// #if RA_NOT_DEFINED == RA_NOT_DEFINED
+#define BSP_TZ_CFG_DTC_USED (0U)
+// #else
+// #define BSP_TZ_CFG_DTC_USED (1U)
+// #endif
+
+/* Security attribution of FLWT and FCKMHZ registers. */
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
+#define BSP_TZ_CFG_FSAR (0xFEFEU)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_FSAR (0xFFFFU)
+#endif
+
+/* Security attribution for SRAM registers. */
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+#define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U)
+
+/* Security attribution for Standby RAM registers. */
+#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+
+/* Security attribution for the DMAC Bus Master MPU settings. */
+/* The DMAC Bus Master MPU settings should align with the DMAC channel settings.
+ */
+#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+
+/* Security Attribution Register A for BUS Control registers. */
+#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+/* Security Attribution Register B for BUS Control registers. */
+#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+
+#define OFS_SEQ1	     0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2	     (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3	     (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4	     (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5	     (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+/* Option Function Select Register 1 Security Attribution */
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+#define BSP_CFG_ROM_REG_OFS1_SEL \
+	(0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+#else
+#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+#endif
+
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+
+/* Used to create IELS values for the interrupt initialization table
+ * g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
+/* Dual Mode Select Register */
+#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU)
+/* Block Protection Register 0 */
+#define BSP_CFG_ROM_REG_BPS0 (~(0U))
+/* Block Protection Register 1 */
+#define BSP_CFG_ROM_REG_BPS1 (~(0U))
+/* Block Protection Register 2 */
+#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU)
+/* Permanent Block Protection Register 0 */
+#define BSP_CFG_ROM_REG_PBPS0 (~(0U))
+/* Permanent Block Protection Register 1 */
+#define BSP_CFG_ROM_REG_PBPS1 (~(0U))
+/* Permanent Block Protection Register 2 */
+#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU)
+/* Security Attribution for Block Protection Register 0 (If any blocks are
+ * marked as protected in the secure application, then mark them as secure) */
+#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+/* Security Attribution for Block Protection Register 1 (If any blocks are
+ * marked as protected in the secure application, then mark them as secure) */
+#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+/* Security Attribution for Block Protection Register 2 (If any blocks are
+ * marked as protected in the secure application, then mark them as secure) */
+#define BSP_CFG_ROM_REG_BPS_SEL2    (0xFFFFFFFFU)
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/r_ioport_cfg.h
new file mode 100755
index 000000000..cb7c07932
--- /dev/null
+++ b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,7 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/vector_data.h
new file mode 100644
index 000000000..37739c12a
--- /dev/null
+++ b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/vector_data.h
@@ -0,0 +1,5 @@
+/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
+#define TU_IRQn 0
+#define USBFS_RESUME_IRQn 1
+#define USBFS_FIFO_0_IRQn 2
+#define USBFS_FIFO_1_IRQn 3
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
new file mode 100644
index 000000000..6b7f43345
--- /dev/null
+++ b/hw/bsp/ra/family.mk
@@ -0,0 +1,55 @@
+DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
+
+# Cross Compiler for RA
+CROSS_COMPILE = arm-none-eabi-
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+	-Wno-error=undef \
+	-Wno-error=strict-prototypes \
+	-Wno-error=cast-align \
+	-Wno-error=cast-qual \
+	-Wno-error=unused-but-set-variable \
+	-Wno-error=unused-variable \
+	-mthumb \
+	-nostdlib \
+	-nostartfiles \
+	-ffunction-sections \
+	-fdata-sections \
+	-ffreestanding
+
+SRC_C += \
+	src/portable/renesas/link/dcd_link.c \
+	src/portable/renesas/link/hcd_link.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_common.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_delay.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_guard.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_io.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_irq.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_security.c \
+	hw/mcu/renesas/fsp/ra/fsp/src/r_ioport/r_ioport.c \
+	$(FSP_BOARD_DIR)/board_init.c \
+	$(FSP_BOARD_DIR)/board_leds.c
+
+INC += \
+  	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(BOARD_PATH)/fsp_cfg \
+	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc \
+	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/api \
+	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/instances \
+	$(TOP)/$(FSP_MCU_DIR) \
+	$(TOP)/$(FSP_BOARD_DIR)
+
+# For freeRTOS port source
+# hack to use the port provided by renesas
+FREERTOS_PORT = hw/mcu/renesas/fsp/ra/fsp/src/rm_freertos_port

From e7027efe7a53fcc3eb383750b8837c91d1d2d31d Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Wed, 9 Mar 2022 14:12:01 +0000
Subject: [PATCH 1039/2085] add contributions to docs

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 CONTRIBUTORS.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index 5726169f8..50a33ae33 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -119,6 +119,7 @@ Notable contributors
 
 -  Port DCD Synopsys to support Silabs EFM32GG12 with SLTB009A board
 -  Rewrite documentation in rst and setup for readthedocs
+-  Generalize Renesas driver and support RA family with EK-RA4M3 board
 
 
 `Raspberry Pi Team <https://github.com/raspberrypi>`__

From c529d0b4405aa33b4793d03ce82568990c3f507c Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Wed, 9 Mar 2022 15:55:35 +0000
Subject: [PATCH 1040/2085] remove duplicate link register bit macros

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 src/portable/renesas/link/dcd_link.c  | 108 +++++++++++++-------------
 src/portable/renesas/link/hcd_link.c  |  98 +++++++++++------------
 src/portable/renesas/link/link_type.h |  98 ++++++++---------------
 3 files changed, 136 insertions(+), 168 deletions(-)

diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c
index 19fbfe293..f2334140a 100644
--- a/src/portable/renesas/link/dcd_link.c
+++ b/src/portable/renesas/link/dcd_link.c
@@ -32,7 +32,7 @@
 #define USE_SOF     0
 
 #if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \
-			CFG_TUSB_MCU == OPT_MCU_RAXXX)
+      CFG_TUSB_MCU == OPT_MCU_RAXXX)
 
 #include "device/dcd.h"
 #include "link_type.h"
@@ -245,7 +245,7 @@ static bool pipe0_xfer_in(void)
     }
   }
   if (len < mps)
-    LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL;
+    LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
   pipe->remaining = rem - len;
   return false;
 }
@@ -268,7 +268,7 @@ static bool pipe0_xfer_out(void)
     }
   }
   if (len < mps)
-    LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
+    LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
@@ -287,7 +287,7 @@ static bool pipe_xfer_in(unsigned num)
     return true;
   }
 
-  LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
+  LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
   const unsigned len  = TU_MIN(rem, mps);
@@ -301,7 +301,7 @@ static bool pipe_xfer_in(unsigned num)
     }
   }
   if (len < mps)
-    LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
+    LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
   LINK_REG->D0FIFOSEL = 0;
   while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
@@ -313,7 +313,7 @@ static bool pipe_xfer_out(unsigned num)
   pipe_state_t  *pipe = &_dcd.pipe[num];
   const unsigned rem  = pipe->remaining;
 
-  LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_8;
+  LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT;
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
   const unsigned vld  = LINK_REG->D0FIFOCTR_b.DTLN;
@@ -328,7 +328,7 @@ static bool pipe_xfer_out(unsigned num)
     }
   }
   if (len < mps)
-    LINK_REG->D0FIFOCTR = USB_FIFOCTR_BCLR;
+    LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
   LINK_REG->D0FIFOSEL = 0;
   while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
@@ -342,13 +342,13 @@ static bool pipe_xfer_out(unsigned num)
 static void process_setup_packet(uint8_t rhport)
 {
   uint16_t setup_packet[4];
-  if (0 == (LINK_REG->INTSTS0 & USB_IS0_VALID)) return;
-  LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
+  if (0 == (LINK_REG->INTSTS0 & LINK_REG_INTSTS0_VALID_Msk)) return;
+  LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
   setup_packet[0] = tu_le16toh(LINK_REG->USBREQ);
   setup_packet[1] = LINK_REG->USBVAL;
   setup_packet[2] = LINK_REG->USBINDX;
   setup_packet[3] = LINK_REG->USBLENG;
-  LINK_REG->INTSTS0 = ~USB_IS0_VALID;
+  LINK_REG->INTSTS0 = ~((uint16_t)LINK_REG_INTSTS0_VALID_Msk);
   dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
 }
 
@@ -356,7 +356,7 @@ static void process_status_completion(uint8_t rhport)
 {
   uint8_t ep_addr;
   /* Check the data stage direction */
-  if (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) {
+  if (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) {
     /* IN transfer. */
     ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
   } else {
@@ -370,12 +370,12 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
 {
   /* configure fifo direction and access unit settings */
   if (ep_addr) { /* IN, 2 bytes */
-    LINK_REG->CFIFOSEL =
-      USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
-    while (!(LINK_REG->CFIFOSEL & USB_FIFOSEL_TX)) ;
+    LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
+             (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
+    while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
   } else { /* OUT, a byte */
-    LINK_REG->CFIFOSEL = USB_FIFOSEL_MBW_8;
-    while (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) ;
+    LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
+    while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
   }
 
   pipe_state_t *pipe = &_dcd.pipe[0];
@@ -388,11 +388,11 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
       TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80));
       pipe0_xfer_in();
     }
-    LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF;
+    LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
   } else {
     /* ZLP */
     pipe->buf        = NULL;
-    LINK_REG->DCPCTR = USB_PIPECTR_CCPL | USB_PIPECTR_PID_BUF;
+    LINK_REG->DCPCTR = LINK_REG_DCPCTR_CCPL_Msk | LINK_REG_PIPE_CTR_PID_BUF;
   }
   return true;
 }
@@ -416,7 +416,7 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
     } else { /* ZLP */
       LINK_REG->D0FIFOSEL = num;
       pipe_wait_for_ready(num);
-      LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
+      LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
       LINK_REG->D0FIFOSEL = 0;
       while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
     }
@@ -429,11 +429,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
     if (pt) {
       const unsigned     mps = edpt_max_packet_size(num);
       volatile uint16_t *ctr = get_pipectr(num);
-      if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
+      if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK;
       pt->TRE   = TU_BIT(8);
       pt->TRN   = (total_bytes + mps - 1) / mps;
       pt->TRENB = 1;
-      *ctr = USB_PIPECTR_PID_BUF;
+      *ctr = LINK_REG_PIPE_CTR_PID_BUF;
     }
   }
   //  TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
@@ -487,7 +487,7 @@ static void process_bus_reset(uint8_t rhport)
 {
   LINK_REG->BEMPENB = 1;
   LINK_REG->BRDYENB = 1;
-  LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
+  LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
   LINK_REG->D0FIFOSEL = 0;
   while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   LINK_REG->D1FIFOSEL = 0;
@@ -497,7 +497,7 @@ static void process_bus_reset(uint8_t rhport)
   for (int i = 1; i <= 5; ++i) {
     LINK_REG->PIPESEL = i;
     LINK_REG->PIPECFG = 0;
-    *ctr = USB_PIPECTR_ACLRM;
+    *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk;
     *ctr = 0;
     ++ctr;
     *tre = TU_BIT(8);
@@ -506,7 +506,7 @@ static void process_bus_reset(uint8_t rhport)
   for (int i = 6; i <= 9; ++i) {
     LINK_REG->PIPESEL = i;
     LINK_REG->PIPECFG = 0;
-    *ctr = USB_PIPECTR_ACLRM;
+    *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk;
     *ctr = 0;
     ++ctr;
   }
@@ -553,8 +553,9 @@ void dcd_init(uint8_t rhport)
 
   /* Setup default control pipe */
   LINK_REG->DCPMAXP_b.MXPS = 64;
-  LINK_REG->INTENB0 = USB_IS0_VBINT | USB_IS0_BRDY | USB_IS0_BEMP | USB_IS0_DVST | USB_IS0_CTRT |
-          (USE_SOF ? USB_IS0_SOFR : 0) | USB_IS0_RESM;
+  LINK_REG->INTENB0 = LINK_REG_INTSTS0_VBINT_Msk | LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk |
+          LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_CTRT_Msk | (USE_SOF ? LINK_REG_INTSTS0_SOFR_Msk : 0) |
+          LINK_REG_INTSTS0_RESM_Msk;
   LINK_REG->BEMPENB = 1;
   LINK_REG->BRDYENB = 1;
 
@@ -633,21 +634,21 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   LINK_REG->PIPESEL = num;
   LINK_REG->PIPEMAXP = mps;
   volatile uint16_t *ctr = get_pipectr(num);
-  *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
+  *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk;
   *ctr = 0;
   unsigned cfg = (dir << 4) | epn;
   if (xfer == TUSB_XFER_BULK) {
-    cfg |= (USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB);
+    cfg |= (LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk);
   } else if (xfer == TUSB_XFER_INTERRUPT) {
-    cfg |= USB_PIPECFG_INT;
+    cfg |= LINK_REG_PIPECFG_TYPE_ISO;
   } else {
-    cfg |= (USB_PIPECFG_ISO | USB_PIPECFG_DBLB);
+    cfg |= (LINK_REG_PIPECFG_TYPE_INT | LINK_REG_PIPECFG_DBLB_Msk);
   }
   LINK_REG->PIPECFG = cfg;
   LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
   LINK_REG->BRDYENB |= TU_BIT(num);
   if (dir || (xfer != TUSB_XFER_BULK)) {
-    *ctr = USB_PIPECTR_PID_BUF;
+    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
   }
   // TU_LOG1("O %d %x %x\r\n", LINK_REG->PIPESEL, LINK_REG->PIPECFG, LINK_REG->PIPEMAXP);
   dcd_int_enable(rhport);
@@ -709,8 +710,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   if (!ctr) return;
   dcd_int_disable(rhport);
   const uint32_t pid = *ctr & 0x3;
-  *ctr = pid | USB_PIPECTR_PID_STALL;
-  *ctr = USB_PIPECTR_PID_STALL;
+  *ctr = pid | LINK_REG_PIPE_CTR_PID_STALL;
+  *ctr = LINK_REG_PIPE_CTR_PID_STALL;
   dcd_int_enable(rhport);
 }
 
@@ -719,15 +720,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
   if (!ctr) return;
   dcd_int_disable(rhport);
-  *ctr = USB_PIPECTR_SQCLR;
+  *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk;
 
   if (tu_edpt_dir(ep_addr)) { /* IN */
-    *ctr = USB_PIPECTR_PID_BUF;
+    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
   } else {
     const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
     LINK_REG->PIPESEL = num;
     if (LINK_REG->PIPECFG_b.TYPE != 1) {
-      *ctr = USB_PIPECTR_PID_BUF;
+      *ctr = LINK_REG_PIPE_CTR_PID_BUF;
     }
   }
   dcd_int_enable(rhport);
@@ -742,39 +743,40 @@ void dcd_int_handler(uint8_t rhport)
 
   unsigned is0 = LINK_REG->INTSTS0;
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  LINK_REG->INTSTS0 = ~((USB_IS0_CTRT | USB_IS0_DVST | USB_IS0_SOFR | USB_IS0_RESM | USB_IS0_VBINT) & is0) | USB_IS0_VALID;
-  if (is0 & USB_IS0_VBINT) {
+  LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_CTRT_Msk | LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_SOFR_Msk |
+                         LINK_REG_INTSTS0_RESM_Msk | LINK_REG_INTSTS0_VBINT_Msk) & is0) | LINK_REG_INTSTS0_VALID_Msk;
+  if (is0 & LINK_REG_INTSTS0_VBINT_Msk) {
     if (LINK_REG->INTSTS0_b.VBSTS) {
       dcd_connect(rhport);
     } else {
       dcd_disconnect(rhport);
     }
   }
-  if (is0 & USB_IS0_RESM) {
+  if (is0 & LINK_REG_INTSTS0_RESM_Msk) {
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
 #if (0==USE_SOF)
     LINK_REG->INTENB0_b.SOFE = 0;
 #endif
   }
-  if ((is0 & USB_IS0_SOFR) && LINK_REG->INTENB0_b.SOFE) {
+  if ((is0 & LINK_REG_INTSTS0_SOFR_Msk) && LINK_REG->INTENB0_b.SOFE) {
     // USBD will exit suspended mode when SOF event is received
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
 #if (0 == USE_SOF)
     LINK_REG->INTENB0_b.SOFE = 0;
 #endif
   }
-  if (is0 & USB_IS0_DVST) {
-    switch (is0 & USB_IS0_DVSQ) {
-    case USB_IS0_DVSQ_DEF:
+  if (is0 & LINK_REG_INTSTS0_DVST_Msk) {
+    switch (is0 & LINK_REG_INTSTS0_DVSQ_Msk) {
+    case LINK_REG_INTSTS0_DVSQ_STATE_DEF:
       process_bus_reset(rhport);
       break;
-    case USB_IS0_DVSQ_ADDR:
+    case LINK_REG_INTSTS0_DVSQ_STATE_ADDR:
       process_set_address(rhport);
       break;
-    case USB_IS0_DVSQ_SUSP0:
-    case USB_IS0_DVSQ_SUSP1:
-    case USB_IS0_DVSQ_SUSP2:
-    case USB_IS0_DVSQ_SUSP3:
+    case LINK_REG_INTSTS0_DVSQ_STATE_SUSP0:
+    case LINK_REG_INTSTS0_DVSQ_STATE_SUSP1:
+    case LINK_REG_INTSTS0_DVSQ_STATE_SUSP2:
+    case LINK_REG_INTSTS0_DVSQ_STATE_SUSP3:
        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
 #if (0==USE_SOF)
       LINK_REG->INTENB0_b.SOFE = 1;
@@ -783,23 +785,23 @@ void dcd_int_handler(uint8_t rhport)
       break;
     }
   }
-  if (is0 & USB_IS0_CTRT) {
-    if (is0 & USB_IS0_CTSQ_SETUP) {
+  if (is0 & LINK_REG_INTSTS0_CTRT_Msk) {
+    if (is0 & LINK_REG_INTSTS0_CTSQ_CTRL_RDATA) {
       /* A setup packet has been received. */
       process_setup_packet(rhport);
-    } else if (0 == (is0 & USB_IS0_CTSQ_MSK)) {
+    } else if (0 == (is0 & LINK_REG_INTSTS0_CTSQ_Msk)) {
       /* A ZLP has been sent/received. */
       process_status_completion(rhport);
     }
   }
-  if (is0 & USB_IS0_BEMP) {
+  if (is0 & LINK_REG_INTSTS0_BEMP_Msk) {
     const unsigned s = LINK_REG->BEMPSTS;
     LINK_REG->BEMPSTS = 0;
     if (s & 1) {
       process_pipe0_bemp(rhport);
     }
   }
-  if (is0 & USB_IS0_BRDY) {
+  if (is0 & LINK_REG_INTSTS0_BRDY_Msk) {
     const unsigned m = LINK_REG->BRDYENB;
     unsigned s = LINK_REG->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c
index 2ada28105..940013c86 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/link/hcd_link.c
@@ -207,18 +207,18 @@ static bool pipe0_xfer_in(void)
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
-    LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
+    LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
     pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps)
-    LINK_REG->CFIFOCTR = USB_FIFOCTR_BCLR;
+    LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return true;
   }
-  LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF;
+  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
   return false;
 }
 
@@ -238,7 +238,7 @@ static bool pipe0_xfer_out(void)
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps)
-    LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL;
+    LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
   pipe->remaining = rem - len;
   return false;
 }
@@ -248,7 +248,7 @@ static bool pipe_xfer_in(unsigned num)
   pipe_state_t  *pipe = &_hcd.pipe[num];
   const unsigned rem  = pipe->remaining;
 
-  LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_8;
+  LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT;
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
   const unsigned vld  = LINK_REG->D0FIFOCTR_b.DTLN;
@@ -259,7 +259,7 @@ static bool pipe_xfer_in(unsigned num)
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps)
-    LINK_REG->D0FIFOCTR = USB_FIFOCTR_BCLR;
+    LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
   LINK_REG->D0FIFOSEL = 0;
   while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
@@ -280,7 +280,7 @@ static bool pipe_xfer_out(unsigned num)
     return true;
   }
 
-  LINK_REG->D0FIFOSEL = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
+  LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
   const unsigned len  = TU_MIN(rem, mps);
@@ -290,7 +290,7 @@ static bool pipe_xfer_out(unsigned num)
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps)
-    LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
+    LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
   LINK_REG->D0FIFOSEL = 0;
   while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
@@ -304,12 +304,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
 
   /* configure fifo direction and access unit settings */
   if (dir_in) { /* IN, a byte */
-    LINK_REG->CFIFOSEL = USB_FIFOSEL_MBW_8;
-    while (LINK_REG->CFIFOSEL & USB_FIFOSEL_TX) ;
+    LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
+    while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
   } else { /* OUT, 2 bytes */
-    LINK_REG->CFIFOSEL =
-      USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
-    while (!(LINK_REG->CFIFOSEL & USB_FIFOSEL_TX)) ;
+    LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
+             (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
+    while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
   }
 
   pipe_state_t *pipe = &_hcd.pipe[0];
@@ -325,15 +325,15 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
   } else { /* ZLP */
     pipe->buf        = NULL;
     if (!dir_in) { /* OUT */
-      LINK_REG->CFIFOCTR = USB_FIFOCTR_BVAL;
+      LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
     }
     if (dir_in == LINK_REG->DCPCFG_b.DIR) {
-      TU_ASSERT(USB_PIPECTR_PID_NAK == LINK_REG->DCPCTR_b.PID);
+      TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID);
       LINK_REG->DCPCTR_b.SQSET = 1;
       LINK_REG->DCPCFG_b.DIR = dir_in ^ 1;
     }
   }
-  LINK_REG->DCPCTR = USB_PIPECTR_PID_BUF;
+  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
   return true;
 }
 
@@ -355,7 +355,7 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u
     } else { /* ZLP */
       LINK_REG->D0FIFOSEL = num;
       pipe_wait_for_ready(num);
-      LINK_REG->D0FIFOCTR = USB_FIFOCTR_BVAL;
+      LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
       LINK_REG->D0FIFOSEL = 0;
       while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
     }
@@ -364,12 +364,12 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u
     volatile reg_pipetre_t *pt = get_pipetre(num);
     if (pt) {
       const unsigned     mps = edpt_max_packet_size(num);
-      if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
+      if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK;
       pt->TRE   = TU_BIT(8);
       pt->TRN   = (buflen + mps - 1) / mps;
       pt->TRENB = 1;
     }
-    *ctr = USB_PIPECTR_PID_BUF;
+    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
   }
   return true;
 }
@@ -403,10 +403,10 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
   unsigned result;
   uint16_t volatile *ctr = get_pipectr(num);
   // TU_LOG1("NRDY %d %x\n", num, *ctr);
-  switch (*ctr & USB_PIPECTR_PID_MSK) {
+  switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) {
     default: return;
-    case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break;
-    case USB_PIPECTR_PID_NAK:   result = XFER_RESULT_FAILED;  break;
+    case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
+    case LINK_REG_PIPE_CTR_PID_NAK:   result = XFER_RESULT_FAILED;  break;
   }
   pipe_state_t *pipe = &_hcd.pipe[num];
   hcd_event_xfer_complete(pipe->dev, pipe->ep,
@@ -464,10 +464,10 @@ bool hcd_init(uint8_t rhport)
   LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
 
   /* Setup default control pipe */
-  LINK_REG->DCPCFG = USB_PIPECFG_SHTNAK;
+  LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk;
   LINK_REG->DCPMAXP = 64;
-  LINK_REG->INTENB0 = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP;
-  LINK_REG->INTENB1 = USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH;
+  LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk;
+  LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk;
   LINK_REG->BEMPENB = 1;
   LINK_REG->NRDYENB = 1;
   LINK_REG->BRDYENB = 1;
@@ -505,7 +505,7 @@ bool hcd_port_connect_status(uint8_t rhport)
 
 void hcd_port_reset(uint8_t rhport)
 {
-  LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
+  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
   while (LINK_REG->DCPCTR_b.PBUSY) ;
   hcd_int_disable(rhport);
   LINK_REG->DVSTCTR0_b.UACT = 0;
@@ -530,8 +530,8 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
   (void)rhport;
   switch (LINK_REG->DVSTCTR0_b.RHST) {
     default: return TUSB_SPEED_INVALID;
-    case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL;
-    case USB_DVSTCTR0_LOW:  return TUSB_SPEED_LOW;
+    case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL;
+    case LINK_REG_DVSTCTR0_RHST_LS:  return TUSB_SPEED_LOW;
   }
 }
 
@@ -572,7 +572,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
   TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ);
 
-  LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
+  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
 
   _hcd.pipe[0].buf = NULL;
   _hcd.pipe[0].length = 8;
@@ -605,14 +605,14 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   const unsigned epn     = tu_edpt_number(ep_addr);
   const unsigned mps     = tu_edpt_packet_size(ep_desc);
   if (0 == epn) {
-    LINK_REG->DCPCTR = USB_PIPECTR_PID_NAK;
+    LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
     hcd_devtree_info_t devtree;
     hcd_devtree_get_info(dev_addr, &devtree);
     uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0];
     devadd += dev_addr;
     while (LINK_REG->DCPCTR_b.PBUSY) ;
     LINK_REG->DCPMAXP = (dev_addr << 12) | mps;
-    *devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW;
+    *devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS;
     _hcd.ctl_mps[dev_addr] = mps;
     return true;
   }
@@ -634,22 +634,22 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   LINK_REG->PIPESEL = num;
   LINK_REG->PIPEMAXP = (dev_addr << 12) | mps;
   volatile uint16_t *ctr = get_pipectr(num);
-  *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
+  *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk;
   *ctr = 0;
   unsigned cfg = ((1 ^ dir_in) << 4) | epn;
   if (xfer == TUSB_XFER_BULK) {
-    cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB;
+    cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk;
   } else if (xfer == TUSB_XFER_INTERRUPT) {
-    cfg |= USB_PIPECFG_INT;
+    cfg |= LINK_REG_PIPECFG_TYPE_ISO;
   } else {
-    cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
+    cfg |= LINK_REG_PIPECFG_TYPE_INT | LINK_REG_PIPECFG_DBLB_Msk;
   }
   LINK_REG->PIPECFG = cfg;
   LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
   LINK_REG->NRDYENB |= TU_BIT(num);
   LINK_REG->BRDYENB |= TU_BIT(num);
   if (!dir_in) {
-    *ctr = USB_PIPECTR_PID_BUF;
+    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
   }
   hcd_int_enable(rhport);
 
@@ -676,12 +676,12 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
     *ctr = pid & 2;
     *ctr = 0;
   }
-  *ctr = USB_PIPECTR_SQCLR;
+  *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk;
   unsigned const epn = tu_edpt_number(ep_addr);
   if (!epn) return true;
 
   if (!tu_edpt_dir(ep_addr)) { /* OUT */
-    *ctr = USB_PIPECTR_PID_BUF;
+    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
   }
   return true;
 }
@@ -702,44 +702,44 @@ void hcd_int_handler(uint8_t rhport)
   unsigned is1 = LINK_REG->INTSTS1;
   unsigned is0 = LINK_REG->INTSTS0;
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  LINK_REG->INTSTS1 = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1);
-  LINK_REG->INTSTS0 = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0);
+  LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1);
+  LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0);
   // TU_LOG1("IS %04x %04x\n", is0, is1);
   is1 &= LINK_REG->INTENB1;
   is0 &= LINK_REG->INTENB0;
 
-  if (is1 & USB_IS1_SACK) {
+  if (is1 & LINK_REG_INTSTS1_SACK_Msk) {
     /* Set DATA1 in advance for the next transfer. */
     LINK_REG->DCPCTR_b.SQSET = 1;
     hcd_event_xfer_complete(
       LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
   }
-  if (is1 & USB_IS1_SIGN) {
+  if (is1 & LINK_REG_INTSTS1_SIGN_Msk) {
     hcd_event_xfer_complete(
       LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
   }
-  if (is1 & USB_IS1_ATTCH) {
+  if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) {
     LINK_REG->DVSTCTR0_b.UACT = 1;
     _hcd.need_reset = true;
-    LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~USB_IS1_ATTCH) | USB_IS1_DTCH;
+    LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk;
     hcd_event_device_attach(rhport, true);
   }
-  if (is1 & USB_IS1_DTCH) {
+  if (is1 & LINK_REG_INTSTS1_DTCH_Msk) {
     LINK_REG->DVSTCTR0_b.UACT = 0;
     if (LINK_REG->DCPCTR_b.SUREQ)
       LINK_REG->DCPCTR_b.SUREQCLR = 1;
-    LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~USB_IS1_DTCH) | USB_IS1_ATTCH;
+    LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk;
     hcd_event_device_remove(rhport, true);
   }
 
-  if (is0 & USB_IS0_BEMP) {
+  if (is0 & LINK_REG_INTSTS0_BEMP_Msk) {
     const unsigned s = LINK_REG->BEMPSTS;
     LINK_REG->BEMPSTS = 0;
     if (s & 1) {
       process_pipe0_bemp(rhport);
     }
   }
-  if (is0 & USB_IS0_NRDY) {
+  if (is0 & LINK_REG_INTSTS0_NRDY_Msk) {
     const unsigned m = LINK_REG->NRDYENB;
     unsigned s = LINK_REG->NRDYSTS & m;
     LINK_REG->NRDYSTS = ~s;
@@ -753,7 +753,7 @@ void hcd_int_handler(uint8_t rhport)
       s &= ~TU_BIT(num);
     }
   }
-  if (is0 & USB_IS0_BRDY) {
+  if (is0 & LINK_REG_INTSTS0_BRDY_Msk) {
     const unsigned m = LINK_REG->BRDYENB;
     unsigned s = LINK_REG->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/link/link_type.h
index 33cf7879e..f1d0130cc 100644
--- a/src/portable/renesas/link/link_type.h
+++ b/src/portable/renesas/link/link_type.h
@@ -33,72 +33,6 @@
 extern "C" {
 #endif
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-#define USB_DVSTCTR0_LOW  (1u)
-#define USB_DVSTCTR0_FULL (2u)
-
-#define USB_FIFOSEL_TX	   ((uint16_t) (1u << 5))
-#define USB_FIFOSEL_BIGEND ((uint16_t) (1u << 8))
-#define USB_FIFOSEL_MBW_8  ((uint16_t) (0u << 10))
-#define USB_FIFOSEL_MBW_16 ((uint16_t) (1u << 10))
-#define USB_IS0_CTSQ	   ((uint16_t) (7u))
-#define USB_IS0_DVSQ	   ((uint16_t) (7u << 4))
-#define USB_IS0_VALID	   ((uint16_t) (1u << 3))
-#define USB_IS0_BRDY	   ((uint16_t) (1u << 8))
-#define USB_IS0_NRDY	   ((uint16_t) (1u << 9))
-#define USB_IS0_BEMP	   ((uint16_t) (1u << 10))
-#define USB_IS0_CTRT	   ((uint16_t) (1u << 11))
-#define USB_IS0_DVST	   ((uint16_t) (1u << 12))
-#define USB_IS0_SOFR	   ((uint16_t) (1u << 13))
-#define USB_IS0_RESM	   ((uint16_t) (1u << 14))
-#define USB_IS0_VBINT	   ((uint16_t) (1u << 15))
-#define USB_IS1_SACK	   ((uint16_t) (1u << 4))
-#define USB_IS1_SIGN	   ((uint16_t) (1u << 5))
-#define USB_IS1_EOFERR	   ((uint16_t) (1u << 6))
-#define USB_IS1_ATTCH	   ((uint16_t) (1u << 11))
-#define USB_IS1_DTCH	   ((uint16_t) (1u << 12))
-#define USB_IS1_BCHG	   ((uint16_t) (1u << 14))
-#define USB_IS1_OVRCR	   ((uint16_t) (1u << 15))
-
-#define USB_IS0_CTSQ_MSK   (7u)
-#define USB_IS0_CTSQ_SETUP (1u)
-#define USB_IS0_DVSQ_DEF   (1u << 4)
-#define USB_IS0_DVSQ_ADDR  (2u << 4)
-#define USB_IS0_DVSQ_SUSP0 (4u << 4)
-#define USB_IS0_DVSQ_SUSP1 (5u << 4)
-#define USB_IS0_DVSQ_SUSP2 (6u << 4)
-#define USB_IS0_DVSQ_SUSP3 (7u << 4)
-
-#define USB_PIPECTR_PID_MSK   (3u)
-#define USB_PIPECTR_PID_NAK   (0u)
-#define USB_PIPECTR_PID_BUF   (1u)
-#define USB_PIPECTR_PID_STALL (2u)
-#define USB_PIPECTR_CCPL      (1u << 2)
-#define USB_PIPECTR_SQMON     (1u << 6)
-#define USB_PIPECTR_SQCLR     (1u << 8)
-#define USB_PIPECTR_ACLRM     (1u << 9)
-#define USB_PIPECTR_INBUFM    (1u << 14)
-#define USB_PIPECTR_BSTS      (1u << 15)
-
-#define USB_FIFOCTR_DTLN (0x1FF)
-#define USB_FIFOCTR_FRDY (1u << 13)
-#define USB_FIFOCTR_BCLR (1u << 14)
-#define USB_FIFOCTR_BVAL (1u << 15)
-
-#define USB_PIPECFG_SHTNAK (1u << 7)
-#define USB_PIPECFG_DBLB   (1u << 9)
-#define USB_PIPECFG_BULK   (1u << 14)
-#define USB_PIPECFG_ISO	   (3u << 14)
-#define USB_PIPECFG_INT	   (2u << 14)
-
-#define FIFO_REQ_CLR  (1u)
-#define FIFO_COMPLETE (1u << 1)
-
-#define USB_DEVADD_LOW	(1u << 6)
-#define USB_DEVADD_FULL (2u << 6)
-
 /*--------------------------------------------------------------------*/
 /* Register Definitions                                           */
 /*--------------------------------------------------------------------*/
@@ -1651,6 +1585,38 @@ TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX tool
 #define LINK_REG_DPUSR1R_FS_DPINTE0_Pos	  (0UL)	       /* DPINTE0 (Bit 0) */
 #define LINK_REG_DPUSR1R_FS_DPINTE0_Msk	  (0x1UL)      /* DPINTE0 (Bitfield-Mask: 0x01) */
 
+/*--------------------------------------------------------------------*/
+/* Register Bit Utils                                           */
+/*--------------------------------------------------------------------*/
+#define LINK_REG_PIPE_CTR_PID_NAK   (0U << LINK_REG_PIPE_CTR_PID_Pos) /* NAK response */
+#define LINK_REG_PIPE_CTR_PID_BUF   (1U << LINK_REG_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */
+#define LINK_REG_PIPE_CTR_PID_STALL (2U << LINK_REG_PIPE_CTR_PID_Pos) /* STALL response */
+
+#define LINK_REG_DVSTCTR0_RHST_LS	(1U << LINK_REG_DVSTCTR0_RHST_Pos) /*  Low-speed connection */
+#define LINK_REG_DVSTCTR0_RHST_FS	(2U << LINK_REG_DVSTCTR0_RHST_Pos) /*  Full-speed connection */
+
+#define LINK_REG_DEVADD_USBSPD_LS (1U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Low-speed */
+#define LINK_REG_DEVADD_USBSPD_FS (2U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Full-speed */
+
+#define LINK_REG_CFIFOSEL_ISEL_WRITE	(1U << LINK_REG_CFIFOSEL_ISEL_Pos)	/* FIFO write AKA TX*/
+
+#define LINK_REG_FIFOSEL_BIGEND			(1U << LINK_REG_CFIFOSEL_BIGEND_Pos)	/* FIFO Big Endian */
+#define LINK_REG_FIFOSEL_MBW_8BIT			(0U << LINK_REG_CFIFOSEL_MBW_Pos)	/* 8-bit width */
+#define LINK_REG_FIFOSEL_MBW_16BIT			(1U << LINK_REG_CFIFOSEL_MBW_Pos)	/* 16-bit width */
+
+#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA (1U << LINK_REG_INTSTS0_CTSQ_Pos)
+
+#define LINK_REG_INTSTS0_DVSQ_STATE_DEF (1U << LINK_REG_INTSTS0_DVSQ_Pos) /* Default state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR (2U << LINK_REG_INTSTS0_DVSQ_Pos) /* Address state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0 (4U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1 (5U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2 (6U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3 (7U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
+
+#define LINK_REG_PIPECFG_TYPE_BULK (1U << LINK_REG_PIPECFG_TYPE_Pos)
+#define LINK_REG_PIPECFG_TYPE_INT (2U << LINK_REG_PIPECFG_TYPE_Pos)
+#define LINK_REG_PIPECFG_TYPE_ISO (3U << LINK_REG_PIPECFG_TYPE_Pos)
+
 #ifdef __cplusplus
 }
 #endif

From e0220c6594f08d5b402994f92c12fc92482e9115 Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Mon, 21 Mar 2022 15:59:08 +0000
Subject: [PATCH 1041/2085] fix int handling for host in ek_ra4m3 port

---
 hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c | 38 +++++++++++++++++++++++-----
 1 file changed, 31 insertions(+), 7 deletions(-)

diff --git a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
index d79d7b425..c2f2a0903 100644
--- a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
+++ b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
@@ -91,28 +91,52 @@ void usbfs_interrupt_handler(void)
 	IRQn_Type irq = R_FSP_CurrentIrqGet();
 	R_BSP_IrqStatusClear(irq);
 
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+	tuh_int_handler(0);
+#endif
+
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
 	tud_int_handler(0);
+#endif
 }
 void usbfs_resume_handler(void)
 {
 	IRQn_Type irq = R_FSP_CurrentIrqGet();
 	R_BSP_IrqStatusClear(irq);
 
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+	tuh_int_handler(0);
+#endif
+
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
 	tud_int_handler(0);
+#endif
 }
 void usbfs_d0fifo_handler(void)
 {
 	IRQn_Type irq = R_FSP_CurrentIrqGet();
 	R_BSP_IrqStatusClear(irq);
 
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+	tuh_int_handler(0);
+#endif
+
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
 	tud_int_handler(0);
+#endif
 }
 void usbfs_d1fifo_handler(void)
 {
 	IRQn_Type irq = R_FSP_CurrentIrqGet();
 	R_BSP_IrqStatusClear(irq);
 
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+	tuh_int_handler(0);
+#endif
+
+#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
 	tud_int_handler(0);
+#endif
 }
 
 void board_init(void)
@@ -125,17 +149,17 @@ void board_init(void)
 	R_MSTP->MSTPCRB &= ~(1U << 11U);
 	R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
 
-#if CFG_TUSB_OS  == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+	// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+	NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+	NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+	NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+	NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 	/* Init systick */
-  	SysTick_Config(SystemCoreClock / 1000);
+	SysTick_Config(SystemCoreClock / 1000);
 #endif
 }
 

From 60aae59eeb1f656bddf87f026fdba48735e03280 Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Mon, 21 Mar 2022 16:02:11 +0000
Subject: [PATCH 1042/2085] style code for consistency with existing codebase

---
 hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c          |  152 +-
 .../ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h     |  112 +-
 src/portable/renesas/link/dcd_link.c          |    8 +-
 src/portable/renesas/link/hcd_link.c          |   10 +-
 src/portable/renesas/link/link_ra.h           |    8 +-
 src/portable/renesas/link/link_rx.h           |   16 +-
 src/portable/renesas/link/link_type.h         | 1838 ++++++++---------
 7 files changed, 1074 insertions(+), 1070 deletions(-)

diff --git a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
index c2f2a0903..eab102de9 100644
--- a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
+++ b/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
@@ -50,35 +50,35 @@ void usbfs_d0fifo_handler(void);
 void usbfs_d1fifo_handler(void);
 
 BSP_DONT_REMOVE const
-	fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
-		[0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
-		[1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
-		[2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
-		[3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
+  fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
+    [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
+    [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
+    [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
+    [3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
 };
 const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
-	[0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
-	[1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
-	[2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
-	[3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
+  [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
+  [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
+  [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
+  [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
 };
 
 const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
-	{.pin = BSP_IO_PORT_04_PIN_07,
-	 .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-	{.pin = BSP_IO_PORT_05_PIN_00,
-	 .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-	{.pin = BSP_IO_PORT_05_PIN_01,
-	 .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-	{.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-	{.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-	{.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-	{.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
-	{.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
+  {.pin = BSP_IO_PORT_04_PIN_07,
+   .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = BSP_IO_PORT_05_PIN_00,
+   .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = BSP_IO_PORT_05_PIN_01,
+   .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+  {.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+  {.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+  {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
+  {.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
 
 const ioport_cfg_t g_bsp_pin_cfg = {
-	.number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
-	.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+  .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
+  .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
 };
 ioport_instance_ctrl_t g_ioport_ctrl;
 const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
@@ -88,78 +88,78 @@ const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_i
 //--------------------------------------------------------------------+
 void usbfs_interrupt_handler(void)
 {
-	IRQn_Type irq = R_FSP_CurrentIrqGet();
-	R_BSP_IrqStatusClear(irq);
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-	tuh_int_handler(0);
+  tuh_int_handler(0);
 #endif
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-	tud_int_handler(0);
+  tud_int_handler(0);
 #endif
 }
 void usbfs_resume_handler(void)
 {
-	IRQn_Type irq = R_FSP_CurrentIrqGet();
-	R_BSP_IrqStatusClear(irq);
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-	tuh_int_handler(0);
+  tuh_int_handler(0);
 #endif
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-	tud_int_handler(0);
+  tud_int_handler(0);
 #endif
 }
 void usbfs_d0fifo_handler(void)
 {
-	IRQn_Type irq = R_FSP_CurrentIrqGet();
-	R_BSP_IrqStatusClear(irq);
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-	tuh_int_handler(0);
+  tuh_int_handler(0);
 #endif
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-	tud_int_handler(0);
+  tud_int_handler(0);
 #endif
 }
 void usbfs_d1fifo_handler(void)
 {
-	IRQn_Type irq = R_FSP_CurrentIrqGet();
-	R_BSP_IrqStatusClear(irq);
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-	tuh_int_handler(0);
+  tuh_int_handler(0);
 #endif
 
 #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-	tud_int_handler(0);
+  tud_int_handler(0);
 #endif
 }
 
 void board_init(void)
 {
-	/* Configure pins. */
-	R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+  /* Configure pins. */
+  R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
 
-	/* Enable USB_BASE */
-	R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
-	R_MSTP->MSTPCRB &= ~(1U << 11U);
-	R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
+  /* Enable USB_BASE */
+  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
+  R_MSTP->MSTPCRB &= ~(1U << 11U);
+  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
-	// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-	NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-	NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
 #if CFG_TUSB_OS == OPT_OS_NONE
-	/* Init systick */
-	SysTick_Config(SystemCoreClock / 1000);
+  /* Init systick */
+  SysTick_Config(SystemCoreClock / 1000);
 #endif
 }
 
@@ -169,66 +169,66 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-	R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
-	R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
-	R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
+  R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
+  R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
+  R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
 }
 
 uint32_t board_button_read(void)
 {
-	bsp_io_level_t lvl;
-	R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
-	return lvl;
+  bsp_io_level_t lvl;
+  R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
+  return lvl;
 }
 
 int board_uart_read(uint8_t *buf, int len)
 {
-	(void) buf;
-	(void) len;
-	return 0;
+  (void) buf;
+  (void) len;
+  return 0;
 }
 
 int board_uart_write(void const *buf, int len)
 {
-	(void) buf;
-	(void) len;
-	return 0;
+  (void) buf;
+  (void) len;
+  return 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler(void)
 {
-	system_ticks++;
+  system_ticks++;
 }
 
 uint32_t board_millis(void)
 {
-	return system_ticks;
+  return system_ticks;
 }
 #else
 #endif
 
 int close(int fd)
 {
-	(void) fd;
-	return -1;
+  (void) fd;
+  return -1;
 }
 int fstat(int fd, void *pstat)
 {
-	(void) fd;
-	(void) pstat;
-	return 0;
+  (void) fd;
+  (void) pstat;
+  return 0;
 }
 off_t lseek(int fd, off_t pos, int whence)
 {
-	(void) fd;
-	(void) pos;
-	(void) whence;
-	return 0;
+  (void) fd;
+  (void) pos;
+  (void) whence;
+  return 0;
 }
 int isatty(int fd)
 {
-	(void) fd;
-	return 1;
+  (void) fd;
+  return 1;
 }
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
index 0449bb4bc..4ecda1c66 100644
--- a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
+++ b/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
@@ -69,40 +69,40 @@
 
 /* Peripheral Security Attribution Register (PSAR) Settings */
 #define BSP_TZ_CFG_PSARB                                                                                             \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ |   \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ |   \
-	 (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ |             \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ |   \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ |   \
+   (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ |             \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */
 #define BSP_TZ_CFG_PSARC                                                                                             \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ |     \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ |  \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ |     \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ |  \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */
 #define BSP_TZ_CFG_PSARD                                                                                               \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ |     \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ |     \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ |                \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ |     \
-	 0xffae07f0) /* Unused */
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ |     \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ |     \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ |                \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ |     \
+   0xffae07f0) /* Unused */
 #define BSP_TZ_CFG_PSARE                                                                                             \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ |    \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ |   \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
-	 (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ |              \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ |              \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ |              \
-	 (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ |    \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ |   \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+   (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ |              \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ |              \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ |              \
+   (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */
 #define BSP_TZ_CFG_MSSAR                                                                                              \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
-	 0xfffffffc) /* Unused */
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+   0xfffffffc) /* Unused */
 
 /* Type 2 Peripheral Security Attribution */
 
@@ -114,9 +114,9 @@
 
 /* Security attribution for registers of LVD channels. */
 #define BSP_TZ_CFG_LVDSAR                                              \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
-	 0xFFFFFFFCU)
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+   0xFFFFFFFCU)
 
 /* Security attribution for LPM registers. */
 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
@@ -137,34 +137,34 @@
 
 /* Security attribution for registers for IRQ channels. */
 #define BSP_TZ_CFG_ICUSARA                                                                                                    \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ |                                                       \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ |   \
-	 (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ |                                                     \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ |                                                     \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U)
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ |                                                       \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ |   \
+   (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ |                                                     \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ |                                                     \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U)
 
 /* Security attribution for NMI registers. */
 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
 
 /* Security attribution for registers for DMAC channels */
 #define BSP_TZ_CFG_ICUSARC                                               \
-	((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
-	 (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U)
+  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U)
 
 /* Security attribution registers for SELSR0. */
 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
@@ -222,7 +222,7 @@
 /* Option Function Select Register 1 Security Attribution */
 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
 #define BSP_CFG_ROM_REG_OFS1_SEL \
-	(0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+  (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
 #else
 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
 #endif
diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c
index f2334140a..bb7e3b60a 100644
--- a/src/portable/renesas/link/dcd_link.c
+++ b/src/portable/renesas/link/dcd_link.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Koji Kitayama
@@ -31,8 +31,10 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \
-      CFG_TUSB_MCU == OPT_MCU_RAXXX)
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
+                        CFG_TUSB_MCU == OPT_MCU_RX65X || \
+                        CFG_TUSB_MCU == OPT_MCU_RX72N || \
+                        CFG_TUSB_MCU == OPT_MCU_RAXXX)
 
 #include "device/dcd.h"
 #include "link_type.h"
diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c
index 940013c86..f60c49114 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/link/hcd_link.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji Kitayama
@@ -27,8 +27,10 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X || CFG_TUSB_MCU == OPT_MCU_RX72N || \
-			CFG_TUSB_MCU == OPT_MCU_RAXXX)
+#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
+                        CFG_TUSB_MCU == OPT_MCU_RX65X || \
+                        CFG_TUSB_MCU == OPT_MCU_RX72N || \
+                        CFG_TUSB_MCU == OPT_MCU_RAXXX)
 
 #include "host/hcd.h"
 #include "link_type.h"
@@ -488,7 +490,7 @@ void hcd_int_disable(uint8_t rhport)
 uint32_t hcd_frame_number(uint8_t rhport)
 {
   (void)rhport;
-  /* The device must be reset at least once after connection 
+  /* The device must be reset at least once after connection
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
   return LINK_REG->FRMNUM_b.FRNM;
diff --git a/src/portable/renesas/link/link_ra.h b/src/portable/renesas/link/link_ra.h
index b42def368..97618ef8f 100644
--- a/src/portable/renesas/link/link_ra.h
+++ b/src/portable/renesas/link/link_ra.h
@@ -41,15 +41,15 @@ extern "C" {
 TU_ATTR_ALWAYS_INLINE
 static inline void link_int_enable(uint8_t rhport)
 {
-	(void) rhport;
-	NVIC_EnableIRQ(TU_IRQn);
+  (void) rhport;
+  NVIC_EnableIRQ(TU_IRQn);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void link_int_disable(uint8_t rhport)
 {
-	(void) rhport;
-	NVIC_DisableIRQ(TU_IRQn);
+  (void) rhport;
+  NVIC_DisableIRQ(TU_IRQn);
 }
 
 // MCU specific PHY init
diff --git a/src/portable/renesas/link/link_rx.h b/src/portable/renesas/link/link_rx.h
index b15084bb3..62f2911c2 100644
--- a/src/portable/renesas/link/link_rx.h
+++ b/src/portable/renesas/link/link_rx.h
@@ -41,21 +41,21 @@ extern "C" {
 
 static inline void link_int_enable(uint8_t rhport)
 {
-	(void) rhport;
+  (void) rhport;
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
-	IEN(PERIB, INTB185) = 1;
+  IEN(PERIB, INTB185) = 1;
 #else
-	IEN(USB0, USBI0) = 1;
+  IEN(USB0, USBI0) = 1;
 #endif
 }
 
 static inline void link_int_disable(uint8_t rhport)
 {
-	(void) rhport;
+  (void) rhport;
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
-	IEN(PERIB, INTB185) = 0;
+  IEN(PERIB, INTB185) = 0;
 #else
-	IEN(USB0, USBI0) = 0;
+  IEN(USB0, USBI0) = 0;
 #endif
 }
 
@@ -63,9 +63,9 @@ static inline void link_int_disable(uint8_t rhport)
 static inline void link_phy_init(void)
 {
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
-	IR(PERIB, INTB185) = 0;
+  IR(PERIB, INTB185) = 0;
 #else
-	IR(USB0, USBI0) = 0;
+  IR(USB0, USBI0) = 0;
 #endif
 }
 
diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/link/link_type.h
index f1d0130cc..eaf0b1ec4 100644
--- a/src/portable/renesas/link/link_type.h
+++ b/src/portable/renesas/link/link_type.h
@@ -42,933 +42,933 @@ TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
 typedef struct TU_ATTR_PACKED {
-	union {
-		volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
+  union {
+    volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
 
-		struct {
-			uint16_t : 8;
-			volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
-			volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
-			uint16_t : 6;
-		} E_b;
-	};
+    struct {
+      uint16_t : 8;
+      volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
+      volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
+      uint16_t : 6;
+    } E_b;
+  };
 
-	union {
-		volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */
+  union {
+    volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */
 
-		struct {
-			volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */
-		} N_b;
-	};
+    struct {
+      volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */
+    } N_b;
+  };
 } LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */
 
 TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size");
 
 /* LINK_REG Structure */
 typedef struct TU_ATTR_PACKED {
-	union {
-		volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
-
-		struct {
-			volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */
-			uint16_t : 2;
-			volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */
-			volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
-			volatile uint16_t DRPD : 1;  /* [5..5] D+/D- Line Resistor Control */
-			volatile uint16_t DCFM : 1;  /* [6..6] Controller Function Select */
-			uint16_t : 1;
-			volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */
-			uint16_t : 1;
-			volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */
-			uint16_t : 5;
-		} SYSCFG_b;
-	};
-
-	union {
-		volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */
-
-		struct {
-			volatile uint16_t
-				BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
-			uint16_t : 12;
-		} BUSWAIT_b;
-	};
-
-	union {
-		volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */
-
-		struct {
-			volatile const uint16_t LNST : 2;  /* [1..0] USB Data Line Status Monitor */
-			volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */
-			uint16_t : 2;
-			volatile const uint16_t
-				SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
-			volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */
-			uint16_t : 7;
-			volatile const uint16_t
-				OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
-		} SYSSTS0_b;
-	};
-
-	union {
-		volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */
-
-		struct {
-			volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
-			uint16_t : 15;
-		} PLLSTA_b;
-	};
-
-	union {
-		volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */
-
-		struct {
-			volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */
-			uint16_t : 1;
-			volatile uint16_t UACT : 1;    /* [4..4] USB Bus Enable */
-			volatile uint16_t RESUME : 1;  /* [5..5] Resume Output */
-			volatile uint16_t USBRST : 1;  /* [6..6] USB Bus Reset Output */
-			volatile uint16_t RWUPE : 1;   /* [7..7] Wakeup Detection Enable */
-			volatile uint16_t WKUP : 1;    /* [8..8] Wakeup Output */
-			volatile uint16_t VBUSEN : 1;  /* [9..9] USB_VBUSEN Output Pin Control */
-			volatile uint16_t EXICEN : 1;  /* [10..10] USB_EXICEN Output Pin Control */
-			volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */
-			uint16_t : 4;
-		} DVSTCTR0_b;
-	};
-	volatile const uint16_t RESERVED;
-
-	union {
-		volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */
-
-		struct {
-			volatile uint16_t UTST : 4; /* [3..0] Test Mode */
-			uint16_t : 12;
-		} TESTMODE_b;
-	};
-	volatile const uint16_t RESERVED1;
-	volatile const uint32_t RESERVED2;
-
-	union {
-		volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */
-
-		struct {
-			union {
-				volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */
-				volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */
-			};
-
-			union {
-				volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */
-
-				struct {
-					volatile const uint8_t RESERVED3;
-					volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */
-				};
-			};
-		};
-	};
-
-	union {
-		volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */
-
-		struct {
-			union {
-				volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */
-				volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */
-			};
-
-			union {
-				volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */
-
-				struct {
-					volatile const uint8_t RESERVED4;
-					volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */
-				};
-			};
-		};
-	};
-
-	union {
-		volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */
-
-		struct {
-			union {
-				volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */
-				volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */
-			};
-
-			union {
-				volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */
-
-				struct {
-					volatile const uint8_t RESERVED5;
-					volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */
-				};
-			};
-		};
-	};
-
-	union {
-		volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */
-
-		struct {
-			volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */
-			uint16_t : 1;
-			volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */
-			uint16_t : 2;
-			volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */
-			uint16_t : 1;
-			volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */
-			uint16_t : 2;
-			volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
-			volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
-		} CFIFOSEL_b;
-	};
-
-	union {
-		volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */
-
-		struct {
-			volatile const uint16_t
-				DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
-			uint16_t : 1;
-			volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
-			volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-			volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
-		} CFIFOCTR_b;
-	};
-	volatile const uint32_t RESERVED6;
-
-	union {
-		volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */
-
-		struct {
-			volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
-			uint16_t : 4;
-			volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
-			uint16_t : 1;
-			volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
-			volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
-			volatile uint16_t
-				DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
-			volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
-			volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
-		} D0FIFOSEL_b;
-	};
-
-	union {
-		volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */
-
-		struct {
-			volatile const uint16_t
-				DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
-			uint16_t : 1;
-			volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
-			volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-			volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
-		} D0FIFOCTR_b;
-	};
-
-	union {
-		volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */
-
-		struct {
-			volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
-			uint16_t : 4;
-			volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
-			uint16_t : 1;
-			volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
-			volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
-			volatile uint16_t
-				DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
-			volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
-			volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
-		} D1FIFOSEL_b;
-	};
-
-	union {
-		volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */
-
-		struct {
-			volatile const uint16_t
-				DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
-			uint16_t : 1;
-			volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
-			volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-			volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
-		} D1FIFOCTR_b;
-	};
-
-	union {
-		volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
-
-		struct {
-			uint16_t : 8;
-			volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
-			volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
-			volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
-			volatile uint16_t CTRE : 1;  /* [11..11] Control Transfer Stage Transition Interrupt Enable */
-			volatile uint16_t DVSE : 1;  /* [12..12] Device State Transition Interrupt Enable */
-			volatile uint16_t SOFE : 1;  /* [13..13] Frame Number Update Interrupt Enable */
-			volatile uint16_t RSME : 1;  /* [14..14] Resume Interrupt Enable */
-			volatile uint16_t VBSE : 1;  /* [15..15] VBUS Interrupt Enable */
-		} INTENB0_b;
-	};
-
-	union {
-		volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */
-
-		struct {
-			volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */
-			uint16_t : 3;
-			volatile uint16_t SACKE : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Enable */
-			volatile uint16_t SIGNE : 1;   /* [5..5] Setup Transaction Error Interrupt Enable */
-			volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */
-			uint16_t : 4;
-			volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */
-			volatile uint16_t DTCHE : 1;  /* [12..12] Disconnection Detection Interrupt Enable */
-			uint16_t : 1;
-			volatile uint16_t BCHGE : 1;  /* [14..14] USB Bus Change Interrupt Enable */
-			volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */
-		} INTENB1_b;
-	};
-	volatile const uint16_t RESERVED7;
-
-	union {
-		volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */
-
-		struct {
-			volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */
-			uint16_t : 6;
-		} BRDYENB_b;
-	};
-
-	union {
-		volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */
-
-		struct {
-			volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */
-			volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */
-			uint16_t : 6;
-		} NRDYENB_b;
-	};
-
-	union {
-		volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */
-
-		struct {
-			volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */
-			volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */
-			uint16_t : 6;
-		} BEMPENB_b;
-	};
-
-	union {
-		volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */
-
-		struct {
-			uint16_t : 4;
-			volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */
-			volatile uint16_t INTL : 1;	     /* [5..5] Interrupt Output Sense Select */
-			volatile uint16_t BRDYM : 1;	     /* [6..6] BRDY Interrupt Status Clear Timing */
-			uint16_t : 1;
-			volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */
-			uint16_t : 7;
-		} SOFCFG_b;
-	};
-
-	union {
-		volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */
-
-		struct {
-			volatile uint16_t DIRPD : 1;	/* [0..0] Power-Down Control */
-			volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */
-			uint16_t : 1;
-			volatile uint16_t CDPEN : 1;  /* [3..3] Charging Downstream Port Enable */
-			volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */
-			uint16_t : 2;
-			volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */
-			uint16_t : 1;
-			volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */
-			uint16_t : 3;
-			volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */
-		} PHYSET_b;
-	};
-
-	union {
-		volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */
-
-		struct {
-			volatile const uint16_t CTSQ : 3;  /* [2..0] Control Transfer Stage */
-			volatile uint16_t VALID : 1;	   /* [3..3] USB Request Reception */
-			volatile const uint16_t DVSQ : 3;  /* [6..4] Device State */
-			volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */
-			volatile const uint16_t BRDY : 1;  /* [8..8] Buffer Ready Interrupt Status */
-			volatile const uint16_t NRDY : 1;  /* [9..9] Buffer Not Ready Interrupt Status */
-			volatile const uint16_t BEMP : 1;  /* [10..10] Buffer Empty Interrupt Status */
-			volatile uint16_t CTRT : 1;	   /* [11..11] Control Transfer Stage Transition Interrupt Status */
-			volatile uint16_t DVST : 1;	   /* [12..12] Device State Transition Interrupt Status */
-			volatile uint16_t SOFR : 1;	   /* [13..13] Frame Number Refresh Interrupt Status */
-			volatile uint16_t RESM : 1;	   /* [14..14] Resume Interrupt Status */
-			volatile uint16_t VBINT : 1;	   /* [15..15] VBUS Interrupt Status */
-		} INTSTS0_b;
-	};
-
-	union {
-		volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */
-
-		struct {
-			volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */
-			uint16_t : 3;
-			volatile uint16_t SACK : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Status */
-			volatile uint16_t SIGN : 1;   /* [5..5] Setup Transaction Error Interrupt Status */
-			volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */
-			uint16_t : 1;
-			volatile uint16_t LPMEND : 1;	/* [8..8] LPM Transaction End Interrupt Status */
-			volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */
-			uint16_t : 1;
-			volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */
-			volatile uint16_t DTCH : 1;  /* [12..12] USB Disconnection Detection Interrupt Status */
-			uint16_t : 1;
-			volatile uint16_t BCHG : 1;  /* [14..14] USB Bus Change Interrupt Status */
-			volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */
-		} INTSTS1_b;
-	};
-	volatile const uint16_t RESERVED8;
-
-	union {
-		volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */
-
-		struct {
-			volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */
-			uint16_t : 6;
-		} BRDYSTS_b;
-	};
-
-	union {
-		volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */
-
-		struct {
-			volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */
-			volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */
-			uint16_t : 6;
-		} NRDYSTS_b;
-	};
-
-	union {
-		volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */
-
-		struct {
-			volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */
-			volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */
-			uint16_t : 6;
-		} BEMPSTS_b;
-	};
-
-	union {
-		volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */
-
-		struct {
-			volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */
-			uint16_t : 3;
-			volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */
-			volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */
-		} FRMNUM_b;
-	};
-
-	union {
-		volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */
-
-		struct {
-			volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */
-			uint16_t : 12;
-			volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */
-		} UFRMNUM_b;
-	};
-
-	union {
-		volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */
-
-		struct {
-			volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */
-			uint16_t : 1;
-			volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */
-			uint16_t : 5;
-		} USBADDR_b;
-	};
-	volatile const uint16_t RESERVED9;
-
-	union {
-		volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */
-
-		struct {
-			volatile uint16_t
-				BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
-			volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
-		} USBREQ_b;
-	};
-
-	union {
-		volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */
-
-		struct {
-			volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */
-		} USBVAL_b;
-	};
-
-	union {
-		volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */
-
-		struct {
-			volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */
-		} USBINDX_b;
-	};
-
-	union {
-		volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */
-
-		struct {
-			volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */
-		} USBLENG_b;
-	};
-
-	union {
-		volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */
-
-		struct {
-			uint16_t : 4;
-			volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */
-			uint16_t : 2;
-			volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
-			volatile uint16_t CNTMD : 1;  /* [8..8] Continuous Transfer Mode */
-			uint16_t : 7;
-		} DCPCFG_b;
-	};
-
-	union {
-		volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */
-
-		struct {
-			volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */
-			uint16_t : 5;
-			volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
-		} DCPMAXP_b;
-	};
-
-	union {
-		volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */
-
-		struct {
-			volatile uint16_t PID : 2;  /* [1..0] Response PID */
-			volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */
-			uint16_t : 2;
-			volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
-			volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */
-			volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
-			volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
-			uint16_t : 2;
-			volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */
-			uint16_t : 2;
-			volatile uint16_t SUREQ : 1;	  /* [14..14] Setup Token Transmission */
-			volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */
-		} DCPCTR_b;
-	};
-	volatile const uint16_t RESERVED10;
-
-	union {
-		volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */
-
-		struct {
-			volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
-			uint16_t : 12;
-		} PIPESEL_b;
-	};
-	volatile const uint16_t RESERVED11;
-
-	union {
-		volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */
-
-		struct {
-			volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */
-			volatile uint16_t DIR : 1;   /* [4..4] Transfer Direction */
-			uint16_t : 2;
-			volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
-			uint16_t : 1;
-			volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */
-			volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */
-			uint16_t : 3;
-			volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */
-		} PIPECFG_b;
-	};
-	volatile const uint16_t RESERVED12;
-
-	union {
-		volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
-
-		struct {
-			volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */
-			uint16_t : 3;
-			volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
-		} PIPEMAXP_b;
-	};
-
-	union {
-		volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */
-
-		struct {
-			volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */
-			uint16_t : 9;
-			volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */
-			uint16_t : 3;
-		} PIPEPERI_b;
-	};
-
-	union {
-		volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */
-
-		struct {
-			volatile uint16_t PID : 2; /* [1..0] Response PID */
-			uint16_t : 3;
-			volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
-			volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */
-			volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
-			volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
-			volatile uint16_t ACLRM : 1;	   /* [9..9] Auto Buffer Clear Mode */
-			volatile uint16_t ATREPM : 1;	   /* [10..10] Auto Response Mode */
-			uint16_t : 1;
-			volatile const uint16_t CSSTS : 1;  /* [12..12] CSSTS Status */
-			volatile uint16_t CSCLR : 1;	    /* [13..13] CSPLIT Status Clear */
-			volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */
-			volatile const uint16_t BSTS : 1;   /* [15..15] Buffer Status */
-		} PIPE_CTR_b[9];
-	};
-	volatile const uint16_t RESERVED13;
-	volatile const uint32_t RESERVED14[3];
-	volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */
-	volatile const uint32_t RESERVED15[3];
-
-	union {
-		volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */
-
-		struct {
-			volatile uint16_t RPDME0 : 1;	/* [0..0] D- Pin Pull-Down Control */
-			volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */
-			volatile uint16_t
-				IDMSINKE0 : 1;		/* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
-			volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
-			volatile uint16_t
-				IDPSINKE0 : 1;		/* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
-			volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
-			uint16_t : 1;
-			volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
-			volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */
-			volatile const uint16_t PDDETSTS0 : 1;	/* [9..9] D+ Pin 0.6 V Input Detection Status */
-			uint16_t : 6;
-		} USBBCCTRL0_b;
-	};
-	volatile const uint16_t RESERVED16;
-	volatile const uint32_t RESERVED17[4];
-
-	union {
-		volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */
-
-		struct {
-			volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
-			uint16_t : 15;
-		} UCKSEL_b;
-	};
-	volatile const uint16_t RESERVED18;
-	volatile const uint32_t RESERVED19;
-
-	union {
-		volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */
-
-		struct {
-			volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */
-			uint16_t : 6;
-			volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */
-			uint16_t : 8;
-		} USBMC_b;
-	};
-	volatile const uint16_t RESERVED20;
-
-	union {
-		volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
-
-		struct {
-			uint16_t : 6;
-			volatile uint16_t USBSPD : 2;  /* [7..6] Transfer Speed of Communication Target Device */
-			volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
-			volatile uint16_t UPPHUB : 4;  /* [14..11] Communication Target Connecting Hub Register */
-			uint16_t : 1;
-		} DEVADD_b[10];
-	};
-	volatile const uint32_t RESERVED21[3];
-
-	union {
-		volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */
-
-		struct {
-			volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */
-			volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
-			volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
-			volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */
-			uint32_t : 28;
-		} PHYSLEW_b;
-	};
-	volatile const uint32_t RESERVED22[3];
-
-	union {
-		volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
-
-		struct {
-			uint16_t : 7;
-			volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
-			uint16_t : 8;
-		} LPCTRL_b;
-	};
-
-	union {
-		volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
-
-		struct {
-			uint16_t : 14;
-			volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
-			uint16_t : 1;
-		} LPSTS_b;
-	};
-	volatile const uint32_t RESERVED23[15];
-
-	union {
-		volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */
-
-		struct {
-			volatile uint16_t IDPSRCE : 1;	/* [0..0] IDPSRC Control */
-			volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */
-			volatile uint16_t VDPSRCE : 1;	/* [2..2] VDPSRC Control */
-			volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */
-			volatile uint16_t VDMSRCE : 1;	/* [4..4] VDMSRC Control */
-			volatile uint16_t DCPMODE : 1;	/* [5..5] DCP Mode Control */
-			uint16_t : 2;
-			volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
-			volatile const uint16_t PDDETSTS : 1;  /* [9..9] PDDET Status */
-			uint16_t : 6;
-		} BCCTRL_b;
-	};
-	volatile const uint16_t RESERVED24;
-
-	union {
-		volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */
-
-		struct {
-			volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */
-			volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */
-			volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */
-			volatile const uint16_t
-				DVSQ : 4;	       /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
-			volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */
-			uint16_t : 2;
-			volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */
-			uint16_t : 1;
-		} PL1CTRL1_b;
-	};
-
-	union {
-		volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
-
-		struct {
-			uint16_t : 8;
-			volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
-			volatile uint16_t RWEMON : 1;  /* [12..12] RWE Value Monitor */
-			uint16_t : 3;
-		} PL1CTRL2_b;
-	};
-
-	union {
-		volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */
-
-		struct {
-			volatile uint16_t L1REQ : 1;	      /* [0..0] L1 Transition Request */
-			volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
-			uint16_t : 13;
-		} HL1CTRL1_b;
-	};
-
-	union {
-		volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */
-
-		struct {
-			volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */
-			uint16_t : 4;
-			volatile uint16_t HIRD : 4;  /* [11..8] LPM Token HIRD */
-			volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */
-			uint16_t : 2;
-			volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */
-		} HL1CTRL2_b;
-	};
-	volatile const uint32_t RESERVED25[5];
-
-	union {
-		volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
-
-		struct {
-			uint32_t : 20;
-			volatile const uint32_t
-				DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
-			volatile const uint32_t
-				DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
-			uint32_t : 1;
-			volatile const uint32_t
-				DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
-			uint32_t : 8;
-		} DPUSR0R_b;
-	};
-
-	union {
-		volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
-
-		struct {
-			uint32_t : 4;
-			volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
-			volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
-			uint32_t : 1;
-			volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */
-			uint32_t : 12;
-			volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */
-			volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
-			uint32_t : 1;
-			volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
-			uint32_t : 8;
-		} DPUSR1R_b;
-	};
-
-	union {
-		volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
-
-		struct {
-			volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */
-			volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */
-			uint16_t : 2;
-			volatile const uint16_t
-				DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
-			volatile const uint16_t
-				DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
-			uint16_t : 2;
-			volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */
-			volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */
-			uint16_t : 6;
-		} DPUSR2R_b;
-	};
-
-	union {
-		volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
-
-		struct {
-			volatile uint16_t FIXPHY : 1;	/* [0..0] USB Transceiver Control Fix */
-			volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
-			uint16_t : 14;
-		} DPUSRCR_b;
-	};
-	volatile const uint32_t RESERVED26[165];
-
-	union {
-		volatile uint32_t
-			DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */
-
-		struct {
-			volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */
-			volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */
-			uint32_t : 1;
-			volatile uint32_t DRPD0 : 1;   /* [3..3] D+/D- Pull-Down Resistor Control */
-			volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */
-			uint32_t : 11;
-			volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
-			volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */
-			uint32_t : 2;
-			volatile const uint32_t
-				DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
-			volatile const uint32_t
-				DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
-			uint32_t : 1;
-			volatile const uint32_t
-				DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
-			uint32_t : 8;
-		} DPUSR0R_FS_b;
-	};
-
-	union {
-		volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */
-
-		struct {
-			volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */
-			volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */
-			uint32_t : 2;
-			volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */
-			volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */
-			uint32_t : 1;
-			volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */
-			uint32_t : 8;
-			volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */
-			volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */
-			uint32_t : 2;
-			volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */
-			volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
-			uint32_t : 1;
-			volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
-			uint32_t : 8;
-		} DPUSR1R_FS_b;
-	};
+  union {
+    volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
+
+    struct {
+      volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */
+      uint16_t : 2;
+      volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */
+      volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
+      volatile uint16_t DRPD : 1;  /* [5..5] D+/D- Line Resistor Control */
+      volatile uint16_t DCFM : 1;  /* [6..6] Controller Function Select */
+      uint16_t : 1;
+      volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */
+      uint16_t : 1;
+      volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */
+      uint16_t : 5;
+    } SYSCFG_b;
+  };
+
+  union {
+    volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */
+
+    struct {
+      volatile uint16_t
+        BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
+      uint16_t : 12;
+    } BUSWAIT_b;
+  };
+
+  union {
+    volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */
+
+    struct {
+      volatile const uint16_t LNST : 2;  /* [1..0] USB Data Line Status Monitor */
+      volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */
+      uint16_t : 2;
+      volatile const uint16_t
+        SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
+      volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */
+      uint16_t : 7;
+      volatile const uint16_t
+        OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
+    } SYSSTS0_b;
+  };
+
+  union {
+    volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */
+
+    struct {
+      volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
+      uint16_t : 15;
+    } PLLSTA_b;
+  };
+
+  union {
+    volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */
+
+    struct {
+      volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */
+      uint16_t : 1;
+      volatile uint16_t UACT : 1;    /* [4..4] USB Bus Enable */
+      volatile uint16_t RESUME : 1;  /* [5..5] Resume Output */
+      volatile uint16_t USBRST : 1;  /* [6..6] USB Bus Reset Output */
+      volatile uint16_t RWUPE : 1;   /* [7..7] Wakeup Detection Enable */
+      volatile uint16_t WKUP : 1;    /* [8..8] Wakeup Output */
+      volatile uint16_t VBUSEN : 1;  /* [9..9] USB_VBUSEN Output Pin Control */
+      volatile uint16_t EXICEN : 1;  /* [10..10] USB_EXICEN Output Pin Control */
+      volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */
+      uint16_t : 4;
+    } DVSTCTR0_b;
+  };
+  volatile const uint16_t RESERVED;
+
+  union {
+    volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */
+
+    struct {
+      volatile uint16_t UTST : 4; /* [3..0] Test Mode */
+      uint16_t : 12;
+    } TESTMODE_b;
+  };
+  volatile const uint16_t RESERVED1;
+  volatile const uint32_t RESERVED2;
+
+  union {
+    volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */
+
+    struct {
+      union {
+        volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */
+        volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */
+      };
+
+      union {
+        volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */
+
+        struct {
+          volatile const uint8_t RESERVED3;
+          volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */
+        };
+      };
+    };
+  };
+
+  union {
+    volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */
+
+    struct {
+      union {
+        volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */
+        volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */
+      };
+
+      union {
+        volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */
+
+        struct {
+          volatile const uint8_t RESERVED4;
+          volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */
+        };
+      };
+    };
+  };
+
+  union {
+    volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */
+
+    struct {
+      union {
+        volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */
+        volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */
+      };
+
+      union {
+        volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */
+
+        struct {
+          volatile const uint8_t RESERVED5;
+          volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */
+        };
+      };
+    };
+  };
+
+  union {
+    volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */
+
+    struct {
+      volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */
+      uint16_t : 1;
+      volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */
+      uint16_t : 2;
+      volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */
+      uint16_t : 1;
+      volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */
+      uint16_t : 2;
+      volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
+      volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+    } CFIFOSEL_b;
+  };
+
+  union {
+    volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */
+
+    struct {
+      volatile const uint16_t
+        DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t : 1;
+      volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+    } CFIFOCTR_b;
+  };
+  volatile const uint32_t RESERVED6;
+
+  union {
+    volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */
+
+    struct {
+      volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
+      uint16_t : 4;
+      volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
+      uint16_t : 1;
+      volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
+      volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
+      volatile uint16_t
+        DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
+      volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
+      volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+    } D0FIFOSEL_b;
+  };
+
+  union {
+    volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */
+
+    struct {
+      volatile const uint16_t
+        DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t : 1;
+      volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+    } D0FIFOCTR_b;
+  };
+
+  union {
+    volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */
+
+    struct {
+      volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
+      uint16_t : 4;
+      volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
+      uint16_t : 1;
+      volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
+      volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
+      volatile uint16_t
+        DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
+      volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
+      volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+    } D1FIFOSEL_b;
+  };
+
+  union {
+    volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */
+
+    struct {
+      volatile const uint16_t
+        DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t : 1;
+      volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+    } D1FIFOCTR_b;
+  };
+
+  union {
+    volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
+
+    struct {
+      uint16_t : 8;
+      volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
+      volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
+      volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
+      volatile uint16_t CTRE : 1;  /* [11..11] Control Transfer Stage Transition Interrupt Enable */
+      volatile uint16_t DVSE : 1;  /* [12..12] Device State Transition Interrupt Enable */
+      volatile uint16_t SOFE : 1;  /* [13..13] Frame Number Update Interrupt Enable */
+      volatile uint16_t RSME : 1;  /* [14..14] Resume Interrupt Enable */
+      volatile uint16_t VBSE : 1;  /* [15..15] VBUS Interrupt Enable */
+    } INTENB0_b;
+  };
+
+  union {
+    volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */
+
+    struct {
+      volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */
+      uint16_t : 3;
+      volatile uint16_t SACKE : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Enable */
+      volatile uint16_t SIGNE : 1;   /* [5..5] Setup Transaction Error Interrupt Enable */
+      volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */
+      uint16_t : 4;
+      volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */
+      volatile uint16_t DTCHE : 1;  /* [12..12] Disconnection Detection Interrupt Enable */
+      uint16_t : 1;
+      volatile uint16_t BCHGE : 1;  /* [14..14] USB Bus Change Interrupt Enable */
+      volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */
+    } INTENB1_b;
+  };
+  volatile const uint16_t RESERVED7;
+
+  union {
+    volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */
+
+    struct {
+      volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE3BRDYE : 1; /* [3..3] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE4BRDYE : 1; /* [4..4] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE5BRDYE : 1; /* [5..5] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE6BRDYE : 1; /* [6..6] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */
+      uint16_t : 6;
+    } BRDYENB_b;
+  };
+
+  union {
+    volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */
+
+    struct {
+      volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE3NRDYE : 1; /* [3..3] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE4NRDYE : 1; /* [4..4] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE5NRDYE : 1; /* [5..5] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE6NRDYE : 1; /* [6..6] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */
+      volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */
+      uint16_t : 6;
+    } NRDYENB_b;
+  };
+
+  union {
+    volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */
+
+    struct {
+      volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE3BEMPE : 1; /* [3..3] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE4BEMPE : 1; /* [4..4] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE5BEMPE : 1; /* [5..5] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE6BEMPE : 1; /* [6..6] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */
+      volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */
+      uint16_t : 6;
+    } BEMPENB_b;
+  };
+
+  union {
+    volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */
+
+    struct {
+      uint16_t : 4;
+      volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */
+      volatile uint16_t INTL : 1;	     /* [5..5] Interrupt Output Sense Select */
+      volatile uint16_t BRDYM : 1;	     /* [6..6] BRDY Interrupt Status Clear Timing */
+      uint16_t : 1;
+      volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */
+      uint16_t : 7;
+    } SOFCFG_b;
+  };
+
+  union {
+    volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */
+
+    struct {
+      volatile uint16_t DIRPD : 1;	/* [0..0] Power-Down Control */
+      volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */
+      uint16_t : 1;
+      volatile uint16_t CDPEN : 1;  /* [3..3] Charging Downstream Port Enable */
+      volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */
+      uint16_t : 2;
+      volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */
+      uint16_t : 1;
+      volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */
+      uint16_t : 3;
+      volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */
+    } PHYSET_b;
+  };
+
+  union {
+    volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */
+
+    struct {
+      volatile const uint16_t CTSQ : 3;  /* [2..0] Control Transfer Stage */
+      volatile uint16_t VALID : 1;	   /* [3..3] USB Request Reception */
+      volatile const uint16_t DVSQ : 3;  /* [6..4] Device State */
+      volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */
+      volatile const uint16_t BRDY : 1;  /* [8..8] Buffer Ready Interrupt Status */
+      volatile const uint16_t NRDY : 1;  /* [9..9] Buffer Not Ready Interrupt Status */
+      volatile const uint16_t BEMP : 1;  /* [10..10] Buffer Empty Interrupt Status */
+      volatile uint16_t CTRT : 1;	   /* [11..11] Control Transfer Stage Transition Interrupt Status */
+      volatile uint16_t DVST : 1;	   /* [12..12] Device State Transition Interrupt Status */
+      volatile uint16_t SOFR : 1;	   /* [13..13] Frame Number Refresh Interrupt Status */
+      volatile uint16_t RESM : 1;	   /* [14..14] Resume Interrupt Status */
+      volatile uint16_t VBINT : 1;	   /* [15..15] VBUS Interrupt Status */
+    } INTSTS0_b;
+  };
+
+  union {
+    volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */
+
+    struct {
+      volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */
+      uint16_t : 3;
+      volatile uint16_t SACK : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Status */
+      volatile uint16_t SIGN : 1;   /* [5..5] Setup Transaction Error Interrupt Status */
+      volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */
+      uint16_t : 1;
+      volatile uint16_t LPMEND : 1;	/* [8..8] LPM Transaction End Interrupt Status */
+      volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */
+      uint16_t : 1;
+      volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */
+      volatile uint16_t DTCH : 1;  /* [12..12] USB Disconnection Detection Interrupt Status */
+      uint16_t : 1;
+      volatile uint16_t BCHG : 1;  /* [14..14] USB Bus Change Interrupt Status */
+      volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */
+    } INTSTS1_b;
+  };
+  volatile const uint16_t RESERVED8;
+
+  union {
+    volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */
+
+    struct {
+      volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE3BRDY : 1; /* [3..3] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE4BRDY : 1; /* [4..4] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE5BRDY : 1; /* [5..5] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE6BRDY : 1; /* [6..6] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */
+      uint16_t : 6;
+    } BRDYSTS_b;
+  };
+
+  union {
+    volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */
+
+    struct {
+      volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE3NRDY : 1; /* [3..3] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE4NRDY : 1; /* [4..4] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE5NRDY : 1; /* [5..5] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE6NRDY : 1; /* [6..6] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */
+      volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */
+      uint16_t : 6;
+    } NRDYSTS_b;
+  };
+
+  union {
+    volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */
+
+    struct {
+      volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE3BEMP : 1; /* [3..3] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE4BEMP : 1; /* [4..4] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE5BEMP : 1; /* [5..5] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE6BEMP : 1; /* [6..6] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */
+      volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */
+      uint16_t : 6;
+    } BEMPSTS_b;
+  };
+
+  union {
+    volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */
+
+    struct {
+      volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */
+      uint16_t : 3;
+      volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */
+      volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */
+    } FRMNUM_b;
+  };
+
+  union {
+    volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */
+
+    struct {
+      volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */
+      uint16_t : 12;
+      volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */
+    } UFRMNUM_b;
+  };
+
+  union {
+    volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */
+
+    struct {
+      volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */
+      uint16_t : 1;
+      volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */
+      uint16_t : 5;
+    } USBADDR_b;
+  };
+  volatile const uint16_t RESERVED9;
+
+  union {
+    volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */
+
+    struct {
+      volatile uint16_t
+        BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
+      volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
+    } USBREQ_b;
+  };
+
+  union {
+    volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */
+
+    struct {
+      volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */
+    } USBVAL_b;
+  };
+
+  union {
+    volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */
+
+    struct {
+      volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */
+    } USBINDX_b;
+  };
+
+  union {
+    volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */
+
+    struct {
+      volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */
+    } USBLENG_b;
+  };
+
+  union {
+    volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */
+
+    struct {
+      uint16_t : 4;
+      volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */
+      uint16_t : 2;
+      volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
+      volatile uint16_t CNTMD : 1;  /* [8..8] Continuous Transfer Mode */
+      uint16_t : 7;
+    } DCPCFG_b;
+  };
+
+  union {
+    volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */
+
+    struct {
+      volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */
+      uint16_t : 5;
+      volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
+    } DCPMAXP_b;
+  };
+
+  union {
+    volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */
+
+    struct {
+      volatile uint16_t PID : 2;  /* [1..0] Response PID */
+      volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */
+      uint16_t : 2;
+      volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
+      volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */
+      volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
+      volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
+      uint16_t : 2;
+      volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */
+      uint16_t : 2;
+      volatile uint16_t SUREQ : 1;	  /* [14..14] Setup Token Transmission */
+      volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */
+    } DCPCTR_b;
+  };
+  volatile const uint16_t RESERVED10;
+
+  union {
+    volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */
+
+    struct {
+      volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
+      uint16_t : 12;
+    } PIPESEL_b;
+  };
+  volatile const uint16_t RESERVED11;
+
+  union {
+    volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */
+
+    struct {
+      volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */
+      volatile uint16_t DIR : 1;   /* [4..4] Transfer Direction */
+      uint16_t : 2;
+      volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
+      uint16_t : 1;
+      volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */
+      volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */
+      uint16_t : 3;
+      volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */
+    } PIPECFG_b;
+  };
+  volatile const uint16_t RESERVED12;
+
+  union {
+    volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
+
+    struct {
+      volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */
+      uint16_t : 3;
+      volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
+    } PIPEMAXP_b;
+  };
+
+  union {
+    volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */
+
+    struct {
+      volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */
+      uint16_t : 9;
+      volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */
+      uint16_t : 3;
+    } PIPEPERI_b;
+  };
+
+  union {
+    volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */
+
+    struct {
+      volatile uint16_t PID : 2; /* [1..0] Response PID */
+      uint16_t : 3;
+      volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
+      volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */
+      volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
+      volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
+      volatile uint16_t ACLRM : 1;	   /* [9..9] Auto Buffer Clear Mode */
+      volatile uint16_t ATREPM : 1;	   /* [10..10] Auto Response Mode */
+      uint16_t : 1;
+      volatile const uint16_t CSSTS : 1;  /* [12..12] CSSTS Status */
+      volatile uint16_t CSCLR : 1;	    /* [13..13] CSPLIT Status Clear */
+      volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */
+      volatile const uint16_t BSTS : 1;   /* [15..15] Buffer Status */
+    } PIPE_CTR_b[9];
+  };
+  volatile const uint16_t RESERVED13;
+  volatile const uint32_t RESERVED14[3];
+  volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */
+  volatile const uint32_t RESERVED15[3];
+
+  union {
+    volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */
+
+    struct {
+      volatile uint16_t RPDME0 : 1;	/* [0..0] D- Pin Pull-Down Control */
+      volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */
+      volatile uint16_t
+        IDMSINKE0 : 1;		/* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
+      volatile uint16_t
+        IDPSINKE0 : 1;		/* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
+      uint16_t : 1;
+      volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
+      volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */
+      volatile const uint16_t PDDETSTS0 : 1;	/* [9..9] D+ Pin 0.6 V Input Detection Status */
+      uint16_t : 6;
+    } USBBCCTRL0_b;
+  };
+  volatile const uint16_t RESERVED16;
+  volatile const uint32_t RESERVED17[4];
+
+  union {
+    volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */
+
+    struct {
+      volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
+      uint16_t : 15;
+    } UCKSEL_b;
+  };
+  volatile const uint16_t RESERVED18;
+  volatile const uint32_t RESERVED19;
+
+  union {
+    volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */
+
+    struct {
+      volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */
+      uint16_t : 6;
+      volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */
+      uint16_t : 8;
+    } USBMC_b;
+  };
+  volatile const uint16_t RESERVED20;
+
+  union {
+    volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
+
+    struct {
+      uint16_t : 6;
+      volatile uint16_t USBSPD : 2;  /* [7..6] Transfer Speed of Communication Target Device */
+      volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
+      volatile uint16_t UPPHUB : 4;  /* [14..11] Communication Target Connecting Hub Register */
+      uint16_t : 1;
+    } DEVADD_b[10];
+  };
+  volatile const uint32_t RESERVED21[3];
+
+  union {
+    volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */
+
+    struct {
+      volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */
+      volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
+      volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
+      volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */
+      uint32_t : 28;
+    } PHYSLEW_b;
+  };
+  volatile const uint32_t RESERVED22[3];
+
+  union {
+    volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
+
+    struct {
+      uint16_t : 7;
+      volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
+      uint16_t : 8;
+    } LPCTRL_b;
+  };
+
+  union {
+    volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
+
+    struct {
+      uint16_t : 14;
+      volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
+      uint16_t : 1;
+    } LPSTS_b;
+  };
+  volatile const uint32_t RESERVED23[15];
+
+  union {
+    volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */
+
+    struct {
+      volatile uint16_t IDPSRCE : 1;	/* [0..0] IDPSRC Control */
+      volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */
+      volatile uint16_t VDPSRCE : 1;	/* [2..2] VDPSRC Control */
+      volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */
+      volatile uint16_t VDMSRCE : 1;	/* [4..4] VDMSRC Control */
+      volatile uint16_t DCPMODE : 1;	/* [5..5] DCP Mode Control */
+      uint16_t : 2;
+      volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
+      volatile const uint16_t PDDETSTS : 1;  /* [9..9] PDDET Status */
+      uint16_t : 6;
+    } BCCTRL_b;
+  };
+  volatile const uint16_t RESERVED24;
+
+  union {
+    volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */
+
+    struct {
+      volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */
+      volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */
+      volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */
+      volatile const uint16_t
+        DVSQ : 4;	       /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
+      volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */
+      uint16_t : 2;
+      volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */
+      uint16_t : 1;
+    } PL1CTRL1_b;
+  };
+
+  union {
+    volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
+
+    struct {
+      uint16_t : 8;
+      volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
+      volatile uint16_t RWEMON : 1;  /* [12..12] RWE Value Monitor */
+      uint16_t : 3;
+    } PL1CTRL2_b;
+  };
+
+  union {
+    volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */
+
+    struct {
+      volatile uint16_t L1REQ : 1;	      /* [0..0] L1 Transition Request */
+      volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
+      uint16_t : 13;
+    } HL1CTRL1_b;
+  };
+
+  union {
+    volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */
+
+    struct {
+      volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */
+      uint16_t : 4;
+      volatile uint16_t HIRD : 4;  /* [11..8] LPM Token HIRD */
+      volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */
+      uint16_t : 2;
+      volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */
+    } HL1CTRL2_b;
+  };
+  volatile const uint32_t RESERVED25[5];
+
+  union {
+    volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
+
+    struct {
+      uint32_t : 20;
+      volatile const uint32_t
+        DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
+      volatile const uint32_t
+        DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
+      uint32_t : 1;
+      volatile const uint32_t
+        DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
+      uint32_t : 8;
+    } DPUSR0R_b;
+  };
+
+  union {
+    volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
+
+    struct {
+      uint32_t : 4;
+      volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
+      volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
+      uint32_t : 1;
+      volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */
+      uint32_t : 12;
+      volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */
+      volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
+      uint32_t : 1;
+      volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
+      uint32_t : 8;
+    } DPUSR1R_b;
+  };
+
+  union {
+    volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
+
+    struct {
+      volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */
+      volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */
+      uint16_t : 2;
+      volatile const uint16_t
+        DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
+      volatile const uint16_t
+        DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
+      uint16_t : 2;
+      volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */
+      volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */
+      uint16_t : 6;
+    } DPUSR2R_b;
+  };
+
+  union {
+    volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
+
+    struct {
+      volatile uint16_t FIXPHY : 1;	/* [0..0] USB Transceiver Control Fix */
+      volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
+      uint16_t : 14;
+    } DPUSRCR_b;
+  };
+  volatile const uint32_t RESERVED26[165];
+
+  union {
+    volatile uint32_t
+      DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */
+
+    struct {
+      volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */
+      volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */
+      uint32_t : 1;
+      volatile uint32_t DRPD0 : 1;   /* [3..3] D+/D- Pull-Down Resistor Control */
+      volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */
+      uint32_t : 11;
+      volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
+      volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */
+      uint32_t : 2;
+      volatile const uint32_t
+        DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
+      volatile const uint32_t
+        DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
+      uint32_t : 1;
+      volatile const uint32_t
+        DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
+      uint32_t : 8;
+    } DPUSR0R_FS_b;
+  };
+
+  union {
+    volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */
+
+    struct {
+      volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */
+      volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */
+      uint32_t : 2;
+      volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */
+      volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */
+      uint32_t : 1;
+      volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */
+      uint32_t : 8;
+      volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */
+      volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */
+      uint32_t : 2;
+      volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */
+      volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
+      uint32_t : 1;
+      volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
+      uint32_t : 8;
+    } DPUSR1R_FS_b;
+  };
 } LINK_REG_t; /* Size = 1032 (0x408) */
 
 TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG) == 0x00000000, "incorrect offset");
@@ -1034,7 +1034,7 @@ TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS) == 0x00000400, "incorrect offs
 TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS) == 0x00000404, "incorrect offset");
 
 TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
-	TU_ATTR_BIT_FIELD_ORDER_END
+TU_ATTR_BIT_FIELD_ORDER_END
 
 /*--------------------------------------------------------------------*/
 /* Register Bit Definitions                                           */

From 79fd23974c04b18a7ebb2dfe14a170cb7c3e6f41 Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Wed, 30 Mar 2022 13:56:00 +0100
Subject: [PATCH 1043/2085] fix host preprocessor flag typo

Co-authored-by: Koji KITAYAMA <45088311+kkitayam@users.noreply.github.com>
---
 src/portable/renesas/link/hcd_link.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c
index f60c49114..4bb103936 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/link/hcd_link.c
@@ -27,7 +27,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
+#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
                         CFG_TUSB_MCU == OPT_MCU_RX65X || \
                         CFG_TUSB_MCU == OPT_MCU_RX72N || \
                         CFG_TUSB_MCU == OPT_MCU_RAXXX)

From fbc29794287b1f22388a09e289ff7b7698ef3eab Mon Sep 17 00:00:00 2001
From: Rafael Silva <perigoso@riseup.net>
Date: Wed, 30 Mar 2022 15:38:31 +0100
Subject: [PATCH 1044/2085] fix iso int register typo

druing the renaming int and iso endpoint configurations were swapped

Co-authored-by: Koji KITAYAMA <45088311+kkitayam@users.noreply.github.com>
---
 src/portable/renesas/link/dcd_link.c | 4 ++--
 src/portable/renesas/link/hcd_link.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c
index bb7e3b60a..0f9037593 100644
--- a/src/portable/renesas/link/dcd_link.c
+++ b/src/portable/renesas/link/dcd_link.c
@@ -642,9 +642,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   if (xfer == TUSB_XFER_BULK) {
     cfg |= (LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk);
   } else if (xfer == TUSB_XFER_INTERRUPT) {
-    cfg |= LINK_REG_PIPECFG_TYPE_ISO;
+    cfg |= LINK_REG_PIPECFG_TYPE_INT;
   } else {
-    cfg |= (LINK_REG_PIPECFG_TYPE_INT | LINK_REG_PIPECFG_DBLB_Msk);
+    cfg |= (LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk);
   }
   LINK_REG->PIPECFG = cfg;
   LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c
index 4bb103936..1197e1de5 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/link/hcd_link.c
@@ -642,9 +642,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   if (xfer == TUSB_XFER_BULK) {
     cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk;
   } else if (xfer == TUSB_XFER_INTERRUPT) {
-    cfg |= LINK_REG_PIPECFG_TYPE_ISO;
+    cfg |= LINK_REG_PIPECFG_TYPE_INT;
   } else {
-    cfg |= LINK_REG_PIPECFG_TYPE_INT | LINK_REG_PIPECFG_DBLB_Msk;
+    cfg |= LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk;
   }
   LINK_REG->PIPECFG = cfg;
   LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);

From ea81d22f184fa8fd6c46c35c8be86e47996b46c8 Mon Sep 17 00:00:00 2001
From: Rafael Silva <rafaelsilva@ajtec.pt>
Date: Thu, 7 Apr 2022 11:13:34 +0100
Subject: [PATCH 1045/2085] add __evenaccess keyword for CCRX compiler
 compatibility

Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt>
---
 src/portable/renesas/link/dcd_link.c | 4 ++++
 src/portable/renesas/link/hcd_link.c | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c
index 0f9037593..dcbd68b8d 100644
--- a/src/portable/renesas/link/dcd_link.c
+++ b/src/portable/renesas/link/dcd_link.c
@@ -52,7 +52,11 @@
 //--------------------------------------------------------------------+
 
 /* LINK core registers */
+#if defined(__CCRX__)
+#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE)
+#else
 #define LINK_REG ((LINK_REG_t*)LINK_REG_BASE)
+#endif
 
 /* Start of definition of packed structs (used by the CCRX toolchain) */
 TU_ATTR_PACKED_BEGIN
diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c
index 1197e1de5..f1ea2b821 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/link/hcd_link.c
@@ -48,7 +48,11 @@
 //--------------------------------------------------------------------+
 
 /* LINK core registers */
+#if defined(__CCRX__)
+#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE)
+#else
 #define LINK_REG ((LINK_REG_t*)LINK_REG_BASE)
+#endif
 
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN

From 8b9cf152a0dedda573fb3374d8c873dce4b883d1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 2 Jun 2022 16:51:17 +0700
Subject: [PATCH 1046/2085] rhport argument in usbd_ API() is not used (always
 use the initialized port)

remove the usage of TUD_OPT_RHPORT in class driver
---
 examples/device/cdc_msc/src/tusb_config.h | 31 ++++-----------
 hw/bsp/lpc18/family.c                     | 35 +++++++++++------
 src/class/bth/bth_device.c                |  8 ++--
 src/class/cdc/cdc_device.c                |  4 +-
 src/class/hid/hid_device.c                |  7 ++--
 src/class/midi/midi_device.c              |  4 +-
 src/class/net/ecm_rndis_device.c          | 10 +++--
 src/class/net/ncm_device.c                |  9 +++--
 src/class/vendor/vendor_device.c          | 12 ++++--
 src/common/tusb_mcu.h                     | 29 ++++++--------
 src/device/usbd.c                         | 14 ++++++-
 src/device/usbd_pvt.h                     |  1 +
 src/tusb_option.h                         | 48 ++++++++++++-----------
 13 files changed, 116 insertions(+), 96 deletions(-)

diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index 3849ad4d0..363da88d7 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -41,7 +41,12 @@
 
 // This example doesn't use an RTOS
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+  #define CFG_TUSB_OS         OPT_OS_NONE
+#endif
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+#ifndef CFG_TUSB_DEBUG
+  #define CFG_TUSB_DEBUG      0
 #endif
 
 // Enable Device stack
@@ -53,34 +58,14 @@
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_TUD_MAX_SPEED
   #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
-#endif
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 
-
-// Device max speed, default is max speed that hardware controller could support without external PHY
-// BOARD_TUD_MAX_SPEED can be used to change value (e.g for board features external PHY).
-#ifdef BOARD_TUD_MAX_SPEED
-  #define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
-#else
-  #define CFG_TUD_MAX_SPEED     OPT_MODE_DEFAULT_SPEED
-#endif
-
-
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index d74ebcd33..a59b6e89d 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -28,28 +28,40 @@
 #include "bsp/board.h"
 #include "board.h"
 
+#ifdef BOARD_TUD_RHPORT
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 //--------------------------------------------------------------------+
 void USB0_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
+  #if PORT_SUPPORT_DEVICE(0)
+    tud_int_handler(0);
   #endif
 
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
+  #if PORT_SUPPORT_HOST(0)
+    tuh_int_handler(0);
   #endif
 }
 
 void USB1_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    tuh_int_handler(1);
+  #if PORT_SUPPORT_DEVICE(1)
+    tud_int_handler(1);
   #endif
 
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-    tud_int_handler(1);
+  #if PORT_SUPPORT_HOST(1)
+    tuh_int_handler(1);
   #endif
 }
 
@@ -84,7 +96,8 @@ void board_init(void)
   SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
   Chip_GPIO_Init(LPC_GPIO_PORT);
@@ -102,11 +115,11 @@ void board_init(void)
   Chip_UART_TXEnable(UART_DEV);
 
   //------------- USB -------------//
-#if CFG_TUSB_RHPORT0_MODE
+#if PORT_SUPPORT_DEVICE(0) || PORT_SUPPORT_HOST(0)
   Chip_USB0_Init();
 #endif
 
-#if CFG_TUSB_RHPORT1_MODE
+#if PORT_SUPPORT_DEVICE(1) || PORT_SUPPORT_HOST(1)
   Chip_USB1_Init();
 #endif
 }
diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index f40bfbd0d..f96bb3552 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -59,10 +59,12 @@ CFG_TUSB_MEM_SECTION btd_interface_t _btd_itf;
 
 static bool bt_tx_data(uint8_t ep, void *data, uint16_t len)
 {
-  // skip if previous transfer not complete
-  TU_VERIFY(!usbd_edpt_busy(TUD_OPT_RHPORT, ep));
+  uint8_t const rhport = 0;
 
-  TU_ASSERT(usbd_edpt_xfer(TUD_OPT_RHPORT, ep, data, len));
+  // skip if previous transfer not complete
+  TU_VERIFY(!usbd_edpt_busy(rhport, ep));
+
+  TU_ASSERT(usbd_edpt_xfer(rhport, ep, data, len));
 
   return true;
 }
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 2b9b84e7a..7aa7a4860 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -82,7 +82,7 @@ CFG_TUSB_MEM_SECTION static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
 
 static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
 {
-  uint8_t const rhport = TUD_OPT_RHPORT;
+  uint8_t const rhport = 0;
   uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff);
 
   // Prepare for incoming data but only allow what we can store in the ring buffer.
@@ -189,7 +189,7 @@ uint32_t tud_cdc_n_write_flush (uint8_t itf)
   // No data to send
   if ( !tu_fifo_count(&p_cdc->tx_ff) ) return 0;
 
-  uint8_t const rhport = TUD_OPT_RHPORT;
+  uint8_t const rhport = 0;
 
   // Claim the endpoint
   TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 );
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 562ca7f36..cdf155e1c 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -76,8 +76,9 @@ static inline uint8_t get_index_by_itfnum(uint8_t itf_num)
 //--------------------------------------------------------------------+
 bool tud_hid_n_ready(uint8_t instance)
 {
+  uint8_t const rhport = 0;
   uint8_t const ep_in = _hidd_itf[instance].ep_in;
-  return tud_ready() && (ep_in != 0) && !usbd_edpt_busy(TUD_OPT_RHPORT, ep_in);
+  return tud_ready() && (ep_in != 0) && !usbd_edpt_busy(rhport, ep_in);
 }
 
 bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, uint8_t len)
@@ -103,7 +104,7 @@ bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, u
     memcpy(p_hid->epin_buf, report, len);
   }
 
-  return usbd_edpt_xfer(TUD_OPT_RHPORT, p_hid->ep_in, p_hid->epin_buf, len);
+  return usbd_edpt_xfer(rhport, p_hid->ep_in, p_hid->epin_buf, len);
 }
 
 uint8_t tud_hid_n_interface_protocol(uint8_t instance)
@@ -172,7 +173,7 @@ bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
 //--------------------------------------------------------------------+
 void hidd_init(void)
 {
-  hidd_reset(TUD_OPT_RHPORT);
+  hidd_reset(0);
 }
 
 void hidd_reset(uint8_t rhport)
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 2ce1376bd..28e6a92d2 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -92,7 +92,7 @@ bool tud_midi_n_mounted (uint8_t itf)
 
 static void _prep_out_transaction (midid_interface_t* p_midi)
 {
-  uint8_t const rhport = TUD_OPT_RHPORT;
+  uint8_t const rhport = 0;
   uint16_t available = tu_fifo_remaining(&p_midi->rx_ff);
 
   // Prepare for incoming data but only allow what we can store in the ring buffer.
@@ -219,7 +219,7 @@ static uint32_t write_flush(midid_interface_t* midi)
   // No data to send
   if ( !tu_fifo_count(&midi->tx_ff) ) return 0;
 
-  uint8_t const rhport = TUD_OPT_RHPORT;
+  uint8_t const rhport = 0;
 
   // skip if previous transfer not complete
   TU_VERIFY( usbd_edpt_claim(rhport, midi->ep_in), 0 );
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index f6b318058..d85a3f778 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -108,20 +108,22 @@ static bool can_xmit;
 
 void tud_network_recv_renew(void)
 {
-  usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_out, received, sizeof(received));
+  usbd_edpt_xfer(0, _netd_itf.ep_out, received, sizeof(received));
 }
 
 static void do_in_xfer(uint8_t *buf, uint16_t len)
 {
   can_xmit = false;
-  usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_in, buf, len);
+  usbd_edpt_xfer(0, _netd_itf.ep_in, buf, len);
 }
 
 void netd_report(uint8_t *buf, uint16_t len)
 {
+  uint8_t const rhport = 0;
+
   // skip if previous report not yet acknowledged by host
-  if ( usbd_edpt_busy(TUD_OPT_RHPORT, _netd_itf.ep_notif) ) return;
-  usbd_edpt_xfer(TUD_OPT_RHPORT, _netd_itf.ep_notif, buf, len);
+  if ( usbd_edpt_busy(rhport, _netd_itf.ep_notif) ) return;
+  usbd_edpt_xfer(rhport, _netd_itf.ep_notif, buf, len);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 1987337f8..00892b49c 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -188,7 +188,7 @@ static void ncm_start_tx(void) {
   ntb->ndp.datagram[ncm_interface.datagram_count].wDatagramLength = 0;
 
   // Kick off an endpoint transfer
-  usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_in, ntb->data, ntb_length);
+  usbd_edpt_xfer(0, ncm_interface.ep_in, ntb->data, ntb_length);
   ncm_interface.transferring = true;
 
   // Swap to the other NTB and clear it out
@@ -229,7 +229,7 @@ void tud_network_recv_renew(void)
 {
   if (!ncm_interface.num_datagrams)
   {
-    usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_out, receive_ntb, sizeof(receive_ntb));
+    usbd_edpt_xfer(0, ncm_interface.ep_out, receive_ntb, sizeof(receive_ntb));
     return;
   }
 
@@ -316,14 +316,15 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1
 
 static void ncm_report(void)
 {
+  uint8_t const rhport = 0;
   if (ncm_interface.report_state == REPORT_SPEED) {
     ncm_notify_speed_change.header.wIndex = ncm_interface.itf_num;
-    usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
+    usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_speed_change, sizeof(ncm_notify_speed_change));
     ncm_interface.report_state = REPORT_CONNECTED;
     ncm_interface.report_pending = true;
   } else if (ncm_interface.report_state == REPORT_CONNECTED) {
     ncm_notify_connected.header.wIndex = ncm_interface.itf_num;
-    usbd_edpt_xfer(TUD_OPT_RHPORT, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected));
+    usbd_edpt_xfer(rhport, ncm_interface.ep_notif, (uint8_t *) &ncm_notify_connected, sizeof(ncm_notify_connected));
     ncm_interface.report_state = REPORT_DONE;
     ncm_interface.report_pending = true;
   }
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 6e3ceb1c4..c7dfa0062 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -84,14 +84,16 @@ bool tud_vendor_n_peek(uint8_t itf, uint8_t* u8)
 //--------------------------------------------------------------------+
 static void _prep_out_transaction (vendord_interface_t* p_itf)
 {
+  uint8_t const rhport = 0;
+
   // skip if previous transfer not complete
-  if ( usbd_edpt_busy(TUD_OPT_RHPORT, p_itf->ep_out) ) return;
+  if ( usbd_edpt_busy(rhport, p_itf->ep_out) ) return;
 
   // Prepare for incoming data but only allow what we can store in the ring buffer.
   uint16_t max_read = tu_fifo_remaining(&p_itf->rx_ff);
   if ( max_read >= CFG_TUD_VENDOR_EPSIZE )
   {
-    usbd_edpt_xfer(TUD_OPT_RHPORT, p_itf->ep_out, p_itf->epout_buf, CFG_TUD_VENDOR_EPSIZE);
+    usbd_edpt_xfer(rhport, p_itf->ep_out, p_itf->epout_buf, CFG_TUD_VENDOR_EPSIZE);
   }
 }
 
@@ -115,13 +117,15 @@ void tud_vendor_n_read_flush (uint8_t itf)
 //--------------------------------------------------------------------+
 static uint16_t maybe_transmit(vendord_interface_t* p_itf)
 {
+  uint8_t const rhport = 0;
+
   // skip if previous transfer not complete
-  TU_VERIFY( !usbd_edpt_busy(TUD_OPT_RHPORT, p_itf->ep_in) );
+  TU_VERIFY( !usbd_edpt_busy(rhport, p_itf->ep_in) );
 
   uint16_t count = tu_fifo_read_n(&p_itf->tx_ff, p_itf->epin_buf, CFG_TUD_VENDOR_EPSIZE);
   if (count > 0)
   {
-    TU_ASSERT( usbd_edpt_xfer(TUD_OPT_RHPORT, p_itf->ep_in, p_itf->epin_buf, count) );
+    TU_ASSERT( usbd_edpt_xfer(rhport, p_itf->ep_in, p_itf->epin_buf, count) );
   }
   return count;
 }
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index c1cf2a810..383a8d686 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -45,8 +45,7 @@
  * - ENDPOINT_MAX: max (logical) number of endpoint
  * - ENDPOINT_EXCLUSIVE_NUMBER: endpoint number with different direction IN and OUT aren't allowed,
  *                              e.g EP1 OUT & EP1 IN cannot exist together
- * - RHPORT_HIGHSPEED: mask to indicate which port support highspeed mode (without external PHY)
- *                     bit0 for port0 and so on.
+ * - RHPORT_HIGHSPEED: support highspeed with on-chip PHY
  */
 
 //------------- NXP -------------//
@@ -63,8 +62,7 @@
   #define TUP_USBIP_EHCI
 
   #define TUP_DCD_ENDPOINT_MAX    6
-  #define TUP_RHPORT_HIGHSPEED    0x01 // Port0 HS, Port1 FS
-
+  #define TUP_RHPORT_HIGHSPEED    1 // Port0 HS, Port1 FS
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
    #define TUP_DCD_ENDPOINT_MAX   5
@@ -82,8 +80,7 @@
   #define TUP_USBIP_EHCI
 
   #define TUP_DCD_ENDPOINT_MAX    8
-  #define TUP_RHPORT_HIGHSPEED    0x03 // Port0 HS, Port1 HS
-
+  #define TUP_RHPORT_HIGHSPEED    1 // Port0 HS, Port1 HS
 
 #elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
   #define TUP_DCD_ENDPOINT_MAX    16
@@ -107,7 +104,7 @@
 
 #elif TU_CHECK_MCU(OPT_MCU_SAMX7X)
   #define TUP_DCD_ENDPOINT_MAX    10
-  #define TUP_RHPORT_HIGHSPEED    0x01
+  #define TUP_RHPORT_HIGHSPEED    1
   #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
 #elif TU_CHECK_MCU(OPT_MCU_PIC32MZ)
@@ -155,7 +152,7 @@
 
   // MCU with on-chip HS Phy
   #if defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F733xx)
-    #define TUP_RHPORT_HIGHSPEED  0x02 // Port 0: FS, Port 1: HS
+    #define TUP_RHPORT_HIGHSPEED  1 // Port0: FS, Port1: HS
   #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
@@ -185,12 +182,12 @@
   #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32WB)
-#define TUP_DCD_ENDPOINT_MAX    8
+  #define TUP_DCD_ENDPOINT_MAX    8
 
 //------------- Sony -------------//
 #elif TU_CHECK_MCU(OPT_MCU_CXD56)
   #define TUP_DCD_ENDPOINT_MAX    7
-  #define TUP_RHPORT_HIGHSPEED    0x01
+  #define TUP_RHPORT_HIGHSPEED    1
   #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
 //------------- TI -------------//
@@ -213,7 +210,7 @@
 
 #elif TU_CHECK_MCU(OPT_MCU_NUC505)
   #define TUP_DCD_ENDPOINT_MAX    12
-  #define TUP_RHPORT_HIGHSPEED    0x01
+  #define TUP_RHPORT_HIGHSPEED    1
 
 //------------- Espressif -------------//
 #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
@@ -228,7 +225,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_RP2040)
   #define TUP_DCD_ENDPOINT_MAX    16
 
-  #define TU_ATTR_FAST_FUNC   __attribute__((section(".time_critical.tinyusb")))
+  #define TU_ATTR_FAST_FUNC       __attribute__((section(".time_critical.tinyusb")))
 
 //------------- Silabs -------------//
 #elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
@@ -248,7 +245,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    8
-  #define TUP_RHPORT_HIGHSPEED    0x01
+  #define TUP_RHPORT_HIGHSPEED    1
 
 //------------- Broadcom -------------//
 #elif TU_CHECK_MCU(OPT_MCU_XMC4000)
@@ -258,11 +255,11 @@
 //------------- BridgeTek -------------//
 #elif TU_CHECK_MCU(OPT_MCU_FT90X)
   #define TUP_DCD_ENDPOINT_MAX    8
-  #define TUP_RHPORT_HIGHSPEED    0x01
+  #define TUP_RHPORT_HIGHSPEED    1
 
 #elif TU_CHECK_MCU(OPT_MCU_FT93X)
   #define TUP_DCD_ENDPOINT_MAX    16
-  #define TUP_RHPORT_HIGHSPEED    0x01
+  #define TUP_RHPORT_HIGHSPEED    1
 
 //------------ Allwinner -------------//
 #elif TU_CHECK_MCU(OPT_MCU_F1C100S)
@@ -281,7 +278,7 @@
 
 // Default to fullspeed if not defined
 #ifndef TUP_RHPORT_HIGHSPEED
-  #define TUP_RHPORT_HIGHSPEED    0x00
+  #define TUP_RHPORT_HIGHSPEED    0
 #endif
 
 // fast function, normally mean placing function in SRAM
diff --git a/src/device/usbd.c b/src/device/usbd.c
index fa75c0214..55e478a4e 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -428,7 +428,6 @@ bool tud_init (uint8_t rhport)
   dcd_init(rhport);
   dcd_int_enable(rhport);
 
-
   return true;
 }
 
@@ -1199,6 +1198,8 @@ void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr)
 
 bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
 {
+  rhport = _usbd_rhport;
+
   TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX);
   TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
 
@@ -1240,6 +1241,8 @@ bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr)
 
 bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
 {
+  rhport = _usbd_rhport;
+
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
@@ -1275,6 +1278,8 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 // into the USB buffer!
 bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
 {
+  rhport = _usbd_rhport;
+
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
@@ -1314,6 +1319,7 @@ bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
+  rhport = _usbd_rhport;
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
@@ -1330,6 +1336,8 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
+  rhport = _usbd_rhport;
+
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
@@ -1361,6 +1369,8 @@ bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
  */
 void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
+  rhport = _usbd_rhport;
+
   TU_ASSERT(dcd_edpt_close, /**/);
   TU_LOG2("  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
 
@@ -1377,6 +1387,8 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 
 void usbd_sof_enable(uint8_t rhport, bool en)
 {
+  rhport = _usbd_rhport;
+
   // TODO: Check needed if all drivers including the user sof_cb does not need an active SOF ISR any more.
   // Only if all drivers switched off SOF calls the SOF interrupt may be disabled
   dcd_sof_enable(rhport, en);
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 603ffc936..17ebbfcd4 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -62,6 +62,7 @@ void usbd_int_set(bool enabled);
 
 //--------------------------------------------------------------------+
 // USBD Endpoint API
+// Note: rhport should be 0 since device stack only support 1 rhport for now
 //--------------------------------------------------------------------+
 
 // Open an endpoint
diff --git a/src/tusb_option.h b/src/tusb_option.h
index ce22a8a6a..c198e4ef3 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -195,25 +195,21 @@ typedef int make_iso_compilers_happy ;
 #define OPT_MODE_HIGH_SPEED     0x0400 ///< High Speed
 #define OPT_MODE_SPEED_MASK     0xff00
 
-#ifndef CFG_TUSB_RHPORT0_MODE
-  #define CFG_TUSB_RHPORT0_MODE OPT_MODE_NONE
-#endif
-
-#ifndef CFG_TUSB_RHPORT1_MODE
-  #define CFG_TUSB_RHPORT1_MODE OPT_MODE_NONE
-#endif
-
-#if (((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST  ) && ((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST  )) || \
-    (((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) && ((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE))
-  #error "TinyUSB currently does not support same modes on more than 1 roothub port"
-#endif
-
 //------------- Roothub as Device -------------//
 
-#if (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE
+//#ifndef CFG_TUSB_RHPORT0_MODE
+//  #define CFG_TUSB_RHPORT0_MODE OPT_MODE_NONE
+//#endif
+//
+//#ifndef CFG_TUSB_RHPORT1_MODE
+//  #define CFG_TUSB_RHPORT1_MODE OPT_MODE_NONE
+//#endif
+
+
+#if defined(CFG_TUSB_RHPORT0_MODE) && ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE)
   #define TUD_RHPORT_MODE     (CFG_TUSB_RHPORT0_MODE)
   #define TUD_OPT_RHPORT      0
-#elif (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE
+#elif defined(CFG_TUSB_RHPORT1_MODE) && ((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE)
   #define TUD_RHPORT_MODE     (CFG_TUSB_RHPORT1_MODE)
   #define TUD_OPT_RHPORT      1
 #else
@@ -222,21 +218,24 @@ typedef int make_iso_compilers_happy ;
 #endif
 
 #ifndef CFG_TUD_ENABLED
-#define CFG_TUD_ENABLED       (TUD_RHPORT_MODE & OPT_MODE_DEVICE)
+  // fallback to use CFG_TUSB_RHPORTx_MODE
+  #define CFG_TUD_ENABLED     (TUD_RHPORT_MODE & OPT_MODE_DEVICE)
 #endif
 
-#if CFG_TUD_ENABLED
-  #define TUD_OPT_HIGH_SPEED  ((TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK) ? (TUD_RHPORT_MODE & OPT_MODE_HIGH_SPEED) : (TUP_RHPORT_HIGHSPEED & (1 << TUD_OPT_RHPORT)))
-#else
-  #define TUD_OPT_HIGH_SPEED  0
+#ifndef CFG_TUD_MAX_SPEED
+  // fallback to use CFG_TUSB_RHPORTx_MODE
+  #define CFG_TUD_MAX_SPEED   (TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK)
 #endif
 
+// highspeed support indicator
+#define TUD_OPT_HIGH_SPEED  (CFG_TUD_MAX_SPEED ? CFG_TUD_MAX_SPEED : TUP_RHPORT_HIGHSPEED)
+
 //------------- Roothub as Host -------------//
 
-#if (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST
+#if defined(CFG_TUSB_RHPORT0_MODE) && ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST)
   #define TUH_RHPORT_MODE  (CFG_TUSB_RHPORT0_MODE)
   #define TUH_OPT_RHPORT   0
-#elif (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST
+#elif defined(CFG_TUSB_RHPORT1_MODE) && ((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST)
   #define TUH_RHPORT_MODE  (CFG_TUSB_RHPORT1_MODE)
   #define TUH_OPT_RHPORT   1
 #else
@@ -244,7 +243,10 @@ typedef int make_iso_compilers_happy ;
   #define TUH_OPT_RHPORT   -1
 #endif
 
-#define CFG_TUH_ENABLED     (TUH_RHPORT_MODE & OPT_MODE_HOST)
+#ifndef CFG_TUH_ENABLED
+  // fallback to use CFG_TUSB_RHPORTx_MODE
+  #define CFG_TUH_ENABLED     (TUH_RHPORT_MODE & OPT_MODE_HOST)
+#endif
 
 // For backward compatible
 #define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED

From 8b37aa157911ff2cd470d090bb2e276ca57f5af4 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@gmail.com>
Date: Wed, 1 Jun 2022 21:50:15 +0200
Subject: [PATCH 1047/2085] nrf5x: Fix DMA access

There were two problems:
- dma_running flag could be checked in USB interrupt (not set yet) then higher priority
  interrupt could start transfer, check dma_running (not set yet) set it to true start
  DMA; then when USB interrupt continues it starts another DMA that is not allowed
- when DMA is started some registers can't be safely accessed, read can yield invalid
  values (SIZE.EPOUT, SIZE.EPISO)
  current implementation could start DMA for one OUT endpoint then check that another
  endpoint also has data and while DMA was not started right away, SIZE.EPOUT was copied
  already to MAXCNT register. Later on when DMA was started not all data was read from
  endpoint due to incorrect DMA size previously set.

To prevent both cases dma_running is changed in atomic way.
Only code that actually set this value to true starts DMA, code that tried and
had dma_running flag already set simply defers DMA start to USB task.
This eliminates also need to have mutex that was there to limit access to dma_running flag
to one task only.
transfer also now has started flag that is set only after dcd_edpt_xfer() sets up total_len
and actua_len. Previously USB interrupt was disabled when total_len and actual_len were
setup to prevent race condition when data arrived to ednpoint before transfer was setup
was finished.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 93 +++++++++++----------------
 1 file changed, 37 insertions(+), 56 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 430d8eded..efa30c60a 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -28,6 +28,7 @@
 
 #if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_NRF5X
 
+#include <stdatomic.h>
 #include "nrf.h"
 #include "nrf_clock.h"
 #include "nrf_power.h"
@@ -72,6 +73,7 @@ typedef struct
   // nRF will auto accept OUT packet after DMA is done
   // indicate packet is already ACK
   volatile bool data_received;
+  volatile bool started;
 
   // Set to true when data was transferred from RAM to ISO IN output buffer.
   // New data can be put in ISO IN output buffer after SOF.
@@ -79,9 +81,6 @@ typedef struct
 
 } xfer_td_t;
 
-static osal_mutex_def_t dcd_mutex_def;
-static osal_mutex_t dcd_mutex;
-
 // Data for managing dcd
 static struct
 {
@@ -90,7 +89,7 @@ static struct
   xfer_td_t xfer[EP_CBI_COUNT + 1][2];
 
   // nRF can only carry one DMA at a time, this is used to guard the access to EasyDMA
-  volatile bool dma_running;
+  atomic_bool dma_running;
 }_dcd;
 
 /*------------------------------------------------------------------*/
@@ -121,8 +120,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void)
 // helper to start DMA
 static void start_dma(volatile uint32_t* reg_startep)
 {
-  _dcd.dma_running = true;
-
   (*reg_startep) = 1;
   __ISB(); __DSB();
 
@@ -131,50 +128,18 @@ static void start_dma(volatile uint32_t* reg_startep)
   // Therefore dma_pending is corrected right away
   if ( (reg_startep == &NRF_USBD->TASKS_EP0STATUS) || (reg_startep == &NRF_USBD->TASKS_EP0RCVOUT) )
   {
-    _dcd.dma_running = false;
+    atomic_flag_clear(&_dcd.dma_running);
   }
 }
 
-// only 1 EasyDMA can be active at any time
-// TODO use Cortex M4 LDREX and STREX command (atomic) to have better mutex access to EasyDMA
-// since current implementation does not 100% guarded against race condition
 static void edpt_dma_start(volatile uint32_t* reg_startep)
 {
-  // Called in critical section i.e within USB ISR, or USB/Global interrupt disabled
-  if ( is_in_isr() || __get_PRIMASK() || !NVIC_GetEnableIRQ(USBD_IRQn) )
+  if ( atomic_flag_test_and_set(&_dcd.dma_running) )
   {
-    if (_dcd.dma_running)
-    {
-      //use usbd task to defer later
-      usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true);
-    }else
-    {
-      start_dma(reg_startep);
-    }
+    usbd_defer_func((osal_task_func_t) edpt_dma_start, (void*) (uintptr_t) reg_startep, true);
   }else
   {
-    // Called in non-critical thread-mode, should be 99% of the time.
-    // Should be safe to blocking wait until previous DMA transfer complete
-    uint8_t const rhport = 0;
-    bool started = false;
-    osal_mutex_lock(dcd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-    while(!started)
-    {
-      // LDREX/STREX may be needed in form of std atomic (required C11) or
-      // use osal mutex to guard against multiple core MCUs such as nRF53
-      dcd_int_disable(rhport);
-
-      if ( !_dcd.dma_running )
-      {
-        start_dma(reg_startep);
-        started = true;
-      }
-
-      dcd_int_enable(rhport);
-
-      // osal_yield();
-    }
-    osal_mutex_unlock(dcd_mutex);
+    start_dma(reg_startep);
   }
 }
 
@@ -182,7 +147,7 @@ static void edpt_dma_start(volatile uint32_t* reg_startep)
 static void edpt_dma_end(void)
 {
   TU_ASSERT(_dcd.dma_running, );
-  _dcd.dma_running = false;
+  atomic_flag_clear(&_dcd.dma_running);
 }
 
 // helper getting td
@@ -191,12 +156,26 @@ static inline xfer_td_t* get_td(uint8_t epnum, uint8_t dir)
   return &_dcd.xfer[epnum][dir];
 }
 
+static void xact_out_dma(uint8_t epnum);
+// Function wraps xact_out_dma which wants uint8_t while usbd_defer_func wants void (*)(void *)
+static void xact_out_dma_wrapper(void *epnum)
+{
+  xact_out_dma((uint8_t)((uintptr_t)epnum));
+}
+
 // Start DMA to move data from Endpoint -> RAM
 static void xact_out_dma(uint8_t epnum)
 {
   xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
   uint32_t xact_len;
 
+  // DMA can't be active during read of SIZE.EPOUT or SIZE.ISOOUT, so try to lock,
+  // If already running deffer call regardless if it was called from ISR or task,
+  if ( atomic_flag_test_and_set(&_dcd.dma_running) )
+  {
+    usbd_defer_func((osal_task_func_t)xact_out_dma_wrapper, (void *)(uint32_t)epnum, is_in_isr());
+    return;
+  }
   if (epnum == EP_ISO_NUM)
   {
     xact_len = NRF_USBD->SIZE.ISOOUT;
@@ -204,6 +183,7 @@ static void xact_out_dma(uint8_t epnum)
     if (xact_len & USBD_SIZE_ISOOUT_ZERO_Msk)
     {
       xact_len = 0;
+      atomic_flag_clear(&_dcd.dma_running);
     }
     else
     {
@@ -211,7 +191,7 @@ static void xact_out_dma(uint8_t epnum)
       NRF_USBD->ISOOUT.PTR = (uint32_t) xfer->buffer;
       NRF_USBD->ISOOUT.MAXCNT = xact_len;
 
-      edpt_dma_start(&NRF_USBD->TASKS_STARTISOOUT);
+      start_dma(&NRF_USBD->TASKS_STARTISOOUT);
     }
   }
   else
@@ -223,7 +203,7 @@ static void xact_out_dma(uint8_t epnum)
     NRF_USBD->EPOUT[epnum].PTR = (uint32_t) xfer->buffer;
     NRF_USBD->EPOUT[epnum].MAXCNT = xact_len;
 
-    edpt_dma_start(&NRF_USBD->TASKS_STARTEPOUT[epnum]);
+    start_dma(&NRF_USBD->TASKS_STARTEPOUT[epnum]);
   }
 }
 
@@ -248,7 +228,6 @@ static void xact_in_dma(uint8_t epnum)
 void dcd_init (uint8_t rhport)
 {
   TU_LOG1("dcd init\r\n");
-  dcd_mutex = osal_mutex_create(&dcd_mutex_def);
   (void) rhport;
 }
 
@@ -471,17 +450,10 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 
   xfer_td_t* xfer = get_td(epnum, dir);
 
-  if (!is_in_isr()) {
-    osal_mutex_lock(dcd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-    dcd_int_disable(rhport);
-  }
+  TU_ASSERT(!xfer->started);
   xfer->buffer     = buffer;
   xfer->total_len  = total_bytes;
   xfer->actual_len = 0;
-  if (!is_in_isr()) {
-    dcd_int_enable(rhport);
-    osal_mutex_unlock(dcd_mutex);
-  }
 
   // Control endpoint with zero-length packet and opposite direction to 1st request byte --> status stage
   bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir(NRF_USBD->BMREQUESTTYPE));
@@ -496,13 +468,20 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   }
   else if ( dir == TUSB_DIR_OUT )
   {
+    xfer->started = true;
     if ( epnum == 0 )
     {
       // Accept next Control Out packet. TASKS_EP0RCVOUT also require EasyDMA
       edpt_dma_start(&NRF_USBD->TASKS_EP0RCVOUT);
     }else
     {
-      if ( xfer->data_received && xfer->total_len > xfer->actual_len)
+      // started just set, it could start DMA transfer if interrupt was trigger after this line
+      // code only needs to start transfer (from Endpoint to RAM) when data_received was set
+      // before started was set. If started is NOT set but data_received is, it means that
+      // current transfer was already finished and next data is already present in endpoint and
+      // can be consumed by future transfer
+      __ISB(); __DSB();
+      if ( xfer->data_received && xfer->started )
       {
         // Data is already received previously
         // start DMA to copy to SRAM
@@ -804,7 +783,9 @@ void dcd_int_handler(uint8_t rhport)
         }
       }else
       {
+        TU_ASSERT(xfer->started,);
         xfer->total_len = xfer->actual_len;
+        xfer->started = false;
 
         // CBI OUT complete
         dcd_event_xfer_complete(0, epnum, xfer->actual_len, XFER_RESULT_SUCCESS, true);
@@ -857,7 +838,7 @@ void dcd_int_handler(uint8_t rhport)
       {
         xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
 
-        if (xfer->actual_len < xfer->total_len)
+        if ( xfer->started && xfer->actual_len < xfer->total_len )
         {
           xact_out_dma(epnum);
         }else

From 2571211957b28be7fd706d3cdd4209f17189788a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 3 Jun 2022 11:32:09 +0700
Subject: [PATCH 1048/2085] remove static port defined for device/host

---
 examples/device/cdc_msc/src/main.c |  4 +++-
 hw/bsp/lpc18/family.c              |  4 ++--
 src/tusb.c                         | 10 ++++++----
 src/tusb_option.h                  | 12 +-----------
 4 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index 131ae6549..c3666763b 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -54,7 +54,9 @@ void cdc_task(void);
 int main(void)
 {
   board_init();
-  tusb_init();
+
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index a59b6e89d..0fc788873 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -96,8 +96,8 @@ void board_init(void)
   SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-  NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USB1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
   Chip_GPIO_Init(LPC_GPIO_PORT);
diff --git a/src/tusb.c b/src/tusb.c
index c86bdd891..709bb7d48 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -38,12 +38,14 @@
 
 bool tusb_init(void)
 {
-#if CFG_TUD_ENABLED
-  TU_ASSERT ( tud_init(TUD_OPT_RHPORT) ); // init device stack
+#if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT)
+  // init device stack CFG_TUSB_RHPORTx_MODE must be defined
+  TU_ASSERT ( tud_init(TUD_OPT_RHPORT) );
 #endif
 
-#if CFG_TUH_ENABLED
-  TU_ASSERT( tuh_init(TUH_OPT_RHPORT) ); // init host stack
+#if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT)
+  // init host stack CFG_TUSB_RHPORTx_MODE must be defined
+  TU_ASSERT( tuh_init(TUH_OPT_RHPORT) );
 #endif
 
   return true;
diff --git a/src/tusb_option.h b/src/tusb_option.h
index c198e4ef3..0a0b20dca 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -197,15 +197,6 @@ typedef int make_iso_compilers_happy ;
 
 //------------- Roothub as Device -------------//
 
-//#ifndef CFG_TUSB_RHPORT0_MODE
-//  #define CFG_TUSB_RHPORT0_MODE OPT_MODE_NONE
-//#endif
-//
-//#ifndef CFG_TUSB_RHPORT1_MODE
-//  #define CFG_TUSB_RHPORT1_MODE OPT_MODE_NONE
-//#endif
-
-
 #if defined(CFG_TUSB_RHPORT0_MODE) && ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE)
   #define TUD_RHPORT_MODE     (CFG_TUSB_RHPORT0_MODE)
   #define TUD_OPT_RHPORT      0
@@ -214,7 +205,6 @@ typedef int make_iso_compilers_happy ;
   #define TUD_OPT_RHPORT      1
 #else
   #define TUD_RHPORT_MODE     OPT_MODE_NONE
-  #define TUD_OPT_RHPORT      -1
 #endif
 
 #ifndef CFG_TUD_ENABLED
@@ -228,7 +218,7 @@ typedef int make_iso_compilers_happy ;
 #endif
 
 // highspeed support indicator
-#define TUD_OPT_HIGH_SPEED  (CFG_TUD_MAX_SPEED ? CFG_TUD_MAX_SPEED : TUP_RHPORT_HIGHSPEED)
+#define TUD_OPT_HIGH_SPEED    (CFG_TUD_MAX_SPEED ? CFG_TUD_MAX_SPEED : TUP_RHPORT_HIGHSPEED)
 
 //------------- Roothub as Host -------------//
 

From 31134f41a17c004aa48d87e397a6bae061f5b328 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 3 Jun 2022 17:24:28 +0700
Subject: [PATCH 1049/2085] make dwc2 stm32 rhport support dynamic

---
 src/portable/synopsys/dwc2/dcd_dwc2.c   | 80 ++++++++++++++-----------
 src/portable/synopsys/dwc2/dwc2_stm32.h | 63 ++++++++++++-------
 src/portable/synopsys/dwc2/dwc2_type.h  | 17 ++++--
 3 files changed, 98 insertions(+), 62 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index e489f6445..4d9e43ba8 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -50,12 +50,14 @@
   #error "Unsupported MCUs"
 #endif
 
+// Note _dwc2_controller[] must be defined by port header
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
 // DWC2 registers
-#define DWC2_REG(_port)       ((dwc2_regs_t*) DWC2_REG_BASE)
+#define DWC2_REG(_port)       ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
 
 // Debug level for DWC2
 #define DWC2_DEBUG    2
@@ -72,7 +74,6 @@
 #define dcache_clean_invalidate(_addr, _size)
 #endif
 
-
 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
 
 typedef struct {
@@ -97,34 +98,32 @@ static bool     _out_ep_closed;                   // Flag to check if RX FIFO si
 static bool _sof_en;
 
 // Calculate the RX FIFO size according to recommendations from reference manual
-static inline uint16_t calc_rx_ff_size(uint16_t ep_size)
+static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count)
 {
-  return 15 + 2*(ep_size/4) + 2*DWC2_EP_MAX;
+  return 15 + 2*(max_ep_size/4) + 2*ep_count;
 }
 
 static void update_grxfsiz(uint8_t rhport)
 {
-  (void) rhport;
-
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   // Determine largest EP size for RX FIFO
   uint16_t max_epsize = 0;
-  for (uint8_t epnum = 0; epnum < DWC2_EP_MAX; epnum++)
+  for (uint8_t epnum = 0; epnum < ep_count; epnum++)
   {
     max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size);
   }
 
   // Update size of RX FIFO
-  dwc2->grxfsiz = calc_rx_ff_size(max_epsize);
+  dwc2->grxfsiz = calc_grxfsiz(max_epsize, ep_count);
 }
 
-// Setup the control endpoint 0.
+// Start of Bus Reset
 static void bus_reset(uint8_t rhport)
 {
-  (void) rhport;
-
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   tu_memclr(xfer_status, sizeof(xfer_status));
   _out_ep_closed = false;
@@ -135,7 +134,7 @@ static void bus_reset(uint8_t rhport)
   dwc2->dcfg &= ~DCFG_DAD_Msk;
 
   // 1. NAK for all OUT endpoints
-  for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
+  for ( uint8_t n = 0; n < ep_count; n++ )
   {
     dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
   }
@@ -185,22 +184,24 @@ static void bus_reset(uint8_t rhport)
   //   - 2 for each used OUT endpoint
   //
   //   Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum
-  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x DWC2_EP_MAX = 47  + 2 x DWC2_EP_MAX
-  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x DWC2_EP_MAX = 271 + 2 x DWC2_EP_MAX
+  //   - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x  16 + 2 x ep_count = 47  + 2 x ep_count
+  //   - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x ep_count = 271 + 2 x ep_count
   //
   //   NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge
-  //   of the overall picture yet. We will use the worst scenario: largest possible + DWC2_EP_MAX
+  //   of the overall picture yet. We will use the worst scenario: largest possible + ep_count
   //
   //   For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO
   //   are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended.  Maybe provide a macro for application to
   //   overwrite this.
 
-  dwc2->grxfsiz = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64);
+  // EP0 out max is 64
+  dwc2->grxfsiz = calc_grxfsiz(64, ep_count);
 
+  // Setup the control endpoint 0
   _allocated_fifo_words_tx = 16;
 
   // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-  dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+  dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx);
 
   // Fixed control EP0 size to 64 bytes
   dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos);
@@ -363,7 +364,11 @@ static void reset_core(dwc2_regs_t * dwc2)
 static bool phy_hs_supported(dwc2_regs_t * dwc2)
 {
   // note: esp32 incorrect report its hs_phy_type as utmi
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  return false;
+#else
   return TUD_OPT_HIGH_SPEED && dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE;
+#endif
 }
 
 static void phy_fs_init(dwc2_regs_t * dwc2)
@@ -620,12 +625,13 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 {
   (void) rhport;
 
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(desc_edpt->bEndpointAddress);
 
-  TU_ASSERT(epnum < DWC2_EP_MAX);
+  TU_ASSERT(epnum < ep_count);
 
   xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
   xfer->max_size = tu_edpt_packet_size(desc_edpt);
@@ -636,12 +642,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   if(dir == TUSB_DIR_OUT)
   {
     // Calculate required size of RX FIFO
-    uint16_t const sz = calc_rx_ff_size(4*fifo_size);
+    uint16_t const sz = calc_grxfsiz(4*fifo_size, ep_count);
 
     // If size_rx needs to be extended check if possible and if so enlarge it
     if (dwc2->grxfsiz < sz)
     {
-      TU_ASSERT(sz + _allocated_fifo_words_tx <= DWC2_EP_FIFO_SIZE/4);
+      TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size/4);
 
       // Enlarge RX FIFO
       dwc2->grxfsiz = sz;
@@ -678,15 +684,15 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
     // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
 
     // Check if free space is available
-    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= DWC2_EP_FIFO_SIZE/4);
+    TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size/4);
 
     _allocated_fifo_words_tx += fifo_size;
 
-    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %u", fifo_size*4, DWC2_EP_FIFO_SIZE-_allocated_fifo_words_tx*4);
+    TU_LOG(DWC2_DEBUG, "    Allocated %u bytes at offset %lu", fifo_size*4, _dwc2_controller[rhport].ep_fifo_size-_allocated_fifo_words_tx*4);
 
     // DIEPTXF starts at FIFO #1.
     // Both TXFD and TXSA are in unit of 32-bit words.
-    dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx);
+    dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | (_dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx);
 
     dwc2->epin[epnum].diepctl |= (1 << DIEPCTL_USBAEP_Pos) |
                                  (epnum << DIEPCTL_TXFNUM_Pos) |
@@ -703,14 +709,13 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
 // Close all non-control endpoints, cancel all pending transfers if any.
 void dcd_edpt_close_all (uint8_t rhport)
 {
-  (void) rhport;
-
-  dwc2_regs_t * dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   // Disable non-control interrupt
   dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
 
-  for(uint8_t n = 1; n < DWC2_EP_MAX; n++)
+  for(uint8_t n = 1; n < ep_count; n++)
   {
     // disable OUT endpoint
     dwc2->epout[n].doepctl = 0;
@@ -871,8 +876,9 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
   {
     uint16_t const fifo_size = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXFD_Msk) >> DIEPTXF_INEPTXFD_Pos;
     uint16_t const fifo_start = (dwc2->dieptxf[epnum - 1] & DIEPTXF_INEPTXSA_Msk) >> DIEPTXF_INEPTXSA_Pos;
+
     // For now only the last opened endpoint can be closed without fuss.
-    TU_ASSERT(fifo_start == DWC2_EP_FIFO_SIZE/4 - _allocated_fifo_words_tx,);
+    TU_ASSERT(fifo_start == _dwc2_controller[rhport].ep_fifo_size/4 - _allocated_fifo_words_tx,);
     _allocated_fifo_words_tx -= fifo_size;
   }
   else
@@ -1075,11 +1081,12 @@ static void handle_rxflvl_irq(uint8_t rhport)
 
 static void handle_epout_irq (uint8_t rhport)
 {
-  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
+  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
 
   // DAINT for a given EP clears when DOEPINTx is cleared.
   // OEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
+  for ( uint8_t n = 0; n < ep_count; n++ )
   {
     if ( dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n) )
     {
@@ -1126,12 +1133,13 @@ static void handle_epout_irq (uint8_t rhport)
 
 static void handle_epin_irq (uint8_t rhport)
 {
-  dwc2_regs_t *dwc2 = DWC2_REG(rhport);
-  dwc2_epin_t* epin = dwc2->epin;
+  dwc2_regs_t * dwc2     = DWC2_REG(rhport);
+  uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
+  dwc2_epin_t* epin      = dwc2->epin;
 
   // DAINT for a given EP clears when DIEPINTx is cleared.
   // IEPINT will be cleared when DAINT's out bits are cleared.
-  for ( uint8_t n = 0; n < DWC2_EP_MAX; n++ )
+  for ( uint8_t n = 0; n < ep_count; n++ )
   {
     if ( dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n) )
     {
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index d54bf1fd7..23632616a 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -56,12 +56,9 @@
   #define EP_FIFO_SIZE_FS 4096
   #define EP_MAX_HS       9
   #define EP_FIFO_SIZE_HS 4096
-  #if (! defined USB2_OTG_FS)
-    // H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
-    // USB_OTG_FS_PERIPH_BASE and OTG_FS_IRQn not defined
-    #define USB_OTG_FS_PERIPH_BASE  USB1_OTG_HS_PERIPH_BASE
-    #define OTG_FS_IRQn             OTG_HS_IRQn
-  #endif
+
+  // NOTE: H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
+  // USB_OTG_FS_PERIPH_BASE and OTG_FS_IRQn not defined
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
   #include "stm32f7xx.h"
@@ -79,35 +76,57 @@
   #error "Unsupported MCUs"
 #endif
 
-// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
-#if TUD_OPT_RHPORT == 0
-  #define DWC2_REG_BASE       USB_OTG_FS_PERIPH_BASE
-  #define DWC2_EP_MAX         EP_MAX_FS
-  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_FS
-  #define RHPORT_IRQn         OTG_FS_IRQn
-
+// OTG HS always has higher number of endpoints than FS
+#ifdef EP_MAX_HS
+  #define DWC2_EP_MAX   EP_MAX_HS
 #else
-  #define DWC2_REG_BASE       USB_OTG_HS_PERIPH_BASE
-  #define DWC2_EP_MAX         EP_MAX_HS
-  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_HS
-  #define RHPORT_IRQn         OTG_HS_IRQn
-
+  #define DWC2_EP_MAX   EP_MAX_FS
 #endif
 
+// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
+//#if TUD_OPT_RHPORT == 0
+//  #define DWC2_REG_BASE       USB_OTG_FS_PERIPH_BASE
+//  #define DWC2_EP_MAX         EP_MAX_FS
+//  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_FS
+//  #define RHPORT_IRQn         OTG_FS_IRQn
+//
+//#else
+//  #define DWC2_REG_BASE       USB_OTG_HS_PERIPH_BASE
+//  #define DWC2_EP_MAX         EP_MAX_HS
+//  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_HS
+//  #define RHPORT_IRQn         OTG_HS_IRQn
+//
+//#endif
+
+// On STM32 for consistency we associate
+// - Port0 to OTG_FS, and Port1 to OTG_HS
+static const dwc2_controller_t _dwc2_controller[] =
+{
+#ifdef USB_OTG_FS_PERIPH_BASE
+  { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS},
+#endif
+
+#ifdef USB_OTG_HS_PERIPH_BASE
+  { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS},
+#endif
+};
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 extern uint32_t SystemCoreClock;
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_EnableIRQ(RHPORT_IRQn);
+  NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_DisableIRQ(RHPORT_IRQn);
+  NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
 }
 
 TU_ATTR_ALWAYS_INLINE
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index 7fa2028eb..e9df7335e 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -19,6 +19,19 @@
 
 #include "stdint.h"
 
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// Controller
+typedef struct
+{
+  uint32_t reg_base;
+  uint32_t irqnum;
+  uint8_t  ep_count;
+  uint32_t ep_fifo_size;
+}dwc2_controller_t;
+
 /* DWC OTG HW Release versions */
 #define DWC2_CORE_REV_2_71a   0x4f54271a
 #define DWC2_CORE_REV_2_72a   0x4f54272a
@@ -40,10 +53,6 @@
 #define DWC2_FS_IOT_ID        0x55310000
 #define DWC2_HS_IOT_ID        0x55320000
 
-#ifdef __cplusplus
- extern "C" {
-#endif
-
 #if 0
 // HS PHY
 typedef struct

From 7df7590f7f96f0647e3164c7c7b368decffc87a2 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sun, 29 May 2022 14:01:24 +0930
Subject: [PATCH 1050/2085] Hub: Remove multi-level hub bypass

---
 src/host/usbh.c | 47 +++++++++++++++++++----------------------------
 1 file changed, 19 insertions(+), 28 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index af2ad0575..908230c83 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1513,40 +1513,31 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
-    if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && dev->hub_addr != 0)
+    // Find driver for this interface
+    uint8_t drv_id;
+    for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
     {
-      // TODO Attach hub to Hub is not currently supported
-      // skip this interface
-      TU_LOG(USBH_DBG_LVL, "Only 1 level of HUB is supported\r\n");
-    }
-    else
-    {
-      // Find driver for this interface
-      uint8_t drv_id;
-      for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+
+      if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
       {
-        usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+        // open successfully
+        TU_LOG2("  %s opened\r\n", driver->name);
 
-        if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
+        // bind (associated) interfaces to found driver
+        for(uint8_t i=0; i<assoc_itf_count; i++)
         {
-          // open successfully
-          TU_LOG2("  %s opened\r\n", driver->name);
+          uint8_t const itf_num = desc_itf->bInterfaceNumber+i;
 
-          // bind (associated) interfaces to found driver
-          for(uint8_t i=0; i<assoc_itf_count; i++)
-          {
-            uint8_t const itf_num = desc_itf->bInterfaceNumber+i;
-
-            // Interface number must not be used already
-            TU_ASSERT( DRVID_INVALID == dev->itf2drv[itf_num] );
-            dev->itf2drv[itf_num] = drv_id;
-          }
-
-          // bind all endpoints to found driver
-          tu_edpt_bind_driver(dev->ep2drv, desc_itf, drv_len, drv_id);
-
-          break; // exit driver find loop
+          // Interface number must not be used already
+          TU_ASSERT( DRVID_INVALID == dev->itf2drv[itf_num] );
+          dev->itf2drv[itf_num] = drv_id;
         }
+
+        // bind all endpoints to found driver
+        tu_edpt_bind_driver(dev->ep2drv, desc_itf, drv_len, drv_id);
+
+        break; // exit driver find loop
       }
 
       if( drv_id >= USBH_CLASS_DRIVER_COUNT )

From f626916a5733fc7beff29ff6f907433e28ff14e0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 4 Jun 2022 23:52:12 +0700
Subject: [PATCH 1051/2085] update all dwc2 ports to support new dynamic
 controller support

---
 src/portable/synopsys/dwc2/dcd_dwc2.c   | 10 ++++++++--
 src/portable/synopsys/dwc2/dwc2_bcm.h   | 13 +++++++------
 src/portable/synopsys/dwc2/dwc2_efm32.h | 12 +++++++-----
 src/portable/synopsys/dwc2/dwc2_esp32.h |  8 +++++---
 src/portable/synopsys/dwc2/dwc2_gd32.h  | 13 +++++++------
 src/portable/synopsys/dwc2/dwc2_stm32.h | 19 ++-----------------
 src/portable/synopsys/dwc2/dwc2_type.h  |  8 ++++----
 src/portable/synopsys/dwc2/dwc2_xmc.h   | 15 ++++++++-------
 8 files changed, 48 insertions(+), 50 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 4d9e43ba8..f5ecdfe4f 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -34,6 +34,13 @@
 #include "device/dcd.h"
 #include "dwc2_type.h"
 
+// Following symbols must be defined by port header
+// - _dwc2_controller[]: array of controllers
+// - DWC2_EP_MAX: largest EP counts of all controllers
+// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
+// - dwc2_dcd_int_enable/dwc2_dcd_int_disable
+// - dwc2_remote_wakeup_delay
+
 #if defined(TUP_USBIP_DWC2_STM32)
   #include "dwc2_stm32.h"
 #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
@@ -50,8 +57,6 @@
   #error "Unsupported MCUs"
 #endif
 
-// Note _dwc2_controller[] must be defined by port header
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -467,6 +472,7 @@ static bool check_dwc2(dwc2_regs_t * dwc2)
 #endif
 
   // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
+  (void) dwc2;
 #if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
   uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
   TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);
diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
index 14194e754..732d96ae0 100644
--- a/src/portable/synopsys/dwc2/dwc2_bcm.h
+++ b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -35,9 +35,12 @@
 #include "broadcom/interrupts.h"
 #include "broadcom/caches.h"
 
-#define DWC2_REG_BASE       USB_OTG_GLOBAL_BASE
 #define DWC2_EP_MAX         8
-#define DWC2_EP_FIFO_SIZE   4096
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+  { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 4096 }
+};
 
 #define dcache_clean(_addr, _size)              data_clean(_addr, _size)
 #define dcache_invalidate(_addr, _size)         data_invalidate(_addr, _size)
@@ -46,15 +49,13 @@
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport;
-  BP_EnableIRQ(USB_IRQn);
+  BP_EnableIRQ(_dwc2_controller[rhport].irqnum);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
-  (void) rhport;
-  BP_DisableIRQ(USB_IRQn);
+  BP_DisableIRQ(_dwc2_controller[rhport].irqnum);
 }
 
 static inline void dwc2_remote_wakeup_delay(void)
diff --git a/src/portable/synopsys/dwc2/dwc2_efm32.h b/src/portable/synopsys/dwc2/dwc2_efm32.h
index ee4c3c715..0e3570cbb 100644
--- a/src/portable/synopsys/dwc2/dwc2_efm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_efm32.h
@@ -37,20 +37,22 @@
 // EFM32 has custom control register before DWC registers
 #define DWC2_REG_BASE       (USB_BASE + offsetof(USB_TypeDef, GOTGCTL))
 #define DWC2_EP_MAX         7
-#define DWC2_EP_FIFO_SIZE   2048
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+  { .reg_base = DWC2_REG_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 2048 }
+};
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_EnableIRQ(USB_IRQn);
+  NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_DisableIRQ(USB_IRQn);
+  NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
 }
 
 static inline void dwc2_remote_wakeup_delay(void)
diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h
index 78da277d5..c50dd66b8 100644
--- a/src/portable/synopsys/dwc2/dwc2_esp32.h
+++ b/src/portable/synopsys/dwc2/dwc2_esp32.h
@@ -37,10 +37,12 @@
 //#include "soc/usb_periph.h"
 
 #define DWC2_REG_BASE       0x60080000UL
-#define DWC2_EP_MAX         5             // USB_OUT_EP_NUM
-#define DWC2_EP_FIFO_SIZE   1024
+#define DWC2_EP_MAX         6             // USB_OUT_EP_NUM. TODO ESP32Sx only has 5 tx fifo (5 endpoint IN)
 
-// #define EP_FIFO_NUM 5
+static const dwc2_controller_t _dwc2_controller[] =
+{
+  { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1024 }
+};
 
 static intr_handle_t usb_ih;
 
diff --git a/src/portable/synopsys/dwc2/dwc2_gd32.h b/src/portable/synopsys/dwc2/dwc2_gd32.h
index f8fa01ee0..0375fffe4 100644
--- a/src/portable/synopsys/dwc2/dwc2_gd32.h
+++ b/src/portable/synopsys/dwc2/dwc2_gd32.h
@@ -34,8 +34,11 @@
 
 #define DWC2_REG_BASE       0x50000000UL
 #define DWC2_EP_MAX         4
-#define DWC2_EP_FIFO_SIZE   1280
-#define RHPORT_IRQn         86
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+  { .reg_base = DWC2_REG_BASE, .irqnum = 86, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1280 }
+};
 
 extern uint32_t SystemCoreClock;
 
@@ -57,15 +60,13 @@ static inline void __eclic_disable_interrupt (uint32_t irq){
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport;
-  __eclic_enable_interrupt(RHPORT_IRQn);
+  __eclic_enable_interrupt(_dwc2_controller[rhport].irqnum);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
-  (void) rhport;
-  __eclic_disable_interrupt(RHPORT_IRQn);
+  __eclic_disable_interrupt(_dwc2_controller[rhport].irqnum);
 }
 
 static inline void dwc2_remote_wakeup_delay(void)
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 23632616a..709428f7f 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -83,31 +83,16 @@
   #define DWC2_EP_MAX   EP_MAX_FS
 #endif
 
-// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
-//#if TUD_OPT_RHPORT == 0
-//  #define DWC2_REG_BASE       USB_OTG_FS_PERIPH_BASE
-//  #define DWC2_EP_MAX         EP_MAX_FS
-//  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_FS
-//  #define RHPORT_IRQn         OTG_FS_IRQn
-//
-//#else
-//  #define DWC2_REG_BASE       USB_OTG_HS_PERIPH_BASE
-//  #define DWC2_EP_MAX         EP_MAX_HS
-//  #define DWC2_EP_FIFO_SIZE   EP_FIFO_SIZE_HS
-//  #define RHPORT_IRQn         OTG_HS_IRQn
-//
-//#endif
-
 // On STM32 for consistency we associate
 // - Port0 to OTG_FS, and Port1 to OTG_HS
 static const dwc2_controller_t _dwc2_controller[] =
 {
 #ifdef USB_OTG_FS_PERIPH_BASE
-  { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS},
+  { .reg_base = USB_OTG_FS_PERIPH_BASE, .irqnum = OTG_FS_IRQn, .ep_count = EP_MAX_FS, .ep_fifo_size = EP_FIFO_SIZE_FS },
 #endif
 
 #ifdef USB_OTG_HS_PERIPH_BASE
-  { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS},
+  { .reg_base = USB_OTG_HS_PERIPH_BASE, .irqnum = OTG_HS_IRQn, .ep_count = EP_MAX_HS, .ep_fifo_size = EP_FIFO_SIZE_HS },
 #endif
 };
 
diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
index e9df7335e..3fc979337 100644
--- a/src/portable/synopsys/dwc2/dwc2_type.h
+++ b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -26,10 +26,10 @@
 // Controller
 typedef struct
 {
-  uint32_t reg_base;
-  uint32_t irqnum;
-  uint8_t  ep_count;
-  uint32_t ep_fifo_size;
+  uintptr_t reg_base;
+  uint32_t  irqnum;
+  uint8_t   ep_count;
+  uint32_t  ep_fifo_size;
 }dwc2_controller_t;
 
 /* DWC OTG HW Release versions */
diff --git a/src/portable/synopsys/dwc2/dwc2_xmc.h b/src/portable/synopsys/dwc2/dwc2_xmc.h
index 4e6bebb01..63419abf7 100644
--- a/src/portable/synopsys/dwc2/dwc2_xmc.h
+++ b/src/portable/synopsys/dwc2/dwc2_xmc.h
@@ -34,23 +34,24 @@
 
 #include "xmc_device.h"
 
-// XMC has custom control register before DWC registers
-#define DWC2_REG_BASE       USB0_BASE
 #define DWC2_EP_MAX         7
-#define DWC2_EP_FIFO_SIZE   2048
+
+static const dwc2_controller_t _dwc2_controller[] =
+{
+  // Note: XMC has some custom control registers before DWC registers
+  { .reg_base = USB0_BASE, .irqnum = USB0_0_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 2048 }
+};
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_EnableIRQ(USB0_0_IRQn);
+  NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_DisableIRQ(USB0_0_IRQn);
+  NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
 }
 
 static inline void dwc2_remote_wakeup_delay(void)

From 7187cd9a8528bfe2b570567ca2d0a2ae36b7c478 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Jun 2022 12:51:10 +0700
Subject: [PATCH 1052/2085] fix ci, remove use of CFG_TUSB_RHPORT0_MODE in bsp

---
 hw/bsp/ea4088qs/ea4088qs.c               |  6 ++--
 hw/bsp/ea4357/ea4357.c                   | 36 ++++++++++++++--------
 hw/bsp/fomu/fomu.c                       |  2 +-
 hw/bsp/imxrt/family.c                    | 38 +++++++++++++++++-------
 hw/bsp/lpc54/family.c                    | 19 ++++++++----
 hw/bsp/lpc55/family.c                    | 16 ++++++++--
 hw/bsp/lpcxpresso1769/lpcxpresso1769.c   |  8 ++---
 hw/bsp/mbed1768/mbed1768.c               |  8 ++---
 hw/bsp/ngx4330/ngx4330.c                 | 35 +++++++++++++---------
 hw/bsp/samg55xplained/samg55xplained.c   |  2 +-
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c |  2 +-
 11 files changed, 114 insertions(+), 58 deletions(-)

diff --git a/hw/bsp/ea4088qs/ea4088qs.c b/hw/bsp/ea4088qs/ea4088qs.c
index b25f9101c..fa905b2f9 100644
--- a/hw/bsp/ea4088qs/ea4088qs.c
+++ b/hw/bsp/ea4088qs/ea4088qs.c
@@ -32,11 +32,11 @@
 //--------------------------------------------------------------------+
 void USB_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+  #if CFG_TUD_ENABLED
     tuh_int_handler(0);
   #endif
 
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+  #if CFG_TUH_ENABLED
     tud_int_handler(0);
   #endif
 }
@@ -115,7 +115,7 @@ void board_init(void)
   SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
   Chip_GPIO_Init(LPC_GPIO);
diff --git a/hw/bsp/ea4357/ea4357.c b/hw/bsp/ea4357/ea4357.c
index aa206a28d..2c1d08770 100644
--- a/hw/bsp/ea4357/ea4357.c
+++ b/hw/bsp/ea4357/ea4357.c
@@ -53,6 +53,18 @@
 //    {0x02, 7, 0, 7  }, // SW6
 //};
 
+#ifdef BOARD_TUD_RHPORT
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
 /*------------------------------------------------------------------*/
 /* BOARD API
  *------------------------------------------------------------------*/
@@ -116,7 +128,7 @@ void board_init(void)
   SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
   Chip_GPIO_Init(LPC_GPIO_PORT);
@@ -170,7 +182,7 @@ void board_init(void)
    * - Insert jumpers in position 2-3 in JP17/JP18/JP19
    * - Insert jumpers in JP31 (OTG)
    */
-#if CFG_TUSB_RHPORT0_MODE
+#if PORT_SUPPORT_DEVICE(0) || PORT_SUPPORT_HOST(0)
   Chip_USB0_Init();
 #endif
 
@@ -195,14 +207,14 @@ void board_init(void)
    * - LED34 lights green when +5V is available on J20.
    * - JP15 shall not be inserted. JP16 has no effect
    */
-#if CFG_TUSB_RHPORT1_MODE
+#if PORT_SUPPORT_DEVICE(1) || PORT_SUPPORT_HOST(1)
   Chip_USB1_Init();
 #endif
 
   // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board)
   Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7);
 
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+  #if PORT_SUPPORT_DEVICE(0)
   // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low.
   Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4);
   Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18);
@@ -217,23 +229,23 @@ void board_init(void)
 //--------------------------------------------------------------------+
 void USB0_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
+  #if PORT_SUPPORT_DEVICE(0)
+    tud_int_handler(0);
   #endif
 
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
+  #if PORT_SUPPORT_HOST(0)
+    tuh_int_handler(0);
   #endif
 }
 
 void USB1_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    tuh_int_handler(1);
+  #if PORT_SUPPORT_DEVICE(1)
+    tud_int_handler(1);
   #endif
 
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-    tud_int_handler(1);
+  #if PORT_SUPPORT_HOST(1)
+    tuh_int_handler(1);
   #endif
 }
 
diff --git a/hw/bsp/fomu/fomu.c b/hw/bsp/fomu/fomu.c
index 12b7bfd18..33c630303 100644
--- a/hw/bsp/fomu/fomu.c
+++ b/hw/bsp/fomu/fomu.c
@@ -61,7 +61,7 @@ void isr(void)
 
   irqs = irq_pending() & irq_getmask();
 
-#if CFG_TUSB_RHPORT0_MODE == OPT_MODE_DEVICE
+#if CFG_TUD_ENABLED
   if (irqs & (1 << USB_INTERRUPT)) {
     tud_int_handler(0);
   }
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 8d34d4b9f..e5f630108 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -34,9 +34,25 @@
 
 #include "clock_config.h"
 
+#ifdef BOARD_TUD_RHPORT
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
 // needed by fsl_flexspi_nor_boot
 const uint8_t dcd_data[] = { 0x00 };
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 void board_init(void)
 {
   // Init clock
@@ -51,9 +67,9 @@ void board_init(void)
   SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
-#ifdef USB_OTG2_IRQn
-  NVIC_SetPriority(USB_OTG2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#ifdef USBPHY2
+  NVIC_SetPriority(USB_OTG2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 #endif
 
@@ -149,23 +165,23 @@ void board_init(void)
 //--------------------------------------------------------------------+
 void USB_OTG1_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
+  #if PORT_SUPPORT_DEVICE(0)
+    tud_int_handler(0);
   #endif
 
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
+  #if PORT_SUPPORT_HOST(0)
+    tuh_int_handler(0);
   #endif
 }
 
 void USB_OTG2_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    tuh_int_handler(1);
+  #if PORT_SUPPORT_DEVICE(1)
+    tud_int_handler(1);
   #endif
 
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-    tud_int_handler(1);
+  #if PORT_SUPPORT_HOST(1)
+    tuh_int_handler(1);
   #endif
 }
 
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index 4f1199c3a..9bb341e73 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -33,6 +33,18 @@
 #include "bsp/board.h"
 #include "board.h"
 
+#ifdef BOARD_TUD_RHPORT
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -152,8 +164,7 @@ void board_init(void)
 
 #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
   // LPC546xx and LPC540xx has OTG 1 FS + 1 HS rhports
-
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+  #if PORT_SUPPORT_DEVICE(0)
     // Port0 is Full Speed
     POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB Phy */
     CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
@@ -167,7 +178,7 @@ void board_init(void)
     CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq());
   #endif
 
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
+  #if PORT_SUPPORT_DEVICE(1)
     // Port1 is High Speed
     POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
 
@@ -178,10 +189,8 @@ void board_init(void)
 
     CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUsbPll, 0U);
   #endif
-
 #else
   // LPC5411x series only has full speed device
-
   POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); // Turn on USB Phy
   CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); /* enable USB IP clock */
 #endif
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index f037a9f5b..e7aed5759 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -34,6 +34,18 @@
 #include "fsl_sctimer.h"
 #include "sct_neopixel.h"
 
+#ifdef BOARD_TUD_RHPORT
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -164,7 +176,7 @@ void board_init(void)
   /* PORT0 PIN22 configured as USB0_VBUS */
   IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+#if PORT_SUPPORT_DEVICE(0)
   // Port0 is Full Speed
 
   /* Turn on USB0 Phy */
@@ -189,7 +201,7 @@ void board_init(void)
   CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
 #endif
 
-#if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
+#if PORT_SUPPORT_DEVICE(1)
   // Port1 is High Speed
 
   /* Turn on USB1 Phy */
diff --git a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
index b82e5ffe0..b7bce93d2 100644
--- a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
+++ b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
@@ -32,12 +32,12 @@
 //--------------------------------------------------------------------+
 void USB_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
+  #if CFG_TUD_ENABLED
+    tud_int_handler(0);
   #endif
 
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
+  #if CFG_TUH_ENABLED
+    tuh_int_handler(0);
   #endif
 }
 
diff --git a/hw/bsp/mbed1768/mbed1768.c b/hw/bsp/mbed1768/mbed1768.c
index 7c2b37016..08cf3adbd 100644
--- a/hw/bsp/mbed1768/mbed1768.c
+++ b/hw/bsp/mbed1768/mbed1768.c
@@ -146,12 +146,12 @@ void board_init(void)
 //--------------------------------------------------------------------+
 void USB_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
+  #if CFG_TUD_ENABLED
+    tud_int_handler(0);
   #endif
 
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
+  #if CFG_TUH_ENABLED
+    tuh_int_handler(0);
   #endif
 }
 
diff --git a/hw/bsp/ngx4330/ngx4330.c b/hw/bsp/ngx4330/ngx4330.c
index b63f9b894..4fc314165 100644
--- a/hw/bsp/ngx4330/ngx4330.c
+++ b/hw/bsp/ngx4330/ngx4330.c
@@ -40,6 +40,18 @@
 #define BOARD_UART_PIN_TX         10 // PF.10 : UART0_TXD
 #define BOARD_UART_PIN_RX         11 // PF.11 : UART0_RXD
 
+#ifdef BOARD_TUD_RHPORT
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
 /*------------------------------------------------------------------*/
 /* BOARD API
  *------------------------------------------------------------------*/
@@ -120,7 +132,7 @@ void board_init(void)
   SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
   Chip_GPIO_Init(LPC_GPIO_PORT);
@@ -167,9 +179,7 @@ void board_init(void)
    * status feedback from the distribution switch. GPIO54 is used for VBUS sensing. 15Kohm pull-down
    * resistors are always active
    */
-#if CFG_TUSB_RHPORT0_MODE
   Chip_USB0_Init();
-#endif
 
   /* USB1
    * When USB channel #1 is used as USB Host, 15Kohm pull-down resistors are needed on the USB data
@@ -189,12 +199,9 @@ void board_init(void)
    * of VBUS can be read via U31.
    * JP16 shall not be inserted.
    */
-#if CFG_TUSB_RHPORT1_MODE
   Chip_USB1_Init();
-
 //	Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 6);							/* GPIO5[6] = USB1_PWR_EN */
 //	Chip_GPIO_SetPinState(LPC_GPIO_PORT, 5, 6, true);							/* GPIO5[6] output high */
-#endif
 }
 
 //--------------------------------------------------------------------+
@@ -202,23 +209,23 @@ void board_init(void)
 //--------------------------------------------------------------------+
 void USB0_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
-    tuh_int_handler(0);
+  #if PORT_SUPPORT_DEVICE(0)
+    tud_int_handler(0);
   #endif
 
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
-    tud_int_handler(0);
+  #if PORT_SUPPORT_HOST(0)
+    tuh_int_handler(0);
   #endif
 }
 
 void USB1_IRQHandler(void)
 {
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST
-    tuh_int_handler(1);
+  #if PORT_SUPPORT_DEVICE(1)
+    tud_int_handler(1);
   #endif
 
-  #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE
-    tud_int_handler(1);
+  #if PORT_SUPPORT_HOST(1)
+    tuh_int_handler(1);
   #endif
 }
 
diff --git a/hw/bsp/samg55xplained/samg55xplained.c b/hw/bsp/samg55xplained/samg55xplained.c
index ed106b06b..027c88e2f 100644
--- a/hw/bsp/samg55xplained/samg55xplained.c
+++ b/hw/bsp/samg55xplained/samg55xplained.c
@@ -99,7 +99,7 @@ void board_init(void)
 //--------------------------------------------------------------------+
 void UDP_Handler(void)
 {
-  #if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+  #if CFG_TUD_ENABLED
     tud_int_handler(0);
   #endif
 }
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 7a65cf5d0..2445593fe 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -312,7 +312,7 @@ static void _dcd_ft90x_detach(void)
 
 // Determine the speed of the USB to which we are connected.
 // Set the speed of the PHY accordingly. 
-// High speed can be disabled through CFG_TUSB_RHPORT0_MODE settings.
+// High speed can be disabled through CFG_TUSB_RHPORT0_MODE or CFG_TUD_MAX_SPEED settings.
 static void _ft90x_usb_speed(void)
 {
 	uint8_t  fctrl_val;

From 1b086729452c67e3e78a736506732ca013959572 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Jun 2022 13:25:48 +0700
Subject: [PATCH 1053/2085] more ci fix

---
 hw/bsp/imxrt/family.c                   | 4 ++--
 src/portable/synopsys/dwc2/dwc2_stm32.h | 5 ++++-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index e5f630108..fc6e9e266 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -34,13 +34,13 @@
 
 #include "clock_config.h"
 
-#ifdef BOARD_TUD_RHPORT
+#if defined(BOARD_TUD_RHPORT) && CFG_TUD_ENABLED
   #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
 #else
   #define PORT_SUPPORT_DEVICE(_n)  0
 #endif
 
-#ifdef BOARD_TUH_RHPORT
+#if defined(BOARD_TUH_RHPORT) && CFG_TUH_ENABLED
   #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
 #else
   #define PORT_SUPPORT_HOST(_n)    0
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 709428f7f..b500ddc46 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -47,6 +47,7 @@
   #include "stm32f4xx.h"
   #define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
   #define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
+
   #define EP_MAX_HS       USB_OTG_HS_MAX_IN_ENDPOINTS
   #define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE
 
@@ -54,6 +55,7 @@
   #include "stm32h7xx.h"
   #define EP_MAX_FS       9
   #define EP_FIFO_SIZE_FS 4096
+
   #define EP_MAX_HS       9
   #define EP_FIFO_SIZE_HS 4096
 
@@ -64,6 +66,7 @@
   #include "stm32f7xx.h"
   #define EP_MAX_FS       6
   #define EP_FIFO_SIZE_FS 1280
+
   #define EP_MAX_HS       9
   #define EP_FIFO_SIZE_HS 4096
 
@@ -77,7 +80,7 @@
 #endif
 
 // OTG HS always has higher number of endpoints than FS
-#ifdef EP_MAX_HS
+#ifdef USB_OTG_HS_PERIPH_BASE
   #define DWC2_EP_MAX   EP_MAX_HS
 #else
   #define DWC2_EP_MAX   EP_MAX_FS

From f4c80dd218240d934a28cb21d8ddd6a0e3a33fe5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Jun 2022 17:35:17 +0700
Subject: [PATCH 1054/2085] clean up example to use CFG_TUD_ENABLED +
 CFG_TUD_MAX_SPEED instead of CFG_TUSB_RHPORT0_MODE

---
 .../device/audio_4_channel_mic/src/main.c     |  3 +-
 .../audio_4_channel_mic/src/tusb_config.h     | 63 +++++++++++--------
 examples/device/board_test/src/tusb_config.h  | 19 +-----
 examples/device/cdc_msc/src/tusb_config.h     | 39 ++++++------
 examples/device/cdc_msc_freertos/src/main.c   |  3 +-
 .../device/cdc_msc_freertos/src/tusb_config.h | 57 ++++++++---------
 6 files changed, 89 insertions(+), 95 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index d085dd43a..9c94edd49 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -81,7 +81,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   // Init values
   sampFreq = AUDIO_SAMPLE_RATE;
diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index 023faa7e2..0f5fbfef7 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -30,6 +30,20 @@
 extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
@@ -39,18 +53,19 @@ extern "C" {
 #error CFG_TUSB_MCU must be defined
 #endif
 
-#define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE
-
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS                 OPT_OS_NONE
+#define CFG_TUSB_OS               OPT_OS_NONE
 #endif
 
 #ifndef CFG_TUSB_DEBUG
-#define CFG_TUSB_DEBUG              0
+#define CFG_TUSB_DEBUG            0
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+// Enable Device stack
+#define CFG_TUD_ENABLED           1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED         BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -64,7 +79,7 @@ extern "C" {
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
@@ -75,13 +90,7 @@ extern "C" {
 #define CFG_TUD_ENDPOINT0_SIZE    64
 #endif
 
-//------------- CLASS -------------//
-#define CFG_TUD_CDC               0
-#define CFG_TUD_MSC               0
-#define CFG_TUD_HID               0
-#define CFG_TUD_MIDI              0
 #define CFG_TUD_AUDIO             1
-#define CFG_TUD_VENDOR            0
 
 //--------------------------------------------------------------------
 // AUDIO CLASS DRIVER CONFIGURATION
@@ -89,23 +98,23 @@ extern "C" {
 
 // Have a look into audio_device.h for all configurations
 
-#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                 TUD_AUDIO_MIC_FOUR_CH_DESC_LEN
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                 TUD_AUDIO_MIC_FOUR_CH_DESC_LEN
 
-#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT                                 1
-#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ                              64
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT                 1
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ              64
 
-#define CFG_TUD_AUDIO_ENABLE_EP_IN                                    1
-#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX                    2         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
-#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                            4         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
-#define CFG_TUD_AUDIO_EP_SZ_IN                                        (48 + 1) * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX      // 48 Samples (48 kHz) x 2 Bytes/Sample x CFG_TUD_AUDIO_N_CHANNELS_TX Channels - the Windows driver always needs an extra sample per channel of space more, otherwise it complains... found by trial and error
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX                             CFG_TUD_AUDIO_EP_SZ_IN
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ                          CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_ENABLE_EP_IN                    1
+#define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX    2         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX            4         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
+#define CFG_TUD_AUDIO_EP_SZ_IN                        (48 + 1) * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX      // 48 Samples (48 kHz) x 2 Bytes/Sample x CFG_TUD_AUDIO_N_CHANNELS_TX Channels - the Windows driver always needs an extra sample per channel of space more, otherwise it complains... found by trial and error
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          CFG_TUD_AUDIO_EP_SZ_IN
 
-#define CFG_TUD_AUDIO_ENABLE_ENCODING                                 1
-#define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING                          1
-#define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX                      2         // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
-#define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO                        (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
-#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ                       (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO)
+#define CFG_TUD_AUDIO_ENABLE_ENCODING                 1
+#define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING          1
+#define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX      2         // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
+#define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO        (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
+#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO)
 
 #ifdef __cplusplus
 }
diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h
index da33729e7..5aea4fd2c 100644
--- a/examples/device/board_test/src/tusb_config.h
+++ b/examples/device/board_test/src/tusb_config.h
@@ -43,7 +43,9 @@
   #define CFG_TUSB_OS               OPT_OS_NONE
 #endif
 
-#define CFG_TUSB_RHPORT0_MODE       OPT_MODE_NONE
+// This example only test LED & GPIO, disable both device and host stack
+#define CFG_TUD_ENABLED   0
+#define CFG_TUH_ENABLED   0
 
 // CFG_TUSB_DEBUG is defined by compiler in DEBUG build
 // #define CFG_TUSB_DEBUG           0
@@ -63,21 +65,6 @@
 #define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
 #endif
 
-//--------------------------------------------------------------------
-// DEVICE CONFIGURATION
-//--------------------------------------------------------------------
-
-#ifndef CFG_TUD_ENDPOINT0_SIZE
-#define CFG_TUD_ENDPOINT0_SIZE   64
-#endif
-
-//------------- CLASS -------------//
-#define CFG_TUD_CDC             0
-#define CFG_TUD_MSC             0
-#define CFG_TUD_HID             0
-#define CFG_TUD_MIDI            0
-#define CFG_TUD_VENDOR          0
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/examples/device/cdc_msc/src/tusb_config.h b/examples/device/cdc_msc/src/tusb_config.h
index 363da88d7..03e0e649c 100644
--- a/examples/device/cdc_msc/src/tusb_config.h
+++ b/examples/device/cdc_msc/src/tusb_config.h
@@ -30,42 +30,43 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
-// COMMON CONFIGURATION
+// Common Configuration
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
+#error CFG_TUSB_MCU must be defined
 #endif
 
-// This example doesn't use an RTOS
 #ifndef CFG_TUSB_OS
-  #define CFG_TUSB_OS         OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
 #ifndef CFG_TUSB_DEBUG
-  #define CFG_TUSB_DEBUG      0
+#define CFG_TUSB_DEBUG        0
 #endif
 
 // Enable Device stack
 #define CFG_TUD_ENABLED       1
 
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
 // Default is max speed that hardware controller could support with on-chip PHY
 #define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -78,7 +79,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN    __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index a5e907199..755220c13 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -123,9 +123,10 @@ void usb_device_task(void* param)
 {
   (void) param;
 
+  // init device stack on configured roothub port
   // This should be called after scheduler/kernel is started.
   // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
-  tusb_init();
+  tud_init(BOARD_TUD_RHPORT);
 
   // RTOS forever loop
   while (1)
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index d8eeda07d..0ec8896b9 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -30,53 +30,48 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT     0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
 // defined by board.mk
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
-#ifndef BOARD_TUD_MAX_SPEED
-  #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \
-       CFG_TUSB_MCU == OPT_MCU_NUC505  || CFG_TUSB_MCU == OPT_MCU_CXD56)
-    #define BOARD_TUD_MAX_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_TUD_MAX_SPEED   OPT_MODE_FULL_SPEED
-  #endif
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 // This examples use FreeRTOS
-#define CFG_TUSB_OS               OPT_OS_FREERTOS
+#define CFG_TUSB_OS           OPT_OS_FREERTOS
 
 // Espressif IDF requires "freertos/" prefix in include path
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-  #define CFG_TUSB_OS_INC_PATH    freertos/
+#define CFG_TUSB_OS_INC_PATH  freertos/
 #endif
 
 // can be defined by compiler in DEBUG build
 #ifndef CFG_TUSB_DEBUG
-  #define CFG_TUSB_DEBUG           0
+#define CFG_TUSB_DEBUG        0
 #endif
 
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -89,7 +84,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN    __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
@@ -97,7 +92,7 @@
 //--------------------------------------------------------------------
 
 #ifndef CFG_TUD_ENDPOINT0_SIZE
-#define CFG_TUD_ENDPOINT0_SIZE    64
+#define CFG_TUD_ENDPOINT0_SIZE   64
 #endif
 
 //------------- CLASS -------------//

From 9794a2b865df81e667b464481bb9b1c70587e64b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Jun 2022 22:41:04 +0700
Subject: [PATCH 1055/2085] more example update

---
 .../audio_4_channel_mic/src/tusb_config.h     |  6 ++
 examples/device/audio_test/src/main.c         |  3 +-
 examples/device/audio_test/src/tusb_config.h  | 24 +++++++-
 examples/device/cdc_dual_ports/src/main.c     |  3 +-
 .../device/cdc_dual_ports/src/tusb_config.h   | 49 ++++++++--------
 examples/device/dfu/src/main.c                |  3 +-
 examples/device/dfu/src/tusb_config.h         | 57 ++++++++++---------
 examples/device/dfu_runtime/src/main.c        |  3 +-
 examples/device/dfu_runtime/src/tusb_config.h | 51 +++++++++--------
 .../device/dynamic_configuration/src/main.c   |  4 +-
 .../dynamic_configuration/src/tusb_config.h   | 53 ++++++++---------
 examples/device/hid_boot_interface/src/main.c |  4 +-
 .../hid_boot_interface/src/tusb_config.h      | 57 +++++++++----------
 examples/device/hid_composite/src/main.c      |  4 +-
 .../device/hid_composite/src/tusb_config.h    | 51 +++++++++--------
 .../device/hid_composite_freertos/src/main.c  |  3 +-
 .../hid_composite_freertos/src/tusb_config.h  | 50 ++++++++--------
 examples/device/hid_generic_inout/src/main.c  |  3 +-
 .../hid_generic_inout/src/tusb_config.h       | 53 ++++++++---------
 .../device/hid_multiple_interface/src/main.c  |  4 +-
 .../hid_multiple_interface/src/tusb_config.h  | 51 +++++++++--------
 examples/device/midi_test/src/main.c          |  3 +-
 examples/device/midi_test/src/tusb_config.h   | 53 ++++++++---------
 examples/device/msc_dual_lun/src/main.c       |  3 +-
 .../device/msc_dual_lun/src/tusb_config.h     | 53 ++++++++---------
 examples/device/net_lwip_webserver/src/main.c |  4 +-
 .../net_lwip_webserver/src/tusb_config.h      | 45 ++++++++-------
 examples/device/uac2_headset/src/main.c       |  3 +-
 .../device/uac2_headset/src/tusb_config.h     | 39 +++++++++----
 examples/device/usbtmc/src/main.c             |  3 +-
 examples/device/usbtmc/src/tusb_config.h      | 45 ++++++++-------
 examples/device/video_capture/src/main.c      |  4 +-
 .../device/video_capture/src/tusb_config.h    | 41 +++++++------
 examples/device/webusb_serial/src/main.c      |  3 +-
 .../device/webusb_serial/src/tusb_config.h    | 45 ++++++++-------
 35 files changed, 478 insertions(+), 402 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index 0f5fbfef7..5cf6d07c3 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -90,7 +90,13 @@ extern "C" {
 #define CFG_TUD_ENDPOINT0_SIZE    64
 #endif
 
+//------------- CLASS -------------//
 #define CFG_TUD_AUDIO             1
+#define CFG_TUD_CDC               0
+#define CFG_TUD_MSC               0
+#define CFG_TUD_HID               0
+#define CFG_TUD_MIDI              0
+#define CFG_TUD_VENDOR            0
 
 //--------------------------------------------------------------------
 // AUDIO CLASS DRIVER CONFIGURATION
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index ed13ce993..51f55b772 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -82,7 +82,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   // Init values
   sampFreq = AUDIO_SAMPLE_RATE;
diff --git a/examples/device/audio_test/src/tusb_config.h b/examples/device/audio_test/src/tusb_config.h
index 9b8514265..355ed1011 100644
--- a/examples/device/audio_test/src/tusb_config.h
+++ b/examples/device/audio_test/src/tusb_config.h
@@ -30,6 +30,20 @@
 extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
@@ -39,8 +53,6 @@ extern "C" {
 #error CFG_TUSB_MCU must be defined
 #endif
 
-#define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE
-
 #ifndef CFG_TUSB_OS
 #define CFG_TUSB_OS                 OPT_OS_NONE
 #endif
@@ -49,6 +61,12 @@ extern "C" {
 #define CFG_TUSB_DEBUG              0
 #endif
 
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
 // CFG_TUSB_DEBUG is defined by compiler in DEBUG build
 // #define CFG_TUSB_DEBUG           0
 
@@ -76,11 +94,11 @@ extern "C" {
 #endif
 
 //------------- CLASS -------------//
+#define CFG_TUD_AUDIO             1
 #define CFG_TUD_CDC               0
 #define CFG_TUD_MSC               0
 #define CFG_TUD_HID               0
 #define CFG_TUD_MIDI              0
-#define CFG_TUD_AUDIO             1
 #define CFG_TUD_VENDOR            0
 
 //--------------------------------------------------------------------
diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 34cd29edd..6053a3b81 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -39,7 +39,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/cdc_dual_ports/src/tusb_config.h b/examples/device/cdc_dual_ports/src/tusb_config.h
index 037fc8290..070f08ed1 100644
--- a/examples/device/cdc_dual_ports/src/tusb_config.h
+++ b/examples/device/cdc_dual_ports/src/tusb_config.h
@@ -30,41 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
 // defined by board.mk
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS                 OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 5c8464526..6bb183819 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -74,7 +74,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/dfu/src/tusb_config.h b/examples/device/dfu/src/tusb_config.h
index 924ede47a..38064147c 100644
--- a/examples/device/dfu/src/tusb_config.h
+++ b/examples/device/dfu/src/tusb_config.h
@@ -12,41 +12,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -60,7 +61,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
@@ -72,10 +73,10 @@
 #endif
 
 //------------- CLASS -------------//
-#define CFG_TUD_DFU    1
+#define CFG_TUD_DFU               1
 
 // DFU buffer size, it has to be set to the buffer size used in TUD_DFU_DESCRIPTOR
-#define CFG_TUD_DFU_XFER_BUFSIZE    ( OPT_MODE_HIGH_SPEED ? 512 : 64 )
+#define CFG_TUD_DFU_XFER_BUFSIZE  (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 #ifdef __cplusplus
  }
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index 823c71ae5..55b380353 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -69,7 +69,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/dfu_runtime/src/tusb_config.h b/examples/device/dfu_runtime/src/tusb_config.h
index f31c9c970..fa1ae6ed3 100644
--- a/examples/device/dfu_runtime/src/tusb_config.h
+++ b/examples/device/dfu_runtime/src/tusb_config.h
@@ -12,41 +12,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index 4c10f55b0..95f8b8286 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -55,7 +55,9 @@ void midi_task(void);
 int main(void)
 {
   board_init();
-  tusb_init();
+
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/dynamic_configuration/src/tusb_config.h b/examples/device/dynamic_configuration/src/tusb_config.h
index 333b62e03..b9b3878cc 100644
--- a/examples/device/dynamic_configuration/src/tusb_config.h
+++ b/examples/device/dynamic_configuration/src/tusb_config.h
@@ -30,41 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -78,7 +79,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index e5e2f6856..21cdb383d 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -55,7 +55,9 @@ void hid_task(void);
 int main(void)
 {
   board_init();
-  tusb_init();
+
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/hid_boot_interface/src/tusb_config.h b/examples/device/hid_boot_interface/src/tusb_config.h
index e3c50aa3f..52723e09f 100644
--- a/examples/device/hid_boot_interface/src/tusb_config.h
+++ b/examples/device/hid_boot_interface/src/tusb_config.h
@@ -30,45 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// Use raspberry pio-usb for device
-// #define CFG_TUD_RPI_PIO_USB     1
-// #define BOARD_TUD_RHPORT 1
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -82,7 +79,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index fd25e620a..bc2347ab8 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -56,7 +56,9 @@ void hid_task(void);
 int main(void)
 {
   board_init();
-  tusb_init();
+
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/hid_composite/src/tusb_config.h b/examples/device/hid_composite/src/tusb_config.h
index 1a9223f5b..6bd32c427 100644
--- a/examples/device/hid_composite/src/tusb_config.h
+++ b/examples/device/hid_composite/src/tusb_config.h
@@ -30,41 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 317b64611..1030f3d05 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -125,9 +125,10 @@ void usb_device_task(void* param)
 {
   (void) param;
 
+  // init device stack on configured roothub port
   // This should be called after scheduler/kernel is started.
   // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
-  tusb_init();
+  tud_init(BOARD_TUD_RHPORT);
 
   // RTOS forever loop
   while (1)
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index 8fd6498e6..935ae9453 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -30,48 +30,48 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT     0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
 // defined by board.mk
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 // This examples use FreeRTOS
-#define CFG_TUSB_OS               OPT_OS_FREERTOS
+#define CFG_TUSB_OS           OPT_OS_FREERTOS
 
 // Espressif IDF requires "freertos/" prefix in include path
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-  #define CFG_TUSB_OS_INC_PATH    freertos/
+#define CFG_TUSB_OS_INC_PATH  freertos/
 #endif
 
-
+// can be defined by compiler in DEBUG build
 #ifndef CFG_TUSB_DEBUG
-#define CFG_TUSB_DEBUG           0
+#define CFG_TUSB_DEBUG        0
 #endif
 
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 32185560e..5b7daf118 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -80,7 +80,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/hid_generic_inout/src/tusb_config.h b/examples/device/hid_generic_inout/src/tusb_config.h
index e5ae4b0cc..98143ac4d 100644
--- a/examples/device/hid_generic_inout/src/tusb_config.h
+++ b/examples/device/hid_generic_inout/src/tusb_config.h
@@ -30,41 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -78,7 +79,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c
index 7cb1d75a7..29ba74398 100644
--- a/examples/device/hid_multiple_interface/src/main.c
+++ b/examples/device/hid_multiple_interface/src/main.c
@@ -60,7 +60,9 @@ void hid_task(void);
 int main(void)
 {
   board_init();
-  tusb_init();
+
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/hid_multiple_interface/src/tusb_config.h b/examples/device/hid_multiple_interface/src/tusb_config.h
index 766b8e518..49dc962fe 100644
--- a/examples/device/hid_multiple_interface/src/tusb_config.h
+++ b/examples/device/hid_multiple_interface/src/tusb_config.h
@@ -30,41 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 193748477..b47d1af76 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -62,7 +62,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/midi_test/src/tusb_config.h b/examples/device/midi_test/src/tusb_config.h
index a7673245e..314dde438 100644
--- a/examples/device/midi_test/src/tusb_config.h
+++ b/examples/device/midi_test/src/tusb_config.h
@@ -30,41 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -78,7 +79,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index 0293261ad..96790d20c 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -54,7 +54,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/msc_dual_lun/src/tusb_config.h b/examples/device/msc_dual_lun/src/tusb_config.h
index 2778e61b0..9cbbbade9 100644
--- a/examples/device/msc_dual_lun/src/tusb_config.h
+++ b/examples/device/msc_dual_lun/src/tusb_config.h
@@ -30,41 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
-#ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -78,7 +79,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 30bb3577b..33b4d38b6 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -228,7 +228,9 @@ int main(void)
 {
   /* initialize TinyUSB */
   board_init();
-  tusb_init();
+
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   /* initialize lwip, dhcp-server, dns-server, and http */
   init_lwip();
diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h
index 5042c0e5d..fe72ecdfe 100644
--- a/examples/device/net_lwip_webserver/src/tusb_config.h
+++ b/examples/device/net_lwip_webserver/src/tusb_config.h
@@ -30,41 +30,42 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------
-// COMMON CONFIGURATION
-//--------------------------------------------------------------------
-
-// defined by board.mk
-#ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
 
 // RHPort number used for device can be defined by board.mk, default to port 0
 #ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
+#define BOARD_TUD_RHPORT      0
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -78,7 +79,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index bbaacd975..a8d204eaa 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -102,7 +102,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   TU_LOG1("Headset running\r\n");
 
diff --git a/examples/device/uac2_headset/src/tusb_config.h b/examples/device/uac2_headset/src/tusb_config.h
index 2a1189a79..1a3e23e95 100644
--- a/examples/device/uac2_headset/src/tusb_config.h
+++ b/examples/device/uac2_headset/src/tusb_config.h
@@ -31,30 +31,45 @@
 extern "C" {
 #endif
 
-//--------------------------------------------------------------------
-// COMMON CONFIGURATION
-//--------------------------------------------------------------------
-
 #include "usb_descriptors.h"
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
 // defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
 #error CFG_TUSB_MCU must be defined
 #endif
 
-#define CFG_TUSB_RHPORT0_MODE       OPT_MODE_DEVICE
-
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS                 OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
 #ifndef CFG_TUSB_DEBUG
-// Can be set during compilation i.e.: make LOG=<value for CFG_TUSB_DEBUG> BOARD=<bsp>
-// Keep in mind that enabling logs when data is streaming can disrupt data flow.
-// It can be very helpful though when audio unit requests are tested/debugged.
-#define CFG_TUSB_DEBUG              0
+#define CFG_TUSB_DEBUG        0
 #endif
 
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -67,7 +82,7 @@ extern "C" {
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 1fce48f45..6945d8743 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -54,7 +54,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/usbtmc/src/tusb_config.h b/examples/device/usbtmc/src/tusb_config.h
index 0b2df291a..ab486b108 100644
--- a/examples/device/usbtmc/src/tusb_config.h
+++ b/examples/device/usbtmc/src/tusb_config.h
@@ -12,41 +12,42 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------
-// COMMON CONFIGURATION
-//--------------------------------------------------------------------
-
-// defined by board.mk
-#ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
 
 // RHPort number used for device can be defined by board.mk, default to port 0
 #ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
+#define BOARD_TUD_RHPORT      0
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -60,7 +61,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index f1d48385f..4028352da 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -55,7 +55,9 @@ void video_task(void);
 int main(void)
 {
   board_init();
-  tusb_init();
+
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index 85bf80a64..e567ba669 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -30,37 +30,42 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------
-// COMMON CONFIGURATION
-//--------------------------------------------------------------------
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
 
 // RHPort number used for device can be defined by board.mk, default to port 0
 #ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
+#define BOARD_TUD_RHPORT      0
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
 #endif
 
-// This example doesn't use an RTOS
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -74,7 +79,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index 2716825f8..8eaad7706 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -93,7 +93,8 @@ int main(void)
 {
   board_init();
 
-  tusb_init();
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
 
   while (1)
   {
diff --git a/examples/device/webusb_serial/src/tusb_config.h b/examples/device/webusb_serial/src/tusb_config.h
index eab1d6387..fde732b9e 100644
--- a/examples/device/webusb_serial/src/tusb_config.h
+++ b/examples/device/webusb_serial/src/tusb_config.h
@@ -30,41 +30,42 @@
  extern "C" {
 #endif
 
-//--------------------------------------------------------------------
-// COMMON CONFIGURATION
-//--------------------------------------------------------------------
-
-// defined by board.mk
-#ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
 
 // RHPort number used for device can be defined by board.mk, default to port 0
 #ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
+#define BOARD_TUD_RHPORT      0
 #endif
 
 // RHPort max operational speed can defined by board.mk
-// Default to max (auto) speed for MCU with internal HighSpeed PHY
 #ifndef BOARD_TUD_MAX_SPEED
-  #define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
 #endif
 
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
@@ -78,7 +79,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------

From 7c8278303bc14770ea9fcd9f6e4a9dbba32572e3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Jun 2022 23:16:49 +0700
Subject: [PATCH 1056/2085] update all host examples

---
 .../dual/host_hid_to_device_cdc/src/main.c    |   4 +-
 .../host_hid_to_device_cdc/src/tusb_config.h  | 106 ++++++++----------
 examples/host/bare_api/src/main.c             |   6 +-
 examples/host/bare_api/src/tusb_config.h      |  35 ++++--
 examples/host/cdc_msc_hid/src/main.c          |   3 +-
 examples/host/cdc_msc_hid/src/tusb_config.h   |  42 ++++---
 examples/host/hid_controller/src/main.c       |   5 +-
 .../host/hid_controller/src/tusb_config.h     |  35 ++++--
 src/tusb_option.h                             |   8 ++
 9 files changed, 141 insertions(+), 103 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index 62ecb2c3f..6a25a28da 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -79,7 +79,9 @@ int main(void)
 
   printf("TinyUSB Host HID <-> Device CDC Example\r\n");
 
-  tusb_init();
+  // init device and host stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
+  tuh_init(BOARD_TUH_RHPORT);
 
   while (1)
   {
diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
index 9a8f31da0..f749bd712 100644
--- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
+++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
@@ -30,75 +30,61 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+// RHPort number used for host can be defined by board.mk, default to port 1
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      1
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
-// defined by board.mk
+// defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
+#error CFG_TUSB_MCU must be defined
 #endif
 
-// RHPort number used for device can be defined by board.mk, default to port 0
-#ifndef BOARD_TUD_RHPORT
-  #define BOARD_TUD_RHPORT     0
-#endif
-
-// RHPort number used for device can be defined by board.mk, default to port 1
-#ifndef BOARD_TUH_RHPORT
-  #define BOARD_TUH_RHPORT     1
-#endif
-
-// Use raspberry pio-usb for host
-#define CFG_TUH_RPI_PIO_USB            1
-
-// RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
-#ifndef BOARD_TUD_MAX_SPEED
-  #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
-      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) ||\
-      TU_CHECK_MCU(OPT_MCU_FT90X, OPT_MCU_FT93X)
-    #define BOARD_TUD_MAX_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_TUD_MAX_SPEED   OPT_MODE_FULL_SPEED
-  #endif
-#endif
-
-// RHPort max operational speed can defined by board.mk
-// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed
-#ifndef BOARD_TUH_MAX_SPEED
-  #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX, OPT_MCU_MIMXRT10XX, OPT_MCU_NUC505) ||\
-      TU_CHECK_MCU(OPT_MCU_CXD56, OPT_MCU_SAMX7X, OPT_MCU_BCM2711) ||\
-      TU_CHECK_MCU(OPT_MCU_FT90X, OPT_MCU_FT93X)
-    #define BOARD_TUH_MAX_SPEED   OPT_MODE_HIGH_SPEED
-  #else
-    #define BOARD_TUH_MAX_SPEED   OPT_MODE_FULL_SPEED
-  #endif
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUD_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#elif BOARD_TUD_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_DEVICE | BOARD_TUD_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
-#endif
-
-// Device mode with rhport and speed defined by board.mk
-#if   BOARD_TUH_RHPORT == 0
-  #define CFG_TUSB_RHPORT0_MODE     (OPT_MODE_HOST | BOARD_TUH_MAX_SPEED)
-#elif BOARD_TUH_RHPORT == 1
-  #define CFG_TUSB_RHPORT1_MODE     (OPT_MODE_HOST | BOARD_TUH_MAX_SPEED)
-#else
-  #error "Incorrect RHPort configuration"
-#endif
-
-// This example doesn't use an RTOS
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS               OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack, Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_ENABLED       1
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+// Enable Host stack, Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_ENABLED       1
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+// Use pico-pio-usb as host controller for raspberry rp2040
+#define CFG_TUH_RPI_PIO_USB   1
+#endif
+
+
 // CFG_TUSB_DEBUG is defined by compiler in DEBUG build
 // #define CFG_TUSB_DEBUG           0
 
@@ -114,7 +100,7 @@
 #endif
 
 #ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index eb3f7d8d7..2cc05d34d 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -62,8 +62,10 @@ int main(void)
 {
   board_init();
 
-  printf("TinyUSB Host HID Controller Example\r\n");
-  tusb_init();
+  printf("TinyUSB Bare API Example\r\n");
+
+  // init host stack on configured roothub port
+  tuh_init(BOARD_TUH_RHPORT);
 
   while (1)
   {
diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index 9b789290d..ed0aaf7da 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -30,27 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-  #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
-#else
-  #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS                 OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index 0fc7ef146..664cbf035 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -45,7 +45,8 @@ int main(void)
 
   printf("TinyUSB Host CDC MSC HID Example\r\n");
 
-  tusb_init();
+  // init host stack on configured roothub port
+  tuh_init(BOARD_TUH_RHPORT);
 
   while (1)
   {
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index e9e68cf5a..76d96b556 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -30,34 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-// Use raspberry pio-usb for host
-// #define CFG_TUH_RPI_PIO_USB            1
-// #define CFG_TUH_RPI_PIO_USB            1
-
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-  #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
-#elif defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB
-  // rp2040: port0 is native, port 1 for PIO-USB
-  #define CFG_TUSB_RHPORT1_MODE       OPT_MODE_HOST
-#else
-  #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS                 OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index b9b37a4d2..299a3ff10 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -49,9 +49,10 @@ int main(void)
   board_init();
 
   printf("TinyUSB Host HID Controller Example\r\n");
-  printf("Note: Events only displayed for explictly supported controllers\r\n");
+  printf("Note: Events only displayed for explicit supported controllers\r\n");
 
-  tusb_init();
+  // init host stack on configured roothub port
+  tuh_init(BOARD_TUH_RHPORT);
 
   while (1)
   {
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index 74b471ae4..475b9ca8f 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -30,27 +30,42 @@
  extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
 
 // defined by compiler flags for flexibility
 #ifndef CFG_TUSB_MCU
-  #error CFG_TUSB_MCU must be defined
-#endif
-
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
-  #define CFG_TUSB_RHPORT0_MODE       (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED)
-#else
-  #define CFG_TUSB_RHPORT0_MODE       OPT_MODE_HOST
+#error CFG_TUSB_MCU must be defined
 #endif
 
 #ifndef CFG_TUSB_OS
-#define CFG_TUSB_OS                 OPT_OS_NONE
+#define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 0a0b20dca..e332c5728 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -238,11 +238,19 @@ typedef int make_iso_compilers_happy ;
   #define CFG_TUH_ENABLED     (TUH_RHPORT_MODE & OPT_MODE_HOST)
 #endif
 
+#ifndef CFG_TUH_MAX_SPEED
+  // fallback to use CFG_TUSB_RHPORTx_MODE
+  #define CFG_TUH_MAX_SPEED   (TUH_RHPORT_MODE & OPT_MODE_SPEED_MASK)
+#endif
+
 // For backward compatible
 #define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED
 #define TUSB_OPT_HOST_ENABLED   CFG_TUH_ENABLED
 
+//--------------------------------------------------------------------+
 // TODO move later
+//--------------------------------------------------------------------+
+
 // TUP_MCU_STRICT_ALIGN will overwrite TUP_ARCH_STRICT_ALIGN.
 // In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler
 // to generate unaligned access code.

From 06392247ebce685a7bd81da4f3f38722767288c2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 7 Jun 2022 11:50:50 +0700
Subject: [PATCH 1057/2085] add TU_ATTR_FAST_FUNC for audio sof isr call chain

---
 src/class/audio/audio_device.c | 2 +-
 src/class/audio/audio_device.h | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index a2801e299..dbd8ab54b 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2114,7 +2114,7 @@ uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles)
 }
 #endif
 
-void audiod_sof_isr (uint8_t rhport, uint32_t frame_count)
+TU_ATTR_FAST_FUNC void audiod_sof_isr (uint8_t rhport, uint32_t frame_count)
 {
   (void) rhport;
   (void) frame_count;
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 13f24fb62..0ef100fa4 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -524,10 +524,10 @@ typedef struct {
 TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param);
 
 // Callback in ISR context, invoked periodically according to feedback endpoint bInterval.
-// Could be used to compute and update feedback value
+// Could be used to compute and update feedback value, should be placed in RAM if possible
 // frame_number  : current SOF count
 // interval_shift: number of bit shift i.e log2(interval) from Feedback endpoint descriptor
-TU_ATTR_WEAK void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift);
+TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift);
 
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 

From 8cbc34de11ccaaf0831cda14ad703d8d962ae725 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Jun 2022 01:17:01 +0700
Subject: [PATCH 1058/2085] add tuh_configure() for port/dynamic host behavior
 config

---
 hw/bsp/rp2040/family.c                        | 16 +++++++-
 src/device/usbd.c                             |  2 +-
 src/host/hcd.h                                |  5 ++-
 src/host/usbh.c                               | 39 ++++++++++++-------
 src/host/usbh.h                               | 16 +++++++-
 .../raspberrypi/pio_usb/hcd_pio_usb.c         | 12 +++++-
 6 files changed, 67 insertions(+), 23 deletions(-)

diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 8de1c1aab..68c9e2d52 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -35,6 +35,13 @@
 #include "bsp/board.h"
 #include "board.h"
 
+#if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
+#include "pio_usb.h"
+#endif
+
+// PIO_USB_DP_PIN_DEFAULT is 0, which conflict with UART, change to 2
+#define PICO_PIO_USB_PIN_DP   2
+
 #ifdef BUTTON_BOOTSEL
 // This example blinks the Picoboard LED when the BOOTSEL button is pressed.
 //
@@ -130,6 +137,12 @@ void board_init(void)
 #if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
   // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb
   set_sys_clock_khz(120000, true);
+
+  // rp2040 use pico-pio-usb for host tuh_configure() can be used to passed pio configuration to the host stack
+  // Note: tuh_configure() must be called before tuh_init()
+  pio_usb_configuration_t pio_cfg = PIO_USB_DEFAULT_CONFIG;
+  pio_cfg.pin_dp = PICO_PIO_USB_PIN_DP;
+  tuh_configure(BOARD_TUH_RHPORT, TUH_CFGID_RPI_PIO_USB_CONFIGURATION, &pio_cfg);
 #endif
 
 #if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
@@ -142,9 +155,8 @@ void board_init(void)
   stdio_rtt_init();
 #endif
 
-  // todo probably set up device mode?
 #if CFG_TUD_ENABLED
-
+  // TODO probably set up device mode?
 #endif
 
 #if CFG_TUH_ENABLED
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 55e478a4e..697477584 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -392,7 +392,7 @@ bool tud_init (uint8_t rhport)
   // skip if already initialized
   if ( tud_inited() ) return true;
 
-  TU_LOG2("USBD init\r\n");
+  TU_LOG2("USBD init rhport %u\r\n", rhport);
   TU_LOG2_INT(sizeof(usbd_device_t));
 
   tu_varclr(&_usbd_dev);
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 036394c72..2bc85034f 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -48,7 +48,7 @@
 //  #endif
 #endif
 
- //--------------------------------------------------------------------+
+//--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 typedef enum
@@ -106,6 +106,9 @@ typedef struct
 // Controller API
 //--------------------------------------------------------------------+
 
+// optional hcd configuration, called by tuh_config()
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_ATTR_WEAK;
+
 // Initialize controller to host mode
 bool hcd_init(uint8_t rhport);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index e0e41a8d1..ab2d8770a 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -274,9 +274,32 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
 static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
+#if CFG_TUSB_OS == OPT_OS_NONE
+// TODO rework time-related function later
+void osal_task_delay(uint32_t msec)
+{
+  (void) msec;
+
+  const uint32_t start = hcd_frame_number(TUH_OPT_RHPORT);
+  while ( ( hcd_frame_number(TUH_OPT_RHPORT) - start ) < msec ) {}
+}
+#endif
+
 //--------------------------------------------------------------------+
 // PUBLIC API (Parameter Verification is required)
 //--------------------------------------------------------------------+
+
+bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param)
+{
+  if (hcd_configure)
+  {
+    return hcd_configure(rhport, cfg_id, cfg_param);
+  }else
+  {
+    return false;
+  }
+}
+
 bool tuh_mounted(uint8_t dev_addr)
 {
   usbh_device_t* dev = get_device(dev_addr);
@@ -303,20 +326,6 @@ tusb_speed_t tuh_speed_get (uint8_t dev_addr)
   return (tusb_speed_t) (dev ? get_device(dev_addr)->speed : _dev0.speed);
 }
 
-#if CFG_TUSB_OS == OPT_OS_NONE
-void osal_task_delay(uint32_t msec)
-{
-  (void) msec;
-
-  const uint32_t start = hcd_frame_number(TUH_OPT_RHPORT);
-  while ( ( hcd_frame_number(TUH_OPT_RHPORT) - start ) < msec ) {}
-}
-#endif
-
-//--------------------------------------------------------------------+
-// CLASS-USBD API (don't require to verify parameters)
-//--------------------------------------------------------------------+
-
 static void clear_device(usbh_device_t* dev)
 {
   tu_memclr(dev, sizeof(usbh_device_t));
@@ -334,7 +343,7 @@ bool tuh_init(uint8_t rhport)
   // skip if already initialized
   if (_usbh_initialized) return _usbh_initialized;
 
-  TU_LOG2("USBH init\r\n");
+  TU_LOG2("USBH init rhport %u\r\n", rhport);
   TU_LOG2_INT(sizeof(usbh_device_t));
   TU_LOG2_INT(sizeof(hcd_event_t));
   TU_LOG2_INT(sizeof(_ctrl_xfer));
diff --git a/src/host/usbh.h b/src/host/usbh.h
index c6d36fb7f..4c65da206 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -46,8 +46,8 @@ typedef void (*tuh_xfer_cb_t)(tuh_xfer_t* xfer);
 
 // Note1: layout and order of this will be changed in near future
 // it is advised to initialize it using member name
-// Note2: not all field is available/meaningful in callback, some info is not saved by
-// usbh to save SRAM
+// Note2: not all field is available/meaningful in callback,
+// some info is not saved by usbh to save SRAM
 struct tuh_xfer_s
 {
   uint8_t daddr;
@@ -69,6 +69,12 @@ struct tuh_xfer_s
   // uint32_t timeout_ms;    // place holder, not supported yet
 };
 
+// ConfigID for tuh_config()
+enum
+{
+  TUH_CFGID_RPI_PIO_USB_CONFIGURATION = OPT_MCU_RP2040 // cfg_param: pio_usb_configuration_t
+};
+
 //--------------------------------------------------------------------+
 // APPLICATION CALLBACK
 //--------------------------------------------------------------------+
@@ -85,6 +91,12 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
 // APPLICATION API
 //--------------------------------------------------------------------+
 
+// Configure host stack behavior with dynamic or port-specific parameters.
+// Should be called before tuh_init()
+// - cfg_id   : configure ID (TBD)
+// - cfg_param: configure data, structure depends on the ID
+bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
+
 // Init host stack
 bool tuh_init(uint8_t rhport);
 
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 1b2d29331..58b153ac3 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -43,17 +43,25 @@
 #define RHPORT_OFFSET     1
 #define RHPORT_PIO(_x)    ((_x)-RHPORT_OFFSET)
 
-static pio_usb_configuration_t pio_host_config = PIO_USB_DEFAULT_CONFIG;
+static pio_usb_configuration_t pio_host_cfg = PIO_USB_DEFAULT_CONFIG;
 
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param)
+{
+  (void) rhport;
+  TU_VERIFY(cfg_id == TUH_CFGID_RPI_PIO_USB_CONFIGURATION);
+  memcpy(&pio_host_cfg, cfg_param, sizeof(pio_usb_configuration_t));
+  return true;
+}
+
 bool hcd_init(uint8_t rhport)
 {
   (void) rhport;
 
   // To run USB SOF interrupt in core1, call this init in core1
-  pio_usb_host_init(&pio_host_config);
+  pio_usb_host_init(&pio_host_cfg);
 
   return true;
 }

From dd035b0eb2ed6ea7fee892d2a832e09f7c5c633c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Jun 2022 16:08:27 +0700
Subject: [PATCH 1059/2085] make all hcd/dcd function used in isr into ram with
 __no_inline_not_in_flash_func() for faster irq handling

result is 1KB of code moved from rom -> ram
---
 src/common/tusb_types.h                      | 14 +++++++-------
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 12 ++++++------
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 18 ++++++++++++------
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 16 ++++++++--------
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 12 ++++++++----
 5 files changed, 41 insertions(+), 31 deletions(-)

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index e2fa17532..1f2a38d4c 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -492,23 +492,23 @@ TU_ATTR_BIT_FIELD_ORDER_END
 //--------------------------------------------------------------------+
 
 // Get direction from Endpoint address
-static inline tusb_dir_t tu_edpt_dir(uint8_t addr)
+TU_ATTR_ALWAYS_INLINE static inline tusb_dir_t tu_edpt_dir(uint8_t addr)
 {
   return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
 }
 
 // Get Endpoint number from address
-static inline uint8_t tu_edpt_number(uint8_t addr)
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_number(uint8_t addr)
 {
   return (uint8_t)(addr & (~TUSB_DIR_IN_MASK));
 }
 
-static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir)
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir)
 {
   return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0));
 }
 
-static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep)
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep)
 {
   return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0);
 }
@@ -516,18 +516,18 @@ static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep)
 //--------------------------------------------------------------------+
 // Descriptor helper
 //--------------------------------------------------------------------+
-static inline uint8_t const * tu_desc_next(void const* desc)
+TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc)
 {
   uint8_t const* desc8 = (uint8_t const*) desc;
   return desc8 + desc8[DESC_OFFSET_LEN];
 }
 
-static inline uint8_t tu_desc_type(void const* desc)
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc)
 {
   return ((uint8_t const*) desc)[DESC_OFFSET_TYPE];
 }
 
-static inline uint8_t tu_desc_len(void const* desc)
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc)
 {
   return ((uint8_t const*) desc)[DESC_OFFSET_LEN];
 }
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 48793b0d0..3fefc972d 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -55,7 +55,7 @@ static uint8_t *next_buffer_ptr;
 // USB_MAX_ENDPOINTS Endpoints, direction TUSB_DIR_OUT for out and TUSB_DIR_IN for in.
 static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2];
 
-static inline struct hw_endpoint *hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir)
+TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint *hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir)
 {
   return &hw_endpoints[num][dir];
 }
@@ -185,7 +185,7 @@ static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_by
     hw_endpoint_xfer_start(ep, buffer, total_bytes);
 }
 
-static void hw_handle_buff_status(void)
+static void __no_inline_not_in_flash_func(hw_handle_buff_status)(void)
 {
     uint32_t remaining_buffers = usb_hw->buf_status;
     pico_trace("buf_status = 0x%08x\n", remaining_buffers);
@@ -214,7 +214,7 @@ static void hw_handle_buff_status(void)
     }
 }
 
-static void reset_ep0_pid(void)
+TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void)
 {
     // If we have finished this transfer on EP0 set pid back to 1 for next
     // setup transfer. Also clear a stall in case
@@ -226,7 +226,7 @@ static void reset_ep0_pid(void)
     }
 }
 
-static void reset_non_control_endpoints(void)
+static void __no_inline_not_in_flash_func(reset_non_control_endpoints)(void)
 {
   // Disable all non-control
   for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS-1; i++ )
@@ -242,7 +242,7 @@ static void reset_non_control_endpoints(void)
   next_buffer_ptr = &usb_dpram->epx_data[0];
 }
 
-static void dcd_rp2040_irq(void)
+static void __no_inline_not_in_flash_func(dcd_rp2040_irq)(void)
 {
     uint32_t const status = usb_hw->ints;
     uint32_t handled = 0;
@@ -524,7 +524,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
     hw_endpoint_close(ep_addr);
 }
 
-void dcd_int_handler(uint8_t rhport)
+void __no_inline_not_in_flash_func(dcd_int_handler)(uint8_t rhport)
 {
   (void) rhport;
   dcd_rp2040_irq();
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 54c27ffe3..063a8acd0 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -79,7 +79,7 @@ static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
   return NULL;
 }
 
-static inline uint8_t dev_speed(void)
+TU_ATTR_ALWAYS_INLINE static inline uint8_t dev_speed(void)
 {
     return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
 }
@@ -91,7 +91,7 @@ static bool need_pre(uint8_t dev_addr)
     return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
 }
 
-static void hw_xfer_complete(struct hw_endpoint *ep, xfer_result_t xfer_result)
+static void __no_inline_not_in_flash_func(hw_xfer_complete)(struct hw_endpoint *ep, xfer_result_t xfer_result)
 {
     // Mark transfer as done before we tell the tinyusb stack
     uint8_t dev_addr = ep->dev_addr;
@@ -101,7 +101,7 @@ static void hw_xfer_complete(struct hw_endpoint *ep, xfer_result_t xfer_result)
     hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
 }
 
-static void _handle_buff_status_bit(uint bit, struct hw_endpoint *ep)
+static void __no_inline_not_in_flash_func(_handle_buff_status_bit)(uint bit, struct hw_endpoint *ep)
 {
     usb_hw_clear->buf_status = bit;
     bool done = hw_endpoint_xfer_continue(ep);
@@ -111,7 +111,7 @@ static void _handle_buff_status_bit(uint bit, struct hw_endpoint *ep)
     }
 }
 
-static void hw_handle_buff_status(void)
+static void __no_inline_not_in_flash_func(hw_handle_buff_status)(void)
 {
     uint32_t remaining_buffers = usb_hw->buf_status;
     pico_trace("buf_status 0x%08x\n", remaining_buffers);
@@ -159,7 +159,7 @@ static void hw_handle_buff_status(void)
     }
 }
 
-static void hw_trans_complete(void)
+static void __no_inline_not_in_flash_func(hw_trans_complete)(void)
 {
   if (usb_hw->sie_ctrl & USB_SIE_CTRL_SEND_SETUP_BITS)
   {
@@ -175,7 +175,7 @@ static void hw_trans_complete(void)
   }
 }
 
-static void hcd_rp2040_irq(void)
+static void __no_inline_not_in_flash_func(hcd_rp2040_irq)(void)
 {
     uint32_t status = usb_hw->ints;
     uint32_t handled = 0;
@@ -240,6 +240,12 @@ static void hcd_rp2040_irq(void)
     }
 }
 
+void __no_inline_not_in_flash_func(hcd_int_handler)(uint8_t rhport)
+{
+  (void) rhport;
+  hcd_rp2040_irq();
+}
+
 static struct hw_endpoint *_next_free_interrupt_ep(void)
 {
     struct hw_endpoint *ep = NULL;
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index c93199fd0..ebcc76a4b 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -38,7 +38,7 @@ const char *ep_dir_string[] = {
         "in",
 };
 
-static inline void _hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) {
+TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) {
     // todo add critsec as necessary to prevent issues between worker and IRQ...
     //  note that this is perhaps as simple as disabling IRQs because it would make
     //  sense to have worker and IRQ on same core, however I think using critsec is about equivalent.
@@ -69,7 +69,7 @@ void rp2040_usb_init(void)
   usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;
 }
 
-void hw_endpoint_reset_transfer(struct hw_endpoint *ep)
+void __no_inline_not_in_flash_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
 {
   ep->active = false;
   ep->remaining_len = 0;
@@ -77,7 +77,7 @@ void hw_endpoint_reset_transfer(struct hw_endpoint *ep)
   ep->user_buf = 0;
 }
 
-void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
+void __no_inline_not_in_flash_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
     uint32_t value = 0;
     if (and_mask) {
         value = *ep->buffer_control & and_mask;
@@ -108,7 +108,7 @@ void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_m
 }
 
 // prepare buffer, return buffer control
-static uint32_t prepare_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
+static uint32_t __no_inline_not_in_flash_func(prepare_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id)
 {
   uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
   ep->remaining_len = (uint16_t)(ep->remaining_len - buflen);
@@ -143,7 +143,7 @@ static uint32_t prepare_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
 }
 
 // Prepare buffer control register value
-static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
+static void __no_inline_not_in_flash_func(_hw_endpoint_start_next_buffer)(struct hw_endpoint *ep)
 {
   uint32_t ep_ctrl = *ep->endpoint_control;
 
@@ -205,7 +205,7 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
 }
 
 // sync endpoint buffer and return transferred bytes
-static uint16_t sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
+static uint16_t __no_inline_not_in_flash_func(sync_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id)
 {
   uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
   if (buf_id)  buf_ctrl = buf_ctrl >> 16;
@@ -241,7 +241,7 @@ static uint16_t sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
   return xferred_bytes;
 }
 
-static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
+static void __no_inline_not_in_flash_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep)
 {
   // Update hw endpoint struct with info from hardware
   // after a buff status interrupt
@@ -292,7 +292,7 @@ static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
 }
 
 // Returns true if transfer is complete
-bool hw_endpoint_xfer_continue(struct hw_endpoint *ep)
+bool __no_inline_not_in_flash_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
 {
   _hw_endpoint_lock_update(ep, 1);
   // Part way through a transfer
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index da1933ddd..4442e22dc 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -72,16 +72,20 @@ bool hw_endpoint_xfer_continue(struct hw_endpoint *ep);
 void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
 
 void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask);
-static inline uint32_t _hw_endpoint_buffer_control_get_value32(struct hw_endpoint *ep) {
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32(struct hw_endpoint *ep) {
     return *ep->buffer_control;
 }
-static inline void _hw_endpoint_buffer_control_set_value32(struct hw_endpoint *ep, uint32_t value) {
+
+TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32(struct hw_endpoint *ep, uint32_t value) {
     return _hw_endpoint_buffer_control_update32(ep, 0, value);
 }
-static inline void _hw_endpoint_buffer_control_set_mask32(struct hw_endpoint *ep, uint32_t value) {
+
+TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32(struct hw_endpoint *ep, uint32_t value) {
     return _hw_endpoint_buffer_control_update32(ep, ~value, value);
 }
-static inline void _hw_endpoint_buffer_control_clear_mask32(struct hw_endpoint *ep, uint32_t value) {
+
+TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32(struct hw_endpoint *ep, uint32_t value) {
     return _hw_endpoint_buffer_control_update32(ep, ~value, 0);
 }
 

From 8451d05c50928b9aa370414f25a0e991cd4ecef3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Jun 2022 01:45:48 +0700
Subject: [PATCH 1060/2085] revert sof_isr driver rename since it cause issue
 with existing code

also removed commented tud_sof_isr_set() API
---
 src/device/usbd.c     | 40 ++++++++++++++--------------------------
 src/device/usbd.h     |  6 ------
 src/device/usbd_pvt.h |  2 +-
 3 files changed, 15 insertions(+), 33 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 697477584..ec598e49f 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -98,7 +98,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = cdcd_open,
     .control_xfer_cb  = cdcd_control_xfer_cb,
     .xfer_cb          = cdcd_xfer_cb,
-    .sof_isr          = NULL
+    .sof              = NULL
   },
   #endif
 
@@ -110,7 +110,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = mscd_open,
     .control_xfer_cb  = mscd_control_xfer_cb,
     .xfer_cb          = mscd_xfer_cb,
-    .sof_isr          = NULL
+    .sof              = NULL
   },
   #endif
 
@@ -122,7 +122,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = hidd_open,
     .control_xfer_cb  = hidd_control_xfer_cb,
     .xfer_cb          = hidd_xfer_cb,
-    .sof_isr          = NULL
+    .sof              = NULL
   },
   #endif
 
@@ -134,7 +134,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = audiod_open,
     .control_xfer_cb  = audiod_control_xfer_cb,
     .xfer_cb          = audiod_xfer_cb,
-    .sof_isr          = audiod_sof_isr
+    .sof              = audiod_sof_isr
   },
   #endif
 
@@ -146,7 +146,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = videod_open,
     .control_xfer_cb  = videod_control_xfer_cb,
     .xfer_cb          = videod_xfer_cb,
-    .sof_isr          = NULL
+    .sof              = NULL
   },
   #endif
 
@@ -158,7 +158,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .reset            = midid_reset,
     .control_xfer_cb  = midid_control_xfer_cb,
     .xfer_cb          = midid_xfer_cb,
-    .sof_isr          = NULL
+    .sof              = NULL
   },
   #endif
 
@@ -170,7 +170,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = vendord_open,
     .control_xfer_cb  = tud_vendor_control_xfer_cb,
     .xfer_cb          = vendord_xfer_cb,
-    .sof_isr          = NULL
+    .sof              = NULL
   },
   #endif
 
@@ -182,7 +182,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = usbtmcd_open_cb,
     .control_xfer_cb  = usbtmcd_control_xfer_cb,
     .xfer_cb          = usbtmcd_xfer_cb,
-    .sof_isr          = NULL
+    .sof              = NULL
   },
   #endif
 
@@ -194,7 +194,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = dfu_rtd_open,
     .control_xfer_cb  = dfu_rtd_control_xfer_cb,
     .xfer_cb          = NULL,
-    .sof_isr          = NULL
+    .sof              = NULL
   },
   #endif
 
@@ -206,7 +206,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = dfu_moded_open,
     .control_xfer_cb  = dfu_moded_control_xfer_cb,
     .xfer_cb          = NULL,
-    .sof_isr          = NULL
+    .sof              = NULL
   },
   #endif
 
@@ -218,7 +218,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = netd_open,
     .control_xfer_cb  = netd_control_xfer_cb,
     .xfer_cb          = netd_xfer_cb,
-    .sof_isr              = NULL,
+    .sof                  = NULL,
   },
   #endif
 
@@ -230,7 +230,7 @@ static usbd_class_driver_t const _usbd_driver[] =
     .open             = btd_open,
     .control_xfer_cb  = btd_control_xfer_cb,
     .xfer_cb          = btd_xfer_cb,
-    .sof_isr          = NULL
+    .sof              = NULL
   },
   #endif
 };
@@ -264,8 +264,6 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 // DCD Event
 //--------------------------------------------------------------------+
 
-//static tud_sof_isr_t _sof_isr = NULL;
-
 enum { RHPORT_INVALID = 0xFFu };
 static uint8_t _usbd_rhport = RHPORT_INVALID;
 
@@ -373,12 +371,6 @@ bool tud_connect(void)
   return true;
 }
 
-//void tud_sof_isr_set(tud_sof_isr_t sof_isr)
-//{
-//  _sof_isr = sof_isr;
-//  dcd_sof_enable(_usbd_rhport, _sof_isr != NULL);
-//}
-
 //--------------------------------------------------------------------+
 // USBD Task
 //--------------------------------------------------------------------+
@@ -422,7 +414,6 @@ bool tud_init (uint8_t rhport)
   }
 
   _usbd_rhport = rhport;
-  //_sof_isr = NULL;
 
   // Init device controller driver
   dcd_init(rhport);
@@ -1110,15 +1101,12 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr)
       for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
       {
         usbd_class_driver_t const * driver = get_driver(i);
-        if (driver->sof_isr)
+        if (driver->sof)
         {
-          driver->sof_isr(event->rhport, event->sof.frame_count);
+          driver->sof(event->rhport, event->sof.frame_count);
         }
       }
 
-      // SOF user handler in ISR context
-      // if (_sof_isr) _sof_isr(event->sof.frame_count);
-
       // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup
       // which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational
       if ( _usbd_dev.suspended )
diff --git a/src/device/usbd.h b/src/device/usbd.h
index f1312f6ec..964cfb992 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -33,8 +33,6 @@
 extern "C" {
 #endif
 
-// typedef void (*tud_sof_isr_t) (uint32_t frame_count);
-
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+
@@ -95,10 +93,6 @@ bool tud_disconnect(void);
 // Return false on unsupported MCUs
 bool tud_connect(void);
 
-// Set Start-of-frame (1ms interval) IRQ handler
-// NULL means disabled, frame_count may not be supported on mcus
-// void tud_sof_isr_set(tud_sof_isr_t sof_isr);
-
 // Carry out Data and Status stage of control transfer
 // - If len = 0, it is equivalent to sending status only
 // - If len > wLength : it will be truncated
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 17ebbfcd4..6fad46db3 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -48,7 +48,7 @@ typedef struct
   uint16_t (* open             ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len);
   bool     (* control_xfer_cb  ) (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
   bool     (* xfer_cb          ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
-  void     (* sof_isr          ) (uint8_t rhport, uint32_t frame_count); // optional
+  void     (* sof              ) (uint8_t rhport, uint32_t frame_count); // optional
 } usbd_class_driver_t;
 
 // Invoked when initializing device stack to get additional class drivers.

From 040ef0640df837a49e7f46c12fa7b00fe6a77bf6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Jun 2022 14:53:03 +0700
Subject: [PATCH 1061/2085] more dynamic controller for host

---
 src/device/usbd.c |  2 +-
 src/host/usbh.c   | 36 ++++++++++++++++++++----------------
 src/host/usbh.h   |  4 ++--
 src/tusb_option.h |  7 ++++---
 4 files changed, 27 insertions(+), 22 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index ec598e49f..1806281ff 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -384,7 +384,7 @@ bool tud_init (uint8_t rhport)
   // skip if already initialized
   if ( tud_inited() ) return true;
 
-  TU_LOG2("USBD init rhport %u\r\n", rhport);
+  TU_LOG2("USBD init on controller %u\r\n", rhport);
   TU_LOG2_INT(sizeof(usbd_device_t));
 
   tu_varclr(&_usbd_dev);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index ab2d8770a..a600f7095 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -125,6 +125,7 @@ typedef struct {
 // Invalid driver ID in itf2drv[] ep2drv[][] mapping
 enum { DRVID_INVALID = 0xFFu };
 enum { ADDR_INVALID  = 0xFFu };
+enum { CONTROLLER_INVALID = 0xFFu };
 
 #if CFG_TUSB_DEBUG >= 2
   #define DRIVER_NAME(_name)    .name = _name,
@@ -203,7 +204,7 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1
 // sum of end device + hub
 #define TOTAL_DEVICES   (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB)
 
-static bool _usbh_initialized = false;
+static uint8_t _usbh_controller = CONTROLLER_INVALID;
 
 // Device with address = 0 for enumeration
 static usbh_dev0_t _dev0;
@@ -280,8 +281,8 @@ void osal_task_delay(uint32_t msec)
 {
   (void) msec;
 
-  const uint32_t start = hcd_frame_number(TUH_OPT_RHPORT);
-  while ( ( hcd_frame_number(TUH_OPT_RHPORT) - start ) < msec ) {}
+  const uint32_t start = hcd_frame_number(_usbh_controller);
+  while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}
 }
 #endif
 
@@ -335,15 +336,15 @@ static void clear_device(usbh_device_t* dev)
 
 bool tuh_inited(void)
 {
-  return _usbh_initialized;
+  return _usbh_controller != CONTROLLER_INVALID;
 }
 
-bool tuh_init(uint8_t rhport)
+bool tuh_init(uint8_t controller_id)
 {
   // skip if already initialized
-  if (_usbh_initialized) return _usbh_initialized;
+  if ( tuh_inited() ) return true;
 
-  TU_LOG2("USBH init rhport %u\r\n", rhport);
+  TU_LOG2("USBH init on controller %u\r\n", controller_id);
   TU_LOG2_INT(sizeof(usbh_device_t));
   TU_LOG2_INT(sizeof(hcd_event_t));
   TU_LOG2_INT(sizeof(_ctrl_xfer));
@@ -376,10 +377,11 @@ bool tuh_init(uint8_t rhport)
     usbh_class_drivers[drv_id].init();
   }
 
-  TU_ASSERT(hcd_init(rhport));
-  hcd_int_enable(rhport);
+  _usbh_controller = controller_id;;
+
+  TU_ASSERT(hcd_init(controller_id));
+  hcd_int_enable(controller_id);
 
-  _usbh_initialized = true;
   return true;
 }
 
@@ -721,13 +723,13 @@ uint8_t* usbh_get_enum_buf(void)
 
 void usbh_int_set(bool enabled)
 {
-  // TODO all host controller
+  // TODO all host controller if multiple is used
   if (enabled)
   {
-    hcd_int_enable(TUH_OPT_RHPORT);
+    hcd_int_enable(_usbh_controller);
   }else
   {
-    hcd_int_disable(TUH_OPT_RHPORT);
+    hcd_int_disable(_usbh_controller);
   }
 }
 
@@ -1238,14 +1240,15 @@ static void process_enumeration(tuh_xfer_t* xfer)
 
 #if 0
     case ENUM_RESET_2:
-      // XXX note used by now, but may be needed for some devices !?
+      // TODO not used by now, but may be needed for some devices !?
       // Reset device again before Set Address
       TU_LOG2("Port reset2 \r\n");
       if (_dev0.hub_addr == 0)
       {
         // connected directly to roothub
         hcd_port_reset( _dev0.rhport );
-        osal_task_delay(RESET_DELAY);
+        osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
+                                      // sof of controller may not running while reseting
         hcd_port_reset_end(_dev0.rhport);
         // TODO: fall through to SET ADDRESS, refactor later
       }
@@ -1364,7 +1367,8 @@ static bool enum_new_device(hcd_event_t* event)
     // connected/disconnected directly with roothub
     // wait until device is stable TODO non blocking
     hcd_port_reset(_dev0.rhport);
-    osal_task_delay(RESET_DELAY);
+    osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
+                                  // sof of controller may not running while reseting
     hcd_port_reset_end( _dev0.rhport);
 
     // device unplugged while delaying
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 4c65da206..347c75b8c 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -95,10 +95,10 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
 // Should be called before tuh_init()
 // - cfg_id   : configure ID (TBD)
 // - cfg_param: configure data, structure depends on the ID
-bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
+bool tuh_configure(uint8_t controller_id, uint32_t cfg_id, const void* cfg_param);
 
 // Init host stack
-bool tuh_init(uint8_t rhport);
+bool tuh_init(uint8_t controller_id);
 
 // Check if host stack is already initialized
 bool tuh_inited(void);
diff --git a/src/tusb_option.h b/src/tusb_option.h
index e332c5728..206d23e72 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -28,7 +28,7 @@
 #define _TUSB_OPTION_H_
 
 // To avoid GCC compiler warnings when -pedantic option is used (strict ISO C)
-typedef int make_iso_compilers_happy ;
+typedef int make_iso_compilers_happy;
 
 #include "common/tusb_compiler.h"
 
@@ -217,6 +217,9 @@ typedef int make_iso_compilers_happy ;
   #define CFG_TUD_MAX_SPEED   (TUD_RHPORT_MODE & OPT_MODE_SPEED_MASK)
 #endif
 
+// For backward compatible
+#define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED
+
 // highspeed support indicator
 #define TUD_OPT_HIGH_SPEED    (CFG_TUD_MAX_SPEED ? CFG_TUD_MAX_SPEED : TUP_RHPORT_HIGHSPEED)
 
@@ -230,7 +233,6 @@ typedef int make_iso_compilers_happy ;
   #define TUH_OPT_RHPORT   1
 #else
   #define TUH_RHPORT_MODE   OPT_MODE_NONE
-  #define TUH_OPT_RHPORT   -1
 #endif
 
 #ifndef CFG_TUH_ENABLED
@@ -244,7 +246,6 @@ typedef int make_iso_compilers_happy ;
 #endif
 
 // For backward compatible
-#define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED
 #define TUSB_OPT_HOST_ENABLED   CFG_TUH_ENABLED
 
 //--------------------------------------------------------------------+

From 19d054f7892beda36c7f6fe5f07d84a13db7df16 Mon Sep 17 00:00:00 2001
From: Liam Fraser <liam@raspberrypi.com>
Date: Thu, 13 Jan 2022 11:17:08 +0000
Subject: [PATCH 1062/2085] hcd_rp2040 improvements:  - Stall now has priority
 over other interrupt responses  - Delete eunused hcd_edpt_busy  - Assert
 !ep->active when trying to start a new xfer  - Assert !ep->active when
 handling buff_status bits  - Set ep->xferred_len to 8 once a setup packet is
 finished so the data structure is accurate

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 46 ++++++++++----------
 1 file changed, 22 insertions(+), 24 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 063a8acd0..dddb9cd90 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -104,6 +104,8 @@ static void __no_inline_not_in_flash_func(hw_xfer_complete)(struct hw_endpoint *
 static void __no_inline_not_in_flash_func(_handle_buff_status_bit)(uint bit, struct hw_endpoint *ep)
 {
     usb_hw_clear->buf_status = bit;
+    // EP may have been stalled?
+    assert(ep->active);
     bool done = hw_endpoint_xfer_continue(ep);
     if (done)
     {
@@ -166,6 +168,8 @@ static void __no_inline_not_in_flash_func(hw_trans_complete)(void)
     pico_trace("Sent setup packet\n");
     struct hw_endpoint *ep = &epx;
     assert(ep->active);
+    // Set transferred length to 8 for a setup packet
+    ep->xferred_len = 8;
     hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
   }
   else
@@ -197,6 +201,18 @@ static void __no_inline_not_in_flash_func(hcd_rp2040_irq)(void)
         usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS;
     }
 
+    if (status & USB_INTS_STALL_BITS)
+    {
+        // We have rx'd a stall from the device
+        // NOTE THIS SHOULD HAVE PRIORITY OVER BUFF_STATUS
+        // AND TRANS_COMPLETE as the stall is an alternative response
+        // to one of those events
+        pico_trace("Stall REC\n");
+        handled |= USB_INTS_STALL_BITS;
+        usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS;
+        hw_xfer_complete(&epx, XFER_RESULT_STALLED);
+    }
+
     if (status & USB_INTS_BUFF_STATUS_BITS)
     {
         handled |= USB_INTS_BUFF_STATUS_BITS;
@@ -212,15 +228,6 @@ static void __no_inline_not_in_flash_func(hcd_rp2040_irq)(void)
         hw_trans_complete();
     }
 
-    if (status & USB_INTS_STALL_BITS)
-    {
-        // We have rx'd a stall from the device
-        pico_trace("Stall REC\n");
-        handled |= USB_INTS_STALL_BITS;
-        usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS;
-        hw_xfer_complete(&epx, XFER_RESULT_STALLED);
-    }
-
     if (status & USB_INTS_ERROR_RX_TIMEOUT_BITS)
     {
         handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS;
@@ -505,6 +512,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
     assert(ep);
 
+    // EP should be inactive
+    assert(!ep->active);
+
     // Control endpoint can change direction 0x00 <-> 0x80
     if ( ep_addr != ep->ep_addr )
     {
@@ -552,6 +562,9 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
     // Configure EP0 struct with setup info for the trans complete
     struct hw_endpoint *ep = _hw_endpoint_allocate(0);
 
+    // EPX should be inactive
+    assert(!ep->active);
+
     // EP0 out
     _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
     assert(ep->configured);
@@ -571,21 +584,6 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
     return true;
 }
 
-
-//bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
-//{
-//    // EPX is shared, so multiple device addresses and endpoint addresses share that
-//    // so if any transfer is active on epx, we are busy. Interrupt endpoints have their own
-//    // EPX so ep->active will only be busy if there is a pending transfer on that interrupt endpoint
-//    // on that device
-//    pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\n", dev_addr, ep_addr);
-//    struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
-//    assert(ep);
-//    bool busy = ep->active;
-//    pico_trace("busy == %d\n", busy);
-//    return busy;
-//}
-
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
     (void) dev_addr;

From f4a7b5b80c86777b62842e19f9bd6236161f2e8d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 16 Jun 2022 14:37:57 +0700
Subject: [PATCH 1063/2085] add note for recursive calls of
 process_device_unplugged() in case of hub

---
 examples/host/cdc_msc_hid/src/tusb_config.h |  2 +-
 src/host/usbh.c                             | 37 +++++++++++----------
 2 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index e9e68cf5a..c469ec813 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -81,7 +81,7 @@
 // Size of buffer to hold descriptors and other data used for enumeration
 #define CFG_TUH_ENUMERATION_BUFSIZE 256
 
-#define CFG_TUH_HUB                 1
+#define CFG_TUH_HUB                 1 // number of supported hubs
 #define CFG_TUH_CDC                 1
 #define CFG_TUH_HID                 4 // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 908230c83..04d969ce6 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1089,6 +1089,12 @@ uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_i
 //
 //--------------------------------------------------------------------+
 
+TU_ATTR_ALWAYS_INLINE
+static inline bool is_hub_addr(uint8_t daddr)
+{
+  return (CFG_TUH_HUB > 0) && (daddr > CFG_TUH_DEVICE_MAX);
+}
+
 // a device unplugged from rhport:hub_addr:hub_port
 static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
 {
@@ -1101,21 +1107,24 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
 
     // TODO Hub multiple level
     if (dev->rhport == rhport   &&
-        (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr == 0 & hub_port == 0 means roothub
-        (hub_port == 0 || dev->hub_port == hub_port) &&
+        (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr = 0 means roothub
+        (hub_port == 0 || dev->hub_port == hub_port) && // hub_port = 0 means all devices of downstream hub
         dev->connected)
     {
       TU_LOG2("  Address = %u\r\n", dev_addr);
 
-      // If the device itself is a usb hub, unplug downstream devices.
-      if (dev_addr > CFG_TUH_DEVICE_MAX)
+      if (is_hub_addr(dev_addr))
       {
+        TU_LOG(USBH_DBG_LVL, "HUB address = %u is unmounted\r\n", dev_addr);
+        // If the device itself is a usb hub, unplug downstream devices.
+        // FIXME un-roll recursive calls to prevent potential stack overflow
         process_device_unplugged(rhport, dev_addr, 0);
+      }else
+      {
+        // Invoke callback before closing driver
+        if (tuh_umount_cb) tuh_umount_cb(dev_addr);
       }
 
-      // Invoke callback before close driver
-      if (tuh_umount_cb) tuh_umount_cb(dev_addr);
-
       // Close class driver
       for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
       {
@@ -1395,12 +1404,6 @@ static bool enum_new_device(hcd_event_t* event)
   return true;
 }
 
-TU_ATTR_ALWAYS_INLINE
-static inline bool is_hub_addr(uint8_t daddr)
-{
-  return daddr > CFG_TUH_DEVICE_MAX;
-}
-
 static uint8_t get_new_address(bool is_hub)
 {
   uint8_t start;
@@ -1577,10 +1580,10 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
   {
     enum_full_complete();
 
-#if CFG_TUH_HUB
-    // skip device mount callback for hub
-    if ( !is_hub_addr(dev_addr) )
-#endif
+    if (is_hub_addr(dev_addr))
+    {
+      TU_LOG(USBH_DBG_LVL, "HUB address = %u is mounted\r\n", dev_addr);
+    }else
     {
       // Invoke callback if available
       if (tuh_mount_cb) tuh_mount_cb(dev_addr);

From 2036a0b62a709168d80d2b314e580ee1d1eda0bf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 16 Jun 2022 14:41:10 +0700
Subject: [PATCH 1064/2085] update readme

---
 README.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index 5b994c357..1a96f6e16 100644
--- a/README.rst
+++ b/README.rst
@@ -82,7 +82,7 @@ Host Stack
 
 - Human Interface Device (HID): Keyboard, Mouse, Generic
 - Mass Storage Class (MSC)
-- Hub currently only supports 1 level of hub (due to my laziness)
+- Hub with multiple-level support
 
 OS Abstraction layer
 ====================

From c5ba4af25babbf7fc6ee97d0f6ec06079e5f1b0f Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Thu, 16 Jun 2022 11:03:53 -0500
Subject: [PATCH 1065/2085] rp2040: make moving 1K of code into RAM optional -
 and off by default

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c |  8 ++++----
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 12 ++++++------
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 14 +++++++-------
 src/portable/raspberrypi/rp2040/rp2040_usb.h |  9 +++++++++
 4 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 3fefc972d..4c8084878 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -185,7 +185,7 @@ static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_by
     hw_endpoint_xfer_start(ep, buffer, total_bytes);
 }
 
-static void __no_inline_not_in_flash_func(hw_handle_buff_status)(void)
+static void __tusb_irq_path_func(hw_handle_buff_status)(void)
 {
     uint32_t remaining_buffers = usb_hw->buf_status;
     pico_trace("buf_status = 0x%08x\n", remaining_buffers);
@@ -226,7 +226,7 @@ TU_ATTR_ALWAYS_INLINE static inline void reset_ep0_pid(void)
     }
 }
 
-static void __no_inline_not_in_flash_func(reset_non_control_endpoints)(void)
+static void __tusb_irq_path_func(reset_non_control_endpoints)(void)
 {
   // Disable all non-control
   for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS-1; i++ )
@@ -242,7 +242,7 @@ static void __no_inline_not_in_flash_func(reset_non_control_endpoints)(void)
   next_buffer_ptr = &usb_dpram->epx_data[0];
 }
 
-static void __no_inline_not_in_flash_func(dcd_rp2040_irq)(void)
+static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
 {
     uint32_t const status = usb_hw->ints;
     uint32_t handled = 0;
@@ -524,7 +524,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
     hw_endpoint_close(ep_addr);
 }
 
-void __no_inline_not_in_flash_func(dcd_int_handler)(uint8_t rhport)
+void __tusb_irq_path_func(dcd_int_handler)(uint8_t rhport)
 {
   (void) rhport;
   dcd_rp2040_irq();
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 063a8acd0..346326cd0 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -91,7 +91,7 @@ static bool need_pre(uint8_t dev_addr)
     return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
 }
 
-static void __no_inline_not_in_flash_func(hw_xfer_complete)(struct hw_endpoint *ep, xfer_result_t xfer_result)
+static void __tusb_irq_path_func(hw_xfer_complete)(struct hw_endpoint *ep, xfer_result_t xfer_result)
 {
     // Mark transfer as done before we tell the tinyusb stack
     uint8_t dev_addr = ep->dev_addr;
@@ -101,7 +101,7 @@ static void __no_inline_not_in_flash_func(hw_xfer_complete)(struct hw_endpoint *
     hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
 }
 
-static void __no_inline_not_in_flash_func(_handle_buff_status_bit)(uint bit, struct hw_endpoint *ep)
+static void __tusb_irq_path_func(_handle_buff_status_bit)(uint bit, struct hw_endpoint *ep)
 {
     usb_hw_clear->buf_status = bit;
     bool done = hw_endpoint_xfer_continue(ep);
@@ -111,7 +111,7 @@ static void __no_inline_not_in_flash_func(_handle_buff_status_bit)(uint bit, str
     }
 }
 
-static void __no_inline_not_in_flash_func(hw_handle_buff_status)(void)
+static void __tusb_irq_path_func(hw_handle_buff_status)(void)
 {
     uint32_t remaining_buffers = usb_hw->buf_status;
     pico_trace("buf_status 0x%08x\n", remaining_buffers);
@@ -159,7 +159,7 @@ static void __no_inline_not_in_flash_func(hw_handle_buff_status)(void)
     }
 }
 
-static void __no_inline_not_in_flash_func(hw_trans_complete)(void)
+static void __tusb_irq_path_func(hw_trans_complete)(void)
 {
   if (usb_hw->sie_ctrl & USB_SIE_CTRL_SEND_SETUP_BITS)
   {
@@ -175,7 +175,7 @@ static void __no_inline_not_in_flash_func(hw_trans_complete)(void)
   }
 }
 
-static void __no_inline_not_in_flash_func(hcd_rp2040_irq)(void)
+static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
 {
     uint32_t status = usb_hw->ints;
     uint32_t handled = 0;
@@ -240,7 +240,7 @@ static void __no_inline_not_in_flash_func(hcd_rp2040_irq)(void)
     }
 }
 
-void __no_inline_not_in_flash_func(hcd_int_handler)(uint8_t rhport)
+void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport)
 {
   (void) rhport;
   hcd_rp2040_irq();
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index ebcc76a4b..f93568f0c 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -69,7 +69,7 @@ void rp2040_usb_init(void)
   usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;
 }
 
-void __no_inline_not_in_flash_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
+void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
 {
   ep->active = false;
   ep->remaining_len = 0;
@@ -77,7 +77,7 @@ void __no_inline_not_in_flash_func(hw_endpoint_reset_transfer)(struct hw_endpoin
   ep->user_buf = 0;
 }
 
-void __no_inline_not_in_flash_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
+void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
     uint32_t value = 0;
     if (and_mask) {
         value = *ep->buffer_control & and_mask;
@@ -108,7 +108,7 @@ void __no_inline_not_in_flash_func(_hw_endpoint_buffer_control_update32)(struct
 }
 
 // prepare buffer, return buffer control
-static uint32_t __no_inline_not_in_flash_func(prepare_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id)
+static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id)
 {
   uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
   ep->remaining_len = (uint16_t)(ep->remaining_len - buflen);
@@ -143,7 +143,7 @@ static uint32_t __no_inline_not_in_flash_func(prepare_ep_buffer)(struct hw_endpo
 }
 
 // Prepare buffer control register value
-static void __no_inline_not_in_flash_func(_hw_endpoint_start_next_buffer)(struct hw_endpoint *ep)
+static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpoint *ep)
 {
   uint32_t ep_ctrl = *ep->endpoint_control;
 
@@ -205,7 +205,7 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
 }
 
 // sync endpoint buffer and return transferred bytes
-static uint16_t __no_inline_not_in_flash_func(sync_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id)
+static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint *ep, uint8_t buf_id)
 {
   uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
   if (buf_id)  buf_ctrl = buf_ctrl >> 16;
@@ -241,7 +241,7 @@ static uint16_t __no_inline_not_in_flash_func(sync_ep_buffer)(struct hw_endpoint
   return xferred_bytes;
 }
 
-static void __no_inline_not_in_flash_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep)
+static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep)
 {
   // Update hw endpoint struct with info from hardware
   // after a buff status interrupt
@@ -292,7 +292,7 @@ static void __no_inline_not_in_flash_func(_hw_endpoint_xfer_sync) (struct hw_end
 }
 
 // Returns true if transfer is complete
-bool __no_inline_not_in_flash_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
+bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
 {
   _hw_endpoint_lock_update(ep, 1);
   // Part way through a transfer
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 4442e22dc..c72dae64c 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -16,6 +16,15 @@
 #define TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX PICO_RP2040_USB_DEVICE_ENUMERATION_FIX
 #endif
 
+#ifndef PICO_RP2040_USB_FAST_IRQ
+#define PICO_RP2040_USB_FAST_IRQ 0
+#endif
+
+#if PICO_RP2040_USB_FAST_IRQ
+#define __tusb_irq_path_func(x) __no_inline_not_in_flash_func(x)
+#else
+#define __tusb_irq_path_func(x) x
+#endif
 
 #define pico_info(...)  TU_LOG(2, __VA_ARGS__)
 #define pico_trace(...) TU_LOG(3, __VA_ARGS__)

From e9089b993f32a5437614008ec14458ad577cc28f Mon Sep 17 00:00:00 2001
From: Maddy <maddy.aby.11@gmail.com>
Date: Thu, 16 Jun 2022 16:22:55 -0700
Subject: [PATCH 1066/2085] Fix typo in audiod_rx_done_cb in audio_device.c

---
 src/class/audio/audio_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index dbd8ab54b..1e534b6a4 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -562,7 +562,7 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
 
     case AUDIO_FORMAT_TYPE_I:
 
-      switch (audio->format_type_I_tx)
+      switch (audio->format_type_I_rx)
       {
         case AUDIO_DATA_FORMAT_TYPE_I_PCM:
           TU_VERIFY(audiod_decode_type_I_pcm(rhport, audio, n_bytes_received));

From 05fc2fa7a64c32aa748c8c0f1fe119f417fed074 Mon Sep 17 00:00:00 2001
From: maddyaby <32046405+maddyaby@users.noreply.github.com>
Date: Thu, 16 Jun 2022 16:57:20 -0700
Subject: [PATCH 1067/2085] Stub out dcd_edpt_close for samd

Not having this prevents the device from finishing the mounting process.

Tested on a SAMD51 and didn't seem to need to actually do anything in the close function.
---
 src/portable/microchip/samd/dcd_samd.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index 5ae5a554b..20dbde0f4 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -250,6 +250,13 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   return true;
 }
 
+void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) {
+  (void) rhport;
+  (void) ep_addr;
+
+  // TODO: implement if necessary?
+}
+
 void dcd_edpt_close_all (uint8_t rhport)
 {
   (void) rhport;

From 905a0b24576deab6a2b4214b1428c87e4cd703a5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Jun 2022 14:37:35 +0700
Subject: [PATCH 1068/2085] correct bulk size for highspeed endpoint in
 dynamic_configuration and usbtmc exmaples

---
 examples/device/dynamic_configuration/src/usb_descriptors.c | 2 +-
 src/class/usbtmc/usbtmc_device.h                            | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index 3352972a5..b88f20163 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -163,7 +163,7 @@ uint8_t const desc_configuration_0[] =
   TUD_CONFIG_DESCRIPTOR(1, ITF_0_NUM_TOTAL, 0, CONFIG_0_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_0_NUM_CDC, 0, EPNUM_0_CDC_NOTIF, 8, EPNUM_0_CDC_OUT, EPNUM_0_CDC_IN, 64),
+  TUD_CDC_DESCRIPTOR(ITF_0_NUM_CDC, 0, EPNUM_0_CDC_NOTIF, 8, EPNUM_0_CDC_OUT, EPNUM_0_CDC_IN, TUD_OPT_HIGH_SPEED ? 512 : 64),
 
   // Interface number, string index, EP Out & EP In address, EP size
   TUD_MIDI_DESCRIPTOR(ITF_0_NUM_MIDI, 0, EPNUM_0_MIDI_OUT, EPNUM_0_MIDI_IN, TUD_OPT_HIGH_SPEED ? 512 : 64),
diff --git a/src/class/usbtmc/usbtmc_device.h b/src/class/usbtmc/usbtmc_device.h
index 0549a1569..5dc4d2dff 100644
--- a/src/class/usbtmc/usbtmc_device.h
+++ b/src/class/usbtmc/usbtmc_device.h
@@ -37,7 +37,7 @@
 
 // USB spec says that full-speed must be 8,16,32, or 64.
 // However, this driver implementation requires it to be >=32
-#define USBTMCD_MAX_PACKET_SIZE (64u)
+#define USBTMCD_MAX_PACKET_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 /***********************************************
  *  Functions to be implemeted by the class implementation

From 1001d2da401bc9abb98207d8f4be239ac62d5c33 Mon Sep 17 00:00:00 2001
From: mingpepe <mingpepemath@gmail.com>
Date: Fri, 17 Jun 2022 16:50:24 +0800
Subject: [PATCH 1069/2085] Fix typo for log format

---
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index f93568f0c..49be90167 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -174,7 +174,7 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo
 
   *ep->endpoint_control = ep_ctrl;
 
-  TU_LOG(3, "  Prepare BufCtrl: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
+  TU_LOG(3, "  Prepare BufCtrl: [0] = 0x%04x  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
 
   // Finally, write to buffer_control which will trigger the transfer
   // the next time the controller polls this dpram address
@@ -247,7 +247,7 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep
   // after a buff status interrupt
 
   uint32_t __unused buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
-  TU_LOG(3, "  Sync BufCtrl: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
+  TU_LOG(3, "  Sync BufCtrl: [0] = 0x%04x  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
 
   // always sync buffer 0
   uint16_t buf0_bytes = sync_ep_buffer(ep, 0);
@@ -285,7 +285,7 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep
       usb_hw->abort &= ~TU_BIT(ep_id);
 
       TU_LOG(3, "----SHORT PACKET buffer0 on EP %02X:\r\n", ep->ep_addr);
-      TU_LOG(3, "  BufCtrl: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
+      TU_LOG(3, "  BufCtrl: [0] = 0x%04x  [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
 #endif
     }
   }

From c45118dacf176b232e22c49ed68acf8c95a1dfc6 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Fri, 17 Jun 2022 09:13:40 -0500
Subject: [PATCH 1070/2085] rp2040: use shared IRQ handlers, so user can also
 hook the USB IRQ

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 2 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 4c8084878..c6018c515 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -363,7 +363,7 @@ void dcd_init (uint8_t rhport)
   usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
 #endif
 
-  irq_set_exclusive_handler(USBCTRL_IRQ, dcd_rp2040_irq);
+  irq_add_shared_handler(USBCTRL_IRQ, dcd_rp2040_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY);
 
   // Init control endpoints
   tu_memclr(hw_endpoints[0], 2*sizeof(hw_endpoint_t));
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 346326cd0..67d2de254 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -369,7 +369,7 @@ bool hcd_init(uint8_t rhport)
     // Force VBUS detect to always present, for now we assume vbus is always provided (without using VBUS En)
     usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
 
-    irq_set_exclusive_handler(USBCTRL_IRQ, hcd_rp2040_irq);
+    irq_add_shared_handler(USBCTRL_IRQ, hcd_rp2040_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY);
 
     // clear epx and interrupt eps
     memset(&ep_pool, 0, sizeof(ep_pool));

From 2f7f3e604eb2641dd87a524ab282939bda6b3348 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Fri, 17 Jun 2022 12:54:28 -0500
Subject: [PATCH 1071/2085] Re-add some warning suppression for rp2040

---
 hw/bsp/rp2040/family.cmake | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index df3a6a91e..ed7041e4e 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -232,6 +232,25 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 
 	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
 	function(suppress_tinyusb_warnings)
-		# there are currently no warnings to suppress, however this function must still exist
+		set_source_files_properties(
+					${PICO_TINYUSB_PATH}/src/device/usbd.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-conversion")
+		set_source_files_properties(
+					${PICO_TINYUSB_PATH}/src/device/usbd_control.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-conversion")
+		set_source_files_properties(
+					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-conversion")
+		set_source_files_properties(
+					${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-conversion")
+		set_source_files_properties(
+					${PICO_TINYUSB_PATH}/src/tusb.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-conversion")
 	endfunction()
 endif()

From 2cc2a90215f94692f18e0a402470c58366bfca47 Mon Sep 17 00:00:00 2001
From: maddyaby <32046405+maddyaby@users.noreply.github.com>
Date: Fri, 17 Jun 2022 16:07:32 -0700
Subject: [PATCH 1072/2085] Allow more endpoint packet sizes for SAMD

Tested on SAMD51 - we can allow more packet sizes by checking that the set size value is greater than the requested packet size instead of exactly the same.
---
 src/portable/microchip/samd/dcd_samd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index 5ae5a554b..2f40c8247 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -222,14 +222,14 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
   UsbDeviceDescBank* bank = &sram_registers[epnum][dir];
   uint32_t size_value = 0;
   while (size_value < 7) {
-    if (1 << (size_value + 3) == tu_edpt_packet_size(desc_edpt)) {
+    if (1 << (size_value + 3) >= tu_edpt_packet_size(desc_edpt)) {
       break;
     }
     size_value++;
   }
 
   // unsupported endpoint size
-  if ( size_value == 7 && tu_edpt_packet_size(desc_edpt) != 1023 ) return false;
+  if ( size_value == 7 && tu_edpt_packet_size(desc_edpt) > 1023 ) return false;
 
   bank->PCKSIZE.bit.SIZE = size_value;
 

From 742b99f6894ae2b4643c96790e51726e4ba9dc58 Mon Sep 17 00:00:00 2001
From: caleb crome <caleb@crome.org>
Date: Tue, 21 Jun 2022 11:12:39 -0700
Subject: [PATCH 1073/2085] Added The Teensy 4.1 board

The Teensy 4.1 board has an 8MB W25Q64JV as opposed to the 2MB flash
on the Teensy 4.0.  This largely doensn't matter for TinyUsb, except
when you attempt to access any memory in the flash above the 2MB
boundary, when it fails with a hard fault.
---
 hw/bsp/imxrt/boards/teensy_41/board.h         |  52 ++++
 hw/bsp/imxrt/boards/teensy_41/board.mk        |  10 +
 .../teensy_41/teensy41_flexspi_nor_config.c   |  49 ++++
 .../teensy_41/teensy41_flexspi_nor_config.h   | 268 ++++++++++++++++++
 4 files changed, 379 insertions(+)
 create mode 100644 hw/bsp/imxrt/boards/teensy_41/board.h
 create mode 100644 hw/bsp/imxrt/boards/teensy_41/board.mk
 create mode 100644 hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
 create mode 100644 hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h

diff --git a/hw/bsp/imxrt/boards/teensy_41/board.h b/hw/bsp/imxrt/boards/teensy_41/board.h
new file mode 100644
index 000000000..b0b4931c7
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board.h
@@ -0,0 +1,52 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+
+// required since iMX RT10xx SDK include this file for board size
+#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
+
+// LED
+#define LED_PINMUX            IOMUXC_GPIO_B0_03_GPIO2_IO03 // D13
+#define LED_PORT              GPIO2
+#define LED_PIN               3
+#define LED_STATE_ON          0
+
+// no button
+#define BUTTON_PINMUX         IOMUXC_GPIO_B0_01_GPIO2_IO01 // D12
+#define BUTTON_PORT           GPIO2
+#define BUTTON_PIN            1
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_PORT             LPUART6
+#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_03_LPUART6_RX  // D0
+#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_02_LPUART6_TX  // D1
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/imxrt/boards/teensy_41/board.mk b/hw/bsp/imxrt/boards/teensy_41/board.mk
new file mode 100644
index 000000000..0ad5ea5c0
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board.mk
@@ -0,0 +1,10 @@
+CFLAGS += -DCPU_MIMXRT1062DVL6A
+MCU_VARIANT = MIMXRT1062
+
+# For flash-jlink target
+JLINK_DEVICE = MIMXRT1062xxx6A
+
+# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
+# Make sure it is in your PATH 
+flash: $(BUILD)/$(PROJECT).hex
+	teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
new file mode 100644
index 000000000..2d2bf8f09
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h>
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf")))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig =
+        {
+            .tag              = FLEXSPI_CFG_BLK_TAG,
+            .version          = FLEXSPI_CFG_BLK_VERSION,
+            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+            .csHoldTime       = 3u,
+            .csSetupTime      = 3u,
+            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
+            .sflashPadType = kSerialFlash_4Pads,
+            .serialClkFreq = kFlexSpiSerialClk_100MHz,
+            .sflashA1Size  = 8u * 1024u * 1024u,
+            .lookupTable =
+                {
+                    // Read LUTs
+                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+                },
+        },
+    .pageSize           = 256u,
+    .sectorSize         = 4u * 1024u,
+    .blockSize          = 256u * 1024u,
+    .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h
new file mode 100644
index 000000000..56068ec6a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __TEENSY40_FLEXSPI_NOR_CONFIG__
+#define __TEENSY40_FLEXSPI_NOR_CONFIG__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz  = 1,
+    kFlexSpiSerialClk_50MHz  = 2,
+    kFlexSpiSerialClk_60MHz  = 3,
+    kFlexSpiSerialClk_75MHz  = 4,
+    kFlexSpiSerialClk_80MHz  = 5,
+    kFlexSpiSerialClk_100MHz = 6,
+    kFlexSpiSerialClk_120MHz = 7,
+    kFlexSpiSerialClk_133MHz = 8,
+    kFlexSpiSerialClk_166MHz = 9,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad  = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
+#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t reserved0[2];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t reserve2[11];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */

From e9c29e6a2d42f931ededbc3ad1467cdd5dc1ea33 Mon Sep 17 00:00:00 2001
From: NConrad <pigrew@gmail.com>
Date: Tue, 21 Jun 2022 21:27:52 -0400
Subject: [PATCH 1074/2085] Update USBTMC driver to support dynamic packet
 sizes (based on descriptor).

---
 src/class/usbtmc/usbtmc_device.c | 36 +++++++++++++++++++-------------
 src/class/usbtmc/usbtmc_device.h |  4 ----
 2 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index b02b07575..9608e4835 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -64,7 +64,8 @@
 // USBTMC 3.2.2 error conditions not strictly followed
 // No local lock-out, REN, or GTL.
 // Clear message available status byte at the correct time? (488 4.3.1.3)
-
+// Ability to defer status byte transmission
+// Transmission of status byte in response to USB488 SRQ condition
 
 #include "tusb_option.h"
 
@@ -80,6 +81,11 @@
 static char logMsg[150];
 #endif
 
+// Buffer size must be an exact multiple of the max packet size for both
+// bulk  (up to 64 bytes for FS, 512 bytes for HS). In addation, this driver
+// imposes a minimum buffer size of 32 bytes. 
+#define USBTMCD_BUFFER_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
 /*
  * The state machine does not allow simultaneous reading and writing. This is
  * consistent with USBTMC.
@@ -120,9 +126,12 @@ typedef struct
   uint8_t ep_int_in;
   // IN buffer is only used for first packet, not the remainder
   // in order to deal with prepending header
-  CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_in_buf[USBTMCD_MAX_PACKET_SIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_in_buf[USBTMCD_BUFFER_SIZE];
+  uint32_t ep_bulk_in_wMaxPacketSize;
   // OUT buffer receives one packet at a time
-  CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_out_buf[USBTMCD_MAX_PACKET_SIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t ep_bulk_out_buf[USBTMCD_BUFFER_SIZE];
+  uint32_t ep_bulk_out_wMaxPacketSize;
+
   uint32_t transfer_size_remaining; // also used for requested length for bulk IN.
   uint32_t transfer_size_sent;      // To keep track of data bytes that have been queued in FIFO (not header bytes)
 
@@ -139,11 +148,8 @@ CFG_TUSB_MEM_SECTION static usbtmc_interface_state_t usbtmc_state =
     .itf_id = 0xFF,
 };
 
-// We need all headers to fit in a single packet in this implementation.
-TU_VERIFY_STATIC(USBTMCD_MAX_PACKET_SIZE >= 32u,"USBTMC dev EP packet size too small");
-TU_VERIFY_STATIC(
-    (sizeof(usbtmc_state.ep_bulk_in_buf) % USBTMCD_MAX_PACKET_SIZE) == 0,
-    "packet buffer must be a multiple of the packet size");
+// We need all headers to fit in a single packet in this implementation, 32 bytes will fit all standard USBTMC headers
+TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small");
 
 static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len);
 static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen);
@@ -151,7 +157,6 @@ static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t pack
 static uint8_t termChar;
 static uint8_t termCharRequested = false;
 
-
 osal_mutex_def_t usbtmcLockBuffer;
 static osal_mutex_t usbtmcLock;
 
@@ -282,12 +287,15 @@ uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
       tusb_desc_endpoint_t const *ep_desc = (tusb_desc_endpoint_t const *)p_desc;
       switch(ep_desc->bmAttributes.xfer) {
         case TUSB_XFER_BULK:
-          TU_ASSERT(tu_edpt_packet_size(ep_desc) == USBTMCD_MAX_PACKET_SIZE, 0);
+          // Ensure  buffer is an exact multiple of the maxPacketSize
+          TU_ASSERT((USBTMCD_BUFFER_SIZE % tu_edpt_packet_size(ep_desc)) == 0, 0);
           if (tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN)
           {
             usbtmc_state.ep_bulk_in = ep_desc->bEndpointAddress;
+            usbtmc_state.ep_bulk_in_wMaxPacketSize = tu_edpt_packet_size(ep_desc);
           } else {
             usbtmc_state.ep_bulk_out = ep_desc->bEndpointAddress;
+            usbtmc_state.ep_bulk_out_wMaxPacketSize = tu_edpt_packet_size(ep_desc);
           }
 
           break;
@@ -395,7 +403,7 @@ static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t pack
   // return true upon failure, as we can assume error is being handled elsewhere.
   TU_VERIFY(usbtmc_state.state == STATE_RCV,true);
 
-  bool shortPacket = (packetLen < USBTMCD_MAX_PACKET_SIZE);
+  bool shortPacket = (packetLen < usbtmc_state.ep_bulk_out_wMaxPacketSize);
 
   // Packet is to be considered complete when we get enough data or at a short packet.
   bool atEnd = false;
@@ -522,7 +530,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
       break;
 
     case STATE_TX_INITIATED:
-      if(usbtmc_state.transfer_size_remaining >=sizeof(usbtmc_state.ep_bulk_in_buf))
+      if(usbtmc_state.transfer_size_remaining >= sizeof(usbtmc_state.ep_bulk_in_buf))
       {
         // FIXME! This removes const below!
         TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in,
@@ -539,7 +547,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
         usbtmc_state.transfer_size_remaining = 0;
         usbtmc_state.devInBuffer = NULL;
         TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_state.ep_bulk_in_buf, (uint16_t)packetLen) );
-        if(((packetLen % USBTMCD_MAX_PACKET_SIZE) != 0) || (packetLen == 0 ))
+        if(((packetLen % usbtmc_state.ep_bulk_in_wMaxPacketSize) != 0) || (packetLen == 0 ))
         {
           usbtmc_state.state = STATE_TX_SHORTED;
         }
@@ -680,7 +688,7 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
     usbtmc_state.transfer_size_remaining = 0u;
       // Check if we've queued a short packet
       criticalEnter();
-      usbtmc_state.state = ((usbtmc_state.transfer_size_sent % USBTMCD_MAX_PACKET_SIZE) == 0) ?
+      usbtmc_state.state = ((usbtmc_state.transfer_size_sent % usbtmc_state.ep_bulk_in_wMaxPacketSize) == 0) ?
               STATE_ABORTING_BULK_IN : STATE_ABORTING_BULK_IN_SHORTED;
       criticalLeave();
       if(usbtmc_state.transfer_size_sent  == 0)
diff --git a/src/class/usbtmc/usbtmc_device.h b/src/class/usbtmc/usbtmc_device.h
index 5dc4d2dff..144b3315d 100644
--- a/src/class/usbtmc/usbtmc_device.h
+++ b/src/class/usbtmc/usbtmc_device.h
@@ -35,10 +35,6 @@
 #define CFG_TUD_USBTMC_ENABLE_488 (1)
 #endif
 
-// USB spec says that full-speed must be 8,16,32, or 64.
-// However, this driver implementation requires it to be >=32
-#define USBTMCD_MAX_PACKET_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
-
 /***********************************************
  *  Functions to be implemeted by the class implementation
  */

From 4a9fe813a807a32bf41ba2ec266a59a443b35d6f Mon Sep 17 00:00:00 2001
From: NConrad <pigrew@gmail.com>
Date: Tue, 21 Jun 2022 22:31:09 -0400
Subject: [PATCH 1075/2085] Update USBTMC descriptors to support high speed,
 set USB version to 2.0.0 for all cases.

---
 examples/device/usbtmc/src/usb_descriptors.c | 70 +++++++++++++++++---
 1 file changed, 59 insertions(+), 11 deletions(-)

diff --git a/examples/device/usbtmc/src/usb_descriptors.c b/examples/device/usbtmc/src/usb_descriptors.c
index 423482634..0946027e4 100644
--- a/examples/device/usbtmc/src/usb_descriptors.c
+++ b/examples/device/usbtmc/src/usb_descriptors.c
@@ -37,6 +37,9 @@
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
                            _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) )
 
+#define USB_VID   0xCafe
+#define USB_BCD   0x0200
+
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
@@ -51,9 +54,9 @@ tusb_desc_device_t const desc_device =
 
     .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-    .idVendor           = 0xCafe,
+    .idVendor           = USB_VID,
     .idProduct          = USB_PID,
-    .bcdDevice          = 0x0100,
+    .bcdDevice          = USB_BCD,
 
     .iManufacturer      = 0x01,
     .iProduct           = 0x02,
@@ -75,22 +78,22 @@ uint8_t const * tud_descriptor_device_cb(void)
 
 #if defined(CFG_TUD_USBTMC)
 
-#  define TUD_USBTMC_DESC_MAIN(_itfnum,_bNumEndpoints) \
+#  define TUD_USBTMC_DESC_MAIN(_itfnum,_bNumEndpoints, _bulkMaxPacketLength) \
      TUD_USBTMC_IF_DESCRIPTOR(_itfnum, _bNumEndpoints,  /*_stridx = */ 4u, TUD_USBTMC_PROTOCOL_USB488), \
-     TUD_USBTMC_BULK_DESCRIPTORS(/* OUT = */0x01, /* IN = */ 0x81, /* packet size = */USBTMCD_MAX_PACKET_SIZE)
+     TUD_USBTMC_BULK_DESCRIPTORS(/* OUT = */0x01, /* IN = */ 0x81, /* packet size = */_bulkMaxPacketLength)
 
 #if CFG_TUD_USBTMC_ENABLE_INT_EP
 // USBTMC Interrupt xfer always has length of 2, but we use epMaxSize=8 for
 //  compatibility with mcus that only allow 8, 16, 32 or 64 for FS endpoints
-#  define TUD_USBTMC_DESC(_itfnum) \
-     TUD_USBTMC_DESC_MAIN(_itfnum, /* _epCount = */ 3), \
+#  define TUD_USBTMC_DESC(_itfnum, _bulkMaxPacketLength) \
+     TUD_USBTMC_DESC_MAIN(_itfnum, /* _epCount = */ 3, _bulkMaxPacketLength), \
      TUD_USBTMC_INT_DESCRIPTOR(/* INT ep # */ 0x82, /* epMaxSize = */ 8, /* bInterval = */16u )
 #  define TUD_USBTMC_DESC_LEN (TUD_USBTMC_IF_DESCRIPTOR_LEN + TUD_USBTMC_BULK_DESCRIPTORS_LEN + TUD_USBTMC_INT_DESCRIPTOR_LEN)
 
 #else
 
-#  define TUD_USBTMC_DESC(_itfnum) \
-     TUD_USBTMC_DESC_MAIN(_itfnum, /* _epCount = */ 2u)
+#  define TUD_USBTMC_DESC(_itfnum, _bulkMaxPacketLength) \
+     TUD_USBTMC_DESC_MAIN(_itfnum, /* _epCount = */ 2u, _bulkMaxPacketLength)
 #  define TUD_USBTMC_DESC_LEN (TUD_USBTMC_IF_DESCRIPTOR_LEN + TUD_USBTMC_BULK_DESCRIPTORS_LEN)
 
 #endif /* CFG_TUD_USBTMC_ENABLE_INT_EP */
@@ -119,21 +122,66 @@ enum
 #endif
 
 
-uint8_t const desc_configuration[] =
+uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
-  TUD_USBTMC_DESC(ITF_NUM_USBTMC),
+  TUD_USBTMC_DESC(ITF_NUM_USBTMC, /* _bulkMaxPacketLength = */ 64),
 };
 
+#if TUD_OPT_HIGH_SPEED
+
+uint8_t const desc_hs_configuration[] =
+{
+  // Config number, interface count, string index, total length, attribute, power in mA
+  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+  TUD_USBTMC_DESC(ITF_NUM_USBTMC, /* _bulkMaxPacketLength = */ 512),
+};
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier =
+{
+  .bLength            = sizeof(tusb_desc_device_qualifier_t),
+  .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
+  .bcdUSB             = USB_BCD,
+
+  .bDeviceClass       = 0x00,
+  .bDeviceSubClass    = 0x00,
+  .bDeviceProtocol    = 0x00,
+
+  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+  .bNumConfigurations = 0x01,
+  .bReserved          = 0x00
+};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+uint8_t const* tud_descriptor_device_qualifier_cb(void)
+{
+  return (uint8_t const*) &desc_device_qualifier;
+}
+
+#endif
+
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
 uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 {
   (void) index; // for multiple configurations
-  return desc_configuration;
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ?  desc_hs_configuration : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
 }
 
 //--------------------------------------------------------------------+

From 4f6e770eda9f8c605b238f35def1edaff93a8fb8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Jun 2022 19:45:49 +0700
Subject: [PATCH 1076/2085] add more warning option, also fix  -Wconversion
 with rp2040

-Wuninitialized, -Wunused,  -Wredundant-decls
---
 examples/device/cdc_msc/src/usb_descriptors.c |  2 +-
 examples/make.mk                              |  7 +++-
 hw/bsp/broadcom_32bit/family.mk               |  2 +-
 hw/bsp/broadcom_64bit/family.mk               |  2 +-
 hw/bsp/imxrt/family.mk                        |  2 +-
 .../boards/mm32f327x_mb39/mm32f327x_mb39.c    |  1 -
 hw/bsp/nrf/family.mk                          |  3 ++
 hw/bsp/rx/family.mk                           |  3 ++
 hw/bsp/samd21/family.mk                       |  2 +-
 hw/bsp/saml2x/family.mk                       |  2 +-
 hw/mcu/raspberry_pi/Pico-PIO-USB              |  2 +-
 src/class/cdc/cdc_device.c                    |  6 ++--
 src/class/msc/msc_device.c                    | 33 ++++++++++---------
 src/common/tusb_fifo.c                        | 12 +++----
 src/device/usbd.c                             | 16 +++++----
 src/device/usbd_control.c                     |  2 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h       |  3 +-
 17 files changed, 58 insertions(+), 42 deletions(-)

diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 09894cf1b..6b59ed50f 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -282,7 +282,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/make.mk b/examples/make.mk
index bed46d02b..26065c027 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -108,8 +108,13 @@ CFLAGS += \
   -Wcast-align \
   -Wcast-function-type \
   -Wcast-qual \
-  -Wnull-dereference
+  -Wnull-dereference \
+  -Wuninitialized \
+  -Wunused \
+  -Wredundant-decls
 
+#  -Wconversion \
+  
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
   CFLAGS += -Og
diff --git a/hw/bsp/broadcom_32bit/family.mk b/hw/bsp/broadcom_32bit/family.mk
index 98744c5d0..cf68e21ee 100644
--- a/hw/bsp/broadcom_32bit/family.mk
+++ b/hw/bsp/broadcom_32bit/family.mk
@@ -16,7 +16,7 @@ CFLAGS += \
 CROSS_COMPILE = arm-none-eabi-
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=cast-qual
+CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
diff --git a/hw/bsp/broadcom_64bit/family.mk b/hw/bsp/broadcom_64bit/family.mk
index 723926734..97af6d64a 100644
--- a/hw/bsp/broadcom_64bit/family.mk
+++ b/hw/bsp/broadcom_64bit/family.mk
@@ -15,7 +15,7 @@ CFLAGS += \
 CROSS_COMPILE = aarch64-none-elf-
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=cast-qual
+CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index c81e67eb6..0a55b740b 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -23,7 +23,7 @@ CFLAGS += -DBOARD_TUH_RHPORT=$(BOARD_TUH_RHPORT)
 endif
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough=
+CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough -Wno-error=redundant-decls
 
 MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
 
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
index cff7bc15e..9793ba241 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
@@ -52,7 +52,6 @@ void USB_DeviceClockInit (void)
 //--------------------------------------------------------------------+
 // LED
 
-void board_led_write (bool state);
 extern u32 SystemCoreClock;
 const int baudrate = 115200;
 
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index d8283a9e6..609e2da0b 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -16,6 +16,9 @@ CFLAGS += \
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
 
+# warning caused by dcd_nrf5x.c due to include of usbd.h and re-declare of dcd_int_handler()
+CFLAGS += -Wno-error=redundant-decls
+
 # All source paths should be relative to the top level.
 LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
 
diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk
index aba05812d..f4f8ae088 100644
--- a/hw/bsp/rx/family.mk
+++ b/hw/bsp/rx/family.mk
@@ -13,6 +13,9 @@ CFLAGS += \
   -mlittle-endian-data \
   -DSSIZE_MAX=__INT_MAX__
 
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=redundant-decls
+
 SRC_C += \
 	src/portable/renesas/usba/dcd_usba.c \
 	src/portable/renesas/usba/hcd_usba.c \
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index 208f23789..95421e753 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -13,7 +13,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD21
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
+CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index bb1faeb7f..afb0afc03 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -14,7 +14,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAML22
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
+CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
diff --git a/hw/mcu/raspberry_pi/Pico-PIO-USB b/hw/mcu/raspberry_pi/Pico-PIO-USB
index 2a9fefd6c..92bd3b4c3 160000
--- a/hw/mcu/raspberry_pi/Pico-PIO-USB
+++ b/hw/mcu/raspberry_pi/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 2a9fefd6ccf42e5d8570ae83fdc54c9c875ebdd1
+Subproject commit 92bd3b4c3ad2fce36166e4a357749b6d4fe9013b
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 7aa7a4860..fab6f0035 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -145,7 +145,7 @@ uint32_t tud_cdc_n_available(uint8_t itf)
 uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize)
 {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, bufsize);
+  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) bufsize);
   _prep_out_transaction(p_cdc);
   return num_read;
 }
@@ -168,7 +168,7 @@ void tud_cdc_n_read_flush (uint8_t itf)
 uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
 {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, bufsize);
+  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) bufsize);
 
   // flush if queue more than packet size
   if ( tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE )
@@ -435,7 +435,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   // Received new data
   if ( ep_addr == p_cdc->ep_out )
   {
-    tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, xferred_bytes);
+    tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, (uint16_t) xferred_bytes);
     
     // Check for wanted char and invoke callback if needed
     if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) )
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 3facb76d6..33dd4ac37 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -463,7 +463,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           {
             // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first
             // but it is OK to just receive data then responded with failed status
-            TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, p_msc->total_len) );
+            TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, (uint16_t) p_msc->total_len) );
           }
         }else
         {
@@ -473,7 +473,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           // Invoke user callback if not built-in
           if ( (resplen < 0) && (p_msc->sense_key == 0) )
           {
-            resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, p_msc->total_len);
+            resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, (uint16_t) p_msc->total_len);
           }
 
           if ( resplen < 0 )
@@ -506,7 +506,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
             {
               // cannot return more than host expect
               p_msc->total_len = tu_min32((uint32_t) resplen, p_cbw->total_bytes);
-              TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, p_msc->total_len) );
+              TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, (uint16_t) p_msc->total_len) );
             }
           }
         }
@@ -541,7 +541,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         // OUT transfer, invoke callback if needed
         if ( !is_data_in(p_cbw->dir) )
         {
-          int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, p_msc->total_len);
+          int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, (uint16_t) p_msc->total_len);
 
           if ( cb_result < 0 )
           {
@@ -707,7 +707,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         read_capa10.block_size = tu_htonl(block_size);
 
         resplen = sizeof(read_capa10);
-        memcpy(buffer, &read_capa10, resplen);
+        memcpy(buffer, &read_capa10, (size_t) resplen);
       }
     }
     break;
@@ -741,7 +741,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         read_fmt_capa.block_size_u16 = tu_htons(block_size);
 
         resplen = sizeof(read_fmt_capa);
-        memcpy(buffer, &read_fmt_capa, resplen);
+        memcpy(buffer, &read_fmt_capa, (size_t) resplen);
       }
     }
     break;
@@ -764,7 +764,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       tud_msc_inquiry_cb(lun, inquiry_rsp.vendor_id, inquiry_rsp.product_id, inquiry_rsp.product_rev);
 
       resplen = sizeof(inquiry_rsp);
-      memcpy(buffer, &inquiry_rsp, resplen);
+      memcpy(buffer, &inquiry_rsp, (size_t) resplen);
     }
     break;
 
@@ -788,7 +788,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       mode_resp.write_protected = !writable;
 
       resplen = sizeof(mode_resp);
-      memcpy(buffer, &mode_resp, resplen);
+      memcpy(buffer, &mode_resp, (size_t) resplen);
     }
     break;
 
@@ -801,17 +801,17 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       };
 
       sense_rsp.add_sense_len       = sizeof(scsi_sense_fixed_resp_t) - 8;
-      sense_rsp.sense_key           = p_msc->sense_key;
+      sense_rsp.sense_key           = (uint8_t) (p_msc->sense_key & 0x0F);
       sense_rsp.add_sense_code      = p_msc->add_sense_code;
       sense_rsp.add_sense_qualifier = p_msc->add_sense_qualifier;
 
       resplen = sizeof(sense_rsp);
-      memcpy(buffer, &sense_rsp, resplen);
+      memcpy(buffer, &sense_rsp, (size_t) resplen);
 
       // request sense callback could overwrite the sense data
       if (tud_msc_request_sense_cb)
       {
-        resplen = tud_msc_request_sense_cb(lun, buffer, bufsize);
+        resplen = tud_msc_request_sense_cb(lun, buffer, (uint16_t) bufsize);
       }
 
       // Clear sense data after copy
@@ -859,7 +859,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   }
   else
   {
-    TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, nbytes), );
+    TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, (uint16_t) nbytes), );
   }
 }
 
@@ -883,7 +883,7 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   }
 
   // remaining bytes capped at class buffer
-  int32_t nbytes = (int32_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len);
+  uint16_t nbytes = (uint16_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len);
 
   // Write10 callback will be called later when usb transfer complete
   TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, nbytes), );
@@ -921,14 +921,15 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
     // Application consume less than what we got (including zero)
     if ( (uint32_t) nbytes < xferred_bytes )
     {
+      uint32_t const left_over = xferred_bytes - (uint32_t) nbytes;
       if ( nbytes > 0 )
       {
-        p_msc->xferred_len += nbytes;
-        memmove(_mscd_buf, _mscd_buf+nbytes, xferred_bytes-nbytes);
+        p_msc->xferred_len += (uint16_t) nbytes;
+        memmove(_mscd_buf, _mscd_buf+nbytes, left_over);
       }
 
       // simulate an transfer complete with adjusted parameters --> callback will be invoked with adjusted parameter
-      dcd_event_xfer_complete(rhport, p_msc->ep_out, xferred_bytes-nbytes, XFER_RESULT_SUCCESS, false);
+      dcd_event_xfer_complete(rhport, p_msc->ep_out, left_over, XFER_RESULT_SUCCESS, false);
     }
     else
     {
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 183c9c6fc..895b9208b 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -79,7 +79,7 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
   // Limit index space to 2*depth - this allows for a fast "modulo" calculation
   // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable
   // only if overflow happens once (important for unsupervised DMA applications)
-  f->max_pointer_idx = 2*depth - 1;
+  f->max_pointer_idx = (uint16_t) (2*depth - 1);
   f->non_used_index_space = UINT16_MAX - f->max_pointer_idx;
 
   f->rd_idx = f->wr_idx = 0;
@@ -205,7 +205,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         uint8_t rem = nLin_bytes & 0x03;
         if (rem > 0)
         {
-          uint8_t remrem = tu_min16(nWrap_bytes, 4-rem);
+          uint8_t remrem = (uint8_t) tu_min16(nWrap_bytes, 4-rem);
           nWrap_bytes -= remrem;
 
           uint32_t tmp32 = *rx_fifo;
@@ -288,7 +288,7 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
         uint8_t rem = nLin_bytes & 0x03;
         if (rem > 0)
         {
-          uint8_t remrem = tu_min16(nWrap_bytes, 4-rem);
+          uint8_t remrem = (uint8_t) tu_min16(nWrap_bytes, 4-rem);
           nWrap_bytes -= remrem;
 
           uint32_t tmp32=0;
@@ -325,7 +325,7 @@ static uint16_t advance_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
   // We are exploiting the wrap around to the correct index
   if ((p > (uint16_t)(p + offset)) || ((uint16_t)(p + offset) > f->max_pointer_idx))
   {
-    p = (p + offset) + f->non_used_index_space;
+    p = (uint16_t) ((p + offset) + f->non_used_index_space);
   }
   else
   {
@@ -342,7 +342,7 @@ static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
   // We are exploiting the wrap around to the correct index
   if ((p < (uint16_t)(p - offset)) || ((uint16_t)(p - offset) > f->max_pointer_idx))
   {
-    p = (p - offset) - f->non_used_index_space;
+    p = (uint16_t) ((p - offset) - f->non_used_index_space);
   }
   else
   {
@@ -818,7 +818,7 @@ bool tu_fifo_clear(tu_fifo_t *f)
   _ff_lock(f->mutex_rd);
 
   f->rd_idx = f->wr_idx = 0;
-  f->max_pointer_idx = 2*f->depth-1;
+  f->max_pointer_idx = (uint16_t) (2*f->depth-1);
   f->non_used_index_space = UINT16_MAX - f->max_pointer_idx;
 
   _ff_unlock(f->mutex_wr);
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 1806281ff..fa894accc 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -409,6 +409,7 @@ bool tud_init (uint8_t rhport)
   for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
   {
     usbd_class_driver_t const * driver = get_driver(i);
+    TU_ASSERT(driver);
     TU_LOG2("%s init\r\n", driver->name);
     driver->init();
   }
@@ -426,7 +427,9 @@ static void configuration_reset(uint8_t rhport)
 {
   for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ )
   {
-    get_driver(i)->reset(rhport);
+    usbd_class_driver_t const * driver = get_driver(i);
+    TU_ASSERT(driver, );
+    driver->reset(rhport);
   }
 
   tu_varclr(&_usbd_dev);
@@ -735,7 +738,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           // Device status bit mask
           // - Bit 0: Self Powered
           // - Bit 1: Remote Wakeup enabled
-          uint16_t status = (_usbd_dev.self_powered ? 1 : 0) | (_usbd_dev.remote_wakeup_en ? 2 : 0);
+          uint16_t status = (uint16_t) ((_usbd_dev.self_powered ? 1u : 0u) | (_usbd_dev.remote_wakeup_en ? 2u : 0u));
           tud_control_xfer(rhport, p_request, &status, 2);
         }
         break;
@@ -867,8 +870,8 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
   TU_ASSERT(desc_cfg != NULL && desc_cfg->bDescriptorType == TUSB_DESC_CONFIGURATION);
 
   // Parse configuration descriptor
-  _usbd_dev.remote_wakeup_support = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP) ? 1 : 0;
-  _usbd_dev.self_powered          = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_SELF_POWERED ) ? 1 : 0;
+  _usbd_dev.remote_wakeup_support = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP) ? 1u : 0u;
+  _usbd_dev.self_powered          = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_SELF_POWERED ) ? 1u : 0u;
 
   // Parse interface descriptor
   uint8_t const * p_desc   = ((uint8_t const*) desc_cfg) + sizeof(tusb_desc_configuration_t);
@@ -895,11 +898,12 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
     tusb_desc_interface_t const * desc_itf = (tusb_desc_interface_t const*) p_desc;
 
     // Find driver for this interface
-    uint16_t const remaining_len = desc_end-p_desc;
+    uint16_t const remaining_len = (uint16_t) (desc_end-p_desc);
     uint8_t drv_id;
     for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
     {
       usbd_class_driver_t const *driver = get_driver(drv_id);
+      TU_ASSERT(driver);
       uint16_t const drv_len = driver->open(rhport, desc_itf, remaining_len);
 
       if ( (sizeof(tusb_desc_interface_t) <= drv_len)  && (drv_len <= remaining_len) )
@@ -1101,7 +1105,7 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const * event, bool in_isr)
       for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
       {
         usbd_class_driver_t const * driver = get_driver(i);
-        if (driver->sof)
+        if (driver && driver->sof)
         {
           driver->sof(event->rhport, event->sof.frame_count);
         }
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 4f4108090..94a952df7 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -189,7 +189,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
     TU_LOG_MEM(2, _usbd_ctrl_buf, xferred_bytes, 2);
   }
 
-  _ctrl_xfer.total_xferred += xferred_bytes;
+  _ctrl_xfer.total_xferred += (uint16_t) xferred_bytes;
   _ctrl_xfer.buffer += xferred_bytes;
 
   // Data Stage is complete when all request's length are transferred or
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index b500ddc46..1d849541e 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -103,7 +103,8 @@ static const dwc2_controller_t _dwc2_controller[] =
 //
 //--------------------------------------------------------------------+
 
-extern uint32_t SystemCoreClock;
+// SystemCoreClock is alrady included by family header
+// extern uint32_t SystemCoreClock;
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)

From 835ab01cab9ebe20eac46da1853eb158e1248f01 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Jun 2022 21:52:51 +0700
Subject: [PATCH 1077/2085] fix stm32 g4 and wb build issue with freertos, also
 add them to ci build

---
 .github/workflows/build_arm.yml | 2 ++
 hw/bsp/board_mcu.h              | 8 +++++++-
 hw/bsp/stm32g4/family.c         | 4 +++-
 hw/bsp/stm32wb/family.c         | 3 ++-
 4 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 5a796a49b..6e4702735 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -57,8 +57,10 @@ jobs:
         - 'stm32f1'
         - 'stm32f4'
         - 'stm32f7'
+        - 'stm32g4'
         - 'stm32h7'
         - 'stm32l4'
+        - 'stm32wb'
         - 'tm4c123'
         - 'xmc4000'
     steps:
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index b911e1e53..8202479cb 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -31,7 +31,7 @@
 #include "tusb_option.h"
 
 //--------------------------------------------------------------------+
-// Low Level MCU header include. TinyUSB stack and example should be
+// Low Level MCU header include. Example should be
 // platform independent and mostly doesn't need to include this file.
 // However there are still certain situation where this file is needed:
 // - FreeRTOSConfig.h to set up correct clock and NVIC interrupts for ARM Cortex
@@ -80,6 +80,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
   #include "stm32f7xx.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
+  #include "stm32g4xx.h"
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32H7
   #include "stm32h7xx.h"
 
@@ -92,6 +95,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L4
   #include "stm32l4xx.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32WB
+  #include "stm32wbxx.h"
+
 #elif CFG_TUSB_MCU == OPT_MCU_CXD56
   // no header needed
 
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index 461dc61a1..a2312b0d8 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -73,7 +73,9 @@ void board_init(void)
   SysTick->CTRL &= ~1U;
 
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB_HP_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USB_LP_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
   GPIO_InitTypeDef  GPIO_InitStruct;
diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c
index 1ed38308b..9f1f46f4d 100644
--- a/hw/bsp/stm32wb/family.c
+++ b/hw/bsp/stm32wb/family.c
@@ -67,7 +67,8 @@ void board_init(void)
   SysTick->CTRL &= ~1U;
 
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+  NVIC_SetPriority(USB_HP_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USB_LP_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
   GPIO_InitTypeDef  GPIO_InitStruct;

From 1d6918ce419b7df13def76759ba804c46ea8024c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Jun 2022 21:53:46 +0700
Subject: [PATCH 1078/2085] suppress redundant-decls warnings for freertos
 examples

---
 examples/device/cdc_msc_freertos/Makefile                       | 2 +-
 .../device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h | 1 +
 examples/device/hid_composite_freertos/Makefile                 | 2 +-
 hw/bsp/samd11/family.mk                                         | 2 +-
 4 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index a155d6cb7..3352dd37d 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -30,7 +30,7 @@ SRC_C += \
 	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
 
 # Suppress FreeRTOS warnings
-CFLAGS += -Wno-error=cast-qual
+CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 # FreeRTOS (lto + Os) linker issue
 LDFLAGS += -Wl,--undefined=vTaskSwitchContext
diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index ccb620720..6a3630dbc 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -53,6 +53,7 @@
 #if CFG_TUSB_MCU == OPT_MCU_MM32F327X
   extern u32 SystemCoreClock;
 #else
+  // FIXME cause redundant-decls warnings
   extern uint32_t SystemCoreClock;
 #endif
 
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index c9b7abdf5..6c8c43ddd 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -29,7 +29,7 @@ SRC_C += \
 	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
 
 # Suppress FreeRTOS warnings
-CFLAGS += -Wno-error=cast-qual
+CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 # FreeRTOS (lto + Os) linker issue
 LDFLAGS += -Wl,--undefined=vTaskSwitchContext
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index ae55be75b..85cc136a6 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD11
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
+CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \

From 0042eccb3b2ff0f980f3a927a271364a2089ada5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Jun 2022 22:22:52 +0700
Subject: [PATCH 1079/2085] fix redundant-decls warnings by usbd/usbh

---
 examples/make.mk           | 6 +++---
 hw/bsp/nrf/family.mk       | 3 ---
 src/class/msc/msc_device.c | 2 +-
 src/device/dcd.h           | 7 -------
 src/device/usbd.c          | 2 +-
 src/device/usbd.h          | 5 ++++-
 src/device/usbd_control.c  | 2 +-
 src/host/hub.c             | 1 +
 src/host/usbh.c            | 3 +--
 src/host/usbh.h            | 6 ++++--
 10 files changed, 16 insertions(+), 21 deletions(-)

diff --git a/examples/make.mk b/examples/make.mk
index 26065c027..fa909ddca 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -90,13 +90,13 @@ CFLAGS += \
   -ffunction-sections \
   -fsingle-precision-constant \
   -fno-strict-aliasing \
-  -Wdouble-promotion \
-  -Wstrict-prototypes \
-  -Wstrict-overflow \
   -Wall \
   -Wextra \
   -Werror \
   -Wfatal-errors \
+  -Wdouble-promotion \
+  -Wstrict-prototypes \
+  -Wstrict-overflow \
   -Werror-implicit-function-declaration \
   -Wfloat-equal \
   -Wundef \
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index 609e2da0b..d8283a9e6 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -16,9 +16,6 @@ CFLAGS += \
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
 
-# warning caused by dcd_nrf5x.c due to include of usbd.h and re-declare of dcd_int_handler()
-CFLAGS += -Wno-error=redundant-decls
-
 # All source paths should be relative to the top level.
 LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
 
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 33dd4ac37..00b0a1d06 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -28,9 +28,9 @@
 
 #if (CFG_TUD_ENABLED && CFG_TUD_MSC)
 
+#include "device/dcd.h"         // for faking dcd_event_xfer_complete
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
-#include "device/dcd.h"         // for faking dcd_event_xfer_complete
 
 #include "msc_device.h"
 
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 6b99734fe..c1780f656 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -110,14 +110,7 @@ typedef struct TU_ATTR_ALIGNED(4)
 void dcd_init       (uint8_t rhport);
 
 // Interrupt Handler
-#if __GNUC__ && !defined(__ARMCC_VERSION)
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wredundant-decls"
-#endif
 void dcd_int_handler(uint8_t rhport);
-#if __GNUC__ && !defined(__ARMCC_VERSION)
-#pragma GCC diagnostic pop
-#endif
 
 // Enable device interrupt
 void dcd_int_enable (uint8_t rhport);
diff --git a/src/device/usbd.c b/src/device/usbd.c
index fa894accc..b2053174e 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -28,12 +28,12 @@
 
 #if CFG_TUD_ENABLED
 
+#include "device/dcd.h"
 #include "tusb.h"
 #include "common/tusb_private.h"
 
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
-#include "device/dcd.h"
 
 //--------------------------------------------------------------------+
 // USBD Configuration
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 964cfb992..17b4d927b 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -58,8 +58,11 @@ void tud_task (void)
 // Check if there is pending events need processing by tud_task()
 bool tud_task_event_ready(void);
 
-// Interrupt handler, name alias to DCD
+#ifndef _TUSB_DCD_H_
 extern void dcd_int_handler(uint8_t rhport);
+#endif
+
+// Interrupt handler, name alias to DCD
 #define tud_int_handler   dcd_int_handler
 
 // Get current bus speed
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 94a952df7..0995ef669 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -28,9 +28,9 @@
 
 #if CFG_TUD_ENABLED
 
+#include "dcd.h"
 #include "tusb.h"
 #include "device/usbd_pvt.h"
-#include "dcd.h"
 
 #if CFG_TUSB_DEBUG >= 2
 extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
diff --git a/src/host/hub.c b/src/host/hub.c
index 5c0fd9166..3400b154a 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -28,6 +28,7 @@
 
 #if (CFG_TUH_ENABLED && CFG_TUH_HUB)
 
+#include "hcd.h"
 #include "usbh.h"
 #include "usbh_classdriver.h"
 #include "hub.h"
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 4807d20b8..4c9b0b1ba 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -28,10 +28,9 @@
 
 #if CFG_TUH_ENABLED
 
+#include "host/hcd.h"
 #include "tusb.h"
 #include "common/tusb_private.h"
-
-#include "host/usbh.h"
 #include "host/usbh_classdriver.h"
 #include "hub.h"
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 347c75b8c..560a1ea23 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -32,7 +32,6 @@
 #endif
 
 #include "common/tusb_common.h"
-#include "hcd.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
@@ -115,8 +114,11 @@ void tuh_task(void)
   tuh_task_ext(UINT32_MAX, false);
 }
 
-// Interrupt handler, name alias to HCD
+#ifndef _TUSB_HCD_H_
 extern void hcd_int_handler(uint8_t rhport);
+#endif
+
+// Interrupt handler, name alias to HCD
 #define tuh_int_handler   hcd_int_handler
 
 bool tuh_vid_pid_get(uint8_t daddr, uint16_t* vid, uint16_t* pid);

From 3d4d37375bbfb0bc88127be3aa79930e865f35b5 Mon Sep 17 00:00:00 2001
From: NConrad <pigrew@gmail.com>
Date: Tue, 21 Jun 2022 23:17:50 -0400
Subject: [PATCH 1080/2085] USBTMC: Update test python code to use the new
 pyvisa namespace, and other misc fixes

---
 examples/device/usbtmc/visaQuery.py | 35 ++++++++++++++++-------------
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/examples/device/usbtmc/visaQuery.py b/examples/device/usbtmc/visaQuery.py
index 50a765a03..c4e5ad2b9 100644
--- a/examples/device/usbtmc/visaQuery.py
+++ b/examples/device/usbtmc/visaQuery.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 
-import visa
+import pyvisa
 import time
 import sys
 
@@ -54,9 +54,9 @@ def test_srq():
 	assert (inst.read_stb() == 0)
 	inst.write("123")
 	
-	#inst.enable_event(visa.constants.VI_EVENT_SERVICE_REQ, visa.constants.VI_QUEUE)
-	#waitrsp = inst.wait_on_event(visa.constants.VI_EVENT_SERVICE_REQ, 5000)
-	#inst.discard_events(visa.constants.VI_EVENT_SERVICE_REQ, visa.constants.VI_QUEUE)
+	#inst.enable_event(pyvisa.constants.VI_EVENT_SERVICE_REQ, pyvisa.constants.VI_QUEUE)
+	#waitrsp = inst.wait_on_event(pyvisa.constants.VI_EVENT_SERVICE_REQ, 5000)
+	#inst.discard_events(pyvisa.constants.VI_EVENT_SERVICE_REQ, pyvisa.constants.VI_QUEUE)
 	#inst.wait_for_srq()
 	time.sleep(0.3)
 	stb = inst.read_stb()
@@ -77,8 +77,8 @@ def test_read_timeout():
 	t0 = time.monotonic()
 	try:
 		rsp = inst.read()
-		assert(false), "Read should have resulted in timeout"
-	except visa.VisaIOError:
+		assert(False), "Read should have resulted in timeout"
+	except pyvisa.VisaIOError:
 		print("  Got expected exception")
 	t = time.monotonic() - t0
 	assert ((t*1000.0) > (inst.timeout - 300))
@@ -99,23 +99,27 @@ def test_abort_in():
 	t0 = time.monotonic()
 	try:
 		rsp = inst.read()
-		assert(false), "Read should have resulted in timeout"
-	except visa.VisaIOError:
+		assert(False), "Read should have resulted in timeout"
+	except pyvisa.VisaIOError:
 		print("  Got expected exception")
 	t = time.monotonic() - t0
 	assert ((t*1000.0) > (inst.timeout - 300))
 	assert ((t*1000.0) < (inst.timeout + 300))
 	print(f"  Delay was {t:0.3}")
-	# Response is still in queue, so send a clear (to be more helpful to the next test)
+	# Response is still in queue, so read it out (to be more helpful to the next test)
 	inst.timeout = 800
 	y = inst.read()
 	assert(y == "xxx\r\n")
 	
 def test_indicate():
 	# perform indicator pulse
-	usb_iface = inst.get_visa_attribute(visa.constants.VI_ATTR_USB_INTFC_NUM)
+	usb_iface = inst.get_visa_attribute(pyvisa.constants.VI_ATTR_USB_INTFC_NUM)
 	retv = inst.control_in(request_type_bitmap_field=0xA1, request_id=64, request_value=0x0000, index=usb_iface, length=0x0001)
-	assert((retv[1] == visa.constants.StatusCode(0)) and (retv[0] == b'\x01')), f"indicator pulse failed: retv={retv}"
+	# pyvisa used to return (statuscode,bytes), but now only returns bytes, so we need to handle both cases
+	if(isinstance(retv,bytes)):
+		assert(retv == b'\x01')
+	else:
+		assert((retv[1] == pyvisa.constants.StatusCode(0)) and (retv[0] == b'\x01')), f"indicator pulse failed: retv={retv}"
 	
 	
 def test_multi_read():
@@ -131,19 +135,19 @@ def test_multi_read():
 	#inst.chunk_size = old_chunk_size
 	
 def test_stall_ep0():
-	usb_iface = inst.get_visa_attribute(visa.constants.VI_ATTR_USB_INTFC_NUM)
+	usb_iface = inst.get_visa_attribute(pyvisa.constants.VI_ATTR_USB_INTFC_NUM)
 	inst.read_stb()
 	# This is an invalid request, should create stall.
 	try:
 		retv = inst.control_in(request_type_bitmap_field=0xA1, request_id=60, request_value=0x0000, index=usb_iface, length=0x0001)
-		assert false
-	except visa.VisaIOError:
+		assert(False)
+	except pyvisa.VisaIOError:
 		pass
 	
 	assert (inst.read_stb() == 0)
 
 
-rm = visa.ResourceManager()
+rm = pyvisa.ResourceManager()
 reslist = rm.list_resources("USB?::?*::INSTR")
 print(reslist)
 
@@ -167,7 +171,6 @@ inst.timeout = 2000
 print("+ multi read")
 test_multi_read()
 
-
 print("+ echo delay=0")
 inst.write("delay 0")
 test_echo(1,175)

From 239b5d52790051949c281e60ba96ac674669f026 Mon Sep 17 00:00:00 2001
From: NConrad <pigrew@gmail.com>
Date: Fri, 24 Jun 2022 23:06:32 -0400
Subject: [PATCH 1081/2085] USBTMC: Manually stall and unstall EP when
 clear(ENDPOINT_HALT) is received.

---
 src/class/usbtmc/usbtmc_device.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 9608e4835..b5232ab91 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -597,18 +597,31 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
   {
     uint32_t ep_addr = (request->wIndex);
 
+    // At this point, a transfer MAY be in progress. Based on USB spec, when clearing bulk EP HALT,
+    // the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if 
+    // the EP is not halted. The only USBD API interface to do this is to stall and then unstall the EP.
     if(ep_addr == usbtmc_state.ep_bulk_out)
     {
       criticalEnter();
+      usbd_edpt_stall(rhport, ep_addr);
+      usbd_edpt_clear_stall(rhport, ep_addr);
       usbtmc_state.state = STATE_NAK; // USBD core has placed EP in NAK state for us
       criticalLeave();
       tud_usbtmc_bulkOut_clearFeature_cb();
     }
     else if (ep_addr == usbtmc_state.ep_bulk_in)
     {
+      usbd_edpt_stall(rhport, ep_addr);
+      usbd_edpt_clear_stall(rhport, ep_addr);
       tud_usbtmc_bulkIn_clearFeature_cb();
     }
-    else
+    else if ((usbtmc_state.ep_int_in != 0) && (ep_addr == usbtmc_state.ep_int_in))
+    {
+      // Clearing interrupt in EP
+      usbd_edpt_stall(rhport, ep_addr);
+      usbd_edpt_clear_stall(rhport, ep_addr);
+    }
+     else
     {
       return false;
     }
@@ -836,6 +849,7 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
           },
           .StatusByte = tud_usbtmc_get_stb_cb(&(rsp.USBTMC_status))
         };
+        // USB488 spec states that transfer must be queued before control request response sent.
         usbd_edpt_xfer(rhport, usbtmc_state.ep_int_in, (void*)&intMsg, sizeof(intMsg));
       }
       else

From c675debfb2dcff1697cb6643afb60c26309bdfcf Mon Sep 17 00:00:00 2001
From: NConrad <pigrew@gmail.com>
Date: Sun, 26 Jun 2022 14:34:34 -0400
Subject: [PATCH 1082/2085] USBTMC: Handle busy interrupt in.

---
 src/class/usbtmc/usbtmc.h        |  5 ++++-
 src/class/usbtmc/usbtmc_device.c | 32 +++++++++++++++++++-------------
 2 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h
index 7d7005c2e..e7016ae24 100644
--- a/src/class/usbtmc/usbtmc.h
+++ b/src/class/usbtmc/usbtmc.h
@@ -189,7 +189,10 @@ typedef enum {
   USBTMC_STATUS_FAILED = 0x80,
   USBTMC_STATUS_TRANSFER_NOT_IN_PROGRESS = 0x81,
   USBTMC_STATUS_SPLIT_NOT_IN_PROGRESS = 0x82,
-  USBTMC_STATUS_SPLIT_IN_PROGRESS  = 0x83
+  USBTMC_STATUS_SPLIT_IN_PROGRESS  = 0x83,
+
+  /****** USBTMC 488 *************/
+  USB488_STATUS_INTERRUPT_IN_BUSY = 0x20
 } usbtmc_status_enum;
 
 /************************************************************
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index b5232ab91..c50ca65d5 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -831,26 +831,32 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
 
       bTag = request->wValue & 0x7F;
       TU_VERIFY(request->bmRequestType == 0xA1);
-      TU_VERIFY((request->wValue & (~0x7F)) == 0u); // Other bits are required to be zero
+      TU_VERIFY((request->wValue & (~0x7F)) == 0u); // Other bits are required to be zero (USB488v1.0 Table 11)
       TU_VERIFY(bTag >= 0x02 && bTag <= 127);
       TU_VERIFY(request->wIndex == usbtmc_state.itf_id);
       TU_VERIFY(request->wLength == 0x0003);
       rsp.bTag = (uint8_t)bTag;
       if(usbtmc_state.ep_int_in != 0)
       {
-        rsp.USBTMC_status = USBTMC_STATUS_SUCCESS;
-        rsp.statusByte = 0x00; // Use interrupt endpoint, instead.
-
-        usbtmc_read_stb_interrupt_488_t intMsg =
+        rsp.statusByte = 0x00; // Use interrupt endpoint, instead. Must be 0x00 (USB488v1.0 4.3.1.2)
+        if(usbd_edpt_busy(rhport, usbtmc_state.ep_int_in))
         {
-          .bNotify1 = {
-              .one = 1,
-              .bTag = bTag & 0x7Fu,
-          },
-          .StatusByte = tud_usbtmc_get_stb_cb(&(rsp.USBTMC_status))
-        };
-        // USB488 spec states that transfer must be queued before control request response sent.
-        usbd_edpt_xfer(rhport, usbtmc_state.ep_int_in, (void*)&intMsg, sizeof(intMsg));
+          rsp.USBTMC_status = USB488_STATUS_INTERRUPT_IN_BUSY;
+        }
+        else
+        {
+          rsp.USBTMC_status = USBTMC_STATUS_SUCCESS;
+          usbtmc_read_stb_interrupt_488_t intMsg =
+          {
+            .bNotify1 = {
+                .one = 1,
+                .bTag = bTag & 0x7Fu,
+            },
+            .StatusByte = tud_usbtmc_get_stb_cb(&(rsp.USBTMC_status))
+          };
+          // Must be queued before control request response sent (USB488v1.0 4.3.1.2)
+          usbd_edpt_xfer(rhport, usbtmc_state.ep_int_in, (void*)&intMsg, sizeof(intMsg));
+        }
       }
       else
       {

From b9dc9dbd78ee1890342429502d585f323c480fc2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 27 Jun 2022 11:50:17 +0700
Subject: [PATCH 1083/2085] fix most warnings with rp2040 -wconversion

---
 .../device/audio_4_channel_mic/CMakeLists.txt |  3 +++
 .../device/audio_4_channel_mic/src/main.c     |  2 +-
 .../audio_4_channel_mic/src/usb_descriptors.c |  4 +--
 examples/device/audio_test/CMakeLists.txt     |  3 +++
 examples/device/audio_test/src/main.c         |  2 +-
 .../device/audio_test/src/usb_descriptors.c   |  4 +--
 examples/device/board_test/CMakeLists.txt     |  3 +++
 examples/device/cdc_dual_ports/CMakeLists.txt |  3 +++
 .../cdc_dual_ports/src/usb_descriptors.c      |  4 +--
 examples/device/cdc_msc/CMakeLists.txt        |  3 +++
 .../cdc_msc_freertos/src/usb_descriptors.c    |  4 +--
 examples/device/dfu/CMakeLists.txt            |  5 +++-
 examples/device/dfu/src/usb_descriptors.c     |  2 +-
 examples/device/dfu_runtime/CMakeLists.txt    |  3 +++
 .../device/dfu_runtime/src/usb_descriptors.c  |  4 +--
 .../dynamic_configuration/CMakeLists.txt      |  3 +++
 .../device/dynamic_configuration/src/main.c   |  2 +-
 .../dynamic_configuration/src/msc_disk.c      |  6 ++---
 .../src/usb_descriptors.c                     |  4 +--
 .../device/hid_boot_interface/CMakeLists.txt  |  3 +++
 .../hid_boot_interface/src/usb_descriptors.c  |  4 +--
 examples/device/hid_composite/CMakeLists.txt  |  3 +++
 .../hid_composite/src/usb_descriptors.c       |  4 +--
 .../src/usb_descriptors.c                     |  4 +--
 .../device/hid_generic_inout/CMakeLists.txt   |  3 +++
 .../hid_generic_inout/src/usb_descriptors.c   |  4 +--
 .../hid_multiple_interface/CMakeLists.txt     |  3 +++
 .../src/usb_descriptors.c                     |  4 +--
 examples/device/midi_test/CMakeLists.txt      |  3 +++
 .../device/midi_test/src/usb_descriptors.c    |  4 +--
 examples/device/msc_dual_lun/CMakeLists.txt   |  3 +++
 .../device/msc_dual_lun/src/usb_descriptors.c |  4 +--
 .../device/net_lwip_webserver/CMakeLists.txt  |  3 +++
 .../net_lwip_webserver/src/usb_descriptors.c  |  4 +--
 examples/device/uac2_headset/CMakeLists.txt   |  3 +++
 .../device/uac2_headset/src/usb_descriptors.c |  2 +-
 examples/device/usbtmc/CMakeLists.txt         |  3 +++
 examples/device/usbtmc/src/usb_descriptors.c  |  2 +-
 examples/device/video_capture/CMakeLists.txt  |  3 +++
 .../video_capture/src/usb_descriptors.c       |  4 +--
 examples/device/webusb_serial/CMakeLists.txt  |  3 +++
 .../webusb_serial/src/usb_descriptors.c       |  4 +--
 .../src/usb_descriptors.c                     |  2 +-
 examples/example.cmake                        | 25 +++++++++++++++++++
 hw/bsp/rp2040/family.c                        |  6 ++++-
 src/class/audio/audio_device.c                |  2 +-
 src/class/hid/hid_device.c                    |  5 ++--
 src/class/midi/midi_device.c                  | 12 ++++-----
 48 files changed, 140 insertions(+), 53 deletions(-)
 create mode 100644 examples/example.cmake

diff --git a/examples/device/audio_4_channel_mic/CMakeLists.txt b/examples/device/audio_4_channel_mic/CMakeLists.txt
index f6e10e2ea..e6ce2813e 100644
--- a/examples/device/audio_4_channel_mic/CMakeLists.txt
+++ b/examples/device/audio_4_channel_mic/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
 )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 9c94edd49..a6af5fd19 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -221,7 +221,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
         // Request uses format layout 2
         TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_2_t));
 
-        volume[channelNum] = ((audio_control_cur_2_t*) pBuff)->bCur;
+        volume[channelNum] = (uint16_t) ((audio_control_cur_2_t*) pBuff)->bCur;
 
         TU_LOG2("    Set Volume: %d dB of channel: %u\r\n", volume[channelNum], channelNum);
       return true;
diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index 93ae2ea47..8929f3057 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -149,7 +149,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     for(uint8_t i=0; i<chr_count; i++)
@@ -159,7 +159,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt
index cb321f9a8..416b91665 100644
--- a/examples/device/audio_test/CMakeLists.txt
+++ b/examples/device/audio_test/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
 )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index 51f55b772..d0849c7ac 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -222,7 +222,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
         // Request uses format layout 2
         TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_2_t));
 
-        volume[channelNum] = ((audio_control_cur_2_t*) pBuff)->bCur;
+        volume[channelNum] = (uint16_t) ((audio_control_cur_2_t*) pBuff)->bCur;
 
         TU_LOG2("    Set Volume: %d dB of channel: %u\r\n", volume[channelNum], channelNum);
       return true;
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index 09b2a2d45..da3e203d7 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -149,7 +149,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     for(uint8_t i=0; i<chr_count; i++)
@@ -159,7 +159,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index 37113578e..ac530a928 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -36,6 +36,9 @@ else()
           ${CMAKE_CURRENT_SOURCE_DIR}/src
           )
 
+  # Example common such as compiler warnings
+  include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
   # Configure compilation flags and libraries for the example... see the corresponding function
   # in hw/bsp/FAMILY/family.cmake for details.
   family_configure_device_example(${PROJECT})
diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt
index abc4d91da..438635958 100644
--- a/examples/device/cdc_dual_ports/CMakeLists.txt
+++ b/examples/device/cdc_dual_ports/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index aa400d486..cda1b63b6 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -236,7 +236,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -247,7 +247,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index fa6e83b7e..04c7c1b26 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -24,6 +24,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
index 9585822a3..30a712275 100644
--- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c
+++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
@@ -247,7 +247,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -258,7 +258,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/dfu/CMakeLists.txt b/examples/device/dfu/CMakeLists.txt
index abc4d91da..121ab3852 100644
--- a/examples/device/dfu/CMakeLists.txt
+++ b/examples/device/dfu/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 350334aa5..51a0d09f5 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -152,7 +152,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) {
       chr_count = 31;
     }
diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt
index abc4d91da..438635958 100644
--- a/examples/device/dfu_runtime/CMakeLists.txt
+++ b/examples/device/dfu_runtime/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/dfu_runtime/src/usb_descriptors.c b/examples/device/dfu_runtime/src/usb_descriptors.c
index 060943289..1b0a60551 100644
--- a/examples/device/dfu_runtime/src/usb_descriptors.c
+++ b/examples/device/dfu_runtime/src/usb_descriptors.c
@@ -147,7 +147,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) {
       chr_count = 31;
     }
@@ -160,7 +160,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t)((((uint16_t)TUSB_DESC_STRING) << 8 ) | (2u*chr_count + 2u));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt
index fa6e83b7e..04c7c1b26 100644
--- a/examples/device/dynamic_configuration/CMakeLists.txt
+++ b/examples/device/dynamic_configuration/CMakeLists.txt
@@ -24,6 +24,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index 95f8b8286..33a603343 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -181,7 +181,7 @@ void midi_task(void)
   start_ms += 286;
 
   // Previous positions in the note sequence.
-  int previous = note_pos - 1;
+  int previous = (int) (note_pos - 1);
 
   // If we currently are at position 0, set the
   // previous position to the last note in the sequence.
diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c
index a895f4738..e8cb03fdd 100644
--- a/examples/device/dynamic_configuration/src/msc_disk.c
+++ b/examples/device/dynamic_configuration/src/msc_disk.c
@@ -184,7 +184,7 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
   uint8_t const* addr = msc_disk[lba] + offset;
   memcpy(buffer, addr, bufsize);
 
-  return bufsize;
+  return (int32_t) bufsize;
 }
 
 // Callback invoked when received WRITE10 command.
@@ -203,7 +203,7 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
   (void) lba; (void) offset; (void) buffer;
 #endif
 
-  return bufsize;
+  return (int32_t) bufsize;
 }
 
 // Callback invoked when received an SCSI command not in built-in list below
@@ -237,7 +237,7 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
   {
     if(in_xfer)
     {
-      memcpy(buffer, response, resplen);
+      memcpy(buffer, response, (size_t) resplen);
     }else
     {
       // SCSI output
diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index b88f20163..457f774d0 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -226,7 +226,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -237,7 +237,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_boot_interface/CMakeLists.txt b/examples/device/hid_boot_interface/CMakeLists.txt
index abc4d91da..438635958 100644
--- a/examples/device/hid_boot_interface/CMakeLists.txt
+++ b/examples/device/hid_boot_interface/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.c b/examples/device/hid_boot_interface/src/usb_descriptors.c
index 3fa48d98d..a0d7e9f15 100644
--- a/examples/device/hid_boot_interface/src/usb_descriptors.c
+++ b/examples/device/hid_boot_interface/src/usb_descriptors.c
@@ -163,7 +163,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -174,7 +174,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt
index abc4d91da..438635958 100644
--- a/examples/device/hid_composite/CMakeLists.txt
+++ b/examples/device/hid_composite/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/hid_composite/src/usb_descriptors.c b/examples/device/hid_composite/src/usb_descriptors.c
index e760b20ba..2988baee2 100644
--- a/examples/device/hid_composite/src/usb_descriptors.c
+++ b/examples/device/hid_composite/src/usb_descriptors.c
@@ -210,7 +210,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -221,7 +221,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.c b/examples/device/hid_composite_freertos/src/usb_descriptors.c
index 791813fdf..4df12d3db 100644
--- a/examples/device/hid_composite_freertos/src/usb_descriptors.c
+++ b/examples/device/hid_composite_freertos/src/usb_descriptors.c
@@ -208,7 +208,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -219,7 +219,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt
index abc4d91da..438635958 100644
--- a/examples/device/hid_generic_inout/CMakeLists.txt
+++ b/examples/device/hid_generic_inout/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/hid_generic_inout/src/usb_descriptors.c b/examples/device/hid_generic_inout/src/usb_descriptors.c
index 5dabf42a3..c2b4792c8 100644
--- a/examples/device/hid_generic_inout/src/usb_descriptors.c
+++ b/examples/device/hid_generic_inout/src/usb_descriptors.c
@@ -153,7 +153,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -164,7 +164,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt
index abc4d91da..438635958 100644
--- a/examples/device/hid_multiple_interface/CMakeLists.txt
+++ b/examples/device/hid_multiple_interface/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/hid_multiple_interface/src/usb_descriptors.c b/examples/device/hid_multiple_interface/src/usb_descriptors.c
index 9eef21504..42471a961 100644
--- a/examples/device/hid_multiple_interface/src/usb_descriptors.c
+++ b/examples/device/hid_multiple_interface/src/usb_descriptors.c
@@ -171,7 +171,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -182,7 +182,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt
index abc4d91da..438635958 100644
--- a/examples/device/midi_test/CMakeLists.txt
+++ b/examples/device/midi_test/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c
index 8444237c6..c84a873b1 100644
--- a/examples/device/midi_test/src/usb_descriptors.c
+++ b/examples/device/midi_test/src/usb_descriptors.c
@@ -166,7 +166,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -177,7 +177,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt
index 9e834ae21..518eac3ad 100644
--- a/examples/device/msc_dual_lun/CMakeLists.txt
+++ b/examples/device/msc_dual_lun/CMakeLists.txt
@@ -24,6 +24,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c
index 2afd391af..68a671c91 100644
--- a/examples/device/msc_dual_lun/src/usb_descriptors.c
+++ b/examples/device/msc_dual_lun/src/usb_descriptors.c
@@ -168,7 +168,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -179,7 +179,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 8e3f0f5a8..5bb091a4f 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -69,6 +69,9 @@ if (EXISTS ${TOP}/lib/lwip/src)
             ${TOP}/lib/networking/rndis_reports.c
             )
 
+    # Example common such as compiler warnings
+    include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
     # Configure compilation flags and libraries for the example... see the corresponding function
     # in hw/bsp/FAMILY/family.cmake for details.
     family_configure_device_example(${PROJECT})
diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c
index 2b4b2a0c3..bee51790a 100644
--- a/examples/device/net_lwip_webserver/src/usb_descriptors.c
+++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c
@@ -231,7 +231,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > (TU_ARRAY_SIZE(_desc_str) - 1)) chr_count = TU_ARRAY_SIZE(_desc_str) - 1;
 
     // Convert ASCII string into UTF-16
@@ -242,7 +242,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt
index abc4d91da..438635958 100644
--- a/examples/device/uac2_headset/CMakeLists.txt
+++ b/examples/device/uac2_headset/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 9e97845b8..a2d6368bf 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -155,7 +155,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if (chr_count > 31) chr_count = 31;
 
     for (uint8_t i = 0; i < chr_count; i++)
diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt
index c49603c26..74f81b24f 100644
--- a/examples/device/usbtmc/CMakeLists.txt
+++ b/examples/device/usbtmc/CMakeLists.txt
@@ -24,6 +24,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/usbtmc/src/usb_descriptors.c b/examples/device/usbtmc/src/usb_descriptors.c
index 423482634..770a97436 100644
--- a/examples/device/usbtmc/src/usb_descriptors.c
+++ b/examples/device/usbtmc/src/usb_descriptors.c
@@ -175,7 +175,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) {
       chr_count = 31;
     }
diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt
index cb321f9a8..416b91665 100644
--- a/examples/device/video_capture/CMakeLists.txt
+++ b/examples/device/video_capture/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
 )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index da8ec8e89..5c97f4fe1 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -149,7 +149,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -160,7 +160,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt
index abc4d91da..438635958 100644
--- a/examples/device/webusb_serial/CMakeLists.txt
+++ b/examples/device/webusb_serial/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c
index 93e802a90..cafe2c22b 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.c
+++ b/examples/device/webusb_serial/src/usb_descriptors.c
@@ -235,7 +235,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
     const char* str = string_desc_arr[index];
 
     // Cap at max char
-    chr_count = strlen(str);
+    chr_count = (uint8_t) strlen(str);
     if ( chr_count > 31 ) chr_count = 31;
 
     // Convert ASCII string into UTF-16
@@ -246,7 +246,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
index e55899f65..6b0a89127 100644
--- a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
+++ b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
@@ -259,7 +259,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2*chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/example.cmake b/examples/example.cmake
new file mode 100644
index 000000000..6bb82a56d
--- /dev/null
+++ b/examples/example.cmake
@@ -0,0 +1,25 @@
+target_compile_options(${PROJECT} PUBLIC
+        -Wall
+        -Wextra
+        -Werror
+        -Wfatal-errors
+        -Wdouble-promotion
+        #-Wstrict-prototypes
+        -Wstrict-overflow
+        #-Werror-implicit-function-declaration
+        -Wfloat-equal
+        #-Wundef
+        -Wshadow
+        -Wwrite-strings
+        -Wsign-compare
+        -Wmissing-format-attribute
+        -Wunreachable-code
+        -Wcast-align
+        -Wcast-function-type
+        -Wcast-qual
+        -Wnull-dereference
+        -Wuninitialized
+        -Wunused
+        -Wredundant-decls
+        -Wconversion
+        )
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 68c9e2d52..90e2192c0 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -53,7 +53,7 @@
 //
 // This doesn't work if others are trying to access flash at the same time,
 // e.g. XIP streamer, or the other core.
-bool __no_inline_not_in_flash_func(get_bootsel_button)() {
+bool __no_inline_not_in_flash_func(get_bootsel_button)(void) {
     const uint CS_PIN_INDEX = 1;
 
     // Must disable interrupts, as interrupt handlers may be in flash, and we
@@ -170,6 +170,8 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
+  (void) state;
+
 #ifdef LED_PIN
   gpio_put(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
 #endif
@@ -192,6 +194,7 @@ int board_uart_read(uint8_t* buf, int len)
   }
   return len;
 #else
+  (void) buf; (void) len;
   return 0;
 #endif
 }
@@ -205,6 +208,7 @@ int board_uart_write(void const * buf, int len)
   }
   return len;
 #else
+  (void) buf; (void) len;
   return 0;
 #endif
 }
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index dbd8ab54b..e13e4a46c 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1619,7 +1619,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
             // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
 #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
-            const uint16_t active_fifo_depth = (audio->tx_supp_ff_sz_max / audio->n_bytes_per_sampe_tx) * audio->n_bytes_per_sampe_tx;
+            const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / audio->n_bytes_per_sampe_tx) * audio->n_bytes_per_sampe_tx);
             for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
             {
               tu_fifo_config(&audio->tx_supp_ff[cnt], audio->tx_supp_ff[cnt].buffer, active_fifo_depth, 1, true);
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index cdf155e1c..d15d44838 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -187,7 +187,8 @@ uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint1
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass, 0);
 
   // len = interface + hid + n*endpoints
-  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
+  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
+                                       desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
   TU_ASSERT(max_len >= drv_len, 0);
 
   // Find available interface
@@ -408,7 +409,7 @@ bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   // Received report
   else if (ep_addr == p_hid->ep_out)
   {
-    tud_hid_set_report_cb(instance, 0, HID_REPORT_TYPE_INVALID, p_hid->epout_buf, xferred_bytes);
+    tud_hid_set_report_cb(instance, 0, HID_REPORT_TYPE_INVALID, p_hid->epout_buf, (uint16_t) xferred_bytes);
     TU_ASSERT(usbd_edpt_xfer(rhport, p_hid->ep_out, p_hid->epout_buf, sizeof(p_hid->epout_buf)));
   }
 
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 28e6a92d2..de41706e8 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -127,7 +127,7 @@ uint32_t tud_midi_n_available(uint8_t itf, uint8_t cable_num)
   midid_stream_t const* stream = &midi->stream_read;
 
   // when using with packet API stream total & index are both zero
-  return tu_fifo_count(&midi->rx_ff) + (stream->total - stream->index);
+  return tu_fifo_count(&midi->rx_ff) + (uint8_t) (stream->total - stream->index);
 }
 
 uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, uint32_t bufsize)
@@ -179,7 +179,7 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, ui
     }
 
     // Copy data up to bufsize
-    uint32_t const count = tu_min32(stream->total - stream->index, bufsize);
+    uint8_t const count = (uint8_t) tu_min32(stream->total - stream->index, bufsize);
 
     // Skip the header (1st byte) in the buffer
     memcpy(buf8, stream->buffer + 1 + stream->index, count);
@@ -276,13 +276,13 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
       else if ( (msg >= 0x8 && msg <= 0xB) || msg == 0xE )
       {
         // Channel Voice Messages
-        stream->buffer[0] = (cable_num << 4) | msg;
+        stream->buffer[0] = (uint8_t) ((cable_num << 4) | msg);
         stream->total = 4;
       }
       else if ( msg == 0xC || msg == 0xD)
       {
         // Channel Voice Messages, two-byte variants (Program Change and Channel Pressure)
-        stream->buffer[0] = (cable_num << 4) | msg;
+        stream->buffer[0] = (uint8_t) ((cable_num << 4) | msg);
         stream->total = 3;
       }
       else if ( msg == 0xf )
@@ -312,7 +312,7 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
       else
       {
         // Pack individual bytes if we don't support packing them into words.
-        stream->buffer[0] = cable_num << 4 | 0xf;
+        stream->buffer[0] = (uint8_t) (cable_num << 4 | 0xf);
         stream->buffer[2] = 0;
         stream->buffer[3] = 0;
         stream->index = 2;
@@ -513,7 +513,7 @@ bool midid_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32
   // receive new data
   if ( ep_addr == p_midi->ep_out )
   {
-    tu_fifo_write_n(&p_midi->rx_ff, p_midi->epout_buf, xferred_bytes);
+    tu_fifo_write_n(&p_midi->rx_ff, p_midi->epout_buf, (uint16_t) xferred_bytes);
 
     // invoke receive callback if available
     if (tud_midi_rx_cb) tud_midi_rx_cb(itf);

From 0b3503cb33e6a269e573a75b6ed67d69aee12dbb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 16 Jun 2022 12:01:19 +0700
Subject: [PATCH 1084/2085] clean up usbd log level

---
 examples/host/bare_api/src/main.c |  4 +-
 src/device/usbd.c                 | 68 +++++++++++++++----------------
 2 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 2cc05d34d..9ccd856d4 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -84,8 +84,8 @@ void tuh_mount_cb (uint8_t daddr)
 {
   printf("Device attached, address = %d\r\n", daddr);
 
-  // Get Device Descriptor sync API
-  // TODO: invoking control trannsfer now has issue with mounting hub with multiple devices attached, fix later
+  // Get Device Descriptor
+  // TODO: invoking control transfer now has issue with mounting hub with multiple devices attached, fix later
   tuh_descriptor_get_device(daddr, &desc_device, 18, print_device_descriptor, 0);
 }
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 1806281ff..59d0e86e3 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -318,7 +318,7 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
     usbd_class_driver_t const * driver = get_driver(i);
     if ( driver->control_xfer_cb == callback )
     {
-      TU_LOG2("  %s control complete\r\n", driver->name);
+      TU_LOG(USBD_DBG, "  %s control complete\r\n", driver->name);
       return;
     }
   }
@@ -384,8 +384,8 @@ bool tud_init (uint8_t rhport)
   // skip if already initialized
   if ( tud_inited() ) return true;
 
-  TU_LOG2("USBD init on controller %u\r\n", rhport);
-  TU_LOG2_INT(sizeof(usbd_device_t));
+  TU_LOG(USBD_DBG, "USBD init on controller %u\r\n", rhport);
+  TU_LOG_INT(USBD_DBG, sizeof(usbd_device_t));
 
   tu_varclr(&_usbd_dev);
 
@@ -409,7 +409,7 @@ bool tud_init (uint8_t rhport)
   for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
   {
     usbd_class_driver_t const * driver = get_driver(i);
-    TU_LOG2("%s init\r\n", driver->name);
+    TU_LOG(USBD_DBG, "%s init\r\n", driver->name);
     driver->init();
   }
 
@@ -480,20 +480,20 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
     if ( !osal_queue_receive(_usbd_q, &event, timeout_ms) ) return;
 
 #if CFG_TUSB_DEBUG >= 2
-    if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG2("\r\n"); // extra line for setup
-    TU_LOG2("USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED");
+    if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG(USBD_DBG, "\r\n"); // extra line for setup
+    TU_LOG(USBD_DBG, "USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED");
 #endif
 
     switch ( event.event_id )
     {
       case DCD_EVENT_BUS_RESET:
-        TU_LOG2(": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]);
+        TU_LOG(USBD_DBG, ": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]);
         usbd_reset(event.rhport);
         _usbd_dev.speed = event.bus_reset.speed;
       break;
 
       case DCD_EVENT_UNPLUGGED:
-        TU_LOG2("\r\n");
+        TU_LOG(USBD_DBG, "\r\n");
         usbd_reset(event.rhport);
 
         // invoke callback
@@ -501,8 +501,8 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
       break;
 
       case DCD_EVENT_SETUP_RECEIVED:
-        TU_LOG2_VAR(&event.setup_received);
-        TU_LOG2("\r\n");
+        TU_LOG_VAR(USBD_DBG, &event.setup_received);
+        TU_LOG(USBD_DBG, "\r\n");
 
         // Mark as connected after receiving 1st setup packet.
         // But it is easier to set it every time instead of wasting time to check then set
@@ -517,7 +517,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         // Process control request
         if ( !process_control_request(event.rhport, &event.setup_received) )
         {
-          TU_LOG2("  Stall EP0\r\n");
+          TU_LOG(USBD_DBG, "  Stall EP0\r\n");
           // Failed -> stall both control endpoint IN and OUT
           dcd_edpt_stall(event.rhport, 0);
           dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK);
@@ -531,7 +531,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         uint8_t const epnum   = tu_edpt_number(ep_addr);
         uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
-        TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
+        TU_LOG(USBD_DBG, "on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
 
         _usbd_dev.ep_status[epnum][ep_dir].busy = false;
         _usbd_dev.ep_status[epnum][ep_dir].claimed = 0;
@@ -545,7 +545,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
           usbd_class_driver_t const * driver = get_driver( _usbd_dev.ep2drv[epnum][ep_dir] );
           TU_ASSERT(driver, );
 
-          TU_LOG2("  %s xfer callback\r\n", driver->name);
+          TU_LOG(USBD_DBG, "  %s xfer callback\r\n", driver->name);
           driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len);
         }
       }
@@ -557,27 +557,27 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected
         if ( _usbd_dev.connected )
         {
-          TU_LOG2(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
+          TU_LOG(USBD_DBG, ": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
           if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
         }else
         {
-          TU_LOG2(" Skipped\r\n");
+          TU_LOG(USBD_DBG, " Skipped\r\n");
         }
       break;
 
       case DCD_EVENT_RESUME:
         if ( _usbd_dev.connected )
         {
-          TU_LOG2("\r\n");
+          TU_LOG(USBD_DBG, "\r\n");
           if (tud_resume_cb) tud_resume_cb();
         }else
         {
-          TU_LOG2(" Skipped\r\n");
+          TU_LOG(USBD_DBG, " Skipped\r\n");
         }
       break;
 
       case USBD_EVENT_FUNC_CALL:
-        TU_LOG2("\r\n");
+        TU_LOG(USBD_DBG, "\r\n");
         if ( event.func_call.func ) event.func_call.func(event.func_call.param);
       break;
 
@@ -602,7 +602,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
 static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request)
 {
   usbd_control_set_complete_callback(driver->control_xfer_cb);
-  TU_LOG2("  %s control request\r\n", driver->name);
+  TU_LOG(USBD_DBG, "  %s control request\r\n", driver->name);
   return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request);
 }
 
@@ -626,8 +626,8 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
 #if CFG_TUSB_DEBUG >= 2
   if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME)
   {
-    TU_LOG2("  %s", tu_str_std_request[p_request->bRequest]);
-    if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG2("\r\n");
+    TU_LOG(USBD_DBG, "  %s", tu_str_std_request[p_request->bRequest]);
+    if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG(USBD_DBG, "\r\n");
   }
 #endif
 
@@ -905,7 +905,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
       if ( (sizeof(tusb_desc_interface_t) <= drv_len)  && (drv_len <= remaining_len) )
       {
         // Open successfully
-        TU_LOG2("  %s opened\r\n", driver->name);
+        TU_LOG(USBD_DBG, "  %s opened\r\n", driver->name);
 
         // Some drivers use 2 or more interfaces but may not have IAD e.g MIDI (always) or
         // BTH (even CDC) with class in device descriptor (single interface)
@@ -964,7 +964,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
   {
     case TUSB_DESC_DEVICE:
     {
-      TU_LOG2(" Device\r\n");
+      TU_LOG(USBD_DBG, " Device\r\n");
 
       void* desc_device = (void*) (uintptr_t) tud_descriptor_device_cb();
 
@@ -988,7 +988,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
     case TUSB_DESC_BOS:
     {
-      TU_LOG2(" BOS\r\n");
+      TU_LOG(USBD_DBG, " BOS\r\n");
 
       // requested by host if USB > 2.0 ( i.e 2.1 or 3.x )
       if (!tud_descriptor_bos_cb) return false;
@@ -1010,12 +1010,12 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
       if ( desc_type == TUSB_DESC_CONFIGURATION )
       {
-        TU_LOG2(" Configuration[%u]\r\n", desc_index);
+        TU_LOG(USBD_DBG, " Configuration[%u]\r\n", desc_index);
         desc_config = (uintptr_t) tud_descriptor_configuration_cb(desc_index);
       }else
       {
         // Host only request this after getting Device Qualifier descriptor
-        TU_LOG2(" Other Speed Configuration\r\n");
+        TU_LOG(USBD_DBG, " Other Speed Configuration\r\n");
         TU_VERIFY( tud_descriptor_other_speed_configuration_cb );
         desc_config = (uintptr_t) tud_descriptor_other_speed_configuration_cb(desc_index);
       }
@@ -1031,7 +1031,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
     case TUSB_DESC_STRING:
     {
-      TU_LOG2(" String[%u]\r\n", desc_index);
+      TU_LOG(USBD_DBG, " String[%u]\r\n", desc_index);
 
       // String Descriptor always uses the desc set from user
       uint8_t const* desc_str = (uint8_t const*) tud_descriptor_string_cb(desc_index, tu_le16toh(p_request->wIndex));
@@ -1044,7 +1044,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
     case TUSB_DESC_DEVICE_QUALIFIER:
     {
-      TU_LOG2(" Device Qualifier\r\n");
+      TU_LOG(USBD_DBG, " Device Qualifier\r\n");
 
       TU_VERIFY( tud_descriptor_device_qualifier_cb );
 
@@ -1237,7 +1237,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   // TODO skip ready() check for now since enumeration also use this API
   // TU_VERIFY(tud_ready());
 
-  TU_LOG2("  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
+  TU_LOG(USBD_DBG, "  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
@@ -1254,7 +1254,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     // DCD error, mark endpoint as ready to allow next transfer
     _usbd_dev.ep_status[epnum][dir].busy = false;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
-    TU_LOG2("FAILED\r\n");
+    TU_LOG(USBD_DBG, "FAILED\r\n");
     TU_BREAKPOINT();
     return false;
   }
@@ -1271,7 +1271,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  TU_LOG2("  Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes);
+  TU_LOG(USBD_DBG, "  Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
@@ -1282,14 +1282,14 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 
   if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes))
   {
-    TU_LOG2("OK\r\n");
+    TU_LOG(USBD_DBG, "OK\r\n");
     return true;
   }else
   {
     // DCD error, mark endpoint as ready to allow next transfer
     _usbd_dev.ep_status[epnum][dir].busy = false;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
-    TU_LOG2("failed\r\n");
+    TU_LOG(USBD_DBG, "failed\r\n");
     TU_BREAKPOINT();
     return false;
   }
@@ -1360,7 +1360,7 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   rhport = _usbd_rhport;
 
   TU_ASSERT(dcd_edpt_close, /**/);
-  TU_LOG2("  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
+  TU_LOG(USBD_DBG, "  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);

From 556b5d5044bd02e89d6b6c6f21e95d46f5fcdfc1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 27 Jun 2022 12:22:36 +0700
Subject: [PATCH 1085/2085] change report len in hid API from uint8_t to
 uint16_t

since HS interrupt endpoint can be up to 1024, 8-bit is not enough.
affected APIs are:
- tud_hid_n_report() / tud_hid_report()
- tud_hid_report_complete_cb()
---
 examples/device/hid_boot_interface/src/main.c     | 2 +-
 examples/device/hid_composite/src/main.c          | 2 +-
 examples/device/hid_composite_freertos/src/main.c | 2 +-
 src/class/hid/hid_device.c                        | 8 ++++----
 src/class/hid/hid_device.h                        | 8 ++++----
 5 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 21cdb383d..1958d614d 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -181,7 +181,7 @@ void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
 {
   (void) instance;
   (void) report;
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index bc2347ab8..3c088b7c2 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -225,7 +225,7 @@ void hid_task(void)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
 {
   (void) instance;
   (void) len;
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 1030f3d05..ea8d917fe 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -294,7 +294,7 @@ void hid_task(void* param)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
 {
   (void) instance;
   (void) len;
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index cdf155e1c..210050858 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -81,7 +81,7 @@ bool tud_hid_n_ready(uint8_t instance)
   return tud_ready() && (ep_in != 0) && !usbd_edpt_busy(rhport, ep_in);
 }
 
-bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, uint8_t len)
+bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, uint16_t len)
 {
   uint8_t const rhport = 0;
   hidd_interface_t * p_hid = &_hidd_itf[instance];
@@ -92,7 +92,7 @@ bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, u
   // prepare data
   if (report_id)
   {
-    len = tu_min8(len, CFG_TUD_HID_EP_BUFSIZE-1);
+    len = tu_min16(len, CFG_TUD_HID_EP_BUFSIZE-1);
 
     p_hid->epin_buf[0] = report_id;
     memcpy(p_hid->epin_buf+1, report, len);
@@ -100,7 +100,7 @@ bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, u
   }else
   {
     // If report id = 0, skip ID field
-    len = tu_min8(len, CFG_TUD_HID_EP_BUFSIZE);
+    len = tu_min16(len, CFG_TUD_HID_EP_BUFSIZE);
     memcpy(p_hid->epin_buf, report, len);
   }
 
@@ -402,7 +402,7 @@ bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   {
     if (tud_hid_report_complete_cb)
     {
-      tud_hid_report_complete_cb(instance, p_hid->epin_buf, (uint8_t) xferred_bytes);
+      tud_hid_report_complete_cb(instance, p_hid->epin_buf, (uint16_t) xferred_bytes);
     }
   }
   // Received report
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 078b67349..3714d2769 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -62,7 +62,7 @@ uint8_t tud_hid_n_interface_protocol(uint8_t instance);
 uint8_t tud_hid_n_get_protocol(uint8_t instance);
 
 // Send report to host
-bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, uint8_t len);
+bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, uint16_t len);
 
 // KEYBOARD: convenient helper to send keyboard report if application
 // use template layout report as defined by hid_keyboard_report_t
@@ -82,7 +82,7 @@ bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id, int8_t x, int
 static inline bool    tud_hid_ready(void);
 static inline uint8_t tud_hid_interface_protocol(void);
 static inline uint8_t tud_hid_get_protocol(void);
-static inline bool    tud_hid_report(uint8_t report_id, void const* report, uint8_t len);
+static inline bool    tud_hid_report(uint8_t report_id, void const* report, uint16_t len);
 static inline bool    tud_hid_keyboard_report(uint8_t report_id, uint8_t modifier, uint8_t keycode[6]);
 static inline bool    tud_hid_mouse_report(uint8_t report_id, uint8_t buttons, int8_t x, int8_t y, int8_t vertical, int8_t horizontal);
 static inline bool    tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons);
@@ -116,7 +116,7 @@ TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate);
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint8_t len);
+TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len);
 
 
 //--------------------------------------------------------------------+
@@ -137,7 +137,7 @@ static inline uint8_t tud_hid_get_protocol(void)
   return tud_hid_n_get_protocol(0);
 }
 
-static inline bool tud_hid_report(uint8_t report_id, void const* report, uint8_t len)
+static inline bool tud_hid_report(uint8_t report_id, void const* report, uint16_t len)
 {
   return tud_hid_n_report(0, report_id, report, len);
 }

From 6522a8150e22d47bacabd2f1f027452db2254984 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 27 Jun 2022 13:48:47 +0700
Subject: [PATCH 1086/2085] fix all device examples warnings

---
 examples/device/midi_test/src/main.c          |  2 +-
 .../device/msc_dual_lun/src/msc_disk_dual.c   |  6 +--
 examples/device/uac2_headset/src/main.c       | 16 ++++----
 .../device/uac2_headset/src/usb_descriptors.c |  2 +-
 src/class/audio/audio_device.c                | 12 ++++--
 src/class/vendor/vendor_device.c              | 10 ++---
 src/class/video/video_device.c                | 38 ++++++++++---------
 7 files changed, 47 insertions(+), 39 deletions(-)

diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index b47d1af76..3310348bd 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -140,7 +140,7 @@ void midi_task(void)
   start_ms += 286;
 
   // Previous positions in the note sequence.
-  int previous = note_pos - 1;
+  int previous = (int) (note_pos - 1);
 
   // If we currently are at position 0, set the
   // previous position to the last note in the sequence.
diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c
index 37446ebc3..2b773b43b 100644
--- a/examples/device/msc_dual_lun/src/msc_disk_dual.c
+++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c
@@ -277,7 +277,7 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
   uint8_t const* addr = (lun ? msc_disk1[lba] : msc_disk0[lba]) + offset;
   memcpy(buffer, addr, bufsize);
 
-  return bufsize;
+  return (int32_t) bufsize;
 }
 
 bool tud_msc_is_writable_cb (uint8_t lun)
@@ -305,7 +305,7 @@ int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t*
   (void) lun; (void) lba; (void) offset; (void) buffer;
 #endif
 
-  return bufsize;
+  return (int32_t) bufsize;
 }
 
 // Callback invoked when received an SCSI command not in built-in list below
@@ -339,7 +339,7 @@ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer,
   {
     if(in_xfer)
     {
-      memcpy(buffer, response, resplen);
+      memcpy(buffer, response, (size_t) resplen);
     }else
     {
       // SCSI output
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index a8d204eaa..003dc2a74 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -159,7 +159,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
     {
       TU_LOG1("Clock get current freq %lu\r\n", current_sample_rate);
 
-      audio_control_cur_4_t curf = { tu_htole32(current_sample_rate) };
+      audio_control_cur_4_t curf = { (int32_t) tu_htole32(current_sample_rate) };
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
     }
     else if (request->bRequest == AUDIO_CS_REQ_RANGE)
@@ -171,8 +171,8 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
       TU_LOG1("Clock get %d freq ranges\r\n", N_SAMPLE_RATES);
       for(uint8_t i = 0; i < N_SAMPLE_RATES; i++)
       {
-        rangef.subrange[i].bMin = sample_rates[i];
-        rangef.subrange[i].bMax = sample_rates[i];
+        rangef.subrange[i].bMin = (int32_t) sample_rates[i];
+        rangef.subrange[i].bMax = (int32_t) sample_rates[i];
         rangef.subrange[i].bRes = 0;
         TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
       }
@@ -204,7 +204,7 @@ static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t
   {
     TU_VERIFY(request->wLength == sizeof(audio_control_cur_4_t));
 
-    current_sample_rate = ((audio_control_cur_4_t const *)buf)->bCur;
+    current_sample_rate = (uint32_t) ((audio_control_cur_4_t const *)buf)->bCur;
 
     TU_LOG1("Clock set current freq: %ld\r\n", current_sample_rate);
 
@@ -403,9 +403,9 @@ void audio_task(void)
         // Combine two channels into one
         int32_t left = *src++;
         int32_t right = *src++;
-        *dst++ = (left >> 1) + (right >> 1);
+        *dst++ = (int16_t) ((left >> 1) + (right >> 1));
       }
-      tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
+      tud_audio_write((uint8_t *)mic_buf, (uint16_t) (spk_data_size / 2));
       spk_data_size = 0;
     }
     else if (current_resolution == 24)
@@ -418,9 +418,9 @@ void audio_task(void)
         // Combine two channels into one
         int32_t left = *src++;
         int32_t right = *src++;
-        *dst++ = ((left >> 1) + (right >> 1)) & 0xffffff00;
+        *dst++ = (int32_t) ((uint32_t) ((left >> 1) + (right >> 1)) & 0xffffff00ul);
       }
-      tud_audio_write((uint8_t *)mic_buf, spk_data_size / 2);
+      tud_audio_write((uint8_t *)mic_buf, (uint16_t) (spk_data_size / 2));
       spk_data_size = 0;
     }
   }
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index a2d6368bf..10f5cbd27 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -165,7 +165,7 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (TUSB_DESC_STRING << 8 ) | (2 * chr_count + 2);
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
 
   return _desc_str;
 }
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index e13e4a46c..6df68c559 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -537,7 +537,7 @@ tu_fifo_t* tud_audio_n_get_rx_support_ff(uint8_t func_id, uint8_t ff_idx)
 
 static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received)
 {
-  uint8_t idxItf;
+  uint8_t idxItf = 0;
   uint8_t const *dummy2;
   uint8_t idx_audio_fct = 0;
 
@@ -548,7 +548,10 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
   }
 
   // Call a weak callback here - a possibility for user to get informed an audio packet was received and data gets now loaded into EP FIFO (or decoded into support RX software FIFO)
-  if (tud_audio_rx_done_pre_read_cb) TU_VERIFY(tud_audio_rx_done_pre_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
+  if (tud_audio_rx_done_pre_read_cb)
+  {
+    TU_VERIFY(tud_audio_rx_done_pre_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
+  }
 
 #if CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_EP_OUT
 
@@ -602,7 +605,10 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
 #endif
 
   // Call a weak callback here - a possibility for user to get informed decoding was completed
-  if (tud_audio_rx_done_post_read_cb) TU_VERIFY(tud_audio_rx_done_post_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
+  if (tud_audio_rx_done_post_read_cb)
+  {
+    TU_VERIFY(tud_audio_rx_done_post_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf]));
+  }
 
   return true;
 }
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index c7dfa0062..3b81a108f 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -100,7 +100,7 @@ static void _prep_out_transaction (vendord_interface_t* p_itf)
 uint32_t tud_vendor_n_read (uint8_t itf, void* buffer, uint32_t bufsize)
 {
   vendord_interface_t* p_itf = &_vendord_itf[itf];
-  uint32_t num_read = tu_fifo_read_n(&p_itf->rx_ff, buffer, bufsize);
+  uint32_t num_read = tu_fifo_read_n(&p_itf->rx_ff, buffer, (uint16_t) bufsize);
   _prep_out_transaction(p_itf);
   return num_read;
 }
@@ -133,7 +133,7 @@ static uint16_t maybe_transmit(vendord_interface_t* p_itf)
 uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize)
 {
   vendord_interface_t* p_itf = &_vendord_itf[itf];
-  uint16_t ret = tu_fifo_write_n(&p_itf->tx_ff, buffer, bufsize);
+  uint16_t ret = tu_fifo_write_n(&p_itf->tx_ff, buffer, (uint16_t) bufsize);
   if (tu_fifo_count(&p_itf->tx_ff) >= CFG_TUD_VENDOR_EPSIZE) {
     maybe_transmit(p_itf);
   }
@@ -231,7 +231,7 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui
     if ( p_vendor->ep_in ) maybe_transmit(p_vendor);
   }
 
-  return (uintptr_t) p_desc - (uintptr_t) desc_itf;
+  return (uint16_t) ((uintptr_t) p_desc - (uintptr_t) desc_itf);
 }
 
 bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
@@ -252,7 +252,7 @@ bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
   if ( ep_addr == p_itf->ep_out )
   {
     // Receive new data
-    tu_fifo_write_n(&p_itf->rx_ff, p_itf->epout_buf, xferred_bytes);
+    tu_fifo_write_n(&p_itf->rx_ff, p_itf->epout_buf, (uint16_t) xferred_bytes);
 
     // Invoked callback if any
     if (tud_vendor_rx_cb) tud_vendor_rx_cb(itf);
@@ -261,7 +261,7 @@ bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
   }
   else if ( ep_addr == p_itf->ep_in )
   {
-    if (tud_vendor_tx_cb) tud_vendor_tx_cb(itf, xferred_bytes);
+    if (tud_vendor_tx_cb) tud_vendor_tx_cb(itf, (uint16_t) xferred_bytes);
     // Send complete, try to send more if possible
     maybe_transmit(p_itf);
   }
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 91718f205..7636db5fe 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -297,7 +297,7 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
 {
   tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
   uint_fast8_t fmtnum = param->bFormatIndex;
-  TU_ASSERT(fmtnum <= vs->stm.bNumFormats);
+  TU_ASSERT(vs && fmtnum <= vs->stm.bNumFormats);
   if (!fmtnum) {
     if (1 < vs->stm.bNumFormats) return true; /* Need to negotiate all variables. */
     fmtnum = 1;
@@ -393,6 +393,7 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
   uint_fast8_t frmnum = param->bFrameIndex;
   if (!frmnum) {
     tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
+    TU_ASSERT(vs);
     void const *end = _end_of_streaming_descriptor(vs);
     tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
     switch (request) {
@@ -407,15 +408,16 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
         break;
       default: return false;
     }
-    param->bFrameIndex = frmnum;
+    param->bFrameIndex = (uint8_t) frmnum;
     /* Set the parameters determined by the frame */
     tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
-    param->dwMaxVideoFrameSize = frm->wWidth * frm->wHeight * fmt->bBitsPerPixel / 8;
+    param->dwMaxVideoFrameSize = (uint32_t) (frm->wWidth * frm->wHeight * fmt->bBitsPerPixel / 8);
     return true;
   }
 
   if (!param->dwFrameInterval) {
     tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
+    TU_ASSERT(vs);
     void const *end = _end_of_streaming_descriptor(vs);
     tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
     tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
@@ -532,7 +534,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
     /* Open the notification endpoint */
     TU_ASSERT(usbd_edpt_open(rhport, notif));
   }
-  self->cur = (void const*)vc - beg;
+  self->cur = (uint16_t) ((void const*)vc - beg);
   return true;
 }
 
@@ -550,7 +552,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
   for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) {
     uint_fast16_t ofs_ep = stm->desc.ep[i];
     if (!ofs_ep) break;
-    uint_fast8_t  ep_adr = _desc_ep_addr(desc + ofs_ep);
+    uint8_t  ep_adr = _desc_ep_addr(desc + ofs_ep);
     usbd_edpt_close(rhport, ep_adr);
     stm->desc.ep[i] = 0;
     TU_LOG2("    close EP%02x\n", ep_adr);
@@ -567,7 +569,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
   TU_VERIFY(cur < end);
   uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints;
   TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep));
-  stm->desc.cur = cur - desc; /* Save the offset of the new settings */
+  stm->desc.cur = (uint16_t) (cur - desc); /* Save the offset of the new settings */
   if (!altnum) {
     /* initialize streaming settings */
     stm->max_payload_transfer_size = 0;
@@ -594,7 +596,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
       stm->max_payload_transfer_size = max_size;
     }
     TU_ASSERT(usbd_edpt_open(rhport, ep));
-    stm->desc.ep[i] = cur - desc;
+    stm->desc.ep[i] = (uint16_t) (cur - desc);
     TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
   }
   /* initialize payload header */
@@ -976,7 +978,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
 
   /* Find EP address */
   void const *desc = _videod_itf[stm->index_vc].beg;
-  uint_fast8_t ep_addr = 0;
+  uint8_t ep_addr = 0;
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
     uint_fast16_t ofs_ep = stm->desc.ep[i];
     if (!ofs_ep) continue;
@@ -985,7 +987,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
   }
   if (!ep_addr) return false;
 
-  TU_VERIFY( usbd_edpt_claim(0, ep_addr));
+  TU_VERIFY( usbd_edpt_claim(0, ep_addr) );
   /* update the packet header */
   tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
   hdr->FrameID   ^= 1;
@@ -994,7 +996,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
   stm->buffer     = (uint8_t*)buffer;
   stm->bufsize    = bufsize;
   uint_fast16_t pkt_len = _prepare_in_payload(stm);
-  TU_ASSERT( usbd_edpt_xfer(0, ep_addr, stm->ep_buf, pkt_len), 0);
+  TU_ASSERT( usbd_edpt_xfer(0, ep_addr, stm->ep_buf, (uint16_t) pkt_len), 0);
   return true;
 }
 
@@ -1034,7 +1036,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 
   /* Find available interface */
   videod_interface_t *self = NULL;
-  uint_fast8_t ctl_idx;
+  uint8_t ctl_idx;
   for (ctl_idx = 0; ctl_idx < CFG_TUD_VIDEO; ++ctl_idx) {
     if (_videod_itf[ctl_idx].beg) continue;
     self = &_videod_itf[ctl_idx];
@@ -1051,10 +1053,10 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   uint_fast8_t bInCollection   = vc->ctl.bInCollection;
   /* Find the end of the video interface descriptor */
   void const *cur = _next_desc_itf(itf_desc, end);
-  for (uint_fast8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) {
+  for (uint8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) {
     videod_streaming_interface_t *stm = NULL;
     /* find free streaming interface handle */
-    for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
+    for (uint8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
       if (_videod_streaming_itf[i].desc.beg) continue;
       stm = &_videod_streaming_itf[i];
       self->stm[stm_idx] = i;
@@ -1063,12 +1065,12 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
     TU_ASSERT(stm, 0);
     stm->index_vc = ctl_idx;
     stm->index_vs = stm_idx;
-    stm->desc.beg = (uintptr_t)cur - (uintptr_t)itf_desc;
+    stm->desc.beg = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
     cur = _next_desc_itf(cur, end);
-    stm->desc.end = (uintptr_t)cur - (uintptr_t)itf_desc;
+    stm->desc.end = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
   }
-  self->len = (uintptr_t)cur - (uintptr_t)itf_desc;
-  return (uintptr_t)cur - (uintptr_t)itf_desc;
+  self->len = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
+  return (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
 }
 
 // Invoked when a control transfer occurred on an interface of this class
@@ -1134,7 +1136,7 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     /* Claim the endpoint */
     TU_VERIFY( usbd_edpt_claim(rhport, ep_addr), 0);
     uint_fast16_t pkt_len = _prepare_in_payload(stm);
-    TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, pkt_len), 0);
+    TU_ASSERT( usbd_edpt_xfer(rhport, ep_addr, stm->ep_buf, (uint16_t) pkt_len), 0);
   } else {
     stm->buffer  = NULL;
     stm->bufsize = 0;

From a0ef4898906a5985deae11e5539a942885398ca1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 27 Jun 2022 17:11:24 +0700
Subject: [PATCH 1087/2085] fix all warnings with host rp2040

---
 .../host_hid_to_device_cdc/CMakeLists.txt     |   4 +
 .../dual/host_hid_to_device_cdc/src/main.c    |   6 +-
 examples/host/bare_api/CMakeLists.txt         |   3 +
 examples/host/bare_api/src/main.c             |  11 +-
 examples/host/cdc_msc_hid/CMakeLists.txt      |   3 +
 examples/host/hid_controller/CMakeLists.txt   |   3 +
 src/class/cdc/cdc_host.c                      |   8 +-
 src/class/hid/hid_host.c                      |   7 +-
 src/class/msc/msc_host.c                      |   8 +-
 src/host/usbh.c                               |   6 +-
 src/osal/osal_pico.h                          |   5 -
 src/portable/raspberrypi/rp2040/hcd_rp2040.c  | 111 ++++++++++--------
 12 files changed, 98 insertions(+), 77 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index ea4e087e3..cd6f16339 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -23,6 +23,10 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+# skip extra warnings since pio-usb still has some warnings to fix
+#include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_dual_usb_example(${PROJECT})
diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index 6a25a28da..bd7870274 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -160,7 +160,7 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
   char tempbuf[256];
   int count = sprintf(tempbuf, "[%04x:%04x][%u] HID Interface%u, Protocol = %s\r\n", vid, pid, dev_addr, instance, protocol_str[itf_protocol]);
 
-  tud_cdc_write(tempbuf, count);
+  tud_cdc_write(tempbuf, (uint32_t) count);
   tud_cdc_write_flush();
 
   // Receive report from boot keyboard & mouse only
@@ -179,7 +179,7 @@ void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
 {
   char tempbuf[256];
   int count = sprintf(tempbuf, "[%u] HID Interface%u is unmounted\r\n", dev_addr, instance);
-  tud_cdc_write(tempbuf, count);
+  tud_cdc_write(tempbuf, (uint32_t) count);
   tud_cdc_write_flush();
 }
 
@@ -251,7 +251,7 @@ static void process_mouse_report(uint8_t dev_addr, hid_mouse_report_t const * re
   char tempbuf[32];
   int count = sprintf(tempbuf, "[%u] %c%c%c %d %d %d\r\n", dev_addr, l, m, r, report->x, report->y, report->wheel);
 
-  tud_cdc_write(tempbuf, count);
+  tud_cdc_write(tempbuf, (uint32_t) count);
   tud_cdc_write_flush();
 }
 
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index bc04b01a7..98540ffb0 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -22,6 +22,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 9ccd856d4..51cab2de0 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -189,7 +189,7 @@ void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const*
     if( TUSB_DESC_INTERFACE != tu_desc_type(p_desc) ) return;
     tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
 
-    uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
+    uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end-p_desc));
 
     // probably corrupted descriptor
     if(drv_len < sizeof(tusb_desc_interface_t)) return;
@@ -244,7 +244,8 @@ void hid_report_received(tuh_xfer_t* xfer);
 void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
   // len = interface + hid + n*endpoints
-  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
+  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
+                                       desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
 
   // corrupted descriptor
   if (max_len < drv_len) return;
@@ -377,7 +378,7 @@ static void _convert_utf16le_to_utf8(const uint16_t *utf16, size_t utf16_len, ui
     for (size_t i = 0; i < utf16_len; i++) {
         uint16_t chr = utf16[i];
         if (chr < 0x80) {
-            *utf8++ = chr & 0xff;
+            *utf8++ = chr & 0xffu;
         } else if (chr < 0x800) {
             *utf8++ = (uint8_t)(0xC0 | (chr >> 6 & 0x1F));
             *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F));
@@ -405,12 +406,12 @@ static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
         }
         // TODO: Handle UTF-16 code points that take two entries.
     }
-    return total_bytes;
+    return (int) total_bytes;
 }
 
 static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
     size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
-    size_t utf8_len = _count_utf8_bytes(temp_buf + 1, utf16_len);
+    size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
     _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);
     ((uint8_t*) temp_buf)[utf8_len] = '\0';
 
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index c4a4d8e63..6990e957b 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -24,6 +24,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index 6153d399a..eefeb4a49 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -23,6 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# Example common such as compiler warnings
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 044085e81..ee824cb4e 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -105,7 +105,7 @@ bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool i
   uint8_t const ep_out = cdch_data[dev_addr-1].ep_out;
   if ( usbh_edpt_busy(dev_addr, ep_out) ) return false;
 
-  return usbh_edpt_xfer(dev_addr, ep_out, (void*)(uintptr_t) p_data, length);
+  return usbh_edpt_xfer(dev_addr, ep_out, (void*)(uintptr_t) p_data, (uint16_t) length);
 }
 
 bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify)
@@ -117,7 +117,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
   uint8_t const ep_in = cdch_data[dev_addr-1].ep_in;
   if ( usbh_edpt_busy(dev_addr, ep_in) ) return false;
 
-  return usbh_edpt_xfer(dev_addr, ep_in, p_buffer, length);
+  return usbh_edpt_xfer(dev_addr, ep_in, p_buffer, (uint16_t) length);
 }
 
 bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb)
@@ -133,8 +133,8 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xf
       .direction = TUSB_DIR_OUT
     },
     .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
-    .wValue   = (rts ? 2 : 0) | (dtr ? 1 : 0),
-    .wIndex   = p_cdc->itf_num,
+    .wValue   = tu_htole16((uint16_t) ((dtr ? 1u : 0u) | (rts ? 2u : 0u))),
+    .wIndex   = tu_htole16(p_cdc->itf_num),
     .wLength  = 0
   };
 
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 2573f5a6b..ca745464c 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -295,10 +295,10 @@ bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint3
   {
     TU_LOG2("  Get Report callback (%u, %u)\r\n", dev_addr, instance);
     TU_LOG3_MEM(hid_itf->epin_buf, xferred_bytes, 2);
-    tuh_hid_report_received_cb(dev_addr, instance, hid_itf->epin_buf, xferred_bytes);
+    tuh_hid_report_received_cb(dev_addr, instance, hid_itf->epin_buf, (uint16_t) xferred_bytes);
   }else
   {
-    if (tuh_hid_report_sent_cb) tuh_hid_report_sent_cb(dev_addr, instance, hid_itf->epout_buf, xferred_bytes);
+    if (tuh_hid_report_sent_cb) tuh_hid_report_sent_cb(dev_addr, instance, hid_itf->epout_buf, (uint16_t) xferred_bytes);
   }
 
   return true;
@@ -332,7 +332,8 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   TU_LOG2("[%u] HID opening Interface %u\r\n", dev_addr, desc_itf->bInterfaceNumber);
 
   // len = interface + hid + n*endpoints
-  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
+  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
+                                       desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
   TU_ASSERT(max_len >= drv_len);
 
   uint8_t const *p_desc = (uint8_t const *) desc_itf;
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index c54a63f37..934f79ff7 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -325,19 +325,19 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
         p_msc->stage = MSC_STAGE_DATA;
 
         uint8_t const ep_data = (cbw->dir & TUSB_DIR_IN_MASK) ? p_msc->ep_in : p_msc->ep_out;
-        TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, cbw->total_bytes));
+        TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, (uint16_t) cbw->total_bytes));
       }else
       {
         // Status stage
         p_msc->stage = MSC_STAGE_STATUS;
-        TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)));
+        TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
       }
     break;
 
     case MSC_STAGE_DATA:
       // Status stage
       p_msc->stage = MSC_STAGE_STATUS;
-      TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)));
+      TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
     break;
 
     case MSC_STAGE_STATUS:
@@ -370,7 +370,7 @@ bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
              MSC_PROTOCOL_BOT  == desc_itf->bInterfaceProtocol);
 
   // msc driver length is fixed
-  uint16_t const drv_len = sizeof(tusb_desc_interface_t) + desc_itf->bNumEndpoints*sizeof(tusb_desc_endpoint_t);
+  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
   TU_ASSERT(drv_len <= max_len);
 
   msch_interface_t* p_msc = get_itf(dev_addr);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 4c9b0b1ba..b6a03b82e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -665,7 +665,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
           TU_LOG2_MEM(_ctrl_xfer.buffer, xferred_bytes, 2);
         }
 
-        _ctrl_xfer.actual_len = xferred_bytes;
+        _ctrl_xfer.actual_len = (uint16_t) xferred_bytes;
 
         // ACK stage: toggle is always 1
         _set_control_xfer_stage(CONTROL_STAGE_ACK);
@@ -696,7 +696,7 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer)
 
   TU_VERIFY(usbh_edpt_claim(daddr, ep_addr));
 
-  if ( !usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, xfer->buflen, xfer->complete_cb, xfer->user_data) )
+  if ( !usbh_edpt_xfer_with_callback(daddr, ep_addr, xfer->buffer, (uint16_t) xfer->buflen, xfer->complete_cb, xfer->user_data) )
   {
     usbh_edpt_release(daddr, ep_addr);
     return false;
@@ -1525,7 +1525,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     }
 #endif
 
-    uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
+    uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end-p_desc));
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
     // Find driver for this interface
diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h
index abef286b4..8b428d642 100644
--- a/src/osal/osal_pico.h
+++ b/src/osal/osal_pico.h
@@ -100,11 +100,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 //--------------------------------------------------------------------+
 #include "common/tusb_fifo.h"
 
-#if CFG_TUH_ENABLED
-extern void hcd_int_disable(uint8_t rhport);
-extern void hcd_int_enable(uint8_t rhport);
-#endif
-
 typedef struct
 {
     tu_fifo_t ff;
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 93c764caf..13e7778ea 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -262,7 +262,7 @@ static struct hw_endpoint *_next_free_interrupt_ep(void)
         if (!ep->configured)
         {
             // Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
-            ep->interrupt_num = i - 1;
+            ep->interrupt_num = (uint8_t) (i - 1);
             return ep;
         }
     }
@@ -297,7 +297,7 @@ static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
     return ep;
 }
 
-static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval)
+static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval)
 {
     // Already has data buffer, endpoint control, and buffer control allocated at this point
     assert(ep->endpoint_control);
@@ -329,7 +329,10 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
                   | EP_CTRL_INTERRUPT_PER_BUFFER
                   | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
                   | dpram_offset;
-    ep_reg |= bmInterval ? (bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB : 0;
+    if (bmInterval)
+    {
+      ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
+    }
     *ep->endpoint_control = ep_reg;
     pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
     ep->configured = true;
@@ -341,7 +344,7 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
         // device address
         // endpoint number / direction
         // preamble
-        uint32_t reg = dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB);
+        uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
 
         if (dir == TUSB_DIR_OUT)
         {
@@ -367,39 +370,41 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
 //--------------------------------------------------------------------+
 bool hcd_init(uint8_t rhport)
 {
-    pico_trace("hcd_init %d\n", rhport);
-    assert(rhport == 0);
+  (void) rhport;
+  pico_trace("hcd_init %d\n", rhport);
+  assert(rhport == 0);
 
-    // Reset any previous state
-    rp2040_usb_init();
+  // Reset any previous state
+  rp2040_usb_init();
 
-    // Force VBUS detect to always present, for now we assume vbus is always provided (without using VBUS En)
-    usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
+  // Force VBUS detect to always present, for now we assume vbus is always provided (without using VBUS En)
+  usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
 
-    irq_add_shared_handler(USBCTRL_IRQ, hcd_rp2040_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY);
+  irq_add_shared_handler(USBCTRL_IRQ, hcd_rp2040_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY);
 
-    // clear epx and interrupt eps
-    memset(&ep_pool, 0, sizeof(ep_pool));
+  // clear epx and interrupt eps
+  memset(&ep_pool, 0, sizeof(ep_pool));
 
-    // Enable in host mode with SOF / Keep alive on
-    usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS | USB_MAIN_CTRL_HOST_NDEVICE_BITS;
-    usb_hw->sie_ctrl = SIE_CTRL_BASE;
-    usb_hw->inte = USB_INTE_BUFF_STATUS_BITS      | 
-                   USB_INTE_HOST_CONN_DIS_BITS    | 
-                   USB_INTE_HOST_RESUME_BITS      | 
-                   USB_INTE_STALL_BITS            | 
-                   USB_INTE_TRANS_COMPLETE_BITS   |
-                   USB_INTE_ERROR_RX_TIMEOUT_BITS |
-                   USB_INTE_ERROR_DATA_SEQ_BITS   ;
+  // Enable in host mode with SOF / Keep alive on
+  usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS | USB_MAIN_CTRL_HOST_NDEVICE_BITS;
+  usb_hw->sie_ctrl = SIE_CTRL_BASE;
+  usb_hw->inte = USB_INTE_BUFF_STATUS_BITS      |
+                 USB_INTE_HOST_CONN_DIS_BITS    |
+                 USB_INTE_HOST_RESUME_BITS      |
+                 USB_INTE_STALL_BITS            |
+                 USB_INTE_TRANS_COMPLETE_BITS   |
+                 USB_INTE_ERROR_RX_TIMEOUT_BITS |
+                 USB_INTE_ERROR_DATA_SEQ_BITS   ;
 
-    return true;
+  return true;
 }
 
 void hcd_port_reset(uint8_t rhport)
 {
-    pico_trace("hcd_port_reset\n");
-    assert(rhport == 0);
-    // TODO: Nothing to do here yet. Perhaps need to reset some state?
+  (void) rhport;
+  pico_trace("hcd_port_reset\n");
+  assert(rhport == 0);
+  // TODO: Nothing to do here yet. Perhaps need to reset some state?
 }
 
 void hcd_port_reset_end(uint8_t rhport)
@@ -409,25 +414,27 @@ void hcd_port_reset_end(uint8_t rhport)
 
 bool hcd_port_connect_status(uint8_t rhport)
 {
-    pico_trace("hcd_port_connect_status\n");
-    assert(rhport == 0);
-    return usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS;
+  (void) rhport;
+  pico_trace("hcd_port_connect_status\n");
+  assert(rhport == 0);
+  return usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS;
 }
 
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
-    assert(rhport == 0);
-    // TODO: Should enumval this register
-    switch (dev_speed())
-    {
-        case 1:
-            return TUSB_SPEED_LOW;
-        case 2:
-            return TUSB_SPEED_FULL;
-        default:
-            panic("Invalid speed\n");
-            return TUSB_SPEED_INVALID;
-    }
+  (void) rhport;
+  assert(rhport == 0);
+  // TODO: Should enumval this register
+  switch (dev_speed())
+  {
+      case 1:
+          return TUSB_SPEED_LOW;
+      case 2:
+          return TUSB_SPEED_FULL;
+      default:
+          panic("Invalid speed\n");
+          return TUSB_SPEED_INVALID;
+  }
 }
 
 // Close all opened endpoint belong to this device
@@ -465,15 +472,17 @@ uint32_t hcd_frame_number(uint8_t rhport)
 
 void hcd_int_enable(uint8_t rhport)
 {
-    assert(rhport == 0);
-    irq_set_enabled(USBCTRL_IRQ, true);
+  (void) rhport;
+  assert(rhport == 0);
+  irq_set_enabled(USBCTRL_IRQ, true);
 }
 
 void hcd_int_disable(uint8_t rhport)
 {
-    // todo we should check this is disabling from the correct core; note currently this is never called
-    assert(rhport == 0);
-    irq_set_enabled(USBCTRL_IRQ, false);
+  (void) rhport;
+  // todo we should check this is disabling from the correct core; note currently this is never called
+  assert(rhport == 0);
+  irq_set_enabled(USBCTRL_IRQ, false);
 }
 
 //--------------------------------------------------------------------+
@@ -488,6 +497,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 
     // Allocated differently based on if it's an interrupt endpoint or not
     struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
+    TU_ASSERT(ep);
 
     _hw_endpoint_init(ep,
         dev_addr,
@@ -510,7 +520,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
     // Get appropriate ep. Either EPX or interrupt endpoint
     struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
-    assert(ep);
+    TU_ASSERT(ep);
 
     // EP should be inactive
     assert(!ep->active);
@@ -532,7 +542,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
         // That has set up buffer control, endpoint control etc
         // for host we have to initiate the transfer
-        usb_hw->dev_addr_ctrl = dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB);
+        usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB));
 
         uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
                          (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS);
@@ -556,11 +566,12 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Warray-bounds"
 #pragma GCC diagnostic ignored "-Wstringop-overflow"
-    memcpy((void*)&usbh_dpram->setup_packet[0], setup_packet, 8);
+    memcpy((void*) (uintptr_t) &usbh_dpram->setup_packet[0], setup_packet, 8);
 #pragma GCC diagnostic pop
 
     // Configure EP0 struct with setup info for the trans complete
     struct hw_endpoint *ep = _hw_endpoint_allocate(0);
+    TU_ASSERT(ep);
 
     // EPX should be inactive
     assert(!ep->active);

From dd7a17c34511e79bc259634f4fa157e7ddf98fd1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 27 Jun 2022 17:53:42 +0700
Subject: [PATCH 1088/2085] prevent error on specific warnings for net lwip &
 dual example for rp2040

---
 examples/device/net_lwip_webserver/CMakeLists.txt |  6 ++++++
 .../dual/host_hid_to_device_cdc/CMakeLists.txt    | 15 +++++++++++++--
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 5bb091a4f..beaa9ad99 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -72,6 +72,12 @@ if (EXISTS ${TOP}/lib/lwip/src)
     # Example common such as compiler warnings
     include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
 
+    # due to warnings from other net source, we need to prevent error from some of the warnings options
+    target_compile_options(${PROJECT} PUBLIC
+        -Wno-error=null-dereference
+        -Wno-error=conversion
+        )
+
     # Configure compilation flags and libraries for the example... see the corresponding function
     # in hw/bsp/FAMILY/family.cmake for details.
     family_configure_device_example(${PROJECT})
diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index cd6f16339..909ee423f 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -24,8 +24,19 @@ target_include_directories(${PROJECT} PUBLIC
         )
 
 # Example common such as compiler warnings
-# skip extra warnings since pio-usb still has some warnings to fix
-#include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+
+# due to warnings from other net source, we need to prevent error from some of the warnings options
+target_compile_options(${PROJECT} PUBLIC
+        -Wno-error=shadow
+        -Wno-error=cast-align
+        -Wno-error=cast-qual
+        -Wno-error=redundant-decls
+        -Wno-error=sign-conversion
+        -Wno-error=conversion
+        -Wno-error=sign-compare
+        -Wno-error=unused-function
+        )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.

From 9c56f7011171ff649a821fe87a3ee477299fa860 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 27 Jun 2022 20:30:47 +0700
Subject: [PATCH 1089/2085] suppress error with net example

---
 examples/device/net_lwip_webserver/CMakeLists.txt | 2 ++
 examples/make.mk                                  | 3 ++-
 src/class/net/ecm_rndis_device.c                  | 6 +++---
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index beaa9ad99..0f41b888a 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -76,6 +76,8 @@ if (EXISTS ${TOP}/lib/lwip/src)
     target_compile_options(${PROJECT} PUBLIC
         -Wno-error=null-dereference
         -Wno-error=conversion
+        -Wno-error=sign-conversion
+        -Wno-error=sign-compare
         )
 
     # Configure compilation flags and libraries for the example... see the corresponding function
diff --git a/examples/make.mk b/examples/make.mk
index fa909ddca..27e1db38c 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -113,7 +113,8 @@ CFLAGS += \
   -Wunused \
   -Wredundant-decls
 
-#  -Wconversion \
+# conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion
+#  -Wconversion
   
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index d85a3f778..5f316762f 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -318,11 +318,11 @@ bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t
             rndis_generic_msg_t *rndis_msg = (rndis_generic_msg_t *) ((void*) notify.rndis_buf);
             uint32_t msglen = tu_le32toh(rndis_msg->MessageLength);
             TU_ASSERT(msglen <= sizeof(notify.rndis_buf));
-            tud_control_xfer(rhport, request, notify.rndis_buf, msglen);
+            tud_control_xfer(rhport, request, notify.rndis_buf, (uint16_t) msglen);
           }
           else
           {
-            tud_control_xfer(rhport, request, notify.rndis_buf, sizeof(notify.rndis_buf));
+            tud_control_xfer(rhport, request, notify.rndis_buf, (uint16_t) sizeof(notify.rndis_buf));
           }
         }
       break;
@@ -369,7 +369,7 @@ static void handle_incoming_packet(uint32_t len)
         }
   }
 
-  if (!tud_network_recv_cb(pnt, size))
+  if (!tud_network_recv_cb(pnt, (uint16_t) size))
   {
     /* if a buffer was never handled by user code, we must renew on the user's behalf */
     tud_network_recv_renew();

From 25580b4fe9acd1d9f9f12cbfdd29037669376a8d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 27 Jun 2022 21:05:41 +0700
Subject: [PATCH 1090/2085] use forloop to avoid -Warray-bounds with host setup
 packet

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 13e7778ea..e9118c6a3 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -563,11 +563,10 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
     (void) rhport;
 
     // Copy data into setup packet buffer
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Warray-bounds"
-#pragma GCC diagnostic ignored "-Wstringop-overflow"
-    memcpy((void*) (uintptr_t) &usbh_dpram->setup_packet[0], setup_packet, 8);
-#pragma GCC diagnostic pop
+    for(uint8_t i=0; i<8; i++)
+    {
+      usbh_dpram->setup_packet[i] = setup_packet[i];
+    }
 
     // Configure EP0 struct with setup info for the trans complete
     struct hw_endpoint *ep = _hw_endpoint_allocate(0);

From bc4da2047bf73f81cfcd6daa9bd07901dcdff3c9 Mon Sep 17 00:00:00 2001
From: robert-hh <robert@hammelrath.com>
Date: Mon, 27 Jun 2022 20:31:44 +0200
Subject: [PATCH 1091/2085] samd: Fix a lock-up situation at high traffic.

This PR fixes a transmit lock-up, which happens, when data is received
and sent at the sime time at moderate to high speeds, like code
which just echoes incoming data.

In my case, an issue was reported here:
https://github.com/micropython/micropython/issues/8521
---
 src/portable/microchip/samd/dcd_samd.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c
index 20dbde0f4..22fe32407 100644
--- a/src/portable/microchip/samd/dcd_samd.c
+++ b/src/portable/microchip/samd/dcd_samd.c
@@ -286,14 +286,14 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   {
     bank->PCKSIZE.bit.MULTI_PACKET_SIZE = total_bytes;
     bank->PCKSIZE.bit.BYTE_COUNT = 0;
-    ep->EPSTATUSCLR.reg |= USB_DEVICE_EPSTATUSCLR_BK0RDY;
-    ep->EPINTFLAG.reg |= USB_DEVICE_EPINTFLAG_TRFAIL0;
+    ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+    ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
   } else
   {
     bank->PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
     bank->PCKSIZE.bit.BYTE_COUNT = total_bytes;
-    ep->EPSTATUSSET.reg |= USB_DEVICE_EPSTATUSSET_BK1RDY;
-    ep->EPINTFLAG.reg |= USB_DEVICE_EPINTFLAG_TRFAIL1;
+    ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
+    ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
   }
 
   return true;

From 4057c2d8d96a364329d14d3a4b2c237f388cfdc2 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Mon, 27 Jun 2022 22:39:10 +0100
Subject: [PATCH 1092/2085] rework suppress_tinyusb_warnings

* gcc 9.2.1 has some spurious -Wconversion warnings
* cmake 3.18 and above require set_target_properties to be added from the target directory (so added it to all examples)
* fixed a few warnings in a couple of examples
---
 examples/device/cdc_dual_ports/src/main.c |  4 +-
 examples/device/hid_composite/src/main.c  |  2 +-
 hw/bsp/rp2040/family.cmake                | 46 ++++++++++++++---------
 3 files changed, 32 insertions(+), 20 deletions(-)

diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 6053a3b81..d4d07dcd6 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -60,12 +60,12 @@ static void echo_serial_port(uint8_t itf, uint8_t buf[], uint32_t count)
     if (itf == 0)
     {
       // echo back 1st port as lower case
-      if (isupper(buf[i])) buf[i] += 'a' - 'A';
+      if (isupper(buf[i])) buf[i] = (uint8_t) (buf[i] + 'a' - 'A');
     }
     else
     {
       // echo back 2nd port as upper case
-      if (islower(buf[i])) buf[i] -= 'a' - 'A';
+      if (islower(buf[i])) buf[i] = (uint8_t) (buf[i] - 'a' - 'A');
     }
 
     tud_cdc_n_write_char(itf, buf[i]);
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index bc2347ab8..cc3566ac1 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -230,7 +230,7 @@ void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint8_t
   (void) instance;
   (void) len;
 
-  uint8_t next_report_id = report[0] + 1;
+  uint8_t next_report_id = (uint8_t)(report[0] + 1);
 
   if (next_report_id < REPORT_ID_COUNT)
   {
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index ed7041e4e..794d02325 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -150,11 +150,13 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	function(family_configure_device_example TARGET)
 		family_configure_target(${TARGET})
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device)
+		suppress_tinyusb_warnings()
 	endfunction()
 
 	function(family_configure_host_example TARGET)
 		family_configure_target(${TARGET})
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
+		suppress_tinyusb_warnings()
 	endfunction()
 
 	function(family_add_pico_pio_usb TARGET)
@@ -165,6 +167,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		family_configure_target(${TARGET})
 		# require tinyusb_pico_pio_usb
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb )
+		suppress_tinyusb_warnings()
 	endfunction()
 
 	function(check_and_add_pico_pio_usb_support)
@@ -232,25 +235,34 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 
 	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
 	function(suppress_tinyusb_warnings)
-		set_source_files_properties(
-					${PICO_TINYUSB_PATH}/src/device/usbd.c
+		# some of these are pretty silly warnings only occurring in some older GCC versions
+		set(CONVERSION_WARNING_FILES
+				${PICO_TINYUSB_PATH}/src/tusb.c
+				${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
+				${PICO_TINYUSB_PATH}/src/device/usbd.c
+				${PICO_TINYUSB_PATH}/src/device/usbd_control.c
+				${PICO_TINYUSB_PATH}/src/host/usbh.c
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
+				${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c
+				${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c
+				${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c
+				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c
+				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c
+				${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c
+				${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c
+				${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+				)
+		foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES)
+			set_source_files_properties(
+					${SOURCE_FILE}
 					PROPERTIES
 					COMPILE_FLAGS "-Wno-conversion")
+		endforeach()
 		set_source_files_properties(
-					${PICO_TINYUSB_PATH}/src/device/usbd_control.c
-					PROPERTIES
-					COMPILE_FLAGS "-Wno-conversion")
-		set_source_files_properties(
-					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
-					PROPERTIES
-					COMPILE_FLAGS "-Wno-conversion")
-		set_source_files_properties(
-					${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
-					PROPERTIES
-					COMPILE_FLAGS "-Wno-conversion")
-		set_source_files_properties(
-					${PICO_TINYUSB_PATH}/src/tusb.c
-					PROPERTIES
-					COMPILE_FLAGS "-Wno-conversion")
+				${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds"
+		)
 	endfunction()
 endif()

From 898b52be45f476d7062d50fed722d92f0dccf4ae Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 28 Jun 2022 16:27:44 +0700
Subject: [PATCH 1093/2085] update rp2040 warnings

- remove "-Wno-stringop-overflow -Wno-array-bounds"
- skip -Wconversion for gcc 9 and prior
- suppress_tinyusb_warnings only when building with gcc 9 and below
---
 examples/device/cdc_dual_ports/src/main.c |  6 ++-
 examples/device/hid_composite/src/main.c  |  2 +-
 examples/example.cmake                    |  6 +++
 hw/bsp/rp2040/family.cmake                | 55 +++++++++++------------
 4 files changed, 37 insertions(+), 32 deletions(-)

diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index d4d07dcd6..0264f0566 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -55,17 +55,19 @@ int main(void)
 // with Serial0 as all lower case, Serial1 as all upper case
 static void echo_serial_port(uint8_t itf, uint8_t buf[], uint32_t count)
 {
+  uint8_t const case_diff = 'a' - 'A';
+
   for(uint32_t i=0; i<count; i++)
   {
     if (itf == 0)
     {
       // echo back 1st port as lower case
-      if (isupper(buf[i])) buf[i] = (uint8_t) (buf[i] + 'a' - 'A');
+      if (isupper(buf[i])) buf[i] += case_diff;
     }
     else
     {
       // echo back 2nd port as upper case
-      if (islower(buf[i])) buf[i] = (uint8_t) (buf[i] - 'a' - 'A');
+      if (islower(buf[i])) buf[i] -= case_diff;
     }
 
     tud_cdc_n_write_char(itf, buf[i]);
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 3a3839a1a..05315f266 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -230,7 +230,7 @@ void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_
   (void) instance;
   (void) len;
 
-  uint8_t next_report_id = (uint8_t)(report[0] + 1);
+  uint8_t next_report_id = report[0] + 1u;
 
   if (next_report_id < REPORT_ID_COUNT)
   {
diff --git a/examples/example.cmake b/examples/example.cmake
index 6bb82a56d..3e395d53f 100644
--- a/examples/example.cmake
+++ b/examples/example.cmake
@@ -21,5 +21,11 @@ target_compile_options(${PROJECT} PUBLIC
         -Wuninitialized
         -Wunused
         -Wredundant-decls
+        )
+
+# GCC version 9 or prior has a bug with incorrect Wconversion warnings
+if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
+  target_compile_options(${PROJECT} PUBLIC
         -Wconversion
         )
+endif()
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 794d02325..530d80fec 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -235,34 +235,31 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 
 	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
 	function(suppress_tinyusb_warnings)
-		# some of these are pretty silly warnings only occurring in some older GCC versions
-		set(CONVERSION_WARNING_FILES
-				${PICO_TINYUSB_PATH}/src/tusb.c
-				${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
-				${PICO_TINYUSB_PATH}/src/device/usbd.c
-				${PICO_TINYUSB_PATH}/src/device/usbd_control.c
-				${PICO_TINYUSB_PATH}/src/host/usbh.c
-				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
-				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
-				${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c
-				${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c
-				${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c
-				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c
-				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c
-				${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c
-				${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c
-				${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
-				)
-		foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES)
-			set_source_files_properties(
-					${SOURCE_FILE}
-					PROPERTIES
-					COMPILE_FLAGS "-Wno-conversion")
-		endforeach()
-		set_source_files_properties(
-				${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c
-				PROPERTIES
-				COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds"
-		)
+		# some of these are pretty silly warnings only occurring in some older GCC versions 9 or prior
+		if (CMAKE_C_COMPILER_VERSION VERSION_LESS 10.0)
+  		set(CONVERSION_WARNING_FILES
+  				${PICO_TINYUSB_PATH}/src/tusb.c
+  				${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
+  				${PICO_TINYUSB_PATH}/src/device/usbd.c
+  				${PICO_TINYUSB_PATH}/src/device/usbd_control.c
+  				${PICO_TINYUSB_PATH}/src/host/usbh.c
+  				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+  				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
+  				${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c
+  				${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c
+  				${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c
+  				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c
+  				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c
+  				${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c
+  				${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c
+  				${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+  				)
+  		foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES)
+  			set_source_files_properties(
+  					${SOURCE_FILE}
+  					PROPERTIES
+  					COMPILE_FLAGS "-Wno-conversion")
+  		endforeach()
+  	endif()
 	endfunction()
 endif()

From b12863d27ca528c6d9545f98d9664d2a342fc4d6 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 29 Jun 2022 07:28:35 +0100
Subject: [PATCH 1094/2085] Fix actual compiler warning on gcc 10.3.1

---
 src/tusb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/tusb.c b/src/tusb.c
index 709bb7d48..c3787ff8f 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -295,7 +295,7 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
 
   // fill up last row to 16 for printing ascii
   const uint32_t remain = count%16;
-  uint8_t nback = (remain ? remain : 16);
+  uint8_t nback = (uint8_t)(remain ? remain : 16);
 
   if ( remain )
   {

From 8fe9022a6e6dea785092f4e0dff8180f1f0d4d86 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Jun 2022 14:06:44 +0700
Subject: [PATCH 1095/2085] fix buid_board.py script

---
 hw/bsp/ea4088qs/ea4088qs.c              |  4 +--
 hw/bsp/frdm_k32l2b/board.mk             |  2 +-
 hw/bsp/frdm_kl25z/board.mk              |  2 +-
 hw/bsp/kuiic/kuiic.c                    |  2 +-
 hw/bsp/lpcxpresso11u37/board.mk         |  2 +-
 hw/bsp/lpcxpresso1347/board.mk          |  2 +-
 hw/bsp/nutiny_nuc121s/board.mk          |  3 ++
 hw/bsp/nutiny_nuc125s/board.mk          |  3 ++
 hw/bsp/nutiny_nuc126v/board.mk          |  3 ++
 hw/bsp/nutiny_sdk_nuc505/board.mk       |  3 ++
 hw/bsp/same70_qmtech/board.mk           |  2 +-
 hw/bsp/same70_xplained/board.mk         |  2 +-
 hw/bsp/samg55xplained/board.mk          |  2 +-
 hw/bsp/spresense/board.mk               |  3 +-
 hw/bsp/stm32l0538disco/board.mk         |  2 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h |  3 ++
 tools/build_family.py                   |  2 +-
 tools/build_utils.py                    | 44 +++++++++++++++----------
 18 files changed, 55 insertions(+), 31 deletions(-)

diff --git a/hw/bsp/ea4088qs/ea4088qs.c b/hw/bsp/ea4088qs/ea4088qs.c
index fa905b2f9..7150ed393 100644
--- a/hw/bsp/ea4088qs/ea4088qs.c
+++ b/hw/bsp/ea4088qs/ea4088qs.c
@@ -33,11 +33,11 @@
 void USB_IRQHandler(void)
 {
   #if CFG_TUD_ENABLED
-    tuh_int_handler(0);
+    tud_int_handler(0);
   #endif
 
   #if CFG_TUH_ENABLED
-    tud_int_handler(0);
+    tuh_int_handler(0);
   #endif
 }
 
diff --git a/hw/bsp/frdm_k32l2b/board.mk b/hw/bsp/frdm_k32l2b/board.mk
index 56df553da..a737eb360 100644
--- a/hw/bsp/frdm_k32l2b/board.mk
+++ b/hw/bsp/frdm_k32l2b/board.mk
@@ -9,7 +9,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
+CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
 
 MCU_DIR = $(SDK_DIR)/devices/K32L2B31A
 
diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
index 3585b8b03..6a72d516b 100644
--- a/hw/bsp/frdm_kl25z/board.mk
+++ b/hw/bsp/frdm_kl25z/board.mk
@@ -14,7 +14,7 @@ LDFLAGS += \
   -Wl,--defsym,__heap_size__=0
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=format
+CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls
 
 MCU_DIR = $(SDK_DIR)/devices/MKL25Z4
 
diff --git a/hw/bsp/kuiic/kuiic.c b/hw/bsp/kuiic/kuiic.c
index 737ef3f5c..7aaa9e03c 100644
--- a/hw/bsp/kuiic/kuiic.c
+++ b/hw/bsp/kuiic/kuiic.c
@@ -45,7 +45,7 @@
  * Variables
  ******************************************************************************/
 /* System clock frequency. */
-extern uint32_t SystemCoreClock;
+// extern uint32_t SystemCoreClock;
 
 /*******************************************************************************
  * Variables for BOARD_BootClockRUN configuration
diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk
index b736eebe1..be6d2ed52 100644
--- a/hw/bsp/lpcxpresso11u37/board.mk
+++ b/hw/bsp/lpcxpresso11u37/board.mk
@@ -15,7 +15,7 @@ CFLAGS += \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=redundant-decls
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc11uxx/lpc_chip_11uxx
 
diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk
index 62135c274..bf9c97c82 100644
--- a/hw/bsp/lpcxpresso1347/board.mk
+++ b/hw/bsp/lpcxpresso1347/board.mk
@@ -15,7 +15,7 @@ CFLAGS += \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
 
 # startup.c and lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=redundant-decls
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
 
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index ff1d5aa3a..ad2ee1ea0 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -10,6 +10,9 @@ CFLAGS += \
   -DCFG_EXAMPLE_MSC_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_NUC121
 
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=redundant-decls
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/nuc121_flash.ld
 
diff --git a/hw/bsp/nutiny_nuc125s/board.mk b/hw/bsp/nutiny_nuc125s/board.mk
index bb56e42ab..000c8cd95 100644
--- a/hw/bsp/nutiny_nuc125s/board.mk
+++ b/hw/bsp/nutiny_nuc125s/board.mk
@@ -10,6 +10,9 @@ CFLAGS += \
   -DCFG_EXAMPLE_MSC_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_NUC121
 
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=redundant-decls
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/nuc125_flash.ld
 
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index 4f0ebf201..0dcd897cb 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -11,6 +11,9 @@ CFLAGS += \
   -D__CORTEX_SC=0 \
   -DCFG_TUSB_MCU=OPT_MCU_NUC126
 
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=redundant-decls
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/nuc126_flash.ld
 
diff --git a/hw/bsp/nutiny_sdk_nuc505/board.mk b/hw/bsp/nutiny_sdk_nuc505/board.mk
index e8514347e..f27577e36 100644
--- a/hw/bsp/nutiny_sdk_nuc505/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc505/board.mk
@@ -9,6 +9,9 @@ CFLAGS += \
   -mfpu=fpv4-sp-d16 \
   -DCFG_TUSB_MCU=OPT_MCU_NUC505
 
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=redundant-decls
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/nuc505_flashtoram.ld
 
diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
index ba7088e44..2aa09f5dd 100644
--- a/hw/bsp/same70_qmtech/board.mk
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -11,7 +11,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
 
 ASF_DIR = hw/mcu/microchip/same70
 
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index cb2decf50..cbc51e6b0 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -11,7 +11,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
 
 ASF_DIR = hw/mcu/microchip/same70
 
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index deff6944c..d0d0ade01 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMG
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=cast-qual -Wno-error=null-dereference
+CFLAGS += -Wno-error=undef -Wno-error=cast-qual -Wno-error=null-dereference -Wno-error=redundant-decls
 
 ASF_DIR = hw/mcu/microchip/samg55
 
diff --git a/hw/bsp/spresense/board.mk b/hw/bsp/spresense/board.mk
index ba291e817..78d7f6a66 100644
--- a/hw/bsp/spresense/board.mk
+++ b/hw/bsp/spresense/board.mk
@@ -34,8 +34,9 @@ CFLAGS += \
 	-Wno-error=unused-parameter \
 	-DCFG_TUSB_MCU=OPT_MCU_CXD56 \
 
+# suppress following warnings from mcu driver
 # lwip/src/core/raw.c:334:43: error: declaration of 'recv' shadows a global declaration
-CFLAGS += -Wno-error=shadow
+CFLAGS += -Wno-error=shadow  -Wno-error=redundant-decls
 
 SPRESENSE_SDK = $(TOP)/hw/mcu/sony/cxd56/spresense-exported-sdk
 
diff --git a/hw/bsp/stm32l0538disco/board.mk b/hw/bsp/stm32l0538disco/board.mk
index e19101d64..69f09075a 100644
--- a/hw/bsp/stm32l0538disco/board.mk
+++ b/hw/bsp/stm32l0538disco/board.mk
@@ -17,7 +17,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L0
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized
+CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=redundant-decls
 
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/$(BOARD)/STM32L053C8Tx_FLASH.ld
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 1d849541e..1187e0d6e 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -43,6 +43,9 @@
   #define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
   #define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
 
+  #define EP_MAX_HS       USB_OTG_HS_MAX_IN_ENDPOINTS
+  #define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F4
   #include "stm32f4xx.h"
   #define EP_MAX_FS       USB_OTG_FS_MAX_IN_ENDPOINTS
diff --git a/tools/build_family.py b/tools/build_family.py
index 095ca4ff7..680411eab 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -48,7 +48,7 @@ all_families.sort()
 def build_family(example, family):
     all_boards = []
     for entry in os.scandir("hw/bsp/{}/boards".format(family)):
-        if entry.is_dir():
+        if entry.is_dir() and entry.name != 'pico_sdk':
             all_boards.append(entry.name)
     filter_with_input(all_boards)
     all_boards.sort()
diff --git a/tools/build_utils.py b/tools/build_utils.py
index 299fffa4d..68c2ed98b 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -4,26 +4,34 @@ def skip_example(example, board):
     ex_dir = pathlib.Path('examples/') / example
     bsp = pathlib.Path("hw/bsp")
 
-    board_dir = list(bsp.glob("*/boards/" + board))
-    if not board_dir:
-        # Skip unknown boards
-        return True
-
-    board_dir = list(board_dir)[0]
+    # board without family
+    board_dir = bsp / board
     
-    family_dir = board_dir.parent.parent
-    family = family_dir.name
+    if board_dir.exists():
+        family = ""
+        mk_contents = ""
+    else:
+        # otherwise look into family        
+        board_dir = list(bsp.glob("*/boards/" + board))
+        if not board_dir:
+            # Skip unknown boards
+            return True
+    
+        board_dir = list(board_dir)[0]
+    
+        family_dir = board_dir.parent.parent
+        family = family_dir.name
+    
+        # family CMake
+        family_mk = family_dir / "family.cmake"
+    
+        # family.mk
+        if not family_mk.exists():
+            family_mk = family_dir / "family.mk"
+    
+        mk_contents = family_mk.read_text()
 
-    # family CMake
-    family_mk = family_dir / "family.cmake"
-
-    # family.mk
-    if not family_mk.exists():
-        family_mk = family_dir / "family.mk"
-
-    mk_contents = family_mk.read_text()
-
-    # Find the mcu
+    # Find the mcu, first in family mk then board mk
     if "CFG_TUSB_MCU=OPT_MCU_" not in mk_contents:
         board_mk = board_dir / "board.cmake"
         if not board_mk.exists():

From 1e00fe78c7271ecc1b813b10efaf929f4172054e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Jun 2022 14:07:00 +0700
Subject: [PATCH 1096/2085] use action gcc

---
 .github/workflows/build_arm.yml | 48 +++++++--------------------------
 1 file changed, 9 insertions(+), 39 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 6e4702735..27cb9f1f7 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -65,7 +65,7 @@ jobs:
         - 'xmc4000'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v3
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
@@ -79,32 +79,17 @@ jobs:
          repository: hathach/linkermap
          path: linkermap
 
-    - name: Checkout pico-sdk
+    - name: Checkout pico-sdk for rp2040
       if: matrix.family == 'rp2040'
       run: |
         git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
         echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
         git submodule update --init hw/mcu/raspberry_pi/Pico-PIO-USB
 
-    - name: Set Toolchain URL
-      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz
-
-    - name: Cache Toolchain
-      uses: actions/cache@v2
-      id: cache-toolchain
+    - name: Install ARM GCC
+      uses: carlosperate/arm-none-eabi-gcc-action@v1
       with:
-        path: ~/cache/
-        key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }}
-
-    - name: Install Toolchain
-      if: steps.cache-toolchain.outputs.cache-hit != 'true'
-      run: |
-        mkdir -p ~/cache/toolchain
-        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
-        tar -C ~/cache/toolchain -xaf toolchain.tar.gz
-
-    - name: Set Toolchain Path
-      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
+        release: '11.2-2022.02'
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
@@ -135,7 +120,7 @@ jobs:
 
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v3
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
@@ -143,25 +128,10 @@ jobs:
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
-    - name: Set Toolchain URL
-      run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v10.2.1-1.1/xpack-arm-none-eabi-gcc-10.2.1-1.1-linux-x64.tar.gz
-
-    - name: Cache Toolchain
-      uses: actions/cache@v2
-      id: cache-toolchain
+    - name: Install ARM GCC
+      uses: carlosperate/arm-none-eabi-gcc-action@v1
       with:
-        path: ~/cache/
-        key: ${{ runner.os }}-21-03-04-${{ env.TOOLCHAIN_URL }}
-
-    - name: Install Toolchain
-      if: steps.cache-toolchain.outputs.cache-hit != 'true'
-      run: |
-        mkdir -p ~/cache/toolchain
-        wget --progress=dot:mega $TOOLCHAIN_URL -O toolchain.tar.gz
-        tar -C ~/cache/toolchain -xaf toolchain.tar.gz
-
-    - name: Set Toolchain Path
-      run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
+        release: '11.2-2022.02'
 
     - name: Build
       run: python3 tools/build_board.py ${{ matrix.example }}

From a62c2640b5217e416ba48aa2011d997cfa7d81a5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Jun 2022 14:08:01 +0700
Subject: [PATCH 1097/2085] remove redundant rp2040 boards, all boards
 supported by pico-sdk already supported

---
 hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake   | 1 -
 hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake | 1 -
 hw/bsp/rp2040/boards/adafruit_qtpy_rp2040/board.cmake      | 1 -
 3 files changed, 3 deletions(-)
 delete mode 100644 hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake
 delete mode 100644 hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake
 delete mode 100644 hw/bsp/rp2040/boards/adafruit_qtpy_rp2040/board.cmake

diff --git a/hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake b/hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake
deleted file mode 100644
index e527a8ce3..000000000
--- a/hw/bsp/rp2040/boards/adafruit_feather_rp2040/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-set(PICO_BOARD adafruit_feather_rp2040)
\ No newline at end of file
diff --git a/hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake b/hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake
deleted file mode 100644
index 3fd2dd06b..000000000
--- a/hw/bsp/rp2040/boards/adafruit_itsybitsy_rp2040/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-set(PICO_BOARD adafruit_itsybitsy_rp2040)
\ No newline at end of file
diff --git a/hw/bsp/rp2040/boards/adafruit_qtpy_rp2040/board.cmake b/hw/bsp/rp2040/boards/adafruit_qtpy_rp2040/board.cmake
deleted file mode 100644
index 469929c51..000000000
--- a/hw/bsp/rp2040/boards/adafruit_qtpy_rp2040/board.cmake
+++ /dev/null
@@ -1 +0,0 @@
-set(PICO_BOARD adafruit_qtpy_rp2040)
\ No newline at end of file

From 7949a4ec7c7e9ccc487068a01b84979d02f94875 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Jun 2022 14:12:58 +0700
Subject: [PATCH 1098/2085] skip freertos example for F1C100S

---
 .../device/cdc_msc_freertos/.skip.MCU_F1C100S   |  0
 examples/device/cdc_msc_freertos/skip.txt       | 17 +++++++++--------
 .../hid_composite_freertos/.skip.MCU_F1C100S    |  0
 examples/device/hid_composite_freertos/skip.txt | 16 +++++++++-------
 4 files changed, 18 insertions(+), 15 deletions(-)
 delete mode 100644 examples/device/cdc_msc_freertos/.skip.MCU_F1C100S
 delete mode 100644 examples/device/hid_composite_freertos/.skip.MCU_F1C100S

diff --git a/examples/device/cdc_msc_freertos/.skip.MCU_F1C100S b/examples/device/cdc_msc_freertos/.skip.MCU_F1C100S
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt
index 7137b78af..1ee51a9d4 100644
--- a/examples/device/cdc_msc_freertos/skip.txt
+++ b/examples/device/cdc_msc_freertos/skip.txt
@@ -1,10 +1,11 @@
 mcu:CXD56
-mcu:MSP430x5xx
-mcu:SAMD11
-mcu:VALENTYUSB_EPTRI
-mcu:MKL25ZXX
-mcu:RP2040
-mcu:SAMX7X
+mcu:F1C100S
 mcu:GD32VF103
-family:broadcom_64bit
-family:broadcom_32bit
\ No newline at end of file
+mcu:MKL25ZXX
+mcu:MSP430x5xx
+mcu:RP2040
+mcu:SAMD11
+mcu:SAMX7X
+mcu:VALENTYUSB_EPTRI
+family:broadcom_32bit
+family:broadcom_64bit
\ No newline at end of file
diff --git a/examples/device/hid_composite_freertos/.skip.MCU_F1C100S b/examples/device/hid_composite_freertos/.skip.MCU_F1C100S
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt
index e64187fd4..1ee51a9d4 100644
--- a/examples/device/hid_composite_freertos/skip.txt
+++ b/examples/device/hid_composite_freertos/skip.txt
@@ -1,9 +1,11 @@
 mcu:CXD56
-mcu:MSP430x5xx
-mcu:SAMD11
-mcu:VALENTYUSB_EPTRI
-mcu:RP2040
-mcu:SAMX7X
+mcu:F1C100S
 mcu:GD32VF103
-family:broadcom_64bit
-family:broadcom_32bit
\ No newline at end of file
+mcu:MKL25ZXX
+mcu:MSP430x5xx
+mcu:RP2040
+mcu:SAMD11
+mcu:SAMX7X
+mcu:VALENTYUSB_EPTRI
+family:broadcom_32bit
+family:broadcom_64bit
\ No newline at end of file

From 5a378703fbc30d8e7481abec81bc70a9e25761e6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Jun 2022 15:05:09 +0700
Subject: [PATCH 1099/2085] fix end symbol for samx7x and same5x

---
 examples/device/video_capture/skip.txt | 3 ++-
 hw/bsp/d5035_01/same51j19a_flash.ld    | 1 +
 hw/mcu/microchip                       | 2 +-
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/examples/device/video_capture/skip.txt b/examples/device/video_capture/skip.txt
index 892a8c6a7..5898664a2 100644
--- a/examples/device/video_capture/skip.txt
+++ b/examples/device/video_capture/skip.txt
@@ -1,2 +1,3 @@
 mcu:MSP430x5xx
-mcu:SAMD11
\ No newline at end of file
+mcu:NUC121
+mcu:SAMD11
diff --git a/hw/bsp/d5035_01/same51j19a_flash.ld b/hw/bsp/d5035_01/same51j19a_flash.ld
index 328d1c72f..a8dd44336 100644
--- a/hw/bsp/d5035_01/same51j19a_flash.ld
+++ b/hw/bsp/d5035_01/same51j19a_flash.ld
@@ -160,4 +160,5 @@ SECTIONS
 
     . = ALIGN(4);
     _end = . ;
+    end = .;
 }
diff --git a/hw/mcu/microchip b/hw/mcu/microchip
index 58eb37632..9e8b37e30 160000
--- a/hw/mcu/microchip
+++ b/hw/mcu/microchip
@@ -1 +1 @@
-Subproject commit 58eb3763200ff51a998be5f537acf67299add227
+Subproject commit 9e8b37e307d8404033bb881623a113931e1edf27

From 4da1a9359d7fa9813a01f133f919533184753064 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Jun 2022 15:12:01 +0700
Subject: [PATCH 1100/2085] fix build with fomu/fomu

---
 tools/build_utils.py | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/tools/build_utils.py b/tools/build_utils.py
index 68c2ed98b..d570d20e3 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -3,15 +3,14 @@ import pathlib
 def skip_example(example, board):
     ex_dir = pathlib.Path('examples/') / example
     bsp = pathlib.Path("hw/bsp")
-
-    # board without family
-    board_dir = bsp / board
     
-    if board_dir.exists():
+    if (bsp / board / "board.mk").exists():
+        # board without family
+        board_dir = bsp / board
         family = ""
         mk_contents = ""
     else:
-        # otherwise look into family        
+        # board within family
         board_dir = list(bsp.glob("*/boards/" + board))
         if not board_dir:
             # Skip unknown boards

From 158b3d761d4c0f1da8d60b63d43664e1f52a286d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Jun 2022 15:27:24 +0700
Subject: [PATCH 1101/2085] fix xmc4000 build

---
 hw/bsp/xmc4000/boards/xmc4500_relax/board.mk | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
index a2c2c5aaf..371adff91 100644
--- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
+++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
@@ -2,6 +2,9 @@ MCU_VARIANT = XMC4500
 CFLAGS += \
   -DXMC4500_F100x1024 \
 
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=stringop-overread
+
 LD_FILE = $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld
 
 JLINK_DEVICE = XMC4500-1024

From 8d07ea7ce560f2a938c573a0f0487ad3776402c4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Jun 2022 16:39:19 +0700
Subject: [PATCH 1102/2085] build_family.py in parallel

---
 tools/build_family.py | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/tools/build_family.py b/tools/build_family.py
index 680411eab..5f03bfc87 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -3,6 +3,7 @@ import glob
 import sys
 import subprocess
 import time
+from multiprocessing import Process
 
 import build_utils
 
@@ -52,9 +53,15 @@ def build_family(example, family):
             all_boards.append(entry.name)
     filter_with_input(all_boards)
     all_boards.sort()
-    
+
+    plist = []
     for board in all_boards:
-        build_board(example, board)
+        p = Process(target=build_board, args=(example, board))
+        plist.append(p)
+        p.start()
+
+    for p in plist:
+        p.join()
     
 def build_board(example, board):
     global success_count, fail_count, skip_count, exit_status
@@ -88,7 +95,6 @@ def build_board(example, board):
             print(build_result.stdout.decode("utf-8"))
 
 def build_size(example, board):
-    #elf_file = 'examples/device/{}/_build/{}/{}-firmware.elf'.format(example, board, board)
     elf_file = 'examples/{}/_build/{}/*.elf'.format(example, board)
     size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8")
     size_list = size_output.split('\n')[1].split('\t')
@@ -96,17 +102,18 @@ def build_size(example, board):
     sram_size = int(size_list[1]) + int(size_list[2])
     return (flash_size, sram_size)
 
-print(build_separator)
-print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
-
-for example in all_examples:
+if __name__ == '__main__':
     print(build_separator)
-    for family in all_families:
-        build_family(example, family)
+    print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
 
-total_time = time.monotonic() - total_time
-print(build_separator)
-print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(success_count, SUCCEEDED, fail_count, FAILED, skip_count, SKIPPED, total_time))
-print(build_separator)
+    for example in all_examples:
+        print(build_separator)
+        for family in all_families:
+            build_family(example, family)
 
-sys.exit(exit_status)
+    total_time = time.monotonic() - total_time
+    print(build_separator)
+    print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(success_count, SUCCEEDED, fail_count, FAILED, skip_count, SKIPPED, total_time))
+    print(build_separator)
+
+    sys.exit(exit_status)

From d5d5a6437cd73d2ad7b35e73b3ffc9d65aaa9ad3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Jun 2022 18:23:45 +0700
Subject: [PATCH 1103/2085] more parallel ci

---
 tools/build_family.py | 55 ++++++++++++++++++++-----------------------
 1 file changed, 26 insertions(+), 29 deletions(-)

diff --git a/tools/build_family.py b/tools/build_family.py
index 5f03bfc87..57a6c4d17 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -3,7 +3,7 @@ import glob
 import sys
 import subprocess
 import time
-from multiprocessing import Process
+from multiprocessing import Pool
 
 import build_utils
 
@@ -11,13 +11,6 @@ SUCCEEDED = "\033[32msucceeded\033[0m"
 FAILED = "\033[31mfailed\033[0m"
 SKIPPED = "\033[33mskipped\033[0m"
 
-success_count = 0
-fail_count = 0
-skip_count = 0
-exit_status = 0
-
-total_time = time.monotonic()
-
 build_format = '| {:29} | {:30} | {:18} | {:7} | {:6} | {:6} |'
 build_separator = '-' * 106
 
@@ -54,46 +47,45 @@ def build_family(example, family):
     filter_with_input(all_boards)
     all_boards.sort()
 
-    plist = []
-    for board in all_boards:
-        p = Process(target=build_board, args=(example, board))
-        plist.append(p)
-        p.start()
-
-    for p in plist:
-        p.join()
+    with Pool(processes=len(all_boards)) as pool:
+        pool_args = list((map(lambda b, e=example: [e, b], all_boards)))
+        result = pool.starmap(build_board, pool_args)
+        return list(map(sum, list(zip(*result))))
     
 def build_board(example, board):
-    global success_count, fail_count, skip_count, exit_status
     start_time = time.monotonic()
     flash_size = "-"
     sram_size = "-"
 
+    # succeeded, failed, skipped
+    ret = [0, 0, 0]
+
     # Check if board is skipped
     if build_utils.skip_example(example, board):
-        success = SKIPPED
-        skip_count += 1
-        print(build_format.format(example, board, success, '-', flash_size, sram_size))
+        status = SKIPPED
+        ret[2] = 1
+        print(build_format.format(example, board, status, '-', flash_size, sram_size))
     else:   
         #subprocess.run("make -C examples/{} BOARD={} clean".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
         build_result = subprocess.run("make -j -C examples/{} BOARD={} all".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
 
         if build_result.returncode == 0:
-            success = SUCCEEDED
-            success_count += 1
+            status = SUCCEEDED
+            ret[0] = 1
             (flash_size, sram_size) = build_size(example, board)
             subprocess.run("make -j -C examples/{} BOARD={} copy-artifact".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
         else:
-            exit_status = build_result.returncode
-            success = FAILED
-            fail_count += 1
+            status = FAILED
+            ret[1] = 1
 
         build_duration = time.monotonic() - start_time
-        print(build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size))
+        print(build_format.format(example, board, status, "{:.2f}s".format(build_duration), flash_size, sram_size))
 
         if build_result.returncode != 0:
             print(build_result.stdout.decode("utf-8"))
 
+    return ret
+
 def build_size(example, board):
     elf_file = 'examples/{}/_build/{}/*.elf'.format(example, board)
     size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8")
@@ -103,17 +95,22 @@ def build_size(example, board):
     return (flash_size, sram_size)
 
 if __name__ == '__main__':
+    # succeeded, failed, skipped
+    total_result = [0, 0, 0]
+
     print(build_separator)
     print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
+    total_time = time.monotonic()
 
     for example in all_examples:
         print(build_separator)
         for family in all_families:
-            build_family(example, family)
+            fret = build_family(example, family)
+            total_result = list(map(lambda x, y: x+y, total_result, fret))
 
     total_time = time.monotonic() - total_time
     print(build_separator)
-    print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(success_count, SUCCEEDED, fail_count, FAILED, skip_count, SKIPPED, total_time))
+    print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(total_result[0], SUCCEEDED, total_result[1], FAILED, total_result[2], SKIPPED, total_time))
     print(build_separator)
 
-    sys.exit(exit_status)
+    sys.exit(total_result[1])

From 8f9ecace4d9fecb14fbf8e8563d2f19334805d4d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Jun 2022 21:06:02 +0700
Subject: [PATCH 1104/2085] update build_board.py to parallel build

---
 tools/build_board.py  | 115 +++++++++++++++---------------------------
 tools/build_family.py |  96 ++++++++++-------------------------
 tools/build_utils.py  |  66 +++++++++++++++++++++---
 3 files changed, 127 insertions(+), 150 deletions(-)

diff --git a/tools/build_board.py b/tools/build_board.py
index 4d895329a..62a4ea82f 100644
--- a/tools/build_board.py
+++ b/tools/build_board.py
@@ -1,8 +1,7 @@
 import os
-import glob
 import sys
-import subprocess
 import time
+from multiprocessing import Pool
 
 import build_utils
 
@@ -10,90 +9,56 @@ SUCCEEDED = "\033[32msucceeded\033[0m"
 FAILED = "\033[31mfailed\033[0m"
 SKIPPED = "\033[33mskipped\033[0m"
 
-success_count = 0
-fail_count = 0
-skip_count = 0
-exit_status = 0
-
-total_time = time.monotonic()
-
-build_format = '| {:29} | {:30} | {:18} | {:7} | {:6} | {:6} |'
 build_separator = '-' * 106
 
+
 def filter_with_input(mylist):
     if len(sys.argv) > 1:
         input_args = list(set(mylist).intersection(sys.argv))
         if len(input_args) > 0:
             mylist[:] = input_args
 
-# If examples are not specified in arguments, build all
-all_examples = []
-for dir1 in os.scandir("examples"):
-    if dir1.is_dir():
-        for entry in os.scandir(dir1.path):
-            if entry.is_dir():
-                all_examples.append(dir1.name + '/' + entry.name)
-filter_with_input(all_examples)
-all_examples.sort()
 
-# If boards are not specified in arguments, build all
-all_boards = []
-for entry in os.scandir("hw/bsp"):
-    if entry.is_dir() and os.path.exists(entry.path + "/board.mk"):
-        all_boards.append(entry.name)
-filter_with_input(all_boards)
-all_boards.sort()
+if __name__ == '__main__':
+    # If examples are not specified in arguments, build all
+    all_examples = []
+    for dir1 in os.scandir("examples"):
+        if dir1.is_dir():
+            for entry in os.scandir(dir1.path):
+                if entry.is_dir():
+                    all_examples.append(dir1.name + '/' + entry.name)
+    filter_with_input(all_examples)
+    all_examples.sort()
 
-def build_board(example, board):
-    global success_count, fail_count, skip_count, exit_status
-    start_time = time.monotonic()
-    flash_size = "-"
-    sram_size = "-"
+    # If boards are not specified in arguments, build all
+    all_boards = []
+    for entry in os.scandir("hw/bsp"):
+        if entry.is_dir() and os.path.exists(entry.path + "/board.mk"):
+            all_boards.append(entry.name)
+    filter_with_input(all_boards)
+    all_boards.sort()
 
-    # Check if board is skipped
-    if build_utils.skip_example(example, board):
-        success = SKIPPED
-        skip_count += 1
-        print(build_format.format(example, board, success, '-', flash_size, sram_size))
-    else:
-        subprocess.run("make -C examples/{} BOARD={} clean".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        build_result = subprocess.run("make -j -C examples/{} BOARD={} all".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-
-        if build_result.returncode == 0:
-            success = SUCCEEDED
-            success_count += 1
-            (flash_size, sram_size) = build_size(example, board)
-        else:
-            exit_status = build_result.returncode
-            success = FAILED
-            fail_count += 1
-
-        build_duration = time.monotonic() - start_time
-        print(build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size))
-
-        if build_result.returncode != 0:
-            print(build_result.stdout.decode("utf-8"))
-
-def build_size(example, board):
-    #elf_file = 'examples/device/{}/_build/{}/{}-firmware.elf'.format(example, board, board)
-    elf_file = 'examples/{}/_build/{}/*.elf'.format(example, board)
-    size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8")
-    size_list = size_output.split('\n')[1].split('\t')
-    flash_size = int(size_list[0])
-    sram_size = int(size_list[1]) + int(size_list[2])
-    return (flash_size, sram_size)
-
-print(build_separator)
-print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
-
-for example in all_examples:
     print(build_separator)
-    for board in all_boards:
-        build_board(example, board)
+    print(build_utils.build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
+    total_time = time.monotonic()
 
-total_time = time.monotonic() - total_time
-print(build_separator)
-print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(success_count, SUCCEEDED, fail_count, FAILED, skip_count, SKIPPED, total_time))
-print(build_separator)
+    # succeeded, failed, skipped
+    total_result = [0, 0, 0]
+    for example in all_examples:
+        print(build_separator)
+        with Pool(processes=os.cpu_count()) as pool:
+            pool_args = list((map(lambda b, e=example: [e, b], all_boards)))
+            result = pool.starmap(build_utils.build_example, pool_args)
+            # sum all element of same index (column sum)
+            result = list(map(sum, list(zip(*result))))
+            
+            # add to total result
+            total_result = list(map(lambda x, y: x + y, total_result, result))
 
-sys.exit(exit_status)
+    total_time = time.monotonic() - total_time
+    print(build_separator)
+    print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(total_result[0], SUCCEEDED, total_result[1],
+                                                                       FAILED, total_result[2], SKIPPED, total_time))
+    print(build_separator)
+
+    sys.exit(total_result[1])
diff --git a/tools/build_family.py b/tools/build_family.py
index 57a6c4d17..c6c64d2b3 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -1,7 +1,5 @@
 import os
-import glob
 import sys
-import subprocess
 import time
 from multiprocessing import Pool
 
@@ -11,33 +9,15 @@ SUCCEEDED = "\033[32msucceeded\033[0m"
 FAILED = "\033[31mfailed\033[0m"
 SKIPPED = "\033[33mskipped\033[0m"
 
-build_format = '| {:29} | {:30} | {:18} | {:7} | {:6} | {:6} |'
 build_separator = '-' * 106
 
+
 def filter_with_input(mylist):
     if len(sys.argv) > 1:
         input_args = list(set(mylist).intersection(sys.argv))
         if len(input_args) > 0:
             mylist[:] = input_args
 
-# If examples are not specified in arguments, build all
-all_examples = []
-for dir1 in os.scandir("examples"):
-    if dir1.is_dir():
-        for entry in os.scandir(dir1.path):
-            if entry.is_dir():
-                all_examples.append(dir1.name + '/' + entry.name)
-filter_with_input(all_examples)
-all_examples.sort()
-
-# If family are not specified in arguments, build all
-all_families = []
-for entry in os.scandir("hw/bsp"):
-    if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name not in ("esp32s2", "esp32s3"):
-        all_families.append(entry.name)
-            
-filter_with_input(all_families)
-all_families.sort()
 
 def build_family(example, family):
     all_boards = []
@@ -47,70 +27,48 @@ def build_family(example, family):
     filter_with_input(all_boards)
     all_boards.sort()
 
-    with Pool(processes=len(all_boards)) as pool:
+    with Pool(processes=os.cpu_count()) as pool:
         pool_args = list((map(lambda b, e=example: [e, b], all_boards)))
-        result = pool.starmap(build_board, pool_args)
+        result = pool.starmap(build_utils.build_example, pool_args)
+        # sum all element of same index (column sum)
         return list(map(sum, list(zip(*result))))
-    
-def build_board(example, board):
-    start_time = time.monotonic()
-    flash_size = "-"
-    sram_size = "-"
 
-    # succeeded, failed, skipped
-    ret = [0, 0, 0]
-
-    # Check if board is skipped
-    if build_utils.skip_example(example, board):
-        status = SKIPPED
-        ret[2] = 1
-        print(build_format.format(example, board, status, '-', flash_size, sram_size))
-    else:   
-        #subprocess.run("make -C examples/{} BOARD={} clean".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        build_result = subprocess.run("make -j -C examples/{} BOARD={} all".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-
-        if build_result.returncode == 0:
-            status = SUCCEEDED
-            ret[0] = 1
-            (flash_size, sram_size) = build_size(example, board)
-            subprocess.run("make -j -C examples/{} BOARD={} copy-artifact".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        else:
-            status = FAILED
-            ret[1] = 1
-
-        build_duration = time.monotonic() - start_time
-        print(build_format.format(example, board, status, "{:.2f}s".format(build_duration), flash_size, sram_size))
-
-        if build_result.returncode != 0:
-            print(build_result.stdout.decode("utf-8"))
-
-    return ret
-
-def build_size(example, board):
-    elf_file = 'examples/{}/_build/{}/*.elf'.format(example, board)
-    size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8")
-    size_list = size_output.split('\n')[1].split('\t')
-    flash_size = int(size_list[0])
-    sram_size = int(size_list[1]) + int(size_list[2])
-    return (flash_size, sram_size)
 
 if __name__ == '__main__':
-    # succeeded, failed, skipped
-    total_result = [0, 0, 0]
+    # If examples are not specified in arguments, build all
+    all_examples = []
+    for dir1 in os.scandir("examples"):
+        if dir1.is_dir():
+            for entry in os.scandir(dir1.path):
+                if entry.is_dir():
+                    all_examples.append(dir1.name + '/' + entry.name)
+    filter_with_input(all_examples)
+    all_examples.sort()
+
+    # If family are not specified in arguments, build all
+    all_families = []
+    for entry in os.scandir("hw/bsp"):
+        if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name not in ("esp32s2", "esp32s3"):
+            all_families.append(entry.name)
+    filter_with_input(all_families)
+    all_families.sort()
 
     print(build_separator)
-    print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
+    print(build_utils.build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
     total_time = time.monotonic()
 
+    # succeeded, failed, skipped
+    total_result = [0, 0, 0]
     for example in all_examples:
         print(build_separator)
         for family in all_families:
             fret = build_family(example, family)
-            total_result = list(map(lambda x, y: x+y, total_result, fret))
+            total_result = list(map(lambda x, y: x + y, total_result, fret))
 
     total_time = time.monotonic() - total_time
     print(build_separator)
-    print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(total_result[0], SUCCEEDED, total_result[1], FAILED, total_result[2], SKIPPED, total_time))
+    print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(total_result[0], SUCCEEDED, total_result[1],
+                                                                       FAILED, total_result[2], SKIPPED, total_time))
     print(build_separator)
 
     sys.exit(total_result[1])
diff --git a/tools/build_utils.py b/tools/build_utils.py
index d570d20e3..f457c7986 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -1,9 +1,18 @@
+import subprocess
 import pathlib
+import time
+
+build_format = '| {:29} | {:30} | {:18} | {:7} | {:6} | {:6} |'
+
+SUCCEEDED = "\033[32msucceeded\033[0m"
+FAILED = "\033[31mfailed\033[0m"
+SKIPPED = "\033[33mskipped\033[0m"
+
 
 def skip_example(example, board):
     ex_dir = pathlib.Path('examples/') / example
     bsp = pathlib.Path("hw/bsp")
-    
+
     if (bsp / board / "board.mk").exists():
         # board without family
         board_dir = bsp / board
@@ -15,19 +24,19 @@ def skip_example(example, board):
         if not board_dir:
             # Skip unknown boards
             return True
-    
+
         board_dir = list(board_dir)[0]
-    
+
         family_dir = board_dir.parent.parent
         family = family_dir.name
-    
+
         # family CMake
         family_mk = family_dir / "family.cmake"
-    
+
         # family.mk
         if not family_mk.exists():
             family_mk = family_dir / "family.mk"
-    
+
         mk_contents = family_mk.read_text()
 
     # Find the mcu, first in family mk then board mk
@@ -66,3 +75,48 @@ def skip_example(example, board):
                     "family:" + family in onlys)
 
     return False
+
+
+def build_example(example, board):
+    start_time = time.monotonic()
+    flash_size = "-"
+    sram_size = "-"
+
+    # succeeded, failed, skipped
+    ret = [0, 0, 0]
+
+    # Check if board is skipped
+    if skip_example(example, board):
+        status = SKIPPED
+        ret[2] = 1
+        print(build_format.format(example, board, status, '-', flash_size, sram_size))
+    else:
+        build_result = subprocess.run("make -j -C examples/{} BOARD={} all".format(example, board), shell=True,
+                                      stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+
+        if build_result.returncode == 0:
+            status = SUCCEEDED
+            ret[0] = 1
+            (flash_size, sram_size) = build_size(example, board)
+            subprocess.run("make -j -C examples/{} BOARD={} copy-artifact".format(example, board), shell=True,
+                           stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        else:
+            status = FAILED
+            ret[1] = 1
+
+        build_duration = time.monotonic() - start_time
+        print(build_format.format(example, board, status, "{:.2f}s".format(build_duration), flash_size, sram_size))
+
+        if build_result.returncode != 0:
+            print(build_result.stdout.decode("utf-8"))
+
+    return ret
+
+
+def build_size(example, board):
+    elf_file = 'examples/{}/_build/{}/*.elf'.format(example, board)
+    size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8")
+    size_list = size_output.split('\n')[1].split('\t')
+    flash_size = int(size_list[0])
+    sram_size = int(size_list[1]) + int(size_list[2])
+    return (flash_size, sram_size)

From 023191be23f736ccebd5eddd75d388ee1edb9e4b Mon Sep 17 00:00:00 2001
From: Pawel Hryniszak <phryniszak@users.noreply.github.com>
Date: Wed, 29 Jun 2022 20:28:22 +0100
Subject: [PATCH 1105/2085] Let to define CFG_BOARD_UART_BAUDRATE in CMake

---
 hw/bsp/board.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index b4e0cb298..339e2e3b5 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -41,7 +41,10 @@
 #include "ansi_escape.h"
 #include "tusb.h"
 
-#define CFG_BOARD_UART_BAUDRATE    115200
+// Define the default baudrate
+#ifndef CFG_BOARD_UART_BAUDRATE
+#define CFG_BOARD_UART_BAUDRATE 115200   ///< Default baud rate
+#endif
 
 //--------------------------------------------------------------------+
 // Board Porting API

From 9ec92ff97bf5e4b5730925ff591ed9f044d2c847 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 30 Jun 2022 15:45:04 +0700
Subject: [PATCH 1106/2085] rp2040 enable SOF as resumed signal when remote
 wakeup

---
 src/device/usbd.c                            |  2 +-
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 25 +++++++++++++-------
 2 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 382efa4d1..c199e647e 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -316,7 +316,7 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
   for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
   {
     usbd_class_driver_t const * driver = get_driver(i);
-    if ( driver->control_xfer_cb == callback )
+    if ( driver && driver->control_xfer_cb == callback )
     {
       TU_LOG(USBD_DBG, "  %s control complete\r\n", driver->name);
       return;
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index c6018c515..2003f72fd 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -55,6 +55,9 @@ static uint8_t *next_buffer_ptr;
 // USB_MAX_ENDPOINTS Endpoints, direction TUSB_DIR_OUT for out and TUSB_DIR_IN for in.
 static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2];
 
+// SOF may be used by remote wakeup as RESUME, this indicate whether SOF is actually used by usbd
+static bool _sof_enable = false;
+
 TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint *hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir)
 {
   return &hw_endpoints[num][dir];
@@ -250,6 +253,10 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
     if (status & USB_INTF_DEV_SOF_BITS)
     {
       handled |= USB_INTF_DEV_SOF_BITS;
+
+      // disable SOF interrupt if it is used for RESUME in remote wakeup
+      if (!_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
+
       dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true);
     }
 
@@ -411,9 +418,13 @@ void dcd_set_address (__unused uint8_t rhport, __unused uint8_t dev_addr)
 
 void dcd_remote_wakeup(__unused uint8_t rhport)
 {
-    pico_info("dcd_remote_wakeup %d\n", rhport);
-    assert(rhport == 0);
-    usb_hw_set->sie_ctrl = USB_SIE_CTRL_RESUME_BITS;
+  pico_info("dcd_remote_wakeup %d\n", rhport);
+  assert(rhport == 0);
+
+  // since RESUME interrupt is not triggered if we are the one initiate
+  // briefly enable SOF to notify usbd when bus is ready
+  usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
+  usb_hw_set->sie_ctrl = USB_SIE_CTRL_RESUME_BITS;
 }
 
 // disconnect by disabling internal pull-up resistor on D+/D-
@@ -434,17 +445,15 @@ void dcd_sof_enable(uint8_t rhport, bool en)
 {
   (void) rhport;
 
-  uint32_t inte = usb_hw->inte;
+  _sof_enable = en;
 
   if (en)
   {
-    inte |= USB_INTS_DEV_SOF_BITS;
+    usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
   }else
   {
-    inte &= ~USB_INTS_DEV_SOF_BITS;
+    usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
   }
-
-  usb_hw->inte = inte;
 }
 
 /*------------------------------------------------------------------*/

From 60c1750a9bd79e46385680b35e12f116808894f7 Mon Sep 17 00:00:00 2001
From: robert-hh <robert@hammelrath.com>
Date: Thu, 30 Jun 2022 22:18:23 +0200
Subject: [PATCH 1107/2085] mimxrt: Add/change definitions for MIMXRT11XX
 boards.

These are mostly identical to the MIMXRT10XX, with one tiny difference.
---
 hw/bsp/board_mcu.h                        | 2 +-
 src/class/audio/audio_device.c            | 3 ++-
 src/common/tusb_mcu.h                     | 2 +-
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 5 +++++
 src/portable/chipidea/ci_hs/dcd_ci_hs.c   | 2 +-
 src/portable/chipidea/ci_hs/hcd_ci_hs.c   | 2 +-
 src/tusb_option.h                         | 1 +
 7 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 8202479cb..93b1d595f 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -110,7 +110,7 @@
 #elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI
   // no header needed
 
-#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX
   #include "fsl_device_registers.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_NUC120
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 6df68c559..ef0f9c4b7 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -66,7 +66,7 @@
 
 // Use ring buffer if it's available, some MCUs need extra RAM requirements
 #ifndef TUD_AUDIO_PREFER_RING_BUFFER
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX
 #define TUD_AUDIO_PREFER_RING_BUFFER 0
 #else
 #define TUD_AUDIO_PREFER_RING_BUFFER 1
@@ -103,6 +103,7 @@
     CFG_TUSB_MCU == OPT_MCU_LPC18XX                               || \
     CFG_TUSB_MCU == OPT_MCU_LPC43XX                               || \
     CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX                            || \
+    CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX                            || \
     CFG_TUSB_MCU == OPT_MCU_MSP432E4
 #if TUD_AUDIO_PREFER_RING_BUFFER
 #define  USE_LINEAR_BUFFER     0
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 383a8d686..37866f2a3 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -75,7 +75,7 @@
   // TODO USB0 has 5, USB1 has 6
   #define TUP_DCD_ENDPOINT_MAX    6
 
-#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX)
+#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX, OPT_MCU_MIMXRT11XX)
   #define TUP_USBIP_CHIPIDEA_HS
   #define TUP_USBIP_EHCI
 
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index 78ca5a5a2..a2a0c98f4 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -29,6 +29,11 @@
 
 #include "fsl_device_registers.h"
 
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX
+#define USB1_BASE USB_OTG1_BASE
+#define USB2_BASE USB_OTG2_BASE
+#endif
+
 static const ci_hs_controller_t _ci_controller[] =
 {
   // RT1010 and RT1020 only has 1 USB controller
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 41d2f1870..0925215ae 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -34,7 +34,7 @@
 #include "device/dcd.h"
 #include "ci_hs_type.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX
   #include "ci_hs_imxrt.h"
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 221721b0f..39b490f72 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -29,7 +29,7 @@
 // Chipidea Highspeed USB IP implement EHCI for host functionality
 
 #if CFG_TUH_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
+    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX)
 
 //--------------------------------------------------------------------+
 // INCLUDE
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 206d23e72..0749a5e52 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -99,6 +99,7 @@ typedef int make_iso_compilers_happy;
 
 // NXP iMX RT
 #define OPT_MCU_MIMXRT10XX        700 ///< NXP iMX RT10xx
+#define OPT_MCU_MIMXRT11XX        701 ///< NXP iMX RT11xx
 
 // Nuvoton
 #define OPT_MCU_NUC121            800

From ec6f56768a03fcc43158b0d429e8b826825d02f7 Mon Sep 17 00:00:00 2001
From: robert-hh <robert@hammelrath.com>
Date: Fri, 1 Jul 2022 08:42:46 +0200
Subject: [PATCH 1108/2085] mimxrt: Change OPT_MCU_MIMXRT1xXX to
 OPT_MCU_MIMXRT.

Which fits both MIMXRT10XX and MIMXRT11XX.
---
 hw/bsp/board_mcu.h                                   | 2 +-
 hw/bsp/f1c100s/README.md                             | 2 +-
 hw/bsp/imxrt/family.mk                               | 2 +-
 src/class/audio/audio_device.c                       | 5 ++---
 src/common/tusb_mcu.h                                | 2 +-
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h            | 2 +-
 src/portable/chipidea/ci_hs/dcd_ci_hs.c              | 2 +-
 src/portable/chipidea/ci_hs/hcd_ci_hs.c              | 4 ++--
 src/portable/nxp/transdimension/dcd_transdimension.c | 6 +++---
 src/portable/nxp/transdimension/hcd_transdimension.c | 6 +++---
 src/tusb_option.h                                    | 4 ++--
 11 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 93b1d595f..5c309a21d 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -110,7 +110,7 @@
 #elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI
   // no header needed
 
-#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX
+#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT
   #include "fsl_device_registers.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_NUC120
diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md
index 325044716..4aa1e153b 100644
--- a/hw/bsp/f1c100s/README.md
+++ b/hw/bsp/f1c100s/README.md
@@ -17,4 +17,4 @@ Flash: `make BOARD=f1c100s flash` will write the image to SPI flash, and then re
 
 ## TODO
 
-* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX` high speed MCU check in examples (maybe we should extract the logic?)
\ No newline at end of file
+* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT` high speed MCU check in examples (maybe we should extract the logic?)
\ No newline at end of file
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 0a55b740b..846ecd255 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -13,7 +13,7 @@ CFLAGS += \
   -D__ARMVFP__=0 -D__ARMFPV5__=0\
   -DXIP_EXTERNAL_FLASH=1 \
   -DXIP_BOOT_HEADER_ENABLE=1 \
-  -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX
+  -DCFG_TUSB_MCU=OPT_MCU_MIMXRT
 
 ifdef BOARD_TUD_RHPORT
 CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT)
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index ef0f9c4b7..473d1e910 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -66,7 +66,7 @@
 
 // Use ring buffer if it's available, some MCUs need extra RAM requirements
 #ifndef TUD_AUDIO_PREFER_RING_BUFFER
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX
+#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT
 #define TUD_AUDIO_PREFER_RING_BUFFER 0
 #else
 #define TUD_AUDIO_PREFER_RING_BUFFER 1
@@ -102,8 +102,7 @@
     CFG_TUSB_MCU == OPT_MCU_GD32VF103                             || \
     CFG_TUSB_MCU == OPT_MCU_LPC18XX                               || \
     CFG_TUSB_MCU == OPT_MCU_LPC43XX                               || \
-    CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX                            || \
-    CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX                            || \
+    CFG_TUSB_MCU == OPT_MCU_MIMXRT                                || \
     CFG_TUSB_MCU == OPT_MCU_MSP432E4
 #if TUD_AUDIO_PREFER_RING_BUFFER
 #define  USE_LINEAR_BUFFER     0
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 37866f2a3..baa82fc14 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -75,7 +75,7 @@
   // TODO USB0 has 5, USB1 has 6
   #define TUP_DCD_ENDPOINT_MAX    6
 
-#elif TU_CHECK_MCU(OPT_MCU_MIMXRT10XX, OPT_MCU_MIMXRT11XX)
+#elif TU_CHECK_MCU(OPT_MCU_MIMXRT)
   #define TUP_USBIP_CHIPIDEA_HS
   #define TUP_USBIP_EHCI
 
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index a2a0c98f4..53bc8bd00 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -29,7 +29,7 @@
 
 #include "fsl_device_registers.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX
+#if !defined(USB1_BASE) && defined(USB_OTG1_BASE)
 #define USB1_BASE USB_OTG1_BASE
 #define USB2_BASE USB_OTG2_BASE
 #endif
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 0925215ae..c7cc3e0e8 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -34,7 +34,7 @@
 #include "device/dcd.h"
 #include "ci_hs_type.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   #include "ci_hs_imxrt.h"
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 39b490f72..d0396daea 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -29,7 +29,7 @@
 // Chipidea Highspeed USB IP implement EHCI for host functionality
 
 #if CFG_TUH_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT11XX)
+    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT)
 
 //--------------------------------------------------------------------+
 // INCLUDE
@@ -39,7 +39,7 @@
 #include "portable/ehci/ehci_api.h"
 #include "ci_hs_type.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   #include "ci_hs_imxrt.h"
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 2347e1dae..1f27a6872 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -27,14 +27,14 @@
 #include "tusb_option.h"
 
 #if CFG_TUD_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
+    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT)
 
 #warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly"
 
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   #include "fsl_device_registers.h"
   #define INCLUDE_FSL_DEVICE_REGISTERS
 #else
@@ -153,7 +153,7 @@ typedef struct
   const uint8_t ep_count; // Max bi-directional Endpoints
 }dcd_controller_t;
 
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   static const dcd_controller_t _dcd_controller[] =
   {
     // RT1010 and RT1020 only has 1 USB controller
diff --git a/src/portable/nxp/transdimension/hcd_transdimension.c b/src/portable/nxp/transdimension/hcd_transdimension.c
index 2d0830981..392764ff6 100644
--- a/src/portable/nxp/transdimension/hcd_transdimension.c
+++ b/src/portable/nxp/transdimension/hcd_transdimension.c
@@ -29,14 +29,14 @@
 // NXP Trans-Dimension USB IP implement EHCI for host functionality
 
 #if CFG_TUH_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX)
+    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT)
 
 #warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly"
 
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   #include "fsl_device_registers.h"
 #else
   // LPCOpen for 18xx & 43xx
@@ -58,7 +58,7 @@ typedef struct
   const IRQn_Type irqnum; // IRQ number
 }hcd_controller_t;
 
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   static const hcd_controller_t _hcd_controller[] =
   {
     // RT1010 and RT1020 only has 1 USB controller
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 0749a5e52..a030197f6 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -98,8 +98,8 @@ typedef int make_iso_compilers_happy;
 #define OPT_MCU_VALENTYUSB_EPTRI  600 ///< Fomu eptri config
 
 // NXP iMX RT
-#define OPT_MCU_MIMXRT10XX        700 ///< NXP iMX RT10xx
-#define OPT_MCU_MIMXRT11XX        701 ///< NXP iMX RT11xx
+#define OPT_MCU_MIMXRT            700 ///< NXP iMX RT Series
+#define OPT_MCU_MIMXRT10XX        OPT_MCU_MIMXRT
 
 // Nuvoton
 #define OPT_MCU_NUC121            800

From 12341118e373cce10cb868f234009e9d37bff940 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Jul 2022 16:24:58 +0700
Subject: [PATCH 1109/2085] add get-deps target

update ci to get-deps first
---
 .github/workflows/build_arm.yml    | 13 +++++++++----
 docs/reference/getting_started.rst |  7 ++++++-
 examples/make.mk                   |  5 -----
 examples/rules.mk                  | 27 ++++++++++++++++++---------
 4 files changed, 33 insertions(+), 19 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 27cb9f1f7..7cc1b10f9 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -67,6 +67,11 @@ jobs:
     - name: Setup Python
       uses: actions/setup-python@v3
 
+    - name: Install ARM GCC
+      uses: carlosperate/arm-none-eabi-gcc-action@v1
+      with:
+        release: '11.2-2022.02'
+
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
@@ -86,10 +91,10 @@ jobs:
         echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
         git submodule update --init hw/mcu/raspberry_pi/Pico-PIO-USB
 
-    - name: Install ARM GCC
-      uses: carlosperate/arm-none-eabi-gcc-action@v1
-      with:
-        release: '11.2-2022.02'
+    - name: Get Dependencies
+      run: |
+        b=`find hw/bsp/${{ matrix.family }}/boards -depth -maxdepth 1 -type d -name '[^.]?*' -printf %f -quit`
+        make BOARD={b} get-deps
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index fa5c51eff..1088d4700 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -50,7 +50,12 @@ Some TinyUSB examples also requires external submodule libraries in ``/lib`` suc
 
    $ git submodule update --init lib
 
-In addition, MCU driver submodule is also needed to provide low-level MCU peripheral's driver. Luckily, it will be fetched if needed when you run the ``make`` to build your board.
+In addition, MCU driver submodule is also needed to provide low-level MCU peripheral's driver. To download these depencies for your board, run the ``get-dpes`` as follow.
+
+.. code-block::
+
+   $ make BOARD=feather_nrf52840_express get-deps
+
 
 Some modules will also require a module-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples.
 
diff --git a/examples/make.mk b/examples/make.mk
index 27e1db38c..47520d660 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -45,11 +45,6 @@ else
   SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(FAMILY_PATH)/*.c))
 endif
 
-# Fetch submodules depended by family
-fetch_submodule_if_empty = $(if $(wildcard $(TOP)/$1/*),,$(info $(shell git -C $(TOP) submodule update --init $1)))
-ifdef DEPS_SUBMODULES
-  $(foreach s,$(DEPS_SUBMODULES),$(call fetch_submodule_if_empty,$(s)))
-endif
 
 #-------------- Cross Compiler  ------------
 # Can be set by board, default to ARM GCC
diff --git a/examples/rules.mk b/examples/rules.mk
index 538dffbcf..c3134056a 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -5,6 +5,7 @@
 # Set all as default goal
 .DEFAULT_GOAL := all
 
+# ---------------- GNU Make Start -----------------------
 # ESP32-Sx and RP2040 has its own CMake build system
 ifeq (,$(findstring $(FAMILY),esp32s2 esp32s3 rp2040))
 
@@ -141,7 +142,23 @@ $(BUILD)/obj/%_asm.o: %.S
 	@echo AS $(notdir $@)
 	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
 
-endif # GNU Make
+endif
+
+.PHONY: clean
+clean:
+ifeq ($(CMDEXE),1)
+	rd /S /Q $(subst /,\,$(BUILD))
+else
+	$(RM) -rf $(BUILD)
+endif
+# ---------------- GNU Make End -----------------------
+
+# get depenecies
+.PHONY: get-deps
+get-deps:
+  ifdef DEPS_SUBMODULES
+	git -C $(TOP) submodule update --init $(DEPS_SUBMODULES)
+  endif
 
 size: $(BUILD)/$(PROJECT).elf
 	-@echo ''
@@ -152,14 +169,6 @@ size: $(BUILD)/$(PROJECT).elf
 linkermap: $(BUILD)/$(PROJECT).elf
 	@linkermap -v $<.map
 
-.PHONY: clean
-clean:
-ifeq ($(CMDEXE),1)
-	rd /S /Q $(subst /,\,$(BUILD))
-else
-	$(RM) -rf $(BUILD)
-endif
-
 # ---------------------------------------
 # Flash Targets
 # ---------------------------------------

From 5323472afd1f35d0e62bd58bb3293bcfce36483b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Jul 2022 16:37:34 +0700
Subject: [PATCH 1110/2085] update get-deps for ci

---
 .github/workflows/build_arm.yml | 2 +-
 tools/build_board.py            | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 7cc1b10f9..935d57e06 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -94,7 +94,7 @@ jobs:
     - name: Get Dependencies
       run: |
         b=`find hw/bsp/${{ matrix.family }}/boards -depth -maxdepth 1 -type d -name '[^.]?*' -printf %f -quit`
-        make BOARD={b} get-deps
+        make -C examples/device/board_test BOARD=${b} get-deps
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/tools/build_board.py b/tools/build_board.py
index 62a4ea82f..8d10ef820 100644
--- a/tools/build_board.py
+++ b/tools/build_board.py
@@ -1,6 +1,7 @@
 import os
 import sys
 import time
+import subprocess
 from multiprocessing import Pool
 
 import build_utils
@@ -38,6 +39,10 @@ if __name__ == '__main__':
     filter_with_input(all_boards)
     all_boards.sort()
 
+    # Get dependencies
+    for b in all_boards:
+        subprocess.run("make -C examples/device/board_test BOARD={} get-deps".format(b), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+
     print(build_separator)
     print(build_utils.build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
     total_time = time.monotonic()

From 53db23142a89def1ad2f866863a559a931eeb035 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 1 Jul 2022 17:23:14 +0700
Subject: [PATCH 1111/2085] add get-dependencies.py

---
 .github/workflows/build_aarch64.yml |  3 +++
 .github/workflows/build_arm.yml     | 15 ++++++---------
 .github/workflows/build_msp430.yml  |  3 +++
 .github/workflows/build_renesas.yml |  3 +++
 .github/workflows/build_riscv.yml   |  3 +++
 hw/bsp/rp2040/family.mk             |  2 ++
 tools/get_dependencies.py           | 25 +++++++++++++++++++++++++
 7 files changed, 45 insertions(+), 9 deletions(-)
 create mode 100644 tools/get_dependencies.py

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 1720ba592..b4ea8a0eb 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -55,6 +55,9 @@ jobs:
     - name: Set Toolchain Path
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
+    - name: Get Dependencies
+      run: python3 tools/get_dependencies.py ${{ matrix.family }}
+
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
 
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 935d57e06..4297ba895 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -89,12 +89,9 @@ jobs:
       run: |
         git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
         echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
-        git submodule update --init hw/mcu/raspberry_pi/Pico-PIO-USB
 
     - name: Get Dependencies
-      run: |
-        b=`find hw/bsp/${{ matrix.family }}/boards -depth -maxdepth 1 -type d -name '[^.]?*' -printf %f -quit`
-        make -C examples/device/board_test BOARD=${b} get-deps
+      run: python3 tools/get_dependencies.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
@@ -127,16 +124,16 @@ jobs:
     - name: Setup Python
       uses: actions/setup-python@v3
 
+    - name: Install ARM GCC
+      uses: carlosperate/arm-none-eabi-gcc-action@v1
+      with:
+        release: '11.2-2022.02'
+
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
     - name: Checkout common submodules in lib
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
-    - name: Install ARM GCC
-      uses: carlosperate/arm-none-eabi-gcc-action@v1
-      with:
-        release: '11.2-2022.02'
-
     - name: Build
       run: python3 tools/build_board.py ${{ matrix.example }}
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 6a468ab04..ea93f09a0 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -52,6 +52,9 @@ jobs:
     - name: Set Toolchain Path
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
+    - name: Get Dependencies
+      run: python3 tools/get_dependencies.py ${{ matrix.family }}
+
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
 
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 50618ff6b..2563d3549 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -53,6 +53,9 @@ jobs:
     - name: Set Toolchain Path
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
+    - name: Get Dependencies
+      run: python3 tools/get_dependencies.py ${{ matrix.family }}
+
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
 
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 2d670138d..90dc35206 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -53,6 +53,9 @@ jobs:
     - name: Set Toolchain Path
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
+    - name: Get Dependencies
+      run: python3 tools/get_dependencies.py ${{ matrix.family }}
+
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
 
diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk
index 5db784b14..cf6b53793 100644
--- a/hw/bsp/rp2040/family.mk
+++ b/hw/bsp/rp2040/family.mk
@@ -1,6 +1,8 @@
 JLINK_DEVICE = rp2040_m0_0
 PYOCD_TARGET = rp2040
 
+DEPS_SUBMODULES += hw/mcu/raspberry_pi/Pico-PIO-USB
+
 ifeq ($(DEBUG), 1)
 CMAKE_DEFSYM += -DCMAKE_BUILD_TYPE=Debug
 endif
diff --git a/tools/get_dependencies.py b/tools/get_dependencies.py
new file mode 100644
index 000000000..e7d3e0a76
--- /dev/null
+++ b/tools/get_dependencies.py
@@ -0,0 +1,25 @@
+import os
+import sys
+import subprocess
+
+
+# dependency lookup (ABC sorted)
+# deps = {
+#    'LPC11UXX' : [ [] ]
+# }
+
+
+def get_family_dep(family):
+    for entry in os.scandir("hw/bsp/{}/boards".format(family)):
+        if entry.is_dir():
+            result = subprocess.run("make -C examples/device/board_test BOARD={} get-deps".format(entry.name),
+                                    shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+            print(result.stdout.decode("utf-8"))
+            return result.returncode
+
+status = 0
+all_family = sys.argv[1:]
+for f in all_family:
+    status += get_family_dep(f)
+
+sys.exit(status)
\ No newline at end of file

From 54250d7dd5b22dee07138b925a4ad218a6defcc8 Mon Sep 17 00:00:00 2001
From: NConrad <pigrew@gmail.com>
Date: Sat, 9 Jul 2022 17:50:17 -0400
Subject: [PATCH 1112/2085] USBTMC: explicit type conversions fix

---
 src/class/usbtmc/usbtmc_device.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index c50ca65d5..af4a92732 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -603,23 +603,23 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
     if(ep_addr == usbtmc_state.ep_bulk_out)
     {
       criticalEnter();
-      usbd_edpt_stall(rhport, ep_addr);
-      usbd_edpt_clear_stall(rhport, ep_addr);
+      usbd_edpt_stall(rhport, (uint8_t)ep_addr);
+      usbd_edpt_clear_stall(rhport, (uint8_t)ep_addr);
       usbtmc_state.state = STATE_NAK; // USBD core has placed EP in NAK state for us
       criticalLeave();
       tud_usbtmc_bulkOut_clearFeature_cb();
     }
     else if (ep_addr == usbtmc_state.ep_bulk_in)
     {
-      usbd_edpt_stall(rhport, ep_addr);
-      usbd_edpt_clear_stall(rhport, ep_addr);
+      usbd_edpt_stall(rhport, (uint8_t)ep_addr);
+      usbd_edpt_clear_stall(rhport, (uint8_t)ep_addr);
       tud_usbtmc_bulkIn_clearFeature_cb();
     }
     else if ((usbtmc_state.ep_int_in != 0) && (ep_addr == usbtmc_state.ep_int_in))
     {
       // Clearing interrupt in EP
-      usbd_edpt_stall(rhport, ep_addr);
-      usbd_edpt_clear_stall(rhport, ep_addr);
+      usbd_edpt_stall(rhport, (uint8_t)ep_addr);
+      usbd_edpt_clear_stall(rhport, (uint8_t)ep_addr);
     }
      else
     {

From 19768936ae6379b4c86947f70ab5cf2c0f8ed8f4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 11 Jul 2022 14:01:18 +0700
Subject: [PATCH 1113/2085] bump up mcux-sdk for rt11xx, add back
 OPT_MCU_MIMXRT11XX

---
 examples/host/bare_api/only.txt           | 1 +
 examples/host/cdc_msc_hid/only.txt        | 1 +
 examples/host/hid_controller/only.txt     | 1 +
 hw/mcu/nxp/mcux-sdk                       | 2 +-
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 3 +++
 src/tusb_option.h                         | 5 +++--
 6 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index 7fe4e3f5c..da3ffdd19 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -4,6 +4,7 @@ mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
 mcu:MIMXRT10XX
+mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index 7fe4e3f5c..da3ffdd19 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -4,6 +4,7 @@ mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
 mcu:MIMXRT10XX
+mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index 7fe4e3f5c..da3ffdd19 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -4,6 +4,7 @@ mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
 mcu:MIMXRT10XX
+mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
diff --git a/hw/mcu/nxp/mcux-sdk b/hw/mcu/nxp/mcux-sdk
index cb21c6609..ae2ab01d9 160000
--- a/hw/mcu/nxp/mcux-sdk
+++ b/hw/mcu/nxp/mcux-sdk
@@ -1 +1 @@
-Subproject commit cb21c660991c92e90ece99ccb63a4bc611899c3a
+Subproject commit ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index 53bc8bd00..2de0d9cb4 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -31,6 +31,9 @@
 
 #if !defined(USB1_BASE) && defined(USB_OTG1_BASE)
 #define USB1_BASE USB_OTG1_BASE
+#endif
+
+#if !defined(USB2_BASE) && defined(USB_OTG2_BASE)
 #define USB2_BASE USB_OTG2_BASE
 #endif
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a030197f6..70ef1c399 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -98,8 +98,9 @@ typedef int make_iso_compilers_happy;
 #define OPT_MCU_VALENTYUSB_EPTRI  600 ///< Fomu eptri config
 
 // NXP iMX RT
-#define OPT_MCU_MIMXRT            700 ///< NXP iMX RT Series
-#define OPT_MCU_MIMXRT10XX        OPT_MCU_MIMXRT
+#define OPT_MCU_MIMXRT            700             ///< NXP iMX RT Series
+#define OPT_MCU_MIMXRT10XX        OPT_MCU_MIMXRT  ///< RT10xx
+#define OPT_MCU_MIMXRT11XX        OPT_MCU_MIMXRT  ///< RT11xx
 
 // Nuvoton
 #define OPT_MCU_NUC121            800

From 6da1e93edd4547a5ec5a1681cd1cb31803564993 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 11 Jul 2022 14:21:19 +0700
Subject: [PATCH 1114/2085] fix rt1050 evk build with latest mcu-sdk

---
 examples/host/bare_api/only.txt             | 1 +
 examples/host/cdc_msc_hid/only.txt          | 1 +
 examples/host/hid_controller/only.txt       | 1 +
 hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h | 4 ++--
 4 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index da3ffdd19..fa9c14857 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -3,6 +3,7 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
+mcu:MIMXRT
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index da3ffdd19..fa9c14857 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -3,6 +3,7 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
+mcu:MIMXRT
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index da3ffdd19..fa9c14857 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -3,6 +3,7 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
+mcu:MIMXRT
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
index 928fbd727..0472f608c 100644
--- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
@@ -45,7 +45,7 @@
 
 // UART
 #define UART_PORT             LPUART1
-#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_13_LPUART1_RX
-#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_12_LPUART1_TX
+#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
+#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
 
 #endif /* BOARD_H_ */

From bb5dbd2da838773d8c1443ce52096ab9de63df19 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 11 Jul 2022 23:57:34 +0700
Subject: [PATCH 1115/2085] only enable warnings with approriate gcc version
 for rp2040

---
 examples/example.cmake | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/examples/example.cmake b/examples/example.cmake
index 3e395d53f..6b5e41dd9 100644
--- a/examples/example.cmake
+++ b/examples/example.cmake
@@ -4,28 +4,29 @@ target_compile_options(${PROJECT} PUBLIC
         -Werror
         -Wfatal-errors
         -Wdouble-promotion
-        #-Wstrict-prototypes
-        -Wstrict-overflow
-        #-Werror-implicit-function-declaration
         -Wfloat-equal
-        #-Wundef
         -Wshadow
         -Wwrite-strings
         -Wsign-compare
         -Wmissing-format-attribute
         -Wunreachable-code
         -Wcast-align
-        -Wcast-function-type
         -Wcast-qual
         -Wnull-dereference
         -Wuninitialized
         -Wunused
         -Wredundant-decls
+        #-Wstrict-prototypes
+        #-Werror-implicit-function-declaration
+        #-Wundef
         )
 
-# GCC version 9 or prior has a bug with incorrect Wconversion warnings
+# GCC 10
 if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
-  target_compile_options(${PROJECT} PUBLIC
-        -Wconversion
-        )
+  target_compile_options(${PROJECT} PUBLIC -Wconversion)
+endif()
+
+# GCC 8
+if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
+  target_compile_options(${PROJECT} PUBLIC -Wcast-function-type -Wstrict-overflow)
 endif()

From 345558307d06338fdc2c79d88c95c8d97bdeeeb0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 12 Jul 2022 00:50:52 +0700
Subject: [PATCH 1116/2085] fix incorrect null-dereference warnings when
 compiling with gcc7

---
 src/host/usbh.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index b6a03b82e..0415a26cb 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -123,7 +123,6 @@ typedef struct {
 
 // Invalid driver ID in itf2drv[] ep2drv[][] mapping
 enum { DRVID_INVALID = 0xFFu };
-enum { ADDR_INVALID  = 0xFFu };
 enum { CONTROLLER_INVALID = 0xFFu };
 
 #if CFG_TUSB_DEBUG >= 2
@@ -1434,7 +1433,8 @@ static uint8_t get_new_address(bool is_hub)
   {
     if (!_usbh_devices[idx].connected) return (idx+1);
   }
-  return ADDR_INVALID;
+
+  return 0; // invalid address
 }
 
 static bool enum_request_set_addr(void)
@@ -1443,7 +1443,7 @@ static bool enum_request_set_addr(void)
 
   // Get new address
   uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
-  TU_ASSERT(new_addr != ADDR_INVALID);
+  TU_ASSERT(new_addr != 0);
 
   TU_LOG2("Set Address = %d\r\n", new_addr);
 

From 4ea27acd1da9e0144dbfbf805b87b22d16f7db8c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 12 Jul 2022 01:55:33 +0700
Subject: [PATCH 1117/2085] minor update to webusb serial example

---
 examples/device/webusb_serial/src/main.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index 8eaad7706..604d30a83 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -71,7 +71,7 @@ enum  {
 
 static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
-#define URL  "example.tinyusb.org/webusb-serial/"
+#define URL  "example.tinyusb.org/webusb-serial/index.html"
 
 const tusb_desc_webusb_url_t desc_url =
 {
@@ -114,6 +114,7 @@ void echo_all(uint8_t buf[], uint32_t count)
   if ( web_serial_connected )
   {
     tud_vendor_write(buf, count);
+    tud_vendor_flush();
   }
 
   // echo to cdc
@@ -211,7 +212,8 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ
           board_led_write(true);
           blink_interval_ms = BLINK_ALWAYS_ON;
 
-          tud_vendor_write_str("\r\nTinyUSB WebUSB device example\r\n");
+          tud_vendor_write_str("\r\nWebUSB interface connected\r\n");
+          tud_vendor_flush();
         }else
         {
           blink_interval_ms = BLINK_MOUNTED;

From fc1a27b6c9d5a19529d6ac968164f2734ea89023 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Tue, 12 Jul 2022 12:58:30 -0500
Subject: [PATCH 1118/2085] RP@040: rework CMake for compiler warnings

---
 .../device/audio_4_channel_mic/CMakeLists.txt |  3 -
 examples/device/audio_test/CMakeLists.txt     |  3 -
 examples/device/board_test/CMakeLists.txt     |  3 -
 examples/device/cdc_dual_ports/CMakeLists.txt |  3 -
 examples/device/cdc_msc/CMakeLists.txt        |  3 -
 examples/device/dfu/CMakeLists.txt            |  3 -
 examples/device/dfu_runtime/CMakeLists.txt    |  3 -
 .../dynamic_configuration/CMakeLists.txt      |  3 -
 .../device/hid_boot_interface/CMakeLists.txt  |  3 -
 examples/device/hid_composite/CMakeLists.txt  |  3 -
 .../device/hid_generic_inout/CMakeLists.txt   |  3 -
 .../hid_multiple_interface/CMakeLists.txt     |  3 -
 examples/device/midi_test/CMakeLists.txt      |  3 -
 examples/device/msc_dual_lun/CMakeLists.txt   |  3 -
 .../device/net_lwip_webserver/CMakeLists.txt  |  3 -
 examples/device/uac2_headset/CMakeLists.txt   |  3 -
 examples/device/usbtmc/CMakeLists.txt         |  3 -
 examples/device/video_capture/CMakeLists.txt  |  3 -
 examples/device/webusb_serial/CMakeLists.txt  |  3 -
 .../host_hid_to_device_cdc/CMakeLists.txt     |  9 +--
 examples/example.cmake                        | 32 ---------
 examples/host/bare_api/CMakeLists.txt         |  3 -
 examples/host/cdc_msc_hid/CMakeLists.txt      |  3 -
 examples/host/hid_controller/CMakeLists.txt   |  3 -
 hw/bsp/family_support.cmake                   | 37 ++++++++++
 hw/bsp/rp2040/family.cmake                    | 71 +++++++++++--------
 src/portable/raspberrypi/rp2040/rp2040_usb.c  |  2 +
 27 files changed, 85 insertions(+), 132 deletions(-)
 delete mode 100644 examples/example.cmake

diff --git a/examples/device/audio_4_channel_mic/CMakeLists.txt b/examples/device/audio_4_channel_mic/CMakeLists.txt
index e6ce2813e..f6e10e2ea 100644
--- a/examples/device/audio_4_channel_mic/CMakeLists.txt
+++ b/examples/device/audio_4_channel_mic/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
 )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt
index 416b91665..cb321f9a8 100644
--- a/examples/device/audio_test/CMakeLists.txt
+++ b/examples/device/audio_test/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
 )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index ac530a928..37113578e 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -36,9 +36,6 @@ else()
           ${CMAKE_CURRENT_SOURCE_DIR}/src
           )
 
-  # Example common such as compiler warnings
-  include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
   # Configure compilation flags and libraries for the example... see the corresponding function
   # in hw/bsp/FAMILY/family.cmake for details.
   family_configure_device_example(${PROJECT})
diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt
index 438635958..abc4d91da 100644
--- a/examples/device/cdc_dual_ports/CMakeLists.txt
+++ b/examples/device/cdc_dual_ports/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index 04c7c1b26..fa6e83b7e 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -24,9 +24,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/dfu/CMakeLists.txt b/examples/device/dfu/CMakeLists.txt
index 121ab3852..acaa54198 100644
--- a/examples/device/dfu/CMakeLists.txt
+++ b/examples/device/dfu/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt
index 438635958..abc4d91da 100644
--- a/examples/device/dfu_runtime/CMakeLists.txt
+++ b/examples/device/dfu_runtime/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt
index 04c7c1b26..fa6e83b7e 100644
--- a/examples/device/dynamic_configuration/CMakeLists.txt
+++ b/examples/device/dynamic_configuration/CMakeLists.txt
@@ -24,9 +24,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/hid_boot_interface/CMakeLists.txt b/examples/device/hid_boot_interface/CMakeLists.txt
index 438635958..abc4d91da 100644
--- a/examples/device/hid_boot_interface/CMakeLists.txt
+++ b/examples/device/hid_boot_interface/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt
index 438635958..abc4d91da 100644
--- a/examples/device/hid_composite/CMakeLists.txt
+++ b/examples/device/hid_composite/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt
index 438635958..abc4d91da 100644
--- a/examples/device/hid_generic_inout/CMakeLists.txt
+++ b/examples/device/hid_generic_inout/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt
index 438635958..abc4d91da 100644
--- a/examples/device/hid_multiple_interface/CMakeLists.txt
+++ b/examples/device/hid_multiple_interface/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt
index 438635958..abc4d91da 100644
--- a/examples/device/midi_test/CMakeLists.txt
+++ b/examples/device/midi_test/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt
index 518eac3ad..9e834ae21 100644
--- a/examples/device/msc_dual_lun/CMakeLists.txt
+++ b/examples/device/msc_dual_lun/CMakeLists.txt
@@ -24,9 +24,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 0f41b888a..9fe1a325e 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -69,9 +69,6 @@ if (EXISTS ${TOP}/lib/lwip/src)
             ${TOP}/lib/networking/rndis_reports.c
             )
 
-    # Example common such as compiler warnings
-    include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
     # due to warnings from other net source, we need to prevent error from some of the warnings options
     target_compile_options(${PROJECT} PUBLIC
         -Wno-error=null-dereference
diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt
index 438635958..abc4d91da 100644
--- a/examples/device/uac2_headset/CMakeLists.txt
+++ b/examples/device/uac2_headset/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt
index 74f81b24f..c49603c26 100644
--- a/examples/device/usbtmc/CMakeLists.txt
+++ b/examples/device/usbtmc/CMakeLists.txt
@@ -24,9 +24,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt
index 416b91665..cb321f9a8 100644
--- a/examples/device/video_capture/CMakeLists.txt
+++ b/examples/device/video_capture/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
 )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt
index 438635958..abc4d91da 100644
--- a/examples/device/webusb_serial/CMakeLists.txt
+++ b/examples/device/webusb_serial/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index 909ee423f..fc9bbfc13 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -23,8 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_dual_usb_example(${PROJECT})
 
 # due to warnings from other net source, we need to prevent error from some of the warnings options
 target_compile_options(${PROJECT} PUBLIC
@@ -37,7 +38,3 @@ target_compile_options(${PROJECT} PUBLIC
         -Wno-error=sign-compare
         -Wno-error=unused-function
         )
-
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_dual_usb_example(${PROJECT})
diff --git a/examples/example.cmake b/examples/example.cmake
deleted file mode 100644
index 6b5e41dd9..000000000
--- a/examples/example.cmake
+++ /dev/null
@@ -1,32 +0,0 @@
-target_compile_options(${PROJECT} PUBLIC
-        -Wall
-        -Wextra
-        -Werror
-        -Wfatal-errors
-        -Wdouble-promotion
-        -Wfloat-equal
-        -Wshadow
-        -Wwrite-strings
-        -Wsign-compare
-        -Wmissing-format-attribute
-        -Wunreachable-code
-        -Wcast-align
-        -Wcast-qual
-        -Wnull-dereference
-        -Wuninitialized
-        -Wunused
-        -Wredundant-decls
-        #-Wstrict-prototypes
-        #-Werror-implicit-function-declaration
-        #-Wundef
-        )
-
-# GCC 10
-if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
-  target_compile_options(${PROJECT} PUBLIC -Wconversion)
-endif()
-
-# GCC 8
-if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
-  target_compile_options(${PROJECT} PUBLIC -Wcast-function-type -Wstrict-overflow)
-endif()
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 98540ffb0..bc04b01a7 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -22,9 +22,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 6990e957b..c4a4d8e63 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -24,9 +24,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index eefeb4a49..6153d399a 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -23,9 +23,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Example common such as compiler warnings
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../example.cmake)
-
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index ee29caba7..75bd97cb6 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -79,6 +79,43 @@ if (NOT TARGET _family_support_marker)
         endif()
     endfunction()
 
+    function(family_add_default_example_warnings TARGET)
+        target_compile_options(${TARGET} PUBLIC
+                -Wall
+                -Wextra
+                -Werror
+                -Wfatal-errors
+                -Wdouble-promotion
+                -Wfloat-equal
+                -Wshadow
+                -Wwrite-strings
+                -Wsign-compare
+                -Wmissing-format-attribute
+                -Wunreachable-code
+                -Wcast-align
+                -Wcast-qual
+                -Wnull-dereference
+                -Wuninitialized
+                -Wunused
+                -Wredundant-decls
+                #-Wstrict-prototypes
+                #-Werror-implicit-function-declaration
+                #-Wundef
+                )
+
+        if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+            # GCC 10
+            if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
+                target_compile_options(${TARGET} PUBLIC -Wconversion)
+            endif()
+
+            # GCC 8
+            if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
+                target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow)
+            endif()
+        endif()
+    endfunction()
+
     # configure an executable target to link to tinyusb in device mode, and add the board implementation
     function(family_configure_device_example TARGET)
         # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 530d80fec..31e97d9af 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -147,16 +147,23 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board tinyusb_additions)
 	endfunction()
 
+	function(rp2040_family_configure_example_warnings TARGET)
+		if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS)
+			family_add_default_example_warnings(${TARGET})
+		endif()
+		suppress_tinyusb_warnings()
+	endfunction()
+
 	function(family_configure_device_example TARGET)
 		family_configure_target(${TARGET})
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device)
-		suppress_tinyusb_warnings()
+		rp2040_family_configure_example_warnings(${TARGET})
 	endfunction()
 
 	function(family_configure_host_example TARGET)
 		family_configure_target(${TARGET})
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
-		suppress_tinyusb_warnings()
+		rp2040_family_configure_example_warnings(${TARGET})
 	endfunction()
 
 	function(family_add_pico_pio_usb TARGET)
@@ -167,7 +174,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		family_configure_target(${TARGET})
 		# require tinyusb_pico_pio_usb
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb )
-		suppress_tinyusb_warnings()
+		rp2040_family_configure_example_warnings(${TARGET})
 	endfunction()
 
 	function(check_and_add_pico_pio_usb_support)
@@ -236,30 +243,38 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
 	function(suppress_tinyusb_warnings)
 		# some of these are pretty silly warnings only occurring in some older GCC versions 9 or prior
-		if (CMAKE_C_COMPILER_VERSION VERSION_LESS 10.0)
-  		set(CONVERSION_WARNING_FILES
-  				${PICO_TINYUSB_PATH}/src/tusb.c
-  				${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
-  				${PICO_TINYUSB_PATH}/src/device/usbd.c
-  				${PICO_TINYUSB_PATH}/src/device/usbd_control.c
-  				${PICO_TINYUSB_PATH}/src/host/usbh.c
-  				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
-  				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
-  				${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c
-  				${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c
-  				${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c
-  				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c
-  				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c
-  				${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c
-  				${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c
-  				${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
-  				)
-  		foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES)
-  			set_source_files_properties(
-  					${SOURCE_FILE}
-  					PROPERTIES
-  					COMPILE_FLAGS "-Wno-conversion")
-  		endforeach()
-  	endif()
+		if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+			if (CMAKE_C_COMPILER_VERSION VERSION_LESS 10.0)
+				set(CONVERSION_WARNING_FILES
+					${PICO_TINYUSB_PATH}/src/tusb.c
+					${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
+					${PICO_TINYUSB_PATH}/src/device/usbd.c
+					${PICO_TINYUSB_PATH}/src/device/usbd_control.c
+					${PICO_TINYUSB_PATH}/src/host/usbh.c
+					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
+					${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c
+					${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c
+					${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c
+					${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c
+					${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c
+					${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c
+					${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c
+					${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+					)
+				foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES)
+					set_source_files_properties(
+							${SOURCE_FILE}
+							PROPERTIES
+							COMPILE_FLAGS "-Wno-conversion")
+				endforeach()
+			endif()
+			if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0)
+				set_source_files_properties(
+						${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c
+						PROPERTIES
+						COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds")
+			endif()
+		endif()
 	endfunction()
 endif()
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 49be90167..25c013bd2 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -60,7 +60,9 @@ void rp2040_usb_init(void)
   // Clear any previous state just in case
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Warray-bounds"
+#if __GNUC__ > 6
 #pragma GCC diagnostic ignored "-Wstringop-overflow"
+#endif
   memset(usb_hw, 0, sizeof(*usb_hw));
   memset(usb_dpram, 0, sizeof(*usb_dpram));
 #pragma GCC diagnostic pop

From 4bd47bcb99eef7a71ba2d45842af43e6269c30d4 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Tue, 12 Jul 2022 13:29:47 -0500
Subject: [PATCH 1119/2085] disable bad gcc 6 warning

---
 hw/bsp/family_support.cmake | 5 +++++
 src/host/usbh.c             | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 75bd97cb6..c5311b63f 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -113,6 +113,11 @@ if (NOT TARGET _family_support_marker)
             if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
                 target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow)
             endif()
+
+            # GCC 6
+            if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0)
+                target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing)
+            endif()
         endif()
     endfunction()
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 0415a26cb..26351d16a 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -655,7 +655,9 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
           TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) );
           return true;
         }
+#if __GNUC__ >= 7
         __attribute__((fallthrough));
+#endif
 
       case CONTROL_STAGE_DATA:
         if (request->wLength)

From 7e4c0f64cd32ee0c73da37703dda2f83ed760132 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 14 Jul 2022 18:39:47 +0700
Subject: [PATCH 1120/2085] abtract attribute fallthrough

---
 src/common/tusb_compiler.h | 10 ++++++++++
 src/host/usbh.c            |  4 +---
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index ae00f4e75..2c30daf6f 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -131,6 +131,12 @@
   #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
   #define TU_ATTR_BIT_FIELD_ORDER_END
 
+  #if __has_attribute(__fallthrough__)
+    #define TU_ATTR_FALLTHROUGH         __attribute__((fallthrough))
+  #else
+    #define TU_ATTR_FALLTHROUGH         do {} while (0)  /* fallthrough */
+  #endif
+
   // Endian conversion use well-known host to network (big endian) naming
   #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
     #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
@@ -156,6 +162,7 @@
   #define TU_ATTR_DEPRECATED(mess)      __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))
+  #define TU_ATTR_FALLTHROUGH           __attribute__((fallthrough))
 
   #define TU_ATTR_PACKED_BEGIN
   #define TU_ATTR_PACKED_END
@@ -182,6 +189,7 @@
   #define TU_ATTR_DEPRECATED(mess)      __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))             // Function/Variable is meant to be used
+  #define TU_ATTR_FALLTHROUGH           __attribute__((fallthrough))
 
   #define TU_ATTR_PACKED_BEGIN
   #define TU_ATTR_PACKED_END
@@ -207,6 +215,7 @@
   #define TU_ATTR_DEPRECATED(mess)
   #define TU_ATTR_UNUSED
   #define TU_ATTR_USED
+  #define TU_ATTR_FALLTHROUGH           do {} while (0)  /* fallthrough */
 
   #define TU_ATTR_PACKED_BEGIN          _Pragma("pack")
   #define TU_ATTR_PACKED_END            _Pragma("packoption")
@@ -227,6 +236,7 @@
   #error "Compiler attribute porting is required"
 #endif
 
+
 #if (TU_BYTE_ORDER == TU_LITTLE_ENDIAN)
 
   #define tu_htons(u16)  (TU_BSWAP16(u16))
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 26351d16a..9d618db92 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -655,9 +655,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
           TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) );
           return true;
         }
-#if __GNUC__ >= 7
-        __attribute__((fallthrough));
-#endif
+        TU_ATTR_FALLTHROUGH;
 
       case CONTROL_STAGE_DATA:
         if (request->wLength)

From b495d6f8ec263e51b0683ab85ff9e54dab6f5fd3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 17 Jul 2022 22:46:16 +0700
Subject: [PATCH 1121/2085] temporarily revert len back to uint8_t in
 tud_hid_report_complete_cb() for up coming release

---
 examples/device/hid_boot_interface/src/main.c     | 2 +-
 examples/device/hid_composite/src/main.c          | 2 +-
 examples/device/hid_composite_freertos/src/main.c | 2 +-
 src/class/hid/hid_device.c                        | 2 +-
 src/class/hid/hid_device.h                        | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 1958d614d..71afa3f46 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -181,7 +181,7 @@ void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len)
 {
   (void) instance;
   (void) report;
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 05315f266..f7d76cfc7 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -225,7 +225,7 @@ void hid_task(void)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len)
 {
   (void) instance;
   (void) len;
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index ea8d917fe..b67c10937 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -294,7 +294,7 @@ void hid_task(void* param)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len)
 {
   (void) instance;
   (void) len;
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 2d46d760f..8077e4deb 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -403,7 +403,7 @@ bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   {
     if (tud_hid_report_complete_cb)
     {
-      tud_hid_report_complete_cb(instance, p_hid->epin_buf, (uint16_t) xferred_bytes);
+      tud_hid_report_complete_cb(instance, p_hid->epin_buf, (/*uint16_t*/ uint8_t) xferred_bytes);
     }
   }
   // Received report
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 3714d2769..3143b1024 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -116,7 +116,7 @@ TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate);
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len);
+TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len );
 
 
 //--------------------------------------------------------------------+

From b0b155c9491d9e8cfc3d40366f77accfd3302cec Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 19 Jul 2022 12:28:52 +0700
Subject: [PATCH 1122/2085] increase version for release

along with minor doc update
---
 README.rst                         |  4 ++--
 docs/reference/getting_started.rst | 19 +++++++++----------
 src/tusb_option.h                  |  2 +-
 3 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/README.rst b/README.rst
index 1a96f6e16..92cb0ba6c 100644
--- a/README.rst
+++ b/README.rst
@@ -94,8 +94,8 @@ TinyUSB is completely thread-safe by pushing all Interrupt Service Request (ISR)
 - `RT-Thread <https://github.com/RT-Thread/rt-thread>`_: `repo <https://github.com/RT-Thread-packages/tinyusb>`_
 - **Mynewt** Due to the newt package build system, Mynewt examples are better to be on its `own repo <https://github.com/hathach/mynewt-tinyusb-example>`_
 
-Local Docs
-==========
+Docs
+====
 
 - Info
 
diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index 1088d4700..3cdb46849 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -50,16 +50,7 @@ Some TinyUSB examples also requires external submodule libraries in ``/lib`` suc
 
    $ git submodule update --init lib
 
-In addition, MCU driver submodule is also needed to provide low-level MCU peripheral's driver. To download these depencies for your board, run the ``get-dpes`` as follow.
-
-.. code-block::
-
-   $ make BOARD=feather_nrf52840_express get-deps
-
-
-Some modules will also require a module-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples.
-
-Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``/examples/device/99-tinyusb.rules`` file to /etc/udev/rules.d/ then run ``sudo udevadm control --reload-rules && sudo udevadm trigger`` is good enough.
+Some ports will also require a port-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples. They are out of scope for tinyusb, you should download/install it first according to its manufacturer guide. 
 
 Build
 ^^^^^
@@ -70,6 +61,13 @@ To build example, first change directory to an example folder.
 
    $ cd examples/device/cdc_msc
 
+Before building, we need to download MCU driver submodule to provide low-level MCU peripheral's driver first. Run the ``get-dpes`` target in one of the example folder as follow. You only need to do this once per mcu
+
+.. code-block::
+
+   $ make BOARD=feather_nrf52840_express get-deps
+
+
 Some modules (e.g. RP2040 and ESP32s2) require the project makefiles to be customized using CMake. If necessary apply any setup steps for the platform's SDK.
 
 Then compile with ``make BOARD=[board_name] all``\ , for example
@@ -79,6 +77,7 @@ Then compile with ``make BOARD=[board_name] all``\ , for example
    $ make BOARD=feather_nrf52840_express all
 
 Note: ``BOARD`` can be found as directory name in ``hw/bsp``\ , either in its family/boards or directly under bsp (no family).
+Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``/examples/device/99-tinyusb.rules`` file to /etc/udev/rules.d/ then run ``sudo udevadm control --reload-rules && sudo udevadm trigger`` is good enough.
 
 Port Selection
 ~~~~~~~~~~~~~~
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 70ef1c399..a557c785a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -33,7 +33,7 @@ typedef int make_iso_compilers_happy;
 #include "common/tusb_compiler.h"
 
 #define TUSB_VERSION_MAJOR     0
-#define TUSB_VERSION_MINOR     13
+#define TUSB_VERSION_MINOR     14
 #define TUSB_VERSION_REVISION  0
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
 

From 23ea8d1e255b00be6916f7d3ca0a1fba60c68ef4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Jul 2022 22:27:33 +0700
Subject: [PATCH 1123/2085] update doc

---
 README.rst                   | 2 +-
 docs/reference/supported.rst | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index 92cb0ba6c..ba176a8c8 100644
--- a/README.rst
+++ b/README.rst
@@ -43,7 +43,7 @@ The stack supports the following MCUs:
 - **Nuvoton:** NUC120, NUC121/NUC125, NUC126, NUC505
 - **NXP:**
 
-  - iMX RT Series: RT1011, RT1015, RT1021, RT1052, RT1062, RT1064
+  - iMX RT Series: RT10xx, RT11xx
   - Kinetis: KL25, K32L2
   - LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
 
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 7ce982713..ad2af98ff 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -41,6 +41,8 @@ Supported MCUs
 |              | NUC505                | ✔      |      | ✔         |                   |              |
 +--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
 | NXP          | iMXRT   | RT10xx      | ✔      | ✔    | ✔         | ci_hs             |              |
+|              |         +-------------+--------+------+-----------+-------------------+--------------+
+|              |         | RT11xx      | ✔      | ✔    | ✔         | ci_hs             |              |
 |              +---------+-------------+--------+------+-----------+-------------------+--------------+
 |              | Kinetis | KL25        | ✔      | ⚠    | ✖         |                   |              |
 |              |         +-------------+--------+------+-----------+-------------------+--------------+

From 0be6db50f873ccba3781aa3dd4fbc9b0fd46f38e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 23 Jul 2022 18:39:22 +0700
Subject: [PATCH 1124/2085] test self-hosted

---
 .github/workflows/build_arm.yml     | 24 ++++++++++++++++++-
 .github/workflows/test_hardware.yml | 37 +++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+), 1 deletion(-)
 create mode 100644 .github/workflows/test_hardware.yml

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 4297ba895..64322082d 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -99,11 +99,33 @@ jobs:
     - name: Linker Map
       run: |
         pip install linkermap/
-        for ex in `ls -d examples/device/*/`; do \
+        # find -quit to only print map of 1 board per example
+        for ex in `ls -d examples/*/*/`; do \
           find ${ex} -name *.map -print -quit | \
           xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
         done
 
+    # Following steps are for Hardware Test with self-hosted
+
+    - name: Prepare Artifacts
+      if: matrix.family == 'rp2040'
+      run: find examples/ -name "*.elf" -exec mv {} . \;
+
+    - name: Upload Artifacts for Hardware Test
+      if: matrix.family == 'rp2040'
+      uses: actions/upload-artifact@v3
+      with:
+        name: ${{ matrix.family }}
+        path: |
+          *.elf
+
+    - name: Trigger Hardware Test
+      if: matrix.family == 'rp2040'
+      uses: benc-uk/workflow-dispatch@v1
+      with:
+        workflow: Hardware Test
+        token: ${{ secrets.TRIGGER_SELF_HOSTED }}
+            
   # ---------------------------------------
   # Build all no-family (orphaned) boards
   # ---------------------------------------
diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
new file mode 100644
index 000000000..a39fb6927
--- /dev/null
+++ b/.github/workflows/test_hardware.yml
@@ -0,0 +1,37 @@
+name: Hardware Test
+on:
+  workflow_dispatch:
+
+# Hardware in the loop (HIL)
+# Current self-hosted instance is running on an RPI4 with
+# - pico + pico-probe connected via USB
+
+jobs:
+  hw-test:
+    # Limit the run to only hathach due to limited resource on RPI4
+    #if: github.repository_owner == 'hathach' && ${{ github.event.workflow_run.conclusion == 'success' }}
+    if: github.repository_owner == 'hathach'
+    runs-on: [self-hosted, Linux, ARM64]
+
+    steps:
+    - name: Test self-host
+      run: |
+        echo "Running on self-hosted"
+        ls
+        
+    - name: Download rp2040 Artifacts
+      uses: dawidd6/action-download-artifact@v2
+      with:
+        workflow: build_arm.yml
+        name: rp2040
+        
+    - name: List
+      run: ls
+
+#    - name: Clean workspace
+#      run: |
+#        echo "Cleaning up previous run"
+#        rm -rf "${{ github.workspace }}"
+#        mkdir -p "${{ github.workspace }}"
+
+    
\ No newline at end of file

From d15a86bc69a31fd0637661f44b6a7d53b80a5cad Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Jul 2022 16:49:51 +0700
Subject: [PATCH 1125/2085] test flash and hw test with cdc msc

---
 .github/workflows/test_hardware.yml | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index a39fb6927..923cd4f0a 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -14,10 +14,11 @@ jobs:
     runs-on: [self-hosted, Linux, ARM64]
 
     steps:
-    - name: Test self-host
+    - name: Clean workspace
       run: |
-        echo "Running on self-hosted"
-        ls
+        echo "Cleaning up previous run"
+        rm -rf "${{ github.workspace }}"
+        mkdir -p "${{ github.workspace }}"
         
     - name: Download rp2040 Artifacts
       uses: dawidd6/action-download-artifact@v2
@@ -25,13 +26,13 @@ jobs:
         workflow: build_arm.yml
         name: rp2040
         
-    - name: List
-      run: ls
-
-#    - name: Clean workspace
-#      run: |
-#        echo "Cleaning up previous run"
-#        rm -rf "${{ github.workspace }}"
-#        mkdir -p "${{ github.workspace }}"
-
-    
\ No newline at end of file
+    - name: Flash cdc_msc
+      run: openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program cdc_msc.elf verify reset exit" 
+ 
+    - name: Test
+      run: |
+        test -e /dev/ttyACM1
+        test -e /media/pi/TinyUSB\ MSC/README.TXT
+        cat /media/pi/TinyUSB\ MSC/README.TXT
+        # failed on purpose
+        test -e /dev/ttyACM2

From 95c0262cd68edbafeb5b8154cf7693d63c26c07f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Jul 2022 22:55:47 +0700
Subject: [PATCH 1126/2085] update test

---
 .github/workflows/test_hardware.yml | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 923cd4f0a..93440754e 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -5,6 +5,7 @@ on:
 # Hardware in the loop (HIL)
 # Current self-hosted instance is running on an RPI4 with
 # - pico + pico-probe connected via USB
+# - pico-probe is /dev/ttyACM0
 
 jobs:
   hw-test:
@@ -26,13 +27,19 @@ jobs:
         workflow: build_arm.yml
         name: rp2040
         
-    - name: Flash cdc_msc
-      run: openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program cdc_msc.elf verify reset exit" 
- 
-    - name: Test
+    - name: Test cdc_dual_ports
+      env:
+        example: cdc_dual_ports
       run: |
+        openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program ${{ env.example }}.elf verify reset exit"
+        test -e /dev/ttyACM1
+        test -e /dev/ttyACM2
+
+    - name: Test cdc_msc
+      env:
+        example: cdc_dual_ports
+      run: |
+        openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program ${{ env.example }}.elf verify reset exit"
         test -e /dev/ttyACM1
         test -e /media/pi/TinyUSB\ MSC/README.TXT
         cat /media/pi/TinyUSB\ MSC/README.TXT
-        # failed on purpose
-        test -e /dev/ttyACM2

From f5f2433c5afef3785caeb5251d4cac75e62b77f0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Jul 2022 11:56:31 +0700
Subject: [PATCH 1127/2085] wait for enumeration before test

---
 .github/workflows/test_hardware.yml | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 93440754e..30f9e53e8 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -32,14 +32,20 @@ jobs:
         example: cdc_dual_ports
       run: |
         openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program ${{ env.example }}.elf verify reset exit"
+        echo "Waiting for enumeration"
+        while ! lsusb | grep "cafe:" ; do : ; done
+        # Test
         test -e /dev/ttyACM1
         test -e /dev/ttyACM2
 
     - name: Test cdc_msc
       env:
-        example: cdc_dual_ports
+        example: cdc_msc
       run: |
         openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program ${{ env.example }}.elf verify reset exit"
+        echo "Waiting for enumeration"
+        while ! lsusb | grep "cafe:" ; do : ; done
+        # Test
         test -e /dev/ttyACM1
         test -e /media/pi/TinyUSB\ MSC/README.TXT
         cat /media/pi/TinyUSB\ MSC/README.TXT

From 1ff0c7a52b1350e477d75cfc5fd5243cdaedd508 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Jul 2022 15:03:55 +0700
Subject: [PATCH 1128/2085] sleep 0.2 for new image take affect

---
 .github/workflows/test_hardware.yml | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 30f9e53e8..68425a645 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -31,21 +31,25 @@ jobs:
       env:
         example: cdc_dual_ports
       run: |
-        openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program ${{ env.example }}.elf verify reset exit"
-        echo "Waiting for enumeration"
-        while ! lsusb | grep "cafe:" ; do : ; done
+        openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program ${{ env.example }}.elf reset exit"
+        echo "Waiting for enumeration (200 ms for reset, 5s for enumeration)"
+        sleep 0.2
+        SECONDS=0
+        while (! lsusb | grep "cafe:") && [ $SECONDS -le 5 ] ; do : ; done
         # Test
-        test -e /dev/ttyACM1
-        test -e /dev/ttyACM2
+        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
     - name: Test cdc_msc
       env:
         example: cdc_msc
       run: |
-        openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program ${{ env.example }}.elf verify reset exit"
-        echo "Waiting for enumeration"
-        while ! lsusb | grep "cafe:" ; do : ; done
+        openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program ${{ env.example }}.elf reset exit"
+        echo "Waiting for enumeration (200 ms for reset, 5s for enumeration)"
+        sleep 0.2
+        SECONDS=0
+        while (! lsusb | grep "cafe:") && [ $SECONDS -le 5 ] ; do : ; done
         # Test
-        test -e /dev/ttyACM1
-        test -e /media/pi/TinyUSB\ MSC/README.TXT
+        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+        test -f /media/pi/TinyUSB\ MSC/README.TXT && echo "MSC README.TXT exist"
         cat /media/pi/TinyUSB\ MSC/README.TXT

From 05ccd6c32b60994634add3b4b867870dab27aca5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Jul 2022 15:44:21 +0700
Subject: [PATCH 1129/2085] more hw test update

---
 .github/workflows/test_hardware.yml | 30 ++++++++++++-----------------
 1 file changed, 12 insertions(+), 18 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 68425a645..1470effd4 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -15,12 +15,20 @@ jobs:
     runs-on: [self-hosted, Linux, ARM64]
 
     steps:
-    - name: Clean workspace
+    - name: Prepare workspace
       run: |
         echo "Cleaning up previous run"
         rm -rf "${{ github.workspace }}"
         mkdir -p "${{ github.workspace }}"
-        
+        echo "Create flash.sh"
+        touch flash.sh
+        chmod +x flash.sh
+        echo >> flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1.elf reset exit"'
+        echo >> flash.sh '"Waiting for enumeration (500 ms for reset, 5s for enumeration)"'
+        echo >> flash.sh 'sleep 0.5'
+        echo >> flash.sh 'SECONDS=0'
+        echo >> flash.sh 'while (! lsusb | grep "cafe:") && [ $SECONDS -le 5 ] ; do : ; done'
+
     - name: Download rp2040 Artifacts
       uses: dawidd6/action-download-artifact@v2
       with:
@@ -28,28 +36,14 @@ jobs:
         name: rp2040
         
     - name: Test cdc_dual_ports
-      env:
-        example: cdc_dual_ports
       run: |
-        openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program ${{ env.example }}.elf reset exit"
-        echo "Waiting for enumeration (200 ms for reset, 5s for enumeration)"
-        sleep 0.2
-        SECONDS=0
-        while (! lsusb | grep "cafe:") && [ $SECONDS -le 5 ] ; do : ; done
-        # Test
+        ./flash_sh cdc_dual_ports
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
     - name: Test cdc_msc
-      env:
-        example: cdc_msc
       run: |
-        openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program ${{ env.example }}.elf reset exit"
-        echo "Waiting for enumeration (200 ms for reset, 5s for enumeration)"
-        sleep 0.2
-        SECONDS=0
-        while (! lsusb | grep "cafe:") && [ $SECONDS -le 5 ] ; do : ; done
-        # Test
+        ./flash.sh cdc_msc
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -f /media/pi/TinyUSB\ MSC/README.TXT && echo "MSC README.TXT exist"
         cat /media/pi/TinyUSB\ MSC/README.TXT

From 4411579ae099acbcf4559c691a0fb67b2596b52c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Jul 2022 16:08:08 +0700
Subject: [PATCH 1130/2085] ci update

---
 .github/workflows/test_hardware.yml | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 1470effd4..b5e0831d4 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -15,33 +15,38 @@ jobs:
     runs-on: [self-hosted, Linux, ARM64]
 
     steps:
-    - name: Prepare workspace
+    - name: Clean workspace
       run: |
         echo "Cleaning up previous run"
         rm -rf "${{ github.workspace }}"
         mkdir -p "${{ github.workspace }}"
-        echo "Create flash.sh"
-        touch flash.sh
-        chmod +x flash.sh
-        echo >> flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1.elf reset exit"'
-        echo >> flash.sh '"Waiting for enumeration (500 ms for reset, 5s for enumeration)"'
-        echo >> flash.sh 'sleep 0.5'
-        echo >> flash.sh 'SECONDS=0'
-        echo >> flash.sh 'while (! lsusb | grep "cafe:") && [ $SECONDS -le 5 ] ; do : ; done'
 
     - name: Download rp2040 Artifacts
       uses: dawidd6/action-download-artifact@v2
       with:
         workflow: build_arm.yml
         name: rp2040
-        
+
+    - name: Create flash.sh
+      #working-directory: ${{github.workspace}}
+      run: |
+        touch flash.sh
+        chmod +x flash.sh
+        echo > flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1.elf reset exit"'
+        echo >> flash.sh '"Waiting for enumeration (500 ms for reset, 5s for enumeration)"'
+        echo >> flash.sh 'sleep 0.5'
+        echo >> flash.sh 'SECONDS=0'
+        echo >> flash.sh 'while (! lsusb | grep "cafe:") && [ $SECONDS -le 5 ] ; do : ; done'
+
     - name: Test cdc_dual_ports
+      #working-directory: ${{github.workspace}}
       run: |
         ./flash_sh cdc_dual_ports
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
     - name: Test cdc_msc
+      #working-directory: ${{github.workspace}}
       run: |
         ./flash.sh cdc_msc
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"

From 2d5be437472d2da573bae0c1e64ee8e017391dfe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Jul 2022 20:31:57 +0700
Subject: [PATCH 1131/2085] fix typo

---
 .github/workflows/test_hardware.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index b5e0831d4..77b95bfee 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -41,7 +41,7 @@ jobs:
     - name: Test cdc_dual_ports
       #working-directory: ${{github.workspace}}
       run: |
-        ./flash_sh cdc_dual_ports
+        ./flash.sh cdc_dual_ports
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 

From e01b437af5581794618ff031b3f8d6614bb46cec Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Jul 2022 11:10:54 +0700
Subject: [PATCH 1132/2085] more hw test

---
 .github/workflows/test_hardware.yml | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 77b95bfee..50353474b 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -33,15 +33,16 @@ jobs:
         touch flash.sh
         chmod +x flash.sh
         echo > flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1.elf reset exit"'
-        echo >> flash.sh '"Waiting for enumeration (500 ms for reset, 5s for enumeration)"'
+        echo >> flash.sh 'echo "Waiting for 0.5s for reset"'
         echo >> flash.sh 'sleep 0.5'
         echo >> flash.sh 'SECONDS=0'
-        echo >> flash.sh 'while (! lsusb | grep "cafe:") && [ $SECONDS -le 5 ] ; do : ; done'
+        echo >> flash.sh 'lsusb | grep "cafe:"'
 
     - name: Test cdc_dual_ports
       #working-directory: ${{github.workspace}}
       run: |
         ./flash.sh cdc_dual_ports
+        while ! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ]) && [$SECONDS -le 5]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
@@ -49,6 +50,8 @@ jobs:
       #working-directory: ${{github.workspace}}
       run: |
         ./flash.sh cdc_msc
+        while ! ([ -e /dev/ttyACM1 ] && [ -e /dev/sda ]) && [$SECONDS -le 5]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+        test -e /dev/sda && echo "sda exists"
         test -f /media/pi/TinyUSB\ MSC/README.TXT && echo "MSC README.TXT exist"
         cat /media/pi/TinyUSB\ MSC/README.TXT

From 229a1c145801861401392184c818f0c87766d601 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Jul 2022 11:37:09 +0700
Subject: [PATCH 1133/2085] update hw test

---
 .github/workflows/test_hardware.yml | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 50353474b..eefdb4c0a 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -42,7 +42,8 @@ jobs:
       #working-directory: ${{github.workspace}}
       run: |
         ./flash.sh cdc_dual_ports
-        while ! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ]) && [$SECONDS -le 5]; do :; done
+        echo $SECONDS
+        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [$SECONDS -le 5]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
@@ -50,7 +51,8 @@ jobs:
       #working-directory: ${{github.workspace}}
       run: |
         ./flash.sh cdc_msc
-        while ! ([ -e /dev/ttyACM1 ] && [ -e /dev/sda ]) && [$SECONDS -le 5]; do :; done
+        echo $SECONDS
+        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/sda ])) && [$SECONDS -le 5]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/sda && echo "sda exists"
         test -f /media/pi/TinyUSB\ MSC/README.TXT && echo "MSC README.TXT exist"

From d36ea6ddc1674c03764d69708cea63b5631e6766 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Jul 2022 12:23:01 +0700
Subject: [PATCH 1134/2085] update issue template

---
 .github/ISSUE_TEMPLATE/bug_report.yml      |  8 ++++
 .github/ISSUE_TEMPLATE/feature_request.md  | 14 -------
 .github/ISSUE_TEMPLATE/feature_request.yml | 49 ++++++++++++++++++++++
 3 files changed, 57 insertions(+), 14 deletions(-)
 delete mode 100644 .github/ISSUE_TEMPLATE/feature_request.md
 create mode 100644 .github/ISSUE_TEMPLATE/feature_request.yml

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index c0b520e35..2958d3b12 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -76,3 +76,11 @@ body:
       description: If applicable, add screenshots to help explain your problem.
     validations:
       required: false
+
+  - type: checkboxes
+    attributes:
+      label: I have checked existing issues, dicussion and documentation
+      description: You agree to check all the resources above before opening a new issue.
+      options:
+        - label: I confirm I have checked existing issues, dicussion and documentation.
+          required: true
diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md
deleted file mode 100644
index 562d3113b..000000000
--- a/.github/ISSUE_TEMPLATE/feature_request.md
+++ /dev/null
@@ -1,14 +0,0 @@
----
-name: Feature Request
-about: Suggest an idea for this project
-title: ''
-labels: Feature 💡
-assignees: ''
-
----
-
-**Is your feature request related to a problem? Please describe.**
-A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]
-
-**Describe the solution you'd like**
-A clear and concise description of what you want to happen.
diff --git a/.github/ISSUE_TEMPLATE/feature_request.yml b/.github/ISSUE_TEMPLATE/feature_request.yml
new file mode 100644
index 000000000..e168b73a6
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/feature_request.yml
@@ -0,0 +1,49 @@
+name: Feature Request
+description: Suggest an idea for this project
+labels: 'Feature 💡'
+body:
+  - type: markdown
+    attributes:
+      value: |
+        Thanks for taking the time to fill out this request!
+        It's okay to leave some blank if it doesn't apply to your request.
+
+  - type: input
+    attributes:
+      label: Related area
+      description: Please briefly explain the area of your Feature Request.
+      placeholder: eg. new port support, device stack, class driver ...
+    validations:
+      required: true
+
+  - type: input
+    attributes:
+      label: Hardware specification
+      description: Please provide if your proposal depends on specific Hardware.
+      placeholder: eg. rp2040, samd51 ...
+    validations:
+      required: true
+
+  - type: textarea
+    attributes:
+      label: Is your feature request related to a problem?
+      description: Please provide a clear and concise description of what the problem is. Add relevant issue link.
+      placeholder: ex. I'm facing the issue/missing function...
+    validations:
+      required: true
+
+  - type: textarea
+    attributes:
+      label: Describe the solution you'd like
+      description: Please provide a clear and concise description of what you want to happen.
+      placeholder: ex. When using this function...
+    validations:
+      required: true
+
+  - type: checkboxes
+      attributes:
+        label: I have checked existing issues, dicussion and documentation
+        description: You agree to check all the resources above before opening a new issue.
+        options:
+          - label: I confirm I have checked existing issues, dicussion and documentation.
+            required: true

From cbb7c9f313f8e8e29ba448ecd3ad07ca36d83309 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Jul 2022 13:31:42 +0700
Subject: [PATCH 1135/2085] fix hw test

---
 .github/workflows/test_hardware.yml | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index eefdb4c0a..77d4c2527 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -33,27 +33,29 @@ jobs:
         touch flash.sh
         chmod +x flash.sh
         echo > flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1.elf reset exit"'
-        echo >> flash.sh 'echo "Waiting for 0.5s for reset"'
-        echo >> flash.sh 'sleep 0.5'
-        echo >> flash.sh 'SECONDS=0'
-        echo >> flash.sh 'lsusb | grep "cafe:"'
+        # echo >> flash.sh 'echo "Waiting for 0.5s for reset"'
+        # echo >> flash.sh 'sleep 0.5'
+        # echo >> flash.sh 'SECONDS=0'
+        # echo >> flash.sh 'lsusb | grep "cafe:"'
 
     - name: Test cdc_dual_ports
-      #working-directory: ${{github.workspace}}
       run: |
+        echo "Second = $SECONDS"
         ./flash.sh cdc_dual_ports
+        echo "Second = $SECONDS"
+        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
         echo $SECONDS
-        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [$SECONDS -le 5]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
     - name: Test cdc_msc
-      #working-directory: ${{github.workspace}}
       run: |
+        readme='/media/pi/TinyUSB MSC/README.TXT'
+        echo "Second = $SECONDS"
         ./flash.sh cdc_msc
-        echo $SECONDS
-        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/sda ])) && [$SECONDS -le 5]; do :; done
+        echo "Second = $SECONDS"
+        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
+        echo "Second = $SECONDS"
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -e /dev/sda && echo "sda exists"
-        test -f /media/pi/TinyUSB\ MSC/README.TXT && echo "MSC README.TXT exist"
-        cat /media/pi/TinyUSB\ MSC/README.TXT
+        test -f "$readme" && echo "$readme exists"
+        cat "$readme"

From 292dea408fe05d9c46ba7ad0b7d317edfb692e11 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Jul 2022 21:27:38 +0700
Subject: [PATCH 1136/2085] add dfu test

---
 .github/workflows/test_hardware.yml | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 77d4c2527..5326ca823 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -28,7 +28,6 @@ jobs:
         name: rp2040
 
     - name: Create flash.sh
-      #working-directory: ${{github.workspace}}
       run: |
         touch flash.sh
         chmod +x flash.sh
@@ -40,22 +39,31 @@ jobs:
 
     - name: Test cdc_dual_ports
       run: |
+        #SECONDS=0
         echo "Second = $SECONDS"
         ./flash.sh cdc_dual_ports
-        echo "Second = $SECONDS"
         while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
-        echo $SECONDS
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
     - name: Test cdc_msc
       run: |
-        readme='/media/pi/TinyUSB MSC/README.TXT'
+        #SECONDS=0
         echo "Second = $SECONDS"
         ./flash.sh cdc_msc
-        echo "Second = $SECONDS"
+        readme='/media/pi/TinyUSB MSC/README.TXT'
         while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
-        echo "Second = $SECONDS"
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -f "$readme" && echo "$readme exists"
         cat "$readme"
+
+    - name: Test dfu
+      run: |
+        #SECONDS=0
+        echo "Second = $SECONDS"
+        ./flash.sh dfu
+        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
+        dfu-util -d cafe -a 0 -U dfu0
+        dfu-util -d cafe -a 1 -U dfu1
+        grep "TinyUSB DFU! - Partition 0" dfu0
+        grep "TinyUSB DFU! - Partition 1" dfu1

From aa8880c681f8d8549e17028cde41c6457b19c66e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Jul 2022 22:13:39 +0700
Subject: [PATCH 1137/2085] clean up

---
 .github/workflows/test_hardware.yml | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 5326ca823..eb24b5351 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -32,15 +32,9 @@ jobs:
         touch flash.sh
         chmod +x flash.sh
         echo > flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1.elf reset exit"'
-        # echo >> flash.sh 'echo "Waiting for 0.5s for reset"'
-        # echo >> flash.sh 'sleep 0.5'
-        # echo >> flash.sh 'SECONDS=0'
-        # echo >> flash.sh 'lsusb | grep "cafe:"'
 
     - name: Test cdc_dual_ports
       run: |
-        #SECONDS=0
-        echo "Second = $SECONDS"
         ./flash.sh cdc_dual_ports
         while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
@@ -48,8 +42,6 @@ jobs:
 
     - name: Test cdc_msc
       run: |
-        #SECONDS=0
-        echo "Second = $SECONDS"
         ./flash.sh cdc_msc
         readme='/media/pi/TinyUSB MSC/README.TXT'
         while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
@@ -59,8 +51,6 @@ jobs:
 
     - name: Test dfu
       run: |
-        #SECONDS=0
-        echo "Second = $SECONDS"
         ./flash.sh dfu
         while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
         dfu-util -d cafe -a 0 -U dfu0

From 4a47db97eb36c36319b1b434ac1f577ad77fb68c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 29 Jul 2022 11:32:17 +0700
Subject: [PATCH 1138/2085] test hw dfu_runtime

---
 .github/workflows/build_arm.yml     | 6 +++---
 .github/workflows/test_hardware.yml | 6 +++++-
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 64322082d..a321948e3 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -108,11 +108,11 @@ jobs:
     # Following steps are for Hardware Test with self-hosted
 
     - name: Prepare Artifacts
-      if: matrix.family == 'rp2040'
+      if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
       run: find examples/ -name "*.elf" -exec mv {} . \;
 
     - name: Upload Artifacts for Hardware Test
-      if: matrix.family == 'rp2040'
+      if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
       uses: actions/upload-artifact@v3
       with:
         name: ${{ matrix.family }}
@@ -120,7 +120,7 @@ jobs:
           *.elf
 
     - name: Trigger Hardware Test
-      if: matrix.family == 'rp2040'
+      if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
       uses: benc-uk/workflow-dispatch@v1
       with:
         workflow: Hardware Test
diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index eb24b5351..2fbfcb991 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -10,7 +10,6 @@ on:
 jobs:
   hw-test:
     # Limit the run to only hathach due to limited resource on RPI4
-    #if: github.repository_owner == 'hathach' && ${{ github.event.workflow_run.conclusion == 'success' }}
     if: github.repository_owner == 'hathach'
     runs-on: [self-hosted, Linux, ARM64]
 
@@ -57,3 +56,8 @@ jobs:
         dfu-util -d cafe -a 1 -U dfu1
         grep "TinyUSB DFU! - Partition 0" dfu0
         grep "TinyUSB DFU! - Partition 1" dfu1
+
+    - name: Test dfu
+      run: |
+        ./flash.sh dfu_runtime
+        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done

From fe7fca7abbea02b9f0ac8f53bf4ca1d1019c6e85 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 1 Aug 2022 14:42:58 +0700
Subject: [PATCH 1139/2085] minor clean up

---
 .github/workflows/test_hardware.yml | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 2fbfcb991..7a6e2a470 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -30,18 +30,18 @@ jobs:
       run: |
         touch flash.sh
         chmod +x flash.sh
-        echo > flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1.elf reset exit"'
+        echo > flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit"'
 
     - name: Test cdc_dual_ports
       run: |
-        ./flash.sh cdc_dual_ports
+        ./flash.sh cdc_dual_ports.elf
         while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
     - name: Test cdc_msc
       run: |
-        ./flash.sh cdc_msc
+        ./flash.sh cdc_msc.elf
         readme='/media/pi/TinyUSB MSC/README.TXT'
         while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
@@ -50,14 +50,20 @@ jobs:
 
     - name: Test dfu
       run: |
-        ./flash.sh dfu
+        ./flash.sh dfu.elf
         while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
         dfu-util -d cafe -a 0 -U dfu0
         dfu-util -d cafe -a 1 -U dfu1
         grep "TinyUSB DFU! - Partition 0" dfu0
         grep "TinyUSB DFU! - Partition 1" dfu1
 
-    - name: Test dfu
+    - name: Test dfu_runtime
       run: |
-        ./flash.sh dfu_runtime
+        ./flash.sh dfu_runtime.elf
         while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
+
+#    - name: Test hid_boot_interface
+#      run: |
+#        ./flash.sh hid_boot_interface.elf
+#        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
+        
\ No newline at end of file

From a219ba86eaf9d5ce1b90556053940daadd8527b5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 1 Aug 2022 14:52:29 +0700
Subject: [PATCH 1140/2085] fix issue with TUD_OPT_HIGH_SPEED

---
 src/tusb_option.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 70ef1c399..e0447b10c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -223,7 +223,7 @@ typedef int make_iso_compilers_happy;
 #define TUSB_OPT_DEVICE_ENABLED CFG_TUD_ENABLED
 
 // highspeed support indicator
-#define TUD_OPT_HIGH_SPEED    (CFG_TUD_MAX_SPEED ? CFG_TUD_MAX_SPEED : TUP_RHPORT_HIGHSPEED)
+#define TUD_OPT_HIGH_SPEED    (CFG_TUD_MAX_SPEED ? (CFG_TUD_MAX_SPEED & OPT_MODE_HIGH_SPEED) : TUP_RHPORT_HIGHSPEED)
 
 //------------- Roothub as Host -------------//
 

From d1c61e33a617439258605555947a1ffc78519674 Mon Sep 17 00:00:00 2001
From: Peter Lawrence <12226419+majbthrd@users.noreply.github.com>
Date: Wed, 3 Aug 2022 12:28:50 -0500
Subject: [PATCH 1141/2085] add 'stm32l052dap52' (STM32L052K8 MCU) board target

'dap52' is Olimex's name of their STM32L052-based fork of 'dap42'
---
 examples/device/uac2_headset/skip.txt         |   3 +-
 .../stm32l052dap52/STM32L052K8Ux_FLASH.ld     | 169 +++++++++
 hw/bsp/stm32l0/boards/stm32l052dap52/board.h  | 109 ++++++
 hw/bsp/stm32l0/boards/stm32l052dap52/board.mk |  11 +
 hw/bsp/stm32l0/family.c                       | 181 ++++++++++
 hw/bsp/stm32l0/family.mk                      |  40 +++
 hw/bsp/stm32l0/stm32l0xx_hal_conf.h           | 338 ++++++++++++++++++
 7 files changed, 850 insertions(+), 1 deletion(-)
 create mode 100644 hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
 create mode 100644 hw/bsp/stm32l0/boards/stm32l052dap52/board.h
 create mode 100644 hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
 create mode 100644 hw/bsp/stm32l0/family.c
 create mode 100644 hw/bsp/stm32l0/family.mk
 create mode 100644 hw/bsp/stm32l0/stm32l0xx_hal_conf.h

diff --git a/examples/device/uac2_headset/skip.txt b/examples/device/uac2_headset/skip.txt
index 9471822a4..70d8e8838 100644
--- a/examples/device/uac2_headset/skip.txt
+++ b/examples/device/uac2_headset/skip.txt
@@ -3,4 +3,5 @@ mcu:LPC13XX
 mcu:NUC121
 mcu:SAMD11
 mcu:SAME5X
-mcu:SAMG
\ No newline at end of file
+mcu:SAMG
+board:stm32l052dap52
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
new file mode 100644
index 000000000..1bc16cc7b
--- /dev/null
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
@@ -0,0 +1,169 @@
+/*
+*****************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Abstract    : Linker script for STM32L052K8Ux Device with
+**                64KByte FLASH, 8KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+**  (c)Copyright Ac6.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Ac6 permit registered System Workbench for MCU users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the System Workbench for MCU toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20002000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 64K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 8K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
new file mode 100644
index 000000000..8ad3e43c8
--- /dev/null
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
@@ -0,0 +1,109 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_4
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PORT           GPIOA
+#define BUTTON_PIN            GPIO_PIN_6
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              USART2
+#define UART_CLK_EN           __HAL_RCC_USART2_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF4_USART2
+#define UART_TX_PIN           GPIO_PIN_2
+#define UART_RX_PIN           GPIO_PIN_3
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32l0_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
+  static RCC_CRSInitTypeDef RCC_CRSInitStruct;
+  
+  /* Enable HSI Oscillator to be used as System clock source
+     Enable HSI48 Oscillator to be used as USB clock source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct); 
+ 
+  /* Select HSI48 as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+  
+  /* Select HSI as system clock source and configure the HCLK, PCLK1 and PCLK2 
+     clock dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;  
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;  
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+    
+  /*Configure the clock recovery system (CRS)**********************************/
+  
+  /*Enable CRS Clock*/
+  __HAL_RCC_CRS_CLK_ENABLE(); 
+  
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;  
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;  
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;  
+  /* Set the TRIM[5:0] to the default value*/
+  RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;   
+  /* Start automatic synchronization */ 
+  HAL_RCCEx_CRSConfig (&RCC_CRSInitStruct);
+}
+
+static inline void board_vbus_sense_init(void)
+{
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk b/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
new file mode 100644
index 000000000..84662344d
--- /dev/null
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += -DSTM32L052xx -DCFG_EXAMPLE_VIDEO_READONLY
+
+LD_FILE = $(BOARD_PATH)/STM32L052K8Ux_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l052xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32l052k8
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c
new file mode 100644
index 000000000..80a7c7435
--- /dev/null
+++ b/hw/bsp/stm32l0/family.c
@@ -0,0 +1,181 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stm32l0xx_hal.h"
+#include "bsp/board.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+UART_HandleTypeDef UartHandle;
+
+void board_init(void)
+{
+  board_stm32l0_clock_init();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+
+  // Enable UART Clock
+  UART_CLK_EN();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  // LED
+  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+  // Uart
+  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull      = GPIO_PULLUP;
+  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle.Instance        = UART_DEV;
+  UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
+  UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
+  UartHandle.Init.StopBits   = UART_STOPBITS_1;
+  UartHandle.Init.Parity     = UART_PARITY_NONE;
+  UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
+  UartHandle.Init.Mode       = UART_MODE_TX_RX;
+  UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
+  HAL_UART_Init(&UartHandle);
+
+  // USB Pins
+  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  // USB Clock enable
+  __HAL_RCC_USB_CLK_ENABLE();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  return len;
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler (void)
+{
+  asm("bkpt");
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t* file, uint32_t line)
+{
+  (void) file; (void) line;
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/stm32l0/family.mk b/hw/bsp/stm32l0/family.mk
new file mode 100644
index 000000000..622fa61e0
--- /dev/null
+++ b/hw/bsp/stm32l0/family.mk
@@ -0,0 +1,40 @@
+ST_FAMILY = l0
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0plus \
+  -mfloat-abi=soft \
+  -nostdlib -nostartfiles \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32L0
+
+# suppress warning caused by vendor mcu driver
+CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-align -Wno-error=maybe-uninitialized
+
+SRC_C += \
+  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+  $(TOP)/$(ST_CMSIS)/Include \
+  $(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM0
diff --git a/hw/bsp/stm32l0/stm32l0xx_hal_conf.h b/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
new file mode 100644
index 000000000..cc20ea8e0
--- /dev/null
+++ b/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
@@ -0,0 +1,338 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file. 
+  *          This file should be copied to the application folder and renamed
+  *          to stm32l0xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CONF_H
+#define __STM32L0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED */
+/*#define HAL_COMP_MODULE_ENABLED */
+/*#define HAL_CRC_MODULE_ENABLED */
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_DAC_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
+/*#define HAL_FIREWALL_MODULE_ENABLED */
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED */
+/*#define HAL_I2S_MODULE_ENABLED */
+/*#define HAL_IWDG_MODULE_ENABLED */
+/*#define HAL_LCD_MODULE_ENABLED */
+/*#define HAL_LPTIM_MODULE_ENABLED */
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+/*#define HAL_RNG_MODULE_ENABLED */
+/*#define HAL_RTC_MODULE_ENABLED */
+/*#define HAL_SPI_MODULE_ENABLED */
+/*#define HAL_TIM_MODULE_ENABLED */
+/*#define HAL_TSC_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED */
+/*#define HAL_IRDA_MODULE_ENABLED */
+/*#define HAL_SMARTCARD_MODULE_ENABLED */
+/*#define HAL_SMBUS_MODULE_ENABLED */
+/*#define HAL_WWDG_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator for USB (HSI48) value.
+  */
+#if !defined  (HSI48_VALUE) 
+#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)37000U)       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+/**
+  * @brief Time out for LSE start up value in ms.
+  */
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+   
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U)    /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              1U              
+#define  PREREAD_ENABLE               0U
+#define  BUFFER_CACHE_DISABLE         0U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+
+/* ################## Register callback feature configuration ############### */
+/**
+  * @brief Set below the peripheral configuration  to "1U" to add the support
+  *        of HAL callback registration/deregistration feature for the HAL
+  *        driver(s). This allows user application to provide specific callback
+  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+  *        the default weak callback functions (see each stm32l0xx_hal_ppp.h file
+  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+  *        for each PPP peripheral).
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS        0U
+#define USE_HAL_COMP_REGISTER_CALLBACKS       0U
+#define USE_HAL_DAC_REGISTER_CALLBACKS        0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS        0U
+#define USE_HAL_I2S_REGISTER_CALLBACKS        0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS       0U
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS      0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS        0U
+#define USE_HAL_RNG_REGISTER_CALLBACKS        0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS        0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS      0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS        0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS        0U
+#define USE_HAL_TSC_REGISTER_CALLBACKS        0U
+#define USE_HAL_UART_REGISTER_CALLBACKS       0U
+#define USE_HAL_USART_REGISTER_CALLBACKS      0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS       0U
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC                   1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32l0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+  
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32l0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32l0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32l0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32l0xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32l0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32l0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32l0xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32l0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+  #include "stm32l0xx_hal_firewall.h"
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+ 
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32l0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32l0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32l0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32l0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32l0xx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32l0xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+   
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32l0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32l0xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32l0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32l0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32l0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32l0xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32l0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32l0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32l0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32l0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32l0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32l0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32l0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

From c7469ce986b495ccd3777e542df31bd90f4134f2 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Tue, 9 Aug 2022 09:53:08 +0200
Subject: [PATCH 1142/2085] dfu: Allow DFU coexistence with other interfaces

dfu_moded_open() only works correct when its called on DFU interface
descriptor. It means that DFU is the only one interface in configuration
or driver is called after all others interface drivers were tried and
gave up.

If other interface is supported and but driver for DFU is called first
(this is the case for BTH and RNDIS).
Code after while loop (that was not entered) has an TU_ASSERT that will
make set_configuration to fail.

Now TU_VERIFY is called first to make sure open code is called for DFU
only and not other interface descriptors like in other drivers.
---
 src/class/dfu/dfu_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 8d859d2ee..aa5891ca9 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -167,6 +167,8 @@ uint16_t dfu_moded_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc,
   uint8_t alt_count = 0;
 
   uint16_t drv_len = 0;
+  TU_VERIFY(itf_desc->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS && itf_desc->bInterfaceProtocol == DFU_PROTOCOL_DFU, 0);
+
   while(itf_desc->bInterfaceSubClass == TUD_DFU_APP_SUBCLASS && itf_desc->bInterfaceProtocol == DFU_PROTOCOL_DFU)
   {
     TU_ASSERT(max_len > drv_len, 0);

From 5efef4393c2f67773843c4ccc0a50f07dac6ece9 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Mon, 15 Aug 2022 17:34:13 +0930
Subject: [PATCH 1143/2085] Hub: Expand hub helpers to handle device events

---
 src/host/hub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/host/hub.c b/src/host/hub.c
index 3400b154a..e3b81ad23 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -85,7 +85,7 @@ bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
   {
     .bmRequestType_bit =
     {
-      .recipient = TUSB_REQ_RCPT_OTHER,
+      .recipient = (hub_port == 0) ? TUSB_REQ_RCPT_DEVICE : TUSB_REQ_RCPT_OTHER,
       .type      = TUSB_REQ_TYPE_CLASS,
       .direction = TUSB_DIR_OUT
     },
@@ -117,7 +117,7 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature,
   {
     .bmRequestType_bit =
     {
-      .recipient = TUSB_REQ_RCPT_OTHER,
+      .recipient = (hub_port == 0) ? TUSB_REQ_RCPT_DEVICE : TUSB_REQ_RCPT_OTHER,
       .type      = TUSB_REQ_TYPE_CLASS,
       .direction = TUSB_DIR_OUT
     },
@@ -149,7 +149,7 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp,
   {
     .bmRequestType_bit =
     {
-      .recipient = TUSB_REQ_RCPT_OTHER,
+      .recipient = (hub_port == 0) ? TUSB_REQ_RCPT_DEVICE : TUSB_REQ_RCPT_OTHER,
       .type      = TUSB_REQ_TYPE_CLASS,
       .direction = TUSB_DIR_IN
     },

From aafea8ef5d6f329d66c6c1e903b8a6b33d769ad5 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Mon, 15 Aug 2022 17:36:45 +0930
Subject: [PATCH 1144/2085] Hub: Rename port status callback to be more generic

---
 src/host/hub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/host/hub.c b/src/host/hub.c
index e3b81ad23..dc2e4e759 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -313,7 +313,7 @@ static void config_port_power_complete (tuh_xfer_t* xfer)
 // Connection Changes
 //--------------------------------------------------------------------+
 
-static void connection_get_status_complete (tuh_xfer_t* xfer);
+static void hub_port_get_status_complete (tuh_xfer_t* xfer);
 static void connection_clear_conn_change_complete (tuh_xfer_t* xfer);
 static void connection_port_reset_complete (tuh_xfer_t* xfer);
 
@@ -333,7 +333,7 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   {
     if ( tu_bit_test(p_hub->status_change, port) )
     {
-      if (hub_port_get_status(dev_addr, port, &p_hub->port_status, connection_get_status_complete, 0) == false)
+      if (hub_port_get_status(dev_addr, port, &p_hub->port_status, hub_port_get_status_complete, 0) == false)
       {
         //Hub status control transfer failed, retry
         hub_edpt_status_xfer(dev_addr);
@@ -347,7 +347,7 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   return true;
 }
 
-static void connection_get_status_complete (tuh_xfer_t* xfer)
+static void hub_port_get_status_complete (tuh_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
 

From 3c7b5dcaffb9ccc81e700d5b0b212e897b4b9b0d Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Mon, 15 Aug 2022 17:39:32 +0930
Subject: [PATCH 1145/2085] Hub: Handle hub device status change interrupt

---
 src/host/hub.c | 59 +++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 51 insertions(+), 8 deletions(-)

diff --git a/src/host/hub.c b/src/host/hub.c
index dc2e4e759..99c629071 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -44,6 +44,7 @@ typedef struct
   uint8_t status_change; // data from status change interrupt endpoint
 
   hub_port_status_response_t port_status;
+  hub_status_response_t hub_status;
 } hub_interface_t;
 
 CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB];
@@ -314,6 +315,7 @@ static void config_port_power_complete (tuh_xfer_t* xfer)
 //--------------------------------------------------------------------+
 
 static void hub_port_get_status_complete (tuh_xfer_t* xfer);
+static void hub_get_status_complete (tuh_xfer_t* xfer);
 static void connection_clear_conn_change_complete (tuh_xfer_t* xfer);
 static void connection_port_reset_complete (tuh_xfer_t* xfer);
 
@@ -326,19 +328,31 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
 
   hub_interface_t* p_hub = get_itf(dev_addr);
 
-  TU_LOG2("  Port Status Change = 0x%02X\r\n", p_hub->status_change);
+  TU_LOG2("  Hub Status Change = 0x%02X\r\n", p_hub->status_change);
 
-  // Hub ignore bit0 in status change
-  for (uint8_t port=1; port <= p_hub->port_count; port++)
+  // Hub bit 0 is for the hub device events
+  if (tu_bit_test(p_hub->status_change, 0))
   {
-    if ( tu_bit_test(p_hub->status_change, port) )
+    if (hub_port_get_status(dev_addr, 0, &p_hub->hub_status, hub_get_status_complete, 0) == false)
     {
-      if (hub_port_get_status(dev_addr, port, &p_hub->port_status, hub_port_get_status_complete, 0) == false)
+      //Hub status control transfer failed, retry
+      hub_edpt_status_xfer(dev_addr);
+    }
+  }
+  else
+  {
+    // Hub bits 1 to n are hub port events
+    for (uint8_t port=1; port <= p_hub->port_count; port++)
+    {
+      if ( tu_bit_test(p_hub->status_change, port) )
       {
-        //Hub status control transfer failed, retry
-        hub_edpt_status_xfer(dev_addr);
+        if (hub_port_get_status(dev_addr, port, &p_hub->port_status, hub_port_get_status_complete, 0) == false)
+        {
+          //Hub status control transfer failed, retry
+          hub_edpt_status_xfer(dev_addr);
+        }
+        break;
       }
-      break;
     }
   }
 
@@ -347,6 +361,35 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
   return true;
 }
 
+static void hub_clear_feature_complete_stub(tuh_xfer_t* xfer)
+{
+  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
+  hub_edpt_status_xfer(xfer->daddr);
+}
+
+static void hub_get_status_complete (tuh_xfer_t* xfer)
+{
+  TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
+
+  uint8_t const daddr = xfer->daddr;
+  hub_interface_t* p_hub = get_itf(daddr);
+  uint8_t const port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  TU_ASSERT(port_num == 0 , );
+
+  TU_LOG2("HUB Got hub status, addr = %u, status = %04x\r\n", daddr, p_hub->hub_status.change.value);
+
+  if (p_hub->hub_status.change.local_power_source)
+  {
+    TU_LOG2("HUB Local Power Change, addr = %u\r\n", daddr);
+    hub_port_clear_feature(daddr, port_num, HUB_FEATURE_HUB_LOCAL_POWER_CHANGE, hub_clear_feature_complete_stub, 0);
+  }
+  else if (p_hub->hub_status.change.over_current)
+  {
+    TU_LOG1("HUB Over Current, addr = %u\r\n", daddr);
+    hub_port_clear_feature(daddr, port_num, HUB_FEATURE_HUB_OVER_CURRENT_CHANGE, hub_clear_feature_complete_stub, 0);
+  }
+}
+
 static void hub_port_get_status_complete (tuh_xfer_t* xfer)
 {
   TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );

From 2b2354d3021202f0b88d17b9356ff924cb01e45f Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Mon, 15 Aug 2022 17:40:59 +0930
Subject: [PATCH 1146/2085] Hub: Clear other port feature changes

---
 src/host/hub.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/host/hub.c b/src/host/hub.c
index 99c629071..3da5358b2 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -408,7 +408,24 @@ static void hub_port_get_status_complete (tuh_xfer_t* xfer)
     hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_CONNECTION_CHANGE, connection_clear_conn_change_complete, 0);
   }else
   {
-    // Other changes are: Enable, Suspend, Over Current, Reset, L1 state
+    // Clear other port status change interrupts. TODO Not currently handled - just cleared.
+    if (p_hub->port_status.change.port_enable)
+    {
+      hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_ENABLE_CHANGE, hub_clear_feature_complete_stub, 0);
+    }
+    else if (p_hub->port_status.change.suspend)
+    {
+      hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_SUSPEND_CHANGE, hub_clear_feature_complete_stub, 0);
+    }
+    else if (p_hub->port_status.change.over_current)
+    {
+      hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_OVER_CURRENT_CHANGE, hub_clear_feature_complete_stub, 0);
+    }
+    else if (p_hub->port_status.change.reset)
+    {
+      hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_RESET_CHANGE, hub_clear_feature_complete_stub, 0);
+    }
+    // Other changes are: L1 state
     // TODO clear change
 
     // prepare for next hub status

From 961e83e0836879ef9010184404c0f61c933035bf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 Aug 2022 17:11:40 +0700
Subject: [PATCH 1147/2085] more docs update

---
 README.rst                   |  2 +-
 docs/info/changelog.rst      | 58 ++++++++++++++++++++++++++++++++++++
 docs/reference/supported.rst |  9 +++++-
 3 files changed, 67 insertions(+), 2 deletions(-)

diff --git a/README.rst b/README.rst
index ba176a8c8..05963a655 100644
--- a/README.rst
+++ b/README.rst
@@ -51,7 +51,7 @@ The stack supports the following MCUs:
 - **Renesas:** RX63N, RX65N, RX72N
 - **Silabs:** EFM32GG
 - **Sony:** CXD56
-- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G4, L0, L1, L4, L4+
+- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G4, L0, L1, L4, L4+, WB
 - **TI:** MSP430, MSP432E4, TM4C123
 - **ValentyUSB:** eptri
 
diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index bd6712b93..67bb6af65 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -2,6 +2,64 @@
 Changelog
 *********
 
+0.14.0
+======
+
+- Improve compiler support for CCRX and IAR
+- Add timeout to osal_queue_receive()
+- Add tud_task_ext(timeout, in_isr) as generic version of tud_task(). Same as tuh_task_ext(), tuh_task()
+- Enable more warnings -Wnull-dereference -Wuninitialized -Wunused -Wredundant-decls -Wconversion
+- Add new examples 
+  - host/bare_api to demonstrate generic (app-level) enumeration and endpoint transfer
+  - dual/host_hid_to_device_cdc to run both device and host stack concurrently, get HID report from host and print out to device CDC. This example only work with multiple-controller MCUs and rp2040 with the help of pio-usb as added controller.
+
+Controller Driver (DCD & HCD)
+-----------------------------
+
+- Enhance rhports management to better support dual roles
+  - CFG_TUD_ENABLED/CFG_TUH_ENABLED, CFG_TUD_MAX_SPEED/CFG_TUH_MAX_SPEED can be used to replace CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE
+  - tud_init(rphort), tuh_init(rhport) can be used to init stack on specified roothub port (controller) instead of tusb_init(void)
+- Add dcd/hcd port specific defines TUP_ (stand for tinyusb port-specific)
+- [dwc2]
+  - Update to support stm32 h72x, h73x with only 1 otg controller
+  - Fix overwrite with grstctl when disable endpoint
+- [EHCI] Fix an issue with EHCI driver
+- [msp430] Fix for possible bug in msp430-elf-gcc 9.3.0
+- [nrf5x] Fix DMA access race condition using atomic function 
+- [pic32] Fix PIC32 santiy
+- [rp2040]
+  - Add PICO-PIO-USB as controller (device/host) support for rp2040
+  - Use shared IRQ handlers, so user can also hook the USB IRQ
+  - Fix resumed signal not reported to device stack
+- [stm32fsdev] Add support for stm32wb55 
+
+Device Stack
+------------
+
+- [Audio] Add support for feedback endpoint computation
+  - New API tud_audio_feedback_params_cb(), tud_audio_feedback_interval_isr().
+  - Supported computation method are: frequency with fixed/float or power of 2. Feedback with fifo count is not yet supported.
+  - Fix nitfs (should be 3) in TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR
+  - Fix typo in audiod_rx_done_cb()
+- [DFU] Fix coexistence with other interfaces BTH, RNDIS
+- [MSC] Fix inquiry response additional length field
+- [Venndor] Improve write performance
+
+Host Stack
+----------
+
+- Add new API tuh_configure(rhport, cfg_id, cfg_param) for dynamnic port specific behavior configuration
+- [HID] Open OUT endpoint if available
+- [Hub] hub clear port and device interrupts
+- [USBH] Major improvement
+  - Rework usbh control transfer with complete callback. New API tuh_control_xfer() though still only carry 1 usbh (no queueing) at a time.
+  - Add generic endpoint transfer with tuh_edpt_open(), tuh_edpt_xfer(). Require `CFG_TUH_API_EDPT_XFER=1`
+  - Support app-level enumeration with new APIs
+    - tuh_descriptor_get(), tuh_descriptor_get_device(), tuh_descriptor_get_configuration(), tuh_descriptor_get_hid_report()
+    - tuh_descriptor_get_string(), tuh_descriptor_get_manufacturer_string(), tuh_descriptor_get_product_string(), tuh_descriptor_get_serial_string()
+    - Also add _sync() as sync/blocking version for above APIs 
+    
+
 0.13.0
 ======
 
diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index ad2af98ff..1fb858a45 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -60,7 +60,7 @@ Supported MCUs
 |              |         +-------------+--------+------+-----------+-------------------+--------------+
 |              |         | 55          | ✔      |      | ✔         | lpc_ip3511        |              |
 +--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
-| Raspberry Pi | RP2040                | ✔      | ✔    | ✖         | rp2040            |              |
+| Raspberry Pi | RP2040                | ✔      | ✔    | ✖         | rp2040, pio_usb   |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
 | Renesas      | RX 63N, 65N, 72N      | ✔      | ✔    | ✖         | usba              |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
@@ -95,6 +95,8 @@ Supported MCUs
 |              | L4+                   | ✔      |      |           | dwc2              |              |
 |              +-----------------------+--------+------+-----------+-------------------+--------------+
 |              | U5                    | âš       |      |           | dwc2              |              |
+|              +-----------------------+--------+------+-----------+-------------------+--------------+
+|              | WBx5                  | ✔      |      |           | stm32_fsdev       |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
 | TI           | MSP430                | ✔      | ✖    | ✖         | msp430x5xx        |              |
 |              +-----------------------+--------+------+-----------+-------------------+--------------+
@@ -241,6 +243,7 @@ iMX RT
 -  `MIMX RT1060 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1060-evk-i.mx-rt1060-evaluation-kit:MIMXRT1060-EVK>`__
 -  `MIMX RT1064 Evaluation Kit <https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK>`__
 -  `Teensy 4.0 Development Board <https://www.pjrc.com/store/teensy40.html>`__
+-  `Teensy 4.1 Development Board <https://www.pjrc.com/store/teensy41.html>`__
 
 Kinetis
 ^^^^^^^
@@ -379,6 +382,10 @@ L4
 -  `STM32 L4P5zg Nucleo <https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html>`__
 -  `STM32 L4R5zi Nucleo <https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html>`__
 
+WB
+^^
+-  `STM32 WB55 Nucleo <https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html>`__
+
 TI
 --
 

From 05e19b7848cea88031b912f69be04bf6a0fdd163 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Fri, 19 Aug 2022 23:57:39 +0700
Subject: [PATCH 1148/2085] Update feature_request.yml

---
 .github/ISSUE_TEMPLATE/feature_request.yml | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/feature_request.yml b/.github/ISSUE_TEMPLATE/feature_request.yml
index e168b73a6..19f403246 100644
--- a/.github/ISSUE_TEMPLATE/feature_request.yml
+++ b/.github/ISSUE_TEMPLATE/feature_request.yml
@@ -41,9 +41,9 @@ body:
       required: true
 
   - type: checkboxes
-      attributes:
-        label: I have checked existing issues, dicussion and documentation
-        description: You agree to check all the resources above before opening a new issue.
-        options:
-          - label: I confirm I have checked existing issues, dicussion and documentation.
-            required: true
+    attributes:
+      label: I have checked existing issues, dicussion and documentation
+      description: You agree to check all the resources above before opening a new issue.
+      options:
+        - label: I confirm I have checked existing issues, dicussion and documentation.
+          required: true

From 3e815c709cef3a12841e07e8c416bad7c0d35c5d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 23 Aug 2022 12:00:20 +0700
Subject: [PATCH 1149/2085] update repository.yml

---
 repository.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/repository.yml b/repository.yml
index aaec10eb7..dc341a3c1 100644
--- a/repository.yml
+++ b/repository.yml
@@ -11,7 +11,8 @@ repo.versions:
     "0.11.0": "0.11.0"
     "0.12.0": "0.12.0"
     "0.13.0": "0.13.0"
+    "0.14.0": "0.14.0"
 
     "0-dev": "0.0.0"        # master
-    "0-latest": "0.13.0"    # latest stable release
+    "0-latest": "0.14.0"    # latest stable release
 

From 660e8f50a7b551eec7e02f78c828a54394920e51 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 23 Aug 2022 14:43:09 +0700
Subject: [PATCH 1150/2085] try to fix release body in tinyusb_src (not tested)

---
 .github/workflows/trigger.yml | 4 +++-
 docs/info/changelog.rst       | 3 +--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/trigger.yml b/.github/workflows/trigger.yml
index 780d6f4f3..e434ca238 100644
--- a/.github/workflows/trigger.yml
+++ b/.github/workflows/trigger.yml
@@ -55,4 +55,6 @@ jobs:
         git push origin ${{ github.event.release.tag_name }}
         
         # Send POST reqwuest to release https://docs.github.com/en/rest/reference/repos#create-a-release
-        curl -X POST -H "Authorization: token ${{ secrets.API_TOKEN_GITHUB }}" -H "Accept: application/vnd.github.v3+json" --data '{"tag_name": "${{ github.event.release.tag_name }}", "name": "${{ github.event.release.name }}", "body": "${{ github.event.release.body }}", "draft": ${{ github.event.release.draft }}, "prerelease": ${{ github.event.release.prerelease }}}' https://api.github.com/repos/hathach/tinyusb_src/releases
+        bb={{ github.event.release.body }}
+        bb=${bb//\n/\\\n}
+        curl -X POST -H "Authorization: token ${{ secrets.API_TOKEN_GITHUB }}" -H "Accept: application/vnd.github.v3+json" --data '{"tag_name": "${{ github.event.release.tag_name }}", "name": "${{ github.event.release.name }}", "body": "$bb", "draft": ${{ github.event.release.draft }}, "prerelease": ${{ github.event.release.prerelease }}}' https://api.github.com/repos/hathach/tinyusb_src/releases
diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index 67bb6af65..da29e04fb 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -57,8 +57,7 @@ Host Stack
   - Support app-level enumeration with new APIs
     - tuh_descriptor_get(), tuh_descriptor_get_device(), tuh_descriptor_get_configuration(), tuh_descriptor_get_hid_report()
     - tuh_descriptor_get_string(), tuh_descriptor_get_manufacturer_string(), tuh_descriptor_get_product_string(), tuh_descriptor_get_serial_string()
-    - Also add _sync() as sync/blocking version for above APIs 
-    
+    - Also add _sync() as sync/blocking version for above APIs
 
 0.13.0
 ======

From 8a537a0092a5bea5540e238c9ff2726204879f77 Mon Sep 17 00:00:00 2001
From: Ahmed El-Sharnoby <Lan-Hekary@users.noreply.github.com>
Date: Tue, 23 Aug 2022 17:18:32 +0200
Subject: [PATCH 1151/2085] Remove Hardcoded interface numbers from video
 descriptors

Removing the Hardcoded interface numbers from the video descriptors allow the user to add other interfaces before or after the Video Control Interface and Video Streaming Interface
---
 examples/device/video_capture/src/usb_descriptors.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 23511c909..90537aa06 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -38,7 +38,7 @@
 #define FRAME_RATE    10
 
 enum {
-  ITF_NUM_VIDEO_CONTROL = 0,
+  ITF_NUM_VIDEO_CONTROL,
   ITF_NUM_VIDEO_STREAMING,
   ITF_NUM_TOTAL
 };
@@ -74,19 +74,19 @@ enum {
   TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_I420, 12, _frmidx, _asrx, _asry, _interlace, _cp)
 
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps, _epsize) \
-  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, ITF_NUM_TOTAL, _stridx), \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
   TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
     TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
          /* wTotalLength - bLength */ \
          TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
-         UVC_CLOCK_FREQUENCY, 1), \
+         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
       TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
                                  /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
                                  /*wObjectiveFocalLength*/0, /*bmControls*/0), \
       TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
   /* Video stream alt. 0 */ \
-  TUD_VIDEO_DESC_STD_VS( 1, 0, 0, 0), \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
         /*wTotalLength - bLength */\
@@ -106,7 +106,7 @@ enum {
             (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
         TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
   /* VS alt 1 */\
-  TUD_VIDEO_DESC_STD_VS(1, 1, 1, 0), \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 1, 1, _stridx), \
     /* EP */ \
     TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
 

From 5e3cfe7b5784ee94a4914b36232d28ce96cf18f2 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Fri, 26 Aug 2022 08:01:06 +0200
Subject: [PATCH 1152/2085] nrf5x: Fix endpoint internal state when closed

Field started (regardind transfer) was only cleaed when transfer
was finished.
For audio devices set interface is called many times.
When there is no audio (silence) set interface requests zero
lenght bandwithd that in turn calls dcd_edpt_close().

When endpoint is closed due to set interface request transfer
should not longer be started since it will block next start transfer
with assert.

This just sets 'started' to false when endpoint is closed.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index efa30c60a..f213e9f9f 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -438,6 +438,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
     // When both ISO endpoint are close there is no need for SOF any more.
     if (_dcd.xfer[EP_ISO_NUM][TUSB_DIR_IN].mps + _dcd.xfer[EP_ISO_NUM][TUSB_DIR_OUT].mps == 0) NRF_USBD->INTENCLR = USBD_INTENCLR_SOF_Msk;
   }
+  _dcd.xfer[epnum][dir].started = false;
   __ISB(); __DSB();
 }
 

From c5992edc7de6f54d5fdab801c46e964bc0f18542 Mon Sep 17 00:00:00 2001
From: ReimuNotMoe <34613827+ReimuNotMoe@users.noreply.github.com>
Date: Sat, 3 Sep 2022 05:18:29 +0800
Subject: [PATCH 1153/2085] Initial PIC32MM/MX & PIC24 support

---
 src/portable/microchip/pic/dcd_pic.c | 711 +++++++++++++++++++++++++++
 src/tusb_option.h                    |   5 +
 2 files changed, 716 insertions(+)
 create mode 100644 src/portable/microchip/pic/dcd_pic.c

diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c
new file mode 100644
index 000000000..df9b2ff01
--- /dev/null
+++ b/src/portable/microchip/pic/dcd_pic.c
@@ -0,0 +1,711 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Koji Kitayama
+ * Copyright (c) 2022 Reimu NotMoe <reimu@sudomaker.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && \
+    (CFG_TUSB_MCU == OPT_MCU_PIC32MX || CFG_TUSB_MCU == OPT_MCU_PIC32MM || \
+     CFG_TUSB_MCU == OPT_MCU_PIC32MK || CFG_TUSB_MCU == OPT_MCU_PIC24 || \
+     CFG_TUSB_MCU == OPT_MCU_DSPIC33)
+
+#include <xc.h>
+
+#include "device/dcd.h"
+
+
+#if (CFG_TUSB_MCU == OPT_MCU_PIC32MX || CFG_TUSB_MCU == OPT_MCU_PIC32MM || CFG_TUSB_MCU == OPT_MCU_PIC32MK)
+
+#define TU_PIC_HAS_MMU          1
+#define TU_PIC_HAS_HW_RMW       1
+#define TU_PIC_INT_SIZE         4
+
+#elif (CFG_TUSB_MCU == OPT_MCU_PIC24 || CFG_TUSB_MCU == OPT_MCU_DSPIC33)
+
+#define TU_PIC_HAS_MMU          0
+#define TU_PIC_HAS_HW_RMW       0
+#define TU_PIC_INT_SIZE         2
+
+#else
+
+#error Unsupportd PIC MCU
+
+#endif
+
+
+#if TU_PIC_HAS_MMU
+
+#ifndef KVA_TO_PA
+#define KVA_TO_PA(kva)    ((uint32_t)(kva) & 0x1fffffff)
+#endif
+
+#ifndef PA_TO_KVA1
+#define PA_TO_KVA1(pa)    ((uint32_t)(pa) | 0xA0000000)
+#endif
+
+#else
+
+#ifndef KVA_TO_PA
+#define KVA_TO_PA(kva)    (kva)
+#endif
+
+#ifndef PA_TO_KVA1
+#define PA_TO_KVA1(pa)    (pa)
+#endif
+
+#endif
+
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+enum {
+  TOK_PID_OUT   = 0x1u,
+  TOK_PID_IN    = 0x9u,
+  TOK_PID_SETUP = 0xDu,
+};
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t head;
+    struct {
+      union {
+        struct {
+          uint16_t           :  2;
+          uint16_t tok_pid   :  4;
+          uint16_t data      :  1;
+          uint16_t own       :  1;
+          uint16_t           :  8;
+        };
+        struct {
+          uint16_t           :  2;
+          uint16_t bdt_stall :  1;
+          uint16_t dts       :  1;
+          uint16_t ninc      :  1;
+          uint16_t keep      :  1;
+          uint16_t           : 10;
+        };
+      };
+      uint16_t bc : 10;
+      uint16_t    :  6;
+    };
+  };
+  uint8_t *addr;
+} buffer_descriptor_t;
+
+TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t state;
+    struct {
+      uint32_t max_packet_size :11;
+      uint32_t                 : 5;
+      uint32_t odd             : 1;
+      uint32_t                 :15;
+    };
+  };
+  uint16_t length;
+  uint16_t remaining;
+} endpoint_state_t;
+
+TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
+
+typedef struct
+{
+  union {
+    /* [#EP][OUT,IN][EVEN,ODD] */
+    buffer_descriptor_t bdt[16][2][2];
+    uint16_t            bda[512];
+  };
+  TU_ATTR_ALIGNED(4) union {
+    endpoint_state_t endpoint[16][2];
+    endpoint_state_t endpoint_unified[16 * 2];
+  };
+  uint8_t setup_packet[8];
+  uint8_t addr;
+} dcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+// BDT(Buffer Descriptor Table) must be 256-byte aligned
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) volatile static dcd_data_t _dcd;
+
+TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
+
+#if TU_PIC_INT_SIZE == 4
+typedef uint32_t ep_reg_t;
+#elif TU_PIC_INT_SIZE == 2
+typedef uint16_t ep_reg_t;
+#endif
+
+static inline volatile void *ep_addr(uint8_t rhport, uint8_t ep_num) {
+#if CFG_TUSB_MCU == OPT_MCU_PIC32MK
+  volatile void *ep_reg_base = rhport ? (&U2EP0) : (&U1EP0);
+#else
+  volatile void *ep_reg_base = &U1EP0;
+#endif
+  return ep_reg_base + 0x10 * ep_num;
+}
+
+static inline ep_reg_t ep_read(uint8_t rhport, uint8_t ep_num) {
+  volatile ep_reg_t *ep = ep_addr(rhport, ep_num);
+  return *ep;
+}
+
+static inline void ep_write(uint8_t rhport, uint8_t ep_num, ep_reg_t val) {
+  volatile ep_reg_t *ep = ep_addr(rhport, ep_num);
+  *ep = val;
+}
+
+static inline void ep_clear(uint8_t rhport, uint8_t ep_num, ep_reg_t val) {
+#if TU_PIC_HAS_HW_RMW
+  volatile ep_reg_t *ep_clr = (ep_addr(rhport, ep_num) + 0x4);
+  *ep_clr = val;
+#else
+  ep_reg_t v = ep_read(rhport, ep_num);
+  v &= ~val;
+  ep_write(rhport, ep_num, v);
+#endif
+}
+
+static inline void ep_set(uint8_t rhport, uint8_t ep_num, ep_reg_t val) {
+#if TU_PIC_HAS_HW_RMW
+  volatile ep_reg_t *ep_s = (ep_addr(rhport, ep_num) + 0x8);
+  *ep_s = val;
+#else
+  ep_reg_t v = ep_read(rhport, ep_num);
+  v |= val;
+  ep_write(rhport, ep_num, v);
+#endif
+}
+
+static inline void intr_enable(uint8_t rhport) {
+#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
+  IEC0SET = _IEC0_USBIE_MASK;
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MX
+  IEC1SET = _IEC1_USBIE_MASK;
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
+  if (rhport == 0)
+    IEC1SET = _IEC1_USB1IE_MASK;
+  else
+    IEC7SET = _IEC7_USB2IE_MASK;
+#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
+  IEC5bits.USB1IE = 1;
+#endif
+}
+
+static inline void intr_disable(uint8_t rhport) {
+#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
+  IEC0CLR = _IEC0_USBIE_MASK;
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MX
+  IEC1CLR = _IEC1_USBIE_MASK;
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
+  if (rhport == 0)
+    IEC1CLR = _IEC1_USB1IE_MASK;
+  else
+    IEC7CLR = _IEC7_USB2IE_MASK;
+#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
+  IEC5bits.USB1IE = 0;
+#endif
+}
+
+static inline int intr_is_enabled(uint8_t rhport) {
+#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
+  return IEC0bits.USBIE;
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MX
+  return IEC1bits.USBIE;
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
+  if (rhport == 0)
+    return IEC1bits.USB1IE;
+  else
+    return IEC7bits.USB2IE;
+#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
+  return IEC5bits.USB1IE;
+#endif
+}
+
+static inline void intr_clear(uint8_t rhport) {
+#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
+  IFS0CLR = _IFS0_USBIF_MASK;
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MX
+  IFS1CLR = _IFS1_USBIF_MASK;
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
+  if (rhport == 0)
+    IFS1CLR = _IFS1_USB1IF_MASK;
+  else
+    IFS7CLR = _IFS7_USB2IF_MASK;
+#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
+  IFS5bits.USB1IF = 0;
+#endif
+}
+
+static void prepare_next_setup_packet(uint8_t rhport)
+{
+  const unsigned out_odd = _dcd.endpoint[0][0].odd;
+  const unsigned in_odd  = _dcd.endpoint[0][1].odd;
+  TU_ASSERT(0 == _dcd.bdt[0][0][out_odd].own, );
+
+  _dcd.bdt[0][0][out_odd].data     = 0;
+  _dcd.bdt[0][0][out_odd ^ 1].data = 1;
+  _dcd.bdt[0][1][in_odd].data      = 1;
+  _dcd.bdt[0][1][in_odd ^ 1].data  = 0;
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
+                _dcd.setup_packet, sizeof(_dcd.setup_packet));
+}
+
+static void process_stall(uint8_t rhport)
+{
+  for (int i = 0; i < 16; ++i) {
+    unsigned const endpt = ep_read(rhport, i);
+
+    if (endpt & _U1EP0_EPSTALL_MASK) {
+      // prepare next setup if endpoint0
+      if ( i == 0 ) prepare_next_setup_packet(rhport);
+
+      // clear stall bit
+      ep_clear(rhport, i, _U1EP0_EPSTALL_MASK);
+    }
+  }
+}
+
+static void process_tokdne(uint8_t rhport)
+{
+  uint32_t s = U1STAT;
+
+  U1IR = _U1IR_TRNIF_MASK;
+
+  uint8_t epnum = (s >> _U1STAT_ENDPT0_POSITION);
+  uint8_t dir   = (s & _U1STAT_DIR_MASK) >> _U1STAT_DIR_POSITION;
+  unsigned odd  = (s & _U1STAT_PPBI_MASK) ? 1 : 0;
+
+  buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
+  endpoint_state_t    *ep = &_dcd.endpoint_unified[s >> 3];
+
+  /* fetch pid before discarded by the next steps */
+  const unsigned pid = bd->tok_pid;
+
+  /* reset values for a next transfer */
+  bd->bdt_stall = 0;
+  bd->dts       = 1;
+  bd->ninc      = 0;
+  bd->keep      = 0;
+  /* update the odd variable to prepare for the next transfer */
+  ep->odd       = odd ^ 1;
+  if (pid == TOK_PID_SETUP) {
+    dcd_event_setup_received(rhport, (uint8_t *)PA_TO_KVA1(bd->addr), true);
+    U1CONCLR = _U1CON_PKTDIS_TOKBUSY_MASK;
+    return;
+  }
+
+  const unsigned bc = bd->bc;
+  const unsigned remaining = ep->remaining - bc;
+  if (remaining && bc == ep->max_packet_size) {
+    /* continue the transferring consecutive data */
+    ep->remaining = remaining;
+    const int next_remaining = remaining - ep->max_packet_size;
+    if (next_remaining > 0) {
+      /* prepare to the after next transfer */
+      bd->addr += ep->max_packet_size * 2;
+      bd->bc    = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
+      bd->own   = 1; /* the own bit must set after addr */
+    }
+    return;
+  }
+  const unsigned length = ep->length;
+  dcd_event_xfer_complete(rhport,
+                          tu_edpt_addr(epnum, dir),
+                          length - remaining, XFER_RESULT_SUCCESS, true);
+  if (0 == epnum && 0 == length) {
+    /* After completion a ZLP of control transfer,
+     * it prepares for the next steup transfer. */
+    if (_dcd.addr) {
+      /* When the transfer was the SetAddress,
+       * the device address should be updated here. */
+      U1ADDR = _dcd.addr;
+      _dcd.addr  = 0;
+    }
+    prepare_next_setup_packet(rhport);
+  }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+  U1PWRCCLR = _U1PWRC_USUSPEND_MASK;
+  U1CONSET = _U1CON_PPBRST_MASK;
+  U1ADDR = 0;
+
+  U1IE = _U1IE_URSTIE_DETACHIE_MASK | _U1IE_TRNIE_MASK | _U1IE_IDLEIE_MASK |
+         _U1IE_UERRIE_MASK | _U1IE_STALLIE_MASK;
+
+  U1EP0 = _U1EP0_EPHSHK_MASK | _U1EP0_EPRXEN_MASK | _U1EP0_EPTXEN_MASK;
+
+  for (unsigned i = 1; i < 16; ++i) {
+    ep_write(rhport, i, 0);
+  }
+
+  buffer_descriptor_t *bd = _dcd.bdt[0][0];
+  for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
+    bd->head = 0;
+  }
+  const endpoint_state_t ep0 = {
+    .max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
+    .odd             = 0,
+    .length          = 0,
+    .remaining       = 0,
+  };
+  _dcd.endpoint[0][0] = ep0;
+  _dcd.endpoint[0][1] = ep0;
+  tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
+  _dcd.addr = 0;
+  prepare_next_setup_packet(rhport);
+  U1CONCLR = _U1CON_PPBRST_MASK;
+  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+}
+
+static void process_bus_sleep(uint8_t rhport)
+{
+  // Enable resume & disable suspend interrupt
+  dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+}
+
+static void process_bus_resume(uint8_t rhport)
+{
+  // Enable suspend & disable resume interrupt
+  U1PWRCCLR = _U1PWRC_USUSPEND_MASK;
+  U1IECLR = _U1IE_RESUMEIE_MASK;
+  U1IESET = _U1IE_IDLEIE_MASK;
+
+  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+void dcd_init(uint8_t rhport)
+{
+  intr_disable(rhport);
+  intr_clear(rhport);
+
+#if CFG_TUSB_MCU == OPT_MCU_PIC32MM
+  TRISBbits.TRISB6 = 1;
+#endif
+
+#if (CFG_TUSB_MCU == OPT_MCU_PIC32MX) || (CFG_TUSB_MCU == OPT_MCU_PIC32MM)
+  U1PWRCSET = _U1PWRC_USBPWR_MASK;
+#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
+  // TODO
+#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
+  U1PWRCbits.USBPWR = 1;
+#endif
+
+  tu_memclr(&_dcd, sizeof(_dcd));
+
+  uint32_t bdt_phys = KVA_TO_PA((uintptr_t)_dcd.bdt);
+
+  U1BDTP1 = (uint8_t)(bdt_phys >>  8);
+  U1BDTP2 = (uint8_t)(bdt_phys >> 16);
+  U1BDTP3 = (uint8_t)(bdt_phys >> 24);
+
+  U1IE = _U1IE_URSTIE_DETACHIE_MASK;
+
+  dcd_connect(rhport);
+
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+  intr_enable(rhport);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  intr_disable(rhport);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  _dcd.addr = dev_addr & 0x7F;
+  /* Response with status first before changing device address */
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  U1CONSET = _U1CON_RESUME_MASK;
+
+  unsigned cnt = 25000000 / 1000;
+  while (cnt--) asm volatile("nop");
+
+  U1CONCLR = _U1CON_RESUME_MASK;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  while (!U1CONbits.USBEN)
+    U1CONSET = _U1CON_USBEN_SOFEN_MASK;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  U1CON = 0;
+}
+
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  const unsigned ep_addr  = ep_desc->bEndpointAddress;
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  const unsigned xfer     = ep_desc->bmAttributes.xfer;
+  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
+  const unsigned odd      = ep->odd;
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+
+  /* No support for control transfer */
+  TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
+
+  ep->max_packet_size = tu_edpt_packet_size(ep_desc);
+
+  unsigned val = _U1EP0_EPCONDIS_MASK;
+  val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? _U1EP0_EPHSHK_MASK : 0;
+  val |= dir ? _U1EP0_EPTXEN_MASK : _U1EP0_EPRXEN_MASK;
+
+  volatile void *ep_reg_base = &U1EP0;
+  volatile uint32_t *reg_ep = (ep_reg_base + 0x10 * epn);
+
+  *reg_ep |= val;
+
+  if (xfer != TUSB_XFER_ISOCHRONOUS) {
+    bd[odd].dts      = 1;
+    bd[odd].data     = 0;
+    bd[odd ^ 1].dts  = 1;
+    bd[odd ^ 1].data = 1;
+  }
+
+  return true;
+}
+
+void dcd_edpt_close_all(uint8_t rhport)
+{
+  const unsigned ie = intr_is_enabled(rhport);
+  intr_disable(rhport);
+
+  for (unsigned i = 1; i < 16; ++i) {
+    ep_write(rhport, i, 0);
+  }
+
+  if (ie) intr_enable(rhport);
+
+  buffer_descriptor_t *bd = _dcd.bdt[1][0];
+  for (unsigned i = 2; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
+    bd->head = 0;
+  }
+  endpoint_state_t *ep = &_dcd.endpoint[1][0];
+  for (unsigned i = 2; i < sizeof(_dcd.endpoint)/sizeof(*ep); ++i, ++ep) {
+    /* Clear except the odd */
+    ep->max_packet_size = 0;
+    ep->length          = 0;
+    ep->remaining       = 0;
+  }
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+  const unsigned msk      = dir ? _U1EP0_EPTXEN_MASK : _U1EP0_EPRXEN_MASK;
+  const unsigned ie       = intr_is_enabled(rhport);
+
+  intr_disable(rhport);
+
+  ep_clear(rhport, epn, msk);
+
+  ep->max_packet_size = 0;
+  ep->length          = 0;
+  ep->remaining       = 0;
+  bd[0].head          = 0;
+  bd[1].head          = 0;
+
+  if (ie) intr_enable(rhport);
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
+  TU_ASSERT(0 == bd->own);
+
+  const unsigned ie       = intr_is_enabled(rhport);
+
+  intr_disable(rhport);
+
+  ep->length    = total_bytes;
+  ep->remaining = total_bytes;
+
+  const unsigned mps = ep->max_packet_size;
+  if (total_bytes > mps) {
+    buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
+    /* When total_bytes is greater than the max packet size,
+     * it prepares to the next transfer to avoid NAK in advance. */
+    next->bc   = total_bytes >= 2 * mps ? mps: total_bytes - mps;
+    next->addr = (uint8_t *)KVA_TO_PA(buffer + mps);
+    next->own  = 1;
+  }
+  bd->bc   = total_bytes >= mps ? mps: total_bytes;
+  bd->addr = (uint8_t *)KVA_TO_PA(buffer);
+//  __DSB();
+  bd->own  = 1; /* This bit must be set last */
+
+  if (ie) intr_enable(rhport);
+
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  const unsigned epn = tu_edpt_number(ep_addr);
+
+  if (0 == epn) {
+    ep_set(rhport, epn, _U1EP0_EPSTALL_MASK);
+  } else {
+    const unsigned dir      = tu_edpt_dir(ep_addr);
+    const unsigned odd      = _dcd.endpoint[epn][dir].odd;
+    buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][odd];
+    TU_ASSERT(0 == bd->own,);
+
+    const unsigned ie       = intr_is_enabled(rhport);
+
+    intr_disable(rhport);
+
+    bd->bdt_stall = 1;
+    bd->own       = 1; /* This bit must be set last */
+
+    if (ie) intr_enable(rhport);
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  TU_VERIFY(epn,);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  const unsigned odd      = _dcd.endpoint[epn][dir].odd;
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+  TU_VERIFY(bd[odd].own,);
+
+  const unsigned ie       = intr_is_enabled(rhport);
+
+  intr_disable(rhport);
+
+  bd[odd].own = 0;
+
+  // clear stall
+  bd[odd].bdt_stall  = 0;
+
+  // Reset data toggle
+  bd[odd    ].data = 0;
+  bd[odd ^ 1].data = 1;
+
+  // We already cleared this in ISR, but just clear it here to be safe
+  const unsigned endpt = ep_read(rhport, epn);
+  if (endpt & _U1EP0_EPSTALL_MASK) {
+    ep_clear(rhport, endpt, _U1EP0_EPSTALL_MASK);
+  }
+
+  if (ie) intr_enable(rhport);
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_int_handler(uint8_t rhport)
+{
+  uint32_t is  = U1IR;
+  uint32_t msk = U1IE;
+
+  U1IR = is & ~msk;
+  is &= msk;
+
+  if (is & _U1IR_UERRIF_MASK) {
+    uint32_t es = U1EIR;
+    U1EIR = es;
+    U1IR   = is; /* discard any pending events */
+  }
+
+  if (is & _U1IR_URSTIF_DETACHIF_MASK) {
+    U1IR = is; /* discard any pending events */
+    process_bus_reset(rhport);
+  }
+
+  if (is & _U1IR_IDLEIF_MASK) {
+    // Note Host usually has extra delay after bus reset (without SOF), which could falsely
+    // detected as Sleep event. Though usbd has debouncing logic so we are good
+    U1IR = _U1IR_IDLEIF_MASK;
+    process_bus_sleep(rhport);
+  }
+
+  if (is & _U1IR_RESUMEIF_MASK) {
+    U1IR = _U1IR_RESUMEIF_MASK;
+    process_bus_resume(rhport);
+  }
+
+  if (is & _U1IR_SOFIF_MASK) {
+    U1IR = _U1IR_SOFIF_MASK;
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+
+  if (is & _U1IR_STALLIF_MASK) {
+    U1IR = _U1IR_STALLIF_MASK;
+    process_stall(rhport);
+  }
+
+  if (is & _U1IR_TRNIF_MASK) {
+    process_tokdne(rhport);
+  }
+
+  intr_clear(rhport);
+
+}
+
+#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index e7fc68858..4c2dd0258 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -146,6 +146,11 @@ typedef int make_iso_compilers_happy;
 
 // PIC
 #define OPT_MCU_PIC32MZ          1900 ///< MicroChip PIC32MZ family
+#define OPT_MCU_PIC32MM          1901 ///< MicroChip PIC32MM family
+#define OPT_MCU_PIC32MX          1902 ///< MicroChip PIC32MX family
+#define OPT_MCU_PIC32MK          1903 ///< MicroChip PIC32MK family
+#define OPT_MCU_PIC24            1910 ///< MicroChip PIC24 family
+#define OPT_MCU_DSPIC33          1911 ///< MicroChip DSPIC33 family
 
 // BridgeTek
 #define OPT_MCU_FT90X            2000 ///< BridgeTek FT90x

From 0931b52b66864ab680f1e5b52eb0c20d028f5558 Mon Sep 17 00:00:00 2001
From: jmark1m <markj@baytekent.com>
Date: Wed, 7 Sep 2022 15:10:44 -0500
Subject: [PATCH 1154/2085] Fix bug #1628 by preventing shared irq slots for
 filling up

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index e9118c6a3..6ca992954 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -380,6 +380,9 @@ bool hcd_init(uint8_t rhport)
   // Force VBUS detect to always present, for now we assume vbus is always provided (without using VBUS En)
   usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
 
+  // Remove shared irq if it was previously added so as not to fill up shared irq slots
+  irq_remove_handler(USBCTRL_IRQ, hcd_rp2040_irq);
+
   irq_add_shared_handler(USBCTRL_IRQ, hcd_rp2040_irq, PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY);
 
   // clear epx and interrupt eps

From d28ff1175d185c399add10be7824310b2b8dcd47 Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Thu, 1 Sep 2022 14:28:00 +0100
Subject: [PATCH 1155/2085] IAR declares strncasecmp in string.h not strings.h

strings.h is not an ISO header file, so IAR generates fatal error Pe1696
'cannot open source file "strings.h"'. Even though strncasecmp isn't an
ISO C library function, IAR's runtime library defines it, though it
declares it in string.h instead.
---
 examples/device/usbtmc/src/usbtmc_app.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index 8f87a6dca..115163c7f 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -23,7 +23,11 @@
  *
  */
 
+#ifdef __ICCARM__
+#include <string.h>
+#else
 #include <strings.h>
+#endif
 #include <stdlib.h>     /* atoi */
 #include "tusb.h"
 #include "bsp/board.h"

From e5355d0335082541ae47b128add049a9d91ec070 Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Fri, 15 Jul 2022 17:32:20 +0100
Subject: [PATCH 1156/2085] [rp2040] Remove non-portable return statements

IAR generates error Pe118 'a void function may not return a value'.
---
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index c72dae64c..87fa999ca 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -87,15 +87,15 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_val
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32(struct hw_endpoint *ep, uint32_t value) {
-    return _hw_endpoint_buffer_control_update32(ep, 0, value);
+    _hw_endpoint_buffer_control_update32(ep, 0, value);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32(struct hw_endpoint *ep, uint32_t value) {
-    return _hw_endpoint_buffer_control_update32(ep, ~value, value);
+    _hw_endpoint_buffer_control_update32(ep, ~value, value);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32(struct hw_endpoint *ep, uint32_t value) {
-    return _hw_endpoint_buffer_control_update32(ep, ~value, 0);
+    _hw_endpoint_buffer_control_update32(ep, ~value, 0);
 }
 
 static inline uintptr_t hw_data_offset(uint8_t *buf)

From 6dfc857b916855e57a15813f423987449dd1a935 Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Wed, 24 Aug 2022 19:53:12 +0100
Subject: [PATCH 1157/2085] [rp2040] Explicit cast value of `hw_set_alias`

Some compilers don't support the GNU extension `typeof` so their definitions
of `hw_set_alias` can't inherit their type from their argument, and the best
we can do is have `hw_set_alias` act the same as `hw_set_alias_untyped`.
This requires an explicit cast when the macro is used instead, otherwise
IAR generates error Pe132 'expression must have pointer-to-struct-or-union
type but it has type "void *"'.

The same goes for `hw_clear_alias`.
---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 4 ++--
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 2003f72fd..89fd6b82d 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -46,8 +46,8 @@
 /* Low level controller
  *------------------------------------------------------------------*/
 
-#define usb_hw_set hw_set_alias(usb_hw)
-#define usb_hw_clear hw_clear_alias(usb_hw)
+#define usb_hw_set ((usb_hw_t *)hw_set_alias(usb_hw))
+#define usb_hw_clear ((usb_hw_t *)hw_clear_alias(usb_hw))
 
 // Init these in dcd_init
 static uint8_t *next_buffer_ptr;
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index e9118c6a3..5badb261a 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -56,8 +56,8 @@ static_assert(PICO_USB_HOST_INTERRUPT_ENDPOINTS <= USB_MAX_ENDPOINTS, "");
 static struct hw_endpoint ep_pool[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
 #define epx (ep_pool[0])
 
-#define usb_hw_set   hw_set_alias(usb_hw)
-#define usb_hw_clear hw_clear_alias(usb_hw)
+#define usb_hw_set   ((usb_hw_t *)hw_set_alias(usb_hw))
+#define usb_hw_clear ((usb_hw_t *)hw_clear_alias(usb_hw))
 
 // Flags we set by default in sie_ctrl (we add other bits on top)
 enum {

From 7a48b1f0d191093caa59c4fcb5c4f85fa2e53323 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 13 Sep 2022 11:04:48 +0700
Subject: [PATCH 1158/2085] re-added code in pr 1438 to fix compile with h7
 with 1 usb otg

---
 src/portable/synopsys/dwc2/dwc2_stm32.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 1187e0d6e..337f611d8 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -64,6 +64,10 @@
 
   // NOTE: H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
   // USB_OTG_FS_PERIPH_BASE and OTG_FS_IRQn not defined
+  #if (! defined USB2_OTG_FS)
+    #define USB_OTG_FS_PERIPH_BASE  USB1_OTG_HS_PERIPH_BASE
+    #define OTG_FS_IRQn             OTG_HS_IRQn
+  #endif
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32F7
   #include "stm32f7xx.h"

From 3133cacc6ab699244617039462f5c3870e16d835 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Tue, 13 Sep 2022 08:10:58 +0200
Subject: [PATCH 1159/2085] nrf5x: Fix reception of large ISO packets

ISO packet size is up to 1023 for full speed device.
Upon completion of ISO reception, reported length of incoming packet
was truncated to one byte only.
This results in incorrect data stream for higher bit rates
48 samples * 4 bytes per sample * 2 channels = 384 bytes of data
and 128 was reported.

There is no change in logic extending xact_len to uint16_t fixes the issue.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index f213e9f9f..ca37d799f 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -765,7 +765,7 @@ void dcd_int_handler(uint8_t rhport)
     if ( tu_bit_test(int_status, USBD_INTEN_ENDEPOUT0_Pos+epnum))
     {
       xfer_td_t* xfer = get_td(epnum, TUSB_DIR_OUT);
-      uint8_t const xact_len = NRF_USBD->EPOUT[epnum].AMOUNT;
+      uint16_t const xact_len = NRF_USBD->EPOUT[epnum].AMOUNT;
 
       xfer->buffer     += xact_len;
       xfer->actual_len += xact_len;

From e80714740ceec841ff4964fe555870cf3ee4f6df Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Tue, 12 Oct 2021 23:29:58 +0900
Subject: [PATCH 1160/2085] Change images to MJPEG

---
 examples/device/video_capture/src/images.h    | 282 ++++++++++++++++++
 examples/device/video_capture/src/main.c      |  21 +-
 .../video_capture/src/usb_descriptors.h       |  10 +-
 src/class/video/video.h                       |  79 +++++
 src/class/video/video_device.c                | 175 +++++++++--
 5 files changed, 536 insertions(+), 31 deletions(-)

diff --git a/examples/device/video_capture/src/images.h b/examples/device/video_capture/src/images.h
index 1b13cfe81..33beff662 100644
--- a/examples/device/video_capture/src/images.h
+++ b/examples/device/video_capture/src/images.h
@@ -1649,3 +1649,285 @@ static const unsigned char frame_buffer[128 * (96 + 1) * 2] = {
   0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
   0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
 };
+
+#define color_bar_0_jpg_len  511
+#define color_bar_1_jpg_len  512
+#define color_bar_2_jpg_len  511
+#define color_bar_3_jpg_len  511
+#define color_bar_4_jpg_len  511
+#define color_bar_5_jpg_len  512
+#define color_bar_6_jpg_len  511
+#define color_bar_7_jpg_len  511
+
+unsigned char color_bar_0_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x92, 0x8a, 0x00,
+  0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
+  0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
+  0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
+  0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
+  0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
+  0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
+  0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00,
+  0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
+  0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
+  0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
+  0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
+  0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
+  0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
+  0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00,
+  0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45,
+  0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89,
+  0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad,
+  0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25,
+  0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3,
+  0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1,
+  0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0xff, 0xd9
+};
+unsigned char color_bar_1_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x7d, 0x15, 0x98,
+  0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94,
+  0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51,
+  0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63,
+  0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45,
+  0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84,
+  0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98,
+  0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94,
+  0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51,
+  0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63,
+  0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45,
+  0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84,
+  0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98,
+  0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94,
+  0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51,
+  0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63,
+  0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45,
+  0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84,
+  0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x7f, 0xff, 0xd9
+};
+unsigned char color_bar_2_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x75, 0x14, 0xcc,
+  0xc4, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94,
+  0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18,
+  0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51,
+  0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61,
+  0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25,
+  0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c,
+  0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94,
+  0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18,
+  0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51,
+  0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61,
+  0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25,
+  0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c,
+  0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94,
+  0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18,
+  0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51,
+  0x40, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61,
+  0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x18, 0xda, 0x2b, 0x63, 0x61, 0x28, 0xac, 0xc6, 0x25,
+  0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x2c, 0x51, 0x40, 0x09, 0x45, 0x66, 0x33, 0xff, 0xd9
+};
+unsigned char color_bar_3_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x5a, 0x2a, 0x08,
+  0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a,
+  0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c,
+  0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac,
+  0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4,
+  0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9,
+  0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12,
+  0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63,
+  0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a,
+  0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c,
+  0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac,
+  0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4,
+  0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9,
+  0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12,
+  0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63,
+  0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a,
+  0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c,
+  0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac,
+  0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4,
+  0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9,
+  0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12,
+  0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x91, 0xff, 0xd9
+};
+unsigned char color_bar_4_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x4a, 0x2a, 0xcb,
+  0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56,
+  0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62,
+  0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4,
+  0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09,
+  0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31,
+  0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5,
+  0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36,
+  0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56,
+  0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62,
+  0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4,
+  0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09,
+  0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31,
+  0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5,
+  0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36,
+  0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56,
+  0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62,
+  0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4,
+  0xc8, 0x4a, 0x2b, 0x31, 0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09,
+  0x45, 0x66, 0x32, 0xc5, 0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31,
+  0x8d, 0xa2, 0xb6, 0x36, 0x12, 0x8a, 0xcc, 0x62, 0x51, 0x5a, 0x99, 0x09, 0x45, 0x66, 0x32, 0xc5,
+  0x14, 0x00, 0x94, 0x56, 0x63, 0x12, 0x8a, 0xd4, 0xc8, 0x4a, 0x2b, 0x31, 0x9f, 0xff, 0xd9
+};
+unsigned char color_bar_5_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x6d, 0x14, 0x8d,
+  0x04, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15,
+  0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56,
+  0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65,
+  0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c,
+  0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28,
+  0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98,
+  0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15,
+  0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56,
+  0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65,
+  0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c,
+  0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28,
+  0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98,
+  0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15,
+  0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32,
+  0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56,
+  0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65,
+  0x8a, 0x28, 0x01, 0x28, 0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c,
+  0x6c, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x65, 0x8a, 0x28, 0x01, 0x28,
+  0xac, 0xc6, 0x25, 0x15, 0xa9, 0x90, 0x94, 0x56, 0x63, 0x1b, 0x45, 0x6c, 0x6c, 0x7f, 0xff, 0xd9
+};
+unsigned char color_bar_6_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x65, 0x15, 0xa0,
+  0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15,
+  0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19,
+  0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b,
+  0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a,
+  0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45,
+  0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c,
+  0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15,
+  0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19,
+  0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b,
+  0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a,
+  0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45,
+  0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c,
+  0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15,
+  0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19,
+  0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b,
+  0x1b, 0x09, 0x45, 0x66, 0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a,
+  0x2b, 0x31, 0x89, 0x45, 0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66,
+  0x31, 0x28, 0xad, 0x4c, 0x84, 0xa2, 0xb3, 0x19, 0x62, 0x8a, 0x00, 0x4a, 0x2b, 0x31, 0x89, 0x45,
+  0x6a, 0x64, 0x25, 0x15, 0x98, 0xc6, 0xd1, 0x5b, 0x1b, 0x09, 0x45, 0x66, 0x33, 0xff, 0xd9
+};
+unsigned char color_bar_7_jpg[] = {
+  0xff, 0xd8, 0xff, 0xdb, 0x00, 0x43, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdb, 0x00, 0x43, 0x01, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00, 0x11,
+  0x08, 0x00, 0x60, 0x00, 0x80, 0x03, 0x01, 0x21, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xff,
+  0xda, 0x00, 0x0c, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3f, 0x00, 0x8e, 0x8a, 0x00,
+  0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad,
+  0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25,
+  0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3,
+  0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2,
+  0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6,
+  0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a,
+  0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c,
+  0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad,
+  0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25,
+  0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3,
+  0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2,
+  0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6,
+  0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a,
+  0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c,
+  0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad,
+  0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25,
+  0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3,
+  0x18, 0x94, 0x56, 0xa6, 0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2,
+  0xb5, 0x32, 0x12, 0x8a, 0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6,
+  0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a,
+  0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x47, 0xff, 0xd9
+};
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 4028352da..362b168d4 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -110,8 +110,21 @@ static unsigned tx_busy = 0;
 static unsigned interval_ms = 1000 / FRAME_RATE;
 
 /* YUY2 frame buffer */
-#ifdef CFG_EXAMPLE_VIDEO_READONLY
+#if 1
 #include "images.h"
+static struct {
+  uint32_t       size;
+  uint8_t const *buffer;
+} const frames[] = {
+  {color_bar_0_jpg_len, color_bar_0_jpg},
+  {color_bar_1_jpg_len, color_bar_1_jpg},
+  {color_bar_2_jpg_len, color_bar_2_jpg},
+  {color_bar_3_jpg_len, color_bar_3_jpg},
+  {color_bar_4_jpg_len, color_bar_4_jpg},
+  {color_bar_5_jpg_len, color_bar_5_jpg},
+  {color_bar_6_jpg_len, color_bar_6_jpg},
+  {color_bar_7_jpg_len, color_bar_7_jpg},
+};
 #else
 static uint8_t frame_buffer[FRAME_WIDTH * FRAME_HEIGHT * 16 / 8];
 static void fill_color_bar(uint8_t *buffer, unsigned start_position)
@@ -168,8 +181,7 @@ void video_task(void)
     already_sent = 1;
     start_ms = board_millis();
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-    tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t) &frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
-                           FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+    tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frames[frame_num % 8].buffer, frames[frame_num % 8].size);
 #else
     fill_color_bar(frame_buffer, frame_num);
     tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
@@ -182,8 +194,7 @@ void video_task(void)
   start_ms += interval_ms;
 
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-  tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t) &frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
-                         FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+  tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frames[frame_num % 8].buffer, frames[frame_num % 8].size);
 #else
   fill_color_bar(frame_buffer, frame_num);
   tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 90537aa06..aa937e168 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -90,17 +90,17 @@ enum {
     /* Video stream header for without still image capture */ \
     TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
         /*wTotalLength - bLength */\
-        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-        + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+        TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
+        + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
         + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
         _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
         /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
         /*bmaControls(1)*/0), \
       /* Video stream format */ \
-      TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
-        /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+      TUD_VIDEO_DESC_CS_VS_FMT_MJPEG(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        1, /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
         /* Video stream frame format */ \
-        TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
+        TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT(/*bFrameIndex */1, 0, _width, _height, \
             _width * _height * 16, _width * _height * 16 * _fps, \
             _width * _height * 16, \
             (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 844746546..e8227ea60 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -302,6 +302,45 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bCopyProtect;
 } tusb_desc_cs_video_fmt_uncompressed_t;
 
+typedef struct TU_ATTR_PACKED {
+  uint8_t bLength;
+  uint8_t bDescriptorType;
+  uint8_t bDescriptorSubType;
+  uint8_t bFormatIndex;
+  uint8_t bNumFrameDescriptors;
+  uint8_t bmFlags;
+  uint8_t bDefaultFrameIndex;
+  uint8_t bAspectRatioX;
+  uint8_t bAspectRatioY;
+  uint8_t bmInterlaceFlags;
+  uint8_t bCopyProtect;
+} tusb_desc_cs_video_fmt_mjpeg_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bFormatIndex;
+  uint32_t dwMaxVideoFrameBufferSize; /* deprecated */
+  uint8_t  bFormatType;
+} tusb_desc_cs_video_fmt_dv_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t bLength;
+  uint8_t bDescriptorType;
+  uint8_t bDescriptorSubType;
+  uint8_t bFormatIndex;
+  uint8_t bNumFrameDescriptors;
+  uint8_t guidFormat[16];
+  uint8_t bBitsPerPixel;
+  uint8_t bDefaultFrameIndex;
+  uint8_t bAspectRatioX;
+  uint8_t bAspectRatioY;
+  uint8_t bmInterlaceFlags;
+  uint8_t bCopyProtect;
+  uint8_t bVaribaleSize;
+} tusb_desc_cs_video_fmt_frame_based_t;
+
 typedef struct TU_ATTR_PACKED {
   uint8_t  bLength;
   uint8_t  bDescriptorType;
@@ -318,6 +357,24 @@ typedef struct TU_ATTR_PACKED {
   uint32_t dwFrameInterval[];
 } tusb_desc_cs_video_frm_uncompressed_t;
 
+typedef tusb_desc_cs_video_frm_uncompressed_t tusb_desc_cs_video_frm_mjpeg_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint8_t  bLength;
+  uint8_t  bDescriptorType;
+  uint8_t  bDescriptorSubType;
+  uint8_t  bFrameIndex;
+  uint8_t  bmCapabilities;
+  uint16_t wWidth;
+  uint16_t wHeight;
+  uint32_t dwMinBitRate;
+  uint32_t dwMaxBitRate;
+  uint32_t dwDefaultFrameInterval;
+  uint8_t  bFrameIntervalType;
+  uint32_t dwBytesPerLine;
+  uint32_t dwFrameInterval[];
+} tusb_desc_cs_video_frm_frame_based_t;
+
 //--------------------------------------------------------------------+
 // Requests
 //--------------------------------------------------------------------+
@@ -378,8 +435,11 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 #define TUD_VIDEO_DESC_CS_VS_IN_LEN               13
 #define TUD_VIDEO_DESC_CS_VS_OUT_LEN              9
 #define TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN      27
+#define TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN        11
 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN 38
 #define TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_DISC_LEN 26
+#define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN   38
+#define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC_LEN   26
 #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN   6
 
 /* 2.2 compression formats */
@@ -462,6 +522,25 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
   _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
   U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
 
+/* Motion-JPEG 3.1.1 Table 3-1 */
+#define TUD_VIDEO_DESC_CS_VS_FMT_MJPEG(_fmtidx, _numfrmdesc, _fixed_sz, _frmidx, _asrx, _asry, _interlace, _cp) \
+  TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FORMAT_MJPEG, \
+  _fmtidx, _numfrmdesc, _fixed_sz, _frmidx, _asrx,  _asry, _interlace, _cp
+
+/* Motion-JPEG 3.1.1 Table 3-2 and 3-3 */
+#define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, _minfrminterval, _maxfrminterval, _frmintervalstep) \
+  TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_MJPEG, \
+  _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
+  U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), 0, \
+  U32_TO_U8S_LE(_minfrminterval), U32_TO_U8S_LE(_maxfrminterval), U32_TO_U8S_LE(_frmintervalstep)
+
+/* Motion-JPEG 3.1.1 Table 3-2 and 3-4 */
+#define TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC(_frmidx, _cap, _width, _height, _minbr, _maxbr, _maxfrmbufsz, _frminterval, ...) \
+  TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_DISC_LEN + (TU_ARGS_NUM(__VA_ARGS__)) * 4, \
+  TUSB_DESC_CS_INTERFACE, VIDEO_CS_VS_INTERFACE_FRAME_MJPEG, \
+  _frmidx, _cap, U16_TO_U8S_LE(_width), U16_TO_U8S_LE(_height), U32_TO_U8S_LE(_minbr), U32_TO_U8S_LE(_maxbr), \
+  U32_TO_U8S_LE(_maxfrmbufsz), U32_TO_U8S_LE(_frminterval), (TU_ARGS_NUM(__VA_ARGS__)), __VA_ARGS__
+
 /* 3.9.2.6 */
 #define TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(_color, _trns, _mat) \
   TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN, \
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 7636db5fe..39e2e9aac 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -29,6 +29,8 @@
 
 #if (CFG_TUD_ENABLED && CFG_TUD_VIDEO && CFG_TUD_VIDEO_STREAMING)
 
+#include <stdarg.h>
+
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
 
@@ -59,6 +61,30 @@ typedef struct TU_ATTR_PACKED {
   uint8_t bEntityId;
 } tusb_desc_cs_video_entity_itf_t;
 
+typedef union {
+  struct TU_ATTR_PACKED {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubType;
+    uint8_t bFormatIndex;
+  };
+  tusb_desc_cs_video_fmt_uncompressed_t uncompressed;
+  tusb_desc_cs_video_fmt_mjpeg_t        mjpeg;
+  tusb_desc_cs_video_fmt_frame_based_t  frame_based;
+} tusb_desc_cs_video_fmt_t;
+
+typedef union {
+  struct TU_ATTR_PACKED {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bDescriptorSubType;
+    uint8_t bFrameIndex;
+  };
+  tusb_desc_cs_video_frm_uncompressed_t uncompressed;
+  tusb_desc_cs_video_frm_mjpeg_t        mjpeg;
+  tusb_desc_cs_video_frm_frame_based_t  frame_based;
+} tusb_desc_cs_video_frm_t;
+
 /* video streaming interface */
 typedef struct TU_ATTR_PACKED {
   uint8_t index_vc;  /* index of bound video control interface */
@@ -167,6 +193,72 @@ static void const* _find_desc(void const *beg, void const *end, uint_fast8_t des
   return cur;
 }
 
+/** Find the first descriptor of a given types
+ *
+ * @param[in] beg        The head of descriptor byte array.
+ * @param[in] end        The tail of descriptor byte array.
+ * @param[in] ...        The target descriptor types. The last type must be 0.
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* _find_desc_n(void const *beg, void const *end, ...)
+{
+  uint_fast8_t target = 0;
+  void const *cur;
+  for (cur = beg; cur < end && !target; cur = tu_desc_next(cur)) {
+    uint_fast8_t actual = tu_desc_type(cur);
+    va_list ap;
+    va_start(ap, end);
+    do {
+      target = va_arg(ap, unsigned);
+    } while (target && target != actual);
+    va_end(ap);
+  } 
+  return cur;
+}
+
+/** Find the first descriptor specified by the arguments
+ *
+ * @param[in] beg        The head of descriptor byte array.
+ * @param[in] end        The tail of descriptor byte array.
+ * @param[in] sub_types  The target bDescriptorSubtype list. The last elemnt must be 0.
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* _find_desc_cs(void const *beg, void const *end, uint8_t const *sub_types)
+{
+  uint_fast8_t target = 0;
+  void const *cur;
+  for (cur = beg; cur < end && !target; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
+    uint_fast8_t actual = ((uint8_t const *)cur)[2];
+    uint8_t const *p = sub_types;
+    do {
+      target = *p++;
+    } while (target && target != actual);
+  } 
+  return cur;
+}
+
+/** Find the first descriptor specified by the arguments
+ *
+ * @param[in] beg        The head of descriptor byte array.
+ * @param[in] end        The tail of descriptor byte array.
+ * @param[in] desc_type  The target descriptor type
+ * @param[in] element_0  The target element following the desc_type
+ *
+ * @return The pointer for interface descriptor.
+ * @retval end   did not found interface descriptor */
+static void const* _find_desc_2(void const *beg, void const *end,
+                                uint_fast8_t desc_type, uint_fast8_t element_0)
+{
+  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) {
+    uint8_t const *p = (uint8_t const *)cur;
+    if (p[2] == element_0) return cur;
+    cur = tu_desc_next(cur);
+  }
+  return end;
+}
+
 /** Find the first descriptor specified by the arguments
  *
  * @param[in] beg        The head of descriptor byte array.
@@ -235,14 +327,19 @@ static inline void const* _find_desc_itf(void const *beg, void const *end, uint_
  * @retval end   did not found endpoint descriptor */
 static void const* _find_desc_ep(void const *beg, void const *end)
 {
-  for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) {
-    uint_fast8_t desc_type = tu_desc_type(cur);
-    if (TUSB_DESC_ENDPOINT == desc_type) return cur;
-    if (TUSB_DESC_INTERFACE == desc_type) break;
-  }
+  void const *cur = _find_desc_n(beg, end, TUSB_DESC_ENDPOINT, TUSB_DESC_INTERFACE, 0);
+  if ((cur < end) && (TUSB_DESC_ENDPOINT == tu_desc_type(cur)))
+    return cur;
   return end;
 }
 
+/** Return the end of the video control descriptor. */
+static inline void const* _end_of_control_descriptor(void const *desc)
+{
+  tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)desc;
+  return desc + vc->std.bLength + vc->ctl.wTotalLength;
+}
+
 /** Find the first entity descriptor with the entity ID
  *  specified by the argument belonging to the current video control descriptor.
  *
@@ -253,10 +350,8 @@ static void const* _find_desc_ep(void const *beg, void const *end)
  * @retval end   did not found interface descriptor */
 static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid)
 {
-  tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const*)desc;
-  void const *beg = vc;
-  void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength;
-  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
+  void const *end = _end_of_control_descriptor(desc);
+  for (void const *cur = desc; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
     tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
     if ((VIDEO_CS_ITF_VC_INPUT_TERMINAL  <= itf->bDescriptorSubtype
          && itf->bDescriptorSubtype < VIDEO_CS_ITF_VC_MAX)
@@ -276,17 +371,38 @@ static inline void const* _end_of_streaming_descriptor(void const *desc)
 }
 
 /** Find the first format descriptor with the specified format number. */
-static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum)
+static inline void const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum)
 {
-  return (tusb_desc_cs_video_fmt_uncompressed_t const*)
-    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED, fmtnum);
+  static uint8_t const sub_types[] = {
+    VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED,
+    VIDEO_CS_ITF_VS_FORMAT_MJPEG,
+    VIDEO_CS_ITF_VS_FORMAT_DV,
+    VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED,
+    0
+  };
+  while (true) {
+    uint8_t const *cur = _find_desc_cs(beg, end, sub_types);
+    if ((end == cur) || (fmtnum == cur[3]))
+      return cur;
+    cur = tu_desc_next(cur);
+  }
 }
 
 /** Find the first frame descriptor with the specified format number. */
-static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum)
+static inline void const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum)
 {
-  return (tusb_desc_cs_video_frm_uncompressed_t const*)
-    _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, frmnum);
+  static uint8_t const sub_types[] = {
+    VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED,
+    VIDEO_CS_ITF_VS_FRAME_MJPEG,
+    VIDEO_CS_ITF_VS_FRAME_FRAME_BASED,
+    0
+  };
+  while (true) {
+    uint8_t const *cur = _find_desc_cs(beg, end, sub_types);
+    if ((end == cur) || (frmnum == ((uint8_t const *)cur)[3]))
+      return cur;
+    cur = tu_desc_next(cur);
+  }
 }
 
 /** Set uniquely determined values to variables that have not been set
@@ -307,7 +423,6 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   /* Set the parameters determined by the format  */
   param->wKeyFrameRate    = 1;
   param->wPFrameRate      = 0;
-  param->wCompQuality     = 1; /* 1 to 10000 */
   param->wCompWindowSize  = 1; /* GOP size? */
   param->wDelay           = 0; /* milliseconds */
   param->dwClockFrequency = 27000000; /* same as MPEG-2 system time clock  */
@@ -319,8 +434,18 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   param->bBitDepthLuma    = 8;
 
   void const *end = _end_of_streaming_descriptor(vs);
-  tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
+  tusb_desc_cs_video_fmt_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
   TU_ASSERT(fmt != end);
+
+  switch (fmt->bDescriptorSubtype) {
+    case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
+      param->wCompQuality = 1; /* 1 to 10000 */
+      break;
+    case VIDEO_CS_ITF_VS_FORMAT_MJPEG;
+      break;
+    default: return false;
+  }
+
   uint_fast8_t frmnum = param->bFrameIndex;
   TU_ASSERT(frmnum <= fmt->bNumFrameDescriptors);
   if (!frmnum) {
@@ -328,13 +453,21 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
     frmnum = 1;
     param->bFrameIndex = 1;
   }
-  tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
+  tusb_desc_cs_video_frm_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
   TU_ASSERT(frm != end);
 
   /* Set the parameters determined by the frame  */
   uint_fast32_t frame_size = param->dwMaxVideoFrameSize;
   if (!frame_size) {
-    frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->bBitsPerPixel / 8;
+    switch (fmt->bDescriptorSubtype) {
+      case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
+        frame_size = (uint_fast32_t)frm->uncompressed.wWidth * frm->uncompressed.wHeight * fmt->uncompressed.bBitsPerPixel / 8;
+        break;
+      case VIDEO_CS_ITF_VS_FORMAT_MJPEG;
+        frame_size = (uint_fast32_t)frm->mjpeg.wWidth * frm->mjpeg.wHeight * 16 / 8; /* YUV422 */
+        break;
+      default: break;
+    }
     param->dwMaxVideoFrameSize = frame_size;
   }
 
@@ -487,7 +620,7 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
   /* The next descriptor after the class-specific VC interface header descriptor. */
   void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength;
   /* The end of the video control interface descriptor. */
-  void const *end = (void const*)vc + vc->std.bLength + vc->ctl.wTotalLength;
+  void const *end = _end_of_control_descriptor(vc);
   if (vc->std.bNumEndpoints) {
     /* Find the notification endpoint descriptor. */
     cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
@@ -519,7 +652,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
   TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING);
 
   /* Update to point the end of the video control interface descriptor. */
-  end  = cur + vc->std.bLength + vc->ctl.wTotalLength;
+  end  = _end_of_control_descriptor(cur);
   /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
   cur += vc->std.bLength + vc->ctl.bLength;
   TU_LOG2("    bNumEndpoints %d\n", vc->std.bNumEndpoints);

From 1debf6270786a612ad99172db76169e025e124f6 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 10 Nov 2021 00:39:51 +0900
Subject: [PATCH 1161/2085] Fix compile errors

---
 .../video_capture/src/usb_descriptors.h       |  6 ++---
 src/class/video/video_device.c                | 24 +++++++++++--------
 2 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index aa937e168..10bae4750 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -53,8 +53,8 @@ enum {
     /* Interface 1, Alternate 0 */\
     + TUD_VIDEO_DESC_STD_VS_LEN\
     + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
-    + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
-    + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
     + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
     /* Interface 1, Alternate 1 */\
     + TUD_VIDEO_DESC_STD_VS_LEN\
@@ -98,7 +98,7 @@ enum {
         /*bmaControls(1)*/0), \
       /* Video stream format */ \
       TUD_VIDEO_DESC_CS_VS_FMT_MJPEG(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
-        1, /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /*bmFlags*/0, /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
         /* Video stream frame format */ \
         TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT(/*bFrameIndex */1, 0, _width, _height, \
             _width * _height * 16, _width * _height * 16 * _fps, \
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 39e2e9aac..14eaca9a4 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -67,6 +67,7 @@ typedef union {
     uint8_t bDescriptorType;
     uint8_t bDescriptorSubType;
     uint8_t bFormatIndex;
+    uint8_t bNumFrameDescriptors;
   };
   tusb_desc_cs_video_fmt_uncompressed_t uncompressed;
   tusb_desc_cs_video_fmt_mjpeg_t        mjpeg;
@@ -437,11 +438,11 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   tusb_desc_cs_video_fmt_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
   TU_ASSERT(fmt != end);
 
-  switch (fmt->bDescriptorSubtype) {
+  switch (fmt->bDescriptorSubType) {
     case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
       param->wCompQuality = 1; /* 1 to 10000 */
       break;
-    case VIDEO_CS_ITF_VS_FORMAT_MJPEG;
+  case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
       break;
     default: return false;
   }
@@ -459,11 +460,11 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   /* Set the parameters determined by the frame  */
   uint_fast32_t frame_size = param->dwMaxVideoFrameSize;
   if (!frame_size) {
-    switch (fmt->bDescriptorSubtype) {
+    switch (fmt->bDescriptorSubType) {
       case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
         frame_size = (uint_fast32_t)frm->uncompressed.wWidth * frm->uncompressed.wHeight * fmt->uncompressed.bBitsPerPixel / 8;
         break;
-      case VIDEO_CS_ITF_VS_FORMAT_MJPEG;
+      case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
         frame_size = (uint_fast32_t)frm->mjpeg.wWidth * frm->mjpeg.wHeight * 16 / 8; /* YUV422 */
         break;
       default: break;
@@ -473,11 +474,12 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
 
   uint_fast32_t interval = param->dwFrameInterval;
   if (!interval) {
-    if ((1 < frm->bFrameIntervalType) ||
-        ((0 == frm->bFrameIntervalType) && (frm->dwFrameInterval[1] != frm->dwFrameInterval[0]))) {
+    if ((1 < frm->uncompressed.bFrameIntervalType) ||
+        ((0 == frm->uncompressed.bFrameIntervalType) &&
+         (frm->uncompressed.dwFrameInterval[1] != frm->uncompressed.dwFrameInterval[0]))) {
       return true;
     }
-    interval = frm->dwFrameInterval[0];
+    interval = frm->uncompressed.dwFrameInterval[0];
     param->dwFrameInterval = interval;
   }
   uint_fast32_t interval_ms = interval / 10000;
@@ -709,6 +711,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     video_probe_and_commit_control_t *param =
       (video_probe_and_commit_control_t *)&stm->ep_buf;
     tu_memclr(param, sizeof(*param));
+    TU_LOG2("    done 0\n");
     return _update_streaming_parameters(stm, param);
   }
   /* Open endpoints of the new settings. */
@@ -737,6 +740,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
   hdr->bHeaderLength = sizeof(*hdr);
   hdr->bmHeaderInfo  = 0;
 
+  TU_LOG2("    done\n");
   return true;
 }
 
@@ -809,7 +813,7 @@ static int handle_video_ctl_cs_req(uint8_t rhport, uint8_t stage,
           if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, &self->power_mode, sizeof(self->power_mode)), VIDEO_ERROR_UNKNOWN);
-          } else if (stage == CONTROL_STAGE_ACK) {
+          } else if (stage == CONTROL_STAGE_DATA) {
             if (tud_video_power_mode_cb) return tud_video_power_mode_cb(ctl_idx, self->power_mode);
           }
           return VIDEO_ERROR_NONE;
@@ -954,7 +958,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
             TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)),
                       VIDEO_ERROR_UNKNOWN);
-          } else if (stage == CONTROL_STAGE_ACK) {
+          } else if (stage == CONTROL_STAGE_DATA) {
             TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf),
                       VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
           }
@@ -1009,7 +1013,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           if (stage == CONTROL_STAGE_SETUP) {
             TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
-          } else if (stage == CONTROL_STAGE_ACK) {
+          } else if (stage == CONTROL_STAGE_DATA) {
             TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
             if (tud_video_commit_cb) {
               return tud_video_commit_cb(self->index_vc, self->index_vs, (video_probe_and_commit_control_t*)self->ep_buf);

From 16518dcbbb6f20182a6f69556908afe35a7f6e25 Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Mon, 5 Sep 2022 12:50:05 +0100
Subject: [PATCH 1162/2085] Refactor pointer arithmetic on void*

This is a GCC extension, illegal in ISO C. IAR generates errors Pa152
'these operand types cannot be used here' and Pe852 'expression must be a
pointer to a complete object type'.

Replace with uint8_t*.
---
 src/class/video/video_device.c | 89 +++++++++++++++++-----------------
 1 file changed, 44 insertions(+), 45 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 7636db5fe..1f653f5c5 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -80,7 +80,7 @@ typedef struct TU_ATTR_PACKED {
 
 /* video control interface */
 typedef struct TU_ATTR_PACKED {
-  void const *beg;  /* The head of the first video control interface descriptor */
+  uint8_t const *beg;  /* The head of the first video control interface descriptor */
   uint16_t    len;  /* Byte length of the descriptors */
   uint16_t    cur;  /* offset for current video control interface */
   uint8_t     stm[CFG_TUD_VIDEO_STREAMING]; /* Indices of streaming interface */
@@ -108,9 +108,9 @@ static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
  * @param[in] desc    interface descriptor
  *
  * @return bInterfaceNumber */
-static inline uint8_t _desc_itfnum(void const *desc)
+static inline uint8_t _desc_itfnum(uint8_t const *desc)
 {
-  return ((uint8_t const*)desc)[2];
+  return desc[2];
 }
 
 /** Get endpoint address from the endpoint descriptor
@@ -118,9 +118,9 @@ static inline uint8_t _desc_itfnum(void const *desc)
  * @param[in] desc    endpoint descriptor
  *
  * @return bEndpointAddress */
-static inline uint8_t _desc_ep_addr(void const *desc)
+static inline uint8_t _desc_ep_addr(uint8_t const *desc)
 {
-  return ((uint8_t const*)desc)[2];
+  return desc[2];
 }
 
 /** Get instance of streaming interface
@@ -146,7 +146,7 @@ static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self)
 static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self)
 {
   if (!self->desc.cur) return NULL;
-  void const *desc = _videod_itf[self->index_vc].beg;
+  uint8_t const *desc = _videod_itf[self->index_vc].beg;
   return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur);
 }
 
@@ -158,9 +158,9 @@ static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _find_desc(void const *beg, void const *end, uint_fast8_t desc_type)
+static uint8_t const* _find_desc(uint8_t const *beg, uint8_t const *end, uint_fast8_t desc_type)
 {
-  void const *cur = beg;
+  uint8_t const *cur = beg;
   while ((cur < end) && (desc_type != tu_desc_type(cur))) {
     cur = tu_desc_next(cur);
   }
@@ -177,14 +177,13 @@ static void const* _find_desc(void const *beg, void const *end, uint_fast8_t des
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _find_desc_3(void const *beg, void const *end,
-                                uint_fast8_t desc_type,
-                                uint_fast8_t element_0,
-                                uint_fast8_t element_1)
+static uint8_t const* _find_desc_3(uint8_t const *beg, uint8_t const *end,
+                                   uint_fast8_t desc_type,
+                                   uint_fast8_t element_0,
+                                   uint_fast8_t element_1)
 {
-  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) {
-    uint8_t const *p = (uint8_t const *)cur;
-    if ((p[2] == element_0) && (p[3] == element_1)) {
+  for (uint8_t const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) {
+    if ((cur[2] == element_0) && (cur[3] == element_1)) {
       return cur;
     }
     cur = tu_desc_next(cur);
@@ -199,9 +198,9 @@ static void const* _find_desc_3(void const *beg, void const *end,
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _next_desc_itf(void const *beg, void const *end)
+static uint8_t const* _next_desc_itf(void const *beg, uint8_t const *end)
 {
-  void const *cur = beg;
+  uint8_t const *cur = beg;
   uint_fast8_t itfnum = ((tusb_desc_interface_t const*)cur)->bInterfaceNumber;
   while ((cur < end) &&
          (itfnum == ((tusb_desc_interface_t const*)cur)->bInterfaceNumber)) {
@@ -219,7 +218,7 @@ static void const* _next_desc_itf(void const *beg, void const *end)
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static inline void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum)
+static inline uint8_t const* _find_desc_itf(uint8_t const *beg, uint8_t const *end, uint_fast8_t itfnum, uint_fast8_t altnum)
 {
   return _find_desc_3(beg, end, TUSB_DESC_INTERFACE, itfnum, altnum);
 }
@@ -233,9 +232,9 @@ static inline void const* _find_desc_itf(void const *beg, void const *end, uint_
  *
  * @return The pointer for endpoint descriptor.
  * @retval end   did not found endpoint descriptor */
-static void const* _find_desc_ep(void const *beg, void const *end)
+static uint8_t const* _find_desc_ep(uint8_t const *beg, uint8_t const *end)
 {
-  for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) {
+  for (uint8_t const *cur = beg; cur < end; cur = tu_desc_next(cur)) {
     uint_fast8_t desc_type = tu_desc_type(cur);
     if (TUSB_DESC_ENDPOINT == desc_type) return cur;
     if (TUSB_DESC_INTERFACE == desc_type) break;
@@ -251,17 +250,17 @@ static void const* _find_desc_ep(void const *beg, void const *end)
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid)
+static uint8_t const* _find_desc_entity(void const *desc, uint_fast8_t entityid)
 {
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const*)desc;
-  void const *beg = vc;
-  void const *end = beg + vc->std.bLength + vc->ctl.wTotalLength;
-  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
+  uint8_t const *beg = desc;
+  uint8_t const *end = beg + vc->std.bLength + vc->ctl.wTotalLength;
+  for (uint8_t const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
     tusb_desc_cs_video_entity_itf_t const *itf = (tusb_desc_cs_video_entity_itf_t const *)cur;
     if ((VIDEO_CS_ITF_VC_INPUT_TERMINAL  <= itf->bDescriptorSubtype
          && itf->bDescriptorSubtype < VIDEO_CS_ITF_VC_MAX)
         && itf->bEntityId == entityid) {
-      return itf;
+      return cur;
     }
     cur = tu_desc_next(cur);
   }
@@ -272,18 +271,18 @@ static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid)
 static inline void const* _end_of_streaming_descriptor(void const *desc)
 {
   tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)desc;
-  return desc + vs->std.bLength + vs->stm.wTotalLength;
+  return (uint8_t const *)desc + vs->std.bLength + vs->stm.wTotalLength;
 }
 
 /** Find the first format descriptor with the specified format number. */
-static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum)
+static inline tusb_desc_cs_video_fmt_uncompressed_t const *_find_desc_format(uint8_t const *beg, uint8_t const *end, uint_fast8_t fmtnum)
 {
   return (tusb_desc_cs_video_fmt_uncompressed_t const*)
     _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED, fmtnum);
 }
 
 /** Find the first frame descriptor with the specified format number. */
-static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum)
+static inline tusb_desc_cs_video_frm_uncompressed_t const *_find_desc_frame(uint8_t const *beg, uint8_t const *end, uint_fast8_t frmnum)
 {
   return (tusb_desc_cs_video_frm_uncompressed_t const*)
     _find_desc_3(beg, end, TUSB_DESC_CS_INTERFACE, VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED, frmnum);
@@ -485,9 +484,9 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
 {
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
   /* The next descriptor after the class-specific VC interface header descriptor. */
-  void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength;
+  uint8_t const *cur = (uint8_t const*)vc + vc->std.bLength + vc->ctl.bLength;
   /* The end of the video control interface descriptor. */
-  void const *end = (void const*)vc + vc->std.bLength + vc->ctl.wTotalLength;
+  uint8_t const *end = (uint8_t const*)vc + vc->std.bLength + vc->ctl.wTotalLength;
   if (vc->std.bNumEndpoints) {
     /* Find the notification endpoint descriptor. */
     cur = _find_desc(cur, end, TUSB_DESC_ENDPOINT);
@@ -506,10 +505,10 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum)
 {
   TU_LOG2("    open VC %d\n", altnum);
-  void const *beg = self->beg;
-  void const *end = beg + self->len;
+  uint8_t const *beg = self->beg;
+  uint8_t const *end = beg + self->len;
   /* The first descriptor is a video control interface descriptor. */
-  void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
+  uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
   TU_LOG2("    cur %d\n", cur - beg);
   TU_VERIFY(cur < end);
 
@@ -534,7 +533,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
     /* Open the notification endpoint */
     TU_ASSERT(usbd_edpt_open(rhport, notif));
   }
-  self->cur = (uint16_t) ((void const*)vc - beg);
+  self->cur = (uint16_t) ((uint8_t const*)vc - beg);
   return true;
 }
 
@@ -546,7 +545,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
 {
   uint_fast8_t i;
   TU_LOG2("    reopen VS %d\n", altnum);
-  void const *desc = _videod_itf[stm->index_vc].beg;
+  uint8_t const *desc = _videod_itf[stm->index_vc].beg;
 
   /* Close endpoints of previous settings. */
   for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) {
@@ -563,9 +562,9 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
   stm->offset  = 0;
 
   /* Find a alternate interface */
-  void const *beg = desc + stm->desc.beg;
-  void const *end = desc + stm->desc.end;
-  void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
+  uint8_t const *beg = desc + stm->desc.beg;
+  uint8_t const *end = desc + stm->desc.end;
+  uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
   TU_VERIFY(cur < end);
   uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints;
   TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep));
@@ -977,7 +976,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
   if (!stm || !stm->desc.ep[0] || stm->buffer) return false;
 
   /* Find EP address */
-  void const *desc = _videod_itf[stm->index_vc].beg;
+  uint8_t const *desc = _videod_itf[stm->index_vc].beg;
   uint8_t ep_addr = 0;
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
     uint_fast16_t ofs_ep = stm->desc.ep[i];
@@ -1044,15 +1043,15 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   }
   TU_ASSERT(ctl_idx < CFG_TUD_VIDEO, 0);
 
-  void const *end = (void const*)itf_desc + max_len;
-  self->beg = itf_desc;
+  uint8_t const *end = (uint8_t const*)itf_desc + max_len;
+  self->beg = (uint8_t const *)itf_desc;
   self->len = max_len;
   /*------------- Video Control Interface -------------*/
   TU_VERIFY(_open_vc_itf(rhport, self, 0), 0);
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
   uint_fast8_t bInCollection   = vc->ctl.bInCollection;
   /* Find the end of the video interface descriptor */
-  void const *cur = _next_desc_itf(itf_desc, end);
+  uint8_t const *cur = _next_desc_itf(itf_desc, end);
   for (uint8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) {
     videod_streaming_interface_t *stm = NULL;
     /* find free streaming interface handle */
@@ -1085,7 +1084,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   /* Identify which control interface to use */
   uint_fast8_t itf;
   for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {
-    void const *desc = _videod_itf[itf].beg;
+    uint8_t const *desc = _videod_itf[itf].beg;
     if (!desc) continue;
     if (itfnum == _desc_itfnum(desc)) break;
   }
@@ -1101,7 +1100,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) {
     videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
     if (!stm->desc.beg) continue;
-    void const *desc = _videod_itf[stm->index_vc].beg;
+    uint8_t const *desc = _videod_itf[stm->index_vc].beg;
     if (itfnum == _desc_itfnum(desc + stm->desc.beg)) break;
   }
 
@@ -1127,7 +1126,7 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     uint_fast16_t const ep_ofs = stm->desc.ep[0];
     if (!ep_ofs) continue;
     ctl = &_videod_itf[stm->index_vc];
-    void const *desc = ctl->beg;
+    uint8_t const *desc = ctl->beg;
     if (ep_addr == _desc_ep_addr(desc + ep_ofs)) break;
   }
 

From 65ba15c37d50fa470fa24c38dbf0e30eba3147c0 Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Mon, 5 Sep 2022 12:53:49 +0100
Subject: [PATCH 1163/2085] Remove unreachable code

IAR generates warning Pe111 'statement is unreachable'. In a couple of
cases, replace return statements with TU_ATTR_FALLTHROUGH; because some
compilers apparently can't figure out that the return statements are
unreachable but do whinge about an imagined fall-through without them!
---
 examples/device/audio_4_channel_mic/src/main.c    |  3 ---
 examples/device/audio_test/src/main.c             |  3 ---
 examples/device/board_test/src/main.c             |  2 --
 examples/device/cdc_dual_ports/src/main.c         |  2 --
 examples/device/cdc_msc/src/main.c                |  2 --
 examples/device/dfu/src/main.c                    |  2 --
 examples/device/dfu_runtime/src/main.c            |  2 --
 examples/device/dynamic_configuration/src/main.c  |  2 --
 examples/device/hid_composite/src/main.c          |  2 --
 examples/device/hid_generic_inout/src/main.c      |  2 --
 examples/device/hid_multiple_interface/src/main.c |  2 --
 examples/device/midi_test/src/main.c              |  3 ---
 examples/device/msc_dual_lun/src/main.c           |  2 --
 examples/device/uac2_headset/src/main.c           |  2 --
 examples/device/usbtmc/src/main.c                 |  2 --
 examples/device/usbtmc/src/usbtmc_app.c           |  1 -
 examples/device/video_capture/src/main.c          |  2 --
 examples/device/webusb_serial/src/main.c          |  2 --
 examples/host/cdc_msc_hid/src/main.c              |  2 --
 examples/host/hid_controller/src/main.c           |  2 --
 src/class/usbtmc/usbtmc_device.c                  | 10 +++-------
 src/class/video/video_device.c                    |  1 -
 src/portable/raspberrypi/rp2040/hcd_rp2040.c      |  6 ++----
 23 files changed, 5 insertions(+), 54 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index a6af5fd19..662f67df3 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -99,9 +99,6 @@ int main(void)
     led_blinking_task();
     audio_task();
   }
-
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index d0849c7ac..4b88c2883 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -100,9 +100,6 @@ int main(void)
     led_blinking_task();
     audio_task();
   }
-
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index 5e28cbb27..207ca6294 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -67,8 +67,6 @@ int main(void)
       led_state = 1 - led_state; // toggle
     }
   }
-
-  return 0;
 }
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 0264f0566..893b0dbc5 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -47,8 +47,6 @@ int main(void)
     tud_task(); // tinyusb device task
     cdc_task();
   }
-
-  return 0;
 }
 
 // echo to either Serial0 or Serial1
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index c3666763b..043b4e8f5 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -65,8 +65,6 @@ int main(void)
 
     cdc_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 6bb183819..5f37f25e1 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -82,8 +82,6 @@ int main(void)
     tud_task(); // tinyusb device task
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index 55b380353..3c5f04e82 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -77,8 +77,6 @@ int main(void)
     tud_task(); // tinyusb device task
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index 33a603343..69b3acd19 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -66,8 +66,6 @@ int main(void)
     cdc_task();
     midi_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index f7d76cfc7..75a0633a3 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -67,8 +67,6 @@ int main(void)
 
     hid_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 5b7daf118..e692d3bd3 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -88,8 +88,6 @@ int main(void)
     tud_task(); // tinyusb device task
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c
index 29ba74398..72240b208 100644
--- a/examples/device/hid_multiple_interface/src/main.c
+++ b/examples/device/hid_multiple_interface/src/main.c
@@ -71,8 +71,6 @@ int main(void)
 
     hid_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 3310348bd..ddf419fe9 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -71,9 +71,6 @@ int main(void)
     led_blinking_task();
     midi_task();
   }
-
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index 96790d20c..18038e442 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -62,8 +62,6 @@ int main(void)
     tud_task(); // tinyusb device task
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 003dc2a74..3256bc272 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -113,8 +113,6 @@ int main(void)
     audio_task();
     led_blinking_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 6945d8743..8fc06b56c 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -63,8 +63,6 @@ int main(void)
     led_blinking_task();
     usbtmc_app_task_iter();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index 115163c7f..e1ce115ad 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -254,7 +254,6 @@ void usbtmc_app_task_iter(void) {
     break;
   default:
     TU_ASSERT(false,);
-    return;
   }
 }
 
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 4028352da..0f81c693a 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -66,8 +66,6 @@ int main(void)
 
     video_task();
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index 604d30a83..23aa79f58 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -103,8 +103,6 @@ int main(void)
     webserial_task();
     led_blinking_task();
   }
-
-  return 0;
 }
 
 // send characters to both CDC and WebUSB
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index 664cbf035..091c002ac 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -62,8 +62,6 @@ int main(void)
     hid_app_task();
 #endif
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index 299a3ff10..13d1d6cdb 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -68,8 +68,6 @@ int main(void)
     hid_app_task();
 #endif
   }
-
-  return 0;
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index af4a92732..64db85fcf 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -496,7 +496,6 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
       default:
         usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
         TU_VERIFY(false);
-        return false;
       }
       return true;
 
@@ -509,8 +508,8 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
       return true;
 
     case STATE_ABORTING_BULK_OUT:
-      TU_VERIFY(false);
-      return false; // Should be stalled by now, shouldn't have received a packet.
+      TU_VERIFY(false); // Should be stalled by now, shouldn't have received a packet.
+      TU_ATTR_FALLTHROUGH; // Not really - some compilers can't figure out that the above macro always returns.
 
     case STATE_TX_REQUESTED:
     case STATE_TX_INITIATED:
@@ -567,7 +566,6 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
 
     default:
       TU_ASSERT(false);
-      return false;
     }
   }
   else if (ep_addr == usbtmc_state.ep_int_in) {
@@ -872,15 +870,13 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
     {
       TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface
       TU_VERIFY(false);
-      return false;
+      TU_ATTR_FALLTHROUGH; // Not really - some compilers can't figure out that the above macro always returns.
     }
 #endif
 
   default:
     TU_VERIFY(false);
-    return false;
   }
-  TU_VERIFY(false);
 }
 
 #endif /* CFG_TUD_TSMC */
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 1f653f5c5..a27287360 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -943,7 +943,6 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage,
 
     default: return VIDEO_ERROR_INVALID_REQUEST;
   }
-  return VIDEO_ERROR_UNKNOWN;
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 5badb261a..f65749a2f 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -432,8 +432,7 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
       case 2:
           return TUSB_SPEED_FULL;
       default:
-          panic("Invalid speed\n");
-          return TUSB_SPEED_INVALID;
+          panic("Invalid speed\n"); // does not return
   }
 }
 
@@ -599,8 +598,7 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
     (void) dev_addr;
     (void) ep_addr;
 
-    panic("hcd_clear_stall");
-    return true;
+    panic("hcd_clear_stall"); // does not return
 }
 
 #endif

From 53f0d5538bd2ab171567c9ba3138522accc8145d Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Thu, 1 Sep 2022 12:34:25 +0100
Subject: [PATCH 1164/2085] Don't assume ints automatically convert to enums

IAR generates warning Pe188 'enumerated type mixed with another type'.
---
 examples/device/audio_4_channel_mic/src/main.c | 2 +-
 examples/device/audio_test/src/main.c          | 2 +-
 src/class/cdc/cdc_host.c                       | 2 +-
 src/host/usbh.c                                | 6 +++---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c   | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 662f67df3..db2e9bf95 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -287,7 +287,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
 
         // Those are dummy values for now
         ret.bNrChannels = 1;
-        ret.bmChannelConfig = 0;
+        ret.bmChannelConfig = (audio_channel_config_t) 0;
         ret.iChannelNames = 0;
 
         TU_LOG2("    Get terminal connector\r\n");
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index 4b88c2883..a3bf767f4 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -288,7 +288,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
 
         // Those are dummy values for now
         ret.bNrChannels = 1;
-        ret.bmChannelConfig = 0;
+        ret.bmChannelConfig = (audio_channel_config_t) 0;
         ret.iChannelNames = 0;
 
         TU_LOG2("    Get terminal connector\r\n");
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index ee824cb4e..09acc0c70 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -245,7 +245,7 @@ bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
 bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
 {
   (void) ep_addr;
-  tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes );
+  tuh_cdc_xfer_isr( dev_addr, event, (cdc_pipeid_t) 0, xferred_bytes );
   return true;
 }
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 9d618db92..32f701248 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -449,7 +449,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
         {
           // device 0 only has control endpoint
           TU_ASSERT(epnum == 0, );
-          usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+          usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
         }
         else
         {
@@ -461,14 +461,14 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
 
           if ( 0 == epnum )
           {
-            usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+            usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
           }else
           {
             uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
             if(drv_id < USBH_CLASS_DRIVER_COUNT)
             {
               TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
-              usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+              usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
             }
             else
             {
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 89fd6b82d..ebf352d39 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -201,7 +201,7 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void)
             usb_hw_clear->buf_status = bit;
 
             // IN transfer for even i, OUT transfer for odd i
-            struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, !(i & 1u));
+            struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, !(i & 1u) ? TUSB_DIR_IN : TUSB_DIR_OUT);
 
             // Continue xfer
             bool done = hw_endpoint_xfer_continue(ep);

From 6a2d01bae47d2660dc2d10941e767fc0bc0e97bc Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Thu, 1 Sep 2022 12:33:12 +0100
Subject: [PATCH 1165/2085] Don't assume different enum types can be combined

IAR generates warning Pa089 'enumerated type mixed with another enumerated
type'.
---
 examples/device/uac2_headset/src/usb_descriptors.h | 8 ++++----
 src/class/video/video.h                            | 2 +-
 src/device/usbd.h                                  | 8 ++++----
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 342b4fac1..7d1f60e82 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -114,7 +114,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Interface 1, Alternate 2 - alternate interface for data streaming */\
@@ -124,7 +124,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Standard AS Interface Descriptor(4.9.1) */\
@@ -138,7 +138,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
     /* Interface 2, Alternate 2 - alternate interface for data streaming */\
@@ -148,7 +148,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 844746546..eb2f6adc9 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -470,7 +470,7 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 
 /* 3.10.1.1 */
 #define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) \
-  7, TUSB_DESC_ENDPOINT, _ep, TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\
+  7, TUSB_DESC_ENDPOINT, _ep, (uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\
   U16_TO_U8S_LE(_epsize), _ep_interval
 
 /* 3.10.1.2 */
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 17b4d927b..64f166826 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -418,7 +418,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */
 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN 7
 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _interval) \
-  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval
+  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval
 
 // AUDIO simple descriptor (UAC2) for 1 microphone input
 // - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source
@@ -465,7 +465,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -514,7 +514,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -562,7 +562,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
   /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\

From caff3b5c54615a0cc4e35dadffb99af543d0165f Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Thu, 1 Sep 2022 14:29:30 +0100
Subject: [PATCH 1166/2085] Remove unused static data

This affects struct rspMsg in usbtmc_app.c (unconditionally) and uint8_t
termChar in usbtmc_device.c (when NDEBUG is defined). IAR generates warning
Pe550 'variable was set but never used'.
---
 examples/device/usbtmc/src/usbtmc_app.c | 11 -----------
 src/class/usbtmc/usbtmc_device.c        |  4 ++++
 2 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index e1ce115ad..0057a429f 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -92,14 +92,6 @@ static size_t buffer_tx_ix; // for transmitting using multiple transfers
 static uint8_t buffer[225]; // A few packets long should be enough.
 
 
-static usbtmc_msg_dev_dep_msg_in_header_t rspMsg = {
-    .bmTransferAttributes =
-    {
-      .EOM = 1,
-      .UsingTermChar = 0
-    }
-};
-
 void tud_usbtmc_open_cb(uint8_t interface_id)
 {
   (void)interface_id;
@@ -188,9 +180,6 @@ static unsigned int msgReqLen;
 
 bool tud_usbtmc_msgBulkIn_request_cb(usbtmc_msg_request_dev_dep_in const * request)
 {
-  rspMsg.header.MsgID = request->header.MsgID,
-  rspMsg.header.bTag = request->header.bTag,
-  rspMsg.header.bTagInverse = request->header.bTagInverse;
   msgReqLen = request->TransferSize;
 
 #ifdef xDEBUG
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 64db85fcf..e96990c49 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -154,7 +154,9 @@ TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small");
 static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len);
 static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen);
 
+#ifndef NDEBUG
 static uint8_t termChar;
+#endif
 static uint8_t termCharRequested = false;
 
 osal_mutex_def_t usbtmcLockBuffer;
@@ -440,7 +442,9 @@ static bool handle_devMsgIn(void *data, size_t len)
   usbtmc_state.transfer_size_sent = 0u;
 
   termCharRequested = msg->bmTransferAttributes.TermCharEnabled;
+#ifndef NDEBUG
   termChar = msg->TermChar;
+#endif
 
   if(termCharRequested)
     TU_VERIFY(usbtmc_state.capabilities->bmDevCapabilities.canEndBulkInOnTermChar);

From 62d90c850096277080e4044dd37ef9c18748f06c Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Thu, 1 Sep 2022 14:33:04 +0100
Subject: [PATCH 1167/2085] Move variable into its own curly-brace scope

IAR generates warning Pe546 'transfer of control bypasses initialization of
variable "invInvTag"'.
---
 src/class/usbtmc/usbtmc_device.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index e96990c49..d7ba02d29 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -470,8 +470,10 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
     case STATE_IDLE:
       TU_VERIFY(xferred_bytes >= sizeof(usbtmc_msg_generic_t));
       msg = (usbtmc_msg_generic_t*)(usbtmc_state.ep_bulk_out_buf);
-      uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse);
-      TU_VERIFY(msg->header.bTag == invInvTag);
+      {
+        uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse);
+        TU_VERIFY(msg->header.bTag == invInvTag);
+      }
       TU_VERIFY(msg->header.bTag != 0x00);
 
       switch(msg->header.MsgID) {

From 01edbb8af6b22fa213bcbbaccd92c9be5f72b376 Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Thu, 1 Sep 2022 17:10:26 +0100
Subject: [PATCH 1168/2085] IAR doesn't support __attribute__((fallthrough))

IAR generates warning Pa167 'the "fallthrough" attribute is not supported'.
It doesn't generate warnings when one switch case falls through to another,
so simply make TU_ATTR_FALLTHROUGH expand to an empty string.

Also replace one instance of __attribute__ with the macro.
---
 src/common/tusb_compiler.h | 2 +-
 src/host/usbh.c            | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 2c30daf6f..894d0178a 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -189,7 +189,7 @@
   #define TU_ATTR_DEPRECATED(mess)      __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))             // Function/Variable is meant to be used
-  #define TU_ATTR_FALLTHROUGH           __attribute__((fallthrough))
+  #define TU_ATTR_FALLTHROUGH
 
   #define TU_ATTR_PACKED_BEGIN
   #define TU_ATTR_PACKED_END
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 32f701248..fb8479419 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1273,7 +1273,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
         break;
       }
       #endif
-      __attribute__((fallthrough));
+      TU_ATTR_FALLTHROUGH;
 #endif
 
     case ENUM_SET_ADDR:

From 73f22e31c7a31e9b974e27407b906bbc8cb05a7a Mon Sep 17 00:00:00 2001
From: Ben Avison <code@piccolosystems.com>
Date: Mon, 12 Sep 2022 14:46:26 +0100
Subject: [PATCH 1169/2085] [rp2040] Wrap GCC pragmas in #ifdef __GNUC__

IAR generates warning Pe161 'unrecognized #pragma'.
---
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 25c013bd2..adb9151f9 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -57,15 +57,19 @@ void rp2040_usb_init(void)
   reset_block(RESETS_RESET_USBCTRL_BITS);
   unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
 
+#ifdef __GNUC__
   // Clear any previous state just in case
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Warray-bounds"
 #if __GNUC__ > 6
 #pragma GCC diagnostic ignored "-Wstringop-overflow"
+#endif
 #endif
   memset(usb_hw, 0, sizeof(*usb_hw));
   memset(usb_dpram, 0, sizeof(*usb_dpram));
+#ifdef __GNUC__
 #pragma GCC diagnostic pop
+#endif
 
   // Mux the controller to the onboard usb phy
   usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;

From 6c3c2df82343e1947a7be3c5f0e72a116c1b634e Mon Sep 17 00:00:00 2001
From: Mark K Cowan <mark@battlesnake.co.uk>
Date: Sat, 17 Sep 2022 21:27:04 +0300
Subject: [PATCH 1170/2085] audio_device: prototype added for function
 referenced before use

---
 src/class/audio/audio_device.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index a021755ba..a65d605b7 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -447,6 +447,10 @@ static inline uint8_t tu_desc_subtype(void const* desc)
 }
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq);
+#endif
+
 bool tud_audio_n_mounted(uint8_t func_id)
 {
   TU_VERIFY(func_id < CFG_TUD_AUDIO);

From ee832e4e37a0ea35d9c2751ee3600ae7a600cb12 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 3 Oct 2022 21:41:58 +0900
Subject: [PATCH 1171/2085] Fix descriptor searching

---
 src/class/video/video_device.c | 121 ++++++++-------------------------
 1 file changed, 28 insertions(+), 93 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 14eaca9a4..690e64658 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -29,8 +29,6 @@
 
 #if (CFG_TUD_ENABLED && CFG_TUD_VIDEO && CFG_TUD_VIDEO_STREAMING)
 
-#include <stdarg.h>
-
 #include "device/usbd.h"
 #include "device/usbd_pvt.h"
 
@@ -194,72 +192,6 @@ static void const* _find_desc(void const *beg, void const *end, uint_fast8_t des
   return cur;
 }
 
-/** Find the first descriptor of a given types
- *
- * @param[in] beg        The head of descriptor byte array.
- * @param[in] end        The tail of descriptor byte array.
- * @param[in] ...        The target descriptor types. The last type must be 0.
- *
- * @return The pointer for interface descriptor.
- * @retval end   did not found interface descriptor */
-static void const* _find_desc_n(void const *beg, void const *end, ...)
-{
-  uint_fast8_t target = 0;
-  void const *cur;
-  for (cur = beg; cur < end && !target; cur = tu_desc_next(cur)) {
-    uint_fast8_t actual = tu_desc_type(cur);
-    va_list ap;
-    va_start(ap, end);
-    do {
-      target = va_arg(ap, unsigned);
-    } while (target && target != actual);
-    va_end(ap);
-  } 
-  return cur;
-}
-
-/** Find the first descriptor specified by the arguments
- *
- * @param[in] beg        The head of descriptor byte array.
- * @param[in] end        The tail of descriptor byte array.
- * @param[in] sub_types  The target bDescriptorSubtype list. The last elemnt must be 0.
- *
- * @return The pointer for interface descriptor.
- * @retval end   did not found interface descriptor */
-static void const* _find_desc_cs(void const *beg, void const *end, uint8_t const *sub_types)
-{
-  uint_fast8_t target = 0;
-  void const *cur;
-  for (cur = beg; cur < end && !target; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
-    uint_fast8_t actual = ((uint8_t const *)cur)[2];
-    uint8_t const *p = sub_types;
-    do {
-      target = *p++;
-    } while (target && target != actual);
-  } 
-  return cur;
-}
-
-/** Find the first descriptor specified by the arguments
- *
- * @param[in] beg        The head of descriptor byte array.
- * @param[in] end        The tail of descriptor byte array.
- * @param[in] desc_type  The target descriptor type
- * @param[in] element_0  The target element following the desc_type
- *
- * @return The pointer for interface descriptor.
- * @retval end   did not found interface descriptor */
-static void const* _find_desc_2(void const *beg, void const *end,
-                                uint_fast8_t desc_type, uint_fast8_t element_0)
-{
-  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, desc_type)) {
-    uint8_t const *p = (uint8_t const *)cur;
-    if (p[2] == element_0) return cur;
-    cur = tu_desc_next(cur);
-  }
-  return end;
-}
-
 /** Find the first descriptor specified by the arguments
  *
  * @param[in] beg        The head of descriptor byte array.
@@ -328,9 +260,11 @@ static inline void const* _find_desc_itf(void const *beg, void const *end, uint_
  * @retval end   did not found endpoint descriptor */
 static void const* _find_desc_ep(void const *beg, void const *end)
 {
-  void const *cur = _find_desc_n(beg, end, TUSB_DESC_ENDPOINT, TUSB_DESC_INTERFACE, 0);
-  if ((cur < end) && (TUSB_DESC_ENDPOINT == tu_desc_type(cur)))
-    return cur;
+  for (void const *cur = beg; cur < end; cur = tu_desc_next(cur)) {
+    uint_fast8_t desc_type = tu_desc_type(cur);
+    if (TUSB_DESC_ENDPOINT == desc_type) return cur;
+    if (TUSB_DESC_INTERFACE == desc_type) break;
+  }
   return end;
 }
 
@@ -374,36 +308,36 @@ static inline void const* _end_of_streaming_descriptor(void const *desc)
 /** Find the first format descriptor with the specified format number. */
 static inline void const *_find_desc_format(void const *beg, void const *end, uint_fast8_t fmtnum)
 {
-  static uint8_t const sub_types[] = {
-    VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED,
-    VIDEO_CS_ITF_VS_FORMAT_MJPEG,
-    VIDEO_CS_ITF_VS_FORMAT_DV,
-    VIDEO_CS_ITF_VS_FORMAT_FRAME_BASED,
-    0
-  };
-  while (true) {
-    uint8_t const *cur = _find_desc_cs(beg, end, sub_types);
-    if ((end == cur) || (fmtnum == cur[3]))
+  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
+    uint8_t const *p = (uint8_t const *)cur;
+    uint_fast8_t fmt = p[2];
+    if ((fmt == VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED ||
+         fmt == VIDEO_CS_ITF_VS_FORMAT_MJPEG ||
+         fmt == VIDEO_CS_ITF_VS_FORMAT_DV ||
+         fmt == VIDEO_CS_ITF_VS_FRAME_FRAME_BASED) &&
+        fmtnum == p[3]) {
       return cur;
+    }
     cur = tu_desc_next(cur);
   }
+  return end;
 }
 
 /** Find the first frame descriptor with the specified format number. */
 static inline void const *_find_desc_frame(void const *beg, void const *end, uint_fast8_t frmnum)
 {
-  static uint8_t const sub_types[] = {
-    VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED,
-    VIDEO_CS_ITF_VS_FRAME_MJPEG,
-    VIDEO_CS_ITF_VS_FRAME_FRAME_BASED,
-    0
-  };
-  while (true) {
-    uint8_t const *cur = _find_desc_cs(beg, end, sub_types);
-    if ((end == cur) || (frmnum == ((uint8_t const *)cur)[3]))
+  for (void const *cur = beg; cur < end; cur = _find_desc(cur, end, TUSB_DESC_CS_INTERFACE)) {
+    uint8_t const *p = (uint8_t const *)cur;
+    uint_fast8_t frm = p[2];
+    if ((frm == VIDEO_CS_ITF_VS_FRAME_UNCOMPRESSED ||
+         frm == VIDEO_CS_ITF_VS_FRAME_MJPEG ||
+         frm == VIDEO_CS_ITF_VS_FRAME_FRAME_BASED) &&
+        frmnum == p[3]) {
       return cur;
+    }
     cur = tu_desc_next(cur);
   }
+  return end;
 }
 
 /** Set uniquely determined values to variables that have not been set
@@ -501,7 +435,8 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
   if (!fmtnum) {
     switch (request) {
       case VIDEO_REQUEST_GET_MAX:
-        param->bFormatIndex = _get_desc_vs(stm)->stm.bNumFormats;
+        if (_get_desc_vs(stm))
+          param->bFormatIndex = _get_desc_vs(stm)->stm.bNumFormats;
         break;
       case VIDEO_REQUEST_GET_MIN:
       case VIDEO_REQUEST_GET_DEF:
@@ -982,7 +917,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
             video_probe_and_commit_control_t tmp;
             tmp = *(video_probe_and_commit_control_t*)&self->ep_buf;
             TU_VERIFY(_negotiate_streaming_parameters(self, request->bRequest, &tmp), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
-            TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, &tmp, sizeof(tmp)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 
@@ -999,7 +934,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
           if (stage == CONTROL_STAGE_SETUP)
           {
             TU_VERIFY(1 == request->wLength, VIDEO_ERROR_UNKNOWN);
-            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t) &_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(tud_control_xfer(rhport, request, (uint8_t*)(uintptr_t)&_cap_get_set, sizeof(_cap_get_set)), VIDEO_ERROR_UNKNOWN);
           }
           return VIDEO_ERROR_NONE;
 

From 988eeb50c6c962279360b457803859956a0d38e4 Mon Sep 17 00:00:00 2001
From: mingpepe <mingpepemath@gmail.com>
Date: Wed, 5 Oct 2022 21:26:22 +0800
Subject: [PATCH 1172/2085] Fix typo for log in dcd_rp2040.c

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 2003f72fd..4952d29b1 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -88,7 +88,7 @@ static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
   uint dpram_offset = hw_data_offset(ep->hw_data_buf);
   hard_assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX);
 
-  pico_info("  Alloced %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf);
+  pico_info("  Allocated %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf);
 
   // Fill in endpoint control register with buffer offset
   uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint)transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;

From 8096afc6dea975e95e0b50dc4b55926236b90b62 Mon Sep 17 00:00:00 2001
From: ReimuNotMoe <34613827+ReimuNotMoe@users.noreply.github.com>
Date: Thu, 6 Oct 2022 03:45:51 +0800
Subject: [PATCH 1173/2085] Microchip PIC24/dsPIC33 device mode support

---
 src/common/tusb_mcu.h                |   5 +
 src/portable/microchip/pic/dcd_pic.c | 141 ++++++++++++++++++++-------
 2 files changed, 113 insertions(+), 33 deletions(-)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index baa82fc14..514ffcd4d 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -111,6 +111,11 @@
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
+#elif TU_CHECK_MCU(OPT_MCU_PIC32MX, OPT_MCU_PIC32MM, OPT_MCU_PIC32MK) || \
+      TU_CHECK_MCU(OPT_MCU_PIC24, OPT_MCU_DSPIC33)
+  #define TUP_DCD_ENDPOINT_MAX    16
+  #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
+
 //------------- ST -------------//
 #elif TU_CHECK_MCU(OPT_MCU_STM32F0)
   #define TUP_DCD_ENDPOINT_MAX    8
diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c
index df9b2ff01..6cf0e6285 100644
--- a/src/portable/microchip/pic/dcd_pic.c
+++ b/src/portable/microchip/pic/dcd_pic.c
@@ -39,14 +39,10 @@
 
 #if (CFG_TUSB_MCU == OPT_MCU_PIC32MX || CFG_TUSB_MCU == OPT_MCU_PIC32MM || CFG_TUSB_MCU == OPT_MCU_PIC32MK)
 
-#define TU_PIC_HAS_MMU          1
-#define TU_PIC_HAS_HW_RMW       1
 #define TU_PIC_INT_SIZE         4
 
 #elif (CFG_TUSB_MCU == OPT_MCU_PIC24 || CFG_TUSB_MCU == OPT_MCU_DSPIC33)
 
-#define TU_PIC_HAS_MMU          0
-#define TU_PIC_HAS_HW_RMW       0
 #define TU_PIC_INT_SIZE         2
 
 #else
@@ -56,7 +52,7 @@
 #endif
 
 
-#if TU_PIC_HAS_MMU
+#if TU_PIC_INT_SIZE == 4
 
 #ifndef KVA_TO_PA
 #define KVA_TO_PA(kva)    ((uint32_t)(kva) & 0x1fffffff)
@@ -89,6 +85,8 @@ enum {
   TOK_PID_SETUP = 0xDu,
 };
 
+// The BDT is 8 bytes on 32bit PICs and 4 bytes on 8/16bit PICs
+#if TU_PIC_INT_SIZE == 4
 typedef struct TU_ATTR_PACKED
 {
   union {
@@ -119,6 +117,37 @@ typedef struct TU_ATTR_PACKED
 } buffer_descriptor_t;
 
 TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
+#else
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint16_t head;
+
+    struct {
+      uint16_t           :  10;
+      uint16_t tok_pid   :  4;
+      uint16_t data      :  1;
+      uint16_t own       :  1;
+    };
+    struct {
+      uint16_t           :  10;
+      uint16_t bdt_stall :  1;
+      uint16_t dts       :  1;
+      uint16_t ninc      :  1;
+      uint16_t keep      :  1;
+    };
+
+    struct {
+      uint16_t bc : 10;
+      uint16_t    :  6;
+    };
+  };
+  uint8_t *addr;
+} buffer_descriptor_t;
+
+TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 4, "size is not correct" );
+#endif
+
 
 typedef struct TU_ATTR_PACKED
 {
@@ -142,7 +171,11 @@ typedef struct
   union {
     /* [#EP][OUT,IN][EVEN,ODD] */
     buffer_descriptor_t bdt[16][2][2];
-    uint16_t            bda[512];
+#if TU_PIC_INT_SIZE == 4
+    uint16_t            bda[256];
+#else
+    uint8_t            bda[256];
+#endif
   };
   TU_ATTR_ALIGNED(4) union {
     endpoint_state_t endpoint[16][2];
@@ -158,7 +191,11 @@ typedef struct
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) volatile static dcd_data_t _dcd;
 
+#if TU_PIC_INT_SIZE == 4
 TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
+#else
+TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 256, "size is not correct" );
+#endif
 
 #if TU_PIC_INT_SIZE == 4
 typedef uint32_t ep_reg_t;
@@ -172,7 +209,12 @@ static inline volatile void *ep_addr(uint8_t rhport, uint8_t ep_num) {
 #else
   volatile void *ep_reg_base = &U1EP0;
 #endif
-  return ep_reg_base + 0x10 * ep_num;
+#if TU_PIC_INT_SIZE == 4
+  const size_t offset = 0x10;
+#else
+  const size_t offset = 0x2;
+#endif
+  return ep_reg_base + offset * ep_num;
 }
 
 static inline ep_reg_t ep_read(uint8_t rhport, uint8_t ep_num) {
@@ -186,7 +228,7 @@ static inline void ep_write(uint8_t rhport, uint8_t ep_num, ep_reg_t val) {
 }
 
 static inline void ep_clear(uint8_t rhport, uint8_t ep_num, ep_reg_t val) {
-#if TU_PIC_HAS_HW_RMW
+#if TU_PIC_INT_SIZE == 4
   volatile ep_reg_t *ep_clr = (ep_addr(rhport, ep_num) + 0x4);
   *ep_clr = val;
 #else
@@ -197,7 +239,7 @@ static inline void ep_clear(uint8_t rhport, uint8_t ep_num, ep_reg_t val) {
 }
 
 static inline void ep_set(uint8_t rhport, uint8_t ep_num, ep_reg_t val) {
-#if TU_PIC_HAS_HW_RMW
+#if TU_PIC_INT_SIZE == 4
   volatile ep_reg_t *ep_s = (ep_addr(rhport, ep_num) + 0x8);
   *ep_s = val;
 #else
@@ -278,7 +320,7 @@ static void prepare_next_setup_packet(uint8_t rhport)
   _dcd.bdt[0][1][in_odd].data      = 1;
   _dcd.bdt[0][1][in_odd ^ 1].data  = 0;
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
-                _dcd.setup_packet, sizeof(_dcd.setup_packet));
+          _dcd.setup_packet, sizeof(_dcd.setup_packet));
 }
 
 static void process_stall(uint8_t rhport)
@@ -298,7 +340,7 @@ static void process_stall(uint8_t rhport)
 
 static void process_tokdne(uint8_t rhport)
 {
-  uint32_t s = U1STAT;
+  ep_reg_t s = U1STAT;
 
   U1IR = _U1IR_TRNIF_MASK;
 
@@ -321,7 +363,11 @@ static void process_tokdne(uint8_t rhport)
   ep->odd       = odd ^ 1;
   if (pid == TOK_PID_SETUP) {
     dcd_event_setup_received(rhport, (uint8_t *)PA_TO_KVA1(bd->addr), true);
+#if TU_PIC_INT_SIZE == 4
     U1CONCLR = _U1CON_PKTDIS_TOKBUSY_MASK;
+#else
+    U1CONbits.PKTDIS = 0;
+#endif
     return;
   }
 
@@ -341,8 +387,8 @@ static void process_tokdne(uint8_t rhport)
   }
   const unsigned length = ep->length;
   dcd_event_xfer_complete(rhport,
-                          tu_edpt_addr(epnum, dir),
-                          length - remaining, XFER_RESULT_SUCCESS, true);
+        tu_edpt_addr(epnum, dir),
+        length - remaining, XFER_RESULT_SUCCESS, true);
   if (0 == epnum && 0 == length) {
     /* After completion a ZLP of control transfer,
      * it prepares for the next steup transfer. */
@@ -358,11 +404,16 @@ static void process_tokdne(uint8_t rhport)
 
 static void process_bus_reset(uint8_t rhport)
 {
+#if TU_PIC_INT_SIZE == 4
   U1PWRCCLR = _U1PWRC_USUSPEND_MASK;
   U1CONSET = _U1CON_PPBRST_MASK;
+#else
+  U1PWRCbits.USUSPND = 0;
+  U1CONbits.PPBRST = 1;
+#endif
   U1ADDR = 0;
 
-  U1IE = _U1IE_URSTIE_DETACHIE_MASK | _U1IE_TRNIE_MASK | _U1IE_IDLEIE_MASK |
+  U1IE = _U1IE_URSTIE_MASK | _U1IE_TRNIE_MASK | _U1IE_IDLEIE_MASK |
          _U1IE_UERRIE_MASK | _U1IE_STALLIE_MASK;
 
   U1EP0 = _U1EP0_EPHSHK_MASK | _U1EP0_EPRXEN_MASK | _U1EP0_EPTXEN_MASK;
@@ -386,7 +437,11 @@ static void process_bus_reset(uint8_t rhport)
   tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
   _dcd.addr = 0;
   prepare_next_setup_packet(rhport);
+#if TU_PIC_INT_SIZE == 4
   U1CONCLR = _U1CON_PPBRST_MASK;
+#else
+  U1CONbits.PPBRST = 0;
+#endif
   dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
 }
 
@@ -399,9 +454,15 @@ static void process_bus_sleep(uint8_t rhport)
 static void process_bus_resume(uint8_t rhport)
 {
   // Enable suspend & disable resume interrupt
+#if TU_PIC_INT_SIZE == 4
   U1PWRCCLR = _U1PWRC_USUSPEND_MASK;
   U1IECLR = _U1IE_RESUMEIE_MASK;
   U1IESET = _U1IE_IDLEIE_MASK;
+#else
+  U1PWRCbits.USUSPND = 0;
+  U1IEbits.RESUMEIE = 0;
+  U1IEbits.IDLEIE = 1;
+#endif
 
   dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
 }
@@ -418,26 +479,29 @@ void dcd_init(uint8_t rhport)
   TRISBbits.TRISB6 = 1;
 #endif
 
-#if (CFG_TUSB_MCU == OPT_MCU_PIC32MX) || (CFG_TUSB_MCU == OPT_MCU_PIC32MM)
-  U1PWRCSET = _U1PWRC_USBPWR_MASK;
-#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK
-  // TODO
-#elif (CFG_TUSB_MCU == OPT_MCU_PIC24) || (CFG_TUSB_MCU == OPT_MCU_DSPIC33)
-  U1PWRCbits.USBPWR = 1;
-#endif
-
   tu_memclr(&_dcd, sizeof(_dcd));
 
+#if TU_PIC_INT_SIZE == 4
+  U1PWRCSET = _U1PWRC_USBPWR_MASK;
+#else
+  U1PWRCbits.USBPWR = 1;
+#endif
+  
+#if TU_PIC_INT_SIZE == 4
   uint32_t bdt_phys = KVA_TO_PA((uintptr_t)_dcd.bdt);
 
   U1BDTP1 = (uint8_t)(bdt_phys >>  8);
   U1BDTP2 = (uint8_t)(bdt_phys >> 16);
   U1BDTP3 = (uint8_t)(bdt_phys >> 24);
+#else
+  U1BDTP1 = (uint8_t)((uint16_t)(void *)_dcd.bdt >> 8);
 
-  U1IE = _U1IE_URSTIE_DETACHIE_MASK;
+  U1CNFG1bits.PPB = 2;
+#endif
+
+  U1IE = _U1IE_URSTIE_MASK;
 
   dcd_connect(rhport);
-
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -459,18 +523,30 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 
 void dcd_remote_wakeup(uint8_t rhport)
 {
+#if TU_PIC_INT_SIZE == 4
   U1CONSET = _U1CON_RESUME_MASK;
-
+#else
+  U1CONbits.RESUME = 1;
+#endif
   unsigned cnt = 25000000 / 1000;
   while (cnt--) asm volatile("nop");
 
+#if TU_PIC_INT_SIZE == 4
   U1CONCLR = _U1CON_RESUME_MASK;
+#else
+  U1CONbits.RESUME = 0;
+#endif
 }
 
 void dcd_connect(uint8_t rhport)
 {
-  while (!U1CONbits.USBEN)
+  while (!U1CONbits.USBEN) {
+#if TU_PIC_INT_SIZE == 4
     U1CONSET = _U1CON_USBEN_SOFEN_MASK;
+#else
+    U1CONbits.USBEN = 1;
+#endif
+  }
 }
 
 void dcd_disconnect(uint8_t rhport)
@@ -502,14 +578,14 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   ep->max_packet_size = tu_edpt_packet_size(ep_desc);
 
+
   unsigned val = _U1EP0_EPCONDIS_MASK;
   val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? _U1EP0_EPHSHK_MASK : 0;
   val |= dir ? _U1EP0_EPTXEN_MASK : _U1EP0_EPRXEN_MASK;
 
-  volatile void *ep_reg_base = &U1EP0;
-  volatile uint32_t *reg_ep = (ep_reg_base + 0x10 * epn);
-
-  *reg_ep |= val;
+  ep_reg_t tmp = ep_read(rhport, epn);
+  tmp |= val;
+  ep_write(rhport, epn, tmp);
 
   if (xfer != TUSB_XFER_ISOCHRONOUS) {
     bd[odd].dts      = 1;
@@ -569,6 +645,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
+
   const unsigned epn      = tu_edpt_number(ep_addr);
   const unsigned dir      = tu_edpt_dir(ep_addr);
   endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
@@ -593,7 +670,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
   }
   bd->bc   = total_bytes >= mps ? mps: total_bytes;
   bd->addr = (uint8_t *)KVA_TO_PA(buffer);
-//  __DSB();
   bd->own  = 1; /* This bit must be set last */
 
   if (ie) intr_enable(rhport);
@@ -673,7 +749,7 @@ void dcd_int_handler(uint8_t rhport)
     U1IR   = is; /* discard any pending events */
   }
 
-  if (is & _U1IR_URSTIF_DETACHIF_MASK) {
+  if (is & _U1IR_URSTIF_MASK) {
     U1IR = is; /* discard any pending events */
     process_bus_reset(rhport);
   }
@@ -705,7 +781,6 @@ void dcd_int_handler(uint8_t rhport)
   }
 
   intr_clear(rhport);
-
 }
 
 #endif

From 3499aa2b2113f0098afff9eb2efd6dda78426a1b Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Thu, 6 Oct 2022 21:10:27 +0900
Subject: [PATCH 1174/2085] Fix pointer

---
 examples/device/video_capture/src/main.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 362b168d4..60c58b853 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -110,7 +110,7 @@ static unsigned tx_busy = 0;
 static unsigned interval_ms = 1000 / FRAME_RATE;
 
 /* YUY2 frame buffer */
-#if 1
+#ifdef CFG_EXAMPLE_VIDEO_READONLY
 #include "images.h"
 static struct {
   uint32_t       size;
@@ -181,7 +181,7 @@ void video_task(void)
     already_sent = 1;
     start_ms = board_millis();
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-    tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frames[frame_num % 8].buffer, frames[frame_num % 8].size);
+    tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size);
 #else
     fill_color_bar(frame_buffer, frame_num);
     tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
@@ -194,7 +194,7 @@ void video_task(void)
   start_ms += interval_ms;
 
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
-  tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frames[frame_num % 8].buffer, frames[frame_num % 8].size);
+  tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size);
 #else
   fill_color_bar(frame_buffer, frame_num);
   tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);

From 4be7ffd63f972e241325355d239c44e472dc56dc Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Fri, 7 Oct 2022 21:30:03 +0900
Subject: [PATCH 1175/2085] Fix max payload size to clip at 1023

---
 src/class/video/video_device.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 690e64658..a96bee617 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -419,6 +419,8 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   uint_fast32_t interval_ms = interval / 10000;
   TU_ASSERT(interval_ms);
   uint_fast32_t payload_size = (frame_size + interval_ms - 1) / interval_ms + 2;
+  if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size)
+    payload_size = CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE;
   param->dwMaxPayloadTransferSize = payload_size;
   return true;
 }
@@ -478,10 +480,10 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
         break;
       default: return false;
     }
-    param->bFrameIndex = (uint8_t) frmnum;
+    param->bFrameIndex = (uint8_t)frmnum;
     /* Set the parameters determined by the frame */
     tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
-    param->dwMaxVideoFrameSize = (uint32_t) (frm->wWidth * frm->wHeight * fmt->bBitsPerPixel / 8);
+    param->dwMaxVideoFrameSize = (uint32_t)(frm->wWidth * frm->wHeight * fmt->bBitsPerPixel / 8);
     return true;
   }
 
@@ -536,11 +538,15 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
       param->dwMaxPayloadTransferSize = 0;
     } else {
       uint_fast32_t frame_size = param->dwMaxVideoFrameSize;
+      uint_fast32_t payload_size;
       if (!interval_ms) {
-        param->dwMaxPayloadTransferSize = frame_size + 2;
+        payload_size = frame_size + 2;
       } else {
-        param->dwMaxPayloadTransferSize = (frame_size + interval_ms - 1) / interval_ms + 2;
+        payload_size = (frame_size + interval_ms - 1) / interval_ms + 2;
       }
+      if (CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE < payload_size)
+        payload_size = CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE;
+      param->dwMaxPayloadTransferSize = payload_size;
     }
     return true;
   }

From aed8051f50dfb72187ba3c9a496d6ad2a57da9f8 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 8 Oct 2022 21:53:32 +0900
Subject: [PATCH 1176/2085] Add motion jpeg

---
 examples/device/video_capture/CMakeLists.txt  |  6 ++
 examples/device/video_capture/Makefile        |  7 +++
 examples/device/video_capture/src/images.h    |  3 +
 examples/device/video_capture/src/main.c      | 14 +++++
 .../video_capture/src/usb_descriptors.c       | 10 ++++
 .../video_capture/src/usb_descriptors.h       | 57 ++++++++++++++++++-
 6 files changed, 96 insertions(+), 1 deletion(-)

diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt
index cb321f9a8..b92a2b804 100644
--- a/examples/device/video_capture/CMakeLists.txt
+++ b/examples/device/video_capture/CMakeLists.txt
@@ -12,6 +12,12 @@ family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
 add_executable(${PROJECT})
 
+if (FORCE_READONLY)
+target_compile_definitions(${PROJECT} PRIVATE
+  CFG_EXAMPLE_VIDEO_READONLY
+)
+endif()
+
 # Example source
 target_sources(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
diff --git a/examples/device/video_capture/Makefile b/examples/device/video_capture/Makefile
index 69b633fea..b06681538 100644
--- a/examples/device/video_capture/Makefile
+++ b/examples/device/video_capture/Makefile
@@ -1,6 +1,13 @@
 include ../../../tools/top.mk
 include ../../make.mk
 
+ifeq ($(DISABLE_MJPG),1)
+CFLAGS += -DCFG_EXAMPLE_VIDEO_DISABLE_MJPG
+endif
+ifeq ($(FORCE_READONLY),1)
+CFLAGS += -DCFG_EXAMPLE_VIDEO_READONLY
+endif
+
 INC += \
 	src \
 	$(TOP)/hw \
diff --git a/examples/device/video_capture/src/images.h b/examples/device/video_capture/src/images.h
index 33beff662..0398428b3 100644
--- a/examples/device/video_capture/src/images.h
+++ b/examples/device/video_capture/src/images.h
@@ -1,3 +1,4 @@
+#if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
 static const unsigned char frame_buffer[128 * (96 + 1) * 2] = {
   /* 0 */
   0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80, 0xeb, 0x80,
@@ -1649,6 +1650,7 @@ static const unsigned char frame_buffer[128 * (96 + 1) * 2] = {
   0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
   0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80, 0x10, 0x80,
 };
+#else
 
 #define color_bar_0_jpg_len  511
 #define color_bar_1_jpg_len  512
@@ -1931,3 +1933,4 @@ unsigned char color_bar_7_jpg[] = {
   0x42, 0x51, 0x59, 0x8c, 0xb1, 0x45, 0x00, 0x25, 0x15, 0x98, 0xc4, 0xa2, 0xb5, 0x32, 0x12, 0x8a,
   0xcc, 0x63, 0x68, 0xad, 0x8d, 0x84, 0xa2, 0xb3, 0x18, 0x94, 0x56, 0xa6, 0x47, 0xff, 0xd9
 };
+#endif
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 60c58b853..3ceebe821 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -112,6 +112,8 @@ static unsigned interval_ms = 1000 / FRAME_RATE;
 /* YUY2 frame buffer */
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
 #include "images.h"
+
+# if !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
 static struct {
   uint32_t       size;
   uint8_t const *buffer;
@@ -125,6 +127,8 @@ static struct {
   {color_bar_6_jpg_len, color_bar_6_jpg},
   {color_bar_7_jpg_len, color_bar_7_jpg},
 };
+# endif
+
 #else
 static uint8_t frame_buffer[FRAME_WIDTH * FRAME_HEIGHT * 16 / 8];
 static void fill_color_bar(uint8_t *buffer, unsigned start_position)
@@ -181,7 +185,12 @@ void video_task(void)
     already_sent = 1;
     start_ms = board_millis();
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
+# if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
+    tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
+                           FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+# else
     tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size);
+# endif
 #else
     fill_color_bar(frame_buffer, frame_num);
     tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
@@ -194,7 +203,12 @@ void video_task(void)
   start_ms += interval_ms;
 
 #ifdef CFG_EXAMPLE_VIDEO_READONLY
+# if defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
+  tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)&frame_buffer[(frame_num % (FRAME_WIDTH / 2)) * 4],
+                         FRAME_WIDTH * FRAME_HEIGHT * 16/8);
+# else
   tud_video_n_frame_xfer(0, 0, (void*)(uintptr_t)frames[frame_num % 8].buffer, frames[frame_num % 8].size);
+# endif
 #else
   fill_color_bar(frame_buffer, frame_num);
   tud_video_n_frame_xfer(0, 0, (void*)frame_buffer, FRAME_WIDTH * FRAME_HEIGHT * 16/8);
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 5c97f4fe1..4c63ab924 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -75,7 +75,11 @@ uint8_t const * tud_descriptor_device_cb(void)
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
+#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPG_LEN)
+#else
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_LEN)
+#endif
 
 #if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
@@ -96,9 +100,15 @@ uint8_t const desc_fs_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
   // IAD for Video Control
+#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
+  TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPG(4, EPNUM_VIDEO_IN,
+                               FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
+                               CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
+#else
   TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN,
                                FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
                                CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
+#endif
 };
 
 // Invoked when received GET CONFIGURATION DESCRIPTOR
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 10bae4750..631e638c9 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -44,6 +44,24 @@ enum {
 };
 
 #define TUD_VIDEO_CAPTURE_DESC_LEN (\
+    TUD_VIDEO_DESC_IAD_LEN\
+    /* control */\
+    + TUD_VIDEO_DESC_STD_VC_LEN\
+    + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+    + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+    + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+    + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+    /* Interface 1, Alternate 1 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + 7/* Endpoint */\
+  )
+
+#define TUD_VIDEO_CAPTURE_DESC_MJPG_LEN (\
     TUD_VIDEO_DESC_IAD_LEN\
     /* control */\
     + TUD_VIDEO_DESC_STD_VC_LEN\
@@ -74,6 +92,43 @@ enum {
   TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_I420, 12, _frmidx, _asrx, _asry, _interlace, _cp)
 
 #define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps, _epsize) \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+  /* Video control 0 */ \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
+    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
+         /* wTotalLength - bLength */ \
+         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
+         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
+                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
+                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+  /* Video stream alt. 0 */ \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 0, _stridx), \
+    /* Video stream header for without still image capture */ \
+    TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+        /*wTotalLength - bLength */\
+        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+        + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+        /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+        /*bmaControls(1)*/0), \
+      /* Video stream format */ \
+      TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /* Video stream frame format */ \
+        TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
+            _width * _height * 16, _width * _height * 16 * _fps, \
+            _width * _height * 16, \
+            (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+  /* VS alt 1 */\
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 1, 1, _stridx), \
+    /* EP */ \
+    TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPG(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
   TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
@@ -102,7 +157,7 @@ enum {
         /* Video stream frame format */ \
         TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT(/*bFrameIndex */1, 0, _width, _height, \
             _width * _height * 16, _width * _height * 16 * _fps, \
-            _width * _height * 16, \
+            _width * _height * 16 / 8, \
             (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
         TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
   /* VS alt 1 */\

From 8a89365bb2b83f9d84e2308e7809ac7d6f94b4a1 Mon Sep 17 00:00:00 2001
From: LynnL4 <lht856@foxmail.com>
Date: Tue, 11 Oct 2022 13:50:07 +0800
Subject: [PATCH 1177/2085] Add stm32u5xx offical driver.

---
 .gitmodules                    | 6 ++++++
 hw/mcu/st/cmsis_device_u5      | 1 +
 hw/mcu/st/stm32u5xx_hal_driver | 1 +
 3 files changed, 8 insertions(+)
 create mode 160000 hw/mcu/st/cmsis_device_u5
 create mode 160000 hw/mcu/st/stm32u5xx_hal_driver

diff --git a/.gitmodules b/.gitmodules
index 044ac24ec..aafb0f520 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -149,3 +149,9 @@
 [submodule "hw/mcu/raspberry_pi/Pico-PIO-USB"]
 	path = hw/mcu/raspberry_pi/Pico-PIO-USB
 	url = https://github.com/sekigon-gonnoc/Pico-PIO-USB.git
+[submodule "/home/ubuntu/tinyusb/hw/mcu/st/cmsis_device_u5"]
+	path = /home/ubuntu/tinyusb/hw/mcu/st/cmsis_device_u5
+	url = https://github.com/STMicroelectronics/cmsis_device_u5
+[submodule "/home/ubuntu/tinyusb/hw/mcu/st/stm32u5xx_hal_driver"]
+	path = /home/ubuntu/tinyusb/hw/mcu/st/stm32u5xx_hal_driver
+	url = https://github.com/STMicroelectronics/stm32u5xx_hal_driver
diff --git a/hw/mcu/st/cmsis_device_u5 b/hw/mcu/st/cmsis_device_u5
new file mode 160000
index 000000000..bc00f3c9d
--- /dev/null
+++ b/hw/mcu/st/cmsis_device_u5
@@ -0,0 +1 @@
+Subproject commit bc00f3c9d8a4e25220f84c26d414902cc6bdf566
diff --git a/hw/mcu/st/stm32u5xx_hal_driver b/hw/mcu/st/stm32u5xx_hal_driver
new file mode 160000
index 000000000..2e1d4cdb3
--- /dev/null
+++ b/hw/mcu/st/stm32u5xx_hal_driver
@@ -0,0 +1 @@
+Subproject commit 2e1d4cdb386e33391cb261dfff4fefa92e4aa35a

From 16f1554a03a89c51cd033b6a06cb758668f32fda Mon Sep 17 00:00:00 2001
From: tswan-quasi <tucker.swan@10xar.com>
Date: Tue, 11 Oct 2022 09:59:28 -0400
Subject: [PATCH 1178/2085] lpc55s69 isochronous, dummy address for endpoint
 buffers to prevent accidental writes

---
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 96 ++++++++++++--------
 1 file changed, 59 insertions(+), 37 deletions(-)

diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 09ebf3b0d..b0ddebad0 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -78,8 +78,9 @@ typedef struct {
 
 // Max nbytes for each control/bulk/interrupt transfer
 enum {
-  NBYTES_CBI_FULLSPEED_MAX = 64,
-  NBYTES_CBI_HIGHSPEED_MAX = 32767 // can be up to all 15-bit, but only tested with 4096
+  NBYTES_CBI_FS_ISO_MAX = 1023, // FS ISO
+  NBYTES_CBI_FS_MAX = 64, // FS control/bulk/interrupt
+  NBYTES_CBI_HS_MAX = 32767 // can be up to all 15-bit, but only tested with 4096
 };
 
 enum {
@@ -174,6 +175,7 @@ typedef struct
 //    For example: LPC55s69 port1 Highspeed must be USB_RAM (0x40100000)
 //    Use CFG_TUSB_MEM_SECTION to place it accordingly.
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static volatile uint8_t dummy[64]; // TODO temp fix to prevent accidental overwrite due to ep[][].buffer_xx.offset being 0
 
 //--------------------------------------------------------------------+
 // Multiple Controllers
@@ -225,8 +227,44 @@ static inline uint8_t ep_addr2id(uint8_t ep_addr)
 //--------------------------------------------------------------------+
 // CONTROLLER API
 //--------------------------------------------------------------------+
+
+static void prepare_setup_packet(uint8_t rhport)
+{
+  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
+  {
+    _dcd.ep[0][1].buffer_fs.offset = get_buf_offset(_dcd.setup_packet);
+  }else
+  {
+    _dcd.ep[0][1].buffer_hs.offset = get_buf_offset(_dcd.setup_packet);
+  }
+}
+
+static void edpt_reset(uint8_t rhport, uint8_t ep_id)
+{
+  const uint32_t offset = get_buf_offset((void*)dummy);
+  tu_memclr(&_dcd.ep[ep_id], sizeof(_dcd.ep[ep_id]));
+  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
+  {
+    _dcd.ep[ep_id][0].buffer_fs.offset = _dcd.ep[ep_id][1].buffer_fs.offset = offset;
+  }
+  else
+  {
+    _dcd.ep[ep_id][0].buffer_hs.offset = _dcd.ep[ep_id][1].buffer_hs.offset = offset;
+  }
+}
+
+static void edpt_reset_all(uint8_t rhport)
+{
+  for (uint8_t ep_id = 0; ep_id < 2*_dcd_controller[rhport].ep_pairs; ++ep_id)
+  {
+    edpt_reset(rhport, ep_id);
+  }
+  prepare_setup_packet(rhport);
+}
 void dcd_init(uint8_t rhport)
 {
+  edpt_reset_all(rhport);
+
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
 
   dcd_reg->EPLISTSTART  = (uint32_t) _dcd.ep;
@@ -310,18 +348,13 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
-  (void) rhport;
-
-  // TODO not support ISO yet
-  TU_VERIFY(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
-
   //------------- Prepare Queue Head -------------//
   uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
 
   // Check if endpoint is available
   TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable );
 
-  tu_memclr(_dcd.ep[ep_id], 2*sizeof(ep_cmd_sts_t));
+  edpt_reset(rhport, ep_id);
   _dcd.ep[ep_id][0].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
 
   // Enable EP interrupt
@@ -333,19 +366,18 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 
 void dcd_edpt_close_all (uint8_t rhport)
 {
-  (void) rhport;
-  // TODO implement dcd_edpt_close_all()
+  for (uint8_t ep_id = 0; ep_id < 2*_dcd_controller[rhport].ep_pairs; ++ep_id)
+  {
+    _dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
+    _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
+  }
 }
 
-static void prepare_setup_packet(uint8_t rhport)
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
-  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
-  {
-    _dcd.ep[0][1].buffer_fs.offset = get_buf_offset(_dcd.setup_packet);;
-  }else
-  {
-    _dcd.ep[0][1].buffer_hs.offset = get_buf_offset(_dcd.setup_packet);;
-  }
+  uint8_t ep_id = ep_addr2id(ep_addr);
+  _dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
+  _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
 }
 
 static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
@@ -354,13 +386,12 @@ static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset,
 
   if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
   {
-    // TODO ISO FullSpeed can have up to 1023 bytes
-    nbytes = tu_min16(total_bytes, NBYTES_CBI_FULLSPEED_MAX);
+    nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].is_iso ? NBYTES_CBI_FS_ISO_MAX : NBYTES_CBI_FS_MAX);
     _dcd.ep[ep_id][0].buffer_fs.offset = buf_offset;
     _dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes;
   }else
   {
-    nbytes = tu_min16(total_bytes, NBYTES_CBI_HIGHSPEED_MAX);
+    nbytes = tu_min16(total_bytes, NBYTES_CBI_HS_MAX);
     _dcd.ep[ep_id][0].buffer_hs.offset = buf_offset;
     _dcd.ep[ep_id][0].buffer_hs.nbytes = nbytes;
   }
@@ -379,7 +410,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
   tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t));
   _dcd.dma[ep_id].total_bytes = total_bytes;
 
-  prepare_ep_xfer(rhport, ep_id, get_buf_offset(buffer), total_bytes);
+  prepare_ep_xfer(rhport, ep_id, buffer ? get_buf_offset(buffer) : get_buf_offset((void*)dummy), total_bytes);
 
   return true;
 }
@@ -390,6 +421,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 static void bus_reset(uint8_t rhport)
 {
   tu_memclr(&_dcd, sizeof(dcd_data_t));
+  edpt_reset_all(rhport); 
 
   // disable all non-control endpoints on bus reset
   for(uint8_t ep_id = 2; ep_id < 2*MAX_EP_PAIRS; ep_id++)
@@ -397,8 +429,6 @@ static void bus_reset(uint8_t rhport)
     _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
   }
 
-  prepare_setup_packet(rhport);
-
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
 
   dcd_reg->EPINUSE      = 0;
@@ -506,23 +536,15 @@ void dcd_int_handler(uint8_t rhport)
       }
     }
 
-    // TODO support suspend & resume
     if (cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
     {
-      if (cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK)
-      { // suspend signal, bus idle for more than 3ms
-        // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-        if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
-        {
-          dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-        }
+      // suspend signal, bus idle for more than 3ms
+      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
+      if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      {
+        dcd_event_bus_signal(rhport, (cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true);
       }
     }
-//        else
-//      { // resume signal
-//    dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-//      }
-//    }
   }
 
   // Setup Receive

From 2c9b5ddff096b6c734346099b5cd4162db8735c9 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 12 Oct 2022 20:07:22 +0900
Subject: [PATCH 1179/2085] Rename descriptor macros for consistency

---
 examples/device/video_capture/Makefile        |  4 ++--
 .../video_capture/src/usb_descriptors.c       | 20 +++++++++----------
 .../video_capture/src/usb_descriptors.h       |  8 ++++----
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/examples/device/video_capture/Makefile b/examples/device/video_capture/Makefile
index b06681538..fda66bcc1 100644
--- a/examples/device/video_capture/Makefile
+++ b/examples/device/video_capture/Makefile
@@ -1,8 +1,8 @@
 include ../../../tools/top.mk
 include ../../make.mk
 
-ifeq ($(DISABLE_MJPG),1)
-CFLAGS += -DCFG_EXAMPLE_VIDEO_DISABLE_MJPG
+ifeq ($(DISABLE_MJPEG),1)
+CFLAGS += -DCFG_EXAMPLE_VIDEO_DISABLE_MJPEG
 endif
 ifeq ($(FORCE_READONLY),1)
 CFLAGS += -DCFG_EXAMPLE_VIDEO_READONLY
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 4c63ab924..499ee311c 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -75,10 +75,10 @@ uint8_t const * tud_descriptor_device_cb(void)
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
-#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPG_LEN)
+#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_LEN)
 #else
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_LEN)
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN)
 #endif
 
 #if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
@@ -100,14 +100,14 @@ uint8_t const desc_fs_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
   // IAD for Video Control
-#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPG)
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPG(4, EPNUM_VIDEO_IN,
-                               FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                               CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
+#if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+  TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(4, EPNUM_VIDEO_IN,
+                                     FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
+                                     CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
 #else
-  TUD_VIDEO_CAPTURE_DESCRIPTOR(4, EPNUM_VIDEO_IN,
-                               FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                               CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
+  TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(4, EPNUM_VIDEO_IN,
+                                       FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
+                                       CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
 #endif
 };
 
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 631e638c9..f1ed3c8e9 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -43,7 +43,7 @@ enum {
   ITF_NUM_TOTAL
 };
 
-#define TUD_VIDEO_CAPTURE_DESC_LEN (\
+#define TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN (\
     TUD_VIDEO_DESC_IAD_LEN\
     /* control */\
     + TUD_VIDEO_DESC_STD_VC_LEN\
@@ -61,7 +61,7 @@ enum {
     + 7/* Endpoint */\
   )
 
-#define TUD_VIDEO_CAPTURE_DESC_MJPG_LEN (\
+#define TUD_VIDEO_CAPTURE_DESC_MJPEG_LEN (\
     TUD_VIDEO_DESC_IAD_LEN\
     /* control */\
     + TUD_VIDEO_DESC_STD_VC_LEN\
@@ -91,7 +91,7 @@ enum {
 #define TUD_VIDEO_DESC_CS_VS_FMT_I420(_fmtidx, _numfmtdesc, _frmidx, _asrx, _asry, _interlace, _cp) \
   TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR(_fmtidx, _numfmtdesc, TUD_VIDEO_GUID_I420, 12, _frmidx, _asrx, _asry, _interlace, _cp)
 
-#define TUD_VIDEO_CAPTURE_DESCRIPTOR(_stridx, _epin, _width, _height, _fps, _epsize) \
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
   TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
@@ -128,7 +128,7 @@ enum {
     /* EP */ \
     TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
 
-#define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPG(_stridx, _epin, _width, _height, _fps, _epsize) \
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(_stridx, _epin, _width, _height, _fps, _epsize) \
   TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
   /* Video control 0 */ \
   TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \

From 53dc9d55b57faa3199711fe82b47195d0369c1d8 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Wed, 12 Oct 2022 20:41:03 +0900
Subject: [PATCH 1180/2085] Fix pointer type to calculate streaming parameter

---
 src/class/video/video_device.c | 63 ++++++++++++++++++++++------------
 1 file changed, 42 insertions(+), 21 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index a96bee617..a6d2724c1 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -74,10 +74,13 @@ typedef union {
 
 typedef union {
   struct TU_ATTR_PACKED {
-    uint8_t bLength;
-    uint8_t bDescriptorType;
-    uint8_t bDescriptorSubType;
-    uint8_t bFrameIndex;
+    uint8_t  bLength;
+    uint8_t  bDescriptorType;
+    uint8_t  bDescriptorSubType;
+    uint8_t  bFrameIndex;
+    uint8_t  bmCapabilities;
+    uint16_t wWidth;
+    uint16_t wHeight;
   };
   tusb_desc_cs_video_frm_uncompressed_t uncompressed;
   tusb_desc_cs_video_frm_mjpeg_t        mjpeg;
@@ -396,10 +399,10 @@ static bool _update_streaming_parameters(videod_streaming_interface_t const *stm
   if (!frame_size) {
     switch (fmt->bDescriptorSubType) {
       case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
-        frame_size = (uint_fast32_t)frm->uncompressed.wWidth * frm->uncompressed.wHeight * fmt->uncompressed.bBitsPerPixel / 8;
+        frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->uncompressed.bBitsPerPixel / 8;
         break;
       case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
-        frame_size = (uint_fast32_t)frm->mjpeg.wWidth * frm->mjpeg.wHeight * 16 / 8; /* YUV422 */
+        frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * 16 / 8; /* YUV422 */
         break;
       default: break;
     }
@@ -467,7 +470,7 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
     tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
     TU_ASSERT(vs);
     void const *end = _end_of_streaming_descriptor(vs);
-    tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
+    tusb_desc_cs_video_fmt_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
     switch (request) {
       case VIDEO_REQUEST_GET_MAX:
         frmnum = fmt->bNumFrameDescriptors;
@@ -476,14 +479,32 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
         frmnum = 1;
         break;
       case VIDEO_REQUEST_GET_DEF:
-        frmnum = fmt->bDefaultFrameIndex;
+        switch (fmt->bDescriptorSubType) {
+        case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
+          frmnum = fmt->uncompressed.bDefaultFrameIndex;
+          break;
+        case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
+          frmnum = fmt->mjpeg.bDefaultFrameIndex;
+          break;
+        default: return false;
+        }
         break;
       default: return false;
     }
     param->bFrameIndex = (uint8_t)frmnum;
     /* Set the parameters determined by the frame */
-    tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
-    param->dwMaxVideoFrameSize = (uint32_t)(frm->wWidth * frm->wHeight * fmt->bBitsPerPixel / 8);
+    tusb_desc_cs_video_frm_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
+    uint_fast32_t frame_size;
+    switch (fmt->bDescriptorSubType) {
+      case VIDEO_CS_ITF_VS_FORMAT_UNCOMPRESSED:
+        frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * fmt->uncompressed.bBitsPerPixel / 8;
+        break;
+      case VIDEO_CS_ITF_VS_FORMAT_MJPEG:
+        frame_size = (uint_fast32_t)frm->wWidth * frm->wHeight * 16 / 8; /* YUV422 */
+        break;
+      default: return false;
+    }
+    param->dwMaxVideoFrameSize = frame_size;
     return true;
   }
 
@@ -491,17 +512,17 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
     tusb_desc_vs_itf_t const *vs = _get_desc_vs(stm);
     TU_ASSERT(vs);
     void const *end = _end_of_streaming_descriptor(vs);
-    tusb_desc_cs_video_fmt_uncompressed_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
-    tusb_desc_cs_video_frm_uncompressed_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
+    tusb_desc_cs_video_fmt_t const *fmt = _find_desc_format(tu_desc_next(vs), end, fmtnum);
+    tusb_desc_cs_video_frm_t const *frm = _find_desc_frame(tu_desc_next(fmt), end, frmnum);
 
     uint_fast32_t interval, interval_ms;
     switch (request) {
       case VIDEO_REQUEST_GET_MAX:
         {
           uint_fast32_t min_interval, max_interval;
-          uint_fast8_t num_intervals = frm->bFrameIntervalType;
-          max_interval = num_intervals ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[1];
-          min_interval = frm->dwFrameInterval[0];
+          uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
+          max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1];
+          min_interval = frm->uncompressed.dwFrameInterval[0];
           interval = max_interval;
           interval_ms = min_interval / 10000;
         }
@@ -509,24 +530,24 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
       case VIDEO_REQUEST_GET_MIN:
         {
           uint_fast32_t min_interval, max_interval;
-          uint_fast8_t num_intervals = frm->bFrameIntervalType;
-          max_interval = num_intervals ? frm->dwFrameInterval[num_intervals - 1]: frm->dwFrameInterval[1];
-          min_interval = frm->dwFrameInterval[0];
+          uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
+          max_interval = num_intervals ? frm->uncompressed.dwFrameInterval[num_intervals - 1]: frm->uncompressed.dwFrameInterval[1];
+          min_interval = frm->uncompressed.dwFrameInterval[0];
           interval = min_interval;
           interval_ms = max_interval / 10000;
         }
         break;
       case VIDEO_REQUEST_GET_DEF:
-        interval = frm->dwDefaultFrameInterval;
+        interval = frm->uncompressed.dwDefaultFrameInterval;
         interval_ms = interval / 10000;
         break;
       case VIDEO_REQUEST_GET_RES:
         {
-          uint_fast8_t num_intervals = frm->bFrameIntervalType;
+          uint_fast8_t num_intervals = frm->uncompressed.bFrameIntervalType;
           if (num_intervals) {
             interval = 0;
           } else {
-            interval = frm->dwFrameInterval[2];
+            interval = frm->uncompressed.dwFrameInterval[2];
             interval_ms = interval / 10000;
           }
         }

From 930c68278c3825bce91ef324090d25c392844558 Mon Sep 17 00:00:00 2001
From: tswan-quasi <tucker.swan@10xar.com>
Date: Wed, 12 Oct 2022 11:16:35 -0400
Subject: [PATCH 1181/2085] double cast of pointer to remove error

---
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index b0ddebad0..7220654e0 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -241,7 +241,7 @@ static void prepare_setup_packet(uint8_t rhport)
 
 static void edpt_reset(uint8_t rhport, uint8_t ep_id)
 {
-  const uint32_t offset = get_buf_offset((void*)dummy);
+  const uint32_t offset = get_buf_offset((void*)(uint32_t)dummy);
   tu_memclr(&_dcd.ep[ep_id], sizeof(_dcd.ep[ep_id]));
   if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
   {
@@ -410,7 +410,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
   tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t));
   _dcd.dma[ep_id].total_bytes = total_bytes;
 
-  prepare_ep_xfer(rhport, ep_id, buffer ? get_buf_offset(buffer) : get_buf_offset((void*)dummy), total_bytes);
+  prepare_ep_xfer(rhport, ep_id, buffer ? get_buf_offset(buffer) : get_buf_offset((void*)(uint32_t)dummy), total_bytes);
 
   return true;
 }

From 4238467b2d78fcb11ba63026daa525d1c09e17ac Mon Sep 17 00:00:00 2001
From: LynnL4 <lht856@foxmail.com>
Date: Thu, 13 Oct 2022 17:37:28 +0800
Subject: [PATCH 1182/2085] Add support for STM32U5 mcu

---
 hw/bsp/board_mcu.h                            |   3 +
 .../stm32u575eval/STM32U575AIIXQ_FLASH.ld     | 167 ++++++
 hw/bsp/stm32u5/boards/stm32u575eval/board.h   | 112 ++++
 hw/bsp/stm32u5/boards/stm32u575eval/board.mk  |  10 +
 hw/bsp/stm32u5/family.c                       | 200 +++++++
 hw/bsp/stm32u5/family.mk                      |  45 ++
 hw/bsp/stm32u5/stm32u5xx_hal_conf.h           | 506 ++++++++++++++++++
 src/common/tusb_mcu.h                         |   5 +
 src/portable/synopsys/dwc2/dwc2_stm32.h       |   6 +
 src/tusb_option.h                             |   1 +
 10 files changed, 1055 insertions(+)
 create mode 100644 hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld
 create mode 100644 hw/bsp/stm32u5/boards/stm32u575eval/board.h
 create mode 100644 hw/bsp/stm32u5/boards/stm32u575eval/board.mk
 create mode 100644 hw/bsp/stm32u5/family.c
 create mode 100644 hw/bsp/stm32u5/family.mk
 create mode 100644 hw/bsp/stm32u5/stm32u5xx_hal_conf.h

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 5c309a21d..18f071a22 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -98,6 +98,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   #include "stm32wbxx.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
+  #include "stm32u5xx.h"
+
 #elif CFG_TUSB_MCU == OPT_MCU_CXD56
   // no header needed
 
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld b/hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld
new file mode 100644
index 000000000..03c022bc2
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld
@@ -0,0 +1,167 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U575xI Device from STM32U5 series
+**                      2048Kbytes FLASH
+**                      784Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 768K
+  SRAM4	(xrw)	: ORIGIN = 0x28000000,	LENGTH = 16K
+  FLASH	(rx)	: ORIGIN = 0x08000000,	LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.h b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
new file mode 100644
index 000000000..5c348b812
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
@@ -0,0 +1,112 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Hongtai Liu <lht856@foxmail.com>
+ * Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// LED GREEN
+#define LED_PORT GPIOB
+#define LED_PIN GPIO_PIN_7
+#define LED_STATE_ON 1
+
+// // LED
+#define BUTTON_PORT GPIOC
+#define BUTTON_PIN GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for STLink VCOM
+#define UART_DEV USART1
+#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
+#define UART_GPIO_PORT GPIOA
+#define UART_GPIO_AF GPIO_AF7_USART1
+#define UART_TX_PIN GPIO_PIN_9
+#define UART_RX_PIN GPIO_PIN_10
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+static inline void board_clock_init(void)
+{
+
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /* Enable Power Clock*/
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /** Configure the main internal regulator output voltage
+   */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the CPU, AHB and APB busses clocks
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 10;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 1;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+  PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
+
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+  /** Initializes the CPU, AHB and APB busses clocks
+   */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
new file mode 100644
index 000000000..19cd2a5b0
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
@@ -0,0 +1,10 @@
+CFLAGS += \
+  -DSTM32U575xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32U575AIIXQ_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32u575
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
new file mode 100644
index 000000000..9bc94cfa3
--- /dev/null
+++ b/hw/bsp/stm32u5/family.c
@@ -0,0 +1,200 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Hongtai Liu <lht856@foxmail.com>
+ * Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stm32u5xx_hal.h"
+#include "bsp/board.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+UART_HandleTypeDef UartHandle;
+
+void board_init(void)
+{
+
+  board_clock_init();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+
+  UART_CLK_EN();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  GPIO_InitTypeDef GPIO_InitStruct;
+
+  // LED
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+  // IOSV bit MUST be set to access GPIO port G[2:15] */
+  HAL_PWREx_EnableVddIO2();
+
+  // Uart
+  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle.Instance = UART_DEV;
+  UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
+  UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
+  UartHandle.Init.StopBits = UART_STOPBITS_1;
+  UartHandle.Init.Parity = UART_PARITY_NONE;
+  UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  UartHandle.Init.Mode = UART_MODE_TX_RX;
+  UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
+  UartHandle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  UartHandle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+
+  HAL_UART_Init(&UartHandle);
+
+  /* Configure USB FS GPIOs */
+  /* Configure DM DP Pins */
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF10_USB;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* Configure ID pin */
+  GPIO_InitStruct.Pin = GPIO_PIN_10;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Alternate = GPIO_AF10_USB;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+#if OTG_FS_VBUS_SENSE
+  // Configure VBUS Pin
+  GPIO_InitStruct.Pin = GPIO_PIN_9;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  // Enable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
+#else
+  // Disable VBUS sense (B device) via pin PA9
+  USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
+
+  // B-peripheral session valid override enable
+  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
+  USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
+#endif // vbus sense
+
+  /* Enable USB power on Pwrctrl CR2 register */
+  HAL_PWREx_EnableVddUSB();
+
+  /* USB_OTG_FS clock enable */
+  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t *buf, int len)
+{
+  (void)buf;
+  (void)len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+  HAL_UART_Transmit(&UartHandle, (uint8_t *)(uintptr_t)buf, len, 0xffff);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler(void)
+{
+  asm("bkpt");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+}
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
new file mode 100644
index 000000000..1cfb81e43
--- /dev/null
+++ b/hw/bsp/stm32u5/family.mk
@@ -0,0 +1,45 @@
+ST_FAMILY = u5
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m33 \
+  -mfloat-abi=hard \
+  -mfpu=fpv5-sp-d16 \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32U5
+
+# suppress warning caused by vendor mcu driver 
+CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=undef -Wno-error=unused-parameter
+
+#src/portable/st/synopsys/dcd_synopsys.c
+SRC_C += \
+	src/portable/synopsys/dwc2/dcd_dwc2.c \
+	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+
+INC += \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc \
+	$(TOP)/$(BOARD_PATH)
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM33_NTZ/non_secure
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
new file mode 100644
index 000000000..15dffa813
--- /dev/null
+++ b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
@@ -0,0 +1,506 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32u5xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_CONF_H
+#define STM32U5xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+
+#define HAL_MODULE_ENABLED
+
+/*#define HAL_ADC_MODULE_ENABLED */
+/*#define HAL_MDF_MODULE_ENABLED */
+/*#define HAL_COMP_MODULE_ENABLED */
+/*#define HAL_CORDIC_MODULE_ENABLED */
+/*#define HAL_CRC_MODULE_ENABLED */
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_DAC_MODULE_ENABLED */
+/*#define HAL_DMA2D_MODULE_ENABLED */
+/*#define HAL_DSI_MODULE_ENABLED */
+/*#define HAL_FDCAN_MODULE_ENABLED */
+/*#define HAL_FMAC_MODULE_ENABLED */
+/*#define HAL_GFXMMU_MODULE_ENABLED */
+/*#define HAL_GPU2D_MODULE_ENABLED */
+/*#define HAL_GTZC_MODULE_ENABLED */
+/*#define HAL_HASH_MODULE_ENABLED */
+/*#define HAL_HRTIM_MODULE_ENABLED */
+/*#define HAL_IRDA_MODULE_ENABLED */
+/*#define HAL_IWDG_MODULE_ENABLED */
+/*#define HAL_I2C_MODULE_ENABLED */
+/*#define HAL_I2S_MODULE_ENABLED */
+/*#define HAL_LPTIM_MODULE_ENABLED */
+/*#define HAL_LTDC_MODULE_ENABLED */
+/*#define HAL_NAND_MODULE_ENABLED */
+/*#define HAL_NOR_MODULE_ENABLED */
+/*#define HAL_OPAMP_MODULE_ENABLED */
+#define HAL_OSPI_MODULE_ENABLED
+/*#define HAL_OTFDEC_MODULE_ENABLED */
+#define HAL_PCD_MODULE_ENABLED
+/*#define HAL_PKA_MODULE_ENABLED */
+/*#define HAL_QSPI_MODULE_ENABLED */
+/*#define HAL_RNG_MODULE_ENABLED */
+/*#define HAL_RTC_MODULE_ENABLED */
+/*#define HAL_SAI_MODULE_ENABLED */
+/*#define HAL_CRYP_MODULE_ENABLED */
+/*#define HAL_SD_MODULE_ENABLED */
+/*#define HAL_MMC_MODULE_ENABLED */
+/*#define HAL_SMARTCARD_MODULE_ENABLED */
+/*#define HAL_SMBUS_MODULE_ENABLED */
+/*#define HAL_SPI_MODULE_ENABLED */
+/*#define HAL_SRAM_MODULE_ENABLED */
+/*#define HAL_TIM_MODULE_ENABLED */
+/*#define HAL_TSC_MODULE_ENABLED */
+/*#define HAL_RAMCFG_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED */
+/*#define HAL_WWDG_MODULE_ENABLED */
+/*#define HAL_DCMI_MODULE_ENABLED */
+/*#define HAL_PSSI_MODULE_ENABLED */
+#define HAL_ICACHE_MODULE_ENABLED
+/*#define HAL_DCACHE_MODULE_ENABLED */
+#define HAL_PCD_MODULE_ENABLED
+/*#define HAL_HCD_MODULE_ENABLED */
+/*#define HAL_XSPI_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    16000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    100UL   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE              4000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE              16000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+  #define HSI48_VALUE             48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+                                               The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+  #define LSI_VALUE  32000UL     /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
+                                                The real value may vary depending on the variations
+                                                in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE  32768UL    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    5000UL   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for SAI1 peripheral
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
+  #define EXTERNAL_SAI1_CLOCK_VALUE    48000UL /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+
+#define  VDD_VALUE                    3300UL /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (15UL)    /*!< tick interrupt priority (lowest by default)  */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U                    /*!< Enable prefetch */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+  * @brief Set below the peripheral configuration  to "1U" to add the support
+  *        of HAL callback registration/unregistration feature for the HAL
+  *        driver(s). This allows user application to provide specific callback
+  *        functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+  *        the default weak callback functions (see each stm32u5xx_hal_ppp.h file
+  *        for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+  *        for each PPP peripheral).
+  */
+#define  USE_HAL_ADC_REGISTER_CALLBACKS        0U /* ADC register callback disabled       */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS       0U /* COMP register callback disabled      */
+#define  USE_HAL_CORDIC_REGISTER_CALLBACKS     0U /* CORDIC register callback disabled    */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS       0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS        0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS       0U /* DCMI register callback disabled      */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS      0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS        0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS        0U /* ETH register callback disabled       */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS      0U /* FDCAN register callback disabled     */
+#define  USE_HAL_FMAC_REGISTER_CALLBACKS       0U /* FMAC register callback disabled      */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS       0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS        0U /* HCD register callback disabled       */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS     0U /* GFXMMU register callback disabled    */
+#define  USE_HAL_GPU2D_REGISTER_CALLBACKS      0U /* GPU2D register callback disabled     */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS        0U /* I2C register callback disabled       */
+#define  USE_HAL_IWDG_REGISTER_CALLBACKS       0U /* IWDG register callback disabled      */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS       0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS      0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS       0U /* LTDC register callback disabled      */
+#define  USE_HAL_MDF_REGISTER_CALLBACKS        0U /* MDF register callback disabled       */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS        0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS       0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS        0U /* NOR register callback disabled       */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS      0U /* MDIO register callback disabled      */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS     0U /* OTFDEC register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS        0U /* PCD register callback disabled       */
+#define  USE_HAL_PKA_REGISTER_CALLBACKS        0U /* PKA register callback disabled       */
+#define  USE_HAL_RAMCFG_REGISTER_CALLBACKS     0U /* RAMCFG register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS        0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS        0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS        0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS         0U /* SD register callback disabled        */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS      0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS      0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS        0U /* SPI register callback disabled       */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS       0U /* SRAM register callback disabled      */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS        0U /* TIM register callback disabled       */
+#define  USE_HAL_TSC_REGISTER_CALLBACKS        0U /* TSC register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS       0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS      0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS       0U /* WWDG register callback disabled      */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+#define USE_SPI_CRC                   0U
+
+/* ################## SDMMC peripheral configuration ######################### */
+
+#define USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32u5xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32u5xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+  #include "stm32u5xx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_DCACHE_MODULE_ENABLED
+  #include "stm32u5xx_hal_dcache.h"
+#endif /* HAL_DCACHE_MODULE_ENABLED */
+
+#ifdef HAL_GTZC_MODULE_ENABLED
+  #include "stm32u5xx_hal_gtzc.h"
+#endif /* HAL_GTZC_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32u5xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32u5xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+#include "stm32u5xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32u5xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+  #include "stm32u5xx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32u5xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32u5xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32u5xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32u5xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32u5xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32u5xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32u5xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32u5xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32u5xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32u5xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32u5xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32u5xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32u5xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32u5xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32u5xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32u5xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32u5xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+ #include "stm32u5xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32u5xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32u5xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32u5xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32u5xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32u5xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32u5xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32u5xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32u5xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32u5xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32u5xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32u5xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32u5xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32u5xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32u5xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32u5xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+ #include "stm32u5xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32u5xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32u5xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+ #include "stm32u5xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+ #include "stm32u5xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32u5xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_GPU2D_MODULE_ENABLED
+  #include "stm32u5xx_hal_gpu2d.h"
+#endif /* HAL_GPU2D_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+ #include "stm32u5xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+ #include "stm32u5xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_RAMCFG_MODULE_ENABLED
+ #include "stm32u5xx_hal_ramcfg.h"
+#endif /* HAL_RAMCFG_MODULE_ENABLED */
+
+#ifdef HAL_MDF_MODULE_ENABLED
+ #include "stm32u5xx_hal_mdf.h"
+#endif /* HAL_MDF_MODULE_ENABLED */
+
+#ifdef HAL_XSPI_MODULE_ENABLED
+ #include "stm32u5xx_hal_xspi.h"
+#endif /* HAL_XSPI_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t *file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_CONF_H */
+
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 514ffcd4d..86c68baf8 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -189,6 +189,11 @@
 #elif TU_CHECK_MCU(OPT_MCU_STM32WB)
   #define TUP_DCD_ENDPOINT_MAX    8
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32U5)
+  #define TUP_USBIP_DWC2
+  #define TUP_USBIP_DWC2_STM32
+  #define TUP_DCD_ENDPOINT_MAX    6
+
 //------------- Sony -------------//
 #elif TU_CHECK_MCU(OPT_MCU_CXD56)
   #define TUP_DCD_ENDPOINT_MAX    7
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index 337f611d8..ea786362e 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -82,6 +82,12 @@
   #define EP_MAX_FS       6
   #define EP_FIFO_SIZE_FS 1280
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32U5
+  #include "stm32u5xx.h"
+  #define USB_OTG_FS_PERIPH_BASE       USB_OTG_FS_BASE
+  #define EP_MAX_FS       6
+  #define EP_FIFO_SIZE_FS 1280
+
 #else
   #error "Unsupported MCUs"
 #endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 4c2dd0258..f95ae6273 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -84,6 +84,7 @@ typedef int make_iso_compilers_happy;
 #define OPT_MCU_STM32G0           310 ///< ST G0
 #define OPT_MCU_STM32G4           311 ///< ST G4
 #define OPT_MCU_STM32WB           312 ///< ST WB
+#define OPT_MCU_STM32U5           313 ///< ST U5
 
 // Sony
 #define OPT_MCU_CXD56             400 ///< SONY CXD56

From 2c1ff2673baaeefc6520d25e87d5ca5e6b2093db Mon Sep 17 00:00:00 2001
From: tswan-quasi <tucker.swan@10xar.com>
Date: Thu, 13 Oct 2022 11:48:30 -0400
Subject: [PATCH 1183/2085] (void) rhport for unused parameter

---
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 7220654e0..1f29abbb8 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -375,6 +375,8 @@ void dcd_edpt_close_all (uint8_t rhport)
 
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
+  (void) rhport;
+  
   uint8_t ep_id = ep_addr2id(ep_addr);
   _dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
   _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
@@ -403,8 +405,6 @@ static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset,
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
-  (void) rhport;
-
   uint8_t const ep_id = ep_addr2id(ep_addr);
 
   tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t));

From 2a520fb921fceb2a8e6182bff073c4a98504127f Mon Sep 17 00:00:00 2001
From: gaoyichuan <gaoyichuan000@gmail.com>
Date: Wed, 25 May 2022 09:51:58 +0800
Subject: [PATCH 1184/2085] hid: add fido hid descriptor templates

---
 src/class/hid/hid.h        |  9 +++++++++
 src/class/hid/hid_device.h | 23 +++++++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 44a464be1..296664f62 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -708,6 +708,7 @@ enum {
   HID_USAGE_PAGE_MSR             = 0x8e,
   HID_USAGE_PAGE_CAMERA          = 0x90,
   HID_USAGE_PAGE_ARCADE          = 0x91,
+  HID_USAGE_PAGE_FIDO_ALLIANCE   = 0xF1D0,
   HID_USAGE_PAGE_VENDOR          = 0xFF00 // 0xFF00 - 0xFFFF
 };
 
@@ -844,6 +845,14 @@ enum
   HID_USAGE_CONSUMER_AC_PAN                            = 0x0238,
 };
 
+/// HID Usage Table: FIDO Alliance Page (0xF1D0)
+enum
+{
+  HID_USAGE_FIDO_U2F_AUTHENTICATOR_DEVICE  = 0x01,
+  HID_USAGE_FIDO_INPUT_REPORT_DATA         = 0x20,
+  HID_USAGE_FIDO_OUTPUT_REPORT_DATA        = 0x21
+};
+
 /*--------------------------------------------------------------------
  * ASCII to KEYCODE Conversion
  *  Expand to array of [128][2] (shift, keycode)
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 3143b1024..d6cf27bd8 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -352,6 +352,29 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     HID_INPUT          ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
   HID_COLLECTION_END \
 
+// FIDO U2F Authenticator Descriptor Template
+#define TUD_HID_REPORT_DESC_FIDO_U2F(...) \
+  HID_USAGE_PAGE_N ( HID_USAGE_PAGE_FIDO_ALLIANCE, 2          ) ,\
+  HID_USAGE      ( HID_USAGE_FIDO_U2F_AUTHENTICATOR_DEVICE    ) ,\
+  HID_COLLECTION ( HID_COLLECTION_APPLICATION                 ) ,\
+    /* Report ID if any */ \
+    __VA_ARGS__ \
+    /* Usage Data In */ \
+    HID_USAGE         ( HID_USAGE_FIDO_INPUT_REPORT_DATA       ) ,\
+    HID_LOGICAL_MIN   ( 0                                      ) ,\
+    HID_LOGICAL_MAX_N ( 255, 2                                 ) ,\
+    HID_REPORT_SIZE   ( 8                                      ) ,\
+    HID_REPORT_COUNT  ( 64                                     ) ,\
+    HID_INPUT         ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+    /* Usage Data Out */ \
+    HID_USAGE         ( HID_USAGE_FIDO_OUTPUT_REPORT_DATA      ) ,\
+    HID_LOGICAL_MIN   ( 0                                      ) ,\
+    HID_LOGICAL_MAX_N ( 255, 2                                 ) ,\
+    HID_REPORT_SIZE   ( 8                                      ) ,\
+    HID_REPORT_COUNT  ( 64                                     ) ,\
+    HID_OUTPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
+  HID_COLLECTION_END \
+
 // HID Generic Input & Output
 // - 1st parameter is report size (mandatory)
 // - 2nd parameter is report id HID_REPORT_ID(n) (optional)

From 3846d5f38c465d673442db1085c69f3602e21470 Mon Sep 17 00:00:00 2001
From: gaoyichuan <gaoyichuan000@gmail.com>
Date: Sat, 15 Oct 2022 19:22:21 +0800
Subject: [PATCH 1185/2085] hid: add configurable report size for fido

---
 src/class/hid/hid_device.h | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index d6cf27bd8..a9f47d644 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -353,7 +353,9 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
   HID_COLLECTION_END \
 
 // FIDO U2F Authenticator Descriptor Template
-#define TUD_HID_REPORT_DESC_FIDO_U2F(...) \
+// - 1st parameter is report size, which is 64 bytes maximum in U2F
+// - 2nd parameter is HID_REPORT_ID(n) (optional)
+#define TUD_HID_REPORT_DESC_FIDO_U2F(report_size, ...) \
   HID_USAGE_PAGE_N ( HID_USAGE_PAGE_FIDO_ALLIANCE, 2          ) ,\
   HID_USAGE      ( HID_USAGE_FIDO_U2F_AUTHENTICATOR_DEVICE    ) ,\
   HID_COLLECTION ( HID_COLLECTION_APPLICATION                 ) ,\
@@ -362,16 +364,16 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
     /* Usage Data In */ \
     HID_USAGE         ( HID_USAGE_FIDO_INPUT_REPORT_DATA       ) ,\
     HID_LOGICAL_MIN   ( 0                                      ) ,\
-    HID_LOGICAL_MAX_N ( 255, 2                                 ) ,\
+    HID_LOGICAL_MAX_N ( 0xff, 2                                ) ,\
     HID_REPORT_SIZE   ( 8                                      ) ,\
-    HID_REPORT_COUNT  ( 64                                     ) ,\
+    HID_REPORT_COUNT  ( report_size                            ) ,\
     HID_INPUT         ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
     /* Usage Data Out */ \
     HID_USAGE         ( HID_USAGE_FIDO_OUTPUT_REPORT_DATA      ) ,\
     HID_LOGICAL_MIN   ( 0                                      ) ,\
-    HID_LOGICAL_MAX_N ( 255, 2                                 ) ,\
+    HID_LOGICAL_MAX_N ( 0xff, 2                                ) ,\
     HID_REPORT_SIZE   ( 8                                      ) ,\
-    HID_REPORT_COUNT  ( 64                                     ) ,\
+    HID_REPORT_COUNT  ( report_size                            ) ,\
     HID_OUTPUT        ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
   HID_COLLECTION_END \
 

From 3f45f3767240dccfccbf9b013a9109912bfa2b5c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 17 Oct 2022 23:13:24 +0700
Subject: [PATCH 1186/2085] minor rename

---
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 1f29abbb8..51baaf224 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -78,7 +78,8 @@ typedef struct {
 
 // Max nbytes for each control/bulk/interrupt transfer
 enum {
-  NBYTES_CBI_FS_ISO_MAX = 1023, // FS ISO
+  NBYTES_ISO_FS_MAX = 1023, // FS ISO
+  NBYTES_ISO_HS_MAX = 1024, // HS ISO
   NBYTES_CBI_FS_MAX = 64, // FS control/bulk/interrupt
   NBYTES_CBI_HS_MAX = 32767 // can be up to all 15-bit, but only tested with 4096
 };
@@ -113,6 +114,8 @@ enum {
 typedef union TU_ATTR_PACKED
 {
   // Full and High speed has different bit layout for buffer_offset and nbytes
+  // TODO FS/HS layout depends on the max speed of controller e.g
+  // lpc55s69 PORT0 is only FS but actually has the same layout as HS on port1
 
   // Buffer (aligned 64) = DATABUFSTART [31:22]  | buffer_offset [21:6]
   volatile struct {
@@ -388,7 +391,7 @@ static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset,
 
   if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
   {
-    nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].is_iso ? NBYTES_CBI_FS_ISO_MAX : NBYTES_CBI_FS_MAX);
+    nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
     _dcd.ep[ep_id][0].buffer_fs.offset = buf_offset;
     _dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes;
   }else

From a49ca795afc9008085d905e6fb43f511dca7be7c Mon Sep 17 00:00:00 2001
From: Tomas Rezucha <tomas.rezucha@espressif.com>
Date: Tue, 18 Oct 2022 08:05:13 +0200
Subject: [PATCH 1187/2085] esp: Fix Isochronous transfers

On ESP32-S2/S3 ISO transfers must be configured for even or odd frame.

Closes https://github.com/hathach/tinyusb/issues/1382
---
 src/portable/espressif/esp32sx/dcd_esp32sx.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index a30fca0d8..0b75af627 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -59,6 +59,7 @@ typedef struct {
     uint16_t queued_len;
     uint16_t max_size;
     bool short_packet;
+    uint8_t interval;
 } xfer_ctl_t;
 
 static const char *TAG = "TUSB:DCD";
@@ -267,6 +268,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
 
   xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
   xfer->max_size = tu_edpt_packet_size(desc_edpt);
+  xfer->interval = desc_edpt->bInterval;
 
   if (dir == TUSB_DIR_OUT) {
     out_ep[epnum].doepctl |= USB_USBACTEP1_M |
@@ -379,6 +381,13 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
     USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes;
     USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK
 
+    // For ISO endpoint with interval=1 set correct DATA0/DATA1 bit for next frame
+    if ((USB0.in_ep_reg[epnum].diepctl & USB_D_EPTYPE0_M) == (1 << USB_D_EPTYPE1_S) && xfer->interval == 1) {
+      // Take odd/even bit from frame counter.
+      uint32_t const odd_frame_now = (USB0.dsts & (1u << USB_SOFFN_S));
+      USB0.in_ep_reg[epnum].diepctl |= (odd_frame_now ? USB_DI_SETD0PID1 : USB_DI_SETD1PID1);
+    }
+
     // Enable fifo empty interrupt only if there are something to put in the fifo.
     if(total_bytes != 0) {
       USB0.dtknqr4_fifoemptymsk |= (1 << epnum);
@@ -387,6 +396,13 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
     // Each complete packet for OUT xfers triggers XFRC.
     USB0.out_ep_reg[epnum].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S);
     USB0.out_ep_reg[epnum].doepctl  |= USB_EPENA0_M | USB_CNAK0_M;
+
+    // For ISO endpoint with interval=1 set correct DATA0/DATA1 bit for next frame
+    if ((USB0.out_ep_reg[epnum].doepctl & USB_D_EPTYPE0_M) == (1 << USB_D_EPTYPE1_S) && xfer->interval == 1) {
+      // Take odd/even bit from frame counter.
+      uint32_t const odd_frame_now = (USB0.dsts & (1u << USB_SOFFN_S));
+      USB0.out_ep_reg[epnum].doepctl |= (odd_frame_now ? USB_DO_SETD0PID1 : USB_DO_SETD1PID1);
+    }
   }
   return true;
 }

From 8f88ff559eb930b26233d19ae9df75f3a5c6a786 Mon Sep 17 00:00:00 2001
From: Bastien Nocera <hadess@hadess.net>
Date: Tue, 18 Oct 2022 15:14:45 +0200
Subject: [PATCH 1188/2085] Fix typo in getting_started guide

Fixes: 1234111 ("add get-deps target")
---
 docs/reference/getting_started.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index 3cdb46849..e328757ba 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -61,7 +61,7 @@ To build example, first change directory to an example folder.
 
    $ cd examples/device/cdc_msc
 
-Before building, we need to download MCU driver submodule to provide low-level MCU peripheral's driver first. Run the ``get-dpes`` target in one of the example folder as follow. You only need to do this once per mcu
+Before building, we need to download MCU driver submodule to provide low-level MCU peripheral's driver first. Run the ``get-deps`` target in one of the example folder as follow. You only need to do this once per mcu
 
 .. code-block::
 

From 19208cd88dc57e6a385dbd4ce04cd9ad394c96c0 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 20 Oct 2022 11:04:49 +0200
Subject: [PATCH 1189/2085] stm32u5: Fix submodules paths

Local paths were commited to submodule definitions
This just removes prefix for submodules path and name
---
 .gitmodules | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/.gitmodules b/.gitmodules
index aafb0f520..dcac0d9ab 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -149,9 +149,9 @@
 [submodule "hw/mcu/raspberry_pi/Pico-PIO-USB"]
 	path = hw/mcu/raspberry_pi/Pico-PIO-USB
 	url = https://github.com/sekigon-gonnoc/Pico-PIO-USB.git
-[submodule "/home/ubuntu/tinyusb/hw/mcu/st/cmsis_device_u5"]
-	path = /home/ubuntu/tinyusb/hw/mcu/st/cmsis_device_u5
+[submodule "hw/mcu/st/cmsis_device_u5"]
+	path = hw/mcu/st/cmsis_device_u5
 	url = https://github.com/STMicroelectronics/cmsis_device_u5
-[submodule "/home/ubuntu/tinyusb/hw/mcu/st/stm32u5xx_hal_driver"]
-	path = /home/ubuntu/tinyusb/hw/mcu/st/stm32u5xx_hal_driver
+[submodule "hw/mcu/st/stm32u5xx_hal_driver"]
+	path = hw/mcu/st/stm32u5xx_hal_driver
 	url = https://github.com/STMicroelectronics/stm32u5xx_hal_driver

From fe4278554b04c3446b30f28fdb6aaad908f8fa48 Mon Sep 17 00:00:00 2001
From: tswan-quasi <tucker.swan@10xar.com>
Date: Thu, 20 Oct 2022 11:02:57 -0400
Subject: [PATCH 1190/2085] dummy buffer only on EP0 OUT ZLPs

---
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 21 ++++++++------------
 1 file changed, 8 insertions(+), 13 deletions(-)

diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 51baaf224..ed6c14f17 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -178,7 +178,7 @@ typedef struct
 //    For example: LPC55s69 port1 Highspeed must be USB_RAM (0x40100000)
 //    Use CFG_TUSB_MEM_SECTION to place it accordingly.
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static volatile uint8_t dummy[64]; // TODO temp fix to prevent accidental overwrite due to ep[][].buffer_xx.offset being 0
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static volatile uint8_t dummy[8] = { 0 }; // a fix for EP0 OUT ZLPs overwriting the buffer
 
 //--------------------------------------------------------------------+
 // Multiple Controllers
@@ -244,16 +244,7 @@ static void prepare_setup_packet(uint8_t rhport)
 
 static void edpt_reset(uint8_t rhport, uint8_t ep_id)
 {
-  const uint32_t offset = get_buf_offset((void*)(uint32_t)dummy);
   tu_memclr(&_dcd.ep[ep_id], sizeof(_dcd.ep[ep_id]));
-  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
-  {
-    _dcd.ep[ep_id][0].buffer_fs.offset = _dcd.ep[ep_id][1].buffer_fs.offset = offset;
-  }
-  else
-  {
-    _dcd.ep[ep_id][0].buffer_hs.offset = _dcd.ep[ep_id][1].buffer_hs.offset = offset;
-  }
 }
 
 static void edpt_reset_all(uint8_t rhport)
@@ -413,7 +404,11 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
   tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t));
   _dcd.dma[ep_id].total_bytes = total_bytes;
 
-  prepare_ep_xfer(rhport, ep_id, buffer ? get_buf_offset(buffer) : get_buf_offset((void*)(uint32_t)dummy), total_bytes);
+  if (!buffer && !ep_id) // for EP0 OUT ZLPs to prevent overwrites to buffer
+  {
+    buffer = (uint8_t*)(uint32_t)dummy;
+  }
+  prepare_ep_xfer(rhport, ep_id, get_buf_offset(buffer), total_bytes);
 
   return true;
 }
@@ -426,8 +421,8 @@ static void bus_reset(uint8_t rhport)
   tu_memclr(&_dcd, sizeof(dcd_data_t));
   edpt_reset_all(rhport); 
 
-  // disable all non-control endpoints on bus reset
-  for(uint8_t ep_id = 2; ep_id < 2*MAX_EP_PAIRS; ep_id++)
+  // disable all endpoints as epecified by LPC55S69 UM Table 778
+  for(uint8_t ep_id = 0; ep_id < 2*MAX_EP_PAIRS; ep_id++)
   {
     _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
   }

From 0b5504708172aa269653924da95e358720aabf7d Mon Sep 17 00:00:00 2001
From: tswan-quasi <tucker.swan@10xar.com>
Date: Thu, 20 Oct 2022 11:04:49 -0400
Subject: [PATCH 1191/2085] typo fix

---
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index ed6c14f17..80d85fa46 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -421,7 +421,7 @@ static void bus_reset(uint8_t rhport)
   tu_memclr(&_dcd, sizeof(dcd_data_t));
   edpt_reset_all(rhport); 
 
-  // disable all endpoints as epecified by LPC55S69 UM Table 778
+  // disable all endpoints as specified by LPC55S69 UM Table 778
   for(uint8_t ep_id = 0; ep_id < 2*MAX_EP_PAIRS; ep_id++)
   {
     _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;

From 4ec1643bdbca34d0e6d575646ed556087bac5d6e Mon Sep 17 00:00:00 2001
From: Mark K Cowan <mark@battlesnake.co.uk>
Date: Thu, 20 Oct 2022 22:45:58 +0300
Subject: [PATCH 1192/2085] do not apply storage attributes to member of struct

---
 src/class/audio/audio_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index a021755ba..0eccf282d 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -341,7 +341,7 @@ typedef struct
 
   // Audio control interrupt buffer - no FIFO - 6 Bytes according to UAC 2 specification (p. 74)
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-  CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
+  uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
 #endif
 
   // Decoding parameters - parameters are set when alternate AS interface is set by host

From 35e1a27c950c4b25106c074d0b66220d099e54a7 Mon Sep 17 00:00:00 2001
From: tswan-quasi <tucker.swan@10xar.com>
Date: Fri, 21 Oct 2022 15:06:30 -0400
Subject: [PATCH 1193/2085] unused (void) cast

---
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 80d85fa46..7825d287f 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -244,6 +244,7 @@ static void prepare_setup_packet(uint8_t rhport)
 
 static void edpt_reset(uint8_t rhport, uint8_t ep_id)
 {
+  (void) rhport;
   tu_memclr(&_dcd.ep[ep_id], sizeof(_dcd.ep[ep_id]));
 }
 

From e3b7ed9ae966be1cb41165343ef30c6523ed5771 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Oct 2022 18:43:21 +0700
Subject: [PATCH 1194/2085] use dummy for all ZLP for ip3511, fix lpc55 build
 with DEBUG=1

---
 hw/bsp/lpc55/family.mk                       |  1 +
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 10 ++++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index 1af1d076e..9d6702b94 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -43,6 +43,7 @@ SRC_C += \
 	$(MCU_DIR)/drivers/fsl_power.c \
 	$(MCU_DIR)/drivers/fsl_reset.c \
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/common/fsl_common_arm.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
 	lib/sct_neopixel/sct_neopixel.c
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 7825d287f..9b490c48c 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -178,7 +178,9 @@ typedef struct
 //    For example: LPC55s69 port1 Highspeed must be USB_RAM (0x40100000)
 //    Use CFG_TUSB_MEM_SECTION to place it accordingly.
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static volatile uint8_t dummy[8] = { 0 }; // a fix for EP0 OUT ZLPs overwriting the buffer
+
+// Dummy buffer to fix ZLPs overwriting the buffer (probably an USB/DMA controller bug)
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
 
 //--------------------------------------------------------------------+
 // Multiple Controllers
@@ -405,10 +407,14 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
   tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t));
   _dcd.dma[ep_id].total_bytes = total_bytes;
 
-  if (!buffer && !ep_id) // for EP0 OUT ZLPs to prevent overwrites to buffer
+  if (!buffer)
   {
+    // Although having no data, ZLPs can cause buffer overwritten to zeroes.
+    // Probably due to USB/DMA controller side effect/bug.
+    // Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART
     buffer = (uint8_t*)(uint32_t)dummy;
   }
+
   prepare_ep_xfer(rhport, ep_id, get_buf_offset(buffer), total_bytes);
 
   return true;

From 815c2cc9959cc9a127d4ff64f65743d4ac8713ce Mon Sep 17 00:00:00 2001
From: Mark K Cowan <mark@battlesnake.co.uk>
Date: Mon, 24 Oct 2022 20:36:45 +0300
Subject: [PATCH 1195/2085] keep alignment spec

---
 src/class/audio/audio_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 0eccf282d..2b22834b6 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -341,7 +341,7 @@ typedef struct
 
   // Audio control interrupt buffer - no FIFO - 6 Bytes according to UAC 2 specification (p. 74)
 #if CFG_TUD_AUDIO_INT_CTR_EPSIZE_IN
-  uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t ep_int_ctr_buf[CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE];
 #endif
 
   // Decoding parameters - parameters are set when alternate AS interface is set by host

From 3f3f6eee1c1b1bec43933488b27772a9f848c529 Mon Sep 17 00:00:00 2001
From: Jannis Achstetter <kripton@kripserver.net>
Date: Tue, 1 Nov 2022 23:42:58 +0100
Subject: [PATCH 1196/2085] dhserver: Support DHCP clients that don't send the
 MESSAGETYPE as first option

Signed-off-by: Jannis Achstetter <kripton@kripserver.net>
---
 lib/networking/dhserver.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/lib/networking/dhserver.c b/lib/networking/dhserver.c
index 590739236..def431f75 100644
--- a/lib/networking/dhserver.c
+++ b/lib/networking/dhserver.c
@@ -240,7 +240,11 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const
 	unsigned n = p->len;
 	if (n > sizeof(dhcp_data)) n = sizeof(dhcp_data);
 	memcpy(&dhcp_data, p->payload, n);
-	switch (dhcp_data.dp_options[2])
+
+	ptr = find_dhcp_option(dhcp_data.dp_options, sizeof(dhcp_data.dp_options), DHCP_MESSAGETYPE);
+	if (ptr == NULL) return;
+
+	switch (ptr[2])
 	{
 		case DHCP_DISCOVER:
 			entry = entry_by_mac(dhcp_data.dp_chaddr);

From 38cdeb9e606b23071cd0bd9c505c09bc8df26bc4 Mon Sep 17 00:00:00 2001
From: Henrik Fegran <henrik.fegran@silabs.com>
Date: Thu, 3 Nov 2022 20:23:27 +0100
Subject: [PATCH 1197/2085] Fixed wrong FreeRTOS port for EFM32GG12

---
 hw/bsp/sltb009a/board.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index f5c240ca2..ddafa8a2b 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -35,7 +35,7 @@ INC += \
   $(TOP)/hw/bsp/$(BOARD)
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM3
+FREERTOS_PORT = ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = EFM32GG12B810F1024

From d2c9b8bcfba42ebc0023154493383b8bcb892020 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Nov 2022 16:14:35 +0700
Subject: [PATCH 1198/2085] fix -wconversion-int and add minor comment

---
 src/common/tusb_types.h                      |  8 ++++++--
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 18 ++++++++++--------
 2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index cfa24bd82..e11f08dd1 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -513,15 +513,19 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpo
   return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0);
 }
 
-static inline const char *tu_edpt_dir_str(tusb_dir_t dir) {
+#if CFG_TUSB_DEBUG
+TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir)
+{
   static const char *str[] = {"out", "in"};
   return str[dir];
 }
 
-static inline const char *tu_edpt_type_str(tusb_xfer_type_t t) {
+TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t)
+{
   static const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
   return str[t];
 }
+#endif
 
 //--------------------------------------------------------------------+
 // Descriptor helper
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 1125d30b6..10237d1f9 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -138,10 +138,10 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void)
         _handle_buff_status_bit(bit, ep);
     }
 
-    // Check interrupt endpoints
+    // Check "interrupt" (asynchronous) endpoints for both IN and OUT
     for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++)
     {
-        // EPX is bit 0
+        // EPX is bit 0 & 1
         // IEP1 IN  is bit 2
         // IEP1 OUT is bit 3
         // IEP2 IN  is bit 4
@@ -149,7 +149,8 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void)
         // IEP3 IN  is bit 6
         // IEP3 OUT is bit 7
         // etc
-        for(int j = 0; j < 2; j++){
+        for(uint j = 0; j < 2; j++)
+        {
             bit = 1 << (i*2+j);
             if (remaining_buffers & bit)
             {
@@ -279,6 +280,8 @@ static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
 
     if (transfer_type != TUSB_XFER_CONTROL)
     {
+        // Note: even though datasheet name these "Interrupt" endpoints. These are actually
+        // "Asynchronous" endpoints and can be used for other type such as: Bulk  (ISO need confirmation)
         ep = _next_free_interrupt_ep();
         pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num);
         assert(ep);
@@ -344,11 +347,10 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t
     if (ep != &epx)
     {
         // Endpoint has its own addr_endp and interrupt bits to be setup!
-        // This is an interrupt endpoint
-        // so need to set up interrupt endpoint address control register with:
-        // device address
-        // endpoint number / direction
-        // preamble
+        // This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with:
+        // - device address
+        // - endpoint number / direction
+        // - preamble
         uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
 
         if (dir == TUSB_DIR_OUT)

From cb0ca6151bda002d8c9c6650ed8d5b225614e0e2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Nov 2022 17:08:02 +0700
Subject: [PATCH 1199/2085] remove CFG_TUSB_DEBUG from tinyusb_common_base

---
 hw/bsp/rp2040/family.cmake | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 31e97d9af..5dba9dc39 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -55,7 +55,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	target_compile_definitions(tinyusb_common_base INTERFACE
 			CFG_TUSB_MCU=OPT_MCU_RP2040
 			CFG_TUSB_OS=OPT_OS_PICO
-			CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
+			#CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
 	)
 
 	#------------------------------------

From 44e19aa3c7ce7436a9722a609ca45530d3e1cb70 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 6 Nov 2022 14:44:18 +0700
Subject: [PATCH 1200/2085] rename PIO_USB_PIN_DP to PIO_USB_DP_PIN and change
 from 2 to 20 & moved to board.h

add support for  PIO_USB_VBUSEN_PIN and its state.
---
 hw/bsp/rp2040/board.h  | 12 ++++++++++++
 hw/bsp/rp2040/family.c | 11 +++++++----
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index 237f29dc2..56b8fec84 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -46,6 +46,18 @@
 #define UART_RX_PIN           PICO_DEFAULT_UART_RX_PIN
 #endif
 
+// PIO_USB_DP_PIN_DEFAULT is 0, which conflict with UART, change to other pin
+#ifndef PIO_USB_DP_PIN
+#define PIO_USB_DP_PIN        20
+#endif
+
+// VBUS enable pin and its active state
+// #define PIO_USB_VBUSEN_PIN    22
+
+#ifndef PIO_USB_VBUSEN_STATE
+#define PIO_USB_VBUSEN_STATE  1
+#endif
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 90e2192c0..ee5a73ff6 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -39,9 +39,6 @@
 #include "pio_usb.h"
 #endif
 
-// PIO_USB_DP_PIN_DEFAULT is 0, which conflict with UART, change to 2
-#define PICO_PIO_USB_PIN_DP   2
-
 #ifdef BUTTON_BOOTSEL
 // This example blinks the Picoboard LED when the BOOTSEL button is pressed.
 //
@@ -138,10 +135,16 @@ void board_init(void)
   // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb
   set_sys_clock_khz(120000, true);
 
+#ifdef PIO_USB_VBUSEN_PIN
+  gpio_init(PIO_USB_VBUSEN_PIN);
+  gpio_set_dir(PIO_USB_VBUSEN_PIN, GPIO_OUT);
+  gpio_put(PIO_USB_VBUSEN_PIN, PIO_USB_VBUSEN_STATE);
+#endif
+
   // rp2040 use pico-pio-usb for host tuh_configure() can be used to passed pio configuration to the host stack
   // Note: tuh_configure() must be called before tuh_init()
   pio_usb_configuration_t pio_cfg = PIO_USB_DEFAULT_CONFIG;
-  pio_cfg.pin_dp = PICO_PIO_USB_PIN_DP;
+  pio_cfg.pin_dp = PIO_USB_DP_PIN;
   tuh_configure(BOARD_TUH_RHPORT, TUH_CFGID_RPI_PIO_USB_CONFIGURATION, &pio_cfg);
 #endif
 

From a061bc41733047468b624fb33dc0811d1eb984e4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 6 Nov 2022 14:46:44 +0700
Subject: [PATCH 1201/2085] bump up pico-pio-usb

---
 hw/mcu/raspberry_pi/Pico-PIO-USB | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/raspberry_pi/Pico-PIO-USB b/hw/mcu/raspberry_pi/Pico-PIO-USB
index 92bd3b4c3..f78dc9b2c 160000
--- a/hw/mcu/raspberry_pi/Pico-PIO-USB
+++ b/hw/mcu/raspberry_pi/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 92bd3b4c3ad2fce36166e4a357749b6d4fe9013b
+Subproject commit f78dc9b2c7fa9b82587e43babdc1d21294a32985

From b92015544490ed6fd8891db59c4cb88365f0f137 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 6 Nov 2022 14:56:05 +0700
Subject: [PATCH 1202/2085] minor clean up

---
 .github/workflows/build_arm.yml     | 8 ++++----
 .github/workflows/build_esp.yml     | 7 ++++---
 .github/workflows/build_msp430.yml  | 7 ++++---
 .github/workflows/build_renesas.yml | 7 ++++---
 .github/workflows/build_riscv.yml   | 7 ++++---
 5 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index a321948e3..56804da8a 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -99,10 +99,10 @@ jobs:
     - name: Linker Map
       run: |
         pip install linkermap/
-        # find -quit to only print map of 1 board per example
-        for ex in `ls -d examples/*/*/`; do \
-          find ${ex} -name *.map -print -quit | \
-          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        # find -quit to only print linkermap of 1 board per example
+        for ex in `ls -d examples/*/*/`
+        do
+          find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
         done
 
     # Following steps are for Hardware Test with self-hosted
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 6a46773b2..417887172 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -43,7 +43,8 @@ jobs:
     - name: Linker Map
       run: |
         pip install linkermap/
-        for ex in `ls -d examples/device/*/`; do \
-          find ${ex} -maxdepth 3 -name *.map -print -quit | \
-          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        # find -quit to only print linkermap of 1 board per example
+        for ex in `ls -d examples/device/*/`
+        do
+          find ${ex} -maxdepth 3 -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
         done
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index ea93f09a0..731febb03 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -61,7 +61,8 @@ jobs:
     - name: Linker Map
       run: |
         pip install linkermap/
-        for ex in `ls -d examples/device/*/`; do \
-          find ${ex} -name *.map -print -quit | \
-          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        # find -quit to only print linkermap of 1 board per example
+        for ex in `ls -d examples/device/*/`
+        do
+          find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
         done
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 2563d3549..4de42f935 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -62,7 +62,8 @@ jobs:
     - name: Linker Map
       run: |
         pip install linkermap/
-        for ex in `ls -d examples/device/*/`; do \
-          find ${ex} -name *.map -print -quit | \
-          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        # find -quit to only print linkermap of 1 board per example
+        for ex in `ls -d examples/device/*/`
+        do
+          find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
         done
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 90dc35206..9362da893 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -62,7 +62,8 @@ jobs:
     - name: Linker Map
       run: |
         pip install linkermap/
-        for ex in `ls -d examples/device/*/`; do \
-          find ${ex} -name *.map -print -quit | \
-          xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'; \
+        # find -quit to only print linkermap of 1 board per example
+        for ex in `ls -d examples/device/*/`
+        do
+          find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
         done

From fee90f353f426d6fafe323534ad7d91918d4b98d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 6 Nov 2022 15:17:00 +0700
Subject: [PATCH 1203/2085] bump up setup  python action to v4

---
 .github/workflows/build_aarch64.yml | 2 +-
 .github/workflows/build_arm.yml     | 2 +-
 .github/workflows/build_esp.yml     | 2 +-
 .github/workflows/build_msp430.yml  | 2 +-
 .github/workflows/build_renesas.yml | 2 +-
 .github/workflows/build_riscv.yml   | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index b4ea8a0eb..d610d6eff 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -21,7 +21,7 @@ jobs:
         - 'broadcom_64bit'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v4
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 56804da8a..4d27ba729 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -65,7 +65,7 @@ jobs:
         - 'xmc4000'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v3
+      uses: actions/setup-python@v4
 
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 417887172..162226cc5 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -23,7 +23,7 @@ jobs:
 
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v4
 
     - name: Pull ESP-IDF docker
       run: docker pull espressif/idf:latest
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 731febb03..b43d9e740 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -18,7 +18,7 @@ jobs:
         - 'msp430'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v4
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 4de42f935..c8920c7f7 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -18,7 +18,7 @@ jobs:
         - 'rx'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v4
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 9362da893..a0e09190b 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -19,7 +19,7 @@ jobs:
         - 'gd32vf103'
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v2
+      uses: actions/setup-python@v4
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3

From ca4ae61c1ce79f36e540fa4848b9e575a21e71d3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 6 Nov 2022 22:06:22 +0700
Subject: [PATCH 1204/2085] use gh cli instead of action for workflow dispatch

---
 .github/workflows/build_aarch64.yml | 2 ++
 .github/workflows/build_arm.yml     | 9 +++++----
 .github/workflows/build_esp.yml     | 2 ++
 .github/workflows/build_renesas.yml | 2 ++
 .github/workflows/build_riscv.yml   | 2 ++
 5 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index d610d6eff..18989a5e9 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -22,6 +22,8 @@ jobs:
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
+      with:
+        python-version: '3.x'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 4d27ba729..12853b72b 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -66,6 +66,8 @@ jobs:
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
+      with:
+        python-version: '3.x'
 
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
@@ -121,10 +123,9 @@ jobs:
 
     - name: Trigger Hardware Test
       if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
-      uses: benc-uk/workflow-dispatch@v1
-      with:
-        workflow: Hardware Test
-        token: ${{ secrets.TRIGGER_SELF_HOSTED }}
+      env:
+        GH_TOKEN: ${{ secrets.API_TOKEN_GITHUB }}
+      run: gh workflow run test_hardware.yml -r $GITHUB_REF
             
   # ---------------------------------------
   # Build all no-family (orphaned) boards
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 162226cc5..51d91de49 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -24,6 +24,8 @@ jobs:
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
+      with:
+        python-version: '3.x'
 
     - name: Pull ESP-IDF docker
       run: docker pull espressif/idf:latest
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index c8920c7f7..d212708f7 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -19,6 +19,8 @@ jobs:
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
+      with:
+        python-version: '3.x'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index a0e09190b..96b8c676b 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -20,6 +20,8 @@ jobs:
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
+      with:
+        python-version: '3.x'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3

From 5d13eb8e7a715b3dd02ef485808d82145870b90c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 6 Nov 2022 22:33:55 +0700
Subject: [PATCH 1205/2085] move test_hardware into build_arm

---
 .github/workflows/build_arm.yml     | 72 ++++++++++++++++++++++++++++-
 .github/workflows/test_hardware.yml | 69 ---------------------------
 2 files changed, 70 insertions(+), 71 deletions(-)
 delete mode 100644 .github/workflows/test_hardware.yml

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 12853b72b..00de92fa6 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -126,7 +126,7 @@ jobs:
       env:
         GH_TOKEN: ${{ secrets.API_TOKEN_GITHUB }}
       run: gh workflow run test_hardware.yml -r $GITHUB_REF
-            
+
   # ---------------------------------------
   # Build all no-family (orphaned) boards
   # ---------------------------------------
@@ -145,7 +145,9 @@ jobs:
 
     steps:
     - name: Setup Python
-      uses: actions/setup-python@v3
+      uses: actions/setup-python@v4
+      with:
+        python-version: '3.x'
 
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
@@ -160,3 +162,69 @@ jobs:
 
     - name: Build
       run: python3 tools/build_board.py ${{ matrix.example }}
+
+  # ---------------------------------------
+  # Hardware in the loop (HIL)
+  # Current self-hosted instance is running on an RPI4 with
+  # - pico + pico-probe connected via USB
+  # - pico-probe is /dev/ttyACM0
+  # ---------------------------------------
+  hw-test:
+    # Limit the run to only hathach due to limited resource on RPI4
+    if: github.repository_owner == 'hathach'
+    needs: build-arm
+    runs-on: [self-hosted, Linux, ARM64]
+
+    steps:
+    - name: Clean workspace
+      run: |
+        echo "Cleaning up previous run"
+        rm -rf "${{ github.workspace }}"
+        mkdir -p "${{ github.workspace }}"
+
+    - name: Download rp2040 Artifacts
+      uses: actions/download-artifact@v3
+      with:
+        name: rp2040
+
+    - name: Create flash.sh
+      run: |
+        touch flash.sh
+        chmod +x flash.sh
+        echo > flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit"'
+
+    - name: Test cdc_dual_ports
+      run: |
+        ./flash.sh cdc_dual_ports.elf
+        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
+        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
+
+    - name: Test cdc_msc
+      run: |
+        ./flash.sh cdc_msc.elf
+        readme='/media/pi/TinyUSB MSC/README.TXT'
+        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
+        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+        test -f "$readme" && echo "$readme exists"
+        cat "$readme"
+
+    - name: Test dfu
+      run: |
+        ./flash.sh dfu.elf
+        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
+        dfu-util -d cafe -a 0 -U dfu0
+        dfu-util -d cafe -a 1 -U dfu1
+        grep "TinyUSB DFU! - Partition 0" dfu0
+        grep "TinyUSB DFU! - Partition 1" dfu1
+
+    - name: Test dfu_runtime
+      run: |
+        ./flash.sh dfu_runtime.elf
+        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
+
+#    - name: Test hid_boot_interface
+#      run: |
+#        ./flash.sh hid_boot_interface.elf
+#        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
+
diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
deleted file mode 100644
index 7a6e2a470..000000000
--- a/.github/workflows/test_hardware.yml
+++ /dev/null
@@ -1,69 +0,0 @@
-name: Hardware Test
-on:
-  workflow_dispatch:
-
-# Hardware in the loop (HIL)
-# Current self-hosted instance is running on an RPI4 with
-# - pico + pico-probe connected via USB
-# - pico-probe is /dev/ttyACM0
-
-jobs:
-  hw-test:
-    # Limit the run to only hathach due to limited resource on RPI4
-    if: github.repository_owner == 'hathach'
-    runs-on: [self-hosted, Linux, ARM64]
-
-    steps:
-    - name: Clean workspace
-      run: |
-        echo "Cleaning up previous run"
-        rm -rf "${{ github.workspace }}"
-        mkdir -p "${{ github.workspace }}"
-
-    - name: Download rp2040 Artifacts
-      uses: dawidd6/action-download-artifact@v2
-      with:
-        workflow: build_arm.yml
-        name: rp2040
-
-    - name: Create flash.sh
-      run: |
-        touch flash.sh
-        chmod +x flash.sh
-        echo > flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit"'
-
-    - name: Test cdc_dual_ports
-      run: |
-        ./flash.sh cdc_dual_ports.elf
-        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-
-    - name: Test cdc_msc
-      run: |
-        ./flash.sh cdc_msc.elf
-        readme='/media/pi/TinyUSB MSC/README.TXT'
-        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -f "$readme" && echo "$readme exists"
-        cat "$readme"
-
-    - name: Test dfu
-      run: |
-        ./flash.sh dfu.elf
-        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
-        dfu-util -d cafe -a 0 -U dfu0
-        dfu-util -d cafe -a 1 -U dfu1
-        grep "TinyUSB DFU! - Partition 0" dfu0
-        grep "TinyUSB DFU! - Partition 1" dfu1
-
-    - name: Test dfu_runtime
-      run: |
-        ./flash.sh dfu_runtime.elf
-        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
-
-#    - name: Test hid_boot_interface
-#      run: |
-#        ./flash.sh hid_boot_interface.elf
-#        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
-        
\ No newline at end of file

From a0dc9008a7c125b3f5e3b0bc565a06cce3d83863 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 6 Nov 2022 22:39:09 +0700
Subject: [PATCH 1206/2085] remove trigger hardware step

---
 .github/workflows/build_arm.yml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 00de92fa6..4d513d7ba 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -121,11 +121,11 @@ jobs:
         path: |
           *.elf
 
-    - name: Trigger Hardware Test
-      if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
-      env:
-        GH_TOKEN: ${{ secrets.API_TOKEN_GITHUB }}
-      run: gh workflow run test_hardware.yml -r $GITHUB_REF
+#    - name: Trigger Hardware Test
+#      if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
+#      env:
+#        GH_TOKEN: ${{ secrets.API_TOKEN_GITHUB }}
+#      run: gh workflow run test_hardware.yml -r $GITHUB_REF
 
   # ---------------------------------------
   # Build all no-family (orphaned) boards

From 030b50dce3434aa94cb7428c3e752133ac274ce5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 6 Nov 2022 23:19:34 +0700
Subject: [PATCH 1207/2085] final clean up

---
 .github/workflows/build_arm.yml | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 4d513d7ba..53f73a48f 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -121,12 +121,6 @@ jobs:
         path: |
           *.elf
 
-#    - name: Trigger Hardware Test
-#      if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
-#      env:
-#        GH_TOKEN: ${{ secrets.API_TOKEN_GITHUB }}
-#      run: gh workflow run test_hardware.yml -r $GITHUB_REF
-
   # ---------------------------------------
   # Build all no-family (orphaned) boards
   # ---------------------------------------

From 1eae139aa94130a63ecc4725852cb69c02566c82 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Mon, 7 Nov 2022 12:32:36 +0100
Subject: [PATCH 1208/2085] Add support for STM32L412.

---
 .../stm32l412nucleo/STM32L412KBUx_FLASH.ld    | 184 ++++++++++++++++++
 hw/bsp/stm32l4/boards/stm32l412nucleo/board.h | 141 ++++++++++++++
 .../stm32l4/boards/stm32l412nucleo/board.mk   |  10 +
 hw/bsp/stm32l4/family.c                       |  27 ++-
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |   9 +-
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   |   4 +
 6 files changed, 370 insertions(+), 5 deletions(-)
 create mode 100644 hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
 create mode 100644 hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
 create mode 100644 hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk

diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
new file mode 100644
index 000000000..28cd96131
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
@@ -0,0 +1,184 @@
+/*
+*****************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Abstract    : Linker script for STM32L412KBTx Device with
+**                128KByte FLASH, 40KByte RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+**  (c)Copyright Ac6.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Ac6 permit registered System Workbench for MCU users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the System Workbench for MCU toolchain.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20008000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 32K
+SRAM2 (xrw)      : ORIGIN = 0x10000000, LENGTH = 8K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >FLASH
+
+  .ARM.extab   : 
+  { 
+  . = ALIGN(8);
+  *(.ARM.extab* .gnu.linkonce.armextab.*)
+  . = ALIGN(8);
+  } >FLASH
+  .ARM : {
+	. = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+	. = ALIGN(8);
+  } >FLASH
+
+  .preinit_array     :
+  {
+	. = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+	. = ALIGN(8);
+  } >FLASH
+  
+  .init_array :
+  {
+	. = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+	. = ALIGN(8);
+  } >FLASH
+  .fini_array :
+  {
+	. = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+	. = ALIGN(8);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
new file mode 100644
index 000000000..704d742cc
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
@@ -0,0 +1,141 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_3
+#define LED_STATE_ON          1
+
+// Not a real button
+#define BUTTON_PORT           GPIOB
+#define BUTTON_PIN            GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE   1
+
+#define UART_DEV              LPUART1
+#define UART_CLK_EN           __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF8_LPUART1
+#define UART_TX_PIN           GPIO_PIN_2
+#define UART_RX_PIN           GPIO_PIN_3
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+/**
+  * @brief  System Clock Configuration
+  *         The system Clock is configured as follow :
+  *            System Clock source            = PLL (MSI)
+  *            SYSCLK(Hz)                     = 80000000
+  *            HCLK(Hz)                       = 80000000
+  *            AHB Prescaler                  = 1
+  *            APB1 Prescaler                 = 1
+  *            APB2 Prescaler                 = 1
+  *            MSI Frequency(Hz)              = 8000000
+  *            PLL_M                          = 1
+  *            PLL_N                          = 10
+  *            PLL_Q                          = 2
+  *            PLL_R                          = 2
+  *            VDD(V)                         = 3.3
+  * @param  None
+  * @retval None
+  */
+
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 10;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+
+  /** Enable the SYSCFG APB clock
+  */
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /** Configures CRS
+  */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+  RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
+  RCC_CRSInitStruct.ErrorLimitValue = 34;
+  RCC_CRSInitStruct.HSI48CalibrationValue = 32;
+
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+  
+  /* Select HSI48 output as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL output as UART clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+  PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
new file mode 100644
index 000000000..841ee4948
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
@@ -0,0 +1,10 @@
+CFLAGS += \
+  -DSTM32L412xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32L412KBUx_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l412xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32l412kb
diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c
index c15be98e5..8b464f647 100644
--- a/hw/bsp/stm32l4/family.c
+++ b/hw/bsp/stm32l4/family.c
@@ -33,7 +33,11 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
+#if defined(USB_OTG_FS)
 void OTG_FS_IRQHandler(void)
+#else
+void USB_IRQHandler(void)
+#endif
 {
   tud_int_handler(0);
 }
@@ -53,9 +57,15 @@ void board_init(void)
   __HAL_RCC_GPIOB_CLK_ENABLE();
   __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
+#if defined(GPIOE)
   __HAL_RCC_GPIOE_CLK_ENABLE();
+#endif
+#if defined(GPIOF)
   __HAL_RCC_GPIOF_CLK_ENABLE();
+#endif
+#if defined(GPIOG)
   __HAL_RCC_GPIOG_CLK_ENABLE();
+#endif
   __HAL_RCC_GPIOH_CLK_ENABLE();
   UART_CLK_EN();
 
@@ -95,7 +105,10 @@ void board_init(void)
 
   // IOSV bit MUST be set to access GPIO port G[2:15] */
   __HAL_RCC_PWR_CLK_ENABLE();
+
+#if defined(PWR_CR2_IOSV)
   HAL_PWREx_EnableVddIO2();
+#endif
 
   // Uart
   GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
@@ -124,9 +137,14 @@ void board_init(void)
   GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
+#if defined(USB_OTG_FS)
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
+#else
+  GPIO_InitStruct.Alternate = GPIO_AF10_USB_FS;
+#endif
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
+#if defined(USB_OTG_FS)
   /* Configure VBUS Pin */
   GPIO_InitStruct.Pin = GPIO_PIN_9;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
@@ -139,11 +157,16 @@ void board_init(void)
   GPIO_InitStruct.Pull = GPIO_PULLUP;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+#endif
 
   /* Enable USB FS Clocks */
+#if defined(USB_OTG_FS)
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
-
   board_vbus_sense_init();
+#else
+  __HAL_RCC_USB_CLK_ENABLE();
+#endif
+
 }
 
 //--------------------------------------------------------------------+
@@ -187,7 +210,7 @@ uint32_t board_millis(void)
 
 void HardFault_Handler (void)
 {
-  asm("bkpt");
+  asm("bkpt 0x10");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 177a7ad2a..ec3964b4a 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -111,7 +111,8 @@
 
 #if TUSB_OPT_DEVICE_ENABLED && \
       ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4) || \
-        (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) \
+        (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) || \
+        (TU_CHECK_MCU(OPT_MCU_STM32L4) && !defined(DCD_ATTR_DWC2_STM32)) \
       )
 
 // In order to reduce the dependance on HAL, we undefine this.
@@ -294,7 +295,8 @@ void dcd_int_enable (uint8_t rhport)
   // Member here forces write to RAM before allowing ISR to execute
   __DSB();
   __ISB();
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || \
+    CFG_TUSB_MCU == OPT_MCU_STM32L4
   NVIC_EnableIRQ(USB_IRQn);
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L1
@@ -338,7 +340,8 @@ void dcd_int_disable(uint8_t rhport)
 {
   (void)rhport;
 
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 || \
+    CFG_TUSB_MCU == OPT_MCU_STM32L4
   NVIC_DisableIRQ(USB_IRQn);
 #elif CFG_TUSB_MCU == OPT_MCU_STM32L1
   NVIC_DisableIRQ(USB_LP_IRQn);
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 596f7be6c..eabefa687 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -91,6 +91,10 @@
   #include "stm32g4xx.h"
   #define PMA_LENGTH (1024u)
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
+  #include "stm32l4xx.h"
+  #define PMA_LENGTH (1024u)
+
 #else
   #error You are using an untested or unimplemented STM32 variant. Please update the driver.
   // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4

From f3f3739073b46bc7609e4c55f50accbfb08e1807 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Mon, 7 Nov 2022 12:58:23 +0100
Subject: [PATCH 1209/2085] Fix DCD build.

---
 hw/bsp/stm32l4/family.mk                      | 1 +
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 9 ++++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index d6f55e5f9..1361e184c 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -22,6 +22,7 @@ CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 #src/portable/st/synopsys/dcd_synopsys.c
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
+    src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index b90ab7d11..c88a8a3a2 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -109,10 +109,17 @@
 #define STM32F1_FSDEV
 #endif
 
+#if defined(STM32L412xx) || defined(STM32L422xx) || \
+    defined(STM32L432xx) || defined(STM32L433xx) || \
+    defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx)
+#define STM32L4_FSDEV
+#endif
+
 #if CFG_TUD_ENABLED && \
       ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4, OPT_MCU_STM32WB) || \
         (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) || \
-        (TU_CHECK_MCU(OPT_MCU_STM32L4) && !defined(DCD_ATTR_DWC2_STM32)) \
+        (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV)) \
       )
 
 // In order to reduce the dependance on HAL, we undefine this.

From da1589f116ede03dfe6a12968934640ebb4cd94a Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Tue, 8 Nov 2022 21:58:51 +0100
Subject: [PATCH 1210/2085] Fix FREERTOS USB IRQ priority.

---
 hw/bsp/stm32l4/family.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c
index 8b464f647..0b1443aa0 100644
--- a/hw/bsp/stm32l4/family.c
+++ b/hw/bsp/stm32l4/family.c
@@ -74,7 +74,11 @@ void board_init(void)
   SysTick_Config(SystemCoreClock / 1000);
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#if defined(USB_OTG_FS)
+  NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#else
+  NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
 #endif
 
   /* Enable USB power on Pwrctrl CR2 register */

From abfcdf2cfb2f19a20d606ca906e2d75f599b2ed8 Mon Sep 17 00:00:00 2001
From: Kay Sievers <kay@versioduo.com>
Date: Fri, 11 Nov 2022 22:47:48 +0100
Subject: [PATCH 1211/2085] MIDI: support port name strings

This allows to set custom descriptive names for virtual MIDI
ports/cables. A MIDI port offers different functionality on
the same physical USB device. The names make it easier to
distinguish one from the other.
---
 src/device/usbd.h | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/device/usbd.h b/src/device/usbd.h
index 17b4d927b..731c57aad 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -308,15 +308,16 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   (uint8_t)(((_cablenum) - 1) * 4 + 4)
 
 #define TUD_MIDI_DESC_JACK_LEN (6 + 6 + 9 + 9)
-#define TUD_MIDI_DESC_JACK(_cablenum) \
+#define TUD_MIDI_DESC_JACK_DESC(_cablenum, _stridx) \
   /* MS In Jack (Embedded) */\
-  6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_IN_EMB(_cablenum), 0,\
+  6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_IN_EMB(_cablenum), _stridx,\
   /* MS In Jack (External) */\
-  6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_IN_EXT(_cablenum), 0,\
+  6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_IN_EXT(_cablenum), _stridx,\
   /* MS Out Jack (Embedded), connected to In Jack External */\
-  9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_OUT_EMB(_cablenum), 1, TUD_MIDI_JACKID_IN_EXT(_cablenum), 1, 0,\
+  9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_OUT_EMB(_cablenum), 1, TUD_MIDI_JACKID_IN_EXT(_cablenum), 1, _stridx,\
   /* MS Out Jack (External), connected to In Jack Embedded */\
-  9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_OUT_EXT(_cablenum), 1, TUD_MIDI_JACKID_IN_EMB(_cablenum), 1, 0
+  9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_OUT_EXT(_cablenum), 1, TUD_MIDI_JACKID_IN_EMB(_cablenum), 1, _stridx
+#define TUD_MIDI_DESC_JACK(_cablenum) TUD_MIDI_DESC_JACK_DESC(_cablenum, 0)
 
 #define TUD_MIDI_DESC_EP_LEN(_numcables) (9 + 4 + (_numcables))
 #define TUD_MIDI_DESC_EP(_epout, _epsize, _numcables) \
@@ -333,7 +334,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 // - 1 Embedded Jack out connected to 1 External Jack In
 #define TUD_MIDI_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \
   TUD_MIDI_DESC_HEAD(_itfnum, _stridx, 1),\
-  TUD_MIDI_DESC_JACK(1),\
+  TUD_MIDI_DESC_JACK_DESC(1, 0),\
   TUD_MIDI_DESC_EP(_epout, _epsize, 1),\
   TUD_MIDI_JACKID_IN_EMB(1),\
   TUD_MIDI_DESC_EP(_epin, _epsize, 1),\

From 931b7182890fb85d697d2073dc353124c4da5d28 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Nov 2022 18:10:41 +0700
Subject: [PATCH 1212/2085] try running HiFiPhile self-host with
 stm32l412nucleo

---
 .github/workflows/build_arm.yml     |  4 +-
 .github/workflows/test_hardware.yml | 82 +++++++++++++++++++++++++++++
 2 files changed, 84 insertions(+), 2 deletions(-)
 create mode 100644 .github/workflows/test_hardware.yml

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 53f73a48f..d47a82173 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -163,11 +163,11 @@ jobs:
   # - pico + pico-probe connected via USB
   # - pico-probe is /dev/ttyACM0
   # ---------------------------------------
-  hw-test:
+  hw-pi4-test:
     # Limit the run to only hathach due to limited resource on RPI4
     if: github.repository_owner == 'hathach'
     needs: build-arm
-    runs-on: [self-hosted, Linux, ARM64]
+    runs-on: [self-hosted, Linux, ARM64, rp2040]
 
     steps:
     - name: Clean workspace
diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
new file mode 100644
index 000000000..534a17e6e
--- /dev/null
+++ b/.github/workflows/test_hardware.yml
@@ -0,0 +1,82 @@
+name: Hardware Test
+on:
+  pull_request:
+  push:
+  release:
+    types:
+      - created
+
+# Hardware in the loop (HIL)
+# Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
+# - STM32L412 Nucleo with on-board jlink (with 1 ttyACM)
+
+jobs:
+  stm32l412nucleo-test:
+    runs-on: [self-hosted, Linux, X64, hifiphile]
+    steps:
+    - name: Clean workspace
+      run: |
+        echo "Cleaning up previous run"
+        rm -rf "${{ github.workspace }}"
+        mkdir -p "${{ github.workspace }}"
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v3
+
+    - name: Get Dependencies and Build
+      run: |
+        git submodule update --init lib/FreeRTOS-Kernel lib/lwip
+        python3 tools/get_dependencies.py stm32l4
+        python3 tools/build_family.py stm32l4
+
+    - name: Pick-up elf files
+      run: |
+        mkdir stm32l412nucleo/
+        find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} stm32l412nucleo/ \;
+
+    - name: Create flash.sh
+      run: |
+      	touch flash.sh
+        chmod +x flash.sh
+      	echo > flash.sh 'echo halt > flash.jlink'
+      	echo > flash.sh 'echo r >> flash.jlink'
+      	echo > flash.sh 'echo loadfile $1 >> flash.jlink'
+      	echo > flash.sh 'echo r >> flash.jlink'
+      	echo > flash.sh 'echo go >> flash.jlink'
+      	echo > flash.sh 'echo exit >> flash.jlink'
+      	echo > flash.sh 'JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -CommandFile flash.jlink'
+
+    - name: Test cdc_dual_ports
+      run: |
+        ./flash.sh cdc_dual_ports.elf
+        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
+        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
+
+    - name: Test cdc_msc
+      run: |
+        ./flash.sh cdc_msc.elf
+        readme='/media/pi/TinyUSB MSC/README.TXT'
+        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
+        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+        test -f "$readme" && echo "$readme exists"
+        cat "$readme"
+
+    - name: Test dfu
+      run: |
+        ./flash.sh dfu.elf
+        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
+        dfu-util -d cafe -a 0 -U dfu0
+        dfu-util -d cafe -a 1 -U dfu1
+        grep "TinyUSB DFU! - Partition 0" dfu0
+        grep "TinyUSB DFU! - Partition 1" dfu1
+
+    - name: Test dfu_runtime
+      run: |
+        ./flash.sh dfu_runtime.elf
+        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
+
+#    - name: Test hid_boot_interface
+#      run: |
+#        ./flash.sh hid_boot_interface.elf
+#        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done

From d8badc948fef7ffc332cd8e99fef6b2134b00147 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Nov 2022 18:13:19 +0700
Subject: [PATCH 1213/2085] update yml

---
 .github/workflows/test_hardware.yml | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 534a17e6e..891f8cd2f 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -36,15 +36,15 @@ jobs:
 
     - name: Create flash.sh
       run: |
-      	touch flash.sh
+        touch flash.sh
         chmod +x flash.sh
-      	echo > flash.sh 'echo halt > flash.jlink'
-      	echo > flash.sh 'echo r >> flash.jlink'
-      	echo > flash.sh 'echo loadfile $1 >> flash.jlink'
-      	echo > flash.sh 'echo r >> flash.jlink'
-      	echo > flash.sh 'echo go >> flash.jlink'
-      	echo > flash.sh 'echo exit >> flash.jlink'
-      	echo > flash.sh 'JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -CommandFile flash.jlink'
+        echo > flash.sh "echo halt > flash.jlink"
+        echo > flash.sh "echo r >> flash.jlink"
+        echo > flash.sh "echo loadfile $1 >> flash.jlink"
+        echo > flash.sh "echo r >> flash.jlink"
+        echo > flash.sh "echo go >> flash.jlink"
+        echo > flash.sh "echo exit >> flash.jlink"
+        echo > flash.sh "JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -CommandFile flash.jlink"
 
     - name: Test cdc_dual_ports
       run: |

From 468ec83c1b6a84b46031c16a3ff1684b59b19745 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Nov 2022 23:07:58 +0700
Subject: [PATCH 1214/2085] correct flash.sh creation

---
 .github/workflows/test_hardware.yml | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 891f8cd2f..70bcb0cb5 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -13,6 +13,7 @@ on:
 jobs:
   stm32l412nucleo-test:
     runs-on: [self-hosted, Linux, X64, hifiphile]
+
     steps:
     - name: Clean workspace
       run: |
@@ -36,15 +37,14 @@ jobs:
 
     - name: Create flash.sh
       run: |
-        touch flash.sh
-        chmod +x flash.sh
         echo > flash.sh "echo halt > flash.jlink"
-        echo > flash.sh "echo r >> flash.jlink"
-        echo > flash.sh "echo loadfile $1 >> flash.jlink"
-        echo > flash.sh "echo r >> flash.jlink"
-        echo > flash.sh "echo go >> flash.jlink"
-        echo > flash.sh "echo exit >> flash.jlink"
-        echo > flash.sh "JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -CommandFile flash.jlink"
+        echo >> flash.sh "echo r >> flash.jlink"
+        echo >> flash.sh "echo loadfile $1 >> flash.jlink"
+        echo >> flash.sh "echo r >> flash.jlink"
+        echo >> flash.sh "echo go >> flash.jlink"
+        echo >> flash.sh "echo exit >> flash.jlink"
+        echo >> flash.sh "JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -CommandFile flash.jlink"
+        chmod +x flash.sh
 
     - name: Test cdc_dual_ports
       run: |

From 2fb0cea7e21c6e985bd85ba876f43785026203b3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Nov 2022 23:37:07 +0700
Subject: [PATCH 1215/2085] more test

---
 .github/workflows/test_hardware.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 70bcb0cb5..796a2a035 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -8,7 +8,7 @@ on:
 
 # Hardware in the loop (HIL)
 # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
-# - STM32L412 Nucleo with on-board jlink (with 1 ttyACM)
+# - STM32L412 Nucleo with on-board jlink as ttyACM0
 
 jobs:
   stm32l412nucleo-test:
@@ -39,7 +39,7 @@ jobs:
       run: |
         echo > flash.sh "echo halt > flash.jlink"
         echo >> flash.sh "echo r >> flash.jlink"
-        echo >> flash.sh "echo loadfile $1 >> flash.jlink"
+        echo >> flash.sh "echo loadfile stm32l412nucleo/$1 >> flash.jlink"
         echo >> flash.sh "echo r >> flash.jlink"
         echo >> flash.sh "echo go >> flash.jlink"
         echo >> flash.sh "echo exit >> flash.jlink"

From 2f909c284a594a7cb853029d31b624eea788a349 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Nov 2022 23:47:24 +0700
Subject: [PATCH 1216/2085] more flash script

---
 .github/workflows/test_hardware.yml | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 796a2a035..2d3dc1e8c 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -37,13 +37,13 @@ jobs:
 
     - name: Create flash.sh
       run: |
-        echo > flash.sh "echo halt > flash.jlink"
-        echo >> flash.sh "echo r >> flash.jlink"
-        echo >> flash.sh "echo loadfile stm32l412nucleo/$1 >> flash.jlink"
-        echo >> flash.sh "echo r >> flash.jlink"
-        echo >> flash.sh "echo go >> flash.jlink"
-        echo >> flash.sh "echo exit >> flash.jlink"
-        echo >> flash.sh "JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -CommandFile flash.jlink"
+        echo > flash.sh 'echo halt > flash.jlink'
+        echo >> flash.sh 'echo r >> flash.jlink'
+        echo >> flash.sh 'echo loadfile stm32l412nucleo/$1 >> flash.jlink'
+        echo >> flash.sh 'echo r >> flash.jlink'
+        echo >> flash.sh 'echo go >> flash.jlink'
+        echo >> flash.sh 'echo exit >> flash.jlink'
+        echo >> flash.sh 'JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -CommandFile flash.jlink'
         chmod +x flash.sh
 
     - name: Test cdc_dual_ports

From a6d9fda5f902726bb073541a122ab93ebc976730 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Nov 2022 01:01:03 +0700
Subject: [PATCH 1217/2085] skip usb msc test

---
 .github/workflows/test_hardware.yml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 2d3dc1e8c..f8124c496 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -53,7 +53,9 @@ jobs:
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
+      # Debian does not auto mount usb drive. skip this test for now
     - name: Test cdc_msc
+      if: false
       run: |
         ./flash.sh cdc_msc.elf
         readme='/media/pi/TinyUSB MSC/README.TXT'

From d17eb94e848fe0bab4a26e18cd5961bd51953c65 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Nov 2022 09:36:12 +0700
Subject: [PATCH 1218/2085] only print flash output if failed

---
 .github/workflows/test_hardware.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index f8124c496..3ef1fdc56 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -43,7 +43,8 @@ jobs:
         echo >> flash.sh 'echo r >> flash.jlink'
         echo >> flash.sh 'echo go >> flash.jlink'
         echo >> flash.sh 'echo exit >> flash.jlink'
-        echo >> flash.sh 'JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -CommandFile flash.jlink'
+        echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
+        echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
         chmod +x flash.sh
 
     - name: Test cdc_dual_ports

From ba0f1a3be51ee35241cac4e6abd579a1b5b43c9a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Nov 2022 11:01:54 +0700
Subject: [PATCH 1219/2085] disable orphan board workflow and minor update to
 pi4 workflow

---
 .github/workflows/build_arm.yml | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index d47a82173..369048fc6 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -123,9 +123,11 @@ jobs:
 
   # ---------------------------------------
   # Build all no-family (orphaned) boards
+  # disable this workflow since it is often failed randomly
   # ---------------------------------------
   build-board:
     runs-on: ubuntu-latest
+    if: false
     strategy:
       fail-fast: false
       matrix:
@@ -163,7 +165,7 @@ jobs:
   # - pico + pico-probe connected via USB
   # - pico-probe is /dev/ttyACM0
   # ---------------------------------------
-  hw-pi4-test:
+  hw-rp2040-test:
     # Limit the run to only hathach due to limited resource on RPI4
     if: github.repository_owner == 'hathach'
     needs: build-arm
@@ -183,9 +185,9 @@ jobs:
 
     - name: Create flash.sh
       run: |
-        touch flash.sh
+        echo > flash.sh 'cmdout=$(openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit")'
+        echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
         chmod +x flash.sh
-        echo > flash.sh 'openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit"'
 
     - name: Test cdc_dual_ports
       run: |

From 9b9d84177025b4b3bc0cf5ef47dc5c13b10e8f19 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Nov 2022 11:11:26 +0700
Subject: [PATCH 1220/2085] fix other ci warnings

---
 .github/workflows/build_aarch64.yml | 2 +-
 .github/workflows/build_msp430.yml  | 2 +-
 .github/workflows/build_renesas.yml | 2 +-
 .github/workflows/build_riscv.yml   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 18989a5e9..af26f33f2 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -41,7 +41,7 @@ jobs:
       run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz
 
     - name: Cache Toolchain
-      uses: actions/cache@v2
+      uses: actions/cache@v3
       id: cache-toolchain
       with:
         path: ~/cache/
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index b43d9e740..3a740a28a 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -36,7 +36,7 @@ jobs:
       run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2
 
     - name: Cache Toolchain
-      uses: actions/cache@v2
+      uses: actions/cache@v3
       id: cache-toolchain
       with:
         path: ~/cache/
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index d212708f7..2e272c832 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -38,7 +38,7 @@ jobs:
       run: echo >> $GITHUB_ENV TOOLCHAIN_URL=http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run
 
     - name: Cache Toolchain
-      uses: actions/cache@v2
+      uses: actions/cache@v3
       id: cache-toolchain
       with:
         path: ~/cache/
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 96b8c676b..61c1c60c5 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -39,7 +39,7 @@ jobs:
       run: echo >> $GITHUB_ENV TOOLCHAIN_URL=https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v10.1.0-1.1/xpack-riscv-none-embed-gcc-10.1.0-1.1-linux-x64.tar.gz
 
     - name: Cache Toolchain
-      uses: actions/cache@v2
+      uses: actions/cache@v3
       id: cache-toolchain
       with:
         path: ~/cache/

From fc523733c188b3afdac772e525e7309358a233d9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Nov 2022 11:16:40 +0700
Subject: [PATCH 1221/2085] more ci warnings

---
 .github/workflows/build_msp430.yml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 3a740a28a..1ef25a6a0 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -16,9 +16,12 @@ jobs:
         family:
         # Alphabetical order
         - 'msp430'
+
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
+      with:
+        python-version: '3.x'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3

From b00529e287c13197f80787f5126626b0d08c06a1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Nov 2022 21:38:03 +0700
Subject: [PATCH 1222/2085] add msc file explorer example

- add lib/fatfs version 15
- add lib/embedded-cli
---
 .../host/msc_file_explorer/CMakeLists.txt     |    43 +
 examples/host/msc_file_explorer/Makefile      |    38 +
 examples/host/msc_file_explorer/only.txt      |    11 +
 examples/host/msc_file_explorer/src/main.c    |    97 +
 examples/host/msc_file_explorer/src/msc_app.c |   171 +
 .../host/msc_file_explorer/src/tusb_config.h  |   115 +
 lib/embedded-cli/embedded_cli.h               |  1511 ++
 lib/fatfs/LICENSE.txt                         |    24 +
 lib/fatfs/source/00history.txt                |   369 +
 lib/fatfs/source/00readme.txt                 |    21 +
 lib/fatfs/source/diskio.c                     |   229 +
 lib/fatfs/source/diskio.h                     |    77 +
 lib/fatfs/source/ff.c                         |  7084 +++++++
 lib/fatfs/source/ff.h                         |   429 +
 lib/fatfs/source/ffconf.h                     |   296 +
 lib/fatfs/source/ffsystem.c                   |   208 +
 lib/fatfs/source/ffunicode.c                  | 15593 ++++++++++++++++
 17 files changed, 26316 insertions(+)
 create mode 100644 examples/host/msc_file_explorer/CMakeLists.txt
 create mode 100644 examples/host/msc_file_explorer/Makefile
 create mode 100644 examples/host/msc_file_explorer/only.txt
 create mode 100644 examples/host/msc_file_explorer/src/main.c
 create mode 100644 examples/host/msc_file_explorer/src/msc_app.c
 create mode 100644 examples/host/msc_file_explorer/src/tusb_config.h
 create mode 100644 lib/embedded-cli/embedded_cli.h
 create mode 100644 lib/fatfs/LICENSE.txt
 create mode 100644 lib/fatfs/source/00history.txt
 create mode 100644 lib/fatfs/source/00readme.txt
 create mode 100644 lib/fatfs/source/diskio.c
 create mode 100644 lib/fatfs/source/diskio.h
 create mode 100644 lib/fatfs/source/ff.c
 create mode 100644 lib/fatfs/source/ff.h
 create mode 100644 lib/fatfs/source/ffconf.h
 create mode 100644 lib/fatfs/source/ffsystem.c
 create mode 100644 lib/fatfs/source/ffunicode.c

diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
new file mode 100644
index 000000000..fc4765cdc
--- /dev/null
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -0,0 +1,43 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT})
+
+# For rp2040, un-comment to enable pico-pio-usb
+family_add_pico_pio_usb(${PROJECT})
+
+# due to warnings from Pico-PIO-USB
+target_compile_options(${PROJECT} PUBLIC
+        -Wno-error=shadow
+        -Wno-error=cast-align
+        -Wno-error=cast-qual
+        -Wno-error=redundant-decls
+        -Wno-error=sign-conversion
+        -Wno-error=conversion
+        -Wno-error=sign-compare
+        -Wno-error=unused-function
+        )
diff --git a/examples/host/msc_file_explorer/Makefile b/examples/host/msc_file_explorer/Makefile
new file mode 100644
index 000000000..518d75063
--- /dev/null
+++ b/examples/host/msc_file_explorer/Makefile
@@ -0,0 +1,38 @@
+include ../../../tools/top.mk
+include ../../make.mk
+
+FATFS_PATH = lib/fatfs/source
+
+INC += \
+	src \
+	$(TOP)/hw \
+	$(TOP)/$(FATFS_PATH) \
+	$(TOP)/lib/embedded-cli \
+
+# Example source
+EXAMPLE_SOURCE = \
+  src/main.c \
+  src/msc_app.c \
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+# FatFS source
+SRC_C += \
+  $(FATFS_PATH)/ff.c \
+  $(FATFS_PATH)/ffsystem.c \
+  $(FATFS_PATH)/ffunicode.c \
+
+# TODO: suppress warning caused by host stack
+CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
+
+# TinyUSB Host Stack source
+SRC_C += \
+	src/class/cdc/cdc_host.c \
+	src/class/hid/hid_host.c \
+	src/class/msc/msc_host.c \
+	src/host/hub.c \
+	src/host/usbh.c \
+	src/portable/ohci/ohci.c \
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+
+include ../../rules.mk
diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt
new file mode 100644
index 000000000..fa9c14857
--- /dev/null
+++ b/examples/host/msc_file_explorer/only.txt
@@ -0,0 +1,11 @@
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MIMXRT
+mcu:MIMXRT10XX
+mcu:MIMXRT11XX
+mcu:RP2040
+mcu:MSP432E4
+mcu:RX65X
diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
new file mode 100644
index 000000000..13c473d9b
--- /dev/null
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -0,0 +1,97 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+void led_blinking_task(void);
+
+extern bool msc_app_init(void);
+extern void msc_app_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  printf("TinyUSB Host CDC MSC HID Example\r\n");
+
+  // init host stack on configured roothub port
+  tuh_init(BOARD_TUH_RHPORT);
+  msc_app_init();
+
+  while (1)
+  {
+    // tinyusb host task
+    tuh_task();
+
+    msc_app_task();
+    led_blinking_task();
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+void tuh_mount_cb(uint8_t dev_addr)
+{
+  // application set-up
+  printf("A device with address %d is mounted\r\n", dev_addr);
+}
+
+void tuh_umount_cb(uint8_t dev_addr)
+{
+  // application tear-down
+  printf("A device with address %d is unmounted \r\n", dev_addr);
+}
+
+
+//--------------------------------------------------------------------+
+// Blinking Task
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  const uint32_t interval_ms = 1000;
+  static uint32_t start_ms = 0;
+
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < interval_ms) return; // not enough time
+  start_ms += interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
new file mode 100644
index 000000000..a9976be23
--- /dev/null
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -0,0 +1,171 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+#define EMBEDDED_CLI_IMPL
+#include "embedded_cli.h" // lib/embedded-cli
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+// embedded cli configuration
+#define CLI_BUFFER_SIZE     256
+#define CLI_RX_BUFFER_SIZE  16
+#define CLI_CMD_BUFFER_SIZE 32
+#define CLI_HISTORY_SIZE    32
+#define CLI_BINDING_COUNT   3
+
+static EmbeddedCli *_cli;
+static CLI_UINT cli_buffer[BYTES_TO_CLI_UINTS(CLI_BUFFER_SIZE)];
+
+static scsi_inquiry_resp_t inquiry_resp;
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+void cli_write_char(EmbeddedCli *cli, char c)
+{
+  (void) cli;
+  putchar((int) c);
+}
+
+void cli_cmd_unknown(EmbeddedCli *cli, CliCommand *command)
+{
+  (void) cli;
+  printf("Unknown commands: %s\r\n", command->name);
+}
+
+bool msc_app_init(void)
+{
+  // disable stdout buffered for echoing typing command
+  setbuf(stdout, NULL);
+
+  EmbeddedCliConfig *config = embeddedCliDefaultConfig();
+  config->cliBuffer         = cli_buffer;
+  config->cliBufferSize     = CLI_BUFFER_SIZE;
+  config->rxBufferSize      = CLI_RX_BUFFER_SIZE;
+  config->cmdBufferSize     = CLI_CMD_BUFFER_SIZE;
+  config->historyBufferSize = CLI_HISTORY_SIZE;
+  config->maxBindingCount   = CLI_BINDING_COUNT;
+
+  _cli = embeddedCliNew(config);
+  TU_ASSERT(_cli != NULL);
+
+  _cli->writeChar = cli_write_char;
+
+  return true;
+}
+
+void msc_app_task(void)
+{
+  if (!_cli) return;
+
+  int ch;
+  while( (ch = getchar()) > 0 )
+  {
+    embeddedCliReceiveChar(_cli, (char) ch);
+  }
+
+  embeddedCliProcess(_cli);
+}
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+
+bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
+{
+  if (csw->status != 0)
+  {
+    printf("Inquiry failed\r\n");
+    return false;
+  }
+
+  // Print out Vendor ID, Product ID and Rev
+  printf("%.8s %.16s rev %.4s\r\n", inquiry_resp.vendor_id, inquiry_resp.product_id, inquiry_resp.product_rev);
+
+  // Get capacity of device
+  uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
+  uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
+
+  printf("Disk Size: %lu MB\r\n", block_count / ((1024*1024)/block_size));
+  printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
+
+  return true;
+}
+
+//------------- IMPLEMENTATION -------------//
+void tuh_msc_mount_cb(uint8_t dev_addr)
+{
+  printf("A MassStorage device is mounted\r\n");
+
+  uint8_t const lun = 0;
+  tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb);
+//
+//  //------------- file system (only 1 LUN support) -------------//
+//  uint8_t phy_disk = dev_addr-1;
+//  disk_initialize(phy_disk);
+//
+//  if ( disk_is_ready(phy_disk) )
+//  {
+//    if ( f_mount(phy_disk, &fatfs[phy_disk]) != FR_OK )
+//    {
+//      puts("mount failed");
+//      return;
+//    }
+//
+//    f_chdrive(phy_disk); // change to newly mounted drive
+//    f_chdir("/"); // root as current dir
+//
+//    cli_init();
+//  }
+}
+
+void tuh_msc_umount_cb(uint8_t dev_addr)
+{
+  (void) dev_addr;
+  printf("A MassStorage device is unmounted\r\n");
+
+//  uint8_t phy_disk = dev_addr-1;
+//
+//  f_mount(phy_disk, NULL); // unmount disk
+//  disk_deinitialize(phy_disk);
+//
+//  if ( phy_disk == f_get_current_drive() )
+//  { // active drive is unplugged --> change to other drive
+//    for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
+//    {
+//      if ( disk_is_ready(i) )
+//      {
+//        f_chdrive(i);
+//        cli_init(); // refractor, rename
+//      }
+//    }
+//  }
+}
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
new file mode 100644
index 000000000..fd1215388
--- /dev/null
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -0,0 +1,115 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+#define CFG_TUH_RPI_PIO_USB   0
+#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+#endif
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#define CFG_TUH_HUB                 1 // number of supported hubs
+#define CFG_TUH_MSC                 1
+#define CFG_TUH_CDC                 0
+#define CFG_TUH_HID                 0 // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_VENDOR              0
+
+// max device support (excluding hub device)
+#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
+
+//------------- HID -------------//
+#define CFG_TUH_HID_EPIN_BUFSIZE    64
+#define CFG_TUH_HID_EPOUT_BUFSIZE   64
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/lib/embedded-cli/embedded_cli.h b/lib/embedded-cli/embedded_cli.h
new file mode 100644
index 000000000..33354cd84
--- /dev/null
+++ b/lib/embedded-cli/embedded_cli.h
@@ -0,0 +1,1511 @@
+/**
+ * This header was automatically built using
+ * embedded_cli.h and embedded_cli.c
+ * @date 2022-11-03
+ *
+ * MIT License
+ *
+ * Copyright (c) 2021 Sviatoslav Kokurin (funbiscuit)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef EMBEDDED_CLI_H
+#define EMBEDDED_CLI_H
+
+
+#ifdef __cplusplus
+
+extern "C" {
+#else
+
+#include <stdbool.h>
+
+#endif
+
+// cstdint is available only since C++11, so use C header
+#include <stdint.h>
+
+// used for proper alignment of cli buffer
+#if UINTPTR_MAX == 0xFFFF
+#define CLI_UINT uint16_t
+#elif UINTPTR_MAX == 0xFFFFFFFF
+#define CLI_UINT uint32_t
+#elif UINTPTR_MAX == 0xFFFFFFFFFFFFFFFFu
+#define CLI_UINT uint64_t
+#else
+#error unsupported pointer size
+#endif
+
+#define CLI_UINT_SIZE (sizeof(CLI_UINT))
+// convert size in bytes to size in terms of CLI_UINTs (rounded up
+// if bytes is not divisible by size of single CLI_UINT)
+#define BYTES_TO_CLI_UINTS(bytes) \
+  (((bytes) + CLI_UINT_SIZE - 1)/CLI_UINT_SIZE)
+
+typedef struct CliCommand CliCommand;
+typedef struct CliCommandBinding CliCommandBinding;
+typedef struct EmbeddedCli EmbeddedCli;
+typedef struct EmbeddedCliConfig EmbeddedCliConfig;
+
+
+struct CliCommand {
+    /**
+     * Name of the command.
+     * In command "set led 1 1" "set" is name
+     */
+    const char *name;
+
+    /**
+     * String of arguments of the command.
+     * In command "set led 1 1" "led 1 1" is string of arguments
+     * Is ended with double 0x00 char
+     * Use tokenize functions to easily get individual tokens
+     */
+    char *args;
+};
+
+/**
+ * Struct to describe binding of command to function and
+ */
+struct CliCommandBinding {
+    /**
+     * Name of command to bind. Should not be NULL.
+     */
+    const char *name;
+
+    /**
+     * Help string that will be displayed when "help <cmd>" is executed.
+     * Can have multiple lines separated with "\r\n"
+     * Can be NULL if no help is provided.
+     */
+    const char *help;
+
+    /**
+     * Flag to perform tokenization before calling binding function.
+     */
+    bool tokenizeArgs;
+
+    /**
+     * Pointer to any specific app context that is required for this binding.
+     * It will be provided in binding callback.
+     */
+    void *context;
+
+    /**
+     * Binding function for when command is received.
+     * If null, default callback (onCommand) will be called.
+     * @param cli - pointer to cli that is calling this binding
+     * @param args - string of args (if tokenizeArgs is false) or tokens otherwise
+     * @param context
+     */
+    void (*binding)(EmbeddedCli *cli, char *args, void *context);
+};
+
+struct EmbeddedCli {
+    /**
+     * Should write char to connection
+     * @param cli - pointer to cli that executed this function
+     * @param c   - actual character to write
+     */
+    void (*writeChar)(EmbeddedCli *cli, char c);
+
+    /**
+     * Called when command is received and command not found in list of
+     * command bindings (or binding function is null).
+     * @param cli     - pointer to cli that executed this function
+     * @param command - pointer to received command
+     */
+    void (*onCommand)(EmbeddedCli *cli, CliCommand *command);
+
+    /**
+     * Can be used by for any application context
+     */
+    void *appContext;
+
+    /**
+     * Pointer to actual implementation, do not use.
+     */
+    void *_impl;
+};
+
+/**
+ * Configuration to create CLI
+ */
+struct EmbeddedCliConfig {
+    /**
+     * Size of buffer that is used to store characters until they're processed
+     */
+    uint16_t rxBufferSize;
+
+    /**
+     * Size of buffer that is used to store current input that is not yet
+     * sended as command (return not pressed yet)
+     */
+    uint16_t cmdBufferSize;
+
+    /**
+     * Size of buffer that is used to store previously entered commands
+     * Only unique commands are stored in buffer. If buffer is smaller than
+     * entered command (including arguments), command is discarded from history
+     */
+    uint16_t historyBufferSize;
+
+    /**
+     * Maximum amount of bindings that can be added via addBinding function.
+     * Cli increases takes extra bindings for internal commands:
+     * - help
+     */
+    uint16_t maxBindingCount;
+
+    /**
+     * Buffer to use for cli and all internal structures. If NULL, memory will
+     * be allocated dynamically. Otherwise this buffer is used and no
+     * allocations are made
+     */
+    CLI_UINT *cliBuffer;
+
+    /**
+     * Size of buffer for cli and internal structures (in bytes).
+     */
+    uint16_t cliBufferSize;
+
+    /**
+     * Whether autocompletion should be enabled.
+     * If false, autocompletion is disabled but you still can use 'tab' to
+     * complete current command manually.
+     */
+    bool enableAutoComplete;
+};
+
+/**
+ * Returns pointer to default configuration for cli creation. It is safe to
+ * modify it and then send to embeddedCliNew().
+ * Returned structure is always the same so do not free and try to use it
+ * immediately.
+ * Default values:
+ * <ul>
+ * <li>rxBufferSize = 64</li>
+ * <li>cmdBufferSize = 64</li>
+ * <li>historyBufferSize = 128</li>
+ * <li>cliBuffer = NULL (use dynamic allocation)</li>
+ * <li>cliBufferSize = 0</li>
+ * <li>maxBindingCount = 8</li>
+ * <li>enableAutoComplete = true</li>
+ * </ul>
+ * @return configuration for cli creation
+ */
+EmbeddedCliConfig *embeddedCliDefaultConfig(void);
+
+/**
+ * Returns how many space in config buffer is required for cli creation
+ * If you provide buffer with less space, embeddedCliNew will return NULL
+ * This amount will always be divisible by CLI_UINT_SIZE so allocated buffer
+ * and internal structures can be properly aligned
+ * @param config
+ * @return
+ */
+uint16_t embeddedCliRequiredSize(EmbeddedCliConfig *config);
+
+/**
+ * Create new CLI.
+ * Memory is allocated dynamically if cliBuffer in config is NULL.
+ * After CLI is created, override function pointers to start using it
+ * @param config - config for cli creation
+ * @return pointer to created CLI
+ */
+EmbeddedCli *embeddedCliNew(EmbeddedCliConfig *config);
+
+/**
+ * Same as calling embeddedCliNew with default config.
+ * @return
+ */
+EmbeddedCli *embeddedCliNewDefault(void);
+
+/**
+ * Receive character and put it to internal buffer
+ * Actual processing is done inside embeddedCliProcess
+ * You can call this function from something like interrupt service routine,
+ * just make sure that you call it only from single place. Otherwise input
+ * might get corrupted
+ * @param cli
+ * @param c   - received char
+ */
+void embeddedCliReceiveChar(EmbeddedCli *cli, char c);
+
+/**
+ * Process rx/tx buffers. Command callbacks are called from here
+ * @param cli
+ */
+void embeddedCliProcess(EmbeddedCli *cli);
+
+/**
+ * Add specified binding to list of bindings. If list is already full, binding
+ * is not added and false is returned
+ * @param cli
+ * @param binding
+ * @return true if binding was added, false otherwise
+ */
+bool embeddedCliAddBinding(EmbeddedCli *cli, CliCommandBinding binding);
+
+/**
+ * Print specified string and account for currently entered but not submitted
+ * command.
+ * Current command is deleted, provided string is printed (with new line) after
+ * that current command is printed again, so user can continue typing it.
+ * @param cli
+ * @param string
+ */
+void embeddedCliPrint(EmbeddedCli *cli, const char *string);
+
+/**
+ * Free allocated for cli memory
+ * @param cli
+ */
+void embeddedCliFree(EmbeddedCli *cli);
+
+/**
+ * Perform tokenization of arguments string. Original string is modified and
+ * should not be used directly (only inside other token functions).
+ * Individual tokens are separated by single 0x00 char, double 0x00 is put at
+ * the end of token list. After calling this function, you can use other
+ * token functions to get individual tokens and token count.
+ *
+ * Important: Call this function only once. Otherwise information will be lost if
+ * more than one token existed
+ * @param args - string to tokenize (must have extra writable char after 0x00)
+ * @return
+ */
+void embeddedCliTokenizeArgs(char *args);
+
+/**
+ * Return specific token from tokenized string
+ * @param tokenizedStr
+ * @param pos (counted from 1)
+ * @return token
+ */
+const char *embeddedCliGetToken(const char *tokenizedStr, uint16_t pos);
+
+/**
+ * Same as embeddedCliGetToken but works on non-const buffer
+ * @param tokenizedStr
+ * @param pos (counted from 1)
+ * @return token
+ */
+char *embeddedCliGetTokenVariable(char *tokenizedStr, uint16_t pos);
+
+/**
+ * Find token in provided tokens string and return its position (counted from 1)
+ * If no such token is found - 0 is returned.
+ * @param tokenizedStr
+ * @param token - token to find
+ * @return position (increased by 1) or zero if no such token found
+ */
+uint16_t embeddedCliFindToken(const char *tokenizedStr, const char *token);
+
+/**
+ * Return number of tokens in tokenized string
+ * @param tokenizedStr
+ * @return number of tokens
+ */
+uint16_t embeddedCliGetTokenCount(const char *tokenizedStr);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif //EMBEDDED_CLI_H
+
+
+#ifdef EMBEDDED_CLI_IMPL
+#ifndef EMBEDDED_CLI_IMPL_GUARD
+#define EMBEDDED_CLI_IMPL_GUARD
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include <stdlib.h>
+#include <string.h>
+
+
+#define CLI_TOKEN_NPOS 0xffff
+
+#define UNUSED(x) (void)x
+
+#define PREPARE_IMPL(t) \
+  EmbeddedCliImpl* impl = (EmbeddedCliImpl*)t->_impl
+
+#define IS_FLAG_SET(flags, flag) (((flags) & (flag)) != 0)
+
+#define SET_FLAG(flags, flag) ((flags) |= (flag))
+
+#define UNSET_U8FLAG(flags, flag) ((flags) &= (uint8_t) ~(flag))
+
+/**
+ * Marks binding as candidate for autocompletion
+ * This flag is updated each time getAutocompletedCommand is called
+ */
+#define BINDING_FLAG_AUTOCOMPLETE 1u
+
+/**
+ * Indicates that rx buffer overflow happened. In such case last command
+ * that wasn't finished (no \r or \n were received) will be discarded
+ */
+#define CLI_FLAG_OVERFLOW 0x01u
+
+/**
+ * Indicates that initialization is completed. Initialization is completed in
+ * first call to process and needed, for example, to print invitation message.
+ */
+#define CLI_FLAG_INIT_COMPLETE 0x02u
+
+/**
+ * Indicates that CLI structure and internal structures were allocated with
+ * malloc and should bre freed
+ */
+#define CLI_FLAG_ALLOCATED 0x04u
+
+/**
+ * Indicates that CLI structure and internal structures were allocated with
+ * malloc and should bre freed
+ */
+#define CLI_FLAG_ESCAPE_MODE 0x08u
+
+/**
+ * Indicates that CLI in mode when it will print directly to output without
+ * clear of current command and printing it back
+ */
+#define CLI_FLAG_DIRECT_PRINT 0x10u
+
+/**
+ * Indicates that live autocompletion is enabled
+ */
+#define CLI_FLAG_AUTOCOMPLETE_ENABLED 0x20u
+
+typedef struct EmbeddedCliImpl EmbeddedCliImpl;
+typedef struct AutocompletedCommand AutocompletedCommand;
+typedef struct FifoBuf FifoBuf;
+typedef struct CliHistory CliHistory;
+
+struct FifoBuf {
+    char *buf;
+    /**
+     * Position of first element in buffer. From this position elements are taken
+     */
+    uint16_t front;
+    /**
+     * Position after last element. At this position new elements are inserted
+     */
+    uint16_t back;
+    /**
+     * Size of buffer
+     */
+    uint16_t size;
+};
+
+struct CliHistory {
+    /**
+     * Items in buffer are separated by null-chars
+     */
+    char *buf;
+
+    /**
+     * Total size of buffer
+     */
+    uint16_t bufferSize;
+
+    /**
+     * Index of currently selected element. This allows to navigate history
+     * After command is sent, current element is reset to 0 (no element)
+     */
+    uint16_t current;
+
+    /**
+     * Number of items in buffer
+     * Items are counted from top to bottom (and are 1 based).
+     * So the most recent item is 1 and the oldest is itemCount.
+     */
+    uint16_t itemsCount;
+};
+
+struct EmbeddedCliImpl {
+    /**
+     * Invitation string. Is printed at the beginning of each line with user
+     * input
+     */
+    const char *invitation;
+
+    CliHistory history;
+
+    /**
+     * Buffer for storing received chars.
+     * Chars are stored in FIFO mode.
+     */
+    FifoBuf rxBuffer;
+
+    /**
+     * Buffer for current command
+     */
+    char *cmdBuffer;
+
+    /**
+     * Size of current command
+     */
+    uint16_t cmdSize;
+
+    /**
+     * Total size of command buffer
+     */
+    uint16_t cmdMaxSize;
+
+    CliCommandBinding *bindings;
+
+    /**
+     * Flags for each binding. Sizes are the same as for bindings array
+     */
+    uint8_t *bindingsFlags;
+
+    uint16_t bindingsCount;
+
+    uint16_t maxBindingsCount;
+
+    /**
+     * Total length of input line. This doesn't include invitation but
+     * includes current command and its live autocompletion
+     */
+    uint16_t inputLineLength;
+
+    /**
+     * Stores last character that was processed.
+     */
+    char lastChar;
+
+    /**
+     * Flags are defined as CLI_FLAG_*
+     */
+    uint8_t flags;
+};
+
+struct AutocompletedCommand {
+    /**
+     * Name of autocompleted command (or first candidate for autocompletion if
+     * there are multiple candidates).
+     * NULL if autocomplete not possible.
+     */
+    const char *firstCandidate;
+
+    /**
+     * Number of characters that can be completed safely. For example, if there
+     * are two possible commands "get-led" and "get-adc", then for prefix "g"
+     * autocompletedLen will be 4. If there are only one candidate, this number
+     * is always equal to length of the command.
+     */
+    uint16_t autocompletedLen;
+
+    /**
+     * Total number of candidates for autocompletion
+     */
+    uint16_t candidateCount;
+};
+
+static EmbeddedCliConfig defaultConfig;
+
+/**
+ * Number of commands that cli adds. Commands:
+ * - help
+ */
+static const uint16_t cliInternalBindingCount = 1;
+
+static const char *lineBreak = "\r\n";
+
+/**
+ * Navigate through command history back and forth. If navigateUp is true,
+ * navigate to older commands, otherwise navigate to newer.
+ * When history end is reached, nothing happens.
+ * @param cli
+ * @param navigateUp
+ */
+static void navigateHistory(EmbeddedCli *cli, bool navigateUp);
+
+/**
+ * Process escaped character. After receiving ESC+[ sequence, all chars up to
+ * ending character are sent to this function
+ * @param cli
+ * @param c
+ */
+static void onEscapedInput(EmbeddedCli *cli, char c);
+
+/**
+ * Process input character. Character is valid displayable char and should be
+ * added to current command string and displayed to client.
+ * @param cli
+ * @param c
+ */
+static void onCharInput(EmbeddedCli *cli, char c);
+
+/**
+ * Process control character (like \r or \n) possibly altering state of current
+ * command or executing onCommand callback.
+ * @param cli
+ * @param c
+ */
+static void onControlInput(EmbeddedCli *cli, char c);
+
+/**
+ * Parse command in buffer and execute callback
+ * @param cli
+ */
+static void parseCommand(EmbeddedCli *cli);
+
+/**
+ * Setup bindings for internal commands, like help
+ * @param cli
+ */
+static void initInternalBindings(EmbeddedCli *cli);
+
+/**
+ * Show help for given tokens (or default help if no tokens)
+ * @param cli
+ * @param tokens
+ * @param context - not used
+ */
+static void onHelp(EmbeddedCli *cli, char *tokens, void *context);
+
+/**
+ * Show error about unknown command
+ * @param cli
+ * @param name
+ */
+static void onUnknownCommand(EmbeddedCli *cli, const char *name);
+
+/**
+ * Return autocompleted command for given prefix.
+ * Prefix is compared to all known command bindings and autocompleted result
+ * is returned
+ * @param cli
+ * @param prefix
+ * @return
+ */
+static AutocompletedCommand getAutocompletedCommand(EmbeddedCli *cli, const char *prefix);
+
+/**
+ * Prints autocompletion result while keeping current command unchanged
+ * Prints only if autocompletion is present and only one candidate exists.
+ * @param cli
+ */
+static void printLiveAutocompletion(EmbeddedCli *cli);
+
+/**
+ * Handles autocomplete request. If autocomplete possible - fills current
+ * command with autocompleted command. When multiple commands satisfy entered
+ * prefix, they are printed to output.
+ * @param cli
+ */
+static void onAutocompleteRequest(EmbeddedCli *cli);
+
+/**
+ * Removes all input from current line (replaces it with whitespaces)
+ * And places cursor at the beginning of the line
+ * @param cli
+ */
+static void clearCurrentLine(EmbeddedCli *cli);
+
+/**
+ * Write given string to cli output
+ * @param cli
+ * @param str
+ */
+static void writeToOutput(EmbeddedCli *cli, const char *str);
+
+/**
+ * Returns true if provided char is a supported control char:
+ * \r, \n, \b or 0x7F (treated as \b)
+ * @param c
+ * @return
+ */
+static bool isControlChar(char c);
+
+/**
+ * Returns true if provided char is a valid displayable character:
+ * a-z, A-Z, 0-9, whitespace, punctuation, etc.
+ * Currently only ASCII is supported
+ * @param c
+ * @return
+ */
+static bool isDisplayableChar(char c);
+
+/**
+ * How many elements are currently available in buffer
+ * @param buffer
+ * @return number of elements
+ */
+static uint16_t fifoBufAvailable(FifoBuf *buffer);
+
+/**
+ * Return first character from buffer and remove it from buffer
+ * Buffer must be non-empty, otherwise 0 is returned
+ * @param buffer
+ * @return
+ */
+static char fifoBufPop(FifoBuf *buffer);
+
+/**
+ * Push character into fifo buffer. If there is no space left, character is
+ * discarded and false is returned
+ * @param buffer
+ * @param a - character to add
+ * @return true if char was added to buffer, false otherwise
+ */
+static bool fifoBufPush(FifoBuf *buffer, char a);
+
+/**
+ * Copy provided string to the history buffer.
+ * If it is already inside history, it will be removed from it and added again.
+ * So after addition, it will always be on top
+ * If available size is not enough (and total size is enough) old elements will
+ * be removed from history so this item can be put to it
+ * @param history
+ * @param str
+ * @return true if string was put in history
+ */
+static bool historyPut(CliHistory *history, const char *str);
+
+/**
+ * Get item from history. Items are counted from 1 so if item is 0 or greater
+ * than itemCount, NULL is returned
+ * @param history
+ * @param item
+ * @return true if string was put in history
+ */
+static const char *historyGet(CliHistory *history, uint16_t item);
+
+/**
+ * Remove specific item from history
+ * @param history
+ * @param str - string to remove
+ * @return
+ */
+static void historyRemove(CliHistory *history, const char *str);
+
+/**
+ * Return position (index of first char) of specified token
+ * @param tokenizedStr - tokenized string (separated by \0 with
+ * \0\0 at the end)
+ * @param pos - token position (counted from 1)
+ * @return index of first char of specified token
+ */
+static uint16_t getTokenPosition(const char *tokenizedStr, uint16_t pos);
+
+EmbeddedCliConfig *embeddedCliDefaultConfig(void) {
+    defaultConfig.rxBufferSize = 64;
+    defaultConfig.cmdBufferSize = 64;
+    defaultConfig.historyBufferSize = 128;
+    defaultConfig.cliBuffer = NULL;
+    defaultConfig.cliBufferSize = 0;
+    defaultConfig.maxBindingCount = 8;
+    defaultConfig.enableAutoComplete = true;
+    return &defaultConfig;
+}
+
+uint16_t embeddedCliRequiredSize(EmbeddedCliConfig *config) {
+    uint16_t bindingCount = (uint16_t) (config->maxBindingCount + cliInternalBindingCount);
+    return (uint16_t) (CLI_UINT_SIZE * (
+            BYTES_TO_CLI_UINTS(sizeof(EmbeddedCli)) +
+            BYTES_TO_CLI_UINTS(sizeof(EmbeddedCliImpl)) +
+            BYTES_TO_CLI_UINTS(config->rxBufferSize * sizeof(char)) +
+            BYTES_TO_CLI_UINTS(config->cmdBufferSize * sizeof(char)) +
+            BYTES_TO_CLI_UINTS(config->historyBufferSize * sizeof(char)) +
+            BYTES_TO_CLI_UINTS(bindingCount * sizeof(CliCommandBinding)) +
+            BYTES_TO_CLI_UINTS(bindingCount * sizeof(uint8_t))));
+}
+
+EmbeddedCli *embeddedCliNew(EmbeddedCliConfig *config) {
+    EmbeddedCli *cli = NULL;
+
+    uint16_t bindingCount = (uint16_t) (config->maxBindingCount + cliInternalBindingCount);
+
+    size_t totalSize = embeddedCliRequiredSize(config);
+
+    bool allocated = false;
+    if (config->cliBuffer == NULL) {
+        config->cliBuffer = (CLI_UINT *) malloc(totalSize); // malloc guarantees alignment.
+        if (config->cliBuffer == NULL)
+            return NULL;
+        allocated = true;
+    } else if (config->cliBufferSize < totalSize) {
+        return NULL;
+    }
+
+    CLI_UINT *buf = config->cliBuffer;
+
+    memset(buf, 0, totalSize);
+
+    cli = (EmbeddedCli *) buf;
+    buf += BYTES_TO_CLI_UINTS(sizeof(EmbeddedCli));
+
+    cli->_impl = (EmbeddedCliImpl *) buf;
+    buf += BYTES_TO_CLI_UINTS(sizeof(EmbeddedCliImpl));
+
+    PREPARE_IMPL(cli);
+    impl->rxBuffer.buf = (char *) buf;
+    buf += BYTES_TO_CLI_UINTS(config->rxBufferSize * sizeof(char));
+
+    impl->cmdBuffer = (char *) buf;
+    buf += BYTES_TO_CLI_UINTS(config->cmdBufferSize * sizeof(char));
+
+    impl->bindings = (CliCommandBinding *) buf;
+    buf += BYTES_TO_CLI_UINTS(bindingCount * sizeof(CliCommandBinding));
+
+    impl->bindingsFlags = (uint8_t *) buf;
+    buf += BYTES_TO_CLI_UINTS(bindingCount);
+
+    impl->history.buf = (char *) buf;
+    impl->history.bufferSize = config->historyBufferSize;
+
+    if (allocated)
+        SET_FLAG(impl->flags, CLI_FLAG_ALLOCATED);
+
+    if (config->enableAutoComplete)
+        SET_FLAG(impl->flags, CLI_FLAG_AUTOCOMPLETE_ENABLED);
+
+    impl->rxBuffer.size = config->rxBufferSize;
+    impl->rxBuffer.front = 0;
+    impl->rxBuffer.back = 0;
+    impl->cmdMaxSize = config->cmdBufferSize;
+    impl->bindingsCount = 0;
+    impl->maxBindingsCount = (uint16_t) (config->maxBindingCount + cliInternalBindingCount);
+    impl->lastChar = '\0';
+    impl->invitation = "> ";
+
+    initInternalBindings(cli);
+
+    return cli;
+}
+
+EmbeddedCli *embeddedCliNewDefault(void) {
+    return embeddedCliNew(embeddedCliDefaultConfig());
+}
+
+void embeddedCliReceiveChar(EmbeddedCli *cli, char c) {
+    PREPARE_IMPL(cli);
+
+    if (!fifoBufPush(&impl->rxBuffer, c)) {
+        SET_FLAG(impl->flags, CLI_FLAG_OVERFLOW);
+    }
+}
+
+void embeddedCliProcess(EmbeddedCli *cli) {
+    if (cli->writeChar == NULL)
+        return;
+
+    PREPARE_IMPL(cli);
+
+
+    if (!IS_FLAG_SET(impl->flags, CLI_FLAG_INIT_COMPLETE)) {
+        SET_FLAG(impl->flags, CLI_FLAG_INIT_COMPLETE);
+        writeToOutput(cli, impl->invitation);
+    }
+
+    while (fifoBufAvailable(&impl->rxBuffer)) {
+        char c = fifoBufPop(&impl->rxBuffer);
+
+        if (IS_FLAG_SET(impl->flags, CLI_FLAG_ESCAPE_MODE)) {
+            onEscapedInput(cli, c);
+        } else if (impl->lastChar == 0x1B && c == '[') {
+            //enter escape mode
+            SET_FLAG(impl->flags, CLI_FLAG_ESCAPE_MODE);
+        } else if (isControlChar(c)) {
+            onControlInput(cli, c);
+        } else if (isDisplayableChar(c)) {
+            onCharInput(cli, c);
+        }
+
+        printLiveAutocompletion(cli);
+
+        impl->lastChar = c;
+    }
+
+    // discard unfinished command if overflow happened
+    if (IS_FLAG_SET(impl->flags, CLI_FLAG_OVERFLOW)) {
+        impl->cmdSize = 0;
+        impl->cmdBuffer[impl->cmdSize] = '\0';
+        UNSET_U8FLAG(impl->flags, CLI_FLAG_OVERFLOW);
+    }
+}
+
+bool embeddedCliAddBinding(EmbeddedCli *cli, CliCommandBinding binding) {
+    PREPARE_IMPL(cli);
+    if (impl->bindingsCount == impl->maxBindingsCount)
+        return false;
+
+    impl->bindings[impl->bindingsCount] = binding;
+
+    ++impl->bindingsCount;
+    return true;
+}
+
+void embeddedCliPrint(EmbeddedCli *cli, const char *string) {
+    if (cli->writeChar == NULL)
+        return;
+
+    PREPARE_IMPL(cli);
+
+    // remove chars for autocompletion and live command
+    if (!IS_FLAG_SET(impl->flags, CLI_FLAG_DIRECT_PRINT))
+        clearCurrentLine(cli);
+
+    // print provided string
+    writeToOutput(cli, string);
+    writeToOutput(cli, lineBreak);
+
+    // print current command back to screen
+    if (!IS_FLAG_SET(impl->flags, CLI_FLAG_DIRECT_PRINT)) {
+        writeToOutput(cli, impl->invitation);
+        writeToOutput(cli, impl->cmdBuffer);
+        impl->inputLineLength = impl->cmdSize;
+
+        printLiveAutocompletion(cli);
+    }
+}
+
+void embeddedCliFree(EmbeddedCli *cli) {
+    PREPARE_IMPL(cli);
+    if (IS_FLAG_SET(impl->flags, CLI_FLAG_ALLOCATED)) {
+        // allocation is done in single call to malloc, so need only single free
+        free(cli);
+    }
+}
+
+void embeddedCliTokenizeArgs(char *args) {
+    if (args == NULL)
+        return;
+
+    // for now only space, but can add more later
+    const char *separators = " ";
+
+    // indicates that arg is quoted so separators are copied as is
+    bool quotesEnabled = false;
+    // indicates that previous char was a slash, so next char is copied as is
+    bool escapeActivated = false;
+    int insertPos = 0;
+
+    int i = 0;
+    char currentChar;
+    while ((currentChar = args[i]) != '\0') {
+        ++i;
+
+        if (escapeActivated) {
+            escapeActivated = false;
+        } else if (currentChar == '\\') {
+            escapeActivated = true;
+            continue;
+        } else if (currentChar == '"') {
+            quotesEnabled = !quotesEnabled;
+            currentChar = '\0';
+        } else if (!quotesEnabled && strchr(separators, currentChar) != NULL) {
+            currentChar = '\0';
+        }
+
+        // null chars are only copied once and not copied to the beginning
+        if (currentChar != '\0' || (insertPos > 0 && args[insertPos - 1] != '\0')) {
+            args[insertPos] = currentChar;
+            ++insertPos;
+        }
+    }
+
+    // make args double null-terminated source buffer must be big enough to contain extra spaces
+    args[insertPos] = '\0';
+    args[insertPos + 1] = '\0';
+}
+
+const char *embeddedCliGetToken(const char *tokenizedStr, uint16_t pos) {
+    uint16_t i = getTokenPosition(tokenizedStr, pos);
+
+    if (i != CLI_TOKEN_NPOS)
+        return &tokenizedStr[i];
+    else
+        return NULL;
+}
+
+char *embeddedCliGetTokenVariable(char *tokenizedStr, uint16_t pos) {
+    uint16_t i = getTokenPosition(tokenizedStr, pos);
+
+    if (i != CLI_TOKEN_NPOS)
+        return &tokenizedStr[i];
+    else
+        return NULL;
+}
+
+uint16_t embeddedCliFindToken(const char *tokenizedStr, const char *token) {
+    if (tokenizedStr == NULL || token == NULL)
+        return 0;
+
+    uint16_t size = embeddedCliGetTokenCount(tokenizedStr);
+    for (uint16_t i = 1; i <= size; ++i) {
+        if (strcmp(embeddedCliGetToken(tokenizedStr, i), token) == 0)
+            return i;
+    }
+
+    return 0;
+}
+
+uint16_t embeddedCliGetTokenCount(const char *tokenizedStr) {
+    if (tokenizedStr == NULL || tokenizedStr[0] == '\0')
+        return 0;
+
+    int i = 0;
+    uint16_t tokenCount = 1;
+    while (true) {
+        if (tokenizedStr[i] == '\0') {
+            if (tokenizedStr[i + 1] == '\0')
+                break;
+            ++tokenCount;
+        }
+        ++i;
+    }
+
+    return tokenCount;
+}
+
+static void navigateHistory(EmbeddedCli *cli, bool navigateUp) {
+    PREPARE_IMPL(cli);
+    if (impl->history.itemsCount == 0 ||
+        (navigateUp && impl->history.current == impl->history.itemsCount) ||
+        (!navigateUp && impl->history.current == 0))
+        return;
+
+    clearCurrentLine(cli);
+
+    writeToOutput(cli, impl->invitation);
+
+    if (navigateUp)
+        ++impl->history.current;
+    else
+        --impl->history.current;
+
+    const char *item = historyGet(&impl->history, impl->history.current);
+    // simple way to handle empty command the same way as others
+    if (item == NULL)
+        item = "";
+    uint16_t len = (uint16_t) strlen(item);
+    memcpy(impl->cmdBuffer, item, len);
+    impl->cmdBuffer[len] = '\0';
+    impl->cmdSize = len;
+
+    writeToOutput(cli, impl->cmdBuffer);
+    impl->inputLineLength = impl->cmdSize;
+
+    printLiveAutocompletion(cli);
+}
+
+static void onEscapedInput(EmbeddedCli *cli, char c) {
+    PREPARE_IMPL(cli);
+
+    if (c >= 64 && c <= 126) {
+        // handle escape sequence
+        UNSET_U8FLAG(impl->flags, CLI_FLAG_ESCAPE_MODE);
+
+        if (c == 'A' || c == 'B') {
+            // treat \e[..A as cursor up and \e[..B as cursor down
+            // there might be extra chars between [ and A/B, just ignore them
+            navigateHistory(cli, c == 'A');
+        }
+    }
+}
+
+static void onCharInput(EmbeddedCli *cli, char c) {
+    PREPARE_IMPL(cli);
+
+    // have to reserve two extra chars for command ending (used in tokenization)
+    if (impl->cmdSize + 2 >= impl->cmdMaxSize)
+        return;
+
+    impl->cmdBuffer[impl->cmdSize] = c;
+    ++impl->cmdSize;
+    impl->cmdBuffer[impl->cmdSize] = '\0';
+
+    cli->writeChar(cli, c);
+}
+
+static void onControlInput(EmbeddedCli *cli, char c) {
+    PREPARE_IMPL(cli);
+
+    // process \r\n and \n\r as single \r\n command
+    if ((impl->lastChar == '\r' && c == '\n') ||
+        (impl->lastChar == '\n' && c == '\r'))
+        return;
+
+    if (c == '\r' || c == '\n') {
+        // try to autocomplete command and then process it
+        onAutocompleteRequest(cli);
+
+        writeToOutput(cli, lineBreak);
+
+        if (impl->cmdSize > 0)
+            parseCommand(cli);
+        impl->cmdSize = 0;
+        impl->cmdBuffer[impl->cmdSize] = '\0';
+        impl->inputLineLength = 0;
+        impl->history.current = 0;
+
+        writeToOutput(cli, impl->invitation);
+    } else if ((c == '\b' || c == 0x7F) && impl->cmdSize > 0) {
+        // remove char from screen
+        cli->writeChar(cli, '\b');
+        cli->writeChar(cli, ' ');
+        cli->writeChar(cli, '\b');
+        // and from buffer
+        --impl->cmdSize;
+        impl->cmdBuffer[impl->cmdSize] = '\0';
+    } else if (c == '\t') {
+        onAutocompleteRequest(cli);
+    }
+
+}
+
+static void parseCommand(EmbeddedCli *cli) {
+    PREPARE_IMPL(cli);
+
+    bool isEmpty = true;
+
+    for (int i = 0; i < impl->cmdSize; ++i) {
+        if (impl->cmdBuffer[i] != ' ') {
+            isEmpty = false;
+            break;
+        }
+    }
+    // do not process empty commands
+    if (isEmpty)
+        return;
+    // push command to history before buffer is modified
+    historyPut(&impl->history, impl->cmdBuffer);
+
+    char *cmdName = NULL;
+    char *cmdArgs = NULL;
+    bool nameFinished = false;
+
+    // find command name and command args inside command buffer
+    for (int i = 0; i < impl->cmdSize; ++i) {
+        char c = impl->cmdBuffer[i];
+
+        if (c == ' ') {
+            // all spaces between name and args are filled with zeros
+            // so name is a correct null-terminated string
+            if (cmdArgs == NULL)
+                impl->cmdBuffer[i] = '\0';
+            if (cmdName != NULL)
+                nameFinished = true;
+
+        } else if (cmdName == NULL) {
+            cmdName = &impl->cmdBuffer[i];
+        } else if (cmdArgs == NULL && nameFinished) {
+            cmdArgs = &impl->cmdBuffer[i];
+        }
+    }
+
+    // we keep two last bytes in cmd buffer reserved so cmdSize is always by 2
+    // less than cmdMaxSize
+    impl->cmdBuffer[impl->cmdSize + 1] = '\0';
+
+    if (cmdName == NULL)
+        return;
+
+    // try to find command in bindings
+    for (int i = 0; i < impl->bindingsCount; ++i) {
+        if (strcmp(cmdName, impl->bindings[i].name) == 0) {
+            if (impl->bindings[i].binding == NULL)
+                break;
+
+            if (impl->bindings[i].tokenizeArgs)
+                embeddedCliTokenizeArgs(cmdArgs);
+            // currently, output is blank line, so we can just print directly
+            SET_FLAG(impl->flags, CLI_FLAG_DIRECT_PRINT);
+            impl->bindings[i].binding(cli, cmdArgs, impl->bindings[i].context);
+            UNSET_U8FLAG(impl->flags, CLI_FLAG_DIRECT_PRINT);
+            return;
+        }
+    }
+
+    // command not found in bindings or binding was null
+    // try to call default callback
+    if (cli->onCommand != NULL) {
+        CliCommand command;
+        command.name = cmdName;
+        command.args = cmdArgs;
+
+        // currently, output is blank line, so we can just print directly
+        SET_FLAG(impl->flags, CLI_FLAG_DIRECT_PRINT);
+        cli->onCommand(cli, &command);
+        UNSET_U8FLAG(impl->flags, CLI_FLAG_DIRECT_PRINT);
+    } else {
+        onUnknownCommand(cli, cmdName);
+    }
+}
+
+static void initInternalBindings(EmbeddedCli *cli) {
+    CliCommandBinding b = {
+            "help",
+            "Print list of commands",
+            true,
+            NULL,
+            onHelp
+    };
+    embeddedCliAddBinding(cli, b);
+}
+
+static void onHelp(EmbeddedCli *cli, char *tokens, void *context) {
+    UNUSED(context);
+    PREPARE_IMPL(cli);
+
+    if (impl->bindingsCount == 0) {
+        writeToOutput(cli, "Help is not available");
+        writeToOutput(cli, lineBreak);
+        return;
+    }
+
+    uint16_t tokenCount = embeddedCliGetTokenCount(tokens);
+    if (tokenCount == 0) {
+        for (int i = 0; i < impl->bindingsCount; ++i) {
+            writeToOutput(cli, " * ");
+            writeToOutput(cli, impl->bindings[i].name);
+            writeToOutput(cli, lineBreak);
+            if (impl->bindings[i].help != NULL) {
+                cli->writeChar(cli, '\t');
+                writeToOutput(cli, impl->bindings[i].help);
+                writeToOutput(cli, lineBreak);
+            }
+        }
+    } else if (tokenCount == 1) {
+        // try find command
+        const char *helpStr = NULL;
+        const char *cmdName = embeddedCliGetToken(tokens, 1);
+        bool found = false;
+        for (int i = 0; i < impl->bindingsCount; ++i) {
+            if (strcmp(impl->bindings[i].name, cmdName) == 0) {
+                helpStr = impl->bindings[i].help;
+                found = true;
+                break;
+            }
+        }
+        if (found && helpStr != NULL) {
+            writeToOutput(cli, " * ");
+            writeToOutput(cli, cmdName);
+            writeToOutput(cli, lineBreak);
+            cli->writeChar(cli, '\t');
+            writeToOutput(cli, helpStr);
+            writeToOutput(cli, lineBreak);
+        } else if (found) {
+            writeToOutput(cli, "Help is not available");
+            writeToOutput(cli, lineBreak);
+        } else {
+            onUnknownCommand(cli, cmdName);
+        }
+    } else {
+        writeToOutput(cli, "Command \"help\" receives one or zero arguments");
+        writeToOutput(cli, lineBreak);
+    }
+}
+
+static void onUnknownCommand(EmbeddedCli *cli, const char *name) {
+    writeToOutput(cli, "Unknown command: \"");
+    writeToOutput(cli, name);
+    writeToOutput(cli, "\". Write \"help\" for a list of available commands");
+    writeToOutput(cli, lineBreak);
+}
+
+static AutocompletedCommand getAutocompletedCommand(EmbeddedCli *cli, const char *prefix) {
+    AutocompletedCommand cmd = {NULL, 0, 0};
+
+    size_t prefixLen = strlen(prefix);
+
+    PREPARE_IMPL(cli);
+    if (impl->bindingsCount == 0 || prefixLen == 0)
+        return cmd;
+
+
+    for (int i = 0; i < impl->bindingsCount; ++i) {
+        const char *name = impl->bindings[i].name;
+        size_t len = strlen(name);
+
+        // unset autocomplete flag
+        UNSET_U8FLAG(impl->bindingsFlags[i], BINDING_FLAG_AUTOCOMPLETE);
+
+        if (len < prefixLen)
+            continue;
+
+        // check if this command is candidate for autocomplete
+        bool isCandidate = true;
+        for (size_t j = 0; j < prefixLen; ++j) {
+            if (prefix[j] != name[j]) {
+                isCandidate = false;
+                break;
+            }
+        }
+        if (!isCandidate)
+            continue;
+
+        impl->bindingsFlags[i] |= BINDING_FLAG_AUTOCOMPLETE;
+
+        if (cmd.candidateCount == 0 || len < cmd.autocompletedLen)
+            cmd.autocompletedLen = (uint16_t) len;
+
+        ++cmd.candidateCount;
+
+        if (cmd.candidateCount == 1) {
+            cmd.firstCandidate = name;
+            continue;
+        }
+
+        for (size_t j = impl->cmdSize; j < cmd.autocompletedLen; ++j) {
+            if (cmd.firstCandidate[j] != name[j]) {
+                cmd.autocompletedLen = (uint16_t) j;
+                break;
+            }
+        }
+    }
+
+    return cmd;
+}
+
+static void printLiveAutocompletion(EmbeddedCli *cli) {
+    PREPARE_IMPL(cli);
+
+    if (!IS_FLAG_SET(impl->flags, CLI_FLAG_AUTOCOMPLETE_ENABLED))
+        return;
+
+    AutocompletedCommand cmd = getAutocompletedCommand(cli, impl->cmdBuffer);
+
+    if (cmd.candidateCount == 0) {
+        cmd.autocompletedLen = impl->cmdSize;
+    }
+
+    // print live autocompletion (or nothing, if it doesn't exist)
+    for (size_t i = impl->cmdSize; i < cmd.autocompletedLen; ++i) {
+        cli->writeChar(cli, cmd.firstCandidate[i]);
+    }
+    // replace with spaces previous autocompletion
+    for (size_t i = cmd.autocompletedLen; i < impl->inputLineLength; ++i) {
+        cli->writeChar(cli, ' ');
+    }
+    impl->inputLineLength = cmd.autocompletedLen;
+    cli->writeChar(cli, '\r');
+    // print current command again so cursor is moved to initial place
+    writeToOutput(cli, impl->invitation);
+    writeToOutput(cli, impl->cmdBuffer);
+}
+
+static void onAutocompleteRequest(EmbeddedCli *cli) {
+    PREPARE_IMPL(cli);
+
+    AutocompletedCommand cmd = getAutocompletedCommand(cli, impl->cmdBuffer);
+
+    if (cmd.candidateCount == 0)
+        return;
+
+    if (cmd.candidateCount == 1 || cmd.autocompletedLen > impl->cmdSize) {
+        // can copy from index cmdSize, but prefix is the same, so copy everything
+        memcpy(impl->cmdBuffer, cmd.firstCandidate, cmd.autocompletedLen);
+        if (cmd.candidateCount == 1) {
+            impl->cmdBuffer[cmd.autocompletedLen] = ' ';
+            ++cmd.autocompletedLen;
+        }
+        impl->cmdBuffer[cmd.autocompletedLen] = '\0';
+
+        writeToOutput(cli, &impl->cmdBuffer[impl->cmdSize]);
+        impl->cmdSize = cmd.autocompletedLen;
+        impl->inputLineLength = impl->cmdSize;
+        return;
+    }
+
+    // with multiple candidates when we already completed to common prefix
+    // we show all candidates and print input again
+    // we need to completely clear current line since it begins with invitation
+    clearCurrentLine(cli);
+
+    for (int i = 0; i < impl->bindingsCount; ++i) {
+        // autocomplete flag is set for all candidates by last call to
+        // getAutocompletedCommand
+        if (!(impl->bindingsFlags[i] & BINDING_FLAG_AUTOCOMPLETE))
+            continue;
+
+        const char *name = impl->bindings[i].name;
+
+        writeToOutput(cli, name);
+        writeToOutput(cli, lineBreak);
+    }
+
+    writeToOutput(cli, impl->invitation);
+    writeToOutput(cli, impl->cmdBuffer);
+
+    impl->inputLineLength = impl->cmdSize;
+}
+
+static void clearCurrentLine(EmbeddedCli *cli) {
+    PREPARE_IMPL(cli);
+    size_t len = impl->inputLineLength + strlen(impl->invitation);
+
+    cli->writeChar(cli, '\r');
+    for (size_t i = 0; i < len; ++i) {
+        cli->writeChar(cli, ' ');
+    }
+    cli->writeChar(cli, '\r');
+    impl->inputLineLength = 0;
+}
+
+static void writeToOutput(EmbeddedCli *cli, const char *str) {
+    size_t len = strlen(str);
+
+    for (size_t i = 0; i < len; ++i) {
+        cli->writeChar(cli, str[i]);
+    }
+}
+
+static bool isControlChar(char c) {
+    return c == '\r' || c == '\n' || c == '\b' || c == '\t' || c == 0x7F;
+}
+
+static bool isDisplayableChar(char c) {
+    return (c >= 32 && c <= 126);
+}
+
+static uint16_t fifoBufAvailable(FifoBuf *buffer) {
+    if (buffer->back >= buffer->front)
+        return (uint16_t) (buffer->back - buffer->front);
+    else
+        return (uint16_t) (buffer->size - buffer->front + buffer->back);
+}
+
+static char fifoBufPop(FifoBuf *buffer) {
+    char a = '\0';
+    if (buffer->front != buffer->back) {
+        a = buffer->buf[buffer->front];
+        buffer->front = (uint16_t) (buffer->front + 1) % buffer->size;
+    }
+    return a;
+}
+
+static bool fifoBufPush(FifoBuf *buffer, char a) {
+    uint16_t newBack = (uint16_t) (buffer->back + 1) % buffer->size;
+    if (newBack != buffer->front) {
+        buffer->buf[buffer->back] = a;
+        buffer->back = newBack;
+        return true;
+    }
+    return false;
+}
+
+static bool historyPut(CliHistory *history, const char *str) {
+    size_t len = strlen(str);
+    // each item is ended with \0 so, need to have that much space at least
+    if (history->bufferSize < len + 1)
+        return false;
+
+    // remove str from history (if it's present) so we don't get duplicates
+    historyRemove(history, str);
+
+    size_t usedSize;
+    // remove old items if new one can't fit into buffer
+    while (history->itemsCount > 0) {
+        const char *item = historyGet(history, history->itemsCount);
+        size_t itemLen = strlen(item);
+        usedSize = ((size_t) (item - history->buf)) + itemLen + 1;
+
+        size_t freeSpace = history->bufferSize - usedSize;
+
+        if (freeSpace >= len + 1)
+            break;
+
+        // space not enough, remove last element
+        --history->itemsCount;
+    }
+    if (history->itemsCount > 0) {
+        // when history not empty, shift elements so new item is first
+        memmove(&history->buf[len + 1], history->buf, usedSize);
+    }
+    memcpy(history->buf, str, len + 1);
+    ++history->itemsCount;
+
+    return true;
+}
+
+static const char *historyGet(CliHistory *history, uint16_t item) {
+    if (item == 0 || item > history->itemsCount)
+        return NULL;
+
+    // items are stored in the same way (separated by \0 and counted from 1),
+    // so can use this call
+    return embeddedCliGetToken(history->buf, item);
+}
+
+static void historyRemove(CliHistory *history, const char *str) {
+    if (str == NULL || history->itemsCount == 0)
+        return;
+    char *item = NULL;
+    uint16_t itemPosition;
+    for (itemPosition = 1; itemPosition <= history->itemsCount; ++itemPosition) {
+        // items are stored in the same way (separated by \0 and counted from 1),
+        // so can use this call
+        item = embeddedCliGetTokenVariable(history->buf, itemPosition);
+        if (strcmp(item, str) == 0) {
+            break;
+        }
+        item = NULL;
+    }
+    if (item == NULL)
+        return;
+
+    --history->itemsCount;
+    if (itemPosition == (history->itemsCount + 1)) {
+        // if this is a last element, nothing is remaining to move
+        return;
+    }
+
+    size_t len = strlen(item);
+    size_t remaining = (size_t) (history->bufferSize - (item + len + 1 - history->buf));
+    // move everything to the right of found item
+    memmove(item, &item[len + 1], remaining);
+}
+
+static uint16_t getTokenPosition(const char *tokenizedStr, uint16_t pos) {
+    if (tokenizedStr == NULL || pos == 0)
+        return CLI_TOKEN_NPOS;
+    uint16_t i = 0;
+    uint16_t tokenCount = 1;
+    while (true) {
+        if (tokenCount == pos)
+            break;
+
+        if (tokenizedStr[i] == '\0') {
+            ++tokenCount;
+            if (tokenizedStr[i + 1] == '\0')
+                break;
+        }
+
+        ++i;
+    }
+
+    if (tokenizedStr[i] != '\0')
+        return i;
+    else
+        return CLI_TOKEN_NPOS;
+}
+#ifdef __cplusplus
+}
+#endif
+#endif // EMBEDDED_CLI_IMPL_GUARD
+#endif // EMBEDDED_CLI_IMPL
diff --git a/lib/fatfs/LICENSE.txt b/lib/fatfs/LICENSE.txt
new file mode 100644
index 000000000..a9e57a905
--- /dev/null
+++ b/lib/fatfs/LICENSE.txt
@@ -0,0 +1,24 @@
+FatFs License
+
+FatFs has being developped as a personal project of the author, ChaN. It is free from the code anyone else wrote at current release. Following code block shows a copy of the FatFs license document that heading the source files.
+
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT Filesystem Module  Rx.xx                               /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 20xx, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/----------------------------------------------------------------------------*/
+
+Therefore FatFs license is one of the BSD-style licenses, but there is a significant feature. FatFs is mainly intended for embedded systems. In order to extend the usability for commercial products, the redistributions of FatFs in binary form, such as embedded code, binary library and any forms without source code, do not need to include about FatFs in the documentations. This is equivalent to the 1-clause BSD license. Of course FatFs is compatible with the most of open source software licenses include GNU GPL. When you redistribute the FatFs source code with changes or create a fork, the license can also be changed to GNU GPL, BSD-style license or any open source software license that not conflict with FatFs license.
diff --git a/lib/fatfs/source/00history.txt b/lib/fatfs/source/00history.txt
new file mode 100644
index 000000000..7a153a229
--- /dev/null
+++ b/lib/fatfs/source/00history.txt
@@ -0,0 +1,369 @@
+----------------------------------------------------------------------------
+  Revision history of FatFs module
+----------------------------------------------------------------------------
+
+R0.00 (February 26, 2006)
+
+  Prototype.
+
+
+
+R0.01 (April 29, 2006)
+
+  The first release.
+
+
+
+R0.02 (June 01, 2006)
+
+  Added FAT12 support.
+  Removed unbuffered mode.
+  Fixed a problem on small (<32M) partition.
+
+
+
+R0.02a (June 10, 2006)
+
+  Added a configuration option (_FS_MINIMUM).
+
+
+
+R0.03 (September 22, 2006)
+
+  Added f_rename().
+  Changed option _FS_MINIMUM to _FS_MINIMIZE.
+
+
+
+R0.03a (December 11, 2006)
+
+  Improved cluster scan algorithm to write files fast.
+  Fixed f_mkdir() creates incorrect directory on FAT32.
+
+
+
+R0.04 (February 04, 2007)
+
+  Added f_mkfs().
+  Supported multiple drive system.
+  Changed some interfaces for multiple drive system.
+  Changed f_mountdrv() to f_mount().
+
+
+
+R0.04a (April 01, 2007)
+
+  Supported multiple partitions on a physical drive.
+  Added a capability of extending file size to f_lseek().
+  Added minimization level 3.
+  Fixed an endian sensitive code in f_mkfs().
+
+
+
+R0.04b (May 05, 2007)
+
+  Added a configuration option _USE_NTFLAG.
+  Added FSINFO support.
+  Fixed DBCS name can result FR_INVALID_NAME.
+  Fixed short seek (<= csize) collapses the file object.
+
+
+
+R0.05 (August 25, 2007)
+
+  Changed arguments of f_read(), f_write() and f_mkfs().
+  Fixed f_mkfs() on FAT32 creates incorrect FSINFO.
+  Fixed f_mkdir() on FAT32 creates incorrect directory.
+
+
+
+R0.05a (February 03, 2008)
+
+  Added f_truncate() and f_utime().
+  Fixed off by one error at FAT sub-type determination.
+  Fixed btr in f_read() can be mistruncated.
+  Fixed cached sector is not flushed when create and close without write.
+
+
+
+R0.06 (April 01, 2008)
+
+  Added fputc(), fputs(), fprintf() and fgets().
+  Improved performance of f_lseek() on moving to the same or following cluster.
+
+
+
+R0.07 (April 01, 2009)
+
+  Merged Tiny-FatFs as a configuration option. (_FS_TINY)
+  Added long file name feature. (_USE_LFN)
+  Added multiple code page feature. (_CODE_PAGE)
+  Added re-entrancy for multitask operation. (_FS_REENTRANT)
+  Added auto cluster size selection to f_mkfs().
+  Added rewind option to f_readdir().
+  Changed result code of critical errors.
+  Renamed string functions to avoid name collision.
+
+
+
+R0.07a (April 14, 2009)
+
+  Septemberarated out OS dependent code on reentrant cfg.
+  Added multiple sector size feature.
+
+
+
+R0.07c (June 21, 2009)
+
+  Fixed f_unlink() can return FR_OK on error.
+  Fixed wrong cache control in f_lseek().
+  Added relative path feature.
+  Added f_chdir() and f_chdrive().
+  Added proper case conversion to extended character.
+
+
+
+R0.07e (November 03, 2009)
+
+  Septemberarated out configuration options from ff.h to ffconf.h.
+  Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH.
+  Fixed name matching error on the 13 character boundary.
+  Added a configuration option, _LFN_UNICODE.
+  Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
+
+
+
+R0.08 (May 15, 2010)
+
+  Added a memory configuration option. (_USE_LFN = 3)
+  Added file lock feature. (_FS_SHARE)
+  Added fast seek feature. (_USE_FASTSEEK)
+  Changed some types on the API, XCHAR->TCHAR.
+  Changed .fname in the FILINFO structure on Unicode cfg.
+  String functions support UTF-8 encoding files on Unicode cfg.
+
+
+
+R0.08a (August 16, 2010)
+
+  Added f_getcwd(). (_FS_RPATH = 2)
+  Added sector erase feature. (_USE_ERASE)
+  Moved file lock semaphore table from fs object to the bss.
+  Fixed f_mkfs() creates wrong FAT32 volume.
+
+
+
+R0.08b (January 15, 2011)
+
+  Fast seek feature is also applied to f_read() and f_write().
+  f_lseek() reports required table size on creating CLMP.
+  Extended format syntax of f_printf().
+  Ignores duplicated directory separators in given path name.
+
+
+
+R0.09 (September 06, 2011)
+
+  f_mkfs() supports multiple partition to complete the multiple partition feature.
+  Added f_fdisk().
+
+
+
+R0.09a (August 27, 2012)
+
+  Changed f_open() and f_opendir() reject null object pointer to avoid crash.
+  Changed option name _FS_SHARE to _FS_LOCK.
+  Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
+
+
+
+R0.09b (January 24, 2013)
+
+  Added f_setlabel() and f_getlabel().
+
+
+
+R0.10 (October 02, 2013)
+
+  Added selection of character encoding on the file. (_STRF_ENCODE)
+  Added f_closedir().
+  Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO)
+  Added forced mount feature with changes of f_mount().
+  Improved behavior of volume auto detection.
+  Improved write throughput of f_puts() and f_printf().
+  Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write().
+  Fixed f_write() can be truncated when the file size is close to 4GB.
+  Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect value on error.
+
+
+
+R0.10a (January 15, 2014)
+
+  Added arbitrary strings as drive number in the path name. (_STR_VOLUME_ID)
+  Added a configuration option of minimum sector size. (_MIN_SS)
+  2nd argument of f_rename() can have a drive number and it will be ignored.
+  Fixed f_mount() with forced mount fails when drive number is >= 1. (appeared at R0.10)
+  Fixed f_close() invalidates the file object without volume lock.
+  Fixed f_closedir() returns but the volume lock is left acquired. (appeared at R0.10)
+  Fixed creation of an entry with LFN fails on too many SFN collisions. (appeared at R0.07)
+
+
+
+R0.10b (May 19, 2014)
+
+  Fixed a hard error in the disk I/O layer can collapse the directory entry.
+  Fixed LFN entry is not deleted when delete/rename an object with lossy converted SFN. (appeared at R0.07)
+
+
+
+R0.10c (November 09, 2014)
+
+  Added a configuration option for the platforms without RTC. (_FS_NORTC)
+  Changed option name _USE_ERASE to _USE_TRIM.
+  Fixed volume label created by Mac OS X cannot be retrieved with f_getlabel(). (appeared at R0.09b)
+  Fixed a potential problem of FAT access that can appear on disk error.
+  Fixed null pointer dereference on attempting to delete the root direcotry. (appeared at R0.08)
+
+
+
+R0.11 (February 09, 2015)
+
+  Added f_findfirst(), f_findnext() and f_findclose(). (_USE_FIND)
+  Fixed f_unlink() does not remove cluster chain of the file. (appeared at R0.10c)
+  Fixed _FS_NORTC option does not work properly. (appeared at R0.10c)
+
+
+
+R0.11a (September 05, 2015)
+
+  Fixed wrong media change can lead a deadlock at thread-safe configuration.
+  Added code page 771, 860, 861, 863, 864, 865 and 869. (_CODE_PAGE)
+  Removed some code pages actually not exist on the standard systems. (_CODE_PAGE)
+  Fixed errors in the case conversion teble of code page 437 and 850 (ff.c).
+  Fixed errors in the case conversion teble of Unicode (cc*.c).
+
+
+
+R0.12 (April 12, 2016)
+
+  Added support for exFAT file system. (_FS_EXFAT)
+  Added f_expand(). (_USE_EXPAND)
+  Changed some members in FINFO structure and behavior of f_readdir().
+  Added an option _USE_CHMOD.
+  Removed an option _WORD_ACCESS.
+  Fixed errors in the case conversion table of Unicode (cc*.c).
+
+
+
+R0.12a (July 10, 2016)
+
+  Added support for creating exFAT volume with some changes of f_mkfs().
+  Added a file open method FA_OPEN_APPEND. An f_lseek() following f_open() is no longer needed.
+  f_forward() is available regardless of _FS_TINY.
+  Fixed f_mkfs() creates wrong volume. (appeared at R0.12)
+  Fixed wrong memory read in create_name(). (appeared at R0.12)
+  Fixed compilation fails at some configurations, _USE_FASTSEEK and _USE_FORWARD.
+
+
+
+R0.12b (September 04, 2016)
+
+  Made f_rename() be able to rename objects with the same name but case.
+  Fixed an error in the case conversion teble of code page 866. (ff.c)
+  Fixed writing data is truncated at the file offset 4GiB on the exFAT volume. (appeared at R0.12)
+  Fixed creating a file in the root directory of exFAT volume can fail. (appeared at R0.12)
+  Fixed f_mkfs() creating exFAT volume with too small cluster size can collapse unallocated memory. (appeared at R0.12)
+  Fixed wrong object name can be returned when read directory at Unicode cfg. (appeared at R0.12)
+  Fixed large file allocation/removing on the exFAT volume collapses allocation bitmap. (appeared at R0.12)
+  Fixed some internal errors in f_expand() and f_lseek(). (appeared at R0.12)
+
+
+
+R0.12c (March 04, 2017)
+
+  Improved write throughput at the fragmented file on the exFAT volume.
+  Made memory usage for exFAT be able to be reduced as decreasing _MAX_LFN.
+  Fixed successive f_getfree() can return wrong count on the FAT12/16 volume. (appeared at R0.12)
+  Fixed configuration option _VOLUMES cannot be set 10. (appeared at R0.10c)
+
+
+
+R0.13 (May 21, 2017)
+
+  Changed heading character of configuration keywords "_" to "FF_".
+  Removed ASCII-only configuration, FF_CODE_PAGE = 1. Use FF_CODE_PAGE = 437 instead.
+  Added f_setcp(), run-time code page configuration. (FF_CODE_PAGE = 0)
+  Improved cluster allocation time on stretch a deep buried cluster chain.
+  Improved processing time of f_mkdir() with large cluster size by using FF_USE_LFN = 3.
+  Improved NoFatChain flag of the fragmented file to be set after it is truncated and got contiguous.
+  Fixed archive attribute is left not set when a file on the exFAT volume is renamed. (appeared at R0.12)
+  Fixed exFAT FAT entry can be collapsed when write or lseek operation to the existing file is done. (appeared at R0.12c)
+  Fixed creating a file can fail when a new cluster allocation to the exFAT directory occures. (appeared at R0.12c)
+
+
+
+R0.13a (October 14, 2017)
+
+  Added support for UTF-8 encoding on the API. (FF_LFN_UNICODE = 2)
+  Added options for file name output buffer. (FF_LFN_BUF, FF_SFN_BUF).
+  Added dynamic memory allocation option for working buffer of f_mkfs() and f_fdisk().
+  Fixed f_fdisk() and f_mkfs() create the partition table with wrong CHS parameters. (appeared at R0.09)
+  Fixed f_unlink() can cause lost clusters at fragmented file on the exFAT volume. (appeared at R0.12c)
+  Fixed f_setlabel() rejects some valid characters for exFAT volume. (appeared at R0.12)
+
+
+
+R0.13b (April 07, 2018)
+
+  Added support for UTF-32 encoding on the API. (FF_LFN_UNICODE = 3)
+  Added support for Unix style volume ID. (FF_STR_VOLUME_ID = 2)
+  Fixed accesing any object on the exFAT root directory beyond the cluster boundary can fail. (appeared at R0.12c)
+  Fixed f_setlabel() does not reject some invalid characters. (appeared at R0.09b)
+
+
+
+R0.13c (October 14, 2018)
+  Supported stdint.h for C99 and later. (integer.h was included in ff.h)
+  Fixed reading a directory gets infinite loop when the last directory entry is not empty. (appeared at R0.12)
+  Fixed creating a sub-directory in the fragmented sub-directory on the exFAT volume collapses FAT chain of the parent directory. (appeared at R0.12)
+  Fixed f_getcwd() cause output buffer overrun when the buffer has a valid drive number. (appeared at R0.13b)
+
+
+
+R0.14 (October 14, 2019)
+  Added support for 64-bit LBA and GUID partition table (FF_LBA64 = 1)
+  Changed some API functions, f_mkfs() and f_fdisk().
+  Fixed f_open() function cannot find the file with file name in length of FF_MAX_LFN characters.
+  Fixed f_readdir() function cannot retrieve long file names in length of FF_MAX_LFN - 1 characters.
+  Fixed f_readdir() function returns file names with wrong case conversion. (appeared at R0.12)
+  Fixed f_mkfs() function can fail to create exFAT volume in the second partition. (appeared at R0.12)
+
+
+R0.14a (December 5, 2020)
+  Limited number of recursive calls in f_findnext().
+  Fixed old floppy disks formatted with MS-DOS 2.x and 3.x cannot be mounted.
+  Fixed some compiler warnings.
+
+
+
+R0.14b (April 17, 2021)
+  Made FatFs uses standard library <string.h> for copy, compare and search instead of built-in string functions.
+  Added support for long long integer and floating point to f_printf(). (FF_STRF_LLI and FF_STRF_FP)
+  Made path name parser ignore the terminating separator to allow "dir/".
+  Improved the compatibility in Unix style path name feature.
+  Fixed the file gets dead-locked when f_open() failed with some conditions. (appeared at R0.12a)
+  Fixed f_mkfs() can create wrong exFAT volume due to a timing dependent error. (appeared at R0.12)
+  Fixed code page 855 cannot be set by f_setcp().
+  Fixed some compiler warnings.
+
+
+
+R0.15 (November 6, 2022)
+  Changed user provided synchronization functions in order to completely eliminate the platform dependency from FatFs code.
+  FF_SYNC_t is removed from the configuration options.
+  Fixed a potential error in f_mount when FF_FS_REENTRANT.
+  Fixed file lock control FF_FS_LOCK is not mutal excluded when FF_FS_REENTRANT && FF_VOLUMES > 1 is true.
+  Fixed f_mkfs() creates broken exFAT volume when the size of volume is >= 2^32 sectors.
+  Fixed string functions cannot write the unicode characters not in BMP when FF_LFN_UNICODE == 2 (UTF-8).
+  Fixed a compatibility issue in identification of GPT header.
+
diff --git a/lib/fatfs/source/00readme.txt b/lib/fatfs/source/00readme.txt
new file mode 100644
index 000000000..3de3aeaa2
--- /dev/null
+++ b/lib/fatfs/source/00readme.txt
@@ -0,0 +1,21 @@
+FatFs Module Source Files R0.15
+
+
+FILES
+
+  00readme.txt   This file.
+  00history.txt  Revision history.
+  ff.c           FatFs module.
+  ffconf.h       Configuration file of FatFs module.
+  ff.h           Common include file for FatFs and application module.
+  diskio.h       Common include file for FatFs and disk I/O module.
+  diskio.c       An example of glue function to attach existing disk I/O module to FatFs.
+  ffunicode.c    Optional Unicode utility functions.
+  ffsystem.c     An example of optional O/S related functions.
+
+
+  Low level disk I/O module is not included in this archive because the FatFs
+  module is only a generic file system layer and it does not depend on any specific
+  storage device. You need to provide a low level disk I/O module written to
+  control the storage device that attached to the target system.
+
diff --git a/lib/fatfs/source/diskio.c b/lib/fatfs/source/diskio.c
new file mode 100644
index 000000000..179e387a2
--- /dev/null
+++ b/lib/fatfs/source/diskio.c
@@ -0,0 +1,229 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module SKELETON for FatFs     (C)ChaN, 2019        */
+/*-----------------------------------------------------------------------*/
+/* If a working storage control module is available, it should be        */
+/* attached to the FatFs via a glue function rather than modifying it.   */
+/* This is an example of glue functions to attach various exsisting      */
+/* storage control modules to the FatFs module with a defined API.       */
+/*-----------------------------------------------------------------------*/
+
+#include "ff.h"			/* Obtains integer types */
+#include "diskio.h"		/* Declarations of disk functions */
+
+/* Definitions of physical drive number for each drive */
+#define DEV_RAM		0	/* Example: Map Ramdisk to physical drive 0 */
+#define DEV_MMC		1	/* Example: Map MMC/SD card to physical drive 1 */
+#define DEV_USB		2	/* Example: Map USB MSD to physical drive 2 */
+
+
+/*-----------------------------------------------------------------------*/
+/* Get Drive Status                                                      */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_status (
+	BYTE pdrv		/* Physical drive nmuber to identify the drive */
+)
+{
+	DSTATUS stat;
+	int result;
+
+	switch (pdrv) {
+	case DEV_RAM :
+		result = RAM_disk_status();
+
+		// translate the reslut code here
+
+		return stat;
+
+	case DEV_MMC :
+		result = MMC_disk_status();
+
+		// translate the reslut code here
+
+		return stat;
+
+	case DEV_USB :
+		result = USB_disk_status();
+
+		// translate the reslut code here
+
+		return stat;
+	}
+	return STA_NOINIT;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Inidialize a Drive                                                    */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (
+	BYTE pdrv				/* Physical drive nmuber to identify the drive */
+)
+{
+	DSTATUS stat;
+	int result;
+
+	switch (pdrv) {
+	case DEV_RAM :
+		result = RAM_disk_initialize();
+
+		// translate the reslut code here
+
+		return stat;
+
+	case DEV_MMC :
+		result = MMC_disk_initialize();
+
+		// translate the reslut code here
+
+		return stat;
+
+	case DEV_USB :
+		result = USB_disk_initialize();
+
+		// translate the reslut code here
+
+		return stat;
+	}
+	return STA_NOINIT;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Sector(s)                                                        */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_read (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	BYTE *buff,		/* Data buffer to store read data */
+	LBA_t sector,	/* Start sector in LBA */
+	UINT count		/* Number of sectors to read */
+)
+{
+	DRESULT res;
+	int result;
+
+	switch (pdrv) {
+	case DEV_RAM :
+		// translate the arguments here
+
+		result = RAM_disk_read(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+
+	case DEV_MMC :
+		// translate the arguments here
+
+		result = MMC_disk_read(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+
+	case DEV_USB :
+		// translate the arguments here
+
+		result = USB_disk_read(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+	}
+
+	return RES_PARERR;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Sector(s)                                                       */
+/*-----------------------------------------------------------------------*/
+
+#if FF_FS_READONLY == 0
+
+DRESULT disk_write (
+	BYTE pdrv,			/* Physical drive nmuber to identify the drive */
+	const BYTE *buff,	/* Data to be written */
+	LBA_t sector,		/* Start sector in LBA */
+	UINT count			/* Number of sectors to write */
+)
+{
+	DRESULT res;
+	int result;
+
+	switch (pdrv) {
+	case DEV_RAM :
+		// translate the arguments here
+
+		result = RAM_disk_write(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+
+	case DEV_MMC :
+		// translate the arguments here
+
+		result = MMC_disk_write(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+
+	case DEV_USB :
+		// translate the arguments here
+
+		result = USB_disk_write(buff, sector, count);
+
+		// translate the reslut code here
+
+		return res;
+	}
+
+	return RES_PARERR;
+}
+
+#endif
+
+
+/*-----------------------------------------------------------------------*/
+/* Miscellaneous Functions                                               */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_ioctl (
+	BYTE pdrv,		/* Physical drive nmuber (0..) */
+	BYTE cmd,		/* Control code */
+	void *buff		/* Buffer to send/receive control data */
+)
+{
+	DRESULT res;
+	int result;
+
+	switch (pdrv) {
+	case DEV_RAM :
+
+		// Process of the command for the RAM drive
+
+		return res;
+
+	case DEV_MMC :
+
+		// Process of the command for the MMC/SD card
+
+		return res;
+
+	case DEV_USB :
+
+		// Process of the command the USB drive
+
+		return res;
+	}
+
+	return RES_PARERR;
+}
+
diff --git a/lib/fatfs/source/diskio.h b/lib/fatfs/source/diskio.h
new file mode 100644
index 000000000..e4ead7838
--- /dev/null
+++ b/lib/fatfs/source/diskio.h
@@ -0,0 +1,77 @@
+/*-----------------------------------------------------------------------/
+/  Low level disk interface modlue include file   (C)ChaN, 2019          /
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO_DEFINED
+#define _DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Successful */
+	RES_ERROR,		/* 1: R/W Error */
+	RES_WRPRT,		/* 2: Write Protected */
+	RES_NOTRDY,		/* 3: Not Ready */
+	RES_PARERR		/* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+#define STA_PROTECT		0x04	/* Write protected */
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (Used by FatFs) */
+#define CTRL_SYNC			0	/* Complete pending write process (needed at FF_FS_READONLY == 0) */
+#define GET_SECTOR_COUNT	1	/* Get media size (needed at FF_USE_MKFS == 1) */
+#define GET_SECTOR_SIZE		2	/* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
+#define GET_BLOCK_SIZE		3	/* Get erase block size (needed at FF_USE_MKFS == 1) */
+#define CTRL_TRIM			4	/* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
+
+/* Generic command (Not used by FatFs) */
+#define CTRL_POWER			5	/* Get/Set power status */
+#define CTRL_LOCK			6	/* Lock/Unlock media removal */
+#define CTRL_EJECT			7	/* Eject media */
+#define CTRL_FORMAT			8	/* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE		10	/* Get card type */
+#define MMC_GET_CSD			11	/* Get CSD */
+#define MMC_GET_CID			12	/* Get CID */
+#define MMC_GET_OCR			13	/* Get OCR */
+#define MMC_GET_SDSTAT		14	/* Get SD status */
+#define ISDIO_READ			55	/* Read data form SD iSDIO register */
+#define ISDIO_WRITE			56	/* Write data to SD iSDIO register */
+#define ISDIO_MRITE			57	/* Masked write data to SD iSDIO register */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV			20	/* Get F/W revision */
+#define ATA_GET_MODEL		21	/* Get model name */
+#define ATA_GET_SN			22	/* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/lib/fatfs/source/ff.c b/lib/fatfs/source/ff.c
new file mode 100644
index 000000000..6d412fa0e
--- /dev/null
+++ b/lib/fatfs/source/ff.c
@@ -0,0 +1,7084 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT Filesystem Module  R0.15 w/patch1                      /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2022, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/
+/----------------------------------------------------------------------------*/
+
+
+#include <string.h>
+#include "ff.h"			/* Declarations of FatFs API */
+#include "diskio.h"		/* Declarations of device I/O functions */
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if FF_DEFINED != 80286	/* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+
+/* Limits and boundaries */
+#define MAX_DIR		0x200000		/* Max size of FAT directory */
+#define MAX_DIR_EX	0x10000000		/* Max size of exFAT directory */
+#define MAX_FAT12	0xFF5			/* Max FAT12 clusters (differs from specs, but right for real DOS/Windows behavior) */
+#define MAX_FAT16	0xFFF5			/* Max FAT16 clusters (differs from specs, but right for real DOS/Windows behavior) */
+#define MAX_FAT32	0x0FFFFFF5		/* Max FAT32 clusters (not specified, practical limit) */
+#define MAX_EXFAT	0x7FFFFFFD		/* Max exFAT clusters (differs from specs, implementation limit) */
+
+
+/* Character code support macros */
+#define IsUpper(c)		((c) >= 'A' && (c) <= 'Z')
+#define IsLower(c)		((c) >= 'a' && (c) <= 'z')
+#define IsDigit(c)		((c) >= '0' && (c) <= '9')
+#define IsSeparator(c)	((c) == '/' || (c) == '\\')
+#define IsTerminator(c)	((UINT)(c) < (FF_USE_LFN ? ' ' : '!'))
+#define IsSurrogate(c)	((c) >= 0xD800 && (c) <= 0xDFFF)
+#define IsSurrogateH(c)	((c) >= 0xD800 && (c) <= 0xDBFF)
+#define IsSurrogateL(c)	((c) >= 0xDC00 && (c) <= 0xDFFF)
+
+
+/* Additional file access control and file status flags for internal use */
+#define FA_SEEKEND	0x20	/* Seek to end of the file on file open */
+#define FA_MODIFIED	0x40	/* File has been modified */
+#define FA_DIRTY	0x80	/* FIL.buf[] needs to be written-back */
+
+
+/* Additional file attribute bits for internal use */
+#define AM_VOL		0x08	/* Volume label */
+#define AM_LFN		0x0F	/* LFN entry */
+#define AM_MASK		0x3F	/* Mask of defined bits in FAT */
+#define AM_MASKX	0x37	/* Mask of defined bits in exFAT */
+
+
+/* Name status flags in fn[11] */
+#define NSFLAG		11		/* Index of the name status byte */
+#define NS_LOSS		0x01	/* Out of 8.3 format */
+#define NS_LFN		0x02	/* Force to create LFN entry */
+#define NS_LAST		0x04	/* Last segment */
+#define NS_BODY		0x08	/* Lower case flag (body) */
+#define NS_EXT		0x10	/* Lower case flag (ext) */
+#define NS_DOT		0x20	/* Dot entry */
+#define NS_NOLFN	0x40	/* Do not find LFN */
+#define NS_NONAME	0x80	/* Not followed */
+
+
+/* exFAT directory entry types */
+#define	ET_BITMAP	0x81	/* Allocation bitmap */
+#define	ET_UPCASE	0x82	/* Up-case table */
+#define	ET_VLABEL	0x83	/* Volume label */
+#define	ET_FILEDIR	0x85	/* File and directory */
+#define	ET_STREAM	0xC0	/* Stream extension */
+#define	ET_FILENAME	0xC1	/* Name extension */
+
+
+/* FatFs refers the FAT structure as simple byte array instead of structure member
+/ because the C structure is not binary compatible between different platforms */
+
+#define BS_JmpBoot			0		/* x86 jump instruction (3-byte) */
+#define BS_OEMName			3		/* OEM name (8-byte) */
+#define BPB_BytsPerSec		11		/* Sector size [byte] (WORD) */
+#define BPB_SecPerClus		13		/* Cluster size [sector] (BYTE) */
+#define BPB_RsvdSecCnt		14		/* Size of reserved area [sector] (WORD) */
+#define BPB_NumFATs			16		/* Number of FATs (BYTE) */
+#define BPB_RootEntCnt		17		/* Size of root directory area for FAT [entry] (WORD) */
+#define BPB_TotSec16		19		/* Volume size (16-bit) [sector] (WORD) */
+#define BPB_Media			21		/* Media descriptor byte (BYTE) */
+#define BPB_FATSz16			22		/* FAT size (16-bit) [sector] (WORD) */
+#define BPB_SecPerTrk		24		/* Number of sectors per track for int13h [sector] (WORD) */
+#define BPB_NumHeads		26		/* Number of heads for int13h (WORD) */
+#define BPB_HiddSec			28		/* Volume offset from top of the drive (DWORD) */
+#define BPB_TotSec32		32		/* Volume size (32-bit) [sector] (DWORD) */
+#define BS_DrvNum			36		/* Physical drive number for int13h (BYTE) */
+#define BS_NTres			37		/* WindowsNT error flag (BYTE) */
+#define BS_BootSig			38		/* Extended boot signature (BYTE) */
+#define BS_VolID			39		/* Volume serial number (DWORD) */
+#define BS_VolLab			43		/* Volume label string (8-byte) */
+#define BS_FilSysType		54		/* Filesystem type string (8-byte) */
+#define BS_BootCode			62		/* Boot code (448-byte) */
+#define BS_55AA				510		/* Signature word (WORD) */
+
+#define BPB_FATSz32			36		/* FAT32: FAT size [sector] (DWORD) */
+#define BPB_ExtFlags32		40		/* FAT32: Extended flags (WORD) */
+#define BPB_FSVer32			42		/* FAT32: Filesystem version (WORD) */
+#define BPB_RootClus32		44		/* FAT32: Root directory cluster (DWORD) */
+#define BPB_FSInfo32		48		/* FAT32: Offset of FSINFO sector (WORD) */
+#define BPB_BkBootSec32		50		/* FAT32: Offset of backup boot sector (WORD) */
+#define BS_DrvNum32			64		/* FAT32: Physical drive number for int13h (BYTE) */
+#define BS_NTres32			65		/* FAT32: Error flag (BYTE) */
+#define BS_BootSig32		66		/* FAT32: Extended boot signature (BYTE) */
+#define BS_VolID32			67		/* FAT32: Volume serial number (DWORD) */
+#define BS_VolLab32			71		/* FAT32: Volume label string (8-byte) */
+#define BS_FilSysType32		82		/* FAT32: Filesystem type string (8-byte) */
+#define BS_BootCode32		90		/* FAT32: Boot code (420-byte) */
+
+#define BPB_ZeroedEx		11		/* exFAT: MBZ field (53-byte) */
+#define BPB_VolOfsEx		64		/* exFAT: Volume offset from top of the drive [sector] (QWORD) */
+#define BPB_TotSecEx		72		/* exFAT: Volume size [sector] (QWORD) */
+#define BPB_FatOfsEx		80		/* exFAT: FAT offset from top of the volume [sector] (DWORD) */
+#define BPB_FatSzEx			84		/* exFAT: FAT size [sector] (DWORD) */
+#define BPB_DataOfsEx		88		/* exFAT: Data offset from top of the volume [sector] (DWORD) */
+#define BPB_NumClusEx		92		/* exFAT: Number of clusters (DWORD) */
+#define BPB_RootClusEx		96		/* exFAT: Root directory start cluster (DWORD) */
+#define BPB_VolIDEx			100		/* exFAT: Volume serial number (DWORD) */
+#define BPB_FSVerEx			104		/* exFAT: Filesystem version (WORD) */
+#define BPB_VolFlagEx		106		/* exFAT: Volume flags (WORD) */
+#define BPB_BytsPerSecEx	108		/* exFAT: Log2 of sector size in unit of byte (BYTE) */
+#define BPB_SecPerClusEx	109		/* exFAT: Log2 of cluster size in unit of sector (BYTE) */
+#define BPB_NumFATsEx		110		/* exFAT: Number of FATs (BYTE) */
+#define BPB_DrvNumEx		111		/* exFAT: Physical drive number for int13h (BYTE) */
+#define BPB_PercInUseEx		112		/* exFAT: Percent in use (BYTE) */
+#define BPB_RsvdEx			113		/* exFAT: Reserved (7-byte) */
+#define BS_BootCodeEx		120		/* exFAT: Boot code (390-byte) */
+
+#define DIR_Name			0		/* Short file name (11-byte) */
+#define DIR_Attr			11		/* Attribute (BYTE) */
+#define DIR_NTres			12		/* Lower case flag (BYTE) */
+#define DIR_CrtTime10		13		/* Created time sub-second (BYTE) */
+#define DIR_CrtTime			14		/* Created time (DWORD) */
+#define DIR_LstAccDate		18		/* Last accessed date (WORD) */
+#define DIR_FstClusHI		20		/* Higher 16-bit of first cluster (WORD) */
+#define DIR_ModTime			22		/* Modified time (DWORD) */
+#define DIR_FstClusLO		26		/* Lower 16-bit of first cluster (WORD) */
+#define DIR_FileSize		28		/* File size (DWORD) */
+#define LDIR_Ord			0		/* LFN: LFN order and LLE flag (BYTE) */
+#define LDIR_Attr			11		/* LFN: LFN attribute (BYTE) */
+#define LDIR_Type			12		/* LFN: Entry type (BYTE) */
+#define LDIR_Chksum			13		/* LFN: Checksum of the SFN (BYTE) */
+#define LDIR_FstClusLO		26		/* LFN: MBZ field (WORD) */
+#define XDIR_Type			0		/* exFAT: Type of exFAT directory entry (BYTE) */
+#define XDIR_NumLabel		1		/* exFAT: Number of volume label characters (BYTE) */
+#define XDIR_Label			2		/* exFAT: Volume label (11-WORD) */
+#define XDIR_CaseSum		4		/* exFAT: Sum of case conversion table (DWORD) */
+#define XDIR_NumSec			1		/* exFAT: Number of secondary entries (BYTE) */
+#define XDIR_SetSum			2		/* exFAT: Sum of the set of directory entries (WORD) */
+#define XDIR_Attr			4		/* exFAT: File attribute (WORD) */
+#define XDIR_CrtTime		8		/* exFAT: Created time (DWORD) */
+#define XDIR_ModTime		12		/* exFAT: Modified time (DWORD) */
+#define XDIR_AccTime		16		/* exFAT: Last accessed time (DWORD) */
+#define XDIR_CrtTime10		20		/* exFAT: Created time subsecond (BYTE) */
+#define XDIR_ModTime10		21		/* exFAT: Modified time subsecond (BYTE) */
+#define XDIR_CrtTZ			22		/* exFAT: Created timezone (BYTE) */
+#define XDIR_ModTZ			23		/* exFAT: Modified timezone (BYTE) */
+#define XDIR_AccTZ			24		/* exFAT: Last accessed timezone (BYTE) */
+#define XDIR_GenFlags		33		/* exFAT: General secondary flags (BYTE) */
+#define XDIR_NumName		35		/* exFAT: Number of file name characters (BYTE) */
+#define XDIR_NameHash		36		/* exFAT: Hash of file name (WORD) */
+#define XDIR_ValidFileSize	40		/* exFAT: Valid file size (QWORD) */
+#define XDIR_FstClus		52		/* exFAT: First cluster of the file data (DWORD) */
+#define XDIR_FileSize		56		/* exFAT: File/Directory size (QWORD) */
+
+#define SZDIRE				32		/* Size of a directory entry */
+#define DDEM				0xE5	/* Deleted directory entry mark set to DIR_Name[0] */
+#define RDDEM				0x05	/* Replacement of the character collides with DDEM */
+#define LLEF				0x40	/* Last long entry flag in LDIR_Ord */
+
+#define FSI_LeadSig			0		/* FAT32 FSI: Leading signature (DWORD) */
+#define FSI_StrucSig		484		/* FAT32 FSI: Structure signature (DWORD) */
+#define FSI_Free_Count		488		/* FAT32 FSI: Number of free clusters (DWORD) */
+#define FSI_Nxt_Free		492		/* FAT32 FSI: Last allocated cluster (DWORD) */
+
+#define MBR_Table			446		/* MBR: Offset of partition table in the MBR */
+#define SZ_PTE				16		/* MBR: Size of a partition table entry */
+#define PTE_Boot			0		/* MBR PTE: Boot indicator */
+#define PTE_StHead			1		/* MBR PTE: Start head */
+#define PTE_StSec			2		/* MBR PTE: Start sector */
+#define PTE_StCyl			3		/* MBR PTE: Start cylinder */
+#define PTE_System			4		/* MBR PTE: System ID */
+#define PTE_EdHead			5		/* MBR PTE: End head */
+#define PTE_EdSec			6		/* MBR PTE: End sector */
+#define PTE_EdCyl			7		/* MBR PTE: End cylinder */
+#define PTE_StLba			8		/* MBR PTE: Start in LBA */
+#define PTE_SizLba			12		/* MBR PTE: Size in LBA */
+
+#define GPTH_Sign			0		/* GPT HDR: Signature (8-byte) */
+#define GPTH_Rev			8		/* GPT HDR: Revision (DWORD) */
+#define GPTH_Size			12		/* GPT HDR: Header size (DWORD) */
+#define GPTH_Bcc			16		/* GPT HDR: Header BCC (DWORD) */
+#define GPTH_CurLba			24		/* GPT HDR: This header LBA (QWORD) */
+#define GPTH_BakLba			32		/* GPT HDR: Another header LBA (QWORD) */
+#define GPTH_FstLba			40		/* GPT HDR: First LBA for partition data (QWORD) */
+#define GPTH_LstLba			48		/* GPT HDR: Last LBA for partition data (QWORD) */
+#define GPTH_DskGuid		56		/* GPT HDR: Disk GUID (16-byte) */
+#define GPTH_PtOfs			72		/* GPT HDR: Partition table LBA (QWORD) */
+#define GPTH_PtNum			80		/* GPT HDR: Number of table entries (DWORD) */
+#define GPTH_PteSize		84		/* GPT HDR: Size of table entry (DWORD) */
+#define GPTH_PtBcc			88		/* GPT HDR: Partition table BCC (DWORD) */
+#define SZ_GPTE				128		/* GPT PTE: Size of partition table entry */
+#define GPTE_PtGuid			0		/* GPT PTE: Partition type GUID (16-byte) */
+#define GPTE_UpGuid			16		/* GPT PTE: Partition unique GUID (16-byte) */
+#define GPTE_FstLba			32		/* GPT PTE: First LBA of partition (QWORD) */
+#define GPTE_LstLba			40		/* GPT PTE: Last LBA of partition (QWORD) */
+#define GPTE_Flags			48		/* GPT PTE: Partition flags (QWORD) */
+#define GPTE_Name			56		/* GPT PTE: Partition name */
+
+
+/* Post process on fatal error in the file operations */
+#define ABORT(fs, res)		{ fp->err = (BYTE)(res); LEAVE_FF(fs, res); }
+
+
+/* Re-entrancy related */
+#if FF_FS_REENTRANT
+#if FF_USE_LFN == 1
+#error Static LFN work area cannot be used in thread-safe configuration
+#endif
+#define LEAVE_FF(fs, res)	{ unlock_volume(fs, res); return res; }
+#else
+#define LEAVE_FF(fs, res)	return res
+#endif
+
+
+/* Definitions of logical drive - physical location conversion */
+#if FF_MULTI_PARTITION
+#define LD2PD(vol) VolToPart[vol].pd	/* Get physical drive number */
+#define LD2PT(vol) VolToPart[vol].pt	/* Get partition number (0:auto search, 1..:forced partition number) */
+#else
+#define LD2PD(vol) (BYTE)(vol)	/* Each logical drive is associated with the same physical drive number */
+#define LD2PT(vol) 0			/* Auto partition search */
+#endif
+
+
+/* Definitions of sector size */
+#if (FF_MAX_SS < FF_MIN_SS) || (FF_MAX_SS != 512 && FF_MAX_SS != 1024 && FF_MAX_SS != 2048 && FF_MAX_SS != 4096) || (FF_MIN_SS != 512 && FF_MIN_SS != 1024 && FF_MIN_SS != 2048 && FF_MIN_SS != 4096)
+#error Wrong sector size configuration
+#endif
+#if FF_MAX_SS == FF_MIN_SS
+#define SS(fs)	((UINT)FF_MAX_SS)	/* Fixed sector size */
+#else
+#define SS(fs)	((fs)->ssize)	/* Variable sector size */
+#endif
+
+
+/* Timestamp */
+#if FF_FS_NORTC == 1
+#if FF_NORTC_YEAR < 1980 || FF_NORTC_YEAR > 2107 || FF_NORTC_MON < 1 || FF_NORTC_MON > 12 || FF_NORTC_MDAY < 1 || FF_NORTC_MDAY > 31
+#error Invalid FF_FS_NORTC settings
+#endif
+#define GET_FATTIME()	((DWORD)(FF_NORTC_YEAR - 1980) << 25 | (DWORD)FF_NORTC_MON << 21 | (DWORD)FF_NORTC_MDAY << 16)
+#else
+#define GET_FATTIME()	get_fattime()
+#endif
+
+
+/* File lock controls */
+#if FF_FS_LOCK
+#if FF_FS_READONLY
+#error FF_FS_LOCK must be 0 at read-only configuration
+#endif
+typedef struct {
+	FATFS* fs;		/* Object ID 1, volume (NULL:blank entry) */
+	DWORD clu;		/* Object ID 2, containing directory (0:root) */
+	DWORD ofs;		/* Object ID 3, offset in the directory */
+	UINT ctr;		/* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+/* SBCS up-case tables (\x80-\xFF) */
+#define TBL_CT437  {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+					0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT720  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT737  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+					0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xEF,0xF5,0xF0,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT771  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDC,0xDE,0xDE, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFE,0xFF}
+#define TBL_CT775  {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F, \
+					0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+					0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT850  {0x43,0x55,0x45,0x41,0x41,0x41,0x41,0x43,0x45,0x45,0x45,0x49,0x49,0x49,0x41,0x41, \
+					0x45,0x92,0x92,0x4F,0x4F,0x4F,0x55,0x55,0x59,0x4F,0x55,0x4F,0x9C,0x4F,0x9E,0x9F, \
+					0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0x41,0x41,0x41,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0x41,0x41,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD1,0xD1,0x45,0x45,0x45,0x49,0x49,0x49,0x49,0xD9,0xDA,0xDB,0xDC,0xDD,0x49,0xDF, \
+					0x4F,0xE1,0x4F,0x4F,0x4F,0x4F,0xE6,0xE8,0xE8,0x55,0x55,0x55,0x59,0x59,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT852  {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0xAC, \
+					0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+#define TBL_CT855  {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F, \
+					0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+					0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+					0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF, \
+					0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT857  {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x49,0x8E,0x8F, \
+					0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+					0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0x49,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT860  {0x80,0x9A,0x90,0x8F,0x8E,0x91,0x86,0x80,0x89,0x89,0x92,0x8B,0x8C,0x98,0x8E,0x8F, \
+					0x90,0x91,0x92,0x8C,0x99,0xA9,0x96,0x9D,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x86,0x8B,0x9F,0x96,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT861  {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x8B,0x8B,0x8D,0x8E,0x8F, \
+					0x90,0x92,0x92,0x4F,0x99,0x8D,0x55,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+					0xA4,0xA5,0xA6,0xA7,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT862  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT863  {0x43,0x55,0x45,0x41,0x41,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x41,0x8F, \
+					0x45,0x45,0x45,0x4F,0x45,0x49,0x55,0x55,0x98,0x4F,0x55,0x9B,0x9C,0x55,0x55,0x9F, \
+					0xA0,0xA1,0x4F,0x55,0xA4,0xA5,0xA6,0xA7,0x49,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT864  {0x80,0x9A,0x45,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+					0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT865  {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F, \
+					0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF, \
+					0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT866  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+					0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+#define TBL_CT869  {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F, \
+					0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x86,0x9C,0x8D,0x8F,0x90, \
+					0x91,0x90,0x92,0x95,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF, \
+					0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+					0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF, \
+					0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xA4,0xA5,0xA6,0xD9,0xDA,0xDB,0xDC,0xA7,0xA8,0xDF, \
+					0xA9,0xAA,0xAC,0xAD,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xCF,0xCF,0xD0,0xEF, \
+					0xF0,0xF1,0xD1,0xD2,0xD3,0xF5,0xD4,0xF7,0xF8,0xF9,0xD5,0x96,0x95,0x98,0xFE,0xFF}
+
+
+/* DBCS code range |----- 1st byte -----|  |----------- 2nd byte -----------| */
+/*                  <------>    <------>    <------>    <------>    <------>  */
+#define TBL_DC932 {0x81, 0x9F, 0xE0, 0xFC, 0x40, 0x7E, 0x80, 0xFC, 0x00, 0x00}
+#define TBL_DC936 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0x80, 0xFE, 0x00, 0x00}
+#define TBL_DC949 {0x81, 0xFE, 0x00, 0x00, 0x41, 0x5A, 0x61, 0x7A, 0x81, 0xFE}
+#define TBL_DC950 {0x81, 0xFE, 0x00, 0x00, 0x40, 0x7E, 0xA1, 0xFE, 0x00, 0x00}
+
+
+/* Macros for table definitions */
+#define MERGE_2STR(a, b) a ## b
+#define MKCVTBL(hd, cp) MERGE_2STR(hd, cp)
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Work Area
+
+---------------------------------------------------------------------------*/
+/* Remark: Variables defined here without initial value shall be guaranteed
+/  zero/null at start-up. If not, the linker option or start-up routine is
+/  not compliance with C standard. */
+
+/*--------------------------------*/
+/* File/Volume controls           */
+/*--------------------------------*/
+
+#if FF_VOLUMES < 1 || FF_VOLUMES > 10
+#error Wrong FF_VOLUMES setting
+#endif
+static FATFS *FatFs[FF_VOLUMES];	/* Pointer to the filesystem objects (logical drives) */
+static WORD Fsid;					/* Filesystem mount ID */
+
+#if FF_FS_RPATH != 0
+static BYTE CurrVol;				/* Current drive set by f_chdrive() */
+#endif
+
+#if FF_FS_LOCK != 0
+static FILESEM Files[FF_FS_LOCK];	/* Open object lock semaphores */
+#if FF_FS_REENTRANT
+static BYTE SysLock;				/* System lock flag (0:no mutex, 1:unlocked, 2:locked) */
+#endif
+#endif
+
+#if FF_STR_VOLUME_ID
+#ifdef FF_VOLUME_STRS
+static const char *const VolumeStr[FF_VOLUMES] = {FF_VOLUME_STRS};	/* Pre-defined volume ID */
+#endif
+#endif
+
+#if FF_LBA64
+#if FF_MIN_GPT > 0x100000000
+#error Wrong FF_MIN_GPT setting
+#endif
+static const BYTE GUID_MS_Basic[16] = {0xA2,0xA0,0xD0,0xEB,0xE5,0xB9,0x33,0x44,0x87,0xC0,0x68,0xB6,0xB7,0x26,0x99,0xC7};
+#endif
+
+
+
+/*--------------------------------*/
+/* LFN/Directory working buffer   */
+/*--------------------------------*/
+
+#if FF_USE_LFN == 0		/* Non-LFN configuration */
+#if FF_FS_EXFAT
+#error LFN must be enabled when enable exFAT
+#endif
+#define DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define FREE_NAMBUF()
+#define LEAVE_MKFS(res)	return res
+
+#else					/* LFN configurations */
+#if FF_MAX_LFN < 12 || FF_MAX_LFN > 255
+#error Wrong setting of FF_MAX_LFN
+#endif
+#if FF_LFN_BUF < FF_SFN_BUF || FF_SFN_BUF < 12
+#error Wrong setting of FF_LFN_BUF or FF_SFN_BUF
+#endif
+#if FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3
+#error Wrong setting of FF_LFN_UNICODE
+#endif
+static const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};	/* FAT: Offset of LFN characters in the directory entry */
+#define MAXDIRB(nc)	((nc + 44U) / 15 * SZDIRE)	/* exFAT: Size of directory entry block scratchpad buffer needed for the name length */
+
+#if FF_USE_LFN == 1		/* LFN enabled with static working buffer */
+#if FF_FS_EXFAT
+static BYTE	DirBuf[MAXDIRB(FF_MAX_LFN)];	/* Directory entry block scratchpad buffer */
+#endif
+static WCHAR LfnBuf[FF_MAX_LFN + 1];		/* LFN working buffer */
+#define DEF_NAMBUF
+#define INIT_NAMBUF(fs)
+#define FREE_NAMBUF()
+#define LEAVE_MKFS(res)	return res
+
+#elif FF_USE_LFN == 2 	/* LFN enabled with dynamic working buffer on the stack */
+#if FF_FS_EXFAT
+#define DEF_NAMBUF		WCHAR lbuf[FF_MAX_LFN+1]; BYTE dbuf[MAXDIRB(FF_MAX_LFN)];	/* LFN working buffer and directory entry block scratchpad buffer */
+#define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; (fs)->dirbuf = dbuf; }
+#define FREE_NAMBUF()
+#else
+#define DEF_NAMBUF		WCHAR lbuf[FF_MAX_LFN+1];	/* LFN working buffer */
+#define INIT_NAMBUF(fs)	{ (fs)->lfnbuf = lbuf; }
+#define FREE_NAMBUF()
+#endif
+#define LEAVE_MKFS(res)	return res
+
+#elif FF_USE_LFN == 3 	/* LFN enabled with dynamic working buffer on the heap */
+#if FF_FS_EXFAT
+#define DEF_NAMBUF		WCHAR *lfn;	/* Pointer to LFN working buffer and directory entry block scratchpad buffer */
+#define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((FF_MAX_LFN+1)*2 + MAXDIRB(FF_MAX_LFN)); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; (fs)->dirbuf = (BYTE*)(lfn+FF_MAX_LFN+1); }
+#define FREE_NAMBUF()	ff_memfree(lfn)
+#else
+#define DEF_NAMBUF		WCHAR *lfn;	/* Pointer to LFN working buffer */
+#define INIT_NAMBUF(fs)	{ lfn = ff_memalloc((FF_MAX_LFN+1)*2); if (!lfn) LEAVE_FF(fs, FR_NOT_ENOUGH_CORE); (fs)->lfnbuf = lfn; }
+#define FREE_NAMBUF()	ff_memfree(lfn)
+#endif
+#define LEAVE_MKFS(res)	{ if (!work) ff_memfree(buf); return res; }
+#define MAX_MALLOC	0x8000	/* Must be >=FF_MAX_SS */
+
+#else
+#error Wrong setting of FF_USE_LFN
+
+#endif	/* FF_USE_LFN == 1 */
+#endif	/* FF_USE_LFN == 0 */
+
+
+
+/*--------------------------------*/
+/* Code conversion tables         */
+/*--------------------------------*/
+
+#if FF_CODE_PAGE == 0	/* Run-time code page configuration */
+#define CODEPAGE CodePage
+static WORD CodePage;	/* Current code page */
+static const BYTE* ExCvt;	/* Ptr to SBCS up-case table Ct???[] (null:not used) */
+static const BYTE* DbcTbl;	/* Ptr to DBCS code range table Dc???[] (null:not used) */
+
+static const BYTE Ct437[] = TBL_CT437;
+static const BYTE Ct720[] = TBL_CT720;
+static const BYTE Ct737[] = TBL_CT737;
+static const BYTE Ct771[] = TBL_CT771;
+static const BYTE Ct775[] = TBL_CT775;
+static const BYTE Ct850[] = TBL_CT850;
+static const BYTE Ct852[] = TBL_CT852;
+static const BYTE Ct855[] = TBL_CT855;
+static const BYTE Ct857[] = TBL_CT857;
+static const BYTE Ct860[] = TBL_CT860;
+static const BYTE Ct861[] = TBL_CT861;
+static const BYTE Ct862[] = TBL_CT862;
+static const BYTE Ct863[] = TBL_CT863;
+static const BYTE Ct864[] = TBL_CT864;
+static const BYTE Ct865[] = TBL_CT865;
+static const BYTE Ct866[] = TBL_CT866;
+static const BYTE Ct869[] = TBL_CT869;
+static const BYTE Dc932[] = TBL_DC932;
+static const BYTE Dc936[] = TBL_DC936;
+static const BYTE Dc949[] = TBL_DC949;
+static const BYTE Dc950[] = TBL_DC950;
+
+#elif FF_CODE_PAGE < 900	/* Static code page configuration (SBCS) */
+#define CODEPAGE FF_CODE_PAGE
+static const BYTE ExCvt[] = MKCVTBL(TBL_CT, FF_CODE_PAGE);
+
+#else					/* Static code page configuration (DBCS) */
+#define CODEPAGE FF_CODE_PAGE
+static const BYTE DbcTbl[] = MKCVTBL(TBL_DC, FF_CODE_PAGE);
+
+#endif
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* Load/Store multi-byte word in the FAT structure                       */
+/*-----------------------------------------------------------------------*/
+
+static WORD ld_word (const BYTE* ptr)	/*	 Load a 2-byte little-endian word */
+{
+	WORD rv;
+
+	rv = ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+
+static DWORD ld_dword (const BYTE* ptr)	/* Load a 4-byte little-endian word */
+{
+	DWORD rv;
+
+	rv = ptr[3];
+	rv = rv << 8 | ptr[2];
+	rv = rv << 8 | ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+
+#if FF_FS_EXFAT
+static QWORD ld_qword (const BYTE* ptr)	/* Load an 8-byte little-endian word */
+{
+	QWORD rv;
+
+	rv = ptr[7];
+	rv = rv << 8 | ptr[6];
+	rv = rv << 8 | ptr[5];
+	rv = rv << 8 | ptr[4];
+	rv = rv << 8 | ptr[3];
+	rv = rv << 8 | ptr[2];
+	rv = rv << 8 | ptr[1];
+	rv = rv << 8 | ptr[0];
+	return rv;
+}
+#endif
+
+#if !FF_FS_READONLY
+static void st_word (BYTE* ptr, WORD val)	/* Store a 2-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+
+static void st_dword (BYTE* ptr, DWORD val)	/* Store a 4-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+
+#if FF_FS_EXFAT
+static void st_qword (BYTE* ptr, QWORD val)	/* Store an 8-byte word in little-endian */
+{
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val; val >>= 8;
+	*ptr++ = (BYTE)val;
+}
+#endif
+#endif	/* !FF_FS_READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions                                                      */
+/*-----------------------------------------------------------------------*/
+
+/* Test if the byte is DBC 1st byte */
+static int dbc_1st (BYTE c)
+{
+#if FF_CODE_PAGE == 0		/* Variable code page */
+	if (DbcTbl && c >= DbcTbl[0]) {
+		if (c <= DbcTbl[1]) return 1;					/* 1st byte range 1 */
+		if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1;	/* 1st byte range 2 */
+	}
+#elif FF_CODE_PAGE >= 900	/* DBCS fixed code page */
+	if (c >= DbcTbl[0]) {
+		if (c <= DbcTbl[1]) return 1;
+		if (c >= DbcTbl[2] && c <= DbcTbl[3]) return 1;
+	}
+#else						/* SBCS fixed code page */
+	if (c != 0) return 0;	/* Always false */
+#endif
+	return 0;
+}
+
+
+/* Test if the byte is DBC 2nd byte */
+static int dbc_2nd (BYTE c)
+{
+#if FF_CODE_PAGE == 0		/* Variable code page */
+	if (DbcTbl && c >= DbcTbl[4]) {
+		if (c <= DbcTbl[5]) return 1;					/* 2nd byte range 1 */
+		if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1;	/* 2nd byte range 2 */
+		if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1;	/* 2nd byte range 3 */
+	}
+#elif FF_CODE_PAGE >= 900	/* DBCS fixed code page */
+	if (c >= DbcTbl[4]) {
+		if (c <= DbcTbl[5]) return 1;
+		if (c >= DbcTbl[6] && c <= DbcTbl[7]) return 1;
+		if (c >= DbcTbl[8] && c <= DbcTbl[9]) return 1;
+	}
+#else						/* SBCS fixed code page */
+	if (c != 0) return 0;	/* Always false */
+#endif
+	return 0;
+}
+
+
+#if FF_USE_LFN
+
+/* Get a Unicode code point from the TCHAR string in defined API encodeing */
+static DWORD tchar2uni (	/* Returns a character in UTF-16 encoding (>=0x10000 on surrogate pair, 0xFFFFFFFF on decode error) */
+	const TCHAR** str		/* Pointer to pointer to TCHAR string in configured encoding */
+)
+{
+	DWORD uc;
+	const TCHAR *p = *str;
+
+#if FF_LFN_UNICODE == 1		/* UTF-16 input */
+	WCHAR wc;
+
+	uc = *p++;	/* Get a unit */
+	if (IsSurrogate(uc)) {	/* Surrogate? */
+		wc = *p++;		/* Get low surrogate */
+		if (!IsSurrogateH(uc) || !IsSurrogateL(wc)) return 0xFFFFFFFF;	/* Wrong surrogate? */
+		uc = uc << 16 | wc;
+	}
+
+#elif FF_LFN_UNICODE == 2	/* UTF-8 input */
+	BYTE b;
+	int nf;
+
+	uc = (BYTE)*p++;	/* Get an encoding unit */
+	if (uc & 0x80) {	/* Multiple byte code? */
+		if        ((uc & 0xE0) == 0xC0) {	/* 2-byte sequence? */
+			uc &= 0x1F; nf = 1;
+		} else if ((uc & 0xF0) == 0xE0) {	/* 3-byte sequence? */
+			uc &= 0x0F; nf = 2;
+		} else if ((uc & 0xF8) == 0xF0) {	/* 4-byte sequence? */
+			uc &= 0x07; nf = 3;
+		} else {							/* Wrong sequence */
+			return 0xFFFFFFFF;
+		}
+		do {	/* Get trailing bytes */
+			b = (BYTE)*p++;
+			if ((b & 0xC0) != 0x80) return 0xFFFFFFFF;	/* Wrong sequence? */
+			uc = uc << 6 | (b & 0x3F);
+		} while (--nf != 0);
+		if (uc < 0x80 || IsSurrogate(uc) || uc >= 0x110000) return 0xFFFFFFFF;	/* Wrong code? */
+		if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF);	/* Make a surrogate pair if needed */
+	}
+
+#elif FF_LFN_UNICODE == 3	/* UTF-32 input */
+	uc = (TCHAR)*p++;	/* Get a unit */
+	if (uc >= 0x110000 || IsSurrogate(uc)) return 0xFFFFFFFF;	/* Wrong code? */
+	if (uc >= 0x010000) uc = 0xD800DC00 | ((uc - 0x10000) << 6 & 0x3FF0000) | (uc & 0x3FF);	/* Make a surrogate pair if needed */
+
+#else		/* ANSI/OEM input */
+	BYTE b;
+	WCHAR wc;
+
+	wc = (BYTE)*p++;			/* Get a byte */
+	if (dbc_1st((BYTE)wc)) {	/* Is it a DBC 1st byte? */
+		b = (BYTE)*p++;			/* Get 2nd byte */
+		if (!dbc_2nd(b)) return 0xFFFFFFFF;	/* Invalid code? */
+		wc = (wc << 8) + b;		/* Make a DBC */
+	}
+	if (wc != 0) {
+		wc = ff_oem2uni(wc, CODEPAGE);	/* ANSI/OEM ==> Unicode */
+		if (wc == 0) return 0xFFFFFFFF;	/* Invalid code? */
+	}
+	uc = wc;
+
+#endif
+	*str = p;	/* Next read pointer */
+	return uc;
+}
+
+
+/* Store a Unicode char in defined API encoding */
+static UINT put_utf (	/* Returns number of encoding units written (0:buffer overflow or wrong encoding) */
+	DWORD chr,	/* UTF-16 encoded character (Surrogate pair if >=0x10000) */
+	TCHAR* buf,	/* Output buffer */
+	UINT szb	/* Size of the buffer */
+)
+{
+#if FF_LFN_UNICODE == 1	/* UTF-16 output */
+	WCHAR hs, wc;
+
+	hs = (WCHAR)(chr >> 16);
+	wc = (WCHAR)chr;
+	if (hs == 0) {	/* Single encoding unit? */
+		if (szb < 1 || IsSurrogate(wc)) return 0;	/* Buffer overflow or wrong code? */
+		*buf = wc;
+		return 1;
+	}
+	if (szb < 2 || !IsSurrogateH(hs) || !IsSurrogateL(wc)) return 0;	/* Buffer overflow or wrong surrogate? */
+	*buf++ = hs;
+	*buf++ = wc;
+	return 2;
+
+#elif FF_LFN_UNICODE == 2	/* UTF-8 output */
+	DWORD hc;
+
+	if (chr < 0x80) {	/* Single byte code? */
+		if (szb < 1) return 0;	/* Buffer overflow? */
+		*buf = (TCHAR)chr;
+		return 1;
+	}
+	if (chr < 0x800) {	/* 2-byte sequence? */
+		if (szb < 2) return 0;	/* Buffer overflow? */
+		*buf++ = (TCHAR)(0xC0 | (chr >> 6 & 0x1F));
+		*buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
+		return 2;
+	}
+	if (chr < 0x10000) {	/* 3-byte sequence? */
+		if (szb < 3 || IsSurrogate(chr)) return 0;	/* Buffer overflow or wrong code? */
+		*buf++ = (TCHAR)(0xE0 | (chr >> 12 & 0x0F));
+		*buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F));
+		*buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
+		return 3;
+	}
+	/* 4-byte sequence */
+	if (szb < 4) return 0;	/* Buffer overflow? */
+	hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6;	/* Get high 10 bits */
+	chr = (chr & 0xFFFF) - 0xDC00;					/* Get low 10 bits */
+	if (hc >= 0x100000 || chr >= 0x400) return 0;	/* Wrong surrogate? */
+	chr = (hc | chr) + 0x10000;
+	*buf++ = (TCHAR)(0xF0 | (chr >> 18 & 0x07));
+	*buf++ = (TCHAR)(0x80 | (chr >> 12 & 0x3F));
+	*buf++ = (TCHAR)(0x80 | (chr >> 6 & 0x3F));
+	*buf++ = (TCHAR)(0x80 | (chr >> 0 & 0x3F));
+	return 4;
+
+#elif FF_LFN_UNICODE == 3	/* UTF-32 output */
+	DWORD hc;
+
+	if (szb < 1) return 0;	/* Buffer overflow? */
+	if (chr >= 0x10000) {	/* Out of BMP? */
+		hc = ((chr & 0xFFFF0000) - 0xD8000000) >> 6;	/* Get high 10 bits */
+		chr = (chr & 0xFFFF) - 0xDC00;					/* Get low 10 bits */
+		if (hc >= 0x100000 || chr >= 0x400) return 0;	/* Wrong surrogate? */
+		chr = (hc | chr) + 0x10000;
+	}
+	*buf++ = (TCHAR)chr;
+	return 1;
+
+#else						/* ANSI/OEM output */
+	WCHAR wc;
+
+	wc = ff_uni2oem(chr, CODEPAGE);
+	if (wc >= 0x100) {	/* Is this a DBC? */
+		if (szb < 2) return 0;
+		*buf++ = (char)(wc >> 8);	/* Store DBC 1st byte */
+		*buf++ = (TCHAR)wc;			/* Store DBC 2nd byte */
+		return 2;
+	}
+	if (wc == 0 || szb < 1) return 0;	/* Invalid char or buffer overflow? */
+	*buf++ = (TCHAR)wc;					/* Store the character */
+	return 1;
+#endif
+}
+#endif	/* FF_USE_LFN */
+
+
+#if FF_FS_REENTRANT
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume                            */
+/*-----------------------------------------------------------------------*/
+
+static int lock_volume (	/* 1:Ok, 0:timeout */
+	FATFS* fs,				/* Filesystem object to lock */
+	int syslock				/* System lock required */
+)
+{
+	int rv;
+
+
+#if FF_FS_LOCK
+	rv = ff_mutex_take(fs->ldrv);	/* Lock the volume */
+	if (rv && syslock) {			/* System lock reqiered? */
+		rv = ff_mutex_take(FF_VOLUMES);	/* Lock the system */
+		if (rv) {
+			SysLock = 2;				/* System lock succeeded */
+		} else {
+			ff_mutex_give(fs->ldrv);	/* Failed system lock */
+		}
+	}
+#else
+	rv = syslock ? ff_mutex_take(fs->ldrv) : ff_mutex_take(fs->ldrv);	/* Lock the volume (this is to prevent compiler warning) */
+#endif
+	return rv;
+}
+
+
+static void unlock_volume (
+	FATFS* fs,		/* Filesystem object */
+	FRESULT res		/* Result code to be returned */
+)
+{
+	if (fs && res != FR_NOT_ENABLED && res != FR_INVALID_DRIVE && res != FR_TIMEOUT) {
+#if FF_FS_LOCK
+		if (SysLock == 2) {	/* Is the system locked? */
+			SysLock = 1;
+			ff_mutex_give(FF_VOLUMES);
+		}
+#endif
+		ff_mutex_give(fs->ldrv);	/* Unlock the volume */
+	}
+}
+
+#endif
+
+
+
+#if FF_FS_LOCK
+/*-----------------------------------------------------------------------*/
+/* File shareing control functions                                       */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT chk_share (	/* Check if the file can be accessed */
+	DIR* dp,		/* Directory object pointing the file to be checked */
+	int acc			/* Desired access type (0:Read mode open, 1:Write mode open, 2:Delete or rename) */
+)
+{
+	UINT i, be;
+
+	/* Search open object table for the object */
+	be = 0;
+	for (i = 0; i < FF_FS_LOCK; i++) {
+		if (Files[i].fs) {	/* Existing entry */
+			if (Files[i].fs == dp->obj.fs &&	 	/* Check if the object matches with an open object */
+				Files[i].clu == dp->obj.sclust &&
+				Files[i].ofs == dp->dptr) break;
+		} else {			/* Blank entry */
+			be = 1;
+		}
+	}
+	if (i == FF_FS_LOCK) {	/* The object has not been opened */
+		return (!be && acc != 2) ? FR_TOO_MANY_OPEN_FILES : FR_OK;	/* Is there a blank entry for new object? */
+	}
+
+	/* The object was opened. Reject any open against writing file and all write mode open */
+	return (acc != 0 || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static int enq_share (void)	/* Check if an entry is available for a new object */
+{
+	UINT i;
+
+	for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ;	/* Find a free entry */
+	return (i == FF_FS_LOCK) ? 0 : 1;
+}
+
+
+static UINT inc_share (	/* Increment object open counter and returns its index (0:Internal error) */
+	DIR* dp,	/* Directory object pointing the file to register or increment */
+	int acc		/* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+	UINT i;
+
+
+	for (i = 0; i < FF_FS_LOCK; i++) {	/* Find the object */
+		if (Files[i].fs == dp->obj.fs
+		 && Files[i].clu == dp->obj.sclust
+		 && Files[i].ofs == dp->dptr) break;
+	}
+
+	if (i == FF_FS_LOCK) {			/* Not opened. Register it as new. */
+		for (i = 0; i < FF_FS_LOCK && Files[i].fs; i++) ;	/* Find a free entry */
+		if (i == FF_FS_LOCK) return 0;	/* No free entry to register (int err) */
+		Files[i].fs = dp->obj.fs;
+		Files[i].clu = dp->obj.sclust;
+		Files[i].ofs = dp->dptr;
+		Files[i].ctr = 0;
+	}
+
+	if (acc >= 1 && Files[i].ctr) return 0;	/* Access violation (int err) */
+
+	Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1;	/* Set semaphore value */
+
+	return i + 1;	/* Index number origin from 1 */
+}
+
+
+static FRESULT dec_share (	/* Decrement object open counter */
+	UINT i			/* Semaphore index (1..) */
+)
+{
+	UINT n;
+	FRESULT res;
+
+
+	if (--i < FF_FS_LOCK) {	/* Index number origin from 0 */
+		n = Files[i].ctr;
+		if (n == 0x100) n = 0;	/* If write mode open, delete the object semaphore */
+		if (n > 0) n--;			/* Decrement read mode open count */
+		Files[i].ctr = n;
+		if (n == 0) {			/* Delete the object semaphore if open count becomes zero */
+			Files[i].fs = 0;	/* Free the entry <<<If this memory write operation is not in atomic, FF_FS_REENTRANT == 1 and FF_VOLUMES > 1, there is a potential error in this process >>> */
+		}
+		res = FR_OK;
+	} else {
+		res = FR_INT_ERR;		/* Invalid index number */
+	}
+	return res;
+}
+
+
+static void clear_share (	/* Clear all lock entries of the volume */
+	FATFS* fs
+)
+{
+	UINT i;
+
+	for (i = 0; i < FF_FS_LOCK; i++) {
+		if (Files[i].fs == fs) Files[i].fs = 0;
+	}
+}
+
+#endif	/* FF_FS_LOCK */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Move/Flush disk access window in the filesystem object                */
+/*-----------------------------------------------------------------------*/
+#if !FF_FS_READONLY
+static FRESULT sync_window (	/* Returns FR_OK or FR_DISK_ERR */
+	FATFS* fs			/* Filesystem object */
+)
+{
+	FRESULT res = FR_OK;
+
+
+	if (fs->wflag) {	/* Is the disk access window dirty? */
+		if (disk_write(fs->pdrv, fs->win, fs->winsect, 1) == RES_OK) {	/* Write it back into the volume */
+			fs->wflag = 0;	/* Clear window dirty flag */
+			if (fs->winsect - fs->fatbase < fs->fsize) {	/* Is it in the 1st FAT? */
+				if (fs->n_fats == 2) disk_write(fs->pdrv, fs->win, fs->winsect + fs->fsize, 1);	/* Reflect it to 2nd FAT if needed */
+			}
+		} else {
+			res = FR_DISK_ERR;
+		}
+	}
+	return res;
+}
+#endif
+
+
+static FRESULT move_window (	/* Returns FR_OK or FR_DISK_ERR */
+	FATFS* fs,		/* Filesystem object */
+	LBA_t sect		/* Sector LBA to make appearance in the fs->win[] */
+)
+{
+	FRESULT res = FR_OK;
+
+
+	if (sect != fs->winsect) {	/* Window offset changed? */
+#if !FF_FS_READONLY
+		res = sync_window(fs);		/* Flush the window */
+#endif
+		if (res == FR_OK) {			/* Fill sector window with new data */
+			if (disk_read(fs->pdrv, fs->win, sect, 1) != RES_OK) {
+				sect = (LBA_t)0 - 1;	/* Invalidate window if read data is not valid */
+				res = FR_DISK_ERR;
+			}
+			fs->winsect = sect;
+		}
+	}
+	return res;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Synchronize filesystem and data on the storage                        */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT sync_fs (	/* Returns FR_OK or FR_DISK_ERR */
+	FATFS* fs		/* Filesystem object */
+)
+{
+	FRESULT res;
+
+
+	res = sync_window(fs);
+	if (res == FR_OK) {
+		if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) {	/* FAT32: Update FSInfo sector if needed */
+			/* Create FSInfo structure */
+			memset(fs->win, 0, sizeof fs->win);
+			st_word(fs->win + BS_55AA, 0xAA55);					/* Boot signature */
+			st_dword(fs->win + FSI_LeadSig, 0x41615252);		/* Leading signature */
+			st_dword(fs->win + FSI_StrucSig, 0x61417272);		/* Structure signature */
+			st_dword(fs->win + FSI_Free_Count, fs->free_clst);	/* Number of free clusters */
+			st_dword(fs->win + FSI_Nxt_Free, fs->last_clst);	/* Last allocated culuster */
+			fs->winsect = fs->volbase + 1;						/* Write it into the FSInfo sector (Next to VBR) */
+			disk_write(fs->pdrv, fs->win, fs->winsect, 1);
+			fs->fsi_flag = 0;
+		}
+		/* Make sure that no pending write process in the lower layer */
+		if (disk_ioctl(fs->pdrv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR;
+	}
+
+	return res;
+}
+
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get physical sector number from cluster number                        */
+/*-----------------------------------------------------------------------*/
+
+static LBA_t clst2sect (	/* !=0:Sector number, 0:Failed (invalid cluster#) */
+	FATFS* fs,		/* Filesystem object */
+	DWORD clst		/* Cluster# to be converted */
+)
+{
+	clst -= 2;		/* Cluster number is origin from 2 */
+	if (clst >= fs->n_fatent - 2) return 0;		/* Is it invalid cluster number? */
+	return fs->database + (LBA_t)fs->csize * clst;	/* Start sector number of the cluster */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of an FAT entry                               */
+/*-----------------------------------------------------------------------*/
+
+static DWORD get_fat (		/* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */
+	FFOBJID* obj,	/* Corresponding object */
+	DWORD clst		/* Cluster number to get the value */
+)
+{
+	UINT wc, bc;
+	DWORD val;
+	FATFS *fs = obj->fs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent) {	/* Check if in valid range */
+		val = 1;	/* Internal error */
+
+	} else {
+		val = 0xFFFFFFFF;	/* Default value falls on disk error */
+
+		switch (fs->fs_type) {
+		case FS_FAT12 :
+			bc = (UINT)clst; bc += bc / 2;
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc = fs->win[bc++ % SS(fs)];		/* Get 1st byte of the entry */
+			if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
+			wc |= fs->win[bc % SS(fs)] << 8;	/* Merge 2nd byte of the entry */
+			val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);	/* Adjust bit position */
+			break;
+
+		case FS_FAT16 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
+			val = ld_word(fs->win + clst * 2 % SS(fs));		/* Simple WORD array */
+			break;
+
+		case FS_FAT32 :
+			if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+			val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;	/* Simple DWORD array but mask out upper 4 bits */
+			break;
+#if FF_FS_EXFAT
+		case FS_EXFAT :
+			if ((obj->objsize != 0 && obj->sclust != 0) || obj->stat == 0) {	/* Object except root dir must have valid data length */
+				DWORD cofs = clst - obj->sclust;	/* Offset from start cluster */
+				DWORD clen = (DWORD)((LBA_t)((obj->objsize - 1) / SS(fs)) / fs->csize);	/* Number of clusters - 1 */
+
+				if (obj->stat == 2 && cofs <= clen) {	/* Is it a contiguous chain? */
+					val = (cofs == clen) ? 0x7FFFFFFF : clst + 1;	/* No data on the FAT, generate the value */
+					break;
+				}
+				if (obj->stat == 3 && cofs < obj->n_cont) {	/* Is it in the 1st fragment? */
+					val = clst + 1; 	/* Generate the value */
+					break;
+				}
+				if (obj->stat != 2) {	/* Get value from FAT if FAT chain is valid */
+					if (obj->n_frag != 0) {	/* Is it on the growing edge? */
+						val = 0x7FFFFFFF;	/* Generate EOC */
+					} else {
+						if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
+						val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x7FFFFFFF;
+					}
+					break;
+				}
+			}
+			val = 1;	/* Internal error */
+			break;
+#endif
+		default:
+			val = 1;	/* Internal error */
+		}
+	}
+
+	return val;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of an FAT entry                             */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT put_fat (	/* FR_OK(0):succeeded, !=0:error */
+	FATFS* fs,		/* Corresponding filesystem object */
+	DWORD clst,		/* FAT index number (cluster number) to be changed */
+	DWORD val		/* New value to be set to the entry */
+)
+{
+	UINT bc;
+	BYTE *p;
+	FRESULT res = FR_INT_ERR;
+
+
+	if (clst >= 2 && clst < fs->n_fatent) {	/* Check if in valid range */
+		switch (fs->fs_type) {
+		case FS_FAT12:
+			bc = (UINT)clst; bc += bc / 2;	/* bc: byte offset of the entry */
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = fs->win + bc++ % SS(fs);
+			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;	/* Update 1st byte */
+			fs->wflag = 1;
+			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+			if (res != FR_OK) break;
+			p = fs->win + bc % SS(fs);
+			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));	/* Update 2nd byte */
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT16:
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+			if (res != FR_OK) break;
+			st_word(fs->win + clst * 2 % SS(fs), (WORD)val);	/* Simple WORD array */
+			fs->wflag = 1;
+			break;
+
+		case FS_FAT32:
+#if FF_FS_EXFAT
+		case FS_EXFAT:
+#endif
+			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+			if (res != FR_OK) break;
+			if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+				val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000);
+			}
+			st_dword(fs->win + clst * 4 % SS(fs), val);
+			fs->wflag = 1;
+			break;
+		}
+	}
+	return res;
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+
+#if FF_FS_EXFAT && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* exFAT: Accessing FAT and Allocation Bitmap                            */
+/*-----------------------------------------------------------------------*/
+
+/*--------------------------------------*/
+/* Find a contiguous free cluster block */
+/*--------------------------------------*/
+
+static DWORD find_bitmap (	/* 0:Not found, 2..:Cluster block found, 0xFFFFFFFF:Disk error */
+	FATFS* fs,	/* Filesystem object */
+	DWORD clst,	/* Cluster number to scan from */
+	DWORD ncl	/* Number of contiguous clusters to find (1..) */
+)
+{
+	BYTE bm, bv;
+	UINT i;
+	DWORD val, scl, ctr;
+
+
+	clst -= 2;	/* The first bit in the bitmap corresponds to cluster #2 */
+	if (clst >= fs->n_fatent - 2) clst = 0;
+	scl = val = clst; ctr = 0;
+	for (;;) {
+		if (move_window(fs, fs->bitbase + val / 8 / SS(fs)) != FR_OK) return 0xFFFFFFFF;
+		i = val / 8 % SS(fs); bm = 1 << (val % 8);
+		do {
+			do {
+				bv = fs->win[i] & bm; bm <<= 1;		/* Get bit value */
+				if (++val >= fs->n_fatent - 2) {	/* Next cluster (with wrap-around) */
+					val = 0; bm = 0; i = SS(fs);
+				}
+				if (bv == 0) {	/* Is it a free cluster? */
+					if (++ctr == ncl) return scl + 2;	/* Check if run length is sufficient for required */
+				} else {
+					scl = val; ctr = 0;		/* Encountered a cluster in-use, restart to scan */
+				}
+				if (val == clst) return 0;	/* All cluster scanned? */
+			} while (bm != 0);
+			bm = 1;
+		} while (++i < SS(fs));
+	}
+}
+
+
+/*----------------------------------------*/
+/* Set/Clear a block of allocation bitmap */
+/*----------------------------------------*/
+
+static FRESULT change_bitmap (
+	FATFS* fs,	/* Filesystem object */
+	DWORD clst,	/* Cluster number to change from */
+	DWORD ncl,	/* Number of clusters to be changed */
+	int bv		/* bit value to be set (0 or 1) */
+)
+{
+	BYTE bm;
+	UINT i;
+	LBA_t sect;
+
+
+	clst -= 2;	/* The first bit corresponds to cluster #2 */
+	sect = fs->bitbase + clst / 8 / SS(fs);	/* Sector address */
+	i = clst / 8 % SS(fs);					/* Byte offset in the sector */
+	bm = 1 << (clst % 8);					/* Bit mask in the byte */
+	for (;;) {
+		if (move_window(fs, sect++) != FR_OK) return FR_DISK_ERR;
+		do {
+			do {
+				if (bv == (int)((fs->win[i] & bm) != 0)) return FR_INT_ERR;	/* Is the bit expected value? */
+				fs->win[i] ^= bm;	/* Flip the bit */
+				fs->wflag = 1;
+				if (--ncl == 0) return FR_OK;	/* All bits processed? */
+			} while (bm <<= 1);		/* Next bit */
+			bm = 1;
+		} while (++i < SS(fs));		/* Next byte */
+		i = 0;
+	}
+}
+
+
+/*---------------------------------------------*/
+/* Fill the first fragment of the FAT chain    */
+/*---------------------------------------------*/
+
+static FRESULT fill_first_frag (
+	FFOBJID* obj	/* Pointer to the corresponding object */
+)
+{
+	FRESULT res;
+	DWORD cl, n;
+
+
+	if (obj->stat == 3) {	/* Has the object been changed 'fragmented' in this session? */
+		for (cl = obj->sclust, n = obj->n_cont; n; cl++, n--) {	/* Create cluster chain on the FAT */
+			res = put_fat(obj->fs, cl, cl + 1);
+			if (res != FR_OK) return res;
+		}
+		obj->stat = 0;	/* Change status 'FAT chain is valid' */
+	}
+	return FR_OK;
+}
+
+
+/*---------------------------------------------*/
+/* Fill the last fragment of the FAT chain     */
+/*---------------------------------------------*/
+
+static FRESULT fill_last_frag (
+	FFOBJID* obj,	/* Pointer to the corresponding object */
+	DWORD lcl,		/* Last cluster of the fragment */
+	DWORD term		/* Value to set the last FAT entry */
+)
+{
+	FRESULT res;
+
+
+	while (obj->n_frag > 0) {	/* Create the chain of last fragment */
+		res = put_fat(obj->fs, lcl - obj->n_frag + 1, (obj->n_frag > 1) ? lcl - obj->n_frag + 2 : term);
+		if (res != FR_OK) return res;
+		obj->n_frag--;
+	}
+	return FR_OK;
+}
+
+#endif	/* FF_FS_EXFAT && !FF_FS_READONLY */
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain                                 */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT remove_chain (	/* FR_OK(0):succeeded, !=0:error */
+	FFOBJID* obj,		/* Corresponding object */
+	DWORD clst,			/* Cluster to remove a chain from */
+	DWORD pclst			/* Previous cluster of clst (0 if entire chain) */
+)
+{
+	FRESULT res = FR_OK;
+	DWORD nxt;
+	FATFS *fs = obj->fs;
+#if FF_FS_EXFAT || FF_USE_TRIM
+	DWORD scl = clst, ecl = clst;
+#endif
+#if FF_USE_TRIM
+	LBA_t rt[2];
+#endif
+
+	if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Check if in valid range */
+
+	/* Mark the previous cluster 'EOC' on the FAT if it exists */
+	if (pclst != 0 && (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) {
+		res = put_fat(fs, pclst, 0xFFFFFFFF);
+		if (res != FR_OK) return res;
+	}
+
+	/* Remove the chain */
+	do {
+		nxt = get_fat(obj, clst);			/* Get cluster status */
+		if (nxt == 0) break;				/* Empty cluster? */
+		if (nxt == 1) return FR_INT_ERR;	/* Internal error? */
+		if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error? */
+		if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {
+			res = put_fat(fs, clst, 0);		/* Mark the cluster 'free' on the FAT */
+			if (res != FR_OK) return res;
+		}
+		if (fs->free_clst < fs->n_fatent - 2) {	/* Update FSINFO */
+			fs->free_clst++;
+			fs->fsi_flag |= 1;
+		}
+#if FF_FS_EXFAT || FF_USE_TRIM
+		if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
+			ecl = nxt;
+		} else {				/* End of contiguous cluster block */
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				res = change_bitmap(fs, scl, ecl - scl + 1, 0);	/* Mark the cluster block 'free' on the bitmap */
+				if (res != FR_OK) return res;
+			}
+#endif
+#if FF_USE_TRIM
+			rt[0] = clst2sect(fs, scl);					/* Start of data area to be freed */
+			rt[1] = clst2sect(fs, ecl) + fs->csize - 1;	/* End of data area to be freed */
+			disk_ioctl(fs->pdrv, CTRL_TRIM, rt);		/* Inform storage device that the data in the block may be erased */
+#endif
+			scl = ecl = nxt;
+		}
+#endif
+		clst = nxt;					/* Next cluster */
+	} while (clst < fs->n_fatent);	/* Repeat while not the last link */
+
+#if FF_FS_EXFAT
+	/* Some post processes for chain status */
+	if (fs->fs_type == FS_EXFAT) {
+		if (pclst == 0) {	/* Has the entire chain been removed? */
+			obj->stat = 0;		/* Change the chain status 'initial' */
+		} else {
+			if (obj->stat == 0) {	/* Is it a fragmented chain from the beginning of this session? */
+				clst = obj->sclust;		/* Follow the chain to check if it gets contiguous */
+				while (clst != pclst) {
+					nxt = get_fat(obj, clst);
+					if (nxt < 2) return FR_INT_ERR;
+					if (nxt == 0xFFFFFFFF) return FR_DISK_ERR;
+					if (nxt != clst + 1) break;	/* Not contiguous? */
+					clst++;
+				}
+				if (clst == pclst) {	/* Has the chain got contiguous again? */
+					obj->stat = 2;		/* Change the chain status 'contiguous' */
+				}
+			} else {
+				if (obj->stat == 3 && pclst >= obj->sclust && pclst <= obj->sclust + obj->n_cont) {	/* Was the chain fragmented in this session and got contiguous again? */
+					obj->stat = 2;	/* Change the chain status 'contiguous' */
+				}
+			}
+		}
+	}
+#endif
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch a chain or Create a new chain                  */
+/*-----------------------------------------------------------------------*/
+
+static DWORD create_chain (	/* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+	FFOBJID* obj,		/* Corresponding object */
+	DWORD clst			/* Cluster# to stretch, 0:Create a new chain */
+)
+{
+	DWORD cs, ncl, scl;
+	FRESULT res;
+	FATFS *fs = obj->fs;
+
+
+	if (clst == 0) {	/* Create a new chain */
+		scl = fs->last_clst;				/* Suggested cluster to start to find */
+		if (scl == 0 || scl >= fs->n_fatent) scl = 1;
+	}
+	else {				/* Stretch a chain */
+		cs = get_fat(obj, clst);			/* Check the cluster status */
+		if (cs < 2) return 1;				/* Test for insanity */
+		if (cs == 0xFFFFFFFF) return cs;	/* Test for disk error */
+		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
+		scl = clst;							/* Cluster to start to find */
+	}
+	if (fs->free_clst == 0) return 0;		/* No free cluster */
+
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		ncl = find_bitmap(fs, scl, 1);				/* Find a free cluster */
+		if (ncl == 0 || ncl == 0xFFFFFFFF) return ncl;	/* No free cluster or hard error? */
+		res = change_bitmap(fs, ncl, 1, 1);			/* Mark the cluster 'in use' */
+		if (res == FR_INT_ERR) return 1;
+		if (res == FR_DISK_ERR) return 0xFFFFFFFF;
+		if (clst == 0) {							/* Is it a new chain? */
+			obj->stat = 2;							/* Set status 'contiguous' */
+		} else {									/* It is a stretched chain */
+			if (obj->stat == 2 && ncl != scl + 1) {	/* Is the chain got fragmented? */
+				obj->n_cont = scl - obj->sclust;	/* Set size of the contiguous part */
+				obj->stat = 3;						/* Change status 'just fragmented' */
+			}
+		}
+		if (obj->stat != 2) {	/* Is the file non-contiguous? */
+			if (ncl == clst + 1) {	/* Is the cluster next to previous one? */
+				obj->n_frag = obj->n_frag ? obj->n_frag + 1 : 2;	/* Increment size of last framgent */
+			} else {				/* New fragment */
+				if (obj->n_frag == 0) obj->n_frag = 1;
+				res = fill_last_frag(obj, clst, ncl);	/* Fill last fragment on the FAT and link it to new one */
+				if (res == FR_OK) obj->n_frag = 1;
+			}
+		}
+	} else
+#endif
+	{	/* On the FAT/FAT32 volume */
+		ncl = 0;
+		if (scl == clst) {						/* Stretching an existing chain? */
+			ncl = scl + 1;						/* Test if next cluster is free */
+			if (ncl >= fs->n_fatent) ncl = 2;
+			cs = get_fat(obj, ncl);				/* Get next cluster status */
+			if (cs == 1 || cs == 0xFFFFFFFF) return cs;	/* Test for error */
+			if (cs != 0) {						/* Not free? */
+				cs = fs->last_clst;				/* Start at suggested cluster if it is valid */
+				if (cs >= 2 && cs < fs->n_fatent) scl = cs;
+				ncl = 0;
+			}
+		}
+		if (ncl == 0) {	/* The new cluster cannot be contiguous and find another fragment */
+			ncl = scl;	/* Start cluster */
+			for (;;) {
+				ncl++;							/* Next cluster */
+				if (ncl >= fs->n_fatent) {		/* Check wrap-around */
+					ncl = 2;
+					if (ncl > scl) return 0;	/* No free cluster found? */
+				}
+				cs = get_fat(obj, ncl);			/* Get the cluster status */
+				if (cs == 0) break;				/* Found a free cluster? */
+				if (cs == 1 || cs == 0xFFFFFFFF) return cs;	/* Test for error */
+				if (ncl == scl) return 0;		/* No free cluster found? */
+			}
+		}
+		res = put_fat(fs, ncl, 0xFFFFFFFF);		/* Mark the new cluster 'EOC' */
+		if (res == FR_OK && clst != 0) {
+			res = put_fat(fs, clst, ncl);		/* Link it from the previous one if needed */
+		}
+	}
+
+	if (res == FR_OK) {			/* Update FSINFO if function succeeded. */
+		fs->last_clst = ncl;
+		if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
+		fs->fsi_flag |= 1;
+	} else {
+		ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;	/* Failed. Generate error status */
+	}
+
+	return ncl;		/* Return new cluster number or error status */
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+
+#if FF_USE_FASTSEEK
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table        */
+/*-----------------------------------------------------------------------*/
+
+static DWORD clmt_clust (	/* <2:Error, >=2:Cluster number */
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t ofs		/* File offset to be converted to cluster# */
+)
+{
+	DWORD cl, ncl;
+	DWORD *tbl;
+	FATFS *fs = fp->obj.fs;
+
+
+	tbl = fp->cltbl + 1;	/* Top of CLMT */
+	cl = (DWORD)(ofs / SS(fs) / fs->csize);	/* Cluster order from top of the file */
+	for (;;) {
+		ncl = *tbl++;			/* Number of cluters in the fragment */
+		if (ncl == 0) return 0;	/* End of table? (error) */
+		if (cl < ncl) break;	/* In this fragment? */
+		cl -= ncl; tbl++;		/* Next fragment */
+	}
+	return cl + *tbl;	/* Return the cluster number */
+}
+
+#endif	/* FF_USE_FASTSEEK */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Fill a cluster with zeros                        */
+/*-----------------------------------------------------------------------*/
+
+#if !FF_FS_READONLY
+static FRESULT dir_clear (	/* Returns FR_OK or FR_DISK_ERR */
+	FATFS *fs,		/* Filesystem object */
+	DWORD clst		/* Directory table to clear */
+)
+{
+	LBA_t sect;
+	UINT n, szb;
+	BYTE *ibuf;
+
+
+	if (sync_window(fs) != FR_OK) return FR_DISK_ERR;	/* Flush disk access window */
+	sect = clst2sect(fs, clst);		/* Top of the cluster */
+	fs->winsect = sect;				/* Set window to top of the cluster */
+	memset(fs->win, 0, sizeof fs->win);	/* Clear window buffer */
+#if FF_USE_LFN == 3		/* Quick table clear by using multi-secter write */
+	/* Allocate a temporary buffer */
+	for (szb = ((DWORD)fs->csize * SS(fs) >= MAX_MALLOC) ? MAX_MALLOC : fs->csize * SS(fs), ibuf = 0; szb > SS(fs) && (ibuf = ff_memalloc(szb)) == 0; szb /= 2) ;
+	if (szb > SS(fs)) {		/* Buffer allocated? */
+		memset(ibuf, 0, szb);
+		szb /= SS(fs);		/* Bytes -> Sectors */
+		for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ;	/* Fill the cluster with 0 */
+		ff_memfree(ibuf);
+	} else
+#endif
+	{
+		ibuf = fs->win; szb = 1;	/* Use window buffer (many single-sector writes may take a time) */
+		for (n = 0; n < fs->csize && disk_write(fs->pdrv, ibuf, sect + n, szb) == RES_OK; n += szb) ;	/* Fill the cluster with 0 */
+	}
+	return (n == fs->csize) ? FR_OK : FR_DISK_ERR;
+}
+#endif	/* !FF_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index                              */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_sdi (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,		/* Pointer to directory object */
+	DWORD ofs		/* Offset of directory table */
+)
+{
+	DWORD csz, clst;
+	FATFS *fs = dp->obj.fs;
+
+
+	if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) {	/* Check range of offset and alignment */
+		return FR_INT_ERR;
+	}
+	dp->dptr = ofs;				/* Set current offset */
+	clst = dp->obj.sclust;		/* Table start cluster (0:root) */
+	if (clst == 0 && fs->fs_type >= FS_FAT32) {	/* Replace cluster# 0 with root cluster# */
+		clst = (DWORD)fs->dirbase;
+		if (FF_FS_EXFAT) dp->obj.stat = 0;	/* exFAT: Root dir has an FAT chain */
+	}
+
+	if (clst == 0) {	/* Static table (root-directory on the FAT volume) */
+		if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR;	/* Is index out of range? */
+		dp->sect = fs->dirbase;
+
+	} else {			/* Dynamic table (sub-directory or root-directory on the FAT32/exFAT volume) */
+		csz = (DWORD)fs->csize * SS(fs);	/* Bytes per cluster */
+		while (ofs >= csz) {				/* Follow cluster chain */
+			clst = get_fat(&dp->obj, clst);				/* Get next cluster */
+			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+			if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR;	/* Reached to end of table or internal error */
+			ofs -= csz;
+		}
+		dp->sect = clst2sect(fs, clst);
+	}
+	dp->clust = clst;					/* Current cluster# */
+	if (dp->sect == 0) return FR_INT_ERR;
+	dp->sect += ofs / SS(fs);			/* Sector# of the directory entry */
+	dp->dir = fs->win + (ofs % SS(fs));	/* Pointer to the entry in the win[] */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next                  */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_next (	/* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
+	DIR* dp,				/* Pointer to the directory object */
+	int stretch				/* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+	DWORD ofs, clst;
+	FATFS *fs = dp->obj.fs;
+
+
+	ofs = dp->dptr + SZDIRE;	/* Next entry */
+	if (ofs >= (DWORD)((FF_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) dp->sect = 0;	/* Disable it if the offset reached the max value */
+	if (dp->sect == 0) return FR_NO_FILE;	/* Report EOT if it has been disabled */
+
+	if (ofs % SS(fs) == 0) {	/* Sector changed? */
+		dp->sect++;				/* Next sector */
+
+		if (dp->clust == 0) {	/* Static table */
+			if (ofs / SZDIRE >= fs->n_rootdir) {	/* Report EOT if it reached end of static table */
+				dp->sect = 0; return FR_NO_FILE;
+			}
+		}
+		else {					/* Dynamic table */
+			if ((ofs / SS(fs) & (fs->csize - 1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(&dp->obj, dp->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_INT_ERR;			/* Internal error */
+				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+				if (clst >= fs->n_fatent) {					/* It reached end of dynamic table */
+#if !FF_FS_READONLY
+					if (!stretch) {								/* If no stretch, report EOT */
+						dp->sect = 0; return FR_NO_FILE;
+					}
+					clst = create_chain(&dp->obj, dp->clust);	/* Allocate a cluster */
+					if (clst == 0) return FR_DENIED;			/* No free cluster */
+					if (clst == 1) return FR_INT_ERR;			/* Internal error */
+					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
+					if (dir_clear(fs, clst) != FR_OK) return FR_DISK_ERR;	/* Clean up the stretched table */
+					if (FF_FS_EXFAT) dp->obj.stat |= 4;			/* exFAT: The directory has been stretched */
+#else
+					if (!stretch) dp->sect = 0;					/* (this line is to suppress compiler warning) */
+					dp->sect = 0; return FR_NO_FILE;			/* Report EOT */
+#endif
+				}
+				dp->clust = clst;		/* Initialize data for new cluster */
+				dp->sect = clst2sect(fs, clst);
+			}
+		}
+	}
+	dp->dptr = ofs;						/* Current entry */
+	dp->dir = fs->win + ofs % SS(fs);	/* Pointer to the entry in the win[] */
+
+	return FR_OK;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Reserve a block of directory entries             */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_alloc (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp,				/* Pointer to the directory object */
+	UINT n_ent				/* Number of contiguous entries to allocate */
+)
+{
+	FRESULT res;
+	UINT n;
+	FATFS *fs = dp->obj.fs;
+
+
+	res = dir_sdi(dp, 0);
+	if (res == FR_OK) {
+		n = 0;
+		do {
+			res = move_window(fs, dp->sect);
+			if (res != FR_OK) break;
+#if FF_FS_EXFAT
+			if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) {	/* Is the entry free? */
+#else
+			if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) {	/* Is the entry free? */
+#endif
+				if (++n == n_ent) break;	/* Is a block of contiguous free entries found? */
+			} else {
+				n = 0;				/* Not a free entry, restart to search */
+			}
+			res = dir_next(dp, 1);	/* Next entry with table stretch enabled */
+		} while (res == FR_OK);
+	}
+
+	if (res == FR_NO_FILE) res = FR_DENIED;	/* No directory entry to allocate */
+	return res;
+}
+
+#endif	/* !FF_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT: Directory handling - Load/Store start cluster number             */
+/*-----------------------------------------------------------------------*/
+
+static DWORD ld_clust (	/* Returns the top cluster value of the SFN entry */
+	FATFS* fs,			/* Pointer to the fs object */
+	const BYTE* dir		/* Pointer to the key entry */
+)
+{
+	DWORD cl;
+
+	cl = ld_word(dir + DIR_FstClusLO);
+	if (fs->fs_type == FS_FAT32) {
+		cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
+	}
+
+	return cl;
+}
+
+
+#if !FF_FS_READONLY
+static void st_clust (
+	FATFS* fs,	/* Pointer to the fs object */
+	BYTE* dir,	/* Pointer to the key entry */
+	DWORD cl	/* Value to be set */
+)
+{
+	st_word(dir + DIR_FstClusLO, (WORD)cl);
+	if (fs->fs_type == FS_FAT32) {
+		st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16));
+	}
+}
+#endif
+
+
+
+#if FF_USE_LFN
+/*--------------------------------------------------------*/
+/* FAT-LFN: Compare a part of file name with an LFN entry */
+/*--------------------------------------------------------*/
+
+static int cmp_lfn (		/* 1:matched, 0:not matched */
+	const WCHAR* lfnbuf,	/* Pointer to the LFN working buffer to be compared */
+	BYTE* dir				/* Pointer to the directory entry containing the part of LFN */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO */
+
+	i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc != 0) {
+			if (i >= FF_MAX_LFN + 1 || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) {	/* Compare it */
+				return 0;					/* Not matched */
+			}
+			wc = uc;
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0;	/* Last segment matched but different length */
+
+	return 1;		/* The part of LFN matched */
+}
+
+
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT
+/*-----------------------------------------------------*/
+/* FAT-LFN: Pick a part of file name from an LFN entry */
+/*-----------------------------------------------------*/
+
+static int pick_lfn (	/* 1:succeeded, 0:buffer overflow or invalid LFN entry */
+	WCHAR* lfnbuf,		/* Pointer to the LFN working buffer */
+	BYTE* dir			/* Pointer to the LFN entry */
+)
+{
+	UINT i, s;
+	WCHAR wc, uc;
+
+
+	if (ld_word(dir + LDIR_FstClusLO) != 0) return 0;	/* Check LDIR_FstClusLO is 0 */
+
+	i = ((dir[LDIR_Ord] & ~LLEF) - 1) * 13;	/* Offset in the LFN buffer */
+
+	for (wc = 1, s = 0; s < 13; s++) {		/* Process all characters in the entry */
+		uc = ld_word(dir + LfnOfs[s]);		/* Pick an LFN character */
+		if (wc != 0) {
+			if (i >= FF_MAX_LFN + 1) return 0;	/* Buffer overflow? */
+			lfnbuf[i++] = wc = uc;			/* Store it */
+		} else {
+			if (uc != 0xFFFF) return 0;		/* Check filler */
+		}
+	}
+
+	if (dir[LDIR_Ord] & LLEF && wc != 0) {	/* Put terminator if it is the last LFN part and not terminated */
+		if (i >= FF_MAX_LFN + 1) return 0;	/* Buffer overflow? */
+		lfnbuf[i] = 0;
+	}
+
+	return 1;		/* The part of LFN is valid */
+}
+#endif
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------*/
+/* FAT-LFN: Create an entry of LFN entries */
+/*-----------------------------------------*/
+
+static void put_lfn (
+	const WCHAR* lfn,	/* Pointer to the LFN */
+	BYTE* dir,			/* Pointer to the LFN entry to be created */
+	BYTE ord,			/* LFN order (1-20) */
+	BYTE sum			/* Checksum of the corresponding SFN */
+)
+{
+	UINT i, s;
+	WCHAR wc;
+
+
+	dir[LDIR_Chksum] = sum;			/* Set checksum */
+	dir[LDIR_Attr] = AM_LFN;		/* Set attribute. LFN entry */
+	dir[LDIR_Type] = 0;
+	st_word(dir + LDIR_FstClusLO, 0);
+
+	i = (ord - 1) * 13;				/* Get offset in the LFN working buffer */
+	s = wc = 0;
+	do {
+		if (wc != 0xFFFF) wc = lfn[i++];	/* Get an effective character */
+		st_word(dir + LfnOfs[s], wc);		/* Put it */
+		if (wc == 0) wc = 0xFFFF;			/* Padding characters for following items */
+	} while (++s < 13);
+	if (wc == 0xFFFF || !lfn[i]) ord |= LLEF;	/* Last LFN part is the start of LFN sequence */
+	dir[LDIR_Ord] = ord;			/* Set the LFN order */
+}
+
+#endif	/* !FF_FS_READONLY */
+#endif	/* FF_USE_LFN */
+
+
+
+#if FF_USE_LFN && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Create a Numbered SFN                                        */
+/*-----------------------------------------------------------------------*/
+
+static void gen_numname (
+	BYTE* dst,			/* Pointer to the buffer to store numbered SFN */
+	const BYTE* src,	/* Pointer to SFN in directory form */
+	const WCHAR* lfn,	/* Pointer to LFN */
+	UINT seq			/* Sequence number */
+)
+{
+	BYTE ns[8], c;
+	UINT i, j;
+	WCHAR wc;
+	DWORD sreg;
+
+
+	memcpy(dst, src, 11);	/* Prepare the SFN to be modified */
+
+	if (seq > 5) {	/* In case of many collisions, generate a hash number instead of sequential number */
+		sreg = seq;
+		while (*lfn) {	/* Create a CRC as hash value */
+			wc = *lfn++;
+			for (i = 0; i < 16; i++) {
+				sreg = (sreg << 1) + (wc & 1);
+				wc >>= 1;
+				if (sreg & 0x10000) sreg ^= 0x11021;
+			}
+		}
+		seq = (UINT)sreg;
+	}
+
+	/* Make suffix (~ + hexadecimal) */
+	i = 7;
+	do {
+		c = (BYTE)((seq % 16) + '0'); seq /= 16;
+		if (c > '9') c += 7;
+		ns[i--] = c;
+	} while (i && seq);
+	ns[i] = '~';
+
+	/* Append the suffix to the SFN body */
+	for (j = 0; j < i && dst[j] != ' '; j++) {	/* Find the offset to append */
+		if (dbc_1st(dst[j])) {	/* To avoid DBC break up */
+			if (j == i - 1) break;
+			j++;
+		}
+	}
+	do {	/* Append the suffix */
+		dst[j++] = (i < 8) ? ns[i++] : ' ';
+	} while (j < 8);
+}
+#endif	/* FF_USE_LFN && !FF_FS_READONLY */
+
+
+
+#if FF_USE_LFN
+/*-----------------------------------------------------------------------*/
+/* FAT-LFN: Calculate checksum of an SFN entry                           */
+/*-----------------------------------------------------------------------*/
+
+static BYTE sum_sfn (
+	const BYTE* dir		/* Pointer to the SFN entry */
+)
+{
+	BYTE sum = 0;
+	UINT n = 11;
+
+	do {
+		sum = (sum >> 1) + (sum << 7) + *dir++;
+	} while (--n);
+	return sum;
+}
+
+#endif	/* FF_USE_LFN */
+
+
+
+#if FF_FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* exFAT: Checksum                                                       */
+/*-----------------------------------------------------------------------*/
+
+static WORD xdir_sum (	/* Get checksum of the directoly entry block */
+	const BYTE* dir		/* Directory entry block to be calculated */
+)
+{
+	UINT i, szblk;
+	WORD sum;
+
+
+	szblk = (dir[XDIR_NumSec] + 1) * SZDIRE;	/* Number of bytes of the entry block */
+	for (i = sum = 0; i < szblk; i++) {
+		if (i == XDIR_SetSum) {	/* Skip 2-byte sum field */
+			i++;
+		} else {
+			sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + dir[i];
+		}
+	}
+	return sum;
+}
+
+
+
+static WORD xname_sum (	/* Get check sum (to be used as hash) of the file name */
+	const WCHAR* name	/* File name to be calculated */
+)
+{
+	WCHAR chr;
+	WORD sum = 0;
+
+
+	while ((chr = *name++) != 0) {
+		chr = (WCHAR)ff_wtoupper(chr);		/* File name needs to be up-case converted */
+		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr & 0xFF);
+		sum = ((sum & 1) ? 0x8000 : 0) + (sum >> 1) + (chr >> 8);
+	}
+	return sum;
+}
+
+
+#if !FF_FS_READONLY && FF_USE_MKFS
+static DWORD xsum32 (	/* Returns 32-bit checksum */
+	BYTE  dat,			/* Byte to be calculated (byte-by-byte processing) */
+	DWORD sum			/* Previous sum value */
+)
+{
+	sum = ((sum & 1) ? 0x80000000 : 0) + (sum >> 1) + dat;
+	return sum;
+}
+#endif
+
+
+
+/*------------------------------------*/
+/* exFAT: Get a directory entry block */
+/*------------------------------------*/
+
+static FRESULT load_xdir (	/* FR_INT_ERR: invalid entry block */
+	DIR* dp					/* Reading directory object pointing top of the entry block to load */
+)
+{
+	FRESULT res;
+	UINT i, sz_ent;
+	BYTE *dirb = dp->obj.fs->dirbuf;	/* Pointer to the on-memory directory entry block 85+C0+C1s */
+
+
+	/* Load file directory entry */
+	res = move_window(dp->obj.fs, dp->sect);
+	if (res != FR_OK) return res;
+	if (dp->dir[XDIR_Type] != ET_FILEDIR) return FR_INT_ERR;	/* Invalid order */
+	memcpy(dirb + 0 * SZDIRE, dp->dir, SZDIRE);
+	sz_ent = (dirb[XDIR_NumSec] + 1) * SZDIRE;
+	if (sz_ent < 3 * SZDIRE || sz_ent > 19 * SZDIRE) return FR_INT_ERR;
+
+	/* Load stream extension entry */
+	res = dir_next(dp, 0);
+	if (res == FR_NO_FILE) res = FR_INT_ERR;	/* It cannot be */
+	if (res != FR_OK) return res;
+	res = move_window(dp->obj.fs, dp->sect);
+	if (res != FR_OK) return res;
+	if (dp->dir[XDIR_Type] != ET_STREAM) return FR_INT_ERR;	/* Invalid order */
+	memcpy(dirb + 1 * SZDIRE, dp->dir, SZDIRE);
+	if (MAXDIRB(dirb[XDIR_NumName]) > sz_ent) return FR_INT_ERR;
+
+	/* Load file name entries */
+	i = 2 * SZDIRE;	/* Name offset to load */
+	do {
+		res = dir_next(dp, 0);
+		if (res == FR_NO_FILE) res = FR_INT_ERR;	/* It cannot be */
+		if (res != FR_OK) return res;
+		res = move_window(dp->obj.fs, dp->sect);
+		if (res != FR_OK) return res;
+		if (dp->dir[XDIR_Type] != ET_FILENAME) return FR_INT_ERR;	/* Invalid order */
+		if (i < MAXDIRB(FF_MAX_LFN)) memcpy(dirb + i, dp->dir, SZDIRE);
+	} while ((i += SZDIRE) < sz_ent);
+
+	/* Sanity check (do it for only accessible object) */
+	if (i <= MAXDIRB(FF_MAX_LFN)) {
+		if (xdir_sum(dirb) != ld_word(dirb + XDIR_SetSum)) return FR_INT_ERR;
+	}
+	return FR_OK;
+}
+
+
+/*------------------------------------------------------------------*/
+/* exFAT: Initialize object allocation info with loaded entry block */
+/*------------------------------------------------------------------*/
+
+static void init_alloc_info (
+	FATFS* fs,		/* Filesystem object */
+	FFOBJID* obj	/* Object allocation information to be initialized */
+)
+{
+	obj->sclust = ld_dword(fs->dirbuf + XDIR_FstClus);		/* Start cluster */
+	obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);	/* Size */
+	obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;				/* Allocation status */
+	obj->n_frag = 0;										/* No last fragment info */
+}
+
+
+
+#if !FF_FS_READONLY || FF_FS_RPATH != 0
+/*------------------------------------------------*/
+/* exFAT: Load the object's directory entry block */
+/*------------------------------------------------*/
+
+static FRESULT load_obj_xdir (
+	DIR* dp,			/* Blank directory object to be used to access containing directory */
+	const FFOBJID* obj	/* Object with its containing directory information */
+)
+{
+	FRESULT res;
+
+	/* Open object containing directory */
+	dp->obj.fs = obj->fs;
+	dp->obj.sclust = obj->c_scl;
+	dp->obj.stat = (BYTE)obj->c_size;
+	dp->obj.objsize = obj->c_size & 0xFFFFFF00;
+	dp->obj.n_frag = 0;
+	dp->blk_ofs = obj->c_ofs;
+
+	res = dir_sdi(dp, dp->blk_ofs);	/* Goto object's entry block */
+	if (res == FR_OK) {
+		res = load_xdir(dp);		/* Load the object's entry block */
+	}
+	return res;
+}
+#endif
+
+
+#if !FF_FS_READONLY
+/*----------------------------------------*/
+/* exFAT: Store the directory entry block */
+/*----------------------------------------*/
+
+static FRESULT store_xdir (
+	DIR* dp				/* Pointer to the directory object */
+)
+{
+	FRESULT res;
+	UINT nent;
+	BYTE *dirb = dp->obj.fs->dirbuf;	/* Pointer to the directory entry block 85+C0+C1s */
+
+	/* Create set sum */
+	st_word(dirb + XDIR_SetSum, xdir_sum(dirb));
+	nent = dirb[XDIR_NumSec] + 1;
+
+	/* Store the directory entry block to the directory */
+	res = dir_sdi(dp, dp->blk_ofs);
+	while (res == FR_OK) {
+		res = move_window(dp->obj.fs, dp->sect);
+		if (res != FR_OK) break;
+		memcpy(dp->dir, dirb, SZDIRE);
+		dp->obj.fs->wflag = 1;
+		if (--nent == 0) break;
+		dirb += SZDIRE;
+		res = dir_next(dp, 0);
+	}
+	return (res == FR_OK || res == FR_DISK_ERR) ? res : FR_INT_ERR;
+}
+
+
+
+/*-------------------------------------------*/
+/* exFAT: Create a new directory entry block */
+/*-------------------------------------------*/
+
+static void create_xdir (
+	BYTE* dirb,			/* Pointer to the directory entry block buffer */
+	const WCHAR* lfn	/* Pointer to the object name */
+)
+{
+	UINT i;
+	BYTE nc1, nlen;
+	WCHAR wc;
+
+
+	/* Create file-directory and stream-extension entry */
+	memset(dirb, 0, 2 * SZDIRE);
+	dirb[0 * SZDIRE + XDIR_Type] = ET_FILEDIR;
+	dirb[1 * SZDIRE + XDIR_Type] = ET_STREAM;
+
+	/* Create file-name entries */
+	i = SZDIRE * 2;	/* Top of file_name entries */
+	nlen = nc1 = 0; wc = 1;
+	do {
+		dirb[i++] = ET_FILENAME; dirb[i++] = 0;
+		do {	/* Fill name field */
+			if (wc != 0 && (wc = lfn[nlen]) != 0) nlen++;	/* Get a character if exist */
+			st_word(dirb + i, wc); 	/* Store it */
+			i += 2;
+		} while (i % SZDIRE != 0);
+		nc1++;
+	} while (lfn[nlen]);	/* Fill next entry if any char follows */
+
+	dirb[XDIR_NumName] = nlen;		/* Set name length */
+	dirb[XDIR_NumSec] = 1 + nc1;	/* Set secondary count (C0 + C1s) */
+	st_word(dirb + XDIR_NameHash, xname_sum(lfn));	/* Set name hash */
+}
+
+#endif	/* !FF_FS_READONLY */
+#endif	/* FF_FS_EXFAT */
+
+
+
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 || FF_USE_LABEL || FF_FS_EXFAT
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+
+#define DIR_READ_FILE(dp) dir_read(dp, 0)
+#define DIR_READ_LABEL(dp) dir_read(dp, 1)
+
+static FRESULT dir_read (
+	DIR* dp,		/* Pointer to the directory object */
+	int vol			/* Filtered by 0:file/directory or 1:volume label */
+)
+{
+	FRESULT res = FR_NO_FILE;
+	FATFS *fs = dp->obj.fs;
+	BYTE attr, b;
+#if FF_USE_LFN
+	BYTE ord = 0xFF, sum = 0xFF;
+#endif
+
+	while (dp->sect) {
+		res = move_window(fs, dp->sect);
+		if (res != FR_OK) break;
+		b = dp->dir[DIR_Name];	/* Test for the entry type */
+		if (b == 0) {
+			res = FR_NO_FILE; break; /* Reached to end of the directory */
+		}
+#if FF_FS_EXFAT
+		if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+			if (FF_USE_LABEL && vol) {
+				if (b == ET_VLABEL) break;	/* Volume label entry? */
+			} else {
+				if (b == ET_FILEDIR) {		/* Start of the file entry block? */
+					dp->blk_ofs = dp->dptr;	/* Get location of the block */
+					res = load_xdir(dp);	/* Load the entry block */
+					if (res == FR_OK) {
+						dp->obj.attr = fs->dirbuf[XDIR_Attr] & AM_MASK;	/* Get attribute */
+					}
+					break;
+				}
+			}
+		} else
+#endif
+		{	/* On the FAT/FAT32 volume */
+			dp->obj.attr = attr = dp->dir[DIR_Attr] & AM_MASK;	/* Get attribute */
+#if FF_USE_LFN		/* LFN configuration */
+			if (b == DDEM || b == '.' || (int)((attr & ~AM_ARC) == AM_VOL) != vol) {	/* An entry without valid data */
+				ord = 0xFF;
+			} else {
+				if (attr == AM_LFN) {	/* An LFN entry is found */
+					if (b & LLEF) {		/* Is it start of an LFN sequence? */
+						sum = dp->dir[LDIR_Chksum];
+						b &= (BYTE)~LLEF; ord = b;
+						dp->blk_ofs = dp->dptr;
+					}
+					/* Check LFN validity and capture it */
+					ord = (b == ord && sum == dp->dir[LDIR_Chksum] && pick_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+				} else {				/* An SFN entry is found */
+					if (ord != 0 || sum != sum_sfn(dp->dir)) {	/* Is there a valid LFN? */
+						dp->blk_ofs = 0xFFFFFFFF;	/* It has no LFN. */
+					}
+					break;
+				}
+			}
+#else		/* Non LFN configuration */
+			if (b != DDEM && b != '.' && attr != AM_LFN && (int)((attr & ~AM_ARC) == AM_VOL) == vol) {	/* Is it a valid entry? */
+				break;
+			}
+#endif
+		}
+		res = dir_next(dp, 0);		/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dp->sect = 0;		/* Terminate the read operation on error or EOT */
+	return res;
+}
+
+#endif	/* FF_FS_MINIMIZE <= 1 || FF_USE_LABEL || FF_FS_RPATH >= 2 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_find (	/* FR_OK(0):succeeded, !=0:error */
+	DIR* dp					/* Pointer to the directory object with the file name */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+	BYTE c;
+#if FF_USE_LFN
+	BYTE a, ord, sum;
+#endif
+
+	res = dir_sdi(dp, 0);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		BYTE nc;
+		UINT di, ni;
+		WORD hash = xname_sum(fs->lfnbuf);		/* Hash value of the name to find */
+
+		while ((res = DIR_READ_FILE(dp)) == FR_OK) {	/* Read an item */
+#if FF_MAX_LFN < 255
+			if (fs->dirbuf[XDIR_NumName] > FF_MAX_LFN) continue;		/* Skip comparison if inaccessible object name */
+#endif
+			if (ld_word(fs->dirbuf + XDIR_NameHash) != hash) continue;	/* Skip comparison if hash mismatched */
+			for (nc = fs->dirbuf[XDIR_NumName], di = SZDIRE * 2, ni = 0; nc; nc--, di += 2, ni++) {	/* Compare the name */
+				if ((di % SZDIRE) == 0) di += 2;
+				if (ff_wtoupper(ld_word(fs->dirbuf + di)) != ff_wtoupper(fs->lfnbuf[ni])) break;
+			}
+			if (nc == 0 && !fs->lfnbuf[ni]) break;	/* Name matched? */
+		}
+		return res;
+	}
+#endif
+	/* On the FAT/FAT32 volume */
+#if FF_USE_LFN
+	ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+#endif
+	do {
+		res = move_window(fs, dp->sect);
+		if (res != FR_OK) break;
+		c = dp->dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+#if FF_USE_LFN		/* LFN configuration */
+		dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;
+		if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) {	/* An entry without valid data */
+			ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+		} else {
+			if (a == AM_LFN) {			/* An LFN entry is found */
+				if (!(dp->fn[NSFLAG] & NS_NOLFN)) {
+					if (c & LLEF) {		/* Is it start of LFN sequence? */
+						sum = dp->dir[LDIR_Chksum];
+						c &= (BYTE)~LLEF; ord = c;	/* LFN start order */
+						dp->blk_ofs = dp->dptr;	/* Start offset of LFN */
+					}
+					/* Check validity of the LFN entry and compare it with given name */
+					ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
+				}
+			} else {					/* An SFN entry is found */
+				if (ord == 0 && sum == sum_sfn(dp->dir)) break;	/* LFN matched? */
+				if (!(dp->fn[NSFLAG] & NS_LOSS) && !memcmp(dp->dir, dp->fn, 11)) break;	/* SFN matched? */
+				ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF;	/* Reset LFN sequence */
+			}
+		}
+#else		/* Non LFN configuration */
+		dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK;
+		if (!(dp->dir[DIR_Attr] & AM_VOL) && !memcmp(dp->dir, dp->fn, 11)) break;	/* Is it a valid entry? */
+#endif
+		res = dir_next(dp, 0);	/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory                                   */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_register (	/* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */
+	DIR* dp						/* Target directory with object name to be created */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+#if FF_USE_LFN		/* LFN configuration */
+	UINT n, len, n_ent;
+	BYTE sn[12], sum;
+
+
+	if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME;	/* Check name validity */
+	for (len = 0; fs->lfnbuf[len]; len++) ;	/* Get lfn length */
+
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		n_ent = (len + 14) / 15 + 2;	/* Number of entries to allocate (85+C0+C1s) */
+		res = dir_alloc(dp, n_ent);		/* Allocate directory entries */
+		if (res != FR_OK) return res;
+		dp->blk_ofs = dp->dptr - SZDIRE * (n_ent - 1);	/* Set the allocated entry block offset */
+
+		if (dp->obj.stat & 4) {			/* Has the directory been stretched by new allocation? */
+			dp->obj.stat &= ~4;
+			res = fill_first_frag(&dp->obj);	/* Fill the first fragment on the FAT if needed */
+			if (res != FR_OK) return res;
+			res = fill_last_frag(&dp->obj, dp->clust, 0xFFFFFFFF);	/* Fill the last fragment on the FAT if needed */
+			if (res != FR_OK) return res;
+			if (dp->obj.sclust != 0) {		/* Is it a sub-directory? */
+				DIR dj;
+
+				res = load_obj_xdir(&dj, &dp->obj);	/* Load the object status */
+				if (res != FR_OK) return res;
+				dp->obj.objsize += (DWORD)fs->csize * SS(fs);		/* Increase the directory size by cluster size */
+				st_qword(fs->dirbuf + XDIR_FileSize, dp->obj.objsize);
+				st_qword(fs->dirbuf + XDIR_ValidFileSize, dp->obj.objsize);
+				fs->dirbuf[XDIR_GenFlags] = dp->obj.stat | 1;		/* Update the allocation status */
+				res = store_xdir(&dj);				/* Store the object status */
+				if (res != FR_OK) return res;
+			}
+		}
+
+		create_xdir(fs->dirbuf, fs->lfnbuf);	/* Create on-memory directory block to be written later */
+		return FR_OK;
+	}
+#endif
+	/* On the FAT/FAT32 volume */
+	memcpy(sn, dp->fn, 12);
+	if (sn[NSFLAG] & NS_LOSS) {			/* When LFN is out of 8.3 format, generate a numbered name */
+		dp->fn[NSFLAG] = NS_NOLFN;		/* Find only SFN */
+		for (n = 1; n < 100; n++) {
+			gen_numname(dp->fn, sn, fs->lfnbuf, n);	/* Generate a numbered name */
+			res = dir_find(dp);				/* Check if the name collides with existing SFN */
+			if (res != FR_OK) break;
+		}
+		if (n == 100) return FR_DENIED;		/* Abort if too many collisions */
+		if (res != FR_NO_FILE) return res;	/* Abort if the result is other than 'not collided' */
+		dp->fn[NSFLAG] = sn[NSFLAG];
+	}
+
+	/* Create an SFN with/without LFNs. */
+	n_ent = (sn[NSFLAG] & NS_LFN) ? (len + 12) / 13 + 1 : 1;	/* Number of entries to allocate */
+	res = dir_alloc(dp, n_ent);		/* Allocate entries */
+	if (res == FR_OK && --n_ent) {	/* Set LFN entry if needed */
+		res = dir_sdi(dp, dp->dptr - n_ent * SZDIRE);
+		if (res == FR_OK) {
+			sum = sum_sfn(dp->fn);	/* Checksum value of the SFN tied to the LFN */
+			do {					/* Store LFN entries in bottom first */
+				res = move_window(fs, dp->sect);
+				if (res != FR_OK) break;
+				put_lfn(fs->lfnbuf, dp->dir, (BYTE)n_ent, sum);
+				fs->wflag = 1;
+				res = dir_next(dp, 0);	/* Next entry */
+			} while (res == FR_OK && --n_ent);
+		}
+	}
+
+#else	/* Non LFN configuration */
+	res = dir_alloc(dp, 1);		/* Allocate an entry for SFN */
+
+#endif
+
+	/* Set SFN entry */
+	if (res == FR_OK) {
+		res = move_window(fs, dp->sect);
+		if (res == FR_OK) {
+			memset(dp->dir, 0, SZDIRE);	/* Clean the entry */
+			memcpy(dp->dir + DIR_Name, dp->fn, 11);	/* Put SFN */
+#if FF_USE_LFN
+			dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT);	/* Put NT flag */
+#endif
+			fs->wflag = 1;
+		}
+	}
+
+	return res;
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+#if !FF_FS_READONLY && FF_FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory                                   */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT dir_remove (	/* FR_OK:Succeeded, FR_DISK_ERR:A disk error */
+	DIR* dp					/* Directory object pointing the entry to be removed */
+)
+{
+	FRESULT res;
+	FATFS *fs = dp->obj.fs;
+#if FF_USE_LFN		/* LFN configuration */
+	DWORD last = dp->dptr;
+
+	res = (dp->blk_ofs == 0xFFFFFFFF) ? FR_OK : dir_sdi(dp, dp->blk_ofs);	/* Goto top of the entry block if LFN is exist */
+	if (res == FR_OK) {
+		do {
+			res = move_window(fs, dp->sect);
+			if (res != FR_OK) break;
+			if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+				dp->dir[XDIR_Type] &= 0x7F;	/* Clear the entry InUse flag. */
+			} else {										/* On the FAT/FAT32 volume */
+				dp->dir[DIR_Name] = DDEM;	/* Mark the entry 'deleted'. */
+			}
+			fs->wflag = 1;
+			if (dp->dptr >= last) break;	/* If reached last entry then all entries of the object has been deleted. */
+			res = dir_next(dp, 0);	/* Next entry */
+		} while (res == FR_OK);
+		if (res == FR_NO_FILE) res = FR_INT_ERR;
+	}
+#else			/* Non LFN configuration */
+
+	res = move_window(fs, dp->sect);
+	if (res == FR_OK) {
+		dp->dir[DIR_Name] = DDEM;	/* Mark the entry 'deleted'.*/
+		fs->wflag = 1;
+	}
+#endif
+
+	return res;
+}
+
+#endif /* !FF_FS_READONLY && FF_FS_MINIMIZE == 0 */
+
+
+
+#if FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+
+static void get_fileinfo (
+	DIR* dp,			/* Pointer to the directory object */
+	FILINFO* fno		/* Pointer to the file information to be filled */
+)
+{
+	UINT si, di;
+#if FF_USE_LFN
+	BYTE lcf;
+	WCHAR wc, hs;
+	FATFS *fs = dp->obj.fs;
+	UINT nw;
+#else
+	TCHAR c;
+#endif
+
+
+	fno->fname[0] = 0;			/* Invaidate file info */
+	if (dp->sect == 0) return;	/* Exit if read pointer has reached end of directory */
+
+#if FF_USE_LFN		/* LFN configuration */
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* exFAT volume */
+		UINT nc = 0;
+
+		si = SZDIRE * 2; di = 0;	/* 1st C1 entry in the entry block */
+		hs = 0;
+		while (nc < fs->dirbuf[XDIR_NumName]) {
+			if (si >= MAXDIRB(FF_MAX_LFN)) {	/* Truncated directory block? */
+				di = 0; break;
+			}
+			if ((si % SZDIRE) == 0) si += 2;	/* Skip entry type field */
+			wc = ld_word(fs->dirbuf + si); si += 2; nc++;	/* Get a character */
+			if (hs == 0 && IsSurrogate(wc)) {	/* Is it a surrogate? */
+				hs = wc; continue;				/* Get low surrogate */
+			}
+			nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di);	/* Store it in API encoding */
+			if (nw == 0) {						/* Buffer overflow or wrong char? */
+				di = 0; break;
+			}
+			di += nw;
+			hs = 0;
+		}
+		if (hs != 0) di = 0;					/* Broken surrogate pair? */
+		if (di == 0) fno->fname[di++] = '\?';	/* Inaccessible object name? */
+		fno->fname[di] = 0;						/* Terminate the name */
+		fno->altname[0] = 0;					/* exFAT does not support SFN */
+
+		fno->fattrib = fs->dirbuf[XDIR_Attr] & AM_MASKX;		/* Attribute */
+		fno->fsize = (fno->fattrib & AM_DIR) ? 0 : ld_qword(fs->dirbuf + XDIR_FileSize);	/* Size */
+		fno->ftime = ld_word(fs->dirbuf + XDIR_ModTime + 0);	/* Time */
+		fno->fdate = ld_word(fs->dirbuf + XDIR_ModTime + 2);	/* Date */
+		return;
+	} else
+#endif
+	{	/* FAT/FAT32 volume */
+		if (dp->blk_ofs != 0xFFFFFFFF) {	/* Get LFN if available */
+			si = di = 0;
+			hs = 0;
+			while (fs->lfnbuf[si] != 0) {
+				wc = fs->lfnbuf[si++];		/* Get an LFN character (UTF-16) */
+				if (hs == 0 && IsSurrogate(wc)) {	/* Is it a surrogate? */
+					hs = wc; continue;		/* Get low surrogate */
+				}
+				nw = put_utf((DWORD)hs << 16 | wc, &fno->fname[di], FF_LFN_BUF - di);	/* Store it in API encoding */
+				if (nw == 0) {				/* Buffer overflow or wrong char? */
+					di = 0; break;
+				}
+				di += nw;
+				hs = 0;
+			}
+			if (hs != 0) di = 0;	/* Broken surrogate pair? */
+			fno->fname[di] = 0;		/* Terminate the LFN (null string means LFN is invalid) */
+		}
+	}
+
+	si = di = 0;
+	while (si < 11) {		/* Get SFN from SFN entry */
+		wc = dp->dir[si++];			/* Get a char */
+		if (wc == ' ') continue;	/* Skip padding spaces */
+		if (wc == RDDEM) wc = DDEM;	/* Restore replaced DDEM character */
+		if (si == 9 && di < FF_SFN_BUF) fno->altname[di++] = '.';	/* Insert a . if extension is exist */
+#if FF_LFN_UNICODE >= 1	/* Unicode output */
+		if (dbc_1st((BYTE)wc) && si != 8 && si != 11 && dbc_2nd(dp->dir[si])) {	/* Make a DBC if needed */
+			wc = wc << 8 | dp->dir[si++];
+		}
+		wc = ff_oem2uni(wc, CODEPAGE);		/* ANSI/OEM -> Unicode */
+		if (wc == 0) {				/* Wrong char in the current code page? */
+			di = 0; break;
+		}
+		nw = put_utf(wc, &fno->altname[di], FF_SFN_BUF - di);	/* Store it in API encoding */
+		if (nw == 0) {				/* Buffer overflow? */
+			di = 0; break;
+		}
+		di += nw;
+#else					/* ANSI/OEM output */
+		fno->altname[di++] = (TCHAR)wc;	/* Store it without any conversion */
+#endif
+	}
+	fno->altname[di] = 0;	/* Terminate the SFN  (null string means SFN is invalid) */
+
+	if (fno->fname[0] == 0) {	/* If LFN is invalid, altname[] needs to be copied to fname[] */
+		if (di == 0) {	/* If LFN and SFN both are invalid, this object is inaccessible */
+			fno->fname[di++] = '\?';
+		} else {
+			for (si = di = 0, lcf = NS_BODY; fno->altname[si]; si++, di++) {	/* Copy altname[] to fname[] with case information */
+				wc = (WCHAR)fno->altname[si];
+				if (wc == '.') lcf = NS_EXT;
+				if (IsUpper(wc) && (dp->dir[DIR_NTres] & lcf)) wc += 0x20;
+				fno->fname[di] = (TCHAR)wc;
+			}
+		}
+		fno->fname[di] = 0;	/* Terminate the LFN */
+		if (!dp->dir[DIR_NTres]) fno->altname[0] = 0;	/* Altname is not needed if neither LFN nor case info is exist. */
+	}
+
+#else	/* Non-LFN configuration */
+	si = di = 0;
+	while (si < 11) {		/* Copy name body and extension */
+		c = (TCHAR)dp->dir[si++];
+		if (c == ' ') continue;		/* Skip padding spaces */
+		if (c == RDDEM) c = DDEM;	/* Restore replaced DDEM character */
+		if (si == 9) fno->fname[di++] = '.';/* Insert a . if extension is exist */
+		fno->fname[di++] = c;
+	}
+	fno->fname[di] = 0;		/* Terminate the SFN */
+#endif
+
+	fno->fattrib = dp->dir[DIR_Attr] & AM_MASK;			/* Attribute */
+	fno->fsize = ld_dword(dp->dir + DIR_FileSize);		/* Size */
+	fno->ftime = ld_word(dp->dir + DIR_ModTime + 0);	/* Time */
+	fno->fdate = ld_word(dp->dir + DIR_ModTime + 2);	/* Date */
+}
+
+#endif /* FF_FS_MINIMIZE <= 1 || FF_FS_RPATH >= 2 */
+
+
+
+#if FF_USE_FIND && FF_FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Pattern matching                                                      */
+/*-----------------------------------------------------------------------*/
+
+#define FIND_RECURS	4	/* Maximum number of wildcard terms in the pattern to limit recursion */
+
+
+static DWORD get_achar (	/* Get a character and advance ptr */
+	const TCHAR** ptr		/* Pointer to pointer to the ANSI/OEM or Unicode string */
+)
+{
+	DWORD chr;
+
+
+#if FF_USE_LFN && FF_LFN_UNICODE >= 1	/* Unicode input */
+	chr = tchar2uni(ptr);
+	if (chr == 0xFFFFFFFF) chr = 0;		/* Wrong UTF encoding is recognized as end of the string */
+	chr = ff_wtoupper(chr);
+
+#else									/* ANSI/OEM input */
+	chr = (BYTE)*(*ptr)++;				/* Get a byte */
+	if (IsLower(chr)) chr -= 0x20;		/* To upper ASCII char */
+#if FF_CODE_PAGE == 0
+	if (ExCvt && chr >= 0x80) chr = ExCvt[chr - 0x80];	/* To upper SBCS extended char */
+#elif FF_CODE_PAGE < 900
+	if (chr >= 0x80) chr = ExCvt[chr - 0x80];	/* To upper SBCS extended char */
+#endif
+#if FF_CODE_PAGE == 0 || FF_CODE_PAGE >= 900
+	if (dbc_1st((BYTE)chr)) {	/* Get DBC 2nd byte if needed */
+		chr = dbc_2nd((BYTE)**ptr) ? chr << 8 | (BYTE)*(*ptr)++ : 0;
+	}
+#endif
+
+#endif
+	return chr;
+}
+
+
+static int pattern_match (	/* 0:mismatched, 1:matched */
+	const TCHAR* pat,	/* Matching pattern */
+	const TCHAR* nam,	/* String to be tested */
+	UINT skip,			/* Number of pre-skip chars (number of ?s, b8:infinite (* specified)) */
+	UINT recur			/* Recursion count */
+)
+{
+	const TCHAR *pptr;
+	const TCHAR *nptr;
+	DWORD pchr, nchr;
+	UINT sk;
+
+
+	while ((skip & 0xFF) != 0) {		/* Pre-skip name chars */
+		if (!get_achar(&nam)) return 0;	/* Branch mismatched if less name chars */
+		skip--;
+	}
+	if (*pat == 0 && skip) return 1;	/* Matched? (short circuit) */
+
+	do {
+		pptr = pat; nptr = nam;			/* Top of pattern and name to match */
+		for (;;) {
+			if (*pptr == '\?' || *pptr == '*') {	/* Wildcard term? */
+				if (recur == 0) return 0;	/* Too many wildcard terms? */
+				sk = 0;
+				do {	/* Analyze the wildcard term */
+					if (*pptr++ == '\?') {
+						sk++;
+					} else {
+						sk |= 0x100;
+					}
+				} while (*pptr == '\?' || *pptr == '*');
+				if (pattern_match(pptr, nptr, sk, recur - 1)) return 1;	/* Test new branch (recursive call) */
+				nchr = *nptr; break;	/* Branch mismatched */
+			}
+			pchr = get_achar(&pptr);	/* Get a pattern char */
+			nchr = get_achar(&nptr);	/* Get a name char */
+			if (pchr != nchr) break;	/* Branch mismatched? */
+			if (pchr == 0) return 1;	/* Branch matched? (matched at end of both strings) */
+		}
+		get_achar(&nam);			/* nam++ */
+	} while (skip && nchr);		/* Retry until end of name if infinite search is specified */
+
+	return 0;
+}
+
+#endif /* FF_USE_FIND && FF_FS_MINIMIZE <= 1 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a top segment and create the object name in directory form       */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT create_name (	/* FR_OK: successful, FR_INVALID_NAME: could not create */
+	DIR* dp,					/* Pointer to the directory object */
+	const TCHAR** path			/* Pointer to pointer to the segment in the path string */
+)
+{
+#if FF_USE_LFN		/* LFN configuration */
+	BYTE b, cf;
+	WCHAR wc;
+	WCHAR *lfn;
+	const TCHAR* p;
+	DWORD uc;
+	UINT i, ni, si, di;
+
+
+	/* Create LFN into LFN working buffer */
+	p = *path; lfn = dp->obj.fs->lfnbuf; di = 0;
+	for (;;) {
+		uc = tchar2uni(&p);			/* Get a character */
+		if (uc == 0xFFFFFFFF) return FR_INVALID_NAME;		/* Invalid code or UTF decode error */
+		if (uc >= 0x10000) lfn[di++] = (WCHAR)(uc >> 16);	/* Store high surrogate if needed */
+		wc = (WCHAR)uc;
+		if (wc < ' ' || IsSeparator(wc)) break;	/* Break if end of the path or a separator is found */
+		if (wc < 0x80 && strchr("*:<>|\"\?\x7F", (int)wc)) return FR_INVALID_NAME;	/* Reject illegal characters for LFN */
+		if (di >= FF_MAX_LFN) return FR_INVALID_NAME;	/* Reject too long name */
+		lfn[di++] = wc;				/* Store the Unicode character */
+	}
+	if (wc < ' ') {				/* Stopped at end of the path? */
+		cf = NS_LAST;			/* Last segment */
+	} else {					/* Stopped at a separator */
+		while (IsSeparator(*p)) p++;	/* Skip duplicated separators if exist */
+		cf = 0;					/* Next segment may follow */
+		if (IsTerminator(*p)) cf = NS_LAST;	/* Ignore terminating separator */
+	}
+	*path = p;					/* Return pointer to the next segment */
+
+#if FF_FS_RPATH != 0
+	if ((di == 1 && lfn[di - 1] == '.') ||
+		(di == 2 && lfn[di - 1] == '.' && lfn[di - 2] == '.')) {	/* Is this segment a dot name? */
+		lfn[di] = 0;
+		for (i = 0; i < 11; i++) {	/* Create dot name for SFN entry */
+			dp->fn[i] = (i < di) ? '.' : ' ';
+		}
+		dp->fn[i] = cf | NS_DOT;	/* This is a dot entry */
+		return FR_OK;
+	}
+#endif
+	while (di) {					/* Snip off trailing spaces and dots if exist */
+		wc = lfn[di - 1];
+		if (wc != ' ' && wc != '.') break;
+		di--;
+	}
+	lfn[di] = 0;							/* LFN is created into the working buffer */
+	if (di == 0) return FR_INVALID_NAME;	/* Reject null name */
+
+	/* Create SFN in directory form */
+	for (si = 0; lfn[si] == ' '; si++) ;	/* Remove leading spaces */
+	if (si > 0 || lfn[si] == '.') cf |= NS_LOSS | NS_LFN;	/* Is there any leading space or dot? */
+	while (di > 0 && lfn[di - 1] != '.') di--;	/* Find last dot (di<=si: no extension) */
+
+	memset(dp->fn, ' ', 11);
+	i = b = 0; ni = 8;
+	for (;;) {
+		wc = lfn[si++];					/* Get an LFN character */
+		if (wc == 0) break;				/* Break on end of the LFN */
+		if (wc == ' ' || (wc == '.' && si != di)) {	/* Remove embedded spaces and dots */
+			cf |= NS_LOSS | NS_LFN;
+			continue;
+		}
+
+		if (i >= ni || si == di) {		/* End of field? */
+			if (ni == 11) {				/* Name extension overflow? */
+				cf |= NS_LOSS | NS_LFN;
+				break;
+			}
+			if (si != di) cf |= NS_LOSS | NS_LFN;	/* Name body overflow? */
+			if (si > di) break;						/* No name extension? */
+			si = di; i = 8; ni = 11; b <<= 2;		/* Enter name extension */
+			continue;
+		}
+
+		if (wc >= 0x80) {	/* Is this an extended character? */
+			cf |= NS_LFN;	/* LFN entry needs to be created */
+#if FF_CODE_PAGE == 0
+			if (ExCvt) {	/* In SBCS cfg */
+				wc = ff_uni2oem(wc, CODEPAGE);			/* Unicode ==> ANSI/OEM code */
+				if (wc & 0x80) wc = ExCvt[wc & 0x7F];	/* Convert extended character to upper (SBCS) */
+			} else {		/* In DBCS cfg */
+				wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE);	/* Unicode ==> Up-convert ==> ANSI/OEM code */
+			}
+#elif FF_CODE_PAGE < 900	/* In SBCS cfg */
+			wc = ff_uni2oem(wc, CODEPAGE);			/* Unicode ==> ANSI/OEM code */
+			if (wc & 0x80) wc = ExCvt[wc & 0x7F];	/* Convert extended character to upper (SBCS) */
+#else						/* In DBCS cfg */
+			wc = ff_uni2oem(ff_wtoupper(wc), CODEPAGE);	/* Unicode ==> Up-convert ==> ANSI/OEM code */
+#endif
+		}
+
+		if (wc >= 0x100) {				/* Is this a DBC? */
+			if (i >= ni - 1) {			/* Field overflow? */
+				cf |= NS_LOSS | NS_LFN;
+				i = ni; continue;		/* Next field */
+			}
+			dp->fn[i++] = (BYTE)(wc >> 8);	/* Put 1st byte */
+		} else {						/* SBC */
+			if (wc == 0 || strchr("+,;=[]", (int)wc)) {	/* Replace illegal characters for SFN */
+				wc = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+			} else {
+				if (IsUpper(wc)) {		/* ASCII upper case? */
+					b |= 2;
+				}
+				if (IsLower(wc)) {		/* ASCII lower case? */
+					b |= 1; wc -= 0x20;
+				}
+			}
+		}
+		dp->fn[i++] = (BYTE)wc;
+	}
+
+	if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+
+	if (ni == 8) b <<= 2;				/* Shift capital flags if no extension */
+	if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN;	/* LFN entry needs to be created if composite capitals */
+	if (!(cf & NS_LFN)) {				/* When LFN is in 8.3 format without extended character, NT flags are created */
+		if (b & 0x01) cf |= NS_EXT;		/* NT flag (Extension has small capital letters only) */
+		if (b & 0x04) cf |= NS_BODY;	/* NT flag (Body has small capital letters only) */
+	}
+
+	dp->fn[NSFLAG] = cf;	/* SFN is created into dp->fn[] */
+
+	return FR_OK;
+
+
+#else	/* FF_USE_LFN : Non-LFN configuration */
+	BYTE c, d;
+	BYTE *sfn;
+	UINT ni, si, i;
+	const char *p;
+
+	/* Create file name in directory form */
+	p = *path; sfn = dp->fn;
+	memset(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+#if FF_FS_RPATH != 0
+	if (p[si] == '.') { /* Is this a dot entry? */
+		for (;;) {
+			c = (BYTE)p[si++];
+			if (c != '.' || si >= 3) break;
+			sfn[i++] = c;
+		}
+		if (!IsSeparator(c) && c > ' ') return FR_INVALID_NAME;
+		*path = p + si;					/* Return pointer to the next segment */
+		sfn[NSFLAG] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT;	/* Set last segment flag if end of the path */
+		return FR_OK;
+	}
+#endif
+	for (;;) {
+		c = (BYTE)p[si++];				/* Get a byte */
+		if (c <= ' ') break; 			/* Break if end of the path name */
+		if (IsSeparator(c)) {			/* Break if a separator is found */
+			while (IsSeparator(p[si])) si++;	/* Skip duplicated separator if exist */
+			break;
+		}
+		if (c == '.' || i >= ni) {		/* End of body or field overflow? */
+			if (ni == 11 || c != '.') return FR_INVALID_NAME;	/* Field overflow or invalid dot? */
+			i = 8; ni = 11;				/* Enter file extension field */
+			continue;
+		}
+#if FF_CODE_PAGE == 0
+		if (ExCvt && c >= 0x80) {		/* Is SBC extended character? */
+			c = ExCvt[c & 0x7F];		/* To upper SBC extended character */
+		}
+#elif FF_CODE_PAGE < 900
+		if (c >= 0x80) {				/* Is SBC extended character? */
+			c = ExCvt[c & 0x7F];		/* To upper SBC extended character */
+		}
+#endif
+		if (dbc_1st(c)) {				/* Check if it is a DBC 1st byte */
+			d = (BYTE)p[si++];			/* Get 2nd byte */
+			if (!dbc_2nd(d) || i >= ni - 1) return FR_INVALID_NAME;	/* Reject invalid DBC */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* SBC */
+			if (strchr("*+,:;<=>[]|\"\?\x7F", (int)c)) return FR_INVALID_NAME;	/* Reject illegal chrs for SFN */
+			if (IsLower(c)) c -= 0x20;	/* To upper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Return pointer to the next segment */
+	if (i == 0) return FR_INVALID_NAME;	/* Reject nul string */
+
+	if (sfn[0] == DDEM) sfn[0] = RDDEM;	/* If the first character collides with DDEM, replace it with RDDEM */
+	sfn[NSFLAG] = (c <= ' ' || p[si] <= ' ') ? NS_LAST : 0;	/* Set last segment flag if end of the path */
+
+	return FR_OK;
+#endif /* FF_USE_LFN */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR* dp,					/* Directory object to return last directory and found object */
+	const TCHAR* path			/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+	BYTE ns;
+	FATFS *fs = dp->obj.fs;
+
+
+#if FF_FS_RPATH != 0
+	if (!IsSeparator(*path) && (FF_STR_VOLUME_ID != 2 || !IsTerminator(*path))) {	/* Without heading separator */
+		dp->obj.sclust = fs->cdir;			/* Start at the current directory */
+	} else
+#endif
+	{										/* With heading separator */
+		while (IsSeparator(*path)) path++;	/* Strip separators */
+		dp->obj.sclust = 0;					/* Start from the root directory */
+	}
+#if FF_FS_EXFAT
+	dp->obj.n_frag = 0;	/* Invalidate last fragment counter of the object */
+#if FF_FS_RPATH != 0
+	if (fs->fs_type == FS_EXFAT && dp->obj.sclust) {	/* exFAT: Retrieve the sub-directory's status */
+		DIR dj;
+
+		dp->obj.c_scl = fs->cdc_scl;
+		dp->obj.c_size = fs->cdc_size;
+		dp->obj.c_ofs = fs->cdc_ofs;
+		res = load_obj_xdir(&dj, &dp->obj);
+		if (res != FR_OK) return res;
+		dp->obj.objsize = ld_dword(fs->dirbuf + XDIR_FileSize);
+		dp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
+	}
+#endif
+#endif
+
+	if ((UINT)*path < ' ') {				/* Null path name is the origin directory itself */
+		dp->fn[NSFLAG] = NS_NONAME;
+		res = dir_sdi(dp, 0);
+
+	} else {								/* Follow path */
+		for (;;) {
+			res = create_name(dp, &path);	/* Get a segment name of the path */
+			if (res != FR_OK) break;
+			res = dir_find(dp);				/* Find an object with the segment name */
+			ns = dp->fn[NSFLAG];
+			if (res != FR_OK) {				/* Failed to find the object */
+				if (res == FR_NO_FILE) {	/* Object is not found */
+					if (FF_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exist, stay there */
+						if (!(ns & NS_LAST)) continue;	/* Continue to follow if not last segment */
+						dp->fn[NSFLAG] = NS_NONAME;
+						res = FR_OK;
+					} else {							/* Could not find the object */
+						if (!(ns & NS_LAST)) res = FR_NO_PATH;	/* Adjust error code if not last segment */
+					}
+				}
+				break;
+			}
+			if (ns & NS_LAST) break;		/* Last segment matched. Function completed. */
+			/* Get into the sub-directory */
+			if (!(dp->obj.attr & AM_DIR)) {	/* It is not a sub-directory and cannot follow */
+				res = FR_NO_PATH; break;
+			}
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {	/* Save containing directory information for next dir */
+				dp->obj.c_scl = dp->obj.sclust;
+				dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat;
+				dp->obj.c_ofs = dp->blk_ofs;
+				init_alloc_info(fs, &dp->obj);	/* Open next directory */
+			} else
+#endif
+			{
+				dp->obj.sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs));	/* Open next directory */
+			}
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get logical drive number from path name                               */
+/*-----------------------------------------------------------------------*/
+
+static int get_ldnumber (	/* Returns logical drive number (-1:invalid drive number or null pointer) */
+	const TCHAR** path		/* Pointer to pointer to the path name */
+)
+{
+	const TCHAR *tp;
+	const TCHAR *tt;
+	TCHAR tc;
+	int i;
+	int vol = -1;
+#if FF_STR_VOLUME_ID		/* Find string volume ID */
+	const char *sp;
+	char c;
+#endif
+
+	tt = tp = *path;
+	if (!tp) return vol;	/* Invalid path name? */
+	do {					/* Find a colon in the path */
+		tc = *tt++;
+	} while (!IsTerminator(tc) && tc != ':');
+
+	if (tc == ':') {	/* DOS/Windows style volume ID? */
+		i = FF_VOLUMES;
+		if (IsDigit(*tp) && tp + 2 == tt) {	/* Is there a numeric volume ID + colon? */
+			i = (int)*tp - '0';	/* Get the LD number */
+		}
+#if FF_STR_VOLUME_ID == 1	/* Arbitrary string is enabled */
+		else {
+			i = 0;
+			do {
+				sp = VolumeStr[i]; tp = *path;	/* This string volume ID and path name */
+				do {	/* Compare the volume ID with path name */
+					c = *sp++; tc = *tp++;
+					if (IsLower(c)) c -= 0x20;
+					if (IsLower(tc)) tc -= 0x20;
+				} while (c && (TCHAR)c == tc);
+			} while ((c || tp != tt) && ++i < FF_VOLUMES);	/* Repeat for each id until pattern match */
+		}
+#endif
+		if (i < FF_VOLUMES) {	/* If a volume ID is found, get the drive number and strip it */
+			vol = i;		/* Drive number */
+			*path = tt;		/* Snip the drive prefix off */
+		}
+		return vol;
+	}
+#if FF_STR_VOLUME_ID == 2		/* Unix style volume ID is enabled */
+	if (*tp == '/') {			/* Is there a volume ID? */
+		while (*(tp + 1) == '/') tp++;	/* Skip duplicated separator */
+		i = 0;
+		do {
+			tt = tp; sp = VolumeStr[i]; /* Path name and this string volume ID */
+			do {	/* Compare the volume ID with path name */
+				c = *sp++; tc = *(++tt);
+				if (IsLower(c)) c -= 0x20;
+				if (IsLower(tc)) tc -= 0x20;
+			} while (c && (TCHAR)c == tc);
+		} while ((c || (tc != '/' && !IsTerminator(tc))) && ++i < FF_VOLUMES);	/* Repeat for each ID until pattern match */
+		if (i < FF_VOLUMES) {	/* If a volume ID is found, get the drive number and strip it */
+			vol = i;		/* Drive number */
+			*path = tt;		/* Snip the drive prefix off */
+		}
+		return vol;
+	}
+#endif
+	/* No drive prefix is found */
+#if FF_FS_RPATH != 0
+	vol = CurrVol;	/* Default drive is current drive */
+#else
+	vol = 0;		/* Default drive is 0 */
+#endif
+	return vol;		/* Return the default drive */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* GPT support functions                                                 */
+/*-----------------------------------------------------------------------*/
+
+#if FF_LBA64
+
+/* Calculate CRC32 in byte-by-byte */
+
+static DWORD crc32 (	/* Returns next CRC value */
+	DWORD crc,			/* Current CRC value */
+	BYTE d				/* A byte to be processed */
+)
+{
+	BYTE b;
+
+
+	for (b = 1; b; b <<= 1) {
+		crc ^= (d & b) ? 1 : 0;
+		crc = (crc & 1) ? crc >> 1 ^ 0xEDB88320 : crc >> 1;
+	}
+	return crc;
+}
+
+
+/* Check validity of GPT header */
+
+static int test_gpt_header (	/* 0:Invalid, 1:Valid */
+	const BYTE* gpth			/* Pointer to the GPT header */
+)
+{
+	UINT i;
+	DWORD bcc, hlen;
+
+
+	if (memcmp(gpth + GPTH_Sign, "EFI PART" "\0\0\1", 12)) return 0;	/* Check signature and version (1.0) */
+	hlen = ld_dword(gpth + GPTH_Size);						/* Check header size */
+	if (hlen < 92 || hlen > FF_MIN_SS) return 0;
+	for (i = 0, bcc = 0xFFFFFFFF; i < hlen; i++) {			/* Check header BCC */
+		bcc = crc32(bcc, i - GPTH_Bcc < 4 ? 0 : gpth[i]);
+	}
+	if (~bcc != ld_dword(gpth + GPTH_Bcc)) return 0;
+	if (ld_dword(gpth + GPTH_PteSize) != SZ_GPTE) return 0;	/* Table entry size (must be SZ_GPTE bytes) */
+	if (ld_dword(gpth + GPTH_PtNum) > 128) return 0;		/* Table size (must be 128 entries or less) */
+
+	return 1;
+}
+
+#if !FF_FS_READONLY && FF_USE_MKFS
+
+/* Generate random value */
+static DWORD make_rand (
+	DWORD seed,		/* Seed value */
+	BYTE *buff,		/* Output buffer */
+	UINT n			/* Data length */
+)
+{
+	UINT r;
+
+
+	if (seed == 0) seed = 1;
+	do {
+		for (r = 0; r < 8; r++) seed = seed & 1 ? seed >> 1 ^ 0xA3000000 : seed >> 1;	/* Shift 8 bits the 32-bit LFSR */
+		*buff++ = (BYTE)seed;
+	} while (--n);
+	return seed;
+}
+
+#endif
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT VBR                           */
+/*-----------------------------------------------------------------------*/
+
+/* Check what the sector is */
+
+static UINT check_fs (	/* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS, 3:Not FAT and invalid BS, 4:Disk error */
+	FATFS* fs,			/* Filesystem object */
+	LBA_t sect			/* Sector to load and check if it is an FAT-VBR or not */
+)
+{
+	WORD w, sign;
+	BYTE b;
+
+
+	fs->wflag = 0; fs->winsect = (LBA_t)0 - 1;		/* Invaidate window */
+	if (move_window(fs, sect) != FR_OK) return 4;	/* Load the boot sector */
+	sign = ld_word(fs->win + BS_55AA);
+#if FF_FS_EXFAT
+	if (sign == 0xAA55 && !memcmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11)) return 1;	/* It is an exFAT VBR */
+#endif
+	b = fs->win[BS_JmpBoot];
+	if (b == 0xEB || b == 0xE9 || b == 0xE8) {	/* Valid JumpBoot code? (short jump, near jump or near call) */
+		if (sign == 0xAA55 && !memcmp(fs->win + BS_FilSysType32, "FAT32   ", 8)) {
+			return 0;	/* It is an FAT32 VBR */
+		}
+		/* FAT volumes formatted with early MS-DOS lack BS_55AA and BS_FilSysType, so FAT VBR needs to be identified without them. */
+		w = ld_word(fs->win + BPB_BytsPerSec);
+		b = fs->win[BPB_SecPerClus];
+		if ((w & (w - 1)) == 0 && w >= FF_MIN_SS && w <= FF_MAX_SS	/* Properness of sector size (512-4096 and 2^n) */
+			&& b != 0 && (b & (b - 1)) == 0				/* Properness of cluster size (2^n) */
+			&& ld_word(fs->win + BPB_RsvdSecCnt) != 0	/* Properness of reserved sectors (MNBZ) */
+			&& (UINT)fs->win[BPB_NumFATs] - 1 <= 1		/* Properness of FATs (1 or 2) */
+			&& ld_word(fs->win + BPB_RootEntCnt) != 0	/* Properness of root dir entries (MNBZ) */
+			&& (ld_word(fs->win + BPB_TotSec16) >= 128 || ld_dword(fs->win + BPB_TotSec32) >= 0x10000)	/* Properness of volume sectors (>=128) */
+			&& ld_word(fs->win + BPB_FATSz16) != 0) {	/* Properness of FAT size (MNBZ) */
+				return 0;	/* It can be presumed an FAT VBR */
+		}
+	}
+	return sign == 0xAA55 ? 2 : 3;	/* Not an FAT VBR (valid or invalid BS) */
+}
+
+
+/* Find an FAT volume */
+/* (It supports only generic partitioning rules, MBR, GPT and SFD) */
+
+static UINT find_volume (	/* Returns BS status found in the hosting drive */
+	FATFS* fs,		/* Filesystem object */
+	UINT part		/* Partition to fined = 0:find as SFD and partitions, >0:forced partition number */
+)
+{
+	UINT fmt, i;
+	DWORD mbr_pt[4];
+
+
+	fmt = check_fs(fs, 0);				/* Load sector 0 and check if it is an FAT VBR as SFD format */
+	if (fmt != 2 && (fmt >= 3 || part == 0)) return fmt;	/* Returns if it is an FAT VBR as auto scan, not a BS or disk error */
+
+	/* Sector 0 is not an FAT VBR or forced partition number wants a partition */
+
+#if FF_LBA64
+	if (fs->win[MBR_Table + PTE_System] == 0xEE) {	/* GPT protective MBR? */
+		DWORD n_ent, v_ent, ofs;
+		QWORD pt_lba;
+
+		if (move_window(fs, 1) != FR_OK) return 4;	/* Load GPT header sector (next to MBR) */
+		if (!test_gpt_header(fs->win)) return 3;	/* Check if GPT header is valid */
+		n_ent = ld_dword(fs->win + GPTH_PtNum);		/* Number of entries */
+		pt_lba = ld_qword(fs->win + GPTH_PtOfs);	/* Table location */
+		for (v_ent = i = 0; i < n_ent; i++) {		/* Find FAT partition */
+			if (move_window(fs, pt_lba + i * SZ_GPTE / SS(fs)) != FR_OK) return 4;	/* PT sector */
+			ofs = i * SZ_GPTE % SS(fs);												/* Offset in the sector */
+			if (!memcmp(fs->win + ofs + GPTE_PtGuid, GUID_MS_Basic, 16)) {	/* MS basic data partition? */
+				v_ent++;
+				fmt = check_fs(fs, ld_qword(fs->win + ofs + GPTE_FstLba));	/* Load VBR and check status */
+				if (part == 0 && fmt <= 1) return fmt;			/* Auto search (valid FAT volume found first) */
+				if (part != 0 && v_ent == part) return fmt;		/* Forced partition order (regardless of it is valid or not) */
+			}
+		}
+		return 3;	/* Not found */
+	}
+#endif
+	if (FF_MULTI_PARTITION && part > 4) return 3;	/* MBR has 4 partitions max */
+	for (i = 0; i < 4; i++) {		/* Load partition offset in the MBR */
+		mbr_pt[i] = ld_dword(fs->win + MBR_Table + i * SZ_PTE + PTE_StLba);
+	}
+	i = part ? part - 1 : 0;		/* Table index to find first */
+	do {							/* Find an FAT volume */
+		fmt = mbr_pt[i] ? check_fs(fs, mbr_pt[i]) : 3;	/* Check if the partition is FAT */
+	} while (part == 0 && fmt >= 2 && ++i < 4);
+	return fmt;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Determine logical drive number and mount the volume if needed         */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT mount_volume (	/* FR_OK(0): successful, !=0: an error occurred */
+	const TCHAR** path,			/* Pointer to pointer to the path name (drive number) */
+	FATFS** rfs,				/* Pointer to pointer to the found filesystem object */
+	BYTE mode					/* Desiered access mode to check write protection */
+)
+{
+	int vol;
+	FATFS *fs;
+	DSTATUS stat;
+	LBA_t bsect;
+	DWORD tsect, sysect, fasize, nclst, szbfat;
+	WORD nrsv;
+	UINT fmt;
+
+
+	/* Get logical drive number */
+	*rfs = 0;
+	vol = get_ldnumber(path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+
+	/* Check if the filesystem object is valid or not */
+	fs = FatFs[vol];					/* Get pointer to the filesystem object */
+	if (!fs) return FR_NOT_ENABLED;		/* Is the filesystem object available? */
+#if FF_FS_REENTRANT
+	if (!lock_volume(fs, 1)) return FR_TIMEOUT;	/* Lock the volume, and system if needed */
+#endif
+	*rfs = fs;							/* Return pointer to the filesystem object */
+
+	mode &= (BYTE)~FA_READ;				/* Desired access mode, write access or not */
+	if (fs->fs_type != 0) {				/* If the volume has been mounted */
+		stat = disk_status(fs->pdrv);
+		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized */
+			if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) {	/* Check write protection if needed */
+				return FR_WRITE_PROTECTED;
+			}
+			return FR_OK;				/* The filesystem object is already valid */
+		}
+	}
+
+	/* The filesystem object is not valid. */
+	/* Following code attempts to mount the volume. (find an FAT volume, analyze the BPB and initialize the filesystem object) */
+
+	fs->fs_type = 0;					/* Invalidate the filesystem object */
+	stat = disk_initialize(fs->pdrv);	/* Initialize the volume hosting physical drive */
+	if (stat & STA_NOINIT) { 			/* Check if the initialization succeeded */
+		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
+	}
+	if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
+		return FR_WRITE_PROTECTED;
+	}
+#if FF_MAX_SS != FF_MIN_SS				/* Get sector size (multiple sector size cfg only) */
+	if (disk_ioctl(fs->pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR;
+	if (SS(fs) > FF_MAX_SS || SS(fs) < FF_MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
+#endif
+
+	/* Find an FAT volume on the hosting drive */
+	fmt = find_volume(fs, LD2PT(vol));
+	if (fmt == 4) return FR_DISK_ERR;		/* An error occurred in the disk I/O layer */
+	if (fmt >= 2) return FR_NO_FILESYSTEM;	/* No FAT volume is found */
+	bsect = fs->winsect;					/* Volume offset in the hosting physical drive */
+
+	/* An FAT volume is found (bsect). Following code initializes the filesystem object */
+
+#if FF_FS_EXFAT
+	if (fmt == 1) {
+		QWORD maxlba;
+		DWORD so, cv, bcl, i;
+
+		for (i = BPB_ZeroedEx; i < BPB_ZeroedEx + 53 && fs->win[i] == 0; i++) ;	/* Check zero filler */
+		if (i < BPB_ZeroedEx + 53) return FR_NO_FILESYSTEM;
+
+		if (ld_word(fs->win + BPB_FSVerEx) != 0x100) return FR_NO_FILESYSTEM;	/* Check exFAT version (must be version 1.0) */
+
+		if (1 << fs->win[BPB_BytsPerSecEx] != SS(fs)) {	/* (BPB_BytsPerSecEx must be equal to the physical sector size) */
+			return FR_NO_FILESYSTEM;
+		}
+
+		maxlba = ld_qword(fs->win + BPB_TotSecEx) + bsect;	/* Last LBA of the volume + 1 */
+		if (!FF_LBA64 && maxlba >= 0x100000000) return FR_NO_FILESYSTEM;	/* (It cannot be accessed in 32-bit LBA) */
+
+		fs->fsize = ld_dword(fs->win + BPB_FatSzEx);	/* Number of sectors per FAT */
+
+		fs->n_fats = fs->win[BPB_NumFATsEx];			/* Number of FATs */
+		if (fs->n_fats != 1) return FR_NO_FILESYSTEM;	/* (Supports only 1 FAT) */
+
+		fs->csize = 1 << fs->win[BPB_SecPerClusEx];		/* Cluster size */
+		if (fs->csize == 0)	return FR_NO_FILESYSTEM;	/* (Must be 1..32768 sectors) */
+
+		nclst = ld_dword(fs->win + BPB_NumClusEx);		/* Number of clusters */
+		if (nclst > MAX_EXFAT) return FR_NO_FILESYSTEM;	/* (Too many clusters) */
+		fs->n_fatent = nclst + 2;
+
+		/* Boundaries and Limits */
+		fs->volbase = bsect;
+		fs->database = bsect + ld_dword(fs->win + BPB_DataOfsEx);
+		fs->fatbase = bsect + ld_dword(fs->win + BPB_FatOfsEx);
+		if (maxlba < (QWORD)fs->database + nclst * fs->csize) return FR_NO_FILESYSTEM;	/* (Volume size must not be smaller than the size required) */
+		fs->dirbase = ld_dword(fs->win + BPB_RootClusEx);
+
+		/* Get bitmap location and check if it is contiguous (implementation assumption) */
+		so = i = 0;
+		for (;;) {	/* Find the bitmap entry in the root directory (in only first cluster) */
+			if (i == 0) {
+				if (so >= fs->csize) return FR_NO_FILESYSTEM;	/* Not found? */
+				if (move_window(fs, clst2sect(fs, (DWORD)fs->dirbase) + so) != FR_OK) return FR_DISK_ERR;
+				so++;
+			}
+			if (fs->win[i] == ET_BITMAP) break;			/* Is it a bitmap entry? */
+			i = (i + SZDIRE) % SS(fs);	/* Next entry */
+		}
+		bcl = ld_dword(fs->win + i + 20);				/* Bitmap cluster */
+		if (bcl < 2 || bcl >= fs->n_fatent) return FR_NO_FILESYSTEM;	/* (Wrong cluster#) */
+		fs->bitbase = fs->database + fs->csize * (bcl - 2);	/* Bitmap sector */
+		for (;;) {	/* Check if bitmap is contiguous */
+			if (move_window(fs, fs->fatbase + bcl / (SS(fs) / 4)) != FR_OK) return FR_DISK_ERR;
+			cv = ld_dword(fs->win + bcl % (SS(fs) / 4) * 4);
+			if (cv == 0xFFFFFFFF) break;				/* Last link? */
+			if (cv != ++bcl) return FR_NO_FILESYSTEM;	/* Fragmented bitmap? */
+		}
+
+#if !FF_FS_READONLY
+		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+#endif
+		fmt = FS_EXFAT;			/* FAT sub-type */
+	} else
+#endif	/* FF_FS_EXFAT */
+	{
+		if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_BytsPerSec must be equal to the physical sector size) */
+
+		fasize = ld_word(fs->win + BPB_FATSz16);		/* Number of sectors per FAT */
+		if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
+		fs->fsize = fasize;
+
+		fs->n_fats = fs->win[BPB_NumFATs];				/* Number of FATs */
+		if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM;	/* (Must be 1 or 2) */
+		fasize *= fs->n_fats;							/* Number of sectors for FAT area */
+
+		fs->csize = fs->win[BPB_SecPerClus];			/* Cluster size */
+		if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM;	/* (Must be power of 2) */
+
+		fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt);	/* Number of root directory entries */
+		if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM;	/* (Must be sector aligned) */
+
+		tsect = ld_word(fs->win + BPB_TotSec16);		/* Number of sectors on the volume */
+		if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
+
+		nrsv = ld_word(fs->win + BPB_RsvdSecCnt);		/* Number of reserved sectors */
+		if (nrsv == 0) return FR_NO_FILESYSTEM;			/* (Must not be 0) */
+
+		/* Determine the FAT sub type */
+		sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE);	/* RSV + FAT + DIR */
+		if (tsect < sysect) return FR_NO_FILESYSTEM;	/* (Invalid volume size) */
+		nclst = (tsect - sysect) / fs->csize;			/* Number of clusters */
+		if (nclst == 0) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
+		fmt = 0;
+		if (nclst <= MAX_FAT32) fmt = FS_FAT32;
+		if (nclst <= MAX_FAT16) fmt = FS_FAT16;
+		if (nclst <= MAX_FAT12) fmt = FS_FAT12;
+		if (fmt == 0) return FR_NO_FILESYSTEM;
+
+		/* Boundaries and Limits */
+		fs->n_fatent = nclst + 2;						/* Number of FAT entries */
+		fs->volbase = bsect;							/* Volume start sector */
+		fs->fatbase = bsect + nrsv; 					/* FAT start sector */
+		fs->database = bsect + sysect;					/* Data start sector */
+		if (fmt == FS_FAT32) {
+			if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM;	/* (Must be FAT32 revision 0.0) */
+			if (fs->n_rootdir != 0) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be 0) */
+			fs->dirbase = ld_dword(fs->win + BPB_RootClus32);	/* Root directory start cluster */
+			szbfat = fs->n_fatent * 4;					/* (Needed FAT size) */
+		} else {
+			if (fs->n_rootdir == 0)	return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must not be 0) */
+			fs->dirbase = fs->fatbase + fasize;			/* Root directory start sector */
+			szbfat = (fmt == FS_FAT16) ?				/* (Needed FAT size) */
+				fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+		}
+		if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM;	/* (BPB_FATSz must not be less than the size needed) */
+
+#if !FF_FS_READONLY
+		/* Get FSInfo if available */
+		fs->last_clst = fs->free_clst = 0xFFFFFFFF;		/* Initialize cluster allocation information */
+		fs->fsi_flag = 0x80;
+#if (FF_FS_NOFSINFO & 3) != 3
+		if (fmt == FS_FAT32				/* Allow to update FSInfo only if BPB_FSInfo32 == 1 */
+			&& ld_word(fs->win + BPB_FSInfo32) == 1
+			&& move_window(fs, bsect + 1) == FR_OK)
+		{
+			fs->fsi_flag = 0;
+			if (ld_word(fs->win + BS_55AA) == 0xAA55	/* Load FSInfo data if available */
+				&& ld_dword(fs->win + FSI_LeadSig) == 0x41615252
+				&& ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
+			{
+#if (FF_FS_NOFSINFO & 1) == 0
+				fs->free_clst = ld_dword(fs->win + FSI_Free_Count);
+#endif
+#if (FF_FS_NOFSINFO & 2) == 0
+				fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free);
+#endif
+			}
+		}
+#endif	/* (FF_FS_NOFSINFO & 3) != 3 */
+#endif	/* !FF_FS_READONLY */
+	}
+
+	fs->fs_type = (BYTE)fmt;/* FAT sub-type (the filesystem object gets valid) */
+	fs->id = ++Fsid;		/* Volume mount ID */
+#if FF_USE_LFN == 1
+	fs->lfnbuf = LfnBuf;	/* Static LFN working buffer */
+#if FF_FS_EXFAT
+	fs->dirbuf = DirBuf;	/* Static directory block scratchpad buuffer */
+#endif
+#endif
+#if FF_FS_RPATH != 0
+	fs->cdir = 0;			/* Initialize current directory */
+#endif
+#if FF_FS_LOCK				/* Clear file lock semaphores */
+	clear_share(fs);
+#endif
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/directory object is valid or not                    */
+/*-----------------------------------------------------------------------*/
+
+static FRESULT validate (	/* Returns FR_OK or FR_INVALID_OBJECT */
+	FFOBJID* obj,			/* Pointer to the FFOBJID, the 1st member in the FIL/DIR structure, to check validity */
+	FATFS** rfs				/* Pointer to pointer to the owner filesystem object to return */
+)
+{
+	FRESULT res = FR_INVALID_OBJECT;
+
+
+	if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) {	/* Test if the object is valid */
+#if FF_FS_REENTRANT
+		if (lock_volume(obj->fs, 0)) {	/* Take a grant to access the volume */
+			if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the hosting phsical drive is kept initialized */
+				res = FR_OK;
+			} else {
+				unlock_volume(obj->fs, FR_OK);	/* Invalidated volume, abort to access */
+			}
+		} else {	/* Could not take */
+			res = FR_TIMEOUT;
+		}
+#else
+		if (!(disk_status(obj->fs->pdrv) & STA_NOINIT)) { /* Test if the hosting phsical drive is kept initialized */
+			res = FR_OK;
+		}
+#endif
+	}
+	*rfs = (res == FR_OK) ? obj->fs : 0;	/* Return corresponding filesystem object if it is valid */
+	return res;
+}
+
+
+
+
+/*---------------------------------------------------------------------------
+
+   Public Functions (FatFs API)
+
+----------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+	FATFS* fs,			/* Pointer to the filesystem object to be registered (NULL:unmount)*/
+	const TCHAR* path,	/* Logical drive number to be mounted/unmounted */
+	BYTE opt			/* Mount option: 0=Do not mount (delayed mount), 1=Mount immediately */
+)
+{
+	FATFS *cfs;
+	int vol;
+	FRESULT res;
+	const TCHAR *rp = path;
+
+
+	/* Get volume ID (logical drive number) */
+	vol = get_ldnumber(&rp);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	cfs = FatFs[vol];			/* Pointer to the filesystem object of the volume */
+
+	if (cfs) {					/* Unregister current filesystem object if regsitered */
+		FatFs[vol] = 0;
+#if FF_FS_LOCK
+		clear_share(cfs);
+#endif
+#if FF_FS_REENTRANT				/* Discard mutex of the current volume */
+		ff_mutex_delete(vol);
+#endif
+		cfs->fs_type = 0;		/* Invalidate the filesystem object to be unregistered */
+	}
+
+	if (fs) {					/* Register new filesystem object */
+		fs->pdrv = LD2PD(vol);	/* Volume hosting physical drive */
+#if FF_FS_REENTRANT				/* Create a volume mutex */
+		fs->ldrv = (BYTE)vol;	/* Owner volume ID */
+		if (!ff_mutex_create(vol)) return FR_INT_ERR;
+#if FF_FS_LOCK
+		if (SysLock == 0) {		/* Create a system mutex if needed */
+			if (!ff_mutex_create(FF_VOLUMES)) {
+				ff_mutex_delete(vol);
+				return FR_INT_ERR;
+			}
+			SysLock = 1;		/* System mutex is ready */
+		}
+#endif
+#endif
+		fs->fs_type = 0;		/* Invalidate the new filesystem object */
+		FatFs[vol] = fs;		/* Register new fs object */
+	}
+
+	if (opt == 0) return FR_OK;	/* Do not mount now, it will be mounted in subsequent file functions */
+
+	res = mount_volume(&path, &fs, 0);	/* Force mounted the volume */
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+	FIL* fp,			/* Pointer to the blank file object */
+	const TCHAR* path,	/* Pointer to the file name */
+	BYTE mode			/* Access mode and open mode flags */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+#if !FF_FS_READONLY
+	DWORD cl, bcs, clst, tm;
+	LBA_t sc;
+	FSIZE_t ofs;
+#endif
+	DEF_NAMBUF
+
+
+	if (!fp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive number */
+	mode &= FF_FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND;
+	res = mount_volume(&path, &fs, mode);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+#if !FF_FS_READONLY	/* Read/Write configuration */
+		if (res == FR_OK) {
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Origin directory itself? */
+				res = FR_INVALID_NAME;
+			}
+#if FF_FS_LOCK
+			else {
+				res = chk_share(&dj, (mode & ~FA_READ) ? 1 : 0);	/* Check if the file can be used */
+			}
+#endif
+		}
+		/* Create or Open a file */
+		if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+			if (res != FR_OK) {					/* No file, create new */
+				if (res == FR_NO_FILE) {		/* There is no file to open, create a new entry */
+#if FF_FS_LOCK
+					res = enq_share() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+					res = dir_register(&dj);
+#endif
+				}
+				mode |= FA_CREATE_ALWAYS;		/* File is created */
+			}
+			else {								/* Any object with the same name is already existing */
+				if (dj.obj.attr & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or DIR) */
+					res = FR_DENIED;
+				} else {
+					if (mode & FA_CREATE_NEW) res = FR_EXIST;	/* Cannot create as new file */
+				}
+			}
+			if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) {	/* Truncate the file if overwrite mode */
+#if FF_FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					/* Get current allocation info */
+					fp->obj.fs = fs;
+					init_alloc_info(fs, &fp->obj);
+					/* Set directory entry block initial state */
+					memset(fs->dirbuf + 2, 0, 30);	/* Clear 85 entry except for NumSec */
+					memset(fs->dirbuf + 38, 0, 26);	/* Clear C0 entry except for NumName and NameHash */
+					fs->dirbuf[XDIR_Attr] = AM_ARC;
+					st_dword(fs->dirbuf + XDIR_CrtTime, GET_FATTIME());
+					fs->dirbuf[XDIR_GenFlags] = 1;
+					res = store_xdir(&dj);
+					if (res == FR_OK && fp->obj.sclust != 0) {	/* Remove the cluster chain if exist */
+						res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+						fs->last_clst = fp->obj.sclust - 1;		/* Reuse the cluster hole */
+					}
+				} else
+#endif
+				{
+					/* Set directory entry initial state */
+					tm = GET_FATTIME();					/* Set created time */
+					st_dword(dj.dir + DIR_CrtTime, tm);
+					st_dword(dj.dir + DIR_ModTime, tm);
+					cl = ld_clust(fs, dj.dir);			/* Get current cluster chain */
+					dj.dir[DIR_Attr] = AM_ARC;			/* Reset attribute */
+					st_clust(fs, dj.dir, 0);			/* Reset file allocation info */
+					st_dword(dj.dir + DIR_FileSize, 0);
+					fs->wflag = 1;
+					if (cl != 0) {						/* Remove the cluster chain if exist */
+						sc = fs->winsect;
+						res = remove_chain(&dj.obj, cl, 0);
+						if (res == FR_OK) {
+							res = move_window(fs, sc);
+							fs->last_clst = cl - 1;		/* Reuse the cluster hole */
+						}
+					}
+				}
+			}
+		}
+		else {	/* Open an existing file */
+			if (res == FR_OK) {					/* Is the object exsiting? */
+				if (dj.obj.attr & AM_DIR) {		/* File open against a directory */
+					res = FR_NO_FILE;
+				} else {
+					if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* Write mode open against R/O file */
+						res = FR_DENIED;
+					}
+				}
+			}
+		}
+		if (res == FR_OK) {
+			if (mode & FA_CREATE_ALWAYS) mode |= FA_MODIFIED;	/* Set file change flag if created or overwritten */
+			fp->dir_sect = fs->winsect;			/* Pointer to the directory entry */
+			fp->dir_ptr = dj.dir;
+#if FF_FS_LOCK
+			fp->obj.lockid = inc_share(&dj, (mode & ~FA_READ) ? 1 : 0);	/* Lock the file for this session */
+			if (fp->obj.lockid == 0) res = FR_INT_ERR;
+#endif
+		}
+#else		/* R/O configuration */
+		if (res == FR_OK) {
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Is it origin directory itself? */
+				res = FR_INVALID_NAME;
+			} else {
+				if (dj.obj.attr & AM_DIR) {		/* Is it a directory? */
+					res = FR_NO_FILE;
+				}
+			}
+		}
+#endif
+
+		if (res == FR_OK) {
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				fp->obj.c_scl = dj.obj.sclust;							/* Get containing directory info */
+				fp->obj.c_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+				fp->obj.c_ofs = dj.blk_ofs;
+				init_alloc_info(fs, &fp->obj);
+			} else
+#endif
+			{
+				fp->obj.sclust = ld_clust(fs, dj.dir);					/* Get object allocation info */
+				fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
+			}
+#if FF_USE_FASTSEEK
+			fp->cltbl = 0;		/* Disable fast seek mode */
+#endif
+			fp->obj.fs = fs;	/* Validate the file object */
+			fp->obj.id = fs->id;
+			fp->flag = mode;	/* Set file access mode */
+			fp->err = 0;		/* Clear error flag */
+			fp->sect = 0;		/* Invalidate current data sector */
+			fp->fptr = 0;		/* Set file pointer top of the file */
+#if !FF_FS_READONLY
+#if !FF_FS_TINY
+			memset(fp->buf, 0, sizeof fp->buf);	/* Clear sector buffer */
+#endif
+			if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) {	/* Seek to end of file if FA_OPEN_APPEND is specified */
+				fp->fptr = fp->obj.objsize;			/* Offset to seek */
+				bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size in byte */
+				clst = fp->obj.sclust;				/* Follow the cluster chain */
+				for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
+					clst = get_fat(&fp->obj, clst);
+					if (clst <= 1) res = FR_INT_ERR;
+					if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
+				}
+				fp->clust = clst;
+				if (res == FR_OK && ofs % SS(fs)) {	/* Fill sector buffer if not on the sector boundary */
+					sc = clst2sect(fs, clst);
+					if (sc == 0) {
+						res = FR_INT_ERR;
+					} else {
+						fp->sect = sc + (DWORD)(ofs / SS(fs));
+#if !FF_FS_TINY
+						if (disk_read(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR;
+#endif
+					}
+				}
+#if FF_FS_LOCK
+				if (res != FR_OK) dec_share(fp->obj.lockid); /* Decrement file open counter if seek failed */
+#endif
+			}
+#endif
+		}
+
+		FREE_NAMBUF();
+	}
+
+	if (res != FR_OK) fp->obj.fs = 0;	/* Invalidate file object on error */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+	FIL* fp, 	/* Open file to be read */
+	void* buff,	/* Data buffer to store the read data */
+	UINT btr,	/* Number of bytes to read */
+	UINT* br	/* Number of bytes read */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst;
+	LBA_t sect;
+	FSIZE_t remain;
+	UINT rcnt, cc, csect;
+	BYTE *rbuff = (BYTE*)buff;
+
+
+	*br = 0;	/* Clear read byte counter */
+	res = validate(&fp->obj, &fs);				/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
+	remain = fp->obj.objsize - fp->fptr;
+	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
+
+	for ( ; btr > 0; btr -= rcnt, *br += rcnt, rbuff += rcnt, fp->fptr += rcnt) {	/* Repeat until btr bytes read */
+		if (fp->fptr % SS(fs) == 0) {			/* On the sector boundary? */
+			csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (csect == 0) {					/* On the cluster boundary? */
+				if (fp->fptr == 0) {			/* On the top of the file? */
+					clst = fp->obj.sclust;		/* Follow cluster chain from the origin */
+				} else {						/* Middle or end of the file */
+#if FF_USE_FASTSEEK
+					if (fp->cltbl) {
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					} else
+#endif
+					{
+						clst = get_fat(&fp->obj, fp->clust);	/* Follow cluster chain on the FAT */
+					}
+				}
+				if (clst < 2) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;				/* Update current cluster */
+			}
+			sect = clst2sect(fs, fp->clust);	/* Get current sector */
+			if (sect == 0) ABORT(fs, FR_INT_ERR);
+			sect += csect;
+			cc = btr / SS(fs);					/* When remaining bytes >= sector size, */
+			if (cc > 0) {						/* Read maximum contiguous sectors directly */
+				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+					cc = fs->csize - csect;
+				}
+				if (disk_read(fs->pdrv, rbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if !FF_FS_READONLY && FF_FS_MINIMIZE <= 2		/* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if FF_FS_TINY
+				if (fs->wflag && fs->winsect - sect < cc) {
+					memcpy(rbuff + ((fs->winsect - sect) * SS(fs)), fs->win, SS(fs));
+				}
+#else
+				if ((fp->flag & FA_DIRTY) && fp->sect - sect < cc) {
+					memcpy(rbuff + ((fp->sect - sect) * SS(fs)), fp->buf, SS(fs));
+				}
+#endif
+#endif
+				rcnt = SS(fs) * cc;				/* Number of bytes transferred */
+				continue;
+			}
+#if !FF_FS_TINY
+			if (fp->sect != sect) {			/* Load data sector if not in cache */
+#if !FF_FS_READONLY
+				if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+					if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+					fp->flag &= (BYTE)~FA_DIRTY;
+				}
+#endif
+				if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
+			}
+#endif
+			fp->sect = sect;
+		}
+		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes remains in the sector */
+		if (rcnt > btr) rcnt = btr;					/* Clip it by btr if needed */
+#if FF_FS_TINY
+		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+		memcpy(rbuff, fs->win + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+#else
+		memcpy(rbuff, fp->buf + fp->fptr % SS(fs), rcnt);	/* Extract partial sector */
+#endif
+	}
+
+	LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+	FIL* fp,			/* Open file to be written */
+	const void* buff,	/* Data to be written */
+	UINT btw,			/* Number of bytes to write */
+	UINT* bw			/* Number of bytes written */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst;
+	LBA_t sect;
+	UINT wcnt, cc, csect;
+	const BYTE *wbuff = (const BYTE*)buff;
+
+
+	*bw = 0;	/* Clear write byte counter */
+	res = validate(&fp->obj, &fs);			/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);	/* Check validity */
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	/* Check fptr wrap-around (file size cannot reach 4 GiB at FAT volume) */
+	if ((!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
+		btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
+	}
+
+	for ( ; btw > 0; btw -= wcnt, *bw += wcnt, wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize) {	/* Repeat until all data written */
+		if (fp->fptr % SS(fs) == 0) {		/* On the sector boundary? */
+			csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1);	/* Sector offset in the cluster */
+			if (csect == 0) {				/* On the cluster boundary? */
+				if (fp->fptr == 0) {		/* On the top of the file? */
+					clst = fp->obj.sclust;	/* Follow from the origin */
+					if (clst == 0) {		/* If no cluster is allocated, */
+						clst = create_chain(&fp->obj, 0);	/* create a new cluster chain */
+					}
+				} else {					/* On the middle or end of the file */
+#if FF_USE_FASTSEEK
+					if (fp->cltbl) {
+						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
+					} else
+#endif
+					{
+						clst = create_chain(&fp->obj, fp->clust);	/* Follow or stretch cluster chain on the FAT */
+					}
+				}
+				if (clst == 0) break;		/* Could not allocate a new cluster (disk full) */
+				if (clst == 1) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;			/* Update current cluster */
+				if (fp->obj.sclust == 0) fp->obj.sclust = clst;	/* Set start cluster if the first write */
+			}
+#if FF_FS_TINY
+			if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Write-back sector cache */
+#else
+			if (fp->flag & FA_DIRTY) {		/* Write-back sector cache */
+				if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			sect = clst2sect(fs, fp->clust);	/* Get current sector */
+			if (sect == 0) ABORT(fs, FR_INT_ERR);
+			sect += csect;
+			cc = btw / SS(fs);				/* When remaining bytes >= sector size, */
+			if (cc > 0) {					/* Write maximum contiguous sectors directly */
+				if (csect + cc > fs->csize) {	/* Clip at cluster boundary */
+					cc = fs->csize - csect;
+				}
+				if (disk_write(fs->pdrv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
+#if FF_FS_MINIMIZE <= 2
+#if FF_FS_TINY
+				if (fs->winsect - sect < cc) {	/* Refill sector cache if it gets invalidated by the direct write */
+					memcpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs));
+					fs->wflag = 0;
+				}
+#else
+				if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+					memcpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
+					fp->flag &= (BYTE)~FA_DIRTY;
+				}
+#endif
+#endif
+				wcnt = SS(fs) * cc;		/* Number of bytes transferred */
+				continue;
+			}
+#if FF_FS_TINY
+			if (fp->fptr >= fp->obj.objsize) {	/* Avoid silly cache filling on the growing edge */
+				if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);
+				fs->winsect = sect;
+			}
+#else
+			if (fp->sect != sect && 		/* Fill sector cache with file data */
+				fp->fptr < fp->obj.objsize &&
+				disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) {
+					ABORT(fs, FR_DISK_ERR);
+			}
+#endif
+			fp->sect = sect;
+		}
+		wcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes remains in the sector */
+		if (wcnt > btw) wcnt = btw;					/* Clip it by btw if needed */
+#if FF_FS_TINY
+		if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window */
+		memcpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+		fs->wflag = 1;
+#else
+		memcpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt);	/* Fit data to the sector */
+		fp->flag |= FA_DIRTY;
+#endif
+	}
+
+	fp->flag |= FA_MODIFIED;				/* Set file change flag */
+
+	LEAVE_FF(fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File                                                  */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+	FIL* fp		/* Open file to be synced */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD tm;
+	BYTE *dir;
+
+
+	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+	if (res == FR_OK) {
+		if (fp->flag & FA_MODIFIED) {	/* Is there any change to the file? */
+#if !FF_FS_TINY
+			if (fp->flag & FA_DIRTY) {	/* Write-back cached data if needed */
+				if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			/* Update the directory entry */
+			tm = GET_FATTIME();				/* Modified time */
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				res = fill_first_frag(&fp->obj);	/* Fill first fragment on the FAT if needed */
+				if (res == FR_OK) {
+					res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+				}
+				if (res == FR_OK) {
+					DIR dj;
+					DEF_NAMBUF
+
+					INIT_NAMBUF(fs);
+					res = load_obj_xdir(&dj, &fp->obj);	/* Load directory entry block */
+					if (res == FR_OK) {
+						fs->dirbuf[XDIR_Attr] |= AM_ARC;				/* Set archive attribute to indicate that the file has been changed */
+						fs->dirbuf[XDIR_GenFlags] = fp->obj.stat | 1;	/* Update file allocation information */
+						st_dword(fs->dirbuf + XDIR_FstClus, fp->obj.sclust);		/* Update start cluster */
+						st_qword(fs->dirbuf + XDIR_FileSize, fp->obj.objsize);		/* Update file size */
+						st_qword(fs->dirbuf + XDIR_ValidFileSize, fp->obj.objsize);	/* (FatFs does not support Valid File Size feature) */
+						st_dword(fs->dirbuf + XDIR_ModTime, tm);		/* Update modified time */
+						fs->dirbuf[XDIR_ModTime10] = 0;
+						st_dword(fs->dirbuf + XDIR_AccTime, 0);
+						res = store_xdir(&dj);	/* Restore it to the directory */
+						if (res == FR_OK) {
+							res = sync_fs(fs);
+							fp->flag &= (BYTE)~FA_MODIFIED;
+						}
+					}
+					FREE_NAMBUF();
+				}
+			} else
+#endif
+			{
+				res = move_window(fs, fp->dir_sect);
+				if (res == FR_OK) {
+					dir = fp->dir_ptr;
+					dir[DIR_Attr] |= AM_ARC;						/* Set archive attribute to indicate that the file has been changed */
+					st_clust(fp->obj.fs, dir, fp->obj.sclust);		/* Update file allocation information  */
+					st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize);	/* Update file size */
+					st_dword(dir + DIR_ModTime, tm);				/* Update modified time */
+					st_word(dir + DIR_LstAccDate, 0);
+					fs->wflag = 1;
+					res = sync_fs(fs);					/* Restore it to the directory */
+					fp->flag &= (BYTE)~FA_MODIFIED;
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !FF_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File                                                            */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+	FIL* fp		/* Open file to be closed */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+
+#if !FF_FS_READONLY
+	res = f_sync(fp);					/* Flush cached data */
+	if (res == FR_OK)
+#endif
+	{
+		res = validate(&fp->obj, &fs);	/* Lock volume */
+		if (res == FR_OK) {
+#if FF_FS_LOCK
+			res = dec_share(fp->obj.lockid);		/* Decrement file open counter */
+			if (res == FR_OK) fp->obj.fs = 0;	/* Invalidate file object */
+#else
+			fp->obj.fs = 0;	/* Invalidate file object */
+#endif
+#if FF_FS_REENTRANT
+			unlock_volume(fs, FR_OK);		/* Unlock volume */
+#endif
+		}
+	}
+	return res;
+}
+
+
+
+
+#if FF_FS_RPATH >= 1
+/*-----------------------------------------------------------------------*/
+/* Change Current Directory or Current Drive, Get Current Directory      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chdrive (
+	const TCHAR* path		/* Drive number to set */
+)
+{
+	int vol;
+
+
+	/* Get logical drive number */
+	vol = get_ldnumber(&path);
+	if (vol < 0) return FR_INVALID_DRIVE;
+	CurrVol = (BYTE)vol;	/* Set it as current volume */
+
+	return FR_OK;
+}
+
+
+
+FRESULT f_chdir (
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+#if FF_STR_VOLUME_ID == 2
+	UINT i;
+#endif
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = mount_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);		/* Follow the path */
+		if (res == FR_OK) {					/* Follow completed */
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* Is it the start directory itself? */
+				fs->cdir = dj.obj.sclust;
+#if FF_FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					fs->cdc_scl = dj.obj.c_scl;
+					fs->cdc_size = dj.obj.c_size;
+					fs->cdc_ofs = dj.obj.c_ofs;
+				}
+#endif
+			} else {
+				if (dj.obj.attr & AM_DIR) {	/* It is a sub-directory */
+#if FF_FS_EXFAT
+					if (fs->fs_type == FS_EXFAT) {
+						fs->cdir = ld_dword(fs->dirbuf + XDIR_FstClus);		/* Sub-directory cluster */
+						fs->cdc_scl = dj.obj.sclust;						/* Save containing directory information */
+						fs->cdc_size = ((DWORD)dj.obj.objsize & 0xFFFFFF00) | dj.obj.stat;
+						fs->cdc_ofs = dj.blk_ofs;
+					} else
+#endif
+					{
+						fs->cdir = ld_clust(fs, dj.dir);					/* Sub-directory cluster */
+					}
+				} else {
+					res = FR_NO_PATH;		/* Reached but a file */
+				}
+			}
+		}
+		FREE_NAMBUF();
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+#if FF_STR_VOLUME_ID == 2	/* Also current drive is changed if in Unix style volume ID */
+		if (res == FR_OK) {
+			for (i = FF_VOLUMES - 1; i && fs != FatFs[i]; i--) ;	/* Set current drive */
+			CurrVol = (BYTE)i;
+		}
+#endif
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+#if FF_FS_RPATH >= 2
+FRESULT f_getcwd (
+	TCHAR* buff,	/* Pointer to the directory path */
+	UINT len		/* Size of buff in unit of TCHAR */
+)
+{
+	FRESULT res;
+	DIR dj;
+	FATFS *fs;
+	UINT i, n;
+	DWORD ccl;
+	TCHAR *tp = buff;
+#if FF_VOLUMES >= 2
+	UINT vl;
+#if FF_STR_VOLUME_ID
+	const char *vp;
+#endif
+#endif
+	FILINFO fno;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	buff[0] = 0;	/* Set null string to get current volume */
+	res = mount_volume((const TCHAR**)&buff, &fs, 0);	/* Get current volume */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+
+		/* Follow parent directories and create the path */
+		i = len;			/* Bottom of buffer (directory stack base) */
+		if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {	/* (Cannot do getcwd on exFAT and returns root path) */
+			dj.obj.sclust = fs->cdir;				/* Start to follow upper directory from current directory */
+			while ((ccl = dj.obj.sclust) != 0) {	/* Repeat while current directory is a sub-directory */
+				res = dir_sdi(&dj, 1 * SZDIRE);	/* Get parent directory */
+				if (res != FR_OK) break;
+				res = move_window(fs, dj.sect);
+				if (res != FR_OK) break;
+				dj.obj.sclust = ld_clust(fs, dj.dir);	/* Goto parent directory */
+				res = dir_sdi(&dj, 0);
+				if (res != FR_OK) break;
+				do {							/* Find the entry links to the child directory */
+					res = DIR_READ_FILE(&dj);
+					if (res != FR_OK) break;
+					if (ccl == ld_clust(fs, dj.dir)) break;	/* Found the entry */
+					res = dir_next(&dj, 0);
+				} while (res == FR_OK);
+				if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+				if (res != FR_OK) break;
+				get_fileinfo(&dj, &fno);		/* Get the directory name and push it to the buffer */
+				for (n = 0; fno.fname[n]; n++) ;	/* Name length */
+				if (i < n + 1) {	/* Insufficient space to store the path name? */
+					res = FR_NOT_ENOUGH_CORE; break;
+				}
+				while (n) buff[--i] = fno.fname[--n];	/* Stack the name */
+				buff[--i] = '/';
+			}
+		}
+		if (res == FR_OK) {
+			if (i == len) buff[--i] = '/';	/* Is it the root-directory? */
+#if FF_VOLUMES >= 2			/* Put drive prefix */
+			vl = 0;
+#if FF_STR_VOLUME_ID >= 1	/* String volume ID */
+			for (n = 0, vp = (const char*)VolumeStr[CurrVol]; vp[n]; n++) ;
+			if (i >= n + 2) {
+				if (FF_STR_VOLUME_ID == 2) *tp++ = (TCHAR)'/';
+				for (vl = 0; vl < n; *tp++ = (TCHAR)vp[vl], vl++) ;
+				if (FF_STR_VOLUME_ID == 1) *tp++ = (TCHAR)':';
+				vl++;
+			}
+#else						/* Numeric volume ID */
+			if (i >= 3) {
+				*tp++ = (TCHAR)'0' + CurrVol;
+				*tp++ = (TCHAR)':';
+				vl = 2;
+			}
+#endif
+			if (vl == 0) res = FR_NOT_ENOUGH_CORE;
+#endif
+			/* Add current directory path */
+			if (res == FR_OK) {
+				do {	/* Copy stacked path string */
+					*tp++ = buff[i++];
+				} while (i < len);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	*tp = 0;
+	LEAVE_FF(fs, res);
+}
+
+#endif /* FF_FS_RPATH >= 2 */
+#endif /* FF_FS_RPATH >= 1 */
+
+
+
+#if FF_FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File Read/Write Pointer                                          */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t ofs		/* File pointer from top of file */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst, bcs;
+	LBA_t nsect;
+	FSIZE_t ifptr;
+#if FF_USE_FASTSEEK
+	DWORD cl, pcl, ncl, tcl, tlen, ulen;
+	DWORD *tbl;
+	LBA_t dsc;
+#endif
+
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res == FR_OK) res = (FRESULT)fp->err;
+#if FF_FS_EXFAT && !FF_FS_READONLY
+	if (res == FR_OK && fs->fs_type == FS_EXFAT) {
+		res = fill_last_frag(&fp->obj, fp->clust, 0xFFFFFFFF);	/* Fill last fragment on the FAT if needed */
+	}
+#endif
+	if (res != FR_OK) LEAVE_FF(fs, res);
+
+#if FF_USE_FASTSEEK
+	if (fp->cltbl) {	/* Fast seek */
+		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
+			tbl = fp->cltbl;
+			tlen = *tbl++; ulen = 2;	/* Given table size and required table size */
+			cl = fp->obj.sclust;		/* Origin of the chain */
+			if (cl != 0) {
+				do {
+					/* Get a fragment */
+					tcl = cl; ncl = 0; ulen += 2;	/* Top, length and used items */
+					do {
+						pcl = cl; ncl++;
+						cl = get_fat(&fp->obj, cl);
+						if (cl <= 1) ABORT(fs, FR_INT_ERR);
+						if (cl == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					} while (cl == pcl + 1);
+					if (ulen <= tlen) {		/* Store the length and top of the fragment */
+						*tbl++ = ncl; *tbl++ = tcl;
+					}
+				} while (cl < fs->n_fatent);	/* Repeat until end of chain */
+			}
+			*fp->cltbl = ulen;	/* Number of items used */
+			if (ulen <= tlen) {
+				*tbl = 0;		/* Terminate table */
+			} else {
+				res = FR_NOT_ENOUGH_CORE;	/* Given table size is smaller than required */
+			}
+		} else {						/* Fast seek */
+			if (ofs > fp->obj.objsize) ofs = fp->obj.objsize;	/* Clip offset at the file size */
+			fp->fptr = ofs;				/* Set file pointer */
+			if (ofs > 0) {
+				fp->clust = clmt_clust(fp, ofs - 1);
+				dsc = clst2sect(fs, fp->clust);
+				if (dsc == 0) ABORT(fs, FR_INT_ERR);
+				dsc += (DWORD)((ofs - 1) / SS(fs)) & (fs->csize - 1);
+				if (fp->fptr % SS(fs) && dsc != fp->sect) {	/* Refill sector cache if needed */
+#if !FF_FS_TINY
+#if !FF_FS_READONLY
+					if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+						if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+						fp->flag &= (BYTE)~FA_DIRTY;
+					}
+#endif
+					if (disk_read(fs->pdrv, fp->buf, dsc, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Load current sector */
+#endif
+					fp->sect = dsc;
+				}
+			}
+		}
+	} else
+#endif
+
+	/* Normal Seek */
+	{
+#if FF_FS_EXFAT
+		if (fs->fs_type != FS_EXFAT && ofs >= 0x100000000) ofs = 0xFFFFFFFF;	/* Clip at 4 GiB - 1 if at FATxx */
+#endif
+		if (ofs > fp->obj.objsize && (FF_FS_READONLY || !(fp->flag & FA_WRITE))) {	/* In read-only mode, clip offset with the file size */
+			ofs = fp->obj.objsize;
+		}
+		ifptr = fp->fptr;
+		fp->fptr = nsect = 0;
+		if (ofs > 0) {
+			bcs = (DWORD)fs->csize * SS(fs);	/* Cluster size (byte) */
+			if (ifptr > 0 &&
+				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+				fp->fptr = (ifptr - 1) & ~(FSIZE_t)(bcs - 1);	/* start from the current cluster */
+				ofs -= fp->fptr;
+				clst = fp->clust;
+			} else {									/* When seek to back cluster, */
+				clst = fp->obj.sclust;					/* start from the first cluster */
+#if !FF_FS_READONLY
+				if (clst == 0) {						/* If no cluster chain, create a new chain */
+					clst = create_chain(&fp->obj, 0);
+					if (clst == 1) ABORT(fs, FR_INT_ERR);
+					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					fp->obj.sclust = clst;
+				}
+#endif
+				fp->clust = clst;
+			}
+			if (clst != 0) {
+				while (ofs > bcs) {						/* Cluster following loop */
+					ofs -= bcs; fp->fptr += bcs;
+#if !FF_FS_READONLY
+					if (fp->flag & FA_WRITE) {			/* Check if in write mode or not */
+						if (FF_FS_EXFAT && fp->fptr > fp->obj.objsize) {	/* No FAT chain object needs correct objsize to generate FAT value */
+							fp->obj.objsize = fp->fptr;
+							fp->flag |= FA_MODIFIED;
+						}
+						clst = create_chain(&fp->obj, clst);	/* Follow chain with forceed stretch */
+						if (clst == 0) {				/* Clip file size in case of disk full */
+							ofs = 0; break;
+						}
+					} else
+#endif
+					{
+						clst = get_fat(&fp->obj, clst);	/* Follow cluster chain if not in write mode */
+					}
+					if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+					if (clst <= 1 || clst >= fs->n_fatent) ABORT(fs, FR_INT_ERR);
+					fp->clust = clst;
+				}
+				fp->fptr += ofs;
+				if (ofs % SS(fs)) {
+					nsect = clst2sect(fs, clst);	/* Current sector */
+					if (nsect == 0) ABORT(fs, FR_INT_ERR);
+					nsect += (DWORD)(ofs / SS(fs));
+				}
+			}
+		}
+		if (!FF_FS_READONLY && fp->fptr > fp->obj.objsize) {	/* Set file change flag if the file size is extended */
+			fp->obj.objsize = fp->fptr;
+			fp->flag |= FA_MODIFIED;
+		}
+		if (fp->fptr % SS(fs) && nsect != fp->sect) {	/* Fill sector cache if needed */
+#if !FF_FS_TINY
+#if !FF_FS_READONLY
+			if (fp->flag & FA_DIRTY) {			/* Write-back dirty sector cache */
+				if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			if (disk_read(fs->pdrv, fp->buf, nsect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);	/* Fill sector cache */
+#endif
+			fp->sect = nsect;
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if FF_FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object                                             */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+	DIR* dp,			/* Pointer to directory object to create */
+	const TCHAR* path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	if (!dp) return FR_INVALID_OBJECT;
+
+	/* Get logical drive */
+	res = mount_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		dp->obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(dp, path);			/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (!(dp->fn[NSFLAG] & NS_NONAME)) {	/* It is not the origin directory itself */
+				if (dp->obj.attr & AM_DIR) {		/* This object is a sub-directory */
+#if FF_FS_EXFAT
+					if (fs->fs_type == FS_EXFAT) {
+						dp->obj.c_scl = dp->obj.sclust;	/* Get containing directory inforamation */
+						dp->obj.c_size = ((DWORD)dp->obj.objsize & 0xFFFFFF00) | dp->obj.stat;
+						dp->obj.c_ofs = dp->blk_ofs;
+						init_alloc_info(fs, &dp->obj);	/* Get object allocation info */
+					} else
+#endif
+					{
+						dp->obj.sclust = ld_clust(fs, dp->dir);	/* Get object allocation info */
+					}
+				} else {						/* This object is a file */
+					res = FR_NO_PATH;
+				}
+			}
+			if (res == FR_OK) {
+				dp->obj.id = fs->id;
+				res = dir_sdi(dp, 0);			/* Rewind directory */
+#if FF_FS_LOCK
+				if (res == FR_OK) {
+					if (dp->obj.sclust != 0) {
+						dp->obj.lockid = inc_share(dp, 0);	/* Lock the sub directory */
+						if (!dp->obj.lockid) res = FR_TOO_MANY_OPEN_FILES;
+					} else {
+						dp->obj.lockid = 0;	/* Root directory need not to be locked */
+					}
+				}
+#endif
+			}
+		}
+		FREE_NAMBUF();
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+	if (res != FR_OK) dp->obj.fs = 0;		/* Invalidate the directory object if function failed */
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close Directory                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_closedir (
+	DIR *dp		/* Pointer to the directory object to be closed */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+
+
+	res = validate(&dp->obj, &fs);	/* Check validity of the file object */
+	if (res == FR_OK) {
+#if FF_FS_LOCK
+		if (dp->obj.lockid) res = dec_share(dp->obj.lockid);	/* Decrement sub-directory open counter */
+		if (res == FR_OK) dp->obj.fs = 0;	/* Invalidate directory object */
+#else
+		dp->obj.fs = 0;	/* Invalidate directory object */
+#endif
+#if FF_FS_REENTRANT
+		unlock_volume(fs, FR_OK);	/* Unlock volume */
+#endif
+	}
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entries in Sequence                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+	DIR* dp,			/* Pointer to the open directory object */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DEF_NAMBUF
+
+
+	res = validate(&dp->obj, &fs);	/* Check validity of the directory object */
+	if (res == FR_OK) {
+		if (!fno) {
+			res = dir_sdi(dp, 0);		/* Rewind the directory object */
+		} else {
+			INIT_NAMBUF(fs);
+			res = DIR_READ_FILE(dp);		/* Read an item */
+			if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory */
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dp, fno);		/* Get the object information */
+				res = dir_next(dp, 0);		/* Increment index for next */
+				if (res == FR_NO_FILE) res = FR_OK;	/* Ignore end of directory now */
+			}
+			FREE_NAMBUF();
+		}
+	}
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if FF_USE_FIND
+/*-----------------------------------------------------------------------*/
+/* Find Next File                                                        */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findnext (
+	DIR* dp,		/* Pointer to the open directory object */
+	FILINFO* fno	/* Pointer to the file information structure */
+)
+{
+	FRESULT res;
+
+
+	for (;;) {
+		res = f_readdir(dp, fno);		/* Get a directory item */
+		if (res != FR_OK || !fno || !fno->fname[0]) break;	/* Terminate if any error or end of directory */
+		if (pattern_match(dp->pat, fno->fname, 0, FIND_RECURS)) break;		/* Test for the file name */
+#if FF_USE_LFN && FF_USE_FIND == 2
+		if (pattern_match(dp->pat, fno->altname, 0, FIND_RECURS)) break;	/* Test for alternative name if exist */
+#endif
+	}
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Find First File                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_findfirst (
+	DIR* dp,				/* Pointer to the blank directory object */
+	FILINFO* fno,			/* Pointer to the file information structure */
+	const TCHAR* path,		/* Pointer to the directory to open */
+	const TCHAR* pattern	/* Pointer to the matching pattern */
+)
+{
+	FRESULT res;
+
+
+	dp->pat = pattern;		/* Save pointer to pattern string */
+	res = f_opendir(dp, path);		/* Open the target directory */
+	if (res == FR_OK) {
+		res = f_findnext(dp, fno);	/* Find the first item */
+	}
+	return res;
+}
+
+#endif	/* FF_USE_FIND */
+
+
+
+#if FF_FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status                                                       */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+	const TCHAR* path,	/* Pointer to the file path */
+	FILINFO* fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	DIR dj;
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = mount_volume(&path, &dj.obj.fs, 0);
+	if (res == FR_OK) {
+		INIT_NAMBUF(dj.obj.fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK) {				/* Follow completed */
+			if (dj.fn[NSFLAG] & NS_NONAME) {	/* It is origin directory */
+				res = FR_INVALID_NAME;
+			} else {							/* Found an object */
+				if (fno) get_fileinfo(&dj, fno);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(dj.obj.fs, res);
+}
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters                                           */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+	const TCHAR* path,	/* Logical drive number */
+	DWORD* nclst,		/* Pointer to a variable to return number of free clusters */
+	FATFS** fatfs		/* Pointer to return pointer to corresponding filesystem object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD nfree, clst, stat;
+	LBA_t sect;
+	UINT i;
+	FFOBJID obj;
+
+
+	/* Get logical drive */
+	res = mount_volume(&path, &fs, 0);
+	if (res == FR_OK) {
+		*fatfs = fs;				/* Return ptr to the fs object */
+		/* If free_clst is valid, return it without full FAT scan */
+		if (fs->free_clst <= fs->n_fatent - 2) {
+			*nclst = fs->free_clst;
+		} else {
+			/* Scan FAT to obtain number of free clusters */
+			nfree = 0;
+			if (fs->fs_type == FS_FAT12) {	/* FAT12: Scan bit field FAT entries */
+				clst = 2; obj.fs = fs;
+				do {
+					stat = get_fat(&obj, clst);
+					if (stat == 0xFFFFFFFF) {
+						res = FR_DISK_ERR; break;
+					}
+					if (stat == 1) {
+						res = FR_INT_ERR; break;
+					}
+					if (stat == 0) nfree++;
+				} while (++clst < fs->n_fatent);
+			} else {
+#if FF_FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {	/* exFAT: Scan allocation bitmap */
+					BYTE bm;
+					UINT b;
+
+					clst = fs->n_fatent - 2;	/* Number of clusters */
+					sect = fs->bitbase;			/* Bitmap sector */
+					i = 0;						/* Offset in the sector */
+					do {	/* Counts numbuer of bits with zero in the bitmap */
+						if (i == 0) {	/* New sector? */
+							res = move_window(fs, sect++);
+							if (res != FR_OK) break;
+						}
+						for (b = 8, bm = ~fs->win[i]; b && clst; b--, clst--) {
+							nfree += bm & 1;
+							bm >>= 1;
+						}
+						i = (i + 1) % SS(fs);
+					} while (clst);
+				} else
+#endif
+				{	/* FAT16/32: Scan WORD/DWORD FAT entries */
+					clst = fs->n_fatent;	/* Number of entries */
+					sect = fs->fatbase;		/* Top of the FAT */
+					i = 0;					/* Offset in the sector */
+					do {	/* Counts numbuer of entries with zero in the FAT */
+						if (i == 0) {	/* New sector? */
+							res = move_window(fs, sect++);
+							if (res != FR_OK) break;
+						}
+						if (fs->fs_type == FS_FAT16) {
+							if (ld_word(fs->win + i) == 0) nfree++;
+							i += 2;
+						} else {
+							if ((ld_dword(fs->win + i) & 0x0FFFFFFF) == 0) nfree++;
+							i += 4;
+						}
+						i %= SS(fs);
+					} while (--clst);
+				}
+			}
+			if (res == FR_OK) {		/* Update parameters if succeeded */
+				*nclst = nfree;			/* Return the free clusters */
+				fs->free_clst = nfree;	/* Now free_clst is valid */
+				fs->fsi_flag |= 1;		/* FAT32: FSInfo is to be updated */
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File                                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD ncl;
+
+
+	res = validate(&fp->obj, &fs);	/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	if (fp->fptr < fp->obj.objsize) {	/* Process when fptr is not on the eof */
+		if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
+			res = remove_chain(&fp->obj, fp->obj.sclust, 0);
+			fp->obj.sclust = 0;
+		} else {				/* When truncate a part of the file, remove remaining clusters */
+			ncl = get_fat(&fp->obj, fp->clust);
+			res = FR_OK;
+			if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+			if (ncl == 1) res = FR_INT_ERR;
+			if (res == FR_OK && ncl < fs->n_fatent) {
+				res = remove_chain(&fp->obj, ncl, fp->clust);
+			}
+		}
+		fp->obj.objsize = fp->fptr;	/* Set file size to current read/write point */
+		fp->flag |= FA_MODIFIED;
+#if !FF_FS_TINY
+		if (res == FR_OK && (fp->flag & FA_DIRTY)) {
+			if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) {
+				res = FR_DISK_ERR;
+			} else {
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+		}
+#endif
+		if (res != FR_OK) ABORT(fs, res);
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File/Directory                                               */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+	const TCHAR* path		/* Pointer to the file or directory path */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj, sdj;
+	DWORD dclst = 0;
+#if FF_FS_EXFAT
+	FFOBJID obj;
+#endif
+	DEF_NAMBUF
+
+
+	/* Get logical drive */
+	res = mount_volume(&path, &fs, FA_WRITE);
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);		/* Follow the file path */
+		if (FF_FS_RPATH && res == FR_OK && (dj.fn[NSFLAG] & NS_DOT)) {
+			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
+		}
+#if FF_FS_LOCK
+		if (res == FR_OK) res = chk_share(&dj, 2);	/* Check if it is an open object */
+#endif
+		if (res == FR_OK) {					/* The object is accessible */
+			if (dj.fn[NSFLAG] & NS_NONAME) {
+				res = FR_INVALID_NAME;		/* Cannot remove the origin directory */
+			} else {
+				if (dj.obj.attr & AM_RDO) {
+					res = FR_DENIED;		/* Cannot remove R/O object */
+				}
+			}
+			if (res == FR_OK) {
+#if FF_FS_EXFAT
+				obj.fs = fs;
+				if (fs->fs_type == FS_EXFAT) {
+					init_alloc_info(fs, &obj);
+					dclst = obj.sclust;
+				} else
+#endif
+				{
+					dclst = ld_clust(fs, dj.dir);
+				}
+				if (dj.obj.attr & AM_DIR) {			/* Is it a sub-directory? */
+#if FF_FS_RPATH != 0
+					if (dclst == fs->cdir) {	 	/* Is it the current directory? */
+						res = FR_DENIED;
+					} else
+#endif
+					{
+						sdj.obj.fs = fs;			/* Open the sub-directory */
+						sdj.obj.sclust = dclst;
+#if FF_FS_EXFAT
+						if (fs->fs_type == FS_EXFAT) {
+							sdj.obj.objsize = obj.objsize;
+							sdj.obj.stat = obj.stat;
+						}
+#endif
+						res = dir_sdi(&sdj, 0);
+						if (res == FR_OK) {
+							res = DIR_READ_FILE(&sdj);			/* Test if the directory is empty */
+							if (res == FR_OK) res = FR_DENIED;	/* Not empty? */
+							if (res == FR_NO_FILE) res = FR_OK;	/* Empty? */
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&dj);			/* Remove the directory entry */
+				if (res == FR_OK && dclst != 0) {	/* Remove the cluster chain if exist */
+#if FF_FS_EXFAT
+					res = remove_chain(&obj, dclst, 0);
+#else
+					res = remove_chain(&dj.obj, dclst, 0);
+#endif
+				}
+				if (res == FR_OK) res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory                                                    */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+	const TCHAR* path		/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj;
+	FFOBJID sobj;
+	DWORD dcl, pcl, tm;
+	DEF_NAMBUF
+
+
+	res = mount_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);			/* Follow the file path */
+		if (res == FR_OK) res = FR_EXIST;		/* Name collision? */
+		if (FF_FS_RPATH && res == FR_NO_FILE && (dj.fn[NSFLAG] & NS_DOT)) {	/* Invalid name? */
+			res = FR_INVALID_NAME;
+		}
+		if (res == FR_NO_FILE) {				/* It is clear to create a new directory */
+			sobj.fs = fs;						/* New object id to create a new chain */
+			dcl = create_chain(&sobj, 0);		/* Allocate a cluster for the new directory */
+			res = FR_OK;
+			if (dcl == 0) res = FR_DENIED;		/* No space to allocate a new cluster? */
+			if (dcl == 1) res = FR_INT_ERR;		/* Any insanity? */
+			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;	/* Disk error? */
+			tm = GET_FATTIME();
+			if (res == FR_OK) {
+				res = dir_clear(fs, dcl);		/* Clean up the new table */
+				if (res == FR_OK) {
+					if (!FF_FS_EXFAT || fs->fs_type != FS_EXFAT) {	/* Create dot entries (FAT only) */
+						memset(fs->win + DIR_Name, ' ', 11);	/* Create "." entry */
+						fs->win[DIR_Name] = '.';
+						fs->win[DIR_Attr] = AM_DIR;
+						st_dword(fs->win + DIR_ModTime, tm);
+						st_clust(fs, fs->win, dcl);
+						memcpy(fs->win + SZDIRE, fs->win, SZDIRE);	/* Create ".." entry */
+						fs->win[SZDIRE + 1] = '.'; pcl = dj.obj.sclust;
+						st_clust(fs, fs->win + SZDIRE, pcl);
+						fs->wflag = 1;
+					}
+					res = dir_register(&dj);	/* Register the object to the parent directoy */
+				}
+			}
+			if (res == FR_OK) {
+#if FF_FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {	/* Initialize directory entry block */
+					st_dword(fs->dirbuf + XDIR_ModTime, tm);	/* Created time */
+					st_dword(fs->dirbuf + XDIR_FstClus, dcl);	/* Table start cluster */
+					st_dword(fs->dirbuf + XDIR_FileSize, (DWORD)fs->csize * SS(fs));	/* Directory size needs to be valid */
+					st_dword(fs->dirbuf + XDIR_ValidFileSize, (DWORD)fs->csize * SS(fs));
+					fs->dirbuf[XDIR_GenFlags] = 3;				/* Initialize the object flag */
+					fs->dirbuf[XDIR_Attr] = AM_DIR;				/* Attribute */
+					res = store_xdir(&dj);
+				} else
+#endif
+				{
+					st_dword(dj.dir + DIR_ModTime, tm);	/* Created time */
+					st_clust(fs, dj.dir, dcl);			/* Table start cluster */
+					dj.dir[DIR_Attr] = AM_DIR;			/* Attribute */
+					fs->wflag = 1;
+				}
+				if (res == FR_OK) {
+					res = sync_fs(fs);
+				}
+			} else {
+				remove_chain(&sobj, dcl, 0);		/* Could not register, remove the allocated cluster */
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename a File/Directory                                               */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+	const TCHAR* path_old,	/* Pointer to the object name to be renamed */
+	const TCHAR* path_new	/* Pointer to the new name */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR djo, djn;
+	BYTE buf[FF_FS_EXFAT ? SZDIRE * 2 : SZDIRE], *dir;
+	LBA_t sect;
+	DEF_NAMBUF
+
+
+	get_ldnumber(&path_new);						/* Snip the drive number of new name off */
+	res = mount_volume(&path_old, &fs, FA_WRITE);	/* Get logical drive of the old object */
+	if (res == FR_OK) {
+		djo.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&djo, path_old);			/* Check old object */
+		if (res == FR_OK && (djo.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check validity of name */
+#if FF_FS_LOCK
+		if (res == FR_OK) {
+			res = chk_share(&djo, 2);
+		}
+#endif
+		if (res == FR_OK) {					/* Object to be renamed is found */
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {	/* At exFAT volume */
+				BYTE nf, nn;
+				WORD nh;
+
+				memcpy(buf, fs->dirbuf, SZDIRE * 2);	/* Save 85+C0 entry of old object */
+				memcpy(&djn, &djo, sizeof djo);
+				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+				}
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+						nf = fs->dirbuf[XDIR_NumSec]; nn = fs->dirbuf[XDIR_NumName];
+						nh = ld_word(fs->dirbuf + XDIR_NameHash);
+						memcpy(fs->dirbuf, buf, SZDIRE * 2);	/* Restore 85+C0 entry */
+						fs->dirbuf[XDIR_NumSec] = nf; fs->dirbuf[XDIR_NumName] = nn;
+						st_word(fs->dirbuf + XDIR_NameHash, nh);
+						if (!(fs->dirbuf[XDIR_Attr] & AM_DIR)) fs->dirbuf[XDIR_Attr] |= AM_ARC;	/* Set archive attribute if it is a file */
+/* Start of critical section where an interruption can cause a cross-link */
+						res = store_xdir(&djn);
+					}
+				}
+			} else
+#endif
+			{	/* At FAT/FAT32 volume */
+				memcpy(buf, djo.dir, SZDIRE);			/* Save directory entry of the object */
+				memcpy(&djn, &djo, sizeof (DIR));		/* Duplicate the directory object */
+				res = follow_path(&djn, path_new);		/* Make sure if new object name is not in use */
+				if (res == FR_OK) {						/* Is new name already in use by any other object? */
+					res = (djn.obj.sclust == djo.obj.sclust && djn.dptr == djo.dptr) ? FR_NO_FILE : FR_EXIST;
+				}
+				if (res == FR_NO_FILE) { 				/* It is a valid path and no name collision */
+					res = dir_register(&djn);			/* Register the new entry */
+					if (res == FR_OK) {
+						dir = djn.dir;					/* Copy directory entry of the object except name */
+						memcpy(dir + 13, buf + 13, SZDIRE - 13);
+						dir[DIR_Attr] = buf[DIR_Attr];
+						if (!(dir[DIR_Attr] & AM_DIR)) dir[DIR_Attr] |= AM_ARC;	/* Set archive attribute if it is a file */
+						fs->wflag = 1;
+						if ((dir[DIR_Attr] & AM_DIR) && djo.obj.sclust != djn.obj.sclust) {	/* Update .. entry in the sub-directory if needed */
+							sect = clst2sect(fs, ld_clust(fs, dir));
+							if (sect == 0) {
+								res = FR_INT_ERR;
+							} else {
+/* Start of critical section where an interruption can cause a cross-link */
+								res = move_window(fs, sect);
+								dir = fs->win + SZDIRE * 1;	/* Ptr to .. entry */
+								if (res == FR_OK && dir[1] == '.') {
+									st_clust(fs, dir, djn.obj.sclust);
+									fs->wflag = 1;
+								}
+							}
+						}
+					}
+				}
+			}
+			if (res == FR_OK) {
+				res = dir_remove(&djo);		/* Remove old entry */
+				if (res == FR_OK) {
+					res = sync_fs(fs);
+				}
+			}
+/* End of the critical section */
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_FS_MINIMIZE == 0 */
+#endif /* FF_FS_MINIMIZE <= 1 */
+#endif /* FF_FS_MINIMIZE <= 2 */
+
+
+
+#if FF_USE_CHMOD && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Change Attribute                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+	const TCHAR* path,	/* Pointer to the file path */
+	BYTE attr,			/* Attribute bits */
+	BYTE mask			/* Attribute mask to change */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj;
+	DEF_NAMBUF
+
+
+	res = mount_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check object validity */
+		if (res == FR_OK) {
+			mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC;	/* Valid attribute mask */
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				fs->dirbuf[XDIR_Attr] = (attr & mask) | (fs->dirbuf[XDIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				res = store_xdir(&dj);
+			} else
+#endif
+			{
+				dj.dir[DIR_Attr] = (attr & mask) | (dj.dir[DIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
+				fs->wflag = 1;
+			}
+			if (res == FR_OK) {
+				res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+	const TCHAR* path,	/* Pointer to the file/directory name */
+	const FILINFO* fno	/* Pointer to the timestamp to be set */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj;
+	DEF_NAMBUF
+
+
+	res = mount_volume(&path, &fs, FA_WRITE);	/* Get logical drive */
+	if (res == FR_OK) {
+		dj.obj.fs = fs;
+		INIT_NAMBUF(fs);
+		res = follow_path(&dj, path);	/* Follow the file path */
+		if (res == FR_OK && (dj.fn[NSFLAG] & (NS_DOT | NS_NONAME))) res = FR_INVALID_NAME;	/* Check object validity */
+		if (res == FR_OK) {
+#if FF_FS_EXFAT
+			if (fs->fs_type == FS_EXFAT) {
+				st_dword(fs->dirbuf + XDIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+				res = store_xdir(&dj);
+			} else
+#endif
+			{
+				st_dword(dj.dir + DIR_ModTime, (DWORD)fno->fdate << 16 | fno->ftime);
+				fs->wflag = 1;
+			}
+			if (res == FR_OK) {
+				res = sync_fs(fs);
+			}
+		}
+		FREE_NAMBUF();
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif	/* FF_USE_CHMOD && !FF_FS_READONLY */
+
+
+
+#if FF_USE_LABEL
+/*-----------------------------------------------------------------------*/
+/* Get Volume Label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getlabel (
+	const TCHAR* path,	/* Logical drive number */
+	TCHAR* label,		/* Buffer to store the volume label */
+	DWORD* vsn			/* Variable to store the volume serial number */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj;
+	UINT si, di;
+	WCHAR wc;
+
+	/* Get logical drive */
+	res = mount_volume(&path, &fs, 0);
+
+	/* Get volume label */
+	if (res == FR_OK && label) {
+		dj.obj.fs = fs; dj.obj.sclust = 0;	/* Open root directory */
+		res = dir_sdi(&dj, 0);
+		if (res == FR_OK) {
+		 	res = DIR_READ_LABEL(&dj);		/* Find a volume label entry */
+		 	if (res == FR_OK) {
+#if FF_FS_EXFAT
+				if (fs->fs_type == FS_EXFAT) {
+					WCHAR hs;
+					UINT nw;
+
+					for (si = di = hs = 0; si < dj.dir[XDIR_NumLabel]; si++) {	/* Extract volume label from 83 entry */
+						wc = ld_word(dj.dir + XDIR_Label + si * 2);
+						if (hs == 0 && IsSurrogate(wc)) {	/* Is the code a surrogate? */
+							hs = wc; continue;
+						}
+						nw = put_utf((DWORD)hs << 16 | wc, &label[di], 4);	/* Store it in API encoding */
+						if (nw == 0) {		/* Encode error? */
+							di = 0; break;
+						}
+						di += nw;
+						hs = 0;
+					}
+					if (hs != 0) di = 0;	/* Broken surrogate pair? */
+					label[di] = 0;
+				} else
+#endif
+				{
+					si = di = 0;		/* Extract volume label from AM_VOL entry */
+					while (si < 11) {
+						wc = dj.dir[si++];
+#if FF_USE_LFN && FF_LFN_UNICODE >= 1 	/* Unicode output */
+						if (dbc_1st((BYTE)wc) && si < 11) wc = wc << 8 | dj.dir[si++];	/* Is it a DBC? */
+						wc = ff_oem2uni(wc, CODEPAGE);		/* Convert it into Unicode */
+						if (wc == 0) {		/* Invalid char in current code page? */
+							di = 0; break;
+						}
+						di += put_utf(wc, &label[di], 4);	/* Store it in Unicode */
+#else									/* ANSI/OEM output */
+						label[di++] = (TCHAR)wc;
+#endif
+					}
+					do {				/* Truncate trailing spaces */
+						label[di] = 0;
+						if (di == 0) break;
+					} while (label[--di] == ' ');
+				}
+			}
+		}
+		if (res == FR_NO_FILE) {	/* No label entry and return nul string */
+			label[0] = 0;
+			res = FR_OK;
+		}
+	}
+
+	/* Get volume serial number */
+	if (res == FR_OK && vsn) {
+		res = move_window(fs, fs->volbase);
+		if (res == FR_OK) {
+			switch (fs->fs_type) {
+			case FS_EXFAT:
+				di = BPB_VolIDEx;
+				break;
+
+			case FS_FAT32:
+				di = BS_VolID32;
+				break;
+
+			default:
+				di = BS_VolID;
+			}
+			*vsn = ld_dword(fs->win + di);
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+
+
+#if !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Set Volume Label                                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setlabel (
+	const TCHAR* label	/* Volume label to set with heading logical drive number */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DIR dj;
+	BYTE dirvn[22];
+	UINT di;
+	WCHAR wc;
+	static const char badchr[18] = "+.,;=[]" "/*:<>|\\\"\?\x7F";	/* [0..16] for FAT, [7..16] for exFAT */
+#if FF_USE_LFN
+	DWORD dc;
+#endif
+
+	/* Get logical drive */
+	res = mount_volume(&label, &fs, FA_WRITE);
+	if (res != FR_OK) LEAVE_FF(fs, res);
+
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {	/* On the exFAT volume */
+		memset(dirvn, 0, 22);
+		di = 0;
+		while ((UINT)*label >= ' ') {	/* Create volume label */
+			dc = tchar2uni(&label);	/* Get a Unicode character */
+			if (dc >= 0x10000) {
+				if (dc == 0xFFFFFFFF || di >= 10) {	/* Wrong surrogate or buffer overflow */
+					dc = 0;
+				} else {
+					st_word(dirvn + di * 2, (WCHAR)(dc >> 16)); di++;
+				}
+			}
+			if (dc == 0 || strchr(&badchr[7], (int)dc) || di >= 11) {	/* Check validity of the volume label */
+				LEAVE_FF(fs, FR_INVALID_NAME);
+			}
+			st_word(dirvn + di * 2, (WCHAR)dc); di++;
+		}
+	} else
+#endif
+	{	/* On the FAT/FAT32 volume */
+		memset(dirvn, ' ', 11);
+		di = 0;
+		while ((UINT)*label >= ' ') {	/* Create volume label */
+#if FF_USE_LFN
+			dc = tchar2uni(&label);
+			wc = (dc < 0x10000) ? ff_uni2oem(ff_wtoupper(dc), CODEPAGE) : 0;
+#else									/* ANSI/OEM input */
+			wc = (BYTE)*label++;
+			if (dbc_1st((BYTE)wc)) wc = dbc_2nd((BYTE)*label) ? wc << 8 | (BYTE)*label++ : 0;
+			if (IsLower(wc)) wc -= 0x20;		/* To upper ASCII characters */
+#if FF_CODE_PAGE == 0
+			if (ExCvt && wc >= 0x80) wc = ExCvt[wc - 0x80];	/* To upper extended characters (SBCS cfg) */
+#elif FF_CODE_PAGE < 900
+			if (wc >= 0x80) wc = ExCvt[wc - 0x80];	/* To upper extended characters (SBCS cfg) */
+#endif
+#endif
+			if (wc == 0 || strchr(&badchr[0], (int)wc) || di >= (UINT)((wc >= 0x100) ? 10 : 11)) {	/* Reject invalid characters for volume label */
+				LEAVE_FF(fs, FR_INVALID_NAME);
+			}
+			if (wc >= 0x100) dirvn[di++] = (BYTE)(wc >> 8);
+			dirvn[di++] = (BYTE)wc;
+		}
+		if (dirvn[0] == DDEM) LEAVE_FF(fs, FR_INVALID_NAME);	/* Reject illegal name (heading DDEM) */
+		while (di && dirvn[di - 1] == ' ') di--;				/* Snip trailing spaces */
+	}
+
+	/* Set volume label */
+	dj.obj.fs = fs; dj.obj.sclust = 0;	/* Open root directory */
+	res = dir_sdi(&dj, 0);
+	if (res == FR_OK) {
+		res = DIR_READ_LABEL(&dj);	/* Get volume label entry */
+		if (res == FR_OK) {
+			if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+				dj.dir[XDIR_NumLabel] = (BYTE)di;	/* Change the volume label */
+				memcpy(dj.dir + XDIR_Label, dirvn, 22);
+			} else {
+				if (di != 0) {
+					memcpy(dj.dir, dirvn, 11);	/* Change the volume label */
+				} else {
+					dj.dir[DIR_Name] = DDEM;	/* Remove the volume label */
+				}
+			}
+			fs->wflag = 1;
+			res = sync_fs(fs);
+		} else {			/* No volume label entry or an error */
+			if (res == FR_NO_FILE) {
+				res = FR_OK;
+				if (di != 0) {	/* Create a volume label entry */
+					res = dir_alloc(&dj, 1);	/* Allocate an entry */
+					if (res == FR_OK) {
+						memset(dj.dir, 0, SZDIRE);	/* Clean the entry */
+						if (FF_FS_EXFAT && fs->fs_type == FS_EXFAT) {
+							dj.dir[XDIR_Type] = ET_VLABEL;	/* Create volume label entry */
+							dj.dir[XDIR_NumLabel] = (BYTE)di;
+							memcpy(dj.dir + XDIR_Label, dirvn, 22);
+						} else {
+							dj.dir[DIR_Attr] = AM_VOL;		/* Create volume label entry */
+							memcpy(dj.dir, dirvn, 11);
+						}
+						fs->wflag = 1;
+						res = sync_fs(fs);
+					}
+				}
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_USE_LABEL */
+
+
+
+#if FF_USE_EXPAND && !FF_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Allocate a Contiguous Blocks to the File                              */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_expand (
+	FIL* fp,		/* Pointer to the file object */
+	FSIZE_t fsz,	/* File size to be expanded to */
+	BYTE opt		/* Operation mode 0:Find and prepare or 1:Find and allocate */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD n, clst, stcl, scl, ncl, tcl, lclst;
+
+
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (fsz == 0 || fp->obj.objsize != 0 || !(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED);
+#if FF_FS_EXFAT
+	if (fs->fs_type != FS_EXFAT && fsz >= 0x100000000) LEAVE_FF(fs, FR_DENIED);	/* Check if in size limit */
+#endif
+	n = (DWORD)fs->csize * SS(fs);	/* Cluster size */
+	tcl = (DWORD)(fsz / n) + ((fsz & (n - 1)) ? 1 : 0);	/* Number of clusters required */
+	stcl = fs->last_clst; lclst = 0;
+	if (stcl < 2 || stcl >= fs->n_fatent) stcl = 2;
+
+#if FF_FS_EXFAT
+	if (fs->fs_type == FS_EXFAT) {
+		scl = find_bitmap(fs, stcl, tcl);			/* Find a contiguous cluster block */
+		if (scl == 0) res = FR_DENIED;				/* No contiguous cluster block was found */
+		if (scl == 0xFFFFFFFF) res = FR_DISK_ERR;
+		if (res == FR_OK) {	/* A contiguous free area is found */
+			if (opt) {		/* Allocate it now */
+				res = change_bitmap(fs, scl, tcl, 1);	/* Mark the cluster block 'in use' */
+				lclst = scl + tcl - 1;
+			} else {		/* Set it as suggested point for next allocation */
+				lclst = scl - 1;
+			}
+		}
+	} else
+#endif
+	{
+		scl = clst = stcl; ncl = 0;
+		for (;;) {	/* Find a contiguous cluster block */
+			n = get_fat(&fp->obj, clst);
+			if (++clst >= fs->n_fatent) clst = 2;
+			if (n == 1) {
+				res = FR_INT_ERR; break;
+			}
+			if (n == 0xFFFFFFFF) {
+				res = FR_DISK_ERR; break;
+			}
+			if (n == 0) {	/* Is it a free cluster? */
+				if (++ncl == tcl) break;	/* Break if a contiguous cluster block is found */
+			} else {
+				scl = clst; ncl = 0;		/* Not a free cluster */
+			}
+			if (clst == stcl) {		/* No contiguous cluster? */
+				res = FR_DENIED; break;
+			}
+		}
+		if (res == FR_OK) {	/* A contiguous free area is found */
+			if (opt) {		/* Allocate it now */
+				for (clst = scl, n = tcl; n; clst++, n--) {	/* Create a cluster chain on the FAT */
+					res = put_fat(fs, clst, (n == 1) ? 0xFFFFFFFF : clst + 1);
+					if (res != FR_OK) break;
+					lclst = clst;
+				}
+			} else {		/* Set it as suggested point for next allocation */
+				lclst = scl - 1;
+			}
+		}
+	}
+
+	if (res == FR_OK) {
+		fs->last_clst = lclst;		/* Set suggested start cluster to start next */
+		if (opt) {	/* Is it allocated now? */
+			fp->obj.sclust = scl;		/* Update object allocation information */
+			fp->obj.objsize = fsz;
+			if (FF_FS_EXFAT) fp->obj.stat = 2;	/* Set status 'contiguous chain' */
+			fp->flag |= FA_MODIFIED;
+			if (fs->free_clst <= fs->n_fatent - 2) {	/* Update FSINFO */
+				fs->free_clst -= tcl;
+				fs->fsi_flag |= 1;
+			}
+		}
+	}
+
+	LEAVE_FF(fs, res);
+}
+
+#endif /* FF_USE_EXPAND && !FF_FS_READONLY */
+
+
+
+#if FF_USE_FORWARD
+/*-----------------------------------------------------------------------*/
+/* Forward Data to the Stream Directly                                   */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_forward (
+	FIL* fp, 						/* Pointer to the file object */
+	UINT (*func)(const BYTE*,UINT),	/* Pointer to the streaming function */
+	UINT btf,						/* Number of bytes to forward */
+	UINT* bf						/* Pointer to number of bytes forwarded */
+)
+{
+	FRESULT res;
+	FATFS *fs;
+	DWORD clst;
+	LBA_t sect;
+	FSIZE_t remain;
+	UINT rcnt, csect;
+	BYTE *dbuf;
+
+
+	*bf = 0;	/* Clear transfer byte counter */
+	res = validate(&fp->obj, &fs);		/* Check validity of the file object */
+	if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res);
+	if (!(fp->flag & FA_READ)) LEAVE_FF(fs, FR_DENIED);	/* Check access mode */
+
+	remain = fp->obj.objsize - fp->fptr;
+	if (btf > remain) btf = (UINT)remain;			/* Truncate btf by remaining bytes */
+
+	for ( ; btf > 0 && (*func)(0, 0); fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {	/* Repeat until all data transferred or stream goes busy */
+		csect = (UINT)(fp->fptr / SS(fs) & (fs->csize - 1));	/* Sector offset in the cluster */
+		if (fp->fptr % SS(fs) == 0) {				/* On the sector boundary? */
+			if (csect == 0) {						/* On the cluster boundary? */
+				clst = (fp->fptr == 0) ?			/* On the top of the file? */
+					fp->obj.sclust : get_fat(&fp->obj, fp->clust);
+				if (clst <= 1) ABORT(fs, FR_INT_ERR);
+				if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
+				fp->clust = clst;					/* Update current cluster */
+			}
+		}
+		sect = clst2sect(fs, fp->clust);			/* Get current data sector */
+		if (sect == 0) ABORT(fs, FR_INT_ERR);
+		sect += csect;
+#if FF_FS_TINY
+		if (move_window(fs, sect) != FR_OK) ABORT(fs, FR_DISK_ERR);	/* Move sector window to the file data */
+		dbuf = fs->win;
+#else
+		if (fp->sect != sect) {		/* Fill sector cache with file data */
+#if !FF_FS_READONLY
+			if (fp->flag & FA_DIRTY) {		/* Write-back dirty sector cache */
+				if (disk_write(fs->pdrv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+				fp->flag &= (BYTE)~FA_DIRTY;
+			}
+#endif
+			if (disk_read(fs->pdrv, fp->buf, sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
+		}
+		dbuf = fp->buf;
+#endif
+		fp->sect = sect;
+		rcnt = SS(fs) - (UINT)fp->fptr % SS(fs);	/* Number of bytes remains in the sector */
+		if (rcnt > btf) rcnt = btf;					/* Clip it by btr if needed */
+		rcnt = (*func)(dbuf + ((UINT)fp->fptr % SS(fs)), rcnt);	/* Forward the file data */
+		if (rcnt == 0) ABORT(fs, FR_INT_ERR);
+	}
+
+	LEAVE_FF(fs, FR_OK);
+}
+#endif /* FF_USE_FORWARD */
+
+
+
+#if !FF_FS_READONLY && FF_USE_MKFS
+/*-----------------------------------------------------------------------*/
+/* Create FAT/exFAT volume (with sub-functions)                          */
+/*-----------------------------------------------------------------------*/
+
+#define N_SEC_TRACK 63			/* Sectors per track for determination of drive CHS */
+#define	GPT_ALIGN	0x100000	/* Alignment of partitions in GPT [byte] (>=128KB) */
+#define GPT_ITEMS	128			/* Number of GPT table size (>=128, sector aligned) */
+
+
+/* Create partitions on the physical drive in format of MBR or GPT */
+
+static FRESULT create_partition (
+	BYTE drv,			/* Physical drive number */
+	const LBA_t plst[],	/* Partition list */
+	BYTE sys,			/* System ID for each partition (for only MBR) */
+	BYTE *buf			/* Working buffer for a sector */
+)
+{
+	UINT i, cy;
+	LBA_t sz_drv;
+	DWORD sz_drv32, nxt_alloc32, sz_part32;
+	BYTE *pte;
+	BYTE hd, n_hd, sc, n_sc;
+
+	/* Get physical drive size */
+	if (disk_ioctl(drv, GET_SECTOR_COUNT, &sz_drv) != RES_OK) return FR_DISK_ERR;
+
+#if FF_LBA64
+	if (sz_drv >= FF_MIN_GPT) {	/* Create partitions in GPT format */
+		WORD ss;
+		UINT sz_ptbl, pi, si, ofs;
+		DWORD bcc, rnd, align;
+		QWORD nxt_alloc, sz_part, sz_pool, top_bpt;
+		static const BYTE gpt_mbr[16] = {0x00, 0x00, 0x02, 0x00, 0xEE, 0xFE, 0xFF, 0x00, 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF};
+
+#if FF_MAX_SS != FF_MIN_SS
+		if (disk_ioctl(drv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;	/* Get sector size */
+		if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+#else
+		ss = FF_MAX_SS;
+#endif
+		rnd = (DWORD)sz_drv + GET_FATTIME();	/* Random seed */
+		align = GPT_ALIGN / ss;				/* Partition alignment for GPT [sector] */
+		sz_ptbl = GPT_ITEMS * SZ_GPTE / ss;	/* Size of partition table [sector] */
+		top_bpt = sz_drv - sz_ptbl - 1;		/* Backup partition table start sector */
+		nxt_alloc = 2 + sz_ptbl;			/* First allocatable sector */
+		sz_pool = top_bpt - nxt_alloc;		/* Size of allocatable area */
+		bcc = 0xFFFFFFFF; sz_part = 1;
+		pi = si = 0;	/* partition table index, size table index */
+		do {
+			if (pi * SZ_GPTE % ss == 0) memset(buf, 0, ss);	/* Clean the buffer if needed */
+			if (sz_part != 0) {				/* Is the size table not termintated? */
+				nxt_alloc = (nxt_alloc + align - 1) & ((QWORD)0 - align);	/* Align partition start */
+				sz_part = plst[si++];		/* Get a partition size */
+				if (sz_part <= 100) {		/* Is the size in percentage? */
+					sz_part = sz_pool * sz_part / 100;
+					sz_part = (sz_part + align - 1) & ((QWORD)0 - align);	/* Align partition end (only if in percentage) */
+				}
+				if (nxt_alloc + sz_part > top_bpt) {	/* Clip the size at end of the pool */
+					sz_part = (nxt_alloc < top_bpt) ? top_bpt - nxt_alloc : 0;
+				}
+			}
+			if (sz_part != 0) {				/* Add a partition? */
+				ofs = pi * SZ_GPTE % ss;
+				memcpy(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16);	/* Set partition GUID (Microsoft Basic Data) */
+				rnd = make_rand(rnd, buf + ofs + GPTE_UpGuid, 16);	/* Set unique partition GUID */
+				st_qword(buf + ofs + GPTE_FstLba, nxt_alloc);		/* Set partition start sector */
+				st_qword(buf + ofs + GPTE_LstLba, nxt_alloc + sz_part - 1);	/* Set partition end sector */
+				nxt_alloc += sz_part;								/* Next allocatable sector */
+			}
+			if ((pi + 1) * SZ_GPTE % ss == 0) {		/* Write the buffer if it is filled up */
+				for (i = 0; i < ss; bcc = crc32(bcc, buf[i++])) ;	/* Calculate table check sum */
+				if (disk_write(drv, buf, 2 + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR;		/* Write to primary table */
+				if (disk_write(drv, buf, top_bpt + pi * SZ_GPTE / ss, 1) != RES_OK) return FR_DISK_ERR;	/* Write to secondary table */
+			}
+		} while (++pi < GPT_ITEMS);
+
+		/* Create primary GPT header */
+		memset(buf, 0, ss);
+		memcpy(buf + GPTH_Sign, "EFI PART" "\0\0\1\0" "\x5C\0\0", 16);	/* Signature, version (1.0) and size (92) */
+		st_dword(buf + GPTH_PtBcc, ~bcc);			/* Table check sum */
+		st_qword(buf + GPTH_CurLba, 1);				/* LBA of this header */
+		st_qword(buf + GPTH_BakLba, sz_drv - 1);	/* LBA of secondary header */
+		st_qword(buf + GPTH_FstLba, 2 + sz_ptbl);	/* LBA of first allocatable sector */
+		st_qword(buf + GPTH_LstLba, top_bpt - 1);	/* LBA of last allocatable sector */
+		st_dword(buf + GPTH_PteSize, SZ_GPTE);		/* Size of a table entry */
+		st_dword(buf + GPTH_PtNum, GPT_ITEMS);		/* Number of table entries */
+		st_dword(buf + GPTH_PtOfs, 2);				/* LBA of this table */
+		rnd = make_rand(rnd, buf + GPTH_DskGuid, 16);	/* Disk GUID */
+		for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ;	/* Calculate header check sum */
+		st_dword(buf + GPTH_Bcc, ~bcc);				/* Header check sum */
+		if (disk_write(drv, buf, 1, 1) != RES_OK) return FR_DISK_ERR;
+
+		/* Create secondary GPT header */
+		st_qword(buf + GPTH_CurLba, sz_drv - 1);	/* LBA of this header */
+		st_qword(buf + GPTH_BakLba, 1);				/* LBA of primary header */
+		st_qword(buf + GPTH_PtOfs, top_bpt);		/* LBA of this table */
+		st_dword(buf + GPTH_Bcc, 0);
+		for (i = 0, bcc= 0xFFFFFFFF; i < 92; bcc = crc32(bcc, buf[i++])) ;	/* Calculate header check sum */
+		st_dword(buf + GPTH_Bcc, ~bcc);				/* Header check sum */
+		if (disk_write(drv, buf, sz_drv - 1, 1) != RES_OK) return FR_DISK_ERR;
+
+		/* Create protective MBR */
+		memset(buf, 0, ss);
+		memcpy(buf + MBR_Table, gpt_mbr, 16);		/* Create a GPT partition */
+		st_word(buf + BS_55AA, 0xAA55);
+		if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;
+
+	} else
+#endif
+	{	/* Create partitions in MBR format */
+		sz_drv32 = (DWORD)sz_drv;
+		n_sc = N_SEC_TRACK;				/* Determine drive CHS without any consideration of the drive geometry */
+		for (n_hd = 8; n_hd != 0 && sz_drv32 / n_hd / n_sc > 1024; n_hd *= 2) ;
+		if (n_hd == 0) n_hd = 255;		/* Number of heads needs to be <256 */
+
+		memset(buf, 0, FF_MAX_SS);		/* Clear MBR */
+		pte = buf + MBR_Table;	/* Partition table in the MBR */
+		for (i = 0, nxt_alloc32 = n_sc; i < 4 && nxt_alloc32 != 0 && nxt_alloc32 < sz_drv32; i++, nxt_alloc32 += sz_part32) {
+			sz_part32 = (DWORD)plst[i];	/* Get partition size */
+			if (sz_part32 <= 100) sz_part32 = (sz_part32 == 100) ? sz_drv32 : sz_drv32 / 100 * sz_part32;	/* Size in percentage? */
+			if (nxt_alloc32 + sz_part32 > sz_drv32 || nxt_alloc32 + sz_part32 < nxt_alloc32) sz_part32 = sz_drv32 - nxt_alloc32;	/* Clip at drive size */
+			if (sz_part32 == 0) break;	/* End of table or no sector to allocate? */
+
+			st_dword(pte + PTE_StLba, nxt_alloc32);	/* Start LBA */
+			st_dword(pte + PTE_SizLba, sz_part32);	/* Number of sectors */
+			pte[PTE_System] = sys;					/* System type */
+
+			cy = (UINT)(nxt_alloc32 / n_sc / n_hd);	/* Start cylinder */
+			hd = (BYTE)(nxt_alloc32 / n_sc % n_hd);	/* Start head */
+			sc = (BYTE)(nxt_alloc32 % n_sc + 1);	/* Start sector */
+			pte[PTE_StHead] = hd;
+			pte[PTE_StSec] = (BYTE)((cy >> 2 & 0xC0) | sc);
+			pte[PTE_StCyl] = (BYTE)cy;
+
+			cy = (UINT)((nxt_alloc32 + sz_part32 - 1) / n_sc / n_hd);	/* End cylinder */
+			hd = (BYTE)((nxt_alloc32 + sz_part32 - 1) / n_sc % n_hd);	/* End head */
+			sc = (BYTE)((nxt_alloc32 + sz_part32 - 1) % n_sc + 1);		/* End sector */
+			pte[PTE_EdHead] = hd;
+			pte[PTE_EdSec] = (BYTE)((cy >> 2 & 0xC0) | sc);
+			pte[PTE_EdCyl] = (BYTE)cy;
+
+			pte += SZ_PTE;		/* Next entry */
+		}
+
+		st_word(buf + BS_55AA, 0xAA55);		/* MBR signature */
+		if (disk_write(drv, buf, 0, 1) != RES_OK) return FR_DISK_ERR;	/* Write it to the MBR */
+	}
+
+	return FR_OK;
+}
+
+
+
+FRESULT f_mkfs (
+	const TCHAR* path,		/* Logical drive number */
+	const MKFS_PARM* opt,	/* Format options */
+	void* work,				/* Pointer to working buffer (null: use len bytes of heap memory) */
+	UINT len				/* Size of working buffer [byte] */
+)
+{
+	static const WORD cst[] = {1, 4, 16, 64, 256, 512, 0};	/* Cluster size boundary for FAT volume (4Ks unit) */
+	static const WORD cst32[] = {1, 2, 4, 8, 16, 32, 0};	/* Cluster size boundary for FAT32 volume (128Ks unit) */
+	static const MKFS_PARM defopt = {FM_ANY, 0, 0, 0, 0};	/* Default parameter */
+	BYTE fsopt, fsty, sys, pdrv, ipart;
+	BYTE *buf;
+	BYTE *pte;
+	WORD ss;	/* Sector size */
+	DWORD sz_buf, sz_blk, n_clst, pau, nsect, n, vsn;
+	LBA_t sz_vol, b_vol, b_fat, b_data;		/* Size of volume, Base LBA of volume, fat, data */
+	LBA_t sect, lba[2];
+	DWORD sz_rsv, sz_fat, sz_dir, sz_au;	/* Size of reserved, fat, dir, data, cluster */
+	UINT n_fat, n_root, i;					/* Index, Number of FATs and Number of roor dir entries */
+	int vol;
+	DSTATUS ds;
+	FRESULT res;
+
+
+	/* Check mounted drive and clear work area */
+	vol = get_ldnumber(&path);					/* Get target logical drive */
+	if (vol < 0) return FR_INVALID_DRIVE;
+	if (FatFs[vol]) FatFs[vol]->fs_type = 0;	/* Clear the fs object if mounted */
+	pdrv = LD2PD(vol);		/* Hosting physical drive */
+	ipart = LD2PT(vol);		/* Hosting partition (0:create as new, 1..:existing partition) */
+
+	/* Initialize the hosting physical drive */
+	ds = disk_initialize(pdrv);
+	if (ds & STA_NOINIT) return FR_NOT_READY;
+	if (ds & STA_PROTECT) return FR_WRITE_PROTECTED;
+
+	/* Get physical drive parameters (sz_drv, sz_blk and ss) */
+	if (!opt) opt = &defopt;	/* Use default parameter if it is not given */
+	sz_blk = opt->align;
+	if (sz_blk == 0) disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk);					/* Block size from the paramter or lower layer */
+ 	if (sz_blk == 0 || sz_blk > 0x8000 || (sz_blk & (sz_blk - 1))) sz_blk = 1;	/* Use default if the block size is invalid */
+#if FF_MAX_SS != FF_MIN_SS
+	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR;
+	if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR;
+#else
+	ss = FF_MAX_SS;
+#endif
+
+	/* Options for FAT sub-type and FAT parameters */
+	fsopt = opt->fmt & (FM_ANY | FM_SFD);
+	n_fat = (opt->n_fat >= 1 && opt->n_fat <= 2) ? opt->n_fat : 1;
+	n_root = (opt->n_root >= 1 && opt->n_root <= 32768 && (opt->n_root % (ss / SZDIRE)) == 0) ? opt->n_root : 512;
+	sz_au = (opt->au_size <= 0x1000000 && (opt->au_size & (opt->au_size - 1)) == 0) ? opt->au_size : 0;
+	sz_au /= ss;	/* Byte --> Sector */
+
+	/* Get working buffer */
+	sz_buf = len / ss;		/* Size of working buffer [sector] */
+	if (sz_buf == 0) return FR_NOT_ENOUGH_CORE;
+	buf = (BYTE*)work;		/* Working buffer */
+#if FF_USE_LFN == 3
+	if (!buf) buf = ff_memalloc(sz_buf * ss);	/* Use heap memory for working buffer */
+#endif
+	if (!buf) return FR_NOT_ENOUGH_CORE;
+
+	/* Determine where the volume to be located (b_vol, sz_vol) */
+	b_vol = sz_vol = 0;
+	if (FF_MULTI_PARTITION && ipart != 0) {	/* Is the volume associated with any specific partition? */
+		/* Get partition location from the existing partition table */
+		if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Load MBR */
+		if (ld_word(buf + BS_55AA) != 0xAA55) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Check if MBR is valid */
+#if FF_LBA64
+		if (buf[MBR_Table + PTE_System] == 0xEE) {	/* GPT protective MBR? */
+			DWORD n_ent, ofs;
+			QWORD pt_lba;
+
+			/* Get the partition location from GPT */
+			if (disk_read(pdrv, buf, 1, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Load GPT header sector (next to MBR) */
+			if (!test_gpt_header(buf)) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Check if GPT header is valid */
+			n_ent = ld_dword(buf + GPTH_PtNum);		/* Number of entries */
+			pt_lba = ld_qword(buf + GPTH_PtOfs);	/* Table start sector */
+			ofs = i = 0;
+			while (n_ent) {		/* Find MS Basic partition with order of ipart */
+				if (ofs == 0 && disk_read(pdrv, buf, pt_lba++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Get PT sector */
+				if (!memcmp(buf + ofs + GPTE_PtGuid, GUID_MS_Basic, 16) && ++i == ipart) {	/* MS basic data partition? */
+					b_vol = ld_qword(buf + ofs + GPTE_FstLba);
+					sz_vol = ld_qword(buf + ofs + GPTE_LstLba) - b_vol + 1;
+					break;
+				}
+				n_ent--; ofs = (ofs + SZ_GPTE) % ss;	/* Next entry */
+			}
+			if (n_ent == 0) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Partition not found */
+			fsopt |= 0x80;	/* Partitioning is in GPT */
+		} else
+#endif
+		{	/* Get the partition location from MBR partition table */
+			pte = buf + (MBR_Table + (ipart - 1) * SZ_PTE);
+			if (ipart > 4 || pte[PTE_System] == 0) LEAVE_MKFS(FR_MKFS_ABORTED);	/* No partition? */
+			b_vol = ld_dword(pte + PTE_StLba);		/* Get volume start sector */
+			sz_vol = ld_dword(pte + PTE_SizLba);	/* Get volume size */
+		}
+	} else {	/* The volume is associated with a physical drive */
+		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+		if (!(fsopt & FM_SFD)) {	/* To be partitioned? */
+			/* Create a single-partition on the drive in this function */
+#if FF_LBA64
+			if (sz_vol >= FF_MIN_GPT) {	/* Which partition type to create, MBR or GPT? */
+				fsopt |= 0x80;		/* Partitioning is in GPT */
+				b_vol = GPT_ALIGN / ss; sz_vol -= b_vol + GPT_ITEMS * SZ_GPTE / ss + 1;	/* Estimated partition offset and size */
+			} else
+#endif
+			{	/* Partitioning is in MBR */
+				if (sz_vol > N_SEC_TRACK) {
+					b_vol = N_SEC_TRACK; sz_vol -= b_vol;	/* Estimated partition offset and size */
+				}
+			}
+		}
+	}
+	if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Check if volume size is >=128s */
+
+	/* Now start to create an FAT volume at b_vol and sz_vol */
+
+	do {	/* Pre-determine the FAT type */
+		if (FF_FS_EXFAT && (fsopt & FM_EXFAT)) {	/* exFAT possible? */
+			if ((fsopt & FM_ANY) == FM_EXFAT || sz_vol >= 0x4000000 || sz_au > 128) {	/* exFAT only, vol >= 64MS or sz_au > 128S ? */
+				fsty = FS_EXFAT; break;
+			}
+		}
+#if FF_LBA64
+		if (sz_vol >= 0x100000000) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too large volume for FAT/FAT32 */
+#endif
+		if (sz_au > 128) sz_au = 128;	/* Invalid AU for FAT/FAT32? */
+		if (fsopt & FM_FAT32) {	/* FAT32 possible? */
+			if (!(fsopt & FM_FAT)) {	/* no-FAT? */
+				fsty = FS_FAT32; break;
+			}
+		}
+		if (!(fsopt & FM_FAT)) LEAVE_MKFS(FR_INVALID_PARAMETER);	/* no-FAT? */
+		fsty = FS_FAT16;
+	} while (0);
+
+	vsn = (DWORD)sz_vol + GET_FATTIME();	/* VSN generated from current time and partitiion size */
+
+#if FF_FS_EXFAT
+	if (fsty == FS_EXFAT) {	/* Create an exFAT volume */
+		DWORD szb_bit, szb_case, sum, nbit, clu, clen[3];
+		WCHAR ch, si;
+		UINT j, st;
+
+		if (sz_vol < 0x1000) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too small volume for exFAT? */
+#if FF_USE_TRIM
+		lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1;	/* Inform storage device that the volume area may be erased */
+		disk_ioctl(pdrv, CTRL_TRIM, lba);
+#endif
+		/* Determine FAT location, data location and number of clusters */
+		if (sz_au == 0) {	/* AU auto-selection */
+			sz_au = 8;
+			if (sz_vol >= 0x80000) sz_au = 64;		/* >= 512Ks */
+			if (sz_vol >= 0x4000000) sz_au = 256;	/* >= 64Ms */
+		}
+		b_fat = b_vol + 32;										/* FAT start at offset 32 */
+		sz_fat = (DWORD)((sz_vol / sz_au + 2) * 4 + ss - 1) / ss;	/* Number of FAT sectors */
+		b_data = (b_fat + sz_fat + sz_blk - 1) & ~((LBA_t)sz_blk - 1);	/* Align data area to the erase block boundary */
+		if (b_data - b_vol >= sz_vol / 2) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too small volume? */
+		n_clst = (DWORD)((sz_vol - (b_data - b_vol)) / sz_au);	/* Number of clusters */
+		if (n_clst <16) LEAVE_MKFS(FR_MKFS_ABORTED);			/* Too few clusters? */
+		if (n_clst > MAX_EXFAT) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too many clusters? */
+
+		szb_bit = (n_clst + 7) / 8;								/* Size of allocation bitmap */
+		clen[0] = (szb_bit + sz_au * ss - 1) / (sz_au * ss);	/* Number of allocation bitmap clusters */
+
+		/* Create a compressed up-case table */
+		sect = b_data + sz_au * clen[0];	/* Table start sector */
+		sum = 0;							/* Table checksum to be stored in the 82 entry */
+		st = 0; si = 0; i = 0; j = 0; szb_case = 0;
+		do {
+			switch (st) {
+			case 0:
+				ch = (WCHAR)ff_wtoupper(si);	/* Get an up-case char */
+				if (ch != si) {
+					si++; break;		/* Store the up-case char if exist */
+				}
+				for (j = 1; (WCHAR)(si + j) && (WCHAR)(si + j) == ff_wtoupper((WCHAR)(si + j)); j++) ;	/* Get run length of no-case block */
+				if (j >= 128) {
+					ch = 0xFFFF; st = 2; break;	/* Compress the no-case block if run is >= 128 chars */
+				}
+				st = 1;			/* Do not compress short run */
+				/* FALLTHROUGH */
+			case 1:
+				ch = si++;		/* Fill the short run */
+				if (--j == 0) st = 0;
+				break;
+
+			default:
+				ch = (WCHAR)j; si += (WCHAR)j;	/* Number of chars to skip */
+				st = 0;
+			}
+			sum = xsum32(buf[i + 0] = (BYTE)ch, sum);	/* Put it into the write buffer */
+			sum = xsum32(buf[i + 1] = (BYTE)(ch >> 8), sum);
+			i += 2; szb_case += 2;
+			if (si == 0 || i == sz_buf * ss) {		/* Write buffered data when buffer full or end of process */
+				n = (i + ss - 1) / ss;
+				if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+				sect += n; i = 0;
+			}
+		} while (si);
+		clen[1] = (szb_case + sz_au * ss - 1) / (sz_au * ss);	/* Number of up-case table clusters */
+		clen[2] = 1;	/* Number of root dir clusters */
+
+		/* Initialize the allocation bitmap */
+		sect = b_data; nsect = (szb_bit + ss - 1) / ss;	/* Start of bitmap and number of bitmap sectors */
+		nbit = clen[0] + clen[1] + clen[2];				/* Number of clusters in-use by system (bitmap, up-case and root-dir) */
+		do {
+			memset(buf, 0, sz_buf * ss);				/* Initialize bitmap buffer */
+			for (i = 0; nbit != 0 && i / 8 < sz_buf * ss; buf[i / 8] |= 1 << (i % 8), i++, nbit--) ;	/* Mark used clusters */
+			n = (nsect > sz_buf) ? sz_buf : nsect;		/* Write the buffered data */
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Initialize the FAT */
+		sect = b_fat; nsect = sz_fat;	/* Start of FAT and number of FAT sectors */
+		j = nbit = clu = 0;
+		do {
+			memset(buf, 0, sz_buf * ss); i = 0;	/* Clear work area and reset write offset */
+			if (clu == 0) {	/* Initialize FAT [0] and FAT[1] */
+				st_dword(buf + i, 0xFFFFFFF8); i += 4; clu++;
+				st_dword(buf + i, 0xFFFFFFFF); i += 4; clu++;
+			}
+			do {			/* Create chains of bitmap, up-case and root dir */
+				while (nbit != 0 && i < sz_buf * ss) {	/* Create a chain */
+					st_dword(buf + i, (nbit > 1) ? clu + 1 : 0xFFFFFFFF);
+					i += 4; clu++; nbit--;
+				}
+				if (nbit == 0 && j < 3) nbit = clen[j++];	/* Get next chain length */
+			} while (nbit != 0 && i < sz_buf * ss);
+			n = (nsect > sz_buf) ? sz_buf : nsect;	/* Write the buffered data */
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Initialize the root directory */
+		memset(buf, 0, sz_buf * ss);
+		buf[SZDIRE * 0 + 0] = ET_VLABEL;				/* Volume label entry (no label) */
+		buf[SZDIRE * 1 + 0] = ET_BITMAP;				/* Bitmap entry */
+		st_dword(buf + SZDIRE * 1 + 20, 2);				/*  cluster */
+		st_dword(buf + SZDIRE * 1 + 24, szb_bit);		/*  size */
+		buf[SZDIRE * 2 + 0] = ET_UPCASE;				/* Up-case table entry */
+		st_dword(buf + SZDIRE * 2 + 4, sum);			/*  sum */
+		st_dword(buf + SZDIRE * 2 + 20, 2 + clen[0]);	/*  cluster */
+		st_dword(buf + SZDIRE * 2 + 24, szb_case);		/*  size */
+		sect = b_data + sz_au * (clen[0] + clen[1]); nsect = sz_au;	/* Start of the root directory and number of sectors */
+		do {	/* Fill root directory sectors */
+			n = (nsect > sz_buf) ? sz_buf : nsect;
+			if (disk_write(pdrv, buf, sect, n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			memset(buf, 0, ss);	/* Rest of entries are filled with zero */
+			sect += n; nsect -= n;
+		} while (nsect);
+
+		/* Create two set of the exFAT VBR blocks */
+		sect = b_vol;
+		for (n = 0; n < 2; n++) {
+			/* Main record (+0) */
+			memset(buf, 0, ss);
+			memcpy(buf + BS_JmpBoot, "\xEB\x76\x90" "EXFAT   ", 11);	/* Boot jump code (x86), OEM name */
+			st_qword(buf + BPB_VolOfsEx, b_vol);					/* Volume offset in the physical drive [sector] */
+			st_qword(buf + BPB_TotSecEx, sz_vol);					/* Volume size [sector] */
+			st_dword(buf + BPB_FatOfsEx, (DWORD)(b_fat - b_vol));	/* FAT offset [sector] */
+			st_dword(buf + BPB_FatSzEx, sz_fat);					/* FAT size [sector] */
+			st_dword(buf + BPB_DataOfsEx, (DWORD)(b_data - b_vol));	/* Data offset [sector] */
+			st_dword(buf + BPB_NumClusEx, n_clst);					/* Number of clusters */
+			st_dword(buf + BPB_RootClusEx, 2 + clen[0] + clen[1]);	/* Root dir cluster # */
+			st_dword(buf + BPB_VolIDEx, vsn);						/* VSN */
+			st_word(buf + BPB_FSVerEx, 0x100);						/* Filesystem version (1.00) */
+			for (buf[BPB_BytsPerSecEx] = 0, i = ss; i >>= 1; buf[BPB_BytsPerSecEx]++) ;	/* Log2 of sector size [byte] */
+			for (buf[BPB_SecPerClusEx] = 0, i = sz_au; i >>= 1; buf[BPB_SecPerClusEx]++) ;	/* Log2 of cluster size [sector] */
+			buf[BPB_NumFATsEx] = 1;					/* Number of FATs */
+			buf[BPB_DrvNumEx] = 0x80;				/* Drive number (for int13) */
+			st_word(buf + BS_BootCodeEx, 0xFEEB);	/* Boot code (x86) */
+			st_word(buf + BS_55AA, 0xAA55);			/* Signature (placed here regardless of sector size) */
+			for (i = sum = 0; i < ss; i++) {		/* VBR checksum */
+				if (i != BPB_VolFlagEx && i != BPB_VolFlagEx + 1 && i != BPB_PercInUseEx) sum = xsum32(buf[i], sum);
+			}
+			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			/* Extended bootstrap record (+1..+8) */
+			memset(buf, 0, ss);
+			st_word(buf + ss - 2, 0xAA55);	/* Signature (placed at end of sector) */
+			for (j = 1; j < 9; j++) {
+				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			}
+			/* OEM/Reserved record (+9..+10) */
+			memset(buf, 0, ss);
+			for ( ; j < 11; j++) {
+				for (i = 0; i < ss; sum = xsum32(buf[i++], sum)) ;	/* VBR checksum */
+				if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			}
+			/* Sum record (+11) */
+			for (i = 0; i < ss; i += 4) st_dword(buf + i, sum);		/* Fill with checksum value */
+			if (disk_write(pdrv, buf, sect++, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+		}
+
+	} else
+#endif	/* FF_FS_EXFAT */
+	{	/* Create an FAT/FAT32 volume */
+		do {
+			pau = sz_au;
+			/* Pre-determine number of clusters and FAT sub-type */
+			if (fsty == FS_FAT32) {	/* FAT32 volume */
+				if (pau == 0) {	/* AU auto-selection */
+					n = (DWORD)sz_vol / 0x20000;	/* Volume size in unit of 128KS */
+					for (i = 0, pau = 1; cst32[i] && cst32[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+				}
+				n_clst = (DWORD)sz_vol / pau;	/* Number of clusters */
+				sz_fat = (n_clst * 4 + 8 + ss - 1) / ss;	/* FAT size [sector] */
+				sz_rsv = 32;	/* Number of reserved sectors */
+				sz_dir = 0;		/* No static directory */
+				if (n_clst <= MAX_FAT16 || n_clst > MAX_FAT32) LEAVE_MKFS(FR_MKFS_ABORTED);
+			} else {				/* FAT volume */
+				if (pau == 0) {	/* au auto-selection */
+					n = (DWORD)sz_vol / 0x1000;	/* Volume size in unit of 4KS */
+					for (i = 0, pau = 1; cst[i] && cst[i] <= n; i++, pau <<= 1) ;	/* Get from table */
+				}
+				n_clst = (DWORD)sz_vol / pau;
+				if (n_clst > MAX_FAT12) {
+					n = n_clst * 2 + 4;		/* FAT size [byte] */
+				} else {
+					fsty = FS_FAT12;
+					n = (n_clst * 3 + 1) / 2 + 3;	/* FAT size [byte] */
+				}
+				sz_fat = (n + ss - 1) / ss;		/* FAT size [sector] */
+				sz_rsv = 1;						/* Number of reserved sectors */
+				sz_dir = (DWORD)n_root * SZDIRE / ss;	/* Root dir size [sector] */
+			}
+			b_fat = b_vol + sz_rsv;						/* FAT base */
+			b_data = b_fat + sz_fat * n_fat + sz_dir;	/* Data base */
+
+			/* Align data area to erase block boundary (for flash memory media) */
+			n = (DWORD)(((b_data + sz_blk - 1) & ~(sz_blk - 1)) - b_data);	/* Sectors to next nearest from current data base */
+			if (fsty == FS_FAT32) {		/* FAT32: Move FAT */
+				sz_rsv += n; b_fat += n;
+			} else {					/* FAT: Expand FAT */
+				if (n % n_fat) {	/* Adjust fractional error if needed */
+					n--; sz_rsv++; b_fat++;
+				}
+				sz_fat += n / n_fat;
+			}
+
+			/* Determine number of clusters and final check of validity of the FAT sub-type */
+			if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too small volume? */
+			n_clst = ((DWORD)sz_vol - sz_rsv - sz_fat * n_fat - sz_dir) / pau;
+			if (fsty == FS_FAT32) {
+				if (n_clst <= MAX_FAT16) {	/* Too few clusters for FAT32? */
+					if (sz_au == 0 && (sz_au = pau / 2) != 0) continue;	/* Adjust cluster size and retry */
+					LEAVE_MKFS(FR_MKFS_ABORTED);
+				}
+			}
+			if (fsty == FS_FAT16) {
+				if (n_clst > MAX_FAT16) {	/* Too many clusters for FAT16 */
+					if (sz_au == 0 && (pau * 2) <= 64) {
+						sz_au = pau * 2; continue;	/* Adjust cluster size and retry */
+					}
+					if ((fsopt & FM_FAT32)) {
+						fsty = FS_FAT32; continue;	/* Switch type to FAT32 and retry */
+					}
+					if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+					LEAVE_MKFS(FR_MKFS_ABORTED);
+				}
+				if  (n_clst <= MAX_FAT12) {	/* Too few clusters for FAT16 */
+					if (sz_au == 0 && (sz_au = pau * 2) <= 128) continue;	/* Adjust cluster size and retry */
+					LEAVE_MKFS(FR_MKFS_ABORTED);
+				}
+			}
+			if (fsty == FS_FAT12 && n_clst > MAX_FAT12) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too many clusters for FAT12 */
+
+			/* Ok, it is the valid cluster configuration */
+			break;
+		} while (1);
+
+#if FF_USE_TRIM
+		lba[0] = b_vol; lba[1] = b_vol + sz_vol - 1;	/* Inform storage device that the volume area may be erased */
+		disk_ioctl(pdrv, CTRL_TRIM, lba);
+#endif
+		/* Create FAT VBR */
+		memset(buf, 0, ss);
+		memcpy(buf + BS_JmpBoot, "\xEB\xFE\x90" "MSDOS5.0", 11);	/* Boot jump code (x86), OEM name */
+		st_word(buf + BPB_BytsPerSec, ss);				/* Sector size [byte] */
+		buf[BPB_SecPerClus] = (BYTE)pau;				/* Cluster size [sector] */
+		st_word(buf + BPB_RsvdSecCnt, (WORD)sz_rsv);	/* Size of reserved area */
+		buf[BPB_NumFATs] = (BYTE)n_fat;					/* Number of FATs */
+		st_word(buf + BPB_RootEntCnt, (WORD)((fsty == FS_FAT32) ? 0 : n_root));	/* Number of root directory entries */
+		if (sz_vol < 0x10000) {
+			st_word(buf + BPB_TotSec16, (WORD)sz_vol);	/* Volume size in 16-bit LBA */
+		} else {
+			st_dword(buf + BPB_TotSec32, (DWORD)sz_vol);	/* Volume size in 32-bit LBA */
+		}
+		buf[BPB_Media] = 0xF8;							/* Media descriptor byte */
+		st_word(buf + BPB_SecPerTrk, 63);				/* Number of sectors per track (for int13) */
+		st_word(buf + BPB_NumHeads, 255);				/* Number of heads (for int13) */
+		st_dword(buf + BPB_HiddSec, (DWORD)b_vol);		/* Volume offset in the physical drive [sector] */
+		if (fsty == FS_FAT32) {
+			st_dword(buf + BS_VolID32, vsn);			/* VSN */
+			st_dword(buf + BPB_FATSz32, sz_fat);		/* FAT size [sector] */
+			st_dword(buf + BPB_RootClus32, 2);			/* Root directory cluster # (2) */
+			st_word(buf + BPB_FSInfo32, 1);				/* Offset of FSINFO sector (VBR + 1) */
+			st_word(buf + BPB_BkBootSec32, 6);			/* Offset of backup VBR (VBR + 6) */
+			buf[BS_DrvNum32] = 0x80;					/* Drive number (for int13) */
+			buf[BS_BootSig32] = 0x29;					/* Extended boot signature */
+			memcpy(buf + BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
+		} else {
+			st_dword(buf + BS_VolID, vsn);				/* VSN */
+			st_word(buf + BPB_FATSz16, (WORD)sz_fat);	/* FAT size [sector] */
+			buf[BS_DrvNum] = 0x80;						/* Drive number (for int13) */
+			buf[BS_BootSig] = 0x29;						/* Extended boot signature */
+			memcpy(buf + BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
+		}
+		st_word(buf + BS_55AA, 0xAA55);					/* Signature (offset is fixed here regardless of sector size) */
+		if (disk_write(pdrv, buf, b_vol, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Write it to the VBR sector */
+
+		/* Create FSINFO record if needed */
+		if (fsty == FS_FAT32) {
+			disk_write(pdrv, buf, b_vol + 6, 1);		/* Write backup VBR (VBR + 6) */
+			memset(buf, 0, ss);
+			st_dword(buf + FSI_LeadSig, 0x41615252);
+			st_dword(buf + FSI_StrucSig, 0x61417272);
+			st_dword(buf + FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
+			st_dword(buf + FSI_Nxt_Free, 2);			/* Last allocated cluster# */
+			st_word(buf + BS_55AA, 0xAA55);
+			disk_write(pdrv, buf, b_vol + 7, 1);		/* Write backup FSINFO (VBR + 7) */
+			disk_write(pdrv, buf, b_vol + 1, 1);		/* Write original FSINFO (VBR + 1) */
+		}
+
+		/* Initialize FAT area */
+		memset(buf, 0, sz_buf * ss);
+		sect = b_fat;		/* FAT start sector */
+		for (i = 0; i < n_fat; i++) {			/* Initialize FATs each */
+			if (fsty == FS_FAT32) {
+				st_dword(buf + 0, 0xFFFFFFF8);	/* FAT[0] */
+				st_dword(buf + 4, 0xFFFFFFFF);	/* FAT[1] */
+				st_dword(buf + 8, 0x0FFFFFFF);	/* FAT[2] (root directory) */
+			} else {
+				st_dword(buf + 0, (fsty == FS_FAT12) ? 0xFFFFF8 : 0xFFFFFFF8);	/* FAT[0] and FAT[1] */
+			}
+			nsect = sz_fat;		/* Number of FAT sectors */
+			do {	/* Fill FAT sectors */
+				n = (nsect > sz_buf) ? sz_buf : nsect;
+				if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+				memset(buf, 0, ss);	/* Rest of FAT all are cleared */
+				sect += n; nsect -= n;
+			} while (nsect);
+		}
+
+		/* Initialize root directory (fill with zero) */
+		nsect = (fsty == FS_FAT32) ? pau : sz_dir;	/* Number of root directory sectors */
+		do {
+			n = (nsect > sz_buf) ? sz_buf : nsect;
+			if (disk_write(pdrv, buf, sect, (UINT)n) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+			sect += n; nsect -= n;
+		} while (nsect);
+	}
+
+	/* A FAT volume has been created here */
+
+	/* Determine system ID in the MBR partition table */
+	if (FF_FS_EXFAT && fsty == FS_EXFAT) {
+		sys = 0x07;		/* exFAT */
+	} else if (fsty == FS_FAT32) {
+		sys = 0x0C;		/* FAT32X */
+	} else if (sz_vol >= 0x10000) {
+		sys = 0x06;		/* FAT12/16 (large) */
+	} else if (fsty == FS_FAT16) {
+		sys = 0x04;		/* FAT16 */
+	} else {
+		sys = 0x01;		/* FAT12 */
+	}
+
+	/* Update partition information */
+	if (FF_MULTI_PARTITION && ipart != 0) {	/* Volume is in the existing partition */
+		if (!FF_LBA64 || !(fsopt & 0x80)) {	/* Is the partition in MBR? */
+			/* Update system ID in the partition table */
+			if (disk_read(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Read the MBR */
+			buf[MBR_Table + (ipart - 1) * SZ_PTE + PTE_System] = sys;			/* Set system ID */
+			if (disk_write(pdrv, buf, 0, 1) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);	/* Write it back to the MBR */
+		}
+	} else {								/* Volume as a new single partition */
+		if (!(fsopt & FM_SFD)) {			/* Create partition table if not in SFD format */
+			lba[0] = sz_vol; lba[1] = 0;
+			res = create_partition(pdrv, lba, sys, buf);
+			if (res != FR_OK) LEAVE_MKFS(res);
+		}
+	}
+
+	if (disk_ioctl(pdrv, CTRL_SYNC, 0) != RES_OK) LEAVE_MKFS(FR_DISK_ERR);
+
+	LEAVE_MKFS(FR_OK);
+}
+
+
+
+
+#if FF_MULTI_PARTITION
+/*-----------------------------------------------------------------------*/
+/* Create Partition Table on the Physical Drive                          */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+	BYTE pdrv,			/* Physical drive number */
+	const LBA_t ptbl[],	/* Pointer to the size table for each partitions */
+	void* work			/* Pointer to the working buffer (null: use heap memory) */
+)
+{
+	BYTE *buf = (BYTE*)work;
+	DSTATUS stat;
+	FRESULT res;
+
+
+	/* Initialize the physical drive */
+	stat = disk_initialize(pdrv);
+	if (stat & STA_NOINIT) return FR_NOT_READY;
+	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+
+#if FF_USE_LFN == 3
+	if (!buf) buf = ff_memalloc(FF_MAX_SS);	/* Use heap memory for working buffer */
+#endif
+	if (!buf) return FR_NOT_ENOUGH_CORE;
+
+	res = create_partition(pdrv, ptbl, 0x07, buf);	/* Create partitions (system ID is temporary setting and determined by f_mkfs) */
+
+	LEAVE_MKFS(res);
+}
+
+#endif /* FF_MULTI_PARTITION */
+#endif /* !FF_FS_READONLY && FF_USE_MKFS */
+
+
+
+
+#if FF_USE_STRFUNC
+#if FF_USE_LFN && FF_LFN_UNICODE && (FF_STRF_ENCODE < 0 || FF_STRF_ENCODE > 3)
+#error Wrong FF_STRF_ENCODE setting
+#endif
+/*-----------------------------------------------------------------------*/
+/* Get a String from the File                                            */
+/*-----------------------------------------------------------------------*/
+
+TCHAR* f_gets (
+	TCHAR* buff,	/* Pointer to the buffer to store read string */
+	int len,		/* Size of string buffer (items) */
+	FIL* fp			/* Pointer to the file object */
+)
+{
+	int nc = 0;
+	TCHAR *p = buff;
+	BYTE s[4];
+	UINT rc;
+	DWORD dc;
+#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE <= 2
+	WCHAR wc;
+#endif
+#if FF_USE_LFN && FF_LFN_UNICODE && FF_STRF_ENCODE == 3
+	UINT ct;
+#endif
+
+#if FF_USE_LFN && FF_LFN_UNICODE			/* With code conversion (Unicode API) */
+	/* Make a room for the character and terminator  */
+	if (FF_LFN_UNICODE == 1) len -= (FF_STRF_ENCODE == 0) ? 1 : 2;
+	if (FF_LFN_UNICODE == 2) len -= (FF_STRF_ENCODE == 0) ? 3 : 4;
+	if (FF_LFN_UNICODE == 3) len -= 1;
+	while (nc < len) {
+#if FF_STRF_ENCODE == 0				/* Read a character in ANSI/OEM */
+		f_read(fp, s, 1, &rc);		/* Get a code unit */
+		if (rc != 1) break;			/* EOF? */
+		wc = s[0];
+		if (dbc_1st((BYTE)wc)) {	/* DBC 1st byte? */
+			f_read(fp, s, 1, &rc);	/* Get 2nd byte */
+			if (rc != 1 || !dbc_2nd(s[0])) continue;	/* Wrong code? */
+			wc = wc << 8 | s[0];
+		}
+		dc = ff_oem2uni(wc, CODEPAGE);	/* Convert ANSI/OEM into Unicode */
+		if (dc == 0) continue;		/* Conversion error? */
+#elif FF_STRF_ENCODE == 1 || FF_STRF_ENCODE == 2 	/* Read a character in UTF-16LE/BE */
+		f_read(fp, s, 2, &rc);		/* Get a code unit */
+		if (rc != 2) break;			/* EOF? */
+		dc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1];
+		if (IsSurrogateL(dc)) continue;	/* Broken surrogate pair? */
+		if (IsSurrogateH(dc)) {		/* High surrogate? */
+			f_read(fp, s, 2, &rc);	/* Get low surrogate */
+			if (rc != 2) break;		/* EOF? */
+			wc = (FF_STRF_ENCODE == 1) ? ld_word(s) : s[0] << 8 | s[1];
+			if (!IsSurrogateL(wc)) continue;	/* Broken surrogate pair? */
+			dc = ((dc & 0x3FF) + 0x40) << 10 | (wc & 0x3FF);	/* Merge surrogate pair */
+		}
+#else	/* Read a character in UTF-8 */
+		f_read(fp, s, 1, &rc);		/* Get a code unit */
+		if (rc != 1) break;			/* EOF? */
+		dc = s[0];
+		if (dc >= 0x80) {			/* Multi-byte sequence? */
+			ct = 0;
+			if ((dc & 0xE0) == 0xC0) {	/* 2-byte sequence? */
+				dc &= 0x1F; ct = 1;
+			}
+			if ((dc & 0xF0) == 0xE0) {	/* 3-byte sequence? */
+				dc &= 0x0F; ct = 2;
+			}
+			if ((dc & 0xF8) == 0xF0) {	/* 4-byte sequence? */
+				dc &= 0x07; ct = 3;
+			}
+			if (ct == 0) continue;
+			f_read(fp, s, ct, &rc);	/* Get trailing bytes */
+			if (rc != ct) break;
+			rc = 0;
+			do {	/* Merge the byte sequence */
+				if ((s[rc] & 0xC0) != 0x80) break;
+				dc = dc << 6 | (s[rc] & 0x3F);
+			} while (++rc < ct);
+			if (rc != ct || dc < 0x80 || IsSurrogate(dc) || dc >= 0x110000) continue;	/* Wrong encoding? */
+		}
+#endif
+		/* A code point is avaialble in dc to be output */
+
+		if (FF_USE_STRFUNC == 2 && dc == '\r') continue;	/* Strip \r off if needed */
+#if FF_LFN_UNICODE == 1	|| FF_LFN_UNICODE == 3	/* Output it in UTF-16/32 encoding */
+		if (FF_LFN_UNICODE == 1 && dc >= 0x10000) {	/* Out of BMP at UTF-16? */
+			*p++ = (TCHAR)(0xD800 | ((dc >> 10) - 0x40)); nc++;	/* Make and output high surrogate */
+			dc = 0xDC00 | (dc & 0x3FF);		/* Make low surrogate */
+		}
+		*p++ = (TCHAR)dc; nc++;
+		if (dc == '\n') break;	/* End of line? */
+#elif FF_LFN_UNICODE == 2		/* Output it in UTF-8 encoding */
+		if (dc < 0x80) {	/* Single byte? */
+			*p++ = (TCHAR)dc;
+			nc++;
+			if (dc == '\n') break;	/* End of line? */
+		} else if (dc < 0x800) {	/* 2-byte sequence? */
+			*p++ = (TCHAR)(0xC0 | (dc >> 6 & 0x1F));
+			*p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
+			nc += 2;
+		} else if (dc < 0x10000) {	/* 3-byte sequence? */
+			*p++ = (TCHAR)(0xE0 | (dc >> 12 & 0x0F));
+			*p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F));
+			*p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
+			nc += 3;
+		} else {					/* 4-byte sequence */
+			*p++ = (TCHAR)(0xF0 | (dc >> 18 & 0x07));
+			*p++ = (TCHAR)(0x80 | (dc >> 12 & 0x3F));
+			*p++ = (TCHAR)(0x80 | (dc >> 6 & 0x3F));
+			*p++ = (TCHAR)(0x80 | (dc >> 0 & 0x3F));
+			nc += 4;
+		}
+#endif
+	}
+
+#else			/* Byte-by-byte read without any conversion (ANSI/OEM API) */
+	len -= 1;	/* Make a room for the terminator */
+	while (nc < len) {
+		f_read(fp, s, 1, &rc);	/* Get a byte */
+		if (rc != 1) break;		/* EOF? */
+		dc = s[0];
+		if (FF_USE_STRFUNC == 2 && dc == '\r') continue;
+		*p++ = (TCHAR)dc; nc++;
+		if (dc == '\n') break;
+	}
+#endif
+
+	*p = 0;		/* Terminate the string */
+	return nc ? buff : 0;	/* When no data read due to EOF or error, return with error. */
+}
+
+
+
+
+#if !FF_FS_READONLY
+#include <stdarg.h>
+#define SZ_PUTC_BUF	64
+#define SZ_NUM_BUF	32
+
+/*-----------------------------------------------------------------------*/
+/* Put a Character to the File (with sub-functions)                      */
+/*-----------------------------------------------------------------------*/
+
+/* Output buffer and work area */
+
+typedef struct {
+	FIL *fp;		/* Ptr to the writing file */
+	int idx, nchr;	/* Write index of buf[] (-1:error), number of encoding units written */
+#if FF_USE_LFN && FF_LFN_UNICODE == 1
+	WCHAR hs;
+#elif FF_USE_LFN && FF_LFN_UNICODE == 2
+	BYTE bs[4];
+	UINT wi, ct;
+#endif
+	BYTE buf[SZ_PUTC_BUF];	/* Write buffer */
+} putbuff;
+
+
+/* Buffered file write with code conversion */
+
+static void putc_bfd (putbuff* pb, TCHAR c)
+{
+	UINT n;
+	int i, nc;
+#if FF_USE_LFN && FF_LFN_UNICODE
+	WCHAR hs, wc;
+#if FF_LFN_UNICODE == 2
+	DWORD dc;
+	const TCHAR* tp;
+#endif
+#endif
+
+	if (FF_USE_STRFUNC == 2 && c == '\n') {	 /* LF -> CRLF conversion */
+		putc_bfd(pb, '\r');
+	}
+
+	i = pb->idx;			/* Write index of pb->buf[] */
+	if (i < 0) return;		/* In write error? */
+	nc = pb->nchr;			/* Write unit counter */
+
+#if FF_USE_LFN && FF_LFN_UNICODE
+#if FF_LFN_UNICODE == 1		/* UTF-16 input */
+	if (IsSurrogateH(c)) {	/* Is this a high-surrogate? */
+		pb->hs = c; return;	/* Save it for next */
+	}
+	hs = pb->hs; pb->hs = 0;
+	if (hs != 0) {			/* Is there a leading high-surrogate? */
+		if (!IsSurrogateL(c)) hs = 0;	/* Discard high-surrogate if not a surrogate pair */
+	} else {
+		if (IsSurrogateL(c)) return;	/* Discard stray low-surrogate */
+	}
+	wc = c;
+#elif FF_LFN_UNICODE == 2	/* UTF-8 input */
+	for (;;) {
+		if (pb->ct == 0) {	/* Out of multi-byte sequence? */
+			pb->bs[pb->wi = 0] = (BYTE)c;	/* Save 1st byte */
+			if ((BYTE)c < 0x80) break;					/* Single byte code? */
+			if (((BYTE)c & 0xE0) == 0xC0) pb->ct = 1;	/* 2-byte sequence? */
+			if (((BYTE)c & 0xF0) == 0xE0) pb->ct = 2;	/* 3-byte sequence? */
+			if (((BYTE)c & 0xF8) == 0xF0) pb->ct = 3;	/* 4-byte sequence? */
+			return;										/* Wrong leading byte (discard it) */
+		} else {				/* In the multi-byte sequence */
+			if (((BYTE)c & 0xC0) != 0x80) {	/* Broken sequence? */
+				pb->ct = 0; continue;		/* Discard the sequense */
+			}
+			pb->bs[++pb->wi] = (BYTE)c;	/* Save the trailing byte */
+			if (--pb->ct == 0) break;	/* End of the sequence? */
+			return;
+		}
+	}
+	tp = (const TCHAR*)pb->bs;
+	dc = tchar2uni(&tp);			/* UTF-8 ==> UTF-16 */
+	if (dc == 0xFFFFFFFF) return;	/* Wrong code? */
+	hs = (WCHAR)(dc >> 16);
+	wc = (WCHAR)dc;
+#elif FF_LFN_UNICODE == 3	/* UTF-32 input */
+	if (IsSurrogate(c) || c >= 0x110000) return;	/* Discard invalid code */
+	if (c >= 0x10000) {		/* Out of BMP? */
+		hs = (WCHAR)(0xD800 | ((c >> 10) - 0x40)); 	/* Make high surrogate */
+		wc = 0xDC00 | (c & 0x3FF);					/* Make low surrogate */
+	} else {
+		hs = 0;
+		wc = (WCHAR)c;
+	}
+#endif
+	/* A code point in UTF-16 is available in hs and wc */
+
+#if FF_STRF_ENCODE == 1		/* Write a code point in UTF-16LE */
+	if (hs != 0) {	/* Surrogate pair? */
+		st_word(&pb->buf[i], hs);
+		i += 2;
+		nc++;
+	}
+	st_word(&pb->buf[i], wc);
+	i += 2;
+#elif FF_STRF_ENCODE == 2	/* Write a code point in UTF-16BE */
+	if (hs != 0) {	/* Surrogate pair? */
+		pb->buf[i++] = (BYTE)(hs >> 8);
+		pb->buf[i++] = (BYTE)hs;
+		nc++;
+	}
+	pb->buf[i++] = (BYTE)(wc >> 8);
+	pb->buf[i++] = (BYTE)wc;
+#elif FF_STRF_ENCODE == 3	/* Write a code point in UTF-8 */
+	if (hs != 0) {	/* 4-byte sequence? */
+		nc += 3;
+		hs = (hs & 0x3FF) + 0x40;
+		pb->buf[i++] = (BYTE)(0xF0 | hs >> 8);
+		pb->buf[i++] = (BYTE)(0x80 | (hs >> 2 & 0x3F));
+		pb->buf[i++] = (BYTE)(0x80 | (hs & 3) << 4 | (wc >> 6 & 0x0F));
+		pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F));
+	} else {
+		if (wc < 0x80) {	/* Single byte? */
+			pb->buf[i++] = (BYTE)wc;
+		} else {
+			if (wc < 0x800) {	/* 2-byte sequence? */
+				nc += 1;
+				pb->buf[i++] = (BYTE)(0xC0 | wc >> 6);
+			} else {			/* 3-byte sequence */
+				nc += 2;
+				pb->buf[i++] = (BYTE)(0xE0 | wc >> 12);
+				pb->buf[i++] = (BYTE)(0x80 | (wc >> 6 & 0x3F));
+			}
+			pb->buf[i++] = (BYTE)(0x80 | (wc & 0x3F));
+		}
+	}
+#else						/* Write a code point in ANSI/OEM */
+	if (hs != 0) return;
+	wc = ff_uni2oem(wc, CODEPAGE);	/* UTF-16 ==> ANSI/OEM */
+	if (wc == 0) return;
+	if (wc >= 0x100) {
+		pb->buf[i++] = (BYTE)(wc >> 8); nc++;
+	}
+	pb->buf[i++] = (BYTE)wc;
+#endif
+
+#else							/* ANSI/OEM input (without re-encoding) */
+	pb->buf[i++] = (BYTE)c;
+#endif
+
+	if (i >= (int)(sizeof pb->buf) - 4) {	/* Write buffered characters to the file */
+		f_write(pb->fp, pb->buf, (UINT)i, &n);
+		i = (n == (UINT)i) ? 0 : -1;
+	}
+	pb->idx = i;
+	pb->nchr = nc + 1;
+}
+
+
+/* Flush remaining characters in the buffer */
+
+static int putc_flush (putbuff* pb)
+{
+	UINT nw;
+
+	if (   pb->idx >= 0	/* Flush buffered characters to the file */
+		&& f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
+		&& (UINT)pb->idx == nw) return pb->nchr;
+	return -1;
+}
+
+
+/* Initialize write buffer */
+
+static void putc_init (putbuff* pb, FIL* fp)
+{
+	memset(pb, 0, sizeof (putbuff));
+	pb->fp = fp;
+}
+
+
+
+int f_putc (
+	TCHAR c,	/* A character to be output */
+	FIL* fp		/* Pointer to the file object */
+)
+{
+	putbuff pb;
+
+
+	putc_init(&pb, fp);
+	putc_bfd(&pb, c);	/* Put the character */
+	return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a String to the File                                              */
+/*-----------------------------------------------------------------------*/
+
+int f_puts (
+	const TCHAR* str,	/* Pointer to the string to be output */
+	FIL* fp				/* Pointer to the file object */
+)
+{
+	putbuff pb;
+
+
+	putc_init(&pb, fp);
+	while (*str) putc_bfd(&pb, *str++);		/* Put the string */
+	return putc_flush(&pb);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a Formatted String to the File (with sub-functions)               */
+/*-----------------------------------------------------------------------*/
+#if FF_PRINT_FLOAT && FF_INTDEF == 2
+#include <math.h>
+
+static int ilog10 (double n)	/* Calculate log10(n) in integer output */
+{
+	int rv = 0;
+
+	while (n >= 10) {	/* Decimate digit in right shift */
+		if (n >= 100000) {
+			n /= 100000; rv += 5;
+		} else {
+			n /= 10; rv++;
+		}
+	}
+	while (n < 1) {		/* Decimate digit in left shift */
+		if (n < 0.00001) {
+			n *= 100000; rv -= 5;
+		} else {
+			n *= 10; rv--;
+		}
+	}
+	return rv;
+}
+
+
+static double i10x (int n)	/* Calculate 10^n in integer input */
+{
+	double rv = 1;
+
+	while (n > 0) {		/* Left shift */
+		if (n >= 5) {
+			rv *= 100000; n -= 5;
+		} else {
+			rv *= 10; n--;
+		}
+	}
+	while (n < 0) {		/* Right shift */
+		if (n <= -5) {
+			rv /= 100000; n += 5;
+		} else {
+			rv /= 10; n++;
+		}
+	}
+	return rv;
+}
+
+
+static void ftoa (
+	char* buf,	/* Buffer to output the floating point string */
+	double val,	/* Value to output */
+	int prec,	/* Number of fractional digits */
+	TCHAR fmt	/* Notation */
+)
+{
+	int d;
+	int e = 0, m = 0;
+	char sign = 0;
+	double w;
+	const char *er = 0;
+	const char ds = FF_PRINT_FLOAT == 2 ? ',' : '.';
+
+
+	if (isnan(val)) {			/* Not a number? */
+		er = "NaN";
+	} else {
+		if (prec < 0) prec = 6;	/* Default precision? (6 fractional digits) */
+		if (val < 0) {			/* Negative? */
+			val = 0 - val; sign = '-';
+		} else {
+			sign = '+';
+		}
+		if (isinf(val)) {		/* Infinite? */
+			er = "INF";
+		} else {
+			if (fmt == 'f') {	/* Decimal notation? */
+				val += i10x(0 - prec) / 2;	/* Round (nearest) */
+				m = ilog10(val);
+				if (m < 0) m = 0;
+				if (m + prec + 3 >= SZ_NUM_BUF) er = "OV";	/* Buffer overflow? */
+			} else {			/* E notation */
+				if (val != 0) {		/* Not a true zero? */
+					val += i10x(ilog10(val) - prec) / 2;	/* Round (nearest) */
+					e = ilog10(val);
+					if (e > 99 || prec + 7 >= SZ_NUM_BUF) {	/* Buffer overflow or E > +99? */
+						er = "OV";
+					} else {
+						if (e < -99) e = -99;
+						val /= i10x(e);	/* Normalize */
+					}
+				}
+			}
+		}
+		if (!er) {	/* Not error condition */
+			if (sign == '-') *buf++ = sign;	/* Add a - if negative value */
+			do {				/* Put decimal number */
+				if (m == -1) *buf++ = ds;	/* Insert a decimal separator when get into fractional part */
+				w = i10x(m);				/* Snip the highest digit d */
+				d = (int)(val / w); val -= d * w;
+				*buf++ = (char)('0' + d);	/* Put the digit */
+			} while (--m >= -prec);			/* Output all digits specified by prec */
+			if (fmt != 'f') {	/* Put exponent if needed */
+				*buf++ = (char)fmt;
+				if (e < 0) {
+					e = 0 - e; *buf++ = '-';
+				} else {
+					*buf++ = '+';
+				}
+				*buf++ = (char)('0' + e / 10);
+				*buf++ = (char)('0' + e % 10);
+			}
+		}
+	}
+	if (er) {	/* Error condition */
+		if (sign) *buf++ = sign;		/* Add sign if needed */
+		do {		/* Put error symbol */
+			*buf++ = *er++;
+		} while (*er);
+	}
+	*buf = 0;	/* Term */
+}
+#endif	/* FF_PRINT_FLOAT && FF_INTDEF == 2 */
+
+
+
+int f_printf (
+	FIL* fp,			/* Pointer to the file object */
+	const TCHAR* fmt,	/* Pointer to the format string */
+	...					/* Optional arguments... */
+)
+{
+	va_list arp;
+	putbuff pb;
+	UINT i, j, w, f, r;
+	int prec;
+#if FF_PRINT_LLI && FF_INTDEF == 2
+	QWORD v;
+#else
+	DWORD v;
+#endif
+	TCHAR *tp;
+	TCHAR tc, pad;
+	TCHAR nul = 0;
+	char d, str[SZ_NUM_BUF];
+
+
+	putc_init(&pb, fp);
+
+	va_start(arp, fmt);
+
+	for (;;) {
+		tc = *fmt++;
+		if (tc == 0) break;			/* End of format string */
+		if (tc != '%') {			/* Not an escape character (pass-through) */
+			putc_bfd(&pb, tc);
+			continue;
+		}
+		f = w = 0; pad = ' '; prec = -1;	/* Initialize parms */
+		tc = *fmt++;
+		if (tc == '0') {			/* Flag: '0' padded */
+			pad = '0'; tc = *fmt++;
+		} else if (tc == '-') {		/* Flag: Left aligned */
+			f = 2; tc = *fmt++;
+		}
+		if (tc == '*') {			/* Minimum width from an argument */
+			w = va_arg(arp, int);
+			tc = *fmt++;
+		} else {
+			while (IsDigit(tc)) {	/* Minimum width */
+				w = w * 10 + tc - '0';
+				tc = *fmt++;
+			}
+		}
+		if (tc == '.') {			/* Precision */
+			tc = *fmt++;
+			if (tc == '*') {		/* Precision from an argument */
+				prec = va_arg(arp, int);
+				tc = *fmt++;
+			} else {
+				prec = 0;
+				while (IsDigit(tc)) {	/* Precision */
+					prec = prec * 10 + tc - '0';
+					tc = *fmt++;
+				}
+			}
+		}
+		if (tc == 'l') {			/* Size: long int */
+			f |= 4; tc = *fmt++;
+#if FF_PRINT_LLI && FF_INTDEF == 2
+			if (tc == 'l') {		/* Size: long long int */
+				f |= 8; tc = *fmt++;
+			}
+#endif
+		}
+		if (tc == 0) break;			/* End of format string */
+		switch (tc) {				/* Atgument type is... */
+		case 'b':					/* Unsigned binary */
+			r = 2; break;
+
+		case 'o':					/* Unsigned octal */
+			r = 8; break;
+
+		case 'd':					/* Signed decimal */
+		case 'u': 					/* Unsigned decimal */
+			r = 10; break;
+
+		case 'x':					/* Unsigned hexadecimal (lower case) */
+		case 'X': 					/* Unsigned hexadecimal (upper case) */
+			r = 16; break;
+
+		case 'c':					/* Character */
+			putc_bfd(&pb, (TCHAR)va_arg(arp, int));
+			continue;
+
+		case 's':					/* String */
+			tp = va_arg(arp, TCHAR*);	/* Get a pointer argument */
+			if (!tp) tp = &nul;		/* Null ptr generates a null string */
+			for (j = 0; tp[j]; j++) ;	/* j = tcslen(tp) */
+			if (prec >= 0 && j > (UINT)prec) j = prec;	/* Limited length of string body */
+			for ( ; !(f & 2) && j < w; j++) putc_bfd(&pb, pad);	/* Left pads */
+			while (*tp && prec--) putc_bfd(&pb, *tp++);	/* Body */
+			while (j++ < w) putc_bfd(&pb, ' ');			/* Right pads */
+			continue;
+#if FF_PRINT_FLOAT && FF_INTDEF == 2
+		case 'f':					/* Floating point (decimal) */
+		case 'e':					/* Floating point (e) */
+		case 'E':					/* Floating point (E) */
+			ftoa(str, va_arg(arp, double), prec, tc);	/* Make a floating point string */
+			for (j = strlen(str); !(f & 2) && j < w; j++) putc_bfd(&pb, pad);	/* Left pads */
+			for (i = 0; str[i]; putc_bfd(&pb, str[i++])) ;	/* Body */
+			while (j++ < w) putc_bfd(&pb, ' ');	/* Right pads */
+			continue;
+#endif
+		default:					/* Unknown type (pass-through) */
+			putc_bfd(&pb, tc); continue;
+		}
+
+		/* Get an integer argument and put it in numeral */
+#if FF_PRINT_LLI && FF_INTDEF == 2
+		if (f & 8) {		/* long long argument? */
+			v = (QWORD)va_arg(arp, long long);
+		} else if (f & 4) {	/* long argument? */
+			v = (tc == 'd') ? (QWORD)(long long)va_arg(arp, long) : (QWORD)va_arg(arp, unsigned long);
+		} else {			/* int/short/char argument */
+			v = (tc == 'd') ? (QWORD)(long long)va_arg(arp, int) : (QWORD)va_arg(arp, unsigned int);
+		}
+		if (tc == 'd' && (v & 0x8000000000000000)) {	/* Negative value? */
+			v = 0 - v; f |= 1;
+		}
+#else
+		if (f & 4) {	/* long argument? */
+			v = (DWORD)va_arg(arp, long);
+		} else {		/* int/short/char argument */
+			v = (tc == 'd') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int);
+		}
+		if (tc == 'd' && (v & 0x80000000)) {	/* Negative value? */
+			v = 0 - v; f |= 1;
+		}
+#endif
+		i = 0;
+		do {	/* Make an integer number string */
+			d = (char)(v % r); v /= r;
+			if (d > 9) d += (tc == 'x') ? 0x27 : 0x07;
+			str[i++] = d + '0';
+		} while (v && i < SZ_NUM_BUF);
+		if (f & 1) str[i++] = '-';	/* Sign */
+		/* Write it */
+		for (j = i; !(f & 2) && j < w; j++) {	/* Left pads */
+			putc_bfd(&pb, pad);
+		}
+		do {				/* Body */
+			putc_bfd(&pb, (TCHAR)str[--i]);
+		} while (i);
+		while (j++ < w) {	/* Right pads */
+			putc_bfd(&pb, ' ');
+		}
+	}
+
+	va_end(arp);
+
+	return putc_flush(&pb);
+}
+
+#endif /* !FF_FS_READONLY */
+#endif /* FF_USE_STRFUNC */
+
+
+
+#if FF_CODE_PAGE == 0
+/*-----------------------------------------------------------------------*/
+/* Set Active Codepage for the Path Name                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_setcp (
+	WORD cp		/* Value to be set as active code page */
+)
+{
+	static const WORD       validcp[22] = {  437,   720,   737,   771,   775,   850,   852,   855,   857,   860,   861,   862,   863,   864,   865,   866,   869,   932,   936,   949,   950, 0};
+	static const BYTE *const tables[22] = {Ct437, Ct720, Ct737, Ct771, Ct775, Ct850, Ct852, Ct855, Ct857, Ct860, Ct861, Ct862, Ct863, Ct864, Ct865, Ct866, Ct869, Dc932, Dc936, Dc949, Dc950, 0};
+	UINT i;
+
+
+	for (i = 0; validcp[i] != 0 && validcp[i] != cp; i++) ;	/* Find the code page */
+	if (validcp[i] != cp) return FR_INVALID_PARAMETER;		/* Not found? */
+
+	CodePage = cp;
+	if (cp >= 900) {	/* DBCS */
+		ExCvt = 0;
+		DbcTbl = tables[i];
+	} else {			/* SBCS */
+		ExCvt = tables[i];
+		DbcTbl = 0;
+	}
+	return FR_OK;
+}
+#endif	/* FF_CODE_PAGE == 0 */
+
diff --git a/lib/fatfs/source/ff.h b/lib/fatfs/source/ff.h
new file mode 100644
index 000000000..e0a77124c
--- /dev/null
+++ b/lib/fatfs/source/ff.h
@@ -0,0 +1,429 @@
+/*----------------------------------------------------------------------------/
+/  FatFs - Generic FAT Filesystem module  R0.15                               /
+/-----------------------------------------------------------------------------/
+/
+/ Copyright (C) 2022, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+/
+/----------------------------------------------------------------------------*/
+
+
+#ifndef FF_DEFINED
+#define FF_DEFINED	80286	/* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ffconf.h"		/* FatFs configuration options */
+
+#if FF_DEFINED != FFCONF_DEF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+/* Integer types used for FatFs API */
+
+#if defined(_WIN32)		/* Windows VC++ (for development only) */
+#define FF_INTDEF 2
+#include <windows.h>
+typedef unsigned __int64 QWORD;
+#include <float.h>
+#define isnan(v) _isnan(v)
+#define isinf(v) (!_finite(v))
+
+#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus)	/* C99 or later */
+#define FF_INTDEF 2
+#include <stdint.h>
+typedef unsigned int	UINT;	/* int must be 16-bit or 32-bit */
+typedef unsigned char	BYTE;	/* char must be 8-bit */
+typedef uint16_t		WORD;	/* 16-bit unsigned integer */
+typedef uint32_t		DWORD;	/* 32-bit unsigned integer */
+typedef uint64_t		QWORD;	/* 64-bit unsigned integer */
+typedef WORD			WCHAR;	/* UTF-16 character type */
+
+#else  	/* Earlier than C99 */
+#define FF_INTDEF 1
+typedef unsigned int	UINT;	/* int must be 16-bit or 32-bit */
+typedef unsigned char	BYTE;	/* char must be 8-bit */
+typedef unsigned short	WORD;	/* 16-bit unsigned integer */
+typedef unsigned long	DWORD;	/* 32-bit unsigned integer */
+typedef WORD			WCHAR;	/* UTF-16 character type */
+#endif
+
+
+/* Type of file size and LBA variables */
+
+#if FF_FS_EXFAT
+#if FF_INTDEF != 2
+#error exFAT feature wants C99 or later
+#endif
+typedef QWORD FSIZE_t;
+#if FF_LBA64
+typedef QWORD LBA_t;
+#else
+typedef DWORD LBA_t;
+#endif
+#else
+#if FF_LBA64
+#error exFAT needs to be enabled when enable 64-bit LBA
+#endif
+typedef DWORD FSIZE_t;
+typedef DWORD LBA_t;
+#endif
+
+
+
+/* Type of path name strings on FatFs API (TCHAR) */
+
+#if FF_USE_LFN && FF_LFN_UNICODE == 1 	/* Unicode in UTF-16 encoding */
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#elif FF_USE_LFN && FF_LFN_UNICODE == 2	/* Unicode in UTF-8 encoding */
+typedef char TCHAR;
+#define _T(x) u8 ## x
+#define _TEXT(x) u8 ## x
+#elif FF_USE_LFN && FF_LFN_UNICODE == 3	/* Unicode in UTF-32 encoding */
+typedef DWORD TCHAR;
+#define _T(x) U ## x
+#define _TEXT(x) U ## x
+#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
+#error Wrong FF_LFN_UNICODE setting
+#else									/* ANSI/OEM code in SBCS/DBCS */
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if FF_MULTI_PARTITION		/* Multiple partition configuration */
+typedef struct {
+	BYTE pd;	/* Physical drive number */
+	BYTE pt;	/* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[];	/* Volume - Partition mapping table */
+#endif
+
+#if FF_STR_VOLUME_ID
+#ifndef FF_VOLUME_STRS
+extern const char* VolumeStr[FF_VOLUMES];	/* User defied volume ID */
+#endif
+#endif
+
+
+
+/* Filesystem object structure (FATFS) */
+
+typedef struct {
+	BYTE	fs_type;		/* Filesystem type (0:not mounted) */
+	BYTE	pdrv;			/* Volume hosting physical drive */
+	BYTE	ldrv;			/* Logical drive number (used only when FF_FS_REENTRANT) */
+	BYTE	n_fats;			/* Number of FATs (1 or 2) */
+	BYTE	wflag;			/* win[] status (b0:dirty) */
+	BYTE	fsi_flag;		/* FSINFO status (b7:disabled, b0:dirty) */
+	WORD	id;				/* Volume mount ID */
+	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
+	WORD	csize;			/* Cluster size [sectors] */
+#if FF_MAX_SS != FF_MIN_SS
+	WORD	ssize;			/* Sector size (512, 1024, 2048 or 4096) */
+#endif
+#if FF_USE_LFN
+	WCHAR*	lfnbuf;			/* LFN working buffer */
+#endif
+#if FF_FS_EXFAT
+	BYTE*	dirbuf;			/* Directory entry block scratchpad buffer for exFAT */
+#endif
+#if !FF_FS_READONLY
+	DWORD	last_clst;		/* Last allocated cluster */
+	DWORD	free_clst;		/* Number of free clusters */
+#endif
+#if FF_FS_RPATH
+	DWORD	cdir;			/* Current directory start cluster (0:root) */
+#if FF_FS_EXFAT
+	DWORD	cdc_scl;		/* Containing directory start cluster (invalid when cdir is 0) */
+	DWORD	cdc_size;		/* b31-b8:Size of containing directory, b7-b0: Chain status */
+	DWORD	cdc_ofs;		/* Offset in the containing directory (invalid when cdir is 0) */
+#endif
+#endif
+	DWORD	n_fatent;		/* Number of FAT entries (number of clusters + 2) */
+	DWORD	fsize;			/* Number of sectors per FAT */
+	LBA_t	volbase;		/* Volume base sector */
+	LBA_t	fatbase;		/* FAT base sector */
+	LBA_t	dirbase;		/* Root directory base sector (FAT12/16) or cluster (FAT32/exFAT) */
+	LBA_t	database;		/* Data base sector */
+#if FF_FS_EXFAT
+	LBA_t	bitbase;		/* Allocation bitmap base sector */
+#endif
+	LBA_t	winsect;		/* Current sector appearing in the win[] */
+	BYTE	win[FF_MAX_SS];	/* Disk access window for Directory, FAT (and file data at tiny cfg) */
+} FATFS;
+
+
+
+/* Object ID and allocation information (FFOBJID) */
+
+typedef struct {
+	FATFS*	fs;				/* Pointer to the hosting volume of this object */
+	WORD	id;				/* Hosting volume's mount ID */
+	BYTE	attr;			/* Object attribute */
+	BYTE	stat;			/* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */
+	DWORD	sclust;			/* Object data start cluster (0:no cluster or root directory) */
+	FSIZE_t	objsize;		/* Object size (valid when sclust != 0) */
+#if FF_FS_EXFAT
+	DWORD	n_cont;			/* Size of first fragment - 1 (valid when stat == 3) */
+	DWORD	n_frag;			/* Size of last fragment needs to be written to FAT (valid when not zero) */
+	DWORD	c_scl;			/* Containing directory start cluster (valid when sclust != 0) */
+	DWORD	c_size;			/* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
+	DWORD	c_ofs;			/* Offset in the containing directory (valid when file object and sclust != 0) */
+#endif
+#if FF_FS_LOCK
+	UINT	lockid;			/* File lock ID origin from 1 (index of file semaphore table Files[]) */
+#endif
+} FFOBJID;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+	FFOBJID	obj;			/* Object identifier (must be the 1st member to detect invalid object pointer) */
+	BYTE	flag;			/* File status flags */
+	BYTE	err;			/* Abort flag (error code) */
+	FSIZE_t	fptr;			/* File read/write pointer (Zeroed on file open) */
+	DWORD	clust;			/* Current cluster of fpter (invalid when fptr is 0) */
+	LBA_t	sect;			/* Sector number appearing in buf[] (0:invalid) */
+#if !FF_FS_READONLY
+	LBA_t	dir_sect;		/* Sector number containing the directory entry (not used at exFAT) */
+	BYTE*	dir_ptr;		/* Pointer to the directory entry in the win[] (not used at exFAT) */
+#endif
+#if FF_USE_FASTSEEK
+	DWORD*	cltbl;			/* Pointer to the cluster link map table (nulled on open, set by application) */
+#endif
+#if !FF_FS_TINY
+	BYTE	buf[FF_MAX_SS];	/* File private data read/write window */
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+	FFOBJID	obj;			/* Object identifier */
+	DWORD	dptr;			/* Current read/write offset */
+	DWORD	clust;			/* Current cluster */
+	LBA_t	sect;			/* Current sector (0:Read operation has terminated) */
+	BYTE*	dir;			/* Pointer to the directory item in the win[] */
+	BYTE	fn[12];			/* SFN (in/out) {body[8],ext[3],status[1]} */
+#if FF_USE_LFN
+	DWORD	blk_ofs;		/* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
+#endif
+#if FF_USE_FIND
+	const TCHAR* pat;		/* Pointer to the name matching pattern */
+#endif
+} DIR;
+
+
+
+/* File information structure (FILINFO) */
+
+typedef struct {
+	FSIZE_t	fsize;			/* File size */
+	WORD	fdate;			/* Modified date */
+	WORD	ftime;			/* Modified time */
+	BYTE	fattrib;		/* File attribute */
+#if FF_USE_LFN
+	TCHAR	altname[FF_SFN_BUF + 1];/* Alternative file name */
+	TCHAR	fname[FF_LFN_BUF + 1];	/* Primary file name */
+#else
+	TCHAR	fname[12 + 1];	/* File name */
+#endif
+} FILINFO;
+
+
+
+/* Format parameter structure (MKFS_PARM) */
+
+typedef struct {
+	BYTE fmt;			/* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */
+	BYTE n_fat;			/* Number of FATs */
+	UINT align;			/* Data area alignment (sector) */
+	UINT n_root;		/* Number of root directory entries */
+	DWORD au_size;		/* Cluster size (byte) */
+} MKFS_PARM;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,				/* (0) Succeeded */
+	FR_DISK_ERR,			/* (1) A hard error occurred in the low level disk I/O layer */
+	FR_INT_ERR,				/* (2) Assertion failed */
+	FR_NOT_READY,			/* (3) The physical drive cannot work */
+	FR_NO_FILE,				/* (4) Could not find the file */
+	FR_NO_PATH,				/* (5) Could not find the path */
+	FR_INVALID_NAME,		/* (6) The path name format is invalid */
+	FR_DENIED,				/* (7) Access denied due to prohibited access or directory full */
+	FR_EXIST,				/* (8) Access denied due to prohibited access */
+	FR_INVALID_OBJECT,		/* (9) The file/directory object is invalid */
+	FR_WRITE_PROTECTED,		/* (10) The physical drive is write protected */
+	FR_INVALID_DRIVE,		/* (11) The logical drive number is invalid */
+	FR_NOT_ENABLED,			/* (12) The volume has no work area */
+	FR_NO_FILESYSTEM,		/* (13) There is no valid FAT volume */
+	FR_MKFS_ABORTED,		/* (14) The f_mkfs() aborted due to any problem */
+	FR_TIMEOUT,				/* (15) Could not get a grant to access the volume within defined period */
+	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
+	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
+	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > FF_FS_LOCK */
+	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs Module Application Interface                           */
+/*--------------------------------------------------------------*/
+
+FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a file */
+FRESULT f_close (FIL* fp);											/* Close an open file object */
+FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from the file */
+FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to the file */
+FRESULT f_lseek (FIL* fp, FSIZE_t ofs);								/* Move file pointer of the file object */
+FRESULT f_truncate (FIL* fp);										/* Truncate the file */
+FRESULT f_sync (FIL* fp);											/* Flush cached data of the writing file */
+FRESULT f_opendir (DIR* dp, const TCHAR* path);						/* Open a directory */
+FRESULT f_closedir (DIR* dp);										/* Close an open directory */
+FRESULT f_readdir (DIR* dp, FILINFO* fno);							/* Read a directory item */
+FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern);	/* Find first file */
+FRESULT f_findnext (DIR* dp, FILINFO* fno);							/* Find next file */
+FRESULT f_mkdir (const TCHAR* path);								/* Create a sub directory */
+FRESULT f_unlink (const TCHAR* path);								/* Delete an existing file or directory */
+FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new);	/* Rename/Move a file or directory */
+FRESULT f_stat (const TCHAR* path, FILINFO* fno);					/* Get file status */
+FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask);			/* Change attribute of a file/dir */
+FRESULT f_utime (const TCHAR* path, const FILINFO* fno);			/* Change timestamp of a file/dir */
+FRESULT f_chdir (const TCHAR* path);								/* Change current directory */
+FRESULT f_chdrive (const TCHAR* path);								/* Change current drive */
+FRESULT f_getcwd (TCHAR* buff, UINT len);							/* Get current directory */
+FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get number of free clusters on the drive */
+FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn);	/* Get volume label */
+FRESULT f_setlabel (const TCHAR* label);							/* Set volume label */
+FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
+FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt);					/* Allocate a contiguous block to the file */
+FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt);			/* Mount/Unmount a logical drive */
+FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len);	/* Create a FAT volume */
+FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work);		/* Divide a physical drive into some partitions */
+FRESULT f_setcp (WORD cp);											/* Set current code page */
+int f_putc (TCHAR c, FIL* fp);										/* Put a character to the file */
+int f_puts (const TCHAR* str, FIL* cp);								/* Put a string to the file */
+int f_printf (FIL* fp, const TCHAR* str, ...);						/* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR* buff, int len, FIL* fp);						/* Get a string from the file */
+
+/* Some API fucntions are implemented as macro */
+
+#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
+#define f_error(fp) ((fp)->err)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->obj.objsize)
+#define f_rewind(fp) f_lseek((fp), 0)
+#define f_rewinddir(dp) f_readdir((dp), 0)
+#define f_rmdir(path) f_unlink(path)
+#define f_unmount(path) f_mount(0, path, 0)
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional Functions                                         */
+/*--------------------------------------------------------------*/
+
+/* RTC function (provided by user) */
+#if !FF_FS_READONLY && !FF_FS_NORTC
+DWORD get_fattime (void);	/* Get current time */
+#endif
+
+
+/* LFN support functions (defined in ffunicode.c) */
+
+#if FF_USE_LFN >= 1
+WCHAR ff_oem2uni (WCHAR oem, WORD cp);	/* OEM code to Unicode conversion */
+WCHAR ff_uni2oem (DWORD uni, WORD cp);	/* Unicode to OEM code conversion */
+DWORD ff_wtoupper (DWORD uni);			/* Unicode upper-case conversion */
+#endif
+
+
+/* O/S dependent functions (samples available in ffsystem.c) */
+
+#if FF_USE_LFN == 3		/* Dynamic memory allocation */
+void* ff_memalloc (UINT msize);		/* Allocate memory block */
+void ff_memfree (void* mblock);		/* Free memory block */
+#endif
+#if FF_FS_REENTRANT	/* Sync functions */
+int ff_mutex_create (int vol);		/* Create a sync object */
+void ff_mutex_delete (int vol);		/* Delete a sync object */
+int ff_mutex_take (int vol);		/* Lock sync object */
+void ff_mutex_give (int vol);		/* Unlock sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and Offset Address                                     */
+/*--------------------------------------------------------------*/
+
+/* File access mode and open method flags (3rd argument of f_open) */
+#define	FA_READ				0x01
+#define	FA_WRITE			0x02
+#define	FA_OPEN_EXISTING	0x00
+#define	FA_CREATE_NEW		0x04
+#define	FA_CREATE_ALWAYS	0x08
+#define	FA_OPEN_ALWAYS		0x10
+#define	FA_OPEN_APPEND		0x30
+
+/* Fast seek controls (2nd argument of f_lseek) */
+#define CREATE_LINKMAP	((FSIZE_t)0 - 1)
+
+/* Format options (2nd argument of f_mkfs) */
+#define FM_FAT		0x01
+#define FM_FAT32	0x02
+#define FM_EXFAT	0x04
+#define FM_ANY		0x07
+#define FM_SFD		0x08
+
+/* Filesystem type (FATFS.fs_type) */
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+#define FS_EXFAT	4
+
+/* File attribute bits for directory entry (FILINFO.fattrib) */
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FF_DEFINED */
diff --git a/lib/fatfs/source/ffconf.h b/lib/fatfs/source/ffconf.h
new file mode 100644
index 000000000..80b20efa1
--- /dev/null
+++ b/lib/fatfs/source/ffconf.h
@@ -0,0 +1,296 @@
+/*---------------------------------------------------------------------------/
+/  Configurations of FatFs Module
+/---------------------------------------------------------------------------*/
+
+#define FFCONF_DEF	80286	/* Revision ID */
+
+/*---------------------------------------------------------------------------/
+/ Function Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_FS_READONLY	0
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/  Read-only configuration removes writing API functions, f_write(), f_sync(),
+/  f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
+/  and optional writing functions as well. */
+
+
+#define FF_FS_MINIMIZE	0
+/* This option defines minimization level to remove some basic API functions.
+/
+/   0: Basic functions are fully enabled.
+/   1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
+/      are removed.
+/   2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/   3: f_lseek() function is removed in addition to 2. */
+
+
+#define FF_USE_FIND		0
+/* This option switches filtered directory read functions, f_findfirst() and
+/  f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
+
+
+#define FF_USE_MKFS		0
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FASTSEEK	0
+/* This option switches fast seek function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_EXPAND	0
+/* This option switches f_expand function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_CHMOD	0
+/* This option switches attribute manipulation functions, f_chmod() and f_utime().
+/  (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
+
+
+#define FF_USE_LABEL	0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/  (0:Disable or 1:Enable) */
+
+
+#define FF_USE_FORWARD	0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+
+
+#define FF_USE_STRFUNC	0
+#define FF_PRINT_LLI	1
+#define FF_PRINT_FLOAT	1
+#define FF_STRF_ENCODE	3
+/* FF_USE_STRFUNC switches string functions, f_gets(), f_putc(), f_puts() and
+/  f_printf().
+/
+/   0: Disable. FF_PRINT_LLI, FF_PRINT_FLOAT and FF_STRF_ENCODE have no effect.
+/   1: Enable without LF-CRLF conversion.
+/   2: Enable with LF-CRLF conversion.
+/
+/  FF_PRINT_LLI = 1 makes f_printf() support long long argument and FF_PRINT_FLOAT = 1/2
+/  makes f_printf() support floating point argument. These features want C99 or later.
+/  When FF_LFN_UNICODE >= 1 with LFN enabled, string functions convert the character
+/  encoding in it. FF_STRF_ENCODE selects assumption of character encoding ON THE FILE
+/  to be read/written via those functions.
+/
+/   0: ANSI/OEM in current CP
+/   1: Unicode in UTF-16LE
+/   2: Unicode in UTF-16BE
+/   3: Unicode in UTF-8
+*/
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_CODE_PAGE	437
+/* This option specifies the OEM code page to be used on the target system.
+/  Incorrect code page setting can cause a file open failure.
+/
+/   437 - U.S.
+/   720 - Arabic
+/   737 - Greek
+/   771 - KBL
+/   775 - Baltic
+/   850 - Latin 1
+/   852 - Latin 2
+/   855 - Cyrillic
+/   857 - Turkish
+/   860 - Portuguese
+/   861 - Icelandic
+/   862 - Hebrew
+/   863 - Canadian French
+/   864 - Arabic
+/   865 - Nordic
+/   866 - Russian
+/   869 - Greek 2
+/   932 - Japanese (DBCS)
+/   936 - Simplified Chinese (DBCS)
+/   949 - Korean (DBCS)
+/   950 - Traditional Chinese (DBCS)
+/     0 - Include all code pages above and configured by f_setcp()
+*/
+
+
+#define FF_USE_LFN		0
+#define FF_MAX_LFN		255
+/* The FF_USE_LFN switches the support for LFN (long file name).
+/
+/   0: Disable LFN. FF_MAX_LFN has no effect.
+/   1: Enable LFN with static  working buffer on the BSS. Always NOT thread-safe.
+/   2: Enable LFN with dynamic working buffer on the STACK.
+/   3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/  To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
+/  requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
+/  additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
+/  The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
+/  be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN
+/  specification.
+/  When use stack for the working buffer, take care on stack overflow. When use heap
+/  memory for the working buffer, memory management functions, ff_memalloc() and
+/  ff_memfree() exemplified in ffsystem.c, need to be added to the project. */
+
+
+#define FF_LFN_UNICODE	0
+/* This option switches the character encoding on the API when LFN is enabled.
+/
+/   0: ANSI/OEM in current CP (TCHAR = char)
+/   1: Unicode in UTF-16 (TCHAR = WCHAR)
+/   2: Unicode in UTF-8 (TCHAR = char)
+/   3: Unicode in UTF-32 (TCHAR = DWORD)
+/
+/  Also behavior of string I/O functions will be affected by this option.
+/  When LFN is not enabled, this option has no effect. */
+
+
+#define FF_LFN_BUF		255
+#define FF_SFN_BUF		12
+/* This set of options defines size of file name members in the FILINFO structure
+/  which is used to read out directory items. These values should be suffcient for
+/  the file names to read. The maximum possible length of the read file name depends
+/  on character encoding. When LFN is not enabled, these options have no effect. */
+
+
+#define FF_FS_RPATH		0
+/* This option configures support for relative path.
+/
+/   0: Disable relative path and remove related functions.
+/   1: Enable relative path. f_chdir() and f_chdrive() are available.
+/   2: f_getcwd() function is available in addition to 1.
+*/
+
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_VOLUMES		1
+/* Number of volumes (logical drives) to be used. (1-10) */
+
+
+#define FF_STR_VOLUME_ID	0
+#define FF_VOLUME_STRS		"RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
+/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
+/  When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
+/  number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
+/  logical drives. Number of items must not be less than FF_VOLUMES. Valid
+/  characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
+/  compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
+/  not defined, a user defined volume string table is needed as:
+/
+/  const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
+*/
+
+
+#define FF_MULTI_PARTITION	0
+/* This option switches support for multiple volumes on the physical drive.
+/  By default (0), each logical drive number is bound to the same physical drive
+/  number and only an FAT volume found on the physical drive will be mounted.
+/  When this function is enabled (1), each logical drive number can be bound to
+/  arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
+/  function will be available. */
+
+
+#define FF_MIN_SS		512
+#define FF_MAX_SS		512
+/* This set of options configures the range of sector size to be supported. (512,
+/  1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
+/  harddisk, but a larger value may be required for on-board flash memory and some
+/  type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
+/  for variable sector size mode and disk_ioctl() function needs to implement
+/  GET_SECTOR_SIZE command. */
+
+
+#define FF_LBA64		0
+/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable)
+/  To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */
+
+
+#define FF_MIN_GPT		0x10000000
+/* Minimum number of sectors to switch GPT as partitioning format in f_mkfs and
+/  f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */
+
+
+#define FF_USE_TRIM		0
+/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
+/  To enable Trim function, also CTRL_TRIM command should be implemented to the
+/  disk_ioctl() function. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/---------------------------------------------------------------------------*/
+
+#define FF_FS_TINY		0
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/  At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
+/  Instead of private sector buffer eliminated from the file object, common sector
+/  buffer in the filesystem object (FATFS) is used for the file data transfer. */
+
+
+#define FF_FS_EXFAT		0
+/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
+/  To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
+/  Note that enabling exFAT discards ANSI C (C89) compatibility. */
+
+
+#define FF_FS_NORTC		0
+#define FF_NORTC_MON	1
+#define FF_NORTC_MDAY	1
+#define FF_NORTC_YEAR	2022
+/* The option FF_FS_NORTC switches timestamp feature. If the system does not have
+/  an RTC or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable the
+/  timestamp feature. Every object modified by FatFs will have a fixed timestamp
+/  defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
+/  To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
+/  added to the project to read current time form real-time clock. FF_NORTC_MON,
+/  FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
+/  These options have no effect in read-only configuration (FF_FS_READONLY = 1). */
+
+
+#define FF_FS_NOFSINFO	0
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/  option, and f_getfree() function at the first time after volume mount will force
+/  a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/  bit0=0: Use free cluster count in the FSINFO if available.
+/  bit0=1: Do not trust free cluster count in the FSINFO.
+/  bit1=0: Use last allocated cluster number in the FSINFO if available.
+/  bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+
+#define FF_FS_LOCK		0
+/* The option FF_FS_LOCK switches file lock function to control duplicated file open
+/  and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
+/  is 1.
+/
+/  0:  Disable file lock function. To avoid volume corruption, application program
+/      should avoid illegal open, remove and rename to the open objects.
+/  >0: Enable file lock function. The value defines how many files/sub-directories
+/      can be opened simultaneously under file lock control. Note that the file
+/      lock control is independent of re-entrancy. */
+
+
+#define FF_FS_REENTRANT	0
+#define FF_FS_TIMEOUT	1000
+/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
+/  module itself. Note that regardless of this option, file access to different
+/  volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/  and f_fdisk() function, are always not re-entrant. Only file/directory access
+/  to the same volume is under control of this featuer.
+/
+/   0: Disable re-entrancy. FF_FS_TIMEOUT have no effect.
+/   1: Enable re-entrancy. Also user provided synchronization handlers,
+/      ff_mutex_create(), ff_mutex_delete(), ff_mutex_take() and ff_mutex_give()
+/      function, must be added to the project. Samples are available in ffsystem.c.
+/
+/  The FF_FS_TIMEOUT defines timeout period in unit of O/S time tick.
+*/
+
+
+
+/*--- End of configuration options ---*/
diff --git a/lib/fatfs/source/ffsystem.c b/lib/fatfs/source/ffsystem.c
new file mode 100644
index 000000000..d5c5134bf
--- /dev/null
+++ b/lib/fatfs/source/ffsystem.c
@@ -0,0 +1,208 @@
+/*------------------------------------------------------------------------*/
+/* A Sample Code of User Provided OS Dependent Functions for FatFs        */
+/*------------------------------------------------------------------------*/
+
+#include "ff.h"
+
+
+#if FF_USE_LFN == 3	/* Use dynamic memory allocation */
+
+/*------------------------------------------------------------------------*/
+/* Allocate/Free a Memory Block                                           */
+/*------------------------------------------------------------------------*/
+
+#include <stdlib.h>		/* with POSIX API */
+
+
+void* ff_memalloc (	/* Returns pointer to the allocated memory block (null if not enough core) */
+	UINT msize		/* Number of bytes to allocate */
+)
+{
+	return malloc((size_t)msize);	/* Allocate a new memory block */
+}
+
+
+void ff_memfree (
+	void* mblock	/* Pointer to the memory block to free (no effect if null) */
+)
+{
+	free(mblock);	/* Free the memory block */
+}
+
+#endif
+
+
+
+
+#if FF_FS_REENTRANT	/* Mutal exclusion */
+/*------------------------------------------------------------------------*/
+/* Definitions of Mutex                                                   */
+/*------------------------------------------------------------------------*/
+
+#define OS_TYPE	0	/* 0:Win32, 1:uITRON4.0, 2:uC/OS-II, 3:FreeRTOS, 4:CMSIS-RTOS */
+
+
+#if   OS_TYPE == 0	/* Win32 */
+#include <windows.h>
+static HANDLE Mutex[FF_VOLUMES + 1];	/* Table of mutex handle */
+
+#elif OS_TYPE == 1	/* uITRON */
+#include "itron.h"
+#include "kernel.h"
+static mtxid Mutex[FF_VOLUMES + 1];		/* Table of mutex ID */
+
+#elif OS_TYPE == 2	/* uc/OS-II */
+#include "includes.h"
+static OS_EVENT *Mutex[FF_VOLUMES + 1];	/* Table of mutex pinter */
+
+#elif OS_TYPE == 3	/* FreeRTOS */
+#include "FreeRTOS.h"
+#include "semphr.h"
+static SemaphoreHandle_t Mutex[FF_VOLUMES + 1];	/* Table of mutex handle */
+
+#elif OS_TYPE == 4	/* CMSIS-RTOS */
+#include "cmsis_os.h"
+static osMutexId Mutex[FF_VOLUMES + 1];	/* Table of mutex ID */
+
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* Create a Mutex                                                         */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount function to create a new mutex
+/  or semaphore for the volume. When a 0 is returned, the f_mount function
+/  fails with FR_INT_ERR.
+*/
+
+int ff_mutex_create (	/* Returns 1:Function succeeded or 0:Could not create the mutex */
+	int vol				/* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */
+)
+{
+#if OS_TYPE == 0	/* Win32 */
+	Mutex[vol] = CreateMutex(NULL, FALSE, NULL);
+	return (int)(Mutex[vol] != INVALID_HANDLE_VALUE);
+
+#elif OS_TYPE == 1	/* uITRON */
+	T_CMTX cmtx = {TA_TPRI,1};
+
+	Mutex[vol] = acre_mtx(&cmtx);
+	return (int)(Mutex[vol] > 0);
+
+#elif OS_TYPE == 2	/* uC/OS-II */
+	OS_ERR err;
+
+	Mutex[vol] = OSMutexCreate(0, &err);
+	return (int)(err == OS_NO_ERR);
+
+#elif OS_TYPE == 3	/* FreeRTOS */
+	Mutex[vol] = xSemaphoreCreateMutex();
+	return (int)(Mutex[vol] != NULL);
+
+#elif OS_TYPE == 4	/* CMSIS-RTOS */
+	osMutexDef(cmsis_os_mutex);
+
+	Mutex[vol] = osMutexCreate(osMutex(cmsis_os_mutex));
+	return (int)(Mutex[vol] != NULL);
+
+#endif
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Delete a Mutex                                                         */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount function to delete a mutex or
+/  semaphore of the volume created with ff_mutex_create function.
+*/
+
+void ff_mutex_delete (	/* Returns 1:Function succeeded or 0:Could not delete due to an error */
+	int vol				/* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */
+)
+{
+#if OS_TYPE == 0	/* Win32 */
+	CloseHandle(Mutex[vol]);
+
+#elif OS_TYPE == 1	/* uITRON */
+	del_mtx(Mutex[vol]);
+
+#elif OS_TYPE == 2	/* uC/OS-II */
+	OS_ERR err;
+
+	OSMutexDel(Mutex[vol], OS_DEL_ALWAYS, &err);
+
+#elif OS_TYPE == 3	/* FreeRTOS */
+	vSemaphoreDelete(Mutex[vol]);
+
+#elif OS_TYPE == 4	/* CMSIS-RTOS */
+	osMutexDelete(Mutex[vol]);
+
+#endif
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Request a Grant to Access the Volume                                   */
+/*------------------------------------------------------------------------*/
+/* This function is called on enter file functions to lock the volume.
+/  When a 0 is returned, the file function fails with FR_TIMEOUT.
+*/
+
+int ff_mutex_take (	/* Returns 1:Succeeded or 0:Timeout */
+	int vol			/* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */
+)
+{
+#if OS_TYPE == 0	/* Win32 */
+	return (int)(WaitForSingleObject(Mutex[vol], FF_FS_TIMEOUT) == WAIT_OBJECT_0);
+
+#elif OS_TYPE == 1	/* uITRON */
+	return (int)(tloc_mtx(Mutex[vol], FF_FS_TIMEOUT) == E_OK);
+
+#elif OS_TYPE == 2	/* uC/OS-II */
+	OS_ERR err;
+
+	OSMutexPend(Mutex[vol], FF_FS_TIMEOUT, &err));
+	return (int)(err == OS_NO_ERR);
+
+#elif OS_TYPE == 3	/* FreeRTOS */
+	return (int)(xSemaphoreTake(Mutex[vol], FF_FS_TIMEOUT) == pdTRUE);
+
+#elif OS_TYPE == 4	/* CMSIS-RTOS */
+	return (int)(osMutexWait(Mutex[vol], FF_FS_TIMEOUT) == osOK);
+
+#endif
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Release a Grant to Access the Volume                                   */
+/*------------------------------------------------------------------------*/
+/* This function is called on leave file functions to unlock the volume.
+*/
+
+void ff_mutex_give (
+	int vol			/* Mutex ID: Volume mutex (0 to FF_VOLUMES - 1) or system mutex (FF_VOLUMES) */
+)
+{
+#if OS_TYPE == 0	/* Win32 */
+	ReleaseMutex(Mutex[vol]);
+
+#elif OS_TYPE == 1	/* uITRON */
+	unl_mtx(Mutex[vol]);
+
+#elif OS_TYPE == 2	/* uC/OS-II */
+	OSMutexPost(Mutex[vol]);
+
+#elif OS_TYPE == 3	/* FreeRTOS */
+	xSemaphoreGive(Mutex[vol]);
+
+#elif OS_TYPE == 4	/* CMSIS-RTOS */
+	osMutexRelease(Mutex[vol]);
+
+#endif
+}
+
+#endif	/* FF_FS_REENTRANT */
+
diff --git a/lib/fatfs/source/ffunicode.c b/lib/fatfs/source/ffunicode.c
new file mode 100644
index 000000000..e6bcacae6
--- /dev/null
+++ b/lib/fatfs/source/ffunicode.c
@@ -0,0 +1,15593 @@
+/*------------------------------------------------------------------------*/
+/* Unicode Handling Functions for FatFs R0.13 and Later                   */
+/*------------------------------------------------------------------------*/
+/* This module will occupy a huge memory in the .rodata section when the  */
+/* FatFs is configured for LFN with DBCS. If the system has a Unicode     */
+/* library for the code conversion, this module should be modified to use */
+/* it to avoid silly memory consumption.                                  */
+/*------------------------------------------------------------------------*/
+/*
+/ Copyright (C) 2022, ChaN, all right reserved.
+/
+/ FatFs module is an open source software. Redistribution and use of FatFs in
+/ source and binary forms, with or without modification, are permitted provided
+/ that the following condition is met:
+/
+/ 1. Redistributions of source code must retain the above copyright notice,
+/    this condition and the following disclaimer.
+/
+/ This software is provided by the copyright holder and contributors "AS IS"
+/ and any warranties related to this software are DISCLAIMED.
+/ The copyright owner or contributors be NOT LIABLE for any damages caused
+/ by use of this software.
+*/
+
+
+#include "ff.h"
+
+#if FF_USE_LFN != 0	/* This module will be blanked if in non-LFN configuration */
+
+#define MERGE2(a, b) a ## b
+#define CVTBL(tbl, cp) MERGE2(tbl, cp)
+
+
+/*------------------------------------------------------------------------*/
+/* Code Conversion Tables                                                 */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE == 932 || FF_CODE_PAGE == 0	/* Japanese */
+static const WCHAR uni2oem932[] = {	/* Unicode --> Shift_JIS pairs */
+	0x00A7, 0x8198, 0x00A8, 0x814E, 0x00B0, 0x818B, 0x00B1, 0x817D,	0x00B4, 0x814C, 0x00B6, 0x81F7, 0x00D7, 0x817E, 0x00F7, 0x8180,
+	0x0391, 0x839F, 0x0392, 0x83A0, 0x0393, 0x83A1, 0x0394, 0x83A2,	0x0395, 0x83A3, 0x0396, 0x83A4, 0x0397, 0x83A5, 0x0398, 0x83A6,
+	0x0399, 0x83A7, 0x039A, 0x83A8, 0x039B, 0x83A9, 0x039C, 0x83AA,	0x039D, 0x83AB, 0x039E, 0x83AC, 0x039F, 0x83AD, 0x03A0, 0x83AE,
+	0x03A1, 0x83AF, 0x03A3, 0x83B0, 0x03A4, 0x83B1, 0x03A5, 0x83B2,	0x03A6, 0x83B3, 0x03A7, 0x83B4, 0x03A8, 0x83B5, 0x03A9, 0x83B6,
+	0x03B1, 0x83BF, 0x03B2, 0x83C0, 0x03B3, 0x83C1, 0x03B4, 0x83C2,	0x03B5, 0x83C3, 0x03B6, 0x83C4, 0x03B7, 0x83C5, 0x03B8, 0x83C6,
+	0x03B9, 0x83C7, 0x03BA, 0x83C8, 0x03BB, 0x83C9, 0x03BC, 0x83CA,	0x03BD, 0x83CB, 0x03BE, 0x83CC, 0x03BF, 0x83CD, 0x03C0, 0x83CE,
+	0x03C1, 0x83CF, 0x03C3, 0x83D0, 0x03C4, 0x83D1, 0x03C5, 0x83D2,	0x03C6, 0x83D3, 0x03C7, 0x83D4, 0x03C8, 0x83D5, 0x03C9, 0x83D6,
+	0x0401, 0x8446, 0x0410, 0x8440, 0x0411, 0x8441, 0x0412, 0x8442,	0x0413, 0x8443, 0x0414, 0x8444, 0x0415, 0x8445, 0x0416, 0x8447,
+	0x0417, 0x8448, 0x0418, 0x8449, 0x0419, 0x844A, 0x041A, 0x844B,	0x041B, 0x844C, 0x041C, 0x844D, 0x041D, 0x844E, 0x041E, 0x844F,
+	0x041F, 0x8450, 0x0420, 0x8451, 0x0421, 0x8452, 0x0422, 0x8453,	0x0423, 0x8454, 0x0424, 0x8455, 0x0425, 0x8456, 0x0426, 0x8457,
+	0x0427, 0x8458, 0x0428, 0x8459, 0x0429, 0x845A, 0x042A, 0x845B,	0x042B, 0x845C, 0x042C, 0x845D, 0x042D, 0x845E, 0x042E, 0x845F,
+	0x042F, 0x8460, 0x0430, 0x8470, 0x0431, 0x8471, 0x0432, 0x8472,	0x0433, 0x8473, 0x0434, 0x8474, 0x0435, 0x8475, 0x0436, 0x8477,
+	0x0437, 0x8478, 0x0438, 0x8479, 0x0439, 0x847A, 0x043A, 0x847B,	0x043B, 0x847C, 0x043C, 0x847D, 0x043D, 0x847E, 0x043E, 0x8480,
+	0x043F, 0x8481, 0x0440, 0x8482, 0x0441, 0x8483, 0x0442, 0x8484,	0x0443, 0x8485, 0x0444, 0x8486, 0x0445, 0x8487, 0x0446, 0x8488,
+	0x0447, 0x8489, 0x0448, 0x848A, 0x0449, 0x848B, 0x044A, 0x848C,	0x044B, 0x848D, 0x044C, 0x848E, 0x044D, 0x848F, 0x044E, 0x8490,
+	0x044F, 0x8491, 0x0451, 0x8476, 0x2010, 0x815D, 0x2015, 0x815C,	0x2018, 0x8165, 0x2019, 0x8166, 0x201C, 0x8167, 0x201D, 0x8168,
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+	0x9A37, 0xE97A, 0x9A3E, 0xE980, 0x9A40, 0xE97D, 0x9A42, 0xE97C,	0x9A43, 0xE97E, 0x9A45, 0xE97B, 0x9A4D, 0xE982, 0x9A4E, 0xFBFB,
+	0x9A55, 0xE981, 0x9A57, 0xE984, 0x9A5A, 0x8BC1, 0x9A5B, 0xE983,	0x9A5F, 0xE985, 0x9A62, 0xE986, 0x9A64, 0xE988, 0x9A65, 0xE987,
+	0x9A69, 0xE989, 0x9A6A, 0xE98B, 0x9A6B, 0xE98A, 0x9AA8, 0x8D9C,	0x9AAD, 0xE98C, 0x9AB0, 0xE98D, 0x9AB8, 0x8A5B, 0x9ABC, 0xE98E,
+	0x9AC0, 0xE98F, 0x9AC4, 0x9091, 0x9ACF, 0xE990, 0x9AD1, 0xE991,	0x9AD3, 0xE992, 0x9AD4, 0xE993, 0x9AD8, 0x8D82, 0x9AD9, 0xFBFC,
+	0x9ADC, 0xFC40, 0x9ADE, 0xE994, 0x9ADF, 0xE995, 0x9AE2, 0xE996,	0x9AE3, 0xE997, 0x9AE6, 0xE998, 0x9AEA, 0x94AF, 0x9AEB, 0xE99A,
+	0x9AED, 0x9545, 0x9AEE, 0xE99B, 0x9AEF, 0xE999, 0x9AF1, 0xE99D,	0x9AF4, 0xE99C, 0x9AF7, 0xE99E, 0x9AFB, 0xE99F, 0x9B06, 0xE9A0,
+	0x9B18, 0xE9A1, 0x9B1A, 0xE9A2, 0x9B1F, 0xE9A3, 0x9B22, 0xE9A4,	0x9B23, 0xE9A5, 0x9B25, 0xE9A6, 0x9B27, 0xE9A7, 0x9B28, 0xE9A8,
+	0x9B29, 0xE9A9, 0x9B2A, 0xE9AA, 0x9B2E, 0xE9AB, 0x9B2F, 0xE9AC,	0x9B31, 0x9F54, 0x9B32, 0xE9AD, 0x9B3B, 0xE2F6, 0x9B3C, 0x8B53,
+	0x9B41, 0x8A40, 0x9B42, 0x8DB0, 0x9B43, 0xE9AF, 0x9B44, 0xE9AE,	0x9B45, 0x96A3, 0x9B4D, 0xE9B1, 0x9B4E, 0xE9B2, 0x9B4F, 0xE9B0,
+	0x9B51, 0xE9B3, 0x9B54, 0x9682, 0x9B58, 0xE9B4, 0x9B5A, 0x8B9B,	0x9B6F, 0x9844, 0x9B72, 0xFC42, 0x9B74, 0xE9B5, 0x9B75, 0xFC41,
+	0x9B83, 0xE9B7, 0x9B8E, 0x88BC, 0x9B8F, 0xFC43, 0x9B91, 0xE9B8,	0x9B92, 0x95A9, 0x9B93, 0xE9B6, 0x9B96, 0xE9B9, 0x9B97, 0xE9BA,
+	0x9B9F, 0xE9BB, 0x9BA0, 0xE9BC, 0x9BA8, 0xE9BD, 0x9BAA, 0x968E,	0x9BAB, 0x8E4C, 0x9BAD, 0x8DF8, 0x9BAE, 0x914E, 0x9BB1, 0xFC44,
+	0x9BB4, 0xE9BE, 0x9BB9, 0xE9C1, 0x9BBB, 0xFC45, 0x9BC0, 0xE9BF,	0x9BC6, 0xE9C2, 0x9BC9, 0x8CEF, 0x9BCA, 0xE9C0, 0x9BCF, 0xE9C3,
+	0x9BD1, 0xE9C4, 0x9BD2, 0xE9C5, 0x9BD4, 0xE9C9, 0x9BD6, 0x8E49,	0x9BDB, 0x91E2, 0x9BE1, 0xE9CA, 0x9BE2, 0xE9C7, 0x9BE3, 0xE9C6,
+	0x9BE4, 0xE9C8, 0x9BE8, 0x8C7E, 0x9BF0, 0xE9CE, 0x9BF1, 0xE9CD,	0x9BF2, 0xE9CC, 0x9BF5, 0x88B1, 0x9C00, 0xFC46, 0x9C04, 0xE9D8,
+	0x9C06, 0xE9D4, 0x9C08, 0xE9D5, 0x9C09, 0xE9D1, 0x9C0A, 0xE9D7,	0x9C0C, 0xE9D3, 0x9C0D, 0x8A82, 0x9C10, 0x986B, 0x9C12, 0xE9D6,
+	0x9C13, 0xE9D2, 0x9C14, 0xE9D0, 0x9C15, 0xE9CF, 0x9C1B, 0xE9DA,	0x9C21, 0xE9DD, 0x9C24, 0xE9DC, 0x9C25, 0xE9DB, 0x9C2D, 0x9568,
+	0x9C2E, 0xE9D9, 0x9C2F, 0x88F1, 0x9C30, 0xE9DE, 0x9C32, 0xE9E0,	0x9C39, 0x8A8F, 0x9C3A, 0xE9CB, 0x9C3B, 0x8956, 0x9C3E, 0xE9E2,
+	0x9C46, 0xE9E1, 0x9C47, 0xE9DF, 0x9C48, 0x924C, 0x9C52, 0x9690,	0x9C57, 0x97D8, 0x9C5A, 0xE9E3, 0x9C60, 0xE9E4, 0x9C67, 0xE9E5,
+	0x9C76, 0xE9E6, 0x9C78, 0xE9E7, 0x9CE5, 0x92B9, 0x9CE7, 0xE9E8,	0x9CE9, 0x94B5, 0x9CEB, 0xE9ED, 0x9CEC, 0xE9E9, 0x9CF0, 0xE9EA,
+	0x9CF3, 0x9650, 0x9CF4, 0x96C2, 0x9CF6, 0x93CE, 0x9D03, 0xE9EE,	0x9D06, 0xE9EF, 0x9D07, 0x93BC, 0x9D08, 0xE9EC, 0x9D09, 0xE9EB,
+	0x9D0E, 0x89A8, 0x9D12, 0xE9F7, 0x9D15, 0xE9F6, 0x9D1B, 0x8995,	0x9D1F, 0xE9F4, 0x9D23, 0xE9F3, 0x9D26, 0xE9F1, 0x9D28, 0x8A9B,
+	0x9D2A, 0xE9F0, 0x9D2B, 0x8EB0, 0x9D2C, 0x89A7, 0x9D3B, 0x8D83,	0x9D3E, 0xE9FA, 0x9D3F, 0xE9F9, 0x9D41, 0xE9F8, 0x9D44, 0xE9F5,
+	0x9D46, 0xE9FB, 0x9D48, 0xE9FC, 0x9D50, 0xEA44, 0x9D51, 0xEA43,	0x9D59, 0xEA45, 0x9D5C, 0x894C, 0x9D5D, 0xEA40, 0x9D5E, 0xEA41,
+	0x9D60, 0x8D94, 0x9D61, 0x96B7, 0x9D64, 0xEA42, 0x9D6B, 0xFC48,	0x9D6C, 0x9651, 0x9D6F, 0xEA4A, 0x9D70, 0xFC47, 0x9D72, 0xEA46,
+	0x9D7A, 0xEA4B, 0x9D87, 0xEA48, 0x9D89, 0xEA47, 0x9D8F, 0x8C7B,	0x9D9A, 0xEA4C, 0x9DA4, 0xEA4D, 0x9DA9, 0xEA4E, 0x9DAB, 0xEA49,
+	0x9DAF, 0xE9F2, 0x9DB2, 0xEA4F, 0x9DB4, 0x92DF, 0x9DB8, 0xEA53,	0x9DBA, 0xEA54, 0x9DBB, 0xEA52, 0x9DC1, 0xEA51, 0x9DC2, 0xEA57,
+	0x9DC4, 0xEA50, 0x9DC6, 0xEA55, 0x9DCF, 0xEA56, 0x9DD3, 0xEA59,	0x9DD9, 0xEA58, 0x9DE6, 0xEA5B, 0x9DED, 0xEA5C, 0x9DEF, 0xEA5D,
+	0x9DF2, 0x9868, 0x9DF8, 0xEA5A, 0x9DF9, 0x91E9, 0x9DFA, 0x8DEB,	0x9DFD, 0xEA5E, 0x9E19, 0xFC4A, 0x9E1A, 0xEA5F, 0x9E1B, 0xEA60,
+	0x9E1E, 0xEA61, 0x9E75, 0xEA62, 0x9E78, 0x8CB2, 0x9E79, 0xEA63,	0x9E7D, 0xEA64, 0x9E7F, 0x8EAD, 0x9E81, 0xEA65, 0x9E88, 0xEA66,
+	0x9E8B, 0xEA67, 0x9E8C, 0xEA68, 0x9E91, 0xEA6B, 0x9E92, 0xEA69,	0x9E93, 0x985B, 0x9E95, 0xEA6A, 0x9E97, 0x97ED, 0x9E9D, 0xEA6C,
+	0x9E9F, 0x97D9, 0x9EA5, 0xEA6D, 0x9EA6, 0x949E, 0x9EA9, 0xEA6E,	0x9EAA, 0xEA70, 0x9EAD, 0xEA71, 0x9EB8, 0xEA6F, 0x9EB9, 0x8D8D,
+	0x9EBA, 0x96CB, 0x9EBB, 0x9683, 0x9EBC, 0x9BF5, 0x9EBE, 0x9F80,	0x9EBF, 0x969B, 0x9EC4, 0x89A9, 0x9ECC, 0xEA73, 0x9ECD, 0x8B6F,
+	0x9ECE, 0xEA74, 0x9ECF, 0xEA75, 0x9ED0, 0xEA76, 0x9ED1, 0xFC4B,	0x9ED2, 0x8D95, 0x9ED4, 0xEA77, 0x9ED8, 0xE0D2, 0x9ED9, 0x96D9,
+	0x9EDB, 0x91E1, 0x9EDC, 0xEA78, 0x9EDD, 0xEA7A, 0x9EDE, 0xEA79,	0x9EE0, 0xEA7B, 0x9EE5, 0xEA7C, 0x9EE8, 0xEA7D, 0x9EEF, 0xEA7E,
+	0x9EF4, 0xEA80, 0x9EF6, 0xEA81, 0x9EF7, 0xEA82, 0x9EF9, 0xEA83,	0x9EFB, 0xEA84, 0x9EFC, 0xEA85, 0x9EFD, 0xEA86, 0x9F07, 0xEA87,
+	0x9F08, 0xEA88, 0x9F0E, 0x9343, 0x9F13, 0x8CDB, 0x9F15, 0xEA8A,	0x9F20, 0x916C, 0x9F21, 0xEA8B, 0x9F2C, 0xEA8C, 0x9F3B, 0x9540,
+	0x9F3E, 0xEA8D, 0x9F4A, 0xEA8E, 0x9F4B, 0xE256, 0x9F4E, 0xE6D8,	0x9F4F, 0xE8EB, 0x9F52, 0xEA8F, 0x9F54, 0xEA90, 0x9F5F, 0xEA92,
+	0x9F60, 0xEA93, 0x9F61, 0xEA94, 0x9F62, 0x97EE, 0x9F63, 0xEA91,	0x9F66, 0xEA95, 0x9F67, 0xEA96, 0x9F6A, 0xEA98, 0x9F6C, 0xEA97,
+	0x9F72, 0xEA9A, 0x9F76, 0xEA9B, 0x9F77, 0xEA99, 0x9F8D, 0x97B4,	0x9F95, 0xEA9C, 0x9F9C, 0xEA9D, 0x9F9D, 0xE273, 0x9FA0, 0xEA9E,
+	0xF929, 0xFAE0, 0xF9DC, 0xFBE9, 0xFA0E, 0xFA90, 0xFA0F, 0xFA9B,	0xFA10, 0xFA9C, 0xFA11, 0xFAB1, 0xFA12, 0xFAD8, 0xFA13, 0xFAE8,
+	0xFA14, 0xFAEA, 0xFA15, 0xFB58, 0xFA16, 0xFB5E, 0xFA17, 0xFB75,	0xFA18, 0xFB7D, 0xFA19, 0xFB7E, 0xFA1A, 0xFB80, 0xFA1B, 0xFB82,
+	0xFA1C, 0xFB86, 0xFA1D, 0xFB89, 0xFA1E, 0xFB92, 0xFA1F, 0xFB9D,	0xFA20, 0xFB9F, 0xFA21, 0xFBA0, 0xFA22, 0xFBA9, 0xFA23, 0xFBB1,
+	0xFA24, 0xFBB3, 0xFA25, 0xFBB4, 0xFA26, 0xFBB7, 0xFA27, 0xFBD3,	0xFA28, 0xFBDA, 0xFA29, 0xFBEA, 0xFA2A, 0xFBF6, 0xFA2B, 0xFBF7,
+	0xFA2C, 0xFBF9, 0xFA2D, 0xFC49, 0xFF01, 0x8149, 0xFF02, 0xFA57,	0xFF03, 0x8194, 0xFF04, 0x8190, 0xFF05, 0x8193, 0xFF06, 0x8195,
+	0xFF07, 0xFA56, 0xFF08, 0x8169, 0xFF09, 0x816A, 0xFF0A, 0x8196,	0xFF0B, 0x817B, 0xFF0C, 0x8143, 0xFF0D, 0x817C, 0xFF0E, 0x8144,
+	0xFF0F, 0x815E, 0xFF10, 0x824F, 0xFF11, 0x8250, 0xFF12, 0x8251,	0xFF13, 0x8252, 0xFF14, 0x8253, 0xFF15, 0x8254, 0xFF16, 0x8255,
+	0xFF17, 0x8256, 0xFF18, 0x8257, 0xFF19, 0x8258, 0xFF1A, 0x8146,	0xFF1B, 0x8147, 0xFF1C, 0x8183, 0xFF1D, 0x8181, 0xFF1E, 0x8184,
+	0xFF1F, 0x8148, 0xFF20, 0x8197, 0xFF21, 0x8260, 0xFF22, 0x8261,	0xFF23, 0x8262, 0xFF24, 0x8263, 0xFF25, 0x8264, 0xFF26, 0x8265,
+	0xFF27, 0x8266, 0xFF28, 0x8267, 0xFF29, 0x8268, 0xFF2A, 0x8269,	0xFF2B, 0x826A, 0xFF2C, 0x826B, 0xFF2D, 0x826C, 0xFF2E, 0x826D,
+	0xFF2F, 0x826E, 0xFF30, 0x826F, 0xFF31, 0x8270, 0xFF32, 0x8271,	0xFF33, 0x8272, 0xFF34, 0x8273, 0xFF35, 0x8274, 0xFF36, 0x8275,
+	0xFF37, 0x8276, 0xFF38, 0x8277, 0xFF39, 0x8278, 0xFF3A, 0x8279,	0xFF3B, 0x816D, 0xFF3C, 0x815F, 0xFF3D, 0x816E, 0xFF3E, 0x814F,
+	0xFF3F, 0x8151, 0xFF40, 0x814D, 0xFF41, 0x8281, 0xFF42, 0x8282,	0xFF43, 0x8283, 0xFF44, 0x8284, 0xFF45, 0x8285, 0xFF46, 0x8286,
+	0xFF47, 0x8287, 0xFF48, 0x8288, 0xFF49, 0x8289, 0xFF4A, 0x828A,	0xFF4B, 0x828B, 0xFF4C, 0x828C, 0xFF4D, 0x828D, 0xFF4E, 0x828E,
+	0xFF4F, 0x828F, 0xFF50, 0x8290, 0xFF51, 0x8291, 0xFF52, 0x8292,	0xFF53, 0x8293, 0xFF54, 0x8294, 0xFF55, 0x8295, 0xFF56, 0x8296,
+	0xFF57, 0x8297, 0xFF58, 0x8298, 0xFF59, 0x8299, 0xFF5A, 0x829A,	0xFF5B, 0x816F, 0xFF5C, 0x8162, 0xFF5D, 0x8170, 0xFF5E, 0x8160,
+	0xFF61, 0x00A1, 0xFF62, 0x00A2, 0xFF63, 0x00A3, 0xFF64, 0x00A4,	0xFF65, 0x00A5, 0xFF66, 0x00A6, 0xFF67, 0x00A7, 0xFF68, 0x00A8,
+	0xFF69, 0x00A9, 0xFF6A, 0x00AA, 0xFF6B, 0x00AB, 0xFF6C, 0x00AC,	0xFF6D, 0x00AD, 0xFF6E, 0x00AE, 0xFF6F, 0x00AF, 0xFF70, 0x00B0,
+	0xFF71, 0x00B1, 0xFF72, 0x00B2, 0xFF73, 0x00B3, 0xFF74, 0x00B4,	0xFF75, 0x00B5, 0xFF76, 0x00B6, 0xFF77, 0x00B7, 0xFF78, 0x00B8,
+	0xFF79, 0x00B9, 0xFF7A, 0x00BA, 0xFF7B, 0x00BB, 0xFF7C, 0x00BC,	0xFF7D, 0x00BD, 0xFF7E, 0x00BE, 0xFF7F, 0x00BF, 0xFF80, 0x00C0,
+	0xFF81, 0x00C1, 0xFF82, 0x00C2, 0xFF83, 0x00C3, 0xFF84, 0x00C4,	0xFF85, 0x00C5, 0xFF86, 0x00C6, 0xFF87, 0x00C7, 0xFF88, 0x00C8,
+	0xFF89, 0x00C9, 0xFF8A, 0x00CA, 0xFF8B, 0x00CB, 0xFF8C, 0x00CC,	0xFF8D, 0x00CD, 0xFF8E, 0x00CE, 0xFF8F, 0x00CF, 0xFF90, 0x00D0,
+	0xFF91, 0x00D1, 0xFF92, 0x00D2, 0xFF93, 0x00D3, 0xFF94, 0x00D4,	0xFF95, 0x00D5, 0xFF96, 0x00D6, 0xFF97, 0x00D7, 0xFF98, 0x00D8,
+	0xFF99, 0x00D9, 0xFF9A, 0x00DA, 0xFF9B, 0x00DB, 0xFF9C, 0x00DC,	0xFF9D, 0x00DD, 0xFF9E, 0x00DE, 0xFF9F, 0x00DF, 0xFFE0, 0x8191,
+	0xFFE1, 0x8192, 0xFFE2, 0x81CA, 0xFFE3, 0x8150, 0xFFE4, 0xFA55,	0xFFE5, 0x818F, 0, 0
+};
+
+static const WCHAR oem2uni932[] = {	/* Shift_JIS --> Unicode pairs */
+	0x00A1, 0xFF61, 0x00A2, 0xFF62, 0x00A3, 0xFF63, 0x00A4, 0xFF64,	0x00A5, 0xFF65, 0x00A6, 0xFF66, 0x00A7, 0xFF67, 0x00A8, 0xFF68,
+	0x00A9, 0xFF69, 0x00AA, 0xFF6A, 0x00AB, 0xFF6B, 0x00AC, 0xFF6C,	0x00AD, 0xFF6D, 0x00AE, 0xFF6E, 0x00AF, 0xFF6F, 0x00B0, 0xFF70,
+	0x00B1, 0xFF71, 0x00B2, 0xFF72, 0x00B3, 0xFF73, 0x00B4, 0xFF74,	0x00B5, 0xFF75, 0x00B6, 0xFF76, 0x00B7, 0xFF77, 0x00B8, 0xFF78,
+	0x00B9, 0xFF79, 0x00BA, 0xFF7A, 0x00BB, 0xFF7B, 0x00BC, 0xFF7C,	0x00BD, 0xFF7D, 0x00BE, 0xFF7E, 0x00BF, 0xFF7F, 0x00C0, 0xFF80,
+	0x00C1, 0xFF81, 0x00C2, 0xFF82, 0x00C3, 0xFF83, 0x00C4, 0xFF84,	0x00C5, 0xFF85, 0x00C6, 0xFF86, 0x00C7, 0xFF87, 0x00C8, 0xFF88,
+	0x00C9, 0xFF89, 0x00CA, 0xFF8A, 0x00CB, 0xFF8B, 0x00CC, 0xFF8C,	0x00CD, 0xFF8D, 0x00CE, 0xFF8E, 0x00CF, 0xFF8F, 0x00D0, 0xFF90,
+	0x00D1, 0xFF91, 0x00D2, 0xFF92, 0x00D3, 0xFF93, 0x00D4, 0xFF94,	0x00D5, 0xFF95, 0x00D6, 0xFF96, 0x00D7, 0xFF97, 0x00D8, 0xFF98,
+	0x00D9, 0xFF99, 0x00DA, 0xFF9A, 0x00DB, 0xFF9B, 0x00DC, 0xFF9C,	0x00DD, 0xFF9D, 0x00DE, 0xFF9E, 0x00DF, 0xFF9F, 0x8140, 0x3000,
+	0x8141, 0x3001, 0x8142, 0x3002, 0x8143, 0xFF0C, 0x8144, 0xFF0E,	0x8145, 0x30FB, 0x8146, 0xFF1A, 0x8147, 0xFF1B, 0x8148, 0xFF1F,
+	0x8149, 0xFF01, 0x814A, 0x309B, 0x814B, 0x309C, 0x814C, 0x00B4,	0x814D, 0xFF40, 0x814E, 0x00A8, 0x814F, 0xFF3E, 0x8150, 0xFFE3,
+	0x8151, 0xFF3F, 0x8152, 0x30FD, 0x8153, 0x30FE, 0x8154, 0x309D,	0x8155, 0x309E, 0x8156, 0x3003, 0x8157, 0x4EDD, 0x8158, 0x3005,
+	0x8159, 0x3006, 0x815A, 0x3007, 0x815B, 0x30FC, 0x815C, 0x2015,	0x815D, 0x2010, 0x815E, 0xFF0F, 0x815F, 0xFF3C, 0x8160, 0xFF5E,
+	0x8161, 0x2225, 0x8162, 0xFF5C, 0x8163, 0x2026, 0x8164, 0x2025,	0x8165, 0x2018, 0x8166, 0x2019, 0x8167, 0x201C, 0x8168, 0x201D,
+	0x8169, 0xFF08, 0x816A, 0xFF09, 0x816B, 0x3014, 0x816C, 0x3015,	0x816D, 0xFF3B, 0x816E, 0xFF3D, 0x816F, 0xFF5B, 0x8170, 0xFF5D,
+	0x8171, 0x3008, 0x8172, 0x3009, 0x8173, 0x300A, 0x8174, 0x300B,	0x8175, 0x300C, 0x8176, 0x300D, 0x8177, 0x300E, 0x8178, 0x300F,
+	0x8179, 0x3010, 0x817A, 0x3011, 0x817B, 0xFF0B, 0x817C, 0xFF0D,	0x817D, 0x00B1, 0x817E, 0x00D7, 0x8180, 0x00F7, 0x8181, 0xFF1D,
+	0x8182, 0x2260, 0x8183, 0xFF1C, 0x8184, 0xFF1E, 0x8185, 0x2266,	0x8186, 0x2267, 0x8187, 0x221E, 0x8188, 0x2234, 0x8189, 0x2642,
+	0x818A, 0x2640, 0x818B, 0x00B0, 0x818C, 0x2032, 0x818D, 0x2033,	0x818E, 0x2103, 0x818F, 0xFFE5, 0x8190, 0xFF04, 0x8191, 0xFFE0,
+	0x8192, 0xFFE1, 0x8193, 0xFF05, 0x8194, 0xFF03, 0x8195, 0xFF06,	0x8196, 0xFF0A, 0x8197, 0xFF20, 0x8198, 0x00A7, 0x8199, 0x2606,
+	0x819A, 0x2605, 0x819B, 0x25CB, 0x819C, 0x25CF, 0x819D, 0x25CE,	0x819E, 0x25C7, 0x819F, 0x25C6, 0x81A0, 0x25A1, 0x81A1, 0x25A0,
+	0x81A2, 0x25B3, 0x81A3, 0x25B2, 0x81A4, 0x25BD, 0x81A5, 0x25BC,	0x81A6, 0x203B, 0x81A7, 0x3012, 0x81A8, 0x2192, 0x81A9, 0x2190,
+	0x81AA, 0x2191, 0x81AB, 0x2193, 0x81AC, 0x3013, 0x81B8, 0x2208,	0x81B9, 0x220B, 0x81BA, 0x2286, 0x81BB, 0x2287, 0x81BC, 0x2282,
+	0x81BD, 0x2283, 0x81BE, 0x222A, 0x81BF, 0x2229, 0x81C8, 0x2227,	0x81C9, 0x2228, 0x81CA, 0xFFE2, 0x81CB, 0x21D2, 0x81CC, 0x21D4,
+	0x81CD, 0x2200, 0x81CE, 0x2203, 0x81DA, 0x2220, 0x81DB, 0x22A5,	0x81DC, 0x2312, 0x81DD, 0x2202, 0x81DE, 0x2207, 0x81DF, 0x2261,
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+	0xE2C5, 0x7C00, 0xE2C6, 0x7C07, 0xE2C7, 0x7C13, 0xE2C8, 0x7BF3,	0xE2C9, 0x7BF7, 0xE2CA, 0x7C17, 0xE2CB, 0x7C0D, 0xE2CC, 0x7BF6,
+	0xE2CD, 0x7C23, 0xE2CE, 0x7C27, 0xE2CF, 0x7C2A, 0xE2D0, 0x7C1F,	0xE2D1, 0x7C37, 0xE2D2, 0x7C2B, 0xE2D3, 0x7C3D, 0xE2D4, 0x7C4C,
+	0xE2D5, 0x7C43, 0xE2D6, 0x7C54, 0xE2D7, 0x7C4F, 0xE2D8, 0x7C40,	0xE2D9, 0x7C50, 0xE2DA, 0x7C58, 0xE2DB, 0x7C5F, 0xE2DC, 0x7C64,
+	0xE2DD, 0x7C56, 0xE2DE, 0x7C65, 0xE2DF, 0x7C6C, 0xE2E0, 0x7C75,	0xE2E1, 0x7C83, 0xE2E2, 0x7C90, 0xE2E3, 0x7CA4, 0xE2E4, 0x7CAD,
+	0xE2E5, 0x7CA2, 0xE2E6, 0x7CAB, 0xE2E7, 0x7CA1, 0xE2E8, 0x7CA8,	0xE2E9, 0x7CB3, 0xE2EA, 0x7CB2, 0xE2EB, 0x7CB1, 0xE2EC, 0x7CAE,
+	0xE2ED, 0x7CB9, 0xE2EE, 0x7CBD, 0xE2EF, 0x7CC0, 0xE2F0, 0x7CC5,	0xE2F1, 0x7CC2, 0xE2F2, 0x7CD8, 0xE2F3, 0x7CD2, 0xE2F4, 0x7CDC,
+	0xE2F5, 0x7CE2, 0xE2F6, 0x9B3B, 0xE2F7, 0x7CEF, 0xE2F8, 0x7CF2,	0xE2F9, 0x7CF4, 0xE2FA, 0x7CF6, 0xE2FB, 0x7CFA, 0xE2FC, 0x7D06,
+	0xE340, 0x7D02, 0xE341, 0x7D1C, 0xE342, 0x7D15, 0xE343, 0x7D0A,	0xE344, 0x7D45, 0xE345, 0x7D4B, 0xE346, 0x7D2E, 0xE347, 0x7D32,
+	0xE348, 0x7D3F, 0xE349, 0x7D35, 0xE34A, 0x7D46, 0xE34B, 0x7D73,	0xE34C, 0x7D56, 0xE34D, 0x7D4E, 0xE34E, 0x7D72, 0xE34F, 0x7D68,
+	0xE350, 0x7D6E, 0xE351, 0x7D4F, 0xE352, 0x7D63, 0xE353, 0x7D93,	0xE354, 0x7D89, 0xE355, 0x7D5B, 0xE356, 0x7D8F, 0xE357, 0x7D7D,
+	0xE358, 0x7D9B, 0xE359, 0x7DBA, 0xE35A, 0x7DAE, 0xE35B, 0x7DA3,	0xE35C, 0x7DB5, 0xE35D, 0x7DC7, 0xE35E, 0x7DBD, 0xE35F, 0x7DAB,
+	0xE360, 0x7E3D, 0xE361, 0x7DA2, 0xE362, 0x7DAF, 0xE363, 0x7DDC,	0xE364, 0x7DB8, 0xE365, 0x7D9F, 0xE366, 0x7DB0, 0xE367, 0x7DD8,
+	0xE368, 0x7DDD, 0xE369, 0x7DE4, 0xE36A, 0x7DDE, 0xE36B, 0x7DFB,	0xE36C, 0x7DF2, 0xE36D, 0x7DE1, 0xE36E, 0x7E05, 0xE36F, 0x7E0A,
+	0xE370, 0x7E23, 0xE371, 0x7E21, 0xE372, 0x7E12, 0xE373, 0x7E31,	0xE374, 0x7E1F, 0xE375, 0x7E09, 0xE376, 0x7E0B, 0xE377, 0x7E22,
+	0xE378, 0x7E46, 0xE379, 0x7E66, 0xE37A, 0x7E3B, 0xE37B, 0x7E35,	0xE37C, 0x7E39, 0xE37D, 0x7E43, 0xE37E, 0x7E37, 0xE380, 0x7E32,
+	0xE381, 0x7E3A, 0xE382, 0x7E67, 0xE383, 0x7E5D, 0xE384, 0x7E56,	0xE385, 0x7E5E, 0xE386, 0x7E59, 0xE387, 0x7E5A, 0xE388, 0x7E79,
+	0xE389, 0x7E6A, 0xE38A, 0x7E69, 0xE38B, 0x7E7C, 0xE38C, 0x7E7B,	0xE38D, 0x7E83, 0xE38E, 0x7DD5, 0xE38F, 0x7E7D, 0xE390, 0x8FAE,
+	0xE391, 0x7E7F, 0xE392, 0x7E88, 0xE393, 0x7E89, 0xE394, 0x7E8C,	0xE395, 0x7E92, 0xE396, 0x7E90, 0xE397, 0x7E93, 0xE398, 0x7E94,
+	0xE399, 0x7E96, 0xE39A, 0x7E8E, 0xE39B, 0x7E9B, 0xE39C, 0x7E9C,	0xE39D, 0x7F38, 0xE39E, 0x7F3A, 0xE39F, 0x7F45, 0xE3A0, 0x7F4C,
+	0xE3A1, 0x7F4D, 0xE3A2, 0x7F4E, 0xE3A3, 0x7F50, 0xE3A4, 0x7F51,	0xE3A5, 0x7F55, 0xE3A6, 0x7F54, 0xE3A7, 0x7F58, 0xE3A8, 0x7F5F,
+	0xE3A9, 0x7F60, 0xE3AA, 0x7F68, 0xE3AB, 0x7F69, 0xE3AC, 0x7F67,	0xE3AD, 0x7F78, 0xE3AE, 0x7F82, 0xE3AF, 0x7F86, 0xE3B0, 0x7F83,
+	0xE3B1, 0x7F88, 0xE3B2, 0x7F87, 0xE3B3, 0x7F8C, 0xE3B4, 0x7F94,	0xE3B5, 0x7F9E, 0xE3B6, 0x7F9D, 0xE3B7, 0x7F9A, 0xE3B8, 0x7FA3,
+	0xE3B9, 0x7FAF, 0xE3BA, 0x7FB2, 0xE3BB, 0x7FB9, 0xE3BC, 0x7FAE,	0xE3BD, 0x7FB6, 0xE3BE, 0x7FB8, 0xE3BF, 0x8B71, 0xE3C0, 0x7FC5,
+	0xE3C1, 0x7FC6, 0xE3C2, 0x7FCA, 0xE3C3, 0x7FD5, 0xE3C4, 0x7FD4,	0xE3C5, 0x7FE1, 0xE3C6, 0x7FE6, 0xE3C7, 0x7FE9, 0xE3C8, 0x7FF3,
+	0xE3C9, 0x7FF9, 0xE3CA, 0x98DC, 0xE3CB, 0x8006, 0xE3CC, 0x8004,	0xE3CD, 0x800B, 0xE3CE, 0x8012, 0xE3CF, 0x8018, 0xE3D0, 0x8019,
+	0xE3D1, 0x801C, 0xE3D2, 0x8021, 0xE3D3, 0x8028, 0xE3D4, 0x803F,	0xE3D5, 0x803B, 0xE3D6, 0x804A, 0xE3D7, 0x8046, 0xE3D8, 0x8052,
+	0xE3D9, 0x8058, 0xE3DA, 0x805A, 0xE3DB, 0x805F, 0xE3DC, 0x8062,	0xE3DD, 0x8068, 0xE3DE, 0x8073, 0xE3DF, 0x8072, 0xE3E0, 0x8070,
+	0xE3E1, 0x8076, 0xE3E2, 0x8079, 0xE3E3, 0x807D, 0xE3E4, 0x807F,	0xE3E5, 0x8084, 0xE3E6, 0x8086, 0xE3E7, 0x8085, 0xE3E8, 0x809B,
+	0xE3E9, 0x8093, 0xE3EA, 0x809A, 0xE3EB, 0x80AD, 0xE3EC, 0x5190,	0xE3ED, 0x80AC, 0xE3EE, 0x80DB, 0xE3EF, 0x80E5, 0xE3F0, 0x80D9,
+	0xE3F1, 0x80DD, 0xE3F2, 0x80C4, 0xE3F3, 0x80DA, 0xE3F4, 0x80D6,	0xE3F5, 0x8109, 0xE3F6, 0x80EF, 0xE3F7, 0x80F1, 0xE3F8, 0x811B,
+	0xE3F9, 0x8129, 0xE3FA, 0x8123, 0xE3FB, 0x812F, 0xE3FC, 0x814B,	0xE440, 0x968B, 0xE441, 0x8146, 0xE442, 0x813E, 0xE443, 0x8153,
+	0xE444, 0x8151, 0xE445, 0x80FC, 0xE446, 0x8171, 0xE447, 0x816E,	0xE448, 0x8165, 0xE449, 0x8166, 0xE44A, 0x8174, 0xE44B, 0x8183,
+	0xE44C, 0x8188, 0xE44D, 0x818A, 0xE44E, 0x8180, 0xE44F, 0x8182,	0xE450, 0x81A0, 0xE451, 0x8195, 0xE452, 0x81A4, 0xE453, 0x81A3,
+	0xE454, 0x815F, 0xE455, 0x8193, 0xE456, 0x81A9, 0xE457, 0x81B0,	0xE458, 0x81B5, 0xE459, 0x81BE, 0xE45A, 0x81B8, 0xE45B, 0x81BD,
+	0xE45C, 0x81C0, 0xE45D, 0x81C2, 0xE45E, 0x81BA, 0xE45F, 0x81C9,	0xE460, 0x81CD, 0xE461, 0x81D1, 0xE462, 0x81D9, 0xE463, 0x81D8,
+	0xE464, 0x81C8, 0xE465, 0x81DA, 0xE466, 0x81DF, 0xE467, 0x81E0,	0xE468, 0x81E7, 0xE469, 0x81FA, 0xE46A, 0x81FB, 0xE46B, 0x81FE,
+	0xE46C, 0x8201, 0xE46D, 0x8202, 0xE46E, 0x8205, 0xE46F, 0x8207,	0xE470, 0x820A, 0xE471, 0x820D, 0xE472, 0x8210, 0xE473, 0x8216,
+	0xE474, 0x8229, 0xE475, 0x822B, 0xE476, 0x8238, 0xE477, 0x8233,	0xE478, 0x8240, 0xE479, 0x8259, 0xE47A, 0x8258, 0xE47B, 0x825D,
+	0xE47C, 0x825A, 0xE47D, 0x825F, 0xE47E, 0x8264, 0xE480, 0x8262,	0xE481, 0x8268, 0xE482, 0x826A, 0xE483, 0x826B, 0xE484, 0x822E,
+	0xE485, 0x8271, 0xE486, 0x8277, 0xE487, 0x8278, 0xE488, 0x827E,	0xE489, 0x828D, 0xE48A, 0x8292, 0xE48B, 0x82AB, 0xE48C, 0x829F,
+	0xE48D, 0x82BB, 0xE48E, 0x82AC, 0xE48F, 0x82E1, 0xE490, 0x82E3,	0xE491, 0x82DF, 0xE492, 0x82D2, 0xE493, 0x82F4, 0xE494, 0x82F3,
+	0xE495, 0x82FA, 0xE496, 0x8393, 0xE497, 0x8303, 0xE498, 0x82FB,	0xE499, 0x82F9, 0xE49A, 0x82DE, 0xE49B, 0x8306, 0xE49C, 0x82DC,
+	0xE49D, 0x8309, 0xE49E, 0x82D9, 0xE49F, 0x8335, 0xE4A0, 0x8334,	0xE4A1, 0x8316, 0xE4A2, 0x8332, 0xE4A3, 0x8331, 0xE4A4, 0x8340,
+	0xE4A5, 0x8339, 0xE4A6, 0x8350, 0xE4A7, 0x8345, 0xE4A8, 0x832F,	0xE4A9, 0x832B, 0xE4AA, 0x8317, 0xE4AB, 0x8318, 0xE4AC, 0x8385,
+	0xE4AD, 0x839A, 0xE4AE, 0x83AA, 0xE4AF, 0x839F, 0xE4B0, 0x83A2,	0xE4B1, 0x8396, 0xE4B2, 0x8323, 0xE4B3, 0x838E, 0xE4B4, 0x8387,
+	0xE4B5, 0x838A, 0xE4B6, 0x837C, 0xE4B7, 0x83B5, 0xE4B8, 0x8373,	0xE4B9, 0x8375, 0xE4BA, 0x83A0, 0xE4BB, 0x8389, 0xE4BC, 0x83A8,
+	0xE4BD, 0x83F4, 0xE4BE, 0x8413, 0xE4BF, 0x83EB, 0xE4C0, 0x83CE,	0xE4C1, 0x83FD, 0xE4C2, 0x8403, 0xE4C3, 0x83D8, 0xE4C4, 0x840B,
+	0xE4C5, 0x83C1, 0xE4C6, 0x83F7, 0xE4C7, 0x8407, 0xE4C8, 0x83E0,	0xE4C9, 0x83F2, 0xE4CA, 0x840D, 0xE4CB, 0x8422, 0xE4CC, 0x8420,
+	0xE4CD, 0x83BD, 0xE4CE, 0x8438, 0xE4CF, 0x8506, 0xE4D0, 0x83FB,	0xE4D1, 0x846D, 0xE4D2, 0x842A, 0xE4D3, 0x843C, 0xE4D4, 0x855A,
+	0xE4D5, 0x8484, 0xE4D6, 0x8477, 0xE4D7, 0x846B, 0xE4D8, 0x84AD,	0xE4D9, 0x846E, 0xE4DA, 0x8482, 0xE4DB, 0x8469, 0xE4DC, 0x8446,
+	0xE4DD, 0x842C, 0xE4DE, 0x846F, 0xE4DF, 0x8479, 0xE4E0, 0x8435,	0xE4E1, 0x84CA, 0xE4E2, 0x8462, 0xE4E3, 0x84B9, 0xE4E4, 0x84BF,
+	0xE4E5, 0x849F, 0xE4E6, 0x84D9, 0xE4E7, 0x84CD, 0xE4E8, 0x84BB,	0xE4E9, 0x84DA, 0xE4EA, 0x84D0, 0xE4EB, 0x84C1, 0xE4EC, 0x84C6,
+	0xE4ED, 0x84D6, 0xE4EE, 0x84A1, 0xE4EF, 0x8521, 0xE4F0, 0x84FF,	0xE4F1, 0x84F4, 0xE4F2, 0x8517, 0xE4F3, 0x8518, 0xE4F4, 0x852C,
+	0xE4F5, 0x851F, 0xE4F6, 0x8515, 0xE4F7, 0x8514, 0xE4F8, 0x84FC,	0xE4F9, 0x8540, 0xE4FA, 0x8563, 0xE4FB, 0x8558, 0xE4FC, 0x8548,
+	0xE540, 0x8541, 0xE541, 0x8602, 0xE542, 0x854B, 0xE543, 0x8555,	0xE544, 0x8580, 0xE545, 0x85A4, 0xE546, 0x8588, 0xE547, 0x8591,
+	0xE548, 0x858A, 0xE549, 0x85A8, 0xE54A, 0x856D, 0xE54B, 0x8594,	0xE54C, 0x859B, 0xE54D, 0x85EA, 0xE54E, 0x8587, 0xE54F, 0x859C,
+	0xE550, 0x8577, 0xE551, 0x857E, 0xE552, 0x8590, 0xE553, 0x85C9,	0xE554, 0x85BA, 0xE555, 0x85CF, 0xE556, 0x85B9, 0xE557, 0x85D0,
+	0xE558, 0x85D5, 0xE559, 0x85DD, 0xE55A, 0x85E5, 0xE55B, 0x85DC,	0xE55C, 0x85F9, 0xE55D, 0x860A, 0xE55E, 0x8613, 0xE55F, 0x860B,
+	0xE560, 0x85FE, 0xE561, 0x85FA, 0xE562, 0x8606, 0xE563, 0x8622,	0xE564, 0x861A, 0xE565, 0x8630, 0xE566, 0x863F, 0xE567, 0x864D,
+	0xE568, 0x4E55, 0xE569, 0x8654, 0xE56A, 0x865F, 0xE56B, 0x8667,	0xE56C, 0x8671, 0xE56D, 0x8693, 0xE56E, 0x86A3, 0xE56F, 0x86A9,
+	0xE570, 0x86AA, 0xE571, 0x868B, 0xE572, 0x868C, 0xE573, 0x86B6,	0xE574, 0x86AF, 0xE575, 0x86C4, 0xE576, 0x86C6, 0xE577, 0x86B0,
+	0xE578, 0x86C9, 0xE579, 0x8823, 0xE57A, 0x86AB, 0xE57B, 0x86D4,	0xE57C, 0x86DE, 0xE57D, 0x86E9, 0xE57E, 0x86EC, 0xE580, 0x86DF,
+	0xE581, 0x86DB, 0xE582, 0x86EF, 0xE583, 0x8712, 0xE584, 0x8706,	0xE585, 0x8708, 0xE586, 0x8700, 0xE587, 0x8703, 0xE588, 0x86FB,
+	0xE589, 0x8711, 0xE58A, 0x8709, 0xE58B, 0x870D, 0xE58C, 0x86F9,	0xE58D, 0x870A, 0xE58E, 0x8734, 0xE58F, 0x873F, 0xE590, 0x8737,
+	0xE591, 0x873B, 0xE592, 0x8725, 0xE593, 0x8729, 0xE594, 0x871A,	0xE595, 0x8760, 0xE596, 0x875F, 0xE597, 0x8778, 0xE598, 0x874C,
+	0xE599, 0x874E, 0xE59A, 0x8774, 0xE59B, 0x8757, 0xE59C, 0x8768,	0xE59D, 0x876E, 0xE59E, 0x8759, 0xE59F, 0x8753, 0xE5A0, 0x8763,
+	0xE5A1, 0x876A, 0xE5A2, 0x8805, 0xE5A3, 0x87A2, 0xE5A4, 0x879F,	0xE5A5, 0x8782, 0xE5A6, 0x87AF, 0xE5A7, 0x87CB, 0xE5A8, 0x87BD,
+	0xE5A9, 0x87C0, 0xE5AA, 0x87D0, 0xE5AB, 0x96D6, 0xE5AC, 0x87AB,	0xE5AD, 0x87C4, 0xE5AE, 0x87B3, 0xE5AF, 0x87C7, 0xE5B0, 0x87C6,
+	0xE5B1, 0x87BB, 0xE5B2, 0x87EF, 0xE5B3, 0x87F2, 0xE5B4, 0x87E0,	0xE5B5, 0x880F, 0xE5B6, 0x880D, 0xE5B7, 0x87FE, 0xE5B8, 0x87F6,
+	0xE5B9, 0x87F7, 0xE5BA, 0x880E, 0xE5BB, 0x87D2, 0xE5BC, 0x8811,	0xE5BD, 0x8816, 0xE5BE, 0x8815, 0xE5BF, 0x8822, 0xE5C0, 0x8821,
+	0xE5C1, 0x8831, 0xE5C2, 0x8836, 0xE5C3, 0x8839, 0xE5C4, 0x8827,	0xE5C5, 0x883B, 0xE5C6, 0x8844, 0xE5C7, 0x8842, 0xE5C8, 0x8852,
+	0xE5C9, 0x8859, 0xE5CA, 0x885E, 0xE5CB, 0x8862, 0xE5CC, 0x886B,	0xE5CD, 0x8881, 0xE5CE, 0x887E, 0xE5CF, 0x889E, 0xE5D0, 0x8875,
+	0xE5D1, 0x887D, 0xE5D2, 0x88B5, 0xE5D3, 0x8872, 0xE5D4, 0x8882,	0xE5D5, 0x8897, 0xE5D6, 0x8892, 0xE5D7, 0x88AE, 0xE5D8, 0x8899,
+	0xE5D9, 0x88A2, 0xE5DA, 0x888D, 0xE5DB, 0x88A4, 0xE5DC, 0x88B0,	0xE5DD, 0x88BF, 0xE5DE, 0x88B1, 0xE5DF, 0x88C3, 0xE5E0, 0x88C4,
+	0xE5E1, 0x88D4, 0xE5E2, 0x88D8, 0xE5E3, 0x88D9, 0xE5E4, 0x88DD,	0xE5E5, 0x88F9, 0xE5E6, 0x8902, 0xE5E7, 0x88FC, 0xE5E8, 0x88F4,
+	0xE5E9, 0x88E8, 0xE5EA, 0x88F2, 0xE5EB, 0x8904, 0xE5EC, 0x890C,	0xE5ED, 0x890A, 0xE5EE, 0x8913, 0xE5EF, 0x8943, 0xE5F0, 0x891E,
+	0xE5F1, 0x8925, 0xE5F2, 0x892A, 0xE5F3, 0x892B, 0xE5F4, 0x8941,	0xE5F5, 0x8944, 0xE5F6, 0x893B, 0xE5F7, 0x8936, 0xE5F8, 0x8938,
+	0xE5F9, 0x894C, 0xE5FA, 0x891D, 0xE5FB, 0x8960, 0xE5FC, 0x895E,	0xE640, 0x8966, 0xE641, 0x8964, 0xE642, 0x896D, 0xE643, 0x896A,
+	0xE644, 0x896F, 0xE645, 0x8974, 0xE646, 0x8977, 0xE647, 0x897E,	0xE648, 0x8983, 0xE649, 0x8988, 0xE64A, 0x898A, 0xE64B, 0x8993,
+	0xE64C, 0x8998, 0xE64D, 0x89A1, 0xE64E, 0x89A9, 0xE64F, 0x89A6,	0xE650, 0x89AC, 0xE651, 0x89AF, 0xE652, 0x89B2, 0xE653, 0x89BA,
+	0xE654, 0x89BD, 0xE655, 0x89BF, 0xE656, 0x89C0, 0xE657, 0x89DA,	0xE658, 0x89DC, 0xE659, 0x89DD, 0xE65A, 0x89E7, 0xE65B, 0x89F4,
+	0xE65C, 0x89F8, 0xE65D, 0x8A03, 0xE65E, 0x8A16, 0xE65F, 0x8A10,	0xE660, 0x8A0C, 0xE661, 0x8A1B, 0xE662, 0x8A1D, 0xE663, 0x8A25,
+	0xE664, 0x8A36, 0xE665, 0x8A41, 0xE666, 0x8A5B, 0xE667, 0x8A52,	0xE668, 0x8A46, 0xE669, 0x8A48, 0xE66A, 0x8A7C, 0xE66B, 0x8A6D,
+	0xE66C, 0x8A6C, 0xE66D, 0x8A62, 0xE66E, 0x8A85, 0xE66F, 0x8A82,	0xE670, 0x8A84, 0xE671, 0x8AA8, 0xE672, 0x8AA1, 0xE673, 0x8A91,
+	0xE674, 0x8AA5, 0xE675, 0x8AA6, 0xE676, 0x8A9A, 0xE677, 0x8AA3,	0xE678, 0x8AC4, 0xE679, 0x8ACD, 0xE67A, 0x8AC2, 0xE67B, 0x8ADA,
+	0xE67C, 0x8AEB, 0xE67D, 0x8AF3, 0xE67E, 0x8AE7, 0xE680, 0x8AE4,	0xE681, 0x8AF1, 0xE682, 0x8B14, 0xE683, 0x8AE0, 0xE684, 0x8AE2,
+	0xE685, 0x8AF7, 0xE686, 0x8ADE, 0xE687, 0x8ADB, 0xE688, 0x8B0C,	0xE689, 0x8B07, 0xE68A, 0x8B1A, 0xE68B, 0x8AE1, 0xE68C, 0x8B16,
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+	0xEA4C, 0x9D9A, 0xEA4D, 0x9DA4, 0xEA4E, 0x9DA9, 0xEA4F, 0x9DB2,	0xEA50, 0x9DC4, 0xEA51, 0x9DC1, 0xEA52, 0x9DBB, 0xEA53, 0x9DB8,
+	0xEA54, 0x9DBA, 0xEA55, 0x9DC6, 0xEA56, 0x9DCF, 0xEA57, 0x9DC2,	0xEA58, 0x9DD9, 0xEA59, 0x9DD3, 0xEA5A, 0x9DF8, 0xEA5B, 0x9DE6,
+	0xEA5C, 0x9DED, 0xEA5D, 0x9DEF, 0xEA5E, 0x9DFD, 0xEA5F, 0x9E1A,	0xEA60, 0x9E1B, 0xEA61, 0x9E1E, 0xEA62, 0x9E75, 0xEA63, 0x9E79,
+	0xEA64, 0x9E7D, 0xEA65, 0x9E81, 0xEA66, 0x9E88, 0xEA67, 0x9E8B,	0xEA68, 0x9E8C, 0xEA69, 0x9E92, 0xEA6A, 0x9E95, 0xEA6B, 0x9E91,
+	0xEA6C, 0x9E9D, 0xEA6D, 0x9EA5, 0xEA6E, 0x9EA9, 0xEA6F, 0x9EB8,	0xEA70, 0x9EAA, 0xEA71, 0x9EAD, 0xEA72, 0x9761, 0xEA73, 0x9ECC,
+	0xEA74, 0x9ECE, 0xEA75, 0x9ECF, 0xEA76, 0x9ED0, 0xEA77, 0x9ED4,	0xEA78, 0x9EDC, 0xEA79, 0x9EDE, 0xEA7A, 0x9EDD, 0xEA7B, 0x9EE0,
+	0xEA7C, 0x9EE5, 0xEA7D, 0x9EE8, 0xEA7E, 0x9EEF, 0xEA80, 0x9EF4,	0xEA81, 0x9EF6, 0xEA82, 0x9EF7, 0xEA83, 0x9EF9, 0xEA84, 0x9EFB,
+	0xEA85, 0x9EFC, 0xEA86, 0x9EFD, 0xEA87, 0x9F07, 0xEA88, 0x9F08,	0xEA89, 0x76B7, 0xEA8A, 0x9F15, 0xEA8B, 0x9F21, 0xEA8C, 0x9F2C,
+	0xEA8D, 0x9F3E, 0xEA8E, 0x9F4A, 0xEA8F, 0x9F52, 0xEA90, 0x9F54,	0xEA91, 0x9F63, 0xEA92, 0x9F5F, 0xEA93, 0x9F60, 0xEA94, 0x9F61,
+	0xEA95, 0x9F66, 0xEA96, 0x9F67, 0xEA97, 0x9F6C, 0xEA98, 0x9F6A,	0xEA99, 0x9F77, 0xEA9A, 0x9F72, 0xEA9B, 0x9F76, 0xEA9C, 0x9F95,
+	0xEA9D, 0x9F9C, 0xEA9E, 0x9FA0, 0xEA9F, 0x582F, 0xEAA0, 0x69C7,	0xEAA1, 0x9059, 0xEAA2, 0x7464, 0xEAA3, 0x51DC, 0xEAA4, 0x7199,
+	0xFA40, 0x2170, 0xFA41, 0x2171, 0xFA42, 0x2172, 0xFA43, 0x2173,	0xFA44, 0x2174, 0xFA45, 0x2175, 0xFA46, 0x2176, 0xFA47, 0x2177,
+	0xFA48, 0x2178, 0xFA49, 0x2179, 0xFA55, 0xFFE4, 0xFA56, 0xFF07,	0xFA57, 0xFF02, 0xFA5C, 0x7E8A, 0xFA5D, 0x891C, 0xFA5E, 0x9348,
+	0xFA5F, 0x9288, 0xFA60, 0x84DC, 0xFA61, 0x4FC9, 0xFA62, 0x70BB,	0xFA63, 0x6631, 0xFA64, 0x68C8, 0xFA65, 0x92F9, 0xFA66, 0x66FB,
+	0xFA67, 0x5F45, 0xFA68, 0x4E28, 0xFA69, 0x4EE1, 0xFA6A, 0x4EFC,	0xFA6B, 0x4F00, 0xFA6C, 0x4F03, 0xFA6D, 0x4F39, 0xFA6E, 0x4F56,
+	0xFA6F, 0x4F92, 0xFA70, 0x4F8A, 0xFA71, 0x4F9A, 0xFA72, 0x4F94,	0xFA73, 0x4FCD, 0xFA74, 0x5040, 0xFA75, 0x5022, 0xFA76, 0x4FFF,
+	0xFA77, 0x501E, 0xFA78, 0x5046, 0xFA79, 0x5070, 0xFA7A, 0x5042,	0xFA7B, 0x5094, 0xFA7C, 0x50F4, 0xFA7D, 0x50D8, 0xFA7E, 0x514A,
+	0xFA80, 0x5164, 0xFA81, 0x519D, 0xFA82, 0x51BE, 0xFA83, 0x51EC,	0xFA84, 0x5215, 0xFA85, 0x529C, 0xFA86, 0x52A6, 0xFA87, 0x52C0,
+	0xFA88, 0x52DB, 0xFA89, 0x5300, 0xFA8A, 0x5307, 0xFA8B, 0x5324,	0xFA8C, 0x5372, 0xFA8D, 0x5393, 0xFA8E, 0x53B2, 0xFA8F, 0x53DD,
+	0xFA90, 0xFA0E, 0xFA91, 0x549C, 0xFA92, 0x548A, 0xFA93, 0x54A9,	0xFA94, 0x54FF, 0xFA95, 0x5586, 0xFA96, 0x5759, 0xFA97, 0x5765,
+	0xFA98, 0x57AC, 0xFA99, 0x57C8, 0xFA9A, 0x57C7, 0xFA9B, 0xFA0F,	0xFA9C, 0xFA10, 0xFA9D, 0x589E, 0xFA9E, 0x58B2, 0xFA9F, 0x590B,
+	0xFAA0, 0x5953, 0xFAA1, 0x595B, 0xFAA2, 0x595D, 0xFAA3, 0x5963,	0xFAA4, 0x59A4, 0xFAA5, 0x59BA, 0xFAA6, 0x5B56, 0xFAA7, 0x5BC0,
+	0xFAA8, 0x752F, 0xFAA9, 0x5BD8, 0xFAAA, 0x5BEC, 0xFAAB, 0x5C1E,	0xFAAC, 0x5CA6, 0xFAAD, 0x5CBA, 0xFAAE, 0x5CF5, 0xFAAF, 0x5D27,
+	0xFAB0, 0x5D53, 0xFAB1, 0xFA11, 0xFAB2, 0x5D42, 0xFAB3, 0x5D6D,	0xFAB4, 0x5DB8, 0xFAB5, 0x5DB9, 0xFAB6, 0x5DD0, 0xFAB7, 0x5F21,
+	0xFAB8, 0x5F34, 0xFAB9, 0x5F67, 0xFABA, 0x5FB7, 0xFABB, 0x5FDE,	0xFABC, 0x605D, 0xFABD, 0x6085, 0xFABE, 0x608A, 0xFABF, 0x60DE,
+	0xFAC0, 0x60D5, 0xFAC1, 0x6120, 0xFAC2, 0x60F2, 0xFAC3, 0x6111,	0xFAC4, 0x6137, 0xFAC5, 0x6130, 0xFAC6, 0x6198, 0xFAC7, 0x6213,
+	0xFAC8, 0x62A6, 0xFAC9, 0x63F5, 0xFACA, 0x6460, 0xFACB, 0x649D,	0xFACC, 0x64CE, 0xFACD, 0x654E, 0xFACE, 0x6600, 0xFACF, 0x6615,
+	0xFAD0, 0x663B, 0xFAD1, 0x6609, 0xFAD2, 0x662E, 0xFAD3, 0x661E,	0xFAD4, 0x6624, 0xFAD5, 0x6665, 0xFAD6, 0x6657, 0xFAD7, 0x6659,
+	0xFAD8, 0xFA12, 0xFAD9, 0x6673, 0xFADA, 0x6699, 0xFADB, 0x66A0,	0xFADC, 0x66B2, 0xFADD, 0x66BF, 0xFADE, 0x66FA, 0xFADF, 0x670E,
+	0xFAE0, 0xF929, 0xFAE1, 0x6766, 0xFAE2, 0x67BB, 0xFAE3, 0x6852,	0xFAE4, 0x67C0, 0xFAE5, 0x6801, 0xFAE6, 0x6844, 0xFAE7, 0x68CF,
+	0xFAE8, 0xFA13, 0xFAE9, 0x6968, 0xFAEA, 0xFA14, 0xFAEB, 0x6998,	0xFAEC, 0x69E2, 0xFAED, 0x6A30, 0xFAEE, 0x6A6B, 0xFAEF, 0x6A46,
+	0xFAF0, 0x6A73, 0xFAF1, 0x6A7E, 0xFAF2, 0x6AE2, 0xFAF3, 0x6AE4,	0xFAF4, 0x6BD6, 0xFAF5, 0x6C3F, 0xFAF6, 0x6C5C, 0xFAF7, 0x6C86,
+	0xFAF8, 0x6C6F, 0xFAF9, 0x6CDA, 0xFAFA, 0x6D04, 0xFAFB, 0x6D87,	0xFAFC, 0x6D6F, 0xFB40, 0x6D96, 0xFB41, 0x6DAC, 0xFB42, 0x6DCF,
+	0xFB43, 0x6DF8, 0xFB44, 0x6DF2, 0xFB45, 0x6DFC, 0xFB46, 0x6E39,	0xFB47, 0x6E5C, 0xFB48, 0x6E27, 0xFB49, 0x6E3C, 0xFB4A, 0x6EBF,
+	0xFB4B, 0x6F88, 0xFB4C, 0x6FB5, 0xFB4D, 0x6FF5, 0xFB4E, 0x7005,	0xFB4F, 0x7007, 0xFB50, 0x7028, 0xFB51, 0x7085, 0xFB52, 0x70AB,
+	0xFB53, 0x710F, 0xFB54, 0x7104, 0xFB55, 0x715C, 0xFB56, 0x7146,	0xFB57, 0x7147, 0xFB58, 0xFA15, 0xFB59, 0x71C1, 0xFB5A, 0x71FE,
+	0xFB5B, 0x72B1, 0xFB5C, 0x72BE, 0xFB5D, 0x7324, 0xFB5E, 0xFA16,	0xFB5F, 0x7377, 0xFB60, 0x73BD, 0xFB61, 0x73C9, 0xFB62, 0x73D6,
+	0xFB63, 0x73E3, 0xFB64, 0x73D2, 0xFB65, 0x7407, 0xFB66, 0x73F5,	0xFB67, 0x7426, 0xFB68, 0x742A, 0xFB69, 0x7429, 0xFB6A, 0x742E,
+	0xFB6B, 0x7462, 0xFB6C, 0x7489, 0xFB6D, 0x749F, 0xFB6E, 0x7501,	0xFB6F, 0x756F, 0xFB70, 0x7682, 0xFB71, 0x769C, 0xFB72, 0x769E,
+	0xFB73, 0x769B, 0xFB74, 0x76A6, 0xFB75, 0xFA17, 0xFB76, 0x7746,	0xFB77, 0x52AF, 0xFB78, 0x7821, 0xFB79, 0x784E, 0xFB7A, 0x7864,
+	0xFB7B, 0x787A, 0xFB7C, 0x7930, 0xFB7D, 0xFA18, 0xFB7E, 0xFA19,	0xFB80, 0xFA1A, 0xFB81, 0x7994, 0xFB82, 0xFA1B, 0xFB83, 0x799B,
+	0xFB84, 0x7AD1, 0xFB85, 0x7AE7, 0xFB86, 0xFA1C, 0xFB87, 0x7AEB,	0xFB88, 0x7B9E, 0xFB89, 0xFA1D, 0xFB8A, 0x7D48, 0xFB8B, 0x7D5C,
+	0xFB8C, 0x7DB7, 0xFB8D, 0x7DA0, 0xFB8E, 0x7DD6, 0xFB8F, 0x7E52,	0xFB90, 0x7F47, 0xFB91, 0x7FA1, 0xFB92, 0xFA1E, 0xFB93, 0x8301,
+	0xFB94, 0x8362, 0xFB95, 0x837F, 0xFB96, 0x83C7, 0xFB97, 0x83F6,	0xFB98, 0x8448, 0xFB99, 0x84B4, 0xFB9A, 0x8553, 0xFB9B, 0x8559,
+	0xFB9C, 0x856B, 0xFB9D, 0xFA1F, 0xFB9E, 0x85B0, 0xFB9F, 0xFA20,	0xFBA0, 0xFA21, 0xFBA1, 0x8807, 0xFBA2, 0x88F5, 0xFBA3, 0x8A12,
+	0xFBA4, 0x8A37, 0xFBA5, 0x8A79, 0xFBA6, 0x8AA7, 0xFBA7, 0x8ABE,	0xFBA8, 0x8ADF, 0xFBA9, 0xFA22, 0xFBAA, 0x8AF6, 0xFBAB, 0x8B53,
+	0xFBAC, 0x8B7F, 0xFBAD, 0x8CF0, 0xFBAE, 0x8CF4, 0xFBAF, 0x8D12,	0xFBB0, 0x8D76, 0xFBB1, 0xFA23, 0xFBB2, 0x8ECF, 0xFBB3, 0xFA24,
+	0xFBB4, 0xFA25, 0xFBB5, 0x9067, 0xFBB6, 0x90DE, 0xFBB7, 0xFA26,	0xFBB8, 0x9115, 0xFBB9, 0x9127, 0xFBBA, 0x91DA, 0xFBBB, 0x91D7,
+	0xFBBC, 0x91DE, 0xFBBD, 0x91ED, 0xFBBE, 0x91EE, 0xFBBF, 0x91E4,	0xFBC0, 0x91E5, 0xFBC1, 0x9206, 0xFBC2, 0x9210, 0xFBC3, 0x920A,
+	0xFBC4, 0x923A, 0xFBC5, 0x9240, 0xFBC6, 0x923C, 0xFBC7, 0x924E,	0xFBC8, 0x9259, 0xFBC9, 0x9251, 0xFBCA, 0x9239, 0xFBCB, 0x9267,
+	0xFBCC, 0x92A7, 0xFBCD, 0x9277, 0xFBCE, 0x9278, 0xFBCF, 0x92E7,	0xFBD0, 0x92D7, 0xFBD1, 0x92D9, 0xFBD2, 0x92D0, 0xFBD3, 0xFA27,
+	0xFBD4, 0x92D5, 0xFBD5, 0x92E0, 0xFBD6, 0x92D3, 0xFBD7, 0x9325,	0xFBD8, 0x9321, 0xFBD9, 0x92FB, 0xFBDA, 0xFA28, 0xFBDB, 0x931E,
+	0xFBDC, 0x92FF, 0xFBDD, 0x931D, 0xFBDE, 0x9302, 0xFBDF, 0x9370,	0xFBE0, 0x9357, 0xFBE1, 0x93A4, 0xFBE2, 0x93C6, 0xFBE3, 0x93DE,
+	0xFBE4, 0x93F8, 0xFBE5, 0x9431, 0xFBE6, 0x9445, 0xFBE7, 0x9448,	0xFBE8, 0x9592, 0xFBE9, 0xF9DC, 0xFBEA, 0xFA29, 0xFBEB, 0x969D,
+	0xFBEC, 0x96AF, 0xFBED, 0x9733, 0xFBEE, 0x973B, 0xFBEF, 0x9743,	0xFBF0, 0x974D, 0xFBF1, 0x974F, 0xFBF2, 0x9751, 0xFBF3, 0x9755,
+	0xFBF4, 0x9857, 0xFBF5, 0x9865, 0xFBF6, 0xFA2A, 0xFBF7, 0xFA2B,	0xFBF8, 0x9927, 0xFBF9, 0xFA2C, 0xFBFA, 0x999E, 0xFBFB, 0x9A4E,
+	0xFBFC, 0x9AD9, 0xFC40, 0x9ADC, 0xFC41, 0x9B75, 0xFC42, 0x9B72,	0xFC43, 0x9B8F, 0xFC44, 0x9BB1, 0xFC45, 0x9BBB, 0xFC46, 0x9C00,
+	0xFC47, 0x9D70, 0xFC48, 0x9D6B, 0xFC49, 0xFA2D, 0xFC4A, 0x9E19,	0xFC4B, 0x9ED1, 0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 936 || FF_CODE_PAGE == 0	/* Simplified Chinese */
+static const WCHAR uni2oem936[] = {	/* Unicode --> GBK pairs */
+	0x00A4, 0xA1E8, 0x00A7, 0xA1EC, 0x00A8, 0xA1A7, 0x00B0, 0xA1E3,	0x00B1, 0xA1C0, 0x00B7, 0xA1A4, 0x00D7, 0xA1C1, 0x00E0, 0xA8A4,
+	0x00E1, 0xA8A2, 0x00E8, 0xA8A8, 0x00E9, 0xA8A6, 0x00EA, 0xA8BA,	0x00EC, 0xA8AC, 0x00ED, 0xA8AA, 0x00F2, 0xA8B0, 0x00F3, 0xA8AE,
+	0x00F7, 0xA1C2, 0x00F9, 0xA8B4, 0x00FA, 0xA8B2, 0x00FC, 0xA8B9,	0x0101, 0xA8A1, 0x0113, 0xA8A5, 0x011B, 0xA8A7, 0x012B, 0xA8A9,
+	0x0144, 0xA8BD, 0x0148, 0xA8BE, 0x014D, 0xA8AD, 0x016B, 0xA8B1,	0x01CE, 0xA8A3, 0x01D0, 0xA8AB, 0x01D2, 0xA8AF, 0x01D4, 0xA8B3,
+	0x01D6, 0xA8B5, 0x01D8, 0xA8B6, 0x01DA, 0xA8B7, 0x01DC, 0xA8B8,	0x0251, 0xA8BB, 0x0261, 0xA8C0, 0x02C7, 0xA1A6, 0x02C9, 0xA1A5,
+	0x02CA, 0xA840, 0x02CB, 0xA841, 0x02D9, 0xA842, 0x0391, 0xA6A1,	0x0392, 0xA6A2, 0x0393, 0xA6A3, 0x0394, 0xA6A4, 0x0395, 0xA6A5,
+	0x0396, 0xA6A6, 0x0397, 0xA6A7, 0x0398, 0xA6A8, 0x0399, 0xA6A9,	0x039A, 0xA6AA, 0x039B, 0xA6AB, 0x039C, 0xA6AC, 0x039D, 0xA6AD,
+	0x039E, 0xA6AE, 0x039F, 0xA6AF, 0x03A0, 0xA6B0, 0x03A1, 0xA6B1,	0x03A3, 0xA6B2, 0x03A4, 0xA6B3, 0x03A5, 0xA6B4, 0x03A6, 0xA6B5,
+	0x03A7, 0xA6B6, 0x03A8, 0xA6B7, 0x03A9, 0xA6B8, 0x03B1, 0xA6C1,	0x03B2, 0xA6C2, 0x03B3, 0xA6C3, 0x03B4, 0xA6C4, 0x03B5, 0xA6C5,
+	0x03B6, 0xA6C6, 0x03B7, 0xA6C7, 0x03B8, 0xA6C8, 0x03B9, 0xA6C9,	0x03BA, 0xA6CA, 0x03BB, 0xA6CB, 0x03BC, 0xA6CC, 0x03BD, 0xA6CD,
+	0x03BE, 0xA6CE, 0x03BF, 0xA6CF, 0x03C0, 0xA6D0, 0x03C1, 0xA6D1,	0x03C3, 0xA6D2, 0x03C4, 0xA6D3, 0x03C5, 0xA6D4, 0x03C6, 0xA6D5,
+	0x03C7, 0xA6D6, 0x03C8, 0xA6D7, 0x03C9, 0xA6D8, 0x0401, 0xA7A7,	0x0410, 0xA7A1, 0x0411, 0xA7A2, 0x0412, 0xA7A3, 0x0413, 0xA7A4,
+	0x0414, 0xA7A5, 0x0415, 0xA7A6, 0x0416, 0xA7A8, 0x0417, 0xA7A9,	0x0418, 0xA7AA, 0x0419, 0xA7AB, 0x041A, 0xA7AC, 0x041B, 0xA7AD,
+	0x041C, 0xA7AE, 0x041D, 0xA7AF, 0x041E, 0xA7B0, 0x041F, 0xA7B1,	0x0420, 0xA7B2, 0x0421, 0xA7B3, 0x0422, 0xA7B4, 0x0423, 0xA7B5,
+	0x0424, 0xA7B6, 0x0425, 0xA7B7, 0x0426, 0xA7B8, 0x0427, 0xA7B9,	0x0428, 0xA7BA, 0x0429, 0xA7BB, 0x042A, 0xA7BC, 0x042B, 0xA7BD,
+	0x042C, 0xA7BE, 0x042D, 0xA7BF, 0x042E, 0xA7C0, 0x042F, 0xA7C1,	0x0430, 0xA7D1, 0x0431, 0xA7D2, 0x0432, 0xA7D3, 0x0433, 0xA7D4,
+	0x0434, 0xA7D5, 0x0435, 0xA7D6, 0x0436, 0xA7D8, 0x0437, 0xA7D9,	0x0438, 0xA7DA, 0x0439, 0xA7DB, 0x043A, 0xA7DC, 0x043B, 0xA7DD,
+	0x043C, 0xA7DE, 0x043D, 0xA7DF, 0x043E, 0xA7E0, 0x043F, 0xA7E1,	0x0440, 0xA7E2, 0x0441, 0xA7E3, 0x0442, 0xA7E4, 0x0443, 0xA7E5,
+	0x0444, 0xA7E6, 0x0445, 0xA7E7, 0x0446, 0xA7E8, 0x0447, 0xA7E9,	0x0448, 0xA7EA, 0x0449, 0xA7EB, 0x044A, 0xA7EC, 0x044B, 0xA7ED,
+	0x044C, 0xA7EE, 0x044D, 0xA7EF, 0x044E, 0xA7F0, 0x044F, 0xA7F1,	0x0451, 0xA7D7, 0x2010, 0xA95C, 0x2013, 0xA843, 0x2014, 0xA1AA,
+	0x2015, 0xA844, 0x2016, 0xA1AC, 0x2018, 0xA1AE, 0x2019, 0xA1AF,	0x201C, 0xA1B0, 0x201D, 0xA1B1, 0x2025, 0xA845, 0x2026, 0xA1AD,
+	0x2030, 0xA1EB, 0x2032, 0xA1E4, 0x2033, 0xA1E5, 0x2035, 0xA846,	0x203B, 0xA1F9, 0x20AC, 0x0080, 0x2103, 0xA1E6, 0x2105, 0xA847,
+	0x2109, 0xA848, 0x2116, 0xA1ED, 0x2121, 0xA959, 0x2160, 0xA2F1,	0x2161, 0xA2F2, 0x2162, 0xA2F3, 0x2163, 0xA2F4, 0x2164, 0xA2F5,
+	0x2165, 0xA2F6, 0x2166, 0xA2F7, 0x2167, 0xA2F8, 0x2168, 0xA2F9,	0x2169, 0xA2FA, 0x216A, 0xA2FB, 0x216B, 0xA2FC, 0x2170, 0xA2A1,
+	0x2171, 0xA2A2, 0x2172, 0xA2A3, 0x2173, 0xA2A4, 0x2174, 0xA2A5,	0x2175, 0xA2A6, 0x2176, 0xA2A7, 0x2177, 0xA2A8, 0x2178, 0xA2A9,
+	0x2179, 0xA2AA, 0x2190, 0xA1FB, 0x2191, 0xA1FC, 0x2192, 0xA1FA,	0x2193, 0xA1FD, 0x2196, 0xA849, 0x2197, 0xA84A, 0x2198, 0xA84B,
+	0x2199, 0xA84C, 0x2208, 0xA1CA, 0x220F, 0xA1C7, 0x2211, 0xA1C6,	0x2215, 0xA84D, 0x221A, 0xA1CC, 0x221D, 0xA1D8, 0x221E, 0xA1DE,
+	0x221F, 0xA84E, 0x2220, 0xA1CF, 0x2223, 0xA84F, 0x2225, 0xA1CE,	0x2227, 0xA1C4, 0x2228, 0xA1C5, 0x2229, 0xA1C9, 0x222A, 0xA1C8,
+	0x222B, 0xA1D2, 0x222E, 0xA1D3, 0x2234, 0xA1E0, 0x2235, 0xA1DF,	0x2236, 0xA1C3, 0x2237, 0xA1CB, 0x223D, 0xA1D7, 0x2248, 0xA1D6,
+	0x224C, 0xA1D5, 0x2252, 0xA850, 0x2260, 0xA1D9, 0x2261, 0xA1D4,	0x2264, 0xA1DC, 0x2265, 0xA1DD, 0x2266, 0xA851, 0x2267, 0xA852,
+	0x226E, 0xA1DA, 0x226F, 0xA1DB, 0x2295, 0xA892, 0x2299, 0xA1D1,	0x22A5, 0xA1CD, 0x22BF, 0xA853, 0x2312, 0xA1D0, 0x2460, 0xA2D9,
+	0x2461, 0xA2DA, 0x2462, 0xA2DB, 0x2463, 0xA2DC, 0x2464, 0xA2DD,	0x2465, 0xA2DE, 0x2466, 0xA2DF, 0x2467, 0xA2E0, 0x2468, 0xA2E1,
+	0x2469, 0xA2E2, 0x2474, 0xA2C5, 0x2475, 0xA2C6, 0x2476, 0xA2C7,	0x2477, 0xA2C8, 0x2478, 0xA2C9, 0x2479, 0xA2CA, 0x247A, 0xA2CB,
+	0x247B, 0xA2CC, 0x247C, 0xA2CD, 0x247D, 0xA2CE, 0x247E, 0xA2CF,	0x247F, 0xA2D0, 0x2480, 0xA2D1, 0x2481, 0xA2D2, 0x2482, 0xA2D3,
+	0x2483, 0xA2D4, 0x2484, 0xA2D5, 0x2485, 0xA2D6, 0x2486, 0xA2D7,	0x2487, 0xA2D8, 0x2488, 0xA2B1, 0x2489, 0xA2B2, 0x248A, 0xA2B3,
+	0x248B, 0xA2B4, 0x248C, 0xA2B5, 0x248D, 0xA2B6, 0x248E, 0xA2B7,	0x248F, 0xA2B8, 0x2490, 0xA2B9, 0x2491, 0xA2BA, 0x2492, 0xA2BB,
+	0x2493, 0xA2BC, 0x2494, 0xA2BD, 0x2495, 0xA2BE, 0x2496, 0xA2BF,	0x2497, 0xA2C0, 0x2498, 0xA2C1, 0x2499, 0xA2C2, 0x249A, 0xA2C3,
+	0x249B, 0xA2C4, 0x2500, 0xA9A4, 0x2501, 0xA9A5, 0x2502, 0xA9A6,	0x2503, 0xA9A7, 0x2504, 0xA9A8, 0x2505, 0xA9A9, 0x2506, 0xA9AA,
+	0x2507, 0xA9AB, 0x2508, 0xA9AC, 0x2509, 0xA9AD, 0x250A, 0xA9AE,	0x250B, 0xA9AF, 0x250C, 0xA9B0, 0x250D, 0xA9B1, 0x250E, 0xA9B2,
+	0x250F, 0xA9B3, 0x2510, 0xA9B4, 0x2511, 0xA9B5, 0x2512, 0xA9B6,	0x2513, 0xA9B7, 0x2514, 0xA9B8, 0x2515, 0xA9B9, 0x2516, 0xA9BA,
+	0x2517, 0xA9BB, 0x2518, 0xA9BC, 0x2519, 0xA9BD, 0x251A, 0xA9BE,	0x251B, 0xA9BF, 0x251C, 0xA9C0, 0x251D, 0xA9C1, 0x251E, 0xA9C2,
+	0x251F, 0xA9C3, 0x2520, 0xA9C4, 0x2521, 0xA9C5, 0x2522, 0xA9C6,	0x2523, 0xA9C7, 0x2524, 0xA9C8, 0x2525, 0xA9C9, 0x2526, 0xA9CA,
+	0x2527, 0xA9CB, 0x2528, 0xA9CC, 0x2529, 0xA9CD, 0x252A, 0xA9CE,	0x252B, 0xA9CF, 0x252C, 0xA9D0, 0x252D, 0xA9D1, 0x252E, 0xA9D2,
+	0x252F, 0xA9D3, 0x2530, 0xA9D4, 0x2531, 0xA9D5, 0x2532, 0xA9D6,	0x2533, 0xA9D7, 0x2534, 0xA9D8, 0x2535, 0xA9D9, 0x2536, 0xA9DA,
+	0x2537, 0xA9DB, 0x2538, 0xA9DC, 0x2539, 0xA9DD, 0x253A, 0xA9DE,	0x253B, 0xA9DF, 0x253C, 0xA9E0, 0x253D, 0xA9E1, 0x253E, 0xA9E2,
+	0x253F, 0xA9E3, 0x2540, 0xA9E4, 0x2541, 0xA9E5, 0x2542, 0xA9E6,	0x2543, 0xA9E7, 0x2544, 0xA9E8, 0x2545, 0xA9E9, 0x2546, 0xA9EA,
+	0x2547, 0xA9EB, 0x2548, 0xA9EC, 0x2549, 0xA9ED, 0x254A, 0xA9EE,	0x254B, 0xA9EF, 0x2550, 0xA854, 0x2551, 0xA855, 0x2552, 0xA856,
+	0x2553, 0xA857, 0x2554, 0xA858, 0x2555, 0xA859, 0x2556, 0xA85A,	0x2557, 0xA85B, 0x2558, 0xA85C, 0x2559, 0xA85D, 0x255A, 0xA85E,
+	0x255B, 0xA85F, 0x255C, 0xA860, 0x255D, 0xA861, 0x255E, 0xA862,	0x255F, 0xA863, 0x2560, 0xA864, 0x2561, 0xA865, 0x2562, 0xA866,
+	0x2563, 0xA867, 0x2564, 0xA868, 0x2565, 0xA869, 0x2566, 0xA86A,	0x2567, 0xA86B, 0x2568, 0xA86C, 0x2569, 0xA86D, 0x256A, 0xA86E,
+	0x256B, 0xA86F, 0x256C, 0xA870, 0x256D, 0xA871, 0x256E, 0xA872,	0x256F, 0xA873, 0x2570, 0xA874, 0x2571, 0xA875, 0x2572, 0xA876,
+	0x2573, 0xA877, 0x2581, 0xA878, 0x2582, 0xA879, 0x2583, 0xA87A,	0x2584, 0xA87B, 0x2585, 0xA87C, 0x2586, 0xA87D, 0x2587, 0xA87E,
+	0x2588, 0xA880, 0x2589, 0xA881, 0x258A, 0xA882, 0x258B, 0xA883,	0x258C, 0xA884, 0x258D, 0xA885, 0x258E, 0xA886, 0x258F, 0xA887,
+	0x2593, 0xA888, 0x2594, 0xA889, 0x2595, 0xA88A, 0x25A0, 0xA1F6,	0x25A1, 0xA1F5, 0x25B2, 0xA1F8, 0x25B3, 0xA1F7, 0x25BC, 0xA88B,
+	0x25BD, 0xA88C, 0x25C6, 0xA1F4, 0x25C7, 0xA1F3, 0x25CB, 0xA1F0,	0x25CE, 0xA1F2, 0x25CF, 0xA1F1, 0x25E2, 0xA88D, 0x25E3, 0xA88E,
+	0x25E4, 0xA88F, 0x25E5, 0xA890, 0x2605, 0xA1EF, 0x2606, 0xA1EE,	0x2609, 0xA891, 0x2640, 0xA1E2, 0x2642, 0xA1E1, 0x3000, 0xA1A1,
+	0x3001, 0xA1A2, 0x3002, 0xA1A3, 0x3003, 0xA1A8, 0x3005, 0xA1A9,	0x3006, 0xA965, 0x3007, 0xA996, 0x3008, 0xA1B4, 0x3009, 0xA1B5,
+	0x300A, 0xA1B6, 0x300B, 0xA1B7, 0x300C, 0xA1B8, 0x300D, 0xA1B9,	0x300E, 0xA1BA, 0x300F, 0xA1BB, 0x3010, 0xA1BE, 0x3011, 0xA1BF,
+	0x3012, 0xA893, 0x3013, 0xA1FE, 0x3014, 0xA1B2, 0x3015, 0xA1B3,	0x3016, 0xA1BC, 0x3017, 0xA1BD, 0x301D, 0xA894, 0x301E, 0xA895,
+	0x3021, 0xA940, 0x3022, 0xA941, 0x3023, 0xA942, 0x3024, 0xA943,	0x3025, 0xA944, 0x3026, 0xA945, 0x3027, 0xA946, 0x3028, 0xA947,
+	0x3029, 0xA948, 0x3041, 0xA4A1, 0x3042, 0xA4A2, 0x3043, 0xA4A3,	0x3044, 0xA4A4, 0x3045, 0xA4A5, 0x3046, 0xA4A6, 0x3047, 0xA4A7,
+	0x3048, 0xA4A8, 0x3049, 0xA4A9, 0x304A, 0xA4AA, 0x304B, 0xA4AB,	0x304C, 0xA4AC, 0x304D, 0xA4AD, 0x304E, 0xA4AE, 0x304F, 0xA4AF,
+	0x3050, 0xA4B0, 0x3051, 0xA4B1, 0x3052, 0xA4B2, 0x3053, 0xA4B3,	0x3054, 0xA4B4, 0x3055, 0xA4B5, 0x3056, 0xA4B6, 0x3057, 0xA4B7,
+	0x3058, 0xA4B8, 0x3059, 0xA4B9, 0x305A, 0xA4BA, 0x305B, 0xA4BB,	0x305C, 0xA4BC, 0x305D, 0xA4BD, 0x305E, 0xA4BE, 0x305F, 0xA4BF,
+	0x3060, 0xA4C0, 0x3061, 0xA4C1, 0x3062, 0xA4C2, 0x3063, 0xA4C3,	0x3064, 0xA4C4, 0x3065, 0xA4C5, 0x3066, 0xA4C6, 0x3067, 0xA4C7,
+	0x3068, 0xA4C8, 0x3069, 0xA4C9, 0x306A, 0xA4CA, 0x306B, 0xA4CB,	0x306C, 0xA4CC, 0x306D, 0xA4CD, 0x306E, 0xA4CE, 0x306F, 0xA4CF,
+	0x3070, 0xA4D0, 0x3071, 0xA4D1, 0x3072, 0xA4D2, 0x3073, 0xA4D3,	0x3074, 0xA4D4, 0x3075, 0xA4D5, 0x3076, 0xA4D6, 0x3077, 0xA4D7,
+	0x3078, 0xA4D8, 0x3079, 0xA4D9, 0x307A, 0xA4DA, 0x307B, 0xA4DB,	0x307C, 0xA4DC, 0x307D, 0xA4DD, 0x307E, 0xA4DE, 0x307F, 0xA4DF,
+	0x3080, 0xA4E0, 0x3081, 0xA4E1, 0x3082, 0xA4E2, 0x3083, 0xA4E3,	0x3084, 0xA4E4, 0x3085, 0xA4E5, 0x3086, 0xA4E6, 0x3087, 0xA4E7,
+	0x3088, 0xA4E8, 0x3089, 0xA4E9, 0x308A, 0xA4EA, 0x308B, 0xA4EB,	0x308C, 0xA4EC, 0x308D, 0xA4ED, 0x308E, 0xA4EE, 0x308F, 0xA4EF,
+	0x3090, 0xA4F0, 0x3091, 0xA4F1, 0x3092, 0xA4F2, 0x3093, 0xA4F3,	0x309B, 0xA961, 0x309C, 0xA962, 0x309D, 0xA966, 0x309E, 0xA967,
+	0x30A1, 0xA5A1, 0x30A2, 0xA5A2, 0x30A3, 0xA5A3, 0x30A4, 0xA5A4,	0x30A5, 0xA5A5, 0x30A6, 0xA5A6, 0x30A7, 0xA5A7, 0x30A8, 0xA5A8,
+	0x30A9, 0xA5A9, 0x30AA, 0xA5AA, 0x30AB, 0xA5AB, 0x30AC, 0xA5AC,	0x30AD, 0xA5AD, 0x30AE, 0xA5AE, 0x30AF, 0xA5AF, 0x30B0, 0xA5B0,
+	0x30B1, 0xA5B1, 0x30B2, 0xA5B2, 0x30B3, 0xA5B3, 0x30B4, 0xA5B4,	0x30B5, 0xA5B5, 0x30B6, 0xA5B6, 0x30B7, 0xA5B7, 0x30B8, 0xA5B8,
+	0x30B9, 0xA5B9, 0x30BA, 0xA5BA, 0x30BB, 0xA5BB, 0x30BC, 0xA5BC,	0x30BD, 0xA5BD, 0x30BE, 0xA5BE, 0x30BF, 0xA5BF, 0x30C0, 0xA5C0,
+	0x30C1, 0xA5C1, 0x30C2, 0xA5C2, 0x30C3, 0xA5C3, 0x30C4, 0xA5C4,	0x30C5, 0xA5C5, 0x30C6, 0xA5C6, 0x30C7, 0xA5C7, 0x30C8, 0xA5C8,
+	0x30C9, 0xA5C9, 0x30CA, 0xA5CA, 0x30CB, 0xA5CB, 0x30CC, 0xA5CC,	0x30CD, 0xA5CD, 0x30CE, 0xA5CE, 0x30CF, 0xA5CF, 0x30D0, 0xA5D0,
+	0x30D1, 0xA5D1, 0x30D2, 0xA5D2, 0x30D3, 0xA5D3, 0x30D4, 0xA5D4,	0x30D5, 0xA5D5, 0x30D6, 0xA5D6, 0x30D7, 0xA5D7, 0x30D8, 0xA5D8,
+	0x30D9, 0xA5D9, 0x30DA, 0xA5DA, 0x30DB, 0xA5DB, 0x30DC, 0xA5DC,	0x30DD, 0xA5DD, 0x30DE, 0xA5DE, 0x30DF, 0xA5DF, 0x30E0, 0xA5E0,
+	0x30E1, 0xA5E1, 0x30E2, 0xA5E2, 0x30E3, 0xA5E3, 0x30E4, 0xA5E4,	0x30E5, 0xA5E5, 0x30E6, 0xA5E6, 0x30E7, 0xA5E7, 0x30E8, 0xA5E8,
+	0x30E9, 0xA5E9, 0x30EA, 0xA5EA, 0x30EB, 0xA5EB, 0x30EC, 0xA5EC,	0x30ED, 0xA5ED, 0x30EE, 0xA5EE, 0x30EF, 0xA5EF, 0x30F0, 0xA5F0,
+	0x30F1, 0xA5F1, 0x30F2, 0xA5F2, 0x30F3, 0xA5F3, 0x30F4, 0xA5F4,	0x30F5, 0xA5F5, 0x30F6, 0xA5F6, 0x30FC, 0xA960, 0x30FD, 0xA963,
+	0x30FE, 0xA964, 0x3105, 0xA8C5, 0x3106, 0xA8C6, 0x3107, 0xA8C7,	0x3108, 0xA8C8, 0x3109, 0xA8C9, 0x310A, 0xA8CA, 0x310B, 0xA8CB,
+	0x310C, 0xA8CC, 0x310D, 0xA8CD, 0x310E, 0xA8CE, 0x310F, 0xA8CF,	0x3110, 0xA8D0, 0x3111, 0xA8D1, 0x3112, 0xA8D2, 0x3113, 0xA8D3,
+	0x3114, 0xA8D4, 0x3115, 0xA8D5, 0x3116, 0xA8D6, 0x3117, 0xA8D7,	0x3118, 0xA8D8, 0x3119, 0xA8D9, 0x311A, 0xA8DA, 0x311B, 0xA8DB,
+	0x311C, 0xA8DC, 0x311D, 0xA8DD, 0x311E, 0xA8DE, 0x311F, 0xA8DF,	0x3120, 0xA8E0, 0x3121, 0xA8E1, 0x3122, 0xA8E2, 0x3123, 0xA8E3,
+	0x3124, 0xA8E4, 0x3125, 0xA8E5, 0x3126, 0xA8E6, 0x3127, 0xA8E7,	0x3128, 0xA8E8, 0x3129, 0xA8E9, 0x3220, 0xA2E5, 0x3221, 0xA2E6,
+	0x3222, 0xA2E7, 0x3223, 0xA2E8, 0x3224, 0xA2E9, 0x3225, 0xA2EA,	0x3226, 0xA2EB, 0x3227, 0xA2EC, 0x3228, 0xA2ED, 0x3229, 0xA2EE,
+	0x3231, 0xA95A, 0x32A3, 0xA949, 0x338E, 0xA94A, 0x338F, 0xA94B,	0x339C, 0xA94C, 0x339D, 0xA94D, 0x339E, 0xA94E, 0x33A1, 0xA94F,
+	0x33C4, 0xA950, 0x33CE, 0xA951, 0x33D1, 0xA952, 0x33D2, 0xA953,	0x33D5, 0xA954, 0x4E00, 0xD2BB, 0x4E01, 0xB6A1, 0x4E02, 0x8140,
+	0x4E03, 0xC6DF, 0x4E04, 0x8141, 0x4E05, 0x8142, 0x4E06, 0x8143,	0x4E07, 0xCDF2, 0x4E08, 0xD5C9, 0x4E09, 0xC8FD, 0x4E0A, 0xC9CF,
+	0x4E0B, 0xCFC2, 0x4E0C, 0xD8A2, 0x4E0D, 0xB2BB, 0x4E0E, 0xD3EB,	0x4E0F, 0x8144, 0x4E10, 0xD8A4, 0x4E11, 0xB3F3, 0x4E12, 0x8145,
+	0x4E13, 0xD7A8, 0x4E14, 0xC7D2, 0x4E15, 0xD8A7, 0x4E16, 0xCAC0,	0x4E17, 0x8146, 0x4E18, 0xC7F0, 0x4E19, 0xB1FB, 0x4E1A, 0xD2B5,
+	0x4E1B, 0xB4D4, 0x4E1C, 0xB6AB, 0x4E1D, 0xCBBF, 0x4E1E, 0xD8A9,	0x4E1F, 0x8147, 0x4E20, 0x8148, 0x4E21, 0x8149, 0x4E22, 0xB6AA,
+	0x4E23, 0x814A, 0x4E24, 0xC1BD, 0x4E25, 0xD1CF, 0x4E26, 0x814B,	0x4E27, 0xC9A5, 0x4E28, 0xD8AD, 0x4E29, 0x814C, 0x4E2A, 0xB8F6,
+	0x4E2B, 0xD1BE, 0x4E2C, 0xE3DC, 0x4E2D, 0xD6D0, 0x4E2E, 0x814D,	0x4E2F, 0x814E, 0x4E30, 0xB7E1, 0x4E31, 0x814F, 0x4E32, 0xB4AE,
+	0x4E33, 0x8150, 0x4E34, 0xC1D9, 0x4E35, 0x8151, 0x4E36, 0xD8BC,	0x4E37, 0x8152, 0x4E38, 0xCDE8, 0x4E39, 0xB5A4, 0x4E3A, 0xCEAA,
+	0x4E3B, 0xD6F7, 0x4E3C, 0x8153, 0x4E3D, 0xC0F6, 0x4E3E, 0xBED9,	0x4E3F, 0xD8AF, 0x4E40, 0x8154, 0x4E41, 0x8155, 0x4E42, 0x8156,
+	0x4E43, 0xC4CB, 0x4E44, 0x8157, 0x4E45, 0xBEC3, 0x4E46, 0x8158,	0x4E47, 0xD8B1, 0x4E48, 0xC3B4, 0x4E49, 0xD2E5, 0x4E4A, 0x8159,
+	0x4E4B, 0xD6AE, 0x4E4C, 0xCEDA, 0x4E4D, 0xD5A7, 0x4E4E, 0xBAF5,	0x4E4F, 0xB7A6, 0x4E50, 0xC0D6, 0x4E51, 0x815A, 0x4E52, 0xC6B9,
+	0x4E53, 0xC5D2, 0x4E54, 0xC7C7, 0x4E55, 0x815B, 0x4E56, 0xB9D4,	0x4E57, 0x815C, 0x4E58, 0xB3CB, 0x4E59, 0xD2D2, 0x4E5A, 0x815D,
+	0x4E5B, 0x815E, 0x4E5C, 0xD8BF, 0x4E5D, 0xBEC5, 0x4E5E, 0xC6F2,	0x4E5F, 0xD2B2, 0x4E60, 0xCFB0, 0x4E61, 0xCFE7, 0x4E62, 0x815F,
+	0x4E63, 0x8160, 0x4E64, 0x8161, 0x4E65, 0x8162, 0x4E66, 0xCAE9,	0x4E67, 0x8163, 0x4E68, 0x8164, 0x4E69, 0xD8C0, 0x4E6A, 0x8165,
+	0x4E6B, 0x8166, 0x4E6C, 0x8167, 0x4E6D, 0x8168, 0x4E6E, 0x8169,	0x4E6F, 0x816A, 0x4E70, 0xC2F2, 0x4E71, 0xC2D2, 0x4E72, 0x816B,
+	0x4E73, 0xC8E9, 0x4E74, 0x816C, 0x4E75, 0x816D, 0x4E76, 0x816E,	0x4E77, 0x816F, 0x4E78, 0x8170, 0x4E79, 0x8171, 0x4E7A, 0x8172,
+	0x4E7B, 0x8173, 0x4E7C, 0x8174, 0x4E7D, 0x8175, 0x4E7E, 0xC7AC,	0x4E7F, 0x8176, 0x4E80, 0x8177, 0x4E81, 0x8178, 0x4E82, 0x8179,
+	0x4E83, 0x817A, 0x4E84, 0x817B, 0x4E85, 0x817C, 0x4E86, 0xC1CB,	0x4E87, 0x817D, 0x4E88, 0xD3E8, 0x4E89, 0xD5F9, 0x4E8A, 0x817E,
+	0x4E8B, 0xCAC2, 0x4E8C, 0xB6FE, 0x4E8D, 0xD8A1, 0x4E8E, 0xD3DA,	0x4E8F, 0xBFF7, 0x4E90, 0x8180, 0x4E91, 0xD4C6, 0x4E92, 0xBBA5,
+	0x4E93, 0xD8C1, 0x4E94, 0xCEE5, 0x4E95, 0xBEAE, 0x4E96, 0x8181,	0x4E97, 0x8182, 0x4E98, 0xD8A8, 0x4E99, 0x8183, 0x4E9A, 0xD1C7,
+	0x4E9B, 0xD0A9, 0x4E9C, 0x8184, 0x4E9D, 0x8185, 0x4E9E, 0x8186,	0x4E9F, 0xD8BD, 0x4EA0, 0xD9EF, 0x4EA1, 0xCDF6, 0x4EA2, 0xBFBA,
+	0x4EA3, 0x8187, 0x4EA4, 0xBDBB, 0x4EA5, 0xBAA5, 0x4EA6, 0xD2E0,	0x4EA7, 0xB2FA, 0x4EA8, 0xBAE0, 0x4EA9, 0xC4B6, 0x4EAA, 0x8188,
+	0x4EAB, 0xCFED, 0x4EAC, 0xBEA9, 0x4EAD, 0xCDA4, 0x4EAE, 0xC1C1,	0x4EAF, 0x8189, 0x4EB0, 0x818A, 0x4EB1, 0x818B, 0x4EB2, 0xC7D7,
+	0x4EB3, 0xD9F1, 0x4EB4, 0x818C, 0x4EB5, 0xD9F4, 0x4EB6, 0x818D,	0x4EB7, 0x818E, 0x4EB8, 0x818F, 0x4EB9, 0x8190, 0x4EBA, 0xC8CB,
+	0x4EBB, 0xD8E9, 0x4EBC, 0x8191, 0x4EBD, 0x8192, 0x4EBE, 0x8193,	0x4EBF, 0xD2DA, 0x4EC0, 0xCAB2, 0x4EC1, 0xC8CA, 0x4EC2, 0xD8EC,
+	0x4EC3, 0xD8EA, 0x4EC4, 0xD8C6, 0x4EC5, 0xBDF6, 0x4EC6, 0xC6CD,	0x4EC7, 0xB3F0, 0x4EC8, 0x8194, 0x4EC9, 0xD8EB, 0x4ECA, 0xBDF1,
+	0x4ECB, 0xBDE9, 0x4ECC, 0x8195, 0x4ECD, 0xC8D4, 0x4ECE, 0xB4D3,	0x4ECF, 0x8196, 0x4ED0, 0x8197, 0x4ED1, 0xC2D8, 0x4ED2, 0x8198,
+	0x4ED3, 0xB2D6, 0x4ED4, 0xD7D0, 0x4ED5, 0xCACB, 0x4ED6, 0xCBFB,	0x4ED7, 0xD5CC, 0x4ED8, 0xB8B6, 0x4ED9, 0xCFC9, 0x4EDA, 0x8199,
+	0x4EDB, 0x819A, 0x4EDC, 0x819B, 0x4EDD, 0xD9DA, 0x4EDE, 0xD8F0,	0x4EDF, 0xC7AA, 0x4EE0, 0x819C, 0x4EE1, 0xD8EE, 0x4EE2, 0x819D,
+	0x4EE3, 0xB4FA, 0x4EE4, 0xC1EE, 0x4EE5, 0xD2D4, 0x4EE6, 0x819E,	0x4EE7, 0x819F, 0x4EE8, 0xD8ED, 0x4EE9, 0x81A0, 0x4EEA, 0xD2C7,
+	0x4EEB, 0xD8EF, 0x4EEC, 0xC3C7, 0x4EED, 0x81A1, 0x4EEE, 0x81A2,	0x4EEF, 0x81A3, 0x4EF0, 0xD1F6, 0x4EF1, 0x81A4, 0x4EF2, 0xD6D9,
+	0x4EF3, 0xD8F2, 0x4EF4, 0x81A5, 0x4EF5, 0xD8F5, 0x4EF6, 0xBCFE,	0x4EF7, 0xBCDB, 0x4EF8, 0x81A6, 0x4EF9, 0x81A7, 0x4EFA, 0x81A8,
+	0x4EFB, 0xC8CE, 0x4EFC, 0x81A9, 0x4EFD, 0xB7DD, 0x4EFE, 0x81AA,	0x4EFF, 0xB7C2, 0x4F00, 0x81AB, 0x4F01, 0xC6F3, 0x4F02, 0x81AC,
+	0x4F03, 0x81AD, 0x4F04, 0x81AE, 0x4F05, 0x81AF, 0x4F06, 0x81B0,	0x4F07, 0x81B1, 0x4F08, 0x81B2, 0x4F09, 0xD8F8, 0x4F0A, 0xD2C1,
+	0x4F0B, 0x81B3, 0x4F0C, 0x81B4, 0x4F0D, 0xCEE9, 0x4F0E, 0xBCBF,	0x4F0F, 0xB7FC, 0x4F10, 0xB7A5, 0x4F11, 0xD0DD, 0x4F12, 0x81B5,
+	0x4F13, 0x81B6, 0x4F14, 0x81B7, 0x4F15, 0x81B8, 0x4F16, 0x81B9,	0x4F17, 0xD6DA, 0x4F18, 0xD3C5, 0x4F19, 0xBBEF, 0x4F1A, 0xBBE1,
+	0x4F1B, 0xD8F1, 0x4F1C, 0x81BA, 0x4F1D, 0x81BB, 0x4F1E, 0xC9A1,	0x4F1F, 0xCEB0, 0x4F20, 0xB4AB, 0x4F21, 0x81BC, 0x4F22, 0xD8F3,
+	0x4F23, 0x81BD, 0x4F24, 0xC9CB, 0x4F25, 0xD8F6, 0x4F26, 0xC2D7,	0x4F27, 0xD8F7, 0x4F28, 0x81BE, 0x4F29, 0x81BF, 0x4F2A, 0xCEB1,
+	0x4F2B, 0xD8F9, 0x4F2C, 0x81C0, 0x4F2D, 0x81C1, 0x4F2E, 0x81C2,	0x4F2F, 0xB2AE, 0x4F30, 0xB9C0, 0x4F31, 0x81C3, 0x4F32, 0xD9A3,
+	0x4F33, 0x81C4, 0x4F34, 0xB0E9, 0x4F35, 0x81C5, 0x4F36, 0xC1E6,	0x4F37, 0x81C6, 0x4F38, 0xC9EC, 0x4F39, 0x81C7, 0x4F3A, 0xCBC5,
+	0x4F3B, 0x81C8, 0x4F3C, 0xCBC6, 0x4F3D, 0xD9A4, 0x4F3E, 0x81C9,	0x4F3F, 0x81CA, 0x4F40, 0x81CB, 0x4F41, 0x81CC, 0x4F42, 0x81CD,
+	0x4F43, 0xB5E8, 0x4F44, 0x81CE, 0x4F45, 0x81CF, 0x4F46, 0xB5AB,	0x4F47, 0x81D0, 0x4F48, 0x81D1, 0x4F49, 0x81D2, 0x4F4A, 0x81D3,
+	0x4F4B, 0x81D4, 0x4F4C, 0x81D5, 0x4F4D, 0xCEBB, 0x4F4E, 0xB5CD,	0x4F4F, 0xD7A1, 0x4F50, 0xD7F4, 0x4F51, 0xD3D3, 0x4F52, 0x81D6,
+	0x4F53, 0xCCE5, 0x4F54, 0x81D7, 0x4F55, 0xBACE, 0x4F56, 0x81D8,	0x4F57, 0xD9A2, 0x4F58, 0xD9DC, 0x4F59, 0xD3E0, 0x4F5A, 0xD8FD,
+	0x4F5B, 0xB7F0, 0x4F5C, 0xD7F7, 0x4F5D, 0xD8FE, 0x4F5E, 0xD8FA,	0x4F5F, 0xD9A1, 0x4F60, 0xC4E3, 0x4F61, 0x81D9, 0x4F62, 0x81DA,
+	0x4F63, 0xD3B6, 0x4F64, 0xD8F4, 0x4F65, 0xD9DD, 0x4F66, 0x81DB,	0x4F67, 0xD8FB, 0x4F68, 0x81DC, 0x4F69, 0xC5E5, 0x4F6A, 0x81DD,
+	0x4F6B, 0x81DE, 0x4F6C, 0xC0D0, 0x4F6D, 0x81DF, 0x4F6E, 0x81E0,	0x4F6F, 0xD1F0, 0x4F70, 0xB0DB, 0x4F71, 0x81E1, 0x4F72, 0x81E2,
+	0x4F73, 0xBCD1, 0x4F74, 0xD9A6, 0x4F75, 0x81E3, 0x4F76, 0xD9A5,	0x4F77, 0x81E4, 0x4F78, 0x81E5, 0x4F79, 0x81E6, 0x4F7A, 0x81E7,
+	0x4F7B, 0xD9AC, 0x4F7C, 0xD9AE, 0x4F7D, 0x81E8, 0x4F7E, 0xD9AB,	0x4F7F, 0xCAB9, 0x4F80, 0x81E9, 0x4F81, 0x81EA, 0x4F82, 0x81EB,
+	0x4F83, 0xD9A9, 0x4F84, 0xD6B6, 0x4F85, 0x81EC, 0x4F86, 0x81ED,	0x4F87, 0x81EE, 0x4F88, 0xB3DE, 0x4F89, 0xD9A8, 0x4F8A, 0x81EF,
+	0x4F8B, 0xC0FD, 0x4F8C, 0x81F0, 0x4F8D, 0xCACC, 0x4F8E, 0x81F1,	0x4F8F, 0xD9AA, 0x4F90, 0x81F2, 0x4F91, 0xD9A7, 0x4F92, 0x81F3,
+	0x4F93, 0x81F4, 0x4F94, 0xD9B0, 0x4F95, 0x81F5, 0x4F96, 0x81F6,	0x4F97, 0xB6B1, 0x4F98, 0x81F7, 0x4F99, 0x81F8, 0x4F9A, 0x81F9,
+	0x4F9B, 0xB9A9, 0x4F9C, 0x81FA, 0x4F9D, 0xD2C0, 0x4F9E, 0x81FB,	0x4F9F, 0x81FC, 0x4FA0, 0xCFC0, 0x4FA1, 0x81FD, 0x4FA2, 0x81FE,
+	0x4FA3, 0xC2C2, 0x4FA4, 0x8240, 0x4FA5, 0xBDC4, 0x4FA6, 0xD5EC,	0x4FA7, 0xB2E0, 0x4FA8, 0xC7C8, 0x4FA9, 0xBFEB, 0x4FAA, 0xD9AD,
+	0x4FAB, 0x8241, 0x4FAC, 0xD9AF, 0x4FAD, 0x8242, 0x4FAE, 0xCEEA,	0x4FAF, 0xBAEE, 0x4FB0, 0x8243, 0x4FB1, 0x8244, 0x4FB2, 0x8245,
+	0x4FB3, 0x8246, 0x4FB4, 0x8247, 0x4FB5, 0xC7D6, 0x4FB6, 0x8248,	0x4FB7, 0x8249, 0x4FB8, 0x824A, 0x4FB9, 0x824B, 0x4FBA, 0x824C,
+	0x4FBB, 0x824D, 0x4FBC, 0x824E, 0x4FBD, 0x824F, 0x4FBE, 0x8250,	0x4FBF, 0xB1E3, 0x4FC0, 0x8251, 0x4FC1, 0x8252, 0x4FC2, 0x8253,
+	0x4FC3, 0xB4D9, 0x4FC4, 0xB6ED, 0x4FC5, 0xD9B4, 0x4FC6, 0x8254,	0x4FC7, 0x8255, 0x4FC8, 0x8256, 0x4FC9, 0x8257, 0x4FCA, 0xBFA1,
+	0x4FCB, 0x8258, 0x4FCC, 0x8259, 0x4FCD, 0x825A, 0x4FCE, 0xD9DE,	0x4FCF, 0xC7CE, 0x4FD0, 0xC0FE, 0x4FD1, 0xD9B8, 0x4FD2, 0x825B,
+	0x4FD3, 0x825C, 0x4FD4, 0x825D, 0x4FD5, 0x825E, 0x4FD6, 0x825F,	0x4FD7, 0xCBD7, 0x4FD8, 0xB7FD, 0x4FD9, 0x8260, 0x4FDA, 0xD9B5,
+	0x4FDB, 0x8261, 0x4FDC, 0xD9B7, 0x4FDD, 0xB1A3, 0x4FDE, 0xD3E1,	0x4FDF, 0xD9B9, 0x4FE0, 0x8262, 0x4FE1, 0xD0C5, 0x4FE2, 0x8263,
+	0x4FE3, 0xD9B6, 0x4FE4, 0x8264, 0x4FE5, 0x8265, 0x4FE6, 0xD9B1,	0x4FE7, 0x8266, 0x4FE8, 0xD9B2, 0x4FE9, 0xC1A9, 0x4FEA, 0xD9B3,
+	0x4FEB, 0x8267, 0x4FEC, 0x8268, 0x4FED, 0xBCF3, 0x4FEE, 0xD0DE,	0x4FEF, 0xB8A9, 0x4FF0, 0x8269, 0x4FF1, 0xBEE3, 0x4FF2, 0x826A,
+	0x4FF3, 0xD9BD, 0x4FF4, 0x826B, 0x4FF5, 0x826C, 0x4FF6, 0x826D,	0x4FF7, 0x826E, 0x4FF8, 0xD9BA, 0x4FF9, 0x826F, 0x4FFA, 0xB0B3,
+	0x4FFB, 0x8270, 0x4FFC, 0x8271, 0x4FFD, 0x8272, 0x4FFE, 0xD9C2,	0x4FFF, 0x8273, 0x5000, 0x8274, 0x5001, 0x8275, 0x5002, 0x8276,
+	0x5003, 0x8277, 0x5004, 0x8278, 0x5005, 0x8279, 0x5006, 0x827A,	0x5007, 0x827B, 0x5008, 0x827C, 0x5009, 0x827D, 0x500A, 0x827E,
+	0x500B, 0x8280, 0x500C, 0xD9C4, 0x500D, 0xB1B6, 0x500E, 0x8281,	0x500F, 0xD9BF, 0x5010, 0x8282, 0x5011, 0x8283, 0x5012, 0xB5B9,
+	0x5013, 0x8284, 0x5014, 0xBEF3, 0x5015, 0x8285, 0x5016, 0x8286,	0x5017, 0x8287, 0x5018, 0xCCC8, 0x5019, 0xBAF2, 0x501A, 0xD2D0,
+	0x501B, 0x8288, 0x501C, 0xD9C3, 0x501D, 0x8289, 0x501E, 0x828A,	0x501F, 0xBDE8, 0x5020, 0x828B, 0x5021, 0xB3AB, 0x5022, 0x828C,
+	0x5023, 0x828D, 0x5024, 0x828E, 0x5025, 0xD9C5, 0x5026, 0xBEEB,	0x5027, 0x828F, 0x5028, 0xD9C6, 0x5029, 0xD9BB, 0x502A, 0xC4DF,
+	0x502B, 0x8290, 0x502C, 0xD9BE, 0x502D, 0xD9C1, 0x502E, 0xD9C0,	0x502F, 0x8291, 0x5030, 0x8292, 0x5031, 0x8293, 0x5032, 0x8294,
+	0x5033, 0x8295, 0x5034, 0x8296, 0x5035, 0x8297, 0x5036, 0x8298,	0x5037, 0x8299, 0x5038, 0x829A, 0x5039, 0x829B, 0x503A, 0xD5AE,
+	0x503B, 0x829C, 0x503C, 0xD6B5, 0x503D, 0x829D, 0x503E, 0xC7E3,	0x503F, 0x829E, 0x5040, 0x829F, 0x5041, 0x82A0, 0x5042, 0x82A1,
+	0x5043, 0xD9C8, 0x5044, 0x82A2, 0x5045, 0x82A3, 0x5046, 0x82A4,	0x5047, 0xBCD9, 0x5048, 0xD9CA, 0x5049, 0x82A5, 0x504A, 0x82A6,
+	0x504B, 0x82A7, 0x504C, 0xD9BC, 0x504D, 0x82A8, 0x504E, 0xD9CB,	0x504F, 0xC6AB, 0x5050, 0x82A9, 0x5051, 0x82AA, 0x5052, 0x82AB,
+	0x5053, 0x82AC, 0x5054, 0x82AD, 0x5055, 0xD9C9, 0x5056, 0x82AE,	0x5057, 0x82AF, 0x5058, 0x82B0, 0x5059, 0x82B1, 0x505A, 0xD7F6,
+	0x505B, 0x82B2, 0x505C, 0xCDA3, 0x505D, 0x82B3, 0x505E, 0x82B4,	0x505F, 0x82B5, 0x5060, 0x82B6, 0x5061, 0x82B7, 0x5062, 0x82B8,
+	0x5063, 0x82B9, 0x5064, 0x82BA, 0x5065, 0xBDA1, 0x5066, 0x82BB,	0x5067, 0x82BC, 0x5068, 0x82BD, 0x5069, 0x82BE, 0x506A, 0x82BF,
+	0x506B, 0x82C0, 0x506C, 0xD9CC, 0x506D, 0x82C1, 0x506E, 0x82C2,	0x506F, 0x82C3, 0x5070, 0x82C4, 0x5071, 0x82C5, 0x5072, 0x82C6,
+	0x5073, 0x82C7, 0x5074, 0x82C8, 0x5075, 0x82C9, 0x5076, 0xC5BC,	0x5077, 0xCDB5, 0x5078, 0x82CA, 0x5079, 0x82CB, 0x507A, 0x82CC,
+	0x507B, 0xD9CD, 0x507C, 0x82CD, 0x507D, 0x82CE, 0x507E, 0xD9C7,	0x507F, 0xB3A5, 0x5080, 0xBFFE, 0x5081, 0x82CF, 0x5082, 0x82D0,
+	0x5083, 0x82D1, 0x5084, 0x82D2, 0x5085, 0xB8B5, 0x5086, 0x82D3,	0x5087, 0x82D4, 0x5088, 0xC0FC, 0x5089, 0x82D5, 0x508A, 0x82D6,
+	0x508B, 0x82D7, 0x508C, 0x82D8, 0x508D, 0xB0F8, 0x508E, 0x82D9,	0x508F, 0x82DA, 0x5090, 0x82DB, 0x5091, 0x82DC, 0x5092, 0x82DD,
+	0x5093, 0x82DE, 0x5094, 0x82DF, 0x5095, 0x82E0, 0x5096, 0x82E1,	0x5097, 0x82E2, 0x5098, 0x82E3, 0x5099, 0x82E4, 0x509A, 0x82E5,
+	0x509B, 0x82E6, 0x509C, 0x82E7, 0x509D, 0x82E8, 0x509E, 0x82E9,	0x509F, 0x82EA, 0x50A0, 0x82EB, 0x50A1, 0x82EC, 0x50A2, 0x82ED,
+	0x50A3, 0xB4F6, 0x50A4, 0x82EE, 0x50A5, 0xD9CE, 0x50A6, 0x82EF,	0x50A7, 0xD9CF, 0x50A8, 0xB4A2, 0x50A9, 0xD9D0, 0x50AA, 0x82F0,
+	0x50AB, 0x82F1, 0x50AC, 0xB4DF, 0x50AD, 0x82F2, 0x50AE, 0x82F3,	0x50AF, 0x82F4, 0x50B0, 0x82F5, 0x50B1, 0x82F6, 0x50B2, 0xB0C1,
+	0x50B3, 0x82F7, 0x50B4, 0x82F8, 0x50B5, 0x82F9, 0x50B6, 0x82FA,	0x50B7, 0x82FB, 0x50B8, 0x82FC, 0x50B9, 0x82FD, 0x50BA, 0xD9D1,
+	0x50BB, 0xC9B5, 0x50BC, 0x82FE, 0x50BD, 0x8340, 0x50BE, 0x8341,	0x50BF, 0x8342, 0x50C0, 0x8343, 0x50C1, 0x8344, 0x50C2, 0x8345,
+	0x50C3, 0x8346, 0x50C4, 0x8347, 0x50C5, 0x8348, 0x50C6, 0x8349,	0x50C7, 0x834A, 0x50C8, 0x834B, 0x50C9, 0x834C, 0x50CA, 0x834D,
+	0x50CB, 0x834E, 0x50CC, 0x834F, 0x50CD, 0x8350, 0x50CE, 0x8351,	0x50CF, 0xCFF1, 0x50D0, 0x8352, 0x50D1, 0x8353, 0x50D2, 0x8354,
+	0x50D3, 0x8355, 0x50D4, 0x8356, 0x50D5, 0x8357, 0x50D6, 0xD9D2,	0x50D7, 0x8358, 0x50D8, 0x8359, 0x50D9, 0x835A, 0x50DA, 0xC1C5,
+	0x50DB, 0x835B, 0x50DC, 0x835C, 0x50DD, 0x835D, 0x50DE, 0x835E,	0x50DF, 0x835F, 0x50E0, 0x8360, 0x50E1, 0x8361, 0x50E2, 0x8362,
+	0x50E3, 0x8363, 0x50E4, 0x8364, 0x50E5, 0x8365, 0x50E6, 0xD9D6,	0x50E7, 0xC9AE, 0x50E8, 0x8366, 0x50E9, 0x8367, 0x50EA, 0x8368,
+	0x50EB, 0x8369, 0x50EC, 0xD9D5, 0x50ED, 0xD9D4, 0x50EE, 0xD9D7,	0x50EF, 0x836A, 0x50F0, 0x836B, 0x50F1, 0x836C, 0x50F2, 0x836D,
+	0x50F3, 0xCBDB, 0x50F4, 0x836E, 0x50F5, 0xBDA9, 0x50F6, 0x836F,	0x50F7, 0x8370, 0x50F8, 0x8371, 0x50F9, 0x8372, 0x50FA, 0x8373,
+	0x50FB, 0xC6A7, 0x50FC, 0x8374, 0x50FD, 0x8375, 0x50FE, 0x8376,	0x50FF, 0x8377, 0x5100, 0x8378, 0x5101, 0x8379, 0x5102, 0x837A,
+	0x5103, 0x837B, 0x5104, 0x837C, 0x5105, 0x837D, 0x5106, 0xD9D3,	0x5107, 0xD9D8, 0x5108, 0x837E, 0x5109, 0x8380, 0x510A, 0x8381,
+	0x510B, 0xD9D9, 0x510C, 0x8382, 0x510D, 0x8383, 0x510E, 0x8384,	0x510F, 0x8385, 0x5110, 0x8386, 0x5111, 0x8387, 0x5112, 0xC8E5,
+	0x5113, 0x8388, 0x5114, 0x8389, 0x5115, 0x838A, 0x5116, 0x838B,	0x5117, 0x838C, 0x5118, 0x838D, 0x5119, 0x838E, 0x511A, 0x838F,
+	0x511B, 0x8390, 0x511C, 0x8391, 0x511D, 0x8392, 0x511E, 0x8393,	0x511F, 0x8394, 0x5120, 0x8395, 0x5121, 0xC0DC, 0x5122, 0x8396,
+	0x5123, 0x8397, 0x5124, 0x8398, 0x5125, 0x8399, 0x5126, 0x839A,	0x5127, 0x839B, 0x5128, 0x839C, 0x5129, 0x839D, 0x512A, 0x839E,
+	0x512B, 0x839F, 0x512C, 0x83A0, 0x512D, 0x83A1, 0x512E, 0x83A2,	0x512F, 0x83A3, 0x5130, 0x83A4, 0x5131, 0x83A5, 0x5132, 0x83A6,
+	0x5133, 0x83A7, 0x5134, 0x83A8, 0x5135, 0x83A9, 0x5136, 0x83AA,	0x5137, 0x83AB, 0x5138, 0x83AC, 0x5139, 0x83AD, 0x513A, 0x83AE,
+	0x513B, 0x83AF, 0x513C, 0x83B0, 0x513D, 0x83B1, 0x513E, 0x83B2,	0x513F, 0xB6F9, 0x5140, 0xD8A3, 0x5141, 0xD4CA, 0x5142, 0x83B3,
+	0x5143, 0xD4AA, 0x5144, 0xD0D6, 0x5145, 0xB3E4, 0x5146, 0xD5D7,	0x5147, 0x83B4, 0x5148, 0xCFC8, 0x5149, 0xB9E2, 0x514A, 0x83B5,
+	0x514B, 0xBFCB, 0x514C, 0x83B6, 0x514D, 0xC3E2, 0x514E, 0x83B7,	0x514F, 0x83B8, 0x5150, 0x83B9, 0x5151, 0xB6D2, 0x5152, 0x83BA,
+	0x5153, 0x83BB, 0x5154, 0xCDC3, 0x5155, 0xD9EE, 0x5156, 0xD9F0,	0x5157, 0x83BC, 0x5158, 0x83BD, 0x5159, 0x83BE, 0x515A, 0xB5B3,
+	0x515B, 0x83BF, 0x515C, 0xB6B5, 0x515D, 0x83C0, 0x515E, 0x83C1,	0x515F, 0x83C2, 0x5160, 0x83C3, 0x5161, 0x83C4, 0x5162, 0xBEA4,
+	0x5163, 0x83C5, 0x5164, 0x83C6, 0x5165, 0xC8EB, 0x5166, 0x83C7,	0x5167, 0x83C8, 0x5168, 0xC8AB, 0x5169, 0x83C9, 0x516A, 0x83CA,
+	0x516B, 0xB0CB, 0x516C, 0xB9AB, 0x516D, 0xC1F9, 0x516E, 0xD9E2,	0x516F, 0x83CB, 0x5170, 0xC0BC, 0x5171, 0xB9B2, 0x5172, 0x83CC,
+	0x5173, 0xB9D8, 0x5174, 0xD0CB, 0x5175, 0xB1F8, 0x5176, 0xC6E4,	0x5177, 0xBEDF, 0x5178, 0xB5E4, 0x5179, 0xD7C8, 0x517A, 0x83CD,
+	0x517B, 0xD1F8, 0x517C, 0xBCE6, 0x517D, 0xCADE, 0x517E, 0x83CE,	0x517F, 0x83CF, 0x5180, 0xBCBD, 0x5181, 0xD9E6, 0x5182, 0xD8E7,
+	0x5183, 0x83D0, 0x5184, 0x83D1, 0x5185, 0xC4DA, 0x5186, 0x83D2,	0x5187, 0x83D3, 0x5188, 0xB8D4, 0x5189, 0xC8BD, 0x518A, 0x83D4,
+	0x518B, 0x83D5, 0x518C, 0xB2E1, 0x518D, 0xD4D9, 0x518E, 0x83D6,	0x518F, 0x83D7, 0x5190, 0x83D8, 0x5191, 0x83D9, 0x5192, 0xC3B0,
+	0x5193, 0x83DA, 0x5194, 0x83DB, 0x5195, 0xC3E1, 0x5196, 0xDAA2,	0x5197, 0xC8DF, 0x5198, 0x83DC, 0x5199, 0xD0B4, 0x519A, 0x83DD,
+	0x519B, 0xBEFC, 0x519C, 0xC5A9, 0x519D, 0x83DE, 0x519E, 0x83DF,	0x519F, 0x83E0, 0x51A0, 0xB9DA, 0x51A1, 0x83E1, 0x51A2, 0xDAA3,
+	0x51A3, 0x83E2, 0x51A4, 0xD4A9, 0x51A5, 0xDAA4, 0x51A6, 0x83E3,	0x51A7, 0x83E4, 0x51A8, 0x83E5, 0x51A9, 0x83E6, 0x51AA, 0x83E7,
+	0x51AB, 0xD9FB, 0x51AC, 0xB6AC, 0x51AD, 0x83E8, 0x51AE, 0x83E9,	0x51AF, 0xB7EB, 0x51B0, 0xB1F9, 0x51B1, 0xD9FC, 0x51B2, 0xB3E5,
+	0x51B3, 0xBEF6, 0x51B4, 0x83EA, 0x51B5, 0xBFF6, 0x51B6, 0xD2B1,	0x51B7, 0xC0E4, 0x51B8, 0x83EB, 0x51B9, 0x83EC, 0x51BA, 0x83ED,
+	0x51BB, 0xB6B3, 0x51BC, 0xD9FE, 0x51BD, 0xD9FD, 0x51BE, 0x83EE,	0x51BF, 0x83EF, 0x51C0, 0xBEBB, 0x51C1, 0x83F0, 0x51C2, 0x83F1,
+	0x51C3, 0x83F2, 0x51C4, 0xC6E0, 0x51C5, 0x83F3, 0x51C6, 0xD7BC,	0x51C7, 0xDAA1, 0x51C8, 0x83F4, 0x51C9, 0xC1B9, 0x51CA, 0x83F5,
+	0x51CB, 0xB5F2, 0x51CC, 0xC1E8, 0x51CD, 0x83F6, 0x51CE, 0x83F7,	0x51CF, 0xBCF5, 0x51D0, 0x83F8, 0x51D1, 0xB4D5, 0x51D2, 0x83F9,
+	0x51D3, 0x83FA, 0x51D4, 0x83FB, 0x51D5, 0x83FC, 0x51D6, 0x83FD,	0x51D7, 0x83FE, 0x51D8, 0x8440, 0x51D9, 0x8441, 0x51DA, 0x8442,
+	0x51DB, 0xC1DD, 0x51DC, 0x8443, 0x51DD, 0xC4FD, 0x51DE, 0x8444,	0x51DF, 0x8445, 0x51E0, 0xBCB8, 0x51E1, 0xB7B2, 0x51E2, 0x8446,
+	0x51E3, 0x8447, 0x51E4, 0xB7EF, 0x51E5, 0x8448, 0x51E6, 0x8449,	0x51E7, 0x844A, 0x51E8, 0x844B, 0x51E9, 0x844C, 0x51EA, 0x844D,
+	0x51EB, 0xD9EC, 0x51EC, 0x844E, 0x51ED, 0xC6BE, 0x51EE, 0x844F,	0x51EF, 0xBFAD, 0x51F0, 0xBBCB, 0x51F1, 0x8450, 0x51F2, 0x8451,
+	0x51F3, 0xB5CA, 0x51F4, 0x8452, 0x51F5, 0xDBC9, 0x51F6, 0xD0D7,	0x51F7, 0x8453, 0x51F8, 0xCDB9, 0x51F9, 0xB0BC, 0x51FA, 0xB3F6,
+	0x51FB, 0xBBF7, 0x51FC, 0xDBCA, 0x51FD, 0xBAAF, 0x51FE, 0x8454,	0x51FF, 0xD4E4, 0x5200, 0xB5B6, 0x5201, 0xB5F3, 0x5202, 0xD8D6,
+	0x5203, 0xC8D0, 0x5204, 0x8455, 0x5205, 0x8456, 0x5206, 0xB7D6,	0x5207, 0xC7D0, 0x5208, 0xD8D7, 0x5209, 0x8457, 0x520A, 0xBFAF,
+	0x520B, 0x8458, 0x520C, 0x8459, 0x520D, 0xDBBB, 0x520E, 0xD8D8,	0x520F, 0x845A, 0x5210, 0x845B, 0x5211, 0xD0CC, 0x5212, 0xBBAE,
+	0x5213, 0x845C, 0x5214, 0x845D, 0x5215, 0x845E, 0x5216, 0xEBBE,	0x5217, 0xC1D0, 0x5218, 0xC1F5, 0x5219, 0xD4F2, 0x521A, 0xB8D5,
+	0x521B, 0xB4B4, 0x521C, 0x845F, 0x521D, 0xB3F5, 0x521E, 0x8460,	0x521F, 0x8461, 0x5220, 0xC9BE, 0x5221, 0x8462, 0x5222, 0x8463,
+	0x5223, 0x8464, 0x5224, 0xC5D0, 0x5225, 0x8465, 0x5226, 0x8466,	0x5227, 0x8467, 0x5228, 0xC5D9, 0x5229, 0xC0FB, 0x522A, 0x8468,
+	0x522B, 0xB1F0, 0x522C, 0x8469, 0x522D, 0xD8D9, 0x522E, 0xB9CE,	0x522F, 0x846A, 0x5230, 0xB5BD, 0x5231, 0x846B, 0x5232, 0x846C,
+	0x5233, 0xD8DA, 0x5234, 0x846D, 0x5235, 0x846E, 0x5236, 0xD6C6,	0x5237, 0xCBA2, 0x5238, 0xC8AF, 0x5239, 0xC9B2, 0x523A, 0xB4CC,
+	0x523B, 0xBFCC, 0x523C, 0x846F, 0x523D, 0xB9F4, 0x523E, 0x8470,	0x523F, 0xD8DB, 0x5240, 0xD8DC, 0x5241, 0xB6E7, 0x5242, 0xBCC1,
+	0x5243, 0xCCEA, 0x5244, 0x8471, 0x5245, 0x8472, 0x5246, 0x8473,	0x5247, 0x8474, 0x5248, 0x8475, 0x5249, 0x8476, 0x524A, 0xCFF7,
+	0x524B, 0x8477, 0x524C, 0xD8DD, 0x524D, 0xC7B0, 0x524E, 0x8478,	0x524F, 0x8479, 0x5250, 0xB9D0, 0x5251, 0xBDA3, 0x5252, 0x847A,
+	0x5253, 0x847B, 0x5254, 0xCCDE, 0x5255, 0x847C, 0x5256, 0xC6CA,	0x5257, 0x847D, 0x5258, 0x847E, 0x5259, 0x8480, 0x525A, 0x8481,
+	0x525B, 0x8482, 0x525C, 0xD8E0, 0x525D, 0x8483, 0x525E, 0xD8DE,	0x525F, 0x8484, 0x5260, 0x8485, 0x5261, 0xD8DF, 0x5262, 0x8486,
+	0x5263, 0x8487, 0x5264, 0x8488, 0x5265, 0xB0FE, 0x5266, 0x8489,	0x5267, 0xBEE7, 0x5268, 0x848A, 0x5269, 0xCAA3, 0x526A, 0xBCF4,
+	0x526B, 0x848B, 0x526C, 0x848C, 0x526D, 0x848D, 0x526E, 0x848E,	0x526F, 0xB8B1, 0x5270, 0x848F, 0x5271, 0x8490, 0x5272, 0xB8EE,
+	0x5273, 0x8491, 0x5274, 0x8492, 0x5275, 0x8493, 0x5276, 0x8494,	0x5277, 0x8495, 0x5278, 0x8496, 0x5279, 0x8497, 0x527A, 0x8498,
+	0x527B, 0x8499, 0x527C, 0x849A, 0x527D, 0xD8E2, 0x527E, 0x849B,	0x527F, 0xBDCB, 0x5280, 0x849C, 0x5281, 0xD8E4, 0x5282, 0xD8E3,
+	0x5283, 0x849D, 0x5284, 0x849E, 0x5285, 0x849F, 0x5286, 0x84A0,	0x5287, 0x84A1, 0x5288, 0xC5FC, 0x5289, 0x84A2, 0x528A, 0x84A3,
+	0x528B, 0x84A4, 0x528C, 0x84A5, 0x528D, 0x84A6, 0x528E, 0x84A7,	0x528F, 0x84A8, 0x5290, 0xD8E5, 0x5291, 0x84A9, 0x5292, 0x84AA,
+	0x5293, 0xD8E6, 0x5294, 0x84AB, 0x5295, 0x84AC, 0x5296, 0x84AD,	0x5297, 0x84AE, 0x5298, 0x84AF, 0x5299, 0x84B0, 0x529A, 0x84B1,
+	0x529B, 0xC1A6, 0x529C, 0x84B2, 0x529D, 0xC8B0, 0x529E, 0xB0EC,	0x529F, 0xB9A6, 0x52A0, 0xBCD3, 0x52A1, 0xCEF1, 0x52A2, 0xDBBD,
+	0x52A3, 0xC1D3, 0x52A4, 0x84B3, 0x52A5, 0x84B4, 0x52A6, 0x84B5,	0x52A7, 0x84B6, 0x52A8, 0xB6AF, 0x52A9, 0xD6FA, 0x52AA, 0xC5AC,
+	0x52AB, 0xBDD9, 0x52AC, 0xDBBE, 0x52AD, 0xDBBF, 0x52AE, 0x84B7,	0x52AF, 0x84B8, 0x52B0, 0x84B9, 0x52B1, 0xC0F8, 0x52B2, 0xBEA2,
+	0x52B3, 0xC0CD, 0x52B4, 0x84BA, 0x52B5, 0x84BB, 0x52B6, 0x84BC,	0x52B7, 0x84BD, 0x52B8, 0x84BE, 0x52B9, 0x84BF, 0x52BA, 0x84C0,
+	0x52BB, 0x84C1, 0x52BC, 0x84C2, 0x52BD, 0x84C3, 0x52BE, 0xDBC0,	0x52BF, 0xCAC6, 0x52C0, 0x84C4, 0x52C1, 0x84C5, 0x52C2, 0x84C6,
+	0x52C3, 0xB2AA, 0x52C4, 0x84C7, 0x52C5, 0x84C8, 0x52C6, 0x84C9,	0x52C7, 0xD3C2, 0x52C8, 0x84CA, 0x52C9, 0xC3E3, 0x52CA, 0x84CB,
+	0x52CB, 0xD1AB, 0x52CC, 0x84CC, 0x52CD, 0x84CD, 0x52CE, 0x84CE,	0x52CF, 0x84CF, 0x52D0, 0xDBC2, 0x52D1, 0x84D0, 0x52D2, 0xC0D5,
+	0x52D3, 0x84D1, 0x52D4, 0x84D2, 0x52D5, 0x84D3, 0x52D6, 0xDBC3,	0x52D7, 0x84D4, 0x52D8, 0xBFB1, 0x52D9, 0x84D5, 0x52DA, 0x84D6,
+	0x52DB, 0x84D7, 0x52DC, 0x84D8, 0x52DD, 0x84D9, 0x52DE, 0x84DA,	0x52DF, 0xC4BC, 0x52E0, 0x84DB, 0x52E1, 0x84DC, 0x52E2, 0x84DD,
+	0x52E3, 0x84DE, 0x52E4, 0xC7DA, 0x52E5, 0x84DF, 0x52E6, 0x84E0,	0x52E7, 0x84E1, 0x52E8, 0x84E2, 0x52E9, 0x84E3, 0x52EA, 0x84E4,
+	0x52EB, 0x84E5, 0x52EC, 0x84E6, 0x52ED, 0x84E7, 0x52EE, 0x84E8,	0x52EF, 0x84E9, 0x52F0, 0xDBC4, 0x52F1, 0x84EA, 0x52F2, 0x84EB,
+	0x52F3, 0x84EC, 0x52F4, 0x84ED, 0x52F5, 0x84EE, 0x52F6, 0x84EF,	0x52F7, 0x84F0, 0x52F8, 0x84F1, 0x52F9, 0xD9E8, 0x52FA, 0xC9D7,
+	0x52FB, 0x84F2, 0x52FC, 0x84F3, 0x52FD, 0x84F4, 0x52FE, 0xB9B4,	0x52FF, 0xCEF0, 0x5300, 0xD4C8, 0x5301, 0x84F5, 0x5302, 0x84F6,
+	0x5303, 0x84F7, 0x5304, 0x84F8, 0x5305, 0xB0FC, 0x5306, 0xB4D2,	0x5307, 0x84F9, 0x5308, 0xD0D9, 0x5309, 0x84FA, 0x530A, 0x84FB,
+	0x530B, 0x84FC, 0x530C, 0x84FD, 0x530D, 0xD9E9, 0x530E, 0x84FE,	0x530F, 0xDECB, 0x5310, 0xD9EB, 0x5311, 0x8540, 0x5312, 0x8541,
+	0x5313, 0x8542, 0x5314, 0x8543, 0x5315, 0xD8B0, 0x5316, 0xBBAF,	0x5317, 0xB1B1, 0x5318, 0x8544, 0x5319, 0xB3D7, 0x531A, 0xD8CE,
+	0x531B, 0x8545, 0x531C, 0x8546, 0x531D, 0xD4D1, 0x531E, 0x8547,	0x531F, 0x8548, 0x5320, 0xBDB3, 0x5321, 0xBFEF, 0x5322, 0x8549,
+	0x5323, 0xCFBB, 0x5324, 0x854A, 0x5325, 0x854B, 0x5326, 0xD8D0,	0x5327, 0x854C, 0x5328, 0x854D, 0x5329, 0x854E, 0x532A, 0xB7CB,
+	0x532B, 0x854F, 0x532C, 0x8550, 0x532D, 0x8551, 0x532E, 0xD8D1,	0x532F, 0x8552, 0x5330, 0x8553, 0x5331, 0x8554, 0x5332, 0x8555,
+	0x5333, 0x8556, 0x5334, 0x8557, 0x5335, 0x8558, 0x5336, 0x8559,	0x5337, 0x855A, 0x5338, 0x855B, 0x5339, 0xC6A5, 0x533A, 0xC7F8,
+	0x533B, 0xD2BD, 0x533C, 0x855C, 0x533D, 0x855D, 0x533E, 0xD8D2,	0x533F, 0xC4E4, 0x5340, 0x855E, 0x5341, 0xCAAE, 0x5342, 0x855F,
+	0x5343, 0xC7A7, 0x5344, 0x8560, 0x5345, 0xD8A6, 0x5346, 0x8561,	0x5347, 0xC9FD, 0x5348, 0xCEE7, 0x5349, 0xBBDC, 0x534A, 0xB0EB,
+	0x534B, 0x8562, 0x534C, 0x8563, 0x534D, 0x8564, 0x534E, 0xBBAA,	0x534F, 0xD0AD, 0x5350, 0x8565, 0x5351, 0xB1B0, 0x5352, 0xD7E4,
+	0x5353, 0xD7BF, 0x5354, 0x8566, 0x5355, 0xB5A5, 0x5356, 0xC2F4,	0x5357, 0xC4CF, 0x5358, 0x8567, 0x5359, 0x8568, 0x535A, 0xB2A9,
+	0x535B, 0x8569, 0x535C, 0xB2B7, 0x535D, 0x856A, 0x535E, 0xB1E5,	0x535F, 0xDFB2, 0x5360, 0xD5BC, 0x5361, 0xBFA8, 0x5362, 0xC2AC,
+	0x5363, 0xD8D5, 0x5364, 0xC2B1, 0x5365, 0x856B, 0x5366, 0xD8D4,	0x5367, 0xCED4, 0x5368, 0x856C, 0x5369, 0xDAE0, 0x536A, 0x856D,
+	0x536B, 0xCEC0, 0x536C, 0x856E, 0x536D, 0x856F, 0x536E, 0xD8B4,	0x536F, 0xC3AE, 0x5370, 0xD3A1, 0x5371, 0xCEA3, 0x5372, 0x8570,
+	0x5373, 0xBCB4, 0x5374, 0xC8B4, 0x5375, 0xC2D1, 0x5376, 0x8571,	0x5377, 0xBEED, 0x5378, 0xD0B6, 0x5379, 0x8572, 0x537A, 0xDAE1,
+	0x537B, 0x8573, 0x537C, 0x8574, 0x537D, 0x8575, 0x537E, 0x8576,	0x537F, 0xC7E4, 0x5380, 0x8577, 0x5381, 0x8578, 0x5382, 0xB3A7,
+	0x5383, 0x8579, 0x5384, 0xB6F2, 0x5385, 0xCCFC, 0x5386, 0xC0FA,	0x5387, 0x857A, 0x5388, 0x857B, 0x5389, 0xC0F7, 0x538A, 0x857C,
+	0x538B, 0xD1B9, 0x538C, 0xD1E1, 0x538D, 0xD8C7, 0x538E, 0x857D,	0x538F, 0x857E, 0x5390, 0x8580, 0x5391, 0x8581, 0x5392, 0x8582,
+	0x5393, 0x8583, 0x5394, 0x8584, 0x5395, 0xB2DE, 0x5396, 0x8585,	0x5397, 0x8586, 0x5398, 0xC0E5, 0x5399, 0x8587, 0x539A, 0xBAF1,
+	0x539B, 0x8588, 0x539C, 0x8589, 0x539D, 0xD8C8, 0x539E, 0x858A,	0x539F, 0xD4AD, 0x53A0, 0x858B, 0x53A1, 0x858C, 0x53A2, 0xCFE1,
+	0x53A3, 0xD8C9, 0x53A4, 0x858D, 0x53A5, 0xD8CA, 0x53A6, 0xCFC3,	0x53A7, 0x858E, 0x53A8, 0xB3F8, 0x53A9, 0xBEC7, 0x53AA, 0x858F,
+	0x53AB, 0x8590, 0x53AC, 0x8591, 0x53AD, 0x8592, 0x53AE, 0xD8CB,	0x53AF, 0x8593, 0x53B0, 0x8594, 0x53B1, 0x8595, 0x53B2, 0x8596,
+	0x53B3, 0x8597, 0x53B4, 0x8598, 0x53B5, 0x8599, 0x53B6, 0xDBCC,	0x53B7, 0x859A, 0x53B8, 0x859B, 0x53B9, 0x859C, 0x53BA, 0x859D,
+	0x53BB, 0xC8A5, 0x53BC, 0x859E, 0x53BD, 0x859F, 0x53BE, 0x85A0,	0x53BF, 0xCFD8, 0x53C0, 0x85A1, 0x53C1, 0xC8FE, 0x53C2, 0xB2CE,
+	0x53C3, 0x85A2, 0x53C4, 0x85A3, 0x53C5, 0x85A4, 0x53C6, 0x85A5,	0x53C7, 0x85A6, 0x53C8, 0xD3D6, 0x53C9, 0xB2E6, 0x53CA, 0xBCB0,
+	0x53CB, 0xD3D1, 0x53CC, 0xCBAB, 0x53CD, 0xB7B4, 0x53CE, 0x85A7,	0x53CF, 0x85A8, 0x53D0, 0x85A9, 0x53D1, 0xB7A2, 0x53D2, 0x85AA,
+	0x53D3, 0x85AB, 0x53D4, 0xCAE5, 0x53D5, 0x85AC, 0x53D6, 0xC8A1,	0x53D7, 0xCADC, 0x53D8, 0xB1E4, 0x53D9, 0xD0F0, 0x53DA, 0x85AD,
+	0x53DB, 0xC5D1, 0x53DC, 0x85AE, 0x53DD, 0x85AF, 0x53DE, 0x85B0,	0x53DF, 0xDBC5, 0x53E0, 0xB5FE, 0x53E1, 0x85B1, 0x53E2, 0x85B2,
+	0x53E3, 0xBFDA, 0x53E4, 0xB9C5, 0x53E5, 0xBEE4, 0x53E6, 0xC1ED,	0x53E7, 0x85B3, 0x53E8, 0xDFB6, 0x53E9, 0xDFB5, 0x53EA, 0xD6BB,
+	0x53EB, 0xBDD0, 0x53EC, 0xD5D9, 0x53ED, 0xB0C8, 0x53EE, 0xB6A3,	0x53EF, 0xBFC9, 0x53F0, 0xCCA8, 0x53F1, 0xDFB3, 0x53F2, 0xCAB7,
+	0x53F3, 0xD3D2, 0x53F4, 0x85B4, 0x53F5, 0xD8CF, 0x53F6, 0xD2B6,	0x53F7, 0xBAC5, 0x53F8, 0xCBBE, 0x53F9, 0xCCBE, 0x53FA, 0x85B5,
+	0x53FB, 0xDFB7, 0x53FC, 0xB5F0, 0x53FD, 0xDFB4, 0x53FE, 0x85B6,	0x53FF, 0x85B7, 0x5400, 0x85B8, 0x5401, 0xD3F5, 0x5402, 0x85B9,
+	0x5403, 0xB3D4, 0x5404, 0xB8F7, 0x5405, 0x85BA, 0x5406, 0xDFBA,	0x5407, 0x85BB, 0x5408, 0xBACF, 0x5409, 0xBCAA, 0x540A, 0xB5F5,
+	0x540B, 0x85BC, 0x540C, 0xCDAC, 0x540D, 0xC3FB, 0x540E, 0xBAF3,	0x540F, 0xC0F4, 0x5410, 0xCDC2, 0x5411, 0xCFF2, 0x5412, 0xDFB8,
+	0x5413, 0xCFC5, 0x5414, 0x85BD, 0x5415, 0xC2C0, 0x5416, 0xDFB9,	0x5417, 0xC2F0, 0x5418, 0x85BE, 0x5419, 0x85BF, 0x541A, 0x85C0,
+	0x541B, 0xBEFD, 0x541C, 0x85C1, 0x541D, 0xC1DF, 0x541E, 0xCDCC,	0x541F, 0xD2F7, 0x5420, 0xB7CD, 0x5421, 0xDFC1, 0x5422, 0x85C2,
+	0x5423, 0xDFC4, 0x5424, 0x85C3, 0x5425, 0x85C4, 0x5426, 0xB7F1,	0x5427, 0xB0C9, 0x5428, 0xB6D6, 0x5429, 0xB7D4, 0x542A, 0x85C5,
+	0x542B, 0xBAAC, 0x542C, 0xCCFD, 0x542D, 0xBFD4, 0x542E, 0xCBB1,	0x542F, 0xC6F4, 0x5430, 0x85C6, 0x5431, 0xD6A8, 0x5432, 0xDFC5,
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+	0x577B, 0xDBE6, 0x577C, 0xDBE5, 0x577D, 0x887B, 0x577E, 0x887C,	0x577F, 0x887D, 0x5780, 0x887E, 0x5781, 0x8880, 0x5782, 0xB4B9,
+	0x5783, 0xC0AC, 0x5784, 0xC2A2, 0x5785, 0xDBE2, 0x5786, 0xDBE4,	0x5787, 0x8881, 0x5788, 0x8882, 0x5789, 0x8883, 0x578A, 0x8884,
+	0x578B, 0xD0CD, 0x578C, 0xDBED, 0x578D, 0x8885, 0x578E, 0x8886,	0x578F, 0x8887, 0x5790, 0x8888, 0x5791, 0x8889, 0x5792, 0xC0DD,
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+	0x57A3, 0xD4AB, 0x57A4, 0xDBEC, 0x57A5, 0x8895, 0x57A6, 0xBFD1,	0x57A7, 0xDBF0, 0x57A8, 0x8896, 0x57A9, 0xDBD1, 0x57AA, 0x8897,
+	0x57AB, 0xB5E6, 0x57AC, 0x8898, 0x57AD, 0xDBEB, 0x57AE, 0xBFE5,	0x57AF, 0x8899, 0x57B0, 0x889A, 0x57B1, 0x889B, 0x57B2, 0xDBEE,
+	0x57B3, 0x889C, 0x57B4, 0xDBF1, 0x57B5, 0x889D, 0x57B6, 0x889E,	0x57B7, 0x889F, 0x57B8, 0xDBF9, 0x57B9, 0x88A0, 0x57BA, 0x88A1,
+	0x57BB, 0x88A2, 0x57BC, 0x88A3, 0x57BD, 0x88A4, 0x57BE, 0x88A5,	0x57BF, 0x88A6, 0x57C0, 0x88A7, 0x57C1, 0x88A8, 0x57C2, 0xB9A1,
+	0x57C3, 0xB0A3, 0x57C4, 0x88A9, 0x57C5, 0x88AA, 0x57C6, 0x88AB,	0x57C7, 0x88AC, 0x57C8, 0x88AD, 0x57C9, 0x88AE, 0x57CA, 0x88AF,
+	0x57CB, 0xC2F1, 0x57CC, 0x88B0, 0x57CD, 0x88B1, 0x57CE, 0xB3C7,	0x57CF, 0xDBEF, 0x57D0, 0x88B2, 0x57D1, 0x88B3, 0x57D2, 0xDBF8,
+	0x57D3, 0x88B4, 0x57D4, 0xC6D2, 0x57D5, 0xDBF4, 0x57D6, 0x88B5,	0x57D7, 0x88B6, 0x57D8, 0xDBF5, 0x57D9, 0xDBF7, 0x57DA, 0xDBF6,
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+	0x57E3, 0x88BC, 0x57E4, 0xDBFD, 0x57E5, 0x88BD, 0x57E6, 0x88BE,	0x57E7, 0x88BF, 0x57E8, 0x88C0, 0x57E9, 0x88C1, 0x57EA, 0x88C2,
+	0x57EB, 0x88C3, 0x57EC, 0x88C4, 0x57ED, 0xDCA4, 0x57EE, 0x88C5,	0x57EF, 0xDBFB, 0x57F0, 0x88C6, 0x57F1, 0x88C7, 0x57F2, 0x88C8,
+	0x57F3, 0x88C9, 0x57F4, 0xDBFA, 0x57F5, 0x88CA, 0x57F6, 0x88CB,	0x57F7, 0x88CC, 0x57F8, 0xDBFC, 0x57F9, 0xC5E0, 0x57FA, 0xBBF9,
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+	0x580B, 0xDCA1, 0x580C, 0x88D8, 0x580D, 0xDCA2, 0x580E, 0x88D9,	0x580F, 0x88DA, 0x5810, 0x88DB, 0x5811, 0xC7B5, 0x5812, 0x88DC,
+	0x5813, 0x88DD, 0x5814, 0x88DE, 0x5815, 0xB6E9, 0x5816, 0x88DF,	0x5817, 0x88E0, 0x5818, 0x88E1, 0x5819, 0xDCA7, 0x581A, 0x88E2,
+	0x581B, 0x88E3, 0x581C, 0x88E4, 0x581D, 0x88E5, 0x581E, 0xDCA6,	0x581F, 0x88E6, 0x5820, 0xDCA9, 0x5821, 0xB1A4, 0x5822, 0x88E7,
+	0x5823, 0x88E8, 0x5824, 0xB5CC, 0x5825, 0x88E9, 0x5826, 0x88EA,	0x5827, 0x88EB, 0x5828, 0x88EC, 0x5829, 0x88ED, 0x582A, 0xBFB0,
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+	0x58DB, 0x89C1, 0x58DC, 0x89C2, 0x58DD, 0x89C3, 0x58DE, 0x89C4,	0x58DF, 0x89C5, 0x58E0, 0x89C6, 0x58E1, 0x89C7, 0x58E2, 0x89C8,
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+	0x596B, 0x8A5B, 0x596C, 0x8A5C, 0x596D, 0x8A5D, 0x596E, 0x8A5E,	0x596F, 0x8A5F, 0x5970, 0x8A60, 0x5971, 0x8A61, 0x5972, 0x8A62,
+	0x5973, 0xC5AE, 0x5974, 0xC5AB, 0x5975, 0x8A63, 0x5976, 0xC4CC,	0x5977, 0x8A64, 0x5978, 0xBCE9, 0x5979, 0xCBFD, 0x597A, 0x8A65,
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+	0x5983, 0xE5FA, 0x5984, 0xCDFD, 0x5985, 0x8A6B, 0x5986, 0xD7B1,	0x5987, 0xB8BE, 0x5988, 0xC2E8, 0x5989, 0x8A6C, 0x598A, 0xC8D1,
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+	0x59D3, 0xD0D5, 0x59D4, 0xCEAF, 0x59D5, 0x8A9C, 0x59D6, 0x8A9D,	0x59D7, 0xE6A9, 0x59D8, 0xE6B0, 0x59D9, 0x8A9E, 0x59DA, 0xD2A6,
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+	0x59E3, 0xE6AF, 0x59E4, 0x8AA5, 0x59E5, 0xC0D1, 0x59E6, 0x8AA6,	0x59E7, 0x8AA7, 0x59E8, 0xD2CC, 0x59E9, 0x8AA8, 0x59EA, 0x8AA9,
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+	0x59F3, 0x8AB1, 0x59F4, 0x8AB2, 0x59F5, 0x8AB3, 0x59F6, 0x8AB4,	0x59F7, 0x8AB5, 0x59F8, 0x8AB6, 0x59F9, 0xE6B1, 0x59FA, 0x8AB7,
+	0x59FB, 0xD2F6, 0x59FC, 0x8AB8, 0x59FD, 0x8AB9, 0x59FE, 0x8ABA,	0x59FF, 0xD7CB, 0x5A00, 0x8ABB, 0x5A01, 0xCDFE, 0x5A02, 0x8ABC,
+	0x5A03, 0xCDDE, 0x5A04, 0xC2A6, 0x5A05, 0xE6AB, 0x5A06, 0xE6AC,	0x5A07, 0xBDBF, 0x5A08, 0xE6AE, 0x5A09, 0xE6B3, 0x5A0A, 0x8ABD,
+	0x5A0B, 0x8ABE, 0x5A0C, 0xE6B2, 0x5A0D, 0x8ABF, 0x5A0E, 0x8AC0,	0x5A0F, 0x8AC1, 0x5A10, 0x8AC2, 0x5A11, 0xE6B6, 0x5A12, 0x8AC3,
+	0x5A13, 0xE6B8, 0x5A14, 0x8AC4, 0x5A15, 0x8AC5, 0x5A16, 0x8AC6,	0x5A17, 0x8AC7, 0x5A18, 0xC4EF, 0x5A19, 0x8AC8, 0x5A1A, 0x8AC9,
+	0x5A1B, 0x8ACA, 0x5A1C, 0xC4C8, 0x5A1D, 0x8ACB, 0x5A1E, 0x8ACC,	0x5A1F, 0xBEEA, 0x5A20, 0xC9EF, 0x5A21, 0x8ACD, 0x5A22, 0x8ACE,
+	0x5A23, 0xE6B7, 0x5A24, 0x8ACF, 0x5A25, 0xB6F0, 0x5A26, 0x8AD0,	0x5A27, 0x8AD1, 0x5A28, 0x8AD2, 0x5A29, 0xC3E4, 0x5A2A, 0x8AD3,
+	0x5A2B, 0x8AD4, 0x5A2C, 0x8AD5, 0x5A2D, 0x8AD6, 0x5A2E, 0x8AD7,	0x5A2F, 0x8AD8, 0x5A30, 0x8AD9, 0x5A31, 0xD3E9, 0x5A32, 0xE6B4,
+	0x5A33, 0x8ADA, 0x5A34, 0xE6B5, 0x5A35, 0x8ADB, 0x5A36, 0xC8A2,	0x5A37, 0x8ADC, 0x5A38, 0x8ADD, 0x5A39, 0x8ADE, 0x5A3A, 0x8ADF,
+	0x5A3B, 0x8AE0, 0x5A3C, 0xE6BD, 0x5A3D, 0x8AE1, 0x5A3E, 0x8AE2,	0x5A3F, 0x8AE3, 0x5A40, 0xE6B9, 0x5A41, 0x8AE4, 0x5A42, 0x8AE5,
+	0x5A43, 0x8AE6, 0x5A44, 0x8AE7, 0x5A45, 0x8AE8, 0x5A46, 0xC6C5,	0x5A47, 0x8AE9, 0x5A48, 0x8AEA, 0x5A49, 0xCDF1, 0x5A4A, 0xE6BB,
+	0x5A4B, 0x8AEB, 0x5A4C, 0x8AEC, 0x5A4D, 0x8AED, 0x5A4E, 0x8AEE,	0x5A4F, 0x8AEF, 0x5A50, 0x8AF0, 0x5A51, 0x8AF1, 0x5A52, 0x8AF2,
+	0x5A53, 0x8AF3, 0x5A54, 0x8AF4, 0x5A55, 0xE6BC, 0x5A56, 0x8AF5,	0x5A57, 0x8AF6, 0x5A58, 0x8AF7, 0x5A59, 0x8AF8, 0x5A5A, 0xBBE9,
+	0x5A5B, 0x8AF9, 0x5A5C, 0x8AFA, 0x5A5D, 0x8AFB, 0x5A5E, 0x8AFC,	0x5A5F, 0x8AFD, 0x5A60, 0x8AFE, 0x5A61, 0x8B40, 0x5A62, 0xE6BE,
+	0x5A63, 0x8B41, 0x5A64, 0x8B42, 0x5A65, 0x8B43, 0x5A66, 0x8B44,	0x5A67, 0xE6BA, 0x5A68, 0x8B45, 0x5A69, 0x8B46, 0x5A6A, 0xC0B7,
+	0x5A6B, 0x8B47, 0x5A6C, 0x8B48, 0x5A6D, 0x8B49, 0x5A6E, 0x8B4A,	0x5A6F, 0x8B4B, 0x5A70, 0x8B4C, 0x5A71, 0x8B4D, 0x5A72, 0x8B4E,
+	0x5A73, 0x8B4F, 0x5A74, 0xD3A4, 0x5A75, 0xE6BF, 0x5A76, 0xC9F4,	0x5A77, 0xE6C3, 0x5A78, 0x8B50, 0x5A79, 0x8B51, 0x5A7A, 0xE6C4,
+	0x5A7B, 0x8B52, 0x5A7C, 0x8B53, 0x5A7D, 0x8B54, 0x5A7E, 0x8B55,	0x5A7F, 0xD0F6, 0x5A80, 0x8B56, 0x5A81, 0x8B57, 0x5A82, 0x8B58,
+	0x5A83, 0x8B59, 0x5A84, 0x8B5A, 0x5A85, 0x8B5B, 0x5A86, 0x8B5C,	0x5A87, 0x8B5D, 0x5A88, 0x8B5E, 0x5A89, 0x8B5F, 0x5A8A, 0x8B60,
+	0x5A8B, 0x8B61, 0x5A8C, 0x8B62, 0x5A8D, 0x8B63, 0x5A8E, 0x8B64,	0x5A8F, 0x8B65, 0x5A90, 0x8B66, 0x5A91, 0x8B67, 0x5A92, 0xC3BD,
+	0x5A93, 0x8B68, 0x5A94, 0x8B69, 0x5A95, 0x8B6A, 0x5A96, 0x8B6B,	0x5A97, 0x8B6C, 0x5A98, 0x8B6D, 0x5A99, 0x8B6E, 0x5A9A, 0xC3C4,
+	0x5A9B, 0xE6C2, 0x5A9C, 0x8B6F, 0x5A9D, 0x8B70, 0x5A9E, 0x8B71,	0x5A9F, 0x8B72, 0x5AA0, 0x8B73, 0x5AA1, 0x8B74, 0x5AA2, 0x8B75,
+	0x5AA3, 0x8B76, 0x5AA4, 0x8B77, 0x5AA5, 0x8B78, 0x5AA6, 0x8B79,	0x5AA7, 0x8B7A, 0x5AA8, 0x8B7B, 0x5AA9, 0x8B7C, 0x5AAA, 0xE6C1,
+	0x5AAB, 0x8B7D, 0x5AAC, 0x8B7E, 0x5AAD, 0x8B80, 0x5AAE, 0x8B81,	0x5AAF, 0x8B82, 0x5AB0, 0x8B83, 0x5AB1, 0x8B84, 0x5AB2, 0xE6C7,
+	0x5AB3, 0xCFB1, 0x5AB4, 0x8B85, 0x5AB5, 0xEBF4, 0x5AB6, 0x8B86,	0x5AB7, 0x8B87, 0x5AB8, 0xE6CA, 0x5AB9, 0x8B88, 0x5ABA, 0x8B89,
+	0x5ABB, 0x8B8A, 0x5ABC, 0x8B8B, 0x5ABD, 0x8B8C, 0x5ABE, 0xE6C5,	0x5ABF, 0x8B8D, 0x5AC0, 0x8B8E, 0x5AC1, 0xBCDE, 0x5AC2, 0xC9A9,
+	0x5AC3, 0x8B8F, 0x5AC4, 0x8B90, 0x5AC5, 0x8B91, 0x5AC6, 0x8B92,	0x5AC7, 0x8B93, 0x5AC8, 0x8B94, 0x5AC9, 0xBCB5, 0x5ACA, 0x8B95,
+	0x5ACB, 0x8B96, 0x5ACC, 0xCFD3, 0x5ACD, 0x8B97, 0x5ACE, 0x8B98,	0x5ACF, 0x8B99, 0x5AD0, 0x8B9A, 0x5AD1, 0x8B9B, 0x5AD2, 0xE6C8,
+	0x5AD3, 0x8B9C, 0x5AD4, 0xE6C9, 0x5AD5, 0x8B9D, 0x5AD6, 0xE6CE,	0x5AD7, 0x8B9E, 0x5AD8, 0xE6D0, 0x5AD9, 0x8B9F, 0x5ADA, 0x8BA0,
+	0x5ADB, 0x8BA1, 0x5ADC, 0xE6D1, 0x5ADD, 0x8BA2, 0x5ADE, 0x8BA3,	0x5ADF, 0x8BA4, 0x5AE0, 0xE6CB, 0x5AE1, 0xB5D5, 0x5AE2, 0x8BA5,
+	0x5AE3, 0xE6CC, 0x5AE4, 0x8BA6, 0x5AE5, 0x8BA7, 0x5AE6, 0xE6CF,	0x5AE7, 0x8BA8, 0x5AE8, 0x8BA9, 0x5AE9, 0xC4DB, 0x5AEA, 0x8BAA,
+	0x5AEB, 0xE6C6, 0x5AEC, 0x8BAB, 0x5AED, 0x8BAC, 0x5AEE, 0x8BAD,	0x5AEF, 0x8BAE, 0x5AF0, 0x8BAF, 0x5AF1, 0xE6CD, 0x5AF2, 0x8BB0,
+	0x5AF3, 0x8BB1, 0x5AF4, 0x8BB2, 0x5AF5, 0x8BB3, 0x5AF6, 0x8BB4,	0x5AF7, 0x8BB5, 0x5AF8, 0x8BB6, 0x5AF9, 0x8BB7, 0x5AFA, 0x8BB8,
+	0x5AFB, 0x8BB9, 0x5AFC, 0x8BBA, 0x5AFD, 0x8BBB, 0x5AFE, 0x8BBC,	0x5AFF, 0x8BBD, 0x5B00, 0x8BBE, 0x5B01, 0x8BBF, 0x5B02, 0x8BC0,
+	0x5B03, 0x8BC1, 0x5B04, 0x8BC2, 0x5B05, 0x8BC3, 0x5B06, 0x8BC4,	0x5B07, 0x8BC5, 0x5B08, 0x8BC6, 0x5B09, 0xE6D2, 0x5B0A, 0x8BC7,
+	0x5B0B, 0x8BC8, 0x5B0C, 0x8BC9, 0x5B0D, 0x8BCA, 0x5B0E, 0x8BCB,	0x5B0F, 0x8BCC, 0x5B10, 0x8BCD, 0x5B11, 0x8BCE, 0x5B12, 0x8BCF,
+	0x5B13, 0x8BD0, 0x5B14, 0x8BD1, 0x5B15, 0x8BD2, 0x5B16, 0xE6D4,	0x5B17, 0xE6D3, 0x5B18, 0x8BD3, 0x5B19, 0x8BD4, 0x5B1A, 0x8BD5,
+	0x5B1B, 0x8BD6, 0x5B1C, 0x8BD7, 0x5B1D, 0x8BD8, 0x5B1E, 0x8BD9,	0x5B1F, 0x8BDA, 0x5B20, 0x8BDB, 0x5B21, 0x8BDC, 0x5B22, 0x8BDD,
+	0x5B23, 0x8BDE, 0x5B24, 0x8BDF, 0x5B25, 0x8BE0, 0x5B26, 0x8BE1,	0x5B27, 0x8BE2, 0x5B28, 0x8BE3, 0x5B29, 0x8BE4, 0x5B2A, 0x8BE5,
+	0x5B2B, 0x8BE6, 0x5B2C, 0x8BE7, 0x5B2D, 0x8BE8, 0x5B2E, 0x8BE9,	0x5B2F, 0x8BEA, 0x5B30, 0x8BEB, 0x5B31, 0x8BEC, 0x5B32, 0xE6D5,
+	0x5B33, 0x8BED, 0x5B34, 0xD9F8, 0x5B35, 0x8BEE, 0x5B36, 0x8BEF,	0x5B37, 0xE6D6, 0x5B38, 0x8BF0, 0x5B39, 0x8BF1, 0x5B3A, 0x8BF2,
+	0x5B3B, 0x8BF3, 0x5B3C, 0x8BF4, 0x5B3D, 0x8BF5, 0x5B3E, 0x8BF6,	0x5B3F, 0x8BF7, 0x5B40, 0xE6D7, 0x5B41, 0x8BF8, 0x5B42, 0x8BF9,
+	0x5B43, 0x8BFA, 0x5B44, 0x8BFB, 0x5B45, 0x8BFC, 0x5B46, 0x8BFD,	0x5B47, 0x8BFE, 0x5B48, 0x8C40, 0x5B49, 0x8C41, 0x5B4A, 0x8C42,
+	0x5B4B, 0x8C43, 0x5B4C, 0x8C44, 0x5B4D, 0x8C45, 0x5B4E, 0x8C46,	0x5B4F, 0x8C47, 0x5B50, 0xD7D3, 0x5B51, 0xE6DD, 0x5B52, 0x8C48,
+	0x5B53, 0xE6DE, 0x5B54, 0xBFD7, 0x5B55, 0xD4D0, 0x5B56, 0x8C49,	0x5B57, 0xD7D6, 0x5B58, 0xB4E6, 0x5B59, 0xCBEF, 0x5B5A, 0xE6DA,
+	0x5B5B, 0xD8C3, 0x5B5C, 0xD7CE, 0x5B5D, 0xD0A2, 0x5B5E, 0x8C4A,	0x5B5F, 0xC3CF, 0x5B60, 0x8C4B, 0x5B61, 0x8C4C, 0x5B62, 0xE6DF,
+	0x5B63, 0xBCBE, 0x5B64, 0xB9C2, 0x5B65, 0xE6DB, 0x5B66, 0xD1A7,	0x5B67, 0x8C4D, 0x5B68, 0x8C4E, 0x5B69, 0xBAA2, 0x5B6A, 0xC2CF,
+	0x5B6B, 0x8C4F, 0x5B6C, 0xD8AB, 0x5B6D, 0x8C50, 0x5B6E, 0x8C51,	0x5B6F, 0x8C52, 0x5B70, 0xCAEB, 0x5B71, 0xE5EE, 0x5B72, 0x8C53,
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+	0x5B7B, 0x8C59, 0x5B7C, 0x8C5A, 0x5B7D, 0xC4F5, 0x5B7E, 0x8C5B,	0x5B7F, 0x8C5C, 0x5B80, 0xE5B2, 0x5B81, 0xC4FE, 0x5B82, 0x8C5D,
+	0x5B83, 0xCBFC, 0x5B84, 0xE5B3, 0x5B85, 0xD5AC, 0x5B86, 0x8C5E,	0x5B87, 0xD3EE, 0x5B88, 0xCAD8, 0x5B89, 0xB0B2, 0x5B8A, 0x8C5F,
+	0x5B8B, 0xCBCE, 0x5B8C, 0xCDEA, 0x5B8D, 0x8C60, 0x5B8E, 0x8C61,	0x5B8F, 0xBAEA, 0x5B90, 0x8C62, 0x5B91, 0x8C63, 0x5B92, 0x8C64,
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+	0x5B9B, 0xCDF0, 0x5B9C, 0xD2CB, 0x5B9D, 0xB1A6, 0x5B9E, 0xCAB5,	0x5B9F, 0x8C67, 0x5BA0, 0xB3E8, 0x5BA1, 0xC9F3, 0x5BA2, 0xBFCD,
+	0x5BA3, 0xD0FB, 0x5BA4, 0xCAD2, 0x5BA5, 0xE5B6, 0x5BA6, 0xBBC2,	0x5BA7, 0x8C68, 0x5BA8, 0x8C69, 0x5BA9, 0x8C6A, 0x5BAA, 0xCFDC,
+	0x5BAB, 0xB9AC, 0x5BAC, 0x8C6B, 0x5BAD, 0x8C6C, 0x5BAE, 0x8C6D,	0x5BAF, 0x8C6E, 0x5BB0, 0xD4D7, 0x5BB1, 0x8C6F, 0x5BB2, 0x8C70,
+	0x5BB3, 0xBAA6, 0x5BB4, 0xD1E7, 0x5BB5, 0xCFFC, 0x5BB6, 0xBCD2,	0x5BB7, 0x8C71, 0x5BB8, 0xE5B7, 0x5BB9, 0xC8DD, 0x5BBA, 0x8C72,
+	0x5BBB, 0x8C73, 0x5BBC, 0x8C74, 0x5BBD, 0xBFED, 0x5BBE, 0xB1F6,	0x5BBF, 0xCBDE, 0x5BC0, 0x8C75, 0x5BC1, 0x8C76, 0x5BC2, 0xBCC5,
+	0x5BC3, 0x8C77, 0x5BC4, 0xBCC4, 0x5BC5, 0xD2FA, 0x5BC6, 0xC3DC,	0x5BC7, 0xBFDC, 0x5BC8, 0x8C78, 0x5BC9, 0x8C79, 0x5BCA, 0x8C7A,
+	0x5BCB, 0x8C7B, 0x5BCC, 0xB8BB, 0x5BCD, 0x8C7C, 0x5BCE, 0x8C7D,	0x5BCF, 0x8C7E, 0x5BD0, 0xC3C2, 0x5BD1, 0x8C80, 0x5BD2, 0xBAAE,
+	0x5BD3, 0xD4A2, 0x5BD4, 0x8C81, 0x5BD5, 0x8C82, 0x5BD6, 0x8C83,	0x5BD7, 0x8C84, 0x5BD8, 0x8C85, 0x5BD9, 0x8C86, 0x5BDA, 0x8C87,
+	0x5BDB, 0x8C88, 0x5BDC, 0x8C89, 0x5BDD, 0xC7DE, 0x5BDE, 0xC4AF,	0x5BDF, 0xB2EC, 0x5BE0, 0x8C8A, 0x5BE1, 0xB9D1, 0x5BE2, 0x8C8B,
+	0x5BE3, 0x8C8C, 0x5BE4, 0xE5BB, 0x5BE5, 0xC1C8, 0x5BE6, 0x8C8D,	0x5BE7, 0x8C8E, 0x5BE8, 0xD5AF, 0x5BE9, 0x8C8F, 0x5BEA, 0x8C90,
+	0x5BEB, 0x8C91, 0x5BEC, 0x8C92, 0x5BED, 0x8C93, 0x5BEE, 0xE5BC,	0x5BEF, 0x8C94, 0x5BF0, 0xE5BE, 0x5BF1, 0x8C95, 0x5BF2, 0x8C96,
+	0x5BF3, 0x8C97, 0x5BF4, 0x8C98, 0x5BF5, 0x8C99, 0x5BF6, 0x8C9A,	0x5BF7, 0x8C9B, 0x5BF8, 0xB4E7, 0x5BF9, 0xB6D4, 0x5BFA, 0xCBC2,
+	0x5BFB, 0xD1B0, 0x5BFC, 0xB5BC, 0x5BFD, 0x8C9C, 0x5BFE, 0x8C9D,	0x5BFF, 0xCAD9, 0x5C00, 0x8C9E, 0x5C01, 0xB7E2, 0x5C02, 0x8C9F,
+	0x5C03, 0x8CA0, 0x5C04, 0xC9E4, 0x5C05, 0x8CA1, 0x5C06, 0xBDAB,	0x5C07, 0x8CA2, 0x5C08, 0x8CA3, 0x5C09, 0xCEBE, 0x5C0A, 0xD7F0,
+	0x5C0B, 0x8CA4, 0x5C0C, 0x8CA5, 0x5C0D, 0x8CA6, 0x5C0E, 0x8CA7,	0x5C0F, 0xD0A1, 0x5C10, 0x8CA8, 0x5C11, 0xC9D9, 0x5C12, 0x8CA9,
+	0x5C13, 0x8CAA, 0x5C14, 0xB6FB, 0x5C15, 0xE6D8, 0x5C16, 0xBCE2,	0x5C17, 0x8CAB, 0x5C18, 0xB3BE, 0x5C19, 0x8CAC, 0x5C1A, 0xC9D0,
+	0x5C1B, 0x8CAD, 0x5C1C, 0xE6D9, 0x5C1D, 0xB3A2, 0x5C1E, 0x8CAE,	0x5C1F, 0x8CAF, 0x5C20, 0x8CB0, 0x5C21, 0x8CB1, 0x5C22, 0xDECC,
+	0x5C23, 0x8CB2, 0x5C24, 0xD3C8, 0x5C25, 0xDECD, 0x5C26, 0x8CB3,	0x5C27, 0xD2A2, 0x5C28, 0x8CB4, 0x5C29, 0x8CB5, 0x5C2A, 0x8CB6,
+	0x5C2B, 0x8CB7, 0x5C2C, 0xDECE, 0x5C2D, 0x8CB8, 0x5C2E, 0x8CB9,	0x5C2F, 0x8CBA, 0x5C30, 0x8CBB, 0x5C31, 0xBECD, 0x5C32, 0x8CBC,
+	0x5C33, 0x8CBD, 0x5C34, 0xDECF, 0x5C35, 0x8CBE, 0x5C36, 0x8CBF,	0x5C37, 0x8CC0, 0x5C38, 0xCAAC, 0x5C39, 0xD2FC, 0x5C3A, 0xB3DF,
+	0x5C3B, 0xE5EA, 0x5C3C, 0xC4E1, 0x5C3D, 0xBEA1, 0x5C3E, 0xCEB2,	0x5C3F, 0xC4F2, 0x5C40, 0xBED6, 0x5C41, 0xC6A8, 0x5C42, 0xB2E3,
+	0x5C43, 0x8CC1, 0x5C44, 0x8CC2, 0x5C45, 0xBED3, 0x5C46, 0x8CC3,	0x5C47, 0x8CC4, 0x5C48, 0xC7FC, 0x5C49, 0xCCEB, 0x5C4A, 0xBDEC,
+	0x5C4B, 0xCEDD, 0x5C4C, 0x8CC5, 0x5C4D, 0x8CC6, 0x5C4E, 0xCABA,	0x5C4F, 0xC6C1, 0x5C50, 0xE5EC, 0x5C51, 0xD0BC, 0x5C52, 0x8CC7,
+	0x5C53, 0x8CC8, 0x5C54, 0x8CC9, 0x5C55, 0xD5B9, 0x5C56, 0x8CCA,	0x5C57, 0x8CCB, 0x5C58, 0x8CCC, 0x5C59, 0xE5ED, 0x5C5A, 0x8CCD,
+	0x5C5B, 0x8CCE, 0x5C5C, 0x8CCF, 0x5C5D, 0x8CD0, 0x5C5E, 0xCAF4,	0x5C5F, 0x8CD1, 0x5C60, 0xCDC0, 0x5C61, 0xC2C5, 0x5C62, 0x8CD2,
+	0x5C63, 0xE5EF, 0x5C64, 0x8CD3, 0x5C65, 0xC2C4, 0x5C66, 0xE5F0,	0x5C67, 0x8CD4, 0x5C68, 0x8CD5, 0x5C69, 0x8CD6, 0x5C6A, 0x8CD7,
+	0x5C6B, 0x8CD8, 0x5C6C, 0x8CD9, 0x5C6D, 0x8CDA, 0x5C6E, 0xE5F8,	0x5C6F, 0xCDCD, 0x5C70, 0x8CDB, 0x5C71, 0xC9BD, 0x5C72, 0x8CDC,
+	0x5C73, 0x8CDD, 0x5C74, 0x8CDE, 0x5C75, 0x8CDF, 0x5C76, 0x8CE0,	0x5C77, 0x8CE1, 0x5C78, 0x8CE2, 0x5C79, 0xD2D9, 0x5C7A, 0xE1A8,
+	0x5C7B, 0x8CE3, 0x5C7C, 0x8CE4, 0x5C7D, 0x8CE5, 0x5C7E, 0x8CE6,	0x5C7F, 0xD3EC, 0x5C80, 0x8CE7, 0x5C81, 0xCBEA, 0x5C82, 0xC6F1,
+	0x5C83, 0x8CE8, 0x5C84, 0x8CE9, 0x5C85, 0x8CEA, 0x5C86, 0x8CEB,	0x5C87, 0x8CEC, 0x5C88, 0xE1AC, 0x5C89, 0x8CED, 0x5C8A, 0x8CEE,
+	0x5C8B, 0x8CEF, 0x5C8C, 0xE1A7, 0x5C8D, 0xE1A9, 0x5C8E, 0x8CF0,	0x5C8F, 0x8CF1, 0x5C90, 0xE1AA, 0x5C91, 0xE1AF, 0x5C92, 0x8CF2,
+	0x5C93, 0x8CF3, 0x5C94, 0xB2ED, 0x5C95, 0x8CF4, 0x5C96, 0xE1AB,	0x5C97, 0xB8DA, 0x5C98, 0xE1AD, 0x5C99, 0xE1AE, 0x5C9A, 0xE1B0,
+	0x5C9B, 0xB5BA, 0x5C9C, 0xE1B1, 0x5C9D, 0x8CF5, 0x5C9E, 0x8CF6,	0x5C9F, 0x8CF7, 0x5CA0, 0x8CF8, 0x5CA1, 0x8CF9, 0x5CA2, 0xE1B3,
+	0x5CA3, 0xE1B8, 0x5CA4, 0x8CFA, 0x5CA5, 0x8CFB, 0x5CA6, 0x8CFC,	0x5CA7, 0x8CFD, 0x5CA8, 0x8CFE, 0x5CA9, 0xD1D2, 0x5CAA, 0x8D40,
+	0x5CAB, 0xE1B6, 0x5CAC, 0xE1B5, 0x5CAD, 0xC1EB, 0x5CAE, 0x8D41,	0x5CAF, 0x8D42, 0x5CB0, 0x8D43, 0x5CB1, 0xE1B7, 0x5CB2, 0x8D44,
+	0x5CB3, 0xD4C0, 0x5CB4, 0x8D45, 0x5CB5, 0xE1B2, 0x5CB6, 0x8D46,	0x5CB7, 0xE1BA, 0x5CB8, 0xB0B6, 0x5CB9, 0x8D47, 0x5CBA, 0x8D48,
+	0x5CBB, 0x8D49, 0x5CBC, 0x8D4A, 0x5CBD, 0xE1B4, 0x5CBE, 0x8D4B,	0x5CBF, 0xBFF9, 0x5CC0, 0x8D4C, 0x5CC1, 0xE1B9, 0x5CC2, 0x8D4D,
+	0x5CC3, 0x8D4E, 0x5CC4, 0xE1BB, 0x5CC5, 0x8D4F, 0x5CC6, 0x8D50,	0x5CC7, 0x8D51, 0x5CC8, 0x8D52, 0x5CC9, 0x8D53, 0x5CCA, 0x8D54,
+	0x5CCB, 0xE1BE, 0x5CCC, 0x8D55, 0x5CCD, 0x8D56, 0x5CCE, 0x8D57,	0x5CCF, 0x8D58, 0x5CD0, 0x8D59, 0x5CD1, 0x8D5A, 0x5CD2, 0xE1BC,
+	0x5CD3, 0x8D5B, 0x5CD4, 0x8D5C, 0x5CD5, 0x8D5D, 0x5CD6, 0x8D5E,	0x5CD7, 0x8D5F, 0x5CD8, 0x8D60, 0x5CD9, 0xD6C5, 0x5CDA, 0x8D61,
+	0x5CDB, 0x8D62, 0x5CDC, 0x8D63, 0x5CDD, 0x8D64, 0x5CDE, 0x8D65,	0x5CDF, 0x8D66, 0x5CE0, 0x8D67, 0x5CE1, 0xCFBF, 0x5CE2, 0x8D68,
+	0x5CE3, 0x8D69, 0x5CE4, 0xE1BD, 0x5CE5, 0xE1BF, 0x5CE6, 0xC2CD,	0x5CE7, 0x8D6A, 0x5CE8, 0xB6EB, 0x5CE9, 0x8D6B, 0x5CEA, 0xD3F8,
+	0x5CEB, 0x8D6C, 0x5CEC, 0x8D6D, 0x5CED, 0xC7CD, 0x5CEE, 0x8D6E,	0x5CEF, 0x8D6F, 0x5CF0, 0xB7E5, 0x5CF1, 0x8D70, 0x5CF2, 0x8D71,
+	0x5CF3, 0x8D72, 0x5CF4, 0x8D73, 0x5CF5, 0x8D74, 0x5CF6, 0x8D75,	0x5CF7, 0x8D76, 0x5CF8, 0x8D77, 0x5CF9, 0x8D78, 0x5CFA, 0x8D79,
+	0x5CFB, 0xBEFE, 0x5CFC, 0x8D7A, 0x5CFD, 0x8D7B, 0x5CFE, 0x8D7C,	0x5CFF, 0x8D7D, 0x5D00, 0x8D7E, 0x5D01, 0x8D80, 0x5D02, 0xE1C0,
+	0x5D03, 0xE1C1, 0x5D04, 0x8D81, 0x5D05, 0x8D82, 0x5D06, 0xE1C7,	0x5D07, 0xB3E7, 0x5D08, 0x8D83, 0x5D09, 0x8D84, 0x5D0A, 0x8D85,
+	0x5D0B, 0x8D86, 0x5D0C, 0x8D87, 0x5D0D, 0x8D88, 0x5D0E, 0xC6E9,	0x5D0F, 0x8D89, 0x5D10, 0x8D8A, 0x5D11, 0x8D8B, 0x5D12, 0x8D8C,
+	0x5D13, 0x8D8D, 0x5D14, 0xB4DE, 0x5D15, 0x8D8E, 0x5D16, 0xD1C2,	0x5D17, 0x8D8F, 0x5D18, 0x8D90, 0x5D19, 0x8D91, 0x5D1A, 0x8D92,
+	0x5D1B, 0xE1C8, 0x5D1C, 0x8D93, 0x5D1D, 0x8D94, 0x5D1E, 0xE1C6,	0x5D1F, 0x8D95, 0x5D20, 0x8D96, 0x5D21, 0x8D97, 0x5D22, 0x8D98,
+	0x5D23, 0x8D99, 0x5D24, 0xE1C5, 0x5D25, 0x8D9A, 0x5D26, 0xE1C3,	0x5D27, 0xE1C2, 0x5D28, 0x8D9B, 0x5D29, 0xB1C0, 0x5D2A, 0x8D9C,
+	0x5D2B, 0x8D9D, 0x5D2C, 0x8D9E, 0x5D2D, 0xD5B8, 0x5D2E, 0xE1C4,	0x5D2F, 0x8D9F, 0x5D30, 0x8DA0, 0x5D31, 0x8DA1, 0x5D32, 0x8DA2,
+	0x5D33, 0x8DA3, 0x5D34, 0xE1CB, 0x5D35, 0x8DA4, 0x5D36, 0x8DA5,	0x5D37, 0x8DA6, 0x5D38, 0x8DA7, 0x5D39, 0x8DA8, 0x5D3A, 0x8DA9,
+	0x5D3B, 0x8DAA, 0x5D3C, 0x8DAB, 0x5D3D, 0xE1CC, 0x5D3E, 0xE1CA,	0x5D3F, 0x8DAC, 0x5D40, 0x8DAD, 0x5D41, 0x8DAE, 0x5D42, 0x8DAF,
+	0x5D43, 0x8DB0, 0x5D44, 0x8DB1, 0x5D45, 0x8DB2, 0x5D46, 0x8DB3,	0x5D47, 0xEFFA, 0x5D48, 0x8DB4, 0x5D49, 0x8DB5, 0x5D4A, 0xE1D3,
+	0x5D4B, 0xE1D2, 0x5D4C, 0xC7B6, 0x5D4D, 0x8DB6, 0x5D4E, 0x8DB7,	0x5D4F, 0x8DB8, 0x5D50, 0x8DB9, 0x5D51, 0x8DBA, 0x5D52, 0x8DBB,
+	0x5D53, 0x8DBC, 0x5D54, 0x8DBD, 0x5D55, 0x8DBE, 0x5D56, 0x8DBF,	0x5D57, 0x8DC0, 0x5D58, 0xE1C9, 0x5D59, 0x8DC1, 0x5D5A, 0x8DC2,
+	0x5D5B, 0xE1CE, 0x5D5C, 0x8DC3, 0x5D5D, 0xE1D0, 0x5D5E, 0x8DC4,	0x5D5F, 0x8DC5, 0x5D60, 0x8DC6, 0x5D61, 0x8DC7, 0x5D62, 0x8DC8,
+	0x5D63, 0x8DC9, 0x5D64, 0x8DCA, 0x5D65, 0x8DCB, 0x5D66, 0x8DCC,	0x5D67, 0x8DCD, 0x5D68, 0x8DCE, 0x5D69, 0xE1D4, 0x5D6A, 0x8DCF,
+	0x5D6B, 0xE1D1, 0x5D6C, 0xE1CD, 0x5D6D, 0x8DD0, 0x5D6E, 0x8DD1,	0x5D6F, 0xE1CF, 0x5D70, 0x8DD2, 0x5D71, 0x8DD3, 0x5D72, 0x8DD4,
+	0x5D73, 0x8DD5, 0x5D74, 0xE1D5, 0x5D75, 0x8DD6, 0x5D76, 0x8DD7,	0x5D77, 0x8DD8, 0x5D78, 0x8DD9, 0x5D79, 0x8DDA, 0x5D7A, 0x8DDB,
+	0x5D7B, 0x8DDC, 0x5D7C, 0x8DDD, 0x5D7D, 0x8DDE, 0x5D7E, 0x8DDF,	0x5D7F, 0x8DE0, 0x5D80, 0x8DE1, 0x5D81, 0x8DE2, 0x5D82, 0xE1D6,
+	0x5D83, 0x8DE3, 0x5D84, 0x8DE4, 0x5D85, 0x8DE5, 0x5D86, 0x8DE6,	0x5D87, 0x8DE7, 0x5D88, 0x8DE8, 0x5D89, 0x8DE9, 0x5D8A, 0x8DEA,
+	0x5D8B, 0x8DEB, 0x5D8C, 0x8DEC, 0x5D8D, 0x8DED, 0x5D8E, 0x8DEE,	0x5D8F, 0x8DEF, 0x5D90, 0x8DF0, 0x5D91, 0x8DF1, 0x5D92, 0x8DF2,
+	0x5D93, 0x8DF3, 0x5D94, 0x8DF4, 0x5D95, 0x8DF5, 0x5D96, 0x8DF6,	0x5D97, 0x8DF7, 0x5D98, 0x8DF8, 0x5D99, 0xE1D7, 0x5D9A, 0x8DF9,
+	0x5D9B, 0x8DFA, 0x5D9C, 0x8DFB, 0x5D9D, 0xE1D8, 0x5D9E, 0x8DFC,	0x5D9F, 0x8DFD, 0x5DA0, 0x8DFE, 0x5DA1, 0x8E40, 0x5DA2, 0x8E41,
+	0x5DA3, 0x8E42, 0x5DA4, 0x8E43, 0x5DA5, 0x8E44, 0x5DA6, 0x8E45,	0x5DA7, 0x8E46, 0x5DA8, 0x8E47, 0x5DA9, 0x8E48, 0x5DAA, 0x8E49,
+	0x5DAB, 0x8E4A, 0x5DAC, 0x8E4B, 0x5DAD, 0x8E4C, 0x5DAE, 0x8E4D,	0x5DAF, 0x8E4E, 0x5DB0, 0x8E4F, 0x5DB1, 0x8E50, 0x5DB2, 0x8E51,
+	0x5DB3, 0x8E52, 0x5DB4, 0x8E53, 0x5DB5, 0x8E54, 0x5DB6, 0x8E55,	0x5DB7, 0xE1DA, 0x5DB8, 0x8E56, 0x5DB9, 0x8E57, 0x5DBA, 0x8E58,
+	0x5DBB, 0x8E59, 0x5DBC, 0x8E5A, 0x5DBD, 0x8E5B, 0x5DBE, 0x8E5C,	0x5DBF, 0x8E5D, 0x5DC0, 0x8E5E, 0x5DC1, 0x8E5F, 0x5DC2, 0x8E60,
+	0x5DC3, 0x8E61, 0x5DC4, 0x8E62, 0x5DC5, 0xE1DB, 0x5DC6, 0x8E63,	0x5DC7, 0x8E64, 0x5DC8, 0x8E65, 0x5DC9, 0x8E66, 0x5DCA, 0x8E67,
+	0x5DCB, 0x8E68, 0x5DCC, 0x8E69, 0x5DCD, 0xCEA1, 0x5DCE, 0x8E6A,	0x5DCF, 0x8E6B, 0x5DD0, 0x8E6C, 0x5DD1, 0x8E6D, 0x5DD2, 0x8E6E,
+	0x5DD3, 0x8E6F, 0x5DD4, 0x8E70, 0x5DD5, 0x8E71, 0x5DD6, 0x8E72,	0x5DD7, 0x8E73, 0x5DD8, 0x8E74, 0x5DD9, 0x8E75, 0x5DDA, 0x8E76,
+	0x5DDB, 0xE7DD, 0x5DDC, 0x8E77, 0x5DDD, 0xB4A8, 0x5DDE, 0xD6DD,	0x5DDF, 0x8E78, 0x5DE0, 0x8E79, 0x5DE1, 0xD1B2, 0x5DE2, 0xB3B2,
+	0x5DE3, 0x8E7A, 0x5DE4, 0x8E7B, 0x5DE5, 0xB9A4, 0x5DE6, 0xD7F3,	0x5DE7, 0xC7C9, 0x5DE8, 0xBEDE, 0x5DE9, 0xB9AE, 0x5DEA, 0x8E7C,
+	0x5DEB, 0xCED7, 0x5DEC, 0x8E7D, 0x5DED, 0x8E7E, 0x5DEE, 0xB2EE,	0x5DEF, 0xDBCF, 0x5DF0, 0x8E80, 0x5DF1, 0xBCBA, 0x5DF2, 0xD2D1,
+	0x5DF3, 0xCBC8, 0x5DF4, 0xB0CD, 0x5DF5, 0x8E81, 0x5DF6, 0x8E82,	0x5DF7, 0xCFEF, 0x5DF8, 0x8E83, 0x5DF9, 0x8E84, 0x5DFA, 0x8E85,
+	0x5DFB, 0x8E86, 0x5DFC, 0x8E87, 0x5DFD, 0xD9E3, 0x5DFE, 0xBDED,	0x5DFF, 0x8E88, 0x5E00, 0x8E89, 0x5E01, 0xB1D2, 0x5E02, 0xCAD0,
+	0x5E03, 0xB2BC, 0x5E04, 0x8E8A, 0x5E05, 0xCBA7, 0x5E06, 0xB7AB,	0x5E07, 0x8E8B, 0x5E08, 0xCAA6, 0x5E09, 0x8E8C, 0x5E0A, 0x8E8D,
+	0x5E0B, 0x8E8E, 0x5E0C, 0xCFA3, 0x5E0D, 0x8E8F, 0x5E0E, 0x8E90,	0x5E0F, 0xE0F8, 0x5E10, 0xD5CA, 0x5E11, 0xE0FB, 0x5E12, 0x8E91,
+	0x5E13, 0x8E92, 0x5E14, 0xE0FA, 0x5E15, 0xC5C1, 0x5E16, 0xCCFB,	0x5E17, 0x8E93, 0x5E18, 0xC1B1, 0x5E19, 0xE0F9, 0x5E1A, 0xD6E3,
+	0x5E1B, 0xB2AF, 0x5E1C, 0xD6C4, 0x5E1D, 0xB5DB, 0x5E1E, 0x8E94,	0x5E1F, 0x8E95, 0x5E20, 0x8E96, 0x5E21, 0x8E97, 0x5E22, 0x8E98,
+	0x5E23, 0x8E99, 0x5E24, 0x8E9A, 0x5E25, 0x8E9B, 0x5E26, 0xB4F8,	0x5E27, 0xD6A1, 0x5E28, 0x8E9C, 0x5E29, 0x8E9D, 0x5E2A, 0x8E9E,
+	0x5E2B, 0x8E9F, 0x5E2C, 0x8EA0, 0x5E2D, 0xCFAF, 0x5E2E, 0xB0EF,	0x5E2F, 0x8EA1, 0x5E30, 0x8EA2, 0x5E31, 0xE0FC, 0x5E32, 0x8EA3,
+	0x5E33, 0x8EA4, 0x5E34, 0x8EA5, 0x5E35, 0x8EA6, 0x5E36, 0x8EA7,	0x5E37, 0xE1A1, 0x5E38, 0xB3A3, 0x5E39, 0x8EA8, 0x5E3A, 0x8EA9,
+	0x5E3B, 0xE0FD, 0x5E3C, 0xE0FE, 0x5E3D, 0xC3B1, 0x5E3E, 0x8EAA,	0x5E3F, 0x8EAB, 0x5E40, 0x8EAC, 0x5E41, 0x8EAD, 0x5E42, 0xC3DD,
+	0x5E43, 0x8EAE, 0x5E44, 0xE1A2, 0x5E45, 0xB7F9, 0x5E46, 0x8EAF,	0x5E47, 0x8EB0, 0x5E48, 0x8EB1, 0x5E49, 0x8EB2, 0x5E4A, 0x8EB3,
+	0x5E4B, 0x8EB4, 0x5E4C, 0xBBCF, 0x5E4D, 0x8EB5, 0x5E4E, 0x8EB6,	0x5E4F, 0x8EB7, 0x5E50, 0x8EB8, 0x5E51, 0x8EB9, 0x5E52, 0x8EBA,
+	0x5E53, 0x8EBB, 0x5E54, 0xE1A3, 0x5E55, 0xC4BB, 0x5E56, 0x8EBC,	0x5E57, 0x8EBD, 0x5E58, 0x8EBE, 0x5E59, 0x8EBF, 0x5E5A, 0x8EC0,
+	0x5E5B, 0xE1A4, 0x5E5C, 0x8EC1, 0x5E5D, 0x8EC2, 0x5E5E, 0xE1A5,	0x5E5F, 0x8EC3, 0x5E60, 0x8EC4, 0x5E61, 0xE1A6, 0x5E62, 0xB4B1,
+	0x5E63, 0x8EC5, 0x5E64, 0x8EC6, 0x5E65, 0x8EC7, 0x5E66, 0x8EC8,	0x5E67, 0x8EC9, 0x5E68, 0x8ECA, 0x5E69, 0x8ECB, 0x5E6A, 0x8ECC,
+	0x5E6B, 0x8ECD, 0x5E6C, 0x8ECE, 0x5E6D, 0x8ECF, 0x5E6E, 0x8ED0,	0x5E6F, 0x8ED1, 0x5E70, 0x8ED2, 0x5E71, 0x8ED3, 0x5E72, 0xB8C9,
+	0x5E73, 0xC6BD, 0x5E74, 0xC4EA, 0x5E75, 0x8ED4, 0x5E76, 0xB2A2,	0x5E77, 0x8ED5, 0x5E78, 0xD0D2, 0x5E79, 0x8ED6, 0x5E7A, 0xE7DB,
+	0x5E7B, 0xBBC3, 0x5E7C, 0xD3D7, 0x5E7D, 0xD3C4, 0x5E7E, 0x8ED7,	0x5E7F, 0xB9E3, 0x5E80, 0xE2CF, 0x5E81, 0x8ED8, 0x5E82, 0x8ED9,
+	0x5E83, 0x8EDA, 0x5E84, 0xD7AF, 0x5E85, 0x8EDB, 0x5E86, 0xC7EC,	0x5E87, 0xB1D3, 0x5E88, 0x8EDC, 0x5E89, 0x8EDD, 0x5E8A, 0xB4B2,
+	0x5E8B, 0xE2D1, 0x5E8C, 0x8EDE, 0x5E8D, 0x8EDF, 0x5E8E, 0x8EE0,	0x5E8F, 0xD0F2, 0x5E90, 0xC2AE, 0x5E91, 0xE2D0, 0x5E92, 0x8EE1,
+	0x5E93, 0xBFE2, 0x5E94, 0xD3A6, 0x5E95, 0xB5D7, 0x5E96, 0xE2D2,	0x5E97, 0xB5EA, 0x5E98, 0x8EE2, 0x5E99, 0xC3ED, 0x5E9A, 0xB8FD,
+	0x5E9B, 0x8EE3, 0x5E9C, 0xB8AE, 0x5E9D, 0x8EE4, 0x5E9E, 0xC5D3,	0x5E9F, 0xB7CF, 0x5EA0, 0xE2D4, 0x5EA1, 0x8EE5, 0x5EA2, 0x8EE6,
+	0x5EA3, 0x8EE7, 0x5EA4, 0x8EE8, 0x5EA5, 0xE2D3, 0x5EA6, 0xB6C8,	0x5EA7, 0xD7F9, 0x5EA8, 0x8EE9, 0x5EA9, 0x8EEA, 0x5EAA, 0x8EEB,
+	0x5EAB, 0x8EEC, 0x5EAC, 0x8EED, 0x5EAD, 0xCDA5, 0x5EAE, 0x8EEE,	0x5EAF, 0x8EEF, 0x5EB0, 0x8EF0, 0x5EB1, 0x8EF1, 0x5EB2, 0x8EF2,
+	0x5EB3, 0xE2D8, 0x5EB4, 0x8EF3, 0x5EB5, 0xE2D6, 0x5EB6, 0xCAFC,	0x5EB7, 0xBFB5, 0x5EB8, 0xD3B9, 0x5EB9, 0xE2D5, 0x5EBA, 0x8EF4,
+	0x5EBB, 0x8EF5, 0x5EBC, 0x8EF6, 0x5EBD, 0x8EF7, 0x5EBE, 0xE2D7,	0x5EBF, 0x8EF8, 0x5EC0, 0x8EF9, 0x5EC1, 0x8EFA, 0x5EC2, 0x8EFB,
+	0x5EC3, 0x8EFC, 0x5EC4, 0x8EFD, 0x5EC5, 0x8EFE, 0x5EC6, 0x8F40,	0x5EC7, 0x8F41, 0x5EC8, 0x8F42, 0x5EC9, 0xC1AE, 0x5ECA, 0xC0C8,
+	0x5ECB, 0x8F43, 0x5ECC, 0x8F44, 0x5ECD, 0x8F45, 0x5ECE, 0x8F46,	0x5ECF, 0x8F47, 0x5ED0, 0x8F48, 0x5ED1, 0xE2DB, 0x5ED2, 0xE2DA,
+	0x5ED3, 0xC0AA, 0x5ED4, 0x8F49, 0x5ED5, 0x8F4A, 0x5ED6, 0xC1CE,	0x5ED7, 0x8F4B, 0x5ED8, 0x8F4C, 0x5ED9, 0x8F4D, 0x5EDA, 0x8F4E,
+	0x5EDB, 0xE2DC, 0x5EDC, 0x8F4F, 0x5EDD, 0x8F50, 0x5EDE, 0x8F51,	0x5EDF, 0x8F52, 0x5EE0, 0x8F53, 0x5EE1, 0x8F54, 0x5EE2, 0x8F55,
+	0x5EE3, 0x8F56, 0x5EE4, 0x8F57, 0x5EE5, 0x8F58, 0x5EE6, 0x8F59,	0x5EE7, 0x8F5A, 0x5EE8, 0xE2DD, 0x5EE9, 0x8F5B, 0x5EEA, 0xE2DE,
+	0x5EEB, 0x8F5C, 0x5EEC, 0x8F5D, 0x5EED, 0x8F5E, 0x5EEE, 0x8F5F,	0x5EEF, 0x8F60, 0x5EF0, 0x8F61, 0x5EF1, 0x8F62, 0x5EF2, 0x8F63,
+	0x5EF3, 0x8F64, 0x5EF4, 0xDBC8, 0x5EF5, 0x8F65, 0x5EF6, 0xD1D3,	0x5EF7, 0xCDA2, 0x5EF8, 0x8F66, 0x5EF9, 0x8F67, 0x5EFA, 0xBDA8,
+	0x5EFB, 0x8F68, 0x5EFC, 0x8F69, 0x5EFD, 0x8F6A, 0x5EFE, 0xDEC3,	0x5EFF, 0xD8A5, 0x5F00, 0xBFAA, 0x5F01, 0xDBCD, 0x5F02, 0xD2EC,
+	0x5F03, 0xC6FA, 0x5F04, 0xC5AA, 0x5F05, 0x8F6B, 0x5F06, 0x8F6C,	0x5F07, 0x8F6D, 0x5F08, 0xDEC4, 0x5F09, 0x8F6E, 0x5F0A, 0xB1D7,
+	0x5F0B, 0xDFAE, 0x5F0C, 0x8F6F, 0x5F0D, 0x8F70, 0x5F0E, 0x8F71,	0x5F0F, 0xCABD, 0x5F10, 0x8F72, 0x5F11, 0xDFB1, 0x5F12, 0x8F73,
+	0x5F13, 0xB9AD, 0x5F14, 0x8F74, 0x5F15, 0xD2FD, 0x5F16, 0x8F75,	0x5F17, 0xB8A5, 0x5F18, 0xBAEB, 0x5F19, 0x8F76, 0x5F1A, 0x8F77,
+	0x5F1B, 0xB3DA, 0x5F1C, 0x8F78, 0x5F1D, 0x8F79, 0x5F1E, 0x8F7A,	0x5F1F, 0xB5DC, 0x5F20, 0xD5C5, 0x5F21, 0x8F7B, 0x5F22, 0x8F7C,
+	0x5F23, 0x8F7D, 0x5F24, 0x8F7E, 0x5F25, 0xC3D6, 0x5F26, 0xCFD2,	0x5F27, 0xBBA1, 0x5F28, 0x8F80, 0x5F29, 0xE5F3, 0x5F2A, 0xE5F2,
+	0x5F2B, 0x8F81, 0x5F2C, 0x8F82, 0x5F2D, 0xE5F4, 0x5F2E, 0x8F83,	0x5F2F, 0xCDE4, 0x5F30, 0x8F84, 0x5F31, 0xC8F5, 0x5F32, 0x8F85,
+	0x5F33, 0x8F86, 0x5F34, 0x8F87, 0x5F35, 0x8F88, 0x5F36, 0x8F89,	0x5F37, 0x8F8A, 0x5F38, 0x8F8B, 0x5F39, 0xB5AF, 0x5F3A, 0xC7BF,
+	0x5F3B, 0x8F8C, 0x5F3C, 0xE5F6, 0x5F3D, 0x8F8D, 0x5F3E, 0x8F8E,	0x5F3F, 0x8F8F, 0x5F40, 0xECB0, 0x5F41, 0x8F90, 0x5F42, 0x8F91,
+	0x5F43, 0x8F92, 0x5F44, 0x8F93, 0x5F45, 0x8F94, 0x5F46, 0x8F95,	0x5F47, 0x8F96, 0x5F48, 0x8F97, 0x5F49, 0x8F98, 0x5F4A, 0x8F99,
+	0x5F4B, 0x8F9A, 0x5F4C, 0x8F9B, 0x5F4D, 0x8F9C, 0x5F4E, 0x8F9D,	0x5F4F, 0x8F9E, 0x5F50, 0xE5E6, 0x5F51, 0x8F9F, 0x5F52, 0xB9E9,
+	0x5F53, 0xB5B1, 0x5F54, 0x8FA0, 0x5F55, 0xC2BC, 0x5F56, 0xE5E8,	0x5F57, 0xE5E7, 0x5F58, 0xE5E9, 0x5F59, 0x8FA1, 0x5F5A, 0x8FA2,
+	0x5F5B, 0x8FA3, 0x5F5C, 0x8FA4, 0x5F5D, 0xD2CD, 0x5F5E, 0x8FA5,	0x5F5F, 0x8FA6, 0x5F60, 0x8FA7, 0x5F61, 0xE1EA, 0x5F62, 0xD0CE,
+	0x5F63, 0x8FA8, 0x5F64, 0xCDAE, 0x5F65, 0x8FA9, 0x5F66, 0xD1E5,	0x5F67, 0x8FAA, 0x5F68, 0x8FAB, 0x5F69, 0xB2CA, 0x5F6A, 0xB1EB,
+	0x5F6B, 0x8FAC, 0x5F6C, 0xB1F2, 0x5F6D, 0xC5ED, 0x5F6E, 0x8FAD,	0x5F6F, 0x8FAE, 0x5F70, 0xD5C3, 0x5F71, 0xD3B0, 0x5F72, 0x8FAF,
+	0x5F73, 0xE1DC, 0x5F74, 0x8FB0, 0x5F75, 0x8FB1, 0x5F76, 0x8FB2,	0x5F77, 0xE1DD, 0x5F78, 0x8FB3, 0x5F79, 0xD2DB, 0x5F7A, 0x8FB4,
+	0x5F7B, 0xB3B9, 0x5F7C, 0xB1CB, 0x5F7D, 0x8FB5, 0x5F7E, 0x8FB6,	0x5F7F, 0x8FB7, 0x5F80, 0xCDF9, 0x5F81, 0xD5F7, 0x5F82, 0xE1DE,
+	0x5F83, 0x8FB8, 0x5F84, 0xBEB6, 0x5F85, 0xB4FD, 0x5F86, 0x8FB9,	0x5F87, 0xE1DF, 0x5F88, 0xBADC, 0x5F89, 0xE1E0, 0x5F8A, 0xBBB2,
+	0x5F8B, 0xC2C9, 0x5F8C, 0xE1E1, 0x5F8D, 0x8FBA, 0x5F8E, 0x8FBB,	0x5F8F, 0x8FBC, 0x5F90, 0xD0EC, 0x5F91, 0x8FBD, 0x5F92, 0xCDBD,
+	0x5F93, 0x8FBE, 0x5F94, 0x8FBF, 0x5F95, 0xE1E2, 0x5F96, 0x8FC0,	0x5F97, 0xB5C3, 0x5F98, 0xC5C7, 0x5F99, 0xE1E3, 0x5F9A, 0x8FC1,
+	0x5F9B, 0x8FC2, 0x5F9C, 0xE1E4, 0x5F9D, 0x8FC3, 0x5F9E, 0x8FC4,	0x5F9F, 0x8FC5, 0x5FA0, 0x8FC6, 0x5FA1, 0xD3F9, 0x5FA2, 0x8FC7,
+	0x5FA3, 0x8FC8, 0x5FA4, 0x8FC9, 0x5FA5, 0x8FCA, 0x5FA6, 0x8FCB,	0x5FA7, 0x8FCC, 0x5FA8, 0xE1E5, 0x5FA9, 0x8FCD, 0x5FAA, 0xD1AD,
+	0x5FAB, 0x8FCE, 0x5FAC, 0x8FCF, 0x5FAD, 0xE1E6, 0x5FAE, 0xCEA2,	0x5FAF, 0x8FD0, 0x5FB0, 0x8FD1, 0x5FB1, 0x8FD2, 0x5FB2, 0x8FD3,
+	0x5FB3, 0x8FD4, 0x5FB4, 0x8FD5, 0x5FB5, 0xE1E7, 0x5FB6, 0x8FD6,	0x5FB7, 0xB5C2, 0x5FB8, 0x8FD7, 0x5FB9, 0x8FD8, 0x5FBA, 0x8FD9,
+	0x5FBB, 0x8FDA, 0x5FBC, 0xE1E8, 0x5FBD, 0xBBD5, 0x5FBE, 0x8FDB,	0x5FBF, 0x8FDC, 0x5FC0, 0x8FDD, 0x5FC1, 0x8FDE, 0x5FC2, 0x8FDF,
+	0x5FC3, 0xD0C4, 0x5FC4, 0xE2E0, 0x5FC5, 0xB1D8, 0x5FC6, 0xD2E4,	0x5FC7, 0x8FE0, 0x5FC8, 0x8FE1, 0x5FC9, 0xE2E1, 0x5FCA, 0x8FE2,
+	0x5FCB, 0x8FE3, 0x5FCC, 0xBCC9, 0x5FCD, 0xC8CC, 0x5FCE, 0x8FE4,	0x5FCF, 0xE2E3, 0x5FD0, 0xECFE, 0x5FD1, 0xECFD, 0x5FD2, 0xDFAF,
+	0x5FD3, 0x8FE5, 0x5FD4, 0x8FE6, 0x5FD5, 0x8FE7, 0x5FD6, 0xE2E2,	0x5FD7, 0xD6BE, 0x5FD8, 0xCDFC, 0x5FD9, 0xC3A6, 0x5FDA, 0x8FE8,
+	0x5FDB, 0x8FE9, 0x5FDC, 0x8FEA, 0x5FDD, 0xE3C3, 0x5FDE, 0x8FEB,	0x5FDF, 0x8FEC, 0x5FE0, 0xD6D2, 0x5FE1, 0xE2E7, 0x5FE2, 0x8FED,
+	0x5FE3, 0x8FEE, 0x5FE4, 0xE2E8, 0x5FE5, 0x8FEF, 0x5FE6, 0x8FF0,	0x5FE7, 0xD3C7, 0x5FE8, 0x8FF1, 0x5FE9, 0x8FF2, 0x5FEA, 0xE2EC,
+	0x5FEB, 0xBFEC, 0x5FEC, 0x8FF3, 0x5FED, 0xE2ED, 0x5FEE, 0xE2E5,	0x5FEF, 0x8FF4, 0x5FF0, 0x8FF5, 0x5FF1, 0xB3C0, 0x5FF2, 0x8FF6,
+	0x5FF3, 0x8FF7, 0x5FF4, 0x8FF8, 0x5FF5, 0xC4EE, 0x5FF6, 0x8FF9,	0x5FF7, 0x8FFA, 0x5FF8, 0xE2EE, 0x5FF9, 0x8FFB, 0x5FFA, 0x8FFC,
+	0x5FFB, 0xD0C3, 0x5FFC, 0x8FFD, 0x5FFD, 0xBAF6, 0x5FFE, 0xE2E9,	0x5FFF, 0xB7DE, 0x6000, 0xBBB3, 0x6001, 0xCCAC, 0x6002, 0xCBCB,
+	0x6003, 0xE2E4, 0x6004, 0xE2E6, 0x6005, 0xE2EA, 0x6006, 0xE2EB,	0x6007, 0x8FFE, 0x6008, 0x9040, 0x6009, 0x9041, 0x600A, 0xE2F7,
+	0x600B, 0x9042, 0x600C, 0x9043, 0x600D, 0xE2F4, 0x600E, 0xD4F5,	0x600F, 0xE2F3, 0x6010, 0x9044, 0x6011, 0x9045, 0x6012, 0xC5AD,
+	0x6013, 0x9046, 0x6014, 0xD5FA, 0x6015, 0xC5C2, 0x6016, 0xB2C0,	0x6017, 0x9047, 0x6018, 0x9048, 0x6019, 0xE2EF, 0x601A, 0x9049,
+	0x601B, 0xE2F2, 0x601C, 0xC1AF, 0x601D, 0xCBBC, 0x601E, 0x904A,	0x601F, 0x904B, 0x6020, 0xB5A1, 0x6021, 0xE2F9, 0x6022, 0x904C,
+	0x6023, 0x904D, 0x6024, 0x904E, 0x6025, 0xBCB1, 0x6026, 0xE2F1,	0x6027, 0xD0D4, 0x6028, 0xD4B9, 0x6029, 0xE2F5, 0x602A, 0xB9D6,
+	0x602B, 0xE2F6, 0x602C, 0x904F, 0x602D, 0x9050, 0x602E, 0x9051,	0x602F, 0xC7D3, 0x6030, 0x9052, 0x6031, 0x9053, 0x6032, 0x9054,
+	0x6033, 0x9055, 0x6034, 0x9056, 0x6035, 0xE2F0, 0x6036, 0x9057,	0x6037, 0x9058, 0x6038, 0x9059, 0x6039, 0x905A, 0x603A, 0x905B,
+	0x603B, 0xD7DC, 0x603C, 0xEDA1, 0x603D, 0x905C, 0x603E, 0x905D,	0x603F, 0xE2F8, 0x6040, 0x905E, 0x6041, 0xEDA5, 0x6042, 0xE2FE,
+	0x6043, 0xCAD1, 0x6044, 0x905F, 0x6045, 0x9060, 0x6046, 0x9061,	0x6047, 0x9062, 0x6048, 0x9063, 0x6049, 0x9064, 0x604A, 0x9065,
+	0x604B, 0xC1B5, 0x604C, 0x9066, 0x604D, 0xBBD0, 0x604E, 0x9067,	0x604F, 0x9068, 0x6050, 0xBFD6, 0x6051, 0x9069, 0x6052, 0xBAE3,
+	0x6053, 0x906A, 0x6054, 0x906B, 0x6055, 0xCBA1, 0x6056, 0x906C,	0x6057, 0x906D, 0x6058, 0x906E, 0x6059, 0xEDA6, 0x605A, 0xEDA3,
+	0x605B, 0x906F, 0x605C, 0x9070, 0x605D, 0xEDA2, 0x605E, 0x9071,	0x605F, 0x9072, 0x6060, 0x9073, 0x6061, 0x9074, 0x6062, 0xBBD6,
+	0x6063, 0xEDA7, 0x6064, 0xD0F4, 0x6065, 0x9075, 0x6066, 0x9076,	0x6067, 0xEDA4, 0x6068, 0xBADE, 0x6069, 0xB6F7, 0x606A, 0xE3A1,
+	0x606B, 0xB6B2, 0x606C, 0xCCF1, 0x606D, 0xB9A7, 0x606E, 0x9077,	0x606F, 0xCFA2, 0x6070, 0xC7A1, 0x6071, 0x9078, 0x6072, 0x9079,
+	0x6073, 0xBFD2, 0x6074, 0x907A, 0x6075, 0x907B, 0x6076, 0xB6F1,	0x6077, 0x907C, 0x6078, 0xE2FA, 0x6079, 0xE2FB, 0x607A, 0xE2FD,
+	0x607B, 0xE2FC, 0x607C, 0xC4D5, 0x607D, 0xE3A2, 0x607E, 0x907D,	0x607F, 0xD3C1, 0x6080, 0x907E, 0x6081, 0x9080, 0x6082, 0x9081,
+	0x6083, 0xE3A7, 0x6084, 0xC7C4, 0x6085, 0x9082, 0x6086, 0x9083,	0x6087, 0x9084, 0x6088, 0x9085, 0x6089, 0xCFA4, 0x608A, 0x9086,
+	0x608B, 0x9087, 0x608C, 0xE3A9, 0x608D, 0xBAB7, 0x608E, 0x9088,	0x608F, 0x9089, 0x6090, 0x908A, 0x6091, 0x908B, 0x6092, 0xE3A8,
+	0x6093, 0x908C, 0x6094, 0xBBDA, 0x6095, 0x908D, 0x6096, 0xE3A3,	0x6097, 0x908E, 0x6098, 0x908F, 0x6099, 0x9090, 0x609A, 0xE3A4,
+	0x609B, 0xE3AA, 0x609C, 0x9091, 0x609D, 0xE3A6, 0x609E, 0x9092,	0x609F, 0xCEF2, 0x60A0, 0xD3C6, 0x60A1, 0x9093, 0x60A2, 0x9094,
+	0x60A3, 0xBBBC, 0x60A4, 0x9095, 0x60A5, 0x9096, 0x60A6, 0xD4C3,	0x60A7, 0x9097, 0x60A8, 0xC4FA, 0x60A9, 0x9098, 0x60AA, 0x9099,
+	0x60AB, 0xEDA8, 0x60AC, 0xD0FC, 0x60AD, 0xE3A5, 0x60AE, 0x909A,	0x60AF, 0xC3F5, 0x60B0, 0x909B, 0x60B1, 0xE3AD, 0x60B2, 0xB1AF,
+	0x60B3, 0x909C, 0x60B4, 0xE3B2, 0x60B5, 0x909D, 0x60B6, 0x909E,	0x60B7, 0x909F, 0x60B8, 0xBCC2, 0x60B9, 0x90A0, 0x60BA, 0x90A1,
+	0x60BB, 0xE3AC, 0x60BC, 0xB5BF, 0x60BD, 0x90A2, 0x60BE, 0x90A3,	0x60BF, 0x90A4, 0x60C0, 0x90A5, 0x60C1, 0x90A6, 0x60C2, 0x90A7,
+	0x60C3, 0x90A8, 0x60C4, 0x90A9, 0x60C5, 0xC7E9, 0x60C6, 0xE3B0,	0x60C7, 0x90AA, 0x60C8, 0x90AB, 0x60C9, 0x90AC, 0x60CA, 0xBEAA,
+	0x60CB, 0xCDEF, 0x60CC, 0x90AD, 0x60CD, 0x90AE, 0x60CE, 0x90AF,	0x60CF, 0x90B0, 0x60D0, 0x90B1, 0x60D1, 0xBBF3, 0x60D2, 0x90B2,
+	0x60D3, 0x90B3, 0x60D4, 0x90B4, 0x60D5, 0xCCE8, 0x60D6, 0x90B5,	0x60D7, 0x90B6, 0x60D8, 0xE3AF, 0x60D9, 0x90B7, 0x60DA, 0xE3B1,
+	0x60DB, 0x90B8, 0x60DC, 0xCFA7, 0x60DD, 0xE3AE, 0x60DE, 0x90B9,	0x60DF, 0xCEA9, 0x60E0, 0xBBDD, 0x60E1, 0x90BA, 0x60E2, 0x90BB,
+	0x60E3, 0x90BC, 0x60E4, 0x90BD, 0x60E5, 0x90BE, 0x60E6, 0xB5EB,	0x60E7, 0xBEE5, 0x60E8, 0xB2D2, 0x60E9, 0xB3CD, 0x60EA, 0x90BF,
+	0x60EB, 0xB1B9, 0x60EC, 0xE3AB, 0x60ED, 0xB2D1, 0x60EE, 0xB5AC,	0x60EF, 0xB9DF, 0x60F0, 0xB6E8, 0x60F1, 0x90C0, 0x60F2, 0x90C1,
+	0x60F3, 0xCFEB, 0x60F4, 0xE3B7, 0x60F5, 0x90C2, 0x60F6, 0xBBCC,	0x60F7, 0x90C3, 0x60F8, 0x90C4, 0x60F9, 0xC8C7, 0x60FA, 0xD0CA,
+	0x60FB, 0x90C5, 0x60FC, 0x90C6, 0x60FD, 0x90C7, 0x60FE, 0x90C8,	0x60FF, 0x90C9, 0x6100, 0xE3B8, 0x6101, 0xB3EE, 0x6102, 0x90CA,
+	0x6103, 0x90CB, 0x6104, 0x90CC, 0x6105, 0x90CD, 0x6106, 0xEDA9,	0x6107, 0x90CE, 0x6108, 0xD3FA, 0x6109, 0xD3E4, 0x610A, 0x90CF,
+	0x610B, 0x90D0, 0x610C, 0x90D1, 0x610D, 0xEDAA, 0x610E, 0xE3B9,	0x610F, 0xD2E2, 0x6110, 0x90D2, 0x6111, 0x90D3, 0x6112, 0x90D4,
+	0x6113, 0x90D5, 0x6114, 0x90D6, 0x6115, 0xE3B5, 0x6116, 0x90D7,	0x6117, 0x90D8, 0x6118, 0x90D9, 0x6119, 0x90DA, 0x611A, 0xD3DE,
+	0x611B, 0x90DB, 0x611C, 0x90DC, 0x611D, 0x90DD, 0x611E, 0x90DE,	0x611F, 0xB8D0, 0x6120, 0xE3B3, 0x6121, 0x90DF, 0x6122, 0x90E0,
+	0x6123, 0xE3B6, 0x6124, 0xB7DF, 0x6125, 0x90E1, 0x6126, 0xE3B4,	0x6127, 0xC0A2, 0x6128, 0x90E2, 0x6129, 0x90E3, 0x612A, 0x90E4,
+	0x612B, 0xE3BA, 0x612C, 0x90E5, 0x612D, 0x90E6, 0x612E, 0x90E7,	0x612F, 0x90E8, 0x6130, 0x90E9, 0x6131, 0x90EA, 0x6132, 0x90EB,
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+	0x613B, 0x90F4, 0x613C, 0x90F5, 0x613D, 0x90F6, 0x613E, 0x90F7,	0x613F, 0xD4B8, 0x6140, 0x90F8, 0x6141, 0x90F9, 0x6142, 0x90FA,
+	0x6143, 0x90FB, 0x6144, 0x90FC, 0x6145, 0x90FD, 0x6146, 0x90FE,	0x6147, 0x9140, 0x6148, 0xB4C8, 0x6149, 0x9141, 0x614A, 0xE3BB,
+	0x614B, 0x9142, 0x614C, 0xBBC5, 0x614D, 0x9143, 0x614E, 0xC9F7,	0x614F, 0x9144, 0x6150, 0x9145, 0x6151, 0xC9E5, 0x6152, 0x9146,
+	0x6153, 0x9147, 0x6154, 0x9148, 0x6155, 0xC4BD, 0x6156, 0x9149,	0x6157, 0x914A, 0x6158, 0x914B, 0x6159, 0x914C, 0x615A, 0x914D,
+	0x615B, 0x914E, 0x615C, 0x914F, 0x615D, 0xEDAB, 0x615E, 0x9150,	0x615F, 0x9151, 0x6160, 0x9152, 0x6161, 0x9153, 0x6162, 0xC2FD,
+	0x6163, 0x9154, 0x6164, 0x9155, 0x6165, 0x9156, 0x6166, 0x9157,	0x6167, 0xBBDB, 0x6168, 0xBFAE, 0x6169, 0x9158, 0x616A, 0x9159,
+	0x616B, 0x915A, 0x616C, 0x915B, 0x616D, 0x915C, 0x616E, 0x915D,	0x616F, 0x915E, 0x6170, 0xCEBF, 0x6171, 0x915F, 0x6172, 0x9160,
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+	0x617B, 0x9167, 0x617C, 0x9168, 0x617D, 0x9169, 0x617E, 0x916A,	0x617F, 0x916B, 0x6180, 0x916C, 0x6181, 0x916D, 0x6182, 0x916E,
+	0x6183, 0x916F, 0x6184, 0x9170, 0x6185, 0x9171, 0x6186, 0x9172,	0x6187, 0x9173, 0x6188, 0x9174, 0x6189, 0x9175, 0x618A, 0x9176,
+	0x618B, 0xB1EF, 0x618C, 0x9177, 0x618D, 0x9178, 0x618E, 0xD4F7,	0x618F, 0x9179, 0x6190, 0x917A, 0x6191, 0x917B, 0x6192, 0x917C,
+	0x6193, 0x917D, 0x6194, 0xE3BE, 0x6195, 0x917E, 0x6196, 0x9180,	0x6197, 0x9181, 0x6198, 0x9182, 0x6199, 0x9183, 0x619A, 0x9184,
+	0x619B, 0x9185, 0x619C, 0x9186, 0x619D, 0xEDAD, 0x619E, 0x9187,	0x619F, 0x9188, 0x61A0, 0x9189, 0x61A1, 0x918A, 0x61A2, 0x918B,
+	0x61A3, 0x918C, 0x61A4, 0x918D, 0x61A5, 0x918E, 0x61A6, 0x918F,	0x61A7, 0xE3BF, 0x61A8, 0xBAA9, 0x61A9, 0xEDAC, 0x61AA, 0x9190,
+	0x61AB, 0x9191, 0x61AC, 0xE3BD, 0x61AD, 0x9192, 0x61AE, 0x9193,	0x61AF, 0x9194, 0x61B0, 0x9195, 0x61B1, 0x9196, 0x61B2, 0x9197,
+	0x61B3, 0x9198, 0x61B4, 0x9199, 0x61B5, 0x919A, 0x61B6, 0x919B,	0x61B7, 0xE3C0, 0x61B8, 0x919C, 0x61B9, 0x919D, 0x61BA, 0x919E,
+	0x61BB, 0x919F, 0x61BC, 0x91A0, 0x61BD, 0x91A1, 0x61BE, 0xBAB6,	0x61BF, 0x91A2, 0x61C0, 0x91A3, 0x61C1, 0x91A4, 0x61C2, 0xB6AE,
+	0x61C3, 0x91A5, 0x61C4, 0x91A6, 0x61C5, 0x91A7, 0x61C6, 0x91A8,	0x61C7, 0x91A9, 0x61C8, 0xD0B8, 0x61C9, 0x91AA, 0x61CA, 0xB0C3,
+	0x61CB, 0xEDAE, 0x61CC, 0x91AB, 0x61CD, 0x91AC, 0x61CE, 0x91AD,	0x61CF, 0x91AE, 0x61D0, 0x91AF, 0x61D1, 0xEDAF, 0x61D2, 0xC0C1,
+	0x61D3, 0x91B0, 0x61D4, 0xE3C1, 0x61D5, 0x91B1, 0x61D6, 0x91B2,	0x61D7, 0x91B3, 0x61D8, 0x91B4, 0x61D9, 0x91B5, 0x61DA, 0x91B6,
+	0x61DB, 0x91B7, 0x61DC, 0x91B8, 0x61DD, 0x91B9, 0x61DE, 0x91BA,	0x61DF, 0x91BB, 0x61E0, 0x91BC, 0x61E1, 0x91BD, 0x61E2, 0x91BE,
+	0x61E3, 0x91BF, 0x61E4, 0x91C0, 0x61E5, 0x91C1, 0x61E6, 0xC5B3,	0x61E7, 0x91C2, 0x61E8, 0x91C3, 0x61E9, 0x91C4, 0x61EA, 0x91C5,
+	0x61EB, 0x91C6, 0x61EC, 0x91C7, 0x61ED, 0x91C8, 0x61EE, 0x91C9,	0x61EF, 0x91CA, 0x61F0, 0x91CB, 0x61F1, 0x91CC, 0x61F2, 0x91CD,
+	0x61F3, 0x91CE, 0x61F4, 0x91CF, 0x61F5, 0xE3C2, 0x61F6, 0x91D0,	0x61F7, 0x91D1, 0x61F8, 0x91D2, 0x61F9, 0x91D3, 0x61FA, 0x91D4,
+	0x61FB, 0x91D5, 0x61FC, 0x91D6, 0x61FD, 0x91D7, 0x61FE, 0x91D8,	0x61FF, 0xDCB2, 0x6200, 0x91D9, 0x6201, 0x91DA, 0x6202, 0x91DB,
+	0x6203, 0x91DC, 0x6204, 0x91DD, 0x6205, 0x91DE, 0x6206, 0xEDB0,	0x6207, 0x91DF, 0x6208, 0xB8EA, 0x6209, 0x91E0, 0x620A, 0xCEEC,
+	0x620B, 0xEAA7, 0x620C, 0xD0E7, 0x620D, 0xCAF9, 0x620E, 0xC8D6,	0x620F, 0xCFB7, 0x6210, 0xB3C9, 0x6211, 0xCED2, 0x6212, 0xBDE4,
+	0x6213, 0x91E1, 0x6214, 0x91E2, 0x6215, 0xE3DE, 0x6216, 0xBBF2,	0x6217, 0xEAA8, 0x6218, 0xD5BD, 0x6219, 0x91E3, 0x621A, 0xC6DD,
+	0x621B, 0xEAA9, 0x621C, 0x91E4, 0x621D, 0x91E5, 0x621E, 0x91E6,	0x621F, 0xEAAA, 0x6220, 0x91E7, 0x6221, 0xEAAC, 0x6222, 0xEAAB,
+	0x6223, 0x91E8, 0x6224, 0xEAAE, 0x6225, 0xEAAD, 0x6226, 0x91E9,	0x6227, 0x91EA, 0x6228, 0x91EB, 0x6229, 0x91EC, 0x622A, 0xBDD8,
+	0x622B, 0x91ED, 0x622C, 0xEAAF, 0x622D, 0x91EE, 0x622E, 0xC2BE,	0x622F, 0x91EF, 0x6230, 0x91F0, 0x6231, 0x91F1, 0x6232, 0x91F2,
+	0x6233, 0xB4C1, 0x6234, 0xB4F7, 0x6235, 0x91F3, 0x6236, 0x91F4,	0x6237, 0xBBA7, 0x6238, 0x91F5, 0x6239, 0x91F6, 0x623A, 0x91F7,
+	0x623B, 0x91F8, 0x623C, 0x91F9, 0x623D, 0xECE6, 0x623E, 0xECE5,	0x623F, 0xB7BF, 0x6240, 0xCBF9, 0x6241, 0xB1E2, 0x6242, 0x91FA,
+	0x6243, 0xECE7, 0x6244, 0x91FB, 0x6245, 0x91FC, 0x6246, 0x91FD,	0x6247, 0xC9C8, 0x6248, 0xECE8, 0x6249, 0xECE9, 0x624A, 0x91FE,
+	0x624B, 0xCAD6, 0x624C, 0xDED0, 0x624D, 0xB2C5, 0x624E, 0xD4FA,	0x624F, 0x9240, 0x6250, 0x9241, 0x6251, 0xC6CB, 0x6252, 0xB0C7,
+	0x6253, 0xB4F2, 0x6254, 0xC8D3, 0x6255, 0x9242, 0x6256, 0x9243,	0x6257, 0x9244, 0x6258, 0xCDD0, 0x6259, 0x9245, 0x625A, 0x9246,
+	0x625B, 0xBFB8, 0x625C, 0x9247, 0x625D, 0x9248, 0x625E, 0x9249,	0x625F, 0x924A, 0x6260, 0x924B, 0x6261, 0x924C, 0x6262, 0x924D,
+	0x6263, 0xBFDB, 0x6264, 0x924E, 0x6265, 0x924F, 0x6266, 0xC7A4,	0x6267, 0xD6B4, 0x6268, 0x9250, 0x6269, 0xC0A9, 0x626A, 0xDED1,
+	0x626B, 0xC9A8, 0x626C, 0xD1EF, 0x626D, 0xC5A4, 0x626E, 0xB0E7,	0x626F, 0xB3B6, 0x6270, 0xC8C5, 0x6271, 0x9251, 0x6272, 0x9252,
+	0x6273, 0xB0E2, 0x6274, 0x9253, 0x6275, 0x9254, 0x6276, 0xB7F6,	0x6277, 0x9255, 0x6278, 0x9256, 0x6279, 0xC5FA, 0x627A, 0x9257,
+	0x627B, 0x9258, 0x627C, 0xB6F3, 0x627D, 0x9259, 0x627E, 0xD5D2,	0x627F, 0xB3D0, 0x6280, 0xBCBC, 0x6281, 0x925A, 0x6282, 0x925B,
+	0x6283, 0x925C, 0x6284, 0xB3AD, 0x6285, 0x925D, 0x6286, 0x925E,	0x6287, 0x925F, 0x6288, 0x9260, 0x6289, 0xBEF1, 0x628A, 0xB0D1,
+	0x628B, 0x9261, 0x628C, 0x9262, 0x628D, 0x9263, 0x628E, 0x9264,	0x628F, 0x9265, 0x6290, 0x9266, 0x6291, 0xD2D6, 0x6292, 0xCAE3,
+	0x6293, 0xD7A5, 0x6294, 0x9267, 0x6295, 0xCDB6, 0x6296, 0xB6B6,	0x6297, 0xBFB9, 0x6298, 0xD5DB, 0x6299, 0x9268, 0x629A, 0xB8A7,
+	0x629B, 0xC5D7, 0x629C, 0x9269, 0x629D, 0x926A, 0x629E, 0x926B,	0x629F, 0xDED2, 0x62A0, 0xBFD9, 0x62A1, 0xC2D5, 0x62A2, 0xC7C0,
+	0x62A3, 0x926C, 0x62A4, 0xBBA4, 0x62A5, 0xB1A8, 0x62A6, 0x926D,	0x62A7, 0x926E, 0x62A8, 0xC5EA, 0x62A9, 0x926F, 0x62AA, 0x9270,
+	0x62AB, 0xC5FB, 0x62AC, 0xCCA7, 0x62AD, 0x9271, 0x62AE, 0x9272,	0x62AF, 0x9273, 0x62B0, 0x9274, 0x62B1, 0xB1A7, 0x62B2, 0x9275,
+	0x62B3, 0x9276, 0x62B4, 0x9277, 0x62B5, 0xB5D6, 0x62B6, 0x9278,	0x62B7, 0x9279, 0x62B8, 0x927A, 0x62B9, 0xC4A8, 0x62BA, 0x927B,
+	0x62BB, 0xDED3, 0x62BC, 0xD1BA, 0x62BD, 0xB3E9, 0x62BE, 0x927C,	0x62BF, 0xC3F2, 0x62C0, 0x927D, 0x62C1, 0x927E, 0x62C2, 0xB7F7,
+	0x62C3, 0x9280, 0x62C4, 0xD6F4, 0x62C5, 0xB5A3, 0x62C6, 0xB2F0,	0x62C7, 0xC4B4, 0x62C8, 0xC4E9, 0x62C9, 0xC0AD, 0x62CA, 0xDED4,
+	0x62CB, 0x9281, 0x62CC, 0xB0E8, 0x62CD, 0xC5C4, 0x62CE, 0xC1E0,	0x62CF, 0x9282, 0x62D0, 0xB9D5, 0x62D1, 0x9283, 0x62D2, 0xBEDC,
+	0x62D3, 0xCDD8, 0x62D4, 0xB0CE, 0x62D5, 0x9284, 0x62D6, 0xCDCF,	0x62D7, 0xDED6, 0x62D8, 0xBED0, 0x62D9, 0xD7BE, 0x62DA, 0xDED5,
+	0x62DB, 0xD5D0, 0x62DC, 0xB0DD, 0x62DD, 0x9285, 0x62DE, 0x9286,	0x62DF, 0xC4E2, 0x62E0, 0x9287, 0x62E1, 0x9288, 0x62E2, 0xC2A3,
+	0x62E3, 0xBCF0, 0x62E4, 0x9289, 0x62E5, 0xD3B5, 0x62E6, 0xC0B9,	0x62E7, 0xC5A1, 0x62E8, 0xB2A6, 0x62E9, 0xD4F1, 0x62EA, 0x928A,
+	0x62EB, 0x928B, 0x62EC, 0xC0A8, 0x62ED, 0xCAC3, 0x62EE, 0xDED7,	0x62EF, 0xD5FC, 0x62F0, 0x928C, 0x62F1, 0xB9B0, 0x62F2, 0x928D,
+	0x62F3, 0xC8AD, 0x62F4, 0xCBA9, 0x62F5, 0x928E, 0x62F6, 0xDED9,	0x62F7, 0xBFBD, 0x62F8, 0x928F, 0x62F9, 0x9290, 0x62FA, 0x9291,
+	0x62FB, 0x9292, 0x62FC, 0xC6B4, 0x62FD, 0xD7A7, 0x62FE, 0xCAB0,	0x62FF, 0xC4C3, 0x6300, 0x9293, 0x6301, 0xB3D6, 0x6302, 0xB9D2,
+	0x6303, 0x9294, 0x6304, 0x9295, 0x6305, 0x9296, 0x6306, 0x9297,	0x6307, 0xD6B8, 0x6308, 0xEAFC, 0x6309, 0xB0B4, 0x630A, 0x9298,
+	0x630B, 0x9299, 0x630C, 0x929A, 0x630D, 0x929B, 0x630E, 0xBFE6,	0x630F, 0x929C, 0x6310, 0x929D, 0x6311, 0xCCF4, 0x6312, 0x929E,
+	0x6313, 0x929F, 0x6314, 0x92A0, 0x6315, 0x92A1, 0x6316, 0xCDDA,	0x6317, 0x92A2, 0x6318, 0x92A3, 0x6319, 0x92A4, 0x631A, 0xD6BF,
+	0x631B, 0xC2CE, 0x631C, 0x92A5, 0x631D, 0xCECE, 0x631E, 0xCCA2,	0x631F, 0xD0AE, 0x6320, 0xC4D3, 0x6321, 0xB5B2, 0x6322, 0xDED8,
+	0x6323, 0xD5F5, 0x6324, 0xBCB7, 0x6325, 0xBBD3, 0x6326, 0x92A6,	0x6327, 0x92A7, 0x6328, 0xB0A4, 0x6329, 0x92A8, 0x632A, 0xC5B2,
+	0x632B, 0xB4EC, 0x632C, 0x92A9, 0x632D, 0x92AA, 0x632E, 0x92AB,	0x632F, 0xD5F1, 0x6330, 0x92AC, 0x6331, 0x92AD, 0x6332, 0xEAFD,
+	0x6333, 0x92AE, 0x6334, 0x92AF, 0x6335, 0x92B0, 0x6336, 0x92B1,	0x6337, 0x92B2, 0x6338, 0x92B3, 0x6339, 0xDEDA, 0x633A, 0xCDA6,
+	0x633B, 0x92B4, 0x633C, 0x92B5, 0x633D, 0xCDEC, 0x633E, 0x92B6,	0x633F, 0x92B7, 0x6340, 0x92B8, 0x6341, 0x92B9, 0x6342, 0xCEE6,
+	0x6343, 0xDEDC, 0x6344, 0x92BA, 0x6345, 0xCDB1, 0x6346, 0xC0A6,	0x6347, 0x92BB, 0x6348, 0x92BC, 0x6349, 0xD7BD, 0x634A, 0x92BD,
+	0x634B, 0xDEDB, 0x634C, 0xB0C6, 0x634D, 0xBAB4, 0x634E, 0xC9D3,	0x634F, 0xC4F3, 0x6350, 0xBEE8, 0x6351, 0x92BE, 0x6352, 0x92BF,
+	0x6353, 0x92C0, 0x6354, 0x92C1, 0x6355, 0xB2B6, 0x6356, 0x92C2,	0x6357, 0x92C3, 0x6358, 0x92C4, 0x6359, 0x92C5, 0x635A, 0x92C6,
+	0x635B, 0x92C7, 0x635C, 0x92C8, 0x635D, 0x92C9, 0x635E, 0xC0CC,	0x635F, 0xCBF0, 0x6360, 0x92CA, 0x6361, 0xBCF1, 0x6362, 0xBBBB,
+	0x6363, 0xB5B7, 0x6364, 0x92CB, 0x6365, 0x92CC, 0x6366, 0x92CD,	0x6367, 0xC5F5, 0x6368, 0x92CE, 0x6369, 0xDEE6, 0x636A, 0x92CF,
+	0x636B, 0x92D0, 0x636C, 0x92D1, 0x636D, 0xDEE3, 0x636E, 0xBEDD,	0x636F, 0x92D2, 0x6370, 0x92D3, 0x6371, 0xDEDF, 0x6372, 0x92D4,
+	0x6373, 0x92D5, 0x6374, 0x92D6, 0x6375, 0x92D7, 0x6376, 0xB4B7,	0x6377, 0xBDDD, 0x6378, 0x92D8, 0x6379, 0x92D9, 0x637A, 0xDEE0,
+	0x637B, 0xC4ED, 0x637C, 0x92DA, 0x637D, 0x92DB, 0x637E, 0x92DC,	0x637F, 0x92DD, 0x6380, 0xCFC6, 0x6381, 0x92DE, 0x6382, 0xB5E0,
+	0x6383, 0x92DF, 0x6384, 0x92E0, 0x6385, 0x92E1, 0x6386, 0x92E2,	0x6387, 0xB6DE, 0x6388, 0xCADA, 0x6389, 0xB5F4, 0x638A, 0xDEE5,
+	0x638B, 0x92E3, 0x638C, 0xD5C6, 0x638D, 0x92E4, 0x638E, 0xDEE1,	0x638F, 0xCCCD, 0x6390, 0xC6FE, 0x6391, 0x92E5, 0x6392, 0xC5C5,
+	0x6393, 0x92E6, 0x6394, 0x92E7, 0x6395, 0x92E8, 0x6396, 0xD2B4,	0x6397, 0x92E9, 0x6398, 0xBEF2, 0x6399, 0x92EA, 0x639A, 0x92EB,
+	0x639B, 0x92EC, 0x639C, 0x92ED, 0x639D, 0x92EE, 0x639E, 0x92EF,	0x639F, 0x92F0, 0x63A0, 0xC2D3, 0x63A1, 0x92F1, 0x63A2, 0xCCBD,
+	0x63A3, 0xB3B8, 0x63A4, 0x92F2, 0x63A5, 0xBDD3, 0x63A6, 0x92F3,	0x63A7, 0xBFD8, 0x63A8, 0xCDC6, 0x63A9, 0xD1DA, 0x63AA, 0xB4EB,
+	0x63AB, 0x92F4, 0x63AC, 0xDEE4, 0x63AD, 0xDEDD, 0x63AE, 0xDEE7,	0x63AF, 0x92F5, 0x63B0, 0xEAFE, 0x63B1, 0x92F6, 0x63B2, 0x92F7,
+	0x63B3, 0xC2B0, 0x63B4, 0xDEE2, 0x63B5, 0x92F8, 0x63B6, 0x92F9,	0x63B7, 0xD6C0, 0x63B8, 0xB5A7, 0x63B9, 0x92FA, 0x63BA, 0xB2F4,
+	0x63BB, 0x92FB, 0x63BC, 0xDEE8, 0x63BD, 0x92FC, 0x63BE, 0xDEF2,	0x63BF, 0x92FD, 0x63C0, 0x92FE, 0x63C1, 0x9340, 0x63C2, 0x9341,
+	0x63C3, 0x9342, 0x63C4, 0xDEED, 0x63C5, 0x9343, 0x63C6, 0xDEF1,	0x63C7, 0x9344, 0x63C8, 0x9345, 0x63C9, 0xC8E0, 0x63CA, 0x9346,
+	0x63CB, 0x9347, 0x63CC, 0x9348, 0x63CD, 0xD7E1, 0x63CE, 0xDEEF,	0x63CF, 0xC3E8, 0x63D0, 0xCCE1, 0x63D1, 0x9349, 0x63D2, 0xB2E5,
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+	0x6BEB, 0xBAC1, 0x6BEC, 0x9AC2, 0x6BED, 0x9AC3, 0x6BEE, 0x9AC4,	0x6BEF, 0xCCBA, 0x6BF0, 0x9AC5, 0x6BF1, 0x9AC6, 0x6BF2, 0x9AC7,
+	0x6BF3, 0xEBA5, 0x6BF4, 0x9AC8, 0x6BF5, 0xEBA7, 0x6BF6, 0x9AC9,	0x6BF7, 0x9ACA, 0x6BF8, 0x9ACB, 0x6BF9, 0xEBA8, 0x6BFA, 0x9ACC,
+	0x6BFB, 0x9ACD, 0x6BFC, 0x9ACE, 0x6BFD, 0xEBA6, 0x6BFE, 0x9ACF,	0x6BFF, 0x9AD0, 0x6C00, 0x9AD1, 0x6C01, 0x9AD2, 0x6C02, 0x9AD3,
+	0x6C03, 0x9AD4, 0x6C04, 0x9AD5, 0x6C05, 0xEBA9, 0x6C06, 0xEBAB,	0x6C07, 0xEBAA, 0x6C08, 0x9AD6, 0x6C09, 0x9AD7, 0x6C0A, 0x9AD8,
+	0x6C0B, 0x9AD9, 0x6C0C, 0x9ADA, 0x6C0D, 0xEBAC, 0x6C0E, 0x9ADB,	0x6C0F, 0xCACF, 0x6C10, 0xD8B5, 0x6C11, 0xC3F1, 0x6C12, 0x9ADC,
+	0x6C13, 0xC3A5, 0x6C14, 0xC6F8, 0x6C15, 0xEBAD, 0x6C16, 0xC4CA,	0x6C17, 0x9ADD, 0x6C18, 0xEBAE, 0x6C19, 0xEBAF, 0x6C1A, 0xEBB0,
+	0x6C1B, 0xB7D5, 0x6C1C, 0x9ADE, 0x6C1D, 0x9ADF, 0x6C1E, 0x9AE0,	0x6C1F, 0xB7FA, 0x6C20, 0x9AE1, 0x6C21, 0xEBB1, 0x6C22, 0xC7E2,
+	0x6C23, 0x9AE2, 0x6C24, 0xEBB3, 0x6C25, 0x9AE3, 0x6C26, 0xBAA4,	0x6C27, 0xD1F5, 0x6C28, 0xB0B1, 0x6C29, 0xEBB2, 0x6C2A, 0xEBB4,
+	0x6C2B, 0x9AE4, 0x6C2C, 0x9AE5, 0x6C2D, 0x9AE6, 0x6C2E, 0xB5AA,	0x6C2F, 0xC2C8, 0x6C30, 0xC7E8, 0x6C31, 0x9AE7, 0x6C32, 0xEBB5,
+	0x6C33, 0x9AE8, 0x6C34, 0xCBAE, 0x6C35, 0xE3DF, 0x6C36, 0x9AE9,	0x6C37, 0x9AEA, 0x6C38, 0xD3C0, 0x6C39, 0x9AEB, 0x6C3A, 0x9AEC,
+	0x6C3B, 0x9AED, 0x6C3C, 0x9AEE, 0x6C3D, 0xD9DB, 0x6C3E, 0x9AEF,	0x6C3F, 0x9AF0, 0x6C40, 0xCDA1, 0x6C41, 0xD6AD, 0x6C42, 0xC7F3,
+	0x6C43, 0x9AF1, 0x6C44, 0x9AF2, 0x6C45, 0x9AF3, 0x6C46, 0xD9E0,	0x6C47, 0xBBE3, 0x6C48, 0x9AF4, 0x6C49, 0xBABA, 0x6C4A, 0xE3E2,
+	0x6C4B, 0x9AF5, 0x6C4C, 0x9AF6, 0x6C4D, 0x9AF7, 0x6C4E, 0x9AF8,	0x6C4F, 0x9AF9, 0x6C50, 0xCFAB, 0x6C51, 0x9AFA, 0x6C52, 0x9AFB,
+	0x6C53, 0x9AFC, 0x6C54, 0xE3E0, 0x6C55, 0xC9C7, 0x6C56, 0x9AFD,	0x6C57, 0xBAB9, 0x6C58, 0x9AFE, 0x6C59, 0x9B40, 0x6C5A, 0x9B41,
+	0x6C5B, 0xD1B4, 0x6C5C, 0xE3E1, 0x6C5D, 0xC8EA, 0x6C5E, 0xB9AF,	0x6C5F, 0xBDAD, 0x6C60, 0xB3D8, 0x6C61, 0xCEDB, 0x6C62, 0x9B42,
+	0x6C63, 0x9B43, 0x6C64, 0xCCC0, 0x6C65, 0x9B44, 0x6C66, 0x9B45,	0x6C67, 0x9B46, 0x6C68, 0xE3E8, 0x6C69, 0xE3E9, 0x6C6A, 0xCDF4,
+	0x6C6B, 0x9B47, 0x6C6C, 0x9B48, 0x6C6D, 0x9B49, 0x6C6E, 0x9B4A,	0x6C6F, 0x9B4B, 0x6C70, 0xCCAD, 0x6C71, 0x9B4C, 0x6C72, 0xBCB3,
+	0x6C73, 0x9B4D, 0x6C74, 0xE3EA, 0x6C75, 0x9B4E, 0x6C76, 0xE3EB,	0x6C77, 0x9B4F, 0x6C78, 0x9B50, 0x6C79, 0xD0DA, 0x6C7A, 0x9B51,
+	0x6C7B, 0x9B52, 0x6C7C, 0x9B53, 0x6C7D, 0xC6FB, 0x6C7E, 0xB7DA,	0x6C7F, 0x9B54, 0x6C80, 0x9B55, 0x6C81, 0xC7DF, 0x6C82, 0xD2CA,
+	0x6C83, 0xCED6, 0x6C84, 0x9B56, 0x6C85, 0xE3E4, 0x6C86, 0xE3EC,	0x6C87, 0x9B57, 0x6C88, 0xC9F2, 0x6C89, 0xB3C1, 0x6C8A, 0x9B58,
+	0x6C8B, 0x9B59, 0x6C8C, 0xE3E7, 0x6C8D, 0x9B5A, 0x6C8E, 0x9B5B,	0x6C8F, 0xC6E3, 0x6C90, 0xE3E5, 0x6C91, 0x9B5C, 0x6C92, 0x9B5D,
+	0x6C93, 0xEDB3, 0x6C94, 0xE3E6, 0x6C95, 0x9B5E, 0x6C96, 0x9B5F,	0x6C97, 0x9B60, 0x6C98, 0x9B61, 0x6C99, 0xC9B3, 0x6C9A, 0x9B62,
+	0x6C9B, 0xC5E6, 0x6C9C, 0x9B63, 0x6C9D, 0x9B64, 0x6C9E, 0x9B65,	0x6C9F, 0xB9B5, 0x6CA0, 0x9B66, 0x6CA1, 0xC3BB, 0x6CA2, 0x9B67,
+	0x6CA3, 0xE3E3, 0x6CA4, 0xC5BD, 0x6CA5, 0xC1A4, 0x6CA6, 0xC2D9,	0x6CA7, 0xB2D7, 0x6CA8, 0x9B68, 0x6CA9, 0xE3ED, 0x6CAA, 0xBBA6,
+	0x6CAB, 0xC4AD, 0x6CAC, 0x9B69, 0x6CAD, 0xE3F0, 0x6CAE, 0xBEDA,	0x6CAF, 0x9B6A, 0x6CB0, 0x9B6B, 0x6CB1, 0xE3FB, 0x6CB2, 0xE3F5,
+	0x6CB3, 0xBAD3, 0x6CB4, 0x9B6C, 0x6CB5, 0x9B6D, 0x6CB6, 0x9B6E,	0x6CB7, 0x9B6F, 0x6CB8, 0xB7D0, 0x6CB9, 0xD3CD, 0x6CBA, 0x9B70,
+	0x6CBB, 0xD6CE, 0x6CBC, 0xD5D3, 0x6CBD, 0xB9C1, 0x6CBE, 0xD5B4,	0x6CBF, 0xD1D8, 0x6CC0, 0x9B71, 0x6CC1, 0x9B72, 0x6CC2, 0x9B73,
+	0x6CC3, 0x9B74, 0x6CC4, 0xD0B9, 0x6CC5, 0xC7F6, 0x6CC6, 0x9B75,	0x6CC7, 0x9B76, 0x6CC8, 0x9B77, 0x6CC9, 0xC8AA, 0x6CCA, 0xB2B4,
+	0x6CCB, 0x9B78, 0x6CCC, 0xC3DA, 0x6CCD, 0x9B79, 0x6CCE, 0x9B7A,	0x6CCF, 0x9B7B, 0x6CD0, 0xE3EE, 0x6CD1, 0x9B7C, 0x6CD2, 0x9B7D,
+	0x6CD3, 0xE3FC, 0x6CD4, 0xE3EF, 0x6CD5, 0xB7A8, 0x6CD6, 0xE3F7,	0x6CD7, 0xE3F4, 0x6CD8, 0x9B7E, 0x6CD9, 0x9B80, 0x6CDA, 0x9B81,
+	0x6CDB, 0xB7BA, 0x6CDC, 0x9B82, 0x6CDD, 0x9B83, 0x6CDE, 0xC5A2,	0x6CDF, 0x9B84, 0x6CE0, 0xE3F6, 0x6CE1, 0xC5DD, 0x6CE2, 0xB2A8,
+	0x6CE3, 0xC6FC, 0x6CE4, 0x9B85, 0x6CE5, 0xC4E0, 0x6CE6, 0x9B86,	0x6CE7, 0x9B87, 0x6CE8, 0xD7A2, 0x6CE9, 0x9B88, 0x6CEA, 0xC0E1,
+	0x6CEB, 0xE3F9, 0x6CEC, 0x9B89, 0x6CED, 0x9B8A, 0x6CEE, 0xE3FA,	0x6CEF, 0xE3FD, 0x6CF0, 0xCCA9, 0x6CF1, 0xE3F3, 0x6CF2, 0x9B8B,
+	0x6CF3, 0xD3BE, 0x6CF4, 0x9B8C, 0x6CF5, 0xB1C3, 0x6CF6, 0xEDB4,	0x6CF7, 0xE3F1, 0x6CF8, 0xE3F2, 0x6CF9, 0x9B8D, 0x6CFA, 0xE3F8,
+	0x6CFB, 0xD0BA, 0x6CFC, 0xC6C3, 0x6CFD, 0xD4F3, 0x6CFE, 0xE3FE,	0x6CFF, 0x9B8E, 0x6D00, 0x9B8F, 0x6D01, 0xBDE0, 0x6D02, 0x9B90,
+	0x6D03, 0x9B91, 0x6D04, 0xE4A7, 0x6D05, 0x9B92, 0x6D06, 0x9B93,	0x6D07, 0xE4A6, 0x6D08, 0x9B94, 0x6D09, 0x9B95, 0x6D0A, 0x9B96,
+	0x6D0B, 0xD1F3, 0x6D0C, 0xE4A3, 0x6D0D, 0x9B97, 0x6D0E, 0xE4A9,	0x6D0F, 0x9B98, 0x6D10, 0x9B99, 0x6D11, 0x9B9A, 0x6D12, 0xC8F7,
+	0x6D13, 0x9B9B, 0x6D14, 0x9B9C, 0x6D15, 0x9B9D, 0x6D16, 0x9B9E,	0x6D17, 0xCFB4, 0x6D18, 0x9B9F, 0x6D19, 0xE4A8, 0x6D1A, 0xE4AE,
+	0x6D1B, 0xC2E5, 0x6D1C, 0x9BA0, 0x6D1D, 0x9BA1, 0x6D1E, 0xB6B4,	0x6D1F, 0x9BA2, 0x6D20, 0x9BA3, 0x6D21, 0x9BA4, 0x6D22, 0x9BA5,
+	0x6D23, 0x9BA6, 0x6D24, 0x9BA7, 0x6D25, 0xBDF2, 0x6D26, 0x9BA8,	0x6D27, 0xE4A2, 0x6D28, 0x9BA9, 0x6D29, 0x9BAA, 0x6D2A, 0xBAE9,
+	0x6D2B, 0xE4AA, 0x6D2C, 0x9BAB, 0x6D2D, 0x9BAC, 0x6D2E, 0xE4AC,	0x6D2F, 0x9BAD, 0x6D30, 0x9BAE, 0x6D31, 0xB6FD, 0x6D32, 0xD6DE,
+	0x6D33, 0xE4B2, 0x6D34, 0x9BAF, 0x6D35, 0xE4AD, 0x6D36, 0x9BB0,	0x6D37, 0x9BB1, 0x6D38, 0x9BB2, 0x6D39, 0xE4A1, 0x6D3A, 0x9BB3,
+	0x6D3B, 0xBBEE, 0x6D3C, 0xCDDD, 0x6D3D, 0xC7A2, 0x6D3E, 0xC5C9,	0x6D3F, 0x9BB4, 0x6D40, 0x9BB5, 0x6D41, 0xC1F7, 0x6D42, 0x9BB6,
+	0x6D43, 0xE4A4, 0x6D44, 0x9BB7, 0x6D45, 0xC7B3, 0x6D46, 0xBDAC,	0x6D47, 0xBDBD, 0x6D48, 0xE4A5, 0x6D49, 0x9BB8, 0x6D4A, 0xD7C7,
+	0x6D4B, 0xB2E2, 0x6D4C, 0x9BB9, 0x6D4D, 0xE4AB, 0x6D4E, 0xBCC3,	0x6D4F, 0xE4AF, 0x6D50, 0x9BBA, 0x6D51, 0xBBEB, 0x6D52, 0xE4B0,
+	0x6D53, 0xC5A8, 0x6D54, 0xE4B1, 0x6D55, 0x9BBB, 0x6D56, 0x9BBC,	0x6D57, 0x9BBD, 0x6D58, 0x9BBE, 0x6D59, 0xD5E3, 0x6D5A, 0xBFA3,
+	0x6D5B, 0x9BBF, 0x6D5C, 0xE4BA, 0x6D5D, 0x9BC0, 0x6D5E, 0xE4B7,	0x6D5F, 0x9BC1, 0x6D60, 0xE4BB, 0x6D61, 0x9BC2, 0x6D62, 0x9BC3,
+	0x6D63, 0xE4BD, 0x6D64, 0x9BC4, 0x6D65, 0x9BC5, 0x6D66, 0xC6D6,	0x6D67, 0x9BC6, 0x6D68, 0x9BC7, 0x6D69, 0xBAC6, 0x6D6A, 0xC0CB,
+	0x6D6B, 0x9BC8, 0x6D6C, 0x9BC9, 0x6D6D, 0x9BCA, 0x6D6E, 0xB8A1,	0x6D6F, 0xE4B4, 0x6D70, 0x9BCB, 0x6D71, 0x9BCC, 0x6D72, 0x9BCD,
+	0x6D73, 0x9BCE, 0x6D74, 0xD4A1, 0x6D75, 0x9BCF, 0x6D76, 0x9BD0,	0x6D77, 0xBAA3, 0x6D78, 0xBDFE, 0x6D79, 0x9BD1, 0x6D7A, 0x9BD2,
+	0x6D7B, 0x9BD3, 0x6D7C, 0xE4BC, 0x6D7D, 0x9BD4, 0x6D7E, 0x9BD5,	0x6D7F, 0x9BD6, 0x6D80, 0x9BD7, 0x6D81, 0x9BD8, 0x6D82, 0xCDBF,
+	0x6D83, 0x9BD9, 0x6D84, 0x9BDA, 0x6D85, 0xC4F9, 0x6D86, 0x9BDB,	0x6D87, 0x9BDC, 0x6D88, 0xCFFB, 0x6D89, 0xC9E6, 0x6D8A, 0x9BDD,
+	0x6D8B, 0x9BDE, 0x6D8C, 0xD3BF, 0x6D8D, 0x9BDF, 0x6D8E, 0xCFD1,	0x6D8F, 0x9BE0, 0x6D90, 0x9BE1, 0x6D91, 0xE4B3, 0x6D92, 0x9BE2,
+	0x6D93, 0xE4B8, 0x6D94, 0xE4B9, 0x6D95, 0xCCE9, 0x6D96, 0x9BE3,	0x6D97, 0x9BE4, 0x6D98, 0x9BE5, 0x6D99, 0x9BE6, 0x6D9A, 0x9BE7,
+	0x6D9B, 0xCCCE, 0x6D9C, 0x9BE8, 0x6D9D, 0xC0D4, 0x6D9E, 0xE4B5,	0x6D9F, 0xC1B0, 0x6DA0, 0xE4B6, 0x6DA1, 0xCED0, 0x6DA2, 0x9BE9,
+	0x6DA3, 0xBBC1, 0x6DA4, 0xB5D3, 0x6DA5, 0x9BEA, 0x6DA6, 0xC8F3,	0x6DA7, 0xBDA7, 0x6DA8, 0xD5C7, 0x6DA9, 0xC9AC, 0x6DAA, 0xB8A2,
+	0x6DAB, 0xE4CA, 0x6DAC, 0x9BEB, 0x6DAD, 0x9BEC, 0x6DAE, 0xE4CC,	0x6DAF, 0xD1C4, 0x6DB0, 0x9BED, 0x6DB1, 0x9BEE, 0x6DB2, 0xD2BA,
+	0x6DB3, 0x9BEF, 0x6DB4, 0x9BF0, 0x6DB5, 0xBAAD, 0x6DB6, 0x9BF1,	0x6DB7, 0x9BF2, 0x6DB8, 0xBAD4, 0x6DB9, 0x9BF3, 0x6DBA, 0x9BF4,
+	0x6DBB, 0x9BF5, 0x6DBC, 0x9BF6, 0x6DBD, 0x9BF7, 0x6DBE, 0x9BF8,	0x6DBF, 0xE4C3, 0x6DC0, 0xB5ED, 0x6DC1, 0x9BF9, 0x6DC2, 0x9BFA,
+	0x6DC3, 0x9BFB, 0x6DC4, 0xD7CD, 0x6DC5, 0xE4C0, 0x6DC6, 0xCFFD,	0x6DC7, 0xE4BF, 0x6DC8, 0x9BFC, 0x6DC9, 0x9BFD, 0x6DCA, 0x9BFE,
+	0x6DCB, 0xC1DC, 0x6DCC, 0xCCCA, 0x6DCD, 0x9C40, 0x6DCE, 0x9C41,	0x6DCF, 0x9C42, 0x6DD0, 0x9C43, 0x6DD1, 0xCAE7, 0x6DD2, 0x9C44,
+	0x6DD3, 0x9C45, 0x6DD4, 0x9C46, 0x6DD5, 0x9C47, 0x6DD6, 0xC4D7,	0x6DD7, 0x9C48, 0x6DD8, 0xCCD4, 0x6DD9, 0xE4C8, 0x6DDA, 0x9C49,
+	0x6DDB, 0x9C4A, 0x6DDC, 0x9C4B, 0x6DDD, 0xE4C7, 0x6DDE, 0xE4C1,	0x6DDF, 0x9C4C, 0x6DE0, 0xE4C4, 0x6DE1, 0xB5AD, 0x6DE2, 0x9C4D,
+	0x6DE3, 0x9C4E, 0x6DE4, 0xD3D9, 0x6DE5, 0x9C4F, 0x6DE6, 0xE4C6,	0x6DE7, 0x9C50, 0x6DE8, 0x9C51, 0x6DE9, 0x9C52, 0x6DEA, 0x9C53,
+	0x6DEB, 0xD2F9, 0x6DEC, 0xB4E3, 0x6DED, 0x9C54, 0x6DEE, 0xBBB4,	0x6DEF, 0x9C55, 0x6DF0, 0x9C56, 0x6DF1, 0xC9EE, 0x6DF2, 0x9C57,
+	0x6DF3, 0xB4BE, 0x6DF4, 0x9C58, 0x6DF5, 0x9C59, 0x6DF6, 0x9C5A,	0x6DF7, 0xBBEC, 0x6DF8, 0x9C5B, 0x6DF9, 0xD1CD, 0x6DFA, 0x9C5C,
+	0x6DFB, 0xCCED, 0x6DFC, 0xEDB5, 0x6DFD, 0x9C5D, 0x6DFE, 0x9C5E,	0x6DFF, 0x9C5F, 0x6E00, 0x9C60, 0x6E01, 0x9C61, 0x6E02, 0x9C62,
+	0x6E03, 0x9C63, 0x6E04, 0x9C64, 0x6E05, 0xC7E5, 0x6E06, 0x9C65,	0x6E07, 0x9C66, 0x6E08, 0x9C67, 0x6E09, 0x9C68, 0x6E0A, 0xD4A8,
+	0x6E0B, 0x9C69, 0x6E0C, 0xE4CB, 0x6E0D, 0xD7D5, 0x6E0E, 0xE4C2,	0x6E0F, 0x9C6A, 0x6E10, 0xBDA5, 0x6E11, 0xE4C5, 0x6E12, 0x9C6B,
+	0x6E13, 0x9C6C, 0x6E14, 0xD3E6, 0x6E15, 0x9C6D, 0x6E16, 0xE4C9,	0x6E17, 0xC9F8, 0x6E18, 0x9C6E, 0x6E19, 0x9C6F, 0x6E1A, 0xE4BE,
+	0x6E1B, 0x9C70, 0x6E1C, 0x9C71, 0x6E1D, 0xD3E5, 0x6E1E, 0x9C72,	0x6E1F, 0x9C73, 0x6E20, 0xC7FE, 0x6E21, 0xB6C9, 0x6E22, 0x9C74,
+	0x6E23, 0xD4FC, 0x6E24, 0xB2B3, 0x6E25, 0xE4D7, 0x6E26, 0x9C75,	0x6E27, 0x9C76, 0x6E28, 0x9C77, 0x6E29, 0xCEC2, 0x6E2A, 0x9C78,
+	0x6E2B, 0xE4CD, 0x6E2C, 0x9C79, 0x6E2D, 0xCEBC, 0x6E2E, 0x9C7A,	0x6E2F, 0xB8DB, 0x6E30, 0x9C7B, 0x6E31, 0x9C7C, 0x6E32, 0xE4D6,
+	0x6E33, 0x9C7D, 0x6E34, 0xBFCA, 0x6E35, 0x9C7E, 0x6E36, 0x9C80,	0x6E37, 0x9C81, 0x6E38, 0xD3CE, 0x6E39, 0x9C82, 0x6E3A, 0xC3EC,
+	0x6E3B, 0x9C83, 0x6E3C, 0x9C84, 0x6E3D, 0x9C85, 0x6E3E, 0x9C86,	0x6E3F, 0x9C87, 0x6E40, 0x9C88, 0x6E41, 0x9C89, 0x6E42, 0x9C8A,
+	0x6E43, 0xC5C8, 0x6E44, 0xE4D8, 0x6E45, 0x9C8B, 0x6E46, 0x9C8C,	0x6E47, 0x9C8D, 0x6E48, 0x9C8E, 0x6E49, 0x9C8F, 0x6E4A, 0x9C90,
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+	0x764B, 0xB046, 0x764C, 0xB0A9, 0x764D, 0xF1AD, 0x764E, 0xB047,	0x764F, 0xB048, 0x7650, 0xB049, 0x7651, 0xB04A, 0x7652, 0xB04B,
+	0x7653, 0xB04C, 0x7654, 0xF1AF, 0x7655, 0xB04D, 0x7656, 0xF1B1,	0x7657, 0xB04E, 0x7658, 0xB04F, 0x7659, 0xB050, 0x765A, 0xB051,
+	0x765B, 0xB052, 0x765C, 0xF1B0, 0x765D, 0xB053, 0x765E, 0xF1AE,	0x765F, 0xB054, 0x7660, 0xB055, 0x7661, 0xB056, 0x7662, 0xB057,
+	0x7663, 0xD1A2, 0x7664, 0xB058, 0x7665, 0xB059, 0x7666, 0xB05A,	0x7667, 0xB05B, 0x7668, 0xB05C, 0x7669, 0xB05D, 0x766A, 0xB05E,
+	0x766B, 0xF1B2, 0x766C, 0xB05F, 0x766D, 0xB060, 0x766E, 0xB061,	0x766F, 0xF1B3, 0x7670, 0xB062, 0x7671, 0xB063, 0x7672, 0xB064,
+	0x7673, 0xB065, 0x7674, 0xB066, 0x7675, 0xB067, 0x7676, 0xB068,	0x7677, 0xB069, 0x7678, 0xB9EF, 0x7679, 0xB06A, 0x767A, 0xB06B,
+	0x767B, 0xB5C7, 0x767C, 0xB06C, 0x767D, 0xB0D7, 0x767E, 0xB0D9,	0x767F, 0xB06D, 0x7680, 0xB06E, 0x7681, 0xB06F, 0x7682, 0xD4ED,
+	0x7683, 0xB070, 0x7684, 0xB5C4, 0x7685, 0xB071, 0x7686, 0xBDD4,	0x7687, 0xBBCA, 0x7688, 0xF0A7, 0x7689, 0xB072, 0x768A, 0xB073,
+	0x768B, 0xB8DE, 0x768C, 0xB074, 0x768D, 0xB075, 0x768E, 0xF0A8,	0x768F, 0xB076, 0x7690, 0xB077, 0x7691, 0xB0A8, 0x7692, 0xB078,
+	0x7693, 0xF0A9, 0x7694, 0xB079, 0x7695, 0xB07A, 0x7696, 0xCDEE,	0x7697, 0xB07B, 0x7698, 0xB07C, 0x7699, 0xF0AA, 0x769A, 0xB07D,
+	0x769B, 0xB07E, 0x769C, 0xB080, 0x769D, 0xB081, 0x769E, 0xB082,	0x769F, 0xB083, 0x76A0, 0xB084, 0x76A1, 0xB085, 0x76A2, 0xB086,
+	0x76A3, 0xB087, 0x76A4, 0xF0AB, 0x76A5, 0xB088, 0x76A6, 0xB089,	0x76A7, 0xB08A, 0x76A8, 0xB08B, 0x76A9, 0xB08C, 0x76AA, 0xB08D,
+	0x76AB, 0xB08E, 0x76AC, 0xB08F, 0x76AD, 0xB090, 0x76AE, 0xC6A4,	0x76AF, 0xB091, 0x76B0, 0xB092, 0x76B1, 0xD6E5, 0x76B2, 0xF1E4,
+	0x76B3, 0xB093, 0x76B4, 0xF1E5, 0x76B5, 0xB094, 0x76B6, 0xB095,	0x76B7, 0xB096, 0x76B8, 0xB097, 0x76B9, 0xB098, 0x76BA, 0xB099,
+	0x76BB, 0xB09A, 0x76BC, 0xB09B, 0x76BD, 0xB09C, 0x76BE, 0xB09D,	0x76BF, 0xC3F3, 0x76C0, 0xB09E, 0x76C1, 0xB09F, 0x76C2, 0xD3DB,
+	0x76C3, 0xB0A0, 0x76C4, 0xB140, 0x76C5, 0xD6D1, 0x76C6, 0xC5E8,	0x76C7, 0xB141, 0x76C8, 0xD3AF, 0x76C9, 0xB142, 0x76CA, 0xD2E6,
+	0x76CB, 0xB143, 0x76CC, 0xB144, 0x76CD, 0xEEC1, 0x76CE, 0xB0BB,	0x76CF, 0xD5B5, 0x76D0, 0xD1CE, 0x76D1, 0xBCE0, 0x76D2, 0xBAD0,
+	0x76D3, 0xB145, 0x76D4, 0xBFF8, 0x76D5, 0xB146, 0x76D6, 0xB8C7,	0x76D7, 0xB5C1, 0x76D8, 0xC5CC, 0x76D9, 0xB147, 0x76DA, 0xB148,
+	0x76DB, 0xCAA2, 0x76DC, 0xB149, 0x76DD, 0xB14A, 0x76DE, 0xB14B,	0x76DF, 0xC3CB, 0x76E0, 0xB14C, 0x76E1, 0xB14D, 0x76E2, 0xB14E,
+	0x76E3, 0xB14F, 0x76E4, 0xB150, 0x76E5, 0xEEC2, 0x76E6, 0xB151,	0x76E7, 0xB152, 0x76E8, 0xB153, 0x76E9, 0xB154, 0x76EA, 0xB155,
+	0x76EB, 0xB156, 0x76EC, 0xB157, 0x76ED, 0xB158, 0x76EE, 0xC4BF,	0x76EF, 0xB6A2, 0x76F0, 0xB159, 0x76F1, 0xEDEC, 0x76F2, 0xC3A4,
+	0x76F3, 0xB15A, 0x76F4, 0xD6B1, 0x76F5, 0xB15B, 0x76F6, 0xB15C,	0x76F7, 0xB15D, 0x76F8, 0xCFE0, 0x76F9, 0xEDEF, 0x76FA, 0xB15E,
+	0x76FB, 0xB15F, 0x76FC, 0xC5CE, 0x76FD, 0xB160, 0x76FE, 0xB6DC,	0x76FF, 0xB161, 0x7700, 0xB162, 0x7701, 0xCAA1, 0x7702, 0xB163,
+	0x7703, 0xB164, 0x7704, 0xEDED, 0x7705, 0xB165, 0x7706, 0xB166,	0x7707, 0xEDF0, 0x7708, 0xEDF1, 0x7709, 0xC3BC, 0x770A, 0xB167,
+	0x770B, 0xBFB4, 0x770C, 0xB168, 0x770D, 0xEDEE, 0x770E, 0xB169,	0x770F, 0xB16A, 0x7710, 0xB16B, 0x7711, 0xB16C, 0x7712, 0xB16D,
+	0x7713, 0xB16E, 0x7714, 0xB16F, 0x7715, 0xB170, 0x7716, 0xB171,	0x7717, 0xB172, 0x7718, 0xB173, 0x7719, 0xEDF4, 0x771A, 0xEDF2,
+	0x771B, 0xB174, 0x771C, 0xB175, 0x771D, 0xB176, 0x771E, 0xB177,	0x771F, 0xD5E6, 0x7720, 0xC3DF, 0x7721, 0xB178, 0x7722, 0xEDF3,
+	0x7723, 0xB179, 0x7724, 0xB17A, 0x7725, 0xB17B, 0x7726, 0xEDF6,	0x7727, 0xB17C, 0x7728, 0xD5A3, 0x7729, 0xD1A3, 0x772A, 0xB17D,
+	0x772B, 0xB17E, 0x772C, 0xB180, 0x772D, 0xEDF5, 0x772E, 0xB181,	0x772F, 0xC3D0, 0x7730, 0xB182, 0x7731, 0xB183, 0x7732, 0xB184,
+	0x7733, 0xB185, 0x7734, 0xB186, 0x7735, 0xEDF7, 0x7736, 0xBFF4,	0x7737, 0xBEEC, 0x7738, 0xEDF8, 0x7739, 0xB187, 0x773A, 0xCCF7,
+	0x773B, 0xB188, 0x773C, 0xD1DB, 0x773D, 0xB189, 0x773E, 0xB18A,	0x773F, 0xB18B, 0x7740, 0xD7C5, 0x7741, 0xD5F6, 0x7742, 0xB18C,
+	0x7743, 0xEDFC, 0x7744, 0xB18D, 0x7745, 0xB18E, 0x7746, 0xB18F,	0x7747, 0xEDFB, 0x7748, 0xB190, 0x7749, 0xB191, 0x774A, 0xB192,
+	0x774B, 0xB193, 0x774C, 0xB194, 0x774D, 0xB195, 0x774E, 0xB196,	0x774F, 0xB197, 0x7750, 0xEDF9, 0x7751, 0xEDFA, 0x7752, 0xB198,
+	0x7753, 0xB199, 0x7754, 0xB19A, 0x7755, 0xB19B, 0x7756, 0xB19C,	0x7757, 0xB19D, 0x7758, 0xB19E, 0x7759, 0xB19F, 0x775A, 0xEDFD,
+	0x775B, 0xBEA6, 0x775C, 0xB1A0, 0x775D, 0xB240, 0x775E, 0xB241,	0x775F, 0xB242, 0x7760, 0xB243, 0x7761, 0xCBAF, 0x7762, 0xEEA1,
+	0x7763, 0xB6BD, 0x7764, 0xB244, 0x7765, 0xEEA2, 0x7766, 0xC4C0,	0x7767, 0xB245, 0x7768, 0xEDFE, 0x7769, 0xB246, 0x776A, 0xB247,
+	0x776B, 0xBDDE, 0x776C, 0xB2C7, 0x776D, 0xB248, 0x776E, 0xB249,	0x776F, 0xB24A, 0x7770, 0xB24B, 0x7771, 0xB24C, 0x7772, 0xB24D,
+	0x7773, 0xB24E, 0x7774, 0xB24F, 0x7775, 0xB250, 0x7776, 0xB251,	0x7777, 0xB252, 0x7778, 0xB253, 0x7779, 0xB6C3, 0x777A, 0xB254,
+	0x777B, 0xB255, 0x777C, 0xB256, 0x777D, 0xEEA5, 0x777E, 0xD8BA,	0x777F, 0xEEA3, 0x7780, 0xEEA6, 0x7781, 0xB257, 0x7782, 0xB258,
+	0x7783, 0xB259, 0x7784, 0xC3E9, 0x7785, 0xB3F2, 0x7786, 0xB25A,	0x7787, 0xB25B, 0x7788, 0xB25C, 0x7789, 0xB25D, 0x778A, 0xB25E,
+	0x778B, 0xB25F, 0x778C, 0xEEA7, 0x778D, 0xEEA4, 0x778E, 0xCFB9,	0x778F, 0xB260, 0x7790, 0xB261, 0x7791, 0xEEA8, 0x7792, 0xC2F7,
+	0x7793, 0xB262, 0x7794, 0xB263, 0x7795, 0xB264, 0x7796, 0xB265,	0x7797, 0xB266, 0x7798, 0xB267, 0x7799, 0xB268, 0x779A, 0xB269,
+	0x779B, 0xB26A, 0x779C, 0xB26B, 0x779D, 0xB26C, 0x779E, 0xB26D,	0x779F, 0xEEA9, 0x77A0, 0xEEAA, 0x77A1, 0xB26E, 0x77A2, 0xDEAB,
+	0x77A3, 0xB26F, 0x77A4, 0xB270, 0x77A5, 0xC6B3, 0x77A6, 0xB271,	0x77A7, 0xC7C6, 0x77A8, 0xB272, 0x77A9, 0xD6F5, 0x77AA, 0xB5C9,
+	0x77AB, 0xB273, 0x77AC, 0xCBB2, 0x77AD, 0xB274, 0x77AE, 0xB275,	0x77AF, 0xB276, 0x77B0, 0xEEAB, 0x77B1, 0xB277, 0x77B2, 0xB278,
+	0x77B3, 0xCDAB, 0x77B4, 0xB279, 0x77B5, 0xEEAC, 0x77B6, 0xB27A,	0x77B7, 0xB27B, 0x77B8, 0xB27C, 0x77B9, 0xB27D, 0x77BA, 0xB27E,
+	0x77BB, 0xD5B0, 0x77BC, 0xB280, 0x77BD, 0xEEAD, 0x77BE, 0xB281,	0x77BF, 0xF6C4, 0x77C0, 0xB282, 0x77C1, 0xB283, 0x77C2, 0xB284,
+	0x77C3, 0xB285, 0x77C4, 0xB286, 0x77C5, 0xB287, 0x77C6, 0xB288,	0x77C7, 0xB289, 0x77C8, 0xB28A, 0x77C9, 0xB28B, 0x77CA, 0xB28C,
+	0x77CB, 0xB28D, 0x77CC, 0xB28E, 0x77CD, 0xDBC7, 0x77CE, 0xB28F,	0x77CF, 0xB290, 0x77D0, 0xB291, 0x77D1, 0xB292, 0x77D2, 0xB293,
+	0x77D3, 0xB294, 0x77D4, 0xB295, 0x77D5, 0xB296, 0x77D6, 0xB297,	0x77D7, 0xB4A3, 0x77D8, 0xB298, 0x77D9, 0xB299, 0x77DA, 0xB29A,
+	0x77DB, 0xC3AC, 0x77DC, 0xF1E6, 0x77DD, 0xB29B, 0x77DE, 0xB29C,	0x77DF, 0xB29D, 0x77E0, 0xB29E, 0x77E1, 0xB29F, 0x77E2, 0xCAB8,
+	0x77E3, 0xD2D3, 0x77E4, 0xB2A0, 0x77E5, 0xD6AA, 0x77E6, 0xB340,	0x77E7, 0xEFF2, 0x77E8, 0xB341, 0x77E9, 0xBED8, 0x77EA, 0xB342,
+	0x77EB, 0xBDC3, 0x77EC, 0xEFF3, 0x77ED, 0xB6CC, 0x77EE, 0xB0AB,	0x77EF, 0xB343, 0x77F0, 0xB344, 0x77F1, 0xB345, 0x77F2, 0xB346,
+	0x77F3, 0xCAAF, 0x77F4, 0xB347, 0x77F5, 0xB348, 0x77F6, 0xEDB6,	0x77F7, 0xB349, 0x77F8, 0xEDB7, 0x77F9, 0xB34A, 0x77FA, 0xB34B,
+	0x77FB, 0xB34C, 0x77FC, 0xB34D, 0x77FD, 0xCEF9, 0x77FE, 0xB7AF,	0x77FF, 0xBFF3, 0x7800, 0xEDB8, 0x7801, 0xC2EB, 0x7802, 0xC9B0,
+	0x7803, 0xB34E, 0x7804, 0xB34F, 0x7805, 0xB350, 0x7806, 0xB351,	0x7807, 0xB352, 0x7808, 0xB353, 0x7809, 0xEDB9, 0x780A, 0xB354,
+	0x780B, 0xB355, 0x780C, 0xC6F6, 0x780D, 0xBFB3, 0x780E, 0xB356,	0x780F, 0xB357, 0x7810, 0xB358, 0x7811, 0xEDBC, 0x7812, 0xC5F8,
+	0x7813, 0xB359, 0x7814, 0xD1D0, 0x7815, 0xB35A, 0x7816, 0xD7A9,	0x7817, 0xEDBA, 0x7818, 0xEDBB, 0x7819, 0xB35B, 0x781A, 0xD1E2,
+	0x781B, 0xB35C, 0x781C, 0xEDBF, 0x781D, 0xEDC0, 0x781E, 0xB35D,	0x781F, 0xEDC4, 0x7820, 0xB35E, 0x7821, 0xB35F, 0x7822, 0xB360,
+	0x7823, 0xEDC8, 0x7824, 0xB361, 0x7825, 0xEDC6, 0x7826, 0xEDCE,	0x7827, 0xD5E8, 0x7828, 0xB362, 0x7829, 0xEDC9, 0x782A, 0xB363,
+	0x782B, 0xB364, 0x782C, 0xEDC7, 0x782D, 0xEDBE, 0x782E, 0xB365,	0x782F, 0xB366, 0x7830, 0xC5E9, 0x7831, 0xB367, 0x7832, 0xB368,
+	0x7833, 0xB369, 0x7834, 0xC6C6, 0x7835, 0xB36A, 0x7836, 0xB36B,	0x7837, 0xC9E9, 0x7838, 0xD4D2, 0x7839, 0xEDC1, 0x783A, 0xEDC2,
+	0x783B, 0xEDC3, 0x783C, 0xEDC5, 0x783D, 0xB36C, 0x783E, 0xC0F9,	0x783F, 0xB36D, 0x7840, 0xB4A1, 0x7841, 0xB36E, 0x7842, 0xB36F,
+	0x7843, 0xB370, 0x7844, 0xB371, 0x7845, 0xB9E8, 0x7846, 0xB372,	0x7847, 0xEDD0, 0x7848, 0xB373, 0x7849, 0xB374, 0x784A, 0xB375,
+	0x784B, 0xB376, 0x784C, 0xEDD1, 0x784D, 0xB377, 0x784E, 0xEDCA,	0x784F, 0xB378, 0x7850, 0xEDCF, 0x7851, 0xB379, 0x7852, 0xCEF8,
+	0x7853, 0xB37A, 0x7854, 0xB37B, 0x7855, 0xCBB6, 0x7856, 0xEDCC,	0x7857, 0xEDCD, 0x7858, 0xB37C, 0x7859, 0xB37D, 0x785A, 0xB37E,
+	0x785B, 0xB380, 0x785C, 0xB381, 0x785D, 0xCFF5, 0x785E, 0xB382,	0x785F, 0xB383, 0x7860, 0xB384, 0x7861, 0xB385, 0x7862, 0xB386,
+	0x7863, 0xB387, 0x7864, 0xB388, 0x7865, 0xB389, 0x7866, 0xB38A,	0x7867, 0xB38B, 0x7868, 0xB38C, 0x7869, 0xB38D, 0x786A, 0xEDD2,
+	0x786B, 0xC1F2, 0x786C, 0xD3B2, 0x786D, 0xEDCB, 0x786E, 0xC8B7,	0x786F, 0xB38E, 0x7870, 0xB38F, 0x7871, 0xB390, 0x7872, 0xB391,
+	0x7873, 0xB392, 0x7874, 0xB393, 0x7875, 0xB394, 0x7876, 0xB395,	0x7877, 0xBCEF, 0x7878, 0xB396, 0x7879, 0xB397, 0x787A, 0xB398,
+	0x787B, 0xB399, 0x787C, 0xC5F0, 0x787D, 0xB39A, 0x787E, 0xB39B,	0x787F, 0xB39C, 0x7880, 0xB39D, 0x7881, 0xB39E, 0x7882, 0xB39F,
+	0x7883, 0xB3A0, 0x7884, 0xB440, 0x7885, 0xB441, 0x7886, 0xB442,	0x7887, 0xEDD6, 0x7888, 0xB443, 0x7889, 0xB5EF, 0x788A, 0xB444,
+	0x788B, 0xB445, 0x788C, 0xC2B5, 0x788D, 0xB0AD, 0x788E, 0xCBE9,	0x788F, 0xB446, 0x7890, 0xB447, 0x7891, 0xB1AE, 0x7892, 0xB448,
+	0x7893, 0xEDD4, 0x7894, 0xB449, 0x7895, 0xB44A, 0x7896, 0xB44B,	0x7897, 0xCDEB, 0x7898, 0xB5E2, 0x7899, 0xB44C, 0x789A, 0xEDD5,
+	0x789B, 0xEDD3, 0x789C, 0xEDD7, 0x789D, 0xB44D, 0x789E, 0xB44E,	0x789F, 0xB5FA, 0x78A0, 0xB44F, 0x78A1, 0xEDD8, 0x78A2, 0xB450,
+	0x78A3, 0xEDD9, 0x78A4, 0xB451, 0x78A5, 0xEDDC, 0x78A6, 0xB452,	0x78A7, 0xB1CC, 0x78A8, 0xB453, 0x78A9, 0xB454, 0x78AA, 0xB455,
+	0x78AB, 0xB456, 0x78AC, 0xB457, 0x78AD, 0xB458, 0x78AE, 0xB459,	0x78AF, 0xB45A, 0x78B0, 0xC5F6, 0x78B1, 0xBCEE, 0x78B2, 0xEDDA,
+	0x78B3, 0xCCBC, 0x78B4, 0xB2EA, 0x78B5, 0xB45B, 0x78B6, 0xB45C,	0x78B7, 0xB45D, 0x78B8, 0xB45E, 0x78B9, 0xEDDB, 0x78BA, 0xB45F,
+	0x78BB, 0xB460, 0x78BC, 0xB461, 0x78BD, 0xB462, 0x78BE, 0xC4EB,	0x78BF, 0xB463, 0x78C0, 0xB464, 0x78C1, 0xB4C5, 0x78C2, 0xB465,
+	0x78C3, 0xB466, 0x78C4, 0xB467, 0x78C5, 0xB0F5, 0x78C6, 0xB468,	0x78C7, 0xB469, 0x78C8, 0xB46A, 0x78C9, 0xEDDF, 0x78CA, 0xC0DA,
+	0x78CB, 0xB4E8, 0x78CC, 0xB46B, 0x78CD, 0xB46C, 0x78CE, 0xB46D,	0x78CF, 0xB46E, 0x78D0, 0xC5CD, 0x78D1, 0xB46F, 0x78D2, 0xB470,
+	0x78D3, 0xB471, 0x78D4, 0xEDDD, 0x78D5, 0xBFC4, 0x78D6, 0xB472,	0x78D7, 0xB473, 0x78D8, 0xB474, 0x78D9, 0xEDDE, 0x78DA, 0xB475,
+	0x78DB, 0xB476, 0x78DC, 0xB477, 0x78DD, 0xB478, 0x78DE, 0xB479,	0x78DF, 0xB47A, 0x78E0, 0xB47B, 0x78E1, 0xB47C, 0x78E2, 0xB47D,
+	0x78E3, 0xB47E, 0x78E4, 0xB480, 0x78E5, 0xB481, 0x78E6, 0xB482,	0x78E7, 0xB483, 0x78E8, 0xC4A5, 0x78E9, 0xB484, 0x78EA, 0xB485,
+	0x78EB, 0xB486, 0x78EC, 0xEDE0, 0x78ED, 0xB487, 0x78EE, 0xB488,	0x78EF, 0xB489, 0x78F0, 0xB48A, 0x78F1, 0xB48B, 0x78F2, 0xEDE1,
+	0x78F3, 0xB48C, 0x78F4, 0xEDE3, 0x78F5, 0xB48D, 0x78F6, 0xB48E,	0x78F7, 0xC1D7, 0x78F8, 0xB48F, 0x78F9, 0xB490, 0x78FA, 0xBBC7,
+	0x78FB, 0xB491, 0x78FC, 0xB492, 0x78FD, 0xB493, 0x78FE, 0xB494,	0x78FF, 0xB495, 0x7900, 0xB496, 0x7901, 0xBDB8, 0x7902, 0xB497,
+	0x7903, 0xB498, 0x7904, 0xB499, 0x7905, 0xEDE2, 0x7906, 0xB49A,	0x7907, 0xB49B, 0x7908, 0xB49C, 0x7909, 0xB49D, 0x790A, 0xB49E,
+	0x790B, 0xB49F, 0x790C, 0xB4A0, 0x790D, 0xB540, 0x790E, 0xB541,	0x790F, 0xB542, 0x7910, 0xB543, 0x7911, 0xB544, 0x7912, 0xB545,
+	0x7913, 0xEDE4, 0x7914, 0xB546, 0x7915, 0xB547, 0x7916, 0xB548,	0x7917, 0xB549, 0x7918, 0xB54A, 0x7919, 0xB54B, 0x791A, 0xB54C,
+	0x791B, 0xB54D, 0x791C, 0xB54E, 0x791D, 0xB54F, 0x791E, 0xEDE6,	0x791F, 0xB550, 0x7920, 0xB551, 0x7921, 0xB552, 0x7922, 0xB553,
+	0x7923, 0xB554, 0x7924, 0xEDE5, 0x7925, 0xB555, 0x7926, 0xB556,	0x7927, 0xB557, 0x7928, 0xB558, 0x7929, 0xB559, 0x792A, 0xB55A,
+	0x792B, 0xB55B, 0x792C, 0xB55C, 0x792D, 0xB55D, 0x792E, 0xB55E,	0x792F, 0xB55F, 0x7930, 0xB560, 0x7931, 0xB561, 0x7932, 0xB562,
+	0x7933, 0xB563, 0x7934, 0xEDE7, 0x7935, 0xB564, 0x7936, 0xB565,	0x7937, 0xB566, 0x7938, 0xB567, 0x7939, 0xB568, 0x793A, 0xCABE,
+	0x793B, 0xECEA, 0x793C, 0xC0F1, 0x793D, 0xB569, 0x793E, 0xC9E7,	0x793F, 0xB56A, 0x7940, 0xECEB, 0x7941, 0xC6EE, 0x7942, 0xB56B,
+	0x7943, 0xB56C, 0x7944, 0xB56D, 0x7945, 0xB56E, 0x7946, 0xECEC,	0x7947, 0xB56F, 0x7948, 0xC6ED, 0x7949, 0xECED, 0x794A, 0xB570,
+	0x794B, 0xB571, 0x794C, 0xB572, 0x794D, 0xB573, 0x794E, 0xB574,	0x794F, 0xB575, 0x7950, 0xB576, 0x7951, 0xB577, 0x7952, 0xB578,
+	0x7953, 0xECF0, 0x7954, 0xB579, 0x7955, 0xB57A, 0x7956, 0xD7E6,	0x7957, 0xECF3, 0x7958, 0xB57B, 0x7959, 0xB57C, 0x795A, 0xECF1,
+	0x795B, 0xECEE, 0x795C, 0xECEF, 0x795D, 0xD7A3, 0x795E, 0xC9F1,	0x795F, 0xCBEE, 0x7960, 0xECF4, 0x7961, 0xB57D, 0x7962, 0xECF2,
+	0x7963, 0xB57E, 0x7964, 0xB580, 0x7965, 0xCFE9, 0x7966, 0xB581,	0x7967, 0xECF6, 0x7968, 0xC6B1, 0x7969, 0xB582, 0x796A, 0xB583,
+	0x796B, 0xB584, 0x796C, 0xB585, 0x796D, 0xBCC0, 0x796E, 0xB586,	0x796F, 0xECF5, 0x7970, 0xB587, 0x7971, 0xB588, 0x7972, 0xB589,
+	0x7973, 0xB58A, 0x7974, 0xB58B, 0x7975, 0xB58C, 0x7976, 0xB58D,	0x7977, 0xB5BB, 0x7978, 0xBBF6, 0x7979, 0xB58E, 0x797A, 0xECF7,
+	0x797B, 0xB58F, 0x797C, 0xB590, 0x797D, 0xB591, 0x797E, 0xB592,	0x797F, 0xB593, 0x7980, 0xD9F7, 0x7981, 0xBDFB, 0x7982, 0xB594,
+	0x7983, 0xB595, 0x7984, 0xC2BB, 0x7985, 0xECF8, 0x7986, 0xB596,	0x7987, 0xB597, 0x7988, 0xB598, 0x7989, 0xB599, 0x798A, 0xECF9,
+	0x798B, 0xB59A, 0x798C, 0xB59B, 0x798D, 0xB59C, 0x798E, 0xB59D,	0x798F, 0xB8A3, 0x7990, 0xB59E, 0x7991, 0xB59F, 0x7992, 0xB5A0,
+	0x7993, 0xB640, 0x7994, 0xB641, 0x7995, 0xB642, 0x7996, 0xB643,	0x7997, 0xB644, 0x7998, 0xB645, 0x7999, 0xB646, 0x799A, 0xECFA,
+	0x799B, 0xB647, 0x799C, 0xB648, 0x799D, 0xB649, 0x799E, 0xB64A,	0x799F, 0xB64B, 0x79A0, 0xB64C, 0x79A1, 0xB64D, 0x79A2, 0xB64E,
+	0x79A3, 0xB64F, 0x79A4, 0xB650, 0x79A5, 0xB651, 0x79A6, 0xB652,	0x79A7, 0xECFB, 0x79A8, 0xB653, 0x79A9, 0xB654, 0x79AA, 0xB655,
+	0x79AB, 0xB656, 0x79AC, 0xB657, 0x79AD, 0xB658, 0x79AE, 0xB659,	0x79AF, 0xB65A, 0x79B0, 0xB65B, 0x79B1, 0xB65C, 0x79B2, 0xB65D,
+	0x79B3, 0xECFC, 0x79B4, 0xB65E, 0x79B5, 0xB65F, 0x79B6, 0xB660,	0x79B7, 0xB661, 0x79B8, 0xB662, 0x79B9, 0xD3ED, 0x79BA, 0xD8AE,
+	0x79BB, 0xC0EB, 0x79BC, 0xB663, 0x79BD, 0xC7DD, 0x79BE, 0xBACC,	0x79BF, 0xB664, 0x79C0, 0xD0E3, 0x79C1, 0xCBBD, 0x79C2, 0xB665,
+	0x79C3, 0xCDBA, 0x79C4, 0xB666, 0x79C5, 0xB667, 0x79C6, 0xB8D1,	0x79C7, 0xB668, 0x79C8, 0xB669, 0x79C9, 0xB1FC, 0x79CA, 0xB66A,
+	0x79CB, 0xC7EF, 0x79CC, 0xB66B, 0x79CD, 0xD6D6, 0x79CE, 0xB66C,	0x79CF, 0xB66D, 0x79D0, 0xB66E, 0x79D1, 0xBFC6, 0x79D2, 0xC3EB,
+	0x79D3, 0xB66F, 0x79D4, 0xB670, 0x79D5, 0xEFF5, 0x79D6, 0xB671,	0x79D7, 0xB672, 0x79D8, 0xC3D8, 0x79D9, 0xB673, 0x79DA, 0xB674,
+	0x79DB, 0xB675, 0x79DC, 0xB676, 0x79DD, 0xB677, 0x79DE, 0xB678,	0x79DF, 0xD7E2, 0x79E0, 0xB679, 0x79E1, 0xB67A, 0x79E2, 0xB67B,
+	0x79E3, 0xEFF7, 0x79E4, 0xB3D3, 0x79E5, 0xB67C, 0x79E6, 0xC7D8,	0x79E7, 0xD1ED, 0x79E8, 0xB67D, 0x79E9, 0xD6C8, 0x79EA, 0xB67E,
+	0x79EB, 0xEFF8, 0x79EC, 0xB680, 0x79ED, 0xEFF6, 0x79EE, 0xB681,	0x79EF, 0xBBFD, 0x79F0, 0xB3C6, 0x79F1, 0xB682, 0x79F2, 0xB683,
+	0x79F3, 0xB684, 0x79F4, 0xB685, 0x79F5, 0xB686, 0x79F6, 0xB687,	0x79F7, 0xB688, 0x79F8, 0xBDD5, 0x79F9, 0xB689, 0x79FA, 0xB68A,
+	0x79FB, 0xD2C6, 0x79FC, 0xB68B, 0x79FD, 0xBBE0, 0x79FE, 0xB68C,	0x79FF, 0xB68D, 0x7A00, 0xCFA1, 0x7A01, 0xB68E, 0x7A02, 0xEFFC,
+	0x7A03, 0xEFFB, 0x7A04, 0xB68F, 0x7A05, 0xB690, 0x7A06, 0xEFF9,	0x7A07, 0xB691, 0x7A08, 0xB692, 0x7A09, 0xB693, 0x7A0A, 0xB694,
+	0x7A0B, 0xB3CC, 0x7A0C, 0xB695, 0x7A0D, 0xC9D4, 0x7A0E, 0xCBB0,	0x7A0F, 0xB696, 0x7A10, 0xB697, 0x7A11, 0xB698, 0x7A12, 0xB699,
+	0x7A13, 0xB69A, 0x7A14, 0xEFFE, 0x7A15, 0xB69B, 0x7A16, 0xB69C,	0x7A17, 0xB0DE, 0x7A18, 0xB69D, 0x7A19, 0xB69E, 0x7A1A, 0xD6C9,
+	0x7A1B, 0xB69F, 0x7A1C, 0xB6A0, 0x7A1D, 0xB740, 0x7A1E, 0xEFFD,	0x7A1F, 0xB741, 0x7A20, 0xB3ED, 0x7A21, 0xB742, 0x7A22, 0xB743,
+	0x7A23, 0xF6D5, 0x7A24, 0xB744, 0x7A25, 0xB745, 0x7A26, 0xB746,	0x7A27, 0xB747, 0x7A28, 0xB748, 0x7A29, 0xB749, 0x7A2A, 0xB74A,
+	0x7A2B, 0xB74B, 0x7A2C, 0xB74C, 0x7A2D, 0xB74D, 0x7A2E, 0xB74E,	0x7A2F, 0xB74F, 0x7A30, 0xB750, 0x7A31, 0xB751, 0x7A32, 0xB752,
+	0x7A33, 0xCEC8, 0x7A34, 0xB753, 0x7A35, 0xB754, 0x7A36, 0xB755,	0x7A37, 0xF0A2, 0x7A38, 0xB756, 0x7A39, 0xF0A1, 0x7A3A, 0xB757,
+	0x7A3B, 0xB5BE, 0x7A3C, 0xBCDA, 0x7A3D, 0xBBFC, 0x7A3E, 0xB758,	0x7A3F, 0xB8E5, 0x7A40, 0xB759, 0x7A41, 0xB75A, 0x7A42, 0xB75B,
+	0x7A43, 0xB75C, 0x7A44, 0xB75D, 0x7A45, 0xB75E, 0x7A46, 0xC4C2,	0x7A47, 0xB75F, 0x7A48, 0xB760, 0x7A49, 0xB761, 0x7A4A, 0xB762,
+	0x7A4B, 0xB763, 0x7A4C, 0xB764, 0x7A4D, 0xB765, 0x7A4E, 0xB766,	0x7A4F, 0xB767, 0x7A50, 0xB768, 0x7A51, 0xF0A3, 0x7A52, 0xB769,
+	0x7A53, 0xB76A, 0x7A54, 0xB76B, 0x7A55, 0xB76C, 0x7A56, 0xB76D,	0x7A57, 0xCBEB, 0x7A58, 0xB76E, 0x7A59, 0xB76F, 0x7A5A, 0xB770,
+	0x7A5B, 0xB771, 0x7A5C, 0xB772, 0x7A5D, 0xB773, 0x7A5E, 0xB774,	0x7A5F, 0xB775, 0x7A60, 0xB776, 0x7A61, 0xB777, 0x7A62, 0xB778,
+	0x7A63, 0xB779, 0x7A64, 0xB77A, 0x7A65, 0xB77B, 0x7A66, 0xB77C,	0x7A67, 0xB77D, 0x7A68, 0xB77E, 0x7A69, 0xB780, 0x7A6A, 0xB781,
+	0x7A6B, 0xB782, 0x7A6C, 0xB783, 0x7A6D, 0xB784, 0x7A6E, 0xB785,	0x7A6F, 0xB786, 0x7A70, 0xF0A6, 0x7A71, 0xB787, 0x7A72, 0xB788,
+	0x7A73, 0xB789, 0x7A74, 0xD1A8, 0x7A75, 0xB78A, 0x7A76, 0xBEBF,	0x7A77, 0xC7EE, 0x7A78, 0xF1B6, 0x7A79, 0xF1B7, 0x7A7A, 0xBFD5,
+	0x7A7B, 0xB78B, 0x7A7C, 0xB78C, 0x7A7D, 0xB78D, 0x7A7E, 0xB78E,	0x7A7F, 0xB4A9, 0x7A80, 0xF1B8, 0x7A81, 0xCDBB, 0x7A82, 0xB78F,
+	0x7A83, 0xC7D4, 0x7A84, 0xD5AD, 0x7A85, 0xB790, 0x7A86, 0xF1B9,	0x7A87, 0xB791, 0x7A88, 0xF1BA, 0x7A89, 0xB792, 0x7A8A, 0xB793,
+	0x7A8B, 0xB794, 0x7A8C, 0xB795, 0x7A8D, 0xC7CF, 0x7A8E, 0xB796,	0x7A8F, 0xB797, 0x7A90, 0xB798, 0x7A91, 0xD2A4, 0x7A92, 0xD6CF,
+	0x7A93, 0xB799, 0x7A94, 0xB79A, 0x7A95, 0xF1BB, 0x7A96, 0xBDD1,	0x7A97, 0xB4B0, 0x7A98, 0xBEBD, 0x7A99, 0xB79B, 0x7A9A, 0xB79C,
+	0x7A9B, 0xB79D, 0x7A9C, 0xB4DC, 0x7A9D, 0xCED1, 0x7A9E, 0xB79E,	0x7A9F, 0xBFDF, 0x7AA0, 0xF1BD, 0x7AA1, 0xB79F, 0x7AA2, 0xB7A0,
+	0x7AA3, 0xB840, 0x7AA4, 0xB841, 0x7AA5, 0xBFFA, 0x7AA6, 0xF1BC,	0x7AA7, 0xB842, 0x7AA8, 0xF1BF, 0x7AA9, 0xB843, 0x7AAA, 0xB844,
+	0x7AAB, 0xB845, 0x7AAC, 0xF1BE, 0x7AAD, 0xF1C0, 0x7AAE, 0xB846,	0x7AAF, 0xB847, 0x7AB0, 0xB848, 0x7AB1, 0xB849, 0x7AB2, 0xB84A,
+	0x7AB3, 0xF1C1, 0x7AB4, 0xB84B, 0x7AB5, 0xB84C, 0x7AB6, 0xB84D,	0x7AB7, 0xB84E, 0x7AB8, 0xB84F, 0x7AB9, 0xB850, 0x7ABA, 0xB851,
+	0x7ABB, 0xB852, 0x7ABC, 0xB853, 0x7ABD, 0xB854, 0x7ABE, 0xB855,	0x7ABF, 0xC1FE, 0x7AC0, 0xB856, 0x7AC1, 0xB857, 0x7AC2, 0xB858,
+	0x7AC3, 0xB859, 0x7AC4, 0xB85A, 0x7AC5, 0xB85B, 0x7AC6, 0xB85C,	0x7AC7, 0xB85D, 0x7AC8, 0xB85E, 0x7AC9, 0xB85F, 0x7ACA, 0xB860,
+	0x7ACB, 0xC1A2, 0x7ACC, 0xB861, 0x7ACD, 0xB862, 0x7ACE, 0xB863,	0x7ACF, 0xB864, 0x7AD0, 0xB865, 0x7AD1, 0xB866, 0x7AD2, 0xB867,
+	0x7AD3, 0xB868, 0x7AD4, 0xB869, 0x7AD5, 0xB86A, 0x7AD6, 0xCAFA,	0x7AD7, 0xB86B, 0x7AD8, 0xB86C, 0x7AD9, 0xD5BE, 0x7ADA, 0xB86D,
+	0x7ADB, 0xB86E, 0x7ADC, 0xB86F, 0x7ADD, 0xB870, 0x7ADE, 0xBEBA,	0x7ADF, 0xBEB9, 0x7AE0, 0xD5C2, 0x7AE1, 0xB871, 0x7AE2, 0xB872,
+	0x7AE3, 0xBFA2, 0x7AE4, 0xB873, 0x7AE5, 0xCDAF, 0x7AE6, 0xF1B5,	0x7AE7, 0xB874, 0x7AE8, 0xB875, 0x7AE9, 0xB876, 0x7AEA, 0xB877,
+	0x7AEB, 0xB878, 0x7AEC, 0xB879, 0x7AED, 0xBDDF, 0x7AEE, 0xB87A,	0x7AEF, 0xB6CB, 0x7AF0, 0xB87B, 0x7AF1, 0xB87C, 0x7AF2, 0xB87D,
+	0x7AF3, 0xB87E, 0x7AF4, 0xB880, 0x7AF5, 0xB881, 0x7AF6, 0xB882,	0x7AF7, 0xB883, 0x7AF8, 0xB884, 0x7AF9, 0xD6F1, 0x7AFA, 0xF3C3,
+	0x7AFB, 0xB885, 0x7AFC, 0xB886, 0x7AFD, 0xF3C4, 0x7AFE, 0xB887,	0x7AFF, 0xB8CD, 0x7B00, 0xB888, 0x7B01, 0xB889, 0x7B02, 0xB88A,
+	0x7B03, 0xF3C6, 0x7B04, 0xF3C7, 0x7B05, 0xB88B, 0x7B06, 0xB0CA,	0x7B07, 0xB88C, 0x7B08, 0xF3C5, 0x7B09, 0xB88D, 0x7B0A, 0xF3C9,
+	0x7B0B, 0xCBF1, 0x7B0C, 0xB88E, 0x7B0D, 0xB88F, 0x7B0E, 0xB890,	0x7B0F, 0xF3CB, 0x7B10, 0xB891, 0x7B11, 0xD0A6, 0x7B12, 0xB892,
+	0x7B13, 0xB893, 0x7B14, 0xB1CA, 0x7B15, 0xF3C8, 0x7B16, 0xB894,	0x7B17, 0xB895, 0x7B18, 0xB896, 0x7B19, 0xF3CF, 0x7B1A, 0xB897,
+	0x7B1B, 0xB5D1, 0x7B1C, 0xB898, 0x7B1D, 0xB899, 0x7B1E, 0xF3D7,	0x7B1F, 0xB89A, 0x7B20, 0xF3D2, 0x7B21, 0xB89B, 0x7B22, 0xB89C,
+	0x7B23, 0xB89D, 0x7B24, 0xF3D4, 0x7B25, 0xF3D3, 0x7B26, 0xB7FB,	0x7B27, 0xB89E, 0x7B28, 0xB1BF, 0x7B29, 0xB89F, 0x7B2A, 0xF3CE,
+	0x7B2B, 0xF3CA, 0x7B2C, 0xB5DA, 0x7B2D, 0xB8A0, 0x7B2E, 0xF3D0,	0x7B2F, 0xB940, 0x7B30, 0xB941, 0x7B31, 0xF3D1, 0x7B32, 0xB942,
+	0x7B33, 0xF3D5, 0x7B34, 0xB943, 0x7B35, 0xB944, 0x7B36, 0xB945,	0x7B37, 0xB946, 0x7B38, 0xF3CD, 0x7B39, 0xB947, 0x7B3A, 0xBCE3,
+	0x7B3B, 0xB948, 0x7B3C, 0xC1FD, 0x7B3D, 0xB949, 0x7B3E, 0xF3D6,	0x7B3F, 0xB94A, 0x7B40, 0xB94B, 0x7B41, 0xB94C, 0x7B42, 0xB94D,
+	0x7B43, 0xB94E, 0x7B44, 0xB94F, 0x7B45, 0xF3DA, 0x7B46, 0xB950,	0x7B47, 0xF3CC, 0x7B48, 0xB951, 0x7B49, 0xB5C8, 0x7B4A, 0xB952,
+	0x7B4B, 0xBDEE, 0x7B4C, 0xF3DC, 0x7B4D, 0xB953, 0x7B4E, 0xB954,	0x7B4F, 0xB7A4, 0x7B50, 0xBFF0, 0x7B51, 0xD6FE, 0x7B52, 0xCDB2,
+	0x7B53, 0xB955, 0x7B54, 0xB4F0, 0x7B55, 0xB956, 0x7B56, 0xB2DF,	0x7B57, 0xB957, 0x7B58, 0xF3D8, 0x7B59, 0xB958, 0x7B5A, 0xF3D9,
+	0x7B5B, 0xC9B8, 0x7B5C, 0xB959, 0x7B5D, 0xF3DD, 0x7B5E, 0xB95A,	0x7B5F, 0xB95B, 0x7B60, 0xF3DE, 0x7B61, 0xB95C, 0x7B62, 0xF3E1,
+	0x7B63, 0xB95D, 0x7B64, 0xB95E, 0x7B65, 0xB95F, 0x7B66, 0xB960,	0x7B67, 0xB961, 0x7B68, 0xB962, 0x7B69, 0xB963, 0x7B6A, 0xB964,
+	0x7B6B, 0xB965, 0x7B6C, 0xB966, 0x7B6D, 0xB967, 0x7B6E, 0xF3DF,	0x7B6F, 0xB968, 0x7B70, 0xB969, 0x7B71, 0xF3E3, 0x7B72, 0xF3E2,
+	0x7B73, 0xB96A, 0x7B74, 0xB96B, 0x7B75, 0xF3DB, 0x7B76, 0xB96C,	0x7B77, 0xBFEA, 0x7B78, 0xB96D, 0x7B79, 0xB3EF, 0x7B7A, 0xB96E,
+	0x7B7B, 0xF3E0, 0x7B7C, 0xB96F, 0x7B7D, 0xB970, 0x7B7E, 0xC7A9,	0x7B7F, 0xB971, 0x7B80, 0xBCF2, 0x7B81, 0xB972, 0x7B82, 0xB973,
+	0x7B83, 0xB974, 0x7B84, 0xB975, 0x7B85, 0xF3EB, 0x7B86, 0xB976,	0x7B87, 0xB977, 0x7B88, 0xB978, 0x7B89, 0xB979, 0x7B8A, 0xB97A,
+	0x7B8B, 0xB97B, 0x7B8C, 0xB97C, 0x7B8D, 0xB9BF, 0x7B8E, 0xB97D,	0x7B8F, 0xB97E, 0x7B90, 0xF3E4, 0x7B91, 0xB980, 0x7B92, 0xB981,
+	0x7B93, 0xB982, 0x7B94, 0xB2AD, 0x7B95, 0xBBFE, 0x7B96, 0xB983,	0x7B97, 0xCBE3, 0x7B98, 0xB984, 0x7B99, 0xB985, 0x7B9A, 0xB986,
+	0x7B9B, 0xB987, 0x7B9C, 0xF3ED, 0x7B9D, 0xF3E9, 0x7B9E, 0xB988,	0x7B9F, 0xB989, 0x7BA0, 0xB98A, 0x7BA1, 0xB9DC, 0x7BA2, 0xF3EE,
+	0x7BA3, 0xB98B, 0x7BA4, 0xB98C, 0x7BA5, 0xB98D, 0x7BA6, 0xF3E5,	0x7BA7, 0xF3E6, 0x7BA8, 0xF3EA, 0x7BA9, 0xC2E1, 0x7BAA, 0xF3EC,
+	0x7BAB, 0xF3EF, 0x7BAC, 0xF3E8, 0x7BAD, 0xBCFD, 0x7BAE, 0xB98E,	0x7BAF, 0xB98F, 0x7BB0, 0xB990, 0x7BB1, 0xCFE4, 0x7BB2, 0xB991,
+	0x7BB3, 0xB992, 0x7BB4, 0xF3F0, 0x7BB5, 0xB993, 0x7BB6, 0xB994,	0x7BB7, 0xB995, 0x7BB8, 0xF3E7, 0x7BB9, 0xB996, 0x7BBA, 0xB997,
+	0x7BBB, 0xB998, 0x7BBC, 0xB999, 0x7BBD, 0xB99A, 0x7BBE, 0xB99B,	0x7BBF, 0xB99C, 0x7BC0, 0xB99D, 0x7BC1, 0xF3F2, 0x7BC2, 0xB99E,
+	0x7BC3, 0xB99F, 0x7BC4, 0xB9A0, 0x7BC5, 0xBA40, 0x7BC6, 0xD7AD,	0x7BC7, 0xC6AA, 0x7BC8, 0xBA41, 0x7BC9, 0xBA42, 0x7BCA, 0xBA43,
+	0x7BCB, 0xBA44, 0x7BCC, 0xF3F3, 0x7BCD, 0xBA45, 0x7BCE, 0xBA46,	0x7BCF, 0xBA47, 0x7BD0, 0xBA48, 0x7BD1, 0xF3F1, 0x7BD2, 0xBA49,
+	0x7BD3, 0xC2A8, 0x7BD4, 0xBA4A, 0x7BD5, 0xBA4B, 0x7BD6, 0xBA4C,	0x7BD7, 0xBA4D, 0x7BD8, 0xBA4E, 0x7BD9, 0xB8DD, 0x7BDA, 0xF3F5,
+	0x7BDB, 0xBA4F, 0x7BDC, 0xBA50, 0x7BDD, 0xF3F4, 0x7BDE, 0xBA51,	0x7BDF, 0xBA52, 0x7BE0, 0xBA53, 0x7BE1, 0xB4DB, 0x7BE2, 0xBA54,
+	0x7BE3, 0xBA55, 0x7BE4, 0xBA56, 0x7BE5, 0xF3F6, 0x7BE6, 0xF3F7,	0x7BE7, 0xBA57, 0x7BE8, 0xBA58, 0x7BE9, 0xBA59, 0x7BEA, 0xF3F8,
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+	0x7E73, 0xC055, 0x7E74, 0xC056, 0x7E75, 0xC057, 0x7E76, 0xC058,	0x7E77, 0xC059, 0x7E78, 0xC05A, 0x7E79, 0xC05B, 0x7E7A, 0xC05C,
+	0x7E7B, 0xC05D, 0x7E7C, 0xC05E, 0x7E7D, 0xC05F, 0x7E7E, 0xC060,	0x7E7F, 0xC061, 0x7E80, 0xC062, 0x7E81, 0xC063, 0x7E82, 0xD7EB,
+	0x7E83, 0xC064, 0x7E84, 0xC065, 0x7E85, 0xC066, 0x7E86, 0xC067,	0x7E87, 0xC068, 0x7E88, 0xC069, 0x7E89, 0xC06A, 0x7E8A, 0xC06B,
+	0x7E8B, 0xC06C, 0x7E8C, 0xC06D, 0x7E8D, 0xC06E, 0x7E8E, 0xC06F,	0x7E8F, 0xC070, 0x7E90, 0xC071, 0x7E91, 0xC072, 0x7E92, 0xC073,
+	0x7E93, 0xC074, 0x7E94, 0xC075, 0x7E95, 0xC076, 0x7E96, 0xC077,	0x7E97, 0xC078, 0x7E98, 0xC079, 0x7E99, 0xC07A, 0x7E9A, 0xC07B,
+	0x7E9B, 0xF4EE, 0x7E9C, 0xC07C, 0x7E9D, 0xC07D, 0x7E9E, 0xC07E,	0x7E9F, 0xE6F9, 0x7EA0, 0xBEC0, 0x7EA1, 0xE6FA, 0x7EA2, 0xBAEC,
+	0x7EA3, 0xE6FB, 0x7EA4, 0xCFCB, 0x7EA5, 0xE6FC, 0x7EA6, 0xD4BC,	0x7EA7, 0xBCB6, 0x7EA8, 0xE6FD, 0x7EA9, 0xE6FE, 0x7EAA, 0xBCCD,
+	0x7EAB, 0xC8D2, 0x7EAC, 0xCEB3, 0x7EAD, 0xE7A1, 0x7EAE, 0xC080,	0x7EAF, 0xB4BF, 0x7EB0, 0xE7A2, 0x7EB1, 0xC9B4, 0x7EB2, 0xB8D9,
+	0x7EB3, 0xC4C9, 0x7EB4, 0xC081, 0x7EB5, 0xD7DD, 0x7EB6, 0xC2DA,	0x7EB7, 0xB7D7, 0x7EB8, 0xD6BD, 0x7EB9, 0xCEC6, 0x7EBA, 0xB7C4,
+	0x7EBB, 0xC082, 0x7EBC, 0xC083, 0x7EBD, 0xC5A6, 0x7EBE, 0xE7A3,	0x7EBF, 0xCFDF, 0x7EC0, 0xE7A4, 0x7EC1, 0xE7A5, 0x7EC2, 0xE7A6,
+	0x7EC3, 0xC1B7, 0x7EC4, 0xD7E9, 0x7EC5, 0xC9F0, 0x7EC6, 0xCFB8,	0x7EC7, 0xD6AF, 0x7EC8, 0xD6D5, 0x7EC9, 0xE7A7, 0x7ECA, 0xB0ED,
+	0x7ECB, 0xE7A8, 0x7ECC, 0xE7A9, 0x7ECD, 0xC9DC, 0x7ECE, 0xD2EF,	0x7ECF, 0xBEAD, 0x7ED0, 0xE7AA, 0x7ED1, 0xB0F3, 0x7ED2, 0xC8DE,
+	0x7ED3, 0xBDE1, 0x7ED4, 0xE7AB, 0x7ED5, 0xC8C6, 0x7ED6, 0xC084,	0x7ED7, 0xE7AC, 0x7ED8, 0xBBE6, 0x7ED9, 0xB8F8, 0x7EDA, 0xD1A4,
+	0x7EDB, 0xE7AD, 0x7EDC, 0xC2E7, 0x7EDD, 0xBEF8, 0x7EDE, 0xBDCA,	0x7EDF, 0xCDB3, 0x7EE0, 0xE7AE, 0x7EE1, 0xE7AF, 0x7EE2, 0xBEEE,
+	0x7EE3, 0xD0E5, 0x7EE4, 0xC085, 0x7EE5, 0xCBE7, 0x7EE6, 0xCCD0,	0x7EE7, 0xBCCC, 0x7EE8, 0xE7B0, 0x7EE9, 0xBCA8, 0x7EEA, 0xD0F7,
+	0x7EEB, 0xE7B1, 0x7EEC, 0xC086, 0x7EED, 0xD0F8, 0x7EEE, 0xE7B2,	0x7EEF, 0xE7B3, 0x7EF0, 0xB4C2, 0x7EF1, 0xE7B4, 0x7EF2, 0xE7B5,
+	0x7EF3, 0xC9FE, 0x7EF4, 0xCEAC, 0x7EF5, 0xC3E0, 0x7EF6, 0xE7B7,	0x7EF7, 0xB1C1, 0x7EF8, 0xB3F1, 0x7EF9, 0xC087, 0x7EFA, 0xE7B8,
+	0x7EFB, 0xE7B9, 0x7EFC, 0xD7DB, 0x7EFD, 0xD5C0, 0x7EFE, 0xE7BA,	0x7EFF, 0xC2CC, 0x7F00, 0xD7BA, 0x7F01, 0xE7BB, 0x7F02, 0xE7BC,
+	0x7F03, 0xE7BD, 0x7F04, 0xBCEA, 0x7F05, 0xC3E5, 0x7F06, 0xC0C2,	0x7F07, 0xE7BE, 0x7F08, 0xE7BF, 0x7F09, 0xBCA9, 0x7F0A, 0xC088,
+	0x7F0B, 0xE7C0, 0x7F0C, 0xE7C1, 0x7F0D, 0xE7B6, 0x7F0E, 0xB6D0,	0x7F0F, 0xE7C2, 0x7F10, 0xC089, 0x7F11, 0xE7C3, 0x7F12, 0xE7C4,
+	0x7F13, 0xBBBA, 0x7F14, 0xB5DE, 0x7F15, 0xC2C6, 0x7F16, 0xB1E0,	0x7F17, 0xE7C5, 0x7F18, 0xD4B5, 0x7F19, 0xE7C6, 0x7F1A, 0xB8BF,
+	0x7F1B, 0xE7C8, 0x7F1C, 0xE7C7, 0x7F1D, 0xB7EC, 0x7F1E, 0xC08A,	0x7F1F, 0xE7C9, 0x7F20, 0xB2F8, 0x7F21, 0xE7CA, 0x7F22, 0xE7CB,
+	0x7F23, 0xE7CC, 0x7F24, 0xE7CD, 0x7F25, 0xE7CE, 0x7F26, 0xE7CF,	0x7F27, 0xE7D0, 0x7F28, 0xD3A7, 0x7F29, 0xCBF5, 0x7F2A, 0xE7D1,
+	0x7F2B, 0xE7D2, 0x7F2C, 0xE7D3, 0x7F2D, 0xE7D4, 0x7F2E, 0xC9C9,	0x7F2F, 0xE7D5, 0x7F30, 0xE7D6, 0x7F31, 0xE7D7, 0x7F32, 0xE7D8,
+	0x7F33, 0xE7D9, 0x7F34, 0xBDC9, 0x7F35, 0xE7DA, 0x7F36, 0xF3BE,	0x7F37, 0xC08B, 0x7F38, 0xB8D7, 0x7F39, 0xC08C, 0x7F3A, 0xC8B1,
+	0x7F3B, 0xC08D, 0x7F3C, 0xC08E, 0x7F3D, 0xC08F, 0x7F3E, 0xC090,	0x7F3F, 0xC091, 0x7F40, 0xC092, 0x7F41, 0xC093, 0x7F42, 0xF3BF,
+	0x7F43, 0xC094, 0x7F44, 0xF3C0, 0x7F45, 0xF3C1, 0x7F46, 0xC095,	0x7F47, 0xC096, 0x7F48, 0xC097, 0x7F49, 0xC098, 0x7F4A, 0xC099,
+	0x7F4B, 0xC09A, 0x7F4C, 0xC09B, 0x7F4D, 0xC09C, 0x7F4E, 0xC09D,	0x7F4F, 0xC09E, 0x7F50, 0xB9DE, 0x7F51, 0xCDF8, 0x7F52, 0xC09F,
+	0x7F53, 0xC0A0, 0x7F54, 0xD8E8, 0x7F55, 0xBAB1, 0x7F56, 0xC140,	0x7F57, 0xC2DE, 0x7F58, 0xEEB7, 0x7F59, 0xC141, 0x7F5A, 0xB7A3,
+	0x7F5B, 0xC142, 0x7F5C, 0xC143, 0x7F5D, 0xC144, 0x7F5E, 0xC145,	0x7F5F, 0xEEB9, 0x7F60, 0xC146, 0x7F61, 0xEEB8, 0x7F62, 0xB0D5,
+	0x7F63, 0xC147, 0x7F64, 0xC148, 0x7F65, 0xC149, 0x7F66, 0xC14A,	0x7F67, 0xC14B, 0x7F68, 0xEEBB, 0x7F69, 0xD5D6, 0x7F6A, 0xD7EF,
+	0x7F6B, 0xC14C, 0x7F6C, 0xC14D, 0x7F6D, 0xC14E, 0x7F6E, 0xD6C3,	0x7F6F, 0xC14F, 0x7F70, 0xC150, 0x7F71, 0xEEBD, 0x7F72, 0xCAF0,
+	0x7F73, 0xC151, 0x7F74, 0xEEBC, 0x7F75, 0xC152, 0x7F76, 0xC153,	0x7F77, 0xC154, 0x7F78, 0xC155, 0x7F79, 0xEEBE, 0x7F7A, 0xC156,
+	0x7F7B, 0xC157, 0x7F7C, 0xC158, 0x7F7D, 0xC159, 0x7F7E, 0xEEC0,	0x7F7F, 0xC15A, 0x7F80, 0xC15B, 0x7F81, 0xEEBF, 0x7F82, 0xC15C,
+	0x7F83, 0xC15D, 0x7F84, 0xC15E, 0x7F85, 0xC15F, 0x7F86, 0xC160,	0x7F87, 0xC161, 0x7F88, 0xC162, 0x7F89, 0xC163, 0x7F8A, 0xD1F2,
+	0x7F8B, 0xC164, 0x7F8C, 0xC7BC, 0x7F8D, 0xC165, 0x7F8E, 0xC3C0,	0x7F8F, 0xC166, 0x7F90, 0xC167, 0x7F91, 0xC168, 0x7F92, 0xC169,
+	0x7F93, 0xC16A, 0x7F94, 0xB8E1, 0x7F95, 0xC16B, 0x7F96, 0xC16C,	0x7F97, 0xC16D, 0x7F98, 0xC16E, 0x7F99, 0xC16F, 0x7F9A, 0xC1E7,
+	0x7F9B, 0xC170, 0x7F9C, 0xC171, 0x7F9D, 0xF4C6, 0x7F9E, 0xD0DF,	0x7F9F, 0xF4C7, 0x7FA0, 0xC172, 0x7FA1, 0xCFDB, 0x7FA2, 0xC173,
+	0x7FA3, 0xC174, 0x7FA4, 0xC8BA, 0x7FA5, 0xC175, 0x7FA6, 0xC176,	0x7FA7, 0xF4C8, 0x7FA8, 0xC177, 0x7FA9, 0xC178, 0x7FAA, 0xC179,
+	0x7FAB, 0xC17A, 0x7FAC, 0xC17B, 0x7FAD, 0xC17C, 0x7FAE, 0xC17D,	0x7FAF, 0xF4C9, 0x7FB0, 0xF4CA, 0x7FB1, 0xC17E, 0x7FB2, 0xF4CB,
+	0x7FB3, 0xC180, 0x7FB4, 0xC181, 0x7FB5, 0xC182, 0x7FB6, 0xC183,	0x7FB7, 0xC184, 0x7FB8, 0xD9FA, 0x7FB9, 0xB8FE, 0x7FBA, 0xC185,
+	0x7FBB, 0xC186, 0x7FBC, 0xE5F1, 0x7FBD, 0xD3F0, 0x7FBE, 0xC187,	0x7FBF, 0xF4E0, 0x7FC0, 0xC188, 0x7FC1, 0xCECC, 0x7FC2, 0xC189,
+	0x7FC3, 0xC18A, 0x7FC4, 0xC18B, 0x7FC5, 0xB3E1, 0x7FC6, 0xC18C,	0x7FC7, 0xC18D, 0x7FC8, 0xC18E, 0x7FC9, 0xC18F, 0x7FCA, 0xF1B4,
+	0x7FCB, 0xC190, 0x7FCC, 0xD2EE, 0x7FCD, 0xC191, 0x7FCE, 0xF4E1,	0x7FCF, 0xC192, 0x7FD0, 0xC193, 0x7FD1, 0xC194, 0x7FD2, 0xC195,
+	0x7FD3, 0xC196, 0x7FD4, 0xCFE8, 0x7FD5, 0xF4E2, 0x7FD6, 0xC197,	0x7FD7, 0xC198, 0x7FD8, 0xC7CC, 0x7FD9, 0xC199, 0x7FDA, 0xC19A,
+	0x7FDB, 0xC19B, 0x7FDC, 0xC19C, 0x7FDD, 0xC19D, 0x7FDE, 0xC19E,	0x7FDF, 0xB5D4, 0x7FE0, 0xB4E4, 0x7FE1, 0xF4E4, 0x7FE2, 0xC19F,
+	0x7FE3, 0xC1A0, 0x7FE4, 0xC240, 0x7FE5, 0xF4E3, 0x7FE6, 0xF4E5,	0x7FE7, 0xC241, 0x7FE8, 0xC242, 0x7FE9, 0xF4E6, 0x7FEA, 0xC243,
+	0x7FEB, 0xC244, 0x7FEC, 0xC245, 0x7FED, 0xC246, 0x7FEE, 0xF4E7,	0x7FEF, 0xC247, 0x7FF0, 0xBAB2, 0x7FF1, 0xB0BF, 0x7FF2, 0xC248,
+	0x7FF3, 0xF4E8, 0x7FF4, 0xC249, 0x7FF5, 0xC24A, 0x7FF6, 0xC24B,	0x7FF7, 0xC24C, 0x7FF8, 0xC24D, 0x7FF9, 0xC24E, 0x7FFA, 0xC24F,
+	0x7FFB, 0xB7AD, 0x7FFC, 0xD2ED, 0x7FFD, 0xC250, 0x7FFE, 0xC251,	0x7FFF, 0xC252, 0x8000, 0xD2AB, 0x8001, 0xC0CF, 0x8002, 0xC253,
+	0x8003, 0xBFBC, 0x8004, 0xEBA3, 0x8005, 0xD5DF, 0x8006, 0xEAC8,	0x8007, 0xC254, 0x8008, 0xC255, 0x8009, 0xC256, 0x800A, 0xC257,
+	0x800B, 0xF1F3, 0x800C, 0xB6F8, 0x800D, 0xCBA3, 0x800E, 0xC258,	0x800F, 0xC259, 0x8010, 0xC4CD, 0x8011, 0xC25A, 0x8012, 0xF1E7,
+	0x8013, 0xC25B, 0x8014, 0xF1E8, 0x8015, 0xB8FB, 0x8016, 0xF1E9,	0x8017, 0xBAC4, 0x8018, 0xD4C5, 0x8019, 0xB0D2, 0x801A, 0xC25C,
+	0x801B, 0xC25D, 0x801C, 0xF1EA, 0x801D, 0xC25E, 0x801E, 0xC25F,	0x801F, 0xC260, 0x8020, 0xF1EB, 0x8021, 0xC261, 0x8022, 0xF1EC,
+	0x8023, 0xC262, 0x8024, 0xC263, 0x8025, 0xF1ED, 0x8026, 0xF1EE,	0x8027, 0xF1EF, 0x8028, 0xF1F1, 0x8029, 0xF1F0, 0x802A, 0xC5D5,
+	0x802B, 0xC264, 0x802C, 0xC265, 0x802D, 0xC266, 0x802E, 0xC267,	0x802F, 0xC268, 0x8030, 0xC269, 0x8031, 0xF1F2, 0x8032, 0xC26A,
+	0x8033, 0xB6FA, 0x8034, 0xC26B, 0x8035, 0xF1F4, 0x8036, 0xD2AE,	0x8037, 0xDEC7, 0x8038, 0xCBCA, 0x8039, 0xC26C, 0x803A, 0xC26D,
+	0x803B, 0xB3DC, 0x803C, 0xC26E, 0x803D, 0xB5A2, 0x803E, 0xC26F,	0x803F, 0xB9A2, 0x8040, 0xC270, 0x8041, 0xC271, 0x8042, 0xC4F4,
+	0x8043, 0xF1F5, 0x8044, 0xC272, 0x8045, 0xC273, 0x8046, 0xF1F6,	0x8047, 0xC274, 0x8048, 0xC275, 0x8049, 0xC276, 0x804A, 0xC1C4,
+	0x804B, 0xC1FB, 0x804C, 0xD6B0, 0x804D, 0xF1F7, 0x804E, 0xC277,	0x804F, 0xC278, 0x8050, 0xC279, 0x8051, 0xC27A, 0x8052, 0xF1F8,
+	0x8053, 0xC27B, 0x8054, 0xC1AA, 0x8055, 0xC27C, 0x8056, 0xC27D,	0x8057, 0xC27E, 0x8058, 0xC6B8, 0x8059, 0xC280, 0x805A, 0xBEDB,
+	0x805B, 0xC281, 0x805C, 0xC282, 0x805D, 0xC283, 0x805E, 0xC284,	0x805F, 0xC285, 0x8060, 0xC286, 0x8061, 0xC287, 0x8062, 0xC288,
+	0x8063, 0xC289, 0x8064, 0xC28A, 0x8065, 0xC28B, 0x8066, 0xC28C,	0x8067, 0xC28D, 0x8068, 0xC28E, 0x8069, 0xF1F9, 0x806A, 0xB4CF,
+	0x806B, 0xC28F, 0x806C, 0xC290, 0x806D, 0xC291, 0x806E, 0xC292,	0x806F, 0xC293, 0x8070, 0xC294, 0x8071, 0xF1FA, 0x8072, 0xC295,
+	0x8073, 0xC296, 0x8074, 0xC297, 0x8075, 0xC298, 0x8076, 0xC299,	0x8077, 0xC29A, 0x8078, 0xC29B, 0x8079, 0xC29C, 0x807A, 0xC29D,
+	0x807B, 0xC29E, 0x807C, 0xC29F, 0x807D, 0xC2A0, 0x807E, 0xC340,	0x807F, 0xEDB2, 0x8080, 0xEDB1, 0x8081, 0xC341, 0x8082, 0xC342,
+	0x8083, 0xCBE0, 0x8084, 0xD2DE, 0x8085, 0xC343, 0x8086, 0xCBC1,	0x8087, 0xD5D8, 0x8088, 0xC344, 0x8089, 0xC8E2, 0x808A, 0xC345,
+	0x808B, 0xC0DF, 0x808C, 0xBCA1, 0x808D, 0xC346, 0x808E, 0xC347,	0x808F, 0xC348, 0x8090, 0xC349, 0x8091, 0xC34A, 0x8092, 0xC34B,
+	0x8093, 0xEBC1, 0x8094, 0xC34C, 0x8095, 0xC34D, 0x8096, 0xD0A4,	0x8097, 0xC34E, 0x8098, 0xD6E2, 0x8099, 0xC34F, 0x809A, 0xB6C7,
+	0x809B, 0xB8D8, 0x809C, 0xEBC0, 0x809D, 0xB8CE, 0x809E, 0xC350,	0x809F, 0xEBBF, 0x80A0, 0xB3A6, 0x80A1, 0xB9C9, 0x80A2, 0xD6AB,
+	0x80A3, 0xC351, 0x80A4, 0xB7F4, 0x80A5, 0xB7CA, 0x80A6, 0xC352,	0x80A7, 0xC353, 0x80A8, 0xC354, 0x80A9, 0xBCE7, 0x80AA, 0xB7BE,
+	0x80AB, 0xEBC6, 0x80AC, 0xC355, 0x80AD, 0xEBC7, 0x80AE, 0xB0B9,	0x80AF, 0xBFCF, 0x80B0, 0xC356, 0x80B1, 0xEBC5, 0x80B2, 0xD3FD,
+	0x80B3, 0xC357, 0x80B4, 0xEBC8, 0x80B5, 0xC358, 0x80B6, 0xC359,	0x80B7, 0xEBC9, 0x80B8, 0xC35A, 0x80B9, 0xC35B, 0x80BA, 0xB7CE,
+	0x80BB, 0xC35C, 0x80BC, 0xEBC2, 0x80BD, 0xEBC4, 0x80BE, 0xC9F6,	0x80BF, 0xD6D7, 0x80C0, 0xD5CD, 0x80C1, 0xD0B2, 0x80C2, 0xEBCF,
+	0x80C3, 0xCEB8, 0x80C4, 0xEBD0, 0x80C5, 0xC35D, 0x80C6, 0xB5A8,	0x80C7, 0xC35E, 0x80C8, 0xC35F, 0x80C9, 0xC360, 0x80CA, 0xC361,
+	0x80CB, 0xC362, 0x80CC, 0xB1B3, 0x80CD, 0xEBD2, 0x80CE, 0xCCA5,	0x80CF, 0xC363, 0x80D0, 0xC364, 0x80D1, 0xC365, 0x80D2, 0xC366,
+	0x80D3, 0xC367, 0x80D4, 0xC368, 0x80D5, 0xC369, 0x80D6, 0xC5D6,	0x80D7, 0xEBD3, 0x80D8, 0xC36A, 0x80D9, 0xEBD1, 0x80DA, 0xC5DF,
+	0x80DB, 0xEBCE, 0x80DC, 0xCAA4, 0x80DD, 0xEBD5, 0x80DE, 0xB0FB,	0x80DF, 0xC36B, 0x80E0, 0xC36C, 0x80E1, 0xBAFA, 0x80E2, 0xC36D,
+	0x80E3, 0xC36E, 0x80E4, 0xD8B7, 0x80E5, 0xF1E3, 0x80E6, 0xC36F,	0x80E7, 0xEBCA, 0x80E8, 0xEBCB, 0x80E9, 0xEBCC, 0x80EA, 0xEBCD,
+	0x80EB, 0xEBD6, 0x80EC, 0xE6C0, 0x80ED, 0xEBD9, 0x80EE, 0xC370,	0x80EF, 0xBFE8, 0x80F0, 0xD2C8, 0x80F1, 0xEBD7, 0x80F2, 0xEBDC,
+	0x80F3, 0xB8EC, 0x80F4, 0xEBD8, 0x80F5, 0xC371, 0x80F6, 0xBDBA,	0x80F7, 0xC372, 0x80F8, 0xD0D8, 0x80F9, 0xC373, 0x80FA, 0xB0B7,
+	0x80FB, 0xC374, 0x80FC, 0xEBDD, 0x80FD, 0xC4DC, 0x80FE, 0xC375,	0x80FF, 0xC376, 0x8100, 0xC377, 0x8101, 0xC378, 0x8102, 0xD6AC,
+	0x8103, 0xC379, 0x8104, 0xC37A, 0x8105, 0xC37B, 0x8106, 0xB4E0,	0x8107, 0xC37C, 0x8108, 0xC37D, 0x8109, 0xC2F6, 0x810A, 0xBCB9,
+	0x810B, 0xC37E, 0x810C, 0xC380, 0x810D, 0xEBDA, 0x810E, 0xEBDB,	0x810F, 0xD4E0, 0x8110, 0xC6EA, 0x8111, 0xC4D4, 0x8112, 0xEBDF,
+	0x8113, 0xC5A7, 0x8114, 0xD9F5, 0x8115, 0xC381, 0x8116, 0xB2B1,	0x8117, 0xC382, 0x8118, 0xEBE4, 0x8119, 0xC383, 0x811A, 0xBDC5,
+	0x811B, 0xC384, 0x811C, 0xC385, 0x811D, 0xC386, 0x811E, 0xEBE2,	0x811F, 0xC387, 0x8120, 0xC388, 0x8121, 0xC389, 0x8122, 0xC38A,
+	0x8123, 0xC38B, 0x8124, 0xC38C, 0x8125, 0xC38D, 0x8126, 0xC38E,	0x8127, 0xC38F, 0x8128, 0xC390, 0x8129, 0xC391, 0x812A, 0xC392,
+	0x812B, 0xC393, 0x812C, 0xEBE3, 0x812D, 0xC394, 0x812E, 0xC395,	0x812F, 0xB8AC, 0x8130, 0xC396, 0x8131, 0xCDD1, 0x8132, 0xEBE5,
+	0x8133, 0xC397, 0x8134, 0xC398, 0x8135, 0xC399, 0x8136, 0xEBE1,	0x8137, 0xC39A, 0x8138, 0xC1B3, 0x8139, 0xC39B, 0x813A, 0xC39C,
+	0x813B, 0xC39D, 0x813C, 0xC39E, 0x813D, 0xC39F, 0x813E, 0xC6A2,	0x813F, 0xC3A0, 0x8140, 0xC440, 0x8141, 0xC441, 0x8142, 0xC442,
+	0x8143, 0xC443, 0x8144, 0xC444, 0x8145, 0xC445, 0x8146, 0xCCF3,	0x8147, 0xC446, 0x8148, 0xEBE6, 0x8149, 0xC447, 0x814A, 0xC0B0,
+	0x814B, 0xD2B8, 0x814C, 0xEBE7, 0x814D, 0xC448, 0x814E, 0xC449,	0x814F, 0xC44A, 0x8150, 0xB8AF, 0x8151, 0xB8AD, 0x8152, 0xC44B,
+	0x8153, 0xEBE8, 0x8154, 0xC7BB, 0x8155, 0xCDF3, 0x8156, 0xC44C,	0x8157, 0xC44D, 0x8158, 0xC44E, 0x8159, 0xEBEA, 0x815A, 0xEBEB,
+	0x815B, 0xC44F, 0x815C, 0xC450, 0x815D, 0xC451, 0x815E, 0xC452,	0x815F, 0xC453, 0x8160, 0xEBED, 0x8161, 0xC454, 0x8162, 0xC455,
+	0x8163, 0xC456, 0x8164, 0xC457, 0x8165, 0xD0C8, 0x8166, 0xC458,	0x8167, 0xEBF2, 0x8168, 0xC459, 0x8169, 0xEBEE, 0x816A, 0xC45A,
+	0x816B, 0xC45B, 0x816C, 0xC45C, 0x816D, 0xEBF1, 0x816E, 0xC8F9,	0x816F, 0xC45D, 0x8170, 0xD1FC, 0x8171, 0xEBEC, 0x8172, 0xC45E,
+	0x8173, 0xC45F, 0x8174, 0xEBE9, 0x8175, 0xC460, 0x8176, 0xC461,	0x8177, 0xC462, 0x8178, 0xC463, 0x8179, 0xB8B9, 0x817A, 0xCFD9,
+	0x817B, 0xC4E5, 0x817C, 0xEBEF, 0x817D, 0xEBF0, 0x817E, 0xCCDA,	0x817F, 0xCDC8, 0x8180, 0xB0F2, 0x8181, 0xC464, 0x8182, 0xEBF6,
+	0x8183, 0xC465, 0x8184, 0xC466, 0x8185, 0xC467, 0x8186, 0xC468,	0x8187, 0xC469, 0x8188, 0xEBF5, 0x8189, 0xC46A, 0x818A, 0xB2B2,
+	0x818B, 0xC46B, 0x818C, 0xC46C, 0x818D, 0xC46D, 0x818E, 0xC46E,	0x818F, 0xB8E0, 0x8190, 0xC46F, 0x8191, 0xEBF7, 0x8192, 0xC470,
+	0x8193, 0xC471, 0x8194, 0xC472, 0x8195, 0xC473, 0x8196, 0xC474,	0x8197, 0xC475, 0x8198, 0xB1EC, 0x8199, 0xC476, 0x819A, 0xC477,
+	0x819B, 0xCCC5, 0x819C, 0xC4A4, 0x819D, 0xCFA5, 0x819E, 0xC478,	0x819F, 0xC479, 0x81A0, 0xC47A, 0x81A1, 0xC47B, 0x81A2, 0xC47C,
+	0x81A3, 0xEBF9, 0x81A4, 0xC47D, 0x81A5, 0xC47E, 0x81A6, 0xECA2,	0x81A7, 0xC480, 0x81A8, 0xC5F2, 0x81A9, 0xC481, 0x81AA, 0xEBFA,
+	0x81AB, 0xC482, 0x81AC, 0xC483, 0x81AD, 0xC484, 0x81AE, 0xC485,	0x81AF, 0xC486, 0x81B0, 0xC487, 0x81B1, 0xC488, 0x81B2, 0xC489,
+	0x81B3, 0xC9C5, 0x81B4, 0xC48A, 0x81B5, 0xC48B, 0x81B6, 0xC48C,	0x81B7, 0xC48D, 0x81B8, 0xC48E, 0x81B9, 0xC48F, 0x81BA, 0xE2DF,
+	0x81BB, 0xEBFE, 0x81BC, 0xC490, 0x81BD, 0xC491, 0x81BE, 0xC492,	0x81BF, 0xC493, 0x81C0, 0xCDCE, 0x81C1, 0xECA1, 0x81C2, 0xB1DB,
+	0x81C3, 0xD3B7, 0x81C4, 0xC494, 0x81C5, 0xC495, 0x81C6, 0xD2DC,	0x81C7, 0xC496, 0x81C8, 0xC497, 0x81C9, 0xC498, 0x81CA, 0xEBFD,
+	0x81CB, 0xC499, 0x81CC, 0xEBFB, 0x81CD, 0xC49A, 0x81CE, 0xC49B,	0x81CF, 0xC49C, 0x81D0, 0xC49D, 0x81D1, 0xC49E, 0x81D2, 0xC49F,
+	0x81D3, 0xC4A0, 0x81D4, 0xC540, 0x81D5, 0xC541, 0x81D6, 0xC542,	0x81D7, 0xC543, 0x81D8, 0xC544, 0x81D9, 0xC545, 0x81DA, 0xC546,
+	0x81DB, 0xC547, 0x81DC, 0xC548, 0x81DD, 0xC549, 0x81DE, 0xC54A,	0x81DF, 0xC54B, 0x81E0, 0xC54C, 0x81E1, 0xC54D, 0x81E2, 0xC54E,
+	0x81E3, 0xB3BC, 0x81E4, 0xC54F, 0x81E5, 0xC550, 0x81E6, 0xC551,	0x81E7, 0xEAB0, 0x81E8, 0xC552, 0x81E9, 0xC553, 0x81EA, 0xD7D4,
+	0x81EB, 0xC554, 0x81EC, 0xF4AB, 0x81ED, 0xB3F4, 0x81EE, 0xC555,	0x81EF, 0xC556, 0x81F0, 0xC557, 0x81F1, 0xC558, 0x81F2, 0xC559,
+	0x81F3, 0xD6C1, 0x81F4, 0xD6C2, 0x81F5, 0xC55A, 0x81F6, 0xC55B,	0x81F7, 0xC55C, 0x81F8, 0xC55D, 0x81F9, 0xC55E, 0x81FA, 0xC55F,
+	0x81FB, 0xD5E9, 0x81FC, 0xBECA, 0x81FD, 0xC560, 0x81FE, 0xF4A7,	0x81FF, 0xC561, 0x8200, 0xD2A8, 0x8201, 0xF4A8, 0x8202, 0xF4A9,
+	0x8203, 0xC562, 0x8204, 0xF4AA, 0x8205, 0xBECB, 0x8206, 0xD3DF,	0x8207, 0xC563, 0x8208, 0xC564, 0x8209, 0xC565, 0x820A, 0xC566,
+	0x820B, 0xC567, 0x820C, 0xC9E0, 0x820D, 0xC9E1, 0x820E, 0xC568,	0x820F, 0xC569, 0x8210, 0xF3C2, 0x8211, 0xC56A, 0x8212, 0xCAE6,
+	0x8213, 0xC56B, 0x8214, 0xCCF2, 0x8215, 0xC56C, 0x8216, 0xC56D,	0x8217, 0xC56E, 0x8218, 0xC56F, 0x8219, 0xC570, 0x821A, 0xC571,
+	0x821B, 0xE2B6, 0x821C, 0xCBB4, 0x821D, 0xC572, 0x821E, 0xCEE8,	0x821F, 0xD6DB, 0x8220, 0xC573, 0x8221, 0xF4AD, 0x8222, 0xF4AE,
+	0x8223, 0xF4AF, 0x8224, 0xC574, 0x8225, 0xC575, 0x8226, 0xC576,	0x8227, 0xC577, 0x8228, 0xF4B2, 0x8229, 0xC578, 0x822A, 0xBABD,
+	0x822B, 0xF4B3, 0x822C, 0xB0E3, 0x822D, 0xF4B0, 0x822E, 0xC579,	0x822F, 0xF4B1, 0x8230, 0xBDA2, 0x8231, 0xB2D5, 0x8232, 0xC57A,
+	0x8233, 0xF4B6, 0x8234, 0xF4B7, 0x8235, 0xB6E6, 0x8236, 0xB2B0,	0x8237, 0xCFCF, 0x8238, 0xF4B4, 0x8239, 0xB4AC, 0x823A, 0xC57B,
+	0x823B, 0xF4B5, 0x823C, 0xC57C, 0x823D, 0xC57D, 0x823E, 0xF4B8,	0x823F, 0xC57E, 0x8240, 0xC580, 0x8241, 0xC581, 0x8242, 0xC582,
+	0x8243, 0xC583, 0x8244, 0xF4B9, 0x8245, 0xC584, 0x8246, 0xC585,	0x8247, 0xCDA7, 0x8248, 0xC586, 0x8249, 0xF4BA, 0x824A, 0xC587,
+	0x824B, 0xF4BB, 0x824C, 0xC588, 0x824D, 0xC589, 0x824E, 0xC58A,	0x824F, 0xF4BC, 0x8250, 0xC58B, 0x8251, 0xC58C, 0x8252, 0xC58D,
+	0x8253, 0xC58E, 0x8254, 0xC58F, 0x8255, 0xC590, 0x8256, 0xC591,	0x8257, 0xC592, 0x8258, 0xCBD2, 0x8259, 0xC593, 0x825A, 0xF4BD,
+	0x825B, 0xC594, 0x825C, 0xC595, 0x825D, 0xC596, 0x825E, 0xC597,	0x825F, 0xF4BE, 0x8260, 0xC598, 0x8261, 0xC599, 0x8262, 0xC59A,
+	0x8263, 0xC59B, 0x8264, 0xC59C, 0x8265, 0xC59D, 0x8266, 0xC59E,	0x8267, 0xC59F, 0x8268, 0xF4BF, 0x8269, 0xC5A0, 0x826A, 0xC640,
+	0x826B, 0xC641, 0x826C, 0xC642, 0x826D, 0xC643, 0x826E, 0xF4DE,	0x826F, 0xC1BC, 0x8270, 0xBCE8, 0x8271, 0xC644, 0x8272, 0xC9AB,
+	0x8273, 0xD1DE, 0x8274, 0xE5F5, 0x8275, 0xC645, 0x8276, 0xC646,	0x8277, 0xC647, 0x8278, 0xC648, 0x8279, 0xDCB3, 0x827A, 0xD2D5,
+	0x827B, 0xC649, 0x827C, 0xC64A, 0x827D, 0xDCB4, 0x827E, 0xB0AC,	0x827F, 0xDCB5, 0x8280, 0xC64B, 0x8281, 0xC64C, 0x8282, 0xBDDA,
+	0x8283, 0xC64D, 0x8284, 0xDCB9, 0x8285, 0xC64E, 0x8286, 0xC64F,	0x8287, 0xC650, 0x8288, 0xD8C2, 0x8289, 0xC651, 0x828A, 0xDCB7,
+	0x828B, 0xD3F3, 0x828C, 0xC652, 0x828D, 0xC9D6, 0x828E, 0xDCBA,	0x828F, 0xDCB6, 0x8290, 0xC653, 0x8291, 0xDCBB, 0x8292, 0xC3A2,
+	0x8293, 0xC654, 0x8294, 0xC655, 0x8295, 0xC656, 0x8296, 0xC657,	0x8297, 0xDCBC, 0x8298, 0xDCC5, 0x8299, 0xDCBD, 0x829A, 0xC658,
+	0x829B, 0xC659, 0x829C, 0xCEDF, 0x829D, 0xD6A5, 0x829E, 0xC65A,	0x829F, 0xDCCF, 0x82A0, 0xC65B, 0x82A1, 0xDCCD, 0x82A2, 0xC65C,
+	0x82A3, 0xC65D, 0x82A4, 0xDCD2, 0x82A5, 0xBDE6, 0x82A6, 0xC2AB,	0x82A7, 0xC65E, 0x82A8, 0xDCB8, 0x82A9, 0xDCCB, 0x82AA, 0xDCCE,
+	0x82AB, 0xDCBE, 0x82AC, 0xB7D2, 0x82AD, 0xB0C5, 0x82AE, 0xDCC7,	0x82AF, 0xD0BE, 0x82B0, 0xDCC1, 0x82B1, 0xBBA8, 0x82B2, 0xC65F,
+	0x82B3, 0xB7BC, 0x82B4, 0xDCCC, 0x82B5, 0xC660, 0x82B6, 0xC661,	0x82B7, 0xDCC6, 0x82B8, 0xDCBF, 0x82B9, 0xC7DB, 0x82BA, 0xC662,
+	0x82BB, 0xC663, 0x82BC, 0xC664, 0x82BD, 0xD1BF, 0x82BE, 0xDCC0,	0x82BF, 0xC665, 0x82C0, 0xC666, 0x82C1, 0xDCCA, 0x82C2, 0xC667,
+	0x82C3, 0xC668, 0x82C4, 0xDCD0, 0x82C5, 0xC669, 0x82C6, 0xC66A,	0x82C7, 0xCEAD, 0x82C8, 0xDCC2, 0x82C9, 0xC66B, 0x82CA, 0xDCC3,
+	0x82CB, 0xDCC8, 0x82CC, 0xDCC9, 0x82CD, 0xB2D4, 0x82CE, 0xDCD1,	0x82CF, 0xCBD5, 0x82D0, 0xC66C, 0x82D1, 0xD4B7, 0x82D2, 0xDCDB,
+	0x82D3, 0xDCDF, 0x82D4, 0xCCA6, 0x82D5, 0xDCE6, 0x82D6, 0xC66D,	0x82D7, 0xC3E7, 0x82D8, 0xDCDC, 0x82D9, 0xC66E, 0x82DA, 0xC66F,
+	0x82DB, 0xBFC1, 0x82DC, 0xDCD9, 0x82DD, 0xC670, 0x82DE, 0xB0FA,	0x82DF, 0xB9B6, 0x82E0, 0xDCE5, 0x82E1, 0xDCD3, 0x82E2, 0xC671,
+	0x82E3, 0xDCC4, 0x82E4, 0xDCD6, 0x82E5, 0xC8F4, 0x82E6, 0xBFE0,	0x82E7, 0xC672, 0x82E8, 0xC673, 0x82E9, 0xC674, 0x82EA, 0xC675,
+	0x82EB, 0xC9BB, 0x82EC, 0xC676, 0x82ED, 0xC677, 0x82EE, 0xC678,	0x82EF, 0xB1BD, 0x82F0, 0xC679, 0x82F1, 0xD3A2, 0x82F2, 0xC67A,
+	0x82F3, 0xC67B, 0x82F4, 0xDCDA, 0x82F5, 0xC67C, 0x82F6, 0xC67D,	0x82F7, 0xDCD5, 0x82F8, 0xC67E, 0x82F9, 0xC6BB, 0x82FA, 0xC680,
+	0x82FB, 0xDCDE, 0x82FC, 0xC681, 0x82FD, 0xC682, 0x82FE, 0xC683,	0x82FF, 0xC684, 0x8300, 0xC685, 0x8301, 0xD7C2, 0x8302, 0xC3AF,
+	0x8303, 0xB7B6, 0x8304, 0xC7D1, 0x8305, 0xC3A9, 0x8306, 0xDCE2,	0x8307, 0xDCD8, 0x8308, 0xDCEB, 0x8309, 0xDCD4, 0x830A, 0xC686,
+	0x830B, 0xC687, 0x830C, 0xDCDD, 0x830D, 0xC688, 0x830E, 0xBEA5,	0x830F, 0xDCD7, 0x8310, 0xC689, 0x8311, 0xDCE0, 0x8312, 0xC68A,
+	0x8313, 0xC68B, 0x8314, 0xDCE3, 0x8315, 0xDCE4, 0x8316, 0xC68C,	0x8317, 0xDCF8, 0x8318, 0xC68D, 0x8319, 0xC68E, 0x831A, 0xDCE1,
+	0x831B, 0xDDA2, 0x831C, 0xDCE7, 0x831D, 0xC68F, 0x831E, 0xC690,	0x831F, 0xC691, 0x8320, 0xC692, 0x8321, 0xC693, 0x8322, 0xC694,
+	0x8323, 0xC695, 0x8324, 0xC696, 0x8325, 0xC697, 0x8326, 0xC698,	0x8327, 0xBCEB, 0x8328, 0xB4C4, 0x8329, 0xC699, 0x832A, 0xC69A,
+	0x832B, 0xC3A3, 0x832C, 0xB2E7, 0x832D, 0xDCFA, 0x832E, 0xC69B,	0x832F, 0xDCF2, 0x8330, 0xC69C, 0x8331, 0xDCEF, 0x8332, 0xC69D,
+	0x8333, 0xDCFC, 0x8334, 0xDCEE, 0x8335, 0xD2F0, 0x8336, 0xB2E8,	0x8337, 0xC69E, 0x8338, 0xC8D7, 0x8339, 0xC8E3, 0x833A, 0xDCFB,
+	0x833B, 0xC69F, 0x833C, 0xDCED, 0x833D, 0xC6A0, 0x833E, 0xC740,	0x833F, 0xC741, 0x8340, 0xDCF7, 0x8341, 0xC742, 0x8342, 0xC743,
+	0x8343, 0xDCF5, 0x8344, 0xC744, 0x8345, 0xC745, 0x8346, 0xBEA3,	0x8347, 0xDCF4, 0x8348, 0xC746, 0x8349, 0xB2DD, 0x834A, 0xC747,
+	0x834B, 0xC748, 0x834C, 0xC749, 0x834D, 0xC74A, 0x834E, 0xC74B,	0x834F, 0xDCF3, 0x8350, 0xBCF6, 0x8351, 0xDCE8, 0x8352, 0xBBC4,
+	0x8353, 0xC74C, 0x8354, 0xC0F3, 0x8355, 0xC74D, 0x8356, 0xC74E,	0x8357, 0xC74F, 0x8358, 0xC750, 0x8359, 0xC751, 0x835A, 0xBCD4,
+	0x835B, 0xDCE9, 0x835C, 0xDCEA, 0x835D, 0xC752, 0x835E, 0xDCF1,	0x835F, 0xDCF6, 0x8360, 0xDCF9, 0x8361, 0xB5B4, 0x8362, 0xC753,
+	0x8363, 0xC8D9, 0x8364, 0xBBE7, 0x8365, 0xDCFE, 0x8366, 0xDCFD,	0x8367, 0xD3AB, 0x8368, 0xDDA1, 0x8369, 0xDDA3, 0x836A, 0xDDA5,
+	0x836B, 0xD2F1, 0x836C, 0xDDA4, 0x836D, 0xDDA6, 0x836E, 0xDDA7,	0x836F, 0xD2A9, 0x8370, 0xC754, 0x8371, 0xC755, 0x8372, 0xC756,
+	0x8373, 0xC757, 0x8374, 0xC758, 0x8375, 0xC759, 0x8376, 0xC75A,	0x8377, 0xBAC9, 0x8378, 0xDDA9, 0x8379, 0xC75B, 0x837A, 0xC75C,
+	0x837B, 0xDDB6, 0x837C, 0xDDB1, 0x837D, 0xDDB4, 0x837E, 0xC75D,	0x837F, 0xC75E, 0x8380, 0xC75F, 0x8381, 0xC760, 0x8382, 0xC761,
+	0x8383, 0xC762, 0x8384, 0xC763, 0x8385, 0xDDB0, 0x8386, 0xC6CE,	0x8387, 0xC764, 0x8388, 0xC765, 0x8389, 0xC0F2, 0x838A, 0xC766,
+	0x838B, 0xC767, 0x838C, 0xC768, 0x838D, 0xC769, 0x838E, 0xC9AF,	0x838F, 0xC76A, 0x8390, 0xC76B, 0x8391, 0xC76C, 0x8392, 0xDCEC,
+	0x8393, 0xDDAE, 0x8394, 0xC76D, 0x8395, 0xC76E, 0x8396, 0xC76F,	0x8397, 0xC770, 0x8398, 0xDDB7, 0x8399, 0xC771, 0x839A, 0xC772,
+	0x839B, 0xDCF0, 0x839C, 0xDDAF, 0x839D, 0xC773, 0x839E, 0xDDB8,	0x839F, 0xC774, 0x83A0, 0xDDAC, 0x83A1, 0xC775, 0x83A2, 0xC776,
+	0x83A3, 0xC777, 0x83A4, 0xC778, 0x83A5, 0xC779, 0x83A6, 0xC77A,	0x83A7, 0xC77B, 0x83A8, 0xDDB9, 0x83A9, 0xDDB3, 0x83AA, 0xDDAD,
+	0x83AB, 0xC4AA, 0x83AC, 0xC77C, 0x83AD, 0xC77D, 0x83AE, 0xC77E,	0x83AF, 0xC780, 0x83B0, 0xDDA8, 0x83B1, 0xC0B3, 0x83B2, 0xC1AB,
+	0x83B3, 0xDDAA, 0x83B4, 0xDDAB, 0x83B5, 0xC781, 0x83B6, 0xDDB2,	0x83B7, 0xBBF1, 0x83B8, 0xDDB5, 0x83B9, 0xD3A8, 0x83BA, 0xDDBA,
+	0x83BB, 0xC782, 0x83BC, 0xDDBB, 0x83BD, 0xC3A7, 0x83BE, 0xC783,	0x83BF, 0xC784, 0x83C0, 0xDDD2, 0x83C1, 0xDDBC, 0x83C2, 0xC785,
+	0x83C3, 0xC786, 0x83C4, 0xC787, 0x83C5, 0xDDD1, 0x83C6, 0xC788,	0x83C7, 0xB9BD, 0x83C8, 0xC789, 0x83C9, 0xC78A, 0x83CA, 0xBED5,
+	0x83CB, 0xC78B, 0x83CC, 0xBEFA, 0x83CD, 0xC78C, 0x83CE, 0xC78D,	0x83CF, 0xBACA, 0x83D0, 0xC78E, 0x83D1, 0xC78F, 0x83D2, 0xC790,
+	0x83D3, 0xC791, 0x83D4, 0xDDCA, 0x83D5, 0xC792, 0x83D6, 0xDDC5,	0x83D7, 0xC793, 0x83D8, 0xDDBF, 0x83D9, 0xC794, 0x83DA, 0xC795,
+	0x83DB, 0xC796, 0x83DC, 0xB2CB, 0x83DD, 0xDDC3, 0x83DE, 0xC797,	0x83DF, 0xDDCB, 0x83E0, 0xB2A4, 0x83E1, 0xDDD5, 0x83E2, 0xC798,
+	0x83E3, 0xC799, 0x83E4, 0xC79A, 0x83E5, 0xDDBE, 0x83E6, 0xC79B,	0x83E7, 0xC79C, 0x83E8, 0xC79D, 0x83E9, 0xC6D0, 0x83EA, 0xDDD0,
+	0x83EB, 0xC79E, 0x83EC, 0xC79F, 0x83ED, 0xC7A0, 0x83EE, 0xC840,	0x83EF, 0xC841, 0x83F0, 0xDDD4, 0x83F1, 0xC1E2, 0x83F2, 0xB7C6,
+	0x83F3, 0xC842, 0x83F4, 0xC843, 0x83F5, 0xC844, 0x83F6, 0xC845,	0x83F7, 0xC846, 0x83F8, 0xDDCE, 0x83F9, 0xDDCF, 0x83FA, 0xC847,
+	0x83FB, 0xC848, 0x83FC, 0xC849, 0x83FD, 0xDDC4, 0x83FE, 0xC84A,	0x83FF, 0xC84B, 0x8400, 0xC84C, 0x8401, 0xDDBD, 0x8402, 0xC84D,
+	0x8403, 0xDDCD, 0x8404, 0xCCD1, 0x8405, 0xC84E, 0x8406, 0xDDC9,	0x8407, 0xC84F, 0x8408, 0xC850, 0x8409, 0xC851, 0x840A, 0xC852,
+	0x840B, 0xDDC2, 0x840C, 0xC3C8, 0x840D, 0xC6BC, 0x840E, 0xCEAE,	0x840F, 0xDDCC, 0x8410, 0xC853, 0x8411, 0xDDC8, 0x8412, 0xC854,
+	0x8413, 0xC855, 0x8414, 0xC856, 0x8415, 0xC857, 0x8416, 0xC858,	0x8417, 0xC859, 0x8418, 0xDDC1, 0x8419, 0xC85A, 0x841A, 0xC85B,
+	0x841B, 0xC85C, 0x841C, 0xDDC6, 0x841D, 0xC2DC, 0x841E, 0xC85D,	0x841F, 0xC85E, 0x8420, 0xC85F, 0x8421, 0xC860, 0x8422, 0xC861,
+	0x8423, 0xC862, 0x8424, 0xD3A9, 0x8425, 0xD3AA, 0x8426, 0xDDD3,	0x8427, 0xCFF4, 0x8428, 0xC8F8, 0x8429, 0xC863, 0x842A, 0xC864,
+	0x842B, 0xC865, 0x842C, 0xC866, 0x842D, 0xC867, 0x842E, 0xC868,	0x842F, 0xC869, 0x8430, 0xC86A, 0x8431, 0xDDE6, 0x8432, 0xC86B,
+	0x8433, 0xC86C, 0x8434, 0xC86D, 0x8435, 0xC86E, 0x8436, 0xC86F,	0x8437, 0xC870, 0x8438, 0xDDC7, 0x8439, 0xC871, 0x843A, 0xC872,
+	0x843B, 0xC873, 0x843C, 0xDDE0, 0x843D, 0xC2E4, 0x843E, 0xC874,	0x843F, 0xC875, 0x8440, 0xC876, 0x8441, 0xC877, 0x8442, 0xC878,
+	0x8443, 0xC879, 0x8444, 0xC87A, 0x8445, 0xC87B, 0x8446, 0xDDE1,	0x8447, 0xC87C, 0x8448, 0xC87D, 0x8449, 0xC87E, 0x844A, 0xC880,
+	0x844B, 0xC881, 0x844C, 0xC882, 0x844D, 0xC883, 0x844E, 0xC884,	0x844F, 0xC885, 0x8450, 0xC886, 0x8451, 0xDDD7, 0x8452, 0xC887,
+	0x8453, 0xC888, 0x8454, 0xC889, 0x8455, 0xC88A, 0x8456, 0xC88B,	0x8457, 0xD6F8, 0x8458, 0xC88C, 0x8459, 0xDDD9, 0x845A, 0xDDD8,
+	0x845B, 0xB8F0, 0x845C, 0xDDD6, 0x845D, 0xC88D, 0x845E, 0xC88E,	0x845F, 0xC88F, 0x8460, 0xC890, 0x8461, 0xC6CF, 0x8462, 0xC891,
+	0x8463, 0xB6AD, 0x8464, 0xC892, 0x8465, 0xC893, 0x8466, 0xC894,	0x8467, 0xC895, 0x8468, 0xC896, 0x8469, 0xDDE2, 0x846A, 0xC897,
+	0x846B, 0xBAF9, 0x846C, 0xD4E1, 0x846D, 0xDDE7, 0x846E, 0xC898,	0x846F, 0xC899, 0x8470, 0xC89A, 0x8471, 0xB4D0, 0x8472, 0xC89B,
+	0x8473, 0xDDDA, 0x8474, 0xC89C, 0x8475, 0xBFFB, 0x8476, 0xDDE3,	0x8477, 0xC89D, 0x8478, 0xDDDF, 0x8479, 0xC89E, 0x847A, 0xDDDD,
+	0x847B, 0xC89F, 0x847C, 0xC8A0, 0x847D, 0xC940, 0x847E, 0xC941,	0x847F, 0xC942, 0x8480, 0xC943, 0x8481, 0xC944, 0x8482, 0xB5D9,
+	0x8483, 0xC945, 0x8484, 0xC946, 0x8485, 0xC947, 0x8486, 0xC948,	0x8487, 0xDDDB, 0x8488, 0xDDDC, 0x8489, 0xDDDE, 0x848A, 0xC949,
+	0x848B, 0xBDAF, 0x848C, 0xDDE4, 0x848D, 0xC94A, 0x848E, 0xDDE5,	0x848F, 0xC94B, 0x8490, 0xC94C, 0x8491, 0xC94D, 0x8492, 0xC94E,
+	0x8493, 0xC94F, 0x8494, 0xC950, 0x8495, 0xC951, 0x8496, 0xC952,	0x8497, 0xDDF5, 0x8498, 0xC953, 0x8499, 0xC3C9, 0x849A, 0xC954,
+	0x849B, 0xC955, 0x849C, 0xCBE2, 0x849D, 0xC956, 0x849E, 0xC957,	0x849F, 0xC958, 0x84A0, 0xC959, 0x84A1, 0xDDF2, 0x84A2, 0xC95A,
+	0x84A3, 0xC95B, 0x84A4, 0xC95C, 0x84A5, 0xC95D, 0x84A6, 0xC95E,	0x84A7, 0xC95F, 0x84A8, 0xC960, 0x84A9, 0xC961, 0x84AA, 0xC962,
+	0x84AB, 0xC963, 0x84AC, 0xC964, 0x84AD, 0xC965, 0x84AE, 0xC966,	0x84AF, 0xD8E1, 0x84B0, 0xC967, 0x84B1, 0xC968, 0x84B2, 0xC6D1,
+	0x84B3, 0xC969, 0x84B4, 0xDDF4, 0x84B5, 0xC96A, 0x84B6, 0xC96B,	0x84B7, 0xC96C, 0x84B8, 0xD5F4, 0x84B9, 0xDDF3, 0x84BA, 0xDDF0,
+	0x84BB, 0xC96D, 0x84BC, 0xC96E, 0x84BD, 0xDDEC, 0x84BE, 0xC96F,	0x84BF, 0xDDEF, 0x84C0, 0xC970, 0x84C1, 0xDDE8, 0x84C2, 0xC971,
+	0x84C3, 0xC972, 0x84C4, 0xD0EE, 0x84C5, 0xC973, 0x84C6, 0xC974,	0x84C7, 0xC975, 0x84C8, 0xC976, 0x84C9, 0xC8D8, 0x84CA, 0xDDEE,
+	0x84CB, 0xC977, 0x84CC, 0xC978, 0x84CD, 0xDDE9, 0x84CE, 0xC979,	0x84CF, 0xC97A, 0x84D0, 0xDDEA, 0x84D1, 0xCBF2, 0x84D2, 0xC97B,
+	0x84D3, 0xDDED, 0x84D4, 0xC97C, 0x84D5, 0xC97D, 0x84D6, 0xB1CD,	0x84D7, 0xC97E, 0x84D8, 0xC980, 0x84D9, 0xC981, 0x84DA, 0xC982,
+	0x84DB, 0xC983, 0x84DC, 0xC984, 0x84DD, 0xC0B6, 0x84DE, 0xC985,	0x84DF, 0xBCBB, 0x84E0, 0xDDF1, 0x84E1, 0xC986, 0x84E2, 0xC987,
+	0x84E3, 0xDDF7, 0x84E4, 0xC988, 0x84E5, 0xDDF6, 0x84E6, 0xDDEB,	0x84E7, 0xC989, 0x84E8, 0xC98A, 0x84E9, 0xC98B, 0x84EA, 0xC98C,
+	0x84EB, 0xC98D, 0x84EC, 0xC5EE, 0x84ED, 0xC98E, 0x84EE, 0xC98F,	0x84EF, 0xC990, 0x84F0, 0xDDFB, 0x84F1, 0xC991, 0x84F2, 0xC992,
+	0x84F3, 0xC993, 0x84F4, 0xC994, 0x84F5, 0xC995, 0x84F6, 0xC996,	0x84F7, 0xC997, 0x84F8, 0xC998, 0x84F9, 0xC999, 0x84FA, 0xC99A,
+	0x84FB, 0xC99B, 0x84FC, 0xDEA4, 0x84FD, 0xC99C, 0x84FE, 0xC99D,	0x84FF, 0xDEA3, 0x8500, 0xC99E, 0x8501, 0xC99F, 0x8502, 0xC9A0,
+	0x8503, 0xCA40, 0x8504, 0xCA41, 0x8505, 0xCA42, 0x8506, 0xCA43,	0x8507, 0xCA44, 0x8508, 0xCA45, 0x8509, 0xCA46, 0x850A, 0xCA47,
+	0x850B, 0xCA48, 0x850C, 0xDDF8, 0x850D, 0xCA49, 0x850E, 0xCA4A,	0x850F, 0xCA4B, 0x8510, 0xCA4C, 0x8511, 0xC3EF, 0x8512, 0xCA4D,
+	0x8513, 0xC2FB, 0x8514, 0xCA4E, 0x8515, 0xCA4F, 0x8516, 0xCA50,	0x8517, 0xD5E1, 0x8518, 0xCA51, 0x8519, 0xCA52, 0x851A, 0xCEB5,
+	0x851B, 0xCA53, 0x851C, 0xCA54, 0x851D, 0xCA55, 0x851E, 0xCA56,	0x851F, 0xDDFD, 0x8520, 0xCA57, 0x8521, 0xB2CC, 0x8522, 0xCA58,
+	0x8523, 0xCA59, 0x8524, 0xCA5A, 0x8525, 0xCA5B, 0x8526, 0xCA5C,	0x8527, 0xCA5D, 0x8528, 0xCA5E, 0x8529, 0xCA5F, 0x852A, 0xCA60,
+	0x852B, 0xC4E8, 0x852C, 0xCADF, 0x852D, 0xCA61, 0x852E, 0xCA62,	0x852F, 0xCA63, 0x8530, 0xCA64, 0x8531, 0xCA65, 0x8532, 0xCA66,
+	0x8533, 0xCA67, 0x8534, 0xCA68, 0x8535, 0xCA69, 0x8536, 0xCA6A,	0x8537, 0xC7BE, 0x8538, 0xDDFA, 0x8539, 0xDDFC, 0x853A, 0xDDFE,
+	0x853B, 0xDEA2, 0x853C, 0xB0AA, 0x853D, 0xB1CE, 0x853E, 0xCA6B,	0x853F, 0xCA6C, 0x8540, 0xCA6D, 0x8541, 0xCA6E, 0x8542, 0xCA6F,
+	0x8543, 0xDEAC, 0x8544, 0xCA70, 0x8545, 0xCA71, 0x8546, 0xCA72,	0x8547, 0xCA73, 0x8548, 0xDEA6, 0x8549, 0xBDB6, 0x854A, 0xC8EF,
+	0x854B, 0xCA74, 0x854C, 0xCA75, 0x854D, 0xCA76, 0x854E, 0xCA77,	0x854F, 0xCA78, 0x8550, 0xCA79, 0x8551, 0xCA7A, 0x8552, 0xCA7B,
+	0x8553, 0xCA7C, 0x8554, 0xCA7D, 0x8555, 0xCA7E, 0x8556, 0xDEA1,	0x8557, 0xCA80, 0x8558, 0xCA81, 0x8559, 0xDEA5, 0x855A, 0xCA82,
+	0x855B, 0xCA83, 0x855C, 0xCA84, 0x855D, 0xCA85, 0x855E, 0xDEA9,	0x855F, 0xCA86, 0x8560, 0xCA87, 0x8561, 0xCA88, 0x8562, 0xCA89,
+	0x8563, 0xCA8A, 0x8564, 0xDEA8, 0x8565, 0xCA8B, 0x8566, 0xCA8C,	0x8567, 0xCA8D, 0x8568, 0xDEA7, 0x8569, 0xCA8E, 0x856A, 0xCA8F,
+	0x856B, 0xCA90, 0x856C, 0xCA91, 0x856D, 0xCA92, 0x856E, 0xCA93,	0x856F, 0xCA94, 0x8570, 0xCA95, 0x8571, 0xCA96, 0x8572, 0xDEAD,
+	0x8573, 0xCA97, 0x8574, 0xD4CC, 0x8575, 0xCA98, 0x8576, 0xCA99,	0x8577, 0xCA9A, 0x8578, 0xCA9B, 0x8579, 0xDEB3, 0x857A, 0xDEAA,
+	0x857B, 0xDEAE, 0x857C, 0xCA9C, 0x857D, 0xCA9D, 0x857E, 0xC0D9,	0x857F, 0xCA9E, 0x8580, 0xCA9F, 0x8581, 0xCAA0, 0x8582, 0xCB40,
+	0x8583, 0xCB41, 0x8584, 0xB1A1, 0x8585, 0xDEB6, 0x8586, 0xCB42,	0x8587, 0xDEB1, 0x8588, 0xCB43, 0x8589, 0xCB44, 0x858A, 0xCB45,
+	0x858B, 0xCB46, 0x858C, 0xCB47, 0x858D, 0xCB48, 0x858E, 0xCB49,	0x858F, 0xDEB2, 0x8590, 0xCB4A, 0x8591, 0xCB4B, 0x8592, 0xCB4C,
+	0x8593, 0xCB4D, 0x8594, 0xCB4E, 0x8595, 0xCB4F, 0x8596, 0xCB50,	0x8597, 0xCB51, 0x8598, 0xCB52, 0x8599, 0xCB53, 0x859A, 0xCB54,
+	0x859B, 0xD1A6, 0x859C, 0xDEB5, 0x859D, 0xCB55, 0x859E, 0xCB56,	0x859F, 0xCB57, 0x85A0, 0xCB58, 0x85A1, 0xCB59, 0x85A2, 0xCB5A,
+	0x85A3, 0xCB5B, 0x85A4, 0xDEAF, 0x85A5, 0xCB5C, 0x85A6, 0xCB5D,	0x85A7, 0xCB5E, 0x85A8, 0xDEB0, 0x85A9, 0xCB5F, 0x85AA, 0xD0BD,
+	0x85AB, 0xCB60, 0x85AC, 0xCB61, 0x85AD, 0xCB62, 0x85AE, 0xDEB4,	0x85AF, 0xCAED, 0x85B0, 0xDEB9, 0x85B1, 0xCB63, 0x85B2, 0xCB64,
+	0x85B3, 0xCB65, 0x85B4, 0xCB66, 0x85B5, 0xCB67, 0x85B6, 0xCB68,	0x85B7, 0xDEB8, 0x85B8, 0xCB69, 0x85B9, 0xDEB7, 0x85BA, 0xCB6A,
+	0x85BB, 0xCB6B, 0x85BC, 0xCB6C, 0x85BD, 0xCB6D, 0x85BE, 0xCB6E,	0x85BF, 0xCB6F, 0x85C0, 0xCB70, 0x85C1, 0xDEBB, 0x85C2, 0xCB71,
+	0x85C3, 0xCB72, 0x85C4, 0xCB73, 0x85C5, 0xCB74, 0x85C6, 0xCB75,	0x85C7, 0xCB76, 0x85C8, 0xCB77, 0x85C9, 0xBDE5, 0x85CA, 0xCB78,
+	0x85CB, 0xCB79, 0x85CC, 0xCB7A, 0x85CD, 0xCB7B, 0x85CE, 0xCB7C,	0x85CF, 0xB2D8, 0x85D0, 0xC3EA, 0x85D1, 0xCB7D, 0x85D2, 0xCB7E,
+	0x85D3, 0xDEBA, 0x85D4, 0xCB80, 0x85D5, 0xC5BA, 0x85D6, 0xCB81,	0x85D7, 0xCB82, 0x85D8, 0xCB83, 0x85D9, 0xCB84, 0x85DA, 0xCB85,
+	0x85DB, 0xCB86, 0x85DC, 0xDEBC, 0x85DD, 0xCB87, 0x85DE, 0xCB88,	0x85DF, 0xCB89, 0x85E0, 0xCB8A, 0x85E1, 0xCB8B, 0x85E2, 0xCB8C,
+	0x85E3, 0xCB8D, 0x85E4, 0xCCD9, 0x85E5, 0xCB8E, 0x85E6, 0xCB8F,	0x85E7, 0xCB90, 0x85E8, 0xCB91, 0x85E9, 0xB7AA, 0x85EA, 0xCB92,
+	0x85EB, 0xCB93, 0x85EC, 0xCB94, 0x85ED, 0xCB95, 0x85EE, 0xCB96,	0x85EF, 0xCB97, 0x85F0, 0xCB98, 0x85F1, 0xCB99, 0x85F2, 0xCB9A,
+	0x85F3, 0xCB9B, 0x85F4, 0xCB9C, 0x85F5, 0xCB9D, 0x85F6, 0xCB9E,	0x85F7, 0xCB9F, 0x85F8, 0xCBA0, 0x85F9, 0xCC40, 0x85FA, 0xCC41,
+	0x85FB, 0xD4E5, 0x85FC, 0xCC42, 0x85FD, 0xCC43, 0x85FE, 0xCC44,	0x85FF, 0xDEBD, 0x8600, 0xCC45, 0x8601, 0xCC46, 0x8602, 0xCC47,
+	0x8603, 0xCC48, 0x8604, 0xCC49, 0x8605, 0xDEBF, 0x8606, 0xCC4A,	0x8607, 0xCC4B, 0x8608, 0xCC4C, 0x8609, 0xCC4D, 0x860A, 0xCC4E,
+	0x860B, 0xCC4F, 0x860C, 0xCC50, 0x860D, 0xCC51, 0x860E, 0xCC52,	0x860F, 0xCC53, 0x8610, 0xCC54, 0x8611, 0xC4A2, 0x8612, 0xCC55,
+	0x8613, 0xCC56, 0x8614, 0xCC57, 0x8615, 0xCC58, 0x8616, 0xDEC1,	0x8617, 0xCC59, 0x8618, 0xCC5A, 0x8619, 0xCC5B, 0x861A, 0xCC5C,
+	0x861B, 0xCC5D, 0x861C, 0xCC5E, 0x861D, 0xCC5F, 0x861E, 0xCC60,	0x861F, 0xCC61, 0x8620, 0xCC62, 0x8621, 0xCC63, 0x8622, 0xCC64,
+	0x8623, 0xCC65, 0x8624, 0xCC66, 0x8625, 0xCC67, 0x8626, 0xCC68,	0x8627, 0xDEBE, 0x8628, 0xCC69, 0x8629, 0xDEC0, 0x862A, 0xCC6A,
+	0x862B, 0xCC6B, 0x862C, 0xCC6C, 0x862D, 0xCC6D, 0x862E, 0xCC6E,	0x862F, 0xCC6F, 0x8630, 0xCC70, 0x8631, 0xCC71, 0x8632, 0xCC72,
+	0x8633, 0xCC73, 0x8634, 0xCC74, 0x8635, 0xCC75, 0x8636, 0xCC76,	0x8637, 0xCC77, 0x8638, 0xD5BA, 0x8639, 0xCC78, 0x863A, 0xCC79,
+	0x863B, 0xCC7A, 0x863C, 0xDEC2, 0x863D, 0xCC7B, 0x863E, 0xCC7C,	0x863F, 0xCC7D, 0x8640, 0xCC7E, 0x8641, 0xCC80, 0x8642, 0xCC81,
+	0x8643, 0xCC82, 0x8644, 0xCC83, 0x8645, 0xCC84, 0x8646, 0xCC85,	0x8647, 0xCC86, 0x8648, 0xCC87, 0x8649, 0xCC88, 0x864A, 0xCC89,
+	0x864B, 0xCC8A, 0x864C, 0xCC8B, 0x864D, 0xF2AE, 0x864E, 0xBBA2,	0x864F, 0xC2B2, 0x8650, 0xC5B0, 0x8651, 0xC2C7, 0x8652, 0xCC8C,
+	0x8653, 0xCC8D, 0x8654, 0xF2AF, 0x8655, 0xCC8E, 0x8656, 0xCC8F,	0x8657, 0xCC90, 0x8658, 0xCC91, 0x8659, 0xCC92, 0x865A, 0xD0E9,
+	0x865B, 0xCC93, 0x865C, 0xCC94, 0x865D, 0xCC95, 0x865E, 0xD3DD,	0x865F, 0xCC96, 0x8660, 0xCC97, 0x8661, 0xCC98, 0x8662, 0xEBBD,
+	0x8663, 0xCC99, 0x8664, 0xCC9A, 0x8665, 0xCC9B, 0x8666, 0xCC9C,	0x8667, 0xCC9D, 0x8668, 0xCC9E, 0x8669, 0xCC9F, 0x866A, 0xCCA0,
+	0x866B, 0xB3E6, 0x866C, 0xF2B0, 0x866D, 0xCD40, 0x866E, 0xF2B1,	0x866F, 0xCD41, 0x8670, 0xCD42, 0x8671, 0xCAAD, 0x8672, 0xCD43,
+	0x8673, 0xCD44, 0x8674, 0xCD45, 0x8675, 0xCD46, 0x8676, 0xCD47,	0x8677, 0xCD48, 0x8678, 0xCD49, 0x8679, 0xBAE7, 0x867A, 0xF2B3,
+	0x867B, 0xF2B5, 0x867C, 0xF2B4, 0x867D, 0xCBE4, 0x867E, 0xCFBA,	0x867F, 0xF2B2, 0x8680, 0xCAB4, 0x8681, 0xD2CF, 0x8682, 0xC2EC,
+	0x8683, 0xCD4A, 0x8684, 0xCD4B, 0x8685, 0xCD4C, 0x8686, 0xCD4D,	0x8687, 0xCD4E, 0x8688, 0xCD4F, 0x8689, 0xCD50, 0x868A, 0xCEC3,
+	0x868B, 0xF2B8, 0x868C, 0xB0F6, 0x868D, 0xF2B7, 0x868E, 0xCD51,	0x868F, 0xCD52, 0x8690, 0xCD53, 0x8691, 0xCD54, 0x8692, 0xCD55,
+	0x8693, 0xF2BE, 0x8694, 0xCD56, 0x8695, 0xB2CF, 0x8696, 0xCD57,	0x8697, 0xCD58, 0x8698, 0xCD59, 0x8699, 0xCD5A, 0x869A, 0xCD5B,
+	0x869B, 0xCD5C, 0x869C, 0xD1C1, 0x869D, 0xF2BA, 0x869E, 0xCD5D,	0x869F, 0xCD5E, 0x86A0, 0xCD5F, 0x86A1, 0xCD60, 0x86A2, 0xCD61,
+	0x86A3, 0xF2BC, 0x86A4, 0xD4E9, 0x86A5, 0xCD62, 0x86A6, 0xCD63,	0x86A7, 0xF2BB, 0x86A8, 0xF2B6, 0x86A9, 0xF2BF, 0x86AA, 0xF2BD,
+	0x86AB, 0xCD64, 0x86AC, 0xF2B9, 0x86AD, 0xCD65, 0x86AE, 0xCD66,	0x86AF, 0xF2C7, 0x86B0, 0xF2C4, 0x86B1, 0xF2C6, 0x86B2, 0xCD67,
+	0x86B3, 0xCD68, 0x86B4, 0xF2CA, 0x86B5, 0xF2C2, 0x86B6, 0xF2C0,	0x86B7, 0xCD69, 0x86B8, 0xCD6A, 0x86B9, 0xCD6B, 0x86BA, 0xF2C5,
+	0x86BB, 0xCD6C, 0x86BC, 0xCD6D, 0x86BD, 0xCD6E, 0x86BE, 0xCD6F,	0x86BF, 0xCD70, 0x86C0, 0xD6FB, 0x86C1, 0xCD71, 0x86C2, 0xCD72,
+	0x86C3, 0xCD73, 0x86C4, 0xF2C1, 0x86C5, 0xCD74, 0x86C6, 0xC7F9,	0x86C7, 0xC9DF, 0x86C8, 0xCD75, 0x86C9, 0xF2C8, 0x86CA, 0xB9C6,
+	0x86CB, 0xB5B0, 0x86CC, 0xCD76, 0x86CD, 0xCD77, 0x86CE, 0xF2C3,	0x86CF, 0xF2C9, 0x86D0, 0xF2D0, 0x86D1, 0xF2D6, 0x86D2, 0xCD78,
+	0x86D3, 0xCD79, 0x86D4, 0xBBD7, 0x86D5, 0xCD7A, 0x86D6, 0xCD7B,	0x86D7, 0xCD7C, 0x86D8, 0xF2D5, 0x86D9, 0xCDDC, 0x86DA, 0xCD7D,
+	0x86DB, 0xD6EB, 0x86DC, 0xCD7E, 0x86DD, 0xCD80, 0x86DE, 0xF2D2,	0x86DF, 0xF2D4, 0x86E0, 0xCD81, 0x86E1, 0xCD82, 0x86E2, 0xCD83,
+	0x86E3, 0xCD84, 0x86E4, 0xB8F2, 0x86E5, 0xCD85, 0x86E6, 0xCD86,	0x86E7, 0xCD87, 0x86E8, 0xCD88, 0x86E9, 0xF2CB, 0x86EA, 0xCD89,
+	0x86EB, 0xCD8A, 0x86EC, 0xCD8B, 0x86ED, 0xF2CE, 0x86EE, 0xC2F9,	0x86EF, 0xCD8C, 0x86F0, 0xD5DD, 0x86F1, 0xF2CC, 0x86F2, 0xF2CD,
+	0x86F3, 0xF2CF, 0x86F4, 0xF2D3, 0x86F5, 0xCD8D, 0x86F6, 0xCD8E,	0x86F7, 0xCD8F, 0x86F8, 0xF2D9, 0x86F9, 0xD3BC, 0x86FA, 0xCD90,
+	0x86FB, 0xCD91, 0x86FC, 0xCD92, 0x86FD, 0xCD93, 0x86FE, 0xB6EA,	0x86FF, 0xCD94, 0x8700, 0xCAF1, 0x8701, 0xCD95, 0x8702, 0xB7E4,
+	0x8703, 0xF2D7, 0x8704, 0xCD96, 0x8705, 0xCD97, 0x8706, 0xCD98,	0x8707, 0xF2D8, 0x8708, 0xF2DA, 0x8709, 0xF2DD, 0x870A, 0xF2DB,
+	0x870B, 0xCD99, 0x870C, 0xCD9A, 0x870D, 0xF2DC, 0x870E, 0xCD9B,	0x870F, 0xCD9C, 0x8710, 0xCD9D, 0x8711, 0xCD9E, 0x8712, 0xD1D1,
+	0x8713, 0xF2D1, 0x8714, 0xCD9F, 0x8715, 0xCDC9, 0x8716, 0xCDA0,	0x8717, 0xCECF, 0x8718, 0xD6A9, 0x8719, 0xCE40, 0x871A, 0xF2E3,
+	0x871B, 0xCE41, 0x871C, 0xC3DB, 0x871D, 0xCE42, 0x871E, 0xF2E0,	0x871F, 0xCE43, 0x8720, 0xCE44, 0x8721, 0xC0AF, 0x8722, 0xF2EC,
+	0x8723, 0xF2DE, 0x8724, 0xCE45, 0x8725, 0xF2E1, 0x8726, 0xCE46,	0x8727, 0xCE47, 0x8728, 0xCE48, 0x8729, 0xF2E8, 0x872A, 0xCE49,
+	0x872B, 0xCE4A, 0x872C, 0xCE4B, 0x872D, 0xCE4C, 0x872E, 0xF2E2,	0x872F, 0xCE4D, 0x8730, 0xCE4E, 0x8731, 0xF2E7, 0x8732, 0xCE4F,
+	0x8733, 0xCE50, 0x8734, 0xF2E6, 0x8735, 0xCE51, 0x8736, 0xCE52,	0x8737, 0xF2E9, 0x8738, 0xCE53, 0x8739, 0xCE54, 0x873A, 0xCE55,
+	0x873B, 0xF2DF, 0x873C, 0xCE56, 0x873D, 0xCE57, 0x873E, 0xF2E4,	0x873F, 0xF2EA, 0x8740, 0xCE58, 0x8741, 0xCE59, 0x8742, 0xCE5A,
+	0x8743, 0xCE5B, 0x8744, 0xCE5C, 0x8745, 0xCE5D, 0x8746, 0xCE5E,	0x8747, 0xD3AC, 0x8748, 0xF2E5, 0x8749, 0xB2F5, 0x874A, 0xCE5F,
+	0x874B, 0xCE60, 0x874C, 0xF2F2, 0x874D, 0xCE61, 0x874E, 0xD0AB,	0x874F, 0xCE62, 0x8750, 0xCE63, 0x8751, 0xCE64, 0x8752, 0xCE65,
+	0x8753, 0xF2F5, 0x8754, 0xCE66, 0x8755, 0xCE67, 0x8756, 0xCE68,	0x8757, 0xBBC8, 0x8758, 0xCE69, 0x8759, 0xF2F9, 0x875A, 0xCE6A,
+	0x875B, 0xCE6B, 0x875C, 0xCE6C, 0x875D, 0xCE6D, 0x875E, 0xCE6E,	0x875F, 0xCE6F, 0x8760, 0xF2F0, 0x8761, 0xCE70, 0x8762, 0xCE71,
+	0x8763, 0xF2F6, 0x8764, 0xF2F8, 0x8765, 0xF2FA, 0x8766, 0xCE72,	0x8767, 0xCE73, 0x8768, 0xCE74, 0x8769, 0xCE75, 0x876A, 0xCE76,
+	0x876B, 0xCE77, 0x876C, 0xCE78, 0x876D, 0xCE79, 0x876E, 0xF2F3,	0x876F, 0xCE7A, 0x8770, 0xF2F1, 0x8771, 0xCE7B, 0x8772, 0xCE7C,
+	0x8773, 0xCE7D, 0x8774, 0xBAFB, 0x8775, 0xCE7E, 0x8776, 0xB5FB,	0x8777, 0xCE80, 0x8778, 0xCE81, 0x8779, 0xCE82, 0x877A, 0xCE83,
+	0x877B, 0xF2EF, 0x877C, 0xF2F7, 0x877D, 0xF2ED, 0x877E, 0xF2EE,	0x877F, 0xCE84, 0x8780, 0xCE85, 0x8781, 0xCE86, 0x8782, 0xF2EB,
+	0x8783, 0xF3A6, 0x8784, 0xCE87, 0x8785, 0xF3A3, 0x8786, 0xCE88,	0x8787, 0xCE89, 0x8788, 0xF3A2, 0x8789, 0xCE8A, 0x878A, 0xCE8B,
+	0x878B, 0xF2F4, 0x878C, 0xCE8C, 0x878D, 0xC8DA, 0x878E, 0xCE8D,	0x878F, 0xCE8E, 0x8790, 0xCE8F, 0x8791, 0xCE90, 0x8792, 0xCE91,
+	0x8793, 0xF2FB, 0x8794, 0xCE92, 0x8795, 0xCE93, 0x8796, 0xCE94,	0x8797, 0xF3A5, 0x8798, 0xCE95, 0x8799, 0xCE96, 0x879A, 0xCE97,
+	0x879B, 0xCE98, 0x879C, 0xCE99, 0x879D, 0xCE9A, 0x879E, 0xCE9B,	0x879F, 0xC3F8, 0x87A0, 0xCE9C, 0x87A1, 0xCE9D, 0x87A2, 0xCE9E,
+	0x87A3, 0xCE9F, 0x87A4, 0xCEA0, 0x87A5, 0xCF40, 0x87A6, 0xCF41,	0x87A7, 0xCF42, 0x87A8, 0xF2FD, 0x87A9, 0xCF43, 0x87AA, 0xCF44,
+	0x87AB, 0xF3A7, 0x87AC, 0xF3A9, 0x87AD, 0xF3A4, 0x87AE, 0xCF45,	0x87AF, 0xF2FC, 0x87B0, 0xCF46, 0x87B1, 0xCF47, 0x87B2, 0xCF48,
+	0x87B3, 0xF3AB, 0x87B4, 0xCF49, 0x87B5, 0xF3AA, 0x87B6, 0xCF4A,	0x87B7, 0xCF4B, 0x87B8, 0xCF4C, 0x87B9, 0xCF4D, 0x87BA, 0xC2DD,
+	0x87BB, 0xCF4E, 0x87BC, 0xCF4F, 0x87BD, 0xF3AE, 0x87BE, 0xCF50,	0x87BF, 0xCF51, 0x87C0, 0xF3B0, 0x87C1, 0xCF52, 0x87C2, 0xCF53,
+	0x87C3, 0xCF54, 0x87C4, 0xCF55, 0x87C5, 0xCF56, 0x87C6, 0xF3A1,	0x87C7, 0xCF57, 0x87C8, 0xCF58, 0x87C9, 0xCF59, 0x87CA, 0xF3B1,
+	0x87CB, 0xF3AC, 0x87CC, 0xCF5A, 0x87CD, 0xCF5B, 0x87CE, 0xCF5C,	0x87CF, 0xCF5D, 0x87D0, 0xCF5E, 0x87D1, 0xF3AF, 0x87D2, 0xF2FE,
+	0x87D3, 0xF3AD, 0x87D4, 0xCF5F, 0x87D5, 0xCF60, 0x87D6, 0xCF61,	0x87D7, 0xCF62, 0x87D8, 0xCF63, 0x87D9, 0xCF64, 0x87DA, 0xCF65,
+	0x87DB, 0xF3B2, 0x87DC, 0xCF66, 0x87DD, 0xCF67, 0x87DE, 0xCF68,	0x87DF, 0xCF69, 0x87E0, 0xF3B4, 0x87E1, 0xCF6A, 0x87E2, 0xCF6B,
+	0x87E3, 0xCF6C, 0x87E4, 0xCF6D, 0x87E5, 0xF3A8, 0x87E6, 0xCF6E,	0x87E7, 0xCF6F, 0x87E8, 0xCF70, 0x87E9, 0xCF71, 0x87EA, 0xF3B3,
+	0x87EB, 0xCF72, 0x87EC, 0xCF73, 0x87ED, 0xCF74, 0x87EE, 0xF3B5,	0x87EF, 0xCF75, 0x87F0, 0xCF76, 0x87F1, 0xCF77, 0x87F2, 0xCF78,
+	0x87F3, 0xCF79, 0x87F4, 0xCF7A, 0x87F5, 0xCF7B, 0x87F6, 0xCF7C,	0x87F7, 0xCF7D, 0x87F8, 0xCF7E, 0x87F9, 0xD0B7, 0x87FA, 0xCF80,
+	0x87FB, 0xCF81, 0x87FC, 0xCF82, 0x87FD, 0xCF83, 0x87FE, 0xF3B8,	0x87FF, 0xCF84, 0x8800, 0xCF85, 0x8801, 0xCF86, 0x8802, 0xCF87,
+	0x8803, 0xD9F9, 0x8804, 0xCF88, 0x8805, 0xCF89, 0x8806, 0xCF8A,	0x8807, 0xCF8B, 0x8808, 0xCF8C, 0x8809, 0xCF8D, 0x880A, 0xF3B9,
+	0x880B, 0xCF8E, 0x880C, 0xCF8F, 0x880D, 0xCF90, 0x880E, 0xCF91,	0x880F, 0xCF92, 0x8810, 0xCF93, 0x8811, 0xCF94, 0x8812, 0xCF95,
+	0x8813, 0xF3B7, 0x8814, 0xCF96, 0x8815, 0xC8E4, 0x8816, 0xF3B6,	0x8817, 0xCF97, 0x8818, 0xCF98, 0x8819, 0xCF99, 0x881A, 0xCF9A,
+	0x881B, 0xF3BA, 0x881C, 0xCF9B, 0x881D, 0xCF9C, 0x881E, 0xCF9D,	0x881F, 0xCF9E, 0x8820, 0xCF9F, 0x8821, 0xF3BB, 0x8822, 0xB4C0,
+	0x8823, 0xCFA0, 0x8824, 0xD040, 0x8825, 0xD041, 0x8826, 0xD042,	0x8827, 0xD043, 0x8828, 0xD044, 0x8829, 0xD045, 0x882A, 0xD046,
+	0x882B, 0xD047, 0x882C, 0xD048, 0x882D, 0xD049, 0x882E, 0xD04A,	0x882F, 0xD04B, 0x8830, 0xD04C, 0x8831, 0xD04D, 0x8832, 0xEEC3,
+	0x8833, 0xD04E, 0x8834, 0xD04F, 0x8835, 0xD050, 0x8836, 0xD051,	0x8837, 0xD052, 0x8838, 0xD053, 0x8839, 0xF3BC, 0x883A, 0xD054,
+	0x883B, 0xD055, 0x883C, 0xF3BD, 0x883D, 0xD056, 0x883E, 0xD057,	0x883F, 0xD058, 0x8840, 0xD1AA, 0x8841, 0xD059, 0x8842, 0xD05A,
+	0x8843, 0xD05B, 0x8844, 0xF4AC, 0x8845, 0xD0C6, 0x8846, 0xD05C,	0x8847, 0xD05D, 0x8848, 0xD05E, 0x8849, 0xD05F, 0x884A, 0xD060,
+	0x884B, 0xD061, 0x884C, 0xD0D0, 0x884D, 0xD1DC, 0x884E, 0xD062,	0x884F, 0xD063, 0x8850, 0xD064, 0x8851, 0xD065, 0x8852, 0xD066,
+	0x8853, 0xD067, 0x8854, 0xCFCE, 0x8855, 0xD068, 0x8856, 0xD069,	0x8857, 0xBDD6, 0x8858, 0xD06A, 0x8859, 0xD1C3, 0x885A, 0xD06B,
+	0x885B, 0xD06C, 0x885C, 0xD06D, 0x885D, 0xD06E, 0x885E, 0xD06F,	0x885F, 0xD070, 0x8860, 0xD071, 0x8861, 0xBAE2, 0x8862, 0xE1E9,
+	0x8863, 0xD2C2, 0x8864, 0xF1C2, 0x8865, 0xB2B9, 0x8866, 0xD072,	0x8867, 0xD073, 0x8868, 0xB1ED, 0x8869, 0xF1C3, 0x886A, 0xD074,
+	0x886B, 0xC9C0, 0x886C, 0xB3C4, 0x886D, 0xD075, 0x886E, 0xD9F2,	0x886F, 0xD076, 0x8870, 0xCBA5, 0x8871, 0xD077, 0x8872, 0xF1C4,
+	0x8873, 0xD078, 0x8874, 0xD079, 0x8875, 0xD07A, 0x8876, 0xD07B,	0x8877, 0xD6D4, 0x8878, 0xD07C, 0x8879, 0xD07D, 0x887A, 0xD07E,
+	0x887B, 0xD080, 0x887C, 0xD081, 0x887D, 0xF1C5, 0x887E, 0xF4C0,	0x887F, 0xF1C6, 0x8880, 0xD082, 0x8881, 0xD4AC, 0x8882, 0xF1C7,
+	0x8883, 0xD083, 0x8884, 0xB0C0, 0x8885, 0xF4C1, 0x8886, 0xD084,	0x8887, 0xD085, 0x8888, 0xF4C2, 0x8889, 0xD086, 0x888A, 0xD087,
+	0x888B, 0xB4FC, 0x888C, 0xD088, 0x888D, 0xC5DB, 0x888E, 0xD089,	0x888F, 0xD08A, 0x8890, 0xD08B, 0x8891, 0xD08C, 0x8892, 0xCCBB,
+	0x8893, 0xD08D, 0x8894, 0xD08E, 0x8895, 0xD08F, 0x8896, 0xD0E4,	0x8897, 0xD090, 0x8898, 0xD091, 0x8899, 0xD092, 0x889A, 0xD093,
+	0x889B, 0xD094, 0x889C, 0xCDE0, 0x889D, 0xD095, 0x889E, 0xD096,	0x889F, 0xD097, 0x88A0, 0xD098, 0x88A1, 0xD099, 0x88A2, 0xF1C8,
+	0x88A3, 0xD09A, 0x88A4, 0xD9F3, 0x88A5, 0xD09B, 0x88A6, 0xD09C,	0x88A7, 0xD09D, 0x88A8, 0xD09E, 0x88A9, 0xD09F, 0x88AA, 0xD0A0,
+	0x88AB, 0xB1BB, 0x88AC, 0xD140, 0x88AD, 0xCFAE, 0x88AE, 0xD141,	0x88AF, 0xD142, 0x88B0, 0xD143, 0x88B1, 0xB8A4, 0x88B2, 0xD144,
+	0x88B3, 0xD145, 0x88B4, 0xD146, 0x88B5, 0xD147, 0x88B6, 0xD148,	0x88B7, 0xF1CA, 0x88B8, 0xD149, 0x88B9, 0xD14A, 0x88BA, 0xD14B,
+	0x88BB, 0xD14C, 0x88BC, 0xF1CB, 0x88BD, 0xD14D, 0x88BE, 0xD14E,	0x88BF, 0xD14F, 0x88C0, 0xD150, 0x88C1, 0xB2C3, 0x88C2, 0xC1D1,
+	0x88C3, 0xD151, 0x88C4, 0xD152, 0x88C5, 0xD7B0, 0x88C6, 0xF1C9,	0x88C7, 0xD153, 0x88C8, 0xD154, 0x88C9, 0xF1CC, 0x88CA, 0xD155,
+	0x88CB, 0xD156, 0x88CC, 0xD157, 0x88CD, 0xD158, 0x88CE, 0xF1CE,	0x88CF, 0xD159, 0x88D0, 0xD15A, 0x88D1, 0xD15B, 0x88D2, 0xD9F6,
+	0x88D3, 0xD15C, 0x88D4, 0xD2E1, 0x88D5, 0xD4A3, 0x88D6, 0xD15D,	0x88D7, 0xD15E, 0x88D8, 0xF4C3, 0x88D9, 0xC8B9, 0x88DA, 0xD15F,
+	0x88DB, 0xD160, 0x88DC, 0xD161, 0x88DD, 0xD162, 0x88DE, 0xD163,	0x88DF, 0xF4C4, 0x88E0, 0xD164, 0x88E1, 0xD165, 0x88E2, 0xF1CD,
+	0x88E3, 0xF1CF, 0x88E4, 0xBFE3, 0x88E5, 0xF1D0, 0x88E6, 0xD166,	0x88E7, 0xD167, 0x88E8, 0xF1D4, 0x88E9, 0xD168, 0x88EA, 0xD169,
+	0x88EB, 0xD16A, 0x88EC, 0xD16B, 0x88ED, 0xD16C, 0x88EE, 0xD16D,	0x88EF, 0xD16E, 0x88F0, 0xF1D6, 0x88F1, 0xF1D1, 0x88F2, 0xD16F,
+	0x88F3, 0xC9D1, 0x88F4, 0xC5E1, 0x88F5, 0xD170, 0x88F6, 0xD171,	0x88F7, 0xD172, 0x88F8, 0xC2E3, 0x88F9, 0xB9FC, 0x88FA, 0xD173,
+	0x88FB, 0xD174, 0x88FC, 0xF1D3, 0x88FD, 0xD175, 0x88FE, 0xF1D5,	0x88FF, 0xD176, 0x8900, 0xD177, 0x8901, 0xD178, 0x8902, 0xB9D3,
+	0x8903, 0xD179, 0x8904, 0xD17A, 0x8905, 0xD17B, 0x8906, 0xD17C,	0x8907, 0xD17D, 0x8908, 0xD17E, 0x8909, 0xD180, 0x890A, 0xF1DB,
+	0x890B, 0xD181, 0x890C, 0xD182, 0x890D, 0xD183, 0x890E, 0xD184,	0x890F, 0xD185, 0x8910, 0xBAD6, 0x8911, 0xD186, 0x8912, 0xB0FD,
+	0x8913, 0xF1D9, 0x8914, 0xD187, 0x8915, 0xD188, 0x8916, 0xD189,	0x8917, 0xD18A, 0x8918, 0xD18B, 0x8919, 0xF1D8, 0x891A, 0xF1D2,
+	0x891B, 0xF1DA, 0x891C, 0xD18C, 0x891D, 0xD18D, 0x891E, 0xD18E,	0x891F, 0xD18F, 0x8920, 0xD190, 0x8921, 0xF1D7, 0x8922, 0xD191,
+	0x8923, 0xD192, 0x8924, 0xD193, 0x8925, 0xC8EC, 0x8926, 0xD194,	0x8927, 0xD195, 0x8928, 0xD196, 0x8929, 0xD197, 0x892A, 0xCDCA,
+	0x892B, 0xF1DD, 0x892C, 0xD198, 0x892D, 0xD199, 0x892E, 0xD19A,	0x892F, 0xD19B, 0x8930, 0xE5BD, 0x8931, 0xD19C, 0x8932, 0xD19D,
+	0x8933, 0xD19E, 0x8934, 0xF1DC, 0x8935, 0xD19F, 0x8936, 0xF1DE,	0x8937, 0xD1A0, 0x8938, 0xD240, 0x8939, 0xD241, 0x893A, 0xD242,
+	0x893B, 0xD243, 0x893C, 0xD244, 0x893D, 0xD245, 0x893E, 0xD246,	0x893F, 0xD247, 0x8940, 0xD248, 0x8941, 0xF1DF, 0x8942, 0xD249,
+	0x8943, 0xD24A, 0x8944, 0xCFE5, 0x8945, 0xD24B, 0x8946, 0xD24C,	0x8947, 0xD24D, 0x8948, 0xD24E, 0x8949, 0xD24F, 0x894A, 0xD250,
+	0x894B, 0xD251, 0x894C, 0xD252, 0x894D, 0xD253, 0x894E, 0xD254,	0x894F, 0xD255, 0x8950, 0xD256, 0x8951, 0xD257, 0x8952, 0xD258,
+	0x8953, 0xD259, 0x8954, 0xD25A, 0x8955, 0xD25B, 0x8956, 0xD25C,	0x8957, 0xD25D, 0x8958, 0xD25E, 0x8959, 0xD25F, 0x895A, 0xD260,
+	0x895B, 0xD261, 0x895C, 0xD262, 0x895D, 0xD263, 0x895E, 0xF4C5,	0x895F, 0xBDF3, 0x8960, 0xD264, 0x8961, 0xD265, 0x8962, 0xD266,
+	0x8963, 0xD267, 0x8964, 0xD268, 0x8965, 0xD269, 0x8966, 0xF1E0,	0x8967, 0xD26A, 0x8968, 0xD26B, 0x8969, 0xD26C, 0x896A, 0xD26D,
+	0x896B, 0xD26E, 0x896C, 0xD26F, 0x896D, 0xD270, 0x896E, 0xD271,	0x896F, 0xD272, 0x8970, 0xD273, 0x8971, 0xD274, 0x8972, 0xD275,
+	0x8973, 0xD276, 0x8974, 0xD277, 0x8975, 0xD278, 0x8976, 0xD279,	0x8977, 0xD27A, 0x8978, 0xD27B, 0x8979, 0xD27C, 0x897A, 0xD27D,
+	0x897B, 0xF1E1, 0x897C, 0xD27E, 0x897D, 0xD280, 0x897E, 0xD281,	0x897F, 0xCEF7, 0x8980, 0xD282, 0x8981, 0xD2AA, 0x8982, 0xD283,
+	0x8983, 0xF1FB, 0x8984, 0xD284, 0x8985, 0xD285, 0x8986, 0xB8B2,	0x8987, 0xD286, 0x8988, 0xD287, 0x8989, 0xD288, 0x898A, 0xD289,
+	0x898B, 0xD28A, 0x898C, 0xD28B, 0x898D, 0xD28C, 0x898E, 0xD28D,	0x898F, 0xD28E, 0x8990, 0xD28F, 0x8991, 0xD290, 0x8992, 0xD291,
+	0x8993, 0xD292, 0x8994, 0xD293, 0x8995, 0xD294, 0x8996, 0xD295,	0x8997, 0xD296, 0x8998, 0xD297, 0x8999, 0xD298, 0x899A, 0xD299,
+	0x899B, 0xD29A, 0x899C, 0xD29B, 0x899D, 0xD29C, 0x899E, 0xD29D,	0x899F, 0xD29E, 0x89A0, 0xD29F, 0x89A1, 0xD2A0, 0x89A2, 0xD340,
+	0x89A3, 0xD341, 0x89A4, 0xD342, 0x89A5, 0xD343, 0x89A6, 0xD344,	0x89A7, 0xD345, 0x89A8, 0xD346, 0x89A9, 0xD347, 0x89AA, 0xD348,
+	0x89AB, 0xD349, 0x89AC, 0xD34A, 0x89AD, 0xD34B, 0x89AE, 0xD34C,	0x89AF, 0xD34D, 0x89B0, 0xD34E, 0x89B1, 0xD34F, 0x89B2, 0xD350,
+	0x89B3, 0xD351, 0x89B4, 0xD352, 0x89B5, 0xD353, 0x89B6, 0xD354,	0x89B7, 0xD355, 0x89B8, 0xD356, 0x89B9, 0xD357, 0x89BA, 0xD358,
+	0x89BB, 0xD359, 0x89BC, 0xD35A, 0x89BD, 0xD35B, 0x89BE, 0xD35C,	0x89BF, 0xD35D, 0x89C0, 0xD35E, 0x89C1, 0xBCFB, 0x89C2, 0xB9DB,
+	0x89C3, 0xD35F, 0x89C4, 0xB9E6, 0x89C5, 0xC3D9, 0x89C6, 0xCAD3,	0x89C7, 0xEAE8, 0x89C8, 0xC0C0, 0x89C9, 0xBEF5, 0x89CA, 0xEAE9,
+	0x89CB, 0xEAEA, 0x89CC, 0xEAEB, 0x89CD, 0xD360, 0x89CE, 0xEAEC,	0x89CF, 0xEAED, 0x89D0, 0xEAEE, 0x89D1, 0xEAEF, 0x89D2, 0xBDC7,
+	0x89D3, 0xD361, 0x89D4, 0xD362, 0x89D5, 0xD363, 0x89D6, 0xF5FB,	0x89D7, 0xD364, 0x89D8, 0xD365, 0x89D9, 0xD366, 0x89DA, 0xF5FD,
+	0x89DB, 0xD367, 0x89DC, 0xF5FE, 0x89DD, 0xD368, 0x89DE, 0xF5FC,	0x89DF, 0xD369, 0x89E0, 0xD36A, 0x89E1, 0xD36B, 0x89E2, 0xD36C,
+	0x89E3, 0xBDE2, 0x89E4, 0xD36D, 0x89E5, 0xF6A1, 0x89E6, 0xB4A5,	0x89E7, 0xD36E, 0x89E8, 0xD36F, 0x89E9, 0xD370, 0x89EA, 0xD371,
+	0x89EB, 0xF6A2, 0x89EC, 0xD372, 0x89ED, 0xD373, 0x89EE, 0xD374,	0x89EF, 0xF6A3, 0x89F0, 0xD375, 0x89F1, 0xD376, 0x89F2, 0xD377,
+	0x89F3, 0xECB2, 0x89F4, 0xD378, 0x89F5, 0xD379, 0x89F6, 0xD37A,	0x89F7, 0xD37B, 0x89F8, 0xD37C, 0x89F9, 0xD37D, 0x89FA, 0xD37E,
+	0x89FB, 0xD380, 0x89FC, 0xD381, 0x89FD, 0xD382, 0x89FE, 0xD383,	0x89FF, 0xD384, 0x8A00, 0xD1D4, 0x8A01, 0xD385, 0x8A02, 0xD386,
+	0x8A03, 0xD387, 0x8A04, 0xD388, 0x8A05, 0xD389, 0x8A06, 0xD38A,	0x8A07, 0xD9EA, 0x8A08, 0xD38B, 0x8A09, 0xD38C, 0x8A0A, 0xD38D,
+	0x8A0B, 0xD38E, 0x8A0C, 0xD38F, 0x8A0D, 0xD390, 0x8A0E, 0xD391,	0x8A0F, 0xD392, 0x8A10, 0xD393, 0x8A11, 0xD394, 0x8A12, 0xD395,
+	0x8A13, 0xD396, 0x8A14, 0xD397, 0x8A15, 0xD398, 0x8A16, 0xD399,	0x8A17, 0xD39A, 0x8A18, 0xD39B, 0x8A19, 0xD39C, 0x8A1A, 0xD39D,
+	0x8A1B, 0xD39E, 0x8A1C, 0xD39F, 0x8A1D, 0xD3A0, 0x8A1E, 0xD440,	0x8A1F, 0xD441, 0x8A20, 0xD442, 0x8A21, 0xD443, 0x8A22, 0xD444,
+	0x8A23, 0xD445, 0x8A24, 0xD446, 0x8A25, 0xD447, 0x8A26, 0xD448,	0x8A27, 0xD449, 0x8A28, 0xD44A, 0x8A29, 0xD44B, 0x8A2A, 0xD44C,
+	0x8A2B, 0xD44D, 0x8A2C, 0xD44E, 0x8A2D, 0xD44F, 0x8A2E, 0xD450,	0x8A2F, 0xD451, 0x8A30, 0xD452, 0x8A31, 0xD453, 0x8A32, 0xD454,
+	0x8A33, 0xD455, 0x8A34, 0xD456, 0x8A35, 0xD457, 0x8A36, 0xD458,	0x8A37, 0xD459, 0x8A38, 0xD45A, 0x8A39, 0xD45B, 0x8A3A, 0xD45C,
+	0x8A3B, 0xD45D, 0x8A3C, 0xD45E, 0x8A3D, 0xD45F, 0x8A3E, 0xF6A4,	0x8A3F, 0xD460, 0x8A40, 0xD461, 0x8A41, 0xD462, 0x8A42, 0xD463,
+	0x8A43, 0xD464, 0x8A44, 0xD465, 0x8A45, 0xD466, 0x8A46, 0xD467,	0x8A47, 0xD468, 0x8A48, 0xEEBA, 0x8A49, 0xD469, 0x8A4A, 0xD46A,
+	0x8A4B, 0xD46B, 0x8A4C, 0xD46C, 0x8A4D, 0xD46D, 0x8A4E, 0xD46E,	0x8A4F, 0xD46F, 0x8A50, 0xD470, 0x8A51, 0xD471, 0x8A52, 0xD472,
+	0x8A53, 0xD473, 0x8A54, 0xD474, 0x8A55, 0xD475, 0x8A56, 0xD476,	0x8A57, 0xD477, 0x8A58, 0xD478, 0x8A59, 0xD479, 0x8A5A, 0xD47A,
+	0x8A5B, 0xD47B, 0x8A5C, 0xD47C, 0x8A5D, 0xD47D, 0x8A5E, 0xD47E,	0x8A5F, 0xD480, 0x8A60, 0xD481, 0x8A61, 0xD482, 0x8A62, 0xD483,
+	0x8A63, 0xD484, 0x8A64, 0xD485, 0x8A65, 0xD486, 0x8A66, 0xD487,	0x8A67, 0xD488, 0x8A68, 0xD489, 0x8A69, 0xD48A, 0x8A6A, 0xD48B,
+	0x8A6B, 0xD48C, 0x8A6C, 0xD48D, 0x8A6D, 0xD48E, 0x8A6E, 0xD48F,	0x8A6F, 0xD490, 0x8A70, 0xD491, 0x8A71, 0xD492, 0x8A72, 0xD493,
+	0x8A73, 0xD494, 0x8A74, 0xD495, 0x8A75, 0xD496, 0x8A76, 0xD497,	0x8A77, 0xD498, 0x8A78, 0xD499, 0x8A79, 0xD5B2, 0x8A7A, 0xD49A,
+	0x8A7B, 0xD49B, 0x8A7C, 0xD49C, 0x8A7D, 0xD49D, 0x8A7E, 0xD49E,	0x8A7F, 0xD49F, 0x8A80, 0xD4A0, 0x8A81, 0xD540, 0x8A82, 0xD541,
+	0x8A83, 0xD542, 0x8A84, 0xD543, 0x8A85, 0xD544, 0x8A86, 0xD545,	0x8A87, 0xD546, 0x8A88, 0xD547, 0x8A89, 0xD3FE, 0x8A8A, 0xCCDC,
+	0x8A8B, 0xD548, 0x8A8C, 0xD549, 0x8A8D, 0xD54A, 0x8A8E, 0xD54B,	0x8A8F, 0xD54C, 0x8A90, 0xD54D, 0x8A91, 0xD54E, 0x8A92, 0xD54F,
+	0x8A93, 0xCAC4, 0x8A94, 0xD550, 0x8A95, 0xD551, 0x8A96, 0xD552,	0x8A97, 0xD553, 0x8A98, 0xD554, 0x8A99, 0xD555, 0x8A9A, 0xD556,
+	0x8A9B, 0xD557, 0x8A9C, 0xD558, 0x8A9D, 0xD559, 0x8A9E, 0xD55A,	0x8A9F, 0xD55B, 0x8AA0, 0xD55C, 0x8AA1, 0xD55D, 0x8AA2, 0xD55E,
+	0x8AA3, 0xD55F, 0x8AA4, 0xD560, 0x8AA5, 0xD561, 0x8AA6, 0xD562,	0x8AA7, 0xD563, 0x8AA8, 0xD564, 0x8AA9, 0xD565, 0x8AAA, 0xD566,
+	0x8AAB, 0xD567, 0x8AAC, 0xD568, 0x8AAD, 0xD569, 0x8AAE, 0xD56A,	0x8AAF, 0xD56B, 0x8AB0, 0xD56C, 0x8AB1, 0xD56D, 0x8AB2, 0xD56E,
+	0x8AB3, 0xD56F, 0x8AB4, 0xD570, 0x8AB5, 0xD571, 0x8AB6, 0xD572,	0x8AB7, 0xD573, 0x8AB8, 0xD574, 0x8AB9, 0xD575, 0x8ABA, 0xD576,
+	0x8ABB, 0xD577, 0x8ABC, 0xD578, 0x8ABD, 0xD579, 0x8ABE, 0xD57A,	0x8ABF, 0xD57B, 0x8AC0, 0xD57C, 0x8AC1, 0xD57D, 0x8AC2, 0xD57E,
+	0x8AC3, 0xD580, 0x8AC4, 0xD581, 0x8AC5, 0xD582, 0x8AC6, 0xD583,	0x8AC7, 0xD584, 0x8AC8, 0xD585, 0x8AC9, 0xD586, 0x8ACA, 0xD587,
+	0x8ACB, 0xD588, 0x8ACC, 0xD589, 0x8ACD, 0xD58A, 0x8ACE, 0xD58B,	0x8ACF, 0xD58C, 0x8AD0, 0xD58D, 0x8AD1, 0xD58E, 0x8AD2, 0xD58F,
+	0x8AD3, 0xD590, 0x8AD4, 0xD591, 0x8AD5, 0xD592, 0x8AD6, 0xD593,	0x8AD7, 0xD594, 0x8AD8, 0xD595, 0x8AD9, 0xD596, 0x8ADA, 0xD597,
+	0x8ADB, 0xD598, 0x8ADC, 0xD599, 0x8ADD, 0xD59A, 0x8ADE, 0xD59B,	0x8ADF, 0xD59C, 0x8AE0, 0xD59D, 0x8AE1, 0xD59E, 0x8AE2, 0xD59F,
+	0x8AE3, 0xD5A0, 0x8AE4, 0xD640, 0x8AE5, 0xD641, 0x8AE6, 0xD642,	0x8AE7, 0xD643, 0x8AE8, 0xD644, 0x8AE9, 0xD645, 0x8AEA, 0xD646,
+	0x8AEB, 0xD647, 0x8AEC, 0xD648, 0x8AED, 0xD649, 0x8AEE, 0xD64A,	0x8AEF, 0xD64B, 0x8AF0, 0xD64C, 0x8AF1, 0xD64D, 0x8AF2, 0xD64E,
+	0x8AF3, 0xD64F, 0x8AF4, 0xD650, 0x8AF5, 0xD651, 0x8AF6, 0xD652,	0x8AF7, 0xD653, 0x8AF8, 0xD654, 0x8AF9, 0xD655, 0x8AFA, 0xD656,
+	0x8AFB, 0xD657, 0x8AFC, 0xD658, 0x8AFD, 0xD659, 0x8AFE, 0xD65A,	0x8AFF, 0xD65B, 0x8B00, 0xD65C, 0x8B01, 0xD65D, 0x8B02, 0xD65E,
+	0x8B03, 0xD65F, 0x8B04, 0xD660, 0x8B05, 0xD661, 0x8B06, 0xD662,	0x8B07, 0xE5C0, 0x8B08, 0xD663, 0x8B09, 0xD664, 0x8B0A, 0xD665,
+	0x8B0B, 0xD666, 0x8B0C, 0xD667, 0x8B0D, 0xD668, 0x8B0E, 0xD669,	0x8B0F, 0xD66A, 0x8B10, 0xD66B, 0x8B11, 0xD66C, 0x8B12, 0xD66D,
+	0x8B13, 0xD66E, 0x8B14, 0xD66F, 0x8B15, 0xD670, 0x8B16, 0xD671,	0x8B17, 0xD672, 0x8B18, 0xD673, 0x8B19, 0xD674, 0x8B1A, 0xD675,
+	0x8B1B, 0xD676, 0x8B1C, 0xD677, 0x8B1D, 0xD678, 0x8B1E, 0xD679,	0x8B1F, 0xD67A, 0x8B20, 0xD67B, 0x8B21, 0xD67C, 0x8B22, 0xD67D,
+	0x8B23, 0xD67E, 0x8B24, 0xD680, 0x8B25, 0xD681, 0x8B26, 0xF6A5,	0x8B27, 0xD682, 0x8B28, 0xD683, 0x8B29, 0xD684, 0x8B2A, 0xD685,
+	0x8B2B, 0xD686, 0x8B2C, 0xD687, 0x8B2D, 0xD688, 0x8B2E, 0xD689,	0x8B2F, 0xD68A, 0x8B30, 0xD68B, 0x8B31, 0xD68C, 0x8B32, 0xD68D,
+	0x8B33, 0xD68E, 0x8B34, 0xD68F, 0x8B35, 0xD690, 0x8B36, 0xD691,	0x8B37, 0xD692, 0x8B38, 0xD693, 0x8B39, 0xD694, 0x8B3A, 0xD695,
+	0x8B3B, 0xD696, 0x8B3C, 0xD697, 0x8B3D, 0xD698, 0x8B3E, 0xD699,	0x8B3F, 0xD69A, 0x8B40, 0xD69B, 0x8B41, 0xD69C, 0x8B42, 0xD69D,
+	0x8B43, 0xD69E, 0x8B44, 0xD69F, 0x8B45, 0xD6A0, 0x8B46, 0xD740,	0x8B47, 0xD741, 0x8B48, 0xD742, 0x8B49, 0xD743, 0x8B4A, 0xD744,
+	0x8B4B, 0xD745, 0x8B4C, 0xD746, 0x8B4D, 0xD747, 0x8B4E, 0xD748,	0x8B4F, 0xD749, 0x8B50, 0xD74A, 0x8B51, 0xD74B, 0x8B52, 0xD74C,
+	0x8B53, 0xD74D, 0x8B54, 0xD74E, 0x8B55, 0xD74F, 0x8B56, 0xD750,	0x8B57, 0xD751, 0x8B58, 0xD752, 0x8B59, 0xD753, 0x8B5A, 0xD754,
+	0x8B5B, 0xD755, 0x8B5C, 0xD756, 0x8B5D, 0xD757, 0x8B5E, 0xD758,	0x8B5F, 0xD759, 0x8B60, 0xD75A, 0x8B61, 0xD75B, 0x8B62, 0xD75C,
+	0x8B63, 0xD75D, 0x8B64, 0xD75E, 0x8B65, 0xD75F, 0x8B66, 0xBEAF,	0x8B67, 0xD760, 0x8B68, 0xD761, 0x8B69, 0xD762, 0x8B6A, 0xD763,
+	0x8B6B, 0xD764, 0x8B6C, 0xC6A9, 0x8B6D, 0xD765, 0x8B6E, 0xD766,	0x8B6F, 0xD767, 0x8B70, 0xD768, 0x8B71, 0xD769, 0x8B72, 0xD76A,
+	0x8B73, 0xD76B, 0x8B74, 0xD76C, 0x8B75, 0xD76D, 0x8B76, 0xD76E,	0x8B77, 0xD76F, 0x8B78, 0xD770, 0x8B79, 0xD771, 0x8B7A, 0xD772,
+	0x8B7B, 0xD773, 0x8B7C, 0xD774, 0x8B7D, 0xD775, 0x8B7E, 0xD776,	0x8B7F, 0xD777, 0x8B80, 0xD778, 0x8B81, 0xD779, 0x8B82, 0xD77A,
+	0x8B83, 0xD77B, 0x8B84, 0xD77C, 0x8B85, 0xD77D, 0x8B86, 0xD77E,	0x8B87, 0xD780, 0x8B88, 0xD781, 0x8B89, 0xD782, 0x8B8A, 0xD783,
+	0x8B8B, 0xD784, 0x8B8C, 0xD785, 0x8B8D, 0xD786, 0x8B8E, 0xD787,	0x8B8F, 0xD788, 0x8B90, 0xD789, 0x8B91, 0xD78A, 0x8B92, 0xD78B,
+	0x8B93, 0xD78C, 0x8B94, 0xD78D, 0x8B95, 0xD78E, 0x8B96, 0xD78F,	0x8B97, 0xD790, 0x8B98, 0xD791, 0x8B99, 0xD792, 0x8B9A, 0xD793,
+	0x8B9B, 0xD794, 0x8B9C, 0xD795, 0x8B9D, 0xD796, 0x8B9E, 0xD797,	0x8B9F, 0xD798, 0x8BA0, 0xDAA5, 0x8BA1, 0xBCC6, 0x8BA2, 0xB6A9,
+	0x8BA3, 0xB8BC, 0x8BA4, 0xC8CF, 0x8BA5, 0xBCA5, 0x8BA6, 0xDAA6,	0x8BA7, 0xDAA7, 0x8BA8, 0xCCD6, 0x8BA9, 0xC8C3, 0x8BAA, 0xDAA8,
+	0x8BAB, 0xC6FD, 0x8BAC, 0xD799, 0x8BAD, 0xD1B5, 0x8BAE, 0xD2E9,	0x8BAF, 0xD1B6, 0x8BB0, 0xBCC7, 0x8BB1, 0xD79A, 0x8BB2, 0xBDB2,
+	0x8BB3, 0xBBE4, 0x8BB4, 0xDAA9, 0x8BB5, 0xDAAA, 0x8BB6, 0xD1C8,	0x8BB7, 0xDAAB, 0x8BB8, 0xD0ED, 0x8BB9, 0xB6EF, 0x8BBA, 0xC2DB,
+	0x8BBB, 0xD79B, 0x8BBC, 0xCBCF, 0x8BBD, 0xB7ED, 0x8BBE, 0xC9E8,	0x8BBF, 0xB7C3, 0x8BC0, 0xBEF7, 0x8BC1, 0xD6A4, 0x8BC2, 0xDAAC,
+	0x8BC3, 0xDAAD, 0x8BC4, 0xC6C0, 0x8BC5, 0xD7E7, 0x8BC6, 0xCAB6,	0x8BC7, 0xD79C, 0x8BC8, 0xD5A9, 0x8BC9, 0xCBDF, 0x8BCA, 0xD5EF,
+	0x8BCB, 0xDAAE, 0x8BCC, 0xD6DF, 0x8BCD, 0xB4CA, 0x8BCE, 0xDAB0,	0x8BCF, 0xDAAF, 0x8BD0, 0xD79D, 0x8BD1, 0xD2EB, 0x8BD2, 0xDAB1,
+	0x8BD3, 0xDAB2, 0x8BD4, 0xDAB3, 0x8BD5, 0xCAD4, 0x8BD6, 0xDAB4,	0x8BD7, 0xCAAB, 0x8BD8, 0xDAB5, 0x8BD9, 0xDAB6, 0x8BDA, 0xB3CF,
+	0x8BDB, 0xD6EF, 0x8BDC, 0xDAB7, 0x8BDD, 0xBBB0, 0x8BDE, 0xB5AE,	0x8BDF, 0xDAB8, 0x8BE0, 0xDAB9, 0x8BE1, 0xB9EE, 0x8BE2, 0xD1AF,
+	0x8BE3, 0xD2E8, 0x8BE4, 0xDABA, 0x8BE5, 0xB8C3, 0x8BE6, 0xCFEA,	0x8BE7, 0xB2EF, 0x8BE8, 0xDABB, 0x8BE9, 0xDABC, 0x8BEA, 0xD79E,
+	0x8BEB, 0xBDEB, 0x8BEC, 0xCEDC, 0x8BED, 0xD3EF, 0x8BEE, 0xDABD,	0x8BEF, 0xCEF3, 0x8BF0, 0xDABE, 0x8BF1, 0xD3D5, 0x8BF2, 0xBBE5,
+	0x8BF3, 0xDABF, 0x8BF4, 0xCBB5, 0x8BF5, 0xCBD0, 0x8BF6, 0xDAC0,	0x8BF7, 0xC7EB, 0x8BF8, 0xD6EE, 0x8BF9, 0xDAC1, 0x8BFA, 0xC5B5,
+	0x8BFB, 0xB6C1, 0x8BFC, 0xDAC2, 0x8BFD, 0xB7CC, 0x8BFE, 0xBFCE,	0x8BFF, 0xDAC3, 0x8C00, 0xDAC4, 0x8C01, 0xCBAD, 0x8C02, 0xDAC5,
+	0x8C03, 0xB5F7, 0x8C04, 0xDAC6, 0x8C05, 0xC1C2, 0x8C06, 0xD7BB,	0x8C07, 0xDAC7, 0x8C08, 0xCCB8, 0x8C09, 0xD79F, 0x8C0A, 0xD2EA,
+	0x8C0B, 0xC4B1, 0x8C0C, 0xDAC8, 0x8C0D, 0xB5FD, 0x8C0E, 0xBBD1,	0x8C0F, 0xDAC9, 0x8C10, 0xD0B3, 0x8C11, 0xDACA, 0x8C12, 0xDACB,
+	0x8C13, 0xCEBD, 0x8C14, 0xDACC, 0x8C15, 0xDACD, 0x8C16, 0xDACE,	0x8C17, 0xB2F7, 0x8C18, 0xDAD1, 0x8C19, 0xDACF, 0x8C1A, 0xD1E8,
+	0x8C1B, 0xDAD0, 0x8C1C, 0xC3D5, 0x8C1D, 0xDAD2, 0x8C1E, 0xD7A0,	0x8C1F, 0xDAD3, 0x8C20, 0xDAD4, 0x8C21, 0xDAD5, 0x8C22, 0xD0BB,
+	0x8C23, 0xD2A5, 0x8C24, 0xB0F9, 0x8C25, 0xDAD6, 0x8C26, 0xC7AB,	0x8C27, 0xDAD7, 0x8C28, 0xBDF7, 0x8C29, 0xC3A1, 0x8C2A, 0xDAD8,
+	0x8C2B, 0xDAD9, 0x8C2C, 0xC3FD, 0x8C2D, 0xCCB7, 0x8C2E, 0xDADA,	0x8C2F, 0xDADB, 0x8C30, 0xC0BE, 0x8C31, 0xC6D7, 0x8C32, 0xDADC,
+	0x8C33, 0xDADD, 0x8C34, 0xC7B4, 0x8C35, 0xDADE, 0x8C36, 0xDADF,	0x8C37, 0xB9C8, 0x8C38, 0xD840, 0x8C39, 0xD841, 0x8C3A, 0xD842,
+	0x8C3B, 0xD843, 0x8C3C, 0xD844, 0x8C3D, 0xD845, 0x8C3E, 0xD846,	0x8C3F, 0xD847, 0x8C40, 0xD848, 0x8C41, 0xBBED, 0x8C42, 0xD849,
+	0x8C43, 0xD84A, 0x8C44, 0xD84B, 0x8C45, 0xD84C, 0x8C46, 0xB6B9,	0x8C47, 0xF4F8, 0x8C48, 0xD84D, 0x8C49, 0xF4F9, 0x8C4A, 0xD84E,
+	0x8C4B, 0xD84F, 0x8C4C, 0xCDE3, 0x8C4D, 0xD850, 0x8C4E, 0xD851,	0x8C4F, 0xD852, 0x8C50, 0xD853, 0x8C51, 0xD854, 0x8C52, 0xD855,
+	0x8C53, 0xD856, 0x8C54, 0xD857, 0x8C55, 0xF5B9, 0x8C56, 0xD858,	0x8C57, 0xD859, 0x8C58, 0xD85A, 0x8C59, 0xD85B, 0x8C5A, 0xEBE0,
+	0x8C5B, 0xD85C, 0x8C5C, 0xD85D, 0x8C5D, 0xD85E, 0x8C5E, 0xD85F,	0x8C5F, 0xD860, 0x8C60, 0xD861, 0x8C61, 0xCFF3, 0x8C62, 0xBBBF,
+	0x8C63, 0xD862, 0x8C64, 0xD863, 0x8C65, 0xD864, 0x8C66, 0xD865,	0x8C67, 0xD866, 0x8C68, 0xD867, 0x8C69, 0xD868, 0x8C6A, 0xBAC0,
+	0x8C6B, 0xD4A5, 0x8C6C, 0xD869, 0x8C6D, 0xD86A, 0x8C6E, 0xD86B,	0x8C6F, 0xD86C, 0x8C70, 0xD86D, 0x8C71, 0xD86E, 0x8C72, 0xD86F,
+	0x8C73, 0xE1D9, 0x8C74, 0xD870, 0x8C75, 0xD871, 0x8C76, 0xD872,	0x8C77, 0xD873, 0x8C78, 0xF5F4, 0x8C79, 0xB1AA, 0x8C7A, 0xB2F2,
+	0x8C7B, 0xD874, 0x8C7C, 0xD875, 0x8C7D, 0xD876, 0x8C7E, 0xD877,	0x8C7F, 0xD878, 0x8C80, 0xD879, 0x8C81, 0xD87A, 0x8C82, 0xF5F5,
+	0x8C83, 0xD87B, 0x8C84, 0xD87C, 0x8C85, 0xF5F7, 0x8C86, 0xD87D,	0x8C87, 0xD87E, 0x8C88, 0xD880, 0x8C89, 0xBAD1, 0x8C8A, 0xF5F6,
+	0x8C8B, 0xD881, 0x8C8C, 0xC3B2, 0x8C8D, 0xD882, 0x8C8E, 0xD883,	0x8C8F, 0xD884, 0x8C90, 0xD885, 0x8C91, 0xD886, 0x8C92, 0xD887,
+	0x8C93, 0xD888, 0x8C94, 0xF5F9, 0x8C95, 0xD889, 0x8C96, 0xD88A,	0x8C97, 0xD88B, 0x8C98, 0xF5F8, 0x8C99, 0xD88C, 0x8C9A, 0xD88D,
+	0x8C9B, 0xD88E, 0x8C9C, 0xD88F, 0x8C9D, 0xD890, 0x8C9E, 0xD891,	0x8C9F, 0xD892, 0x8CA0, 0xD893, 0x8CA1, 0xD894, 0x8CA2, 0xD895,
+	0x8CA3, 0xD896, 0x8CA4, 0xD897, 0x8CA5, 0xD898, 0x8CA6, 0xD899,	0x8CA7, 0xD89A, 0x8CA8, 0xD89B, 0x8CA9, 0xD89C, 0x8CAA, 0xD89D,
+	0x8CAB, 0xD89E, 0x8CAC, 0xD89F, 0x8CAD, 0xD8A0, 0x8CAE, 0xD940,	0x8CAF, 0xD941, 0x8CB0, 0xD942, 0x8CB1, 0xD943, 0x8CB2, 0xD944,
+	0x8CB3, 0xD945, 0x8CB4, 0xD946, 0x8CB5, 0xD947, 0x8CB6, 0xD948,	0x8CB7, 0xD949, 0x8CB8, 0xD94A, 0x8CB9, 0xD94B, 0x8CBA, 0xD94C,
+	0x8CBB, 0xD94D, 0x8CBC, 0xD94E, 0x8CBD, 0xD94F, 0x8CBE, 0xD950,	0x8CBF, 0xD951, 0x8CC0, 0xD952, 0x8CC1, 0xD953, 0x8CC2, 0xD954,
+	0x8CC3, 0xD955, 0x8CC4, 0xD956, 0x8CC5, 0xD957, 0x8CC6, 0xD958,	0x8CC7, 0xD959, 0x8CC8, 0xD95A, 0x8CC9, 0xD95B, 0x8CCA, 0xD95C,
+	0x8CCB, 0xD95D, 0x8CCC, 0xD95E, 0x8CCD, 0xD95F, 0x8CCE, 0xD960,	0x8CCF, 0xD961, 0x8CD0, 0xD962, 0x8CD1, 0xD963, 0x8CD2, 0xD964,
+	0x8CD3, 0xD965, 0x8CD4, 0xD966, 0x8CD5, 0xD967, 0x8CD6, 0xD968,	0x8CD7, 0xD969, 0x8CD8, 0xD96A, 0x8CD9, 0xD96B, 0x8CDA, 0xD96C,
+	0x8CDB, 0xD96D, 0x8CDC, 0xD96E, 0x8CDD, 0xD96F, 0x8CDE, 0xD970,	0x8CDF, 0xD971, 0x8CE0, 0xD972, 0x8CE1, 0xD973, 0x8CE2, 0xD974,
+	0x8CE3, 0xD975, 0x8CE4, 0xD976, 0x8CE5, 0xD977, 0x8CE6, 0xD978,	0x8CE7, 0xD979, 0x8CE8, 0xD97A, 0x8CE9, 0xD97B, 0x8CEA, 0xD97C,
+	0x8CEB, 0xD97D, 0x8CEC, 0xD97E, 0x8CED, 0xD980, 0x8CEE, 0xD981,	0x8CEF, 0xD982, 0x8CF0, 0xD983, 0x8CF1, 0xD984, 0x8CF2, 0xD985,
+	0x8CF3, 0xD986, 0x8CF4, 0xD987, 0x8CF5, 0xD988, 0x8CF6, 0xD989,	0x8CF7, 0xD98A, 0x8CF8, 0xD98B, 0x8CF9, 0xD98C, 0x8CFA, 0xD98D,
+	0x8CFB, 0xD98E, 0x8CFC, 0xD98F, 0x8CFD, 0xD990, 0x8CFE, 0xD991,	0x8CFF, 0xD992, 0x8D00, 0xD993, 0x8D01, 0xD994, 0x8D02, 0xD995,
+	0x8D03, 0xD996, 0x8D04, 0xD997, 0x8D05, 0xD998, 0x8D06, 0xD999,	0x8D07, 0xD99A, 0x8D08, 0xD99B, 0x8D09, 0xD99C, 0x8D0A, 0xD99D,
+	0x8D0B, 0xD99E, 0x8D0C, 0xD99F, 0x8D0D, 0xD9A0, 0x8D0E, 0xDA40,	0x8D0F, 0xDA41, 0x8D10, 0xDA42, 0x8D11, 0xDA43, 0x8D12, 0xDA44,
+	0x8D13, 0xDA45, 0x8D14, 0xDA46, 0x8D15, 0xDA47, 0x8D16, 0xDA48,	0x8D17, 0xDA49, 0x8D18, 0xDA4A, 0x8D19, 0xDA4B, 0x8D1A, 0xDA4C,
+	0x8D1B, 0xDA4D, 0x8D1C, 0xDA4E, 0x8D1D, 0xB1B4, 0x8D1E, 0xD5EA,	0x8D1F, 0xB8BA, 0x8D20, 0xDA4F, 0x8D21, 0xB9B1, 0x8D22, 0xB2C6,
+	0x8D23, 0xD4F0, 0x8D24, 0xCFCD, 0x8D25, 0xB0DC, 0x8D26, 0xD5CB,	0x8D27, 0xBBF5, 0x8D28, 0xD6CA, 0x8D29, 0xB7B7, 0x8D2A, 0xCCB0,
+	0x8D2B, 0xC6B6, 0x8D2C, 0xB1E1, 0x8D2D, 0xB9BA, 0x8D2E, 0xD6FC,	0x8D2F, 0xB9E1, 0x8D30, 0xB7A1, 0x8D31, 0xBCFA, 0x8D32, 0xEADA,
+	0x8D33, 0xEADB, 0x8D34, 0xCCF9, 0x8D35, 0xB9F3, 0x8D36, 0xEADC,	0x8D37, 0xB4FB, 0x8D38, 0xC3B3, 0x8D39, 0xB7D1, 0x8D3A, 0xBAD8,
+	0x8D3B, 0xEADD, 0x8D3C, 0xD4F4, 0x8D3D, 0xEADE, 0x8D3E, 0xBCD6,	0x8D3F, 0xBBDF, 0x8D40, 0xEADF, 0x8D41, 0xC1DE, 0x8D42, 0xC2B8,
+	0x8D43, 0xD4DF, 0x8D44, 0xD7CA, 0x8D45, 0xEAE0, 0x8D46, 0xEAE1,	0x8D47, 0xEAE4, 0x8D48, 0xEAE2, 0x8D49, 0xEAE3, 0x8D4A, 0xC9DE,
+	0x8D4B, 0xB8B3, 0x8D4C, 0xB6C4, 0x8D4D, 0xEAE5, 0x8D4E, 0xCAEA,	0x8D4F, 0xC9CD, 0x8D50, 0xB4CD, 0x8D51, 0xDA50, 0x8D52, 0xDA51,
+	0x8D53, 0xE2D9, 0x8D54, 0xC5E2, 0x8D55, 0xEAE6, 0x8D56, 0xC0B5,	0x8D57, 0xDA52, 0x8D58, 0xD7B8, 0x8D59, 0xEAE7, 0x8D5A, 0xD7AC,
+	0x8D5B, 0xC8FC, 0x8D5C, 0xD8D3, 0x8D5D, 0xD8CD, 0x8D5E, 0xD4DE,	0x8D5F, 0xDA53, 0x8D60, 0xD4F9, 0x8D61, 0xC9C4, 0x8D62, 0xD3AE,
+	0x8D63, 0xB8D3, 0x8D64, 0xB3E0, 0x8D65, 0xDA54, 0x8D66, 0xC9E2,	0x8D67, 0xF4F6, 0x8D68, 0xDA55, 0x8D69, 0xDA56, 0x8D6A, 0xDA57,
+	0x8D6B, 0xBAD5, 0x8D6C, 0xDA58, 0x8D6D, 0xF4F7, 0x8D6E, 0xDA59,	0x8D6F, 0xDA5A, 0x8D70, 0xD7DF, 0x8D71, 0xDA5B, 0x8D72, 0xDA5C,
+	0x8D73, 0xF4F1, 0x8D74, 0xB8B0, 0x8D75, 0xD5D4, 0x8D76, 0xB8CF,	0x8D77, 0xC6F0, 0x8D78, 0xDA5D, 0x8D79, 0xDA5E, 0x8D7A, 0xDA5F,
+	0x8D7B, 0xDA60, 0x8D7C, 0xDA61, 0x8D7D, 0xDA62, 0x8D7E, 0xDA63,	0x8D7F, 0xDA64, 0x8D80, 0xDA65, 0x8D81, 0xB3C3, 0x8D82, 0xDA66,
+	0x8D83, 0xDA67, 0x8D84, 0xF4F2, 0x8D85, 0xB3AC, 0x8D86, 0xDA68,	0x8D87, 0xDA69, 0x8D88, 0xDA6A, 0x8D89, 0xDA6B, 0x8D8A, 0xD4BD,
+	0x8D8B, 0xC7F7, 0x8D8C, 0xDA6C, 0x8D8D, 0xDA6D, 0x8D8E, 0xDA6E,	0x8D8F, 0xDA6F, 0x8D90, 0xDA70, 0x8D91, 0xF4F4, 0x8D92, 0xDA71,
+	0x8D93, 0xDA72, 0x8D94, 0xF4F3, 0x8D95, 0xDA73, 0x8D96, 0xDA74,	0x8D97, 0xDA75, 0x8D98, 0xDA76, 0x8D99, 0xDA77, 0x8D9A, 0xDA78,
+	0x8D9B, 0xDA79, 0x8D9C, 0xDA7A, 0x8D9D, 0xDA7B, 0x8D9E, 0xDA7C,	0x8D9F, 0xCCCB, 0x8DA0, 0xDA7D, 0x8DA1, 0xDA7E, 0x8DA2, 0xDA80,
+	0x8DA3, 0xC8A4, 0x8DA4, 0xDA81, 0x8DA5, 0xDA82, 0x8DA6, 0xDA83,	0x8DA7, 0xDA84, 0x8DA8, 0xDA85, 0x8DA9, 0xDA86, 0x8DAA, 0xDA87,
+	0x8DAB, 0xDA88, 0x8DAC, 0xDA89, 0x8DAD, 0xDA8A, 0x8DAE, 0xDA8B,	0x8DAF, 0xDA8C, 0x8DB0, 0xDA8D, 0x8DB1, 0xF4F5, 0x8DB2, 0xDA8E,
+	0x8DB3, 0xD7E3, 0x8DB4, 0xC5BF, 0x8DB5, 0xF5C0, 0x8DB6, 0xDA8F,	0x8DB7, 0xDA90, 0x8DB8, 0xF5BB, 0x8DB9, 0xDA91, 0x8DBA, 0xF5C3,
+	0x8DBB, 0xDA92, 0x8DBC, 0xF5C2, 0x8DBD, 0xDA93, 0x8DBE, 0xD6BA,	0x8DBF, 0xF5C1, 0x8DC0, 0xDA94, 0x8DC1, 0xDA95, 0x8DC2, 0xDA96,
+	0x8DC3, 0xD4BE, 0x8DC4, 0xF5C4, 0x8DC5, 0xDA97, 0x8DC6, 0xF5CC,	0x8DC7, 0xDA98, 0x8DC8, 0xDA99, 0x8DC9, 0xDA9A, 0x8DCA, 0xDA9B,
+	0x8DCB, 0xB0CF, 0x8DCC, 0xB5F8, 0x8DCD, 0xDA9C, 0x8DCE, 0xF5C9,	0x8DCF, 0xF5CA, 0x8DD0, 0xDA9D, 0x8DD1, 0xC5DC, 0x8DD2, 0xDA9E,
+	0x8DD3, 0xDA9F, 0x8DD4, 0xDAA0, 0x8DD5, 0xDB40, 0x8DD6, 0xF5C5,	0x8DD7, 0xF5C6, 0x8DD8, 0xDB41, 0x8DD9, 0xDB42, 0x8DDA, 0xF5C7,
+	0x8DDB, 0xF5CB, 0x8DDC, 0xDB43, 0x8DDD, 0xBEE0, 0x8DDE, 0xF5C8,	0x8DDF, 0xB8FA, 0x8DE0, 0xDB44, 0x8DE1, 0xDB45, 0x8DE2, 0xDB46,
+	0x8DE3, 0xF5D0, 0x8DE4, 0xF5D3, 0x8DE5, 0xDB47, 0x8DE6, 0xDB48,	0x8DE7, 0xDB49, 0x8DE8, 0xBFE7, 0x8DE9, 0xDB4A, 0x8DEA, 0xB9F2,
+	0x8DEB, 0xF5BC, 0x8DEC, 0xF5CD, 0x8DED, 0xDB4B, 0x8DEE, 0xDB4C,	0x8DEF, 0xC2B7, 0x8DF0, 0xDB4D, 0x8DF1, 0xDB4E, 0x8DF2, 0xDB4F,
+	0x8DF3, 0xCCF8, 0x8DF4, 0xDB50, 0x8DF5, 0xBCF9, 0x8DF6, 0xDB51,	0x8DF7, 0xF5CE, 0x8DF8, 0xF5CF, 0x8DF9, 0xF5D1, 0x8DFA, 0xB6E5,
+	0x8DFB, 0xF5D2, 0x8DFC, 0xDB52, 0x8DFD, 0xF5D5, 0x8DFE, 0xDB53,	0x8DFF, 0xDB54, 0x8E00, 0xDB55, 0x8E01, 0xDB56, 0x8E02, 0xDB57,
+	0x8E03, 0xDB58, 0x8E04, 0xDB59, 0x8E05, 0xF5BD, 0x8E06, 0xDB5A,	0x8E07, 0xDB5B, 0x8E08, 0xDB5C, 0x8E09, 0xF5D4, 0x8E0A, 0xD3BB,
+	0x8E0B, 0xDB5D, 0x8E0C, 0xB3EC, 0x8E0D, 0xDB5E, 0x8E0E, 0xDB5F,	0x8E0F, 0xCCA4, 0x8E10, 0xDB60, 0x8E11, 0xDB61, 0x8E12, 0xDB62,
+	0x8E13, 0xDB63, 0x8E14, 0xF5D6, 0x8E15, 0xDB64, 0x8E16, 0xDB65,	0x8E17, 0xDB66, 0x8E18, 0xDB67, 0x8E19, 0xDB68, 0x8E1A, 0xDB69,
+	0x8E1B, 0xDB6A, 0x8E1C, 0xDB6B, 0x8E1D, 0xF5D7, 0x8E1E, 0xBEE1,	0x8E1F, 0xF5D8, 0x8E20, 0xDB6C, 0x8E21, 0xDB6D, 0x8E22, 0xCCDF,
+	0x8E23, 0xF5DB, 0x8E24, 0xDB6E, 0x8E25, 0xDB6F, 0x8E26, 0xDB70,	0x8E27, 0xDB71, 0x8E28, 0xDB72, 0x8E29, 0xB2C8, 0x8E2A, 0xD7D9,
+	0x8E2B, 0xDB73, 0x8E2C, 0xF5D9, 0x8E2D, 0xDB74, 0x8E2E, 0xF5DA,	0x8E2F, 0xF5DC, 0x8E30, 0xDB75, 0x8E31, 0xF5E2, 0x8E32, 0xDB76,
+	0x8E33, 0xDB77, 0x8E34, 0xDB78, 0x8E35, 0xF5E0, 0x8E36, 0xDB79,	0x8E37, 0xDB7A, 0x8E38, 0xDB7B, 0x8E39, 0xF5DF, 0x8E3A, 0xF5DD,
+	0x8E3B, 0xDB7C, 0x8E3C, 0xDB7D, 0x8E3D, 0xF5E1, 0x8E3E, 0xDB7E,	0x8E3F, 0xDB80, 0x8E40, 0xF5DE, 0x8E41, 0xF5E4, 0x8E42, 0xF5E5,
+	0x8E43, 0xDB81, 0x8E44, 0xCCE3, 0x8E45, 0xDB82, 0x8E46, 0xDB83,	0x8E47, 0xE5BF, 0x8E48, 0xB5B8, 0x8E49, 0xF5E3, 0x8E4A, 0xF5E8,
+	0x8E4B, 0xCCA3, 0x8E4C, 0xDB84, 0x8E4D, 0xDB85, 0x8E4E, 0xDB86,	0x8E4F, 0xDB87, 0x8E50, 0xDB88, 0x8E51, 0xF5E6, 0x8E52, 0xF5E7,
+	0x8E53, 0xDB89, 0x8E54, 0xDB8A, 0x8E55, 0xDB8B, 0x8E56, 0xDB8C,	0x8E57, 0xDB8D, 0x8E58, 0xDB8E, 0x8E59, 0xF5BE, 0x8E5A, 0xDB8F,
+	0x8E5B, 0xDB90, 0x8E5C, 0xDB91, 0x8E5D, 0xDB92, 0x8E5E, 0xDB93,	0x8E5F, 0xDB94, 0x8E60, 0xDB95, 0x8E61, 0xDB96, 0x8E62, 0xDB97,
+	0x8E63, 0xDB98, 0x8E64, 0xDB99, 0x8E65, 0xDB9A, 0x8E66, 0xB1C4,	0x8E67, 0xDB9B, 0x8E68, 0xDB9C, 0x8E69, 0xF5BF, 0x8E6A, 0xDB9D,
+	0x8E6B, 0xDB9E, 0x8E6C, 0xB5C5, 0x8E6D, 0xB2E4, 0x8E6E, 0xDB9F,	0x8E6F, 0xF5EC, 0x8E70, 0xF5E9, 0x8E71, 0xDBA0, 0x8E72, 0xB6D7,
+	0x8E73, 0xDC40, 0x8E74, 0xF5ED, 0x8E75, 0xDC41, 0x8E76, 0xF5EA,	0x8E77, 0xDC42, 0x8E78, 0xDC43, 0x8E79, 0xDC44, 0x8E7A, 0xDC45,
+	0x8E7B, 0xDC46, 0x8E7C, 0xF5EB, 0x8E7D, 0xDC47, 0x8E7E, 0xDC48,	0x8E7F, 0xB4DA, 0x8E80, 0xDC49, 0x8E81, 0xD4EA, 0x8E82, 0xDC4A,
+	0x8E83, 0xDC4B, 0x8E84, 0xDC4C, 0x8E85, 0xF5EE, 0x8E86, 0xDC4D,	0x8E87, 0xB3F9, 0x8E88, 0xDC4E, 0x8E89, 0xDC4F, 0x8E8A, 0xDC50,
+	0x8E8B, 0xDC51, 0x8E8C, 0xDC52, 0x8E8D, 0xDC53, 0x8E8E, 0xDC54,	0x8E8F, 0xF5EF, 0x8E90, 0xF5F1, 0x8E91, 0xDC55, 0x8E92, 0xDC56,
+	0x8E93, 0xDC57, 0x8E94, 0xF5F0, 0x8E95, 0xDC58, 0x8E96, 0xDC59,	0x8E97, 0xDC5A, 0x8E98, 0xDC5B, 0x8E99, 0xDC5C, 0x8E9A, 0xDC5D,
+	0x8E9B, 0xDC5E, 0x8E9C, 0xF5F2, 0x8E9D, 0xDC5F, 0x8E9E, 0xF5F3,	0x8E9F, 0xDC60, 0x8EA0, 0xDC61, 0x8EA1, 0xDC62, 0x8EA2, 0xDC63,
+	0x8EA3, 0xDC64, 0x8EA4, 0xDC65, 0x8EA5, 0xDC66, 0x8EA6, 0xDC67,	0x8EA7, 0xDC68, 0x8EA8, 0xDC69, 0x8EA9, 0xDC6A, 0x8EAA, 0xDC6B,
+	0x8EAB, 0xC9ED, 0x8EAC, 0xB9AA, 0x8EAD, 0xDC6C, 0x8EAE, 0xDC6D,	0x8EAF, 0xC7FB, 0x8EB0, 0xDC6E, 0x8EB1, 0xDC6F, 0x8EB2, 0xB6E3,
+	0x8EB3, 0xDC70, 0x8EB4, 0xDC71, 0x8EB5, 0xDC72, 0x8EB6, 0xDC73,	0x8EB7, 0xDC74, 0x8EB8, 0xDC75, 0x8EB9, 0xDC76, 0x8EBA, 0xCCC9,
+	0x8EBB, 0xDC77, 0x8EBC, 0xDC78, 0x8EBD, 0xDC79, 0x8EBE, 0xDC7A,	0x8EBF, 0xDC7B, 0x8EC0, 0xDC7C, 0x8EC1, 0xDC7D, 0x8EC2, 0xDC7E,
+	0x8EC3, 0xDC80, 0x8EC4, 0xDC81, 0x8EC5, 0xDC82, 0x8EC6, 0xDC83,	0x8EC7, 0xDC84, 0x8EC8, 0xDC85, 0x8EC9, 0xDC86, 0x8ECA, 0xDC87,
+	0x8ECB, 0xDC88, 0x8ECC, 0xDC89, 0x8ECD, 0xDC8A, 0x8ECE, 0xEAA6,	0x8ECF, 0xDC8B, 0x8ED0, 0xDC8C, 0x8ED1, 0xDC8D, 0x8ED2, 0xDC8E,
+	0x8ED3, 0xDC8F, 0x8ED4, 0xDC90, 0x8ED5, 0xDC91, 0x8ED6, 0xDC92,	0x8ED7, 0xDC93, 0x8ED8, 0xDC94, 0x8ED9, 0xDC95, 0x8EDA, 0xDC96,
+	0x8EDB, 0xDC97, 0x8EDC, 0xDC98, 0x8EDD, 0xDC99, 0x8EDE, 0xDC9A,	0x8EDF, 0xDC9B, 0x8EE0, 0xDC9C, 0x8EE1, 0xDC9D, 0x8EE2, 0xDC9E,
+	0x8EE3, 0xDC9F, 0x8EE4, 0xDCA0, 0x8EE5, 0xDD40, 0x8EE6, 0xDD41,	0x8EE7, 0xDD42, 0x8EE8, 0xDD43, 0x8EE9, 0xDD44, 0x8EEA, 0xDD45,
+	0x8EEB, 0xDD46, 0x8EEC, 0xDD47, 0x8EED, 0xDD48, 0x8EEE, 0xDD49,	0x8EEF, 0xDD4A, 0x8EF0, 0xDD4B, 0x8EF1, 0xDD4C, 0x8EF2, 0xDD4D,
+	0x8EF3, 0xDD4E, 0x8EF4, 0xDD4F, 0x8EF5, 0xDD50, 0x8EF6, 0xDD51,	0x8EF7, 0xDD52, 0x8EF8, 0xDD53, 0x8EF9, 0xDD54, 0x8EFA, 0xDD55,
+	0x8EFB, 0xDD56, 0x8EFC, 0xDD57, 0x8EFD, 0xDD58, 0x8EFE, 0xDD59,	0x8EFF, 0xDD5A, 0x8F00, 0xDD5B, 0x8F01, 0xDD5C, 0x8F02, 0xDD5D,
+	0x8F03, 0xDD5E, 0x8F04, 0xDD5F, 0x8F05, 0xDD60, 0x8F06, 0xDD61,	0x8F07, 0xDD62, 0x8F08, 0xDD63, 0x8F09, 0xDD64, 0x8F0A, 0xDD65,
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+	0x978B, 0xD0AC, 0x978C, 0xEC94, 0x978D, 0xB0B0, 0x978E, 0xEC95,	0x978F, 0xEC96, 0x9790, 0xEC97, 0x9791, 0xF7B2, 0x9792, 0xF7B3,
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+	0x979B, 0xEC9E, 0x979C, 0xEC9F, 0x979D, 0xECA0, 0x979E, 0xED40,	0x979F, 0xED41, 0x97A0, 0xBECF, 0x97A1, 0xED42, 0x97A2, 0xED43,
+	0x97A3, 0xF7B7, 0x97A4, 0xED44, 0x97A5, 0xED45, 0x97A6, 0xED46,	0x97A7, 0xED47, 0x97A8, 0xED48, 0x97A9, 0xED49, 0x97AA, 0xED4A,
+	0x97AB, 0xF7B6, 0x97AC, 0xED4B, 0x97AD, 0xB1DE, 0x97AE, 0xED4C,	0x97AF, 0xF7B5, 0x97B0, 0xED4D, 0x97B1, 0xED4E, 0x97B2, 0xF7B8,
+	0x97B3, 0xED4F, 0x97B4, 0xF7B9, 0x97B5, 0xED50, 0x97B6, 0xED51,	0x97B7, 0xED52, 0x97B8, 0xED53, 0x97B9, 0xED54, 0x97BA, 0xED55,
+	0x97BB, 0xED56, 0x97BC, 0xED57, 0x97BD, 0xED58, 0x97BE, 0xED59,	0x97BF, 0xED5A, 0x97C0, 0xED5B, 0x97C1, 0xED5C, 0x97C2, 0xED5D,
+	0x97C3, 0xED5E, 0x97C4, 0xED5F, 0x97C5, 0xED60, 0x97C6, 0xED61,	0x97C7, 0xED62, 0x97C8, 0xED63, 0x97C9, 0xED64, 0x97CA, 0xED65,
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+	0x97D3, 0xED6E, 0x97D4, 0xED6F, 0x97D5, 0xED70, 0x97D6, 0xED71,	0x97D7, 0xED72, 0x97D8, 0xED73, 0x97D9, 0xED74, 0x97DA, 0xED75,
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+	0x97E3, 0xED7E, 0x97E4, 0xED80, 0x97E5, 0xED81, 0x97E6, 0xCEA4,	0x97E7, 0xC8CD, 0x97E8, 0xED82, 0x97E9, 0xBAAB, 0x97EA, 0xE8B8,
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+	0x97F3, 0xD2F4, 0x97F4, 0xED88, 0x97F5, 0xD4CF, 0x97F6, 0xC9D8,	0x97F7, 0xED89, 0x97F8, 0xED8A, 0x97F9, 0xED8B, 0x97FA, 0xED8C,
+	0x97FB, 0xED8D, 0x97FC, 0xED8E, 0x97FD, 0xED8F, 0x97FE, 0xED90,	0x97FF, 0xED91, 0x9800, 0xED92, 0x9801, 0xED93, 0x9802, 0xED94,
+	0x9803, 0xED95, 0x9804, 0xED96, 0x9805, 0xED97, 0x9806, 0xED98,	0x9807, 0xED99, 0x9808, 0xED9A, 0x9809, 0xED9B, 0x980A, 0xED9C,
+	0x980B, 0xED9D, 0x980C, 0xED9E, 0x980D, 0xED9F, 0x980E, 0xEDA0,	0x980F, 0xEE40, 0x9810, 0xEE41, 0x9811, 0xEE42, 0x9812, 0xEE43,
+	0x9813, 0xEE44, 0x9814, 0xEE45, 0x9815, 0xEE46, 0x9816, 0xEE47,	0x9817, 0xEE48, 0x9818, 0xEE49, 0x9819, 0xEE4A, 0x981A, 0xEE4B,
+	0x981B, 0xEE4C, 0x981C, 0xEE4D, 0x981D, 0xEE4E, 0x981E, 0xEE4F,	0x981F, 0xEE50, 0x9820, 0xEE51, 0x9821, 0xEE52, 0x9822, 0xEE53,
+	0x9823, 0xEE54, 0x9824, 0xEE55, 0x9825, 0xEE56, 0x9826, 0xEE57,	0x9827, 0xEE58, 0x9828, 0xEE59, 0x9829, 0xEE5A, 0x982A, 0xEE5B,
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+	0x983B, 0xEE6C, 0x983C, 0xEE6D, 0x983D, 0xEE6E, 0x983E, 0xEE6F,	0x983F, 0xEE70, 0x9840, 0xEE71, 0x9841, 0xEE72, 0x9842, 0xEE73,
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+	0x984B, 0xEE7C, 0x984C, 0xEE7D, 0x984D, 0xEE7E, 0x984E, 0xEE80,	0x984F, 0xEE81, 0x9850, 0xEE82, 0x9851, 0xEE83, 0x9852, 0xEE84,
+	0x9853, 0xEE85, 0x9854, 0xEE86, 0x9855, 0xEE87, 0x9856, 0xEE88,	0x9857, 0xEE89, 0x9858, 0xEE8A, 0x9859, 0xEE8B, 0x985A, 0xEE8C,
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+	0x988B, 0xEF46, 0x988C, 0xF2A2, 0x988D, 0xF2A3, 0x988E, 0xEF47,	0x988F, 0xF2A4, 0x9890, 0xD2C3, 0x9891, 0xC6B5, 0x9892, 0xEF48,
+	0x9893, 0xCDC7, 0x9894, 0xF2A5, 0x9895, 0xEF49, 0x9896, 0xD3B1,	0x9897, 0xBFC5, 0x9898, 0xCCE2, 0x9899, 0xEF4A, 0x989A, 0xF2A6,
+	0x989B, 0xF2A7, 0x989C, 0xD1D5, 0x989D, 0xB6EE, 0x989E, 0xF2A8,	0x989F, 0xF2A9, 0x98A0, 0xB5DF, 0x98A1, 0xF2AA, 0x98A2, 0xF2AB,
+	0x98A3, 0xEF4B, 0x98A4, 0xB2FC, 0x98A5, 0xF2AC, 0x98A6, 0xF2AD,	0x98A7, 0xC8A7, 0x98A8, 0xEF4C, 0x98A9, 0xEF4D, 0x98AA, 0xEF4E,
+	0x98AB, 0xEF4F, 0x98AC, 0xEF50, 0x98AD, 0xEF51, 0x98AE, 0xEF52,	0x98AF, 0xEF53, 0x98B0, 0xEF54, 0x98B1, 0xEF55, 0x98B2, 0xEF56,
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+	0x98D3, 0xECAB, 0x98D4, 0xEF74, 0x98D5, 0xECAC, 0x98D6, 0xEF75,	0x98D7, 0xEF76, 0x98D8, 0xC6AE, 0x98D9, 0xECAD, 0x98DA, 0xECAE,
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+	0x98E3, 0xEF7D, 0x98E4, 0xEF7E, 0x98E5, 0xEF80, 0x98E6, 0xEF81,	0x98E7, 0xE2B8, 0x98E8, 0xF7CF, 0x98E9, 0xEF82, 0x98EA, 0xEF83,
+	0x98EB, 0xEF84, 0x98EC, 0xEF85, 0x98ED, 0xEF86, 0x98EE, 0xEF87,	0x98EF, 0xEF88, 0x98F0, 0xEF89, 0x98F1, 0xEF8A, 0x98F2, 0xEF8B,
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+	0x9913, 0xF049, 0x9914, 0xF04A, 0x9915, 0xF04B, 0x9916, 0xF04C,	0x9917, 0xF04D, 0x9918, 0xF04E, 0x9919, 0xF04F, 0x991A, 0xF050,
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+	0x9943, 0xF078, 0x9944, 0xF079, 0x9945, 0xF07A, 0x9946, 0xF07B,	0x9947, 0xF07C, 0x9948, 0xF07D, 0x9949, 0xF07E, 0x994A, 0xF080,
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+	0x9953, 0xF089, 0x9954, 0xF7D3, 0x9955, 0xF7D2, 0x9956, 0xF08A,	0x9957, 0xF08B, 0x9958, 0xF08C, 0x9959, 0xF08D, 0x995A, 0xF08E,
+	0x995B, 0xF08F, 0x995C, 0xF090, 0x995D, 0xF091, 0x995E, 0xF092,	0x995F, 0xF093, 0x9960, 0xF094, 0x9961, 0xF095, 0x9962, 0xF096,
+	0x9963, 0xE2BB, 0x9964, 0xF097, 0x9965, 0xBCA2, 0x9966, 0xF098,	0x9967, 0xE2BC, 0x9968, 0xE2BD, 0x9969, 0xE2BE, 0x996A, 0xE2BF,
+	0x996B, 0xE2C0, 0x996C, 0xE2C1, 0x996D, 0xB7B9, 0x996E, 0xD2FB,	0x996F, 0xBDA4, 0x9970, 0xCACE, 0x9971, 0xB1A5, 0x9972, 0xCBC7,
+	0x9973, 0xF099, 0x9974, 0xE2C2, 0x9975, 0xB6FC, 0x9976, 0xC8C4,	0x9977, 0xE2C3, 0x9978, 0xF09A, 0x9979, 0xF09B, 0x997A, 0xBDC8,
+	0x997B, 0xF09C, 0x997C, 0xB1FD, 0x997D, 0xE2C4, 0x997E, 0xF09D,	0x997F, 0xB6F6, 0x9980, 0xE2C5, 0x9981, 0xC4D9, 0x9982, 0xF09E,
+	0x9983, 0xF09F, 0x9984, 0xE2C6, 0x9985, 0xCFDA, 0x9986, 0xB9DD,	0x9987, 0xE2C7, 0x9988, 0xC0A1, 0x9989, 0xF0A0, 0x998A, 0xE2C8,
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+	0x9993, 0xE2CC, 0x9994, 0xE2CD, 0x9995, 0xE2CE, 0x9996, 0xCAD7,	0x9997, 0xD8B8, 0x9998, 0xD9E5, 0x9999, 0xCFE3, 0x999A, 0xF142,
+	0x999B, 0xF143, 0x999C, 0xF144, 0x999D, 0xF145, 0x999E, 0xF146,	0x999F, 0xF147, 0x99A0, 0xF148, 0x99A1, 0xF149, 0x99A2, 0xF14A,
+	0x99A3, 0xF14B, 0x99A4, 0xF14C, 0x99A5, 0xF0A5, 0x99A6, 0xF14D,	0x99A7, 0xF14E, 0x99A8, 0xDCB0, 0x99A9, 0xF14F, 0x99AA, 0xF150,
+	0x99AB, 0xF151, 0x99AC, 0xF152, 0x99AD, 0xF153, 0x99AE, 0xF154,	0x99AF, 0xF155, 0x99B0, 0xF156, 0x99B1, 0xF157, 0x99B2, 0xF158,
+	0x99B3, 0xF159, 0x99B4, 0xF15A, 0x99B5, 0xF15B, 0x99B6, 0xF15C,	0x99B7, 0xF15D, 0x99B8, 0xF15E, 0x99B9, 0xF15F, 0x99BA, 0xF160,
+	0x99BB, 0xF161, 0x99BC, 0xF162, 0x99BD, 0xF163, 0x99BE, 0xF164,	0x99BF, 0xF165, 0x99C0, 0xF166, 0x99C1, 0xF167, 0x99C2, 0xF168,
+	0x99C3, 0xF169, 0x99C4, 0xF16A, 0x99C5, 0xF16B, 0x99C6, 0xF16C,	0x99C7, 0xF16D, 0x99C8, 0xF16E, 0x99C9, 0xF16F, 0x99CA, 0xF170,
+	0x99CB, 0xF171, 0x99CC, 0xF172, 0x99CD, 0xF173, 0x99CE, 0xF174,	0x99CF, 0xF175, 0x99D0, 0xF176, 0x99D1, 0xF177, 0x99D2, 0xF178,
+	0x99D3, 0xF179, 0x99D4, 0xF17A, 0x99D5, 0xF17B, 0x99D6, 0xF17C,	0x99D7, 0xF17D, 0x99D8, 0xF17E, 0x99D9, 0xF180, 0x99DA, 0xF181,
+	0x99DB, 0xF182, 0x99DC, 0xF183, 0x99DD, 0xF184, 0x99DE, 0xF185,	0x99DF, 0xF186, 0x99E0, 0xF187, 0x99E1, 0xF188, 0x99E2, 0xF189,
+	0x99E3, 0xF18A, 0x99E4, 0xF18B, 0x99E5, 0xF18C, 0x99E6, 0xF18D,	0x99E7, 0xF18E, 0x99E8, 0xF18F, 0x99E9, 0xF190, 0x99EA, 0xF191,
+	0x99EB, 0xF192, 0x99EC, 0xF193, 0x99ED, 0xF194, 0x99EE, 0xF195,	0x99EF, 0xF196, 0x99F0, 0xF197, 0x99F1, 0xF198, 0x99F2, 0xF199,
+	0x99F3, 0xF19A, 0x99F4, 0xF19B, 0x99F5, 0xF19C, 0x99F6, 0xF19D,	0x99F7, 0xF19E, 0x99F8, 0xF19F, 0x99F9, 0xF1A0, 0x99FA, 0xF240,
+	0x99FB, 0xF241, 0x99FC, 0xF242, 0x99FD, 0xF243, 0x99FE, 0xF244,	0x99FF, 0xF245, 0x9A00, 0xF246, 0x9A01, 0xF247, 0x9A02, 0xF248,
+	0x9A03, 0xF249, 0x9A04, 0xF24A, 0x9A05, 0xF24B, 0x9A06, 0xF24C,	0x9A07, 0xF24D, 0x9A08, 0xF24E, 0x9A09, 0xF24F, 0x9A0A, 0xF250,
+	0x9A0B, 0xF251, 0x9A0C, 0xF252, 0x9A0D, 0xF253, 0x9A0E, 0xF254,	0x9A0F, 0xF255, 0x9A10, 0xF256, 0x9A11, 0xF257, 0x9A12, 0xF258,
+	0x9A13, 0xF259, 0x9A14, 0xF25A, 0x9A15, 0xF25B, 0x9A16, 0xF25C,	0x9A17, 0xF25D, 0x9A18, 0xF25E, 0x9A19, 0xF25F, 0x9A1A, 0xF260,
+	0x9A1B, 0xF261, 0x9A1C, 0xF262, 0x9A1D, 0xF263, 0x9A1E, 0xF264,	0x9A1F, 0xF265, 0x9A20, 0xF266, 0x9A21, 0xF267, 0x9A22, 0xF268,
+	0x9A23, 0xF269, 0x9A24, 0xF26A, 0x9A25, 0xF26B, 0x9A26, 0xF26C,	0x9A27, 0xF26D, 0x9A28, 0xF26E, 0x9A29, 0xF26F, 0x9A2A, 0xF270,
+	0x9A2B, 0xF271, 0x9A2C, 0xF272, 0x9A2D, 0xF273, 0x9A2E, 0xF274,	0x9A2F, 0xF275, 0x9A30, 0xF276, 0x9A31, 0xF277, 0x9A32, 0xF278,
+	0x9A33, 0xF279, 0x9A34, 0xF27A, 0x9A35, 0xF27B, 0x9A36, 0xF27C,	0x9A37, 0xF27D, 0x9A38, 0xF27E, 0x9A39, 0xF280, 0x9A3A, 0xF281,
+	0x9A3B, 0xF282, 0x9A3C, 0xF283, 0x9A3D, 0xF284, 0x9A3E, 0xF285,	0x9A3F, 0xF286, 0x9A40, 0xF287, 0x9A41, 0xF288, 0x9A42, 0xF289,
+	0x9A43, 0xF28A, 0x9A44, 0xF28B, 0x9A45, 0xF28C, 0x9A46, 0xF28D,	0x9A47, 0xF28E, 0x9A48, 0xF28F, 0x9A49, 0xF290, 0x9A4A, 0xF291,
+	0x9A4B, 0xF292, 0x9A4C, 0xF293, 0x9A4D, 0xF294, 0x9A4E, 0xF295,	0x9A4F, 0xF296, 0x9A50, 0xF297, 0x9A51, 0xF298, 0x9A52, 0xF299,
+	0x9A53, 0xF29A, 0x9A54, 0xF29B, 0x9A55, 0xF29C, 0x9A56, 0xF29D,	0x9A57, 0xF29E, 0x9A58, 0xF29F, 0x9A59, 0xF2A0, 0x9A5A, 0xF340,
+	0x9A5B, 0xF341, 0x9A5C, 0xF342, 0x9A5D, 0xF343, 0x9A5E, 0xF344,	0x9A5F, 0xF345, 0x9A60, 0xF346, 0x9A61, 0xF347, 0x9A62, 0xF348,
+	0x9A63, 0xF349, 0x9A64, 0xF34A, 0x9A65, 0xF34B, 0x9A66, 0xF34C,	0x9A67, 0xF34D, 0x9A68, 0xF34E, 0x9A69, 0xF34F, 0x9A6A, 0xF350,
+	0x9A6B, 0xF351, 0x9A6C, 0xC2ED, 0x9A6D, 0xD4A6, 0x9A6E, 0xCDD4,	0x9A6F, 0xD1B1, 0x9A70, 0xB3DB, 0x9A71, 0xC7FD, 0x9A72, 0xF352,
+	0x9A73, 0xB2B5, 0x9A74, 0xC2BF, 0x9A75, 0xE6E0, 0x9A76, 0xCABB,	0x9A77, 0xE6E1, 0x9A78, 0xE6E2, 0x9A79, 0xBED4, 0x9A7A, 0xE6E3,
+	0x9A7B, 0xD7A4, 0x9A7C, 0xCDD5, 0x9A7D, 0xE6E5, 0x9A7E, 0xBCDD,	0x9A7F, 0xE6E4, 0x9A80, 0xE6E6, 0x9A81, 0xE6E7, 0x9A82, 0xC2EE,
+	0x9A83, 0xF353, 0x9A84, 0xBDBE, 0x9A85, 0xE6E8, 0x9A86, 0xC2E6,	0x9A87, 0xBAA7, 0x9A88, 0xE6E9, 0x9A89, 0xF354, 0x9A8A, 0xE6EA,
+	0x9A8B, 0xB3D2, 0x9A8C, 0xD1E9, 0x9A8D, 0xF355, 0x9A8E, 0xF356,	0x9A8F, 0xBFA5, 0x9A90, 0xE6EB, 0x9A91, 0xC6EF, 0x9A92, 0xE6EC,
+	0x9A93, 0xE6ED, 0x9A94, 0xF357, 0x9A95, 0xF358, 0x9A96, 0xE6EE,	0x9A97, 0xC6AD, 0x9A98, 0xE6EF, 0x9A99, 0xF359, 0x9A9A, 0xC9A7,
+	0x9A9B, 0xE6F0, 0x9A9C, 0xE6F1, 0x9A9D, 0xE6F2, 0x9A9E, 0xE5B9,	0x9A9F, 0xE6F3, 0x9AA0, 0xE6F4, 0x9AA1, 0xC2E2, 0x9AA2, 0xE6F5,
+	0x9AA3, 0xE6F6, 0x9AA4, 0xD6E8, 0x9AA5, 0xE6F7, 0x9AA6, 0xF35A,	0x9AA7, 0xE6F8, 0x9AA8, 0xB9C7, 0x9AA9, 0xF35B, 0x9AAA, 0xF35C,
+	0x9AAB, 0xF35D, 0x9AAC, 0xF35E, 0x9AAD, 0xF35F, 0x9AAE, 0xF360,	0x9AAF, 0xF361, 0x9AB0, 0xF7BB, 0x9AB1, 0xF7BA, 0x9AB2, 0xF362,
+	0x9AB3, 0xF363, 0x9AB4, 0xF364, 0x9AB5, 0xF365, 0x9AB6, 0xF7BE,	0x9AB7, 0xF7BC, 0x9AB8, 0xBAA1, 0x9AB9, 0xF366, 0x9ABA, 0xF7BF,
+	0x9ABB, 0xF367, 0x9ABC, 0xF7C0, 0x9ABD, 0xF368, 0x9ABE, 0xF369,	0x9ABF, 0xF36A, 0x9AC0, 0xF7C2, 0x9AC1, 0xF7C1, 0x9AC2, 0xF7C4,
+	0x9AC3, 0xF36B, 0x9AC4, 0xF36C, 0x9AC5, 0xF7C3, 0x9AC6, 0xF36D,	0x9AC7, 0xF36E, 0x9AC8, 0xF36F, 0x9AC9, 0xF370, 0x9ACA, 0xF371,
+	0x9ACB, 0xF7C5, 0x9ACC, 0xF7C6, 0x9ACD, 0xF372, 0x9ACE, 0xF373,	0x9ACF, 0xF374, 0x9AD0, 0xF375, 0x9AD1, 0xF7C7, 0x9AD2, 0xF376,
+	0x9AD3, 0xCBE8, 0x9AD4, 0xF377, 0x9AD5, 0xF378, 0x9AD6, 0xF379,	0x9AD7, 0xF37A, 0x9AD8, 0xB8DF, 0x9AD9, 0xF37B, 0x9ADA, 0xF37C,
+	0x9ADB, 0xF37D, 0x9ADC, 0xF37E, 0x9ADD, 0xF380, 0x9ADE, 0xF381,	0x9ADF, 0xF7D4, 0x9AE0, 0xF382, 0x9AE1, 0xF7D5, 0x9AE2, 0xF383,
+	0x9AE3, 0xF384, 0x9AE4, 0xF385, 0x9AE5, 0xF386, 0x9AE6, 0xF7D6,	0x9AE7, 0xF387, 0x9AE8, 0xF388, 0x9AE9, 0xF389, 0x9AEA, 0xF38A,
+	0x9AEB, 0xF7D8, 0x9AEC, 0xF38B, 0x9AED, 0xF7DA, 0x9AEE, 0xF38C,	0x9AEF, 0xF7D7, 0x9AF0, 0xF38D, 0x9AF1, 0xF38E, 0x9AF2, 0xF38F,
+	0x9AF3, 0xF390, 0x9AF4, 0xF391, 0x9AF5, 0xF392, 0x9AF6, 0xF393,	0x9AF7, 0xF394, 0x9AF8, 0xF395, 0x9AF9, 0xF7DB, 0x9AFA, 0xF396,
+	0x9AFB, 0xF7D9, 0x9AFC, 0xF397, 0x9AFD, 0xF398, 0x9AFE, 0xF399,	0x9AFF, 0xF39A, 0x9B00, 0xF39B, 0x9B01, 0xF39C, 0x9B02, 0xF39D,
+	0x9B03, 0xD7D7, 0x9B04, 0xF39E, 0x9B05, 0xF39F, 0x9B06, 0xF3A0,	0x9B07, 0xF440, 0x9B08, 0xF7DC, 0x9B09, 0xF441, 0x9B0A, 0xF442,
+	0x9B0B, 0xF443, 0x9B0C, 0xF444, 0x9B0D, 0xF445, 0x9B0E, 0xF446,	0x9B0F, 0xF7DD, 0x9B10, 0xF447, 0x9B11, 0xF448, 0x9B12, 0xF449,
+	0x9B13, 0xF7DE, 0x9B14, 0xF44A, 0x9B15, 0xF44B, 0x9B16, 0xF44C,	0x9B17, 0xF44D, 0x9B18, 0xF44E, 0x9B19, 0xF44F, 0x9B1A, 0xF450,
+	0x9B1B, 0xF451, 0x9B1C, 0xF452, 0x9B1D, 0xF453, 0x9B1E, 0xF454,	0x9B1F, 0xF7DF, 0x9B20, 0xF455, 0x9B21, 0xF456, 0x9B22, 0xF457,
+	0x9B23, 0xF7E0, 0x9B24, 0xF458, 0x9B25, 0xF459, 0x9B26, 0xF45A,	0x9B27, 0xF45B, 0x9B28, 0xF45C, 0x9B29, 0xF45D, 0x9B2A, 0xF45E,
+	0x9B2B, 0xF45F, 0x9B2C, 0xF460, 0x9B2D, 0xF461, 0x9B2E, 0xF462,	0x9B2F, 0xDBCB, 0x9B30, 0xF463, 0x9B31, 0xF464, 0x9B32, 0xD8AA,
+	0x9B33, 0xF465, 0x9B34, 0xF466, 0x9B35, 0xF467, 0x9B36, 0xF468,	0x9B37, 0xF469, 0x9B38, 0xF46A, 0x9B39, 0xF46B, 0x9B3A, 0xF46C,
+	0x9B3B, 0xE5F7, 0x9B3C, 0xB9ED, 0x9B3D, 0xF46D, 0x9B3E, 0xF46E,	0x9B3F, 0xF46F, 0x9B40, 0xF470, 0x9B41, 0xBFFD, 0x9B42, 0xBBEA,
+	0x9B43, 0xF7C9, 0x9B44, 0xC6C7, 0x9B45, 0xF7C8, 0x9B46, 0xF471,	0x9B47, 0xF7CA, 0x9B48, 0xF7CC, 0x9B49, 0xF7CB, 0x9B4A, 0xF472,
+	0x9B4B, 0xF473, 0x9B4C, 0xF474, 0x9B4D, 0xF7CD, 0x9B4E, 0xF475,	0x9B4F, 0xCEBA, 0x9B50, 0xF476, 0x9B51, 0xF7CE, 0x9B52, 0xF477,
+	0x9B53, 0xF478, 0x9B54, 0xC4A7, 0x9B55, 0xF479, 0x9B56, 0xF47A,	0x9B57, 0xF47B, 0x9B58, 0xF47C, 0x9B59, 0xF47D, 0x9B5A, 0xF47E,
+	0x9B5B, 0xF480, 0x9B5C, 0xF481, 0x9B5D, 0xF482, 0x9B5E, 0xF483,	0x9B5F, 0xF484, 0x9B60, 0xF485, 0x9B61, 0xF486, 0x9B62, 0xF487,
+	0x9B63, 0xF488, 0x9B64, 0xF489, 0x9B65, 0xF48A, 0x9B66, 0xF48B,	0x9B67, 0xF48C, 0x9B68, 0xF48D, 0x9B69, 0xF48E, 0x9B6A, 0xF48F,
+	0x9B6B, 0xF490, 0x9B6C, 0xF491, 0x9B6D, 0xF492, 0x9B6E, 0xF493,	0x9B6F, 0xF494, 0x9B70, 0xF495, 0x9B71, 0xF496, 0x9B72, 0xF497,
+	0x9B73, 0xF498, 0x9B74, 0xF499, 0x9B75, 0xF49A, 0x9B76, 0xF49B,	0x9B77, 0xF49C, 0x9B78, 0xF49D, 0x9B79, 0xF49E, 0x9B7A, 0xF49F,
+	0x9B7B, 0xF4A0, 0x9B7C, 0xF540, 0x9B7D, 0xF541, 0x9B7E, 0xF542,	0x9B7F, 0xF543, 0x9B80, 0xF544, 0x9B81, 0xF545, 0x9B82, 0xF546,
+	0x9B83, 0xF547, 0x9B84, 0xF548, 0x9B85, 0xF549, 0x9B86, 0xF54A,	0x9B87, 0xF54B, 0x9B88, 0xF54C, 0x9B89, 0xF54D, 0x9B8A, 0xF54E,
+	0x9B8B, 0xF54F, 0x9B8C, 0xF550, 0x9B8D, 0xF551, 0x9B8E, 0xF552,	0x9B8F, 0xF553, 0x9B90, 0xF554, 0x9B91, 0xF555, 0x9B92, 0xF556,
+	0x9B93, 0xF557, 0x9B94, 0xF558, 0x9B95, 0xF559, 0x9B96, 0xF55A,	0x9B97, 0xF55B, 0x9B98, 0xF55C, 0x9B99, 0xF55D, 0x9B9A, 0xF55E,
+	0x9B9B, 0xF55F, 0x9B9C, 0xF560, 0x9B9D, 0xF561, 0x9B9E, 0xF562,	0x9B9F, 0xF563, 0x9BA0, 0xF564, 0x9BA1, 0xF565, 0x9BA2, 0xF566,
+	0x9BA3, 0xF567, 0x9BA4, 0xF568, 0x9BA5, 0xF569, 0x9BA6, 0xF56A,	0x9BA7, 0xF56B, 0x9BA8, 0xF56C, 0x9BA9, 0xF56D, 0x9BAA, 0xF56E,
+	0x9BAB, 0xF56F, 0x9BAC, 0xF570, 0x9BAD, 0xF571, 0x9BAE, 0xF572,	0x9BAF, 0xF573, 0x9BB0, 0xF574, 0x9BB1, 0xF575, 0x9BB2, 0xF576,
+	0x9BB3, 0xF577, 0x9BB4, 0xF578, 0x9BB5, 0xF579, 0x9BB6, 0xF57A,	0x9BB7, 0xF57B, 0x9BB8, 0xF57C, 0x9BB9, 0xF57D, 0x9BBA, 0xF57E,
+	0x9BBB, 0xF580, 0x9BBC, 0xF581, 0x9BBD, 0xF582, 0x9BBE, 0xF583,	0x9BBF, 0xF584, 0x9BC0, 0xF585, 0x9BC1, 0xF586, 0x9BC2, 0xF587,
+	0x9BC3, 0xF588, 0x9BC4, 0xF589, 0x9BC5, 0xF58A, 0x9BC6, 0xF58B,	0x9BC7, 0xF58C, 0x9BC8, 0xF58D, 0x9BC9, 0xF58E, 0x9BCA, 0xF58F,
+	0x9BCB, 0xF590, 0x9BCC, 0xF591, 0x9BCD, 0xF592, 0x9BCE, 0xF593,	0x9BCF, 0xF594, 0x9BD0, 0xF595, 0x9BD1, 0xF596, 0x9BD2, 0xF597,
+	0x9BD3, 0xF598, 0x9BD4, 0xF599, 0x9BD5, 0xF59A, 0x9BD6, 0xF59B,	0x9BD7, 0xF59C, 0x9BD8, 0xF59D, 0x9BD9, 0xF59E, 0x9BDA, 0xF59F,
+	0x9BDB, 0xF5A0, 0x9BDC, 0xF640, 0x9BDD, 0xF641, 0x9BDE, 0xF642,	0x9BDF, 0xF643, 0x9BE0, 0xF644, 0x9BE1, 0xF645, 0x9BE2, 0xF646,
+	0x9BE3, 0xF647, 0x9BE4, 0xF648, 0x9BE5, 0xF649, 0x9BE6, 0xF64A,	0x9BE7, 0xF64B, 0x9BE8, 0xF64C, 0x9BE9, 0xF64D, 0x9BEA, 0xF64E,
+	0x9BEB, 0xF64F, 0x9BEC, 0xF650, 0x9BED, 0xF651, 0x9BEE, 0xF652,	0x9BEF, 0xF653, 0x9BF0, 0xF654, 0x9BF1, 0xF655, 0x9BF2, 0xF656,
+	0x9BF3, 0xF657, 0x9BF4, 0xF658, 0x9BF5, 0xF659, 0x9BF6, 0xF65A,	0x9BF7, 0xF65B, 0x9BF8, 0xF65C, 0x9BF9, 0xF65D, 0x9BFA, 0xF65E,
+	0x9BFB, 0xF65F, 0x9BFC, 0xF660, 0x9BFD, 0xF661, 0x9BFE, 0xF662,	0x9BFF, 0xF663, 0x9C00, 0xF664, 0x9C01, 0xF665, 0x9C02, 0xF666,
+	0x9C03, 0xF667, 0x9C04, 0xF668, 0x9C05, 0xF669, 0x9C06, 0xF66A,	0x9C07, 0xF66B, 0x9C08, 0xF66C, 0x9C09, 0xF66D, 0x9C0A, 0xF66E,
+	0x9C0B, 0xF66F, 0x9C0C, 0xF670, 0x9C0D, 0xF671, 0x9C0E, 0xF672,	0x9C0F, 0xF673, 0x9C10, 0xF674, 0x9C11, 0xF675, 0x9C12, 0xF676,
+	0x9C13, 0xF677, 0x9C14, 0xF678, 0x9C15, 0xF679, 0x9C16, 0xF67A,	0x9C17, 0xF67B, 0x9C18, 0xF67C, 0x9C19, 0xF67D, 0x9C1A, 0xF67E,
+	0x9C1B, 0xF680, 0x9C1C, 0xF681, 0x9C1D, 0xF682, 0x9C1E, 0xF683,	0x9C1F, 0xF684, 0x9C20, 0xF685, 0x9C21, 0xF686, 0x9C22, 0xF687,
+	0x9C23, 0xF688, 0x9C24, 0xF689, 0x9C25, 0xF68A, 0x9C26, 0xF68B,	0x9C27, 0xF68C, 0x9C28, 0xF68D, 0x9C29, 0xF68E, 0x9C2A, 0xF68F,
+	0x9C2B, 0xF690, 0x9C2C, 0xF691, 0x9C2D, 0xF692, 0x9C2E, 0xF693,	0x9C2F, 0xF694, 0x9C30, 0xF695, 0x9C31, 0xF696, 0x9C32, 0xF697,
+	0x9C33, 0xF698, 0x9C34, 0xF699, 0x9C35, 0xF69A, 0x9C36, 0xF69B,	0x9C37, 0xF69C, 0x9C38, 0xF69D, 0x9C39, 0xF69E, 0x9C3A, 0xF69F,
+	0x9C3B, 0xF6A0, 0x9C3C, 0xF740, 0x9C3D, 0xF741, 0x9C3E, 0xF742,	0x9C3F, 0xF743, 0x9C40, 0xF744, 0x9C41, 0xF745, 0x9C42, 0xF746,
+	0x9C43, 0xF747, 0x9C44, 0xF748, 0x9C45, 0xF749, 0x9C46, 0xF74A,	0x9C47, 0xF74B, 0x9C48, 0xF74C, 0x9C49, 0xF74D, 0x9C4A, 0xF74E,
+	0x9C4B, 0xF74F, 0x9C4C, 0xF750, 0x9C4D, 0xF751, 0x9C4E, 0xF752,	0x9C4F, 0xF753, 0x9C50, 0xF754, 0x9C51, 0xF755, 0x9C52, 0xF756,
+	0x9C53, 0xF757, 0x9C54, 0xF758, 0x9C55, 0xF759, 0x9C56, 0xF75A,	0x9C57, 0xF75B, 0x9C58, 0xF75C, 0x9C59, 0xF75D, 0x9C5A, 0xF75E,
+	0x9C5B, 0xF75F, 0x9C5C, 0xF760, 0x9C5D, 0xF761, 0x9C5E, 0xF762,	0x9C5F, 0xF763, 0x9C60, 0xF764, 0x9C61, 0xF765, 0x9C62, 0xF766,
+	0x9C63, 0xF767, 0x9C64, 0xF768, 0x9C65, 0xF769, 0x9C66, 0xF76A,	0x9C67, 0xF76B, 0x9C68, 0xF76C, 0x9C69, 0xF76D, 0x9C6A, 0xF76E,
+	0x9C6B, 0xF76F, 0x9C6C, 0xF770, 0x9C6D, 0xF771, 0x9C6E, 0xF772,	0x9C6F, 0xF773, 0x9C70, 0xF774, 0x9C71, 0xF775, 0x9C72, 0xF776,
+	0x9C73, 0xF777, 0x9C74, 0xF778, 0x9C75, 0xF779, 0x9C76, 0xF77A,	0x9C77, 0xF77B, 0x9C78, 0xF77C, 0x9C79, 0xF77D, 0x9C7A, 0xF77E,
+	0x9C7B, 0xF780, 0x9C7C, 0xD3E3, 0x9C7D, 0xF781, 0x9C7E, 0xF782,	0x9C7F, 0xF6CF, 0x9C80, 0xF783, 0x9C81, 0xC2B3, 0x9C82, 0xF6D0,
+	0x9C83, 0xF784, 0x9C84, 0xF785, 0x9C85, 0xF6D1, 0x9C86, 0xF6D2,	0x9C87, 0xF6D3, 0x9C88, 0xF6D4, 0x9C89, 0xF786, 0x9C8A, 0xF787,
+	0x9C8B, 0xF6D6, 0x9C8C, 0xF788, 0x9C8D, 0xB1AB, 0x9C8E, 0xF6D7,	0x9C8F, 0xF789, 0x9C90, 0xF6D8, 0x9C91, 0xF6D9, 0x9C92, 0xF6DA,
+	0x9C93, 0xF78A, 0x9C94, 0xF6DB, 0x9C95, 0xF6DC, 0x9C96, 0xF78B,	0x9C97, 0xF78C, 0x9C98, 0xF78D, 0x9C99, 0xF78E, 0x9C9A, 0xF6DD,
+	0x9C9B, 0xF6DE, 0x9C9C, 0xCFCA, 0x9C9D, 0xF78F, 0x9C9E, 0xF6DF,	0x9C9F, 0xF6E0, 0x9CA0, 0xF6E1, 0x9CA1, 0xF6E2, 0x9CA2, 0xF6E3,
+	0x9CA3, 0xF6E4, 0x9CA4, 0xC0F0, 0x9CA5, 0xF6E5, 0x9CA6, 0xF6E6,	0x9CA7, 0xF6E7, 0x9CA8, 0xF6E8, 0x9CA9, 0xF6E9, 0x9CAA, 0xF790,
+	0x9CAB, 0xF6EA, 0x9CAC, 0xF791, 0x9CAD, 0xF6EB, 0x9CAE, 0xF6EC,	0x9CAF, 0xF792, 0x9CB0, 0xF6ED, 0x9CB1, 0xF6EE, 0x9CB2, 0xF6EF,
+	0x9CB3, 0xF6F0, 0x9CB4, 0xF6F1, 0x9CB5, 0xF6F2, 0x9CB6, 0xF6F3,	0x9CB7, 0xF6F4, 0x9CB8, 0xBEA8, 0x9CB9, 0xF793, 0x9CBA, 0xF6F5,
+	0x9CBB, 0xF6F6, 0x9CBC, 0xF6F7, 0x9CBD, 0xF6F8, 0x9CBE, 0xF794,	0x9CBF, 0xF795, 0x9CC0, 0xF796, 0x9CC1, 0xF797, 0x9CC2, 0xF798,
+	0x9CC3, 0xC8FA, 0x9CC4, 0xF6F9, 0x9CC5, 0xF6FA, 0x9CC6, 0xF6FB,	0x9CC7, 0xF6FC, 0x9CC8, 0xF799, 0x9CC9, 0xF79A, 0x9CCA, 0xF6FD,
+	0x9CCB, 0xF6FE, 0x9CCC, 0xF7A1, 0x9CCD, 0xF7A2, 0x9CCE, 0xF7A3,	0x9CCF, 0xF7A4, 0x9CD0, 0xF7A5, 0x9CD1, 0xF79B, 0x9CD2, 0xF79C,
+	0x9CD3, 0xF7A6, 0x9CD4, 0xF7A7, 0x9CD5, 0xF7A8, 0x9CD6, 0xB1EE,	0x9CD7, 0xF7A9, 0x9CD8, 0xF7AA, 0x9CD9, 0xF7AB, 0x9CDA, 0xF79D,
+	0x9CDB, 0xF79E, 0x9CDC, 0xF7AC, 0x9CDD, 0xF7AD, 0x9CDE, 0xC1DB,	0x9CDF, 0xF7AE, 0x9CE0, 0xF79F, 0x9CE1, 0xF7A0, 0x9CE2, 0xF7AF,
+	0x9CE3, 0xF840, 0x9CE4, 0xF841, 0x9CE5, 0xF842, 0x9CE6, 0xF843,	0x9CE7, 0xF844, 0x9CE8, 0xF845, 0x9CE9, 0xF846, 0x9CEA, 0xF847,
+	0x9CEB, 0xF848, 0x9CEC, 0xF849, 0x9CED, 0xF84A, 0x9CEE, 0xF84B,	0x9CEF, 0xF84C, 0x9CF0, 0xF84D, 0x9CF1, 0xF84E, 0x9CF2, 0xF84F,
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+	0x9F73, 0xFD79, 0x9F74, 0xFD7A, 0x9F75, 0xFD7B, 0x9F76, 0xFD7C,	0x9F77, 0xFD7D, 0x9F78, 0xFD7E, 0x9F79, 0xFD80, 0x9F7A, 0xFD81,
+	0x9F7B, 0xFD82, 0x9F7C, 0xFD83, 0x9F7D, 0xFD84, 0x9F7E, 0xFD85,	0x9F7F, 0xB3DD, 0x9F80, 0xF6B3, 0x9F81, 0xFD86, 0x9F82, 0xFD87,
+	0x9F83, 0xF6B4, 0x9F84, 0xC1E4, 0x9F85, 0xF6B5, 0x9F86, 0xF6B6,	0x9F87, 0xF6B7, 0x9F88, 0xF6B8, 0x9F89, 0xF6B9, 0x9F8A, 0xF6BA,
+	0x9F8B, 0xC8A3, 0x9F8C, 0xF6BB, 0x9F8D, 0xFD88, 0x9F8E, 0xFD89,	0x9F8F, 0xFD8A, 0x9F90, 0xFD8B, 0x9F91, 0xFD8C, 0x9F92, 0xFD8D,
+	0x9F93, 0xFD8E, 0x9F94, 0xFD8F, 0x9F95, 0xFD90, 0x9F96, 0xFD91,	0x9F97, 0xFD92, 0x9F98, 0xFD93, 0x9F99, 0xC1FA, 0x9F9A, 0xB9A8,
+	0x9F9B, 0xEDE8, 0x9F9C, 0xFD94, 0x9F9D, 0xFD95, 0x9F9E, 0xFD96,	0x9F9F, 0xB9EA, 0x9FA0, 0xD9DF, 0x9FA1, 0xFD97, 0x9FA2, 0xFD98,
+	0x9FA3, 0xFD99, 0x9FA4, 0xFD9A, 0x9FA5, 0xFD9B, 0xF92C, 0xFD9C,	0xF979, 0xFD9D, 0xF995, 0xFD9E, 0xF9E7, 0xFD9F, 0xF9F1, 0xFDA0,
+	0xFA0C, 0xFE40, 0xFA0D, 0xFE41, 0xFA0E, 0xFE42, 0xFA0F, 0xFE43,	0xFA11, 0xFE44, 0xFA13, 0xFE45, 0xFA14, 0xFE46, 0xFA18, 0xFE47,
+	0xFA1F, 0xFE48, 0xFA20, 0xFE49, 0xFA21, 0xFE4A, 0xFA23, 0xFE4B,	0xFA24, 0xFE4C, 0xFA27, 0xFE4D, 0xFA28, 0xFE4E, 0xFA29, 0xFE4F,
+	0xFE30, 0xA955, 0xFE31, 0xA6F2, 0xFE33, 0xA6F4, 0xFE34, 0xA6F5,	0xFE35, 0xA6E0, 0xFE36, 0xA6E1, 0xFE37, 0xA6F0, 0xFE38, 0xA6F1,
+	0xFE39, 0xA6E2, 0xFE3A, 0xA6E3, 0xFE3B, 0xA6EE, 0xFE3C, 0xA6EF,	0xFE3D, 0xA6E6, 0xFE3E, 0xA6E7, 0xFE3F, 0xA6E4, 0xFE40, 0xA6E5,
+	0xFE41, 0xA6E8, 0xFE42, 0xA6E9, 0xFE43, 0xA6EA, 0xFE44, 0xA6EB,	0xFE49, 0xA968, 0xFE4A, 0xA969, 0xFE4B, 0xA96A, 0xFE4C, 0xA96B,
+	0xFE4D, 0xA96C, 0xFE4E, 0xA96D, 0xFE4F, 0xA96E, 0xFE50, 0xA96F,	0xFE51, 0xA970, 0xFE52, 0xA971, 0xFE54, 0xA972, 0xFE55, 0xA973,
+	0xFE56, 0xA974, 0xFE57, 0xA975, 0xFE59, 0xA976, 0xFE5A, 0xA977,	0xFE5B, 0xA978, 0xFE5C, 0xA979, 0xFE5D, 0xA97A, 0xFE5E, 0xA97B,
+	0xFE5F, 0xA97C, 0xFE60, 0xA97D, 0xFE61, 0xA97E, 0xFE62, 0xA980,	0xFE63, 0xA981, 0xFE64, 0xA982, 0xFE65, 0xA983, 0xFE66, 0xA984,
+	0xFE68, 0xA985, 0xFE69, 0xA986, 0xFE6A, 0xA987, 0xFE6B, 0xA988,	0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA1E7,
+	0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8,	0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC,
+	0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0,	0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4,
+	0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8,	0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC,
+	0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0,	0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4,
+	0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8,	0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC,
+	0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0,	0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4,
+	0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8,	0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA3DC,
+	0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0,	0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4,
+	0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8,	0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC,
+	0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0,	0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4,
+	0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8,	0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC,
+	0xFF5D, 0xA3FD, 0xFF5E, 0xA1AB, 0xFFE0, 0xA1E9, 0xFFE1, 0xA1EA,	0xFFE2, 0xA956, 0xFFE3, 0xA3FE, 0xFFE4, 0xA957, 0xFFE5, 0xA3A4,
+	0, 0
+};
+
+static const WCHAR oem2uni936[] = {	/* GBK --> Unicode pairs */
+	0x0080, 0x20AC, 0x8140, 0x4E02, 0x8141, 0x4E04, 0x8142, 0x4E05,	0x8143, 0x4E06, 0x8144, 0x4E0F, 0x8145, 0x4E12, 0x8146, 0x4E17,
+	0x8147, 0x4E1F, 0x8148, 0x4E20, 0x8149, 0x4E21, 0x814A, 0x4E23,	0x814B, 0x4E26, 0x814C, 0x4E29, 0x814D, 0x4E2E, 0x814E, 0x4E2F,
+	0x814F, 0x4E31, 0x8150, 0x4E33, 0x8151, 0x4E35, 0x8152, 0x4E37,	0x8153, 0x4E3C, 0x8154, 0x4E40, 0x8155, 0x4E41, 0x8156, 0x4E42,
+	0x8157, 0x4E44, 0x8158, 0x4E46, 0x8159, 0x4E4A, 0x815A, 0x4E51,	0x815B, 0x4E55, 0x815C, 0x4E57, 0x815D, 0x4E5A, 0x815E, 0x4E5B,
+	0x815F, 0x4E62, 0x8160, 0x4E63, 0x8161, 0x4E64, 0x8162, 0x4E65,	0x8163, 0x4E67, 0x8164, 0x4E68, 0x8165, 0x4E6A, 0x8166, 0x4E6B,
+	0x8167, 0x4E6C, 0x8168, 0x4E6D, 0x8169, 0x4E6E, 0x816A, 0x4E6F,	0x816B, 0x4E72, 0x816C, 0x4E74, 0x816D, 0x4E75, 0x816E, 0x4E76,
+	0x816F, 0x4E77, 0x8170, 0x4E78, 0x8171, 0x4E79, 0x8172, 0x4E7A,	0x8173, 0x4E7B, 0x8174, 0x4E7C, 0x8175, 0x4E7D, 0x8176, 0x4E7F,
+	0x8177, 0x4E80, 0x8178, 0x4E81, 0x8179, 0x4E82, 0x817A, 0x4E83,	0x817B, 0x4E84, 0x817C, 0x4E85, 0x817D, 0x4E87, 0x817E, 0x4E8A,
+	0x8180, 0x4E90, 0x8181, 0x4E96, 0x8182, 0x4E97, 0x8183, 0x4E99,	0x8184, 0x4E9C, 0x8185, 0x4E9D, 0x8186, 0x4E9E, 0x8187, 0x4EA3,
+	0x8188, 0x4EAA, 0x8189, 0x4EAF, 0x818A, 0x4EB0, 0x818B, 0x4EB1,	0x818C, 0x4EB4, 0x818D, 0x4EB6, 0x818E, 0x4EB7, 0x818F, 0x4EB8,
+	0x8190, 0x4EB9, 0x8191, 0x4EBC, 0x8192, 0x4EBD, 0x8193, 0x4EBE,	0x8194, 0x4EC8, 0x8195, 0x4ECC, 0x8196, 0x4ECF, 0x8197, 0x4ED0,
+	0x8198, 0x4ED2, 0x8199, 0x4EDA, 0x819A, 0x4EDB, 0x819B, 0x4EDC,	0x819C, 0x4EE0, 0x819D, 0x4EE2, 0x819E, 0x4EE6, 0x819F, 0x4EE7,
+	0x81A0, 0x4EE9, 0x81A1, 0x4EED, 0x81A2, 0x4EEE, 0x81A3, 0x4EEF,	0x81A4, 0x4EF1, 0x81A5, 0x4EF4, 0x81A6, 0x4EF8, 0x81A7, 0x4EF9,
+	0x81A8, 0x4EFA, 0x81A9, 0x4EFC, 0x81AA, 0x4EFE, 0x81AB, 0x4F00,	0x81AC, 0x4F02, 0x81AD, 0x4F03, 0x81AE, 0x4F04, 0x81AF, 0x4F05,
+	0x81B0, 0x4F06, 0x81B1, 0x4F07, 0x81B2, 0x4F08, 0x81B3, 0x4F0B,	0x81B4, 0x4F0C, 0x81B5, 0x4F12, 0x81B6, 0x4F13, 0x81B7, 0x4F14,
+	0x81B8, 0x4F15, 0x81B9, 0x4F16, 0x81BA, 0x4F1C, 0x81BB, 0x4F1D,	0x81BC, 0x4F21, 0x81BD, 0x4F23, 0x81BE, 0x4F28, 0x81BF, 0x4F29,
+	0x81C0, 0x4F2C, 0x81C1, 0x4F2D, 0x81C2, 0x4F2E, 0x81C3, 0x4F31,	0x81C4, 0x4F33, 0x81C5, 0x4F35, 0x81C6, 0x4F37, 0x81C7, 0x4F39,
+	0x81C8, 0x4F3B, 0x81C9, 0x4F3E, 0x81CA, 0x4F3F, 0x81CB, 0x4F40,	0x81CC, 0x4F41, 0x81CD, 0x4F42, 0x81CE, 0x4F44, 0x81CF, 0x4F45,
+	0x81D0, 0x4F47, 0x81D1, 0x4F48, 0x81D2, 0x4F49, 0x81D3, 0x4F4A,	0x81D4, 0x4F4B, 0x81D5, 0x4F4C, 0x81D6, 0x4F52, 0x81D7, 0x4F54,
+	0x81D8, 0x4F56, 0x81D9, 0x4F61, 0x81DA, 0x4F62, 0x81DB, 0x4F66,	0x81DC, 0x4F68, 0x81DD, 0x4F6A, 0x81DE, 0x4F6B, 0x81DF, 0x4F6D,
+	0x81E0, 0x4F6E, 0x81E1, 0x4F71, 0x81E2, 0x4F72, 0x81E3, 0x4F75,	0x81E4, 0x4F77, 0x81E5, 0x4F78, 0x81E6, 0x4F79, 0x81E7, 0x4F7A,
+	0x81E8, 0x4F7D, 0x81E9, 0x4F80, 0x81EA, 0x4F81, 0x81EB, 0x4F82,	0x81EC, 0x4F85, 0x81ED, 0x4F86, 0x81EE, 0x4F87, 0x81EF, 0x4F8A,
+	0x81F0, 0x4F8C, 0x81F1, 0x4F8E, 0x81F2, 0x4F90, 0x81F3, 0x4F92,	0x81F4, 0x4F93, 0x81F5, 0x4F95, 0x81F6, 0x4F96, 0x81F7, 0x4F98,
+	0x81F8, 0x4F99, 0x81F9, 0x4F9A, 0x81FA, 0x4F9C, 0x81FB, 0x4F9E,	0x81FC, 0x4F9F, 0x81FD, 0x4FA1, 0x81FE, 0x4FA2, 0x8240, 0x4FA4,
+	0x8241, 0x4FAB, 0x8242, 0x4FAD, 0x8243, 0x4FB0, 0x8244, 0x4FB1,	0x8245, 0x4FB2, 0x8246, 0x4FB3, 0x8247, 0x4FB4, 0x8248, 0x4FB6,
+	0x8249, 0x4FB7, 0x824A, 0x4FB8, 0x824B, 0x4FB9, 0x824C, 0x4FBA,	0x824D, 0x4FBB, 0x824E, 0x4FBC, 0x824F, 0x4FBD, 0x8250, 0x4FBE,
+	0x8251, 0x4FC0, 0x8252, 0x4FC1, 0x8253, 0x4FC2, 0x8254, 0x4FC6,	0x8255, 0x4FC7, 0x8256, 0x4FC8, 0x8257, 0x4FC9, 0x8258, 0x4FCB,
+	0x8259, 0x4FCC, 0x825A, 0x4FCD, 0x825B, 0x4FD2, 0x825C, 0x4FD3,	0x825D, 0x4FD4, 0x825E, 0x4FD5, 0x825F, 0x4FD6, 0x8260, 0x4FD9,
+	0x8261, 0x4FDB, 0x8262, 0x4FE0, 0x8263, 0x4FE2, 0x8264, 0x4FE4,	0x8265, 0x4FE5, 0x8266, 0x4FE7, 0x8267, 0x4FEB, 0x8268, 0x4FEC,
+	0x8269, 0x4FF0, 0x826A, 0x4FF2, 0x826B, 0x4FF4, 0x826C, 0x4FF5,	0x826D, 0x4FF6, 0x826E, 0x4FF7, 0x826F, 0x4FF9, 0x8270, 0x4FFB,
+	0x8271, 0x4FFC, 0x8272, 0x4FFD, 0x8273, 0x4FFF, 0x8274, 0x5000,	0x8275, 0x5001, 0x8276, 0x5002, 0x8277, 0x5003, 0x8278, 0x5004,
+	0x8279, 0x5005, 0x827A, 0x5006, 0x827B, 0x5007, 0x827C, 0x5008,	0x827D, 0x5009, 0x827E, 0x500A, 0x8280, 0x500B, 0x8281, 0x500E,
+	0x8282, 0x5010, 0x8283, 0x5011, 0x8284, 0x5013, 0x8285, 0x5015,	0x8286, 0x5016, 0x8287, 0x5017, 0x8288, 0x501B, 0x8289, 0x501D,
+	0x828A, 0x501E, 0x828B, 0x5020, 0x828C, 0x5022, 0x828D, 0x5023,	0x828E, 0x5024, 0x828F, 0x5027, 0x8290, 0x502B, 0x8291, 0x502F,
+	0x8292, 0x5030, 0x8293, 0x5031, 0x8294, 0x5032, 0x8295, 0x5033,	0x8296, 0x5034, 0x8297, 0x5035, 0x8298, 0x5036, 0x8299, 0x5037,
+	0x829A, 0x5038, 0x829B, 0x5039, 0x829C, 0x503B, 0x829D, 0x503D,	0x829E, 0x503F, 0x829F, 0x5040, 0x82A0, 0x5041, 0x82A1, 0x5042,
+	0x82A2, 0x5044, 0x82A3, 0x5045, 0x82A4, 0x5046, 0x82A5, 0x5049,	0x82A6, 0x504A, 0x82A7, 0x504B, 0x82A8, 0x504D, 0x82A9, 0x5050,
+	0x82AA, 0x5051, 0x82AB, 0x5052, 0x82AC, 0x5053, 0x82AD, 0x5054,	0x82AE, 0x5056, 0x82AF, 0x5057, 0x82B0, 0x5058, 0x82B1, 0x5059,
+	0x82B2, 0x505B, 0x82B3, 0x505D, 0x82B4, 0x505E, 0x82B5, 0x505F,	0x82B6, 0x5060, 0x82B7, 0x5061, 0x82B8, 0x5062, 0x82B9, 0x5063,
+	0x82BA, 0x5064, 0x82BB, 0x5066, 0x82BC, 0x5067, 0x82BD, 0x5068,	0x82BE, 0x5069, 0x82BF, 0x506A, 0x82C0, 0x506B, 0x82C1, 0x506D,
+	0x82C2, 0x506E, 0x82C3, 0x506F, 0x82C4, 0x5070, 0x82C5, 0x5071,	0x82C6, 0x5072, 0x82C7, 0x5073, 0x82C8, 0x5074, 0x82C9, 0x5075,
+	0x82CA, 0x5078, 0x82CB, 0x5079, 0x82CC, 0x507A, 0x82CD, 0x507C,	0x82CE, 0x507D, 0x82CF, 0x5081, 0x82D0, 0x5082, 0x82D1, 0x5083,
+	0x82D2, 0x5084, 0x82D3, 0x5086, 0x82D4, 0x5087, 0x82D5, 0x5089,	0x82D6, 0x508A, 0x82D7, 0x508B, 0x82D8, 0x508C, 0x82D9, 0x508E,
+	0x82DA, 0x508F, 0x82DB, 0x5090, 0x82DC, 0x5091, 0x82DD, 0x5092,	0x82DE, 0x5093, 0x82DF, 0x5094, 0x82E0, 0x5095, 0x82E1, 0x5096,
+	0x82E2, 0x5097, 0x82E3, 0x5098, 0x82E4, 0x5099, 0x82E5, 0x509A,	0x82E6, 0x509B, 0x82E7, 0x509C, 0x82E8, 0x509D, 0x82E9, 0x509E,
+	0x82EA, 0x509F, 0x82EB, 0x50A0, 0x82EC, 0x50A1, 0x82ED, 0x50A2,	0x82EE, 0x50A4, 0x82EF, 0x50A6, 0x82F0, 0x50AA, 0x82F1, 0x50AB,
+	0x82F2, 0x50AD, 0x82F3, 0x50AE, 0x82F4, 0x50AF, 0x82F5, 0x50B0,	0x82F6, 0x50B1, 0x82F7, 0x50B3, 0x82F8, 0x50B4, 0x82F9, 0x50B5,
+	0x82FA, 0x50B6, 0x82FB, 0x50B7, 0x82FC, 0x50B8, 0x82FD, 0x50B9,	0x82FE, 0x50BC, 0x8340, 0x50BD, 0x8341, 0x50BE, 0x8342, 0x50BF,
+	0x8343, 0x50C0, 0x8344, 0x50C1, 0x8345, 0x50C2, 0x8346, 0x50C3,	0x8347, 0x50C4, 0x8348, 0x50C5, 0x8349, 0x50C6, 0x834A, 0x50C7,
+	0x834B, 0x50C8, 0x834C, 0x50C9, 0x834D, 0x50CA, 0x834E, 0x50CB,	0x834F, 0x50CC, 0x8350, 0x50CD, 0x8351, 0x50CE, 0x8352, 0x50D0,
+	0x8353, 0x50D1, 0x8354, 0x50D2, 0x8355, 0x50D3, 0x8356, 0x50D4,	0x8357, 0x50D5, 0x8358, 0x50D7, 0x8359, 0x50D8, 0x835A, 0x50D9,
+	0x835B, 0x50DB, 0x835C, 0x50DC, 0x835D, 0x50DD, 0x835E, 0x50DE,	0x835F, 0x50DF, 0x8360, 0x50E0, 0x8361, 0x50E1, 0x8362, 0x50E2,
+	0x8363, 0x50E3, 0x8364, 0x50E4, 0x8365, 0x50E5, 0x8366, 0x50E8,	0x8367, 0x50E9, 0x8368, 0x50EA, 0x8369, 0x50EB, 0x836A, 0x50EF,
+	0x836B, 0x50F0, 0x836C, 0x50F1, 0x836D, 0x50F2, 0x836E, 0x50F4,	0x836F, 0x50F6, 0x8370, 0x50F7, 0x8371, 0x50F8, 0x8372, 0x50F9,
+	0x8373, 0x50FA, 0x8374, 0x50FC, 0x8375, 0x50FD, 0x8376, 0x50FE,	0x8377, 0x50FF, 0x8378, 0x5100, 0x8379, 0x5101, 0x837A, 0x5102,
+	0x837B, 0x5103, 0x837C, 0x5104, 0x837D, 0x5105, 0x837E, 0x5108,	0x8380, 0x5109, 0x8381, 0x510A, 0x8382, 0x510C, 0x8383, 0x510D,
+	0x8384, 0x510E, 0x8385, 0x510F, 0x8386, 0x5110, 0x8387, 0x5111,	0x8388, 0x5113, 0x8389, 0x5114, 0x838A, 0x5115, 0x838B, 0x5116,
+	0x838C, 0x5117, 0x838D, 0x5118, 0x838E, 0x5119, 0x838F, 0x511A,	0x8390, 0x511B, 0x8391, 0x511C, 0x8392, 0x511D, 0x8393, 0x511E,
+	0x8394, 0x511F, 0x8395, 0x5120, 0x8396, 0x5122, 0x8397, 0x5123,	0x8398, 0x5124, 0x8399, 0x5125, 0x839A, 0x5126, 0x839B, 0x5127,
+	0x839C, 0x5128, 0x839D, 0x5129, 0x839E, 0x512A, 0x839F, 0x512B,	0x83A0, 0x512C, 0x83A1, 0x512D, 0x83A2, 0x512E, 0x83A3, 0x512F,
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+	0x9F8C, 0x7142, 0x9F8D, 0x7143, 0x9F8E, 0x7144, 0x9F8F, 0x7146,	0x9F90, 0x7147, 0x9F91, 0x7148, 0x9F92, 0x7149, 0x9F93, 0x714B,
+	0x9F94, 0x714D, 0x9F95, 0x714F, 0x9F96, 0x7150, 0x9F97, 0x7151,	0x9F98, 0x7152, 0x9F99, 0x7153, 0x9F9A, 0x7154, 0x9F9B, 0x7155,
+	0x9F9C, 0x7156, 0x9F9D, 0x7157, 0x9F9E, 0x7158, 0x9F9F, 0x7159,	0x9FA0, 0x715A, 0x9FA1, 0x715B, 0x9FA2, 0x715D, 0x9FA3, 0x715F,
+	0x9FA4, 0x7160, 0x9FA5, 0x7161, 0x9FA6, 0x7162, 0x9FA7, 0x7163,	0x9FA8, 0x7165, 0x9FA9, 0x7169, 0x9FAA, 0x716A, 0x9FAB, 0x716B,
+	0x9FAC, 0x716C, 0x9FAD, 0x716D, 0x9FAE, 0x716F, 0x9FAF, 0x7170,	0x9FB0, 0x7171, 0x9FB1, 0x7174, 0x9FB2, 0x7175, 0x9FB3, 0x7176,
+	0x9FB4, 0x7177, 0x9FB5, 0x7179, 0x9FB6, 0x717B, 0x9FB7, 0x717C,	0x9FB8, 0x717E, 0x9FB9, 0x717F, 0x9FBA, 0x7180, 0x9FBB, 0x7181,
+	0x9FBC, 0x7182, 0x9FBD, 0x7183, 0x9FBE, 0x7185, 0x9FBF, 0x7186,	0x9FC0, 0x7187, 0x9FC1, 0x7188, 0x9FC2, 0x7189, 0x9FC3, 0x718B,
+	0x9FC4, 0x718C, 0x9FC5, 0x718D, 0x9FC6, 0x718E, 0x9FC7, 0x7190,	0x9FC8, 0x7191, 0x9FC9, 0x7192, 0x9FCA, 0x7193, 0x9FCB, 0x7195,
+	0x9FCC, 0x7196, 0x9FCD, 0x7197, 0x9FCE, 0x719A, 0x9FCF, 0x719B,	0x9FD0, 0x719C, 0x9FD1, 0x719D, 0x9FD2, 0x719E, 0x9FD3, 0x71A1,
+	0x9FD4, 0x71A2, 0x9FD5, 0x71A3, 0x9FD6, 0x71A4, 0x9FD7, 0x71A5,	0x9FD8, 0x71A6, 0x9FD9, 0x71A7, 0x9FDA, 0x71A9, 0x9FDB, 0x71AA,
+	0x9FDC, 0x71AB, 0x9FDD, 0x71AD, 0x9FDE, 0x71AE, 0x9FDF, 0x71AF,	0x9FE0, 0x71B0, 0x9FE1, 0x71B1, 0x9FE2, 0x71B2, 0x9FE3, 0x71B4,
+	0x9FE4, 0x71B6, 0x9FE5, 0x71B7, 0x9FE6, 0x71B8, 0x9FE7, 0x71BA,	0x9FE8, 0x71BB, 0x9FE9, 0x71BC, 0x9FEA, 0x71BD, 0x9FEB, 0x71BE,
+	0x9FEC, 0x71BF, 0x9FED, 0x71C0, 0x9FEE, 0x71C1, 0x9FEF, 0x71C2,	0x9FF0, 0x71C4, 0x9FF1, 0x71C5, 0x9FF2, 0x71C6, 0x9FF3, 0x71C7,
+	0x9FF4, 0x71C8, 0x9FF5, 0x71C9, 0x9FF6, 0x71CA, 0x9FF7, 0x71CB,	0x9FF8, 0x71CC, 0x9FF9, 0x71CD, 0x9FFA, 0x71CF, 0x9FFB, 0x71D0,
+	0x9FFC, 0x71D1, 0x9FFD, 0x71D2, 0x9FFE, 0x71D3, 0xA040, 0x71D6,	0xA041, 0x71D7, 0xA042, 0x71D8, 0xA043, 0x71D9, 0xA044, 0x71DA,
+	0xA045, 0x71DB, 0xA046, 0x71DC, 0xA047, 0x71DD, 0xA048, 0x71DE,	0xA049, 0x71DF, 0xA04A, 0x71E1, 0xA04B, 0x71E2, 0xA04C, 0x71E3,
+	0xA04D, 0x71E4, 0xA04E, 0x71E6, 0xA04F, 0x71E8, 0xA050, 0x71E9,	0xA051, 0x71EA, 0xA052, 0x71EB, 0xA053, 0x71EC, 0xA054, 0x71ED,
+	0xA055, 0x71EF, 0xA056, 0x71F0, 0xA057, 0x71F1, 0xA058, 0x71F2,	0xA059, 0x71F3, 0xA05A, 0x71F4, 0xA05B, 0x71F5, 0xA05C, 0x71F6,
+	0xA05D, 0x71F7, 0xA05E, 0x71F8, 0xA05F, 0x71FA, 0xA060, 0x71FB,	0xA061, 0x71FC, 0xA062, 0x71FD, 0xA063, 0x71FE, 0xA064, 0x71FF,
+	0xA065, 0x7200, 0xA066, 0x7201, 0xA067, 0x7202, 0xA068, 0x7203,	0xA069, 0x7204, 0xA06A, 0x7205, 0xA06B, 0x7207, 0xA06C, 0x7208,
+	0xA06D, 0x7209, 0xA06E, 0x720A, 0xA06F, 0x720B, 0xA070, 0x720C,	0xA071, 0x720D, 0xA072, 0x720E, 0xA073, 0x720F, 0xA074, 0x7210,
+	0xA075, 0x7211, 0xA076, 0x7212, 0xA077, 0x7213, 0xA078, 0x7214,	0xA079, 0x7215, 0xA07A, 0x7216, 0xA07B, 0x7217, 0xA07C, 0x7218,
+	0xA07D, 0x7219, 0xA07E, 0x721A, 0xA080, 0x721B, 0xA081, 0x721C,	0xA082, 0x721E, 0xA083, 0x721F, 0xA084, 0x7220, 0xA085, 0x7221,
+	0xA086, 0x7222, 0xA087, 0x7223, 0xA088, 0x7224, 0xA089, 0x7225,	0xA08A, 0x7226, 0xA08B, 0x7227, 0xA08C, 0x7229, 0xA08D, 0x722B,
+	0xA08E, 0x722D, 0xA08F, 0x722E, 0xA090, 0x722F, 0xA091, 0x7232,	0xA092, 0x7233, 0xA093, 0x7234, 0xA094, 0x723A, 0xA095, 0x723C,
+	0xA096, 0x723E, 0xA097, 0x7240, 0xA098, 0x7241, 0xA099, 0x7242,	0xA09A, 0x7243, 0xA09B, 0x7244, 0xA09C, 0x7245, 0xA09D, 0x7246,
+	0xA09E, 0x7249, 0xA09F, 0x724A, 0xA0A0, 0x724B, 0xA0A1, 0x724E,	0xA0A2, 0x724F, 0xA0A3, 0x7250, 0xA0A4, 0x7251, 0xA0A5, 0x7253,
+	0xA0A6, 0x7254, 0xA0A7, 0x7255, 0xA0A8, 0x7257, 0xA0A9, 0x7258,	0xA0AA, 0x725A, 0xA0AB, 0x725C, 0xA0AC, 0x725E, 0xA0AD, 0x7260,
+	0xA0AE, 0x7263, 0xA0AF, 0x7264, 0xA0B0, 0x7265, 0xA0B1, 0x7268,	0xA0B2, 0x726A, 0xA0B3, 0x726B, 0xA0B4, 0x726C, 0xA0B5, 0x726D,
+	0xA0B6, 0x7270, 0xA0B7, 0x7271, 0xA0B8, 0x7273, 0xA0B9, 0x7274,	0xA0BA, 0x7276, 0xA0BB, 0x7277, 0xA0BC, 0x7278, 0xA0BD, 0x727B,
+	0xA0BE, 0x727C, 0xA0BF, 0x727D, 0xA0C0, 0x7282, 0xA0C1, 0x7283,	0xA0C2, 0x7285, 0xA0C3, 0x7286, 0xA0C4, 0x7287, 0xA0C5, 0x7288,
+	0xA0C6, 0x7289, 0xA0C7, 0x728C, 0xA0C8, 0x728E, 0xA0C9, 0x7290,	0xA0CA, 0x7291, 0xA0CB, 0x7293, 0xA0CC, 0x7294, 0xA0CD, 0x7295,
+	0xA0CE, 0x7296, 0xA0CF, 0x7297, 0xA0D0, 0x7298, 0xA0D1, 0x7299,	0xA0D2, 0x729A, 0xA0D3, 0x729B, 0xA0D4, 0x729C, 0xA0D5, 0x729D,
+	0xA0D6, 0x729E, 0xA0D7, 0x72A0, 0xA0D8, 0x72A1, 0xA0D9, 0x72A2,	0xA0DA, 0x72A3, 0xA0DB, 0x72A4, 0xA0DC, 0x72A5, 0xA0DD, 0x72A6,
+	0xA0DE, 0x72A7, 0xA0DF, 0x72A8, 0xA0E0, 0x72A9, 0xA0E1, 0x72AA,	0xA0E2, 0x72AB, 0xA0E3, 0x72AE, 0xA0E4, 0x72B1, 0xA0E5, 0x72B2,
+	0xA0E6, 0x72B3, 0xA0E7, 0x72B5, 0xA0E8, 0x72BA, 0xA0E9, 0x72BB,	0xA0EA, 0x72BC, 0xA0EB, 0x72BD, 0xA0EC, 0x72BE, 0xA0ED, 0x72BF,
+	0xA0EE, 0x72C0, 0xA0EF, 0x72C5, 0xA0F0, 0x72C6, 0xA0F1, 0x72C7,	0xA0F2, 0x72C9, 0xA0F3, 0x72CA, 0xA0F4, 0x72CB, 0xA0F5, 0x72CC,
+	0xA0F6, 0x72CF, 0xA0F7, 0x72D1, 0xA0F8, 0x72D3, 0xA0F9, 0x72D4,	0xA0FA, 0x72D5, 0xA0FB, 0x72D6, 0xA0FC, 0x72D8, 0xA0FD, 0x72DA,
+	0xA0FE, 0x72DB, 0xA1A1, 0x3000, 0xA1A2, 0x3001, 0xA1A3, 0x3002,	0xA1A4, 0x00B7, 0xA1A5, 0x02C9, 0xA1A6, 0x02C7, 0xA1A7, 0x00A8,
+	0xA1A8, 0x3003, 0xA1A9, 0x3005, 0xA1AA, 0x2014, 0xA1AB, 0xFF5E,	0xA1AC, 0x2016, 0xA1AD, 0x2026, 0xA1AE, 0x2018, 0xA1AF, 0x2019,
+	0xA1B0, 0x201C, 0xA1B1, 0x201D, 0xA1B2, 0x3014, 0xA1B3, 0x3015,	0xA1B4, 0x3008, 0xA1B5, 0x3009, 0xA1B6, 0x300A, 0xA1B7, 0x300B,
+	0xA1B8, 0x300C, 0xA1B9, 0x300D, 0xA1BA, 0x300E, 0xA1BB, 0x300F,	0xA1BC, 0x3016, 0xA1BD, 0x3017, 0xA1BE, 0x3010, 0xA1BF, 0x3011,
+	0xA1C0, 0x00B1, 0xA1C1, 0x00D7, 0xA1C2, 0x00F7, 0xA1C3, 0x2236,	0xA1C4, 0x2227, 0xA1C5, 0x2228, 0xA1C6, 0x2211, 0xA1C7, 0x220F,
+	0xA1C8, 0x222A, 0xA1C9, 0x2229, 0xA1CA, 0x2208, 0xA1CB, 0x2237,	0xA1CC, 0x221A, 0xA1CD, 0x22A5, 0xA1CE, 0x2225, 0xA1CF, 0x2220,
+	0xA1D0, 0x2312, 0xA1D1, 0x2299, 0xA1D2, 0x222B, 0xA1D3, 0x222E,	0xA1D4, 0x2261, 0xA1D5, 0x224C, 0xA1D6, 0x2248, 0xA1D7, 0x223D,
+	0xA1D8, 0x221D, 0xA1D9, 0x2260, 0xA1DA, 0x226E, 0xA1DB, 0x226F,	0xA1DC, 0x2264, 0xA1DD, 0x2265, 0xA1DE, 0x221E, 0xA1DF, 0x2235,
+	0xA1E0, 0x2234, 0xA1E1, 0x2642, 0xA1E2, 0x2640, 0xA1E3, 0x00B0,	0xA1E4, 0x2032, 0xA1E5, 0x2033, 0xA1E6, 0x2103, 0xA1E7, 0xFF04,
+	0xA1E8, 0x00A4, 0xA1E9, 0xFFE0, 0xA1EA, 0xFFE1, 0xA1EB, 0x2030,	0xA1EC, 0x00A7, 0xA1ED, 0x2116, 0xA1EE, 0x2606, 0xA1EF, 0x2605,
+	0xA1F0, 0x25CB, 0xA1F1, 0x25CF, 0xA1F2, 0x25CE, 0xA1F3, 0x25C7,	0xA1F4, 0x25C6, 0xA1F5, 0x25A1, 0xA1F6, 0x25A0, 0xA1F7, 0x25B3,
+	0xA1F8, 0x25B2, 0xA1F9, 0x203B, 0xA1FA, 0x2192, 0xA1FB, 0x2190,	0xA1FC, 0x2191, 0xA1FD, 0x2193, 0xA1FE, 0x3013, 0xA2A1, 0x2170,
+	0xA2A2, 0x2171, 0xA2A3, 0x2172, 0xA2A4, 0x2173, 0xA2A5, 0x2174,	0xA2A6, 0x2175, 0xA2A7, 0x2176, 0xA2A8, 0x2177, 0xA2A9, 0x2178,
+	0xA2AA, 0x2179, 0xA2B1, 0x2488, 0xA2B2, 0x2489, 0xA2B3, 0x248A,	0xA2B4, 0x248B, 0xA2B5, 0x248C, 0xA2B6, 0x248D, 0xA2B7, 0x248E,
+	0xA2B8, 0x248F, 0xA2B9, 0x2490, 0xA2BA, 0x2491, 0xA2BB, 0x2492,	0xA2BC, 0x2493, 0xA2BD, 0x2494, 0xA2BE, 0x2495, 0xA2BF, 0x2496,
+	0xA2C0, 0x2497, 0xA2C1, 0x2498, 0xA2C2, 0x2499, 0xA2C3, 0x249A,	0xA2C4, 0x249B, 0xA2C5, 0x2474, 0xA2C6, 0x2475, 0xA2C7, 0x2476,
+	0xA2C8, 0x2477, 0xA2C9, 0x2478, 0xA2CA, 0x2479, 0xA2CB, 0x247A,	0xA2CC, 0x247B, 0xA2CD, 0x247C, 0xA2CE, 0x247D, 0xA2CF, 0x247E,
+	0xA2D0, 0x247F, 0xA2D1, 0x2480, 0xA2D2, 0x2481, 0xA2D3, 0x2482,	0xA2D4, 0x2483, 0xA2D5, 0x2484, 0xA2D6, 0x2485, 0xA2D7, 0x2486,
+	0xA2D8, 0x2487, 0xA2D9, 0x2460, 0xA2DA, 0x2461, 0xA2DB, 0x2462,	0xA2DC, 0x2463, 0xA2DD, 0x2464, 0xA2DE, 0x2465, 0xA2DF, 0x2466,
+	0xA2E0, 0x2467, 0xA2E1, 0x2468, 0xA2E2, 0x2469, 0xA2E5, 0x3220,	0xA2E6, 0x3221, 0xA2E7, 0x3222, 0xA2E8, 0x3223, 0xA2E9, 0x3224,
+	0xA2EA, 0x3225, 0xA2EB, 0x3226, 0xA2EC, 0x3227, 0xA2ED, 0x3228,	0xA2EE, 0x3229, 0xA2F1, 0x2160, 0xA2F2, 0x2161, 0xA2F3, 0x2162,
+	0xA2F4, 0x2163, 0xA2F5, 0x2164, 0xA2F6, 0x2165, 0xA2F7, 0x2166,	0xA2F8, 0x2167, 0xA2F9, 0x2168, 0xA2FA, 0x2169, 0xA2FB, 0x216A,
+	0xA2FC, 0x216B, 0xA3A1, 0xFF01, 0xA3A2, 0xFF02, 0xA3A3, 0xFF03,	0xA3A4, 0xFFE5, 0xA3A5, 0xFF05, 0xA3A6, 0xFF06, 0xA3A7, 0xFF07,
+	0xA3A8, 0xFF08, 0xA3A9, 0xFF09, 0xA3AA, 0xFF0A, 0xA3AB, 0xFF0B,	0xA3AC, 0xFF0C, 0xA3AD, 0xFF0D, 0xA3AE, 0xFF0E, 0xA3AF, 0xFF0F,
+	0xA3B0, 0xFF10, 0xA3B1, 0xFF11, 0xA3B2, 0xFF12, 0xA3B3, 0xFF13,	0xA3B4, 0xFF14, 0xA3B5, 0xFF15, 0xA3B6, 0xFF16, 0xA3B7, 0xFF17,
+	0xA3B8, 0xFF18, 0xA3B9, 0xFF19, 0xA3BA, 0xFF1A, 0xA3BB, 0xFF1B,	0xA3BC, 0xFF1C, 0xA3BD, 0xFF1D, 0xA3BE, 0xFF1E, 0xA3BF, 0xFF1F,
+	0xA3C0, 0xFF20, 0xA3C1, 0xFF21, 0xA3C2, 0xFF22, 0xA3C3, 0xFF23,	0xA3C4, 0xFF24, 0xA3C5, 0xFF25, 0xA3C6, 0xFF26, 0xA3C7, 0xFF27,
+	0xA3C8, 0xFF28, 0xA3C9, 0xFF29, 0xA3CA, 0xFF2A, 0xA3CB, 0xFF2B,	0xA3CC, 0xFF2C, 0xA3CD, 0xFF2D, 0xA3CE, 0xFF2E, 0xA3CF, 0xFF2F,
+	0xA3D0, 0xFF30, 0xA3D1, 0xFF31, 0xA3D2, 0xFF32, 0xA3D3, 0xFF33,	0xA3D4, 0xFF34, 0xA3D5, 0xFF35, 0xA3D6, 0xFF36, 0xA3D7, 0xFF37,
+	0xA3D8, 0xFF38, 0xA3D9, 0xFF39, 0xA3DA, 0xFF3A, 0xA3DB, 0xFF3B,	0xA3DC, 0xFF3C, 0xA3DD, 0xFF3D, 0xA3DE, 0xFF3E, 0xA3DF, 0xFF3F,
+	0xA3E0, 0xFF40, 0xA3E1, 0xFF41, 0xA3E2, 0xFF42, 0xA3E3, 0xFF43,	0xA3E4, 0xFF44, 0xA3E5, 0xFF45, 0xA3E6, 0xFF46, 0xA3E7, 0xFF47,
+	0xA3E8, 0xFF48, 0xA3E9, 0xFF49, 0xA3EA, 0xFF4A, 0xA3EB, 0xFF4B,	0xA3EC, 0xFF4C, 0xA3ED, 0xFF4D, 0xA3EE, 0xFF4E, 0xA3EF, 0xFF4F,
+	0xA3F0, 0xFF50, 0xA3F1, 0xFF51, 0xA3F2, 0xFF52, 0xA3F3, 0xFF53,	0xA3F4, 0xFF54, 0xA3F5, 0xFF55, 0xA3F6, 0xFF56, 0xA3F7, 0xFF57,
+	0xA3F8, 0xFF58, 0xA3F9, 0xFF59, 0xA3FA, 0xFF5A, 0xA3FB, 0xFF5B,	0xA3FC, 0xFF5C, 0xA3FD, 0xFF5D, 0xA3FE, 0xFFE3, 0xA4A1, 0x3041,
+	0xA4A2, 0x3042, 0xA4A3, 0x3043, 0xA4A4, 0x3044, 0xA4A5, 0x3045,	0xA4A6, 0x3046, 0xA4A7, 0x3047, 0xA4A8, 0x3048, 0xA4A9, 0x3049,
+	0xA4AA, 0x304A, 0xA4AB, 0x304B, 0xA4AC, 0x304C, 0xA4AD, 0x304D,	0xA4AE, 0x304E, 0xA4AF, 0x304F, 0xA4B0, 0x3050, 0xA4B1, 0x3051,
+	0xA4B2, 0x3052, 0xA4B3, 0x3053, 0xA4B4, 0x3054, 0xA4B5, 0x3055,	0xA4B6, 0x3056, 0xA4B7, 0x3057, 0xA4B8, 0x3058, 0xA4B9, 0x3059,
+	0xA4BA, 0x305A, 0xA4BB, 0x305B, 0xA4BC, 0x305C, 0xA4BD, 0x305D,	0xA4BE, 0x305E, 0xA4BF, 0x305F, 0xA4C0, 0x3060, 0xA4C1, 0x3061,
+	0xA4C2, 0x3062, 0xA4C3, 0x3063, 0xA4C4, 0x3064, 0xA4C5, 0x3065,	0xA4C6, 0x3066, 0xA4C7, 0x3067, 0xA4C8, 0x3068, 0xA4C9, 0x3069,
+	0xA4CA, 0x306A, 0xA4CB, 0x306B, 0xA4CC, 0x306C, 0xA4CD, 0x306D,	0xA4CE, 0x306E, 0xA4CF, 0x306F, 0xA4D0, 0x3070, 0xA4D1, 0x3071,
+	0xA4D2, 0x3072, 0xA4D3, 0x3073, 0xA4D4, 0x3074, 0xA4D5, 0x3075,	0xA4D6, 0x3076, 0xA4D7, 0x3077, 0xA4D8, 0x3078, 0xA4D9, 0x3079,
+	0xA4DA, 0x307A, 0xA4DB, 0x307B, 0xA4DC, 0x307C, 0xA4DD, 0x307D,	0xA4DE, 0x307E, 0xA4DF, 0x307F, 0xA4E0, 0x3080, 0xA4E1, 0x3081,
+	0xA4E2, 0x3082, 0xA4E3, 0x3083, 0xA4E4, 0x3084, 0xA4E5, 0x3085,	0xA4E6, 0x3086, 0xA4E7, 0x3087, 0xA4E8, 0x3088, 0xA4E9, 0x3089,
+	0xA4EA, 0x308A, 0xA4EB, 0x308B, 0xA4EC, 0x308C, 0xA4ED, 0x308D,	0xA4EE, 0x308E, 0xA4EF, 0x308F, 0xA4F0, 0x3090, 0xA4F1, 0x3091,
+	0xA4F2, 0x3092, 0xA4F3, 0x3093, 0xA5A1, 0x30A1, 0xA5A2, 0x30A2,	0xA5A3, 0x30A3, 0xA5A4, 0x30A4, 0xA5A5, 0x30A5, 0xA5A6, 0x30A6,
+	0xA5A7, 0x30A7, 0xA5A8, 0x30A8, 0xA5A9, 0x30A9, 0xA5AA, 0x30AA,	0xA5AB, 0x30AB, 0xA5AC, 0x30AC, 0xA5AD, 0x30AD, 0xA5AE, 0x30AE,
+	0xA5AF, 0x30AF, 0xA5B0, 0x30B0, 0xA5B1, 0x30B1, 0xA5B2, 0x30B2,	0xA5B3, 0x30B3, 0xA5B4, 0x30B4, 0xA5B5, 0x30B5, 0xA5B6, 0x30B6,
+	0xA5B7, 0x30B7, 0xA5B8, 0x30B8, 0xA5B9, 0x30B9, 0xA5BA, 0x30BA,	0xA5BB, 0x30BB, 0xA5BC, 0x30BC, 0xA5BD, 0x30BD, 0xA5BE, 0x30BE,
+	0xA5BF, 0x30BF, 0xA5C0, 0x30C0, 0xA5C1, 0x30C1, 0xA5C2, 0x30C2,	0xA5C3, 0x30C3, 0xA5C4, 0x30C4, 0xA5C5, 0x30C5, 0xA5C6, 0x30C6,
+	0xA5C7, 0x30C7, 0xA5C8, 0x30C8, 0xA5C9, 0x30C9, 0xA5CA, 0x30CA,	0xA5CB, 0x30CB, 0xA5CC, 0x30CC, 0xA5CD, 0x30CD, 0xA5CE, 0x30CE,
+	0xA5CF, 0x30CF, 0xA5D0, 0x30D0, 0xA5D1, 0x30D1, 0xA5D2, 0x30D2,	0xA5D3, 0x30D3, 0xA5D4, 0x30D4, 0xA5D5, 0x30D5, 0xA5D6, 0x30D6,
+	0xA5D7, 0x30D7, 0xA5D8, 0x30D8, 0xA5D9, 0x30D9, 0xA5DA, 0x30DA,	0xA5DB, 0x30DB, 0xA5DC, 0x30DC, 0xA5DD, 0x30DD, 0xA5DE, 0x30DE,
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+	0xA6C1, 0x03B1, 0xA6C2, 0x03B2, 0xA6C3, 0x03B3, 0xA6C4, 0x03B4,	0xA6C5, 0x03B5, 0xA6C6, 0x03B6, 0xA6C7, 0x03B7, 0xA6C8, 0x03B8,
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+	0xA6D1, 0x03C1, 0xA6D2, 0x03C3, 0xA6D3, 0x03C4, 0xA6D4, 0x03C5,	0xA6D5, 0x03C6, 0xA6D6, 0x03C7, 0xA6D7, 0x03C8, 0xA6D8, 0x03C9,
+	0xA6E0, 0xFE35, 0xA6E1, 0xFE36, 0xA6E2, 0xFE39, 0xA6E3, 0xFE3A,	0xA6E4, 0xFE3F, 0xA6E5, 0xFE40, 0xA6E6, 0xFE3D, 0xA6E7, 0xFE3E,
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+	0xA9CB, 0x2527, 0xA9CC, 0x2528, 0xA9CD, 0x2529, 0xA9CE, 0x252A,	0xA9CF, 0x252B, 0xA9D0, 0x252C, 0xA9D1, 0x252D, 0xA9D2, 0x252E,
+	0xA9D3, 0x252F, 0xA9D4, 0x2530, 0xA9D5, 0x2531, 0xA9D6, 0x2532,	0xA9D7, 0x2533, 0xA9D8, 0x2534, 0xA9D9, 0x2535, 0xA9DA, 0x2536,
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+	0xAB63, 0x739E, 0xAB64, 0x73A0, 0xAB65, 0x73A1, 0xAB66, 0x73A3,	0xAB67, 0x73A4, 0xAB68, 0x73A5, 0xAB69, 0x73A6, 0xAB6A, 0x73A7,
+	0xAB6B, 0x73A8, 0xAB6C, 0x73AA, 0xAB6D, 0x73AC, 0xAB6E, 0x73AD,	0xAB6F, 0x73B1, 0xAB70, 0x73B4, 0xAB71, 0x73B5, 0xAB72, 0x73B6,
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+	0xAB7B, 0x73C4, 0xAB7C, 0x73C5, 0xAB7D, 0x73C6, 0xAB7E, 0x73C7,	0xAB80, 0x73CB, 0xAB81, 0x73CC, 0xAB82, 0x73CE, 0xAB83, 0x73D2,
+	0xAB84, 0x73D3, 0xAB85, 0x73D4, 0xAB86, 0x73D5, 0xAB87, 0x73D6,	0xAB88, 0x73D7, 0xAB89, 0x73D8, 0xAB8A, 0x73DA, 0xAB8B, 0x73DB,
+	0xAB8C, 0x73DC, 0xAB8D, 0x73DD, 0xAB8E, 0x73DF, 0xAB8F, 0x73E1,	0xAB90, 0x73E2, 0xAB91, 0x73E3, 0xAB92, 0x73E4, 0xAB93, 0x73E6,
+	0xAB94, 0x73E8, 0xAB95, 0x73EA, 0xAB96, 0x73EB, 0xAB97, 0x73EC,	0xAB98, 0x73EE, 0xAB99, 0x73EF, 0xAB9A, 0x73F0, 0xAB9B, 0x73F1,
+	0xAB9C, 0x73F3, 0xAB9D, 0x73F4, 0xAB9E, 0x73F5, 0xAB9F, 0x73F6,	0xABA0, 0x73F7, 0xAC40, 0x73F8, 0xAC41, 0x73F9, 0xAC42, 0x73FA,
+	0xAC43, 0x73FB, 0xAC44, 0x73FC, 0xAC45, 0x73FD, 0xAC46, 0x73FE,	0xAC47, 0x73FF, 0xAC48, 0x7400, 0xAC49, 0x7401, 0xAC4A, 0x7402,
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+	0xAC5B, 0x741C, 0xAC5C, 0x741D, 0xAC5D, 0x741E, 0xAC5E, 0x741F,	0xAC5F, 0x7420, 0xAC60, 0x7421, 0xAC61, 0x7423, 0xAC62, 0x7424,
+	0xAC63, 0x7427, 0xAC64, 0x7429, 0xAC65, 0x742B, 0xAC66, 0x742D,	0xAC67, 0x742F, 0xAC68, 0x7431, 0xAC69, 0x7432, 0xAC6A, 0x7437,
+	0xAC6B, 0x7438, 0xAC6C, 0x7439, 0xAC6D, 0x743A, 0xAC6E, 0x743B,	0xAC6F, 0x743D, 0xAC70, 0x743E, 0xAC71, 0x743F, 0xAC72, 0x7440,
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+	0xAF9C, 0x763B, 0xAF9D, 0x763D, 0xAF9E, 0x7641, 0xAF9F, 0x7642,	0xAFA0, 0x7644, 0xB040, 0x7645, 0xB041, 0x7646, 0xB042, 0x7647,
+	0xB043, 0x7648, 0xB044, 0x7649, 0xB045, 0x764A, 0xB046, 0x764B,	0xB047, 0x764E, 0xB048, 0x764F, 0xB049, 0x7650, 0xB04A, 0x7651,
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+	0xB073, 0x768A, 0xB074, 0x768C, 0xB075, 0x768D, 0xB076, 0x768F,	0xB077, 0x7690, 0xB078, 0x7692, 0xB079, 0x7694, 0xB07A, 0x7695,
+	0xB07B, 0x7697, 0xB07C, 0x7698, 0xB07D, 0x769A, 0xB07E, 0x769B,	0xB080, 0x769C, 0xB081, 0x769D, 0xB082, 0x769E, 0xB083, 0x769F,
+	0xB084, 0x76A0, 0xB085, 0x76A1, 0xB086, 0x76A2, 0xB087, 0x76A3,	0xB088, 0x76A5, 0xB089, 0x76A6, 0xB08A, 0x76A7, 0xB08B, 0x76A8,
+	0xB08C, 0x76A9, 0xB08D, 0x76AA, 0xB08E, 0x76AB, 0xB08F, 0x76AC,	0xB090, 0x76AD, 0xB091, 0x76AF, 0xB092, 0x76B0, 0xB093, 0x76B3,
+	0xB094, 0x76B5, 0xB095, 0x76B6, 0xB096, 0x76B7, 0xB097, 0x76B8,	0xB098, 0x76B9, 0xB099, 0x76BA, 0xB09A, 0x76BB, 0xB09B, 0x76BC,
+	0xB09C, 0x76BD, 0xB09D, 0x76BE, 0xB09E, 0x76C0, 0xB09F, 0x76C1,	0xB0A0, 0x76C3, 0xB0A1, 0x554A, 0xB0A2, 0x963F, 0xB0A3, 0x57C3,
+	0xB0A4, 0x6328, 0xB0A5, 0x54CE, 0xB0A6, 0x5509, 0xB0A7, 0x54C0,	0xB0A8, 0x7691, 0xB0A9, 0x764C, 0xB0AA, 0x853C, 0xB0AB, 0x77EE,
+	0xB0AC, 0x827E, 0xB0AD, 0x788D, 0xB0AE, 0x7231, 0xB0AF, 0x9698,	0xB0B0, 0x978D, 0xB0B1, 0x6C28, 0xB0B2, 0x5B89, 0xB0B3, 0x4FFA,
+	0xB0B4, 0x6309, 0xB0B5, 0x6697, 0xB0B6, 0x5CB8, 0xB0B7, 0x80FA,	0xB0B8, 0x6848, 0xB0B9, 0x80AE, 0xB0BA, 0x6602, 0xB0BB, 0x76CE,
+	0xB0BC, 0x51F9, 0xB0BD, 0x6556, 0xB0BE, 0x71AC, 0xB0BF, 0x7FF1,	0xB0C0, 0x8884, 0xB0C1, 0x50B2, 0xB0C2, 0x5965, 0xB0C3, 0x61CA,
+	0xB0C4, 0x6FB3, 0xB0C5, 0x82AD, 0xB0C6, 0x634C, 0xB0C7, 0x6252,	0xB0C8, 0x53ED, 0xB0C9, 0x5427, 0xB0CA, 0x7B06, 0xB0CB, 0x516B,
+	0xB0CC, 0x75A4, 0xB0CD, 0x5DF4, 0xB0CE, 0x62D4, 0xB0CF, 0x8DCB,	0xB0D0, 0x9776, 0xB0D1, 0x628A, 0xB0D2, 0x8019, 0xB0D3, 0x575D,
+	0xB0D4, 0x9738, 0xB0D5, 0x7F62, 0xB0D6, 0x7238, 0xB0D7, 0x767D,	0xB0D8, 0x67CF, 0xB0D9, 0x767E, 0xB0DA, 0x6446, 0xB0DB, 0x4F70,
+	0xB0DC, 0x8D25, 0xB0DD, 0x62DC, 0xB0DE, 0x7A17, 0xB0DF, 0x6591,	0xB0E0, 0x73ED, 0xB0E1, 0x642C, 0xB0E2, 0x6273, 0xB0E3, 0x822C,
+	0xB0E4, 0x9881, 0xB0E5, 0x677F, 0xB0E6, 0x7248, 0xB0E7, 0x626E,	0xB0E8, 0x62CC, 0xB0E9, 0x4F34, 0xB0EA, 0x74E3, 0xB0EB, 0x534A,
+	0xB0EC, 0x529E, 0xB0ED, 0x7ECA, 0xB0EE, 0x90A6, 0xB0EF, 0x5E2E,	0xB0F0, 0x6886, 0xB0F1, 0x699C, 0xB0F2, 0x8180, 0xB0F3, 0x7ED1,
+	0xB0F4, 0x68D2, 0xB0F5, 0x78C5, 0xB0F6, 0x868C, 0xB0F7, 0x9551,	0xB0F8, 0x508D, 0xB0F9, 0x8C24, 0xB0FA, 0x82DE, 0xB0FB, 0x80DE,
+	0xB0FC, 0x5305, 0xB0FD, 0x8912, 0xB0FE, 0x5265, 0xB140, 0x76C4,	0xB141, 0x76C7, 0xB142, 0x76C9, 0xB143, 0x76CB, 0xB144, 0x76CC,
+	0xB145, 0x76D3, 0xB146, 0x76D5, 0xB147, 0x76D9, 0xB148, 0x76DA,	0xB149, 0x76DC, 0xB14A, 0x76DD, 0xB14B, 0x76DE, 0xB14C, 0x76E0,
+	0xB14D, 0x76E1, 0xB14E, 0x76E2, 0xB14F, 0x76E3, 0xB150, 0x76E4,	0xB151, 0x76E6, 0xB152, 0x76E7, 0xB153, 0x76E8, 0xB154, 0x76E9,
+	0xB155, 0x76EA, 0xB156, 0x76EB, 0xB157, 0x76EC, 0xB158, 0x76ED,	0xB159, 0x76F0, 0xB15A, 0x76F3, 0xB15B, 0x76F5, 0xB15C, 0x76F6,
+	0xB15D, 0x76F7, 0xB15E, 0x76FA, 0xB15F, 0x76FB, 0xB160, 0x76FD,	0xB161, 0x76FF, 0xB162, 0x7700, 0xB163, 0x7702, 0xB164, 0x7703,
+	0xB165, 0x7705, 0xB166, 0x7706, 0xB167, 0x770A, 0xB168, 0x770C,	0xB169, 0x770E, 0xB16A, 0x770F, 0xB16B, 0x7710, 0xB16C, 0x7711,
+	0xB16D, 0x7712, 0xB16E, 0x7713, 0xB16F, 0x7714, 0xB170, 0x7715,	0xB171, 0x7716, 0xB172, 0x7717, 0xB173, 0x7718, 0xB174, 0x771B,
+	0xB175, 0x771C, 0xB176, 0x771D, 0xB177, 0x771E, 0xB178, 0x7721,	0xB179, 0x7723, 0xB17A, 0x7724, 0xB17B, 0x7725, 0xB17C, 0x7727,
+	0xB17D, 0x772A, 0xB17E, 0x772B, 0xB180, 0x772C, 0xB181, 0x772E,	0xB182, 0x7730, 0xB183, 0x7731, 0xB184, 0x7732, 0xB185, 0x7733,
+	0xB186, 0x7734, 0xB187, 0x7739, 0xB188, 0x773B, 0xB189, 0x773D,	0xB18A, 0x773E, 0xB18B, 0x773F, 0xB18C, 0x7742, 0xB18D, 0x7744,
+	0xB18E, 0x7745, 0xB18F, 0x7746, 0xB190, 0x7748, 0xB191, 0x7749,	0xB192, 0x774A, 0xB193, 0x774B, 0xB194, 0x774C, 0xB195, 0x774D,
+	0xB196, 0x774E, 0xB197, 0x774F, 0xB198, 0x7752, 0xB199, 0x7753,	0xB19A, 0x7754, 0xB19B, 0x7755, 0xB19C, 0x7756, 0xB19D, 0x7757,
+	0xB19E, 0x7758, 0xB19F, 0x7759, 0xB1A0, 0x775C, 0xB1A1, 0x8584,	0xB1A2, 0x96F9, 0xB1A3, 0x4FDD, 0xB1A4, 0x5821, 0xB1A5, 0x9971,
+	0xB1A6, 0x5B9D, 0xB1A7, 0x62B1, 0xB1A8, 0x62A5, 0xB1A9, 0x66B4,	0xB1AA, 0x8C79, 0xB1AB, 0x9C8D, 0xB1AC, 0x7206, 0xB1AD, 0x676F,
+	0xB1AE, 0x7891, 0xB1AF, 0x60B2, 0xB1B0, 0x5351, 0xB1B1, 0x5317,	0xB1B2, 0x8F88, 0xB1B3, 0x80CC, 0xB1B4, 0x8D1D, 0xB1B5, 0x94A1,
+	0xB1B6, 0x500D, 0xB1B7, 0x72C8, 0xB1B8, 0x5907, 0xB1B9, 0x60EB,	0xB1BA, 0x7119, 0xB1BB, 0x88AB, 0xB1BC, 0x5954, 0xB1BD, 0x82EF,
+	0xB1BE, 0x672C, 0xB1BF, 0x7B28, 0xB1C0, 0x5D29, 0xB1C1, 0x7EF7,	0xB1C2, 0x752D, 0xB1C3, 0x6CF5, 0xB1C4, 0x8E66, 0xB1C5, 0x8FF8,
+	0xB1C6, 0x903C, 0xB1C7, 0x9F3B, 0xB1C8, 0x6BD4, 0xB1C9, 0x9119,	0xB1CA, 0x7B14, 0xB1CB, 0x5F7C, 0xB1CC, 0x78A7, 0xB1CD, 0x84D6,
+	0xB1CE, 0x853D, 0xB1CF, 0x6BD5, 0xB1D0, 0x6BD9, 0xB1D1, 0x6BD6,	0xB1D2, 0x5E01, 0xB1D3, 0x5E87, 0xB1D4, 0x75F9, 0xB1D5, 0x95ED,
+	0xB1D6, 0x655D, 0xB1D7, 0x5F0A, 0xB1D8, 0x5FC5, 0xB1D9, 0x8F9F,	0xB1DA, 0x58C1, 0xB1DB, 0x81C2, 0xB1DC, 0x907F, 0xB1DD, 0x965B,
+	0xB1DE, 0x97AD, 0xB1DF, 0x8FB9, 0xB1E0, 0x7F16, 0xB1E1, 0x8D2C,	0xB1E2, 0x6241, 0xB1E3, 0x4FBF, 0xB1E4, 0x53D8, 0xB1E5, 0x535E,
+	0xB1E6, 0x8FA8, 0xB1E7, 0x8FA9, 0xB1E8, 0x8FAB, 0xB1E9, 0x904D,	0xB1EA, 0x6807, 0xB1EB, 0x5F6A, 0xB1EC, 0x8198, 0xB1ED, 0x8868,
+	0xB1EE, 0x9CD6, 0xB1EF, 0x618B, 0xB1F0, 0x522B, 0xB1F1, 0x762A,	0xB1F2, 0x5F6C, 0xB1F3, 0x658C, 0xB1F4, 0x6FD2, 0xB1F5, 0x6EE8,
+	0xB1F6, 0x5BBE, 0xB1F7, 0x6448, 0xB1F8, 0x5175, 0xB1F9, 0x51B0,	0xB1FA, 0x67C4, 0xB1FB, 0x4E19, 0xB1FC, 0x79C9, 0xB1FD, 0x997C,
+	0xB1FE, 0x70B3, 0xB240, 0x775D, 0xB241, 0x775E, 0xB242, 0x775F,	0xB243, 0x7760, 0xB244, 0x7764, 0xB245, 0x7767, 0xB246, 0x7769,
+	0xB247, 0x776A, 0xB248, 0x776D, 0xB249, 0x776E, 0xB24A, 0x776F,	0xB24B, 0x7770, 0xB24C, 0x7771, 0xB24D, 0x7772, 0xB24E, 0x7773,
+	0xB24F, 0x7774, 0xB250, 0x7775, 0xB251, 0x7776, 0xB252, 0x7777,	0xB253, 0x7778, 0xB254, 0x777A, 0xB255, 0x777B, 0xB256, 0x777C,
+	0xB257, 0x7781, 0xB258, 0x7782, 0xB259, 0x7783, 0xB25A, 0x7786,	0xB25B, 0x7787, 0xB25C, 0x7788, 0xB25D, 0x7789, 0xB25E, 0x778A,
+	0xB25F, 0x778B, 0xB260, 0x778F, 0xB261, 0x7790, 0xB262, 0x7793,	0xB263, 0x7794, 0xB264, 0x7795, 0xB265, 0x7796, 0xB266, 0x7797,
+	0xB267, 0x7798, 0xB268, 0x7799, 0xB269, 0x779A, 0xB26A, 0x779B,	0xB26B, 0x779C, 0xB26C, 0x779D, 0xB26D, 0x779E, 0xB26E, 0x77A1,
+	0xB26F, 0x77A3, 0xB270, 0x77A4, 0xB271, 0x77A6, 0xB272, 0x77A8,	0xB273, 0x77AB, 0xB274, 0x77AD, 0xB275, 0x77AE, 0xB276, 0x77AF,
+	0xB277, 0x77B1, 0xB278, 0x77B2, 0xB279, 0x77B4, 0xB27A, 0x77B6,	0xB27B, 0x77B7, 0xB27C, 0x77B8, 0xB27D, 0x77B9, 0xB27E, 0x77BA,
+	0xB280, 0x77BC, 0xB281, 0x77BE, 0xB282, 0x77C0, 0xB283, 0x77C1,	0xB284, 0x77C2, 0xB285, 0x77C3, 0xB286, 0x77C4, 0xB287, 0x77C5,
+	0xB288, 0x77C6, 0xB289, 0x77C7, 0xB28A, 0x77C8, 0xB28B, 0x77C9,	0xB28C, 0x77CA, 0xB28D, 0x77CB, 0xB28E, 0x77CC, 0xB28F, 0x77CE,
+	0xB290, 0x77CF, 0xB291, 0x77D0, 0xB292, 0x77D1, 0xB293, 0x77D2,	0xB294, 0x77D3, 0xB295, 0x77D4, 0xB296, 0x77D5, 0xB297, 0x77D6,
+	0xB298, 0x77D8, 0xB299, 0x77D9, 0xB29A, 0x77DA, 0xB29B, 0x77DD,	0xB29C, 0x77DE, 0xB29D, 0x77DF, 0xB29E, 0x77E0, 0xB29F, 0x77E1,
+	0xB2A0, 0x77E4, 0xB2A1, 0x75C5, 0xB2A2, 0x5E76, 0xB2A3, 0x73BB,	0xB2A4, 0x83E0, 0xB2A5, 0x64AD, 0xB2A6, 0x62E8, 0xB2A7, 0x94B5,
+	0xB2A8, 0x6CE2, 0xB2A9, 0x535A, 0xB2AA, 0x52C3, 0xB2AB, 0x640F,	0xB2AC, 0x94C2, 0xB2AD, 0x7B94, 0xB2AE, 0x4F2F, 0xB2AF, 0x5E1B,
+	0xB2B0, 0x8236, 0xB2B1, 0x8116, 0xB2B2, 0x818A, 0xB2B3, 0x6E24,	0xB2B4, 0x6CCA, 0xB2B5, 0x9A73, 0xB2B6, 0x6355, 0xB2B7, 0x535C,
+	0xB2B8, 0x54FA, 0xB2B9, 0x8865, 0xB2BA, 0x57E0, 0xB2BB, 0x4E0D,	0xB2BC, 0x5E03, 0xB2BD, 0x6B65, 0xB2BE, 0x7C3F, 0xB2BF, 0x90E8,
+	0xB2C0, 0x6016, 0xB2C1, 0x64E6, 0xB2C2, 0x731C, 0xB2C3, 0x88C1,	0xB2C4, 0x6750, 0xB2C5, 0x624D, 0xB2C6, 0x8D22, 0xB2C7, 0x776C,
+	0xB2C8, 0x8E29, 0xB2C9, 0x91C7, 0xB2CA, 0x5F69, 0xB2CB, 0x83DC,	0xB2CC, 0x8521, 0xB2CD, 0x9910, 0xB2CE, 0x53C2, 0xB2CF, 0x8695,
+	0xB2D0, 0x6B8B, 0xB2D1, 0x60ED, 0xB2D2, 0x60E8, 0xB2D3, 0x707F,	0xB2D4, 0x82CD, 0xB2D5, 0x8231, 0xB2D6, 0x4ED3, 0xB2D7, 0x6CA7,
+	0xB2D8, 0x85CF, 0xB2D9, 0x64CD, 0xB2DA, 0x7CD9, 0xB2DB, 0x69FD,	0xB2DC, 0x66F9, 0xB2DD, 0x8349, 0xB2DE, 0x5395, 0xB2DF, 0x7B56,
+	0xB2E0, 0x4FA7, 0xB2E1, 0x518C, 0xB2E2, 0x6D4B, 0xB2E3, 0x5C42,	0xB2E4, 0x8E6D, 0xB2E5, 0x63D2, 0xB2E6, 0x53C9, 0xB2E7, 0x832C,
+	0xB2E8, 0x8336, 0xB2E9, 0x67E5, 0xB2EA, 0x78B4, 0xB2EB, 0x643D,	0xB2EC, 0x5BDF, 0xB2ED, 0x5C94, 0xB2EE, 0x5DEE, 0xB2EF, 0x8BE7,
+	0xB2F0, 0x62C6, 0xB2F1, 0x67F4, 0xB2F2, 0x8C7A, 0xB2F3, 0x6400,	0xB2F4, 0x63BA, 0xB2F5, 0x8749, 0xB2F6, 0x998B, 0xB2F7, 0x8C17,
+	0xB2F8, 0x7F20, 0xB2F9, 0x94F2, 0xB2FA, 0x4EA7, 0xB2FB, 0x9610,	0xB2FC, 0x98A4, 0xB2FD, 0x660C, 0xB2FE, 0x7316, 0xB340, 0x77E6,
+	0xB341, 0x77E8, 0xB342, 0x77EA, 0xB343, 0x77EF, 0xB344, 0x77F0,	0xB345, 0x77F1, 0xB346, 0x77F2, 0xB347, 0x77F4, 0xB348, 0x77F5,
+	0xB349, 0x77F7, 0xB34A, 0x77F9, 0xB34B, 0x77FA, 0xB34C, 0x77FB,	0xB34D, 0x77FC, 0xB34E, 0x7803, 0xB34F, 0x7804, 0xB350, 0x7805,
+	0xB351, 0x7806, 0xB352, 0x7807, 0xB353, 0x7808, 0xB354, 0x780A,	0xB355, 0x780B, 0xB356, 0x780E, 0xB357, 0x780F, 0xB358, 0x7810,
+	0xB359, 0x7813, 0xB35A, 0x7815, 0xB35B, 0x7819, 0xB35C, 0x781B,	0xB35D, 0x781E, 0xB35E, 0x7820, 0xB35F, 0x7821, 0xB360, 0x7822,
+	0xB361, 0x7824, 0xB362, 0x7828, 0xB363, 0x782A, 0xB364, 0x782B,	0xB365, 0x782E, 0xB366, 0x782F, 0xB367, 0x7831, 0xB368, 0x7832,
+	0xB369, 0x7833, 0xB36A, 0x7835, 0xB36B, 0x7836, 0xB36C, 0x783D,	0xB36D, 0x783F, 0xB36E, 0x7841, 0xB36F, 0x7842, 0xB370, 0x7843,
+	0xB371, 0x7844, 0xB372, 0x7846, 0xB373, 0x7848, 0xB374, 0x7849,	0xB375, 0x784A, 0xB376, 0x784B, 0xB377, 0x784D, 0xB378, 0x784F,
+	0xB379, 0x7851, 0xB37A, 0x7853, 0xB37B, 0x7854, 0xB37C, 0x7858,	0xB37D, 0x7859, 0xB37E, 0x785A, 0xB380, 0x785B, 0xB381, 0x785C,
+	0xB382, 0x785E, 0xB383, 0x785F, 0xB384, 0x7860, 0xB385, 0x7861,	0xB386, 0x7862, 0xB387, 0x7863, 0xB388, 0x7864, 0xB389, 0x7865,
+	0xB38A, 0x7866, 0xB38B, 0x7867, 0xB38C, 0x7868, 0xB38D, 0x7869,	0xB38E, 0x786F, 0xB38F, 0x7870, 0xB390, 0x7871, 0xB391, 0x7872,
+	0xB392, 0x7873, 0xB393, 0x7874, 0xB394, 0x7875, 0xB395, 0x7876,	0xB396, 0x7878, 0xB397, 0x7879, 0xB398, 0x787A, 0xB399, 0x787B,
+	0xB39A, 0x787D, 0xB39B, 0x787E, 0xB39C, 0x787F, 0xB39D, 0x7880,	0xB39E, 0x7881, 0xB39F, 0x7882, 0xB3A0, 0x7883, 0xB3A1, 0x573A,
+	0xB3A2, 0x5C1D, 0xB3A3, 0x5E38, 0xB3A4, 0x957F, 0xB3A5, 0x507F,	0xB3A6, 0x80A0, 0xB3A7, 0x5382, 0xB3A8, 0x655E, 0xB3A9, 0x7545,
+	0xB3AA, 0x5531, 0xB3AB, 0x5021, 0xB3AC, 0x8D85, 0xB3AD, 0x6284,	0xB3AE, 0x949E, 0xB3AF, 0x671D, 0xB3B0, 0x5632, 0xB3B1, 0x6F6E,
+	0xB3B2, 0x5DE2, 0xB3B3, 0x5435, 0xB3B4, 0x7092, 0xB3B5, 0x8F66,	0xB3B6, 0x626F, 0xB3B7, 0x64A4, 0xB3B8, 0x63A3, 0xB3B9, 0x5F7B,
+	0xB3BA, 0x6F88, 0xB3BB, 0x90F4, 0xB3BC, 0x81E3, 0xB3BD, 0x8FB0,	0xB3BE, 0x5C18, 0xB3BF, 0x6668, 0xB3C0, 0x5FF1, 0xB3C1, 0x6C89,
+	0xB3C2, 0x9648, 0xB3C3, 0x8D81, 0xB3C4, 0x886C, 0xB3C5, 0x6491,	0xB3C6, 0x79F0, 0xB3C7, 0x57CE, 0xB3C8, 0x6A59, 0xB3C9, 0x6210,
+	0xB3CA, 0x5448, 0xB3CB, 0x4E58, 0xB3CC, 0x7A0B, 0xB3CD, 0x60E9,	0xB3CE, 0x6F84, 0xB3CF, 0x8BDA, 0xB3D0, 0x627F, 0xB3D1, 0x901E,
+	0xB3D2, 0x9A8B, 0xB3D3, 0x79E4, 0xB3D4, 0x5403, 0xB3D5, 0x75F4,	0xB3D6, 0x6301, 0xB3D7, 0x5319, 0xB3D8, 0x6C60, 0xB3D9, 0x8FDF,
+	0xB3DA, 0x5F1B, 0xB3DB, 0x9A70, 0xB3DC, 0x803B, 0xB3DD, 0x9F7F,	0xB3DE, 0x4F88, 0xB3DF, 0x5C3A, 0xB3E0, 0x8D64, 0xB3E1, 0x7FC5,
+	0xB3E2, 0x65A5, 0xB3E3, 0x70BD, 0xB3E4, 0x5145, 0xB3E5, 0x51B2,	0xB3E6, 0x866B, 0xB3E7, 0x5D07, 0xB3E8, 0x5BA0, 0xB3E9, 0x62BD,
+	0xB3EA, 0x916C, 0xB3EB, 0x7574, 0xB3EC, 0x8E0C, 0xB3ED, 0x7A20,	0xB3EE, 0x6101, 0xB3EF, 0x7B79, 0xB3F0, 0x4EC7, 0xB3F1, 0x7EF8,
+	0xB3F2, 0x7785, 0xB3F3, 0x4E11, 0xB3F4, 0x81ED, 0xB3F5, 0x521D,	0xB3F6, 0x51FA, 0xB3F7, 0x6A71, 0xB3F8, 0x53A8, 0xB3F9, 0x8E87,
+	0xB3FA, 0x9504, 0xB3FB, 0x96CF, 0xB3FC, 0x6EC1, 0xB3FD, 0x9664,	0xB3FE, 0x695A, 0xB440, 0x7884, 0xB441, 0x7885, 0xB442, 0x7886,
+	0xB443, 0x7888, 0xB444, 0x788A, 0xB445, 0x788B, 0xB446, 0x788F,	0xB447, 0x7890, 0xB448, 0x7892, 0xB449, 0x7894, 0xB44A, 0x7895,
+	0xB44B, 0x7896, 0xB44C, 0x7899, 0xB44D, 0x789D, 0xB44E, 0x789E,	0xB44F, 0x78A0, 0xB450, 0x78A2, 0xB451, 0x78A4, 0xB452, 0x78A6,
+	0xB453, 0x78A8, 0xB454, 0x78A9, 0xB455, 0x78AA, 0xB456, 0x78AB,	0xB457, 0x78AC, 0xB458, 0x78AD, 0xB459, 0x78AE, 0xB45A, 0x78AF,
+	0xB45B, 0x78B5, 0xB45C, 0x78B6, 0xB45D, 0x78B7, 0xB45E, 0x78B8,	0xB45F, 0x78BA, 0xB460, 0x78BB, 0xB461, 0x78BC, 0xB462, 0x78BD,
+	0xB463, 0x78BF, 0xB464, 0x78C0, 0xB465, 0x78C2, 0xB466, 0x78C3,	0xB467, 0x78C4, 0xB468, 0x78C6, 0xB469, 0x78C7, 0xB46A, 0x78C8,
+	0xB46B, 0x78CC, 0xB46C, 0x78CD, 0xB46D, 0x78CE, 0xB46E, 0x78CF,	0xB46F, 0x78D1, 0xB470, 0x78D2, 0xB471, 0x78D3, 0xB472, 0x78D6,
+	0xB473, 0x78D7, 0xB474, 0x78D8, 0xB475, 0x78DA, 0xB476, 0x78DB,	0xB477, 0x78DC, 0xB478, 0x78DD, 0xB479, 0x78DE, 0xB47A, 0x78DF,
+	0xB47B, 0x78E0, 0xB47C, 0x78E1, 0xB47D, 0x78E2, 0xB47E, 0x78E3,	0xB480, 0x78E4, 0xB481, 0x78E5, 0xB482, 0x78E6, 0xB483, 0x78E7,
+	0xB484, 0x78E9, 0xB485, 0x78EA, 0xB486, 0x78EB, 0xB487, 0x78ED,	0xB488, 0x78EE, 0xB489, 0x78EF, 0xB48A, 0x78F0, 0xB48B, 0x78F1,
+	0xB48C, 0x78F3, 0xB48D, 0x78F5, 0xB48E, 0x78F6, 0xB48F, 0x78F8,	0xB490, 0x78F9, 0xB491, 0x78FB, 0xB492, 0x78FC, 0xB493, 0x78FD,
+	0xB494, 0x78FE, 0xB495, 0x78FF, 0xB496, 0x7900, 0xB497, 0x7902,	0xB498, 0x7903, 0xB499, 0x7904, 0xB49A, 0x7906, 0xB49B, 0x7907,
+	0xB49C, 0x7908, 0xB49D, 0x7909, 0xB49E, 0x790A, 0xB49F, 0x790B,	0xB4A0, 0x790C, 0xB4A1, 0x7840, 0xB4A2, 0x50A8, 0xB4A3, 0x77D7,
+	0xB4A4, 0x6410, 0xB4A5, 0x89E6, 0xB4A6, 0x5904, 0xB4A7, 0x63E3,	0xB4A8, 0x5DDD, 0xB4A9, 0x7A7F, 0xB4AA, 0x693D, 0xB4AB, 0x4F20,
+	0xB4AC, 0x8239, 0xB4AD, 0x5598, 0xB4AE, 0x4E32, 0xB4AF, 0x75AE,	0xB4B0, 0x7A97, 0xB4B1, 0x5E62, 0xB4B2, 0x5E8A, 0xB4B3, 0x95EF,
+	0xB4B4, 0x521B, 0xB4B5, 0x5439, 0xB4B6, 0x708A, 0xB4B7, 0x6376,	0xB4B8, 0x9524, 0xB4B9, 0x5782, 0xB4BA, 0x6625, 0xB4BB, 0x693F,
+	0xB4BC, 0x9187, 0xB4BD, 0x5507, 0xB4BE, 0x6DF3, 0xB4BF, 0x7EAF,	0xB4C0, 0x8822, 0xB4C1, 0x6233, 0xB4C2, 0x7EF0, 0xB4C3, 0x75B5,
+	0xB4C4, 0x8328, 0xB4C5, 0x78C1, 0xB4C6, 0x96CC, 0xB4C7, 0x8F9E,	0xB4C8, 0x6148, 0xB4C9, 0x74F7, 0xB4CA, 0x8BCD, 0xB4CB, 0x6B64,
+	0xB4CC, 0x523A, 0xB4CD, 0x8D50, 0xB4CE, 0x6B21, 0xB4CF, 0x806A,	0xB4D0, 0x8471, 0xB4D1, 0x56F1, 0xB4D2, 0x5306, 0xB4D3, 0x4ECE,
+	0xB4D4, 0x4E1B, 0xB4D5, 0x51D1, 0xB4D6, 0x7C97, 0xB4D7, 0x918B,	0xB4D8, 0x7C07, 0xB4D9, 0x4FC3, 0xB4DA, 0x8E7F, 0xB4DB, 0x7BE1,
+	0xB4DC, 0x7A9C, 0xB4DD, 0x6467, 0xB4DE, 0x5D14, 0xB4DF, 0x50AC,	0xB4E0, 0x8106, 0xB4E1, 0x7601, 0xB4E2, 0x7CB9, 0xB4E3, 0x6DEC,
+	0xB4E4, 0x7FE0, 0xB4E5, 0x6751, 0xB4E6, 0x5B58, 0xB4E7, 0x5BF8,	0xB4E8, 0x78CB, 0xB4E9, 0x64AE, 0xB4EA, 0x6413, 0xB4EB, 0x63AA,
+	0xB4EC, 0x632B, 0xB4ED, 0x9519, 0xB4EE, 0x642D, 0xB4EF, 0x8FBE,	0xB4F0, 0x7B54, 0xB4F1, 0x7629, 0xB4F2, 0x6253, 0xB4F3, 0x5927,
+	0xB4F4, 0x5446, 0xB4F5, 0x6B79, 0xB4F6, 0x50A3, 0xB4F7, 0x6234,	0xB4F8, 0x5E26, 0xB4F9, 0x6B86, 0xB4FA, 0x4EE3, 0xB4FB, 0x8D37,
+	0xB4FC, 0x888B, 0xB4FD, 0x5F85, 0xB4FE, 0x902E, 0xB540, 0x790D,	0xB541, 0x790E, 0xB542, 0x790F, 0xB543, 0x7910, 0xB544, 0x7911,
+	0xB545, 0x7912, 0xB546, 0x7914, 0xB547, 0x7915, 0xB548, 0x7916,	0xB549, 0x7917, 0xB54A, 0x7918, 0xB54B, 0x7919, 0xB54C, 0x791A,
+	0xB54D, 0x791B, 0xB54E, 0x791C, 0xB54F, 0x791D, 0xB550, 0x791F,	0xB551, 0x7920, 0xB552, 0x7921, 0xB553, 0x7922, 0xB554, 0x7923,
+	0xB555, 0x7925, 0xB556, 0x7926, 0xB557, 0x7927, 0xB558, 0x7928,	0xB559, 0x7929, 0xB55A, 0x792A, 0xB55B, 0x792B, 0xB55C, 0x792C,
+	0xB55D, 0x792D, 0xB55E, 0x792E, 0xB55F, 0x792F, 0xB560, 0x7930,	0xB561, 0x7931, 0xB562, 0x7932, 0xB563, 0x7933, 0xB564, 0x7935,
+	0xB565, 0x7936, 0xB566, 0x7937, 0xB567, 0x7938, 0xB568, 0x7939,	0xB569, 0x793D, 0xB56A, 0x793F, 0xB56B, 0x7942, 0xB56C, 0x7943,
+	0xB56D, 0x7944, 0xB56E, 0x7945, 0xB56F, 0x7947, 0xB570, 0x794A,	0xB571, 0x794B, 0xB572, 0x794C, 0xB573, 0x794D, 0xB574, 0x794E,
+	0xB575, 0x794F, 0xB576, 0x7950, 0xB577, 0x7951, 0xB578, 0x7952,	0xB579, 0x7954, 0xB57A, 0x7955, 0xB57B, 0x7958, 0xB57C, 0x7959,
+	0xB57D, 0x7961, 0xB57E, 0x7963, 0xB580, 0x7964, 0xB581, 0x7966,	0xB582, 0x7969, 0xB583, 0x796A, 0xB584, 0x796B, 0xB585, 0x796C,
+	0xB586, 0x796E, 0xB587, 0x7970, 0xB588, 0x7971, 0xB589, 0x7972,	0xB58A, 0x7973, 0xB58B, 0x7974, 0xB58C, 0x7975, 0xB58D, 0x7976,
+	0xB58E, 0x7979, 0xB58F, 0x797B, 0xB590, 0x797C, 0xB591, 0x797D,	0xB592, 0x797E, 0xB593, 0x797F, 0xB594, 0x7982, 0xB595, 0x7983,
+	0xB596, 0x7986, 0xB597, 0x7987, 0xB598, 0x7988, 0xB599, 0x7989,	0xB59A, 0x798B, 0xB59B, 0x798C, 0xB59C, 0x798D, 0xB59D, 0x798E,
+	0xB59E, 0x7990, 0xB59F, 0x7991, 0xB5A0, 0x7992, 0xB5A1, 0x6020,	0xB5A2, 0x803D, 0xB5A3, 0x62C5, 0xB5A4, 0x4E39, 0xB5A5, 0x5355,
+	0xB5A6, 0x90F8, 0xB5A7, 0x63B8, 0xB5A8, 0x80C6, 0xB5A9, 0x65E6,	0xB5AA, 0x6C2E, 0xB5AB, 0x4F46, 0xB5AC, 0x60EE, 0xB5AD, 0x6DE1,
+	0xB5AE, 0x8BDE, 0xB5AF, 0x5F39, 0xB5B0, 0x86CB, 0xB5B1, 0x5F53,	0xB5B2, 0x6321, 0xB5B3, 0x515A, 0xB5B4, 0x8361, 0xB5B5, 0x6863,
+	0xB5B6, 0x5200, 0xB5B7, 0x6363, 0xB5B8, 0x8E48, 0xB5B9, 0x5012,	0xB5BA, 0x5C9B, 0xB5BB, 0x7977, 0xB5BC, 0x5BFC, 0xB5BD, 0x5230,
+	0xB5BE, 0x7A3B, 0xB5BF, 0x60BC, 0xB5C0, 0x9053, 0xB5C1, 0x76D7,	0xB5C2, 0x5FB7, 0xB5C3, 0x5F97, 0xB5C4, 0x7684, 0xB5C5, 0x8E6C,
+	0xB5C6, 0x706F, 0xB5C7, 0x767B, 0xB5C8, 0x7B49, 0xB5C9, 0x77AA,	0xB5CA, 0x51F3, 0xB5CB, 0x9093, 0xB5CC, 0x5824, 0xB5CD, 0x4F4E,
+	0xB5CE, 0x6EF4, 0xB5CF, 0x8FEA, 0xB5D0, 0x654C, 0xB5D1, 0x7B1B,	0xB5D2, 0x72C4, 0xB5D3, 0x6DA4, 0xB5D4, 0x7FDF, 0xB5D5, 0x5AE1,
+	0xB5D6, 0x62B5, 0xB5D7, 0x5E95, 0xB5D8, 0x5730, 0xB5D9, 0x8482,	0xB5DA, 0x7B2C, 0xB5DB, 0x5E1D, 0xB5DC, 0x5F1F, 0xB5DD, 0x9012,
+	0xB5DE, 0x7F14, 0xB5DF, 0x98A0, 0xB5E0, 0x6382, 0xB5E1, 0x6EC7,	0xB5E2, 0x7898, 0xB5E3, 0x70B9, 0xB5E4, 0x5178, 0xB5E5, 0x975B,
+	0xB5E6, 0x57AB, 0xB5E7, 0x7535, 0xB5E8, 0x4F43, 0xB5E9, 0x7538,	0xB5EA, 0x5E97, 0xB5EB, 0x60E6, 0xB5EC, 0x5960, 0xB5ED, 0x6DC0,
+	0xB5EE, 0x6BBF, 0xB5EF, 0x7889, 0xB5F0, 0x53FC, 0xB5F1, 0x96D5,	0xB5F2, 0x51CB, 0xB5F3, 0x5201, 0xB5F4, 0x6389, 0xB5F5, 0x540A,
+	0xB5F6, 0x9493, 0xB5F7, 0x8C03, 0xB5F8, 0x8DCC, 0xB5F9, 0x7239,	0xB5FA, 0x789F, 0xB5FB, 0x8776, 0xB5FC, 0x8FED, 0xB5FD, 0x8C0D,
+	0xB5FE, 0x53E0, 0xB640, 0x7993, 0xB641, 0x7994, 0xB642, 0x7995,	0xB643, 0x7996, 0xB644, 0x7997, 0xB645, 0x7998, 0xB646, 0x7999,
+	0xB647, 0x799B, 0xB648, 0x799C, 0xB649, 0x799D, 0xB64A, 0x799E,	0xB64B, 0x799F, 0xB64C, 0x79A0, 0xB64D, 0x79A1, 0xB64E, 0x79A2,
+	0xB64F, 0x79A3, 0xB650, 0x79A4, 0xB651, 0x79A5, 0xB652, 0x79A6,	0xB653, 0x79A8, 0xB654, 0x79A9, 0xB655, 0x79AA, 0xB656, 0x79AB,
+	0xB657, 0x79AC, 0xB658, 0x79AD, 0xB659, 0x79AE, 0xB65A, 0x79AF,	0xB65B, 0x79B0, 0xB65C, 0x79B1, 0xB65D, 0x79B2, 0xB65E, 0x79B4,
+	0xB65F, 0x79B5, 0xB660, 0x79B6, 0xB661, 0x79B7, 0xB662, 0x79B8,	0xB663, 0x79BC, 0xB664, 0x79BF, 0xB665, 0x79C2, 0xB666, 0x79C4,
+	0xB667, 0x79C5, 0xB668, 0x79C7, 0xB669, 0x79C8, 0xB66A, 0x79CA,	0xB66B, 0x79CC, 0xB66C, 0x79CE, 0xB66D, 0x79CF, 0xB66E, 0x79D0,
+	0xB66F, 0x79D3, 0xB670, 0x79D4, 0xB671, 0x79D6, 0xB672, 0x79D7,	0xB673, 0x79D9, 0xB674, 0x79DA, 0xB675, 0x79DB, 0xB676, 0x79DC,
+	0xB677, 0x79DD, 0xB678, 0x79DE, 0xB679, 0x79E0, 0xB67A, 0x79E1,	0xB67B, 0x79E2, 0xB67C, 0x79E5, 0xB67D, 0x79E8, 0xB67E, 0x79EA,
+	0xB680, 0x79EC, 0xB681, 0x79EE, 0xB682, 0x79F1, 0xB683, 0x79F2,	0xB684, 0x79F3, 0xB685, 0x79F4, 0xB686, 0x79F5, 0xB687, 0x79F6,
+	0xB688, 0x79F7, 0xB689, 0x79F9, 0xB68A, 0x79FA, 0xB68B, 0x79FC,	0xB68C, 0x79FE, 0xB68D, 0x79FF, 0xB68E, 0x7A01, 0xB68F, 0x7A04,
+	0xB690, 0x7A05, 0xB691, 0x7A07, 0xB692, 0x7A08, 0xB693, 0x7A09,	0xB694, 0x7A0A, 0xB695, 0x7A0C, 0xB696, 0x7A0F, 0xB697, 0x7A10,
+	0xB698, 0x7A11, 0xB699, 0x7A12, 0xB69A, 0x7A13, 0xB69B, 0x7A15,	0xB69C, 0x7A16, 0xB69D, 0x7A18, 0xB69E, 0x7A19, 0xB69F, 0x7A1B,
+	0xB6A0, 0x7A1C, 0xB6A1, 0x4E01, 0xB6A2, 0x76EF, 0xB6A3, 0x53EE,	0xB6A4, 0x9489, 0xB6A5, 0x9876, 0xB6A6, 0x9F0E, 0xB6A7, 0x952D,
+	0xB6A8, 0x5B9A, 0xB6A9, 0x8BA2, 0xB6AA, 0x4E22, 0xB6AB, 0x4E1C,	0xB6AC, 0x51AC, 0xB6AD, 0x8463, 0xB6AE, 0x61C2, 0xB6AF, 0x52A8,
+	0xB6B0, 0x680B, 0xB6B1, 0x4F97, 0xB6B2, 0x606B, 0xB6B3, 0x51BB,	0xB6B4, 0x6D1E, 0xB6B5, 0x515C, 0xB6B6, 0x6296, 0xB6B7, 0x6597,
+	0xB6B8, 0x9661, 0xB6B9, 0x8C46, 0xB6BA, 0x9017, 0xB6BB, 0x75D8,	0xB6BC, 0x90FD, 0xB6BD, 0x7763, 0xB6BE, 0x6BD2, 0xB6BF, 0x728A,
+	0xB6C0, 0x72EC, 0xB6C1, 0x8BFB, 0xB6C2, 0x5835, 0xB6C3, 0x7779,	0xB6C4, 0x8D4C, 0xB6C5, 0x675C, 0xB6C6, 0x9540, 0xB6C7, 0x809A,
+	0xB6C8, 0x5EA6, 0xB6C9, 0x6E21, 0xB6CA, 0x5992, 0xB6CB, 0x7AEF,	0xB6CC, 0x77ED, 0xB6CD, 0x953B, 0xB6CE, 0x6BB5, 0xB6CF, 0x65AD,
+	0xB6D0, 0x7F0E, 0xB6D1, 0x5806, 0xB6D2, 0x5151, 0xB6D3, 0x961F,	0xB6D4, 0x5BF9, 0xB6D5, 0x58A9, 0xB6D6, 0x5428, 0xB6D7, 0x8E72,
+	0xB6D8, 0x6566, 0xB6D9, 0x987F, 0xB6DA, 0x56E4, 0xB6DB, 0x949D,	0xB6DC, 0x76FE, 0xB6DD, 0x9041, 0xB6DE, 0x6387, 0xB6DF, 0x54C6,
+	0xB6E0, 0x591A, 0xB6E1, 0x593A, 0xB6E2, 0x579B, 0xB6E3, 0x8EB2,	0xB6E4, 0x6735, 0xB6E5, 0x8DFA, 0xB6E6, 0x8235, 0xB6E7, 0x5241,
+	0xB6E8, 0x60F0, 0xB6E9, 0x5815, 0xB6EA, 0x86FE, 0xB6EB, 0x5CE8,	0xB6EC, 0x9E45, 0xB6ED, 0x4FC4, 0xB6EE, 0x989D, 0xB6EF, 0x8BB9,
+	0xB6F0, 0x5A25, 0xB6F1, 0x6076, 0xB6F2, 0x5384, 0xB6F3, 0x627C,	0xB6F4, 0x904F, 0xB6F5, 0x9102, 0xB6F6, 0x997F, 0xB6F7, 0x6069,
+	0xB6F8, 0x800C, 0xB6F9, 0x513F, 0xB6FA, 0x8033, 0xB6FB, 0x5C14,	0xB6FC, 0x9975, 0xB6FD, 0x6D31, 0xB6FE, 0x4E8C, 0xB740, 0x7A1D,
+	0xB741, 0x7A1F, 0xB742, 0x7A21, 0xB743, 0x7A22, 0xB744, 0x7A24,	0xB745, 0x7A25, 0xB746, 0x7A26, 0xB747, 0x7A27, 0xB748, 0x7A28,
+	0xB749, 0x7A29, 0xB74A, 0x7A2A, 0xB74B, 0x7A2B, 0xB74C, 0x7A2C,	0xB74D, 0x7A2D, 0xB74E, 0x7A2E, 0xB74F, 0x7A2F, 0xB750, 0x7A30,
+	0xB751, 0x7A31, 0xB752, 0x7A32, 0xB753, 0x7A34, 0xB754, 0x7A35,	0xB755, 0x7A36, 0xB756, 0x7A38, 0xB757, 0x7A3A, 0xB758, 0x7A3E,
+	0xB759, 0x7A40, 0xB75A, 0x7A41, 0xB75B, 0x7A42, 0xB75C, 0x7A43,	0xB75D, 0x7A44, 0xB75E, 0x7A45, 0xB75F, 0x7A47, 0xB760, 0x7A48,
+	0xB761, 0x7A49, 0xB762, 0x7A4A, 0xB763, 0x7A4B, 0xB764, 0x7A4C,	0xB765, 0x7A4D, 0xB766, 0x7A4E, 0xB767, 0x7A4F, 0xB768, 0x7A50,
+	0xB769, 0x7A52, 0xB76A, 0x7A53, 0xB76B, 0x7A54, 0xB76C, 0x7A55,	0xB76D, 0x7A56, 0xB76E, 0x7A58, 0xB76F, 0x7A59, 0xB770, 0x7A5A,
+	0xB771, 0x7A5B, 0xB772, 0x7A5C, 0xB773, 0x7A5D, 0xB774, 0x7A5E,	0xB775, 0x7A5F, 0xB776, 0x7A60, 0xB777, 0x7A61, 0xB778, 0x7A62,
+	0xB779, 0x7A63, 0xB77A, 0x7A64, 0xB77B, 0x7A65, 0xB77C, 0x7A66,	0xB77D, 0x7A67, 0xB77E, 0x7A68, 0xB780, 0x7A69, 0xB781, 0x7A6A,
+	0xB782, 0x7A6B, 0xB783, 0x7A6C, 0xB784, 0x7A6D, 0xB785, 0x7A6E,	0xB786, 0x7A6F, 0xB787, 0x7A71, 0xB788, 0x7A72, 0xB789, 0x7A73,
+	0xB78A, 0x7A75, 0xB78B, 0x7A7B, 0xB78C, 0x7A7C, 0xB78D, 0x7A7D,	0xB78E, 0x7A7E, 0xB78F, 0x7A82, 0xB790, 0x7A85, 0xB791, 0x7A87,
+	0xB792, 0x7A89, 0xB793, 0x7A8A, 0xB794, 0x7A8B, 0xB795, 0x7A8C,	0xB796, 0x7A8E, 0xB797, 0x7A8F, 0xB798, 0x7A90, 0xB799, 0x7A93,
+	0xB79A, 0x7A94, 0xB79B, 0x7A99, 0xB79C, 0x7A9A, 0xB79D, 0x7A9B,	0xB79E, 0x7A9E, 0xB79F, 0x7AA1, 0xB7A0, 0x7AA2, 0xB7A1, 0x8D30,
+	0xB7A2, 0x53D1, 0xB7A3, 0x7F5A, 0xB7A4, 0x7B4F, 0xB7A5, 0x4F10,	0xB7A6, 0x4E4F, 0xB7A7, 0x9600, 0xB7A8, 0x6CD5, 0xB7A9, 0x73D0,
+	0xB7AA, 0x85E9, 0xB7AB, 0x5E06, 0xB7AC, 0x756A, 0xB7AD, 0x7FFB,	0xB7AE, 0x6A0A, 0xB7AF, 0x77FE, 0xB7B0, 0x9492, 0xB7B1, 0x7E41,
+	0xB7B2, 0x51E1, 0xB7B3, 0x70E6, 0xB7B4, 0x53CD, 0xB7B5, 0x8FD4,	0xB7B6, 0x8303, 0xB7B7, 0x8D29, 0xB7B8, 0x72AF, 0xB7B9, 0x996D,
+	0xB7BA, 0x6CDB, 0xB7BB, 0x574A, 0xB7BC, 0x82B3, 0xB7BD, 0x65B9,	0xB7BE, 0x80AA, 0xB7BF, 0x623F, 0xB7C0, 0x9632, 0xB7C1, 0x59A8,
+	0xB7C2, 0x4EFF, 0xB7C3, 0x8BBF, 0xB7C4, 0x7EBA, 0xB7C5, 0x653E,	0xB7C6, 0x83F2, 0xB7C7, 0x975E, 0xB7C8, 0x5561, 0xB7C9, 0x98DE,
+	0xB7CA, 0x80A5, 0xB7CB, 0x532A, 0xB7CC, 0x8BFD, 0xB7CD, 0x5420,	0xB7CE, 0x80BA, 0xB7CF, 0x5E9F, 0xB7D0, 0x6CB8, 0xB7D1, 0x8D39,
+	0xB7D2, 0x82AC, 0xB7D3, 0x915A, 0xB7D4, 0x5429, 0xB7D5, 0x6C1B,	0xB7D6, 0x5206, 0xB7D7, 0x7EB7, 0xB7D8, 0x575F, 0xB7D9, 0x711A,
+	0xB7DA, 0x6C7E, 0xB7DB, 0x7C89, 0xB7DC, 0x594B, 0xB7DD, 0x4EFD,	0xB7DE, 0x5FFF, 0xB7DF, 0x6124, 0xB7E0, 0x7CAA, 0xB7E1, 0x4E30,
+	0xB7E2, 0x5C01, 0xB7E3, 0x67AB, 0xB7E4, 0x8702, 0xB7E5, 0x5CF0,	0xB7E6, 0x950B, 0xB7E7, 0x98CE, 0xB7E8, 0x75AF, 0xB7E9, 0x70FD,
+	0xB7EA, 0x9022, 0xB7EB, 0x51AF, 0xB7EC, 0x7F1D, 0xB7ED, 0x8BBD,	0xB7EE, 0x5949, 0xB7EF, 0x51E4, 0xB7F0, 0x4F5B, 0xB7F1, 0x5426,
+	0xB7F2, 0x592B, 0xB7F3, 0x6577, 0xB7F4, 0x80A4, 0xB7F5, 0x5B75,	0xB7F6, 0x6276, 0xB7F7, 0x62C2, 0xB7F8, 0x8F90, 0xB7F9, 0x5E45,
+	0xB7FA, 0x6C1F, 0xB7FB, 0x7B26, 0xB7FC, 0x4F0F, 0xB7FD, 0x4FD8,	0xB7FE, 0x670D, 0xB840, 0x7AA3, 0xB841, 0x7AA4, 0xB842, 0x7AA7,
+	0xB843, 0x7AA9, 0xB844, 0x7AAA, 0xB845, 0x7AAB, 0xB846, 0x7AAE,	0xB847, 0x7AAF, 0xB848, 0x7AB0, 0xB849, 0x7AB1, 0xB84A, 0x7AB2,
+	0xB84B, 0x7AB4, 0xB84C, 0x7AB5, 0xB84D, 0x7AB6, 0xB84E, 0x7AB7,	0xB84F, 0x7AB8, 0xB850, 0x7AB9, 0xB851, 0x7ABA, 0xB852, 0x7ABB,
+	0xB853, 0x7ABC, 0xB854, 0x7ABD, 0xB855, 0x7ABE, 0xB856, 0x7AC0,	0xB857, 0x7AC1, 0xB858, 0x7AC2, 0xB859, 0x7AC3, 0xB85A, 0x7AC4,
+	0xB85B, 0x7AC5, 0xB85C, 0x7AC6, 0xB85D, 0x7AC7, 0xB85E, 0x7AC8,	0xB85F, 0x7AC9, 0xB860, 0x7ACA, 0xB861, 0x7ACC, 0xB862, 0x7ACD,
+	0xB863, 0x7ACE, 0xB864, 0x7ACF, 0xB865, 0x7AD0, 0xB866, 0x7AD1,	0xB867, 0x7AD2, 0xB868, 0x7AD3, 0xB869, 0x7AD4, 0xB86A, 0x7AD5,
+	0xB86B, 0x7AD7, 0xB86C, 0x7AD8, 0xB86D, 0x7ADA, 0xB86E, 0x7ADB,	0xB86F, 0x7ADC, 0xB870, 0x7ADD, 0xB871, 0x7AE1, 0xB872, 0x7AE2,
+	0xB873, 0x7AE4, 0xB874, 0x7AE7, 0xB875, 0x7AE8, 0xB876, 0x7AE9,	0xB877, 0x7AEA, 0xB878, 0x7AEB, 0xB879, 0x7AEC, 0xB87A, 0x7AEE,
+	0xB87B, 0x7AF0, 0xB87C, 0x7AF1, 0xB87D, 0x7AF2, 0xB87E, 0x7AF3,	0xB880, 0x7AF4, 0xB881, 0x7AF5, 0xB882, 0x7AF6, 0xB883, 0x7AF7,
+	0xB884, 0x7AF8, 0xB885, 0x7AFB, 0xB886, 0x7AFC, 0xB887, 0x7AFE,	0xB888, 0x7B00, 0xB889, 0x7B01, 0xB88A, 0x7B02, 0xB88B, 0x7B05,
+	0xB88C, 0x7B07, 0xB88D, 0x7B09, 0xB88E, 0x7B0C, 0xB88F, 0x7B0D,	0xB890, 0x7B0E, 0xB891, 0x7B10, 0xB892, 0x7B12, 0xB893, 0x7B13,
+	0xB894, 0x7B16, 0xB895, 0x7B17, 0xB896, 0x7B18, 0xB897, 0x7B1A,	0xB898, 0x7B1C, 0xB899, 0x7B1D, 0xB89A, 0x7B1F, 0xB89B, 0x7B21,
+	0xB89C, 0x7B22, 0xB89D, 0x7B23, 0xB89E, 0x7B27, 0xB89F, 0x7B29,	0xB8A0, 0x7B2D, 0xB8A1, 0x6D6E, 0xB8A2, 0x6DAA, 0xB8A3, 0x798F,
+	0xB8A4, 0x88B1, 0xB8A5, 0x5F17, 0xB8A6, 0x752B, 0xB8A7, 0x629A,	0xB8A8, 0x8F85, 0xB8A9, 0x4FEF, 0xB8AA, 0x91DC, 0xB8AB, 0x65A7,
+	0xB8AC, 0x812F, 0xB8AD, 0x8151, 0xB8AE, 0x5E9C, 0xB8AF, 0x8150,	0xB8B0, 0x8D74, 0xB8B1, 0x526F, 0xB8B2, 0x8986, 0xB8B3, 0x8D4B,
+	0xB8B4, 0x590D, 0xB8B5, 0x5085, 0xB8B6, 0x4ED8, 0xB8B7, 0x961C,	0xB8B8, 0x7236, 0xB8B9, 0x8179, 0xB8BA, 0x8D1F, 0xB8BB, 0x5BCC,
+	0xB8BC, 0x8BA3, 0xB8BD, 0x9644, 0xB8BE, 0x5987, 0xB8BF, 0x7F1A,	0xB8C0, 0x5490, 0xB8C1, 0x5676, 0xB8C2, 0x560E, 0xB8C3, 0x8BE5,
+	0xB8C4, 0x6539, 0xB8C5, 0x6982, 0xB8C6, 0x9499, 0xB8C7, 0x76D6,	0xB8C8, 0x6E89, 0xB8C9, 0x5E72, 0xB8CA, 0x7518, 0xB8CB, 0x6746,
+	0xB8CC, 0x67D1, 0xB8CD, 0x7AFF, 0xB8CE, 0x809D, 0xB8CF, 0x8D76,	0xB8D0, 0x611F, 0xB8D1, 0x79C6, 0xB8D2, 0x6562, 0xB8D3, 0x8D63,
+	0xB8D4, 0x5188, 0xB8D5, 0x521A, 0xB8D6, 0x94A2, 0xB8D7, 0x7F38,	0xB8D8, 0x809B, 0xB8D9, 0x7EB2, 0xB8DA, 0x5C97, 0xB8DB, 0x6E2F,
+	0xB8DC, 0x6760, 0xB8DD, 0x7BD9, 0xB8DE, 0x768B, 0xB8DF, 0x9AD8,	0xB8E0, 0x818F, 0xB8E1, 0x7F94, 0xB8E2, 0x7CD5, 0xB8E3, 0x641E,
+	0xB8E4, 0x9550, 0xB8E5, 0x7A3F, 0xB8E6, 0x544A, 0xB8E7, 0x54E5,	0xB8E8, 0x6B4C, 0xB8E9, 0x6401, 0xB8EA, 0x6208, 0xB8EB, 0x9E3D,
+	0xB8EC, 0x80F3, 0xB8ED, 0x7599, 0xB8EE, 0x5272, 0xB8EF, 0x9769,	0xB8F0, 0x845B, 0xB8F1, 0x683C, 0xB8F2, 0x86E4, 0xB8F3, 0x9601,
+	0xB8F4, 0x9694, 0xB8F5, 0x94EC, 0xB8F6, 0x4E2A, 0xB8F7, 0x5404,	0xB8F8, 0x7ED9, 0xB8F9, 0x6839, 0xB8FA, 0x8DDF, 0xB8FB, 0x8015,
+	0xB8FC, 0x66F4, 0xB8FD, 0x5E9A, 0xB8FE, 0x7FB9, 0xB940, 0x7B2F,	0xB941, 0x7B30, 0xB942, 0x7B32, 0xB943, 0x7B34, 0xB944, 0x7B35,
+	0xB945, 0x7B36, 0xB946, 0x7B37, 0xB947, 0x7B39, 0xB948, 0x7B3B,	0xB949, 0x7B3D, 0xB94A, 0x7B3F, 0xB94B, 0x7B40, 0xB94C, 0x7B41,
+	0xB94D, 0x7B42, 0xB94E, 0x7B43, 0xB94F, 0x7B44, 0xB950, 0x7B46,	0xB951, 0x7B48, 0xB952, 0x7B4A, 0xB953, 0x7B4D, 0xB954, 0x7B4E,
+	0xB955, 0x7B53, 0xB956, 0x7B55, 0xB957, 0x7B57, 0xB958, 0x7B59,	0xB959, 0x7B5C, 0xB95A, 0x7B5E, 0xB95B, 0x7B5F, 0xB95C, 0x7B61,
+	0xB95D, 0x7B63, 0xB95E, 0x7B64, 0xB95F, 0x7B65, 0xB960, 0x7B66,	0xB961, 0x7B67, 0xB962, 0x7B68, 0xB963, 0x7B69, 0xB964, 0x7B6A,
+	0xB965, 0x7B6B, 0xB966, 0x7B6C, 0xB967, 0x7B6D, 0xB968, 0x7B6F,	0xB969, 0x7B70, 0xB96A, 0x7B73, 0xB96B, 0x7B74, 0xB96C, 0x7B76,
+	0xB96D, 0x7B78, 0xB96E, 0x7B7A, 0xB96F, 0x7B7C, 0xB970, 0x7B7D,	0xB971, 0x7B7F, 0xB972, 0x7B81, 0xB973, 0x7B82, 0xB974, 0x7B83,
+	0xB975, 0x7B84, 0xB976, 0x7B86, 0xB977, 0x7B87, 0xB978, 0x7B88,	0xB979, 0x7B89, 0xB97A, 0x7B8A, 0xB97B, 0x7B8B, 0xB97C, 0x7B8C,
+	0xB97D, 0x7B8E, 0xB97E, 0x7B8F, 0xB980, 0x7B91, 0xB981, 0x7B92,	0xB982, 0x7B93, 0xB983, 0x7B96, 0xB984, 0x7B98, 0xB985, 0x7B99,
+	0xB986, 0x7B9A, 0xB987, 0x7B9B, 0xB988, 0x7B9E, 0xB989, 0x7B9F,	0xB98A, 0x7BA0, 0xB98B, 0x7BA3, 0xB98C, 0x7BA4, 0xB98D, 0x7BA5,
+	0xB98E, 0x7BAE, 0xB98F, 0x7BAF, 0xB990, 0x7BB0, 0xB991, 0x7BB2,	0xB992, 0x7BB3, 0xB993, 0x7BB5, 0xB994, 0x7BB6, 0xB995, 0x7BB7,
+	0xB996, 0x7BB9, 0xB997, 0x7BBA, 0xB998, 0x7BBB, 0xB999, 0x7BBC,	0xB99A, 0x7BBD, 0xB99B, 0x7BBE, 0xB99C, 0x7BBF, 0xB99D, 0x7BC0,
+	0xB99E, 0x7BC2, 0xB99F, 0x7BC3, 0xB9A0, 0x7BC4, 0xB9A1, 0x57C2,	0xB9A2, 0x803F, 0xB9A3, 0x6897, 0xB9A4, 0x5DE5, 0xB9A5, 0x653B,
+	0xB9A6, 0x529F, 0xB9A7, 0x606D, 0xB9A8, 0x9F9A, 0xB9A9, 0x4F9B,	0xB9AA, 0x8EAC, 0xB9AB, 0x516C, 0xB9AC, 0x5BAB, 0xB9AD, 0x5F13,
+	0xB9AE, 0x5DE9, 0xB9AF, 0x6C5E, 0xB9B0, 0x62F1, 0xB9B1, 0x8D21,	0xB9B2, 0x5171, 0xB9B3, 0x94A9, 0xB9B4, 0x52FE, 0xB9B5, 0x6C9F,
+	0xB9B6, 0x82DF, 0xB9B7, 0x72D7, 0xB9B8, 0x57A2, 0xB9B9, 0x6784,	0xB9BA, 0x8D2D, 0xB9BB, 0x591F, 0xB9BC, 0x8F9C, 0xB9BD, 0x83C7,
+	0xB9BE, 0x5495, 0xB9BF, 0x7B8D, 0xB9C0, 0x4F30, 0xB9C1, 0x6CBD,	0xB9C2, 0x5B64, 0xB9C3, 0x59D1, 0xB9C4, 0x9F13, 0xB9C5, 0x53E4,
+	0xB9C6, 0x86CA, 0xB9C7, 0x9AA8, 0xB9C8, 0x8C37, 0xB9C9, 0x80A1,	0xB9CA, 0x6545, 0xB9CB, 0x987E, 0xB9CC, 0x56FA, 0xB9CD, 0x96C7,
+	0xB9CE, 0x522E, 0xB9CF, 0x74DC, 0xB9D0, 0x5250, 0xB9D1, 0x5BE1,	0xB9D2, 0x6302, 0xB9D3, 0x8902, 0xB9D4, 0x4E56, 0xB9D5, 0x62D0,
+	0xB9D6, 0x602A, 0xB9D7, 0x68FA, 0xB9D8, 0x5173, 0xB9D9, 0x5B98,	0xB9DA, 0x51A0, 0xB9DB, 0x89C2, 0xB9DC, 0x7BA1, 0xB9DD, 0x9986,
+	0xB9DE, 0x7F50, 0xB9DF, 0x60EF, 0xB9E0, 0x704C, 0xB9E1, 0x8D2F,	0xB9E2, 0x5149, 0xB9E3, 0x5E7F, 0xB9E4, 0x901B, 0xB9E5, 0x7470,
+	0xB9E6, 0x89C4, 0xB9E7, 0x572D, 0xB9E8, 0x7845, 0xB9E9, 0x5F52,	0xB9EA, 0x9F9F, 0xB9EB, 0x95FA, 0xB9EC, 0x8F68, 0xB9ED, 0x9B3C,
+	0xB9EE, 0x8BE1, 0xB9EF, 0x7678, 0xB9F0, 0x6842, 0xB9F1, 0x67DC,	0xB9F2, 0x8DEA, 0xB9F3, 0x8D35, 0xB9F4, 0x523D, 0xB9F5, 0x8F8A,
+	0xB9F6, 0x6EDA, 0xB9F7, 0x68CD, 0xB9F8, 0x9505, 0xB9F9, 0x90ED,	0xB9FA, 0x56FD, 0xB9FB, 0x679C, 0xB9FC, 0x88F9, 0xB9FD, 0x8FC7,
+	0xB9FE, 0x54C8, 0xBA40, 0x7BC5, 0xBA41, 0x7BC8, 0xBA42, 0x7BC9,	0xBA43, 0x7BCA, 0xBA44, 0x7BCB, 0xBA45, 0x7BCD, 0xBA46, 0x7BCE,
+	0xBA47, 0x7BCF, 0xBA48, 0x7BD0, 0xBA49, 0x7BD2, 0xBA4A, 0x7BD4,	0xBA4B, 0x7BD5, 0xBA4C, 0x7BD6, 0xBA4D, 0x7BD7, 0xBA4E, 0x7BD8,
+	0xBA4F, 0x7BDB, 0xBA50, 0x7BDC, 0xBA51, 0x7BDE, 0xBA52, 0x7BDF,	0xBA53, 0x7BE0, 0xBA54, 0x7BE2, 0xBA55, 0x7BE3, 0xBA56, 0x7BE4,
+	0xBA57, 0x7BE7, 0xBA58, 0x7BE8, 0xBA59, 0x7BE9, 0xBA5A, 0x7BEB,	0xBA5B, 0x7BEC, 0xBA5C, 0x7BED, 0xBA5D, 0x7BEF, 0xBA5E, 0x7BF0,
+	0xBA5F, 0x7BF2, 0xBA60, 0x7BF3, 0xBA61, 0x7BF4, 0xBA62, 0x7BF5,	0xBA63, 0x7BF6, 0xBA64, 0x7BF8, 0xBA65, 0x7BF9, 0xBA66, 0x7BFA,
+	0xBA67, 0x7BFB, 0xBA68, 0x7BFD, 0xBA69, 0x7BFF, 0xBA6A, 0x7C00,	0xBA6B, 0x7C01, 0xBA6C, 0x7C02, 0xBA6D, 0x7C03, 0xBA6E, 0x7C04,
+	0xBA6F, 0x7C05, 0xBA70, 0x7C06, 0xBA71, 0x7C08, 0xBA72, 0x7C09,	0xBA73, 0x7C0A, 0xBA74, 0x7C0D, 0xBA75, 0x7C0E, 0xBA76, 0x7C10,
+	0xBA77, 0x7C11, 0xBA78, 0x7C12, 0xBA79, 0x7C13, 0xBA7A, 0x7C14,	0xBA7B, 0x7C15, 0xBA7C, 0x7C17, 0xBA7D, 0x7C18, 0xBA7E, 0x7C19,
+	0xBA80, 0x7C1A, 0xBA81, 0x7C1B, 0xBA82, 0x7C1C, 0xBA83, 0x7C1D,	0xBA84, 0x7C1E, 0xBA85, 0x7C20, 0xBA86, 0x7C21, 0xBA87, 0x7C22,
+	0xBA88, 0x7C23, 0xBA89, 0x7C24, 0xBA8A, 0x7C25, 0xBA8B, 0x7C28,	0xBA8C, 0x7C29, 0xBA8D, 0x7C2B, 0xBA8E, 0x7C2C, 0xBA8F, 0x7C2D,
+	0xBA90, 0x7C2E, 0xBA91, 0x7C2F, 0xBA92, 0x7C30, 0xBA93, 0x7C31,	0xBA94, 0x7C32, 0xBA95, 0x7C33, 0xBA96, 0x7C34, 0xBA97, 0x7C35,
+	0xBA98, 0x7C36, 0xBA99, 0x7C37, 0xBA9A, 0x7C39, 0xBA9B, 0x7C3A,	0xBA9C, 0x7C3B, 0xBA9D, 0x7C3C, 0xBA9E, 0x7C3D, 0xBA9F, 0x7C3E,
+	0xBAA0, 0x7C42, 0xBAA1, 0x9AB8, 0xBAA2, 0x5B69, 0xBAA3, 0x6D77,	0xBAA4, 0x6C26, 0xBAA5, 0x4EA5, 0xBAA6, 0x5BB3, 0xBAA7, 0x9A87,
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+	0xBAC8, 0x559D, 0xBAC9, 0x8377, 0xBACA, 0x83CF, 0xBACB, 0x6838,	0xBACC, 0x79BE, 0xBACD, 0x548C, 0xBACE, 0x4F55, 0xBACF, 0x5408,
+	0xBAD0, 0x76D2, 0xBAD1, 0x8C89, 0xBAD2, 0x9602, 0xBAD3, 0x6CB3,	0xBAD4, 0x6DB8, 0xBAD5, 0x8D6B, 0xBAD6, 0x8910, 0xBAD7, 0x9E64,
+	0xBAD8, 0x8D3A, 0xBAD9, 0x563F, 0xBADA, 0x9ED1, 0xBADB, 0x75D5,	0xBADC, 0x5F88, 0xBADD, 0x72E0, 0xBADE, 0x6068, 0xBADF, 0x54FC,
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+	0xBB82, 0x7C8B, 0xBB83, 0x7C8C, 0xBB84, 0x7C8D, 0xBB85, 0x7C8E,	0xBB86, 0x7C8F, 0xBB87, 0x7C90, 0xBB88, 0x7C93, 0xBB89, 0x7C94,
+	0xBB8A, 0x7C96, 0xBB8B, 0x7C99, 0xBB8C, 0x7C9A, 0xBB8D, 0x7C9B,	0xBB8E, 0x7CA0, 0xBB8F, 0x7CA1, 0xBB90, 0x7CA3, 0xBB91, 0x7CA6,
+	0xBB92, 0x7CA7, 0xBB93, 0x7CA8, 0xBB94, 0x7CA9, 0xBB95, 0x7CAB,	0xBB96, 0x7CAC, 0xBB97, 0x7CAD, 0xBB98, 0x7CAF, 0xBB99, 0x7CB0,
+	0xBB9A, 0x7CB4, 0xBB9B, 0x7CB5, 0xBB9C, 0x7CB6, 0xBB9D, 0x7CB7,	0xBB9E, 0x7CB8, 0xBB9F, 0x7CBA, 0xBBA0, 0x7CBB, 0xBBA1, 0x5F27,
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+	0xBBBA, 0x7F13, 0xBBBB, 0x6362, 0xBBBC, 0x60A3, 0xBBBD, 0x5524,	0xBBBE, 0x75EA, 0xBBBF, 0x8C62, 0xBBC0, 0x7115, 0xBBC1, 0x6DA3,
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+	0xBBDA, 0x6094, 0xBBDB, 0x6167, 0xBBDC, 0x5349, 0xBBDD, 0x60E0,	0xBBDE, 0x6666, 0xBBDF, 0x8D3F, 0xBBE0, 0x79FD, 0xBBE1, 0x4F1A,
+	0xBBE2, 0x70E9, 0xBBE3, 0x6C47, 0xBBE4, 0x8BB3, 0xBBE5, 0x8BF2,	0xBBE6, 0x7ED8, 0xBBE7, 0x8364, 0xBBE8, 0x660F, 0xBBE9, 0x5A5A,
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+	0xBC53, 0x7CDE, 0xBC54, 0x7CE1, 0xBC55, 0x7CE2, 0xBC56, 0x7CE3,	0xBC57, 0x7CE4, 0xBC58, 0x7CE5, 0xBC59, 0x7CE6, 0xBC5A, 0x7CE7,
+	0xBC5B, 0x7CE9, 0xBC5C, 0x7CEA, 0xBC5D, 0x7CEB, 0xBC5E, 0x7CEC,	0xBC5F, 0x7CED, 0xBC60, 0x7CEE, 0xBC61, 0x7CF0, 0xBC62, 0x7CF1,
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+	0xBC6B, 0x7CFC, 0xBC6C, 0x7CFD, 0xBC6D, 0x7CFE, 0xBC6E, 0x7CFF,	0xBC6F, 0x7D00, 0xBC70, 0x7D01, 0xBC71, 0x7D02, 0xBC72, 0x7D03,
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+	0xBC8C, 0x7D1D, 0xBC8D, 0x7D1E, 0xBC8E, 0x7D1F, 0xBC8F, 0x7D21,	0xBC90, 0x7D23, 0xBC91, 0x7D24, 0xBC92, 0x7D25, 0xBC93, 0x7D26,
+	0xBC94, 0x7D28, 0xBC95, 0x7D29, 0xBC96, 0x7D2A, 0xBC97, 0x7D2C,	0xBC98, 0x7D2D, 0xBC99, 0x7D2E, 0xBC9A, 0x7D30, 0xBC9B, 0x7D31,
+	0xBC9C, 0x7D32, 0xBC9D, 0x7D33, 0xBC9E, 0x7D34, 0xBC9F, 0x7D35,	0xBCA0, 0x7D36, 0xBCA1, 0x808C, 0xBCA2, 0x9965, 0xBCA3, 0x8FF9,
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+	0xBCAC, 0x68D8, 0xBCAD, 0x8F91, 0xBCAE, 0x7C4D, 0xBCAF, 0x96C6,	0xBCB0, 0x53CA, 0xBCB1, 0x6025, 0xBCB2, 0x75BE, 0xBCB3, 0x6C72,
+	0xBCB4, 0x5373, 0xBCB5, 0x5AC9, 0xBCB6, 0x7EA7, 0xBCB7, 0x6324,	0xBCB8, 0x51E0, 0xBCB9, 0x810A, 0xBCBA, 0x5DF1, 0xBCBB, 0x84DF,
+	0xBCBC, 0x6280, 0xBCBD, 0x5180, 0xBCBE, 0x5B63, 0xBCBF, 0x4F0E,	0xBCC0, 0x796D, 0xBCC1, 0x5242, 0xBCC2, 0x60B8, 0xBCC3, 0x6D4E,
+	0xBCC4, 0x5BC4, 0xBCC5, 0x5BC2, 0xBCC6, 0x8BA1, 0xBCC7, 0x8BB0,	0xBCC8, 0x65E2, 0xBCC9, 0x5FCC, 0xBCCA, 0x9645, 0xBCCB, 0x5993,
+	0xBCCC, 0x7EE7, 0xBCCD, 0x7EAA, 0xBCCE, 0x5609, 0xBCCF, 0x67B7,	0xBCD0, 0x5939, 0xBCD1, 0x4F73, 0xBCD2, 0x5BB6, 0xBCD3, 0x52A0,
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+	0xBCDC, 0x67B6, 0xBCDD, 0x9A7E, 0xBCDE, 0x5AC1, 0xBCDF, 0x6B7C,	0xBCE0, 0x76D1, 0xBCE1, 0x575A, 0xBCE2, 0x5C16, 0xBCE3, 0x7B3A,
+	0xBCE4, 0x95F4, 0xBCE5, 0x714E, 0xBCE6, 0x517C, 0xBCE7, 0x80A9,	0xBCE8, 0x8270, 0xBCE9, 0x5978, 0xBCEA, 0x7F04, 0xBCEB, 0x8327,
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+	0xBCF4, 0x526A, 0xBCF5, 0x51CF, 0xBCF6, 0x8350, 0xBCF7, 0x69DB,	0xBCF8, 0x9274, 0xBCF9, 0x8DF5, 0xBCFA, 0x8D31, 0xBCFB, 0x89C1,
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+	0xC0A4, 0x5764, 0xC0A5, 0x6606, 0xC0A6, 0x6346, 0xC0A7, 0x56F0,	0xC0A8, 0x62EC, 0xC0A9, 0x6269, 0xC0AA, 0x5ED3, 0xC0AB, 0x9614,
+	0xC0AC, 0x5783, 0xC0AD, 0x62C9, 0xC0AE, 0x5587, 0xC0AF, 0x8721,	0xC0B0, 0x814A, 0xC0B1, 0x8FA3, 0xC0B2, 0x5566, 0xC0B3, 0x83B1,
+	0xC0B4, 0x6765, 0xC0B5, 0x8D56, 0xC0B6, 0x84DD, 0xC0B7, 0x5A6A,	0xC0B8, 0x680F, 0xC0B9, 0x62E6, 0xC0BA, 0x7BEE, 0xC0BB, 0x9611,
+	0xC0BC, 0x5170, 0xC0BD, 0x6F9C, 0xC0BE, 0x8C30, 0xC0BF, 0x63FD,	0xC0C0, 0x89C8, 0xC0C1, 0x61D2, 0xC0C2, 0x7F06, 0xC0C3, 0x70C2,
+	0xC0C4, 0x6EE5, 0xC0C5, 0x7405, 0xC0C6, 0x6994, 0xC0C7, 0x72FC,	0xC0C8, 0x5ECA, 0xC0C9, 0x90CE, 0xC0CA, 0x6717, 0xC0CB, 0x6D6A,
+	0xC0CC, 0x635E, 0xC0CD, 0x52B3, 0xC0CE, 0x7262, 0xC0CF, 0x8001,	0xC0D0, 0x4F6C, 0xC0D1, 0x59E5, 0xC0D2, 0x916A, 0xC0D3, 0x70D9,
+	0xC0D4, 0x6D9D, 0xC0D5, 0x52D2, 0xC0D6, 0x4E50, 0xC0D7, 0x96F7,	0xC0D8, 0x956D, 0xC0D9, 0x857E, 0xC0DA, 0x78CA, 0xC0DB, 0x7D2F,
+	0xC0DC, 0x5121, 0xC0DD, 0x5792, 0xC0DE, 0x64C2, 0xC0DF, 0x808B,	0xC0E0, 0x7C7B, 0xC0E1, 0x6CEA, 0xC0E2, 0x68F1, 0xC0E3, 0x695E,
+	0xC0E4, 0x51B7, 0xC0E5, 0x5398, 0xC0E6, 0x68A8, 0xC0E7, 0x7281,	0xC0E8, 0x9ECE, 0xC0E9, 0x7BF1, 0xC0EA, 0x72F8, 0xC0EB, 0x79BB,
+	0xC0EC, 0x6F13, 0xC0ED, 0x7406, 0xC0EE, 0x674E, 0xC0EF, 0x91CC,	0xC0F0, 0x9CA4, 0xC0F1, 0x793C, 0xC0F2, 0x8389, 0xC0F3, 0x8354,
+	0xC0F4, 0x540F, 0xC0F5, 0x6817, 0xC0F6, 0x4E3D, 0xC0F7, 0x5389,	0xC0F8, 0x52B1, 0xC0F9, 0x783E, 0xC0FA, 0x5386, 0xC0FB, 0x5229,
+	0xC0FC, 0x5088, 0xC0FD, 0x4F8B, 0xC0FE, 0x4FD0, 0xC140, 0x7F56,	0xC141, 0x7F59, 0xC142, 0x7F5B, 0xC143, 0x7F5C, 0xC144, 0x7F5D,
+	0xC145, 0x7F5E, 0xC146, 0x7F60, 0xC147, 0x7F63, 0xC148, 0x7F64,	0xC149, 0x7F65, 0xC14A, 0x7F66, 0xC14B, 0x7F67, 0xC14C, 0x7F6B,
+	0xC14D, 0x7F6C, 0xC14E, 0x7F6D, 0xC14F, 0x7F6F, 0xC150, 0x7F70,	0xC151, 0x7F73, 0xC152, 0x7F75, 0xC153, 0x7F76, 0xC154, 0x7F77,
+	0xC155, 0x7F78, 0xC156, 0x7F7A, 0xC157, 0x7F7B, 0xC158, 0x7F7C,	0xC159, 0x7F7D, 0xC15A, 0x7F7F, 0xC15B, 0x7F80, 0xC15C, 0x7F82,
+	0xC15D, 0x7F83, 0xC15E, 0x7F84, 0xC15F, 0x7F85, 0xC160, 0x7F86,	0xC161, 0x7F87, 0xC162, 0x7F88, 0xC163, 0x7F89, 0xC164, 0x7F8B,
+	0xC165, 0x7F8D, 0xC166, 0x7F8F, 0xC167, 0x7F90, 0xC168, 0x7F91,	0xC169, 0x7F92, 0xC16A, 0x7F93, 0xC16B, 0x7F95, 0xC16C, 0x7F96,
+	0xC16D, 0x7F97, 0xC16E, 0x7F98, 0xC16F, 0x7F99, 0xC170, 0x7F9B,	0xC171, 0x7F9C, 0xC172, 0x7FA0, 0xC173, 0x7FA2, 0xC174, 0x7FA3,
+	0xC175, 0x7FA5, 0xC176, 0x7FA6, 0xC177, 0x7FA8, 0xC178, 0x7FA9,	0xC179, 0x7FAA, 0xC17A, 0x7FAB, 0xC17B, 0x7FAC, 0xC17C, 0x7FAD,
+	0xC17D, 0x7FAE, 0xC17E, 0x7FB1, 0xC180, 0x7FB3, 0xC181, 0x7FB4,	0xC182, 0x7FB5, 0xC183, 0x7FB6, 0xC184, 0x7FB7, 0xC185, 0x7FBA,
+	0xC186, 0x7FBB, 0xC187, 0x7FBE, 0xC188, 0x7FC0, 0xC189, 0x7FC2,	0xC18A, 0x7FC3, 0xC18B, 0x7FC4, 0xC18C, 0x7FC6, 0xC18D, 0x7FC7,
+	0xC18E, 0x7FC8, 0xC18F, 0x7FC9, 0xC190, 0x7FCB, 0xC191, 0x7FCD,	0xC192, 0x7FCF, 0xC193, 0x7FD0, 0xC194, 0x7FD1, 0xC195, 0x7FD2,
+	0xC196, 0x7FD3, 0xC197, 0x7FD6, 0xC198, 0x7FD7, 0xC199, 0x7FD9,	0xC19A, 0x7FDA, 0xC19B, 0x7FDB, 0xC19C, 0x7FDC, 0xC19D, 0x7FDD,
+	0xC19E, 0x7FDE, 0xC19F, 0x7FE2, 0xC1A0, 0x7FE3, 0xC1A1, 0x75E2,	0xC1A2, 0x7ACB, 0xC1A3, 0x7C92, 0xC1A4, 0x6CA5, 0xC1A5, 0x96B6,
+	0xC1A6, 0x529B, 0xC1A7, 0x7483, 0xC1A8, 0x54E9, 0xC1A9, 0x4FE9,	0xC1AA, 0x8054, 0xC1AB, 0x83B2, 0xC1AC, 0x8FDE, 0xC1AD, 0x9570,
+	0xC1AE, 0x5EC9, 0xC1AF, 0x601C, 0xC1B0, 0x6D9F, 0xC1B1, 0x5E18,	0xC1B2, 0x655B, 0xC1B3, 0x8138, 0xC1B4, 0x94FE, 0xC1B5, 0x604B,
+	0xC1B6, 0x70BC, 0xC1B7, 0x7EC3, 0xC1B8, 0x7CAE, 0xC1B9, 0x51C9,	0xC1BA, 0x6881, 0xC1BB, 0x7CB1, 0xC1BC, 0x826F, 0xC1BD, 0x4E24,
+	0xC1BE, 0x8F86, 0xC1BF, 0x91CF, 0xC1C0, 0x667E, 0xC1C1, 0x4EAE,	0xC1C2, 0x8C05, 0xC1C3, 0x64A9, 0xC1C4, 0x804A, 0xC1C5, 0x50DA,
+	0xC1C6, 0x7597, 0xC1C7, 0x71CE, 0xC1C8, 0x5BE5, 0xC1C9, 0x8FBD,	0xC1CA, 0x6F66, 0xC1CB, 0x4E86, 0xC1CC, 0x6482, 0xC1CD, 0x9563,
+	0xC1CE, 0x5ED6, 0xC1CF, 0x6599, 0xC1D0, 0x5217, 0xC1D1, 0x88C2,	0xC1D2, 0x70C8, 0xC1D3, 0x52A3, 0xC1D4, 0x730E, 0xC1D5, 0x7433,
+	0xC1D6, 0x6797, 0xC1D7, 0x78F7, 0xC1D8, 0x9716, 0xC1D9, 0x4E34,	0xC1DA, 0x90BB, 0xC1DB, 0x9CDE, 0xC1DC, 0x6DCB, 0xC1DD, 0x51DB,
+	0xC1DE, 0x8D41, 0xC1DF, 0x541D, 0xC1E0, 0x62CE, 0xC1E1, 0x73B2,	0xC1E2, 0x83F1, 0xC1E3, 0x96F6, 0xC1E4, 0x9F84, 0xC1E5, 0x94C3,
+	0xC1E6, 0x4F36, 0xC1E7, 0x7F9A, 0xC1E8, 0x51CC, 0xC1E9, 0x7075,	0xC1EA, 0x9675, 0xC1EB, 0x5CAD, 0xC1EC, 0x9886, 0xC1ED, 0x53E6,
+	0xC1EE, 0x4EE4, 0xC1EF, 0x6E9C, 0xC1F0, 0x7409, 0xC1F1, 0x69B4,	0xC1F2, 0x786B, 0xC1F3, 0x998F, 0xC1F4, 0x7559, 0xC1F5, 0x5218,
+	0xC1F6, 0x7624, 0xC1F7, 0x6D41, 0xC1F8, 0x67F3, 0xC1F9, 0x516D,	0xC1FA, 0x9F99, 0xC1FB, 0x804B, 0xC1FC, 0x5499, 0xC1FD, 0x7B3C,
+	0xC1FE, 0x7ABF, 0xC240, 0x7FE4, 0xC241, 0x7FE7, 0xC242, 0x7FE8,	0xC243, 0x7FEA, 0xC244, 0x7FEB, 0xC245, 0x7FEC, 0xC246, 0x7FED,
+	0xC247, 0x7FEF, 0xC248, 0x7FF2, 0xC249, 0x7FF4, 0xC24A, 0x7FF5,	0xC24B, 0x7FF6, 0xC24C, 0x7FF7, 0xC24D, 0x7FF8, 0xC24E, 0x7FF9,
+	0xC24F, 0x7FFA, 0xC250, 0x7FFD, 0xC251, 0x7FFE, 0xC252, 0x7FFF,	0xC253, 0x8002, 0xC254, 0x8007, 0xC255, 0x8008, 0xC256, 0x8009,
+	0xC257, 0x800A, 0xC258, 0x800E, 0xC259, 0x800F, 0xC25A, 0x8011,	0xC25B, 0x8013, 0xC25C, 0x801A, 0xC25D, 0x801B, 0xC25E, 0x801D,
+	0xC25F, 0x801E, 0xC260, 0x801F, 0xC261, 0x8021, 0xC262, 0x8023,	0xC263, 0x8024, 0xC264, 0x802B, 0xC265, 0x802C, 0xC266, 0x802D,
+	0xC267, 0x802E, 0xC268, 0x802F, 0xC269, 0x8030, 0xC26A, 0x8032,	0xC26B, 0x8034, 0xC26C, 0x8039, 0xC26D, 0x803A, 0xC26E, 0x803C,
+	0xC26F, 0x803E, 0xC270, 0x8040, 0xC271, 0x8041, 0xC272, 0x8044,	0xC273, 0x8045, 0xC274, 0x8047, 0xC275, 0x8048, 0xC276, 0x8049,
+	0xC277, 0x804E, 0xC278, 0x804F, 0xC279, 0x8050, 0xC27A, 0x8051,	0xC27B, 0x8053, 0xC27C, 0x8055, 0xC27D, 0x8056, 0xC27E, 0x8057,
+	0xC280, 0x8059, 0xC281, 0x805B, 0xC282, 0x805C, 0xC283, 0x805D,	0xC284, 0x805E, 0xC285, 0x805F, 0xC286, 0x8060, 0xC287, 0x8061,
+	0xC288, 0x8062, 0xC289, 0x8063, 0xC28A, 0x8064, 0xC28B, 0x8065,	0xC28C, 0x8066, 0xC28D, 0x8067, 0xC28E, 0x8068, 0xC28F, 0x806B,
+	0xC290, 0x806C, 0xC291, 0x806D, 0xC292, 0x806E, 0xC293, 0x806F,	0xC294, 0x8070, 0xC295, 0x8072, 0xC296, 0x8073, 0xC297, 0x8074,
+	0xC298, 0x8075, 0xC299, 0x8076, 0xC29A, 0x8077, 0xC29B, 0x8078,	0xC29C, 0x8079, 0xC29D, 0x807A, 0xC29E, 0x807B, 0xC29F, 0x807C,
+	0xC2A0, 0x807D, 0xC2A1, 0x9686, 0xC2A2, 0x5784, 0xC2A3, 0x62E2,	0xC2A4, 0x9647, 0xC2A5, 0x697C, 0xC2A6, 0x5A04, 0xC2A7, 0x6402,
+	0xC2A8, 0x7BD3, 0xC2A9, 0x6F0F, 0xC2AA, 0x964B, 0xC2AB, 0x82A6,	0xC2AC, 0x5362, 0xC2AD, 0x9885, 0xC2AE, 0x5E90, 0xC2AF, 0x7089,
+	0xC2B0, 0x63B3, 0xC2B1, 0x5364, 0xC2B2, 0x864F, 0xC2B3, 0x9C81,	0xC2B4, 0x9E93, 0xC2B5, 0x788C, 0xC2B6, 0x9732, 0xC2B7, 0x8DEF,
+	0xC2B8, 0x8D42, 0xC2B9, 0x9E7F, 0xC2BA, 0x6F5E, 0xC2BB, 0x7984,	0xC2BC, 0x5F55, 0xC2BD, 0x9646, 0xC2BE, 0x622E, 0xC2BF, 0x9A74,
+	0xC2C0, 0x5415, 0xC2C1, 0x94DD, 0xC2C2, 0x4FA3, 0xC2C3, 0x65C5,	0xC2C4, 0x5C65, 0xC2C5, 0x5C61, 0xC2C6, 0x7F15, 0xC2C7, 0x8651,
+	0xC2C8, 0x6C2F, 0xC2C9, 0x5F8B, 0xC2CA, 0x7387, 0xC2CB, 0x6EE4,	0xC2CC, 0x7EFF, 0xC2CD, 0x5CE6, 0xC2CE, 0x631B, 0xC2CF, 0x5B6A,
+	0xC2D0, 0x6EE6, 0xC2D1, 0x5375, 0xC2D2, 0x4E71, 0xC2D3, 0x63A0,	0xC2D4, 0x7565, 0xC2D5, 0x62A1, 0xC2D6, 0x8F6E, 0xC2D7, 0x4F26,
+	0xC2D8, 0x4ED1, 0xC2D9, 0x6CA6, 0xC2DA, 0x7EB6, 0xC2DB, 0x8BBA,	0xC2DC, 0x841D, 0xC2DD, 0x87BA, 0xC2DE, 0x7F57, 0xC2DF, 0x903B,
+	0xC2E0, 0x9523, 0xC2E1, 0x7BA9, 0xC2E2, 0x9AA1, 0xC2E3, 0x88F8,	0xC2E4, 0x843D, 0xC2E5, 0x6D1B, 0xC2E6, 0x9A86, 0xC2E7, 0x7EDC,
+	0xC2E8, 0x5988, 0xC2E9, 0x9EBB, 0xC2EA, 0x739B, 0xC2EB, 0x7801,	0xC2EC, 0x8682, 0xC2ED, 0x9A6C, 0xC2EE, 0x9A82, 0xC2EF, 0x561B,
+	0xC2F0, 0x5417, 0xC2F1, 0x57CB, 0xC2F2, 0x4E70, 0xC2F3, 0x9EA6,	0xC2F4, 0x5356, 0xC2F5, 0x8FC8, 0xC2F6, 0x8109, 0xC2F7, 0x7792,
+	0xC2F8, 0x9992, 0xC2F9, 0x86EE, 0xC2FA, 0x6EE1, 0xC2FB, 0x8513,	0xC2FC, 0x66FC, 0xC2FD, 0x6162, 0xC2FE, 0x6F2B, 0xC340, 0x807E,
+	0xC341, 0x8081, 0xC342, 0x8082, 0xC343, 0x8085, 0xC344, 0x8088,	0xC345, 0x808A, 0xC346, 0x808D, 0xC347, 0x808E, 0xC348, 0x808F,
+	0xC349, 0x8090, 0xC34A, 0x8091, 0xC34B, 0x8092, 0xC34C, 0x8094,	0xC34D, 0x8095, 0xC34E, 0x8097, 0xC34F, 0x8099, 0xC350, 0x809E,
+	0xC351, 0x80A3, 0xC352, 0x80A6, 0xC353, 0x80A7, 0xC354, 0x80A8,	0xC355, 0x80AC, 0xC356, 0x80B0, 0xC357, 0x80B3, 0xC358, 0x80B5,
+	0xC359, 0x80B6, 0xC35A, 0x80B8, 0xC35B, 0x80B9, 0xC35C, 0x80BB,	0xC35D, 0x80C5, 0xC35E, 0x80C7, 0xC35F, 0x80C8, 0xC360, 0x80C9,
+	0xC361, 0x80CA, 0xC362, 0x80CB, 0xC363, 0x80CF, 0xC364, 0x80D0,	0xC365, 0x80D1, 0xC366, 0x80D2, 0xC367, 0x80D3, 0xC368, 0x80D4,
+	0xC369, 0x80D5, 0xC36A, 0x80D8, 0xC36B, 0x80DF, 0xC36C, 0x80E0,	0xC36D, 0x80E2, 0xC36E, 0x80E3, 0xC36F, 0x80E6, 0xC370, 0x80EE,
+	0xC371, 0x80F5, 0xC372, 0x80F7, 0xC373, 0x80F9, 0xC374, 0x80FB,	0xC375, 0x80FE, 0xC376, 0x80FF, 0xC377, 0x8100, 0xC378, 0x8101,
+	0xC379, 0x8103, 0xC37A, 0x8104, 0xC37B, 0x8105, 0xC37C, 0x8107,	0xC37D, 0x8108, 0xC37E, 0x810B, 0xC380, 0x810C, 0xC381, 0x8115,
+	0xC382, 0x8117, 0xC383, 0x8119, 0xC384, 0x811B, 0xC385, 0x811C,	0xC386, 0x811D, 0xC387, 0x811F, 0xC388, 0x8120, 0xC389, 0x8121,
+	0xC38A, 0x8122, 0xC38B, 0x8123, 0xC38C, 0x8124, 0xC38D, 0x8125,	0xC38E, 0x8126, 0xC38F, 0x8127, 0xC390, 0x8128, 0xC391, 0x8129,
+	0xC392, 0x812A, 0xC393, 0x812B, 0xC394, 0x812D, 0xC395, 0x812E,	0xC396, 0x8130, 0xC397, 0x8133, 0xC398, 0x8134, 0xC399, 0x8135,
+	0xC39A, 0x8137, 0xC39B, 0x8139, 0xC39C, 0x813A, 0xC39D, 0x813B,	0xC39E, 0x813C, 0xC39F, 0x813D, 0xC3A0, 0x813F, 0xC3A1, 0x8C29,
+	0xC3A2, 0x8292, 0xC3A3, 0x832B, 0xC3A4, 0x76F2, 0xC3A5, 0x6C13,	0xC3A6, 0x5FD9, 0xC3A7, 0x83BD, 0xC3A8, 0x732B, 0xC3A9, 0x8305,
+	0xC3AA, 0x951A, 0xC3AB, 0x6BDB, 0xC3AC, 0x77DB, 0xC3AD, 0x94C6,	0xC3AE, 0x536F, 0xC3AF, 0x8302, 0xC3B0, 0x5192, 0xC3B1, 0x5E3D,
+	0xC3B2, 0x8C8C, 0xC3B3, 0x8D38, 0xC3B4, 0x4E48, 0xC3B5, 0x73AB,	0xC3B6, 0x679A, 0xC3B7, 0x6885, 0xC3B8, 0x9176, 0xC3B9, 0x9709,
+	0xC3BA, 0x7164, 0xC3BB, 0x6CA1, 0xC3BC, 0x7709, 0xC3BD, 0x5A92,	0xC3BE, 0x9541, 0xC3BF, 0x6BCF, 0xC3C0, 0x7F8E, 0xC3C1, 0x6627,
+	0xC3C2, 0x5BD0, 0xC3C3, 0x59B9, 0xC3C4, 0x5A9A, 0xC3C5, 0x95E8,	0xC3C6, 0x95F7, 0xC3C7, 0x4EEC, 0xC3C8, 0x840C, 0xC3C9, 0x8499,
+	0xC3CA, 0x6AAC, 0xC3CB, 0x76DF, 0xC3CC, 0x9530, 0xC3CD, 0x731B,	0xC3CE, 0x68A6, 0xC3CF, 0x5B5F, 0xC3D0, 0x772F, 0xC3D1, 0x919A,
+	0xC3D2, 0x9761, 0xC3D3, 0x7CDC, 0xC3D4, 0x8FF7, 0xC3D5, 0x8C1C,	0xC3D6, 0x5F25, 0xC3D7, 0x7C73, 0xC3D8, 0x79D8, 0xC3D9, 0x89C5,
+	0xC3DA, 0x6CCC, 0xC3DB, 0x871C, 0xC3DC, 0x5BC6, 0xC3DD, 0x5E42,	0xC3DE, 0x68C9, 0xC3DF, 0x7720, 0xC3E0, 0x7EF5, 0xC3E1, 0x5195,
+	0xC3E2, 0x514D, 0xC3E3, 0x52C9, 0xC3E4, 0x5A29, 0xC3E5, 0x7F05,	0xC3E6, 0x9762, 0xC3E7, 0x82D7, 0xC3E8, 0x63CF, 0xC3E9, 0x7784,
+	0xC3EA, 0x85D0, 0xC3EB, 0x79D2, 0xC3EC, 0x6E3A, 0xC3ED, 0x5E99,	0xC3EE, 0x5999, 0xC3EF, 0x8511, 0xC3F0, 0x706D, 0xC3F1, 0x6C11,
+	0xC3F2, 0x62BF, 0xC3F3, 0x76BF, 0xC3F4, 0x654F, 0xC3F5, 0x60AF,	0xC3F6, 0x95FD, 0xC3F7, 0x660E, 0xC3F8, 0x879F, 0xC3F9, 0x9E23,
+	0xC3FA, 0x94ED, 0xC3FB, 0x540D, 0xC3FC, 0x547D, 0xC3FD, 0x8C2C,	0xC3FE, 0x6478, 0xC440, 0x8140, 0xC441, 0x8141, 0xC442, 0x8142,
+	0xC443, 0x8143, 0xC444, 0x8144, 0xC445, 0x8145, 0xC446, 0x8147,	0xC447, 0x8149, 0xC448, 0x814D, 0xC449, 0x814E, 0xC44A, 0x814F,
+	0xC44B, 0x8152, 0xC44C, 0x8156, 0xC44D, 0x8157, 0xC44E, 0x8158,	0xC44F, 0x815B, 0xC450, 0x815C, 0xC451, 0x815D, 0xC452, 0x815E,
+	0xC453, 0x815F, 0xC454, 0x8161, 0xC455, 0x8162, 0xC456, 0x8163,	0xC457, 0x8164, 0xC458, 0x8166, 0xC459, 0x8168, 0xC45A, 0x816A,
+	0xC45B, 0x816B, 0xC45C, 0x816C, 0xC45D, 0x816F, 0xC45E, 0x8172,	0xC45F, 0x8173, 0xC460, 0x8175, 0xC461, 0x8176, 0xC462, 0x8177,
+	0xC463, 0x8178, 0xC464, 0x8181, 0xC465, 0x8183, 0xC466, 0x8184,	0xC467, 0x8185, 0xC468, 0x8186, 0xC469, 0x8187, 0xC46A, 0x8189,
+	0xC46B, 0x818B, 0xC46C, 0x818C, 0xC46D, 0x818D, 0xC46E, 0x818E,	0xC46F, 0x8190, 0xC470, 0x8192, 0xC471, 0x8193, 0xC472, 0x8194,
+	0xC473, 0x8195, 0xC474, 0x8196, 0xC475, 0x8197, 0xC476, 0x8199,	0xC477, 0x819A, 0xC478, 0x819E, 0xC479, 0x819F, 0xC47A, 0x81A0,
+	0xC47B, 0x81A1, 0xC47C, 0x81A2, 0xC47D, 0x81A4, 0xC47E, 0x81A5,	0xC480, 0x81A7, 0xC481, 0x81A9, 0xC482, 0x81AB, 0xC483, 0x81AC,
+	0xC484, 0x81AD, 0xC485, 0x81AE, 0xC486, 0x81AF, 0xC487, 0x81B0,	0xC488, 0x81B1, 0xC489, 0x81B2, 0xC48A, 0x81B4, 0xC48B, 0x81B5,
+	0xC48C, 0x81B6, 0xC48D, 0x81B7, 0xC48E, 0x81B8, 0xC48F, 0x81B9,	0xC490, 0x81BC, 0xC491, 0x81BD, 0xC492, 0x81BE, 0xC493, 0x81BF,
+	0xC494, 0x81C4, 0xC495, 0x81C5, 0xC496, 0x81C7, 0xC497, 0x81C8,	0xC498, 0x81C9, 0xC499, 0x81CB, 0xC49A, 0x81CD, 0xC49B, 0x81CE,
+	0xC49C, 0x81CF, 0xC49D, 0x81D0, 0xC49E, 0x81D1, 0xC49F, 0x81D2,	0xC4A0, 0x81D3, 0xC4A1, 0x6479, 0xC4A2, 0x8611, 0xC4A3, 0x6A21,
+	0xC4A4, 0x819C, 0xC4A5, 0x78E8, 0xC4A6, 0x6469, 0xC4A7, 0x9B54,	0xC4A8, 0x62B9, 0xC4A9, 0x672B, 0xC4AA, 0x83AB, 0xC4AB, 0x58A8,
+	0xC4AC, 0x9ED8, 0xC4AD, 0x6CAB, 0xC4AE, 0x6F20, 0xC4AF, 0x5BDE,	0xC4B0, 0x964C, 0xC4B1, 0x8C0B, 0xC4B2, 0x725F, 0xC4B3, 0x67D0,
+	0xC4B4, 0x62C7, 0xC4B5, 0x7261, 0xC4B6, 0x4EA9, 0xC4B7, 0x59C6,	0xC4B8, 0x6BCD, 0xC4B9, 0x5893, 0xC4BA, 0x66AE, 0xC4BB, 0x5E55,
+	0xC4BC, 0x52DF, 0xC4BD, 0x6155, 0xC4BE, 0x6728, 0xC4BF, 0x76EE,	0xC4C0, 0x7766, 0xC4C1, 0x7267, 0xC4C2, 0x7A46, 0xC4C3, 0x62FF,
+	0xC4C4, 0x54EA, 0xC4C5, 0x5450, 0xC4C6, 0x94A0, 0xC4C7, 0x90A3,	0xC4C8, 0x5A1C, 0xC4C9, 0x7EB3, 0xC4CA, 0x6C16, 0xC4CB, 0x4E43,
+	0xC4CC, 0x5976, 0xC4CD, 0x8010, 0xC4CE, 0x5948, 0xC4CF, 0x5357,	0xC4D0, 0x7537, 0xC4D1, 0x96BE, 0xC4D2, 0x56CA, 0xC4D3, 0x6320,
+	0xC4D4, 0x8111, 0xC4D5, 0x607C, 0xC4D6, 0x95F9, 0xC4D7, 0x6DD6,	0xC4D8, 0x5462, 0xC4D9, 0x9981, 0xC4DA, 0x5185, 0xC4DB, 0x5AE9,
+	0xC4DC, 0x80FD, 0xC4DD, 0x59AE, 0xC4DE, 0x9713, 0xC4DF, 0x502A,	0xC4E0, 0x6CE5, 0xC4E1, 0x5C3C, 0xC4E2, 0x62DF, 0xC4E3, 0x4F60,
+	0xC4E4, 0x533F, 0xC4E5, 0x817B, 0xC4E6, 0x9006, 0xC4E7, 0x6EBA,	0xC4E8, 0x852B, 0xC4E9, 0x62C8, 0xC4EA, 0x5E74, 0xC4EB, 0x78BE,
+	0xC4EC, 0x64B5, 0xC4ED, 0x637B, 0xC4EE, 0x5FF5, 0xC4EF, 0x5A18,	0xC4F0, 0x917F, 0xC4F1, 0x9E1F, 0xC4F2, 0x5C3F, 0xC4F3, 0x634F,
+	0xC4F4, 0x8042, 0xC4F5, 0x5B7D, 0xC4F6, 0x556E, 0xC4F7, 0x954A,	0xC4F8, 0x954D, 0xC4F9, 0x6D85, 0xC4FA, 0x60A8, 0xC4FB, 0x67E0,
+	0xC4FC, 0x72DE, 0xC4FD, 0x51DD, 0xC4FE, 0x5B81, 0xC540, 0x81D4,	0xC541, 0x81D5, 0xC542, 0x81D6, 0xC543, 0x81D7, 0xC544, 0x81D8,
+	0xC545, 0x81D9, 0xC546, 0x81DA, 0xC547, 0x81DB, 0xC548, 0x81DC,	0xC549, 0x81DD, 0xC54A, 0x81DE, 0xC54B, 0x81DF, 0xC54C, 0x81E0,
+	0xC54D, 0x81E1, 0xC54E, 0x81E2, 0xC54F, 0x81E4, 0xC550, 0x81E5,	0xC551, 0x81E6, 0xC552, 0x81E8, 0xC553, 0x81E9, 0xC554, 0x81EB,
+	0xC555, 0x81EE, 0xC556, 0x81EF, 0xC557, 0x81F0, 0xC558, 0x81F1,	0xC559, 0x81F2, 0xC55A, 0x81F5, 0xC55B, 0x81F6, 0xC55C, 0x81F7,
+	0xC55D, 0x81F8, 0xC55E, 0x81F9, 0xC55F, 0x81FA, 0xC560, 0x81FD,	0xC561, 0x81FF, 0xC562, 0x8203, 0xC563, 0x8207, 0xC564, 0x8208,
+	0xC565, 0x8209, 0xC566, 0x820A, 0xC567, 0x820B, 0xC568, 0x820E,	0xC569, 0x820F, 0xC56A, 0x8211, 0xC56B, 0x8213, 0xC56C, 0x8215,
+	0xC56D, 0x8216, 0xC56E, 0x8217, 0xC56F, 0x8218, 0xC570, 0x8219,	0xC571, 0x821A, 0xC572, 0x821D, 0xC573, 0x8220, 0xC574, 0x8224,
+	0xC575, 0x8225, 0xC576, 0x8226, 0xC577, 0x8227, 0xC578, 0x8229,	0xC579, 0x822E, 0xC57A, 0x8232, 0xC57B, 0x823A, 0xC57C, 0x823C,
+	0xC57D, 0x823D, 0xC57E, 0x823F, 0xC580, 0x8240, 0xC581, 0x8241,	0xC582, 0x8242, 0xC583, 0x8243, 0xC584, 0x8245, 0xC585, 0x8246,
+	0xC586, 0x8248, 0xC587, 0x824A, 0xC588, 0x824C, 0xC589, 0x824D,	0xC58A, 0x824E, 0xC58B, 0x8250, 0xC58C, 0x8251, 0xC58D, 0x8252,
+	0xC58E, 0x8253, 0xC58F, 0x8254, 0xC590, 0x8255, 0xC591, 0x8256,	0xC592, 0x8257, 0xC593, 0x8259, 0xC594, 0x825B, 0xC595, 0x825C,
+	0xC596, 0x825D, 0xC597, 0x825E, 0xC598, 0x8260, 0xC599, 0x8261,	0xC59A, 0x8262, 0xC59B, 0x8263, 0xC59C, 0x8264, 0xC59D, 0x8265,
+	0xC59E, 0x8266, 0xC59F, 0x8267, 0xC5A0, 0x8269, 0xC5A1, 0x62E7,	0xC5A2, 0x6CDE, 0xC5A3, 0x725B, 0xC5A4, 0x626D, 0xC5A5, 0x94AE,
+	0xC5A6, 0x7EBD, 0xC5A7, 0x8113, 0xC5A8, 0x6D53, 0xC5A9, 0x519C,	0xC5AA, 0x5F04, 0xC5AB, 0x5974, 0xC5AC, 0x52AA, 0xC5AD, 0x6012,
+	0xC5AE, 0x5973, 0xC5AF, 0x6696, 0xC5B0, 0x8650, 0xC5B1, 0x759F,	0xC5B2, 0x632A, 0xC5B3, 0x61E6, 0xC5B4, 0x7CEF, 0xC5B5, 0x8BFA,
+	0xC5B6, 0x54E6, 0xC5B7, 0x6B27, 0xC5B8, 0x9E25, 0xC5B9, 0x6BB4,	0xC5BA, 0x85D5, 0xC5BB, 0x5455, 0xC5BC, 0x5076, 0xC5BD, 0x6CA4,
+	0xC5BE, 0x556A, 0xC5BF, 0x8DB4, 0xC5C0, 0x722C, 0xC5C1, 0x5E15,	0xC5C2, 0x6015, 0xC5C3, 0x7436, 0xC5C4, 0x62CD, 0xC5C5, 0x6392,
+	0xC5C6, 0x724C, 0xC5C7, 0x5F98, 0xC5C8, 0x6E43, 0xC5C9, 0x6D3E,	0xC5CA, 0x6500, 0xC5CB, 0x6F58, 0xC5CC, 0x76D8, 0xC5CD, 0x78D0,
+	0xC5CE, 0x76FC, 0xC5CF, 0x7554, 0xC5D0, 0x5224, 0xC5D1, 0x53DB,	0xC5D2, 0x4E53, 0xC5D3, 0x5E9E, 0xC5D4, 0x65C1, 0xC5D5, 0x802A,
+	0xC5D6, 0x80D6, 0xC5D7, 0x629B, 0xC5D8, 0x5486, 0xC5D9, 0x5228,	0xC5DA, 0x70AE, 0xC5DB, 0x888D, 0xC5DC, 0x8DD1, 0xC5DD, 0x6CE1,
+	0xC5DE, 0x5478, 0xC5DF, 0x80DA, 0xC5E0, 0x57F9, 0xC5E1, 0x88F4,	0xC5E2, 0x8D54, 0xC5E3, 0x966A, 0xC5E4, 0x914D, 0xC5E5, 0x4F69,
+	0xC5E6, 0x6C9B, 0xC5E7, 0x55B7, 0xC5E8, 0x76C6, 0xC5E9, 0x7830,	0xC5EA, 0x62A8, 0xC5EB, 0x70F9, 0xC5EC, 0x6F8E, 0xC5ED, 0x5F6D,
+	0xC5EE, 0x84EC, 0xC5EF, 0x68DA, 0xC5F0, 0x787C, 0xC5F1, 0x7BF7,	0xC5F2, 0x81A8, 0xC5F3, 0x670B, 0xC5F4, 0x9E4F, 0xC5F5, 0x6367,
+	0xC5F6, 0x78B0, 0xC5F7, 0x576F, 0xC5F8, 0x7812, 0xC5F9, 0x9739,	0xC5FA, 0x6279, 0xC5FB, 0x62AB, 0xC5FC, 0x5288, 0xC5FD, 0x7435,
+	0xC5FE, 0x6BD7, 0xC640, 0x826A, 0xC641, 0x826B, 0xC642, 0x826C,	0xC643, 0x826D, 0xC644, 0x8271, 0xC645, 0x8275, 0xC646, 0x8276,
+	0xC647, 0x8277, 0xC648, 0x8278, 0xC649, 0x827B, 0xC64A, 0x827C,	0xC64B, 0x8280, 0xC64C, 0x8281, 0xC64D, 0x8283, 0xC64E, 0x8285,
+	0xC64F, 0x8286, 0xC650, 0x8287, 0xC651, 0x8289, 0xC652, 0x828C,	0xC653, 0x8290, 0xC654, 0x8293, 0xC655, 0x8294, 0xC656, 0x8295,
+	0xC657, 0x8296, 0xC658, 0x829A, 0xC659, 0x829B, 0xC65A, 0x829E,	0xC65B, 0x82A0, 0xC65C, 0x82A2, 0xC65D, 0x82A3, 0xC65E, 0x82A7,
+	0xC65F, 0x82B2, 0xC660, 0x82B5, 0xC661, 0x82B6, 0xC662, 0x82BA,	0xC663, 0x82BB, 0xC664, 0x82BC, 0xC665, 0x82BF, 0xC666, 0x82C0,
+	0xC667, 0x82C2, 0xC668, 0x82C3, 0xC669, 0x82C5, 0xC66A, 0x82C6,	0xC66B, 0x82C9, 0xC66C, 0x82D0, 0xC66D, 0x82D6, 0xC66E, 0x82D9,
+	0xC66F, 0x82DA, 0xC670, 0x82DD, 0xC671, 0x82E2, 0xC672, 0x82E7,	0xC673, 0x82E8, 0xC674, 0x82E9, 0xC675, 0x82EA, 0xC676, 0x82EC,
+	0xC677, 0x82ED, 0xC678, 0x82EE, 0xC679, 0x82F0, 0xC67A, 0x82F2,	0xC67B, 0x82F3, 0xC67C, 0x82F5, 0xC67D, 0x82F6, 0xC67E, 0x82F8,
+	0xC680, 0x82FA, 0xC681, 0x82FC, 0xC682, 0x82FD, 0xC683, 0x82FE,	0xC684, 0x82FF, 0xC685, 0x8300, 0xC686, 0x830A, 0xC687, 0x830B,
+	0xC688, 0x830D, 0xC689, 0x8310, 0xC68A, 0x8312, 0xC68B, 0x8313,	0xC68C, 0x8316, 0xC68D, 0x8318, 0xC68E, 0x8319, 0xC68F, 0x831D,
+	0xC690, 0x831E, 0xC691, 0x831F, 0xC692, 0x8320, 0xC693, 0x8321,	0xC694, 0x8322, 0xC695, 0x8323, 0xC696, 0x8324, 0xC697, 0x8325,
+	0xC698, 0x8326, 0xC699, 0x8329, 0xC69A, 0x832A, 0xC69B, 0x832E,	0xC69C, 0x8330, 0xC69D, 0x8332, 0xC69E, 0x8337, 0xC69F, 0x833B,
+	0xC6A0, 0x833D, 0xC6A1, 0x5564, 0xC6A2, 0x813E, 0xC6A3, 0x75B2,	0xC6A4, 0x76AE, 0xC6A5, 0x5339, 0xC6A6, 0x75DE, 0xC6A7, 0x50FB,
+	0xC6A8, 0x5C41, 0xC6A9, 0x8B6C, 0xC6AA, 0x7BC7, 0xC6AB, 0x504F,	0xC6AC, 0x7247, 0xC6AD, 0x9A97, 0xC6AE, 0x98D8, 0xC6AF, 0x6F02,
+	0xC6B0, 0x74E2, 0xC6B1, 0x7968, 0xC6B2, 0x6487, 0xC6B3, 0x77A5,	0xC6B4, 0x62FC, 0xC6B5, 0x9891, 0xC6B6, 0x8D2B, 0xC6B7, 0x54C1,
+	0xC6B8, 0x8058, 0xC6B9, 0x4E52, 0xC6BA, 0x576A, 0xC6BB, 0x82F9,	0xC6BC, 0x840D, 0xC6BD, 0x5E73, 0xC6BE, 0x51ED, 0xC6BF, 0x74F6,
+	0xC6C0, 0x8BC4, 0xC6C1, 0x5C4F, 0xC6C2, 0x5761, 0xC6C3, 0x6CFC,	0xC6C4, 0x9887, 0xC6C5, 0x5A46, 0xC6C6, 0x7834, 0xC6C7, 0x9B44,
+	0xC6C8, 0x8FEB, 0xC6C9, 0x7C95, 0xC6CA, 0x5256, 0xC6CB, 0x6251,	0xC6CC, 0x94FA, 0xC6CD, 0x4EC6, 0xC6CE, 0x8386, 0xC6CF, 0x8461,
+	0xC6D0, 0x83E9, 0xC6D1, 0x84B2, 0xC6D2, 0x57D4, 0xC6D3, 0x6734,	0xC6D4, 0x5703, 0xC6D5, 0x666E, 0xC6D6, 0x6D66, 0xC6D7, 0x8C31,
+	0xC6D8, 0x66DD, 0xC6D9, 0x7011, 0xC6DA, 0x671F, 0xC6DB, 0x6B3A,	0xC6DC, 0x6816, 0xC6DD, 0x621A, 0xC6DE, 0x59BB, 0xC6DF, 0x4E03,
+	0xC6E0, 0x51C4, 0xC6E1, 0x6F06, 0xC6E2, 0x67D2, 0xC6E3, 0x6C8F,	0xC6E4, 0x5176, 0xC6E5, 0x68CB, 0xC6E6, 0x5947, 0xC6E7, 0x6B67,
+	0xC6E8, 0x7566, 0xC6E9, 0x5D0E, 0xC6EA, 0x8110, 0xC6EB, 0x9F50,	0xC6EC, 0x65D7, 0xC6ED, 0x7948, 0xC6EE, 0x7941, 0xC6EF, 0x9A91,
+	0xC6F0, 0x8D77, 0xC6F1, 0x5C82, 0xC6F2, 0x4E5E, 0xC6F3, 0x4F01,	0xC6F4, 0x542F, 0xC6F5, 0x5951, 0xC6F6, 0x780C, 0xC6F7, 0x5668,
+	0xC6F8, 0x6C14, 0xC6F9, 0x8FC4, 0xC6FA, 0x5F03, 0xC6FB, 0x6C7D,	0xC6FC, 0x6CE3, 0xC6FD, 0x8BAB, 0xC6FE, 0x6390, 0xC740, 0x833E,
+	0xC741, 0x833F, 0xC742, 0x8341, 0xC743, 0x8342, 0xC744, 0x8344,	0xC745, 0x8345, 0xC746, 0x8348, 0xC747, 0x834A, 0xC748, 0x834B,
+	0xC749, 0x834C, 0xC74A, 0x834D, 0xC74B, 0x834E, 0xC74C, 0x8353,	0xC74D, 0x8355, 0xC74E, 0x8356, 0xC74F, 0x8357, 0xC750, 0x8358,
+	0xC751, 0x8359, 0xC752, 0x835D, 0xC753, 0x8362, 0xC754, 0x8370,	0xC755, 0x8371, 0xC756, 0x8372, 0xC757, 0x8373, 0xC758, 0x8374,
+	0xC759, 0x8375, 0xC75A, 0x8376, 0xC75B, 0x8379, 0xC75C, 0x837A,	0xC75D, 0x837E, 0xC75E, 0x837F, 0xC75F, 0x8380, 0xC760, 0x8381,
+	0xC761, 0x8382, 0xC762, 0x8383, 0xC763, 0x8384, 0xC764, 0x8387,	0xC765, 0x8388, 0xC766, 0x838A, 0xC767, 0x838B, 0xC768, 0x838C,
+	0xC769, 0x838D, 0xC76A, 0x838F, 0xC76B, 0x8390, 0xC76C, 0x8391,	0xC76D, 0x8394, 0xC76E, 0x8395, 0xC76F, 0x8396, 0xC770, 0x8397,
+	0xC771, 0x8399, 0xC772, 0x839A, 0xC773, 0x839D, 0xC774, 0x839F,	0xC775, 0x83A1, 0xC776, 0x83A2, 0xC777, 0x83A3, 0xC778, 0x83A4,
+	0xC779, 0x83A5, 0xC77A, 0x83A6, 0xC77B, 0x83A7, 0xC77C, 0x83AC,	0xC77D, 0x83AD, 0xC77E, 0x83AE, 0xC780, 0x83AF, 0xC781, 0x83B5,
+	0xC782, 0x83BB, 0xC783, 0x83BE, 0xC784, 0x83BF, 0xC785, 0x83C2,	0xC786, 0x83C3, 0xC787, 0x83C4, 0xC788, 0x83C6, 0xC789, 0x83C8,
+	0xC78A, 0x83C9, 0xC78B, 0x83CB, 0xC78C, 0x83CD, 0xC78D, 0x83CE,	0xC78E, 0x83D0, 0xC78F, 0x83D1, 0xC790, 0x83D2, 0xC791, 0x83D3,
+	0xC792, 0x83D5, 0xC793, 0x83D7, 0xC794, 0x83D9, 0xC795, 0x83DA,	0xC796, 0x83DB, 0xC797, 0x83DE, 0xC798, 0x83E2, 0xC799, 0x83E3,
+	0xC79A, 0x83E4, 0xC79B, 0x83E6, 0xC79C, 0x83E7, 0xC79D, 0x83E8,	0xC79E, 0x83EB, 0xC79F, 0x83EC, 0xC7A0, 0x83ED, 0xC7A1, 0x6070,
+	0xC7A2, 0x6D3D, 0xC7A3, 0x7275, 0xC7A4, 0x6266, 0xC7A5, 0x948E,	0xC7A6, 0x94C5, 0xC7A7, 0x5343, 0xC7A8, 0x8FC1, 0xC7A9, 0x7B7E,
+	0xC7AA, 0x4EDF, 0xC7AB, 0x8C26, 0xC7AC, 0x4E7E, 0xC7AD, 0x9ED4,	0xC7AE, 0x94B1, 0xC7AF, 0x94B3, 0xC7B0, 0x524D, 0xC7B1, 0x6F5C,
+	0xC7B2, 0x9063, 0xC7B3, 0x6D45, 0xC7B4, 0x8C34, 0xC7B5, 0x5811,	0xC7B6, 0x5D4C, 0xC7B7, 0x6B20, 0xC7B8, 0x6B49, 0xC7B9, 0x67AA,
+	0xC7BA, 0x545B, 0xC7BB, 0x8154, 0xC7BC, 0x7F8C, 0xC7BD, 0x5899,	0xC7BE, 0x8537, 0xC7BF, 0x5F3A, 0xC7C0, 0x62A2, 0xC7C1, 0x6A47,
+	0xC7C2, 0x9539, 0xC7C3, 0x6572, 0xC7C4, 0x6084, 0xC7C5, 0x6865,	0xC7C6, 0x77A7, 0xC7C7, 0x4E54, 0xC7C8, 0x4FA8, 0xC7C9, 0x5DE7,
+	0xC7CA, 0x9798, 0xC7CB, 0x64AC, 0xC7CC, 0x7FD8, 0xC7CD, 0x5CED,	0xC7CE, 0x4FCF, 0xC7CF, 0x7A8D, 0xC7D0, 0x5207, 0xC7D1, 0x8304,
+	0xC7D2, 0x4E14, 0xC7D3, 0x602F, 0xC7D4, 0x7A83, 0xC7D5, 0x94A6,	0xC7D6, 0x4FB5, 0xC7D7, 0x4EB2, 0xC7D8, 0x79E6, 0xC7D9, 0x7434,
+	0xC7DA, 0x52E4, 0xC7DB, 0x82B9, 0xC7DC, 0x64D2, 0xC7DD, 0x79BD,	0xC7DE, 0x5BDD, 0xC7DF, 0x6C81, 0xC7E0, 0x9752, 0xC7E1, 0x8F7B,
+	0xC7E2, 0x6C22, 0xC7E3, 0x503E, 0xC7E4, 0x537F, 0xC7E5, 0x6E05,	0xC7E6, 0x64CE, 0xC7E7, 0x6674, 0xC7E8, 0x6C30, 0xC7E9, 0x60C5,
+	0xC7EA, 0x9877, 0xC7EB, 0x8BF7, 0xC7EC, 0x5E86, 0xC7ED, 0x743C,	0xC7EE, 0x7A77, 0xC7EF, 0x79CB, 0xC7F0, 0x4E18, 0xC7F1, 0x90B1,
+	0xC7F2, 0x7403, 0xC7F3, 0x6C42, 0xC7F4, 0x56DA, 0xC7F5, 0x914B,	0xC7F6, 0x6CC5, 0xC7F7, 0x8D8B, 0xC7F8, 0x533A, 0xC7F9, 0x86C6,
+	0xC7FA, 0x66F2, 0xC7FB, 0x8EAF, 0xC7FC, 0x5C48, 0xC7FD, 0x9A71,	0xC7FE, 0x6E20, 0xC840, 0x83EE, 0xC841, 0x83EF, 0xC842, 0x83F3,
+	0xC843, 0x83F4, 0xC844, 0x83F5, 0xC845, 0x83F6, 0xC846, 0x83F7,	0xC847, 0x83FA, 0xC848, 0x83FB, 0xC849, 0x83FC, 0xC84A, 0x83FE,
+	0xC84B, 0x83FF, 0xC84C, 0x8400, 0xC84D, 0x8402, 0xC84E, 0x8405,	0xC84F, 0x8407, 0xC850, 0x8408, 0xC851, 0x8409, 0xC852, 0x840A,
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+	0xCF92, 0x880F, 0xCF93, 0x8810, 0xCF94, 0x8811, 0xCF95, 0x8812,	0xCF96, 0x8814, 0xCF97, 0x8817, 0xCF98, 0x8818, 0xCF99, 0x8819,
+	0xCF9A, 0x881A, 0xCF9B, 0x881C, 0xCF9C, 0x881D, 0xCF9D, 0x881E,	0xCF9E, 0x881F, 0xCF9F, 0x8820, 0xCFA0, 0x8823, 0xCFA1, 0x7A00,
+	0xCFA2, 0x606F, 0xCFA3, 0x5E0C, 0xCFA4, 0x6089, 0xCFA5, 0x819D,	0xCFA6, 0x5915, 0xCFA7, 0x60DC, 0xCFA8, 0x7184, 0xCFA9, 0x70EF,
+	0xCFAA, 0x6EAA, 0xCFAB, 0x6C50, 0xCFAC, 0x7280, 0xCFAD, 0x6A84,	0xCFAE, 0x88AD, 0xCFAF, 0x5E2D, 0xCFB0, 0x4E60, 0xCFB1, 0x5AB3,
+	0xCFB2, 0x559C, 0xCFB3, 0x94E3, 0xCFB4, 0x6D17, 0xCFB5, 0x7CFB,	0xCFB6, 0x9699, 0xCFB7, 0x620F, 0xCFB8, 0x7EC6, 0xCFB9, 0x778E,
+	0xCFBA, 0x867E, 0xCFBB, 0x5323, 0xCFBC, 0x971E, 0xCFBD, 0x8F96,	0xCFBE, 0x6687, 0xCFBF, 0x5CE1, 0xCFC0, 0x4FA0, 0xCFC1, 0x72ED,
+	0xCFC2, 0x4E0B, 0xCFC3, 0x53A6, 0xCFC4, 0x590F, 0xCFC5, 0x5413,	0xCFC6, 0x6380, 0xCFC7, 0x9528, 0xCFC8, 0x5148, 0xCFC9, 0x4ED9,
+	0xCFCA, 0x9C9C, 0xCFCB, 0x7EA4, 0xCFCC, 0x54B8, 0xCFCD, 0x8D24,	0xCFCE, 0x8854, 0xCFCF, 0x8237, 0xCFD0, 0x95F2, 0xCFD1, 0x6D8E,
+	0xCFD2, 0x5F26, 0xCFD3, 0x5ACC, 0xCFD4, 0x663E, 0xCFD5, 0x9669,	0xCFD6, 0x73B0, 0xCFD7, 0x732E, 0xCFD8, 0x53BF, 0xCFD9, 0x817A,
+	0xCFDA, 0x9985, 0xCFDB, 0x7FA1, 0xCFDC, 0x5BAA, 0xCFDD, 0x9677,	0xCFDE, 0x9650, 0xCFDF, 0x7EBF, 0xCFE0, 0x76F8, 0xCFE1, 0x53A2,
+	0xCFE2, 0x9576, 0xCFE3, 0x9999, 0xCFE4, 0x7BB1, 0xCFE5, 0x8944,	0xCFE6, 0x6E58, 0xCFE7, 0x4E61, 0xCFE8, 0x7FD4, 0xCFE9, 0x7965,
+	0xCFEA, 0x8BE6, 0xCFEB, 0x60F3, 0xCFEC, 0x54CD, 0xCFED, 0x4EAB,	0xCFEE, 0x9879, 0xCFEF, 0x5DF7, 0xCFF0, 0x6A61, 0xCFF1, 0x50CF,
+	0xCFF2, 0x5411, 0xCFF3, 0x8C61, 0xCFF4, 0x8427, 0xCFF5, 0x785D,	0xCFF6, 0x9704, 0xCFF7, 0x524A, 0xCFF8, 0x54EE, 0xCFF9, 0x56A3,
+	0xCFFA, 0x9500, 0xCFFB, 0x6D88, 0xCFFC, 0x5BB5, 0xCFFD, 0x6DC6,	0xCFFE, 0x6653, 0xD040, 0x8824, 0xD041, 0x8825, 0xD042, 0x8826,
+	0xD043, 0x8827, 0xD044, 0x8828, 0xD045, 0x8829, 0xD046, 0x882A,	0xD047, 0x882B, 0xD048, 0x882C, 0xD049, 0x882D, 0xD04A, 0x882E,
+	0xD04B, 0x882F, 0xD04C, 0x8830, 0xD04D, 0x8831, 0xD04E, 0x8833,	0xD04F, 0x8834, 0xD050, 0x8835, 0xD051, 0x8836, 0xD052, 0x8837,
+	0xD053, 0x8838, 0xD054, 0x883A, 0xD055, 0x883B, 0xD056, 0x883D,	0xD057, 0x883E, 0xD058, 0x883F, 0xD059, 0x8841, 0xD05A, 0x8842,
+	0xD05B, 0x8843, 0xD05C, 0x8846, 0xD05D, 0x8847, 0xD05E, 0x8848,	0xD05F, 0x8849, 0xD060, 0x884A, 0xD061, 0x884B, 0xD062, 0x884E,
+	0xD063, 0x884F, 0xD064, 0x8850, 0xD065, 0x8851, 0xD066, 0x8852,	0xD067, 0x8853, 0xD068, 0x8855, 0xD069, 0x8856, 0xD06A, 0x8858,
+	0xD06B, 0x885A, 0xD06C, 0x885B, 0xD06D, 0x885C, 0xD06E, 0x885D,	0xD06F, 0x885E, 0xD070, 0x885F, 0xD071, 0x8860, 0xD072, 0x8866,
+	0xD073, 0x8867, 0xD074, 0x886A, 0xD075, 0x886D, 0xD076, 0x886F,	0xD077, 0x8871, 0xD078, 0x8873, 0xD079, 0x8874, 0xD07A, 0x8875,
+	0xD07B, 0x8876, 0xD07C, 0x8878, 0xD07D, 0x8879, 0xD07E, 0x887A,	0xD080, 0x887B, 0xD081, 0x887C, 0xD082, 0x8880, 0xD083, 0x8883,
+	0xD084, 0x8886, 0xD085, 0x8887, 0xD086, 0x8889, 0xD087, 0x888A,	0xD088, 0x888C, 0xD089, 0x888E, 0xD08A, 0x888F, 0xD08B, 0x8890,
+	0xD08C, 0x8891, 0xD08D, 0x8893, 0xD08E, 0x8894, 0xD08F, 0x8895,	0xD090, 0x8897, 0xD091, 0x8898, 0xD092, 0x8899, 0xD093, 0x889A,
+	0xD094, 0x889B, 0xD095, 0x889D, 0xD096, 0x889E, 0xD097, 0x889F,	0xD098, 0x88A0, 0xD099, 0x88A1, 0xD09A, 0x88A3, 0xD09B, 0x88A5,
+	0xD09C, 0x88A6, 0xD09D, 0x88A7, 0xD09E, 0x88A8, 0xD09F, 0x88A9,	0xD0A0, 0x88AA, 0xD0A1, 0x5C0F, 0xD0A2, 0x5B5D, 0xD0A3, 0x6821,
+	0xD0A4, 0x8096, 0xD0A5, 0x5578, 0xD0A6, 0x7B11, 0xD0A7, 0x6548,	0xD0A8, 0x6954, 0xD0A9, 0x4E9B, 0xD0AA, 0x6B47, 0xD0AB, 0x874E,
+	0xD0AC, 0x978B, 0xD0AD, 0x534F, 0xD0AE, 0x631F, 0xD0AF, 0x643A,	0xD0B0, 0x90AA, 0xD0B1, 0x659C, 0xD0B2, 0x80C1, 0xD0B3, 0x8C10,
+	0xD0B4, 0x5199, 0xD0B5, 0x68B0, 0xD0B6, 0x5378, 0xD0B7, 0x87F9,	0xD0B8, 0x61C8, 0xD0B9, 0x6CC4, 0xD0BA, 0x6CFB, 0xD0BB, 0x8C22,
+	0xD0BC, 0x5C51, 0xD0BD, 0x85AA, 0xD0BE, 0x82AF, 0xD0BF, 0x950C,	0xD0C0, 0x6B23, 0xD0C1, 0x8F9B, 0xD0C2, 0x65B0, 0xD0C3, 0x5FFB,
+	0xD0C4, 0x5FC3, 0xD0C5, 0x4FE1, 0xD0C6, 0x8845, 0xD0C7, 0x661F,	0xD0C8, 0x8165, 0xD0C9, 0x7329, 0xD0CA, 0x60FA, 0xD0CB, 0x5174,
+	0xD0CC, 0x5211, 0xD0CD, 0x578B, 0xD0CE, 0x5F62, 0xD0CF, 0x90A2,	0xD0D0, 0x884C, 0xD0D1, 0x9192, 0xD0D2, 0x5E78, 0xD0D3, 0x674F,
+	0xD0D4, 0x6027, 0xD0D5, 0x59D3, 0xD0D6, 0x5144, 0xD0D7, 0x51F6,	0xD0D8, 0x80F8, 0xD0D9, 0x5308, 0xD0DA, 0x6C79, 0xD0DB, 0x96C4,
+	0xD0DC, 0x718A, 0xD0DD, 0x4F11, 0xD0DE, 0x4FEE, 0xD0DF, 0x7F9E,	0xD0E0, 0x673D, 0xD0E1, 0x55C5, 0xD0E2, 0x9508, 0xD0E3, 0x79C0,
+	0xD0E4, 0x8896, 0xD0E5, 0x7EE3, 0xD0E6, 0x589F, 0xD0E7, 0x620C,	0xD0E8, 0x9700, 0xD0E9, 0x865A, 0xD0EA, 0x5618, 0xD0EB, 0x987B,
+	0xD0EC, 0x5F90, 0xD0ED, 0x8BB8, 0xD0EE, 0x84C4, 0xD0EF, 0x9157,	0xD0F0, 0x53D9, 0xD0F1, 0x65ED, 0xD0F2, 0x5E8F, 0xD0F3, 0x755C,
+	0xD0F4, 0x6064, 0xD0F5, 0x7D6E, 0xD0F6, 0x5A7F, 0xD0F7, 0x7EEA,	0xD0F8, 0x7EED, 0xD0F9, 0x8F69, 0xD0FA, 0x55A7, 0xD0FB, 0x5BA3,
+	0xD0FC, 0x60AC, 0xD0FD, 0x65CB, 0xD0FE, 0x7384, 0xD140, 0x88AC,	0xD141, 0x88AE, 0xD142, 0x88AF, 0xD143, 0x88B0, 0xD144, 0x88B2,
+	0xD145, 0x88B3, 0xD146, 0x88B4, 0xD147, 0x88B5, 0xD148, 0x88B6,	0xD149, 0x88B8, 0xD14A, 0x88B9, 0xD14B, 0x88BA, 0xD14C, 0x88BB,
+	0xD14D, 0x88BD, 0xD14E, 0x88BE, 0xD14F, 0x88BF, 0xD150, 0x88C0,	0xD151, 0x88C3, 0xD152, 0x88C4, 0xD153, 0x88C7, 0xD154, 0x88C8,
+	0xD155, 0x88CA, 0xD156, 0x88CB, 0xD157, 0x88CC, 0xD158, 0x88CD,	0xD159, 0x88CF, 0xD15A, 0x88D0, 0xD15B, 0x88D1, 0xD15C, 0x88D3,
+	0xD15D, 0x88D6, 0xD15E, 0x88D7, 0xD15F, 0x88DA, 0xD160, 0x88DB,	0xD161, 0x88DC, 0xD162, 0x88DD, 0xD163, 0x88DE, 0xD164, 0x88E0,
+	0xD165, 0x88E1, 0xD166, 0x88E6, 0xD167, 0x88E7, 0xD168, 0x88E9,	0xD169, 0x88EA, 0xD16A, 0x88EB, 0xD16B, 0x88EC, 0xD16C, 0x88ED,
+	0xD16D, 0x88EE, 0xD16E, 0x88EF, 0xD16F, 0x88F2, 0xD170, 0x88F5,	0xD171, 0x88F6, 0xD172, 0x88F7, 0xD173, 0x88FA, 0xD174, 0x88FB,
+	0xD175, 0x88FD, 0xD176, 0x88FF, 0xD177, 0x8900, 0xD178, 0x8901,	0xD179, 0x8903, 0xD17A, 0x8904, 0xD17B, 0x8905, 0xD17C, 0x8906,
+	0xD17D, 0x8907, 0xD17E, 0x8908, 0xD180, 0x8909, 0xD181, 0x890B,	0xD182, 0x890C, 0xD183, 0x890D, 0xD184, 0x890E, 0xD185, 0x890F,
+	0xD186, 0x8911, 0xD187, 0x8914, 0xD188, 0x8915, 0xD189, 0x8916,	0xD18A, 0x8917, 0xD18B, 0x8918, 0xD18C, 0x891C, 0xD18D, 0x891D,
+	0xD18E, 0x891E, 0xD18F, 0x891F, 0xD190, 0x8920, 0xD191, 0x8922,	0xD192, 0x8923, 0xD193, 0x8924, 0xD194, 0x8926, 0xD195, 0x8927,
+	0xD196, 0x8928, 0xD197, 0x8929, 0xD198, 0x892C, 0xD199, 0x892D,	0xD19A, 0x892E, 0xD19B, 0x892F, 0xD19C, 0x8931, 0xD19D, 0x8932,
+	0xD19E, 0x8933, 0xD19F, 0x8935, 0xD1A0, 0x8937, 0xD1A1, 0x9009,	0xD1A2, 0x7663, 0xD1A3, 0x7729, 0xD1A4, 0x7EDA, 0xD1A5, 0x9774,
+	0xD1A6, 0x859B, 0xD1A7, 0x5B66, 0xD1A8, 0x7A74, 0xD1A9, 0x96EA,	0xD1AA, 0x8840, 0xD1AB, 0x52CB, 0xD1AC, 0x718F, 0xD1AD, 0x5FAA,
+	0xD1AE, 0x65EC, 0xD1AF, 0x8BE2, 0xD1B0, 0x5BFB, 0xD1B1, 0x9A6F,	0xD1B2, 0x5DE1, 0xD1B3, 0x6B89, 0xD1B4, 0x6C5B, 0xD1B5, 0x8BAD,
+	0xD1B6, 0x8BAF, 0xD1B7, 0x900A, 0xD1B8, 0x8FC5, 0xD1B9, 0x538B,	0xD1BA, 0x62BC, 0xD1BB, 0x9E26, 0xD1BC, 0x9E2D, 0xD1BD, 0x5440,
+	0xD1BE, 0x4E2B, 0xD1BF, 0x82BD, 0xD1C0, 0x7259, 0xD1C1, 0x869C,	0xD1C2, 0x5D16, 0xD1C3, 0x8859, 0xD1C4, 0x6DAF, 0xD1C5, 0x96C5,
+	0xD1C6, 0x54D1, 0xD1C7, 0x4E9A, 0xD1C8, 0x8BB6, 0xD1C9, 0x7109,	0xD1CA, 0x54BD, 0xD1CB, 0x9609, 0xD1CC, 0x70DF, 0xD1CD, 0x6DF9,
+	0xD1CE, 0x76D0, 0xD1CF, 0x4E25, 0xD1D0, 0x7814, 0xD1D1, 0x8712,	0xD1D2, 0x5CA9, 0xD1D3, 0x5EF6, 0xD1D4, 0x8A00, 0xD1D5, 0x989C,
+	0xD1D6, 0x960E, 0xD1D7, 0x708E, 0xD1D8, 0x6CBF, 0xD1D9, 0x5944,	0xD1DA, 0x63A9, 0xD1DB, 0x773C, 0xD1DC, 0x884D, 0xD1DD, 0x6F14,
+	0xD1DE, 0x8273, 0xD1DF, 0x5830, 0xD1E0, 0x71D5, 0xD1E1, 0x538C,	0xD1E2, 0x781A, 0xD1E3, 0x96C1, 0xD1E4, 0x5501, 0xD1E5, 0x5F66,
+	0xD1E6, 0x7130, 0xD1E7, 0x5BB4, 0xD1E8, 0x8C1A, 0xD1E9, 0x9A8C,	0xD1EA, 0x6B83, 0xD1EB, 0x592E, 0xD1EC, 0x9E2F, 0xD1ED, 0x79E7,
+	0xD1EE, 0x6768, 0xD1EF, 0x626C, 0xD1F0, 0x4F6F, 0xD1F1, 0x75A1,	0xD1F2, 0x7F8A, 0xD1F3, 0x6D0B, 0xD1F4, 0x9633, 0xD1F5, 0x6C27,
+	0xD1F6, 0x4EF0, 0xD1F7, 0x75D2, 0xD1F8, 0x517B, 0xD1F9, 0x6837,	0xD1FA, 0x6F3E, 0xD1FB, 0x9080, 0xD1FC, 0x8170, 0xD1FD, 0x5996,
+	0xD1FE, 0x7476, 0xD240, 0x8938, 0xD241, 0x8939, 0xD242, 0x893A,	0xD243, 0x893B, 0xD244, 0x893C, 0xD245, 0x893D, 0xD246, 0x893E,
+	0xD247, 0x893F, 0xD248, 0x8940, 0xD249, 0x8942, 0xD24A, 0x8943,	0xD24B, 0x8945, 0xD24C, 0x8946, 0xD24D, 0x8947, 0xD24E, 0x8948,
+	0xD24F, 0x8949, 0xD250, 0x894A, 0xD251, 0x894B, 0xD252, 0x894C,	0xD253, 0x894D, 0xD254, 0x894E, 0xD255, 0x894F, 0xD256, 0x8950,
+	0xD257, 0x8951, 0xD258, 0x8952, 0xD259, 0x8953, 0xD25A, 0x8954,	0xD25B, 0x8955, 0xD25C, 0x8956, 0xD25D, 0x8957, 0xD25E, 0x8958,
+	0xD25F, 0x8959, 0xD260, 0x895A, 0xD261, 0x895B, 0xD262, 0x895C,	0xD263, 0x895D, 0xD264, 0x8960, 0xD265, 0x8961, 0xD266, 0x8962,
+	0xD267, 0x8963, 0xD268, 0x8964, 0xD269, 0x8965, 0xD26A, 0x8967,	0xD26B, 0x8968, 0xD26C, 0x8969, 0xD26D, 0x896A, 0xD26E, 0x896B,
+	0xD26F, 0x896C, 0xD270, 0x896D, 0xD271, 0x896E, 0xD272, 0x896F,	0xD273, 0x8970, 0xD274, 0x8971, 0xD275, 0x8972, 0xD276, 0x8973,
+	0xD277, 0x8974, 0xD278, 0x8975, 0xD279, 0x8976, 0xD27A, 0x8977,	0xD27B, 0x8978, 0xD27C, 0x8979, 0xD27D, 0x897A, 0xD27E, 0x897C,
+	0xD280, 0x897D, 0xD281, 0x897E, 0xD282, 0x8980, 0xD283, 0x8982,	0xD284, 0x8984, 0xD285, 0x8985, 0xD286, 0x8987, 0xD287, 0x8988,
+	0xD288, 0x8989, 0xD289, 0x898A, 0xD28A, 0x898B, 0xD28B, 0x898C,	0xD28C, 0x898D, 0xD28D, 0x898E, 0xD28E, 0x898F, 0xD28F, 0x8990,
+	0xD290, 0x8991, 0xD291, 0x8992, 0xD292, 0x8993, 0xD293, 0x8994,	0xD294, 0x8995, 0xD295, 0x8996, 0xD296, 0x8997, 0xD297, 0x8998,
+	0xD298, 0x8999, 0xD299, 0x899A, 0xD29A, 0x899B, 0xD29B, 0x899C,	0xD29C, 0x899D, 0xD29D, 0x899E, 0xD29E, 0x899F, 0xD29F, 0x89A0,
+	0xD2A0, 0x89A1, 0xD2A1, 0x6447, 0xD2A2, 0x5C27, 0xD2A3, 0x9065,	0xD2A4, 0x7A91, 0xD2A5, 0x8C23, 0xD2A6, 0x59DA, 0xD2A7, 0x54AC,
+	0xD2A8, 0x8200, 0xD2A9, 0x836F, 0xD2AA, 0x8981, 0xD2AB, 0x8000,	0xD2AC, 0x6930, 0xD2AD, 0x564E, 0xD2AE, 0x8036, 0xD2AF, 0x7237,
+	0xD2B0, 0x91CE, 0xD2B1, 0x51B6, 0xD2B2, 0x4E5F, 0xD2B3, 0x9875,	0xD2B4, 0x6396, 0xD2B5, 0x4E1A, 0xD2B6, 0x53F6, 0xD2B7, 0x66F3,
+	0xD2B8, 0x814B, 0xD2B9, 0x591C, 0xD2BA, 0x6DB2, 0xD2BB, 0x4E00,	0xD2BC, 0x58F9, 0xD2BD, 0x533B, 0xD2BE, 0x63D6, 0xD2BF, 0x94F1,
+	0xD2C0, 0x4F9D, 0xD2C1, 0x4F0A, 0xD2C2, 0x8863, 0xD2C3, 0x9890,	0xD2C4, 0x5937, 0xD2C5, 0x9057, 0xD2C6, 0x79FB, 0xD2C7, 0x4EEA,
+	0xD2C8, 0x80F0, 0xD2C9, 0x7591, 0xD2CA, 0x6C82, 0xD2CB, 0x5B9C,	0xD2CC, 0x59E8, 0xD2CD, 0x5F5D, 0xD2CE, 0x6905, 0xD2CF, 0x8681,
+	0xD2D0, 0x501A, 0xD2D1, 0x5DF2, 0xD2D2, 0x4E59, 0xD2D3, 0x77E3,	0xD2D4, 0x4EE5, 0xD2D5, 0x827A, 0xD2D6, 0x6291, 0xD2D7, 0x6613,
+	0xD2D8, 0x9091, 0xD2D9, 0x5C79, 0xD2DA, 0x4EBF, 0xD2DB, 0x5F79,	0xD2DC, 0x81C6, 0xD2DD, 0x9038, 0xD2DE, 0x8084, 0xD2DF, 0x75AB,
+	0xD2E0, 0x4EA6, 0xD2E1, 0x88D4, 0xD2E2, 0x610F, 0xD2E3, 0x6BC5,	0xD2E4, 0x5FC6, 0xD2E5, 0x4E49, 0xD2E6, 0x76CA, 0xD2E7, 0x6EA2,
+	0xD2E8, 0x8BE3, 0xD2E9, 0x8BAE, 0xD2EA, 0x8C0A, 0xD2EB, 0x8BD1,	0xD2EC, 0x5F02, 0xD2ED, 0x7FFC, 0xD2EE, 0x7FCC, 0xD2EF, 0x7ECE,
+	0xD2F0, 0x8335, 0xD2F1, 0x836B, 0xD2F2, 0x56E0, 0xD2F3, 0x6BB7,	0xD2F4, 0x97F3, 0xD2F5, 0x9634, 0xD2F6, 0x59FB, 0xD2F7, 0x541F,
+	0xD2F8, 0x94F6, 0xD2F9, 0x6DEB, 0xD2FA, 0x5BC5, 0xD2FB, 0x996E,	0xD2FC, 0x5C39, 0xD2FD, 0x5F15, 0xD2FE, 0x9690, 0xD340, 0x89A2,
+	0xD341, 0x89A3, 0xD342, 0x89A4, 0xD343, 0x89A5, 0xD344, 0x89A6,	0xD345, 0x89A7, 0xD346, 0x89A8, 0xD347, 0x89A9, 0xD348, 0x89AA,
+	0xD349, 0x89AB, 0xD34A, 0x89AC, 0xD34B, 0x89AD, 0xD34C, 0x89AE,	0xD34D, 0x89AF, 0xD34E, 0x89B0, 0xD34F, 0x89B1, 0xD350, 0x89B2,
+	0xD351, 0x89B3, 0xD352, 0x89B4, 0xD353, 0x89B5, 0xD354, 0x89B6,	0xD355, 0x89B7, 0xD356, 0x89B8, 0xD357, 0x89B9, 0xD358, 0x89BA,
+	0xD359, 0x89BB, 0xD35A, 0x89BC, 0xD35B, 0x89BD, 0xD35C, 0x89BE,	0xD35D, 0x89BF, 0xD35E, 0x89C0, 0xD35F, 0x89C3, 0xD360, 0x89CD,
+	0xD361, 0x89D3, 0xD362, 0x89D4, 0xD363, 0x89D5, 0xD364, 0x89D7,	0xD365, 0x89D8, 0xD366, 0x89D9, 0xD367, 0x89DB, 0xD368, 0x89DD,
+	0xD369, 0x89DF, 0xD36A, 0x89E0, 0xD36B, 0x89E1, 0xD36C, 0x89E2,	0xD36D, 0x89E4, 0xD36E, 0x89E7, 0xD36F, 0x89E8, 0xD370, 0x89E9,
+	0xD371, 0x89EA, 0xD372, 0x89EC, 0xD373, 0x89ED, 0xD374, 0x89EE,	0xD375, 0x89F0, 0xD376, 0x89F1, 0xD377, 0x89F2, 0xD378, 0x89F4,
+	0xD379, 0x89F5, 0xD37A, 0x89F6, 0xD37B, 0x89F7, 0xD37C, 0x89F8,	0xD37D, 0x89F9, 0xD37E, 0x89FA, 0xD380, 0x89FB, 0xD381, 0x89FC,
+	0xD382, 0x89FD, 0xD383, 0x89FE, 0xD384, 0x89FF, 0xD385, 0x8A01,	0xD386, 0x8A02, 0xD387, 0x8A03, 0xD388, 0x8A04, 0xD389, 0x8A05,
+	0xD38A, 0x8A06, 0xD38B, 0x8A08, 0xD38C, 0x8A09, 0xD38D, 0x8A0A,	0xD38E, 0x8A0B, 0xD38F, 0x8A0C, 0xD390, 0x8A0D, 0xD391, 0x8A0E,
+	0xD392, 0x8A0F, 0xD393, 0x8A10, 0xD394, 0x8A11, 0xD395, 0x8A12,	0xD396, 0x8A13, 0xD397, 0x8A14, 0xD398, 0x8A15, 0xD399, 0x8A16,
+	0xD39A, 0x8A17, 0xD39B, 0x8A18, 0xD39C, 0x8A19, 0xD39D, 0x8A1A,	0xD39E, 0x8A1B, 0xD39F, 0x8A1C, 0xD3A0, 0x8A1D, 0xD3A1, 0x5370,
+	0xD3A2, 0x82F1, 0xD3A3, 0x6A31, 0xD3A4, 0x5A74, 0xD3A5, 0x9E70,	0xD3A6, 0x5E94, 0xD3A7, 0x7F28, 0xD3A8, 0x83B9, 0xD3A9, 0x8424,
+	0xD3AA, 0x8425, 0xD3AB, 0x8367, 0xD3AC, 0x8747, 0xD3AD, 0x8FCE,	0xD3AE, 0x8D62, 0xD3AF, 0x76C8, 0xD3B0, 0x5F71, 0xD3B1, 0x9896,
+	0xD3B2, 0x786C, 0xD3B3, 0x6620, 0xD3B4, 0x54DF, 0xD3B5, 0x62E5,	0xD3B6, 0x4F63, 0xD3B7, 0x81C3, 0xD3B8, 0x75C8, 0xD3B9, 0x5EB8,
+	0xD3BA, 0x96CD, 0xD3BB, 0x8E0A, 0xD3BC, 0x86F9, 0xD3BD, 0x548F,	0xD3BE, 0x6CF3, 0xD3BF, 0x6D8C, 0xD3C0, 0x6C38, 0xD3C1, 0x607F,
+	0xD3C2, 0x52C7, 0xD3C3, 0x7528, 0xD3C4, 0x5E7D, 0xD3C5, 0x4F18,	0xD3C6, 0x60A0, 0xD3C7, 0x5FE7, 0xD3C8, 0x5C24, 0xD3C9, 0x7531,
+	0xD3CA, 0x90AE, 0xD3CB, 0x94C0, 0xD3CC, 0x72B9, 0xD3CD, 0x6CB9,	0xD3CE, 0x6E38, 0xD3CF, 0x9149, 0xD3D0, 0x6709, 0xD3D1, 0x53CB,
+	0xD3D2, 0x53F3, 0xD3D3, 0x4F51, 0xD3D4, 0x91C9, 0xD3D5, 0x8BF1,	0xD3D6, 0x53C8, 0xD3D7, 0x5E7C, 0xD3D8, 0x8FC2, 0xD3D9, 0x6DE4,
+	0xD3DA, 0x4E8E, 0xD3DB, 0x76C2, 0xD3DC, 0x6986, 0xD3DD, 0x865E,	0xD3DE, 0x611A, 0xD3DF, 0x8206, 0xD3E0, 0x4F59, 0xD3E1, 0x4FDE,
+	0xD3E2, 0x903E, 0xD3E3, 0x9C7C, 0xD3E4, 0x6109, 0xD3E5, 0x6E1D,	0xD3E6, 0x6E14, 0xD3E7, 0x9685, 0xD3E8, 0x4E88, 0xD3E9, 0x5A31,
+	0xD3EA, 0x96E8, 0xD3EB, 0x4E0E, 0xD3EC, 0x5C7F, 0xD3ED, 0x79B9,	0xD3EE, 0x5B87, 0xD3EF, 0x8BED, 0xD3F0, 0x7FBD, 0xD3F1, 0x7389,
+	0xD3F2, 0x57DF, 0xD3F3, 0x828B, 0xD3F4, 0x90C1, 0xD3F5, 0x5401,	0xD3F6, 0x9047, 0xD3F7, 0x55BB, 0xD3F8, 0x5CEA, 0xD3F9, 0x5FA1,
+	0xD3FA, 0x6108, 0xD3FB, 0x6B32, 0xD3FC, 0x72F1, 0xD3FD, 0x80B2,	0xD3FE, 0x8A89, 0xD440, 0x8A1E, 0xD441, 0x8A1F, 0xD442, 0x8A20,
+	0xD443, 0x8A21, 0xD444, 0x8A22, 0xD445, 0x8A23, 0xD446, 0x8A24,	0xD447, 0x8A25, 0xD448, 0x8A26, 0xD449, 0x8A27, 0xD44A, 0x8A28,
+	0xD44B, 0x8A29, 0xD44C, 0x8A2A, 0xD44D, 0x8A2B, 0xD44E, 0x8A2C,	0xD44F, 0x8A2D, 0xD450, 0x8A2E, 0xD451, 0x8A2F, 0xD452, 0x8A30,
+	0xD453, 0x8A31, 0xD454, 0x8A32, 0xD455, 0x8A33, 0xD456, 0x8A34,	0xD457, 0x8A35, 0xD458, 0x8A36, 0xD459, 0x8A37, 0xD45A, 0x8A38,
+	0xD45B, 0x8A39, 0xD45C, 0x8A3A, 0xD45D, 0x8A3B, 0xD45E, 0x8A3C,	0xD45F, 0x8A3D, 0xD460, 0x8A3F, 0xD461, 0x8A40, 0xD462, 0x8A41,
+	0xD463, 0x8A42, 0xD464, 0x8A43, 0xD465, 0x8A44, 0xD466, 0x8A45,	0xD467, 0x8A46, 0xD468, 0x8A47, 0xD469, 0x8A49, 0xD46A, 0x8A4A,
+	0xD46B, 0x8A4B, 0xD46C, 0x8A4C, 0xD46D, 0x8A4D, 0xD46E, 0x8A4E,	0xD46F, 0x8A4F, 0xD470, 0x8A50, 0xD471, 0x8A51, 0xD472, 0x8A52,
+	0xD473, 0x8A53, 0xD474, 0x8A54, 0xD475, 0x8A55, 0xD476, 0x8A56,	0xD477, 0x8A57, 0xD478, 0x8A58, 0xD479, 0x8A59, 0xD47A, 0x8A5A,
+	0xD47B, 0x8A5B, 0xD47C, 0x8A5C, 0xD47D, 0x8A5D, 0xD47E, 0x8A5E,	0xD480, 0x8A5F, 0xD481, 0x8A60, 0xD482, 0x8A61, 0xD483, 0x8A62,
+	0xD484, 0x8A63, 0xD485, 0x8A64, 0xD486, 0x8A65, 0xD487, 0x8A66,	0xD488, 0x8A67, 0xD489, 0x8A68, 0xD48A, 0x8A69, 0xD48B, 0x8A6A,
+	0xD48C, 0x8A6B, 0xD48D, 0x8A6C, 0xD48E, 0x8A6D, 0xD48F, 0x8A6E,	0xD490, 0x8A6F, 0xD491, 0x8A70, 0xD492, 0x8A71, 0xD493, 0x8A72,
+	0xD494, 0x8A73, 0xD495, 0x8A74, 0xD496, 0x8A75, 0xD497, 0x8A76,	0xD498, 0x8A77, 0xD499, 0x8A78, 0xD49A, 0x8A7A, 0xD49B, 0x8A7B,
+	0xD49C, 0x8A7C, 0xD49D, 0x8A7D, 0xD49E, 0x8A7E, 0xD49F, 0x8A7F,	0xD4A0, 0x8A80, 0xD4A1, 0x6D74, 0xD4A2, 0x5BD3, 0xD4A3, 0x88D5,
+	0xD4A4, 0x9884, 0xD4A5, 0x8C6B, 0xD4A6, 0x9A6D, 0xD4A7, 0x9E33,	0xD4A8, 0x6E0A, 0xD4A9, 0x51A4, 0xD4AA, 0x5143, 0xD4AB, 0x57A3,
+	0xD4AC, 0x8881, 0xD4AD, 0x539F, 0xD4AE, 0x63F4, 0xD4AF, 0x8F95,	0xD4B0, 0x56ED, 0xD4B1, 0x5458, 0xD4B2, 0x5706, 0xD4B3, 0x733F,
+	0xD4B4, 0x6E90, 0xD4B5, 0x7F18, 0xD4B6, 0x8FDC, 0xD4B7, 0x82D1,	0xD4B8, 0x613F, 0xD4B9, 0x6028, 0xD4BA, 0x9662, 0xD4BB, 0x66F0,
+	0xD4BC, 0x7EA6, 0xD4BD, 0x8D8A, 0xD4BE, 0x8DC3, 0xD4BF, 0x94A5,	0xD4C0, 0x5CB3, 0xD4C1, 0x7CA4, 0xD4C2, 0x6708, 0xD4C3, 0x60A6,
+	0xD4C4, 0x9605, 0xD4C5, 0x8018, 0xD4C6, 0x4E91, 0xD4C7, 0x90E7,	0xD4C8, 0x5300, 0xD4C9, 0x9668, 0xD4CA, 0x5141, 0xD4CB, 0x8FD0,
+	0xD4CC, 0x8574, 0xD4CD, 0x915D, 0xD4CE, 0x6655, 0xD4CF, 0x97F5,	0xD4D0, 0x5B55, 0xD4D1, 0x531D, 0xD4D2, 0x7838, 0xD4D3, 0x6742,
+	0xD4D4, 0x683D, 0xD4D5, 0x54C9, 0xD4D6, 0x707E, 0xD4D7, 0x5BB0,	0xD4D8, 0x8F7D, 0xD4D9, 0x518D, 0xD4DA, 0x5728, 0xD4DB, 0x54B1,
+	0xD4DC, 0x6512, 0xD4DD, 0x6682, 0xD4DE, 0x8D5E, 0xD4DF, 0x8D43,	0xD4E0, 0x810F, 0xD4E1, 0x846C, 0xD4E2, 0x906D, 0xD4E3, 0x7CDF,
+	0xD4E4, 0x51FF, 0xD4E5, 0x85FB, 0xD4E6, 0x67A3, 0xD4E7, 0x65E9,	0xD4E8, 0x6FA1, 0xD4E9, 0x86A4, 0xD4EA, 0x8E81, 0xD4EB, 0x566A,
+	0xD4EC, 0x9020, 0xD4ED, 0x7682, 0xD4EE, 0x7076, 0xD4EF, 0x71E5,	0xD4F0, 0x8D23, 0xD4F1, 0x62E9, 0xD4F2, 0x5219, 0xD4F3, 0x6CFD,
+	0xD4F4, 0x8D3C, 0xD4F5, 0x600E, 0xD4F6, 0x589E, 0xD4F7, 0x618E,	0xD4F8, 0x66FE, 0xD4F9, 0x8D60, 0xD4FA, 0x624E, 0xD4FB, 0x55B3,
+	0xD4FC, 0x6E23, 0xD4FD, 0x672D, 0xD4FE, 0x8F67, 0xD540, 0x8A81,	0xD541, 0x8A82, 0xD542, 0x8A83, 0xD543, 0x8A84, 0xD544, 0x8A85,
+	0xD545, 0x8A86, 0xD546, 0x8A87, 0xD547, 0x8A88, 0xD548, 0x8A8B,	0xD549, 0x8A8C, 0xD54A, 0x8A8D, 0xD54B, 0x8A8E, 0xD54C, 0x8A8F,
+	0xD54D, 0x8A90, 0xD54E, 0x8A91, 0xD54F, 0x8A92, 0xD550, 0x8A94,	0xD551, 0x8A95, 0xD552, 0x8A96, 0xD553, 0x8A97, 0xD554, 0x8A98,
+	0xD555, 0x8A99, 0xD556, 0x8A9A, 0xD557, 0x8A9B, 0xD558, 0x8A9C,	0xD559, 0x8A9D, 0xD55A, 0x8A9E, 0xD55B, 0x8A9F, 0xD55C, 0x8AA0,
+	0xD55D, 0x8AA1, 0xD55E, 0x8AA2, 0xD55F, 0x8AA3, 0xD560, 0x8AA4,	0xD561, 0x8AA5, 0xD562, 0x8AA6, 0xD563, 0x8AA7, 0xD564, 0x8AA8,
+	0xD565, 0x8AA9, 0xD566, 0x8AAA, 0xD567, 0x8AAB, 0xD568, 0x8AAC,	0xD569, 0x8AAD, 0xD56A, 0x8AAE, 0xD56B, 0x8AAF, 0xD56C, 0x8AB0,
+	0xD56D, 0x8AB1, 0xD56E, 0x8AB2, 0xD56F, 0x8AB3, 0xD570, 0x8AB4,	0xD571, 0x8AB5, 0xD572, 0x8AB6, 0xD573, 0x8AB7, 0xD574, 0x8AB8,
+	0xD575, 0x8AB9, 0xD576, 0x8ABA, 0xD577, 0x8ABB, 0xD578, 0x8ABC,	0xD579, 0x8ABD, 0xD57A, 0x8ABE, 0xD57B, 0x8ABF, 0xD57C, 0x8AC0,
+	0xD57D, 0x8AC1, 0xD57E, 0x8AC2, 0xD580, 0x8AC3, 0xD581, 0x8AC4,	0xD582, 0x8AC5, 0xD583, 0x8AC6, 0xD584, 0x8AC7, 0xD585, 0x8AC8,
+	0xD586, 0x8AC9, 0xD587, 0x8ACA, 0xD588, 0x8ACB, 0xD589, 0x8ACC,	0xD58A, 0x8ACD, 0xD58B, 0x8ACE, 0xD58C, 0x8ACF, 0xD58D, 0x8AD0,
+	0xD58E, 0x8AD1, 0xD58F, 0x8AD2, 0xD590, 0x8AD3, 0xD591, 0x8AD4,	0xD592, 0x8AD5, 0xD593, 0x8AD6, 0xD594, 0x8AD7, 0xD595, 0x8AD8,
+	0xD596, 0x8AD9, 0xD597, 0x8ADA, 0xD598, 0x8ADB, 0xD599, 0x8ADC,	0xD59A, 0x8ADD, 0xD59B, 0x8ADE, 0xD59C, 0x8ADF, 0xD59D, 0x8AE0,
+	0xD59E, 0x8AE1, 0xD59F, 0x8AE2, 0xD5A0, 0x8AE3, 0xD5A1, 0x94E1,	0xD5A2, 0x95F8, 0xD5A3, 0x7728, 0xD5A4, 0x6805, 0xD5A5, 0x69A8,
+	0xD5A6, 0x548B, 0xD5A7, 0x4E4D, 0xD5A8, 0x70B8, 0xD5A9, 0x8BC8,	0xD5AA, 0x6458, 0xD5AB, 0x658B, 0xD5AC, 0x5B85, 0xD5AD, 0x7A84,
+	0xD5AE, 0x503A, 0xD5AF, 0x5BE8, 0xD5B0, 0x77BB, 0xD5B1, 0x6BE1,	0xD5B2, 0x8A79, 0xD5B3, 0x7C98, 0xD5B4, 0x6CBE, 0xD5B5, 0x76CF,
+	0xD5B6, 0x65A9, 0xD5B7, 0x8F97, 0xD5B8, 0x5D2D, 0xD5B9, 0x5C55,	0xD5BA, 0x8638, 0xD5BB, 0x6808, 0xD5BC, 0x5360, 0xD5BD, 0x6218,
+	0xD5BE, 0x7AD9, 0xD5BF, 0x6E5B, 0xD5C0, 0x7EFD, 0xD5C1, 0x6A1F,	0xD5C2, 0x7AE0, 0xD5C3, 0x5F70, 0xD5C4, 0x6F33, 0xD5C5, 0x5F20,
+	0xD5C6, 0x638C, 0xD5C7, 0x6DA8, 0xD5C8, 0x6756, 0xD5C9, 0x4E08,	0xD5CA, 0x5E10, 0xD5CB, 0x8D26, 0xD5CC, 0x4ED7, 0xD5CD, 0x80C0,
+	0xD5CE, 0x7634, 0xD5CF, 0x969C, 0xD5D0, 0x62DB, 0xD5D1, 0x662D,	0xD5D2, 0x627E, 0xD5D3, 0x6CBC, 0xD5D4, 0x8D75, 0xD5D5, 0x7167,
+	0xD5D6, 0x7F69, 0xD5D7, 0x5146, 0xD5D8, 0x8087, 0xD5D9, 0x53EC,	0xD5DA, 0x906E, 0xD5DB, 0x6298, 0xD5DC, 0x54F2, 0xD5DD, 0x86F0,
+	0xD5DE, 0x8F99, 0xD5DF, 0x8005, 0xD5E0, 0x9517, 0xD5E1, 0x8517,	0xD5E2, 0x8FD9, 0xD5E3, 0x6D59, 0xD5E4, 0x73CD, 0xD5E5, 0x659F,
+	0xD5E6, 0x771F, 0xD5E7, 0x7504, 0xD5E8, 0x7827, 0xD5E9, 0x81FB,	0xD5EA, 0x8D1E, 0xD5EB, 0x9488, 0xD5EC, 0x4FA6, 0xD5ED, 0x6795,
+	0xD5EE, 0x75B9, 0xD5EF, 0x8BCA, 0xD5F0, 0x9707, 0xD5F1, 0x632F,	0xD5F2, 0x9547, 0xD5F3, 0x9635, 0xD5F4, 0x84B8, 0xD5F5, 0x6323,
+	0xD5F6, 0x7741, 0xD5F7, 0x5F81, 0xD5F8, 0x72F0, 0xD5F9, 0x4E89,	0xD5FA, 0x6014, 0xD5FB, 0x6574, 0xD5FC, 0x62EF, 0xD5FD, 0x6B63,
+	0xD5FE, 0x653F, 0xD640, 0x8AE4, 0xD641, 0x8AE5, 0xD642, 0x8AE6,	0xD643, 0x8AE7, 0xD644, 0x8AE8, 0xD645, 0x8AE9, 0xD646, 0x8AEA,
+	0xD647, 0x8AEB, 0xD648, 0x8AEC, 0xD649, 0x8AED, 0xD64A, 0x8AEE,	0xD64B, 0x8AEF, 0xD64C, 0x8AF0, 0xD64D, 0x8AF1, 0xD64E, 0x8AF2,
+	0xD64F, 0x8AF3, 0xD650, 0x8AF4, 0xD651, 0x8AF5, 0xD652, 0x8AF6,	0xD653, 0x8AF7, 0xD654, 0x8AF8, 0xD655, 0x8AF9, 0xD656, 0x8AFA,
+	0xD657, 0x8AFB, 0xD658, 0x8AFC, 0xD659, 0x8AFD, 0xD65A, 0x8AFE,	0xD65B, 0x8AFF, 0xD65C, 0x8B00, 0xD65D, 0x8B01, 0xD65E, 0x8B02,
+	0xD65F, 0x8B03, 0xD660, 0x8B04, 0xD661, 0x8B05, 0xD662, 0x8B06,	0xD663, 0x8B08, 0xD664, 0x8B09, 0xD665, 0x8B0A, 0xD666, 0x8B0B,
+	0xD667, 0x8B0C, 0xD668, 0x8B0D, 0xD669, 0x8B0E, 0xD66A, 0x8B0F,	0xD66B, 0x8B10, 0xD66C, 0x8B11, 0xD66D, 0x8B12, 0xD66E, 0x8B13,
+	0xD66F, 0x8B14, 0xD670, 0x8B15, 0xD671, 0x8B16, 0xD672, 0x8B17,	0xD673, 0x8B18, 0xD674, 0x8B19, 0xD675, 0x8B1A, 0xD676, 0x8B1B,
+	0xD677, 0x8B1C, 0xD678, 0x8B1D, 0xD679, 0x8B1E, 0xD67A, 0x8B1F,	0xD67B, 0x8B20, 0xD67C, 0x8B21, 0xD67D, 0x8B22, 0xD67E, 0x8B23,
+	0xD680, 0x8B24, 0xD681, 0x8B25, 0xD682, 0x8B27, 0xD683, 0x8B28,	0xD684, 0x8B29, 0xD685, 0x8B2A, 0xD686, 0x8B2B, 0xD687, 0x8B2C,
+	0xD688, 0x8B2D, 0xD689, 0x8B2E, 0xD68A, 0x8B2F, 0xD68B, 0x8B30,	0xD68C, 0x8B31, 0xD68D, 0x8B32, 0xD68E, 0x8B33, 0xD68F, 0x8B34,
+	0xD690, 0x8B35, 0xD691, 0x8B36, 0xD692, 0x8B37, 0xD693, 0x8B38,	0xD694, 0x8B39, 0xD695, 0x8B3A, 0xD696, 0x8B3B, 0xD697, 0x8B3C,
+	0xD698, 0x8B3D, 0xD699, 0x8B3E, 0xD69A, 0x8B3F, 0xD69B, 0x8B40,	0xD69C, 0x8B41, 0xD69D, 0x8B42, 0xD69E, 0x8B43, 0xD69F, 0x8B44,
+	0xD6A0, 0x8B45, 0xD6A1, 0x5E27, 0xD6A2, 0x75C7, 0xD6A3, 0x90D1,	0xD6A4, 0x8BC1, 0xD6A5, 0x829D, 0xD6A6, 0x679D, 0xD6A7, 0x652F,
+	0xD6A8, 0x5431, 0xD6A9, 0x8718, 0xD6AA, 0x77E5, 0xD6AB, 0x80A2,	0xD6AC, 0x8102, 0xD6AD, 0x6C41, 0xD6AE, 0x4E4B, 0xD6AF, 0x7EC7,
+	0xD6B0, 0x804C, 0xD6B1, 0x76F4, 0xD6B2, 0x690D, 0xD6B3, 0x6B96,	0xD6B4, 0x6267, 0xD6B5, 0x503C, 0xD6B6, 0x4F84, 0xD6B7, 0x5740,
+	0xD6B8, 0x6307, 0xD6B9, 0x6B62, 0xD6BA, 0x8DBE, 0xD6BB, 0x53EA,	0xD6BC, 0x65E8, 0xD6BD, 0x7EB8, 0xD6BE, 0x5FD7, 0xD6BF, 0x631A,
+	0xD6C0, 0x63B7, 0xD6C1, 0x81F3, 0xD6C2, 0x81F4, 0xD6C3, 0x7F6E,	0xD6C4, 0x5E1C, 0xD6C5, 0x5CD9, 0xD6C6, 0x5236, 0xD6C7, 0x667A,
+	0xD6C8, 0x79E9, 0xD6C9, 0x7A1A, 0xD6CA, 0x8D28, 0xD6CB, 0x7099,	0xD6CC, 0x75D4, 0xD6CD, 0x6EDE, 0xD6CE, 0x6CBB, 0xD6CF, 0x7A92,
+	0xD6D0, 0x4E2D, 0xD6D1, 0x76C5, 0xD6D2, 0x5FE0, 0xD6D3, 0x949F,	0xD6D4, 0x8877, 0xD6D5, 0x7EC8, 0xD6D6, 0x79CD, 0xD6D7, 0x80BF,
+	0xD6D8, 0x91CD, 0xD6D9, 0x4EF2, 0xD6DA, 0x4F17, 0xD6DB, 0x821F,	0xD6DC, 0x5468, 0xD6DD, 0x5DDE, 0xD6DE, 0x6D32, 0xD6DF, 0x8BCC,
+	0xD6E0, 0x7CA5, 0xD6E1, 0x8F74, 0xD6E2, 0x8098, 0xD6E3, 0x5E1A,	0xD6E4, 0x5492, 0xD6E5, 0x76B1, 0xD6E6, 0x5B99, 0xD6E7, 0x663C,
+	0xD6E8, 0x9AA4, 0xD6E9, 0x73E0, 0xD6EA, 0x682A, 0xD6EB, 0x86DB,	0xD6EC, 0x6731, 0xD6ED, 0x732A, 0xD6EE, 0x8BF8, 0xD6EF, 0x8BDB,
+	0xD6F0, 0x9010, 0xD6F1, 0x7AF9, 0xD6F2, 0x70DB, 0xD6F3, 0x716E,	0xD6F4, 0x62C4, 0xD6F5, 0x77A9, 0xD6F6, 0x5631, 0xD6F7, 0x4E3B,
+	0xD6F8, 0x8457, 0xD6F9, 0x67F1, 0xD6FA, 0x52A9, 0xD6FB, 0x86C0,	0xD6FC, 0x8D2E, 0xD6FD, 0x94F8, 0xD6FE, 0x7B51, 0xD740, 0x8B46,
+	0xD741, 0x8B47, 0xD742, 0x8B48, 0xD743, 0x8B49, 0xD744, 0x8B4A,	0xD745, 0x8B4B, 0xD746, 0x8B4C, 0xD747, 0x8B4D, 0xD748, 0x8B4E,
+	0xD749, 0x8B4F, 0xD74A, 0x8B50, 0xD74B, 0x8B51, 0xD74C, 0x8B52,	0xD74D, 0x8B53, 0xD74E, 0x8B54, 0xD74F, 0x8B55, 0xD750, 0x8B56,
+	0xD751, 0x8B57, 0xD752, 0x8B58, 0xD753, 0x8B59, 0xD754, 0x8B5A,	0xD755, 0x8B5B, 0xD756, 0x8B5C, 0xD757, 0x8B5D, 0xD758, 0x8B5E,
+	0xD759, 0x8B5F, 0xD75A, 0x8B60, 0xD75B, 0x8B61, 0xD75C, 0x8B62,	0xD75D, 0x8B63, 0xD75E, 0x8B64, 0xD75F, 0x8B65, 0xD760, 0x8B67,
+	0xD761, 0x8B68, 0xD762, 0x8B69, 0xD763, 0x8B6A, 0xD764, 0x8B6B,	0xD765, 0x8B6D, 0xD766, 0x8B6E, 0xD767, 0x8B6F, 0xD768, 0x8B70,
+	0xD769, 0x8B71, 0xD76A, 0x8B72, 0xD76B, 0x8B73, 0xD76C, 0x8B74,	0xD76D, 0x8B75, 0xD76E, 0x8B76, 0xD76F, 0x8B77, 0xD770, 0x8B78,
+	0xD771, 0x8B79, 0xD772, 0x8B7A, 0xD773, 0x8B7B, 0xD774, 0x8B7C,	0xD775, 0x8B7D, 0xD776, 0x8B7E, 0xD777, 0x8B7F, 0xD778, 0x8B80,
+	0xD779, 0x8B81, 0xD77A, 0x8B82, 0xD77B, 0x8B83, 0xD77C, 0x8B84,	0xD77D, 0x8B85, 0xD77E, 0x8B86, 0xD780, 0x8B87, 0xD781, 0x8B88,
+	0xD782, 0x8B89, 0xD783, 0x8B8A, 0xD784, 0x8B8B, 0xD785, 0x8B8C,	0xD786, 0x8B8D, 0xD787, 0x8B8E, 0xD788, 0x8B8F, 0xD789, 0x8B90,
+	0xD78A, 0x8B91, 0xD78B, 0x8B92, 0xD78C, 0x8B93, 0xD78D, 0x8B94,	0xD78E, 0x8B95, 0xD78F, 0x8B96, 0xD790, 0x8B97, 0xD791, 0x8B98,
+	0xD792, 0x8B99, 0xD793, 0x8B9A, 0xD794, 0x8B9B, 0xD795, 0x8B9C,	0xD796, 0x8B9D, 0xD797, 0x8B9E, 0xD798, 0x8B9F, 0xD799, 0x8BAC,
+	0xD79A, 0x8BB1, 0xD79B, 0x8BBB, 0xD79C, 0x8BC7, 0xD79D, 0x8BD0,	0xD79E, 0x8BEA, 0xD79F, 0x8C09, 0xD7A0, 0x8C1E, 0xD7A1, 0x4F4F,
+	0xD7A2, 0x6CE8, 0xD7A3, 0x795D, 0xD7A4, 0x9A7B, 0xD7A5, 0x6293,	0xD7A6, 0x722A, 0xD7A7, 0x62FD, 0xD7A8, 0x4E13, 0xD7A9, 0x7816,
+	0xD7AA, 0x8F6C, 0xD7AB, 0x64B0, 0xD7AC, 0x8D5A, 0xD7AD, 0x7BC6,	0xD7AE, 0x6869, 0xD7AF, 0x5E84, 0xD7B0, 0x88C5, 0xD7B1, 0x5986,
+	0xD7B2, 0x649E, 0xD7B3, 0x58EE, 0xD7B4, 0x72B6, 0xD7B5, 0x690E,	0xD7B6, 0x9525, 0xD7B7, 0x8FFD, 0xD7B8, 0x8D58, 0xD7B9, 0x5760,
+	0xD7BA, 0x7F00, 0xD7BB, 0x8C06, 0xD7BC, 0x51C6, 0xD7BD, 0x6349,	0xD7BE, 0x62D9, 0xD7BF, 0x5353, 0xD7C0, 0x684C, 0xD7C1, 0x7422,
+	0xD7C2, 0x8301, 0xD7C3, 0x914C, 0xD7C4, 0x5544, 0xD7C5, 0x7740,	0xD7C6, 0x707C, 0xD7C7, 0x6D4A, 0xD7C8, 0x5179, 0xD7C9, 0x54A8,
+	0xD7CA, 0x8D44, 0xD7CB, 0x59FF, 0xD7CC, 0x6ECB, 0xD7CD, 0x6DC4,	0xD7CE, 0x5B5C, 0xD7CF, 0x7D2B, 0xD7D0, 0x4ED4, 0xD7D1, 0x7C7D,
+	0xD7D2, 0x6ED3, 0xD7D3, 0x5B50, 0xD7D4, 0x81EA, 0xD7D5, 0x6E0D,	0xD7D6, 0x5B57, 0xD7D7, 0x9B03, 0xD7D8, 0x68D5, 0xD7D9, 0x8E2A,
+	0xD7DA, 0x5B97, 0xD7DB, 0x7EFC, 0xD7DC, 0x603B, 0xD7DD, 0x7EB5,	0xD7DE, 0x90B9, 0xD7DF, 0x8D70, 0xD7E0, 0x594F, 0xD7E1, 0x63CD,
+	0xD7E2, 0x79DF, 0xD7E3, 0x8DB3, 0xD7E4, 0x5352, 0xD7E5, 0x65CF,	0xD7E6, 0x7956, 0xD7E7, 0x8BC5, 0xD7E8, 0x963B, 0xD7E9, 0x7EC4,
+	0xD7EA, 0x94BB, 0xD7EB, 0x7E82, 0xD7EC, 0x5634, 0xD7ED, 0x9189,	0xD7EE, 0x6700, 0xD7EF, 0x7F6A, 0xD7F0, 0x5C0A, 0xD7F1, 0x9075,
+	0xD7F2, 0x6628, 0xD7F3, 0x5DE6, 0xD7F4, 0x4F50, 0xD7F5, 0x67DE,	0xD7F6, 0x505A, 0xD7F7, 0x4F5C, 0xD7F8, 0x5750, 0xD7F9, 0x5EA7,
+	0xD840, 0x8C38, 0xD841, 0x8C39, 0xD842, 0x8C3A, 0xD843, 0x8C3B,	0xD844, 0x8C3C, 0xD845, 0x8C3D, 0xD846, 0x8C3E, 0xD847, 0x8C3F,
+	0xD848, 0x8C40, 0xD849, 0x8C42, 0xD84A, 0x8C43, 0xD84B, 0x8C44,	0xD84C, 0x8C45, 0xD84D, 0x8C48, 0xD84E, 0x8C4A, 0xD84F, 0x8C4B,
+	0xD850, 0x8C4D, 0xD851, 0x8C4E, 0xD852, 0x8C4F, 0xD853, 0x8C50,	0xD854, 0x8C51, 0xD855, 0x8C52, 0xD856, 0x8C53, 0xD857, 0x8C54,
+	0xD858, 0x8C56, 0xD859, 0x8C57, 0xD85A, 0x8C58, 0xD85B, 0x8C59,	0xD85C, 0x8C5B, 0xD85D, 0x8C5C, 0xD85E, 0x8C5D, 0xD85F, 0x8C5E,
+	0xD860, 0x8C5F, 0xD861, 0x8C60, 0xD862, 0x8C63, 0xD863, 0x8C64,	0xD864, 0x8C65, 0xD865, 0x8C66, 0xD866, 0x8C67, 0xD867, 0x8C68,
+	0xD868, 0x8C69, 0xD869, 0x8C6C, 0xD86A, 0x8C6D, 0xD86B, 0x8C6E,	0xD86C, 0x8C6F, 0xD86D, 0x8C70, 0xD86E, 0x8C71, 0xD86F, 0x8C72,
+	0xD870, 0x8C74, 0xD871, 0x8C75, 0xD872, 0x8C76, 0xD873, 0x8C77,	0xD874, 0x8C7B, 0xD875, 0x8C7C, 0xD876, 0x8C7D, 0xD877, 0x8C7E,
+	0xD878, 0x8C7F, 0xD879, 0x8C80, 0xD87A, 0x8C81, 0xD87B, 0x8C83,	0xD87C, 0x8C84, 0xD87D, 0x8C86, 0xD87E, 0x8C87, 0xD880, 0x8C88,
+	0xD881, 0x8C8B, 0xD882, 0x8C8D, 0xD883, 0x8C8E, 0xD884, 0x8C8F,	0xD885, 0x8C90, 0xD886, 0x8C91, 0xD887, 0x8C92, 0xD888, 0x8C93,
+	0xD889, 0x8C95, 0xD88A, 0x8C96, 0xD88B, 0x8C97, 0xD88C, 0x8C99,	0xD88D, 0x8C9A, 0xD88E, 0x8C9B, 0xD88F, 0x8C9C, 0xD890, 0x8C9D,
+	0xD891, 0x8C9E, 0xD892, 0x8C9F, 0xD893, 0x8CA0, 0xD894, 0x8CA1,	0xD895, 0x8CA2, 0xD896, 0x8CA3, 0xD897, 0x8CA4, 0xD898, 0x8CA5,
+	0xD899, 0x8CA6, 0xD89A, 0x8CA7, 0xD89B, 0x8CA8, 0xD89C, 0x8CA9,	0xD89D, 0x8CAA, 0xD89E, 0x8CAB, 0xD89F, 0x8CAC, 0xD8A0, 0x8CAD,
+	0xD8A1, 0x4E8D, 0xD8A2, 0x4E0C, 0xD8A3, 0x5140, 0xD8A4, 0x4E10,	0xD8A5, 0x5EFF, 0xD8A6, 0x5345, 0xD8A7, 0x4E15, 0xD8A8, 0x4E98,
+	0xD8A9, 0x4E1E, 0xD8AA, 0x9B32, 0xD8AB, 0x5B6C, 0xD8AC, 0x5669,	0xD8AD, 0x4E28, 0xD8AE, 0x79BA, 0xD8AF, 0x4E3F, 0xD8B0, 0x5315,
+	0xD8B1, 0x4E47, 0xD8B2, 0x592D, 0xD8B3, 0x723B, 0xD8B4, 0x536E,	0xD8B5, 0x6C10, 0xD8B6, 0x56DF, 0xD8B7, 0x80E4, 0xD8B8, 0x9997,
+	0xD8B9, 0x6BD3, 0xD8BA, 0x777E, 0xD8BB, 0x9F17, 0xD8BC, 0x4E36,	0xD8BD, 0x4E9F, 0xD8BE, 0x9F10, 0xD8BF, 0x4E5C, 0xD8C0, 0x4E69,
+	0xD8C1, 0x4E93, 0xD8C2, 0x8288, 0xD8C3, 0x5B5B, 0xD8C4, 0x556C,	0xD8C5, 0x560F, 0xD8C6, 0x4EC4, 0xD8C7, 0x538D, 0xD8C8, 0x539D,
+	0xD8C9, 0x53A3, 0xD8CA, 0x53A5, 0xD8CB, 0x53AE, 0xD8CC, 0x9765,	0xD8CD, 0x8D5D, 0xD8CE, 0x531A, 0xD8CF, 0x53F5, 0xD8D0, 0x5326,
+	0xD8D1, 0x532E, 0xD8D2, 0x533E, 0xD8D3, 0x8D5C, 0xD8D4, 0x5366,	0xD8D5, 0x5363, 0xD8D6, 0x5202, 0xD8D7, 0x5208, 0xD8D8, 0x520E,
+	0xD8D9, 0x522D, 0xD8DA, 0x5233, 0xD8DB, 0x523F, 0xD8DC, 0x5240,	0xD8DD, 0x524C, 0xD8DE, 0x525E, 0xD8DF, 0x5261, 0xD8E0, 0x525C,
+	0xD8E1, 0x84AF, 0xD8E2, 0x527D, 0xD8E3, 0x5282, 0xD8E4, 0x5281,	0xD8E5, 0x5290, 0xD8E6, 0x5293, 0xD8E7, 0x5182, 0xD8E8, 0x7F54,
+	0xD8E9, 0x4EBB, 0xD8EA, 0x4EC3, 0xD8EB, 0x4EC9, 0xD8EC, 0x4EC2,	0xD8ED, 0x4EE8, 0xD8EE, 0x4EE1, 0xD8EF, 0x4EEB, 0xD8F0, 0x4EDE,
+	0xD8F1, 0x4F1B, 0xD8F2, 0x4EF3, 0xD8F3, 0x4F22, 0xD8F4, 0x4F64,	0xD8F5, 0x4EF5, 0xD8F6, 0x4F25, 0xD8F7, 0x4F27, 0xD8F8, 0x4F09,
+	0xD8F9, 0x4F2B, 0xD8FA, 0x4F5E, 0xD8FB, 0x4F67, 0xD8FC, 0x6538,	0xD8FD, 0x4F5A, 0xD8FE, 0x4F5D, 0xD940, 0x8CAE, 0xD941, 0x8CAF,
+	0xD942, 0x8CB0, 0xD943, 0x8CB1, 0xD944, 0x8CB2, 0xD945, 0x8CB3,	0xD946, 0x8CB4, 0xD947, 0x8CB5, 0xD948, 0x8CB6, 0xD949, 0x8CB7,
+	0xD94A, 0x8CB8, 0xD94B, 0x8CB9, 0xD94C, 0x8CBA, 0xD94D, 0x8CBB,	0xD94E, 0x8CBC, 0xD94F, 0x8CBD, 0xD950, 0x8CBE, 0xD951, 0x8CBF,
+	0xD952, 0x8CC0, 0xD953, 0x8CC1, 0xD954, 0x8CC2, 0xD955, 0x8CC3,	0xD956, 0x8CC4, 0xD957, 0x8CC5, 0xD958, 0x8CC6, 0xD959, 0x8CC7,
+	0xD95A, 0x8CC8, 0xD95B, 0x8CC9, 0xD95C, 0x8CCA, 0xD95D, 0x8CCB,	0xD95E, 0x8CCC, 0xD95F, 0x8CCD, 0xD960, 0x8CCE, 0xD961, 0x8CCF,
+	0xD962, 0x8CD0, 0xD963, 0x8CD1, 0xD964, 0x8CD2, 0xD965, 0x8CD3,	0xD966, 0x8CD4, 0xD967, 0x8CD5, 0xD968, 0x8CD6, 0xD969, 0x8CD7,
+	0xD96A, 0x8CD8, 0xD96B, 0x8CD9, 0xD96C, 0x8CDA, 0xD96D, 0x8CDB,	0xD96E, 0x8CDC, 0xD96F, 0x8CDD, 0xD970, 0x8CDE, 0xD971, 0x8CDF,
+	0xD972, 0x8CE0, 0xD973, 0x8CE1, 0xD974, 0x8CE2, 0xD975, 0x8CE3,	0xD976, 0x8CE4, 0xD977, 0x8CE5, 0xD978, 0x8CE6, 0xD979, 0x8CE7,
+	0xD97A, 0x8CE8, 0xD97B, 0x8CE9, 0xD97C, 0x8CEA, 0xD97D, 0x8CEB,	0xD97E, 0x8CEC, 0xD980, 0x8CED, 0xD981, 0x8CEE, 0xD982, 0x8CEF,
+	0xD983, 0x8CF0, 0xD984, 0x8CF1, 0xD985, 0x8CF2, 0xD986, 0x8CF3,	0xD987, 0x8CF4, 0xD988, 0x8CF5, 0xD989, 0x8CF6, 0xD98A, 0x8CF7,
+	0xD98B, 0x8CF8, 0xD98C, 0x8CF9, 0xD98D, 0x8CFA, 0xD98E, 0x8CFB,	0xD98F, 0x8CFC, 0xD990, 0x8CFD, 0xD991, 0x8CFE, 0xD992, 0x8CFF,
+	0xD993, 0x8D00, 0xD994, 0x8D01, 0xD995, 0x8D02, 0xD996, 0x8D03,	0xD997, 0x8D04, 0xD998, 0x8D05, 0xD999, 0x8D06, 0xD99A, 0x8D07,
+	0xD99B, 0x8D08, 0xD99C, 0x8D09, 0xD99D, 0x8D0A, 0xD99E, 0x8D0B,	0xD99F, 0x8D0C, 0xD9A0, 0x8D0D, 0xD9A1, 0x4F5F, 0xD9A2, 0x4F57,
+	0xD9A3, 0x4F32, 0xD9A4, 0x4F3D, 0xD9A5, 0x4F76, 0xD9A6, 0x4F74,	0xD9A7, 0x4F91, 0xD9A8, 0x4F89, 0xD9A9, 0x4F83, 0xD9AA, 0x4F8F,
+	0xD9AB, 0x4F7E, 0xD9AC, 0x4F7B, 0xD9AD, 0x4FAA, 0xD9AE, 0x4F7C,	0xD9AF, 0x4FAC, 0xD9B0, 0x4F94, 0xD9B1, 0x4FE6, 0xD9B2, 0x4FE8,
+	0xD9B3, 0x4FEA, 0xD9B4, 0x4FC5, 0xD9B5, 0x4FDA, 0xD9B6, 0x4FE3,	0xD9B7, 0x4FDC, 0xD9B8, 0x4FD1, 0xD9B9, 0x4FDF, 0xD9BA, 0x4FF8,
+	0xD9BB, 0x5029, 0xD9BC, 0x504C, 0xD9BD, 0x4FF3, 0xD9BE, 0x502C,	0xD9BF, 0x500F, 0xD9C0, 0x502E, 0xD9C1, 0x502D, 0xD9C2, 0x4FFE,
+	0xD9C3, 0x501C, 0xD9C4, 0x500C, 0xD9C5, 0x5025, 0xD9C6, 0x5028,	0xD9C7, 0x507E, 0xD9C8, 0x5043, 0xD9C9, 0x5055, 0xD9CA, 0x5048,
+	0xD9CB, 0x504E, 0xD9CC, 0x506C, 0xD9CD, 0x507B, 0xD9CE, 0x50A5,	0xD9CF, 0x50A7, 0xD9D0, 0x50A9, 0xD9D1, 0x50BA, 0xD9D2, 0x50D6,
+	0xD9D3, 0x5106, 0xD9D4, 0x50ED, 0xD9D5, 0x50EC, 0xD9D6, 0x50E6,	0xD9D7, 0x50EE, 0xD9D8, 0x5107, 0xD9D9, 0x510B, 0xD9DA, 0x4EDD,
+	0xD9DB, 0x6C3D, 0xD9DC, 0x4F58, 0xD9DD, 0x4F65, 0xD9DE, 0x4FCE,	0xD9DF, 0x9FA0, 0xD9E0, 0x6C46, 0xD9E1, 0x7C74, 0xD9E2, 0x516E,
+	0xD9E3, 0x5DFD, 0xD9E4, 0x9EC9, 0xD9E5, 0x9998, 0xD9E6, 0x5181,	0xD9E7, 0x5914, 0xD9E8, 0x52F9, 0xD9E9, 0x530D, 0xD9EA, 0x8A07,
+	0xD9EB, 0x5310, 0xD9EC, 0x51EB, 0xD9ED, 0x5919, 0xD9EE, 0x5155,	0xD9EF, 0x4EA0, 0xD9F0, 0x5156, 0xD9F1, 0x4EB3, 0xD9F2, 0x886E,
+	0xD9F3, 0x88A4, 0xD9F4, 0x4EB5, 0xD9F5, 0x8114, 0xD9F6, 0x88D2,	0xD9F7, 0x7980, 0xD9F8, 0x5B34, 0xD9F9, 0x8803, 0xD9FA, 0x7FB8,
+	0xD9FB, 0x51AB, 0xD9FC, 0x51B1, 0xD9FD, 0x51BD, 0xD9FE, 0x51BC,	0xDA40, 0x8D0E, 0xDA41, 0x8D0F, 0xDA42, 0x8D10, 0xDA43, 0x8D11,
+	0xDA44, 0x8D12, 0xDA45, 0x8D13, 0xDA46, 0x8D14, 0xDA47, 0x8D15,	0xDA48, 0x8D16, 0xDA49, 0x8D17, 0xDA4A, 0x8D18, 0xDA4B, 0x8D19,
+	0xDA4C, 0x8D1A, 0xDA4D, 0x8D1B, 0xDA4E, 0x8D1C, 0xDA4F, 0x8D20,	0xDA50, 0x8D51, 0xDA51, 0x8D52, 0xDA52, 0x8D57, 0xDA53, 0x8D5F,
+	0xDA54, 0x8D65, 0xDA55, 0x8D68, 0xDA56, 0x8D69, 0xDA57, 0x8D6A,	0xDA58, 0x8D6C, 0xDA59, 0x8D6E, 0xDA5A, 0x8D6F, 0xDA5B, 0x8D71,
+	0xDA5C, 0x8D72, 0xDA5D, 0x8D78, 0xDA5E, 0x8D79, 0xDA5F, 0x8D7A,	0xDA60, 0x8D7B, 0xDA61, 0x8D7C, 0xDA62, 0x8D7D, 0xDA63, 0x8D7E,
+	0xDA64, 0x8D7F, 0xDA65, 0x8D80, 0xDA66, 0x8D82, 0xDA67, 0x8D83,	0xDA68, 0x8D86, 0xDA69, 0x8D87, 0xDA6A, 0x8D88, 0xDA6B, 0x8D89,
+	0xDA6C, 0x8D8C, 0xDA6D, 0x8D8D, 0xDA6E, 0x8D8E, 0xDA6F, 0x8D8F,	0xDA70, 0x8D90, 0xDA71, 0x8D92, 0xDA72, 0x8D93, 0xDA73, 0x8D95,
+	0xDA74, 0x8D96, 0xDA75, 0x8D97, 0xDA76, 0x8D98, 0xDA77, 0x8D99,	0xDA78, 0x8D9A, 0xDA79, 0x8D9B, 0xDA7A, 0x8D9C, 0xDA7B, 0x8D9D,
+	0xDA7C, 0x8D9E, 0xDA7D, 0x8DA0, 0xDA7E, 0x8DA1, 0xDA80, 0x8DA2,	0xDA81, 0x8DA4, 0xDA82, 0x8DA5, 0xDA83, 0x8DA6, 0xDA84, 0x8DA7,
+	0xDA85, 0x8DA8, 0xDA86, 0x8DA9, 0xDA87, 0x8DAA, 0xDA88, 0x8DAB,	0xDA89, 0x8DAC, 0xDA8A, 0x8DAD, 0xDA8B, 0x8DAE, 0xDA8C, 0x8DAF,
+	0xDA8D, 0x8DB0, 0xDA8E, 0x8DB2, 0xDA8F, 0x8DB6, 0xDA90, 0x8DB7,	0xDA91, 0x8DB9, 0xDA92, 0x8DBB, 0xDA93, 0x8DBD, 0xDA94, 0x8DC0,
+	0xDA95, 0x8DC1, 0xDA96, 0x8DC2, 0xDA97, 0x8DC5, 0xDA98, 0x8DC7,	0xDA99, 0x8DC8, 0xDA9A, 0x8DC9, 0xDA9B, 0x8DCA, 0xDA9C, 0x8DCD,
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+	0xE1D3, 0x5D4A, 0xE1D4, 0x5D69, 0xE1D5, 0x5D74, 0xE1D6, 0x5D82,	0xE1D7, 0x5D99, 0xE1D8, 0x5D9D, 0xE1D9, 0x8C73, 0xE1DA, 0x5DB7,
+	0xE1DB, 0x5DC5, 0xE1DC, 0x5F73, 0xE1DD, 0x5F77, 0xE1DE, 0x5F82,	0xE1DF, 0x5F87, 0xE1E0, 0x5F89, 0xE1E1, 0x5F8C, 0xE1E2, 0x5F95,
+	0xE1E3, 0x5F99, 0xE1E4, 0x5F9C, 0xE1E5, 0x5FA8, 0xE1E6, 0x5FAD,	0xE1E7, 0x5FB5, 0xE1E8, 0x5FBC, 0xE1E9, 0x8862, 0xE1EA, 0x5F61,
+	0xE1EB, 0x72AD, 0xE1EC, 0x72B0, 0xE1ED, 0x72B4, 0xE1EE, 0x72B7,	0xE1EF, 0x72B8, 0xE1F0, 0x72C3, 0xE1F1, 0x72C1, 0xE1F2, 0x72CE,
+	0xE1F3, 0x72CD, 0xE1F4, 0x72D2, 0xE1F5, 0x72E8, 0xE1F6, 0x72EF,	0xE1F7, 0x72E9, 0xE1F8, 0x72F2, 0xE1F9, 0x72F4, 0xE1FA, 0x72F7,
+	0xE1FB, 0x7301, 0xE1FC, 0x72F3, 0xE1FD, 0x7303, 0xE1FE, 0x72FA,	0xE240, 0x91E6, 0xE241, 0x91E7, 0xE242, 0x91E8, 0xE243, 0x91E9,
+	0xE244, 0x91EA, 0xE245, 0x91EB, 0xE246, 0x91EC, 0xE247, 0x91ED,	0xE248, 0x91EE, 0xE249, 0x91EF, 0xE24A, 0x91F0, 0xE24B, 0x91F1,
+	0xE24C, 0x91F2, 0xE24D, 0x91F3, 0xE24E, 0x91F4, 0xE24F, 0x91F5,	0xE250, 0x91F6, 0xE251, 0x91F7, 0xE252, 0x91F8, 0xE253, 0x91F9,
+	0xE254, 0x91FA, 0xE255, 0x91FB, 0xE256, 0x91FC, 0xE257, 0x91FD,	0xE258, 0x91FE, 0xE259, 0x91FF, 0xE25A, 0x9200, 0xE25B, 0x9201,
+	0xE25C, 0x9202, 0xE25D, 0x9203, 0xE25E, 0x9204, 0xE25F, 0x9205,	0xE260, 0x9206, 0xE261, 0x9207, 0xE262, 0x9208, 0xE263, 0x9209,
+	0xE264, 0x920A, 0xE265, 0x920B, 0xE266, 0x920C, 0xE267, 0x920D,	0xE268, 0x920E, 0xE269, 0x920F, 0xE26A, 0x9210, 0xE26B, 0x9211,
+	0xE26C, 0x9212, 0xE26D, 0x9213, 0xE26E, 0x9214, 0xE26F, 0x9215,	0xE270, 0x9216, 0xE271, 0x9217, 0xE272, 0x9218, 0xE273, 0x9219,
+	0xE274, 0x921A, 0xE275, 0x921B, 0xE276, 0x921C, 0xE277, 0x921D,	0xE278, 0x921E, 0xE279, 0x921F, 0xE27A, 0x9220, 0xE27B, 0x9221,
+	0xE27C, 0x9222, 0xE27D, 0x9223, 0xE27E, 0x9224, 0xE280, 0x9225,	0xE281, 0x9226, 0xE282, 0x9227, 0xE283, 0x9228, 0xE284, 0x9229,
+	0xE285, 0x922A, 0xE286, 0x922B, 0xE287, 0x922C, 0xE288, 0x922D,	0xE289, 0x922E, 0xE28A, 0x922F, 0xE28B, 0x9230, 0xE28C, 0x9231,
+	0xE28D, 0x9232, 0xE28E, 0x9233, 0xE28F, 0x9234, 0xE290, 0x9235,	0xE291, 0x9236, 0xE292, 0x9237, 0xE293, 0x9238, 0xE294, 0x9239,
+	0xE295, 0x923A, 0xE296, 0x923B, 0xE297, 0x923C, 0xE298, 0x923D,	0xE299, 0x923E, 0xE29A, 0x923F, 0xE29B, 0x9240, 0xE29C, 0x9241,
+	0xE29D, 0x9242, 0xE29E, 0x9243, 0xE29F, 0x9244, 0xE2A0, 0x9245,	0xE2A1, 0x72FB, 0xE2A2, 0x7317, 0xE2A3, 0x7313, 0xE2A4, 0x7321,
+	0xE2A5, 0x730A, 0xE2A6, 0x731E, 0xE2A7, 0x731D, 0xE2A8, 0x7315,	0xE2A9, 0x7322, 0xE2AA, 0x7339, 0xE2AB, 0x7325, 0xE2AC, 0x732C,
+	0xE2AD, 0x7338, 0xE2AE, 0x7331, 0xE2AF, 0x7350, 0xE2B0, 0x734D,	0xE2B1, 0x7357, 0xE2B2, 0x7360, 0xE2B3, 0x736C, 0xE2B4, 0x736F,
+	0xE2B5, 0x737E, 0xE2B6, 0x821B, 0xE2B7, 0x5925, 0xE2B8, 0x98E7,	0xE2B9, 0x5924, 0xE2BA, 0x5902, 0xE2BB, 0x9963, 0xE2BC, 0x9967,
+	0xE2BD, 0x9968, 0xE2BE, 0x9969, 0xE2BF, 0x996A, 0xE2C0, 0x996B,	0xE2C1, 0x996C, 0xE2C2, 0x9974, 0xE2C3, 0x9977, 0xE2C4, 0x997D,
+	0xE2C5, 0x9980, 0xE2C6, 0x9984, 0xE2C7, 0x9987, 0xE2C8, 0x998A,	0xE2C9, 0x998D, 0xE2CA, 0x9990, 0xE2CB, 0x9991, 0xE2CC, 0x9993,
+	0xE2CD, 0x9994, 0xE2CE, 0x9995, 0xE2CF, 0x5E80, 0xE2D0, 0x5E91,	0xE2D1, 0x5E8B, 0xE2D2, 0x5E96, 0xE2D3, 0x5EA5, 0xE2D4, 0x5EA0,
+	0xE2D5, 0x5EB9, 0xE2D6, 0x5EB5, 0xE2D7, 0x5EBE, 0xE2D8, 0x5EB3,	0xE2D9, 0x8D53, 0xE2DA, 0x5ED2, 0xE2DB, 0x5ED1, 0xE2DC, 0x5EDB,
+	0xE2DD, 0x5EE8, 0xE2DE, 0x5EEA, 0xE2DF, 0x81BA, 0xE2E0, 0x5FC4,	0xE2E1, 0x5FC9, 0xE2E2, 0x5FD6, 0xE2E3, 0x5FCF, 0xE2E4, 0x6003,
+	0xE2E5, 0x5FEE, 0xE2E6, 0x6004, 0xE2E7, 0x5FE1, 0xE2E8, 0x5FE4,	0xE2E9, 0x5FFE, 0xE2EA, 0x6005, 0xE2EB, 0x6006, 0xE2EC, 0x5FEA,
+	0xE2ED, 0x5FED, 0xE2EE, 0x5FF8, 0xE2EF, 0x6019, 0xE2F0, 0x6035,	0xE2F1, 0x6026, 0xE2F2, 0x601B, 0xE2F3, 0x600F, 0xE2F4, 0x600D,
+	0xE2F5, 0x6029, 0xE2F6, 0x602B, 0xE2F7, 0x600A, 0xE2F8, 0x603F,	0xE2F9, 0x6021, 0xE2FA, 0x6078, 0xE2FB, 0x6079, 0xE2FC, 0x607B,
+	0xE2FD, 0x607A, 0xE2FE, 0x6042, 0xE340, 0x9246, 0xE341, 0x9247,	0xE342, 0x9248, 0xE343, 0x9249, 0xE344, 0x924A, 0xE345, 0x924B,
+	0xE346, 0x924C, 0xE347, 0x924D, 0xE348, 0x924E, 0xE349, 0x924F,	0xE34A, 0x9250, 0xE34B, 0x9251, 0xE34C, 0x9252, 0xE34D, 0x9253,
+	0xE34E, 0x9254, 0xE34F, 0x9255, 0xE350, 0x9256, 0xE351, 0x9257,	0xE352, 0x9258, 0xE353, 0x9259, 0xE354, 0x925A, 0xE355, 0x925B,
+	0xE356, 0x925C, 0xE357, 0x925D, 0xE358, 0x925E, 0xE359, 0x925F,	0xE35A, 0x9260, 0xE35B, 0x9261, 0xE35C, 0x9262, 0xE35D, 0x9263,
+	0xE35E, 0x9264, 0xE35F, 0x9265, 0xE360, 0x9266, 0xE361, 0x9267,	0xE362, 0x9268, 0xE363, 0x9269, 0xE364, 0x926A, 0xE365, 0x926B,
+	0xE366, 0x926C, 0xE367, 0x926D, 0xE368, 0x926E, 0xE369, 0x926F,	0xE36A, 0x9270, 0xE36B, 0x9271, 0xE36C, 0x9272, 0xE36D, 0x9273,
+	0xE36E, 0x9275, 0xE36F, 0x9276, 0xE370, 0x9277, 0xE371, 0x9278,	0xE372, 0x9279, 0xE373, 0x927A, 0xE374, 0x927B, 0xE375, 0x927C,
+	0xE376, 0x927D, 0xE377, 0x927E, 0xE378, 0x927F, 0xE379, 0x9280,	0xE37A, 0x9281, 0xE37B, 0x9282, 0xE37C, 0x9283, 0xE37D, 0x9284,
+	0xE37E, 0x9285, 0xE380, 0x9286, 0xE381, 0x9287, 0xE382, 0x9288,	0xE383, 0x9289, 0xE384, 0x928A, 0xE385, 0x928B, 0xE386, 0x928C,
+	0xE387, 0x928D, 0xE388, 0x928F, 0xE389, 0x9290, 0xE38A, 0x9291,	0xE38B, 0x9292, 0xE38C, 0x9293, 0xE38D, 0x9294, 0xE38E, 0x9295,
+	0xE38F, 0x9296, 0xE390, 0x9297, 0xE391, 0x9298, 0xE392, 0x9299,	0xE393, 0x929A, 0xE394, 0x929B, 0xE395, 0x929C, 0xE396, 0x929D,
+	0xE397, 0x929E, 0xE398, 0x929F, 0xE399, 0x92A0, 0xE39A, 0x92A1,	0xE39B, 0x92A2, 0xE39C, 0x92A3, 0xE39D, 0x92A4, 0xE39E, 0x92A5,
+	0xE39F, 0x92A6, 0xE3A0, 0x92A7, 0xE3A1, 0x606A, 0xE3A2, 0x607D,	0xE3A3, 0x6096, 0xE3A4, 0x609A, 0xE3A5, 0x60AD, 0xE3A6, 0x609D,
+	0xE3A7, 0x6083, 0xE3A8, 0x6092, 0xE3A9, 0x608C, 0xE3AA, 0x609B,	0xE3AB, 0x60EC, 0xE3AC, 0x60BB, 0xE3AD, 0x60B1, 0xE3AE, 0x60DD,
+	0xE3AF, 0x60D8, 0xE3B0, 0x60C6, 0xE3B1, 0x60DA, 0xE3B2, 0x60B4,	0xE3B3, 0x6120, 0xE3B4, 0x6126, 0xE3B5, 0x6115, 0xE3B6, 0x6123,
+	0xE3B7, 0x60F4, 0xE3B8, 0x6100, 0xE3B9, 0x610E, 0xE3BA, 0x612B,	0xE3BB, 0x614A, 0xE3BC, 0x6175, 0xE3BD, 0x61AC, 0xE3BE, 0x6194,
+	0xE3BF, 0x61A7, 0xE3C0, 0x61B7, 0xE3C1, 0x61D4, 0xE3C2, 0x61F5,	0xE3C3, 0x5FDD, 0xE3C4, 0x96B3, 0xE3C5, 0x95E9, 0xE3C6, 0x95EB,
+	0xE3C7, 0x95F1, 0xE3C8, 0x95F3, 0xE3C9, 0x95F5, 0xE3CA, 0x95F6,	0xE3CB, 0x95FC, 0xE3CC, 0x95FE, 0xE3CD, 0x9603, 0xE3CE, 0x9604,
+	0xE3CF, 0x9606, 0xE3D0, 0x9608, 0xE3D1, 0x960A, 0xE3D2, 0x960B,	0xE3D3, 0x960C, 0xE3D4, 0x960D, 0xE3D5, 0x960F, 0xE3D6, 0x9612,
+	0xE3D7, 0x9615, 0xE3D8, 0x9616, 0xE3D9, 0x9617, 0xE3DA, 0x9619,	0xE3DB, 0x961A, 0xE3DC, 0x4E2C, 0xE3DD, 0x723F, 0xE3DE, 0x6215,
+	0xE3DF, 0x6C35, 0xE3E0, 0x6C54, 0xE3E1, 0x6C5C, 0xE3E2, 0x6C4A,	0xE3E3, 0x6CA3, 0xE3E4, 0x6C85, 0xE3E5, 0x6C90, 0xE3E6, 0x6C94,
+	0xE3E7, 0x6C8C, 0xE3E8, 0x6C68, 0xE3E9, 0x6C69, 0xE3EA, 0x6C74,	0xE3EB, 0x6C76, 0xE3EC, 0x6C86, 0xE3ED, 0x6CA9, 0xE3EE, 0x6CD0,
+	0xE3EF, 0x6CD4, 0xE3F0, 0x6CAD, 0xE3F1, 0x6CF7, 0xE3F2, 0x6CF8,	0xE3F3, 0x6CF1, 0xE3F4, 0x6CD7, 0xE3F5, 0x6CB2, 0xE3F6, 0x6CE0,
+	0xE3F7, 0x6CD6, 0xE3F8, 0x6CFA, 0xE3F9, 0x6CEB, 0xE3FA, 0x6CEE,	0xE3FB, 0x6CB1, 0xE3FC, 0x6CD3, 0xE3FD, 0x6CEF, 0xE3FE, 0x6CFE,
+	0xE440, 0x92A8, 0xE441, 0x92A9, 0xE442, 0x92AA, 0xE443, 0x92AB,	0xE444, 0x92AC, 0xE445, 0x92AD, 0xE446, 0x92AF, 0xE447, 0x92B0,
+	0xE448, 0x92B1, 0xE449, 0x92B2, 0xE44A, 0x92B3, 0xE44B, 0x92B4,	0xE44C, 0x92B5, 0xE44D, 0x92B6, 0xE44E, 0x92B7, 0xE44F, 0x92B8,
+	0xE450, 0x92B9, 0xE451, 0x92BA, 0xE452, 0x92BB, 0xE453, 0x92BC,	0xE454, 0x92BD, 0xE455, 0x92BE, 0xE456, 0x92BF, 0xE457, 0x92C0,
+	0xE458, 0x92C1, 0xE459, 0x92C2, 0xE45A, 0x92C3, 0xE45B, 0x92C4,	0xE45C, 0x92C5, 0xE45D, 0x92C6, 0xE45E, 0x92C7, 0xE45F, 0x92C9,
+	0xE460, 0x92CA, 0xE461, 0x92CB, 0xE462, 0x92CC, 0xE463, 0x92CD,	0xE464, 0x92CE, 0xE465, 0x92CF, 0xE466, 0x92D0, 0xE467, 0x92D1,
+	0xE468, 0x92D2, 0xE469, 0x92D3, 0xE46A, 0x92D4, 0xE46B, 0x92D5,	0xE46C, 0x92D6, 0xE46D, 0x92D7, 0xE46E, 0x92D8, 0xE46F, 0x92D9,
+	0xE470, 0x92DA, 0xE471, 0x92DB, 0xE472, 0x92DC, 0xE473, 0x92DD,	0xE474, 0x92DE, 0xE475, 0x92DF, 0xE476, 0x92E0, 0xE477, 0x92E1,
+	0xE478, 0x92E2, 0xE479, 0x92E3, 0xE47A, 0x92E4, 0xE47B, 0x92E5,	0xE47C, 0x92E6, 0xE47D, 0x92E7, 0xE47E, 0x92E8, 0xE480, 0x92E9,
+	0xE481, 0x92EA, 0xE482, 0x92EB, 0xE483, 0x92EC, 0xE484, 0x92ED,	0xE485, 0x92EE, 0xE486, 0x92EF, 0xE487, 0x92F0, 0xE488, 0x92F1,
+	0xE489, 0x92F2, 0xE48A, 0x92F3, 0xE48B, 0x92F4, 0xE48C, 0x92F5,	0xE48D, 0x92F6, 0xE48E, 0x92F7, 0xE48F, 0x92F8, 0xE490, 0x92F9,
+	0xE491, 0x92FA, 0xE492, 0x92FB, 0xE493, 0x92FC, 0xE494, 0x92FD,	0xE495, 0x92FE, 0xE496, 0x92FF, 0xE497, 0x9300, 0xE498, 0x9301,
+	0xE499, 0x9302, 0xE49A, 0x9303, 0xE49B, 0x9304, 0xE49C, 0x9305,	0xE49D, 0x9306, 0xE49E, 0x9307, 0xE49F, 0x9308, 0xE4A0, 0x9309,
+	0xE4A1, 0x6D39, 0xE4A2, 0x6D27, 0xE4A3, 0x6D0C, 0xE4A4, 0x6D43,	0xE4A5, 0x6D48, 0xE4A6, 0x6D07, 0xE4A7, 0x6D04, 0xE4A8, 0x6D19,
+	0xE4A9, 0x6D0E, 0xE4AA, 0x6D2B, 0xE4AB, 0x6D4D, 0xE4AC, 0x6D2E,	0xE4AD, 0x6D35, 0xE4AE, 0x6D1A, 0xE4AF, 0x6D4F, 0xE4B0, 0x6D52,
+	0xE4B1, 0x6D54, 0xE4B2, 0x6D33, 0xE4B3, 0x6D91, 0xE4B4, 0x6D6F,	0xE4B5, 0x6D9E, 0xE4B6, 0x6DA0, 0xE4B7, 0x6D5E, 0xE4B8, 0x6D93,
+	0xE4B9, 0x6D94, 0xE4BA, 0x6D5C, 0xE4BB, 0x6D60, 0xE4BC, 0x6D7C,	0xE4BD, 0x6D63, 0xE4BE, 0x6E1A, 0xE4BF, 0x6DC7, 0xE4C0, 0x6DC5,
+	0xE4C1, 0x6DDE, 0xE4C2, 0x6E0E, 0xE4C3, 0x6DBF, 0xE4C4, 0x6DE0,	0xE4C5, 0x6E11, 0xE4C6, 0x6DE6, 0xE4C7, 0x6DDD, 0xE4C8, 0x6DD9,
+	0xE4C9, 0x6E16, 0xE4CA, 0x6DAB, 0xE4CB, 0x6E0C, 0xE4CC, 0x6DAE,	0xE4CD, 0x6E2B, 0xE4CE, 0x6E6E, 0xE4CF, 0x6E4E, 0xE4D0, 0x6E6B,
+	0xE4D1, 0x6EB2, 0xE4D2, 0x6E5F, 0xE4D3, 0x6E86, 0xE4D4, 0x6E53,	0xE4D5, 0x6E54, 0xE4D6, 0x6E32, 0xE4D7, 0x6E25, 0xE4D8, 0x6E44,
+	0xE4D9, 0x6EDF, 0xE4DA, 0x6EB1, 0xE4DB, 0x6E98, 0xE4DC, 0x6EE0,	0xE4DD, 0x6F2D, 0xE4DE, 0x6EE2, 0xE4DF, 0x6EA5, 0xE4E0, 0x6EA7,
+	0xE4E1, 0x6EBD, 0xE4E2, 0x6EBB, 0xE4E3, 0x6EB7, 0xE4E4, 0x6ED7,	0xE4E5, 0x6EB4, 0xE4E6, 0x6ECF, 0xE4E7, 0x6E8F, 0xE4E8, 0x6EC2,
+	0xE4E9, 0x6E9F, 0xE4EA, 0x6F62, 0xE4EB, 0x6F46, 0xE4EC, 0x6F47,	0xE4ED, 0x6F24, 0xE4EE, 0x6F15, 0xE4EF, 0x6EF9, 0xE4F0, 0x6F2F,
+	0xE4F1, 0x6F36, 0xE4F2, 0x6F4B, 0xE4F3, 0x6F74, 0xE4F4, 0x6F2A,	0xE4F5, 0x6F09, 0xE4F6, 0x6F29, 0xE4F7, 0x6F89, 0xE4F8, 0x6F8D,
+	0xE4F9, 0x6F8C, 0xE4FA, 0x6F78, 0xE4FB, 0x6F72, 0xE4FC, 0x6F7C,	0xE4FD, 0x6F7A, 0xE4FE, 0x6FD1, 0xE540, 0x930A, 0xE541, 0x930B,
+	0xE542, 0x930C, 0xE543, 0x930D, 0xE544, 0x930E, 0xE545, 0x930F,	0xE546, 0x9310, 0xE547, 0x9311, 0xE548, 0x9312, 0xE549, 0x9313,
+	0xE54A, 0x9314, 0xE54B, 0x9315, 0xE54C, 0x9316, 0xE54D, 0x9317,	0xE54E, 0x9318, 0xE54F, 0x9319, 0xE550, 0x931A, 0xE551, 0x931B,
+	0xE552, 0x931C, 0xE553, 0x931D, 0xE554, 0x931E, 0xE555, 0x931F,	0xE556, 0x9320, 0xE557, 0x9321, 0xE558, 0x9322, 0xE559, 0x9323,
+	0xE55A, 0x9324, 0xE55B, 0x9325, 0xE55C, 0x9326, 0xE55D, 0x9327,	0xE55E, 0x9328, 0xE55F, 0x9329, 0xE560, 0x932A, 0xE561, 0x932B,
+	0xE562, 0x932C, 0xE563, 0x932D, 0xE564, 0x932E, 0xE565, 0x932F,	0xE566, 0x9330, 0xE567, 0x9331, 0xE568, 0x9332, 0xE569, 0x9333,
+	0xE56A, 0x9334, 0xE56B, 0x9335, 0xE56C, 0x9336, 0xE56D, 0x9337,	0xE56E, 0x9338, 0xE56F, 0x9339, 0xE570, 0x933A, 0xE571, 0x933B,
+	0xE572, 0x933C, 0xE573, 0x933D, 0xE574, 0x933F, 0xE575, 0x9340,	0xE576, 0x9341, 0xE577, 0x9342, 0xE578, 0x9343, 0xE579, 0x9344,
+	0xE57A, 0x9345, 0xE57B, 0x9346, 0xE57C, 0x9347, 0xE57D, 0x9348,	0xE57E, 0x9349, 0xE580, 0x934A, 0xE581, 0x934B, 0xE582, 0x934C,
+	0xE583, 0x934D, 0xE584, 0x934E, 0xE585, 0x934F, 0xE586, 0x9350,	0xE587, 0x9351, 0xE588, 0x9352, 0xE589, 0x9353, 0xE58A, 0x9354,
+	0xE58B, 0x9355, 0xE58C, 0x9356, 0xE58D, 0x9357, 0xE58E, 0x9358,	0xE58F, 0x9359, 0xE590, 0x935A, 0xE591, 0x935B, 0xE592, 0x935C,
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+	0xE59B, 0x9365, 0xE59C, 0x9366, 0xE59D, 0x9367, 0xE59E, 0x9368,	0xE59F, 0x9369, 0xE5A0, 0x936B, 0xE5A1, 0x6FC9, 0xE5A2, 0x6FA7,
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+	0xF0B1, 0x9E28, 0xF0B2, 0x9E29, 0xF0B3, 0x9E2A, 0xF0B4, 0x9E2B,	0xF0B5, 0x9E2C, 0xF0B6, 0x9E32, 0xF0B7, 0x9E31, 0xF0B8, 0x9E36,
+	0xF0B9, 0x9E38, 0xF0BA, 0x9E37, 0xF0BB, 0x9E39, 0xF0BC, 0x9E3A,	0xF0BD, 0x9E3E, 0xF0BE, 0x9E41, 0xF0BF, 0x9E42, 0xF0C0, 0x9E44,
+	0xF0C1, 0x9E46, 0xF0C2, 0x9E47, 0xF0C3, 0x9E48, 0xF0C4, 0x9E49,	0xF0C5, 0x9E4B, 0xF0C6, 0x9E4C, 0xF0C7, 0x9E4E, 0xF0C8, 0x9E51,
+	0xF0C9, 0x9E55, 0xF0CA, 0x9E57, 0xF0CB, 0x9E5A, 0xF0CC, 0x9E5B,	0xF0CD, 0x9E5C, 0xF0CE, 0x9E5E, 0xF0CF, 0x9E63, 0xF0D0, 0x9E66,
+	0xF0D1, 0x9E67, 0xF0D2, 0x9E68, 0xF0D3, 0x9E69, 0xF0D4, 0x9E6A,	0xF0D5, 0x9E6B, 0xF0D6, 0x9E6C, 0xF0D7, 0x9E71, 0xF0D8, 0x9E6D,
+	0xF0D9, 0x9E73, 0xF0DA, 0x7592, 0xF0DB, 0x7594, 0xF0DC, 0x7596,	0xF0DD, 0x75A0, 0xF0DE, 0x759D, 0xF0DF, 0x75AC, 0xF0E0, 0x75A3,
+	0xF0E1, 0x75B3, 0xF0E2, 0x75B4, 0xF0E3, 0x75B8, 0xF0E4, 0x75C4,	0xF0E5, 0x75B1, 0xF0E6, 0x75B0, 0xF0E7, 0x75C3, 0xF0E8, 0x75C2,
+	0xF0E9, 0x75D6, 0xF0EA, 0x75CD, 0xF0EB, 0x75E3, 0xF0EC, 0x75E8,	0xF0ED, 0x75E6, 0xF0EE, 0x75E4, 0xF0EF, 0x75EB, 0xF0F0, 0x75E7,
+	0xF0F1, 0x7603, 0xF0F2, 0x75F1, 0xF0F3, 0x75FC, 0xF0F4, 0x75FF,	0xF0F5, 0x7610, 0xF0F6, 0x7600, 0xF0F7, 0x7605, 0xF0F8, 0x760C,
+	0xF0F9, 0x7617, 0xF0FA, 0x760A, 0xF0FB, 0x7625, 0xF0FC, 0x7618,	0xF0FD, 0x7615, 0xF0FE, 0x7619, 0xF140, 0x998C, 0xF141, 0x998E,
+	0xF142, 0x999A, 0xF143, 0x999B, 0xF144, 0x999C, 0xF145, 0x999D,	0xF146, 0x999E, 0xF147, 0x999F, 0xF148, 0x99A0, 0xF149, 0x99A1,
+	0xF14A, 0x99A2, 0xF14B, 0x99A3, 0xF14C, 0x99A4, 0xF14D, 0x99A6,	0xF14E, 0x99A7, 0xF14F, 0x99A9, 0xF150, 0x99AA, 0xF151, 0x99AB,
+	0xF152, 0x99AC, 0xF153, 0x99AD, 0xF154, 0x99AE, 0xF155, 0x99AF,	0xF156, 0x99B0, 0xF157, 0x99B1, 0xF158, 0x99B2, 0xF159, 0x99B3,
+	0xF15A, 0x99B4, 0xF15B, 0x99B5, 0xF15C, 0x99B6, 0xF15D, 0x99B7,	0xF15E, 0x99B8, 0xF15F, 0x99B9, 0xF160, 0x99BA, 0xF161, 0x99BB,
+	0xF162, 0x99BC, 0xF163, 0x99BD, 0xF164, 0x99BE, 0xF165, 0x99BF,	0xF166, 0x99C0, 0xF167, 0x99C1, 0xF168, 0x99C2, 0xF169, 0x99C3,
+	0xF16A, 0x99C4, 0xF16B, 0x99C5, 0xF16C, 0x99C6, 0xF16D, 0x99C7,	0xF16E, 0x99C8, 0xF16F, 0x99C9, 0xF170, 0x99CA, 0xF171, 0x99CB,
+	0xF172, 0x99CC, 0xF173, 0x99CD, 0xF174, 0x99CE, 0xF175, 0x99CF,	0xF176, 0x99D0, 0xF177, 0x99D1, 0xF178, 0x99D2, 0xF179, 0x99D3,
+	0xF17A, 0x99D4, 0xF17B, 0x99D5, 0xF17C, 0x99D6, 0xF17D, 0x99D7,	0xF17E, 0x99D8, 0xF180, 0x99D9, 0xF181, 0x99DA, 0xF182, 0x99DB,
+	0xF183, 0x99DC, 0xF184, 0x99DD, 0xF185, 0x99DE, 0xF186, 0x99DF,	0xF187, 0x99E0, 0xF188, 0x99E1, 0xF189, 0x99E2, 0xF18A, 0x99E3,
+	0xF18B, 0x99E4, 0xF18C, 0x99E5, 0xF18D, 0x99E6, 0xF18E, 0x99E7,	0xF18F, 0x99E8, 0xF190, 0x99E9, 0xF191, 0x99EA, 0xF192, 0x99EB,
+	0xF193, 0x99EC, 0xF194, 0x99ED, 0xF195, 0x99EE, 0xF196, 0x99EF,	0xF197, 0x99F0, 0xF198, 0x99F1, 0xF199, 0x99F2, 0xF19A, 0x99F3,
+	0xF19B, 0x99F4, 0xF19C, 0x99F5, 0xF19D, 0x99F6, 0xF19E, 0x99F7,	0xF19F, 0x99F8, 0xF1A0, 0x99F9, 0xF1A1, 0x761B, 0xF1A2, 0x763C,
+	0xF1A3, 0x7622, 0xF1A4, 0x7620, 0xF1A5, 0x7640, 0xF1A6, 0x762D,	0xF1A7, 0x7630, 0xF1A8, 0x763F, 0xF1A9, 0x7635, 0xF1AA, 0x7643,
+	0xF1AB, 0x763E, 0xF1AC, 0x7633, 0xF1AD, 0x764D, 0xF1AE, 0x765E,	0xF1AF, 0x7654, 0xF1B0, 0x765C, 0xF1B1, 0x7656, 0xF1B2, 0x766B,
+	0xF1B3, 0x766F, 0xF1B4, 0x7FCA, 0xF1B5, 0x7AE6, 0xF1B6, 0x7A78,	0xF1B7, 0x7A79, 0xF1B8, 0x7A80, 0xF1B9, 0x7A86, 0xF1BA, 0x7A88,
+	0xF1BB, 0x7A95, 0xF1BC, 0x7AA6, 0xF1BD, 0x7AA0, 0xF1BE, 0x7AAC,	0xF1BF, 0x7AA8, 0xF1C0, 0x7AAD, 0xF1C1, 0x7AB3, 0xF1C2, 0x8864,
+	0xF1C3, 0x8869, 0xF1C4, 0x8872, 0xF1C5, 0x887D, 0xF1C6, 0x887F,	0xF1C7, 0x8882, 0xF1C8, 0x88A2, 0xF1C9, 0x88C6, 0xF1CA, 0x88B7,
+	0xF1CB, 0x88BC, 0xF1CC, 0x88C9, 0xF1CD, 0x88E2, 0xF1CE, 0x88CE,	0xF1CF, 0x88E3, 0xF1D0, 0x88E5, 0xF1D1, 0x88F1, 0xF1D2, 0x891A,
+	0xF1D3, 0x88FC, 0xF1D4, 0x88E8, 0xF1D5, 0x88FE, 0xF1D6, 0x88F0,	0xF1D7, 0x8921, 0xF1D8, 0x8919, 0xF1D9, 0x8913, 0xF1DA, 0x891B,
+	0xF1DB, 0x890A, 0xF1DC, 0x8934, 0xF1DD, 0x892B, 0xF1DE, 0x8936,	0xF1DF, 0x8941, 0xF1E0, 0x8966, 0xF1E1, 0x897B, 0xF1E2, 0x758B,
+	0xF1E3, 0x80E5, 0xF1E4, 0x76B2, 0xF1E5, 0x76B4, 0xF1E6, 0x77DC,	0xF1E7, 0x8012, 0xF1E8, 0x8014, 0xF1E9, 0x8016, 0xF1EA, 0x801C,
+	0xF1EB, 0x8020, 0xF1EC, 0x8022, 0xF1ED, 0x8025, 0xF1EE, 0x8026,	0xF1EF, 0x8027, 0xF1F0, 0x8029, 0xF1F1, 0x8028, 0xF1F2, 0x8031,
+	0xF1F3, 0x800B, 0xF1F4, 0x8035, 0xF1F5, 0x8043, 0xF1F6, 0x8046,	0xF1F7, 0x804D, 0xF1F8, 0x8052, 0xF1F9, 0x8069, 0xF1FA, 0x8071,
+	0xF1FB, 0x8983, 0xF1FC, 0x9878, 0xF1FD, 0x9880, 0xF1FE, 0x9883,	0xF240, 0x99FA, 0xF241, 0x99FB, 0xF242, 0x99FC, 0xF243, 0x99FD,
+	0xF244, 0x99FE, 0xF245, 0x99FF, 0xF246, 0x9A00, 0xF247, 0x9A01,	0xF248, 0x9A02, 0xF249, 0x9A03, 0xF24A, 0x9A04, 0xF24B, 0x9A05,
+	0xF24C, 0x9A06, 0xF24D, 0x9A07, 0xF24E, 0x9A08, 0xF24F, 0x9A09,	0xF250, 0x9A0A, 0xF251, 0x9A0B, 0xF252, 0x9A0C, 0xF253, 0x9A0D,
+	0xF254, 0x9A0E, 0xF255, 0x9A0F, 0xF256, 0x9A10, 0xF257, 0x9A11,	0xF258, 0x9A12, 0xF259, 0x9A13, 0xF25A, 0x9A14, 0xF25B, 0x9A15,
+	0xF25C, 0x9A16, 0xF25D, 0x9A17, 0xF25E, 0x9A18, 0xF25F, 0x9A19,	0xF260, 0x9A1A, 0xF261, 0x9A1B, 0xF262, 0x9A1C, 0xF263, 0x9A1D,
+	0xF264, 0x9A1E, 0xF265, 0x9A1F, 0xF266, 0x9A20, 0xF267, 0x9A21,	0xF268, 0x9A22, 0xF269, 0x9A23, 0xF26A, 0x9A24, 0xF26B, 0x9A25,
+	0xF26C, 0x9A26, 0xF26D, 0x9A27, 0xF26E, 0x9A28, 0xF26F, 0x9A29,	0xF270, 0x9A2A, 0xF271, 0x9A2B, 0xF272, 0x9A2C, 0xF273, 0x9A2D,
+	0xF274, 0x9A2E, 0xF275, 0x9A2F, 0xF276, 0x9A30, 0xF277, 0x9A31,	0xF278, 0x9A32, 0xF279, 0x9A33, 0xF27A, 0x9A34, 0xF27B, 0x9A35,
+	0xF27C, 0x9A36, 0xF27D, 0x9A37, 0xF27E, 0x9A38, 0xF280, 0x9A39,	0xF281, 0x9A3A, 0xF282, 0x9A3B, 0xF283, 0x9A3C, 0xF284, 0x9A3D,
+	0xF285, 0x9A3E, 0xF286, 0x9A3F, 0xF287, 0x9A40, 0xF288, 0x9A41,	0xF289, 0x9A42, 0xF28A, 0x9A43, 0xF28B, 0x9A44, 0xF28C, 0x9A45,
+	0xF28D, 0x9A46, 0xF28E, 0x9A47, 0xF28F, 0x9A48, 0xF290, 0x9A49,	0xF291, 0x9A4A, 0xF292, 0x9A4B, 0xF293, 0x9A4C, 0xF294, 0x9A4D,
+	0xF295, 0x9A4E, 0xF296, 0x9A4F, 0xF297, 0x9A50, 0xF298, 0x9A51,	0xF299, 0x9A52, 0xF29A, 0x9A53, 0xF29B, 0x9A54, 0xF29C, 0x9A55,
+	0xF29D, 0x9A56, 0xF29E, 0x9A57, 0xF29F, 0x9A58, 0xF2A0, 0x9A59,	0xF2A1, 0x9889, 0xF2A2, 0x988C, 0xF2A3, 0x988D, 0xF2A4, 0x988F,
+	0xF2A5, 0x9894, 0xF2A6, 0x989A, 0xF2A7, 0x989B, 0xF2A8, 0x989E,	0xF2A9, 0x989F, 0xF2AA, 0x98A1, 0xF2AB, 0x98A2, 0xF2AC, 0x98A5,
+	0xF2AD, 0x98A6, 0xF2AE, 0x864D, 0xF2AF, 0x8654, 0xF2B0, 0x866C,	0xF2B1, 0x866E, 0xF2B2, 0x867F, 0xF2B3, 0x867A, 0xF2B4, 0x867C,
+	0xF2B5, 0x867B, 0xF2B6, 0x86A8, 0xF2B7, 0x868D, 0xF2B8, 0x868B,	0xF2B9, 0x86AC, 0xF2BA, 0x869D, 0xF2BB, 0x86A7, 0xF2BC, 0x86A3,
+	0xF2BD, 0x86AA, 0xF2BE, 0x8693, 0xF2BF, 0x86A9, 0xF2C0, 0x86B6,	0xF2C1, 0x86C4, 0xF2C2, 0x86B5, 0xF2C3, 0x86CE, 0xF2C4, 0x86B0,
+	0xF2C5, 0x86BA, 0xF2C6, 0x86B1, 0xF2C7, 0x86AF, 0xF2C8, 0x86C9,	0xF2C9, 0x86CF, 0xF2CA, 0x86B4, 0xF2CB, 0x86E9, 0xF2CC, 0x86F1,
+	0xF2CD, 0x86F2, 0xF2CE, 0x86ED, 0xF2CF, 0x86F3, 0xF2D0, 0x86D0,	0xF2D1, 0x8713, 0xF2D2, 0x86DE, 0xF2D3, 0x86F4, 0xF2D4, 0x86DF,
+	0xF2D5, 0x86D8, 0xF2D6, 0x86D1, 0xF2D7, 0x8703, 0xF2D8, 0x8707,	0xF2D9, 0x86F8, 0xF2DA, 0x8708, 0xF2DB, 0x870A, 0xF2DC, 0x870D,
+	0xF2DD, 0x8709, 0xF2DE, 0x8723, 0xF2DF, 0x873B, 0xF2E0, 0x871E,	0xF2E1, 0x8725, 0xF2E2, 0x872E, 0xF2E3, 0x871A, 0xF2E4, 0x873E,
+	0xF2E5, 0x8748, 0xF2E6, 0x8734, 0xF2E7, 0x8731, 0xF2E8, 0x8729,	0xF2E9, 0x8737, 0xF2EA, 0x873F, 0xF2EB, 0x8782, 0xF2EC, 0x8722,
+	0xF2ED, 0x877D, 0xF2EE, 0x877E, 0xF2EF, 0x877B, 0xF2F0, 0x8760,	0xF2F1, 0x8770, 0xF2F2, 0x874C, 0xF2F3, 0x876E, 0xF2F4, 0x878B,
+	0xF2F5, 0x8753, 0xF2F6, 0x8763, 0xF2F7, 0x877C, 0xF2F8, 0x8764,	0xF2F9, 0x8759, 0xF2FA, 0x8765, 0xF2FB, 0x8793, 0xF2FC, 0x87AF,
+	0xF2FD, 0x87A8, 0xF2FE, 0x87D2, 0xF340, 0x9A5A, 0xF341, 0x9A5B,	0xF342, 0x9A5C, 0xF343, 0x9A5D, 0xF344, 0x9A5E, 0xF345, 0x9A5F,
+	0xF346, 0x9A60, 0xF347, 0x9A61, 0xF348, 0x9A62, 0xF349, 0x9A63,	0xF34A, 0x9A64, 0xF34B, 0x9A65, 0xF34C, 0x9A66, 0xF34D, 0x9A67,
+	0xF34E, 0x9A68, 0xF34F, 0x9A69, 0xF350, 0x9A6A, 0xF351, 0x9A6B,	0xF352, 0x9A72, 0xF353, 0x9A83, 0xF354, 0x9A89, 0xF355, 0x9A8D,
+	0xF356, 0x9A8E, 0xF357, 0x9A94, 0xF358, 0x9A95, 0xF359, 0x9A99,	0xF35A, 0x9AA6, 0xF35B, 0x9AA9, 0xF35C, 0x9AAA, 0xF35D, 0x9AAB,
+	0xF35E, 0x9AAC, 0xF35F, 0x9AAD, 0xF360, 0x9AAE, 0xF361, 0x9AAF,	0xF362, 0x9AB2, 0xF363, 0x9AB3, 0xF364, 0x9AB4, 0xF365, 0x9AB5,
+	0xF366, 0x9AB9, 0xF367, 0x9ABB, 0xF368, 0x9ABD, 0xF369, 0x9ABE,	0xF36A, 0x9ABF, 0xF36B, 0x9AC3, 0xF36C, 0x9AC4, 0xF36D, 0x9AC6,
+	0xF36E, 0x9AC7, 0xF36F, 0x9AC8, 0xF370, 0x9AC9, 0xF371, 0x9ACA,	0xF372, 0x9ACD, 0xF373, 0x9ACE, 0xF374, 0x9ACF, 0xF375, 0x9AD0,
+	0xF376, 0x9AD2, 0xF377, 0x9AD4, 0xF378, 0x9AD5, 0xF379, 0x9AD6,	0xF37A, 0x9AD7, 0xF37B, 0x9AD9, 0xF37C, 0x9ADA, 0xF37D, 0x9ADB,
+	0xF37E, 0x9ADC, 0xF380, 0x9ADD, 0xF381, 0x9ADE, 0xF382, 0x9AE0,	0xF383, 0x9AE2, 0xF384, 0x9AE3, 0xF385, 0x9AE4, 0xF386, 0x9AE5,
+	0xF387, 0x9AE7, 0xF388, 0x9AE8, 0xF389, 0x9AE9, 0xF38A, 0x9AEA,	0xF38B, 0x9AEC, 0xF38C, 0x9AEE, 0xF38D, 0x9AF0, 0xF38E, 0x9AF1,
+	0xF38F, 0x9AF2, 0xF390, 0x9AF3, 0xF391, 0x9AF4, 0xF392, 0x9AF5,	0xF393, 0x9AF6, 0xF394, 0x9AF7, 0xF395, 0x9AF8, 0xF396, 0x9AFA,
+	0xF397, 0x9AFC, 0xF398, 0x9AFD, 0xF399, 0x9AFE, 0xF39A, 0x9AFF,	0xF39B, 0x9B00, 0xF39C, 0x9B01, 0xF39D, 0x9B02, 0xF39E, 0x9B04,
+	0xF39F, 0x9B05, 0xF3A0, 0x9B06, 0xF3A1, 0x87C6, 0xF3A2, 0x8788,	0xF3A3, 0x8785, 0xF3A4, 0x87AD, 0xF3A5, 0x8797, 0xF3A6, 0x8783,
+	0xF3A7, 0x87AB, 0xF3A8, 0x87E5, 0xF3A9, 0x87AC, 0xF3AA, 0x87B5,	0xF3AB, 0x87B3, 0xF3AC, 0x87CB, 0xF3AD, 0x87D3, 0xF3AE, 0x87BD,
+	0xF3AF, 0x87D1, 0xF3B0, 0x87C0, 0xF3B1, 0x87CA, 0xF3B2, 0x87DB,	0xF3B3, 0x87EA, 0xF3B4, 0x87E0, 0xF3B5, 0x87EE, 0xF3B6, 0x8816,
+	0xF3B7, 0x8813, 0xF3B8, 0x87FE, 0xF3B9, 0x880A, 0xF3BA, 0x881B,	0xF3BB, 0x8821, 0xF3BC, 0x8839, 0xF3BD, 0x883C, 0xF3BE, 0x7F36,
+	0xF3BF, 0x7F42, 0xF3C0, 0x7F44, 0xF3C1, 0x7F45, 0xF3C2, 0x8210,	0xF3C3, 0x7AFA, 0xF3C4, 0x7AFD, 0xF3C5, 0x7B08, 0xF3C6, 0x7B03,
+	0xF3C7, 0x7B04, 0xF3C8, 0x7B15, 0xF3C9, 0x7B0A, 0xF3CA, 0x7B2B,	0xF3CB, 0x7B0F, 0xF3CC, 0x7B47, 0xF3CD, 0x7B38, 0xF3CE, 0x7B2A,
+	0xF3CF, 0x7B19, 0xF3D0, 0x7B2E, 0xF3D1, 0x7B31, 0xF3D2, 0x7B20,	0xF3D3, 0x7B25, 0xF3D4, 0x7B24, 0xF3D5, 0x7B33, 0xF3D6, 0x7B3E,
+	0xF3D7, 0x7B1E, 0xF3D8, 0x7B58, 0xF3D9, 0x7B5A, 0xF3DA, 0x7B45,	0xF3DB, 0x7B75, 0xF3DC, 0x7B4C, 0xF3DD, 0x7B5D, 0xF3DE, 0x7B60,
+	0xF3DF, 0x7B6E, 0xF3E0, 0x7B7B, 0xF3E1, 0x7B62, 0xF3E2, 0x7B72,	0xF3E3, 0x7B71, 0xF3E4, 0x7B90, 0xF3E5, 0x7BA6, 0xF3E6, 0x7BA7,
+	0xF3E7, 0x7BB8, 0xF3E8, 0x7BAC, 0xF3E9, 0x7B9D, 0xF3EA, 0x7BA8,	0xF3EB, 0x7B85, 0xF3EC, 0x7BAA, 0xF3ED, 0x7B9C, 0xF3EE, 0x7BA2,
+	0xF3EF, 0x7BAB, 0xF3F0, 0x7BB4, 0xF3F1, 0x7BD1, 0xF3F2, 0x7BC1,	0xF3F3, 0x7BCC, 0xF3F4, 0x7BDD, 0xF3F5, 0x7BDA, 0xF3F6, 0x7BE5,
+	0xF3F7, 0x7BE6, 0xF3F8, 0x7BEA, 0xF3F9, 0x7C0C, 0xF3FA, 0x7BFE,	0xF3FB, 0x7BFC, 0xF3FC, 0x7C0F, 0xF3FD, 0x7C16, 0xF3FE, 0x7C0B,
+	0xF440, 0x9B07, 0xF441, 0x9B09, 0xF442, 0x9B0A, 0xF443, 0x9B0B,	0xF444, 0x9B0C, 0xF445, 0x9B0D, 0xF446, 0x9B0E, 0xF447, 0x9B10,
+	0xF448, 0x9B11, 0xF449, 0x9B12, 0xF44A, 0x9B14, 0xF44B, 0x9B15,	0xF44C, 0x9B16, 0xF44D, 0x9B17, 0xF44E, 0x9B18, 0xF44F, 0x9B19,
+	0xF450, 0x9B1A, 0xF451, 0x9B1B, 0xF452, 0x9B1C, 0xF453, 0x9B1D,	0xF454, 0x9B1E, 0xF455, 0x9B20, 0xF456, 0x9B21, 0xF457, 0x9B22,
+	0xF458, 0x9B24, 0xF459, 0x9B25, 0xF45A, 0x9B26, 0xF45B, 0x9B27,	0xF45C, 0x9B28, 0xF45D, 0x9B29, 0xF45E, 0x9B2A, 0xF45F, 0x9B2B,
+	0xF460, 0x9B2C, 0xF461, 0x9B2D, 0xF462, 0x9B2E, 0xF463, 0x9B30,	0xF464, 0x9B31, 0xF465, 0x9B33, 0xF466, 0x9B34, 0xF467, 0x9B35,
+	0xF468, 0x9B36, 0xF469, 0x9B37, 0xF46A, 0x9B38, 0xF46B, 0x9B39,	0xF46C, 0x9B3A, 0xF46D, 0x9B3D, 0xF46E, 0x9B3E, 0xF46F, 0x9B3F,
+	0xF470, 0x9B40, 0xF471, 0x9B46, 0xF472, 0x9B4A, 0xF473, 0x9B4B,	0xF474, 0x9B4C, 0xF475, 0x9B4E, 0xF476, 0x9B50, 0xF477, 0x9B52,
+	0xF478, 0x9B53, 0xF479, 0x9B55, 0xF47A, 0x9B56, 0xF47B, 0x9B57,	0xF47C, 0x9B58, 0xF47D, 0x9B59, 0xF47E, 0x9B5A, 0xF480, 0x9B5B,
+	0xF481, 0x9B5C, 0xF482, 0x9B5D, 0xF483, 0x9B5E, 0xF484, 0x9B5F,	0xF485, 0x9B60, 0xF486, 0x9B61, 0xF487, 0x9B62, 0xF488, 0x9B63,
+	0xF489, 0x9B64, 0xF48A, 0x9B65, 0xF48B, 0x9B66, 0xF48C, 0x9B67,	0xF48D, 0x9B68, 0xF48E, 0x9B69, 0xF48F, 0x9B6A, 0xF490, 0x9B6B,
+	0xF491, 0x9B6C, 0xF492, 0x9B6D, 0xF493, 0x9B6E, 0xF494, 0x9B6F,	0xF495, 0x9B70, 0xF496, 0x9B71, 0xF497, 0x9B72, 0xF498, 0x9B73,
+	0xF499, 0x9B74, 0xF49A, 0x9B75, 0xF49B, 0x9B76, 0xF49C, 0x9B77,	0xF49D, 0x9B78, 0xF49E, 0x9B79, 0xF49F, 0x9B7A, 0xF4A0, 0x9B7B,
+	0xF4A1, 0x7C1F, 0xF4A2, 0x7C2A, 0xF4A3, 0x7C26, 0xF4A4, 0x7C38,	0xF4A5, 0x7C41, 0xF4A6, 0x7C40, 0xF4A7, 0x81FE, 0xF4A8, 0x8201,
+	0xF4A9, 0x8202, 0xF4AA, 0x8204, 0xF4AB, 0x81EC, 0xF4AC, 0x8844,	0xF4AD, 0x8221, 0xF4AE, 0x8222, 0xF4AF, 0x8223, 0xF4B0, 0x822D,
+	0xF4B1, 0x822F, 0xF4B2, 0x8228, 0xF4B3, 0x822B, 0xF4B4, 0x8238,	0xF4B5, 0x823B, 0xF4B6, 0x8233, 0xF4B7, 0x8234, 0xF4B8, 0x823E,
+	0xF4B9, 0x8244, 0xF4BA, 0x8249, 0xF4BB, 0x824B, 0xF4BC, 0x824F,	0xF4BD, 0x825A, 0xF4BE, 0x825F, 0xF4BF, 0x8268, 0xF4C0, 0x887E,
+	0xF4C1, 0x8885, 0xF4C2, 0x8888, 0xF4C3, 0x88D8, 0xF4C4, 0x88DF,	0xF4C5, 0x895E, 0xF4C6, 0x7F9D, 0xF4C7, 0x7F9F, 0xF4C8, 0x7FA7,
+	0xF4C9, 0x7FAF, 0xF4CA, 0x7FB0, 0xF4CB, 0x7FB2, 0xF4CC, 0x7C7C,	0xF4CD, 0x6549, 0xF4CE, 0x7C91, 0xF4CF, 0x7C9D, 0xF4D0, 0x7C9C,
+	0xF4D1, 0x7C9E, 0xF4D2, 0x7CA2, 0xF4D3, 0x7CB2, 0xF4D4, 0x7CBC,	0xF4D5, 0x7CBD, 0xF4D6, 0x7CC1, 0xF4D7, 0x7CC7, 0xF4D8, 0x7CCC,
+	0xF4D9, 0x7CCD, 0xF4DA, 0x7CC8, 0xF4DB, 0x7CC5, 0xF4DC, 0x7CD7,	0xF4DD, 0x7CE8, 0xF4DE, 0x826E, 0xF4DF, 0x66A8, 0xF4E0, 0x7FBF,
+	0xF4E1, 0x7FCE, 0xF4E2, 0x7FD5, 0xF4E3, 0x7FE5, 0xF4E4, 0x7FE1,	0xF4E5, 0x7FE6, 0xF4E6, 0x7FE9, 0xF4E7, 0x7FEE, 0xF4E8, 0x7FF3,
+	0xF4E9, 0x7CF8, 0xF4EA, 0x7D77, 0xF4EB, 0x7DA6, 0xF4EC, 0x7DAE,	0xF4ED, 0x7E47, 0xF4EE, 0x7E9B, 0xF4EF, 0x9EB8, 0xF4F0, 0x9EB4,
+	0xF4F1, 0x8D73, 0xF4F2, 0x8D84, 0xF4F3, 0x8D94, 0xF4F4, 0x8D91,	0xF4F5, 0x8DB1, 0xF4F6, 0x8D67, 0xF4F7, 0x8D6D, 0xF4F8, 0x8C47,
+	0xF4F9, 0x8C49, 0xF4FA, 0x914A, 0xF4FB, 0x9150, 0xF4FC, 0x914E,	0xF4FD, 0x914F, 0xF4FE, 0x9164, 0xF540, 0x9B7C, 0xF541, 0x9B7D,
+	0xF542, 0x9B7E, 0xF543, 0x9B7F, 0xF544, 0x9B80, 0xF545, 0x9B81,	0xF546, 0x9B82, 0xF547, 0x9B83, 0xF548, 0x9B84, 0xF549, 0x9B85,
+	0xF54A, 0x9B86, 0xF54B, 0x9B87, 0xF54C, 0x9B88, 0xF54D, 0x9B89,	0xF54E, 0x9B8A, 0xF54F, 0x9B8B, 0xF550, 0x9B8C, 0xF551, 0x9B8D,
+	0xF552, 0x9B8E, 0xF553, 0x9B8F, 0xF554, 0x9B90, 0xF555, 0x9B91,	0xF556, 0x9B92, 0xF557, 0x9B93, 0xF558, 0x9B94, 0xF559, 0x9B95,
+	0xF55A, 0x9B96, 0xF55B, 0x9B97, 0xF55C, 0x9B98, 0xF55D, 0x9B99,	0xF55E, 0x9B9A, 0xF55F, 0x9B9B, 0xF560, 0x9B9C, 0xF561, 0x9B9D,
+	0xF562, 0x9B9E, 0xF563, 0x9B9F, 0xF564, 0x9BA0, 0xF565, 0x9BA1,	0xF566, 0x9BA2, 0xF567, 0x9BA3, 0xF568, 0x9BA4, 0xF569, 0x9BA5,
+	0xF56A, 0x9BA6, 0xF56B, 0x9BA7, 0xF56C, 0x9BA8, 0xF56D, 0x9BA9,	0xF56E, 0x9BAA, 0xF56F, 0x9BAB, 0xF570, 0x9BAC, 0xF571, 0x9BAD,
+	0xF572, 0x9BAE, 0xF573, 0x9BAF, 0xF574, 0x9BB0, 0xF575, 0x9BB1,	0xF576, 0x9BB2, 0xF577, 0x9BB3, 0xF578, 0x9BB4, 0xF579, 0x9BB5,
+	0xF57A, 0x9BB6, 0xF57B, 0x9BB7, 0xF57C, 0x9BB8, 0xF57D, 0x9BB9,	0xF57E, 0x9BBA, 0xF580, 0x9BBB, 0xF581, 0x9BBC, 0xF582, 0x9BBD,
+	0xF583, 0x9BBE, 0xF584, 0x9BBF, 0xF585, 0x9BC0, 0xF586, 0x9BC1,	0xF587, 0x9BC2, 0xF588, 0x9BC3, 0xF589, 0x9BC4, 0xF58A, 0x9BC5,
+	0xF58B, 0x9BC6, 0xF58C, 0x9BC7, 0xF58D, 0x9BC8, 0xF58E, 0x9BC9,	0xF58F, 0x9BCA, 0xF590, 0x9BCB, 0xF591, 0x9BCC, 0xF592, 0x9BCD,
+	0xF593, 0x9BCE, 0xF594, 0x9BCF, 0xF595, 0x9BD0, 0xF596, 0x9BD1,	0xF597, 0x9BD2, 0xF598, 0x9BD3, 0xF599, 0x9BD4, 0xF59A, 0x9BD5,
+	0xF59B, 0x9BD6, 0xF59C, 0x9BD7, 0xF59D, 0x9BD8, 0xF59E, 0x9BD9,	0xF59F, 0x9BDA, 0xF5A0, 0x9BDB, 0xF5A1, 0x9162, 0xF5A2, 0x9161,
+	0xF5A3, 0x9170, 0xF5A4, 0x9169, 0xF5A5, 0x916F, 0xF5A6, 0x917D,	0xF5A7, 0x917E, 0xF5A8, 0x9172, 0xF5A9, 0x9174, 0xF5AA, 0x9179,
+	0xF5AB, 0x918C, 0xF5AC, 0x9185, 0xF5AD, 0x9190, 0xF5AE, 0x918D,	0xF5AF, 0x9191, 0xF5B0, 0x91A2, 0xF5B1, 0x91A3, 0xF5B2, 0x91AA,
+	0xF5B3, 0x91AD, 0xF5B4, 0x91AE, 0xF5B5, 0x91AF, 0xF5B6, 0x91B5,	0xF5B7, 0x91B4, 0xF5B8, 0x91BA, 0xF5B9, 0x8C55, 0xF5BA, 0x9E7E,
+	0xF5BB, 0x8DB8, 0xF5BC, 0x8DEB, 0xF5BD, 0x8E05, 0xF5BE, 0x8E59,	0xF5BF, 0x8E69, 0xF5C0, 0x8DB5, 0xF5C1, 0x8DBF, 0xF5C2, 0x8DBC,
+	0xF5C3, 0x8DBA, 0xF5C4, 0x8DC4, 0xF5C5, 0x8DD6, 0xF5C6, 0x8DD7,	0xF5C7, 0x8DDA, 0xF5C8, 0x8DDE, 0xF5C9, 0x8DCE, 0xF5CA, 0x8DCF,
+	0xF5CB, 0x8DDB, 0xF5CC, 0x8DC6, 0xF5CD, 0x8DEC, 0xF5CE, 0x8DF7,	0xF5CF, 0x8DF8, 0xF5D0, 0x8DE3, 0xF5D1, 0x8DF9, 0xF5D2, 0x8DFB,
+	0xF5D3, 0x8DE4, 0xF5D4, 0x8E09, 0xF5D5, 0x8DFD, 0xF5D6, 0x8E14,	0xF5D7, 0x8E1D, 0xF5D8, 0x8E1F, 0xF5D9, 0x8E2C, 0xF5DA, 0x8E2E,
+	0xF5DB, 0x8E23, 0xF5DC, 0x8E2F, 0xF5DD, 0x8E3A, 0xF5DE, 0x8E40,	0xF5DF, 0x8E39, 0xF5E0, 0x8E35, 0xF5E1, 0x8E3D, 0xF5E2, 0x8E31,
+	0xF5E3, 0x8E49, 0xF5E4, 0x8E41, 0xF5E5, 0x8E42, 0xF5E6, 0x8E51,	0xF5E7, 0x8E52, 0xF5E8, 0x8E4A, 0xF5E9, 0x8E70, 0xF5EA, 0x8E76,
+	0xF5EB, 0x8E7C, 0xF5EC, 0x8E6F, 0xF5ED, 0x8E74, 0xF5EE, 0x8E85,	0xF5EF, 0x8E8F, 0xF5F0, 0x8E94, 0xF5F1, 0x8E90, 0xF5F2, 0x8E9C,
+	0xF5F3, 0x8E9E, 0xF5F4, 0x8C78, 0xF5F5, 0x8C82, 0xF5F6, 0x8C8A,	0xF5F7, 0x8C85, 0xF5F8, 0x8C98, 0xF5F9, 0x8C94, 0xF5FA, 0x659B,
+	0xF5FB, 0x89D6, 0xF5FC, 0x89DE, 0xF5FD, 0x89DA, 0xF5FE, 0x89DC,	0xF640, 0x9BDC, 0xF641, 0x9BDD, 0xF642, 0x9BDE, 0xF643, 0x9BDF,
+	0xF644, 0x9BE0, 0xF645, 0x9BE1, 0xF646, 0x9BE2, 0xF647, 0x9BE3,	0xF648, 0x9BE4, 0xF649, 0x9BE5, 0xF64A, 0x9BE6, 0xF64B, 0x9BE7,
+	0xF64C, 0x9BE8, 0xF64D, 0x9BE9, 0xF64E, 0x9BEA, 0xF64F, 0x9BEB,	0xF650, 0x9BEC, 0xF651, 0x9BED, 0xF652, 0x9BEE, 0xF653, 0x9BEF,
+	0xF654, 0x9BF0, 0xF655, 0x9BF1, 0xF656, 0x9BF2, 0xF657, 0x9BF3,	0xF658, 0x9BF4, 0xF659, 0x9BF5, 0xF65A, 0x9BF6, 0xF65B, 0x9BF7,
+	0xF65C, 0x9BF8, 0xF65D, 0x9BF9, 0xF65E, 0x9BFA, 0xF65F, 0x9BFB,	0xF660, 0x9BFC, 0xF661, 0x9BFD, 0xF662, 0x9BFE, 0xF663, 0x9BFF,
+	0xF664, 0x9C00, 0xF665, 0x9C01, 0xF666, 0x9C02, 0xF667, 0x9C03,	0xF668, 0x9C04, 0xF669, 0x9C05, 0xF66A, 0x9C06, 0xF66B, 0x9C07,
+	0xF66C, 0x9C08, 0xF66D, 0x9C09, 0xF66E, 0x9C0A, 0xF66F, 0x9C0B,	0xF670, 0x9C0C, 0xF671, 0x9C0D, 0xF672, 0x9C0E, 0xF673, 0x9C0F,
+	0xF674, 0x9C10, 0xF675, 0x9C11, 0xF676, 0x9C12, 0xF677, 0x9C13,	0xF678, 0x9C14, 0xF679, 0x9C15, 0xF67A, 0x9C16, 0xF67B, 0x9C17,
+	0xF67C, 0x9C18, 0xF67D, 0x9C19, 0xF67E, 0x9C1A, 0xF680, 0x9C1B,	0xF681, 0x9C1C, 0xF682, 0x9C1D, 0xF683, 0x9C1E, 0xF684, 0x9C1F,
+	0xF685, 0x9C20, 0xF686, 0x9C21, 0xF687, 0x9C22, 0xF688, 0x9C23,	0xF689, 0x9C24, 0xF68A, 0x9C25, 0xF68B, 0x9C26, 0xF68C, 0x9C27,
+	0xF68D, 0x9C28, 0xF68E, 0x9C29, 0xF68F, 0x9C2A, 0xF690, 0x9C2B,	0xF691, 0x9C2C, 0xF692, 0x9C2D, 0xF693, 0x9C2E, 0xF694, 0x9C2F,
+	0xF695, 0x9C30, 0xF696, 0x9C31, 0xF697, 0x9C32, 0xF698, 0x9C33,	0xF699, 0x9C34, 0xF69A, 0x9C35, 0xF69B, 0x9C36, 0xF69C, 0x9C37,
+	0xF69D, 0x9C38, 0xF69E, 0x9C39, 0xF69F, 0x9C3A, 0xF6A0, 0x9C3B,	0xF6A1, 0x89E5, 0xF6A2, 0x89EB, 0xF6A3, 0x89EF, 0xF6A4, 0x8A3E,
+	0xF6A5, 0x8B26, 0xF6A6, 0x9753, 0xF6A7, 0x96E9, 0xF6A8, 0x96F3,	0xF6A9, 0x96EF, 0xF6AA, 0x9706, 0xF6AB, 0x9701, 0xF6AC, 0x9708,
+	0xF6AD, 0x970F, 0xF6AE, 0x970E, 0xF6AF, 0x972A, 0xF6B0, 0x972D,	0xF6B1, 0x9730, 0xF6B2, 0x973E, 0xF6B3, 0x9F80, 0xF6B4, 0x9F83,
+	0xF6B5, 0x9F85, 0xF6B6, 0x9F86, 0xF6B7, 0x9F87, 0xF6B8, 0x9F88,	0xF6B9, 0x9F89, 0xF6BA, 0x9F8A, 0xF6BB, 0x9F8C, 0xF6BC, 0x9EFE,
+	0xF6BD, 0x9F0B, 0xF6BE, 0x9F0D, 0xF6BF, 0x96B9, 0xF6C0, 0x96BC,	0xF6C1, 0x96BD, 0xF6C2, 0x96CE, 0xF6C3, 0x96D2, 0xF6C4, 0x77BF,
+	0xF6C5, 0x96E0, 0xF6C6, 0x928E, 0xF6C7, 0x92AE, 0xF6C8, 0x92C8,	0xF6C9, 0x933E, 0xF6CA, 0x936A, 0xF6CB, 0x93CA, 0xF6CC, 0x938F,
+	0xF6CD, 0x943E, 0xF6CE, 0x946B, 0xF6CF, 0x9C7F, 0xF6D0, 0x9C82,	0xF6D1, 0x9C85, 0xF6D2, 0x9C86, 0xF6D3, 0x9C87, 0xF6D4, 0x9C88,
+	0xF6D5, 0x7A23, 0xF6D6, 0x9C8B, 0xF6D7, 0x9C8E, 0xF6D8, 0x9C90,	0xF6D9, 0x9C91, 0xF6DA, 0x9C92, 0xF6DB, 0x9C94, 0xF6DC, 0x9C95,
+	0xF6DD, 0x9C9A, 0xF6DE, 0x9C9B, 0xF6DF, 0x9C9E, 0xF6E0, 0x9C9F,	0xF6E1, 0x9CA0, 0xF6E2, 0x9CA1, 0xF6E3, 0x9CA2, 0xF6E4, 0x9CA3,
+	0xF6E5, 0x9CA5, 0xF6E6, 0x9CA6, 0xF6E7, 0x9CA7, 0xF6E8, 0x9CA8,	0xF6E9, 0x9CA9, 0xF6EA, 0x9CAB, 0xF6EB, 0x9CAD, 0xF6EC, 0x9CAE,
+	0xF6ED, 0x9CB0, 0xF6EE, 0x9CB1, 0xF6EF, 0x9CB2, 0xF6F0, 0x9CB3,	0xF6F1, 0x9CB4, 0xF6F2, 0x9CB5, 0xF6F3, 0x9CB6, 0xF6F4, 0x9CB7,
+	0xF6F5, 0x9CBA, 0xF6F6, 0x9CBB, 0xF6F7, 0x9CBC, 0xF6F8, 0x9CBD,	0xF6F9, 0x9CC4, 0xF6FA, 0x9CC5, 0xF6FB, 0x9CC6, 0xF6FC, 0x9CC7,
+	0xF6FD, 0x9CCA, 0xF6FE, 0x9CCB, 0xF740, 0x9C3C, 0xF741, 0x9C3D,	0xF742, 0x9C3E, 0xF743, 0x9C3F, 0xF744, 0x9C40, 0xF745, 0x9C41,
+	0xF746, 0x9C42, 0xF747, 0x9C43, 0xF748, 0x9C44, 0xF749, 0x9C45,	0xF74A, 0x9C46, 0xF74B, 0x9C47, 0xF74C, 0x9C48, 0xF74D, 0x9C49,
+	0xF74E, 0x9C4A, 0xF74F, 0x9C4B, 0xF750, 0x9C4C, 0xF751, 0x9C4D,	0xF752, 0x9C4E, 0xF753, 0x9C4F, 0xF754, 0x9C50, 0xF755, 0x9C51,
+	0xF756, 0x9C52, 0xF757, 0x9C53, 0xF758, 0x9C54, 0xF759, 0x9C55,	0xF75A, 0x9C56, 0xF75B, 0x9C57, 0xF75C, 0x9C58, 0xF75D, 0x9C59,
+	0xF75E, 0x9C5A, 0xF75F, 0x9C5B, 0xF760, 0x9C5C, 0xF761, 0x9C5D,	0xF762, 0x9C5E, 0xF763, 0x9C5F, 0xF764, 0x9C60, 0xF765, 0x9C61,
+	0xF766, 0x9C62, 0xF767, 0x9C63, 0xF768, 0x9C64, 0xF769, 0x9C65,	0xF76A, 0x9C66, 0xF76B, 0x9C67, 0xF76C, 0x9C68, 0xF76D, 0x9C69,
+	0xF76E, 0x9C6A, 0xF76F, 0x9C6B, 0xF770, 0x9C6C, 0xF771, 0x9C6D,	0xF772, 0x9C6E, 0xF773, 0x9C6F, 0xF774, 0x9C70, 0xF775, 0x9C71,
+	0xF776, 0x9C72, 0xF777, 0x9C73, 0xF778, 0x9C74, 0xF779, 0x9C75,	0xF77A, 0x9C76, 0xF77B, 0x9C77, 0xF77C, 0x9C78, 0xF77D, 0x9C79,
+	0xF77E, 0x9C7A, 0xF780, 0x9C7B, 0xF781, 0x9C7D, 0xF782, 0x9C7E,	0xF783, 0x9C80, 0xF784, 0x9C83, 0xF785, 0x9C84, 0xF786, 0x9C89,
+	0xF787, 0x9C8A, 0xF788, 0x9C8C, 0xF789, 0x9C8F, 0xF78A, 0x9C93,	0xF78B, 0x9C96, 0xF78C, 0x9C97, 0xF78D, 0x9C98, 0xF78E, 0x9C99,
+	0xF78F, 0x9C9D, 0xF790, 0x9CAA, 0xF791, 0x9CAC, 0xF792, 0x9CAF,	0xF793, 0x9CB9, 0xF794, 0x9CBE, 0xF795, 0x9CBF, 0xF796, 0x9CC0,
+	0xF797, 0x9CC1, 0xF798, 0x9CC2, 0xF799, 0x9CC8, 0xF79A, 0x9CC9,	0xF79B, 0x9CD1, 0xF79C, 0x9CD2, 0xF79D, 0x9CDA, 0xF79E, 0x9CDB,
+	0xF79F, 0x9CE0, 0xF7A0, 0x9CE1, 0xF7A1, 0x9CCC, 0xF7A2, 0x9CCD,	0xF7A3, 0x9CCE, 0xF7A4, 0x9CCF, 0xF7A5, 0x9CD0, 0xF7A6, 0x9CD3,
+	0xF7A7, 0x9CD4, 0xF7A8, 0x9CD5, 0xF7A9, 0x9CD7, 0xF7AA, 0x9CD8,	0xF7AB, 0x9CD9, 0xF7AC, 0x9CDC, 0xF7AD, 0x9CDD, 0xF7AE, 0x9CDF,
+	0xF7AF, 0x9CE2, 0xF7B0, 0x977C, 0xF7B1, 0x9785, 0xF7B2, 0x9791,	0xF7B3, 0x9792, 0xF7B4, 0x9794, 0xF7B5, 0x97AF, 0xF7B6, 0x97AB,
+	0xF7B7, 0x97A3, 0xF7B8, 0x97B2, 0xF7B9, 0x97B4, 0xF7BA, 0x9AB1,	0xF7BB, 0x9AB0, 0xF7BC, 0x9AB7, 0xF7BD, 0x9E58, 0xF7BE, 0x9AB6,
+	0xF7BF, 0x9ABA, 0xF7C0, 0x9ABC, 0xF7C1, 0x9AC1, 0xF7C2, 0x9AC0,	0xF7C3, 0x9AC5, 0xF7C4, 0x9AC2, 0xF7C5, 0x9ACB, 0xF7C6, 0x9ACC,
+	0xF7C7, 0x9AD1, 0xF7C8, 0x9B45, 0xF7C9, 0x9B43, 0xF7CA, 0x9B47,	0xF7CB, 0x9B49, 0xF7CC, 0x9B48, 0xF7CD, 0x9B4D, 0xF7CE, 0x9B51,
+	0xF7CF, 0x98E8, 0xF7D0, 0x990D, 0xF7D1, 0x992E, 0xF7D2, 0x9955,	0xF7D3, 0x9954, 0xF7D4, 0x9ADF, 0xF7D5, 0x9AE1, 0xF7D6, 0x9AE6,
+	0xF7D7, 0x9AEF, 0xF7D8, 0x9AEB, 0xF7D9, 0x9AFB, 0xF7DA, 0x9AED,	0xF7DB, 0x9AF9, 0xF7DC, 0x9B08, 0xF7DD, 0x9B0F, 0xF7DE, 0x9B13,
+	0xF7DF, 0x9B1F, 0xF7E0, 0x9B23, 0xF7E1, 0x9EBD, 0xF7E2, 0x9EBE,	0xF7E3, 0x7E3B, 0xF7E4, 0x9E82, 0xF7E5, 0x9E87, 0xF7E6, 0x9E88,
+	0xF7E7, 0x9E8B, 0xF7E8, 0x9E92, 0xF7E9, 0x93D6, 0xF7EA, 0x9E9D,	0xF7EB, 0x9E9F, 0xF7EC, 0x9EDB, 0xF7ED, 0x9EDC, 0xF7EE, 0x9EDD,
+	0xF7EF, 0x9EE0, 0xF7F0, 0x9EDF, 0xF7F1, 0x9EE2, 0xF7F2, 0x9EE9,	0xF7F3, 0x9EE7, 0xF7F4, 0x9EE5, 0xF7F5, 0x9EEA, 0xF7F6, 0x9EEF,
+	0xF7F7, 0x9F22, 0xF7F8, 0x9F2C, 0xF7F9, 0x9F2F, 0xF7FA, 0x9F39,	0xF7FB, 0x9F37, 0xF7FC, 0x9F3D, 0xF7FD, 0x9F3E, 0xF7FE, 0x9F44,
+	0xF840, 0x9CE3, 0xF841, 0x9CE4, 0xF842, 0x9CE5, 0xF843, 0x9CE6,	0xF844, 0x9CE7, 0xF845, 0x9CE8, 0xF846, 0x9CE9, 0xF847, 0x9CEA,
+	0xF848, 0x9CEB, 0xF849, 0x9CEC, 0xF84A, 0x9CED, 0xF84B, 0x9CEE,	0xF84C, 0x9CEF, 0xF84D, 0x9CF0, 0xF84E, 0x9CF1, 0xF84F, 0x9CF2,
+	0xF850, 0x9CF3, 0xF851, 0x9CF4, 0xF852, 0x9CF5, 0xF853, 0x9CF6,	0xF854, 0x9CF7, 0xF855, 0x9CF8, 0xF856, 0x9CF9, 0xF857, 0x9CFA,
+	0xF858, 0x9CFB, 0xF859, 0x9CFC, 0xF85A, 0x9CFD, 0xF85B, 0x9CFE,	0xF85C, 0x9CFF, 0xF85D, 0x9D00, 0xF85E, 0x9D01, 0xF85F, 0x9D02,
+	0xF860, 0x9D03, 0xF861, 0x9D04, 0xF862, 0x9D05, 0xF863, 0x9D06,	0xF864, 0x9D07, 0xF865, 0x9D08, 0xF866, 0x9D09, 0xF867, 0x9D0A,
+	0xF868, 0x9D0B, 0xF869, 0x9D0C, 0xF86A, 0x9D0D, 0xF86B, 0x9D0E,	0xF86C, 0x9D0F, 0xF86D, 0x9D10, 0xF86E, 0x9D11, 0xF86F, 0x9D12,
+	0xF870, 0x9D13, 0xF871, 0x9D14, 0xF872, 0x9D15, 0xF873, 0x9D16,	0xF874, 0x9D17, 0xF875, 0x9D18, 0xF876, 0x9D19, 0xF877, 0x9D1A,
+	0xF878, 0x9D1B, 0xF879, 0x9D1C, 0xF87A, 0x9D1D, 0xF87B, 0x9D1E,	0xF87C, 0x9D1F, 0xF87D, 0x9D20, 0xF87E, 0x9D21, 0xF880, 0x9D22,
+	0xF881, 0x9D23, 0xF882, 0x9D24, 0xF883, 0x9D25, 0xF884, 0x9D26,	0xF885, 0x9D27, 0xF886, 0x9D28, 0xF887, 0x9D29, 0xF888, 0x9D2A,
+	0xF889, 0x9D2B, 0xF88A, 0x9D2C, 0xF88B, 0x9D2D, 0xF88C, 0x9D2E,	0xF88D, 0x9D2F, 0xF88E, 0x9D30, 0xF88F, 0x9D31, 0xF890, 0x9D32,
+	0xF891, 0x9D33, 0xF892, 0x9D34, 0xF893, 0x9D35, 0xF894, 0x9D36,	0xF895, 0x9D37, 0xF896, 0x9D38, 0xF897, 0x9D39, 0xF898, 0x9D3A,
+	0xF899, 0x9D3B, 0xF89A, 0x9D3C, 0xF89B, 0x9D3D, 0xF89C, 0x9D3E,	0xF89D, 0x9D3F, 0xF89E, 0x9D40, 0xF89F, 0x9D41, 0xF8A0, 0x9D42,
+	0xF940, 0x9D43, 0xF941, 0x9D44, 0xF942, 0x9D45, 0xF943, 0x9D46,	0xF944, 0x9D47, 0xF945, 0x9D48, 0xF946, 0x9D49, 0xF947, 0x9D4A,
+	0xF948, 0x9D4B, 0xF949, 0x9D4C, 0xF94A, 0x9D4D, 0xF94B, 0x9D4E,	0xF94C, 0x9D4F, 0xF94D, 0x9D50, 0xF94E, 0x9D51, 0xF94F, 0x9D52,
+	0xF950, 0x9D53, 0xF951, 0x9D54, 0xF952, 0x9D55, 0xF953, 0x9D56,	0xF954, 0x9D57, 0xF955, 0x9D58, 0xF956, 0x9D59, 0xF957, 0x9D5A,
+	0xF958, 0x9D5B, 0xF959, 0x9D5C, 0xF95A, 0x9D5D, 0xF95B, 0x9D5E,	0xF95C, 0x9D5F, 0xF95D, 0x9D60, 0xF95E, 0x9D61, 0xF95F, 0x9D62,
+	0xF960, 0x9D63, 0xF961, 0x9D64, 0xF962, 0x9D65, 0xF963, 0x9D66,	0xF964, 0x9D67, 0xF965, 0x9D68, 0xF966, 0x9D69, 0xF967, 0x9D6A,
+	0xF968, 0x9D6B, 0xF969, 0x9D6C, 0xF96A, 0x9D6D, 0xF96B, 0x9D6E,	0xF96C, 0x9D6F, 0xF96D, 0x9D70, 0xF96E, 0x9D71, 0xF96F, 0x9D72,
+	0xF970, 0x9D73, 0xF971, 0x9D74, 0xF972, 0x9D75, 0xF973, 0x9D76,	0xF974, 0x9D77, 0xF975, 0x9D78, 0xF976, 0x9D79, 0xF977, 0x9D7A,
+	0xF978, 0x9D7B, 0xF979, 0x9D7C, 0xF97A, 0x9D7D, 0xF97B, 0x9D7E,	0xF97C, 0x9D7F, 0xF97D, 0x9D80, 0xF97E, 0x9D81, 0xF980, 0x9D82,
+	0xF981, 0x9D83, 0xF982, 0x9D84, 0xF983, 0x9D85, 0xF984, 0x9D86,	0xF985, 0x9D87, 0xF986, 0x9D88, 0xF987, 0x9D89, 0xF988, 0x9D8A,
+	0xF989, 0x9D8B, 0xF98A, 0x9D8C, 0xF98B, 0x9D8D, 0xF98C, 0x9D8E,	0xF98D, 0x9D8F, 0xF98E, 0x9D90, 0xF98F, 0x9D91, 0xF990, 0x9D92,
+	0xF991, 0x9D93, 0xF992, 0x9D94, 0xF993, 0x9D95, 0xF994, 0x9D96,	0xF995, 0x9D97, 0xF996, 0x9D98, 0xF997, 0x9D99, 0xF998, 0x9D9A,
+	0xF999, 0x9D9B, 0xF99A, 0x9D9C, 0xF99B, 0x9D9D, 0xF99C, 0x9D9E,	0xF99D, 0x9D9F, 0xF99E, 0x9DA0, 0xF99F, 0x9DA1, 0xF9A0, 0x9DA2,
+	0xFA40, 0x9DA3, 0xFA41, 0x9DA4, 0xFA42, 0x9DA5, 0xFA43, 0x9DA6,	0xFA44, 0x9DA7, 0xFA45, 0x9DA8, 0xFA46, 0x9DA9, 0xFA47, 0x9DAA,
+	0xFA48, 0x9DAB, 0xFA49, 0x9DAC, 0xFA4A, 0x9DAD, 0xFA4B, 0x9DAE,	0xFA4C, 0x9DAF, 0xFA4D, 0x9DB0, 0xFA4E, 0x9DB1, 0xFA4F, 0x9DB2,
+	0xFA50, 0x9DB3, 0xFA51, 0x9DB4, 0xFA52, 0x9DB5, 0xFA53, 0x9DB6,	0xFA54, 0x9DB7, 0xFA55, 0x9DB8, 0xFA56, 0x9DB9, 0xFA57, 0x9DBA,
+	0xFA58, 0x9DBB, 0xFA59, 0x9DBC, 0xFA5A, 0x9DBD, 0xFA5B, 0x9DBE,	0xFA5C, 0x9DBF, 0xFA5D, 0x9DC0, 0xFA5E, 0x9DC1, 0xFA5F, 0x9DC2,
+	0xFA60, 0x9DC3, 0xFA61, 0x9DC4, 0xFA62, 0x9DC5, 0xFA63, 0x9DC6,	0xFA64, 0x9DC7, 0xFA65, 0x9DC8, 0xFA66, 0x9DC9, 0xFA67, 0x9DCA,
+	0xFA68, 0x9DCB, 0xFA69, 0x9DCC, 0xFA6A, 0x9DCD, 0xFA6B, 0x9DCE,	0xFA6C, 0x9DCF, 0xFA6D, 0x9DD0, 0xFA6E, 0x9DD1, 0xFA6F, 0x9DD2,
+	0xFA70, 0x9DD3, 0xFA71, 0x9DD4, 0xFA72, 0x9DD5, 0xFA73, 0x9DD6,	0xFA74, 0x9DD7, 0xFA75, 0x9DD8, 0xFA76, 0x9DD9, 0xFA77, 0x9DDA,
+	0xFA78, 0x9DDB, 0xFA79, 0x9DDC, 0xFA7A, 0x9DDD, 0xFA7B, 0x9DDE,	0xFA7C, 0x9DDF, 0xFA7D, 0x9DE0, 0xFA7E, 0x9DE1, 0xFA80, 0x9DE2,
+	0xFA81, 0x9DE3, 0xFA82, 0x9DE4, 0xFA83, 0x9DE5, 0xFA84, 0x9DE6,	0xFA85, 0x9DE7, 0xFA86, 0x9DE8, 0xFA87, 0x9DE9, 0xFA88, 0x9DEA,
+	0xFA89, 0x9DEB, 0xFA8A, 0x9DEC, 0xFA8B, 0x9DED, 0xFA8C, 0x9DEE,	0xFA8D, 0x9DEF, 0xFA8E, 0x9DF0, 0xFA8F, 0x9DF1, 0xFA90, 0x9DF2,
+	0xFA91, 0x9DF3, 0xFA92, 0x9DF4, 0xFA93, 0x9DF5, 0xFA94, 0x9DF6,	0xFA95, 0x9DF7, 0xFA96, 0x9DF8, 0xFA97, 0x9DF9, 0xFA98, 0x9DFA,
+	0xFA99, 0x9DFB, 0xFA9A, 0x9DFC, 0xFA9B, 0x9DFD, 0xFA9C, 0x9DFE,	0xFA9D, 0x9DFF, 0xFA9E, 0x9E00, 0xFA9F, 0x9E01, 0xFAA0, 0x9E02,
+	0xFB40, 0x9E03, 0xFB41, 0x9E04, 0xFB42, 0x9E05, 0xFB43, 0x9E06,	0xFB44, 0x9E07, 0xFB45, 0x9E08, 0xFB46, 0x9E09, 0xFB47, 0x9E0A,
+	0xFB48, 0x9E0B, 0xFB49, 0x9E0C, 0xFB4A, 0x9E0D, 0xFB4B, 0x9E0E,	0xFB4C, 0x9E0F, 0xFB4D, 0x9E10, 0xFB4E, 0x9E11, 0xFB4F, 0x9E12,
+	0xFB50, 0x9E13, 0xFB51, 0x9E14, 0xFB52, 0x9E15, 0xFB53, 0x9E16,	0xFB54, 0x9E17, 0xFB55, 0x9E18, 0xFB56, 0x9E19, 0xFB57, 0x9E1A,
+	0xFB58, 0x9E1B, 0xFB59, 0x9E1C, 0xFB5A, 0x9E1D, 0xFB5B, 0x9E1E,	0xFB5C, 0x9E24, 0xFB5D, 0x9E27, 0xFB5E, 0x9E2E, 0xFB5F, 0x9E30,
+	0xFB60, 0x9E34, 0xFB61, 0x9E3B, 0xFB62, 0x9E3C, 0xFB63, 0x9E40,	0xFB64, 0x9E4D, 0xFB65, 0x9E50, 0xFB66, 0x9E52, 0xFB67, 0x9E53,
+	0xFB68, 0x9E54, 0xFB69, 0x9E56, 0xFB6A, 0x9E59, 0xFB6B, 0x9E5D,	0xFB6C, 0x9E5F, 0xFB6D, 0x9E60, 0xFB6E, 0x9E61, 0xFB6F, 0x9E62,
+	0xFB70, 0x9E65, 0xFB71, 0x9E6E, 0xFB72, 0x9E6F, 0xFB73, 0x9E72,	0xFB74, 0x9E74, 0xFB75, 0x9E75, 0xFB76, 0x9E76, 0xFB77, 0x9E77,
+	0xFB78, 0x9E78, 0xFB79, 0x9E79, 0xFB7A, 0x9E7A, 0xFB7B, 0x9E7B,	0xFB7C, 0x9E7C, 0xFB7D, 0x9E7D, 0xFB7E, 0x9E80, 0xFB80, 0x9E81,
+	0xFB81, 0x9E83, 0xFB82, 0x9E84, 0xFB83, 0x9E85, 0xFB84, 0x9E86,	0xFB85, 0x9E89, 0xFB86, 0x9E8A, 0xFB87, 0x9E8C, 0xFB88, 0x9E8D,
+	0xFB89, 0x9E8E, 0xFB8A, 0x9E8F, 0xFB8B, 0x9E90, 0xFB8C, 0x9E91,	0xFB8D, 0x9E94, 0xFB8E, 0x9E95, 0xFB8F, 0x9E96, 0xFB90, 0x9E97,
+	0xFB91, 0x9E98, 0xFB92, 0x9E99, 0xFB93, 0x9E9A, 0xFB94, 0x9E9B,	0xFB95, 0x9E9C, 0xFB96, 0x9E9E, 0xFB97, 0x9EA0, 0xFB98, 0x9EA1,
+	0xFB99, 0x9EA2, 0xFB9A, 0x9EA3, 0xFB9B, 0x9EA4, 0xFB9C, 0x9EA5,	0xFB9D, 0x9EA7, 0xFB9E, 0x9EA8, 0xFB9F, 0x9EA9, 0xFBA0, 0x9EAA,
+	0xFC40, 0x9EAB, 0xFC41, 0x9EAC, 0xFC42, 0x9EAD, 0xFC43, 0x9EAE,	0xFC44, 0x9EAF, 0xFC45, 0x9EB0, 0xFC46, 0x9EB1, 0xFC47, 0x9EB2,
+	0xFC48, 0x9EB3, 0xFC49, 0x9EB5, 0xFC4A, 0x9EB6, 0xFC4B, 0x9EB7,	0xFC4C, 0x9EB9, 0xFC4D, 0x9EBA, 0xFC4E, 0x9EBC, 0xFC4F, 0x9EBF,
+	0xFC50, 0x9EC0, 0xFC51, 0x9EC1, 0xFC52, 0x9EC2, 0xFC53, 0x9EC3,	0xFC54, 0x9EC5, 0xFC55, 0x9EC6, 0xFC56, 0x9EC7, 0xFC57, 0x9EC8,
+	0xFC58, 0x9ECA, 0xFC59, 0x9ECB, 0xFC5A, 0x9ECC, 0xFC5B, 0x9ED0,	0xFC5C, 0x9ED2, 0xFC5D, 0x9ED3, 0xFC5E, 0x9ED5, 0xFC5F, 0x9ED6,
+	0xFC60, 0x9ED7, 0xFC61, 0x9ED9, 0xFC62, 0x9EDA, 0xFC63, 0x9EDE,	0xFC64, 0x9EE1, 0xFC65, 0x9EE3, 0xFC66, 0x9EE4, 0xFC67, 0x9EE6,
+	0xFC68, 0x9EE8, 0xFC69, 0x9EEB, 0xFC6A, 0x9EEC, 0xFC6B, 0x9EED,	0xFC6C, 0x9EEE, 0xFC6D, 0x9EF0, 0xFC6E, 0x9EF1, 0xFC6F, 0x9EF2,
+	0xFC70, 0x9EF3, 0xFC71, 0x9EF4, 0xFC72, 0x9EF5, 0xFC73, 0x9EF6,	0xFC74, 0x9EF7, 0xFC75, 0x9EF8, 0xFC76, 0x9EFA, 0xFC77, 0x9EFD,
+	0xFC78, 0x9EFF, 0xFC79, 0x9F00, 0xFC7A, 0x9F01, 0xFC7B, 0x9F02,	0xFC7C, 0x9F03, 0xFC7D, 0x9F04, 0xFC7E, 0x9F05, 0xFC80, 0x9F06,
+	0xFC81, 0x9F07, 0xFC82, 0x9F08, 0xFC83, 0x9F09, 0xFC84, 0x9F0A,	0xFC85, 0x9F0C, 0xFC86, 0x9F0F, 0xFC87, 0x9F11, 0xFC88, 0x9F12,
+	0xFC89, 0x9F14, 0xFC8A, 0x9F15, 0xFC8B, 0x9F16, 0xFC8C, 0x9F18,	0xFC8D, 0x9F1A, 0xFC8E, 0x9F1B, 0xFC8F, 0x9F1C, 0xFC90, 0x9F1D,
+	0xFC91, 0x9F1E, 0xFC92, 0x9F1F, 0xFC93, 0x9F21, 0xFC94, 0x9F23,	0xFC95, 0x9F24, 0xFC96, 0x9F25, 0xFC97, 0x9F26, 0xFC98, 0x9F27,
+	0xFC99, 0x9F28, 0xFC9A, 0x9F29, 0xFC9B, 0x9F2A, 0xFC9C, 0x9F2B,	0xFC9D, 0x9F2D, 0xFC9E, 0x9F2E, 0xFC9F, 0x9F30, 0xFCA0, 0x9F31,
+	0xFD40, 0x9F32, 0xFD41, 0x9F33, 0xFD42, 0x9F34, 0xFD43, 0x9F35,	0xFD44, 0x9F36, 0xFD45, 0x9F38, 0xFD46, 0x9F3A, 0xFD47, 0x9F3C,
+	0xFD48, 0x9F3F, 0xFD49, 0x9F40, 0xFD4A, 0x9F41, 0xFD4B, 0x9F42,	0xFD4C, 0x9F43, 0xFD4D, 0x9F45, 0xFD4E, 0x9F46, 0xFD4F, 0x9F47,
+	0xFD50, 0x9F48, 0xFD51, 0x9F49, 0xFD52, 0x9F4A, 0xFD53, 0x9F4B,	0xFD54, 0x9F4C, 0xFD55, 0x9F4D, 0xFD56, 0x9F4E, 0xFD57, 0x9F4F,
+	0xFD58, 0x9F52, 0xFD59, 0x9F53, 0xFD5A, 0x9F54, 0xFD5B, 0x9F55,	0xFD5C, 0x9F56, 0xFD5D, 0x9F57, 0xFD5E, 0x9F58, 0xFD5F, 0x9F59,
+	0xFD60, 0x9F5A, 0xFD61, 0x9F5B, 0xFD62, 0x9F5C, 0xFD63, 0x9F5D,	0xFD64, 0x9F5E, 0xFD65, 0x9F5F, 0xFD66, 0x9F60, 0xFD67, 0x9F61,
+	0xFD68, 0x9F62, 0xFD69, 0x9F63, 0xFD6A, 0x9F64, 0xFD6B, 0x9F65,	0xFD6C, 0x9F66, 0xFD6D, 0x9F67, 0xFD6E, 0x9F68, 0xFD6F, 0x9F69,
+	0xFD70, 0x9F6A, 0xFD71, 0x9F6B, 0xFD72, 0x9F6C, 0xFD73, 0x9F6D,	0xFD74, 0x9F6E, 0xFD75, 0x9F6F, 0xFD76, 0x9F70, 0xFD77, 0x9F71,
+	0xFD78, 0x9F72, 0xFD79, 0x9F73, 0xFD7A, 0x9F74, 0xFD7B, 0x9F75,	0xFD7C, 0x9F76, 0xFD7D, 0x9F77, 0xFD7E, 0x9F78, 0xFD80, 0x9F79,
+	0xFD81, 0x9F7A, 0xFD82, 0x9F7B, 0xFD83, 0x9F7C, 0xFD84, 0x9F7D,	0xFD85, 0x9F7E, 0xFD86, 0x9F81, 0xFD87, 0x9F82, 0xFD88, 0x9F8D,
+	0xFD89, 0x9F8E, 0xFD8A, 0x9F8F, 0xFD8B, 0x9F90, 0xFD8C, 0x9F91,	0xFD8D, 0x9F92, 0xFD8E, 0x9F93, 0xFD8F, 0x9F94, 0xFD90, 0x9F95,
+	0xFD91, 0x9F96, 0xFD92, 0x9F97, 0xFD93, 0x9F98, 0xFD94, 0x9F9C,	0xFD95, 0x9F9D, 0xFD96, 0x9F9E, 0xFD97, 0x9FA1, 0xFD98, 0x9FA2,
+	0xFD99, 0x9FA3, 0xFD9A, 0x9FA4, 0xFD9B, 0x9FA5, 0xFD9C, 0xF92C,	0xFD9D, 0xF979, 0xFD9E, 0xF995, 0xFD9F, 0xF9E7, 0xFDA0, 0xF9F1,
+	0xFE40, 0xFA0C, 0xFE41, 0xFA0D, 0xFE42, 0xFA0E, 0xFE43, 0xFA0F,	0xFE44, 0xFA11, 0xFE45, 0xFA13, 0xFE46, 0xFA14, 0xFE47, 0xFA18,
+	0xFE48, 0xFA1F, 0xFE49, 0xFA20, 0xFE4A, 0xFA21, 0xFE4B, 0xFA23,	0xFE4C, 0xFA24, 0xFE4D, 0xFA27, 0xFE4E, 0xFA28, 0xFE4F, 0xFA29,
+	0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 949 || FF_CODE_PAGE == 0	/* Korean */
+static const WCHAR uni2oem949[] = {	/* Unicode --> Korean pairs */
+	0x00A1, 0xA2AE, 0x00A4, 0xA2B4, 0x00A7, 0xA1D7, 0x00A8, 0xA1A7,	0x00AA, 0xA8A3, 0x00AD, 0xA1A9, 0x00AE, 0xA2E7, 0x00B0, 0xA1C6,
+	0x00B1, 0xA1BE, 0x00B2, 0xA9F7, 0x00B3, 0xA9F8, 0x00B4, 0xA2A5,	0x00B6, 0xA2D2, 0x00B7, 0xA1A4, 0x00B8, 0xA2AC, 0x00B9, 0xA9F6,
+	0x00BA, 0xA8AC, 0x00BC, 0xA8F9, 0x00BD, 0xA8F6, 0x00BE, 0xA8FA,	0x00BF, 0xA2AF, 0x00C6, 0xA8A1, 0x00D0, 0xA8A2, 0x00D7, 0xA1BF,
+	0x00D8, 0xA8AA, 0x00DE, 0xA8AD, 0x00DF, 0xA9AC, 0x00E6, 0xA9A1,	0x00F0, 0xA9A3, 0x00F7, 0xA1C0, 0x00F8, 0xA9AA, 0x00FE, 0xA9AD,
+	0x0111, 0xA9A2, 0x0126, 0xA8A4, 0x0127, 0xA9A4, 0x0131, 0xA9A5,	0x0132, 0xA8A6, 0x0133, 0xA9A6, 0x0138, 0xA9A7, 0x013F, 0xA8A8,
+	0x0140, 0xA9A8, 0x0141, 0xA8A9, 0x0142, 0xA9A9, 0x0149, 0xA9B0,	0x014A, 0xA8AF, 0x014B, 0xA9AF, 0x0152, 0xA8AB, 0x0153, 0xA9AB,
+	0x0166, 0xA8AE, 0x0167, 0xA9AE, 0x02C7, 0xA2A7, 0x02D0, 0xA2B0,	0x02D8, 0xA2A8, 0x02D9, 0xA2AB, 0x02DA, 0xA2AA, 0x02DB, 0xA2AD,
+	0x02DD, 0xA2A9, 0x0391, 0xA5C1, 0x0392, 0xA5C2, 0x0393, 0xA5C3,	0x0394, 0xA5C4, 0x0395, 0xA5C5, 0x0396, 0xA5C6, 0x0397, 0xA5C7,
+	0x0398, 0xA5C8, 0x0399, 0xA5C9, 0x039A, 0xA5CA, 0x039B, 0xA5CB,	0x039C, 0xA5CC, 0x039D, 0xA5CD, 0x039E, 0xA5CE, 0x039F, 0xA5CF,
+	0x03A0, 0xA5D0, 0x03A1, 0xA5D1, 0x03A3, 0xA5D2, 0x03A4, 0xA5D3,	0x03A5, 0xA5D4, 0x03A6, 0xA5D5, 0x03A7, 0xA5D6, 0x03A8, 0xA5D7,
+	0x03A9, 0xA5D8, 0x03B1, 0xA5E1, 0x03B2, 0xA5E2, 0x03B3, 0xA5E3,	0x03B4, 0xA5E4, 0x03B5, 0xA5E5, 0x03B6, 0xA5E6, 0x03B7, 0xA5E7,
+	0x03B8, 0xA5E8, 0x03B9, 0xA5E9, 0x03BA, 0xA5EA, 0x03BB, 0xA5EB,	0x03BC, 0xA5EC, 0x03BD, 0xA5ED, 0x03BE, 0xA5EE, 0x03BF, 0xA5EF,
+	0x03C0, 0xA5F0, 0x03C1, 0xA5F1, 0x03C3, 0xA5F2, 0x03C4, 0xA5F3,	0x03C5, 0xA5F4, 0x03C6, 0xA5F5, 0x03C7, 0xA5F6, 0x03C8, 0xA5F7,
+	0x03C9, 0xA5F8, 0x0401, 0xACA7, 0x0410, 0xACA1, 0x0411, 0xACA2,	0x0412, 0xACA3, 0x0413, 0xACA4, 0x0414, 0xACA5, 0x0415, 0xACA6,
+	0x0416, 0xACA8, 0x0417, 0xACA9, 0x0418, 0xACAA, 0x0419, 0xACAB,	0x041A, 0xACAC, 0x041B, 0xACAD, 0x041C, 0xACAE, 0x041D, 0xACAF,
+	0x041E, 0xACB0, 0x041F, 0xACB1, 0x0420, 0xACB2, 0x0421, 0xACB3,	0x0422, 0xACB4, 0x0423, 0xACB5, 0x0424, 0xACB6, 0x0425, 0xACB7,
+	0x0426, 0xACB8, 0x0427, 0xACB9, 0x0428, 0xACBA, 0x0429, 0xACBB,	0x042A, 0xACBC, 0x042B, 0xACBD, 0x042C, 0xACBE, 0x042D, 0xACBF,
+	0x042E, 0xACC0, 0x042F, 0xACC1, 0x0430, 0xACD1, 0x0431, 0xACD2,	0x0432, 0xACD3, 0x0433, 0xACD4, 0x0434, 0xACD5, 0x0435, 0xACD6,
+	0x0436, 0xACD8, 0x0437, 0xACD9, 0x0438, 0xACDA, 0x0439, 0xACDB,	0x043A, 0xACDC, 0x043B, 0xACDD, 0x043C, 0xACDE, 0x043D, 0xACDF,
+	0x043E, 0xACE0, 0x043F, 0xACE1, 0x0440, 0xACE2, 0x0441, 0xACE3,	0x0442, 0xACE4, 0x0443, 0xACE5, 0x0444, 0xACE6, 0x0445, 0xACE7,
+	0x0446, 0xACE8, 0x0447, 0xACE9, 0x0448, 0xACEA, 0x0449, 0xACEB,	0x044A, 0xACEC, 0x044B, 0xACED, 0x044C, 0xACEE, 0x044D, 0xACEF,
+	0x044E, 0xACF0, 0x044F, 0xACF1, 0x0451, 0xACD7, 0x2015, 0xA1AA,	0x2018, 0xA1AE, 0x2019, 0xA1AF, 0x201C, 0xA1B0, 0x201D, 0xA1B1,
+	0x2020, 0xA2D3, 0x2021, 0xA2D4, 0x2025, 0xA1A5, 0x2026, 0xA1A6,	0x2030, 0xA2B6, 0x2032, 0xA1C7, 0x2033, 0xA1C8, 0x203B, 0xA1D8,
+	0x2074, 0xA9F9, 0x207F, 0xA9FA, 0x2081, 0xA9FB, 0x2082, 0xA9FC,	0x2083, 0xA9FD, 0x2084, 0xA9FE, 0x20AC, 0xA2E6, 0x2103, 0xA1C9,
+	0x2109, 0xA2B5, 0x2113, 0xA7A4, 0x2116, 0xA2E0, 0x2121, 0xA2E5,	0x2122, 0xA2E2, 0x2126, 0xA7D9, 0x212B, 0xA1CA, 0x2153, 0xA8F7,
+	0x2154, 0xA8F8, 0x215B, 0xA8FB, 0x215C, 0xA8FC, 0x215D, 0xA8FD,	0x215E, 0xA8FE, 0x2160, 0xA5B0, 0x2161, 0xA5B1, 0x2162, 0xA5B2,
+	0x2163, 0xA5B3, 0x2164, 0xA5B4, 0x2165, 0xA5B5, 0x2166, 0xA5B6,	0x2167, 0xA5B7, 0x2168, 0xA5B8, 0x2169, 0xA5B9, 0x2170, 0xA5A1,
+	0x2171, 0xA5A2, 0x2172, 0xA5A3, 0x2173, 0xA5A4, 0x2174, 0xA5A5,	0x2175, 0xA5A6, 0x2176, 0xA5A7, 0x2177, 0xA5A8, 0x2178, 0xA5A9,
+	0x2179, 0xA5AA, 0x2190, 0xA1E7, 0x2191, 0xA1E8, 0x2192, 0xA1E6,	0x2193, 0xA1E9, 0x2194, 0xA1EA, 0x2195, 0xA2D5, 0x2196, 0xA2D8,
+	0x2197, 0xA2D6, 0x2198, 0xA2D9, 0x2199, 0xA2D7, 0x21D2, 0xA2A1,	0x21D4, 0xA2A2, 0x2200, 0xA2A3, 0x2202, 0xA1D3, 0x2203, 0xA2A4,
+	0x2207, 0xA1D4, 0x2208, 0xA1F4, 0x220B, 0xA1F5, 0x220F, 0xA2B3,	0x2211, 0xA2B2, 0x221A, 0xA1EE, 0x221D, 0xA1F0, 0x221E, 0xA1C4,
+	0x2220, 0xA1D0, 0x2225, 0xA1AB, 0x2227, 0xA1FC, 0x2228, 0xA1FD,	0x2229, 0xA1FB, 0x222A, 0xA1FA, 0x222B, 0xA1F2, 0x222C, 0xA1F3,
+	0x222E, 0xA2B1, 0x2234, 0xA1C5, 0x2235, 0xA1F1, 0x223C, 0xA1AD,	0x223D, 0xA1EF, 0x2252, 0xA1D6, 0x2260, 0xA1C1, 0x2261, 0xA1D5,
+	0x2264, 0xA1C2, 0x2265, 0xA1C3, 0x226A, 0xA1EC, 0x226B, 0xA1ED,	0x2282, 0xA1F8, 0x2283, 0xA1F9, 0x2286, 0xA1F6, 0x2287, 0xA1F7,
+	0x2299, 0xA2C1, 0x22A5, 0xA1D1, 0x2312, 0xA1D2, 0x2460, 0xA8E7,	0x2461, 0xA8E8, 0x2462, 0xA8E9, 0x2463, 0xA8EA, 0x2464, 0xA8EB,
+	0x2465, 0xA8EC, 0x2466, 0xA8ED, 0x2467, 0xA8EE, 0x2468, 0xA8EF,	0x2469, 0xA8F0, 0x246A, 0xA8F1, 0x246B, 0xA8F2, 0x246C, 0xA8F3,
+	0x246D, 0xA8F4, 0x246E, 0xA8F5, 0x2474, 0xA9E7, 0x2475, 0xA9E8,	0x2476, 0xA9E9, 0x2477, 0xA9EA, 0x2478, 0xA9EB, 0x2479, 0xA9EC,
+	0x247A, 0xA9ED, 0x247B, 0xA9EE, 0x247C, 0xA9EF, 0x247D, 0xA9F0,	0x247E, 0xA9F1, 0x247F, 0xA9F2, 0x2480, 0xA9F3, 0x2481, 0xA9F4,
+	0x2482, 0xA9F5, 0x249C, 0xA9CD, 0x249D, 0xA9CE, 0x249E, 0xA9CF,	0x249F, 0xA9D0, 0x24A0, 0xA9D1, 0x24A1, 0xA9D2, 0x24A2, 0xA9D3,
+	0x24A3, 0xA9D4, 0x24A4, 0xA9D5, 0x24A5, 0xA9D6, 0x24A6, 0xA9D7,	0x24A7, 0xA9D8, 0x24A8, 0xA9D9, 0x24A9, 0xA9DA, 0x24AA, 0xA9DB,
+	0x24AB, 0xA9DC, 0x24AC, 0xA9DD, 0x24AD, 0xA9DE, 0x24AE, 0xA9DF,	0x24AF, 0xA9E0, 0x24B0, 0xA9E1, 0x24B1, 0xA9E2, 0x24B2, 0xA9E3,
+	0x24B3, 0xA9E4, 0x24B4, 0xA9E5, 0x24B5, 0xA9E6, 0x24D0, 0xA8CD,	0x24D1, 0xA8CE, 0x24D2, 0xA8CF, 0x24D3, 0xA8D0, 0x24D4, 0xA8D1,
+	0x24D5, 0xA8D2, 0x24D6, 0xA8D3, 0x24D7, 0xA8D4, 0x24D8, 0xA8D5,	0x24D9, 0xA8D6, 0x24DA, 0xA8D7, 0x24DB, 0xA8D8, 0x24DC, 0xA8D9,
+	0x24DD, 0xA8DA, 0x24DE, 0xA8DB, 0x24DF, 0xA8DC, 0x24E0, 0xA8DD,	0x24E1, 0xA8DE, 0x24E2, 0xA8DF, 0x24E3, 0xA8E0, 0x24E4, 0xA8E1,
+	0x24E5, 0xA8E2, 0x24E6, 0xA8E3, 0x24E7, 0xA8E4, 0x24E8, 0xA8E5,	0x24E9, 0xA8E6, 0x2500, 0xA6A1, 0x2501, 0xA6AC, 0x2502, 0xA6A2,
+	0x2503, 0xA6AD, 0x250C, 0xA6A3, 0x250D, 0xA6C8, 0x250E, 0xA6C7,	0x250F, 0xA6AE, 0x2510, 0xA6A4, 0x2511, 0xA6C2, 0x2512, 0xA6C1,
+	0x2513, 0xA6AF, 0x2514, 0xA6A6, 0x2515, 0xA6C6, 0x2516, 0xA6C5,	0x2517, 0xA6B1, 0x2518, 0xA6A5, 0x2519, 0xA6C4, 0x251A, 0xA6C3,
+	0x251B, 0xA6B0, 0x251C, 0xA6A7, 0x251D, 0xA6BC, 0x251E, 0xA6C9,	0x251F, 0xA6CA, 0x2520, 0xA6B7, 0x2521, 0xA6CB, 0x2522, 0xA6CC,
+	0x2523, 0xA6B2, 0x2524, 0xA6A9, 0x2525, 0xA6BE, 0x2526, 0xA6CD,	0x2527, 0xA6CE, 0x2528, 0xA6B9, 0x2529, 0xA6CF, 0x252A, 0xA6D0,
+	0x252B, 0xA6B4, 0x252C, 0xA6A8, 0x252D, 0xA6D1, 0x252E, 0xA6D2,	0x252F, 0xA6B8, 0x2530, 0xA6BD, 0x2531, 0xA6D3, 0x2532, 0xA6D4,
+	0x2533, 0xA6B3, 0x2534, 0xA6AA, 0x2535, 0xA6D5, 0x2536, 0xA6D6,	0x2537, 0xA6BA, 0x2538, 0xA6BF, 0x2539, 0xA6D7, 0x253A, 0xA6D8,
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+	0x2543, 0xA6DD, 0x2544, 0xA6DE, 0x2545, 0xA6DF, 0x2546, 0xA6E0,	0x2547, 0xA6E1, 0x2548, 0xA6E2, 0x2549, 0xA6E3, 0x254A, 0xA6E4,
+	0x254B, 0xA6B6, 0x2592, 0xA2C6, 0x25A0, 0xA1E1, 0x25A1, 0xA1E0,	0x25A3, 0xA2C3, 0x25A4, 0xA2C7, 0x25A5, 0xA2C8, 0x25A6, 0xA2CB,
+	0x25A7, 0xA2CA, 0x25A8, 0xA2C9, 0x25A9, 0xA2CC, 0x25B2, 0xA1E3,	0x25B3, 0xA1E2, 0x25B6, 0xA2BA, 0x25B7, 0xA2B9, 0x25BC, 0xA1E5,
+	0x25BD, 0xA1E4, 0x25C0, 0xA2B8, 0x25C1, 0xA2B7, 0x25C6, 0xA1DF,	0x25C7, 0xA1DE, 0x25C8, 0xA2C2, 0x25CB, 0xA1DB, 0x25CE, 0xA1DD,
+	0x25CF, 0xA1DC, 0x25D0, 0xA2C4, 0x25D1, 0xA2C5, 0x2605, 0xA1DA,	0x2606, 0xA1D9, 0x260E, 0xA2CF, 0x260F, 0xA2CE, 0x261C, 0xA2D0,
+	0x261E, 0xA2D1, 0x2640, 0xA1CF, 0x2642, 0xA1CE, 0x2660, 0xA2BC,	0x2661, 0xA2BD, 0x2663, 0xA2C0, 0x2664, 0xA2BB, 0x2665, 0xA2BE,
+	0x2667, 0xA2BF, 0x2668, 0xA2CD, 0x2669, 0xA2DB, 0x266A, 0xA2DC,	0x266C, 0xA2DD, 0x266D, 0xA2DA, 0x3000, 0xA1A1, 0x3001, 0xA1A2,
+	0x3002, 0xA1A3, 0x3003, 0xA1A8, 0x3008, 0xA1B4, 0x3009, 0xA1B5,	0x300A, 0xA1B6, 0x300B, 0xA1B7, 0x300C, 0xA1B8, 0x300D, 0xA1B9,
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+	0x3042, 0xAAA2, 0x3043, 0xAAA3, 0x3044, 0xAAA4, 0x3045, 0xAAA5,	0x3046, 0xAAA6, 0x3047, 0xAAA7, 0x3048, 0xAAA8, 0x3049, 0xAAA9,
+	0x304A, 0xAAAA, 0x304B, 0xAAAB, 0x304C, 0xAAAC, 0x304D, 0xAAAD,	0x304E, 0xAAAE, 0x304F, 0xAAAF, 0x3050, 0xAAB0, 0x3051, 0xAAB1,
+	0x3052, 0xAAB2, 0x3053, 0xAAB3, 0x3054, 0xAAB4, 0x3055, 0xAAB5,	0x3056, 0xAAB6, 0x3057, 0xAAB7, 0x3058, 0xAAB8, 0x3059, 0xAAB9,
+	0x305A, 0xAABA, 0x305B, 0xAABB, 0x305C, 0xAABC, 0x305D, 0xAABD,	0x305E, 0xAABE, 0x305F, 0xAABF, 0x3060, 0xAAC0, 0x3061, 0xAAC1,
+	0x3062, 0xAAC2, 0x3063, 0xAAC3, 0x3064, 0xAAC4, 0x3065, 0xAAC5,	0x3066, 0xAAC6, 0x3067, 0xAAC7, 0x3068, 0xAAC8, 0x3069, 0xAAC9,
+	0x306A, 0xAACA, 0x306B, 0xAACB, 0x306C, 0xAACC, 0x306D, 0xAACD,	0x306E, 0xAACE, 0x306F, 0xAACF, 0x3070, 0xAAD0, 0x3071, 0xAAD1,
+	0x3072, 0xAAD2, 0x3073, 0xAAD3, 0x3074, 0xAAD4, 0x3075, 0xAAD5,	0x3076, 0xAAD6, 0x3077, 0xAAD7, 0x3078, 0xAAD8, 0x3079, 0xAAD9,
+	0x307A, 0xAADA, 0x307B, 0xAADB, 0x307C, 0xAADC, 0x307D, 0xAADD,	0x307E, 0xAADE, 0x307F, 0xAADF, 0x3080, 0xAAE0, 0x3081, 0xAAE1,
+	0x3082, 0xAAE2, 0x3083, 0xAAE3, 0x3084, 0xAAE4, 0x3085, 0xAAE5,	0x3086, 0xAAE6, 0x3087, 0xAAE7, 0x3088, 0xAAE8, 0x3089, 0xAAE9,
+	0x308A, 0xAAEA, 0x308B, 0xAAEB, 0x308C, 0xAAEC, 0x308D, 0xAAED,	0x308E, 0xAAEE, 0x308F, 0xAAEF, 0x3090, 0xAAF0, 0x3091, 0xAAF1,
+	0x3092, 0xAAF2, 0x3093, 0xAAF3, 0x30A1, 0xABA1, 0x30A2, 0xABA2,	0x30A3, 0xABA3, 0x30A4, 0xABA4, 0x30A5, 0xABA5, 0x30A6, 0xABA6,
+	0x30A7, 0xABA7, 0x30A8, 0xABA8, 0x30A9, 0xABA9, 0x30AA, 0xABAA,	0x30AB, 0xABAB, 0x30AC, 0xABAC, 0x30AD, 0xABAD, 0x30AE, 0xABAE,
+	0x30AF, 0xABAF, 0x30B0, 0xABB0, 0x30B1, 0xABB1, 0x30B2, 0xABB2,	0x30B3, 0xABB3, 0x30B4, 0xABB4, 0x30B5, 0xABB5, 0x30B6, 0xABB6,
+	0x30B7, 0xABB7, 0x30B8, 0xABB8, 0x30B9, 0xABB9, 0x30BA, 0xABBA,	0x30BB, 0xABBB, 0x30BC, 0xABBC, 0x30BD, 0xABBD, 0x30BE, 0xABBE,
+	0x30BF, 0xABBF, 0x30C0, 0xABC0, 0x30C1, 0xABC1, 0x30C2, 0xABC2,	0x30C3, 0xABC3, 0x30C4, 0xABC4, 0x30C5, 0xABC5, 0x30C6, 0xABC6,
+	0x30C7, 0xABC7, 0x30C8, 0xABC8, 0x30C9, 0xABC9, 0x30CA, 0xABCA,	0x30CB, 0xABCB, 0x30CC, 0xABCC, 0x30CD, 0xABCD, 0x30CE, 0xABCE,
+	0x30CF, 0xABCF, 0x30D0, 0xABD0, 0x30D1, 0xABD1, 0x30D2, 0xABD2,	0x30D3, 0xABD3, 0x30D4, 0xABD4, 0x30D5, 0xABD5, 0x30D6, 0xABD6,
+	0x30D7, 0xABD7, 0x30D8, 0xABD8, 0x30D9, 0xABD9, 0x30DA, 0xABDA,	0x30DB, 0xABDB, 0x30DC, 0xABDC, 0x30DD, 0xABDD, 0x30DE, 0xABDE,
+	0x30DF, 0xABDF, 0x30E0, 0xABE0, 0x30E1, 0xABE1, 0x30E2, 0xABE2,	0x30E3, 0xABE3, 0x30E4, 0xABE4, 0x30E5, 0xABE5, 0x30E6, 0xABE6,
+	0x30E7, 0xABE7, 0x30E8, 0xABE8, 0x30E9, 0xABE9, 0x30EA, 0xABEA,	0x30EB, 0xABEB, 0x30EC, 0xABEC, 0x30ED, 0xABED, 0x30EE, 0xABEE,
+	0x30EF, 0xABEF, 0x30F0, 0xABF0, 0x30F1, 0xABF1, 0x30F2, 0xABF2,	0x30F3, 0xABF3, 0x30F4, 0xABF4, 0x30F5, 0xABF5, 0x30F6, 0xABF6,
+	0x3131, 0xA4A1, 0x3132, 0xA4A2, 0x3133, 0xA4A3, 0x3134, 0xA4A4,	0x3135, 0xA4A5, 0x3136, 0xA4A6, 0x3137, 0xA4A7, 0x3138, 0xA4A8,
+	0x3139, 0xA4A9, 0x313A, 0xA4AA, 0x313B, 0xA4AB, 0x313C, 0xA4AC,	0x313D, 0xA4AD, 0x313E, 0xA4AE, 0x313F, 0xA4AF, 0x3140, 0xA4B0,
+	0x3141, 0xA4B1, 0x3142, 0xA4B2, 0x3143, 0xA4B3, 0x3144, 0xA4B4,	0x3145, 0xA4B5, 0x3146, 0xA4B6, 0x3147, 0xA4B7, 0x3148, 0xA4B8,
+	0x3149, 0xA4B9, 0x314A, 0xA4BA, 0x314B, 0xA4BB, 0x314C, 0xA4BC,	0x314D, 0xA4BD, 0x314E, 0xA4BE, 0x314F, 0xA4BF, 0x3150, 0xA4C0,
+	0x3151, 0xA4C1, 0x3152, 0xA4C2, 0x3153, 0xA4C3, 0x3154, 0xA4C4,	0x3155, 0xA4C5, 0x3156, 0xA4C6, 0x3157, 0xA4C7, 0x3158, 0xA4C8,
+	0x3159, 0xA4C9, 0x315A, 0xA4CA, 0x315B, 0xA4CB, 0x315C, 0xA4CC,	0x315D, 0xA4CD, 0x315E, 0xA4CE, 0x315F, 0xA4CF, 0x3160, 0xA4D0,
+	0x3161, 0xA4D1, 0x3162, 0xA4D2, 0x3163, 0xA4D3, 0x3164, 0xA4D4,	0x3165, 0xA4D5, 0x3166, 0xA4D6, 0x3167, 0xA4D7, 0x3168, 0xA4D8,
+	0x3169, 0xA4D9, 0x316A, 0xA4DA, 0x316B, 0xA4DB, 0x316C, 0xA4DC,	0x316D, 0xA4DD, 0x316E, 0xA4DE, 0x316F, 0xA4DF, 0x3170, 0xA4E0,
+	0x3171, 0xA4E1, 0x3172, 0xA4E2, 0x3173, 0xA4E3, 0x3174, 0xA4E4,	0x3175, 0xA4E5, 0x3176, 0xA4E6, 0x3177, 0xA4E7, 0x3178, 0xA4E8,
+	0x3179, 0xA4E9, 0x317A, 0xA4EA, 0x317B, 0xA4EB, 0x317C, 0xA4EC,	0x317D, 0xA4ED, 0x317E, 0xA4EE, 0x317F, 0xA4EF, 0x3180, 0xA4F0,
+	0x3181, 0xA4F1, 0x3182, 0xA4F2, 0x3183, 0xA4F3, 0x3184, 0xA4F4,	0x3185, 0xA4F5, 0x3186, 0xA4F6, 0x3187, 0xA4F7, 0x3188, 0xA4F8,
+	0x3189, 0xA4F9, 0x318A, 0xA4FA, 0x318B, 0xA4FB, 0x318C, 0xA4FC,	0x318D, 0xA4FD, 0x318E, 0xA4FE, 0x3200, 0xA9B1, 0x3201, 0xA9B2,
+	0x3202, 0xA9B3, 0x3203, 0xA9B4, 0x3204, 0xA9B5, 0x3205, 0xA9B6,	0x3206, 0xA9B7, 0x3207, 0xA9B8, 0x3208, 0xA9B9, 0x3209, 0xA9BA,
+	0x320A, 0xA9BB, 0x320B, 0xA9BC, 0x320C, 0xA9BD, 0x320D, 0xA9BE,	0x320E, 0xA9BF, 0x320F, 0xA9C0, 0x3210, 0xA9C1, 0x3211, 0xA9C2,
+	0x3212, 0xA9C3, 0x3213, 0xA9C4, 0x3214, 0xA9C5, 0x3215, 0xA9C6,	0x3216, 0xA9C7, 0x3217, 0xA9C8, 0x3218, 0xA9C9, 0x3219, 0xA9CA,
+	0x321A, 0xA9CB, 0x321B, 0xA9CC, 0x321C, 0xA2DF, 0x3260, 0xA8B1,	0x3261, 0xA8B2, 0x3262, 0xA8B3, 0x3263, 0xA8B4, 0x3264, 0xA8B5,
+	0x3265, 0xA8B6, 0x3266, 0xA8B7, 0x3267, 0xA8B8, 0x3268, 0xA8B9,	0x3269, 0xA8BA, 0x326A, 0xA8BB, 0x326B, 0xA8BC, 0x326C, 0xA8BD,
+	0x326D, 0xA8BE, 0x326E, 0xA8BF, 0x326F, 0xA8C0, 0x3270, 0xA8C1,	0x3271, 0xA8C2, 0x3272, 0xA8C3, 0x3273, 0xA8C4, 0x3274, 0xA8C5,
+	0x3275, 0xA8C6, 0x3276, 0xA8C7, 0x3277, 0xA8C8, 0x3278, 0xA8C9,	0x3279, 0xA8CA, 0x327A, 0xA8CB, 0x327B, 0xA8CC, 0x327F, 0xA2DE,
+	0x3380, 0xA7C9, 0x3381, 0xA7CA, 0x3382, 0xA7CB, 0x3383, 0xA7CC,	0x3384, 0xA7CD, 0x3388, 0xA7BA, 0x3389, 0xA7BB, 0x338A, 0xA7DC,
+	0x338B, 0xA7DD, 0x338C, 0xA7DE, 0x338D, 0xA7B6, 0x338E, 0xA7B7,	0x338F, 0xA7B8, 0x3390, 0xA7D4, 0x3391, 0xA7D5, 0x3392, 0xA7D6,
+	0x3393, 0xA7D7, 0x3394, 0xA7D8, 0x3395, 0xA7A1, 0x3396, 0xA7A2,	0x3397, 0xA7A3, 0x3398, 0xA7A5, 0x3399, 0xA7AB, 0x339A, 0xA7AC,
+	0x339B, 0xA7AD, 0x339C, 0xA7AE, 0x339D, 0xA7AF, 0x339E, 0xA7B0,	0x339F, 0xA7B1, 0x33A0, 0xA7B2, 0x33A1, 0xA7B3, 0x33A2, 0xA7B4,
+	0x33A3, 0xA7A7, 0x33A4, 0xA7A8, 0x33A5, 0xA7A9, 0x33A6, 0xA7AA,	0x33A7, 0xA7BD, 0x33A8, 0xA7BE, 0x33A9, 0xA7E5, 0x33AA, 0xA7E6,
+	0x33AB, 0xA7E7, 0x33AC, 0xA7E8, 0x33AD, 0xA7E1, 0x33AE, 0xA7E2,	0x33AF, 0xA7E3, 0x33B0, 0xA7BF, 0x33B1, 0xA7C0, 0x33B2, 0xA7C1,
+	0x33B3, 0xA7C2, 0x33B4, 0xA7C3, 0x33B5, 0xA7C4, 0x33B6, 0xA7C5,	0x33B7, 0xA7C6, 0x33B8, 0xA7C7, 0x33B9, 0xA7C8, 0x33BA, 0xA7CE,
+	0x33BB, 0xA7CF, 0x33BC, 0xA7D0, 0x33BD, 0xA7D1, 0x33BE, 0xA7D2,	0x33BF, 0xA7D3, 0x33C0, 0xA7DA, 0x33C1, 0xA7DB, 0x33C2, 0xA2E3,
+	0x33C3, 0xA7EC, 0x33C4, 0xA7A6, 0x33C5, 0xA7E0, 0x33C6, 0xA7EF,	0x33C7, 0xA2E1, 0x33C8, 0xA7BC, 0x33C9, 0xA7ED, 0x33CA, 0xA7B5,
+	0x33CF, 0xA7B9, 0x33D0, 0xA7EA, 0x33D3, 0xA7EB, 0x33D6, 0xA7DF,	0x33D8, 0xA2E4, 0x33DB, 0xA7E4, 0x33DC, 0xA7EE, 0x33DD, 0xA7E9,
+	0x4E00, 0xECE9, 0x4E01, 0xEFCB, 0x4E03, 0xF6D2, 0x4E07, 0xD8B2,	0x4E08, 0xEDDB, 0x4E09, 0xDFB2, 0x4E0A, 0xDFBE, 0x4E0B, 0xF9BB,
+	0x4E0D, 0xDCF4, 0x4E11, 0xF5E4, 0x4E14, 0xF3A6, 0x4E15, 0xDDE0,	0x4E16, 0xE1A6, 0x4E18, 0xCEF8, 0x4E19, 0xDCB0, 0x4E1E, 0xE3AA,
+	0x4E2D, 0xF1E9, 0x4E32, 0xCDFA, 0x4E38, 0xFCAF, 0x4E39, 0xD3A1,	0x4E3B, 0xF1AB, 0x4E42, 0xE7D1, 0x4E43, 0xD2AC, 0x4E45, 0xCEF9,
+	0x4E4B, 0xF1FD, 0x4E4D, 0xDEBF, 0x4E4E, 0xFBBA, 0x4E4F, 0xF9B9,	0x4E56, 0xCED2, 0x4E58, 0xE3AB, 0x4E59, 0xEBE0, 0x4E5D, 0xCEFA,
+	0x4E5E, 0xCBF7, 0x4E5F, 0xE5A5, 0x4E6B, 0xCAE1, 0x4E6D, 0xD4CC,	0x4E73, 0xEAE1, 0x4E76, 0xDCE3, 0x4E77, 0xDFAD, 0x4E7E, 0xCBEB,
+	0x4E82, 0xD5AF, 0x4E86, 0xD6F5, 0x4E88, 0xE5F8, 0x4E8B, 0xDEC0,	0x4E8C, 0xECA3, 0x4E8E, 0xE9CD, 0x4E90, 0xEAA7, 0x4E91, 0xE9F6,
+	0x4E92, 0xFBBB, 0x4E94, 0xE7E9, 0x4E95, 0xEFCC, 0x4E98, 0xD0E6,	0x4E9B, 0xDEC1, 0x4E9E, 0xE4AC, 0x4EA1, 0xD8CC, 0x4EA2, 0xF9F1,
+	0x4EA4, 0xCEDF, 0x4EA5, 0xFAA4, 0x4EA6, 0xE6B2, 0x4EA8, 0xFAFB,	0x4EAB, 0xFABD, 0x4EAC, 0xCCC8, 0x4EAD, 0xEFCD, 0x4EAE, 0xD5D5,
+	0x4EB6, 0xD3A2, 0x4EBA, 0xECD1, 0x4EC0, 0xE4A7, 0x4EC1, 0xECD2,	0x4EC4, 0xF6B1, 0x4EC7, 0xCEFB, 0x4ECA, 0xD0D1, 0x4ECB, 0xCBBF,
+	0x4ECD, 0xEDA4, 0x4ED4, 0xEDA8, 0x4ED5, 0xDEC2, 0x4ED6, 0xF6E2,	0x4ED7, 0xEDDC, 0x4ED8, 0xDCF5, 0x4ED9, 0xE0B9, 0x4EDD, 0xD4CE,
+	0x4EDF, 0xF4B5, 0x4EE3, 0xD3DB, 0x4EE4, 0xD6B5, 0x4EE5, 0xECA4,	0x4EF0, 0xE4E6, 0x4EF2, 0xF1EA, 0x4EF6, 0xCBEC, 0x4EF7, 0xCBC0,
+	0x4EFB, 0xECF2, 0x4F01, 0xD0EA, 0x4F09, 0xF9F2, 0x4F0A, 0xECA5,	0x4F0B, 0xD0DF, 0x4F0D, 0xE7EA, 0x4F0E, 0xD0EB, 0x4F0F, 0xDCD1,
+	0x4F10, 0xDBE9, 0x4F11, 0xFDCC, 0x4F2F, 0xDBD7, 0x4F34, 0xDAE1,	0x4F36, 0xD6B6, 0x4F38, 0xE3DF, 0x4F3A, 0xDEC3, 0x4F3C, 0xDEC4,
+	0x4F3D, 0xCAA1, 0x4F43, 0xEEEC, 0x4F46, 0xD3A3, 0x4F47, 0xEEB7,	0x4F48, 0xF8CF, 0x4F4D, 0xEAC8, 0x4F4E, 0xEEB8, 0x4F4F, 0xF1AC,
+	0x4F50, 0xF1A5, 0x4F51, 0xE9CE, 0x4F55, 0xF9BC, 0x4F59, 0xE5F9,	0x4F5A, 0xECEA, 0x4F5B, 0xDDD6, 0x4F5C, 0xEDC2, 0x4F69, 0xF8A5,
+	0x4F6F, 0xE5BA, 0x4F70, 0xDBD8, 0x4F73, 0xCAA2, 0x4F76, 0xD1CD,	0x4F7A, 0xEEED, 0x4F7E, 0xECEB, 0x4F7F, 0xDEC5, 0x4F81, 0xE3E0,
+	0x4F83, 0xCAC9, 0x4F84, 0xF2E9, 0x4F86, 0xD5CE, 0x4F88, 0xF6B6,	0x4F8A, 0xCEC2, 0x4F8B, 0xD6C7, 0x4F8D, 0xE3B4, 0x4F8F, 0xF1AD,
+	0x4F91, 0xEAE2, 0x4F96, 0xD7C2, 0x4F98, 0xF3A7, 0x4F9B, 0xCDEA,	0x4F9D, 0xEBEE, 0x4FAE, 0xD9B2, 0x4FAF, 0xFDA5, 0x4FB5, 0xF6D5,
+	0x4FB6, 0xD5E2, 0x4FBF, 0xF8B5, 0x4FC2, 0xCCF5, 0x4FC3, 0xF5B5,	0x4FC4, 0xE4AD, 0x4FC9, 0xE7EB, 0x4FCA, 0xF1D5, 0x4FCE, 0xF0BB,
+	0x4FD1, 0xE9B5, 0x4FD3, 0xCCC9, 0x4FD4, 0xFAD5, 0x4FD7, 0xE1D4,	0x4FDA, 0xD7D6, 0x4FDD, 0xDCC1, 0x4FDF, 0xDEC6, 0x4FE0, 0xFAEF,
+	0x4FE1, 0xE3E1, 0x4FEE, 0xE1F3, 0x4FEF, 0xDCF6, 0x4FF1, 0xCEFC,	0x4FF3, 0xDBC4, 0x4FF5, 0xF8F1, 0x4FF8, 0xDCE4, 0x4FFA, 0xE5EF,
+	0x5002, 0xDCB1, 0x5006, 0xD5D6, 0x5009, 0xF3DA, 0x500B, 0xCBC1,	0x500D, 0xDBC3, 0x5011, 0xD9FA, 0x5012, 0xD3EE, 0x5016, 0xFAB8,
+	0x5019, 0xFDA6, 0x501A, 0xEBEF, 0x501C, 0xF4A6, 0x501E, 0xCCCA,	0x501F, 0xF3A8, 0x5021, 0xF3DB, 0x5023, 0xDBA7, 0x5024, 0xF6B7,
+	0x5026, 0xCFE6, 0x5027, 0xF0F2, 0x5028, 0xCBDA, 0x502A, 0xE7D2,	0x502B, 0xD7C3, 0x502C, 0xF6F0, 0x502D, 0xE8DE, 0x503B, 0xE5A6,
+	0x5043, 0xE5E7, 0x5047, 0xCAA3, 0x5048, 0xCCA7, 0x5049, 0xEAC9,	0x504F, 0xF8B6, 0x5055, 0xFAA5, 0x505A, 0xF1AE, 0x505C, 0xEFCE,
+	0x5065, 0xCBED, 0x5074, 0xF6B0, 0x5075, 0xEFCF, 0x5076, 0xE9CF,	0x5078, 0xF7DE, 0x5080, 0xCED3, 0x5085, 0xDCF7, 0x508D, 0xDBA8,
+	0x5091, 0xCBF8, 0x5098, 0xDFA1, 0x5099, 0xDDE1, 0x50AC, 0xF5CA,	0x50AD, 0xE9B6, 0x50B2, 0xE7EC, 0x50B3, 0xEEEE, 0x50B5, 0xF3F0,
+	0x50B7, 0xDFBF, 0x50BE, 0xCCCB, 0x50C5, 0xD0C1, 0x50C9, 0xF4D2,	0x50CA, 0xE0BA, 0x50CF, 0xDFC0, 0x50D1, 0xCEE0, 0x50D5, 0xDCD2,
+	0x50D6, 0xFDEA, 0x50DA, 0xD6F6, 0x50DE, 0xEACA, 0x50E5, 0xE8E9,	0x50E7, 0xE3AC, 0x50ED, 0xF3D0, 0x50F9, 0xCAA4, 0x50FB, 0xDBF8,
+	0x50FF, 0xDEC7, 0x5100, 0xEBF0, 0x5101, 0xF1D6, 0x5104, 0xE5E2,	0x5106, 0xCCCC, 0x5109, 0xCBFB, 0x5112, 0xEAE3, 0x511F, 0xDFC1,
+	0x5121, 0xD6ED, 0x512A, 0xE9D0, 0x5132, 0xEEB9, 0x5137, 0xD5E3,	0x513A, 0xD1D3, 0x513C, 0xE5F0, 0x5140, 0xE8B4, 0x5141, 0xEBC3,
+	0x5143, 0xEAAA, 0x5144, 0xFAFC, 0x5145, 0xF5F6, 0x5146, 0xF0BC,	0x5147, 0xFDD4, 0x5148, 0xE0BB, 0x5149, 0xCEC3, 0x514B, 0xD0BA,
+	0x514C, 0xF7BA, 0x514D, 0xD8F3, 0x514E, 0xF7CD, 0x5152, 0xE4AE,	0x515C, 0xD4DF, 0x5162, 0xD0E7, 0x5165, 0xECFD, 0x5167, 0xD2AE,
+	0x5168, 0xEEEF, 0x5169, 0xD5D7, 0x516A, 0xEAE4, 0x516B, 0xF8A2,	0x516C, 0xCDEB, 0x516D, 0xD7BF, 0x516E, 0xFBB1, 0x5171, 0xCDEC,
+	0x5175, 0xDCB2, 0x5176, 0xD0EC, 0x5177, 0xCEFD, 0x5178, 0xEEF0,	0x517C, 0xCCC2, 0x5180, 0xD0ED, 0x5186, 0xE5F7, 0x518A, 0xF3FC,
+	0x518D, 0xEEA2, 0x5192, 0xD9B3, 0x5195, 0xD8F4, 0x5197, 0xE9B7,	0x51A0, 0xCEAE, 0x51A5, 0xD9A2, 0x51AA, 0xD8F1, 0x51AC, 0xD4CF,
+	0x51B6, 0xE5A7, 0x51B7, 0xD5D2, 0x51BD, 0xD6A9, 0x51C4, 0xF4A2,	0x51C6, 0xF1D7, 0x51C9, 0xD5D8, 0x51CB, 0xF0BD, 0x51CC, 0xD7D0,
+	0x51CD, 0xD4D0, 0x51DC, 0xD7CF, 0x51DD, 0xEBEA, 0x51DE, 0xFDEB,	0x51E1, 0xDBED, 0x51F0, 0xFCC5, 0x51F1, 0xCBC2, 0x51F6, 0xFDD5,
+	0x51F8, 0xF4C8, 0x51F9, 0xE8EA, 0x51FA, 0xF5F3, 0x51FD, 0xF9DE,	0x5200, 0xD3EF, 0x5203, 0xECD3, 0x5206, 0xDDC2, 0x5207, 0xEFB7,
+	0x5208, 0xE7D4, 0x520A, 0xCACA, 0x520E, 0xD9FB, 0x5211, 0xFAFD,	0x5217, 0xD6AA, 0x521D, 0xF4F8, 0x5224, 0xF7F7, 0x5225, 0xDCAC,
+	0x5229, 0xD7D7, 0x522A, 0xDFA2, 0x522E, 0xCEBE, 0x5230, 0xD3F0,	0x5236, 0xF0A4, 0x5237, 0xE1EC, 0x5238, 0xCFE7, 0x5239, 0xF3CB,
+	0x523A, 0xEDA9, 0x523B, 0xCABE, 0x5243, 0xF4EF, 0x5247, 0xF6CE,	0x524A, 0xDEFB, 0x524B, 0xD0BB, 0x524C, 0xD5B7, 0x524D, 0xEEF1,
+	0x5254, 0xF4A8, 0x5256, 0xDCF8, 0x525B, 0xCBA7, 0x525D, 0xDACE,	0x5261, 0xE0E6, 0x5269, 0xEDA5, 0x526A, 0xEEF2, 0x526F, 0xDCF9,
+	0x5272, 0xF9DC, 0x5275, 0xF3DC, 0x527D, 0xF8F2, 0x527F, 0xF4F9,	0x5283, 0xFCF1, 0x5287, 0xD0BC, 0x5288, 0xDBF9, 0x5289, 0xD7B1,
+	0x528D, 0xCBFC, 0x5291, 0xF0A5, 0x5292, 0xCBFD, 0x529B, 0xD5F4,	0x529F, 0xCDED, 0x52A0, 0xCAA5, 0x52A3, 0xD6AB, 0x52A4, 0xD0C2,
+	0x52A9, 0xF0BE, 0x52AA, 0xD2BD, 0x52AB, 0xCCA4, 0x52BE, 0xFAB6,	0x52C1, 0xCCCD, 0x52C3, 0xDAFA, 0x52C5, 0xF6CF, 0x52C7, 0xE9B8,
+	0x52C9, 0xD8F5, 0x52CD, 0xCCCE, 0x52D2, 0xD7CD, 0x52D5, 0xD4D1,	0x52D6, 0xE9ED, 0x52D8, 0xCAEB, 0x52D9, 0xD9E2, 0x52DB, 0xFDB2,
+	0x52DD, 0xE3AD, 0x52DE, 0xD6CC, 0x52DF, 0xD9B4, 0x52E2, 0xE1A7,	0x52E3, 0xEED3, 0x52E4, 0xD0C3, 0x52F3, 0xFDB3, 0x52F5, 0xD5E4,
+	0x52F8, 0xCFE8, 0x52FA, 0xEDC3, 0x52FB, 0xD0B2, 0x52FE, 0xCEFE,	0x52FF, 0xDAA8, 0x5305, 0xF8D0, 0x5308, 0xFDD6, 0x530D, 0xF8D1,
+	0x530F, 0xF8D2, 0x5310, 0xDCD3, 0x5315, 0xDDE2, 0x5316, 0xFBF9,	0x5317, 0xDDC1, 0x5319, 0xE3B5, 0x5320, 0xEDDD, 0x5321, 0xCEC4,
+	0x5323, 0xCBA1, 0x532A, 0xDDE3, 0x532F, 0xFCDD, 0x5339, 0xF9AF,	0x533F, 0xD2FB, 0x5340, 0xCFA1, 0x5341, 0xE4A8, 0x5343, 0xF4B6,
+	0x5344, 0xECFE, 0x5347, 0xE3AE, 0x5348, 0xE7ED, 0x5349, 0xFDC1,	0x534A, 0xDAE2, 0x534D, 0xD8B3, 0x5351, 0xDDE4, 0x5352, 0xF0EF,
+	0x5353, 0xF6F1, 0x5354, 0xFAF0, 0x5357, 0xD1F5, 0x535A, 0xDACF,	0x535C, 0xDCD4, 0x535E, 0xDCA6, 0x5360, 0xEFBF, 0x5366, 0xCECF,
+	0x5368, 0xE0D9, 0x536F, 0xD9D6, 0x5370, 0xECD4, 0x5371, 0xEACB,	0x5374, 0xCABF, 0x5375, 0xD5B0, 0x5377, 0xCFE9, 0x537D, 0xF1ED,
+	0x537F, 0xCCCF, 0x5384, 0xE4F8, 0x5393, 0xE4ED, 0x5398, 0xD7D8,	0x539A, 0xFDA7, 0x539F, 0xEAAB, 0x53A0, 0xF6B2, 0x53A5, 0xCFF0,
+	0x53A6, 0xF9BD, 0x53AD, 0xE6F4, 0x53BB, 0xCBDB, 0x53C3, 0xF3D1,	0x53C8, 0xE9D1, 0x53C9, 0xF3A9, 0x53CA, 0xD0E0, 0x53CB, 0xE9D2,
+	0x53CD, 0xDAE3, 0x53D4, 0xE2D2, 0x53D6, 0xF6A2, 0x53D7, 0xE1F4,	0x53DB, 0xDAE4, 0x53E1, 0xE7D5, 0x53E2, 0xF5BF, 0x53E3, 0xCFA2,
+	0x53E4, 0xCDAF, 0x53E5, 0xCFA3, 0x53E9, 0xCDB0, 0x53EA, 0xF1FE,	0x53EB, 0xD0A3, 0x53EC, 0xE1AF, 0x53ED, 0xF8A3, 0x53EF, 0xCAA6,
+	0x53F0, 0xF7BB, 0x53F1, 0xF2EA, 0x53F2, 0xDEC8, 0x53F3, 0xE9D3,	0x53F8, 0xDEC9, 0x5403, 0xFDDE, 0x5404, 0xCAC0, 0x5408, 0xF9EA,
+	0x5409, 0xD1CE, 0x540A, 0xEED4, 0x540C, 0xD4D2, 0x540D, 0xD9A3,	0x540E, 0xFDA8, 0x540F, 0xD7D9, 0x5410, 0xF7CE, 0x5411, 0xFABE,
+	0x541B, 0xCFD6, 0x541D, 0xD7F0, 0x541F, 0xEBE1, 0x5420, 0xF8C5,	0x5426, 0xDCFA, 0x5429, 0xDDC3, 0x542B, 0xF9DF, 0x5433, 0xE7EF,
+	0x5438, 0xFDE5, 0x5439, 0xF6A3, 0x543B, 0xD9FC, 0x543C, 0xFDA9,	0x543E, 0xE7EE, 0x5442, 0xD5E5, 0x5448, 0xEFD0, 0x544A, 0xCDB1,
+	0x5451, 0xF7A2, 0x5468, 0xF1B2, 0x546A, 0xF1B1, 0x5471, 0xCDB2,	0x5473, 0xDAAB, 0x5475, 0xCAA7, 0x547B, 0xE3E2, 0x547C, 0xFBBC,
+	0x547D, 0xD9A4, 0x5480, 0xEEBA, 0x5486, 0xF8D3, 0x548C, 0xFBFA,	0x548E, 0xCFA4, 0x5490, 0xDCFB, 0x54A4, 0xF6E3, 0x54A8, 0xEDAA,
+	0x54AB, 0xF2A1, 0x54AC, 0xCEE1, 0x54B3, 0xFAA6, 0x54B8, 0xF9E0,	0x54BD, 0xECD6, 0x54C0, 0xE4EE, 0x54C1, 0xF9A1, 0x54C4, 0xFBEF,
+	0x54C8, 0xF9EB, 0x54C9, 0xEEA3, 0x54E1, 0xEAAC, 0x54E5, 0xCAA8,	0x54E8, 0xF4FA, 0x54ED, 0xCDD6, 0x54EE, 0xFCF6, 0x54F2, 0xF4C9,
+	0x54FA, 0xF8D4, 0x5504, 0xF8A6, 0x5506, 0xDECA, 0x5507, 0xF2C6,	0x550E, 0xD7DA, 0x5510, 0xD3D0, 0x551C, 0xD8C5, 0x552F, 0xEAE6,
+	0x5531, 0xF3DD, 0x5535, 0xE4DA, 0x553E, 0xF6E4, 0x5544, 0xF6F2,	0x5546, 0xDFC2, 0x554F, 0xD9FD, 0x5553, 0xCCF6, 0x5556, 0xD3BA,
+	0x555E, 0xE4AF, 0x5563, 0xF9E1, 0x557C, 0xF0A6, 0x5580, 0xCBD3,	0x5584, 0xE0BC, 0x5586, 0xF4CA, 0x5587, 0xD4FA, 0x5589, 0xFDAA,
+	0x558A, 0xF9E2, 0x5598, 0xF4B7, 0x5599, 0xFDC2, 0x559A, 0xFCB0,	0x559C, 0xFDEC, 0x559D, 0xCAE2, 0x55A7, 0xFDBD, 0x55A9, 0xEAE7,
+	0x55AA, 0xDFC3, 0x55AB, 0xD1D2, 0x55AC, 0xCEE2, 0x55AE, 0xD3A4,	0x55C5, 0xFDAB, 0x55C7, 0xDFE0, 0x55D4, 0xF2C7, 0x55DA, 0xE7F0,
+	0x55DC, 0xD0EE, 0x55DF, 0xF3AA, 0x55E3, 0xDECB, 0x55E4, 0xF6B8,	0x55FD, 0xE1F5, 0x55FE, 0xF1B3, 0x5606, 0xF7A3, 0x5609, 0xCAA9,
+	0x5614, 0xCFA5, 0x5617, 0xDFC4, 0x562F, 0xE1B0, 0x5632, 0xF0BF,	0x5634, 0xF6A4, 0x5636, 0xE3B6, 0x5653, 0xFAC6, 0x5668, 0xD0EF,
+	0x566B, 0xFDED, 0x5674, 0xDDC4, 0x5686, 0xFCF7, 0x56A5, 0xE6BF,	0x56AC, 0xDEAD, 0x56AE, 0xFABF, 0x56B4, 0xE5F1, 0x56BC, 0xEDC4,
+	0x56CA, 0xD2A5, 0x56CD, 0xFDEE, 0x56D1, 0xF5B6, 0x56DA, 0xE1F6,	0x56DB, 0xDECC, 0x56DE, 0xFCDE, 0x56E0, 0xECD7, 0x56F0, 0xCDDD,
+	0x56F9, 0xD6B7, 0x56FA, 0xCDB3, 0x5703, 0xF8D5, 0x5704, 0xE5D8,	0x5708, 0xCFEA, 0x570B, 0xCFD0, 0x570D, 0xEACC, 0x5712, 0xEAAE,
+	0x5713, 0xEAAD, 0x5716, 0xD3F1, 0x5718, 0xD3A5, 0x571F, 0xF7CF,	0x5728, 0xEEA4, 0x572D, 0xD0A4, 0x5730, 0xF2A2, 0x573B, 0xD0F0,
+	0x5740, 0xF2A3, 0x5742, 0xF7F8, 0x5747, 0xD0B3, 0x574A, 0xDBA9,	0x574D, 0xD3BB, 0x574E, 0xCAEC, 0x5750, 0xF1A6, 0x5751, 0xCBD5,
+	0x5761, 0xF7E7, 0x5764, 0xCDDE, 0x5766, 0xF7A4, 0x576A, 0xF8C0,	0x576E, 0xD3DD, 0x5770, 0xCCD0, 0x5775, 0xCFA6, 0x577C, 0xF6F3,
+	0x5782, 0xE1F7, 0x5788, 0xD3DC, 0x578B, 0xFAFE, 0x5793, 0xFAA7,	0x57A0, 0xEBD9, 0x57A2, 0xCFA7, 0x57A3, 0xEAAF, 0x57C3, 0xE4EF,
+	0x57C7, 0xE9B9, 0x57C8, 0xF1D8, 0x57CB, 0xD8D8, 0x57CE, 0xE0F2,	0x57DF, 0xE6B4, 0x57E0, 0xDCFC, 0x57F0, 0xF3F1, 0x57F4, 0xE3D0,
+	0x57F7, 0xF2FB, 0x57F9, 0xDBC6, 0x57FA, 0xD0F1, 0x57FC, 0xD0F2,	0x5800, 0xCFDC, 0x5802, 0xD3D1, 0x5805, 0xCCB1, 0x5806, 0xF7D8,
+	0x5808, 0xCBA8, 0x5809, 0xEBBC, 0x580A, 0xE4BE, 0x581E, 0xF4DC,	0x5821, 0xDCC2, 0x5824, 0xF0A7, 0x5827, 0xE6C0, 0x582A, 0xCAED,
+	0x582F, 0xE8EB, 0x5830, 0xE5E8, 0x5831, 0xDCC3, 0x5834, 0xEDDE,	0x5835, 0xD3F2, 0x583A, 0xCCF7, 0x584A, 0xCED4, 0x584B, 0xE7AB,
+	0x584F, 0xCBC3, 0x5851, 0xE1B1, 0x5854, 0xF7B2, 0x5857, 0xD3F3,	0x5858, 0xD3D2, 0x585A, 0xF5C0, 0x585E, 0xDFDD, 0x5861, 0xEEF3,
+	0x5862, 0xE7F1, 0x5864, 0xFDB4, 0x5875, 0xF2C8, 0x5879, 0xF3D2,	0x587C, 0xEEF4, 0x587E, 0xE2D3, 0x5883, 0xCCD1, 0x5885, 0xDFEA,
+	0x5889, 0xE9BA, 0x5893, 0xD9D7, 0x589C, 0xF5CD, 0x589E, 0xF1F2,	0x589F, 0xFAC7, 0x58A8, 0xD9F8, 0x58A9, 0xD4C2, 0x58AE, 0xF6E5,
+	0x58B3, 0xDDC5, 0x58BA, 0xE7F2, 0x58BB, 0xEDDF, 0x58BE, 0xCACB,	0x58C1, 0xDBFA, 0x58C5, 0xE8B5, 0x58C7, 0xD3A6, 0x58CE, 0xFDB5,
+	0x58D1, 0xF9C9, 0x58D3, 0xE4E2, 0x58D5, 0xFBBD, 0x58D8, 0xD7A4,	0x58D9, 0xCEC5, 0x58DE, 0xCED5, 0x58DF, 0xD6E6, 0x58E4, 0xE5BD,
+	0x58EB, 0xDECD, 0x58EC, 0xECF3, 0x58EF, 0xEDE0, 0x58F9, 0xECEC,	0x58FA, 0xFBBE, 0x58FB, 0xDFEB, 0x58FD, 0xE1F8, 0x590F, 0xF9BE,
+	0x5914, 0xD0F3, 0x5915, 0xE0AA, 0x5916, 0xE8E2, 0x5919, 0xE2D4,	0x591A, 0xD2FD, 0x591C, 0xE5A8, 0x5922, 0xD9D3, 0x5927, 0xD3DE,
+	0x5929, 0xF4B8, 0x592A, 0xF7BC, 0x592B, 0xDCFD, 0x592D, 0xE8EC,	0x592E, 0xE4E7, 0x5931, 0xE3F7, 0x5937, 0xECA8, 0x593E, 0xFAF1,
+	0x5944, 0xE5F2, 0x5947, 0xD0F4, 0x5948, 0xD2AF, 0x5949, 0xDCE5,	0x594E, 0xD0A5, 0x594F, 0xF1B4, 0x5950, 0xFCB1, 0x5951, 0xCCF8,
+	0x5954, 0xDDC6, 0x5955, 0xFAD1, 0x5957, 0xF7DF, 0x595A, 0xFAA8,	0x5960, 0xEEF5, 0x5962, 0xDECE, 0x5967, 0xE7F3, 0x596A, 0xF7AC,
+	0x596B, 0xEBC4, 0x596C, 0xEDE1, 0x596D, 0xE0AB, 0x596E, 0xDDC7,	0x5973, 0xD2B3, 0x5974, 0xD2BF, 0x5978, 0xCACC, 0x597D, 0xFBBF,
+	0x5982, 0xE5FD, 0x5983, 0xDDE5, 0x5984, 0xD8CD, 0x598A, 0xECF4,	0x5993, 0xD0F5, 0x5996, 0xE8ED, 0x5997, 0xD0D2, 0x5999, 0xD9D8,
+	0x59A5, 0xF6E6, 0x59A8, 0xDBAA, 0x59AC, 0xF7E0, 0x59B9, 0xD8D9,	0x59BB, 0xF4A3, 0x59BE, 0xF4DD, 0x59C3, 0xEFD1, 0x59C6, 0xD9B5,
+	0x59C9, 0xEDAB, 0x59CB, 0xE3B7, 0x59D0, 0xEEBB, 0x59D1, 0xCDB4,	0x59D3, 0xE0F3, 0x59D4, 0xEACD, 0x59D9, 0xECF5, 0x59DA, 0xE8EE,
+	0x59DC, 0xCBA9, 0x59DD, 0xF1AF, 0x59E6, 0xCACD, 0x59E8, 0xECA9,	0x59EA, 0xF2EB, 0x59EC, 0xFDEF, 0x59EE, 0xF9F3, 0x59F8, 0xE6C1,
+	0x59FB, 0xECD8, 0x59FF, 0xEDAC, 0x5A01, 0xEACE, 0x5A03, 0xE8DF,	0x5A11, 0xDECF, 0x5A18, 0xD2A6, 0x5A1B, 0xE7F4, 0x5A1C, 0xD1D6,
+	0x5A1F, 0xE6C2, 0x5A20, 0xE3E3, 0x5A25, 0xE4B0, 0x5A29, 0xD8B4,	0x5A36, 0xF6A5, 0x5A3C, 0xF3DE, 0x5A41, 0xD7A5, 0x5A46, 0xF7E8,
+	0x5A49, 0xE8C6, 0x5A5A, 0xFBE6, 0x5A62, 0xDDE6, 0x5A66, 0xDCFE,	0x5A92, 0xD8DA, 0x5A9A, 0xDAAC, 0x5A9B, 0xEAB0, 0x5AA4, 0xE3B8,
+	0x5AC1, 0xCAAA, 0x5AC2, 0xE1F9, 0x5AC4, 0xEAB1, 0x5AC9, 0xF2EC,	0x5ACC, 0xFAEE, 0x5AE1, 0xEED5, 0x5AE6, 0xF9F4, 0x5AE9, 0xD2EC,
+	0x5B05, 0xFBFB, 0x5B09, 0xFDF0, 0x5B0B, 0xE0BD, 0x5B0C, 0xCEE3,	0x5B16, 0xF8C6, 0x5B2A, 0xDEAE, 0x5B40, 0xDFC5, 0x5B43, 0xE5BE,
+	0x5B50, 0xEDAD, 0x5B51, 0xFAEA, 0x5B54, 0xCDEE, 0x5B55, 0xEDA6,	0x5B57, 0xEDAE, 0x5B58, 0xF0ED, 0x5B5A, 0xDDA1, 0x5B5C, 0xEDAF,
+	0x5B5D, 0xFCF8, 0x5B5F, 0xD8EB, 0x5B63, 0xCCF9, 0x5B64, 0xCDB5,	0x5B69, 0xFAA9, 0x5B6B, 0xE1DD, 0x5B70, 0xE2D5, 0x5B71, 0xEDCF,
+	0x5B75, 0xDDA2, 0x5B78, 0xF9CA, 0x5B7A, 0xEAE8, 0x5B7C, 0xE5ED,	0x5B85, 0xD3EB, 0x5B87, 0xE9D4, 0x5B88, 0xE1FA, 0x5B89, 0xE4CC,
+	0x5B8B, 0xE1E4, 0x5B8C, 0xE8C7, 0x5B8F, 0xCEDB, 0x5B93, 0xDCD5,	0x5B95, 0xF7B5, 0x5B96, 0xFCF3, 0x5B97, 0xF0F3, 0x5B98, 0xCEAF,
+	0x5B99, 0xF1B5, 0x5B9A, 0xEFD2, 0x5B9B, 0xE8C8, 0x5B9C, 0xEBF1,	0x5BA2, 0xCBD4, 0x5BA3, 0xE0BE, 0x5BA4, 0xE3F8, 0x5BA5, 0xEAE9,
+	0x5BA6, 0xFCB2, 0x5BAC, 0xE0F4, 0x5BAE, 0xCFE0, 0x5BB0, 0xEEA5,	0x5BB3, 0xFAAA, 0x5BB4, 0xE6C3, 0x5BB5, 0xE1B2, 0x5BB6, 0xCAAB,
+	0x5BB8, 0xE3E4, 0x5BB9, 0xE9BB, 0x5BBF, 0xE2D6, 0x5BC0, 0xF3F2,	0x5BC2, 0xEED6, 0x5BC3, 0xEAB2, 0x5BC4, 0xD0F6, 0x5BC5, 0xECD9,
+	0x5BC6, 0xDACB, 0x5BC7, 0xCFA8, 0x5BCC, 0xDDA3, 0x5BD0, 0xD8DB,	0x5BD2, 0xF9CE, 0x5BD3, 0xE9D5, 0x5BD4, 0xE3D1, 0x5BD7, 0xD2BC,
+	0x5BDE, 0xD8AC, 0x5BDF, 0xF3CC, 0x5BE1, 0xCDFB, 0x5BE2, 0xF6D6,	0x5BE4, 0xE7F5, 0x5BE5, 0xE8EF, 0x5BE6, 0xE3F9, 0x5BE7, 0xD2BB,
+	0x5BE8, 0xF3F3, 0x5BE9, 0xE3FB, 0x5BEB, 0xDED0, 0x5BEC, 0xCEB0,	0x5BEE, 0xD6F7, 0x5BEF, 0xF1D9, 0x5BF5, 0xF5C1, 0x5BF6, 0xDCC4,
+	0x5BF8, 0xF5BB, 0x5BFA, 0xDED1, 0x5C01, 0xDCE6, 0x5C04, 0xDED2,	0x5C07, 0xEDE2, 0x5C08, 0xEEF6, 0x5C09, 0xEACF, 0x5C0A, 0xF0EE,
+	0x5C0B, 0xE3FC, 0x5C0D, 0xD3DF, 0x5C0E, 0xD3F4, 0x5C0F, 0xE1B3,	0x5C11, 0xE1B4, 0x5C16, 0xF4D3, 0x5C19, 0xDFC6, 0x5C24, 0xE9D6,
+	0x5C28, 0xDBAB, 0x5C31, 0xF6A6, 0x5C38, 0xE3B9, 0x5C39, 0xEBC5,	0x5C3A, 0xF4A9, 0x5C3B, 0xCDB6, 0x5C3C, 0xD2F9, 0x5C3E, 0xDAAD,
+	0x5C3F, 0xD2E3, 0x5C40, 0xCFD1, 0x5C45, 0xCBDC, 0x5C46, 0xCCFA,	0x5C48, 0xCFDD, 0x5C4B, 0xE8A9, 0x5C4D, 0xE3BB, 0x5C4E, 0xE3BA,
+	0x5C51, 0xE0DA, 0x5C55, 0xEEF7, 0x5C5B, 0xDCB3, 0x5C60, 0xD3F5,	0x5C62, 0xD7A6, 0x5C64, 0xF6B5, 0x5C65, 0xD7DB, 0x5C6C, 0xE1D5,
+	0x5C6F, 0xD4EA, 0x5C71, 0xDFA3, 0x5C79, 0xFDDF, 0x5C90, 0xD0F7,	0x5C91, 0xEDD4, 0x5CA1, 0xCBAA, 0x5CA9, 0xE4DB, 0x5CAB, 0xE1FB,
+	0x5CAC, 0xCBA2, 0x5CB1, 0xD3E0, 0x5CB3, 0xE4BF, 0x5CB5, 0xFBC0,	0x5CB7, 0xDABE, 0x5CB8, 0xE4CD, 0x5CBA, 0xD6B9, 0x5CBE, 0xEFC0,
+	0x5CC0, 0xE1FC, 0x5CD9, 0xF6B9, 0x5CE0, 0xDFC7, 0x5CE8, 0xE4B1,	0x5CEF, 0xDCE7, 0x5CF0, 0xDCE8, 0x5CF4, 0xFAD6, 0x5CF6, 0xD3F6,
+	0x5CFB, 0xF1DA, 0x5CFD, 0xFAF2, 0x5D07, 0xE2FD, 0x5D0D, 0xD5CF,	0x5D0E, 0xD0F8, 0x5D11, 0xCDDF, 0x5D14, 0xF5CB, 0x5D16, 0xE4F0,
+	0x5D17, 0xCBAB, 0x5D19, 0xD7C4, 0x5D27, 0xE2FE, 0x5D29, 0xDDDA,	0x5D4B, 0xDAAE, 0x5D4C, 0xCAEE, 0x5D50, 0xD5B9, 0x5D69, 0xE3A1,
+	0x5D6C, 0xE8E3, 0x5D6F, 0xF3AB, 0x5D87, 0xCFA9, 0x5D8B, 0xD3F7,	0x5D9D, 0xD4F1, 0x5DA0, 0xCEE4, 0x5DA2, 0xE8F2, 0x5DAA, 0xE5F5,
+	0x5DB8, 0xE7AE, 0x5DBA, 0xD6BA, 0x5DBC, 0xDFEC, 0x5DBD, 0xE4C0,	0x5DCD, 0xE8E4, 0x5DD2, 0xD8B5, 0x5DD6, 0xE4DC, 0x5DDD, 0xF4B9,
+	0x5DDE, 0xF1B6, 0x5DE1, 0xE2DE, 0x5DE2, 0xE1B5, 0x5DE5, 0xCDEF,	0x5DE6, 0xF1A7, 0x5DE7, 0xCEE5, 0x5DE8, 0xCBDD, 0x5DEB, 0xD9E3,
+	0x5DEE, 0xF3AC, 0x5DF1, 0xD0F9, 0x5DF2, 0xECAB, 0x5DF3, 0xDED3,	0x5DF4, 0xF7E9, 0x5DF7, 0xF9F5, 0x5DFD, 0xE1DE, 0x5DFE, 0xCBEE,
+	0x5E02, 0xE3BC, 0x5E03, 0xF8D6, 0x5E06, 0xDBEE, 0x5E0C, 0xFDF1,	0x5E11, 0xF7B6, 0x5E16, 0xF4DE, 0x5E19, 0xF2ED, 0x5E1B, 0xDBD9,
+	0x5E1D, 0xF0A8, 0x5E25, 0xE1FD, 0x5E2B, 0xDED4, 0x5E2D, 0xE0AC,	0x5E33, 0xEDE3, 0x5E36, 0xD3E1, 0x5E38, 0xDFC8, 0x5E3D, 0xD9B6,
+	0x5E3F, 0xFDAC, 0x5E40, 0xEFD3, 0x5E44, 0xE4C1, 0x5E45, 0xF8EB,	0x5E47, 0xDBAC, 0x5E4C, 0xFCC6, 0x5E55, 0xD8AD, 0x5E5F, 0xF6BA,
+	0x5E61, 0xDBDF, 0x5E62, 0xD3D3, 0x5E63, 0xF8C7, 0x5E72, 0xCACE,	0x5E73, 0xF8C1, 0x5E74, 0xD2B4, 0x5E77, 0xDCB4, 0x5E78, 0xFAB9,
+	0x5E79, 0xCACF, 0x5E7B, 0xFCB3, 0x5E7C, 0xEAEA, 0x5E7D, 0xEAEB,	0x5E7E, 0xD0FA, 0x5E84, 0xEDE4, 0x5E87, 0xDDE7, 0x5E8A, 0xDFC9,
+	0x5E8F, 0xDFED, 0x5E95, 0xEEBC, 0x5E97, 0xEFC1, 0x5E9A, 0xCCD2,	0x5E9C, 0xDDA4, 0x5EA0, 0xDFCA, 0x5EA6, 0xD3F8, 0x5EA7, 0xF1A8,
+	0x5EAB, 0xCDB7, 0x5EAD, 0xEFD4, 0x5EB5, 0xE4DD, 0x5EB6, 0xDFEE,	0x5EB7, 0xCBAC, 0x5EB8, 0xE9BC, 0x5EBE, 0xEAEC, 0x5EC2, 0xDFCB,
+	0x5EC8, 0xF9BF, 0x5EC9, 0xD6AF, 0x5ECA, 0xD5C6, 0x5ED0, 0xCFAA,	0x5ED3, 0xCEA9, 0x5ED6, 0xD6F8, 0x5EDA, 0xF1B7, 0x5EDB, 0xEEF8,
+	0x5EDF, 0xD9D9, 0x5EE0, 0xF3DF, 0x5EE2, 0xF8C8, 0x5EE3, 0xCEC6,	0x5EEC, 0xD5E6, 0x5EF3, 0xF4E6, 0x5EF6, 0xE6C5, 0x5EF7, 0xEFD5,
+	0x5EFA, 0xCBEF, 0x5EFB, 0xFCDF, 0x5F01, 0xDCA7, 0x5F04, 0xD6E7,	0x5F0A, 0xF8C9, 0x5F0F, 0xE3D2, 0x5F11, 0xE3BD, 0x5F13, 0xCFE1,
+	0x5F14, 0xF0C0, 0x5F15, 0xECDA, 0x5F17, 0xDDD7, 0x5F18, 0xFBF0,	0x5F1B, 0xECAC, 0x5F1F, 0xF0A9, 0x5F26, 0xFAD7, 0x5F27, 0xFBC1,
+	0x5F29, 0xD2C0, 0x5F31, 0xE5B0, 0x5F35, 0xEDE5, 0x5F3A, 0xCBAD,	0x5F3C, 0xF9B0, 0x5F48, 0xF7A5, 0x5F4A, 0xCBAE, 0x5F4C, 0xDAAF,
+	0x5F4E, 0xD8B6, 0x5F56, 0xD3A7, 0x5F57, 0xFBB2, 0x5F59, 0xFDC4,	0x5F5B, 0xECAD, 0x5F62, 0xFBA1, 0x5F66, 0xE5E9, 0x5F67, 0xE9EE,
+	0x5F69, 0xF3F4, 0x5F6A, 0xF8F3, 0x5F6B, 0xF0C1, 0x5F6C, 0xDEAF,	0x5F6D, 0xF8B0, 0x5F70, 0xF3E0, 0x5F71, 0xE7AF, 0x5F77, 0xDBAD,
+	0x5F79, 0xE6B5, 0x5F7C, 0xF9A8, 0x5F7F, 0xDDD8, 0x5F80, 0xE8D9,	0x5F81, 0xEFD6, 0x5F85, 0xD3E2, 0x5F87, 0xE2DF, 0x5F8A, 0xFCE0,
+	0x5F8B, 0xD7C8, 0x5F8C, 0xFDAD, 0x5F90, 0xDFEF, 0x5F91, 0xCCD3,	0x5F92, 0xD3F9, 0x5F97, 0xD4F0, 0x5F98, 0xDBC7, 0x5F99, 0xDED5,
+	0x5F9E, 0xF0F4, 0x5FA0, 0xD5D0, 0x5FA1, 0xE5D9, 0x5FA8, 0xFCC7,	0x5FA9, 0xDCD6, 0x5FAA, 0xE2E0, 0x5FAE, 0xDAB0, 0x5FB5, 0xF3A3,
+	0x5FB7, 0xD3EC, 0x5FB9, 0xF4CB, 0x5FBD, 0xFDC5, 0x5FC3, 0xE3FD,	0x5FC5, 0xF9B1, 0x5FCC, 0xD0FB, 0x5FCD, 0xECDB, 0x5FD6, 0xF5BC,
+	0x5FD7, 0xF2A4, 0x5FD8, 0xD8CE, 0x5FD9, 0xD8CF, 0x5FE0, 0xF5F7,	0x5FEB, 0xF6E1, 0x5FF5, 0xD2B7, 0x5FFD, 0xFBEC, 0x5FFF, 0xDDC8,
+	0x600F, 0xE4E8, 0x6012, 0xD2C1, 0x6016, 0xF8D7, 0x601C, 0xD6BB,	0x601D, 0xDED6, 0x6020, 0xF7BD, 0x6021, 0xECAE, 0x6025, 0xD0E1,
+	0x6027, 0xE0F5, 0x6028, 0xEAB3, 0x602A, 0xCED6, 0x602F, 0xCCA5,	0x6041, 0xECF6, 0x6042, 0xE2E1, 0x6043, 0xE3BE, 0x604D, 0xFCC8,
+	0x6050, 0xCDF0, 0x6052, 0xF9F6, 0x6055, 0xDFF0, 0x6059, 0xE5BF,	0x605D, 0xCEBF, 0x6062, 0xFCE1, 0x6063, 0xEDB0, 0x6064, 0xFDD1,
+	0x6065, 0xF6BB, 0x6068, 0xF9CF, 0x6069, 0xEBDA, 0x606A, 0xCAC1,	0x606C, 0xD2B8, 0x606D, 0xCDF1, 0x606F, 0xE3D3, 0x6070, 0xFDE6,
+	0x6085, 0xE6ED, 0x6089, 0xE3FA, 0x608C, 0xF0AA, 0x608D, 0xF9D0,	0x6094, 0xFCE2, 0x6096, 0xF8A7, 0x609A, 0xE1E5, 0x609B, 0xEEF9,
+	0x609F, 0xE7F6, 0x60A0, 0xEAED, 0x60A3, 0xFCB4, 0x60A4, 0xF5C2,	0x60A7, 0xD7DC, 0x60B0, 0xF0F5, 0x60B2, 0xDDE8, 0x60B3, 0xD3ED,
+	0x60B4, 0xF5FC, 0x60B6, 0xDABF, 0x60B8, 0xCCFB, 0x60BC, 0xD3FA,	0x60BD, 0xF4A4, 0x60C5, 0xEFD7, 0x60C7, 0xD4C3, 0x60D1, 0xFBE3,
+	0x60DA, 0xFBED, 0x60DC, 0xE0AD, 0x60DF, 0xEAEE, 0x60E0, 0xFBB3,	0x60E1, 0xE4C2, 0x60F0, 0xF6E7, 0x60F1, 0xD2DD, 0x60F3, 0xDFCC,
+	0x60F6, 0xFCC9, 0x60F9, 0xE5A9, 0x60FA, 0xE0F6, 0x60FB, 0xF6B3,	0x6101, 0xE1FE, 0x6106, 0xCBF0, 0x6108, 0xEAEF, 0x6109, 0xEAF0,
+	0x610D, 0xDAC0, 0x610E, 0xF8B4, 0x610F, 0xEBF2, 0x6115, 0xE4C3,	0x611A, 0xE9D7, 0x611B, 0xE4F1, 0x611F, 0xCAEF, 0x6127, 0xCED7,
+	0x6130, 0xFCCA, 0x6134, 0xF3E1, 0x6137, 0xCBC4, 0x613C, 0xE3E5,	0x613E, 0xCBC5, 0x613F, 0xEAB4, 0x6142, 0xE9BD, 0x6144, 0xD7C9,
+	0x6147, 0xEBDB, 0x6148, 0xEDB1, 0x614A, 0xCCC3, 0x614B, 0xF7BE,	0x614C, 0xFCCB, 0x6153, 0xF8F4, 0x6155, 0xD9B7, 0x6158, 0xF3D3,
+	0x6159, 0xF3D4, 0x615D, 0xF7E4, 0x615F, 0xF7D1, 0x6162, 0xD8B7,	0x6163, 0xCEB1, 0x6164, 0xCAC2, 0x6167, 0xFBB4, 0x6168, 0xCBC6,
+	0x616B, 0xF0F6, 0x616E, 0xD5E7, 0x6170, 0xEAD0, 0x6176, 0xCCD4,	0x6177, 0xCBAF, 0x617D, 0xF4AA, 0x617E, 0xE9AF, 0x6181, 0xF5C3,
+	0x6182, 0xE9D8, 0x618A, 0xDDE9, 0x618E, 0xF1F3, 0x6190, 0xD5FB,	0x6191, 0xDEBB, 0x6194, 0xF4FB, 0x6198, 0xFDF3, 0x6199, 0xFDF2,
+	0x619A, 0xF7A6, 0x61A4, 0xDDC9, 0x61A7, 0xD4D3, 0x61A9, 0xCCA8,	0x61AB, 0xDAC1, 0x61AC, 0xCCD5, 0x61AE, 0xD9E4, 0x61B2, 0xFACA,
+	0x61B6, 0xE5E3, 0x61BA, 0xD3BC, 0x61BE, 0xCAF0, 0x61C3, 0xD0C4,	0x61C7, 0xCAD0, 0x61C8, 0xFAAB, 0x61C9, 0xEBEB, 0x61CA, 0xE7F8,
+	0x61CB, 0xD9E5, 0x61E6, 0xD1D7, 0x61F2, 0xF3A4, 0x61F6, 0xD4FB,	0x61F7, 0xFCE3, 0x61F8, 0xFAD8, 0x61FA, 0xF3D5, 0x61FC, 0xCFAB,
+	0x61FF, 0xEBF3, 0x6200, 0xD5FC, 0x6207, 0xD3D4, 0x6208, 0xCDFC,	0x620A, 0xD9E6, 0x620C, 0xE2F9, 0x620D, 0xE2A1, 0x620E, 0xEBD4,
+	0x6210, 0xE0F7, 0x6211, 0xE4B2, 0x6212, 0xCCFC, 0x6216, 0xFBE4,	0x621A, 0xF4AB, 0x621F, 0xD0BD, 0x6221, 0xCAF1, 0x622A, 0xEFB8,
+	0x622E, 0xD7C0, 0x6230, 0xEEFA, 0x6231, 0xFDF4, 0x6234, 0xD3E3,	0x6236, 0xFBC2, 0x623E, 0xD5E8, 0x623F, 0xDBAE, 0x6240, 0xE1B6,
+	0x6241, 0xF8B7, 0x6247, 0xE0BF, 0x6248, 0xFBC3, 0x6249, 0xDDEA,	0x624B, 0xE2A2, 0x624D, 0xEEA6, 0x6253, 0xF6E8, 0x6258, 0xF6F5,
+	0x626E, 0xDDCA, 0x6271, 0xD0E2, 0x6276, 0xDDA6, 0x6279, 0xDDEB,	0x627C, 0xE4F9, 0x627F, 0xE3AF, 0x6280, 0xD0FC, 0x6284, 0xF4FC,
+	0x6289, 0xCCBC, 0x628A, 0xF7EA, 0x6291, 0xE5E4, 0x6292, 0xDFF1,	0x6295, 0xF7E1, 0x6297, 0xF9F7, 0x6298, 0xEFB9, 0x629B, 0xF8D8,
+	0x62AB, 0xF9A9, 0x62B1, 0xF8D9, 0x62B5, 0xEEBD, 0x62B9, 0xD8C6,	0x62BC, 0xE4E3, 0x62BD, 0xF5CE, 0x62C2, 0xDDD9, 0x62C7, 0xD9E7,
+	0x62C8, 0xD2B9, 0x62C9, 0xD5C3, 0x62CC, 0xDAE5, 0x62CD, 0xDAD0,	0x62CF, 0xD1D9, 0x62D0, 0xCED8, 0x62D2, 0xCBDE, 0x62D3, 0xF4AC,
+	0x62D4, 0xDAFB, 0x62D6, 0xF6E9, 0x62D7, 0xE8F3, 0x62D8, 0xCFAC,	0x62D9, 0xF0F0, 0x62DB, 0xF4FD, 0x62DC, 0xDBC8, 0x62EC, 0xCEC0,
+	0x62ED, 0xE3D4, 0x62EE, 0xD1CF, 0x62EF, 0xF1F5, 0x62F1, 0xCDF2,	0x62F3, 0xCFEB, 0x62F7, 0xCDB8, 0x62FE, 0xE3A6, 0x62FF, 0xD1DA,
+	0x6301, 0xF2A5, 0x6307, 0xF2A6, 0x6309, 0xE4CE, 0x6311, 0xD3FB,	0x632B, 0xF1A9, 0x632F, 0xF2C9, 0x633A, 0xEFD8, 0x633B, 0xE6C9,
+	0x633D, 0xD8B8, 0x633E, 0xFAF3, 0x6349, 0xF3B5, 0x634C, 0xF8A4,	0x634F, 0xD1F3, 0x6350, 0xE6C8, 0x6355, 0xF8DA, 0x6367, 0xDCE9,
+	0x6368, 0xDED7, 0x636E, 0xCBDF, 0x6372, 0xCFEC, 0x6377, 0xF4DF,	0x637A, 0xD1F4, 0x637B, 0xD2BA, 0x637F, 0xDFF2, 0x6383, 0xE1B7,
+	0x6388, 0xE2A3, 0x6389, 0xD3FC, 0x638C, 0xEDE6, 0x6392, 0xDBC9,	0x6396, 0xE4FA, 0x6398, 0xCFDE, 0x639B, 0xCED0, 0x63A0, 0xD5D3,
+	0x63A1, 0xF3F5, 0x63A2, 0xF7AE, 0x63A5, 0xEFC8, 0x63A7, 0xCDF3,	0x63A8, 0xF5CF, 0x63A9, 0xE5F3, 0x63AA, 0xF0C2, 0x63C0, 0xCAD1,
+	0x63C4, 0xEAF1, 0x63C6, 0xD0A6, 0x63CF, 0xD9DA, 0x63D0, 0xF0AB,	0x63D6, 0xEBE7, 0x63DA, 0xE5C0, 0x63DB, 0xFCB5, 0x63E1, 0xE4C4,
+	0x63ED, 0xCCA9, 0x63EE, 0xFDC6, 0x63F4, 0xEAB5, 0x63F6, 0xE5AA,	0x63F7, 0xDFBA, 0x640D, 0xE1DF, 0x640F, 0xDAD1, 0x6414, 0xE1B8,
+	0x6416, 0xE8F4, 0x6417, 0xD3FD, 0x641C, 0xE2A4, 0x6422, 0xF2CA,	0x642C, 0xDAE6, 0x642D, 0xF7B3, 0x643A, 0xFDCD, 0x643E, 0xF3B6,
+	0x6458, 0xEED7, 0x6460, 0xF5C4, 0x6469, 0xD8A4, 0x646F, 0xF2A7,	0x6478, 0xD9B8, 0x6479, 0xD9B9, 0x647A, 0xEFC9, 0x6488, 0xD6CE,
+	0x6491, 0xF7CB, 0x6492, 0xDFAE, 0x6493, 0xE8F5, 0x649A, 0xD2B5,	0x649E, 0xD3D5, 0x64A4, 0xF4CC, 0x64A5, 0xDAFC, 0x64AB, 0xD9E8,
+	0x64AD, 0xF7EB, 0x64AE, 0xF5C9, 0x64B0, 0xF3BC, 0x64B2, 0xDAD2,	0x64BB, 0xD3B5, 0x64C1, 0xE8B6, 0x64C4, 0xD6CF, 0x64C5, 0xF4BA,
+	0x64C7, 0xF7C9, 0x64CA, 0xCCAA, 0x64CD, 0xF0C3, 0x64CE, 0xCCD6,	0x64D2, 0xD0D3, 0x64D4, 0xD3BD, 0x64D8, 0xDBFB, 0x64DA, 0xCBE0,
+	0x64E1, 0xD3E4, 0x64E2, 0xF6F7, 0x64E5, 0xD5BA, 0x64E6, 0xF3CD,	0x64E7, 0xCBE1, 0x64EC, 0xEBF4, 0x64F2, 0xF4AD, 0x64F4, 0xFCAA,
+	0x64FA, 0xF7EC, 0x64FE, 0xE8F6, 0x6500, 0xDAE7, 0x6504, 0xF7CC,	0x6518, 0xE5C1, 0x651D, 0xE0EE, 0x6523, 0xD5FD, 0x652A, 0xCEE6,
+	0x652B, 0xFCAB, 0x652C, 0xD5BB, 0x652F, 0xF2A8, 0x6536, 0xE2A5,	0x6537, 0xCDB9, 0x6538, 0xEAF2, 0x6539, 0xCBC7, 0x653B, 0xCDF4,
+	0x653E, 0xDBAF, 0x653F, 0xEFD9, 0x6545, 0xCDBA, 0x6548, 0xFCF9,	0x654D, 0xDFF3, 0x654E, 0xCEE7, 0x654F, 0xDAC2, 0x6551, 0xCFAD,
+	0x6556, 0xE7F9, 0x6557, 0xF8A8, 0x655E, 0xF3E2, 0x6562, 0xCAF2,	0x6563, 0xDFA4, 0x6566, 0xD4C4, 0x656C, 0xCCD7, 0x656D, 0xE5C2,
+	0x6572, 0xCDBB, 0x6574, 0xEFDA, 0x6575, 0xEED8, 0x6577, 0xDDA7,	0x6578, 0xE2A6, 0x657E, 0xE0C0, 0x6582, 0xD6B0, 0x6583, 0xF8CA,
+	0x6585, 0xFCFA, 0x6587, 0xD9FE, 0x658C, 0xDEB0, 0x6590, 0xDDEC,	0x6591, 0xDAE8, 0x6597, 0xD4E0, 0x6599, 0xD6F9, 0x659B, 0xCDD7,
+	0x659C, 0xDED8, 0x659F, 0xF2F8, 0x65A1, 0xE4D6, 0x65A4, 0xD0C5,	0x65A5, 0xF4AE, 0x65A7, 0xDDA8, 0x65AB, 0xEDC5, 0x65AC, 0xF3D6,
+	0x65AF, 0xDED9, 0x65B0, 0xE3E6, 0x65B7, 0xD3A8, 0x65B9, 0xDBB0,	0x65BC, 0xE5DA, 0x65BD, 0xE3BF, 0x65C1, 0xDBB1, 0x65C5, 0xD5E9,
+	0x65CB, 0xE0C1, 0x65CC, 0xEFDB, 0x65CF, 0xF0E9, 0x65D2, 0xD7B2,	0x65D7, 0xD0FD, 0x65E0, 0xD9E9, 0x65E3, 0xD0FE, 0x65E5, 0xECED,
+	0x65E6, 0xD3A9, 0x65E8, 0xF2A9, 0x65E9, 0xF0C4, 0x65EC, 0xE2E2,	0x65ED, 0xE9EF, 0x65F1, 0xF9D1, 0x65F4, 0xE9D9, 0x65FA, 0xE8DA,
+	0x65FB, 0xDAC3, 0x65FC, 0xDAC4, 0x65FD, 0xD4C5, 0x65FF, 0xE7FA,	0x6606, 0xCDE0, 0x6607, 0xE3B0, 0x6609, 0xDBB2, 0x660A, 0xFBC4,
+	0x660C, 0xF3E3, 0x660E, 0xD9A5, 0x660F, 0xFBE7, 0x6610, 0xDDCB,	0x6611, 0xD0D4, 0x6613, 0xE6B6, 0x6614, 0xE0AE, 0x6615, 0xFDDA,
+	0x661E, 0xDCB5, 0x661F, 0xE0F8, 0x6620, 0xE7B1, 0x6625, 0xF5F0,	0x6627, 0xD8DC, 0x6628, 0xEDC6, 0x662D, 0xE1B9, 0x662F, 0xE3C0,
+	0x6630, 0xF9C0, 0x6631, 0xE9F0, 0x6634, 0xD9DB, 0x6636, 0xF3E4,	0x663A, 0xDCB6, 0x663B, 0xE4E9, 0x6641, 0xF0C5, 0x6642, 0xE3C1,
+	0x6643, 0xFCCC, 0x6644, 0xFCCD, 0x6649, 0xF2CB, 0x664B, 0xF2CC,	0x664F, 0xE4CF, 0x6659, 0xF1DB, 0x665B, 0xFAD9, 0x665D, 0xF1B8,
+	0x665E, 0xFDF5, 0x665F, 0xE0F9, 0x6664, 0xE7FB, 0x6665, 0xFCB7,	0x6666, 0xFCE4, 0x6667, 0xFBC5, 0x6668, 0xE3E7, 0x6669, 0xD8B9,
+	0x666B, 0xF6F8, 0x666E, 0xDCC5, 0x666F, 0xCCD8, 0x6673, 0xE0AF,	0x6674, 0xF4E7, 0x6676, 0xEFDC, 0x6677, 0xCFFC, 0x6678, 0xEFDD,
+	0x667A, 0xF2AA, 0x6684, 0xFDBE, 0x6687, 0xCAAC, 0x6688, 0xFDBB,	0x6689, 0xFDC7, 0x668E, 0xE7B2, 0x6690, 0xEAD1, 0x6691, 0xDFF4,
+	0x6696, 0xD1EC, 0x6697, 0xE4DE, 0x6698, 0xE5C3, 0x669D, 0xD9A6,	0x66A0, 0xCDBC, 0x66A2, 0xF3E5, 0x66AB, 0xEDD5, 0x66AE, 0xD9BA,
+	0x66B2, 0xEDE7, 0x66B3, 0xFBB5, 0x66B4, 0xF8EC, 0x66B9, 0xE0E7,	0x66BB, 0xCCD9, 0x66BE, 0xD4C6, 0x66C4, 0xE7A5, 0x66C6, 0xD5F5,
+	0x66C7, 0xD3BE, 0x66C9, 0xFCFB, 0x66D6, 0xE4F2, 0x66D9, 0xDFF5,	0x66DC, 0xE8F8, 0x66DD, 0xF8ED, 0x66E0, 0xCEC7, 0x66E6, 0xFDF6,
+	0x66F0, 0xE8D8, 0x66F2, 0xCDD8, 0x66F3, 0xE7D6, 0x66F4, 0xCCDA,	0x66F7, 0xCAE3, 0x66F8, 0xDFF6, 0x66F9, 0xF0C7, 0x66FA, 0xF0C6,
+	0x66FC, 0xD8BA, 0x66FE, 0xF1F4, 0x66FF, 0xF4F0, 0x6700, 0xF5CC,	0x6703, 0xFCE5, 0x6708, 0xEAC5, 0x6709, 0xEAF3, 0x670B, 0xDDDB,
+	0x670D, 0xDCD7, 0x6714, 0xDEFD, 0x6715, 0xF2F9, 0x6717, 0xD5C7,	0x671B, 0xD8D0, 0x671D, 0xF0C8, 0x671E, 0xD1A1, 0x671F, 0xD1A2,
+	0x6726, 0xD9D4, 0x6727, 0xD6E8, 0x6728, 0xD9CA, 0x672A, 0xDAB1,	0x672B, 0xD8C7, 0x672C, 0xDCE2, 0x672D, 0xF3CE, 0x672E, 0xF5F4,
+	0x6731, 0xF1B9, 0x6734, 0xDAD3, 0x6736, 0xF6EA, 0x673A, 0xCFF5,	0x673D, 0xFDAE, 0x6746, 0xCAD2, 0x6749, 0xDFB4, 0x674E, 0xD7DD,
+	0x674F, 0xFABA, 0x6750, 0xEEA7, 0x6751, 0xF5BD, 0x6753, 0xF8F5,	0x6756, 0xEDE8, 0x675C, 0xD4E1, 0x675E, 0xD1A3, 0x675F, 0xE1D6,
+	0x676D, 0xF9F8, 0x676F, 0xDBCA, 0x6770, 0xCBF9, 0x6771, 0xD4D4,	0x6773, 0xD9DC, 0x6775, 0xEEBE, 0x6777, 0xF7ED, 0x677B, 0xD2EE,
+	0x677E, 0xE1E6, 0x677F, 0xF7F9, 0x6787, 0xDDED, 0x6789, 0xE8DB,	0x678B, 0xDBB3, 0x678F, 0xD1F7, 0x6790, 0xE0B0, 0x6793, 0xD4E2,
+	0x6795, 0xF6D7, 0x6797, 0xD7F9, 0x679A, 0xD8DD, 0x679C, 0xCDFD,	0x679D, 0xF2AB, 0x67AF, 0xCDBD, 0x67B0, 0xF8C2, 0x67B3, 0xF2AC,
+	0x67B6, 0xCAAD, 0x67B7, 0xCAAE, 0x67B8, 0xCFAE, 0x67BE, 0xE3C2,	0x67C4, 0xDCB7, 0x67CF, 0xDBDA, 0x67D0, 0xD9BB, 0x67D1, 0xCAF3,
+	0x67D2, 0xF6D3, 0x67D3, 0xE6F8, 0x67D4, 0xEAF5, 0x67DA, 0xEAF6,	0x67DD, 0xF6F9, 0x67E9, 0xCFAF, 0x67EC, 0xCAD3, 0x67EF, 0xCAAF,
+	0x67F0, 0xD2B0, 0x67F1, 0xF1BA, 0x67F3, 0xD7B3, 0x67F4, 0xE3C3,	0x67F5, 0xF3FD, 0x67F6, 0xDEDA, 0x67FB, 0xDEDB, 0x67FE, 0xEFDE,
+	0x6812, 0xE2E3, 0x6813, 0xEEFB, 0x6816, 0xDFF7, 0x6817, 0xD7CA,	0x6821, 0xCEE8, 0x6822, 0xDBDB, 0x682A, 0xF1BB, 0x682F, 0xE9F1,
+	0x6838, 0xFAB7, 0x6839, 0xD0C6, 0x683C, 0xCCAB, 0x683D, 0xEEA8,	0x6840, 0xCBFA, 0x6841, 0xF9F9, 0x6842, 0xCCFD, 0x6843, 0xD3FE,
+	0x6848, 0xE4D0, 0x684E, 0xF2EE, 0x6850, 0xD4D5, 0x6851, 0xDFCD,	0x6853, 0xFCB8, 0x6854, 0xD1D0, 0x686D, 0xF2CD, 0x6876, 0xF7D2,
+	0x687F, 0xCAD4, 0x6881, 0xD5D9, 0x6885, 0xD8DE, 0x688F, 0xCDD9,	0x6893, 0xEEA9, 0x6894, 0xF6BC, 0x6897, 0xCCDB, 0x689D, 0xF0C9,
+	0x689F, 0xFCFC, 0x68A1, 0xE8C9, 0x68A2, 0xF4FE, 0x68A7, 0xE7FC,	0x68A8, 0xD7DE, 0x68AD, 0xDEDC, 0x68AF, 0xF0AC, 0x68B0, 0xCCFE,
+	0x68B1, 0xCDE1, 0x68B3, 0xE1BA, 0x68B5, 0xDBEF, 0x68B6, 0xDAB2,	0x68C4, 0xD1A5, 0x68C5, 0xDCB8, 0x68C9, 0xD8F6, 0x68CB, 0xD1A4,
+	0x68CD, 0xCDE2, 0x68D2, 0xDCEA, 0x68D5, 0xF0F7, 0x68D7, 0xF0CA,	0x68D8, 0xD0BE, 0x68DA, 0xDDDC, 0x68DF, 0xD4D6, 0x68E0, 0xD3D6,
+	0x68E7, 0xEDD0, 0x68E8, 0xCDA1, 0x68EE, 0xDFB5, 0x68F2, 0xDFF8,	0x68F9, 0xD4A1, 0x68FA, 0xCEB2, 0x6900, 0xE8CA, 0x6905, 0xEBF5,
+	0x690D, 0xE3D5, 0x690E, 0xF5D0, 0x6912, 0xF5A1, 0x6927, 0xD9A7,	0x6930, 0xE5AB, 0x693D, 0xE6CB, 0x693F, 0xF5F1, 0x694A, 0xE5C5,
+	0x6953, 0xF9A3, 0x6954, 0xE0DB, 0x6955, 0xF6EB, 0x6957, 0xCBF1,	0x6959, 0xD9EA, 0x695A, 0xF5A2, 0x695E, 0xD7D1, 0x6960, 0xD1F8,
+	0x6961, 0xEAF8, 0x6962, 0xEAF9, 0x6963, 0xDAB3, 0x6968, 0xEFDF,	0x696B, 0xF1EF, 0x696D, 0xE5F6, 0x696E, 0xEEBF, 0x696F, 0xE2E4,
+	0x6975, 0xD0BF, 0x6977, 0xFAAC, 0x6978, 0xF5D1, 0x6979, 0xE7B3,	0x6995, 0xE9BE, 0x699B, 0xF2CE, 0x699C, 0xDBB4, 0x69A5, 0xFCCE,
+	0x69A7, 0xDDEE, 0x69AE, 0xE7B4, 0x69B4, 0xD7B4, 0x69BB, 0xF7B4,	0x69C1, 0xCDBE, 0x69C3, 0xDAE9, 0x69CB, 0xCFB0, 0x69CC, 0xF7D9,
+	0x69CD, 0xF3E6, 0x69D0, 0xCED9, 0x69E8, 0xCEAA, 0x69EA, 0xCBC8,	0x69FB, 0xD0A7, 0x69FD, 0xF0CB, 0x69FF, 0xD0C7, 0x6A02, 0xE4C5,
+	0x6A0A, 0xDBE0, 0x6A11, 0xD5DA, 0x6A13, 0xD7A7, 0x6A17, 0xEEC0,	0x6A19, 0xF8F6, 0x6A1E, 0xF5D2, 0x6A1F, 0xEDE9, 0x6A21, 0xD9BC,
+	0x6A23, 0xE5C6, 0x6A35, 0xF5A3, 0x6A38, 0xDAD4, 0x6A39, 0xE2A7,	0x6A3A, 0xFBFC, 0x6A3D, 0xF1DC, 0x6A44, 0xCAF4, 0x6A48, 0xE8FA,
+	0x6A4B, 0xCEE9, 0x6A52, 0xE9F8, 0x6A53, 0xE2E5, 0x6A58, 0xD0B9,	0x6A59, 0xD4F2, 0x6A5F, 0xD1A6, 0x6A61, 0xDFCE, 0x6A6B, 0xFCF4,
+	0x6A80, 0xD3AA, 0x6A84, 0xCCAC, 0x6A89, 0xEFE0, 0x6A8D, 0xE5E5,	0x6A8E, 0xD0D5, 0x6A97, 0xDBFC, 0x6A9C, 0xFCE6, 0x6AA2, 0xCBFE,
+	0x6AA3, 0xEDEA, 0x6AB3, 0xDEB1, 0x6ABB, 0xF9E3, 0x6AC2, 0xD4A2,	0x6AC3, 0xCFF6, 0x6AD3, 0xD6D0, 0x6ADA, 0xD5EA, 0x6ADB, 0xF1EE,
+	0x6AF6, 0xFACB, 0x6AFB, 0xE5A1, 0x6B04, 0xD5B1, 0x6B0A, 0xCFED,	0x6B0C, 0xEDEB, 0x6B12, 0xD5B2, 0x6B16, 0xD5BC, 0x6B20, 0xFDE2,
+	0x6B21, 0xF3AD, 0x6B23, 0xFDDB, 0x6B32, 0xE9B0, 0x6B3A, 0xD1A7,	0x6B3D, 0xFDE3, 0x6B3E, 0xCEB3, 0x6B46, 0xFDE4, 0x6B47, 0xFACE,
+	0x6B4C, 0xCAB0, 0x6B4E, 0xF7A7, 0x6B50, 0xCFB1, 0x6B5F, 0xE6A2,	0x6B61, 0xFCB6, 0x6B62, 0xF2AD, 0x6B63, 0xEFE1, 0x6B64, 0xF3AE,
+	0x6B65, 0xDCC6, 0x6B66, 0xD9EB, 0x6B6A, 0xE8E0, 0x6B72, 0xE1A8,	0x6B77, 0xD5F6, 0x6B78, 0xCFFD, 0x6B7B, 0xDEDD, 0x6B7F, 0xD9D1,
+	0x6B83, 0xE4EA, 0x6B84, 0xF2CF, 0x6B86, 0xF7BF, 0x6B89, 0xE2E6,	0x6B8A, 0xE2A8, 0x6B96, 0xE3D6, 0x6B98, 0xEDD1, 0x6B9E, 0xE9F9,
+	0x6BAE, 0xD6B1, 0x6BAF, 0xDEB2, 0x6BB2, 0xE0E8, 0x6BB5, 0xD3AB,	0x6BB7, 0xEBDC, 0x6BBA, 0xDFAF, 0x6BBC, 0xCAC3, 0x6BBF, 0xEEFC,
+	0x6BC1, 0xFDC3, 0x6BC5, 0xEBF6, 0x6BC6, 0xCFB2, 0x6BCB, 0xD9EC,	0x6BCD, 0xD9BD, 0x6BCF, 0xD8DF, 0x6BD2, 0xD4B8, 0x6BD3, 0xEBBE,
+	0x6BD4, 0xDDEF, 0x6BD6, 0xDDF0, 0x6BD7, 0xDDF1, 0x6BD8, 0xDDF2,	0x6BDB, 0xD9BE, 0x6BEB, 0xFBC6, 0x6BEC, 0xCFB3, 0x6C08, 0xEEFD,
+	0x6C0F, 0xE4AB, 0x6C11, 0xDAC5, 0x6C13, 0xD8EC, 0x6C23, 0xD1A8,	0x6C34, 0xE2A9, 0x6C37, 0xDEBC, 0x6C38, 0xE7B5, 0x6C3E, 0xDBF0,
+	0x6C40, 0xEFE2, 0x6C41, 0xF1F0, 0x6C42, 0xCFB4, 0x6C4E, 0xDBF1,	0x6C50, 0xE0B1, 0x6C55, 0xDFA5, 0x6C57, 0xF9D2, 0x6C5A, 0xE7FD,
+	0x6C5D, 0xE6A3, 0x6C5E, 0xFBF1, 0x6C5F, 0xCBB0, 0x6C60, 0xF2AE,	0x6C68, 0xCDE7, 0x6C6A, 0xE8DC, 0x6C6D, 0xE7D7, 0x6C70, 0xF7C0,
+	0x6C72, 0xD0E3, 0x6C76, 0xDAA1, 0x6C7A, 0xCCBD, 0x6C7D, 0xD1A9,	0x6C7E, 0xDDCC, 0x6C81, 0xE3FE, 0x6C82, 0xD1AA, 0x6C83, 0xE8AA,
+	0x6C85, 0xEAB6, 0x6C86, 0xF9FA, 0x6C87, 0xE6CC, 0x6C88, 0xF6D8,	0x6C8C, 0xD4C7, 0x6C90, 0xD9CB, 0x6C92, 0xD9D2, 0x6C93, 0xD3CB,
+	0x6C94, 0xD8F7, 0x6C95, 0xDAA9, 0x6C96, 0xF5F8, 0x6C99, 0xDEDE,	0x6C9A, 0xF2AF, 0x6C9B, 0xF8A9, 0x6CAB, 0xD8C8, 0x6CAE, 0xEEC1,
+	0x6CB3, 0xF9C1, 0x6CB8, 0xDDF3, 0x6CB9, 0xEAFA, 0x6CBB, 0xF6BD,	0x6CBC, 0xE1BB, 0x6CBD, 0xCDBF, 0x6CBE, 0xF4D4, 0x6CBF, 0xE6CD,
+	0x6CC1, 0xFCCF, 0x6CC2, 0xFBA2, 0x6CC4, 0xE0DC, 0x6CC9, 0xF4BB,	0x6CCA, 0xDAD5, 0x6CCC, 0xF9B2, 0x6CD3, 0xFBF2, 0x6CD5, 0xDBF6,
+	0x6CD7, 0xDEDF, 0x6CDB, 0xDBF2, 0x6CE1, 0xF8DC, 0x6CE2, 0xF7EE,	0x6CE3, 0xEBE8, 0x6CE5, 0xD2FA, 0x6CE8, 0xF1BC, 0x6CEB, 0xFADA,
+	0x6CEE, 0xDAEA, 0x6CEF, 0xDAC6, 0x6CF0, 0xF7C1, 0x6CF3, 0xE7B6,	0x6D0B, 0xE5C7, 0x6D0C, 0xD6AC, 0x6D11, 0xDCC7, 0x6D17, 0xE1A9,
+	0x6D19, 0xE2AA, 0x6D1B, 0xD5A6, 0x6D1E, 0xD4D7, 0x6D25, 0xF2D0,	0x6D27, 0xEAFB, 0x6D29, 0xE0DD, 0x6D2A, 0xFBF3, 0x6D32, 0xF1BD,
+	0x6D35, 0xE2E7, 0x6D36, 0xFDD7, 0x6D38, 0xCEC8, 0x6D39, 0xEAB7,	0x6D3B, 0xFCC0, 0x6D3D, 0xFDE7, 0x6D3E, 0xF7EF, 0x6D41, 0xD7B5,
+	0x6D59, 0xEFBA, 0x6D5A, 0xF1DD, 0x6D5C, 0xDEB3, 0x6D63, 0xE8CB,	0x6D66, 0xF8DD, 0x6D69, 0xFBC7, 0x6D6A, 0xD5C8, 0x6D6C, 0xD7DF,
+	0x6D6E, 0xDDA9, 0x6D74, 0xE9B1, 0x6D77, 0xFAAD, 0x6D78, 0xF6D9,	0x6D79, 0xFAF4, 0x6D7F, 0xF8AA, 0x6D85, 0xE6EE, 0x6D87, 0xCCDC,
+	0x6D88, 0xE1BC, 0x6D89, 0xE0EF, 0x6D8C, 0xE9BF, 0x6D8D, 0xFCFD,	0x6D8E, 0xE6CE, 0x6D91, 0xE1D7, 0x6D93, 0xE6CF, 0x6D95, 0xF4F1,
+	0x6DAF, 0xE4F3, 0x6DB2, 0xE4FB, 0x6DB5, 0xF9E4, 0x6DC0, 0xEFE3,	0x6DC3, 0xCFEE, 0x6DC4, 0xF6BE, 0x6DC5, 0xE0B2, 0x6DC6, 0xFCFE,
+	0x6DC7, 0xD1AB, 0x6DCB, 0xD7FA, 0x6DCF, 0xFBC8, 0x6DD1, 0xE2D7,	0x6DD8, 0xD4A3, 0x6DD9, 0xF0F8, 0x6DDA, 0xD7A8, 0x6DDE, 0xE1E7,
+	0x6DE1, 0xD3BF, 0x6DE8, 0xEFE4, 0x6DEA, 0xD7C5, 0x6DEB, 0xEBE2,	0x6DEE, 0xFCE7, 0x6DF1, 0xE4A2, 0x6DF3, 0xE2E8, 0x6DF5, 0xE6D0,
+	0x6DF7, 0xFBE8, 0x6DF8, 0xF4E8, 0x6DF9, 0xE5F4, 0x6DFA, 0xF4BC,	0x6DFB, 0xF4D5, 0x6E17, 0xDFB6, 0x6E19, 0xFCB9, 0x6E1A, 0xEEC2,
+	0x6E1B, 0xCAF5, 0x6E1F, 0xEFE5, 0x6E20, 0xCBE2, 0x6E21, 0xD4A4,	0x6E23, 0xDEE0, 0x6E24, 0xDAFD, 0x6E25, 0xE4C6, 0x6E26, 0xE8BE,
+	0x6E2B, 0xE0DE, 0x6E2C, 0xF6B4, 0x6E2D, 0xEAD2, 0x6E2F, 0xF9FB,	0x6E32, 0xE0C2, 0x6E34, 0xCAE4, 0x6E36, 0xE7B7, 0x6E38, 0xEAFD,
+	0x6E3A, 0xD9DD, 0x6E3C, 0xDAB4, 0x6E3D, 0xEEAA, 0x6E3E, 0xFBE9,	0x6E43, 0xDBCB, 0x6E44, 0xDAB5, 0x6E4A, 0xF1BE, 0x6E4D, 0xD3AC,
+	0x6E56, 0xFBC9, 0x6E58, 0xDFCF, 0x6E5B, 0xD3C0, 0x6E5C, 0xE3D7,	0x6E5E, 0xEFE6, 0x6E5F, 0xFCD0, 0x6E67, 0xE9C0, 0x6E6B, 0xF5D3,
+	0x6E6E, 0xECDC, 0x6E6F, 0xF7B7, 0x6E72, 0xEAB8, 0x6E73, 0xD1F9,	0x6E7A, 0xDCC8, 0x6E90, 0xEAB9, 0x6E96, 0xF1DE, 0x6E9C, 0xD7B6,
+	0x6E9D, 0xCFB5, 0x6E9F, 0xD9A8, 0x6EA2, 0xECEE, 0x6EA5, 0xDDAA,	0x6EAA, 0xCDA2, 0x6EAB, 0xE8AE, 0x6EAF, 0xE1BD, 0x6EB1, 0xF2D1,
+	0x6EB6, 0xE9C1, 0x6EBA, 0xD2FC, 0x6EC2, 0xDBB5, 0x6EC4, 0xF3E7,	0x6EC5, 0xD8FE, 0x6EC9, 0xFCD1, 0x6ECB, 0xEDB2, 0x6ECC, 0xF4AF,
+	0x6ECE, 0xFBA3, 0x6ED1, 0xFCC1, 0x6ED3, 0xEEAB, 0x6ED4, 0xD4A5,	0x6EEF, 0xF4F2, 0x6EF4, 0xEED9, 0x6EF8, 0xFBCA, 0x6EFE, 0xCDE3,
+	0x6EFF, 0xD8BB, 0x6F01, 0xE5DB, 0x6F02, 0xF8F7, 0x6F06, 0xF6D4,	0x6F0F, 0xD7A9, 0x6F11, 0xCBC9, 0x6F14, 0xE6D1, 0x6F15, 0xF0CC,
+	0x6F20, 0xD8AE, 0x6F22, 0xF9D3, 0x6F23, 0xD5FE, 0x6F2B, 0xD8BC,	0x6F2C, 0xF2B0, 0x6F31, 0xE2AB, 0x6F32, 0xF3E8, 0x6F38, 0xEFC2,
+	0x6F3F, 0xEDEC, 0x6F41, 0xE7B8, 0x6F51, 0xDAFE, 0x6F54, 0xCCBE,	0x6F57, 0xF2FC, 0x6F58, 0xDAEB, 0x6F5A, 0xE2D8, 0x6F5B, 0xEDD6,
+	0x6F5E, 0xD6D1, 0x6F5F, 0xE0B3, 0x6F62, 0xFCD2, 0x6F64, 0xEBC8,	0x6F6D, 0xD3C1, 0x6F6E, 0xF0CD, 0x6F70, 0xCFF7, 0x6F7A, 0xEDD2,
+	0x6F7C, 0xD4D8, 0x6F7D, 0xDCC9, 0x6F7E, 0xD7F1, 0x6F81, 0xDFBB,	0x6F84, 0xF3A5, 0x6F88, 0xF4CD, 0x6F8D, 0xF1BF, 0x6F8E, 0xF8B1,
+	0x6F90, 0xE9FA, 0x6F94, 0xFBCB, 0x6F97, 0xCAD5, 0x6FA3, 0xF9D4,	0x6FA4, 0xF7CA, 0x6FA7, 0xD6C8, 0x6FAE, 0xFCE8, 0x6FAF, 0xF3BD,
+	0x6FB1, 0xEEFE, 0x6FB3, 0xE7FE, 0x6FB9, 0xD3C2, 0x6FBE, 0xD3B6,	0x6FC0, 0xCCAD, 0x6FC1, 0xF6FA, 0x6FC2, 0xD6B2, 0x6FC3, 0xD2D8,
+	0x6FCA, 0xE7D8, 0x6FD5, 0xE3A5, 0x6FDA, 0xE7B9, 0x6FDF, 0xF0AD,	0x6FE0, 0xFBCC, 0x6FE1, 0xEBA1, 0x6FE4, 0xD4A6, 0x6FE9, 0xFBCD,
+	0x6FEB, 0xD5BD, 0x6FEC, 0xF1DF, 0x6FEF, 0xF6FB, 0x6FF1, 0xDEB4,	0x6FFE, 0xD5EB, 0x7001, 0xE5C8, 0x7005, 0xFBA4, 0x7006, 0xD4B9,
+	0x7009, 0xDEE1, 0x700B, 0xE4A3, 0x700F, 0xD7B7, 0x7011, 0xF8EE,	0x7015, 0xDEB5, 0x7018, 0xD6D2, 0x701A, 0xF9D5, 0x701B, 0xE7BA,
+	0x701C, 0xEBD5, 0x701D, 0xD5F7, 0x701E, 0xEFE7, 0x701F, 0xE1BE,	0x7023, 0xFAAE, 0x7027, 0xD6E9, 0x7028, 0xD6EE, 0x702F, 0xE7BB,
+	0x7037, 0xECCB, 0x703E, 0xD5B3, 0x704C, 0xCEB4, 0x7050, 0xFBA5,	0x7051, 0xE1EE, 0x7058, 0xF7A8, 0x705D, 0xFBCE, 0x7063, 0xD8BD,
+	0x706B, 0xFBFD, 0x7070, 0xFCE9, 0x7078, 0xCFB6, 0x707C, 0xEDC7,	0x707D, 0xEEAC, 0x7085, 0xCCDD, 0x708A, 0xF6A7, 0x708E, 0xE6FA,
+	0x7092, 0xF5A4, 0x7098, 0xFDDC, 0x7099, 0xEDB3, 0x709A, 0xCEC9,	0x70A1, 0xEFE8, 0x70A4, 0xE1BF, 0x70AB, 0xFADB, 0x70AC, 0xCBE3,
+	0x70AD, 0xF7A9, 0x70AF, 0xFBA6, 0x70B3, 0xDCB9, 0x70B7, 0xF1C0,	0x70B8, 0xEDC8, 0x70B9, 0xEFC3, 0x70C8, 0xD6AD, 0x70CB, 0xFDCE,
+	0x70CF, 0xE8A1, 0x70D8, 0xFBF4, 0x70D9, 0xD5A7, 0x70DD, 0xF1F6,	0x70DF, 0xE6D3, 0x70F1, 0xCCDE, 0x70F9, 0xF8B2, 0x70FD, 0xDCEB,
+	0x7104, 0xFDB6, 0x7109, 0xE5EA, 0x710C, 0xF1E0, 0x7119, 0xDBCC,	0x711A, 0xDDCD, 0x711E, 0xD4C8, 0x7121, 0xD9ED, 0x7126, 0xF5A5,
+	0x7130, 0xE6FB, 0x7136, 0xE6D4, 0x7147, 0xFDC8, 0x7149, 0xD6A1,	0x714A, 0xFDBF, 0x714C, 0xFCD3, 0x714E, 0xEFA1, 0x7150, 0xE7BC,
+	0x7156, 0xD1EE, 0x7159, 0xE6D5, 0x715C, 0xE9F2, 0x715E, 0xDFB0,	0x7164, 0xD8E0, 0x7165, 0xFCBA, 0x7166, 0xFDAF, 0x7167, 0xF0CE,
+	0x7169, 0xDBE1, 0x716C, 0xE5C9, 0x716E, 0xEDB4, 0x717D, 0xE0C3,	0x7184, 0xE3D8, 0x7189, 0xE9FB, 0x718A, 0xEAA8, 0x718F, 0xFDB7,
+	0x7192, 0xFBA7, 0x7194, 0xE9C2, 0x7199, 0xFDF7, 0x719F, 0xE2D9,	0x71A2, 0xDCEC, 0x71AC, 0xE8A2, 0x71B1, 0xE6F0, 0x71B9, 0xFDF8,
+	0x71BA, 0xFDF9, 0x71BE, 0xF6BF, 0x71C1, 0xE7A7, 0x71C3, 0xE6D7,	0x71C8, 0xD4F3, 0x71C9, 0xD4C9, 0x71CE, 0xD6FA, 0x71D0, 0xD7F2,
+	0x71D2, 0xE1C0, 0x71D4, 0xDBE2, 0x71D5, 0xE6D8, 0x71DF, 0xE7BD,	0x71E5, 0xF0CF, 0x71E6, 0xF3BE, 0x71E7, 0xE2AC, 0x71ED, 0xF5B7,
+	0x71EE, 0xE0F0, 0x71FB, 0xFDB8, 0x71FC, 0xE3E8, 0x71FE, 0xD4A7,	0x71FF, 0xE8FC, 0x7200, 0xFAD2, 0x7206, 0xF8EF, 0x7210, 0xD6D3,
+	0x721B, 0xD5B4, 0x722A, 0xF0D0, 0x722C, 0xF7F0, 0x722D, 0xEEB3,	0x7230, 0xEABA, 0x7232, 0xEAD3, 0x7235, 0xEDC9, 0x7236, 0xDDAB,
+	0x723A, 0xE5AC, 0x723B, 0xFDA1, 0x723D, 0xDFD0, 0x723E, 0xECB3,	0x7240, 0xDFD1, 0x7246, 0xEDED, 0x7247, 0xF8B8, 0x7248, 0xF7FA,
+	0x724C, 0xF8AB, 0x7252, 0xF4E0, 0x7258, 0xD4BA, 0x7259, 0xE4B3,	0x725B, 0xE9DA, 0x725D, 0xDEB6, 0x725F, 0xD9BF, 0x7261, 0xD9C0,
+	0x7262, 0xD6EF, 0x7267, 0xD9CC, 0x7269, 0xDAAA, 0x7272, 0xDFE5,	0x7279, 0xF7E5, 0x727D, 0xCCB2, 0x7280, 0xDFF9, 0x7281, 0xD7E0,
+	0x72A2, 0xD4BB, 0x72A7, 0xFDFA, 0x72AC, 0xCCB3, 0x72AF, 0xDBF3,	0x72C0, 0xDFD2, 0x72C2, 0xCECA, 0x72C4, 0xEEDA, 0x72CE, 0xE4E4,
+	0x72D0, 0xFBCF, 0x72D7, 0xCFB7, 0x72D9, 0xEEC3, 0x72E1, 0xCEEA,	0x72E9, 0xE2AD, 0x72F8, 0xD7E1, 0x72F9, 0xFAF5, 0x72FC, 0xD5C9,
+	0x72FD, 0xF8AC, 0x730A, 0xE7D9, 0x7316, 0xF3E9, 0x731B, 0xD8ED,	0x731C, 0xE3C4, 0x731D, 0xF0F1, 0x7325, 0xE8E5, 0x7329, 0xE0FA,
+	0x732A, 0xEEC4, 0x732B, 0xD9DE, 0x7336, 0xEBA2, 0x7337, 0xEBA3,	0x733E, 0xFCC2, 0x733F, 0xEABB, 0x7344, 0xE8AB, 0x7345, 0xDEE2,
+	0x7350, 0xEDEF, 0x7352, 0xE8A3, 0x7357, 0xCFF1, 0x7368, 0xD4BC,	0x736A, 0xFCEA, 0x7370, 0xE7BE, 0x7372, 0xFCF2, 0x7375, 0xD6B4,
+	0x7378, 0xE2AE, 0x737A, 0xD3B7, 0x737B, 0xFACC, 0x7384, 0xFADC,	0x7386, 0xEDB5, 0x7387, 0xE1E3, 0x7389, 0xE8AC, 0x738B, 0xE8DD,
+	0x738E, 0xEFE9, 0x7394, 0xF4BD, 0x7396, 0xCFB8, 0x7397, 0xE9DB,	0x7398, 0xD1AC, 0x739F, 0xDAC7, 0x73A7, 0xEBC9, 0x73A9, 0xE8CC,
+	0x73AD, 0xDEB7, 0x73B2, 0xD6BC, 0x73B3, 0xD3E5, 0x73B9, 0xFADD,	0x73C0, 0xDAD6, 0x73C2, 0xCAB1, 0x73C9, 0xDAC8, 0x73CA, 0xDFA6,
+	0x73CC, 0xF9B3, 0x73CD, 0xF2D2, 0x73CF, 0xCAC4, 0x73D6, 0xCECB,	0x73D9, 0xCDF5, 0x73DD, 0xFDB0, 0x73DE, 0xD5A8, 0x73E0, 0xF1C1,
+	0x73E3, 0xE2E9, 0x73E4, 0xDCCA, 0x73E5, 0xECB4, 0x73E6, 0xFAC0,	0x73E9, 0xFBA8, 0x73EA, 0xD0A8, 0x73ED, 0xDAEC, 0x73F7, 0xD9EE,
+	0x73F9, 0xE0FB, 0x73FD, 0xEFEA, 0x73FE, 0xFADE, 0x7401, 0xE0C4,	0x7403, 0xCFB9, 0x7405, 0xD5CA, 0x7406, 0xD7E2, 0x7407, 0xE2AF,
+	0x7409, 0xD7B8, 0x7413, 0xE8CD, 0x741B, 0xF6DA, 0x7420, 0xEFA2,	0x7421, 0xE2DA, 0x7422, 0xF6FC, 0x7425, 0xFBD0, 0x7426, 0xD1AD,
+	0x7428, 0xCDE4, 0x742A, 0xD1AE, 0x742B, 0xDCED, 0x742C, 0xE8CE,	0x742E, 0xF0F9, 0x742F, 0xCEB5, 0x7430, 0xE6FC, 0x7433, 0xD7FB,
+	0x7434, 0xD0D6, 0x7435, 0xDDF5, 0x7436, 0xF7F1, 0x7438, 0xF6FD,	0x743A, 0xDBF7, 0x743F, 0xFBEA, 0x7440, 0xE9DC, 0x7441, 0xD9C1,
+	0x7443, 0xF5F2, 0x7444, 0xE0C5, 0x744B, 0xEAD4, 0x7455, 0xF9C2,	0x7457, 0xEABC, 0x7459, 0xD2C5, 0x745A, 0xFBD1, 0x745B, 0xE7C0,
+	0x745C, 0xEBA5, 0x745E, 0xDFFA, 0x745F, 0xE3A2, 0x7460, 0xD7B9,	0x7462, 0xE9C3, 0x7464, 0xE8FD, 0x7465, 0xE8AF, 0x7468, 0xF2D3,
+	0x7469, 0xFBA9, 0x746A, 0xD8A5, 0x746F, 0xD5CB, 0x747E, 0xD0C8,	0x7482, 0xD1AF, 0x7483, 0xD7E3, 0x7487, 0xE0C6, 0x7489, 0xD6A2,
+	0x748B, 0xEDF0, 0x7498, 0xD7F3, 0x749C, 0xFCD4, 0x749E, 0xDAD7,	0x749F, 0xCCDF, 0x74A1, 0xF2D4, 0x74A3, 0xD1B0, 0x74A5, 0xCCE0,
+	0x74A7, 0xDBFD, 0x74A8, 0xF3BF, 0x74AA, 0xF0D1, 0x74B0, 0xFCBB,	0x74B2, 0xE2B0, 0x74B5, 0xE6A5, 0x74B9, 0xE2DB, 0x74BD, 0xDFDE,
+	0x74BF, 0xE0C7, 0x74C6, 0xF2EF, 0x74CA, 0xCCE1, 0x74CF, 0xD6EA,	0x74D4, 0xE7C2, 0x74D8, 0xCEB6, 0x74DA, 0xF3C0, 0x74DC, 0xCDFE,
+	0x74E0, 0xFBD2, 0x74E2, 0xF8F8, 0x74E3, 0xF7FB, 0x74E6, 0xE8BF,	0x74EE, 0xE8B7, 0x74F7, 0xEDB6, 0x7501, 0xDCBA, 0x7504, 0xCCB4,
+	0x7511, 0xF1F7, 0x7515, 0xE8B8, 0x7518, 0xCAF6, 0x751A, 0xE4A4,	0x751B, 0xF4D6, 0x751F, 0xDFE6, 0x7523, 0xDFA7, 0x7525, 0xDFE7,
+	0x7526, 0xE1C1, 0x7528, 0xE9C4, 0x752B, 0xDCCB, 0x752C, 0xE9C5,	0x7530, 0xEFA3, 0x7531, 0xEBA6, 0x7532, 0xCBA3, 0x7533, 0xE3E9,
+	0x7537, 0xD1FB, 0x7538, 0xEFA4, 0x753A, 0xEFEB, 0x7547, 0xD0B4,	0x754C, 0xCDA3, 0x754F, 0xE8E6, 0x7551, 0xEFA5, 0x7553, 0xD3CC,
+	0x7554, 0xDAED, 0x7559, 0xD7BA, 0x755B, 0xF2D5, 0x755C, 0xF5E5,	0x755D, 0xD9EF, 0x7562, 0xF9B4, 0x7565, 0xD5D4, 0x7566, 0xFDCF,
+	0x756A, 0xDBE3, 0x756F, 0xF1E1, 0x7570, 0xECB6, 0x7575, 0xFBFE,	0x7576, 0xD3D7, 0x7578, 0xD1B1, 0x757A, 0xCBB1, 0x757F, 0xD1B2,
+	0x7586, 0xCBB2, 0x7587, 0xF1C2, 0x758A, 0xF4E1, 0x758B, 0xF9B5,	0x758E, 0xE1C3, 0x758F, 0xE1C2, 0x7591, 0xEBF7, 0x759D, 0xDFA8,
+	0x75A5, 0xCBCA, 0x75AB, 0xE6B9, 0x75B1, 0xF8DE, 0x75B2, 0xF9AA,	0x75B3, 0xCAF7, 0x75B5, 0xEDB7, 0x75B8, 0xD3B8, 0x75B9, 0xF2D6,
+	0x75BC, 0xD4D9, 0x75BD, 0xEEC5, 0x75BE, 0xF2F0, 0x75C2, 0xCAB2,	0x75C5, 0xDCBB, 0x75C7, 0xF1F8, 0x75CD, 0xECB7, 0x75D2, 0xE5CA,
+	0x75D4, 0xF6C0, 0x75D5, 0xFDDD, 0x75D8, 0xD4E3, 0x75D9, 0xCCE2,	0x75DB, 0xF7D4, 0x75E2, 0xD7E5, 0x75F0, 0xD3C3, 0x75F2, 0xD8A6,
+	0x75F4, 0xF6C1, 0x75FA, 0xDDF6, 0x75FC, 0xCDC0, 0x7600, 0xE5DC,	0x760D, 0xE5CB, 0x7619, 0xE1C4, 0x761F, 0xE8B0, 0x7620, 0xF4B0,
+	0x7621, 0xF3EA, 0x7622, 0xDAEE, 0x7624, 0xD7BB, 0x7626, 0xE2B1,	0x763B, 0xD7AA, 0x7642, 0xD6FB, 0x764C, 0xE4DF, 0x764E, 0xCAD6,
+	0x7652, 0xEBA8, 0x7656, 0xDBFE, 0x7661, 0xF6C2, 0x7664, 0xEFBB,	0x7669, 0xD4FD, 0x766C, 0xE0C8, 0x7670, 0xE8B9, 0x7672, 0xEFA6,
+	0x7678, 0xCDA4, 0x767B, 0xD4F4, 0x767C, 0xDBA1, 0x767D, 0xDBDC,	0x767E, 0xDBDD, 0x7684, 0xEEDC, 0x7686, 0xCBCB, 0x7687, 0xFCD5,
+	0x768E, 0xCEEB, 0x7690, 0xCDC1, 0x7693, 0xFBD3, 0x76AE, 0xF9AB,	0x76BA, 0xF5D4, 0x76BF, 0xD9A9, 0x76C2, 0xE9DD, 0x76C3, 0xDBCD,
+	0x76C6, 0xDDCE, 0x76C8, 0xE7C3, 0x76CA, 0xECCC, 0x76D2, 0xF9EC,	0x76D6, 0xCBCC, 0x76DB, 0xE0FC, 0x76DC, 0xD4A8, 0x76DE, 0xEDD3,
+	0x76DF, 0xD8EF, 0x76E1, 0xF2D7, 0x76E3, 0xCAF8, 0x76E4, 0xDAEF,	0x76E7, 0xD6D4, 0x76EE, 0xD9CD, 0x76F2, 0xD8EE, 0x76F4, 0xF2C1,
+	0x76F8, 0xDFD3, 0x76FC, 0xDAF0, 0x76FE, 0xE2EA, 0x7701, 0xE0FD,	0x7704, 0xD8F8, 0x7708, 0xF7AF, 0x7709, 0xDAB6, 0x770B, 0xCAD7,
+	0x771E, 0xF2D8, 0x7720, 0xD8F9, 0x7729, 0xFADF, 0x7737, 0xCFEF,	0x7738, 0xD9C2, 0x773A, 0xF0D2, 0x773C, 0xE4D1, 0x7740, 0xF3B7,
+	0x774D, 0xFAE0, 0x775B, 0xEFEC, 0x7761, 0xE2B2, 0x7763, 0xD4BD,	0x7766, 0xD9CE, 0x776B, 0xF4E2, 0x7779, 0xD4A9, 0x777E, 0xCDC2,
+	0x777F, 0xE7DA, 0x778B, 0xF2D9, 0x7791, 0xD9AA, 0x779E, 0xD8BE,	0x77A5, 0xDCAD, 0x77AC, 0xE2EB, 0x77AD, 0xD6FC, 0x77B0, 0xCAF9,
+	0x77B3, 0xD4DA, 0x77BB, 0xF4D7, 0x77BC, 0xCCA1, 0x77BF, 0xCFBA,	0x77D7, 0xF5B8, 0x77DB, 0xD9C3, 0x77DC, 0xD0E8, 0x77E2, 0xE3C5,
+	0x77E3, 0xEBF8, 0x77E5, 0xF2B1, 0x77E9, 0xCFBB, 0x77ED, 0xD3AD,	0x77EE, 0xE8E1, 0x77EF, 0xCEEC, 0x77F3, 0xE0B4, 0x7802, 0xDEE3,
+	0x7812, 0xDDF7, 0x7825, 0xF2B2, 0x7826, 0xF3F6, 0x7827, 0xF6DB,	0x782C, 0xD7FE, 0x7832, 0xF8DF, 0x7834, 0xF7F2, 0x7845, 0xD0A9,
+	0x784F, 0xE6DA, 0x785D, 0xF5A6, 0x786B, 0xD7BC, 0x786C, 0xCCE3,	0x786F, 0xE6DB, 0x787C, 0xDDDD, 0x7881, 0xD1B3, 0x7887, 0xEFED,
+	0x788C, 0xD6DE, 0x788D, 0xE4F4, 0x788E, 0xE1EF, 0x7891, 0xDDF8,	0x7897, 0xE8CF, 0x78A3, 0xCAE5, 0x78A7, 0xDCA1, 0x78A9, 0xE0B5,
+	0x78BA, 0xFCAC, 0x78BB, 0xFCAD, 0x78BC, 0xD8A7, 0x78C1, 0xEDB8,	0x78C5, 0xDBB6, 0x78CA, 0xD6F0, 0x78CB, 0xF3AF, 0x78CE, 0xCDA5,
+	0x78D0, 0xDAF1, 0x78E8, 0xD8A8, 0x78EC, 0xCCE4, 0x78EF, 0xD1B4,	0x78F5, 0xCAD8, 0x78FB, 0xDAF2, 0x7901, 0xF5A7, 0x790E, 0xF5A8,
+	0x7916, 0xE6A6, 0x792A, 0xD5EC, 0x792B, 0xD5F8, 0x792C, 0xDAF3,	0x793A, 0xE3C6, 0x793E, 0xDEE4, 0x7940, 0xDEE5, 0x7941, 0xD1B5,
+	0x7947, 0xD1B6, 0x7948, 0xD1B7, 0x7949, 0xF2B3, 0x7950, 0xE9DE,	0x7956, 0xF0D3, 0x7957, 0xF2B4, 0x795A, 0xF0D4, 0x795B, 0xCBE4,
+	0x795C, 0xFBD4, 0x795D, 0xF5E6, 0x795E, 0xE3EA, 0x7960, 0xDEE6,	0x7965, 0xDFD4, 0x7968, 0xF8F9, 0x796D, 0xF0AE, 0x797A, 0xD1B8,
+	0x797F, 0xD6DF, 0x7981, 0xD0D7, 0x798D, 0xFCA1, 0x798E, 0xEFEE,	0x798F, 0xDCD8, 0x7991, 0xE9DF, 0x79A6, 0xE5DD, 0x79A7, 0xFDFB,
+	0x79AA, 0xE0C9, 0x79AE, 0xD6C9, 0x79B1, 0xD4AA, 0x79B3, 0xE5CC,	0x79B9, 0xE9E0, 0x79BD, 0xD0D8, 0x79BE, 0xFCA2, 0x79BF, 0xD4BE,
+	0x79C0, 0xE2B3, 0x79C1, 0xDEE7, 0x79C9, 0xDCBC, 0x79CA, 0xD2B6,	0x79CB, 0xF5D5, 0x79D1, 0xCEA1, 0x79D2, 0xF5A9, 0x79D5, 0xDDF9,
+	0x79D8, 0xDDFA, 0x79DF, 0xF0D5, 0x79E4, 0xF6DF, 0x79E6, 0xF2DA,	0x79E7, 0xE4EB, 0x79E9, 0xF2F1, 0x79FB, 0xECB9, 0x7A00, 0xFDFC,
+	0x7A05, 0xE1AA, 0x7A08, 0xCAD9, 0x7A0B, 0xEFEF, 0x7A0D, 0xF5AA,	0x7A14, 0xECF9, 0x7A17, 0xF8AD, 0x7A19, 0xF2C2, 0x7A1A, 0xF6C3,
+	0x7A1C, 0xD7D2, 0x7A1F, 0xF9A2, 0x7A20, 0xF0D6, 0x7A2E, 0xF0FA,	0x7A31, 0xF6E0, 0x7A36, 0xE9F3, 0x7A37, 0xF2C3, 0x7A3B, 0xD4AB,
+	0x7A3C, 0xCAB3, 0x7A3D, 0xCDA6, 0x7A3F, 0xCDC3, 0x7A40, 0xCDDA,	0x7A46, 0xD9CF, 0x7A49, 0xF6C4, 0x7A4D, 0xEEDD, 0x7A4E, 0xE7C4,
+	0x7A57, 0xE2B4, 0x7A61, 0xDFE2, 0x7A62, 0xE7DB, 0x7A69, 0xE8B1,	0x7A6B, 0xFCAE, 0x7A70, 0xE5CD, 0x7A74, 0xFAEB, 0x7A76, 0xCFBC,
+	0x7A79, 0xCFE2, 0x7A7A, 0xCDF6, 0x7A7D, 0xEFF0, 0x7A7F, 0xF4BE,	0x7A81, 0xD4CD, 0x7A84, 0xF3B8, 0x7A88, 0xE9A1, 0x7A92, 0xF2F2,
+	0x7A93, 0xF3EB, 0x7A95, 0xF0D7, 0x7A98, 0xCFD7, 0x7A9F, 0xCFDF,	0x7AA9, 0xE8C0, 0x7AAA, 0xE8C1, 0x7AAE, 0xCFE3, 0x7AAF, 0xE9A2,
+	0x7ABA, 0xD0AA, 0x7AC4, 0xF3C1, 0x7AC5, 0xD0AB, 0x7AC7, 0xD4E4,	0x7ACA, 0xEFBC, 0x7ACB, 0xD8A1, 0x7AD7, 0xD9DF, 0x7AD9, 0xF3D7,
+	0x7ADD, 0xDCBD, 0x7ADF, 0xCCE5, 0x7AE0, 0xEDF1, 0x7AE3, 0xF1E2,	0x7AE5, 0xD4DB, 0x7AEA, 0xE2B5, 0x7AED, 0xCAE6, 0x7AEF, 0xD3AE,
+	0x7AF6, 0xCCE6, 0x7AF9, 0xF1D3, 0x7AFA, 0xF5E7, 0x7AFF, 0xCADA,	0x7B0F, 0xFBEE, 0x7B11, 0xE1C5, 0x7B19, 0xDFE9, 0x7B1B, 0xEEDE,
+	0x7B1E, 0xF7C2, 0x7B20, 0xD8A2, 0x7B26, 0xDDAC, 0x7B2C, 0xF0AF,	0x7B2D, 0xD6BD, 0x7B39, 0xE1AB, 0x7B46, 0xF9B6, 0x7B49, 0xD4F5,
+	0x7B4B, 0xD0C9, 0x7B4C, 0xEFA7, 0x7B4D, 0xE2EC, 0x7B4F, 0xDBEA,	0x7B50, 0xCECC, 0x7B51, 0xF5E8, 0x7B52, 0xF7D5, 0x7B54, 0xD3CD,
+	0x7B56, 0xF3FE, 0x7B60, 0xD0B5, 0x7B6C, 0xE0FE, 0x7B6E, 0xDFFB,	0x7B75, 0xE6DD, 0x7B7D, 0xE8A4, 0x7B87, 0xCBCD, 0x7B8B, 0xEFA8,
+	0x7B8F, 0xEEB4, 0x7B94, 0xDAD8, 0x7B95, 0xD1B9, 0x7B97, 0xDFA9,	0x7B9A, 0xF3B0, 0x7B9D, 0xCCC4, 0x7BA1, 0xCEB7, 0x7BAD, 0xEFA9,
+	0x7BB1, 0xDFD5, 0x7BB4, 0xEDD7, 0x7BB8, 0xEEC6, 0x7BC0, 0xEFBD,	0x7BC1, 0xFCD6, 0x7BC4, 0xDBF4, 0x7BC6, 0xEFAA, 0x7BC7, 0xF8B9,
+	0x7BC9, 0xF5E9, 0x7BD2, 0xE3D9, 0x7BE0, 0xE1C6, 0x7BE4, 0xD4BF,	0x7BE9, 0xDEE8, 0x7C07, 0xF0EA, 0x7C12, 0xF3C2, 0x7C1E, 0xD3AF,
+	0x7C21, 0xCADB, 0x7C27, 0xFCD7, 0x7C2A, 0xEDD8, 0x7C2B, 0xE1C7,	0x7C3D, 0xF4D8, 0x7C3E, 0xD6B3, 0x7C3F, 0xDDAD, 0x7C43, 0xD5BE,
+	0x7C4C, 0xF1C3, 0x7C4D, 0xEEDF, 0x7C60, 0xD6EB, 0x7C64, 0xF4D9,	0x7C6C, 0xD7E6, 0x7C73, 0xDAB7, 0x7C83, 0xDDFB, 0x7C89, 0xDDCF,
+	0x7C92, 0xD8A3, 0x7C95, 0xDAD9, 0x7C97, 0xF0D8, 0x7C98, 0xEFC4,	0x7C9F, 0xE1D8, 0x7CA5, 0xF1D4, 0x7CA7, 0xEDF2, 0x7CAE, 0xD5DB,
+	0x7CB1, 0xD5DC, 0x7CB2, 0xF3C4, 0x7CB3, 0xCBD7, 0x7CB9, 0xE2B6,	0x7CBE, 0xEFF1, 0x7CCA, 0xFBD5, 0x7CD6, 0xD3D8, 0x7CDE, 0xDDD0,
+	0x7CDF, 0xF0D9, 0x7CE0, 0xCBB3, 0x7CE7, 0xD5DD, 0x7CFB, 0xCDA7,	0x7CFE, 0xD0AC, 0x7D00, 0xD1BA, 0x7D02, 0xF1C4, 0x7D04, 0xE5B3,
+	0x7D05, 0xFBF5, 0x7D06, 0xE9E1, 0x7D07, 0xFDE0, 0x7D08, 0xFCBC,	0x7D0A, 0xDAA2, 0x7D0B, 0xDAA3, 0x7D0D, 0xD2A1, 0x7D10, 0xD2EF,
+	0x7D14, 0xE2ED, 0x7D17, 0xDEE9, 0x7D18, 0xCEDC, 0x7D19, 0xF2B5,	0x7D1A, 0xD0E4, 0x7D1B, 0xDDD1, 0x7D20, 0xE1C8, 0x7D21, 0xDBB7,
+	0x7D22, 0xDFE3, 0x7D2B, 0xEDB9, 0x7D2C, 0xF1C5, 0x7D2E, 0xF3CF,	0x7D2F, 0xD7AB, 0x7D30, 0xE1AC, 0x7D33, 0xE3EB, 0x7D35, 0xEEC7,
+	0x7D39, 0xE1C9, 0x7D3A, 0xCAFA, 0x7D42, 0xF0FB, 0x7D43, 0xFAE1,	0x7D44, 0xF0DA, 0x7D45, 0xCCE7, 0x7D46, 0xDAF4, 0x7D50, 0xCCBF,
+	0x7D5E, 0xCEED, 0x7D61, 0xD5A9, 0x7D62, 0xFAE2, 0x7D66, 0xD0E5,	0x7D68, 0xEBD6, 0x7D6A, 0xECDF, 0x7D6E, 0xDFFC, 0x7D71, 0xF7D6,
+	0x7D72, 0xDEEA, 0x7D73, 0xCBB4, 0x7D76, 0xEFBE, 0x7D79, 0xCCB5,	0x7D7F, 0xCFBD, 0x7D8E, 0xEFF2, 0x7D8F, 0xE2B7, 0x7D93, 0xCCE8,
+	0x7D9C, 0xF0FC, 0x7DA0, 0xD6E0, 0x7DA2, 0xF1C6, 0x7DAC, 0xE2B8,	0x7DAD, 0xEBAB, 0x7DB1, 0xCBB5, 0x7DB2, 0xD8D1, 0x7DB4, 0xF4CE,
+	0x7DB5, 0xF3F7, 0x7DB8, 0xD7C6, 0x7DBA, 0xD1BB, 0x7DBB, 0xF7AA,	0x7DBD, 0xEDCA, 0x7DBE, 0xD7D3, 0x7DBF, 0xD8FA, 0x7DC7, 0xF6C5,
+	0x7DCA, 0xD1CC, 0x7DCB, 0xDDFC, 0x7DD6, 0xDFFD, 0x7DD8, 0xF9E5,	0x7DDA, 0xE0CA, 0x7DDD, 0xF2FD, 0x7DDE, 0xD3B0, 0x7DE0, 0xF4F3,
+	0x7DE1, 0xDAC9, 0x7DE3, 0xE6DE, 0x7DE8, 0xF8BA, 0x7DE9, 0xE8D0,	0x7DEC, 0xD8FB, 0x7DEF, 0xEAD5, 0x7DF4, 0xD6A3, 0x7DFB, 0xF6C6,
+	0x7E09, 0xF2DB, 0x7E0A, 0xE4FC, 0x7E15, 0xE8B2, 0x7E1B, 0xDADA,	0x7E1D, 0xF2DC, 0x7E1E, 0xFBD6, 0x7E1F, 0xE9B2, 0x7E21, 0xEEAD,
+	0x7E23, 0xFAE3, 0x7E2B, 0xDCEE, 0x7E2E, 0xF5EA, 0x7E2F, 0xE6E0,	0x7E31, 0xF0FD, 0x7E37, 0xD7AC, 0x7E3D, 0xF5C5, 0x7E3E, 0xEEE0,
+	0x7E41, 0xDBE5, 0x7E43, 0xDDDE, 0x7E46, 0xD9F0, 0x7E47, 0xE9A3,	0x7E52, 0xF1F9, 0x7E54, 0xF2C4, 0x7E55, 0xE0CB, 0x7E5E, 0xE9A4,
+	0x7E61, 0xE2B9, 0x7E69, 0xE3B1, 0x7E6A, 0xFCEB, 0x7E6B, 0xCDA8,	0x7E6D, 0xCCB6, 0x7E70, 0xF0DB, 0x7E79, 0xE6BA, 0x7E7C, 0xCDA9,
+	0x7E82, 0xF3C3, 0x7E8C, 0xE1D9, 0x7E8F, 0xEFAB, 0x7E93, 0xE7C5,	0x7E96, 0xE0E9, 0x7E98, 0xF3C5, 0x7E9B, 0xD4C0, 0x7E9C, 0xD5BF,
+	0x7F36, 0xDDAE, 0x7F38, 0xF9FC, 0x7F3A, 0xCCC0, 0x7F4C, 0xE5A2,	0x7F50, 0xCEB8, 0x7F54, 0xD8D2, 0x7F55, 0xF9D6, 0x7F6A, 0xF1AA,
+	0x7F6B, 0xCED1, 0x7F6E, 0xF6C7, 0x7F70, 0xDBEB, 0x7F72, 0xDFFE,	0x7F75, 0xD8E1, 0x7F77, 0xF7F3, 0x7F79, 0xD7E7, 0x7F85, 0xD4FE,
+	0x7F88, 0xD1BC, 0x7F8A, 0xE5CF, 0x7F8C, 0xCBB6, 0x7F8E, 0xDAB8,	0x7F94, 0xCDC4, 0x7F9A, 0xD6BE, 0x7F9E, 0xE2BA, 0x7FA4, 0xCFD8,
+	0x7FA8, 0xE0CC, 0x7FA9, 0xEBF9, 0x7FB2, 0xFDFD, 0x7FB8, 0xD7E8,	0x7FB9, 0xCBD8, 0x7FBD, 0xE9E2, 0x7FC1, 0xE8BA, 0x7FC5, 0xE3C7,
+	0x7FCA, 0xECCD, 0x7FCC, 0xECCE, 0x7FCE, 0xD6BF, 0x7FD2, 0xE3A7,	0x7FD4, 0xDFD6, 0x7FD5, 0xFDE8, 0x7FDF, 0xEEE1, 0x7FE0, 0xF6A8,
+	0x7FE1, 0xDDFD, 0x7FE9, 0xF8BB, 0x7FEB, 0xE8D1, 0x7FF0, 0xF9D7,	0x7FF9, 0xCEEE, 0x7FFC, 0xECCF, 0x8000, 0xE9A5, 0x8001, 0xD6D5,
+	0x8003, 0xCDC5, 0x8005, 0xEDBA, 0x8006, 0xD1BD, 0x8009, 0xCFBE,	0x800C, 0xECBB, 0x8010, 0xD2B1, 0x8015, 0xCCE9, 0x8017, 0xD9C4,
+	0x8018, 0xE9FC, 0x802D, 0xD1BE, 0x8033, 0xECBC, 0x8036, 0xE5AD,	0x803D, 0xF7B0, 0x803F, 0xCCEA, 0x8043, 0xD3C4, 0x8046, 0xD6C0,
+	0x804A, 0xD6FD, 0x8056, 0xE1A1, 0x8058, 0xDEBD, 0x805A, 0xF6A9,	0x805E, 0xDAA4, 0x806F, 0xD6A4, 0x8070, 0xF5C6, 0x8072, 0xE1A2,
+	0x8073, 0xE9C6, 0x8077, 0xF2C5, 0x807D, 0xF4E9, 0x807E, 0xD6EC,	0x807F, 0xEBD3, 0x8084, 0xECBD, 0x8085, 0xE2DC, 0x8086, 0xDEEB,
+	0x8087, 0xF0DC, 0x8089, 0xEBBF, 0x808B, 0xD7CE, 0x808C, 0xD1BF,	0x8096, 0xF5AB, 0x809B, 0xF9FD, 0x809D, 0xCADC, 0x80A1, 0xCDC6,
+	0x80A2, 0xF2B6, 0x80A5, 0xDDFE, 0x80A9, 0xCCB7, 0x80AA, 0xDBB8,	0x80AF, 0xD0E9, 0x80B1, 0xCEDD, 0x80B2, 0xEBC0, 0x80B4, 0xFDA2,
+	0x80BA, 0xF8CB, 0x80C3, 0xEAD6, 0x80C4, 0xF1B0, 0x80CC, 0xDBCE,	0x80CE, 0xF7C3, 0x80DA, 0xDBCF, 0x80DB, 0xCBA4, 0x80DE, 0xF8E0,
+	0x80E1, 0xFBD7, 0x80E4, 0xEBCA, 0x80E5, 0xE0A1, 0x80F1, 0xCECD,	0x80F4, 0xD4DC, 0x80F8, 0xFDD8, 0x80FD, 0xD2F6, 0x8102, 0xF2B7,
+	0x8105, 0xFAF6, 0x8106, 0xF6AA, 0x8107, 0xFAF7, 0x8108, 0xD8E6,	0x810A, 0xF4B1, 0x8118, 0xE8D2, 0x811A, 0xCAC5, 0x811B, 0xCCEB,
+	0x8123, 0xE2EE, 0x8129, 0xE2BB, 0x812B, 0xF7AD, 0x812F, 0xF8E1,	0x8139, 0xF3EC, 0x813E, 0xDEA1, 0x814B, 0xE4FD, 0x814E, 0xE3EC,
+	0x8150, 0xDDAF, 0x8151, 0xDDB0, 0x8154, 0xCBB7, 0x8155, 0xE8D3,	0x8165, 0xE1A3, 0x8166, 0xD2E0, 0x816B, 0xF0FE, 0x8170, 0xE9A6,
+	0x8171, 0xCBF2, 0x8178, 0xEDF3, 0x8179, 0xDCD9, 0x817A, 0xE0CD,	0x817F, 0xF7DA, 0x8180, 0xDBB9, 0x8188, 0xCCAE, 0x818A, 0xDADB,
+	0x818F, 0xCDC7, 0x819A, 0xDDB1, 0x819C, 0xD8AF, 0x819D, 0xE3A3,	0x81A0, 0xCEEF, 0x81A3, 0xF2F3, 0x81A8, 0xF8B3, 0x81B3, 0xE0CE,
+	0x81B5, 0xF5FD, 0x81BA, 0xEBEC, 0x81BD, 0xD3C5, 0x81BE, 0xFCEC,	0x81BF, 0xD2DB, 0x81C0, 0xD4EB, 0x81C2, 0xDEA2, 0x81C6, 0xE5E6,
+	0x81CD, 0xF0B0, 0x81D8, 0xD5C4, 0x81DF, 0xEDF4, 0x81E3, 0xE3ED,	0x81E5, 0xE8C2, 0x81E7, 0xEDF5, 0x81E8, 0xD7FC, 0x81EA, 0xEDBB,
+	0x81ED, 0xF6AB, 0x81F3, 0xF2B8, 0x81F4, 0xF6C8, 0x81FA, 0xD3E6,	0x81FB, 0xF2DD, 0x81FC, 0xCFBF, 0x81FE, 0xEBAC, 0x8205, 0xCFC0,
+	0x8207, 0xE6A8, 0x8208, 0xFDE9, 0x820A, 0xCFC1, 0x820C, 0xE0DF,	0x820D, 0xDEEC, 0x8212, 0xE0A2, 0x821B, 0xF4BF, 0x821C, 0xE2EF,
+	0x821E, 0xD9F1, 0x821F, 0xF1C7, 0x8221, 0xCBB8, 0x822A, 0xF9FE,	0x822B, 0xDBBA, 0x822C, 0xDAF5, 0x8235, 0xF6EC, 0x8236, 0xDADC,
+	0x8237, 0xFAE4, 0x8239, 0xE0CF, 0x8240, 0xDDB2, 0x8245, 0xE6A9,	0x8247, 0xEFF3, 0x8259, 0xF3ED, 0x8264, 0xEBFA, 0x8266, 0xF9E6,
+	0x826E, 0xCADD, 0x826F, 0xD5DE, 0x8271, 0xCADE, 0x8272, 0xDFE4,	0x8276, 0xE6FD, 0x8278, 0xF5AC, 0x827E, 0xE4F5, 0x828B, 0xE9E3,
+	0x828D, 0xEDCB, 0x828E, 0xCFE4, 0x8292, 0xD8D3, 0x8299, 0xDDB3,	0x829A, 0xD4EC, 0x829D, 0xF2B9, 0x829F, 0xDFB7, 0x82A5, 0xCBCE,
+	0x82A6, 0xFBD8, 0x82A9, 0xD0D9, 0x82AC, 0xDDD2, 0x82AD, 0xF7F4,	0x82AE, 0xE7DC, 0x82AF, 0xE4A5, 0x82B1, 0xFCA3, 0x82B3, 0xDBBB,
+	0x82B7, 0xF2BA, 0x82B8, 0xE9FD, 0x82B9, 0xD0CA, 0x82BB, 0xF5D6,	0x82BC, 0xD9C5, 0x82BD, 0xE4B4, 0x82BF, 0xEDA7, 0x82D1, 0xEABD,
+	0x82D2, 0xE6FE, 0x82D4, 0xF7C4, 0x82D5, 0xF5AD, 0x82D7, 0xD9E0,	0x82DB, 0xCAB4, 0x82DE, 0xF8E2, 0x82DF, 0xCFC2, 0x82E1, 0xECBE,
+	0x82E5, 0xE5B4, 0x82E6, 0xCDC8, 0x82E7, 0xEEC8, 0x82F1, 0xE7C8,	0x82FD, 0xCDC9, 0x82FE, 0xF9B7, 0x8301, 0xF1E8, 0x8302, 0xD9F2,
+	0x8303, 0xDBF5, 0x8304, 0xCAB5, 0x8305, 0xD9C6, 0x8309, 0xD8C9,	0x8317, 0xD9AB, 0x8328, 0xEDBC, 0x832B, 0xD8D4, 0x832F, 0xDCDA,
+	0x8331, 0xE2BC, 0x8334, 0xFCED, 0x8335, 0xECE0, 0x8336, 0xD2FE,	0x8338, 0xE9C7, 0x8339, 0xE6AA, 0x8340, 0xE2F0, 0x8347, 0xFABB,
+	0x8349, 0xF5AE, 0x834A, 0xFBAA, 0x834F, 0xECFB, 0x8351, 0xECBF,	0x8352, 0xFCD8, 0x8373, 0xD4E5, 0x8377, 0xF9C3, 0x837B, 0xEEE2,
+	0x8389, 0xD7E9, 0x838A, 0xEDF6, 0x838E, 0xDEED, 0x8396, 0xCCEC,	0x8398, 0xE3EE, 0x839E, 0xE8D4, 0x83A2, 0xFAF8, 0x83A9, 0xDDB4,
+	0x83AA, 0xE4B5, 0x83AB, 0xD8B0, 0x83BD, 0xD8D5, 0x83C1, 0xF4EA,	0x83C5, 0xCEB9, 0x83C9, 0xD6E1, 0x83CA, 0xCFD2, 0x83CC, 0xD0B6,
+	0x83D3, 0xCEA2, 0x83D6, 0xF3EE, 0x83DC, 0xF3F8, 0x83E9, 0xDCCC,	0x83EB, 0xD0CB, 0x83EF, 0xFCA4, 0x83F0, 0xCDCA, 0x83F1, 0xD7D4,
+	0x83F2, 0xDEA3, 0x83F4, 0xE4E0, 0x83F9, 0xEEC9, 0x83FD, 0xE2DD,	0x8403, 0xF5FE, 0x8404, 0xD4AC, 0x840A, 0xD5D1, 0x840C, 0xD8F0,
+	0x840D, 0xF8C3, 0x840E, 0xEAD7, 0x8429, 0xF5D7, 0x842C, 0xD8BF,	0x8431, 0xFDC0, 0x8438, 0xEBAD, 0x843D, 0xD5AA, 0x8449, 0xE7A8,
+	0x8457, 0xEECA, 0x845B, 0xCAE7, 0x8461, 0xF8E3, 0x8463, 0xD4DD,	0x8466, 0xEAD8, 0x846B, 0xFBD9, 0x846C, 0xEDF7, 0x846F, 0xE5B5,
+	0x8475, 0xD0AD, 0x847A, 0xF1F1, 0x8490, 0xE2BD, 0x8494, 0xE3C8,	0x8499, 0xD9D5, 0x849C, 0xDFAA, 0x84A1, 0xDBBC, 0x84B2, 0xF8E4,
+	0x84B8, 0xF1FA, 0x84BB, 0xE5B6, 0x84BC, 0xF3EF, 0x84BF, 0xFBDA,	0x84C0, 0xE1E0, 0x84C2, 0xD9AC, 0x84C4, 0xF5EB, 0x84C6, 0xE0B6,
+	0x84C9, 0xE9C8, 0x84CB, 0xCBCF, 0x84CD, 0xE3C9, 0x84D1, 0xDEEE,	0x84DA, 0xE2BE, 0x84EC, 0xDCEF, 0x84EE, 0xD6A5, 0x84F4, 0xE2F1,
+	0x84FC, 0xD6FE, 0x8511, 0xD9A1, 0x8513, 0xD8C0, 0x8514, 0xDCDB,	0x8517, 0xEDBD, 0x8518, 0xDFB8, 0x851A, 0xEAA5, 0x851E, 0xD7AD,
+	0x8521, 0xF3F9, 0x8523, 0xEDF8, 0x8525, 0xF5C7, 0x852C, 0xE1CA,	0x852D, 0xEBE3, 0x852F, 0xF2DE, 0x853D, 0xF8CC, 0x853F, 0xEAD9,
+	0x8541, 0xD3C6, 0x8543, 0xDBE6, 0x8549, 0xF5AF, 0x854E, 0xCEF0,	0x8553, 0xE9FE, 0x8559, 0xFBB6, 0x8563, 0xE2F2, 0x8568, 0xCFF2,
+	0x8569, 0xF7B9, 0x856A, 0xD9F3, 0x856D, 0xE1CB, 0x8584, 0xDADD,	0x8587, 0xDAB9, 0x858F, 0xEBFB, 0x8591, 0xCBB9, 0x8594, 0xEDF9,
+	0x859B, 0xE0E0, 0x85A6, 0xF4C0, 0x85A8, 0xFDBC, 0x85A9, 0xDFB1,	0x85AA, 0xE3EF, 0x85AF, 0xE0A3, 0x85B0, 0xFDB9, 0x85BA, 0xF0B1,
+	0x85C1, 0xCDCB, 0x85C9, 0xEDBE, 0x85CD, 0xD5C0, 0x85CE, 0xE3F0,	0x85CF, 0xEDFA, 0x85D5, 0xE9E4, 0x85DC, 0xD5ED, 0x85DD, 0xE7DD,
+	0x85E4, 0xD4F6, 0x85E5, 0xE5B7, 0x85E9, 0xDBE7, 0x85EA, 0xE2BF,	0x85F7, 0xEECB, 0x85FA, 0xD7F4, 0x85FB, 0xF0DD, 0x85FF, 0xCEAB,
+	0x8602, 0xE7DE, 0x8606, 0xD6D6, 0x8607, 0xE1CC, 0x860A, 0xE8B3,	0x8616, 0xE5EE, 0x8617, 0xDCA2, 0x861A, 0xE0D0, 0x862D, 0xD5B5,
+	0x863F, 0xD5A1, 0x864E, 0xFBDB, 0x8650, 0xF9CB, 0x8654, 0xCBF3,	0x8655, 0xF4A5, 0x865B, 0xFAC8, 0x865C, 0xD6D7, 0x865E, 0xE9E5,
+	0x865F, 0xFBDC, 0x8667, 0xFDD0, 0x8679, 0xFBF6, 0x868A, 0xDAA5,	0x868C, 0xDBBD, 0x8693, 0xECE2, 0x86A3, 0xCDF7, 0x86A4, 0xF0DE,
+	0x86A9, 0xF6C9, 0x86C7, 0xDEEF, 0x86CB, 0xD3B1, 0x86D4, 0xFCEE,	0x86D9, 0xE8C3, 0x86DB, 0xF1C8, 0x86DF, 0xCEF1, 0x86E4, 0xF9ED,
+	0x86ED, 0xF2F4, 0x86FE, 0xE4B6, 0x8700, 0xF5B9, 0x8702, 0xDCF0,	0x8703, 0xE3F1, 0x8708, 0xE8A5, 0x8718, 0xF2BB, 0x871A, 0xDEA4,
+	0x871C, 0xDACC, 0x874E, 0xCAE9, 0x8755, 0xE3DA, 0x8757, 0xFCD9,	0x875F, 0xEADA, 0x8766, 0xF9C4, 0x8768, 0xE3A4, 0x8774, 0xFBDD,
+	0x8776, 0xEFCA, 0x8778, 0xE8C4, 0x8782, 0xD5CC, 0x878D, 0xEBD7,	0x879F, 0xD9AD, 0x87A2, 0xFBAB, 0x87B3, 0xD3D9, 0x87BA, 0xD5A2,
+	0x87C4, 0xF6DE, 0x87E0, 0xDAF6, 0x87EC, 0xE0D1, 0x87EF, 0xE9A8,	0x87F2, 0xF5F9, 0x87F9, 0xFAAF, 0x87FB, 0xEBFC, 0x87FE, 0xE0EA,
+	0x8805, 0xE3B2, 0x881F, 0xD5C5, 0x8822, 0xF1E3, 0x8823, 0xD5EE,	0x8831, 0xCDCC, 0x8836, 0xEDD9, 0x883B, 0xD8C1, 0x8840, 0xFAEC,
+	0x8846, 0xF1EB, 0x884C, 0xFABC, 0x884D, 0xE6E2, 0x8852, 0xFAE5,	0x8853, 0xE2FA, 0x8857, 0xCAB6, 0x8859, 0xE4B7, 0x885B, 0xEADB,
+	0x885D, 0xF5FA, 0x8861, 0xFBAC, 0x8862, 0xCFC3, 0x8863, 0xEBFD,	0x8868, 0xF8FA, 0x886B, 0xDFB9, 0x8870, 0xE1F1, 0x8872, 0xD2A4,
+	0x8877, 0xF5FB, 0x887E, 0xD0DA, 0x887F, 0xD0DB, 0x8881, 0xEABE,	0x8882, 0xD9B1, 0x8888, 0xCAB7, 0x888B, 0xD3E7, 0x888D, 0xF8E5,
+	0x8892, 0xD3B2, 0x8896, 0xE2C0, 0x8897, 0xF2DF, 0x889E, 0xCDE5,	0x88AB, 0xF9AC, 0x88B4, 0xCDCD, 0x88C1, 0xEEAE, 0x88C2, 0xD6AE,
+	0x88CF, 0xD7EA, 0x88D4, 0xE7E0, 0x88D5, 0xEBAE, 0x88D9, 0xCFD9,	0x88DC, 0xDCCD, 0x88DD, 0xEDFB, 0x88DF, 0xDEF0, 0x88E1, 0xD7EB,
+	0x88E8, 0xDEA5, 0x88F3, 0xDFD7, 0x88F4, 0xDBD0, 0x88F5, 0xDBD1,	0x88F8, 0xD5A3, 0x88FD, 0xF0B2, 0x8907, 0xDCDC, 0x8910, 0xCAE8,
+	0x8912, 0xF8E6, 0x8913, 0xDCCE, 0x8918, 0xEADC, 0x8919, 0xDBD2,	0x8925, 0xE9B3, 0x892A, 0xF7DB, 0x8936, 0xE3A8, 0x8938, 0xD7AE,
+	0x893B, 0xE0E1, 0x8941, 0xCBBA, 0x8944, 0xE5D1, 0x895F, 0xD0DC,	0x8964, 0xD5C1, 0x896A, 0xD8CA, 0x8972, 0xE3A9, 0x897F, 0xE0A4,
+	0x8981, 0xE9A9, 0x8983, 0xD3C7, 0x8986, 0xDCDD, 0x8987, 0xF8AE,	0x898B, 0xCCB8, 0x898F, 0xD0AE, 0x8993, 0xD8F2, 0x8996, 0xE3CA,
+	0x89A1, 0xCCAF, 0x89A9, 0xD4AD, 0x89AA, 0xF6D1, 0x89B2, 0xD0CC,	0x89BA, 0xCAC6, 0x89BD, 0xD5C2, 0x89C0, 0xCEBA, 0x89D2, 0xCAC7,
+	0x89E3, 0xFAB0, 0x89F4, 0xDFD8, 0x89F8, 0xF5BA, 0x8A00, 0xE5EB,	0x8A02, 0xEFF4, 0x8A03, 0xDDB5, 0x8A08, 0xCDAA, 0x8A0A, 0xE3F2,
+	0x8A0C, 0xFBF7, 0x8A0E, 0xF7D0, 0x8A13, 0xFDBA, 0x8A16, 0xFDE1,	0x8A17, 0xF6FE, 0x8A18, 0xD1C0, 0x8A1B, 0xE8C5, 0x8A1D, 0xE4B8,
+	0x8A1F, 0xE1E8, 0x8A23, 0xCCC1, 0x8A25, 0xD2ED, 0x8A2A, 0xDBBE,	0x8A2D, 0xE0E2, 0x8A31, 0xFAC9, 0x8A34, 0xE1CD, 0x8A36, 0xCAB8,
+	0x8A3A, 0xF2E0, 0x8A3B, 0xF1C9, 0x8A50, 0xDEF1, 0x8A54, 0xF0DF,	0x8A55, 0xF8C4, 0x8A5B, 0xEECC, 0x8A5E, 0xDEF2, 0x8A60, 0xE7C9,
+	0x8A62, 0xE2F3, 0x8A63, 0xE7E1, 0x8A66, 0xE3CB, 0x8A69, 0xE3CC,	0x8A6D, 0xCFF8, 0x8A6E, 0xEFAC, 0x8A70, 0xFDFE, 0x8A71, 0xFCA5,
+	0x8A72, 0xFAB1, 0x8A73, 0xDFD9, 0x8A75, 0xE0D2, 0x8A79, 0xF4DA,	0x8A85, 0xF1CA, 0x8A87, 0xCEA3, 0x8A8C, 0xF2BC, 0x8A8D, 0xECE3,
+	0x8A93, 0xE0A5, 0x8A95, 0xF7AB, 0x8A98, 0xEBAF, 0x8A9E, 0xE5DE,	0x8AA0, 0xE1A4, 0x8AA1, 0xCDAB, 0x8AA3, 0xD9F4, 0x8AA4, 0xE8A6,
+	0x8AA5, 0xCDCE, 0x8AA6, 0xE1E9, 0x8AA8, 0xFCEF, 0x8AAA, 0xE0E3,	0x8AB0, 0xE2C1, 0x8AB2, 0xCEA4, 0x8AB9, 0xDEA6, 0x8ABC, 0xEBFE,
+	0x8ABE, 0xEBDD, 0x8ABF, 0xF0E0, 0x8AC2, 0xF4DB, 0x8AC4, 0xE2F4,	0x8AC7, 0xD3C8, 0x8ACB, 0xF4EB, 0x8ACD, 0xEEB5, 0x8ACF, 0xF5D8,
+	0x8AD2, 0xD5DF, 0x8AD6, 0xD6E5, 0x8ADB, 0xEBB0, 0x8ADC, 0xF4E3,	0x8AE1, 0xE3CD, 0x8AE6, 0xF4F4, 0x8AE7, 0xFAB2, 0x8AEA, 0xEFF5,
+	0x8AEB, 0xCADF, 0x8AED, 0xEBB1, 0x8AEE, 0xEDBF, 0x8AF1, 0xFDC9,	0x8AF6, 0xE4A6, 0x8AF7, 0xF9A4, 0x8AF8, 0xF0B3, 0x8AFA, 0xE5EC,
+	0x8AFE, 0xD1E7, 0x8B00, 0xD9C7, 0x8B01, 0xE4D7, 0x8B02, 0xEADD,	0x8B04, 0xD4F7, 0x8B0E, 0xDABA, 0x8B10, 0xDACD, 0x8B14, 0xF9CC,
+	0x8B16, 0xE1DA, 0x8B17, 0xDBBF, 0x8B19, 0xCCC5, 0x8B1A, 0xECD0,	0x8B1B, 0xCBBB, 0x8B1D, 0xDEF3, 0x8B20, 0xE9AA, 0x8B28, 0xD9C8,
+	0x8B2B, 0xEEE3, 0x8B2C, 0xD7BD, 0x8B33, 0xCFC4, 0x8B39, 0xD0CD,	0x8B41, 0xFCA6, 0x8B49, 0xF1FB, 0x8B4E, 0xFDD2, 0x8B4F, 0xD1C1,
+	0x8B58, 0xE3DB, 0x8B5A, 0xD3C9, 0x8B5C, 0xDCCF, 0x8B66, 0xCCED,	0x8B6C, 0xDEA7, 0x8B6F, 0xE6BB, 0x8B70, 0xECA1, 0x8B74, 0xCCB9,
+	0x8B77, 0xFBDE, 0x8B7D, 0xE7E2, 0x8B80, 0xD4C1, 0x8B8A, 0xDCA8,	0x8B90, 0xE2C2, 0x8B92, 0xF3D8, 0x8B93, 0xE5D3, 0x8B96, 0xF3D9,
+	0x8B9A, 0xF3C6, 0x8C37, 0xCDDB, 0x8C3F, 0xCDAC, 0x8C41, 0xFCC3,	0x8C46, 0xD4E7, 0x8C48, 0xD1C2, 0x8C4A, 0xF9A5, 0x8C4C, 0xE8D5,
+	0x8C55, 0xE3CE, 0x8C5A, 0xD4CA, 0x8C61, 0xDFDA, 0x8C6A, 0xFBDF,	0x8C6B, 0xE7E3, 0x8C79, 0xF8FB, 0x8C7A, 0xE3CF, 0x8C82, 0xF5B0,
+	0x8C8A, 0xD8E7, 0x8C8C, 0xD9C9, 0x8C9D, 0xF8AF, 0x8C9E, 0xEFF6,	0x8CA0, 0xDDB6, 0x8CA1, 0xEEAF, 0x8CA2, 0xCDF8, 0x8CA7, 0xDEB8,
+	0x8CA8, 0xFCA7, 0x8CA9, 0xF7FC, 0x8CAA, 0xF7B1, 0x8CAB, 0xCEBB,	0x8CAC, 0xF4A1, 0x8CAF, 0xEECD, 0x8CB0, 0xE1AE, 0x8CB3, 0xECC3,
+	0x8CB4, 0xCFFE, 0x8CB6, 0xF8BF, 0x8CB7, 0xD8E2, 0x8CB8, 0xD3E8,	0x8CBB, 0xDEA8, 0x8CBC, 0xF4E4, 0x8CBD, 0xECC2, 0x8CBF, 0xD9F5,
+	0x8CC0, 0xF9C5, 0x8CC1, 0xDDD3, 0x8CC2, 0xD6F1, 0x8CC3, 0xECFC,	0x8CC4, 0xFCF0, 0x8CC7, 0xEDC0, 0x8CC8, 0xCAB9, 0x8CCA, 0xEEE4,
+	0x8CD1, 0xF2E1, 0x8CD3, 0xDEB9, 0x8CDA, 0xD6F2, 0x8CDC, 0xDEF4,	0x8CDE, 0xDFDB, 0x8CE0, 0xDBD3, 0x8CE2, 0xFAE7, 0x8CE3, 0xD8E3,
+	0x8CE4, 0xF4C1, 0x8CE6, 0xDDB7, 0x8CEA, 0xF2F5, 0x8CED, 0xD4AE,	0x8CF4, 0xD6F3, 0x8CFB, 0xDDB8, 0x8CFC, 0xCFC5, 0x8CFD, 0xDFDF,
+	0x8D04, 0xF2BE, 0x8D05, 0xF6A1, 0x8D07, 0xEBCB, 0x8D08, 0xF1FC,	0x8D0A, 0xF3C7, 0x8D0D, 0xE0EB, 0x8D13, 0xEDFC, 0x8D16, 0xE1DB,
+	0x8D64, 0xEEE5, 0x8D66, 0xDEF5, 0x8D6B, 0xFAD3, 0x8D70, 0xF1CB,	0x8D73, 0xD0AF, 0x8D74, 0xDDB9, 0x8D77, 0xD1C3, 0x8D85, 0xF5B1,
+	0x8D8A, 0xEAC6, 0x8D99, 0xF0E1, 0x8DA3, 0xF6AC, 0x8DA8, 0xF5D9,	0x8DB3, 0xF0EB, 0x8DBA, 0xDDBA, 0x8DBE, 0xF2BF, 0x8DC6, 0xF7C5,
+	0x8DCB, 0xDBA2, 0x8DCC, 0xF2F6, 0x8DCF, 0xCABA, 0x8DDB, 0xF7F5,	0x8DDD, 0xCBE5, 0x8DE1, 0xEEE6, 0x8DE3, 0xE0D3, 0x8DE8, 0xCEA5,
+	0x8DEF, 0xD6D8, 0x8DF3, 0xD4AF, 0x8E0A, 0xE9C9, 0x8E0F, 0xD3CE,	0x8E10, 0xF4C2, 0x8E1E, 0xCBE6, 0x8E2A, 0xF1A1, 0x8E30, 0xEBB2,
+	0x8E35, 0xF1A2, 0x8E42, 0xEBB3, 0x8E44, 0xF0B4, 0x8E47, 0xCBF4,	0x8E48, 0xD4B0, 0x8E49, 0xF3B2, 0x8E4A, 0xFBB7, 0x8E59, 0xF5EC,
+	0x8E5F, 0xEEE7, 0x8E60, 0xF4B2, 0x8E74, 0xF5ED, 0x8E76, 0xCFF3,	0x8E81, 0xF0E2, 0x8E87, 0xEECE, 0x8E8A, 0xF1CC, 0x8E8D, 0xE5B8,
+	0x8EAA, 0xD7F5, 0x8EAB, 0xE3F3, 0x8EAC, 0xCFE5, 0x8EC0, 0xCFC6,	0x8ECA, 0xF3B3, 0x8ECB, 0xE4D8, 0x8ECC, 0xCFF9, 0x8ECD, 0xCFDA,
+	0x8ED2, 0xFACD, 0x8EDF, 0xE6E3, 0x8EEB, 0xF2E2, 0x8EF8, 0xF5EE,	0x8EFB, 0xCABB, 0x8EFE, 0xE3DC, 0x8F03, 0xCEF2, 0x8F05, 0xD6D9,
+	0x8F09, 0xEEB0, 0x8F12, 0xF4E5, 0x8F13, 0xD8C2, 0x8F14, 0xDCD0,	0x8F15, 0xCCEE, 0x8F1B, 0xD5E0, 0x8F1C, 0xF6CA, 0x8F1D, 0xFDCA,
+	0x8F1E, 0xD8D6, 0x8F1F, 0xF4CF, 0x8F26, 0xD6A6, 0x8F27, 0xDCBE,	0x8F29, 0xDBD4, 0x8F2A, 0xD7C7, 0x8F2F, 0xF2FE, 0x8F33, 0xF1CD,
+	0x8F38, 0xE2C3, 0x8F39, 0xDCDE, 0x8F3B, 0xDCDF, 0x8F3E, 0xEFAD,	0x8F3F, 0xE6AB, 0x8F44, 0xF9DD, 0x8F45, 0xEABF, 0x8F49, 0xEFAE,
+	0x8F4D, 0xF4D0, 0x8F4E, 0xCEF3, 0x8F5D, 0xE6AC, 0x8F5F, 0xCEDE,	0x8F62, 0xD5F9, 0x8F9B, 0xE3F4, 0x8F9C, 0xCDD0, 0x8FA3, 0xD5B8,
+	0x8FA6, 0xF7FD, 0x8FA8, 0xDCA9, 0x8FAD, 0xDEF6, 0x8FAF, 0xDCAA,	0x8FB0, 0xF2E3, 0x8FB1, 0xE9B4, 0x8FB2, 0xD2DC, 0x8FC2, 0xE9E6,
+	0x8FC5, 0xE3F6, 0x8FCE, 0xE7CA, 0x8FD1, 0xD0CE, 0x8FD4, 0xDAF7,	0x8FE6, 0xCABC, 0x8FEA, 0xEEE8, 0x8FEB, 0xDADE, 0x8FED, 0xF2F7,
+	0x8FF0, 0xE2FB, 0x8FF2, 0xCCA6, 0x8FF7, 0xDABB, 0x8FF9, 0xEEE9,	0x8FFD, 0xF5DA, 0x9000, 0xF7DC, 0x9001, 0xE1EA, 0x9002, 0xCEC1,
+	0x9003, 0xD4B1, 0x9005, 0xFDB1, 0x9006, 0xE6BD, 0x9008, 0xFBAD,	0x900B, 0xF8E7, 0x900D, 0xE1CE, 0x900F, 0xF7E2, 0x9010, 0xF5EF,
+	0x9011, 0xCFC7, 0x9014, 0xD4B2, 0x9015, 0xCCEF, 0x9017, 0xD4E8,	0x9019, 0xEECF, 0x901A, 0xF7D7, 0x901D, 0xE0A6, 0x901E, 0xD6C1,
+	0x901F, 0xE1DC, 0x9020, 0xF0E3, 0x9021, 0xF1E4, 0x9022, 0xDCF1,	0x9023, 0xD6A7, 0x902E, 0xF4F5, 0x9031, 0xF1CE, 0x9032, 0xF2E4,
+	0x9035, 0xD0B0, 0x9038, 0xECEF, 0x903C, 0xF9BA, 0x903E, 0xEBB5,	0x9041, 0xD4ED, 0x9042, 0xE2C4, 0x9047, 0xE9E7, 0x904A, 0xEBB4,
+	0x904B, 0xEAA1, 0x904D, 0xF8BC, 0x904E, 0xCEA6, 0x9050, 0xF9C6,	0x9051, 0xFCDA, 0x9053, 0xD4B3, 0x9054, 0xD3B9, 0x9055, 0xEADE,
+	0x9059, 0xE9AB, 0x905C, 0xE1E1, 0x905D, 0xD3CF, 0x905E, 0xF4F6,	0x9060, 0xEAC0, 0x9061, 0xE1CF, 0x9063, 0xCCBA, 0x9069, 0xEEEA,
+	0x906D, 0xF0E4, 0x906E, 0xF3B4, 0x906F, 0xD4EE, 0x9072, 0xF2C0,	0x9075, 0xF1E5, 0x9077, 0xF4C3, 0x9078, 0xE0D4, 0x907A, 0xEBB6,
+	0x907C, 0xD7A1, 0x907D, 0xCBE8, 0x907F, 0xF9AD, 0x9080, 0xE9AD,	0x9081, 0xD8E4, 0x9082, 0xFAB3, 0x9083, 0xE2C5, 0x9084, 0xFCBD,
+	0x9087, 0xECC4, 0x9088, 0xD8B1, 0x908A, 0xDCAB, 0x908F, 0xD5A4,	0x9091, 0xEBE9, 0x9095, 0xE8BB, 0x9099, 0xD8D7, 0x90A2, 0xFBAE,
+	0x90A3, 0xD1E1, 0x90A6, 0xDBC0, 0x90A8, 0xF5BE, 0x90AA, 0xDEF7,	0x90AF, 0xCAFB, 0x90B0, 0xF7C6, 0x90B1, 0xCFC8, 0x90B5, 0xE1D0,
+	0x90B8, 0xEED0, 0x90C1, 0xE9F4, 0x90CA, 0xCEF4, 0x90DE, 0xD5CD,	0x90E1, 0xCFDB, 0x90E8, 0xDDBB, 0x90ED, 0xCEAC, 0x90F5, 0xE9E8,
+	0x90FD, 0xD4B4, 0x9102, 0xE4C7, 0x9112, 0xF5DB, 0x9115, 0xFAC1,	0x9119, 0xDEA9, 0x9127, 0xD4F8, 0x912D, 0xEFF7, 0x9132, 0xD3B3,
+	0x9149, 0xEBB7, 0x914A, 0xEFF8, 0x914B, 0xF5DC, 0x914C, 0xEDCC,	0x914D, 0xDBD5, 0x914E, 0xF1CF, 0x9152, 0xF1D0, 0x9162, 0xF5B2,
+	0x9169, 0xD9AE, 0x916A, 0xD5AC, 0x916C, 0xE2C6, 0x9175, 0xFDA3,	0x9177, 0xFBE5, 0x9178, 0xDFAB, 0x9187, 0xE2F5, 0x9189, 0xF6AD,
+	0x918B, 0xF5B3, 0x918D, 0xF0B5, 0x9192, 0xE1A5, 0x919C, 0xF5DD,	0x91AB, 0xECA2, 0x91AC, 0xEDFD, 0x91AE, 0xF5B4, 0x91AF, 0xFBB8,
+	0x91B1, 0xDBA3, 0x91B4, 0xD6CA, 0x91B5, 0xCBD9, 0x91C0, 0xE5D4,	0x91C7, 0xF3FA, 0x91C9, 0xEBB8, 0x91CB, 0xE0B7, 0x91CC, 0xD7EC,
+	0x91CD, 0xF1EC, 0x91CE, 0xE5AF, 0x91CF, 0xD5E1, 0x91D0, 0xD7ED,	0x91D1, 0xD1D1, 0x91D7, 0xE1F2, 0x91D8, 0xEFF9, 0x91DC, 0xDDBC,
+	0x91DD, 0xF6DC, 0x91E3, 0xF0E5, 0x91E7, 0xF4C4, 0x91EA, 0xE9E9,	0x91F5, 0xF3FB, 0x920D, 0xD4EF, 0x9210, 0xCCA2, 0x9211, 0xF7FE,
+	0x9212, 0xDFBC, 0x9217, 0xEBCD, 0x921E, 0xD0B7, 0x9234, 0xD6C2,	0x923A, 0xE8AD, 0x923F, 0xEFAF, 0x9240, 0xCBA5, 0x9245, 0xCBE9,
+	0x9249, 0xFAE8, 0x9257, 0xCCC6, 0x925B, 0xE6E7, 0x925E, 0xEAC7,	0x9262, 0xDBA4, 0x9264, 0xCFC9, 0x9265, 0xE2FC, 0x9266, 0xEFFA,
+	0x9280, 0xEBDE, 0x9283, 0xF5C8, 0x9285, 0xD4DE, 0x9291, 0xE0D5,	0x9293, 0xEFB0, 0x9296, 0xE2C7, 0x9298, 0xD9AF, 0x929C, 0xF9E7,
+	0x92B3, 0xE7E5, 0x92B6, 0xCFCA, 0x92B7, 0xE1D1, 0x92B9, 0xE2C8,	0x92CC, 0xEFFB, 0x92CF, 0xFAF9, 0x92D2, 0xDCF2, 0x92E4, 0xE0A7,
+	0x92EA, 0xF8E8, 0x92F8, 0xCBEA, 0x92FC, 0xCBBC, 0x9304, 0xD6E2,	0x9310, 0xF5DE, 0x9318, 0xF5DF, 0x931A, 0xEEB6, 0x931E, 0xE2F6,
+	0x931F, 0xD3CA, 0x9320, 0xEFFC, 0x9321, 0xD1C4, 0x9322, 0xEFB1,	0x9324, 0xD1C5, 0x9326, 0xD0DE, 0x9328, 0xD9E1, 0x932B, 0xE0B8,
+	0x932E, 0xCDD1, 0x932F, 0xF3B9, 0x9348, 0xE7CC, 0x934A, 0xD6A8,	0x934B, 0xCEA7, 0x934D, 0xD4B5, 0x9354, 0xE4C8, 0x935B, 0xD3B4,
+	0x936E, 0xEBB9, 0x9375, 0xCBF5, 0x937C, 0xF6DD, 0x937E, 0xF1A3,	0x938C, 0xCCC7, 0x9394, 0xE9CA, 0x9396, 0xE1F0, 0x939A, 0xF5E0,
+	0x93A3, 0xFBAF, 0x93A7, 0xCBD1, 0x93AC, 0xFBE0, 0x93AD, 0xF2E5,	0x93B0, 0xECF0, 0x93C3, 0xF0EC, 0x93D1, 0xEEEB, 0x93DE, 0xE9CB,
+	0x93E1, 0xCCF0, 0x93E4, 0xD7AF, 0x93F6, 0xF3A1, 0x9404, 0xFCF5,	0x9418, 0xF1A4, 0x9425, 0xE0D6, 0x942B, 0xEFB2, 0x9435, 0xF4D1,
+	0x9438, 0xF7A1, 0x9444, 0xF1D1, 0x9451, 0xCAFC, 0x9452, 0xCAFD,	0x945B, 0xCECE, 0x947D, 0xF3C8, 0x947F, 0xF3BA, 0x9577, 0xEDFE,
+	0x9580, 0xDAA6, 0x9583, 0xE0EC, 0x9589, 0xF8CD, 0x958B, 0xCBD2,	0x958F, 0xEBCE, 0x9591, 0xF9D8, 0x9592, 0xF9D9, 0x9593, 0xCAE0,
+	0x9594, 0xDACA, 0x9598, 0xCBA6, 0x95A3, 0xCAC8, 0x95A4, 0xF9EE,	0x95A5, 0xDBEC, 0x95A8, 0xD0B1, 0x95AD, 0xD5EF, 0x95B1, 0xE6F3,
+	0x95BB, 0xE7A2, 0x95BC, 0xE4D9, 0x95C7, 0xE4E1, 0x95CA, 0xFCC4,	0x95D4, 0xF9EF, 0x95D5, 0xCFF4, 0x95D6, 0xF7E6, 0x95DC, 0xCEBC,
+	0x95E1, 0xF4C5, 0x95E2, 0xDCA3, 0x961C, 0xDDBD, 0x9621, 0xF4C6,	0x962A, 0xF8A1, 0x962E, 0xE8D6, 0x9632, 0xDBC1, 0x963B, 0xF0E6,
+	0x963F, 0xE4B9, 0x9640, 0xF6ED, 0x9642, 0xF9AE, 0x9644, 0xDDBE,	0x964B, 0xD7B0, 0x964C, 0xD8E8, 0x964D, 0xCBBD, 0x9650, 0xF9DA,
+	0x965B, 0xF8CE, 0x965C, 0xF9F0, 0x965D, 0xE0ED, 0x965E, 0xE3B3,	0x965F, 0xF4B3, 0x9662, 0xEAC2, 0x9663, 0xF2E6, 0x9664, 0xF0B6,
+	0x966A, 0xDBD6, 0x9670, 0xEBE4, 0x9673, 0xF2E7, 0x9675, 0xD7D5,	0x9676, 0xD4B6, 0x9677, 0xF9E8, 0x9678, 0xD7C1, 0x967D, 0xE5D5,
+	0x9685, 0xE9EA, 0x9686, 0xD7CC, 0x968A, 0xD3E9, 0x968B, 0xE2C9,	0x968D, 0xFCDB, 0x968E, 0xCDAD, 0x9694, 0xCCB0, 0x9695, 0xEAA2,
+	0x9698, 0xE4F6, 0x9699, 0xD0C0, 0x969B, 0xF0B7, 0x969C, 0xEEA1,	0x96A3, 0xD7F6, 0x96A7, 0xE2CA, 0x96A8, 0xE2CB, 0x96AA, 0xFACF,
+	0x96B1, 0xEBDF, 0x96B7, 0xD6CB, 0x96BB, 0xF4B4, 0x96C0, 0xEDCD,	0x96C1, 0xE4D2, 0x96C4, 0xEAA9, 0x96C5, 0xE4BA, 0x96C6, 0xF3A2,
+	0x96C7, 0xCDD2, 0x96C9, 0xF6CB, 0x96CB, 0xF1E6, 0x96CC, 0xEDC1,	0x96CD, 0xE8BC, 0x96CE, 0xEED1, 0x96D5, 0xF0E7, 0x96D6, 0xE2CC,
+	0x96D9, 0xE4AA, 0x96DB, 0xF5E1, 0x96DC, 0xEDDA, 0x96E2, 0xD7EE,	0x96E3, 0xD1F1, 0x96E8, 0xE9EB, 0x96E9, 0xE9EC, 0x96EA, 0xE0E4,
+	0x96EF, 0xDAA7, 0x96F0, 0xDDD4, 0x96F2, 0xEAA3, 0x96F6, 0xD6C3,	0x96F7, 0xD6F4, 0x96F9, 0xDADF, 0x96FB, 0xEFB3, 0x9700, 0xE2CD,
+	0x9706, 0xEFFD, 0x9707, 0xF2E8, 0x9711, 0xEFC5, 0x9713, 0xE7E7,	0x9716, 0xD7FD, 0x9719, 0xE7CE, 0x971C, 0xDFDC, 0x971E, 0xF9C7,
+	0x9727, 0xD9F6, 0x9730, 0xDFAC, 0x9732, 0xD6DA, 0x9739, 0xDCA4,	0x973D, 0xF0B8, 0x9742, 0xD5FA, 0x9744, 0xE4F7, 0x9748, 0xD6C4,
+	0x9751, 0xF4EC, 0x9756, 0xEFFE, 0x975C, 0xF0A1, 0x975E, 0xDEAA,	0x9761, 0xDABC, 0x9762, 0xD8FC, 0x9769, 0xFAD4, 0x976D, 0xECE5,
+	0x9774, 0xFCA8, 0x9777, 0xECE6, 0x977A, 0xD8CB, 0x978B, 0xFBB9,	0x978D, 0xE4D3, 0x978F, 0xCDF9, 0x97A0, 0xCFD3, 0x97A8, 0xCAEA,
+	0x97AB, 0xCFD4, 0x97AD, 0xF8BD, 0x97C6, 0xF4C7, 0x97CB, 0xEADF,	0x97D3, 0xF9DB, 0x97DC, 0xD4B7, 0x97F3, 0xEBE5, 0x97F6, 0xE1D2,
+	0x97FB, 0xEAA4, 0x97FF, 0xFAC2, 0x9800, 0xFBE1, 0x9801, 0xFAED,	0x9802, 0xF0A2, 0x9803, 0xCCF1, 0x9805, 0xFAA3, 0x9806, 0xE2F7,
+	0x9808, 0xE2CE, 0x980A, 0xE9F5, 0x980C, 0xE1EB, 0x9810, 0xE7E8,	0x9811, 0xE8D7, 0x9812, 0xDAF8, 0x9813, 0xD4CB, 0x9817, 0xF7F6,
+	0x9818, 0xD6C5, 0x982D, 0xD4E9, 0x9830, 0xFAFA, 0x9838, 0xCCF2,	0x9839, 0xF7DD, 0x983B, 0xDEBA, 0x9846, 0xCEA8, 0x984C, 0xF0B9,
+	0x984D, 0xE4FE, 0x984E, 0xE4C9, 0x9854, 0xE4D4, 0x9858, 0xEAC3,	0x985A, 0xEFB4, 0x985E, 0xD7BE, 0x9865, 0xFBE2, 0x9867, 0xCDD3,
+	0x986B, 0xEFB5, 0x986F, 0xFAE9, 0x98A8, 0xF9A6, 0x98AF, 0xDFBD,	0x98B1, 0xF7C7, 0x98C4, 0xF8FD, 0x98C7, 0xF8FC, 0x98DB, 0xDEAB,
+	0x98DC, 0xDBE8, 0x98DF, 0xE3DD, 0x98E1, 0xE1E2, 0x98E2, 0xD1C6,	0x98ED, 0xF6D0, 0x98EE, 0xEBE6, 0x98EF, 0xDAF9, 0x98F4, 0xECC7,
+	0x98FC, 0xDEF8, 0x98FD, 0xF8E9, 0x98FE, 0xE3DE, 0x9903, 0xCEF5,	0x9909, 0xFAC3, 0x990A, 0xE5D7, 0x990C, 0xECC8, 0x9910, 0xF3C9,
+	0x9913, 0xE4BB, 0x9918, 0xE6AE, 0x991E, 0xEFB6, 0x9920, 0xDCBF,	0x9928, 0xCEBD, 0x9945, 0xD8C3, 0x9949, 0xD0CF, 0x994B, 0xCFFA,
+	0x994C, 0xF3CA, 0x994D, 0xE0D7, 0x9951, 0xD1C7, 0x9952, 0xE9AE,	0x9954, 0xE8BD, 0x9957, 0xFAC4, 0x9996, 0xE2CF, 0x9999, 0xFAC5,
+	0x999D, 0xF9B8, 0x99A5, 0xDCE0, 0x99A8, 0xFBB0, 0x99AC, 0xD8A9,	0x99AD, 0xE5DF, 0x99AE, 0xF9A7, 0x99B1, 0xF6EE, 0x99B3, 0xF6CC,
+	0x99B4, 0xE2F8, 0x99B9, 0xECF1, 0x99C1, 0xDAE0, 0x99D0, 0xF1D2,	0x99D1, 0xD2CC, 0x99D2, 0xCFCB, 0x99D5, 0xCABD, 0x99D9, 0xDDBF,
+	0x99DD, 0xF6EF, 0x99DF, 0xDEF9, 0x99ED, 0xFAB4, 0x99F1, 0xD5AD,	0x99FF, 0xF1E7, 0x9A01, 0xDEBE, 0x9A08, 0xDCC0, 0x9A0E, 0xD1C8,
+	0x9A0F, 0xD1C9, 0x9A19, 0xF8BE, 0x9A2B, 0xCBF6, 0x9A30, 0xD4F9,	0x9A36, 0xF5E2, 0x9A37, 0xE1D3, 0x9A40, 0xD8E9, 0x9A43, 0xF8FE,
+	0x9A45, 0xCFCC, 0x9A4D, 0xFDA4, 0x9A55, 0xCEF6, 0x9A57, 0xFAD0,	0x9A5A, 0xCCF3, 0x9A5B, 0xE6BE, 0x9A5F, 0xF6AE, 0x9A62, 0xD5F0,
+	0x9A65, 0xD1CA, 0x9A69, 0xFCBE, 0x9A6A, 0xD5F1, 0x9AA8, 0xCDE9,	0x9AB8, 0xFAB5, 0x9AD3, 0xE2D0, 0x9AD4, 0xF4F7, 0x9AD8, 0xCDD4,
+	0x9AE5, 0xE7A3, 0x9AEE, 0xDBA5, 0x9B1A, 0xE2D1, 0x9B27, 0xD7A2,	0x9B2A, 0xF7E3, 0x9B31, 0xEAA6, 0x9B3C, 0xD0A1, 0x9B41, 0xCEDA,
+	0x9B42, 0xFBEB, 0x9B43, 0xDBA6, 0x9B44, 0xDBDE, 0x9B45, 0xD8E5,	0x9B4F, 0xEAE0, 0x9B54, 0xD8AA, 0x9B5A, 0xE5E0, 0x9B6F, 0xD6DB,
+	0x9B8E, 0xEFC6, 0x9B91, 0xF8EA, 0x9B9F, 0xE4D5, 0x9BAB, 0xCEF7,	0x9BAE, 0xE0D8, 0x9BC9, 0xD7EF, 0x9BD6, 0xF4ED, 0x9BE4, 0xCDE6,
+	0x9BE8, 0xCCF4, 0x9C0D, 0xF5E3, 0x9C10, 0xE4CA, 0x9C12, 0xDCE1,	0x9C15, 0xF9C8, 0x9C25, 0xFCBF, 0x9C32, 0xE8A7, 0x9C3B, 0xD8C4,
+	0x9C47, 0xCBBE, 0x9C49, 0xDCAE, 0x9C57, 0xD7F7, 0x9CE5, 0xF0E8,	0x9CE7, 0xDDC0, 0x9CE9, 0xCFCD, 0x9CF3, 0xDCF3, 0x9CF4, 0xD9B0,
+	0x9CF6, 0xE6E9, 0x9D09, 0xE4BC, 0x9D1B, 0xEAC4, 0x9D26, 0xE4EC,	0x9D28, 0xE4E5, 0x9D3B, 0xFBF8, 0x9D51, 0xCCBB, 0x9D5D, 0xE4BD,
+	0x9D60, 0xCDDC, 0x9D61, 0xD9F7, 0x9D6C, 0xDDDF, 0x9D72, 0xEDCE,	0x9DA9, 0xD9D0, 0x9DAF, 0xE5A3, 0x9DB4, 0xF9CD, 0x9DC4, 0xCDAE,
+	0x9DD7, 0xCFCE, 0x9DF2, 0xF6AF, 0x9DF8, 0xFDD3, 0x9DF9, 0xEBED,	0x9DFA, 0xD6DC, 0x9E1A, 0xE5A4, 0x9E1E, 0xD5B6, 0x9E75, 0xD6DD,
+	0x9E79, 0xF9E9, 0x9E7D, 0xE7A4, 0x9E7F, 0xD6E3, 0x9E92, 0xD1CB,	0x9E93, 0xD6E4, 0x9E97, 0xD5F2, 0x9E9D, 0xDEFA, 0x9E9F, 0xD7F8,
+	0x9EA5, 0xD8EA, 0x9EB4, 0xCFD5, 0x9EB5, 0xD8FD, 0x9EBB, 0xD8AB,	0x9EBE, 0xFDCB, 0x9EC3, 0xFCDC, 0x9ECD, 0xE0A8, 0x9ECE, 0xD5F3,
+	0x9ED1, 0xFDD9, 0x9ED4, 0xCCA3, 0x9ED8, 0xD9F9, 0x9EDB, 0xD3EA,	0x9EDC, 0xF5F5, 0x9EDE, 0xEFC7, 0x9EE8, 0xD3DA, 0x9EF4, 0xDABD,
+	0x9F07, 0xE8A8, 0x9F08, 0xDCAF, 0x9F0E, 0xF0A3, 0x9F13, 0xCDD5,	0x9F20, 0xE0A9, 0x9F3B, 0xDEAC, 0x9F4A, 0xF0BA, 0x9F4B, 0xEEB1,
+	0x9F4E, 0xEEB2, 0x9F52, 0xF6CD, 0x9F5F, 0xEED2, 0x9F61, 0xD6C6,	0x9F67, 0xE0E5, 0x9F6A, 0xF3BB, 0x9F6C, 0xE5E1, 0x9F77, 0xE4CB,
+	0x9F8D, 0xD7A3, 0x9F90, 0xDBC2, 0x9F95, 0xCAFE, 0x9F9C, 0xCFCF,	0xAC00, 0xB0A1, 0xAC01, 0xB0A2, 0xAC02, 0x8141, 0xAC03, 0x8142,
+	0xAC04, 0xB0A3, 0xAC05, 0x8143, 0xAC06, 0x8144, 0xAC07, 0xB0A4,	0xAC08, 0xB0A5, 0xAC09, 0xB0A6, 0xAC0A, 0xB0A7, 0xAC0B, 0x8145,
+	0xAC0C, 0x8146, 0xAC0D, 0x8147, 0xAC0E, 0x8148, 0xAC0F, 0x8149,	0xAC10, 0xB0A8, 0xAC11, 0xB0A9, 0xAC12, 0xB0AA, 0xAC13, 0xB0AB,
+	0xAC14, 0xB0AC, 0xAC15, 0xB0AD, 0xAC16, 0xB0AE, 0xAC17, 0xB0AF,	0xAC18, 0x814A, 0xAC19, 0xB0B0, 0xAC1A, 0xB0B1, 0xAC1B, 0xB0B2,
+	0xAC1C, 0xB0B3, 0xAC1D, 0xB0B4, 0xAC1E, 0x814B, 0xAC1F, 0x814C,	0xAC20, 0xB0B5, 0xAC21, 0x814D, 0xAC22, 0x814E, 0xAC23, 0x814F,
+	0xAC24, 0xB0B6, 0xAC25, 0x8150, 0xAC26, 0x8151, 0xAC27, 0x8152,	0xAC28, 0x8153, 0xAC29, 0x8154, 0xAC2A, 0x8155, 0xAC2B, 0x8156,
+	0xAC2C, 0xB0B7, 0xAC2D, 0xB0B8, 0xAC2E, 0x8157, 0xAC2F, 0xB0B9,	0xAC30, 0xB0BA, 0xAC31, 0xB0BB, 0xAC32, 0x8158, 0xAC33, 0x8159,
+	0xAC34, 0x815A, 0xAC35, 0x8161, 0xAC36, 0x8162, 0xAC37, 0x8163,	0xAC38, 0xB0BC, 0xAC39, 0xB0BD, 0xAC3A, 0x8164, 0xAC3B, 0x8165,
+	0xAC3C, 0xB0BE, 0xAC3D, 0x8166, 0xAC3E, 0x8167, 0xAC3F, 0x8168,	0xAC40, 0xB0BF, 0xAC41, 0x8169, 0xAC42, 0x816A, 0xAC43, 0x816B,
+	0xAC44, 0x816C, 0xAC45, 0x816D, 0xAC46, 0x816E, 0xAC47, 0x816F,	0xAC48, 0x8170, 0xAC49, 0x8171, 0xAC4A, 0x8172, 0xAC4B, 0xB0C0,
+	0xAC4C, 0x8173, 0xAC4D, 0xB0C1, 0xAC4E, 0x8174, 0xAC4F, 0x8175,	0xAC50, 0x8176, 0xAC51, 0x8177, 0xAC52, 0x8178, 0xAC53, 0x8179,
+	0xAC54, 0xB0C2, 0xAC55, 0x817A, 0xAC56, 0x8181, 0xAC57, 0x8182,	0xAC58, 0xB0C3, 0xAC59, 0x8183, 0xAC5A, 0x8184, 0xAC5B, 0x8185,
+	0xAC5C, 0xB0C4, 0xAC5D, 0x8186, 0xAC5E, 0x8187, 0xAC5F, 0x8188,	0xAC60, 0x8189, 0xAC61, 0x818A, 0xAC62, 0x818B, 0xAC63, 0x818C,
+	0xAC64, 0x818D, 0xAC65, 0x818E, 0xAC66, 0x818F, 0xAC67, 0x8190,	0xAC68, 0x8191, 0xAC69, 0x8192, 0xAC6A, 0x8193, 0xAC6B, 0x8194,
+	0xAC6C, 0x8195, 0xAC6D, 0x8196, 0xAC6E, 0x8197, 0xAC6F, 0x8198,	0xAC70, 0xB0C5, 0xAC71, 0xB0C6, 0xAC72, 0x8199, 0xAC73, 0x819A,
+	0xAC74, 0xB0C7, 0xAC75, 0x819B, 0xAC76, 0x819C, 0xAC77, 0xB0C8,	0xAC78, 0xB0C9, 0xAC79, 0x819D, 0xAC7A, 0xB0CA, 0xAC7B, 0x819E,
+	0xAC7C, 0x819F, 0xAC7D, 0x81A0, 0xAC7E, 0x81A1, 0xAC7F, 0x81A2,	0xAC80, 0xB0CB, 0xAC81, 0xB0CC, 0xAC82, 0x81A3, 0xAC83, 0xB0CD,
+	0xAC84, 0xB0CE, 0xAC85, 0xB0CF, 0xAC86, 0xB0D0, 0xAC87, 0x81A4,	0xAC88, 0x81A5, 0xAC89, 0xB0D1, 0xAC8A, 0xB0D2, 0xAC8B, 0xB0D3,
+	0xAC8C, 0xB0D4, 0xAC8D, 0x81A6, 0xAC8E, 0x81A7, 0xAC8F, 0x81A8,	0xAC90, 0xB0D5, 0xAC91, 0x81A9, 0xAC92, 0x81AA, 0xAC93, 0x81AB,
+	0xAC94, 0xB0D6, 0xAC95, 0x81AC, 0xAC96, 0x81AD, 0xAC97, 0x81AE,	0xAC98, 0x81AF, 0xAC99, 0x81B0, 0xAC9A, 0x81B1, 0xAC9B, 0x81B2,
+	0xAC9C, 0xB0D7, 0xAC9D, 0xB0D8, 0xAC9E, 0x81B3, 0xAC9F, 0xB0D9,	0xACA0, 0xB0DA, 0xACA1, 0xB0DB, 0xACA2, 0x81B4, 0xACA3, 0x81B5,
+	0xACA4, 0x81B6, 0xACA5, 0x81B7, 0xACA6, 0x81B8, 0xACA7, 0x81B9,	0xACA8, 0xB0DC, 0xACA9, 0xB0DD, 0xACAA, 0xB0DE, 0xACAB, 0x81BA,
+	0xACAC, 0xB0DF, 0xACAD, 0x81BB, 0xACAE, 0x81BC, 0xACAF, 0xB0E0,	0xACB0, 0xB0E1, 0xACB1, 0x81BD, 0xACB2, 0x81BE, 0xACB3, 0x81BF,
+	0xACB4, 0x81C0, 0xACB5, 0x81C1, 0xACB6, 0x81C2, 0xACB7, 0x81C3,	0xACB8, 0xB0E2, 0xACB9, 0xB0E3, 0xACBA, 0x81C4, 0xACBB, 0xB0E4,
+	0xACBC, 0xB0E5, 0xACBD, 0xB0E6, 0xACBE, 0x81C5, 0xACBF, 0x81C6,	0xACC0, 0x81C7, 0xACC1, 0xB0E7, 0xACC2, 0x81C8, 0xACC3, 0x81C9,
+	0xACC4, 0xB0E8, 0xACC5, 0x81CA, 0xACC6, 0x81CB, 0xACC7, 0x81CC,	0xACC8, 0xB0E9, 0xACC9, 0x81CD, 0xACCA, 0x81CE, 0xACCB, 0x81CF,
+	0xACCC, 0xB0EA, 0xACCD, 0x81D0, 0xACCE, 0x81D1, 0xACCF, 0x81D2,	0xACD0, 0x81D3, 0xACD1, 0x81D4, 0xACD2, 0x81D5, 0xACD3, 0x81D6,
+	0xACD4, 0x81D7, 0xACD5, 0xB0EB, 0xACD6, 0x81D8, 0xACD7, 0xB0EC,	0xACD8, 0x81D9, 0xACD9, 0x81DA, 0xACDA, 0x81DB, 0xACDB, 0x81DC,
+	0xACDC, 0x81DD, 0xACDD, 0x81DE, 0xACDE, 0x81DF, 0xACDF, 0x81E0,	0xACE0, 0xB0ED, 0xACE1, 0xB0EE, 0xACE2, 0x81E1, 0xACE3, 0x81E2,
+	0xACE4, 0xB0EF, 0xACE5, 0x81E3, 0xACE6, 0x81E4, 0xACE7, 0xB0F0,	0xACE8, 0xB0F1, 0xACE9, 0x81E5, 0xACEA, 0xB0F2, 0xACEB, 0x81E6,
+	0xACEC, 0xB0F3, 0xACED, 0x81E7, 0xACEE, 0x81E8, 0xACEF, 0xB0F4,	0xACF0, 0xB0F5, 0xACF1, 0xB0F6, 0xACF2, 0x81E9, 0xACF3, 0xB0F7,
+	0xACF4, 0x81EA, 0xACF5, 0xB0F8, 0xACF6, 0xB0F9, 0xACF7, 0x81EB,	0xACF8, 0x81EC, 0xACF9, 0x81ED, 0xACFA, 0x81EE, 0xACFB, 0x81EF,
+	0xACFC, 0xB0FA, 0xACFD, 0xB0FB, 0xACFE, 0x81F0, 0xACFF, 0x81F1,	0xAD00, 0xB0FC, 0xAD01, 0x81F2, 0xAD02, 0x81F3, 0xAD03, 0x81F4,
+	0xAD04, 0xB0FD, 0xAD05, 0x81F5, 0xAD06, 0xB0FE, 0xAD07, 0x81F6,	0xAD08, 0x81F7, 0xAD09, 0x81F8, 0xAD0A, 0x81F9, 0xAD0B, 0x81FA,
+	0xAD0C, 0xB1A1, 0xAD0D, 0xB1A2, 0xAD0E, 0x81FB, 0xAD0F, 0xB1A3,	0xAD10, 0x81FC, 0xAD11, 0xB1A4, 0xAD12, 0x81FD, 0xAD13, 0x81FE,
+	0xAD14, 0x8241, 0xAD15, 0x8242, 0xAD16, 0x8243, 0xAD17, 0x8244,	0xAD18, 0xB1A5, 0xAD19, 0x8245, 0xAD1A, 0x8246, 0xAD1B, 0x8247,
+	0xAD1C, 0xB1A6, 0xAD1D, 0x8248, 0xAD1E, 0x8249, 0xAD1F, 0x824A,	0xAD20, 0xB1A7, 0xAD21, 0x824B, 0xAD22, 0x824C, 0xAD23, 0x824D,
+	0xAD24, 0x824E, 0xAD25, 0x824F, 0xAD26, 0x8250, 0xAD27, 0x8251,	0xAD28, 0x8252, 0xAD29, 0xB1A8, 0xAD2A, 0x8253, 0xAD2B, 0x8254,
+	0xAD2C, 0xB1A9, 0xAD2D, 0xB1AA, 0xAD2E, 0x8255, 0xAD2F, 0x8256,	0xAD30, 0x8257, 0xAD31, 0x8258, 0xAD32, 0x8259, 0xAD33, 0x825A,
+	0xAD34, 0xB1AB, 0xAD35, 0xB1AC, 0xAD36, 0x8261, 0xAD37, 0x8262,	0xAD38, 0xB1AD, 0xAD39, 0x8263, 0xAD3A, 0x8264, 0xAD3B, 0x8265,
+	0xAD3C, 0xB1AE, 0xAD3D, 0x8266, 0xAD3E, 0x8267, 0xAD3F, 0x8268,	0xAD40, 0x8269, 0xAD41, 0x826A, 0xAD42, 0x826B, 0xAD43, 0x826C,
+	0xAD44, 0xB1AF, 0xAD45, 0xB1B0, 0xAD46, 0x826D, 0xAD47, 0xB1B1,	0xAD48, 0x826E, 0xAD49, 0xB1B2, 0xAD4A, 0x826F, 0xAD4B, 0x8270,
+	0xAD4C, 0x8271, 0xAD4D, 0x8272, 0xAD4E, 0x8273, 0xAD4F, 0x8274,	0xAD50, 0xB1B3, 0xAD51, 0x8275, 0xAD52, 0x8276, 0xAD53, 0x8277,
+	0xAD54, 0xB1B4, 0xAD55, 0x8278, 0xAD56, 0x8279, 0xAD57, 0x827A,	0xAD58, 0xB1B5, 0xAD59, 0x8281, 0xAD5A, 0x8282, 0xAD5B, 0x8283,
+	0xAD5C, 0x8284, 0xAD5D, 0x8285, 0xAD5E, 0x8286, 0xAD5F, 0x8287,	0xAD60, 0x8288, 0xAD61, 0xB1B6, 0xAD62, 0x8289, 0xAD63, 0xB1B7,
+	0xAD64, 0x828A, 0xAD65, 0x828B, 0xAD66, 0x828C, 0xAD67, 0x828D,	0xAD68, 0x828E, 0xAD69, 0x828F, 0xAD6A, 0x8290, 0xAD6B, 0x8291,
+	0xAD6C, 0xB1B8, 0xAD6D, 0xB1B9, 0xAD6E, 0x8292, 0xAD6F, 0x8293,	0xAD70, 0xB1BA, 0xAD71, 0x8294, 0xAD72, 0x8295, 0xAD73, 0xB1BB,
+	0xAD74, 0xB1BC, 0xAD75, 0xB1BD, 0xAD76, 0xB1BE, 0xAD77, 0x8296,	0xAD78, 0x8297, 0xAD79, 0x8298, 0xAD7A, 0x8299, 0xAD7B, 0xB1BF,
+	0xAD7C, 0xB1C0, 0xAD7D, 0xB1C1, 0xAD7E, 0x829A, 0xAD7F, 0xB1C2,	0xAD80, 0x829B, 0xAD81, 0xB1C3, 0xAD82, 0xB1C4, 0xAD83, 0x829C,
+	0xAD84, 0x829D, 0xAD85, 0x829E, 0xAD86, 0x829F, 0xAD87, 0x82A0,	0xAD88, 0xB1C5, 0xAD89, 0xB1C6, 0xAD8A, 0x82A1, 0xAD8B, 0x82A2,
+	0xAD8C, 0xB1C7, 0xAD8D, 0x82A3, 0xAD8E, 0x82A4, 0xAD8F, 0x82A5,	0xAD90, 0xB1C8, 0xAD91, 0x82A6, 0xAD92, 0x82A7, 0xAD93, 0x82A8,
+	0xAD94, 0x82A9, 0xAD95, 0x82AA, 0xAD96, 0x82AB, 0xAD97, 0x82AC,	0xAD98, 0x82AD, 0xAD99, 0x82AE, 0xAD9A, 0x82AF, 0xAD9B, 0x82B0,
+	0xAD9C, 0xB1C9, 0xAD9D, 0xB1CA, 0xAD9E, 0x82B1, 0xAD9F, 0x82B2,	0xADA0, 0x82B3, 0xADA1, 0x82B4, 0xADA2, 0x82B5, 0xADA3, 0x82B6,
+	0xADA4, 0xB1CB, 0xADA5, 0x82B7, 0xADA6, 0x82B8, 0xADA7, 0x82B9,	0xADA8, 0x82BA, 0xADA9, 0x82BB, 0xADAA, 0x82BC, 0xADAB, 0x82BD,
+	0xADAC, 0x82BE, 0xADAD, 0x82BF, 0xADAE, 0x82C0, 0xADAF, 0x82C1,	0xADB0, 0x82C2, 0xADB1, 0x82C3, 0xADB2, 0x82C4, 0xADB3, 0x82C5,
+	0xADB4, 0x82C6, 0xADB5, 0x82C7, 0xADB6, 0x82C8, 0xADB7, 0xB1CC,	0xADB8, 0x82C9, 0xADB9, 0x82CA, 0xADBA, 0x82CB, 0xADBB, 0x82CC,
+	0xADBC, 0x82CD, 0xADBD, 0x82CE, 0xADBE, 0x82CF, 0xADBF, 0x82D0,	0xADC0, 0xB1CD, 0xADC1, 0xB1CE, 0xADC2, 0x82D1, 0xADC3, 0x82D2,
+	0xADC4, 0xB1CF, 0xADC5, 0x82D3, 0xADC6, 0x82D4, 0xADC7, 0x82D5,	0xADC8, 0xB1D0, 0xADC9, 0x82D6, 0xADCA, 0x82D7, 0xADCB, 0x82D8,
+	0xADCC, 0x82D9, 0xADCD, 0x82DA, 0xADCE, 0x82DB, 0xADCF, 0x82DC,	0xADD0, 0xB1D1, 0xADD1, 0xB1D2, 0xADD2, 0x82DD, 0xADD3, 0xB1D3,
+	0xADD4, 0x82DE, 0xADD5, 0x82DF, 0xADD6, 0x82E0, 0xADD7, 0x82E1,	0xADD8, 0x82E2, 0xADD9, 0x82E3, 0xADDA, 0x82E4, 0xADDB, 0x82E5,
+	0xADDC, 0xB1D4, 0xADDD, 0x82E6, 0xADDE, 0x82E7, 0xADDF, 0x82E8,	0xADE0, 0xB1D5, 0xADE1, 0x82E9, 0xADE2, 0x82EA, 0xADE3, 0x82EB,
+	0xADE4, 0xB1D6, 0xADE5, 0x82EC, 0xADE6, 0x82ED, 0xADE7, 0x82EE,	0xADE8, 0x82EF, 0xADE9, 0x82F0, 0xADEA, 0x82F1, 0xADEB, 0x82F2,
+	0xADEC, 0x82F3, 0xADED, 0x82F4, 0xADEE, 0x82F5, 0xADEF, 0x82F6,	0xADF0, 0x82F7, 0xADF1, 0x82F8, 0xADF2, 0x82F9, 0xADF3, 0x82FA,
+	0xADF4, 0x82FB, 0xADF5, 0x82FC, 0xADF6, 0x82FD, 0xADF7, 0x82FE,	0xADF8, 0xB1D7, 0xADF9, 0xB1D8, 0xADFA, 0x8341, 0xADFB, 0x8342,
+	0xADFC, 0xB1D9, 0xADFD, 0x8343, 0xADFE, 0x8344, 0xADFF, 0xB1DA,	0xAE00, 0xB1DB, 0xAE01, 0xB1DC, 0xAE02, 0x8345, 0xAE03, 0x8346,
+	0xAE04, 0x8347, 0xAE05, 0x8348, 0xAE06, 0x8349, 0xAE07, 0x834A,	0xAE08, 0xB1DD, 0xAE09, 0xB1DE, 0xAE0A, 0x834B, 0xAE0B, 0xB1DF,
+	0xAE0C, 0x834C, 0xAE0D, 0xB1E0, 0xAE0E, 0x834D, 0xAE0F, 0x834E,	0xAE10, 0x834F, 0xAE11, 0x8350, 0xAE12, 0x8351, 0xAE13, 0x8352,
+	0xAE14, 0xB1E1, 0xAE15, 0x8353, 0xAE16, 0x8354, 0xAE17, 0x8355,	0xAE18, 0x8356, 0xAE19, 0x8357, 0xAE1A, 0x8358, 0xAE1B, 0x8359,
+	0xAE1C, 0x835A, 0xAE1D, 0x8361, 0xAE1E, 0x8362, 0xAE1F, 0x8363,	0xAE20, 0x8364, 0xAE21, 0x8365, 0xAE22, 0x8366, 0xAE23, 0x8367,
+	0xAE24, 0x8368, 0xAE25, 0x8369, 0xAE26, 0x836A, 0xAE27, 0x836B,	0xAE28, 0x836C, 0xAE29, 0x836D, 0xAE2A, 0x836E, 0xAE2B, 0x836F,
+	0xAE2C, 0x8370, 0xAE2D, 0x8371, 0xAE2E, 0x8372, 0xAE2F, 0x8373,	0xAE30, 0xB1E2, 0xAE31, 0xB1E3, 0xAE32, 0x8374, 0xAE33, 0x8375,
+	0xAE34, 0xB1E4, 0xAE35, 0x8376, 0xAE36, 0x8377, 0xAE37, 0xB1E5,	0xAE38, 0xB1E6, 0xAE39, 0x8378, 0xAE3A, 0xB1E7, 0xAE3B, 0x8379,
+	0xAE3C, 0x837A, 0xAE3D, 0x8381, 0xAE3E, 0x8382, 0xAE3F, 0x8383,	0xAE40, 0xB1E8, 0xAE41, 0xB1E9, 0xAE42, 0x8384, 0xAE43, 0xB1EA,
+	0xAE44, 0x8385, 0xAE45, 0xB1EB, 0xAE46, 0xB1EC, 0xAE47, 0x8386,	0xAE48, 0x8387, 0xAE49, 0x8388, 0xAE4A, 0xB1ED, 0xAE4B, 0x8389,
+	0xAE4C, 0xB1EE, 0xAE4D, 0xB1EF, 0xAE4E, 0xB1F0, 0xAE4F, 0x838A,	0xAE50, 0xB1F1, 0xAE51, 0x838B, 0xAE52, 0x838C, 0xAE53, 0x838D,
+	0xAE54, 0xB1F2, 0xAE55, 0x838E, 0xAE56, 0xB1F3, 0xAE57, 0x838F,	0xAE58, 0x8390, 0xAE59, 0x8391, 0xAE5A, 0x8392, 0xAE5B, 0x8393,
+	0xAE5C, 0xB1F4, 0xAE5D, 0xB1F5, 0xAE5E, 0x8394, 0xAE5F, 0xB1F6,	0xAE60, 0xB1F7, 0xAE61, 0xB1F8, 0xAE62, 0x8395, 0xAE63, 0x8396,
+	0xAE64, 0x8397, 0xAE65, 0xB1F9, 0xAE66, 0x8398, 0xAE67, 0x8399,	0xAE68, 0xB1FA, 0xAE69, 0xB1FB, 0xAE6A, 0x839A, 0xAE6B, 0x839B,
+	0xAE6C, 0xB1FC, 0xAE6D, 0x839C, 0xAE6E, 0x839D, 0xAE6F, 0x839E,	0xAE70, 0xB1FD, 0xAE71, 0x839F, 0xAE72, 0x83A0, 0xAE73, 0x83A1,
+	0xAE74, 0x83A2, 0xAE75, 0x83A3, 0xAE76, 0x83A4, 0xAE77, 0x83A5,	0xAE78, 0xB1FE, 0xAE79, 0xB2A1, 0xAE7A, 0x83A6, 0xAE7B, 0xB2A2,
+	0xAE7C, 0xB2A3, 0xAE7D, 0xB2A4, 0xAE7E, 0x83A7, 0xAE7F, 0x83A8,	0xAE80, 0x83A9, 0xAE81, 0x83AA, 0xAE82, 0x83AB, 0xAE83, 0x83AC,
+	0xAE84, 0xB2A5, 0xAE85, 0xB2A6, 0xAE86, 0x83AD, 0xAE87, 0x83AE,	0xAE88, 0x83AF, 0xAE89, 0x83B0, 0xAE8A, 0x83B1, 0xAE8B, 0x83B2,
+	0xAE8C, 0xB2A7, 0xAE8D, 0x83B3, 0xAE8E, 0x83B4, 0xAE8F, 0x83B5,	0xAE90, 0x83B6, 0xAE91, 0x83B7, 0xAE92, 0x83B8, 0xAE93, 0x83B9,
+	0xAE94, 0x83BA, 0xAE95, 0x83BB, 0xAE96, 0x83BC, 0xAE97, 0x83BD,	0xAE98, 0x83BE, 0xAE99, 0x83BF, 0xAE9A, 0x83C0, 0xAE9B, 0x83C1,
+	0xAE9C, 0x83C2, 0xAE9D, 0x83C3, 0xAE9E, 0x83C4, 0xAE9F, 0x83C5,	0xAEA0, 0x83C6, 0xAEA1, 0x83C7, 0xAEA2, 0x83C8, 0xAEA3, 0x83C9,
+	0xAEA4, 0x83CA, 0xAEA5, 0x83CB, 0xAEA6, 0x83CC, 0xAEA7, 0x83CD,	0xAEA8, 0x83CE, 0xAEA9, 0x83CF, 0xAEAA, 0x83D0, 0xAEAB, 0x83D1,
+	0xAEAC, 0x83D2, 0xAEAD, 0x83D3, 0xAEAE, 0x83D4, 0xAEAF, 0x83D5,	0xAEB0, 0x83D6, 0xAEB1, 0x83D7, 0xAEB2, 0x83D8, 0xAEB3, 0x83D9,
+	0xAEB4, 0x83DA, 0xAEB5, 0x83DB, 0xAEB6, 0x83DC, 0xAEB7, 0x83DD,	0xAEB8, 0x83DE, 0xAEB9, 0x83DF, 0xAEBA, 0x83E0, 0xAEBB, 0x83E1,
+	0xAEBC, 0xB2A8, 0xAEBD, 0xB2A9, 0xAEBE, 0xB2AA, 0xAEBF, 0x83E2,	0xAEC0, 0xB2AB, 0xAEC1, 0x83E3, 0xAEC2, 0x83E4, 0xAEC3, 0x83E5,
+	0xAEC4, 0xB2AC, 0xAEC5, 0x83E6, 0xAEC6, 0x83E7, 0xAEC7, 0x83E8,	0xAEC8, 0x83E9, 0xAEC9, 0x83EA, 0xAECA, 0x83EB, 0xAECB, 0x83EC,
+	0xAECC, 0xB2AD, 0xAECD, 0xB2AE, 0xAECE, 0x83ED, 0xAECF, 0xB2AF,	0xAED0, 0xB2B0, 0xAED1, 0xB2B1, 0xAED2, 0x83EE, 0xAED3, 0x83EF,
+	0xAED4, 0x83F0, 0xAED5, 0x83F1, 0xAED6, 0x83F2, 0xAED7, 0x83F3,	0xAED8, 0xB2B2, 0xAED9, 0xB2B3, 0xAEDA, 0x83F4, 0xAEDB, 0x83F5,
+	0xAEDC, 0xB2B4, 0xAEDD, 0x83F6, 0xAEDE, 0x83F7, 0xAEDF, 0x83F8,	0xAEE0, 0x83F9, 0xAEE1, 0x83FA, 0xAEE2, 0x83FB, 0xAEE3, 0x83FC,
+	0xAEE4, 0x83FD, 0xAEE5, 0x83FE, 0xAEE6, 0x8441, 0xAEE7, 0x8442,	0xAEE8, 0xB2B5, 0xAEE9, 0x8443, 0xAEEA, 0x8444, 0xAEEB, 0xB2B6,
+	0xAEEC, 0x8445, 0xAEED, 0xB2B7, 0xAEEE, 0x8446, 0xAEEF, 0x8447,	0xAEF0, 0x8448, 0xAEF1, 0x8449, 0xAEF2, 0x844A, 0xAEF3, 0x844B,
+	0xAEF4, 0xB2B8, 0xAEF5, 0x844C, 0xAEF6, 0x844D, 0xAEF7, 0x844E,	0xAEF8, 0xB2B9, 0xAEF9, 0x844F, 0xAEFA, 0x8450, 0xAEFB, 0x8451,
+	0xAEFC, 0xB2BA, 0xAEFD, 0x8452, 0xAEFE, 0x8453, 0xAEFF, 0x8454,	0xAF00, 0x8455, 0xAF01, 0x8456, 0xAF02, 0x8457, 0xAF03, 0x8458,
+	0xAF04, 0x8459, 0xAF05, 0x845A, 0xAF06, 0x8461, 0xAF07, 0xB2BB,	0xAF08, 0xB2BC, 0xAF09, 0x8462, 0xAF0A, 0x8463, 0xAF0B, 0x8464,
+	0xAF0C, 0x8465, 0xAF0D, 0xB2BD, 0xAF0E, 0x8466, 0xAF0F, 0x8467,	0xAF10, 0xB2BE, 0xAF11, 0x8468, 0xAF12, 0x8469, 0xAF13, 0x846A,
+	0xAF14, 0x846B, 0xAF15, 0x846C, 0xAF16, 0x846D, 0xAF17, 0x846E,	0xAF18, 0x846F, 0xAF19, 0x8470, 0xAF1A, 0x8471, 0xAF1B, 0x8472,
+	0xAF1C, 0x8473, 0xAF1D, 0x8474, 0xAF1E, 0x8475, 0xAF1F, 0x8476,	0xAF20, 0x8477, 0xAF21, 0x8478, 0xAF22, 0x8479, 0xAF23, 0x847A,
+	0xAF24, 0x8481, 0xAF25, 0x8482, 0xAF26, 0x8483, 0xAF27, 0x8484,	0xAF28, 0x8485, 0xAF29, 0x8486, 0xAF2A, 0x8487, 0xAF2B, 0x8488,
+	0xAF2C, 0xB2BF, 0xAF2D, 0xB2C0, 0xAF2E, 0x8489, 0xAF2F, 0x848A,	0xAF30, 0xB2C1, 0xAF31, 0x848B, 0xAF32, 0xB2C2, 0xAF33, 0x848C,
+	0xAF34, 0xB2C3, 0xAF35, 0x848D, 0xAF36, 0x848E, 0xAF37, 0x848F,	0xAF38, 0x8490, 0xAF39, 0x8491, 0xAF3A, 0x8492, 0xAF3B, 0x8493,
+	0xAF3C, 0xB2C4, 0xAF3D, 0xB2C5, 0xAF3E, 0x8494, 0xAF3F, 0xB2C6,	0xAF40, 0x8495, 0xAF41, 0xB2C7, 0xAF42, 0xB2C8, 0xAF43, 0xB2C9,
+	0xAF44, 0x8496, 0xAF45, 0x8497, 0xAF46, 0x8498, 0xAF47, 0x8499,	0xAF48, 0xB2CA, 0xAF49, 0xB2CB, 0xAF4A, 0x849A, 0xAF4B, 0x849B,
+	0xAF4C, 0x849C, 0xAF4D, 0x849D, 0xAF4E, 0x849E, 0xAF4F, 0x849F,	0xAF50, 0xB2CC, 0xAF51, 0x84A0, 0xAF52, 0x84A1, 0xAF53, 0x84A2,
+	0xAF54, 0x84A3, 0xAF55, 0x84A4, 0xAF56, 0x84A5, 0xAF57, 0x84A6,	0xAF58, 0x84A7, 0xAF59, 0x84A8, 0xAF5A, 0x84A9, 0xAF5B, 0x84AA,
+	0xAF5C, 0xB2CD, 0xAF5D, 0xB2CE, 0xAF5E, 0x84AB, 0xAF5F, 0x84AC,	0xAF60, 0x84AD, 0xAF61, 0x84AE, 0xAF62, 0x84AF, 0xAF63, 0x84B0,
+	0xAF64, 0xB2CF, 0xAF65, 0xB2D0, 0xAF66, 0x84B1, 0xAF67, 0x84B2,	0xAF68, 0x84B3, 0xAF69, 0x84B4, 0xAF6A, 0x84B5, 0xAF6B, 0x84B6,
+	0xAF6C, 0x84B7, 0xAF6D, 0x84B8, 0xAF6E, 0x84B9, 0xAF6F, 0x84BA,	0xAF70, 0x84BB, 0xAF71, 0x84BC, 0xAF72, 0x84BD, 0xAF73, 0x84BE,
+	0xAF74, 0x84BF, 0xAF75, 0x84C0, 0xAF76, 0x84C1, 0xAF77, 0x84C2,	0xAF78, 0x84C3, 0xAF79, 0xB2D1, 0xAF7A, 0x84C4, 0xAF7B, 0x84C5,
+	0xAF7C, 0x84C6, 0xAF7D, 0x84C7, 0xAF7E, 0x84C8, 0xAF7F, 0x84C9,	0xAF80, 0xB2D2, 0xAF81, 0x84CA, 0xAF82, 0x84CB, 0xAF83, 0x84CC,
+	0xAF84, 0xB2D3, 0xAF85, 0x84CD, 0xAF86, 0x84CE, 0xAF87, 0x84CF,	0xAF88, 0xB2D4, 0xAF89, 0x84D0, 0xAF8A, 0x84D1, 0xAF8B, 0x84D2,
+	0xAF8C, 0x84D3, 0xAF8D, 0x84D4, 0xAF8E, 0x84D5, 0xAF8F, 0x84D6,	0xAF90, 0xB2D5, 0xAF91, 0xB2D6, 0xAF92, 0x84D7, 0xAF93, 0x84D8,
+	0xAF94, 0x84D9, 0xAF95, 0xB2D7, 0xAF96, 0x84DA, 0xAF97, 0x84DB,	0xAF98, 0x84DC, 0xAF99, 0x84DD, 0xAF9A, 0x84DE, 0xAF9B, 0x84DF,
+	0xAF9C, 0xB2D8, 0xAF9D, 0x84E0, 0xAF9E, 0x84E1, 0xAF9F, 0x84E2,	0xAFA0, 0x84E3, 0xAFA1, 0x84E4, 0xAFA2, 0x84E5, 0xAFA3, 0x84E6,
+	0xAFA4, 0x84E7, 0xAFA5, 0x84E8, 0xAFA6, 0x84E9, 0xAFA7, 0x84EA,	0xAFA8, 0x84EB, 0xAFA9, 0x84EC, 0xAFAA, 0x84ED, 0xAFAB, 0x84EE,
+	0xAFAC, 0x84EF, 0xAFAD, 0x84F0, 0xAFAE, 0x84F1, 0xAFAF, 0x84F2,	0xAFB0, 0x84F3, 0xAFB1, 0x84F4, 0xAFB2, 0x84F5, 0xAFB3, 0x84F6,
+	0xAFB4, 0x84F7, 0xAFB5, 0x84F8, 0xAFB6, 0x84F9, 0xAFB7, 0x84FA,	0xAFB8, 0xB2D9, 0xAFB9, 0xB2DA, 0xAFBA, 0x84FB, 0xAFBB, 0x84FC,
+	0xAFBC, 0xB2DB, 0xAFBD, 0x84FD, 0xAFBE, 0x84FE, 0xAFBF, 0x8541,	0xAFC0, 0xB2DC, 0xAFC1, 0x8542, 0xAFC2, 0x8543, 0xAFC3, 0x8544,
+	0xAFC4, 0x8545, 0xAFC5, 0x8546, 0xAFC6, 0x8547, 0xAFC7, 0xB2DD,	0xAFC8, 0xB2DE, 0xAFC9, 0xB2DF, 0xAFCA, 0x8548, 0xAFCB, 0xB2E0,
+	0xAFCC, 0x8549, 0xAFCD, 0xB2E1, 0xAFCE, 0xB2E2, 0xAFCF, 0x854A,	0xAFD0, 0x854B, 0xAFD1, 0x854C, 0xAFD2, 0x854D, 0xAFD3, 0x854E,
+	0xAFD4, 0xB2E3, 0xAFD5, 0x854F, 0xAFD6, 0x8550, 0xAFD7, 0x8551,	0xAFD8, 0x8552, 0xAFD9, 0x8553, 0xAFDA, 0x8554, 0xAFDB, 0x8555,
+	0xAFDC, 0xB2E4, 0xAFDD, 0x8556, 0xAFDE, 0x8557, 0xAFDF, 0x8558,	0xAFE0, 0x8559, 0xAFE1, 0x855A, 0xAFE2, 0x8561, 0xAFE3, 0x8562,
+	0xAFE4, 0x8563, 0xAFE5, 0x8564, 0xAFE6, 0x8565, 0xAFE7, 0x8566,	0xAFE8, 0xB2E5, 0xAFE9, 0xB2E6, 0xAFEA, 0x8567, 0xAFEB, 0x8568,
+	0xAFEC, 0x8569, 0xAFED, 0x856A, 0xAFEE, 0x856B, 0xAFEF, 0x856C,	0xAFF0, 0xB2E7, 0xAFF1, 0xB2E8, 0xAFF2, 0x856D, 0xAFF3, 0x856E,
+	0xAFF4, 0xB2E9, 0xAFF5, 0x856F, 0xAFF6, 0x8570, 0xAFF7, 0x8571,	0xAFF8, 0xB2EA, 0xAFF9, 0x8572, 0xAFFA, 0x8573, 0xAFFB, 0x8574,
+	0xAFFC, 0x8575, 0xAFFD, 0x8576, 0xAFFE, 0x8577, 0xAFFF, 0x8578,	0xB000, 0xB2EB, 0xB001, 0xB2EC, 0xB002, 0x8579, 0xB003, 0x857A,
+	0xB004, 0xB2ED, 0xB005, 0x8581, 0xB006, 0x8582, 0xB007, 0x8583,	0xB008, 0x8584, 0xB009, 0x8585, 0xB00A, 0x8586, 0xB00B, 0x8587,
+	0xB00C, 0xB2EE, 0xB00D, 0x8588, 0xB00E, 0x8589, 0xB00F, 0x858A,	0xB010, 0xB2EF, 0xB011, 0x858B, 0xB012, 0x858C, 0xB013, 0x858D,
+	0xB014, 0xB2F0, 0xB015, 0x858E, 0xB016, 0x858F, 0xB017, 0x8590,	0xB018, 0x8591, 0xB019, 0x8592, 0xB01A, 0x8593, 0xB01B, 0x8594,
+	0xB01C, 0xB2F1, 0xB01D, 0xB2F2, 0xB01E, 0x8595, 0xB01F, 0x8596,	0xB020, 0x8597, 0xB021, 0x8598, 0xB022, 0x8599, 0xB023, 0x859A,
+	0xB024, 0x859B, 0xB025, 0x859C, 0xB026, 0x859D, 0xB027, 0x859E,	0xB028, 0xB2F3, 0xB029, 0x859F, 0xB02A, 0x85A0, 0xB02B, 0x85A1,
+	0xB02C, 0x85A2, 0xB02D, 0x85A3, 0xB02E, 0x85A4, 0xB02F, 0x85A5,	0xB030, 0x85A6, 0xB031, 0x85A7, 0xB032, 0x85A8, 0xB033, 0x85A9,
+	0xB034, 0x85AA, 0xB035, 0x85AB, 0xB036, 0x85AC, 0xB037, 0x85AD,	0xB038, 0x85AE, 0xB039, 0x85AF, 0xB03A, 0x85B0, 0xB03B, 0x85B1,
+	0xB03C, 0x85B2, 0xB03D, 0x85B3, 0xB03E, 0x85B4, 0xB03F, 0x85B5,	0xB040, 0x85B6, 0xB041, 0x85B7, 0xB042, 0x85B8, 0xB043, 0x85B9,
+	0xB044, 0xB2F4, 0xB045, 0xB2F5, 0xB046, 0x85BA, 0xB047, 0x85BB,	0xB048, 0xB2F6, 0xB049, 0x85BC, 0xB04A, 0xB2F7, 0xB04B, 0x85BD,
+	0xB04C, 0xB2F8, 0xB04D, 0x85BE, 0xB04E, 0xB2F9, 0xB04F, 0x85BF,	0xB050, 0x85C0, 0xB051, 0x85C1, 0xB052, 0x85C2, 0xB053, 0xB2FA,
+	0xB054, 0xB2FB, 0xB055, 0xB2FC, 0xB056, 0x85C3, 0xB057, 0xB2FD,	0xB058, 0x85C4, 0xB059, 0xB2FE, 0xB05A, 0x85C5, 0xB05B, 0x85C6,
+	0xB05C, 0x85C7, 0xB05D, 0xB3A1, 0xB05E, 0x85C8, 0xB05F, 0x85C9,	0xB060, 0x85CA, 0xB061, 0x85CB, 0xB062, 0x85CC, 0xB063, 0x85CD,
+	0xB064, 0x85CE, 0xB065, 0x85CF, 0xB066, 0x85D0, 0xB067, 0x85D1,	0xB068, 0x85D2, 0xB069, 0x85D3, 0xB06A, 0x85D4, 0xB06B, 0x85D5,
+	0xB06C, 0x85D6, 0xB06D, 0x85D7, 0xB06E, 0x85D8, 0xB06F, 0x85D9,	0xB070, 0x85DA, 0xB071, 0x85DB, 0xB072, 0x85DC, 0xB073, 0x85DD,
+	0xB074, 0x85DE, 0xB075, 0x85DF, 0xB076, 0x85E0, 0xB077, 0x85E1,	0xB078, 0x85E2, 0xB079, 0x85E3, 0xB07A, 0x85E4, 0xB07B, 0x85E5,
+	0xB07C, 0xB3A2, 0xB07D, 0xB3A3, 0xB07E, 0x85E6, 0xB07F, 0x85E7,	0xB080, 0xB3A4, 0xB081, 0x85E8, 0xB082, 0x85E9, 0xB083, 0x85EA,
+	0xB084, 0xB3A5, 0xB085, 0x85EB, 0xB086, 0x85EC, 0xB087, 0x85ED,	0xB088, 0x85EE, 0xB089, 0x85EF, 0xB08A, 0x85F0, 0xB08B, 0x85F1,
+	0xB08C, 0xB3A6, 0xB08D, 0xB3A7, 0xB08E, 0x85F2, 0xB08F, 0xB3A8,	0xB090, 0x85F3, 0xB091, 0xB3A9, 0xB092, 0x85F4, 0xB093, 0x85F5,
+	0xB094, 0x85F6, 0xB095, 0x85F7, 0xB096, 0x85F8, 0xB097, 0x85F9,	0xB098, 0xB3AA, 0xB099, 0xB3AB, 0xB09A, 0xB3AC, 0xB09B, 0x85FA,
+	0xB09C, 0xB3AD, 0xB09D, 0x85FB, 0xB09E, 0x85FC, 0xB09F, 0xB3AE,	0xB0A0, 0xB3AF, 0xB0A1, 0xB3B0, 0xB0A2, 0xB3B1, 0xB0A3, 0x85FD,
+	0xB0A4, 0x85FE, 0xB0A5, 0x8641, 0xB0A6, 0x8642, 0xB0A7, 0x8643,	0xB0A8, 0xB3B2, 0xB0A9, 0xB3B3, 0xB0AA, 0x8644, 0xB0AB, 0xB3B4,
+	0xB0AC, 0xB3B5, 0xB0AD, 0xB3B6, 0xB0AE, 0xB3B7, 0xB0AF, 0xB3B8,	0xB0B0, 0x8645, 0xB0B1, 0xB3B9, 0xB0B2, 0x8646, 0xB0B3, 0xB3BA,
+	0xB0B4, 0xB3BB, 0xB0B5, 0xB3BC, 0xB0B6, 0x8647, 0xB0B7, 0x8648,	0xB0B8, 0xB3BD, 0xB0B9, 0x8649, 0xB0BA, 0x864A, 0xB0BB, 0x864B,
+	0xB0BC, 0xB3BE, 0xB0BD, 0x864C, 0xB0BE, 0x864D, 0xB0BF, 0x864E,	0xB0C0, 0x864F, 0xB0C1, 0x8650, 0xB0C2, 0x8651, 0xB0C3, 0x8652,
+	0xB0C4, 0xB3BF, 0xB0C5, 0xB3C0, 0xB0C6, 0x8653, 0xB0C7, 0xB3C1,	0xB0C8, 0xB3C2, 0xB0C9, 0xB3C3, 0xB0CA, 0x8654, 0xB0CB, 0x8655,
+	0xB0CC, 0x8656, 0xB0CD, 0x8657, 0xB0CE, 0x8658, 0xB0CF, 0x8659,	0xB0D0, 0xB3C4, 0xB0D1, 0xB3C5, 0xB0D2, 0x865A, 0xB0D3, 0x8661,
+	0xB0D4, 0xB3C6, 0xB0D5, 0x8662, 0xB0D6, 0x8663, 0xB0D7, 0x8664,	0xB0D8, 0xB3C7, 0xB0D9, 0x8665, 0xB0DA, 0x8666, 0xB0DB, 0x8667,
+	0xB0DC, 0x8668, 0xB0DD, 0x8669, 0xB0DE, 0x866A, 0xB0DF, 0x866B,	0xB0E0, 0xB3C8, 0xB0E1, 0x866C, 0xB0E2, 0x866D, 0xB0E3, 0x866E,
+	0xB0E4, 0x866F, 0xB0E5, 0xB3C9, 0xB0E6, 0x8670, 0xB0E7, 0x8671,	0xB0E8, 0x8672, 0xB0E9, 0x8673, 0xB0EA, 0x8674, 0xB0EB, 0x8675,
+	0xB0EC, 0x8676, 0xB0ED, 0x8677, 0xB0EE, 0x8678, 0xB0EF, 0x8679,	0xB0F0, 0x867A, 0xB0F1, 0x8681, 0xB0F2, 0x8682, 0xB0F3, 0x8683,
+	0xB0F4, 0x8684, 0xB0F5, 0x8685, 0xB0F6, 0x8686, 0xB0F7, 0x8687,	0xB0F8, 0x8688, 0xB0F9, 0x8689, 0xB0FA, 0x868A, 0xB0FB, 0x868B,
+	0xB0FC, 0x868C, 0xB0FD, 0x868D, 0xB0FE, 0x868E, 0xB0FF, 0x868F,	0xB100, 0x8690, 0xB101, 0x8691, 0xB102, 0x8692, 0xB103, 0x8693,
+	0xB104, 0x8694, 0xB105, 0x8695, 0xB106, 0x8696, 0xB107, 0x8697,	0xB108, 0xB3CA, 0xB109, 0xB3CB, 0xB10A, 0x8698, 0xB10B, 0xB3CC,
+	0xB10C, 0xB3CD, 0xB10D, 0x8699, 0xB10E, 0x869A, 0xB10F, 0x869B,	0xB110, 0xB3CE, 0xB111, 0x869C, 0xB112, 0xB3CF, 0xB113, 0xB3D0,
+	0xB114, 0x869D, 0xB115, 0x869E, 0xB116, 0x869F, 0xB117, 0x86A0,	0xB118, 0xB3D1, 0xB119, 0xB3D2, 0xB11A, 0x86A1, 0xB11B, 0xB3D3,
+	0xB11C, 0xB3D4, 0xB11D, 0xB3D5, 0xB11E, 0x86A2, 0xB11F, 0x86A3,	0xB120, 0x86A4, 0xB121, 0x86A5, 0xB122, 0x86A6, 0xB123, 0xB3D6,
+	0xB124, 0xB3D7, 0xB125, 0xB3D8, 0xB126, 0x86A7, 0xB127, 0x86A8,	0xB128, 0xB3D9, 0xB129, 0x86A9, 0xB12A, 0x86AA, 0xB12B, 0x86AB,
+	0xB12C, 0xB3DA, 0xB12D, 0x86AC, 0xB12E, 0x86AD, 0xB12F, 0x86AE,	0xB130, 0x86AF, 0xB131, 0x86B0, 0xB132, 0x86B1, 0xB133, 0x86B2,
+	0xB134, 0xB3DB, 0xB135, 0xB3DC, 0xB136, 0x86B3, 0xB137, 0xB3DD,	0xB138, 0xB3DE, 0xB139, 0xB3DF, 0xB13A, 0x86B4, 0xB13B, 0x86B5,
+	0xB13C, 0x86B6, 0xB13D, 0x86B7, 0xB13E, 0x86B8, 0xB13F, 0x86B9,	0xB140, 0xB3E0, 0xB141, 0xB3E1, 0xB142, 0x86BA, 0xB143, 0x86BB,
+	0xB144, 0xB3E2, 0xB145, 0x86BC, 0xB146, 0x86BD, 0xB147, 0x86BE,	0xB148, 0xB3E3, 0xB149, 0x86BF, 0xB14A, 0x86C0, 0xB14B, 0x86C1,
+	0xB14C, 0x86C2, 0xB14D, 0x86C3, 0xB14E, 0x86C4, 0xB14F, 0x86C5,	0xB150, 0xB3E4, 0xB151, 0xB3E5, 0xB152, 0x86C6, 0xB153, 0x86C7,
+	0xB154, 0xB3E6, 0xB155, 0xB3E7, 0xB156, 0x86C8, 0xB157, 0x86C9,	0xB158, 0xB3E8, 0xB159, 0x86CA, 0xB15A, 0x86CB, 0xB15B, 0x86CC,
+	0xB15C, 0xB3E9, 0xB15D, 0x86CD, 0xB15E, 0x86CE, 0xB15F, 0x86CF,	0xB160, 0xB3EA, 0xB161, 0x86D0, 0xB162, 0x86D1, 0xB163, 0x86D2,
+	0xB164, 0x86D3, 0xB165, 0x86D4, 0xB166, 0x86D5, 0xB167, 0x86D6,	0xB168, 0x86D7, 0xB169, 0x86D8, 0xB16A, 0x86D9, 0xB16B, 0x86DA,
+	0xB16C, 0x86DB, 0xB16D, 0x86DC, 0xB16E, 0x86DD, 0xB16F, 0x86DE,	0xB170, 0x86DF, 0xB171, 0x86E0, 0xB172, 0x86E1, 0xB173, 0x86E2,
+	0xB174, 0x86E3, 0xB175, 0x86E4, 0xB176, 0x86E5, 0xB177, 0x86E6,	0xB178, 0xB3EB, 0xB179, 0xB3EC, 0xB17A, 0x86E7, 0xB17B, 0x86E8,
+	0xB17C, 0xB3ED, 0xB17D, 0x86E9, 0xB17E, 0x86EA, 0xB17F, 0x86EB,	0xB180, 0xB3EE, 0xB181, 0x86EC, 0xB182, 0xB3EF, 0xB183, 0x86ED,
+	0xB184, 0x86EE, 0xB185, 0x86EF, 0xB186, 0x86F0, 0xB187, 0x86F1,	0xB188, 0xB3F0, 0xB189, 0xB3F1, 0xB18A, 0x86F2, 0xB18B, 0xB3F2,
+	0xB18C, 0x86F3, 0xB18D, 0xB3F3, 0xB18E, 0x86F4, 0xB18F, 0x86F5,	0xB190, 0x86F6, 0xB191, 0x86F7, 0xB192, 0xB3F4, 0xB193, 0xB3F5,
+	0xB194, 0xB3F6, 0xB195, 0x86F8, 0xB196, 0x86F9, 0xB197, 0x86FA,	0xB198, 0xB3F7, 0xB199, 0x86FB, 0xB19A, 0x86FC, 0xB19B, 0x86FD,
+	0xB19C, 0xB3F8, 0xB19D, 0x86FE, 0xB19E, 0x8741, 0xB19F, 0x8742,	0xB1A0, 0x8743, 0xB1A1, 0x8744, 0xB1A2, 0x8745, 0xB1A3, 0x8746,
+	0xB1A4, 0x8747, 0xB1A5, 0x8748, 0xB1A6, 0x8749, 0xB1A7, 0x874A,	0xB1A8, 0xB3F9, 0xB1A9, 0x874B, 0xB1AA, 0x874C, 0xB1AB, 0x874D,
+	0xB1AC, 0x874E, 0xB1AD, 0x874F, 0xB1AE, 0x8750, 0xB1AF, 0x8751,	0xB1B0, 0x8752, 0xB1B1, 0x8753, 0xB1B2, 0x8754, 0xB1B3, 0x8755,
+	0xB1B4, 0x8756, 0xB1B5, 0x8757, 0xB1B6, 0x8758, 0xB1B7, 0x8759,	0xB1B8, 0x875A, 0xB1B9, 0x8761, 0xB1BA, 0x8762, 0xB1BB, 0x8763,
+	0xB1BC, 0x8764, 0xB1BD, 0x8765, 0xB1BE, 0x8766, 0xB1BF, 0x8767,	0xB1C0, 0x8768, 0xB1C1, 0x8769, 0xB1C2, 0x876A, 0xB1C3, 0x876B,
+	0xB1C4, 0x876C, 0xB1C5, 0x876D, 0xB1C6, 0x876E, 0xB1C7, 0x876F,	0xB1C8, 0x8770, 0xB1C9, 0x8771, 0xB1CA, 0x8772, 0xB1CB, 0x8773,
+	0xB1CC, 0xB3FA, 0xB1CD, 0x8774, 0xB1CE, 0x8775, 0xB1CF, 0x8776,	0xB1D0, 0xB3FB, 0xB1D1, 0x8777, 0xB1D2, 0x8778, 0xB1D3, 0x8779,
+	0xB1D4, 0xB3FC, 0xB1D5, 0x877A, 0xB1D6, 0x8781, 0xB1D7, 0x8782,	0xB1D8, 0x8783, 0xB1D9, 0x8784, 0xB1DA, 0x8785, 0xB1DB, 0x8786,
+	0xB1DC, 0xB3FD, 0xB1DD, 0xB3FE, 0xB1DE, 0x8787, 0xB1DF, 0xB4A1,	0xB1E0, 0x8788, 0xB1E1, 0x8789, 0xB1E2, 0x878A, 0xB1E3, 0x878B,
+	0xB1E4, 0x878C, 0xB1E5, 0x878D, 0xB1E6, 0x878E, 0xB1E7, 0x878F,	0xB1E8, 0xB4A2, 0xB1E9, 0xB4A3, 0xB1EA, 0x8790, 0xB1EB, 0x8791,
+	0xB1EC, 0xB4A4, 0xB1ED, 0x8792, 0xB1EE, 0x8793, 0xB1EF, 0x8794,	0xB1F0, 0xB4A5, 0xB1F1, 0x8795, 0xB1F2, 0x8796, 0xB1F3, 0x8797,
+	0xB1F4, 0x8798, 0xB1F5, 0x8799, 0xB1F6, 0x879A, 0xB1F7, 0x879B,	0xB1F8, 0x879C, 0xB1F9, 0xB4A6, 0xB1FA, 0x879D, 0xB1FB, 0xB4A7,
+	0xB1FC, 0x879E, 0xB1FD, 0xB4A8, 0xB1FE, 0x879F, 0xB1FF, 0x87A0,	0xB200, 0x87A1, 0xB201, 0x87A2, 0xB202, 0x87A3, 0xB203, 0x87A4,
+	0xB204, 0xB4A9, 0xB205, 0xB4AA, 0xB206, 0x87A5, 0xB207, 0x87A6,	0xB208, 0xB4AB, 0xB209, 0x87A7, 0xB20A, 0x87A8, 0xB20B, 0xB4AC,
+	0xB20C, 0xB4AD, 0xB20D, 0x87A9, 0xB20E, 0x87AA, 0xB20F, 0x87AB,	0xB210, 0x87AC, 0xB211, 0x87AD, 0xB212, 0x87AE, 0xB213, 0x87AF,
+	0xB214, 0xB4AE, 0xB215, 0xB4AF, 0xB216, 0x87B0, 0xB217, 0xB4B0,	0xB218, 0x87B1, 0xB219, 0xB4B1, 0xB21A, 0x87B2, 0xB21B, 0x87B3,
+	0xB21C, 0x87B4, 0xB21D, 0x87B5, 0xB21E, 0x87B6, 0xB21F, 0x87B7,	0xB220, 0xB4B2, 0xB221, 0x87B8, 0xB222, 0x87B9, 0xB223, 0x87BA,
+	0xB224, 0x87BB, 0xB225, 0x87BC, 0xB226, 0x87BD, 0xB227, 0x87BE,	0xB228, 0x87BF, 0xB229, 0x87C0, 0xB22A, 0x87C1, 0xB22B, 0x87C2,
+	0xB22C, 0x87C3, 0xB22D, 0x87C4, 0xB22E, 0x87C5, 0xB22F, 0x87C6,	0xB230, 0x87C7, 0xB231, 0x87C8, 0xB232, 0x87C9, 0xB233, 0x87CA,
+	0xB234, 0xB4B3, 0xB235, 0x87CB, 0xB236, 0x87CC, 0xB237, 0x87CD,	0xB238, 0x87CE, 0xB239, 0x87CF, 0xB23A, 0x87D0, 0xB23B, 0x87D1,
+	0xB23C, 0xB4B4, 0xB23D, 0x87D2, 0xB23E, 0x87D3, 0xB23F, 0x87D4,	0xB240, 0x87D5, 0xB241, 0x87D6, 0xB242, 0x87D7, 0xB243, 0x87D8,
+	0xB244, 0x87D9, 0xB245, 0x87DA, 0xB246, 0x87DB, 0xB247, 0x87DC,	0xB248, 0x87DD, 0xB249, 0x87DE, 0xB24A, 0x87DF, 0xB24B, 0x87E0,
+	0xB24C, 0x87E1, 0xB24D, 0x87E2, 0xB24E, 0x87E3, 0xB24F, 0x87E4,	0xB250, 0x87E5, 0xB251, 0x87E6, 0xB252, 0x87E7, 0xB253, 0x87E8,
+	0xB254, 0x87E9, 0xB255, 0x87EA, 0xB256, 0x87EB, 0xB257, 0x87EC,	0xB258, 0xB4B5, 0xB259, 0x87ED, 0xB25A, 0x87EE, 0xB25B, 0x87EF,
+	0xB25C, 0xB4B6, 0xB25D, 0x87F0, 0xB25E, 0x87F1, 0xB25F, 0x87F2,	0xB260, 0xB4B7, 0xB261, 0x87F3, 0xB262, 0x87F4, 0xB263, 0x87F5,
+	0xB264, 0x87F6, 0xB265, 0x87F7, 0xB266, 0x87F8, 0xB267, 0x87F9,	0xB268, 0xB4B8, 0xB269, 0xB4B9, 0xB26A, 0x87FA, 0xB26B, 0x87FB,
+	0xB26C, 0x87FC, 0xB26D, 0x87FD, 0xB26E, 0x87FE, 0xB26F, 0x8841,	0xB270, 0x8842, 0xB271, 0x8843, 0xB272, 0x8844, 0xB273, 0x8845,
+	0xB274, 0xB4BA, 0xB275, 0xB4BB, 0xB276, 0x8846, 0xB277, 0x8847,	0xB278, 0x8848, 0xB279, 0x8849, 0xB27A, 0x884A, 0xB27B, 0x884B,
+	0xB27C, 0xB4BC, 0xB27D, 0x884C, 0xB27E, 0x884D, 0xB27F, 0x884E,	0xB280, 0x884F, 0xB281, 0x8850, 0xB282, 0x8851, 0xB283, 0x8852,
+	0xB284, 0xB4BD, 0xB285, 0xB4BE, 0xB286, 0x8853, 0xB287, 0x8854,	0xB288, 0x8855, 0xB289, 0xB4BF, 0xB28A, 0x8856, 0xB28B, 0x8857,
+	0xB28C, 0x8858, 0xB28D, 0x8859, 0xB28E, 0x885A, 0xB28F, 0x8861,	0xB290, 0xB4C0, 0xB291, 0xB4C1, 0xB292, 0x8862, 0xB293, 0x8863,
+	0xB294, 0xB4C2, 0xB295, 0x8864, 0xB296, 0x8865, 0xB297, 0x8866,	0xB298, 0xB4C3, 0xB299, 0xB4C4, 0xB29A, 0xB4C5, 0xB29B, 0x8867,
+	0xB29C, 0x8868, 0xB29D, 0x8869, 0xB29E, 0x886A, 0xB29F, 0x886B,	0xB2A0, 0xB4C6, 0xB2A1, 0xB4C7, 0xB2A2, 0x886C, 0xB2A3, 0xB4C8,
+	0xB2A4, 0x886D, 0xB2A5, 0xB4C9, 0xB2A6, 0xB4CA, 0xB2A7, 0x886E,	0xB2A8, 0x886F, 0xB2A9, 0x8870, 0xB2AA, 0xB4CB, 0xB2AB, 0x8871,
+	0xB2AC, 0xB4CC, 0xB2AD, 0x8872, 0xB2AE, 0x8873, 0xB2AF, 0x8874,	0xB2B0, 0xB4CD, 0xB2B1, 0x8875, 0xB2B2, 0x8876, 0xB2B3, 0x8877,
+	0xB2B4, 0xB4CE, 0xB2B5, 0x8878, 0xB2B6, 0x8879, 0xB2B7, 0x887A,	0xB2B8, 0x8881, 0xB2B9, 0x8882, 0xB2BA, 0x8883, 0xB2BB, 0x8884,
+	0xB2BC, 0x8885, 0xB2BD, 0x8886, 0xB2BE, 0x8887, 0xB2BF, 0x8888,	0xB2C0, 0x8889, 0xB2C1, 0x888A, 0xB2C2, 0x888B, 0xB2C3, 0x888C,
+	0xB2C4, 0x888D, 0xB2C5, 0x888E, 0xB2C6, 0x888F, 0xB2C7, 0x8890,	0xB2C8, 0xB4CF, 0xB2C9, 0xB4D0, 0xB2CA, 0x8891, 0xB2CB, 0x8892,
+	0xB2CC, 0xB4D1, 0xB2CD, 0x8893, 0xB2CE, 0x8894, 0xB2CF, 0x8895,	0xB2D0, 0xB4D2, 0xB2D1, 0x8896, 0xB2D2, 0xB4D3, 0xB2D3, 0x8897,
+	0xB2D4, 0x8898, 0xB2D5, 0x8899, 0xB2D6, 0x889A, 0xB2D7, 0x889B,	0xB2D8, 0xB4D4, 0xB2D9, 0xB4D5, 0xB2DA, 0x889C, 0xB2DB, 0xB4D6,
+	0xB2DC, 0x889D, 0xB2DD, 0xB4D7, 0xB2DE, 0x889E, 0xB2DF, 0x889F,	0xB2E0, 0x88A0, 0xB2E1, 0x88A1, 0xB2E2, 0xB4D8, 0xB2E3, 0x88A2,
+	0xB2E4, 0xB4D9, 0xB2E5, 0xB4DA, 0xB2E6, 0xB4DB, 0xB2E7, 0x88A3,	0xB2E8, 0xB4DC, 0xB2E9, 0x88A4, 0xB2EA, 0x88A5, 0xB2EB, 0xB4DD,
+	0xB2EC, 0xB4DE, 0xB2ED, 0xB4DF, 0xB2EE, 0xB4E0, 0xB2EF, 0xB4E1,	0xB2F0, 0x88A6, 0xB2F1, 0x88A7, 0xB2F2, 0x88A8, 0xB2F3, 0xB4E2,
+	0xB2F4, 0xB4E3, 0xB2F5, 0xB4E4, 0xB2F6, 0x88A9, 0xB2F7, 0xB4E5,	0xB2F8, 0xB4E6, 0xB2F9, 0xB4E7, 0xB2FA, 0xB4E8, 0xB2FB, 0xB4E9,
+	0xB2FC, 0x88AA, 0xB2FD, 0x88AB, 0xB2FE, 0x88AC, 0xB2FF, 0xB4EA,	0xB300, 0xB4EB, 0xB301, 0xB4EC, 0xB302, 0x88AD, 0xB303, 0x88AE,
+	0xB304, 0xB4ED, 0xB305, 0x88AF, 0xB306, 0x88B0, 0xB307, 0x88B1,	0xB308, 0xB4EE, 0xB309, 0x88B2, 0xB30A, 0x88B3, 0xB30B, 0x88B4,
+	0xB30C, 0x88B5, 0xB30D, 0x88B6, 0xB30E, 0x88B7, 0xB30F, 0x88B8,	0xB310, 0xB4EF, 0xB311, 0xB4F0, 0xB312, 0x88B9, 0xB313, 0xB4F1,
+	0xB314, 0xB4F2, 0xB315, 0xB4F3, 0xB316, 0x88BA, 0xB317, 0x88BB,	0xB318, 0x88BC, 0xB319, 0x88BD, 0xB31A, 0x88BE, 0xB31B, 0x88BF,
+	0xB31C, 0xB4F4, 0xB31D, 0x88C0, 0xB31E, 0x88C1, 0xB31F, 0x88C2,	0xB320, 0x88C3, 0xB321, 0x88C4, 0xB322, 0x88C5, 0xB323, 0x88C6,
+	0xB324, 0x88C7, 0xB325, 0x88C8, 0xB326, 0x88C9, 0xB327, 0x88CA,	0xB328, 0x88CB, 0xB329, 0x88CC, 0xB32A, 0x88CD, 0xB32B, 0x88CE,
+	0xB32C, 0x88CF, 0xB32D, 0x88D0, 0xB32E, 0x88D1, 0xB32F, 0x88D2,	0xB330, 0x88D3, 0xB331, 0x88D4, 0xB332, 0x88D5, 0xB333, 0x88D6,
+	0xB334, 0x88D7, 0xB335, 0x88D8, 0xB336, 0x88D9, 0xB337, 0x88DA,	0xB338, 0x88DB, 0xB339, 0x88DC, 0xB33A, 0x88DD, 0xB33B, 0x88DE,
+	0xB33C, 0x88DF, 0xB33D, 0x88E0, 0xB33E, 0x88E1, 0xB33F, 0x88E2,	0xB340, 0x88E3, 0xB341, 0x88E4, 0xB342, 0x88E5, 0xB343, 0x88E6,
+	0xB344, 0x88E7, 0xB345, 0x88E8, 0xB346, 0x88E9, 0xB347, 0x88EA,	0xB348, 0x88EB, 0xB349, 0x88EC, 0xB34A, 0x88ED, 0xB34B, 0x88EE,
+	0xB34C, 0x88EF, 0xB34D, 0x88F0, 0xB34E, 0x88F1, 0xB34F, 0x88F2,	0xB350, 0x88F3, 0xB351, 0x88F4, 0xB352, 0x88F5, 0xB353, 0x88F6,
+	0xB354, 0xB4F5, 0xB355, 0xB4F6, 0xB356, 0xB4F7, 0xB357, 0x88F7,	0xB358, 0xB4F8, 0xB359, 0x88F8, 0xB35A, 0x88F9, 0xB35B, 0xB4F9,
+	0xB35C, 0xB4FA, 0xB35D, 0x88FA, 0xB35E, 0xB4FB, 0xB35F, 0xB4FC,	0xB360, 0x88FB, 0xB361, 0x88FC, 0xB362, 0x88FD, 0xB363, 0x88FE,
+	0xB364, 0xB4FD, 0xB365, 0xB4FE, 0xB366, 0x8941, 0xB367, 0xB5A1,	0xB368, 0x8942, 0xB369, 0xB5A2, 0xB36A, 0x8943, 0xB36B, 0xB5A3,
+	0xB36C, 0x8944, 0xB36D, 0x8945, 0xB36E, 0xB5A4, 0xB36F, 0x8946,	0xB370, 0xB5A5, 0xB371, 0xB5A6, 0xB372, 0x8947, 0xB373, 0x8948,
+	0xB374, 0xB5A7, 0xB375, 0x8949, 0xB376, 0x894A, 0xB377, 0x894B,	0xB378, 0xB5A8, 0xB379, 0x894C, 0xB37A, 0x894D, 0xB37B, 0x894E,
+	0xB37C, 0x894F, 0xB37D, 0x8950, 0xB37E, 0x8951, 0xB37F, 0x8952,	0xB380, 0xB5A9, 0xB381, 0xB5AA, 0xB382, 0x8953, 0xB383, 0xB5AB,
+	0xB384, 0xB5AC, 0xB385, 0xB5AD, 0xB386, 0x8954, 0xB387, 0x8955,	0xB388, 0x8956, 0xB389, 0x8957, 0xB38A, 0x8958, 0xB38B, 0x8959,
+	0xB38C, 0xB5AE, 0xB38D, 0x895A, 0xB38E, 0x8961, 0xB38F, 0x8962,	0xB390, 0xB5AF, 0xB391, 0x8963, 0xB392, 0x8964, 0xB393, 0x8965,
+	0xB394, 0xB5B0, 0xB395, 0x8966, 0xB396, 0x8967, 0xB397, 0x8968,	0xB398, 0x8969, 0xB399, 0x896A, 0xB39A, 0x896B, 0xB39B, 0x896C,
+	0xB39C, 0x896D, 0xB39D, 0x896E, 0xB39E, 0x896F, 0xB39F, 0x8970,	0xB3A0, 0xB5B1, 0xB3A1, 0xB5B2, 0xB3A2, 0x8971, 0xB3A3, 0x8972,
+	0xB3A4, 0x8973, 0xB3A5, 0x8974, 0xB3A6, 0x8975, 0xB3A7, 0x8976,	0xB3A8, 0xB5B3, 0xB3A9, 0x8977, 0xB3AA, 0x8978, 0xB3AB, 0x8979,
+	0xB3AC, 0xB5B4, 0xB3AD, 0x897A, 0xB3AE, 0x8981, 0xB3AF, 0x8982,	0xB3B0, 0x8983, 0xB3B1, 0x8984, 0xB3B2, 0x8985, 0xB3B3, 0x8986,
+	0xB3B4, 0x8987, 0xB3B5, 0x8988, 0xB3B6, 0x8989, 0xB3B7, 0x898A,	0xB3B8, 0x898B, 0xB3B9, 0x898C, 0xB3BA, 0x898D, 0xB3BB, 0x898E,
+	0xB3BC, 0x898F, 0xB3BD, 0x8990, 0xB3BE, 0x8991, 0xB3BF, 0x8992,	0xB3C0, 0x8993, 0xB3C1, 0x8994, 0xB3C2, 0x8995, 0xB3C3, 0x8996,
+	0xB3C4, 0xB5B5, 0xB3C5, 0xB5B6, 0xB3C6, 0x8997, 0xB3C7, 0x8998,	0xB3C8, 0xB5B7, 0xB3C9, 0x8999, 0xB3CA, 0x899A, 0xB3CB, 0xB5B8,
+	0xB3CC, 0xB5B9, 0xB3CD, 0x899B, 0xB3CE, 0xB5BA, 0xB3CF, 0x899C,	0xB3D0, 0xB5BB, 0xB3D1, 0x899D, 0xB3D2, 0x899E, 0xB3D3, 0x899F,
+	0xB3D4, 0xB5BC, 0xB3D5, 0xB5BD, 0xB3D6, 0x89A0, 0xB3D7, 0xB5BE,	0xB3D8, 0x89A1, 0xB3D9, 0xB5BF, 0xB3DA, 0x89A2, 0xB3DB, 0xB5C0,
+	0xB3DC, 0x89A3, 0xB3DD, 0xB5C1, 0xB3DE, 0x89A4, 0xB3DF, 0x89A5,	0xB3E0, 0xB5C2, 0xB3E1, 0x89A6, 0xB3E2, 0x89A7, 0xB3E3, 0x89A8,
+	0xB3E4, 0xB5C3, 0xB3E5, 0x89A9, 0xB3E6, 0x89AA, 0xB3E7, 0x89AB,	0xB3E8, 0xB5C4, 0xB3E9, 0x89AC, 0xB3EA, 0x89AD, 0xB3EB, 0x89AE,
+	0xB3EC, 0x89AF, 0xB3ED, 0x89B0, 0xB3EE, 0x89B1, 0xB3EF, 0x89B2,	0xB3F0, 0x89B3, 0xB3F1, 0x89B4, 0xB3F2, 0x89B5, 0xB3F3, 0x89B6,
+	0xB3F4, 0x89B7, 0xB3F5, 0x89B8, 0xB3F6, 0x89B9, 0xB3F7, 0x89BA,	0xB3F8, 0x89BB, 0xB3F9, 0x89BC, 0xB3FA, 0x89BD, 0xB3FB, 0x89BE,
+	0xB3FC, 0xB5C5, 0xB3FD, 0x89BF, 0xB3FE, 0x89C0, 0xB3FF, 0x89C1,	0xB400, 0x89C2, 0xB401, 0x89C3, 0xB402, 0x89C4, 0xB403, 0x89C5,
+	0xB404, 0x89C6, 0xB405, 0x89C7, 0xB406, 0x89C8, 0xB407, 0x89C9,	0xB408, 0x89CA, 0xB409, 0x89CB, 0xB40A, 0x89CC, 0xB40B, 0x89CD,
+	0xB40C, 0x89CE, 0xB40D, 0x89CF, 0xB40E, 0x89D0, 0xB40F, 0x89D1,	0xB410, 0xB5C6, 0xB411, 0x89D2, 0xB412, 0x89D3, 0xB413, 0x89D4,
+	0xB414, 0x89D5, 0xB415, 0x89D6, 0xB416, 0x89D7, 0xB417, 0x89D8,	0xB418, 0xB5C7, 0xB419, 0x89D9, 0xB41A, 0x89DA, 0xB41B, 0x89DB,
+	0xB41C, 0xB5C8, 0xB41D, 0x89DC, 0xB41E, 0x89DD, 0xB41F, 0x89DE,	0xB420, 0xB5C9, 0xB421, 0x89DF, 0xB422, 0x89E0, 0xB423, 0x89E1,
+	0xB424, 0x89E2, 0xB425, 0x89E3, 0xB426, 0x89E4, 0xB427, 0x89E5,	0xB428, 0xB5CA, 0xB429, 0xB5CB, 0xB42A, 0x89E6, 0xB42B, 0xB5CC,
+	0xB42C, 0x89E7, 0xB42D, 0x89E8, 0xB42E, 0x89E9, 0xB42F, 0x89EA,	0xB430, 0x89EB, 0xB431, 0x89EC, 0xB432, 0x89ED, 0xB433, 0x89EE,
+	0xB434, 0xB5CD, 0xB435, 0x89EF, 0xB436, 0x89F0, 0xB437, 0x89F1,	0xB438, 0x89F2, 0xB439, 0x89F3, 0xB43A, 0x89F4, 0xB43B, 0x89F5,
+	0xB43C, 0x89F6, 0xB43D, 0x89F7, 0xB43E, 0x89F8, 0xB43F, 0x89F9,	0xB440, 0x89FA, 0xB441, 0x89FB, 0xB442, 0x89FC, 0xB443, 0x89FD,
+	0xB444, 0x89FE, 0xB445, 0x8A41, 0xB446, 0x8A42, 0xB447, 0x8A43,	0xB448, 0x8A44, 0xB449, 0x8A45, 0xB44A, 0x8A46, 0xB44B, 0x8A47,
+	0xB44C, 0x8A48, 0xB44D, 0x8A49, 0xB44E, 0x8A4A, 0xB44F, 0x8A4B,	0xB450, 0xB5CE, 0xB451, 0xB5CF, 0xB452, 0x8A4C, 0xB453, 0x8A4D,
+	0xB454, 0xB5D0, 0xB455, 0x8A4E, 0xB456, 0x8A4F, 0xB457, 0x8A50,	0xB458, 0xB5D1, 0xB459, 0x8A51, 0xB45A, 0x8A52, 0xB45B, 0x8A53,
+	0xB45C, 0x8A54, 0xB45D, 0x8A55, 0xB45E, 0x8A56, 0xB45F, 0x8A57,	0xB460, 0xB5D2, 0xB461, 0xB5D3, 0xB462, 0x8A58, 0xB463, 0xB5D4,
+	0xB464, 0x8A59, 0xB465, 0xB5D5, 0xB466, 0x8A5A, 0xB467, 0x8A61,	0xB468, 0x8A62, 0xB469, 0x8A63, 0xB46A, 0x8A64, 0xB46B, 0x8A65,
+	0xB46C, 0xB5D6, 0xB46D, 0x8A66, 0xB46E, 0x8A67, 0xB46F, 0x8A68,	0xB470, 0x8A69, 0xB471, 0x8A6A, 0xB472, 0x8A6B, 0xB473, 0x8A6C,
+	0xB474, 0x8A6D, 0xB475, 0x8A6E, 0xB476, 0x8A6F, 0xB477, 0x8A70,	0xB478, 0x8A71, 0xB479, 0x8A72, 0xB47A, 0x8A73, 0xB47B, 0x8A74,
+	0xB47C, 0x8A75, 0xB47D, 0x8A76, 0xB47E, 0x8A77, 0xB47F, 0x8A78,	0xB480, 0xB5D7, 0xB481, 0x8A79, 0xB482, 0x8A7A, 0xB483, 0x8A81,
+	0xB484, 0x8A82, 0xB485, 0x8A83, 0xB486, 0x8A84, 0xB487, 0x8A85,	0xB488, 0xB5D8, 0xB489, 0x8A86, 0xB48A, 0x8A87, 0xB48B, 0x8A88,
+	0xB48C, 0x8A89, 0xB48D, 0x8A8A, 0xB48E, 0x8A8B, 0xB48F, 0x8A8C,	0xB490, 0x8A8D, 0xB491, 0x8A8E, 0xB492, 0x8A8F, 0xB493, 0x8A90,
+	0xB494, 0x8A91, 0xB495, 0x8A92, 0xB496, 0x8A93, 0xB497, 0x8A94,	0xB498, 0x8A95, 0xB499, 0x8A96, 0xB49A, 0x8A97, 0xB49B, 0x8A98,
+	0xB49C, 0x8A99, 0xB49D, 0xB5D9, 0xB49E, 0x8A9A, 0xB49F, 0x8A9B,	0xB4A0, 0x8A9C, 0xB4A1, 0x8A9D, 0xB4A2, 0x8A9E, 0xB4A3, 0x8A9F,
+	0xB4A4, 0xB5DA, 0xB4A5, 0x8AA0, 0xB4A6, 0x8AA1, 0xB4A7, 0x8AA2,	0xB4A8, 0xB5DB, 0xB4A9, 0x8AA3, 0xB4AA, 0x8AA4, 0xB4AB, 0x8AA5,
+	0xB4AC, 0xB5DC, 0xB4AD, 0x8AA6, 0xB4AE, 0x8AA7, 0xB4AF, 0x8AA8,	0xB4B0, 0x8AA9, 0xB4B1, 0x8AAA, 0xB4B2, 0x8AAB, 0xB4B3, 0x8AAC,
+	0xB4B4, 0x8AAD, 0xB4B5, 0xB5DD, 0xB4B6, 0x8AAE, 0xB4B7, 0xB5DE,	0xB4B8, 0x8AAF, 0xB4B9, 0xB5DF, 0xB4BA, 0x8AB0, 0xB4BB, 0x8AB1,
+	0xB4BC, 0x8AB2, 0xB4BD, 0x8AB3, 0xB4BE, 0x8AB4, 0xB4BF, 0x8AB5,	0xB4C0, 0xB5E0, 0xB4C1, 0x8AB6, 0xB4C2, 0x8AB7, 0xB4C3, 0x8AB8,
+	0xB4C4, 0xB5E1, 0xB4C5, 0x8AB9, 0xB4C6, 0x8ABA, 0xB4C7, 0x8ABB,	0xB4C8, 0xB5E2, 0xB4C9, 0x8ABC, 0xB4CA, 0x8ABD, 0xB4CB, 0x8ABE,
+	0xB4CC, 0x8ABF, 0xB4CD, 0x8AC0, 0xB4CE, 0x8AC1, 0xB4CF, 0x8AC2,	0xB4D0, 0xB5E3, 0xB4D1, 0x8AC3, 0xB4D2, 0x8AC4, 0xB4D3, 0x8AC5,
+	0xB4D4, 0x8AC6, 0xB4D5, 0xB5E4, 0xB4D6, 0x8AC7, 0xB4D7, 0x8AC8,	0xB4D8, 0x8AC9, 0xB4D9, 0x8ACA, 0xB4DA, 0x8ACB, 0xB4DB, 0x8ACC,
+	0xB4DC, 0xB5E5, 0xB4DD, 0xB5E6, 0xB4DE, 0x8ACD, 0xB4DF, 0x8ACE,	0xB4E0, 0xB5E7, 0xB4E1, 0x8ACF, 0xB4E2, 0x8AD0, 0xB4E3, 0xB5E8,
+	0xB4E4, 0xB5E9, 0xB4E5, 0x8AD1, 0xB4E6, 0xB5EA, 0xB4E7, 0x8AD2,	0xB4E8, 0x8AD3, 0xB4E9, 0x8AD4, 0xB4EA, 0x8AD5, 0xB4EB, 0x8AD6,
+	0xB4EC, 0xB5EB, 0xB4ED, 0xB5EC, 0xB4EE, 0x8AD7, 0xB4EF, 0xB5ED,	0xB4F0, 0x8AD8, 0xB4F1, 0xB5EE, 0xB4F2, 0x8AD9, 0xB4F3, 0x8ADA,
+	0xB4F4, 0x8ADB, 0xB4F5, 0x8ADC, 0xB4F6, 0x8ADD, 0xB4F7, 0x8ADE,	0xB4F8, 0xB5EF, 0xB4F9, 0x8ADF, 0xB4FA, 0x8AE0, 0xB4FB, 0x8AE1,
+	0xB4FC, 0x8AE2, 0xB4FD, 0x8AE3, 0xB4FE, 0x8AE4, 0xB4FF, 0x8AE5,	0xB500, 0x8AE6, 0xB501, 0x8AE7, 0xB502, 0x8AE8, 0xB503, 0x8AE9,
+	0xB504, 0x8AEA, 0xB505, 0x8AEB, 0xB506, 0x8AEC, 0xB507, 0x8AED,	0xB508, 0x8AEE, 0xB509, 0x8AEF, 0xB50A, 0x8AF0, 0xB50B, 0x8AF1,
+	0xB50C, 0x8AF2, 0xB50D, 0x8AF3, 0xB50E, 0x8AF4, 0xB50F, 0x8AF5,	0xB510, 0x8AF6, 0xB511, 0x8AF7, 0xB512, 0x8AF8, 0xB513, 0x8AF9,
+	0xB514, 0xB5F0, 0xB515, 0xB5F1, 0xB516, 0x8AFA, 0xB517, 0x8AFB,	0xB518, 0xB5F2, 0xB519, 0x8AFC, 0xB51A, 0x8AFD, 0xB51B, 0xB5F3,
+	0xB51C, 0xB5F4, 0xB51D, 0x8AFE, 0xB51E, 0x8B41, 0xB51F, 0x8B42,	0xB520, 0x8B43, 0xB521, 0x8B44, 0xB522, 0x8B45, 0xB523, 0x8B46,
+	0xB524, 0xB5F5, 0xB525, 0xB5F6, 0xB526, 0x8B47, 0xB527, 0xB5F7,	0xB528, 0xB5F8, 0xB529, 0xB5F9, 0xB52A, 0xB5FA, 0xB52B, 0x8B48,
+	0xB52C, 0x8B49, 0xB52D, 0x8B4A, 0xB52E, 0x8B4B, 0xB52F, 0x8B4C,	0xB530, 0xB5FB, 0xB531, 0xB5FC, 0xB532, 0x8B4D, 0xB533, 0x8B4E,
+	0xB534, 0xB5FD, 0xB535, 0x8B4F, 0xB536, 0x8B50, 0xB537, 0x8B51,	0xB538, 0xB5FE, 0xB539, 0x8B52, 0xB53A, 0x8B53, 0xB53B, 0x8B54,
+	0xB53C, 0x8B55, 0xB53D, 0x8B56, 0xB53E, 0x8B57, 0xB53F, 0x8B58,	0xB540, 0xB6A1, 0xB541, 0xB6A2, 0xB542, 0x8B59, 0xB543, 0xB6A3,
+	0xB544, 0xB6A4, 0xB545, 0xB6A5, 0xB546, 0x8B5A, 0xB547, 0x8B61,	0xB548, 0x8B62, 0xB549, 0x8B63, 0xB54A, 0x8B64, 0xB54B, 0xB6A6,
+	0xB54C, 0xB6A7, 0xB54D, 0xB6A8, 0xB54E, 0x8B65, 0xB54F, 0x8B66,	0xB550, 0xB6A9, 0xB551, 0x8B67, 0xB552, 0x8B68, 0xB553, 0x8B69,
+	0xB554, 0xB6AA, 0xB555, 0x8B6A, 0xB556, 0x8B6B, 0xB557, 0x8B6C,	0xB558, 0x8B6D, 0xB559, 0x8B6E, 0xB55A, 0x8B6F, 0xB55B, 0x8B70,
+	0xB55C, 0xB6AB, 0xB55D, 0xB6AC, 0xB55E, 0x8B71, 0xB55F, 0xB6AD,	0xB560, 0xB6AE, 0xB561, 0xB6AF, 0xB562, 0x8B72, 0xB563, 0x8B73,
+	0xB564, 0x8B74, 0xB565, 0x8B75, 0xB566, 0x8B76, 0xB567, 0x8B77,	0xB568, 0x8B78, 0xB569, 0x8B79, 0xB56A, 0x8B7A, 0xB56B, 0x8B81,
+	0xB56C, 0x8B82, 0xB56D, 0x8B83, 0xB56E, 0x8B84, 0xB56F, 0x8B85,	0xB570, 0x8B86, 0xB571, 0x8B87, 0xB572, 0x8B88, 0xB573, 0x8B89,
+	0xB574, 0x8B8A, 0xB575, 0x8B8B, 0xB576, 0x8B8C, 0xB577, 0x8B8D,	0xB578, 0x8B8E, 0xB579, 0x8B8F, 0xB57A, 0x8B90, 0xB57B, 0x8B91,
+	0xB57C, 0x8B92, 0xB57D, 0x8B93, 0xB57E, 0x8B94, 0xB57F, 0x8B95,	0xB580, 0x8B96, 0xB581, 0x8B97, 0xB582, 0x8B98, 0xB583, 0x8B99,
+	0xB584, 0x8B9A, 0xB585, 0x8B9B, 0xB586, 0x8B9C, 0xB587, 0x8B9D,	0xB588, 0x8B9E, 0xB589, 0x8B9F, 0xB58A, 0x8BA0, 0xB58B, 0x8BA1,
+	0xB58C, 0x8BA2, 0xB58D, 0x8BA3, 0xB58E, 0x8BA4, 0xB58F, 0x8BA5,	0xB590, 0x8BA6, 0xB591, 0x8BA7, 0xB592, 0x8BA8, 0xB593, 0x8BA9,
+	0xB594, 0x8BAA, 0xB595, 0x8BAB, 0xB596, 0x8BAC, 0xB597, 0x8BAD,	0xB598, 0x8BAE, 0xB599, 0x8BAF, 0xB59A, 0x8BB0, 0xB59B, 0x8BB1,
+	0xB59C, 0x8BB2, 0xB59D, 0x8BB3, 0xB59E, 0x8BB4, 0xB59F, 0x8BB5,	0xB5A0, 0xB6B0, 0xB5A1, 0xB6B1, 0xB5A2, 0x8BB6, 0xB5A3, 0x8BB7,
+	0xB5A4, 0xB6B2, 0xB5A5, 0x8BB8, 0xB5A6, 0x8BB9, 0xB5A7, 0x8BBA,	0xB5A8, 0xB6B3, 0xB5A9, 0x8BBB, 0xB5AA, 0xB6B4, 0xB5AB, 0xB6B5,
+	0xB5AC, 0x8BBC, 0xB5AD, 0x8BBD, 0xB5AE, 0x8BBE, 0xB5AF, 0x8BBF,	0xB5B0, 0xB6B6, 0xB5B1, 0xB6B7, 0xB5B2, 0x8BC0, 0xB5B3, 0xB6B8,
+	0xB5B4, 0xB6B9, 0xB5B5, 0xB6BA, 0xB5B6, 0x8BC1, 0xB5B7, 0x8BC2,	0xB5B8, 0x8BC3, 0xB5B9, 0x8BC4, 0xB5BA, 0x8BC5, 0xB5BB, 0xB6BB,
+	0xB5BC, 0xB6BC, 0xB5BD, 0xB6BD, 0xB5BE, 0x8BC6, 0xB5BF, 0x8BC7,	0xB5C0, 0xB6BE, 0xB5C1, 0x8BC8, 0xB5C2, 0x8BC9, 0xB5C3, 0x8BCA,
+	0xB5C4, 0xB6BF, 0xB5C5, 0x8BCB, 0xB5C6, 0x8BCC, 0xB5C7, 0x8BCD,	0xB5C8, 0x8BCE, 0xB5C9, 0x8BCF, 0xB5CA, 0x8BD0, 0xB5CB, 0x8BD1,
+	0xB5CC, 0xB6C0, 0xB5CD, 0xB6C1, 0xB5CE, 0x8BD2, 0xB5CF, 0xB6C2,	0xB5D0, 0xB6C3, 0xB5D1, 0xB6C4, 0xB5D2, 0x8BD3, 0xB5D3, 0x8BD4,
+	0xB5D4, 0x8BD5, 0xB5D5, 0x8BD6, 0xB5D6, 0x8BD7, 0xB5D7, 0x8BD8,	0xB5D8, 0xB6C5, 0xB5D9, 0x8BD9, 0xB5DA, 0x8BDA, 0xB5DB, 0x8BDB,
+	0xB5DC, 0x8BDC, 0xB5DD, 0x8BDD, 0xB5DE, 0x8BDE, 0xB5DF, 0x8BDF,	0xB5E0, 0x8BE0, 0xB5E1, 0x8BE1, 0xB5E2, 0x8BE2, 0xB5E3, 0x8BE3,
+	0xB5E4, 0x8BE4, 0xB5E5, 0x8BE5, 0xB5E6, 0x8BE6, 0xB5E7, 0x8BE7,	0xB5E8, 0x8BE8, 0xB5E9, 0x8BE9, 0xB5EA, 0x8BEA, 0xB5EB, 0x8BEB,
+	0xB5EC, 0xB6C6, 0xB5ED, 0x8BEC, 0xB5EE, 0x8BED, 0xB5EF, 0x8BEE,	0xB5F0, 0x8BEF, 0xB5F1, 0x8BF0, 0xB5F2, 0x8BF1, 0xB5F3, 0x8BF2,
+	0xB5F4, 0x8BF3, 0xB5F5, 0x8BF4, 0xB5F6, 0x8BF5, 0xB5F7, 0x8BF6,	0xB5F8, 0x8BF7, 0xB5F9, 0x8BF8, 0xB5FA, 0x8BF9, 0xB5FB, 0x8BFA,
+	0xB5FC, 0x8BFB, 0xB5FD, 0x8BFC, 0xB5FE, 0x8BFD, 0xB5FF, 0x8BFE,	0xB600, 0x8C41, 0xB601, 0x8C42, 0xB602, 0x8C43, 0xB603, 0x8C44,
+	0xB604, 0x8C45, 0xB605, 0x8C46, 0xB606, 0x8C47, 0xB607, 0x8C48,	0xB608, 0x8C49, 0xB609, 0x8C4A, 0xB60A, 0x8C4B, 0xB60B, 0x8C4C,
+	0xB60C, 0x8C4D, 0xB60D, 0x8C4E, 0xB60E, 0x8C4F, 0xB60F, 0x8C50,	0xB610, 0xB6C7, 0xB611, 0xB6C8, 0xB612, 0x8C51, 0xB613, 0x8C52,
+	0xB614, 0xB6C9, 0xB615, 0x8C53, 0xB616, 0x8C54, 0xB617, 0x8C55,	0xB618, 0xB6CA, 0xB619, 0x8C56, 0xB61A, 0x8C57, 0xB61B, 0x8C58,
+	0xB61C, 0x8C59, 0xB61D, 0x8C5A, 0xB61E, 0x8C61, 0xB61F, 0x8C62,	0xB620, 0x8C63, 0xB621, 0x8C64, 0xB622, 0x8C65, 0xB623, 0x8C66,
+	0xB624, 0x8C67, 0xB625, 0xB6CB, 0xB626, 0x8C68, 0xB627, 0x8C69,	0xB628, 0x8C6A, 0xB629, 0x8C6B, 0xB62A, 0x8C6C, 0xB62B, 0x8C6D,
+	0xB62C, 0xB6CC, 0xB62D, 0x8C6E, 0xB62E, 0x8C6F, 0xB62F, 0x8C70,	0xB630, 0x8C71, 0xB631, 0x8C72, 0xB632, 0x8C73, 0xB633, 0x8C74,
+	0xB634, 0xB6CD, 0xB635, 0x8C75, 0xB636, 0x8C76, 0xB637, 0x8C77,	0xB638, 0x8C78, 0xB639, 0x8C79, 0xB63A, 0x8C7A, 0xB63B, 0x8C81,
+	0xB63C, 0x8C82, 0xB63D, 0x8C83, 0xB63E, 0x8C84, 0xB63F, 0x8C85,	0xB640, 0x8C86, 0xB641, 0x8C87, 0xB642, 0x8C88, 0xB643, 0x8C89,
+	0xB644, 0x8C8A, 0xB645, 0x8C8B, 0xB646, 0x8C8C, 0xB647, 0x8C8D,	0xB648, 0xB6CE, 0xB649, 0x8C8E, 0xB64A, 0x8C8F, 0xB64B, 0x8C90,
+	0xB64C, 0x8C91, 0xB64D, 0x8C92, 0xB64E, 0x8C93, 0xB64F, 0x8C94,	0xB650, 0x8C95, 0xB651, 0x8C96, 0xB652, 0x8C97, 0xB653, 0x8C98,
+	0xB654, 0x8C99, 0xB655, 0x8C9A, 0xB656, 0x8C9B, 0xB657, 0x8C9C,	0xB658, 0x8C9D, 0xB659, 0x8C9E, 0xB65A, 0x8C9F, 0xB65B, 0x8CA0,
+	0xB65C, 0x8CA1, 0xB65D, 0x8CA2, 0xB65E, 0x8CA3, 0xB65F, 0x8CA4,	0xB660, 0x8CA5, 0xB661, 0x8CA6, 0xB662, 0x8CA7, 0xB663, 0x8CA8,
+	0xB664, 0xB6CF, 0xB665, 0x8CA9, 0xB666, 0x8CAA, 0xB667, 0x8CAB,	0xB668, 0xB6D0, 0xB669, 0x8CAC, 0xB66A, 0x8CAD, 0xB66B, 0x8CAE,
+	0xB66C, 0x8CAF, 0xB66D, 0x8CB0, 0xB66E, 0x8CB1, 0xB66F, 0x8CB2,	0xB670, 0x8CB3, 0xB671, 0x8CB4, 0xB672, 0x8CB5, 0xB673, 0x8CB6,
+	0xB674, 0x8CB7, 0xB675, 0x8CB8, 0xB676, 0x8CB9, 0xB677, 0x8CBA,	0xB678, 0x8CBB, 0xB679, 0x8CBC, 0xB67A, 0x8CBD, 0xB67B, 0x8CBE,
+	0xB67C, 0x8CBF, 0xB67D, 0x8CC0, 0xB67E, 0x8CC1, 0xB67F, 0x8CC2,	0xB680, 0x8CC3, 0xB681, 0x8CC4, 0xB682, 0x8CC5, 0xB683, 0x8CC6,
+	0xB684, 0x8CC7, 0xB685, 0x8CC8, 0xB686, 0x8CC9, 0xB687, 0x8CCA,	0xB688, 0x8CCB, 0xB689, 0x8CCC, 0xB68A, 0x8CCD, 0xB68B, 0x8CCE,
+	0xB68C, 0x8CCF, 0xB68D, 0x8CD0, 0xB68E, 0x8CD1, 0xB68F, 0x8CD2,	0xB690, 0x8CD3, 0xB691, 0x8CD4, 0xB692, 0x8CD5, 0xB693, 0x8CD6,
+	0xB694, 0x8CD7, 0xB695, 0x8CD8, 0xB696, 0x8CD9, 0xB697, 0x8CDA,	0xB698, 0x8CDB, 0xB699, 0x8CDC, 0xB69A, 0x8CDD, 0xB69B, 0x8CDE,
+	0xB69C, 0xB6D1, 0xB69D, 0xB6D2, 0xB69E, 0x8CDF, 0xB69F, 0x8CE0,	0xB6A0, 0xB6D3, 0xB6A1, 0x8CE1, 0xB6A2, 0x8CE2, 0xB6A3, 0x8CE3,
+	0xB6A4, 0xB6D4, 0xB6A5, 0x8CE4, 0xB6A6, 0x8CE5, 0xB6A7, 0x8CE6,	0xB6A8, 0x8CE7, 0xB6A9, 0x8CE8, 0xB6AA, 0x8CE9, 0xB6AB, 0xB6D5,
+	0xB6AC, 0xB6D6, 0xB6AD, 0x8CEA, 0xB6AE, 0x8CEB, 0xB6AF, 0x8CEC,	0xB6B0, 0x8CED, 0xB6B1, 0xB6D7, 0xB6B2, 0x8CEE, 0xB6B3, 0x8CEF,
+	0xB6B4, 0x8CF0, 0xB6B5, 0x8CF1, 0xB6B6, 0x8CF2, 0xB6B7, 0x8CF3,	0xB6B8, 0x8CF4, 0xB6B9, 0x8CF5, 0xB6BA, 0x8CF6, 0xB6BB, 0x8CF7,
+	0xB6BC, 0x8CF8, 0xB6BD, 0x8CF9, 0xB6BE, 0x8CFA, 0xB6BF, 0x8CFB,	0xB6C0, 0x8CFC, 0xB6C1, 0x8CFD, 0xB6C2, 0x8CFE, 0xB6C3, 0x8D41,
+	0xB6C4, 0x8D42, 0xB6C5, 0x8D43, 0xB6C6, 0x8D44, 0xB6C7, 0x8D45,	0xB6C8, 0x8D46, 0xB6C9, 0x8D47, 0xB6CA, 0x8D48, 0xB6CB, 0x8D49,
+	0xB6CC, 0x8D4A, 0xB6CD, 0x8D4B, 0xB6CE, 0x8D4C, 0xB6CF, 0x8D4D,	0xB6D0, 0x8D4E, 0xB6D1, 0x8D4F, 0xB6D2, 0x8D50, 0xB6D3, 0x8D51,
+	0xB6D4, 0xB6D8, 0xB6D5, 0x8D52, 0xB6D6, 0x8D53, 0xB6D7, 0x8D54,	0xB6D8, 0x8D55, 0xB6D9, 0x8D56, 0xB6DA, 0x8D57, 0xB6DB, 0x8D58,
+	0xB6DC, 0x8D59, 0xB6DD, 0x8D5A, 0xB6DE, 0x8D61, 0xB6DF, 0x8D62,	0xB6E0, 0x8D63, 0xB6E1, 0x8D64, 0xB6E2, 0x8D65, 0xB6E3, 0x8D66,
+	0xB6E4, 0x8D67, 0xB6E5, 0x8D68, 0xB6E6, 0x8D69, 0xB6E7, 0x8D6A,	0xB6E8, 0x8D6B, 0xB6E9, 0x8D6C, 0xB6EA, 0x8D6D, 0xB6EB, 0x8D6E,
+	0xB6EC, 0x8D6F, 0xB6ED, 0x8D70, 0xB6EE, 0x8D71, 0xB6EF, 0x8D72,	0xB6F0, 0xB6D9, 0xB6F1, 0x8D73, 0xB6F2, 0x8D74, 0xB6F3, 0x8D75,
+	0xB6F4, 0xB6DA, 0xB6F5, 0x8D76, 0xB6F6, 0x8D77, 0xB6F7, 0x8D78,	0xB6F8, 0xB6DB, 0xB6F9, 0x8D79, 0xB6FA, 0x8D7A, 0xB6FB, 0x8D81,
+	0xB6FC, 0x8D82, 0xB6FD, 0x8D83, 0xB6FE, 0x8D84, 0xB6FF, 0x8D85,	0xB700, 0xB6DC, 0xB701, 0xB6DD, 0xB702, 0x8D86, 0xB703, 0x8D87,
+	0xB704, 0x8D88, 0xB705, 0xB6DE, 0xB706, 0x8D89, 0xB707, 0x8D8A,	0xB708, 0x8D8B, 0xB709, 0x8D8C, 0xB70A, 0x8D8D, 0xB70B, 0x8D8E,
+	0xB70C, 0x8D8F, 0xB70D, 0x8D90, 0xB70E, 0x8D91, 0xB70F, 0x8D92,	0xB710, 0x8D93, 0xB711, 0x8D94, 0xB712, 0x8D95, 0xB713, 0x8D96,
+	0xB714, 0x8D97, 0xB715, 0x8D98, 0xB716, 0x8D99, 0xB717, 0x8D9A,	0xB718, 0x8D9B, 0xB719, 0x8D9C, 0xB71A, 0x8D9D, 0xB71B, 0x8D9E,
+	0xB71C, 0x8D9F, 0xB71D, 0x8DA0, 0xB71E, 0x8DA1, 0xB71F, 0x8DA2,	0xB720, 0x8DA3, 0xB721, 0x8DA4, 0xB722, 0x8DA5, 0xB723, 0x8DA6,
+	0xB724, 0x8DA7, 0xB725, 0x8DA8, 0xB726, 0x8DA9, 0xB727, 0x8DAA,	0xB728, 0xB6DF, 0xB729, 0xB6E0, 0xB72A, 0x8DAB, 0xB72B, 0x8DAC,
+	0xB72C, 0xB6E1, 0xB72D, 0x8DAD, 0xB72E, 0x8DAE, 0xB72F, 0xB6E2,	0xB730, 0xB6E3, 0xB731, 0x8DAF, 0xB732, 0x8DB0, 0xB733, 0x8DB1,
+	0xB734, 0x8DB2, 0xB735, 0x8DB3, 0xB736, 0x8DB4, 0xB737, 0x8DB5,	0xB738, 0xB6E4, 0xB739, 0xB6E5, 0xB73A, 0x8DB6, 0xB73B, 0xB6E6,
+	0xB73C, 0x8DB7, 0xB73D, 0x8DB8, 0xB73E, 0x8DB9, 0xB73F, 0x8DBA,	0xB740, 0x8DBB, 0xB741, 0x8DBC, 0xB742, 0x8DBD, 0xB743, 0x8DBE,
+	0xB744, 0xB6E7, 0xB745, 0x8DBF, 0xB746, 0x8DC0, 0xB747, 0x8DC1,	0xB748, 0xB6E8, 0xB749, 0x8DC2, 0xB74A, 0x8DC3, 0xB74B, 0x8DC4,
+	0xB74C, 0xB6E9, 0xB74D, 0x8DC5, 0xB74E, 0x8DC6, 0xB74F, 0x8DC7,	0xB750, 0x8DC8, 0xB751, 0x8DC9, 0xB752, 0x8DCA, 0xB753, 0x8DCB,
+	0xB754, 0xB6EA, 0xB755, 0xB6EB, 0xB756, 0x8DCC, 0xB757, 0x8DCD,	0xB758, 0x8DCE, 0xB759, 0x8DCF, 0xB75A, 0x8DD0, 0xB75B, 0x8DD1,
+	0xB75C, 0x8DD2, 0xB75D, 0x8DD3, 0xB75E, 0x8DD4, 0xB75F, 0x8DD5,	0xB760, 0xB6EC, 0xB761, 0x8DD6, 0xB762, 0x8DD7, 0xB763, 0x8DD8,
+	0xB764, 0xB6ED, 0xB765, 0x8DD9, 0xB766, 0x8DDA, 0xB767, 0x8DDB,	0xB768, 0xB6EE, 0xB769, 0x8DDC, 0xB76A, 0x8DDD, 0xB76B, 0x8DDE,
+	0xB76C, 0x8DDF, 0xB76D, 0x8DE0, 0xB76E, 0x8DE1, 0xB76F, 0x8DE2,	0xB770, 0xB6EF, 0xB771, 0xB6F0, 0xB772, 0x8DE3, 0xB773, 0xB6F1,
+	0xB774, 0x8DE4, 0xB775, 0xB6F2, 0xB776, 0x8DE5, 0xB777, 0x8DE6,	0xB778, 0x8DE7, 0xB779, 0x8DE8, 0xB77A, 0x8DE9, 0xB77B, 0x8DEA,
+	0xB77C, 0xB6F3, 0xB77D, 0xB6F4, 0xB77E, 0x8DEB, 0xB77F, 0x8DEC,	0xB780, 0xB6F5, 0xB781, 0x8DED, 0xB782, 0x8DEE, 0xB783, 0x8DEF,
+	0xB784, 0xB6F6, 0xB785, 0x8DF0, 0xB786, 0x8DF1, 0xB787, 0x8DF2,	0xB788, 0x8DF3, 0xB789, 0x8DF4, 0xB78A, 0x8DF5, 0xB78B, 0x8DF6,
+	0xB78C, 0xB6F7, 0xB78D, 0xB6F8, 0xB78E, 0x8DF7, 0xB78F, 0xB6F9,	0xB790, 0xB6FA, 0xB791, 0xB6FB, 0xB792, 0xB6FC, 0xB793, 0x8DF8,
+	0xB794, 0x8DF9, 0xB795, 0x8DFA, 0xB796, 0xB6FD, 0xB797, 0xB6FE,	0xB798, 0xB7A1, 0xB799, 0xB7A2, 0xB79A, 0x8DFB, 0xB79B, 0x8DFC,
+	0xB79C, 0xB7A3, 0xB79D, 0x8DFD, 0xB79E, 0x8DFE, 0xB79F, 0x8E41,	0xB7A0, 0xB7A4, 0xB7A1, 0x8E42, 0xB7A2, 0x8E43, 0xB7A3, 0x8E44,
+	0xB7A4, 0x8E45, 0xB7A5, 0x8E46, 0xB7A6, 0x8E47, 0xB7A7, 0x8E48,	0xB7A8, 0xB7A5, 0xB7A9, 0xB7A6, 0xB7AA, 0x8E49, 0xB7AB, 0xB7A7,
+	0xB7AC, 0xB7A8, 0xB7AD, 0xB7A9, 0xB7AE, 0x8E4A, 0xB7AF, 0x8E4B,	0xB7B0, 0x8E4C, 0xB7B1, 0x8E4D, 0xB7B2, 0x8E4E, 0xB7B3, 0x8E4F,
+	0xB7B4, 0xB7AA, 0xB7B5, 0xB7AB, 0xB7B6, 0x8E50, 0xB7B7, 0x8E51,	0xB7B8, 0xB7AC, 0xB7B9, 0x8E52, 0xB7BA, 0x8E53, 0xB7BB, 0x8E54,
+	0xB7BC, 0x8E55, 0xB7BD, 0x8E56, 0xB7BE, 0x8E57, 0xB7BF, 0x8E58,	0xB7C0, 0x8E59, 0xB7C1, 0x8E5A, 0xB7C2, 0x8E61, 0xB7C3, 0x8E62,
+	0xB7C4, 0x8E63, 0xB7C5, 0x8E64, 0xB7C6, 0x8E65, 0xB7C7, 0xB7AD,	0xB7C8, 0x8E66, 0xB7C9, 0xB7AE, 0xB7CA, 0x8E67, 0xB7CB, 0x8E68,
+	0xB7CC, 0x8E69, 0xB7CD, 0x8E6A, 0xB7CE, 0x8E6B, 0xB7CF, 0x8E6C,	0xB7D0, 0x8E6D, 0xB7D1, 0x8E6E, 0xB7D2, 0x8E6F, 0xB7D3, 0x8E70,
+	0xB7D4, 0x8E71, 0xB7D5, 0x8E72, 0xB7D6, 0x8E73, 0xB7D7, 0x8E74,	0xB7D8, 0x8E75, 0xB7D9, 0x8E76, 0xB7DA, 0x8E77, 0xB7DB, 0x8E78,
+	0xB7DC, 0x8E79, 0xB7DD, 0x8E7A, 0xB7DE, 0x8E81, 0xB7DF, 0x8E82,	0xB7E0, 0x8E83, 0xB7E1, 0x8E84, 0xB7E2, 0x8E85, 0xB7E3, 0x8E86,
+	0xB7E4, 0x8E87, 0xB7E5, 0x8E88, 0xB7E6, 0x8E89, 0xB7E7, 0x8E8A,	0xB7E8, 0x8E8B, 0xB7E9, 0x8E8C, 0xB7EA, 0x8E8D, 0xB7EB, 0x8E8E,
+	0xB7EC, 0xB7AF, 0xB7ED, 0xB7B0, 0xB7EE, 0x8E8F, 0xB7EF, 0x8E90,	0xB7F0, 0xB7B1, 0xB7F1, 0x8E91, 0xB7F2, 0x8E92, 0xB7F3, 0x8E93,
+	0xB7F4, 0xB7B2, 0xB7F5, 0x8E94, 0xB7F6, 0x8E95, 0xB7F7, 0x8E96,	0xB7F8, 0x8E97, 0xB7F9, 0x8E98, 0xB7FA, 0x8E99, 0xB7FB, 0x8E9A,
+	0xB7FC, 0xB7B3, 0xB7FD, 0xB7B4, 0xB7FE, 0x8E9B, 0xB7FF, 0xB7B5,	0xB800, 0xB7B6, 0xB801, 0xB7B7, 0xB802, 0x8E9C, 0xB803, 0x8E9D,
+	0xB804, 0x8E9E, 0xB805, 0x8E9F, 0xB806, 0x8EA0, 0xB807, 0xB7B8,	0xB808, 0xB7B9, 0xB809, 0xB7BA, 0xB80A, 0x8EA1, 0xB80B, 0x8EA2,
+	0xB80C, 0xB7BB, 0xB80D, 0x8EA3, 0xB80E, 0x8EA4, 0xB80F, 0x8EA5,	0xB810, 0xB7BC, 0xB811, 0x8EA6, 0xB812, 0x8EA7, 0xB813, 0x8EA8,
+	0xB814, 0x8EA9, 0xB815, 0x8EAA, 0xB816, 0x8EAB, 0xB817, 0x8EAC,	0xB818, 0xB7BD, 0xB819, 0xB7BE, 0xB81A, 0x8EAD, 0xB81B, 0xB7BF,
+	0xB81C, 0x8EAE, 0xB81D, 0xB7C0, 0xB81E, 0x8EAF, 0xB81F, 0x8EB0,	0xB820, 0x8EB1, 0xB821, 0x8EB2, 0xB822, 0x8EB3, 0xB823, 0x8EB4,
+	0xB824, 0xB7C1, 0xB825, 0xB7C2, 0xB826, 0x8EB5, 0xB827, 0x8EB6,	0xB828, 0xB7C3, 0xB829, 0x8EB7, 0xB82A, 0x8EB8, 0xB82B, 0x8EB9,
+	0xB82C, 0xB7C4, 0xB82D, 0x8EBA, 0xB82E, 0x8EBB, 0xB82F, 0x8EBC,	0xB830, 0x8EBD, 0xB831, 0x8EBE, 0xB832, 0x8EBF, 0xB833, 0x8EC0,
+	0xB834, 0xB7C5, 0xB835, 0xB7C6, 0xB836, 0x8EC1, 0xB837, 0xB7C7,	0xB838, 0xB7C8, 0xB839, 0xB7C9, 0xB83A, 0x8EC2, 0xB83B, 0x8EC3,
+	0xB83C, 0x8EC4, 0xB83D, 0x8EC5, 0xB83E, 0x8EC6, 0xB83F, 0x8EC7,	0xB840, 0xB7CA, 0xB841, 0x8EC8, 0xB842, 0x8EC9, 0xB843, 0x8ECA,
+	0xB844, 0xB7CB, 0xB845, 0x8ECB, 0xB846, 0x8ECC, 0xB847, 0x8ECD,	0xB848, 0x8ECE, 0xB849, 0x8ECF, 0xB84A, 0x8ED0, 0xB84B, 0x8ED1,
+	0xB84C, 0x8ED2, 0xB84D, 0x8ED3, 0xB84E, 0x8ED4, 0xB84F, 0x8ED5,	0xB850, 0x8ED6, 0xB851, 0xB7CC, 0xB852, 0x8ED7, 0xB853, 0xB7CD,
+	0xB854, 0x8ED8, 0xB855, 0x8ED9, 0xB856, 0x8EDA, 0xB857, 0x8EDB,	0xB858, 0x8EDC, 0xB859, 0x8EDD, 0xB85A, 0x8EDE, 0xB85B, 0x8EDF,
+	0xB85C, 0xB7CE, 0xB85D, 0xB7CF, 0xB85E, 0x8EE0, 0xB85F, 0x8EE1,	0xB860, 0xB7D0, 0xB861, 0x8EE2, 0xB862, 0x8EE3, 0xB863, 0x8EE4,
+	0xB864, 0xB7D1, 0xB865, 0x8EE5, 0xB866, 0x8EE6, 0xB867, 0x8EE7,	0xB868, 0x8EE8, 0xB869, 0x8EE9, 0xB86A, 0x8EEA, 0xB86B, 0x8EEB,
+	0xB86C, 0xB7D2, 0xB86D, 0xB7D3, 0xB86E, 0x8EEC, 0xB86F, 0xB7D4,	0xB870, 0x8EED, 0xB871, 0xB7D5, 0xB872, 0x8EEE, 0xB873, 0x8EEF,
+	0xB874, 0x8EF0, 0xB875, 0x8EF1, 0xB876, 0x8EF2, 0xB877, 0x8EF3,	0xB878, 0xB7D6, 0xB879, 0x8EF4, 0xB87A, 0x8EF5, 0xB87B, 0x8EF6,
+	0xB87C, 0xB7D7, 0xB87D, 0x8EF7, 0xB87E, 0x8EF8, 0xB87F, 0x8EF9,	0xB880, 0x8EFA, 0xB881, 0x8EFB, 0xB882, 0x8EFC, 0xB883, 0x8EFD,
+	0xB884, 0x8EFE, 0xB885, 0x8F41, 0xB886, 0x8F42, 0xB887, 0x8F43,	0xB888, 0x8F44, 0xB889, 0x8F45, 0xB88A, 0x8F46, 0xB88B, 0x8F47,
+	0xB88C, 0x8F48, 0xB88D, 0xB7D8, 0xB88E, 0x8F49, 0xB88F, 0x8F4A,	0xB890, 0x8F4B, 0xB891, 0x8F4C, 0xB892, 0x8F4D, 0xB893, 0x8F4E,
+	0xB894, 0x8F4F, 0xB895, 0x8F50, 0xB896, 0x8F51, 0xB897, 0x8F52,	0xB898, 0x8F53, 0xB899, 0x8F54, 0xB89A, 0x8F55, 0xB89B, 0x8F56,
+	0xB89C, 0x8F57, 0xB89D, 0x8F58, 0xB89E, 0x8F59, 0xB89F, 0x8F5A,	0xB8A0, 0x8F61, 0xB8A1, 0x8F62, 0xB8A2, 0x8F63, 0xB8A3, 0x8F64,
+	0xB8A4, 0x8F65, 0xB8A5, 0x8F66, 0xB8A6, 0x8F67, 0xB8A7, 0x8F68,	0xB8A8, 0xB7D9, 0xB8A9, 0x8F69, 0xB8AA, 0x8F6A, 0xB8AB, 0x8F6B,
+	0xB8AC, 0x8F6C, 0xB8AD, 0x8F6D, 0xB8AE, 0x8F6E, 0xB8AF, 0x8F6F,	0xB8B0, 0xB7DA, 0xB8B1, 0x8F70, 0xB8B2, 0x8F71, 0xB8B3, 0x8F72,
+	0xB8B4, 0xB7DB, 0xB8B5, 0x8F73, 0xB8B6, 0x8F74, 0xB8B7, 0x8F75,	0xB8B8, 0xB7DC, 0xB8B9, 0x8F76, 0xB8BA, 0x8F77, 0xB8BB, 0x8F78,
+	0xB8BC, 0x8F79, 0xB8BD, 0x8F7A, 0xB8BE, 0x8F81, 0xB8BF, 0x8F82,	0xB8C0, 0xB7DD, 0xB8C1, 0xB7DE, 0xB8C2, 0x8F83, 0xB8C3, 0xB7DF,
+	0xB8C4, 0x8F84, 0xB8C5, 0xB7E0, 0xB8C6, 0x8F85, 0xB8C7, 0x8F86,	0xB8C8, 0x8F87, 0xB8C9, 0x8F88, 0xB8CA, 0x8F89, 0xB8CB, 0x8F8A,
+	0xB8CC, 0xB7E1, 0xB8CD, 0x8F8B, 0xB8CE, 0x8F8C, 0xB8CF, 0x8F8D,	0xB8D0, 0xB7E2, 0xB8D1, 0x8F8E, 0xB8D2, 0x8F8F, 0xB8D3, 0x8F90,
+	0xB8D4, 0xB7E3, 0xB8D5, 0x8F91, 0xB8D6, 0x8F92, 0xB8D7, 0x8F93,	0xB8D8, 0x8F94, 0xB8D9, 0x8F95, 0xB8DA, 0x8F96, 0xB8DB, 0x8F97,
+	0xB8DC, 0x8F98, 0xB8DD, 0xB7E4, 0xB8DE, 0x8F99, 0xB8DF, 0xB7E5,	0xB8E0, 0x8F9A, 0xB8E1, 0xB7E6, 0xB8E2, 0x8F9B, 0xB8E3, 0x8F9C,
+	0xB8E4, 0x8F9D, 0xB8E5, 0x8F9E, 0xB8E6, 0x8F9F, 0xB8E7, 0x8FA0,	0xB8E8, 0xB7E7, 0xB8E9, 0xB7E8, 0xB8EA, 0x8FA1, 0xB8EB, 0x8FA2,
+	0xB8EC, 0xB7E9, 0xB8ED, 0x8FA3, 0xB8EE, 0x8FA4, 0xB8EF, 0x8FA5,	0xB8F0, 0xB7EA, 0xB8F1, 0x8FA6, 0xB8F2, 0x8FA7, 0xB8F3, 0x8FA8,
+	0xB8F4, 0x8FA9, 0xB8F5, 0x8FAA, 0xB8F6, 0x8FAB, 0xB8F7, 0x8FAC,	0xB8F8, 0xB7EB, 0xB8F9, 0xB7EC, 0xB8FA, 0x8FAD, 0xB8FB, 0xB7ED,
+	0xB8FC, 0x8FAE, 0xB8FD, 0xB7EE, 0xB8FE, 0x8FAF, 0xB8FF, 0x8FB0,	0xB900, 0x8FB1, 0xB901, 0x8FB2, 0xB902, 0x8FB3, 0xB903, 0x8FB4,
+	0xB904, 0xB7EF, 0xB905, 0x8FB5, 0xB906, 0x8FB6, 0xB907, 0x8FB7,	0xB908, 0x8FB8, 0xB909, 0x8FB9, 0xB90A, 0x8FBA, 0xB90B, 0x8FBB,
+	0xB90C, 0x8FBC, 0xB90D, 0x8FBD, 0xB90E, 0x8FBE, 0xB90F, 0x8FBF,	0xB910, 0x8FC0, 0xB911, 0x8FC1, 0xB912, 0x8FC2, 0xB913, 0x8FC3,
+	0xB914, 0x8FC4, 0xB915, 0x8FC5, 0xB916, 0x8FC6, 0xB917, 0x8FC7,	0xB918, 0xB7F0, 0xB919, 0x8FC8, 0xB91A, 0x8FC9, 0xB91B, 0x8FCA,
+	0xB91C, 0x8FCB, 0xB91D, 0x8FCC, 0xB91E, 0x8FCD, 0xB91F, 0x8FCE,	0xB920, 0xB7F1, 0xB921, 0x8FCF, 0xB922, 0x8FD0, 0xB923, 0x8FD1,
+	0xB924, 0x8FD2, 0xB925, 0x8FD3, 0xB926, 0x8FD4, 0xB927, 0x8FD5,	0xB928, 0x8FD6, 0xB929, 0x8FD7, 0xB92A, 0x8FD8, 0xB92B, 0x8FD9,
+	0xB92C, 0x8FDA, 0xB92D, 0x8FDB, 0xB92E, 0x8FDC, 0xB92F, 0x8FDD,	0xB930, 0x8FDE, 0xB931, 0x8FDF, 0xB932, 0x8FE0, 0xB933, 0x8FE1,
+	0xB934, 0x8FE2, 0xB935, 0x8FE3, 0xB936, 0x8FE4, 0xB937, 0x8FE5,	0xB938, 0x8FE6, 0xB939, 0x8FE7, 0xB93A, 0x8FE8, 0xB93B, 0x8FE9,
+	0xB93C, 0xB7F2, 0xB93D, 0xB7F3, 0xB93E, 0x8FEA, 0xB93F, 0x8FEB,	0xB940, 0xB7F4, 0xB941, 0x8FEC, 0xB942, 0x8FED, 0xB943, 0x8FEE,
+	0xB944, 0xB7F5, 0xB945, 0x8FEF, 0xB946, 0x8FF0, 0xB947, 0x8FF1,	0xB948, 0x8FF2, 0xB949, 0x8FF3, 0xB94A, 0x8FF4, 0xB94B, 0x8FF5,
+	0xB94C, 0xB7F6, 0xB94D, 0x8FF6, 0xB94E, 0x8FF7, 0xB94F, 0xB7F7,	0xB950, 0x8FF8, 0xB951, 0xB7F8, 0xB952, 0x8FF9, 0xB953, 0x8FFA,
+	0xB954, 0x8FFB, 0xB955, 0x8FFC, 0xB956, 0x8FFD, 0xB957, 0x8FFE,	0xB958, 0xB7F9, 0xB959, 0xB7FA, 0xB95A, 0x9041, 0xB95B, 0x9042,
+	0xB95C, 0xB7FB, 0xB95D, 0x9043, 0xB95E, 0x9044, 0xB95F, 0x9045,	0xB960, 0xB7FC, 0xB961, 0x9046, 0xB962, 0x9047, 0xB963, 0x9048,
+	0xB964, 0x9049, 0xB965, 0x904A, 0xB966, 0x904B, 0xB967, 0x904C,	0xB968, 0xB7FD, 0xB969, 0xB7FE, 0xB96A, 0x904D, 0xB96B, 0xB8A1,
+	0xB96C, 0x904E, 0xB96D, 0xB8A2, 0xB96E, 0x904F, 0xB96F, 0x9050,	0xB970, 0x9051, 0xB971, 0x9052, 0xB972, 0x9053, 0xB973, 0x9054,
+	0xB974, 0xB8A3, 0xB975, 0xB8A4, 0xB976, 0x9055, 0xB977, 0x9056,	0xB978, 0xB8A5, 0xB979, 0x9057, 0xB97A, 0x9058, 0xB97B, 0x9059,
+	0xB97C, 0xB8A6, 0xB97D, 0x905A, 0xB97E, 0x9061, 0xB97F, 0x9062,	0xB980, 0x9063, 0xB981, 0x9064, 0xB982, 0x9065, 0xB983, 0x9066,
+	0xB984, 0xB8A7, 0xB985, 0xB8A8, 0xB986, 0x9067, 0xB987, 0xB8A9,	0xB988, 0x9068, 0xB989, 0xB8AA, 0xB98A, 0xB8AB, 0xB98B, 0x9069,
+	0xB98C, 0x906A, 0xB98D, 0xB8AC, 0xB98E, 0xB8AD, 0xB98F, 0x906B,	0xB990, 0x906C, 0xB991, 0x906D, 0xB992, 0x906E, 0xB993, 0x906F,
+	0xB994, 0x9070, 0xB995, 0x9071, 0xB996, 0x9072, 0xB997, 0x9073,	0xB998, 0x9074, 0xB999, 0x9075, 0xB99A, 0x9076, 0xB99B, 0x9077,
+	0xB99C, 0x9078, 0xB99D, 0x9079, 0xB99E, 0x907A, 0xB99F, 0x9081,	0xB9A0, 0x9082, 0xB9A1, 0x9083, 0xB9A2, 0x9084, 0xB9A3, 0x9085,
+	0xB9A4, 0x9086, 0xB9A5, 0x9087, 0xB9A6, 0x9088, 0xB9A7, 0x9089,	0xB9A8, 0x908A, 0xB9A9, 0x908B, 0xB9AA, 0x908C, 0xB9AB, 0x908D,
+	0xB9AC, 0xB8AE, 0xB9AD, 0xB8AF, 0xB9AE, 0x908E, 0xB9AF, 0x908F,	0xB9B0, 0xB8B0, 0xB9B1, 0x9090, 0xB9B2, 0x9091, 0xB9B3, 0x9092,
+	0xB9B4, 0xB8B1, 0xB9B5, 0x9093, 0xB9B6, 0x9094, 0xB9B7, 0x9095,	0xB9B8, 0x9096, 0xB9B9, 0x9097, 0xB9BA, 0x9098, 0xB9BB, 0x9099,
+	0xB9BC, 0xB8B2, 0xB9BD, 0xB8B3, 0xB9BE, 0x909A, 0xB9BF, 0xB8B4,	0xB9C0, 0x909B, 0xB9C1, 0xB8B5, 0xB9C2, 0x909C, 0xB9C3, 0x909D,
+	0xB9C4, 0x909E, 0xB9C5, 0x909F, 0xB9C6, 0x90A0, 0xB9C7, 0x90A1,	0xB9C8, 0xB8B6, 0xB9C9, 0xB8B7, 0xB9CA, 0x90A2, 0xB9CB, 0x90A3,
+	0xB9CC, 0xB8B8, 0xB9CD, 0x90A4, 0xB9CE, 0xB8B9, 0xB9CF, 0xB8BA,	0xB9D0, 0xB8BB, 0xB9D1, 0xB8BC, 0xB9D2, 0xB8BD, 0xB9D3, 0x90A5,
+	0xB9D4, 0x90A6, 0xB9D5, 0x90A7, 0xB9D6, 0x90A8, 0xB9D7, 0x90A9,	0xB9D8, 0xB8BE, 0xB9D9, 0xB8BF, 0xB9DA, 0x90AA, 0xB9DB, 0xB8C0,
+	0xB9DC, 0x90AB, 0xB9DD, 0xB8C1, 0xB9DE, 0xB8C2, 0xB9DF, 0x90AC,	0xB9E0, 0x90AD, 0xB9E1, 0xB8C3, 0xB9E2, 0x90AE, 0xB9E3, 0xB8C4,
+	0xB9E4, 0xB8C5, 0xB9E5, 0xB8C6, 0xB9E6, 0x90AF, 0xB9E7, 0x90B0,	0xB9E8, 0xB8C7, 0xB9E9, 0x90B1, 0xB9EA, 0x90B2, 0xB9EB, 0x90B3,
+	0xB9EC, 0xB8C8, 0xB9ED, 0x90B4, 0xB9EE, 0x90B5, 0xB9EF, 0x90B6,	0xB9F0, 0x90B7, 0xB9F1, 0x90B8, 0xB9F2, 0x90B9, 0xB9F3, 0x90BA,
+	0xB9F4, 0xB8C9, 0xB9F5, 0xB8CA, 0xB9F6, 0x90BB, 0xB9F7, 0xB8CB,	0xB9F8, 0xB8CC, 0xB9F9, 0xB8CD, 0xB9FA, 0xB8CE, 0xB9FB, 0x90BC,
+	0xB9FC, 0x90BD, 0xB9FD, 0x90BE, 0xB9FE, 0x90BF, 0xB9FF, 0x90C0,	0xBA00, 0xB8CF, 0xBA01, 0xB8D0, 0xBA02, 0x90C1, 0xBA03, 0x90C2,
+	0xBA04, 0x90C3, 0xBA05, 0x90C4, 0xBA06, 0x90C5, 0xBA07, 0x90C6,	0xBA08, 0xB8D1, 0xBA09, 0x90C7, 0xBA0A, 0x90C8, 0xBA0B, 0x90C9,
+	0xBA0C, 0x90CA, 0xBA0D, 0x90CB, 0xBA0E, 0x90CC, 0xBA0F, 0x90CD,	0xBA10, 0x90CE, 0xBA11, 0x90CF, 0xBA12, 0x90D0, 0xBA13, 0x90D1,
+	0xBA14, 0x90D2, 0xBA15, 0xB8D2, 0xBA16, 0x90D3, 0xBA17, 0x90D4,	0xBA18, 0x90D5, 0xBA19, 0x90D6, 0xBA1A, 0x90D7, 0xBA1B, 0x90D8,
+	0xBA1C, 0x90D9, 0xBA1D, 0x90DA, 0xBA1E, 0x90DB, 0xBA1F, 0x90DC,	0xBA20, 0x90DD, 0xBA21, 0x90DE, 0xBA22, 0x90DF, 0xBA23, 0x90E0,
+	0xBA24, 0x90E1, 0xBA25, 0x90E2, 0xBA26, 0x90E3, 0xBA27, 0x90E4,	0xBA28, 0x90E5, 0xBA29, 0x90E6, 0xBA2A, 0x90E7, 0xBA2B, 0x90E8,
+	0xBA2C, 0x90E9, 0xBA2D, 0x90EA, 0xBA2E, 0x90EB, 0xBA2F, 0x90EC,	0xBA30, 0x90ED, 0xBA31, 0x90EE, 0xBA32, 0x90EF, 0xBA33, 0x90F0,
+	0xBA34, 0x90F1, 0xBA35, 0x90F2, 0xBA36, 0x90F3, 0xBA37, 0x90F4,	0xBA38, 0xB8D3, 0xBA39, 0xB8D4, 0xBA3A, 0x90F5, 0xBA3B, 0x90F6,
+	0xBA3C, 0xB8D5, 0xBA3D, 0x90F7, 0xBA3E, 0x90F8, 0xBA3F, 0x90F9,	0xBA40, 0xB8D6, 0xBA41, 0x90FA, 0xBA42, 0xB8D7, 0xBA43, 0x90FB,
+	0xBA44, 0x90FC, 0xBA45, 0x90FD, 0xBA46, 0x90FE, 0xBA47, 0x9141,	0xBA48, 0xB8D8, 0xBA49, 0xB8D9, 0xBA4A, 0x9142, 0xBA4B, 0xB8DA,
+	0xBA4C, 0x9143, 0xBA4D, 0xB8DB, 0xBA4E, 0xB8DC, 0xBA4F, 0x9144,	0xBA50, 0x9145, 0xBA51, 0x9146, 0xBA52, 0x9147, 0xBA53, 0xB8DD,
+	0xBA54, 0xB8DE, 0xBA55, 0xB8DF, 0xBA56, 0x9148, 0xBA57, 0x9149,	0xBA58, 0xB8E0, 0xBA59, 0x914A, 0xBA5A, 0x914B, 0xBA5B, 0x914C,
+	0xBA5C, 0xB8E1, 0xBA5D, 0x914D, 0xBA5E, 0x914E, 0xBA5F, 0x914F,	0xBA60, 0x9150, 0xBA61, 0x9151, 0xBA62, 0x9152, 0xBA63, 0x9153,
+	0xBA64, 0xB8E2, 0xBA65, 0xB8E3, 0xBA66, 0x9154, 0xBA67, 0xB8E4,	0xBA68, 0xB8E5, 0xBA69, 0xB8E6, 0xBA6A, 0x9155, 0xBA6B, 0x9156,
+	0xBA6C, 0x9157, 0xBA6D, 0x9158, 0xBA6E, 0x9159, 0xBA6F, 0x915A,	0xBA70, 0xB8E7, 0xBA71, 0xB8E8, 0xBA72, 0x9161, 0xBA73, 0x9162,
+	0xBA74, 0xB8E9, 0xBA75, 0x9163, 0xBA76, 0x9164, 0xBA77, 0x9165,	0xBA78, 0xB8EA, 0xBA79, 0x9166, 0xBA7A, 0x9167, 0xBA7B, 0x9168,
+	0xBA7C, 0x9169, 0xBA7D, 0x916A, 0xBA7E, 0x916B, 0xBA7F, 0x916C,	0xBA80, 0x916D, 0xBA81, 0x916E, 0xBA82, 0x916F, 0xBA83, 0xB8EB,
+	0xBA84, 0xB8EC, 0xBA85, 0xB8ED, 0xBA86, 0x9170, 0xBA87, 0xB8EE,	0xBA88, 0x9171, 0xBA89, 0x9172, 0xBA8A, 0x9173, 0xBA8B, 0x9174,
+	0xBA8C, 0xB8EF, 0xBA8D, 0x9175, 0xBA8E, 0x9176, 0xBA8F, 0x9177,	0xBA90, 0x9178, 0xBA91, 0x9179, 0xBA92, 0x917A, 0xBA93, 0x9181,
+	0xBA94, 0x9182, 0xBA95, 0x9183, 0xBA96, 0x9184, 0xBA97, 0x9185,	0xBA98, 0x9186, 0xBA99, 0x9187, 0xBA9A, 0x9188, 0xBA9B, 0x9189,
+	0xBA9C, 0x918A, 0xBA9D, 0x918B, 0xBA9E, 0x918C, 0xBA9F, 0x918D,	0xBAA0, 0x918E, 0xBAA1, 0x918F, 0xBAA2, 0x9190, 0xBAA3, 0x9191,
+	0xBAA4, 0x9192, 0xBAA5, 0x9193, 0xBAA6, 0x9194, 0xBAA7, 0x9195,	0xBAA8, 0xB8F0, 0xBAA9, 0xB8F1, 0xBAAA, 0x9196, 0xBAAB, 0xB8F2,
+	0xBAAC, 0xB8F3, 0xBAAD, 0x9197, 0xBAAE, 0x9198, 0xBAAF, 0x9199,	0xBAB0, 0xB8F4, 0xBAB1, 0x919A, 0xBAB2, 0xB8F5, 0xBAB3, 0x919B,
+	0xBAB4, 0x919C, 0xBAB5, 0x919D, 0xBAB6, 0x919E, 0xBAB7, 0x919F,	0xBAB8, 0xB8F6, 0xBAB9, 0xB8F7, 0xBABA, 0x91A0, 0xBABB, 0xB8F8,
+	0xBABC, 0x91A1, 0xBABD, 0xB8F9, 0xBABE, 0x91A2, 0xBABF, 0x91A3,	0xBAC0, 0x91A4, 0xBAC1, 0x91A5, 0xBAC2, 0x91A6, 0xBAC3, 0x91A7,
+	0xBAC4, 0xB8FA, 0xBAC5, 0x91A8, 0xBAC6, 0x91A9, 0xBAC7, 0x91AA,	0xBAC8, 0xB8FB, 0xBAC9, 0x91AB, 0xBACA, 0x91AC, 0xBACB, 0x91AD,
+	0xBACC, 0x91AE, 0xBACD, 0x91AF, 0xBACE, 0x91B0, 0xBACF, 0x91B1,	0xBAD0, 0x91B2, 0xBAD1, 0x91B3, 0xBAD2, 0x91B4, 0xBAD3, 0x91B5,
+	0xBAD4, 0x91B6, 0xBAD5, 0x91B7, 0xBAD6, 0x91B8, 0xBAD7, 0x91B9,	0xBAD8, 0xB8FC, 0xBAD9, 0xB8FD, 0xBADA, 0x91BA, 0xBADB, 0x91BB,
+	0xBADC, 0x91BC, 0xBADD, 0x91BD, 0xBADE, 0x91BE, 0xBADF, 0x91BF,	0xBAE0, 0x91C0, 0xBAE1, 0x91C1, 0xBAE2, 0x91C2, 0xBAE3, 0x91C3,
+	0xBAE4, 0x91C4, 0xBAE5, 0x91C5, 0xBAE6, 0x91C6, 0xBAE7, 0x91C7,	0xBAE8, 0x91C8, 0xBAE9, 0x91C9, 0xBAEA, 0x91CA, 0xBAEB, 0x91CB,
+	0xBAEC, 0x91CC, 0xBAED, 0x91CD, 0xBAEE, 0x91CE, 0xBAEF, 0x91CF,	0xBAF0, 0x91D0, 0xBAF1, 0x91D1, 0xBAF2, 0x91D2, 0xBAF3, 0x91D3,
+	0xBAF4, 0x91D4, 0xBAF5, 0x91D5, 0xBAF6, 0x91D6, 0xBAF7, 0x91D7,	0xBAF8, 0x91D8, 0xBAF9, 0x91D9, 0xBAFA, 0x91DA, 0xBAFB, 0x91DB,
+	0xBAFC, 0xB8FE, 0xBAFD, 0x91DC, 0xBAFE, 0x91DD, 0xBAFF, 0x91DE,	0xBB00, 0xB9A1, 0xBB01, 0x91DF, 0xBB02, 0x91E0, 0xBB03, 0x91E1,
+	0xBB04, 0xB9A2, 0xBB05, 0x91E2, 0xBB06, 0x91E3, 0xBB07, 0x91E4,	0xBB08, 0x91E5, 0xBB09, 0x91E6, 0xBB0A, 0x91E7, 0xBB0B, 0x91E8,
+	0xBB0C, 0x91E9, 0xBB0D, 0xB9A3, 0xBB0E, 0x91EA, 0xBB0F, 0xB9A4,	0xBB10, 0x91EB, 0xBB11, 0xB9A5, 0xBB12, 0x91EC, 0xBB13, 0x91ED,
+	0xBB14, 0x91EE, 0xBB15, 0x91EF, 0xBB16, 0x91F0, 0xBB17, 0x91F1,	0xBB18, 0xB9A6, 0xBB19, 0x91F2, 0xBB1A, 0x91F3, 0xBB1B, 0x91F4,
+	0xBB1C, 0xB9A7, 0xBB1D, 0x91F5, 0xBB1E, 0x91F6, 0xBB1F, 0x91F7,	0xBB20, 0xB9A8, 0xBB21, 0x91F8, 0xBB22, 0x91F9, 0xBB23, 0x91FA,
+	0xBB24, 0x91FB, 0xBB25, 0x91FC, 0xBB26, 0x91FD, 0xBB27, 0x91FE,	0xBB28, 0x9241, 0xBB29, 0xB9A9, 0xBB2A, 0x9242, 0xBB2B, 0xB9AA,
+	0xBB2C, 0x9243, 0xBB2D, 0x9244, 0xBB2E, 0x9245, 0xBB2F, 0x9246,	0xBB30, 0x9247, 0xBB31, 0x9248, 0xBB32, 0x9249, 0xBB33, 0x924A,
+	0xBB34, 0xB9AB, 0xBB35, 0xB9AC, 0xBB36, 0xB9AD, 0xBB37, 0x924B,	0xBB38, 0xB9AE, 0xBB39, 0x924C, 0xBB3A, 0x924D, 0xBB3B, 0xB9AF,
+	0xBB3C, 0xB9B0, 0xBB3D, 0xB9B1, 0xBB3E, 0xB9B2, 0xBB3F, 0x924E,	0xBB40, 0x924F, 0xBB41, 0x9250, 0xBB42, 0x9251, 0xBB43, 0x9252,
+	0xBB44, 0xB9B3, 0xBB45, 0xB9B4, 0xBB46, 0x9253, 0xBB47, 0xB9B5,	0xBB48, 0x9254, 0xBB49, 0xB9B6, 0xBB4A, 0x9255, 0xBB4B, 0x9256,
+	0xBB4C, 0x9257, 0xBB4D, 0xB9B7, 0xBB4E, 0x9258, 0xBB4F, 0xB9B8,	0xBB50, 0xB9B9, 0xBB51, 0x9259, 0xBB52, 0x925A, 0xBB53, 0x9261,
+	0xBB54, 0xB9BA, 0xBB55, 0x9262, 0xBB56, 0x9263, 0xBB57, 0x9264,	0xBB58, 0xB9BB, 0xBB59, 0x9265, 0xBB5A, 0x9266, 0xBB5B, 0x9267,
+	0xBB5C, 0x9268, 0xBB5D, 0x9269, 0xBB5E, 0x926A, 0xBB5F, 0x926B,	0xBB60, 0x926C, 0xBB61, 0xB9BC, 0xBB62, 0x926D, 0xBB63, 0xB9BD,
+	0xBB64, 0x926E, 0xBB65, 0x926F, 0xBB66, 0x9270, 0xBB67, 0x9271,	0xBB68, 0x9272, 0xBB69, 0x9273, 0xBB6A, 0x9274, 0xBB6B, 0x9275,
+	0xBB6C, 0xB9BE, 0xBB6D, 0x9276, 0xBB6E, 0x9277, 0xBB6F, 0x9278,	0xBB70, 0x9279, 0xBB71, 0x927A, 0xBB72, 0x9281, 0xBB73, 0x9282,
+	0xBB74, 0x9283, 0xBB75, 0x9284, 0xBB76, 0x9285, 0xBB77, 0x9286,	0xBB78, 0x9287, 0xBB79, 0x9288, 0xBB7A, 0x9289, 0xBB7B, 0x928A,
+	0xBB7C, 0x928B, 0xBB7D, 0x928C, 0xBB7E, 0x928D, 0xBB7F, 0x928E,	0xBB80, 0x928F, 0xBB81, 0x9290, 0xBB82, 0x9291, 0xBB83, 0x9292,
+	0xBB84, 0x9293, 0xBB85, 0x9294, 0xBB86, 0x9295, 0xBB87, 0x9296,	0xBB88, 0xB9BF, 0xBB89, 0x9297, 0xBB8A, 0x9298, 0xBB8B, 0x9299,
+	0xBB8C, 0xB9C0, 0xBB8D, 0x929A, 0xBB8E, 0x929B, 0xBB8F, 0x929C,	0xBB90, 0xB9C1, 0xBB91, 0x929D, 0xBB92, 0x929E, 0xBB93, 0x929F,
+	0xBB94, 0x92A0, 0xBB95, 0x92A1, 0xBB96, 0x92A2, 0xBB97, 0x92A3,	0xBB98, 0x92A4, 0xBB99, 0x92A5, 0xBB9A, 0x92A6, 0xBB9B, 0x92A7,
+	0xBB9C, 0x92A8, 0xBB9D, 0x92A9, 0xBB9E, 0x92AA, 0xBB9F, 0x92AB,	0xBBA0, 0x92AC, 0xBBA1, 0x92AD, 0xBBA2, 0x92AE, 0xBBA3, 0x92AF,
+	0xBBA4, 0xB9C2, 0xBBA5, 0x92B0, 0xBBA6, 0x92B1, 0xBBA7, 0x92B2,	0xBBA8, 0xB9C3, 0xBBA9, 0x92B3, 0xBBAA, 0x92B4, 0xBBAB, 0x92B5,
+	0xBBAC, 0xB9C4, 0xBBAD, 0x92B6, 0xBBAE, 0x92B7, 0xBBAF, 0x92B8,	0xBBB0, 0x92B9, 0xBBB1, 0x92BA, 0xBBB2, 0x92BB, 0xBBB3, 0x92BC,
+	0xBBB4, 0xB9C5, 0xBBB5, 0x92BD, 0xBBB6, 0x92BE, 0xBBB7, 0xB9C6,	0xBBB8, 0x92BF, 0xBBB9, 0x92C0, 0xBBBA, 0x92C1, 0xBBBB, 0x92C2,
+	0xBBBC, 0x92C3, 0xBBBD, 0x92C4, 0xBBBE, 0x92C5, 0xBBBF, 0x92C6,	0xBBC0, 0xB9C7, 0xBBC1, 0x92C7, 0xBBC2, 0x92C8, 0xBBC3, 0x92C9,
+	0xBBC4, 0xB9C8, 0xBBC5, 0x92CA, 0xBBC6, 0x92CB, 0xBBC7, 0x92CC,	0xBBC8, 0xB9C9, 0xBBC9, 0x92CD, 0xBBCA, 0x92CE, 0xBBCB, 0x92CF,
+	0xBBCC, 0x92D0, 0xBBCD, 0x92D1, 0xBBCE, 0x92D2, 0xBBCF, 0x92D3,	0xBBD0, 0xB9CA, 0xBBD1, 0x92D4, 0xBBD2, 0x92D5, 0xBBD3, 0xB9CB,
+	0xBBD4, 0x92D6, 0xBBD5, 0x92D7, 0xBBD6, 0x92D8, 0xBBD7, 0x92D9,	0xBBD8, 0x92DA, 0xBBD9, 0x92DB, 0xBBDA, 0x92DC, 0xBBDB, 0x92DD,
+	0xBBDC, 0x92DE, 0xBBDD, 0x92DF, 0xBBDE, 0x92E0, 0xBBDF, 0x92E1,	0xBBE0, 0x92E2, 0xBBE1, 0x92E3, 0xBBE2, 0x92E4, 0xBBE3, 0x92E5,
+	0xBBE4, 0x92E6, 0xBBE5, 0x92E7, 0xBBE6, 0x92E8, 0xBBE7, 0x92E9,	0xBBE8, 0x92EA, 0xBBE9, 0x92EB, 0xBBEA, 0x92EC, 0xBBEB, 0x92ED,
+	0xBBEC, 0x92EE, 0xBBED, 0x92EF, 0xBBEE, 0x92F0, 0xBBEF, 0x92F1,	0xBBF0, 0x92F2, 0xBBF1, 0x92F3, 0xBBF2, 0x92F4, 0xBBF3, 0x92F5,
+	0xBBF4, 0x92F6, 0xBBF5, 0x92F7, 0xBBF6, 0x92F8, 0xBBF7, 0x92F9,	0xBBF8, 0xB9CC, 0xBBF9, 0xB9CD, 0xBBFA, 0x92FA, 0xBBFB, 0x92FB,
+	0xBBFC, 0xB9CE, 0xBBFD, 0x92FC, 0xBBFE, 0x92FD, 0xBBFF, 0xB9CF,	0xBC00, 0xB9D0, 0xBC01, 0x92FE, 0xBC02, 0xB9D1, 0xBC03, 0x9341,
+	0xBC04, 0x9342, 0xBC05, 0x9343, 0xBC06, 0x9344, 0xBC07, 0x9345,	0xBC08, 0xB9D2, 0xBC09, 0xB9D3, 0xBC0A, 0x9346, 0xBC0B, 0xB9D4,
+	0xBC0C, 0xB9D5, 0xBC0D, 0xB9D6, 0xBC0E, 0x9347, 0xBC0F, 0xB9D7,	0xBC10, 0x9348, 0xBC11, 0xB9D8, 0xBC12, 0x9349, 0xBC13, 0x934A,
+	0xBC14, 0xB9D9, 0xBC15, 0xB9DA, 0xBC16, 0xB9DB, 0xBC17, 0xB9DC,	0xBC18, 0xB9DD, 0xBC19, 0x934B, 0xBC1A, 0x934C, 0xBC1B, 0xB9DE,
+	0xBC1C, 0xB9DF, 0xBC1D, 0xB9E0, 0xBC1E, 0xB9E1, 0xBC1F, 0xB9E2,	0xBC20, 0x934D, 0xBC21, 0x934E, 0xBC22, 0x934F, 0xBC23, 0x9350,
+	0xBC24, 0xB9E3, 0xBC25, 0xB9E4, 0xBC26, 0x9351, 0xBC27, 0xB9E5,	0xBC28, 0x9352, 0xBC29, 0xB9E6, 0xBC2A, 0x9353, 0xBC2B, 0x9354,
+	0xBC2C, 0x9355, 0xBC2D, 0xB9E7, 0xBC2E, 0x9356, 0xBC2F, 0x9357,	0xBC30, 0xB9E8, 0xBC31, 0xB9E9, 0xBC32, 0x9358, 0xBC33, 0x9359,
+	0xBC34, 0xB9EA, 0xBC35, 0x935A, 0xBC36, 0x9361, 0xBC37, 0x9362,	0xBC38, 0xB9EB, 0xBC39, 0x9363, 0xBC3A, 0x9364, 0xBC3B, 0x9365,
+	0xBC3C, 0x9366, 0xBC3D, 0x9367, 0xBC3E, 0x9368, 0xBC3F, 0x9369,	0xBC40, 0xB9EC, 0xBC41, 0xB9ED, 0xBC42, 0x936A, 0xBC43, 0xB9EE,
+	0xBC44, 0xB9EF, 0xBC45, 0xB9F0, 0xBC46, 0x936B, 0xBC47, 0x936C,	0xBC48, 0x936D, 0xBC49, 0xB9F1, 0xBC4A, 0x936E, 0xBC4B, 0x936F,
+	0xBC4C, 0xB9F2, 0xBC4D, 0xB9F3, 0xBC4E, 0x9370, 0xBC4F, 0x9371,	0xBC50, 0xB9F4, 0xBC51, 0x9372, 0xBC52, 0x9373, 0xBC53, 0x9374,
+	0xBC54, 0x9375, 0xBC55, 0x9376, 0xBC56, 0x9377, 0xBC57, 0x9378,	0xBC58, 0x9379, 0xBC59, 0x937A, 0xBC5A, 0x9381, 0xBC5B, 0x9382,
+	0xBC5C, 0x9383, 0xBC5D, 0xB9F5, 0xBC5E, 0x9384, 0xBC5F, 0x9385,	0xBC60, 0x9386, 0xBC61, 0x9387, 0xBC62, 0x9388, 0xBC63, 0x9389,
+	0xBC64, 0x938A, 0xBC65, 0x938B, 0xBC66, 0x938C, 0xBC67, 0x938D,	0xBC68, 0x938E, 0xBC69, 0x938F, 0xBC6A, 0x9390, 0xBC6B, 0x9391,
+	0xBC6C, 0x9392, 0xBC6D, 0x9393, 0xBC6E, 0x9394, 0xBC6F, 0x9395,	0xBC70, 0x9396, 0xBC71, 0x9397, 0xBC72, 0x9398, 0xBC73, 0x9399,
+	0xBC74, 0x939A, 0xBC75, 0x939B, 0xBC76, 0x939C, 0xBC77, 0x939D,	0xBC78, 0x939E, 0xBC79, 0x939F, 0xBC7A, 0x93A0, 0xBC7B, 0x93A1,
+	0xBC7C, 0x93A2, 0xBC7D, 0x93A3, 0xBC7E, 0x93A4, 0xBC7F, 0x93A5,	0xBC80, 0x93A6, 0xBC81, 0x93A7, 0xBC82, 0x93A8, 0xBC83, 0x93A9,
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+	0xBF2C, 0x96AF, 0xBF2D, 0x96B0, 0xBF2E, 0x96B1, 0xBF2F, 0x96B2,	0xBF30, 0x96B3, 0xBF31, 0x96B4, 0xBF32, 0x96B5, 0xBF33, 0x96B6,
+	0xBF34, 0x96B7, 0xBF35, 0x96B8, 0xBF36, 0x96B9, 0xBF37, 0x96BA,	0xBF38, 0x96BB, 0xBF39, 0x96BC, 0xBF3A, 0x96BD, 0xBF3B, 0x96BE,
+	0xBF3C, 0x96BF, 0xBF3D, 0x96C0, 0xBF3E, 0x96C1, 0xBF3F, 0x96C2,	0xBF40, 0xBBC7, 0xBF41, 0xBBC8, 0xBF42, 0x96C3, 0xBF43, 0x96C4,
+	0xBF44, 0xBBC9, 0xBF45, 0x96C5, 0xBF46, 0x96C6, 0xBF47, 0x96C7,	0xBF48, 0xBBCA, 0xBF49, 0x96C8, 0xBF4A, 0x96C9, 0xBF4B, 0x96CA,
+	0xBF4C, 0x96CB, 0xBF4D, 0x96CC, 0xBF4E, 0x96CD, 0xBF4F, 0x96CE,	0xBF50, 0xBBCB, 0xBF51, 0xBBCC, 0xBF52, 0x96CF, 0xBF53, 0x96D0,
+	0xBF54, 0x96D1, 0xBF55, 0xBBCD, 0xBF56, 0x96D2, 0xBF57, 0x96D3,	0xBF58, 0x96D4, 0xBF59, 0x96D5, 0xBF5A, 0x96D6, 0xBF5B, 0x96D7,
+	0xBF5C, 0x96D8, 0xBF5D, 0x96D9, 0xBF5E, 0x96DA, 0xBF5F, 0x96DB,	0xBF60, 0x96DC, 0xBF61, 0x96DD, 0xBF62, 0x96DE, 0xBF63, 0x96DF,
+	0xBF64, 0x96E0, 0xBF65, 0x96E1, 0xBF66, 0x96E2, 0xBF67, 0x96E3,	0xBF68, 0x96E4, 0xBF69, 0x96E5, 0xBF6A, 0x96E6, 0xBF6B, 0x96E7,
+	0xBF6C, 0x96E8, 0xBF6D, 0x96E9, 0xBF6E, 0x96EA, 0xBF6F, 0x96EB,	0xBF70, 0x96EC, 0xBF71, 0x96ED, 0xBF72, 0x96EE, 0xBF73, 0x96EF,
+	0xBF74, 0x96F0, 0xBF75, 0x96F1, 0xBF76, 0x96F2, 0xBF77, 0x96F3,	0xBF78, 0x96F4, 0xBF79, 0x96F5, 0xBF7A, 0x96F6, 0xBF7B, 0x96F7,
+	0xBF7C, 0x96F8, 0xBF7D, 0x96F9, 0xBF7E, 0x96FA, 0xBF7F, 0x96FB,	0xBF80, 0x96FC, 0xBF81, 0x96FD, 0xBF82, 0x96FE, 0xBF83, 0x9741,
+	0xBF84, 0x9742, 0xBF85, 0x9743, 0xBF86, 0x9744, 0xBF87, 0x9745,	0xBF88, 0x9746, 0xBF89, 0x9747, 0xBF8A, 0x9748, 0xBF8B, 0x9749,
+	0xBF8C, 0x974A, 0xBF8D, 0x974B, 0xBF8E, 0x974C, 0xBF8F, 0x974D,	0xBF90, 0x974E, 0xBF91, 0x974F, 0xBF92, 0x9750, 0xBF93, 0x9751,
+	0xBF94, 0xBBCE, 0xBF95, 0x9752, 0xBF96, 0x9753, 0xBF97, 0x9754,	0xBF98, 0x9755, 0xBF99, 0x9756, 0xBF9A, 0x9757, 0xBF9B, 0x9758,
+	0xBF9C, 0x9759, 0xBF9D, 0x975A, 0xBF9E, 0x9761, 0xBF9F, 0x9762,	0xBFA0, 0x9763, 0xBFA1, 0x9764, 0xBFA2, 0x9765, 0xBFA3, 0x9766,
+	0xBFA4, 0x9767, 0xBFA5, 0x9768, 0xBFA6, 0x9769, 0xBFA7, 0x976A,	0xBFA8, 0x976B, 0xBFA9, 0x976C, 0xBFAA, 0x976D, 0xBFAB, 0x976E,
+	0xBFAC, 0x976F, 0xBFAD, 0x9770, 0xBFAE, 0x9771, 0xBFAF, 0x9772,	0xBFB0, 0xBBCF, 0xBFB1, 0x9773, 0xBFB2, 0x9774, 0xBFB3, 0x9775,
+	0xBFB4, 0x9776, 0xBFB5, 0x9777, 0xBFB6, 0x9778, 0xBFB7, 0x9779,	0xBFB8, 0x977A, 0xBFB9, 0x9781, 0xBFBA, 0x9782, 0xBFBB, 0x9783,
+	0xBFBC, 0x9784, 0xBFBD, 0x9785, 0xBFBE, 0x9786, 0xBFBF, 0x9787,	0xBFC0, 0x9788, 0xBFC1, 0x9789, 0xBFC2, 0x978A, 0xBFC3, 0x978B,
+	0xBFC4, 0x978C, 0xBFC5, 0xBBD0, 0xBFC6, 0x978D, 0xBFC7, 0x978E,	0xBFC8, 0x978F, 0xBFC9, 0x9790, 0xBFCA, 0x9791, 0xBFCB, 0x9792,
+	0xBFCC, 0xBBD1, 0xBFCD, 0xBBD2, 0xBFCE, 0x9793, 0xBFCF, 0x9794,	0xBFD0, 0xBBD3, 0xBFD1, 0x9795, 0xBFD2, 0x9796, 0xBFD3, 0x9797,
+	0xBFD4, 0xBBD4, 0xBFD5, 0x9798, 0xBFD6, 0x9799, 0xBFD7, 0x979A,	0xBFD8, 0x979B, 0xBFD9, 0x979C, 0xBFDA, 0x979D, 0xBFDB, 0x979E,
+	0xBFDC, 0xBBD5, 0xBFDD, 0x979F, 0xBFDE, 0x97A0, 0xBFDF, 0xBBD6,	0xBFE0, 0x97A1, 0xBFE1, 0xBBD7, 0xBFE2, 0x97A2, 0xBFE3, 0x97A3,
+	0xBFE4, 0x97A4, 0xBFE5, 0x97A5, 0xBFE6, 0x97A6, 0xBFE7, 0x97A7,	0xBFE8, 0x97A8, 0xBFE9, 0x97A9, 0xBFEA, 0x97AA, 0xBFEB, 0x97AB,
+	0xBFEC, 0x97AC, 0xBFED, 0x97AD, 0xBFEE, 0x97AE, 0xBFEF, 0x97AF,	0xBFF0, 0x97B0, 0xBFF1, 0x97B1, 0xBFF2, 0x97B2, 0xBFF3, 0x97B3,
+	0xBFF4, 0x97B4, 0xBFF5, 0x97B5, 0xBFF6, 0x97B6, 0xBFF7, 0x97B7,	0xBFF8, 0x97B8, 0xBFF9, 0x97B9, 0xBFFA, 0x97BA, 0xBFFB, 0x97BB,
+	0xBFFC, 0x97BC, 0xBFFD, 0x97BD, 0xBFFE, 0x97BE, 0xBFFF, 0x97BF,	0xC000, 0x97C0, 0xC001, 0x97C1, 0xC002, 0x97C2, 0xC003, 0x97C3,
+	0xC004, 0x97C4, 0xC005, 0x97C5, 0xC006, 0x97C6, 0xC007, 0x97C7,	0xC008, 0x97C8, 0xC009, 0x97C9, 0xC00A, 0x97CA, 0xC00B, 0x97CB,
+	0xC00C, 0x97CC, 0xC00D, 0x97CD, 0xC00E, 0x97CE, 0xC00F, 0x97CF,	0xC010, 0x97D0, 0xC011, 0x97D1, 0xC012, 0x97D2, 0xC013, 0x97D3,
+	0xC014, 0x97D4, 0xC015, 0x97D5, 0xC016, 0x97D6, 0xC017, 0x97D7,	0xC018, 0x97D8, 0xC019, 0x97D9, 0xC01A, 0x97DA, 0xC01B, 0x97DB,
+	0xC01C, 0x97DC, 0xC01D, 0x97DD, 0xC01E, 0x97DE, 0xC01F, 0x97DF,	0xC020, 0x97E0, 0xC021, 0x97E1, 0xC022, 0x97E2, 0xC023, 0x97E3,
+	0xC024, 0x97E4, 0xC025, 0x97E5, 0xC026, 0x97E6, 0xC027, 0x97E7,	0xC028, 0x97E8, 0xC029, 0x97E9, 0xC02A, 0x97EA, 0xC02B, 0x97EB,
+	0xC02C, 0x97EC, 0xC02D, 0x97ED, 0xC02E, 0x97EE, 0xC02F, 0x97EF,	0xC030, 0x97F0, 0xC031, 0x97F1, 0xC032, 0x97F2, 0xC033, 0x97F3,
+	0xC034, 0x97F4, 0xC035, 0x97F5, 0xC036, 0x97F6, 0xC037, 0x97F7,	0xC038, 0x97F8, 0xC039, 0x97F9, 0xC03A, 0x97FA, 0xC03B, 0x97FB,
+	0xC03C, 0xBBD8, 0xC03D, 0x97FC, 0xC03E, 0x97FD, 0xC03F, 0x97FE,	0xC040, 0x9841, 0xC041, 0x9842, 0xC042, 0x9843, 0xC043, 0x9844,
+	0xC044, 0x9845, 0xC045, 0x9846, 0xC046, 0x9847, 0xC047, 0x9848,	0xC048, 0x9849, 0xC049, 0x984A, 0xC04A, 0x984B, 0xC04B, 0x984C,
+	0xC04C, 0x984D, 0xC04D, 0x984E, 0xC04E, 0x984F, 0xC04F, 0x9850,	0xC050, 0x9851, 0xC051, 0xBBD9, 0xC052, 0x9852, 0xC053, 0x9853,
+	0xC054, 0x9854, 0xC055, 0x9855, 0xC056, 0x9856, 0xC057, 0x9857,	0xC058, 0xBBDA, 0xC059, 0x9858, 0xC05A, 0x9859, 0xC05B, 0x985A,
+	0xC05C, 0xBBDB, 0xC05D, 0x9861, 0xC05E, 0x9862, 0xC05F, 0x9863,	0xC060, 0xBBDC, 0xC061, 0x9864, 0xC062, 0x9865, 0xC063, 0x9866,
+	0xC064, 0x9867, 0xC065, 0x9868, 0xC066, 0x9869, 0xC067, 0x986A,	0xC068, 0xBBDD, 0xC069, 0xBBDE, 0xC06A, 0x986B, 0xC06B, 0x986C,
+	0xC06C, 0x986D, 0xC06D, 0x986E, 0xC06E, 0x986F, 0xC06F, 0x9870,	0xC070, 0x9871, 0xC071, 0x9872, 0xC072, 0x9873, 0xC073, 0x9874,
+	0xC074, 0x9875, 0xC075, 0x9876, 0xC076, 0x9877, 0xC077, 0x9878,	0xC078, 0x9879, 0xC079, 0x987A, 0xC07A, 0x9881, 0xC07B, 0x9882,
+	0xC07C, 0x9883, 0xC07D, 0x9884, 0xC07E, 0x9885, 0xC07F, 0x9886,	0xC080, 0x9887, 0xC081, 0x9888, 0xC082, 0x9889, 0xC083, 0x988A,
+	0xC084, 0x988B, 0xC085, 0x988C, 0xC086, 0x988D, 0xC087, 0x988E,	0xC088, 0x988F, 0xC089, 0x9890, 0xC08A, 0x9891, 0xC08B, 0x9892,
+	0xC08C, 0x9893, 0xC08D, 0x9894, 0xC08E, 0x9895, 0xC08F, 0x9896,	0xC090, 0xBBDF, 0xC091, 0xBBE0, 0xC092, 0x9897, 0xC093, 0x9898,
+	0xC094, 0xBBE1, 0xC095, 0x9899, 0xC096, 0x989A, 0xC097, 0x989B,	0xC098, 0xBBE2, 0xC099, 0x989C, 0xC09A, 0x989D, 0xC09B, 0x989E,
+	0xC09C, 0x989F, 0xC09D, 0x98A0, 0xC09E, 0x98A1, 0xC09F, 0x98A2,	0xC0A0, 0xBBE3, 0xC0A1, 0xBBE4, 0xC0A2, 0x98A3, 0xC0A3, 0xBBE5,
+	0xC0A4, 0x98A4, 0xC0A5, 0xBBE6, 0xC0A6, 0x98A5, 0xC0A7, 0x98A6,	0xC0A8, 0x98A7, 0xC0A9, 0x98A8, 0xC0AA, 0x98A9, 0xC0AB, 0x98AA,
+	0xC0AC, 0xBBE7, 0xC0AD, 0xBBE8, 0xC0AE, 0x98AB, 0xC0AF, 0xBBE9,	0xC0B0, 0xBBEA, 0xC0B1, 0x98AC, 0xC0B2, 0x98AD, 0xC0B3, 0xBBEB,
+	0xC0B4, 0xBBEC, 0xC0B5, 0xBBED, 0xC0B6, 0xBBEE, 0xC0B7, 0x98AE,	0xC0B8, 0x98AF, 0xC0B9, 0x98B0, 0xC0BA, 0x98B1, 0xC0BB, 0x98B2,
+	0xC0BC, 0xBBEF, 0xC0BD, 0xBBF0, 0xC0BE, 0x98B3, 0xC0BF, 0xBBF1,	0xC0C0, 0xBBF2, 0xC0C1, 0xBBF3, 0xC0C2, 0x98B4, 0xC0C3, 0x98B5,
+	0xC0C4, 0x98B6, 0xC0C5, 0xBBF4, 0xC0C6, 0x98B7, 0xC0C7, 0x98B8,	0xC0C8, 0xBBF5, 0xC0C9, 0xBBF6, 0xC0CA, 0x98B9, 0xC0CB, 0x98BA,
+	0xC0CC, 0xBBF7, 0xC0CD, 0x98BB, 0xC0CE, 0x98BC, 0xC0CF, 0x98BD,	0xC0D0, 0xBBF8, 0xC0D1, 0x98BE, 0xC0D2, 0x98BF, 0xC0D3, 0x98C0,
+	0xC0D4, 0x98C1, 0xC0D5, 0x98C2, 0xC0D6, 0x98C3, 0xC0D7, 0x98C4,	0xC0D8, 0xBBF9, 0xC0D9, 0xBBFA, 0xC0DA, 0x98C5, 0xC0DB, 0xBBFB,
+	0xC0DC, 0xBBFC, 0xC0DD, 0xBBFD, 0xC0DE, 0x98C6, 0xC0DF, 0x98C7,	0xC0E0, 0x98C8, 0xC0E1, 0x98C9, 0xC0E2, 0x98CA, 0xC0E3, 0x98CB,
+	0xC0E4, 0xBBFE, 0xC0E5, 0xBCA1, 0xC0E6, 0x98CC, 0xC0E7, 0x98CD,	0xC0E8, 0xBCA2, 0xC0E9, 0x98CE, 0xC0EA, 0x98CF, 0xC0EB, 0x98D0,
+	0xC0EC, 0xBCA3, 0xC0ED, 0x98D1, 0xC0EE, 0x98D2, 0xC0EF, 0x98D3,	0xC0F0, 0x98D4, 0xC0F1, 0x98D5, 0xC0F2, 0x98D6, 0xC0F3, 0x98D7,
+	0xC0F4, 0xBCA4, 0xC0F5, 0xBCA5, 0xC0F6, 0x98D8, 0xC0F7, 0xBCA6,	0xC0F8, 0x98D9, 0xC0F9, 0xBCA7, 0xC0FA, 0x98DA, 0xC0FB, 0x98DB,
+	0xC0FC, 0x98DC, 0xC0FD, 0x98DD, 0xC0FE, 0x98DE, 0xC0FF, 0x98DF,	0xC100, 0xBCA8, 0xC101, 0x98E0, 0xC102, 0x98E1, 0xC103, 0x98E2,
+	0xC104, 0xBCA9, 0xC105, 0x98E3, 0xC106, 0x98E4, 0xC107, 0x98E5,	0xC108, 0xBCAA, 0xC109, 0x98E6, 0xC10A, 0x98E7, 0xC10B, 0x98E8,
+	0xC10C, 0x98E9, 0xC10D, 0x98EA, 0xC10E, 0x98EB, 0xC10F, 0x98EC,	0xC110, 0xBCAB, 0xC111, 0x98ED, 0xC112, 0x98EE, 0xC113, 0x98EF,
+	0xC114, 0x98F0, 0xC115, 0xBCAC, 0xC116, 0x98F1, 0xC117, 0x98F2,	0xC118, 0x98F3, 0xC119, 0x98F4, 0xC11A, 0x98F5, 0xC11B, 0x98F6,
+	0xC11C, 0xBCAD, 0xC11D, 0xBCAE, 0xC11E, 0xBCAF, 0xC11F, 0xBCB0,	0xC120, 0xBCB1, 0xC121, 0x98F7, 0xC122, 0x98F8, 0xC123, 0xBCB2,
+	0xC124, 0xBCB3, 0xC125, 0x98F9, 0xC126, 0xBCB4, 0xC127, 0xBCB5,	0xC128, 0x98FA, 0xC129, 0x98FB, 0xC12A, 0x98FC, 0xC12B, 0x98FD,
+	0xC12C, 0xBCB6, 0xC12D, 0xBCB7, 0xC12E, 0x98FE, 0xC12F, 0xBCB8,	0xC130, 0xBCB9, 0xC131, 0xBCBA, 0xC132, 0x9941, 0xC133, 0x9942,
+	0xC134, 0x9943, 0xC135, 0x9944, 0xC136, 0xBCBB, 0xC137, 0x9945,	0xC138, 0xBCBC, 0xC139, 0xBCBD, 0xC13A, 0x9946, 0xC13B, 0x9947,
+	0xC13C, 0xBCBE, 0xC13D, 0x9948, 0xC13E, 0x9949, 0xC13F, 0x994A,	0xC140, 0xBCBF, 0xC141, 0x994B, 0xC142, 0x994C, 0xC143, 0x994D,
+	0xC144, 0x994E, 0xC145, 0x994F, 0xC146, 0x9950, 0xC147, 0x9951,	0xC148, 0xBCC0, 0xC149, 0xBCC1, 0xC14A, 0x9952, 0xC14B, 0xBCC2,
+	0xC14C, 0xBCC3, 0xC14D, 0xBCC4, 0xC14E, 0x9953, 0xC14F, 0x9954,	0xC150, 0x9955, 0xC151, 0x9956, 0xC152, 0x9957, 0xC153, 0x9958,
+	0xC154, 0xBCC5, 0xC155, 0xBCC6, 0xC156, 0x9959, 0xC157, 0x995A,	0xC158, 0xBCC7, 0xC159, 0x9961, 0xC15A, 0x9962, 0xC15B, 0x9963,
+	0xC15C, 0xBCC8, 0xC15D, 0x9964, 0xC15E, 0x9965, 0xC15F, 0x9966,	0xC160, 0x9967, 0xC161, 0x9968, 0xC162, 0x9969, 0xC163, 0x996A,
+	0xC164, 0xBCC9, 0xC165, 0xBCCA, 0xC166, 0x996B, 0xC167, 0xBCCB,	0xC168, 0xBCCC, 0xC169, 0xBCCD, 0xC16A, 0x996C, 0xC16B, 0x996D,
+	0xC16C, 0x996E, 0xC16D, 0x996F, 0xC16E, 0x9970, 0xC16F, 0x9971,	0xC170, 0xBCCE, 0xC171, 0x9972, 0xC172, 0x9973, 0xC173, 0x9974,
+	0xC174, 0xBCCF, 0xC175, 0x9975, 0xC176, 0x9976, 0xC177, 0x9977,	0xC178, 0xBCD0, 0xC179, 0x9978, 0xC17A, 0x9979, 0xC17B, 0x997A,
+	0xC17C, 0x9981, 0xC17D, 0x9982, 0xC17E, 0x9983, 0xC17F, 0x9984,	0xC180, 0x9985, 0xC181, 0x9986, 0xC182, 0x9987, 0xC183, 0x9988,
+	0xC184, 0x9989, 0xC185, 0xBCD1, 0xC186, 0x998A, 0xC187, 0x998B,	0xC188, 0x998C, 0xC189, 0x998D, 0xC18A, 0x998E, 0xC18B, 0x998F,
+	0xC18C, 0xBCD2, 0xC18D, 0xBCD3, 0xC18E, 0xBCD4, 0xC18F, 0x9990,	0xC190, 0xBCD5, 0xC191, 0x9991, 0xC192, 0x9992, 0xC193, 0x9993,
+	0xC194, 0xBCD6, 0xC195, 0x9994, 0xC196, 0xBCD7, 0xC197, 0x9995,	0xC198, 0x9996, 0xC199, 0x9997, 0xC19A, 0x9998, 0xC19B, 0x9999,
+	0xC19C, 0xBCD8, 0xC19D, 0xBCD9, 0xC19E, 0x999A, 0xC19F, 0xBCDA,	0xC1A0, 0x999B, 0xC1A1, 0xBCDB, 0xC1A2, 0x999C, 0xC1A3, 0x999D,
+	0xC1A4, 0x999E, 0xC1A5, 0xBCDC, 0xC1A6, 0x999F, 0xC1A7, 0x99A0,	0xC1A8, 0xBCDD, 0xC1A9, 0xBCDE, 0xC1AA, 0x99A1, 0xC1AB, 0x99A2,
+	0xC1AC, 0xBCDF, 0xC1AD, 0x99A3, 0xC1AE, 0x99A4, 0xC1AF, 0x99A5,	0xC1B0, 0xBCE0, 0xC1B1, 0x99A6, 0xC1B2, 0x99A7, 0xC1B3, 0x99A8,
+	0xC1B4, 0x99A9, 0xC1B5, 0x99AA, 0xC1B6, 0x99AB, 0xC1B7, 0x99AC,	0xC1B8, 0x99AD, 0xC1B9, 0x99AE, 0xC1BA, 0x99AF, 0xC1BB, 0x99B0,
+	0xC1BC, 0x99B1, 0xC1BD, 0xBCE1, 0xC1BE, 0x99B2, 0xC1BF, 0x99B3,	0xC1C0, 0x99B4, 0xC1C1, 0x99B5, 0xC1C2, 0x99B6, 0xC1C3, 0x99B7,
+	0xC1C4, 0xBCE2, 0xC1C5, 0x99B8, 0xC1C6, 0x99B9, 0xC1C7, 0x99BA,	0xC1C8, 0xBCE3, 0xC1C9, 0x99BB, 0xC1CA, 0x99BC, 0xC1CB, 0x99BD,
+	0xC1CC, 0xBCE4, 0xC1CD, 0x99BE, 0xC1CE, 0x99BF, 0xC1CF, 0x99C0,	0xC1D0, 0x99C1, 0xC1D1, 0x99C2, 0xC1D2, 0x99C3, 0xC1D3, 0x99C4,
+	0xC1D4, 0xBCE5, 0xC1D5, 0x99C5, 0xC1D6, 0x99C6, 0xC1D7, 0xBCE6,	0xC1D8, 0xBCE7, 0xC1D9, 0x99C7, 0xC1DA, 0x99C8, 0xC1DB, 0x99C9,
+	0xC1DC, 0x99CA, 0xC1DD, 0x99CB, 0xC1DE, 0x99CC, 0xC1DF, 0x99CD,	0xC1E0, 0xBCE8, 0xC1E1, 0x99CE, 0xC1E2, 0x99CF, 0xC1E3, 0x99D0,
+	0xC1E4, 0xBCE9, 0xC1E5, 0x99D1, 0xC1E6, 0x99D2, 0xC1E7, 0x99D3,	0xC1E8, 0xBCEA, 0xC1E9, 0x99D4, 0xC1EA, 0x99D5, 0xC1EB, 0x99D6,
+	0xC1EC, 0x99D7, 0xC1ED, 0x99D8, 0xC1EE, 0x99D9, 0xC1EF, 0x99DA,	0xC1F0, 0xBCEB, 0xC1F1, 0xBCEC, 0xC1F2, 0x99DB, 0xC1F3, 0xBCED,
+	0xC1F4, 0x99DC, 0xC1F5, 0x99DD, 0xC1F6, 0x99DE, 0xC1F7, 0x99DF,	0xC1F8, 0x99E0, 0xC1F9, 0x99E1, 0xC1FA, 0x99E2, 0xC1FB, 0x99E3,
+	0xC1FC, 0xBCEE, 0xC1FD, 0xBCEF, 0xC1FE, 0x99E4, 0xC1FF, 0x99E5,	0xC200, 0xBCF0, 0xC201, 0x99E6, 0xC202, 0x99E7, 0xC203, 0x99E8,
+	0xC204, 0xBCF1, 0xC205, 0x99E9, 0xC206, 0x99EA, 0xC207, 0x99EB,	0xC208, 0x99EC, 0xC209, 0x99ED, 0xC20A, 0x99EE, 0xC20B, 0x99EF,
+	0xC20C, 0xBCF2, 0xC20D, 0xBCF3, 0xC20E, 0x99F0, 0xC20F, 0xBCF4,	0xC210, 0x99F1, 0xC211, 0xBCF5, 0xC212, 0x99F2, 0xC213, 0x99F3,
+	0xC214, 0x99F4, 0xC215, 0x99F5, 0xC216, 0x99F6, 0xC217, 0x99F7,	0xC218, 0xBCF6, 0xC219, 0xBCF7, 0xC21A, 0x99F8, 0xC21B, 0x99F9,
+	0xC21C, 0xBCF8, 0xC21D, 0x99FA, 0xC21E, 0x99FB, 0xC21F, 0xBCF9,	0xC220, 0xBCFA, 0xC221, 0x99FC, 0xC222, 0x99FD, 0xC223, 0x99FE,
+	0xC224, 0x9A41, 0xC225, 0x9A42, 0xC226, 0x9A43, 0xC227, 0x9A44,	0xC228, 0xBCFB, 0xC229, 0xBCFC, 0xC22A, 0x9A45, 0xC22B, 0xBCFD,
+	0xC22C, 0x9A46, 0xC22D, 0xBCFE, 0xC22E, 0x9A47, 0xC22F, 0xBDA1,	0xC230, 0x9A48, 0xC231, 0xBDA2, 0xC232, 0xBDA3, 0xC233, 0x9A49,
+	0xC234, 0xBDA4, 0xC235, 0x9A4A, 0xC236, 0x9A4B, 0xC237, 0x9A4C,	0xC238, 0x9A4D, 0xC239, 0x9A4E, 0xC23A, 0x9A4F, 0xC23B, 0x9A50,
+	0xC23C, 0x9A51, 0xC23D, 0x9A52, 0xC23E, 0x9A53, 0xC23F, 0x9A54,	0xC240, 0x9A55, 0xC241, 0x9A56, 0xC242, 0x9A57, 0xC243, 0x9A58,
+	0xC244, 0x9A59, 0xC245, 0x9A5A, 0xC246, 0x9A61, 0xC247, 0x9A62,	0xC248, 0xBDA5, 0xC249, 0x9A63, 0xC24A, 0x9A64, 0xC24B, 0x9A65,
+	0xC24C, 0x9A66, 0xC24D, 0x9A67, 0xC24E, 0x9A68, 0xC24F, 0x9A69,	0xC250, 0xBDA6, 0xC251, 0xBDA7, 0xC252, 0x9A6A, 0xC253, 0x9A6B,
+	0xC254, 0xBDA8, 0xC255, 0x9A6C, 0xC256, 0x9A6D, 0xC257, 0x9A6E,	0xC258, 0xBDA9, 0xC259, 0x9A6F, 0xC25A, 0x9A70, 0xC25B, 0x9A71,
+	0xC25C, 0x9A72, 0xC25D, 0x9A73, 0xC25E, 0x9A74, 0xC25F, 0x9A75,	0xC260, 0xBDAA, 0xC261, 0x9A76, 0xC262, 0x9A77, 0xC263, 0x9A78,
+	0xC264, 0x9A79, 0xC265, 0xBDAB, 0xC266, 0x9A7A, 0xC267, 0x9A81,	0xC268, 0x9A82, 0xC269, 0x9A83, 0xC26A, 0x9A84, 0xC26B, 0x9A85,
+	0xC26C, 0xBDAC, 0xC26D, 0xBDAD, 0xC26E, 0x9A86, 0xC26F, 0x9A87,	0xC270, 0xBDAE, 0xC271, 0x9A88, 0xC272, 0x9A89, 0xC273, 0x9A8A,
+	0xC274, 0xBDAF, 0xC275, 0x9A8B, 0xC276, 0x9A8C, 0xC277, 0x9A8D,	0xC278, 0x9A8E, 0xC279, 0x9A8F, 0xC27A, 0x9A90, 0xC27B, 0x9A91,
+	0xC27C, 0xBDB0, 0xC27D, 0xBDB1, 0xC27E, 0x9A92, 0xC27F, 0xBDB2,	0xC280, 0x9A93, 0xC281, 0xBDB3, 0xC282, 0x9A94, 0xC283, 0x9A95,
+	0xC284, 0x9A96, 0xC285, 0x9A97, 0xC286, 0x9A98, 0xC287, 0x9A99,	0xC288, 0xBDB4, 0xC289, 0xBDB5, 0xC28A, 0x9A9A, 0xC28B, 0x9A9B,
+	0xC28C, 0x9A9C, 0xC28D, 0x9A9D, 0xC28E, 0x9A9E, 0xC28F, 0x9A9F,	0xC290, 0xBDB6, 0xC291, 0x9AA0, 0xC292, 0x9AA1, 0xC293, 0x9AA2,
+	0xC294, 0x9AA3, 0xC295, 0x9AA4, 0xC296, 0x9AA5, 0xC297, 0x9AA6,	0xC298, 0xBDB7, 0xC299, 0x9AA7, 0xC29A, 0x9AA8, 0xC29B, 0xBDB8,
+	0xC29C, 0x9AA9, 0xC29D, 0xBDB9, 0xC29E, 0x9AAA, 0xC29F, 0x9AAB,	0xC2A0, 0x9AAC, 0xC2A1, 0x9AAD, 0xC2A2, 0x9AAE, 0xC2A3, 0x9AAF,
+	0xC2A4, 0xBDBA, 0xC2A5, 0xBDBB, 0xC2A6, 0x9AB0, 0xC2A7, 0x9AB1,	0xC2A8, 0xBDBC, 0xC2A9, 0x9AB2, 0xC2AA, 0x9AB3, 0xC2AB, 0x9AB4,
+	0xC2AC, 0xBDBD, 0xC2AD, 0xBDBE, 0xC2AE, 0x9AB5, 0xC2AF, 0x9AB6,	0xC2B0, 0x9AB7, 0xC2B1, 0x9AB8, 0xC2B2, 0x9AB9, 0xC2B3, 0x9ABA,
+	0xC2B4, 0xBDBF, 0xC2B5, 0xBDC0, 0xC2B6, 0x9ABB, 0xC2B7, 0xBDC1,	0xC2B8, 0x9ABC, 0xC2B9, 0xBDC2, 0xC2BA, 0x9ABD, 0xC2BB, 0x9ABE,
+	0xC2BC, 0x9ABF, 0xC2BD, 0x9AC0, 0xC2BE, 0x9AC1, 0xC2BF, 0x9AC2,	0xC2C0, 0x9AC3, 0xC2C1, 0x9AC4, 0xC2C2, 0x9AC5, 0xC2C3, 0x9AC6,
+	0xC2C4, 0x9AC7, 0xC2C5, 0x9AC8, 0xC2C6, 0x9AC9, 0xC2C7, 0x9ACA,	0xC2C8, 0x9ACB, 0xC2C9, 0x9ACC, 0xC2CA, 0x9ACD, 0xC2CB, 0x9ACE,
+	0xC2CC, 0x9ACF, 0xC2CD, 0x9AD0, 0xC2CE, 0x9AD1, 0xC2CF, 0x9AD2,	0xC2D0, 0x9AD3, 0xC2D1, 0x9AD4, 0xC2D2, 0x9AD5, 0xC2D3, 0x9AD6,
+	0xC2D4, 0x9AD7, 0xC2D5, 0x9AD8, 0xC2D6, 0x9AD9, 0xC2D7, 0x9ADA,	0xC2D8, 0x9ADB, 0xC2D9, 0x9ADC, 0xC2DA, 0x9ADD, 0xC2DB, 0x9ADE,
+	0xC2DC, 0xBDC3, 0xC2DD, 0xBDC4, 0xC2DE, 0x9ADF, 0xC2DF, 0x9AE0,	0xC2E0, 0xBDC5, 0xC2E1, 0x9AE1, 0xC2E2, 0x9AE2, 0xC2E3, 0xBDC6,
+	0xC2E4, 0xBDC7, 0xC2E5, 0x9AE3, 0xC2E6, 0x9AE4, 0xC2E7, 0x9AE5,	0xC2E8, 0x9AE6, 0xC2E9, 0x9AE7, 0xC2EA, 0x9AE8, 0xC2EB, 0xBDC8,
+	0xC2EC, 0xBDC9, 0xC2ED, 0xBDCA, 0xC2EE, 0x9AE9, 0xC2EF, 0xBDCB,	0xC2F0, 0x9AEA, 0xC2F1, 0xBDCC, 0xC2F2, 0x9AEB, 0xC2F3, 0x9AEC,
+	0xC2F4, 0x9AED, 0xC2F5, 0x9AEE, 0xC2F6, 0xBDCD, 0xC2F7, 0x9AEF,	0xC2F8, 0xBDCE, 0xC2F9, 0xBDCF, 0xC2FA, 0x9AF0, 0xC2FB, 0xBDD0,
+	0xC2FC, 0xBDD1, 0xC2FD, 0x9AF1, 0xC2FE, 0x9AF2, 0xC2FF, 0x9AF3,	0xC300, 0xBDD2, 0xC301, 0x9AF4, 0xC302, 0x9AF5, 0xC303, 0x9AF6,
+	0xC304, 0x9AF7, 0xC305, 0x9AF8, 0xC306, 0x9AF9, 0xC307, 0x9AFA,	0xC308, 0xBDD3, 0xC309, 0xBDD4, 0xC30A, 0x9AFB, 0xC30B, 0x9AFC,
+	0xC30C, 0xBDD5, 0xC30D, 0xBDD6, 0xC30E, 0x9AFD, 0xC30F, 0x9AFE,	0xC310, 0x9B41, 0xC311, 0x9B42, 0xC312, 0x9B43, 0xC313, 0xBDD7,
+	0xC314, 0xBDD8, 0xC315, 0xBDD9, 0xC316, 0x9B44, 0xC317, 0x9B45,	0xC318, 0xBDDA, 0xC319, 0x9B46, 0xC31A, 0x9B47, 0xC31B, 0x9B48,
+	0xC31C, 0xBDDB, 0xC31D, 0x9B49, 0xC31E, 0x9B4A, 0xC31F, 0x9B4B,	0xC320, 0x9B4C, 0xC321, 0x9B4D, 0xC322, 0x9B4E, 0xC323, 0x9B4F,
+	0xC324, 0xBDDC, 0xC325, 0xBDDD, 0xC326, 0x9B50, 0xC327, 0x9B51,	0xC328, 0xBDDE, 0xC329, 0xBDDF, 0xC32A, 0x9B52, 0xC32B, 0x9B53,
+	0xC32C, 0x9B54, 0xC32D, 0x9B55, 0xC32E, 0x9B56, 0xC32F, 0x9B57,	0xC330, 0x9B58, 0xC331, 0x9B59, 0xC332, 0x9B5A, 0xC333, 0x9B61,
+	0xC334, 0x9B62, 0xC335, 0x9B63, 0xC336, 0x9B64, 0xC337, 0x9B65,	0xC338, 0x9B66, 0xC339, 0x9B67, 0xC33A, 0x9B68, 0xC33B, 0x9B69,
+	0xC33C, 0x9B6A, 0xC33D, 0x9B6B, 0xC33E, 0x9B6C, 0xC33F, 0x9B6D,	0xC340, 0x9B6E, 0xC341, 0x9B6F, 0xC342, 0x9B70, 0xC343, 0x9B71,
+	0xC344, 0x9B72, 0xC345, 0xBDE0, 0xC346, 0x9B73, 0xC347, 0x9B74,	0xC348, 0x9B75, 0xC349, 0x9B76, 0xC34A, 0x9B77, 0xC34B, 0x9B78,
+	0xC34C, 0x9B79, 0xC34D, 0x9B7A, 0xC34E, 0x9B81, 0xC34F, 0x9B82,	0xC350, 0x9B83, 0xC351, 0x9B84, 0xC352, 0x9B85, 0xC353, 0x9B86,
+	0xC354, 0x9B87, 0xC355, 0x9B88, 0xC356, 0x9B89, 0xC357, 0x9B8A,	0xC358, 0x9B8B, 0xC359, 0x9B8C, 0xC35A, 0x9B8D, 0xC35B, 0x9B8E,
+	0xC35C, 0x9B8F, 0xC35D, 0x9B90, 0xC35E, 0x9B91, 0xC35F, 0x9B92,	0xC360, 0x9B93, 0xC361, 0x9B94, 0xC362, 0x9B95, 0xC363, 0x9B96,
+	0xC364, 0x9B97, 0xC365, 0x9B98, 0xC366, 0x9B99, 0xC367, 0x9B9A,	0xC368, 0xBDE1, 0xC369, 0xBDE2, 0xC36A, 0x9B9B, 0xC36B, 0x9B9C,
+	0xC36C, 0xBDE3, 0xC36D, 0x9B9D, 0xC36E, 0x9B9E, 0xC36F, 0x9B9F,	0xC370, 0xBDE4, 0xC371, 0x9BA0, 0xC372, 0xBDE5, 0xC373, 0x9BA1,
+	0xC374, 0x9BA2, 0xC375, 0x9BA3, 0xC376, 0x9BA4, 0xC377, 0x9BA5,	0xC378, 0xBDE6, 0xC379, 0xBDE7, 0xC37A, 0x9BA6, 0xC37B, 0x9BA7,
+	0xC37C, 0xBDE8, 0xC37D, 0xBDE9, 0xC37E, 0x9BA8, 0xC37F, 0x9BA9,	0xC380, 0x9BAA, 0xC381, 0x9BAB, 0xC382, 0x9BAC, 0xC383, 0x9BAD,
+	0xC384, 0xBDEA, 0xC385, 0x9BAE, 0xC386, 0x9BAF, 0xC387, 0x9BB0,	0xC388, 0xBDEB, 0xC389, 0x9BB1, 0xC38A, 0x9BB2, 0xC38B, 0x9BB3,
+	0xC38C, 0xBDEC, 0xC38D, 0x9BB4, 0xC38E, 0x9BB5, 0xC38F, 0x9BB6,	0xC390, 0x9BB7, 0xC391, 0x9BB8, 0xC392, 0x9BB9, 0xC393, 0x9BBA,
+	0xC394, 0x9BBB, 0xC395, 0x9BBC, 0xC396, 0x9BBD, 0xC397, 0x9BBE,	0xC398, 0x9BBF, 0xC399, 0x9BC0, 0xC39A, 0x9BC1, 0xC39B, 0x9BC2,
+	0xC39C, 0x9BC3, 0xC39D, 0x9BC4, 0xC39E, 0x9BC5, 0xC39F, 0x9BC6,	0xC3A0, 0x9BC7, 0xC3A1, 0x9BC8, 0xC3A2, 0x9BC9, 0xC3A3, 0x9BCA,
+	0xC3A4, 0x9BCB, 0xC3A5, 0x9BCC, 0xC3A6, 0x9BCD, 0xC3A7, 0x9BCE,	0xC3A8, 0x9BCF, 0xC3A9, 0x9BD0, 0xC3AA, 0x9BD1, 0xC3AB, 0x9BD2,
+	0xC3AC, 0x9BD3, 0xC3AD, 0x9BD4, 0xC3AE, 0x9BD5, 0xC3AF, 0x9BD6,	0xC3B0, 0x9BD7, 0xC3B1, 0x9BD8, 0xC3B2, 0x9BD9, 0xC3B3, 0x9BDA,
+	0xC3B4, 0x9BDB, 0xC3B5, 0x9BDC, 0xC3B6, 0x9BDD, 0xC3B7, 0x9BDE,	0xC3B8, 0x9BDF, 0xC3B9, 0x9BE0, 0xC3BA, 0x9BE1, 0xC3BB, 0x9BE2,
+	0xC3BC, 0x9BE3, 0xC3BD, 0x9BE4, 0xC3BE, 0x9BE5, 0xC3BF, 0x9BE6,	0xC3C0, 0xBDED, 0xC3C1, 0x9BE7, 0xC3C2, 0x9BE8, 0xC3C3, 0x9BE9,
+	0xC3C4, 0x9BEA, 0xC3C5, 0x9BEB, 0xC3C6, 0x9BEC, 0xC3C7, 0x9BED,	0xC3C8, 0x9BEE, 0xC3C9, 0x9BEF, 0xC3CA, 0x9BF0, 0xC3CB, 0x9BF1,
+	0xC3CC, 0x9BF2, 0xC3CD, 0x9BF3, 0xC3CE, 0x9BF4, 0xC3CF, 0x9BF5,	0xC3D0, 0x9BF6, 0xC3D1, 0x9BF7, 0xC3D2, 0x9BF8, 0xC3D3, 0x9BF9,
+	0xC3D4, 0x9BFA, 0xC3D5, 0x9BFB, 0xC3D6, 0x9BFC, 0xC3D7, 0x9BFD,	0xC3D8, 0xBDEE, 0xC3D9, 0xBDEF, 0xC3DA, 0x9BFE, 0xC3DB, 0x9C41,
+	0xC3DC, 0xBDF0, 0xC3DD, 0x9C42, 0xC3DE, 0x9C43, 0xC3DF, 0xBDF1,	0xC3E0, 0xBDF2, 0xC3E1, 0x9C44, 0xC3E2, 0xBDF3, 0xC3E3, 0x9C45,
+	0xC3E4, 0x9C46, 0xC3E5, 0x9C47, 0xC3E6, 0x9C48, 0xC3E7, 0x9C49,	0xC3E8, 0xBDF4, 0xC3E9, 0xBDF5, 0xC3EA, 0x9C4A, 0xC3EB, 0x9C4B,
+	0xC3EC, 0x9C4C, 0xC3ED, 0xBDF6, 0xC3EE, 0x9C4D, 0xC3EF, 0x9C4E,	0xC3F0, 0x9C4F, 0xC3F1, 0x9C50, 0xC3F2, 0x9C51, 0xC3F3, 0x9C52,
+	0xC3F4, 0xBDF7, 0xC3F5, 0xBDF8, 0xC3F6, 0x9C53, 0xC3F7, 0x9C54,	0xC3F8, 0xBDF9, 0xC3F9, 0x9C55, 0xC3FA, 0x9C56, 0xC3FB, 0x9C57,
+	0xC3FC, 0x9C58, 0xC3FD, 0x9C59, 0xC3FE, 0x9C5A, 0xC3FF, 0x9C61,	0xC400, 0x9C62, 0xC401, 0x9C63, 0xC402, 0x9C64, 0xC403, 0x9C65,
+	0xC404, 0x9C66, 0xC405, 0x9C67, 0xC406, 0x9C68, 0xC407, 0x9C69,	0xC408, 0xBDFA, 0xC409, 0x9C6A, 0xC40A, 0x9C6B, 0xC40B, 0x9C6C,
+	0xC40C, 0x9C6D, 0xC40D, 0x9C6E, 0xC40E, 0x9C6F, 0xC40F, 0x9C70,	0xC410, 0xBDFB, 0xC411, 0x9C71, 0xC412, 0x9C72, 0xC413, 0x9C73,
+	0xC414, 0x9C74, 0xC415, 0x9C75, 0xC416, 0x9C76, 0xC417, 0x9C77,	0xC418, 0x9C78, 0xC419, 0x9C79, 0xC41A, 0x9C7A, 0xC41B, 0x9C81,
+	0xC41C, 0x9C82, 0xC41D, 0x9C83, 0xC41E, 0x9C84, 0xC41F, 0x9C85,	0xC420, 0x9C86, 0xC421, 0x9C87, 0xC422, 0x9C88, 0xC423, 0x9C89,
+	0xC424, 0xBDFC, 0xC425, 0x9C8A, 0xC426, 0x9C8B, 0xC427, 0x9C8C,	0xC428, 0x9C8D, 0xC429, 0x9C8E, 0xC42A, 0x9C8F, 0xC42B, 0x9C90,
+	0xC42C, 0xBDFD, 0xC42D, 0x9C91, 0xC42E, 0x9C92, 0xC42F, 0x9C93,	0xC430, 0xBDFE, 0xC431, 0x9C94, 0xC432, 0x9C95, 0xC433, 0x9C96,
+	0xC434, 0xBEA1, 0xC435, 0x9C97, 0xC436, 0x9C98, 0xC437, 0x9C99,	0xC438, 0x9C9A, 0xC439, 0x9C9B, 0xC43A, 0x9C9C, 0xC43B, 0x9C9D,
+	0xC43C, 0xBEA2, 0xC43D, 0xBEA3, 0xC43E, 0x9C9E, 0xC43F, 0x9C9F,	0xC440, 0x9CA0, 0xC441, 0x9CA1, 0xC442, 0x9CA2, 0xC443, 0x9CA3,
+	0xC444, 0x9CA4, 0xC445, 0x9CA5, 0xC446, 0x9CA6, 0xC447, 0x9CA7,	0xC448, 0xBEA4, 0xC449, 0x9CA8, 0xC44A, 0x9CA9, 0xC44B, 0x9CAA,
+	0xC44C, 0x9CAB, 0xC44D, 0x9CAC, 0xC44E, 0x9CAD, 0xC44F, 0x9CAE,	0xC450, 0x9CAF, 0xC451, 0x9CB0, 0xC452, 0x9CB1, 0xC453, 0x9CB2,
+	0xC454, 0x9CB3, 0xC455, 0x9CB4, 0xC456, 0x9CB5, 0xC457, 0x9CB6,	0xC458, 0x9CB7, 0xC459, 0x9CB8, 0xC45A, 0x9CB9, 0xC45B, 0x9CBA,
+	0xC45C, 0x9CBB, 0xC45D, 0x9CBC, 0xC45E, 0x9CBD, 0xC45F, 0x9CBE,	0xC460, 0x9CBF, 0xC461, 0x9CC0, 0xC462, 0x9CC1, 0xC463, 0x9CC2,
+	0xC464, 0xBEA5, 0xC465, 0xBEA6, 0xC466, 0x9CC3, 0xC467, 0x9CC4,	0xC468, 0xBEA7, 0xC469, 0x9CC5, 0xC46A, 0x9CC6, 0xC46B, 0x9CC7,
+	0xC46C, 0xBEA8, 0xC46D, 0x9CC8, 0xC46E, 0x9CC9, 0xC46F, 0x9CCA,	0xC470, 0x9CCB, 0xC471, 0x9CCC, 0xC472, 0x9CCD, 0xC473, 0x9CCE,
+	0xC474, 0xBEA9, 0xC475, 0xBEAA, 0xC476, 0x9CCF, 0xC477, 0x9CD0,	0xC478, 0x9CD1, 0xC479, 0xBEAB, 0xC47A, 0x9CD2, 0xC47B, 0x9CD3,
+	0xC47C, 0x9CD4, 0xC47D, 0x9CD5, 0xC47E, 0x9CD6, 0xC47F, 0x9CD7,	0xC480, 0xBEAC, 0xC481, 0x9CD8, 0xC482, 0x9CD9, 0xC483, 0x9CDA,
+	0xC484, 0x9CDB, 0xC485, 0x9CDC, 0xC486, 0x9CDD, 0xC487, 0x9CDE,	0xC488, 0x9CDF, 0xC489, 0x9CE0, 0xC48A, 0x9CE1, 0xC48B, 0x9CE2,
+	0xC48C, 0x9CE3, 0xC48D, 0x9CE4, 0xC48E, 0x9CE5, 0xC48F, 0x9CE6,	0xC490, 0x9CE7, 0xC491, 0x9CE8, 0xC492, 0x9CE9, 0xC493, 0x9CEA,
+	0xC494, 0xBEAD, 0xC495, 0x9CEB, 0xC496, 0x9CEC, 0xC497, 0x9CED,	0xC498, 0x9CEE, 0xC499, 0x9CEF, 0xC49A, 0x9CF0, 0xC49B, 0x9CF1,
+	0xC49C, 0xBEAE, 0xC49D, 0x9CF2, 0xC49E, 0x9CF3, 0xC49F, 0x9CF4,	0xC4A0, 0x9CF5, 0xC4A1, 0x9CF6, 0xC4A2, 0x9CF7, 0xC4A3, 0x9CF8,
+	0xC4A4, 0x9CF9, 0xC4A5, 0x9CFA, 0xC4A6, 0x9CFB, 0xC4A7, 0x9CFC,	0xC4A8, 0x9CFD, 0xC4A9, 0x9CFE, 0xC4AA, 0x9D41, 0xC4AB, 0x9D42,
+	0xC4AC, 0x9D43, 0xC4AD, 0x9D44, 0xC4AE, 0x9D45, 0xC4AF, 0x9D46,	0xC4B0, 0x9D47, 0xC4B1, 0x9D48, 0xC4B2, 0x9D49, 0xC4B3, 0x9D4A,
+	0xC4B4, 0x9D4B, 0xC4B5, 0x9D4C, 0xC4B6, 0x9D4D, 0xC4B7, 0x9D4E,	0xC4B8, 0xBEAF, 0xC4B9, 0x9D4F, 0xC4BA, 0x9D50, 0xC4BB, 0x9D51,
+	0xC4BC, 0xBEB0, 0xC4BD, 0x9D52, 0xC4BE, 0x9D53, 0xC4BF, 0x9D54,	0xC4C0, 0x9D55, 0xC4C1, 0x9D56, 0xC4C2, 0x9D57, 0xC4C3, 0x9D58,
+	0xC4C4, 0x9D59, 0xC4C5, 0x9D5A, 0xC4C6, 0x9D61, 0xC4C7, 0x9D62,	0xC4C8, 0x9D63, 0xC4C9, 0x9D64, 0xC4CA, 0x9D65, 0xC4CB, 0x9D66,
+	0xC4CC, 0x9D67, 0xC4CD, 0x9D68, 0xC4CE, 0x9D69, 0xC4CF, 0x9D6A,	0xC4D0, 0x9D6B, 0xC4D1, 0x9D6C, 0xC4D2, 0x9D6D, 0xC4D3, 0x9D6E,
+	0xC4D4, 0x9D6F, 0xC4D5, 0x9D70, 0xC4D6, 0x9D71, 0xC4D7, 0x9D72,	0xC4D8, 0x9D73, 0xC4D9, 0x9D74, 0xC4DA, 0x9D75, 0xC4DB, 0x9D76,
+	0xC4DC, 0x9D77, 0xC4DD, 0x9D78, 0xC4DE, 0x9D79, 0xC4DF, 0x9D7A,	0xC4E0, 0x9D81, 0xC4E1, 0x9D82, 0xC4E2, 0x9D83, 0xC4E3, 0x9D84,
+	0xC4E4, 0x9D85, 0xC4E5, 0x9D86, 0xC4E6, 0x9D87, 0xC4E7, 0x9D88,	0xC4E8, 0x9D89, 0xC4E9, 0xBEB1, 0xC4EA, 0x9D8A, 0xC4EB, 0x9D8B,
+	0xC4EC, 0x9D8C, 0xC4ED, 0x9D8D, 0xC4EE, 0x9D8E, 0xC4EF, 0x9D8F,	0xC4F0, 0xBEB2, 0xC4F1, 0xBEB3, 0xC4F2, 0x9D90, 0xC4F3, 0x9D91,
+	0xC4F4, 0xBEB4, 0xC4F5, 0x9D92, 0xC4F6, 0x9D93, 0xC4F7, 0x9D94,	0xC4F8, 0xBEB5, 0xC4F9, 0x9D95, 0xC4FA, 0xBEB6, 0xC4FB, 0x9D96,
+	0xC4FC, 0x9D97, 0xC4FD, 0x9D98, 0xC4FE, 0x9D99, 0xC4FF, 0xBEB7,	0xC500, 0xBEB8, 0xC501, 0xBEB9, 0xC502, 0x9D9A, 0xC503, 0x9D9B,
+	0xC504, 0x9D9C, 0xC505, 0x9D9D, 0xC506, 0x9D9E, 0xC507, 0x9D9F,	0xC508, 0x9DA0, 0xC509, 0x9DA1, 0xC50A, 0x9DA2, 0xC50B, 0x9DA3,
+	0xC50C, 0xBEBA, 0xC50D, 0x9DA4, 0xC50E, 0x9DA5, 0xC50F, 0x9DA6,	0xC510, 0xBEBB, 0xC511, 0x9DA7, 0xC512, 0x9DA8, 0xC513, 0x9DA9,
+	0xC514, 0xBEBC, 0xC515, 0x9DAA, 0xC516, 0x9DAB, 0xC517, 0x9DAC,	0xC518, 0x9DAD, 0xC519, 0x9DAE, 0xC51A, 0x9DAF, 0xC51B, 0x9DB0,
+	0xC51C, 0xBEBD, 0xC51D, 0x9DB1, 0xC51E, 0x9DB2, 0xC51F, 0x9DB3,	0xC520, 0x9DB4, 0xC521, 0x9DB5, 0xC522, 0x9DB6, 0xC523, 0x9DB7,
+	0xC524, 0x9DB8, 0xC525, 0x9DB9, 0xC526, 0x9DBA, 0xC527, 0x9DBB,	0xC528, 0xBEBE, 0xC529, 0xBEBF, 0xC52A, 0x9DBC, 0xC52B, 0x9DBD,
+	0xC52C, 0xBEC0, 0xC52D, 0x9DBE, 0xC52E, 0x9DBF, 0xC52F, 0x9DC0,	0xC530, 0xBEC1, 0xC531, 0x9DC1, 0xC532, 0x9DC2, 0xC533, 0x9DC3,
+	0xC534, 0x9DC4, 0xC535, 0x9DC5, 0xC536, 0x9DC6, 0xC537, 0x9DC7,	0xC538, 0xBEC2, 0xC539, 0xBEC3, 0xC53A, 0x9DC8, 0xC53B, 0xBEC4,
+	0xC53C, 0x9DC9, 0xC53D, 0xBEC5, 0xC53E, 0x9DCA, 0xC53F, 0x9DCB,	0xC540, 0x9DCC, 0xC541, 0x9DCD, 0xC542, 0x9DCE, 0xC543, 0x9DCF,
+	0xC544, 0xBEC6, 0xC545, 0xBEC7, 0xC546, 0x9DD0, 0xC547, 0x9DD1,	0xC548, 0xBEC8, 0xC549, 0xBEC9, 0xC54A, 0xBECA, 0xC54B, 0x9DD2,
+	0xC54C, 0xBECB, 0xC54D, 0xBECC, 0xC54E, 0xBECD, 0xC54F, 0x9DD3,	0xC550, 0x9DD4, 0xC551, 0x9DD5, 0xC552, 0x9DD6, 0xC553, 0xBECE,
+	0xC554, 0xBECF, 0xC555, 0xBED0, 0xC556, 0x9DD7, 0xC557, 0xBED1,	0xC558, 0xBED2, 0xC559, 0xBED3, 0xC55A, 0x9DD8, 0xC55B, 0x9DD9,
+	0xC55C, 0x9DDA, 0xC55D, 0xBED4, 0xC55E, 0xBED5, 0xC55F, 0x9DDB,	0xC560, 0xBED6, 0xC561, 0xBED7, 0xC562, 0x9DDC, 0xC563, 0x9DDD,
+	0xC564, 0xBED8, 0xC565, 0x9DDE, 0xC566, 0x9DDF, 0xC567, 0x9DE0,	0xC568, 0xBED9, 0xC569, 0x9DE1, 0xC56A, 0x9DE2, 0xC56B, 0x9DE3,
+	0xC56C, 0x9DE4, 0xC56D, 0x9DE5, 0xC56E, 0x9DE6, 0xC56F, 0x9DE7,	0xC570, 0xBEDA, 0xC571, 0xBEDB, 0xC572, 0x9DE8, 0xC573, 0xBEDC,
+	0xC574, 0xBEDD, 0xC575, 0xBEDE, 0xC576, 0x9DE9, 0xC577, 0x9DEA,	0xC578, 0x9DEB, 0xC579, 0x9DEC, 0xC57A, 0x9DED, 0xC57B, 0x9DEE,
+	0xC57C, 0xBEDF, 0xC57D, 0xBEE0, 0xC57E, 0x9DEF, 0xC57F, 0x9DF0,	0xC580, 0xBEE1, 0xC581, 0x9DF1, 0xC582, 0x9DF2, 0xC583, 0x9DF3,
+	0xC584, 0xBEE2, 0xC585, 0x9DF4, 0xC586, 0x9DF5, 0xC587, 0xBEE3,	0xC588, 0x9DF6, 0xC589, 0x9DF7, 0xC58A, 0x9DF8, 0xC58B, 0x9DF9,
+	0xC58C, 0xBEE4, 0xC58D, 0xBEE5, 0xC58E, 0x9DFA, 0xC58F, 0xBEE6,	0xC590, 0x9DFB, 0xC591, 0xBEE7, 0xC592, 0x9DFC, 0xC593, 0x9DFD,
+	0xC594, 0x9DFE, 0xC595, 0xBEE8, 0xC596, 0x9E41, 0xC597, 0xBEE9,	0xC598, 0xBEEA, 0xC599, 0x9E42, 0xC59A, 0x9E43, 0xC59B, 0x9E44,
+	0xC59C, 0xBEEB, 0xC59D, 0x9E45, 0xC59E, 0x9E46, 0xC59F, 0x9E47,	0xC5A0, 0xBEEC, 0xC5A1, 0x9E48, 0xC5A2, 0x9E49, 0xC5A3, 0x9E4A,
+	0xC5A4, 0x9E4B, 0xC5A5, 0x9E4C, 0xC5A6, 0x9E4D, 0xC5A7, 0x9E4E,	0xC5A8, 0x9E4F, 0xC5A9, 0xBEED, 0xC5AA, 0x9E50, 0xC5AB, 0x9E51,
+	0xC5AC, 0x9E52, 0xC5AD, 0x9E53, 0xC5AE, 0x9E54, 0xC5AF, 0x9E55,	0xC5B0, 0x9E56, 0xC5B1, 0x9E57, 0xC5B2, 0x9E58, 0xC5B3, 0x9E59,
+	0xC5B4, 0xBEEE, 0xC5B5, 0xBEEF, 0xC5B6, 0x9E5A, 0xC5B7, 0x9E61,	0xC5B8, 0xBEF0, 0xC5B9, 0xBEF1, 0xC5BA, 0x9E62, 0xC5BB, 0xBEF2,
+	0xC5BC, 0xBEF3, 0xC5BD, 0xBEF4, 0xC5BE, 0xBEF5, 0xC5BF, 0x9E63,	0xC5C0, 0x9E64, 0xC5C1, 0x9E65, 0xC5C2, 0x9E66, 0xC5C3, 0x9E67,
+	0xC5C4, 0xBEF6, 0xC5C5, 0xBEF7, 0xC5C6, 0xBEF8, 0xC5C7, 0xBEF9,	0xC5C8, 0xBEFA, 0xC5C9, 0xBEFB, 0xC5CA, 0xBEFC, 0xC5CB, 0x9E68,
+	0xC5CC, 0xBEFD, 0xC5CD, 0x9E69, 0xC5CE, 0xBEFE, 0xC5CF, 0x9E6A,	0xC5D0, 0xBFA1, 0xC5D1, 0xBFA2, 0xC5D2, 0x9E6B, 0xC5D3, 0x9E6C,
+	0xC5D4, 0xBFA3, 0xC5D5, 0x9E6D, 0xC5D6, 0x9E6E, 0xC5D7, 0x9E6F,	0xC5D8, 0xBFA4, 0xC5D9, 0x9E70, 0xC5DA, 0x9E71, 0xC5DB, 0x9E72,
+	0xC5DC, 0x9E73, 0xC5DD, 0x9E74, 0xC5DE, 0x9E75, 0xC5DF, 0x9E76,	0xC5E0, 0xBFA5, 0xC5E1, 0xBFA6, 0xC5E2, 0x9E77, 0xC5E3, 0xBFA7,
+	0xC5E4, 0x9E78, 0xC5E5, 0xBFA8, 0xC5E6, 0x9E79, 0xC5E7, 0x9E7A,	0xC5E8, 0x9E81, 0xC5E9, 0x9E82, 0xC5EA, 0x9E83, 0xC5EB, 0x9E84,
+	0xC5EC, 0xBFA9, 0xC5ED, 0xBFAA, 0xC5EE, 0xBFAB, 0xC5EF, 0x9E85,	0xC5F0, 0xBFAC, 0xC5F1, 0x9E86, 0xC5F2, 0x9E87, 0xC5F3, 0x9E88,
+	0xC5F4, 0xBFAD, 0xC5F5, 0x9E89, 0xC5F6, 0xBFAE, 0xC5F7, 0xBFAF,	0xC5F8, 0x9E8A, 0xC5F9, 0x9E8B, 0xC5FA, 0x9E8C, 0xC5FB, 0x9E8D,
+	0xC5FC, 0xBFB0, 0xC5FD, 0xBFB1, 0xC5FE, 0xBFB2, 0xC5FF, 0xBFB3,	0xC600, 0xBFB4, 0xC601, 0xBFB5, 0xC602, 0x9E8E, 0xC603, 0x9E8F,
+	0xC604, 0x9E90, 0xC605, 0xBFB6, 0xC606, 0xBFB7, 0xC607, 0xBFB8,	0xC608, 0xBFB9, 0xC609, 0x9E91, 0xC60A, 0x9E92, 0xC60B, 0x9E93,
+	0xC60C, 0xBFBA, 0xC60D, 0x9E94, 0xC60E, 0x9E95, 0xC60F, 0x9E96,	0xC610, 0xBFBB, 0xC611, 0x9E97, 0xC612, 0x9E98, 0xC613, 0x9E99,
+	0xC614, 0x9E9A, 0xC615, 0x9E9B, 0xC616, 0x9E9C, 0xC617, 0x9E9D,	0xC618, 0xBFBC, 0xC619, 0xBFBD, 0xC61A, 0x9E9E, 0xC61B, 0xBFBE,
+	0xC61C, 0xBFBF, 0xC61D, 0x9E9F, 0xC61E, 0x9EA0, 0xC61F, 0x9EA1,	0xC620, 0x9EA2, 0xC621, 0x9EA3, 0xC622, 0x9EA4, 0xC623, 0x9EA5,
+	0xC624, 0xBFC0, 0xC625, 0xBFC1, 0xC626, 0x9EA6, 0xC627, 0x9EA7,	0xC628, 0xBFC2, 0xC629, 0x9EA8, 0xC62A, 0x9EA9, 0xC62B, 0x9EAA,
+	0xC62C, 0xBFC3, 0xC62D, 0xBFC4, 0xC62E, 0xBFC5, 0xC62F, 0x9EAB,	0xC630, 0xBFC6, 0xC631, 0x9EAC, 0xC632, 0x9EAD, 0xC633, 0xBFC7,
+	0xC634, 0xBFC8, 0xC635, 0xBFC9, 0xC636, 0x9EAE, 0xC637, 0xBFCA,	0xC638, 0x9EAF, 0xC639, 0xBFCB, 0xC63A, 0x9EB0, 0xC63B, 0xBFCC,
+	0xC63C, 0x9EB1, 0xC63D, 0x9EB2, 0xC63E, 0x9EB3, 0xC63F, 0x9EB4,	0xC640, 0xBFCD, 0xC641, 0xBFCE, 0xC642, 0x9EB5, 0xC643, 0x9EB6,
+	0xC644, 0xBFCF, 0xC645, 0x9EB7, 0xC646, 0x9EB8, 0xC647, 0x9EB9,	0xC648, 0xBFD0, 0xC649, 0x9EBA, 0xC64A, 0x9EBB, 0xC64B, 0x9EBC,
+	0xC64C, 0x9EBD, 0xC64D, 0x9EBE, 0xC64E, 0x9EBF, 0xC64F, 0x9EC0,	0xC650, 0xBFD1, 0xC651, 0xBFD2, 0xC652, 0x9EC1, 0xC653, 0xBFD3,
+	0xC654, 0xBFD4, 0xC655, 0xBFD5, 0xC656, 0x9EC2, 0xC657, 0x9EC3,	0xC658, 0x9EC4, 0xC659, 0x9EC5, 0xC65A, 0x9EC6, 0xC65B, 0x9EC7,
+	0xC65C, 0xBFD6, 0xC65D, 0xBFD7, 0xC65E, 0x9EC8, 0xC65F, 0x9EC9,	0xC660, 0xBFD8, 0xC661, 0x9ECA, 0xC662, 0x9ECB, 0xC663, 0x9ECC,
+	0xC664, 0x9ECD, 0xC665, 0x9ECE, 0xC666, 0x9ECF, 0xC667, 0x9ED0,	0xC668, 0x9ED1, 0xC669, 0x9ED2, 0xC66A, 0x9ED3, 0xC66B, 0x9ED4,
+	0xC66C, 0xBFD9, 0xC66D, 0x9ED5, 0xC66E, 0x9ED6, 0xC66F, 0xBFDA,	0xC670, 0x9ED7, 0xC671, 0xBFDB, 0xC672, 0x9ED8, 0xC673, 0x9ED9,
+	0xC674, 0x9EDA, 0xC675, 0x9EDB, 0xC676, 0x9EDC, 0xC677, 0x9EDD,	0xC678, 0xBFDC, 0xC679, 0xBFDD, 0xC67A, 0x9EDE, 0xC67B, 0x9EDF,
+	0xC67C, 0xBFDE, 0xC67D, 0x9EE0, 0xC67E, 0x9EE1, 0xC67F, 0x9EE2,	0xC680, 0xBFDF, 0xC681, 0x9EE3, 0xC682, 0x9EE4, 0xC683, 0x9EE5,
+	0xC684, 0x9EE6, 0xC685, 0x9EE7, 0xC686, 0x9EE8, 0xC687, 0x9EE9,	0xC688, 0xBFE0, 0xC689, 0xBFE1, 0xC68A, 0x9EEA, 0xC68B, 0xBFE2,
+	0xC68C, 0x9EEB, 0xC68D, 0xBFE3, 0xC68E, 0x9EEC, 0xC68F, 0x9EED,	0xC690, 0x9EEE, 0xC691, 0x9EEF, 0xC692, 0x9EF0, 0xC693, 0x9EF1,
+	0xC694, 0xBFE4, 0xC695, 0xBFE5, 0xC696, 0x9EF2, 0xC697, 0x9EF3,	0xC698, 0xBFE6, 0xC699, 0x9EF4, 0xC69A, 0x9EF5, 0xC69B, 0x9EF6,
+	0xC69C, 0xBFE7, 0xC69D, 0x9EF7, 0xC69E, 0x9EF8, 0xC69F, 0x9EF9,	0xC6A0, 0x9EFA, 0xC6A1, 0x9EFB, 0xC6A2, 0x9EFC, 0xC6A3, 0x9EFD,
+	0xC6A4, 0xBFE8, 0xC6A5, 0xBFE9, 0xC6A6, 0x9EFE, 0xC6A7, 0xBFEA,	0xC6A8, 0x9F41, 0xC6A9, 0xBFEB, 0xC6AA, 0x9F42, 0xC6AB, 0x9F43,
+	0xC6AC, 0x9F44, 0xC6AD, 0x9F45, 0xC6AE, 0x9F46, 0xC6AF, 0x9F47,	0xC6B0, 0xBFEC, 0xC6B1, 0xBFED, 0xC6B2, 0x9F48, 0xC6B3, 0x9F49,
+	0xC6B4, 0xBFEE, 0xC6B5, 0x9F4A, 0xC6B6, 0x9F4B, 0xC6B7, 0x9F4C,	0xC6B8, 0xBFEF, 0xC6B9, 0xBFF0, 0xC6BA, 0xBFF1, 0xC6BB, 0x9F4D,
+	0xC6BC, 0x9F4E, 0xC6BD, 0x9F4F, 0xC6BE, 0x9F50, 0xC6BF, 0x9F51,	0xC6C0, 0xBFF2, 0xC6C1, 0xBFF3, 0xC6C2, 0x9F52, 0xC6C3, 0xBFF4,
+	0xC6C4, 0x9F53, 0xC6C5, 0xBFF5, 0xC6C6, 0x9F54, 0xC6C7, 0x9F55,	0xC6C8, 0x9F56, 0xC6C9, 0x9F57, 0xC6CA, 0x9F58, 0xC6CB, 0x9F59,
+	0xC6CC, 0xBFF6, 0xC6CD, 0xBFF7, 0xC6CE, 0x9F5A, 0xC6CF, 0x9F61,	0xC6D0, 0xBFF8, 0xC6D1, 0x9F62, 0xC6D2, 0x9F63, 0xC6D3, 0x9F64,
+	0xC6D4, 0xBFF9, 0xC6D5, 0x9F65, 0xC6D6, 0x9F66, 0xC6D7, 0x9F67,	0xC6D8, 0x9F68, 0xC6D9, 0x9F69, 0xC6DA, 0x9F6A, 0xC6DB, 0x9F6B,
+	0xC6DC, 0xBFFA, 0xC6DD, 0xBFFB, 0xC6DE, 0x9F6C, 0xC6DF, 0x9F6D,	0xC6E0, 0xBFFC, 0xC6E1, 0xBFFD, 0xC6E2, 0x9F6E, 0xC6E3, 0x9F6F,
+	0xC6E4, 0x9F70, 0xC6E5, 0x9F71, 0xC6E6, 0x9F72, 0xC6E7, 0x9F73,	0xC6E8, 0xBFFE, 0xC6E9, 0xC0A1, 0xC6EA, 0x9F74, 0xC6EB, 0x9F75,
+	0xC6EC, 0xC0A2, 0xC6ED, 0x9F76, 0xC6EE, 0x9F77, 0xC6EF, 0x9F78,	0xC6F0, 0xC0A3, 0xC6F1, 0x9F79, 0xC6F2, 0x9F7A, 0xC6F3, 0x9F81,
+	0xC6F4, 0x9F82, 0xC6F5, 0x9F83, 0xC6F6, 0x9F84, 0xC6F7, 0x9F85,	0xC6F8, 0xC0A4, 0xC6F9, 0xC0A5, 0xC6FA, 0x9F86, 0xC6FB, 0x9F87,
+	0xC6FC, 0x9F88, 0xC6FD, 0xC0A6, 0xC6FE, 0x9F89, 0xC6FF, 0x9F8A,	0xC700, 0x9F8B, 0xC701, 0x9F8C, 0xC702, 0x9F8D, 0xC703, 0x9F8E,
+	0xC704, 0xC0A7, 0xC705, 0xC0A8, 0xC706, 0x9F8F, 0xC707, 0x9F90,	0xC708, 0xC0A9, 0xC709, 0x9F91, 0xC70A, 0x9F92, 0xC70B, 0x9F93,
+	0xC70C, 0xC0AA, 0xC70D, 0x9F94, 0xC70E, 0x9F95, 0xC70F, 0x9F96,	0xC710, 0x9F97, 0xC711, 0x9F98, 0xC712, 0x9F99, 0xC713, 0x9F9A,
+	0xC714, 0xC0AB, 0xC715, 0xC0AC, 0xC716, 0x9F9B, 0xC717, 0xC0AD,	0xC718, 0x9F9C, 0xC719, 0xC0AE, 0xC71A, 0x9F9D, 0xC71B, 0x9F9E,
+	0xC71C, 0x9F9F, 0xC71D, 0x9FA0, 0xC71E, 0x9FA1, 0xC71F, 0x9FA2,	0xC720, 0xC0AF, 0xC721, 0xC0B0, 0xC722, 0x9FA3, 0xC723, 0x9FA4,
+	0xC724, 0xC0B1, 0xC725, 0x9FA5, 0xC726, 0x9FA6, 0xC727, 0x9FA7,	0xC728, 0xC0B2, 0xC729, 0x9FA8, 0xC72A, 0x9FA9, 0xC72B, 0x9FAA,
+	0xC72C, 0x9FAB, 0xC72D, 0x9FAC, 0xC72E, 0x9FAD, 0xC72F, 0x9FAE,	0xC730, 0xC0B3, 0xC731, 0xC0B4, 0xC732, 0x9FAF, 0xC733, 0xC0B5,
+	0xC734, 0x9FB0, 0xC735, 0xC0B6, 0xC736, 0x9FB1, 0xC737, 0xC0B7,	0xC738, 0x9FB2, 0xC739, 0x9FB3, 0xC73A, 0x9FB4, 0xC73B, 0x9FB5,
+	0xC73C, 0xC0B8, 0xC73D, 0xC0B9, 0xC73E, 0x9FB6, 0xC73F, 0x9FB7,	0xC740, 0xC0BA, 0xC741, 0x9FB8, 0xC742, 0x9FB9, 0xC743, 0x9FBA,
+	0xC744, 0xC0BB, 0xC745, 0x9FBB, 0xC746, 0x9FBC, 0xC747, 0x9FBD,	0xC748, 0x9FBE, 0xC749, 0x9FBF, 0xC74A, 0xC0BC, 0xC74B, 0x9FC0,
+	0xC74C, 0xC0BD, 0xC74D, 0xC0BE, 0xC74E, 0x9FC1, 0xC74F, 0xC0BF,	0xC750, 0x9FC2, 0xC751, 0xC0C0, 0xC752, 0xC0C1, 0xC753, 0xC0C2,
+	0xC754, 0xC0C3, 0xC755, 0xC0C4, 0xC756, 0xC0C5, 0xC757, 0xC0C6,	0xC758, 0xC0C7, 0xC759, 0x9FC3, 0xC75A, 0x9FC4, 0xC75B, 0x9FC5,
+	0xC75C, 0xC0C8, 0xC75D, 0x9FC6, 0xC75E, 0x9FC7, 0xC75F, 0x9FC8,	0xC760, 0xC0C9, 0xC761, 0x9FC9, 0xC762, 0x9FCA, 0xC763, 0x9FCB,
+	0xC764, 0x9FCC, 0xC765, 0x9FCD, 0xC766, 0x9FCE, 0xC767, 0x9FCF,	0xC768, 0xC0CA, 0xC769, 0x9FD0, 0xC76A, 0x9FD1, 0xC76B, 0xC0CB,
+	0xC76C, 0x9FD2, 0xC76D, 0x9FD3, 0xC76E, 0x9FD4, 0xC76F, 0x9FD5,	0xC770, 0x9FD6, 0xC771, 0x9FD7, 0xC772, 0x9FD8, 0xC773, 0x9FD9,
+	0xC774, 0xC0CC, 0xC775, 0xC0CD, 0xC776, 0x9FDA, 0xC777, 0x9FDB,	0xC778, 0xC0CE, 0xC779, 0x9FDC, 0xC77A, 0x9FDD, 0xC77B, 0x9FDE,
+	0xC77C, 0xC0CF, 0xC77D, 0xC0D0, 0xC77E, 0xC0D1, 0xC77F, 0x9FDF,	0xC780, 0x9FE0, 0xC781, 0x9FE1, 0xC782, 0x9FE2, 0xC783, 0xC0D2,
+	0xC784, 0xC0D3, 0xC785, 0xC0D4, 0xC786, 0x9FE3, 0xC787, 0xC0D5,	0xC788, 0xC0D6, 0xC789, 0xC0D7, 0xC78A, 0xC0D8, 0xC78B, 0x9FE4,
+	0xC78C, 0x9FE5, 0xC78D, 0x9FE6, 0xC78E, 0xC0D9, 0xC78F, 0x9FE7,	0xC790, 0xC0DA, 0xC791, 0xC0DB, 0xC792, 0x9FE8, 0xC793, 0x9FE9,
+	0xC794, 0xC0DC, 0xC795, 0x9FEA, 0xC796, 0xC0DD, 0xC797, 0xC0DE,	0xC798, 0xC0DF, 0xC799, 0x9FEB, 0xC79A, 0xC0E0, 0xC79B, 0x9FEC,
+	0xC79C, 0x9FED, 0xC79D, 0x9FEE, 0xC79E, 0x9FEF, 0xC79F, 0x9FF0,	0xC7A0, 0xC0E1, 0xC7A1, 0xC0E2, 0xC7A2, 0x9FF1, 0xC7A3, 0xC0E3,
+	0xC7A4, 0xC0E4, 0xC7A5, 0xC0E5, 0xC7A6, 0xC0E6, 0xC7A7, 0x9FF2,	0xC7A8, 0x9FF3, 0xC7A9, 0x9FF4, 0xC7AA, 0x9FF5, 0xC7AB, 0x9FF6,
+	0xC7AC, 0xC0E7, 0xC7AD, 0xC0E8, 0xC7AE, 0x9FF7, 0xC7AF, 0x9FF8,	0xC7B0, 0xC0E9, 0xC7B1, 0x9FF9, 0xC7B2, 0x9FFA, 0xC7B3, 0x9FFB,
+	0xC7B4, 0xC0EA, 0xC7B5, 0x9FFC, 0xC7B6, 0x9FFD, 0xC7B7, 0x9FFE,	0xC7B8, 0xA041, 0xC7B9, 0xA042, 0xC7BA, 0xA043, 0xC7BB, 0xA044,
+	0xC7BC, 0xC0EB, 0xC7BD, 0xC0EC, 0xC7BE, 0xA045, 0xC7BF, 0xC0ED,	0xC7C0, 0xC0EE, 0xC7C1, 0xC0EF, 0xC7C2, 0xA046, 0xC7C3, 0xA047,
+	0xC7C4, 0xA048, 0xC7C5, 0xA049, 0xC7C6, 0xA04A, 0xC7C7, 0xA04B,	0xC7C8, 0xC0F0, 0xC7C9, 0xC0F1, 0xC7CA, 0xA04C, 0xC7CB, 0xA04D,
+	0xC7CC, 0xC0F2, 0xC7CD, 0xA04E, 0xC7CE, 0xC0F3, 0xC7CF, 0xA04F,	0xC7D0, 0xC0F4, 0xC7D1, 0xA050, 0xC7D2, 0xA051, 0xC7D3, 0xA052,
+	0xC7D4, 0xA053, 0xC7D5, 0xA054, 0xC7D6, 0xA055, 0xC7D7, 0xA056,	0xC7D8, 0xC0F5, 0xC7D9, 0xA057, 0xC7DA, 0xA058, 0xC7DB, 0xA059,
+	0xC7DC, 0xA05A, 0xC7DD, 0xC0F6, 0xC7DE, 0xA061, 0xC7DF, 0xA062,	0xC7E0, 0xA063, 0xC7E1, 0xA064, 0xC7E2, 0xA065, 0xC7E3, 0xA066,
+	0xC7E4, 0xC0F7, 0xC7E5, 0xA067, 0xC7E6, 0xA068, 0xC7E7, 0xA069,	0xC7E8, 0xC0F8, 0xC7E9, 0xA06A, 0xC7EA, 0xA06B, 0xC7EB, 0xA06C,
+	0xC7EC, 0xC0F9, 0xC7ED, 0xA06D, 0xC7EE, 0xA06E, 0xC7EF, 0xA06F,	0xC7F0, 0xA070, 0xC7F1, 0xA071, 0xC7F2, 0xA072, 0xC7F3, 0xA073,
+	0xC7F4, 0xA074, 0xC7F5, 0xA075, 0xC7F6, 0xA076, 0xC7F7, 0xA077,	0xC7F8, 0xA078, 0xC7F9, 0xA079, 0xC7FA, 0xA07A, 0xC7FB, 0xA081,
+	0xC7FC, 0xA082, 0xC7FD, 0xA083, 0xC7FE, 0xA084, 0xC7FF, 0xA085,	0xC800, 0xC0FA, 0xC801, 0xC0FB, 0xC802, 0xA086, 0xC803, 0xA087,
+	0xC804, 0xC0FC, 0xC805, 0xA088, 0xC806, 0xA089, 0xC807, 0xA08A,	0xC808, 0xC0FD, 0xC809, 0xA08B, 0xC80A, 0xC0FE, 0xC80B, 0xA08C,
+	0xC80C, 0xA08D, 0xC80D, 0xA08E, 0xC80E, 0xA08F, 0xC80F, 0xA090,	0xC810, 0xC1A1, 0xC811, 0xC1A2, 0xC812, 0xA091, 0xC813, 0xC1A3,
+	0xC814, 0xA092, 0xC815, 0xC1A4, 0xC816, 0xC1A5, 0xC817, 0xA093,	0xC818, 0xA094, 0xC819, 0xA095, 0xC81A, 0xA096, 0xC81B, 0xA097,
+	0xC81C, 0xC1A6, 0xC81D, 0xC1A7, 0xC81E, 0xA098, 0xC81F, 0xA099,	0xC820, 0xC1A8, 0xC821, 0xA09A, 0xC822, 0xA09B, 0xC823, 0xA09C,
+	0xC824, 0xC1A9, 0xC825, 0xA09D, 0xC826, 0xA09E, 0xC827, 0xA09F,	0xC828, 0xA0A0, 0xC829, 0xA0A1, 0xC82A, 0xA0A2, 0xC82B, 0xA0A3,
+	0xC82C, 0xC1AA, 0xC82D, 0xC1AB, 0xC82E, 0xA0A4, 0xC82F, 0xC1AC,	0xC830, 0xA0A5, 0xC831, 0xC1AD, 0xC832, 0xA0A6, 0xC833, 0xA0A7,
+	0xC834, 0xA0A8, 0xC835, 0xA0A9, 0xC836, 0xA0AA, 0xC837, 0xA0AB,	0xC838, 0xC1AE, 0xC839, 0xA0AC, 0xC83A, 0xA0AD, 0xC83B, 0xA0AE,
+	0xC83C, 0xC1AF, 0xC83D, 0xA0AF, 0xC83E, 0xA0B0, 0xC83F, 0xA0B1,	0xC840, 0xC1B0, 0xC841, 0xA0B2, 0xC842, 0xA0B3, 0xC843, 0xA0B4,
+	0xC844, 0xA0B5, 0xC845, 0xA0B6, 0xC846, 0xA0B7, 0xC847, 0xA0B8,	0xC848, 0xC1B1, 0xC849, 0xC1B2, 0xC84A, 0xA0B9, 0xC84B, 0xA0BA,
+	0xC84C, 0xC1B3, 0xC84D, 0xC1B4, 0xC84E, 0xA0BB, 0xC84F, 0xA0BC,	0xC850, 0xA0BD, 0xC851, 0xA0BE, 0xC852, 0xA0BF, 0xC853, 0xA0C0,
+	0xC854, 0xC1B5, 0xC855, 0xA0C1, 0xC856, 0xA0C2, 0xC857, 0xA0C3,	0xC858, 0xA0C4, 0xC859, 0xA0C5, 0xC85A, 0xA0C6, 0xC85B, 0xA0C7,
+	0xC85C, 0xA0C8, 0xC85D, 0xA0C9, 0xC85E, 0xA0CA, 0xC85F, 0xA0CB,	0xC860, 0xA0CC, 0xC861, 0xA0CD, 0xC862, 0xA0CE, 0xC863, 0xA0CF,
+	0xC864, 0xA0D0, 0xC865, 0xA0D1, 0xC866, 0xA0D2, 0xC867, 0xA0D3,	0xC868, 0xA0D4, 0xC869, 0xA0D5, 0xC86A, 0xA0D6, 0xC86B, 0xA0D7,
+	0xC86C, 0xA0D8, 0xC86D, 0xA0D9, 0xC86E, 0xA0DA, 0xC86F, 0xA0DB,	0xC870, 0xC1B6, 0xC871, 0xC1B7, 0xC872, 0xA0DC, 0xC873, 0xA0DD,
+	0xC874, 0xC1B8, 0xC875, 0xA0DE, 0xC876, 0xA0DF, 0xC877, 0xA0E0,	0xC878, 0xC1B9, 0xC879, 0xA0E1, 0xC87A, 0xC1BA, 0xC87B, 0xA0E2,
+	0xC87C, 0xA0E3, 0xC87D, 0xA0E4, 0xC87E, 0xA0E5, 0xC87F, 0xA0E6,	0xC880, 0xC1BB, 0xC881, 0xC1BC, 0xC882, 0xA0E7, 0xC883, 0xC1BD,
+	0xC884, 0xA0E8, 0xC885, 0xC1BE, 0xC886, 0xC1BF, 0xC887, 0xC1C0,	0xC888, 0xA0E9, 0xC889, 0xA0EA, 0xC88A, 0xA0EB, 0xC88B, 0xC1C1,
+	0xC88C, 0xC1C2, 0xC88D, 0xC1C3, 0xC88E, 0xA0EC, 0xC88F, 0xA0ED,	0xC890, 0xA0EE, 0xC891, 0xA0EF, 0xC892, 0xA0F0, 0xC893, 0xA0F1,
+	0xC894, 0xC1C4, 0xC895, 0xA0F2, 0xC896, 0xA0F3, 0xC897, 0xA0F4,	0xC898, 0xA0F5, 0xC899, 0xA0F6, 0xC89A, 0xA0F7, 0xC89B, 0xA0F8,
+	0xC89C, 0xA0F9, 0xC89D, 0xC1C5, 0xC89E, 0xA0FA, 0xC89F, 0xC1C6,	0xC8A0, 0xA0FB, 0xC8A1, 0xC1C7, 0xC8A2, 0xA0FC, 0xC8A3, 0xA0FD,
+	0xC8A4, 0xA0FE, 0xC8A5, 0xA141, 0xC8A6, 0xA142, 0xC8A7, 0xA143,	0xC8A8, 0xC1C8, 0xC8A9, 0xA144, 0xC8AA, 0xA145, 0xC8AB, 0xA146,
+	0xC8AC, 0xA147, 0xC8AD, 0xA148, 0xC8AE, 0xA149, 0xC8AF, 0xA14A,	0xC8B0, 0xA14B, 0xC8B1, 0xA14C, 0xC8B2, 0xA14D, 0xC8B3, 0xA14E,
+	0xC8B4, 0xA14F, 0xC8B5, 0xA150, 0xC8B6, 0xA151, 0xC8B7, 0xA152,	0xC8B8, 0xA153, 0xC8B9, 0xA154, 0xC8BA, 0xA155, 0xC8BB, 0xA156,
+	0xC8BC, 0xC1C9, 0xC8BD, 0xC1CA, 0xC8BE, 0xA157, 0xC8BF, 0xA158,	0xC8C0, 0xA159, 0xC8C1, 0xA15A, 0xC8C2, 0xA161, 0xC8C3, 0xA162,
+	0xC8C4, 0xC1CB, 0xC8C5, 0xA163, 0xC8C6, 0xA164, 0xC8C7, 0xA165,	0xC8C8, 0xC1CC, 0xC8C9, 0xA166, 0xC8CA, 0xA167, 0xC8CB, 0xA168,
+	0xC8CC, 0xC1CD, 0xC8CD, 0xA169, 0xC8CE, 0xA16A, 0xC8CF, 0xA16B,	0xC8D0, 0xA16C, 0xC8D1, 0xA16D, 0xC8D2, 0xA16E, 0xC8D3, 0xA16F,
+	0xC8D4, 0xC1CE, 0xC8D5, 0xC1CF, 0xC8D6, 0xA170, 0xC8D7, 0xC1D0,	0xC8D8, 0xA171, 0xC8D9, 0xC1D1, 0xC8DA, 0xA172, 0xC8DB, 0xA173,
+	0xC8DC, 0xA174, 0xC8DD, 0xA175, 0xC8DE, 0xA176, 0xC8DF, 0xA177,	0xC8E0, 0xC1D2, 0xC8E1, 0xC1D3, 0xC8E2, 0xA178, 0xC8E3, 0xA179,
+	0xC8E4, 0xC1D4, 0xC8E5, 0xA17A, 0xC8E6, 0xA181, 0xC8E7, 0xA182,	0xC8E8, 0xA183, 0xC8E9, 0xA184, 0xC8EA, 0xA185, 0xC8EB, 0xA186,
+	0xC8EC, 0xA187, 0xC8ED, 0xA188, 0xC8EE, 0xA189, 0xC8EF, 0xA18A,	0xC8F0, 0xA18B, 0xC8F1, 0xA18C, 0xC8F2, 0xA18D, 0xC8F3, 0xA18E,
+	0xC8F4, 0xA18F, 0xC8F5, 0xC1D5, 0xC8F6, 0xA190, 0xC8F7, 0xA191,	0xC8F8, 0xA192, 0xC8F9, 0xA193, 0xC8FA, 0xA194, 0xC8FB, 0xA195,
+	0xC8FC, 0xC1D6, 0xC8FD, 0xC1D7, 0xC8FE, 0xA196, 0xC8FF, 0xA197,	0xC900, 0xC1D8, 0xC901, 0xA198, 0xC902, 0xA199, 0xC903, 0xA19A,
+	0xC904, 0xC1D9, 0xC905, 0xC1DA, 0xC906, 0xC1DB, 0xC907, 0xA19B,	0xC908, 0xA19C, 0xC909, 0xA19D, 0xC90A, 0xA19E, 0xC90B, 0xA19F,
+	0xC90C, 0xC1DC, 0xC90D, 0xC1DD, 0xC90E, 0xA1A0, 0xC90F, 0xC1DE,	0xC910, 0xA241, 0xC911, 0xC1DF, 0xC912, 0xA242, 0xC913, 0xA243,
+	0xC914, 0xA244, 0xC915, 0xA245, 0xC916, 0xA246, 0xC917, 0xA247,	0xC918, 0xC1E0, 0xC919, 0xA248, 0xC91A, 0xA249, 0xC91B, 0xA24A,
+	0xC91C, 0xA24B, 0xC91D, 0xA24C, 0xC91E, 0xA24D, 0xC91F, 0xA24E,	0xC920, 0xA24F, 0xC921, 0xA250, 0xC922, 0xA251, 0xC923, 0xA252,
+	0xC924, 0xA253, 0xC925, 0xA254, 0xC926, 0xA255, 0xC927, 0xA256,	0xC928, 0xA257, 0xC929, 0xA258, 0xC92A, 0xA259, 0xC92B, 0xA25A,
+	0xC92C, 0xC1E1, 0xC92D, 0xA261, 0xC92E, 0xA262, 0xC92F, 0xA263,	0xC930, 0xA264, 0xC931, 0xA265, 0xC932, 0xA266, 0xC933, 0xA267,
+	0xC934, 0xC1E2, 0xC935, 0xA268, 0xC936, 0xA269, 0xC937, 0xA26A,	0xC938, 0xA26B, 0xC939, 0xA26C, 0xC93A, 0xA26D, 0xC93B, 0xA26E,
+	0xC93C, 0xA26F, 0xC93D, 0xA270, 0xC93E, 0xA271, 0xC93F, 0xA272,	0xC940, 0xA273, 0xC941, 0xA274, 0xC942, 0xA275, 0xC943, 0xA276,
+	0xC944, 0xA277, 0xC945, 0xA278, 0xC946, 0xA279, 0xC947, 0xA27A,	0xC948, 0xA281, 0xC949, 0xA282, 0xC94A, 0xA283, 0xC94B, 0xA284,
+	0xC94C, 0xA285, 0xC94D, 0xA286, 0xC94E, 0xA287, 0xC94F, 0xA288,	0xC950, 0xC1E3, 0xC951, 0xC1E4, 0xC952, 0xA289, 0xC953, 0xA28A,
+	0xC954, 0xC1E5, 0xC955, 0xA28B, 0xC956, 0xA28C, 0xC957, 0xA28D,	0xC958, 0xC1E6, 0xC959, 0xA28E, 0xC95A, 0xA28F, 0xC95B, 0xA290,
+	0xC95C, 0xA291, 0xC95D, 0xA292, 0xC95E, 0xA293, 0xC95F, 0xA294,	0xC960, 0xC1E7, 0xC961, 0xC1E8, 0xC962, 0xA295, 0xC963, 0xC1E9,
+	0xC964, 0xA296, 0xC965, 0xA297, 0xC966, 0xA298, 0xC967, 0xA299,	0xC968, 0xA29A, 0xC969, 0xA29B, 0xC96A, 0xA29C, 0xC96B, 0xA29D,
+	0xC96C, 0xC1EA, 0xC96D, 0xA29E, 0xC96E, 0xA29F, 0xC96F, 0xA2A0,	0xC970, 0xC1EB, 0xC971, 0xA341, 0xC972, 0xA342, 0xC973, 0xA343,
+	0xC974, 0xC1EC, 0xC975, 0xA344, 0xC976, 0xA345, 0xC977, 0xA346,	0xC978, 0xA347, 0xC979, 0xA348, 0xC97A, 0xA349, 0xC97B, 0xA34A,
+	0xC97C, 0xC1ED, 0xC97D, 0xA34B, 0xC97E, 0xA34C, 0xC97F, 0xA34D,	0xC980, 0xA34E, 0xC981, 0xA34F, 0xC982, 0xA350, 0xC983, 0xA351,
+	0xC984, 0xA352, 0xC985, 0xA353, 0xC986, 0xA354, 0xC987, 0xA355,	0xC988, 0xC1EE, 0xC989, 0xC1EF, 0xC98A, 0xA356, 0xC98B, 0xA357,
+	0xC98C, 0xC1F0, 0xC98D, 0xA358, 0xC98E, 0xA359, 0xC98F, 0xA35A,	0xC990, 0xC1F1, 0xC991, 0xA361, 0xC992, 0xA362, 0xC993, 0xA363,
+	0xC994, 0xA364, 0xC995, 0xA365, 0xC996, 0xA366, 0xC997, 0xA367,	0xC998, 0xC1F2, 0xC999, 0xC1F3, 0xC99A, 0xA368, 0xC99B, 0xC1F4,
+	0xC99C, 0xA369, 0xC99D, 0xC1F5, 0xC99E, 0xA36A, 0xC99F, 0xA36B,	0xC9A0, 0xA36C, 0xC9A1, 0xA36D, 0xC9A2, 0xA36E, 0xC9A3, 0xA36F,
+	0xC9A4, 0xA370, 0xC9A5, 0xA371, 0xC9A6, 0xA372, 0xC9A7, 0xA373,	0xC9A8, 0xA374, 0xC9A9, 0xA375, 0xC9AA, 0xA376, 0xC9AB, 0xA377,
+	0xC9AC, 0xA378, 0xC9AD, 0xA379, 0xC9AE, 0xA37A, 0xC9AF, 0xA381,	0xC9B0, 0xA382, 0xC9B1, 0xA383, 0xC9B2, 0xA384, 0xC9B3, 0xA385,
+	0xC9B4, 0xA386, 0xC9B5, 0xA387, 0xC9B6, 0xA388, 0xC9B7, 0xA389,	0xC9B8, 0xA38A, 0xC9B9, 0xA38B, 0xC9BA, 0xA38C, 0xC9BB, 0xA38D,
+	0xC9BC, 0xA38E, 0xC9BD, 0xA38F, 0xC9BE, 0xA390, 0xC9BF, 0xA391,	0xC9C0, 0xC1F6, 0xC9C1, 0xC1F7, 0xC9C2, 0xA392, 0xC9C3, 0xA393,
+	0xC9C4, 0xC1F8, 0xC9C5, 0xA394, 0xC9C6, 0xA395, 0xC9C7, 0xC1F9,	0xC9C8, 0xC1FA, 0xC9C9, 0xA396, 0xC9CA, 0xC1FB, 0xC9CB, 0xA397,
+	0xC9CC, 0xA398, 0xC9CD, 0xA399, 0xC9CE, 0xA39A, 0xC9CF, 0xA39B,	0xC9D0, 0xC1FC, 0xC9D1, 0xC1FD, 0xC9D2, 0xA39C, 0xC9D3, 0xC1FE,
+	0xC9D4, 0xA39D, 0xC9D5, 0xC2A1, 0xC9D6, 0xC2A2, 0xC9D7, 0xA39E,	0xC9D8, 0xA39F, 0xC9D9, 0xC2A3, 0xC9DA, 0xC2A4, 0xC9DB, 0xA3A0,
+	0xC9DC, 0xC2A5, 0xC9DD, 0xC2A6, 0xC9DE, 0xA441, 0xC9DF, 0xA442,	0xC9E0, 0xC2A7, 0xC9E1, 0xA443, 0xC9E2, 0xC2A8, 0xC9E3, 0xA444,
+	0xC9E4, 0xC2A9, 0xC9E5, 0xA445, 0xC9E6, 0xA446, 0xC9E7, 0xC2AA,	0xC9E8, 0xA447, 0xC9E9, 0xA448, 0xC9EA, 0xA449, 0xC9EB, 0xA44A,
+	0xC9EC, 0xC2AB, 0xC9ED, 0xC2AC, 0xC9EE, 0xA44B, 0xC9EF, 0xC2AD,	0xC9F0, 0xC2AE, 0xC9F1, 0xC2AF, 0xC9F2, 0xA44C, 0xC9F3, 0xA44D,
+	0xC9F4, 0xA44E, 0xC9F5, 0xA44F, 0xC9F6, 0xA450, 0xC9F7, 0xA451,	0xC9F8, 0xC2B0, 0xC9F9, 0xC2B1, 0xC9FA, 0xA452, 0xC9FB, 0xA453,
+	0xC9FC, 0xC2B2, 0xC9FD, 0xA454, 0xC9FE, 0xA455, 0xC9FF, 0xA456,	0xCA00, 0xC2B3, 0xCA01, 0xA457, 0xCA02, 0xA458, 0xCA03, 0xA459,
+	0xCA04, 0xA45A, 0xCA05, 0xA461, 0xCA06, 0xA462, 0xCA07, 0xA463,	0xCA08, 0xC2B4, 0xCA09, 0xC2B5, 0xCA0A, 0xA464, 0xCA0B, 0xC2B6,
+	0xCA0C, 0xC2B7, 0xCA0D, 0xC2B8, 0xCA0E, 0xA465, 0xCA0F, 0xA466,	0xCA10, 0xA467, 0xCA11, 0xA468, 0xCA12, 0xA469, 0xCA13, 0xA46A,
+	0xCA14, 0xC2B9, 0xCA15, 0xA46B, 0xCA16, 0xA46C, 0xCA17, 0xA46D,	0xCA18, 0xC2BA, 0xCA19, 0xA46E, 0xCA1A, 0xA46F, 0xCA1B, 0xA470,
+	0xCA1C, 0xA471, 0xCA1D, 0xA472, 0xCA1E, 0xA473, 0xCA1F, 0xA474,	0xCA20, 0xA475, 0xCA21, 0xA476, 0xCA22, 0xA477, 0xCA23, 0xA478,
+	0xCA24, 0xA479, 0xCA25, 0xA47A, 0xCA26, 0xA481, 0xCA27, 0xA482,	0xCA28, 0xA483, 0xCA29, 0xC2BB, 0xCA2A, 0xA484, 0xCA2B, 0xA485,
+	0xCA2C, 0xA486, 0xCA2D, 0xA487, 0xCA2E, 0xA488, 0xCA2F, 0xA489,	0xCA30, 0xA48A, 0xCA31, 0xA48B, 0xCA32, 0xA48C, 0xCA33, 0xA48D,
+	0xCA34, 0xA48E, 0xCA35, 0xA48F, 0xCA36, 0xA490, 0xCA37, 0xA491,	0xCA38, 0xA492, 0xCA39, 0xA493, 0xCA3A, 0xA494, 0xCA3B, 0xA495,
+	0xCA3C, 0xA496, 0xCA3D, 0xA497, 0xCA3E, 0xA498, 0xCA3F, 0xA499,	0xCA40, 0xA49A, 0xCA41, 0xA49B, 0xCA42, 0xA49C, 0xCA43, 0xA49D,
+	0xCA44, 0xA49E, 0xCA45, 0xA49F, 0xCA46, 0xA4A0, 0xCA47, 0xA541,	0xCA48, 0xA542, 0xCA49, 0xA543, 0xCA4A, 0xA544, 0xCA4B, 0xA545,
+	0xCA4C, 0xC2BC, 0xCA4D, 0xC2BD, 0xCA4E, 0xA546, 0xCA4F, 0xA547,	0xCA50, 0xC2BE, 0xCA51, 0xA548, 0xCA52, 0xA549, 0xCA53, 0xA54A,
+	0xCA54, 0xC2BF, 0xCA55, 0xA54B, 0xCA56, 0xA54C, 0xCA57, 0xA54D,	0xCA58, 0xA54E, 0xCA59, 0xA54F, 0xCA5A, 0xA550, 0xCA5B, 0xA551,
+	0xCA5C, 0xC2C0, 0xCA5D, 0xC2C1, 0xCA5E, 0xA552, 0xCA5F, 0xC2C2,	0xCA60, 0xC2C3, 0xCA61, 0xC2C4, 0xCA62, 0xA553, 0xCA63, 0xA554,
+	0xCA64, 0xA555, 0xCA65, 0xA556, 0xCA66, 0xA557, 0xCA67, 0xA558,	0xCA68, 0xC2C5, 0xCA69, 0xA559, 0xCA6A, 0xA55A, 0xCA6B, 0xA561,
+	0xCA6C, 0xA562, 0xCA6D, 0xA563, 0xCA6E, 0xA564, 0xCA6F, 0xA565,	0xCA70, 0xA566, 0xCA71, 0xA567, 0xCA72, 0xA568, 0xCA73, 0xA569,
+	0xCA74, 0xA56A, 0xCA75, 0xA56B, 0xCA76, 0xA56C, 0xCA77, 0xA56D,	0xCA78, 0xA56E, 0xCA79, 0xA56F, 0xCA7A, 0xA570, 0xCA7B, 0xA571,
+	0xCA7C, 0xA572, 0xCA7D, 0xC2C6, 0xCA7E, 0xA573, 0xCA7F, 0xA574,	0xCA80, 0xA575, 0xCA81, 0xA576, 0xCA82, 0xA577, 0xCA83, 0xA578,
+	0xCA84, 0xC2C7, 0xCA85, 0xA579, 0xCA86, 0xA57A, 0xCA87, 0xA581,	0xCA88, 0xA582, 0xCA89, 0xA583, 0xCA8A, 0xA584, 0xCA8B, 0xA585,
+	0xCA8C, 0xA586, 0xCA8D, 0xA587, 0xCA8E, 0xA588, 0xCA8F, 0xA589,	0xCA90, 0xA58A, 0xCA91, 0xA58B, 0xCA92, 0xA58C, 0xCA93, 0xA58D,
+	0xCA94, 0xA58E, 0xCA95, 0xA58F, 0xCA96, 0xA590, 0xCA97, 0xA591,	0xCA98, 0xC2C8, 0xCA99, 0xA592, 0xCA9A, 0xA593, 0xCA9B, 0xA594,
+	0xCA9C, 0xA595, 0xCA9D, 0xA596, 0xCA9E, 0xA597, 0xCA9F, 0xA598,	0xCAA0, 0xA599, 0xCAA1, 0xA59A, 0xCAA2, 0xA59B, 0xCAA3, 0xA59C,
+	0xCAA4, 0xA59D, 0xCAA5, 0xA59E, 0xCAA6, 0xA59F, 0xCAA7, 0xA5A0,	0xCAA8, 0xA641, 0xCAA9, 0xA642, 0xCAAA, 0xA643, 0xCAAB, 0xA644,
+	0xCAAC, 0xA645, 0xCAAD, 0xA646, 0xCAAE, 0xA647, 0xCAAF, 0xA648,	0xCAB0, 0xA649, 0xCAB1, 0xA64A, 0xCAB2, 0xA64B, 0xCAB3, 0xA64C,
+	0xCAB4, 0xA64D, 0xCAB5, 0xA64E, 0xCAB6, 0xA64F, 0xCAB7, 0xA650,	0xCAB8, 0xA651, 0xCAB9, 0xA652, 0xCABA, 0xA653, 0xCABB, 0xA654,
+	0xCABC, 0xC2C9, 0xCABD, 0xC2CA, 0xCABE, 0xA655, 0xCABF, 0xA656,	0xCAC0, 0xC2CB, 0xCAC1, 0xA657, 0xCAC2, 0xA658, 0xCAC3, 0xA659,
+	0xCAC4, 0xC2CC, 0xCAC5, 0xA65A, 0xCAC6, 0xA661, 0xCAC7, 0xA662,	0xCAC8, 0xA663, 0xCAC9, 0xA664, 0xCACA, 0xA665, 0xCACB, 0xA666,
+	0xCACC, 0xC2CD, 0xCACD, 0xC2CE, 0xCACE, 0xA667, 0xCACF, 0xC2CF,	0xCAD0, 0xA668, 0xCAD1, 0xC2D0, 0xCAD2, 0xA669, 0xCAD3, 0xC2D1,
+	0xCAD4, 0xA66A, 0xCAD5, 0xA66B, 0xCAD6, 0xA66C, 0xCAD7, 0xA66D,	0xCAD8, 0xC2D2, 0xCAD9, 0xC2D3, 0xCADA, 0xA66E, 0xCADB, 0xA66F,
+	0xCADC, 0xA670, 0xCADD, 0xA671, 0xCADE, 0xA672, 0xCADF, 0xA673,	0xCAE0, 0xC2D4, 0xCAE1, 0xA674, 0xCAE2, 0xA675, 0xCAE3, 0xA676,
+	0xCAE4, 0xA677, 0xCAE5, 0xA678, 0xCAE6, 0xA679, 0xCAE7, 0xA67A,	0xCAE8, 0xA681, 0xCAE9, 0xA682, 0xCAEA, 0xA683, 0xCAEB, 0xA684,
+	0xCAEC, 0xC2D5, 0xCAED, 0xA685, 0xCAEE, 0xA686, 0xCAEF, 0xA687,	0xCAF0, 0xA688, 0xCAF1, 0xA689, 0xCAF2, 0xA68A, 0xCAF3, 0xA68B,
+	0xCAF4, 0xC2D6, 0xCAF5, 0xA68C, 0xCAF6, 0xA68D, 0xCAF7, 0xA68E,	0xCAF8, 0xA68F, 0xCAF9, 0xA690, 0xCAFA, 0xA691, 0xCAFB, 0xA692,
+	0xCAFC, 0xA693, 0xCAFD, 0xA694, 0xCAFE, 0xA695, 0xCAFF, 0xA696,	0xCB00, 0xA697, 0xCB01, 0xA698, 0xCB02, 0xA699, 0xCB03, 0xA69A,
+	0xCB04, 0xA69B, 0xCB05, 0xA69C, 0xCB06, 0xA69D, 0xCB07, 0xA69E,	0xCB08, 0xC2D7, 0xCB09, 0xA69F, 0xCB0A, 0xA6A0, 0xCB0B, 0xA741,
+	0xCB0C, 0xA742, 0xCB0D, 0xA743, 0xCB0E, 0xA744, 0xCB0F, 0xA745,	0xCB10, 0xC2D8, 0xCB11, 0xA746, 0xCB12, 0xA747, 0xCB13, 0xA748,
+	0xCB14, 0xC2D9, 0xCB15, 0xA749, 0xCB16, 0xA74A, 0xCB17, 0xA74B,	0xCB18, 0xC2DA, 0xCB19, 0xA74C, 0xCB1A, 0xA74D, 0xCB1B, 0xA74E,
+	0xCB1C, 0xA74F, 0xCB1D, 0xA750, 0xCB1E, 0xA751, 0xCB1F, 0xA752,	0xCB20, 0xC2DB, 0xCB21, 0xC2DC, 0xCB22, 0xA753, 0xCB23, 0xA754,
+	0xCB24, 0xA755, 0xCB25, 0xA756, 0xCB26, 0xA757, 0xCB27, 0xA758,	0xCB28, 0xA759, 0xCB29, 0xA75A, 0xCB2A, 0xA761, 0xCB2B, 0xA762,
+	0xCB2C, 0xA763, 0xCB2D, 0xA764, 0xCB2E, 0xA765, 0xCB2F, 0xA766,	0xCB30, 0xA767, 0xCB31, 0xA768, 0xCB32, 0xA769, 0xCB33, 0xA76A,
+	0xCB34, 0xA76B, 0xCB35, 0xA76C, 0xCB36, 0xA76D, 0xCB37, 0xA76E,	0xCB38, 0xA76F, 0xCB39, 0xA770, 0xCB3A, 0xA771, 0xCB3B, 0xA772,
+	0xCB3C, 0xA773, 0xCB3D, 0xA774, 0xCB3E, 0xA775, 0xCB3F, 0xA776,	0xCB40, 0xA777, 0xCB41, 0xC2DD, 0xCB42, 0xA778, 0xCB43, 0xA779,
+	0xCB44, 0xA77A, 0xCB45, 0xA781, 0xCB46, 0xA782, 0xCB47, 0xA783,	0xCB48, 0xC2DE, 0xCB49, 0xC2DF, 0xCB4A, 0xA784, 0xCB4B, 0xA785,
+	0xCB4C, 0xC2E0, 0xCB4D, 0xA786, 0xCB4E, 0xA787, 0xCB4F, 0xA788,	0xCB50, 0xC2E1, 0xCB51, 0xA789, 0xCB52, 0xA78A, 0xCB53, 0xA78B,
+	0xCB54, 0xA78C, 0xCB55, 0xA78D, 0xCB56, 0xA78E, 0xCB57, 0xA78F,	0xCB58, 0xC2E2, 0xCB59, 0xC2E3, 0xCB5A, 0xA790, 0xCB5B, 0xA791,
+	0xCB5C, 0xA792, 0xCB5D, 0xC2E4, 0xCB5E, 0xA793, 0xCB5F, 0xA794,	0xCB60, 0xA795, 0xCB61, 0xA796, 0xCB62, 0xA797, 0xCB63, 0xA798,
+	0xCB64, 0xC2E5, 0xCB65, 0xA799, 0xCB66, 0xA79A, 0xCB67, 0xA79B,	0xCB68, 0xA79C, 0xCB69, 0xA79D, 0xCB6A, 0xA79E, 0xCB6B, 0xA79F,
+	0xCB6C, 0xA7A0, 0xCB6D, 0xA841, 0xCB6E, 0xA842, 0xCB6F, 0xA843,	0xCB70, 0xA844, 0xCB71, 0xA845, 0xCB72, 0xA846, 0xCB73, 0xA847,
+	0xCB74, 0xA848, 0xCB75, 0xA849, 0xCB76, 0xA84A, 0xCB77, 0xA84B,	0xCB78, 0xC2E6, 0xCB79, 0xC2E7, 0xCB7A, 0xA84C, 0xCB7B, 0xA84D,
+	0xCB7C, 0xA84E, 0xCB7D, 0xA84F, 0xCB7E, 0xA850, 0xCB7F, 0xA851,	0xCB80, 0xA852, 0xCB81, 0xA853, 0xCB82, 0xA854, 0xCB83, 0xA855,
+	0xCB84, 0xA856, 0xCB85, 0xA857, 0xCB86, 0xA858, 0xCB87, 0xA859,	0xCB88, 0xA85A, 0xCB89, 0xA861, 0xCB8A, 0xA862, 0xCB8B, 0xA863,
+	0xCB8C, 0xA864, 0xCB8D, 0xA865, 0xCB8E, 0xA866, 0xCB8F, 0xA867,	0xCB90, 0xA868, 0xCB91, 0xA869, 0xCB92, 0xA86A, 0xCB93, 0xA86B,
+	0xCB94, 0xA86C, 0xCB95, 0xA86D, 0xCB96, 0xA86E, 0xCB97, 0xA86F,	0xCB98, 0xA870, 0xCB99, 0xA871, 0xCB9A, 0xA872, 0xCB9B, 0xA873,
+	0xCB9C, 0xC2E8, 0xCB9D, 0xA874, 0xCB9E, 0xA875, 0xCB9F, 0xA876,	0xCBA0, 0xA877, 0xCBA1, 0xA878, 0xCBA2, 0xA879, 0xCBA3, 0xA87A,
+	0xCBA4, 0xA881, 0xCBA5, 0xA882, 0xCBA6, 0xA883, 0xCBA7, 0xA884,	0xCBA8, 0xA885, 0xCBA9, 0xA886, 0xCBAA, 0xA887, 0xCBAB, 0xA888,
+	0xCBAC, 0xA889, 0xCBAD, 0xA88A, 0xCBAE, 0xA88B, 0xCBAF, 0xA88C,	0xCBB0, 0xA88D, 0xCBB1, 0xA88E, 0xCBB2, 0xA88F, 0xCBB3, 0xA890,
+	0xCBB4, 0xA891, 0xCBB5, 0xA892, 0xCBB6, 0xA893, 0xCBB7, 0xA894,	0xCBB8, 0xC2E9, 0xCBB9, 0xA895, 0xCBBA, 0xA896, 0xCBBB, 0xA897,
+	0xCBBC, 0xA898, 0xCBBD, 0xA899, 0xCBBE, 0xA89A, 0xCBBF, 0xA89B,	0xCBC0, 0xA89C, 0xCBC1, 0xA89D, 0xCBC2, 0xA89E, 0xCBC3, 0xA89F,
+	0xCBC4, 0xA8A0, 0xCBC5, 0xA941, 0xCBC6, 0xA942, 0xCBC7, 0xA943,	0xCBC8, 0xA944, 0xCBC9, 0xA945, 0xCBCA, 0xA946, 0xCBCB, 0xA947,
+	0xCBCC, 0xA948, 0xCBCD, 0xA949, 0xCBCE, 0xA94A, 0xCBCF, 0xA94B,	0xCBD0, 0xA94C, 0xCBD1, 0xA94D, 0xCBD2, 0xA94E, 0xCBD3, 0xA94F,
+	0xCBD4, 0xC2EA, 0xCBD5, 0xA950, 0xCBD6, 0xA951, 0xCBD7, 0xA952,	0xCBD8, 0xA953, 0xCBD9, 0xA954, 0xCBDA, 0xA955, 0xCBDB, 0xA956,
+	0xCBDC, 0xA957, 0xCBDD, 0xA958, 0xCBDE, 0xA959, 0xCBDF, 0xA95A,	0xCBE0, 0xA961, 0xCBE1, 0xA962, 0xCBE2, 0xA963, 0xCBE3, 0xA964,
+	0xCBE4, 0xC2EB, 0xCBE5, 0xA965, 0xCBE6, 0xA966, 0xCBE7, 0xC2EC,	0xCBE8, 0xA967, 0xCBE9, 0xC2ED, 0xCBEA, 0xA968, 0xCBEB, 0xA969,
+	0xCBEC, 0xA96A, 0xCBED, 0xA96B, 0xCBEE, 0xA96C, 0xCBEF, 0xA96D,	0xCBF0, 0xA96E, 0xCBF1, 0xA96F, 0xCBF2, 0xA970, 0xCBF3, 0xA971,
+	0xCBF4, 0xA972, 0xCBF5, 0xA973, 0xCBF6, 0xA974, 0xCBF7, 0xA975,	0xCBF8, 0xA976, 0xCBF9, 0xA977, 0xCBFA, 0xA978, 0xCBFB, 0xA979,
+	0xCBFC, 0xA97A, 0xCBFD, 0xA981, 0xCBFE, 0xA982, 0xCBFF, 0xA983,	0xCC00, 0xA984, 0xCC01, 0xA985, 0xCC02, 0xA986, 0xCC03, 0xA987,
+	0xCC04, 0xA988, 0xCC05, 0xA989, 0xCC06, 0xA98A, 0xCC07, 0xA98B,	0xCC08, 0xA98C, 0xCC09, 0xA98D, 0xCC0A, 0xA98E, 0xCC0B, 0xA98F,
+	0xCC0C, 0xC2EE, 0xCC0D, 0xC2EF, 0xCC0E, 0xA990, 0xCC0F, 0xA991,	0xCC10, 0xC2F0, 0xCC11, 0xA992, 0xCC12, 0xA993, 0xCC13, 0xA994,
+	0xCC14, 0xC2F1, 0xCC15, 0xA995, 0xCC16, 0xA996, 0xCC17, 0xA997,	0xCC18, 0xA998, 0xCC19, 0xA999, 0xCC1A, 0xA99A, 0xCC1B, 0xA99B,
+	0xCC1C, 0xC2F2, 0xCC1D, 0xC2F3, 0xCC1E, 0xA99C, 0xCC1F, 0xA99D,	0xCC20, 0xA99E, 0xCC21, 0xC2F4, 0xCC22, 0xC2F5, 0xCC23, 0xA99F,
+	0xCC24, 0xA9A0, 0xCC25, 0xAA41, 0xCC26, 0xAA42, 0xCC27, 0xC2F6,	0xCC28, 0xC2F7, 0xCC29, 0xC2F8, 0xCC2A, 0xAA43, 0xCC2B, 0xAA44,
+	0xCC2C, 0xC2F9, 0xCC2D, 0xAA45, 0xCC2E, 0xC2FA, 0xCC2F, 0xAA46,	0xCC30, 0xC2FB, 0xCC31, 0xAA47, 0xCC32, 0xAA48, 0xCC33, 0xAA49,
+	0xCC34, 0xAA4A, 0xCC35, 0xAA4B, 0xCC36, 0xAA4C, 0xCC37, 0xAA4D,	0xCC38, 0xC2FC, 0xCC39, 0xC2FD, 0xCC3A, 0xAA4E, 0xCC3B, 0xC2FE,
+	0xCC3C, 0xC3A1, 0xCC3D, 0xC3A2, 0xCC3E, 0xC3A3, 0xCC3F, 0xAA4F,	0xCC40, 0xAA50, 0xCC41, 0xAA51, 0xCC42, 0xAA52, 0xCC43, 0xAA53,
+	0xCC44, 0xC3A4, 0xCC45, 0xC3A5, 0xCC46, 0xAA54, 0xCC47, 0xAA55,	0xCC48, 0xC3A6, 0xCC49, 0xAA56, 0xCC4A, 0xAA57, 0xCC4B, 0xAA58,
+	0xCC4C, 0xC3A7, 0xCC4D, 0xAA59, 0xCC4E, 0xAA5A, 0xCC4F, 0xAA61,	0xCC50, 0xAA62, 0xCC51, 0xAA63, 0xCC52, 0xAA64, 0xCC53, 0xAA65,
+	0xCC54, 0xC3A8, 0xCC55, 0xC3A9, 0xCC56, 0xAA66, 0xCC57, 0xC3AA,	0xCC58, 0xC3AB, 0xCC59, 0xC3AC, 0xCC5A, 0xAA67, 0xCC5B, 0xAA68,
+	0xCC5C, 0xAA69, 0xCC5D, 0xAA6A, 0xCC5E, 0xAA6B, 0xCC5F, 0xAA6C,	0xCC60, 0xC3AD, 0xCC61, 0xAA6D, 0xCC62, 0xAA6E, 0xCC63, 0xAA6F,
+	0xCC64, 0xC3AE, 0xCC65, 0xAA70, 0xCC66, 0xC3AF, 0xCC67, 0xAA71,	0xCC68, 0xC3B0, 0xCC69, 0xAA72, 0xCC6A, 0xAA73, 0xCC6B, 0xAA74,
+	0xCC6C, 0xAA75, 0xCC6D, 0xAA76, 0xCC6E, 0xAA77, 0xCC6F, 0xAA78,	0xCC70, 0xC3B1, 0xCC71, 0xAA79, 0xCC72, 0xAA7A, 0xCC73, 0xAA81,
+	0xCC74, 0xAA82, 0xCC75, 0xC3B2, 0xCC76, 0xAA83, 0xCC77, 0xAA84,	0xCC78, 0xAA85, 0xCC79, 0xAA86, 0xCC7A, 0xAA87, 0xCC7B, 0xAA88,
+	0xCC7C, 0xAA89, 0xCC7D, 0xAA8A, 0xCC7E, 0xAA8B, 0xCC7F, 0xAA8C,	0xCC80, 0xAA8D, 0xCC81, 0xAA8E, 0xCC82, 0xAA8F, 0xCC83, 0xAA90,
+	0xCC84, 0xAA91, 0xCC85, 0xAA92, 0xCC86, 0xAA93, 0xCC87, 0xAA94,	0xCC88, 0xAA95, 0xCC89, 0xAA96, 0xCC8A, 0xAA97, 0xCC8B, 0xAA98,
+	0xCC8C, 0xAA99, 0xCC8D, 0xAA9A, 0xCC8E, 0xAA9B, 0xCC8F, 0xAA9C,	0xCC90, 0xAA9D, 0xCC91, 0xAA9E, 0xCC92, 0xAA9F, 0xCC93, 0xAAA0,
+	0xCC94, 0xAB41, 0xCC95, 0xAB42, 0xCC96, 0xAB43, 0xCC97, 0xAB44,	0xCC98, 0xC3B3, 0xCC99, 0xC3B4, 0xCC9A, 0xAB45, 0xCC9B, 0xAB46,
+	0xCC9C, 0xC3B5, 0xCC9D, 0xAB47, 0xCC9E, 0xAB48, 0xCC9F, 0xAB49,	0xCCA0, 0xC3B6, 0xCCA1, 0xAB4A, 0xCCA2, 0xAB4B, 0xCCA3, 0xAB4C,
+	0xCCA4, 0xAB4D, 0xCCA5, 0xAB4E, 0xCCA6, 0xAB4F, 0xCCA7, 0xAB50,	0xCCA8, 0xC3B7, 0xCCA9, 0xC3B8, 0xCCAA, 0xAB51, 0xCCAB, 0xC3B9,
+	0xCCAC, 0xC3BA, 0xCCAD, 0xC3BB, 0xCCAE, 0xAB52, 0xCCAF, 0xAB53,	0xCCB0, 0xAB54, 0xCCB1, 0xAB55, 0xCCB2, 0xAB56, 0xCCB3, 0xAB57,
+	0xCCB4, 0xC3BC, 0xCCB5, 0xC3BD, 0xCCB6, 0xAB58, 0xCCB7, 0xAB59,	0xCCB8, 0xC3BE, 0xCCB9, 0xAB5A, 0xCCBA, 0xAB61, 0xCCBB, 0xAB62,
+	0xCCBC, 0xC3BF, 0xCCBD, 0xAB63, 0xCCBE, 0xAB64, 0xCCBF, 0xAB65,	0xCCC0, 0xAB66, 0xCCC1, 0xAB67, 0xCCC2, 0xAB68, 0xCCC3, 0xAB69,
+	0xCCC4, 0xC3C0, 0xCCC5, 0xC3C1, 0xCCC6, 0xAB6A, 0xCCC7, 0xC3C2,	0xCCC8, 0xAB6B, 0xCCC9, 0xC3C3, 0xCCCA, 0xAB6C, 0xCCCB, 0xAB6D,
+	0xCCCC, 0xAB6E, 0xCCCD, 0xAB6F, 0xCCCE, 0xAB70, 0xCCCF, 0xAB71,	0xCCD0, 0xC3C4, 0xCCD1, 0xAB72, 0xCCD2, 0xAB73, 0xCCD3, 0xAB74,
+	0xCCD4, 0xC3C5, 0xCCD5, 0xAB75, 0xCCD6, 0xAB76, 0xCCD7, 0xAB77,	0xCCD8, 0xAB78, 0xCCD9, 0xAB79, 0xCCDA, 0xAB7A, 0xCCDB, 0xAB81,
+	0xCCDC, 0xAB82, 0xCCDD, 0xAB83, 0xCCDE, 0xAB84, 0xCCDF, 0xAB85,	0xCCE0, 0xAB86, 0xCCE1, 0xAB87, 0xCCE2, 0xAB88, 0xCCE3, 0xAB89,
+	0xCCE4, 0xC3C6, 0xCCE5, 0xAB8A, 0xCCE6, 0xAB8B, 0xCCE7, 0xAB8C,	0xCCE8, 0xAB8D, 0xCCE9, 0xAB8E, 0xCCEA, 0xAB8F, 0xCCEB, 0xAB90,
+	0xCCEC, 0xC3C7, 0xCCED, 0xAB91, 0xCCEE, 0xAB92, 0xCCEF, 0xAB93,	0xCCF0, 0xC3C8, 0xCCF1, 0xAB94, 0xCCF2, 0xAB95, 0xCCF3, 0xAB96,
+	0xCCF4, 0xAB97, 0xCCF5, 0xAB98, 0xCCF6, 0xAB99, 0xCCF7, 0xAB9A,	0xCCF8, 0xAB9B, 0xCCF9, 0xAB9C, 0xCCFA, 0xAB9D, 0xCCFB, 0xAB9E,
+	0xCCFC, 0xAB9F, 0xCCFD, 0xABA0, 0xCCFE, 0xAC41, 0xCCFF, 0xAC42,	0xCD00, 0xAC43, 0xCD01, 0xC3C9, 0xCD02, 0xAC44, 0xCD03, 0xAC45,
+	0xCD04, 0xAC46, 0xCD05, 0xAC47, 0xCD06, 0xAC48, 0xCD07, 0xAC49,	0xCD08, 0xC3CA, 0xCD09, 0xC3CB, 0xCD0A, 0xAC4A, 0xCD0B, 0xAC4B,
+	0xCD0C, 0xC3CC, 0xCD0D, 0xAC4C, 0xCD0E, 0xAC4D, 0xCD0F, 0xAC4E,	0xCD10, 0xC3CD, 0xCD11, 0xAC4F, 0xCD12, 0xAC50, 0xCD13, 0xAC51,
+	0xCD14, 0xAC52, 0xCD15, 0xAC53, 0xCD16, 0xAC54, 0xCD17, 0xAC55,	0xCD18, 0xC3CE, 0xCD19, 0xC3CF, 0xCD1A, 0xAC56, 0xCD1B, 0xC3D0,
+	0xCD1C, 0xAC57, 0xCD1D, 0xC3D1, 0xCD1E, 0xAC58, 0xCD1F, 0xAC59,	0xCD20, 0xAC5A, 0xCD21, 0xAC61, 0xCD22, 0xAC62, 0xCD23, 0xAC63,
+	0xCD24, 0xC3D2, 0xCD25, 0xAC64, 0xCD26, 0xAC65, 0xCD27, 0xAC66,	0xCD28, 0xC3D3, 0xCD29, 0xAC67, 0xCD2A, 0xAC68, 0xCD2B, 0xAC69,
+	0xCD2C, 0xC3D4, 0xCD2D, 0xAC6A, 0xCD2E, 0xAC6B, 0xCD2F, 0xAC6C,	0xCD30, 0xAC6D, 0xCD31, 0xAC6E, 0xCD32, 0xAC6F, 0xCD33, 0xAC70,
+	0xCD34, 0xAC71, 0xCD35, 0xAC72, 0xCD36, 0xAC73, 0xCD37, 0xAC74,	0xCD38, 0xAC75, 0xCD39, 0xC3D5, 0xCD3A, 0xAC76, 0xCD3B, 0xAC77,
+	0xCD3C, 0xAC78, 0xCD3D, 0xAC79, 0xCD3E, 0xAC7A, 0xCD3F, 0xAC81,	0xCD40, 0xAC82, 0xCD41, 0xAC83, 0xCD42, 0xAC84, 0xCD43, 0xAC85,
+	0xCD44, 0xAC86, 0xCD45, 0xAC87, 0xCD46, 0xAC88, 0xCD47, 0xAC89,	0xCD48, 0xAC8A, 0xCD49, 0xAC8B, 0xCD4A, 0xAC8C, 0xCD4B, 0xAC8D,
+	0xCD4C, 0xAC8E, 0xCD4D, 0xAC8F, 0xCD4E, 0xAC90, 0xCD4F, 0xAC91,	0xCD50, 0xAC92, 0xCD51, 0xAC93, 0xCD52, 0xAC94, 0xCD53, 0xAC95,
+	0xCD54, 0xAC96, 0xCD55, 0xAC97, 0xCD56, 0xAC98, 0xCD57, 0xAC99,	0xCD58, 0xAC9A, 0xCD59, 0xAC9B, 0xCD5A, 0xAC9C, 0xCD5B, 0xAC9D,
+	0xCD5C, 0xC3D6, 0xCD5D, 0xAC9E, 0xCD5E, 0xAC9F, 0xCD5F, 0xACA0,	0xCD60, 0xC3D7, 0xCD61, 0xAD41, 0xCD62, 0xAD42, 0xCD63, 0xAD43,
+	0xCD64, 0xC3D8, 0xCD65, 0xAD44, 0xCD66, 0xAD45, 0xCD67, 0xAD46,	0xCD68, 0xAD47, 0xCD69, 0xAD48, 0xCD6A, 0xAD49, 0xCD6B, 0xAD4A,
+	0xCD6C, 0xC3D9, 0xCD6D, 0xC3DA, 0xCD6E, 0xAD4B, 0xCD6F, 0xC3DB,	0xCD70, 0xAD4C, 0xCD71, 0xC3DC, 0xCD72, 0xAD4D, 0xCD73, 0xAD4E,
+	0xCD74, 0xAD4F, 0xCD75, 0xAD50, 0xCD76, 0xAD51, 0xCD77, 0xAD52,	0xCD78, 0xC3DD, 0xCD79, 0xAD53, 0xCD7A, 0xAD54, 0xCD7B, 0xAD55,
+	0xCD7C, 0xAD56, 0xCD7D, 0xAD57, 0xCD7E, 0xAD58, 0xCD7F, 0xAD59,	0xCD80, 0xAD5A, 0xCD81, 0xAD61, 0xCD82, 0xAD62, 0xCD83, 0xAD63,
+	0xCD84, 0xAD64, 0xCD85, 0xAD65, 0xCD86, 0xAD66, 0xCD87, 0xAD67,	0xCD88, 0xC3DE, 0xCD89, 0xAD68, 0xCD8A, 0xAD69, 0xCD8B, 0xAD6A,
+	0xCD8C, 0xAD6B, 0xCD8D, 0xAD6C, 0xCD8E, 0xAD6D, 0xCD8F, 0xAD6E,	0xCD90, 0xAD6F, 0xCD91, 0xAD70, 0xCD92, 0xAD71, 0xCD93, 0xAD72,
+	0xCD94, 0xC3DF, 0xCD95, 0xC3E0, 0xCD96, 0xAD73, 0xCD97, 0xAD74,	0xCD98, 0xC3E1, 0xCD99, 0xAD75, 0xCD9A, 0xAD76, 0xCD9B, 0xAD77,
+	0xCD9C, 0xC3E2, 0xCD9D, 0xAD78, 0xCD9E, 0xAD79, 0xCD9F, 0xAD7A,	0xCDA0, 0xAD81, 0xCDA1, 0xAD82, 0xCDA2, 0xAD83, 0xCDA3, 0xAD84,
+	0xCDA4, 0xC3E3, 0xCDA5, 0xC3E4, 0xCDA6, 0xAD85, 0xCDA7, 0xC3E5,	0xCDA8, 0xAD86, 0xCDA9, 0xC3E6, 0xCDAA, 0xAD87, 0xCDAB, 0xAD88,
+	0xCDAC, 0xAD89, 0xCDAD, 0xAD8A, 0xCDAE, 0xAD8B, 0xCDAF, 0xAD8C,	0xCDB0, 0xC3E7, 0xCDB1, 0xAD8D, 0xCDB2, 0xAD8E, 0xCDB3, 0xAD8F,
+	0xCDB4, 0xAD90, 0xCDB5, 0xAD91, 0xCDB6, 0xAD92, 0xCDB7, 0xAD93,	0xCDB8, 0xAD94, 0xCDB9, 0xAD95, 0xCDBA, 0xAD96, 0xCDBB, 0xAD97,
+	0xCDBC, 0xAD98, 0xCDBD, 0xAD99, 0xCDBE, 0xAD9A, 0xCDBF, 0xAD9B,	0xCDC0, 0xAD9C, 0xCDC1, 0xAD9D, 0xCDC2, 0xAD9E, 0xCDC3, 0xAD9F,
+	0xCDC4, 0xC3E8, 0xCDC5, 0xADA0, 0xCDC6, 0xAE41, 0xCDC7, 0xAE42,	0xCDC8, 0xAE43, 0xCDC9, 0xAE44, 0xCDCA, 0xAE45, 0xCDCB, 0xAE46,
+	0xCDCC, 0xC3E9, 0xCDCD, 0xAE47, 0xCDCE, 0xAE48, 0xCDCF, 0xAE49,	0xCDD0, 0xC3EA, 0xCDD1, 0xAE4A, 0xCDD2, 0xAE4B, 0xCDD3, 0xAE4C,
+	0xCDD4, 0xAE4D, 0xCDD5, 0xAE4E, 0xCDD6, 0xAE4F, 0xCDD7, 0xAE50,	0xCDD8, 0xAE51, 0xCDD9, 0xAE52, 0xCDDA, 0xAE53, 0xCDDB, 0xAE54,
+	0xCDDC, 0xAE55, 0xCDDD, 0xAE56, 0xCDDE, 0xAE57, 0xCDDF, 0xAE58,	0xCDE0, 0xAE59, 0xCDE1, 0xAE5A, 0xCDE2, 0xAE61, 0xCDE3, 0xAE62,
+	0xCDE4, 0xAE63, 0xCDE5, 0xAE64, 0xCDE6, 0xAE65, 0xCDE7, 0xAE66,	0xCDE8, 0xC3EB, 0xCDE9, 0xAE67, 0xCDEA, 0xAE68, 0xCDEB, 0xAE69,
+	0xCDEC, 0xC3EC, 0xCDED, 0xAE6A, 0xCDEE, 0xAE6B, 0xCDEF, 0xAE6C,	0xCDF0, 0xC3ED, 0xCDF1, 0xAE6D, 0xCDF2, 0xAE6E, 0xCDF3, 0xAE6F,
+	0xCDF4, 0xAE70, 0xCDF5, 0xAE71, 0xCDF6, 0xAE72, 0xCDF7, 0xAE73,	0xCDF8, 0xC3EE, 0xCDF9, 0xC3EF, 0xCDFA, 0xAE74, 0xCDFB, 0xC3F0,
+	0xCDFC, 0xAE75, 0xCDFD, 0xC3F1, 0xCDFE, 0xAE76, 0xCDFF, 0xAE77,	0xCE00, 0xAE78, 0xCE01, 0xAE79, 0xCE02, 0xAE7A, 0xCE03, 0xAE81,
+	0xCE04, 0xC3F2, 0xCE05, 0xAE82, 0xCE06, 0xAE83, 0xCE07, 0xAE84,	0xCE08, 0xC3F3, 0xCE09, 0xAE85, 0xCE0A, 0xAE86, 0xCE0B, 0xAE87,
+	0xCE0C, 0xC3F4, 0xCE0D, 0xAE88, 0xCE0E, 0xAE89, 0xCE0F, 0xAE8A,	0xCE10, 0xAE8B, 0xCE11, 0xAE8C, 0xCE12, 0xAE8D, 0xCE13, 0xAE8E,
+	0xCE14, 0xC3F5, 0xCE15, 0xAE8F, 0xCE16, 0xAE90, 0xCE17, 0xAE91,	0xCE18, 0xAE92, 0xCE19, 0xC3F6, 0xCE1A, 0xAE93, 0xCE1B, 0xAE94,
+	0xCE1C, 0xAE95, 0xCE1D, 0xAE96, 0xCE1E, 0xAE97, 0xCE1F, 0xAE98,	0xCE20, 0xC3F7, 0xCE21, 0xC3F8, 0xCE22, 0xAE99, 0xCE23, 0xAE9A,
+	0xCE24, 0xC3F9, 0xCE25, 0xAE9B, 0xCE26, 0xAE9C, 0xCE27, 0xAE9D,	0xCE28, 0xC3FA, 0xCE29, 0xAE9E, 0xCE2A, 0xAE9F, 0xCE2B, 0xAEA0,
+	0xCE2C, 0xAF41, 0xCE2D, 0xAF42, 0xCE2E, 0xAF43, 0xCE2F, 0xAF44,	0xCE30, 0xC3FB, 0xCE31, 0xC3FC, 0xCE32, 0xAF45, 0xCE33, 0xC3FD,
+	0xCE34, 0xAF46, 0xCE35, 0xC3FE, 0xCE36, 0xAF47, 0xCE37, 0xAF48,	0xCE38, 0xAF49, 0xCE39, 0xAF4A, 0xCE3A, 0xAF4B, 0xCE3B, 0xAF4C,
+	0xCE3C, 0xAF4D, 0xCE3D, 0xAF4E, 0xCE3E, 0xAF4F, 0xCE3F, 0xAF50,	0xCE40, 0xAF51, 0xCE41, 0xAF52, 0xCE42, 0xAF53, 0xCE43, 0xAF54,
+	0xCE44, 0xAF55, 0xCE45, 0xAF56, 0xCE46, 0xAF57, 0xCE47, 0xAF58,	0xCE48, 0xAF59, 0xCE49, 0xAF5A, 0xCE4A, 0xAF61, 0xCE4B, 0xAF62,
+	0xCE4C, 0xAF63, 0xCE4D, 0xAF64, 0xCE4E, 0xAF65, 0xCE4F, 0xAF66,	0xCE50, 0xAF67, 0xCE51, 0xAF68, 0xCE52, 0xAF69, 0xCE53, 0xAF6A,
+	0xCE54, 0xAF6B, 0xCE55, 0xAF6C, 0xCE56, 0xAF6D, 0xCE57, 0xAF6E,	0xCE58, 0xC4A1, 0xCE59, 0xC4A2, 0xCE5A, 0xAF6F, 0xCE5B, 0xAF70,
+	0xCE5C, 0xC4A3, 0xCE5D, 0xAF71, 0xCE5E, 0xAF72, 0xCE5F, 0xC4A4,	0xCE60, 0xC4A5, 0xCE61, 0xC4A6, 0xCE62, 0xAF73, 0xCE63, 0xAF74,
+	0xCE64, 0xAF75, 0xCE65, 0xAF76, 0xCE66, 0xAF77, 0xCE67, 0xAF78,	0xCE68, 0xC4A7, 0xCE69, 0xC4A8, 0xCE6A, 0xAF79, 0xCE6B, 0xC4A9,
+	0xCE6C, 0xAF7A, 0xCE6D, 0xC4AA, 0xCE6E, 0xAF81, 0xCE6F, 0xAF82,	0xCE70, 0xAF83, 0xCE71, 0xAF84, 0xCE72, 0xAF85, 0xCE73, 0xAF86,
+	0xCE74, 0xC4AB, 0xCE75, 0xC4AC, 0xCE76, 0xAF87, 0xCE77, 0xAF88,	0xCE78, 0xC4AD, 0xCE79, 0xAF89, 0xCE7A, 0xAF8A, 0xCE7B, 0xAF8B,
+	0xCE7C, 0xC4AE, 0xCE7D, 0xAF8C, 0xCE7E, 0xAF8D, 0xCE7F, 0xAF8E,	0xCE80, 0xAF8F, 0xCE81, 0xAF90, 0xCE82, 0xAF91, 0xCE83, 0xAF92,
+	0xCE84, 0xC4AF, 0xCE85, 0xC4B0, 0xCE86, 0xAF93, 0xCE87, 0xC4B1,	0xCE88, 0xAF94, 0xCE89, 0xC4B2, 0xCE8A, 0xAF95, 0xCE8B, 0xAF96,
+	0xCE8C, 0xAF97, 0xCE8D, 0xAF98, 0xCE8E, 0xAF99, 0xCE8F, 0xAF9A,	0xCE90, 0xC4B3, 0xCE91, 0xC4B4, 0xCE92, 0xAF9B, 0xCE93, 0xAF9C,
+	0xCE94, 0xC4B5, 0xCE95, 0xAF9D, 0xCE96, 0xAF9E, 0xCE97, 0xAF9F,	0xCE98, 0xC4B6, 0xCE99, 0xAFA0, 0xCE9A, 0xB041, 0xCE9B, 0xB042,
+	0xCE9C, 0xB043, 0xCE9D, 0xB044, 0xCE9E, 0xB045, 0xCE9F, 0xB046,	0xCEA0, 0xC4B7, 0xCEA1, 0xC4B8, 0xCEA2, 0xB047, 0xCEA3, 0xC4B9,
+	0xCEA4, 0xC4BA, 0xCEA5, 0xC4BB, 0xCEA6, 0xB048, 0xCEA7, 0xB049,	0xCEA8, 0xB04A, 0xCEA9, 0xB04B, 0xCEAA, 0xB04C, 0xCEAB, 0xB04D,
+	0xCEAC, 0xC4BC, 0xCEAD, 0xC4BD, 0xCEAE, 0xB04E, 0xCEAF, 0xB04F,	0xCEB0, 0xB050, 0xCEB1, 0xB051, 0xCEB2, 0xB052, 0xCEB3, 0xB053,
+	0xCEB4, 0xB054, 0xCEB5, 0xB055, 0xCEB6, 0xB056, 0xCEB7, 0xB057,	0xCEB8, 0xB058, 0xCEB9, 0xB059, 0xCEBA, 0xB05A, 0xCEBB, 0xB061,
+	0xCEBC, 0xB062, 0xCEBD, 0xB063, 0xCEBE, 0xB064, 0xCEBF, 0xB065,	0xCEC0, 0xB066, 0xCEC1, 0xC4BE, 0xCEC2, 0xB067, 0xCEC3, 0xB068,
+	0xCEC4, 0xB069, 0xCEC5, 0xB06A, 0xCEC6, 0xB06B, 0xCEC7, 0xB06C,	0xCEC8, 0xB06D, 0xCEC9, 0xB06E, 0xCECA, 0xB06F, 0xCECB, 0xB070,
+	0xCECC, 0xB071, 0xCECD, 0xB072, 0xCECE, 0xB073, 0xCECF, 0xB074,	0xCED0, 0xB075, 0xCED1, 0xB076, 0xCED2, 0xB077, 0xCED3, 0xB078,
+	0xCED4, 0xB079, 0xCED5, 0xB07A, 0xCED6, 0xB081, 0xCED7, 0xB082,	0xCED8, 0xB083, 0xCED9, 0xB084, 0xCEDA, 0xB085, 0xCEDB, 0xB086,
+	0xCEDC, 0xB087, 0xCEDD, 0xB088, 0xCEDE, 0xB089, 0xCEDF, 0xB08A,	0xCEE0, 0xB08B, 0xCEE1, 0xB08C, 0xCEE2, 0xB08D, 0xCEE3, 0xB08E,
+	0xCEE4, 0xC4BF, 0xCEE5, 0xC4C0, 0xCEE6, 0xB08F, 0xCEE7, 0xB090,	0xCEE8, 0xC4C1, 0xCEE9, 0xB091, 0xCEEA, 0xB092, 0xCEEB, 0xC4C2,
+	0xCEEC, 0xC4C3, 0xCEED, 0xB093, 0xCEEE, 0xB094, 0xCEEF, 0xB095,	0xCEF0, 0xB096, 0xCEF1, 0xB097, 0xCEF2, 0xB098, 0xCEF3, 0xB099,
+	0xCEF4, 0xC4C4, 0xCEF5, 0xC4C5, 0xCEF6, 0xB09A, 0xCEF7, 0xC4C6,	0xCEF8, 0xC4C7, 0xCEF9, 0xC4C8, 0xCEFA, 0xB09B, 0xCEFB, 0xB09C,
+	0xCEFC, 0xB09D, 0xCEFD, 0xB09E, 0xCEFE, 0xB09F, 0xCEFF, 0xB0A0,	0xCF00, 0xC4C9, 0xCF01, 0xC4CA, 0xCF02, 0xB141, 0xCF03, 0xB142,
+	0xCF04, 0xC4CB, 0xCF05, 0xB143, 0xCF06, 0xB144, 0xCF07, 0xB145,	0xCF08, 0xC4CC, 0xCF09, 0xB146, 0xCF0A, 0xB147, 0xCF0B, 0xB148,
+	0xCF0C, 0xB149, 0xCF0D, 0xB14A, 0xCF0E, 0xB14B, 0xCF0F, 0xB14C,	0xCF10, 0xC4CD, 0xCF11, 0xC4CE, 0xCF12, 0xB14D, 0xCF13, 0xC4CF,
+	0xCF14, 0xB14E, 0xCF15, 0xC4D0, 0xCF16, 0xB14F, 0xCF17, 0xB150,	0xCF18, 0xB151, 0xCF19, 0xB152, 0xCF1A, 0xB153, 0xCF1B, 0xB154,
+	0xCF1C, 0xC4D1, 0xCF1D, 0xB155, 0xCF1E, 0xB156, 0xCF1F, 0xB157,	0xCF20, 0xC4D2, 0xCF21, 0xB158, 0xCF22, 0xB159, 0xCF23, 0xB15A,
+	0xCF24, 0xC4D3, 0xCF25, 0xB161, 0xCF26, 0xB162, 0xCF27, 0xB163,	0xCF28, 0xB164, 0xCF29, 0xB165, 0xCF2A, 0xB166, 0xCF2B, 0xB167,
+	0xCF2C, 0xC4D4, 0xCF2D, 0xC4D5, 0xCF2E, 0xB168, 0xCF2F, 0xC4D6,	0xCF30, 0xC4D7, 0xCF31, 0xC4D8, 0xCF32, 0xB169, 0xCF33, 0xB16A,
+	0xCF34, 0xB16B, 0xCF35, 0xB16C, 0xCF36, 0xB16D, 0xCF37, 0xB16E,	0xCF38, 0xC4D9, 0xCF39, 0xB16F, 0xCF3A, 0xB170, 0xCF3B, 0xB171,
+	0xCF3C, 0xB172, 0xCF3D, 0xB173, 0xCF3E, 0xB174, 0xCF3F, 0xB175,	0xCF40, 0xB176, 0xCF41, 0xB177, 0xCF42, 0xB178, 0xCF43, 0xB179,
+	0xCF44, 0xB17A, 0xCF45, 0xB181, 0xCF46, 0xB182, 0xCF47, 0xB183,	0xCF48, 0xB184, 0xCF49, 0xB185, 0xCF4A, 0xB186, 0xCF4B, 0xB187,
+	0xCF4C, 0xB188, 0xCF4D, 0xB189, 0xCF4E, 0xB18A, 0xCF4F, 0xB18B,	0xCF50, 0xB18C, 0xCF51, 0xB18D, 0xCF52, 0xB18E, 0xCF53, 0xB18F,
+	0xCF54, 0xC4DA, 0xCF55, 0xC4DB, 0xCF56, 0xB190, 0xCF57, 0xB191,	0xCF58, 0xC4DC, 0xCF59, 0xB192, 0xCF5A, 0xB193, 0xCF5B, 0xB194,
+	0xCF5C, 0xC4DD, 0xCF5D, 0xB195, 0xCF5E, 0xB196, 0xCF5F, 0xB197,	0xCF60, 0xB198, 0xCF61, 0xB199, 0xCF62, 0xB19A, 0xCF63, 0xB19B,
+	0xCF64, 0xC4DE, 0xCF65, 0xC4DF, 0xCF66, 0xB19C, 0xCF67, 0xC4E0,	0xCF68, 0xB19D, 0xCF69, 0xC4E1, 0xCF6A, 0xB19E, 0xCF6B, 0xB19F,
+	0xCF6C, 0xB1A0, 0xCF6D, 0xB241, 0xCF6E, 0xB242, 0xCF6F, 0xB243,	0xCF70, 0xC4E2, 0xCF71, 0xC4E3, 0xCF72, 0xB244, 0xCF73, 0xB245,
+	0xCF74, 0xC4E4, 0xCF75, 0xB246, 0xCF76, 0xB247, 0xCF77, 0xB248,	0xCF78, 0xC4E5, 0xCF79, 0xB249, 0xCF7A, 0xB24A, 0xCF7B, 0xB24B,
+	0xCF7C, 0xB24C, 0xCF7D, 0xB24D, 0xCF7E, 0xB24E, 0xCF7F, 0xB24F,	0xCF80, 0xC4E6, 0xCF81, 0xB250, 0xCF82, 0xB251, 0xCF83, 0xB252,
+	0xCF84, 0xB253, 0xCF85, 0xC4E7, 0xCF86, 0xB254, 0xCF87, 0xB255,	0xCF88, 0xB256, 0xCF89, 0xB257, 0xCF8A, 0xB258, 0xCF8B, 0xB259,
+	0xCF8C, 0xC4E8, 0xCF8D, 0xB25A, 0xCF8E, 0xB261, 0xCF8F, 0xB262,	0xCF90, 0xB263, 0xCF91, 0xB264, 0xCF92, 0xB265, 0xCF93, 0xB266,
+	0xCF94, 0xB267, 0xCF95, 0xB268, 0xCF96, 0xB269, 0xCF97, 0xB26A,	0xCF98, 0xB26B, 0xCF99, 0xB26C, 0xCF9A, 0xB26D, 0xCF9B, 0xB26E,
+	0xCF9C, 0xB26F, 0xCF9D, 0xB270, 0xCF9E, 0xB271, 0xCF9F, 0xB272,	0xCFA0, 0xB273, 0xCFA1, 0xC4E9, 0xCFA2, 0xB274, 0xCFA3, 0xB275,
+	0xCFA4, 0xB276, 0xCFA5, 0xB277, 0xCFA6, 0xB278, 0xCFA7, 0xB279,	0xCFA8, 0xC4EA, 0xCFA9, 0xB27A, 0xCFAA, 0xB281, 0xCFAB, 0xB282,
+	0xCFAC, 0xB283, 0xCFAD, 0xB284, 0xCFAE, 0xB285, 0xCFAF, 0xB286,	0xCFB0, 0xC4EB, 0xCFB1, 0xB287, 0xCFB2, 0xB288, 0xCFB3, 0xB289,
+	0xCFB4, 0xB28A, 0xCFB5, 0xB28B, 0xCFB6, 0xB28C, 0xCFB7, 0xB28D,	0xCFB8, 0xB28E, 0xCFB9, 0xB28F, 0xCFBA, 0xB290, 0xCFBB, 0xB291,
+	0xCFBC, 0xB292, 0xCFBD, 0xB293, 0xCFBE, 0xB294, 0xCFBF, 0xB295,	0xCFC0, 0xB296, 0xCFC1, 0xB297, 0xCFC2, 0xB298, 0xCFC3, 0xB299,
+	0xCFC4, 0xC4EC, 0xCFC5, 0xB29A, 0xCFC6, 0xB29B, 0xCFC7, 0xB29C,	0xCFC8, 0xB29D, 0xCFC9, 0xB29E, 0xCFCA, 0xB29F, 0xCFCB, 0xB2A0,
+	0xCFCC, 0xB341, 0xCFCD, 0xB342, 0xCFCE, 0xB343, 0xCFCF, 0xB344,	0xCFD0, 0xB345, 0xCFD1, 0xB346, 0xCFD2, 0xB347, 0xCFD3, 0xB348,
+	0xCFD4, 0xB349, 0xCFD5, 0xB34A, 0xCFD6, 0xB34B, 0xCFD7, 0xB34C,	0xCFD8, 0xB34D, 0xCFD9, 0xB34E, 0xCFDA, 0xB34F, 0xCFDB, 0xB350,
+	0xCFDC, 0xB351, 0xCFDD, 0xB352, 0xCFDE, 0xB353, 0xCFDF, 0xB354,	0xCFE0, 0xC4ED, 0xCFE1, 0xC4EE, 0xCFE2, 0xB355, 0xCFE3, 0xB356,
+	0xCFE4, 0xC4EF, 0xCFE5, 0xB357, 0xCFE6, 0xB358, 0xCFE7, 0xB359,	0xCFE8, 0xC4F0, 0xCFE9, 0xB35A, 0xCFEA, 0xB361, 0xCFEB, 0xB362,
+	0xCFEC, 0xB363, 0xCFED, 0xB364, 0xCFEE, 0xB365, 0xCFEF, 0xB366,	0xCFF0, 0xC4F1, 0xCFF1, 0xC4F2, 0xCFF2, 0xB367, 0xCFF3, 0xC4F3,
+	0xCFF4, 0xB368, 0xCFF5, 0xC4F4, 0xCFF6, 0xB369, 0xCFF7, 0xB36A,	0xCFF8, 0xB36B, 0xCFF9, 0xB36C, 0xCFFA, 0xB36D, 0xCFFB, 0xB36E,
+	0xCFFC, 0xC4F5, 0xCFFD, 0xB36F, 0xCFFE, 0xB370, 0xCFFF, 0xB371,	0xD000, 0xC4F6, 0xD001, 0xB372, 0xD002, 0xB373, 0xD003, 0xB374,
+	0xD004, 0xC4F7, 0xD005, 0xB375, 0xD006, 0xB376, 0xD007, 0xB377,	0xD008, 0xB378, 0xD009, 0xB379, 0xD00A, 0xB37A, 0xD00B, 0xB381,
+	0xD00C, 0xB382, 0xD00D, 0xB383, 0xD00E, 0xB384, 0xD00F, 0xB385,	0xD010, 0xB386, 0xD011, 0xC4F8, 0xD012, 0xB387, 0xD013, 0xB388,
+	0xD014, 0xB389, 0xD015, 0xB38A, 0xD016, 0xB38B, 0xD017, 0xB38C,	0xD018, 0xC4F9, 0xD019, 0xB38D, 0xD01A, 0xB38E, 0xD01B, 0xB38F,
+	0xD01C, 0xB390, 0xD01D, 0xB391, 0xD01E, 0xB392, 0xD01F, 0xB393,	0xD020, 0xB394, 0xD021, 0xB395, 0xD022, 0xB396, 0xD023, 0xB397,
+	0xD024, 0xB398, 0xD025, 0xB399, 0xD026, 0xB39A, 0xD027, 0xB39B,	0xD028, 0xB39C, 0xD029, 0xB39D, 0xD02A, 0xB39E, 0xD02B, 0xB39F,
+	0xD02C, 0xB3A0, 0xD02D, 0xC4FA, 0xD02E, 0xB441, 0xD02F, 0xB442,	0xD030, 0xB443, 0xD031, 0xB444, 0xD032, 0xB445, 0xD033, 0xB446,
+	0xD034, 0xC4FB, 0xD035, 0xC4FC, 0xD036, 0xB447, 0xD037, 0xB448,	0xD038, 0xC4FD, 0xD039, 0xB449, 0xD03A, 0xB44A, 0xD03B, 0xB44B,
+	0xD03C, 0xC4FE, 0xD03D, 0xB44C, 0xD03E, 0xB44D, 0xD03F, 0xB44E,	0xD040, 0xB44F, 0xD041, 0xB450, 0xD042, 0xB451, 0xD043, 0xB452,
+	0xD044, 0xC5A1, 0xD045, 0xC5A2, 0xD046, 0xB453, 0xD047, 0xC5A3,	0xD048, 0xB454, 0xD049, 0xC5A4, 0xD04A, 0xB455, 0xD04B, 0xB456,
+	0xD04C, 0xB457, 0xD04D, 0xB458, 0xD04E, 0xB459, 0xD04F, 0xB45A,	0xD050, 0xC5A5, 0xD051, 0xB461, 0xD052, 0xB462, 0xD053, 0xB463,
+	0xD054, 0xC5A6, 0xD055, 0xB464, 0xD056, 0xB465, 0xD057, 0xB466,	0xD058, 0xC5A7, 0xD059, 0xB467, 0xD05A, 0xB468, 0xD05B, 0xB469,
+	0xD05C, 0xB46A, 0xD05D, 0xB46B, 0xD05E, 0xB46C, 0xD05F, 0xB46D,	0xD060, 0xC5A8, 0xD061, 0xB46E, 0xD062, 0xB46F, 0xD063, 0xB470,
+	0xD064, 0xB471, 0xD065, 0xB472, 0xD066, 0xB473, 0xD067, 0xB474,	0xD068, 0xB475, 0xD069, 0xB476, 0xD06A, 0xB477, 0xD06B, 0xB478,
+	0xD06C, 0xC5A9, 0xD06D, 0xC5AA, 0xD06E, 0xB479, 0xD06F, 0xB47A,	0xD070, 0xC5AB, 0xD071, 0xB481, 0xD072, 0xB482, 0xD073, 0xB483,
+	0xD074, 0xC5AC, 0xD075, 0xB484, 0xD076, 0xB485, 0xD077, 0xB486,	0xD078, 0xB487, 0xD079, 0xB488, 0xD07A, 0xB489, 0xD07B, 0xB48A,
+	0xD07C, 0xC5AD, 0xD07D, 0xC5AE, 0xD07E, 0xB48B, 0xD07F, 0xB48C,	0xD080, 0xB48D, 0xD081, 0xC5AF, 0xD082, 0xB48E, 0xD083, 0xB48F,
+	0xD084, 0xB490, 0xD085, 0xB491, 0xD086, 0xB492, 0xD087, 0xB493,	0xD088, 0xB494, 0xD089, 0xB495, 0xD08A, 0xB496, 0xD08B, 0xB497,
+	0xD08C, 0xB498, 0xD08D, 0xB499, 0xD08E, 0xB49A, 0xD08F, 0xB49B,	0xD090, 0xB49C, 0xD091, 0xB49D, 0xD092, 0xB49E, 0xD093, 0xB49F,
+	0xD094, 0xB4A0, 0xD095, 0xB541, 0xD096, 0xB542, 0xD097, 0xB543,	0xD098, 0xB544, 0xD099, 0xB545, 0xD09A, 0xB546, 0xD09B, 0xB547,
+	0xD09C, 0xB548, 0xD09D, 0xB549, 0xD09E, 0xB54A, 0xD09F, 0xB54B,	0xD0A0, 0xB54C, 0xD0A1, 0xB54D, 0xD0A2, 0xB54E, 0xD0A3, 0xB54F,
+	0xD0A4, 0xC5B0, 0xD0A5, 0xC5B1, 0xD0A6, 0xB550, 0xD0A7, 0xB551,	0xD0A8, 0xC5B2, 0xD0A9, 0xB552, 0xD0AA, 0xB553, 0xD0AB, 0xB554,
+	0xD0AC, 0xC5B3, 0xD0AD, 0xB555, 0xD0AE, 0xB556, 0xD0AF, 0xB557,	0xD0B0, 0xB558, 0xD0B1, 0xB559, 0xD0B2, 0xB55A, 0xD0B3, 0xB561,
+	0xD0B4, 0xC5B4, 0xD0B5, 0xC5B5, 0xD0B6, 0xB562, 0xD0B7, 0xC5B6,	0xD0B8, 0xB563, 0xD0B9, 0xC5B7, 0xD0BA, 0xB564, 0xD0BB, 0xB565,
+	0xD0BC, 0xB566, 0xD0BD, 0xB567, 0xD0BE, 0xB568, 0xD0BF, 0xB569,	0xD0C0, 0xC5B8, 0xD0C1, 0xC5B9, 0xD0C2, 0xB56A, 0xD0C3, 0xB56B,
+	0xD0C4, 0xC5BA, 0xD0C5, 0xB56C, 0xD0C6, 0xB56D, 0xD0C7, 0xB56E,	0xD0C8, 0xC5BB, 0xD0C9, 0xC5BC, 0xD0CA, 0xB56F, 0xD0CB, 0xB570,
+	0xD0CC, 0xB571, 0xD0CD, 0xB572, 0xD0CE, 0xB573, 0xD0CF, 0xB574,	0xD0D0, 0xC5BD, 0xD0D1, 0xC5BE, 0xD0D2, 0xB575, 0xD0D3, 0xC5BF,
+	0xD0D4, 0xC5C0, 0xD0D5, 0xC5C1, 0xD0D6, 0xB576, 0xD0D7, 0xB577,	0xD0D8, 0xB578, 0xD0D9, 0xB579, 0xD0DA, 0xB57A, 0xD0DB, 0xB581,
+	0xD0DC, 0xC5C2, 0xD0DD, 0xC5C3, 0xD0DE, 0xB582, 0xD0DF, 0xB583,	0xD0E0, 0xC5C4, 0xD0E1, 0xB584, 0xD0E2, 0xB585, 0xD0E3, 0xB586,
+	0xD0E4, 0xC5C5, 0xD0E5, 0xB587, 0xD0E6, 0xB588, 0xD0E7, 0xB589,	0xD0E8, 0xB58A, 0xD0E9, 0xB58B, 0xD0EA, 0xB58C, 0xD0EB, 0xB58D,
+	0xD0EC, 0xC5C6, 0xD0ED, 0xC5C7, 0xD0EE, 0xB58E, 0xD0EF, 0xC5C8,	0xD0F0, 0xC5C9, 0xD0F1, 0xC5CA, 0xD0F2, 0xB58F, 0xD0F3, 0xB590,
+	0xD0F4, 0xB591, 0xD0F5, 0xB592, 0xD0F6, 0xB593, 0xD0F7, 0xB594,	0xD0F8, 0xC5CB, 0xD0F9, 0xB595, 0xD0FA, 0xB596, 0xD0FB, 0xB597,
+	0xD0FC, 0xB598, 0xD0FD, 0xB599, 0xD0FE, 0xB59A, 0xD0FF, 0xB59B,	0xD100, 0xB59C, 0xD101, 0xB59D, 0xD102, 0xB59E, 0xD103, 0xB59F,
+	0xD104, 0xB5A0, 0xD105, 0xB641, 0xD106, 0xB642, 0xD107, 0xB643,	0xD108, 0xB644, 0xD109, 0xB645, 0xD10A, 0xB646, 0xD10B, 0xB647,
+	0xD10C, 0xB648, 0xD10D, 0xC5CC, 0xD10E, 0xB649, 0xD10F, 0xB64A,	0xD110, 0xB64B, 0xD111, 0xB64C, 0xD112, 0xB64D, 0xD113, 0xB64E,
+	0xD114, 0xB64F, 0xD115, 0xB650, 0xD116, 0xB651, 0xD117, 0xB652,	0xD118, 0xB653, 0xD119, 0xB654, 0xD11A, 0xB655, 0xD11B, 0xB656,
+	0xD11C, 0xB657, 0xD11D, 0xB658, 0xD11E, 0xB659, 0xD11F, 0xB65A,	0xD120, 0xB661, 0xD121, 0xB662, 0xD122, 0xB663, 0xD123, 0xB664,
+	0xD124, 0xB665, 0xD125, 0xB666, 0xD126, 0xB667, 0xD127, 0xB668,	0xD128, 0xB669, 0xD129, 0xB66A, 0xD12A, 0xB66B, 0xD12B, 0xB66C,
+	0xD12C, 0xB66D, 0xD12D, 0xB66E, 0xD12E, 0xB66F, 0xD12F, 0xB670,	0xD130, 0xC5CD, 0xD131, 0xC5CE, 0xD132, 0xB671, 0xD133, 0xB672,
+	0xD134, 0xC5CF, 0xD135, 0xB673, 0xD136, 0xB674, 0xD137, 0xB675,	0xD138, 0xC5D0, 0xD139, 0xB676, 0xD13A, 0xC5D1, 0xD13B, 0xB677,
+	0xD13C, 0xB678, 0xD13D, 0xB679, 0xD13E, 0xB67A, 0xD13F, 0xB681,	0xD140, 0xC5D2, 0xD141, 0xC5D3, 0xD142, 0xB682, 0xD143, 0xC5D4,
+	0xD144, 0xC5D5, 0xD145, 0xC5D6, 0xD146, 0xB683, 0xD147, 0xB684,	0xD148, 0xB685, 0xD149, 0xB686, 0xD14A, 0xB687, 0xD14B, 0xB688,
+	0xD14C, 0xC5D7, 0xD14D, 0xC5D8, 0xD14E, 0xB689, 0xD14F, 0xB68A,	0xD150, 0xC5D9, 0xD151, 0xB68B, 0xD152, 0xB68C, 0xD153, 0xB68D,
+	0xD154, 0xC5DA, 0xD155, 0xB68E, 0xD156, 0xB68F, 0xD157, 0xB690,	0xD158, 0xB691, 0xD159, 0xB692, 0xD15A, 0xB693, 0xD15B, 0xB694,
+	0xD15C, 0xC5DB, 0xD15D, 0xC5DC, 0xD15E, 0xB695, 0xD15F, 0xC5DD,	0xD160, 0xB696, 0xD161, 0xC5DE, 0xD162, 0xB697, 0xD163, 0xB698,
+	0xD164, 0xB699, 0xD165, 0xB69A, 0xD166, 0xB69B, 0xD167, 0xB69C,	0xD168, 0xC5DF, 0xD169, 0xB69D, 0xD16A, 0xB69E, 0xD16B, 0xB69F,
+	0xD16C, 0xC5E0, 0xD16D, 0xB6A0, 0xD16E, 0xB741, 0xD16F, 0xB742,	0xD170, 0xB743, 0xD171, 0xB744, 0xD172, 0xB745, 0xD173, 0xB746,
+	0xD174, 0xB747, 0xD175, 0xB748, 0xD176, 0xB749, 0xD177, 0xB74A,	0xD178, 0xB74B, 0xD179, 0xB74C, 0xD17A, 0xB74D, 0xD17B, 0xB74E,
+	0xD17C, 0xC5E1, 0xD17D, 0xB74F, 0xD17E, 0xB750, 0xD17F, 0xB751,	0xD180, 0xB752, 0xD181, 0xB753, 0xD182, 0xB754, 0xD183, 0xB755,
+	0xD184, 0xC5E2, 0xD185, 0xB756, 0xD186, 0xB757, 0xD187, 0xB758,	0xD188, 0xC5E3, 0xD189, 0xB759, 0xD18A, 0xB75A, 0xD18B, 0xB761,
+	0xD18C, 0xB762, 0xD18D, 0xB763, 0xD18E, 0xB764, 0xD18F, 0xB765,	0xD190, 0xB766, 0xD191, 0xB767, 0xD192, 0xB768, 0xD193, 0xB769,
+	0xD194, 0xB76A, 0xD195, 0xB76B, 0xD196, 0xB76C, 0xD197, 0xB76D,	0xD198, 0xB76E, 0xD199, 0xB76F, 0xD19A, 0xB770, 0xD19B, 0xB771,
+	0xD19C, 0xB772, 0xD19D, 0xB773, 0xD19E, 0xB774, 0xD19F, 0xB775,	0xD1A0, 0xC5E4, 0xD1A1, 0xC5E5, 0xD1A2, 0xB776, 0xD1A3, 0xB777,
+	0xD1A4, 0xC5E6, 0xD1A5, 0xB778, 0xD1A6, 0xB779, 0xD1A7, 0xB77A,	0xD1A8, 0xC5E7, 0xD1A9, 0xB781, 0xD1AA, 0xB782, 0xD1AB, 0xB783,
+	0xD1AC, 0xB784, 0xD1AD, 0xB785, 0xD1AE, 0xB786, 0xD1AF, 0xB787,	0xD1B0, 0xC5E8, 0xD1B1, 0xC5E9, 0xD1B2, 0xB788, 0xD1B3, 0xC5EA,
+	0xD1B4, 0xB789, 0xD1B5, 0xC5EB, 0xD1B6, 0xB78A, 0xD1B7, 0xB78B,	0xD1B8, 0xB78C, 0xD1B9, 0xB78D, 0xD1BA, 0xC5EC, 0xD1BB, 0xB78E,
+	0xD1BC, 0xC5ED, 0xD1BD, 0xB78F, 0xD1BE, 0xB790, 0xD1BF, 0xB791,	0xD1C0, 0xC5EE, 0xD1C1, 0xB792, 0xD1C2, 0xB793, 0xD1C3, 0xB794,
+	0xD1C4, 0xB795, 0xD1C5, 0xB796, 0xD1C6, 0xB797, 0xD1C7, 0xB798,	0xD1C8, 0xB799, 0xD1C9, 0xB79A, 0xD1CA, 0xB79B, 0xD1CB, 0xB79C,
+	0xD1CC, 0xB79D, 0xD1CD, 0xB79E, 0xD1CE, 0xB79F, 0xD1CF, 0xB7A0,	0xD1D0, 0xB841, 0xD1D1, 0xB842, 0xD1D2, 0xB843, 0xD1D3, 0xB844,
+	0xD1D4, 0xB845, 0xD1D5, 0xB846, 0xD1D6, 0xB847, 0xD1D7, 0xB848,	0xD1D8, 0xC5EF, 0xD1D9, 0xB849, 0xD1DA, 0xB84A, 0xD1DB, 0xB84B,
+	0xD1DC, 0xB84C, 0xD1DD, 0xB84D, 0xD1DE, 0xB84E, 0xD1DF, 0xB84F,	0xD1E0, 0xB850, 0xD1E1, 0xB851, 0xD1E2, 0xB852, 0xD1E3, 0xB853,
+	0xD1E4, 0xB854, 0xD1E5, 0xB855, 0xD1E6, 0xB856, 0xD1E7, 0xB857,	0xD1E8, 0xB858, 0xD1E9, 0xB859, 0xD1EA, 0xB85A, 0xD1EB, 0xB861,
+	0xD1EC, 0xB862, 0xD1ED, 0xB863, 0xD1EE, 0xB864, 0xD1EF, 0xB865,	0xD1F0, 0xB866, 0xD1F1, 0xB867, 0xD1F2, 0xB868, 0xD1F3, 0xB869,
+	0xD1F4, 0xC5F0, 0xD1F5, 0xB86A, 0xD1F6, 0xB86B, 0xD1F7, 0xB86C,	0xD1F8, 0xC5F1, 0xD1F9, 0xB86D, 0xD1FA, 0xB86E, 0xD1FB, 0xB86F,
+	0xD1FC, 0xB870, 0xD1FD, 0xB871, 0xD1FE, 0xB872, 0xD1FF, 0xB873,	0xD200, 0xB874, 0xD201, 0xB875, 0xD202, 0xB876, 0xD203, 0xB877,
+	0xD204, 0xB878, 0xD205, 0xB879, 0xD206, 0xB87A, 0xD207, 0xC5F2,	0xD208, 0xB881, 0xD209, 0xC5F3, 0xD20A, 0xB882, 0xD20B, 0xB883,
+	0xD20C, 0xB884, 0xD20D, 0xB885, 0xD20E, 0xB886, 0xD20F, 0xB887,	0xD210, 0xC5F4, 0xD211, 0xB888, 0xD212, 0xB889, 0xD213, 0xB88A,
+	0xD214, 0xB88B, 0xD215, 0xB88C, 0xD216, 0xB88D, 0xD217, 0xB88E,	0xD218, 0xB88F, 0xD219, 0xB890, 0xD21A, 0xB891, 0xD21B, 0xB892,
+	0xD21C, 0xB893, 0xD21D, 0xB894, 0xD21E, 0xB895, 0xD21F, 0xB896,	0xD220, 0xB897, 0xD221, 0xB898, 0xD222, 0xB899, 0xD223, 0xB89A,
+	0xD224, 0xB89B, 0xD225, 0xB89C, 0xD226, 0xB89D, 0xD227, 0xB89E,	0xD228, 0xB89F, 0xD229, 0xB8A0, 0xD22A, 0xB941, 0xD22B, 0xB942,
+	0xD22C, 0xC5F5, 0xD22D, 0xC5F6, 0xD22E, 0xB943, 0xD22F, 0xB944,	0xD230, 0xC5F7, 0xD231, 0xB945, 0xD232, 0xB946, 0xD233, 0xB947,
+	0xD234, 0xC5F8, 0xD235, 0xB948, 0xD236, 0xB949, 0xD237, 0xB94A,	0xD238, 0xB94B, 0xD239, 0xB94C, 0xD23A, 0xB94D, 0xD23B, 0xB94E,
+	0xD23C, 0xC5F9, 0xD23D, 0xC5FA, 0xD23E, 0xB94F, 0xD23F, 0xC5FB,	0xD240, 0xB950, 0xD241, 0xC5FC, 0xD242, 0xB951, 0xD243, 0xB952,
+	0xD244, 0xB953, 0xD245, 0xB954, 0xD246, 0xB955, 0xD247, 0xB956,	0xD248, 0xC5FD, 0xD249, 0xB957, 0xD24A, 0xB958, 0xD24B, 0xB959,
+	0xD24C, 0xB95A, 0xD24D, 0xB961, 0xD24E, 0xB962, 0xD24F, 0xB963,	0xD250, 0xB964, 0xD251, 0xB965, 0xD252, 0xB966, 0xD253, 0xB967,
+	0xD254, 0xB968, 0xD255, 0xB969, 0xD256, 0xB96A, 0xD257, 0xB96B,	0xD258, 0xB96C, 0xD259, 0xB96D, 0xD25A, 0xB96E, 0xD25B, 0xB96F,
+	0xD25C, 0xC5FE, 0xD25D, 0xB970, 0xD25E, 0xB971, 0xD25F, 0xB972,	0xD260, 0xB973, 0xD261, 0xB974, 0xD262, 0xB975, 0xD263, 0xB976,
+	0xD264, 0xC6A1, 0xD265, 0xB977, 0xD266, 0xB978, 0xD267, 0xB979,	0xD268, 0xB97A, 0xD269, 0xB981, 0xD26A, 0xB982, 0xD26B, 0xB983,
+	0xD26C, 0xB984, 0xD26D, 0xB985, 0xD26E, 0xB986, 0xD26F, 0xB987,	0xD270, 0xB988, 0xD271, 0xB989, 0xD272, 0xB98A, 0xD273, 0xB98B,
+	0xD274, 0xB98C, 0xD275, 0xB98D, 0xD276, 0xB98E, 0xD277, 0xB98F,	0xD278, 0xB990, 0xD279, 0xB991, 0xD27A, 0xB992, 0xD27B, 0xB993,
+	0xD27C, 0xB994, 0xD27D, 0xB995, 0xD27E, 0xB996, 0xD27F, 0xB997,	0xD280, 0xC6A2, 0xD281, 0xC6A3, 0xD282, 0xB998, 0xD283, 0xB999,
+	0xD284, 0xC6A4, 0xD285, 0xB99A, 0xD286, 0xB99B, 0xD287, 0xB99C,	0xD288, 0xC6A5, 0xD289, 0xB99D, 0xD28A, 0xB99E, 0xD28B, 0xB99F,
+	0xD28C, 0xB9A0, 0xD28D, 0xBA41, 0xD28E, 0xBA42, 0xD28F, 0xBA43,	0xD290, 0xC6A6, 0xD291, 0xC6A7, 0xD292, 0xBA44, 0xD293, 0xBA45,
+	0xD294, 0xBA46, 0xD295, 0xC6A8, 0xD296, 0xBA47, 0xD297, 0xBA48,	0xD298, 0xBA49, 0xD299, 0xBA4A, 0xD29A, 0xBA4B, 0xD29B, 0xBA4C,
+	0xD29C, 0xC6A9, 0xD29D, 0xBA4D, 0xD29E, 0xBA4E, 0xD29F, 0xBA4F,	0xD2A0, 0xC6AA, 0xD2A1, 0xBA50, 0xD2A2, 0xBA51, 0xD2A3, 0xBA52,
+	0xD2A4, 0xC6AB, 0xD2A5, 0xBA53, 0xD2A6, 0xBA54, 0xD2A7, 0xBA55,	0xD2A8, 0xBA56, 0xD2A9, 0xBA57, 0xD2AA, 0xBA58, 0xD2AB, 0xBA59,
+	0xD2AC, 0xC6AC, 0xD2AD, 0xBA5A, 0xD2AE, 0xBA61, 0xD2AF, 0xBA62,	0xD2B0, 0xBA63, 0xD2B1, 0xC6AD, 0xD2B2, 0xBA64, 0xD2B3, 0xBA65,
+	0xD2B4, 0xBA66, 0xD2B5, 0xBA67, 0xD2B6, 0xBA68, 0xD2B7, 0xBA69,	0xD2B8, 0xC6AE, 0xD2B9, 0xC6AF, 0xD2BA, 0xBA6A, 0xD2BB, 0xBA6B,
+	0xD2BC, 0xC6B0, 0xD2BD, 0xBA6C, 0xD2BE, 0xBA6D, 0xD2BF, 0xC6B1,	0xD2C0, 0xC6B2, 0xD2C1, 0xBA6E, 0xD2C2, 0xC6B3, 0xD2C3, 0xBA6F,
+	0xD2C4, 0xBA70, 0xD2C5, 0xBA71, 0xD2C6, 0xBA72, 0xD2C7, 0xBA73,	0xD2C8, 0xC6B4, 0xD2C9, 0xC6B5, 0xD2CA, 0xBA74, 0xD2CB, 0xC6B6,
+	0xD2CC, 0xBA75, 0xD2CD, 0xBA76, 0xD2CE, 0xBA77, 0xD2CF, 0xBA78,	0xD2D0, 0xBA79, 0xD2D1, 0xBA7A, 0xD2D2, 0xBA81, 0xD2D3, 0xBA82,
+	0xD2D4, 0xC6B7, 0xD2D5, 0xBA83, 0xD2D6, 0xBA84, 0xD2D7, 0xBA85,	0xD2D8, 0xC6B8, 0xD2D9, 0xBA86, 0xD2DA, 0xBA87, 0xD2DB, 0xBA88,
+	0xD2DC, 0xC6B9, 0xD2DD, 0xBA89, 0xD2DE, 0xBA8A, 0xD2DF, 0xBA8B,	0xD2E0, 0xBA8C, 0xD2E1, 0xBA8D, 0xD2E2, 0xBA8E, 0xD2E3, 0xBA8F,
+	0xD2E4, 0xC6BA, 0xD2E5, 0xC6BB, 0xD2E6, 0xBA90, 0xD2E7, 0xBA91,	0xD2E8, 0xBA92, 0xD2E9, 0xBA93, 0xD2EA, 0xBA94, 0xD2EB, 0xBA95,
+	0xD2EC, 0xBA96, 0xD2ED, 0xBA97, 0xD2EE, 0xBA98, 0xD2EF, 0xBA99,	0xD2F0, 0xC6BC, 0xD2F1, 0xC6BD, 0xD2F2, 0xBA9A, 0xD2F3, 0xBA9B,
+	0xD2F4, 0xC6BE, 0xD2F5, 0xBA9C, 0xD2F6, 0xBA9D, 0xD2F7, 0xBA9E,	0xD2F8, 0xC6BF, 0xD2F9, 0xBA9F, 0xD2FA, 0xBAA0, 0xD2FB, 0xBB41,
+	0xD2FC, 0xBB42, 0xD2FD, 0xBB43, 0xD2FE, 0xBB44, 0xD2FF, 0xBB45,	0xD300, 0xC6C0, 0xD301, 0xC6C1, 0xD302, 0xBB46, 0xD303, 0xC6C2,
+	0xD304, 0xBB47, 0xD305, 0xC6C3, 0xD306, 0xBB48, 0xD307, 0xBB49,	0xD308, 0xBB4A, 0xD309, 0xBB4B, 0xD30A, 0xBB4C, 0xD30B, 0xBB4D,
+	0xD30C, 0xC6C4, 0xD30D, 0xC6C5, 0xD30E, 0xC6C6, 0xD30F, 0xBB4E,	0xD310, 0xC6C7, 0xD311, 0xBB4F, 0xD312, 0xBB50, 0xD313, 0xBB51,
+	0xD314, 0xC6C8, 0xD315, 0xBB52, 0xD316, 0xC6C9, 0xD317, 0xBB53,	0xD318, 0xBB54, 0xD319, 0xBB55, 0xD31A, 0xBB56, 0xD31B, 0xBB57,
+	0xD31C, 0xC6CA, 0xD31D, 0xC6CB, 0xD31E, 0xBB58, 0xD31F, 0xC6CC,	0xD320, 0xC6CD, 0xD321, 0xC6CE, 0xD322, 0xBB59, 0xD323, 0xBB5A,
+	0xD324, 0xBB61, 0xD325, 0xC6CF, 0xD326, 0xBB62, 0xD327, 0xBB63,	0xD328, 0xC6D0, 0xD329, 0xC6D1, 0xD32A, 0xBB64, 0xD32B, 0xBB65,
+	0xD32C, 0xC6D2, 0xD32D, 0xBB66, 0xD32E, 0xBB67, 0xD32F, 0xBB68,	0xD330, 0xC6D3, 0xD331, 0xBB69, 0xD332, 0xBB6A, 0xD333, 0xBB6B,
+	0xD334, 0xBB6C, 0xD335, 0xBB6D, 0xD336, 0xBB6E, 0xD337, 0xBB6F,	0xD338, 0xC6D4, 0xD339, 0xC6D5, 0xD33A, 0xBB70, 0xD33B, 0xC6D6,
+	0xD33C, 0xC6D7, 0xD33D, 0xC6D8, 0xD33E, 0xBB71, 0xD33F, 0xBB72,	0xD340, 0xBB73, 0xD341, 0xBB74, 0xD342, 0xBB75, 0xD343, 0xBB76,
+	0xD344, 0xC6D9, 0xD345, 0xC6DA, 0xD346, 0xBB77, 0xD347, 0xBB78,	0xD348, 0xBB79, 0xD349, 0xBB7A, 0xD34A, 0xBB81, 0xD34B, 0xBB82,
+	0xD34C, 0xBB83, 0xD34D, 0xBB84, 0xD34E, 0xBB85, 0xD34F, 0xBB86,	0xD350, 0xBB87, 0xD351, 0xBB88, 0xD352, 0xBB89, 0xD353, 0xBB8A,
+	0xD354, 0xBB8B, 0xD355, 0xBB8C, 0xD356, 0xBB8D, 0xD357, 0xBB8E,	0xD358, 0xBB8F, 0xD359, 0xBB90, 0xD35A, 0xBB91, 0xD35B, 0xBB92,
+	0xD35C, 0xBB93, 0xD35D, 0xBB94, 0xD35E, 0xBB95, 0xD35F, 0xBB96,	0xD360, 0xBB97, 0xD361, 0xBB98, 0xD362, 0xBB99, 0xD363, 0xBB9A,
+	0xD364, 0xBB9B, 0xD365, 0xBB9C, 0xD366, 0xBB9D, 0xD367, 0xBB9E,	0xD368, 0xBB9F, 0xD369, 0xBBA0, 0xD36A, 0xBC41, 0xD36B, 0xBC42,
+	0xD36C, 0xBC43, 0xD36D, 0xBC44, 0xD36E, 0xBC45, 0xD36F, 0xBC46,	0xD370, 0xBC47, 0xD371, 0xBC48, 0xD372, 0xBC49, 0xD373, 0xBC4A,
+	0xD374, 0xBC4B, 0xD375, 0xBC4C, 0xD376, 0xBC4D, 0xD377, 0xBC4E,	0xD378, 0xBC4F, 0xD379, 0xBC50, 0xD37A, 0xBC51, 0xD37B, 0xBC52,
+	0xD37C, 0xC6DB, 0xD37D, 0xC6DC, 0xD37E, 0xBC53, 0xD37F, 0xBC54,	0xD380, 0xC6DD, 0xD381, 0xBC55, 0xD382, 0xBC56, 0xD383, 0xBC57,
+	0xD384, 0xC6DE, 0xD385, 0xBC58, 0xD386, 0xBC59, 0xD387, 0xBC5A,	0xD388, 0xBC61, 0xD389, 0xBC62, 0xD38A, 0xBC63, 0xD38B, 0xBC64,
+	0xD38C, 0xC6DF, 0xD38D, 0xC6E0, 0xD38E, 0xBC65, 0xD38F, 0xC6E1,	0xD390, 0xC6E2, 0xD391, 0xC6E3, 0xD392, 0xBC66, 0xD393, 0xBC67,
+	0xD394, 0xBC68, 0xD395, 0xBC69, 0xD396, 0xBC6A, 0xD397, 0xBC6B,	0xD398, 0xC6E4, 0xD399, 0xC6E5, 0xD39A, 0xBC6C, 0xD39B, 0xBC6D,
+	0xD39C, 0xC6E6, 0xD39D, 0xBC6E, 0xD39E, 0xBC6F, 0xD39F, 0xBC70,	0xD3A0, 0xC6E7, 0xD3A1, 0xBC71, 0xD3A2, 0xBC72, 0xD3A3, 0xBC73,
+	0xD3A4, 0xBC74, 0xD3A5, 0xBC75, 0xD3A6, 0xBC76, 0xD3A7, 0xBC77,	0xD3A8, 0xC6E8, 0xD3A9, 0xC6E9, 0xD3AA, 0xBC78, 0xD3AB, 0xC6EA,
+	0xD3AC, 0xBC79, 0xD3AD, 0xC6EB, 0xD3AE, 0xBC7A, 0xD3AF, 0xBC81,	0xD3B0, 0xBC82, 0xD3B1, 0xBC83, 0xD3B2, 0xBC84, 0xD3B3, 0xBC85,
+	0xD3B4, 0xC6EC, 0xD3B5, 0xBC86, 0xD3B6, 0xBC87, 0xD3B7, 0xBC88,	0xD3B8, 0xC6ED, 0xD3B9, 0xBC89, 0xD3BA, 0xBC8A, 0xD3BB, 0xBC8B,
+	0xD3BC, 0xC6EE, 0xD3BD, 0xBC8C, 0xD3BE, 0xBC8D, 0xD3BF, 0xBC8E,	0xD3C0, 0xBC8F, 0xD3C1, 0xBC90, 0xD3C2, 0xBC91, 0xD3C3, 0xBC92,
+	0xD3C4, 0xC6EF, 0xD3C5, 0xC6F0, 0xD3C6, 0xBC93, 0xD3C7, 0xBC94,	0xD3C8, 0xC6F1, 0xD3C9, 0xC6F2, 0xD3CA, 0xBC95, 0xD3CB, 0xBC96,
+	0xD3CC, 0xBC97, 0xD3CD, 0xBC98, 0xD3CE, 0xBC99, 0xD3CF, 0xBC9A,	0xD3D0, 0xC6F3, 0xD3D1, 0xBC9B, 0xD3D2, 0xBC9C, 0xD3D3, 0xBC9D,
+	0xD3D4, 0xBC9E, 0xD3D5, 0xBC9F, 0xD3D6, 0xBCA0, 0xD3D7, 0xBD41,	0xD3D8, 0xC6F4, 0xD3D9, 0xBD42, 0xD3DA, 0xBD43, 0xD3DB, 0xBD44,
+	0xD3DC, 0xBD45, 0xD3DD, 0xBD46, 0xD3DE, 0xBD47, 0xD3DF, 0xBD48,	0xD3E0, 0xBD49, 0xD3E1, 0xC6F5, 0xD3E2, 0xBD4A, 0xD3E3, 0xC6F6,
+	0xD3E4, 0xBD4B, 0xD3E5, 0xBD4C, 0xD3E6, 0xBD4D, 0xD3E7, 0xBD4E,	0xD3E8, 0xBD4F, 0xD3E9, 0xBD50, 0xD3EA, 0xBD51, 0xD3EB, 0xBD52,
+	0xD3EC, 0xC6F7, 0xD3ED, 0xC6F8, 0xD3EE, 0xBD53, 0xD3EF, 0xBD54,	0xD3F0, 0xC6F9, 0xD3F1, 0xBD55, 0xD3F2, 0xBD56, 0xD3F3, 0xBD57,
+	0xD3F4, 0xC6FA, 0xD3F5, 0xBD58, 0xD3F6, 0xBD59, 0xD3F7, 0xBD5A,	0xD3F8, 0xBD61, 0xD3F9, 0xBD62, 0xD3FA, 0xBD63, 0xD3FB, 0xBD64,
+	0xD3FC, 0xC6FB, 0xD3FD, 0xC6FC, 0xD3FE, 0xBD65, 0xD3FF, 0xC6FD,	0xD400, 0xBD66, 0xD401, 0xC6FE, 0xD402, 0xBD67, 0xD403, 0xBD68,
+	0xD404, 0xBD69, 0xD405, 0xBD6A, 0xD406, 0xBD6B, 0xD407, 0xBD6C,	0xD408, 0xC7A1, 0xD409, 0xBD6D, 0xD40A, 0xBD6E, 0xD40B, 0xBD6F,
+	0xD40C, 0xBD70, 0xD40D, 0xBD71, 0xD40E, 0xBD72, 0xD40F, 0xBD73,	0xD410, 0xBD74, 0xD411, 0xBD75, 0xD412, 0xBD76, 0xD413, 0xBD77,
+	0xD414, 0xBD78, 0xD415, 0xBD79, 0xD416, 0xBD7A, 0xD417, 0xBD81,	0xD418, 0xBD82, 0xD419, 0xBD83, 0xD41A, 0xBD84, 0xD41B, 0xBD85,
+	0xD41C, 0xBD86, 0xD41D, 0xC7A2, 0xD41E, 0xBD87, 0xD41F, 0xBD88,	0xD420, 0xBD89, 0xD421, 0xBD8A, 0xD422, 0xBD8B, 0xD423, 0xBD8C,
+	0xD424, 0xBD8D, 0xD425, 0xBD8E, 0xD426, 0xBD8F, 0xD427, 0xBD90,	0xD428, 0xBD91, 0xD429, 0xBD92, 0xD42A, 0xBD93, 0xD42B, 0xBD94,
+	0xD42C, 0xBD95, 0xD42D, 0xBD96, 0xD42E, 0xBD97, 0xD42F, 0xBD98,	0xD430, 0xBD99, 0xD431, 0xBD9A, 0xD432, 0xBD9B, 0xD433, 0xBD9C,
+	0xD434, 0xBD9D, 0xD435, 0xBD9E, 0xD436, 0xBD9F, 0xD437, 0xBDA0,	0xD438, 0xBE41, 0xD439, 0xBE42, 0xD43A, 0xBE43, 0xD43B, 0xBE44,
+	0xD43C, 0xBE45, 0xD43D, 0xBE46, 0xD43E, 0xBE47, 0xD43F, 0xBE48,	0xD440, 0xC7A3, 0xD441, 0xBE49, 0xD442, 0xBE4A, 0xD443, 0xBE4B,
+	0xD444, 0xC7A4, 0xD445, 0xBE4C, 0xD446, 0xBE4D, 0xD447, 0xBE4E,	0xD448, 0xBE4F, 0xD449, 0xBE50, 0xD44A, 0xBE51, 0xD44B, 0xBE52,
+	0xD44C, 0xBE53, 0xD44D, 0xBE54, 0xD44E, 0xBE55, 0xD44F, 0xBE56,	0xD450, 0xBE57, 0xD451, 0xBE58, 0xD452, 0xBE59, 0xD453, 0xBE5A,
+	0xD454, 0xBE61, 0xD455, 0xBE62, 0xD456, 0xBE63, 0xD457, 0xBE64,	0xD458, 0xBE65, 0xD459, 0xBE66, 0xD45A, 0xBE67, 0xD45B, 0xBE68,
+	0xD45C, 0xC7A5, 0xD45D, 0xBE69, 0xD45E, 0xBE6A, 0xD45F, 0xBE6B,	0xD460, 0xC7A6, 0xD461, 0xBE6C, 0xD462, 0xBE6D, 0xD463, 0xBE6E,
+	0xD464, 0xC7A7, 0xD465, 0xBE6F, 0xD466, 0xBE70, 0xD467, 0xBE71,	0xD468, 0xBE72, 0xD469, 0xBE73, 0xD46A, 0xBE74, 0xD46B, 0xBE75,
+	0xD46C, 0xBE76, 0xD46D, 0xC7A8, 0xD46E, 0xBE77, 0xD46F, 0xC7A9,	0xD470, 0xBE78, 0xD471, 0xBE79, 0xD472, 0xBE7A, 0xD473, 0xBE81,
+	0xD474, 0xBE82, 0xD475, 0xBE83, 0xD476, 0xBE84, 0xD477, 0xBE85,	0xD478, 0xC7AA, 0xD479, 0xC7AB, 0xD47A, 0xBE86, 0xD47B, 0xBE87,
+	0xD47C, 0xC7AC, 0xD47D, 0xBE88, 0xD47E, 0xBE89, 0xD47F, 0xC7AD,	0xD480, 0xC7AE, 0xD481, 0xBE8A, 0xD482, 0xC7AF, 0xD483, 0xBE8B,
+	0xD484, 0xBE8C, 0xD485, 0xBE8D, 0xD486, 0xBE8E, 0xD487, 0xBE8F,	0xD488, 0xC7B0, 0xD489, 0xC7B1, 0xD48A, 0xBE90, 0xD48B, 0xC7B2,
+	0xD48C, 0xBE91, 0xD48D, 0xC7B3, 0xD48E, 0xBE92, 0xD48F, 0xBE93,	0xD490, 0xBE94, 0xD491, 0xBE95, 0xD492, 0xBE96, 0xD493, 0xBE97,
+	0xD494, 0xC7B4, 0xD495, 0xBE98, 0xD496, 0xBE99, 0xD497, 0xBE9A,	0xD498, 0xBE9B, 0xD499, 0xBE9C, 0xD49A, 0xBE9D, 0xD49B, 0xBE9E,
+	0xD49C, 0xBE9F, 0xD49D, 0xBEA0, 0xD49E, 0xBF41, 0xD49F, 0xBF42,	0xD4A0, 0xBF43, 0xD4A1, 0xBF44, 0xD4A2, 0xBF45, 0xD4A3, 0xBF46,
+	0xD4A4, 0xBF47, 0xD4A5, 0xBF48, 0xD4A6, 0xBF49, 0xD4A7, 0xBF4A,	0xD4A8, 0xBF4B, 0xD4A9, 0xC7B5, 0xD4AA, 0xBF4C, 0xD4AB, 0xBF4D,
+	0xD4AC, 0xBF4E, 0xD4AD, 0xBF4F, 0xD4AE, 0xBF50, 0xD4AF, 0xBF51,	0xD4B0, 0xBF52, 0xD4B1, 0xBF53, 0xD4B2, 0xBF54, 0xD4B3, 0xBF55,
+	0xD4B4, 0xBF56, 0xD4B5, 0xBF57, 0xD4B6, 0xBF58, 0xD4B7, 0xBF59,	0xD4B8, 0xBF5A, 0xD4B9, 0xBF61, 0xD4BA, 0xBF62, 0xD4BB, 0xBF63,
+	0xD4BC, 0xBF64, 0xD4BD, 0xBF65, 0xD4BE, 0xBF66, 0xD4BF, 0xBF67,	0xD4C0, 0xBF68, 0xD4C1, 0xBF69, 0xD4C2, 0xBF6A, 0xD4C3, 0xBF6B,
+	0xD4C4, 0xBF6C, 0xD4C5, 0xBF6D, 0xD4C6, 0xBF6E, 0xD4C7, 0xBF6F,	0xD4C8, 0xBF70, 0xD4C9, 0xBF71, 0xD4CA, 0xBF72, 0xD4CB, 0xBF73,
+	0xD4CC, 0xC7B6, 0xD4CD, 0xBF74, 0xD4CE, 0xBF75, 0xD4CF, 0xBF76,	0xD4D0, 0xC7B7, 0xD4D1, 0xBF77, 0xD4D2, 0xBF78, 0xD4D3, 0xBF79,
+	0xD4D4, 0xC7B8, 0xD4D5, 0xBF7A, 0xD4D6, 0xBF81, 0xD4D7, 0xBF82,	0xD4D8, 0xBF83, 0xD4D9, 0xBF84, 0xD4DA, 0xBF85, 0xD4DB, 0xBF86,
+	0xD4DC, 0xC7B9, 0xD4DD, 0xBF87, 0xD4DE, 0xBF88, 0xD4DF, 0xC7BA,	0xD4E0, 0xBF89, 0xD4E1, 0xBF8A, 0xD4E2, 0xBF8B, 0xD4E3, 0xBF8C,
+	0xD4E4, 0xBF8D, 0xD4E5, 0xBF8E, 0xD4E6, 0xBF8F, 0xD4E7, 0xBF90,	0xD4E8, 0xC7BB, 0xD4E9, 0xBF91, 0xD4EA, 0xBF92, 0xD4EB, 0xBF93,
+	0xD4EC, 0xC7BC, 0xD4ED, 0xBF94, 0xD4EE, 0xBF95, 0xD4EF, 0xBF96,	0xD4F0, 0xC7BD, 0xD4F1, 0xBF97, 0xD4F2, 0xBF98, 0xD4F3, 0xBF99,
+	0xD4F4, 0xBF9A, 0xD4F5, 0xBF9B, 0xD4F6, 0xBF9C, 0xD4F7, 0xBF9D,	0xD4F8, 0xC7BE, 0xD4F9, 0xBF9E, 0xD4FA, 0xBF9F, 0xD4FB, 0xC7BF,
+	0xD4FC, 0xBFA0, 0xD4FD, 0xC7C0, 0xD4FE, 0xC041, 0xD4FF, 0xC042,	0xD500, 0xC043, 0xD501, 0xC044, 0xD502, 0xC045, 0xD503, 0xC046,
+	0xD504, 0xC7C1, 0xD505, 0xC047, 0xD506, 0xC048, 0xD507, 0xC049,	0xD508, 0xC7C2, 0xD509, 0xC04A, 0xD50A, 0xC04B, 0xD50B, 0xC04C,
+	0xD50C, 0xC7C3, 0xD50D, 0xC04D, 0xD50E, 0xC04E, 0xD50F, 0xC04F,	0xD510, 0xC050, 0xD511, 0xC051, 0xD512, 0xC052, 0xD513, 0xC053,
+	0xD514, 0xC7C4, 0xD515, 0xC7C5, 0xD516, 0xC054, 0xD517, 0xC7C6,	0xD518, 0xC055, 0xD519, 0xC056, 0xD51A, 0xC057, 0xD51B, 0xC058,
+	0xD51C, 0xC059, 0xD51D, 0xC05A, 0xD51E, 0xC061, 0xD51F, 0xC062,	0xD520, 0xC063, 0xD521, 0xC064, 0xD522, 0xC065, 0xD523, 0xC066,
+	0xD524, 0xC067, 0xD525, 0xC068, 0xD526, 0xC069, 0xD527, 0xC06A,	0xD528, 0xC06B, 0xD529, 0xC06C, 0xD52A, 0xC06D, 0xD52B, 0xC06E,
+	0xD52C, 0xC06F, 0xD52D, 0xC070, 0xD52E, 0xC071, 0xD52F, 0xC072,	0xD530, 0xC073, 0xD531, 0xC074, 0xD532, 0xC075, 0xD533, 0xC076,
+	0xD534, 0xC077, 0xD535, 0xC078, 0xD536, 0xC079, 0xD537, 0xC07A,	0xD538, 0xC081, 0xD539, 0xC082, 0xD53A, 0xC083, 0xD53B, 0xC084,
+	0xD53C, 0xC7C7, 0xD53D, 0xC7C8, 0xD53E, 0xC085, 0xD53F, 0xC086,	0xD540, 0xC7C9, 0xD541, 0xC087, 0xD542, 0xC088, 0xD543, 0xC089,
+	0xD544, 0xC7CA, 0xD545, 0xC08A, 0xD546, 0xC08B, 0xD547, 0xC08C,	0xD548, 0xC08D, 0xD549, 0xC08E, 0xD54A, 0xC08F, 0xD54B, 0xC090,
+	0xD54C, 0xC7CB, 0xD54D, 0xC7CC, 0xD54E, 0xC091, 0xD54F, 0xC7CD,	0xD550, 0xC092, 0xD551, 0xC7CE, 0xD552, 0xC093, 0xD553, 0xC094,
+	0xD554, 0xC095, 0xD555, 0xC096, 0xD556, 0xC097, 0xD557, 0xC098,	0xD558, 0xC7CF, 0xD559, 0xC7D0, 0xD55A, 0xC099, 0xD55B, 0xC09A,
+	0xD55C, 0xC7D1, 0xD55D, 0xC09B, 0xD55E, 0xC09C, 0xD55F, 0xC09D,	0xD560, 0xC7D2, 0xD561, 0xC09E, 0xD562, 0xC09F, 0xD563, 0xC0A0,
+	0xD564, 0xC141, 0xD565, 0xC7D3, 0xD566, 0xC142, 0xD567, 0xC143,	0xD568, 0xC7D4, 0xD569, 0xC7D5, 0xD56A, 0xC144, 0xD56B, 0xC7D6,
+	0xD56C, 0xC145, 0xD56D, 0xC7D7, 0xD56E, 0xC146, 0xD56F, 0xC147,	0xD570, 0xC148, 0xD571, 0xC149, 0xD572, 0xC14A, 0xD573, 0xC14B,
+	0xD574, 0xC7D8, 0xD575, 0xC7D9, 0xD576, 0xC14C, 0xD577, 0xC14D,	0xD578, 0xC7DA, 0xD579, 0xC14E, 0xD57A, 0xC14F, 0xD57B, 0xC150,
+	0xD57C, 0xC7DB, 0xD57D, 0xC151, 0xD57E, 0xC152, 0xD57F, 0xC153,	0xD580, 0xC154, 0xD581, 0xC155, 0xD582, 0xC156, 0xD583, 0xC157,
+	0xD584, 0xC7DC, 0xD585, 0xC7DD, 0xD586, 0xC158, 0xD587, 0xC7DE,	0xD588, 0xC7DF, 0xD589, 0xC7E0, 0xD58A, 0xC159, 0xD58B, 0xC15A,
+	0xD58C, 0xC161, 0xD58D, 0xC162, 0xD58E, 0xC163, 0xD58F, 0xC164,	0xD590, 0xC7E1, 0xD591, 0xC165, 0xD592, 0xC166, 0xD593, 0xC167,
+	0xD594, 0xC168, 0xD595, 0xC169, 0xD596, 0xC16A, 0xD597, 0xC16B,	0xD598, 0xC16C, 0xD599, 0xC16D, 0xD59A, 0xC16E, 0xD59B, 0xC16F,
+	0xD59C, 0xC170, 0xD59D, 0xC171, 0xD59E, 0xC172, 0xD59F, 0xC173,	0xD5A0, 0xC174, 0xD5A1, 0xC175, 0xD5A2, 0xC176, 0xD5A3, 0xC177,
+	0xD5A4, 0xC178, 0xD5A5, 0xC7E2, 0xD5A6, 0xC179, 0xD5A7, 0xC17A,	0xD5A8, 0xC181, 0xD5A9, 0xC182, 0xD5AA, 0xC183, 0xD5AB, 0xC184,
+	0xD5AC, 0xC185, 0xD5AD, 0xC186, 0xD5AE, 0xC187, 0xD5AF, 0xC188,	0xD5B0, 0xC189, 0xD5B1, 0xC18A, 0xD5B2, 0xC18B, 0xD5B3, 0xC18C,
+	0xD5B4, 0xC18D, 0xD5B5, 0xC18E, 0xD5B6, 0xC18F, 0xD5B7, 0xC190,	0xD5B8, 0xC191, 0xD5B9, 0xC192, 0xD5BA, 0xC193, 0xD5BB, 0xC194,
+	0xD5BC, 0xC195, 0xD5BD, 0xC196, 0xD5BE, 0xC197, 0xD5BF, 0xC198,	0xD5C0, 0xC199, 0xD5C1, 0xC19A, 0xD5C2, 0xC19B, 0xD5C3, 0xC19C,
+	0xD5C4, 0xC19D, 0xD5C5, 0xC19E, 0xD5C6, 0xC19F, 0xD5C7, 0xC1A0,	0xD5C8, 0xC7E3, 0xD5C9, 0xC7E4, 0xD5CA, 0xC241, 0xD5CB, 0xC242,
+	0xD5CC, 0xC7E5, 0xD5CD, 0xC243, 0xD5CE, 0xC244, 0xD5CF, 0xC245,	0xD5D0, 0xC7E6, 0xD5D1, 0xC246, 0xD5D2, 0xC7E7, 0xD5D3, 0xC247,
+	0xD5D4, 0xC248, 0xD5D5, 0xC249, 0xD5D6, 0xC24A, 0xD5D7, 0xC24B,	0xD5D8, 0xC7E8, 0xD5D9, 0xC7E9, 0xD5DA, 0xC24C, 0xD5DB, 0xC7EA,
+	0xD5DC, 0xC24D, 0xD5DD, 0xC7EB, 0xD5DE, 0xC24E, 0xD5DF, 0xC24F,	0xD5E0, 0xC250, 0xD5E1, 0xC251, 0xD5E2, 0xC252, 0xD5E3, 0xC253,
+	0xD5E4, 0xC7EC, 0xD5E5, 0xC7ED, 0xD5E6, 0xC254, 0xD5E7, 0xC255,	0xD5E8, 0xC7EE, 0xD5E9, 0xC256, 0xD5EA, 0xC257, 0xD5EB, 0xC258,
+	0xD5EC, 0xC7EF, 0xD5ED, 0xC259, 0xD5EE, 0xC25A, 0xD5EF, 0xC261,	0xD5F0, 0xC262, 0xD5F1, 0xC263, 0xD5F2, 0xC264, 0xD5F3, 0xC265,
+	0xD5F4, 0xC7F0, 0xD5F5, 0xC7F1, 0xD5F6, 0xC266, 0xD5F7, 0xC7F2,	0xD5F8, 0xC267, 0xD5F9, 0xC7F3, 0xD5FA, 0xC268, 0xD5FB, 0xC269,
+	0xD5FC, 0xC26A, 0xD5FD, 0xC26B, 0xD5FE, 0xC26C, 0xD5FF, 0xC26D,	0xD600, 0xC7F4, 0xD601, 0xC7F5, 0xD602, 0xC26E, 0xD603, 0xC26F,
+	0xD604, 0xC7F6, 0xD605, 0xC270, 0xD606, 0xC271, 0xD607, 0xC272,	0xD608, 0xC7F7, 0xD609, 0xC273, 0xD60A, 0xC274, 0xD60B, 0xC275,
+	0xD60C, 0xC276, 0xD60D, 0xC277, 0xD60E, 0xC278, 0xD60F, 0xC279,	0xD610, 0xC7F8, 0xD611, 0xC7F9, 0xD612, 0xC27A, 0xD613, 0xC7FA,
+	0xD614, 0xC7FB, 0xD615, 0xC7FC, 0xD616, 0xC281, 0xD617, 0xC282,	0xD618, 0xC283, 0xD619, 0xC284, 0xD61A, 0xC285, 0xD61B, 0xC286,
+	0xD61C, 0xC7FD, 0xD61D, 0xC287, 0xD61E, 0xC288, 0xD61F, 0xC289,	0xD620, 0xC7FE, 0xD621, 0xC28A, 0xD622, 0xC28B, 0xD623, 0xC28C,
+	0xD624, 0xC8A1, 0xD625, 0xC28D, 0xD626, 0xC28E, 0xD627, 0xC28F,	0xD628, 0xC290, 0xD629, 0xC291, 0xD62A, 0xC292, 0xD62B, 0xC293,
+	0xD62C, 0xC294, 0xD62D, 0xC8A2, 0xD62E, 0xC295, 0xD62F, 0xC296,	0xD630, 0xC297, 0xD631, 0xC298, 0xD632, 0xC299, 0xD633, 0xC29A,
+	0xD634, 0xC29B, 0xD635, 0xC29C, 0xD636, 0xC29D, 0xD637, 0xC29E,	0xD638, 0xC8A3, 0xD639, 0xC8A4, 0xD63A, 0xC29F, 0xD63B, 0xC2A0,
+	0xD63C, 0xC8A5, 0xD63D, 0xC341, 0xD63E, 0xC342, 0xD63F, 0xC343,	0xD640, 0xC8A6, 0xD641, 0xC344, 0xD642, 0xC345, 0xD643, 0xC346,
+	0xD644, 0xC347, 0xD645, 0xC8A7, 0xD646, 0xC348, 0xD647, 0xC349,	0xD648, 0xC8A8, 0xD649, 0xC8A9, 0xD64A, 0xC34A, 0xD64B, 0xC8AA,
+	0xD64C, 0xC34B, 0xD64D, 0xC8AB, 0xD64E, 0xC34C, 0xD64F, 0xC34D,	0xD650, 0xC34E, 0xD651, 0xC8AC, 0xD652, 0xC34F, 0xD653, 0xC350,
+	0xD654, 0xC8AD, 0xD655, 0xC8AE, 0xD656, 0xC351, 0xD657, 0xC352,	0xD658, 0xC8AF, 0xD659, 0xC353, 0xD65A, 0xC354, 0xD65B, 0xC355,
+	0xD65C, 0xC8B0, 0xD65D, 0xC356, 0xD65E, 0xC357, 0xD65F, 0xC358,	0xD660, 0xC359, 0xD661, 0xC35A, 0xD662, 0xC361, 0xD663, 0xC362,
+	0xD664, 0xC363, 0xD665, 0xC364, 0xD666, 0xC365, 0xD667, 0xC8B1,	0xD668, 0xC366, 0xD669, 0xC8B2, 0xD66A, 0xC367, 0xD66B, 0xC368,
+	0xD66C, 0xC369, 0xD66D, 0xC36A, 0xD66E, 0xC36B, 0xD66F, 0xC36C,	0xD670, 0xC8B3, 0xD671, 0xC8B4, 0xD672, 0xC36D, 0xD673, 0xC36E,
+	0xD674, 0xC8B5, 0xD675, 0xC36F, 0xD676, 0xC370, 0xD677, 0xC371,	0xD678, 0xC372, 0xD679, 0xC373, 0xD67A, 0xC374, 0xD67B, 0xC375,
+	0xD67C, 0xC376, 0xD67D, 0xC377, 0xD67E, 0xC378, 0xD67F, 0xC379,	0xD680, 0xC37A, 0xD681, 0xC381, 0xD682, 0xC382, 0xD683, 0xC8B6,
+	0xD684, 0xC383, 0xD685, 0xC8B7, 0xD686, 0xC384, 0xD687, 0xC385,	0xD688, 0xC386, 0xD689, 0xC387, 0xD68A, 0xC388, 0xD68B, 0xC389,
+	0xD68C, 0xC8B8, 0xD68D, 0xC8B9, 0xD68E, 0xC38A, 0xD68F, 0xC38B,	0xD690, 0xC8BA, 0xD691, 0xC38C, 0xD692, 0xC38D, 0xD693, 0xC38E,
+	0xD694, 0xC8BB, 0xD695, 0xC38F, 0xD696, 0xC390, 0xD697, 0xC391,	0xD698, 0xC392, 0xD699, 0xC393, 0xD69A, 0xC394, 0xD69B, 0xC395,
+	0xD69C, 0xC396, 0xD69D, 0xC8BC, 0xD69E, 0xC397, 0xD69F, 0xC8BD,	0xD6A0, 0xC398, 0xD6A1, 0xC8BE, 0xD6A2, 0xC399, 0xD6A3, 0xC39A,
+	0xD6A4, 0xC39B, 0xD6A5, 0xC39C, 0xD6A6, 0xC39D, 0xD6A7, 0xC39E,	0xD6A8, 0xC8BF, 0xD6A9, 0xC39F, 0xD6AA, 0xC3A0, 0xD6AB, 0xC441,
+	0xD6AC, 0xC8C0, 0xD6AD, 0xC442, 0xD6AE, 0xC443, 0xD6AF, 0xC444,	0xD6B0, 0xC8C1, 0xD6B1, 0xC445, 0xD6B2, 0xC446, 0xD6B3, 0xC447,
+	0xD6B4, 0xC448, 0xD6B5, 0xC449, 0xD6B6, 0xC44A, 0xD6B7, 0xC44B,	0xD6B8, 0xC44C, 0xD6B9, 0xC8C2, 0xD6BA, 0xC44D, 0xD6BB, 0xC8C3,
+	0xD6BC, 0xC44E, 0xD6BD, 0xC44F, 0xD6BE, 0xC450, 0xD6BF, 0xC451,	0xD6C0, 0xC452, 0xD6C1, 0xC453, 0xD6C2, 0xC454, 0xD6C3, 0xC455,
+	0xD6C4, 0xC8C4, 0xD6C5, 0xC8C5, 0xD6C6, 0xC456, 0xD6C7, 0xC457,	0xD6C8, 0xC8C6, 0xD6C9, 0xC458, 0xD6CA, 0xC459, 0xD6CB, 0xC45A,
+	0xD6CC, 0xC8C7, 0xD6CD, 0xC461, 0xD6CE, 0xC462, 0xD6CF, 0xC463,	0xD6D0, 0xC464, 0xD6D1, 0xC8C8, 0xD6D2, 0xC465, 0xD6D3, 0xC466,
+	0xD6D4, 0xC8C9, 0xD6D5, 0xC467, 0xD6D6, 0xC468, 0xD6D7, 0xC8CA,	0xD6D8, 0xC469, 0xD6D9, 0xC8CB, 0xD6DA, 0xC46A, 0xD6DB, 0xC46B,
+	0xD6DC, 0xC46C, 0xD6DD, 0xC46D, 0xD6DE, 0xC46E, 0xD6DF, 0xC46F,	0xD6E0, 0xC8CC, 0xD6E1, 0xC470, 0xD6E2, 0xC471, 0xD6E3, 0xC472,
+	0xD6E4, 0xC8CD, 0xD6E5, 0xC473, 0xD6E6, 0xC474, 0xD6E7, 0xC475,	0xD6E8, 0xC8CE, 0xD6E9, 0xC476, 0xD6EA, 0xC477, 0xD6EB, 0xC478,
+	0xD6EC, 0xC479, 0xD6ED, 0xC47A, 0xD6EE, 0xC481, 0xD6EF, 0xC482,	0xD6F0, 0xC8CF, 0xD6F1, 0xC483, 0xD6F2, 0xC484, 0xD6F3, 0xC485,
+	0xD6F4, 0xC486, 0xD6F5, 0xC8D0, 0xD6F6, 0xC487, 0xD6F7, 0xC488,	0xD6F8, 0xC489, 0xD6F9, 0xC48A, 0xD6FA, 0xC48B, 0xD6FB, 0xC48C,
+	0xD6FC, 0xC8D1, 0xD6FD, 0xC8D2, 0xD6FE, 0xC48D, 0xD6FF, 0xC48E,	0xD700, 0xC8D3, 0xD701, 0xC48F, 0xD702, 0xC490, 0xD703, 0xC491,
+	0xD704, 0xC8D4, 0xD705, 0xC492, 0xD706, 0xC493, 0xD707, 0xC494,	0xD708, 0xC495, 0xD709, 0xC496, 0xD70A, 0xC497, 0xD70B, 0xC498,
+	0xD70C, 0xC499, 0xD70D, 0xC49A, 0xD70E, 0xC49B, 0xD70F, 0xC49C,	0xD710, 0xC49D, 0xD711, 0xC8D5, 0xD712, 0xC49E, 0xD713, 0xC49F,
+	0xD714, 0xC4A0, 0xD715, 0xC541, 0xD716, 0xC542, 0xD717, 0xC543,	0xD718, 0xC8D6, 0xD719, 0xC8D7, 0xD71A, 0xC544, 0xD71B, 0xC545,
+	0xD71C, 0xC8D8, 0xD71D, 0xC546, 0xD71E, 0xC547, 0xD71F, 0xC548,	0xD720, 0xC8D9, 0xD721, 0xC549, 0xD722, 0xC54A, 0xD723, 0xC54B,
+	0xD724, 0xC54C, 0xD725, 0xC54D, 0xD726, 0xC54E, 0xD727, 0xC54F,	0xD728, 0xC8DA, 0xD729, 0xC8DB, 0xD72A, 0xC550, 0xD72B, 0xC8DC,
+	0xD72C, 0xC551, 0xD72D, 0xC8DD, 0xD72E, 0xC552, 0xD72F, 0xC553,	0xD730, 0xC554, 0xD731, 0xC555, 0xD732, 0xC556, 0xD733, 0xC557,
+	0xD734, 0xC8DE, 0xD735, 0xC8DF, 0xD736, 0xC558, 0xD737, 0xC559,	0xD738, 0xC8E0, 0xD739, 0xC55A, 0xD73A, 0xC561, 0xD73B, 0xC562,
+	0xD73C, 0xC8E1, 0xD73D, 0xC563, 0xD73E, 0xC564, 0xD73F, 0xC565,	0xD740, 0xC566, 0xD741, 0xC567, 0xD742, 0xC568, 0xD743, 0xC569,
+	0xD744, 0xC8E2, 0xD745, 0xC56A, 0xD746, 0xC56B, 0xD747, 0xC8E3,	0xD748, 0xC56C, 0xD749, 0xC8E4, 0xD74A, 0xC56D, 0xD74B, 0xC56E,
+	0xD74C, 0xC56F, 0xD74D, 0xC570, 0xD74E, 0xC571, 0xD74F, 0xC572,	0xD750, 0xC8E5, 0xD751, 0xC8E6, 0xD752, 0xC573, 0xD753, 0xC574,
+	0xD754, 0xC8E7, 0xD755, 0xC575, 0xD756, 0xC8E8, 0xD757, 0xC8E9,	0xD758, 0xC8EA, 0xD759, 0xC8EB, 0xD75A, 0xC576, 0xD75B, 0xC577,
+	0xD75C, 0xC578, 0xD75D, 0xC579, 0xD75E, 0xC57A, 0xD75F, 0xC581,	0xD760, 0xC8EC, 0xD761, 0xC8ED, 0xD762, 0xC582, 0xD763, 0xC8EE,
+	0xD764, 0xC583, 0xD765, 0xC8EF, 0xD766, 0xC584, 0xD767, 0xC585,	0xD768, 0xC586, 0xD769, 0xC8F0, 0xD76A, 0xC587, 0xD76B, 0xC588,
+	0xD76C, 0xC8F1, 0xD76D, 0xC589, 0xD76E, 0xC58A, 0xD76F, 0xC58B,	0xD770, 0xC8F2, 0xD771, 0xC58C, 0xD772, 0xC58D, 0xD773, 0xC58E,
+	0xD774, 0xC8F3, 0xD775, 0xC58F, 0xD776, 0xC590, 0xD777, 0xC591,	0xD778, 0xC592, 0xD779, 0xC593, 0xD77A, 0xC594, 0xD77B, 0xC595,
+	0xD77C, 0xC8F4, 0xD77D, 0xC8F5, 0xD77E, 0xC596, 0xD77F, 0xC597,	0xD780, 0xC598, 0xD781, 0xC8F6, 0xD782, 0xC599, 0xD783, 0xC59A,
+	0xD784, 0xC59B, 0xD785, 0xC59C, 0xD786, 0xC59D, 0xD787, 0xC59E,	0xD788, 0xC8F7, 0xD789, 0xC8F8, 0xD78A, 0xC59F, 0xD78B, 0xC5A0,
+	0xD78C, 0xC8F9, 0xD78D, 0xC641, 0xD78E, 0xC642, 0xD78F, 0xC643,	0xD790, 0xC8FA, 0xD791, 0xC644, 0xD792, 0xC645, 0xD793, 0xC646,
+	0xD794, 0xC647, 0xD795, 0xC648, 0xD796, 0xC649, 0xD797, 0xC64A,	0xD798, 0xC8FB, 0xD799, 0xC8FC, 0xD79A, 0xC64B, 0xD79B, 0xC8FD,
+	0xD79C, 0xC64C, 0xD79D, 0xC8FE, 0xD79E, 0xC64D, 0xD79F, 0xC64E,	0xD7A0, 0xC64F, 0xD7A1, 0xC650, 0xD7A2, 0xC651, 0xD7A3, 0xC652,
+	0xF900, 0xCBD0, 0xF901, 0xCBD6, 0xF902, 0xCBE7, 0xF903, 0xCDCF,	0xF904, 0xCDE8, 0xF905, 0xCEAD, 0xF906, 0xCFFB, 0xF907, 0xD0A2,
+	0xF908, 0xD0B8, 0xF909, 0xD0D0, 0xF90A, 0xD0DD, 0xF90B, 0xD1D4,	0xF90C, 0xD1D5, 0xF90D, 0xD1D8, 0xF90E, 0xD1DB, 0xF90F, 0xD1DC,
+	0xF910, 0xD1DD, 0xF911, 0xD1DE, 0xF912, 0xD1DF, 0xF913, 0xD1E0,	0xF914, 0xD1E2, 0xF915, 0xD1E3, 0xF916, 0xD1E4, 0xF917, 0xD1E5,
+	0xF918, 0xD1E6, 0xF919, 0xD1E8, 0xF91A, 0xD1E9, 0xF91B, 0xD1EA,	0xF91C, 0xD1EB, 0xF91D, 0xD1ED, 0xF91E, 0xD1EF, 0xF91F, 0xD1F0,
+	0xF920, 0xD1F2, 0xF921, 0xD1F6, 0xF922, 0xD1FA, 0xF923, 0xD1FC,	0xF924, 0xD1FD, 0xF925, 0xD1FE, 0xF926, 0xD2A2, 0xF927, 0xD2A3,
+	0xF928, 0xD2A7, 0xF929, 0xD2A8, 0xF92A, 0xD2A9, 0xF92B, 0xD2AA,	0xF92C, 0xD2AB, 0xF92D, 0xD2AD, 0xF92E, 0xD2B2, 0xF92F, 0xD2BE,
+	0xF930, 0xD2C2, 0xF931, 0xD2C3, 0xF932, 0xD2C4, 0xF933, 0xD2C6,	0xF934, 0xD2C7, 0xF935, 0xD2C8, 0xF936, 0xD2C9, 0xF937, 0xD2CA,
+	0xF938, 0xD2CB, 0xF939, 0xD2CD, 0xF93A, 0xD2CE, 0xF93B, 0xD2CF,	0xF93C, 0xD2D0, 0xF93D, 0xD2D1, 0xF93E, 0xD2D2, 0xF93F, 0xD2D3,
+	0xF940, 0xD2D4, 0xF941, 0xD2D5, 0xF942, 0xD2D6, 0xF943, 0xD2D7,	0xF944, 0xD2D9, 0xF945, 0xD2DA, 0xF946, 0xD2DE, 0xF947, 0xD2DF,
+	0xF948, 0xD2E1, 0xF949, 0xD2E2, 0xF94A, 0xD2E4, 0xF94B, 0xD2E5,	0xF94C, 0xD2E6, 0xF94D, 0xD2E7, 0xF94E, 0xD2E8, 0xF94F, 0xD2E9,
+	0xF950, 0xD2EA, 0xF951, 0xD2EB, 0xF952, 0xD2F0, 0xF953, 0xD2F1,	0xF954, 0xD2F2, 0xF955, 0xD2F3, 0xF956, 0xD2F4, 0xF957, 0xD2F5,
+	0xF958, 0xD2F7, 0xF959, 0xD2F8, 0xF95A, 0xD4E6, 0xF95B, 0xD4FC,	0xF95C, 0xD5A5, 0xF95D, 0xD5AB, 0xF95E, 0xD5AE, 0xF95F, 0xD6B8,
+	0xF960, 0xD6CD, 0xF961, 0xD7CB, 0xF962, 0xD7E4, 0xF963, 0xDBC5,	0xF964, 0xDBE4, 0xF965, 0xDCA5, 0xF966, 0xDDA5, 0xF967, 0xDDD5,
+	0xF968, 0xDDF4, 0xF969, 0xDEFC, 0xF96A, 0xDEFE, 0xF96B, 0xDFB3,	0xF96C, 0xDFE1, 0xF96D, 0xDFE8, 0xF96E, 0xE0F1, 0xF96F, 0xE1AD,
+	0xF970, 0xE1ED, 0xF971, 0xE3F5, 0xF972, 0xE4A1, 0xF973, 0xE4A9,	0xF974, 0xE5AE, 0xF975, 0xE5B1, 0xF976, 0xE5B2, 0xF977, 0xE5B9,
+	0xF978, 0xE5BB, 0xF979, 0xE5BC, 0xF97A, 0xE5C4, 0xF97B, 0xE5CE,	0xF97C, 0xE5D0, 0xF97D, 0xE5D2, 0xF97E, 0xE5D6, 0xF97F, 0xE5FA,
+	0xF980, 0xE5FB, 0xF981, 0xE5FC, 0xF982, 0xE5FE, 0xF983, 0xE6A1,	0xF984, 0xE6A4, 0xF985, 0xE6A7, 0xF986, 0xE6AD, 0xF987, 0xE6AF,
+	0xF988, 0xE6B0, 0xF989, 0xE6B1, 0xF98A, 0xE6B3, 0xF98B, 0xE6B7,	0xF98C, 0xE6B8, 0xF98D, 0xE6BC, 0xF98E, 0xE6C4, 0xF98F, 0xE6C6,
+	0xF990, 0xE6C7, 0xF991, 0xE6CA, 0xF992, 0xE6D2, 0xF993, 0xE6D6,	0xF994, 0xE6D9, 0xF995, 0xE6DC, 0xF996, 0xE6DF, 0xF997, 0xE6E1,
+	0xF998, 0xE6E4, 0xF999, 0xE6E5, 0xF99A, 0xE6E6, 0xF99B, 0xE6E8,	0xF99C, 0xE6EA, 0xF99D, 0xE6EB, 0xF99E, 0xE6EC, 0xF99F, 0xE6EF,
+	0xF9A0, 0xE6F1, 0xF9A1, 0xE6F2, 0xF9A2, 0xE6F5, 0xF9A3, 0xE6F6,	0xF9A4, 0xE6F7, 0xF9A5, 0xE6F9, 0xF9A6, 0xE7A1, 0xF9A7, 0xE7A6,
+	0xF9A8, 0xE7A9, 0xF9A9, 0xE7AA, 0xF9AA, 0xE7AC, 0xF9AB, 0xE7AD,	0xF9AC, 0xE7B0, 0xF9AD, 0xE7BF, 0xF9AE, 0xE7C1, 0xF9AF, 0xE7C6,
+	0xF9B0, 0xE7C7, 0xF9B1, 0xE7CB, 0xF9B2, 0xE7CD, 0xF9B3, 0xE7CF,	0xF9B4, 0xE7D0, 0xF9B5, 0xE7D3, 0xF9B6, 0xE7DF, 0xF9B7, 0xE7E4,
+	0xF9B8, 0xE7E6, 0xF9B9, 0xE7F7, 0xF9BA, 0xE8E7, 0xF9BB, 0xE8E8,	0xF9BC, 0xE8F0, 0xF9BD, 0xE8F1, 0xF9BE, 0xE8F7, 0xF9BF, 0xE8F9,
+	0xF9C0, 0xE8FB, 0xF9C1, 0xE8FE, 0xF9C2, 0xE9A7, 0xF9C3, 0xE9AC,	0xF9C4, 0xE9CC, 0xF9C5, 0xE9F7, 0xF9C6, 0xEAC1, 0xF9C7, 0xEAE5,
+	0xF9C8, 0xEAF4, 0xF9C9, 0xEAF7, 0xF9CA, 0xEAFC, 0xF9CB, 0xEAFE,	0xF9CC, 0xEBA4, 0xF9CD, 0xEBA7, 0xF9CE, 0xEBA9, 0xF9CF, 0xEBAA,
+	0xF9D0, 0xEBBA, 0xF9D1, 0xEBBB, 0xF9D2, 0xEBBD, 0xF9D3, 0xEBC1,	0xF9D4, 0xEBC2, 0xF9D5, 0xEBC6, 0xF9D6, 0xEBC7, 0xF9D7, 0xEBCC,
+	0xF9D8, 0xEBCF, 0xF9D9, 0xEBD0, 0xF9DA, 0xEBD1, 0xF9DB, 0xEBD2,	0xF9DC, 0xEBD8, 0xF9DD, 0xECA6, 0xF9DE, 0xECA7, 0xF9DF, 0xECAA,
+	0xF9E0, 0xECAF, 0xF9E1, 0xECB0, 0xF9E2, 0xECB1, 0xF9E3, 0xECB2,	0xF9E4, 0xECB5, 0xF9E5, 0xECB8, 0xF9E6, 0xECBA, 0xF9E7, 0xECC0,
+	0xF9E8, 0xECC1, 0xF9E9, 0xECC5, 0xF9EA, 0xECC6, 0xF9EB, 0xECC9,	0xF9EC, 0xECCA, 0xF9ED, 0xECD5, 0xF9EE, 0xECDD, 0xF9EF, 0xECDE,
+	0xF9F0, 0xECE1, 0xF9F1, 0xECE4, 0xF9F2, 0xECE7, 0xF9F3, 0xECE8,	0xF9F4, 0xECF7, 0xF9F5, 0xECF8, 0xF9F6, 0xECFA, 0xF9F7, 0xEDA1,
+	0xF9F8, 0xEDA2, 0xF9F9, 0xEDA3, 0xF9FA, 0xEDEE, 0xF9FB, 0xEEDB,	0xF9FC, 0xF2BD, 0xF9FD, 0xF2FA, 0xF9FE, 0xF3B1, 0xF9FF, 0xF4A7,
+	0xFA00, 0xF4EE, 0xFA01, 0xF6F4, 0xFA02, 0xF6F6, 0xFA03, 0xF7B8,	0xFA04, 0xF7C8, 0xFA05, 0xF7D3, 0xFA06, 0xF8DB, 0xFA07, 0xF8F0,
+	0xFA08, 0xFAA1, 0xFA09, 0xFAA2, 0xFA0A, 0xFAE6, 0xFA0B, 0xFCA9,	0xFF01, 0xA3A1, 0xFF02, 0xA3A2, 0xFF03, 0xA3A3, 0xFF04, 0xA3A4,
+	0xFF05, 0xA3A5, 0xFF06, 0xA3A6, 0xFF07, 0xA3A7, 0xFF08, 0xA3A8,	0xFF09, 0xA3A9, 0xFF0A, 0xA3AA, 0xFF0B, 0xA3AB, 0xFF0C, 0xA3AC,
+	0xFF0D, 0xA3AD, 0xFF0E, 0xA3AE, 0xFF0F, 0xA3AF, 0xFF10, 0xA3B0,	0xFF11, 0xA3B1, 0xFF12, 0xA3B2, 0xFF13, 0xA3B3, 0xFF14, 0xA3B4,
+	0xFF15, 0xA3B5, 0xFF16, 0xA3B6, 0xFF17, 0xA3B7, 0xFF18, 0xA3B8,	0xFF19, 0xA3B9, 0xFF1A, 0xA3BA, 0xFF1B, 0xA3BB, 0xFF1C, 0xA3BC,
+	0xFF1D, 0xA3BD, 0xFF1E, 0xA3BE, 0xFF1F, 0xA3BF, 0xFF20, 0xA3C0,	0xFF21, 0xA3C1, 0xFF22, 0xA3C2, 0xFF23, 0xA3C3, 0xFF24, 0xA3C4,
+	0xFF25, 0xA3C5, 0xFF26, 0xA3C6, 0xFF27, 0xA3C7, 0xFF28, 0xA3C8,	0xFF29, 0xA3C9, 0xFF2A, 0xA3CA, 0xFF2B, 0xA3CB, 0xFF2C, 0xA3CC,
+	0xFF2D, 0xA3CD, 0xFF2E, 0xA3CE, 0xFF2F, 0xA3CF, 0xFF30, 0xA3D0,	0xFF31, 0xA3D1, 0xFF32, 0xA3D2, 0xFF33, 0xA3D3, 0xFF34, 0xA3D4,
+	0xFF35, 0xA3D5, 0xFF36, 0xA3D6, 0xFF37, 0xA3D7, 0xFF38, 0xA3D8,	0xFF39, 0xA3D9, 0xFF3A, 0xA3DA, 0xFF3B, 0xA3DB, 0xFF3C, 0xA1AC,
+	0xFF3D, 0xA3DD, 0xFF3E, 0xA3DE, 0xFF3F, 0xA3DF, 0xFF40, 0xA3E0,	0xFF41, 0xA3E1, 0xFF42, 0xA3E2, 0xFF43, 0xA3E3, 0xFF44, 0xA3E4,
+	0xFF45, 0xA3E5, 0xFF46, 0xA3E6, 0xFF47, 0xA3E7, 0xFF48, 0xA3E8,	0xFF49, 0xA3E9, 0xFF4A, 0xA3EA, 0xFF4B, 0xA3EB, 0xFF4C, 0xA3EC,
+	0xFF4D, 0xA3ED, 0xFF4E, 0xA3EE, 0xFF4F, 0xA3EF, 0xFF50, 0xA3F0,	0xFF51, 0xA3F1, 0xFF52, 0xA3F2, 0xFF53, 0xA3F3, 0xFF54, 0xA3F4,
+	0xFF55, 0xA3F5, 0xFF56, 0xA3F6, 0xFF57, 0xA3F7, 0xFF58, 0xA3F8,	0xFF59, 0xA3F9, 0xFF5A, 0xA3FA, 0xFF5B, 0xA3FB, 0xFF5C, 0xA3FC,
+	0xFF5D, 0xA3FD, 0xFF5E, 0xA2A6, 0xFFE0, 0xA1CB, 0xFFE1, 0xA1CC,	0xFFE2, 0xA1FE, 0xFFE3, 0xA3FE, 0xFFE5, 0xA1CD, 0xFFE6, 0xA3DC,
+	0, 0
+};
+
+static const WCHAR oem2uni949[] = {	/* Korean --> Unicode pairs */
+	0x8141, 0xAC02, 0x8142, 0xAC03, 0x8143, 0xAC05, 0x8144, 0xAC06,	0x8145, 0xAC0B, 0x8146, 0xAC0C, 0x8147, 0xAC0D, 0x8148, 0xAC0E,
+	0x8149, 0xAC0F, 0x814A, 0xAC18, 0x814B, 0xAC1E, 0x814C, 0xAC1F,	0x814D, 0xAC21, 0x814E, 0xAC22, 0x814F, 0xAC23, 0x8150, 0xAC25,
+	0x8151, 0xAC26, 0x8152, 0xAC27, 0x8153, 0xAC28, 0x8154, 0xAC29,	0x8155, 0xAC2A, 0x8156, 0xAC2B, 0x8157, 0xAC2E, 0x8158, 0xAC32,
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+	0x8549, 0xAFCC, 0x854A, 0xAFCF, 0x854B, 0xAFD0, 0x854C, 0xAFD1,	0x854D, 0xAFD2, 0x854E, 0xAFD3, 0x854F, 0xAFD5, 0x8550, 0xAFD6,
+	0x8551, 0xAFD7, 0x8552, 0xAFD8, 0x8553, 0xAFD9, 0x8554, 0xAFDA,	0x8555, 0xAFDB, 0x8556, 0xAFDD, 0x8557, 0xAFDE, 0x8558, 0xAFDF,
+	0x8559, 0xAFE0, 0x855A, 0xAFE1, 0x8561, 0xAFE2, 0x8562, 0xAFE3,	0x8563, 0xAFE4, 0x8564, 0xAFE5, 0x8565, 0xAFE6, 0x8566, 0xAFE7,
+	0x8567, 0xAFEA, 0x8568, 0xAFEB, 0x8569, 0xAFEC, 0x856A, 0xAFED,	0x856B, 0xAFEE, 0x856C, 0xAFEF, 0x856D, 0xAFF2, 0x856E, 0xAFF3,
+	0x856F, 0xAFF5, 0x8570, 0xAFF6, 0x8571, 0xAFF7, 0x8572, 0xAFF9,	0x8573, 0xAFFA, 0x8574, 0xAFFB, 0x8575, 0xAFFC, 0x8576, 0xAFFD,
+	0x8577, 0xAFFE, 0x8578, 0xAFFF, 0x8579, 0xB002, 0x857A, 0xB003,	0x8581, 0xB005, 0x8582, 0xB006, 0x8583, 0xB007, 0x8584, 0xB008,
+	0x8585, 0xB009, 0x8586, 0xB00A, 0x8587, 0xB00B, 0x8588, 0xB00D,	0x8589, 0xB00E, 0x858A, 0xB00F, 0x858B, 0xB011, 0x858C, 0xB012,
+	0x858D, 0xB013, 0x858E, 0xB015, 0x858F, 0xB016, 0x8590, 0xB017,	0x8591, 0xB018, 0x8592, 0xB019, 0x8593, 0xB01A, 0x8594, 0xB01B,
+	0x8595, 0xB01E, 0x8596, 0xB01F, 0x8597, 0xB020, 0x8598, 0xB021,	0x8599, 0xB022, 0x859A, 0xB023, 0x859B, 0xB024, 0x859C, 0xB025,
+	0x859D, 0xB026, 0x859E, 0xB027, 0x859F, 0xB029, 0x85A0, 0xB02A,	0x85A1, 0xB02B, 0x85A2, 0xB02C, 0x85A3, 0xB02D, 0x85A4, 0xB02E,
+	0x85A5, 0xB02F, 0x85A6, 0xB030, 0x85A7, 0xB031, 0x85A8, 0xB032,	0x85A9, 0xB033, 0x85AA, 0xB034, 0x85AB, 0xB035, 0x85AC, 0xB036,
+	0x85AD, 0xB037, 0x85AE, 0xB038, 0x85AF, 0xB039, 0x85B0, 0xB03A,	0x85B1, 0xB03B, 0x85B2, 0xB03C, 0x85B3, 0xB03D, 0x85B4, 0xB03E,
+	0x85B5, 0xB03F, 0x85B6, 0xB040, 0x85B7, 0xB041, 0x85B8, 0xB042,	0x85B9, 0xB043, 0x85BA, 0xB046, 0x85BB, 0xB047, 0x85BC, 0xB049,
+	0x85BD, 0xB04B, 0x85BE, 0xB04D, 0x85BF, 0xB04F, 0x85C0, 0xB050,	0x85C1, 0xB051, 0x85C2, 0xB052, 0x85C3, 0xB056, 0x85C4, 0xB058,
+	0x85C5, 0xB05A, 0x85C6, 0xB05B, 0x85C7, 0xB05C, 0x85C8, 0xB05E,	0x85C9, 0xB05F, 0x85CA, 0xB060, 0x85CB, 0xB061, 0x85CC, 0xB062,
+	0x85CD, 0xB063, 0x85CE, 0xB064, 0x85CF, 0xB065, 0x85D0, 0xB066,	0x85D1, 0xB067, 0x85D2, 0xB068, 0x85D3, 0xB069, 0x85D4, 0xB06A,
+	0x85D5, 0xB06B, 0x85D6, 0xB06C, 0x85D7, 0xB06D, 0x85D8, 0xB06E,	0x85D9, 0xB06F, 0x85DA, 0xB070, 0x85DB, 0xB071, 0x85DC, 0xB072,
+	0x85DD, 0xB073, 0x85DE, 0xB074, 0x85DF, 0xB075, 0x85E0, 0xB076,	0x85E1, 0xB077, 0x85E2, 0xB078, 0x85E3, 0xB079, 0x85E4, 0xB07A,
+	0x85E5, 0xB07B, 0x85E6, 0xB07E, 0x85E7, 0xB07F, 0x85E8, 0xB081,	0x85E9, 0xB082, 0x85EA, 0xB083, 0x85EB, 0xB085, 0x85EC, 0xB086,
+	0x85ED, 0xB087, 0x85EE, 0xB088, 0x85EF, 0xB089, 0x85F0, 0xB08A,	0x85F1, 0xB08B, 0x85F2, 0xB08E, 0x85F3, 0xB090, 0x85F4, 0xB092,
+	0x85F5, 0xB093, 0x85F6, 0xB094, 0x85F7, 0xB095, 0x85F8, 0xB096,	0x85F9, 0xB097, 0x85FA, 0xB09B, 0x85FB, 0xB09D, 0x85FC, 0xB09E,
+	0x85FD, 0xB0A3, 0x85FE, 0xB0A4, 0x8641, 0xB0A5, 0x8642, 0xB0A6,	0x8643, 0xB0A7, 0x8644, 0xB0AA, 0x8645, 0xB0B0, 0x8646, 0xB0B2,
+	0x8647, 0xB0B6, 0x8648, 0xB0B7, 0x8649, 0xB0B9, 0x864A, 0xB0BA,	0x864B, 0xB0BB, 0x864C, 0xB0BD, 0x864D, 0xB0BE, 0x864E, 0xB0BF,
+	0x864F, 0xB0C0, 0x8650, 0xB0C1, 0x8651, 0xB0C2, 0x8652, 0xB0C3,	0x8653, 0xB0C6, 0x8654, 0xB0CA, 0x8655, 0xB0CB, 0x8656, 0xB0CC,
+	0x8657, 0xB0CD, 0x8658, 0xB0CE, 0x8659, 0xB0CF, 0x865A, 0xB0D2,	0x8661, 0xB0D3, 0x8662, 0xB0D5, 0x8663, 0xB0D6, 0x8664, 0xB0D7,
+	0x8665, 0xB0D9, 0x8666, 0xB0DA, 0x8667, 0xB0DB, 0x8668, 0xB0DC,	0x8669, 0xB0DD, 0x866A, 0xB0DE, 0x866B, 0xB0DF, 0x866C, 0xB0E1,
+	0x866D, 0xB0E2, 0x866E, 0xB0E3, 0x866F, 0xB0E4, 0x8670, 0xB0E6,	0x8671, 0xB0E7, 0x8672, 0xB0E8, 0x8673, 0xB0E9, 0x8674, 0xB0EA,
+	0x8675, 0xB0EB, 0x8676, 0xB0EC, 0x8677, 0xB0ED, 0x8678, 0xB0EE,	0x8679, 0xB0EF, 0x867A, 0xB0F0, 0x8681, 0xB0F1, 0x8682, 0xB0F2,
+	0x8683, 0xB0F3, 0x8684, 0xB0F4, 0x8685, 0xB0F5, 0x8686, 0xB0F6,	0x8687, 0xB0F7, 0x8688, 0xB0F8, 0x8689, 0xB0F9, 0x868A, 0xB0FA,
+	0x868B, 0xB0FB, 0x868C, 0xB0FC, 0x868D, 0xB0FD, 0x868E, 0xB0FE,	0x868F, 0xB0FF, 0x8690, 0xB100, 0x8691, 0xB101, 0x8692, 0xB102,
+	0x8693, 0xB103, 0x8694, 0xB104, 0x8695, 0xB105, 0x8696, 0xB106,	0x8697, 0xB107, 0x8698, 0xB10A, 0x8699, 0xB10D, 0x869A, 0xB10E,
+	0x869B, 0xB10F, 0x869C, 0xB111, 0x869D, 0xB114, 0x869E, 0xB115,	0x869F, 0xB116, 0x86A0, 0xB117, 0x86A1, 0xB11A, 0x86A2, 0xB11E,
+	0x86A3, 0xB11F, 0x86A4, 0xB120, 0x86A5, 0xB121, 0x86A6, 0xB122,	0x86A7, 0xB126, 0x86A8, 0xB127, 0x86A9, 0xB129, 0x86AA, 0xB12A,
+	0x86AB, 0xB12B, 0x86AC, 0xB12D, 0x86AD, 0xB12E, 0x86AE, 0xB12F,	0x86AF, 0xB130, 0x86B0, 0xB131, 0x86B1, 0xB132, 0x86B2, 0xB133,
+	0x86B3, 0xB136, 0x86B4, 0xB13A, 0x86B5, 0xB13B, 0x86B6, 0xB13C,	0x86B7, 0xB13D, 0x86B8, 0xB13E, 0x86B9, 0xB13F, 0x86BA, 0xB142,
+	0x86BB, 0xB143, 0x86BC, 0xB145, 0x86BD, 0xB146, 0x86BE, 0xB147,	0x86BF, 0xB149, 0x86C0, 0xB14A, 0x86C1, 0xB14B, 0x86C2, 0xB14C,
+	0x86C3, 0xB14D, 0x86C4, 0xB14E, 0x86C5, 0xB14F, 0x86C6, 0xB152,	0x86C7, 0xB153, 0x86C8, 0xB156, 0x86C9, 0xB157, 0x86CA, 0xB159,
+	0x86CB, 0xB15A, 0x86CC, 0xB15B, 0x86CD, 0xB15D, 0x86CE, 0xB15E,	0x86CF, 0xB15F, 0x86D0, 0xB161, 0x86D1, 0xB162, 0x86D2, 0xB163,
+	0x86D3, 0xB164, 0x86D4, 0xB165, 0x86D5, 0xB166, 0x86D6, 0xB167,	0x86D7, 0xB168, 0x86D8, 0xB169, 0x86D9, 0xB16A, 0x86DA, 0xB16B,
+	0x86DB, 0xB16C, 0x86DC, 0xB16D, 0x86DD, 0xB16E, 0x86DE, 0xB16F,	0x86DF, 0xB170, 0x86E0, 0xB171, 0x86E1, 0xB172, 0x86E2, 0xB173,
+	0x86E3, 0xB174, 0x86E4, 0xB175, 0x86E5, 0xB176, 0x86E6, 0xB177,	0x86E7, 0xB17A, 0x86E8, 0xB17B, 0x86E9, 0xB17D, 0x86EA, 0xB17E,
+	0x86EB, 0xB17F, 0x86EC, 0xB181, 0x86ED, 0xB183, 0x86EE, 0xB184,	0x86EF, 0xB185, 0x86F0, 0xB186, 0x86F1, 0xB187, 0x86F2, 0xB18A,
+	0x86F3, 0xB18C, 0x86F4, 0xB18E, 0x86F5, 0xB18F, 0x86F6, 0xB190,	0x86F7, 0xB191, 0x86F8, 0xB195, 0x86F9, 0xB196, 0x86FA, 0xB197,
+	0x86FB, 0xB199, 0x86FC, 0xB19A, 0x86FD, 0xB19B, 0x86FE, 0xB19D,	0x8741, 0xB19E, 0x8742, 0xB19F, 0x8743, 0xB1A0, 0x8744, 0xB1A1,
+	0x8745, 0xB1A2, 0x8746, 0xB1A3, 0x8747, 0xB1A4, 0x8748, 0xB1A5,	0x8749, 0xB1A6, 0x874A, 0xB1A7, 0x874B, 0xB1A9, 0x874C, 0xB1AA,
+	0x874D, 0xB1AB, 0x874E, 0xB1AC, 0x874F, 0xB1AD, 0x8750, 0xB1AE,	0x8751, 0xB1AF, 0x8752, 0xB1B0, 0x8753, 0xB1B1, 0x8754, 0xB1B2,
+	0x8755, 0xB1B3, 0x8756, 0xB1B4, 0x8757, 0xB1B5, 0x8758, 0xB1B6,	0x8759, 0xB1B7, 0x875A, 0xB1B8, 0x8761, 0xB1B9, 0x8762, 0xB1BA,
+	0x8763, 0xB1BB, 0x8764, 0xB1BC, 0x8765, 0xB1BD, 0x8766, 0xB1BE,	0x8767, 0xB1BF, 0x8768, 0xB1C0, 0x8769, 0xB1C1, 0x876A, 0xB1C2,
+	0x876B, 0xB1C3, 0x876C, 0xB1C4, 0x876D, 0xB1C5, 0x876E, 0xB1C6,	0x876F, 0xB1C7, 0x8770, 0xB1C8, 0x8771, 0xB1C9, 0x8772, 0xB1CA,
+	0x8773, 0xB1CB, 0x8774, 0xB1CD, 0x8775, 0xB1CE, 0x8776, 0xB1CF,	0x8777, 0xB1D1, 0x8778, 0xB1D2, 0x8779, 0xB1D3, 0x877A, 0xB1D5,
+	0x8781, 0xB1D6, 0x8782, 0xB1D7, 0x8783, 0xB1D8, 0x8784, 0xB1D9,	0x8785, 0xB1DA, 0x8786, 0xB1DB, 0x8787, 0xB1DE, 0x8788, 0xB1E0,
+	0x8789, 0xB1E1, 0x878A, 0xB1E2, 0x878B, 0xB1E3, 0x878C, 0xB1E4,	0x878D, 0xB1E5, 0x878E, 0xB1E6, 0x878F, 0xB1E7, 0x8790, 0xB1EA,
+	0x8791, 0xB1EB, 0x8792, 0xB1ED, 0x8793, 0xB1EE, 0x8794, 0xB1EF,	0x8795, 0xB1F1, 0x8796, 0xB1F2, 0x8797, 0xB1F3, 0x8798, 0xB1F4,
+	0x8799, 0xB1F5, 0x879A, 0xB1F6, 0x879B, 0xB1F7, 0x879C, 0xB1F8,	0x879D, 0xB1FA, 0x879E, 0xB1FC, 0x879F, 0xB1FE, 0x87A0, 0xB1FF,
+	0x87A1, 0xB200, 0x87A2, 0xB201, 0x87A3, 0xB202, 0x87A4, 0xB203,	0x87A5, 0xB206, 0x87A6, 0xB207, 0x87A7, 0xB209, 0x87A8, 0xB20A,
+	0x87A9, 0xB20D, 0x87AA, 0xB20E, 0x87AB, 0xB20F, 0x87AC, 0xB210,	0x87AD, 0xB211, 0x87AE, 0xB212, 0x87AF, 0xB213, 0x87B0, 0xB216,
+	0x87B1, 0xB218, 0x87B2, 0xB21A, 0x87B3, 0xB21B, 0x87B4, 0xB21C,	0x87B5, 0xB21D, 0x87B6, 0xB21E, 0x87B7, 0xB21F, 0x87B8, 0xB221,
+	0x87B9, 0xB222, 0x87BA, 0xB223, 0x87BB, 0xB224, 0x87BC, 0xB225,	0x87BD, 0xB226, 0x87BE, 0xB227, 0x87BF, 0xB228, 0x87C0, 0xB229,
+	0x87C1, 0xB22A, 0x87C2, 0xB22B, 0x87C3, 0xB22C, 0x87C4, 0xB22D,	0x87C5, 0xB22E, 0x87C6, 0xB22F, 0x87C7, 0xB230, 0x87C8, 0xB231,
+	0x87C9, 0xB232, 0x87CA, 0xB233, 0x87CB, 0xB235, 0x87CC, 0xB236,	0x87CD, 0xB237, 0x87CE, 0xB238, 0x87CF, 0xB239, 0x87D0, 0xB23A,
+	0x87D1, 0xB23B, 0x87D2, 0xB23D, 0x87D3, 0xB23E, 0x87D4, 0xB23F,	0x87D5, 0xB240, 0x87D6, 0xB241, 0x87D7, 0xB242, 0x87D8, 0xB243,
+	0x87D9, 0xB244, 0x87DA, 0xB245, 0x87DB, 0xB246, 0x87DC, 0xB247,	0x87DD, 0xB248, 0x87DE, 0xB249, 0x87DF, 0xB24A, 0x87E0, 0xB24B,
+	0x87E1, 0xB24C, 0x87E2, 0xB24D, 0x87E3, 0xB24E, 0x87E4, 0xB24F,	0x87E5, 0xB250, 0x87E6, 0xB251, 0x87E7, 0xB252, 0x87E8, 0xB253,
+	0x87E9, 0xB254, 0x87EA, 0xB255, 0x87EB, 0xB256, 0x87EC, 0xB257,	0x87ED, 0xB259, 0x87EE, 0xB25A, 0x87EF, 0xB25B, 0x87F0, 0xB25D,
+	0x87F1, 0xB25E, 0x87F2, 0xB25F, 0x87F3, 0xB261, 0x87F4, 0xB262,	0x87F5, 0xB263, 0x87F6, 0xB264, 0x87F7, 0xB265, 0x87F8, 0xB266,
+	0x87F9, 0xB267, 0x87FA, 0xB26A, 0x87FB, 0xB26B, 0x87FC, 0xB26C,	0x87FD, 0xB26D, 0x87FE, 0xB26E, 0x8841, 0xB26F, 0x8842, 0xB270,
+	0x8843, 0xB271, 0x8844, 0xB272, 0x8845, 0xB273, 0x8846, 0xB276,	0x8847, 0xB277, 0x8848, 0xB278, 0x8849, 0xB279, 0x884A, 0xB27A,
+	0x884B, 0xB27B, 0x884C, 0xB27D, 0x884D, 0xB27E, 0x884E, 0xB27F,	0x884F, 0xB280, 0x8850, 0xB281, 0x8851, 0xB282, 0x8852, 0xB283,
+	0x8853, 0xB286, 0x8854, 0xB287, 0x8855, 0xB288, 0x8856, 0xB28A,	0x8857, 0xB28B, 0x8858, 0xB28C, 0x8859, 0xB28D, 0x885A, 0xB28E,
+	0x8861, 0xB28F, 0x8862, 0xB292, 0x8863, 0xB293, 0x8864, 0xB295,	0x8865, 0xB296, 0x8866, 0xB297, 0x8867, 0xB29B, 0x8868, 0xB29C,
+	0x8869, 0xB29D, 0x886A, 0xB29E, 0x886B, 0xB29F, 0x886C, 0xB2A2,	0x886D, 0xB2A4, 0x886E, 0xB2A7, 0x886F, 0xB2A8, 0x8870, 0xB2A9,
+	0x8871, 0xB2AB, 0x8872, 0xB2AD, 0x8873, 0xB2AE, 0x8874, 0xB2AF,	0x8875, 0xB2B1, 0x8876, 0xB2B2, 0x8877, 0xB2B3, 0x8878, 0xB2B5,
+	0x8879, 0xB2B6, 0x887A, 0xB2B7, 0x8881, 0xB2B8, 0x8882, 0xB2B9,	0x8883, 0xB2BA, 0x8884, 0xB2BB, 0x8885, 0xB2BC, 0x8886, 0xB2BD,
+	0x8887, 0xB2BE, 0x8888, 0xB2BF, 0x8889, 0xB2C0, 0x888A, 0xB2C1,	0x888B, 0xB2C2, 0x888C, 0xB2C3, 0x888D, 0xB2C4, 0x888E, 0xB2C5,
+	0x888F, 0xB2C6, 0x8890, 0xB2C7, 0x8891, 0xB2CA, 0x8892, 0xB2CB,	0x8893, 0xB2CD, 0x8894, 0xB2CE, 0x8895, 0xB2CF, 0x8896, 0xB2D1,
+	0x8897, 0xB2D3, 0x8898, 0xB2D4, 0x8899, 0xB2D5, 0x889A, 0xB2D6,	0x889B, 0xB2D7, 0x889C, 0xB2DA, 0x889D, 0xB2DC, 0x889E, 0xB2DE,
+	0x889F, 0xB2DF, 0x88A0, 0xB2E0, 0x88A1, 0xB2E1, 0x88A2, 0xB2E3,	0x88A3, 0xB2E7, 0x88A4, 0xB2E9, 0x88A5, 0xB2EA, 0x88A6, 0xB2F0,
+	0x88A7, 0xB2F1, 0x88A8, 0xB2F2, 0x88A9, 0xB2F6, 0x88AA, 0xB2FC,	0x88AB, 0xB2FD, 0x88AC, 0xB2FE, 0x88AD, 0xB302, 0x88AE, 0xB303,
+	0x88AF, 0xB305, 0x88B0, 0xB306, 0x88B1, 0xB307, 0x88B2, 0xB309,	0x88B3, 0xB30A, 0x88B4, 0xB30B, 0x88B5, 0xB30C, 0x88B6, 0xB30D,
+	0x88B7, 0xB30E, 0x88B8, 0xB30F, 0x88B9, 0xB312, 0x88BA, 0xB316,	0x88BB, 0xB317, 0x88BC, 0xB318, 0x88BD, 0xB319, 0x88BE, 0xB31A,
+	0x88BF, 0xB31B, 0x88C0, 0xB31D, 0x88C1, 0xB31E, 0x88C2, 0xB31F,	0x88C3, 0xB320, 0x88C4, 0xB321, 0x88C5, 0xB322, 0x88C6, 0xB323,
+	0x88C7, 0xB324, 0x88C8, 0xB325, 0x88C9, 0xB326, 0x88CA, 0xB327,	0x88CB, 0xB328, 0x88CC, 0xB329, 0x88CD, 0xB32A, 0x88CE, 0xB32B,
+	0x88CF, 0xB32C, 0x88D0, 0xB32D, 0x88D1, 0xB32E, 0x88D2, 0xB32F,	0x88D3, 0xB330, 0x88D4, 0xB331, 0x88D5, 0xB332, 0x88D6, 0xB333,
+	0x88D7, 0xB334, 0x88D8, 0xB335, 0x88D9, 0xB336, 0x88DA, 0xB337,	0x88DB, 0xB338, 0x88DC, 0xB339, 0x88DD, 0xB33A, 0x88DE, 0xB33B,
+	0x88DF, 0xB33C, 0x88E0, 0xB33D, 0x88E1, 0xB33E, 0x88E2, 0xB33F,	0x88E3, 0xB340, 0x88E4, 0xB341, 0x88E5, 0xB342, 0x88E6, 0xB343,
+	0x88E7, 0xB344, 0x88E8, 0xB345, 0x88E9, 0xB346, 0x88EA, 0xB347,	0x88EB, 0xB348, 0x88EC, 0xB349, 0x88ED, 0xB34A, 0x88EE, 0xB34B,
+	0x88EF, 0xB34C, 0x88F0, 0xB34D, 0x88F1, 0xB34E, 0x88F2, 0xB34F,	0x88F3, 0xB350, 0x88F4, 0xB351, 0x88F5, 0xB352, 0x88F6, 0xB353,
+	0x88F7, 0xB357, 0x88F8, 0xB359, 0x88F9, 0xB35A, 0x88FA, 0xB35D,	0x88FB, 0xB360, 0x88FC, 0xB361, 0x88FD, 0xB362, 0x88FE, 0xB363,
+	0x8941, 0xB366, 0x8942, 0xB368, 0x8943, 0xB36A, 0x8944, 0xB36C,	0x8945, 0xB36D, 0x8946, 0xB36F, 0x8947, 0xB372, 0x8948, 0xB373,
+	0x8949, 0xB375, 0x894A, 0xB376, 0x894B, 0xB377, 0x894C, 0xB379,	0x894D, 0xB37A, 0x894E, 0xB37B, 0x894F, 0xB37C, 0x8950, 0xB37D,
+	0x8951, 0xB37E, 0x8952, 0xB37F, 0x8953, 0xB382, 0x8954, 0xB386,	0x8955, 0xB387, 0x8956, 0xB388, 0x8957, 0xB389, 0x8958, 0xB38A,
+	0x8959, 0xB38B, 0x895A, 0xB38D, 0x8961, 0xB38E, 0x8962, 0xB38F,	0x8963, 0xB391, 0x8964, 0xB392, 0x8965, 0xB393, 0x8966, 0xB395,
+	0x8967, 0xB396, 0x8968, 0xB397, 0x8969, 0xB398, 0x896A, 0xB399,	0x896B, 0xB39A, 0x896C, 0xB39B, 0x896D, 0xB39C, 0x896E, 0xB39D,
+	0x896F, 0xB39E, 0x8970, 0xB39F, 0x8971, 0xB3A2, 0x8972, 0xB3A3,	0x8973, 0xB3A4, 0x8974, 0xB3A5, 0x8975, 0xB3A6, 0x8976, 0xB3A7,
+	0x8977, 0xB3A9, 0x8978, 0xB3AA, 0x8979, 0xB3AB, 0x897A, 0xB3AD,	0x8981, 0xB3AE, 0x8982, 0xB3AF, 0x8983, 0xB3B0, 0x8984, 0xB3B1,
+	0x8985, 0xB3B2, 0x8986, 0xB3B3, 0x8987, 0xB3B4, 0x8988, 0xB3B5,	0x8989, 0xB3B6, 0x898A, 0xB3B7, 0x898B, 0xB3B8, 0x898C, 0xB3B9,
+	0x898D, 0xB3BA, 0x898E, 0xB3BB, 0x898F, 0xB3BC, 0x8990, 0xB3BD,	0x8991, 0xB3BE, 0x8992, 0xB3BF, 0x8993, 0xB3C0, 0x8994, 0xB3C1,
+	0x8995, 0xB3C2, 0x8996, 0xB3C3, 0x8997, 0xB3C6, 0x8998, 0xB3C7,	0x8999, 0xB3C9, 0x899A, 0xB3CA, 0x899B, 0xB3CD, 0x899C, 0xB3CF,
+	0x899D, 0xB3D1, 0x899E, 0xB3D2, 0x899F, 0xB3D3, 0x89A0, 0xB3D6,	0x89A1, 0xB3D8, 0x89A2, 0xB3DA, 0x89A3, 0xB3DC, 0x89A4, 0xB3DE,
+	0x89A5, 0xB3DF, 0x89A6, 0xB3E1, 0x89A7, 0xB3E2, 0x89A8, 0xB3E3,	0x89A9, 0xB3E5, 0x89AA, 0xB3E6, 0x89AB, 0xB3E7, 0x89AC, 0xB3E9,
+	0x89AD, 0xB3EA, 0x89AE, 0xB3EB, 0x89AF, 0xB3EC, 0x89B0, 0xB3ED,	0x89B1, 0xB3EE, 0x89B2, 0xB3EF, 0x89B3, 0xB3F0, 0x89B4, 0xB3F1,
+	0x89B5, 0xB3F2, 0x89B6, 0xB3F3, 0x89B7, 0xB3F4, 0x89B8, 0xB3F5,	0x89B9, 0xB3F6, 0x89BA, 0xB3F7, 0x89BB, 0xB3F8, 0x89BC, 0xB3F9,
+	0x89BD, 0xB3FA, 0x89BE, 0xB3FB, 0x89BF, 0xB3FD, 0x89C0, 0xB3FE,	0x89C1, 0xB3FF, 0x89C2, 0xB400, 0x89C3, 0xB401, 0x89C4, 0xB402,
+	0x89C5, 0xB403, 0x89C6, 0xB404, 0x89C7, 0xB405, 0x89C8, 0xB406,	0x89C9, 0xB407, 0x89CA, 0xB408, 0x89CB, 0xB409, 0x89CC, 0xB40A,
+	0x89CD, 0xB40B, 0x89CE, 0xB40C, 0x89CF, 0xB40D, 0x89D0, 0xB40E,	0x89D1, 0xB40F, 0x89D2, 0xB411, 0x89D3, 0xB412, 0x89D4, 0xB413,
+	0x89D5, 0xB414, 0x89D6, 0xB415, 0x89D7, 0xB416, 0x89D8, 0xB417,	0x89D9, 0xB419, 0x89DA, 0xB41A, 0x89DB, 0xB41B, 0x89DC, 0xB41D,
+	0x89DD, 0xB41E, 0x89DE, 0xB41F, 0x89DF, 0xB421, 0x89E0, 0xB422,	0x89E1, 0xB423, 0x89E2, 0xB424, 0x89E3, 0xB425, 0x89E4, 0xB426,
+	0x89E5, 0xB427, 0x89E6, 0xB42A, 0x89E7, 0xB42C, 0x89E8, 0xB42D,	0x89E9, 0xB42E, 0x89EA, 0xB42F, 0x89EB, 0xB430, 0x89EC, 0xB431,
+	0x89ED, 0xB432, 0x89EE, 0xB433, 0x89EF, 0xB435, 0x89F0, 0xB436,	0x89F1, 0xB437, 0x89F2, 0xB438, 0x89F3, 0xB439, 0x89F4, 0xB43A,
+	0x89F5, 0xB43B, 0x89F6, 0xB43C, 0x89F7, 0xB43D, 0x89F8, 0xB43E,	0x89F9, 0xB43F, 0x89FA, 0xB440, 0x89FB, 0xB441, 0x89FC, 0xB442,
+	0x89FD, 0xB443, 0x89FE, 0xB444, 0x8A41, 0xB445, 0x8A42, 0xB446,	0x8A43, 0xB447, 0x8A44, 0xB448, 0x8A45, 0xB449, 0x8A46, 0xB44A,
+	0x8A47, 0xB44B, 0x8A48, 0xB44C, 0x8A49, 0xB44D, 0x8A4A, 0xB44E,	0x8A4B, 0xB44F, 0x8A4C, 0xB452, 0x8A4D, 0xB453, 0x8A4E, 0xB455,
+	0x8A4F, 0xB456, 0x8A50, 0xB457, 0x8A51, 0xB459, 0x8A52, 0xB45A,	0x8A53, 0xB45B, 0x8A54, 0xB45C, 0x8A55, 0xB45D, 0x8A56, 0xB45E,
+	0x8A57, 0xB45F, 0x8A58, 0xB462, 0x8A59, 0xB464, 0x8A5A, 0xB466,	0x8A61, 0xB467, 0x8A62, 0xB468, 0x8A63, 0xB469, 0x8A64, 0xB46A,
+	0x8A65, 0xB46B, 0x8A66, 0xB46D, 0x8A67, 0xB46E, 0x8A68, 0xB46F,	0x8A69, 0xB470, 0x8A6A, 0xB471, 0x8A6B, 0xB472, 0x8A6C, 0xB473,
+	0x8A6D, 0xB474, 0x8A6E, 0xB475, 0x8A6F, 0xB476, 0x8A70, 0xB477,	0x8A71, 0xB478, 0x8A72, 0xB479, 0x8A73, 0xB47A, 0x8A74, 0xB47B,
+	0x8A75, 0xB47C, 0x8A76, 0xB47D, 0x8A77, 0xB47E, 0x8A78, 0xB47F,	0x8A79, 0xB481, 0x8A7A, 0xB482, 0x8A81, 0xB483, 0x8A82, 0xB484,
+	0x8A83, 0xB485, 0x8A84, 0xB486, 0x8A85, 0xB487, 0x8A86, 0xB489,	0x8A87, 0xB48A, 0x8A88, 0xB48B, 0x8A89, 0xB48C, 0x8A8A, 0xB48D,
+	0x8A8B, 0xB48E, 0x8A8C, 0xB48F, 0x8A8D, 0xB490, 0x8A8E, 0xB491,	0x8A8F, 0xB492, 0x8A90, 0xB493, 0x8A91, 0xB494, 0x8A92, 0xB495,
+	0x8A93, 0xB496, 0x8A94, 0xB497, 0x8A95, 0xB498, 0x8A96, 0xB499,	0x8A97, 0xB49A, 0x8A98, 0xB49B, 0x8A99, 0xB49C, 0x8A9A, 0xB49E,
+	0x8A9B, 0xB49F, 0x8A9C, 0xB4A0, 0x8A9D, 0xB4A1, 0x8A9E, 0xB4A2,	0x8A9F, 0xB4A3, 0x8AA0, 0xB4A5, 0x8AA1, 0xB4A6, 0x8AA2, 0xB4A7,
+	0x8AA3, 0xB4A9, 0x8AA4, 0xB4AA, 0x8AA5, 0xB4AB, 0x8AA6, 0xB4AD,	0x8AA7, 0xB4AE, 0x8AA8, 0xB4AF, 0x8AA9, 0xB4B0, 0x8AAA, 0xB4B1,
+	0x8AAB, 0xB4B2, 0x8AAC, 0xB4B3, 0x8AAD, 0xB4B4, 0x8AAE, 0xB4B6,	0x8AAF, 0xB4B8, 0x8AB0, 0xB4BA, 0x8AB1, 0xB4BB, 0x8AB2, 0xB4BC,
+	0x8AB3, 0xB4BD, 0x8AB4, 0xB4BE, 0x8AB5, 0xB4BF, 0x8AB6, 0xB4C1,	0x8AB7, 0xB4C2, 0x8AB8, 0xB4C3, 0x8AB9, 0xB4C5, 0x8ABA, 0xB4C6,
+	0x8ABB, 0xB4C7, 0x8ABC, 0xB4C9, 0x8ABD, 0xB4CA, 0x8ABE, 0xB4CB,	0x8ABF, 0xB4CC, 0x8AC0, 0xB4CD, 0x8AC1, 0xB4CE, 0x8AC2, 0xB4CF,
+	0x8AC3, 0xB4D1, 0x8AC4, 0xB4D2, 0x8AC5, 0xB4D3, 0x8AC6, 0xB4D4,	0x8AC7, 0xB4D6, 0x8AC8, 0xB4D7, 0x8AC9, 0xB4D8, 0x8ACA, 0xB4D9,
+	0x8ACB, 0xB4DA, 0x8ACC, 0xB4DB, 0x8ACD, 0xB4DE, 0x8ACE, 0xB4DF,	0x8ACF, 0xB4E1, 0x8AD0, 0xB4E2, 0x8AD1, 0xB4E5, 0x8AD2, 0xB4E7,
+	0x8AD3, 0xB4E8, 0x8AD4, 0xB4E9, 0x8AD5, 0xB4EA, 0x8AD6, 0xB4EB,	0x8AD7, 0xB4EE, 0x8AD8, 0xB4F0, 0x8AD9, 0xB4F2, 0x8ADA, 0xB4F3,
+	0x8ADB, 0xB4F4, 0x8ADC, 0xB4F5, 0x8ADD, 0xB4F6, 0x8ADE, 0xB4F7,	0x8ADF, 0xB4F9, 0x8AE0, 0xB4FA, 0x8AE1, 0xB4FB, 0x8AE2, 0xB4FC,
+	0x8AE3, 0xB4FD, 0x8AE4, 0xB4FE, 0x8AE5, 0xB4FF, 0x8AE6, 0xB500,	0x8AE7, 0xB501, 0x8AE8, 0xB502, 0x8AE9, 0xB503, 0x8AEA, 0xB504,
+	0x8AEB, 0xB505, 0x8AEC, 0xB506, 0x8AED, 0xB507, 0x8AEE, 0xB508,	0x8AEF, 0xB509, 0x8AF0, 0xB50A, 0x8AF1, 0xB50B, 0x8AF2, 0xB50C,
+	0x8AF3, 0xB50D, 0x8AF4, 0xB50E, 0x8AF5, 0xB50F, 0x8AF6, 0xB510,	0x8AF7, 0xB511, 0x8AF8, 0xB512, 0x8AF9, 0xB513, 0x8AFA, 0xB516,
+	0x8AFB, 0xB517, 0x8AFC, 0xB519, 0x8AFD, 0xB51A, 0x8AFE, 0xB51D,	0x8B41, 0xB51E, 0x8B42, 0xB51F, 0x8B43, 0xB520, 0x8B44, 0xB521,
+	0x8B45, 0xB522, 0x8B46, 0xB523, 0x8B47, 0xB526, 0x8B48, 0xB52B,	0x8B49, 0xB52C, 0x8B4A, 0xB52D, 0x8B4B, 0xB52E, 0x8B4C, 0xB52F,
+	0x8B4D, 0xB532, 0x8B4E, 0xB533, 0x8B4F, 0xB535, 0x8B50, 0xB536,	0x8B51, 0xB537, 0x8B52, 0xB539, 0x8B53, 0xB53A, 0x8B54, 0xB53B,
+	0x8B55, 0xB53C, 0x8B56, 0xB53D, 0x8B57, 0xB53E, 0x8B58, 0xB53F,	0x8B59, 0xB542, 0x8B5A, 0xB546, 0x8B61, 0xB547, 0x8B62, 0xB548,
+	0x8B63, 0xB549, 0x8B64, 0xB54A, 0x8B65, 0xB54E, 0x8B66, 0xB54F,	0x8B67, 0xB551, 0x8B68, 0xB552, 0x8B69, 0xB553, 0x8B6A, 0xB555,
+	0x8B6B, 0xB556, 0x8B6C, 0xB557, 0x8B6D, 0xB558, 0x8B6E, 0xB559,	0x8B6F, 0xB55A, 0x8B70, 0xB55B, 0x8B71, 0xB55E, 0x8B72, 0xB562,
+	0x8B73, 0xB563, 0x8B74, 0xB564, 0x8B75, 0xB565, 0x8B76, 0xB566,	0x8B77, 0xB567, 0x8B78, 0xB568, 0x8B79, 0xB569, 0x8B7A, 0xB56A,
+	0x8B81, 0xB56B, 0x8B82, 0xB56C, 0x8B83, 0xB56D, 0x8B84, 0xB56E,	0x8B85, 0xB56F, 0x8B86, 0xB570, 0x8B87, 0xB571, 0x8B88, 0xB572,
+	0x8B89, 0xB573, 0x8B8A, 0xB574, 0x8B8B, 0xB575, 0x8B8C, 0xB576,	0x8B8D, 0xB577, 0x8B8E, 0xB578, 0x8B8F, 0xB579, 0x8B90, 0xB57A,
+	0x8B91, 0xB57B, 0x8B92, 0xB57C, 0x8B93, 0xB57D, 0x8B94, 0xB57E,	0x8B95, 0xB57F, 0x8B96, 0xB580, 0x8B97, 0xB581, 0x8B98, 0xB582,
+	0x8B99, 0xB583, 0x8B9A, 0xB584, 0x8B9B, 0xB585, 0x8B9C, 0xB586,	0x8B9D, 0xB587, 0x8B9E, 0xB588, 0x8B9F, 0xB589, 0x8BA0, 0xB58A,
+	0x8BA1, 0xB58B, 0x8BA2, 0xB58C, 0x8BA3, 0xB58D, 0x8BA4, 0xB58E,	0x8BA5, 0xB58F, 0x8BA6, 0xB590, 0x8BA7, 0xB591, 0x8BA8, 0xB592,
+	0x8BA9, 0xB593, 0x8BAA, 0xB594, 0x8BAB, 0xB595, 0x8BAC, 0xB596,	0x8BAD, 0xB597, 0x8BAE, 0xB598, 0x8BAF, 0xB599, 0x8BB0, 0xB59A,
+	0x8BB1, 0xB59B, 0x8BB2, 0xB59C, 0x8BB3, 0xB59D, 0x8BB4, 0xB59E,	0x8BB5, 0xB59F, 0x8BB6, 0xB5A2, 0x8BB7, 0xB5A3, 0x8BB8, 0xB5A5,
+	0x8BB9, 0xB5A6, 0x8BBA, 0xB5A7, 0x8BBB, 0xB5A9, 0x8BBC, 0xB5AC,	0x8BBD, 0xB5AD, 0x8BBE, 0xB5AE, 0x8BBF, 0xB5AF, 0x8BC0, 0xB5B2,
+	0x8BC1, 0xB5B6, 0x8BC2, 0xB5B7, 0x8BC3, 0xB5B8, 0x8BC4, 0xB5B9,	0x8BC5, 0xB5BA, 0x8BC6, 0xB5BE, 0x8BC7, 0xB5BF, 0x8BC8, 0xB5C1,
+	0x8BC9, 0xB5C2, 0x8BCA, 0xB5C3, 0x8BCB, 0xB5C5, 0x8BCC, 0xB5C6,	0x8BCD, 0xB5C7, 0x8BCE, 0xB5C8, 0x8BCF, 0xB5C9, 0x8BD0, 0xB5CA,
+	0x8BD1, 0xB5CB, 0x8BD2, 0xB5CE, 0x8BD3, 0xB5D2, 0x8BD4, 0xB5D3,	0x8BD5, 0xB5D4, 0x8BD6, 0xB5D5, 0x8BD7, 0xB5D6, 0x8BD8, 0xB5D7,
+	0x8BD9, 0xB5D9, 0x8BDA, 0xB5DA, 0x8BDB, 0xB5DB, 0x8BDC, 0xB5DC,	0x8BDD, 0xB5DD, 0x8BDE, 0xB5DE, 0x8BDF, 0xB5DF, 0x8BE0, 0xB5E0,
+	0x8BE1, 0xB5E1, 0x8BE2, 0xB5E2, 0x8BE3, 0xB5E3, 0x8BE4, 0xB5E4,	0x8BE5, 0xB5E5, 0x8BE6, 0xB5E6, 0x8BE7, 0xB5E7, 0x8BE8, 0xB5E8,
+	0x8BE9, 0xB5E9, 0x8BEA, 0xB5EA, 0x8BEB, 0xB5EB, 0x8BEC, 0xB5ED,	0x8BED, 0xB5EE, 0x8BEE, 0xB5EF, 0x8BEF, 0xB5F0, 0x8BF0, 0xB5F1,
+	0x8BF1, 0xB5F2, 0x8BF2, 0xB5F3, 0x8BF3, 0xB5F4, 0x8BF4, 0xB5F5,	0x8BF5, 0xB5F6, 0x8BF6, 0xB5F7, 0x8BF7, 0xB5F8, 0x8BF8, 0xB5F9,
+	0x8BF9, 0xB5FA, 0x8BFA, 0xB5FB, 0x8BFB, 0xB5FC, 0x8BFC, 0xB5FD,	0x8BFD, 0xB5FE, 0x8BFE, 0xB5FF, 0x8C41, 0xB600, 0x8C42, 0xB601,
+	0x8C43, 0xB602, 0x8C44, 0xB603, 0x8C45, 0xB604, 0x8C46, 0xB605,	0x8C47, 0xB606, 0x8C48, 0xB607, 0x8C49, 0xB608, 0x8C4A, 0xB609,
+	0x8C4B, 0xB60A, 0x8C4C, 0xB60B, 0x8C4D, 0xB60C, 0x8C4E, 0xB60D,	0x8C4F, 0xB60E, 0x8C50, 0xB60F, 0x8C51, 0xB612, 0x8C52, 0xB613,
+	0x8C53, 0xB615, 0x8C54, 0xB616, 0x8C55, 0xB617, 0x8C56, 0xB619,	0x8C57, 0xB61A, 0x8C58, 0xB61B, 0x8C59, 0xB61C, 0x8C5A, 0xB61D,
+	0x8C61, 0xB61E, 0x8C62, 0xB61F, 0x8C63, 0xB620, 0x8C64, 0xB621,	0x8C65, 0xB622, 0x8C66, 0xB623, 0x8C67, 0xB624, 0x8C68, 0xB626,
+	0x8C69, 0xB627, 0x8C6A, 0xB628, 0x8C6B, 0xB629, 0x8C6C, 0xB62A,	0x8C6D, 0xB62B, 0x8C6E, 0xB62D, 0x8C6F, 0xB62E, 0x8C70, 0xB62F,
+	0x8C71, 0xB630, 0x8C72, 0xB631, 0x8C73, 0xB632, 0x8C74, 0xB633,	0x8C75, 0xB635, 0x8C76, 0xB636, 0x8C77, 0xB637, 0x8C78, 0xB638,
+	0x8C79, 0xB639, 0x8C7A, 0xB63A, 0x8C81, 0xB63B, 0x8C82, 0xB63C,	0x8C83, 0xB63D, 0x8C84, 0xB63E, 0x8C85, 0xB63F, 0x8C86, 0xB640,
+	0x8C87, 0xB641, 0x8C88, 0xB642, 0x8C89, 0xB643, 0x8C8A, 0xB644,	0x8C8B, 0xB645, 0x8C8C, 0xB646, 0x8C8D, 0xB647, 0x8C8E, 0xB649,
+	0x8C8F, 0xB64A, 0x8C90, 0xB64B, 0x8C91, 0xB64C, 0x8C92, 0xB64D,	0x8C93, 0xB64E, 0x8C94, 0xB64F, 0x8C95, 0xB650, 0x8C96, 0xB651,
+	0x8C97, 0xB652, 0x8C98, 0xB653, 0x8C99, 0xB654, 0x8C9A, 0xB655,	0x8C9B, 0xB656, 0x8C9C, 0xB657, 0x8C9D, 0xB658, 0x8C9E, 0xB659,
+	0x8C9F, 0xB65A, 0x8CA0, 0xB65B, 0x8CA1, 0xB65C, 0x8CA2, 0xB65D,	0x8CA3, 0xB65E, 0x8CA4, 0xB65F, 0x8CA5, 0xB660, 0x8CA6, 0xB661,
+	0x8CA7, 0xB662, 0x8CA8, 0xB663, 0x8CA9, 0xB665, 0x8CAA, 0xB666,	0x8CAB, 0xB667, 0x8CAC, 0xB669, 0x8CAD, 0xB66A, 0x8CAE, 0xB66B,
+	0x8CAF, 0xB66C, 0x8CB0, 0xB66D, 0x8CB1, 0xB66E, 0x8CB2, 0xB66F,	0x8CB3, 0xB670, 0x8CB4, 0xB671, 0x8CB5, 0xB672, 0x8CB6, 0xB673,
+	0x8CB7, 0xB674, 0x8CB8, 0xB675, 0x8CB9, 0xB676, 0x8CBA, 0xB677,	0x8CBB, 0xB678, 0x8CBC, 0xB679, 0x8CBD, 0xB67A, 0x8CBE, 0xB67B,
+	0x8CBF, 0xB67C, 0x8CC0, 0xB67D, 0x8CC1, 0xB67E, 0x8CC2, 0xB67F,	0x8CC3, 0xB680, 0x8CC4, 0xB681, 0x8CC5, 0xB682, 0x8CC6, 0xB683,
+	0x8CC7, 0xB684, 0x8CC8, 0xB685, 0x8CC9, 0xB686, 0x8CCA, 0xB687,	0x8CCB, 0xB688, 0x8CCC, 0xB689, 0x8CCD, 0xB68A, 0x8CCE, 0xB68B,
+	0x8CCF, 0xB68C, 0x8CD0, 0xB68D, 0x8CD1, 0xB68E, 0x8CD2, 0xB68F,	0x8CD3, 0xB690, 0x8CD4, 0xB691, 0x8CD5, 0xB692, 0x8CD6, 0xB693,
+	0x8CD7, 0xB694, 0x8CD8, 0xB695, 0x8CD9, 0xB696, 0x8CDA, 0xB697,	0x8CDB, 0xB698, 0x8CDC, 0xB699, 0x8CDD, 0xB69A, 0x8CDE, 0xB69B,
+	0x8CDF, 0xB69E, 0x8CE0, 0xB69F, 0x8CE1, 0xB6A1, 0x8CE2, 0xB6A2,	0x8CE3, 0xB6A3, 0x8CE4, 0xB6A5, 0x8CE5, 0xB6A6, 0x8CE6, 0xB6A7,
+	0x8CE7, 0xB6A8, 0x8CE8, 0xB6A9, 0x8CE9, 0xB6AA, 0x8CEA, 0xB6AD,	0x8CEB, 0xB6AE, 0x8CEC, 0xB6AF, 0x8CED, 0xB6B0, 0x8CEE, 0xB6B2,
+	0x8CEF, 0xB6B3, 0x8CF0, 0xB6B4, 0x8CF1, 0xB6B5, 0x8CF2, 0xB6B6,	0x8CF3, 0xB6B7, 0x8CF4, 0xB6B8, 0x8CF5, 0xB6B9, 0x8CF6, 0xB6BA,
+	0x8CF7, 0xB6BB, 0x8CF8, 0xB6BC, 0x8CF9, 0xB6BD, 0x8CFA, 0xB6BE,	0x8CFB, 0xB6BF, 0x8CFC, 0xB6C0, 0x8CFD, 0xB6C1, 0x8CFE, 0xB6C2,
+	0x8D41, 0xB6C3, 0x8D42, 0xB6C4, 0x8D43, 0xB6C5, 0x8D44, 0xB6C6,	0x8D45, 0xB6C7, 0x8D46, 0xB6C8, 0x8D47, 0xB6C9, 0x8D48, 0xB6CA,
+	0x8D49, 0xB6CB, 0x8D4A, 0xB6CC, 0x8D4B, 0xB6CD, 0x8D4C, 0xB6CE,	0x8D4D, 0xB6CF, 0x8D4E, 0xB6D0, 0x8D4F, 0xB6D1, 0x8D50, 0xB6D2,
+	0x8D51, 0xB6D3, 0x8D52, 0xB6D5, 0x8D53, 0xB6D6, 0x8D54, 0xB6D7,	0x8D55, 0xB6D8, 0x8D56, 0xB6D9, 0x8D57, 0xB6DA, 0x8D58, 0xB6DB,
+	0x8D59, 0xB6DC, 0x8D5A, 0xB6DD, 0x8D61, 0xB6DE, 0x8D62, 0xB6DF,	0x8D63, 0xB6E0, 0x8D64, 0xB6E1, 0x8D65, 0xB6E2, 0x8D66, 0xB6E3,
+	0x8D67, 0xB6E4, 0x8D68, 0xB6E5, 0x8D69, 0xB6E6, 0x8D6A, 0xB6E7,	0x8D6B, 0xB6E8, 0x8D6C, 0xB6E9, 0x8D6D, 0xB6EA, 0x8D6E, 0xB6EB,
+	0x8D6F, 0xB6EC, 0x8D70, 0xB6ED, 0x8D71, 0xB6EE, 0x8D72, 0xB6EF,	0x8D73, 0xB6F1, 0x8D74, 0xB6F2, 0x8D75, 0xB6F3, 0x8D76, 0xB6F5,
+	0x8D77, 0xB6F6, 0x8D78, 0xB6F7, 0x8D79, 0xB6F9, 0x8D7A, 0xB6FA,	0x8D81, 0xB6FB, 0x8D82, 0xB6FC, 0x8D83, 0xB6FD, 0x8D84, 0xB6FE,
+	0x8D85, 0xB6FF, 0x8D86, 0xB702, 0x8D87, 0xB703, 0x8D88, 0xB704,	0x8D89, 0xB706, 0x8D8A, 0xB707, 0x8D8B, 0xB708, 0x8D8C, 0xB709,
+	0x8D8D, 0xB70A, 0x8D8E, 0xB70B, 0x8D8F, 0xB70C, 0x8D90, 0xB70D,	0x8D91, 0xB70E, 0x8D92, 0xB70F, 0x8D93, 0xB710, 0x8D94, 0xB711,
+	0x8D95, 0xB712, 0x8D96, 0xB713, 0x8D97, 0xB714, 0x8D98, 0xB715,	0x8D99, 0xB716, 0x8D9A, 0xB717, 0x8D9B, 0xB718, 0x8D9C, 0xB719,
+	0x8D9D, 0xB71A, 0x8D9E, 0xB71B, 0x8D9F, 0xB71C, 0x8DA0, 0xB71D,	0x8DA1, 0xB71E, 0x8DA2, 0xB71F, 0x8DA3, 0xB720, 0x8DA4, 0xB721,
+	0x8DA5, 0xB722, 0x8DA6, 0xB723, 0x8DA7, 0xB724, 0x8DA8, 0xB725,	0x8DA9, 0xB726, 0x8DAA, 0xB727, 0x8DAB, 0xB72A, 0x8DAC, 0xB72B,
+	0x8DAD, 0xB72D, 0x8DAE, 0xB72E, 0x8DAF, 0xB731, 0x8DB0, 0xB732,	0x8DB1, 0xB733, 0x8DB2, 0xB734, 0x8DB3, 0xB735, 0x8DB4, 0xB736,
+	0x8DB5, 0xB737, 0x8DB6, 0xB73A, 0x8DB7, 0xB73C, 0x8DB8, 0xB73D,	0x8DB9, 0xB73E, 0x8DBA, 0xB73F, 0x8DBB, 0xB740, 0x8DBC, 0xB741,
+	0x8DBD, 0xB742, 0x8DBE, 0xB743, 0x8DBF, 0xB745, 0x8DC0, 0xB746,	0x8DC1, 0xB747, 0x8DC2, 0xB749, 0x8DC3, 0xB74A, 0x8DC4, 0xB74B,
+	0x8DC5, 0xB74D, 0x8DC6, 0xB74E, 0x8DC7, 0xB74F, 0x8DC8, 0xB750,	0x8DC9, 0xB751, 0x8DCA, 0xB752, 0x8DCB, 0xB753, 0x8DCC, 0xB756,
+	0x8DCD, 0xB757, 0x8DCE, 0xB758, 0x8DCF, 0xB759, 0x8DD0, 0xB75A,	0x8DD1, 0xB75B, 0x8DD2, 0xB75C, 0x8DD3, 0xB75D, 0x8DD4, 0xB75E,
+	0x8DD5, 0xB75F, 0x8DD6, 0xB761, 0x8DD7, 0xB762, 0x8DD8, 0xB763,	0x8DD9, 0xB765, 0x8DDA, 0xB766, 0x8DDB, 0xB767, 0x8DDC, 0xB769,
+	0x8DDD, 0xB76A, 0x8DDE, 0xB76B, 0x8DDF, 0xB76C, 0x8DE0, 0xB76D,	0x8DE1, 0xB76E, 0x8DE2, 0xB76F, 0x8DE3, 0xB772, 0x8DE4, 0xB774,
+	0x8DE5, 0xB776, 0x8DE6, 0xB777, 0x8DE7, 0xB778, 0x8DE8, 0xB779,	0x8DE9, 0xB77A, 0x8DEA, 0xB77B, 0x8DEB, 0xB77E, 0x8DEC, 0xB77F,
+	0x8DED, 0xB781, 0x8DEE, 0xB782, 0x8DEF, 0xB783, 0x8DF0, 0xB785,	0x8DF1, 0xB786, 0x8DF2, 0xB787, 0x8DF3, 0xB788, 0x8DF4, 0xB789,
+	0x8DF5, 0xB78A, 0x8DF6, 0xB78B, 0x8DF7, 0xB78E, 0x8DF8, 0xB793,	0x8DF9, 0xB794, 0x8DFA, 0xB795, 0x8DFB, 0xB79A, 0x8DFC, 0xB79B,
+	0x8DFD, 0xB79D, 0x8DFE, 0xB79E, 0x8E41, 0xB79F, 0x8E42, 0xB7A1,	0x8E43, 0xB7A2, 0x8E44, 0xB7A3, 0x8E45, 0xB7A4, 0x8E46, 0xB7A5,
+	0x8E47, 0xB7A6, 0x8E48, 0xB7A7, 0x8E49, 0xB7AA, 0x8E4A, 0xB7AE,	0x8E4B, 0xB7AF, 0x8E4C, 0xB7B0, 0x8E4D, 0xB7B1, 0x8E4E, 0xB7B2,
+	0x8E4F, 0xB7B3, 0x8E50, 0xB7B6, 0x8E51, 0xB7B7, 0x8E52, 0xB7B9,	0x8E53, 0xB7BA, 0x8E54, 0xB7BB, 0x8E55, 0xB7BC, 0x8E56, 0xB7BD,
+	0x8E57, 0xB7BE, 0x8E58, 0xB7BF, 0x8E59, 0xB7C0, 0x8E5A, 0xB7C1,	0x8E61, 0xB7C2, 0x8E62, 0xB7C3, 0x8E63, 0xB7C4, 0x8E64, 0xB7C5,
+	0x8E65, 0xB7C6, 0x8E66, 0xB7C8, 0x8E67, 0xB7CA, 0x8E68, 0xB7CB,	0x8E69, 0xB7CC, 0x8E6A, 0xB7CD, 0x8E6B, 0xB7CE, 0x8E6C, 0xB7CF,
+	0x8E6D, 0xB7D0, 0x8E6E, 0xB7D1, 0x8E6F, 0xB7D2, 0x8E70, 0xB7D3,	0x8E71, 0xB7D4, 0x8E72, 0xB7D5, 0x8E73, 0xB7D6, 0x8E74, 0xB7D7,
+	0x8E75, 0xB7D8, 0x8E76, 0xB7D9, 0x8E77, 0xB7DA, 0x8E78, 0xB7DB,	0x8E79, 0xB7DC, 0x8E7A, 0xB7DD, 0x8E81, 0xB7DE, 0x8E82, 0xB7DF,
+	0x8E83, 0xB7E0, 0x8E84, 0xB7E1, 0x8E85, 0xB7E2, 0x8E86, 0xB7E3,	0x8E87, 0xB7E4, 0x8E88, 0xB7E5, 0x8E89, 0xB7E6, 0x8E8A, 0xB7E7,
+	0x8E8B, 0xB7E8, 0x8E8C, 0xB7E9, 0x8E8D, 0xB7EA, 0x8E8E, 0xB7EB,	0x8E8F, 0xB7EE, 0x8E90, 0xB7EF, 0x8E91, 0xB7F1, 0x8E92, 0xB7F2,
+	0x8E93, 0xB7F3, 0x8E94, 0xB7F5, 0x8E95, 0xB7F6, 0x8E96, 0xB7F7,	0x8E97, 0xB7F8, 0x8E98, 0xB7F9, 0x8E99, 0xB7FA, 0x8E9A, 0xB7FB,
+	0x8E9B, 0xB7FE, 0x8E9C, 0xB802, 0x8E9D, 0xB803, 0x8E9E, 0xB804,	0x8E9F, 0xB805, 0x8EA0, 0xB806, 0x8EA1, 0xB80A, 0x8EA2, 0xB80B,
+	0x8EA3, 0xB80D, 0x8EA4, 0xB80E, 0x8EA5, 0xB80F, 0x8EA6, 0xB811,	0x8EA7, 0xB812, 0x8EA8, 0xB813, 0x8EA9, 0xB814, 0x8EAA, 0xB815,
+	0x8EAB, 0xB816, 0x8EAC, 0xB817, 0x8EAD, 0xB81A, 0x8EAE, 0xB81C,	0x8EAF, 0xB81E, 0x8EB0, 0xB81F, 0x8EB1, 0xB820, 0x8EB2, 0xB821,
+	0x8EB3, 0xB822, 0x8EB4, 0xB823, 0x8EB5, 0xB826, 0x8EB6, 0xB827,	0x8EB7, 0xB829, 0x8EB8, 0xB82A, 0x8EB9, 0xB82B, 0x8EBA, 0xB82D,
+	0x8EBB, 0xB82E, 0x8EBC, 0xB82F, 0x8EBD, 0xB830, 0x8EBE, 0xB831,	0x8EBF, 0xB832, 0x8EC0, 0xB833, 0x8EC1, 0xB836, 0x8EC2, 0xB83A,
+	0x8EC3, 0xB83B, 0x8EC4, 0xB83C, 0x8EC5, 0xB83D, 0x8EC6, 0xB83E,	0x8EC7, 0xB83F, 0x8EC8, 0xB841, 0x8EC9, 0xB842, 0x8ECA, 0xB843,
+	0x8ECB, 0xB845, 0x8ECC, 0xB846, 0x8ECD, 0xB847, 0x8ECE, 0xB848,	0x8ECF, 0xB849, 0x8ED0, 0xB84A, 0x8ED1, 0xB84B, 0x8ED2, 0xB84C,
+	0x8ED3, 0xB84D, 0x8ED4, 0xB84E, 0x8ED5, 0xB84F, 0x8ED6, 0xB850,	0x8ED7, 0xB852, 0x8ED8, 0xB854, 0x8ED9, 0xB855, 0x8EDA, 0xB856,
+	0x8EDB, 0xB857, 0x8EDC, 0xB858, 0x8EDD, 0xB859, 0x8EDE, 0xB85A,	0x8EDF, 0xB85B, 0x8EE0, 0xB85E, 0x8EE1, 0xB85F, 0x8EE2, 0xB861,
+	0x8EE3, 0xB862, 0x8EE4, 0xB863, 0x8EE5, 0xB865, 0x8EE6, 0xB866,	0x8EE7, 0xB867, 0x8EE8, 0xB868, 0x8EE9, 0xB869, 0x8EEA, 0xB86A,
+	0x8EEB, 0xB86B, 0x8EEC, 0xB86E, 0x8EED, 0xB870, 0x8EEE, 0xB872,	0x8EEF, 0xB873, 0x8EF0, 0xB874, 0x8EF1, 0xB875, 0x8EF2, 0xB876,
+	0x8EF3, 0xB877, 0x8EF4, 0xB879, 0x8EF5, 0xB87A, 0x8EF6, 0xB87B,	0x8EF7, 0xB87D, 0x8EF8, 0xB87E, 0x8EF9, 0xB87F, 0x8EFA, 0xB880,
+	0x8EFB, 0xB881, 0x8EFC, 0xB882, 0x8EFD, 0xB883, 0x8EFE, 0xB884,	0x8F41, 0xB885, 0x8F42, 0xB886, 0x8F43, 0xB887, 0x8F44, 0xB888,
+	0x8F45, 0xB889, 0x8F46, 0xB88A, 0x8F47, 0xB88B, 0x8F48, 0xB88C,	0x8F49, 0xB88E, 0x8F4A, 0xB88F, 0x8F4B, 0xB890, 0x8F4C, 0xB891,
+	0x8F4D, 0xB892, 0x8F4E, 0xB893, 0x8F4F, 0xB894, 0x8F50, 0xB895,	0x8F51, 0xB896, 0x8F52, 0xB897, 0x8F53, 0xB898, 0x8F54, 0xB899,
+	0x8F55, 0xB89A, 0x8F56, 0xB89B, 0x8F57, 0xB89C, 0x8F58, 0xB89D,	0x8F59, 0xB89E, 0x8F5A, 0xB89F, 0x8F61, 0xB8A0, 0x8F62, 0xB8A1,
+	0x8F63, 0xB8A2, 0x8F64, 0xB8A3, 0x8F65, 0xB8A4, 0x8F66, 0xB8A5,	0x8F67, 0xB8A6, 0x8F68, 0xB8A7, 0x8F69, 0xB8A9, 0x8F6A, 0xB8AA,
+	0x8F6B, 0xB8AB, 0x8F6C, 0xB8AC, 0x8F6D, 0xB8AD, 0x8F6E, 0xB8AE,	0x8F6F, 0xB8AF, 0x8F70, 0xB8B1, 0x8F71, 0xB8B2, 0x8F72, 0xB8B3,
+	0x8F73, 0xB8B5, 0x8F74, 0xB8B6, 0x8F75, 0xB8B7, 0x8F76, 0xB8B9,	0x8F77, 0xB8BA, 0x8F78, 0xB8BB, 0x8F79, 0xB8BC, 0x8F7A, 0xB8BD,
+	0x8F81, 0xB8BE, 0x8F82, 0xB8BF, 0x8F83, 0xB8C2, 0x8F84, 0xB8C4,	0x8F85, 0xB8C6, 0x8F86, 0xB8C7, 0x8F87, 0xB8C8, 0x8F88, 0xB8C9,
+	0x8F89, 0xB8CA, 0x8F8A, 0xB8CB, 0x8F8B, 0xB8CD, 0x8F8C, 0xB8CE,	0x8F8D, 0xB8CF, 0x8F8E, 0xB8D1, 0x8F8F, 0xB8D2, 0x8F90, 0xB8D3,
+	0x8F91, 0xB8D5, 0x8F92, 0xB8D6, 0x8F93, 0xB8D7, 0x8F94, 0xB8D8,	0x8F95, 0xB8D9, 0x8F96, 0xB8DA, 0x8F97, 0xB8DB, 0x8F98, 0xB8DC,
+	0x8F99, 0xB8DE, 0x8F9A, 0xB8E0, 0x8F9B, 0xB8E2, 0x8F9C, 0xB8E3,	0x8F9D, 0xB8E4, 0x8F9E, 0xB8E5, 0x8F9F, 0xB8E6, 0x8FA0, 0xB8E7,
+	0x8FA1, 0xB8EA, 0x8FA2, 0xB8EB, 0x8FA3, 0xB8ED, 0x8FA4, 0xB8EE,	0x8FA5, 0xB8EF, 0x8FA6, 0xB8F1, 0x8FA7, 0xB8F2, 0x8FA8, 0xB8F3,
+	0x8FA9, 0xB8F4, 0x8FAA, 0xB8F5, 0x8FAB, 0xB8F6, 0x8FAC, 0xB8F7,	0x8FAD, 0xB8FA, 0x8FAE, 0xB8FC, 0x8FAF, 0xB8FE, 0x8FB0, 0xB8FF,
+	0x8FB1, 0xB900, 0x8FB2, 0xB901, 0x8FB3, 0xB902, 0x8FB4, 0xB903,	0x8FB5, 0xB905, 0x8FB6, 0xB906, 0x8FB7, 0xB907, 0x8FB8, 0xB908,
+	0x8FB9, 0xB909, 0x8FBA, 0xB90A, 0x8FBB, 0xB90B, 0x8FBC, 0xB90C,	0x8FBD, 0xB90D, 0x8FBE, 0xB90E, 0x8FBF, 0xB90F, 0x8FC0, 0xB910,
+	0x8FC1, 0xB911, 0x8FC2, 0xB912, 0x8FC3, 0xB913, 0x8FC4, 0xB914,	0x8FC5, 0xB915, 0x8FC6, 0xB916, 0x8FC7, 0xB917, 0x8FC8, 0xB919,
+	0x8FC9, 0xB91A, 0x8FCA, 0xB91B, 0x8FCB, 0xB91C, 0x8FCC, 0xB91D,	0x8FCD, 0xB91E, 0x8FCE, 0xB91F, 0x8FCF, 0xB921, 0x8FD0, 0xB922,
+	0x8FD1, 0xB923, 0x8FD2, 0xB924, 0x8FD3, 0xB925, 0x8FD4, 0xB926,	0x8FD5, 0xB927, 0x8FD6, 0xB928, 0x8FD7, 0xB929, 0x8FD8, 0xB92A,
+	0x8FD9, 0xB92B, 0x8FDA, 0xB92C, 0x8FDB, 0xB92D, 0x8FDC, 0xB92E,	0x8FDD, 0xB92F, 0x8FDE, 0xB930, 0x8FDF, 0xB931, 0x8FE0, 0xB932,
+	0x8FE1, 0xB933, 0x8FE2, 0xB934, 0x8FE3, 0xB935, 0x8FE4, 0xB936,	0x8FE5, 0xB937, 0x8FE6, 0xB938, 0x8FE7, 0xB939, 0x8FE8, 0xB93A,
+	0x8FE9, 0xB93B, 0x8FEA, 0xB93E, 0x8FEB, 0xB93F, 0x8FEC, 0xB941,	0x8FED, 0xB942, 0x8FEE, 0xB943, 0x8FEF, 0xB945, 0x8FF0, 0xB946,
+	0x8FF1, 0xB947, 0x8FF2, 0xB948, 0x8FF3, 0xB949, 0x8FF4, 0xB94A,	0x8FF5, 0xB94B, 0x8FF6, 0xB94D, 0x8FF7, 0xB94E, 0x8FF8, 0xB950,
+	0x8FF9, 0xB952, 0x8FFA, 0xB953, 0x8FFB, 0xB954, 0x8FFC, 0xB955,	0x8FFD, 0xB956, 0x8FFE, 0xB957, 0x9041, 0xB95A, 0x9042, 0xB95B,
+	0x9043, 0xB95D, 0x9044, 0xB95E, 0x9045, 0xB95F, 0x9046, 0xB961,	0x9047, 0xB962, 0x9048, 0xB963, 0x9049, 0xB964, 0x904A, 0xB965,
+	0x904B, 0xB966, 0x904C, 0xB967, 0x904D, 0xB96A, 0x904E, 0xB96C,	0x904F, 0xB96E, 0x9050, 0xB96F, 0x9051, 0xB970, 0x9052, 0xB971,
+	0x9053, 0xB972, 0x9054, 0xB973, 0x9055, 0xB976, 0x9056, 0xB977,	0x9057, 0xB979, 0x9058, 0xB97A, 0x9059, 0xB97B, 0x905A, 0xB97D,
+	0x9061, 0xB97E, 0x9062, 0xB97F, 0x9063, 0xB980, 0x9064, 0xB981,	0x9065, 0xB982, 0x9066, 0xB983, 0x9067, 0xB986, 0x9068, 0xB988,
+	0x9069, 0xB98B, 0x906A, 0xB98C, 0x906B, 0xB98F, 0x906C, 0xB990,	0x906D, 0xB991, 0x906E, 0xB992, 0x906F, 0xB993, 0x9070, 0xB994,
+	0x9071, 0xB995, 0x9072, 0xB996, 0x9073, 0xB997, 0x9074, 0xB998,	0x9075, 0xB999, 0x9076, 0xB99A, 0x9077, 0xB99B, 0x9078, 0xB99C,
+	0x9079, 0xB99D, 0x907A, 0xB99E, 0x9081, 0xB99F, 0x9082, 0xB9A0,	0x9083, 0xB9A1, 0x9084, 0xB9A2, 0x9085, 0xB9A3, 0x9086, 0xB9A4,
+	0x9087, 0xB9A5, 0x9088, 0xB9A6, 0x9089, 0xB9A7, 0x908A, 0xB9A8,	0x908B, 0xB9A9, 0x908C, 0xB9AA, 0x908D, 0xB9AB, 0x908E, 0xB9AE,
+	0x908F, 0xB9AF, 0x9090, 0xB9B1, 0x9091, 0xB9B2, 0x9092, 0xB9B3,	0x9093, 0xB9B5, 0x9094, 0xB9B6, 0x9095, 0xB9B7, 0x9096, 0xB9B8,
+	0x9097, 0xB9B9, 0x9098, 0xB9BA, 0x9099, 0xB9BB, 0x909A, 0xB9BE,	0x909B, 0xB9C0, 0x909C, 0xB9C2, 0x909D, 0xB9C3, 0x909E, 0xB9C4,
+	0x909F, 0xB9C5, 0x90A0, 0xB9C6, 0x90A1, 0xB9C7, 0x90A2, 0xB9CA,	0x90A3, 0xB9CB, 0x90A4, 0xB9CD, 0x90A5, 0xB9D3, 0x90A6, 0xB9D4,
+	0x90A7, 0xB9D5, 0x90A8, 0xB9D6, 0x90A9, 0xB9D7, 0x90AA, 0xB9DA,	0x90AB, 0xB9DC, 0x90AC, 0xB9DF, 0x90AD, 0xB9E0, 0x90AE, 0xB9E2,
+	0x90AF, 0xB9E6, 0x90B0, 0xB9E7, 0x90B1, 0xB9E9, 0x90B2, 0xB9EA,	0x90B3, 0xB9EB, 0x90B4, 0xB9ED, 0x90B5, 0xB9EE, 0x90B6, 0xB9EF,
+	0x90B7, 0xB9F0, 0x90B8, 0xB9F1, 0x90B9, 0xB9F2, 0x90BA, 0xB9F3,	0x90BB, 0xB9F6, 0x90BC, 0xB9FB, 0x90BD, 0xB9FC, 0x90BE, 0xB9FD,
+	0x90BF, 0xB9FE, 0x90C0, 0xB9FF, 0x90C1, 0xBA02, 0x90C2, 0xBA03,	0x90C3, 0xBA04, 0x90C4, 0xBA05, 0x90C5, 0xBA06, 0x90C6, 0xBA07,
+	0x90C7, 0xBA09, 0x90C8, 0xBA0A, 0x90C9, 0xBA0B, 0x90CA, 0xBA0C,	0x90CB, 0xBA0D, 0x90CC, 0xBA0E, 0x90CD, 0xBA0F, 0x90CE, 0xBA10,
+	0x90CF, 0xBA11, 0x90D0, 0xBA12, 0x90D1, 0xBA13, 0x90D2, 0xBA14,	0x90D3, 0xBA16, 0x90D4, 0xBA17, 0x90D5, 0xBA18, 0x90D6, 0xBA19,
+	0x90D7, 0xBA1A, 0x90D8, 0xBA1B, 0x90D9, 0xBA1C, 0x90DA, 0xBA1D,	0x90DB, 0xBA1E, 0x90DC, 0xBA1F, 0x90DD, 0xBA20, 0x90DE, 0xBA21,
+	0x90DF, 0xBA22, 0x90E0, 0xBA23, 0x90E1, 0xBA24, 0x90E2, 0xBA25,	0x90E3, 0xBA26, 0x90E4, 0xBA27, 0x90E5, 0xBA28, 0x90E6, 0xBA29,
+	0x90E7, 0xBA2A, 0x90E8, 0xBA2B, 0x90E9, 0xBA2C, 0x90EA, 0xBA2D,	0x90EB, 0xBA2E, 0x90EC, 0xBA2F, 0x90ED, 0xBA30, 0x90EE, 0xBA31,
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+	0x98EF, 0xC113, 0x98F0, 0xC114, 0x98F1, 0xC116, 0x98F2, 0xC117,	0x98F3, 0xC118, 0x98F4, 0xC119, 0x98F5, 0xC11A, 0x98F6, 0xC11B,
+	0x98F7, 0xC121, 0x98F8, 0xC122, 0x98F9, 0xC125, 0x98FA, 0xC128,	0x98FB, 0xC129, 0x98FC, 0xC12A, 0x98FD, 0xC12B, 0x98FE, 0xC12E,
+	0x9941, 0xC132, 0x9942, 0xC133, 0x9943, 0xC134, 0x9944, 0xC135,	0x9945, 0xC137, 0x9946, 0xC13A, 0x9947, 0xC13B, 0x9948, 0xC13D,
+	0x9949, 0xC13E, 0x994A, 0xC13F, 0x994B, 0xC141, 0x994C, 0xC142,	0x994D, 0xC143, 0x994E, 0xC144, 0x994F, 0xC145, 0x9950, 0xC146,
+	0x9951, 0xC147, 0x9952, 0xC14A, 0x9953, 0xC14E, 0x9954, 0xC14F,	0x9955, 0xC150, 0x9956, 0xC151, 0x9957, 0xC152, 0x9958, 0xC153,
+	0x9959, 0xC156, 0x995A, 0xC157, 0x9961, 0xC159, 0x9962, 0xC15A,	0x9963, 0xC15B, 0x9964, 0xC15D, 0x9965, 0xC15E, 0x9966, 0xC15F,
+	0x9967, 0xC160, 0x9968, 0xC161, 0x9969, 0xC162, 0x996A, 0xC163,	0x996B, 0xC166, 0x996C, 0xC16A, 0x996D, 0xC16B, 0x996E, 0xC16C,
+	0x996F, 0xC16D, 0x9970, 0xC16E, 0x9971, 0xC16F, 0x9972, 0xC171,	0x9973, 0xC172, 0x9974, 0xC173, 0x9975, 0xC175, 0x9976, 0xC176,
+	0x9977, 0xC177, 0x9978, 0xC179, 0x9979, 0xC17A, 0x997A, 0xC17B,	0x9981, 0xC17C, 0x9982, 0xC17D, 0x9983, 0xC17E, 0x9984, 0xC17F,
+	0x9985, 0xC180, 0x9986, 0xC181, 0x9987, 0xC182, 0x9988, 0xC183,	0x9989, 0xC184, 0x998A, 0xC186, 0x998B, 0xC187, 0x998C, 0xC188,
+	0x998D, 0xC189, 0x998E, 0xC18A, 0x998F, 0xC18B, 0x9990, 0xC18F,	0x9991, 0xC191, 0x9992, 0xC192, 0x9993, 0xC193, 0x9994, 0xC195,
+	0x9995, 0xC197, 0x9996, 0xC198, 0x9997, 0xC199, 0x9998, 0xC19A,	0x9999, 0xC19B, 0x999A, 0xC19E, 0x999B, 0xC1A0, 0x999C, 0xC1A2,
+	0x999D, 0xC1A3, 0x999E, 0xC1A4, 0x999F, 0xC1A6, 0x99A0, 0xC1A7,	0x99A1, 0xC1AA, 0x99A2, 0xC1AB, 0x99A3, 0xC1AD, 0x99A4, 0xC1AE,
+	0x99A5, 0xC1AF, 0x99A6, 0xC1B1, 0x99A7, 0xC1B2, 0x99A8, 0xC1B3,	0x99A9, 0xC1B4, 0x99AA, 0xC1B5, 0x99AB, 0xC1B6, 0x99AC, 0xC1B7,
+	0x99AD, 0xC1B8, 0x99AE, 0xC1B9, 0x99AF, 0xC1BA, 0x99B0, 0xC1BB,	0x99B1, 0xC1BC, 0x99B2, 0xC1BE, 0x99B3, 0xC1BF, 0x99B4, 0xC1C0,
+	0x99B5, 0xC1C1, 0x99B6, 0xC1C2, 0x99B7, 0xC1C3, 0x99B8, 0xC1C5,	0x99B9, 0xC1C6, 0x99BA, 0xC1C7, 0x99BB, 0xC1C9, 0x99BC, 0xC1CA,
+	0x99BD, 0xC1CB, 0x99BE, 0xC1CD, 0x99BF, 0xC1CE, 0x99C0, 0xC1CF,	0x99C1, 0xC1D0, 0x99C2, 0xC1D1, 0x99C3, 0xC1D2, 0x99C4, 0xC1D3,
+	0x99C5, 0xC1D5, 0x99C6, 0xC1D6, 0x99C7, 0xC1D9, 0x99C8, 0xC1DA,	0x99C9, 0xC1DB, 0x99CA, 0xC1DC, 0x99CB, 0xC1DD, 0x99CC, 0xC1DE,
+	0x99CD, 0xC1DF, 0x99CE, 0xC1E1, 0x99CF, 0xC1E2, 0x99D0, 0xC1E3,	0x99D1, 0xC1E5, 0x99D2, 0xC1E6, 0x99D3, 0xC1E7, 0x99D4, 0xC1E9,
+	0x99D5, 0xC1EA, 0x99D6, 0xC1EB, 0x99D7, 0xC1EC, 0x99D8, 0xC1ED,	0x99D9, 0xC1EE, 0x99DA, 0xC1EF, 0x99DB, 0xC1F2, 0x99DC, 0xC1F4,
+	0x99DD, 0xC1F5, 0x99DE, 0xC1F6, 0x99DF, 0xC1F7, 0x99E0, 0xC1F8,	0x99E1, 0xC1F9, 0x99E2, 0xC1FA, 0x99E3, 0xC1FB, 0x99E4, 0xC1FE,
+	0x99E5, 0xC1FF, 0x99E6, 0xC201, 0x99E7, 0xC202, 0x99E8, 0xC203,	0x99E9, 0xC205, 0x99EA, 0xC206, 0x99EB, 0xC207, 0x99EC, 0xC208,
+	0x99ED, 0xC209, 0x99EE, 0xC20A, 0x99EF, 0xC20B, 0x99F0, 0xC20E,	0x99F1, 0xC210, 0x99F2, 0xC212, 0x99F3, 0xC213, 0x99F4, 0xC214,
+	0x99F5, 0xC215, 0x99F6, 0xC216, 0x99F7, 0xC217, 0x99F8, 0xC21A,	0x99F9, 0xC21B, 0x99FA, 0xC21D, 0x99FB, 0xC21E, 0x99FC, 0xC221,
+	0x99FD, 0xC222, 0x99FE, 0xC223, 0x9A41, 0xC224, 0x9A42, 0xC225,	0x9A43, 0xC226, 0x9A44, 0xC227, 0x9A45, 0xC22A, 0x9A46, 0xC22C,
+	0x9A47, 0xC22E, 0x9A48, 0xC230, 0x9A49, 0xC233, 0x9A4A, 0xC235,	0x9A4B, 0xC236, 0x9A4C, 0xC237, 0x9A4D, 0xC238, 0x9A4E, 0xC239,
+	0x9A4F, 0xC23A, 0x9A50, 0xC23B, 0x9A51, 0xC23C, 0x9A52, 0xC23D,	0x9A53, 0xC23E, 0x9A54, 0xC23F, 0x9A55, 0xC240, 0x9A56, 0xC241,
+	0x9A57, 0xC242, 0x9A58, 0xC243, 0x9A59, 0xC244, 0x9A5A, 0xC245,	0x9A61, 0xC246, 0x9A62, 0xC247, 0x9A63, 0xC249, 0x9A64, 0xC24A,
+	0x9A65, 0xC24B, 0x9A66, 0xC24C, 0x9A67, 0xC24D, 0x9A68, 0xC24E,	0x9A69, 0xC24F, 0x9A6A, 0xC252, 0x9A6B, 0xC253, 0x9A6C, 0xC255,
+	0x9A6D, 0xC256, 0x9A6E, 0xC257, 0x9A6F, 0xC259, 0x9A70, 0xC25A,	0x9A71, 0xC25B, 0x9A72, 0xC25C, 0x9A73, 0xC25D, 0x9A74, 0xC25E,
+	0x9A75, 0xC25F, 0x9A76, 0xC261, 0x9A77, 0xC262, 0x9A78, 0xC263,	0x9A79, 0xC264, 0x9A7A, 0xC266, 0x9A81, 0xC267, 0x9A82, 0xC268,
+	0x9A83, 0xC269, 0x9A84, 0xC26A, 0x9A85, 0xC26B, 0x9A86, 0xC26E,	0x9A87, 0xC26F, 0x9A88, 0xC271, 0x9A89, 0xC272, 0x9A8A, 0xC273,
+	0x9A8B, 0xC275, 0x9A8C, 0xC276, 0x9A8D, 0xC277, 0x9A8E, 0xC278,	0x9A8F, 0xC279, 0x9A90, 0xC27A, 0x9A91, 0xC27B, 0x9A92, 0xC27E,
+	0x9A93, 0xC280, 0x9A94, 0xC282, 0x9A95, 0xC283, 0x9A96, 0xC284,	0x9A97, 0xC285, 0x9A98, 0xC286, 0x9A99, 0xC287, 0x9A9A, 0xC28A,
+	0x9A9B, 0xC28B, 0x9A9C, 0xC28C, 0x9A9D, 0xC28D, 0x9A9E, 0xC28E,	0x9A9F, 0xC28F, 0x9AA0, 0xC291, 0x9AA1, 0xC292, 0x9AA2, 0xC293,
+	0x9AA3, 0xC294, 0x9AA4, 0xC295, 0x9AA5, 0xC296, 0x9AA6, 0xC297,	0x9AA7, 0xC299, 0x9AA8, 0xC29A, 0x9AA9, 0xC29C, 0x9AAA, 0xC29E,
+	0x9AAB, 0xC29F, 0x9AAC, 0xC2A0, 0x9AAD, 0xC2A1, 0x9AAE, 0xC2A2,	0x9AAF, 0xC2A3, 0x9AB0, 0xC2A6, 0x9AB1, 0xC2A7, 0x9AB2, 0xC2A9,
+	0x9AB3, 0xC2AA, 0x9AB4, 0xC2AB, 0x9AB5, 0xC2AE, 0x9AB6, 0xC2AF,	0x9AB7, 0xC2B0, 0x9AB8, 0xC2B1, 0x9AB9, 0xC2B2, 0x9ABA, 0xC2B3,
+	0x9ABB, 0xC2B6, 0x9ABC, 0xC2B8, 0x9ABD, 0xC2BA, 0x9ABE, 0xC2BB,	0x9ABF, 0xC2BC, 0x9AC0, 0xC2BD, 0x9AC1, 0xC2BE, 0x9AC2, 0xC2BF,
+	0x9AC3, 0xC2C0, 0x9AC4, 0xC2C1, 0x9AC5, 0xC2C2, 0x9AC6, 0xC2C3,	0x9AC7, 0xC2C4, 0x9AC8, 0xC2C5, 0x9AC9, 0xC2C6, 0x9ACA, 0xC2C7,
+	0x9ACB, 0xC2C8, 0x9ACC, 0xC2C9, 0x9ACD, 0xC2CA, 0x9ACE, 0xC2CB,	0x9ACF, 0xC2CC, 0x9AD0, 0xC2CD, 0x9AD1, 0xC2CE, 0x9AD2, 0xC2CF,
+	0x9AD3, 0xC2D0, 0x9AD4, 0xC2D1, 0x9AD5, 0xC2D2, 0x9AD6, 0xC2D3,	0x9AD7, 0xC2D4, 0x9AD8, 0xC2D5, 0x9AD9, 0xC2D6, 0x9ADA, 0xC2D7,
+	0x9ADB, 0xC2D8, 0x9ADC, 0xC2D9, 0x9ADD, 0xC2DA, 0x9ADE, 0xC2DB,	0x9ADF, 0xC2DE, 0x9AE0, 0xC2DF, 0x9AE1, 0xC2E1, 0x9AE2, 0xC2E2,
+	0x9AE3, 0xC2E5, 0x9AE4, 0xC2E6, 0x9AE5, 0xC2E7, 0x9AE6, 0xC2E8,	0x9AE7, 0xC2E9, 0x9AE8, 0xC2EA, 0x9AE9, 0xC2EE, 0x9AEA, 0xC2F0,
+	0x9AEB, 0xC2F2, 0x9AEC, 0xC2F3, 0x9AED, 0xC2F4, 0x9AEE, 0xC2F5,	0x9AEF, 0xC2F7, 0x9AF0, 0xC2FA, 0x9AF1, 0xC2FD, 0x9AF2, 0xC2FE,
+	0x9AF3, 0xC2FF, 0x9AF4, 0xC301, 0x9AF5, 0xC302, 0x9AF6, 0xC303,	0x9AF7, 0xC304, 0x9AF8, 0xC305, 0x9AF9, 0xC306, 0x9AFA, 0xC307,
+	0x9AFB, 0xC30A, 0x9AFC, 0xC30B, 0x9AFD, 0xC30E, 0x9AFE, 0xC30F,	0x9B41, 0xC310, 0x9B42, 0xC311, 0x9B43, 0xC312, 0x9B44, 0xC316,
+	0x9B45, 0xC317, 0x9B46, 0xC319, 0x9B47, 0xC31A, 0x9B48, 0xC31B,	0x9B49, 0xC31D, 0x9B4A, 0xC31E, 0x9B4B, 0xC31F, 0x9B4C, 0xC320,
+	0x9B4D, 0xC321, 0x9B4E, 0xC322, 0x9B4F, 0xC323, 0x9B50, 0xC326,	0x9B51, 0xC327, 0x9B52, 0xC32A, 0x9B53, 0xC32B, 0x9B54, 0xC32C,
+	0x9B55, 0xC32D, 0x9B56, 0xC32E, 0x9B57, 0xC32F, 0x9B58, 0xC330,	0x9B59, 0xC331, 0x9B5A, 0xC332, 0x9B61, 0xC333, 0x9B62, 0xC334,
+	0x9B63, 0xC335, 0x9B64, 0xC336, 0x9B65, 0xC337, 0x9B66, 0xC338,	0x9B67, 0xC339, 0x9B68, 0xC33A, 0x9B69, 0xC33B, 0x9B6A, 0xC33C,
+	0x9B6B, 0xC33D, 0x9B6C, 0xC33E, 0x9B6D, 0xC33F, 0x9B6E, 0xC340,	0x9B6F, 0xC341, 0x9B70, 0xC342, 0x9B71, 0xC343, 0x9B72, 0xC344,
+	0x9B73, 0xC346, 0x9B74, 0xC347, 0x9B75, 0xC348, 0x9B76, 0xC349,	0x9B77, 0xC34A, 0x9B78, 0xC34B, 0x9B79, 0xC34C, 0x9B7A, 0xC34D,
+	0x9B81, 0xC34E, 0x9B82, 0xC34F, 0x9B83, 0xC350, 0x9B84, 0xC351,	0x9B85, 0xC352, 0x9B86, 0xC353, 0x9B87, 0xC354, 0x9B88, 0xC355,
+	0x9B89, 0xC356, 0x9B8A, 0xC357, 0x9B8B, 0xC358, 0x9B8C, 0xC359,	0x9B8D, 0xC35A, 0x9B8E, 0xC35B, 0x9B8F, 0xC35C, 0x9B90, 0xC35D,
+	0x9B91, 0xC35E, 0x9B92, 0xC35F, 0x9B93, 0xC360, 0x9B94, 0xC361,	0x9B95, 0xC362, 0x9B96, 0xC363, 0x9B97, 0xC364, 0x9B98, 0xC365,
+	0x9B99, 0xC366, 0x9B9A, 0xC367, 0x9B9B, 0xC36A, 0x9B9C, 0xC36B,	0x9B9D, 0xC36D, 0x9B9E, 0xC36E, 0x9B9F, 0xC36F, 0x9BA0, 0xC371,
+	0x9BA1, 0xC373, 0x9BA2, 0xC374, 0x9BA3, 0xC375, 0x9BA4, 0xC376,	0x9BA5, 0xC377, 0x9BA6, 0xC37A, 0x9BA7, 0xC37B, 0x9BA8, 0xC37E,
+	0x9BA9, 0xC37F, 0x9BAA, 0xC380, 0x9BAB, 0xC381, 0x9BAC, 0xC382,	0x9BAD, 0xC383, 0x9BAE, 0xC385, 0x9BAF, 0xC386, 0x9BB0, 0xC387,
+	0x9BB1, 0xC389, 0x9BB2, 0xC38A, 0x9BB3, 0xC38B, 0x9BB4, 0xC38D,	0x9BB5, 0xC38E, 0x9BB6, 0xC38F, 0x9BB7, 0xC390, 0x9BB8, 0xC391,
+	0x9BB9, 0xC392, 0x9BBA, 0xC393, 0x9BBB, 0xC394, 0x9BBC, 0xC395,	0x9BBD, 0xC396, 0x9BBE, 0xC397, 0x9BBF, 0xC398, 0x9BC0, 0xC399,
+	0x9BC1, 0xC39A, 0x9BC2, 0xC39B, 0x9BC3, 0xC39C, 0x9BC4, 0xC39D,	0x9BC5, 0xC39E, 0x9BC6, 0xC39F, 0x9BC7, 0xC3A0, 0x9BC8, 0xC3A1,
+	0x9BC9, 0xC3A2, 0x9BCA, 0xC3A3, 0x9BCB, 0xC3A4, 0x9BCC, 0xC3A5,	0x9BCD, 0xC3A6, 0x9BCE, 0xC3A7, 0x9BCF, 0xC3A8, 0x9BD0, 0xC3A9,
+	0x9BD1, 0xC3AA, 0x9BD2, 0xC3AB, 0x9BD3, 0xC3AC, 0x9BD4, 0xC3AD,	0x9BD5, 0xC3AE, 0x9BD6, 0xC3AF, 0x9BD7, 0xC3B0, 0x9BD8, 0xC3B1,
+	0x9BD9, 0xC3B2, 0x9BDA, 0xC3B3, 0x9BDB, 0xC3B4, 0x9BDC, 0xC3B5,	0x9BDD, 0xC3B6, 0x9BDE, 0xC3B7, 0x9BDF, 0xC3B8, 0x9BE0, 0xC3B9,
+	0x9BE1, 0xC3BA, 0x9BE2, 0xC3BB, 0x9BE3, 0xC3BC, 0x9BE4, 0xC3BD,	0x9BE5, 0xC3BE, 0x9BE6, 0xC3BF, 0x9BE7, 0xC3C1, 0x9BE8, 0xC3C2,
+	0x9BE9, 0xC3C3, 0x9BEA, 0xC3C4, 0x9BEB, 0xC3C5, 0x9BEC, 0xC3C6,	0x9BED, 0xC3C7, 0x9BEE, 0xC3C8, 0x9BEF, 0xC3C9, 0x9BF0, 0xC3CA,
+	0x9BF1, 0xC3CB, 0x9BF2, 0xC3CC, 0x9BF3, 0xC3CD, 0x9BF4, 0xC3CE,	0x9BF5, 0xC3CF, 0x9BF6, 0xC3D0, 0x9BF7, 0xC3D1, 0x9BF8, 0xC3D2,
+	0x9BF9, 0xC3D3, 0x9BFA, 0xC3D4, 0x9BFB, 0xC3D5, 0x9BFC, 0xC3D6,	0x9BFD, 0xC3D7, 0x9BFE, 0xC3DA, 0x9C41, 0xC3DB, 0x9C42, 0xC3DD,
+	0x9C43, 0xC3DE, 0x9C44, 0xC3E1, 0x9C45, 0xC3E3, 0x9C46, 0xC3E4,	0x9C47, 0xC3E5, 0x9C48, 0xC3E6, 0x9C49, 0xC3E7, 0x9C4A, 0xC3EA,
+	0x9C4B, 0xC3EB, 0x9C4C, 0xC3EC, 0x9C4D, 0xC3EE, 0x9C4E, 0xC3EF,	0x9C4F, 0xC3F0, 0x9C50, 0xC3F1, 0x9C51, 0xC3F2, 0x9C52, 0xC3F3,
+	0x9C53, 0xC3F6, 0x9C54, 0xC3F7, 0x9C55, 0xC3F9, 0x9C56, 0xC3FA,	0x9C57, 0xC3FB, 0x9C58, 0xC3FC, 0x9C59, 0xC3FD, 0x9C5A, 0xC3FE,
+	0x9C61, 0xC3FF, 0x9C62, 0xC400, 0x9C63, 0xC401, 0x9C64, 0xC402,	0x9C65, 0xC403, 0x9C66, 0xC404, 0x9C67, 0xC405, 0x9C68, 0xC406,
+	0x9C69, 0xC407, 0x9C6A, 0xC409, 0x9C6B, 0xC40A, 0x9C6C, 0xC40B,	0x9C6D, 0xC40C, 0x9C6E, 0xC40D, 0x9C6F, 0xC40E, 0x9C70, 0xC40F,
+	0x9C71, 0xC411, 0x9C72, 0xC412, 0x9C73, 0xC413, 0x9C74, 0xC414,	0x9C75, 0xC415, 0x9C76, 0xC416, 0x9C77, 0xC417, 0x9C78, 0xC418,
+	0x9C79, 0xC419, 0x9C7A, 0xC41A, 0x9C81, 0xC41B, 0x9C82, 0xC41C,	0x9C83, 0xC41D, 0x9C84, 0xC41E, 0x9C85, 0xC41F, 0x9C86, 0xC420,
+	0x9C87, 0xC421, 0x9C88, 0xC422, 0x9C89, 0xC423, 0x9C8A, 0xC425,	0x9C8B, 0xC426, 0x9C8C, 0xC427, 0x9C8D, 0xC428, 0x9C8E, 0xC429,
+	0x9C8F, 0xC42A, 0x9C90, 0xC42B, 0x9C91, 0xC42D, 0x9C92, 0xC42E,	0x9C93, 0xC42F, 0x9C94, 0xC431, 0x9C95, 0xC432, 0x9C96, 0xC433,
+	0x9C97, 0xC435, 0x9C98, 0xC436, 0x9C99, 0xC437, 0x9C9A, 0xC438,	0x9C9B, 0xC439, 0x9C9C, 0xC43A, 0x9C9D, 0xC43B, 0x9C9E, 0xC43E,
+	0x9C9F, 0xC43F, 0x9CA0, 0xC440, 0x9CA1, 0xC441, 0x9CA2, 0xC442,	0x9CA3, 0xC443, 0x9CA4, 0xC444, 0x9CA5, 0xC445, 0x9CA6, 0xC446,
+	0x9CA7, 0xC447, 0x9CA8, 0xC449, 0x9CA9, 0xC44A, 0x9CAA, 0xC44B,	0x9CAB, 0xC44C, 0x9CAC, 0xC44D, 0x9CAD, 0xC44E, 0x9CAE, 0xC44F,
+	0x9CAF, 0xC450, 0x9CB0, 0xC451, 0x9CB1, 0xC452, 0x9CB2, 0xC453,	0x9CB3, 0xC454, 0x9CB4, 0xC455, 0x9CB5, 0xC456, 0x9CB6, 0xC457,
+	0x9CB7, 0xC458, 0x9CB8, 0xC459, 0x9CB9, 0xC45A, 0x9CBA, 0xC45B,	0x9CBB, 0xC45C, 0x9CBC, 0xC45D, 0x9CBD, 0xC45E, 0x9CBE, 0xC45F,
+	0x9CBF, 0xC460, 0x9CC0, 0xC461, 0x9CC1, 0xC462, 0x9CC2, 0xC463,	0x9CC3, 0xC466, 0x9CC4, 0xC467, 0x9CC5, 0xC469, 0x9CC6, 0xC46A,
+	0x9CC7, 0xC46B, 0x9CC8, 0xC46D, 0x9CC9, 0xC46E, 0x9CCA, 0xC46F,	0x9CCB, 0xC470, 0x9CCC, 0xC471, 0x9CCD, 0xC472, 0x9CCE, 0xC473,
+	0x9CCF, 0xC476, 0x9CD0, 0xC477, 0x9CD1, 0xC478, 0x9CD2, 0xC47A,	0x9CD3, 0xC47B, 0x9CD4, 0xC47C, 0x9CD5, 0xC47D, 0x9CD6, 0xC47E,
+	0x9CD7, 0xC47F, 0x9CD8, 0xC481, 0x9CD9, 0xC482, 0x9CDA, 0xC483,	0x9CDB, 0xC484, 0x9CDC, 0xC485, 0x9CDD, 0xC486, 0x9CDE, 0xC487,
+	0x9CDF, 0xC488, 0x9CE0, 0xC489, 0x9CE1, 0xC48A, 0x9CE2, 0xC48B,	0x9CE3, 0xC48C, 0x9CE4, 0xC48D, 0x9CE5, 0xC48E, 0x9CE6, 0xC48F,
+	0x9CE7, 0xC490, 0x9CE8, 0xC491, 0x9CE9, 0xC492, 0x9CEA, 0xC493,	0x9CEB, 0xC495, 0x9CEC, 0xC496, 0x9CED, 0xC497, 0x9CEE, 0xC498,
+	0x9CEF, 0xC499, 0x9CF0, 0xC49A, 0x9CF1, 0xC49B, 0x9CF2, 0xC49D,	0x9CF3, 0xC49E, 0x9CF4, 0xC49F, 0x9CF5, 0xC4A0, 0x9CF6, 0xC4A1,
+	0x9CF7, 0xC4A2, 0x9CF8, 0xC4A3, 0x9CF9, 0xC4A4, 0x9CFA, 0xC4A5,	0x9CFB, 0xC4A6, 0x9CFC, 0xC4A7, 0x9CFD, 0xC4A8, 0x9CFE, 0xC4A9,
+	0x9D41, 0xC4AA, 0x9D42, 0xC4AB, 0x9D43, 0xC4AC, 0x9D44, 0xC4AD,	0x9D45, 0xC4AE, 0x9D46, 0xC4AF, 0x9D47, 0xC4B0, 0x9D48, 0xC4B1,
+	0x9D49, 0xC4B2, 0x9D4A, 0xC4B3, 0x9D4B, 0xC4B4, 0x9D4C, 0xC4B5,	0x9D4D, 0xC4B6, 0x9D4E, 0xC4B7, 0x9D4F, 0xC4B9, 0x9D50, 0xC4BA,
+	0x9D51, 0xC4BB, 0x9D52, 0xC4BD, 0x9D53, 0xC4BE, 0x9D54, 0xC4BF,	0x9D55, 0xC4C0, 0x9D56, 0xC4C1, 0x9D57, 0xC4C2, 0x9D58, 0xC4C3,
+	0x9D59, 0xC4C4, 0x9D5A, 0xC4C5, 0x9D61, 0xC4C6, 0x9D62, 0xC4C7,	0x9D63, 0xC4C8, 0x9D64, 0xC4C9, 0x9D65, 0xC4CA, 0x9D66, 0xC4CB,
+	0x9D67, 0xC4CC, 0x9D68, 0xC4CD, 0x9D69, 0xC4CE, 0x9D6A, 0xC4CF,	0x9D6B, 0xC4D0, 0x9D6C, 0xC4D1, 0x9D6D, 0xC4D2, 0x9D6E, 0xC4D3,
+	0x9D6F, 0xC4D4, 0x9D70, 0xC4D5, 0x9D71, 0xC4D6, 0x9D72, 0xC4D7,	0x9D73, 0xC4D8, 0x9D74, 0xC4D9, 0x9D75, 0xC4DA, 0x9D76, 0xC4DB,
+	0x9D77, 0xC4DC, 0x9D78, 0xC4DD, 0x9D79, 0xC4DE, 0x9D7A, 0xC4DF,	0x9D81, 0xC4E0, 0x9D82, 0xC4E1, 0x9D83, 0xC4E2, 0x9D84, 0xC4E3,
+	0x9D85, 0xC4E4, 0x9D86, 0xC4E5, 0x9D87, 0xC4E6, 0x9D88, 0xC4E7,	0x9D89, 0xC4E8, 0x9D8A, 0xC4EA, 0x9D8B, 0xC4EB, 0x9D8C, 0xC4EC,
+	0x9D8D, 0xC4ED, 0x9D8E, 0xC4EE, 0x9D8F, 0xC4EF, 0x9D90, 0xC4F2,	0x9D91, 0xC4F3, 0x9D92, 0xC4F5, 0x9D93, 0xC4F6, 0x9D94, 0xC4F7,
+	0x9D95, 0xC4F9, 0x9D96, 0xC4FB, 0x9D97, 0xC4FC, 0x9D98, 0xC4FD,	0x9D99, 0xC4FE, 0x9D9A, 0xC502, 0x9D9B, 0xC503, 0x9D9C, 0xC504,
+	0x9D9D, 0xC505, 0x9D9E, 0xC506, 0x9D9F, 0xC507, 0x9DA0, 0xC508,	0x9DA1, 0xC509, 0x9DA2, 0xC50A, 0x9DA3, 0xC50B, 0x9DA4, 0xC50D,
+	0x9DA5, 0xC50E, 0x9DA6, 0xC50F, 0x9DA7, 0xC511, 0x9DA8, 0xC512,	0x9DA9, 0xC513, 0x9DAA, 0xC515, 0x9DAB, 0xC516, 0x9DAC, 0xC517,
+	0x9DAD, 0xC518, 0x9DAE, 0xC519, 0x9DAF, 0xC51A, 0x9DB0, 0xC51B,	0x9DB1, 0xC51D, 0x9DB2, 0xC51E, 0x9DB3, 0xC51F, 0x9DB4, 0xC520,
+	0x9DB5, 0xC521, 0x9DB6, 0xC522, 0x9DB7, 0xC523, 0x9DB8, 0xC524,	0x9DB9, 0xC525, 0x9DBA, 0xC526, 0x9DBB, 0xC527, 0x9DBC, 0xC52A,
+	0x9DBD, 0xC52B, 0x9DBE, 0xC52D, 0x9DBF, 0xC52E, 0x9DC0, 0xC52F,	0x9DC1, 0xC531, 0x9DC2, 0xC532, 0x9DC3, 0xC533, 0x9DC4, 0xC534,
+	0x9DC5, 0xC535, 0x9DC6, 0xC536, 0x9DC7, 0xC537, 0x9DC8, 0xC53A,	0x9DC9, 0xC53C, 0x9DCA, 0xC53E, 0x9DCB, 0xC53F, 0x9DCC, 0xC540,
+	0x9DCD, 0xC541, 0x9DCE, 0xC542, 0x9DCF, 0xC543, 0x9DD0, 0xC546,	0x9DD1, 0xC547, 0x9DD2, 0xC54B, 0x9DD3, 0xC54F, 0x9DD4, 0xC550,
+	0x9DD5, 0xC551, 0x9DD6, 0xC552, 0x9DD7, 0xC556, 0x9DD8, 0xC55A,	0x9DD9, 0xC55B, 0x9DDA, 0xC55C, 0x9DDB, 0xC55F, 0x9DDC, 0xC562,
+	0x9DDD, 0xC563, 0x9DDE, 0xC565, 0x9DDF, 0xC566, 0x9DE0, 0xC567,	0x9DE1, 0xC569, 0x9DE2, 0xC56A, 0x9DE3, 0xC56B, 0x9DE4, 0xC56C,
+	0x9DE5, 0xC56D, 0x9DE6, 0xC56E, 0x9DE7, 0xC56F, 0x9DE8, 0xC572,	0x9DE9, 0xC576, 0x9DEA, 0xC577, 0x9DEB, 0xC578, 0x9DEC, 0xC579,
+	0x9DED, 0xC57A, 0x9DEE, 0xC57B, 0x9DEF, 0xC57E, 0x9DF0, 0xC57F,	0x9DF1, 0xC581, 0x9DF2, 0xC582, 0x9DF3, 0xC583, 0x9DF4, 0xC585,
+	0x9DF5, 0xC586, 0x9DF6, 0xC588, 0x9DF7, 0xC589, 0x9DF8, 0xC58A,	0x9DF9, 0xC58B, 0x9DFA, 0xC58E, 0x9DFB, 0xC590, 0x9DFC, 0xC592,
+	0x9DFD, 0xC593, 0x9DFE, 0xC594, 0x9E41, 0xC596, 0x9E42, 0xC599,	0x9E43, 0xC59A, 0x9E44, 0xC59B, 0x9E45, 0xC59D, 0x9E46, 0xC59E,
+	0x9E47, 0xC59F, 0x9E48, 0xC5A1, 0x9E49, 0xC5A2, 0x9E4A, 0xC5A3,	0x9E4B, 0xC5A4, 0x9E4C, 0xC5A5, 0x9E4D, 0xC5A6, 0x9E4E, 0xC5A7,
+	0x9E4F, 0xC5A8, 0x9E50, 0xC5AA, 0x9E51, 0xC5AB, 0x9E52, 0xC5AC,	0x9E53, 0xC5AD, 0x9E54, 0xC5AE, 0x9E55, 0xC5AF, 0x9E56, 0xC5B0,
+	0x9E57, 0xC5B1, 0x9E58, 0xC5B2, 0x9E59, 0xC5B3, 0x9E5A, 0xC5B6,	0x9E61, 0xC5B7, 0x9E62, 0xC5BA, 0x9E63, 0xC5BF, 0x9E64, 0xC5C0,
+	0x9E65, 0xC5C1, 0x9E66, 0xC5C2, 0x9E67, 0xC5C3, 0x9E68, 0xC5CB,	0x9E69, 0xC5CD, 0x9E6A, 0xC5CF, 0x9E6B, 0xC5D2, 0x9E6C, 0xC5D3,
+	0x9E6D, 0xC5D5, 0x9E6E, 0xC5D6, 0x9E6F, 0xC5D7, 0x9E70, 0xC5D9,	0x9E71, 0xC5DA, 0x9E72, 0xC5DB, 0x9E73, 0xC5DC, 0x9E74, 0xC5DD,
+	0x9E75, 0xC5DE, 0x9E76, 0xC5DF, 0x9E77, 0xC5E2, 0x9E78, 0xC5E4,	0x9E79, 0xC5E6, 0x9E7A, 0xC5E7, 0x9E81, 0xC5E8, 0x9E82, 0xC5E9,
+	0x9E83, 0xC5EA, 0x9E84, 0xC5EB, 0x9E85, 0xC5EF, 0x9E86, 0xC5F1,	0x9E87, 0xC5F2, 0x9E88, 0xC5F3, 0x9E89, 0xC5F5, 0x9E8A, 0xC5F8,
+	0x9E8B, 0xC5F9, 0x9E8C, 0xC5FA, 0x9E8D, 0xC5FB, 0x9E8E, 0xC602,	0x9E8F, 0xC603, 0x9E90, 0xC604, 0x9E91, 0xC609, 0x9E92, 0xC60A,
+	0x9E93, 0xC60B, 0x9E94, 0xC60D, 0x9E95, 0xC60E, 0x9E96, 0xC60F,	0x9E97, 0xC611, 0x9E98, 0xC612, 0x9E99, 0xC613, 0x9E9A, 0xC614,
+	0x9E9B, 0xC615, 0x9E9C, 0xC616, 0x9E9D, 0xC617, 0x9E9E, 0xC61A,	0x9E9F, 0xC61D, 0x9EA0, 0xC61E, 0x9EA1, 0xC61F, 0x9EA2, 0xC620,
+	0x9EA3, 0xC621, 0x9EA4, 0xC622, 0x9EA5, 0xC623, 0x9EA6, 0xC626,	0x9EA7, 0xC627, 0x9EA8, 0xC629, 0x9EA9, 0xC62A, 0x9EAA, 0xC62B,
+	0x9EAB, 0xC62F, 0x9EAC, 0xC631, 0x9EAD, 0xC632, 0x9EAE, 0xC636,	0x9EAF, 0xC638, 0x9EB0, 0xC63A, 0x9EB1, 0xC63C, 0x9EB2, 0xC63D,
+	0x9EB3, 0xC63E, 0x9EB4, 0xC63F, 0x9EB5, 0xC642, 0x9EB6, 0xC643,	0x9EB7, 0xC645, 0x9EB8, 0xC646, 0x9EB9, 0xC647, 0x9EBA, 0xC649,
+	0x9EBB, 0xC64A, 0x9EBC, 0xC64B, 0x9EBD, 0xC64C, 0x9EBE, 0xC64D,	0x9EBF, 0xC64E, 0x9EC0, 0xC64F, 0x9EC1, 0xC652, 0x9EC2, 0xC656,
+	0x9EC3, 0xC657, 0x9EC4, 0xC658, 0x9EC5, 0xC659, 0x9EC6, 0xC65A,	0x9EC7, 0xC65B, 0x9EC8, 0xC65E, 0x9EC9, 0xC65F, 0x9ECA, 0xC661,
+	0x9ECB, 0xC662, 0x9ECC, 0xC663, 0x9ECD, 0xC664, 0x9ECE, 0xC665,	0x9ECF, 0xC666, 0x9ED0, 0xC667, 0x9ED1, 0xC668, 0x9ED2, 0xC669,
+	0x9ED3, 0xC66A, 0x9ED4, 0xC66B, 0x9ED5, 0xC66D, 0x9ED6, 0xC66E,	0x9ED7, 0xC670, 0x9ED8, 0xC672, 0x9ED9, 0xC673, 0x9EDA, 0xC674,
+	0x9EDB, 0xC675, 0x9EDC, 0xC676, 0x9EDD, 0xC677, 0x9EDE, 0xC67A,	0x9EDF, 0xC67B, 0x9EE0, 0xC67D, 0x9EE1, 0xC67E, 0x9EE2, 0xC67F,
+	0x9EE3, 0xC681, 0x9EE4, 0xC682, 0x9EE5, 0xC683, 0x9EE6, 0xC684,	0x9EE7, 0xC685, 0x9EE8, 0xC686, 0x9EE9, 0xC687, 0x9EEA, 0xC68A,
+	0x9EEB, 0xC68C, 0x9EEC, 0xC68E, 0x9EED, 0xC68F, 0x9EEE, 0xC690,	0x9EEF, 0xC691, 0x9EF0, 0xC692, 0x9EF1, 0xC693, 0x9EF2, 0xC696,
+	0x9EF3, 0xC697, 0x9EF4, 0xC699, 0x9EF5, 0xC69A, 0x9EF6, 0xC69B,	0x9EF7, 0xC69D, 0x9EF8, 0xC69E, 0x9EF9, 0xC69F, 0x9EFA, 0xC6A0,
+	0x9EFB, 0xC6A1, 0x9EFC, 0xC6A2, 0x9EFD, 0xC6A3, 0x9EFE, 0xC6A6,	0x9F41, 0xC6A8, 0x9F42, 0xC6AA, 0x9F43, 0xC6AB, 0x9F44, 0xC6AC,
+	0x9F45, 0xC6AD, 0x9F46, 0xC6AE, 0x9F47, 0xC6AF, 0x9F48, 0xC6B2,	0x9F49, 0xC6B3, 0x9F4A, 0xC6B5, 0x9F4B, 0xC6B6, 0x9F4C, 0xC6B7,
+	0x9F4D, 0xC6BB, 0x9F4E, 0xC6BC, 0x9F4F, 0xC6BD, 0x9F50, 0xC6BE,	0x9F51, 0xC6BF, 0x9F52, 0xC6C2, 0x9F53, 0xC6C4, 0x9F54, 0xC6C6,
+	0x9F55, 0xC6C7, 0x9F56, 0xC6C8, 0x9F57, 0xC6C9, 0x9F58, 0xC6CA,	0x9F59, 0xC6CB, 0x9F5A, 0xC6CE, 0x9F61, 0xC6CF, 0x9F62, 0xC6D1,
+	0x9F63, 0xC6D2, 0x9F64, 0xC6D3, 0x9F65, 0xC6D5, 0x9F66, 0xC6D6,	0x9F67, 0xC6D7, 0x9F68, 0xC6D8, 0x9F69, 0xC6D9, 0x9F6A, 0xC6DA,
+	0x9F6B, 0xC6DB, 0x9F6C, 0xC6DE, 0x9F6D, 0xC6DF, 0x9F6E, 0xC6E2,	0x9F6F, 0xC6E3, 0x9F70, 0xC6E4, 0x9F71, 0xC6E5, 0x9F72, 0xC6E6,
+	0x9F73, 0xC6E7, 0x9F74, 0xC6EA, 0x9F75, 0xC6EB, 0x9F76, 0xC6ED,	0x9F77, 0xC6EE, 0x9F78, 0xC6EF, 0x9F79, 0xC6F1, 0x9F7A, 0xC6F2,
+	0x9F81, 0xC6F3, 0x9F82, 0xC6F4, 0x9F83, 0xC6F5, 0x9F84, 0xC6F6,	0x9F85, 0xC6F7, 0x9F86, 0xC6FA, 0x9F87, 0xC6FB, 0x9F88, 0xC6FC,
+	0x9F89, 0xC6FE, 0x9F8A, 0xC6FF, 0x9F8B, 0xC700, 0x9F8C, 0xC701,	0x9F8D, 0xC702, 0x9F8E, 0xC703, 0x9F8F, 0xC706, 0x9F90, 0xC707,
+	0x9F91, 0xC709, 0x9F92, 0xC70A, 0x9F93, 0xC70B, 0x9F94, 0xC70D,	0x9F95, 0xC70E, 0x9F96, 0xC70F, 0x9F97, 0xC710, 0x9F98, 0xC711,
+	0x9F99, 0xC712, 0x9F9A, 0xC713, 0x9F9B, 0xC716, 0x9F9C, 0xC718,	0x9F9D, 0xC71A, 0x9F9E, 0xC71B, 0x9F9F, 0xC71C, 0x9FA0, 0xC71D,
+	0x9FA1, 0xC71E, 0x9FA2, 0xC71F, 0x9FA3, 0xC722, 0x9FA4, 0xC723,	0x9FA5, 0xC725, 0x9FA6, 0xC726, 0x9FA7, 0xC727, 0x9FA8, 0xC729,
+	0x9FA9, 0xC72A, 0x9FAA, 0xC72B, 0x9FAB, 0xC72C, 0x9FAC, 0xC72D,	0x9FAD, 0xC72E, 0x9FAE, 0xC72F, 0x9FAF, 0xC732, 0x9FB0, 0xC734,
+	0x9FB1, 0xC736, 0x9FB2, 0xC738, 0x9FB3, 0xC739, 0x9FB4, 0xC73A,	0x9FB5, 0xC73B, 0x9FB6, 0xC73E, 0x9FB7, 0xC73F, 0x9FB8, 0xC741,
+	0x9FB9, 0xC742, 0x9FBA, 0xC743, 0x9FBB, 0xC745, 0x9FBC, 0xC746,	0x9FBD, 0xC747, 0x9FBE, 0xC748, 0x9FBF, 0xC749, 0x9FC0, 0xC74B,
+	0x9FC1, 0xC74E, 0x9FC2, 0xC750, 0x9FC3, 0xC759, 0x9FC4, 0xC75A,	0x9FC5, 0xC75B, 0x9FC6, 0xC75D, 0x9FC7, 0xC75E, 0x9FC8, 0xC75F,
+	0x9FC9, 0xC761, 0x9FCA, 0xC762, 0x9FCB, 0xC763, 0x9FCC, 0xC764,	0x9FCD, 0xC765, 0x9FCE, 0xC766, 0x9FCF, 0xC767, 0x9FD0, 0xC769,
+	0x9FD1, 0xC76A, 0x9FD2, 0xC76C, 0x9FD3, 0xC76D, 0x9FD4, 0xC76E,	0x9FD5, 0xC76F, 0x9FD6, 0xC770, 0x9FD7, 0xC771, 0x9FD8, 0xC772,
+	0x9FD9, 0xC773, 0x9FDA, 0xC776, 0x9FDB, 0xC777, 0x9FDC, 0xC779,	0x9FDD, 0xC77A, 0x9FDE, 0xC77B, 0x9FDF, 0xC77F, 0x9FE0, 0xC780,
+	0x9FE1, 0xC781, 0x9FE2, 0xC782, 0x9FE3, 0xC786, 0x9FE4, 0xC78B,	0x9FE5, 0xC78C, 0x9FE6, 0xC78D, 0x9FE7, 0xC78F, 0x9FE8, 0xC792,
+	0x9FE9, 0xC793, 0x9FEA, 0xC795, 0x9FEB, 0xC799, 0x9FEC, 0xC79B,	0x9FED, 0xC79C, 0x9FEE, 0xC79D, 0x9FEF, 0xC79E, 0x9FF0, 0xC79F,
+	0x9FF1, 0xC7A2, 0x9FF2, 0xC7A7, 0x9FF3, 0xC7A8, 0x9FF4, 0xC7A9,	0x9FF5, 0xC7AA, 0x9FF6, 0xC7AB, 0x9FF7, 0xC7AE, 0x9FF8, 0xC7AF,
+	0x9FF9, 0xC7B1, 0x9FFA, 0xC7B2, 0x9FFB, 0xC7B3, 0x9FFC, 0xC7B5,	0x9FFD, 0xC7B6, 0x9FFE, 0xC7B7, 0xA041, 0xC7B8, 0xA042, 0xC7B9,
+	0xA043, 0xC7BA, 0xA044, 0xC7BB, 0xA045, 0xC7BE, 0xA046, 0xC7C2,	0xA047, 0xC7C3, 0xA048, 0xC7C4, 0xA049, 0xC7C5, 0xA04A, 0xC7C6,
+	0xA04B, 0xC7C7, 0xA04C, 0xC7CA, 0xA04D, 0xC7CB, 0xA04E, 0xC7CD,	0xA04F, 0xC7CF, 0xA050, 0xC7D1, 0xA051, 0xC7D2, 0xA052, 0xC7D3,
+	0xA053, 0xC7D4, 0xA054, 0xC7D5, 0xA055, 0xC7D6, 0xA056, 0xC7D7,	0xA057, 0xC7D9, 0xA058, 0xC7DA, 0xA059, 0xC7DB, 0xA05A, 0xC7DC,
+	0xA061, 0xC7DE, 0xA062, 0xC7DF, 0xA063, 0xC7E0, 0xA064, 0xC7E1,	0xA065, 0xC7E2, 0xA066, 0xC7E3, 0xA067, 0xC7E5, 0xA068, 0xC7E6,
+	0xA069, 0xC7E7, 0xA06A, 0xC7E9, 0xA06B, 0xC7EA, 0xA06C, 0xC7EB,	0xA06D, 0xC7ED, 0xA06E, 0xC7EE, 0xA06F, 0xC7EF, 0xA070, 0xC7F0,
+	0xA071, 0xC7F1, 0xA072, 0xC7F2, 0xA073, 0xC7F3, 0xA074, 0xC7F4,	0xA075, 0xC7F5, 0xA076, 0xC7F6, 0xA077, 0xC7F7, 0xA078, 0xC7F8,
+	0xA079, 0xC7F9, 0xA07A, 0xC7FA, 0xA081, 0xC7FB, 0xA082, 0xC7FC,	0xA083, 0xC7FD, 0xA084, 0xC7FE, 0xA085, 0xC7FF, 0xA086, 0xC802,
+	0xA087, 0xC803, 0xA088, 0xC805, 0xA089, 0xC806, 0xA08A, 0xC807,	0xA08B, 0xC809, 0xA08C, 0xC80B, 0xA08D, 0xC80C, 0xA08E, 0xC80D,
+	0xA08F, 0xC80E, 0xA090, 0xC80F, 0xA091, 0xC812, 0xA092, 0xC814,	0xA093, 0xC817, 0xA094, 0xC818, 0xA095, 0xC819, 0xA096, 0xC81A,
+	0xA097, 0xC81B, 0xA098, 0xC81E, 0xA099, 0xC81F, 0xA09A, 0xC821,	0xA09B, 0xC822, 0xA09C, 0xC823, 0xA09D, 0xC825, 0xA09E, 0xC826,
+	0xA09F, 0xC827, 0xA0A0, 0xC828, 0xA0A1, 0xC829, 0xA0A2, 0xC82A,	0xA0A3, 0xC82B, 0xA0A4, 0xC82E, 0xA0A5, 0xC830, 0xA0A6, 0xC832,
+	0xA0A7, 0xC833, 0xA0A8, 0xC834, 0xA0A9, 0xC835, 0xA0AA, 0xC836,	0xA0AB, 0xC837, 0xA0AC, 0xC839, 0xA0AD, 0xC83A, 0xA0AE, 0xC83B,
+	0xA0AF, 0xC83D, 0xA0B0, 0xC83E, 0xA0B1, 0xC83F, 0xA0B2, 0xC841,	0xA0B3, 0xC842, 0xA0B4, 0xC843, 0xA0B5, 0xC844, 0xA0B6, 0xC845,
+	0xA0B7, 0xC846, 0xA0B8, 0xC847, 0xA0B9, 0xC84A, 0xA0BA, 0xC84B,	0xA0BB, 0xC84E, 0xA0BC, 0xC84F, 0xA0BD, 0xC850, 0xA0BE, 0xC851,
+	0xA0BF, 0xC852, 0xA0C0, 0xC853, 0xA0C1, 0xC855, 0xA0C2, 0xC856,	0xA0C3, 0xC857, 0xA0C4, 0xC858, 0xA0C5, 0xC859, 0xA0C6, 0xC85A,
+	0xA0C7, 0xC85B, 0xA0C8, 0xC85C, 0xA0C9, 0xC85D, 0xA0CA, 0xC85E,	0xA0CB, 0xC85F, 0xA0CC, 0xC860, 0xA0CD, 0xC861, 0xA0CE, 0xC862,
+	0xA0CF, 0xC863, 0xA0D0, 0xC864, 0xA0D1, 0xC865, 0xA0D2, 0xC866,	0xA0D3, 0xC867, 0xA0D4, 0xC868, 0xA0D5, 0xC869, 0xA0D6, 0xC86A,
+	0xA0D7, 0xC86B, 0xA0D8, 0xC86C, 0xA0D9, 0xC86D, 0xA0DA, 0xC86E,	0xA0DB, 0xC86F, 0xA0DC, 0xC872, 0xA0DD, 0xC873, 0xA0DE, 0xC875,
+	0xA0DF, 0xC876, 0xA0E0, 0xC877, 0xA0E1, 0xC879, 0xA0E2, 0xC87B,	0xA0E3, 0xC87C, 0xA0E4, 0xC87D, 0xA0E5, 0xC87E, 0xA0E6, 0xC87F,
+	0xA0E7, 0xC882, 0xA0E8, 0xC884, 0xA0E9, 0xC888, 0xA0EA, 0xC889,	0xA0EB, 0xC88A, 0xA0EC, 0xC88E, 0xA0ED, 0xC88F, 0xA0EE, 0xC890,
+	0xA0EF, 0xC891, 0xA0F0, 0xC892, 0xA0F1, 0xC893, 0xA0F2, 0xC895,	0xA0F3, 0xC896, 0xA0F4, 0xC897, 0xA0F5, 0xC898, 0xA0F6, 0xC899,
+	0xA0F7, 0xC89A, 0xA0F8, 0xC89B, 0xA0F9, 0xC89C, 0xA0FA, 0xC89E,	0xA0FB, 0xC8A0, 0xA0FC, 0xC8A2, 0xA0FD, 0xC8A3, 0xA0FE, 0xC8A4,
+	0xA141, 0xC8A5, 0xA142, 0xC8A6, 0xA143, 0xC8A7, 0xA144, 0xC8A9,	0xA145, 0xC8AA, 0xA146, 0xC8AB, 0xA147, 0xC8AC, 0xA148, 0xC8AD,
+	0xA149, 0xC8AE, 0xA14A, 0xC8AF, 0xA14B, 0xC8B0, 0xA14C, 0xC8B1,	0xA14D, 0xC8B2, 0xA14E, 0xC8B3, 0xA14F, 0xC8B4, 0xA150, 0xC8B5,
+	0xA151, 0xC8B6, 0xA152, 0xC8B7, 0xA153, 0xC8B8, 0xA154, 0xC8B9,	0xA155, 0xC8BA, 0xA156, 0xC8BB, 0xA157, 0xC8BE, 0xA158, 0xC8BF,
+	0xA159, 0xC8C0, 0xA15A, 0xC8C1, 0xA161, 0xC8C2, 0xA162, 0xC8C3,	0xA163, 0xC8C5, 0xA164, 0xC8C6, 0xA165, 0xC8C7, 0xA166, 0xC8C9,
+	0xA167, 0xC8CA, 0xA168, 0xC8CB, 0xA169, 0xC8CD, 0xA16A, 0xC8CE,	0xA16B, 0xC8CF, 0xA16C, 0xC8D0, 0xA16D, 0xC8D1, 0xA16E, 0xC8D2,
+	0xA16F, 0xC8D3, 0xA170, 0xC8D6, 0xA171, 0xC8D8, 0xA172, 0xC8DA,	0xA173, 0xC8DB, 0xA174, 0xC8DC, 0xA175, 0xC8DD, 0xA176, 0xC8DE,
+	0xA177, 0xC8DF, 0xA178, 0xC8E2, 0xA179, 0xC8E3, 0xA17A, 0xC8E5,	0xA181, 0xC8E6, 0xA182, 0xC8E7, 0xA183, 0xC8E8, 0xA184, 0xC8E9,
+	0xA185, 0xC8EA, 0xA186, 0xC8EB, 0xA187, 0xC8EC, 0xA188, 0xC8ED,	0xA189, 0xC8EE, 0xA18A, 0xC8EF, 0xA18B, 0xC8F0, 0xA18C, 0xC8F1,
+	0xA18D, 0xC8F2, 0xA18E, 0xC8F3, 0xA18F, 0xC8F4, 0xA190, 0xC8F6,	0xA191, 0xC8F7, 0xA192, 0xC8F8, 0xA193, 0xC8F9, 0xA194, 0xC8FA,
+	0xA195, 0xC8FB, 0xA196, 0xC8FE, 0xA197, 0xC8FF, 0xA198, 0xC901,	0xA199, 0xC902, 0xA19A, 0xC903, 0xA19B, 0xC907, 0xA19C, 0xC908,
+	0xA19D, 0xC909, 0xA19E, 0xC90A, 0xA19F, 0xC90B, 0xA1A0, 0xC90E,	0xA1A1, 0x3000, 0xA1A2, 0x3001, 0xA1A3, 0x3002, 0xA1A4, 0x00B7,
+	0xA1A5, 0x2025, 0xA1A6, 0x2026, 0xA1A7, 0x00A8, 0xA1A8, 0x3003,	0xA1A9, 0x00AD, 0xA1AA, 0x2015, 0xA1AB, 0x2225, 0xA1AC, 0xFF3C,
+	0xA1AD, 0x223C, 0xA1AE, 0x2018, 0xA1AF, 0x2019, 0xA1B0, 0x201C,	0xA1B1, 0x201D, 0xA1B2, 0x3014, 0xA1B3, 0x3015, 0xA1B4, 0x3008,
+	0xA1B5, 0x3009, 0xA1B6, 0x300A, 0xA1B7, 0x300B, 0xA1B8, 0x300C,	0xA1B9, 0x300D, 0xA1BA, 0x300E, 0xA1BB, 0x300F, 0xA1BC, 0x3010,
+	0xA1BD, 0x3011, 0xA1BE, 0x00B1, 0xA1BF, 0x00D7, 0xA1C0, 0x00F7,	0xA1C1, 0x2260, 0xA1C2, 0x2264, 0xA1C3, 0x2265, 0xA1C4, 0x221E,
+	0xA1C5, 0x2234, 0xA1C6, 0x00B0, 0xA1C7, 0x2032, 0xA1C8, 0x2033,	0xA1C9, 0x2103, 0xA1CA, 0x212B, 0xA1CB, 0xFFE0, 0xA1CC, 0xFFE1,
+	0xA1CD, 0xFFE5, 0xA1CE, 0x2642, 0xA1CF, 0x2640, 0xA1D0, 0x2220,	0xA1D1, 0x22A5, 0xA1D2, 0x2312, 0xA1D3, 0x2202, 0xA1D4, 0x2207,
+	0xA1D5, 0x2261, 0xA1D6, 0x2252, 0xA1D7, 0x00A7, 0xA1D8, 0x203B,	0xA1D9, 0x2606, 0xA1DA, 0x2605, 0xA1DB, 0x25CB, 0xA1DC, 0x25CF,
+	0xA1DD, 0x25CE, 0xA1DE, 0x25C7, 0xA1DF, 0x25C6, 0xA1E0, 0x25A1,	0xA1E1, 0x25A0, 0xA1E2, 0x25B3, 0xA1E3, 0x25B2, 0xA1E4, 0x25BD,
+	0xA1E5, 0x25BC, 0xA1E6, 0x2192, 0xA1E7, 0x2190, 0xA1E8, 0x2191,	0xA1E9, 0x2193, 0xA1EA, 0x2194, 0xA1EB, 0x3013, 0xA1EC, 0x226A,
+	0xA1ED, 0x226B, 0xA1EE, 0x221A, 0xA1EF, 0x223D, 0xA1F0, 0x221D,	0xA1F1, 0x2235, 0xA1F2, 0x222B, 0xA1F3, 0x222C, 0xA1F4, 0x2208,
+	0xA1F5, 0x220B, 0xA1F6, 0x2286, 0xA1F7, 0x2287, 0xA1F8, 0x2282,	0xA1F9, 0x2283, 0xA1FA, 0x222A, 0xA1FB, 0x2229, 0xA1FC, 0x2227,
+	0xA1FD, 0x2228, 0xA1FE, 0xFFE2, 0xA241, 0xC910, 0xA242, 0xC912,	0xA243, 0xC913, 0xA244, 0xC914, 0xA245, 0xC915, 0xA246, 0xC916,
+	0xA247, 0xC917, 0xA248, 0xC919, 0xA249, 0xC91A, 0xA24A, 0xC91B,	0xA24B, 0xC91C, 0xA24C, 0xC91D, 0xA24D, 0xC91E, 0xA24E, 0xC91F,
+	0xA24F, 0xC920, 0xA250, 0xC921, 0xA251, 0xC922, 0xA252, 0xC923,	0xA253, 0xC924, 0xA254, 0xC925, 0xA255, 0xC926, 0xA256, 0xC927,
+	0xA257, 0xC928, 0xA258, 0xC929, 0xA259, 0xC92A, 0xA25A, 0xC92B,	0xA261, 0xC92D, 0xA262, 0xC92E, 0xA263, 0xC92F, 0xA264, 0xC930,
+	0xA265, 0xC931, 0xA266, 0xC932, 0xA267, 0xC933, 0xA268, 0xC935,	0xA269, 0xC936, 0xA26A, 0xC937, 0xA26B, 0xC938, 0xA26C, 0xC939,
+	0xA26D, 0xC93A, 0xA26E, 0xC93B, 0xA26F, 0xC93C, 0xA270, 0xC93D,	0xA271, 0xC93E, 0xA272, 0xC93F, 0xA273, 0xC940, 0xA274, 0xC941,
+	0xA275, 0xC942, 0xA276, 0xC943, 0xA277, 0xC944, 0xA278, 0xC945,	0xA279, 0xC946, 0xA27A, 0xC947, 0xA281, 0xC948, 0xA282, 0xC949,
+	0xA283, 0xC94A, 0xA284, 0xC94B, 0xA285, 0xC94C, 0xA286, 0xC94D,	0xA287, 0xC94E, 0xA288, 0xC94F, 0xA289, 0xC952, 0xA28A, 0xC953,
+	0xA28B, 0xC955, 0xA28C, 0xC956, 0xA28D, 0xC957, 0xA28E, 0xC959,	0xA28F, 0xC95A, 0xA290, 0xC95B, 0xA291, 0xC95C, 0xA292, 0xC95D,
+	0xA293, 0xC95E, 0xA294, 0xC95F, 0xA295, 0xC962, 0xA296, 0xC964,	0xA297, 0xC965, 0xA298, 0xC966, 0xA299, 0xC967, 0xA29A, 0xC968,
+	0xA29B, 0xC969, 0xA29C, 0xC96A, 0xA29D, 0xC96B, 0xA29E, 0xC96D,	0xA29F, 0xC96E, 0xA2A0, 0xC96F, 0xA2A1, 0x21D2, 0xA2A2, 0x21D4,
+	0xA2A3, 0x2200, 0xA2A4, 0x2203, 0xA2A5, 0x00B4, 0xA2A6, 0xFF5E,	0xA2A7, 0x02C7, 0xA2A8, 0x02D8, 0xA2A9, 0x02DD, 0xA2AA, 0x02DA,
+	0xA2AB, 0x02D9, 0xA2AC, 0x00B8, 0xA2AD, 0x02DB, 0xA2AE, 0x00A1,	0xA2AF, 0x00BF, 0xA2B0, 0x02D0, 0xA2B1, 0x222E, 0xA2B2, 0x2211,
+	0xA2B3, 0x220F, 0xA2B4, 0x00A4, 0xA2B5, 0x2109, 0xA2B6, 0x2030,	0xA2B7, 0x25C1, 0xA2B8, 0x25C0, 0xA2B9, 0x25B7, 0xA2BA, 0x25B6,
+	0xA2BB, 0x2664, 0xA2BC, 0x2660, 0xA2BD, 0x2661, 0xA2BE, 0x2665,	0xA2BF, 0x2667, 0xA2C0, 0x2663, 0xA2C1, 0x2299, 0xA2C2, 0x25C8,
+	0xA2C3, 0x25A3, 0xA2C4, 0x25D0, 0xA2C5, 0x25D1, 0xA2C6, 0x2592,	0xA2C7, 0x25A4, 0xA2C8, 0x25A5, 0xA2C9, 0x25A8, 0xA2CA, 0x25A7,
+	0xA2CB, 0x25A6, 0xA2CC, 0x25A9, 0xA2CD, 0x2668, 0xA2CE, 0x260F,	0xA2CF, 0x260E, 0xA2D0, 0x261C, 0xA2D1, 0x261E, 0xA2D2, 0x00B6,
+	0xA2D3, 0x2020, 0xA2D4, 0x2021, 0xA2D5, 0x2195, 0xA2D6, 0x2197,	0xA2D7, 0x2199, 0xA2D8, 0x2196, 0xA2D9, 0x2198, 0xA2DA, 0x266D,
+	0xA2DB, 0x2669, 0xA2DC, 0x266A, 0xA2DD, 0x266C, 0xA2DE, 0x327F,	0xA2DF, 0x321C, 0xA2E0, 0x2116, 0xA2E1, 0x33C7, 0xA2E2, 0x2122,
+	0xA2E3, 0x33C2, 0xA2E4, 0x33D8, 0xA2E5, 0x2121, 0xA2E6, 0x20AC,	0xA2E7, 0x00AE, 0xA341, 0xC971, 0xA342, 0xC972, 0xA343, 0xC973,
+	0xA344, 0xC975, 0xA345, 0xC976, 0xA346, 0xC977, 0xA347, 0xC978,	0xA348, 0xC979, 0xA349, 0xC97A, 0xA34A, 0xC97B, 0xA34B, 0xC97D,
+	0xA34C, 0xC97E, 0xA34D, 0xC97F, 0xA34E, 0xC980, 0xA34F, 0xC981,	0xA350, 0xC982, 0xA351, 0xC983, 0xA352, 0xC984, 0xA353, 0xC985,
+	0xA354, 0xC986, 0xA355, 0xC987, 0xA356, 0xC98A, 0xA357, 0xC98B,	0xA358, 0xC98D, 0xA359, 0xC98E, 0xA35A, 0xC98F, 0xA361, 0xC991,
+	0xA362, 0xC992, 0xA363, 0xC993, 0xA364, 0xC994, 0xA365, 0xC995,	0xA366, 0xC996, 0xA367, 0xC997, 0xA368, 0xC99A, 0xA369, 0xC99C,
+	0xA36A, 0xC99E, 0xA36B, 0xC99F, 0xA36C, 0xC9A0, 0xA36D, 0xC9A1,	0xA36E, 0xC9A2, 0xA36F, 0xC9A3, 0xA370, 0xC9A4, 0xA371, 0xC9A5,
+	0xA372, 0xC9A6, 0xA373, 0xC9A7, 0xA374, 0xC9A8, 0xA375, 0xC9A9,	0xA376, 0xC9AA, 0xA377, 0xC9AB, 0xA378, 0xC9AC, 0xA379, 0xC9AD,
+	0xA37A, 0xC9AE, 0xA381, 0xC9AF, 0xA382, 0xC9B0, 0xA383, 0xC9B1,	0xA384, 0xC9B2, 0xA385, 0xC9B3, 0xA386, 0xC9B4, 0xA387, 0xC9B5,
+	0xA388, 0xC9B6, 0xA389, 0xC9B7, 0xA38A, 0xC9B8, 0xA38B, 0xC9B9,	0xA38C, 0xC9BA, 0xA38D, 0xC9BB, 0xA38E, 0xC9BC, 0xA38F, 0xC9BD,
+	0xA390, 0xC9BE, 0xA391, 0xC9BF, 0xA392, 0xC9C2, 0xA393, 0xC9C3,	0xA394, 0xC9C5, 0xA395, 0xC9C6, 0xA396, 0xC9C9, 0xA397, 0xC9CB,
+	0xA398, 0xC9CC, 0xA399, 0xC9CD, 0xA39A, 0xC9CE, 0xA39B, 0xC9CF,	0xA39C, 0xC9D2, 0xA39D, 0xC9D4, 0xA39E, 0xC9D7, 0xA39F, 0xC9D8,
+	0xA3A0, 0xC9DB, 0xA3A1, 0xFF01, 0xA3A2, 0xFF02, 0xA3A3, 0xFF03,	0xA3A4, 0xFF04, 0xA3A5, 0xFF05, 0xA3A6, 0xFF06, 0xA3A7, 0xFF07,
+	0xA3A8, 0xFF08, 0xA3A9, 0xFF09, 0xA3AA, 0xFF0A, 0xA3AB, 0xFF0B,	0xA3AC, 0xFF0C, 0xA3AD, 0xFF0D, 0xA3AE, 0xFF0E, 0xA3AF, 0xFF0F,
+	0xA3B0, 0xFF10, 0xA3B1, 0xFF11, 0xA3B2, 0xFF12, 0xA3B3, 0xFF13,	0xA3B4, 0xFF14, 0xA3B5, 0xFF15, 0xA3B6, 0xFF16, 0xA3B7, 0xFF17,
+	0xA3B8, 0xFF18, 0xA3B9, 0xFF19, 0xA3BA, 0xFF1A, 0xA3BB, 0xFF1B,	0xA3BC, 0xFF1C, 0xA3BD, 0xFF1D, 0xA3BE, 0xFF1E, 0xA3BF, 0xFF1F,
+	0xA3C0, 0xFF20, 0xA3C1, 0xFF21, 0xA3C2, 0xFF22, 0xA3C3, 0xFF23,	0xA3C4, 0xFF24, 0xA3C5, 0xFF25, 0xA3C6, 0xFF26, 0xA3C7, 0xFF27,
+	0xA3C8, 0xFF28, 0xA3C9, 0xFF29, 0xA3CA, 0xFF2A, 0xA3CB, 0xFF2B,	0xA3CC, 0xFF2C, 0xA3CD, 0xFF2D, 0xA3CE, 0xFF2E, 0xA3CF, 0xFF2F,
+	0xA3D0, 0xFF30, 0xA3D1, 0xFF31, 0xA3D2, 0xFF32, 0xA3D3, 0xFF33,	0xA3D4, 0xFF34, 0xA3D5, 0xFF35, 0xA3D6, 0xFF36, 0xA3D7, 0xFF37,
+	0xA3D8, 0xFF38, 0xA3D9, 0xFF39, 0xA3DA, 0xFF3A, 0xA3DB, 0xFF3B,	0xA3DC, 0xFFE6, 0xA3DD, 0xFF3D, 0xA3DE, 0xFF3E, 0xA3DF, 0xFF3F,
+	0xA3E0, 0xFF40, 0xA3E1, 0xFF41, 0xA3E2, 0xFF42, 0xA3E3, 0xFF43,	0xA3E4, 0xFF44, 0xA3E5, 0xFF45, 0xA3E6, 0xFF46, 0xA3E7, 0xFF47,
+	0xA3E8, 0xFF48, 0xA3E9, 0xFF49, 0xA3EA, 0xFF4A, 0xA3EB, 0xFF4B,	0xA3EC, 0xFF4C, 0xA3ED, 0xFF4D, 0xA3EE, 0xFF4E, 0xA3EF, 0xFF4F,
+	0xA3F0, 0xFF50, 0xA3F1, 0xFF51, 0xA3F2, 0xFF52, 0xA3F3, 0xFF53,	0xA3F4, 0xFF54, 0xA3F5, 0xFF55, 0xA3F6, 0xFF56, 0xA3F7, 0xFF57,
+	0xA3F8, 0xFF58, 0xA3F9, 0xFF59, 0xA3FA, 0xFF5A, 0xA3FB, 0xFF5B,	0xA3FC, 0xFF5C, 0xA3FD, 0xFF5D, 0xA3FE, 0xFFE3, 0xA441, 0xC9DE,
+	0xA442, 0xC9DF, 0xA443, 0xC9E1, 0xA444, 0xC9E3, 0xA445, 0xC9E5,	0xA446, 0xC9E6, 0xA447, 0xC9E8, 0xA448, 0xC9E9, 0xA449, 0xC9EA,
+	0xA44A, 0xC9EB, 0xA44B, 0xC9EE, 0xA44C, 0xC9F2, 0xA44D, 0xC9F3,	0xA44E, 0xC9F4, 0xA44F, 0xC9F5, 0xA450, 0xC9F6, 0xA451, 0xC9F7,
+	0xA452, 0xC9FA, 0xA453, 0xC9FB, 0xA454, 0xC9FD, 0xA455, 0xC9FE,	0xA456, 0xC9FF, 0xA457, 0xCA01, 0xA458, 0xCA02, 0xA459, 0xCA03,
+	0xA45A, 0xCA04, 0xA461, 0xCA05, 0xA462, 0xCA06, 0xA463, 0xCA07,	0xA464, 0xCA0A, 0xA465, 0xCA0E, 0xA466, 0xCA0F, 0xA467, 0xCA10,
+	0xA468, 0xCA11, 0xA469, 0xCA12, 0xA46A, 0xCA13, 0xA46B, 0xCA15,	0xA46C, 0xCA16, 0xA46D, 0xCA17, 0xA46E, 0xCA19, 0xA46F, 0xCA1A,
+	0xA470, 0xCA1B, 0xA471, 0xCA1C, 0xA472, 0xCA1D, 0xA473, 0xCA1E,	0xA474, 0xCA1F, 0xA475, 0xCA20, 0xA476, 0xCA21, 0xA477, 0xCA22,
+	0xA478, 0xCA23, 0xA479, 0xCA24, 0xA47A, 0xCA25, 0xA481, 0xCA26,	0xA482, 0xCA27, 0xA483, 0xCA28, 0xA484, 0xCA2A, 0xA485, 0xCA2B,
+	0xA486, 0xCA2C, 0xA487, 0xCA2D, 0xA488, 0xCA2E, 0xA489, 0xCA2F,	0xA48A, 0xCA30, 0xA48B, 0xCA31, 0xA48C, 0xCA32, 0xA48D, 0xCA33,
+	0xA48E, 0xCA34, 0xA48F, 0xCA35, 0xA490, 0xCA36, 0xA491, 0xCA37,	0xA492, 0xCA38, 0xA493, 0xCA39, 0xA494, 0xCA3A, 0xA495, 0xCA3B,
+	0xA496, 0xCA3C, 0xA497, 0xCA3D, 0xA498, 0xCA3E, 0xA499, 0xCA3F,	0xA49A, 0xCA40, 0xA49B, 0xCA41, 0xA49C, 0xCA42, 0xA49D, 0xCA43,
+	0xA49E, 0xCA44, 0xA49F, 0xCA45, 0xA4A0, 0xCA46, 0xA4A1, 0x3131,	0xA4A2, 0x3132, 0xA4A3, 0x3133, 0xA4A4, 0x3134, 0xA4A5, 0x3135,
+	0xA4A6, 0x3136, 0xA4A7, 0x3137, 0xA4A8, 0x3138, 0xA4A9, 0x3139,	0xA4AA, 0x313A, 0xA4AB, 0x313B, 0xA4AC, 0x313C, 0xA4AD, 0x313D,
+	0xA4AE, 0x313E, 0xA4AF, 0x313F, 0xA4B0, 0x3140, 0xA4B1, 0x3141,	0xA4B2, 0x3142, 0xA4B3, 0x3143, 0xA4B4, 0x3144, 0xA4B5, 0x3145,
+	0xA4B6, 0x3146, 0xA4B7, 0x3147, 0xA4B8, 0x3148, 0xA4B9, 0x3149,	0xA4BA, 0x314A, 0xA4BB, 0x314B, 0xA4BC, 0x314C, 0xA4BD, 0x314D,
+	0xA4BE, 0x314E, 0xA4BF, 0x314F, 0xA4C0, 0x3150, 0xA4C1, 0x3151,	0xA4C2, 0x3152, 0xA4C3, 0x3153, 0xA4C4, 0x3154, 0xA4C5, 0x3155,
+	0xA4C6, 0x3156, 0xA4C7, 0x3157, 0xA4C8, 0x3158, 0xA4C9, 0x3159,	0xA4CA, 0x315A, 0xA4CB, 0x315B, 0xA4CC, 0x315C, 0xA4CD, 0x315D,
+	0xA4CE, 0x315E, 0xA4CF, 0x315F, 0xA4D0, 0x3160, 0xA4D1, 0x3161,	0xA4D2, 0x3162, 0xA4D3, 0x3163, 0xA4D4, 0x3164, 0xA4D5, 0x3165,
+	0xA4D6, 0x3166, 0xA4D7, 0x3167, 0xA4D8, 0x3168, 0xA4D9, 0x3169,	0xA4DA, 0x316A, 0xA4DB, 0x316B, 0xA4DC, 0x316C, 0xA4DD, 0x316D,
+	0xA4DE, 0x316E, 0xA4DF, 0x316F, 0xA4E0, 0x3170, 0xA4E1, 0x3171,	0xA4E2, 0x3172, 0xA4E3, 0x3173, 0xA4E4, 0x3174, 0xA4E5, 0x3175,
+	0xA4E6, 0x3176, 0xA4E7, 0x3177, 0xA4E8, 0x3178, 0xA4E9, 0x3179,	0xA4EA, 0x317A, 0xA4EB, 0x317B, 0xA4EC, 0x317C, 0xA4ED, 0x317D,
+	0xA4EE, 0x317E, 0xA4EF, 0x317F, 0xA4F0, 0x3180, 0xA4F1, 0x3181,	0xA4F2, 0x3182, 0xA4F3, 0x3183, 0xA4F4, 0x3184, 0xA4F5, 0x3185,
+	0xA4F6, 0x3186, 0xA4F7, 0x3187, 0xA4F8, 0x3188, 0xA4F9, 0x3189,	0xA4FA, 0x318A, 0xA4FB, 0x318B, 0xA4FC, 0x318C, 0xA4FD, 0x318D,
+	0xA4FE, 0x318E, 0xA541, 0xCA47, 0xA542, 0xCA48, 0xA543, 0xCA49,	0xA544, 0xCA4A, 0xA545, 0xCA4B, 0xA546, 0xCA4E, 0xA547, 0xCA4F,
+	0xA548, 0xCA51, 0xA549, 0xCA52, 0xA54A, 0xCA53, 0xA54B, 0xCA55,	0xA54C, 0xCA56, 0xA54D, 0xCA57, 0xA54E, 0xCA58, 0xA54F, 0xCA59,
+	0xA550, 0xCA5A, 0xA551, 0xCA5B, 0xA552, 0xCA5E, 0xA553, 0xCA62,	0xA554, 0xCA63, 0xA555, 0xCA64, 0xA556, 0xCA65, 0xA557, 0xCA66,
+	0xA558, 0xCA67, 0xA559, 0xCA69, 0xA55A, 0xCA6A, 0xA561, 0xCA6B,	0xA562, 0xCA6C, 0xA563, 0xCA6D, 0xA564, 0xCA6E, 0xA565, 0xCA6F,
+	0xA566, 0xCA70, 0xA567, 0xCA71, 0xA568, 0xCA72, 0xA569, 0xCA73,	0xA56A, 0xCA74, 0xA56B, 0xCA75, 0xA56C, 0xCA76, 0xA56D, 0xCA77,
+	0xA56E, 0xCA78, 0xA56F, 0xCA79, 0xA570, 0xCA7A, 0xA571, 0xCA7B,	0xA572, 0xCA7C, 0xA573, 0xCA7E, 0xA574, 0xCA7F, 0xA575, 0xCA80,
+	0xA576, 0xCA81, 0xA577, 0xCA82, 0xA578, 0xCA83, 0xA579, 0xCA85,	0xA57A, 0xCA86, 0xA581, 0xCA87, 0xA582, 0xCA88, 0xA583, 0xCA89,
+	0xA584, 0xCA8A, 0xA585, 0xCA8B, 0xA586, 0xCA8C, 0xA587, 0xCA8D,	0xA588, 0xCA8E, 0xA589, 0xCA8F, 0xA58A, 0xCA90, 0xA58B, 0xCA91,
+	0xA58C, 0xCA92, 0xA58D, 0xCA93, 0xA58E, 0xCA94, 0xA58F, 0xCA95,	0xA590, 0xCA96, 0xA591, 0xCA97, 0xA592, 0xCA99, 0xA593, 0xCA9A,
+	0xA594, 0xCA9B, 0xA595, 0xCA9C, 0xA596, 0xCA9D, 0xA597, 0xCA9E,	0xA598, 0xCA9F, 0xA599, 0xCAA0, 0xA59A, 0xCAA1, 0xA59B, 0xCAA2,
+	0xA59C, 0xCAA3, 0xA59D, 0xCAA4, 0xA59E, 0xCAA5, 0xA59F, 0xCAA6,	0xA5A0, 0xCAA7, 0xA5A1, 0x2170, 0xA5A2, 0x2171, 0xA5A3, 0x2172,
+	0xA5A4, 0x2173, 0xA5A5, 0x2174, 0xA5A6, 0x2175, 0xA5A7, 0x2176,	0xA5A8, 0x2177, 0xA5A9, 0x2178, 0xA5AA, 0x2179, 0xA5B0, 0x2160,
+	0xA5B1, 0x2161, 0xA5B2, 0x2162, 0xA5B3, 0x2163, 0xA5B4, 0x2164,	0xA5B5, 0x2165, 0xA5B6, 0x2166, 0xA5B7, 0x2167, 0xA5B8, 0x2168,
+	0xA5B9, 0x2169, 0xA5C1, 0x0391, 0xA5C2, 0x0392, 0xA5C3, 0x0393,	0xA5C4, 0x0394, 0xA5C5, 0x0395, 0xA5C6, 0x0396, 0xA5C7, 0x0397,
+	0xA5C8, 0x0398, 0xA5C9, 0x0399, 0xA5CA, 0x039A, 0xA5CB, 0x039B,	0xA5CC, 0x039C, 0xA5CD, 0x039D, 0xA5CE, 0x039E, 0xA5CF, 0x039F,
+	0xA5D0, 0x03A0, 0xA5D1, 0x03A1, 0xA5D2, 0x03A3, 0xA5D3, 0x03A4,	0xA5D4, 0x03A5, 0xA5D5, 0x03A6, 0xA5D6, 0x03A7, 0xA5D7, 0x03A8,
+	0xA5D8, 0x03A9, 0xA5E1, 0x03B1, 0xA5E2, 0x03B2, 0xA5E3, 0x03B3,	0xA5E4, 0x03B4, 0xA5E5, 0x03B5, 0xA5E6, 0x03B6, 0xA5E7, 0x03B7,
+	0xA5E8, 0x03B8, 0xA5E9, 0x03B9, 0xA5EA, 0x03BA, 0xA5EB, 0x03BB,	0xA5EC, 0x03BC, 0xA5ED, 0x03BD, 0xA5EE, 0x03BE, 0xA5EF, 0x03BF,
+	0xA5F0, 0x03C0, 0xA5F1, 0x03C1, 0xA5F2, 0x03C3, 0xA5F3, 0x03C4,	0xA5F4, 0x03C5, 0xA5F5, 0x03C6, 0xA5F6, 0x03C7, 0xA5F7, 0x03C8,
+	0xA5F8, 0x03C9, 0xA641, 0xCAA8, 0xA642, 0xCAA9, 0xA643, 0xCAAA,	0xA644, 0xCAAB, 0xA645, 0xCAAC, 0xA646, 0xCAAD, 0xA647, 0xCAAE,
+	0xA648, 0xCAAF, 0xA649, 0xCAB0, 0xA64A, 0xCAB1, 0xA64B, 0xCAB2,	0xA64C, 0xCAB3, 0xA64D, 0xCAB4, 0xA64E, 0xCAB5, 0xA64F, 0xCAB6,
+	0xA650, 0xCAB7, 0xA651, 0xCAB8, 0xA652, 0xCAB9, 0xA653, 0xCABA,	0xA654, 0xCABB, 0xA655, 0xCABE, 0xA656, 0xCABF, 0xA657, 0xCAC1,
+	0xA658, 0xCAC2, 0xA659, 0xCAC3, 0xA65A, 0xCAC5, 0xA661, 0xCAC6,	0xA662, 0xCAC7, 0xA663, 0xCAC8, 0xA664, 0xCAC9, 0xA665, 0xCACA,
+	0xA666, 0xCACB, 0xA667, 0xCACE, 0xA668, 0xCAD0, 0xA669, 0xCAD2,	0xA66A, 0xCAD4, 0xA66B, 0xCAD5, 0xA66C, 0xCAD6, 0xA66D, 0xCAD7,
+	0xA66E, 0xCADA, 0xA66F, 0xCADB, 0xA670, 0xCADC, 0xA671, 0xCADD,	0xA672, 0xCADE, 0xA673, 0xCADF, 0xA674, 0xCAE1, 0xA675, 0xCAE2,
+	0xA676, 0xCAE3, 0xA677, 0xCAE4, 0xA678, 0xCAE5, 0xA679, 0xCAE6,	0xA67A, 0xCAE7, 0xA681, 0xCAE8, 0xA682, 0xCAE9, 0xA683, 0xCAEA,
+	0xA684, 0xCAEB, 0xA685, 0xCAED, 0xA686, 0xCAEE, 0xA687, 0xCAEF,	0xA688, 0xCAF0, 0xA689, 0xCAF1, 0xA68A, 0xCAF2, 0xA68B, 0xCAF3,
+	0xA68C, 0xCAF5, 0xA68D, 0xCAF6, 0xA68E, 0xCAF7, 0xA68F, 0xCAF8,	0xA690, 0xCAF9, 0xA691, 0xCAFA, 0xA692, 0xCAFB, 0xA693, 0xCAFC,
+	0xA694, 0xCAFD, 0xA695, 0xCAFE, 0xA696, 0xCAFF, 0xA697, 0xCB00,	0xA698, 0xCB01, 0xA699, 0xCB02, 0xA69A, 0xCB03, 0xA69B, 0xCB04,
+	0xA69C, 0xCB05, 0xA69D, 0xCB06, 0xA69E, 0xCB07, 0xA69F, 0xCB09,	0xA6A0, 0xCB0A, 0xA6A1, 0x2500, 0xA6A2, 0x2502, 0xA6A3, 0x250C,
+	0xA6A4, 0x2510, 0xA6A5, 0x2518, 0xA6A6, 0x2514, 0xA6A7, 0x251C,	0xA6A8, 0x252C, 0xA6A9, 0x2524, 0xA6AA, 0x2534, 0xA6AB, 0x253C,
+	0xA6AC, 0x2501, 0xA6AD, 0x2503, 0xA6AE, 0x250F, 0xA6AF, 0x2513,	0xA6B0, 0x251B, 0xA6B1, 0x2517, 0xA6B2, 0x2523, 0xA6B3, 0x2533,
+	0xA6B4, 0x252B, 0xA6B5, 0x253B, 0xA6B6, 0x254B, 0xA6B7, 0x2520,	0xA6B8, 0x252F, 0xA6B9, 0x2528, 0xA6BA, 0x2537, 0xA6BB, 0x253F,
+	0xA6BC, 0x251D, 0xA6BD, 0x2530, 0xA6BE, 0x2525, 0xA6BF, 0x2538,	0xA6C0, 0x2542, 0xA6C1, 0x2512, 0xA6C2, 0x2511, 0xA6C3, 0x251A,
+	0xA6C4, 0x2519, 0xA6C5, 0x2516, 0xA6C6, 0x2515, 0xA6C7, 0x250E,	0xA6C8, 0x250D, 0xA6C9, 0x251E, 0xA6CA, 0x251F, 0xA6CB, 0x2521,
+	0xA6CC, 0x2522, 0xA6CD, 0x2526, 0xA6CE, 0x2527, 0xA6CF, 0x2529,	0xA6D0, 0x252A, 0xA6D1, 0x252D, 0xA6D2, 0x252E, 0xA6D3, 0x2531,
+	0xA6D4, 0x2532, 0xA6D5, 0x2535, 0xA6D6, 0x2536, 0xA6D7, 0x2539,	0xA6D8, 0x253A, 0xA6D9, 0x253D, 0xA6DA, 0x253E, 0xA6DB, 0x2540,
+	0xA6DC, 0x2541, 0xA6DD, 0x2543, 0xA6DE, 0x2544, 0xA6DF, 0x2545,	0xA6E0, 0x2546, 0xA6E1, 0x2547, 0xA6E2, 0x2548, 0xA6E3, 0x2549,
+	0xA6E4, 0x254A, 0xA741, 0xCB0B, 0xA742, 0xCB0C, 0xA743, 0xCB0D,	0xA744, 0xCB0E, 0xA745, 0xCB0F, 0xA746, 0xCB11, 0xA747, 0xCB12,
+	0xA748, 0xCB13, 0xA749, 0xCB15, 0xA74A, 0xCB16, 0xA74B, 0xCB17,	0xA74C, 0xCB19, 0xA74D, 0xCB1A, 0xA74E, 0xCB1B, 0xA74F, 0xCB1C,
+	0xA750, 0xCB1D, 0xA751, 0xCB1E, 0xA752, 0xCB1F, 0xA753, 0xCB22,	0xA754, 0xCB23, 0xA755, 0xCB24, 0xA756, 0xCB25, 0xA757, 0xCB26,
+	0xA758, 0xCB27, 0xA759, 0xCB28, 0xA75A, 0xCB29, 0xA761, 0xCB2A,	0xA762, 0xCB2B, 0xA763, 0xCB2C, 0xA764, 0xCB2D, 0xA765, 0xCB2E,
+	0xA766, 0xCB2F, 0xA767, 0xCB30, 0xA768, 0xCB31, 0xA769, 0xCB32,	0xA76A, 0xCB33, 0xA76B, 0xCB34, 0xA76C, 0xCB35, 0xA76D, 0xCB36,
+	0xA76E, 0xCB37, 0xA76F, 0xCB38, 0xA770, 0xCB39, 0xA771, 0xCB3A,	0xA772, 0xCB3B, 0xA773, 0xCB3C, 0xA774, 0xCB3D, 0xA775, 0xCB3E,
+	0xA776, 0xCB3F, 0xA777, 0xCB40, 0xA778, 0xCB42, 0xA779, 0xCB43,	0xA77A, 0xCB44, 0xA781, 0xCB45, 0xA782, 0xCB46, 0xA783, 0xCB47,
+	0xA784, 0xCB4A, 0xA785, 0xCB4B, 0xA786, 0xCB4D, 0xA787, 0xCB4E,	0xA788, 0xCB4F, 0xA789, 0xCB51, 0xA78A, 0xCB52, 0xA78B, 0xCB53,
+	0xA78C, 0xCB54, 0xA78D, 0xCB55, 0xA78E, 0xCB56, 0xA78F, 0xCB57,	0xA790, 0xCB5A, 0xA791, 0xCB5B, 0xA792, 0xCB5C, 0xA793, 0xCB5E,
+	0xA794, 0xCB5F, 0xA795, 0xCB60, 0xA796, 0xCB61, 0xA797, 0xCB62,	0xA798, 0xCB63, 0xA799, 0xCB65, 0xA79A, 0xCB66, 0xA79B, 0xCB67,
+	0xA79C, 0xCB68, 0xA79D, 0xCB69, 0xA79E, 0xCB6A, 0xA79F, 0xCB6B,	0xA7A0, 0xCB6C, 0xA7A1, 0x3395, 0xA7A2, 0x3396, 0xA7A3, 0x3397,
+	0xA7A4, 0x2113, 0xA7A5, 0x3398, 0xA7A6, 0x33C4, 0xA7A7, 0x33A3,	0xA7A8, 0x33A4, 0xA7A9, 0x33A5, 0xA7AA, 0x33A6, 0xA7AB, 0x3399,
+	0xA7AC, 0x339A, 0xA7AD, 0x339B, 0xA7AE, 0x339C, 0xA7AF, 0x339D,	0xA7B0, 0x339E, 0xA7B1, 0x339F, 0xA7B2, 0x33A0, 0xA7B3, 0x33A1,
+	0xA7B4, 0x33A2, 0xA7B5, 0x33CA, 0xA7B6, 0x338D, 0xA7B7, 0x338E,	0xA7B8, 0x338F, 0xA7B9, 0x33CF, 0xA7BA, 0x3388, 0xA7BB, 0x3389,
+	0xA7BC, 0x33C8, 0xA7BD, 0x33A7, 0xA7BE, 0x33A8, 0xA7BF, 0x33B0,	0xA7C0, 0x33B1, 0xA7C1, 0x33B2, 0xA7C2, 0x33B3, 0xA7C3, 0x33B4,
+	0xA7C4, 0x33B5, 0xA7C5, 0x33B6, 0xA7C6, 0x33B7, 0xA7C7, 0x33B8,	0xA7C8, 0x33B9, 0xA7C9, 0x3380, 0xA7CA, 0x3381, 0xA7CB, 0x3382,
+	0xA7CC, 0x3383, 0xA7CD, 0x3384, 0xA7CE, 0x33BA, 0xA7CF, 0x33BB,	0xA7D0, 0x33BC, 0xA7D1, 0x33BD, 0xA7D2, 0x33BE, 0xA7D3, 0x33BF,
+	0xA7D4, 0x3390, 0xA7D5, 0x3391, 0xA7D6, 0x3392, 0xA7D7, 0x3393,	0xA7D8, 0x3394, 0xA7D9, 0x2126, 0xA7DA, 0x33C0, 0xA7DB, 0x33C1,
+	0xA7DC, 0x338A, 0xA7DD, 0x338B, 0xA7DE, 0x338C, 0xA7DF, 0x33D6,	0xA7E0, 0x33C5, 0xA7E1, 0x33AD, 0xA7E2, 0x33AE, 0xA7E3, 0x33AF,
+	0xA7E4, 0x33DB, 0xA7E5, 0x33A9, 0xA7E6, 0x33AA, 0xA7E7, 0x33AB,	0xA7E8, 0x33AC, 0xA7E9, 0x33DD, 0xA7EA, 0x33D0, 0xA7EB, 0x33D3,
+	0xA7EC, 0x33C3, 0xA7ED, 0x33C9, 0xA7EE, 0x33DC, 0xA7EF, 0x33C6,	0xA841, 0xCB6D, 0xA842, 0xCB6E, 0xA843, 0xCB6F, 0xA844, 0xCB70,
+	0xA845, 0xCB71, 0xA846, 0xCB72, 0xA847, 0xCB73, 0xA848, 0xCB74,	0xA849, 0xCB75, 0xA84A, 0xCB76, 0xA84B, 0xCB77, 0xA84C, 0xCB7A,
+	0xA84D, 0xCB7B, 0xA84E, 0xCB7C, 0xA84F, 0xCB7D, 0xA850, 0xCB7E,	0xA851, 0xCB7F, 0xA852, 0xCB80, 0xA853, 0xCB81, 0xA854, 0xCB82,
+	0xA855, 0xCB83, 0xA856, 0xCB84, 0xA857, 0xCB85, 0xA858, 0xCB86,	0xA859, 0xCB87, 0xA85A, 0xCB88, 0xA861, 0xCB89, 0xA862, 0xCB8A,
+	0xA863, 0xCB8B, 0xA864, 0xCB8C, 0xA865, 0xCB8D, 0xA866, 0xCB8E,	0xA867, 0xCB8F, 0xA868, 0xCB90, 0xA869, 0xCB91, 0xA86A, 0xCB92,
+	0xA86B, 0xCB93, 0xA86C, 0xCB94, 0xA86D, 0xCB95, 0xA86E, 0xCB96,	0xA86F, 0xCB97, 0xA870, 0xCB98, 0xA871, 0xCB99, 0xA872, 0xCB9A,
+	0xA873, 0xCB9B, 0xA874, 0xCB9D, 0xA875, 0xCB9E, 0xA876, 0xCB9F,	0xA877, 0xCBA0, 0xA878, 0xCBA1, 0xA879, 0xCBA2, 0xA87A, 0xCBA3,
+	0xA881, 0xCBA4, 0xA882, 0xCBA5, 0xA883, 0xCBA6, 0xA884, 0xCBA7,	0xA885, 0xCBA8, 0xA886, 0xCBA9, 0xA887, 0xCBAA, 0xA888, 0xCBAB,
+	0xA889, 0xCBAC, 0xA88A, 0xCBAD, 0xA88B, 0xCBAE, 0xA88C, 0xCBAF,	0xA88D, 0xCBB0, 0xA88E, 0xCBB1, 0xA88F, 0xCBB2, 0xA890, 0xCBB3,
+	0xA891, 0xCBB4, 0xA892, 0xCBB5, 0xA893, 0xCBB6, 0xA894, 0xCBB7,	0xA895, 0xCBB9, 0xA896, 0xCBBA, 0xA897, 0xCBBB, 0xA898, 0xCBBC,
+	0xA899, 0xCBBD, 0xA89A, 0xCBBE, 0xA89B, 0xCBBF, 0xA89C, 0xCBC0,	0xA89D, 0xCBC1, 0xA89E, 0xCBC2, 0xA89F, 0xCBC3, 0xA8A0, 0xCBC4,
+	0xA8A1, 0x00C6, 0xA8A2, 0x00D0, 0xA8A3, 0x00AA, 0xA8A4, 0x0126,	0xA8A6, 0x0132, 0xA8A8, 0x013F, 0xA8A9, 0x0141, 0xA8AA, 0x00D8,
+	0xA8AB, 0x0152, 0xA8AC, 0x00BA, 0xA8AD, 0x00DE, 0xA8AE, 0x0166,	0xA8AF, 0x014A, 0xA8B1, 0x3260, 0xA8B2, 0x3261, 0xA8B3, 0x3262,
+	0xA8B4, 0x3263, 0xA8B5, 0x3264, 0xA8B6, 0x3265, 0xA8B7, 0x3266,	0xA8B8, 0x3267, 0xA8B9, 0x3268, 0xA8BA, 0x3269, 0xA8BB, 0x326A,
+	0xA8BC, 0x326B, 0xA8BD, 0x326C, 0xA8BE, 0x326D, 0xA8BF, 0x326E,	0xA8C0, 0x326F, 0xA8C1, 0x3270, 0xA8C2, 0x3271, 0xA8C3, 0x3272,
+	0xA8C4, 0x3273, 0xA8C5, 0x3274, 0xA8C6, 0x3275, 0xA8C7, 0x3276,	0xA8C8, 0x3277, 0xA8C9, 0x3278, 0xA8CA, 0x3279, 0xA8CB, 0x327A,
+	0xA8CC, 0x327B, 0xA8CD, 0x24D0, 0xA8CE, 0x24D1, 0xA8CF, 0x24D2,	0xA8D0, 0x24D3, 0xA8D1, 0x24D4, 0xA8D2, 0x24D5, 0xA8D3, 0x24D6,
+	0xA8D4, 0x24D7, 0xA8D5, 0x24D8, 0xA8D6, 0x24D9, 0xA8D7, 0x24DA,	0xA8D8, 0x24DB, 0xA8D9, 0x24DC, 0xA8DA, 0x24DD, 0xA8DB, 0x24DE,
+	0xA8DC, 0x24DF, 0xA8DD, 0x24E0, 0xA8DE, 0x24E1, 0xA8DF, 0x24E2,	0xA8E0, 0x24E3, 0xA8E1, 0x24E4, 0xA8E2, 0x24E5, 0xA8E3, 0x24E6,
+	0xA8E4, 0x24E7, 0xA8E5, 0x24E8, 0xA8E6, 0x24E9, 0xA8E7, 0x2460,	0xA8E8, 0x2461, 0xA8E9, 0x2462, 0xA8EA, 0x2463, 0xA8EB, 0x2464,
+	0xA8EC, 0x2465, 0xA8ED, 0x2466, 0xA8EE, 0x2467, 0xA8EF, 0x2468,	0xA8F0, 0x2469, 0xA8F1, 0x246A, 0xA8F2, 0x246B, 0xA8F3, 0x246C,
+	0xA8F4, 0x246D, 0xA8F5, 0x246E, 0xA8F6, 0x00BD, 0xA8F7, 0x2153,	0xA8F8, 0x2154, 0xA8F9, 0x00BC, 0xA8FA, 0x00BE, 0xA8FB, 0x215B,
+	0xA8FC, 0x215C, 0xA8FD, 0x215D, 0xA8FE, 0x215E, 0xA941, 0xCBC5,	0xA942, 0xCBC6, 0xA943, 0xCBC7, 0xA944, 0xCBC8, 0xA945, 0xCBC9,
+	0xA946, 0xCBCA, 0xA947, 0xCBCB, 0xA948, 0xCBCC, 0xA949, 0xCBCD,	0xA94A, 0xCBCE, 0xA94B, 0xCBCF, 0xA94C, 0xCBD0, 0xA94D, 0xCBD1,
+	0xA94E, 0xCBD2, 0xA94F, 0xCBD3, 0xA950, 0xCBD5, 0xA951, 0xCBD6,	0xA952, 0xCBD7, 0xA953, 0xCBD8, 0xA954, 0xCBD9, 0xA955, 0xCBDA,
+	0xA956, 0xCBDB, 0xA957, 0xCBDC, 0xA958, 0xCBDD, 0xA959, 0xCBDE,	0xA95A, 0xCBDF, 0xA961, 0xCBE0, 0xA962, 0xCBE1, 0xA963, 0xCBE2,
+	0xA964, 0xCBE3, 0xA965, 0xCBE5, 0xA966, 0xCBE6, 0xA967, 0xCBE8,	0xA968, 0xCBEA, 0xA969, 0xCBEB, 0xA96A, 0xCBEC, 0xA96B, 0xCBED,
+	0xA96C, 0xCBEE, 0xA96D, 0xCBEF, 0xA96E, 0xCBF0, 0xA96F, 0xCBF1,	0xA970, 0xCBF2, 0xA971, 0xCBF3, 0xA972, 0xCBF4, 0xA973, 0xCBF5,
+	0xA974, 0xCBF6, 0xA975, 0xCBF7, 0xA976, 0xCBF8, 0xA977, 0xCBF9,	0xA978, 0xCBFA, 0xA979, 0xCBFB, 0xA97A, 0xCBFC, 0xA981, 0xCBFD,
+	0xA982, 0xCBFE, 0xA983, 0xCBFF, 0xA984, 0xCC00, 0xA985, 0xCC01,	0xA986, 0xCC02, 0xA987, 0xCC03, 0xA988, 0xCC04, 0xA989, 0xCC05,
+	0xA98A, 0xCC06, 0xA98B, 0xCC07, 0xA98C, 0xCC08, 0xA98D, 0xCC09,	0xA98E, 0xCC0A, 0xA98F, 0xCC0B, 0xA990, 0xCC0E, 0xA991, 0xCC0F,
+	0xA992, 0xCC11, 0xA993, 0xCC12, 0xA994, 0xCC13, 0xA995, 0xCC15,	0xA996, 0xCC16, 0xA997, 0xCC17, 0xA998, 0xCC18, 0xA999, 0xCC19,
+	0xA99A, 0xCC1A, 0xA99B, 0xCC1B, 0xA99C, 0xCC1E, 0xA99D, 0xCC1F,	0xA99E, 0xCC20, 0xA99F, 0xCC23, 0xA9A0, 0xCC24, 0xA9A1, 0x00E6,
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+	0xAE6F, 0xCDF3, 0xAE70, 0xCDF4, 0xAE71, 0xCDF5, 0xAE72, 0xCDF6,	0xAE73, 0xCDF7, 0xAE74, 0xCDFA, 0xAE75, 0xCDFC, 0xAE76, 0xCDFE,
+	0xAE77, 0xCDFF, 0xAE78, 0xCE00, 0xAE79, 0xCE01, 0xAE7A, 0xCE02,	0xAE81, 0xCE03, 0xAE82, 0xCE05, 0xAE83, 0xCE06, 0xAE84, 0xCE07,
+	0xAE85, 0xCE09, 0xAE86, 0xCE0A, 0xAE87, 0xCE0B, 0xAE88, 0xCE0D,	0xAE89, 0xCE0E, 0xAE8A, 0xCE0F, 0xAE8B, 0xCE10, 0xAE8C, 0xCE11,
+	0xAE8D, 0xCE12, 0xAE8E, 0xCE13, 0xAE8F, 0xCE15, 0xAE90, 0xCE16,	0xAE91, 0xCE17, 0xAE92, 0xCE18, 0xAE93, 0xCE1A, 0xAE94, 0xCE1B,
+	0xAE95, 0xCE1C, 0xAE96, 0xCE1D, 0xAE97, 0xCE1E, 0xAE98, 0xCE1F,	0xAE99, 0xCE22, 0xAE9A, 0xCE23, 0xAE9B, 0xCE25, 0xAE9C, 0xCE26,
+	0xAE9D, 0xCE27, 0xAE9E, 0xCE29, 0xAE9F, 0xCE2A, 0xAEA0, 0xCE2B,	0xAF41, 0xCE2C, 0xAF42, 0xCE2D, 0xAF43, 0xCE2E, 0xAF44, 0xCE2F,
+	0xAF45, 0xCE32, 0xAF46, 0xCE34, 0xAF47, 0xCE36, 0xAF48, 0xCE37,	0xAF49, 0xCE38, 0xAF4A, 0xCE39, 0xAF4B, 0xCE3A, 0xAF4C, 0xCE3B,
+	0xAF4D, 0xCE3C, 0xAF4E, 0xCE3D, 0xAF4F, 0xCE3E, 0xAF50, 0xCE3F,	0xAF51, 0xCE40, 0xAF52, 0xCE41, 0xAF53, 0xCE42, 0xAF54, 0xCE43,
+	0xAF55, 0xCE44, 0xAF56, 0xCE45, 0xAF57, 0xCE46, 0xAF58, 0xCE47,	0xAF59, 0xCE48, 0xAF5A, 0xCE49, 0xAF61, 0xCE4A, 0xAF62, 0xCE4B,
+	0xAF63, 0xCE4C, 0xAF64, 0xCE4D, 0xAF65, 0xCE4E, 0xAF66, 0xCE4F,	0xAF67, 0xCE50, 0xAF68, 0xCE51, 0xAF69, 0xCE52, 0xAF6A, 0xCE53,
+	0xAF6B, 0xCE54, 0xAF6C, 0xCE55, 0xAF6D, 0xCE56, 0xAF6E, 0xCE57,	0xAF6F, 0xCE5A, 0xAF70, 0xCE5B, 0xAF71, 0xCE5D, 0xAF72, 0xCE5E,
+	0xAF73, 0xCE62, 0xAF74, 0xCE63, 0xAF75, 0xCE64, 0xAF76, 0xCE65,	0xAF77, 0xCE66, 0xAF78, 0xCE67, 0xAF79, 0xCE6A, 0xAF7A, 0xCE6C,
+	0xAF81, 0xCE6E, 0xAF82, 0xCE6F, 0xAF83, 0xCE70, 0xAF84, 0xCE71,	0xAF85, 0xCE72, 0xAF86, 0xCE73, 0xAF87, 0xCE76, 0xAF88, 0xCE77,
+	0xAF89, 0xCE79, 0xAF8A, 0xCE7A, 0xAF8B, 0xCE7B, 0xAF8C, 0xCE7D,	0xAF8D, 0xCE7E, 0xAF8E, 0xCE7F, 0xAF8F, 0xCE80, 0xAF90, 0xCE81,
+	0xAF91, 0xCE82, 0xAF92, 0xCE83, 0xAF93, 0xCE86, 0xAF94, 0xCE88,	0xAF95, 0xCE8A, 0xAF96, 0xCE8B, 0xAF97, 0xCE8C, 0xAF98, 0xCE8D,
+	0xAF99, 0xCE8E, 0xAF9A, 0xCE8F, 0xAF9B, 0xCE92, 0xAF9C, 0xCE93,	0xAF9D, 0xCE95, 0xAF9E, 0xCE96, 0xAF9F, 0xCE97, 0xAFA0, 0xCE99,
+	0xB041, 0xCE9A, 0xB042, 0xCE9B, 0xB043, 0xCE9C, 0xB044, 0xCE9D,	0xB045, 0xCE9E, 0xB046, 0xCE9F, 0xB047, 0xCEA2, 0xB048, 0xCEA6,
+	0xB049, 0xCEA7, 0xB04A, 0xCEA8, 0xB04B, 0xCEA9, 0xB04C, 0xCEAA,	0xB04D, 0xCEAB, 0xB04E, 0xCEAE, 0xB04F, 0xCEAF, 0xB050, 0xCEB0,
+	0xB051, 0xCEB1, 0xB052, 0xCEB2, 0xB053, 0xCEB3, 0xB054, 0xCEB4,	0xB055, 0xCEB5, 0xB056, 0xCEB6, 0xB057, 0xCEB7, 0xB058, 0xCEB8,
+	0xB059, 0xCEB9, 0xB05A, 0xCEBA, 0xB061, 0xCEBB, 0xB062, 0xCEBC,	0xB063, 0xCEBD, 0xB064, 0xCEBE, 0xB065, 0xCEBF, 0xB066, 0xCEC0,
+	0xB067, 0xCEC2, 0xB068, 0xCEC3, 0xB069, 0xCEC4, 0xB06A, 0xCEC5,	0xB06B, 0xCEC6, 0xB06C, 0xCEC7, 0xB06D, 0xCEC8, 0xB06E, 0xCEC9,
+	0xB06F, 0xCECA, 0xB070, 0xCECB, 0xB071, 0xCECC, 0xB072, 0xCECD,	0xB073, 0xCECE, 0xB074, 0xCECF, 0xB075, 0xCED0, 0xB076, 0xCED1,
+	0xB077, 0xCED2, 0xB078, 0xCED3, 0xB079, 0xCED4, 0xB07A, 0xCED5,	0xB081, 0xCED6, 0xB082, 0xCED7, 0xB083, 0xCED8, 0xB084, 0xCED9,
+	0xB085, 0xCEDA, 0xB086, 0xCEDB, 0xB087, 0xCEDC, 0xB088, 0xCEDD,	0xB089, 0xCEDE, 0xB08A, 0xCEDF, 0xB08B, 0xCEE0, 0xB08C, 0xCEE1,
+	0xB08D, 0xCEE2, 0xB08E, 0xCEE3, 0xB08F, 0xCEE6, 0xB090, 0xCEE7,	0xB091, 0xCEE9, 0xB092, 0xCEEA, 0xB093, 0xCEED, 0xB094, 0xCEEE,
+	0xB095, 0xCEEF, 0xB096, 0xCEF0, 0xB097, 0xCEF1, 0xB098, 0xCEF2,	0xB099, 0xCEF3, 0xB09A, 0xCEF6, 0xB09B, 0xCEFA, 0xB09C, 0xCEFB,
+	0xB09D, 0xCEFC, 0xB09E, 0xCEFD, 0xB09F, 0xCEFE, 0xB0A0, 0xCEFF,	0xB0A1, 0xAC00, 0xB0A2, 0xAC01, 0xB0A3, 0xAC04, 0xB0A4, 0xAC07,
+	0xB0A5, 0xAC08, 0xB0A6, 0xAC09, 0xB0A7, 0xAC0A, 0xB0A8, 0xAC10,	0xB0A9, 0xAC11, 0xB0AA, 0xAC12, 0xB0AB, 0xAC13, 0xB0AC, 0xAC14,
+	0xB0AD, 0xAC15, 0xB0AE, 0xAC16, 0xB0AF, 0xAC17, 0xB0B0, 0xAC19,	0xB0B1, 0xAC1A, 0xB0B2, 0xAC1B, 0xB0B3, 0xAC1C, 0xB0B4, 0xAC1D,
+	0xB0B5, 0xAC20, 0xB0B6, 0xAC24, 0xB0B7, 0xAC2C, 0xB0B8, 0xAC2D,	0xB0B9, 0xAC2F, 0xB0BA, 0xAC30, 0xB0BB, 0xAC31, 0xB0BC, 0xAC38,
+	0xB0BD, 0xAC39, 0xB0BE, 0xAC3C, 0xB0BF, 0xAC40, 0xB0C0, 0xAC4B,	0xB0C1, 0xAC4D, 0xB0C2, 0xAC54, 0xB0C3, 0xAC58, 0xB0C4, 0xAC5C,
+	0xB0C5, 0xAC70, 0xB0C6, 0xAC71, 0xB0C7, 0xAC74, 0xB0C8, 0xAC77,	0xB0C9, 0xAC78, 0xB0CA, 0xAC7A, 0xB0CB, 0xAC80, 0xB0CC, 0xAC81,
+	0xB0CD, 0xAC83, 0xB0CE, 0xAC84, 0xB0CF, 0xAC85, 0xB0D0, 0xAC86,	0xB0D1, 0xAC89, 0xB0D2, 0xAC8A, 0xB0D3, 0xAC8B, 0xB0D4, 0xAC8C,
+	0xB0D5, 0xAC90, 0xB0D6, 0xAC94, 0xB0D7, 0xAC9C, 0xB0D8, 0xAC9D,	0xB0D9, 0xAC9F, 0xB0DA, 0xACA0, 0xB0DB, 0xACA1, 0xB0DC, 0xACA8,
+	0xB0DD, 0xACA9, 0xB0DE, 0xACAA, 0xB0DF, 0xACAC, 0xB0E0, 0xACAF,	0xB0E1, 0xACB0, 0xB0E2, 0xACB8, 0xB0E3, 0xACB9, 0xB0E4, 0xACBB,
+	0xB0E5, 0xACBC, 0xB0E6, 0xACBD, 0xB0E7, 0xACC1, 0xB0E8, 0xACC4,	0xB0E9, 0xACC8, 0xB0EA, 0xACCC, 0xB0EB, 0xACD5, 0xB0EC, 0xACD7,
+	0xB0ED, 0xACE0, 0xB0EE, 0xACE1, 0xB0EF, 0xACE4, 0xB0F0, 0xACE7,	0xB0F1, 0xACE8, 0xB0F2, 0xACEA, 0xB0F3, 0xACEC, 0xB0F4, 0xACEF,
+	0xB0F5, 0xACF0, 0xB0F6, 0xACF1, 0xB0F7, 0xACF3, 0xB0F8, 0xACF5,	0xB0F9, 0xACF6, 0xB0FA, 0xACFC, 0xB0FB, 0xACFD, 0xB0FC, 0xAD00,
+	0xB0FD, 0xAD04, 0xB0FE, 0xAD06, 0xB141, 0xCF02, 0xB142, 0xCF03,	0xB143, 0xCF05, 0xB144, 0xCF06, 0xB145, 0xCF07, 0xB146, 0xCF09,
+	0xB147, 0xCF0A, 0xB148, 0xCF0B, 0xB149, 0xCF0C, 0xB14A, 0xCF0D,	0xB14B, 0xCF0E, 0xB14C, 0xCF0F, 0xB14D, 0xCF12, 0xB14E, 0xCF14,
+	0xB14F, 0xCF16, 0xB150, 0xCF17, 0xB151, 0xCF18, 0xB152, 0xCF19,	0xB153, 0xCF1A, 0xB154, 0xCF1B, 0xB155, 0xCF1D, 0xB156, 0xCF1E,
+	0xB157, 0xCF1F, 0xB158, 0xCF21, 0xB159, 0xCF22, 0xB15A, 0xCF23,	0xB161, 0xCF25, 0xB162, 0xCF26, 0xB163, 0xCF27, 0xB164, 0xCF28,
+	0xB165, 0xCF29, 0xB166, 0xCF2A, 0xB167, 0xCF2B, 0xB168, 0xCF2E,	0xB169, 0xCF32, 0xB16A, 0xCF33, 0xB16B, 0xCF34, 0xB16C, 0xCF35,
+	0xB16D, 0xCF36, 0xB16E, 0xCF37, 0xB16F, 0xCF39, 0xB170, 0xCF3A,	0xB171, 0xCF3B, 0xB172, 0xCF3C, 0xB173, 0xCF3D, 0xB174, 0xCF3E,
+	0xB175, 0xCF3F, 0xB176, 0xCF40, 0xB177, 0xCF41, 0xB178, 0xCF42,	0xB179, 0xCF43, 0xB17A, 0xCF44, 0xB181, 0xCF45, 0xB182, 0xCF46,
+	0xB183, 0xCF47, 0xB184, 0xCF48, 0xB185, 0xCF49, 0xB186, 0xCF4A,	0xB187, 0xCF4B, 0xB188, 0xCF4C, 0xB189, 0xCF4D, 0xB18A, 0xCF4E,
+	0xB18B, 0xCF4F, 0xB18C, 0xCF50, 0xB18D, 0xCF51, 0xB18E, 0xCF52,	0xB18F, 0xCF53, 0xB190, 0xCF56, 0xB191, 0xCF57, 0xB192, 0xCF59,
+	0xB193, 0xCF5A, 0xB194, 0xCF5B, 0xB195, 0xCF5D, 0xB196, 0xCF5E,	0xB197, 0xCF5F, 0xB198, 0xCF60, 0xB199, 0xCF61, 0xB19A, 0xCF62,
+	0xB19B, 0xCF63, 0xB19C, 0xCF66, 0xB19D, 0xCF68, 0xB19E, 0xCF6A,	0xB19F, 0xCF6B, 0xB1A0, 0xCF6C, 0xB1A1, 0xAD0C, 0xB1A2, 0xAD0D,
+	0xB1A3, 0xAD0F, 0xB1A4, 0xAD11, 0xB1A5, 0xAD18, 0xB1A6, 0xAD1C,	0xB1A7, 0xAD20, 0xB1A8, 0xAD29, 0xB1A9, 0xAD2C, 0xB1AA, 0xAD2D,
+	0xB1AB, 0xAD34, 0xB1AC, 0xAD35, 0xB1AD, 0xAD38, 0xB1AE, 0xAD3C,	0xB1AF, 0xAD44, 0xB1B0, 0xAD45, 0xB1B1, 0xAD47, 0xB1B2, 0xAD49,
+	0xB1B3, 0xAD50, 0xB1B4, 0xAD54, 0xB1B5, 0xAD58, 0xB1B6, 0xAD61,	0xB1B7, 0xAD63, 0xB1B8, 0xAD6C, 0xB1B9, 0xAD6D, 0xB1BA, 0xAD70,
+	0xB1BB, 0xAD73, 0xB1BC, 0xAD74, 0xB1BD, 0xAD75, 0xB1BE, 0xAD76,	0xB1BF, 0xAD7B, 0xB1C0, 0xAD7C, 0xB1C1, 0xAD7D, 0xB1C2, 0xAD7F,
+	0xB1C3, 0xAD81, 0xB1C4, 0xAD82, 0xB1C5, 0xAD88, 0xB1C6, 0xAD89,	0xB1C7, 0xAD8C, 0xB1C8, 0xAD90, 0xB1C9, 0xAD9C, 0xB1CA, 0xAD9D,
+	0xB1CB, 0xADA4, 0xB1CC, 0xADB7, 0xB1CD, 0xADC0, 0xB1CE, 0xADC1,	0xB1CF, 0xADC4, 0xB1D0, 0xADC8, 0xB1D1, 0xADD0, 0xB1D2, 0xADD1,
+	0xB1D3, 0xADD3, 0xB1D4, 0xADDC, 0xB1D5, 0xADE0, 0xB1D6, 0xADE4,	0xB1D7, 0xADF8, 0xB1D8, 0xADF9, 0xB1D9, 0xADFC, 0xB1DA, 0xADFF,
+	0xB1DB, 0xAE00, 0xB1DC, 0xAE01, 0xB1DD, 0xAE08, 0xB1DE, 0xAE09,	0xB1DF, 0xAE0B, 0xB1E0, 0xAE0D, 0xB1E1, 0xAE14, 0xB1E2, 0xAE30,
+	0xB1E3, 0xAE31, 0xB1E4, 0xAE34, 0xB1E5, 0xAE37, 0xB1E6, 0xAE38,	0xB1E7, 0xAE3A, 0xB1E8, 0xAE40, 0xB1E9, 0xAE41, 0xB1EA, 0xAE43,
+	0xB1EB, 0xAE45, 0xB1EC, 0xAE46, 0xB1ED, 0xAE4A, 0xB1EE, 0xAE4C,	0xB1EF, 0xAE4D, 0xB1F0, 0xAE4E, 0xB1F1, 0xAE50, 0xB1F2, 0xAE54,
+	0xB1F3, 0xAE56, 0xB1F4, 0xAE5C, 0xB1F5, 0xAE5D, 0xB1F6, 0xAE5F,	0xB1F7, 0xAE60, 0xB1F8, 0xAE61, 0xB1F9, 0xAE65, 0xB1FA, 0xAE68,
+	0xB1FB, 0xAE69, 0xB1FC, 0xAE6C, 0xB1FD, 0xAE70, 0xB1FE, 0xAE78,	0xB241, 0xCF6D, 0xB242, 0xCF6E, 0xB243, 0xCF6F, 0xB244, 0xCF72,
+	0xB245, 0xCF73, 0xB246, 0xCF75, 0xB247, 0xCF76, 0xB248, 0xCF77,	0xB249, 0xCF79, 0xB24A, 0xCF7A, 0xB24B, 0xCF7B, 0xB24C, 0xCF7C,
+	0xB24D, 0xCF7D, 0xB24E, 0xCF7E, 0xB24F, 0xCF7F, 0xB250, 0xCF81,	0xB251, 0xCF82, 0xB252, 0xCF83, 0xB253, 0xCF84, 0xB254, 0xCF86,
+	0xB255, 0xCF87, 0xB256, 0xCF88, 0xB257, 0xCF89, 0xB258, 0xCF8A,	0xB259, 0xCF8B, 0xB25A, 0xCF8D, 0xB261, 0xCF8E, 0xB262, 0xCF8F,
+	0xB263, 0xCF90, 0xB264, 0xCF91, 0xB265, 0xCF92, 0xB266, 0xCF93,	0xB267, 0xCF94, 0xB268, 0xCF95, 0xB269, 0xCF96, 0xB26A, 0xCF97,
+	0xB26B, 0xCF98, 0xB26C, 0xCF99, 0xB26D, 0xCF9A, 0xB26E, 0xCF9B,	0xB26F, 0xCF9C, 0xB270, 0xCF9D, 0xB271, 0xCF9E, 0xB272, 0xCF9F,
+	0xB273, 0xCFA0, 0xB274, 0xCFA2, 0xB275, 0xCFA3, 0xB276, 0xCFA4,	0xB277, 0xCFA5, 0xB278, 0xCFA6, 0xB279, 0xCFA7, 0xB27A, 0xCFA9,
+	0xB281, 0xCFAA, 0xB282, 0xCFAB, 0xB283, 0xCFAC, 0xB284, 0xCFAD,	0xB285, 0xCFAE, 0xB286, 0xCFAF, 0xB287, 0xCFB1, 0xB288, 0xCFB2,
+	0xB289, 0xCFB3, 0xB28A, 0xCFB4, 0xB28B, 0xCFB5, 0xB28C, 0xCFB6,	0xB28D, 0xCFB7, 0xB28E, 0xCFB8, 0xB28F, 0xCFB9, 0xB290, 0xCFBA,
+	0xB291, 0xCFBB, 0xB292, 0xCFBC, 0xB293, 0xCFBD, 0xB294, 0xCFBE,	0xB295, 0xCFBF, 0xB296, 0xCFC0, 0xB297, 0xCFC1, 0xB298, 0xCFC2,
+	0xB299, 0xCFC3, 0xB29A, 0xCFC5, 0xB29B, 0xCFC6, 0xB29C, 0xCFC7,	0xB29D, 0xCFC8, 0xB29E, 0xCFC9, 0xB29F, 0xCFCA, 0xB2A0, 0xCFCB,
+	0xB2A1, 0xAE79, 0xB2A2, 0xAE7B, 0xB2A3, 0xAE7C, 0xB2A4, 0xAE7D,	0xB2A5, 0xAE84, 0xB2A6, 0xAE85, 0xB2A7, 0xAE8C, 0xB2A8, 0xAEBC,
+	0xB2A9, 0xAEBD, 0xB2AA, 0xAEBE, 0xB2AB, 0xAEC0, 0xB2AC, 0xAEC4,	0xB2AD, 0xAECC, 0xB2AE, 0xAECD, 0xB2AF, 0xAECF, 0xB2B0, 0xAED0,
+	0xB2B1, 0xAED1, 0xB2B2, 0xAED8, 0xB2B3, 0xAED9, 0xB2B4, 0xAEDC,	0xB2B5, 0xAEE8, 0xB2B6, 0xAEEB, 0xB2B7, 0xAEED, 0xB2B8, 0xAEF4,
+	0xB2B9, 0xAEF8, 0xB2BA, 0xAEFC, 0xB2BB, 0xAF07, 0xB2BC, 0xAF08,	0xB2BD, 0xAF0D, 0xB2BE, 0xAF10, 0xB2BF, 0xAF2C, 0xB2C0, 0xAF2D,
+	0xB2C1, 0xAF30, 0xB2C2, 0xAF32, 0xB2C3, 0xAF34, 0xB2C4, 0xAF3C,	0xB2C5, 0xAF3D, 0xB2C6, 0xAF3F, 0xB2C7, 0xAF41, 0xB2C8, 0xAF42,
+	0xB2C9, 0xAF43, 0xB2CA, 0xAF48, 0xB2CB, 0xAF49, 0xB2CC, 0xAF50,	0xB2CD, 0xAF5C, 0xB2CE, 0xAF5D, 0xB2CF, 0xAF64, 0xB2D0, 0xAF65,
+	0xB2D1, 0xAF79, 0xB2D2, 0xAF80, 0xB2D3, 0xAF84, 0xB2D4, 0xAF88,	0xB2D5, 0xAF90, 0xB2D6, 0xAF91, 0xB2D7, 0xAF95, 0xB2D8, 0xAF9C,
+	0xB2D9, 0xAFB8, 0xB2DA, 0xAFB9, 0xB2DB, 0xAFBC, 0xB2DC, 0xAFC0,	0xB2DD, 0xAFC7, 0xB2DE, 0xAFC8, 0xB2DF, 0xAFC9, 0xB2E0, 0xAFCB,
+	0xB2E1, 0xAFCD, 0xB2E2, 0xAFCE, 0xB2E3, 0xAFD4, 0xB2E4, 0xAFDC,	0xB2E5, 0xAFE8, 0xB2E6, 0xAFE9, 0xB2E7, 0xAFF0, 0xB2E8, 0xAFF1,
+	0xB2E9, 0xAFF4, 0xB2EA, 0xAFF8, 0xB2EB, 0xB000, 0xB2EC, 0xB001,	0xB2ED, 0xB004, 0xB2EE, 0xB00C, 0xB2EF, 0xB010, 0xB2F0, 0xB014,
+	0xB2F1, 0xB01C, 0xB2F2, 0xB01D, 0xB2F3, 0xB028, 0xB2F4, 0xB044,	0xB2F5, 0xB045, 0xB2F6, 0xB048, 0xB2F7, 0xB04A, 0xB2F8, 0xB04C,
+	0xB2F9, 0xB04E, 0xB2FA, 0xB053, 0xB2FB, 0xB054, 0xB2FC, 0xB055,	0xB2FD, 0xB057, 0xB2FE, 0xB059, 0xB341, 0xCFCC, 0xB342, 0xCFCD,
+	0xB343, 0xCFCE, 0xB344, 0xCFCF, 0xB345, 0xCFD0, 0xB346, 0xCFD1,	0xB347, 0xCFD2, 0xB348, 0xCFD3, 0xB349, 0xCFD4, 0xB34A, 0xCFD5,
+	0xB34B, 0xCFD6, 0xB34C, 0xCFD7, 0xB34D, 0xCFD8, 0xB34E, 0xCFD9,	0xB34F, 0xCFDA, 0xB350, 0xCFDB, 0xB351, 0xCFDC, 0xB352, 0xCFDD,
+	0xB353, 0xCFDE, 0xB354, 0xCFDF, 0xB355, 0xCFE2, 0xB356, 0xCFE3,	0xB357, 0xCFE5, 0xB358, 0xCFE6, 0xB359, 0xCFE7, 0xB35A, 0xCFE9,
+	0xB361, 0xCFEA, 0xB362, 0xCFEB, 0xB363, 0xCFEC, 0xB364, 0xCFED,	0xB365, 0xCFEE, 0xB366, 0xCFEF, 0xB367, 0xCFF2, 0xB368, 0xCFF4,
+	0xB369, 0xCFF6, 0xB36A, 0xCFF7, 0xB36B, 0xCFF8, 0xB36C, 0xCFF9,	0xB36D, 0xCFFA, 0xB36E, 0xCFFB, 0xB36F, 0xCFFD, 0xB370, 0xCFFE,
+	0xB371, 0xCFFF, 0xB372, 0xD001, 0xB373, 0xD002, 0xB374, 0xD003,	0xB375, 0xD005, 0xB376, 0xD006, 0xB377, 0xD007, 0xB378, 0xD008,
+	0xB379, 0xD009, 0xB37A, 0xD00A, 0xB381, 0xD00B, 0xB382, 0xD00C,	0xB383, 0xD00D, 0xB384, 0xD00E, 0xB385, 0xD00F, 0xB386, 0xD010,
+	0xB387, 0xD012, 0xB388, 0xD013, 0xB389, 0xD014, 0xB38A, 0xD015,	0xB38B, 0xD016, 0xB38C, 0xD017, 0xB38D, 0xD019, 0xB38E, 0xD01A,
+	0xB38F, 0xD01B, 0xB390, 0xD01C, 0xB391, 0xD01D, 0xB392, 0xD01E,	0xB393, 0xD01F, 0xB394, 0xD020, 0xB395, 0xD021, 0xB396, 0xD022,
+	0xB397, 0xD023, 0xB398, 0xD024, 0xB399, 0xD025, 0xB39A, 0xD026,	0xB39B, 0xD027, 0xB39C, 0xD028, 0xB39D, 0xD029, 0xB39E, 0xD02A,
+	0xB39F, 0xD02B, 0xB3A0, 0xD02C, 0xB3A1, 0xB05D, 0xB3A2, 0xB07C,	0xB3A3, 0xB07D, 0xB3A4, 0xB080, 0xB3A5, 0xB084, 0xB3A6, 0xB08C,
+	0xB3A7, 0xB08D, 0xB3A8, 0xB08F, 0xB3A9, 0xB091, 0xB3AA, 0xB098,	0xB3AB, 0xB099, 0xB3AC, 0xB09A, 0xB3AD, 0xB09C, 0xB3AE, 0xB09F,
+	0xB3AF, 0xB0A0, 0xB3B0, 0xB0A1, 0xB3B1, 0xB0A2, 0xB3B2, 0xB0A8,	0xB3B3, 0xB0A9, 0xB3B4, 0xB0AB, 0xB3B5, 0xB0AC, 0xB3B6, 0xB0AD,
+	0xB3B7, 0xB0AE, 0xB3B8, 0xB0AF, 0xB3B9, 0xB0B1, 0xB3BA, 0xB0B3,	0xB3BB, 0xB0B4, 0xB3BC, 0xB0B5, 0xB3BD, 0xB0B8, 0xB3BE, 0xB0BC,
+	0xB3BF, 0xB0C4, 0xB3C0, 0xB0C5, 0xB3C1, 0xB0C7, 0xB3C2, 0xB0C8,	0xB3C3, 0xB0C9, 0xB3C4, 0xB0D0, 0xB3C5, 0xB0D1, 0xB3C6, 0xB0D4,
+	0xB3C7, 0xB0D8, 0xB3C8, 0xB0E0, 0xB3C9, 0xB0E5, 0xB3CA, 0xB108,	0xB3CB, 0xB109, 0xB3CC, 0xB10B, 0xB3CD, 0xB10C, 0xB3CE, 0xB110,
+	0xB3CF, 0xB112, 0xB3D0, 0xB113, 0xB3D1, 0xB118, 0xB3D2, 0xB119,	0xB3D3, 0xB11B, 0xB3D4, 0xB11C, 0xB3D5, 0xB11D, 0xB3D6, 0xB123,
+	0xB3D7, 0xB124, 0xB3D8, 0xB125, 0xB3D9, 0xB128, 0xB3DA, 0xB12C,	0xB3DB, 0xB134, 0xB3DC, 0xB135, 0xB3DD, 0xB137, 0xB3DE, 0xB138,
+	0xB3DF, 0xB139, 0xB3E0, 0xB140, 0xB3E1, 0xB141, 0xB3E2, 0xB144,	0xB3E3, 0xB148, 0xB3E4, 0xB150, 0xB3E5, 0xB151, 0xB3E6, 0xB154,
+	0xB3E7, 0xB155, 0xB3E8, 0xB158, 0xB3E9, 0xB15C, 0xB3EA, 0xB160,	0xB3EB, 0xB178, 0xB3EC, 0xB179, 0xB3ED, 0xB17C, 0xB3EE, 0xB180,
+	0xB3EF, 0xB182, 0xB3F0, 0xB188, 0xB3F1, 0xB189, 0xB3F2, 0xB18B,	0xB3F3, 0xB18D, 0xB3F4, 0xB192, 0xB3F5, 0xB193, 0xB3F6, 0xB194,
+	0xB3F7, 0xB198, 0xB3F8, 0xB19C, 0xB3F9, 0xB1A8, 0xB3FA, 0xB1CC,	0xB3FB, 0xB1D0, 0xB3FC, 0xB1D4, 0xB3FD, 0xB1DC, 0xB3FE, 0xB1DD,
+	0xB441, 0xD02E, 0xB442, 0xD02F, 0xB443, 0xD030, 0xB444, 0xD031,	0xB445, 0xD032, 0xB446, 0xD033, 0xB447, 0xD036, 0xB448, 0xD037,
+	0xB449, 0xD039, 0xB44A, 0xD03A, 0xB44B, 0xD03B, 0xB44C, 0xD03D,	0xB44D, 0xD03E, 0xB44E, 0xD03F, 0xB44F, 0xD040, 0xB450, 0xD041,
+	0xB451, 0xD042, 0xB452, 0xD043, 0xB453, 0xD046, 0xB454, 0xD048,	0xB455, 0xD04A, 0xB456, 0xD04B, 0xB457, 0xD04C, 0xB458, 0xD04D,
+	0xB459, 0xD04E, 0xB45A, 0xD04F, 0xB461, 0xD051, 0xB462, 0xD052,	0xB463, 0xD053, 0xB464, 0xD055, 0xB465, 0xD056, 0xB466, 0xD057,
+	0xB467, 0xD059, 0xB468, 0xD05A, 0xB469, 0xD05B, 0xB46A, 0xD05C,	0xB46B, 0xD05D, 0xB46C, 0xD05E, 0xB46D, 0xD05F, 0xB46E, 0xD061,
+	0xB46F, 0xD062, 0xB470, 0xD063, 0xB471, 0xD064, 0xB472, 0xD065,	0xB473, 0xD066, 0xB474, 0xD067, 0xB475, 0xD068, 0xB476, 0xD069,
+	0xB477, 0xD06A, 0xB478, 0xD06B, 0xB479, 0xD06E, 0xB47A, 0xD06F,	0xB481, 0xD071, 0xB482, 0xD072, 0xB483, 0xD073, 0xB484, 0xD075,
+	0xB485, 0xD076, 0xB486, 0xD077, 0xB487, 0xD078, 0xB488, 0xD079,	0xB489, 0xD07A, 0xB48A, 0xD07B, 0xB48B, 0xD07E, 0xB48C, 0xD07F,
+	0xB48D, 0xD080, 0xB48E, 0xD082, 0xB48F, 0xD083, 0xB490, 0xD084,	0xB491, 0xD085, 0xB492, 0xD086, 0xB493, 0xD087, 0xB494, 0xD088,
+	0xB495, 0xD089, 0xB496, 0xD08A, 0xB497, 0xD08B, 0xB498, 0xD08C,	0xB499, 0xD08D, 0xB49A, 0xD08E, 0xB49B, 0xD08F, 0xB49C, 0xD090,
+	0xB49D, 0xD091, 0xB49E, 0xD092, 0xB49F, 0xD093, 0xB4A0, 0xD094,	0xB4A1, 0xB1DF, 0xB4A2, 0xB1E8, 0xB4A3, 0xB1E9, 0xB4A4, 0xB1EC,
+	0xB4A5, 0xB1F0, 0xB4A6, 0xB1F9, 0xB4A7, 0xB1FB, 0xB4A8, 0xB1FD,	0xB4A9, 0xB204, 0xB4AA, 0xB205, 0xB4AB, 0xB208, 0xB4AC, 0xB20B,
+	0xB4AD, 0xB20C, 0xB4AE, 0xB214, 0xB4AF, 0xB215, 0xB4B0, 0xB217,	0xB4B1, 0xB219, 0xB4B2, 0xB220, 0xB4B3, 0xB234, 0xB4B4, 0xB23C,
+	0xB4B5, 0xB258, 0xB4B6, 0xB25C, 0xB4B7, 0xB260, 0xB4B8, 0xB268,	0xB4B9, 0xB269, 0xB4BA, 0xB274, 0xB4BB, 0xB275, 0xB4BC, 0xB27C,
+	0xB4BD, 0xB284, 0xB4BE, 0xB285, 0xB4BF, 0xB289, 0xB4C0, 0xB290,	0xB4C1, 0xB291, 0xB4C2, 0xB294, 0xB4C3, 0xB298, 0xB4C4, 0xB299,
+	0xB4C5, 0xB29A, 0xB4C6, 0xB2A0, 0xB4C7, 0xB2A1, 0xB4C8, 0xB2A3,	0xB4C9, 0xB2A5, 0xB4CA, 0xB2A6, 0xB4CB, 0xB2AA, 0xB4CC, 0xB2AC,
+	0xB4CD, 0xB2B0, 0xB4CE, 0xB2B4, 0xB4CF, 0xB2C8, 0xB4D0, 0xB2C9,	0xB4D1, 0xB2CC, 0xB4D2, 0xB2D0, 0xB4D3, 0xB2D2, 0xB4D4, 0xB2D8,
+	0xB4D5, 0xB2D9, 0xB4D6, 0xB2DB, 0xB4D7, 0xB2DD, 0xB4D8, 0xB2E2,	0xB4D9, 0xB2E4, 0xB4DA, 0xB2E5, 0xB4DB, 0xB2E6, 0xB4DC, 0xB2E8,
+	0xB4DD, 0xB2EB, 0xB4DE, 0xB2EC, 0xB4DF, 0xB2ED, 0xB4E0, 0xB2EE,	0xB4E1, 0xB2EF, 0xB4E2, 0xB2F3, 0xB4E3, 0xB2F4, 0xB4E4, 0xB2F5,
+	0xB4E5, 0xB2F7, 0xB4E6, 0xB2F8, 0xB4E7, 0xB2F9, 0xB4E8, 0xB2FA,	0xB4E9, 0xB2FB, 0xB4EA, 0xB2FF, 0xB4EB, 0xB300, 0xB4EC, 0xB301,
+	0xB4ED, 0xB304, 0xB4EE, 0xB308, 0xB4EF, 0xB310, 0xB4F0, 0xB311,	0xB4F1, 0xB313, 0xB4F2, 0xB314, 0xB4F3, 0xB315, 0xB4F4, 0xB31C,
+	0xB4F5, 0xB354, 0xB4F6, 0xB355, 0xB4F7, 0xB356, 0xB4F8, 0xB358,	0xB4F9, 0xB35B, 0xB4FA, 0xB35C, 0xB4FB, 0xB35E, 0xB4FC, 0xB35F,
+	0xB4FD, 0xB364, 0xB4FE, 0xB365, 0xB541, 0xD095, 0xB542, 0xD096,	0xB543, 0xD097, 0xB544, 0xD098, 0xB545, 0xD099, 0xB546, 0xD09A,
+	0xB547, 0xD09B, 0xB548, 0xD09C, 0xB549, 0xD09D, 0xB54A, 0xD09E,	0xB54B, 0xD09F, 0xB54C, 0xD0A0, 0xB54D, 0xD0A1, 0xB54E, 0xD0A2,
+	0xB54F, 0xD0A3, 0xB550, 0xD0A6, 0xB551, 0xD0A7, 0xB552, 0xD0A9,	0xB553, 0xD0AA, 0xB554, 0xD0AB, 0xB555, 0xD0AD, 0xB556, 0xD0AE,
+	0xB557, 0xD0AF, 0xB558, 0xD0B0, 0xB559, 0xD0B1, 0xB55A, 0xD0B2,	0xB561, 0xD0B3, 0xB562, 0xD0B6, 0xB563, 0xD0B8, 0xB564, 0xD0BA,
+	0xB565, 0xD0BB, 0xB566, 0xD0BC, 0xB567, 0xD0BD, 0xB568, 0xD0BE,	0xB569, 0xD0BF, 0xB56A, 0xD0C2, 0xB56B, 0xD0C3, 0xB56C, 0xD0C5,
+	0xB56D, 0xD0C6, 0xB56E, 0xD0C7, 0xB56F, 0xD0CA, 0xB570, 0xD0CB,	0xB571, 0xD0CC, 0xB572, 0xD0CD, 0xB573, 0xD0CE, 0xB574, 0xD0CF,
+	0xB575, 0xD0D2, 0xB576, 0xD0D6, 0xB577, 0xD0D7, 0xB578, 0xD0D8,	0xB579, 0xD0D9, 0xB57A, 0xD0DA, 0xB581, 0xD0DB, 0xB582, 0xD0DE,
+	0xB583, 0xD0DF, 0xB584, 0xD0E1, 0xB585, 0xD0E2, 0xB586, 0xD0E3,	0xB587, 0xD0E5, 0xB588, 0xD0E6, 0xB589, 0xD0E7, 0xB58A, 0xD0E8,
+	0xB58B, 0xD0E9, 0xB58C, 0xD0EA, 0xB58D, 0xD0EB, 0xB58E, 0xD0EE,	0xB58F, 0xD0F2, 0xB590, 0xD0F3, 0xB591, 0xD0F4, 0xB592, 0xD0F5,
+	0xB593, 0xD0F6, 0xB594, 0xD0F7, 0xB595, 0xD0F9, 0xB596, 0xD0FA,	0xB597, 0xD0FB, 0xB598, 0xD0FC, 0xB599, 0xD0FD, 0xB59A, 0xD0FE,
+	0xB59B, 0xD0FF, 0xB59C, 0xD100, 0xB59D, 0xD101, 0xB59E, 0xD102,	0xB59F, 0xD103, 0xB5A0, 0xD104, 0xB5A1, 0xB367, 0xB5A2, 0xB369,
+	0xB5A3, 0xB36B, 0xB5A4, 0xB36E, 0xB5A5, 0xB370, 0xB5A6, 0xB371,	0xB5A7, 0xB374, 0xB5A8, 0xB378, 0xB5A9, 0xB380, 0xB5AA, 0xB381,
+	0xB5AB, 0xB383, 0xB5AC, 0xB384, 0xB5AD, 0xB385, 0xB5AE, 0xB38C,	0xB5AF, 0xB390, 0xB5B0, 0xB394, 0xB5B1, 0xB3A0, 0xB5B2, 0xB3A1,
+	0xB5B3, 0xB3A8, 0xB5B4, 0xB3AC, 0xB5B5, 0xB3C4, 0xB5B6, 0xB3C5,	0xB5B7, 0xB3C8, 0xB5B8, 0xB3CB, 0xB5B9, 0xB3CC, 0xB5BA, 0xB3CE,
+	0xB5BB, 0xB3D0, 0xB5BC, 0xB3D4, 0xB5BD, 0xB3D5, 0xB5BE, 0xB3D7,	0xB5BF, 0xB3D9, 0xB5C0, 0xB3DB, 0xB5C1, 0xB3DD, 0xB5C2, 0xB3E0,
+	0xB5C3, 0xB3E4, 0xB5C4, 0xB3E8, 0xB5C5, 0xB3FC, 0xB5C6, 0xB410,	0xB5C7, 0xB418, 0xB5C8, 0xB41C, 0xB5C9, 0xB420, 0xB5CA, 0xB428,
+	0xB5CB, 0xB429, 0xB5CC, 0xB42B, 0xB5CD, 0xB434, 0xB5CE, 0xB450,	0xB5CF, 0xB451, 0xB5D0, 0xB454, 0xB5D1, 0xB458, 0xB5D2, 0xB460,
+	0xB5D3, 0xB461, 0xB5D4, 0xB463, 0xB5D5, 0xB465, 0xB5D6, 0xB46C,	0xB5D7, 0xB480, 0xB5D8, 0xB488, 0xB5D9, 0xB49D, 0xB5DA, 0xB4A4,
+	0xB5DB, 0xB4A8, 0xB5DC, 0xB4AC, 0xB5DD, 0xB4B5, 0xB5DE, 0xB4B7,	0xB5DF, 0xB4B9, 0xB5E0, 0xB4C0, 0xB5E1, 0xB4C4, 0xB5E2, 0xB4C8,
+	0xB5E3, 0xB4D0, 0xB5E4, 0xB4D5, 0xB5E5, 0xB4DC, 0xB5E6, 0xB4DD,	0xB5E7, 0xB4E0, 0xB5E8, 0xB4E3, 0xB5E9, 0xB4E4, 0xB5EA, 0xB4E6,
+	0xB5EB, 0xB4EC, 0xB5EC, 0xB4ED, 0xB5ED, 0xB4EF, 0xB5EE, 0xB4F1,	0xB5EF, 0xB4F8, 0xB5F0, 0xB514, 0xB5F1, 0xB515, 0xB5F2, 0xB518,
+	0xB5F3, 0xB51B, 0xB5F4, 0xB51C, 0xB5F5, 0xB524, 0xB5F6, 0xB525,	0xB5F7, 0xB527, 0xB5F8, 0xB528, 0xB5F9, 0xB529, 0xB5FA, 0xB52A,
+	0xB5FB, 0xB530, 0xB5FC, 0xB531, 0xB5FD, 0xB534, 0xB5FE, 0xB538,	0xB641, 0xD105, 0xB642, 0xD106, 0xB643, 0xD107, 0xB644, 0xD108,
+	0xB645, 0xD109, 0xB646, 0xD10A, 0xB647, 0xD10B, 0xB648, 0xD10C,	0xB649, 0xD10E, 0xB64A, 0xD10F, 0xB64B, 0xD110, 0xB64C, 0xD111,
+	0xB64D, 0xD112, 0xB64E, 0xD113, 0xB64F, 0xD114, 0xB650, 0xD115,	0xB651, 0xD116, 0xB652, 0xD117, 0xB653, 0xD118, 0xB654, 0xD119,
+	0xB655, 0xD11A, 0xB656, 0xD11B, 0xB657, 0xD11C, 0xB658, 0xD11D,	0xB659, 0xD11E, 0xB65A, 0xD11F, 0xB661, 0xD120, 0xB662, 0xD121,
+	0xB663, 0xD122, 0xB664, 0xD123, 0xB665, 0xD124, 0xB666, 0xD125,	0xB667, 0xD126, 0xB668, 0xD127, 0xB669, 0xD128, 0xB66A, 0xD129,
+	0xB66B, 0xD12A, 0xB66C, 0xD12B, 0xB66D, 0xD12C, 0xB66E, 0xD12D,	0xB66F, 0xD12E, 0xB670, 0xD12F, 0xB671, 0xD132, 0xB672, 0xD133,
+	0xB673, 0xD135, 0xB674, 0xD136, 0xB675, 0xD137, 0xB676, 0xD139,	0xB677, 0xD13B, 0xB678, 0xD13C, 0xB679, 0xD13D, 0xB67A, 0xD13E,
+	0xB681, 0xD13F, 0xB682, 0xD142, 0xB683, 0xD146, 0xB684, 0xD147,	0xB685, 0xD148, 0xB686, 0xD149, 0xB687, 0xD14A, 0xB688, 0xD14B,
+	0xB689, 0xD14E, 0xB68A, 0xD14F, 0xB68B, 0xD151, 0xB68C, 0xD152,	0xB68D, 0xD153, 0xB68E, 0xD155, 0xB68F, 0xD156, 0xB690, 0xD157,
+	0xB691, 0xD158, 0xB692, 0xD159, 0xB693, 0xD15A, 0xB694, 0xD15B,	0xB695, 0xD15E, 0xB696, 0xD160, 0xB697, 0xD162, 0xB698, 0xD163,
+	0xB699, 0xD164, 0xB69A, 0xD165, 0xB69B, 0xD166, 0xB69C, 0xD167,	0xB69D, 0xD169, 0xB69E, 0xD16A, 0xB69F, 0xD16B, 0xB6A0, 0xD16D,
+	0xB6A1, 0xB540, 0xB6A2, 0xB541, 0xB6A3, 0xB543, 0xB6A4, 0xB544,	0xB6A5, 0xB545, 0xB6A6, 0xB54B, 0xB6A7, 0xB54C, 0xB6A8, 0xB54D,
+	0xB6A9, 0xB550, 0xB6AA, 0xB554, 0xB6AB, 0xB55C, 0xB6AC, 0xB55D,	0xB6AD, 0xB55F, 0xB6AE, 0xB560, 0xB6AF, 0xB561, 0xB6B0, 0xB5A0,
+	0xB6B1, 0xB5A1, 0xB6B2, 0xB5A4, 0xB6B3, 0xB5A8, 0xB6B4, 0xB5AA,	0xB6B5, 0xB5AB, 0xB6B6, 0xB5B0, 0xB6B7, 0xB5B1, 0xB6B8, 0xB5B3,
+	0xB6B9, 0xB5B4, 0xB6BA, 0xB5B5, 0xB6BB, 0xB5BB, 0xB6BC, 0xB5BC,	0xB6BD, 0xB5BD, 0xB6BE, 0xB5C0, 0xB6BF, 0xB5C4, 0xB6C0, 0xB5CC,
+	0xB6C1, 0xB5CD, 0xB6C2, 0xB5CF, 0xB6C3, 0xB5D0, 0xB6C4, 0xB5D1,	0xB6C5, 0xB5D8, 0xB6C6, 0xB5EC, 0xB6C7, 0xB610, 0xB6C8, 0xB611,
+	0xB6C9, 0xB614, 0xB6CA, 0xB618, 0xB6CB, 0xB625, 0xB6CC, 0xB62C,	0xB6CD, 0xB634, 0xB6CE, 0xB648, 0xB6CF, 0xB664, 0xB6D0, 0xB668,
+	0xB6D1, 0xB69C, 0xB6D2, 0xB69D, 0xB6D3, 0xB6A0, 0xB6D4, 0xB6A4,	0xB6D5, 0xB6AB, 0xB6D6, 0xB6AC, 0xB6D7, 0xB6B1, 0xB6D8, 0xB6D4,
+	0xB6D9, 0xB6F0, 0xB6DA, 0xB6F4, 0xB6DB, 0xB6F8, 0xB6DC, 0xB700,	0xB6DD, 0xB701, 0xB6DE, 0xB705, 0xB6DF, 0xB728, 0xB6E0, 0xB729,
+	0xB6E1, 0xB72C, 0xB6E2, 0xB72F, 0xB6E3, 0xB730, 0xB6E4, 0xB738,	0xB6E5, 0xB739, 0xB6E6, 0xB73B, 0xB6E7, 0xB744, 0xB6E8, 0xB748,
+	0xB6E9, 0xB74C, 0xB6EA, 0xB754, 0xB6EB, 0xB755, 0xB6EC, 0xB760,	0xB6ED, 0xB764, 0xB6EE, 0xB768, 0xB6EF, 0xB770, 0xB6F0, 0xB771,
+	0xB6F1, 0xB773, 0xB6F2, 0xB775, 0xB6F3, 0xB77C, 0xB6F4, 0xB77D,	0xB6F5, 0xB780, 0xB6F6, 0xB784, 0xB6F7, 0xB78C, 0xB6F8, 0xB78D,
+	0xB6F9, 0xB78F, 0xB6FA, 0xB790, 0xB6FB, 0xB791, 0xB6FC, 0xB792,	0xB6FD, 0xB796, 0xB6FE, 0xB797, 0xB741, 0xD16E, 0xB742, 0xD16F,
+	0xB743, 0xD170, 0xB744, 0xD171, 0xB745, 0xD172, 0xB746, 0xD173,	0xB747, 0xD174, 0xB748, 0xD175, 0xB749, 0xD176, 0xB74A, 0xD177,
+	0xB74B, 0xD178, 0xB74C, 0xD179, 0xB74D, 0xD17A, 0xB74E, 0xD17B,	0xB74F, 0xD17D, 0xB750, 0xD17E, 0xB751, 0xD17F, 0xB752, 0xD180,
+	0xB753, 0xD181, 0xB754, 0xD182, 0xB755, 0xD183, 0xB756, 0xD185,	0xB757, 0xD186, 0xB758, 0xD187, 0xB759, 0xD189, 0xB75A, 0xD18A,
+	0xB761, 0xD18B, 0xB762, 0xD18C, 0xB763, 0xD18D, 0xB764, 0xD18E,	0xB765, 0xD18F, 0xB766, 0xD190, 0xB767, 0xD191, 0xB768, 0xD192,
+	0xB769, 0xD193, 0xB76A, 0xD194, 0xB76B, 0xD195, 0xB76C, 0xD196,	0xB76D, 0xD197, 0xB76E, 0xD198, 0xB76F, 0xD199, 0xB770, 0xD19A,
+	0xB771, 0xD19B, 0xB772, 0xD19C, 0xB773, 0xD19D, 0xB774, 0xD19E,	0xB775, 0xD19F, 0xB776, 0xD1A2, 0xB777, 0xD1A3, 0xB778, 0xD1A5,
+	0xB779, 0xD1A6, 0xB77A, 0xD1A7, 0xB781, 0xD1A9, 0xB782, 0xD1AA,	0xB783, 0xD1AB, 0xB784, 0xD1AC, 0xB785, 0xD1AD, 0xB786, 0xD1AE,
+	0xB787, 0xD1AF, 0xB788, 0xD1B2, 0xB789, 0xD1B4, 0xB78A, 0xD1B6,	0xB78B, 0xD1B7, 0xB78C, 0xD1B8, 0xB78D, 0xD1B9, 0xB78E, 0xD1BB,
+	0xB78F, 0xD1BD, 0xB790, 0xD1BE, 0xB791, 0xD1BF, 0xB792, 0xD1C1,	0xB793, 0xD1C2, 0xB794, 0xD1C3, 0xB795, 0xD1C4, 0xB796, 0xD1C5,
+	0xB797, 0xD1C6, 0xB798, 0xD1C7, 0xB799, 0xD1C8, 0xB79A, 0xD1C9,	0xB79B, 0xD1CA, 0xB79C, 0xD1CB, 0xB79D, 0xD1CC, 0xB79E, 0xD1CD,
+	0xB79F, 0xD1CE, 0xB7A0, 0xD1CF, 0xB7A1, 0xB798, 0xB7A2, 0xB799,	0xB7A3, 0xB79C, 0xB7A4, 0xB7A0, 0xB7A5, 0xB7A8, 0xB7A6, 0xB7A9,
+	0xB7A7, 0xB7AB, 0xB7A8, 0xB7AC, 0xB7A9, 0xB7AD, 0xB7AA, 0xB7B4,	0xB7AB, 0xB7B5, 0xB7AC, 0xB7B8, 0xB7AD, 0xB7C7, 0xB7AE, 0xB7C9,
+	0xB7AF, 0xB7EC, 0xB7B0, 0xB7ED, 0xB7B1, 0xB7F0, 0xB7B2, 0xB7F4,	0xB7B3, 0xB7FC, 0xB7B4, 0xB7FD, 0xB7B5, 0xB7FF, 0xB7B6, 0xB800,
+	0xB7B7, 0xB801, 0xB7B8, 0xB807, 0xB7B9, 0xB808, 0xB7BA, 0xB809,	0xB7BB, 0xB80C, 0xB7BC, 0xB810, 0xB7BD, 0xB818, 0xB7BE, 0xB819,
+	0xB7BF, 0xB81B, 0xB7C0, 0xB81D, 0xB7C1, 0xB824, 0xB7C2, 0xB825,	0xB7C3, 0xB828, 0xB7C4, 0xB82C, 0xB7C5, 0xB834, 0xB7C6, 0xB835,
+	0xB7C7, 0xB837, 0xB7C8, 0xB838, 0xB7C9, 0xB839, 0xB7CA, 0xB840,	0xB7CB, 0xB844, 0xB7CC, 0xB851, 0xB7CD, 0xB853, 0xB7CE, 0xB85C,
+	0xB7CF, 0xB85D, 0xB7D0, 0xB860, 0xB7D1, 0xB864, 0xB7D2, 0xB86C,	0xB7D3, 0xB86D, 0xB7D4, 0xB86F, 0xB7D5, 0xB871, 0xB7D6, 0xB878,
+	0xB7D7, 0xB87C, 0xB7D8, 0xB88D, 0xB7D9, 0xB8A8, 0xB7DA, 0xB8B0,	0xB7DB, 0xB8B4, 0xB7DC, 0xB8B8, 0xB7DD, 0xB8C0, 0xB7DE, 0xB8C1,
+	0xB7DF, 0xB8C3, 0xB7E0, 0xB8C5, 0xB7E1, 0xB8CC, 0xB7E2, 0xB8D0,	0xB7E3, 0xB8D4, 0xB7E4, 0xB8DD, 0xB7E5, 0xB8DF, 0xB7E6, 0xB8E1,
+	0xB7E7, 0xB8E8, 0xB7E8, 0xB8E9, 0xB7E9, 0xB8EC, 0xB7EA, 0xB8F0,	0xB7EB, 0xB8F8, 0xB7EC, 0xB8F9, 0xB7ED, 0xB8FB, 0xB7EE, 0xB8FD,
+	0xB7EF, 0xB904, 0xB7F0, 0xB918, 0xB7F1, 0xB920, 0xB7F2, 0xB93C,	0xB7F3, 0xB93D, 0xB7F4, 0xB940, 0xB7F5, 0xB944, 0xB7F6, 0xB94C,
+	0xB7F7, 0xB94F, 0xB7F8, 0xB951, 0xB7F9, 0xB958, 0xB7FA, 0xB959,	0xB7FB, 0xB95C, 0xB7FC, 0xB960, 0xB7FD, 0xB968, 0xB7FE, 0xB969,
+	0xB841, 0xD1D0, 0xB842, 0xD1D1, 0xB843, 0xD1D2, 0xB844, 0xD1D3,	0xB845, 0xD1D4, 0xB846, 0xD1D5, 0xB847, 0xD1D6, 0xB848, 0xD1D7,
+	0xB849, 0xD1D9, 0xB84A, 0xD1DA, 0xB84B, 0xD1DB, 0xB84C, 0xD1DC,	0xB84D, 0xD1DD, 0xB84E, 0xD1DE, 0xB84F, 0xD1DF, 0xB850, 0xD1E0,
+	0xB851, 0xD1E1, 0xB852, 0xD1E2, 0xB853, 0xD1E3, 0xB854, 0xD1E4,	0xB855, 0xD1E5, 0xB856, 0xD1E6, 0xB857, 0xD1E7, 0xB858, 0xD1E8,
+	0xB859, 0xD1E9, 0xB85A, 0xD1EA, 0xB861, 0xD1EB, 0xB862, 0xD1EC,	0xB863, 0xD1ED, 0xB864, 0xD1EE, 0xB865, 0xD1EF, 0xB866, 0xD1F0,
+	0xB867, 0xD1F1, 0xB868, 0xD1F2, 0xB869, 0xD1F3, 0xB86A, 0xD1F5,	0xB86B, 0xD1F6, 0xB86C, 0xD1F7, 0xB86D, 0xD1F9, 0xB86E, 0xD1FA,
+	0xB86F, 0xD1FB, 0xB870, 0xD1FC, 0xB871, 0xD1FD, 0xB872, 0xD1FE,	0xB873, 0xD1FF, 0xB874, 0xD200, 0xB875, 0xD201, 0xB876, 0xD202,
+	0xB877, 0xD203, 0xB878, 0xD204, 0xB879, 0xD205, 0xB87A, 0xD206,	0xB881, 0xD208, 0xB882, 0xD20A, 0xB883, 0xD20B, 0xB884, 0xD20C,
+	0xB885, 0xD20D, 0xB886, 0xD20E, 0xB887, 0xD20F, 0xB888, 0xD211,	0xB889, 0xD212, 0xB88A, 0xD213, 0xB88B, 0xD214, 0xB88C, 0xD215,
+	0xB88D, 0xD216, 0xB88E, 0xD217, 0xB88F, 0xD218, 0xB890, 0xD219,	0xB891, 0xD21A, 0xB892, 0xD21B, 0xB893, 0xD21C, 0xB894, 0xD21D,
+	0xB895, 0xD21E, 0xB896, 0xD21F, 0xB897, 0xD220, 0xB898, 0xD221,	0xB899, 0xD222, 0xB89A, 0xD223, 0xB89B, 0xD224, 0xB89C, 0xD225,
+	0xB89D, 0xD226, 0xB89E, 0xD227, 0xB89F, 0xD228, 0xB8A0, 0xD229,	0xB8A1, 0xB96B, 0xB8A2, 0xB96D, 0xB8A3, 0xB974, 0xB8A4, 0xB975,
+	0xB8A5, 0xB978, 0xB8A6, 0xB97C, 0xB8A7, 0xB984, 0xB8A8, 0xB985,	0xB8A9, 0xB987, 0xB8AA, 0xB989, 0xB8AB, 0xB98A, 0xB8AC, 0xB98D,
+	0xB8AD, 0xB98E, 0xB8AE, 0xB9AC, 0xB8AF, 0xB9AD, 0xB8B0, 0xB9B0,	0xB8B1, 0xB9B4, 0xB8B2, 0xB9BC, 0xB8B3, 0xB9BD, 0xB8B4, 0xB9BF,
+	0xB8B5, 0xB9C1, 0xB8B6, 0xB9C8, 0xB8B7, 0xB9C9, 0xB8B8, 0xB9CC,	0xB8B9, 0xB9CE, 0xB8BA, 0xB9CF, 0xB8BB, 0xB9D0, 0xB8BC, 0xB9D1,
+	0xB8BD, 0xB9D2, 0xB8BE, 0xB9D8, 0xB8BF, 0xB9D9, 0xB8C0, 0xB9DB,	0xB8C1, 0xB9DD, 0xB8C2, 0xB9DE, 0xB8C3, 0xB9E1, 0xB8C4, 0xB9E3,
+	0xB8C5, 0xB9E4, 0xB8C6, 0xB9E5, 0xB8C7, 0xB9E8, 0xB8C8, 0xB9EC,	0xB8C9, 0xB9F4, 0xB8CA, 0xB9F5, 0xB8CB, 0xB9F7, 0xB8CC, 0xB9F8,
+	0xB8CD, 0xB9F9, 0xB8CE, 0xB9FA, 0xB8CF, 0xBA00, 0xB8D0, 0xBA01,	0xB8D1, 0xBA08, 0xB8D2, 0xBA15, 0xB8D3, 0xBA38, 0xB8D4, 0xBA39,
+	0xB8D5, 0xBA3C, 0xB8D6, 0xBA40, 0xB8D7, 0xBA42, 0xB8D8, 0xBA48,	0xB8D9, 0xBA49, 0xB8DA, 0xBA4B, 0xB8DB, 0xBA4D, 0xB8DC, 0xBA4E,
+	0xB8DD, 0xBA53, 0xB8DE, 0xBA54, 0xB8DF, 0xBA55, 0xB8E0, 0xBA58,	0xB8E1, 0xBA5C, 0xB8E2, 0xBA64, 0xB8E3, 0xBA65, 0xB8E4, 0xBA67,
+	0xB8E5, 0xBA68, 0xB8E6, 0xBA69, 0xB8E7, 0xBA70, 0xB8E8, 0xBA71,	0xB8E9, 0xBA74, 0xB8EA, 0xBA78, 0xB8EB, 0xBA83, 0xB8EC, 0xBA84,
+	0xB8ED, 0xBA85, 0xB8EE, 0xBA87, 0xB8EF, 0xBA8C, 0xB8F0, 0xBAA8,	0xB8F1, 0xBAA9, 0xB8F2, 0xBAAB, 0xB8F3, 0xBAAC, 0xB8F4, 0xBAB0,
+	0xB8F5, 0xBAB2, 0xB8F6, 0xBAB8, 0xB8F7, 0xBAB9, 0xB8F8, 0xBABB,	0xB8F9, 0xBABD, 0xB8FA, 0xBAC4, 0xB8FB, 0xBAC8, 0xB8FC, 0xBAD8,
+	0xB8FD, 0xBAD9, 0xB8FE, 0xBAFC, 0xB941, 0xD22A, 0xB942, 0xD22B,	0xB943, 0xD22E, 0xB944, 0xD22F, 0xB945, 0xD231, 0xB946, 0xD232,
+	0xB947, 0xD233, 0xB948, 0xD235, 0xB949, 0xD236, 0xB94A, 0xD237,	0xB94B, 0xD238, 0xB94C, 0xD239, 0xB94D, 0xD23A, 0xB94E, 0xD23B,
+	0xB94F, 0xD23E, 0xB950, 0xD240, 0xB951, 0xD242, 0xB952, 0xD243,	0xB953, 0xD244, 0xB954, 0xD245, 0xB955, 0xD246, 0xB956, 0xD247,
+	0xB957, 0xD249, 0xB958, 0xD24A, 0xB959, 0xD24B, 0xB95A, 0xD24C,	0xB961, 0xD24D, 0xB962, 0xD24E, 0xB963, 0xD24F, 0xB964, 0xD250,
+	0xB965, 0xD251, 0xB966, 0xD252, 0xB967, 0xD253, 0xB968, 0xD254,	0xB969, 0xD255, 0xB96A, 0xD256, 0xB96B, 0xD257, 0xB96C, 0xD258,
+	0xB96D, 0xD259, 0xB96E, 0xD25A, 0xB96F, 0xD25B, 0xB970, 0xD25D,	0xB971, 0xD25E, 0xB972, 0xD25F, 0xB973, 0xD260, 0xB974, 0xD261,
+	0xB975, 0xD262, 0xB976, 0xD263, 0xB977, 0xD265, 0xB978, 0xD266,	0xB979, 0xD267, 0xB97A, 0xD268, 0xB981, 0xD269, 0xB982, 0xD26A,
+	0xB983, 0xD26B, 0xB984, 0xD26C, 0xB985, 0xD26D, 0xB986, 0xD26E,	0xB987, 0xD26F, 0xB988, 0xD270, 0xB989, 0xD271, 0xB98A, 0xD272,
+	0xB98B, 0xD273, 0xB98C, 0xD274, 0xB98D, 0xD275, 0xB98E, 0xD276,	0xB98F, 0xD277, 0xB990, 0xD278, 0xB991, 0xD279, 0xB992, 0xD27A,
+	0xB993, 0xD27B, 0xB994, 0xD27C, 0xB995, 0xD27D, 0xB996, 0xD27E,	0xB997, 0xD27F, 0xB998, 0xD282, 0xB999, 0xD283, 0xB99A, 0xD285,
+	0xB99B, 0xD286, 0xB99C, 0xD287, 0xB99D, 0xD289, 0xB99E, 0xD28A,	0xB99F, 0xD28B, 0xB9A0, 0xD28C, 0xB9A1, 0xBB00, 0xB9A2, 0xBB04,
+	0xB9A3, 0xBB0D, 0xB9A4, 0xBB0F, 0xB9A5, 0xBB11, 0xB9A6, 0xBB18,	0xB9A7, 0xBB1C, 0xB9A8, 0xBB20, 0xB9A9, 0xBB29, 0xB9AA, 0xBB2B,
+	0xB9AB, 0xBB34, 0xB9AC, 0xBB35, 0xB9AD, 0xBB36, 0xB9AE, 0xBB38,	0xB9AF, 0xBB3B, 0xB9B0, 0xBB3C, 0xB9B1, 0xBB3D, 0xB9B2, 0xBB3E,
+	0xB9B3, 0xBB44, 0xB9B4, 0xBB45, 0xB9B5, 0xBB47, 0xB9B6, 0xBB49,	0xB9B7, 0xBB4D, 0xB9B8, 0xBB4F, 0xB9B9, 0xBB50, 0xB9BA, 0xBB54,
+	0xB9BB, 0xBB58, 0xB9BC, 0xBB61, 0xB9BD, 0xBB63, 0xB9BE, 0xBB6C,	0xB9BF, 0xBB88, 0xB9C0, 0xBB8C, 0xB9C1, 0xBB90, 0xB9C2, 0xBBA4,
+	0xB9C3, 0xBBA8, 0xB9C4, 0xBBAC, 0xB9C5, 0xBBB4, 0xB9C6, 0xBBB7,	0xB9C7, 0xBBC0, 0xB9C8, 0xBBC4, 0xB9C9, 0xBBC8, 0xB9CA, 0xBBD0,
+	0xB9CB, 0xBBD3, 0xB9CC, 0xBBF8, 0xB9CD, 0xBBF9, 0xB9CE, 0xBBFC,	0xB9CF, 0xBBFF, 0xB9D0, 0xBC00, 0xB9D1, 0xBC02, 0xB9D2, 0xBC08,
+	0xB9D3, 0xBC09, 0xB9D4, 0xBC0B, 0xB9D5, 0xBC0C, 0xB9D6, 0xBC0D,	0xB9D7, 0xBC0F, 0xB9D8, 0xBC11, 0xB9D9, 0xBC14, 0xB9DA, 0xBC15,
+	0xB9DB, 0xBC16, 0xB9DC, 0xBC17, 0xB9DD, 0xBC18, 0xB9DE, 0xBC1B,	0xB9DF, 0xBC1C, 0xB9E0, 0xBC1D, 0xB9E1, 0xBC1E, 0xB9E2, 0xBC1F,
+	0xB9E3, 0xBC24, 0xB9E4, 0xBC25, 0xB9E5, 0xBC27, 0xB9E6, 0xBC29,	0xB9E7, 0xBC2D, 0xB9E8, 0xBC30, 0xB9E9, 0xBC31, 0xB9EA, 0xBC34,
+	0xB9EB, 0xBC38, 0xB9EC, 0xBC40, 0xB9ED, 0xBC41, 0xB9EE, 0xBC43,	0xB9EF, 0xBC44, 0xB9F0, 0xBC45, 0xB9F1, 0xBC49, 0xB9F2, 0xBC4C,
+	0xB9F3, 0xBC4D, 0xB9F4, 0xBC50, 0xB9F5, 0xBC5D, 0xB9F6, 0xBC84,	0xB9F7, 0xBC85, 0xB9F8, 0xBC88, 0xB9F9, 0xBC8B, 0xB9FA, 0xBC8C,
+	0xB9FB, 0xBC8E, 0xB9FC, 0xBC94, 0xB9FD, 0xBC95, 0xB9FE, 0xBC97,	0xBA41, 0xD28D, 0xBA42, 0xD28E, 0xBA43, 0xD28F, 0xBA44, 0xD292,
+	0xBA45, 0xD293, 0xBA46, 0xD294, 0xBA47, 0xD296, 0xBA48, 0xD297,	0xBA49, 0xD298, 0xBA4A, 0xD299, 0xBA4B, 0xD29A, 0xBA4C, 0xD29B,
+	0xBA4D, 0xD29D, 0xBA4E, 0xD29E, 0xBA4F, 0xD29F, 0xBA50, 0xD2A1,	0xBA51, 0xD2A2, 0xBA52, 0xD2A3, 0xBA53, 0xD2A5, 0xBA54, 0xD2A6,
+	0xBA55, 0xD2A7, 0xBA56, 0xD2A8, 0xBA57, 0xD2A9, 0xBA58, 0xD2AA,	0xBA59, 0xD2AB, 0xBA5A, 0xD2AD, 0xBA61, 0xD2AE, 0xBA62, 0xD2AF,
+	0xBA63, 0xD2B0, 0xBA64, 0xD2B2, 0xBA65, 0xD2B3, 0xBA66, 0xD2B4,	0xBA67, 0xD2B5, 0xBA68, 0xD2B6, 0xBA69, 0xD2B7, 0xBA6A, 0xD2BA,
+	0xBA6B, 0xD2BB, 0xBA6C, 0xD2BD, 0xBA6D, 0xD2BE, 0xBA6E, 0xD2C1,	0xBA6F, 0xD2C3, 0xBA70, 0xD2C4, 0xBA71, 0xD2C5, 0xBA72, 0xD2C6,
+	0xBA73, 0xD2C7, 0xBA74, 0xD2CA, 0xBA75, 0xD2CC, 0xBA76, 0xD2CD,	0xBA77, 0xD2CE, 0xBA78, 0xD2CF, 0xBA79, 0xD2D0, 0xBA7A, 0xD2D1,
+	0xBA81, 0xD2D2, 0xBA82, 0xD2D3, 0xBA83, 0xD2D5, 0xBA84, 0xD2D6,	0xBA85, 0xD2D7, 0xBA86, 0xD2D9, 0xBA87, 0xD2DA, 0xBA88, 0xD2DB,
+	0xBA89, 0xD2DD, 0xBA8A, 0xD2DE, 0xBA8B, 0xD2DF, 0xBA8C, 0xD2E0,	0xBA8D, 0xD2E1, 0xBA8E, 0xD2E2, 0xBA8F, 0xD2E3, 0xBA90, 0xD2E6,
+	0xBA91, 0xD2E7, 0xBA92, 0xD2E8, 0xBA93, 0xD2E9, 0xBA94, 0xD2EA,	0xBA95, 0xD2EB, 0xBA96, 0xD2EC, 0xBA97, 0xD2ED, 0xBA98, 0xD2EE,
+	0xBA99, 0xD2EF, 0xBA9A, 0xD2F2, 0xBA9B, 0xD2F3, 0xBA9C, 0xD2F5,	0xBA9D, 0xD2F6, 0xBA9E, 0xD2F7, 0xBA9F, 0xD2F9, 0xBAA0, 0xD2FA,
+	0xBAA1, 0xBC99, 0xBAA2, 0xBC9A, 0xBAA3, 0xBCA0, 0xBAA4, 0xBCA1,	0xBAA5, 0xBCA4, 0xBAA6, 0xBCA7, 0xBAA7, 0xBCA8, 0xBAA8, 0xBCB0,
+	0xBAA9, 0xBCB1, 0xBAAA, 0xBCB3, 0xBAAB, 0xBCB4, 0xBAAC, 0xBCB5,	0xBAAD, 0xBCBC, 0xBAAE, 0xBCBD, 0xBAAF, 0xBCC0, 0xBAB0, 0xBCC4,
+	0xBAB1, 0xBCCD, 0xBAB2, 0xBCCF, 0xBAB3, 0xBCD0, 0xBAB4, 0xBCD1,	0xBAB5, 0xBCD5, 0xBAB6, 0xBCD8, 0xBAB7, 0xBCDC, 0xBAB8, 0xBCF4,
+	0xBAB9, 0xBCF5, 0xBABA, 0xBCF6, 0xBABB, 0xBCF8, 0xBABC, 0xBCFC,	0xBABD, 0xBD04, 0xBABE, 0xBD05, 0xBABF, 0xBD07, 0xBAC0, 0xBD09,
+	0xBAC1, 0xBD10, 0xBAC2, 0xBD14, 0xBAC3, 0xBD24, 0xBAC4, 0xBD2C,	0xBAC5, 0xBD40, 0xBAC6, 0xBD48, 0xBAC7, 0xBD49, 0xBAC8, 0xBD4C,
+	0xBAC9, 0xBD50, 0xBACA, 0xBD58, 0xBACB, 0xBD59, 0xBACC, 0xBD64,	0xBACD, 0xBD68, 0xBACE, 0xBD80, 0xBACF, 0xBD81, 0xBAD0, 0xBD84,
+	0xBAD1, 0xBD87, 0xBAD2, 0xBD88, 0xBAD3, 0xBD89, 0xBAD4, 0xBD8A,	0xBAD5, 0xBD90, 0xBAD6, 0xBD91, 0xBAD7, 0xBD93, 0xBAD8, 0xBD95,
+	0xBAD9, 0xBD99, 0xBADA, 0xBD9A, 0xBADB, 0xBD9C, 0xBADC, 0xBDA4,	0xBADD, 0xBDB0, 0xBADE, 0xBDB8, 0xBADF, 0xBDD4, 0xBAE0, 0xBDD5,
+	0xBAE1, 0xBDD8, 0xBAE2, 0xBDDC, 0xBAE3, 0xBDE9, 0xBAE4, 0xBDF0,	0xBAE5, 0xBDF4, 0xBAE6, 0xBDF8, 0xBAE7, 0xBE00, 0xBAE8, 0xBE03,
+	0xBAE9, 0xBE05, 0xBAEA, 0xBE0C, 0xBAEB, 0xBE0D, 0xBAEC, 0xBE10,	0xBAED, 0xBE14, 0xBAEE, 0xBE1C, 0xBAEF, 0xBE1D, 0xBAF0, 0xBE1F,
+	0xBAF1, 0xBE44, 0xBAF2, 0xBE45, 0xBAF3, 0xBE48, 0xBAF4, 0xBE4C,	0xBAF5, 0xBE4E, 0xBAF6, 0xBE54, 0xBAF7, 0xBE55, 0xBAF8, 0xBE57,
+	0xBAF9, 0xBE59, 0xBAFA, 0xBE5A, 0xBAFB, 0xBE5B, 0xBAFC, 0xBE60,	0xBAFD, 0xBE61, 0xBAFE, 0xBE64, 0xBB41, 0xD2FB, 0xBB42, 0xD2FC,
+	0xBB43, 0xD2FD, 0xBB44, 0xD2FE, 0xBB45, 0xD2FF, 0xBB46, 0xD302,	0xBB47, 0xD304, 0xBB48, 0xD306, 0xBB49, 0xD307, 0xBB4A, 0xD308,
+	0xBB4B, 0xD309, 0xBB4C, 0xD30A, 0xBB4D, 0xD30B, 0xBB4E, 0xD30F,	0xBB4F, 0xD311, 0xBB50, 0xD312, 0xBB51, 0xD313, 0xBB52, 0xD315,
+	0xBB53, 0xD317, 0xBB54, 0xD318, 0xBB55, 0xD319, 0xBB56, 0xD31A,	0xBB57, 0xD31B, 0xBB58, 0xD31E, 0xBB59, 0xD322, 0xBB5A, 0xD323,
+	0xBB61, 0xD324, 0xBB62, 0xD326, 0xBB63, 0xD327, 0xBB64, 0xD32A,	0xBB65, 0xD32B, 0xBB66, 0xD32D, 0xBB67, 0xD32E, 0xBB68, 0xD32F,
+	0xBB69, 0xD331, 0xBB6A, 0xD332, 0xBB6B, 0xD333, 0xBB6C, 0xD334,	0xBB6D, 0xD335, 0xBB6E, 0xD336, 0xBB6F, 0xD337, 0xBB70, 0xD33A,
+	0xBB71, 0xD33E, 0xBB72, 0xD33F, 0xBB73, 0xD340, 0xBB74, 0xD341,	0xBB75, 0xD342, 0xBB76, 0xD343, 0xBB77, 0xD346, 0xBB78, 0xD347,
+	0xBB79, 0xD348, 0xBB7A, 0xD349, 0xBB81, 0xD34A, 0xBB82, 0xD34B,	0xBB83, 0xD34C, 0xBB84, 0xD34D, 0xBB85, 0xD34E, 0xBB86, 0xD34F,
+	0xBB87, 0xD350, 0xBB88, 0xD351, 0xBB89, 0xD352, 0xBB8A, 0xD353,	0xBB8B, 0xD354, 0xBB8C, 0xD355, 0xBB8D, 0xD356, 0xBB8E, 0xD357,
+	0xBB8F, 0xD358, 0xBB90, 0xD359, 0xBB91, 0xD35A, 0xBB92, 0xD35B,	0xBB93, 0xD35C, 0xBB94, 0xD35D, 0xBB95, 0xD35E, 0xBB96, 0xD35F,
+	0xBB97, 0xD360, 0xBB98, 0xD361, 0xBB99, 0xD362, 0xBB9A, 0xD363,	0xBB9B, 0xD364, 0xBB9C, 0xD365, 0xBB9D, 0xD366, 0xBB9E, 0xD367,
+	0xBB9F, 0xD368, 0xBBA0, 0xD369, 0xBBA1, 0xBE68, 0xBBA2, 0xBE6A,	0xBBA3, 0xBE70, 0xBBA4, 0xBE71, 0xBBA5, 0xBE73, 0xBBA6, 0xBE74,
+	0xBBA7, 0xBE75, 0xBBA8, 0xBE7B, 0xBBA9, 0xBE7C, 0xBBAA, 0xBE7D,	0xBBAB, 0xBE80, 0xBBAC, 0xBE84, 0xBBAD, 0xBE8C, 0xBBAE, 0xBE8D,
+	0xBBAF, 0xBE8F, 0xBBB0, 0xBE90, 0xBBB1, 0xBE91, 0xBBB2, 0xBE98,	0xBBB3, 0xBE99, 0xBBB4, 0xBEA8, 0xBBB5, 0xBED0, 0xBBB6, 0xBED1,
+	0xBBB7, 0xBED4, 0xBBB8, 0xBED7, 0xBBB9, 0xBED8, 0xBBBA, 0xBEE0,	0xBBBB, 0xBEE3, 0xBBBC, 0xBEE4, 0xBBBD, 0xBEE5, 0xBBBE, 0xBEEC,
+	0xBBBF, 0xBF01, 0xBBC0, 0xBF08, 0xBBC1, 0xBF09, 0xBBC2, 0xBF18,	0xBBC3, 0xBF19, 0xBBC4, 0xBF1B, 0xBBC5, 0xBF1C, 0xBBC6, 0xBF1D,
+	0xBBC7, 0xBF40, 0xBBC8, 0xBF41, 0xBBC9, 0xBF44, 0xBBCA, 0xBF48,	0xBBCB, 0xBF50, 0xBBCC, 0xBF51, 0xBBCD, 0xBF55, 0xBBCE, 0xBF94,
+	0xBBCF, 0xBFB0, 0xBBD0, 0xBFC5, 0xBBD1, 0xBFCC, 0xBBD2, 0xBFCD,	0xBBD3, 0xBFD0, 0xBBD4, 0xBFD4, 0xBBD5, 0xBFDC, 0xBBD6, 0xBFDF,
+	0xBBD7, 0xBFE1, 0xBBD8, 0xC03C, 0xBBD9, 0xC051, 0xBBDA, 0xC058,	0xBBDB, 0xC05C, 0xBBDC, 0xC060, 0xBBDD, 0xC068, 0xBBDE, 0xC069,
+	0xBBDF, 0xC090, 0xBBE0, 0xC091, 0xBBE1, 0xC094, 0xBBE2, 0xC098,	0xBBE3, 0xC0A0, 0xBBE4, 0xC0A1, 0xBBE5, 0xC0A3, 0xBBE6, 0xC0A5,
+	0xBBE7, 0xC0AC, 0xBBE8, 0xC0AD, 0xBBE9, 0xC0AF, 0xBBEA, 0xC0B0,	0xBBEB, 0xC0B3, 0xBBEC, 0xC0B4, 0xBBED, 0xC0B5, 0xBBEE, 0xC0B6,
+	0xBBEF, 0xC0BC, 0xBBF0, 0xC0BD, 0xBBF1, 0xC0BF, 0xBBF2, 0xC0C0,	0xBBF3, 0xC0C1, 0xBBF4, 0xC0C5, 0xBBF5, 0xC0C8, 0xBBF6, 0xC0C9,
+	0xBBF7, 0xC0CC, 0xBBF8, 0xC0D0, 0xBBF9, 0xC0D8, 0xBBFA, 0xC0D9,	0xBBFB, 0xC0DB, 0xBBFC, 0xC0DC, 0xBBFD, 0xC0DD, 0xBBFE, 0xC0E4,
+	0xBC41, 0xD36A, 0xBC42, 0xD36B, 0xBC43, 0xD36C, 0xBC44, 0xD36D,	0xBC45, 0xD36E, 0xBC46, 0xD36F, 0xBC47, 0xD370, 0xBC48, 0xD371,
+	0xBC49, 0xD372, 0xBC4A, 0xD373, 0xBC4B, 0xD374, 0xBC4C, 0xD375,	0xBC4D, 0xD376, 0xBC4E, 0xD377, 0xBC4F, 0xD378, 0xBC50, 0xD379,
+	0xBC51, 0xD37A, 0xBC52, 0xD37B, 0xBC53, 0xD37E, 0xBC54, 0xD37F,	0xBC55, 0xD381, 0xBC56, 0xD382, 0xBC57, 0xD383, 0xBC58, 0xD385,
+	0xBC59, 0xD386, 0xBC5A, 0xD387, 0xBC61, 0xD388, 0xBC62, 0xD389,	0xBC63, 0xD38A, 0xBC64, 0xD38B, 0xBC65, 0xD38E, 0xBC66, 0xD392,
+	0xBC67, 0xD393, 0xBC68, 0xD394, 0xBC69, 0xD395, 0xBC6A, 0xD396,	0xBC6B, 0xD397, 0xBC6C, 0xD39A, 0xBC6D, 0xD39B, 0xBC6E, 0xD39D,
+	0xBC6F, 0xD39E, 0xBC70, 0xD39F, 0xBC71, 0xD3A1, 0xBC72, 0xD3A2,	0xBC73, 0xD3A3, 0xBC74, 0xD3A4, 0xBC75, 0xD3A5, 0xBC76, 0xD3A6,
+	0xBC77, 0xD3A7, 0xBC78, 0xD3AA, 0xBC79, 0xD3AC, 0xBC7A, 0xD3AE,	0xBC81, 0xD3AF, 0xBC82, 0xD3B0, 0xBC83, 0xD3B1, 0xBC84, 0xD3B2,
+	0xBC85, 0xD3B3, 0xBC86, 0xD3B5, 0xBC87, 0xD3B6, 0xBC88, 0xD3B7,	0xBC89, 0xD3B9, 0xBC8A, 0xD3BA, 0xBC8B, 0xD3BB, 0xBC8C, 0xD3BD,
+	0xBC8D, 0xD3BE, 0xBC8E, 0xD3BF, 0xBC8F, 0xD3C0, 0xBC90, 0xD3C1,	0xBC91, 0xD3C2, 0xBC92, 0xD3C3, 0xBC93, 0xD3C6, 0xBC94, 0xD3C7,
+	0xBC95, 0xD3CA, 0xBC96, 0xD3CB, 0xBC97, 0xD3CC, 0xBC98, 0xD3CD,	0xBC99, 0xD3CE, 0xBC9A, 0xD3CF, 0xBC9B, 0xD3D1, 0xBC9C, 0xD3D2,
+	0xBC9D, 0xD3D3, 0xBC9E, 0xD3D4, 0xBC9F, 0xD3D5, 0xBCA0, 0xD3D6,	0xBCA1, 0xC0E5, 0xBCA2, 0xC0E8, 0xBCA3, 0xC0EC, 0xBCA4, 0xC0F4,
+	0xBCA5, 0xC0F5, 0xBCA6, 0xC0F7, 0xBCA7, 0xC0F9, 0xBCA8, 0xC100,	0xBCA9, 0xC104, 0xBCAA, 0xC108, 0xBCAB, 0xC110, 0xBCAC, 0xC115,
+	0xBCAD, 0xC11C, 0xBCAE, 0xC11D, 0xBCAF, 0xC11E, 0xBCB0, 0xC11F,	0xBCB1, 0xC120, 0xBCB2, 0xC123, 0xBCB3, 0xC124, 0xBCB4, 0xC126,
+	0xBCB5, 0xC127, 0xBCB6, 0xC12C, 0xBCB7, 0xC12D, 0xBCB8, 0xC12F,	0xBCB9, 0xC130, 0xBCBA, 0xC131, 0xBCBB, 0xC136, 0xBCBC, 0xC138,
+	0xBCBD, 0xC139, 0xBCBE, 0xC13C, 0xBCBF, 0xC140, 0xBCC0, 0xC148,	0xBCC1, 0xC149, 0xBCC2, 0xC14B, 0xBCC3, 0xC14C, 0xBCC4, 0xC14D,
+	0xBCC5, 0xC154, 0xBCC6, 0xC155, 0xBCC7, 0xC158, 0xBCC8, 0xC15C,	0xBCC9, 0xC164, 0xBCCA, 0xC165, 0xBCCB, 0xC167, 0xBCCC, 0xC168,
+	0xBCCD, 0xC169, 0xBCCE, 0xC170, 0xBCCF, 0xC174, 0xBCD0, 0xC178,	0xBCD1, 0xC185, 0xBCD2, 0xC18C, 0xBCD3, 0xC18D, 0xBCD4, 0xC18E,
+	0xBCD5, 0xC190, 0xBCD6, 0xC194, 0xBCD7, 0xC196, 0xBCD8, 0xC19C,	0xBCD9, 0xC19D, 0xBCDA, 0xC19F, 0xBCDB, 0xC1A1, 0xBCDC, 0xC1A5,
+	0xBCDD, 0xC1A8, 0xBCDE, 0xC1A9, 0xBCDF, 0xC1AC, 0xBCE0, 0xC1B0,	0xBCE1, 0xC1BD, 0xBCE2, 0xC1C4, 0xBCE3, 0xC1C8, 0xBCE4, 0xC1CC,
+	0xBCE5, 0xC1D4, 0xBCE6, 0xC1D7, 0xBCE7, 0xC1D8, 0xBCE8, 0xC1E0,	0xBCE9, 0xC1E4, 0xBCEA, 0xC1E8, 0xBCEB, 0xC1F0, 0xBCEC, 0xC1F1,
+	0xBCED, 0xC1F3, 0xBCEE, 0xC1FC, 0xBCEF, 0xC1FD, 0xBCF0, 0xC200,	0xBCF1, 0xC204, 0xBCF2, 0xC20C, 0xBCF3, 0xC20D, 0xBCF4, 0xC20F,
+	0xBCF5, 0xC211, 0xBCF6, 0xC218, 0xBCF7, 0xC219, 0xBCF8, 0xC21C,	0xBCF9, 0xC21F, 0xBCFA, 0xC220, 0xBCFB, 0xC228, 0xBCFC, 0xC229,
+	0xBCFD, 0xC22B, 0xBCFE, 0xC22D, 0xBD41, 0xD3D7, 0xBD42, 0xD3D9,	0xBD43, 0xD3DA, 0xBD44, 0xD3DB, 0xBD45, 0xD3DC, 0xBD46, 0xD3DD,
+	0xBD47, 0xD3DE, 0xBD48, 0xD3DF, 0xBD49, 0xD3E0, 0xBD4A, 0xD3E2,	0xBD4B, 0xD3E4, 0xBD4C, 0xD3E5, 0xBD4D, 0xD3E6, 0xBD4E, 0xD3E7,
+	0xBD4F, 0xD3E8, 0xBD50, 0xD3E9, 0xBD51, 0xD3EA, 0xBD52, 0xD3EB,	0xBD53, 0xD3EE, 0xBD54, 0xD3EF, 0xBD55, 0xD3F1, 0xBD56, 0xD3F2,
+	0xBD57, 0xD3F3, 0xBD58, 0xD3F5, 0xBD59, 0xD3F6, 0xBD5A, 0xD3F7,	0xBD61, 0xD3F8, 0xBD62, 0xD3F9, 0xBD63, 0xD3FA, 0xBD64, 0xD3FB,
+	0xBD65, 0xD3FE, 0xBD66, 0xD400, 0xBD67, 0xD402, 0xBD68, 0xD403,	0xBD69, 0xD404, 0xBD6A, 0xD405, 0xBD6B, 0xD406, 0xBD6C, 0xD407,
+	0xBD6D, 0xD409, 0xBD6E, 0xD40A, 0xBD6F, 0xD40B, 0xBD70, 0xD40C,	0xBD71, 0xD40D, 0xBD72, 0xD40E, 0xBD73, 0xD40F, 0xBD74, 0xD410,
+	0xBD75, 0xD411, 0xBD76, 0xD412, 0xBD77, 0xD413, 0xBD78, 0xD414,	0xBD79, 0xD415, 0xBD7A, 0xD416, 0xBD81, 0xD417, 0xBD82, 0xD418,
+	0xBD83, 0xD419, 0xBD84, 0xD41A, 0xBD85, 0xD41B, 0xBD86, 0xD41C,	0xBD87, 0xD41E, 0xBD88, 0xD41F, 0xBD89, 0xD420, 0xBD8A, 0xD421,
+	0xBD8B, 0xD422, 0xBD8C, 0xD423, 0xBD8D, 0xD424, 0xBD8E, 0xD425,	0xBD8F, 0xD426, 0xBD90, 0xD427, 0xBD91, 0xD428, 0xBD92, 0xD429,
+	0xBD93, 0xD42A, 0xBD94, 0xD42B, 0xBD95, 0xD42C, 0xBD96, 0xD42D,	0xBD97, 0xD42E, 0xBD98, 0xD42F, 0xBD99, 0xD430, 0xBD9A, 0xD431,
+	0xBD9B, 0xD432, 0xBD9C, 0xD433, 0xBD9D, 0xD434, 0xBD9E, 0xD435,	0xBD9F, 0xD436, 0xBDA0, 0xD437, 0xBDA1, 0xC22F, 0xBDA2, 0xC231,
+	0xBDA3, 0xC232, 0xBDA4, 0xC234, 0xBDA5, 0xC248, 0xBDA6, 0xC250,	0xBDA7, 0xC251, 0xBDA8, 0xC254, 0xBDA9, 0xC258, 0xBDAA, 0xC260,
+	0xBDAB, 0xC265, 0xBDAC, 0xC26C, 0xBDAD, 0xC26D, 0xBDAE, 0xC270,	0xBDAF, 0xC274, 0xBDB0, 0xC27C, 0xBDB1, 0xC27D, 0xBDB2, 0xC27F,
+	0xBDB3, 0xC281, 0xBDB4, 0xC288, 0xBDB5, 0xC289, 0xBDB6, 0xC290,	0xBDB7, 0xC298, 0xBDB8, 0xC29B, 0xBDB9, 0xC29D, 0xBDBA, 0xC2A4,
+	0xBDBB, 0xC2A5, 0xBDBC, 0xC2A8, 0xBDBD, 0xC2AC, 0xBDBE, 0xC2AD,	0xBDBF, 0xC2B4, 0xBDC0, 0xC2B5, 0xBDC1, 0xC2B7, 0xBDC2, 0xC2B9,
+	0xBDC3, 0xC2DC, 0xBDC4, 0xC2DD, 0xBDC5, 0xC2E0, 0xBDC6, 0xC2E3,	0xBDC7, 0xC2E4, 0xBDC8, 0xC2EB, 0xBDC9, 0xC2EC, 0xBDCA, 0xC2ED,
+	0xBDCB, 0xC2EF, 0xBDCC, 0xC2F1, 0xBDCD, 0xC2F6, 0xBDCE, 0xC2F8,	0xBDCF, 0xC2F9, 0xBDD0, 0xC2FB, 0xBDD1, 0xC2FC, 0xBDD2, 0xC300,
+	0xBDD3, 0xC308, 0xBDD4, 0xC309, 0xBDD5, 0xC30C, 0xBDD6, 0xC30D,	0xBDD7, 0xC313, 0xBDD8, 0xC314, 0xBDD9, 0xC315, 0xBDDA, 0xC318,
+	0xBDDB, 0xC31C, 0xBDDC, 0xC324, 0xBDDD, 0xC325, 0xBDDE, 0xC328,	0xBDDF, 0xC329, 0xBDE0, 0xC345, 0xBDE1, 0xC368, 0xBDE2, 0xC369,
+	0xBDE3, 0xC36C, 0xBDE4, 0xC370, 0xBDE5, 0xC372, 0xBDE6, 0xC378,	0xBDE7, 0xC379, 0xBDE8, 0xC37C, 0xBDE9, 0xC37D, 0xBDEA, 0xC384,
+	0xBDEB, 0xC388, 0xBDEC, 0xC38C, 0xBDED, 0xC3C0, 0xBDEE, 0xC3D8,	0xBDEF, 0xC3D9, 0xBDF0, 0xC3DC, 0xBDF1, 0xC3DF, 0xBDF2, 0xC3E0,
+	0xBDF3, 0xC3E2, 0xBDF4, 0xC3E8, 0xBDF5, 0xC3E9, 0xBDF6, 0xC3ED,	0xBDF7, 0xC3F4, 0xBDF8, 0xC3F5, 0xBDF9, 0xC3F8, 0xBDFA, 0xC408,
+	0xBDFB, 0xC410, 0xBDFC, 0xC424, 0xBDFD, 0xC42C, 0xBDFE, 0xC430,	0xBE41, 0xD438, 0xBE42, 0xD439, 0xBE43, 0xD43A, 0xBE44, 0xD43B,
+	0xBE45, 0xD43C, 0xBE46, 0xD43D, 0xBE47, 0xD43E, 0xBE48, 0xD43F,	0xBE49, 0xD441, 0xBE4A, 0xD442, 0xBE4B, 0xD443, 0xBE4C, 0xD445,
+	0xBE4D, 0xD446, 0xBE4E, 0xD447, 0xBE4F, 0xD448, 0xBE50, 0xD449,	0xBE51, 0xD44A, 0xBE52, 0xD44B, 0xBE53, 0xD44C, 0xBE54, 0xD44D,
+	0xBE55, 0xD44E, 0xBE56, 0xD44F, 0xBE57, 0xD450, 0xBE58, 0xD451,	0xBE59, 0xD452, 0xBE5A, 0xD453, 0xBE61, 0xD454, 0xBE62, 0xD455,
+	0xBE63, 0xD456, 0xBE64, 0xD457, 0xBE65, 0xD458, 0xBE66, 0xD459,	0xBE67, 0xD45A, 0xBE68, 0xD45B, 0xBE69, 0xD45D, 0xBE6A, 0xD45E,
+	0xBE6B, 0xD45F, 0xBE6C, 0xD461, 0xBE6D, 0xD462, 0xBE6E, 0xD463,	0xBE6F, 0xD465, 0xBE70, 0xD466, 0xBE71, 0xD467, 0xBE72, 0xD468,
+	0xBE73, 0xD469, 0xBE74, 0xD46A, 0xBE75, 0xD46B, 0xBE76, 0xD46C,	0xBE77, 0xD46E, 0xBE78, 0xD470, 0xBE79, 0xD471, 0xBE7A, 0xD472,
+	0xBE81, 0xD473, 0xBE82, 0xD474, 0xBE83, 0xD475, 0xBE84, 0xD476,	0xBE85, 0xD477, 0xBE86, 0xD47A, 0xBE87, 0xD47B, 0xBE88, 0xD47D,
+	0xBE89, 0xD47E, 0xBE8A, 0xD481, 0xBE8B, 0xD483, 0xBE8C, 0xD484,	0xBE8D, 0xD485, 0xBE8E, 0xD486, 0xBE8F, 0xD487, 0xBE90, 0xD48A,
+	0xBE91, 0xD48C, 0xBE92, 0xD48E, 0xBE93, 0xD48F, 0xBE94, 0xD490,	0xBE95, 0xD491, 0xBE96, 0xD492, 0xBE97, 0xD493, 0xBE98, 0xD495,
+	0xBE99, 0xD496, 0xBE9A, 0xD497, 0xBE9B, 0xD498, 0xBE9C, 0xD499,	0xBE9D, 0xD49A, 0xBE9E, 0xD49B, 0xBE9F, 0xD49C, 0xBEA0, 0xD49D,
+	0xBEA1, 0xC434, 0xBEA2, 0xC43C, 0xBEA3, 0xC43D, 0xBEA4, 0xC448,	0xBEA5, 0xC464, 0xBEA6, 0xC465, 0xBEA7, 0xC468, 0xBEA8, 0xC46C,
+	0xBEA9, 0xC474, 0xBEAA, 0xC475, 0xBEAB, 0xC479, 0xBEAC, 0xC480,	0xBEAD, 0xC494, 0xBEAE, 0xC49C, 0xBEAF, 0xC4B8, 0xBEB0, 0xC4BC,
+	0xBEB1, 0xC4E9, 0xBEB2, 0xC4F0, 0xBEB3, 0xC4F1, 0xBEB4, 0xC4F4,	0xBEB5, 0xC4F8, 0xBEB6, 0xC4FA, 0xBEB7, 0xC4FF, 0xBEB8, 0xC500,
+	0xBEB9, 0xC501, 0xBEBA, 0xC50C, 0xBEBB, 0xC510, 0xBEBC, 0xC514,	0xBEBD, 0xC51C, 0xBEBE, 0xC528, 0xBEBF, 0xC529, 0xBEC0, 0xC52C,
+	0xBEC1, 0xC530, 0xBEC2, 0xC538, 0xBEC3, 0xC539, 0xBEC4, 0xC53B,	0xBEC5, 0xC53D, 0xBEC6, 0xC544, 0xBEC7, 0xC545, 0xBEC8, 0xC548,
+	0xBEC9, 0xC549, 0xBECA, 0xC54A, 0xBECB, 0xC54C, 0xBECC, 0xC54D,	0xBECD, 0xC54E, 0xBECE, 0xC553, 0xBECF, 0xC554, 0xBED0, 0xC555,
+	0xBED1, 0xC557, 0xBED2, 0xC558, 0xBED3, 0xC559, 0xBED4, 0xC55D,	0xBED5, 0xC55E, 0xBED6, 0xC560, 0xBED7, 0xC561, 0xBED8, 0xC564,
+	0xBED9, 0xC568, 0xBEDA, 0xC570, 0xBEDB, 0xC571, 0xBEDC, 0xC573,	0xBEDD, 0xC574, 0xBEDE, 0xC575, 0xBEDF, 0xC57C, 0xBEE0, 0xC57D,
+	0xBEE1, 0xC580, 0xBEE2, 0xC584, 0xBEE3, 0xC587, 0xBEE4, 0xC58C,	0xBEE5, 0xC58D, 0xBEE6, 0xC58F, 0xBEE7, 0xC591, 0xBEE8, 0xC595,
+	0xBEE9, 0xC597, 0xBEEA, 0xC598, 0xBEEB, 0xC59C, 0xBEEC, 0xC5A0,	0xBEED, 0xC5A9, 0xBEEE, 0xC5B4, 0xBEEF, 0xC5B5, 0xBEF0, 0xC5B8,
+	0xBEF1, 0xC5B9, 0xBEF2, 0xC5BB, 0xBEF3, 0xC5BC, 0xBEF4, 0xC5BD,	0xBEF5, 0xC5BE, 0xBEF6, 0xC5C4, 0xBEF7, 0xC5C5, 0xBEF8, 0xC5C6,
+	0xBEF9, 0xC5C7, 0xBEFA, 0xC5C8, 0xBEFB, 0xC5C9, 0xBEFC, 0xC5CA,	0xBEFD, 0xC5CC, 0xBEFE, 0xC5CE, 0xBF41, 0xD49E, 0xBF42, 0xD49F,
+	0xBF43, 0xD4A0, 0xBF44, 0xD4A1, 0xBF45, 0xD4A2, 0xBF46, 0xD4A3,	0xBF47, 0xD4A4, 0xBF48, 0xD4A5, 0xBF49, 0xD4A6, 0xBF4A, 0xD4A7,
+	0xBF4B, 0xD4A8, 0xBF4C, 0xD4AA, 0xBF4D, 0xD4AB, 0xBF4E, 0xD4AC,	0xBF4F, 0xD4AD, 0xBF50, 0xD4AE, 0xBF51, 0xD4AF, 0xBF52, 0xD4B0,
+	0xBF53, 0xD4B1, 0xBF54, 0xD4B2, 0xBF55, 0xD4B3, 0xBF56, 0xD4B4,	0xBF57, 0xD4B5, 0xBF58, 0xD4B6, 0xBF59, 0xD4B7, 0xBF5A, 0xD4B8,
+	0xBF61, 0xD4B9, 0xBF62, 0xD4BA, 0xBF63, 0xD4BB, 0xBF64, 0xD4BC,	0xBF65, 0xD4BD, 0xBF66, 0xD4BE, 0xBF67, 0xD4BF, 0xBF68, 0xD4C0,
+	0xBF69, 0xD4C1, 0xBF6A, 0xD4C2, 0xBF6B, 0xD4C3, 0xBF6C, 0xD4C4,	0xBF6D, 0xD4C5, 0xBF6E, 0xD4C6, 0xBF6F, 0xD4C7, 0xBF70, 0xD4C8,
+	0xBF71, 0xD4C9, 0xBF72, 0xD4CA, 0xBF73, 0xD4CB, 0xBF74, 0xD4CD,	0xBF75, 0xD4CE, 0xBF76, 0xD4CF, 0xBF77, 0xD4D1, 0xBF78, 0xD4D2,
+	0xBF79, 0xD4D3, 0xBF7A, 0xD4D5, 0xBF81, 0xD4D6, 0xBF82, 0xD4D7,	0xBF83, 0xD4D8, 0xBF84, 0xD4D9, 0xBF85, 0xD4DA, 0xBF86, 0xD4DB,
+	0xBF87, 0xD4DD, 0xBF88, 0xD4DE, 0xBF89, 0xD4E0, 0xBF8A, 0xD4E1,	0xBF8B, 0xD4E2, 0xBF8C, 0xD4E3, 0xBF8D, 0xD4E4, 0xBF8E, 0xD4E5,
+	0xBF8F, 0xD4E6, 0xBF90, 0xD4E7, 0xBF91, 0xD4E9, 0xBF92, 0xD4EA,	0xBF93, 0xD4EB, 0xBF94, 0xD4ED, 0xBF95, 0xD4EE, 0xBF96, 0xD4EF,
+	0xBF97, 0xD4F1, 0xBF98, 0xD4F2, 0xBF99, 0xD4F3, 0xBF9A, 0xD4F4,	0xBF9B, 0xD4F5, 0xBF9C, 0xD4F6, 0xBF9D, 0xD4F7, 0xBF9E, 0xD4F9,
+	0xBF9F, 0xD4FA, 0xBFA0, 0xD4FC, 0xBFA1, 0xC5D0, 0xBFA2, 0xC5D1,	0xBFA3, 0xC5D4, 0xBFA4, 0xC5D8, 0xBFA5, 0xC5E0, 0xBFA6, 0xC5E1,
+	0xBFA7, 0xC5E3, 0xBFA8, 0xC5E5, 0xBFA9, 0xC5EC, 0xBFAA, 0xC5ED,	0xBFAB, 0xC5EE, 0xBFAC, 0xC5F0, 0xBFAD, 0xC5F4, 0xBFAE, 0xC5F6,
+	0xBFAF, 0xC5F7, 0xBFB0, 0xC5FC, 0xBFB1, 0xC5FD, 0xBFB2, 0xC5FE,	0xBFB3, 0xC5FF, 0xBFB4, 0xC600, 0xBFB5, 0xC601, 0xBFB6, 0xC605,
+	0xBFB7, 0xC606, 0xBFB8, 0xC607, 0xBFB9, 0xC608, 0xBFBA, 0xC60C,	0xBFBB, 0xC610, 0xBFBC, 0xC618, 0xBFBD, 0xC619, 0xBFBE, 0xC61B,
+	0xBFBF, 0xC61C, 0xBFC0, 0xC624, 0xBFC1, 0xC625, 0xBFC2, 0xC628,	0xBFC3, 0xC62C, 0xBFC4, 0xC62D, 0xBFC5, 0xC62E, 0xBFC6, 0xC630,
+	0xBFC7, 0xC633, 0xBFC8, 0xC634, 0xBFC9, 0xC635, 0xBFCA, 0xC637,	0xBFCB, 0xC639, 0xBFCC, 0xC63B, 0xBFCD, 0xC640, 0xBFCE, 0xC641,
+	0xBFCF, 0xC644, 0xBFD0, 0xC648, 0xBFD1, 0xC650, 0xBFD2, 0xC651,	0xBFD3, 0xC653, 0xBFD4, 0xC654, 0xBFD5, 0xC655, 0xBFD6, 0xC65C,
+	0xBFD7, 0xC65D, 0xBFD8, 0xC660, 0xBFD9, 0xC66C, 0xBFDA, 0xC66F,	0xBFDB, 0xC671, 0xBFDC, 0xC678, 0xBFDD, 0xC679, 0xBFDE, 0xC67C,
+	0xBFDF, 0xC680, 0xBFE0, 0xC688, 0xBFE1, 0xC689, 0xBFE2, 0xC68B,	0xBFE3, 0xC68D, 0xBFE4, 0xC694, 0xBFE5, 0xC695, 0xBFE6, 0xC698,
+	0xBFE7, 0xC69C, 0xBFE8, 0xC6A4, 0xBFE9, 0xC6A5, 0xBFEA, 0xC6A7,	0xBFEB, 0xC6A9, 0xBFEC, 0xC6B0, 0xBFED, 0xC6B1, 0xBFEE, 0xC6B4,
+	0xBFEF, 0xC6B8, 0xBFF0, 0xC6B9, 0xBFF1, 0xC6BA, 0xBFF2, 0xC6C0,	0xBFF3, 0xC6C1, 0xBFF4, 0xC6C3, 0xBFF5, 0xC6C5, 0xBFF6, 0xC6CC,
+	0xBFF7, 0xC6CD, 0xBFF8, 0xC6D0, 0xBFF9, 0xC6D4, 0xBFFA, 0xC6DC,	0xBFFB, 0xC6DD, 0xBFFC, 0xC6E0, 0xBFFD, 0xC6E1, 0xBFFE, 0xC6E8,
+	0xC041, 0xD4FE, 0xC042, 0xD4FF, 0xC043, 0xD500, 0xC044, 0xD501,	0xC045, 0xD502, 0xC046, 0xD503, 0xC047, 0xD505, 0xC048, 0xD506,
+	0xC049, 0xD507, 0xC04A, 0xD509, 0xC04B, 0xD50A, 0xC04C, 0xD50B,	0xC04D, 0xD50D, 0xC04E, 0xD50E, 0xC04F, 0xD50F, 0xC050, 0xD510,
+	0xC051, 0xD511, 0xC052, 0xD512, 0xC053, 0xD513, 0xC054, 0xD516,	0xC055, 0xD518, 0xC056, 0xD519, 0xC057, 0xD51A, 0xC058, 0xD51B,
+	0xC059, 0xD51C, 0xC05A, 0xD51D, 0xC061, 0xD51E, 0xC062, 0xD51F,	0xC063, 0xD520, 0xC064, 0xD521, 0xC065, 0xD522, 0xC066, 0xD523,
+	0xC067, 0xD524, 0xC068, 0xD525, 0xC069, 0xD526, 0xC06A, 0xD527,	0xC06B, 0xD528, 0xC06C, 0xD529, 0xC06D, 0xD52A, 0xC06E, 0xD52B,
+	0xC06F, 0xD52C, 0xC070, 0xD52D, 0xC071, 0xD52E, 0xC072, 0xD52F,	0xC073, 0xD530, 0xC074, 0xD531, 0xC075, 0xD532, 0xC076, 0xD533,
+	0xC077, 0xD534, 0xC078, 0xD535, 0xC079, 0xD536, 0xC07A, 0xD537,	0xC081, 0xD538, 0xC082, 0xD539, 0xC083, 0xD53A, 0xC084, 0xD53B,
+	0xC085, 0xD53E, 0xC086, 0xD53F, 0xC087, 0xD541, 0xC088, 0xD542,	0xC089, 0xD543, 0xC08A, 0xD545, 0xC08B, 0xD546, 0xC08C, 0xD547,
+	0xC08D, 0xD548, 0xC08E, 0xD549, 0xC08F, 0xD54A, 0xC090, 0xD54B,	0xC091, 0xD54E, 0xC092, 0xD550, 0xC093, 0xD552, 0xC094, 0xD553,
+	0xC095, 0xD554, 0xC096, 0xD555, 0xC097, 0xD556, 0xC098, 0xD557,	0xC099, 0xD55A, 0xC09A, 0xD55B, 0xC09B, 0xD55D, 0xC09C, 0xD55E,
+	0xC09D, 0xD55F, 0xC09E, 0xD561, 0xC09F, 0xD562, 0xC0A0, 0xD563,	0xC0A1, 0xC6E9, 0xC0A2, 0xC6EC, 0xC0A3, 0xC6F0, 0xC0A4, 0xC6F8,
+	0xC0A5, 0xC6F9, 0xC0A6, 0xC6FD, 0xC0A7, 0xC704, 0xC0A8, 0xC705,	0xC0A9, 0xC708, 0xC0AA, 0xC70C, 0xC0AB, 0xC714, 0xC0AC, 0xC715,
+	0xC0AD, 0xC717, 0xC0AE, 0xC719, 0xC0AF, 0xC720, 0xC0B0, 0xC721,	0xC0B1, 0xC724, 0xC0B2, 0xC728, 0xC0B3, 0xC730, 0xC0B4, 0xC731,
+	0xC0B5, 0xC733, 0xC0B6, 0xC735, 0xC0B7, 0xC737, 0xC0B8, 0xC73C,	0xC0B9, 0xC73D, 0xC0BA, 0xC740, 0xC0BB, 0xC744, 0xC0BC, 0xC74A,
+	0xC0BD, 0xC74C, 0xC0BE, 0xC74D, 0xC0BF, 0xC74F, 0xC0C0, 0xC751,	0xC0C1, 0xC752, 0xC0C2, 0xC753, 0xC0C3, 0xC754, 0xC0C4, 0xC755,
+	0xC0C5, 0xC756, 0xC0C6, 0xC757, 0xC0C7, 0xC758, 0xC0C8, 0xC75C,	0xC0C9, 0xC760, 0xC0CA, 0xC768, 0xC0CB, 0xC76B, 0xC0CC, 0xC774,
+	0xC0CD, 0xC775, 0xC0CE, 0xC778, 0xC0CF, 0xC77C, 0xC0D0, 0xC77D,	0xC0D1, 0xC77E, 0xC0D2, 0xC783, 0xC0D3, 0xC784, 0xC0D4, 0xC785,
+	0xC0D5, 0xC787, 0xC0D6, 0xC788, 0xC0D7, 0xC789, 0xC0D8, 0xC78A,	0xC0D9, 0xC78E, 0xC0DA, 0xC790, 0xC0DB, 0xC791, 0xC0DC, 0xC794,
+	0xC0DD, 0xC796, 0xC0DE, 0xC797, 0xC0DF, 0xC798, 0xC0E0, 0xC79A,	0xC0E1, 0xC7A0, 0xC0E2, 0xC7A1, 0xC0E3, 0xC7A3, 0xC0E4, 0xC7A4,
+	0xC0E5, 0xC7A5, 0xC0E6, 0xC7A6, 0xC0E7, 0xC7AC, 0xC0E8, 0xC7AD,	0xC0E9, 0xC7B0, 0xC0EA, 0xC7B4, 0xC0EB, 0xC7BC, 0xC0EC, 0xC7BD,
+	0xC0ED, 0xC7BF, 0xC0EE, 0xC7C0, 0xC0EF, 0xC7C1, 0xC0F0, 0xC7C8,	0xC0F1, 0xC7C9, 0xC0F2, 0xC7CC, 0xC0F3, 0xC7CE, 0xC0F4, 0xC7D0,
+	0xC0F5, 0xC7D8, 0xC0F6, 0xC7DD, 0xC0F7, 0xC7E4, 0xC0F8, 0xC7E8,	0xC0F9, 0xC7EC, 0xC0FA, 0xC800, 0xC0FB, 0xC801, 0xC0FC, 0xC804,
+	0xC0FD, 0xC808, 0xC0FE, 0xC80A, 0xC141, 0xD564, 0xC142, 0xD566,	0xC143, 0xD567, 0xC144, 0xD56A, 0xC145, 0xD56C, 0xC146, 0xD56E,
+	0xC147, 0xD56F, 0xC148, 0xD570, 0xC149, 0xD571, 0xC14A, 0xD572,	0xC14B, 0xD573, 0xC14C, 0xD576, 0xC14D, 0xD577, 0xC14E, 0xD579,
+	0xC14F, 0xD57A, 0xC150, 0xD57B, 0xC151, 0xD57D, 0xC152, 0xD57E,	0xC153, 0xD57F, 0xC154, 0xD580, 0xC155, 0xD581, 0xC156, 0xD582,
+	0xC157, 0xD583, 0xC158, 0xD586, 0xC159, 0xD58A, 0xC15A, 0xD58B,	0xC161, 0xD58C, 0xC162, 0xD58D, 0xC163, 0xD58E, 0xC164, 0xD58F,
+	0xC165, 0xD591, 0xC166, 0xD592, 0xC167, 0xD593, 0xC168, 0xD594,	0xC169, 0xD595, 0xC16A, 0xD596, 0xC16B, 0xD597, 0xC16C, 0xD598,
+	0xC16D, 0xD599, 0xC16E, 0xD59A, 0xC16F, 0xD59B, 0xC170, 0xD59C,	0xC171, 0xD59D, 0xC172, 0xD59E, 0xC173, 0xD59F, 0xC174, 0xD5A0,
+	0xC175, 0xD5A1, 0xC176, 0xD5A2, 0xC177, 0xD5A3, 0xC178, 0xD5A4,	0xC179, 0xD5A6, 0xC17A, 0xD5A7, 0xC181, 0xD5A8, 0xC182, 0xD5A9,
+	0xC183, 0xD5AA, 0xC184, 0xD5AB, 0xC185, 0xD5AC, 0xC186, 0xD5AD,	0xC187, 0xD5AE, 0xC188, 0xD5AF, 0xC189, 0xD5B0, 0xC18A, 0xD5B1,
+	0xC18B, 0xD5B2, 0xC18C, 0xD5B3, 0xC18D, 0xD5B4, 0xC18E, 0xD5B5,	0xC18F, 0xD5B6, 0xC190, 0xD5B7, 0xC191, 0xD5B8, 0xC192, 0xD5B9,
+	0xC193, 0xD5BA, 0xC194, 0xD5BB, 0xC195, 0xD5BC, 0xC196, 0xD5BD,	0xC197, 0xD5BE, 0xC198, 0xD5BF, 0xC199, 0xD5C0, 0xC19A, 0xD5C1,
+	0xC19B, 0xD5C2, 0xC19C, 0xD5C3, 0xC19D, 0xD5C4, 0xC19E, 0xD5C5,	0xC19F, 0xD5C6, 0xC1A0, 0xD5C7, 0xC1A1, 0xC810, 0xC1A2, 0xC811,
+	0xC1A3, 0xC813, 0xC1A4, 0xC815, 0xC1A5, 0xC816, 0xC1A6, 0xC81C,	0xC1A7, 0xC81D, 0xC1A8, 0xC820, 0xC1A9, 0xC824, 0xC1AA, 0xC82C,
+	0xC1AB, 0xC82D, 0xC1AC, 0xC82F, 0xC1AD, 0xC831, 0xC1AE, 0xC838,	0xC1AF, 0xC83C, 0xC1B0, 0xC840, 0xC1B1, 0xC848, 0xC1B2, 0xC849,
+	0xC1B3, 0xC84C, 0xC1B4, 0xC84D, 0xC1B5, 0xC854, 0xC1B6, 0xC870,	0xC1B7, 0xC871, 0xC1B8, 0xC874, 0xC1B9, 0xC878, 0xC1BA, 0xC87A,
+	0xC1BB, 0xC880, 0xC1BC, 0xC881, 0xC1BD, 0xC883, 0xC1BE, 0xC885,	0xC1BF, 0xC886, 0xC1C0, 0xC887, 0xC1C1, 0xC88B, 0xC1C2, 0xC88C,
+	0xC1C3, 0xC88D, 0xC1C4, 0xC894, 0xC1C5, 0xC89D, 0xC1C6, 0xC89F,	0xC1C7, 0xC8A1, 0xC1C8, 0xC8A8, 0xC1C9, 0xC8BC, 0xC1CA, 0xC8BD,
+	0xC1CB, 0xC8C4, 0xC1CC, 0xC8C8, 0xC1CD, 0xC8CC, 0xC1CE, 0xC8D4,	0xC1CF, 0xC8D5, 0xC1D0, 0xC8D7, 0xC1D1, 0xC8D9, 0xC1D2, 0xC8E0,
+	0xC1D3, 0xC8E1, 0xC1D4, 0xC8E4, 0xC1D5, 0xC8F5, 0xC1D6, 0xC8FC,	0xC1D7, 0xC8FD, 0xC1D8, 0xC900, 0xC1D9, 0xC904, 0xC1DA, 0xC905,
+	0xC1DB, 0xC906, 0xC1DC, 0xC90C, 0xC1DD, 0xC90D, 0xC1DE, 0xC90F,	0xC1DF, 0xC911, 0xC1E0, 0xC918, 0xC1E1, 0xC92C, 0xC1E2, 0xC934,
+	0xC1E3, 0xC950, 0xC1E4, 0xC951, 0xC1E5, 0xC954, 0xC1E6, 0xC958,	0xC1E7, 0xC960, 0xC1E8, 0xC961, 0xC1E9, 0xC963, 0xC1EA, 0xC96C,
+	0xC1EB, 0xC970, 0xC1EC, 0xC974, 0xC1ED, 0xC97C, 0xC1EE, 0xC988,	0xC1EF, 0xC989, 0xC1F0, 0xC98C, 0xC1F1, 0xC990, 0xC1F2, 0xC998,
+	0xC1F3, 0xC999, 0xC1F4, 0xC99B, 0xC1F5, 0xC99D, 0xC1F6, 0xC9C0,	0xC1F7, 0xC9C1, 0xC1F8, 0xC9C4, 0xC1F9, 0xC9C7, 0xC1FA, 0xC9C8,
+	0xC1FB, 0xC9CA, 0xC1FC, 0xC9D0, 0xC1FD, 0xC9D1, 0xC1FE, 0xC9D3,	0xC241, 0xD5CA, 0xC242, 0xD5CB, 0xC243, 0xD5CD, 0xC244, 0xD5CE,
+	0xC245, 0xD5CF, 0xC246, 0xD5D1, 0xC247, 0xD5D3, 0xC248, 0xD5D4,	0xC249, 0xD5D5, 0xC24A, 0xD5D6, 0xC24B, 0xD5D7, 0xC24C, 0xD5DA,
+	0xC24D, 0xD5DC, 0xC24E, 0xD5DE, 0xC24F, 0xD5DF, 0xC250, 0xD5E0,	0xC251, 0xD5E1, 0xC252, 0xD5E2, 0xC253, 0xD5E3, 0xC254, 0xD5E6,
+	0xC255, 0xD5E7, 0xC256, 0xD5E9, 0xC257, 0xD5EA, 0xC258, 0xD5EB,	0xC259, 0xD5ED, 0xC25A, 0xD5EE, 0xC261, 0xD5EF, 0xC262, 0xD5F0,
+	0xC263, 0xD5F1, 0xC264, 0xD5F2, 0xC265, 0xD5F3, 0xC266, 0xD5F6,	0xC267, 0xD5F8, 0xC268, 0xD5FA, 0xC269, 0xD5FB, 0xC26A, 0xD5FC,
+	0xC26B, 0xD5FD, 0xC26C, 0xD5FE, 0xC26D, 0xD5FF, 0xC26E, 0xD602,	0xC26F, 0xD603, 0xC270, 0xD605, 0xC271, 0xD606, 0xC272, 0xD607,
+	0xC273, 0xD609, 0xC274, 0xD60A, 0xC275, 0xD60B, 0xC276, 0xD60C,	0xC277, 0xD60D, 0xC278, 0xD60E, 0xC279, 0xD60F, 0xC27A, 0xD612,
+	0xC281, 0xD616, 0xC282, 0xD617, 0xC283, 0xD618, 0xC284, 0xD619,	0xC285, 0xD61A, 0xC286, 0xD61B, 0xC287, 0xD61D, 0xC288, 0xD61E,
+	0xC289, 0xD61F, 0xC28A, 0xD621, 0xC28B, 0xD622, 0xC28C, 0xD623,	0xC28D, 0xD625, 0xC28E, 0xD626, 0xC28F, 0xD627, 0xC290, 0xD628,
+	0xC291, 0xD629, 0xC292, 0xD62A, 0xC293, 0xD62B, 0xC294, 0xD62C,	0xC295, 0xD62E, 0xC296, 0xD62F, 0xC297, 0xD630, 0xC298, 0xD631,
+	0xC299, 0xD632, 0xC29A, 0xD633, 0xC29B, 0xD634, 0xC29C, 0xD635,	0xC29D, 0xD636, 0xC29E, 0xD637, 0xC29F, 0xD63A, 0xC2A0, 0xD63B,
+	0xC2A1, 0xC9D5, 0xC2A2, 0xC9D6, 0xC2A3, 0xC9D9, 0xC2A4, 0xC9DA,	0xC2A5, 0xC9DC, 0xC2A6, 0xC9DD, 0xC2A7, 0xC9E0, 0xC2A8, 0xC9E2,
+	0xC2A9, 0xC9E4, 0xC2AA, 0xC9E7, 0xC2AB, 0xC9EC, 0xC2AC, 0xC9ED,	0xC2AD, 0xC9EF, 0xC2AE, 0xC9F0, 0xC2AF, 0xC9F1, 0xC2B0, 0xC9F8,
+	0xC2B1, 0xC9F9, 0xC2B2, 0xC9FC, 0xC2B3, 0xCA00, 0xC2B4, 0xCA08,	0xC2B5, 0xCA09, 0xC2B6, 0xCA0B, 0xC2B7, 0xCA0C, 0xC2B8, 0xCA0D,
+	0xC2B9, 0xCA14, 0xC2BA, 0xCA18, 0xC2BB, 0xCA29, 0xC2BC, 0xCA4C,	0xC2BD, 0xCA4D, 0xC2BE, 0xCA50, 0xC2BF, 0xCA54, 0xC2C0, 0xCA5C,
+	0xC2C1, 0xCA5D, 0xC2C2, 0xCA5F, 0xC2C3, 0xCA60, 0xC2C4, 0xCA61,	0xC2C5, 0xCA68, 0xC2C6, 0xCA7D, 0xC2C7, 0xCA84, 0xC2C8, 0xCA98,
+	0xC2C9, 0xCABC, 0xC2CA, 0xCABD, 0xC2CB, 0xCAC0, 0xC2CC, 0xCAC4,	0xC2CD, 0xCACC, 0xC2CE, 0xCACD, 0xC2CF, 0xCACF, 0xC2D0, 0xCAD1,
+	0xC2D1, 0xCAD3, 0xC2D2, 0xCAD8, 0xC2D3, 0xCAD9, 0xC2D4, 0xCAE0,	0xC2D5, 0xCAEC, 0xC2D6, 0xCAF4, 0xC2D7, 0xCB08, 0xC2D8, 0xCB10,
+	0xC2D9, 0xCB14, 0xC2DA, 0xCB18, 0xC2DB, 0xCB20, 0xC2DC, 0xCB21,	0xC2DD, 0xCB41, 0xC2DE, 0xCB48, 0xC2DF, 0xCB49, 0xC2E0, 0xCB4C,
+	0xC2E1, 0xCB50, 0xC2E2, 0xCB58, 0xC2E3, 0xCB59, 0xC2E4, 0xCB5D,	0xC2E5, 0xCB64, 0xC2E6, 0xCB78, 0xC2E7, 0xCB79, 0xC2E8, 0xCB9C,
+	0xC2E9, 0xCBB8, 0xC2EA, 0xCBD4, 0xC2EB, 0xCBE4, 0xC2EC, 0xCBE7,	0xC2ED, 0xCBE9, 0xC2EE, 0xCC0C, 0xC2EF, 0xCC0D, 0xC2F0, 0xCC10,
+	0xC2F1, 0xCC14, 0xC2F2, 0xCC1C, 0xC2F3, 0xCC1D, 0xC2F4, 0xCC21,	0xC2F5, 0xCC22, 0xC2F6, 0xCC27, 0xC2F7, 0xCC28, 0xC2F8, 0xCC29,
+	0xC2F9, 0xCC2C, 0xC2FA, 0xCC2E, 0xC2FB, 0xCC30, 0xC2FC, 0xCC38,	0xC2FD, 0xCC39, 0xC2FE, 0xCC3B, 0xC341, 0xD63D, 0xC342, 0xD63E,
+	0xC343, 0xD63F, 0xC344, 0xD641, 0xC345, 0xD642, 0xC346, 0xD643,	0xC347, 0xD644, 0xC348, 0xD646, 0xC349, 0xD647, 0xC34A, 0xD64A,
+	0xC34B, 0xD64C, 0xC34C, 0xD64E, 0xC34D, 0xD64F, 0xC34E, 0xD650,	0xC34F, 0xD652, 0xC350, 0xD653, 0xC351, 0xD656, 0xC352, 0xD657,
+	0xC353, 0xD659, 0xC354, 0xD65A, 0xC355, 0xD65B, 0xC356, 0xD65D,	0xC357, 0xD65E, 0xC358, 0xD65F, 0xC359, 0xD660, 0xC35A, 0xD661,
+	0xC361, 0xD662, 0xC362, 0xD663, 0xC363, 0xD664, 0xC364, 0xD665,	0xC365, 0xD666, 0xC366, 0xD668, 0xC367, 0xD66A, 0xC368, 0xD66B,
+	0xC369, 0xD66C, 0xC36A, 0xD66D, 0xC36B, 0xD66E, 0xC36C, 0xD66F,	0xC36D, 0xD672, 0xC36E, 0xD673, 0xC36F, 0xD675, 0xC370, 0xD676,
+	0xC371, 0xD677, 0xC372, 0xD678, 0xC373, 0xD679, 0xC374, 0xD67A,	0xC375, 0xD67B, 0xC376, 0xD67C, 0xC377, 0xD67D, 0xC378, 0xD67E,
+	0xC379, 0xD67F, 0xC37A, 0xD680, 0xC381, 0xD681, 0xC382, 0xD682,	0xC383, 0xD684, 0xC384, 0xD686, 0xC385, 0xD687, 0xC386, 0xD688,
+	0xC387, 0xD689, 0xC388, 0xD68A, 0xC389, 0xD68B, 0xC38A, 0xD68E,	0xC38B, 0xD68F, 0xC38C, 0xD691, 0xC38D, 0xD692, 0xC38E, 0xD693,
+	0xC38F, 0xD695, 0xC390, 0xD696, 0xC391, 0xD697, 0xC392, 0xD698,	0xC393, 0xD699, 0xC394, 0xD69A, 0xC395, 0xD69B, 0xC396, 0xD69C,
+	0xC397, 0xD69E, 0xC398, 0xD6A0, 0xC399, 0xD6A2, 0xC39A, 0xD6A3,	0xC39B, 0xD6A4, 0xC39C, 0xD6A5, 0xC39D, 0xD6A6, 0xC39E, 0xD6A7,
+	0xC39F, 0xD6A9, 0xC3A0, 0xD6AA, 0xC3A1, 0xCC3C, 0xC3A2, 0xCC3D,	0xC3A3, 0xCC3E, 0xC3A4, 0xCC44, 0xC3A5, 0xCC45, 0xC3A6, 0xCC48,
+	0xC3A7, 0xCC4C, 0xC3A8, 0xCC54, 0xC3A9, 0xCC55, 0xC3AA, 0xCC57,	0xC3AB, 0xCC58, 0xC3AC, 0xCC59, 0xC3AD, 0xCC60, 0xC3AE, 0xCC64,
+	0xC3AF, 0xCC66, 0xC3B0, 0xCC68, 0xC3B1, 0xCC70, 0xC3B2, 0xCC75,	0xC3B3, 0xCC98, 0xC3B4, 0xCC99, 0xC3B5, 0xCC9C, 0xC3B6, 0xCCA0,
+	0xC3B7, 0xCCA8, 0xC3B8, 0xCCA9, 0xC3B9, 0xCCAB, 0xC3BA, 0xCCAC,	0xC3BB, 0xCCAD, 0xC3BC, 0xCCB4, 0xC3BD, 0xCCB5, 0xC3BE, 0xCCB8,
+	0xC3BF, 0xCCBC, 0xC3C0, 0xCCC4, 0xC3C1, 0xCCC5, 0xC3C2, 0xCCC7,	0xC3C3, 0xCCC9, 0xC3C4, 0xCCD0, 0xC3C5, 0xCCD4, 0xC3C6, 0xCCE4,
+	0xC3C7, 0xCCEC, 0xC3C8, 0xCCF0, 0xC3C9, 0xCD01, 0xC3CA, 0xCD08,	0xC3CB, 0xCD09, 0xC3CC, 0xCD0C, 0xC3CD, 0xCD10, 0xC3CE, 0xCD18,
+	0xC3CF, 0xCD19, 0xC3D0, 0xCD1B, 0xC3D1, 0xCD1D, 0xC3D2, 0xCD24,	0xC3D3, 0xCD28, 0xC3D4, 0xCD2C, 0xC3D5, 0xCD39, 0xC3D6, 0xCD5C,
+	0xC3D7, 0xCD60, 0xC3D8, 0xCD64, 0xC3D9, 0xCD6C, 0xC3DA, 0xCD6D,	0xC3DB, 0xCD6F, 0xC3DC, 0xCD71, 0xC3DD, 0xCD78, 0xC3DE, 0xCD88,
+	0xC3DF, 0xCD94, 0xC3E0, 0xCD95, 0xC3E1, 0xCD98, 0xC3E2, 0xCD9C,	0xC3E3, 0xCDA4, 0xC3E4, 0xCDA5, 0xC3E5, 0xCDA7, 0xC3E6, 0xCDA9,
+	0xC3E7, 0xCDB0, 0xC3E8, 0xCDC4, 0xC3E9, 0xCDCC, 0xC3EA, 0xCDD0,	0xC3EB, 0xCDE8, 0xC3EC, 0xCDEC, 0xC3ED, 0xCDF0, 0xC3EE, 0xCDF8,
+	0xC3EF, 0xCDF9, 0xC3F0, 0xCDFB, 0xC3F1, 0xCDFD, 0xC3F2, 0xCE04,	0xC3F3, 0xCE08, 0xC3F4, 0xCE0C, 0xC3F5, 0xCE14, 0xC3F6, 0xCE19,
+	0xC3F7, 0xCE20, 0xC3F8, 0xCE21, 0xC3F9, 0xCE24, 0xC3FA, 0xCE28,	0xC3FB, 0xCE30, 0xC3FC, 0xCE31, 0xC3FD, 0xCE33, 0xC3FE, 0xCE35,
+	0xC441, 0xD6AB, 0xC442, 0xD6AD, 0xC443, 0xD6AE, 0xC444, 0xD6AF,	0xC445, 0xD6B1, 0xC446, 0xD6B2, 0xC447, 0xD6B3, 0xC448, 0xD6B4,
+	0xC449, 0xD6B5, 0xC44A, 0xD6B6, 0xC44B, 0xD6B7, 0xC44C, 0xD6B8,	0xC44D, 0xD6BA, 0xC44E, 0xD6BC, 0xC44F, 0xD6BD, 0xC450, 0xD6BE,
+	0xC451, 0xD6BF, 0xC452, 0xD6C0, 0xC453, 0xD6C1, 0xC454, 0xD6C2,	0xC455, 0xD6C3, 0xC456, 0xD6C6, 0xC457, 0xD6C7, 0xC458, 0xD6C9,
+	0xC459, 0xD6CA, 0xC45A, 0xD6CB, 0xC461, 0xD6CD, 0xC462, 0xD6CE,	0xC463, 0xD6CF, 0xC464, 0xD6D0, 0xC465, 0xD6D2, 0xC466, 0xD6D3,
+	0xC467, 0xD6D5, 0xC468, 0xD6D6, 0xC469, 0xD6D8, 0xC46A, 0xD6DA,	0xC46B, 0xD6DB, 0xC46C, 0xD6DC, 0xC46D, 0xD6DD, 0xC46E, 0xD6DE,
+	0xC46F, 0xD6DF, 0xC470, 0xD6E1, 0xC471, 0xD6E2, 0xC472, 0xD6E3,	0xC473, 0xD6E5, 0xC474, 0xD6E6, 0xC475, 0xD6E7, 0xC476, 0xD6E9,
+	0xC477, 0xD6EA, 0xC478, 0xD6EB, 0xC479, 0xD6EC, 0xC47A, 0xD6ED,	0xC481, 0xD6EE, 0xC482, 0xD6EF, 0xC483, 0xD6F1, 0xC484, 0xD6F2,
+	0xC485, 0xD6F3, 0xC486, 0xD6F4, 0xC487, 0xD6F6, 0xC488, 0xD6F7,	0xC489, 0xD6F8, 0xC48A, 0xD6F9, 0xC48B, 0xD6FA, 0xC48C, 0xD6FB,
+	0xC48D, 0xD6FE, 0xC48E, 0xD6FF, 0xC48F, 0xD701, 0xC490, 0xD702,	0xC491, 0xD703, 0xC492, 0xD705, 0xC493, 0xD706, 0xC494, 0xD707,
+	0xC495, 0xD708, 0xC496, 0xD709, 0xC497, 0xD70A, 0xC498, 0xD70B,	0xC499, 0xD70C, 0xC49A, 0xD70D, 0xC49B, 0xD70E, 0xC49C, 0xD70F,
+	0xC49D, 0xD710, 0xC49E, 0xD712, 0xC49F, 0xD713, 0xC4A0, 0xD714,	0xC4A1, 0xCE58, 0xC4A2, 0xCE59, 0xC4A3, 0xCE5C, 0xC4A4, 0xCE5F,
+	0xC4A5, 0xCE60, 0xC4A6, 0xCE61, 0xC4A7, 0xCE68, 0xC4A8, 0xCE69,	0xC4A9, 0xCE6B, 0xC4AA, 0xCE6D, 0xC4AB, 0xCE74, 0xC4AC, 0xCE75,
+	0xC4AD, 0xCE78, 0xC4AE, 0xCE7C, 0xC4AF, 0xCE84, 0xC4B0, 0xCE85,	0xC4B1, 0xCE87, 0xC4B2, 0xCE89, 0xC4B3, 0xCE90, 0xC4B4, 0xCE91,
+	0xC4B5, 0xCE94, 0xC4B6, 0xCE98, 0xC4B7, 0xCEA0, 0xC4B8, 0xCEA1,	0xC4B9, 0xCEA3, 0xC4BA, 0xCEA4, 0xC4BB, 0xCEA5, 0xC4BC, 0xCEAC,
+	0xC4BD, 0xCEAD, 0xC4BE, 0xCEC1, 0xC4BF, 0xCEE4, 0xC4C0, 0xCEE5,	0xC4C1, 0xCEE8, 0xC4C2, 0xCEEB, 0xC4C3, 0xCEEC, 0xC4C4, 0xCEF4,
+	0xC4C5, 0xCEF5, 0xC4C6, 0xCEF7, 0xC4C7, 0xCEF8, 0xC4C8, 0xCEF9,	0xC4C9, 0xCF00, 0xC4CA, 0xCF01, 0xC4CB, 0xCF04, 0xC4CC, 0xCF08,
+	0xC4CD, 0xCF10, 0xC4CE, 0xCF11, 0xC4CF, 0xCF13, 0xC4D0, 0xCF15,	0xC4D1, 0xCF1C, 0xC4D2, 0xCF20, 0xC4D3, 0xCF24, 0xC4D4, 0xCF2C,
+	0xC4D5, 0xCF2D, 0xC4D6, 0xCF2F, 0xC4D7, 0xCF30, 0xC4D8, 0xCF31,	0xC4D9, 0xCF38, 0xC4DA, 0xCF54, 0xC4DB, 0xCF55, 0xC4DC, 0xCF58,
+	0xC4DD, 0xCF5C, 0xC4DE, 0xCF64, 0xC4DF, 0xCF65, 0xC4E0, 0xCF67,	0xC4E1, 0xCF69, 0xC4E2, 0xCF70, 0xC4E3, 0xCF71, 0xC4E4, 0xCF74,
+	0xC4E5, 0xCF78, 0xC4E6, 0xCF80, 0xC4E7, 0xCF85, 0xC4E8, 0xCF8C,	0xC4E9, 0xCFA1, 0xC4EA, 0xCFA8, 0xC4EB, 0xCFB0, 0xC4EC, 0xCFC4,
+	0xC4ED, 0xCFE0, 0xC4EE, 0xCFE1, 0xC4EF, 0xCFE4, 0xC4F0, 0xCFE8,	0xC4F1, 0xCFF0, 0xC4F2, 0xCFF1, 0xC4F3, 0xCFF3, 0xC4F4, 0xCFF5,
+	0xC4F5, 0xCFFC, 0xC4F6, 0xD000, 0xC4F7, 0xD004, 0xC4F8, 0xD011,	0xC4F9, 0xD018, 0xC4FA, 0xD02D, 0xC4FB, 0xD034, 0xC4FC, 0xD035,
+	0xC4FD, 0xD038, 0xC4FE, 0xD03C, 0xC541, 0xD715, 0xC542, 0xD716,	0xC543, 0xD717, 0xC544, 0xD71A, 0xC545, 0xD71B, 0xC546, 0xD71D,
+	0xC547, 0xD71E, 0xC548, 0xD71F, 0xC549, 0xD721, 0xC54A, 0xD722,	0xC54B, 0xD723, 0xC54C, 0xD724, 0xC54D, 0xD725, 0xC54E, 0xD726,
+	0xC54F, 0xD727, 0xC550, 0xD72A, 0xC551, 0xD72C, 0xC552, 0xD72E,	0xC553, 0xD72F, 0xC554, 0xD730, 0xC555, 0xD731, 0xC556, 0xD732,
+	0xC557, 0xD733, 0xC558, 0xD736, 0xC559, 0xD737, 0xC55A, 0xD739,	0xC561, 0xD73A, 0xC562, 0xD73B, 0xC563, 0xD73D, 0xC564, 0xD73E,
+	0xC565, 0xD73F, 0xC566, 0xD740, 0xC567, 0xD741, 0xC568, 0xD742,	0xC569, 0xD743, 0xC56A, 0xD745, 0xC56B, 0xD746, 0xC56C, 0xD748,
+	0xC56D, 0xD74A, 0xC56E, 0xD74B, 0xC56F, 0xD74C, 0xC570, 0xD74D,	0xC571, 0xD74E, 0xC572, 0xD74F, 0xC573, 0xD752, 0xC574, 0xD753,
+	0xC575, 0xD755, 0xC576, 0xD75A, 0xC577, 0xD75B, 0xC578, 0xD75C,	0xC579, 0xD75D, 0xC57A, 0xD75E, 0xC581, 0xD75F, 0xC582, 0xD762,
+	0xC583, 0xD764, 0xC584, 0xD766, 0xC585, 0xD767, 0xC586, 0xD768,	0xC587, 0xD76A, 0xC588, 0xD76B, 0xC589, 0xD76D, 0xC58A, 0xD76E,
+	0xC58B, 0xD76F, 0xC58C, 0xD771, 0xC58D, 0xD772, 0xC58E, 0xD773,	0xC58F, 0xD775, 0xC590, 0xD776, 0xC591, 0xD777, 0xC592, 0xD778,
+	0xC593, 0xD779, 0xC594, 0xD77A, 0xC595, 0xD77B, 0xC596, 0xD77E,	0xC597, 0xD77F, 0xC598, 0xD780, 0xC599, 0xD782, 0xC59A, 0xD783,
+	0xC59B, 0xD784, 0xC59C, 0xD785, 0xC59D, 0xD786, 0xC59E, 0xD787,	0xC59F, 0xD78A, 0xC5A0, 0xD78B, 0xC5A1, 0xD044, 0xC5A2, 0xD045,
+	0xC5A3, 0xD047, 0xC5A4, 0xD049, 0xC5A5, 0xD050, 0xC5A6, 0xD054,	0xC5A7, 0xD058, 0xC5A8, 0xD060, 0xC5A9, 0xD06C, 0xC5AA, 0xD06D,
+	0xC5AB, 0xD070, 0xC5AC, 0xD074, 0xC5AD, 0xD07C, 0xC5AE, 0xD07D,	0xC5AF, 0xD081, 0xC5B0, 0xD0A4, 0xC5B1, 0xD0A5, 0xC5B2, 0xD0A8,
+	0xC5B3, 0xD0AC, 0xC5B4, 0xD0B4, 0xC5B5, 0xD0B5, 0xC5B6, 0xD0B7,	0xC5B7, 0xD0B9, 0xC5B8, 0xD0C0, 0xC5B9, 0xD0C1, 0xC5BA, 0xD0C4,
+	0xC5BB, 0xD0C8, 0xC5BC, 0xD0C9, 0xC5BD, 0xD0D0, 0xC5BE, 0xD0D1,	0xC5BF, 0xD0D3, 0xC5C0, 0xD0D4, 0xC5C1, 0xD0D5, 0xC5C2, 0xD0DC,
+	0xC5C3, 0xD0DD, 0xC5C4, 0xD0E0, 0xC5C5, 0xD0E4, 0xC5C6, 0xD0EC,	0xC5C7, 0xD0ED, 0xC5C8, 0xD0EF, 0xC5C9, 0xD0F0, 0xC5CA, 0xD0F1,
+	0xC5CB, 0xD0F8, 0xC5CC, 0xD10D, 0xC5CD, 0xD130, 0xC5CE, 0xD131,	0xC5CF, 0xD134, 0xC5D0, 0xD138, 0xC5D1, 0xD13A, 0xC5D2, 0xD140,
+	0xC5D3, 0xD141, 0xC5D4, 0xD143, 0xC5D5, 0xD144, 0xC5D6, 0xD145,	0xC5D7, 0xD14C, 0xC5D8, 0xD14D, 0xC5D9, 0xD150, 0xC5DA, 0xD154,
+	0xC5DB, 0xD15C, 0xC5DC, 0xD15D, 0xC5DD, 0xD15F, 0xC5DE, 0xD161,	0xC5DF, 0xD168, 0xC5E0, 0xD16C, 0xC5E1, 0xD17C, 0xC5E2, 0xD184,
+	0xC5E3, 0xD188, 0xC5E4, 0xD1A0, 0xC5E5, 0xD1A1, 0xC5E6, 0xD1A4,	0xC5E7, 0xD1A8, 0xC5E8, 0xD1B0, 0xC5E9, 0xD1B1, 0xC5EA, 0xD1B3,
+	0xC5EB, 0xD1B5, 0xC5EC, 0xD1BA, 0xC5ED, 0xD1BC, 0xC5EE, 0xD1C0,	0xC5EF, 0xD1D8, 0xC5F0, 0xD1F4, 0xC5F1, 0xD1F8, 0xC5F2, 0xD207,
+	0xC5F3, 0xD209, 0xC5F4, 0xD210, 0xC5F5, 0xD22C, 0xC5F6, 0xD22D,	0xC5F7, 0xD230, 0xC5F8, 0xD234, 0xC5F9, 0xD23C, 0xC5FA, 0xD23D,
+	0xC5FB, 0xD23F, 0xC5FC, 0xD241, 0xC5FD, 0xD248, 0xC5FE, 0xD25C,	0xC641, 0xD78D, 0xC642, 0xD78E, 0xC643, 0xD78F, 0xC644, 0xD791,
+	0xC645, 0xD792, 0xC646, 0xD793, 0xC647, 0xD794, 0xC648, 0xD795,	0xC649, 0xD796, 0xC64A, 0xD797, 0xC64B, 0xD79A, 0xC64C, 0xD79C,
+	0xC64D, 0xD79E, 0xC64E, 0xD79F, 0xC64F, 0xD7A0, 0xC650, 0xD7A1,	0xC651, 0xD7A2, 0xC652, 0xD7A3, 0xC6A1, 0xD264, 0xC6A2, 0xD280,
+	0xC6A3, 0xD281, 0xC6A4, 0xD284, 0xC6A5, 0xD288, 0xC6A6, 0xD290,	0xC6A7, 0xD291, 0xC6A8, 0xD295, 0xC6A9, 0xD29C, 0xC6AA, 0xD2A0,
+	0xC6AB, 0xD2A4, 0xC6AC, 0xD2AC, 0xC6AD, 0xD2B1, 0xC6AE, 0xD2B8,	0xC6AF, 0xD2B9, 0xC6B0, 0xD2BC, 0xC6B1, 0xD2BF, 0xC6B2, 0xD2C0,
+	0xC6B3, 0xD2C2, 0xC6B4, 0xD2C8, 0xC6B5, 0xD2C9, 0xC6B6, 0xD2CB,	0xC6B7, 0xD2D4, 0xC6B8, 0xD2D8, 0xC6B9, 0xD2DC, 0xC6BA, 0xD2E4,
+	0xC6BB, 0xD2E5, 0xC6BC, 0xD2F0, 0xC6BD, 0xD2F1, 0xC6BE, 0xD2F4,	0xC6BF, 0xD2F8, 0xC6C0, 0xD300, 0xC6C1, 0xD301, 0xC6C2, 0xD303,
+	0xC6C3, 0xD305, 0xC6C4, 0xD30C, 0xC6C5, 0xD30D, 0xC6C6, 0xD30E,	0xC6C7, 0xD310, 0xC6C8, 0xD314, 0xC6C9, 0xD316, 0xC6CA, 0xD31C,
+	0xC6CB, 0xD31D, 0xC6CC, 0xD31F, 0xC6CD, 0xD320, 0xC6CE, 0xD321,	0xC6CF, 0xD325, 0xC6D0, 0xD328, 0xC6D1, 0xD329, 0xC6D2, 0xD32C,
+	0xC6D3, 0xD330, 0xC6D4, 0xD338, 0xC6D5, 0xD339, 0xC6D6, 0xD33B,	0xC6D7, 0xD33C, 0xC6D8, 0xD33D, 0xC6D9, 0xD344, 0xC6DA, 0xD345,
+	0xC6DB, 0xD37C, 0xC6DC, 0xD37D, 0xC6DD, 0xD380, 0xC6DE, 0xD384,	0xC6DF, 0xD38C, 0xC6E0, 0xD38D, 0xC6E1, 0xD38F, 0xC6E2, 0xD390,
+	0xC6E3, 0xD391, 0xC6E4, 0xD398, 0xC6E5, 0xD399, 0xC6E6, 0xD39C,	0xC6E7, 0xD3A0, 0xC6E8, 0xD3A8, 0xC6E9, 0xD3A9, 0xC6EA, 0xD3AB,
+	0xC6EB, 0xD3AD, 0xC6EC, 0xD3B4, 0xC6ED, 0xD3B8, 0xC6EE, 0xD3BC,	0xC6EF, 0xD3C4, 0xC6F0, 0xD3C5, 0xC6F1, 0xD3C8, 0xC6F2, 0xD3C9,
+	0xC6F3, 0xD3D0, 0xC6F4, 0xD3D8, 0xC6F5, 0xD3E1, 0xC6F6, 0xD3E3,	0xC6F7, 0xD3EC, 0xC6F8, 0xD3ED, 0xC6F9, 0xD3F0, 0xC6FA, 0xD3F4,
+	0xC6FB, 0xD3FC, 0xC6FC, 0xD3FD, 0xC6FD, 0xD3FF, 0xC6FE, 0xD401,	0xC7A1, 0xD408, 0xC7A2, 0xD41D, 0xC7A3, 0xD440, 0xC7A4, 0xD444,
+	0xC7A5, 0xD45C, 0xC7A6, 0xD460, 0xC7A7, 0xD464, 0xC7A8, 0xD46D,	0xC7A9, 0xD46F, 0xC7AA, 0xD478, 0xC7AB, 0xD479, 0xC7AC, 0xD47C,
+	0xC7AD, 0xD47F, 0xC7AE, 0xD480, 0xC7AF, 0xD482, 0xC7B0, 0xD488,	0xC7B1, 0xD489, 0xC7B2, 0xD48B, 0xC7B3, 0xD48D, 0xC7B4, 0xD494,
+	0xC7B5, 0xD4A9, 0xC7B6, 0xD4CC, 0xC7B7, 0xD4D0, 0xC7B8, 0xD4D4,	0xC7B9, 0xD4DC, 0xC7BA, 0xD4DF, 0xC7BB, 0xD4E8, 0xC7BC, 0xD4EC,
+	0xC7BD, 0xD4F0, 0xC7BE, 0xD4F8, 0xC7BF, 0xD4FB, 0xC7C0, 0xD4FD,	0xC7C1, 0xD504, 0xC7C2, 0xD508, 0xC7C3, 0xD50C, 0xC7C4, 0xD514,
+	0xC7C5, 0xD515, 0xC7C6, 0xD517, 0xC7C7, 0xD53C, 0xC7C8, 0xD53D,	0xC7C9, 0xD540, 0xC7CA, 0xD544, 0xC7CB, 0xD54C, 0xC7CC, 0xD54D,
+	0xC7CD, 0xD54F, 0xC7CE, 0xD551, 0xC7CF, 0xD558, 0xC7D0, 0xD559,	0xC7D1, 0xD55C, 0xC7D2, 0xD560, 0xC7D3, 0xD565, 0xC7D4, 0xD568,
+	0xC7D5, 0xD569, 0xC7D6, 0xD56B, 0xC7D7, 0xD56D, 0xC7D8, 0xD574,	0xC7D9, 0xD575, 0xC7DA, 0xD578, 0xC7DB, 0xD57C, 0xC7DC, 0xD584,
+	0xC7DD, 0xD585, 0xC7DE, 0xD587, 0xC7DF, 0xD588, 0xC7E0, 0xD589,	0xC7E1, 0xD590, 0xC7E2, 0xD5A5, 0xC7E3, 0xD5C8, 0xC7E4, 0xD5C9,
+	0xC7E5, 0xD5CC, 0xC7E6, 0xD5D0, 0xC7E7, 0xD5D2, 0xC7E8, 0xD5D8,	0xC7E9, 0xD5D9, 0xC7EA, 0xD5DB, 0xC7EB, 0xD5DD, 0xC7EC, 0xD5E4,
+	0xC7ED, 0xD5E5, 0xC7EE, 0xD5E8, 0xC7EF, 0xD5EC, 0xC7F0, 0xD5F4,	0xC7F1, 0xD5F5, 0xC7F2, 0xD5F7, 0xC7F3, 0xD5F9, 0xC7F4, 0xD600,
+	0xC7F5, 0xD601, 0xC7F6, 0xD604, 0xC7F7, 0xD608, 0xC7F8, 0xD610,	0xC7F9, 0xD611, 0xC7FA, 0xD613, 0xC7FB, 0xD614, 0xC7FC, 0xD615,
+	0xC7FD, 0xD61C, 0xC7FE, 0xD620, 0xC8A1, 0xD624, 0xC8A2, 0xD62D,	0xC8A3, 0xD638, 0xC8A4, 0xD639, 0xC8A5, 0xD63C, 0xC8A6, 0xD640,
+	0xC8A7, 0xD645, 0xC8A8, 0xD648, 0xC8A9, 0xD649, 0xC8AA, 0xD64B,	0xC8AB, 0xD64D, 0xC8AC, 0xD651, 0xC8AD, 0xD654, 0xC8AE, 0xD655,
+	0xC8AF, 0xD658, 0xC8B0, 0xD65C, 0xC8B1, 0xD667, 0xC8B2, 0xD669,	0xC8B3, 0xD670, 0xC8B4, 0xD671, 0xC8B5, 0xD674, 0xC8B6, 0xD683,
+	0xC8B7, 0xD685, 0xC8B8, 0xD68C, 0xC8B9, 0xD68D, 0xC8BA, 0xD690,	0xC8BB, 0xD694, 0xC8BC, 0xD69D, 0xC8BD, 0xD69F, 0xC8BE, 0xD6A1,
+	0xC8BF, 0xD6A8, 0xC8C0, 0xD6AC, 0xC8C1, 0xD6B0, 0xC8C2, 0xD6B9,	0xC8C3, 0xD6BB, 0xC8C4, 0xD6C4, 0xC8C5, 0xD6C5, 0xC8C6, 0xD6C8,
+	0xC8C7, 0xD6CC, 0xC8C8, 0xD6D1, 0xC8C9, 0xD6D4, 0xC8CA, 0xD6D7,	0xC8CB, 0xD6D9, 0xC8CC, 0xD6E0, 0xC8CD, 0xD6E4, 0xC8CE, 0xD6E8,
+	0xC8CF, 0xD6F0, 0xC8D0, 0xD6F5, 0xC8D1, 0xD6FC, 0xC8D2, 0xD6FD,	0xC8D3, 0xD700, 0xC8D4, 0xD704, 0xC8D5, 0xD711, 0xC8D6, 0xD718,
+	0xC8D7, 0xD719, 0xC8D8, 0xD71C, 0xC8D9, 0xD720, 0xC8DA, 0xD728,	0xC8DB, 0xD729, 0xC8DC, 0xD72B, 0xC8DD, 0xD72D, 0xC8DE, 0xD734,
+	0xC8DF, 0xD735, 0xC8E0, 0xD738, 0xC8E1, 0xD73C, 0xC8E2, 0xD744,	0xC8E3, 0xD747, 0xC8E4, 0xD749, 0xC8E5, 0xD750, 0xC8E6, 0xD751,
+	0xC8E7, 0xD754, 0xC8E8, 0xD756, 0xC8E9, 0xD757, 0xC8EA, 0xD758,	0xC8EB, 0xD759, 0xC8EC, 0xD760, 0xC8ED, 0xD761, 0xC8EE, 0xD763,
+	0xC8EF, 0xD765, 0xC8F0, 0xD769, 0xC8F1, 0xD76C, 0xC8F2, 0xD770,	0xC8F3, 0xD774, 0xC8F4, 0xD77C, 0xC8F5, 0xD77D, 0xC8F6, 0xD781,
+	0xC8F7, 0xD788, 0xC8F8, 0xD789, 0xC8F9, 0xD78C, 0xC8FA, 0xD790,	0xC8FB, 0xD798, 0xC8FC, 0xD799, 0xC8FD, 0xD79B, 0xC8FE, 0xD79D,
+	0xCAA1, 0x4F3D, 0xCAA2, 0x4F73, 0xCAA3, 0x5047, 0xCAA4, 0x50F9,	0xCAA5, 0x52A0, 0xCAA6, 0x53EF, 0xCAA7, 0x5475, 0xCAA8, 0x54E5,
+	0xCAA9, 0x5609, 0xCAAA, 0x5AC1, 0xCAAB, 0x5BB6, 0xCAAC, 0x6687,	0xCAAD, 0x67B6, 0xCAAE, 0x67B7, 0xCAAF, 0x67EF, 0xCAB0, 0x6B4C,
+	0xCAB1, 0x73C2, 0xCAB2, 0x75C2, 0xCAB3, 0x7A3C, 0xCAB4, 0x82DB,	0xCAB5, 0x8304, 0xCAB6, 0x8857, 0xCAB7, 0x8888, 0xCAB8, 0x8A36,
+	0xCAB9, 0x8CC8, 0xCABA, 0x8DCF, 0xCABB, 0x8EFB, 0xCABC, 0x8FE6,	0xCABD, 0x99D5, 0xCABE, 0x523B, 0xCABF, 0x5374, 0xCAC0, 0x5404,
+	0xCAC1, 0x606A, 0xCAC2, 0x6164, 0xCAC3, 0x6BBC, 0xCAC4, 0x73CF,	0xCAC5, 0x811A, 0xCAC6, 0x89BA, 0xCAC7, 0x89D2, 0xCAC8, 0x95A3,
+	0xCAC9, 0x4F83, 0xCACA, 0x520A, 0xCACB, 0x58BE, 0xCACC, 0x5978,	0xCACD, 0x59E6, 0xCACE, 0x5E72, 0xCACF, 0x5E79, 0xCAD0, 0x61C7,
+	0xCAD1, 0x63C0, 0xCAD2, 0x6746, 0xCAD3, 0x67EC, 0xCAD4, 0x687F,	0xCAD5, 0x6F97, 0xCAD6, 0x764E, 0xCAD7, 0x770B, 0xCAD8, 0x78F5,
+	0xCAD9, 0x7A08, 0xCADA, 0x7AFF, 0xCADB, 0x7C21, 0xCADC, 0x809D,	0xCADD, 0x826E, 0xCADE, 0x8271, 0xCADF, 0x8AEB, 0xCAE0, 0x9593,
+	0xCAE1, 0x4E6B, 0xCAE2, 0x559D, 0xCAE3, 0x66F7, 0xCAE4, 0x6E34,	0xCAE5, 0x78A3, 0xCAE6, 0x7AED, 0xCAE7, 0x845B, 0xCAE8, 0x8910,
+	0xCAE9, 0x874E, 0xCAEA, 0x97A8, 0xCAEB, 0x52D8, 0xCAEC, 0x574E,	0xCAED, 0x582A, 0xCAEE, 0x5D4C, 0xCAEF, 0x611F, 0xCAF0, 0x61BE,
+	0xCAF1, 0x6221, 0xCAF2, 0x6562, 0xCAF3, 0x67D1, 0xCAF4, 0x6A44,	0xCAF5, 0x6E1B, 0xCAF6, 0x7518, 0xCAF7, 0x75B3, 0xCAF8, 0x76E3,
+	0xCAF9, 0x77B0, 0xCAFA, 0x7D3A, 0xCAFB, 0x90AF, 0xCAFC, 0x9451,	0xCAFD, 0x9452, 0xCAFE, 0x9F95, 0xCBA1, 0x5323, 0xCBA2, 0x5CAC,
+	0xCBA3, 0x7532, 0xCBA4, 0x80DB, 0xCBA5, 0x9240, 0xCBA6, 0x9598,	0xCBA7, 0x525B, 0xCBA8, 0x5808, 0xCBA9, 0x59DC, 0xCBAA, 0x5CA1,
+	0xCBAB, 0x5D17, 0xCBAC, 0x5EB7, 0xCBAD, 0x5F3A, 0xCBAE, 0x5F4A,	0xCBAF, 0x6177, 0xCBB0, 0x6C5F, 0xCBB1, 0x757A, 0xCBB2, 0x7586,
+	0xCBB3, 0x7CE0, 0xCBB4, 0x7D73, 0xCBB5, 0x7DB1, 0xCBB6, 0x7F8C,	0xCBB7, 0x8154, 0xCBB8, 0x8221, 0xCBB9, 0x8591, 0xCBBA, 0x8941,
+	0xCBBB, 0x8B1B, 0xCBBC, 0x92FC, 0xCBBD, 0x964D, 0xCBBE, 0x9C47,	0xCBBF, 0x4ECB, 0xCBC0, 0x4EF7, 0xCBC1, 0x500B, 0xCBC2, 0x51F1,
+	0xCBC3, 0x584F, 0xCBC4, 0x6137, 0xCBC5, 0x613E, 0xCBC6, 0x6168,	0xCBC7, 0x6539, 0xCBC8, 0x69EA, 0xCBC9, 0x6F11, 0xCBCA, 0x75A5,
+	0xCBCB, 0x7686, 0xCBCC, 0x76D6, 0xCBCD, 0x7B87, 0xCBCE, 0x82A5,	0xCBCF, 0x84CB, 0xCBD0, 0xF900, 0xCBD1, 0x93A7, 0xCBD2, 0x958B,
+	0xCBD3, 0x5580, 0xCBD4, 0x5BA2, 0xCBD5, 0x5751, 0xCBD6, 0xF901,	0xCBD7, 0x7CB3, 0xCBD8, 0x7FB9, 0xCBD9, 0x91B5, 0xCBDA, 0x5028,
+	0xCBDB, 0x53BB, 0xCBDC, 0x5C45, 0xCBDD, 0x5DE8, 0xCBDE, 0x62D2,	0xCBDF, 0x636E, 0xCBE0, 0x64DA, 0xCBE1, 0x64E7, 0xCBE2, 0x6E20,
+	0xCBE3, 0x70AC, 0xCBE4, 0x795B, 0xCBE5, 0x8DDD, 0xCBE6, 0x8E1E,	0xCBE7, 0xF902, 0xCBE8, 0x907D, 0xCBE9, 0x9245, 0xCBEA, 0x92F8,
+	0xCBEB, 0x4E7E, 0xCBEC, 0x4EF6, 0xCBED, 0x5065, 0xCBEE, 0x5DFE,	0xCBEF, 0x5EFA, 0xCBF0, 0x6106, 0xCBF1, 0x6957, 0xCBF2, 0x8171,
+	0xCBF3, 0x8654, 0xCBF4, 0x8E47, 0xCBF5, 0x9375, 0xCBF6, 0x9A2B,	0xCBF7, 0x4E5E, 0xCBF8, 0x5091, 0xCBF9, 0x6770, 0xCBFA, 0x6840,
+	0xCBFB, 0x5109, 0xCBFC, 0x528D, 0xCBFD, 0x5292, 0xCBFE, 0x6AA2,	0xCCA1, 0x77BC, 0xCCA2, 0x9210, 0xCCA3, 0x9ED4, 0xCCA4, 0x52AB,
+	0xCCA5, 0x602F, 0xCCA6, 0x8FF2, 0xCCA7, 0x5048, 0xCCA8, 0x61A9,	0xCCA9, 0x63ED, 0xCCAA, 0x64CA, 0xCCAB, 0x683C, 0xCCAC, 0x6A84,
+	0xCCAD, 0x6FC0, 0xCCAE, 0x8188, 0xCCAF, 0x89A1, 0xCCB0, 0x9694,	0xCCB1, 0x5805, 0xCCB2, 0x727D, 0xCCB3, 0x72AC, 0xCCB4, 0x7504,
+	0xCCB5, 0x7D79, 0xCCB6, 0x7E6D, 0xCCB7, 0x80A9, 0xCCB8, 0x898B,	0xCCB9, 0x8B74, 0xCCBA, 0x9063, 0xCCBB, 0x9D51, 0xCCBC, 0x6289,
+	0xCCBD, 0x6C7A, 0xCCBE, 0x6F54, 0xCCBF, 0x7D50, 0xCCC0, 0x7F3A,	0xCCC1, 0x8A23, 0xCCC2, 0x517C, 0xCCC3, 0x614A, 0xCCC4, 0x7B9D,
+	0xCCC5, 0x8B19, 0xCCC6, 0x9257, 0xCCC7, 0x938C, 0xCCC8, 0x4EAC,	0xCCC9, 0x4FD3, 0xCCCA, 0x501E, 0xCCCB, 0x50BE, 0xCCCC, 0x5106,
+	0xCCCD, 0x52C1, 0xCCCE, 0x52CD, 0xCCCF, 0x537F, 0xCCD0, 0x5770,	0xCCD1, 0x5883, 0xCCD2, 0x5E9A, 0xCCD3, 0x5F91, 0xCCD4, 0x6176,
+	0xCCD5, 0x61AC, 0xCCD6, 0x64CE, 0xCCD7, 0x656C, 0xCCD8, 0x666F,	0xCCD9, 0x66BB, 0xCCDA, 0x66F4, 0xCCDB, 0x6897, 0xCCDC, 0x6D87,
+	0xCCDD, 0x7085, 0xCCDE, 0x70F1, 0xCCDF, 0x749F, 0xCCE0, 0x74A5,	0xCCE1, 0x74CA, 0xCCE2, 0x75D9, 0xCCE3, 0x786C, 0xCCE4, 0x78EC,
+	0xCCE5, 0x7ADF, 0xCCE6, 0x7AF6, 0xCCE7, 0x7D45, 0xCCE8, 0x7D93,	0xCCE9, 0x8015, 0xCCEA, 0x803F, 0xCCEB, 0x811B, 0xCCEC, 0x8396,
+	0xCCED, 0x8B66, 0xCCEE, 0x8F15, 0xCCEF, 0x9015, 0xCCF0, 0x93E1,	0xCCF1, 0x9803, 0xCCF2, 0x9838, 0xCCF3, 0x9A5A, 0xCCF4, 0x9BE8,
+	0xCCF5, 0x4FC2, 0xCCF6, 0x5553, 0xCCF7, 0x583A, 0xCCF8, 0x5951,	0xCCF9, 0x5B63, 0xCCFA, 0x5C46, 0xCCFB, 0x60B8, 0xCCFC, 0x6212,
+	0xCCFD, 0x6842, 0xCCFE, 0x68B0, 0xCDA1, 0x68E8, 0xCDA2, 0x6EAA,	0xCDA3, 0x754C, 0xCDA4, 0x7678, 0xCDA5, 0x78CE, 0xCDA6, 0x7A3D,
+	0xCDA7, 0x7CFB, 0xCDA8, 0x7E6B, 0xCDA9, 0x7E7C, 0xCDAA, 0x8A08,	0xCDAB, 0x8AA1, 0xCDAC, 0x8C3F, 0xCDAD, 0x968E, 0xCDAE, 0x9DC4,
+	0xCDAF, 0x53E4, 0xCDB0, 0x53E9, 0xCDB1, 0x544A, 0xCDB2, 0x5471,	0xCDB3, 0x56FA, 0xCDB4, 0x59D1, 0xCDB5, 0x5B64, 0xCDB6, 0x5C3B,
+	0xCDB7, 0x5EAB, 0xCDB8, 0x62F7, 0xCDB9, 0x6537, 0xCDBA, 0x6545,	0xCDBB, 0x6572, 0xCDBC, 0x66A0, 0xCDBD, 0x67AF, 0xCDBE, 0x69C1,
+	0xCDBF, 0x6CBD, 0xCDC0, 0x75FC, 0xCDC1, 0x7690, 0xCDC2, 0x777E,	0xCDC3, 0x7A3F, 0xCDC4, 0x7F94, 0xCDC5, 0x8003, 0xCDC6, 0x80A1,
+	0xCDC7, 0x818F, 0xCDC8, 0x82E6, 0xCDC9, 0x82FD, 0xCDCA, 0x83F0,	0xCDCB, 0x85C1, 0xCDCC, 0x8831, 0xCDCD, 0x88B4, 0xCDCE, 0x8AA5,
+	0xCDCF, 0xF903, 0xCDD0, 0x8F9C, 0xCDD1, 0x932E, 0xCDD2, 0x96C7,	0xCDD3, 0x9867, 0xCDD4, 0x9AD8, 0xCDD5, 0x9F13, 0xCDD6, 0x54ED,
+	0xCDD7, 0x659B, 0xCDD8, 0x66F2, 0xCDD9, 0x688F, 0xCDDA, 0x7A40,	0xCDDB, 0x8C37, 0xCDDC, 0x9D60, 0xCDDD, 0x56F0, 0xCDDE, 0x5764,
+	0xCDDF, 0x5D11, 0xCDE0, 0x6606, 0xCDE1, 0x68B1, 0xCDE2, 0x68CD,	0xCDE3, 0x6EFE, 0xCDE4, 0x7428, 0xCDE5, 0x889E, 0xCDE6, 0x9BE4,
+	0xCDE7, 0x6C68, 0xCDE8, 0xF904, 0xCDE9, 0x9AA8, 0xCDEA, 0x4F9B,	0xCDEB, 0x516C, 0xCDEC, 0x5171, 0xCDED, 0x529F, 0xCDEE, 0x5B54,
+	0xCDEF, 0x5DE5, 0xCDF0, 0x6050, 0xCDF1, 0x606D, 0xCDF2, 0x62F1,	0xCDF3, 0x63A7, 0xCDF4, 0x653B, 0xCDF5, 0x73D9, 0xCDF6, 0x7A7A,
+	0xCDF7, 0x86A3, 0xCDF8, 0x8CA2, 0xCDF9, 0x978F, 0xCDFA, 0x4E32,	0xCDFB, 0x5BE1, 0xCDFC, 0x6208, 0xCDFD, 0x679C, 0xCDFE, 0x74DC,
+	0xCEA1, 0x79D1, 0xCEA2, 0x83D3, 0xCEA3, 0x8A87, 0xCEA4, 0x8AB2,	0xCEA5, 0x8DE8, 0xCEA6, 0x904E, 0xCEA7, 0x934B, 0xCEA8, 0x9846,
+	0xCEA9, 0x5ED3, 0xCEAA, 0x69E8, 0xCEAB, 0x85FF, 0xCEAC, 0x90ED,	0xCEAD, 0xF905, 0xCEAE, 0x51A0, 0xCEAF, 0x5B98, 0xCEB0, 0x5BEC,
+	0xCEB1, 0x6163, 0xCEB2, 0x68FA, 0xCEB3, 0x6B3E, 0xCEB4, 0x704C,	0xCEB5, 0x742F, 0xCEB6, 0x74D8, 0xCEB7, 0x7BA1, 0xCEB8, 0x7F50,
+	0xCEB9, 0x83C5, 0xCEBA, 0x89C0, 0xCEBB, 0x8CAB, 0xCEBC, 0x95DC,	0xCEBD, 0x9928, 0xCEBE, 0x522E, 0xCEBF, 0x605D, 0xCEC0, 0x62EC,
+	0xCEC1, 0x9002, 0xCEC2, 0x4F8A, 0xCEC3, 0x5149, 0xCEC4, 0x5321,	0xCEC5, 0x58D9, 0xCEC6, 0x5EE3, 0xCEC7, 0x66E0, 0xCEC8, 0x6D38,
+	0xCEC9, 0x709A, 0xCECA, 0x72C2, 0xCECB, 0x73D6, 0xCECC, 0x7B50,	0xCECD, 0x80F1, 0xCECE, 0x945B, 0xCECF, 0x5366, 0xCED0, 0x639B,
+	0xCED1, 0x7F6B, 0xCED2, 0x4E56, 0xCED3, 0x5080, 0xCED4, 0x584A,	0xCED5, 0x58DE, 0xCED6, 0x602A, 0xCED7, 0x6127, 0xCED8, 0x62D0,
+	0xCED9, 0x69D0, 0xCEDA, 0x9B41, 0xCEDB, 0x5B8F, 0xCEDC, 0x7D18,	0xCEDD, 0x80B1, 0xCEDE, 0x8F5F, 0xCEDF, 0x4EA4, 0xCEE0, 0x50D1,
+	0xCEE1, 0x54AC, 0xCEE2, 0x55AC, 0xCEE3, 0x5B0C, 0xCEE4, 0x5DA0,	0xCEE5, 0x5DE7, 0xCEE6, 0x652A, 0xCEE7, 0x654E, 0xCEE8, 0x6821,
+	0xCEE9, 0x6A4B, 0xCEEA, 0x72E1, 0xCEEB, 0x768E, 0xCEEC, 0x77EF,	0xCEED, 0x7D5E, 0xCEEE, 0x7FF9, 0xCEEF, 0x81A0, 0xCEF0, 0x854E,
+	0xCEF1, 0x86DF, 0xCEF2, 0x8F03, 0xCEF3, 0x8F4E, 0xCEF4, 0x90CA,	0xCEF5, 0x9903, 0xCEF6, 0x9A55, 0xCEF7, 0x9BAB, 0xCEF8, 0x4E18,
+	0xCEF9, 0x4E45, 0xCEFA, 0x4E5D, 0xCEFB, 0x4EC7, 0xCEFC, 0x4FF1,	0xCEFD, 0x5177, 0xCEFE, 0x52FE, 0xCFA1, 0x5340, 0xCFA2, 0x53E3,
+	0xCFA3, 0x53E5, 0xCFA4, 0x548E, 0xCFA5, 0x5614, 0xCFA6, 0x5775,	0xCFA7, 0x57A2, 0xCFA8, 0x5BC7, 0xCFA9, 0x5D87, 0xCFAA, 0x5ED0,
+	0xCFAB, 0x61FC, 0xCFAC, 0x62D8, 0xCFAD, 0x6551, 0xCFAE, 0x67B8,	0xCFAF, 0x67E9, 0xCFB0, 0x69CB, 0xCFB1, 0x6B50, 0xCFB2, 0x6BC6,
+	0xCFB3, 0x6BEC, 0xCFB4, 0x6C42, 0xCFB5, 0x6E9D, 0xCFB6, 0x7078,	0xCFB7, 0x72D7, 0xCFB8, 0x7396, 0xCFB9, 0x7403, 0xCFBA, 0x77BF,
+	0xCFBB, 0x77E9, 0xCFBC, 0x7A76, 0xCFBD, 0x7D7F, 0xCFBE, 0x8009,	0xCFBF, 0x81FC, 0xCFC0, 0x8205, 0xCFC1, 0x820A, 0xCFC2, 0x82DF,
+	0xCFC3, 0x8862, 0xCFC4, 0x8B33, 0xCFC5, 0x8CFC, 0xCFC6, 0x8EC0,	0xCFC7, 0x9011, 0xCFC8, 0x90B1, 0xCFC9, 0x9264, 0xCFCA, 0x92B6,
+	0xCFCB, 0x99D2, 0xCFCC, 0x9A45, 0xCFCD, 0x9CE9, 0xCFCE, 0x9DD7,	0xCFCF, 0x9F9C, 0xCFD0, 0x570B, 0xCFD1, 0x5C40, 0xCFD2, 0x83CA,
+	0xCFD3, 0x97A0, 0xCFD4, 0x97AB, 0xCFD5, 0x9EB4, 0xCFD6, 0x541B,	0xCFD7, 0x7A98, 0xCFD8, 0x7FA4, 0xCFD9, 0x88D9, 0xCFDA, 0x8ECD,
+	0xCFDB, 0x90E1, 0xCFDC, 0x5800, 0xCFDD, 0x5C48, 0xCFDE, 0x6398,	0xCFDF, 0x7A9F, 0xCFE0, 0x5BAE, 0xCFE1, 0x5F13, 0xCFE2, 0x7A79,
+	0xCFE3, 0x7AAE, 0xCFE4, 0x828E, 0xCFE5, 0x8EAC, 0xCFE6, 0x5026,	0xCFE7, 0x5238, 0xCFE8, 0x52F8, 0xCFE9, 0x5377, 0xCFEA, 0x5708,
+	0xCFEB, 0x62F3, 0xCFEC, 0x6372, 0xCFED, 0x6B0A, 0xCFEE, 0x6DC3,	0xCFEF, 0x7737, 0xCFF0, 0x53A5, 0xCFF1, 0x7357, 0xCFF2, 0x8568,
+	0xCFF3, 0x8E76, 0xCFF4, 0x95D5, 0xCFF5, 0x673A, 0xCFF6, 0x6AC3,	0xCFF7, 0x6F70, 0xCFF8, 0x8A6D, 0xCFF9, 0x8ECC, 0xCFFA, 0x994B,
+	0xCFFB, 0xF906, 0xCFFC, 0x6677, 0xCFFD, 0x6B78, 0xCFFE, 0x8CB4,	0xD0A1, 0x9B3C, 0xD0A2, 0xF907, 0xD0A3, 0x53EB, 0xD0A4, 0x572D,
+	0xD0A5, 0x594E, 0xD0A6, 0x63C6, 0xD0A7, 0x69FB, 0xD0A8, 0x73EA,	0xD0A9, 0x7845, 0xD0AA, 0x7ABA, 0xD0AB, 0x7AC5, 0xD0AC, 0x7CFE,
+	0xD0AD, 0x8475, 0xD0AE, 0x898F, 0xD0AF, 0x8D73, 0xD0B0, 0x9035,	0xD0B1, 0x95A8, 0xD0B2, 0x52FB, 0xD0B3, 0x5747, 0xD0B4, 0x7547,
+	0xD0B5, 0x7B60, 0xD0B6, 0x83CC, 0xD0B7, 0x921E, 0xD0B8, 0xF908,	0xD0B9, 0x6A58, 0xD0BA, 0x514B, 0xD0BB, 0x524B, 0xD0BC, 0x5287,
+	0xD0BD, 0x621F, 0xD0BE, 0x68D8, 0xD0BF, 0x6975, 0xD0C0, 0x9699,	0xD0C1, 0x50C5, 0xD0C2, 0x52A4, 0xD0C3, 0x52E4, 0xD0C4, 0x61C3,
+	0xD0C5, 0x65A4, 0xD0C6, 0x6839, 0xD0C7, 0x69FF, 0xD0C8, 0x747E,	0xD0C9, 0x7B4B, 0xD0CA, 0x82B9, 0xD0CB, 0x83EB, 0xD0CC, 0x89B2,
+	0xD0CD, 0x8B39, 0xD0CE, 0x8FD1, 0xD0CF, 0x9949, 0xD0D0, 0xF909,	0xD0D1, 0x4ECA, 0xD0D2, 0x5997, 0xD0D3, 0x64D2, 0xD0D4, 0x6611,
+	0xD0D5, 0x6A8E, 0xD0D6, 0x7434, 0xD0D7, 0x7981, 0xD0D8, 0x79BD,	0xD0D9, 0x82A9, 0xD0DA, 0x887E, 0xD0DB, 0x887F, 0xD0DC, 0x895F,
+	0xD0DD, 0xF90A, 0xD0DE, 0x9326, 0xD0DF, 0x4F0B, 0xD0E0, 0x53CA,	0xD0E1, 0x6025, 0xD0E2, 0x6271, 0xD0E3, 0x6C72, 0xD0E4, 0x7D1A,
+	0xD0E5, 0x7D66, 0xD0E6, 0x4E98, 0xD0E7, 0x5162, 0xD0E8, 0x77DC,	0xD0E9, 0x80AF, 0xD0EA, 0x4F01, 0xD0EB, 0x4F0E, 0xD0EC, 0x5176,
+	0xD0ED, 0x5180, 0xD0EE, 0x55DC, 0xD0EF, 0x5668, 0xD0F0, 0x573B,	0xD0F1, 0x57FA, 0xD0F2, 0x57FC, 0xD0F3, 0x5914, 0xD0F4, 0x5947,
+	0xD0F5, 0x5993, 0xD0F6, 0x5BC4, 0xD0F7, 0x5C90, 0xD0F8, 0x5D0E,	0xD0F9, 0x5DF1, 0xD0FA, 0x5E7E, 0xD0FB, 0x5FCC, 0xD0FC, 0x6280,
+	0xD0FD, 0x65D7, 0xD0FE, 0x65E3, 0xD1A1, 0x671E, 0xD1A2, 0x671F,	0xD1A3, 0x675E, 0xD1A4, 0x68CB, 0xD1A5, 0x68C4, 0xD1A6, 0x6A5F,
+	0xD1A7, 0x6B3A, 0xD1A8, 0x6C23, 0xD1A9, 0x6C7D, 0xD1AA, 0x6C82,	0xD1AB, 0x6DC7, 0xD1AC, 0x7398, 0xD1AD, 0x7426, 0xD1AE, 0x742A,
+	0xD1AF, 0x7482, 0xD1B0, 0x74A3, 0xD1B1, 0x7578, 0xD1B2, 0x757F,	0xD1B3, 0x7881, 0xD1B4, 0x78EF, 0xD1B5, 0x7941, 0xD1B6, 0x7947,
+	0xD1B7, 0x7948, 0xD1B8, 0x797A, 0xD1B9, 0x7B95, 0xD1BA, 0x7D00,	0xD1BB, 0x7DBA, 0xD1BC, 0x7F88, 0xD1BD, 0x8006, 0xD1BE, 0x802D,
+	0xD1BF, 0x808C, 0xD1C0, 0x8A18, 0xD1C1, 0x8B4F, 0xD1C2, 0x8C48,	0xD1C3, 0x8D77, 0xD1C4, 0x9321, 0xD1C5, 0x9324, 0xD1C6, 0x98E2,
+	0xD1C7, 0x9951, 0xD1C8, 0x9A0E, 0xD1C9, 0x9A0F, 0xD1CA, 0x9A65,	0xD1CB, 0x9E92, 0xD1CC, 0x7DCA, 0xD1CD, 0x4F76, 0xD1CE, 0x5409,
+	0xD1CF, 0x62EE, 0xD1D0, 0x6854, 0xD1D1, 0x91D1, 0xD1D2, 0x55AB,	0xD1D3, 0x513A, 0xD1D4, 0xF90B, 0xD1D5, 0xF90C, 0xD1D6, 0x5A1C,
+	0xD1D7, 0x61E6, 0xD1D8, 0xF90D, 0xD1D9, 0x62CF, 0xD1DA, 0x62FF,	0xD1DB, 0xF90E, 0xD1DC, 0xF90F, 0xD1DD, 0xF910, 0xD1DE, 0xF911,
+	0xD1DF, 0xF912, 0xD1E0, 0xF913, 0xD1E1, 0x90A3, 0xD1E2, 0xF914,	0xD1E3, 0xF915, 0xD1E4, 0xF916, 0xD1E5, 0xF917, 0xD1E6, 0xF918,
+	0xD1E7, 0x8AFE, 0xD1E8, 0xF919, 0xD1E9, 0xF91A, 0xD1EA, 0xF91B,	0xD1EB, 0xF91C, 0xD1EC, 0x6696, 0xD1ED, 0xF91D, 0xD1EE, 0x7156,
+	0xD1EF, 0xF91E, 0xD1F0, 0xF91F, 0xD1F1, 0x96E3, 0xD1F2, 0xF920,	0xD1F3, 0x634F, 0xD1F4, 0x637A, 0xD1F5, 0x5357, 0xD1F6, 0xF921,
+	0xD1F7, 0x678F, 0xD1F8, 0x6960, 0xD1F9, 0x6E73, 0xD1FA, 0xF922,	0xD1FB, 0x7537, 0xD1FC, 0xF923, 0xD1FD, 0xF924, 0xD1FE, 0xF925,
+	0xD2A1, 0x7D0D, 0xD2A2, 0xF926, 0xD2A3, 0xF927, 0xD2A4, 0x8872,	0xD2A5, 0x56CA, 0xD2A6, 0x5A18, 0xD2A7, 0xF928, 0xD2A8, 0xF929,
+	0xD2A9, 0xF92A, 0xD2AA, 0xF92B, 0xD2AB, 0xF92C, 0xD2AC, 0x4E43,	0xD2AD, 0xF92D, 0xD2AE, 0x5167, 0xD2AF, 0x5948, 0xD2B0, 0x67F0,
+	0xD2B1, 0x8010, 0xD2B2, 0xF92E, 0xD2B3, 0x5973, 0xD2B4, 0x5E74,	0xD2B5, 0x649A, 0xD2B6, 0x79CA, 0xD2B7, 0x5FF5, 0xD2B8, 0x606C,
+	0xD2B9, 0x62C8, 0xD2BA, 0x637B, 0xD2BB, 0x5BE7, 0xD2BC, 0x5BD7,	0xD2BD, 0x52AA, 0xD2BE, 0xF92F, 0xD2BF, 0x5974, 0xD2C0, 0x5F29,
+	0xD2C1, 0x6012, 0xD2C2, 0xF930, 0xD2C3, 0xF931, 0xD2C4, 0xF932,	0xD2C5, 0x7459, 0xD2C6, 0xF933, 0xD2C7, 0xF934, 0xD2C8, 0xF935,
+	0xD2C9, 0xF936, 0xD2CA, 0xF937, 0xD2CB, 0xF938, 0xD2CC, 0x99D1,	0xD2CD, 0xF939, 0xD2CE, 0xF93A, 0xD2CF, 0xF93B, 0xD2D0, 0xF93C,
+	0xD2D1, 0xF93D, 0xD2D2, 0xF93E, 0xD2D3, 0xF93F, 0xD2D4, 0xF940,	0xD2D5, 0xF941, 0xD2D6, 0xF942, 0xD2D7, 0xF943, 0xD2D8, 0x6FC3,
+	0xD2D9, 0xF944, 0xD2DA, 0xF945, 0xD2DB, 0x81BF, 0xD2DC, 0x8FB2,	0xD2DD, 0x60F1, 0xD2DE, 0xF946, 0xD2DF, 0xF947, 0xD2E0, 0x8166,
+	0xD2E1, 0xF948, 0xD2E2, 0xF949, 0xD2E3, 0x5C3F, 0xD2E4, 0xF94A,	0xD2E5, 0xF94B, 0xD2E6, 0xF94C, 0xD2E7, 0xF94D, 0xD2E8, 0xF94E,
+	0xD2E9, 0xF94F, 0xD2EA, 0xF950, 0xD2EB, 0xF951, 0xD2EC, 0x5AE9,	0xD2ED, 0x8A25, 0xD2EE, 0x677B, 0xD2EF, 0x7D10, 0xD2F0, 0xF952,
+	0xD2F1, 0xF953, 0xD2F2, 0xF954, 0xD2F3, 0xF955, 0xD2F4, 0xF956,	0xD2F5, 0xF957, 0xD2F6, 0x80FD, 0xD2F7, 0xF958, 0xD2F8, 0xF959,
+	0xD2F9, 0x5C3C, 0xD2FA, 0x6CE5, 0xD2FB, 0x533F, 0xD2FC, 0x6EBA,	0xD2FD, 0x591A, 0xD2FE, 0x8336, 0xD3A1, 0x4E39, 0xD3A2, 0x4EB6,
+	0xD3A3, 0x4F46, 0xD3A4, 0x55AE, 0xD3A5, 0x5718, 0xD3A6, 0x58C7,	0xD3A7, 0x5F56, 0xD3A8, 0x65B7, 0xD3A9, 0x65E6, 0xD3AA, 0x6A80,
+	0xD3AB, 0x6BB5, 0xD3AC, 0x6E4D, 0xD3AD, 0x77ED, 0xD3AE, 0x7AEF,	0xD3AF, 0x7C1E, 0xD3B0, 0x7DDE, 0xD3B1, 0x86CB, 0xD3B2, 0x8892,
+	0xD3B3, 0x9132, 0xD3B4, 0x935B, 0xD3B5, 0x64BB, 0xD3B6, 0x6FBE,	0xD3B7, 0x737A, 0xD3B8, 0x75B8, 0xD3B9, 0x9054, 0xD3BA, 0x5556,
+	0xD3BB, 0x574D, 0xD3BC, 0x61BA, 0xD3BD, 0x64D4, 0xD3BE, 0x66C7,	0xD3BF, 0x6DE1, 0xD3C0, 0x6E5B, 0xD3C1, 0x6F6D, 0xD3C2, 0x6FB9,
+	0xD3C3, 0x75F0, 0xD3C4, 0x8043, 0xD3C5, 0x81BD, 0xD3C6, 0x8541,	0xD3C7, 0x8983, 0xD3C8, 0x8AC7, 0xD3C9, 0x8B5A, 0xD3CA, 0x931F,
+	0xD3CB, 0x6C93, 0xD3CC, 0x7553, 0xD3CD, 0x7B54, 0xD3CE, 0x8E0F,	0xD3CF, 0x905D, 0xD3D0, 0x5510, 0xD3D1, 0x5802, 0xD3D2, 0x5858,
+	0xD3D3, 0x5E62, 0xD3D4, 0x6207, 0xD3D5, 0x649E, 0xD3D6, 0x68E0,	0xD3D7, 0x7576, 0xD3D8, 0x7CD6, 0xD3D9, 0x87B3, 0xD3DA, 0x9EE8,
+	0xD3DB, 0x4EE3, 0xD3DC, 0x5788, 0xD3DD, 0x576E, 0xD3DE, 0x5927,	0xD3DF, 0x5C0D, 0xD3E0, 0x5CB1, 0xD3E1, 0x5E36, 0xD3E2, 0x5F85,
+	0xD3E3, 0x6234, 0xD3E4, 0x64E1, 0xD3E5, 0x73B3, 0xD3E6, 0x81FA,	0xD3E7, 0x888B, 0xD3E8, 0x8CB8, 0xD3E9, 0x968A, 0xD3EA, 0x9EDB,
+	0xD3EB, 0x5B85, 0xD3EC, 0x5FB7, 0xD3ED, 0x60B3, 0xD3EE, 0x5012,	0xD3EF, 0x5200, 0xD3F0, 0x5230, 0xD3F1, 0x5716, 0xD3F2, 0x5835,
+	0xD3F3, 0x5857, 0xD3F4, 0x5C0E, 0xD3F5, 0x5C60, 0xD3F6, 0x5CF6,	0xD3F7, 0x5D8B, 0xD3F8, 0x5EA6, 0xD3F9, 0x5F92, 0xD3FA, 0x60BC,
+	0xD3FB, 0x6311, 0xD3FC, 0x6389, 0xD3FD, 0x6417, 0xD3FE, 0x6843,	0xD4A1, 0x68F9, 0xD4A2, 0x6AC2, 0xD4A3, 0x6DD8, 0xD4A4, 0x6E21,
+	0xD4A5, 0x6ED4, 0xD4A6, 0x6FE4, 0xD4A7, 0x71FE, 0xD4A8, 0x76DC,	0xD4A9, 0x7779, 0xD4AA, 0x79B1, 0xD4AB, 0x7A3B, 0xD4AC, 0x8404,
+	0xD4AD, 0x89A9, 0xD4AE, 0x8CED, 0xD4AF, 0x8DF3, 0xD4B0, 0x8E48,	0xD4B1, 0x9003, 0xD4B2, 0x9014, 0xD4B3, 0x9053, 0xD4B4, 0x90FD,
+	0xD4B5, 0x934D, 0xD4B6, 0x9676, 0xD4B7, 0x97DC, 0xD4B8, 0x6BD2,	0xD4B9, 0x7006, 0xD4BA, 0x7258, 0xD4BB, 0x72A2, 0xD4BC, 0x7368,
+	0xD4BD, 0x7763, 0xD4BE, 0x79BF, 0xD4BF, 0x7BE4, 0xD4C0, 0x7E9B,	0xD4C1, 0x8B80, 0xD4C2, 0x58A9, 0xD4C3, 0x60C7, 0xD4C4, 0x6566,
+	0xD4C5, 0x65FD, 0xD4C6, 0x66BE, 0xD4C7, 0x6C8C, 0xD4C8, 0x711E,	0xD4C9, 0x71C9, 0xD4CA, 0x8C5A, 0xD4CB, 0x9813, 0xD4CC, 0x4E6D,
+	0xD4CD, 0x7A81, 0xD4CE, 0x4EDD, 0xD4CF, 0x51AC, 0xD4D0, 0x51CD,	0xD4D1, 0x52D5, 0xD4D2, 0x540C, 0xD4D3, 0x61A7, 0xD4D4, 0x6771,
+	0xD4D5, 0x6850, 0xD4D6, 0x68DF, 0xD4D7, 0x6D1E, 0xD4D8, 0x6F7C,	0xD4D9, 0x75BC, 0xD4DA, 0x77B3, 0xD4DB, 0x7AE5, 0xD4DC, 0x80F4,
+	0xD4DD, 0x8463, 0xD4DE, 0x9285, 0xD4DF, 0x515C, 0xD4E0, 0x6597,	0xD4E1, 0x675C, 0xD4E2, 0x6793, 0xD4E3, 0x75D8, 0xD4E4, 0x7AC7,
+	0xD4E5, 0x8373, 0xD4E6, 0xF95A, 0xD4E7, 0x8C46, 0xD4E8, 0x9017,	0xD4E9, 0x982D, 0xD4EA, 0x5C6F, 0xD4EB, 0x81C0, 0xD4EC, 0x829A,
+	0xD4ED, 0x9041, 0xD4EE, 0x906F, 0xD4EF, 0x920D, 0xD4F0, 0x5F97,	0xD4F1, 0x5D9D, 0xD4F2, 0x6A59, 0xD4F3, 0x71C8, 0xD4F4, 0x767B,
+	0xD4F5, 0x7B49, 0xD4F6, 0x85E4, 0xD4F7, 0x8B04, 0xD4F8, 0x9127,	0xD4F9, 0x9A30, 0xD4FA, 0x5587, 0xD4FB, 0x61F6, 0xD4FC, 0xF95B,
+	0xD4FD, 0x7669, 0xD4FE, 0x7F85, 0xD5A1, 0x863F, 0xD5A2, 0x87BA,	0xD5A3, 0x88F8, 0xD5A4, 0x908F, 0xD5A5, 0xF95C, 0xD5A6, 0x6D1B,
+	0xD5A7, 0x70D9, 0xD5A8, 0x73DE, 0xD5A9, 0x7D61, 0xD5AA, 0x843D,	0xD5AB, 0xF95D, 0xD5AC, 0x916A, 0xD5AD, 0x99F1, 0xD5AE, 0xF95E,
+	0xD5AF, 0x4E82, 0xD5B0, 0x5375, 0xD5B1, 0x6B04, 0xD5B2, 0x6B12,	0xD5B3, 0x703E, 0xD5B4, 0x721B, 0xD5B5, 0x862D, 0xD5B6, 0x9E1E,
+	0xD5B7, 0x524C, 0xD5B8, 0x8FA3, 0xD5B9, 0x5D50, 0xD5BA, 0x64E5,	0xD5BB, 0x652C, 0xD5BC, 0x6B16, 0xD5BD, 0x6FEB, 0xD5BE, 0x7C43,
+	0xD5BF, 0x7E9C, 0xD5C0, 0x85CD, 0xD5C1, 0x8964, 0xD5C2, 0x89BD,	0xD5C3, 0x62C9, 0xD5C4, 0x81D8, 0xD5C5, 0x881F, 0xD5C6, 0x5ECA,
+	0xD5C7, 0x6717, 0xD5C8, 0x6D6A, 0xD5C9, 0x72FC, 0xD5CA, 0x7405,	0xD5CB, 0x746F, 0xD5CC, 0x8782, 0xD5CD, 0x90DE, 0xD5CE, 0x4F86,
+	0xD5CF, 0x5D0D, 0xD5D0, 0x5FA0, 0xD5D1, 0x840A, 0xD5D2, 0x51B7,	0xD5D3, 0x63A0, 0xD5D4, 0x7565, 0xD5D5, 0x4EAE, 0xD5D6, 0x5006,
+	0xD5D7, 0x5169, 0xD5D8, 0x51C9, 0xD5D9, 0x6881, 0xD5DA, 0x6A11,	0xD5DB, 0x7CAE, 0xD5DC, 0x7CB1, 0xD5DD, 0x7CE7, 0xD5DE, 0x826F,
+	0xD5DF, 0x8AD2, 0xD5E0, 0x8F1B, 0xD5E1, 0x91CF, 0xD5E2, 0x4FB6,	0xD5E3, 0x5137, 0xD5E4, 0x52F5, 0xD5E5, 0x5442, 0xD5E6, 0x5EEC,
+	0xD5E7, 0x616E, 0xD5E8, 0x623E, 0xD5E9, 0x65C5, 0xD5EA, 0x6ADA,	0xD5EB, 0x6FFE, 0xD5EC, 0x792A, 0xD5ED, 0x85DC, 0xD5EE, 0x8823,
+	0xD5EF, 0x95AD, 0xD5F0, 0x9A62, 0xD5F1, 0x9A6A, 0xD5F2, 0x9E97,	0xD5F3, 0x9ECE, 0xD5F4, 0x529B, 0xD5F5, 0x66C6, 0xD5F6, 0x6B77,
+	0xD5F7, 0x701D, 0xD5F8, 0x792B, 0xD5F9, 0x8F62, 0xD5FA, 0x9742,	0xD5FB, 0x6190, 0xD5FC, 0x6200, 0xD5FD, 0x6523, 0xD5FE, 0x6F23,
+	0xD6A1, 0x7149, 0xD6A2, 0x7489, 0xD6A3, 0x7DF4, 0xD6A4, 0x806F,	0xD6A5, 0x84EE, 0xD6A6, 0x8F26, 0xD6A7, 0x9023, 0xD6A8, 0x934A,
+	0xD6A9, 0x51BD, 0xD6AA, 0x5217, 0xD6AB, 0x52A3, 0xD6AC, 0x6D0C,	0xD6AD, 0x70C8, 0xD6AE, 0x88C2, 0xD6AF, 0x5EC9, 0xD6B0, 0x6582,
+	0xD6B1, 0x6BAE, 0xD6B2, 0x6FC2, 0xD6B3, 0x7C3E, 0xD6B4, 0x7375,	0xD6B5, 0x4EE4, 0xD6B6, 0x4F36, 0xD6B7, 0x56F9, 0xD6B8, 0xF95F,
+	0xD6B9, 0x5CBA, 0xD6BA, 0x5DBA, 0xD6BB, 0x601C, 0xD6BC, 0x73B2,	0xD6BD, 0x7B2D, 0xD6BE, 0x7F9A, 0xD6BF, 0x7FCE, 0xD6C0, 0x8046,
+	0xD6C1, 0x901E, 0xD6C2, 0x9234, 0xD6C3, 0x96F6, 0xD6C4, 0x9748,	0xD6C5, 0x9818, 0xD6C6, 0x9F61, 0xD6C7, 0x4F8B, 0xD6C8, 0x6FA7,
+	0xD6C9, 0x79AE, 0xD6CA, 0x91B4, 0xD6CB, 0x96B7, 0xD6CC, 0x52DE,	0xD6CD, 0xF960, 0xD6CE, 0x6488, 0xD6CF, 0x64C4, 0xD6D0, 0x6AD3,
+	0xD6D1, 0x6F5E, 0xD6D2, 0x7018, 0xD6D3, 0x7210, 0xD6D4, 0x76E7,	0xD6D5, 0x8001, 0xD6D6, 0x8606, 0xD6D7, 0x865C, 0xD6D8, 0x8DEF,
+	0xD6D9, 0x8F05, 0xD6DA, 0x9732, 0xD6DB, 0x9B6F, 0xD6DC, 0x9DFA,	0xD6DD, 0x9E75, 0xD6DE, 0x788C, 0xD6DF, 0x797F, 0xD6E0, 0x7DA0,
+	0xD6E1, 0x83C9, 0xD6E2, 0x9304, 0xD6E3, 0x9E7F, 0xD6E4, 0x9E93,	0xD6E5, 0x8AD6, 0xD6E6, 0x58DF, 0xD6E7, 0x5F04, 0xD6E8, 0x6727,
+	0xD6E9, 0x7027, 0xD6EA, 0x74CF, 0xD6EB, 0x7C60, 0xD6EC, 0x807E,	0xD6ED, 0x5121, 0xD6EE, 0x7028, 0xD6EF, 0x7262, 0xD6F0, 0x78CA,
+	0xD6F1, 0x8CC2, 0xD6F2, 0x8CDA, 0xD6F3, 0x8CF4, 0xD6F4, 0x96F7,	0xD6F5, 0x4E86, 0xD6F6, 0x50DA, 0xD6F7, 0x5BEE, 0xD6F8, 0x5ED6,
+	0xD6F9, 0x6599, 0xD6FA, 0x71CE, 0xD6FB, 0x7642, 0xD6FC, 0x77AD,	0xD6FD, 0x804A, 0xD6FE, 0x84FC, 0xD7A1, 0x907C, 0xD7A2, 0x9B27,
+	0xD7A3, 0x9F8D, 0xD7A4, 0x58D8, 0xD7A5, 0x5A41, 0xD7A6, 0x5C62,	0xD7A7, 0x6A13, 0xD7A8, 0x6DDA, 0xD7A9, 0x6F0F, 0xD7AA, 0x763B,
+	0xD7AB, 0x7D2F, 0xD7AC, 0x7E37, 0xD7AD, 0x851E, 0xD7AE, 0x8938,	0xD7AF, 0x93E4, 0xD7B0, 0x964B, 0xD7B1, 0x5289, 0xD7B2, 0x65D2,
+	0xD7B3, 0x67F3, 0xD7B4, 0x69B4, 0xD7B5, 0x6D41, 0xD7B6, 0x6E9C,	0xD7B7, 0x700F, 0xD7B8, 0x7409, 0xD7B9, 0x7460, 0xD7BA, 0x7559,
+	0xD7BB, 0x7624, 0xD7BC, 0x786B, 0xD7BD, 0x8B2C, 0xD7BE, 0x985E,	0xD7BF, 0x516D, 0xD7C0, 0x622E, 0xD7C1, 0x9678, 0xD7C2, 0x4F96,
+	0xD7C3, 0x502B, 0xD7C4, 0x5D19, 0xD7C5, 0x6DEA, 0xD7C6, 0x7DB8,	0xD7C7, 0x8F2A, 0xD7C8, 0x5F8B, 0xD7C9, 0x6144, 0xD7CA, 0x6817,
+	0xD7CB, 0xF961, 0xD7CC, 0x9686, 0xD7CD, 0x52D2, 0xD7CE, 0x808B,	0xD7CF, 0x51DC, 0xD7D0, 0x51CC, 0xD7D1, 0x695E, 0xD7D2, 0x7A1C,
+	0xD7D3, 0x7DBE, 0xD7D4, 0x83F1, 0xD7D5, 0x9675, 0xD7D6, 0x4FDA,	0xD7D7, 0x5229, 0xD7D8, 0x5398, 0xD7D9, 0x540F, 0xD7DA, 0x550E,
+	0xD7DB, 0x5C65, 0xD7DC, 0x60A7, 0xD7DD, 0x674E, 0xD7DE, 0x68A8,	0xD7DF, 0x6D6C, 0xD7E0, 0x7281, 0xD7E1, 0x72F8, 0xD7E2, 0x7406,
+	0xD7E3, 0x7483, 0xD7E4, 0xF962, 0xD7E5, 0x75E2, 0xD7E6, 0x7C6C,	0xD7E7, 0x7F79, 0xD7E8, 0x7FB8, 0xD7E9, 0x8389, 0xD7EA, 0x88CF,
+	0xD7EB, 0x88E1, 0xD7EC, 0x91CC, 0xD7ED, 0x91D0, 0xD7EE, 0x96E2,	0xD7EF, 0x9BC9, 0xD7F0, 0x541D, 0xD7F1, 0x6F7E, 0xD7F2, 0x71D0,
+	0xD7F3, 0x7498, 0xD7F4, 0x85FA, 0xD7F5, 0x8EAA, 0xD7F6, 0x96A3,	0xD7F7, 0x9C57, 0xD7F8, 0x9E9F, 0xD7F9, 0x6797, 0xD7FA, 0x6DCB,
+	0xD7FB, 0x7433, 0xD7FC, 0x81E8, 0xD7FD, 0x9716, 0xD7FE, 0x782C,	0xD8A1, 0x7ACB, 0xD8A2, 0x7B20, 0xD8A3, 0x7C92, 0xD8A4, 0x6469,
+	0xD8A5, 0x746A, 0xD8A6, 0x75F2, 0xD8A7, 0x78BC, 0xD8A8, 0x78E8,	0xD8A9, 0x99AC, 0xD8AA, 0x9B54, 0xD8AB, 0x9EBB, 0xD8AC, 0x5BDE,
+	0xD8AD, 0x5E55, 0xD8AE, 0x6F20, 0xD8AF, 0x819C, 0xD8B0, 0x83AB,	0xD8B1, 0x9088, 0xD8B2, 0x4E07, 0xD8B3, 0x534D, 0xD8B4, 0x5A29,
+	0xD8B5, 0x5DD2, 0xD8B6, 0x5F4E, 0xD8B7, 0x6162, 0xD8B8, 0x633D,	0xD8B9, 0x6669, 0xD8BA, 0x66FC, 0xD8BB, 0x6EFF, 0xD8BC, 0x6F2B,
+	0xD8BD, 0x7063, 0xD8BE, 0x779E, 0xD8BF, 0x842C, 0xD8C0, 0x8513,	0xD8C1, 0x883B, 0xD8C2, 0x8F13, 0xD8C3, 0x9945, 0xD8C4, 0x9C3B,
+	0xD8C5, 0x551C, 0xD8C6, 0x62B9, 0xD8C7, 0x672B, 0xD8C8, 0x6CAB,	0xD8C9, 0x8309, 0xD8CA, 0x896A, 0xD8CB, 0x977A, 0xD8CC, 0x4EA1,
+	0xD8CD, 0x5984, 0xD8CE, 0x5FD8, 0xD8CF, 0x5FD9, 0xD8D0, 0x671B,	0xD8D1, 0x7DB2, 0xD8D2, 0x7F54, 0xD8D3, 0x8292, 0xD8D4, 0x832B,
+	0xD8D5, 0x83BD, 0xD8D6, 0x8F1E, 0xD8D7, 0x9099, 0xD8D8, 0x57CB,	0xD8D9, 0x59B9, 0xD8DA, 0x5A92, 0xD8DB, 0x5BD0, 0xD8DC, 0x6627,
+	0xD8DD, 0x679A, 0xD8DE, 0x6885, 0xD8DF, 0x6BCF, 0xD8E0, 0x7164,	0xD8E1, 0x7F75, 0xD8E2, 0x8CB7, 0xD8E3, 0x8CE3, 0xD8E4, 0x9081,
+	0xD8E5, 0x9B45, 0xD8E6, 0x8108, 0xD8E7, 0x8C8A, 0xD8E8, 0x964C,	0xD8E9, 0x9A40, 0xD8EA, 0x9EA5, 0xD8EB, 0x5B5F, 0xD8EC, 0x6C13,
+	0xD8ED, 0x731B, 0xD8EE, 0x76F2, 0xD8EF, 0x76DF, 0xD8F0, 0x840C,	0xD8F1, 0x51AA, 0xD8F2, 0x8993, 0xD8F3, 0x514D, 0xD8F4, 0x5195,
+	0xD8F5, 0x52C9, 0xD8F6, 0x68C9, 0xD8F7, 0x6C94, 0xD8F8, 0x7704,	0xD8F9, 0x7720, 0xD8FA, 0x7DBF, 0xD8FB, 0x7DEC, 0xD8FC, 0x9762,
+	0xD8FD, 0x9EB5, 0xD8FE, 0x6EC5, 0xD9A1, 0x8511, 0xD9A2, 0x51A5,	0xD9A3, 0x540D, 0xD9A4, 0x547D, 0xD9A5, 0x660E, 0xD9A6, 0x669D,
+	0xD9A7, 0x6927, 0xD9A8, 0x6E9F, 0xD9A9, 0x76BF, 0xD9AA, 0x7791,	0xD9AB, 0x8317, 0xD9AC, 0x84C2, 0xD9AD, 0x879F, 0xD9AE, 0x9169,
+	0xD9AF, 0x9298, 0xD9B0, 0x9CF4, 0xD9B1, 0x8882, 0xD9B2, 0x4FAE,	0xD9B3, 0x5192, 0xD9B4, 0x52DF, 0xD9B5, 0x59C6, 0xD9B6, 0x5E3D,
+	0xD9B7, 0x6155, 0xD9B8, 0x6478, 0xD9B9, 0x6479, 0xD9BA, 0x66AE,	0xD9BB, 0x67D0, 0xD9BC, 0x6A21, 0xD9BD, 0x6BCD, 0xD9BE, 0x6BDB,
+	0xD9BF, 0x725F, 0xD9C0, 0x7261, 0xD9C1, 0x7441, 0xD9C2, 0x7738,	0xD9C3, 0x77DB, 0xD9C4, 0x8017, 0xD9C5, 0x82BC, 0xD9C6, 0x8305,
+	0xD9C7, 0x8B00, 0xD9C8, 0x8B28, 0xD9C9, 0x8C8C, 0xD9CA, 0x6728,	0xD9CB, 0x6C90, 0xD9CC, 0x7267, 0xD9CD, 0x76EE, 0xD9CE, 0x7766,
+	0xD9CF, 0x7A46, 0xD9D0, 0x9DA9, 0xD9D1, 0x6B7F, 0xD9D2, 0x6C92,	0xD9D3, 0x5922, 0xD9D4, 0x6726, 0xD9D5, 0x8499, 0xD9D6, 0x536F,
+	0xD9D7, 0x5893, 0xD9D8, 0x5999, 0xD9D9, 0x5EDF, 0xD9DA, 0x63CF,	0xD9DB, 0x6634, 0xD9DC, 0x6773, 0xD9DD, 0x6E3A, 0xD9DE, 0x732B,
+	0xD9DF, 0x7AD7, 0xD9E0, 0x82D7, 0xD9E1, 0x9328, 0xD9E2, 0x52D9,	0xD9E3, 0x5DEB, 0xD9E4, 0x61AE, 0xD9E5, 0x61CB, 0xD9E6, 0x620A,
+	0xD9E7, 0x62C7, 0xD9E8, 0x64AB, 0xD9E9, 0x65E0, 0xD9EA, 0x6959,	0xD9EB, 0x6B66, 0xD9EC, 0x6BCB, 0xD9ED, 0x7121, 0xD9EE, 0x73F7,
+	0xD9EF, 0x755D, 0xD9F0, 0x7E46, 0xD9F1, 0x821E, 0xD9F2, 0x8302,	0xD9F3, 0x856A, 0xD9F4, 0x8AA3, 0xD9F5, 0x8CBF, 0xD9F6, 0x9727,
+	0xD9F7, 0x9D61, 0xD9F8, 0x58A8, 0xD9F9, 0x9ED8, 0xD9FA, 0x5011,	0xD9FB, 0x520E, 0xD9FC, 0x543B, 0xD9FD, 0x554F, 0xD9FE, 0x6587,
+	0xDAA1, 0x6C76, 0xDAA2, 0x7D0A, 0xDAA3, 0x7D0B, 0xDAA4, 0x805E,	0xDAA5, 0x868A, 0xDAA6, 0x9580, 0xDAA7, 0x96EF, 0xDAA8, 0x52FF,
+	0xDAA9, 0x6C95, 0xDAAA, 0x7269, 0xDAAB, 0x5473, 0xDAAC, 0x5A9A,	0xDAAD, 0x5C3E, 0xDAAE, 0x5D4B, 0xDAAF, 0x5F4C, 0xDAB0, 0x5FAE,
+	0xDAB1, 0x672A, 0xDAB2, 0x68B6, 0xDAB3, 0x6963, 0xDAB4, 0x6E3C,	0xDAB5, 0x6E44, 0xDAB6, 0x7709, 0xDAB7, 0x7C73, 0xDAB8, 0x7F8E,
+	0xDAB9, 0x8587, 0xDABA, 0x8B0E, 0xDABB, 0x8FF7, 0xDABC, 0x9761,	0xDABD, 0x9EF4, 0xDABE, 0x5CB7, 0xDABF, 0x60B6, 0xDAC0, 0x610D,
+	0xDAC1, 0x61AB, 0xDAC2, 0x654F, 0xDAC3, 0x65FB, 0xDAC4, 0x65FC,	0xDAC5, 0x6C11, 0xDAC6, 0x6CEF, 0xDAC7, 0x739F, 0xDAC8, 0x73C9,
+	0xDAC9, 0x7DE1, 0xDACA, 0x9594, 0xDACB, 0x5BC6, 0xDACC, 0x871C,	0xDACD, 0x8B10, 0xDACE, 0x525D, 0xDACF, 0x535A, 0xDAD0, 0x62CD,
+	0xDAD1, 0x640F, 0xDAD2, 0x64B2, 0xDAD3, 0x6734, 0xDAD4, 0x6A38,	0xDAD5, 0x6CCA, 0xDAD6, 0x73C0, 0xDAD7, 0x749E, 0xDAD8, 0x7B94,
+	0xDAD9, 0x7C95, 0xDADA, 0x7E1B, 0xDADB, 0x818A, 0xDADC, 0x8236,	0xDADD, 0x8584, 0xDADE, 0x8FEB, 0xDADF, 0x96F9, 0xDAE0, 0x99C1,
+	0xDAE1, 0x4F34, 0xDAE2, 0x534A, 0xDAE3, 0x53CD, 0xDAE4, 0x53DB,	0xDAE5, 0x62CC, 0xDAE6, 0x642C, 0xDAE7, 0x6500, 0xDAE8, 0x6591,
+	0xDAE9, 0x69C3, 0xDAEA, 0x6CEE, 0xDAEB, 0x6F58, 0xDAEC, 0x73ED,	0xDAED, 0x7554, 0xDAEE, 0x7622, 0xDAEF, 0x76E4, 0xDAF0, 0x76FC,
+	0xDAF1, 0x78D0, 0xDAF2, 0x78FB, 0xDAF3, 0x792C, 0xDAF4, 0x7D46,	0xDAF5, 0x822C, 0xDAF6, 0x87E0, 0xDAF7, 0x8FD4, 0xDAF8, 0x9812,
+	0xDAF9, 0x98EF, 0xDAFA, 0x52C3, 0xDAFB, 0x62D4, 0xDAFC, 0x64A5,	0xDAFD, 0x6E24, 0xDAFE, 0x6F51, 0xDBA1, 0x767C, 0xDBA2, 0x8DCB,
+	0xDBA3, 0x91B1, 0xDBA4, 0x9262, 0xDBA5, 0x9AEE, 0xDBA6, 0x9B43,	0xDBA7, 0x5023, 0xDBA8, 0x508D, 0xDBA9, 0x574A, 0xDBAA, 0x59A8,
+	0xDBAB, 0x5C28, 0xDBAC, 0x5E47, 0xDBAD, 0x5F77, 0xDBAE, 0x623F,	0xDBAF, 0x653E, 0xDBB0, 0x65B9, 0xDBB1, 0x65C1, 0xDBB2, 0x6609,
+	0xDBB3, 0x678B, 0xDBB4, 0x699C, 0xDBB5, 0x6EC2, 0xDBB6, 0x78C5,	0xDBB7, 0x7D21, 0xDBB8, 0x80AA, 0xDBB9, 0x8180, 0xDBBA, 0x822B,
+	0xDBBB, 0x82B3, 0xDBBC, 0x84A1, 0xDBBD, 0x868C, 0xDBBE, 0x8A2A,	0xDBBF, 0x8B17, 0xDBC0, 0x90A6, 0xDBC1, 0x9632, 0xDBC2, 0x9F90,
+	0xDBC3, 0x500D, 0xDBC4, 0x4FF3, 0xDBC5, 0xF963, 0xDBC6, 0x57F9,	0xDBC7, 0x5F98, 0xDBC8, 0x62DC, 0xDBC9, 0x6392, 0xDBCA, 0x676F,
+	0xDBCB, 0x6E43, 0xDBCC, 0x7119, 0xDBCD, 0x76C3, 0xDBCE, 0x80CC,	0xDBCF, 0x80DA, 0xDBD0, 0x88F4, 0xDBD1, 0x88F5, 0xDBD2, 0x8919,
+	0xDBD3, 0x8CE0, 0xDBD4, 0x8F29, 0xDBD5, 0x914D, 0xDBD6, 0x966A,	0xDBD7, 0x4F2F, 0xDBD8, 0x4F70, 0xDBD9, 0x5E1B, 0xDBDA, 0x67CF,
+	0xDBDB, 0x6822, 0xDBDC, 0x767D, 0xDBDD, 0x767E, 0xDBDE, 0x9B44,	0xDBDF, 0x5E61, 0xDBE0, 0x6A0A, 0xDBE1, 0x7169, 0xDBE2, 0x71D4,
+	0xDBE3, 0x756A, 0xDBE4, 0xF964, 0xDBE5, 0x7E41, 0xDBE6, 0x8543,	0xDBE7, 0x85E9, 0xDBE8, 0x98DC, 0xDBE9, 0x4F10, 0xDBEA, 0x7B4F,
+	0xDBEB, 0x7F70, 0xDBEC, 0x95A5, 0xDBED, 0x51E1, 0xDBEE, 0x5E06,	0xDBEF, 0x68B5, 0xDBF0, 0x6C3E, 0xDBF1, 0x6C4E, 0xDBF2, 0x6CDB,
+	0xDBF3, 0x72AF, 0xDBF4, 0x7BC4, 0xDBF5, 0x8303, 0xDBF6, 0x6CD5,	0xDBF7, 0x743A, 0xDBF8, 0x50FB, 0xDBF9, 0x5288, 0xDBFA, 0x58C1,
+	0xDBFB, 0x64D8, 0xDBFC, 0x6A97, 0xDBFD, 0x74A7, 0xDBFE, 0x7656,	0xDCA1, 0x78A7, 0xDCA2, 0x8617, 0xDCA3, 0x95E2, 0xDCA4, 0x9739,
+	0xDCA5, 0xF965, 0xDCA6, 0x535E, 0xDCA7, 0x5F01, 0xDCA8, 0x8B8A,	0xDCA9, 0x8FA8, 0xDCAA, 0x8FAF, 0xDCAB, 0x908A, 0xDCAC, 0x5225,
+	0xDCAD, 0x77A5, 0xDCAE, 0x9C49, 0xDCAF, 0x9F08, 0xDCB0, 0x4E19,	0xDCB1, 0x5002, 0xDCB2, 0x5175, 0xDCB3, 0x5C5B, 0xDCB4, 0x5E77,
+	0xDCB5, 0x661E, 0xDCB6, 0x663A, 0xDCB7, 0x67C4, 0xDCB8, 0x68C5,	0xDCB9, 0x70B3, 0xDCBA, 0x7501, 0xDCBB, 0x75C5, 0xDCBC, 0x79C9,
+	0xDCBD, 0x7ADD, 0xDCBE, 0x8F27, 0xDCBF, 0x9920, 0xDCC0, 0x9A08,	0xDCC1, 0x4FDD, 0xDCC2, 0x5821, 0xDCC3, 0x5831, 0xDCC4, 0x5BF6,
+	0xDCC5, 0x666E, 0xDCC6, 0x6B65, 0xDCC7, 0x6D11, 0xDCC8, 0x6E7A,	0xDCC9, 0x6F7D, 0xDCCA, 0x73E4, 0xDCCB, 0x752B, 0xDCCC, 0x83E9,
+	0xDCCD, 0x88DC, 0xDCCE, 0x8913, 0xDCCF, 0x8B5C, 0xDCD0, 0x8F14,	0xDCD1, 0x4F0F, 0xDCD2, 0x50D5, 0xDCD3, 0x5310, 0xDCD4, 0x535C,
+	0xDCD5, 0x5B93, 0xDCD6, 0x5FA9, 0xDCD7, 0x670D, 0xDCD8, 0x798F,	0xDCD9, 0x8179, 0xDCDA, 0x832F, 0xDCDB, 0x8514, 0xDCDC, 0x8907,
+	0xDCDD, 0x8986, 0xDCDE, 0x8F39, 0xDCDF, 0x8F3B, 0xDCE0, 0x99A5,	0xDCE1, 0x9C12, 0xDCE2, 0x672C, 0xDCE3, 0x4E76, 0xDCE4, 0x4FF8,
+	0xDCE5, 0x5949, 0xDCE6, 0x5C01, 0xDCE7, 0x5CEF, 0xDCE8, 0x5CF0,	0xDCE9, 0x6367, 0xDCEA, 0x68D2, 0xDCEB, 0x70FD, 0xDCEC, 0x71A2,
+	0xDCED, 0x742B, 0xDCEE, 0x7E2B, 0xDCEF, 0x84EC, 0xDCF0, 0x8702,	0xDCF1, 0x9022, 0xDCF2, 0x92D2, 0xDCF3, 0x9CF3, 0xDCF4, 0x4E0D,
+	0xDCF5, 0x4ED8, 0xDCF6, 0x4FEF, 0xDCF7, 0x5085, 0xDCF8, 0x5256,	0xDCF9, 0x526F, 0xDCFA, 0x5426, 0xDCFB, 0x5490, 0xDCFC, 0x57E0,
+	0xDCFD, 0x592B, 0xDCFE, 0x5A66, 0xDDA1, 0x5B5A, 0xDDA2, 0x5B75,	0xDDA3, 0x5BCC, 0xDDA4, 0x5E9C, 0xDDA5, 0xF966, 0xDDA6, 0x6276,
+	0xDDA7, 0x6577, 0xDDA8, 0x65A7, 0xDDA9, 0x6D6E, 0xDDAA, 0x6EA5,	0xDDAB, 0x7236, 0xDDAC, 0x7B26, 0xDDAD, 0x7C3F, 0xDDAE, 0x7F36,
+	0xDDAF, 0x8150, 0xDDB0, 0x8151, 0xDDB1, 0x819A, 0xDDB2, 0x8240,	0xDDB3, 0x8299, 0xDDB4, 0x83A9, 0xDDB5, 0x8A03, 0xDDB6, 0x8CA0,
+	0xDDB7, 0x8CE6, 0xDDB8, 0x8CFB, 0xDDB9, 0x8D74, 0xDDBA, 0x8DBA,	0xDDBB, 0x90E8, 0xDDBC, 0x91DC, 0xDDBD, 0x961C, 0xDDBE, 0x9644,
+	0xDDBF, 0x99D9, 0xDDC0, 0x9CE7, 0xDDC1, 0x5317, 0xDDC2, 0x5206,	0xDDC3, 0x5429, 0xDDC4, 0x5674, 0xDDC5, 0x58B3, 0xDDC6, 0x5954,
+	0xDDC7, 0x596E, 0xDDC8, 0x5FFF, 0xDDC9, 0x61A4, 0xDDCA, 0x626E,	0xDDCB, 0x6610, 0xDDCC, 0x6C7E, 0xDDCD, 0x711A, 0xDDCE, 0x76C6,
+	0xDDCF, 0x7C89, 0xDDD0, 0x7CDE, 0xDDD1, 0x7D1B, 0xDDD2, 0x82AC,	0xDDD3, 0x8CC1, 0xDDD4, 0x96F0, 0xDDD5, 0xF967, 0xDDD6, 0x4F5B,
+	0xDDD7, 0x5F17, 0xDDD8, 0x5F7F, 0xDDD9, 0x62C2, 0xDDDA, 0x5D29,	0xDDDB, 0x670B, 0xDDDC, 0x68DA, 0xDDDD, 0x787C, 0xDDDE, 0x7E43,
+	0xDDDF, 0x9D6C, 0xDDE0, 0x4E15, 0xDDE1, 0x5099, 0xDDE2, 0x5315,	0xDDE3, 0x532A, 0xDDE4, 0x5351, 0xDDE5, 0x5983, 0xDDE6, 0x5A62,
+	0xDDE7, 0x5E87, 0xDDE8, 0x60B2, 0xDDE9, 0x618A, 0xDDEA, 0x6249,	0xDDEB, 0x6279, 0xDDEC, 0x6590, 0xDDED, 0x6787, 0xDDEE, 0x69A7,
+	0xDDEF, 0x6BD4, 0xDDF0, 0x6BD6, 0xDDF1, 0x6BD7, 0xDDF2, 0x6BD8,	0xDDF3, 0x6CB8, 0xDDF4, 0xF968, 0xDDF5, 0x7435, 0xDDF6, 0x75FA,
+	0xDDF7, 0x7812, 0xDDF8, 0x7891, 0xDDF9, 0x79D5, 0xDDFA, 0x79D8,	0xDDFB, 0x7C83, 0xDDFC, 0x7DCB, 0xDDFD, 0x7FE1, 0xDDFE, 0x80A5,
+	0xDEA1, 0x813E, 0xDEA2, 0x81C2, 0xDEA3, 0x83F2, 0xDEA4, 0x871A,	0xDEA5, 0x88E8, 0xDEA6, 0x8AB9, 0xDEA7, 0x8B6C, 0xDEA8, 0x8CBB,
+	0xDEA9, 0x9119, 0xDEAA, 0x975E, 0xDEAB, 0x98DB, 0xDEAC, 0x9F3B,	0xDEAD, 0x56AC, 0xDEAE, 0x5B2A, 0xDEAF, 0x5F6C, 0xDEB0, 0x658C,
+	0xDEB1, 0x6AB3, 0xDEB2, 0x6BAF, 0xDEB3, 0x6D5C, 0xDEB4, 0x6FF1,	0xDEB5, 0x7015, 0xDEB6, 0x725D, 0xDEB7, 0x73AD, 0xDEB8, 0x8CA7,
+	0xDEB9, 0x8CD3, 0xDEBA, 0x983B, 0xDEBB, 0x6191, 0xDEBC, 0x6C37,	0xDEBD, 0x8058, 0xDEBE, 0x9A01, 0xDEBF, 0x4E4D, 0xDEC0, 0x4E8B,
+	0xDEC1, 0x4E9B, 0xDEC2, 0x4ED5, 0xDEC3, 0x4F3A, 0xDEC4, 0x4F3C,	0xDEC5, 0x4F7F, 0xDEC6, 0x4FDF, 0xDEC7, 0x50FF, 0xDEC8, 0x53F2,
+	0xDEC9, 0x53F8, 0xDECA, 0x5506, 0xDECB, 0x55E3, 0xDECC, 0x56DB,	0xDECD, 0x58EB, 0xDECE, 0x5962, 0xDECF, 0x5A11, 0xDED0, 0x5BEB,
+	0xDED1, 0x5BFA, 0xDED2, 0x5C04, 0xDED3, 0x5DF3, 0xDED4, 0x5E2B,	0xDED5, 0x5F99, 0xDED6, 0x601D, 0xDED7, 0x6368, 0xDED8, 0x659C,
+	0xDED9, 0x65AF, 0xDEDA, 0x67F6, 0xDEDB, 0x67FB, 0xDEDC, 0x68AD,	0xDEDD, 0x6B7B, 0xDEDE, 0x6C99, 0xDEDF, 0x6CD7, 0xDEE0, 0x6E23,
+	0xDEE1, 0x7009, 0xDEE2, 0x7345, 0xDEE3, 0x7802, 0xDEE4, 0x793E,	0xDEE5, 0x7940, 0xDEE6, 0x7960, 0xDEE7, 0x79C1, 0xDEE8, 0x7BE9,
+	0xDEE9, 0x7D17, 0xDEEA, 0x7D72, 0xDEEB, 0x8086, 0xDEEC, 0x820D,	0xDEED, 0x838E, 0xDEEE, 0x84D1, 0xDEEF, 0x86C7, 0xDEF0, 0x88DF,
+	0xDEF1, 0x8A50, 0xDEF2, 0x8A5E, 0xDEF3, 0x8B1D, 0xDEF4, 0x8CDC,	0xDEF5, 0x8D66, 0xDEF6, 0x8FAD, 0xDEF7, 0x90AA, 0xDEF8, 0x98FC,
+	0xDEF9, 0x99DF, 0xDEFA, 0x9E9D, 0xDEFB, 0x524A, 0xDEFC, 0xF969,	0xDEFD, 0x6714, 0xDEFE, 0xF96A, 0xDFA1, 0x5098, 0xDFA2, 0x522A,
+	0xDFA3, 0x5C71, 0xDFA4, 0x6563, 0xDFA5, 0x6C55, 0xDFA6, 0x73CA,	0xDFA7, 0x7523, 0xDFA8, 0x759D, 0xDFA9, 0x7B97, 0xDFAA, 0x849C,
+	0xDFAB, 0x9178, 0xDFAC, 0x9730, 0xDFAD, 0x4E77, 0xDFAE, 0x6492,	0xDFAF, 0x6BBA, 0xDFB0, 0x715E, 0xDFB1, 0x85A9, 0xDFB2, 0x4E09,
+	0xDFB3, 0xF96B, 0xDFB4, 0x6749, 0xDFB5, 0x68EE, 0xDFB6, 0x6E17,	0xDFB7, 0x829F, 0xDFB8, 0x8518, 0xDFB9, 0x886B, 0xDFBA, 0x63F7,
+	0xDFBB, 0x6F81, 0xDFBC, 0x9212, 0xDFBD, 0x98AF, 0xDFBE, 0x4E0A,	0xDFBF, 0x50B7, 0xDFC0, 0x50CF, 0xDFC1, 0x511F, 0xDFC2, 0x5546,
+	0xDFC3, 0x55AA, 0xDFC4, 0x5617, 0xDFC5, 0x5B40, 0xDFC6, 0x5C19,	0xDFC7, 0x5CE0, 0xDFC8, 0x5E38, 0xDFC9, 0x5E8A, 0xDFCA, 0x5EA0,
+	0xDFCB, 0x5EC2, 0xDFCC, 0x60F3, 0xDFCD, 0x6851, 0xDFCE, 0x6A61,	0xDFCF, 0x6E58, 0xDFD0, 0x723D, 0xDFD1, 0x7240, 0xDFD2, 0x72C0,
+	0xDFD3, 0x76F8, 0xDFD4, 0x7965, 0xDFD5, 0x7BB1, 0xDFD6, 0x7FD4,	0xDFD7, 0x88F3, 0xDFD8, 0x89F4, 0xDFD9, 0x8A73, 0xDFDA, 0x8C61,
+	0xDFDB, 0x8CDE, 0xDFDC, 0x971C, 0xDFDD, 0x585E, 0xDFDE, 0x74BD,	0xDFDF, 0x8CFD, 0xDFE0, 0x55C7, 0xDFE1, 0xF96C, 0xDFE2, 0x7A61,
+	0xDFE3, 0x7D22, 0xDFE4, 0x8272, 0xDFE5, 0x7272, 0xDFE6, 0x751F,	0xDFE7, 0x7525, 0xDFE8, 0xF96D, 0xDFE9, 0x7B19, 0xDFEA, 0x5885,
+	0xDFEB, 0x58FB, 0xDFEC, 0x5DBC, 0xDFED, 0x5E8F, 0xDFEE, 0x5EB6,	0xDFEF, 0x5F90, 0xDFF0, 0x6055, 0xDFF1, 0x6292, 0xDFF2, 0x637F,
+	0xDFF3, 0x654D, 0xDFF4, 0x6691, 0xDFF5, 0x66D9, 0xDFF6, 0x66F8,	0xDFF7, 0x6816, 0xDFF8, 0x68F2, 0xDFF9, 0x7280, 0xDFFA, 0x745E,
+	0xDFFB, 0x7B6E, 0xDFFC, 0x7D6E, 0xDFFD, 0x7DD6, 0xDFFE, 0x7F72,	0xE0A1, 0x80E5, 0xE0A2, 0x8212, 0xE0A3, 0x85AF, 0xE0A4, 0x897F,
+	0xE0A5, 0x8A93, 0xE0A6, 0x901D, 0xE0A7, 0x92E4, 0xE0A8, 0x9ECD,	0xE0A9, 0x9F20, 0xE0AA, 0x5915, 0xE0AB, 0x596D, 0xE0AC, 0x5E2D,
+	0xE0AD, 0x60DC, 0xE0AE, 0x6614, 0xE0AF, 0x6673, 0xE0B0, 0x6790,	0xE0B1, 0x6C50, 0xE0B2, 0x6DC5, 0xE0B3, 0x6F5F, 0xE0B4, 0x77F3,
+	0xE0B5, 0x78A9, 0xE0B6, 0x84C6, 0xE0B7, 0x91CB, 0xE0B8, 0x932B,	0xE0B9, 0x4ED9, 0xE0BA, 0x50CA, 0xE0BB, 0x5148, 0xE0BC, 0x5584,
+	0xE0BD, 0x5B0B, 0xE0BE, 0x5BA3, 0xE0BF, 0x6247, 0xE0C0, 0x657E,	0xE0C1, 0x65CB, 0xE0C2, 0x6E32, 0xE0C3, 0x717D, 0xE0C4, 0x7401,
+	0xE0C5, 0x7444, 0xE0C6, 0x7487, 0xE0C7, 0x74BF, 0xE0C8, 0x766C,	0xE0C9, 0x79AA, 0xE0CA, 0x7DDA, 0xE0CB, 0x7E55, 0xE0CC, 0x7FA8,
+	0xE0CD, 0x817A, 0xE0CE, 0x81B3, 0xE0CF, 0x8239, 0xE0D0, 0x861A,	0xE0D1, 0x87EC, 0xE0D2, 0x8A75, 0xE0D3, 0x8DE3, 0xE0D4, 0x9078,
+	0xE0D5, 0x9291, 0xE0D6, 0x9425, 0xE0D7, 0x994D, 0xE0D8, 0x9BAE,	0xE0D9, 0x5368, 0xE0DA, 0x5C51, 0xE0DB, 0x6954, 0xE0DC, 0x6CC4,
+	0xE0DD, 0x6D29, 0xE0DE, 0x6E2B, 0xE0DF, 0x820C, 0xE0E0, 0x859B,	0xE0E1, 0x893B, 0xE0E2, 0x8A2D, 0xE0E3, 0x8AAA, 0xE0E4, 0x96EA,
+	0xE0E5, 0x9F67, 0xE0E6, 0x5261, 0xE0E7, 0x66B9, 0xE0E8, 0x6BB2,	0xE0E9, 0x7E96, 0xE0EA, 0x87FE, 0xE0EB, 0x8D0D, 0xE0EC, 0x9583,
+	0xE0ED, 0x965D, 0xE0EE, 0x651D, 0xE0EF, 0x6D89, 0xE0F0, 0x71EE,	0xE0F1, 0xF96E, 0xE0F2, 0x57CE, 0xE0F3, 0x59D3, 0xE0F4, 0x5BAC,
+	0xE0F5, 0x6027, 0xE0F6, 0x60FA, 0xE0F7, 0x6210, 0xE0F8, 0x661F,	0xE0F9, 0x665F, 0xE0FA, 0x7329, 0xE0FB, 0x73F9, 0xE0FC, 0x76DB,
+	0xE0FD, 0x7701, 0xE0FE, 0x7B6C, 0xE1A1, 0x8056, 0xE1A2, 0x8072,	0xE1A3, 0x8165, 0xE1A4, 0x8AA0, 0xE1A5, 0x9192, 0xE1A6, 0x4E16,
+	0xE1A7, 0x52E2, 0xE1A8, 0x6B72, 0xE1A9, 0x6D17, 0xE1AA, 0x7A05,	0xE1AB, 0x7B39, 0xE1AC, 0x7D30, 0xE1AD, 0xF96F, 0xE1AE, 0x8CB0,
+	0xE1AF, 0x53EC, 0xE1B0, 0x562F, 0xE1B1, 0x5851, 0xE1B2, 0x5BB5,	0xE1B3, 0x5C0F, 0xE1B4, 0x5C11, 0xE1B5, 0x5DE2, 0xE1B6, 0x6240,
+	0xE1B7, 0x6383, 0xE1B8, 0x6414, 0xE1B9, 0x662D, 0xE1BA, 0x68B3,	0xE1BB, 0x6CBC, 0xE1BC, 0x6D88, 0xE1BD, 0x6EAF, 0xE1BE, 0x701F,
+	0xE1BF, 0x70A4, 0xE1C0, 0x71D2, 0xE1C1, 0x7526, 0xE1C2, 0x758F,	0xE1C3, 0x758E, 0xE1C4, 0x7619, 0xE1C5, 0x7B11, 0xE1C6, 0x7BE0,
+	0xE1C7, 0x7C2B, 0xE1C8, 0x7D20, 0xE1C9, 0x7D39, 0xE1CA, 0x852C,	0xE1CB, 0x856D, 0xE1CC, 0x8607, 0xE1CD, 0x8A34, 0xE1CE, 0x900D,
+	0xE1CF, 0x9061, 0xE1D0, 0x90B5, 0xE1D1, 0x92B7, 0xE1D2, 0x97F6,	0xE1D3, 0x9A37, 0xE1D4, 0x4FD7, 0xE1D5, 0x5C6C, 0xE1D6, 0x675F,
+	0xE1D7, 0x6D91, 0xE1D8, 0x7C9F, 0xE1D9, 0x7E8C, 0xE1DA, 0x8B16,	0xE1DB, 0x8D16, 0xE1DC, 0x901F, 0xE1DD, 0x5B6B, 0xE1DE, 0x5DFD,
+	0xE1DF, 0x640D, 0xE1E0, 0x84C0, 0xE1E1, 0x905C, 0xE1E2, 0x98E1,	0xE1E3, 0x7387, 0xE1E4, 0x5B8B, 0xE1E5, 0x609A, 0xE1E6, 0x677E,
+	0xE1E7, 0x6DDE, 0xE1E8, 0x8A1F, 0xE1E9, 0x8AA6, 0xE1EA, 0x9001,	0xE1EB, 0x980C, 0xE1EC, 0x5237, 0xE1ED, 0xF970, 0xE1EE, 0x7051,
+	0xE1EF, 0x788E, 0xE1F0, 0x9396, 0xE1F1, 0x8870, 0xE1F2, 0x91D7,	0xE1F3, 0x4FEE, 0xE1F4, 0x53D7, 0xE1F5, 0x55FD, 0xE1F6, 0x56DA,
+	0xE1F7, 0x5782, 0xE1F8, 0x58FD, 0xE1F9, 0x5AC2, 0xE1FA, 0x5B88,	0xE1FB, 0x5CAB, 0xE1FC, 0x5CC0, 0xE1FD, 0x5E25, 0xE1FE, 0x6101,
+	0xE2A1, 0x620D, 0xE2A2, 0x624B, 0xE2A3, 0x6388, 0xE2A4, 0x641C,	0xE2A5, 0x6536, 0xE2A6, 0x6578, 0xE2A7, 0x6A39, 0xE2A8, 0x6B8A,
+	0xE2A9, 0x6C34, 0xE2AA, 0x6D19, 0xE2AB, 0x6F31, 0xE2AC, 0x71E7,	0xE2AD, 0x72E9, 0xE2AE, 0x7378, 0xE2AF, 0x7407, 0xE2B0, 0x74B2,
+	0xE2B1, 0x7626, 0xE2B2, 0x7761, 0xE2B3, 0x79C0, 0xE2B4, 0x7A57,	0xE2B5, 0x7AEA, 0xE2B6, 0x7CB9, 0xE2B7, 0x7D8F, 0xE2B8, 0x7DAC,
+	0xE2B9, 0x7E61, 0xE2BA, 0x7F9E, 0xE2BB, 0x8129, 0xE2BC, 0x8331,	0xE2BD, 0x8490, 0xE2BE, 0x84DA, 0xE2BF, 0x85EA, 0xE2C0, 0x8896,
+	0xE2C1, 0x8AB0, 0xE2C2, 0x8B90, 0xE2C3, 0x8F38, 0xE2C4, 0x9042,	0xE2C5, 0x9083, 0xE2C6, 0x916C, 0xE2C7, 0x9296, 0xE2C8, 0x92B9,
+	0xE2C9, 0x968B, 0xE2CA, 0x96A7, 0xE2CB, 0x96A8, 0xE2CC, 0x96D6,	0xE2CD, 0x9700, 0xE2CE, 0x9808, 0xE2CF, 0x9996, 0xE2D0, 0x9AD3,
+	0xE2D1, 0x9B1A, 0xE2D2, 0x53D4, 0xE2D3, 0x587E, 0xE2D4, 0x5919,	0xE2D5, 0x5B70, 0xE2D6, 0x5BBF, 0xE2D7, 0x6DD1, 0xE2D8, 0x6F5A,
+	0xE2D9, 0x719F, 0xE2DA, 0x7421, 0xE2DB, 0x74B9, 0xE2DC, 0x8085,	0xE2DD, 0x83FD, 0xE2DE, 0x5DE1, 0xE2DF, 0x5F87, 0xE2E0, 0x5FAA,
+	0xE2E1, 0x6042, 0xE2E2, 0x65EC, 0xE2E3, 0x6812, 0xE2E4, 0x696F,	0xE2E5, 0x6A53, 0xE2E6, 0x6B89, 0xE2E7, 0x6D35, 0xE2E8, 0x6DF3,
+	0xE2E9, 0x73E3, 0xE2EA, 0x76FE, 0xE2EB, 0x77AC, 0xE2EC, 0x7B4D,	0xE2ED, 0x7D14, 0xE2EE, 0x8123, 0xE2EF, 0x821C, 0xE2F0, 0x8340,
+	0xE2F1, 0x84F4, 0xE2F2, 0x8563, 0xE2F3, 0x8A62, 0xE2F4, 0x8AC4,	0xE2F5, 0x9187, 0xE2F6, 0x931E, 0xE2F7, 0x9806, 0xE2F8, 0x99B4,
+	0xE2F9, 0x620C, 0xE2FA, 0x8853, 0xE2FB, 0x8FF0, 0xE2FC, 0x9265,	0xE2FD, 0x5D07, 0xE2FE, 0x5D27, 0xE3A1, 0x5D69, 0xE3A2, 0x745F,
+	0xE3A3, 0x819D, 0xE3A4, 0x8768, 0xE3A5, 0x6FD5, 0xE3A6, 0x62FE,	0xE3A7, 0x7FD2, 0xE3A8, 0x8936, 0xE3A9, 0x8972, 0xE3AA, 0x4E1E,
+	0xE3AB, 0x4E58, 0xE3AC, 0x50E7, 0xE3AD, 0x52DD, 0xE3AE, 0x5347,	0xE3AF, 0x627F, 0xE3B0, 0x6607, 0xE3B1, 0x7E69, 0xE3B2, 0x8805,
+	0xE3B3, 0x965E, 0xE3B4, 0x4F8D, 0xE3B5, 0x5319, 0xE3B6, 0x5636,	0xE3B7, 0x59CB, 0xE3B8, 0x5AA4, 0xE3B9, 0x5C38, 0xE3BA, 0x5C4E,
+	0xE3BB, 0x5C4D, 0xE3BC, 0x5E02, 0xE3BD, 0x5F11, 0xE3BE, 0x6043,	0xE3BF, 0x65BD, 0xE3C0, 0x662F, 0xE3C1, 0x6642, 0xE3C2, 0x67BE,
+	0xE3C3, 0x67F4, 0xE3C4, 0x731C, 0xE3C5, 0x77E2, 0xE3C6, 0x793A,	0xE3C7, 0x7FC5, 0xE3C8, 0x8494, 0xE3C9, 0x84CD, 0xE3CA, 0x8996,
+	0xE3CB, 0x8A66, 0xE3CC, 0x8A69, 0xE3CD, 0x8AE1, 0xE3CE, 0x8C55,	0xE3CF, 0x8C7A, 0xE3D0, 0x57F4, 0xE3D1, 0x5BD4, 0xE3D2, 0x5F0F,
+	0xE3D3, 0x606F, 0xE3D4, 0x62ED, 0xE3D5, 0x690D, 0xE3D6, 0x6B96,	0xE3D7, 0x6E5C, 0xE3D8, 0x7184, 0xE3D9, 0x7BD2, 0xE3DA, 0x8755,
+	0xE3DB, 0x8B58, 0xE3DC, 0x8EFE, 0xE3DD, 0x98DF, 0xE3DE, 0x98FE,	0xE3DF, 0x4F38, 0xE3E0, 0x4F81, 0xE3E1, 0x4FE1, 0xE3E2, 0x547B,
+	0xE3E3, 0x5A20, 0xE3E4, 0x5BB8, 0xE3E5, 0x613C, 0xE3E6, 0x65B0,	0xE3E7, 0x6668, 0xE3E8, 0x71FC, 0xE3E9, 0x7533, 0xE3EA, 0x795E,
+	0xE3EB, 0x7D33, 0xE3EC, 0x814E, 0xE3ED, 0x81E3, 0xE3EE, 0x8398,	0xE3EF, 0x85AA, 0xE3F0, 0x85CE, 0xE3F1, 0x8703, 0xE3F2, 0x8A0A,
+	0xE3F3, 0x8EAB, 0xE3F4, 0x8F9B, 0xE3F5, 0xF971, 0xE3F6, 0x8FC5,	0xE3F7, 0x5931, 0xE3F8, 0x5BA4, 0xE3F9, 0x5BE6, 0xE3FA, 0x6089,
+	0xE3FB, 0x5BE9, 0xE3FC, 0x5C0B, 0xE3FD, 0x5FC3, 0xE3FE, 0x6C81,	0xE4A1, 0xF972, 0xE4A2, 0x6DF1, 0xE4A3, 0x700B, 0xE4A4, 0x751A,
+	0xE4A5, 0x82AF, 0xE4A6, 0x8AF6, 0xE4A7, 0x4EC0, 0xE4A8, 0x5341,	0xE4A9, 0xF973, 0xE4AA, 0x96D9, 0xE4AB, 0x6C0F, 0xE4AC, 0x4E9E,
+	0xE4AD, 0x4FC4, 0xE4AE, 0x5152, 0xE4AF, 0x555E, 0xE4B0, 0x5A25,	0xE4B1, 0x5CE8, 0xE4B2, 0x6211, 0xE4B3, 0x7259, 0xE4B4, 0x82BD,
+	0xE4B5, 0x83AA, 0xE4B6, 0x86FE, 0xE4B7, 0x8859, 0xE4B8, 0x8A1D,	0xE4B9, 0x963F, 0xE4BA, 0x96C5, 0xE4BB, 0x9913, 0xE4BC, 0x9D09,
+	0xE4BD, 0x9D5D, 0xE4BE, 0x580A, 0xE4BF, 0x5CB3, 0xE4C0, 0x5DBD,	0xE4C1, 0x5E44, 0xE4C2, 0x60E1, 0xE4C3, 0x6115, 0xE4C4, 0x63E1,
+	0xE4C5, 0x6A02, 0xE4C6, 0x6E25, 0xE4C7, 0x9102, 0xE4C8, 0x9354,	0xE4C9, 0x984E, 0xE4CA, 0x9C10, 0xE4CB, 0x9F77, 0xE4CC, 0x5B89,
+	0xE4CD, 0x5CB8, 0xE4CE, 0x6309, 0xE4CF, 0x664F, 0xE4D0, 0x6848,	0xE4D1, 0x773C, 0xE4D2, 0x96C1, 0xE4D3, 0x978D, 0xE4D4, 0x9854,
+	0xE4D5, 0x9B9F, 0xE4D6, 0x65A1, 0xE4D7, 0x8B01, 0xE4D8, 0x8ECB,	0xE4D9, 0x95BC, 0xE4DA, 0x5535, 0xE4DB, 0x5CA9, 0xE4DC, 0x5DD6,
+	0xE4DD, 0x5EB5, 0xE4DE, 0x6697, 0xE4DF, 0x764C, 0xE4E0, 0x83F4,	0xE4E1, 0x95C7, 0xE4E2, 0x58D3, 0xE4E3, 0x62BC, 0xE4E4, 0x72CE,
+	0xE4E5, 0x9D28, 0xE4E6, 0x4EF0, 0xE4E7, 0x592E, 0xE4E8, 0x600F,	0xE4E9, 0x663B, 0xE4EA, 0x6B83, 0xE4EB, 0x79E7, 0xE4EC, 0x9D26,
+	0xE4ED, 0x5393, 0xE4EE, 0x54C0, 0xE4EF, 0x57C3, 0xE4F0, 0x5D16,	0xE4F1, 0x611B, 0xE4F2, 0x66D6, 0xE4F3, 0x6DAF, 0xE4F4, 0x788D,
+	0xE4F5, 0x827E, 0xE4F6, 0x9698, 0xE4F7, 0x9744, 0xE4F8, 0x5384,	0xE4F9, 0x627C, 0xE4FA, 0x6396, 0xE4FB, 0x6DB2, 0xE4FC, 0x7E0A,
+	0xE4FD, 0x814B, 0xE4FE, 0x984D, 0xE5A1, 0x6AFB, 0xE5A2, 0x7F4C,	0xE5A3, 0x9DAF, 0xE5A4, 0x9E1A, 0xE5A5, 0x4E5F, 0xE5A6, 0x503B,
+	0xE5A7, 0x51B6, 0xE5A8, 0x591C, 0xE5A9, 0x60F9, 0xE5AA, 0x63F6,	0xE5AB, 0x6930, 0xE5AC, 0x723A, 0xE5AD, 0x8036, 0xE5AE, 0xF974,
+	0xE5AF, 0x91CE, 0xE5B0, 0x5F31, 0xE5B1, 0xF975, 0xE5B2, 0xF976,	0xE5B3, 0x7D04, 0xE5B4, 0x82E5, 0xE5B5, 0x846F, 0xE5B6, 0x84BB,
+	0xE5B7, 0x85E5, 0xE5B8, 0x8E8D, 0xE5B9, 0xF977, 0xE5BA, 0x4F6F,	0xE5BB, 0xF978, 0xE5BC, 0xF979, 0xE5BD, 0x58E4, 0xE5BE, 0x5B43,
+	0xE5BF, 0x6059, 0xE5C0, 0x63DA, 0xE5C1, 0x6518, 0xE5C2, 0x656D,	0xE5C3, 0x6698, 0xE5C4, 0xF97A, 0xE5C5, 0x694A, 0xE5C6, 0x6A23,
+	0xE5C7, 0x6D0B, 0xE5C8, 0x7001, 0xE5C9, 0x716C, 0xE5CA, 0x75D2,	0xE5CB, 0x760D, 0xE5CC, 0x79B3, 0xE5CD, 0x7A70, 0xE5CE, 0xF97B,
+	0xE5CF, 0x7F8A, 0xE5D0, 0xF97C, 0xE5D1, 0x8944, 0xE5D2, 0xF97D,	0xE5D3, 0x8B93, 0xE5D4, 0x91C0, 0xE5D5, 0x967D, 0xE5D6, 0xF97E,
+	0xE5D7, 0x990A, 0xE5D8, 0x5704, 0xE5D9, 0x5FA1, 0xE5DA, 0x65BC,	0xE5DB, 0x6F01, 0xE5DC, 0x7600, 0xE5DD, 0x79A6, 0xE5DE, 0x8A9E,
+	0xE5DF, 0x99AD, 0xE5E0, 0x9B5A, 0xE5E1, 0x9F6C, 0xE5E2, 0x5104,	0xE5E3, 0x61B6, 0xE5E4, 0x6291, 0xE5E5, 0x6A8D, 0xE5E6, 0x81C6,
+	0xE5E7, 0x5043, 0xE5E8, 0x5830, 0xE5E9, 0x5F66, 0xE5EA, 0x7109,	0xE5EB, 0x8A00, 0xE5EC, 0x8AFA, 0xE5ED, 0x5B7C, 0xE5EE, 0x8616,
+	0xE5EF, 0x4FFA, 0xE5F0, 0x513C, 0xE5F1, 0x56B4, 0xE5F2, 0x5944,	0xE5F3, 0x63A9, 0xE5F4, 0x6DF9, 0xE5F5, 0x5DAA, 0xE5F6, 0x696D,
+	0xE5F7, 0x5186, 0xE5F8, 0x4E88, 0xE5F9, 0x4F59, 0xE5FA, 0xF97F,	0xE5FB, 0xF980, 0xE5FC, 0xF981, 0xE5FD, 0x5982, 0xE5FE, 0xF982,
+	0xE6A1, 0xF983, 0xE6A2, 0x6B5F, 0xE6A3, 0x6C5D, 0xE6A4, 0xF984,	0xE6A5, 0x74B5, 0xE6A6, 0x7916, 0xE6A7, 0xF985, 0xE6A8, 0x8207,
+	0xE6A9, 0x8245, 0xE6AA, 0x8339, 0xE6AB, 0x8F3F, 0xE6AC, 0x8F5D,	0xE6AD, 0xF986, 0xE6AE, 0x9918, 0xE6AF, 0xF987, 0xE6B0, 0xF988,
+	0xE6B1, 0xF989, 0xE6B2, 0x4EA6, 0xE6B3, 0xF98A, 0xE6B4, 0x57DF,	0xE6B5, 0x5F79, 0xE6B6, 0x6613, 0xE6B7, 0xF98B, 0xE6B8, 0xF98C,
+	0xE6B9, 0x75AB, 0xE6BA, 0x7E79, 0xE6BB, 0x8B6F, 0xE6BC, 0xF98D,	0xE6BD, 0x9006, 0xE6BE, 0x9A5B, 0xE6BF, 0x56A5, 0xE6C0, 0x5827,
+	0xE6C1, 0x59F8, 0xE6C2, 0x5A1F, 0xE6C3, 0x5BB4, 0xE6C4, 0xF98E,	0xE6C5, 0x5EF6, 0xE6C6, 0xF98F, 0xE6C7, 0xF990, 0xE6C8, 0x6350,
+	0xE6C9, 0x633B, 0xE6CA, 0xF991, 0xE6CB, 0x693D, 0xE6CC, 0x6C87,	0xE6CD, 0x6CBF, 0xE6CE, 0x6D8E, 0xE6CF, 0x6D93, 0xE6D0, 0x6DF5,
+	0xE6D1, 0x6F14, 0xE6D2, 0xF992, 0xE6D3, 0x70DF, 0xE6D4, 0x7136,	0xE6D5, 0x7159, 0xE6D6, 0xF993, 0xE6D7, 0x71C3, 0xE6D8, 0x71D5,
+	0xE6D9, 0xF994, 0xE6DA, 0x784F, 0xE6DB, 0x786F, 0xE6DC, 0xF995,	0xE6DD, 0x7B75, 0xE6DE, 0x7DE3, 0xE6DF, 0xF996, 0xE6E0, 0x7E2F,
+	0xE6E1, 0xF997, 0xE6E2, 0x884D, 0xE6E3, 0x8EDF, 0xE6E4, 0xF998,	0xE6E5, 0xF999, 0xE6E6, 0xF99A, 0xE6E7, 0x925B, 0xE6E8, 0xF99B,
+	0xE6E9, 0x9CF6, 0xE6EA, 0xF99C, 0xE6EB, 0xF99D, 0xE6EC, 0xF99E,	0xE6ED, 0x6085, 0xE6EE, 0x6D85, 0xE6EF, 0xF99F, 0xE6F0, 0x71B1,
+	0xE6F1, 0xF9A0, 0xE6F2, 0xF9A1, 0xE6F3, 0x95B1, 0xE6F4, 0x53AD,	0xE6F5, 0xF9A2, 0xE6F6, 0xF9A3, 0xE6F7, 0xF9A4, 0xE6F8, 0x67D3,
+	0xE6F9, 0xF9A5, 0xE6FA, 0x708E, 0xE6FB, 0x7130, 0xE6FC, 0x7430,	0xE6FD, 0x8276, 0xE6FE, 0x82D2, 0xE7A1, 0xF9A6, 0xE7A2, 0x95BB,
+	0xE7A3, 0x9AE5, 0xE7A4, 0x9E7D, 0xE7A5, 0x66C4, 0xE7A6, 0xF9A7,	0xE7A7, 0x71C1, 0xE7A8, 0x8449, 0xE7A9, 0xF9A8, 0xE7AA, 0xF9A9,
+	0xE7AB, 0x584B, 0xE7AC, 0xF9AA, 0xE7AD, 0xF9AB, 0xE7AE, 0x5DB8,	0xE7AF, 0x5F71, 0xE7B0, 0xF9AC, 0xE7B1, 0x6620, 0xE7B2, 0x668E,
+	0xE7B3, 0x6979, 0xE7B4, 0x69AE, 0xE7B5, 0x6C38, 0xE7B6, 0x6CF3,	0xE7B7, 0x6E36, 0xE7B8, 0x6F41, 0xE7B9, 0x6FDA, 0xE7BA, 0x701B,
+	0xE7BB, 0x702F, 0xE7BC, 0x7150, 0xE7BD, 0x71DF, 0xE7BE, 0x7370,	0xE7BF, 0xF9AD, 0xE7C0, 0x745B, 0xE7C1, 0xF9AE, 0xE7C2, 0x74D4,
+	0xE7C3, 0x76C8, 0xE7C4, 0x7A4E, 0xE7C5, 0x7E93, 0xE7C6, 0xF9AF,	0xE7C7, 0xF9B0, 0xE7C8, 0x82F1, 0xE7C9, 0x8A60, 0xE7CA, 0x8FCE,
+	0xE7CB, 0xF9B1, 0xE7CC, 0x9348, 0xE7CD, 0xF9B2, 0xE7CE, 0x9719,	0xE7CF, 0xF9B3, 0xE7D0, 0xF9B4, 0xE7D1, 0x4E42, 0xE7D2, 0x502A,
+	0xE7D3, 0xF9B5, 0xE7D4, 0x5208, 0xE7D5, 0x53E1, 0xE7D6, 0x66F3,	0xE7D7, 0x6C6D, 0xE7D8, 0x6FCA, 0xE7D9, 0x730A, 0xE7DA, 0x777F,
+	0xE7DB, 0x7A62, 0xE7DC, 0x82AE, 0xE7DD, 0x85DD, 0xE7DE, 0x8602,	0xE7DF, 0xF9B6, 0xE7E0, 0x88D4, 0xE7E1, 0x8A63, 0xE7E2, 0x8B7D,
+	0xE7E3, 0x8C6B, 0xE7E4, 0xF9B7, 0xE7E5, 0x92B3, 0xE7E6, 0xF9B8,	0xE7E7, 0x9713, 0xE7E8, 0x9810, 0xE7E9, 0x4E94, 0xE7EA, 0x4F0D,
+	0xE7EB, 0x4FC9, 0xE7EC, 0x50B2, 0xE7ED, 0x5348, 0xE7EE, 0x543E,	0xE7EF, 0x5433, 0xE7F0, 0x55DA, 0xE7F1, 0x5862, 0xE7F2, 0x58BA,
+	0xE7F3, 0x5967, 0xE7F4, 0x5A1B, 0xE7F5, 0x5BE4, 0xE7F6, 0x609F,	0xE7F7, 0xF9B9, 0xE7F8, 0x61CA, 0xE7F9, 0x6556, 0xE7FA, 0x65FF,
+	0xE7FB, 0x6664, 0xE7FC, 0x68A7, 0xE7FD, 0x6C5A, 0xE7FE, 0x6FB3,	0xE8A1, 0x70CF, 0xE8A2, 0x71AC, 0xE8A3, 0x7352, 0xE8A4, 0x7B7D,
+	0xE8A5, 0x8708, 0xE8A6, 0x8AA4, 0xE8A7, 0x9C32, 0xE8A8, 0x9F07,	0xE8A9, 0x5C4B, 0xE8AA, 0x6C83, 0xE8AB, 0x7344, 0xE8AC, 0x7389,
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+	0xEFBB, 0x7664, 0xEFBC, 0x7ACA, 0xEFBD, 0x7BC0, 0xEFBE, 0x7D76,	0xEFBF, 0x5360, 0xEFC0, 0x5CBE, 0xEFC1, 0x5E97, 0xEFC2, 0x6F38,
+	0xEFC3, 0x70B9, 0xEFC4, 0x7C98, 0xEFC5, 0x9711, 0xEFC6, 0x9B8E,	0xEFC7, 0x9EDE, 0xEFC8, 0x63A5, 0xEFC9, 0x647A, 0xEFCA, 0x8776,
+	0xEFCB, 0x4E01, 0xEFCC, 0x4E95, 0xEFCD, 0x4EAD, 0xEFCE, 0x505C,	0xEFCF, 0x5075, 0xEFD0, 0x5448, 0xEFD1, 0x59C3, 0xEFD2, 0x5B9A,
+	0xEFD3, 0x5E40, 0xEFD4, 0x5EAD, 0xEFD5, 0x5EF7, 0xEFD6, 0x5F81,	0xEFD7, 0x60C5, 0xEFD8, 0x633A, 0xEFD9, 0x653F, 0xEFDA, 0x6574,
+	0xEFDB, 0x65CC, 0xEFDC, 0x6676, 0xEFDD, 0x6678, 0xEFDE, 0x67FE,	0xEFDF, 0x6968, 0xEFE0, 0x6A89, 0xEFE1, 0x6B63, 0xEFE2, 0x6C40,
+	0xEFE3, 0x6DC0, 0xEFE4, 0x6DE8, 0xEFE5, 0x6E1F, 0xEFE6, 0x6E5E,	0xEFE7, 0x701E, 0xEFE8, 0x70A1, 0xEFE9, 0x738E, 0xEFEA, 0x73FD,
+	0xEFEB, 0x753A, 0xEFEC, 0x775B, 0xEFED, 0x7887, 0xEFEE, 0x798E,	0xEFEF, 0x7A0B, 0xEFF0, 0x7A7D, 0xEFF1, 0x7CBE, 0xEFF2, 0x7D8E,
+	0xEFF3, 0x8247, 0xEFF4, 0x8A02, 0xEFF5, 0x8AEA, 0xEFF6, 0x8C9E,	0xEFF7, 0x912D, 0xEFF8, 0x914A, 0xEFF9, 0x91D8, 0xEFFA, 0x9266,
+	0xEFFB, 0x92CC, 0xEFFC, 0x9320, 0xEFFD, 0x9706, 0xEFFE, 0x9756,	0xF0A1, 0x975C, 0xF0A2, 0x9802, 0xF0A3, 0x9F0E, 0xF0A4, 0x5236,
+	0xF0A5, 0x5291, 0xF0A6, 0x557C, 0xF0A7, 0x5824, 0xF0A8, 0x5E1D,	0xF0A9, 0x5F1F, 0xF0AA, 0x608C, 0xF0AB, 0x63D0, 0xF0AC, 0x68AF,
+	0xF0AD, 0x6FDF, 0xF0AE, 0x796D, 0xF0AF, 0x7B2C, 0xF0B0, 0x81CD,	0xF0B1, 0x85BA, 0xF0B2, 0x88FD, 0xF0B3, 0x8AF8, 0xF0B4, 0x8E44,
+	0xF0B5, 0x918D, 0xF0B6, 0x9664, 0xF0B7, 0x969B, 0xF0B8, 0x973D,	0xF0B9, 0x984C, 0xF0BA, 0x9F4A, 0xF0BB, 0x4FCE, 0xF0BC, 0x5146,
+	0xF0BD, 0x51CB, 0xF0BE, 0x52A9, 0xF0BF, 0x5632, 0xF0C0, 0x5F14,	0xF0C1, 0x5F6B, 0xF0C2, 0x63AA, 0xF0C3, 0x64CD, 0xF0C4, 0x65E9,
+	0xF0C5, 0x6641, 0xF0C6, 0x66FA, 0xF0C7, 0x66F9, 0xF0C8, 0x671D,	0xF0C9, 0x689D, 0xF0CA, 0x68D7, 0xF0CB, 0x69FD, 0xF0CC, 0x6F15,
+	0xF0CD, 0x6F6E, 0xF0CE, 0x7167, 0xF0CF, 0x71E5, 0xF0D0, 0x722A,	0xF0D1, 0x74AA, 0xF0D2, 0x773A, 0xF0D3, 0x7956, 0xF0D4, 0x795A,
+	0xF0D5, 0x79DF, 0xF0D6, 0x7A20, 0xF0D7, 0x7A95, 0xF0D8, 0x7C97,	0xF0D9, 0x7CDF, 0xF0DA, 0x7D44, 0xF0DB, 0x7E70, 0xF0DC, 0x8087,
+	0xF0DD, 0x85FB, 0xF0DE, 0x86A4, 0xF0DF, 0x8A54, 0xF0E0, 0x8ABF,	0xF0E1, 0x8D99, 0xF0E2, 0x8E81, 0xF0E3, 0x9020, 0xF0E4, 0x906D,
+	0xF0E5, 0x91E3, 0xF0E6, 0x963B, 0xF0E7, 0x96D5, 0xF0E8, 0x9CE5,	0xF0E9, 0x65CF, 0xF0EA, 0x7C07, 0xF0EB, 0x8DB3, 0xF0EC, 0x93C3,
+	0xF0ED, 0x5B58, 0xF0EE, 0x5C0A, 0xF0EF, 0x5352, 0xF0F0, 0x62D9,	0xF0F1, 0x731D, 0xF0F2, 0x5027, 0xF0F3, 0x5B97, 0xF0F4, 0x5F9E,
+	0xF0F5, 0x60B0, 0xF0F6, 0x616B, 0xF0F7, 0x68D5, 0xF0F8, 0x6DD9,	0xF0F9, 0x742E, 0xF0FA, 0x7A2E, 0xF0FB, 0x7D42, 0xF0FC, 0x7D9C,
+	0xF0FD, 0x7E31, 0xF0FE, 0x816B, 0xF1A1, 0x8E2A, 0xF1A2, 0x8E35,	0xF1A3, 0x937E, 0xF1A4, 0x9418, 0xF1A5, 0x4F50, 0xF1A6, 0x5750,
+	0xF1A7, 0x5DE6, 0xF1A8, 0x5EA7, 0xF1A9, 0x632B, 0xF1AA, 0x7F6A,	0xF1AB, 0x4E3B, 0xF1AC, 0x4F4F, 0xF1AD, 0x4F8F, 0xF1AE, 0x505A,
+	0xF1AF, 0x59DD, 0xF1B0, 0x80C4, 0xF1B1, 0x546A, 0xF1B2, 0x5468,	0xF1B3, 0x55FE, 0xF1B4, 0x594F, 0xF1B5, 0x5B99, 0xF1B6, 0x5DDE,
+	0xF1B7, 0x5EDA, 0xF1B8, 0x665D, 0xF1B9, 0x6731, 0xF1BA, 0x67F1,	0xF1BB, 0x682A, 0xF1BC, 0x6CE8, 0xF1BD, 0x6D32, 0xF1BE, 0x6E4A,
+	0xF1BF, 0x6F8D, 0xF1C0, 0x70B7, 0xF1C1, 0x73E0, 0xF1C2, 0x7587,	0xF1C3, 0x7C4C, 0xF1C4, 0x7D02, 0xF1C5, 0x7D2C, 0xF1C6, 0x7DA2,
+	0xF1C7, 0x821F, 0xF1C8, 0x86DB, 0xF1C9, 0x8A3B, 0xF1CA, 0x8A85,	0xF1CB, 0x8D70, 0xF1CC, 0x8E8A, 0xF1CD, 0x8F33, 0xF1CE, 0x9031,
+	0xF1CF, 0x914E, 0xF1D0, 0x9152, 0xF1D1, 0x9444, 0xF1D2, 0x99D0,	0xF1D3, 0x7AF9, 0xF1D4, 0x7CA5, 0xF1D5, 0x4FCA, 0xF1D6, 0x5101,
+	0xF1D7, 0x51C6, 0xF1D8, 0x57C8, 0xF1D9, 0x5BEF, 0xF1DA, 0x5CFB,	0xF1DB, 0x6659, 0xF1DC, 0x6A3D, 0xF1DD, 0x6D5A, 0xF1DE, 0x6E96,
+	0xF1DF, 0x6FEC, 0xF1E0, 0x710C, 0xF1E1, 0x756F, 0xF1E2, 0x7AE3,	0xF1E3, 0x8822, 0xF1E4, 0x9021, 0xF1E5, 0x9075, 0xF1E6, 0x96CB,
+	0xF1E7, 0x99FF, 0xF1E8, 0x8301, 0xF1E9, 0x4E2D, 0xF1EA, 0x4EF2,	0xF1EB, 0x8846, 0xF1EC, 0x91CD, 0xF1ED, 0x537D, 0xF1EE, 0x6ADB,
+	0xF1EF, 0x696B, 0xF1F0, 0x6C41, 0xF1F1, 0x847A, 0xF1F2, 0x589E,	0xF1F3, 0x618E, 0xF1F4, 0x66FE, 0xF1F5, 0x62EF, 0xF1F6, 0x70DD,
+	0xF1F7, 0x7511, 0xF1F8, 0x75C7, 0xF1F9, 0x7E52, 0xF1FA, 0x84B8,	0xF1FB, 0x8B49, 0xF1FC, 0x8D08, 0xF1FD, 0x4E4B, 0xF1FE, 0x53EA,
+	0xF2A1, 0x54AB, 0xF2A2, 0x5730, 0xF2A3, 0x5740, 0xF2A4, 0x5FD7,	0xF2A5, 0x6301, 0xF2A6, 0x6307, 0xF2A7, 0x646F, 0xF2A8, 0x652F,
+	0xF2A9, 0x65E8, 0xF2AA, 0x667A, 0xF2AB, 0x679D, 0xF2AC, 0x67B3,	0xF2AD, 0x6B62, 0xF2AE, 0x6C60, 0xF2AF, 0x6C9A, 0xF2B0, 0x6F2C,
+	0xF2B1, 0x77E5, 0xF2B2, 0x7825, 0xF2B3, 0x7949, 0xF2B4, 0x7957,	0xF2B5, 0x7D19, 0xF2B6, 0x80A2, 0xF2B7, 0x8102, 0xF2B8, 0x81F3,
+	0xF2B9, 0x829D, 0xF2BA, 0x82B7, 0xF2BB, 0x8718, 0xF2BC, 0x8A8C,	0xF2BD, 0xF9FC, 0xF2BE, 0x8D04, 0xF2BF, 0x8DBE, 0xF2C0, 0x9072,
+	0xF2C1, 0x76F4, 0xF2C2, 0x7A19, 0xF2C3, 0x7A37, 0xF2C4, 0x7E54,	0xF2C5, 0x8077, 0xF2C6, 0x5507, 0xF2C7, 0x55D4, 0xF2C8, 0x5875,
+	0xF2C9, 0x632F, 0xF2CA, 0x6422, 0xF2CB, 0x6649, 0xF2CC, 0x664B,	0xF2CD, 0x686D, 0xF2CE, 0x699B, 0xF2CF, 0x6B84, 0xF2D0, 0x6D25,
+	0xF2D1, 0x6EB1, 0xF2D2, 0x73CD, 0xF2D3, 0x7468, 0xF2D4, 0x74A1,	0xF2D5, 0x755B, 0xF2D6, 0x75B9, 0xF2D7, 0x76E1, 0xF2D8, 0x771E,
+	0xF2D9, 0x778B, 0xF2DA, 0x79E6, 0xF2DB, 0x7E09, 0xF2DC, 0x7E1D,	0xF2DD, 0x81FB, 0xF2DE, 0x852F, 0xF2DF, 0x8897, 0xF2E0, 0x8A3A,
+	0xF2E1, 0x8CD1, 0xF2E2, 0x8EEB, 0xF2E3, 0x8FB0, 0xF2E4, 0x9032,	0xF2E5, 0x93AD, 0xF2E6, 0x9663, 0xF2E7, 0x9673, 0xF2E8, 0x9707,
+	0xF2E9, 0x4F84, 0xF2EA, 0x53F1, 0xF2EB, 0x59EA, 0xF2EC, 0x5AC9,	0xF2ED, 0x5E19, 0xF2EE, 0x684E, 0xF2EF, 0x74C6, 0xF2F0, 0x75BE,
+	0xF2F1, 0x79E9, 0xF2F2, 0x7A92, 0xF2F3, 0x81A3, 0xF2F4, 0x86ED,	0xF2F5, 0x8CEA, 0xF2F6, 0x8DCC, 0xF2F7, 0x8FED, 0xF2F8, 0x659F,
+	0xF2F9, 0x6715, 0xF2FA, 0xF9FD, 0xF2FB, 0x57F7, 0xF2FC, 0x6F57,	0xF2FD, 0x7DDD, 0xF2FE, 0x8F2F, 0xF3A1, 0x93F6, 0xF3A2, 0x96C6,
+	0xF3A3, 0x5FB5, 0xF3A4, 0x61F2, 0xF3A5, 0x6F84, 0xF3A6, 0x4E14,	0xF3A7, 0x4F98, 0xF3A8, 0x501F, 0xF3A9, 0x53C9, 0xF3AA, 0x55DF,
+	0xF3AB, 0x5D6F, 0xF3AC, 0x5DEE, 0xF3AD, 0x6B21, 0xF3AE, 0x6B64,	0xF3AF, 0x78CB, 0xF3B0, 0x7B9A, 0xF3B1, 0xF9FE, 0xF3B2, 0x8E49,
+	0xF3B3, 0x8ECA, 0xF3B4, 0x906E, 0xF3B5, 0x6349, 0xF3B6, 0x643E,	0xF3B7, 0x7740, 0xF3B8, 0x7A84, 0xF3B9, 0x932F, 0xF3BA, 0x947F,
+	0xF3BB, 0x9F6A, 0xF3BC, 0x64B0, 0xF3BD, 0x6FAF, 0xF3BE, 0x71E6,	0xF3BF, 0x74A8, 0xF3C0, 0x74DA, 0xF3C1, 0x7AC4, 0xF3C2, 0x7C12,
+	0xF3C3, 0x7E82, 0xF3C4, 0x7CB2, 0xF3C5, 0x7E98, 0xF3C6, 0x8B9A,	0xF3C7, 0x8D0A, 0xF3C8, 0x947D, 0xF3C9, 0x9910, 0xF3CA, 0x994C,
+	0xF3CB, 0x5239, 0xF3CC, 0x5BDF, 0xF3CD, 0x64E6, 0xF3CE, 0x672D,	0xF3CF, 0x7D2E, 0xF3D0, 0x50ED, 0xF3D1, 0x53C3, 0xF3D2, 0x5879,
+	0xF3D3, 0x6158, 0xF3D4, 0x6159, 0xF3D5, 0x61FA, 0xF3D6, 0x65AC,	0xF3D7, 0x7AD9, 0xF3D8, 0x8B92, 0xF3D9, 0x8B96, 0xF3DA, 0x5009,
+	0xF3DB, 0x5021, 0xF3DC, 0x5275, 0xF3DD, 0x5531, 0xF3DE, 0x5A3C,	0xF3DF, 0x5EE0, 0xF3E0, 0x5F70, 0xF3E1, 0x6134, 0xF3E2, 0x655E,
+	0xF3E3, 0x660C, 0xF3E4, 0x6636, 0xF3E5, 0x66A2, 0xF3E6, 0x69CD,	0xF3E7, 0x6EC4, 0xF3E8, 0x6F32, 0xF3E9, 0x7316, 0xF3EA, 0x7621,
+	0xF3EB, 0x7A93, 0xF3EC, 0x8139, 0xF3ED, 0x8259, 0xF3EE, 0x83D6,	0xF3EF, 0x84BC, 0xF3F0, 0x50B5, 0xF3F1, 0x57F0, 0xF3F2, 0x5BC0,
+	0xF3F3, 0x5BE8, 0xF3F4, 0x5F69, 0xF3F5, 0x63A1, 0xF3F6, 0x7826,	0xF3F7, 0x7DB5, 0xF3F8, 0x83DC, 0xF3F9, 0x8521, 0xF3FA, 0x91C7,
+	0xF3FB, 0x91F5, 0xF3FC, 0x518A, 0xF3FD, 0x67F5, 0xF3FE, 0x7B56,	0xF4A1, 0x8CAC, 0xF4A2, 0x51C4, 0xF4A3, 0x59BB, 0xF4A4, 0x60BD,
+	0xF4A5, 0x8655, 0xF4A6, 0x501C, 0xF4A7, 0xF9FF, 0xF4A8, 0x5254,	0xF4A9, 0x5C3A, 0xF4AA, 0x617D, 0xF4AB, 0x621A, 0xF4AC, 0x62D3,
+	0xF4AD, 0x64F2, 0xF4AE, 0x65A5, 0xF4AF, 0x6ECC, 0xF4B0, 0x7620,	0xF4B1, 0x810A, 0xF4B2, 0x8E60, 0xF4B3, 0x965F, 0xF4B4, 0x96BB,
+	0xF4B5, 0x4EDF, 0xF4B6, 0x5343, 0xF4B7, 0x5598, 0xF4B8, 0x5929,	0xF4B9, 0x5DDD, 0xF4BA, 0x64C5, 0xF4BB, 0x6CC9, 0xF4BC, 0x6DFA,
+	0xF4BD, 0x7394, 0xF4BE, 0x7A7F, 0xF4BF, 0x821B, 0xF4C0, 0x85A6,	0xF4C1, 0x8CE4, 0xF4C2, 0x8E10, 0xF4C3, 0x9077, 0xF4C4, 0x91E7,
+	0xF4C5, 0x95E1, 0xF4C6, 0x9621, 0xF4C7, 0x97C6, 0xF4C8, 0x51F8,	0xF4C9, 0x54F2, 0xF4CA, 0x5586, 0xF4CB, 0x5FB9, 0xF4CC, 0x64A4,
+	0xF4CD, 0x6F88, 0xF4CE, 0x7DB4, 0xF4CF, 0x8F1F, 0xF4D0, 0x8F4D,	0xF4D1, 0x9435, 0xF4D2, 0x50C9, 0xF4D3, 0x5C16, 0xF4D4, 0x6CBE,
+	0xF4D5, 0x6DFB, 0xF4D6, 0x751B, 0xF4D7, 0x77BB, 0xF4D8, 0x7C3D,	0xF4D9, 0x7C64, 0xF4DA, 0x8A79, 0xF4DB, 0x8AC2, 0xF4DC, 0x581E,
+	0xF4DD, 0x59BE, 0xF4DE, 0x5E16, 0xF4DF, 0x6377, 0xF4E0, 0x7252,	0xF4E1, 0x758A, 0xF4E2, 0x776B, 0xF4E3, 0x8ADC, 0xF4E4, 0x8CBC,
+	0xF4E5, 0x8F12, 0xF4E6, 0x5EF3, 0xF4E7, 0x6674, 0xF4E8, 0x6DF8,	0xF4E9, 0x807D, 0xF4EA, 0x83C1, 0xF4EB, 0x8ACB, 0xF4EC, 0x9751,
+	0xF4ED, 0x9BD6, 0xF4EE, 0xFA00, 0xF4EF, 0x5243, 0xF4F0, 0x66FF,	0xF4F1, 0x6D95, 0xF4F2, 0x6EEF, 0xF4F3, 0x7DE0, 0xF4F4, 0x8AE6,
+	0xF4F5, 0x902E, 0xF4F6, 0x905E, 0xF4F7, 0x9AD4, 0xF4F8, 0x521D,	0xF4F9, 0x527F, 0xF4FA, 0x54E8, 0xF4FB, 0x6194, 0xF4FC, 0x6284,
+	0xF4FD, 0x62DB, 0xF4FE, 0x68A2, 0xF5A1, 0x6912, 0xF5A2, 0x695A,	0xF5A3, 0x6A35, 0xF5A4, 0x7092, 0xF5A5, 0x7126, 0xF5A6, 0x785D,
+	0xF5A7, 0x7901, 0xF5A8, 0x790E, 0xF5A9, 0x79D2, 0xF5AA, 0x7A0D,	0xF5AB, 0x8096, 0xF5AC, 0x8278, 0xF5AD, 0x82D5, 0xF5AE, 0x8349,
+	0xF5AF, 0x8549, 0xF5B0, 0x8C82, 0xF5B1, 0x8D85, 0xF5B2, 0x9162,	0xF5B3, 0x918B, 0xF5B4, 0x91AE, 0xF5B5, 0x4FC3, 0xF5B6, 0x56D1,
+	0xF5B7, 0x71ED, 0xF5B8, 0x77D7, 0xF5B9, 0x8700, 0xF5BA, 0x89F8,	0xF5BB, 0x5BF8, 0xF5BC, 0x5FD6, 0xF5BD, 0x6751, 0xF5BE, 0x90A8,
+	0xF5BF, 0x53E2, 0xF5C0, 0x585A, 0xF5C1, 0x5BF5, 0xF5C2, 0x60A4,	0xF5C3, 0x6181, 0xF5C4, 0x6460, 0xF5C5, 0x7E3D, 0xF5C6, 0x8070,
+	0xF5C7, 0x8525, 0xF5C8, 0x9283, 0xF5C9, 0x64AE, 0xF5CA, 0x50AC,	0xF5CB, 0x5D14, 0xF5CC, 0x6700, 0xF5CD, 0x589C, 0xF5CE, 0x62BD,
+	0xF5CF, 0x63A8, 0xF5D0, 0x690E, 0xF5D1, 0x6978, 0xF5D2, 0x6A1E,	0xF5D3, 0x6E6B, 0xF5D4, 0x76BA, 0xF5D5, 0x79CB, 0xF5D6, 0x82BB,
+	0xF5D7, 0x8429, 0xF5D8, 0x8ACF, 0xF5D9, 0x8DA8, 0xF5DA, 0x8FFD,	0xF5DB, 0x9112, 0xF5DC, 0x914B, 0xF5DD, 0x919C, 0xF5DE, 0x9310,
+	0xF5DF, 0x9318, 0xF5E0, 0x939A, 0xF5E1, 0x96DB, 0xF5E2, 0x9A36,	0xF5E3, 0x9C0D, 0xF5E4, 0x4E11, 0xF5E5, 0x755C, 0xF5E6, 0x795D,
+	0xF5E7, 0x7AFA, 0xF5E8, 0x7B51, 0xF5E9, 0x7BC9, 0xF5EA, 0x7E2E,	0xF5EB, 0x84C4, 0xF5EC, 0x8E59, 0xF5ED, 0x8E74, 0xF5EE, 0x8EF8,
+	0xF5EF, 0x9010, 0xF5F0, 0x6625, 0xF5F1, 0x693F, 0xF5F2, 0x7443,	0xF5F3, 0x51FA, 0xF5F4, 0x672E, 0xF5F5, 0x9EDC, 0xF5F6, 0x5145,
+	0xF5F7, 0x5FE0, 0xF5F8, 0x6C96, 0xF5F9, 0x87F2, 0xF5FA, 0x885D,	0xF5FB, 0x8877, 0xF5FC, 0x60B4, 0xF5FD, 0x81B5, 0xF5FE, 0x8403,
+	0xF6A1, 0x8D05, 0xF6A2, 0x53D6, 0xF6A3, 0x5439, 0xF6A4, 0x5634,	0xF6A5, 0x5A36, 0xF6A6, 0x5C31, 0xF6A7, 0x708A, 0xF6A8, 0x7FE0,
+	0xF6A9, 0x805A, 0xF6AA, 0x8106, 0xF6AB, 0x81ED, 0xF6AC, 0x8DA3,	0xF6AD, 0x9189, 0xF6AE, 0x9A5F, 0xF6AF, 0x9DF2, 0xF6B0, 0x5074,
+	0xF6B1, 0x4EC4, 0xF6B2, 0x53A0, 0xF6B3, 0x60FB, 0xF6B4, 0x6E2C,	0xF6B5, 0x5C64, 0xF6B6, 0x4F88, 0xF6B7, 0x5024, 0xF6B8, 0x55E4,
+	0xF6B9, 0x5CD9, 0xF6BA, 0x5E5F, 0xF6BB, 0x6065, 0xF6BC, 0x6894,	0xF6BD, 0x6CBB, 0xF6BE, 0x6DC4, 0xF6BF, 0x71BE, 0xF6C0, 0x75D4,
+	0xF6C1, 0x75F4, 0xF6C2, 0x7661, 0xF6C3, 0x7A1A, 0xF6C4, 0x7A49,	0xF6C5, 0x7DC7, 0xF6C6, 0x7DFB, 0xF6C7, 0x7F6E, 0xF6C8, 0x81F4,
+	0xF6C9, 0x86A9, 0xF6CA, 0x8F1C, 0xF6CB, 0x96C9, 0xF6CC, 0x99B3,	0xF6CD, 0x9F52, 0xF6CE, 0x5247, 0xF6CF, 0x52C5, 0xF6D0, 0x98ED,
+	0xF6D1, 0x89AA, 0xF6D2, 0x4E03, 0xF6D3, 0x67D2, 0xF6D4, 0x6F06,	0xF6D5, 0x4FB5, 0xF6D6, 0x5BE2, 0xF6D7, 0x6795, 0xF6D8, 0x6C88,
+	0xF6D9, 0x6D78, 0xF6DA, 0x741B, 0xF6DB, 0x7827, 0xF6DC, 0x91DD,	0xF6DD, 0x937C, 0xF6DE, 0x87C4, 0xF6DF, 0x79E4, 0xF6E0, 0x7A31,
+	0xF6E1, 0x5FEB, 0xF6E2, 0x4ED6, 0xF6E3, 0x54A4, 0xF6E4, 0x553E,	0xF6E5, 0x58AE, 0xF6E6, 0x59A5, 0xF6E7, 0x60F0, 0xF6E8, 0x6253,
+	0xF6E9, 0x62D6, 0xF6EA, 0x6736, 0xF6EB, 0x6955, 0xF6EC, 0x8235,	0xF6ED, 0x9640, 0xF6EE, 0x99B1, 0xF6EF, 0x99DD, 0xF6F0, 0x502C,
+	0xF6F1, 0x5353, 0xF6F2, 0x5544, 0xF6F3, 0x577C, 0xF6F4, 0xFA01,	0xF6F5, 0x6258, 0xF6F6, 0xFA02, 0xF6F7, 0x64E2, 0xF6F8, 0x666B,
+	0xF6F9, 0x67DD, 0xF6FA, 0x6FC1, 0xF6FB, 0x6FEF, 0xF6FC, 0x7422,	0xF6FD, 0x7438, 0xF6FE, 0x8A17, 0xF7A1, 0x9438, 0xF7A2, 0x5451,
+	0xF7A3, 0x5606, 0xF7A4, 0x5766, 0xF7A5, 0x5F48, 0xF7A6, 0x619A,	0xF7A7, 0x6B4E, 0xF7A8, 0x7058, 0xF7A9, 0x70AD, 0xF7AA, 0x7DBB,
+	0xF7AB, 0x8A95, 0xF7AC, 0x596A, 0xF7AD, 0x812B, 0xF7AE, 0x63A2,	0xF7AF, 0x7708, 0xF7B0, 0x803D, 0xF7B1, 0x8CAA, 0xF7B2, 0x5854,
+	0xF7B3, 0x642D, 0xF7B4, 0x69BB, 0xF7B5, 0x5B95, 0xF7B6, 0x5E11,	0xF7B7, 0x6E6F, 0xF7B8, 0xFA03, 0xF7B9, 0x8569, 0xF7BA, 0x514C,
+	0xF7BB, 0x53F0, 0xF7BC, 0x592A, 0xF7BD, 0x6020, 0xF7BE, 0x614B,	0xF7BF, 0x6B86, 0xF7C0, 0x6C70, 0xF7C1, 0x6CF0, 0xF7C2, 0x7B1E,
+	0xF7C3, 0x80CE, 0xF7C4, 0x82D4, 0xF7C5, 0x8DC6, 0xF7C6, 0x90B0,	0xF7C7, 0x98B1, 0xF7C8, 0xFA04, 0xF7C9, 0x64C7, 0xF7CA, 0x6FA4,
+	0xF7CB, 0x6491, 0xF7CC, 0x6504, 0xF7CD, 0x514E, 0xF7CE, 0x5410,	0xF7CF, 0x571F, 0xF7D0, 0x8A0E, 0xF7D1, 0x615F, 0xF7D2, 0x6876,
+	0xF7D3, 0xFA05, 0xF7D4, 0x75DB, 0xF7D5, 0x7B52, 0xF7D6, 0x7D71,	0xF7D7, 0x901A, 0xF7D8, 0x5806, 0xF7D9, 0x69CC, 0xF7DA, 0x817F,
+	0xF7DB, 0x892A, 0xF7DC, 0x9000, 0xF7DD, 0x9839, 0xF7DE, 0x5078,	0xF7DF, 0x5957, 0xF7E0, 0x59AC, 0xF7E1, 0x6295, 0xF7E2, 0x900F,
+	0xF7E3, 0x9B2A, 0xF7E4, 0x615D, 0xF7E5, 0x7279, 0xF7E6, 0x95D6,	0xF7E7, 0x5761, 0xF7E8, 0x5A46, 0xF7E9, 0x5DF4, 0xF7EA, 0x628A,
+	0xF7EB, 0x64AD, 0xF7EC, 0x64FA, 0xF7ED, 0x6777, 0xF7EE, 0x6CE2,	0xF7EF, 0x6D3E, 0xF7F0, 0x722C, 0xF7F1, 0x7436, 0xF7F2, 0x7834,
+	0xF7F3, 0x7F77, 0xF7F4, 0x82AD, 0xF7F5, 0x8DDB, 0xF7F6, 0x9817,	0xF7F7, 0x5224, 0xF7F8, 0x5742, 0xF7F9, 0x677F, 0xF7FA, 0x7248,
+	0xF7FB, 0x74E3, 0xF7FC, 0x8CA9, 0xF7FD, 0x8FA6, 0xF7FE, 0x9211,	0xF8A1, 0x962A, 0xF8A2, 0x516B, 0xF8A3, 0x53ED, 0xF8A4, 0x634C,
+	0xF8A5, 0x4F69, 0xF8A6, 0x5504, 0xF8A7, 0x6096, 0xF8A8, 0x6557,	0xF8A9, 0x6C9B, 0xF8AA, 0x6D7F, 0xF8AB, 0x724C, 0xF8AC, 0x72FD,
+	0xF8AD, 0x7A17, 0xF8AE, 0x8987, 0xF8AF, 0x8C9D, 0xF8B0, 0x5F6D,	0xF8B1, 0x6F8E, 0xF8B2, 0x70F9, 0xF8B3, 0x81A8, 0xF8B4, 0x610E,
+	0xF8B5, 0x4FBF, 0xF8B6, 0x504F, 0xF8B7, 0x6241, 0xF8B8, 0x7247,	0xF8B9, 0x7BC7, 0xF8BA, 0x7DE8, 0xF8BB, 0x7FE9, 0xF8BC, 0x904D,
+	0xF8BD, 0x97AD, 0xF8BE, 0x9A19, 0xF8BF, 0x8CB6, 0xF8C0, 0x576A,	0xF8C1, 0x5E73, 0xF8C2, 0x67B0, 0xF8C3, 0x840D, 0xF8C4, 0x8A55,
+	0xF8C5, 0x5420, 0xF8C6, 0x5B16, 0xF8C7, 0x5E63, 0xF8C8, 0x5EE2,	0xF8C9, 0x5F0A, 0xF8CA, 0x6583, 0xF8CB, 0x80BA, 0xF8CC, 0x853D,
+	0xF8CD, 0x9589, 0xF8CE, 0x965B, 0xF8CF, 0x4F48, 0xF8D0, 0x5305,	0xF8D1, 0x530D, 0xF8D2, 0x530F, 0xF8D3, 0x5486, 0xF8D4, 0x54FA,
+	0xF8D5, 0x5703, 0xF8D6, 0x5E03, 0xF8D7, 0x6016, 0xF8D8, 0x629B,	0xF8D9, 0x62B1, 0xF8DA, 0x6355, 0xF8DB, 0xFA06, 0xF8DC, 0x6CE1,
+	0xF8DD, 0x6D66, 0xF8DE, 0x75B1, 0xF8DF, 0x7832, 0xF8E0, 0x80DE,	0xF8E1, 0x812F, 0xF8E2, 0x82DE, 0xF8E3, 0x8461, 0xF8E4, 0x84B2,
+	0xF8E5, 0x888D, 0xF8E6, 0x8912, 0xF8E7, 0x900B, 0xF8E8, 0x92EA,	0xF8E9, 0x98FD, 0xF8EA, 0x9B91, 0xF8EB, 0x5E45, 0xF8EC, 0x66B4,
+	0xF8ED, 0x66DD, 0xF8EE, 0x7011, 0xF8EF, 0x7206, 0xF8F0, 0xFA07,	0xF8F1, 0x4FF5, 0xF8F2, 0x527D, 0xF8F3, 0x5F6A, 0xF8F4, 0x6153,
+	0xF8F5, 0x6753, 0xF8F6, 0x6A19, 0xF8F7, 0x6F02, 0xF8F8, 0x74E2,	0xF8F9, 0x7968, 0xF8FA, 0x8868, 0xF8FB, 0x8C79, 0xF8FC, 0x98C7,
+	0xF8FD, 0x98C4, 0xF8FE, 0x9A43, 0xF9A1, 0x54C1, 0xF9A2, 0x7A1F,	0xF9A3, 0x6953, 0xF9A4, 0x8AF7, 0xF9A5, 0x8C4A, 0xF9A6, 0x98A8,
+	0xF9A7, 0x99AE, 0xF9A8, 0x5F7C, 0xF9A9, 0x62AB, 0xF9AA, 0x75B2,	0xF9AB, 0x76AE, 0xF9AC, 0x88AB, 0xF9AD, 0x907F, 0xF9AE, 0x9642,
+	0xF9AF, 0x5339, 0xF9B0, 0x5F3C, 0xF9B1, 0x5FC5, 0xF9B2, 0x6CCC,	0xF9B3, 0x73CC, 0xF9B4, 0x7562, 0xF9B5, 0x758B, 0xF9B6, 0x7B46,
+	0xF9B7, 0x82FE, 0xF9B8, 0x999D, 0xF9B9, 0x4E4F, 0xF9BA, 0x903C,	0xF9BB, 0x4E0B, 0xF9BC, 0x4F55, 0xF9BD, 0x53A6, 0xF9BE, 0x590F,
+	0xF9BF, 0x5EC8, 0xF9C0, 0x6630, 0xF9C1, 0x6CB3, 0xF9C2, 0x7455,	0xF9C3, 0x8377, 0xF9C4, 0x8766, 0xF9C5, 0x8CC0, 0xF9C6, 0x9050,
+	0xF9C7, 0x971E, 0xF9C8, 0x9C15, 0xF9C9, 0x58D1, 0xF9CA, 0x5B78,	0xF9CB, 0x8650, 0xF9CC, 0x8B14, 0xF9CD, 0x9DB4, 0xF9CE, 0x5BD2,
+	0xF9CF, 0x6068, 0xF9D0, 0x608D, 0xF9D1, 0x65F1, 0xF9D2, 0x6C57,	0xF9D3, 0x6F22, 0xF9D4, 0x6FA3, 0xF9D5, 0x701A, 0xF9D6, 0x7F55,
+	0xF9D7, 0x7FF0, 0xF9D8, 0x9591, 0xF9D9, 0x9592, 0xF9DA, 0x9650,	0xF9DB, 0x97D3, 0xF9DC, 0x5272, 0xF9DD, 0x8F44, 0xF9DE, 0x51FD,
+	0xF9DF, 0x542B, 0xF9E0, 0x54B8, 0xF9E1, 0x5563, 0xF9E2, 0x558A,	0xF9E3, 0x6ABB, 0xF9E4, 0x6DB5, 0xF9E5, 0x7DD8, 0xF9E6, 0x8266,
+	0xF9E7, 0x929C, 0xF9E8, 0x9677, 0xF9E9, 0x9E79, 0xF9EA, 0x5408,	0xF9EB, 0x54C8, 0xF9EC, 0x76D2, 0xF9ED, 0x86E4, 0xF9EE, 0x95A4,
+	0xF9EF, 0x95D4, 0xF9F0, 0x965C, 0xF9F1, 0x4EA2, 0xF9F2, 0x4F09,	0xF9F3, 0x59EE, 0xF9F4, 0x5AE6, 0xF9F5, 0x5DF7, 0xF9F6, 0x6052,
+	0xF9F7, 0x6297, 0xF9F8, 0x676D, 0xF9F9, 0x6841, 0xF9FA, 0x6C86,	0xF9FB, 0x6E2F, 0xF9FC, 0x7F38, 0xF9FD, 0x809B, 0xF9FE, 0x822A,
+	0xFAA1, 0xFA08, 0xFAA2, 0xFA09, 0xFAA3, 0x9805, 0xFAA4, 0x4EA5,	0xFAA5, 0x5055, 0xFAA6, 0x54B3, 0xFAA7, 0x5793, 0xFAA8, 0x595A,
+	0xFAA9, 0x5B69, 0xFAAA, 0x5BB3, 0xFAAB, 0x61C8, 0xFAAC, 0x6977,	0xFAAD, 0x6D77, 0xFAAE, 0x7023, 0xFAAF, 0x87F9, 0xFAB0, 0x89E3,
+	0xFAB1, 0x8A72, 0xFAB2, 0x8AE7, 0xFAB3, 0x9082, 0xFAB4, 0x99ED,	0xFAB5, 0x9AB8, 0xFAB6, 0x52BE, 0xFAB7, 0x6838, 0xFAB8, 0x5016,
+	0xFAB9, 0x5E78, 0xFABA, 0x674F, 0xFABB, 0x8347, 0xFABC, 0x884C,	0xFABD, 0x4EAB, 0xFABE, 0x5411, 0xFABF, 0x56AE, 0xFAC0, 0x73E6,
+	0xFAC1, 0x9115, 0xFAC2, 0x97FF, 0xFAC3, 0x9909, 0xFAC4, 0x9957,	0xFAC5, 0x9999, 0xFAC6, 0x5653, 0xFAC7, 0x589F, 0xFAC8, 0x865B,
+	0xFAC9, 0x8A31, 0xFACA, 0x61B2, 0xFACB, 0x6AF6, 0xFACC, 0x737B,	0xFACD, 0x8ED2, 0xFACE, 0x6B47, 0xFACF, 0x96AA, 0xFAD0, 0x9A57,
+	0xFAD1, 0x5955, 0xFAD2, 0x7200, 0xFAD3, 0x8D6B, 0xFAD4, 0x9769,	0xFAD5, 0x4FD4, 0xFAD6, 0x5CF4, 0xFAD7, 0x5F26, 0xFAD8, 0x61F8,
+	0xFAD9, 0x665B, 0xFADA, 0x6CEB, 0xFADB, 0x70AB, 0xFADC, 0x7384,	0xFADD, 0x73B9, 0xFADE, 0x73FE, 0xFADF, 0x7729, 0xFAE0, 0x774D,
+	0xFAE1, 0x7D43, 0xFAE2, 0x7D62, 0xFAE3, 0x7E23, 0xFAE4, 0x8237,	0xFAE5, 0x8852, 0xFAE6, 0xFA0A, 0xFAE7, 0x8CE2, 0xFAE8, 0x9249,
+	0xFAE9, 0x986F, 0xFAEA, 0x5B51, 0xFAEB, 0x7A74, 0xFAEC, 0x8840,	0xFAED, 0x9801, 0xFAEE, 0x5ACC, 0xFAEF, 0x4FE0, 0xFAF0, 0x5354,
+	0xFAF1, 0x593E, 0xFAF2, 0x5CFD, 0xFAF3, 0x633E, 0xFAF4, 0x6D79,	0xFAF5, 0x72F9, 0xFAF6, 0x8105, 0xFAF7, 0x8107, 0xFAF8, 0x83A2,
+	0xFAF9, 0x92CF, 0xFAFA, 0x9830, 0xFAFB, 0x4EA8, 0xFAFC, 0x5144,	0xFAFD, 0x5211, 0xFAFE, 0x578B, 0xFBA1, 0x5F62, 0xFBA2, 0x6CC2,
+	0xFBA3, 0x6ECE, 0xFBA4, 0x7005, 0xFBA5, 0x7050, 0xFBA6, 0x70AF,	0xFBA7, 0x7192, 0xFBA8, 0x73E9, 0xFBA9, 0x7469, 0xFBAA, 0x834A,
+	0xFBAB, 0x87A2, 0xFBAC, 0x8861, 0xFBAD, 0x9008, 0xFBAE, 0x90A2,	0xFBAF, 0x93A3, 0xFBB0, 0x99A8, 0xFBB1, 0x516E, 0xFBB2, 0x5F57,
+	0xFBB3, 0x60E0, 0xFBB4, 0x6167, 0xFBB5, 0x66B3, 0xFBB6, 0x8559,	0xFBB7, 0x8E4A, 0xFBB8, 0x91AF, 0xFBB9, 0x978B, 0xFBBA, 0x4E4E,
+	0xFBBB, 0x4E92, 0xFBBC, 0x547C, 0xFBBD, 0x58D5, 0xFBBE, 0x58FA,	0xFBBF, 0x597D, 0xFBC0, 0x5CB5, 0xFBC1, 0x5F27, 0xFBC2, 0x6236,
+	0xFBC3, 0x6248, 0xFBC4, 0x660A, 0xFBC5, 0x6667, 0xFBC6, 0x6BEB,	0xFBC7, 0x6D69, 0xFBC8, 0x6DCF, 0xFBC9, 0x6E56, 0xFBCA, 0x6EF8,
+	0xFBCB, 0x6F94, 0xFBCC, 0x6FE0, 0xFBCD, 0x6FE9, 0xFBCE, 0x705D,	0xFBCF, 0x72D0, 0xFBD0, 0x7425, 0xFBD1, 0x745A, 0xFBD2, 0x74E0,
+	0xFBD3, 0x7693, 0xFBD4, 0x795C, 0xFBD5, 0x7CCA, 0xFBD6, 0x7E1E,	0xFBD7, 0x80E1, 0xFBD8, 0x82A6, 0xFBD9, 0x846B, 0xFBDA, 0x84BF,
+	0xFBDB, 0x864E, 0xFBDC, 0x865F, 0xFBDD, 0x8774, 0xFBDE, 0x8B77,	0xFBDF, 0x8C6A, 0xFBE0, 0x93AC, 0xFBE1, 0x9800, 0xFBE2, 0x9865,
+	0xFBE3, 0x60D1, 0xFBE4, 0x6216, 0xFBE5, 0x9177, 0xFBE6, 0x5A5A,	0xFBE7, 0x660F, 0xFBE8, 0x6DF7, 0xFBE9, 0x6E3E, 0xFBEA, 0x743F,
+	0xFBEB, 0x9B42, 0xFBEC, 0x5FFD, 0xFBED, 0x60DA, 0xFBEE, 0x7B0F,	0xFBEF, 0x54C4, 0xFBF0, 0x5F18, 0xFBF1, 0x6C5E, 0xFBF2, 0x6CD3,
+	0xFBF3, 0x6D2A, 0xFBF4, 0x70D8, 0xFBF5, 0x7D05, 0xFBF6, 0x8679,	0xFBF7, 0x8A0C, 0xFBF8, 0x9D3B, 0xFBF9, 0x5316, 0xFBFA, 0x548C,
+	0xFBFB, 0x5B05, 0xFBFC, 0x6A3A, 0xFBFD, 0x706B, 0xFBFE, 0x7575,	0xFCA1, 0x798D, 0xFCA2, 0x79BE, 0xFCA3, 0x82B1, 0xFCA4, 0x83EF,
+	0xFCA5, 0x8A71, 0xFCA6, 0x8B41, 0xFCA7, 0x8CA8, 0xFCA8, 0x9774,	0xFCA9, 0xFA0B, 0xFCAA, 0x64F4, 0xFCAB, 0x652B, 0xFCAC, 0x78BA,
+	0xFCAD, 0x78BB, 0xFCAE, 0x7A6B, 0xFCAF, 0x4E38, 0xFCB0, 0x559A,	0xFCB1, 0x5950, 0xFCB2, 0x5BA6, 0xFCB3, 0x5E7B, 0xFCB4, 0x60A3,
+	0xFCB5, 0x63DB, 0xFCB6, 0x6B61, 0xFCB7, 0x6665, 0xFCB8, 0x6853,	0xFCB9, 0x6E19, 0xFCBA, 0x7165, 0xFCBB, 0x74B0, 0xFCBC, 0x7D08,
+	0xFCBD, 0x9084, 0xFCBE, 0x9A69, 0xFCBF, 0x9C25, 0xFCC0, 0x6D3B,	0xFCC1, 0x6ED1, 0xFCC2, 0x733E, 0xFCC3, 0x8C41, 0xFCC4, 0x95CA,
+	0xFCC5, 0x51F0, 0xFCC6, 0x5E4C, 0xFCC7, 0x5FA8, 0xFCC8, 0x604D,	0xFCC9, 0x60F6, 0xFCCA, 0x6130, 0xFCCB, 0x614C, 0xFCCC, 0x6643,
+	0xFCCD, 0x6644, 0xFCCE, 0x69A5, 0xFCCF, 0x6CC1, 0xFCD0, 0x6E5F,	0xFCD1, 0x6EC9, 0xFCD2, 0x6F62, 0xFCD3, 0x714C, 0xFCD4, 0x749C,
+	0xFCD5, 0x7687, 0xFCD6, 0x7BC1, 0xFCD7, 0x7C27, 0xFCD8, 0x8352,	0xFCD9, 0x8757, 0xFCDA, 0x9051, 0xFCDB, 0x968D, 0xFCDC, 0x9EC3,
+	0xFCDD, 0x532F, 0xFCDE, 0x56DE, 0xFCDF, 0x5EFB, 0xFCE0, 0x5F8A,	0xFCE1, 0x6062, 0xFCE2, 0x6094, 0xFCE3, 0x61F7, 0xFCE4, 0x6666,
+	0xFCE5, 0x6703, 0xFCE6, 0x6A9C, 0xFCE7, 0x6DEE, 0xFCE8, 0x6FAE,	0xFCE9, 0x7070, 0xFCEA, 0x736A, 0xFCEB, 0x7E6A, 0xFCEC, 0x81BE,
+	0xFCED, 0x8334, 0xFCEE, 0x86D4, 0xFCEF, 0x8AA8, 0xFCF0, 0x8CC4,	0xFCF1, 0x5283, 0xFCF2, 0x7372, 0xFCF3, 0x5B96, 0xFCF4, 0x6A6B,
+	0xFCF5, 0x9404, 0xFCF6, 0x54EE, 0xFCF7, 0x5686, 0xFCF8, 0x5B5D,	0xFCF9, 0x6548, 0xFCFA, 0x6585, 0xFCFB, 0x66C9, 0xFCFC, 0x689F,
+	0xFCFD, 0x6D8D, 0xFCFE, 0x6DC6, 0xFDA1, 0x723B, 0xFDA2, 0x80B4,	0xFDA3, 0x9175, 0xFDA4, 0x9A4D, 0xFDA5, 0x4FAF, 0xFDA6, 0x5019,
+	0xFDA7, 0x539A, 0xFDA8, 0x540E, 0xFDA9, 0x543C, 0xFDAA, 0x5589,	0xFDAB, 0x55C5, 0xFDAC, 0x5E3F, 0xFDAD, 0x5F8C, 0xFDAE, 0x673D,
+	0xFDAF, 0x7166, 0xFDB0, 0x73DD, 0xFDB1, 0x9005, 0xFDB2, 0x52DB,	0xFDB3, 0x52F3, 0xFDB4, 0x5864, 0xFDB5, 0x58CE, 0xFDB6, 0x7104,
+	0xFDB7, 0x718F, 0xFDB8, 0x71FB, 0xFDB9, 0x85B0, 0xFDBA, 0x8A13,	0xFDBB, 0x6688, 0xFDBC, 0x85A8, 0xFDBD, 0x55A7, 0xFDBE, 0x6684,
+	0xFDBF, 0x714A, 0xFDC0, 0x8431, 0xFDC1, 0x5349, 0xFDC2, 0x5599,	0xFDC3, 0x6BC1, 0xFDC4, 0x5F59, 0xFDC5, 0x5FBD, 0xFDC6, 0x63EE,
+	0xFDC7, 0x6689, 0xFDC8, 0x7147, 0xFDC9, 0x8AF1, 0xFDCA, 0x8F1D,	0xFDCB, 0x9EBE, 0xFDCC, 0x4F11, 0xFDCD, 0x643A, 0xFDCE, 0x70CB,
+	0xFDCF, 0x7566, 0xFDD0, 0x8667, 0xFDD1, 0x6064, 0xFDD2, 0x8B4E,	0xFDD3, 0x9DF8, 0xFDD4, 0x5147, 0xFDD5, 0x51F6, 0xFDD6, 0x5308,
+	0xFDD7, 0x6D36, 0xFDD8, 0x80F8, 0xFDD9, 0x9ED1, 0xFDDA, 0x6615,	0xFDDB, 0x6B23, 0xFDDC, 0x7098, 0xFDDD, 0x75D5, 0xFDDE, 0x5403,
+	0xFDDF, 0x5C79, 0xFDE0, 0x7D07, 0xFDE1, 0x8A16, 0xFDE2, 0x6B20,	0xFDE3, 0x6B3D, 0xFDE4, 0x6B46, 0xFDE5, 0x5438, 0xFDE6, 0x6070,
+	0xFDE7, 0x6D3D, 0xFDE8, 0x7FD5, 0xFDE9, 0x8208, 0xFDEA, 0x50D6,	0xFDEB, 0x51DE, 0xFDEC, 0x559C, 0xFDED, 0x566B, 0xFDEE, 0x56CD,
+	0xFDEF, 0x59EC, 0xFDF0, 0x5B09, 0xFDF1, 0x5E0C, 0xFDF2, 0x6199,	0xFDF3, 0x6198, 0xFDF4, 0x6231, 0xFDF5, 0x665E, 0xFDF6, 0x66E6,
+	0xFDF7, 0x7199, 0xFDF8, 0x71B9, 0xFDF9, 0x71BA, 0xFDFA, 0x72A7,	0xFDFB, 0x79A7, 0xFDFC, 0x7A00, 0xFDFD, 0x7FB2, 0xFDFE, 0x8A70,
+	0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 950 || FF_CODE_PAGE == 0	/* Traditional Chinese */
+static const WCHAR uni2oem950[] = {	/* Unicode --> Big5 pairs */
+	0x00A7, 0xA1B1, 0x00AF, 0xA1C2, 0x00B0, 0xA258, 0x00B1, 0xA1D3,	0x00B7, 0xA150, 0x00D7, 0xA1D1, 0x00F7, 0xA1D2, 0x02C7, 0xA3BE,
+	0x02C9, 0xA3BC, 0x02CA, 0xA3BD, 0x02CB, 0xA3BF, 0x02CD, 0xA1C5,	0x02D9, 0xA3BB, 0x0391, 0xA344, 0x0392, 0xA345, 0x0393, 0xA346,
+	0x0394, 0xA347, 0x0395, 0xA348, 0x0396, 0xA349, 0x0397, 0xA34A,	0x0398, 0xA34B, 0x0399, 0xA34C, 0x039A, 0xA34D, 0x039B, 0xA34E,
+	0x039C, 0xA34F, 0x039D, 0xA350, 0x039E, 0xA351, 0x039F, 0xA352,	0x03A0, 0xA353, 0x03A1, 0xA354, 0x03A3, 0xA355, 0x03A4, 0xA356,
+	0x03A5, 0xA357, 0x03A6, 0xA358, 0x03A7, 0xA359, 0x03A8, 0xA35A,	0x03A9, 0xA35B, 0x03B1, 0xA35C, 0x03B2, 0xA35D, 0x03B3, 0xA35E,
+	0x03B4, 0xA35F, 0x03B5, 0xA360, 0x03B6, 0xA361, 0x03B7, 0xA362,	0x03B8, 0xA363, 0x03B9, 0xA364, 0x03BA, 0xA365, 0x03BB, 0xA366,
+	0x03BC, 0xA367, 0x03BD, 0xA368, 0x03BE, 0xA369, 0x03BF, 0xA36A,	0x03C0, 0xA36B, 0x03C1, 0xA36C, 0x03C3, 0xA36D, 0x03C4, 0xA36E,
+	0x03C5, 0xA36F, 0x03C6, 0xA370, 0x03C7, 0xA371, 0x03C8, 0xA372,	0x03C9, 0xA373, 0x2013, 0xA156, 0x2014, 0xA158, 0x2018, 0xA1A5,
+	0x2019, 0xA1A6, 0x201C, 0xA1A7, 0x201D, 0xA1A8, 0x2025, 0xA14C,	0x2026, 0xA14B, 0x2027, 0xA145, 0x2032, 0xA1AC, 0x2035, 0xA1AB,
+	0x203B, 0xA1B0, 0x20AC, 0xA3E1, 0x2103, 0xA24A, 0x2105, 0xA1C1,	0x2109, 0xA24B, 0x2160, 0xA2B9, 0x2161, 0xA2BA, 0x2162, 0xA2BB,
+	0x2163, 0xA2BC, 0x2164, 0xA2BD, 0x2165, 0xA2BE, 0x2166, 0xA2BF,	0x2167, 0xA2C0, 0x2168, 0xA2C1, 0x2169, 0xA2C2, 0x2190, 0xA1F6,
+	0x2191, 0xA1F4, 0x2192, 0xA1F7, 0x2193, 0xA1F5, 0x2196, 0xA1F8,	0x2197, 0xA1F9, 0x2198, 0xA1FB, 0x2199, 0xA1FA, 0x2215, 0xA241,
+	0x221A, 0xA1D4, 0x221E, 0xA1DB, 0x221F, 0xA1E8, 0x2220, 0xA1E7,	0x2223, 0xA1FD, 0x2225, 0xA1FC, 0x2229, 0xA1E4, 0x222A, 0xA1E5,
+	0x222B, 0xA1EC, 0x222E, 0xA1ED, 0x2234, 0xA1EF, 0x2235, 0xA1EE,	0x2252, 0xA1DC, 0x2260, 0xA1DA, 0x2261, 0xA1DD, 0x2266, 0xA1D8,
+	0x2267, 0xA1D9, 0x2295, 0xA1F2, 0x2299, 0xA1F3, 0x22A5, 0xA1E6,	0x22BF, 0xA1E9, 0x2500, 0xA277, 0x2502, 0xA278, 0x250C, 0xA27A,
+	0x2510, 0xA27B, 0x2514, 0xA27C, 0x2518, 0xA27D, 0x251C, 0xA275,	0x2524, 0xA274, 0x252C, 0xA273, 0x2534, 0xA272, 0x253C, 0xA271,
+	0x2550, 0xA2A4, 0x2550, 0xF9F9, 0x2551, 0xF9F8, 0x2552, 0xF9E6,	0x2553, 0xF9EF, 0x2554, 0xF9DD, 0x2555, 0xF9E8, 0x2556, 0xF9F1,
+	0x2557, 0xF9DF, 0x2558, 0xF9EC, 0x2559, 0xF9F5, 0x255A, 0xF9E3,	0x255B, 0xF9EE, 0x255C, 0xF9F7, 0x255D, 0xF9E5, 0x255E, 0xA2A5,
+	0x255E, 0xF9E9, 0x255F, 0xF9F2, 0x2560, 0xF9E0, 0x2561, 0xA2A7,	0x2561, 0xF9EB, 0x2562, 0xF9F4, 0x2563, 0xF9E2, 0x2564, 0xF9E7,
+	0x2565, 0xF9F0, 0x2566, 0xF9DE, 0x2567, 0xF9ED, 0x2568, 0xF9F6,	0x2569, 0xF9E4, 0x256A, 0xA2A6, 0x256A, 0xF9EA, 0x256B, 0xF9F3,
+	0x256C, 0xF9E1, 0x256D, 0xA27E, 0x256D, 0xF9FA, 0x256E, 0xA2A1,	0x256E, 0xF9FB, 0x256F, 0xA2A3, 0x256F, 0xF9FD, 0x2570, 0xA2A2,
+	0x2570, 0xF9FC, 0x2571, 0xA2AC, 0x2572, 0xA2AD, 0x2573, 0xA2AE,	0x2574, 0xA15A, 0x2581, 0xA262, 0x2582, 0xA263, 0x2583, 0xA264,
+	0x2584, 0xA265, 0x2585, 0xA266, 0x2586, 0xA267, 0x2587, 0xA268,	0x2588, 0xA269, 0x2589, 0xA270, 0x258A, 0xA26F, 0x258B, 0xA26E,
+	0x258C, 0xA26D, 0x258D, 0xA26C, 0x258E, 0xA26B, 0x258F, 0xA26A,	0x2593, 0xF9FE, 0x2594, 0xA276, 0x2595, 0xA279, 0x25A0, 0xA1BD,
+	0x25A1, 0xA1BC, 0x25B2, 0xA1B6, 0x25B3, 0xA1B5, 0x25BC, 0xA1BF,	0x25BD, 0xA1BE, 0x25C6, 0xA1BB, 0x25C7, 0xA1BA, 0x25CB, 0xA1B3,
+	0x25CE, 0xA1B7, 0x25CF, 0xA1B4, 0x25E2, 0xA2A8, 0x25E3, 0xA2A9,	0x25E4, 0xA2AB, 0x25E5, 0xA2AA, 0x2605, 0xA1B9, 0x2606, 0xA1B8,
+	0x2640, 0xA1F0, 0x2642, 0xA1F1, 0x3000, 0xA140, 0x3001, 0xA142,	0x3002, 0xA143, 0x3003, 0xA1B2, 0x3008, 0xA171, 0x3009, 0xA172,
+	0x300A, 0xA16D, 0x300B, 0xA16E, 0x300C, 0xA175, 0x300D, 0xA176,	0x300E, 0xA179, 0x300F, 0xA17A, 0x3010, 0xA169, 0x3011, 0xA16A,
+	0x3012, 0xA245, 0x3014, 0xA165, 0x3015, 0xA166, 0x301D, 0xA1A9,	0x301E, 0xA1AA, 0x3021, 0xA2C3, 0x3022, 0xA2C4, 0x3023, 0xA2C5,
+	0x3024, 0xA2C6, 0x3025, 0xA2C7, 0x3026, 0xA2C8, 0x3027, 0xA2C9,	0x3028, 0xA2CA, 0x3029, 0xA2CB, 0x3105, 0xA374, 0x3106, 0xA375,
+	0x3107, 0xA376, 0x3108, 0xA377, 0x3109, 0xA378, 0x310A, 0xA379,	0x310B, 0xA37A, 0x310C, 0xA37B, 0x310D, 0xA37C, 0x310E, 0xA37D,
+	0x310F, 0xA37E, 0x3110, 0xA3A1, 0x3111, 0xA3A2, 0x3112, 0xA3A3,	0x3113, 0xA3A4, 0x3114, 0xA3A5, 0x3115, 0xA3A6, 0x3116, 0xA3A7,
+	0x3117, 0xA3A8, 0x3118, 0xA3A9, 0x3119, 0xA3AA, 0x311A, 0xA3AB,	0x311B, 0xA3AC, 0x311C, 0xA3AD, 0x311D, 0xA3AE, 0x311E, 0xA3AF,
+	0x311F, 0xA3B0, 0x3120, 0xA3B1, 0x3121, 0xA3B2, 0x3122, 0xA3B3,	0x3123, 0xA3B4, 0x3124, 0xA3B5, 0x3125, 0xA3B6, 0x3126, 0xA3B7,
+	0x3127, 0xA3B8, 0x3128, 0xA3B9, 0x3129, 0xA3BA, 0x32A3, 0xA1C0,	0x338E, 0xA255, 0x338F, 0xA256, 0x339C, 0xA250, 0x339D, 0xA251,
+	0x339E, 0xA252, 0x33A1, 0xA254, 0x33C4, 0xA257, 0x33CE, 0xA253,	0x33D1, 0xA1EB, 0x33D2, 0xA1EA, 0x33D5, 0xA24F, 0x4E00, 0xA440,
+	0x4E01, 0xA442, 0x4E03, 0xA443, 0x4E07, 0xC945, 0x4E08, 0xA456,	0x4E09, 0xA454, 0x4E0A, 0xA457, 0x4E0B, 0xA455, 0x4E0C, 0xC946,
+	0x4E0D, 0xA4A3, 0x4E0E, 0xC94F, 0x4E0F, 0xC94D, 0x4E10, 0xA4A2,	0x4E11, 0xA4A1, 0x4E14, 0xA542, 0x4E15, 0xA541, 0x4E16, 0xA540,
+	0x4E18, 0xA543, 0x4E19, 0xA4FE, 0x4E1E, 0xA5E0, 0x4E1F, 0xA5E1,	0x4E26, 0xA8C3, 0x4E2B, 0xA458, 0x4E2D, 0xA4A4, 0x4E2E, 0xC950,
+	0x4E30, 0xA4A5, 0x4E31, 0xC963, 0x4E32, 0xA6EA, 0x4E33, 0xCBB1,	0x4E38, 0xA459, 0x4E39, 0xA4A6, 0x4E3B, 0xA544, 0x4E3C, 0xC964,
+	0x4E42, 0xC940, 0x4E43, 0xA444, 0x4E45, 0xA45B, 0x4E47, 0xC947,	0x4E48, 0xA45C, 0x4E4B, 0xA4A7, 0x4E4D, 0xA545, 0x4E4E, 0xA547,
+	0x4E4F, 0xA546, 0x4E52, 0xA5E2, 0x4E53, 0xA5E3, 0x4E56, 0xA8C4,	0x4E58, 0xADBC, 0x4E59, 0xA441, 0x4E5C, 0xC941, 0x4E5D, 0xA445,
+	0x4E5E, 0xA45E, 0x4E5F, 0xA45D, 0x4E69, 0xA5E4, 0x4E73, 0xA8C5,	0x4E7E, 0xB0AE, 0x4E7F, 0xD44B, 0x4E82, 0xB6C3, 0x4E83, 0xDCB1,
+	0x4E84, 0xDCB2, 0x4E86, 0xA446, 0x4E88, 0xA4A9, 0x4E8B, 0xA8C6,	0x4E8C, 0xA447, 0x4E8D, 0xC948, 0x4E8E, 0xA45F, 0x4E91, 0xA4AA,
+	0x4E92, 0xA4AC, 0x4E93, 0xC951, 0x4E94, 0xA4AD, 0x4E95, 0xA4AB,	0x4E99, 0xA5E5, 0x4E9B, 0xA8C7, 0x4E9E, 0xA8C8, 0x4E9F, 0xAB45,
+	0x4EA1, 0xA460, 0x4EA2, 0xA4AE, 0x4EA4, 0xA5E6, 0x4EA5, 0xA5E8,	0x4EA6, 0xA5E7, 0x4EA8, 0xA6EB, 0x4EAB, 0xA8C9, 0x4EAC, 0xA8CA,
+	0x4EAD, 0xAB46, 0x4EAE, 0xAB47, 0x4EB3, 0xADBD, 0x4EB6, 0xDCB3,	0x4EB9, 0xF6D6, 0x4EBA, 0xA448, 0x4EC0, 0xA4B0, 0x4EC1, 0xA4AF,
+	0x4EC2, 0xC952, 0x4EC3, 0xA4B1, 0x4EC4, 0xA4B7, 0x4EC6, 0xA4B2,	0x4EC7, 0xA4B3, 0x4EC8, 0xC954, 0x4EC9, 0xC953, 0x4ECA, 0xA4B5,
+	0x4ECB, 0xA4B6, 0x4ECD, 0xA4B4, 0x4ED4, 0xA54A, 0x4ED5, 0xA54B,	0x4ED6, 0xA54C, 0x4ED7, 0xA54D, 0x4ED8, 0xA549, 0x4ED9, 0xA550,
+	0x4EDA, 0xC96A, 0x4EDC, 0xC966, 0x4EDD, 0xC969, 0x4EDE, 0xA551,	0x4EDF, 0xA561, 0x4EE1, 0xC968, 0x4EE3, 0xA54E, 0x4EE4, 0xA54F,
+	0x4EE5, 0xA548, 0x4EE8, 0xC965, 0x4EE9, 0xC967, 0x4EF0, 0xA5F5,	0x4EF1, 0xC9B0, 0x4EF2, 0xA5F2, 0x4EF3, 0xA5F6, 0x4EF4, 0xC9BA,
+	0x4EF5, 0xC9AE, 0x4EF6, 0xA5F3, 0x4EF7, 0xC9B2, 0x4EFB, 0xA5F4,	0x4EFD, 0xA5F7, 0x4EFF, 0xA5E9, 0x4F00, 0xC9B1, 0x4F01, 0xA5F8,
+	0x4F02, 0xC9B5, 0x4F04, 0xC9B9, 0x4F05, 0xC9B6, 0x4F08, 0xC9B3,	0x4F09, 0xA5EA, 0x4F0A, 0xA5EC, 0x4F0B, 0xA5F9, 0x4F0D, 0xA5EE,
+	0x4F0E, 0xC9AB, 0x4F0F, 0xA5F1, 0x4F10, 0xA5EF, 0x4F11, 0xA5F0,	0x4F12, 0xC9BB, 0x4F13, 0xC9B8, 0x4F14, 0xC9AF, 0x4F15, 0xA5ED,
+	0x4F18, 0xC9AC, 0x4F19, 0xA5EB, 0x4F1D, 0xC9B4, 0x4F22, 0xC9B7,	0x4F2C, 0xC9AD, 0x4F2D, 0xCA66, 0x4F2F, 0xA742, 0x4F30, 0xA6F4,
+	0x4F33, 0xCA67, 0x4F34, 0xA6F1, 0x4F36, 0xA744, 0x4F38, 0xA6F9,	0x4F3A, 0xA6F8, 0x4F3B, 0xCA5B, 0x4F3C, 0xA6FC, 0x4F3D, 0xA6F7,
+	0x4F3E, 0xCA60, 0x4F3F, 0xCA68, 0x4F41, 0xCA64, 0x4F43, 0xA6FA,	0x4F46, 0xA6FD, 0x4F47, 0xA6EE, 0x4F48, 0xA747, 0x4F49, 0xCA5D,
+	0x4F4C, 0xCBBD, 0x4F4D, 0xA6EC, 0x4F4E, 0xA743, 0x4F4F, 0xA6ED,	0x4F50, 0xA6F5, 0x4F51, 0xA6F6, 0x4F52, 0xCA62, 0x4F53, 0xCA5E,
+	0x4F54, 0xA6FB, 0x4F55, 0xA6F3, 0x4F56, 0xCA5A, 0x4F57, 0xA6EF,	0x4F58, 0xCA65, 0x4F59, 0xA745, 0x4F5A, 0xA748, 0x4F5B, 0xA6F2,
+	0x4F5C, 0xA740, 0x4F5D, 0xA746, 0x4F5E, 0xA6F0, 0x4F5F, 0xCA63,	0x4F60, 0xA741, 0x4F61, 0xCA69, 0x4F62, 0xCA5C, 0x4F63, 0xA6FE,
+	0x4F64, 0xCA5F, 0x4F67, 0xCA61, 0x4F69, 0xA8D8, 0x4F6A, 0xCBBF,	0x4F6B, 0xCBCB, 0x4F6C, 0xA8D0, 0x4F6E, 0xCBCC, 0x4F6F, 0xA8CB,
+	0x4F70, 0xA8D5, 0x4F73, 0xA8CE, 0x4F74, 0xCBB9, 0x4F75, 0xA8D6,	0x4F76, 0xCBB8, 0x4F77, 0xCBBC, 0x4F78, 0xCBC3, 0x4F79, 0xCBC1,
+	0x4F7A, 0xA8DE, 0x4F7B, 0xA8D9, 0x4F7C, 0xCBB3, 0x4F7D, 0xCBB5,	0x4F7E, 0xA8DB, 0x4F7F, 0xA8CF, 0x4F80, 0xCBB6, 0x4F81, 0xCBC2,
+	0x4F82, 0xCBC9, 0x4F83, 0xA8D4, 0x4F84, 0xCBBB, 0x4F85, 0xCBB4,	0x4F86, 0xA8D3, 0x4F87, 0xCBB7, 0x4F88, 0xA8D7, 0x4F89, 0xCBBA,
+	0x4F8B, 0xA8D2, 0x4F8D, 0xA8CD, 0x4F8F, 0xA8DC, 0x4F90, 0xCBC4,	0x4F91, 0xA8DD, 0x4F92, 0xCBC8, 0x4F94, 0xCBC6, 0x4F95, 0xCBCA,
+	0x4F96, 0xA8DA, 0x4F97, 0xCBBE, 0x4F98, 0xCBB2, 0x4F9A, 0xCBC0,	0x4F9B, 0xA8D1, 0x4F9C, 0xCBC5, 0x4F9D, 0xA8CC, 0x4F9E, 0xCBC7,
+	0x4FAE, 0xAB56, 0x4FAF, 0xAB4A, 0x4FB2, 0xCDE0, 0x4FB3, 0xCDE8,	0x4FB5, 0xAB49, 0x4FB6, 0xAB51, 0x4FB7, 0xAB5D, 0x4FB9, 0xCDEE,
+	0x4FBA, 0xCDEC, 0x4FBB, 0xCDE7, 0x4FBF, 0xAB4B, 0x4FC0, 0xCDED,	0x4FC1, 0xCDE3, 0x4FC2, 0xAB59, 0x4FC3, 0xAB50, 0x4FC4, 0xAB58,
+	0x4FC5, 0xCDDE, 0x4FC7, 0xCDEA, 0x4FC9, 0xCDE1, 0x4FCA, 0xAB54,	0x4FCB, 0xCDE2, 0x4FCD, 0xCDDD, 0x4FCE, 0xAB5B, 0x4FCF, 0xAB4E,
+	0x4FD0, 0xAB57, 0x4FD1, 0xAB4D, 0x4FD3, 0xCDDF, 0x4FD4, 0xCDE4,	0x4FD6, 0xCDEB, 0x4FD7, 0xAB55, 0x4FD8, 0xAB52, 0x4FD9, 0xCDE6,
+	0x4FDA, 0xAB5A, 0x4FDB, 0xCDE9, 0x4FDC, 0xCDE5, 0x4FDD, 0xAB4F,	0x4FDE, 0xAB5C, 0x4FDF, 0xAB53, 0x4FE0, 0xAB4C, 0x4FE1, 0xAB48,
+	0x4FEC, 0xCDEF, 0x4FEE, 0xADD7, 0x4FEF, 0xADC1, 0x4FF1, 0xADD1,	0x4FF3, 0xADD6, 0x4FF4, 0xD0D0, 0x4FF5, 0xD0CF, 0x4FF6, 0xD0D4,
+	0x4FF7, 0xD0D5, 0x4FF8, 0xADC4, 0x4FFA, 0xADCD, 0x4FFE, 0xADDA,	0x5000, 0xADCE, 0x5005, 0xD0C9, 0x5006, 0xADC7, 0x5007, 0xD0CA,
+	0x5009, 0xADDC, 0x500B, 0xADD3, 0x500C, 0xADBE, 0x500D, 0xADBF,	0x500E, 0xD0DD, 0x500F, 0xB0BF, 0x5011, 0xADCC, 0x5012, 0xADCB,
+	0x5013, 0xD0CB, 0x5014, 0xADCF, 0x5015, 0xD45B, 0x5016, 0xADC6,	0x5017, 0xD0D6, 0x5018, 0xADD5, 0x5019, 0xADD4, 0x501A, 0xADCA,
+	0x501B, 0xD0CE, 0x501C, 0xD0D7, 0x501E, 0xD0C8, 0x501F, 0xADC9,	0x5020, 0xD0D8, 0x5021, 0xADD2, 0x5022, 0xD0CC, 0x5023, 0xADC0,
+	0x5025, 0xADC3, 0x5026, 0xADC2, 0x5027, 0xD0D9, 0x5028, 0xADD0,	0x5029, 0xADC5, 0x502A, 0xADD9, 0x502B, 0xADDB, 0x502C, 0xD0D3,
+	0x502D, 0xADD8, 0x502F, 0xD0DB, 0x5030, 0xD0CD, 0x5031, 0xD0DC,	0x5033, 0xD0D1, 0x5035, 0xD0DA, 0x5037, 0xD0D2, 0x503C, 0xADC8,
+	0x5040, 0xD463, 0x5041, 0xD457, 0x5043, 0xB0B3, 0x5045, 0xD45C,	0x5046, 0xD462, 0x5047, 0xB0B2, 0x5048, 0xD455, 0x5049, 0xB0B6,
+	0x504A, 0xD459, 0x504B, 0xD452, 0x504C, 0xB0B4, 0x504D, 0xD456,	0x504E, 0xB0B9, 0x504F, 0xB0BE, 0x5051, 0xD467, 0x5053, 0xD451,
+	0x5055, 0xB0BA, 0x5057, 0xD466, 0x505A, 0xB0B5, 0x505B, 0xD458,	0x505C, 0xB0B1, 0x505D, 0xD453, 0x505E, 0xD44F, 0x505F, 0xD45D,
+	0x5060, 0xD450, 0x5061, 0xD44E, 0x5062, 0xD45A, 0x5063, 0xD460,	0x5064, 0xD461, 0x5065, 0xB0B7, 0x5068, 0xD85B, 0x5069, 0xD45E,
+	0x506A, 0xD44D, 0x506B, 0xD45F, 0x506D, 0xB0C1, 0x506E, 0xD464,	0x506F, 0xB0C0, 0x5070, 0xD44C, 0x5072, 0xD454, 0x5073, 0xD465,
+	0x5074, 0xB0BC, 0x5075, 0xB0BB, 0x5076, 0xB0B8, 0x5077, 0xB0BD,	0x507A, 0xB0AF, 0x507D, 0xB0B0, 0x5080, 0xB3C8, 0x5082, 0xD85E,
+	0x5083, 0xD857, 0x5085, 0xB3C5, 0x5087, 0xD85F, 0x508B, 0xD855,	0x508C, 0xD858, 0x508D, 0xB3C4, 0x508E, 0xD859, 0x5091, 0xB3C7,
+	0x5092, 0xD85D, 0x5094, 0xD853, 0x5095, 0xD852, 0x5096, 0xB3C9,	0x5098, 0xB3CA, 0x5099, 0xB3C6, 0x509A, 0xB3CB, 0x509B, 0xD851,
+	0x509C, 0xD85C, 0x509D, 0xD85A, 0x509E, 0xD854, 0x50A2, 0xB3C3,	0x50A3, 0xD856, 0x50AC, 0xB6CA, 0x50AD, 0xB6C4, 0x50AE, 0xDCB7,
+	0x50AF, 0xB6CD, 0x50B0, 0xDCBD, 0x50B1, 0xDCC0, 0x50B2, 0xB6C6,	0x50B3, 0xB6C7, 0x50B4, 0xDCBA, 0x50B5, 0xB6C5, 0x50B6, 0xDCC3,
+	0x50B7, 0xB6CB, 0x50B8, 0xDCC4, 0x50BA, 0xDCBF, 0x50BB, 0xB6CC,	0x50BD, 0xDCB4, 0x50BE, 0xB6C9, 0x50BF, 0xDCB5, 0x50C1, 0xDCBE,
+	0x50C2, 0xDCBC, 0x50C4, 0xDCB8, 0x50C5, 0xB6C8, 0x50C6, 0xDCB6,	0x50C7, 0xB6CE, 0x50C8, 0xDCBB, 0x50C9, 0xDCC2, 0x50CA, 0xDCB9,
+	0x50CB, 0xDCC1, 0x50CE, 0xB9B6, 0x50CF, 0xB9B3, 0x50D1, 0xB9B4,	0x50D3, 0xE0F9, 0x50D4, 0xE0F1, 0x50D5, 0xB9B2, 0x50D6, 0xB9AF,
+	0x50D7, 0xE0F2, 0x50DA, 0xB9B1, 0x50DB, 0xE0F5, 0x50DD, 0xE0F7,	0x50E0, 0xE0FE, 0x50E3, 0xE0FD, 0x50E4, 0xE0F8, 0x50E5, 0xB9AE,
+	0x50E6, 0xE0F0, 0x50E7, 0xB9AC, 0x50E8, 0xE0F3, 0x50E9, 0xB9B7,	0x50EA, 0xE0F6, 0x50EC, 0xE0FA, 0x50ED, 0xB9B0, 0x50EE, 0xB9AD,
+	0x50EF, 0xE0FC, 0x50F0, 0xE0FB, 0x50F1, 0xB9B5, 0x50F3, 0xE0F4,	0x50F5, 0xBBF8, 0x50F6, 0xE4EC, 0x50F8, 0xE4E9, 0x50F9, 0xBBF9,
+	0x50FB, 0xBBF7, 0x50FD, 0xE4F0, 0x50FE, 0xE4ED, 0x50FF, 0xE4E6,	0x5100, 0xBBF6, 0x5102, 0xBBFA, 0x5103, 0xE4E7, 0x5104, 0xBBF5,
+	0x5105, 0xBBFD, 0x5106, 0xE4EA, 0x5107, 0xE4EB, 0x5108, 0xBBFB,	0x5109, 0xBBFC, 0x510A, 0xE4F1, 0x510B, 0xE4EE, 0x510C, 0xE4EF,
+	0x5110, 0xBEAA, 0x5111, 0xE8F8, 0x5112, 0xBEA7, 0x5113, 0xE8F5,	0x5114, 0xBEA9, 0x5115, 0xBEAB, 0x5117, 0xE8F6, 0x5118, 0xBEA8,
+	0x511A, 0xE8F7, 0x511C, 0xE8F4, 0x511F, 0xC076, 0x5120, 0xECBD,	0x5121, 0xC077, 0x5122, 0xECBB, 0x5124, 0xECBC, 0x5125, 0xECBA,
+	0x5126, 0xECB9, 0x5129, 0xECBE, 0x512A, 0xC075, 0x512D, 0xEFB8,	0x512E, 0xEFB9, 0x5130, 0xE4E8, 0x5131, 0xEFB7, 0x5132, 0xC078,
+	0x5133, 0xC35F, 0x5134, 0xF1EB, 0x5135, 0xF1EC, 0x5137, 0xC4D7,	0x5138, 0xC4D8, 0x5139, 0xF5C1, 0x513A, 0xF5C0, 0x513B, 0xC56C,
+	0x513C, 0xC56B, 0x513D, 0xF7D0, 0x513F, 0xA449, 0x5140, 0xA461,	0x5141, 0xA4B9, 0x5143, 0xA4B8, 0x5144, 0xA553, 0x5145, 0xA552,
+	0x5146, 0xA5FC, 0x5147, 0xA5FB, 0x5148, 0xA5FD, 0x5149, 0xA5FA,	0x514B, 0xA74A, 0x514C, 0xA749, 0x514D, 0xA74B, 0x5152, 0xA8E0,
+	0x5154, 0xA8DF, 0x5155, 0xA8E1, 0x5157, 0xAB5E, 0x5159, 0xA259,	0x515A, 0xD0DE, 0x515B, 0xA25A, 0x515C, 0xB0C2, 0x515D, 0xA25C,
+	0x515E, 0xA25B, 0x515F, 0xD860, 0x5161, 0xA25D, 0x5162, 0xB9B8,	0x5163, 0xA25E, 0x5165, 0xA44A, 0x5167, 0xA4BA, 0x5168, 0xA5FE,
+	0x5169, 0xA8E2, 0x516B, 0xA44B, 0x516C, 0xA4BD, 0x516D, 0xA4BB,	0x516E, 0xA4BC, 0x5171, 0xA640, 0x5175, 0xA74C, 0x5176, 0xA8E4,
+	0x5177, 0xA8E3, 0x5178, 0xA8E5, 0x517C, 0xADDD, 0x5180, 0xBEAC,	0x5187, 0xC94E, 0x5189, 0xA554, 0x518A, 0xA555, 0x518D, 0xA641,
+	0x518F, 0xCA6A, 0x5191, 0xAB60, 0x5192, 0xAB5F, 0x5193, 0xD0E0,	0x5194, 0xD0DF, 0x5195, 0xB0C3, 0x5197, 0xA4BE, 0x5198, 0xC955,
+	0x519E, 0xCBCD, 0x51A0, 0xAB61, 0x51A2, 0xADE0, 0x51A4, 0xADDE,	0x51A5, 0xADDF, 0x51AA, 0xBEAD, 0x51AC, 0xA556, 0x51B0, 0xA642,
+	0x51B1, 0xC9BC, 0x51B6, 0xA74D, 0x51B7, 0xA74E, 0x51B9, 0xCA6B,	0x51BC, 0xCBCE, 0x51BD, 0xA8E6, 0x51BE, 0xCBCF, 0x51C4, 0xD0E2,
+	0x51C5, 0xD0E3, 0x51C6, 0xADE3, 0x51C8, 0xD0E4, 0x51CA, 0xD0E1,	0x51CB, 0xADE4, 0x51CC, 0xADE2, 0x51CD, 0xADE1, 0x51CE, 0xD0E5,
+	0x51D0, 0xD468, 0x51D4, 0xD861, 0x51D7, 0xDCC5, 0x51D8, 0xE140,	0x51DC, 0xBBFE, 0x51DD, 0xBEAE, 0x51DE, 0xE8F9, 0x51E0, 0xA44C,
+	0x51E1, 0xA45A, 0x51F0, 0xB0C4, 0x51F1, 0xB3CD, 0x51F3, 0xB9B9,	0x51F5, 0xC942, 0x51F6, 0xA4BF, 0x51F8, 0xA559, 0x51F9, 0xA557,
+	0x51FA, 0xA558, 0x51FD, 0xA8E7, 0x5200, 0xA44D, 0x5201, 0xA44E,	0x5203, 0xA462, 0x5206, 0xA4C0, 0x5207, 0xA4C1, 0x5208, 0xA4C2,
+	0x5209, 0xC9BE, 0x520A, 0xA55A, 0x520C, 0xC96B, 0x520E, 0xA646,	0x5210, 0xC9BF, 0x5211, 0xA644, 0x5212, 0xA645, 0x5213, 0xC9BD,
+	0x5216, 0xA647, 0x5217, 0xA643, 0x521C, 0xCA6C, 0x521D, 0xAAEC,	0x521E, 0xCA6D, 0x5221, 0xCA6E, 0x5224, 0xA750, 0x5225, 0xA74F,
+	0x5228, 0xA753, 0x5229, 0xA751, 0x522A, 0xA752, 0x522E, 0xA8ED,	0x5230, 0xA8EC, 0x5231, 0xCBD4, 0x5232, 0xCBD1, 0x5233, 0xCBD2,
+	0x5235, 0xCBD0, 0x5236, 0xA8EE, 0x5237, 0xA8EA, 0x5238, 0xA8E9,	0x523A, 0xA8EB, 0x523B, 0xA8E8, 0x5241, 0xA8EF, 0x5243, 0xAB63,
+	0x5244, 0xCDF0, 0x5246, 0xCBD3, 0x5247, 0xAB68, 0x5249, 0xCDF1,	0x524A, 0xAB64, 0x524B, 0xAB67, 0x524C, 0xAB66, 0x524D, 0xAB65,
+	0x524E, 0xAB62, 0x5252, 0xD0E8, 0x5254, 0xADE7, 0x5255, 0xD0EB,	0x5256, 0xADE5, 0x525A, 0xD0E7, 0x525B, 0xADE8, 0x525C, 0xADE6,
+	0x525D, 0xADE9, 0x525E, 0xD0E9, 0x525F, 0xD0EA, 0x5261, 0xD0E6,	0x5262, 0xD0EC, 0x5269, 0xB3D1, 0x526A, 0xB0C5, 0x526B, 0xD469,
+	0x526C, 0xD46B, 0x526D, 0xD46A, 0x526E, 0xD46C, 0x526F, 0xB0C6,	0x5272, 0xB3CE, 0x5274, 0xB3CF, 0x5275, 0xB3D0, 0x5277, 0xB6D0,
+	0x5278, 0xDCC7, 0x527A, 0xDCC6, 0x527B, 0xDCC8, 0x527C, 0xDCC9,	0x527D, 0xB6D1, 0x527F, 0xB6CF, 0x5280, 0xE141, 0x5281, 0xE142,
+	0x5282, 0xB9BB, 0x5283, 0xB9BA, 0x5284, 0xE35A, 0x5287, 0xBC40,	0x5288, 0xBC41, 0x5289, 0xBC42, 0x528A, 0xBC44, 0x528B, 0xE4F2,
+	0x528C, 0xE4F3, 0x528D, 0xBC43, 0x5291, 0xBEAF, 0x5293, 0xBEB0,	0x5296, 0xF1ED, 0x5297, 0xF5C3, 0x5298, 0xF5C2, 0x5299, 0xF7D1,
+	0x529B, 0xA44F, 0x529F, 0xA55C, 0x52A0, 0xA55B, 0x52A3, 0xA648,	0x52A6, 0xC9C0, 0x52A9, 0xA755, 0x52AA, 0xA756, 0x52AB, 0xA754,
+	0x52AC, 0xA757, 0x52AD, 0xCA6F, 0x52AE, 0xCA70, 0x52BB, 0xA8F1,	0x52BC, 0xCBD5, 0x52BE, 0xA8F0, 0x52C0, 0xCDF2, 0x52C1, 0xAB6C,
+	0x52C2, 0xCDF3, 0x52C3, 0xAB6B, 0x52C7, 0xAB69, 0x52C9, 0xAB6A,	0x52CD, 0xD0ED, 0x52D2, 0xB0C7, 0x52D3, 0xD46E, 0x52D5, 0xB0CA,
+	0x52D6, 0xD46D, 0x52D7, 0xB1E5, 0x52D8, 0xB0C9, 0x52D9, 0xB0C8,	0x52DB, 0xB3D4, 0x52DD, 0xB3D3, 0x52DE, 0xB3D2, 0x52DF, 0xB6D2,
+	0x52E2, 0xB6D5, 0x52E3, 0xB6D6, 0x52E4, 0xB6D4, 0x52E6, 0xB6D3,	0x52E9, 0xE143, 0x52EB, 0xE144, 0x52EF, 0xE4F5, 0x52F0, 0xBC45,
+	0x52F1, 0xE4F4, 0x52F3, 0xBEB1, 0x52F4, 0xECBF, 0x52F5, 0xC079,	0x52F7, 0xF1EE, 0x52F8, 0xC455, 0x52FA, 0xA463, 0x52FB, 0xA4C3,
+	0x52FC, 0xC956, 0x52FE, 0xA4C4, 0x52FF, 0xA4C5, 0x5305, 0xA55D,	0x5306, 0xA55E, 0x5308, 0xA649, 0x5309, 0xCA71, 0x530A, 0xCBD6,
+	0x530B, 0xCBD7, 0x530D, 0xAB6D, 0x530E, 0xD0EE, 0x530F, 0xB0CC,	0x5310, 0xB0CB, 0x5311, 0xD863, 0x5312, 0xD862, 0x5315, 0xA450,
+	0x5316, 0xA4C6, 0x5317, 0xA55F, 0x5319, 0xB0CD, 0x531A, 0xC943,	0x531C, 0xC96C, 0x531D, 0xA560, 0x531F, 0xC9C2, 0x5320, 0xA64B,
+	0x5321, 0xA64A, 0x5322, 0xC9C1, 0x5323, 0xA758, 0x532A, 0xADEA,	0x532D, 0xD46F, 0x532F, 0xB6D7, 0x5330, 0xE145, 0x5331, 0xB9BC,
+	0x5334, 0xE8FA, 0x5337, 0xF3FD, 0x5339, 0xA4C7, 0x533C, 0xCBD8,	0x533D, 0xCDF4, 0x533E, 0xB0D0, 0x533F, 0xB0CE, 0x5340, 0xB0CF,
+	0x5341, 0xA2CC, 0x5341, 0xA451, 0x5343, 0xA464, 0x5344, 0xA2CD,	0x5345, 0xA2CE, 0x5345, 0xA4CA, 0x5347, 0xA4C9, 0x5348, 0xA4C8,
+	0x5349, 0xA563, 0x534A, 0xA562, 0x534C, 0xC96D, 0x534D, 0xC9C3,	0x5351, 0xA8F5, 0x5352, 0xA8F2, 0x5353, 0xA8F4, 0x5354, 0xA8F3,
+	0x5357, 0xAB6E, 0x535A, 0xB3D5, 0x535C, 0xA452, 0x535E, 0xA4CB,	0x5360, 0xA565, 0x5361, 0xA564, 0x5363, 0xCA72, 0x5366, 0xA8F6,
+	0x536C, 0xC957, 0x536E, 0xA567, 0x536F, 0xA566, 0x5370, 0xA64C,	0x5371, 0xA64D, 0x5372, 0xCA73, 0x5373, 0xA759, 0x5375, 0xA75A,
+	0x5377, 0xA8F7, 0x5378, 0xA8F8, 0x5379, 0xA8F9, 0x537B, 0xAB6F,	0x537C, 0xCDF5, 0x537F, 0xADEB, 0x5382, 0xC944, 0x5384, 0xA4CC,
+	0x538A, 0xC9C4, 0x538E, 0xCA74, 0x538F, 0xCA75, 0x5392, 0xCBD9,	0x5394, 0xCBDA, 0x5396, 0xCDF7, 0x5397, 0xCDF6, 0x5398, 0xCDF9,
+	0x5399, 0xCDF8, 0x539A, 0xAB70, 0x539C, 0xD470, 0x539D, 0xADED,	0x539E, 0xD0EF, 0x539F, 0xADEC, 0x53A4, 0xD864, 0x53A5, 0xB3D6,
+	0x53A7, 0xD865, 0x53AC, 0xE146, 0x53AD, 0xB9BD, 0x53B2, 0xBC46,	0x53B4, 0xF1EF, 0x53B9, 0xC958, 0x53BB, 0xA568, 0x53C3, 0xB0D1,
+	0x53C8, 0xA453, 0x53C9, 0xA465, 0x53CA, 0xA4CE, 0x53CB, 0xA4CD,	0x53CD, 0xA4CF, 0x53D4, 0xA8FB, 0x53D6, 0xA8FA, 0x53D7, 0xA8FC,
+	0x53DB, 0xAB71, 0x53DF, 0xADEE, 0x53E1, 0xE8FB, 0x53E2, 0xC24F,	0x53E3, 0xA466, 0x53E4, 0xA56A, 0x53E5, 0xA579, 0x53E6, 0xA574,
+	0x53E8, 0xA56F, 0x53E9, 0xA56E, 0x53EA, 0xA575, 0x53EB, 0xA573,	0x53EC, 0xA56C, 0x53ED, 0xA57A, 0x53EE, 0xA56D, 0x53EF, 0xA569,
+	0x53F0, 0xA578, 0x53F1, 0xA577, 0x53F2, 0xA576, 0x53F3, 0xA56B,	0x53F5, 0xA572, 0x53F8, 0xA571, 0x53FB, 0xA57B, 0x53FC, 0xA570,
+	0x5401, 0xA653, 0x5403, 0xA659, 0x5404, 0xA655, 0x5406, 0xA65B,	0x5407, 0xC9C5, 0x5408, 0xA658, 0x5409, 0xA64E, 0x540A, 0xA651,
+	0x540B, 0xA654, 0x540C, 0xA650, 0x540D, 0xA657, 0x540E, 0xA65A,	0x540F, 0xA64F, 0x5410, 0xA652, 0x5411, 0xA656, 0x5412, 0xA65C,
+	0x5418, 0xCA7E, 0x5419, 0xCA7B, 0x541B, 0xA767, 0x541C, 0xCA7C,	0x541D, 0xA75B, 0x541E, 0xA75D, 0x541F, 0xA775, 0x5420, 0xA770,
+	0x5424, 0xCAA5, 0x5425, 0xCA7D, 0x5426, 0xA75F, 0x5427, 0xA761,	0x5428, 0xCAA4, 0x5429, 0xA768, 0x542A, 0xCA78, 0x542B, 0xA774,
+	0x542C, 0xA776, 0x542D, 0xA75C, 0x542E, 0xA76D, 0x5430, 0xCA76,	0x5431, 0xA773, 0x5433, 0xA764, 0x5435, 0xA76E, 0x5436, 0xA76F,
+	0x5437, 0xCA77, 0x5438, 0xA76C, 0x5439, 0xA76A, 0x543B, 0xA76B,	0x543C, 0xA771, 0x543D, 0xCAA1, 0x543E, 0xA75E, 0x5440, 0xA772,
+	0x5441, 0xCAA3, 0x5442, 0xA766, 0x5443, 0xA763, 0x5445, 0xCA7A,	0x5446, 0xA762, 0x5447, 0xCAA6, 0x5448, 0xA765, 0x544A, 0xA769,
+	0x544E, 0xA760, 0x544F, 0xCAA2, 0x5454, 0xCA79, 0x5460, 0xCBEB,	0x5461, 0xCBEA, 0x5462, 0xA94F, 0x5463, 0xCBED, 0x5464, 0xCBEF,
+	0x5465, 0xCBE4, 0x5466, 0xCBE7, 0x5467, 0xCBEE, 0x5468, 0xA950,	0x546B, 0xCBE1, 0x546C, 0xCBE5, 0x546F, 0xCBE9, 0x5470, 0xCE49,
+	0x5471, 0xA94B, 0x5472, 0xCE4D, 0x5473, 0xA8FD, 0x5474, 0xCBE6,	0x5475, 0xA8FE, 0x5476, 0xA94C, 0x5477, 0xA945, 0x5478, 0xA941,
+	0x547A, 0xCBE2, 0x547B, 0xA944, 0x547C, 0xA949, 0x547D, 0xA952,	0x547E, 0xCBE3, 0x547F, 0xCBDC, 0x5480, 0xA943, 0x5481, 0xCBDD,
+	0x5482, 0xCBDF, 0x5484, 0xA946, 0x5486, 0xA948, 0x5487, 0xCBDB,	0x5488, 0xCBE0, 0x548B, 0xA951, 0x548C, 0xA94D, 0x548D, 0xCBE8,
+	0x548E, 0xA953, 0x5490, 0xA94A, 0x5491, 0xCBDE, 0x5492, 0xA947,	0x5495, 0xA942, 0x5496, 0xA940, 0x5498, 0xCBEC, 0x549A, 0xA94E,
+	0x54A0, 0xCE48, 0x54A1, 0xCDFB, 0x54A2, 0xCE4B, 0x54A5, 0xCDFD,	0x54A6, 0xAB78, 0x54A7, 0xABA8, 0x54A8, 0xAB74, 0x54A9, 0xABA7,
+	0x54AA, 0xAB7D, 0x54AB, 0xABA4, 0x54AC, 0xAB72, 0x54AD, 0xCDFC,	0x54AE, 0xCE43, 0x54AF, 0xABA3, 0x54B0, 0xCE4F, 0x54B1, 0xABA5,
+	0x54B3, 0xAB79, 0x54B6, 0xCE45, 0x54B7, 0xCE42, 0x54B8, 0xAB77,	0x54BA, 0xCDFA, 0x54BB, 0xABA6, 0x54BC, 0xCE4A, 0x54BD, 0xAB7C,
+	0x54BE, 0xCE4C, 0x54BF, 0xABA9, 0x54C0, 0xAB73, 0x54C1, 0xAB7E,	0x54C2, 0xAB7B, 0x54C3, 0xCE40, 0x54C4, 0xABA1, 0x54C5, 0xCE46,
+	0x54C6, 0xCE47, 0x54C7, 0xAB7A, 0x54C8, 0xABA2, 0x54C9, 0xAB76,	0x54CE, 0xAB75, 0x54CF, 0xCDFE, 0x54D6, 0xCE44, 0x54DE, 0xCE4E,
+	0x54E0, 0xD144, 0x54E1, 0xADFB, 0x54E2, 0xD0F1, 0x54E4, 0xD0F6,	0x54E5, 0xADF4, 0x54E6, 0xAE40, 0x54E7, 0xD0F4, 0x54E8, 0xADEF,
+	0x54E9, 0xADF9, 0x54EA, 0xADFE, 0x54EB, 0xD0FB, 0x54ED, 0xADFA,	0x54EE, 0xADFD, 0x54F1, 0xD0FE, 0x54F2, 0xADF5, 0x54F3, 0xD0F5,
+	0x54F7, 0xD142, 0x54F8, 0xD143, 0x54FA, 0xADF7, 0x54FB, 0xD141,	0x54FC, 0xADF3, 0x54FD, 0xAE43, 0x54FF, 0xD0F8, 0x5501, 0xADF1,
+	0x5503, 0xD146, 0x5504, 0xD0F9, 0x5505, 0xD0FD, 0x5506, 0xADF6,	0x5507, 0xAE42, 0x5508, 0xD0FA, 0x5509, 0xADFC, 0x550A, 0xD140,
+	0x550B, 0xD147, 0x550C, 0xD4A1, 0x550E, 0xD145, 0x550F, 0xAE44,	0x5510, 0xADF0, 0x5511, 0xD0FC, 0x5512, 0xD0F3, 0x5514, 0xADF8,
+	0x5517, 0xD0F2, 0x551A, 0xD0F7, 0x5526, 0xD0F0, 0x5527, 0xAE41,	0x552A, 0xD477, 0x552C, 0xB0E4, 0x552D, 0xD4A7, 0x552E, 0xB0E2,
+	0x552F, 0xB0DF, 0x5530, 0xD47C, 0x5531, 0xB0DB, 0x5532, 0xD4A2,	0x5533, 0xB0E6, 0x5534, 0xD476, 0x5535, 0xD47B, 0x5536, 0xD47A,
+	0x5537, 0xADF2, 0x5538, 0xB0E1, 0x5539, 0xD4A5, 0x553B, 0xD4A8,	0x553C, 0xD473, 0x553E, 0xB3E8, 0x5540, 0xD4A9, 0x5541, 0xB0E7,
+	0x5543, 0xB0D9, 0x5544, 0xB0D6, 0x5545, 0xD47E, 0x5546, 0xB0D3,	0x5548, 0xD4A6, 0x554A, 0xB0DA, 0x554B, 0xD4AA, 0x554D, 0xD474,
+	0x554E, 0xD4A4, 0x554F, 0xB0DD, 0x5550, 0xD475, 0x5551, 0xD478,	0x5552, 0xD47D, 0x5555, 0xB0DE, 0x5556, 0xB0DC, 0x5557, 0xB0E8,
+	0x555C, 0xB0E3, 0x555E, 0xB0D7, 0x555F, 0xB1D2, 0x5561, 0xB0D8,	0x5562, 0xD479, 0x5563, 0xB0E5, 0x5564, 0xB0E0, 0x5565, 0xD4A3,
+	0x5566, 0xB0D5, 0x556A, 0xB0D4, 0x5575, 0xD471, 0x5576, 0xD472,	0x5577, 0xD86A, 0x557B, 0xB3D7, 0x557C, 0xB3DA, 0x557D, 0xD875,
+	0x557E, 0xB3EE, 0x557F, 0xD878, 0x5580, 0xB3D8, 0x5581, 0xD871,	0x5582, 0xB3DE, 0x5583, 0xB3E4, 0x5584, 0xB5BD, 0x5587, 0xB3E2,
+	0x5588, 0xD86E, 0x5589, 0xB3EF, 0x558A, 0xB3DB, 0x558B, 0xB3E3,	0x558C, 0xD876, 0x558D, 0xDCD7, 0x558E, 0xD87B, 0x558F, 0xD86F,
+	0x5591, 0xD866, 0x5592, 0xD873, 0x5593, 0xD86D, 0x5594, 0xB3E1,	0x5595, 0xD879, 0x5598, 0xB3DD, 0x5599, 0xB3F1, 0x559A, 0xB3EA,
+	0x559C, 0xB3DF, 0x559D, 0xB3DC, 0x559F, 0xB3E7, 0x55A1, 0xD87A,	0x55A2, 0xD86C, 0x55A3, 0xD872, 0x55A4, 0xD874, 0x55A5, 0xD868,
+	0x55A6, 0xD877, 0x55A7, 0xB3D9, 0x55A8, 0xD867, 0x55AA, 0xB3E0,	0x55AB, 0xB3F0, 0x55AC, 0xB3EC, 0x55AD, 0xD869, 0x55AE, 0xB3E6,
+	0x55B1, 0xB3ED, 0x55B2, 0xB3E9, 0x55B3, 0xB3E5, 0x55B5, 0xD870,	0x55BB, 0xB3EB, 0x55BF, 0xDCD5, 0x55C0, 0xDCD1, 0x55C2, 0xDCE0,
+	0x55C3, 0xDCCA, 0x55C4, 0xDCD3, 0x55C5, 0xB6E5, 0x55C6, 0xB6E6,	0x55C7, 0xB6DE, 0x55C8, 0xDCDC, 0x55C9, 0xB6E8, 0x55CA, 0xDCCF,
+	0x55CB, 0xDCCE, 0x55CC, 0xDCCC, 0x55CD, 0xDCDE, 0x55CE, 0xB6DC,	0x55CF, 0xDCD8, 0x55D0, 0xDCCD, 0x55D1, 0xB6DF, 0x55D2, 0xDCD6,
+	0x55D3, 0xB6DA, 0x55D4, 0xDCD2, 0x55D5, 0xDCD9, 0x55D6, 0xDCDB,	0x55D9, 0xDCDF, 0x55DA, 0xB6E3, 0x55DB, 0xDCCB, 0x55DC, 0xB6DD,
+	0x55DD, 0xDCD0, 0x55DF, 0xB6D8, 0x55E1, 0xB6E4, 0x55E2, 0xDCDA,	0x55E3, 0xB6E0, 0x55E4, 0xB6E1, 0x55E5, 0xB6E7, 0x55E6, 0xB6DB,
+	0x55E7, 0xA25F, 0x55E8, 0xB6D9, 0x55E9, 0xDCD4, 0x55EF, 0xB6E2,	0x55F2, 0xDCDD, 0x55F6, 0xB9CD, 0x55F7, 0xB9C8, 0x55F9, 0xE155,
+	0x55FA, 0xE151, 0x55FC, 0xE14B, 0x55FD, 0xB9C2, 0x55FE, 0xB9BE,	0x55FF, 0xE154, 0x5600, 0xB9BF, 0x5601, 0xE14E, 0x5602, 0xE150,
+	0x5604, 0xE153, 0x5606, 0xB9C4, 0x5608, 0xB9CB, 0x5609, 0xB9C5,	0x560C, 0xE149, 0x560D, 0xB9C6, 0x560E, 0xB9C7, 0x560F, 0xE14C,
+	0x5610, 0xB9CC, 0x5612, 0xE14A, 0x5613, 0xE14F, 0x5614, 0xB9C3,	0x5615, 0xE148, 0x5616, 0xB9C9, 0x5617, 0xB9C1, 0x561B, 0xB9C0,
+	0x561C, 0xE14D, 0x561D, 0xE152, 0x561F, 0xB9CA, 0x5627, 0xE147,	0x5629, 0xBC4D, 0x562A, 0xE547, 0x562C, 0xE544, 0x562E, 0xBC47,
+	0x562F, 0xBC53, 0x5630, 0xBC54, 0x5632, 0xBC4A, 0x5633, 0xE542,	0x5634, 0xBC4C, 0x5635, 0xE4F9, 0x5636, 0xBC52, 0x5638, 0xE546,
+	0x5639, 0xBC49, 0x563A, 0xE548, 0x563B, 0xBC48, 0x563D, 0xE543,	0x563E, 0xE545, 0x563F, 0xBC4B, 0x5640, 0xE541, 0x5641, 0xE4FA,
+	0x5642, 0xE4F7, 0x5645, 0xD86B, 0x5646, 0xE4FD, 0x5648, 0xE4F6,	0x5649, 0xE4FC, 0x564A, 0xE4FB, 0x564C, 0xE4F8, 0x564E, 0xBC4F,
+	0x5653, 0xBC4E, 0x5657, 0xBC50, 0x5658, 0xE4FE, 0x5659, 0xBEB2,	0x565A, 0xE540, 0x565E, 0xE945, 0x5660, 0xE8FD, 0x5662, 0xBEBE,
+	0x5663, 0xE942, 0x5664, 0xBEB6, 0x5665, 0xBEBA, 0x5666, 0xE941,	0x5668, 0xBEB9, 0x5669, 0xBEB5, 0x566A, 0xBEB8, 0x566B, 0xBEB3,
+	0x566C, 0xBEBD, 0x566D, 0xE943, 0x566E, 0xE8FE, 0x566F, 0xBEBC,	0x5670, 0xE8FC, 0x5671, 0xBEBB, 0x5672, 0xE944, 0x5673, 0xE940,
+	0x5674, 0xBC51, 0x5676, 0xBEBF, 0x5677, 0xE946, 0x5678, 0xBEB7,	0x5679, 0xBEB4, 0x567E, 0xECC6, 0x567F, 0xECC8, 0x5680, 0xC07B,
+	0x5681, 0xECC9, 0x5682, 0xECC7, 0x5683, 0xECC5, 0x5684, 0xECC4,	0x5685, 0xC07D, 0x5686, 0xECC3, 0x5687, 0xC07E, 0x568C, 0xECC1,
+	0x568D, 0xECC2, 0x568E, 0xC07A, 0x568F, 0xC0A1, 0x5690, 0xC07C,	0x5693, 0xECC0, 0x5695, 0xC250, 0x5697, 0xEFBC, 0x5698, 0xEFBA,
+	0x5699, 0xEFBF, 0x569A, 0xEFBD, 0x569C, 0xEFBB, 0x569D, 0xEFBE,	0x56A5, 0xC360, 0x56A6, 0xF1F2, 0x56A7, 0xF1F3, 0x56A8, 0xC456,
+	0x56AA, 0xF1F4, 0x56AB, 0xF1F0, 0x56AC, 0xF1F5, 0x56AD, 0xF1F1,	0x56AE, 0xC251, 0x56B2, 0xF3FE, 0x56B3, 0xF441, 0x56B4, 0xC459,
+	0x56B5, 0xF440, 0x56B6, 0xC458, 0x56B7, 0xC457, 0x56BC, 0xC45A,	0x56BD, 0xF5C5, 0x56BE, 0xF5C6, 0x56C0, 0xC4DA, 0x56C1, 0xC4D9,
+	0x56C2, 0xC4DB, 0x56C3, 0xF5C4, 0x56C5, 0xF6D8, 0x56C6, 0xF6D7,	0x56C8, 0xC56D, 0x56C9, 0xC56F, 0x56CA, 0xC56E, 0x56CB, 0xF6D9,
+	0x56CC, 0xC5C8, 0x56CD, 0xF8A6, 0x56D1, 0xC5F1, 0x56D3, 0xF8A5,	0x56D4, 0xF8EE, 0x56D7, 0xC949, 0x56DA, 0xA57D, 0x56DB, 0xA57C,
+	0x56DD, 0xA65F, 0x56DE, 0xA65E, 0x56DF, 0xC9C7, 0x56E0, 0xA65D,	0x56E1, 0xC9C6, 0x56E4, 0xA779, 0x56E5, 0xCAA9, 0x56E7, 0xCAA8,
+	0x56EA, 0xA777, 0x56EB, 0xA77A, 0x56EE, 0xCAA7, 0x56F0, 0xA778,	0x56F7, 0xCBF0, 0x56F9, 0xCBF1, 0x56FA, 0xA954, 0x56FF, 0xABAA,
+	0x5701, 0xD148, 0x5702, 0xD149, 0x5703, 0xAE45, 0x5704, 0xAE46,	0x5707, 0xD4AC, 0x5708, 0xB0E9, 0x5709, 0xB0EB, 0x570A, 0xD4AB,
+	0x570B, 0xB0EA, 0x570C, 0xD87C, 0x570D, 0xB3F2, 0x5712, 0xB6E9,	0x5713, 0xB6EA, 0x5714, 0xDCE1, 0x5716, 0xB9CF, 0x5718, 0xB9CE,
+	0x571A, 0xE549, 0x571B, 0xE948, 0x571C, 0xE947, 0x571E, 0xF96B,	0x571F, 0xA467, 0x5720, 0xC959, 0x5722, 0xC96E, 0x5723, 0xC96F,
+	0x5728, 0xA662, 0x5729, 0xA666, 0x572A, 0xC9C9, 0x572C, 0xA664,	0x572D, 0xA663, 0x572E, 0xC9C8, 0x572F, 0xA665, 0x5730, 0xA661,
+	0x5733, 0xA660, 0x5734, 0xC9CA, 0x573B, 0xA7A6, 0x573E, 0xA7A3,	0x5740, 0xA77D, 0x5741, 0xCAAA, 0x5745, 0xCAAB, 0x5747, 0xA7A1,
+	0x5749, 0xCAAD, 0x574A, 0xA77B, 0x574B, 0xCAAE, 0x574C, 0xCAAC,	0x574D, 0xA77E, 0x574E, 0xA7A2, 0x574F, 0xA7A5, 0x5750, 0xA7A4,
+	0x5751, 0xA77C, 0x5752, 0xCAAF, 0x5761, 0xA959, 0x5762, 0xCBFE,	0x5764, 0xA95B, 0x5766, 0xA95A, 0x5768, 0xCC40, 0x5769, 0xA958,
+	0x576A, 0xA957, 0x576B, 0xCBF5, 0x576D, 0xCBF4, 0x576F, 0xCBF2,	0x5770, 0xCBF7, 0x5771, 0xCBF6, 0x5772, 0xCBF3, 0x5773, 0xCBFC,
+	0x5774, 0xCBFD, 0x5775, 0xCBFA, 0x5776, 0xCBF8, 0x5777, 0xA956,	0x577B, 0xCBFB, 0x577C, 0xA95C, 0x577D, 0xCC41, 0x5780, 0xCBF9,
+	0x5782, 0xABAB, 0x5783, 0xA955, 0x578B, 0xABAC, 0x578C, 0xCE54,	0x578F, 0xCE5A, 0x5793, 0xABB2, 0x5794, 0xCE58, 0x5795, 0xCE5E,
+	0x5797, 0xCE55, 0x5798, 0xCE59, 0x5799, 0xCE5B, 0x579A, 0xCE5D,	0x579B, 0xCE57, 0x579D, 0xCE56, 0x579E, 0xCE51, 0x579F, 0xCE52,
+	0x57A0, 0xABAD, 0x57A2, 0xABAF, 0x57A3, 0xABAE, 0x57A4, 0xCE53,	0x57A5, 0xCE5C, 0x57AE, 0xABB1, 0x57B5, 0xCE50, 0x57B6, 0xD153,
+	0x57B8, 0xD152, 0x57B9, 0xD157, 0x57BA, 0xD14E, 0x57BC, 0xD151,	0x57BD, 0xD150, 0x57BF, 0xD154, 0x57C1, 0xD158, 0x57C2, 0xAE47,
+	0x57C3, 0xAE4A, 0x57C6, 0xD14F, 0x57C7, 0xD155, 0x57CB, 0xAE49,	0x57CC, 0xD14A, 0x57CE, 0xABB0, 0x57CF, 0xD4BA, 0x57D0, 0xD156,
+	0x57D2, 0xD14D, 0x57D4, 0xAE48, 0x57D5, 0xD14C, 0x57DC, 0xD4B1,	0x57DF, 0xB0EC, 0x57E0, 0xB0F0, 0x57E1, 0xD4C1, 0x57E2, 0xD4AF,
+	0x57E3, 0xD4BD, 0x57E4, 0xB0F1, 0x57E5, 0xD4BF, 0x57E7, 0xD4C5,	0x57E9, 0xD4C9, 0x57EC, 0xD4C0, 0x57ED, 0xD4B4, 0x57EE, 0xD4BC,
+	0x57F0, 0xD4CA, 0x57F1, 0xD4C8, 0x57F2, 0xD4BE, 0x57F3, 0xD4B9,	0x57F4, 0xD4B2, 0x57F5, 0xD8A6, 0x57F6, 0xD4B0, 0x57F7, 0xB0F5,
+	0x57F8, 0xD4B7, 0x57F9, 0xB0F6, 0x57FA, 0xB0F2, 0x57FB, 0xD4AD,	0x57FC, 0xD4C3, 0x57FD, 0xD4B5, 0x5800, 0xD4B3, 0x5801, 0xD4C6,
+	0x5802, 0xB0F3, 0x5804, 0xD4CC, 0x5805, 0xB0ED, 0x5806, 0xB0EF,	0x5807, 0xD4BB, 0x5808, 0xD4B6, 0x5809, 0xAE4B, 0x580A, 0xB0EE,
+	0x580B, 0xD4B8, 0x580C, 0xD4C7, 0x580D, 0xD4CB, 0x580E, 0xD4C2,	0x5810, 0xD4C4, 0x5814, 0xD4AE, 0x5819, 0xD8A1, 0x581B, 0xD8AA,
+	0x581C, 0xD8A9, 0x581D, 0xB3FA, 0x581E, 0xD8A2, 0x5820, 0xB3FB,	0x5821, 0xB3F9, 0x5823, 0xD8A4, 0x5824, 0xB3F6, 0x5825, 0xD8A8,
+	0x5827, 0xD8A3, 0x5828, 0xD8A5, 0x5829, 0xD87D, 0x582A, 0xB3F4,	0x582C, 0xD8B2, 0x582D, 0xD8B1, 0x582E, 0xD8AE, 0x582F, 0xB3F3,
+	0x5830, 0xB3F7, 0x5831, 0xB3F8, 0x5832, 0xD14B, 0x5833, 0xD8AB,	0x5834, 0xB3F5, 0x5835, 0xB0F4, 0x5836, 0xD8AD, 0x5837, 0xD87E,
+	0x5838, 0xD8B0, 0x5839, 0xD8AF, 0x583B, 0xD8B3, 0x583D, 0xDCEF,	0x583F, 0xD8AC, 0x5848, 0xD8A7, 0x5849, 0xDCE7, 0x584A, 0xB6F4,
+	0x584B, 0xB6F7, 0x584C, 0xB6F2, 0x584D, 0xDCE6, 0x584E, 0xDCEA,	0x584F, 0xDCE5, 0x5851, 0xB6EC, 0x5852, 0xB6F6, 0x5853, 0xDCE2,
+	0x5854, 0xB6F0, 0x5855, 0xDCE9, 0x5857, 0xB6EE, 0x5858, 0xB6ED,	0x5859, 0xDCEC, 0x585A, 0xB6EF, 0x585B, 0xDCEE, 0x585D, 0xDCEB,
+	0x585E, 0xB6EB, 0x5862, 0xB6F5, 0x5863, 0xDCF0, 0x5864, 0xDCE4,	0x5865, 0xDCED, 0x5868, 0xDCE3, 0x586B, 0xB6F1, 0x586D, 0xB6F3,
+	0x586F, 0xDCE8, 0x5871, 0xDCF1, 0x5874, 0xE15D, 0x5875, 0xB9D0,	0x5876, 0xE163, 0x5879, 0xB9D5, 0x587A, 0xE15F, 0x587B, 0xE166,
+	0x587C, 0xE157, 0x587D, 0xB9D7, 0x587E, 0xB9D1, 0x587F, 0xE15C,	0x5880, 0xBC55, 0x5881, 0xE15B, 0x5882, 0xE164, 0x5883, 0xB9D2,
+	0x5885, 0xB9D6, 0x5886, 0xE15A, 0x5887, 0xE160, 0x5888, 0xE165,	0x5889, 0xE156, 0x588A, 0xB9D4, 0x588B, 0xE15E, 0x588E, 0xE162,
+	0x588F, 0xE168, 0x5890, 0xE158, 0x5891, 0xE161, 0x5893, 0xB9D3,	0x5894, 0xE167, 0x5898, 0xE159, 0x589C, 0xBC59, 0x589D, 0xE54B,
+	0x589E, 0xBC57, 0x589F, 0xBC56, 0x58A0, 0xE54D, 0x58A1, 0xE552,	0x58A3, 0xE54E, 0x58A5, 0xE551, 0x58A6, 0xBC5C, 0x58A8, 0xBEA5,
+	0x58A9, 0xBC5B, 0x58AB, 0xE54A, 0x58AC, 0xE550, 0x58AE, 0xBC5A,	0x58AF, 0xE54F, 0x58B1, 0xE54C, 0x58B3, 0xBC58, 0x58BA, 0xE94D,
+	0x58BB, 0xF9D9, 0x58BC, 0xE94F, 0x58BD, 0xE94A, 0x58BE, 0xBEC1,	0x58BF, 0xE94C, 0x58C1, 0xBEC0, 0x58C2, 0xE94E, 0x58C5, 0xBEC3,
+	0x58C6, 0xE950, 0x58C7, 0xBEC2, 0x58C8, 0xE949, 0x58C9, 0xE94B,	0x58CE, 0xC0A5, 0x58CF, 0xECCC, 0x58D1, 0xC0A4, 0x58D2, 0xECCD,
+	0x58D3, 0xC0A3, 0x58D4, 0xECCB, 0x58D5, 0xC0A2, 0x58D6, 0xECCA,	0x58D8, 0xC253, 0x58D9, 0xC252, 0x58DA, 0xF1F6, 0x58DB, 0xF1F8,
+	0x58DD, 0xF1F7, 0x58DE, 0xC361, 0x58DF, 0xC362, 0x58E2, 0xC363,	0x58E3, 0xF442, 0x58E4, 0xC45B, 0x58E7, 0xF7D3, 0x58E8, 0xF7D2,
+	0x58E9, 0xC5F2, 0x58EB, 0xA468, 0x58EC, 0xA4D0, 0x58EF, 0xA7A7,	0x58F4, 0xCE5F, 0x58F9, 0xB3FC, 0x58FA, 0xB3FD, 0x58FC, 0xDCF2,
+	0x58FD, 0xB9D8, 0x58FE, 0xE169, 0x58FF, 0xE553, 0x5903, 0xC95A,	0x5906, 0xCAB0, 0x590C, 0xCC42, 0x590D, 0xCE60, 0x590E, 0xD159,
+	0x590F, 0xAE4C, 0x5912, 0xF1F9, 0x5914, 0xC4DC, 0x5915, 0xA469,	0x5916, 0xA57E, 0x5917, 0xC970, 0x5919, 0xA667, 0x591A, 0xA668,
+	0x591C, 0xA95D, 0x5920, 0xB0F7, 0x5922, 0xB9DA, 0x5924, 0xB9DB,	0x5925, 0xB9D9, 0x5927, 0xA46A, 0x5929, 0xA4D1, 0x592A, 0xA4D3,
+	0x592B, 0xA4D2, 0x592C, 0xC95B, 0x592D, 0xA4D4, 0x592E, 0xA5A1,	0x592F, 0xC971, 0x5931, 0xA5A2, 0x5937, 0xA669, 0x5938, 0xA66A,
+	0x593C, 0xC9CB, 0x593E, 0xA7A8, 0x5940, 0xCAB1, 0x5944, 0xA961,	0x5945, 0xCC43, 0x5947, 0xA95F, 0x5948, 0xA960, 0x5949, 0xA95E,
+	0x594A, 0xD15A, 0x594E, 0xABB6, 0x594F, 0xABB5, 0x5950, 0xABB7,	0x5951, 0xABB4, 0x5953, 0xCE61, 0x5954, 0xA962, 0x5955, 0xABB3,
+	0x5957, 0xAE4D, 0x5958, 0xAE4E, 0x595A, 0xAE4F, 0x595C, 0xD4CD,	0x5960, 0xB3FE, 0x5961, 0xD8B4, 0x5962, 0xB0F8, 0x5967, 0xB6F8,
+	0x5969, 0xB9DD, 0x596A, 0xB9DC, 0x596B, 0xE16A, 0x596D, 0xBC5D,	0x596E, 0xBEC4, 0x5970, 0xEFC0, 0x5971, 0xF6DA, 0x5972, 0xF7D4,
+	0x5973, 0xA46B, 0x5974, 0xA5A3, 0x5976, 0xA5A4, 0x5977, 0xC9D1,	0x5978, 0xA66C, 0x5979, 0xA66F, 0x597B, 0xC9CF, 0x597C, 0xC9CD,
+	0x597D, 0xA66E, 0x597E, 0xC9D0, 0x597F, 0xC9D2, 0x5980, 0xC9CC,	0x5981, 0xA671, 0x5982, 0xA670, 0x5983, 0xA66D, 0x5984, 0xA66B,
+	0x5985, 0xC9CE, 0x598A, 0xA7B3, 0x598D, 0xA7B0, 0x598E, 0xCAB6,	0x598F, 0xCAB9, 0x5990, 0xCAB8, 0x5992, 0xA7AA, 0x5993, 0xA7B2,
+	0x5996, 0xA7AF, 0x5997, 0xCAB5, 0x5998, 0xCAB3, 0x5999, 0xA7AE,	0x599D, 0xA7A9, 0x599E, 0xA7AC, 0x59A0, 0xCAB4, 0x59A1, 0xCABB,
+	0x59A2, 0xCAB7, 0x59A3, 0xA7AD, 0x59A4, 0xA7B1, 0x59A5, 0xA7B4,	0x59A6, 0xCAB2, 0x59A7, 0xCABA, 0x59A8, 0xA7AB, 0x59AE, 0xA967,
+	0x59AF, 0xA96F, 0x59B1, 0xCC4F, 0x59B2, 0xCC48, 0x59B3, 0xA970,	0x59B4, 0xCC53, 0x59B5, 0xCC44, 0x59B6, 0xCC4B, 0x59B9, 0xA966,
+	0x59BA, 0xCC45, 0x59BB, 0xA964, 0x59BC, 0xCC4C, 0x59BD, 0xCC50,	0x59BE, 0xA963, 0x59C0, 0xCC51, 0x59C1, 0xCC4A, 0x59C3, 0xCC4D,
+	0x59C5, 0xA972, 0x59C6, 0xA969, 0x59C7, 0xCC54, 0x59C8, 0xCC52,	0x59CA, 0xA96E, 0x59CB, 0xA96C, 0x59CC, 0xCC49, 0x59CD, 0xA96B,
+	0x59CE, 0xCC47, 0x59CF, 0xCC46, 0x59D0, 0xA96A, 0x59D1, 0xA968,	0x59D2, 0xA971, 0x59D3, 0xA96D, 0x59D4, 0xA965, 0x59D6, 0xCC4E,
+	0x59D8, 0xABB9, 0x59DA, 0xABC0, 0x59DB, 0xCE6F, 0x59DC, 0xABB8,	0x59DD, 0xCE67, 0x59DE, 0xCE63, 0x59E0, 0xCE73, 0x59E1, 0xCE62,
+	0x59E3, 0xABBB, 0x59E4, 0xCE6C, 0x59E5, 0xABBE, 0x59E6, 0xABC1,	0x59E8, 0xABBC, 0x59E9, 0xCE70, 0x59EA, 0xABBF, 0x59EC, 0xAE56,
+	0x59ED, 0xCE76, 0x59EE, 0xCE64, 0x59F1, 0xCE66, 0x59F2, 0xCE6D,	0x59F3, 0xCE71, 0x59F4, 0xCE75, 0x59F5, 0xCE72, 0x59F6, 0xCE6B,
+	0x59F7, 0xCE6E, 0x59FA, 0xCE68, 0x59FB, 0xABC3, 0x59FC, 0xCE6A,	0x59FD, 0xCE69, 0x59FE, 0xCE74, 0x59FF, 0xABBA, 0x5A00, 0xCE65,
+	0x5A01, 0xABC2, 0x5A03, 0xABBD, 0x5A09, 0xAE5C, 0x5A0A, 0xD162,	0x5A0C, 0xAE5B, 0x5A0F, 0xD160, 0x5A11, 0xAE50, 0x5A13, 0xAE55,
+	0x5A15, 0xD15F, 0x5A16, 0xD15C, 0x5A17, 0xD161, 0x5A18, 0xAE51,	0x5A19, 0xD15B, 0x5A1B, 0xAE54, 0x5A1C, 0xAE52, 0x5A1E, 0xD163,
+	0x5A1F, 0xAE53, 0x5A20, 0xAE57, 0x5A23, 0xAE58, 0x5A25, 0xAE5A,	0x5A29, 0xAE59, 0x5A2D, 0xD15D, 0x5A2E, 0xD15E, 0x5A33, 0xD164,
+	0x5A35, 0xD4D4, 0x5A36, 0xB0F9, 0x5A37, 0xD8C2, 0x5A38, 0xD4D3,	0x5A39, 0xD4E6, 0x5A3C, 0xB140, 0x5A3E, 0xD4E4, 0x5A40, 0xB0FE,
+	0x5A41, 0xB0FA, 0x5A42, 0xD4ED, 0x5A43, 0xD4DD, 0x5A44, 0xD4E0,	0x5A46, 0xB143, 0x5A47, 0xD4EA, 0x5A48, 0xD4E2, 0x5A49, 0xB0FB,
+	0x5A4A, 0xB144, 0x5A4C, 0xD4E7, 0x5A4D, 0xD4E5, 0x5A50, 0xD4D6,	0x5A51, 0xD4EB, 0x5A52, 0xD4DF, 0x5A53, 0xD4DA, 0x5A55, 0xD4D0,
+	0x5A56, 0xD4EC, 0x5A57, 0xD4DC, 0x5A58, 0xD4CF, 0x5A5A, 0xB142,	0x5A5B, 0xD4E1, 0x5A5C, 0xD4EE, 0x5A5D, 0xD4DE, 0x5A5E, 0xD4D2,
+	0x5A5F, 0xD4D7, 0x5A60, 0xD4CE, 0x5A62, 0xB141, 0x5A64, 0xD4DB,	0x5A65, 0xD4D8, 0x5A66, 0xB0FC, 0x5A67, 0xD4D1, 0x5A69, 0xD4E9,
+	0x5A6A, 0xB0FD, 0x5A6C, 0xD4D9, 0x5A6D, 0xD4D5, 0x5A70, 0xD4E8,	0x5A77, 0xB440, 0x5A78, 0xD8BB, 0x5A7A, 0xD8B8, 0x5A7B, 0xD8C9,
+	0x5A7C, 0xD8BD, 0x5A7D, 0xD8CA, 0x5A7F, 0xB442, 0x5A83, 0xD8C6,	0x5A84, 0xD8C3, 0x5A8A, 0xD8C4, 0x5A8B, 0xD8C7, 0x5A8C, 0xD8CB,
+	0x5A8E, 0xD4E3, 0x5A8F, 0xD8CD, 0x5A90, 0xDD47, 0x5A92, 0xB443,	0x5A93, 0xD8CE, 0x5A94, 0xD8B6, 0x5A95, 0xD8C0, 0x5A97, 0xD8C5,
+	0x5A9A, 0xB441, 0x5A9B, 0xB444, 0x5A9C, 0xD8CC, 0x5A9D, 0xD8CF,	0x5A9E, 0xD8BA, 0x5A9F, 0xD8B7, 0x5AA2, 0xD8B9, 0x5AA5, 0xD8BE,
+	0x5AA6, 0xD8BC, 0x5AA7, 0xB445, 0x5AA9, 0xD8C8, 0x5AAC, 0xD8BF,	0x5AAE, 0xD8C1, 0x5AAF, 0xD8B5, 0x5AB0, 0xDCFA, 0x5AB1, 0xDCF8,
+	0x5AB2, 0xB742, 0x5AB3, 0xB740, 0x5AB4, 0xDD43, 0x5AB5, 0xDCF9,	0x5AB6, 0xDD44, 0x5AB7, 0xDD40, 0x5AB8, 0xDCF7, 0x5AB9, 0xDD46,
+	0x5ABA, 0xDCF6, 0x5ABB, 0xDCFD, 0x5ABC, 0xB6FE, 0x5ABD, 0xB6FD,	0x5ABE, 0xB6FC, 0x5ABF, 0xDCFB, 0x5AC0, 0xDD41, 0x5AC1, 0xB6F9,
+	0x5AC2, 0xB741, 0x5AC4, 0xDCF4, 0x5AC6, 0xDCFE, 0x5AC7, 0xDCF3,	0x5AC8, 0xDCFC, 0x5AC9, 0xB6FA, 0x5ACA, 0xDD42, 0x5ACB, 0xDCF5,
+	0x5ACC, 0xB6FB, 0x5ACD, 0xDD45, 0x5AD5, 0xE16E, 0x5AD6, 0xB9E2,	0x5AD7, 0xB9E1, 0x5AD8, 0xB9E3, 0x5AD9, 0xE17A, 0x5ADA, 0xE170,
+	0x5ADB, 0xE176, 0x5ADC, 0xE16B, 0x5ADD, 0xE179, 0x5ADE, 0xE178,	0x5ADF, 0xE17C, 0x5AE0, 0xE175, 0x5AE1, 0xB9DE, 0x5AE2, 0xE174,
+	0x5AE3, 0xB9E4, 0x5AE5, 0xE16D, 0x5AE6, 0xB9DF, 0x5AE8, 0xE17B,	0x5AE9, 0xB9E0, 0x5AEA, 0xE16F, 0x5AEB, 0xE172, 0x5AEC, 0xE177,
+	0x5AED, 0xE171, 0x5AEE, 0xE16C, 0x5AF3, 0xE173, 0x5AF4, 0xE555,	0x5AF5, 0xBC61, 0x5AF6, 0xE558, 0x5AF7, 0xE557, 0x5AF8, 0xE55A,
+	0x5AF9, 0xE55C, 0x5AFA, 0xF9DC, 0x5AFB, 0xBC5F, 0x5AFD, 0xE556,	0x5AFF, 0xE554, 0x5B01, 0xE55D, 0x5B02, 0xE55B, 0x5B03, 0xE559,
+	0x5B05, 0xE55F, 0x5B07, 0xE55E, 0x5B08, 0xBC63, 0x5B09, 0xBC5E,	0x5B0B, 0xBC60, 0x5B0C, 0xBC62, 0x5B0F, 0xE560, 0x5B10, 0xE957,
+	0x5B13, 0xE956, 0x5B14, 0xE955, 0x5B16, 0xE958, 0x5B17, 0xE951,	0x5B19, 0xE952, 0x5B1A, 0xE95A, 0x5B1B, 0xE953, 0x5B1D, 0xBEC5,
+	0x5B1E, 0xE95C, 0x5B20, 0xE95B, 0x5B21, 0xE954, 0x5B23, 0xECD1,	0x5B24, 0xC0A8, 0x5B25, 0xECCF, 0x5B26, 0xECD4, 0x5B27, 0xECD3,
+	0x5B28, 0xE959, 0x5B2A, 0xC0A7, 0x5B2C, 0xECD2, 0x5B2D, 0xECCE,	0x5B2E, 0xECD6, 0x5B2F, 0xECD5, 0x5B30, 0xC0A6, 0x5B32, 0xECD0,
+	0x5B34, 0xBEC6, 0x5B38, 0xC254, 0x5B3C, 0xEFC1, 0x5B3D, 0xF1FA,	0x5B3E, 0xF1FB, 0x5B3F, 0xF1FC, 0x5B40, 0xC45C, 0x5B43, 0xC45D,
+	0x5B45, 0xF443, 0x5B47, 0xF5C8, 0x5B48, 0xF5C7, 0x5B4B, 0xF6DB,	0x5B4C, 0xF6DC, 0x5B4D, 0xF7D5, 0x5B4E, 0xF8A7, 0x5B50, 0xA46C,
+	0x5B51, 0xA46D, 0x5B53, 0xA46E, 0x5B54, 0xA4D5, 0x5B55, 0xA5A5,	0x5B56, 0xC9D3, 0x5B57, 0xA672, 0x5B58, 0xA673, 0x5B5A, 0xA7B7,
+	0x5B5B, 0xA7B8, 0x5B5C, 0xA7B6, 0x5B5D, 0xA7B5, 0x5B5F, 0xA973,	0x5B62, 0xCC55, 0x5B63, 0xA975, 0x5B64, 0xA974, 0x5B65, 0xCC56,
+	0x5B69, 0xABC4, 0x5B6B, 0xAE5D, 0x5B6C, 0xD165, 0x5B6E, 0xD4F0,	0x5B70, 0xB145, 0x5B71, 0xB447, 0x5B72, 0xD4EF, 0x5B73, 0xB446,
+	0x5B75, 0xB9E5, 0x5B77, 0xE17D, 0x5B78, 0xBEC7, 0x5B7A, 0xC0A9,	0x5B7B, 0xECD7, 0x5B7D, 0xC45E, 0x5B7F, 0xC570, 0x5B81, 0xC972,
+	0x5B83, 0xA5A6, 0x5B84, 0xC973, 0x5B85, 0xA676, 0x5B87, 0xA674,	0x5B88, 0xA675, 0x5B89, 0xA677, 0x5B8B, 0xA7BA, 0x5B8C, 0xA7B9,
+	0x5B8E, 0xCABC, 0x5B8F, 0xA7BB, 0x5B92, 0xCABD, 0x5B93, 0xCC57,	0x5B95, 0xCC58, 0x5B97, 0xA976, 0x5B98, 0xA978, 0x5B99, 0xA97A,
+	0x5B9A, 0xA977, 0x5B9B, 0xA97B, 0x5B9C, 0xA979, 0x5BA2, 0xABC8,	0x5BA3, 0xABC5, 0x5BA4, 0xABC7, 0x5BA5, 0xABC9, 0x5BA6, 0xABC6,
+	0x5BA7, 0xD166, 0x5BA8, 0xCE77, 0x5BAC, 0xD168, 0x5BAD, 0xD167,	0x5BAE, 0xAE63, 0x5BB0, 0xAE5F, 0x5BB3, 0xAE60, 0x5BB4, 0xAE62,
+	0x5BB5, 0xAE64, 0x5BB6, 0xAE61, 0x5BB8, 0xAE66, 0x5BB9, 0xAE65,	0x5BBF, 0xB14A, 0x5BC0, 0xD4F2, 0x5BC1, 0xD4F1, 0x5BC2, 0xB149,
+	0x5BC4, 0xB148, 0x5BC5, 0xB147, 0x5BC6, 0xB14B, 0x5BC7, 0xB146,	0x5BCA, 0xD8D5, 0x5BCB, 0xD8D2, 0x5BCC, 0xB449, 0x5BCD, 0xD8D1,
+	0x5BCE, 0xD8D6, 0x5BD0, 0xB44B, 0x5BD1, 0xD8D4, 0x5BD2, 0xB448,	0x5BD3, 0xB44A, 0x5BD4, 0xD8D3, 0x5BD6, 0xDD48, 0x5BD8, 0xDD49,
+	0x5BD9, 0xDD4A, 0x5BDE, 0xB9E6, 0x5BDF, 0xB9EE, 0x5BE0, 0xE17E,	0x5BE1, 0xB9E8, 0x5BE2, 0xB9EC, 0x5BE3, 0xE1A1, 0x5BE4, 0xB9ED,
+	0x5BE5, 0xB9E9, 0x5BE6, 0xB9EA, 0x5BE7, 0xB9E7, 0x5BE8, 0xB9EB,	0x5BE9, 0xBC66, 0x5BEA, 0xD8D0, 0x5BEB, 0xBC67, 0x5BEC, 0xBC65,
+	0x5BEE, 0xBC64, 0x5BEF, 0xE95D, 0x5BF0, 0xBEC8, 0x5BF1, 0xECD8,	0x5BF2, 0xECD9, 0x5BF5, 0xC364, 0x5BF6, 0xC45F, 0x5BF8, 0xA46F,
+	0x5BFA, 0xA678, 0x5C01, 0xABCA, 0x5C03, 0xD169, 0x5C04, 0xAE67,	0x5C07, 0xB14E, 0x5C08, 0xB14D, 0x5C09, 0xB14C, 0x5C0A, 0xB44C,
+	0x5C0B, 0xB44D, 0x5C0C, 0xD8D7, 0x5C0D, 0xB9EF, 0x5C0E, 0xBEC9,	0x5C0F, 0xA470, 0x5C10, 0xC95C, 0x5C11, 0xA4D6, 0x5C12, 0xC974,
+	0x5C15, 0xC9D4, 0x5C16, 0xA679, 0x5C1A, 0xA97C, 0x5C1F, 0xDD4B,	0x5C22, 0xA471, 0x5C24, 0xA4D7, 0x5C25, 0xC9D5, 0x5C28, 0xCABE,
+	0x5C2A, 0xCABF, 0x5C2C, 0xA7BC, 0x5C30, 0xD8D8, 0x5C31, 0xB44E,	0x5C33, 0xDD4C, 0x5C37, 0xC0AA, 0x5C38, 0xA472, 0x5C39, 0xA4A8,
+	0x5C3A, 0xA4D8, 0x5C3B, 0xC975, 0x5C3C, 0xA5A7, 0x5C3E, 0xA7C0,	0x5C3F, 0xA7BF, 0x5C40, 0xA7BD, 0x5C41, 0xA7BE, 0x5C44, 0xCC59,
+	0x5C45, 0xA97E, 0x5C46, 0xA9A1, 0x5C47, 0xCC5A, 0x5C48, 0xA97D,	0x5C4B, 0xABCE, 0x5C4C, 0xCE78, 0x5C4D, 0xABCD, 0x5C4E, 0xABCB,
+	0x5C4F, 0xABCC, 0x5C50, 0xAE6A, 0x5C51, 0xAE68, 0x5C54, 0xD16B,	0x5C55, 0xAE69, 0x5C56, 0xD16A, 0x5C58, 0xAE5E, 0x5C59, 0xD4F3,
+	0x5C5C, 0xB150, 0x5C5D, 0xB151, 0x5C60, 0xB14F, 0x5C62, 0xB9F0,	0x5C63, 0xE1A2, 0x5C64, 0xBC68, 0x5C65, 0xBC69, 0x5C67, 0xE561,
+	0x5C68, 0xC0AB, 0x5C69, 0xEFC2, 0x5C6A, 0xEFC3, 0x5C6C, 0xC4DD,	0x5C6D, 0xF8A8, 0x5C6E, 0xC94B, 0x5C6F, 0xA4D9, 0x5C71, 0xA473,
+	0x5C73, 0xC977, 0x5C74, 0xC976, 0x5C79, 0xA67A, 0x5C7A, 0xC9D7,	0x5C7B, 0xC9D8, 0x5C7C, 0xC9D6, 0x5C7E, 0xC9D9, 0x5C86, 0xCAC7,
+	0x5C88, 0xCAC2, 0x5C89, 0xCAC4, 0x5C8A, 0xCAC6, 0x5C8B, 0xCAC3,	0x5C8C, 0xA7C4, 0x5C8D, 0xCAC0, 0x5C8F, 0xCAC1, 0x5C90, 0xA7C1,
+	0x5C91, 0xA7C2, 0x5C92, 0xCAC5, 0x5C93, 0xCAC8, 0x5C94, 0xA7C3,	0x5C95, 0xCAC9, 0x5C9D, 0xCC68, 0x5C9F, 0xCC62, 0x5CA0, 0xCC5D,
+	0x5CA1, 0xA9A3, 0x5CA2, 0xCC65, 0x5CA3, 0xCC63, 0x5CA4, 0xCC5C,	0x5CA5, 0xCC69, 0x5CA6, 0xCC6C, 0x5CA7, 0xCC67, 0x5CA8, 0xCC60,
+	0x5CA9, 0xA9A5, 0x5CAA, 0xCC66, 0x5CAB, 0xA9A6, 0x5CAC, 0xCC61,	0x5CAD, 0xCC64, 0x5CAE, 0xCC5B, 0x5CAF, 0xCC5F, 0x5CB0, 0xCC6B,
+	0x5CB1, 0xA9A7, 0x5CB3, 0xA9A8, 0x5CB5, 0xCC5E, 0x5CB6, 0xCC6A,	0x5CB7, 0xA9A2, 0x5CB8, 0xA9A4, 0x5CC6, 0xCEAB, 0x5CC7, 0xCEA4,
+	0x5CC8, 0xCEAA, 0x5CC9, 0xCEA3, 0x5CCA, 0xCEA5, 0x5CCB, 0xCE7D,	0x5CCC, 0xCE7B, 0x5CCE, 0xCEAC, 0x5CCF, 0xCEA9, 0x5CD0, 0xCE79,
+	0x5CD2, 0xABD0, 0x5CD3, 0xCEA7, 0x5CD4, 0xCEA8, 0x5CD6, 0xCEA6,	0x5CD7, 0xCE7C, 0x5CD8, 0xCE7A, 0x5CD9, 0xABCF, 0x5CDA, 0xCEA2,
+	0x5CDB, 0xCE7E, 0x5CDE, 0xCEA1, 0x5CDF, 0xCEAD, 0x5CE8, 0xAE6F,	0x5CEA, 0xAE6E, 0x5CEC, 0xD16C, 0x5CED, 0xAE6B, 0x5CEE, 0xD16E,
+	0x5CF0, 0xAE70, 0x5CF1, 0xD16F, 0x5CF4, 0xAE73, 0x5CF6, 0xAE71,	0x5CF7, 0xD170, 0x5CF8, 0xCEAE, 0x5CF9, 0xD172, 0x5CFB, 0xAE6D,
+	0x5CFD, 0xAE6C, 0x5CFF, 0xD16D, 0x5D00, 0xD171, 0x5D01, 0xAE72,	0x5D06, 0xB153, 0x5D07, 0xB152, 0x5D0B, 0xD4F5, 0x5D0C, 0xD4F9,
+	0x5D0D, 0xD4FB, 0x5D0E, 0xB154, 0x5D0F, 0xD4FE, 0x5D11, 0xB158,	0x5D12, 0xD541, 0x5D14, 0xB15A, 0x5D16, 0xB156, 0x5D17, 0xB15E,
+	0x5D19, 0xB15B, 0x5D1A, 0xD4F7, 0x5D1B, 0xB155, 0x5D1D, 0xD4F6,	0x5D1E, 0xD4F4, 0x5D1F, 0xD543, 0x5D20, 0xD4F8, 0x5D22, 0xB157,
+	0x5D23, 0xD542, 0x5D24, 0xB15C, 0x5D25, 0xD4FD, 0x5D26, 0xD4FC,	0x5D27, 0xB15D, 0x5D28, 0xD4FA, 0x5D29, 0xB159, 0x5D2E, 0xD544,
+	0x5D30, 0xD540, 0x5D31, 0xD8E7, 0x5D32, 0xD8EE, 0x5D33, 0xD8E3,	0x5D34, 0xB451, 0x5D35, 0xD8DF, 0x5D36, 0xD8EF, 0x5D37, 0xD8D9,
+	0x5D38, 0xD8EC, 0x5D39, 0xD8EA, 0x5D3A, 0xD8E4, 0x5D3C, 0xD8ED,	0x5D3D, 0xD8E6, 0x5D3F, 0xD8DE, 0x5D40, 0xD8F0, 0x5D41, 0xD8DC,
+	0x5D42, 0xD8E9, 0x5D43, 0xD8DA, 0x5D45, 0xD8F1, 0x5D47, 0xB452,	0x5D49, 0xD8EB, 0x5D4A, 0xDD4F, 0x5D4B, 0xD8DD, 0x5D4C, 0xB44F,
+	0x5D4E, 0xD8E1, 0x5D50, 0xB450, 0x5D51, 0xD8E0, 0x5D52, 0xD8E5,	0x5D55, 0xD8E2, 0x5D59, 0xD8E8, 0x5D5E, 0xDD53, 0x5D62, 0xDD56,
+	0x5D63, 0xDD4E, 0x5D65, 0xDD50, 0x5D67, 0xDD55, 0x5D68, 0xDD54,	0x5D69, 0xB743, 0x5D6B, 0xD8DB, 0x5D6C, 0xDD52, 0x5D6F, 0xB744,
+	0x5D71, 0xDD4D, 0x5D72, 0xDD51, 0x5D77, 0xE1A9, 0x5D79, 0xE1B0,	0x5D7A, 0xE1A7, 0x5D7C, 0xE1AE, 0x5D7D, 0xE1A5, 0x5D7E, 0xE1AD,
+	0x5D7F, 0xE1B1, 0x5D80, 0xE1A4, 0x5D81, 0xE1A8, 0x5D82, 0xE1A3,	0x5D84, 0xB9F1, 0x5D86, 0xE1A6, 0x5D87, 0xB9F2, 0x5D88, 0xE1AC,
+	0x5D89, 0xE1AB, 0x5D8A, 0xE1AA, 0x5D8D, 0xE1AF, 0x5D92, 0xE565,	0x5D93, 0xE567, 0x5D94, 0xBC6B, 0x5D95, 0xE568, 0x5D97, 0xE563,
+	0x5D99, 0xE562, 0x5D9A, 0xE56C, 0x5D9C, 0xE56A, 0x5D9D, 0xBC6A,	0x5D9E, 0xE56D, 0x5D9F, 0xE564, 0x5DA0, 0xE569, 0x5DA1, 0xE56B,
+	0x5DA2, 0xE566, 0x5DA7, 0xE961, 0x5DA8, 0xE966, 0x5DA9, 0xE960,	0x5DAA, 0xE965, 0x5DAC, 0xE95E, 0x5DAD, 0xE968, 0x5DAE, 0xE964,
+	0x5DAF, 0xE969, 0x5DB0, 0xE963, 0x5DB1, 0xE95F, 0x5DB2, 0xE967,	0x5DB4, 0xE96A, 0x5DB5, 0xE962, 0x5DB7, 0xECDA, 0x5DB8, 0xC0AF,
+	0x5DBA, 0xC0AD, 0x5DBC, 0xC0AC, 0x5DBD, 0xC0AE, 0x5DC0, 0xEFC4,	0x5DC2, 0xF172, 0x5DC3, 0xF1FD, 0x5DC6, 0xF444, 0x5DC7, 0xF445,
+	0x5DC9, 0xC460, 0x5DCB, 0xF5C9, 0x5DCD, 0xC4DE, 0x5DCF, 0xF5CA,	0x5DD1, 0xF6DE, 0x5DD2, 0xC572, 0x5DD4, 0xC571, 0x5DD5, 0xF6DD,
+	0x5DD6, 0xC5C9, 0x5DD8, 0xF7D6, 0x5DDD, 0xA474, 0x5DDE, 0xA67B,	0x5DDF, 0xC9DA, 0x5DE0, 0xCACA, 0x5DE1, 0xA8B5, 0x5DE2, 0xB15F,
+	0x5DE5, 0xA475, 0x5DE6, 0xA5AA, 0x5DE7, 0xA5A9, 0x5DE8, 0xA5A8,	0x5DEB, 0xA7C5, 0x5DEE, 0xAE74, 0x5DF0, 0xDD57, 0x5DF1, 0xA476,
+	0x5DF2, 0xA477, 0x5DF3, 0xA478, 0x5DF4, 0xA4DA, 0x5DF7, 0xABD1,	0x5DF9, 0xCEAF, 0x5DFD, 0xB453, 0x5DFE, 0xA479, 0x5DFF, 0xC95D,
+	0x5E02, 0xA5AB, 0x5E03, 0xA5AC, 0x5E04, 0xC978, 0x5E06, 0xA67C,	0x5E0A, 0xCACB, 0x5E0C, 0xA7C6, 0x5E0E, 0xCACC, 0x5E11, 0xA9AE,
+	0x5E14, 0xCC6E, 0x5E15, 0xA9AC, 0x5E16, 0xA9AB, 0x5E17, 0xCC6D,	0x5E18, 0xA9A9, 0x5E19, 0xCC6F, 0x5E1A, 0xA9AA, 0x5E1B, 0xA9AD,
+	0x5E1D, 0xABD2, 0x5E1F, 0xABD4, 0x5E20, 0xCEB3, 0x5E21, 0xCEB0,	0x5E22, 0xCEB1, 0x5E23, 0xCEB2, 0x5E24, 0xCEB4, 0x5E25, 0xABD3,
+	0x5E28, 0xD174, 0x5E29, 0xD173, 0x5E2B, 0xAE76, 0x5E2D, 0xAE75,	0x5E33, 0xB162, 0x5E34, 0xD546, 0x5E36, 0xB161, 0x5E37, 0xB163,
+	0x5E38, 0xB160, 0x5E3D, 0xB455, 0x5E3E, 0xD545, 0x5E40, 0xB456,	0x5E41, 0xD8F3, 0x5E43, 0xB457, 0x5E44, 0xD8F2, 0x5E45, 0xB454,
+	0x5E4A, 0xDD5A, 0x5E4B, 0xDD5C, 0x5E4C, 0xB745, 0x5E4D, 0xDD5B,	0x5E4E, 0xDD59, 0x5E4F, 0xDD58, 0x5E53, 0xE1B4, 0x5E54, 0xB9F7,
+	0x5E55, 0xB9F5, 0x5E57, 0xB9F6, 0x5E58, 0xE1B2, 0x5E59, 0xE1B3,	0x5E5B, 0xB9F3, 0x5E5C, 0xE571, 0x5E5D, 0xE56F, 0x5E5F, 0xBC6D,
+	0x5E60, 0xE570, 0x5E61, 0xBC6E, 0x5E62, 0xBC6C, 0x5E63, 0xB9F4,	0x5E66, 0xE96D, 0x5E67, 0xE96B, 0x5E68, 0xE96C, 0x5E69, 0xE56E,
+	0x5E6A, 0xECDC, 0x5E6B, 0xC0B0, 0x5E6C, 0xECDB, 0x5E6D, 0xEFC5,	0x5E6E, 0xEFC6, 0x5E6F, 0xE96E, 0x5E70, 0xF1FE, 0x5E72, 0xA47A,
+	0x5E73, 0xA5AD, 0x5E74, 0xA67E, 0x5E75, 0xC9DB, 0x5E76, 0xA67D,	0x5E78, 0xA9AF, 0x5E79, 0xB746, 0x5E7B, 0xA4DB, 0x5E7C, 0xA5AE,
+	0x5E7D, 0xABD5, 0x5E7E, 0xB458, 0x5E80, 0xC979, 0x5E82, 0xC97A,	0x5E84, 0xC9DC, 0x5E87, 0xA7C8, 0x5E88, 0xCAD0, 0x5E89, 0xCACE,
+	0x5E8A, 0xA7C9, 0x5E8B, 0xCACD, 0x5E8C, 0xCACF, 0x5E8D, 0xCAD1,	0x5E8F, 0xA7C7, 0x5E95, 0xA9B3, 0x5E96, 0xA9B4, 0x5E97, 0xA9B1,
+	0x5E9A, 0xA9B0, 0x5E9B, 0xCEB8, 0x5E9C, 0xA9B2, 0x5EA0, 0xABD6,	0x5EA2, 0xCEB7, 0x5EA3, 0xCEB9, 0x5EA4, 0xCEB6, 0x5EA5, 0xCEBA,
+	0x5EA6, 0xABD7, 0x5EA7, 0xAE79, 0x5EA8, 0xD175, 0x5EAA, 0xD177,	0x5EAB, 0xAE77, 0x5EAC, 0xD178, 0x5EAD, 0xAE78, 0x5EAE, 0xD176,
+	0x5EB0, 0xCEB5, 0x5EB1, 0xD547, 0x5EB2, 0xD54A, 0x5EB3, 0xD54B,	0x5EB4, 0xD548, 0x5EB5, 0xB167, 0x5EB6, 0xB166, 0x5EB7, 0xB164,
+	0x5EB8, 0xB165, 0x5EB9, 0xD549, 0x5EBE, 0xB168, 0x5EC1, 0xB45A,	0x5EC2, 0xB45B, 0x5EC4, 0xB45C, 0x5EC5, 0xDD5D, 0x5EC6, 0xDD5F,
+	0x5EC7, 0xDD61, 0x5EC8, 0xB748, 0x5EC9, 0xB747, 0x5ECA, 0xB459,	0x5ECB, 0xDD60, 0x5ECC, 0xDD5E, 0x5ECE, 0xE1B8, 0x5ED1, 0xE1B6,
+	0x5ED2, 0xE1BC, 0x5ED3, 0xB9F8, 0x5ED4, 0xE1BD, 0x5ED5, 0xE1BA,	0x5ED6, 0xB9F9, 0x5ED7, 0xE1B7, 0x5ED8, 0xE1B5, 0x5ED9, 0xE1BB,
+	0x5EDA, 0xBC70, 0x5EDB, 0xE573, 0x5EDC, 0xE1B9, 0x5EDD, 0xBC72,	0x5EDE, 0xE574, 0x5EDF, 0xBC71, 0x5EE0, 0xBC74, 0x5EE1, 0xE575,
+	0x5EE2, 0xBC6F, 0x5EE3, 0xBC73, 0x5EE5, 0xE973, 0x5EE6, 0xE971,	0x5EE7, 0xE970, 0x5EE8, 0xE972, 0x5EE9, 0xE96F, 0x5EEC, 0xC366,
+	0x5EEE, 0xF446, 0x5EEF, 0xF447, 0x5EF1, 0xF5CB, 0x5EF2, 0xF6DF,	0x5EF3, 0xC655, 0x5EF6, 0xA9B5, 0x5EF7, 0xA7CA, 0x5EFA, 0xABD8,
+	0x5EFE, 0xA47B, 0x5EFF, 0xA4DC, 0x5F01, 0xA5AF, 0x5F02, 0xC9DD,	0x5F04, 0xA7CB, 0x5F05, 0xCAD2, 0x5F07, 0xCEBB, 0x5F08, 0xABD9,
+	0x5F0A, 0xB9FA, 0x5F0B, 0xA47C, 0x5F0F, 0xA6A1, 0x5F12, 0xB749,	0x5F13, 0xA47D, 0x5F14, 0xA4DD, 0x5F15, 0xA4DE, 0x5F17, 0xA5B1,
+	0x5F18, 0xA5B0, 0x5F1A, 0xC9DE, 0x5F1B, 0xA6A2, 0x5F1D, 0xCAD3,	0x5F1F, 0xA7CC, 0x5F22, 0xCC71, 0x5F23, 0xCC72, 0x5F24, 0xCC73,
+	0x5F26, 0xA9B6, 0x5F27, 0xA9B7, 0x5F28, 0xCC70, 0x5F29, 0xA9B8,	0x5F2D, 0xABDA, 0x5F2E, 0xCEBC, 0x5F30, 0xD17A, 0x5F31, 0xAE7A,
+	0x5F33, 0xD179, 0x5F35, 0xB169, 0x5F36, 0xD54C, 0x5F37, 0xB16A,	0x5F38, 0xD54D, 0x5F3C, 0xB45D, 0x5F40, 0xDD62, 0x5F43, 0xE1BF,
+	0x5F44, 0xE1BE, 0x5F46, 0xB9FB, 0x5F48, 0xBC75, 0x5F49, 0xE576,	0x5F4A, 0xBECA, 0x5F4B, 0xE974, 0x5F4C, 0xC0B1, 0x5F4E, 0xC573,
+	0x5F4F, 0xF7D8, 0x5F54, 0xCC74, 0x5F56, 0xCEBD, 0x5F57, 0xB16B,	0x5F58, 0xD8F4, 0x5F59, 0xB74A, 0x5F5D, 0xC255, 0x5F62, 0xA7CE,
+	0x5F64, 0xA7CD, 0x5F65, 0xABDB, 0x5F67, 0xD17B, 0x5F69, 0xB16D,	0x5F6A, 0xB343, 0x5F6B, 0xB16E, 0x5F6C, 0xB16C, 0x5F6D, 0xB45E,
+	0x5F6F, 0xE1C0, 0x5F70, 0xB9FC, 0x5F71, 0xBC76, 0x5F73, 0xC94C,	0x5F74, 0xC9DF, 0x5F76, 0xCAD5, 0x5F77, 0xA7CF, 0x5F78, 0xCAD4,
+	0x5F79, 0xA7D0, 0x5F7C, 0xA9BC, 0x5F7D, 0xCC77, 0x5F7E, 0xCC76,	0x5F7F, 0xA9BB, 0x5F80, 0xA9B9, 0x5F81, 0xA9BA, 0x5F82, 0xCC75,
+	0x5F85, 0xABDD, 0x5F86, 0xCEBE, 0x5F87, 0xABE0, 0x5F88, 0xABDC,	0x5F89, 0xABE2, 0x5F8A, 0xABDE, 0x5F8B, 0xABDF, 0x5F8C, 0xABE1,
+	0x5F90, 0xAE7D, 0x5F91, 0xAE7C, 0x5F92, 0xAE7B, 0x5F96, 0xD54F,	0x5F97, 0xB16F, 0x5F98, 0xB172, 0x5F99, 0xB170, 0x5F9B, 0xD54E,
+	0x5F9C, 0xB175, 0x5F9E, 0xB171, 0x5F9F, 0xD550, 0x5FA0, 0xB174,	0x5FA1, 0xB173, 0x5FA5, 0xD8F6, 0x5FA6, 0xD8F5, 0x5FA8, 0xB461,
+	0x5FA9, 0xB45F, 0x5FAA, 0xB460, 0x5FAB, 0xD8F7, 0x5FAC, 0xB74B,	0x5FAD, 0xDD64, 0x5FAE, 0xB74C, 0x5FAF, 0xDD63, 0x5FB2, 0xE577,
+	0x5FB5, 0xBC78, 0x5FB6, 0xE1C1, 0x5FB7, 0xBC77, 0x5FB9, 0xB9FD,	0x5FBB, 0xECDE, 0x5FBC, 0xE975, 0x5FBD, 0xC0B2, 0x5FBE, 0xECDD,
+	0x5FBF, 0xF240, 0x5FC0, 0xF448, 0x5FC1, 0xF449, 0x5FC3, 0xA4DF,	0x5FC5, 0xA5B2, 0x5FC9, 0xC97B, 0x5FCC, 0xA7D2, 0x5FCD, 0xA7D4,
+	0x5FCF, 0xC9E2, 0x5FD0, 0xCAD8, 0x5FD1, 0xCAD7, 0x5FD2, 0xCAD6,	0x5FD4, 0xC9E1, 0x5FD5, 0xC9E0, 0x5FD6, 0xA6A4, 0x5FD7, 0xA7D3,
+	0x5FD8, 0xA7D1, 0x5FD9, 0xA6A3, 0x5FDD, 0xA9BD, 0x5FDE, 0xCC78,	0x5FE0, 0xA9BE, 0x5FE1, 0xCADD, 0x5FE3, 0xCADF, 0x5FE4, 0xCADE,
+	0x5FE5, 0xCC79, 0x5FE8, 0xCADA, 0x5FEA, 0xA7D8, 0x5FEB, 0xA7D6,	0x5FED, 0xCAD9, 0x5FEE, 0xCADB, 0x5FEF, 0xCAE1, 0x5FF1, 0xA7D5,
+	0x5FF3, 0xCADC, 0x5FF4, 0xCAE5, 0x5FF5, 0xA9C0, 0x5FF7, 0xCAE2,	0x5FF8, 0xA7D7, 0x5FFA, 0xCAE0, 0x5FFB, 0xCAE3, 0x5FFD, 0xA9BF,
+	0x5FFF, 0xA9C1, 0x6000, 0xCAE4, 0x6009, 0xCCAF, 0x600A, 0xCCA2,	0x600B, 0xCC7E, 0x600C, 0xCCAE, 0x600D, 0xCCA9, 0x600E, 0xABE7,
+	0x600F, 0xA9C2, 0x6010, 0xCCAA, 0x6011, 0xCCAD, 0x6012, 0xABE3,	0x6013, 0xCCAC, 0x6014, 0xA9C3, 0x6015, 0xA9C8, 0x6016, 0xA9C6,
+	0x6017, 0xCCA3, 0x6019, 0xCC7C, 0x601A, 0xCCA5, 0x601B, 0xA9CD,	0x601C, 0xCCB0, 0x601D, 0xABE4, 0x601E, 0xCCA6, 0x6020, 0xABE5,
+	0x6021, 0xA9C9, 0x6022, 0xCCA8, 0x6024, 0xCECD, 0x6025, 0xABE6,	0x6026, 0xCC7B, 0x6027, 0xA9CA, 0x6028, 0xABE8, 0x6029, 0xA9CB,
+	0x602A, 0xA9C7, 0x602B, 0xA9CC, 0x602C, 0xCCA7, 0x602D, 0xCC7A,	0x602E, 0xCCAB, 0x602F, 0xA9C4, 0x6032, 0xCC7D, 0x6033, 0xCCA4,
+	0x6034, 0xCCA1, 0x6035, 0xA9C5, 0x6037, 0xCEBF, 0x6039, 0xCEC0,	0x6040, 0xCECA, 0x6041, 0xD1A1, 0x6042, 0xCECB, 0x6043, 0xABEE,
+	0x6044, 0xCECE, 0x6045, 0xCEC4, 0x6046, 0xABED, 0x6047, 0xCEC6,	0x6049, 0xCEC7, 0x604C, 0xCEC9, 0x604D, 0xABE9, 0x6050, 0xAEA3,
+	0x6052, 0xF9DA, 0x6053, 0xCEC5, 0x6054, 0xCEC1, 0x6055, 0xAEA4,	0x6058, 0xCECF, 0x6059, 0xAE7E, 0x605A, 0xD17D, 0x605B, 0xCEC8,
+	0x605D, 0xD17C, 0x605E, 0xCEC3, 0x605F, 0xCECC, 0x6062, 0xABEC,	0x6063, 0xAEA1, 0x6064, 0xABF2, 0x6065, 0xAEA2, 0x6066, 0xCED0,
+	0x6067, 0xD17E, 0x6068, 0xABEB, 0x6069, 0xAEA6, 0x606A, 0xABF1,	0x606B, 0xABF0, 0x606C, 0xABEF, 0x606D, 0xAEA5, 0x606E, 0xCED1,
+	0x606F, 0xAEA7, 0x6070, 0xABEA, 0x6072, 0xCEC2, 0x607F, 0xB176,	0x6080, 0xD1A4, 0x6081, 0xD1A6, 0x6083, 0xD1A8, 0x6084, 0xAEA8,
+	0x6085, 0xAEAE, 0x6086, 0xD553, 0x6087, 0xD1AC, 0x6088, 0xD1A3,	0x6089, 0xB178, 0x608A, 0xD551, 0x608C, 0xAEAD, 0x608D, 0xAEAB,
+	0x608E, 0xD1AE, 0x6090, 0xD552, 0x6092, 0xD1A5, 0x6094, 0xAEAC,	0x6095, 0xD1A9, 0x6096, 0xAEAF, 0x6097, 0xD1AB, 0x609A, 0xAEAA,
+	0x609B, 0xD1AA, 0x609C, 0xD1AD, 0x609D, 0xD1A7, 0x609F, 0xAEA9,	0x60A0, 0xB179, 0x60A2, 0xD1A2, 0x60A3, 0xB177, 0x60A8, 0xB17A,
+	0x60B0, 0xD555, 0x60B1, 0xD55E, 0x60B2, 0xB464, 0x60B4, 0xB17C,	0x60B5, 0xB1A3, 0x60B6, 0xB465, 0x60B7, 0xD560, 0x60B8, 0xB1AA,
+	0x60B9, 0xD8F9, 0x60BA, 0xD556, 0x60BB, 0xB1A2, 0x60BC, 0xB1A5,	0x60BD, 0xB17E, 0x60BE, 0xD554, 0x60BF, 0xD562, 0x60C0, 0xD565,
+	0x60C1, 0xD949, 0x60C3, 0xD563, 0x60C4, 0xD8FD, 0x60C5, 0xB1A1,	0x60C6, 0xB1A8, 0x60C7, 0xB1AC, 0x60C8, 0xD55D, 0x60C9, 0xD8F8,
+	0x60CA, 0xD561, 0x60CB, 0xB17B, 0x60CC, 0xD8FA, 0x60CD, 0xD564,	0x60CE, 0xD8FC, 0x60CF, 0xD559, 0x60D1, 0xB462, 0x60D3, 0xD557,
+	0x60D4, 0xD558, 0x60D5, 0xB1A7, 0x60D8, 0xB1A6, 0x60D9, 0xD55B,	0x60DA, 0xB1AB, 0x60DB, 0xD55F, 0x60DC, 0xB1A4, 0x60DD, 0xD55C,
+	0x60DF, 0xB1A9, 0x60E0, 0xB466, 0x60E1, 0xB463, 0x60E2, 0xD8FB,	0x60E4, 0xD55A, 0x60E6, 0xB17D, 0x60F0, 0xB46B, 0x60F1, 0xB46F,
+	0x60F2, 0xD940, 0x60F3, 0xB751, 0x60F4, 0xB46D, 0x60F5, 0xD944,	0x60F6, 0xB471, 0x60F7, 0xDD65, 0x60F8, 0xD946, 0x60F9, 0xB753,
+	0x60FA, 0xB469, 0x60FB, 0xB46C, 0x60FC, 0xD947, 0x60FE, 0xD948,	0x60FF, 0xD94E, 0x6100, 0xB473, 0x6101, 0xB754, 0x6103, 0xD94A,
+	0x6104, 0xD94F, 0x6105, 0xD943, 0x6106, 0xB75E, 0x6108, 0xB755,	0x6109, 0xB472, 0x610A, 0xD941, 0x610B, 0xD950, 0x610D, 0xB75D,
+	0x610E, 0xB470, 0x610F, 0xB74E, 0x6110, 0xD94D, 0x6112, 0xB474,	0x6113, 0xD945, 0x6114, 0xD8FE, 0x6115, 0xB46A, 0x6116, 0xD942,
+	0x6118, 0xD94B, 0x611A, 0xB74D, 0x611B, 0xB752, 0x611C, 0xB467,	0x611D, 0xD94C, 0x611F, 0xB750, 0x6123, 0xB468, 0x6127, 0xB75C,
+	0x6128, 0xE1C3, 0x6129, 0xDD70, 0x612B, 0xDD68, 0x612C, 0xE1C2,	0x612E, 0xDD6C, 0x612F, 0xDD6E, 0x6132, 0xDD6B, 0x6134, 0xB75B,
+	0x6136, 0xDD6A, 0x6137, 0xB75F, 0x613B, 0xE1D2, 0x613E, 0xB75A,	0x613F, 0xBA40, 0x6140, 0xDD71, 0x6141, 0xE1C4, 0x6144, 0xB758,
+	0x6145, 0xDD69, 0x6146, 0xDD6D, 0x6147, 0xB9FE, 0x6148, 0xB74F,	0x6149, 0xDD66, 0x614A, 0xDD67, 0x614B, 0xBA41, 0x614C, 0xB757,
+	0x614D, 0xB759, 0x614E, 0xB756, 0x614F, 0xDD6F, 0x6152, 0xE1C8,	0x6153, 0xE1C9, 0x6154, 0xE1CE, 0x6155, 0xBC7D, 0x6156, 0xE1D5,
+	0x6158, 0xBA47, 0x615A, 0xBA46, 0x615B, 0xE1D0, 0x615D, 0xBC7C,	0x615E, 0xE1C5, 0x615F, 0xBA45, 0x6161, 0xE1D4, 0x6162, 0xBA43,
+	0x6163, 0xBA44, 0x6165, 0xE1D1, 0x6166, 0xE5AA, 0x6167, 0xBC7A,	0x6168, 0xB46E, 0x616A, 0xE1D3, 0x616B, 0xBCA3, 0x616C, 0xE1CB,
+	0x616E, 0xBC7B, 0x6170, 0xBCA2, 0x6171, 0xE1C6, 0x6172, 0xE1CA,	0x6173, 0xE1C7, 0x6174, 0xE1CD, 0x6175, 0xBA48, 0x6176, 0xBC79,
+	0x6177, 0xBA42, 0x6179, 0xE57A, 0x617A, 0xE1CF, 0x617C, 0xBCA1,	0x617E, 0xBCA4, 0x6180, 0xE1CC, 0x6182, 0xBC7E, 0x6183, 0xE579,
+	0x6189, 0xE57E, 0x618A, 0xBECE, 0x618B, 0xE578, 0x618C, 0xE9A3,	0x618D, 0xE5A9, 0x618E, 0xBCA8, 0x6190, 0xBCA6, 0x6191, 0xBECC,
+	0x6192, 0xE5A6, 0x6193, 0xE5A2, 0x6194, 0xBCAC, 0x6196, 0xE978,	0x619A, 0xBCAA, 0x619B, 0xE5A1, 0x619D, 0xE976, 0x619F, 0xE5A5,
+	0x61A1, 0xE5A8, 0x61A2, 0xE57D, 0x61A4, 0xBCAB, 0x61A7, 0xBCA5,	0x61A8, 0xE977, 0x61A9, 0xBECD, 0x61AA, 0xE5A7, 0x61AB, 0xBCA7,
+	0x61AC, 0xBCA9, 0x61AD, 0xE5A4, 0x61AE, 0xBCAD, 0x61AF, 0xE5A3,	0x61B0, 0xE57C, 0x61B1, 0xE57B, 0x61B2, 0xBECB, 0x61B3, 0xE5AB,
+	0x61B4, 0xE97A, 0x61B5, 0xECE0, 0x61B6, 0xBED0, 0x61B8, 0xE9A2,	0x61BA, 0xE97E, 0x61BC, 0xECE1, 0x61BE, 0xBED1, 0x61BF, 0xE9A1,
+	0x61C1, 0xE97C, 0x61C2, 0xC0B4, 0x61C3, 0xECDF, 0x61C5, 0xE979,	0x61C6, 0xE97B, 0x61C7, 0xC0B5, 0x61C8, 0xBED3, 0x61C9, 0xC0B3,
+	0x61CA, 0xBED2, 0x61CB, 0xC0B7, 0x61CC, 0xE97D, 0x61CD, 0xBECF,	0x61D6, 0xEFCF, 0x61D8, 0xEFC7, 0x61DE, 0xECE7, 0x61DF, 0xEFC8,
+	0x61E0, 0xECE3, 0x61E3, 0xC256, 0x61E4, 0xECE5, 0x61E5, 0xECE4,	0x61E6, 0xC0B6, 0x61E7, 0xECE2, 0x61E8, 0xECE6, 0x61E9, 0xEFD0,
+	0x61EA, 0xEFCC, 0x61EB, 0xEFCE, 0x61ED, 0xEFC9, 0x61EE, 0xEFCA,	0x61F0, 0xEFCD, 0x61F1, 0xEFCB, 0x61F2, 0xC367, 0x61F5, 0xC36A,
+	0x61F6, 0xC369, 0x61F7, 0xC368, 0x61F8, 0xC461, 0x61F9, 0xF44A,	0x61FA, 0xC462, 0x61FB, 0xF241, 0x61FC, 0xC4DF, 0x61FD, 0xF5CC,
+	0x61FE, 0xC4E0, 0x61FF, 0xC574, 0x6200, 0xC5CA, 0x6201, 0xF7D9,	0x6203, 0xF7DA, 0x6204, 0xF7DB, 0x6207, 0xF9BA, 0x6208, 0xA4E0,
+	0x6209, 0xC97C, 0x620A, 0xA5B3, 0x620C, 0xA6A6, 0x620D, 0xA6A7,	0x620E, 0xA6A5, 0x6210, 0xA6A8, 0x6211, 0xA7DA, 0x6212, 0xA7D9,
+	0x6214, 0xCCB1, 0x6215, 0xA9CF, 0x6216, 0xA9CE, 0x6219, 0xD1AF,	0x621A, 0xB1AD, 0x621B, 0xB1AE, 0x621F, 0xB475, 0x6220, 0xDD72,
+	0x6221, 0xB760, 0x6222, 0xB761, 0x6223, 0xDD74, 0x6224, 0xDD76,	0x6225, 0xDD75, 0x6227, 0xE1D7, 0x6229, 0xE1D6, 0x622A, 0xBA49,
+	0x622B, 0xE1D8, 0x622D, 0xE5AC, 0x622E, 0xBCAE, 0x6230, 0xBED4,	0x6232, 0xC0B8, 0x6233, 0xC257, 0x6234, 0xC0B9, 0x6236, 0xA4E1,
+	0x623A, 0xCAE6, 0x623D, 0xCCB2, 0x623E, 0xA9D1, 0x623F, 0xA9D0,	0x6240, 0xA9D2, 0x6241, 0xABF3, 0x6242, 0xCED2, 0x6243, 0xCED3,
+	0x6246, 0xD1B0, 0x6247, 0xAEB0, 0x6248, 0xB1AF, 0x6249, 0xB476,	0x624A, 0xD951, 0x624B, 0xA4E2, 0x624D, 0xA47E, 0x624E, 0xA4E3,
+	0x6250, 0xC97D, 0x6251, 0xA5B7, 0x6252, 0xA5B6, 0x6253, 0xA5B4,	0x6254, 0xA5B5, 0x6258, 0xA6AB, 0x6259, 0xC9E9, 0x625A, 0xC9EB,
+	0x625B, 0xA6AA, 0x625C, 0xC9E3, 0x625E, 0xC9E4, 0x6260, 0xC9EA,	0x6261, 0xC9E6, 0x6262, 0xC9E8, 0x6263, 0xA6A9, 0x6264, 0xC9E5,
+	0x6265, 0xC9EC, 0x6266, 0xC9E7, 0x626D, 0xA7E1, 0x626E, 0xA7EA,	0x626F, 0xA7E8, 0x6270, 0xCAF0, 0x6271, 0xCAED, 0x6272, 0xCAF5,
+	0x6273, 0xA7E6, 0x6274, 0xCAF6, 0x6276, 0xA7DF, 0x6277, 0xCAF3,	0x6279, 0xA7E5, 0x627A, 0xCAEF, 0x627B, 0xCAEE, 0x627C, 0xA7E3,
+	0x627D, 0xCAF4, 0x627E, 0xA7E4, 0x627F, 0xA9D3, 0x6280, 0xA7DE,	0x6281, 0xCAF1, 0x6283, 0xCAE7, 0x6284, 0xA7DB, 0x6286, 0xA7EE,
+	0x6287, 0xCAEC, 0x6288, 0xCAF2, 0x6289, 0xA7E0, 0x628A, 0xA7E2,	0x628C, 0xCAE8, 0x628E, 0xCAE9, 0x628F, 0xCAEA, 0x6291, 0xA7ED,
+	0x6292, 0xA7E7, 0x6293, 0xA7EC, 0x6294, 0xCAEB, 0x6295, 0xA7EB,	0x6296, 0xA7DD, 0x6297, 0xA7DC, 0x6298, 0xA7E9, 0x62A8, 0xA9E1,
+	0x62A9, 0xCCBE, 0x62AA, 0xCCB7, 0x62AB, 0xA9DC, 0x62AC, 0xA9EF,	0x62AD, 0xCCB3, 0x62AE, 0xCCBA, 0x62AF, 0xCCBC, 0x62B0, 0xCCBF,
+	0x62B1, 0xA9EA, 0x62B3, 0xCCBB, 0x62B4, 0xCCB4, 0x62B5, 0xA9E8,	0x62B6, 0xCCB8, 0x62B8, 0xCCC0, 0x62B9, 0xA9D9, 0x62BB, 0xCCBD,
+	0x62BC, 0xA9E3, 0x62BD, 0xA9E2, 0x62BE, 0xCCB6, 0x62BF, 0xA9D7,	0x62C2, 0xA9D8, 0x62C4, 0xA9D6, 0x62C6, 0xA9EE, 0x62C7, 0xA9E6,
+	0x62C8, 0xA9E0, 0x62C9, 0xA9D4, 0x62CA, 0xCCB9, 0x62CB, 0xA9DF,	0x62CC, 0xA9D5, 0x62CD, 0xA9E7, 0x62CE, 0xA9F0, 0x62CF, 0xCED4,
+	0x62D0, 0xA9E4, 0x62D1, 0xCCB5, 0x62D2, 0xA9DA, 0x62D3, 0xA9DD,	0x62D4, 0xA9DE, 0x62D6, 0xA9EC, 0x62D7, 0xA9ED, 0x62D8, 0xA9EB,
+	0x62D9, 0xA9E5, 0x62DA, 0xA9E9, 0x62DB, 0xA9DB, 0x62DC, 0xABF4,	0x62EB, 0xCEDA, 0x62EC, 0xAC41, 0x62ED, 0xABF8, 0x62EE, 0xABFA,
+	0x62EF, 0xAC40, 0x62F0, 0xCEE6, 0x62F1, 0xABFD, 0x62F2, 0xD1B1,	0x62F3, 0xAEB1, 0x62F4, 0xAC43, 0x62F5, 0xCED7, 0x62F6, 0xCEDF,
+	0x62F7, 0xABFE, 0x62F8, 0xCEDE, 0x62F9, 0xCEDB, 0x62FA, 0xCEE3,	0x62FB, 0xCEE5, 0x62FC, 0xABF7, 0x62FD, 0xABFB, 0x62FE, 0xAC42,
+	0x62FF, 0xAEB3, 0x6300, 0xCEE0, 0x6301, 0xABF9, 0x6302, 0xAC45,	0x6303, 0xCED9, 0x6307, 0xABFC, 0x6308, 0xAEB2, 0x6309, 0xABF6,
+	0x630B, 0xCED6, 0x630C, 0xCEDD, 0x630D, 0xCED5, 0x630E, 0xCED8,	0x630F, 0xCEDC, 0x6310, 0xD1B2, 0x6311, 0xAC44, 0x6313, 0xCEE1,
+	0x6314, 0xCEE2, 0x6315, 0xCEE4, 0x6316, 0xABF5, 0x6328, 0xAEC1,	0x6329, 0xD1BE, 0x632A, 0xAEBF, 0x632B, 0xAEC0, 0x632C, 0xD1B4,
+	0x632D, 0xD1C4, 0x632F, 0xAEB6, 0x6332, 0xD566, 0x6333, 0xD1C6,	0x6334, 0xD1C0, 0x6336, 0xD1B7, 0x6338, 0xD1C9, 0x6339, 0xD1BA,
+	0x633A, 0xAEBC, 0x633B, 0xD57D, 0x633C, 0xD1BD, 0x633D, 0xAEBE,	0x633E, 0xAEB5, 0x6340, 0xD1CB, 0x6341, 0xD1BF, 0x6342, 0xAEB8,
+	0x6343, 0xD1B8, 0x6344, 0xD1B5, 0x6345, 0xD1B6, 0x6346, 0xAEB9,	0x6347, 0xD1C5, 0x6348, 0xD1CC, 0x6349, 0xAEBB, 0x634A, 0xD1BC,
+	0x634B, 0xD1BB, 0x634C, 0xAEC3, 0x634D, 0xAEC2, 0x634E, 0xAEB4,	0x634F, 0xAEBA, 0x6350, 0xAEBD, 0x6351, 0xD1C8, 0x6354, 0xD1C2,
+	0x6355, 0xAEB7, 0x6356, 0xD1B3, 0x6357, 0xD1CA, 0x6358, 0xD1C1,	0x6359, 0xD1C3, 0x635A, 0xD1C7, 0x6365, 0xD567, 0x6367, 0xB1B7,
+	0x6368, 0xB1CB, 0x6369, 0xB1CA, 0x636B, 0xB1BF, 0x636D, 0xD579,	0x636E, 0xD575, 0x636F, 0xD572, 0x6370, 0xD5A6, 0x6371, 0xB1BA,
+	0x6372, 0xB1B2, 0x6375, 0xD577, 0x6376, 0xB4A8, 0x6377, 0xB1B6,	0x6378, 0xD5A1, 0x637A, 0xB1CC, 0x637B, 0xB1C9, 0x637C, 0xD57B,
+	0x637D, 0xD56A, 0x6380, 0xB1C8, 0x6381, 0xD5A3, 0x6382, 0xD569,	0x6383, 0xB1BD, 0x6384, 0xB1C1, 0x6385, 0xD5A2, 0x6387, 0xD573,
+	0x6388, 0xB1C2, 0x6389, 0xB1BC, 0x638A, 0xD568, 0x638C, 0xB478,	0x638D, 0xD5A5, 0x638E, 0xD571, 0x638F, 0xB1C7, 0x6390, 0xD574,
+	0x6391, 0xD5A4, 0x6392, 0xB1C6, 0x6394, 0xD952, 0x6396, 0xB1B3,	0x6397, 0xD56F, 0x6398, 0xB1B8, 0x6399, 0xB1C3, 0x639B, 0xB1BE,
+	0x639C, 0xD578, 0x639D, 0xD56E, 0x639E, 0xD56C, 0x639F, 0xD57E,	0x63A0, 0xB1B0, 0x63A1, 0xB1C4, 0x63A2, 0xB1B4, 0x63A3, 0xB477,
+	0x63A4, 0xD57C, 0x63A5, 0xB1B5, 0x63A7, 0xB1B1, 0x63A8, 0xB1C0,	0x63A9, 0xB1BB, 0x63AA, 0xB1B9, 0x63AB, 0xD570, 0x63AC, 0xB1C5,
+	0x63AD, 0xD56D, 0x63AE, 0xD57A, 0x63AF, 0xD576, 0x63B0, 0xD954,	0x63B1, 0xD953, 0x63BD, 0xD56B, 0x63BE, 0xD964, 0x63C0, 0xB47A,
+	0x63C2, 0xD96A, 0x63C3, 0xD959, 0x63C4, 0xD967, 0x63C5, 0xDD77,	0x63C6, 0xB47D, 0x63C7, 0xD96B, 0x63C8, 0xD96E, 0x63C9, 0xB47C,
+	0x63CA, 0xD95C, 0x63CB, 0xD96D, 0x63CC, 0xD96C, 0x63CD, 0xB47E,	0x63CE, 0xD955, 0x63CF, 0xB479, 0x63D0, 0xB4A3, 0x63D2, 0xB4A1,
+	0x63D3, 0xD969, 0x63D5, 0xD95F, 0x63D6, 0xB4A5, 0x63D7, 0xD970,	0x63D8, 0xD968, 0x63D9, 0xD971, 0x63DA, 0xB4AD, 0x63DB, 0xB4AB,
+	0x63DC, 0xD966, 0x63DD, 0xD965, 0x63DF, 0xD963, 0x63E0, 0xD95D,	0x63E1, 0xB4A4, 0x63E3, 0xB4A2, 0x63E4, 0xD1B9, 0x63E5, 0xD956,
+	0x63E7, 0xDDB7, 0x63E8, 0xD957, 0x63E9, 0xB47B, 0x63EA, 0xB4AA,	0x63EB, 0xDD79, 0x63ED, 0xB4A6, 0x63EE, 0xB4A7, 0x63EF, 0xD958,
+	0x63F0, 0xD96F, 0x63F1, 0xDD78, 0x63F2, 0xD960, 0x63F3, 0xD95B,	0x63F4, 0xB4A9, 0x63F5, 0xD961, 0x63F6, 0xD95E, 0x63F9, 0xB4AE,
+	0x6406, 0xB770, 0x6409, 0xDD7C, 0x640A, 0xDDB1, 0x640B, 0xDDB6,	0x640C, 0xDDAA, 0x640D, 0xB76C, 0x640E, 0xDDBB, 0x640F, 0xB769,
+	0x6410, 0xDD7A, 0x6412, 0xDD7B, 0x6413, 0xB762, 0x6414, 0xB76B,	0x6415, 0xDDA4, 0x6416, 0xB76E, 0x6417, 0xB76F, 0x6418, 0xDDA5,
+	0x641A, 0xDDB2, 0x641B, 0xDDB8, 0x641C, 0xB76A, 0x641E, 0xB764,	0x641F, 0xDDA3, 0x6420, 0xDD7D, 0x6421, 0xDDBA, 0x6422, 0xDDA8,
+	0x6423, 0xDDA9, 0x6424, 0xDD7E, 0x6425, 0xDDB4, 0x6426, 0xDDAB,	0x6427, 0xDDB5, 0x6428, 0xDDAD, 0x642A, 0xB765, 0x642B, 0xE1D9,
+	0x642C, 0xB768, 0x642D, 0xB766, 0x642E, 0xDDB9, 0x642F, 0xDDB0,	0x6430, 0xDDAC, 0x6433, 0xDDA1, 0x6434, 0xBA53, 0x6435, 0xDDAF,
+	0x6436, 0xB76D, 0x6437, 0xDDA7, 0x6439, 0xDDA6, 0x643D, 0xB767,	0x643E, 0xB763, 0x643F, 0xE1EE, 0x6440, 0xDDB3, 0x6441, 0xDDAE,
+	0x6443, 0xDDA2, 0x644B, 0xE1E9, 0x644D, 0xE1DA, 0x644E, 0xE1E5,	0x6450, 0xE1EC, 0x6451, 0xBA51, 0x6452, 0xB4AC, 0x6453, 0xE1EA,
+	0x6454, 0xBA4C, 0x6458, 0xBA4B, 0x6459, 0xE1F1, 0x645B, 0xE1DB,	0x645C, 0xE1E8, 0x645D, 0xE1DC, 0x645E, 0xE1E7, 0x645F, 0xBA4F,
+	0x6460, 0xE1EB, 0x6461, 0xD962, 0x6465, 0xE1F2, 0x6466, 0xE1E3,	0x6467, 0xBA52, 0x6468, 0xE5BA, 0x6469, 0xBCAF, 0x646B, 0xE1F0,
+	0x646C, 0xE1EF, 0x646D, 0xBA54, 0x646E, 0xE5AD, 0x646F, 0xBCB0,	0x6470, 0xE5AE, 0x6472, 0xE1DF, 0x6473, 0xE1E0, 0x6474, 0xE1DD,
+	0x6475, 0xE1E2, 0x6476, 0xE1DE, 0x6477, 0xE1F3, 0x6478, 0xBA4E,	0x6479, 0xBCB1, 0x647A, 0xBA50, 0x647B, 0xBA55, 0x647D, 0xE1E1,
+	0x647F, 0xE1ED, 0x6482, 0xE1E6, 0x6485, 0xE5B1, 0x6487, 0xBA4A,	0x6488, 0xBCB4, 0x6489, 0xE9AA, 0x648A, 0xE5B6, 0x648B, 0xE5B5,
+	0x648C, 0xE5B7, 0x648F, 0xE5B4, 0x6490, 0xBCB5, 0x6492, 0xBCBB,	0x6493, 0xBCB8, 0x6495, 0xBCB9, 0x6496, 0xE5AF, 0x6497, 0xE5B2,
+	0x6498, 0xE5BC, 0x6499, 0xBCC1, 0x649A, 0xBCBF, 0x649C, 0xE5B3,	0x649D, 0xD95A, 0x649E, 0xBCB2, 0x649F, 0xE5B9, 0x64A0, 0xE5B0,
+	0x64A2, 0xBCC2, 0x64A3, 0xE5B8, 0x64A4, 0xBA4D, 0x64A5, 0xBCB7,	0x64A6, 0xE1E4, 0x64A9, 0xBCBA, 0x64AB, 0xBCBE, 0x64AC, 0xBCC0,
+	0x64AD, 0xBCBD, 0x64AE, 0xBCBC, 0x64B0, 0xBCB6, 0x64B1, 0xE5BB,	0x64B2, 0xBCB3, 0x64B3, 0xBCC3, 0x64BB, 0xBED8, 0x64BC, 0xBED9,
+	0x64BD, 0xE9A9, 0x64BE, 0xBEE2, 0x64BF, 0xBEDF, 0x64C1, 0xBED6,	0x64C2, 0xBEDD, 0x64C3, 0xE9AB, 0x64C4, 0xBEDB, 0x64C5, 0xBED5,
+	0x64C7, 0xBEDC, 0x64C9, 0xE9A8, 0x64CA, 0xC0BB, 0x64CB, 0xBED7,	0x64CD, 0xBEDE, 0x64CE, 0xC0BA, 0x64CF, 0xE9A7, 0x64D0, 0xE9A6,
+	0x64D2, 0xBEE0, 0x64D4, 0xBEE1, 0x64D6, 0xE9A5, 0x64D7, 0xE9A4,	0x64D8, 0xC0BC, 0x64D9, 0xE9AE, 0x64DA, 0xBEDA, 0x64DB, 0xE9AC,
+	0x64E0, 0xC0BD, 0x64E2, 0xC0C2, 0x64E3, 0xECEA, 0x64E4, 0xECEC,	0x64E6, 0xC0BF, 0x64E8, 0xECED, 0x64E9, 0xECE9, 0x64EB, 0xECEB,
+	0x64EC, 0xC0C0, 0x64ED, 0xC0C3, 0x64EF, 0xECE8, 0x64F0, 0xC0BE,	0x64F1, 0xC0C1, 0x64F2, 0xC259, 0x64F3, 0xE9AD, 0x64F4, 0xC258,
+	0x64F7, 0xC25E, 0x64F8, 0xEFD4, 0x64FA, 0xC25C, 0x64FB, 0xC25D,	0x64FC, 0xEFD7, 0x64FD, 0xEFD3, 0x64FE, 0xC25A, 0x64FF, 0xEFD1,
+	0x6500, 0xC36B, 0x6501, 0xEFD5, 0x6503, 0xEFD6, 0x6504, 0xEFD2,	0x6506, 0xC25B, 0x6507, 0xF242, 0x6509, 0xF245, 0x650C, 0xF246,
+	0x650D, 0xF244, 0x650E, 0xF247, 0x650F, 0xC36C, 0x6510, 0xF243,	0x6513, 0xF44E, 0x6514, 0xC464, 0x6515, 0xF44D, 0x6516, 0xF44C,
+	0x6517, 0xF44B, 0x6518, 0xC463, 0x6519, 0xC465, 0x651B, 0xF5CD,	0x651C, 0xC4E2, 0x651D, 0xC4E1, 0x6520, 0xF6E1, 0x6521, 0xF6E0,
+	0x6522, 0xF6E3, 0x6523, 0xC5CB, 0x6524, 0xC575, 0x6525, 0xF7DD,	0x6526, 0xF6E2, 0x6529, 0xF7DC, 0x652A, 0xC5CD, 0x652B, 0xC5CC,
+	0x652C, 0xC5F3, 0x652D, 0xF8A9, 0x652E, 0xF8EF, 0x652F, 0xA4E4,	0x6532, 0xD972, 0x6533, 0xE9AF, 0x6536, 0xA6AC, 0x6537, 0xCAF7,
+	0x6538, 0xA7F1, 0x6539, 0xA7EF, 0x653B, 0xA7F0, 0x653D, 0xCCC1,	0x653E, 0xA9F1, 0x653F, 0xAC46, 0x6541, 0xCEE7, 0x6543, 0xCEE8,
+	0x6545, 0xAC47, 0x6546, 0xD1CE, 0x6548, 0xAEC4, 0x6549, 0xAEC5,	0x654A, 0xD1CD, 0x654F, 0xB1D3, 0x6551, 0xB1CF, 0x6553, 0xD5A7,
+	0x6554, 0xB1D6, 0x6555, 0xB1D5, 0x6556, 0xB1CE, 0x6557, 0xB1D1,	0x6558, 0xB1D4, 0x6559, 0xB1D0, 0x655C, 0xD976, 0x655D, 0xB1CD,
+	0x655E, 0xB4AF, 0x6562, 0xB4B1, 0x6563, 0xB4B2, 0x6564, 0xD975,	0x6565, 0xD978, 0x6566, 0xB4B0, 0x6567, 0xD973, 0x6568, 0xD977,
+	0x656A, 0xD974, 0x656C, 0xB771, 0x656F, 0xDDBC, 0x6572, 0xBA56,	0x6573, 0xE1F4, 0x6574, 0xBEE3, 0x6575, 0xBCC4, 0x6576, 0xE5BD,
+	0x6577, 0xBCC5, 0x6578, 0xBCC6, 0x6579, 0xE5BF, 0x657A, 0xE5BE,	0x657B, 0xE5C0, 0x657C, 0xE9B1, 0x657F, 0xE9B0, 0x6580, 0xECEF,
+	0x6581, 0xECEE, 0x6582, 0xC0C4, 0x6583, 0xC0C5, 0x6584, 0xF248,	0x6587, 0xA4E5, 0x658C, 0xD979, 0x6590, 0xB4B4, 0x6591, 0xB4B3,
+	0x6592, 0xDDBD, 0x6594, 0xEFD8, 0x6595, 0xC4E3, 0x6596, 0xF7DE,	0x6597, 0xA4E6, 0x6599, 0xAEC6, 0x659B, 0xB1D8, 0x659C, 0xB1D7,
+	0x659D, 0xD97A, 0x659E, 0xD97B, 0x659F, 0xB772, 0x65A0, 0xE1F5,	0x65A1, 0xBA57, 0x65A2, 0xE9B2, 0x65A4, 0xA4E7, 0x65A5, 0xA5B8,
+	0x65A7, 0xA9F2, 0x65A8, 0xCCC2, 0x65AA, 0xCEE9, 0x65AB, 0xAC48,	0x65AC, 0xB1D9, 0x65AE, 0xD97C, 0x65AF, 0xB4B5, 0x65B0, 0xB773,
+	0x65B2, 0xE5C1, 0x65B3, 0xE5C2, 0x65B6, 0xECF0, 0x65B7, 0xC25F,	0x65B8, 0xF8F0, 0x65B9, 0xA4E8, 0x65BB, 0xCCC3, 0x65BC, 0xA9F3,
+	0x65BD, 0xAC49, 0x65BF, 0xCEEA, 0x65C1, 0xAEC7, 0x65C2, 0xD1D2,	0x65C3, 0xD1D0, 0x65C4, 0xD1D1, 0x65C5, 0xAEC8, 0x65C6, 0xD1CF,
+	0x65CB, 0xB1DB, 0x65CC, 0xB1DC, 0x65CD, 0xD5A8, 0x65CE, 0xB1DD,	0x65CF, 0xB1DA, 0x65D0, 0xD97D, 0x65D2, 0xD97E, 0x65D3, 0xDDBE,
+	0x65D6, 0xBA59, 0x65D7, 0xBA58, 0x65DA, 0xECF1, 0x65DB, 0xEFD9,	0x65DD, 0xF24A, 0x65DE, 0xF249, 0x65DF, 0xF44F, 0x65E1, 0xC95E,
+	0x65E2, 0xAC4A, 0x65E5, 0xA4E9, 0x65E6, 0xA5B9, 0x65E8, 0xA6AE,	0x65E9, 0xA6AD, 0x65EC, 0xA6AF, 0x65ED, 0xA6B0, 0x65EE, 0xC9EE,
+	0x65EF, 0xC9ED, 0x65F0, 0xCAF8, 0x65F1, 0xA7F2, 0x65F2, 0xCAFB,	0x65F3, 0xCAFA, 0x65F4, 0xCAF9, 0x65F5, 0xCAFC, 0x65FA, 0xA9F4,
+	0x65FB, 0xCCC9, 0x65FC, 0xCCC5, 0x65FD, 0xCCCE, 0x6600, 0xA9FB,	0x6602, 0xA9F9, 0x6603, 0xCCCA, 0x6604, 0xCCC6, 0x6605, 0xCCCD,
+	0x6606, 0xA9F8, 0x6607, 0xAA40, 0x6608, 0xCCC8, 0x6609, 0xCCC4,	0x660A, 0xA9FE, 0x660B, 0xCCCB, 0x660C, 0xA9F7, 0x660D, 0xCCCC,
+	0x660E, 0xA9FA, 0x660F, 0xA9FC, 0x6610, 0xCCD0, 0x6611, 0xCCCF,	0x6612, 0xCCC7, 0x6613, 0xA9F6, 0x6614, 0xA9F5, 0x6615, 0xA9FD,
+	0x661C, 0xCEEF, 0x661D, 0xCEF5, 0x661F, 0xAC50, 0x6620, 0xAC4D,	0x6621, 0xCEEC, 0x6622, 0xCEF1, 0x6624, 0xAC53, 0x6625, 0xAC4B,
+	0x6626, 0xCEF0, 0x6627, 0xAC4E, 0x6628, 0xAC51, 0x662B, 0xCEF3,	0x662D, 0xAC4C, 0x662E, 0xCEF8, 0x662F, 0xAC4F, 0x6631, 0xAC52,
+	0x6632, 0xCEED, 0x6633, 0xCEF2, 0x6634, 0xCEF6, 0x6635, 0xCEEE,	0x6636, 0xCEEB, 0x6639, 0xCEF7, 0x663A, 0xCEF4, 0x6641, 0xAED0,
+	0x6642, 0xAEC9, 0x6643, 0xAECC, 0x6645, 0xAECF, 0x6647, 0xD1D5,	0x6649, 0xAECA, 0x664A, 0xD1D3, 0x664C, 0xAECE, 0x664F, 0xAECB,
+	0x6651, 0xD1D6, 0x6652, 0xAECD, 0x6659, 0xD5AC, 0x665A, 0xB1DF,	0x665B, 0xD5AB, 0x665C, 0xD5AD, 0x665D, 0xB1DE, 0x665E, 0xB1E3,
+	0x665F, 0xD1D4, 0x6661, 0xD5AA, 0x6662, 0xD5AE, 0x6664, 0xB1E0,	0x6665, 0xD5A9, 0x6666, 0xB1E2, 0x6668, 0xB1E1, 0x666A, 0xD9A7,
+	0x666C, 0xD9A2, 0x666E, 0xB4B6, 0x666F, 0xB4BA, 0x6670, 0xB4B7,	0x6671, 0xD9A5, 0x6672, 0xD9A8, 0x6674, 0xB4B8, 0x6676, 0xB4B9,
+	0x6677, 0xB4BE, 0x6678, 0xDDC7, 0x6679, 0xD9A6, 0x667A, 0xB4BC,	0x667B, 0xD9A3, 0x667C, 0xD9A1, 0x667E, 0xB4BD, 0x6680, 0xD9A4,
+	0x6684, 0xB779, 0x6686, 0xDDBF, 0x6687, 0xB776, 0x6688, 0xB777,	0x6689, 0xB775, 0x668A, 0xDDC4, 0x668B, 0xDDC3, 0x668C, 0xDDC0,
+	0x668D, 0xB77B, 0x6690, 0xDDC2, 0x6691, 0xB4BB, 0x6694, 0xDDC6,	0x6695, 0xDDC1, 0x6696, 0xB778, 0x6697, 0xB774, 0x6698, 0xB77A,
+	0x6699, 0xDDC5, 0x669D, 0xBA5C, 0x669F, 0xE1F8, 0x66A0, 0xE1F7,	0x66A1, 0xE1F6, 0x66A2, 0xBA5A, 0x66A8, 0xBA5B, 0x66A9, 0xE5C5,
+	0x66AA, 0xE5C8, 0x66AB, 0xBCC8, 0x66AE, 0xBCC7, 0x66AF, 0xE5C9,	0x66B0, 0xE5C4, 0x66B1, 0xBCCA, 0x66B2, 0xE5C6, 0x66B4, 0xBCC9,
+	0x66B5, 0xE5C3, 0x66B7, 0xE5C7, 0x66B8, 0xBEE9, 0x66B9, 0xBEE6,	0x66BA, 0xE9BB, 0x66BB, 0xE9BA, 0x66BD, 0xE9B9, 0x66BE, 0xE9B4,
+	0x66C0, 0xE9B5, 0x66C4, 0xBEE7, 0x66C6, 0xBEE4, 0x66C7, 0xBEE8,	0x66C8, 0xE9B3, 0x66C9, 0xBEE5, 0x66CA, 0xE9B6, 0x66CB, 0xE9B7,
+	0x66CC, 0xE9BC, 0x66CF, 0xE9B8, 0x66D2, 0xECF2, 0x66D6, 0xC0C7,	0x66D8, 0xEFDC, 0x66D9, 0xC0C6, 0x66DA, 0xEFDA, 0x66DB, 0xEFDB,
+	0x66DC, 0xC260, 0x66DD, 0xC36E, 0x66DE, 0xF24B, 0x66E0, 0xC36D,	0x66E3, 0xF451, 0x66E4, 0xF452, 0x66E6, 0xC466, 0x66E8, 0xF450,
+	0x66E9, 0xC4E4, 0x66EB, 0xF7DF, 0x66EC, 0xC5CE, 0x66ED, 0xF8AA,	0x66EE, 0xF8AB, 0x66F0, 0xA4EA, 0x66F2, 0xA6B1, 0x66F3, 0xA6B2,
+	0x66F4, 0xA7F3, 0x66F6, 0xCCD1, 0x66F7, 0xAC54, 0x66F8, 0xAED1,	0x66F9, 0xB1E4, 0x66FC, 0xB0D2, 0x66FE, 0xB4BF, 0x66FF, 0xB4C0,
+	0x6700, 0xB3CC, 0x6701, 0xD9A9, 0x6703, 0xB77C, 0x6704, 0xE1FA,	0x6705, 0xE1F9, 0x6708, 0xA4EB, 0x6709, 0xA6B3, 0x670A, 0xCCD2,
+	0x670B, 0xAA42, 0x670D, 0xAA41, 0x670F, 0xCEF9, 0x6710, 0xCEFA,	0x6712, 0xD1D7, 0x6713, 0xD1D8, 0x6714, 0xAED2, 0x6715, 0xAED3,
+	0x6717, 0xAED4, 0x6718, 0xD5AF, 0x671B, 0xB1E6, 0x671D, 0xB4C2,	0x671F, 0xB4C1, 0x6720, 0xDDC8, 0x6721, 0xDF7A, 0x6722, 0xE1FB,
+	0x6723, 0xE9BD, 0x6726, 0xC261, 0x6727, 0xC467, 0x6728, 0xA4EC,	0x672A, 0xA5BC, 0x672B, 0xA5BD, 0x672C, 0xA5BB, 0x672D, 0xA5BE,
+	0x672E, 0xA5BA, 0x6731, 0xA6B6, 0x6733, 0xC9F6, 0x6734, 0xA6B5,	0x6735, 0xA6B7, 0x6738, 0xC9F1, 0x6739, 0xC9F0, 0x673A, 0xC9F3,
+	0x673B, 0xC9F2, 0x673C, 0xC9F5, 0x673D, 0xA6B4, 0x673E, 0xC9EF,	0x673F, 0xC9F4, 0x6745, 0xCAFD, 0x6746, 0xA7FD, 0x6747, 0xCAFE,
+	0x6748, 0xCB43, 0x6749, 0xA7FC, 0x674B, 0xCB47, 0x674C, 0xCB42,	0x674D, 0xCB45, 0x674E, 0xA7F5, 0x674F, 0xA7F6, 0x6750, 0xA7F7,
+	0x6751, 0xA7F8, 0x6753, 0xA840, 0x6755, 0xCB41, 0x6756, 0xA7FA,	0x6757, 0xA841, 0x6759, 0xCB40, 0x675A, 0xCB46, 0x675C, 0xA7F9,
+	0x675D, 0xCB44, 0x675E, 0xA7FB, 0x675F, 0xA7F4, 0x6760, 0xA7FE,	0x676A, 0xAA57, 0x676C, 0xCCD4, 0x676D, 0xAA43, 0x676F, 0xAA4D,
+	0x6770, 0xAA4E, 0x6771, 0xAA46, 0x6772, 0xAA58, 0x6773, 0xAA48,	0x6774, 0xCCDC, 0x6775, 0xAA53, 0x6776, 0xCCD7, 0x6777, 0xAA49,
+	0x6778, 0xCCE6, 0x6779, 0xCCE7, 0x677A, 0xCCDF, 0x677B, 0xCCD8,	0x677C, 0xAA56, 0x677D, 0xCCE4, 0x677E, 0xAA51, 0x677F, 0xAA4F,
+	0x6781, 0xCCE5, 0x6783, 0xCCE3, 0x6784, 0xCCDB, 0x6785, 0xCCD3,	0x6786, 0xCCDA, 0x6787, 0xAA4A, 0x6789, 0xAA50, 0x678B, 0xAA44,
+	0x678C, 0xCCDE, 0x678D, 0xCCDD, 0x678E, 0xCCD5, 0x6790, 0xAA52,	0x6791, 0xCCE1, 0x6792, 0xCCD6, 0x6793, 0xAA55, 0x6794, 0xCCE8,
+	0x6795, 0xAA45, 0x6797, 0xAA4C, 0x6798, 0xCCD9, 0x6799, 0xCCE2,	0x679A, 0xAA54, 0x679C, 0xAA47, 0x679D, 0xAA4B, 0x679F, 0xCCE0,
+	0x67AE, 0xCF5B, 0x67AF, 0xAC5C, 0x67B0, 0xAC69, 0x67B2, 0xCF56,	0x67B3, 0xCF4C, 0x67B4, 0xAC62, 0x67B5, 0xCF4A, 0x67B6, 0xAC5B,
+	0x67B7, 0xCF45, 0x67B8, 0xAC65, 0x67B9, 0xCF52, 0x67BA, 0xCEFE,	0x67BB, 0xCF41, 0x67C0, 0xCF44, 0x67C1, 0xCEFB, 0x67C2, 0xCF51,
+	0x67C3, 0xCF61, 0x67C4, 0xAC60, 0x67C5, 0xCF46, 0x67C6, 0xCF58,	0x67C8, 0xCEFD, 0x67C9, 0xCF5F, 0x67CA, 0xCF60, 0x67CB, 0xCF63,
+	0x67CC, 0xCF5A, 0x67CD, 0xCF4B, 0x67CE, 0xCF53, 0x67CF, 0xAC66,	0x67D0, 0xAC59, 0x67D1, 0xAC61, 0x67D2, 0xAC6D, 0x67D3, 0xAC56,
+	0x67D4, 0xAC58, 0x67D8, 0xCF43, 0x67D9, 0xAC6A, 0x67DA, 0xAC63,	0x67DB, 0xCF5D, 0x67DC, 0xCF40, 0x67DD, 0xAC6C, 0x67DE, 0xAC67,
+	0x67DF, 0xCF49, 0x67E2, 0xAC6B, 0x67E3, 0xCF50, 0x67E4, 0xCF48,	0x67E5, 0xAC64, 0x67E6, 0xCF5C, 0x67E7, 0xCF54, 0x67E9, 0xAC5E,
+	0x67EA, 0xCF62, 0x67EB, 0xCF47, 0x67EC, 0xAC5A, 0x67ED, 0xCF59,	0x67EE, 0xCF4F, 0x67EF, 0xAC5F, 0x67F0, 0xCF55, 0x67F1, 0xAC57,
+	0x67F2, 0xCEFC, 0x67F3, 0xAC68, 0x67F4, 0xAEE3, 0x67F5, 0xAC5D,	0x67F6, 0xCF4E, 0x67F7, 0xCF4D, 0x67F8, 0xCF42, 0x67FA, 0xCF5E,
+	0x67FC, 0xCF57, 0x67FF, 0xAC55, 0x6812, 0xD1EC, 0x6813, 0xAEEA,	0x6814, 0xD1ED, 0x6816, 0xD1E1, 0x6817, 0xAEDF, 0x6818, 0xAEEB,
+	0x681A, 0xD1DA, 0x681C, 0xD1E3, 0x681D, 0xD1EB, 0x681F, 0xD1D9,	0x6820, 0xD1F4, 0x6821, 0xAED5, 0x6825, 0xD1F3, 0x6826, 0xD1EE,
+	0x6828, 0xD1EF, 0x6829, 0xAEDD, 0x682A, 0xAEE8, 0x682B, 0xD1E5,	0x682D, 0xD1E6, 0x682E, 0xD1F0, 0x682F, 0xD1E7, 0x6831, 0xD1E2,
+	0x6832, 0xD1DC, 0x6833, 0xD1DD, 0x6834, 0xD1EA, 0x6835, 0xD1E4,	0x6838, 0xAED6, 0x6839, 0xAEDA, 0x683A, 0xD1F2, 0x683B, 0xD1DE,
+	0x683C, 0xAEE6, 0x683D, 0xAEE2, 0x6840, 0xAEE5, 0x6841, 0xAEEC,	0x6842, 0xAEDB, 0x6843, 0xAEE7, 0x6844, 0xD1E9, 0x6845, 0xAEE9,
+	0x6846, 0xAED8, 0x6848, 0xAED7, 0x6849, 0xD1DB, 0x684B, 0xD1DF,	0x684C, 0xAEE0, 0x684D, 0xD1F1, 0x684E, 0xD1E8, 0x684F, 0xD1E0,
+	0x6850, 0xAEE4, 0x6851, 0xAEE1, 0x6853, 0xAED9, 0x6854, 0xAEDC,	0x686B, 0xD5C4, 0x686D, 0xD5B4, 0x686E, 0xD5B5, 0x686F, 0xD5B9,
+	0x6871, 0xD5C8, 0x6872, 0xD5C5, 0x6874, 0xD5BE, 0x6875, 0xD5BD,	0x6876, 0xB1ED, 0x6877, 0xD5C1, 0x6878, 0xD5D0, 0x6879, 0xD5B0,
+	0x687B, 0xD5D1, 0x687C, 0xD5C3, 0x687D, 0xD5D5, 0x687E, 0xD5C9,	0x687F, 0xB1EC, 0x6880, 0xD5C7, 0x6881, 0xB1E7, 0x6882, 0xB1FC,
+	0x6883, 0xB1F2, 0x6885, 0xB1F6, 0x6886, 0xB1F5, 0x6887, 0xD5B1,	0x6889, 0xD5CE, 0x688A, 0xD5D4, 0x688B, 0xD5CC, 0x688C, 0xD5D3,
+	0x688F, 0xD5C0, 0x6890, 0xD5B2, 0x6891, 0xD5D2, 0x6892, 0xD5C2,	0x6893, 0xB1EA, 0x6894, 0xB1F7, 0x6896, 0xD5CB, 0x6897, 0xB1F0,
+	0x689B, 0xD5CA, 0x689C, 0xD5B3, 0x689D, 0xB1F8, 0x689F, 0xB1FA,	0x68A0, 0xD5CD, 0x68A1, 0xB1FB, 0x68A2, 0xB1E9, 0x68A3, 0xD5BA,
+	0x68A4, 0xD5CF, 0x68A7, 0xB1EF, 0x68A8, 0xB1F9, 0x68A9, 0xD5BC,	0x68AA, 0xD5C6, 0x68AB, 0xD5B7, 0x68AC, 0xD5BB, 0x68AD, 0xB1F4,
+	0x68AE, 0xD5B6, 0x68AF, 0xB1E8, 0x68B0, 0xB1F1, 0x68B1, 0xB1EE,	0x68B2, 0xD5BF, 0x68B3, 0xAEDE, 0x68B4, 0xD9C0, 0x68B5, 0xB1EB,
+	0x68C4, 0xB1F3, 0x68C6, 0xD9C3, 0x68C7, 0xD9D9, 0x68C8, 0xD9CE,	0x68C9, 0xB4D6, 0x68CB, 0xB4D1, 0x68CC, 0xD9BD, 0x68CD, 0xB4D2,
+	0x68CE, 0xD9CD, 0x68D0, 0xD9C6, 0x68D1, 0xD9D3, 0x68D2, 0xB4CE,	0x68D3, 0xD9AB, 0x68D4, 0xD9D5, 0x68D5, 0xB4C4, 0x68D6, 0xD9B3,
+	0x68D7, 0xB4C7, 0x68D8, 0xB4C6, 0x68DA, 0xB4D7, 0x68DC, 0xD9AD,	0x68DD, 0xD9CF, 0x68DE, 0xD9D0, 0x68DF, 0xB4C9, 0x68E0, 0xB4C5,
+	0x68E1, 0xD9BB, 0x68E3, 0xB4D0, 0x68E4, 0xD9B6, 0x68E6, 0xD9D1,	0x68E7, 0xB4CC, 0x68E8, 0xD9C9, 0x68E9, 0xD9D6, 0x68EA, 0xD9B0,
+	0x68EB, 0xD9B5, 0x68EC, 0xD9AF, 0x68EE, 0xB4CB, 0x68EF, 0xD9C2,	0x68F0, 0xDDDE, 0x68F1, 0xD9B1, 0x68F2, 0xB4CF, 0x68F3, 0xD9BA,
+	0x68F4, 0xD9D2, 0x68F5, 0xB4CA, 0x68F6, 0xD9B7, 0x68F7, 0xD9B4,	0x68F8, 0xD9C5, 0x68F9, 0xB4CD, 0x68FA, 0xB4C3, 0x68FB, 0xB4D9,
+	0x68FC, 0xD9C8, 0x68FD, 0xD9C7, 0x6904, 0xD9AC, 0x6905, 0xB4C8,	0x6906, 0xD9D4, 0x6907, 0xD9BC, 0x6908, 0xD9BE, 0x690A, 0xD9CB,
+	0x690B, 0xD9CA, 0x690C, 0xD9AA, 0x690D, 0xB4D3, 0x690E, 0xB4D5,	0x690F, 0xD9B2, 0x6910, 0xD9B9, 0x6911, 0xD9C1, 0x6912, 0xB4D4,
+	0x6913, 0xD9B8, 0x6914, 0xD9C4, 0x6915, 0xD9D7, 0x6917, 0xD9CC,	0x6925, 0xD9D8, 0x692A, 0xD9AE, 0x692F, 0xDDF2, 0x6930, 0xB7A6,
+	0x6932, 0xDDF0, 0x6933, 0xDDDB, 0x6934, 0xDDE0, 0x6935, 0xDDD9,	0x6937, 0xDDEC, 0x6938, 0xDDCB, 0x6939, 0xDDD2, 0x693B, 0xDDEA,
+	0x693C, 0xDDF4, 0x693D, 0xDDDC, 0x693F, 0xDDCF, 0x6940, 0xDDE2,	0x6941, 0xDDE7, 0x6942, 0xDDD3, 0x6944, 0xDDE4, 0x6945, 0xDDD0,
+	0x6948, 0xDDD7, 0x6949, 0xDDD8, 0x694A, 0xB7A8, 0x694B, 0xDDEB,	0x694C, 0xDDE9, 0x694E, 0xDDCC, 0x694F, 0xDDEE, 0x6951, 0xDDEF,
+	0x6952, 0xDDF1, 0x6953, 0xB7AC, 0x6954, 0xB7A4, 0x6956, 0xD5B8,	0x6957, 0xDDD4, 0x6958, 0xDDE6, 0x6959, 0xDDD5, 0x695A, 0xB7A1,
+	0x695B, 0xB7B1, 0x695C, 0xDDED, 0x695D, 0xB7AF, 0x695E, 0xB7AB,	0x695F, 0xDDCA, 0x6960, 0xB7A3, 0x6962, 0xDDCD, 0x6963, 0xB7B0,
+	0x6965, 0xDDDD, 0x6966, 0xDDC9, 0x6968, 0xB7A9, 0x6969, 0xDDE1,	0x696A, 0xDDD1, 0x696B, 0xB7AA, 0x696C, 0xDDDA, 0x696D, 0xB77E,
+	0x696E, 0xB4D8, 0x696F, 0xDDE3, 0x6970, 0xD9BF, 0x6971, 0xDDCE,	0x6974, 0xDDE8, 0x6975, 0xB7A5, 0x6976, 0xDDE5, 0x6977, 0xB7A2,
+	0x6978, 0xDDDF, 0x6979, 0xB7AD, 0x697A, 0xDDD6, 0x697B, 0xDDF3,	0x6982, 0xB7A7, 0x6983, 0xDEC6, 0x6986, 0xB7AE, 0x698D, 0xE24A,
+	0x698E, 0xE248, 0x6990, 0xE25E, 0x6991, 0xE246, 0x6993, 0xE258,	0x6994, 0xB77D, 0x6995, 0xBA5F, 0x6996, 0xE242, 0x6997, 0xE25D,
+	0x6999, 0xE247, 0x699A, 0xE255, 0x699B, 0xBA64, 0x699C, 0xBA5D,	0x699E, 0xE25B, 0x69A0, 0xE240, 0x69A1, 0xE25A, 0x69A3, 0xBA6F,
+	0x69A4, 0xE251, 0x69A5, 0xE261, 0x69A6, 0xBA6D, 0x69A7, 0xE249,	0x69A8, 0xBA5E, 0x69A9, 0xE24B, 0x69AA, 0xE259, 0x69AB, 0xBA67,
+	0x69AC, 0xE244, 0x69AD, 0xBA6B, 0x69AE, 0xBA61, 0x69AF, 0xE24D,	0x69B0, 0xE243, 0x69B1, 0xE1FC, 0x69B3, 0xE257, 0x69B4, 0xBA68,
+	0x69B5, 0xE260, 0x69B6, 0xE1FD, 0x69B7, 0xBA65, 0x69B9, 0xE253,	0x69BB, 0xBA66, 0x69BC, 0xE245, 0x69BD, 0xE250, 0x69BE, 0xE24C,
+	0x69BF, 0xE24E, 0x69C1, 0xBA60, 0x69C2, 0xE25F, 0x69C3, 0xBA6E,	0x69C4, 0xE24F, 0x69C6, 0xE262, 0x69C9, 0xE1FE, 0x69CA, 0xE254,
+	0x69CB, 0xBA63, 0x69CC, 0xBA6C, 0x69CD, 0xBA6A, 0x69CE, 0xE241,	0x69CF, 0xE256, 0x69D0, 0xBA69, 0x69D3, 0xBA62, 0x69D4, 0xE252,
+	0x69D9, 0xE25C, 0x69E2, 0xE5D5, 0x69E4, 0xE5D1, 0x69E5, 0xE5CD,	0x69E6, 0xE5E1, 0x69E7, 0xE5DE, 0x69E8, 0xBCCD, 0x69EB, 0xE5E5,
+	0x69EC, 0xE5D4, 0x69ED, 0xBCD8, 0x69EE, 0xE5DB, 0x69F1, 0xE5D0,	0x69F2, 0xE5DA, 0x69F3, 0xBCD5, 0x69F4, 0xE5EE, 0x69F6, 0xE5EB,
+	0x69F7, 0xE5DD, 0x69F8, 0xE5CE, 0x69FB, 0xE5E2, 0x69FC, 0xE5E4,	0x69FD, 0xBCD1, 0x69FE, 0xE5D8, 0x69FF, 0xE5D3, 0x6A00, 0xE5CA,
+	0x6A01, 0xBCCE, 0x6A02, 0xBCD6, 0x6A04, 0xE5E7, 0x6A05, 0xBCD7,	0x6A06, 0xE5CB, 0x6A07, 0xE5ED, 0x6A08, 0xE5E0, 0x6A09, 0xE5E6,
+	0x6A0A, 0xBCD4, 0x6A0D, 0xE5E3, 0x6A0F, 0xE5EA, 0x6A11, 0xBCD9,	0x6A13, 0xBCD3, 0x6A14, 0xE5DC, 0x6A15, 0xE5CF, 0x6A16, 0xE5EF,
+	0x6A17, 0xE5CC, 0x6A18, 0xE5E8, 0x6A19, 0xBCD0, 0x6A1B, 0xE5D6,	0x6A1D, 0xE5D7, 0x6A1E, 0xBCCF, 0x6A1F, 0xBCCC, 0x6A20, 0xE5D2,
+	0x6A21, 0xBCD2, 0x6A23, 0xBCCB, 0x6A25, 0xE5E9, 0x6A26, 0xE5EC,	0x6A27, 0xE5D9, 0x6A28, 0xE9CA, 0x6A32, 0xE9C2, 0x6A34, 0xE9BE,
+	0x6A35, 0xBEF6, 0x6A38, 0xBEEB, 0x6A39, 0xBEF0, 0x6A3A, 0xBEEC,	0x6A3B, 0xE9CC, 0x6A3C, 0xE9D7, 0x6A3D, 0xBEEA, 0x6A3E, 0xE9C4,
+	0x6A3F, 0xE9CD, 0x6A40, 0xE5DF, 0x6A41, 0xE9CE, 0x6A44, 0xBEF1,	0x6A46, 0xE9DD, 0x6A47, 0xBEF5, 0x6A48, 0xBEF8, 0x6A49, 0xE9C0,
+	0x6A4B, 0xBEF4, 0x6A4D, 0xE9DB, 0x6A4E, 0xE9DC, 0x6A4F, 0xE9D2,	0x6A50, 0xE9D1, 0x6A51, 0xE9C9, 0x6A54, 0xE9D3, 0x6A55, 0xE9DA,
+	0x6A56, 0xE9D9, 0x6A58, 0xBEEF, 0x6A59, 0xBEED, 0x6A5A, 0xE9CB,	0x6A5B, 0xE9C8, 0x6A5D, 0xE9C5, 0x6A5E, 0xE9D8, 0x6A5F, 0xBEF7,
+	0x6A60, 0xE9D6, 0x6A61, 0xBEF3, 0x6A62, 0xBEF2, 0x6A64, 0xE9D0,	0x6A66, 0xE9BF, 0x6A67, 0xE9C1, 0x6A68, 0xE9C3, 0x6A69, 0xE9D5,
+	0x6A6A, 0xE9CF, 0x6A6B, 0xBEEE, 0x6A6D, 0xE9C6, 0x6A6F, 0xE9D4,	0x6A76, 0xE9C7, 0x6A7E, 0xC0CF, 0x6A7F, 0xED45, 0x6A80, 0xC0C8,
+	0x6A81, 0xECF5, 0x6A83, 0xED41, 0x6A84, 0xC0CA, 0x6A85, 0xED48,	0x6A87, 0xECFC, 0x6A89, 0xECF7, 0x6A8C, 0xED49, 0x6A8D, 0xECF3,
+	0x6A8E, 0xECFE, 0x6A90, 0xC0D1, 0x6A91, 0xED44, 0x6A92, 0xED4A,	0x6A93, 0xECFD, 0x6A94, 0xC0C9, 0x6A95, 0xED40, 0x6A96, 0xECF4,
+	0x6A97, 0xC0D0, 0x6A9A, 0xED47, 0x6A9B, 0xECF9, 0x6A9C, 0xC0CC,	0x6A9E, 0xECFB, 0x6A9F, 0xECF8, 0x6AA0, 0xC0D2, 0x6AA1, 0xECFA,
+	0x6AA2, 0xC0CB, 0x6AA3, 0xC0CE, 0x6AA4, 0xED43, 0x6AA5, 0xECF6,	0x6AA6, 0xED46, 0x6AA8, 0xED42, 0x6AAC, 0xC263, 0x6AAD, 0xEFE7,
+	0x6AAE, 0xC268, 0x6AAF, 0xC269, 0x6AB3, 0xC262, 0x6AB4, 0xEFE6,	0x6AB6, 0xEFE3, 0x6AB7, 0xEFE4, 0x6AB8, 0xC266, 0x6AB9, 0xEFDE,
+	0x6ABA, 0xEFE2, 0x6ABB, 0xC265, 0x6ABD, 0xEFDF, 0x6AC2, 0xC267,	0x6AC3, 0xC264, 0x6AC5, 0xEFDD, 0x6AC6, 0xEFE1, 0x6AC7, 0xEFE5,
+	0x6ACB, 0xF251, 0x6ACC, 0xF24E, 0x6ACD, 0xF257, 0x6ACF, 0xF256,	0x6AD0, 0xF254, 0x6AD1, 0xF24F, 0x6AD3, 0xC372, 0x6AD9, 0xF250,
+	0x6ADA, 0xC371, 0x6ADB, 0xC0CD, 0x6ADC, 0xF253, 0x6ADD, 0xC370,	0x6ADE, 0xF258, 0x6ADF, 0xF252, 0x6AE0, 0xF24D, 0x6AE1, 0xEFE0,
+	0x6AE5, 0xC36F, 0x6AE7, 0xF24C, 0x6AE8, 0xF456, 0x6AEA, 0xF455,	0x6AEB, 0xF255, 0x6AEC, 0xC468, 0x6AEE, 0xF459, 0x6AEF, 0xF45A,
+	0x6AF0, 0xF454, 0x6AF1, 0xF458, 0x6AF3, 0xF453, 0x6AF8, 0xF5D1,	0x6AF9, 0xF457, 0x6AFA, 0xC4E7, 0x6AFB, 0xC4E5, 0x6AFC, 0xF5CF,
+	0x6B00, 0xF5D2, 0x6B02, 0xF5CE, 0x6B03, 0xF5D0, 0x6B04, 0xC4E6,	0x6B08, 0xF6E5, 0x6B09, 0xF6E6, 0x6B0A, 0xC576, 0x6B0B, 0xF6E4,
+	0x6B0F, 0xF7E2, 0x6B10, 0xC5CF, 0x6B11, 0xF7E0, 0x6B12, 0xF7E1,	0x6B13, 0xF8AC, 0x6B16, 0xC656, 0x6B17, 0xF8F3, 0x6B18, 0xF8F1,
+	0x6B19, 0xF8F2, 0x6B1A, 0xF8F4, 0x6B1E, 0xF9BB, 0x6B20, 0xA4ED,	0x6B21, 0xA6B8, 0x6B23, 0xAA59, 0x6B25, 0xCCE9, 0x6B28, 0xCF64,
+	0x6B2C, 0xD1F5, 0x6B2D, 0xD1F7, 0x6B2F, 0xD1F6, 0x6B31, 0xD1F8,	0x6B32, 0xB1FD, 0x6B33, 0xD5D7, 0x6B34, 0xD1F9, 0x6B36, 0xD5D6,
+	0x6B37, 0xD5D8, 0x6B38, 0xD5D9, 0x6B39, 0xD9DA, 0x6B3A, 0xB4DB,	0x6B3B, 0xD9DB, 0x6B3C, 0xD9DD, 0x6B3D, 0xB4DC, 0x6B3E, 0xB4DA,
+	0x6B3F, 0xD9DC, 0x6B41, 0xDDFA, 0x6B42, 0xDDF8, 0x6B43, 0xDDF7,	0x6B45, 0xDDF6, 0x6B46, 0xDDF5, 0x6B47, 0xB7B2, 0x6B48, 0xDDF9,
+	0x6B49, 0xBA70, 0x6B4A, 0xE263, 0x6B4B, 0xE265, 0x6B4C, 0xBA71,	0x6B4D, 0xE264, 0x6B4E, 0xBCDB, 0x6B50, 0xBCDA, 0x6B51, 0xE5F0,
+	0x6B54, 0xE9DF, 0x6B55, 0xE9DE, 0x6B56, 0xE9E0, 0x6B59, 0xBEF9,	0x6B5B, 0xED4B, 0x6B5C, 0xC0D3, 0x6B5E, 0xEFE8, 0x6B5F, 0xC26A,
+	0x6B60, 0xF259, 0x6B61, 0xC577, 0x6B62, 0xA4EE, 0x6B63, 0xA5BF,	0x6B64, 0xA6B9, 0x6B65, 0xA842, 0x6B66, 0xAA5A, 0x6B67, 0xAA5B,
+	0x6B6A, 0xAC6E, 0x6B6D, 0xD1FA, 0x6B72, 0xB7B3, 0x6B76, 0xE6D1,	0x6B77, 0xBEFA, 0x6B78, 0xC26B, 0x6B79, 0xA4EF, 0x6B7B, 0xA6BA,
+	0x6B7E, 0xCCEB, 0x6B7F, 0xAA5C, 0x6B80, 0xCCEA, 0x6B82, 0xCF65,	0x6B83, 0xAC6F, 0x6B84, 0xCF66, 0x6B86, 0xAC70, 0x6B88, 0xD1FC,
+	0x6B89, 0xAEEE, 0x6B8A, 0xAEED, 0x6B8C, 0xD5DE, 0x6B8D, 0xD5DC,	0x6B8E, 0xD5DD, 0x6B8F, 0xD5DB, 0x6B91, 0xD5DA, 0x6B94, 0xD9DE,
+	0x6B95, 0xD9E1, 0x6B96, 0xB4DE, 0x6B97, 0xD9DF, 0x6B98, 0xB4DD,	0x6B99, 0xD9E0, 0x6B9B, 0xDDFB, 0x6B9E, 0xE266, 0x6B9F, 0xE267,
+	0x6BA0, 0xE268, 0x6BA2, 0xE5F3, 0x6BA3, 0xE5F2, 0x6BA4, 0xBCDC,	0x6BA5, 0xE5F1, 0x6BA6, 0xE5F4, 0x6BA7, 0xE9E1, 0x6BAA, 0xE9E2,
+	0x6BAB, 0xE9E3, 0x6BAD, 0xED4C, 0x6BAE, 0xC0D4, 0x6BAF, 0xC26C,	0x6BB0, 0xF25A, 0x6BB2, 0xC4E8, 0x6BB3, 0xC95F, 0x6BB5, 0xAC71,
+	0x6BB6, 0xCF67, 0x6BB7, 0xAEEF, 0x6BBA, 0xB1FE, 0x6BBC, 0xB4DF,	0x6BBD, 0xD9E2, 0x6BBF, 0xB7B5, 0x6BC0, 0xB7B4, 0x6BC3, 0xE269,
+	0x6BC4, 0xE26A, 0x6BC5, 0xBCDD, 0x6BC6, 0xBCDE, 0x6BC7, 0xE9E5,	0x6BC8, 0xE9E4, 0x6BC9, 0xEFE9, 0x6BCA, 0xF7E3, 0x6BCB, 0xA4F0,
+	0x6BCC, 0xC960, 0x6BCD, 0xA5C0, 0x6BCF, 0xA843, 0x6BD0, 0xCB48,	0x6BD2, 0xAC72, 0x6BD3, 0xB7B6, 0x6BD4, 0xA4F1, 0x6BD6, 0xCF68,
+	0x6BD7, 0xAC73, 0x6BD8, 0xCF69, 0x6BDA, 0xC0D5, 0x6BDB, 0xA4F2,	0x6BDE, 0xCCEC, 0x6BE0, 0xCF6A, 0x6BE2, 0xD242, 0x6BE3, 0xD241,
+	0x6BE4, 0xD1FE, 0x6BE6, 0xD1FD, 0x6BE7, 0xD243, 0x6BE8, 0xD240,	0x6BEB, 0xB240, 0x6BEC, 0xB241, 0x6BEF, 0xB4E0, 0x6BF0, 0xD9E3,
+	0x6BF2, 0xD9E4, 0x6BF3, 0xD9E5, 0x6BF7, 0xDE41, 0x6BF8, 0xDE42,	0x6BF9, 0xDE40, 0x6BFB, 0xDDFD, 0x6BFC, 0xDDFE, 0x6BFD, 0xB7B7,
+	0x6BFE, 0xE26B, 0x6BFF, 0xE5F7, 0x6C00, 0xE5F6, 0x6C01, 0xE5F5,	0x6C02, 0xE5F8, 0x6C03, 0xE9E7, 0x6C04, 0xE9E6, 0x6C05, 0xBEFB,
+	0x6C06, 0xE9E8, 0x6C08, 0xC0D6, 0x6C09, 0xED4D, 0x6C0B, 0xEFEA,	0x6C0C, 0xF25B, 0x6C0D, 0xF6E7, 0x6C0F, 0xA4F3, 0x6C10, 0xA5C2,
+	0x6C11, 0xA5C1, 0x6C13, 0xAA5D, 0x6C14, 0xC961, 0x6C15, 0xC97E,	0x6C16, 0xA6BB, 0x6C18, 0xC9F7, 0x6C19, 0xCB49, 0x6C1A, 0xCB4A,
+	0x6C1B, 0xAA5E, 0x6C1D, 0xCCED, 0x6C1F, 0xAC74, 0x6C20, 0xCF6B,	0x6C21, 0xCF6C, 0x6C23, 0xAEF0, 0x6C24, 0xAEF4, 0x6C25, 0xD244,
+	0x6C26, 0xAEF3, 0x6C27, 0xAEF1, 0x6C28, 0xAEF2, 0x6C2A, 0xD5DF,	0x6C2B, 0xB242, 0x6C2C, 0xB4E3, 0x6C2E, 0xB4E1, 0x6C2F, 0xB4E2,
+	0x6C30, 0xD9E6, 0x6C33, 0xBA72, 0x6C34, 0xA4F4, 0x6C36, 0xC9A1,	0x6C38, 0xA5C3, 0x6C3B, 0xC9A4, 0x6C3E, 0xA5C6, 0x6C3F, 0xC9A3,
+	0x6C40, 0xA5C5, 0x6C41, 0xA5C4, 0x6C42, 0xA844, 0x6C43, 0xC9A2,	0x6C46, 0xC9F8, 0x6C4A, 0xC9FC, 0x6C4B, 0xC9FE, 0x6C4C, 0xCA40,
+	0x6C4D, 0xA6C5, 0x6C4E, 0xA6C6, 0x6C4F, 0xC9FB, 0x6C50, 0xA6C1,	0x6C52, 0xC9F9, 0x6C54, 0xC9FD, 0x6C55, 0xA6C2, 0x6C57, 0xA6BD,
+	0x6C59, 0xA6BE, 0x6C5B, 0xA6C4, 0x6C5C, 0xC9FA, 0x6C5D, 0xA6BC,	0x6C5E, 0xA845, 0x6C5F, 0xA6BF, 0x6C60, 0xA6C0, 0x6C61, 0xA6C3,
+	0x6C65, 0xCB5B, 0x6C66, 0xCB59, 0x6C67, 0xCB4C, 0x6C68, 0xA851,	0x6C69, 0xCB53, 0x6C6A, 0xA84C, 0x6C6B, 0xCB4D, 0x6C6D, 0xCB55,
+	0x6C6F, 0xCB52, 0x6C70, 0xA84F, 0x6C71, 0xCB51, 0x6C72, 0xA856,	0x6C73, 0xCB5A, 0x6C74, 0xA858, 0x6C76, 0xA85A, 0x6C78, 0xCB4B,
+	0x6C7A, 0xA84D, 0x6C7B, 0xCB5C, 0x6C7D, 0xA854, 0x6C7E, 0xA857,	0x6C80, 0xCD45, 0x6C81, 0xA847, 0x6C82, 0xA85E, 0x6C83, 0xA855,
+	0x6C84, 0xCB4E, 0x6C85, 0xA84A, 0x6C86, 0xA859, 0x6C87, 0xCB56,	0x6C88, 0xA848, 0x6C89, 0xA849, 0x6C8A, 0xCD43, 0x6C8B, 0xCB4F,
+	0x6C8C, 0xA850, 0x6C8D, 0xA85B, 0x6C8E, 0xCB5D, 0x6C8F, 0xCB50,	0x6C90, 0xA84E, 0x6C92, 0xA853, 0x6C93, 0xCCEE, 0x6C94, 0xA85C,
+	0x6C95, 0xCB57, 0x6C96, 0xA852, 0x6C98, 0xA85D, 0x6C99, 0xA846,	0x6C9A, 0xCB54, 0x6C9B, 0xA84B, 0x6C9C, 0xCB58, 0x6C9D, 0xCD44,
+	0x6CAB, 0xAA6A, 0x6CAC, 0xAA7A, 0x6CAD, 0xCCF5, 0x6CAE, 0xAA71,	0x6CB0, 0xCD4B, 0x6CB1, 0xAA62, 0x6CB3, 0xAA65, 0x6CB4, 0xCD42,
+	0x6CB6, 0xCCF3, 0x6CB7, 0xCCF7, 0x6CB8, 0xAA6D, 0x6CB9, 0xAA6F,	0x6CBA, 0xCCFA, 0x6CBB, 0xAA76, 0x6CBC, 0xAA68, 0x6CBD, 0xAA66,
+	0x6CBE, 0xAA67, 0x6CBF, 0xAA75, 0x6CC0, 0xCD47, 0x6CC1, 0xAA70,	0x6CC2, 0xCCF9, 0x6CC3, 0xCCFB, 0x6CC4, 0xAA6E, 0x6CC5, 0xAA73,
+	0x6CC6, 0xCCFC, 0x6CC7, 0xCD4A, 0x6CC9, 0xAC75, 0x6CCA, 0xAA79,	0x6CCC, 0xAA63, 0x6CCD, 0xCD49, 0x6CCF, 0xCD4D, 0x6CD0, 0xCCF8,
+	0x6CD1, 0xCD4F, 0x6CD2, 0xCD40, 0x6CD3, 0xAA6C, 0x6CD4, 0xCCF4,	0x6CD5, 0xAA6B, 0x6CD6, 0xAA7D, 0x6CD7, 0xAA72, 0x6CD9, 0xCCF2,
+	0x6CDA, 0xCF75, 0x6CDB, 0xAA78, 0x6CDC, 0xAA7C, 0x6CDD, 0xCD41,	0x6CDE, 0xCD46, 0x6CE0, 0xAA7E, 0x6CE1, 0xAA77, 0x6CE2, 0xAA69,
+	0x6CE3, 0xAA5F, 0x6CE5, 0xAA64, 0x6CE7, 0xCCF6, 0x6CE8, 0xAA60,	0x6CE9, 0xCD4E, 0x6CEB, 0xCCF0, 0x6CEC, 0xCCEF, 0x6CED, 0xCCFD,
+	0x6CEE, 0xCCF1, 0x6CEF, 0xAA7B, 0x6CF0, 0xAEF5, 0x6CF1, 0xAA74,	0x6CF2, 0xCCFE, 0x6CF3, 0xAA61, 0x6CF5, 0xACA6, 0x6CF9, 0xCD4C,
+	0x6D00, 0xCF7C, 0x6D01, 0xCFA1, 0x6D03, 0xCFA4, 0x6D04, 0xCF77,	0x6D07, 0xCFA7, 0x6D08, 0xCFAA, 0x6D09, 0xCFAC, 0x6D0A, 0xCF74,
+	0x6D0B, 0xAC76, 0x6D0C, 0xAC7B, 0x6D0D, 0xD249, 0x6D0E, 0xACAD,	0x6D0F, 0xCFA5, 0x6D10, 0xCFAD, 0x6D11, 0xCF7B, 0x6D12, 0xCF73,
+	0x6D16, 0xD264, 0x6D17, 0xAC7E, 0x6D18, 0xCFA2, 0x6D19, 0xCF78,	0x6D1A, 0xCF7A, 0x6D1B, 0xACA5, 0x6D1D, 0xCF7D, 0x6D1E, 0xAC7D,
+	0x6D1F, 0xCF70, 0x6D20, 0xCFA8, 0x6D22, 0xCFAB, 0x6D25, 0xAC7A,	0x6D27, 0xACA8, 0x6D28, 0xCF6D, 0x6D29, 0xACAA, 0x6D2A, 0xAC78,
+	0x6D2B, 0xACAE, 0x6D2C, 0xCFA9, 0x6D2D, 0xCF6F, 0x6D2E, 0xACAB,	0x6D2F, 0xD25E, 0x6D30, 0xCD48, 0x6D31, 0xAC7C, 0x6D32, 0xAC77,
+	0x6D33, 0xCF76, 0x6D34, 0xCF6E, 0x6D35, 0xACAC, 0x6D36, 0xACA4,	0x6D37, 0xCFA3, 0x6D38, 0xACA9, 0x6D39, 0xACA7, 0x6D3A, 0xCF79,
+	0x6D3B, 0xACA1, 0x6D3C, 0xCF71, 0x6D3D, 0xACA2, 0x6D3E, 0xACA3,	0x6D3F, 0xCF72, 0x6D40, 0xCFA6, 0x6D41, 0xAC79, 0x6D42, 0xCF7E,
+	0x6D58, 0xD24C, 0x6D59, 0xAEFD, 0x6D5A, 0xAF43, 0x6D5E, 0xD255,	0x6D5F, 0xD25B, 0x6D60, 0xD257, 0x6D61, 0xD24A, 0x6D62, 0xD24D,
+	0x6D63, 0xD246, 0x6D64, 0xD247, 0x6D65, 0xAF4A, 0x6D66, 0xAEFA,	0x6D67, 0xD256, 0x6D68, 0xD25F, 0x6D69, 0xAF45, 0x6D6A, 0xAEF6,
+	0x6D6C, 0xAF40, 0x6D6D, 0xD24E, 0x6D6E, 0xAF42, 0x6D6F, 0xD24F,	0x6D70, 0xD259, 0x6D74, 0xAF44, 0x6D75, 0xD268, 0x6D76, 0xD248,
+	0x6D77, 0xAEFC, 0x6D78, 0xAEFB, 0x6D79, 0xAF48, 0x6D7A, 0xD245,	0x6D7B, 0xD266, 0x6D7C, 0xD25A, 0x6D7D, 0xD267, 0x6D7E, 0xD261,
+	0x6D7F, 0xD253, 0x6D80, 0xD262, 0x6D82, 0xD25C, 0x6D83, 0xD265,	0x6D84, 0xD263, 0x6D85, 0xAF49, 0x6D86, 0xD254, 0x6D87, 0xAEF9,
+	0x6D88, 0xAEF8, 0x6D89, 0xAF41, 0x6D8A, 0xAF47, 0x6D8B, 0xD260,	0x6D8C, 0xAF46, 0x6D8D, 0xD251, 0x6D8E, 0xB243, 0x6D90, 0xD269,
+	0x6D91, 0xD250, 0x6D92, 0xD24B, 0x6D93, 0xAEFE, 0x6D94, 0xAF4B,	0x6D95, 0xAEF7, 0x6D97, 0xD258, 0x6D98, 0xD25D, 0x6DAA, 0xB265,
+	0x6DAB, 0xD5E1, 0x6DAC, 0xD5E5, 0x6DAE, 0xB252, 0x6DAF, 0xB250,	0x6DB2, 0xB247, 0x6DB3, 0xD5E3, 0x6DB4, 0xD5E2, 0x6DB5, 0xB25B,
+	0x6DB7, 0xD5E8, 0x6DB8, 0xB255, 0x6DBA, 0xD5FA, 0x6DBB, 0xD647,	0x6DBC, 0xB244, 0x6DBD, 0xD5F7, 0x6DBE, 0xD5F0, 0x6DBF, 0xB267,
+	0x6DC0, 0xD5E0, 0x6DC2, 0xD5FC, 0x6DC4, 0xB264, 0x6DC5, 0xB258,	0x6DC6, 0xB263, 0x6DC7, 0xB24E, 0x6DC8, 0xD5EC, 0x6DC9, 0xD5FE,
+	0x6DCA, 0xD5F6, 0x6DCB, 0xB24F, 0x6DCC, 0xB249, 0x6DCD, 0xD645,	0x6DCF, 0xD5FD, 0x6DD0, 0xD640, 0x6DD1, 0xB251, 0x6DD2, 0xB259,
+	0x6DD3, 0xD642, 0x6DD4, 0xD5EA, 0x6DD5, 0xD5FB, 0x6DD6, 0xD5EF,	0x6DD7, 0xD644, 0x6DD8, 0xB25E, 0x6DD9, 0xB246, 0x6DDA, 0xB25C,
+	0x6DDB, 0xD5F4, 0x6DDC, 0xD5F2, 0x6DDD, 0xD5F3, 0x6DDE, 0xB253,	0x6DDF, 0xD5EE, 0x6DE0, 0xD5ED, 0x6DE1, 0xB248, 0x6DE2, 0xD5E7,
+	0x6DE3, 0xD646, 0x6DE4, 0xB24A, 0x6DE5, 0xD5F1, 0x6DE6, 0xB268,	0x6DE8, 0xB262, 0x6DE9, 0xD5E6, 0x6DEA, 0xB25F, 0x6DEB, 0xB25D,
+	0x6DEC, 0xB266, 0x6DED, 0xD5F8, 0x6DEE, 0xB261, 0x6DEF, 0xD252,	0x6DF0, 0xD5F9, 0x6DF1, 0xB260, 0x6DF2, 0xD641, 0x6DF3, 0xB245,
+	0x6DF4, 0xD5F5, 0x6DF5, 0xB257, 0x6DF6, 0xD5E9, 0x6DF7, 0xB256,	0x6DF9, 0xB254, 0x6DFA, 0xB24C, 0x6DFB, 0xB24B, 0x6DFC, 0xD9E7,
+	0x6DFD, 0xD643, 0x6E00, 0xD5EB, 0x6E03, 0xD9FC, 0x6E05, 0xB24D,	0x6E19, 0xB541, 0x6E1A, 0xB25A, 0x6E1B, 0xB4EE, 0x6E1C, 0xD9F6,
+	0x6E1D, 0xB4FC, 0x6E1F, 0xD9EA, 0x6E20, 0xB4EB, 0x6E21, 0xB4E7,	0x6E22, 0xDA49, 0x6E23, 0xB4ED, 0x6E24, 0xB4F1, 0x6E25, 0xB4EC,
+	0x6E26, 0xB4F5, 0x6E27, 0xDA4D, 0x6E28, 0xDA44, 0x6E2B, 0xD9F1,	0x6E2C, 0xB4FA, 0x6E2D, 0xB4F4, 0x6E2E, 0xD9FD, 0x6E2F, 0xB4E4,
+	0x6E30, 0xDA4A, 0x6E31, 0xDA43, 0x6E32, 0xB4E8, 0x6E33, 0xD9F7,	0x6E34, 0xB4F7, 0x6E35, 0xDA55, 0x6E36, 0xDA56, 0x6E38, 0xB4E5,
+	0x6E39, 0xDA48, 0x6E3A, 0xB4F9, 0x6E3B, 0xD9FB, 0x6E3C, 0xD9ED,	0x6E3D, 0xD9EE, 0x6E3E, 0xB4FD, 0x6E3F, 0xD9F2, 0x6E40, 0xD9F9,
+	0x6E41, 0xD9F3, 0x6E43, 0xB4FB, 0x6E44, 0xB544, 0x6E45, 0xD9EF,	0x6E46, 0xD9E8, 0x6E47, 0xD9E9, 0x6E49, 0xD9EB, 0x6E4A, 0xB4EA,
+	0x6E4B, 0xD9F8, 0x6E4D, 0xB4F8, 0x6E4E, 0xB542, 0x6E51, 0xD9FA,	0x6E52, 0xDA53, 0x6E53, 0xDA4B, 0x6E54, 0xB4E6, 0x6E55, 0xDA51,
+	0x6E56, 0xB4F2, 0x6E58, 0xB4F0, 0x6E5A, 0xDA57, 0x6E5B, 0xB4EF,	0x6E5C, 0xDA41, 0x6E5D, 0xD9F4, 0x6E5E, 0xD9FE, 0x6E5F, 0xB547,
+	0x6E60, 0xDA45, 0x6E61, 0xDA42, 0x6E62, 0xD9F0, 0x6E63, 0xB543,	0x6E64, 0xDA4F, 0x6E65, 0xDA4C, 0x6E66, 0xDA54, 0x6E67, 0xB4E9,
+	0x6E68, 0xDA40, 0x6E69, 0xB546, 0x6E6B, 0xDA47, 0x6E6E, 0xB4F3,	0x6E6F, 0xB4F6, 0x6E71, 0xDA46, 0x6E72, 0xB545, 0x6E73, 0xD9F5,
+	0x6E74, 0xD5E4, 0x6E77, 0xDA50, 0x6E78, 0xDA4E, 0x6E79, 0xDA52,	0x6E88, 0xD9EC, 0x6E89, 0xB540, 0x6E8D, 0xDE61, 0x6E8E, 0xDE60,
+	0x6E8F, 0xDE46, 0x6E90, 0xB7BD, 0x6E92, 0xDE5F, 0x6E93, 0xDE49,	0x6E94, 0xDE4A, 0x6E96, 0xB7C7, 0x6E97, 0xDE68, 0x6E98, 0xB7C2,
+	0x6E99, 0xDE5E, 0x6E9B, 0xDE43, 0x6E9C, 0xB7C8, 0x6E9D, 0xB7BE,	0x6E9E, 0xDE52, 0x6E9F, 0xDE48, 0x6EA0, 0xDE4B, 0x6EA1, 0xDE63,
+	0x6EA2, 0xB7B8, 0x6EA3, 0xDE6A, 0x6EA4, 0xDE62, 0x6EA5, 0xB7C1,	0x6EA6, 0xDE57, 0x6EA7, 0xB7CC, 0x6EAA, 0xB7CB, 0x6EAB, 0xB7C5,
+	0x6EAE, 0xDE69, 0x6EAF, 0xB7B9, 0x6EB0, 0xDE55, 0x6EB1, 0xDE4C,	0x6EB2, 0xDE59, 0x6EB3, 0xDE65, 0x6EB4, 0xB7CD, 0x6EB6, 0xB7BB,
+	0x6EB7, 0xDE54, 0x6EB9, 0xDE4D, 0x6EBA, 0xB7C4, 0x6EBC, 0xB7C3,	0x6EBD, 0xDE50, 0x6EBE, 0xDE5A, 0x6EBF, 0xDE64, 0x6EC0, 0xDE47,
+	0x6EC1, 0xDE51, 0x6EC2, 0xB7BC, 0x6EC3, 0xDE5B, 0x6EC4, 0xB7C9,	0x6EC5, 0xB7C0, 0x6EC6, 0xDE4E, 0x6EC7, 0xB7BF, 0x6EC8, 0xDE45,
+	0x6EC9, 0xDE53, 0x6ECA, 0xDE67, 0x6ECB, 0xB4FE, 0x6ECC, 0xBAB0,	0x6ECD, 0xDE56, 0x6ECE, 0xE26C, 0x6ECF, 0xDE58, 0x6ED0, 0xDE66,
+	0x6ED1, 0xB7C6, 0x6ED2, 0xDE4F, 0x6ED3, 0xB7BA, 0x6ED4, 0xB7CA,	0x6ED5, 0xBCF0, 0x6ED6, 0xDE44, 0x6ED8, 0xDE5D, 0x6EDC, 0xDE5C,
+	0x6EEB, 0xE2AA, 0x6EEC, 0xBAAD, 0x6EED, 0xE27D, 0x6EEE, 0xE2A4,	0x6EEF, 0xBAA2, 0x6EF1, 0xE26E, 0x6EF2, 0xBAAF, 0x6EF4, 0xBA77,
+	0x6EF5, 0xE26D, 0x6EF6, 0xE2B0, 0x6EF7, 0xBAB1, 0x6EF8, 0xE271,	0x6EF9, 0xE2A3, 0x6EFB, 0xE273, 0x6EFC, 0xE2B3, 0x6EFD, 0xE2AF,
+	0x6EFE, 0xBA75, 0x6EFF, 0xBAA1, 0x6F00, 0xE653, 0x6F01, 0xBAAE,	0x6F02, 0xBA7D, 0x6F03, 0xE26F, 0x6F05, 0xE2AE, 0x6F06, 0xBAA3,
+	0x6F07, 0xE2AB, 0x6F08, 0xE2B8, 0x6F09, 0xE275, 0x6F0A, 0xE27E,	0x6F0D, 0xE2B6, 0x6F0E, 0xE2AC, 0x6F0F, 0xBA7C, 0x6F12, 0xE27C,
+	0x6F13, 0xBA76, 0x6F14, 0xBA74, 0x6F15, 0xBAA8, 0x6F18, 0xE27A,	0x6F19, 0xE277, 0x6F1A, 0xE278, 0x6F1C, 0xE2B2, 0x6F1E, 0xE2B7,
+	0x6F1F, 0xE2B5, 0x6F20, 0xBA7A, 0x6F21, 0xE2B9, 0x6F22, 0xBA7E,	0x6F23, 0xBAA7, 0x6F25, 0xE270, 0x6F26, 0xE5FA, 0x6F27, 0xE279,
+	0x6F29, 0xBA78, 0x6F2A, 0xBAAC, 0x6F2B, 0xBAA9, 0x6F2C, 0xBA7B,	0x6F2D, 0xE2A5, 0x6F2E, 0xE274, 0x6F2F, 0xBAAA, 0x6F30, 0xE2A7,
+	0x6F31, 0xBAA4, 0x6F32, 0xBAA6, 0x6F33, 0xBA73, 0x6F35, 0xE2A9,	0x6F36, 0xE2A1, 0x6F37, 0xE272, 0x6F38, 0xBAA5, 0x6F39, 0xE2B1,
+	0x6F3A, 0xE2B4, 0x6F3B, 0xE27B, 0x6F3C, 0xE2A8, 0x6F3E, 0xBA79,	0x6F3F, 0xBCDF, 0x6F40, 0xE2A6, 0x6F41, 0xE5F9, 0x6F43, 0xE2AD,
+	0x6F4E, 0xE276, 0x6F4F, 0xE644, 0x6F50, 0xE64E, 0x6F51, 0xBCE2,	0x6F52, 0xE64D, 0x6F53, 0xE659, 0x6F54, 0xBCE4, 0x6F55, 0xE64B,
+	0x6F57, 0xE64F, 0x6F58, 0xBCEF, 0x6F5A, 0xE646, 0x6F5B, 0xBCE7,	0x6F5D, 0xE652, 0x6F5E, 0xE9F0, 0x6F5F, 0xBCF3, 0x6F60, 0xBCF2,
+	0x6F61, 0xE654, 0x6F62, 0xE643, 0x6F63, 0xE65E, 0x6F64, 0xBCED,	0x6F66, 0xBCE3, 0x6F67, 0xE657, 0x6F69, 0xE65B, 0x6F6A, 0xE660,
+	0x6F6B, 0xE655, 0x6F6C, 0xE649, 0x6F6D, 0xBCE6, 0x6F6E, 0xBCE9,	0x6F6F, 0xBCF1, 0x6F70, 0xBCEC, 0x6F72, 0xE64C, 0x6F73, 0xE2A2,
+	0x6F76, 0xE648, 0x6F77, 0xE65F, 0x6F78, 0xBCE8, 0x6F7A, 0xBCEB,	0x6F7B, 0xE661, 0x6F7C, 0xBCE0, 0x6F7D, 0xE656, 0x6F7E, 0xE5FB,
+	0x6F7F, 0xE65C, 0x6F80, 0xC0DF, 0x6F82, 0xE64A, 0x6F84, 0xBCE1,	0x6F85, 0xE645, 0x6F86, 0xBCE5, 0x6F87, 0xE5FC, 0x6F88, 0xBAAB,
+	0x6F89, 0xE641, 0x6F8B, 0xE65A, 0x6F8C, 0xE642, 0x6F8D, 0xE640,	0x6F8E, 0xBCEA, 0x6F90, 0xE658, 0x6F92, 0xE5FE, 0x6F93, 0xE651,
+	0x6F94, 0xE650, 0x6F95, 0xE65D, 0x6F96, 0xE647, 0x6F97, 0xBCEE,	0x6F9E, 0xE9F3, 0x6FA0, 0xBF49, 0x6FA1, 0xBEFE, 0x6FA2, 0xEA40,
+	0x6FA3, 0xE9EB, 0x6FA4, 0xBF41, 0x6FA5, 0xE9F7, 0x6FA6, 0xBF48,	0x6FA7, 0xBF43, 0x6FA8, 0xE9F5, 0x6FA9, 0xED4F, 0x6FAA, 0xE9FB,
+	0x6FAB, 0xEA42, 0x6FAC, 0xE9FA, 0x6FAD, 0xE9E9, 0x6FAE, 0xE9F8,	0x6FAF, 0xEA44, 0x6FB0, 0xEA46, 0x6FB1, 0xBEFD, 0x6FB2, 0xEA45,
+	0x6FB3, 0xBF44, 0x6FB4, 0xBF4A, 0x6FB6, 0xBF47, 0x6FB8, 0xE9FE,	0x6FB9, 0xBF46, 0x6FBA, 0xE9F9, 0x6FBC, 0xE9ED, 0x6FBD, 0xE9F2,
+	0x6FBF, 0xE9FD, 0x6FC0, 0xBF45, 0x6FC1, 0xBF42, 0x6FC2, 0xBEFC,	0x6FC3, 0xBF40, 0x6FC4, 0xE9F1, 0x6FC6, 0xE5FD, 0x6FC7, 0xE9EC,
+	0x6FC8, 0xE9EF, 0x6FC9, 0xEA41, 0x6FCA, 0xE9F4, 0x6FCB, 0xE9EA,	0x6FCC, 0xED4E, 0x6FCD, 0xEA43, 0x6FCE, 0xE9EE, 0x6FCF, 0xE9FC,
+	0x6FD4, 0xED51, 0x6FD5, 0xC0E3, 0x6FD8, 0xC0D7, 0x6FDB, 0xC0DB,	0x6FDC, 0xED53, 0x6FDD, 0xED59, 0x6FDE, 0xED57, 0x6FDF, 0xC0D9,
+	0x6FE0, 0xC0DA, 0x6FE1, 0xC0E1, 0x6FE2, 0xED5A, 0x6FE3, 0xED52,	0x6FE4, 0xC0DC, 0x6FE6, 0xED56, 0x6FE7, 0xED55, 0x6FE8, 0xED5B,
+	0x6FE9, 0xC0E2, 0x6FEB, 0xC0DD, 0x6FEC, 0xC0E0, 0x6FED, 0xED54,	0x6FEE, 0xC0E4, 0x6FEF, 0xC0DE, 0x6FF0, 0xC0E5, 0x6FF1, 0xC0D8,
+	0x6FF2, 0xED58, 0x6FF4, 0xED50, 0x6FF7, 0xEFF7, 0x6FFA, 0xC271,	0x6FFB, 0xEFF4, 0x6FFC, 0xEFF6, 0x6FFE, 0xC26F, 0x6FFF, 0xEFF2,
+	0x7000, 0xEFF3, 0x7001, 0xEFEE, 0x7004, 0xE9F6, 0x7005, 0xEFEF,	0x7006, 0xC270, 0x7007, 0xEFEB, 0x7009, 0xC26D, 0x700A, 0xEFF8,
+	0x700B, 0xC26E, 0x700C, 0xEFEC, 0x700D, 0xEFED, 0x700E, 0xEFF1,	0x700F, 0xC273, 0x7011, 0xC272, 0x7014, 0xEFF0, 0x7015, 0xC378,
+	0x7016, 0xF25F, 0x7017, 0xF265, 0x7018, 0xC379, 0x7019, 0xF25C,	0x701A, 0xC376, 0x701B, 0xC373, 0x701C, 0xF267, 0x701D, 0xC377,
+	0x701F, 0xC374, 0x7020, 0xF25E, 0x7021, 0xF261, 0x7022, 0xF262,	0x7023, 0xF263, 0x7024, 0xF266, 0x7026, 0xEFF5, 0x7027, 0xF25D,
+	0x7028, 0xC375, 0x7029, 0xF264, 0x702A, 0xF268, 0x702B, 0xF260,	0x702F, 0xF45D, 0x7030, 0xC46A, 0x7031, 0xF460, 0x7032, 0xC46B,
+	0x7033, 0xF468, 0x7034, 0xF45F, 0x7035, 0xF45C, 0x7037, 0xF45E,	0x7038, 0xF462, 0x7039, 0xF465, 0x703A, 0xF464, 0x703B, 0xF467,
+	0x703C, 0xF45B, 0x703E, 0xC469, 0x703F, 0xF463, 0x7040, 0xF466,	0x7041, 0xF469, 0x7042, 0xF461, 0x7043, 0xF5D3, 0x7044, 0xF5D4,
+	0x7045, 0xF5D8, 0x7046, 0xF5D9, 0x7048, 0xF5D6, 0x7049, 0xF5D7,	0x704A, 0xF5D5, 0x704C, 0xC4E9, 0x7051, 0xC578, 0x7052, 0xF6EB,
+	0x7055, 0xF6E8, 0x7056, 0xF6E9, 0x7057, 0xF6EA, 0x7058, 0xC579,	0x705A, 0xF7E5, 0x705B, 0xF7E4, 0x705D, 0xF8AF, 0x705E, 0xC5F4,
+	0x705F, 0xF8AD, 0x7060, 0xF8B0, 0x7061, 0xF8AE, 0x7062, 0xF8F5,	0x7063, 0xC657, 0x7064, 0xC665, 0x7065, 0xF9A3, 0x7066, 0xF96C,
+	0x7068, 0xF9A2, 0x7069, 0xF9D0, 0x706A, 0xF9D1, 0x706B, 0xA4F5,	0x7070, 0xA6C7, 0x7071, 0xCA41, 0x7074, 0xCB5E, 0x7076, 0xA85F,
+	0x7078, 0xA862, 0x707A, 0xCB5F, 0x707C, 0xA860, 0x707D, 0xA861,	0x7082, 0xCD58, 0x7083, 0xCD5A, 0x7084, 0xCD55, 0x7085, 0xCD52,
+	0x7086, 0xCD54, 0x708A, 0xAAA4, 0x708E, 0xAAA2, 0x7091, 0xCD56,	0x7092, 0xAAA3, 0x7093, 0xCD53, 0x7094, 0xCD50, 0x7095, 0xAAA1,
+	0x7096, 0xCD57, 0x7098, 0xCD51, 0x7099, 0xAAA5, 0x709A, 0xCD59,	0x709F, 0xCFAF, 0x70A1, 0xCFB3, 0x70A4, 0xACB7, 0x70A9, 0xCFB6,
+	0x70AB, 0xACAF, 0x70AC, 0xACB2, 0x70AD, 0xACB4, 0x70AE, 0xACB6,	0x70AF, 0xACB3, 0x70B0, 0xCFB2, 0x70B1, 0xCFB1, 0x70B3, 0xACB1,
+	0x70B4, 0xCFB4, 0x70B5, 0xCFB5, 0x70B7, 0xCFAE, 0x70B8, 0xACB5,	0x70BA, 0xACB0, 0x70BE, 0xCFB0, 0x70C5, 0xD277, 0x70C6, 0xD278,
+	0x70C7, 0xD279, 0x70C8, 0xAF50, 0x70CA, 0xAF4C, 0x70CB, 0xD26E,	0x70CD, 0xD276, 0x70CE, 0xD27B, 0x70CF, 0xAF51, 0x70D1, 0xD26C,
+	0x70D2, 0xD272, 0x70D3, 0xD26B, 0x70D4, 0xD275, 0x70D7, 0xD271,	0x70D8, 0xAF4D, 0x70D9, 0xAF4F, 0x70DA, 0xD27A, 0x70DC, 0xD26A,
+	0x70DD, 0xD26D, 0x70DE, 0xD273, 0x70E0, 0xD274, 0x70E1, 0xD27C,	0x70E2, 0xD270, 0x70E4, 0xAF4E, 0x70EF, 0xB26D, 0x70F0, 0xD64E,
+	0x70F3, 0xD650, 0x70F4, 0xD64C, 0x70F6, 0xD658, 0x70F7, 0xD64A,	0x70F8, 0xD657, 0x70F9, 0xB269, 0x70FA, 0xD648, 0x70FB, 0xDA5B,
+	0x70FC, 0xD652, 0x70FD, 0xB26C, 0x70FF, 0xD653, 0x7100, 0xD656,	0x7102, 0xD65A, 0x7104, 0xD64F, 0x7106, 0xD654, 0x7109, 0xB26A,
+	0x710A, 0xB26B, 0x710B, 0xD659, 0x710C, 0xD64D, 0x710D, 0xD649,	0x710E, 0xD65B, 0x7110, 0xD651, 0x7113, 0xD655, 0x7117, 0xD64B,
+	0x7119, 0xB548, 0x711A, 0xB549, 0x711B, 0xDA65, 0x711C, 0xB54F,	0x711E, 0xDA59, 0x711F, 0xDA62, 0x7120, 0xDA58, 0x7121, 0xB54C,
+	0x7122, 0xDA60, 0x7123, 0xDA5E, 0x7125, 0xDA5F, 0x7126, 0xB54A,	0x7128, 0xDA63, 0x712E, 0xDA5C, 0x712F, 0xDA5A, 0x7130, 0xB54B,
+	0x7131, 0xDA5D, 0x7132, 0xDA61, 0x7136, 0xB54D, 0x713A, 0xDA64,	0x7141, 0xDE70, 0x7142, 0xDE77, 0x7143, 0xDE79, 0x7144, 0xDEA1,
+	0x7146, 0xB7DA, 0x7147, 0xDE6B, 0x7149, 0xB7D2, 0x714B, 0xDE7A,	0x714C, 0xB7D7, 0x714D, 0xDEA2, 0x714E, 0xB7CE, 0x7150, 0xDE7D,
+	0x7152, 0xDE6D, 0x7153, 0xDE7E, 0x7154, 0xDE6C, 0x7156, 0xB7DC,	0x7158, 0xDE78, 0x7159, 0xB7CF, 0x715A, 0xDEA3, 0x715C, 0xB7D4,
+	0x715D, 0xDE71, 0x715E, 0xB7D9, 0x715F, 0xDE7C, 0x7160, 0xDE6F,	0x7161, 0xDE76, 0x7162, 0xDE72, 0x7163, 0xDE6E, 0x7164, 0xB7D1,
+	0x7165, 0xB7D8, 0x7166, 0xB7D6, 0x7167, 0xB7D3, 0x7168, 0xB7DB,	0x7169, 0xB7D0, 0x716A, 0xDE75, 0x716C, 0xB7D5, 0x716E, 0xB54E,
+	0x7170, 0xDE7B, 0x7172, 0xDE73, 0x7178, 0xDE74, 0x717B, 0xE2C1,	0x717D, 0xBAB4, 0x7180, 0xE2BD, 0x7181, 0xE2C3, 0x7182, 0xE2BF,
+	0x7184, 0xBAB6, 0x7185, 0xE2BE, 0x7186, 0xE2C2, 0x7187, 0xE2BA,	0x7189, 0xE2BC, 0x718A, 0xBAB5, 0x718F, 0xE2C0, 0x7190, 0xE2BB,
+	0x7192, 0xBAB7, 0x7194, 0xBAB2, 0x7197, 0xE2C4, 0x7199, 0xBAB3,	0x719A, 0xE667, 0x719B, 0xE664, 0x719C, 0xE670, 0x719D, 0xE66A,
+	0x719E, 0xE66C, 0x719F, 0xBCF4, 0x71A0, 0xE666, 0x71A1, 0xE66E,	0x71A4, 0xE66D, 0x71A5, 0xE66B, 0x71A7, 0xE671, 0x71A8, 0xBCF7,
+	0x71A9, 0xE668, 0x71AA, 0xE66F, 0x71AC, 0xBCF5, 0x71AF, 0xE663,	0x71B0, 0xE665, 0x71B1, 0xBCF6, 0x71B2, 0xE662, 0x71B3, 0xE672,
+	0x71B5, 0xE669, 0x71B8, 0xEA4A, 0x71B9, 0xBF51, 0x71BC, 0xEA55,	0x71BD, 0xEA53, 0x71BE, 0xBF4B, 0x71BF, 0xEA49, 0x71C0, 0xEA4C,
+	0x71C1, 0xEA4D, 0x71C2, 0xEA48, 0x71C3, 0xBF55, 0x71C4, 0xBF56,	0x71C5, 0xEA47, 0x71C6, 0xEA56, 0x71C7, 0xEA51, 0x71C8, 0xBF4F,
+	0x71C9, 0xBF4C, 0x71CA, 0xEA50, 0x71CB, 0xEA4E, 0x71CE, 0xBF52,	0x71CF, 0xEA52, 0x71D0, 0xBF4D, 0x71D2, 0xBF4E, 0x71D4, 0xEA4F,
+	0x71D5, 0xBF50, 0x71D6, 0xEA4B, 0x71D8, 0xEA54, 0x71D9, 0xBF53,	0x71DA, 0xEA57, 0x71DB, 0xEA58, 0x71DC, 0xBF54, 0x71DF, 0xC0E7,
+	0x71E0, 0xC0EE, 0x71E1, 0xED5C, 0x71E2, 0xED62, 0x71E4, 0xED60,	0x71E5, 0xC0EA, 0x71E6, 0xC0E9, 0x71E7, 0xC0E6, 0x71E8, 0xED5E,
+	0x71EC, 0xC0EC, 0x71ED, 0xC0EB, 0x71EE, 0xC0E8, 0x71F0, 0xED61,	0x71F1, 0xED5D, 0x71F2, 0xED5F, 0x71F4, 0xC0ED, 0x71F8, 0xC277,
+	0x71F9, 0xEFFB, 0x71FB, 0xC274, 0x71FC, 0xC275, 0x71FD, 0xEFFD,	0x71FE, 0xC276, 0x71FF, 0xEFFA, 0x7201, 0xEFF9, 0x7202, 0xF26C,
+	0x7203, 0xEFFC, 0x7205, 0xF26D, 0x7206, 0xC37A, 0x7207, 0xF26B,	0x720A, 0xF26A, 0x720C, 0xF269, 0x720D, 0xC37B, 0x7210, 0xC46C,
+	0x7213, 0xF46A, 0x7214, 0xF46B, 0x7219, 0xF5DC, 0x721A, 0xF5DB,	0x721B, 0xC4EA, 0x721D, 0xF5DA, 0x721E, 0xF6EC, 0x721F, 0xF6ED,
+	0x7222, 0xF7E6, 0x7223, 0xF8B1, 0x7226, 0xF8F6, 0x7227, 0xF9BC,	0x7228, 0xC679, 0x7229, 0xF9C6, 0x722A, 0xA4F6, 0x722C, 0xAAA6,
+	0x722D, 0xAAA7, 0x7230, 0xACB8, 0x7235, 0xC0EF, 0x7236, 0xA4F7,	0x7238, 0xAAA8, 0x7239, 0xAF52, 0x723A, 0xB7DD, 0x723B, 0xA4F8,
+	0x723D, 0xB26E, 0x723E, 0xBAB8, 0x723F, 0xC962, 0x7241, 0xCFB7,	0x7242, 0xD27D, 0x7244, 0xE2C5, 0x7246, 0xC0F0, 0x7247, 0xA4F9,
+	0x7248, 0xAAA9, 0x7249, 0xCFB8, 0x724A, 0xCFB9, 0x724B, 0xDA66,	0x724C, 0xB550, 0x724F, 0xDEA4, 0x7252, 0xB7DE, 0x7253, 0xE2C6,
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+	0x769E, 0xE6BA, 0x76A4, 0xED78, 0x76A6, 0xF051, 0x76AA, 0xF471,	0x76AB, 0xF470, 0x76AD, 0xF6F5, 0x76AE, 0xA5D6, 0x76AF, 0xCD75,
+	0x76B0, 0xAF70, 0x76B4, 0xB572, 0x76B5, 0xDED6, 0x76B8, 0xE2E1,	0x76BA, 0xBD4B, 0x76BB, 0xEA74, 0x76BD, 0xF052, 0x76BE, 0xF472,
+	0x76BF, 0xA5D7, 0x76C2, 0xAABB, 0x76C3, 0xACD7, 0x76C4, 0xCFDF,	0x76C5, 0xACD8, 0x76C6, 0xACD6, 0x76C8, 0xACD5, 0x76C9, 0xD2CC,
+	0x76CA, 0xAF71, 0x76CD, 0xAF72, 0x76CE, 0xAF73, 0x76D2, 0xB2B0,	0x76D3, 0xD6A7, 0x76D4, 0xB2AF, 0x76DA, 0xDAB9, 0x76DB, 0xB2B1,
+	0x76DC, 0xB573, 0x76DD, 0xDED7, 0x76DE, 0xB7F8, 0x76DF, 0xB7F9,	0x76E1, 0xBAC9, 0x76E3, 0xBACA, 0x76E4, 0xBD4C, 0x76E5, 0xBF64,
+	0x76E6, 0xEA75, 0x76E7, 0xBF63, 0x76E9, 0xED79, 0x76EA, 0xC0FA,	0x76EC, 0xF053, 0x76ED, 0xF473, 0x76EE, 0xA5D8, 0x76EF, 0xA86E,
+	0x76F0, 0xCD78, 0x76F1, 0xCD77, 0x76F2, 0xAABC, 0x76F3, 0xCD76,	0x76F4, 0xAABD, 0x76F5, 0xCD79, 0x76F7, 0xCFE5, 0x76F8, 0xACDB,
+	0x76F9, 0xACDA, 0x76FA, 0xCFE7, 0x76FB, 0xCFE6, 0x76FC, 0xACDF,	0x76FE, 0xACDE, 0x7701, 0xACD9, 0x7703, 0xCFE1, 0x7704, 0xCFE2,
+	0x7705, 0xCFE3, 0x7707, 0xACE0, 0x7708, 0xCFE0, 0x7709, 0xACDC,	0x770A, 0xCFE4, 0x770B, 0xACDD, 0x7710, 0xD2CF, 0x7711, 0xD2D3,
+	0x7712, 0xD2D1, 0x7713, 0xD2D0, 0x7715, 0xD2D4, 0x7719, 0xD2D5,	0x771A, 0xD2D6, 0x771B, 0xD2CE, 0x771D, 0xD2CD, 0x771F, 0xAF75,
+	0x7720, 0xAF76, 0x7722, 0xD2D7, 0x7723, 0xD2D2, 0x7725, 0xD6B0,	0x7727, 0xD2D8, 0x7728, 0xAF77, 0x7729, 0xAF74, 0x772D, 0xD6AA,
+	0x772F, 0xD6A9, 0x7731, 0xD6AB, 0x7732, 0xD6AC, 0x7733, 0xD6AE,	0x7734, 0xD6AD, 0x7735, 0xD6B2, 0x7736, 0xB2B5, 0x7737, 0xB2B2,
+	0x7738, 0xB2B6, 0x7739, 0xD6A8, 0x773A, 0xB2B7, 0x773B, 0xD6B1,	0x773C, 0xB2B4, 0x773D, 0xD6AF, 0x773E, 0xB2B3, 0x7744, 0xDABC,
+	0x7745, 0xDABE, 0x7746, 0xDABA, 0x7747, 0xDABB, 0x774A, 0xDABF,	0x774B, 0xDAC1, 0x774C, 0xDAC2, 0x774D, 0xDABD, 0x774E, 0xDAC0,
+	0x774F, 0xB574, 0x7752, 0xDEDB, 0x7754, 0xDEE0, 0x7755, 0xDED8,	0x7756, 0xDEDC, 0x7759, 0xDEE1, 0x775A, 0xDEDD, 0x775B, 0xB7FA,
+	0x775C, 0xB843, 0x775E, 0xB7FD, 0x775F, 0xDED9, 0x7760, 0xDEDA,	0x7761, 0xBACE, 0x7762, 0xB846, 0x7763, 0xB7FE, 0x7765, 0xB844,
+	0x7766, 0xB7FC, 0x7767, 0xDEDF, 0x7768, 0xB845, 0x7769, 0xDEDE,	0x776A, 0xB841, 0x776B, 0xB7FB, 0x776C, 0xB842, 0x776D, 0xDEE2,
+	0x776E, 0xE2E6, 0x776F, 0xE2E8, 0x7779, 0xB840, 0x777C, 0xE2E3,	0x777D, 0xBACC, 0x777E, 0xE2E9, 0x777F, 0xBACD, 0x7780, 0xE2E7,
+	0x7781, 0xE2E2, 0x7782, 0xE2E5, 0x7783, 0xE2EA, 0x7784, 0xBACB,	0x7785, 0xE2E4, 0x7787, 0xBD4E, 0x7788, 0xE6BF, 0x7789, 0xE6BE,
+	0x778B, 0xBD51, 0x778C, 0xBD4F, 0x778D, 0xE6BC, 0x778E, 0xBD4D,	0x778F, 0xE6BD, 0x7791, 0xBD50, 0x7795, 0xEA7D, 0x7797, 0xEAA1,
+	0x7799, 0xEA7E, 0x779A, 0xEA76, 0x779B, 0xEA7A, 0x779C, 0xEA79,	0x779D, 0xEA77, 0x779E, 0xBF66, 0x779F, 0xBF67, 0x77A0, 0xBF65,
+	0x77A1, 0xEA78, 0x77A2, 0xEA7B, 0x77A3, 0xEA7C, 0x77A5, 0xBF68,	0x77A7, 0xC140, 0x77A8, 0xEDA3, 0x77AA, 0xC0FC, 0x77AB, 0xED7B,
+	0x77AC, 0xC0FE, 0x77AD, 0xC141, 0x77B0, 0xC0FD, 0x77B1, 0xEDA2,	0x77B2, 0xED7C, 0x77B3, 0xC0FB, 0x77B4, 0xEDA1, 0x77B5, 0xED7A,
+	0x77B6, 0xED7E, 0x77B7, 0xED7D, 0x77BA, 0xF055, 0x77BB, 0xC2A4,	0x77BC, 0xC2A5, 0x77BD, 0xC2A2, 0x77BF, 0xC2A3, 0x77C2, 0xF054,
+	0x77C4, 0xF27B, 0x77C7, 0xC3A9, 0x77C9, 0xF279, 0x77CA, 0xF27A,	0x77CC, 0xF474, 0x77CD, 0xF477, 0x77CE, 0xF475, 0x77CF, 0xF476,
+	0x77D0, 0xF5E0, 0x77D3, 0xC4EF, 0x77D4, 0xF7EB, 0x77D5, 0xF8B4,	0x77D7, 0xC5F7, 0x77D8, 0xF8F8, 0x77D9, 0xF8F9, 0x77DA, 0xC666,
+	0x77DB, 0xA5D9, 0x77DC, 0xACE1, 0x77DE, 0xDAC3, 0x77E0, 0xDEE3,	0x77E2, 0xA5DA, 0x77E3, 0xA86F, 0x77E5, 0xAABE, 0x77E7, 0xCFE8,
+	0x77E8, 0xCFE9, 0x77E9, 0xAF78, 0x77EC, 0xDAC4, 0x77ED, 0xB575,	0x77EE, 0xB847, 0x77EF, 0xC142, 0x77F0, 0xEDA4, 0x77F1, 0xF27C,
+	0x77F2, 0xF478, 0x77F3, 0xA5DB, 0x77F7, 0xCDA1, 0x77F8, 0xCD7A,	0x77F9, 0xCD7C, 0x77FA, 0xCD7E, 0x77FB, 0xCD7D, 0x77FC, 0xCD7B,
+	0x77FD, 0xAABF, 0x7802, 0xACE2, 0x7803, 0xCFF2, 0x7805, 0xCFED,	0x7806, 0xCFEA, 0x7809, 0xCFF1, 0x780C, 0xACE4, 0x780D, 0xACE5,
+	0x780E, 0xCFF0, 0x780F, 0xCFEF, 0x7810, 0xCFEE, 0x7811, 0xCFEB,	0x7812, 0xCFEC, 0x7813, 0xCFF3, 0x7814, 0xACE3, 0x781D, 0xAF7C,
+	0x781F, 0xAFA4, 0x7820, 0xAFA3, 0x7821, 0xD2E1, 0x7822, 0xD2DB,	0x7823, 0xD2D9, 0x7825, 0xAFA1, 0x7826, 0xD6B9, 0x7827, 0xAF7A,
+	0x7828, 0xD2DE, 0x7829, 0xD2E2, 0x782A, 0xD2E4, 0x782B, 0xD2E0,	0x782C, 0xD2DA, 0x782D, 0xAFA2, 0x782E, 0xD2DF, 0x782F, 0xD2DD,
+	0x7830, 0xAF79, 0x7831, 0xD2E5, 0x7832, 0xAFA5, 0x7833, 0xD2E3,	0x7834, 0xAF7D, 0x7835, 0xD2DC, 0x7837, 0xAF7E, 0x7838, 0xAF7B,
+	0x7843, 0xB2B9, 0x7845, 0xD6BA, 0x7848, 0xD6B3, 0x7849, 0xD6B5,	0x784A, 0xD6B7, 0x784C, 0xD6B8, 0x784D, 0xD6B6, 0x784E, 0xB2BA,
+	0x7850, 0xD6BB, 0x7852, 0xD6B4, 0x785C, 0xDAC8, 0x785D, 0xB576,	0x785E, 0xDAD0, 0x7860, 0xDAC5, 0x7862, 0xDAD1, 0x7864, 0xDAC6,
+	0x7865, 0xDAC7, 0x7868, 0xDACF, 0x7869, 0xDACE, 0x786A, 0xDACB,	0x786B, 0xB2B8, 0x786C, 0xB577, 0x786D, 0xDAC9, 0x786E, 0xDACC,
+	0x786F, 0xB578, 0x7870, 0xDACD, 0x7871, 0xDACA, 0x7879, 0xDEEE,	0x787B, 0xDEF2, 0x787C, 0xB84E, 0x787E, 0xE2F0, 0x787F, 0xB851,
+	0x7880, 0xDEF0, 0x7881, 0xF9D6, 0x7883, 0xDEED, 0x7884, 0xDEE8,	0x7885, 0xDEEA, 0x7886, 0xDEEB, 0x7887, 0xDEE4, 0x7889, 0xB84D,
+	0x788C, 0xB84C, 0x788E, 0xB848, 0x788F, 0xDEE7, 0x7891, 0xB84F,	0x7893, 0xB850, 0x7894, 0xDEE6, 0x7895, 0xDEE9, 0x7896, 0xDEF1,
+	0x7897, 0xB84A, 0x7898, 0xB84B, 0x7899, 0xDEEF, 0x789A, 0xDEE5,	0x789E, 0xE2F2, 0x789F, 0xBAD0, 0x78A0, 0xE2F4, 0x78A1, 0xDEEC,
+	0x78A2, 0xE2F6, 0x78A3, 0xBAD4, 0x78A4, 0xE2F7, 0x78A5, 0xE2F3,	0x78A7, 0xBAD1, 0x78A8, 0xE2EF, 0x78A9, 0xBAD3, 0x78AA, 0xE2EC,
+	0x78AB, 0xE2F1, 0x78AC, 0xE2F5, 0x78AD, 0xE2EE, 0x78B0, 0xB849,	0x78B2, 0xE2EB, 0x78B3, 0xBAD2, 0x78B4, 0xE2ED, 0x78BA, 0xBD54,
+	0x78BB, 0xE6C1, 0x78BC, 0xBD58, 0x78BE, 0xBD56, 0x78C1, 0xBACF,	0x78C3, 0xE6C8, 0x78C4, 0xE6C9, 0x78C5, 0xBD53, 0x78C8, 0xE6C7,
+	0x78C9, 0xE6CA, 0x78CA, 0xBD55, 0x78CB, 0xBD52, 0x78CC, 0xE6C3,	0x78CD, 0xE6C0, 0x78CE, 0xE6C5, 0x78CF, 0xE6C2, 0x78D0, 0xBD59,
+	0x78D1, 0xE6C4, 0x78D4, 0xE6C6, 0x78D5, 0xBD57, 0x78DA, 0xBF6A,	0x78DB, 0xEAA8, 0x78DD, 0xEAA2, 0x78DE, 0xEAA6, 0x78DF, 0xEAAC,
+	0x78E0, 0xEAAD, 0x78E1, 0xEAA9, 0x78E2, 0xEAAA, 0x78E3, 0xEAA7,	0x78E5, 0xEAA4, 0x78E7, 0xBF6C, 0x78E8, 0xBF69, 0x78E9, 0xEAA3,
+	0x78EA, 0xEAA5, 0x78EC, 0xBF6B, 0x78ED, 0xEAAB, 0x78EF, 0xC146,	0x78F2, 0xEDAA, 0x78F3, 0xEDA5, 0x78F4, 0xC145, 0x78F7, 0xC143,
+	0x78F9, 0xEDAC, 0x78FA, 0xC144, 0x78FB, 0xEDA8, 0x78FC, 0xEDA9,	0x78FD, 0xEDA6, 0x78FE, 0xEDAD, 0x78FF, 0xF056, 0x7901, 0xC147,
+	0x7902, 0xEDA7, 0x7904, 0xEDAE, 0x7905, 0xEDAB, 0x7909, 0xF05A,	0x790C, 0xF057, 0x790E, 0xC2A6, 0x7910, 0xF05B, 0x7911, 0xF05D,
+	0x7912, 0xF05C, 0x7913, 0xF058, 0x7914, 0xF059, 0x7917, 0xF2A3,	0x7919, 0xC3AA, 0x791B, 0xF27E, 0x791C, 0xF2A2, 0x791D, 0xF27D,
+	0x791E, 0xF2A4, 0x7921, 0xF2A1, 0x7923, 0xF47A, 0x7924, 0xF47D,	0x7925, 0xF479, 0x7926, 0xC471, 0x7927, 0xF47B, 0x7928, 0xF47C,
+	0x7929, 0xF47E, 0x792A, 0xC472, 0x792B, 0xC474, 0x792C, 0xC473,	0x792D, 0xF5E1, 0x792F, 0xF5E3, 0x7931, 0xF5E2, 0x7935, 0xF6F6,
+	0x7938, 0xF8B5, 0x7939, 0xF8FA, 0x793A, 0xA5DC, 0x793D, 0xCB72,	0x793E, 0xAAC0, 0x793F, 0xCDA3, 0x7940, 0xAAC1, 0x7941, 0xAAC2,
+	0x7942, 0xCDA2, 0x7944, 0xCFF8, 0x7945, 0xCFF7, 0x7946, 0xACE6,	0x7947, 0xACE9, 0x7948, 0xACE8, 0x7949, 0xACE7, 0x794A, 0xCFF4,
+	0x794B, 0xCFF6, 0x794C, 0xCFF5, 0x794F, 0xD2E8, 0x7950, 0xAFA7,	0x7951, 0xD2EC, 0x7952, 0xD2EB, 0x7953, 0xD2EA, 0x7954, 0xD2E6,
+	0x7955, 0xAFA6, 0x7956, 0xAFAA, 0x7957, 0xAFAD, 0x795A, 0xAFAE,	0x795B, 0xD2E7, 0x795C, 0xD2E9, 0x795D, 0xAFAC, 0x795E, 0xAFAB,
+	0x795F, 0xAFA9, 0x7960, 0xAFA8, 0x7961, 0xD6C2, 0x7963, 0xD6C0,	0x7964, 0xD6BC, 0x7965, 0xB2BB, 0x7967, 0xD6BD, 0x7968, 0xB2BC,
+	0x7969, 0xD6BE, 0x796A, 0xD6BF, 0x796B, 0xD6C1, 0x796D, 0xB2BD,	0x7970, 0xDAD5, 0x7972, 0xDAD4, 0x7973, 0xDAD3, 0x7974, 0xDAD2,
+	0x7979, 0xDEF6, 0x797A, 0xB852, 0x797C, 0xDEF3, 0x797D, 0xDEF5,	0x797F, 0xB853, 0x7981, 0xB854, 0x7982, 0xDEF4, 0x7988, 0xE341,
+	0x798A, 0xE2F9, 0x798B, 0xE2FA, 0x798D, 0xBAD7, 0x798E, 0xBAD5,	0x798F, 0xBAD6, 0x7990, 0xE343, 0x7992, 0xE342, 0x7993, 0xE2FE,
+	0x7994, 0xE2FD, 0x7995, 0xE2FC, 0x7996, 0xE2FB, 0x7997, 0xE340,	0x7998, 0xE2F8, 0x799A, 0xE6CB, 0x799B, 0xE6D0, 0x799C, 0xE6CE,
+	0x79A0, 0xE6CD, 0x79A1, 0xE6CC, 0x79A2, 0xE6CF, 0x79A4, 0xEAAE,	0x79A6, 0xBF6D, 0x79A7, 0xC148, 0x79A8, 0xEDB0, 0x79AA, 0xC149,
+	0x79AB, 0xEDAF, 0x79AC, 0xF05F, 0x79AD, 0xF05E, 0x79AE, 0xC2A7,	0x79B0, 0xF2A5, 0x79B1, 0xC3AB, 0x79B2, 0xF4A1, 0x79B3, 0xC5A1,
+	0x79B4, 0xF6F7, 0x79B6, 0xF8B7, 0x79B7, 0xF8B6, 0x79B8, 0xC9A8,	0x79B9, 0xACEA, 0x79BA, 0xACEB, 0x79BB, 0xD6C3, 0x79BD, 0xB856,
+	0x79BE, 0xA5DD, 0x79BF, 0xA872, 0x79C0, 0xA871, 0x79C1, 0xA870,	0x79C5, 0xCDA4, 0x79C8, 0xAAC4, 0x79C9, 0xAAC3, 0x79CB, 0xACEE,
+	0x79CD, 0xCFFA, 0x79CE, 0xCFFD, 0x79CF, 0xCFFB, 0x79D1, 0xACEC,	0x79D2, 0xACED, 0x79D5, 0xCFF9, 0x79D6, 0xCFFC, 0x79D8, 0xAFB5,
+	0x79DC, 0xD2F3, 0x79DD, 0xD2F5, 0x79DE, 0xD2F4, 0x79DF, 0xAFB2,	0x79E0, 0xD2EF, 0x79E3, 0xAFB0, 0x79E4, 0xAFAF, 0x79E6, 0xAFB3,
+	0x79E7, 0xAFB1, 0x79E9, 0xAFB4, 0x79EA, 0xD2F2, 0x79EB, 0xD2ED,	0x79EC, 0xD2EE, 0x79ED, 0xD2F1, 0x79EE, 0xD2F0, 0x79F6, 0xD6C6,
+	0x79F7, 0xD6C7, 0x79F8, 0xD6C5, 0x79FA, 0xD6C4, 0x79FB, 0xB2BE,	0x7A00, 0xB57D, 0x7A02, 0xDAD6, 0x7A03, 0xDAD8, 0x7A04, 0xDADA,
+	0x7A05, 0xB57C, 0x7A08, 0xB57A, 0x7A0A, 0xDAD7, 0x7A0B, 0xB57B,	0x7A0C, 0xDAD9, 0x7A0D, 0xB579, 0x7A10, 0xDF41, 0x7A11, 0xDEF7,
+	0x7A12, 0xDEFA, 0x7A13, 0xDEFE, 0x7A14, 0xB85A, 0x7A15, 0xDEFC,	0x7A17, 0xDEFB, 0x7A18, 0xDEF8, 0x7A19, 0xDEF9, 0x7A1A, 0xB858,
+	0x7A1B, 0xDF40, 0x7A1C, 0xB857, 0x7A1E, 0xB85C, 0x7A1F, 0xB85B,	0x7A20, 0xB859, 0x7A22, 0xDEFD, 0x7A26, 0xE349, 0x7A28, 0xE348,
+	0x7A2B, 0xE344, 0x7A2E, 0xBAD8, 0x7A2F, 0xE347, 0x7A30, 0xE346,	0x7A31, 0xBAD9, 0x7A37, 0xBD5E, 0x7A39, 0xE6D2, 0x7A3B, 0xBD5F,
+	0x7A3C, 0xBD5B, 0x7A3D, 0xBD5D, 0x7A3F, 0xBD5A, 0x7A40, 0xBD5C,	0x7A44, 0xEAAF, 0x7A46, 0xBF70, 0x7A47, 0xEAB1, 0x7A48, 0xEAB0,
+	0x7A4A, 0xE345, 0x7A4B, 0xBF72, 0x7A4C, 0xBF71, 0x7A4D, 0xBF6E,	0x7A4E, 0xBF6F, 0x7A54, 0xEDB5, 0x7A56, 0xEDB3, 0x7A57, 0xC14A,
+	0x7A58, 0xEDB4, 0x7A5A, 0xEDB6, 0x7A5B, 0xEDB2, 0x7A5C, 0xEDB1,	0x7A5F, 0xF060, 0x7A60, 0xC2AA, 0x7A61, 0xC2A8, 0x7A62, 0xC2A9,
+	0x7A67, 0xF2A6, 0x7A68, 0xF2A7, 0x7A69, 0xC3AD, 0x7A6B, 0xC3AC,	0x7A6C, 0xF4A3, 0x7A6D, 0xF4A4, 0x7A6E, 0xF4A2, 0x7A70, 0xF6F8,
+	0x7A71, 0xF6F9, 0x7A74, 0xA5DE, 0x7A75, 0xCA48, 0x7A76, 0xA873,	0x7A78, 0xCDA5, 0x7A79, 0xAAC6, 0x7A7A, 0xAAC5, 0x7A7B, 0xCDA6,
+	0x7A7E, 0xD040, 0x7A7F, 0xACEF, 0x7A80, 0xCFFE, 0x7A81, 0xACF0,	0x7A84, 0xAFB6, 0x7A85, 0xD2F8, 0x7A86, 0xD2F6, 0x7A87, 0xD2FC,
+	0x7A88, 0xAFB7, 0x7A89, 0xD2F7, 0x7A8A, 0xD2FB, 0x7A8B, 0xD2F9,	0x7A8C, 0xD2FA, 0x7A8F, 0xD6C8, 0x7A90, 0xD6CA, 0x7A92, 0xB2BF,
+	0x7A94, 0xD6C9, 0x7A95, 0xB2C0, 0x7A96, 0xB5A2, 0x7A97, 0xB5A1,	0x7A98, 0xB57E, 0x7A99, 0xDADB, 0x7A9E, 0xDF44, 0x7A9F, 0xB85D,
+	0x7AA0, 0xB85E, 0x7AA2, 0xDF43, 0x7AA3, 0xDF42, 0x7AA8, 0xE34A,	0x7AA9, 0xBADB, 0x7AAA, 0xBADA, 0x7AAB, 0xE34B, 0x7AAC, 0xE34C,
+	0x7AAE, 0xBD61, 0x7AAF, 0xBD60, 0x7AB1, 0xEAB5, 0x7AB2, 0xE6D3,	0x7AB3, 0xE6D5, 0x7AB4, 0xE6D4, 0x7AB5, 0xEAB4, 0x7AB6, 0xEAB2,
+	0x7AB7, 0xEAB6, 0x7AB8, 0xEAB3, 0x7ABA, 0xBF73, 0x7ABE, 0xEDB7,	0x7ABF, 0xC14B, 0x7AC0, 0xEDB8, 0x7AC1, 0xEDB9, 0x7AC4, 0xC2AB,
+	0x7AC5, 0xC2AC, 0x7AC7, 0xC475, 0x7ACA, 0xC5D1, 0x7ACB, 0xA5DF,	0x7AD1, 0xD041, 0x7AD8, 0xD2FD, 0x7AD9, 0xAFB8, 0x7ADF, 0xB3BA,
+	0x7AE0, 0xB3B9, 0x7AE3, 0xB5A4, 0x7AE4, 0xDADD, 0x7AE5, 0xB5A3,	0x7AE6, 0xDADC, 0x7AEB, 0xDF45, 0x7AED, 0xBADC, 0x7AEE, 0xE34D,
+	0x7AEF, 0xBADD, 0x7AF6, 0xC476, 0x7AF7, 0xF4A5, 0x7AF9, 0xA6CB,	0x7AFA, 0xAAC7, 0x7AFB, 0xCDA7, 0x7AFD, 0xACF2, 0x7AFF, 0xACF1,
+	0x7B00, 0xD042, 0x7B01, 0xD043, 0x7B04, 0xD340, 0x7B05, 0xD342,	0x7B06, 0xAFB9, 0x7B08, 0xD344, 0x7B09, 0xD347, 0x7B0A, 0xD345,
+	0x7B0E, 0xD346, 0x7B0F, 0xD343, 0x7B10, 0xD2FE, 0x7B11, 0xAFBA,	0x7B12, 0xD348, 0x7B13, 0xD341, 0x7B18, 0xD6D3, 0x7B19, 0xB2C6,
+	0x7B1A, 0xD6DC, 0x7B1B, 0xB2C3, 0x7B1D, 0xD6D5, 0x7B1E, 0xB2C7,	0x7B20, 0xB2C1, 0x7B22, 0xD6D0, 0x7B23, 0xD6DD, 0x7B24, 0xD6D1,
+	0x7B25, 0xD6CE, 0x7B26, 0xB2C5, 0x7B28, 0xB2C2, 0x7B2A, 0xD6D4,	0x7B2B, 0xD6D7, 0x7B2C, 0xB2C4, 0x7B2D, 0xD6D8, 0x7B2E, 0xB2C8,
+	0x7B2F, 0xD6D9, 0x7B30, 0xD6CF, 0x7B31, 0xD6D6, 0x7B32, 0xD6DA,	0x7B33, 0xD6D2, 0x7B34, 0xD6CD, 0x7B35, 0xD6CB, 0x7B38, 0xD6DB,
+	0x7B3B, 0xDADF, 0x7B40, 0xDAE4, 0x7B44, 0xDAE0, 0x7B45, 0xDAE6,	0x7B46, 0xB5A7, 0x7B47, 0xD6CC, 0x7B48, 0xDAE1, 0x7B49, 0xB5A5,
+	0x7B4A, 0xDADE, 0x7B4B, 0xB5AC, 0x7B4C, 0xDAE2, 0x7B4D, 0xB5AB,	0x7B4E, 0xDAE3, 0x7B4F, 0xB5AD, 0x7B50, 0xB5A8, 0x7B51, 0xB5AE,
+	0x7B52, 0xB5A9, 0x7B54, 0xB5AA, 0x7B56, 0xB5A6, 0x7B58, 0xDAE5,	0x7B60, 0xB861, 0x7B61, 0xDF50, 0x7B63, 0xDF53, 0x7B64, 0xDF47,
+	0x7B65, 0xDF4C, 0x7B66, 0xDF46, 0x7B67, 0xB863, 0x7B69, 0xDF4A,	0x7B6D, 0xDF48, 0x7B6E, 0xB862, 0x7B70, 0xDF4F, 0x7B71, 0xDF4E,
+	0x7B72, 0xDF4B, 0x7B73, 0xDF4D, 0x7B74, 0xDF49, 0x7B75, 0xBAE1,	0x7B76, 0xDF52, 0x7B77, 0xB85F, 0x7B78, 0xDF51, 0x7B82, 0xE35D,
+	0x7B84, 0xBAE8, 0x7B85, 0xE358, 0x7B87, 0xBAE7, 0x7B88, 0xE34E,	0x7B8A, 0xE350, 0x7B8B, 0xBAE0, 0x7B8C, 0xE355, 0x7B8D, 0xE354,
+	0x7B8E, 0xE357, 0x7B8F, 0xBAE5, 0x7B90, 0xE352, 0x7B91, 0xE351,	0x7B94, 0xBAE4, 0x7B95, 0xBADF, 0x7B96, 0xE353, 0x7B97, 0xBAE2,
+	0x7B98, 0xE359, 0x7B99, 0xE35B, 0x7B9B, 0xE356, 0x7B9C, 0xE34F,	0x7B9D, 0xBAE3, 0x7BA0, 0xBD69, 0x7BA1, 0xBADE, 0x7BA4, 0xE35C,
+	0x7BAC, 0xE6D9, 0x7BAD, 0xBD62, 0x7BAF, 0xE6DB, 0x7BB1, 0xBD63,	0x7BB4, 0xBD65, 0x7BB5, 0xE6DE, 0x7BB7, 0xE6D6, 0x7BB8, 0xBAE6,
+	0x7BB9, 0xE6DC, 0x7BBE, 0xE6D8, 0x7BC0, 0xB860, 0x7BC1, 0xBD68,	0x7BC4, 0xBD64, 0x7BC6, 0xBD66, 0x7BC7, 0xBD67, 0x7BC9, 0xBF76,
+	0x7BCA, 0xE6DD, 0x7BCB, 0xE6D7, 0x7BCC, 0xBD6A, 0x7BCE, 0xE6DA,	0x7BD4, 0xEAC0, 0x7BD5, 0xEABB, 0x7BD8, 0xEAC5, 0x7BD9, 0xBF74,
+	0x7BDA, 0xEABD, 0x7BDB, 0xBF78, 0x7BDC, 0xEAC3, 0x7BDD, 0xEABA,	0x7BDE, 0xEAB7, 0x7BDF, 0xEAC6, 0x7BE0, 0xC151, 0x7BE1, 0xBF79,
+	0x7BE2, 0xEAC2, 0x7BE3, 0xEAB8, 0x7BE4, 0xBF77, 0x7BE5, 0xEABC,	0x7BE6, 0xBF7B, 0x7BE7, 0xEAB9, 0x7BE8, 0xEABE, 0x7BE9, 0xBF7A,
+	0x7BEA, 0xEAC1, 0x7BEB, 0xEAC4, 0x7BF0, 0xEDCB, 0x7BF1, 0xEDCC,	0x7BF2, 0xEDBC, 0x7BF3, 0xEDC3, 0x7BF4, 0xEDC1, 0x7BF7, 0xC14F,
+	0x7BF8, 0xEDC8, 0x7BF9, 0xEABF, 0x7BFB, 0xEDBF, 0x7BFD, 0xEDC9,	0x7BFE, 0xC14E, 0x7BFF, 0xEDBE, 0x7C00, 0xEDBD, 0x7C01, 0xEDC7,
+	0x7C02, 0xEDC4, 0x7C03, 0xEDC6, 0x7C05, 0xEDBA, 0x7C06, 0xEDCA,	0x7C07, 0xC14C, 0x7C09, 0xEDC5, 0x7C0A, 0xEDCE, 0x7C0B, 0xEDC2,
+	0x7C0C, 0xC150, 0x7C0D, 0xC14D, 0x7C0E, 0xEDC0, 0x7C0F, 0xEDBB,	0x7C10, 0xEDCD, 0x7C11, 0xBF75, 0x7C19, 0xF063, 0x7C1C, 0xF061,
+	0x7C1D, 0xF067, 0x7C1E, 0xC2B0, 0x7C1F, 0xF065, 0x7C20, 0xF064,	0x7C21, 0xC2B2, 0x7C22, 0xF06A, 0x7C23, 0xC2B1, 0x7C25, 0xF06B,
+	0x7C26, 0xF068, 0x7C27, 0xC2AE, 0x7C28, 0xF069, 0x7C29, 0xF062,	0x7C2A, 0xC2AF, 0x7C2B, 0xC2AD, 0x7C2C, 0xF2AB, 0x7C2D, 0xF066,
+	0x7C30, 0xF06C, 0x7C33, 0xF2A8, 0x7C37, 0xC3B2, 0x7C38, 0xC3B0,	0x7C39, 0xF2AA, 0x7C3B, 0xF2AC, 0x7C3C, 0xF2A9, 0x7C3D, 0xC3B1,
+	0x7C3E, 0xC3AE, 0x7C3F, 0xC3AF, 0x7C40, 0xC3B3, 0x7C43, 0xC478,	0x7C45, 0xF4AA, 0x7C47, 0xF4A9, 0x7C48, 0xF4A7, 0x7C49, 0xF4A6,
+	0x7C4A, 0xF4A8, 0x7C4C, 0xC477, 0x7C4D, 0xC479, 0x7C50, 0xC4F0,	0x7C53, 0xF5E5, 0x7C54, 0xF5E4, 0x7C57, 0xF6FA, 0x7C59, 0xF6FC,
+	0x7C5A, 0xF6FE, 0x7C5B, 0xF6FD, 0x7C5C, 0xF6FB, 0x7C5F, 0xC5A3,	0x7C60, 0xC5A2, 0x7C63, 0xC5D3, 0x7C64, 0xC5D2, 0x7C65, 0xC5D4,
+	0x7C66, 0xF7ED, 0x7C67, 0xF7EC, 0x7C69, 0xF8FB, 0x7C6A, 0xF8B8,	0x7C6B, 0xF8FC, 0x7C6C, 0xC658, 0x7C6E, 0xC659, 0x7C6F, 0xF96D,
+	0x7C72, 0xC67E, 0x7C73, 0xA6CC, 0x7C75, 0xCDA8, 0x7C78, 0xD045,	0x7C79, 0xD046, 0x7C7A, 0xD044, 0x7C7D, 0xACF3, 0x7C7F, 0xD047,
+	0x7C80, 0xD048, 0x7C81, 0xD049, 0x7C84, 0xD349, 0x7C85, 0xD34F,	0x7C88, 0xD34D, 0x7C89, 0xAFBB, 0x7C8A, 0xD34B, 0x7C8C, 0xD34C,
+	0x7C8D, 0xD34E, 0x7C91, 0xD34A, 0x7C92, 0xB2C9, 0x7C94, 0xD6DE,	0x7C95, 0xB2CB, 0x7C96, 0xD6E0, 0x7C97, 0xB2CA, 0x7C98, 0xD6DF,
+	0x7C9E, 0xDAE8, 0x7C9F, 0xB5AF, 0x7CA1, 0xDAEA, 0x7CA2, 0xDAE7,	0x7CA3, 0xD6E1, 0x7CA5, 0xB5B0, 0x7CA7, 0xF9DB, 0x7CA8, 0xDAE9,
+	0x7CAF, 0xDF56, 0x7CB1, 0xB864, 0x7CB2, 0xDF54, 0x7CB3, 0xB865,	0x7CB4, 0xDF55, 0x7CB5, 0xB866, 0x7CB9, 0xBAE9, 0x7CBA, 0xE361,
+	0x7CBB, 0xE35E, 0x7CBC, 0xE360, 0x7CBD, 0xBAEA, 0x7CBE, 0xBAEB,	0x7CBF, 0xE35F, 0x7CC5, 0xE6DF, 0x7CC8, 0xE6E0, 0x7CCA, 0xBD6B,
+	0x7CCB, 0xE6E2, 0x7CCC, 0xE6E1, 0x7CCE, 0xA261, 0x7CD0, 0xEACA,	0x7CD1, 0xEACB, 0x7CD2, 0xEAC7, 0x7CD4, 0xEAC8, 0x7CD5, 0xBF7C,
+	0x7CD6, 0xBF7D, 0x7CD7, 0xEAC9, 0x7CD9, 0xC157, 0x7CDC, 0xC153,	0x7CDD, 0xC158, 0x7CDE, 0xC154, 0x7CDF, 0xC156, 0x7CE0, 0xC152,
+	0x7CE2, 0xC155, 0x7CE7, 0xC2B3, 0x7CE8, 0xEDCF, 0x7CEA, 0xF2AE,	0x7CEC, 0xF2AD, 0x7CEE, 0xF4AB, 0x7CEF, 0xC47A, 0x7CF0, 0xC47B,
+	0x7CF1, 0xF741, 0x7CF2, 0xF5E6, 0x7CF4, 0xF740, 0x7CF6, 0xF8FD,	0x7CF7, 0xF9A4, 0x7CF8, 0xA6CD, 0x7CFB, 0xA874, 0x7CFD, 0xCDA9,
+	0x7CFE, 0xAAC8, 0x7D00, 0xACF6, 0x7D01, 0xD04C, 0x7D02, 0xACF4,	0x7D03, 0xD04A, 0x7D04, 0xACF9, 0x7D05, 0xACF5, 0x7D06, 0xACFA,
+	0x7D07, 0xACF8, 0x7D08, 0xD04B, 0x7D09, 0xACF7, 0x7D0A, 0xAFBF,	0x7D0B, 0xAFBE, 0x7D0C, 0xD35A, 0x7D0D, 0xAFC7, 0x7D0E, 0xD353,
+	0x7D0F, 0xD359, 0x7D10, 0xAFC3, 0x7D11, 0xD352, 0x7D12, 0xD358,	0x7D13, 0xD356, 0x7D14, 0xAFC2, 0x7D15, 0xAFC4, 0x7D16, 0xD355,
+	0x7D17, 0xAFBD, 0x7D18, 0xD354, 0x7D19, 0xAFC8, 0x7D1A, 0xAFC5,	0x7D1B, 0xAFC9, 0x7D1C, 0xAFC6, 0x7D1D, 0xD351, 0x7D1E, 0xD350,
+	0x7D1F, 0xD357, 0x7D20, 0xAFC0, 0x7D21, 0xAFBC, 0x7D22, 0xAFC1,	0x7D28, 0xD6F0, 0x7D29, 0xD6E9, 0x7D2B, 0xB5B5, 0x7D2C, 0xD6E8,
+	0x7D2E, 0xB2CF, 0x7D2F, 0xB2D6, 0x7D30, 0xB2D3, 0x7D31, 0xB2D9,	0x7D32, 0xB2D8, 0x7D33, 0xB2D4, 0x7D35, 0xD6E2, 0x7D36, 0xD6E5,
+	0x7D38, 0xD6E4, 0x7D39, 0xB2D0, 0x7D3A, 0xD6E6, 0x7D3B, 0xD6EF,	0x7D3C, 0xB2D1, 0x7D3D, 0xD6E3, 0x7D3E, 0xD6EC, 0x7D3F, 0xD6ED,
+	0x7D40, 0xB2D2, 0x7D41, 0xD6EA, 0x7D42, 0xB2D7, 0x7D43, 0xB2CD,	0x7D44, 0xB2D5, 0x7D45, 0xD6E7, 0x7D46, 0xB2CC, 0x7D47, 0xD6EB,
+	0x7D4A, 0xD6EE, 0x7D4E, 0xDAFB, 0x7D4F, 0xDAF2, 0x7D50, 0xB5B2,	0x7D51, 0xDAF9, 0x7D52, 0xDAF6, 0x7D53, 0xDAEE, 0x7D54, 0xDAF7,
+	0x7D55, 0xB5B4, 0x7D56, 0xDAEF, 0x7D58, 0xDAEB, 0x7D5B, 0xB86C,	0x7D5C, 0xDAF4, 0x7D5E, 0xB5B1, 0x7D5F, 0xDAFA, 0x7D61, 0xB5B8,
+	0x7D62, 0xB5BA, 0x7D63, 0xDAED, 0x7D66, 0xB5B9, 0x7D67, 0xDAF0,	0x7D68, 0xB5B3, 0x7D69, 0xDAF8, 0x7D6A, 0xDAF1, 0x7D6B, 0xDAF5,
+	0x7D6D, 0xDAF3, 0x7D6E, 0xB5B6, 0x7D6F, 0xDAEC, 0x7D70, 0xB5BB,	0x7D71, 0xB2CE, 0x7D72, 0xB5B7, 0x7D73, 0xB5BC, 0x7D79, 0xB868,
+	0x7D7A, 0xDF5D, 0x7D7B, 0xDF5F, 0x7D7C, 0xDF61, 0x7D7D, 0xDF65,	0x7D7F, 0xDF5B, 0x7D80, 0xDF59, 0x7D81, 0xB86A, 0x7D83, 0xDF60,
+	0x7D84, 0xDF64, 0x7D85, 0xDF5C, 0x7D86, 0xDF58, 0x7D88, 0xDF57,	0x7D8C, 0xDF62, 0x7D8D, 0xDF5A, 0x7D8E, 0xDF5E, 0x7D8F, 0xB86B,
+	0x7D91, 0xB869, 0x7D92, 0xDF66, 0x7D93, 0xB867, 0x7D94, 0xDF63,	0x7D96, 0xE372, 0x7D9C, 0xBAEE, 0x7D9D, 0xE36A, 0x7D9E, 0xBD78,
+	0x7D9F, 0xE374, 0x7DA0, 0xBAF1, 0x7DA1, 0xE378, 0x7DA2, 0xBAF7,	0x7DA3, 0xE365, 0x7DA6, 0xE375, 0x7DA7, 0xE362, 0x7DA9, 0xE377,
+	0x7DAA, 0xE366, 0x7DAC, 0xBAFE, 0x7DAD, 0xBAFB, 0x7DAE, 0xE376,	0x7DAF, 0xE370, 0x7DB0, 0xBAED, 0x7DB1, 0xBAF5, 0x7DB2, 0xBAF4,
+	0x7DB4, 0xBAF3, 0x7DB5, 0xBAF9, 0x7DB7, 0xE363, 0x7DB8, 0xBAFA,	0x7DB9, 0xE371, 0x7DBA, 0xBAF6, 0x7DBB, 0xBAEC, 0x7DBC, 0xE373,
+	0x7DBD, 0xBAEF, 0x7DBE, 0xBAF0, 0x7DBF, 0xBAF8, 0x7DC0, 0xE368,	0x7DC1, 0xE367, 0x7DC2, 0xE364, 0x7DC4, 0xE36C, 0x7DC5, 0xE369,
+	0x7DC6, 0xE36D, 0x7DC7, 0xBAFD, 0x7DC9, 0xE379, 0x7DCA, 0xBAF2,	0x7DCB, 0xE36E, 0x7DCC, 0xE36F, 0x7DCE, 0xE36B, 0x7DD2, 0xBAFC,
+	0x7DD7, 0xE6E7, 0x7DD8, 0xBD70, 0x7DD9, 0xBD79, 0x7DDA, 0xBD75,	0x7DDB, 0xE6E4, 0x7DDD, 0xBD72, 0x7DDE, 0xBD76, 0x7DDF, 0xE6F0,
+	0x7DE0, 0xBD6C, 0x7DE1, 0xE6E8, 0x7DE3, 0xBD74, 0x7DE6, 0xE6EB,	0x7DE7, 0xE6E6, 0x7DE8, 0xBD73, 0x7DE9, 0xBD77, 0x7DEA, 0xE6E5,
+	0x7DEC, 0xBD71, 0x7DEE, 0xE6EF, 0x7DEF, 0xBD6E, 0x7DF0, 0xE6EE,	0x7DF1, 0xE6ED, 0x7DF2, 0xBD7A, 0x7DF3, 0xE572, 0x7DF4, 0xBD6D,
+	0x7DF6, 0xE6EC, 0x7DF7, 0xE6E3, 0x7DF9, 0xBD7B, 0x7DFA, 0xE6EA,	0x7DFB, 0xBD6F, 0x7E03, 0xE6E9, 0x7E08, 0xBFA2, 0x7E09, 0xBFA7,
+	0x7E0A, 0xBF7E, 0x7E0B, 0xEAD8, 0x7E0C, 0xEACF, 0x7E0D, 0xEADB,	0x7E0E, 0xEAD3, 0x7E0F, 0xEAD9, 0x7E10, 0xBFA8, 0x7E11, 0xBFA1,
+	0x7E12, 0xEACC, 0x7E13, 0xEAD2, 0x7E14, 0xEADC, 0x7E15, 0xEAD5,	0x7E16, 0xEADA, 0x7E17, 0xEACE, 0x7E1A, 0xEAD6, 0x7E1B, 0xBFA3,
+	0x7E1C, 0xEAD4, 0x7E1D, 0xBFA6, 0x7E1E, 0xBFA5, 0x7E1F, 0xEAD0,	0x7E20, 0xEAD1, 0x7E21, 0xEACD, 0x7E22, 0xEAD7, 0x7E23, 0xBFA4,
+	0x7E24, 0xEADE, 0x7E25, 0xEADD, 0x7E29, 0xEDDA, 0x7E2A, 0xEDD6,	0x7E2B, 0xC15F, 0x7E2D, 0xEDD0, 0x7E2E, 0xC159, 0x7E2F, 0xC169,
+	0x7E30, 0xEDDC, 0x7E31, 0xC161, 0x7E32, 0xC15D, 0x7E33, 0xEDD3,	0x7E34, 0xC164, 0x7E35, 0xC167, 0x7E36, 0xEDDE, 0x7E37, 0xC15C,
+	0x7E38, 0xEDD5, 0x7E39, 0xC165, 0x7E3A, 0xEDE0, 0x7E3B, 0xEDDD,	0x7E3C, 0xEDD1, 0x7E3D, 0xC160, 0x7E3E, 0xC15A, 0x7E3F, 0xC168,
+	0x7E40, 0xEDD8, 0x7E41, 0xC163, 0x7E42, 0xEDD2, 0x7E43, 0xC15E,	0x7E44, 0xEDDF, 0x7E45, 0xC162, 0x7E46, 0xC15B, 0x7E47, 0xEDD9,
+	0x7E48, 0xC166, 0x7E49, 0xEDD7, 0x7E4C, 0xEDDB, 0x7E50, 0xF06E,	0x7E51, 0xF074, 0x7E52, 0xC2B9, 0x7E53, 0xF077, 0x7E54, 0xC2B4,
+	0x7E55, 0xC2B5, 0x7E56, 0xF06F, 0x7E57, 0xF076, 0x7E58, 0xF071,	0x7E59, 0xC2BA, 0x7E5A, 0xC2B7, 0x7E5C, 0xF06D, 0x7E5E, 0xC2B6,
+	0x7E5F, 0xF073, 0x7E60, 0xF075, 0x7E61, 0xC2B8, 0x7E62, 0xF072,	0x7E63, 0xF070, 0x7E68, 0xF2B8, 0x7E69, 0xC3B7, 0x7E6A, 0xC3B8,
+	0x7E6B, 0xC3B4, 0x7E6D, 0xC3B5, 0x7E6F, 0xF2B4, 0x7E70, 0xF2B2,	0x7E72, 0xF2B6, 0x7E73, 0xC3BA, 0x7E74, 0xF2B7, 0x7E75, 0xF2B0,
+	0x7E76, 0xF2AF, 0x7E77, 0xF2B3, 0x7E78, 0xF2B1, 0x7E79, 0xC3B6,	0x7E7A, 0xF2B5, 0x7E7B, 0xF4AC, 0x7E7C, 0xC47E, 0x7E7D, 0xC47D,
+	0x7E7E, 0xF4AD, 0x7E80, 0xF4AF, 0x7E81, 0xF4AE, 0x7E82, 0xC4A1,	0x7E86, 0xF5EB, 0x7E87, 0xF5E8, 0x7E88, 0xF5E9, 0x7E8A, 0xF5E7,
+	0x7E8B, 0xF5EA, 0x7E8C, 0xC4F2, 0x7E8D, 0xF5EC, 0x7E8F, 0xC4F1,	0x7E91, 0xF742, 0x7E93, 0xC5D5, 0x7E94, 0xC5D7, 0x7E95, 0xF7EE,
+	0x7E96, 0xC5D6, 0x7E97, 0xF8B9, 0x7E98, 0xF940, 0x7E99, 0xF942,	0x7E9A, 0xF8FE, 0x7E9B, 0xF941, 0x7E9C, 0xC66C, 0x7F36, 0xA6CE,
+	0x7F38, 0xACFB, 0x7F39, 0xD26F, 0x7F3A, 0xAFCA, 0x7F3D, 0xB2DA,	0x7F3E, 0xDAFC, 0x7F3F, 0xDAFD, 0x7F43, 0xEADF, 0x7F44, 0xC16A,
+	0x7F45, 0xEDE1, 0x7F48, 0xC2BB, 0x7F4A, 0xF2BA, 0x7F4B, 0xF2B9,	0x7F4C, 0xC4A2, 0x7F4D, 0xF5ED, 0x7F4F, 0xF743, 0x7F50, 0xC5F8,
+	0x7F51, 0xCA49, 0x7F54, 0xAAC9, 0x7F55, 0xA875, 0x7F58, 0xD04D,	0x7F5B, 0xD360, 0x7F5C, 0xD35B, 0x7F5D, 0xD35F, 0x7F5E, 0xD35D,
+	0x7F5F, 0xAFCB, 0x7F60, 0xD35E, 0x7F61, 0xD35C, 0x7F63, 0xD6F1,	0x7F65, 0xDAFE, 0x7F66, 0xDB40, 0x7F67, 0xDF69, 0x7F68, 0xDF6A,
+	0x7F69, 0xB86E, 0x7F6A, 0xB86F, 0x7F6B, 0xDF68, 0x7F6C, 0xDF6B,	0x7F6D, 0xDF67, 0x7F6E, 0xB86D, 0x7F70, 0xBB40, 0x7F72, 0xB870,
+	0x7F73, 0xE37A, 0x7F75, 0xBD7C, 0x7F76, 0xE6F1, 0x7F77, 0xBD7D,	0x7F79, 0xBFA9, 0x7F7A, 0xEAE2, 0x7F7B, 0xEAE0, 0x7F7C, 0xEAE1,
+	0x7F7D, 0xEDE4, 0x7F7E, 0xEDE3, 0x7F7F, 0xEDE2, 0x7F83, 0xF2BB,	0x7F85, 0xC3B9, 0x7F86, 0xF2BC, 0x7F87, 0xF744, 0x7F88, 0xC5F9,
+	0x7F89, 0xF8BA, 0x7F8A, 0xA6CF, 0x7F8B, 0xAACB, 0x7F8C, 0xAACA,	0x7F8D, 0xD04F, 0x7F8E, 0xACFC, 0x7F91, 0xD04E, 0x7F92, 0xD362,
+	0x7F94, 0xAFCC, 0x7F95, 0xD6F2, 0x7F96, 0xD361, 0x7F9A, 0xB2DC,	0x7F9B, 0xD6F5, 0x7F9C, 0xD6F3, 0x7F9D, 0xD6F4, 0x7F9E, 0xB2DB,
+	0x7FA0, 0xDB42, 0x7FA1, 0xDB43, 0x7FA2, 0xDB41, 0x7FA4, 0xB873,	0x7FA5, 0xDF6D, 0x7FA6, 0xDF6C, 0x7FA7, 0xDF6E, 0x7FA8, 0xB872,
+	0x7FA9, 0xB871, 0x7FAC, 0xE6F2, 0x7FAD, 0xE6F4, 0x7FAF, 0xBD7E,	0x7FB0, 0xE6F3, 0x7FB1, 0xEAE3, 0x7FB2, 0xBFAA, 0x7FB3, 0xF079,
+	0x7FB5, 0xF078, 0x7FB6, 0xC3BB, 0x7FB7, 0xF2BD, 0x7FB8, 0xC3BD,	0x7FB9, 0xC3BC, 0x7FBA, 0xF4B0, 0x7FBB, 0xF5EE, 0x7FBC, 0xC4F3,
+	0x7FBD, 0xA6D0, 0x7FBE, 0xD050, 0x7FBF, 0xACFD, 0x7FC0, 0xD365,	0x7FC1, 0xAFCE, 0x7FC2, 0xD364, 0x7FC3, 0xD363, 0x7FC5, 0xAFCD,
+	0x7FC7, 0xD6FB, 0x7FC9, 0xD6FD, 0x7FCA, 0xD6F6, 0x7FCB, 0xD6F7,	0x7FCC, 0xB2DD, 0x7FCD, 0xD6F8, 0x7FCE, 0xB2DE, 0x7FCF, 0xD6FC,
+	0x7FD0, 0xD6F9, 0x7FD1, 0xD6FA, 0x7FD2, 0xB2DF, 0x7FD4, 0xB5BE,	0x7FD5, 0xB5BF, 0x7FD7, 0xDB44, 0x7FDB, 0xDF6F, 0x7FDC, 0xDF70,
+	0x7FDE, 0xE37E, 0x7FDF, 0xBB43, 0x7FE0, 0xBB41, 0x7FE1, 0xBB42,	0x7FE2, 0xE37B, 0x7FE3, 0xE37C, 0x7FE5, 0xE37D, 0x7FE6, 0xE6F9,
+	0x7FE8, 0xE6FA, 0x7FE9, 0xBDA1, 0x7FEA, 0xE6F7, 0x7FEB, 0xE6F6,	0x7FEC, 0xE6F8, 0x7FED, 0xE6F5, 0x7FEE, 0xBFAD, 0x7FEF, 0xEAE4,
+	0x7FF0, 0xBFAB, 0x7FF1, 0xBFAC, 0x7FF2, 0xEDE6, 0x7FF3, 0xC16B,	0x7FF4, 0xEDE5, 0x7FF5, 0xEFA8, 0x7FF7, 0xF07A, 0x7FF8, 0xF07B,
+	0x7FF9, 0xC2BC, 0x7FFB, 0xC2BD, 0x7FFC, 0xC16C, 0x7FFD, 0xF2BE,	0x7FFE, 0xF2BF, 0x7FFF, 0xF4B1, 0x8000, 0xC4A3, 0x8001, 0xA6D1,
+	0x8003, 0xA6D2, 0x8004, 0xACFE, 0x8005, 0xAACC, 0x8006, 0xAFCF,	0x8007, 0xD051, 0x800B, 0xB5C0, 0x800C, 0xA6D3, 0x800D, 0xAD41,
+	0x800E, 0xD052, 0x800F, 0xD053, 0x8010, 0xAD40, 0x8011, 0xAD42,	0x8012, 0xA6D4, 0x8014, 0xD054, 0x8015, 0xAFD1, 0x8016, 0xD366,
+	0x8017, 0xAFD3, 0x8018, 0xAFD0, 0x8019, 0xAFD2, 0x801B, 0xD741,	0x801C, 0xB2E0, 0x801E, 0xD740, 0x801F, 0xD6FE, 0x8021, 0xDF71,
+	0x8024, 0xE3A1, 0x8026, 0xBDA2, 0x8028, 0xBFAE, 0x8029, 0xEAE6,	0x802A, 0xEAE5, 0x802C, 0xEDE7, 0x8030, 0xF5EF, 0x8033, 0xA6D5,
+	0x8034, 0xCB73, 0x8035, 0xCDAA, 0x8036, 0xAD43, 0x8037, 0xD055,	0x8039, 0xD368, 0x803D, 0xAFD4, 0x803E, 0xD367, 0x803F, 0xAFD5,
+	0x8043, 0xD743, 0x8046, 0xB2E2, 0x8047, 0xD742, 0x8048, 0xD744,	0x804A, 0xB2E1, 0x804F, 0xDB46, 0x8050, 0xDB47, 0x8051, 0xDB45,
+	0x8052, 0xB5C1, 0x8056, 0xB874, 0x8058, 0xB875, 0x805A, 0xBB45,	0x805C, 0xE3A3, 0x805D, 0xE3A2, 0x805E, 0xBB44, 0x8064, 0xE6FB,
+	0x8067, 0xE6FC, 0x806C, 0xEAE7, 0x806F, 0xC170, 0x8070, 0xC16F,	0x8071, 0xC16D, 0x8072, 0xC16E, 0x8073, 0xC171, 0x8075, 0xF07C,
+	0x8076, 0xC2BF, 0x8077, 0xC2BE, 0x8078, 0xF2C0, 0x8079, 0xF4B2,	0x807D, 0xC5A5, 0x807E, 0xC5A4, 0x807F, 0xA6D6, 0x8082, 0xD1FB,
+	0x8084, 0xB877, 0x8085, 0xB5C2, 0x8086, 0xB876, 0x8087, 0xBB46,	0x8089, 0xA6D7, 0x808A, 0xC9A9, 0x808B, 0xA6D8, 0x808C, 0xA6D9,
+	0x808F, 0xCDAB, 0x8090, 0xCB76, 0x8092, 0xCB77, 0x8093, 0xA877,	0x8095, 0xCB74, 0x8096, 0xA876, 0x8098, 0xA879, 0x8099, 0xCB75,
+	0x809A, 0xA87B, 0x809B, 0xA87A, 0x809C, 0xCB78, 0x809D, 0xA878,	0x80A1, 0xAAD1, 0x80A2, 0xAACF, 0x80A3, 0xCDAD, 0x80A5, 0xAACE,
+	0x80A9, 0xAAD3, 0x80AA, 0xAAD5, 0x80AB, 0xAAD2, 0x80AD, 0xCDB0,	0x80AE, 0xCDAC, 0x80AF, 0xAAD6, 0x80B1, 0xAAD0, 0x80B2, 0xA87C,
+	0x80B4, 0xAAD4, 0x80B5, 0xCDAF, 0x80B8, 0xCDAE, 0x80BA, 0xAACD,	0x80C2, 0xD05B, 0x80C3, 0xAD47, 0x80C4, 0xAD48, 0x80C5, 0xD05D,
+	0x80C7, 0xD057, 0x80C8, 0xD05A, 0x80C9, 0xD063, 0x80CA, 0xD061,	0x80CC, 0xAD49, 0x80CD, 0xD067, 0x80CE, 0xAD4C, 0x80CF, 0xD064,
+	0x80D0, 0xD05C, 0x80D1, 0xD059, 0x80D4, 0xDB49, 0x80D5, 0xD062,	0x80D6, 0xAD44, 0x80D7, 0xD065, 0x80D8, 0xD056, 0x80D9, 0xD05F,
+	0x80DA, 0xAD46, 0x80DB, 0xAD4B, 0x80DC, 0xD060, 0x80DD, 0xAD4F,	0x80DE, 0xAD4D, 0x80E0, 0xD058, 0x80E1, 0xAD4A, 0x80E3, 0xD05E,
+	0x80E4, 0xAD4E, 0x80E5, 0xAD45, 0x80E6, 0xD066, 0x80ED, 0xAFDA,	0x80EF, 0xAFE3, 0x80F0, 0xAFD8, 0x80F1, 0xAFD6, 0x80F2, 0xD36A,
+	0x80F3, 0xAFDE, 0x80F4, 0xAFDB, 0x80F5, 0xD36C, 0x80F8, 0xAFDD,	0x80F9, 0xD36B, 0x80FA, 0xD369, 0x80FB, 0xD36E, 0x80FC, 0xAFE2,
+	0x80FD, 0xAFE0, 0x80FE, 0xDB48, 0x8100, 0xD36F, 0x8101, 0xD36D,	0x8102, 0xAFD7, 0x8105, 0xAFD9, 0x8106, 0xAFDC, 0x8108, 0xAFDF,
+	0x810A, 0xAFE1, 0x8115, 0xD74E, 0x8116, 0xB2E4, 0x8118, 0xD745,	0x8119, 0xD747, 0x811B, 0xD748, 0x811D, 0xD750, 0x811E, 0xD74C,
+	0x811F, 0xD74A, 0x8121, 0xD74D, 0x8122, 0xD751, 0x8123, 0xB2E5,	0x8124, 0xB2E9, 0x8125, 0xD746, 0x8127, 0xD74F, 0x8129, 0xB2E7,
+	0x812B, 0xB2E6, 0x812C, 0xD74B, 0x812D, 0xD749, 0x812F, 0xB2E3,	0x8130, 0xB2E8, 0x8139, 0xB5C8, 0x813A, 0xDB51, 0x813D, 0xDB4F,
+	0x813E, 0xB5CA, 0x8143, 0xDB4A, 0x8144, 0xDFA1, 0x8146, 0xB5C9,	0x8147, 0xDB4E, 0x814A, 0xDB4B, 0x814B, 0xB5C5, 0x814C, 0xB5CB,
+	0x814D, 0xDB50, 0x814E, 0xB5C7, 0x814F, 0xDB4D, 0x8150, 0xBB47,	0x8151, 0xB5C6, 0x8152, 0xDB4C, 0x8153, 0xB5CC, 0x8154, 0xB5C4,
+	0x8155, 0xB5C3, 0x815B, 0xDF77, 0x815C, 0xDF75, 0x815E, 0xDF7B,	0x8160, 0xDF73, 0x8161, 0xDFA2, 0x8162, 0xDF78, 0x8164, 0xDF72,
+	0x8165, 0xB87B, 0x8166, 0xB8A3, 0x8167, 0xDF7D, 0x8169, 0xDF76,	0x816B, 0xB87E, 0x816E, 0xB87C, 0x816F, 0xDF7E, 0x8170, 0xB879,
+	0x8171, 0xB878, 0x8172, 0xDF79, 0x8173, 0xB87D, 0x8174, 0xB5CD,	0x8176, 0xDF7C, 0x8177, 0xDF74, 0x8178, 0xB87A, 0x8179, 0xB8A1,
+	0x817A, 0xB8A2, 0x817F, 0xBB4C, 0x8180, 0xBB48, 0x8182, 0xBB4D,	0x8183, 0xE3A6, 0x8186, 0xE3A5, 0x8187, 0xE3A7, 0x8188, 0xBB4A,
+	0x8189, 0xE3A4, 0x818A, 0xBB4B, 0x818B, 0xE3AA, 0x818C, 0xE3A9,	0x818D, 0xE3A8, 0x818F, 0xBB49, 0x8195, 0xE741, 0x8197, 0xE744,
+	0x8198, 0xBDA8, 0x8199, 0xE743, 0x819A, 0xBDA7, 0x819B, 0xBDA3,	0x819C, 0xBDA4, 0x819D, 0xBDA5, 0x819E, 0xE740, 0x819F, 0xE6FE,
+	0x81A0, 0xBDA6, 0x81A2, 0xE742, 0x81A3, 0xE6FD, 0x81A6, 0xEAE9,	0x81A7, 0xEAF3, 0x81A8, 0xBFB1, 0x81A9, 0xBFB0, 0x81AB, 0xEAED,
+	0x81AC, 0xEAEF, 0x81AE, 0xEAEA, 0x81B0, 0xEAEE, 0x81B1, 0xEAE8,	0x81B2, 0xEAF1, 0x81B3, 0xBFAF, 0x81B4, 0xEAF0, 0x81B5, 0xEAEC,
+	0x81B7, 0xEAF2, 0x81B9, 0xEAEB, 0x81BA, 0xC174, 0x81BB, 0xEDE8,	0x81BC, 0xEDEE, 0x81BD, 0xC178, 0x81BE, 0xC17A, 0x81BF, 0xC177,
+	0x81C0, 0xC176, 0x81C2, 0xC175, 0x81C3, 0xC173, 0x81C4, 0xEDE9,	0x81C5, 0xEDEC, 0x81C6, 0xC172, 0x81C7, 0xEDED, 0x81C9, 0xC179,
+	0x81CA, 0xEDEB, 0x81CC, 0xEDEA, 0x81CD, 0xC2C0, 0x81CF, 0xC2C1,	0x81D0, 0xF0A1, 0x81D1, 0xF07D, 0x81D2, 0xF07E, 0x81D5, 0xF2C2,
+	0x81D7, 0xF2C1, 0x81D8, 0xC3BE, 0x81D9, 0xF4B4, 0x81DA, 0xC4A4,	0x81DB, 0xF4B3, 0x81DD, 0xF5F0, 0x81DE, 0xF745, 0x81DF, 0xC5A6,
+	0x81E0, 0xF943, 0x81E1, 0xF944, 0x81E2, 0xC5D8, 0x81E3, 0xA6DA,	0x81E5, 0xAAD7, 0x81E6, 0xDB52, 0x81E7, 0xBB4E, 0x81E8, 0xC17B,
+	0x81E9, 0xEDEF, 0x81EA, 0xA6DB, 0x81EC, 0xAFE5, 0x81ED, 0xAFE4,	0x81EE, 0xDB53, 0x81F2, 0xEAF4, 0x81F3, 0xA6DC, 0x81F4, 0xAD50,
+	0x81F7, 0xDB54, 0x81F8, 0xDB55, 0x81F9, 0xDB56, 0x81FA, 0xBB4F,	0x81FB, 0xBFB2, 0x81FC, 0xA6DD, 0x81FE, 0xAAD8, 0x81FF, 0xD068,
+	0x8200, 0xAFE6, 0x8201, 0xD370, 0x8202, 0xB2EA, 0x8204, 0xDB57,	0x8205, 0xB8A4, 0x8207, 0xBB50, 0x8208, 0xBFB3, 0x8209, 0xC17C,
+	0x820A, 0xC2C2, 0x820B, 0xF4B5, 0x820C, 0xA6DE, 0x820D, 0xAAD9,	0x8210, 0xAFE7, 0x8211, 0xD752, 0x8212, 0xB5CE, 0x8214, 0xBB51,
+	0x8215, 0xE3AB, 0x8216, 0xE745, 0x821B, 0xA6DF, 0x821C, 0xB5CF,	0x821D, 0xDFA3, 0x821E, 0xBB52, 0x821F, 0xA6E0, 0x8220, 0xCDB1,
+	0x8221, 0xD069, 0x8222, 0xAD51, 0x8225, 0xD372, 0x8228, 0xAFEA,	0x822A, 0xAFE8, 0x822B, 0xAFE9, 0x822C, 0xAFEB, 0x822F, 0xD371,
+	0x8232, 0xD757, 0x8233, 0xD754, 0x8234, 0xD756, 0x8235, 0xB2EB,	0x8236, 0xB2ED, 0x8237, 0xB2EC, 0x8238, 0xD753, 0x8239, 0xB2EE,
+	0x823A, 0xD755, 0x823C, 0xDB58, 0x823D, 0xDB59, 0x823F, 0xDB5A,	0x8240, 0xDFA6, 0x8242, 0xDFA7, 0x8244, 0xDFA5, 0x8245, 0xDFA8,
+	0x8247, 0xB8A5, 0x8249, 0xDFA4, 0x824B, 0xBB53, 0x824E, 0xE74A,	0x824F, 0xE746, 0x8250, 0xE749, 0x8251, 0xE74B, 0x8252, 0xE748,
+	0x8253, 0xE747, 0x8255, 0xEAF5, 0x8256, 0xEAF6, 0x8257, 0xEAF7,	0x8258, 0xBFB4, 0x8259, 0xBFB5, 0x825A, 0xEDF1, 0x825B, 0xEDF0,
+	0x825C, 0xEDF2, 0x825E, 0xF0A3, 0x825F, 0xF0A2, 0x8261, 0xF2C4,	0x8263, 0xF2C5, 0x8264, 0xF2C3, 0x8266, 0xC4A5, 0x8268, 0xF4B6,
+	0x8269, 0xF4B7, 0x826B, 0xF746, 0x826C, 0xF7EF, 0x826D, 0xF8BB,	0x826E, 0xA6E1, 0x826F, 0xA87D, 0x8271, 0xC17D, 0x8272, 0xA6E2,
+	0x8274, 0xD758, 0x8275, 0xDB5B, 0x8277, 0xC641, 0x8278, 0xCA4A,	0x827C, 0xCA4B, 0x827D, 0xCA4D, 0x827E, 0xA6E3, 0x827F, 0xCA4E,
+	0x8280, 0xCA4C, 0x8283, 0xCBA2, 0x8284, 0xCBA3, 0x8285, 0xCB7B,	0x828A, 0xCBA1, 0x828B, 0xA8A1, 0x828D, 0xA8A2, 0x828E, 0xCB7C,
+	0x828F, 0xCB7A, 0x8290, 0xCB79, 0x8291, 0xCB7D, 0x8292, 0xA87E,	0x8293, 0xCB7E, 0x8294, 0xD06A, 0x8298, 0xCDB6, 0x8299, 0xAADC,
+	0x829A, 0xCDB5, 0x829B, 0xCDB7, 0x829D, 0xAADB, 0x829E, 0xCDBC,	0x829F, 0xAADF, 0x82A0, 0xCDB2, 0x82A1, 0xCDC0, 0x82A2, 0xCDC6,
+	0x82A3, 0xAAE6, 0x82A4, 0xCDC3, 0x82A5, 0xAAE3, 0x82A7, 0xCDB9,	0x82A8, 0xCDBF, 0x82A9, 0xCDC1, 0x82AB, 0xCDB4, 0x82AC, 0xAAE2,
+	0x82AD, 0xAADD, 0x82AE, 0xCDBA, 0x82AF, 0xAAE4, 0x82B0, 0xAAE7,	0x82B1, 0xAAE1, 0x82B3, 0xAADA, 0x82B4, 0xCDBE, 0x82B5, 0xCDB8,
+	0x82B6, 0xCDC5, 0x82B7, 0xAAE9, 0x82B8, 0xAAE5, 0x82B9, 0xAAE0,	0x82BA, 0xCDBD, 0x82BB, 0xAFEC, 0x82BC, 0xCDBB, 0x82BD, 0xAADE,
+	0x82BE, 0xAAE8, 0x82C0, 0xCDB3, 0x82C2, 0xCDC2, 0x82C3, 0xCDC4,	0x82D1, 0xAD62, 0x82D2, 0xAD5C, 0x82D3, 0xAD64, 0x82D4, 0xAD61,
+	0x82D5, 0xD071, 0x82D6, 0xD074, 0x82D7, 0xAD5D, 0x82D9, 0xD06B,	0x82DB, 0xAD56, 0x82DC, 0xAD60, 0x82DE, 0xAD63, 0x82DF, 0xAD65,
+	0x82E0, 0xD0A2, 0x82E1, 0xD077, 0x82E3, 0xAD55, 0x82E4, 0xD0A1,	0x82E5, 0xAD59, 0x82E6, 0xAD57, 0x82E7, 0xAD52, 0x82E8, 0xD06F,
+	0x82EA, 0xD07E, 0x82EB, 0xD073, 0x82EC, 0xD076, 0x82ED, 0xD0A5,	0x82EF, 0xAD66, 0x82F0, 0xD07D, 0x82F1, 0xAD5E, 0x82F2, 0xD078,
+	0x82F3, 0xD0A4, 0x82F4, 0xD075, 0x82F5, 0xD079, 0x82F6, 0xD07C,	0x82F9, 0xD06D, 0x82FA, 0xD0A3, 0x82FB, 0xD07B, 0x82FE, 0xD06C,
+	0x8300, 0xD070, 0x8301, 0xAD5F, 0x8302, 0xAD5A, 0x8303, 0xAD53,	0x8304, 0xAD58, 0x8305, 0xAD54, 0x8306, 0xAD67, 0x8307, 0xD06E,
+	0x8308, 0xD3A5, 0x8309, 0xAD5B, 0x830C, 0xD07A, 0x830D, 0xCE41,	0x8316, 0xD3A8, 0x8317, 0xAFFA, 0x8319, 0xD376, 0x831B, 0xD3A3,
+	0x831C, 0xD37D, 0x831E, 0xD3B2, 0x8320, 0xD3AA, 0x8322, 0xD37E,	0x8324, 0xD3A9, 0x8325, 0xD378, 0x8326, 0xD37C, 0x8327, 0xD3B5,
+	0x8328, 0xAFFD, 0x8329, 0xD3AD, 0x832A, 0xD3A4, 0x832B, 0xAFED,	0x832C, 0xD3B3, 0x832D, 0xD374, 0x832F, 0xD3AC, 0x8331, 0xAFFC,
+	0x8332, 0xAFF7, 0x8333, 0xD373, 0x8334, 0xAFF5, 0x8335, 0xAFF4,	0x8336, 0xAFF9, 0x8337, 0xD3AB, 0x8338, 0xAFF1, 0x8339, 0xAFF8,
+	0x833A, 0xD072, 0x833B, 0xDB5C, 0x833C, 0xD3A6, 0x833F, 0xD37A,	0x8340, 0xAFFB, 0x8341, 0xD37B, 0x8342, 0xD3A1, 0x8343, 0xAFFE,
+	0x8344, 0xD375, 0x8345, 0xD3AF, 0x8347, 0xD3AE, 0x8348, 0xD3B6,	0x8349, 0xAFF3, 0x834A, 0xAFF0, 0x834B, 0xD3B4, 0x834C, 0xD3B0,
+	0x834D, 0xD3A7, 0x834E, 0xD3A2, 0x834F, 0xAFF6, 0x8350, 0xAFF2,	0x8351, 0xD377, 0x8352, 0xAFEE, 0x8353, 0xD3B1, 0x8354, 0xAFEF,
+	0x8356, 0xD379, 0x8373, 0xD75E, 0x8374, 0xD760, 0x8375, 0xD765,	0x8376, 0xD779, 0x8377, 0xB2FC, 0x8378, 0xB2F2, 0x837A, 0xD75D,
+	0x837B, 0xB2FD, 0x837C, 0xB2FE, 0x837D, 0xD768, 0x837E, 0xD76F,	0x837F, 0xD775, 0x8381, 0xD762, 0x8383, 0xD769, 0x8386, 0xB340,
+	0x8387, 0xD777, 0x8388, 0xD772, 0x8389, 0xB2FA, 0x838A, 0xB2F8,	0x838B, 0xD76E, 0x838C, 0xD76A, 0x838D, 0xD75C, 0x838E, 0xB2EF,
+	0x838F, 0xD761, 0x8390, 0xD759, 0x8392, 0xB2F7, 0x8393, 0xB2F9,	0x8394, 0xD766, 0x8395, 0xD763, 0x8396, 0xB2F4, 0x8397, 0xD773,
+	0x8398, 0xB2F1, 0x8399, 0xD764, 0x839A, 0xD77A, 0x839B, 0xD76C,	0x839D, 0xD76B, 0x839E, 0xB2F0, 0x83A0, 0xB2FB, 0x83A2, 0xB2F3,
+	0x83A3, 0xD75A, 0x83A4, 0xD75F, 0x83A5, 0xD770, 0x83A6, 0xD776,	0x83A7, 0xB341, 0x83A8, 0xD75B, 0x83A9, 0xD767, 0x83AA, 0xD76D,
+	0x83AB, 0xB2F6, 0x83AE, 0xD778, 0x83AF, 0xD771, 0x83B0, 0xD774,	0x83BD, 0xB2F5, 0x83BF, 0xDB6C, 0x83C0, 0xDB60, 0x83C1, 0xB5D7,
+	0x83C2, 0xDB7D, 0x83C3, 0xDBA7, 0x83C4, 0xDBAA, 0x83C5, 0xB5D5,	0x83C6, 0xDB68, 0x83C7, 0xDBA3, 0x83C8, 0xDB69, 0x83C9, 0xDB77,
+	0x83CA, 0xB5E2, 0x83CB, 0xDB73, 0x83CC, 0xB5DF, 0x83CE, 0xDB74,	0x83CF, 0xDB5D, 0x83D1, 0xDBA4, 0x83D4, 0xB5E8, 0x83D5, 0xDBA1,
+	0x83D6, 0xDB75, 0x83D7, 0xDBAC, 0x83D8, 0xDB70, 0x83D9, 0xDFC8,	0x83DB, 0xDBAF, 0x83DC, 0xB5E6, 0x83DD, 0xDB6E, 0x83DE, 0xDB7A,
+	0x83DF, 0xB5E9, 0x83E0, 0xB5D4, 0x83E1, 0xDB72, 0x83E2, 0xDBAD,	0x83E3, 0xDB6B, 0x83E4, 0xDB64, 0x83E5, 0xDB6F, 0x83E7, 0xDB63,
+	0x83E8, 0xDB61, 0x83E9, 0xB5D0, 0x83EA, 0xDBA5, 0x83EB, 0xDB6A,	0x83EC, 0xDBA8, 0x83EE, 0xDBA9, 0x83EF, 0xB5D8, 0x83F0, 0xB5DD,
+	0x83F1, 0xB5D9, 0x83F2, 0xB5E1, 0x83F3, 0xDB7E, 0x83F4, 0xB5DA,	0x83F5, 0xDB76, 0x83F6, 0xDB66, 0x83F8, 0xB5D2, 0x83F9, 0xDB5E,
+	0x83FA, 0xDBA2, 0x83FB, 0xDBAB, 0x83FC, 0xDB65, 0x83FD, 0xB5E0,	0x83FE, 0xDBB0, 0x83FF, 0xDB71, 0x8401, 0xDB6D, 0x8403, 0xB5D1,
+	0x8404, 0xB5E5, 0x8406, 0xDB7C, 0x8407, 0xB5E7, 0x8409, 0xDB78,	0x840A, 0xB5DC, 0x840B, 0xB5D6, 0x840C, 0xB5DE, 0x840D, 0xB5D3,
+	0x840E, 0xB5E4, 0x840F, 0xDB79, 0x8410, 0xDB67, 0x8411, 0xDB7B,	0x8412, 0xDB62, 0x8413, 0xDBA6, 0x841B, 0xDBAE, 0x8423, 0xDB5F,
+	0x8429, 0xDFC7, 0x842B, 0xDFDD, 0x842C, 0xB855, 0x842D, 0xDFCC,	0x842F, 0xDFCA, 0x8430, 0xDFB5, 0x8431, 0xB8A9, 0x8432, 0xDFC5,
+	0x8433, 0xDFD9, 0x8434, 0xDFC1, 0x8435, 0xB8B1, 0x8436, 0xDFD8,	0x8437, 0xDFBF, 0x8438, 0xB5E3, 0x8439, 0xDFCF, 0x843A, 0xDFC0,
+	0x843B, 0xDFD6, 0x843C, 0xB8B0, 0x843D, 0xB8A8, 0x843F, 0xDFAA,	0x8440, 0xDFB2, 0x8442, 0xDFCB, 0x8443, 0xDFC3, 0x8444, 0xDFDC,
+	0x8445, 0xDFC6, 0x8446, 0xB8B6, 0x8447, 0xDFD7, 0x8449, 0xB8AD,	0x844B, 0xDFC9, 0x844C, 0xDFD1, 0x844D, 0xDFB6, 0x844E, 0xDFD0,
+	0x8450, 0xDFE1, 0x8451, 0xDFB1, 0x8452, 0xDFD2, 0x8454, 0xDFDF,	0x8456, 0xDFAB, 0x8457, 0xB5DB, 0x8459, 0xDFB9, 0x845A, 0xDFB8,
+	0x845B, 0xB8AF, 0x845D, 0xDFBC, 0x845E, 0xDFBE, 0x845F, 0xDFCD,	0x8460, 0xDFDE, 0x8461, 0xB8B2, 0x8463, 0xB8B3, 0x8465, 0xDFB0,
+	0x8466, 0xB8AB, 0x8467, 0xDFB4, 0x8468, 0xDFDA, 0x8469, 0xB8B4,	0x846B, 0xB8AC, 0x846C, 0xB8AE, 0x846D, 0xB8B5, 0x846E, 0xDFE0,
+	0x846F, 0xDFD3, 0x8470, 0xDFCE, 0x8473, 0xDFBB, 0x8474, 0xDFBA,	0x8475, 0xB8AA, 0x8476, 0xDFAC, 0x8477, 0xB8A7, 0x8478, 0xDFC4,
+	0x8479, 0xDFAD, 0x847A, 0xDFC2, 0x847D, 0xDFB7, 0x847E, 0xDFDB,	0x8482, 0xB8A6, 0x8486, 0xDFB3, 0x848D, 0xDFAF, 0x848E, 0xDFD5,
+	0x848F, 0xDFAE, 0x8490, 0xBB60, 0x8491, 0xE3D3, 0x8494, 0xE3C2,	0x8497, 0xE3AC, 0x8498, 0xE3CA, 0x8499, 0xBB58, 0x849A, 0xE3BB,
+	0x849B, 0xE3C5, 0x849C, 0xBB5B, 0x849D, 0xE3BE, 0x849E, 0xBB59,	0x849F, 0xE3AF, 0x84A0, 0xE3CD, 0x84A1, 0xE3AE, 0x84A2, 0xE3C1,
+	0x84A4, 0xE3AD, 0x84A7, 0xE3BF, 0x84A8, 0xE3C8, 0x84A9, 0xE3C6,	0x84AA, 0xE3BA, 0x84AB, 0xE3B5, 0x84AC, 0xE3B3, 0x84AE, 0xE3B4,
+	0x84AF, 0xE3C7, 0x84B0, 0xE3D2, 0x84B1, 0xE3BC, 0x84B2, 0xBB5A,	0x84B4, 0xE3B7, 0x84B6, 0xE3CB, 0x84B8, 0xBB5D, 0x84B9, 0xE3B6,
+	0x84BA, 0xE3B0, 0x84BB, 0xE3C0, 0x84BC, 0xBB61, 0x84BF, 0xBB55,	0x84C0, 0xBB5E, 0x84C1, 0xE3B8, 0x84C2, 0xE3B2, 0x84C4, 0xBB57,
+	0x84C5, 0xDFD4, 0x84C6, 0xBB56, 0x84C7, 0xE3C3, 0x84C9, 0xBB54,	0x84CA, 0xBB63, 0x84CB, 0xBB5C, 0x84CC, 0xE3C4, 0x84CD, 0xE3B9,
+	0x84CE, 0xE3B1, 0x84CF, 0xE3CC, 0x84D0, 0xE3BD, 0x84D1, 0xBB62,	0x84D2, 0xE3D0, 0x84D3, 0xBB5F, 0x84D4, 0xE3CF, 0x84D6, 0xE3C9,
+	0x84D7, 0xE3CE, 0x84DB, 0xE3D1, 0x84E7, 0xE773, 0x84E8, 0xE774,	0x84E9, 0xE767, 0x84EA, 0xE766, 0x84EB, 0xE762, 0x84EC, 0xBDB4,
+	0x84EE, 0xBDAC, 0x84EF, 0xE776, 0x84F0, 0xE775, 0x84F1, 0xDFA9,	0x84F2, 0xE75F, 0x84F3, 0xE763, 0x84F4, 0xE75D, 0x84F6, 0xE770,
+	0x84F7, 0xE761, 0x84F9, 0xE777, 0x84FA, 0xE75A, 0x84FB, 0xE758,	0x84FC, 0xE764, 0x84FD, 0xE76E, 0x84FE, 0xE769, 0x84FF, 0xBDB6,
+	0x8500, 0xE74F, 0x8502, 0xE76D, 0x8506, 0xBDB7, 0x8507, 0xDFBD,	0x8508, 0xE75B, 0x8509, 0xE752, 0x850A, 0xE755, 0x850B, 0xE77B,
+	0x850C, 0xE75C, 0x850D, 0xE753, 0x850E, 0xE751, 0x850F, 0xE74E,	0x8511, 0xBDB0, 0x8512, 0xE765, 0x8513, 0xBDAF, 0x8514, 0xBDB3,
+	0x8515, 0xE760, 0x8516, 0xE768, 0x8517, 0xBDA9, 0x8518, 0xE778,	0x8519, 0xE77C, 0x851A, 0xBDAB, 0x851C, 0xE757, 0x851D, 0xE76B,
+	0x851E, 0xE76F, 0x851F, 0xE754, 0x8520, 0xE779, 0x8521, 0xBDB2,	0x8523, 0xBDB1, 0x8524, 0xE74C, 0x8525, 0xBDB5, 0x8526, 0xE772,
+	0x8527, 0xE756, 0x8528, 0xE76A, 0x8529, 0xE750, 0x852A, 0xE75E,	0x852B, 0xE759, 0x852C, 0xBDAD, 0x852D, 0xBDAE, 0x852E, 0xE76C,
+	0x852F, 0xE77D, 0x8530, 0xE77A, 0x8531, 0xE771, 0x853B, 0xE74D,	0x853D, 0xBDAA, 0x853E, 0xEB49, 0x8540, 0xEB40, 0x8541, 0xEB43,
+	0x8543, 0xBFBB, 0x8544, 0xEB45, 0x8545, 0xEAF9, 0x8546, 0xEB41,	0x8547, 0xEB47, 0x8548, 0xBFB8, 0x8549, 0xBFBC, 0x854A, 0xBFB6,
+	0x854D, 0xEAFB, 0x854E, 0xEB4C, 0x8551, 0xEB46, 0x8553, 0xEAFC,	0x8554, 0xEB55, 0x8555, 0xEB4F, 0x8556, 0xEAF8, 0x8557, 0xEE46,
+	0x8558, 0xEAFE, 0x8559, 0xBFB7, 0x855B, 0xEB4A, 0x855D, 0xEB54,	0x855E, 0xBFBF, 0x8560, 0xEB51, 0x8561, 0xEAFD, 0x8562, 0xEB44,
+	0x8563, 0xEB48, 0x8564, 0xEB42, 0x8565, 0xEB56, 0x8566, 0xEB53,	0x8567, 0xEB50, 0x8568, 0xBFB9, 0x8569, 0xBFBA, 0x856A, 0xBFBE,
+	0x856B, 0xEAFA, 0x856C, 0xEB57, 0x856D, 0xBFBD, 0x856E, 0xEB4D,	0x8571, 0xEB4B, 0x8575, 0xEB4E, 0x8576, 0xEE53, 0x8577, 0xEE40,
+	0x8578, 0xEE45, 0x8579, 0xEE52, 0x857A, 0xEE44, 0x857B, 0xEDFB,	0x857C, 0xEE41, 0x857E, 0xC1A2, 0x8580, 0xEDF4, 0x8581, 0xEE4D,
+	0x8582, 0xEE4F, 0x8583, 0xEDF3, 0x8584, 0xC1A1, 0x8585, 0xEE51,	0x8586, 0xEE49, 0x8587, 0xC1A8, 0x8588, 0xEE50, 0x8589, 0xEE42,
+	0x858A, 0xC1AA, 0x858B, 0xEDF9, 0x858C, 0xEB52, 0x858D, 0xEE4A,	0x858E, 0xEE47, 0x858F, 0xEDF5, 0x8590, 0xEE55, 0x8591, 0xC1A4,
+	0x8594, 0xC1A5, 0x8595, 0xEDF7, 0x8596, 0xEE48, 0x8598, 0xEE54,	0x8599, 0xEE4B, 0x859A, 0xEDFD, 0x859B, 0xC1A7, 0x859C, 0xC1A3,
+	0x859D, 0xEE4C, 0x859E, 0xEDFE, 0x859F, 0xEE56, 0x85A0, 0xEDF8,	0x85A1, 0xEE43, 0x85A2, 0xEE4E, 0x85A3, 0xEDFA, 0x85A4, 0xEDFC,
+	0x85A6, 0xC2CB, 0x85A7, 0xEDF6, 0x85A8, 0xC1A9, 0x85A9, 0xC2C4,	0x85AA, 0xC17E, 0x85AF, 0xC1A6, 0x85B0, 0xC2C8, 0x85B1, 0xF0B3,
+	0x85B3, 0xF0A9, 0x85B4, 0xF0A4, 0x85B5, 0xF0AA, 0x85B6, 0xF0B4,	0x85B7, 0xF0B8, 0x85B8, 0xF0B7, 0x85B9, 0xC2CA, 0x85BA, 0xC2C9,
+	0x85BD, 0xF0AB, 0x85BE, 0xF0B9, 0x85BF, 0xF0AE, 0x85C0, 0xF0A6,	0x85C2, 0xF0A8, 0x85C3, 0xF0A7, 0x85C4, 0xF0AD, 0x85C5, 0xF0B2,
+	0x85C6, 0xF0A5, 0x85C7, 0xF0AC, 0x85C8, 0xF0B1, 0x85C9, 0xC2C7,	0x85CB, 0xF0AF, 0x85CD, 0xC2C5, 0x85CE, 0xF0B0, 0x85CF, 0xC2C3,
+	0x85D0, 0xC2C6, 0x85D1, 0xF2D5, 0x85D2, 0xF0B5, 0x85D5, 0xC3C2,	0x85D7, 0xF2CD, 0x85D8, 0xF2D1, 0x85D9, 0xF2C9, 0x85DA, 0xF2CC,
+	0x85DC, 0xF2D4, 0x85DD, 0xC3C0, 0x85DE, 0xF2D9, 0x85DF, 0xF2D2,	0x85E1, 0xF2CA, 0x85E2, 0xF2DA, 0x85E3, 0xF2D3, 0x85E4, 0xC3C3,
+	0x85E5, 0xC3C4, 0x85E6, 0xF2D7, 0x85E8, 0xF2CB, 0x85E9, 0xC3BF,	0x85EA, 0xC3C1, 0x85EB, 0xF2C6, 0x85EC, 0xF2CE, 0x85ED, 0xF2C8,
+	0x85EF, 0xF2D8, 0x85F0, 0xF2D6, 0x85F1, 0xF2C7, 0x85F2, 0xF2CF,	0x85F6, 0xF4BE, 0x85F7, 0xC3C5, 0x85F8, 0xF2D0, 0x85F9, 0xC4A7,
+	0x85FA, 0xC4A9, 0x85FB, 0xC4A6, 0x85FD, 0xF4C3, 0x85FE, 0xF4BB,	0x85FF, 0xF4B9, 0x8600, 0xF4BD, 0x8601, 0xF4BA, 0x8604, 0xF4BF,
+	0x8605, 0xF4C1, 0x8606, 0xC4AA, 0x8607, 0xC4AC, 0x8609, 0xF4C0,	0x860A, 0xC4AD, 0x860B, 0xC4AB, 0x860C, 0xF4C2, 0x8611, 0xC4A8,
+	0x8617, 0xC4F4, 0x8618, 0xF5F1, 0x8619, 0xF5F7, 0x861A, 0xC4F6,	0x861B, 0xF4BC, 0x861C, 0xF5F6, 0x861E, 0xF5FD, 0x861F, 0xF5F4,
+	0x8620, 0xF5FB, 0x8621, 0xF5FA, 0x8622, 0xF4B8, 0x8623, 0xF5F5,	0x8624, 0xF0B6, 0x8625, 0xF5FE, 0x8626, 0xF5F3, 0x8627, 0xF5F8,
+	0x8629, 0xF5FC, 0x862A, 0xF5F2, 0x862C, 0xF74A, 0x862D, 0xC4F5,	0x862E, 0xF5F9, 0x8631, 0xF7F4, 0x8632, 0xF74B, 0x8633, 0xF749,
+	0x8634, 0xF747, 0x8635, 0xF748, 0x8636, 0xF74C, 0x8638, 0xC5D9,	0x8639, 0xF7F2, 0x863A, 0xF7F0, 0x863B, 0xF7F5, 0x863C, 0xF7F3,
+	0x863E, 0xF7F6, 0x863F, 0xC5DA, 0x8640, 0xF7F1, 0x8643, 0xF8BC,	0x8646, 0xF945, 0x8647, 0xF946, 0x8648, 0xF947, 0x864B, 0xF9C7,
+	0x864C, 0xF9BD, 0x864D, 0xCA4F, 0x864E, 0xAAEA, 0x8650, 0xAD68,	0x8652, 0xD3B8, 0x8653, 0xD3B7, 0x8654, 0xB040, 0x8655, 0xB342,
+	0x8656, 0xD77C, 0x8659, 0xD77B, 0x865B, 0xB5EA, 0x865C, 0xB8B8,	0x865E, 0xB8B7, 0x865F, 0xB8B9, 0x8661, 0xE3D4, 0x8662, 0xE77E,
+	0x8663, 0xEB58, 0x8664, 0xEB5A, 0x8665, 0xEB59, 0x8667, 0xC1AB,	0x8668, 0xEE57, 0x8669, 0xF0BA, 0x866A, 0xF9A5, 0x866B, 0xA6E4,
+	0x866D, 0xCDC9, 0x866E, 0xCDCA, 0x866F, 0xCDC8, 0x8670, 0xCDC7,	0x8671, 0xAAEB, 0x8673, 0xD0A9, 0x8674, 0xD0A7, 0x8677, 0xD0A6,
+	0x8679, 0xAD69, 0x867A, 0xAD6B, 0x867B, 0xAD6A, 0x867C, 0xD0A8,	0x8685, 0xD3C4, 0x8686, 0xD3C1, 0x8687, 0xD3BF, 0x868A, 0xB041,
+	0x868B, 0xD3C2, 0x868C, 0xB046, 0x868D, 0xD3BC, 0x868E, 0xD3CB,	0x8690, 0xD3CD, 0x8691, 0xD3BD, 0x8693, 0xB043, 0x8694, 0xD3CE,
+	0x8695, 0xD3C9, 0x8696, 0xD3BB, 0x8697, 0xD3C0, 0x8698, 0xD3CA,	0x8699, 0xD3C6, 0x869A, 0xD3C3, 0x869C, 0xB048, 0x869D, 0xD3CC,
+	0x869E, 0xD3BE, 0x86A1, 0xD3C7, 0x86A2, 0xD3B9, 0x86A3, 0xB047,	0x86A4, 0xB044, 0x86A5, 0xD3C5, 0x86A7, 0xD3C8, 0x86A8, 0xD3BA,
+	0x86A9, 0xB045, 0x86AA, 0xB042, 0x86AF, 0xB34C, 0x86B0, 0xD7A5,	0x86B1, 0xB34B, 0x86B3, 0xD7A8, 0x86B4, 0xD7AB, 0x86B5, 0xB348,
+	0x86B6, 0xB346, 0x86B7, 0xD77E, 0x86B8, 0xD7A9, 0x86B9, 0xD7A7,	0x86BA, 0xD7A4, 0x86BB, 0xD7AC, 0x86BC, 0xD7AD, 0x86BD, 0xD7AF,
+	0x86BE, 0xD7B0, 0x86BF, 0xD77D, 0x86C0, 0xB345, 0x86C1, 0xD7A2,	0x86C2, 0xD7A1, 0x86C3, 0xD7AE, 0x86C4, 0xB347, 0x86C5, 0xD7A3,
+	0x86C6, 0xB349, 0x86C7, 0xB344, 0x86C8, 0xD7A6, 0x86C9, 0xB34D,	0x86CB, 0xB34A, 0x86CC, 0xD7AA, 0x86D0, 0xB5F1, 0x86D1, 0xDBBF,
+	0x86D3, 0xDBB4, 0x86D4, 0xB5EE, 0x86D6, 0xDFE7, 0x86D7, 0xDBBD,	0x86D8, 0xDBB1, 0x86D9, 0xB5EC, 0x86DA, 0xDBB6, 0x86DB, 0xB5EF,
+	0x86DC, 0xDBBA, 0x86DD, 0xDBB8, 0x86DE, 0xB5F2, 0x86DF, 0xB5EB,	0x86E2, 0xDBB2, 0x86E3, 0xDBB5, 0x86E4, 0xB5F0, 0x86E6, 0xDBB3,
+	0x86E8, 0xDBBE, 0x86E9, 0xDBBC, 0x86EA, 0xDBB7, 0x86EB, 0xDBB9,	0x86EC, 0xDBBB, 0x86ED, 0xB5ED, 0x86F5, 0xDFE8, 0x86F6, 0xDFEE,
+	0x86F7, 0xDFE4, 0x86F8, 0xDFEA, 0x86F9, 0xB8BA, 0x86FA, 0xDFE6,	0x86FB, 0xB8C0, 0x86FE, 0xB8BF, 0x8700, 0xB8BE, 0x8701, 0xDFED,
+	0x8702, 0xB8C1, 0x8703, 0xB8C2, 0x8704, 0xDFE3, 0x8705, 0xDFF0,	0x8706, 0xB8C3, 0x8707, 0xB8BD, 0x8708, 0xB8BC, 0x8709, 0xDFEC,
+	0x870A, 0xB8C4, 0x870B, 0xDFE2, 0x870C, 0xDFE5, 0x870D, 0xDFEF,	0x870E, 0xDFEB, 0x8711, 0xE3F4, 0x8712, 0xE3E9, 0x8713, 0xB8BB,
+	0x8718, 0xBB6A, 0x8719, 0xE3DD, 0x871A, 0xE3F2, 0x871B, 0xE3DE,	0x871C, 0xBB65, 0x871E, 0xE3DB, 0x8720, 0xE3E4, 0x8721, 0xE3DC,
+	0x8722, 0xBB67, 0x8723, 0xE3D6, 0x8724, 0xE3F1, 0x8725, 0xBB68,	0x8726, 0xE3EE, 0x8727, 0xE3EF, 0x8728, 0xE3D7, 0x8729, 0xBB6D,
+	0x872A, 0xE3E6, 0x872C, 0xE3E0, 0x872D, 0xE3E7, 0x872E, 0xE3DA,	0x8730, 0xE3F3, 0x8731, 0xE3EB, 0x8732, 0xE3E5, 0x8733, 0xE3D5,
+	0x8734, 0xBB69, 0x8735, 0xE3EC, 0x8737, 0xBB6C, 0x8738, 0xE3F0,	0x873A, 0xE3EA, 0x873B, 0xBB66, 0x873C, 0xE3E8, 0x873E, 0xE3E2,
+	0x873F, 0xBB64, 0x8740, 0xE3D9, 0x8741, 0xE3E1, 0x8742, 0xE3ED,	0x8743, 0xE3DF, 0x8746, 0xE3E3, 0x874C, 0xBDC1, 0x874D, 0xDFE9,
+	0x874E, 0xE7B2, 0x874F, 0xE7BB, 0x8750, 0xE7B1, 0x8751, 0xE7AD,	0x8752, 0xE7AA, 0x8753, 0xBDC2, 0x8754, 0xE7A8, 0x8755, 0xBB6B,
+	0x8756, 0xE7A1, 0x8757, 0xBDC0, 0x8758, 0xE7A7, 0x8759, 0xBDBF,	0x875A, 0xE7AC, 0x875B, 0xE7A9, 0x875C, 0xE7B9, 0x875D, 0xE7B4,
+	0x875E, 0xE7AE, 0x875F, 0xE7B3, 0x8760, 0xBDBB, 0x8761, 0xE7AB,	0x8762, 0xE7BE, 0x8763, 0xE7A2, 0x8764, 0xE7A3, 0x8765, 0xE7BA,
+	0x8766, 0xBDBC, 0x8767, 0xE7BF, 0x8768, 0xBDBE, 0x8769, 0xE7C0,	0x876A, 0xE7B0, 0x876B, 0xE3D8, 0x876C, 0xE7B6, 0x876D, 0xE7AF,
+	0x876E, 0xE7B8, 0x876F, 0xE7B5, 0x8773, 0xE7A6, 0x8774, 0xBDB9,	0x8775, 0xE7BD, 0x8776, 0xBDBA, 0x8777, 0xE7A4, 0x8778, 0xBDBD,
+	0x8779, 0xEB64, 0x877A, 0xE7B7, 0x877B, 0xE7BC, 0x8781, 0xEB61,	0x8782, 0xBDB8, 0x8783, 0xBFC0, 0x8784, 0xEB6B, 0x8785, 0xEB67,
+	0x8787, 0xEB65, 0x8788, 0xEB60, 0x8789, 0xEB6F, 0x878D, 0xBFC4,	0x878F, 0xEB5C, 0x8790, 0xEB68, 0x8791, 0xEB69, 0x8792, 0xEB5F,
+	0x8793, 0xEB5E, 0x8794, 0xEB6C, 0x8796, 0xEB62, 0x8797, 0xEB5D,	0x8798, 0xEB63, 0x879A, 0xEB6E, 0x879B, 0xEB5B, 0x879C, 0xEB6D,
+	0x879D, 0xEB6A, 0x879E, 0xBFC2, 0x879F, 0xBFC1, 0x87A2, 0xBFC3,	0x87A3, 0xEB66, 0x87A4, 0xF0CB, 0x87AA, 0xEE59, 0x87AB, 0xC1B1,
+	0x87AC, 0xEE5D, 0x87AD, 0xEE5A, 0x87AE, 0xEE61, 0x87AF, 0xEE67,	0x87B0, 0xEE5C, 0x87B2, 0xEE70, 0x87B3, 0xC1AE, 0x87B4, 0xEE6A,
+	0x87B5, 0xEE5F, 0x87B6, 0xEE6B, 0x87B7, 0xEE66, 0x87B8, 0xEE6D,	0x87B9, 0xEE5E, 0x87BA, 0xC1B3, 0x87BB, 0xC1B2, 0x87BC, 0xEE60,
+	0x87BD, 0xEE6E, 0x87BE, 0xEE58, 0x87BF, 0xEE6C, 0x87C0, 0xC1AC,	0x87C2, 0xEE64, 0x87C3, 0xEE63, 0x87C4, 0xEE68, 0x87C5, 0xEE5B,
+	0x87C6, 0xC1B0, 0x87C8, 0xC1B4, 0x87C9, 0xEE62, 0x87CA, 0xEE69,	0x87CB, 0xC1B5, 0x87CC, 0xEE65, 0x87D1, 0xC1AD, 0x87D2, 0xC1AF,
+	0x87D3, 0xF0C7, 0x87D4, 0xF0C5, 0x87D7, 0xF0CC, 0x87D8, 0xF0C9,	0x87D9, 0xF0CD, 0x87DB, 0xF0BE, 0x87DC, 0xF0C6, 0x87DD, 0xF0D1,
+	0x87DE, 0xEE6F, 0x87DF, 0xF0C2, 0x87E0, 0xC2CF, 0x87E1, 0xE7A5,	0x87E2, 0xF0BD, 0x87E3, 0xF0CA, 0x87E4, 0xF0C4, 0x87E5, 0xF0C1,
+	0x87E6, 0xF0BC, 0x87E7, 0xF0BB, 0x87E8, 0xF0D0, 0x87EA, 0xF0C0,	0x87EB, 0xF0BF, 0x87EC, 0xC2CD, 0x87ED, 0xF0C8, 0x87EF, 0xC2CC,
+	0x87F2, 0xC2CE, 0x87F3, 0xF0C3, 0x87F4, 0xF0CF, 0x87F6, 0xF2DE,	0x87F7, 0xF2DF, 0x87F9, 0xC3C9, 0x87FA, 0xF2DC, 0x87FB, 0xC3C6,
+	0x87FC, 0xF2E4, 0x87FE, 0xC3CA, 0x87FF, 0xF2E6, 0x8800, 0xF2DB,	0x8801, 0xF0CE, 0x8802, 0xF2E8, 0x8803, 0xF2DD, 0x8805, 0xC3C7,
+	0x8806, 0xF2E3, 0x8808, 0xF2E5, 0x8809, 0xF2E0, 0x880A, 0xF2E7,	0x880B, 0xF2E2, 0x880C, 0xF2E1, 0x880D, 0xC3C8, 0x8810, 0xF4C5,
+	0x8811, 0xF4C6, 0x8813, 0xF4C8, 0x8814, 0xC4AE, 0x8815, 0xC4AF,	0x8816, 0xF4C9, 0x8817, 0xF4C7, 0x8819, 0xF4C4, 0x881B, 0xF642,
+	0x881C, 0xF645, 0x881D, 0xF641, 0x881F, 0xC4FA, 0x8820, 0xF643,	0x8821, 0xC4F9, 0x8822, 0xC4F8, 0x8823, 0xC4F7, 0x8824, 0xF644,
+	0x8825, 0xF751, 0x8826, 0xF74F, 0x8828, 0xF74E, 0x8829, 0xF640,	0x882A, 0xF750, 0x882B, 0xF646, 0x882C, 0xF74D, 0x882E, 0xF7F9,
+	0x882F, 0xF7D7, 0x8830, 0xF7F7, 0x8831, 0xC5DB, 0x8832, 0xF7F8,	0x8833, 0xF7FA, 0x8835, 0xF8BF, 0x8836, 0xC5FA, 0x8837, 0xF8BE,
+	0x8838, 0xF8BD, 0x8839, 0xC5FB, 0x883B, 0xC65A, 0x883C, 0xF96E,	0x883D, 0xF9A7, 0x883E, 0xF9A6, 0x883F, 0xF9A8, 0x8840, 0xA6E5,
+	0x8841, 0xD0AA, 0x8843, 0xD3CF, 0x8844, 0xD3D0, 0x8848, 0xDBC0,	0x884A, 0xF647, 0x884B, 0xF8C0, 0x884C, 0xA6E6, 0x884D, 0xAD6C,
+	0x884E, 0xD0AB, 0x8852, 0xD7B1, 0x8853, 0xB34E, 0x8855, 0xDBC2,	0x8856, 0xDBC1, 0x8857, 0xB5F3, 0x8859, 0xB8C5, 0x885A, 0xE7C1,
+	0x885B, 0xBDC3, 0x885D, 0xBDC4, 0x8861, 0xBFC5, 0x8862, 0xC5FC,	0x8863, 0xA6E7, 0x8867, 0xD0AC, 0x8868, 0xAAED, 0x8869, 0xD0AE,
+	0x886A, 0xD0AD, 0x886B, 0xAD6D, 0x886D, 0xD3D1, 0x886F, 0xD3D8,	0x8870, 0xB049, 0x8871, 0xD3D6, 0x8872, 0xD3D4, 0x8874, 0xD3DB,
+	0x8875, 0xD3D2, 0x8876, 0xD3D3, 0x8877, 0xB04A, 0x8879, 0xB04E,	0x887C, 0xD3DC, 0x887D, 0xB04D, 0x887E, 0xD3DA, 0x887F, 0xD3D7,
+	0x8880, 0xD3D5, 0x8881, 0xB04B, 0x8882, 0xB04C, 0x8883, 0xD3D9,	0x8888, 0xB350, 0x8889, 0xD7B2, 0x888B, 0xB355, 0x888C, 0xD7C2,
+	0x888D, 0xB354, 0x888E, 0xD7C4, 0x8891, 0xD7B8, 0x8892, 0xB352,	0x8893, 0xD7C3, 0x8895, 0xD7B3, 0x8896, 0xB353, 0x8897, 0xD7BF,
+	0x8898, 0xD7BB, 0x8899, 0xD7BD, 0x889A, 0xD7B7, 0x889B, 0xD7BE,	0x889E, 0xB34F, 0x889F, 0xD7BA, 0x88A1, 0xD7B9, 0x88A2, 0xD7B5,
+	0x88A4, 0xD7C0, 0x88A7, 0xD7BC, 0x88A8, 0xD7B4, 0x88AA, 0xD7B6,	0x88AB, 0xB351, 0x88AC, 0xD7C1, 0x88B1, 0xB5F6, 0x88B2, 0xDBCD,
+	0x88B6, 0xDBC9, 0x88B7, 0xDBCB, 0x88B8, 0xDBC6, 0x88B9, 0xDBC5,	0x88BA, 0xDBC3, 0x88BC, 0xDBCA, 0x88BD, 0xDBCC, 0x88BE, 0xDBC8,
+	0x88C0, 0xDBC7, 0x88C1, 0xB5F4, 0x88C2, 0xB5F5, 0x88C9, 0xDBCF,	0x88CA, 0xB8CD, 0x88CB, 0xDFF2, 0x88CC, 0xDFF8, 0x88CD, 0xDFF3,
+	0x88CE, 0xDFF4, 0x88CF, 0xF9D8, 0x88D0, 0xDFF9, 0x88D2, 0xB8CF,	0x88D4, 0xB8C7, 0x88D5, 0xB8CE, 0x88D6, 0xDFF1, 0x88D7, 0xDBC4,
+	0x88D8, 0xB8CA, 0x88D9, 0xB8C8, 0x88DA, 0xDFF7, 0x88DB, 0xDFF6,	0x88DC, 0xB8C9, 0x88DD, 0xB8CB, 0x88DE, 0xDFF5, 0x88DF, 0xB8C6,
+	0x88E1, 0xB8CC, 0x88E7, 0xE3F6, 0x88E8, 0xBB74, 0x88EB, 0xE442,	0x88EC, 0xE441, 0x88EE, 0xE3FB, 0x88EF, 0xBB76, 0x88F0, 0xE440,
+	0x88F1, 0xE3F7, 0x88F2, 0xE3F8, 0x88F3, 0xBB6E, 0x88F4, 0xBB70,	0x88F6, 0xE3FD, 0x88F7, 0xE3F5, 0x88F8, 0xBB72, 0x88F9, 0xBB71,
+	0x88FA, 0xE3F9, 0x88FB, 0xE3FE, 0x88FC, 0xE3FC, 0x88FD, 0xBB73,	0x88FE, 0xE3FA, 0x8901, 0xDBCE, 0x8902, 0xBB6F, 0x8905, 0xE7C2,
+	0x8906, 0xE7C9, 0x8907, 0xBDC6, 0x8909, 0xE7CD, 0x890A, 0xBDCA,	0x890B, 0xE7C5, 0x890C, 0xE7C3, 0x890E, 0xE7CC, 0x8910, 0xBDC5,
+	0x8911, 0xE7CB, 0x8912, 0xBDC7, 0x8913, 0xBDC8, 0x8914, 0xE7C4,	0x8915, 0xBDC9, 0x8916, 0xE7CA, 0x8917, 0xE7C6, 0x8918, 0xE7C7,
+	0x8919, 0xE7C8, 0x891A, 0xBB75, 0x891E, 0xEB70, 0x891F, 0xEB7C,	0x8921, 0xBFCA, 0x8922, 0xEB77, 0x8923, 0xEB79, 0x8925, 0xBFC8,
+	0x8926, 0xEB71, 0x8927, 0xEB75, 0x8929, 0xEB78, 0x892A, 0xBFC6,	0x892B, 0xBFC9, 0x892C, 0xEB7B, 0x892D, 0xEB73, 0x892E, 0xEB74,
+	0x892F, 0xEB7A, 0x8930, 0xEB72, 0x8931, 0xEB76, 0x8932, 0xBFC7,	0x8933, 0xEE72, 0x8935, 0xEE71, 0x8936, 0xC1B7, 0x8937, 0xEE77,
+	0x8938, 0xC1B9, 0x893B, 0xC1B6, 0x893C, 0xEE73, 0x893D, 0xC1BA,	0x893E, 0xEE74, 0x8941, 0xEE75, 0x8942, 0xEE78, 0x8944, 0xC1B8,
+	0x8946, 0xF0D6, 0x8949, 0xF0D9, 0x894B, 0xF0D3, 0x894C, 0xF0D5,	0x894F, 0xF0D4, 0x8950, 0xF0D7, 0x8951, 0xF0D8, 0x8952, 0xEE76,
+	0x8953, 0xF0D2, 0x8956, 0xC3CD, 0x8957, 0xF2EC, 0x8958, 0xF2EF,	0x8959, 0xF2F1, 0x895A, 0xF2EA, 0x895B, 0xF2EB, 0x895C, 0xF2EE,
+	0x895D, 0xF2F0, 0x895E, 0xC3CE, 0x895F, 0xC3CC, 0x8960, 0xC3CB,	0x8961, 0xF2ED, 0x8962, 0xF2E9, 0x8963, 0xF4CA, 0x8964, 0xC4B0,
+	0x8966, 0xF4CB, 0x8969, 0xF649, 0x896A, 0xC4FB, 0x896B, 0xF64B,	0x896C, 0xC4FC, 0x896D, 0xF648, 0x896E, 0xF64A, 0x896F, 0xC5A8,
+	0x8971, 0xF752, 0x8972, 0xC5A7, 0x8973, 0xF7FD, 0x8974, 0xF7FC,	0x8976, 0xF7FB, 0x8979, 0xF948, 0x897A, 0xF949, 0x897B, 0xF94B,
+	0x897C, 0xF94A, 0x897E, 0xCA50, 0x897F, 0xA6E8, 0x8981, 0xAD6E,	0x8982, 0xD7C5, 0x8983, 0xB5F7, 0x8985, 0xDFFA, 0x8986, 0xC2D0,
+	0x8988, 0xF2F2, 0x898B, 0xA8A3, 0x898F, 0xB357, 0x8993, 0xB356,	0x8995, 0xDBD0, 0x8996, 0xB5F8, 0x8997, 0xDBD2, 0x8998, 0xDBD1,
+	0x899B, 0xDFFB, 0x899C, 0xB8D0, 0x899D, 0xE443, 0x899E, 0xE446,	0x899F, 0xE445, 0x89A1, 0xE444, 0x89A2, 0xE7CE, 0x89A3, 0xE7D0,
+	0x89A4, 0xE7CF, 0x89A6, 0xBFCC, 0x89AA, 0xBFCB, 0x89AC, 0xC1BB,	0x89AD, 0xEE79, 0x89AE, 0xEE7B, 0x89AF, 0xEE7A, 0x89B2, 0xC2D1,
+	0x89B6, 0xF2F4, 0x89B7, 0xF2F3, 0x89B9, 0xF4CC, 0x89BA, 0xC4B1,	0x89BD, 0xC4FD, 0x89BE, 0xF754, 0x89BF, 0xF753, 0x89C0, 0xC65B,
+	0x89D2, 0xA8A4, 0x89D3, 0xD0AF, 0x89D4, 0xAD6F, 0x89D5, 0xD7C8,	0x89D6, 0xD7C6, 0x89D9, 0xD7C7, 0x89DA, 0xDBD4, 0x89DB, 0xDBD5,
+	0x89DC, 0xE043, 0x89DD, 0xDBD3, 0x89DF, 0xDFFC, 0x89E0, 0xE041,	0x89E1, 0xE040, 0x89E2, 0xE042, 0x89E3, 0xB8D1, 0x89E4, 0xDFFE,
+	0x89E5, 0xDFFD, 0x89E6, 0xE044, 0x89E8, 0xE449, 0x89E9, 0xE447,	0x89EB, 0xE448, 0x89EC, 0xE7D3, 0x89ED, 0xE7D1, 0x89F0, 0xE7D2,
+	0x89F1, 0xEB7D, 0x89F2, 0xEE7C, 0x89F3, 0xEE7D, 0x89F4, 0xC2D2,	0x89F6, 0xF2F5, 0x89F7, 0xF4CD, 0x89F8, 0xC4B2, 0x89FA, 0xF64C,
+	0x89FB, 0xF755, 0x89FC, 0xC5A9, 0x89FE, 0xF7FE, 0x89FF, 0xF94C,	0x8A00, 0xA8A5, 0x8A02, 0xAD71, 0x8A03, 0xAD72, 0x8A04, 0xD0B0,
+	0x8A07, 0xD0B1, 0x8A08, 0xAD70, 0x8A0A, 0xB054, 0x8A0C, 0xB052,	0x8A0E, 0xB051, 0x8A0F, 0xB058, 0x8A10, 0xB050, 0x8A11, 0xB059,
+	0x8A12, 0xD3DD, 0x8A13, 0xB056, 0x8A15, 0xB053, 0x8A16, 0xB057,	0x8A17, 0xB055, 0x8A18, 0xB04F, 0x8A1B, 0xB35F, 0x8A1D, 0xB359,
+	0x8A1E, 0xD7CC, 0x8A1F, 0xB35E, 0x8A22, 0xB360, 0x8A23, 0xB35A,	0x8A25, 0xB35B, 0x8A27, 0xD7CA, 0x8A2A, 0xB358, 0x8A2C, 0xD7CB,
+	0x8A2D, 0xB35D, 0x8A30, 0xD7C9, 0x8A31, 0xB35C, 0x8A34, 0xB644,	0x8A36, 0xB646, 0x8A39, 0xDBD8, 0x8A3A, 0xB645, 0x8A3B, 0xB5F9,
+	0x8A3C, 0xB5FD, 0x8A3E, 0xB8E4, 0x8A3F, 0xE049, 0x8A40, 0xDBDA,	0x8A41, 0xB5FE, 0x8A44, 0xDBDD, 0x8A45, 0xDBDE, 0x8A46, 0xB643,
+	0x8A48, 0xDBE0, 0x8A4A, 0xDBE2, 0x8A4C, 0xDBE3, 0x8A4D, 0xDBD7,	0x8A4E, 0xDBD6, 0x8A4F, 0xDBE4, 0x8A50, 0xB642, 0x8A51, 0xDBE1,
+	0x8A52, 0xDBDF, 0x8A54, 0xB640, 0x8A55, 0xB5FB, 0x8A56, 0xB647,	0x8A57, 0xDBDB, 0x8A58, 0xDBDC, 0x8A59, 0xDBD9, 0x8A5B, 0xB641,
+	0x8A5E, 0xB5FC, 0x8A60, 0xB5FA, 0x8A61, 0xE048, 0x8A62, 0xB8DF,	0x8A63, 0xB8DA, 0x8A66, 0xB8D5, 0x8A68, 0xB8E5, 0x8A69, 0xB8D6,
+	0x8A6B, 0xB8D2, 0x8A6C, 0xB8E1, 0x8A6D, 0xB8DE, 0x8A6E, 0xB8E0,	0x8A70, 0xB8D7, 0x8A71, 0xB8DC, 0x8A72, 0xB8D3, 0x8A73, 0xB8D4,
+	0x8A74, 0xE050, 0x8A75, 0xE04D, 0x8A76, 0xE045, 0x8A77, 0xE04A,	0x8A79, 0xB8E2, 0x8A7A, 0xE051, 0x8A7B, 0xB8E3, 0x8A7C, 0xB8D9,
+	0x8A7F, 0xE047, 0x8A81, 0xE04F, 0x8A82, 0xE04B, 0x8A83, 0xE04E,	0x8A84, 0xE04C, 0x8A85, 0xB8DD, 0x8A86, 0xE046, 0x8A87, 0xB8D8,
+	0x8A8B, 0xE44C, 0x8A8C, 0xBB78, 0x8A8D, 0xBB7B, 0x8A8F, 0xE44E,	0x8A91, 0xBBA5, 0x8A92, 0xE44D, 0x8A93, 0xBB7D, 0x8A95, 0xBDCF,
+	0x8A96, 0xE44F, 0x8A98, 0xBBA4, 0x8A99, 0xE44B, 0x8A9A, 0xBBA6,	0x8A9E, 0xBB79, 0x8AA0, 0xB8DB, 0x8AA1, 0xBB7C, 0x8AA3, 0xBB7A,
+	0x8AA4, 0xBB7E, 0x8AA5, 0xBBA2, 0x8AA6, 0xBB77, 0x8AA7, 0xBBA7,	0x8AA8, 0xBBA3, 0x8AAA, 0xBBA1, 0x8AAB, 0xE44A, 0x8AB0, 0xBDD6,
+	0x8AB2, 0xBDD2, 0x8AB6, 0xBDD9, 0x8AB8, 0xE7D6, 0x8AB9, 0xBDDA,	0x8ABA, 0xE7E2, 0x8ABB, 0xE7DB, 0x8ABC, 0xBDCB, 0x8ABD, 0xE7E3,
+	0x8ABE, 0xE7DD, 0x8ABF, 0xBDD5, 0x8AC0, 0xE7DE, 0x8AC2, 0xBDD4,	0x8AC3, 0xE7E1, 0x8AC4, 0xBDCE, 0x8AC5, 0xE7DF, 0x8AC6, 0xE7D5,
+	0x8AC7, 0xBDCD, 0x8AC8, 0xEBAA, 0x8AC9, 0xBDD3, 0x8ACB, 0xBDD0,	0x8ACD, 0xBDD8, 0x8ACF, 0xE7D4, 0x8AD1, 0xE7D8, 0x8AD2, 0xBDCC,
+	0x8AD3, 0xE7D7, 0x8AD4, 0xE7D9, 0x8AD5, 0xE7DA, 0x8AD6, 0xBDD7,	0x8AD7, 0xE7DC, 0x8AD8, 0xE7E0, 0x8AD9, 0xE7E4, 0x8ADB, 0xBDDB,
+	0x8ADC, 0xBFD2, 0x8ADD, 0xEBA5, 0x8ADE, 0xEBAB, 0x8ADF, 0xEBA8,	0x8AE0, 0xEB7E, 0x8AE1, 0xEBAC, 0x8AE2, 0xEBA1, 0x8AE4, 0xEBA7,
+	0x8AE6, 0xBFCD, 0x8AE7, 0xBFD3, 0x8AE8, 0xEBAD, 0x8AEB, 0xBFCF,	0x8AED, 0xBFD9, 0x8AEE, 0xBFD4, 0x8AEF, 0xEBAF, 0x8AF0, 0xEBA9,
+	0x8AF1, 0xBFD0, 0x8AF2, 0xEBA2, 0x8AF3, 0xBFDA, 0x8AF4, 0xEBA3,	0x8AF5, 0xEBA4, 0x8AF6, 0xBFDB, 0x8AF7, 0xBFD8, 0x8AF8, 0xBDD1,
+	0x8AFA, 0xBFCE, 0x8AFB, 0xEBB0, 0x8AFC, 0xBFDC, 0x8AFE, 0xBFD5,	0x8AFF, 0xEBAE, 0x8B00, 0xBFD1, 0x8B01, 0xBFD6, 0x8B02, 0xBFD7,
+	0x8B04, 0xC1C3, 0x8B05, 0xEEA4, 0x8B06, 0xEEAD, 0x8B07, 0xEEAA,	0x8B08, 0xEEAC, 0x8B0A, 0xC1C0, 0x8B0B, 0xEEA5, 0x8B0D, 0xEEAB,
+	0x8B0E, 0xC1BC, 0x8B0F, 0xEEA7, 0x8B10, 0xC1C4, 0x8B11, 0xEEA3,	0x8B12, 0xEEA8, 0x8B13, 0xEEAF, 0x8B14, 0xEBA6, 0x8B15, 0xEEA9,
+	0x8B16, 0xEEA2, 0x8B17, 0xC1BD, 0x8B18, 0xEEA1, 0x8B19, 0xC1BE,	0x8B1A, 0xEEB0, 0x8B1B, 0xC1BF, 0x8B1C, 0xEEAE, 0x8B1D, 0xC1C2,
+	0x8B1E, 0xEE7E, 0x8B20, 0xC1C1, 0x8B22, 0xEEA6, 0x8B23, 0xF0DC,	0x8B24, 0xF0EA, 0x8B25, 0xF0E5, 0x8B26, 0xF0E7, 0x8B27, 0xF0DB,
+	0x8B28, 0xC2D3, 0x8B2A, 0xF0DA, 0x8B2B, 0xC2D6, 0x8B2C, 0xC2D5,	0x8B2E, 0xF0E9, 0x8B2F, 0xF0E1, 0x8B30, 0xF0DE, 0x8B31, 0xF0E4,
+	0x8B33, 0xF0DD, 0x8B35, 0xF0DF, 0x8B36, 0xF0E8, 0x8B37, 0xF0E6,	0x8B39, 0xC2D4, 0x8B3A, 0xF0ED, 0x8B3B, 0xF0EB, 0x8B3C, 0xF0E2,
+	0x8B3D, 0xF0EC, 0x8B3E, 0xF0E3, 0x8B40, 0xF2F9, 0x8B41, 0xC3CF,	0x8B42, 0xF341, 0x8B45, 0xF64F, 0x8B46, 0xC3D6, 0x8B47, 0xF0E0,
+	0x8B48, 0xF2F7, 0x8B49, 0xC3D2, 0x8B4A, 0xF2F8, 0x8B4B, 0xF2FD,	0x8B4E, 0xC3D4, 0x8B4F, 0xC3D5, 0x8B50, 0xF2F6, 0x8B51, 0xF340,
+	0x8B52, 0xF342, 0x8B53, 0xF2FA, 0x8B54, 0xF2FC, 0x8B55, 0xF2FE,	0x8B56, 0xF2FB, 0x8B57, 0xF343, 0x8B58, 0xC3D1, 0x8B59, 0xC3D7,
+	0x8B5A, 0xC3D3, 0x8B5C, 0xC3D0, 0x8B5D, 0xF4D0, 0x8B5F, 0xC4B7,	0x8B60, 0xF4CE, 0x8B63, 0xF4D2, 0x8B65, 0xF4D3, 0x8B66, 0xC4B5,
+	0x8B67, 0xF4D4, 0x8B68, 0xF4D1, 0x8B6A, 0xF4CF, 0x8B6B, 0xC4B8,	0x8B6C, 0xC4B4, 0x8B6D, 0xF4D5, 0x8B6F, 0xC4B6, 0x8B70, 0xC4B3,
+	0x8B74, 0xC4FE, 0x8B77, 0xC540, 0x8B78, 0xF64E, 0x8B79, 0xF64D,	0x8B7A, 0xF650, 0x8B7B, 0xF651, 0x8B7D, 0xC541, 0x8B7E, 0xF756,
+	0x8B7F, 0xF75B, 0x8B80, 0xC5AA, 0x8B82, 0xF758, 0x8B84, 0xF757,	0x8B85, 0xF75A, 0x8B86, 0xF759, 0x8B88, 0xF843, 0x8B8A, 0xC5DC,
+	0x8B8B, 0xF842, 0x8B8C, 0xF840, 0x8B8E, 0xF841, 0x8B92, 0xC5FE,	0x8B93, 0xC5FD, 0x8B94, 0xF8C1, 0x8B95, 0xF8C2, 0x8B96, 0xC640,
+	0x8B98, 0xF94D, 0x8B99, 0xF94E, 0x8B9A, 0xC667, 0x8B9C, 0xC66D,	0x8B9E, 0xF9A9, 0x8B9F, 0xF9C8, 0x8C37, 0xA8A6, 0x8C39, 0xD7CD,
+	0x8C3B, 0xD7CE, 0x8C3C, 0xE052, 0x8C3D, 0xE450, 0x8C3E, 0xE7E5,	0x8C3F, 0xC1C6, 0x8C41, 0xC1C5, 0x8C42, 0xF0EE, 0x8C43, 0xF344,
+	0x8C45, 0xF844, 0x8C46, 0xA8A7, 0x8C47, 0xD3DE, 0x8C48, 0xB05A,	0x8C49, 0xB361, 0x8C4A, 0xE054, 0x8C4B, 0xE053, 0x8C4C, 0xBDDC,
+	0x8C4D, 0xE7E6, 0x8C4E, 0xBDDD, 0x8C4F, 0xEEB1, 0x8C50, 0xC2D7,	0x8C54, 0xC676, 0x8C55, 0xA8A8, 0x8C56, 0xCDCB, 0x8C57, 0xD3DF,
+	0x8C5A, 0xB362, 0x8C5C, 0xD7CF, 0x8C5D, 0xD7D0, 0x8C5F, 0xDBE5,	0x8C61, 0xB648, 0x8C62, 0xB8E6, 0x8C64, 0xE056, 0x8C65, 0xE055,
+	0x8C66, 0xE057, 0x8C68, 0xE451, 0x8C69, 0xE452, 0x8C6A, 0xBBA8,	0x8C6B, 0xBFDD, 0x8C6C, 0xBDDE, 0x8C6D, 0xBFDE, 0x8C6F, 0xEEB5,
+	0x8C70, 0xEEB2, 0x8C71, 0xEEB4, 0x8C72, 0xEEB3, 0x8C73, 0xC1C7,	0x8C75, 0xF0EF, 0x8C76, 0xF346, 0x8C77, 0xF345, 0x8C78, 0xCBA4,
+	0x8C79, 0xB05C, 0x8C7A, 0xB05B, 0x8C7B, 0xD3E0, 0x8C7D, 0xD7D1,	0x8C80, 0xDBE7, 0x8C81, 0xDBE6, 0x8C82, 0xB649, 0x8C84, 0xE059,
+	0x8C85, 0xE05A, 0x8C86, 0xE058, 0x8C89, 0xB8E8, 0x8C8A, 0xB8E7,	0x8C8C, 0xBBAA, 0x8C8D, 0xBBA9, 0x8C8F, 0xE7E7, 0x8C90, 0xEBB3,
+	0x8C91, 0xEBB1, 0x8C92, 0xEBB2, 0x8C93, 0xBFDF, 0x8C94, 0xEEB7,	0x8C95, 0xEEB6, 0x8C97, 0xF0F2, 0x8C98, 0xF0F1, 0x8C99, 0xF0F0,
+	0x8C9A, 0xF347, 0x8C9C, 0xF9AA, 0x8C9D, 0xA8A9, 0x8C9E, 0xAD73,	0x8CA0, 0xAD74, 0x8CA1, 0xB05D, 0x8CA2, 0xB05E, 0x8CA3, 0xD3E2,
+	0x8CA4, 0xD3E1, 0x8CA5, 0xD7D2, 0x8CA7, 0xB368, 0x8CA8, 0xB366,	0x8CA9, 0xB363, 0x8CAA, 0xB367, 0x8CAB, 0xB365, 0x8CAC, 0xB364,
+	0x8CAF, 0xB64A, 0x8CB0, 0xDBEA, 0x8CB2, 0xB8ED, 0x8CB3, 0xB64C,	0x8CB4, 0xB651, 0x8CB5, 0xDBEC, 0x8CB6, 0xB653, 0x8CB7, 0xB652,
+	0x8CB8, 0xB655, 0x8CB9, 0xDBEB, 0x8CBA, 0xDBE8, 0x8CBB, 0xB64F,	0x8CBC, 0xB64B, 0x8CBD, 0xB64D, 0x8CBE, 0xDBE9, 0x8CBF, 0xB654,
+	0x8CC0, 0xB650, 0x8CC1, 0xB64E, 0x8CC2, 0xB8EF, 0x8CC3, 0xB8EE,	0x8CC4, 0xB8EC, 0x8CC5, 0xB8F0, 0x8CC7, 0xB8EA, 0x8CC8, 0xB8EB,
+	0x8CCA, 0xB8E9, 0x8CCC, 0xE05B, 0x8CCF, 0xE454, 0x8CD1, 0xBBAC,	0x8CD2, 0xBBAD, 0x8CD3, 0xBBAB, 0x8CD5, 0xE453, 0x8CD7, 0xE455,
+	0x8CD9, 0xE7EA, 0x8CDA, 0xE7EC, 0x8CDC, 0xBDE7, 0x8CDD, 0xE7ED,	0x8CDE, 0xBDE0, 0x8CDF, 0xE7E9, 0x8CE0, 0xBDDF, 0x8CE1, 0xBDE9,
+	0x8CE2, 0xBDE5, 0x8CE3, 0xBDE6, 0x8CE4, 0xBDE2, 0x8CE5, 0xE7E8,	0x8CE6, 0xBDE1, 0x8CE7, 0xE7EE, 0x8CE8, 0xE7EB, 0x8CEA, 0xBDE8,
+	0x8CEC, 0xBDE3, 0x8CED, 0xBDE4, 0x8CEE, 0xEBB5, 0x8CF0, 0xEBB7,	0x8CF1, 0xEBB6, 0x8CF3, 0xEBB8, 0x8CF4, 0xBFE0, 0x8CF5, 0xEBB4,
+	0x8CF8, 0xC1CB, 0x8CF9, 0xEEB8, 0x8CFA, 0xC1C8, 0x8CFB, 0xC1CC,	0x8CFC, 0xC1CA, 0x8CFD, 0xC1C9, 0x8CFE, 0xF0F3, 0x8D00, 0xF0F6,
+	0x8D02, 0xF0F5, 0x8D04, 0xF0F4, 0x8D05, 0xC2D8, 0x8D06, 0xF348,	0x8D07, 0xF349, 0x8D08, 0xC3D8, 0x8D09, 0xF34A, 0x8D0A, 0xC3D9,
+	0x8D0D, 0xC4BA, 0x8D0F, 0xC4B9, 0x8D10, 0xF652, 0x8D13, 0xC542,	0x8D14, 0xF653, 0x8D15, 0xF75C, 0x8D16, 0xC5AB, 0x8D17, 0xC5AC,
+	0x8D19, 0xF845, 0x8D1B, 0xC642, 0x8D64, 0xA8AA, 0x8D66, 0xB36A,	0x8D67, 0xB369, 0x8D68, 0xE05C, 0x8D69, 0xE05D, 0x8D6B, 0xBBAE,
+	0x8D6C, 0xEBB9, 0x8D6D, 0xBDEA, 0x8D6E, 0xEBBA, 0x8D6F, 0xEEB9,	0x8D70, 0xA8AB, 0x8D72, 0xD0B2, 0x8D73, 0xAD76, 0x8D74, 0xAD75,
+	0x8D76, 0xD3E3, 0x8D77, 0xB05F, 0x8D78, 0xD3E4, 0x8D79, 0xD7D5,	0x8D7B, 0xD7D4, 0x8D7D, 0xD7D3, 0x8D80, 0xDBEE, 0x8D81, 0xB658,
+	0x8D84, 0xDBED, 0x8D85, 0xB657, 0x8D89, 0xDBEF, 0x8D8A, 0xB656,	0x8D8C, 0xE05F, 0x8D8D, 0xE062, 0x8D8E, 0xE060, 0x8D8F, 0xE061,
+	0x8D90, 0xE065, 0x8D91, 0xE05E, 0x8D92, 0xE066, 0x8D93, 0xE063,	0x8D94, 0xE064, 0x8D95, 0xBBB0, 0x8D96, 0xE456, 0x8D99, 0xBBAF,
+	0x8D9B, 0xE7F2, 0x8D9C, 0xE7F0, 0x8D9F, 0xBDEB, 0x8DA0, 0xE7EF,	0x8DA1, 0xE7F1, 0x8DA3, 0xBDEC, 0x8DA5, 0xEBBB, 0x8DA7, 0xEBBC,
+	0x8DA8, 0xC1CD, 0x8DAA, 0xF34C, 0x8DAB, 0xF34E, 0x8DAC, 0xF34B,	0x8DAD, 0xF34D, 0x8DAE, 0xF4D6, 0x8DAF, 0xF654, 0x8DB2, 0xF96F,
+	0x8DB3, 0xA8AC, 0x8DB4, 0xAD77, 0x8DB5, 0xD3E5, 0x8DB6, 0xD3E7,	0x8DB7, 0xD3E6, 0x8DB9, 0xD7D8, 0x8DBA, 0xB36C, 0x8DBC, 0xD7D6,
+	0x8DBE, 0xB36B, 0x8DBF, 0xD7D9, 0x8DC1, 0xD7DA, 0x8DC2, 0xD7D7,	0x8DC5, 0xDBFB, 0x8DC6, 0xB660, 0x8DC7, 0xDBF3, 0x8DC8, 0xDBF9,
+	0x8DCB, 0xB65B, 0x8DCC, 0xB65E, 0x8DCD, 0xDBF2, 0x8DCE, 0xB659,	0x8DCF, 0xDBF6, 0x8DD0, 0xE06C, 0x8DD1, 0xB65D, 0x8DD3, 0xDBF1,
+	0x8DD5, 0xDBF7, 0x8DD6, 0xDBF4, 0x8DD7, 0xDBFA, 0x8DD8, 0xDBF0,	0x8DD9, 0xDBF8, 0x8DDA, 0xB65C, 0x8DDB, 0xB65F, 0x8DDC, 0xDBF5,
+	0x8DDD, 0xB65A, 0x8DDF, 0xB8F2, 0x8DE0, 0xE068, 0x8DE1, 0xB8F1,	0x8DE2, 0xE06F, 0x8DE3, 0xE06E, 0x8DE4, 0xB8F8, 0x8DE6, 0xB8F9,
+	0x8DE7, 0xE070, 0x8DE8, 0xB8F3, 0x8DE9, 0xE06D, 0x8DEA, 0xB8F7,	0x8DEB, 0xE072, 0x8DEC, 0xE069, 0x8DEE, 0xE06B, 0x8DEF, 0xB8F4,
+	0x8DF0, 0xE067, 0x8DF1, 0xE06A, 0x8DF2, 0xE071, 0x8DF3, 0xB8F5,	0x8DF4, 0xE073, 0x8DFA, 0xB8F6, 0x8DFC, 0xBBB1, 0x8DFD, 0xE45B,
+	0x8DFE, 0xE461, 0x8DFF, 0xE459, 0x8E00, 0xE462, 0x8E02, 0xE458,	0x8E03, 0xE45D, 0x8E04, 0xE463, 0x8E05, 0xE460, 0x8E06, 0xE45F,
+	0x8E07, 0xE45E, 0x8E09, 0xE457, 0x8E0A, 0xE45C, 0x8E0D, 0xE45A,	0x8E0F, 0xBDF1, 0x8E10, 0xBDEE, 0x8E11, 0xE7FB, 0x8E12, 0xE841,
+	0x8E13, 0xE843, 0x8E14, 0xE840, 0x8E15, 0xE7F8, 0x8E16, 0xE7FA,	0x8E17, 0xE845, 0x8E18, 0xE842, 0x8E19, 0xE7FC, 0x8E1A, 0xE846,
+	0x8E1B, 0xE7F9, 0x8E1C, 0xE844, 0x8E1D, 0xBDEF, 0x8E1E, 0xBDF5,	0x8E1F, 0xBDF3, 0x8E20, 0xE7F3, 0x8E21, 0xBDF4, 0x8E22, 0xBDF0,
+	0x8E23, 0xE7F4, 0x8E24, 0xE7F6, 0x8E25, 0xE7F5, 0x8E26, 0xE7FD,	0x8E27, 0xE7FE, 0x8E29, 0xBDF2, 0x8E2B, 0xBDED, 0x8E2E, 0xE7F7,
+	0x8E30, 0xEBC6, 0x8E31, 0xBFE2, 0x8E33, 0xEBBD, 0x8E34, 0xBFE3,	0x8E35, 0xBFE6, 0x8E36, 0xEBC2, 0x8E38, 0xEBBF, 0x8E39, 0xBFE5,
+	0x8E3C, 0xEBC3, 0x8E3D, 0xEBC4, 0x8E3E, 0xEBBE, 0x8E3F, 0xEBC7,	0x8E40, 0xEBC0, 0x8E41, 0xEBC5, 0x8E42, 0xBFE4, 0x8E44, 0xBFE1,
+	0x8E45, 0xEBC1, 0x8E47, 0xEEBF, 0x8E48, 0xC1D0, 0x8E49, 0xC1CE,	0x8E4A, 0xC1D1, 0x8E4B, 0xC1CF, 0x8E4C, 0xEEBE, 0x8E4D, 0xEEBB,
+	0x8E4E, 0xEEBA, 0x8E50, 0xEEBD, 0x8E53, 0xEEBC, 0x8E54, 0xF145,	0x8E55, 0xC2DE, 0x8E56, 0xF0FB, 0x8E57, 0xF0FA, 0x8E59, 0xC2D9,
+	0x8E5A, 0xF141, 0x8E5B, 0xF140, 0x8E5C, 0xF0F7, 0x8E5D, 0xF143,	0x8E5E, 0xF0FC, 0x8E5F, 0xC2DD, 0x8E60, 0xF0F9, 0x8E61, 0xF142,
+	0x8E62, 0xF0F8, 0x8E63, 0xC2DA, 0x8E64, 0xC2DC, 0x8E65, 0xF0FD,	0x8E66, 0xC2DB, 0x8E67, 0xF0FE, 0x8E69, 0xF144, 0x8E6A, 0xF352,
+	0x8E6C, 0xC3DE, 0x8E6D, 0xF34F, 0x8E6F, 0xF353, 0x8E72, 0xC3DB,	0x8E73, 0xF351, 0x8E74, 0xC3E0, 0x8E76, 0xC3DD, 0x8E78, 0xF350,
+	0x8E7A, 0xC3DF, 0x8E7B, 0xF354, 0x8E7C, 0xC3DA, 0x8E81, 0xC4BC,	0x8E82, 0xC4BE, 0x8E84, 0xF4D9, 0x8E85, 0xC4BD, 0x8E86, 0xF4D7,
+	0x8E87, 0xC3DC, 0x8E88, 0xF4D8, 0x8E89, 0xC4BB, 0x8E8A, 0xC543,	0x8E8B, 0xC545, 0x8E8C, 0xF656, 0x8E8D, 0xC544, 0x8E8E, 0xF655,
+	0x8E90, 0xF761, 0x8E91, 0xC5AD, 0x8E92, 0xF760, 0x8E93, 0xC5AE,	0x8E94, 0xF75E, 0x8E95, 0xF75D, 0x8E96, 0xF762, 0x8E97, 0xF763,
+	0x8E98, 0xF846, 0x8E9A, 0xF75F, 0x8E9D, 0xF8C6, 0x8E9E, 0xF8C3,	0x8E9F, 0xF8C4, 0x8EA0, 0xF8C5, 0x8EA1, 0xC65C, 0x8EA3, 0xF951,
+	0x8EA4, 0xF950, 0x8EA5, 0xF94F, 0x8EA6, 0xF970, 0x8EA8, 0xF9BE,	0x8EA9, 0xF9AB, 0x8EAA, 0xC66E, 0x8EAB, 0xA8AD, 0x8EAC, 0xB060,
+	0x8EB2, 0xB8FA, 0x8EBA, 0xBDF6, 0x8EBD, 0xEBC8, 0x8EC0, 0xC2DF,	0x8EC2, 0xF355, 0x8EC9, 0xF9AC, 0x8ECA, 0xA8AE, 0x8ECB, 0xAAEE,
+	0x8ECC, 0xAD79, 0x8ECD, 0xAD78, 0x8ECF, 0xB063, 0x8ED1, 0xD3E8,	0x8ED2, 0xB061, 0x8ED3, 0xD3E9, 0x8ED4, 0xB062, 0x8ED7, 0xD7DF,
+	0x8ED8, 0xD7DB, 0x8EDB, 0xB36D, 0x8EDC, 0xD7DE, 0x8EDD, 0xD7DD,	0x8EDE, 0xD7DC, 0x8EDF, 0xB36E, 0x8EE0, 0xD7E0, 0x8EE1, 0xD7E1,
+	0x8EE5, 0xDC43, 0x8EE6, 0xDC41, 0x8EE7, 0xDC45, 0x8EE8, 0xDC46,	0x8EE9, 0xDC4C, 0x8EEB, 0xDC48, 0x8EEC, 0xDC4A, 0x8EEE, 0xDC42,
+	0x8EEF, 0xDBFC, 0x8EF1, 0xDC49, 0x8EF4, 0xDC4B, 0x8EF5, 0xDC44,	0x8EF6, 0xDC47, 0x8EF7, 0xDBFD, 0x8EF8, 0xB662, 0x8EF9, 0xDC40,
+	0x8EFA, 0xDBFE, 0x8EFB, 0xB661, 0x8EFC, 0xB663, 0x8EFE, 0xB8FD,	0x8EFF, 0xE075, 0x8F00, 0xE077, 0x8F01, 0xE076, 0x8F02, 0xE07B,
+	0x8F03, 0xB8FB, 0x8F05, 0xE078, 0x8F06, 0xE074, 0x8F07, 0xE079,	0x8F08, 0xE07A, 0x8F09, 0xB8FC, 0x8F0A, 0xB8FE, 0x8F0B, 0xE07C,
+	0x8F0D, 0xE467, 0x8F0E, 0xE466, 0x8F10, 0xE464, 0x8F11, 0xE465,	0x8F12, 0xBBB3, 0x8F13, 0xBBB5, 0x8F14, 0xBBB2, 0x8F15, 0xBBB4,
+	0x8F16, 0xE84D, 0x8F17, 0xE84E, 0x8F18, 0xE849, 0x8F1A, 0xE84A,	0x8F1B, 0xBDF8, 0x8F1C, 0xBDFD, 0x8F1D, 0xBDF7, 0x8F1E, 0xBDFE,
+	0x8F1F, 0xBDF9, 0x8F20, 0xE84B, 0x8F23, 0xE84C, 0x8F24, 0xE848,	0x8F25, 0xBE40, 0x8F26, 0xBDFB, 0x8F29, 0xBDFA, 0x8F2A, 0xBDFC,
+	0x8F2C, 0xE847, 0x8F2E, 0xEBCA, 0x8F2F, 0xBFE8, 0x8F32, 0xEBCC,	0x8F33, 0xBFEA, 0x8F34, 0xEBCF, 0x8F35, 0xEBCB, 0x8F36, 0xEBC9,
+	0x8F37, 0xEBCE, 0x8F38, 0xBFE9, 0x8F39, 0xEBCD, 0x8F3B, 0xBFE7,	0x8F3E, 0xC1D3, 0x8F3F, 0xC1D6, 0x8F40, 0xEEC1, 0x8F42, 0xC1D4,
+	0x8F43, 0xEEC0, 0x8F44, 0xC1D2, 0x8F45, 0xC1D5, 0x8F46, 0xF146,	0x8F47, 0xF147, 0x8F48, 0xF148, 0x8F49, 0xC2E0, 0x8F4B, 0xF149,
+	0x8F4D, 0xC2E1, 0x8F4E, 0xC3E2, 0x8F4F, 0xF358, 0x8F50, 0xF359,	0x8F51, 0xF357, 0x8F52, 0xF356, 0x8F53, 0xF35A, 0x8F54, 0xC3E1,
+	0x8F55, 0xF4DD, 0x8F56, 0xF4DB, 0x8F57, 0xF4DC, 0x8F58, 0xF4DE,	0x8F59, 0xF4DA, 0x8F5A, 0xF4DF, 0x8F5B, 0xF658, 0x8F5D, 0xF659,
+	0x8F5E, 0xF657, 0x8F5F, 0xC546, 0x8F60, 0xF764, 0x8F61, 0xC5AF,	0x8F62, 0xF765, 0x8F63, 0xF848, 0x8F64, 0xF847, 0x8F9B, 0xA8AF,
+	0x8F9C, 0xB664, 0x8F9F, 0xB940, 0x8FA3, 0xBBB6, 0x8FA6, 0xBFEC,	0x8FA8, 0xBFEB, 0x8FAD, 0xC3E3, 0x8FAE, 0xC47C, 0x8FAF, 0xC547,
+	0x8FB0, 0xA8B0, 0x8FB1, 0xB064, 0x8FB2, 0xB941, 0x8FB4, 0xF35B,	0x8FBF, 0xCBA6, 0x8FC2, 0xA8B1, 0x8FC4, 0xA8B4, 0x8FC5, 0xA8B3,
+	0x8FC6, 0xA8B2, 0x8FC9, 0xCBA5, 0x8FCB, 0xCDCD, 0x8FCD, 0xCDCF,	0x8FCE, 0xAAEF, 0x8FD1, 0xAAF1, 0x8FD2, 0xCDCC, 0x8FD3, 0xCDCE,
+	0x8FD4, 0xAAF0, 0x8FD5, 0xCDD1, 0x8FD6, 0xCDD0, 0x8FD7, 0xCDD2,	0x8FE0, 0xD0B6, 0x8FE1, 0xD0B4, 0x8FE2, 0xAD7C, 0x8FE3, 0xD0B3,
+	0x8FE4, 0xADA3, 0x8FE5, 0xAD7E, 0x8FE6, 0xAD7B, 0x8FE8, 0xADA4,	0x8FEA, 0xAD7D, 0x8FEB, 0xADA2, 0x8FED, 0xADA1, 0x8FEE, 0xD0B5,
+	0x8FF0, 0xAD7A, 0x8FF4, 0xB06A, 0x8FF5, 0xD3EB, 0x8FF6, 0xD3F1,	0x8FF7, 0xB067, 0x8FF8, 0xB06E, 0x8FFA, 0xB069, 0x8FFB, 0xD3EE,
+	0x8FFC, 0xD3F0, 0x8FFD, 0xB06C, 0x8FFE, 0xD3EA, 0x8FFF, 0xD3ED,	0x9000, 0xB068, 0x9001, 0xB065, 0x9002, 0xD3EC, 0x9003, 0xB06B,
+	0x9004, 0xD3EF, 0x9005, 0xB06D, 0x9006, 0xB066, 0x900B, 0xD7E3,	0x900C, 0xD7E6, 0x900D, 0xB370, 0x900F, 0xB37A, 0x9010, 0xB376,
+	0x9011, 0xD7E4, 0x9014, 0xB37E, 0x9015, 0xB377, 0x9016, 0xB37C,	0x9017, 0xB372, 0x9019, 0xB36F, 0x901A, 0xB371, 0x901B, 0xB37D,
+	0x901C, 0xD7E5, 0x901D, 0xB375, 0x901E, 0xB378, 0x901F, 0xB374,	0x9020, 0xB379, 0x9021, 0xD7E7, 0x9022, 0xB37B, 0x9023, 0xB373,
+	0x9024, 0xD7E2, 0x902D, 0xDC4D, 0x902E, 0xB665, 0x902F, 0xDC4F,	0x9031, 0xB667, 0x9032, 0xB669, 0x9034, 0xDC4E, 0x9035, 0xB666,
+	0x9036, 0xB66A, 0x9038, 0xB668, 0x903C, 0xB947, 0x903D, 0xE0A3,	0x903E, 0xB94F, 0x903F, 0xE07E, 0x9041, 0xB950, 0x9042, 0xB945,
+	0x9044, 0xE0A1, 0x9047, 0xB94A, 0x9049, 0xE0A2, 0x904A, 0xB943,	0x904B, 0xB942, 0x904D, 0xB94D, 0x904E, 0xB94C, 0x904F, 0xB94B,
+	0x9050, 0xB949, 0x9051, 0xB94E, 0x9052, 0xE07D, 0x9053, 0xB944,	0x9054, 0xB946, 0x9055, 0xB948, 0x9058, 0xBBB8, 0x9059, 0xBBBB,
+	0x905B, 0xBBBF, 0x905C, 0xBBB9, 0x905D, 0xBBBE, 0x905E, 0xBBBC,	0x9060, 0xBBB7, 0x9062, 0xBBBD, 0x9063, 0xBBBA, 0x9067, 0xE852,
+	0x9068, 0xBE43, 0x9069, 0xBE41, 0x906B, 0xE853, 0x906D, 0xBE44,	0x906E, 0xBE42, 0x906F, 0xE851, 0x9070, 0xE850, 0x9072, 0xBFF0,
+	0x9073, 0xE84F, 0x9074, 0xBFEE, 0x9075, 0xBFED, 0x9076, 0xEBD0,	0x9077, 0xBE45, 0x9078, 0xBFEF, 0x9079, 0xEBD1, 0x907A, 0xBFF2,
+	0x907B, 0xEBD2, 0x907C, 0xBFF1, 0x907D, 0xC1D8, 0x907E, 0xEEC3,	0x907F, 0xC1D7, 0x9080, 0xC1DC, 0x9081, 0xC1DA, 0x9082, 0xC1DB,
+	0x9083, 0xC2E3, 0x9084, 0xC1D9, 0x9085, 0xEEC2, 0x9086, 0xEBD3,	0x9087, 0xC2E2, 0x9088, 0xC2E4, 0x908A, 0xC3E4, 0x908B, 0xC3E5,
+	0x908D, 0xF4E0, 0x908F, 0xC5DE, 0x9090, 0xC5DD, 0x9091, 0xA8B6,	0x9094, 0xCA55, 0x9095, 0xB06F, 0x9097, 0xCA52, 0x9098, 0xCA53,
+	0x9099, 0xCA51, 0x909B, 0xCA54, 0x909E, 0xCBAA, 0x909F, 0xCBA7,	0x90A0, 0xCBAC, 0x90A1, 0xCBA8, 0x90A2, 0xA8B7, 0x90A3, 0xA8BA,
+	0x90A5, 0xCBA9, 0x90A6, 0xA8B9, 0x90A7, 0xCBAB, 0x90AA, 0xA8B8,	0x90AF, 0xCDD5, 0x90B0, 0xCDD7, 0x90B1, 0xAAF4, 0x90B2, 0xCDD3,
+	0x90B3, 0xCDD6, 0x90B4, 0xCDD4, 0x90B5, 0xAAF2, 0x90B6, 0xAAF5,	0x90B8, 0xAAF3, 0x90BD, 0xD0B8, 0x90BE, 0xD0BC, 0x90BF, 0xD0B9,
+	0x90C1, 0xADA7, 0x90C3, 0xADA8, 0x90C5, 0xD0BB, 0x90C7, 0xD0BD,	0x90C8, 0xD0BF, 0x90CA, 0xADA5, 0x90CB, 0xD0BE, 0x90CE, 0xADA6,
+	0x90D4, 0xD7EE, 0x90D5, 0xD0BA, 0x90D6, 0xD3F2, 0x90D7, 0xD3FB,	0x90D8, 0xD3F9, 0x90D9, 0xD3F4, 0x90DA, 0xD3F5, 0x90DB, 0xD3FA,
+	0x90DC, 0xD3FC, 0x90DD, 0xB071, 0x90DF, 0xD3F7, 0x90E0, 0xD3F3,	0x90E1, 0xB070, 0x90E2, 0xB072, 0x90E3, 0xD3F6, 0x90E4, 0xD3FD,
+	0x90E5, 0xD3F8, 0x90E8, 0xB3A1, 0x90E9, 0xD7F1, 0x90EA, 0xD7E9,	0x90EB, 0xD7EF, 0x90EC, 0xD7F0, 0x90ED, 0xB3A2, 0x90EF, 0xD7E8,
+	0x90F0, 0xD7EA, 0x90F1, 0xD0B7, 0x90F2, 0xD7EC, 0x90F3, 0xD7ED,	0x90F4, 0xD7EB, 0x90F5, 0xB66C, 0x90F9, 0xDC56, 0x90FA, 0xEBD4,
+	0x90FB, 0xDC57, 0x90FC, 0xDC54, 0x90FD, 0xB3A3, 0x90FE, 0xB66E,	0x90FF, 0xDC53, 0x9100, 0xDC59, 0x9101, 0xDC58, 0x9102, 0xB66B,
+	0x9103, 0xDC5C, 0x9104, 0xDC52, 0x9105, 0xDC5B, 0x9106, 0xDC50,	0x9107, 0xDC5A, 0x9108, 0xDC55, 0x9109, 0xB66D, 0x910B, 0xE0AA,
+	0x910D, 0xE0A5, 0x910E, 0xE0AB, 0x910F, 0xE0A6, 0x9110, 0xE0A4,	0x9111, 0xE0A7, 0x9112, 0xB951, 0x9114, 0xE0A9, 0x9116, 0xE0A8,
+	0x9117, 0xB952, 0x9118, 0xBBC1, 0x9119, 0xBBC0, 0x911A, 0xE46E,	0x911B, 0xE471, 0x911C, 0xE469, 0x911D, 0xE46D, 0x911E, 0xBBC2,
+	0x911F, 0xE46C, 0x9120, 0xE46A, 0x9121, 0xE470, 0x9122, 0xE46B,	0x9123, 0xE468, 0x9124, 0xE46F, 0x9126, 0xE859, 0x9127, 0xBE48,
+	0x9128, 0xF14A, 0x9129, 0xE856, 0x912A, 0xE857, 0x912B, 0xE855,	0x912C, 0xDC51, 0x912D, 0xBE47, 0x912E, 0xE85A, 0x912F, 0xE854,
+	0x9130, 0xBE46, 0x9131, 0xBE49, 0x9132, 0xE858, 0x9133, 0xEBD5,	0x9134, 0xBFF3, 0x9135, 0xEBD6, 0x9136, 0xEBD7, 0x9138, 0xEEC4,
+	0x9139, 0xC1DD, 0x913A, 0xF14B, 0x913B, 0xF14C, 0x913E, 0xF14D,	0x913F, 0xF35D, 0x9140, 0xF35C, 0x9141, 0xF4E2, 0x9143, 0xF4E1,
+	0x9144, 0xF65B, 0x9145, 0xF65C, 0x9146, 0xF65A, 0x9147, 0xF766,	0x9148, 0xC5B0, 0x9149, 0xA8BB, 0x914A, 0xADAA, 0x914B, 0xADA9,
+	0x914C, 0xB075, 0x914D, 0xB074, 0x914E, 0xD440, 0x914F, 0xD441,	0x9150, 0xD3FE, 0x9152, 0xB073, 0x9153, 0xD7F5, 0x9155, 0xD7F6,
+	0x9156, 0xD7F2, 0x9157, 0xB3A4, 0x9158, 0xD7F3, 0x915A, 0xD7F4,	0x915F, 0xDC5F, 0x9160, 0xDC61, 0x9161, 0xDC5D, 0x9162, 0xDC60,
+	0x9163, 0xB66F, 0x9164, 0xDC5E, 0x9165, 0xB670, 0x9168, 0xDD73,	0x9169, 0xB955, 0x916A, 0xB954, 0x916C, 0xB953, 0x916E, 0xE0AC,
+	0x916F, 0xE0AD, 0x9172, 0xE473, 0x9173, 0xE475, 0x9174, 0xBBC6,	0x9175, 0xBBC3, 0x9177, 0xBBC5, 0x9178, 0xBBC4, 0x9179, 0xE474,
+	0x917A, 0xE472, 0x9180, 0xE861, 0x9181, 0xE85E, 0x9182, 0xE85F,	0x9183, 0xBE4D, 0x9184, 0xE860, 0x9185, 0xE85B, 0x9186, 0xE85C,
+	0x9187, 0xBE4A, 0x9189, 0xBE4B, 0x918A, 0xE85D, 0x918B, 0xBE4C,	0x918D, 0xEBDB, 0x918F, 0xEBDC, 0x9190, 0xEBD9, 0x9191, 0xEBDA,
+	0x9192, 0xBFF4, 0x9193, 0xEBD8, 0x9199, 0xEEC8, 0x919A, 0xEEC5,	0x919B, 0xEEC7, 0x919C, 0xC1E0, 0x919D, 0xEECB, 0x919E, 0xC1DF,
+	0x919F, 0xEEC9, 0x91A0, 0xEECC, 0x91A1, 0xEECA, 0x91A2, 0xEEC6,	0x91A3, 0xC1DE, 0x91A5, 0xF14F, 0x91A7, 0xF150, 0x91A8, 0xF14E,
+	0x91AA, 0xF152, 0x91AB, 0xC2E5, 0x91AC, 0xC2E6, 0x91AD, 0xF35F,	0x91AE, 0xC3E7, 0x91AF, 0xF151, 0x91B0, 0xF35E, 0x91B1, 0xC3E6,
+	0x91B2, 0xF4E5, 0x91B3, 0xF4E6, 0x91B4, 0xC4BF, 0x91B5, 0xF4E4,	0x91B7, 0xF4E3, 0x91B9, 0xF65D, 0x91BA, 0xC548, 0x91BC, 0xF849,
+	0x91BD, 0xF8C8, 0x91BE, 0xF8C7, 0x91C0, 0xC643, 0x91C1, 0xC65D,	0x91C2, 0xF8C9, 0x91C3, 0xF971, 0x91C5, 0xC66F, 0x91C6, 0xA8BC,
+	0x91C7, 0xAAF6, 0x91C9, 0xB956, 0x91CB, 0xC4C0, 0x91CC, 0xA8BD,	0x91CD, 0xADAB, 0x91CE, 0xB3A5, 0x91CF, 0xB671, 0x91D0, 0xC2E7,
+	0x91D1, 0xAAF7, 0x91D3, 0xD0C1, 0x91D4, 0xD0C0, 0x91D5, 0xD442,	0x91D7, 0xB078, 0x91D8, 0xB076, 0x91D9, 0xB07A, 0x91DA, 0xD444,
+	0x91DC, 0xB079, 0x91DD, 0xB077, 0x91E2, 0xD443, 0x91E3, 0xB3A8,	0x91E4, 0xD7FC, 0x91E6, 0xB3A7, 0x91E7, 0xB3A9, 0x91E8, 0xD842,
+	0x91E9, 0xB3AB, 0x91EA, 0xD7FE, 0x91EB, 0xD840, 0x91EC, 0xD7F7,	0x91ED, 0xB3AA, 0x91EE, 0xD843, 0x91F1, 0xD7F9, 0x91F3, 0xD7FA,
+	0x91F4, 0xD7F8, 0x91F5, 0xB3A6, 0x91F7, 0xD841, 0x91F8, 0xD7FB,	0x91F9, 0xD7FD, 0x91FD, 0xDC6D, 0x91FF, 0xDC6C, 0x9200, 0xDC6A,
+	0x9201, 0xDC62, 0x9202, 0xDC71, 0x9203, 0xDC65, 0x9204, 0xDC6F,	0x9205, 0xDC76, 0x9206, 0xDC6E, 0x9207, 0xB679, 0x9209, 0xB675,
+	0x920A, 0xDC63, 0x920C, 0xDC69, 0x920D, 0xB677, 0x920F, 0xDC68,	0x9210, 0xB678, 0x9211, 0xB67A, 0x9212, 0xDC6B, 0x9214, 0xB672,
+	0x9215, 0xB673, 0x9216, 0xDC77, 0x9217, 0xDC75, 0x9219, 0xDC74,	0x921A, 0xDC66, 0x921C, 0xDC72, 0x921E, 0xB676, 0x9223, 0xB674,
+	0x9224, 0xDC73, 0x9225, 0xDC64, 0x9226, 0xDC67, 0x9227, 0xDC70,	0x922D, 0xE4BA, 0x922E, 0xE0B7, 0x9230, 0xE0B0, 0x9231, 0xE0C3,
+	0x9232, 0xE0CC, 0x9233, 0xE0B3, 0x9234, 0xB961, 0x9236, 0xE0C0,	0x9237, 0xB957, 0x9238, 0xB959, 0x9239, 0xB965, 0x923A, 0xE0B1,
+	0x923D, 0xB95A, 0x923E, 0xB95C, 0x923F, 0xB966, 0x9240, 0xB95B,	0x9245, 0xB964, 0x9246, 0xE0B9, 0x9248, 0xE0AE, 0x9249, 0xB962,
+	0x924A, 0xE0B8, 0x924B, 0xB95E, 0x924C, 0xE0CA, 0x924D, 0xB963,	0x924E, 0xE0C8, 0x924F, 0xE0BC, 0x9250, 0xE0C6, 0x9251, 0xB960,
+	0x9252, 0xE0AF, 0x9253, 0xE0C9, 0x9254, 0xE0C4, 0x9256, 0xE0CB,	0x9257, 0xB958, 0x925A, 0xB967, 0x925B, 0xB95D, 0x925E, 0xE0B5,
+	0x9260, 0xE0BD, 0x9261, 0xE0C1, 0x9263, 0xE0C5, 0x9264, 0xB95F,	0x9265, 0xE0B4, 0x9266, 0xE0B2, 0x9267, 0xE0BE, 0x926C, 0xE0BB,
+	0x926D, 0xE0BA, 0x926F, 0xE0BF, 0x9270, 0xE0C2, 0x9272, 0xE0C7,	0x9276, 0xE478, 0x9278, 0xBBC7, 0x9279, 0xE4A4, 0x927A, 0xE47A,
+	0x927B, 0xBBCC, 0x927C, 0xBBD0, 0x927D, 0xE4AD, 0x927E, 0xE4B5,	0x927F, 0xE4A6, 0x9280, 0xBBC8, 0x9282, 0xE4AA, 0x9283, 0xE0B6,
+	0x9285, 0xBBC9, 0x9286, 0xE4B1, 0x9287, 0xE4B6, 0x9288, 0xE4AE,	0x928A, 0xE4B0, 0x928B, 0xE4B9, 0x928C, 0xE4B2, 0x928D, 0xE47E,
+	0x928E, 0xE4A9, 0x9291, 0xBBD1, 0x9293, 0xBBCD, 0x9294, 0xE47C,	0x9295, 0xE4AB, 0x9296, 0xBBCB, 0x9297, 0xE4A5, 0x9298, 0xBBCA,
+	0x9299, 0xE4B3, 0x929A, 0xE4A2, 0x929B, 0xE479, 0x929C, 0xBBCE,	0x929D, 0xE4B8, 0x92A0, 0xE47B, 0x92A1, 0xE4AF, 0x92A2, 0xE4AC,
+	0x92A3, 0xE4A7, 0x92A4, 0xE477, 0x92A5, 0xE476, 0x92A6, 0xE4A1,	0x92A7, 0xE4B4, 0x92A8, 0xBBCF, 0x92A9, 0xE4B7, 0x92AA, 0xE47D,
+	0x92AB, 0xE4A3, 0x92AC, 0xBE52, 0x92B2, 0xBE5A, 0x92B3, 0xBE55,	0x92B4, 0xE8A4, 0x92B5, 0xE8A1, 0x92B6, 0xE867, 0x92B7, 0xBE50,
+	0x92B9, 0xF9D7, 0x92BB, 0xBE4F, 0x92BC, 0xBE56, 0x92C0, 0xE865,	0x92C1, 0xBE54, 0x92C2, 0xE871, 0x92C3, 0xE863, 0x92C4, 0xE864,
+	0x92C5, 0xBE4E, 0x92C6, 0xE8A3, 0x92C7, 0xBE58, 0x92C8, 0xE874,	0x92C9, 0xE879, 0x92CA, 0xE873, 0x92CB, 0xEBEE, 0x92CC, 0xE86F,
+	0x92CD, 0xE877, 0x92CE, 0xE875, 0x92CF, 0xE868, 0x92D0, 0xE862,	0x92D1, 0xE87D, 0x92D2, 0xBE57, 0x92D3, 0xE87E, 0x92D5, 0xE878,
+	0x92D7, 0xE86D, 0x92D8, 0xE86B, 0x92D9, 0xE866, 0x92DD, 0xE86E,	0x92DE, 0xE87B, 0x92DF, 0xE86A, 0x92E0, 0xE87A, 0x92E1, 0xE8A2,
+	0x92E4, 0xBE53, 0x92E6, 0xE876, 0x92E7, 0xE87C, 0x92E8, 0xE872,	0x92E9, 0xE86C, 0x92EA, 0xBE51, 0x92EE, 0xE4A8, 0x92EF, 0xE870,
+	0x92F0, 0xBE59, 0x92F1, 0xE869, 0x92F7, 0xEBF4, 0x92F8, 0xBFF7,	0x92F9, 0xEBF3, 0x92FA, 0xEBF0, 0x92FB, 0xEC44, 0x92FC, 0xBFFB,
+	0x92FE, 0xEC41, 0x92FF, 0xEBF8, 0x9300, 0xEC43, 0x9301, 0xEBE9,	0x9302, 0xEBF6, 0x9304, 0xBFFD, 0x9306, 0xEBE1, 0x9308, 0xEBDF,
+	0x9309, 0xEC42, 0x930B, 0xEC40, 0x930C, 0xEBFE, 0x930D, 0xEBED,	0x930E, 0xEBEC, 0x930F, 0xEBE2, 0x9310, 0xC040, 0x9312, 0xEBE8,
+	0x9313, 0xEBF2, 0x9314, 0xEBFD, 0x9315, 0xC043, 0x9316, 0xEC45,	0x9318, 0xC1E8, 0x9319, 0xC045, 0x931A, 0xBFFE, 0x931B, 0xEBE6,
+	0x931D, 0xEBEF, 0x931E, 0xEBDE, 0x931F, 0xEBE0, 0x9320, 0xBFF5,	0x9321, 0xC042, 0x9322, 0xBFFA, 0x9323, 0xEBE7, 0x9324, 0xEBF7,
+	0x9325, 0xEBF1, 0x9326, 0xC041, 0x9327, 0xEBDD, 0x9328, 0xC1E3,	0x9329, 0xEBF9, 0x932A, 0xEBFC, 0x932B, 0xBFFC, 0x932D, 0xEBEB,
+	0x932E, 0xC044, 0x932F, 0xBFF9, 0x9333, 0xBFF8, 0x9334, 0xEBF5,	0x9335, 0xEBFB, 0x9336, 0xBFF6, 0x9338, 0xEBE4, 0x9339, 0xEBFA,
+	0x933C, 0xEBE5, 0x9346, 0xEBEA, 0x9347, 0xEED2, 0x9349, 0xEED7,	0x934A, 0xC1E5, 0x934B, 0xC1E7, 0x934C, 0xEEDD, 0x934D, 0xC1E1,
+	0x934E, 0xEEEC, 0x934F, 0xEEE3, 0x9350, 0xEED8, 0x9351, 0xEED9,	0x9352, 0xEEE2, 0x9354, 0xC1EE, 0x9355, 0xEEE1, 0x9356, 0xEED1,
+	0x9357, 0xEEE0, 0x9358, 0xEED4, 0x9359, 0xEEED, 0x935A, 0xC1ED,	0x935B, 0xC1EB, 0x935C, 0xEED5, 0x935E, 0xEEE8, 0x9360, 0xEEDA,
+	0x9361, 0xEEE7, 0x9363, 0xEEE9, 0x9364, 0xEED0, 0x9365, 0xC1E6,	0x9367, 0xEEEA, 0x936A, 0xEEDE, 0x936C, 0xC1EA, 0x936D, 0xEEDB,
+	0x9370, 0xC1EC, 0x9371, 0xEEE4, 0x9375, 0xC1E4, 0x9376, 0xEED6,	0x9377, 0xEEE5, 0x9379, 0xEEDF, 0x937A, 0xEBE3, 0x937B, 0xEEE6,
+	0x937C, 0xEED3, 0x937E, 0xC1E9, 0x9380, 0xEEEB, 0x9382, 0xC1E2,	0x9383, 0xEECE, 0x9388, 0xF160, 0x9389, 0xF159, 0x938A, 0xC2E9,
+	0x938C, 0xF154, 0x938D, 0xF163, 0x938E, 0xF15B, 0x938F, 0xEEDC,	0x9391, 0xF165, 0x9392, 0xF155, 0x9394, 0xC2E8, 0x9395, 0xF15F,
+	0x9396, 0xC2EA, 0x9397, 0xC2F2, 0x9398, 0xC2F0, 0x9399, 0xF161,	0x939A, 0xC2F1, 0x939B, 0xF157, 0x939D, 0xF158, 0x939E, 0xF15D,
+	0x939F, 0xF162, 0x93A1, 0xEECD, 0x93A2, 0xC2EB, 0x93A3, 0xF16A,	0x93A4, 0xF167, 0x93A5, 0xF16B, 0x93A6, 0xF15E, 0x93A7, 0xF15A,
+	0x93A8, 0xF168, 0x93A9, 0xF36A, 0x93AA, 0xF15C, 0x93AC, 0xC2EE,	0x93AE, 0xC2ED, 0x93AF, 0xEECF, 0x93B0, 0xC2EF, 0x93B1, 0xF164,
+	0x93B2, 0xF166, 0x93B3, 0xC2EC, 0x93B4, 0xF169, 0x93B5, 0xF153,	0x93B7, 0xF156, 0x93C0, 0xF373, 0x93C2, 0xF363, 0x93C3, 0xC3EB,
+	0x93C4, 0xF371, 0x93C7, 0xF361, 0x93C8, 0xC3EC, 0x93CA, 0xF36C,	0x93CC, 0xF368, 0x93CD, 0xC3F1, 0x93CE, 0xF372, 0x93CF, 0xF362,
+	0x93D0, 0xF365, 0x93D1, 0xC3E9, 0x93D2, 0xF374, 0x93D4, 0xF36D,	0x93D5, 0xF370, 0x93D6, 0xC3EF, 0x93D7, 0xC3F4, 0x93D8, 0xC3F2,
+	0x93D9, 0xF369, 0x93DA, 0xF364, 0x93DC, 0xC3ED, 0x93DD, 0xC3EE,	0x93DE, 0xF360, 0x93DF, 0xC3EA, 0x93E1, 0xC3E8, 0x93E2, 0xC3F0,
+	0x93E3, 0xF36F, 0x93E4, 0xC3F3, 0x93E6, 0xF36B, 0x93E7, 0xF375,	0x93E8, 0xC3F5, 0x93EC, 0xF367, 0x93EE, 0xF36E, 0x93F5, 0xF4F3,
+	0x93F6, 0xF542, 0x93F7, 0xF4F5, 0x93F8, 0xF4FC, 0x93F9, 0xF366,	0x93FA, 0xF4FA, 0x93FB, 0xF4E9, 0x93FC, 0xF540, 0x93FD, 0xC4C3,
+	0x93FE, 0xF4ED, 0x93FF, 0xF4FE, 0x9400, 0xF4F4, 0x9403, 0xC4C2,	0x9406, 0xF544, 0x9407, 0xF4F6, 0x9409, 0xF4FB, 0x940A, 0xF4FD,
+	0x940B, 0xF4E7, 0x940C, 0xF541, 0x940D, 0xF4F2, 0x940E, 0xF4F7,	0x940F, 0xF4EB, 0x9410, 0xF4EF, 0x9411, 0xF543, 0x9412, 0xF4F9,
+	0x9413, 0xF4E8, 0x9414, 0xF4EC, 0x9415, 0xF4EE, 0x9416, 0xF4F8,	0x9418, 0xC4C1, 0x9419, 0xF4F1, 0x9420, 0xF4EA, 0x9428, 0xF4F0,
+	0x9429, 0xF661, 0x942A, 0xF666, 0x942B, 0xC54F, 0x942C, 0xF668,	0x942E, 0xC549, 0x9430, 0xF664, 0x9431, 0xF66A, 0x9432, 0xC54E,
+	0x9433, 0xC54A, 0x9435, 0xC54B, 0x9436, 0xF660, 0x9437, 0xF667,	0x9438, 0xC54D, 0x9439, 0xF665, 0x943A, 0xC54C, 0x943B, 0xF65F,
+	0x943C, 0xF663, 0x943D, 0xF662, 0x943F, 0xF65E, 0x9440, 0xF669,	0x9444, 0xC5B1, 0x9445, 0xF76D, 0x9446, 0xF770, 0x9447, 0xF76C,
+	0x9448, 0xF76E, 0x9449, 0xF76F, 0x944A, 0xF769, 0x944B, 0xF76A,	0x944C, 0xF767, 0x944F, 0xF76B, 0x9450, 0xF768, 0x9451, 0xC5B2,
+	0x9452, 0xC5B3, 0x9455, 0xF84B, 0x9457, 0xF84D, 0x945D, 0xF84C,	0x945E, 0xF84E, 0x9460, 0xC5E0, 0x9462, 0xF84A, 0x9463, 0xC5DF,
+	0x9464, 0xC5E1, 0x9468, 0xF8CB, 0x9469, 0xF8CC, 0x946A, 0xC644,	0x946B, 0xF8CA, 0x946D, 0xF953, 0x946E, 0xF952, 0x946F, 0xF954,
+	0x9470, 0xC65F, 0x9471, 0xF955, 0x9472, 0xC65E, 0x9473, 0xF956,	0x9474, 0xF972, 0x9475, 0xF975, 0x9476, 0xF974, 0x9477, 0xC668,
+	0x9478, 0xF973, 0x947C, 0xC672, 0x947D, 0xC670, 0x947E, 0xC671,	0x947F, 0xC677, 0x9480, 0xF9C0, 0x9481, 0xF9C1, 0x9482, 0xF9BF,
+	0x9483, 0xF9C9, 0x9577, 0xAAF8, 0x957A, 0xD844, 0x957B, 0xDC78,	0x957C, 0xE8A5, 0x957D, 0xF376, 0x9580, 0xAAF9, 0x9582, 0xADAC,
+	0x9583, 0xB07B, 0x9586, 0xD845, 0x9588, 0xD846, 0x9589, 0xB3AC,	0x958B, 0xB67D, 0x958C, 0xDC7A, 0x958D, 0xDC79, 0x958E, 0xB6A3,
+	0x958F, 0xB67C, 0x9590, 0xDC7B, 0x9591, 0xB67E, 0x9592, 0xB6A2,	0x9593, 0xB6A1, 0x9594, 0xB67B, 0x9598, 0xB968, 0x959B, 0xE0D0,
+	0x959C, 0xE0CE, 0x959E, 0xE0CF, 0x959F, 0xE0CD, 0x95A1, 0xBBD2,	0x95A3, 0xBBD5, 0x95A4, 0xBBD7, 0x95A5, 0xBBD6, 0x95A8, 0xBBD3,
+	0x95A9, 0xBBD4, 0x95AB, 0xE8A7, 0x95AC, 0xE8A6, 0x95AD, 0xBE5B,	0x95AE, 0xE8A8, 0x95B0, 0xE8A9, 0x95B1, 0xBE5C, 0x95B5, 0xEC4D,
+	0x95B6, 0xEC4B, 0x95B7, 0xEEF3, 0x95B9, 0xEC49, 0x95BA, 0xEC4A,	0x95BB, 0xC046, 0x95BC, 0xEC46, 0x95BD, 0xEC4E, 0x95BE, 0xEC48,
+	0x95BF, 0xEC4C, 0x95C0, 0xEEEF, 0x95C3, 0xEEF1, 0x95C5, 0xEEF2,	0x95C6, 0xC1F3, 0x95C7, 0xEEEE, 0x95C8, 0xC1F2, 0x95C9, 0xEEF0,
+	0x95CA, 0xC1EF, 0x95CB, 0xC1F0, 0x95CC, 0xC1F1, 0x95CD, 0xEC47,	0x95D0, 0xC2F5, 0x95D1, 0xF16E, 0x95D2, 0xF16C, 0x95D3, 0xF16D,
+	0x95D4, 0xC2F3, 0x95D5, 0xC2F6, 0x95D6, 0xC2F4, 0x95DA, 0xF377,	0x95DB, 0xF378, 0x95DC, 0xC3F6, 0x95DE, 0xF545, 0x95DF, 0xF547,
+	0x95E0, 0xF546, 0x95E1, 0xC4C4, 0x95E2, 0xC550, 0x95E3, 0xF66D,	0x95E4, 0xF66C, 0x95E5, 0xF66B, 0x961C, 0xAAFA, 0x961E, 0xC9AA,
+	0x9620, 0xCA58, 0x9621, 0xA6E9, 0x9622, 0xCA56, 0x9623, 0xCA59,	0x9624, 0xCA57, 0x9628, 0xCBAE, 0x962A, 0xA8C1, 0x962C, 0xA8C2,
+	0x962D, 0xCBB0, 0x962E, 0xA8BF, 0x962F, 0xCBAF, 0x9630, 0xCBAD,	0x9631, 0xA8C0, 0x9632, 0xA8BE, 0x9639, 0xCDD8, 0x963A, 0xCDDB,
+	0x963B, 0xAAFD, 0x963C, 0xCDDA, 0x963D, 0xCDD9, 0x963F, 0xAAFC,	0x9640, 0xAAFB, 0x9642, 0xAB40, 0x9643, 0xCDDC, 0x9644, 0xAAFE,
+	0x964A, 0xD0C6, 0x964B, 0xADAE, 0x964C, 0xADAF, 0x964D, 0xADB0,	0x964E, 0xD0C7, 0x964F, 0xD0C3, 0x9650, 0xADAD, 0x9651, 0xD0C4,
+	0x9653, 0xD0C5, 0x9654, 0xD0C2, 0x9658, 0xB0A4, 0x965B, 0xB0A1,	0x965C, 0xD445, 0x965D, 0xB0A2, 0x965E, 0xB0A5, 0x965F, 0xD446,
+	0x9661, 0xB07E, 0x9662, 0xB07C, 0x9663, 0xB07D, 0x9664, 0xB0A3,	0x966A, 0xB3AD, 0x966B, 0xD849, 0x966C, 0xB3B5, 0x966D, 0xD848,
+	0x966F, 0xD84B, 0x9670, 0xB3B1, 0x9671, 0xD84A, 0x9672, 0xB6AB,	0x9673, 0xB3AF, 0x9674, 0xB3B2, 0x9675, 0xB3AE, 0x9676, 0xB3B3,
+	0x9677, 0xB3B4, 0x9678, 0xB3B0, 0x967C, 0xD847, 0x967D, 0xB6A7,	0x967E, 0xDC7D, 0x9680, 0xDCA3, 0x9683, 0xDCA2, 0x9684, 0xB6AC,
+	0x9685, 0xB6A8, 0x9686, 0xB6A9, 0x9687, 0xDC7C, 0x9688, 0xDC7E,	0x9689, 0xDCA1, 0x968A, 0xB6A4, 0x968B, 0xB6A6, 0x968D, 0xB6AA,
+	0x968E, 0xB6A5, 0x9691, 0xE0D3, 0x9692, 0xE0D1, 0x9693, 0xE0D2,	0x9694, 0xB96A, 0x9695, 0xB96B, 0x9697, 0xE0D4, 0x9698, 0xB969,
+	0x9699, 0xBBD8, 0x969B, 0xBBDA, 0x969C, 0xBBD9, 0x969E, 0xE4BB,	0x96A1, 0xE4BC, 0x96A2, 0xE8AB, 0x96A4, 0xE8AA, 0x96A7, 0xC047,
+	0x96A8, 0xC048, 0x96A9, 0xEC4F, 0x96AA, 0xC049, 0x96AC, 0xEEF6,	0x96AE, 0xEEF4, 0x96B0, 0xEEF5, 0x96B1, 0xC1F4, 0x96B3, 0xF16F,
+	0x96B4, 0xC3F7, 0x96B8, 0xC1F5, 0x96B9, 0xAB41, 0x96BB, 0xB0A6,	0x96BC, 0xD447, 0x96BF, 0xD84C, 0x96C0, 0xB3B6, 0x96C1, 0xB6AD,
+	0x96C2, 0xDCA4, 0x96C3, 0xDCA6, 0x96C4, 0xB6AF, 0x96C5, 0xB6AE,	0x96C6, 0xB6B0, 0x96C7, 0xB6B1, 0x96C8, 0xDCA5, 0x96C9, 0xB96E,
+	0x96CA, 0xB96F, 0x96CB, 0xB96D, 0x96CC, 0xBBDB, 0x96CD, 0xB96C,	0x96CE, 0xE0D5, 0x96D2, 0xBBDC, 0x96D3, 0xE8AC, 0x96D4, 0xEC50,
+	0x96D5, 0xC04A, 0x96D6, 0xC1F6, 0x96D7, 0xF170, 0x96D8, 0xF174,	0x96D9, 0xC2F9, 0x96DA, 0xF171, 0x96DB, 0xC2FA, 0x96DC, 0xC2F8,
+	0x96DD, 0xF175, 0x96DE, 0xC2FB, 0x96DF, 0xF173, 0x96E1, 0xF379,	0x96E2, 0xC2F7, 0x96E3, 0xC3F8, 0x96E5, 0xF8CD, 0x96E8, 0xAB42,
+	0x96E9, 0xB3B8, 0x96EA, 0xB3B7, 0x96EF, 0xB6B2, 0x96F0, 0xDCA8,	0x96F1, 0xDCA7, 0x96F2, 0xB6B3, 0x96F5, 0xE0D9, 0x96F6, 0xB973,
+	0x96F7, 0xB970, 0x96F8, 0xE0D8, 0x96F9, 0xB972, 0x96FA, 0xE0D6,	0x96FB, 0xB971, 0x96FD, 0xE0D7, 0x96FF, 0xE4BD, 0x9700, 0xBBDD,
+	0x9702, 0xE8AF, 0x9704, 0xBE5D, 0x9705, 0xE8AD, 0x9706, 0xBE5E,	0x9707, 0xBE5F, 0x9708, 0xE8AE, 0x9709, 0xBE60, 0x970B, 0xEC51,
+	0x970D, 0xC04E, 0x970E, 0xC04B, 0x970F, 0xC050, 0x9710, 0xEC53,	0x9711, 0xC04C, 0x9712, 0xEC52, 0x9713, 0xC04F, 0x9716, 0xC04D,
+	0x9718, 0xEEF9, 0x9719, 0xEEFB, 0x971C, 0xC1F7, 0x971D, 0xEEFA,	0x971E, 0xC1F8, 0x971F, 0xEEF8, 0x9720, 0xEEF7, 0x9722, 0xF177,
+	0x9723, 0xF176, 0x9724, 0xC2FC, 0x9725, 0xF178, 0x9726, 0xF37E,	0x9727, 0xC3FA, 0x9728, 0xF37D, 0x9729, 0xF37A, 0x972A, 0xC3F9,
+	0x972B, 0xF37B, 0x972C, 0xF37C, 0x972E, 0xF548, 0x972F, 0xF549,	0x9730, 0xC4C5, 0x9732, 0xC553, 0x9735, 0xF66E, 0x9738, 0xC551,
+	0x9739, 0xC552, 0x973A, 0xF66F, 0x973D, 0xC5B4, 0x973E, 0xC5B5,	0x973F, 0xF771, 0x9742, 0xC645, 0x9743, 0xF8CF, 0x9744, 0xC647,
+	0x9746, 0xF8CE, 0x9747, 0xF8D0, 0x9748, 0xC646, 0x9749, 0xF957,	0x974B, 0xF9AD, 0x9752, 0xAB43, 0x9756, 0xB974, 0x9758, 0xE4BE,
+	0x975A, 0xE8B0, 0x975B, 0xC051, 0x975C, 0xC052, 0x975E, 0xAB44,	0x9760, 0xBE61, 0x9761, 0xC3FB, 0x9762, 0xADB1, 0x9766, 0xC053,
+	0x9768, 0xC5E2, 0x9769, 0xADB2, 0x976A, 0xD84D, 0x976C, 0xDCA9,	0x976E, 0xDCAB, 0x9770, 0xDCAA, 0x9772, 0xE0DD, 0x9773, 0xE0DA,
+	0x9774, 0xB975, 0x9776, 0xB976, 0x9777, 0xE0DB, 0x9778, 0xE0DC,	0x977A, 0xE4C0, 0x977B, 0xE4C5, 0x977C, 0xBBDE, 0x977D, 0xE4BF,
+	0x977E, 0xE4C1, 0x977F, 0xE4C8, 0x9780, 0xE4C3, 0x9781, 0xE4C7,	0x9782, 0xE4C4, 0x9783, 0xE4C2, 0x9784, 0xE4C6, 0x9785, 0xBBDF,
+	0x9788, 0xE8B3, 0x978A, 0xE8B1, 0x978B, 0xBE63, 0x978D, 0xBE62,	0x978E, 0xE8B2, 0x978F, 0xBE64, 0x9794, 0xEC56, 0x9797, 0xEC55,
+	0x9798, 0xC054, 0x9799, 0xEC54, 0x979A, 0xEEFC, 0x979C, 0xEEFE,	0x979D, 0xEF41, 0x979E, 0xEF40, 0x97A0, 0xC1F9, 0x97A1, 0xEEFD,
+	0x97A2, 0xF1A1, 0x97A3, 0xC2FD, 0x97A4, 0xF17D, 0x97A5, 0xF1A2,	0x97A6, 0xC2FE, 0x97A8, 0xF17B, 0x97AA, 0xF17E, 0x97AB, 0xF17C,
+	0x97AC, 0xF179, 0x97AD, 0xC340, 0x97AE, 0xF17A, 0x97B3, 0xF3A1,	0x97B6, 0xF3A3, 0x97B7, 0xF3A2, 0x97B9, 0xF54A, 0x97BB, 0xF54B,
+	0x97BF, 0xF670, 0x97C1, 0xC5B7, 0x97C3, 0xC5B6, 0x97C4, 0xF84F,	0x97C5, 0xF850, 0x97C6, 0xC648, 0x97C7, 0xF8D1, 0x97C9, 0xC669,
+	0x97CB, 0xADB3, 0x97CC, 0xB6B4, 0x97CD, 0xE4CA, 0x97CE, 0xE4C9,	0x97CF, 0xE8B5, 0x97D0, 0xE8B4, 0x97D3, 0xC1FA, 0x97D4, 0xEF43,
+	0x97D5, 0xEF42, 0x97D6, 0xF1A5, 0x97D7, 0xF1A3, 0x97D8, 0xF1A6,	0x97D9, 0xF1A4, 0x97DC, 0xC3FC, 0x97DD, 0xF3A4, 0x97DE, 0xF3A5,
+	0x97DF, 0xF3A6, 0x97E1, 0xF671, 0x97E3, 0xF772, 0x97E5, 0xF8D2,	0x97ED, 0xADB4, 0x97F0, 0xEC57, 0x97F1, 0xEF44, 0x97F3, 0xADB5,
+	0x97F6, 0xBBE0, 0x97F8, 0xEC58, 0x97F9, 0xC341, 0x97FA, 0xF1A7,	0x97FB, 0xC3FD, 0x97FD, 0xF54C, 0x97FE, 0xF54D, 0x97FF, 0xC554,
+	0x9800, 0xF851, 0x9801, 0xADB6, 0x9802, 0xB3BB, 0x9803, 0xB3BC,	0x9804, 0xD84E, 0x9805, 0xB6B5, 0x9806, 0xB6B6, 0x9807, 0xDCAC,
+	0x9808, 0xB6B7, 0x980A, 0xB97A, 0x980C, 0xB97C, 0x980D, 0xE0DF,	0x980E, 0xE0E0, 0x980F, 0xE0DE, 0x9810, 0xB977, 0x9811, 0xB978,
+	0x9812, 0xB97B, 0x9813, 0xB979, 0x9816, 0xE4CB, 0x9817, 0xBBE1,	0x9818, 0xBBE2, 0x981B, 0xE8BC, 0x981C, 0xBE67, 0x981D, 0xE8B7,
+	0x981E, 0xE8B6, 0x9820, 0xE8BB, 0x9821, 0xBE65, 0x9824, 0xC05B,	0x9826, 0xE8B8, 0x9827, 0xE8BD, 0x9828, 0xE8BA, 0x9829, 0xE8B9,
+	0x982B, 0xBE66, 0x982D, 0xC059, 0x982F, 0xEC5A, 0x9830, 0xC055,	0x9832, 0xEC5B, 0x9835, 0xEC59, 0x9837, 0xC058, 0x9838, 0xC056,
+	0x9839, 0xC05A, 0x983B, 0xC057, 0x9841, 0xEF45, 0x9843, 0xEF4A,	0x9844, 0xEF46, 0x9845, 0xEF49, 0x9846, 0xC1FB, 0x9848, 0xEDD4,
+	0x9849, 0xEF48, 0x984A, 0xEF47, 0x984C, 0xC344, 0x984D, 0xC342,	0x984E, 0xC345, 0x984F, 0xC343, 0x9850, 0xF1A8, 0x9851, 0xF1A9,
+	0x9852, 0xF1AA, 0x9853, 0xC346, 0x9857, 0xF3AA, 0x9858, 0xC440,	0x9859, 0xF3A8, 0x985B, 0xC441, 0x985C, 0xF3A7, 0x985D, 0xF3A9,
+	0x985E, 0xC3FE, 0x985F, 0xF551, 0x9860, 0xF54E, 0x9862, 0xF54F,	0x9863, 0xF550, 0x9864, 0xF672, 0x9865, 0xC556, 0x9867, 0xC555,
+	0x9869, 0xF774, 0x986A, 0xF773, 0x986B, 0xC5B8, 0x986F, 0xC5E3,	0x9870, 0xC649, 0x9871, 0xC660, 0x9872, 0xF958, 0x9873, 0xF9AE,
+	0x9874, 0xF9AF, 0x98A8, 0xADB7, 0x98A9, 0xDCAD, 0x98AC, 0xE0E1,	0x98AD, 0xE4CC, 0x98AE, 0xE4CD, 0x98AF, 0xBBE3, 0x98B1, 0xBBE4,
+	0x98B2, 0xE8BE, 0x98B3, 0xBE68, 0x98B6, 0xC1FC, 0x98B8, 0xF1AB,	0x98BA, 0xC347, 0x98BB, 0xF3AD, 0x98BC, 0xC442, 0x98BD, 0xF3AC,
+	0x98BE, 0xF3AE, 0x98BF, 0xF3AB, 0x98C0, 0xF675, 0x98C1, 0xF552,	0x98C2, 0xF553, 0x98C4, 0xC4C6, 0x98C6, 0xF674, 0x98C9, 0xF673,
+	0x98CB, 0xF775, 0x98CC, 0xF9B0, 0x98DB, 0xADB8, 0x98DF, 0xADB9,	0x98E2, 0xB0A7, 0x98E3, 0xD448, 0x98E5, 0xD84F, 0x98E7, 0xB6B8,
+	0x98E9, 0xB6BB, 0x98EA, 0xB6B9, 0x98EB, 0xDCAE, 0x98ED, 0xB6BD,	0x98EF, 0xB6BA, 0x98F2, 0xB6BC, 0x98F4, 0xB97E, 0x98F6, 0xE0E2,
+	0x98F9, 0xE0E3, 0x98FA, 0xE8C0, 0x98FC, 0xB97D, 0x98FD, 0xB9A1,	0x98FE, 0xB9A2, 0x9900, 0xE4CF, 0x9902, 0xE4CE, 0x9903, 0xBBE5,
+	0x9905, 0xBBE6, 0x9907, 0xE4D0, 0x9908, 0xE8BF, 0x9909, 0xBBE8,	0x990A, 0xBE69, 0x990C, 0xBBE7, 0x9910, 0xC05C, 0x9911, 0xE8C1,
+	0x9912, 0xBE6B, 0x9913, 0xBE6A, 0x9914, 0xE8C2, 0x9915, 0xE8C5,	0x9916, 0xE8C3, 0x9917, 0xE8C4, 0x9918, 0xBE6C, 0x991A, 0xC061,
+	0x991B, 0xC05F, 0x991E, 0xC05E, 0x991F, 0xEC5D, 0x9921, 0xC060,	0x9924, 0xEC5C, 0x9925, 0xEF4B, 0x9927, 0xEC5E, 0x9928, 0xC05D,
+	0x9929, 0xEC5F, 0x992A, 0xEF4E, 0x992B, 0xEF4C, 0x992C, 0xEF4D,	0x992D, 0xEF52, 0x992E, 0xC34B, 0x992F, 0xEF51, 0x9930, 0xEF54,
+	0x9931, 0xEF53, 0x9932, 0xEF50, 0x9933, 0xEF4F, 0x9935, 0xC1FD,	0x993A, 0xF1AE, 0x993C, 0xF1AD, 0x993D, 0xC34A, 0x993E, 0xC348,
+	0x993F, 0xC349, 0x9941, 0xF1AC, 0x9943, 0xF3B1, 0x9945, 0xC443,	0x9947, 0xF3B0, 0x9948, 0xF3AF, 0x9949, 0xC444, 0x994B, 0xF558,
+	0x994C, 0xF557, 0x994E, 0xF555, 0x9950, 0xF554, 0x9951, 0xC4C8,	0x9952, 0xC4C7, 0x9953, 0xF559, 0x9954, 0xF776, 0x9955, 0xC5B9,
+	0x9956, 0xF677, 0x9957, 0xC557, 0x9958, 0xF676, 0x9959, 0xF556,	0x995B, 0xF777, 0x995C, 0xC5E4, 0x995E, 0xC661, 0x995F, 0xF959,
+	0x9961, 0xF9B1, 0x9996, 0xADBA, 0x9997, 0xD850, 0x9998, 0xEF55,	0x9999, 0xADBB, 0x999C, 0xE4D2, 0x999D, 0xE4D1, 0x999E, 0xEC60,
+	0x99A1, 0xEF57, 0x99A3, 0xEF56, 0x99A5, 0xC34C, 0x99A6, 0xF3B2,	0x99A7, 0xF3B3, 0x99A8, 0xC4C9, 0x99AB, 0xF9B2, 0x99AC, 0xB0A8,
+	0x99AD, 0xB6BF, 0x99AE, 0xB6BE, 0x99AF, 0xE0E4, 0x99B0, 0xE0E6,	0x99B1, 0xB9A4, 0x99B2, 0xE0E5, 0x99B3, 0xB9A3, 0x99B4, 0xB9A5,
+	0x99B5, 0xE0E7, 0x99B9, 0xE4D4, 0x99BA, 0xE4D6, 0x99BB, 0xE4D5,	0x99BD, 0xE4D8, 0x99C1, 0xBBE9, 0x99C2, 0xE4D7, 0x99C3, 0xE4D3,
+	0x99C7, 0xE4D9, 0x99C9, 0xE8CC, 0x99CB, 0xE8CF, 0x99CC, 0xE8D1,	0x99CD, 0xE8C7, 0x99CE, 0xE8CB, 0x99CF, 0xE8C8, 0x99D0, 0xBE6E,
+	0x99D1, 0xBE71, 0x99D2, 0xBE73, 0x99D3, 0xE8C9, 0x99D4, 0xE8CA,	0x99D5, 0xBE72, 0x99D6, 0xE8CD, 0x99D7, 0xE8D0, 0x99D8, 0xE8CE,
+	0x99D9, 0xBE74, 0x99DB, 0xBE70, 0x99DC, 0xE8C6, 0x99DD, 0xBE6D,	0x99DF, 0xBE6F, 0x99E2, 0xC063, 0x99E3, 0xEC66, 0x99E4, 0xEC64,
+	0x99E5, 0xEC63, 0x99E7, 0xEC69, 0x99E9, 0xEC68, 0x99EA, 0xEC67,	0x99EC, 0xEC62, 0x99ED, 0xC062, 0x99EE, 0xEC61, 0x99F0, 0xEC65,
+	0x99F1, 0xC064, 0x99F4, 0xEF5A, 0x99F6, 0xEF5E, 0x99F7, 0xEF5B,	0x99F8, 0xEF5D, 0x99F9, 0xEF5C, 0x99FA, 0xEF59, 0x99FB, 0xEF5F,
+	0x99FC, 0xEF62, 0x99FD, 0xEF60, 0x99FE, 0xEF61, 0x99FF, 0xC240,	0x9A01, 0xC1FE, 0x9A02, 0xEF58, 0x9A03, 0xEF63, 0x9A04, 0xF1B3,
+	0x9A05, 0xF1B6, 0x9A06, 0xF1B8, 0x9A07, 0xF1B7, 0x9A09, 0xF1B1,	0x9A0A, 0xF1B5, 0x9A0B, 0xF1B0, 0x9A0D, 0xF1B2, 0x9A0E, 0xC34D,
+	0x9A0F, 0xF1AF, 0x9A11, 0xF1B4, 0x9A14, 0xF3C0, 0x9A15, 0xF3B5,	0x9A16, 0xC445, 0x9A19, 0xC446, 0x9A1A, 0xF3B4, 0x9A1B, 0xF3B9,
+	0x9A1C, 0xF3BF, 0x9A1D, 0xF3B7, 0x9A1E, 0xF3BE, 0x9A20, 0xF3BB,	0x9A22, 0xF3BA, 0x9A23, 0xF3BD, 0x9A24, 0xF3B8, 0x9A25, 0xF3B6,
+	0x9A27, 0xF3BC, 0x9A29, 0xF560, 0x9A2A, 0xF55E, 0x9A2B, 0xC4CA,	0x9A2C, 0xF55D, 0x9A2D, 0xF563, 0x9A2E, 0xF561, 0x9A30, 0xC4CB,
+	0x9A31, 0xF55C, 0x9A32, 0xF55A, 0x9A34, 0xF55B, 0x9A35, 0xC4CD,	0x9A36, 0xF55F, 0x9A37, 0xC4CC, 0x9A38, 0xF562, 0x9A39, 0xF678,
+	0x9A3A, 0xF67E, 0x9A3D, 0xF679, 0x9A3E, 0xC55B, 0x9A3F, 0xF6A1,	0x9A40, 0xC55A, 0x9A41, 0xF67D, 0x9A42, 0xF67C, 0x9A43, 0xC559,
+	0x9A44, 0xF67B, 0x9A45, 0xC558, 0x9A46, 0xF67A, 0x9A48, 0xF77D,	0x9A49, 0xF7A1, 0x9A4A, 0xF77E, 0x9A4C, 0xF77B, 0x9A4D, 0xC5BB,
+	0x9A4E, 0xF778, 0x9A4F, 0xF77C, 0x9A50, 0xF7A3, 0x9A52, 0xF7A2,	0x9A53, 0xF779, 0x9A54, 0xF77A, 0x9A55, 0xC5BA, 0x9A56, 0xF852,
+	0x9A57, 0xC5E7, 0x9A59, 0xF853, 0x9A5A, 0xC5E5, 0x9A5B, 0xC5E6,	0x9A5E, 0xF8D3, 0x9A5F, 0xC64A, 0x9A60, 0xF976, 0x9A62, 0xC66A,
+	0x9A64, 0xF9B3, 0x9A65, 0xC66B, 0x9A66, 0xF9B4, 0x9A67, 0xF9B5,	0x9A68, 0xF9C3, 0x9A69, 0xF9C2, 0x9A6A, 0xC67A, 0x9A6B, 0xF9CD,
+	0x9AA8, 0xB0A9, 0x9AAB, 0xE0E9, 0x9AAD, 0xE0E8, 0x9AAF, 0xBBEA,	0x9AB0, 0xBBEB, 0x9AB1, 0xE4DA, 0x9AB3, 0xE8D2, 0x9AB4, 0xEC6C,
+	0x9AB7, 0xBE75, 0x9AB8, 0xC065, 0x9AB9, 0xEC6A, 0x9ABB, 0xEC6D,	0x9ABC, 0xC066, 0x9ABE, 0xEF64, 0x9ABF, 0xEC6B, 0x9AC0, 0xF1B9,
+	0x9AC1, 0xC34E, 0x9AC2, 0xF3C1, 0x9AC6, 0xF566, 0x9AC7, 0xF564,	0x9ACA, 0xF565, 0x9ACD, 0xF6A2, 0x9ACF, 0xC55C, 0x9AD0, 0xF7A4,
+	0x9AD1, 0xC5EA, 0x9AD2, 0xC5BC, 0x9AD3, 0xC5E8, 0x9AD4, 0xC5E9,	0x9AD5, 0xF8D4, 0x9AD6, 0xC662, 0x9AD8, 0xB0AA, 0x9ADC, 0xF1BA,
+	0x9ADF, 0xD449, 0x9AE1, 0xB9A6, 0x9AE3, 0xE4DB, 0x9AE6, 0xBBEC,	0x9AE7, 0xE4DC, 0x9AEB, 0xE8D4, 0x9AEC, 0xE8D3, 0x9AED, 0xC068,
+	0x9AEE, 0xBE76, 0x9AEF, 0xBE77, 0x9AF1, 0xE8D7, 0x9AF2, 0xE8D6,	0x9AF3, 0xE8D5, 0x9AF6, 0xEC6E, 0x9AF7, 0xEC71, 0x9AF9, 0xEC70,
+	0x9AFA, 0xEC6F, 0x9AFB, 0xC067, 0x9AFC, 0xEF68, 0x9AFD, 0xEF66,	0x9AFE, 0xEF65, 0x9B01, 0xEF67, 0x9B03, 0xC34F, 0x9B04, 0xF1BC,
+	0x9B05, 0xF1BD, 0x9B06, 0xC350, 0x9B08, 0xF1BB, 0x9B0A, 0xF3C3,	0x9B0B, 0xF3C2, 0x9B0C, 0xF3C5, 0x9B0D, 0xC447, 0x9B0E, 0xF3C4,
+	0x9B10, 0xF567, 0x9B11, 0xF569, 0x9B12, 0xF568, 0x9B15, 0xF6A3,	0x9B16, 0xF6A6, 0x9B17, 0xF6A4, 0x9B18, 0xF6A5, 0x9B19, 0xF7A5,
+	0x9B1A, 0xC5BD, 0x9B1E, 0xF854, 0x9B1F, 0xF855, 0x9B20, 0xF856,	0x9B22, 0xC64B, 0x9B23, 0xC663, 0x9B24, 0xF9B6, 0x9B25, 0xB0AB,
+	0x9B27, 0xBE78, 0x9B28, 0xC069, 0x9B29, 0xF1BE, 0x9B2B, 0xF7A6,	0x9B2E, 0xF9C4, 0x9B2F, 0xD44A, 0x9B31, 0xC67B, 0x9B32, 0xB0AC,
+	0x9B33, 0xEC72, 0x9B35, 0xF1BF, 0x9B37, 0xF3C6, 0x9B3A, 0xF6A7,	0x9B3B, 0xF7A7, 0x9B3C, 0xB0AD, 0x9B3E, 0xE4DD, 0x9B3F, 0xE4DE,
+	0x9B41, 0xBBED, 0x9B42, 0xBBEE, 0x9B43, 0xE8D9, 0x9B44, 0xBE7A,	0x9B45, 0xBE79, 0x9B46, 0xE8D8, 0x9B48, 0xEF69, 0x9B4A, 0xF1C0,
+	0x9B4B, 0xF1C2, 0x9B4C, 0xF1C1, 0x9B4D, 0xC353, 0x9B4E, 0xC352,	0x9B4F, 0xC351, 0x9B51, 0xC55E, 0x9B52, 0xF6A8, 0x9B54, 0xC55D,
+	0x9B55, 0xF7A9, 0x9B56, 0xF7A8, 0x9B58, 0xC64C, 0x9B59, 0xF8D5,	0x9B5A, 0xB3BD, 0x9B5B, 0xE0EA, 0x9B5F, 0xE4E1, 0x9B60, 0xE4DF,
+	0x9B61, 0xE4E0, 0x9B64, 0xE8E2, 0x9B66, 0xE8DD, 0x9B67, 0xE8DA,	0x9B68, 0xE8E1, 0x9B6C, 0xE8E3, 0x9B6F, 0xBE7C, 0x9B70, 0xE8E0,
+	0x9B71, 0xE8DC, 0x9B74, 0xE8DB, 0x9B75, 0xE8DF, 0x9B76, 0xE8DE,	0x9B77, 0xBE7B, 0x9B7A, 0xEC7D, 0x9B7B, 0xEC78, 0x9B7C, 0xEC76,
+	0x9B7D, 0xECA1, 0x9B7E, 0xEC77, 0x9B80, 0xEC73, 0x9B82, 0xEC79,	0x9B85, 0xEC74, 0x9B86, 0xEF72, 0x9B87, 0xEC75, 0x9B88, 0xECA2,
+	0x9B90, 0xEC7C, 0x9B91, 0xC06A, 0x9B92, 0xEC7B, 0x9B93, 0xEC7A,	0x9B95, 0xEC7E, 0x9B9A, 0xEF6A, 0x9B9B, 0xEF6D, 0x9B9E, 0xEF6C,
+	0x9BA0, 0xEF74, 0x9BA1, 0xEF6F, 0x9BA2, 0xEF73, 0x9BA4, 0xEF71,	0x9BA5, 0xEF70, 0x9BA6, 0xEF6E, 0x9BA8, 0xEF6B, 0x9BAA, 0xC243,
+	0x9BAB, 0xC242, 0x9BAD, 0xC244, 0x9BAE, 0xC241, 0x9BAF, 0xEF75,	0x9BB5, 0xF1C8, 0x9BB6, 0xF1CB, 0x9BB8, 0xF1C9, 0x9BB9, 0xF1CD,
+	0x9BBD, 0xF1CE, 0x9BBF, 0xF1C6, 0x9BC0, 0xC358, 0x9BC1, 0xF1C7,	0x9BC3, 0xF1C5, 0x9BC4, 0xF1CC, 0x9BC6, 0xF1C4, 0x9BC7, 0xF1C3,
+	0x9BC8, 0xC357, 0x9BC9, 0xC355, 0x9BCA, 0xC354, 0x9BD3, 0xF1CA,	0x9BD4, 0xF3CF, 0x9BD5, 0xF3D5, 0x9BD6, 0xC44A, 0x9BD7, 0xF3D0,
+	0x9BD9, 0xF3D3, 0x9BDA, 0xF3D7, 0x9BDB, 0xC44B, 0x9BDC, 0xF3D2,	0x9BDE, 0xF3CA, 0x9BE0, 0xF3C9, 0x9BE1, 0xF3D6, 0x9BE2, 0xF3CD,
+	0x9BE4, 0xF3CB, 0x9BE5, 0xF3D4, 0x9BE6, 0xF3CC, 0x9BE7, 0xC449,	0x9BE8, 0xC448, 0x9BEA, 0xF3C7, 0x9BEB, 0xF3C8, 0x9BEC, 0xF3D1,
+	0x9BF0, 0xF3CE, 0x9BF7, 0xF56C, 0x9BF8, 0xF56F, 0x9BFD, 0xC356,	0x9C05, 0xF56D, 0x9C06, 0xF573, 0x9C07, 0xF571, 0x9C08, 0xF56B,
+	0x9C09, 0xF576, 0x9C0B, 0xF56A, 0x9C0D, 0xC4CF, 0x9C0E, 0xF572,	0x9C12, 0xF56E, 0x9C13, 0xC4CE, 0x9C14, 0xF575, 0x9C17, 0xF574,
+	0x9C1C, 0xF6AB, 0x9C1D, 0xF6AA, 0x9C21, 0xF6B1, 0x9C23, 0xF6AD,	0x9C24, 0xF6B0, 0x9C25, 0xC560, 0x9C28, 0xF6AE, 0x9C29, 0xF6AF,
+	0x9C2B, 0xF6A9, 0x9C2C, 0xF6AC, 0x9C2D, 0xC55F, 0x9C31, 0xC5BF,	0x9C32, 0xF7B4, 0x9C33, 0xF7AF, 0x9C34, 0xF7B3, 0x9C36, 0xF7B6,
+	0x9C37, 0xF7B2, 0x9C39, 0xF7AE, 0x9C3B, 0xC5C1, 0x9C3C, 0xF7B1,	0x9C3D, 0xF7B5, 0x9C3E, 0xC5C0, 0x9C3F, 0xF7AC, 0x9C40, 0xF570,
+	0x9C41, 0xF7B0, 0x9C44, 0xF7AD, 0x9C46, 0xF7AA, 0x9C48, 0xF7AB,	0x9C49, 0xC5BE, 0x9C4A, 0xF85A, 0x9C4B, 0xF85C, 0x9C4C, 0xF85F,
+	0x9C4D, 0xF85B, 0x9C4E, 0xF860, 0x9C50, 0xF859, 0x9C52, 0xF857,	0x9C54, 0xC5EB, 0x9C55, 0xF85D, 0x9C56, 0xC5ED, 0x9C57, 0xC5EC,
+	0x9C58, 0xF858, 0x9C59, 0xF85E, 0x9C5E, 0xF8DA, 0x9C5F, 0xC64D,	0x9C60, 0xF8DB, 0x9C62, 0xF8D9, 0x9C63, 0xF8D6, 0x9C66, 0xF8D8,
+	0x9C67, 0xF8D7, 0x9C68, 0xF95A, 0x9C6D, 0xF95C, 0x9C6E, 0xF95B,	0x9C71, 0xF979, 0x9C73, 0xF978, 0x9C74, 0xF977, 0x9C75, 0xF97A,
+	0x9C77, 0xC673, 0x9C78, 0xC674, 0x9C79, 0xF9CA, 0x9C7A, 0xF9CE,	0x9CE5, 0xB3BE, 0x9CE6, 0xDCAF, 0x9CE7, 0xE0ED, 0x9CE9, 0xB9A7,
+	0x9CEA, 0xE0EB, 0x9CED, 0xE0EC, 0x9CF1, 0xE4E2, 0x9CF2, 0xE4E3,	0x9CF3, 0xBBF1, 0x9CF4, 0xBBEF, 0x9CF5, 0xE4E4, 0x9CF6, 0xBBF0,
+	0x9CF7, 0xE8E8, 0x9CF9, 0xE8EB, 0x9CFA, 0xE8E5, 0x9CFB, 0xE8EC,	0x9CFC, 0xE8E4, 0x9CFD, 0xE8E6, 0x9CFF, 0xE8E7, 0x9D00, 0xE8EA,
+	0x9D03, 0xBEA1, 0x9D04, 0xE8EF, 0x9D05, 0xE8EE, 0x9D06, 0xBE7D,	0x9D07, 0xE8E9, 0x9D08, 0xE8ED, 0x9D09, 0xBE7E, 0x9D10, 0xECAC,
+	0x9D12, 0xC06F, 0x9D14, 0xECA7, 0x9D15, 0xC06B, 0x9D17, 0xECA4,	0x9D18, 0xECAA, 0x9D19, 0xECAD, 0x9D1B, 0xC070, 0x9D1D, 0xECA9,
+	0x9D1E, 0xECA6, 0x9D1F, 0xECAE, 0x9D20, 0xECA5, 0x9D22, 0xECAB,	0x9D23, 0xC06C, 0x9D25, 0xECA3, 0x9D26, 0xC06D, 0x9D28, 0xC06E,
+	0x9D29, 0xECA8, 0x9D2D, 0xEFA9, 0x9D2E, 0xEF7A, 0x9D2F, 0xEF7B,	0x9D30, 0xEF7E, 0x9D31, 0xEF7C, 0x9D33, 0xEF76, 0x9D36, 0xEF79,
+	0x9D37, 0xEFA5, 0x9D38, 0xEF7D, 0x9D3B, 0xC245, 0x9D3D, 0xEFA7,	0x9D3E, 0xEFA4, 0x9D3F, 0xC246, 0x9D40, 0xEFA6, 0x9D41, 0xEF77,
+	0x9D42, 0xEFA2, 0x9D43, 0xEFA3, 0x9D45, 0xEFA1, 0x9D4A, 0xF1D2,	0x9D4B, 0xF1D4, 0x9D4C, 0xF1D7, 0x9D4F, 0xF1D1, 0x9D51, 0xC359,
+	0x9D52, 0xF1D9, 0x9D53, 0xF1D0, 0x9D54, 0xF1DA, 0x9D56, 0xF1D6,	0x9D57, 0xF1D8, 0x9D58, 0xF1DC, 0x9D59, 0xF1D5, 0x9D5A, 0xF1DD,
+	0x9D5B, 0xF1D3, 0x9D5C, 0xF1CF, 0x9D5D, 0xC35A, 0x9D5F, 0xF1DB,	0x9D60, 0xC35B, 0x9D61, 0xC44D, 0x9D67, 0xEF78, 0x9D68, 0xF3F1,
+	0x9D69, 0xF3E8, 0x9D6A, 0xC44F, 0x9D6B, 0xF3E4, 0x9D6C, 0xC450,	0x9D6F, 0xF3ED, 0x9D70, 0xF3E7, 0x9D71, 0xF3DD, 0x9D72, 0xC44E,
+	0x9D73, 0xF3EA, 0x9D74, 0xF3E5, 0x9D75, 0xF3E6, 0x9D77, 0xF3D8,	0x9D78, 0xF3DF, 0x9D79, 0xF3EE, 0x9D7B, 0xF3EB, 0x9D7D, 0xF3E3,
+	0x9D7F, 0xF3EF, 0x9D80, 0xF3DE, 0x9D81, 0xF3D9, 0x9D82, 0xF3EC,	0x9D84, 0xF3DB, 0x9D85, 0xF3E9, 0x9D86, 0xF3E0, 0x9D87, 0xF3F0,
+	0x9D88, 0xF3DC, 0x9D89, 0xC44C, 0x9D8A, 0xF3DA, 0x9D8B, 0xF3E1,	0x9D8C, 0xF3E2, 0x9D90, 0xF57D, 0x9D92, 0xF57B, 0x9D94, 0xF5A2,
+	0x9D96, 0xF5AE, 0x9D97, 0xF5A5, 0x9D98, 0xF57C, 0x9D99, 0xF578,	0x9D9A, 0xF5A7, 0x9D9B, 0xF57E, 0x9D9C, 0xF5A3, 0x9D9D, 0xF57A,
+	0x9D9E, 0xF5AA, 0x9D9F, 0xF577, 0x9DA0, 0xF5A1, 0x9DA1, 0xF5A6,	0x9DA2, 0xF5A8, 0x9DA3, 0xF5AB, 0x9DA4, 0xF579, 0x9DA6, 0xF5AF,
+	0x9DA7, 0xF5B0, 0x9DA8, 0xF5A9, 0x9DA9, 0xF5AD, 0x9DAA, 0xF5A4,	0x9DAC, 0xF6C1, 0x9DAD, 0xF6C4, 0x9DAF, 0xC561, 0x9DB1, 0xF6C3,
+	0x9DB2, 0xF6C8, 0x9DB3, 0xF6C6, 0x9DB4, 0xC562, 0x9DB5, 0xF6BD,	0x9DB6, 0xF6B3, 0x9DB7, 0xF6B2, 0x9DB8, 0xC564, 0x9DB9, 0xF6BF,
+	0x9DBA, 0xF6C0, 0x9DBB, 0xF6BC, 0x9DBC, 0xF6B4, 0x9DBE, 0xF6B9,	0x9DBF, 0xF5AC, 0x9DC1, 0xF6B5, 0x9DC2, 0xC563, 0x9DC3, 0xF6BB,
+	0x9DC5, 0xF6BA, 0x9DC7, 0xF6B6, 0x9DC8, 0xF6C2, 0x9DCA, 0xF6B7,	0x9DCB, 0xF7BB, 0x9DCC, 0xF6C5, 0x9DCD, 0xF6C7, 0x9DCE, 0xF6BE,
+	0x9DCF, 0xF6B8, 0x9DD0, 0xF7BC, 0x9DD1, 0xF7BE, 0x9DD2, 0xF7B8,	0x9DD3, 0xC5C2, 0x9DD5, 0xF7C5, 0x9DD6, 0xF7C3, 0x9DD7, 0xC5C3,
+	0x9DD8, 0xF7C2, 0x9DD9, 0xF7C1, 0x9DDA, 0xF7BA, 0x9DDB, 0xF7B7,	0x9DDC, 0xF7BD, 0x9DDD, 0xF7C6, 0x9DDE, 0xF7B9, 0x9DDF, 0xF7BF,
+	0x9DE1, 0xF869, 0x9DE2, 0xF86E, 0x9DE3, 0xF864, 0x9DE4, 0xF867,	0x9DE5, 0xC5EE, 0x9DE6, 0xF86B, 0x9DE8, 0xF872, 0x9DE9, 0xF7C0,
+	0x9DEB, 0xF865, 0x9DEC, 0xF86F, 0x9DED, 0xF873, 0x9DEE, 0xF86A,	0x9DEF, 0xF863, 0x9DF0, 0xF86D, 0x9DF2, 0xF86C, 0x9DF3, 0xF871,
+	0x9DF4, 0xF870, 0x9DF5, 0xF7C4, 0x9DF6, 0xF868, 0x9DF7, 0xF862,	0x9DF8, 0xF866, 0x9DF9, 0xC64E, 0x9DFA, 0xC64F, 0x9DFB, 0xF861,
+	0x9DFD, 0xF8E6, 0x9DFE, 0xF8DD, 0x9DFF, 0xF8E5, 0x9E00, 0xF8E2,	0x9E01, 0xF8E3, 0x9E02, 0xF8DC, 0x9E03, 0xF8DF, 0x9E04, 0xF8E7,
+	0x9E05, 0xF8E1, 0x9E06, 0xF8E0, 0x9E07, 0xF8DE, 0x9E09, 0xF8E4,	0x9E0B, 0xF95D, 0x9E0D, 0xF95E, 0x9E0F, 0xF960, 0x9E10, 0xF95F,
+	0x9E11, 0xF962, 0x9E12, 0xF961, 0x9E13, 0xF97C, 0x9E14, 0xF97B,	0x9E15, 0xF9B7, 0x9E17, 0xF9B8, 0x9E19, 0xF9C5, 0x9E1A, 0xC678,
+	0x9E1B, 0xC67C, 0x9E1D, 0xF9CF, 0x9E1E, 0xC67D, 0x9E75, 0xB3BF,	0x9E79, 0xC4D0, 0x9E7A, 0xF6C9, 0x9E7C, 0xC650, 0x9E7D, 0xC651,
+	0x9E7F, 0xB3C0, 0x9E80, 0xE0EE, 0x9E82, 0xB9A8, 0x9E83, 0xE8F0,	0x9E86, 0xECB0, 0x9E87, 0xECB1, 0x9E88, 0xECAF, 0x9E89, 0xEFAB,
+	0x9E8A, 0xEFAA, 0x9E8B, 0xC247, 0x9E8C, 0xF1DF, 0x9E8D, 0xEFAC,	0x9E8E, 0xF1DE, 0x9E91, 0xF3F3, 0x9E92, 0xC451, 0x9E93, 0xC453,
+	0x9E94, 0xF3F2, 0x9E97, 0xC452, 0x9E99, 0xF5B1, 0x9E9A, 0xF5B3,	0x9E9B, 0xF5B2, 0x9E9C, 0xF6CA, 0x9E9D, 0xC565, 0x9E9F, 0xC5EF,
+	0x9EA0, 0xF8E8, 0x9EA1, 0xF963, 0x9EA4, 0xF9D2, 0x9EA5, 0xB3C1,	0x9EA7, 0xE4E5, 0x9EA9, 0xBEA2, 0x9EAD, 0xECB3, 0x9EAE, 0xECB2,
+	0x9EB0, 0xEFAD, 0x9EB4, 0xC454, 0x9EB5, 0xC4D1, 0x9EB6, 0xF7C7,	0x9EB7, 0xF9CB, 0x9EBB, 0xB3C2, 0x9EBC, 0xBBF2, 0x9EBE, 0xBEA3,
+	0x9EC0, 0xF3F4, 0x9EC2, 0xF874, 0x9EC3, 0xB6C0, 0x9EC8, 0xEFAE,	0x9ECC, 0xC664, 0x9ECD, 0xB6C1, 0x9ECE, 0xBEA4, 0x9ECF, 0xC248,
+	0x9ED0, 0xF875, 0x9ED1, 0xB6C2, 0x9ED3, 0xE8F1, 0x9ED4, 0xC072,	0x9ED5, 0xECB4, 0x9ED6, 0xECB5, 0x9ED8, 0xC071, 0x9EDA, 0xEFAF,
+	0x9EDB, 0xC24C, 0x9EDC, 0xC24A, 0x9EDD, 0xC24B, 0x9EDE, 0xC249,	0x9EDF, 0xF1E0, 0x9EE0, 0xC35C, 0x9EE4, 0xF5B5, 0x9EE5, 0xF5B4,
+	0x9EE6, 0xF5B7, 0x9EE7, 0xF5B6, 0x9EE8, 0xC4D2, 0x9EEB, 0xF6CB,	0x9EED, 0xF6CD, 0x9EEE, 0xF6CC, 0x9EEF, 0xC566, 0x9EF0, 0xF7C8,
+	0x9EF2, 0xF876, 0x9EF3, 0xF877, 0x9EF4, 0xC5F0, 0x9EF5, 0xF964,	0x9EF6, 0xF97D, 0x9EF7, 0xC675, 0x9EF9, 0xDCB0, 0x9EFA, 0xECB6,
+	0x9EFB, 0xEFB0, 0x9EFC, 0xF3F5, 0x9EFD, 0xE0EF, 0x9EFF, 0xEFB1,	0x9F00, 0xF1E2, 0x9F01, 0xF1E1, 0x9F06, 0xF878, 0x9F07, 0xC652,
+	0x9F09, 0xF965, 0x9F0A, 0xF97E, 0x9F0E, 0xB9A9, 0x9F0F, 0xE8F2,	0x9F10, 0xE8F3, 0x9F12, 0xECB7, 0x9F13, 0xB9AA, 0x9F15, 0xC35D,
+	0x9F16, 0xF1E3, 0x9F18, 0xF6CF, 0x9F19, 0xC567, 0x9F1A, 0xF6D0,	0x9F1B, 0xF6CE, 0x9F1C, 0xF879, 0x9F1E, 0xF8E9, 0x9F20, 0xB9AB,
+	0x9F22, 0xEFB4, 0x9F23, 0xEFB3, 0x9F24, 0xEFB2, 0x9F25, 0xF1E4,	0x9F28, 0xF1E8, 0x9F29, 0xF1E7, 0x9F2A, 0xF1E6, 0x9F2B, 0xF1E5,
+	0x9F2C, 0xC35E, 0x9F2D, 0xF3F6, 0x9F2E, 0xF5B9, 0x9F2F, 0xC4D3,	0x9F30, 0xF5B8, 0x9F31, 0xF6D1, 0x9F32, 0xF7CB, 0x9F33, 0xF7CA,
+	0x9F34, 0xC5C4, 0x9F35, 0xF7C9, 0x9F36, 0xF87C, 0x9F37, 0xF87B,	0x9F38, 0xF87A, 0x9F3B, 0xBBF3, 0x9F3D, 0xECB8, 0x9F3E, 0xC24D,
+	0x9F40, 0xF3F7, 0x9F41, 0xF3F8, 0x9F42, 0xF7CC, 0x9F43, 0xF87D,	0x9F46, 0xF8EA, 0x9F47, 0xF966, 0x9F48, 0xF9B9, 0x9F49, 0xF9D4,
+	0x9F4A, 0xBBF4, 0x9F4B, 0xC24E, 0x9F4C, 0xF1E9, 0x9F4D, 0xF3F9,	0x9F4E, 0xF6D2, 0x9F4F, 0xF87E, 0x9F52, 0xBEA6, 0x9F54, 0xEFB5,
+	0x9F55, 0xF1EA, 0x9F56, 0xF3FA, 0x9F57, 0xF3FB, 0x9F58, 0xF3FC,	0x9F59, 0xF5BE, 0x9F5B, 0xF5BA, 0x9F5C, 0xC568, 0x9F5D, 0xF5BD,
+	0x9F5E, 0xF5BC, 0x9F5F, 0xC4D4, 0x9F60, 0xF5BB, 0x9F61, 0xC4D6,	0x9F63, 0xC4D5, 0x9F64, 0xF6D4, 0x9F65, 0xF6D3, 0x9F66, 0xC569,
+	0x9F67, 0xC56A, 0x9F6A, 0xC5C6, 0x9F6B, 0xF7CD, 0x9F6C, 0xC5C5,	0x9F6E, 0xF8A3, 0x9F6F, 0xF8A4, 0x9F70, 0xF8A2, 0x9F71, 0xF8A1,
+	0x9F72, 0xC654, 0x9F74, 0xF8EB, 0x9F75, 0xF8EC, 0x9F76, 0xF8ED,	0x9F77, 0xC653, 0x9F78, 0xF967, 0x9F79, 0xF96A, 0x9F7A, 0xF969,
+	0x9F7B, 0xF968, 0x9F7E, 0xF9D3, 0x9F8D, 0xC073, 0x9F90, 0xC365,	0x9F91, 0xF5BF, 0x9F92, 0xF6D5, 0x9F94, 0xC5C7, 0x9F95, 0xF7CE,
+	0x9F98, 0xF9D5, 0x9F9C, 0xC074, 0x9FA0, 0xEFB6, 0x9FA2, 0xF7CF,	0x9FA4, 0xF9A1, 0xFA0C, 0xC94A, 0xFA0D, 0xDDFC, 0xFE30, 0xA14A,
+	0xFE31, 0xA157, 0xFE33, 0xA159, 0xFE34, 0xA15B, 0xFE35, 0xA15F,	0xFE36, 0xA160, 0xFE37, 0xA163, 0xFE38, 0xA164, 0xFE39, 0xA167,
+	0xFE3A, 0xA168, 0xFE3B, 0xA16B, 0xFE3C, 0xA16C, 0xFE3D, 0xA16F,	0xFE3E, 0xA170, 0xFE3F, 0xA173, 0xFE40, 0xA174, 0xFE41, 0xA177,
+	0xFE42, 0xA178, 0xFE43, 0xA17B, 0xFE44, 0xA17C, 0xFE49, 0xA1C6,	0xFE4A, 0xA1C7, 0xFE4B, 0xA1CA, 0xFE4C, 0xA1CB, 0xFE4D, 0xA1C8,
+	0xFE4E, 0xA1C9, 0xFE4F, 0xA15C, 0xFE50, 0xA14D, 0xFE51, 0xA14E,	0xFE52, 0xA14F, 0xFE54, 0xA151, 0xFE55, 0xA152, 0xFE56, 0xA153,
+	0xFE57, 0xA154, 0xFE59, 0xA17D, 0xFE5A, 0xA17E, 0xFE5B, 0xA1A1,	0xFE5C, 0xA1A2, 0xFE5D, 0xA1A3, 0xFE5E, 0xA1A4, 0xFE5F, 0xA1CC,
+	0xFE60, 0xA1CD, 0xFE61, 0xA1CE, 0xFE62, 0xA1DE, 0xFE63, 0xA1DF,	0xFE64, 0xA1E0, 0xFE65, 0xA1E1, 0xFE66, 0xA1E2, 0xFE68, 0xA242,
+	0xFE69, 0xA24C, 0xFE6A, 0xA24D, 0xFE6B, 0xA24E, 0xFF01, 0xA149,	0xFF03, 0xA1AD, 0xFF04, 0xA243, 0xFF05, 0xA248, 0xFF06, 0xA1AE,
+	0xFF08, 0xA15D, 0xFF09, 0xA15E, 0xFF0A, 0xA1AF, 0xFF0B, 0xA1CF,	0xFF0C, 0xA141, 0xFF0D, 0xA1D0, 0xFF0E, 0xA144, 0xFF0F, 0xA1FE,
+	0xFF10, 0xA2AF, 0xFF11, 0xA2B0, 0xFF12, 0xA2B1, 0xFF13, 0xA2B2,	0xFF14, 0xA2B3, 0xFF15, 0xA2B4, 0xFF16, 0xA2B5, 0xFF17, 0xA2B6,
+	0xFF18, 0xA2B7, 0xFF19, 0xA2B8, 0xFF1A, 0xA147, 0xFF1B, 0xA146,	0xFF1C, 0xA1D5, 0xFF1D, 0xA1D7, 0xFF1E, 0xA1D6, 0xFF1F, 0xA148,
+	0xFF20, 0xA249, 0xFF21, 0xA2CF, 0xFF22, 0xA2D0, 0xFF23, 0xA2D1,	0xFF24, 0xA2D2, 0xFF25, 0xA2D3, 0xFF26, 0xA2D4, 0xFF27, 0xA2D5,
+	0xFF28, 0xA2D6, 0xFF29, 0xA2D7, 0xFF2A, 0xA2D8, 0xFF2B, 0xA2D9,	0xFF2C, 0xA2DA, 0xFF2D, 0xA2DB, 0xFF2E, 0xA2DC, 0xFF2F, 0xA2DD,
+	0xFF30, 0xA2DE, 0xFF31, 0xA2DF, 0xFF32, 0xA2E0, 0xFF33, 0xA2E1,	0xFF34, 0xA2E2, 0xFF35, 0xA2E3, 0xFF36, 0xA2E4, 0xFF37, 0xA2E5,
+	0xFF38, 0xA2E6, 0xFF39, 0xA2E7, 0xFF3A, 0xA2E8, 0xFF3C, 0xA240,	0xFF3F, 0xA1C4, 0xFF41, 0xA2E9, 0xFF42, 0xA2EA, 0xFF43, 0xA2EB,
+	0xFF44, 0xA2EC, 0xFF45, 0xA2ED, 0xFF46, 0xA2EE, 0xFF47, 0xA2EF,	0xFF48, 0xA2F0, 0xFF49, 0xA2F1, 0xFF4A, 0xA2F2, 0xFF4B, 0xA2F3,
+	0xFF4C, 0xA2F4, 0xFF4D, 0xA2F5, 0xFF4E, 0xA2F6, 0xFF4F, 0xA2F7,	0xFF50, 0xA2F8, 0xFF51, 0xA2F9, 0xFF52, 0xA2FA, 0xFF53, 0xA2FB,
+	0xFF54, 0xA2FC, 0xFF55, 0xA2FD, 0xFF56, 0xA2FE, 0xFF57, 0xA340,	0xFF58, 0xA341, 0xFF59, 0xA342, 0xFF5A, 0xA343, 0xFF5B, 0xA161,
+	0xFF5C, 0xA155, 0xFF5D, 0xA162, 0xFF5E, 0xA1E3, 0xFFE0, 0xA246,	0xFFE1, 0xA247, 0xFFE3, 0xA1C3, 0xFFE5, 0xA244, 0, 0
+};
+
+static const WCHAR oem2uni950[] = {	/* Big5 --> Unicode pairs */
+	0xA140, 0x3000, 0xA141, 0xFF0C, 0xA142, 0x3001, 0xA143, 0x3002,	0xA144, 0xFF0E, 0xA145, 0x2027, 0xA146, 0xFF1B, 0xA147, 0xFF1A,
+	0xA148, 0xFF1F, 0xA149, 0xFF01, 0xA14A, 0xFE30, 0xA14B, 0x2026,	0xA14C, 0x2025, 0xA14D, 0xFE50, 0xA14E, 0xFE51, 0xA14F, 0xFE52,
+	0xA150, 0x00B7, 0xA151, 0xFE54, 0xA152, 0xFE55, 0xA153, 0xFE56,	0xA154, 0xFE57, 0xA155, 0xFF5C, 0xA156, 0x2013, 0xA157, 0xFE31,
+	0xA158, 0x2014, 0xA159, 0xFE33, 0xA15A, 0x2574, 0xA15B, 0xFE34,	0xA15C, 0xFE4F, 0xA15D, 0xFF08, 0xA15E, 0xFF09, 0xA15F, 0xFE35,
+	0xA160, 0xFE36, 0xA161, 0xFF5B, 0xA162, 0xFF5D, 0xA163, 0xFE37,	0xA164, 0xFE38, 0xA165, 0x3014, 0xA166, 0x3015, 0xA167, 0xFE39,
+	0xA168, 0xFE3A, 0xA169, 0x3010, 0xA16A, 0x3011, 0xA16B, 0xFE3B,	0xA16C, 0xFE3C, 0xA16D, 0x300A, 0xA16E, 0x300B, 0xA16F, 0xFE3D,
+	0xA170, 0xFE3E, 0xA171, 0x3008, 0xA172, 0x3009, 0xA173, 0xFE3F,	0xA174, 0xFE40, 0xA175, 0x300C, 0xA176, 0x300D, 0xA177, 0xFE41,
+	0xA178, 0xFE42, 0xA179, 0x300E, 0xA17A, 0x300F, 0xA17B, 0xFE43,	0xA17C, 0xFE44, 0xA17D, 0xFE59, 0xA17E, 0xFE5A, 0xA1A1, 0xFE5B,
+	0xA1A2, 0xFE5C, 0xA1A3, 0xFE5D, 0xA1A4, 0xFE5E, 0xA1A5, 0x2018,	0xA1A6, 0x2019, 0xA1A7, 0x201C, 0xA1A8, 0x201D, 0xA1A9, 0x301D,
+	0xA1AA, 0x301E, 0xA1AB, 0x2035, 0xA1AC, 0x2032, 0xA1AD, 0xFF03,	0xA1AE, 0xFF06, 0xA1AF, 0xFF0A, 0xA1B0, 0x203B, 0xA1B1, 0x00A7,
+	0xA1B2, 0x3003, 0xA1B3, 0x25CB, 0xA1B4, 0x25CF, 0xA1B5, 0x25B3,	0xA1B6, 0x25B2, 0xA1B7, 0x25CE, 0xA1B8, 0x2606, 0xA1B9, 0x2605,
+	0xA1BA, 0x25C7, 0xA1BB, 0x25C6, 0xA1BC, 0x25A1, 0xA1BD, 0x25A0,	0xA1BE, 0x25BD, 0xA1BF, 0x25BC, 0xA1C0, 0x32A3, 0xA1C1, 0x2105,
+	0xA1C2, 0x00AF, 0xA1C3, 0xFFE3, 0xA1C4, 0xFF3F, 0xA1C5, 0x02CD,	0xA1C6, 0xFE49, 0xA1C7, 0xFE4A, 0xA1C8, 0xFE4D, 0xA1C9, 0xFE4E,
+	0xA1CA, 0xFE4B, 0xA1CB, 0xFE4C, 0xA1CC, 0xFE5F, 0xA1CD, 0xFE60,	0xA1CE, 0xFE61, 0xA1CF, 0xFF0B, 0xA1D0, 0xFF0D, 0xA1D1, 0x00D7,
+	0xA1D2, 0x00F7, 0xA1D3, 0x00B1, 0xA1D4, 0x221A, 0xA1D5, 0xFF1C,	0xA1D6, 0xFF1E, 0xA1D7, 0xFF1D, 0xA1D8, 0x2266, 0xA1D9, 0x2267,
+	0xA1DA, 0x2260, 0xA1DB, 0x221E, 0xA1DC, 0x2252, 0xA1DD, 0x2261,	0xA1DE, 0xFE62, 0xA1DF, 0xFE63, 0xA1E0, 0xFE64, 0xA1E1, 0xFE65,
+	0xA1E2, 0xFE66, 0xA1E3, 0xFF5E, 0xA1E4, 0x2229, 0xA1E5, 0x222A,	0xA1E6, 0x22A5, 0xA1E7, 0x2220, 0xA1E8, 0x221F, 0xA1E9, 0x22BF,
+	0xA1EA, 0x33D2, 0xA1EB, 0x33D1, 0xA1EC, 0x222B, 0xA1ED, 0x222E,	0xA1EE, 0x2235, 0xA1EF, 0x2234, 0xA1F0, 0x2640, 0xA1F1, 0x2642,
+	0xA1F2, 0x2295, 0xA1F3, 0x2299, 0xA1F4, 0x2191, 0xA1F5, 0x2193,	0xA1F6, 0x2190, 0xA1F7, 0x2192, 0xA1F8, 0x2196, 0xA1F9, 0x2197,
+	0xA1FA, 0x2199, 0xA1FB, 0x2198, 0xA1FC, 0x2225, 0xA1FD, 0x2223,	0xA1FE, 0xFF0F, 0xA240, 0xFF3C, 0xA241, 0x2215, 0xA242, 0xFE68,
+	0xA243, 0xFF04, 0xA244, 0xFFE5, 0xA245, 0x3012, 0xA246, 0xFFE0,	0xA247, 0xFFE1, 0xA248, 0xFF05, 0xA249, 0xFF20, 0xA24A, 0x2103,
+	0xA24B, 0x2109, 0xA24C, 0xFE69, 0xA24D, 0xFE6A, 0xA24E, 0xFE6B,	0xA24F, 0x33D5, 0xA250, 0x339C, 0xA251, 0x339D, 0xA252, 0x339E,
+	0xA253, 0x33CE, 0xA254, 0x33A1, 0xA255, 0x338E, 0xA256, 0x338F,	0xA257, 0x33C4, 0xA258, 0x00B0, 0xA259, 0x5159, 0xA25A, 0x515B,
+	0xA25B, 0x515E, 0xA25C, 0x515D, 0xA25D, 0x5161, 0xA25E, 0x5163,	0xA25F, 0x55E7, 0xA260, 0x74E9, 0xA261, 0x7CCE, 0xA262, 0x2581,
+	0xA263, 0x2582, 0xA264, 0x2583, 0xA265, 0x2584, 0xA266, 0x2585,	0xA267, 0x2586, 0xA268, 0x2587, 0xA269, 0x2588, 0xA26A, 0x258F,
+	0xA26B, 0x258E, 0xA26C, 0x258D, 0xA26D, 0x258C, 0xA26E, 0x258B,	0xA26F, 0x258A, 0xA270, 0x2589, 0xA271, 0x253C, 0xA272, 0x2534,
+	0xA273, 0x252C, 0xA274, 0x2524, 0xA275, 0x251C, 0xA276, 0x2594,	0xA277, 0x2500, 0xA278, 0x2502, 0xA279, 0x2595, 0xA27A, 0x250C,
+	0xA27B, 0x2510, 0xA27C, 0x2514, 0xA27D, 0x2518, 0xA27E, 0x256D,	0xA2A1, 0x256E, 0xA2A2, 0x2570, 0xA2A3, 0x256F, 0xA2A4, 0x2550,
+	0xA2A5, 0x255E, 0xA2A6, 0x256A, 0xA2A7, 0x2561, 0xA2A8, 0x25E2,	0xA2A9, 0x25E3, 0xA2AA, 0x25E5, 0xA2AB, 0x25E4, 0xA2AC, 0x2571,
+	0xA2AD, 0x2572, 0xA2AE, 0x2573, 0xA2AF, 0xFF10, 0xA2B0, 0xFF11,	0xA2B1, 0xFF12, 0xA2B2, 0xFF13, 0xA2B3, 0xFF14, 0xA2B4, 0xFF15,
+	0xA2B5, 0xFF16, 0xA2B6, 0xFF17, 0xA2B7, 0xFF18, 0xA2B8, 0xFF19,	0xA2B9, 0x2160, 0xA2BA, 0x2161, 0xA2BB, 0x2162, 0xA2BC, 0x2163,
+	0xA2BD, 0x2164, 0xA2BE, 0x2165, 0xA2BF, 0x2166, 0xA2C0, 0x2167,	0xA2C1, 0x2168, 0xA2C2, 0x2169, 0xA2C3, 0x3021, 0xA2C4, 0x3022,
+	0xA2C5, 0x3023, 0xA2C6, 0x3024, 0xA2C7, 0x3025, 0xA2C8, 0x3026,	0xA2C9, 0x3027, 0xA2CA, 0x3028, 0xA2CB, 0x3029, 0xA2CC, 0x5341,
+	0xA2CD, 0x5344, 0xA2CE, 0x5345, 0xA2CF, 0xFF21, 0xA2D0, 0xFF22,	0xA2D1, 0xFF23, 0xA2D2, 0xFF24, 0xA2D3, 0xFF25, 0xA2D4, 0xFF26,
+	0xA2D5, 0xFF27, 0xA2D6, 0xFF28, 0xA2D7, 0xFF29, 0xA2D8, 0xFF2A,	0xA2D9, 0xFF2B, 0xA2DA, 0xFF2C, 0xA2DB, 0xFF2D, 0xA2DC, 0xFF2E,
+	0xA2DD, 0xFF2F, 0xA2DE, 0xFF30, 0xA2DF, 0xFF31, 0xA2E0, 0xFF32,	0xA2E1, 0xFF33, 0xA2E2, 0xFF34, 0xA2E3, 0xFF35, 0xA2E4, 0xFF36,
+	0xA2E5, 0xFF37, 0xA2E6, 0xFF38, 0xA2E7, 0xFF39, 0xA2E8, 0xFF3A,	0xA2E9, 0xFF41, 0xA2EA, 0xFF42, 0xA2EB, 0xFF43, 0xA2EC, 0xFF44,
+	0xA2ED, 0xFF45, 0xA2EE, 0xFF46, 0xA2EF, 0xFF47, 0xA2F0, 0xFF48,	0xA2F1, 0xFF49, 0xA2F2, 0xFF4A, 0xA2F3, 0xFF4B, 0xA2F4, 0xFF4C,
+	0xA2F5, 0xFF4D, 0xA2F6, 0xFF4E, 0xA2F7, 0xFF4F, 0xA2F8, 0xFF50,	0xA2F9, 0xFF51, 0xA2FA, 0xFF52, 0xA2FB, 0xFF53, 0xA2FC, 0xFF54,
+	0xA2FD, 0xFF55, 0xA2FE, 0xFF56, 0xA340, 0xFF57, 0xA341, 0xFF58,	0xA342, 0xFF59, 0xA343, 0xFF5A, 0xA344, 0x0391, 0xA345, 0x0392,
+	0xA346, 0x0393, 0xA347, 0x0394, 0xA348, 0x0395, 0xA349, 0x0396,	0xA34A, 0x0397, 0xA34B, 0x0398, 0xA34C, 0x0399, 0xA34D, 0x039A,
+	0xA34E, 0x039B, 0xA34F, 0x039C, 0xA350, 0x039D, 0xA351, 0x039E,	0xA352, 0x039F, 0xA353, 0x03A0, 0xA354, 0x03A1, 0xA355, 0x03A3,
+	0xA356, 0x03A4, 0xA357, 0x03A5, 0xA358, 0x03A6, 0xA359, 0x03A7,	0xA35A, 0x03A8, 0xA35B, 0x03A9, 0xA35C, 0x03B1, 0xA35D, 0x03B2,
+	0xA35E, 0x03B3, 0xA35F, 0x03B4, 0xA360, 0x03B5, 0xA361, 0x03B6,	0xA362, 0x03B7, 0xA363, 0x03B8, 0xA364, 0x03B9, 0xA365, 0x03BA,
+	0xA366, 0x03BB, 0xA367, 0x03BC, 0xA368, 0x03BD, 0xA369, 0x03BE,	0xA36A, 0x03BF, 0xA36B, 0x03C0, 0xA36C, 0x03C1, 0xA36D, 0x03C3,
+	0xA36E, 0x03C4, 0xA36F, 0x03C5, 0xA370, 0x03C6, 0xA371, 0x03C7,	0xA372, 0x03C8, 0xA373, 0x03C9, 0xA374, 0x3105, 0xA375, 0x3106,
+	0xA376, 0x3107, 0xA377, 0x3108, 0xA378, 0x3109, 0xA379, 0x310A,	0xA37A, 0x310B, 0xA37B, 0x310C, 0xA37C, 0x310D, 0xA37D, 0x310E,
+	0xA37E, 0x310F, 0xA3A1, 0x3110, 0xA3A2, 0x3111, 0xA3A3, 0x3112,	0xA3A4, 0x3113, 0xA3A5, 0x3114, 0xA3A6, 0x3115, 0xA3A7, 0x3116,
+	0xA3A8, 0x3117, 0xA3A9, 0x3118, 0xA3AA, 0x3119, 0xA3AB, 0x311A,	0xA3AC, 0x311B, 0xA3AD, 0x311C, 0xA3AE, 0x311D, 0xA3AF, 0x311E,
+	0xA3B0, 0x311F, 0xA3B1, 0x3120, 0xA3B2, 0x3121, 0xA3B3, 0x3122,	0xA3B4, 0x3123, 0xA3B5, 0x3124, 0xA3B6, 0x3125, 0xA3B7, 0x3126,
+	0xA3B8, 0x3127, 0xA3B9, 0x3128, 0xA3BA, 0x3129, 0xA3BB, 0x02D9,	0xA3BC, 0x02C9, 0xA3BD, 0x02CA, 0xA3BE, 0x02C7, 0xA3BF, 0x02CB,
+	0xA3E1, 0x20AC, 0xA440, 0x4E00, 0xA441, 0x4E59, 0xA442, 0x4E01,	0xA443, 0x4E03, 0xA444, 0x4E43, 0xA445, 0x4E5D, 0xA446, 0x4E86,
+	0xA447, 0x4E8C, 0xA448, 0x4EBA, 0xA449, 0x513F, 0xA44A, 0x5165,	0xA44B, 0x516B, 0xA44C, 0x51E0, 0xA44D, 0x5200, 0xA44E, 0x5201,
+	0xA44F, 0x529B, 0xA450, 0x5315, 0xA451, 0x5341, 0xA452, 0x535C,	0xA453, 0x53C8, 0xA454, 0x4E09, 0xA455, 0x4E0B, 0xA456, 0x4E08,
+	0xA457, 0x4E0A, 0xA458, 0x4E2B, 0xA459, 0x4E38, 0xA45A, 0x51E1,	0xA45B, 0x4E45, 0xA45C, 0x4E48, 0xA45D, 0x4E5F, 0xA45E, 0x4E5E,
+	0xA45F, 0x4E8E, 0xA460, 0x4EA1, 0xA461, 0x5140, 0xA462, 0x5203,	0xA463, 0x52FA, 0xA464, 0x5343, 0xA465, 0x53C9, 0xA466, 0x53E3,
+	0xA467, 0x571F, 0xA468, 0x58EB, 0xA469, 0x5915, 0xA46A, 0x5927,	0xA46B, 0x5973, 0xA46C, 0x5B50, 0xA46D, 0x5B51, 0xA46E, 0x5B53,
+	0xA46F, 0x5BF8, 0xA470, 0x5C0F, 0xA471, 0x5C22, 0xA472, 0x5C38,	0xA473, 0x5C71, 0xA474, 0x5DDD, 0xA475, 0x5DE5, 0xA476, 0x5DF1,
+	0xA477, 0x5DF2, 0xA478, 0x5DF3, 0xA479, 0x5DFE, 0xA47A, 0x5E72,	0xA47B, 0x5EFE, 0xA47C, 0x5F0B, 0xA47D, 0x5F13, 0xA47E, 0x624D,
+	0xA4A1, 0x4E11, 0xA4A2, 0x4E10, 0xA4A3, 0x4E0D, 0xA4A4, 0x4E2D,	0xA4A5, 0x4E30, 0xA4A6, 0x4E39, 0xA4A7, 0x4E4B, 0xA4A8, 0x5C39,
+	0xA4A9, 0x4E88, 0xA4AA, 0x4E91, 0xA4AB, 0x4E95, 0xA4AC, 0x4E92,	0xA4AD, 0x4E94, 0xA4AE, 0x4EA2, 0xA4AF, 0x4EC1, 0xA4B0, 0x4EC0,
+	0xA4B1, 0x4EC3, 0xA4B2, 0x4EC6, 0xA4B3, 0x4EC7, 0xA4B4, 0x4ECD,	0xA4B5, 0x4ECA, 0xA4B6, 0x4ECB, 0xA4B7, 0x4EC4, 0xA4B8, 0x5143,
+	0xA4B9, 0x5141, 0xA4BA, 0x5167, 0xA4BB, 0x516D, 0xA4BC, 0x516E,	0xA4BD, 0x516C, 0xA4BE, 0x5197, 0xA4BF, 0x51F6, 0xA4C0, 0x5206,
+	0xA4C1, 0x5207, 0xA4C2, 0x5208, 0xA4C3, 0x52FB, 0xA4C4, 0x52FE,	0xA4C5, 0x52FF, 0xA4C6, 0x5316, 0xA4C7, 0x5339, 0xA4C8, 0x5348,
+	0xA4C9, 0x5347, 0xA4CA, 0x5345, 0xA4CB, 0x535E, 0xA4CC, 0x5384,	0xA4CD, 0x53CB, 0xA4CE, 0x53CA, 0xA4CF, 0x53CD, 0xA4D0, 0x58EC,
+	0xA4D1, 0x5929, 0xA4D2, 0x592B, 0xA4D3, 0x592A, 0xA4D4, 0x592D,	0xA4D5, 0x5B54, 0xA4D6, 0x5C11, 0xA4D7, 0x5C24, 0xA4D8, 0x5C3A,
+	0xA4D9, 0x5C6F, 0xA4DA, 0x5DF4, 0xA4DB, 0x5E7B, 0xA4DC, 0x5EFF,	0xA4DD, 0x5F14, 0xA4DE, 0x5F15, 0xA4DF, 0x5FC3, 0xA4E0, 0x6208,
+	0xA4E1, 0x6236, 0xA4E2, 0x624B, 0xA4E3, 0x624E, 0xA4E4, 0x652F,	0xA4E5, 0x6587, 0xA4E6, 0x6597, 0xA4E7, 0x65A4, 0xA4E8, 0x65B9,
+	0xA4E9, 0x65E5, 0xA4EA, 0x66F0, 0xA4EB, 0x6708, 0xA4EC, 0x6728,	0xA4ED, 0x6B20, 0xA4EE, 0x6B62, 0xA4EF, 0x6B79, 0xA4F0, 0x6BCB,
+	0xA4F1, 0x6BD4, 0xA4F2, 0x6BDB, 0xA4F3, 0x6C0F, 0xA4F4, 0x6C34,	0xA4F5, 0x706B, 0xA4F6, 0x722A, 0xA4F7, 0x7236, 0xA4F8, 0x723B,
+	0xA4F9, 0x7247, 0xA4FA, 0x7259, 0xA4FB, 0x725B, 0xA4FC, 0x72AC,	0xA4FD, 0x738B, 0xA4FE, 0x4E19, 0xA540, 0x4E16, 0xA541, 0x4E15,
+	0xA542, 0x4E14, 0xA543, 0x4E18, 0xA544, 0x4E3B, 0xA545, 0x4E4D,	0xA546, 0x4E4F, 0xA547, 0x4E4E, 0xA548, 0x4EE5, 0xA549, 0x4ED8,
+	0xA54A, 0x4ED4, 0xA54B, 0x4ED5, 0xA54C, 0x4ED6, 0xA54D, 0x4ED7,	0xA54E, 0x4EE3, 0xA54F, 0x4EE4, 0xA550, 0x4ED9, 0xA551, 0x4EDE,
+	0xA552, 0x5145, 0xA553, 0x5144, 0xA554, 0x5189, 0xA555, 0x518A,	0xA556, 0x51AC, 0xA557, 0x51F9, 0xA558, 0x51FA, 0xA559, 0x51F8,
+	0xA55A, 0x520A, 0xA55B, 0x52A0, 0xA55C, 0x529F, 0xA55D, 0x5305,	0xA55E, 0x5306, 0xA55F, 0x5317, 0xA560, 0x531D, 0xA561, 0x4EDF,
+	0xA562, 0x534A, 0xA563, 0x5349, 0xA564, 0x5361, 0xA565, 0x5360,	0xA566, 0x536F, 0xA567, 0x536E, 0xA568, 0x53BB, 0xA569, 0x53EF,
+	0xA56A, 0x53E4, 0xA56B, 0x53F3, 0xA56C, 0x53EC, 0xA56D, 0x53EE,	0xA56E, 0x53E9, 0xA56F, 0x53E8, 0xA570, 0x53FC, 0xA571, 0x53F8,
+	0xA572, 0x53F5, 0xA573, 0x53EB, 0xA574, 0x53E6, 0xA575, 0x53EA,	0xA576, 0x53F2, 0xA577, 0x53F1, 0xA578, 0x53F0, 0xA579, 0x53E5,
+	0xA57A, 0x53ED, 0xA57B, 0x53FB, 0xA57C, 0x56DB, 0xA57D, 0x56DA,	0xA57E, 0x5916, 0xA5A1, 0x592E, 0xA5A2, 0x5931, 0xA5A3, 0x5974,
+	0xA5A4, 0x5976, 0xA5A5, 0x5B55, 0xA5A6, 0x5B83, 0xA5A7, 0x5C3C,	0xA5A8, 0x5DE8, 0xA5A9, 0x5DE7, 0xA5AA, 0x5DE6, 0xA5AB, 0x5E02,
+	0xA5AC, 0x5E03, 0xA5AD, 0x5E73, 0xA5AE, 0x5E7C, 0xA5AF, 0x5F01,	0xA5B0, 0x5F18, 0xA5B1, 0x5F17, 0xA5B2, 0x5FC5, 0xA5B3, 0x620A,
+	0xA5B4, 0x6253, 0xA5B5, 0x6254, 0xA5B6, 0x6252, 0xA5B7, 0x6251,	0xA5B8, 0x65A5, 0xA5B9, 0x65E6, 0xA5BA, 0x672E, 0xA5BB, 0x672C,
+	0xA5BC, 0x672A, 0xA5BD, 0x672B, 0xA5BE, 0x672D, 0xA5BF, 0x6B63,	0xA5C0, 0x6BCD, 0xA5C1, 0x6C11, 0xA5C2, 0x6C10, 0xA5C3, 0x6C38,
+	0xA5C4, 0x6C41, 0xA5C5, 0x6C40, 0xA5C6, 0x6C3E, 0xA5C7, 0x72AF,	0xA5C8, 0x7384, 0xA5C9, 0x7389, 0xA5CA, 0x74DC, 0xA5CB, 0x74E6,
+	0xA5CC, 0x7518, 0xA5CD, 0x751F, 0xA5CE, 0x7528, 0xA5CF, 0x7529,	0xA5D0, 0x7530, 0xA5D1, 0x7531, 0xA5D2, 0x7532, 0xA5D3, 0x7533,
+	0xA5D4, 0x758B, 0xA5D5, 0x767D, 0xA5D6, 0x76AE, 0xA5D7, 0x76BF,	0xA5D8, 0x76EE, 0xA5D9, 0x77DB, 0xA5DA, 0x77E2, 0xA5DB, 0x77F3,
+	0xA5DC, 0x793A, 0xA5DD, 0x79BE, 0xA5DE, 0x7A74, 0xA5DF, 0x7ACB,	0xA5E0, 0x4E1E, 0xA5E1, 0x4E1F, 0xA5E2, 0x4E52, 0xA5E3, 0x4E53,
+	0xA5E4, 0x4E69, 0xA5E5, 0x4E99, 0xA5E6, 0x4EA4, 0xA5E7, 0x4EA6,	0xA5E8, 0x4EA5, 0xA5E9, 0x4EFF, 0xA5EA, 0x4F09, 0xA5EB, 0x4F19,
+	0xA5EC, 0x4F0A, 0xA5ED, 0x4F15, 0xA5EE, 0x4F0D, 0xA5EF, 0x4F10,	0xA5F0, 0x4F11, 0xA5F1, 0x4F0F, 0xA5F2, 0x4EF2, 0xA5F3, 0x4EF6,
+	0xA5F4, 0x4EFB, 0xA5F5, 0x4EF0, 0xA5F6, 0x4EF3, 0xA5F7, 0x4EFD,	0xA5F8, 0x4F01, 0xA5F9, 0x4F0B, 0xA5FA, 0x5149, 0xA5FB, 0x5147,
+	0xA5FC, 0x5146, 0xA5FD, 0x5148, 0xA5FE, 0x5168, 0xA640, 0x5171,	0xA641, 0x518D, 0xA642, 0x51B0, 0xA643, 0x5217, 0xA644, 0x5211,
+	0xA645, 0x5212, 0xA646, 0x520E, 0xA647, 0x5216, 0xA648, 0x52A3,	0xA649, 0x5308, 0xA64A, 0x5321, 0xA64B, 0x5320, 0xA64C, 0x5370,
+	0xA64D, 0x5371, 0xA64E, 0x5409, 0xA64F, 0x540F, 0xA650, 0x540C,	0xA651, 0x540A, 0xA652, 0x5410, 0xA653, 0x5401, 0xA654, 0x540B,
+	0xA655, 0x5404, 0xA656, 0x5411, 0xA657, 0x540D, 0xA658, 0x5408,	0xA659, 0x5403, 0xA65A, 0x540E, 0xA65B, 0x5406, 0xA65C, 0x5412,
+	0xA65D, 0x56E0, 0xA65E, 0x56DE, 0xA65F, 0x56DD, 0xA660, 0x5733,	0xA661, 0x5730, 0xA662, 0x5728, 0xA663, 0x572D, 0xA664, 0x572C,
+	0xA665, 0x572F, 0xA666, 0x5729, 0xA667, 0x5919, 0xA668, 0x591A,	0xA669, 0x5937, 0xA66A, 0x5938, 0xA66B, 0x5984, 0xA66C, 0x5978,
+	0xA66D, 0x5983, 0xA66E, 0x597D, 0xA66F, 0x5979, 0xA670, 0x5982,	0xA671, 0x5981, 0xA672, 0x5B57, 0xA673, 0x5B58, 0xA674, 0x5B87,
+	0xA675, 0x5B88, 0xA676, 0x5B85, 0xA677, 0x5B89, 0xA678, 0x5BFA,	0xA679, 0x5C16, 0xA67A, 0x5C79, 0xA67B, 0x5DDE, 0xA67C, 0x5E06,
+	0xA67D, 0x5E76, 0xA67E, 0x5E74, 0xA6A1, 0x5F0F, 0xA6A2, 0x5F1B,	0xA6A3, 0x5FD9, 0xA6A4, 0x5FD6, 0xA6A5, 0x620E, 0xA6A6, 0x620C,
+	0xA6A7, 0x620D, 0xA6A8, 0x6210, 0xA6A9, 0x6263, 0xA6AA, 0x625B,	0xA6AB, 0x6258, 0xA6AC, 0x6536, 0xA6AD, 0x65E9, 0xA6AE, 0x65E8,
+	0xA6AF, 0x65EC, 0xA6B0, 0x65ED, 0xA6B1, 0x66F2, 0xA6B2, 0x66F3,	0xA6B3, 0x6709, 0xA6B4, 0x673D, 0xA6B5, 0x6734, 0xA6B6, 0x6731,
+	0xA6B7, 0x6735, 0xA6B8, 0x6B21, 0xA6B9, 0x6B64, 0xA6BA, 0x6B7B,	0xA6BB, 0x6C16, 0xA6BC, 0x6C5D, 0xA6BD, 0x6C57, 0xA6BE, 0x6C59,
+	0xA6BF, 0x6C5F, 0xA6C0, 0x6C60, 0xA6C1, 0x6C50, 0xA6C2, 0x6C55,	0xA6C3, 0x6C61, 0xA6C4, 0x6C5B, 0xA6C5, 0x6C4D, 0xA6C6, 0x6C4E,
+	0xA6C7, 0x7070, 0xA6C8, 0x725F, 0xA6C9, 0x725D, 0xA6CA, 0x767E,	0xA6CB, 0x7AF9, 0xA6CC, 0x7C73, 0xA6CD, 0x7CF8, 0xA6CE, 0x7F36,
+	0xA6CF, 0x7F8A, 0xA6D0, 0x7FBD, 0xA6D1, 0x8001, 0xA6D2, 0x8003,	0xA6D3, 0x800C, 0xA6D4, 0x8012, 0xA6D5, 0x8033, 0xA6D6, 0x807F,
+	0xA6D7, 0x8089, 0xA6D8, 0x808B, 0xA6D9, 0x808C, 0xA6DA, 0x81E3,	0xA6DB, 0x81EA, 0xA6DC, 0x81F3, 0xA6DD, 0x81FC, 0xA6DE, 0x820C,
+	0xA6DF, 0x821B, 0xA6E0, 0x821F, 0xA6E1, 0x826E, 0xA6E2, 0x8272,	0xA6E3, 0x827E, 0xA6E4, 0x866B, 0xA6E5, 0x8840, 0xA6E6, 0x884C,
+	0xA6E7, 0x8863, 0xA6E8, 0x897F, 0xA6E9, 0x9621, 0xA6EA, 0x4E32,	0xA6EB, 0x4EA8, 0xA6EC, 0x4F4D, 0xA6ED, 0x4F4F, 0xA6EE, 0x4F47,
+	0xA6EF, 0x4F57, 0xA6F0, 0x4F5E, 0xA6F1, 0x4F34, 0xA6F2, 0x4F5B,	0xA6F3, 0x4F55, 0xA6F4, 0x4F30, 0xA6F5, 0x4F50, 0xA6F6, 0x4F51,
+	0xA6F7, 0x4F3D, 0xA6F8, 0x4F3A, 0xA6F9, 0x4F38, 0xA6FA, 0x4F43,	0xA6FB, 0x4F54, 0xA6FC, 0x4F3C, 0xA6FD, 0x4F46, 0xA6FE, 0x4F63,
+	0xA740, 0x4F5C, 0xA741, 0x4F60, 0xA742, 0x4F2F, 0xA743, 0x4F4E,	0xA744, 0x4F36, 0xA745, 0x4F59, 0xA746, 0x4F5D, 0xA747, 0x4F48,
+	0xA748, 0x4F5A, 0xA749, 0x514C, 0xA74A, 0x514B, 0xA74B, 0x514D,	0xA74C, 0x5175, 0xA74D, 0x51B6, 0xA74E, 0x51B7, 0xA74F, 0x5225,
+	0xA750, 0x5224, 0xA751, 0x5229, 0xA752, 0x522A, 0xA753, 0x5228,	0xA754, 0x52AB, 0xA755, 0x52A9, 0xA756, 0x52AA, 0xA757, 0x52AC,
+	0xA758, 0x5323, 0xA759, 0x5373, 0xA75A, 0x5375, 0xA75B, 0x541D,	0xA75C, 0x542D, 0xA75D, 0x541E, 0xA75E, 0x543E, 0xA75F, 0x5426,
+	0xA760, 0x544E, 0xA761, 0x5427, 0xA762, 0x5446, 0xA763, 0x5443,	0xA764, 0x5433, 0xA765, 0x5448, 0xA766, 0x5442, 0xA767, 0x541B,
+	0xA768, 0x5429, 0xA769, 0x544A, 0xA76A, 0x5439, 0xA76B, 0x543B,	0xA76C, 0x5438, 0xA76D, 0x542E, 0xA76E, 0x5435, 0xA76F, 0x5436,
+	0xA770, 0x5420, 0xA771, 0x543C, 0xA772, 0x5440, 0xA773, 0x5431,	0xA774, 0x542B, 0xA775, 0x541F, 0xA776, 0x542C, 0xA777, 0x56EA,
+	0xA778, 0x56F0, 0xA779, 0x56E4, 0xA77A, 0x56EB, 0xA77B, 0x574A,	0xA77C, 0x5751, 0xA77D, 0x5740, 0xA77E, 0x574D, 0xA7A1, 0x5747,
+	0xA7A2, 0x574E, 0xA7A3, 0x573E, 0xA7A4, 0x5750, 0xA7A5, 0x574F,	0xA7A6, 0x573B, 0xA7A7, 0x58EF, 0xA7A8, 0x593E, 0xA7A9, 0x599D,
+	0xA7AA, 0x5992, 0xA7AB, 0x59A8, 0xA7AC, 0x599E, 0xA7AD, 0x59A3,	0xA7AE, 0x5999, 0xA7AF, 0x5996, 0xA7B0, 0x598D, 0xA7B1, 0x59A4,
+	0xA7B2, 0x5993, 0xA7B3, 0x598A, 0xA7B4, 0x59A5, 0xA7B5, 0x5B5D,	0xA7B6, 0x5B5C, 0xA7B7, 0x5B5A, 0xA7B8, 0x5B5B, 0xA7B9, 0x5B8C,
+	0xA7BA, 0x5B8B, 0xA7BB, 0x5B8F, 0xA7BC, 0x5C2C, 0xA7BD, 0x5C40,	0xA7BE, 0x5C41, 0xA7BF, 0x5C3F, 0xA7C0, 0x5C3E, 0xA7C1, 0x5C90,
+	0xA7C2, 0x5C91, 0xA7C3, 0x5C94, 0xA7C4, 0x5C8C, 0xA7C5, 0x5DEB,	0xA7C6, 0x5E0C, 0xA7C7, 0x5E8F, 0xA7C8, 0x5E87, 0xA7C9, 0x5E8A,
+	0xA7CA, 0x5EF7, 0xA7CB, 0x5F04, 0xA7CC, 0x5F1F, 0xA7CD, 0x5F64,	0xA7CE, 0x5F62, 0xA7CF, 0x5F77, 0xA7D0, 0x5F79, 0xA7D1, 0x5FD8,
+	0xA7D2, 0x5FCC, 0xA7D3, 0x5FD7, 0xA7D4, 0x5FCD, 0xA7D5, 0x5FF1,	0xA7D6, 0x5FEB, 0xA7D7, 0x5FF8, 0xA7D8, 0x5FEA, 0xA7D9, 0x6212,
+	0xA7DA, 0x6211, 0xA7DB, 0x6284, 0xA7DC, 0x6297, 0xA7DD, 0x6296,	0xA7DE, 0x6280, 0xA7DF, 0x6276, 0xA7E0, 0x6289, 0xA7E1, 0x626D,
+	0xA7E2, 0x628A, 0xA7E3, 0x627C, 0xA7E4, 0x627E, 0xA7E5, 0x6279,	0xA7E6, 0x6273, 0xA7E7, 0x6292, 0xA7E8, 0x626F, 0xA7E9, 0x6298,
+	0xA7EA, 0x626E, 0xA7EB, 0x6295, 0xA7EC, 0x6293, 0xA7ED, 0x6291,	0xA7EE, 0x6286, 0xA7EF, 0x6539, 0xA7F0, 0x653B, 0xA7F1, 0x6538,
+	0xA7F2, 0x65F1, 0xA7F3, 0x66F4, 0xA7F4, 0x675F, 0xA7F5, 0x674E,	0xA7F6, 0x674F, 0xA7F7, 0x6750, 0xA7F8, 0x6751, 0xA7F9, 0x675C,
+	0xA7FA, 0x6756, 0xA7FB, 0x675E, 0xA7FC, 0x6749, 0xA7FD, 0x6746,	0xA7FE, 0x6760, 0xA840, 0x6753, 0xA841, 0x6757, 0xA842, 0x6B65,
+	0xA843, 0x6BCF, 0xA844, 0x6C42, 0xA845, 0x6C5E, 0xA846, 0x6C99,	0xA847, 0x6C81, 0xA848, 0x6C88, 0xA849, 0x6C89, 0xA84A, 0x6C85,
+	0xA84B, 0x6C9B, 0xA84C, 0x6C6A, 0xA84D, 0x6C7A, 0xA84E, 0x6C90,	0xA84F, 0x6C70, 0xA850, 0x6C8C, 0xA851, 0x6C68, 0xA852, 0x6C96,
+	0xA853, 0x6C92, 0xA854, 0x6C7D, 0xA855, 0x6C83, 0xA856, 0x6C72,	0xA857, 0x6C7E, 0xA858, 0x6C74, 0xA859, 0x6C86, 0xA85A, 0x6C76,
+	0xA85B, 0x6C8D, 0xA85C, 0x6C94, 0xA85D, 0x6C98, 0xA85E, 0x6C82,	0xA85F, 0x7076, 0xA860, 0x707C, 0xA861, 0x707D, 0xA862, 0x7078,
+	0xA863, 0x7262, 0xA864, 0x7261, 0xA865, 0x7260, 0xA866, 0x72C4,	0xA867, 0x72C2, 0xA868, 0x7396, 0xA869, 0x752C, 0xA86A, 0x752B,
+	0xA86B, 0x7537, 0xA86C, 0x7538, 0xA86D, 0x7682, 0xA86E, 0x76EF,	0xA86F, 0x77E3, 0xA870, 0x79C1, 0xA871, 0x79C0, 0xA872, 0x79BF,
+	0xA873, 0x7A76, 0xA874, 0x7CFB, 0xA875, 0x7F55, 0xA876, 0x8096,	0xA877, 0x8093, 0xA878, 0x809D, 0xA879, 0x8098, 0xA87A, 0x809B,
+	0xA87B, 0x809A, 0xA87C, 0x80B2, 0xA87D, 0x826F, 0xA87E, 0x8292,	0xA8A1, 0x828B, 0xA8A2, 0x828D, 0xA8A3, 0x898B, 0xA8A4, 0x89D2,
+	0xA8A5, 0x8A00, 0xA8A6, 0x8C37, 0xA8A7, 0x8C46, 0xA8A8, 0x8C55,	0xA8A9, 0x8C9D, 0xA8AA, 0x8D64, 0xA8AB, 0x8D70, 0xA8AC, 0x8DB3,
+	0xA8AD, 0x8EAB, 0xA8AE, 0x8ECA, 0xA8AF, 0x8F9B, 0xA8B0, 0x8FB0,	0xA8B1, 0x8FC2, 0xA8B2, 0x8FC6, 0xA8B3, 0x8FC5, 0xA8B4, 0x8FC4,
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+	0xAD72, 0x8A03, 0xAD73, 0x8C9E, 0xAD74, 0x8CA0, 0xAD75, 0x8D74,	0xAD76, 0x8D73, 0xAD77, 0x8DB4, 0xAD78, 0x8ECD, 0xAD79, 0x8ECC,
+	0xAD7A, 0x8FF0, 0xAD7B, 0x8FE6, 0xAD7C, 0x8FE2, 0xAD7D, 0x8FEA,	0xAD7E, 0x8FE5, 0xADA1, 0x8FED, 0xADA2, 0x8FEB, 0xADA3, 0x8FE4,
+	0xADA4, 0x8FE8, 0xADA5, 0x90CA, 0xADA6, 0x90CE, 0xADA7, 0x90C1,	0xADA8, 0x90C3, 0xADA9, 0x914B, 0xADAA, 0x914A, 0xADAB, 0x91CD,
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+	0xADB4, 0x97ED, 0xADB5, 0x97F3, 0xADB6, 0x9801, 0xADB7, 0x98A8,	0xADB8, 0x98DB, 0xADB9, 0x98DF, 0xADBA, 0x9996, 0xADBB, 0x9999,
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+	0xADCC, 0x5011, 0xADCD, 0x4FFA, 0xADCE, 0x5000, 0xADCF, 0x5014,	0xADD0, 0x5028, 0xADD1, 0x4FF1, 0xADD2, 0x5021, 0xADD3, 0x500B,
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+	0xADDC, 0x5009, 0xADDD, 0x517C, 0xADDE, 0x51A4, 0xADDF, 0x51A5,	0xADE0, 0x51A2, 0xADE1, 0x51CD, 0xADE2, 0x51CC, 0xADE3, 0x51C6,
+	0xADE4, 0x51CB, 0xADE5, 0x5256, 0xADE6, 0x525C, 0xADE7, 0x5254,	0xADE8, 0x525B, 0xADE9, 0x525D, 0xADEA, 0x532A, 0xADEB, 0x537F,
+	0xADEC, 0x539F, 0xADED, 0x539D, 0xADEE, 0x53DF, 0xADEF, 0x54E8,	0xADF0, 0x5510, 0xADF1, 0x5501, 0xADF2, 0x5537, 0xADF3, 0x54FC,
+	0xADF4, 0x54E5, 0xADF5, 0x54F2, 0xADF6, 0x5506, 0xADF7, 0x54FA,	0xADF8, 0x5514, 0xADF9, 0x54E9, 0xADFA, 0x54ED, 0xADFB, 0x54E1,
+	0xADFC, 0x5509, 0xADFD, 0x54EE, 0xADFE, 0x54EA, 0xAE40, 0x54E6,	0xAE41, 0x5527, 0xAE42, 0x5507, 0xAE43, 0x54FD, 0xAE44, 0x550F,
+	0xAE45, 0x5703, 0xAE46, 0x5704, 0xAE47, 0x57C2, 0xAE48, 0x57D4,	0xAE49, 0x57CB, 0xAE4A, 0x57C3, 0xAE4B, 0x5809, 0xAE4C, 0x590F,
+	0xAE4D, 0x5957, 0xAE4E, 0x5958, 0xAE4F, 0x595A, 0xAE50, 0x5A11,	0xAE51, 0x5A18, 0xAE52, 0x5A1C, 0xAE53, 0x5A1F, 0xAE54, 0x5A1B,
+	0xAE55, 0x5A13, 0xAE56, 0x59EC, 0xAE57, 0x5A20, 0xAE58, 0x5A23,	0xAE59, 0x5A29, 0xAE5A, 0x5A25, 0xAE5B, 0x5A0C, 0xAE5C, 0x5A09,
+	0xAE5D, 0x5B6B, 0xAE5E, 0x5C58, 0xAE5F, 0x5BB0, 0xAE60, 0x5BB3,	0xAE61, 0x5BB6, 0xAE62, 0x5BB4, 0xAE63, 0x5BAE, 0xAE64, 0x5BB5,
+	0xAE65, 0x5BB9, 0xAE66, 0x5BB8, 0xAE67, 0x5C04, 0xAE68, 0x5C51,	0xAE69, 0x5C55, 0xAE6A, 0x5C50, 0xAE6B, 0x5CED, 0xAE6C, 0x5CFD,
+	0xAE6D, 0x5CFB, 0xAE6E, 0x5CEA, 0xAE6F, 0x5CE8, 0xAE70, 0x5CF0,	0xAE71, 0x5CF6, 0xAE72, 0x5D01, 0xAE73, 0x5CF4, 0xAE74, 0x5DEE,
+	0xAE75, 0x5E2D, 0xAE76, 0x5E2B, 0xAE77, 0x5EAB, 0xAE78, 0x5EAD,	0xAE79, 0x5EA7, 0xAE7A, 0x5F31, 0xAE7B, 0x5F92, 0xAE7C, 0x5F91,
+	0xAE7D, 0x5F90, 0xAE7E, 0x6059, 0xAEA1, 0x6063, 0xAEA2, 0x6065,	0xAEA3, 0x6050, 0xAEA4, 0x6055, 0xAEA5, 0x606D, 0xAEA6, 0x6069,
+	0xAEA7, 0x606F, 0xAEA8, 0x6084, 0xAEA9, 0x609F, 0xAEAA, 0x609A,	0xAEAB, 0x608D, 0xAEAC, 0x6094, 0xAEAD, 0x608C, 0xAEAE, 0x6085,
+	0xAEAF, 0x6096, 0xAEB0, 0x6247, 0xAEB1, 0x62F3, 0xAEB2, 0x6308,	0xAEB3, 0x62FF, 0xAEB4, 0x634E, 0xAEB5, 0x633E, 0xAEB6, 0x632F,
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+	0xAEBF, 0x632A, 0xAEC0, 0x632B, 0xAEC1, 0x6328, 0xAEC2, 0x634D,	0xAEC3, 0x634C, 0xAEC4, 0x6548, 0xAEC5, 0x6549, 0xAEC6, 0x6599,
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+	0xAECF, 0x6645, 0xAED0, 0x6641, 0xAED1, 0x66F8, 0xAED2, 0x6714,	0xAED3, 0x6715, 0xAED4, 0x6717, 0xAED5, 0x6821, 0xAED6, 0x6838,
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+	0xAEEF, 0x6BB7, 0xAEF0, 0x6C23, 0xAEF1, 0x6C27, 0xAEF2, 0x6C28,	0xAEF3, 0x6C26, 0xAEF4, 0x6C24, 0xAEF5, 0x6CF0, 0xAEF6, 0x6D6A,
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+	0xAF40, 0x6D6C, 0xAF41, 0x6D89, 0xAF42, 0x6D6E, 0xAF43, 0x6D5A,	0xAF44, 0x6D74, 0xAF45, 0x6D69, 0xAF46, 0x6D8C, 0xAF47, 0x6D8A,
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+	0xAF70, 0x76B0, 0xAF71, 0x76CA, 0xAF72, 0x76CD, 0xAF73, 0x76CE,	0xAF74, 0x7729, 0xAF75, 0x771F, 0xAF76, 0x7720, 0xAF77, 0x7728,
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+	0xAFB2, 0x79DF, 0xAFB3, 0x79E6, 0xAFB4, 0x79E9, 0xAFB5, 0x79D8,	0xAFB6, 0x7A84, 0xAFB7, 0x7A88, 0xAFB8, 0x7AD9, 0xAFB9, 0x7B06,
+	0xAFBA, 0x7B11, 0xAFBB, 0x7C89, 0xAFBC, 0x7D21, 0xAFBD, 0x7D17,	0xAFBE, 0x7D0B, 0xAFBF, 0x7D0A, 0xAFC0, 0x7D20, 0xAFC1, 0x7D22,
+	0xAFC2, 0x7D14, 0xAFC3, 0x7D10, 0xAFC4, 0x7D15, 0xAFC5, 0x7D1A,	0xAFC6, 0x7D1C, 0xAFC7, 0x7D0D, 0xAFC8, 0x7D19, 0xAFC9, 0x7D1B,
+	0xAFCA, 0x7F3A, 0xAFCB, 0x7F5F, 0xAFCC, 0x7F94, 0xAFCD, 0x7FC5,	0xAFCE, 0x7FC1, 0xAFCF, 0x8006, 0xAFD0, 0x8018, 0xAFD1, 0x8015,
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+	0xAFDA, 0x80ED, 0xAFDB, 0x80F4, 0xAFDC, 0x8106, 0xAFDD, 0x80F8,	0xAFDE, 0x80F3, 0xAFDF, 0x8108, 0xAFE0, 0x80FD, 0xAFE1, 0x810A,
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+	0xB043, 0x8693, 0xB044, 0x86A4, 0xB045, 0x86A9, 0xB046, 0x868C,	0xB047, 0x86A3, 0xB048, 0x869C, 0xB049, 0x8870, 0xB04A, 0x8877,
+	0xB04B, 0x8881, 0xB04C, 0x8882, 0xB04D, 0x887D, 0xB04E, 0x8879,	0xB04F, 0x8A18, 0xB050, 0x8A10, 0xB051, 0x8A0E, 0xB052, 0x8A0C,
+	0xB053, 0x8A15, 0xB054, 0x8A0A, 0xB055, 0x8A17, 0xB056, 0x8A13,	0xB057, 0x8A16, 0xB058, 0x8A0F, 0xB059, 0x8A11, 0xB05A, 0x8C48,
+	0xB05B, 0x8C7A, 0xB05C, 0x8C79, 0xB05D, 0x8CA1, 0xB05E, 0x8CA2,	0xB05F, 0x8D77, 0xB060, 0x8EAC, 0xB061, 0x8ED2, 0xB062, 0x8ED4,
+	0xB063, 0x8ECF, 0xB064, 0x8FB1, 0xB065, 0x9001, 0xB066, 0x9006,	0xB067, 0x8FF7, 0xB068, 0x9000, 0xB069, 0x8FFA, 0xB06A, 0x8FF4,
+	0xB06B, 0x9003, 0xB06C, 0x8FFD, 0xB06D, 0x9005, 0xB06E, 0x8FF8,	0xB06F, 0x9095, 0xB070, 0x90E1, 0xB071, 0x90DD, 0xB072, 0x90E2,
+	0xB073, 0x9152, 0xB074, 0x914D, 0xB075, 0x914C, 0xB076, 0x91D8,	0xB077, 0x91DD, 0xB078, 0x91D7, 0xB079, 0x91DC, 0xB07A, 0x91D9,
+	0xB07B, 0x9583, 0xB07C, 0x9662, 0xB07D, 0x9663, 0xB07E, 0x9661,	0xB0A1, 0x965B, 0xB0A2, 0x965D, 0xB0A3, 0x9664, 0xB0A4, 0x9658,
+	0xB0A5, 0x965E, 0xB0A6, 0x96BB, 0xB0A7, 0x98E2, 0xB0A8, 0x99AC,	0xB0A9, 0x9AA8, 0xB0AA, 0x9AD8, 0xB0AB, 0x9B25, 0xB0AC, 0x9B32,
+	0xB0AD, 0x9B3C, 0xB0AE, 0x4E7E, 0xB0AF, 0x507A, 0xB0B0, 0x507D,	0xB0B1, 0x505C, 0xB0B2, 0x5047, 0xB0B3, 0x5043, 0xB0B4, 0x504C,
+	0xB0B5, 0x505A, 0xB0B6, 0x5049, 0xB0B7, 0x5065, 0xB0B8, 0x5076,	0xB0B9, 0x504E, 0xB0BA, 0x5055, 0xB0BB, 0x5075, 0xB0BC, 0x5074,
+	0xB0BD, 0x5077, 0xB0BE, 0x504F, 0xB0BF, 0x500F, 0xB0C0, 0x506F,	0xB0C1, 0x506D, 0xB0C2, 0x515C, 0xB0C3, 0x5195, 0xB0C4, 0x51F0,
+	0xB0C5, 0x526A, 0xB0C6, 0x526F, 0xB0C7, 0x52D2, 0xB0C8, 0x52D9,	0xB0C9, 0x52D8, 0xB0CA, 0x52D5, 0xB0CB, 0x5310, 0xB0CC, 0x530F,
+	0xB0CD, 0x5319, 0xB0CE, 0x533F, 0xB0CF, 0x5340, 0xB0D0, 0x533E,	0xB0D1, 0x53C3, 0xB0D2, 0x66FC, 0xB0D3, 0x5546, 0xB0D4, 0x556A,
+	0xB0D5, 0x5566, 0xB0D6, 0x5544, 0xB0D7, 0x555E, 0xB0D8, 0x5561,	0xB0D9, 0x5543, 0xB0DA, 0x554A, 0xB0DB, 0x5531, 0xB0DC, 0x5556,
+	0xB0DD, 0x554F, 0xB0DE, 0x5555, 0xB0DF, 0x552F, 0xB0E0, 0x5564,	0xB0E1, 0x5538, 0xB0E2, 0x552E, 0xB0E3, 0x555C, 0xB0E4, 0x552C,
+	0xB0E5, 0x5563, 0xB0E6, 0x5533, 0xB0E7, 0x5541, 0xB0E8, 0x5557,	0xB0E9, 0x5708, 0xB0EA, 0x570B, 0xB0EB, 0x5709, 0xB0EC, 0x57DF,
+	0xB0ED, 0x5805, 0xB0EE, 0x580A, 0xB0EF, 0x5806, 0xB0F0, 0x57E0,	0xB0F1, 0x57E4, 0xB0F2, 0x57FA, 0xB0F3, 0x5802, 0xB0F4, 0x5835,
+	0xB0F5, 0x57F7, 0xB0F6, 0x57F9, 0xB0F7, 0x5920, 0xB0F8, 0x5962,	0xB0F9, 0x5A36, 0xB0FA, 0x5A41, 0xB0FB, 0x5A49, 0xB0FC, 0x5A66,
+	0xB0FD, 0x5A6A, 0xB0FE, 0x5A40, 0xB140, 0x5A3C, 0xB141, 0x5A62,	0xB142, 0x5A5A, 0xB143, 0x5A46, 0xB144, 0x5A4A, 0xB145, 0x5B70,
+	0xB146, 0x5BC7, 0xB147, 0x5BC5, 0xB148, 0x5BC4, 0xB149, 0x5BC2,	0xB14A, 0x5BBF, 0xB14B, 0x5BC6, 0xB14C, 0x5C09, 0xB14D, 0x5C08,
+	0xB14E, 0x5C07, 0xB14F, 0x5C60, 0xB150, 0x5C5C, 0xB151, 0x5C5D,	0xB152, 0x5D07, 0xB153, 0x5D06, 0xB154, 0x5D0E, 0xB155, 0x5D1B,
+	0xB156, 0x5D16, 0xB157, 0x5D22, 0xB158, 0x5D11, 0xB159, 0x5D29,	0xB15A, 0x5D14, 0xB15B, 0x5D19, 0xB15C, 0x5D24, 0xB15D, 0x5D27,
+	0xB15E, 0x5D17, 0xB15F, 0x5DE2, 0xB160, 0x5E38, 0xB161, 0x5E36,	0xB162, 0x5E33, 0xB163, 0x5E37, 0xB164, 0x5EB7, 0xB165, 0x5EB8,
+	0xB166, 0x5EB6, 0xB167, 0x5EB5, 0xB168, 0x5EBE, 0xB169, 0x5F35,	0xB16A, 0x5F37, 0xB16B, 0x5F57, 0xB16C, 0x5F6C, 0xB16D, 0x5F69,
+	0xB16E, 0x5F6B, 0xB16F, 0x5F97, 0xB170, 0x5F99, 0xB171, 0x5F9E,	0xB172, 0x5F98, 0xB173, 0x5FA1, 0xB174, 0x5FA0, 0xB175, 0x5F9C,
+	0xB176, 0x607F, 0xB177, 0x60A3, 0xB178, 0x6089, 0xB179, 0x60A0,	0xB17A, 0x60A8, 0xB17B, 0x60CB, 0xB17C, 0x60B4, 0xB17D, 0x60E6,
+	0xB17E, 0x60BD, 0xB1A1, 0x60C5, 0xB1A2, 0x60BB, 0xB1A3, 0x60B5,	0xB1A4, 0x60DC, 0xB1A5, 0x60BC, 0xB1A6, 0x60D8, 0xB1A7, 0x60D5,
+	0xB1A8, 0x60C6, 0xB1A9, 0x60DF, 0xB1AA, 0x60B8, 0xB1AB, 0x60DA,	0xB1AC, 0x60C7, 0xB1AD, 0x621A, 0xB1AE, 0x621B, 0xB1AF, 0x6248,
+	0xB1B0, 0x63A0, 0xB1B1, 0x63A7, 0xB1B2, 0x6372, 0xB1B3, 0x6396,	0xB1B4, 0x63A2, 0xB1B5, 0x63A5, 0xB1B6, 0x6377, 0xB1B7, 0x6367,
+	0xB1B8, 0x6398, 0xB1B9, 0x63AA, 0xB1BA, 0x6371, 0xB1BB, 0x63A9,	0xB1BC, 0x6389, 0xB1BD, 0x6383, 0xB1BE, 0x639B, 0xB1BF, 0x636B,
+	0xB1C0, 0x63A8, 0xB1C1, 0x6384, 0xB1C2, 0x6388, 0xB1C3, 0x6399,	0xB1C4, 0x63A1, 0xB1C5, 0x63AC, 0xB1C6, 0x6392, 0xB1C7, 0x638F,
+	0xB1C8, 0x6380, 0xB1C9, 0x637B, 0xB1CA, 0x6369, 0xB1CB, 0x6368,	0xB1CC, 0x637A, 0xB1CD, 0x655D, 0xB1CE, 0x6556, 0xB1CF, 0x6551,
+	0xB1D0, 0x6559, 0xB1D1, 0x6557, 0xB1D2, 0x555F, 0xB1D3, 0x654F,	0xB1D4, 0x6558, 0xB1D5, 0x6555, 0xB1D6, 0x6554, 0xB1D7, 0x659C,
+	0xB1D8, 0x659B, 0xB1D9, 0x65AC, 0xB1DA, 0x65CF, 0xB1DB, 0x65CB,	0xB1DC, 0x65CC, 0xB1DD, 0x65CE, 0xB1DE, 0x665D, 0xB1DF, 0x665A,
+	0xB1E0, 0x6664, 0xB1E1, 0x6668, 0xB1E2, 0x6666, 0xB1E3, 0x665E,	0xB1E4, 0x66F9, 0xB1E5, 0x52D7, 0xB1E6, 0x671B, 0xB1E7, 0x6881,
+	0xB1E8, 0x68AF, 0xB1E9, 0x68A2, 0xB1EA, 0x6893, 0xB1EB, 0x68B5,	0xB1EC, 0x687F, 0xB1ED, 0x6876, 0xB1EE, 0x68B1, 0xB1EF, 0x68A7,
+	0xB1F0, 0x6897, 0xB1F1, 0x68B0, 0xB1F2, 0x6883, 0xB1F3, 0x68C4,	0xB1F4, 0x68AD, 0xB1F5, 0x6886, 0xB1F6, 0x6885, 0xB1F7, 0x6894,
+	0xB1F8, 0x689D, 0xB1F9, 0x68A8, 0xB1FA, 0x689F, 0xB1FB, 0x68A1,	0xB1FC, 0x6882, 0xB1FD, 0x6B32, 0xB1FE, 0x6BBA, 0xB240, 0x6BEB,
+	0xB241, 0x6BEC, 0xB242, 0x6C2B, 0xB243, 0x6D8E, 0xB244, 0x6DBC,	0xB245, 0x6DF3, 0xB246, 0x6DD9, 0xB247, 0x6DB2, 0xB248, 0x6DE1,
+	0xB249, 0x6DCC, 0xB24A, 0x6DE4, 0xB24B, 0x6DFB, 0xB24C, 0x6DFA,	0xB24D, 0x6E05, 0xB24E, 0x6DC7, 0xB24F, 0x6DCB, 0xB250, 0x6DAF,
+	0xB251, 0x6DD1, 0xB252, 0x6DAE, 0xB253, 0x6DDE, 0xB254, 0x6DF9,	0xB255, 0x6DB8, 0xB256, 0x6DF7, 0xB257, 0x6DF5, 0xB258, 0x6DC5,
+	0xB259, 0x6DD2, 0xB25A, 0x6E1A, 0xB25B, 0x6DB5, 0xB25C, 0x6DDA,	0xB25D, 0x6DEB, 0xB25E, 0x6DD8, 0xB25F, 0x6DEA, 0xB260, 0x6DF1,
+	0xB261, 0x6DEE, 0xB262, 0x6DE8, 0xB263, 0x6DC6, 0xB264, 0x6DC4,	0xB265, 0x6DAA, 0xB266, 0x6DEC, 0xB267, 0x6DBF, 0xB268, 0x6DE6,
+	0xB269, 0x70F9, 0xB26A, 0x7109, 0xB26B, 0x710A, 0xB26C, 0x70FD,	0xB26D, 0x70EF, 0xB26E, 0x723D, 0xB26F, 0x727D, 0xB270, 0x7281,
+	0xB271, 0x731C, 0xB272, 0x731B, 0xB273, 0x7316, 0xB274, 0x7313,	0xB275, 0x7319, 0xB276, 0x7387, 0xB277, 0x7405, 0xB278, 0x740A,
+	0xB279, 0x7403, 0xB27A, 0x7406, 0xB27B, 0x73FE, 0xB27C, 0x740D,	0xB27D, 0x74E0, 0xB27E, 0x74F6, 0xB2A1, 0x74F7, 0xB2A2, 0x751C,
+	0xB2A3, 0x7522, 0xB2A4, 0x7565, 0xB2A5, 0x7566, 0xB2A6, 0x7562,	0xB2A7, 0x7570, 0xB2A8, 0x758F, 0xB2A9, 0x75D4, 0xB2AA, 0x75D5,
+	0xB2AB, 0x75B5, 0xB2AC, 0x75CA, 0xB2AD, 0x75CD, 0xB2AE, 0x768E,	0xB2AF, 0x76D4, 0xB2B0, 0x76D2, 0xB2B1, 0x76DB, 0xB2B2, 0x7737,
+	0xB2B3, 0x773E, 0xB2B4, 0x773C, 0xB2B5, 0x7736, 0xB2B6, 0x7738,	0xB2B7, 0x773A, 0xB2B8, 0x786B, 0xB2B9, 0x7843, 0xB2BA, 0x784E,
+	0xB2BB, 0x7965, 0xB2BC, 0x7968, 0xB2BD, 0x796D, 0xB2BE, 0x79FB,	0xB2BF, 0x7A92, 0xB2C0, 0x7A95, 0xB2C1, 0x7B20, 0xB2C2, 0x7B28,
+	0xB2C3, 0x7B1B, 0xB2C4, 0x7B2C, 0xB2C5, 0x7B26, 0xB2C6, 0x7B19,	0xB2C7, 0x7B1E, 0xB2C8, 0x7B2E, 0xB2C9, 0x7C92, 0xB2CA, 0x7C97,
+	0xB2CB, 0x7C95, 0xB2CC, 0x7D46, 0xB2CD, 0x7D43, 0xB2CE, 0x7D71,	0xB2CF, 0x7D2E, 0xB2D0, 0x7D39, 0xB2D1, 0x7D3C, 0xB2D2, 0x7D40,
+	0xB2D3, 0x7D30, 0xB2D4, 0x7D33, 0xB2D5, 0x7D44, 0xB2D6, 0x7D2F,	0xB2D7, 0x7D42, 0xB2D8, 0x7D32, 0xB2D9, 0x7D31, 0xB2DA, 0x7F3D,
+	0xB2DB, 0x7F9E, 0xB2DC, 0x7F9A, 0xB2DD, 0x7FCC, 0xB2DE, 0x7FCE,	0xB2DF, 0x7FD2, 0xB2E0, 0x801C, 0xB2E1, 0x804A, 0xB2E2, 0x8046,
+	0xB2E3, 0x812F, 0xB2E4, 0x8116, 0xB2E5, 0x8123, 0xB2E6, 0x812B,	0xB2E7, 0x8129, 0xB2E8, 0x8130, 0xB2E9, 0x8124, 0xB2EA, 0x8202,
+	0xB2EB, 0x8235, 0xB2EC, 0x8237, 0xB2ED, 0x8236, 0xB2EE, 0x8239,	0xB2EF, 0x838E, 0xB2F0, 0x839E, 0xB2F1, 0x8398, 0xB2F2, 0x8378,
+	0xB2F3, 0x83A2, 0xB2F4, 0x8396, 0xB2F5, 0x83BD, 0xB2F6, 0x83AB,	0xB2F7, 0x8392, 0xB2F8, 0x838A, 0xB2F9, 0x8393, 0xB2FA, 0x8389,
+	0xB2FB, 0x83A0, 0xB2FC, 0x8377, 0xB2FD, 0x837B, 0xB2FE, 0x837C,	0xB340, 0x8386, 0xB341, 0x83A7, 0xB342, 0x8655, 0xB343, 0x5F6A,
+	0xB344, 0x86C7, 0xB345, 0x86C0, 0xB346, 0x86B6, 0xB347, 0x86C4,	0xB348, 0x86B5, 0xB349, 0x86C6, 0xB34A, 0x86CB, 0xB34B, 0x86B1,
+	0xB34C, 0x86AF, 0xB34D, 0x86C9, 0xB34E, 0x8853, 0xB34F, 0x889E,	0xB350, 0x8888, 0xB351, 0x88AB, 0xB352, 0x8892, 0xB353, 0x8896,
+	0xB354, 0x888D, 0xB355, 0x888B, 0xB356, 0x8993, 0xB357, 0x898F,	0xB358, 0x8A2A, 0xB359, 0x8A1D, 0xB35A, 0x8A23, 0xB35B, 0x8A25,
+	0xB35C, 0x8A31, 0xB35D, 0x8A2D, 0xB35E, 0x8A1F, 0xB35F, 0x8A1B,	0xB360, 0x8A22, 0xB361, 0x8C49, 0xB362, 0x8C5A, 0xB363, 0x8CA9,
+	0xB364, 0x8CAC, 0xB365, 0x8CAB, 0xB366, 0x8CA8, 0xB367, 0x8CAA,	0xB368, 0x8CA7, 0xB369, 0x8D67, 0xB36A, 0x8D66, 0xB36B, 0x8DBE,
+	0xB36C, 0x8DBA, 0xB36D, 0x8EDB, 0xB36E, 0x8EDF, 0xB36F, 0x9019,	0xB370, 0x900D, 0xB371, 0x901A, 0xB372, 0x9017, 0xB373, 0x9023,
+	0xB374, 0x901F, 0xB375, 0x901D, 0xB376, 0x9010, 0xB377, 0x9015,	0xB378, 0x901E, 0xB379, 0x9020, 0xB37A, 0x900F, 0xB37B, 0x9022,
+	0xB37C, 0x9016, 0xB37D, 0x901B, 0xB37E, 0x9014, 0xB3A1, 0x90E8,	0xB3A2, 0x90ED, 0xB3A3, 0x90FD, 0xB3A4, 0x9157, 0xB3A5, 0x91CE,
+	0xB3A6, 0x91F5, 0xB3A7, 0x91E6, 0xB3A8, 0x91E3, 0xB3A9, 0x91E7,	0xB3AA, 0x91ED, 0xB3AB, 0x91E9, 0xB3AC, 0x9589, 0xB3AD, 0x966A,
+	0xB3AE, 0x9675, 0xB3AF, 0x9673, 0xB3B0, 0x9678, 0xB3B1, 0x9670,	0xB3B2, 0x9674, 0xB3B3, 0x9676, 0xB3B4, 0x9677, 0xB3B5, 0x966C,
+	0xB3B6, 0x96C0, 0xB3B7, 0x96EA, 0xB3B8, 0x96E9, 0xB3B9, 0x7AE0,	0xB3BA, 0x7ADF, 0xB3BB, 0x9802, 0xB3BC, 0x9803, 0xB3BD, 0x9B5A,
+	0xB3BE, 0x9CE5, 0xB3BF, 0x9E75, 0xB3C0, 0x9E7F, 0xB3C1, 0x9EA5,	0xB3C2, 0x9EBB, 0xB3C3, 0x50A2, 0xB3C4, 0x508D, 0xB3C5, 0x5085,
+	0xB3C6, 0x5099, 0xB3C7, 0x5091, 0xB3C8, 0x5080, 0xB3C9, 0x5096,	0xB3CA, 0x5098, 0xB3CB, 0x509A, 0xB3CC, 0x6700, 0xB3CD, 0x51F1,
+	0xB3CE, 0x5272, 0xB3CF, 0x5274, 0xB3D0, 0x5275, 0xB3D1, 0x5269,	0xB3D2, 0x52DE, 0xB3D3, 0x52DD, 0xB3D4, 0x52DB, 0xB3D5, 0x535A,
+	0xB3D6, 0x53A5, 0xB3D7, 0x557B, 0xB3D8, 0x5580, 0xB3D9, 0x55A7,	0xB3DA, 0x557C, 0xB3DB, 0x558A, 0xB3DC, 0x559D, 0xB3DD, 0x5598,
+	0xB3DE, 0x5582, 0xB3DF, 0x559C, 0xB3E0, 0x55AA, 0xB3E1, 0x5594,	0xB3E2, 0x5587, 0xB3E3, 0x558B, 0xB3E4, 0x5583, 0xB3E5, 0x55B3,
+	0xB3E6, 0x55AE, 0xB3E7, 0x559F, 0xB3E8, 0x553E, 0xB3E9, 0x55B2,	0xB3EA, 0x559A, 0xB3EB, 0x55BB, 0xB3EC, 0x55AC, 0xB3ED, 0x55B1,
+	0xB3EE, 0x557E, 0xB3EF, 0x5589, 0xB3F0, 0x55AB, 0xB3F1, 0x5599,	0xB3F2, 0x570D, 0xB3F3, 0x582F, 0xB3F4, 0x582A, 0xB3F5, 0x5834,
+	0xB3F6, 0x5824, 0xB3F7, 0x5830, 0xB3F8, 0x5831, 0xB3F9, 0x5821,	0xB3FA, 0x581D, 0xB3FB, 0x5820, 0xB3FC, 0x58F9, 0xB3FD, 0x58FA,
+	0xB3FE, 0x5960, 0xB440, 0x5A77, 0xB441, 0x5A9A, 0xB442, 0x5A7F,	0xB443, 0x5A92, 0xB444, 0x5A9B, 0xB445, 0x5AA7, 0xB446, 0x5B73,
+	0xB447, 0x5B71, 0xB448, 0x5BD2, 0xB449, 0x5BCC, 0xB44A, 0x5BD3,	0xB44B, 0x5BD0, 0xB44C, 0x5C0A, 0xB44D, 0x5C0B, 0xB44E, 0x5C31,
+	0xB44F, 0x5D4C, 0xB450, 0x5D50, 0xB451, 0x5D34, 0xB452, 0x5D47,	0xB453, 0x5DFD, 0xB454, 0x5E45, 0xB455, 0x5E3D, 0xB456, 0x5E40,
+	0xB457, 0x5E43, 0xB458, 0x5E7E, 0xB459, 0x5ECA, 0xB45A, 0x5EC1,	0xB45B, 0x5EC2, 0xB45C, 0x5EC4, 0xB45D, 0x5F3C, 0xB45E, 0x5F6D,
+	0xB45F, 0x5FA9, 0xB460, 0x5FAA, 0xB461, 0x5FA8, 0xB462, 0x60D1,	0xB463, 0x60E1, 0xB464, 0x60B2, 0xB465, 0x60B6, 0xB466, 0x60E0,
+	0xB467, 0x611C, 0xB468, 0x6123, 0xB469, 0x60FA, 0xB46A, 0x6115,	0xB46B, 0x60F0, 0xB46C, 0x60FB, 0xB46D, 0x60F4, 0xB46E, 0x6168,
+	0xB46F, 0x60F1, 0xB470, 0x610E, 0xB471, 0x60F6, 0xB472, 0x6109,	0xB473, 0x6100, 0xB474, 0x6112, 0xB475, 0x621F, 0xB476, 0x6249,
+	0xB477, 0x63A3, 0xB478, 0x638C, 0xB479, 0x63CF, 0xB47A, 0x63C0,	0xB47B, 0x63E9, 0xB47C, 0x63C9, 0xB47D, 0x63C6, 0xB47E, 0x63CD,
+	0xB4A1, 0x63D2, 0xB4A2, 0x63E3, 0xB4A3, 0x63D0, 0xB4A4, 0x63E1,	0xB4A5, 0x63D6, 0xB4A6, 0x63ED, 0xB4A7, 0x63EE, 0xB4A8, 0x6376,
+	0xB4A9, 0x63F4, 0xB4AA, 0x63EA, 0xB4AB, 0x63DB, 0xB4AC, 0x6452,	0xB4AD, 0x63DA, 0xB4AE, 0x63F9, 0xB4AF, 0x655E, 0xB4B0, 0x6566,
+	0xB4B1, 0x6562, 0xB4B2, 0x6563, 0xB4B3, 0x6591, 0xB4B4, 0x6590,	0xB4B5, 0x65AF, 0xB4B6, 0x666E, 0xB4B7, 0x6670, 0xB4B8, 0x6674,
+	0xB4B9, 0x6676, 0xB4BA, 0x666F, 0xB4BB, 0x6691, 0xB4BC, 0x667A,	0xB4BD, 0x667E, 0xB4BE, 0x6677, 0xB4BF, 0x66FE, 0xB4C0, 0x66FF,
+	0xB4C1, 0x671F, 0xB4C2, 0x671D, 0xB4C3, 0x68FA, 0xB4C4, 0x68D5,	0xB4C5, 0x68E0, 0xB4C6, 0x68D8, 0xB4C7, 0x68D7, 0xB4C8, 0x6905,
+	0xB4C9, 0x68DF, 0xB4CA, 0x68F5, 0xB4CB, 0x68EE, 0xB4CC, 0x68E7,	0xB4CD, 0x68F9, 0xB4CE, 0x68D2, 0xB4CF, 0x68F2, 0xB4D0, 0x68E3,
+	0xB4D1, 0x68CB, 0xB4D2, 0x68CD, 0xB4D3, 0x690D, 0xB4D4, 0x6912,	0xB4D5, 0x690E, 0xB4D6, 0x68C9, 0xB4D7, 0x68DA, 0xB4D8, 0x696E,
+	0xB4D9, 0x68FB, 0xB4DA, 0x6B3E, 0xB4DB, 0x6B3A, 0xB4DC, 0x6B3D,	0xB4DD, 0x6B98, 0xB4DE, 0x6B96, 0xB4DF, 0x6BBC, 0xB4E0, 0x6BEF,
+	0xB4E1, 0x6C2E, 0xB4E2, 0x6C2F, 0xB4E3, 0x6C2C, 0xB4E4, 0x6E2F,	0xB4E5, 0x6E38, 0xB4E6, 0x6E54, 0xB4E7, 0x6E21, 0xB4E8, 0x6E32,
+	0xB4E9, 0x6E67, 0xB4EA, 0x6E4A, 0xB4EB, 0x6E20, 0xB4EC, 0x6E25,	0xB4ED, 0x6E23, 0xB4EE, 0x6E1B, 0xB4EF, 0x6E5B, 0xB4F0, 0x6E58,
+	0xB4F1, 0x6E24, 0xB4F2, 0x6E56, 0xB4F3, 0x6E6E, 0xB4F4, 0x6E2D,	0xB4F5, 0x6E26, 0xB4F6, 0x6E6F, 0xB4F7, 0x6E34, 0xB4F8, 0x6E4D,
+	0xB4F9, 0x6E3A, 0xB4FA, 0x6E2C, 0xB4FB, 0x6E43, 0xB4FC, 0x6E1D,	0xB4FD, 0x6E3E, 0xB4FE, 0x6ECB, 0xB540, 0x6E89, 0xB541, 0x6E19,
+	0xB542, 0x6E4E, 0xB543, 0x6E63, 0xB544, 0x6E44, 0xB545, 0x6E72,	0xB546, 0x6E69, 0xB547, 0x6E5F, 0xB548, 0x7119, 0xB549, 0x711A,
+	0xB54A, 0x7126, 0xB54B, 0x7130, 0xB54C, 0x7121, 0xB54D, 0x7136,	0xB54E, 0x716E, 0xB54F, 0x711C, 0xB550, 0x724C, 0xB551, 0x7284,
+	0xB552, 0x7280, 0xB553, 0x7336, 0xB554, 0x7325, 0xB555, 0x7334,	0xB556, 0x7329, 0xB557, 0x743A, 0xB558, 0x742A, 0xB559, 0x7433,
+	0xB55A, 0x7422, 0xB55B, 0x7425, 0xB55C, 0x7435, 0xB55D, 0x7436,	0xB55E, 0x7434, 0xB55F, 0x742F, 0xB560, 0x741B, 0xB561, 0x7426,
+	0xB562, 0x7428, 0xB563, 0x7525, 0xB564, 0x7526, 0xB565, 0x756B,	0xB566, 0x756A, 0xB567, 0x75E2, 0xB568, 0x75DB, 0xB569, 0x75E3,
+	0xB56A, 0x75D9, 0xB56B, 0x75D8, 0xB56C, 0x75DE, 0xB56D, 0x75E0,	0xB56E, 0x767B, 0xB56F, 0x767C, 0xB570, 0x7696, 0xB571, 0x7693,
+	0xB572, 0x76B4, 0xB573, 0x76DC, 0xB574, 0x774F, 0xB575, 0x77ED,	0xB576, 0x785D, 0xB577, 0x786C, 0xB578, 0x786F, 0xB579, 0x7A0D,
+	0xB57A, 0x7A08, 0xB57B, 0x7A0B, 0xB57C, 0x7A05, 0xB57D, 0x7A00,	0xB57E, 0x7A98, 0xB5A1, 0x7A97, 0xB5A2, 0x7A96, 0xB5A3, 0x7AE5,
+	0xB5A4, 0x7AE3, 0xB5A5, 0x7B49, 0xB5A6, 0x7B56, 0xB5A7, 0x7B46,	0xB5A8, 0x7B50, 0xB5A9, 0x7B52, 0xB5AA, 0x7B54, 0xB5AB, 0x7B4D,
+	0xB5AC, 0x7B4B, 0xB5AD, 0x7B4F, 0xB5AE, 0x7B51, 0xB5AF, 0x7C9F,	0xB5B0, 0x7CA5, 0xB5B1, 0x7D5E, 0xB5B2, 0x7D50, 0xB5B3, 0x7D68,
+	0xB5B4, 0x7D55, 0xB5B5, 0x7D2B, 0xB5B6, 0x7D6E, 0xB5B7, 0x7D72,	0xB5B8, 0x7D61, 0xB5B9, 0x7D66, 0xB5BA, 0x7D62, 0xB5BB, 0x7D70,
+	0xB5BC, 0x7D73, 0xB5BD, 0x5584, 0xB5BE, 0x7FD4, 0xB5BF, 0x7FD5,	0xB5C0, 0x800B, 0xB5C1, 0x8052, 0xB5C2, 0x8085, 0xB5C3, 0x8155,
+	0xB5C4, 0x8154, 0xB5C5, 0x814B, 0xB5C6, 0x8151, 0xB5C7, 0x814E,	0xB5C8, 0x8139, 0xB5C9, 0x8146, 0xB5CA, 0x813E, 0xB5CB, 0x814C,
+	0xB5CC, 0x8153, 0xB5CD, 0x8174, 0xB5CE, 0x8212, 0xB5CF, 0x821C,	0xB5D0, 0x83E9, 0xB5D1, 0x8403, 0xB5D2, 0x83F8, 0xB5D3, 0x840D,
+	0xB5D4, 0x83E0, 0xB5D5, 0x83C5, 0xB5D6, 0x840B, 0xB5D7, 0x83C1,	0xB5D8, 0x83EF, 0xB5D9, 0x83F1, 0xB5DA, 0x83F4, 0xB5DB, 0x8457,
+	0xB5DC, 0x840A, 0xB5DD, 0x83F0, 0xB5DE, 0x840C, 0xB5DF, 0x83CC,	0xB5E0, 0x83FD, 0xB5E1, 0x83F2, 0xB5E2, 0x83CA, 0xB5E3, 0x8438,
+	0xB5E4, 0x840E, 0xB5E5, 0x8404, 0xB5E6, 0x83DC, 0xB5E7, 0x8407,	0xB5E8, 0x83D4, 0xB5E9, 0x83DF, 0xB5EA, 0x865B, 0xB5EB, 0x86DF,
+	0xB5EC, 0x86D9, 0xB5ED, 0x86ED, 0xB5EE, 0x86D4, 0xB5EF, 0x86DB,	0xB5F0, 0x86E4, 0xB5F1, 0x86D0, 0xB5F2, 0x86DE, 0xB5F3, 0x8857,
+	0xB5F4, 0x88C1, 0xB5F5, 0x88C2, 0xB5F6, 0x88B1, 0xB5F7, 0x8983,	0xB5F8, 0x8996, 0xB5F9, 0x8A3B, 0xB5FA, 0x8A60, 0xB5FB, 0x8A55,
+	0xB5FC, 0x8A5E, 0xB5FD, 0x8A3C, 0xB5FE, 0x8A41, 0xB640, 0x8A54,	0xB641, 0x8A5B, 0xB642, 0x8A50, 0xB643, 0x8A46, 0xB644, 0x8A34,
+	0xB645, 0x8A3A, 0xB646, 0x8A36, 0xB647, 0x8A56, 0xB648, 0x8C61,	0xB649, 0x8C82, 0xB64A, 0x8CAF, 0xB64B, 0x8CBC, 0xB64C, 0x8CB3,
+	0xB64D, 0x8CBD, 0xB64E, 0x8CC1, 0xB64F, 0x8CBB, 0xB650, 0x8CC0,	0xB651, 0x8CB4, 0xB652, 0x8CB7, 0xB653, 0x8CB6, 0xB654, 0x8CBF,
+	0xB655, 0x8CB8, 0xB656, 0x8D8A, 0xB657, 0x8D85, 0xB658, 0x8D81,	0xB659, 0x8DCE, 0xB65A, 0x8DDD, 0xB65B, 0x8DCB, 0xB65C, 0x8DDA,
+	0xB65D, 0x8DD1, 0xB65E, 0x8DCC, 0xB65F, 0x8DDB, 0xB660, 0x8DC6,	0xB661, 0x8EFB, 0xB662, 0x8EF8, 0xB663, 0x8EFC, 0xB664, 0x8F9C,
+	0xB665, 0x902E, 0xB666, 0x9035, 0xB667, 0x9031, 0xB668, 0x9038,	0xB669, 0x9032, 0xB66A, 0x9036, 0xB66B, 0x9102, 0xB66C, 0x90F5,
+	0xB66D, 0x9109, 0xB66E, 0x90FE, 0xB66F, 0x9163, 0xB670, 0x9165,	0xB671, 0x91CF, 0xB672, 0x9214, 0xB673, 0x9215, 0xB674, 0x9223,
+	0xB675, 0x9209, 0xB676, 0x921E, 0xB677, 0x920D, 0xB678, 0x9210,	0xB679, 0x9207, 0xB67A, 0x9211, 0xB67B, 0x9594, 0xB67C, 0x958F,
+	0xB67D, 0x958B, 0xB67E, 0x9591, 0xB6A1, 0x9593, 0xB6A2, 0x9592,	0xB6A3, 0x958E, 0xB6A4, 0x968A, 0xB6A5, 0x968E, 0xB6A6, 0x968B,
+	0xB6A7, 0x967D, 0xB6A8, 0x9685, 0xB6A9, 0x9686, 0xB6AA, 0x968D,	0xB6AB, 0x9672, 0xB6AC, 0x9684, 0xB6AD, 0x96C1, 0xB6AE, 0x96C5,
+	0xB6AF, 0x96C4, 0xB6B0, 0x96C6, 0xB6B1, 0x96C7, 0xB6B2, 0x96EF,	0xB6B3, 0x96F2, 0xB6B4, 0x97CC, 0xB6B5, 0x9805, 0xB6B6, 0x9806,
+	0xB6B7, 0x9808, 0xB6B8, 0x98E7, 0xB6B9, 0x98EA, 0xB6BA, 0x98EF,	0xB6BB, 0x98E9, 0xB6BC, 0x98F2, 0xB6BD, 0x98ED, 0xB6BE, 0x99AE,
+	0xB6BF, 0x99AD, 0xB6C0, 0x9EC3, 0xB6C1, 0x9ECD, 0xB6C2, 0x9ED1,	0xB6C3, 0x4E82, 0xB6C4, 0x50AD, 0xB6C5, 0x50B5, 0xB6C6, 0x50B2,
+	0xB6C7, 0x50B3, 0xB6C8, 0x50C5, 0xB6C9, 0x50BE, 0xB6CA, 0x50AC,	0xB6CB, 0x50B7, 0xB6CC, 0x50BB, 0xB6CD, 0x50AF, 0xB6CE, 0x50C7,
+	0xB6CF, 0x527F, 0xB6D0, 0x5277, 0xB6D1, 0x527D, 0xB6D2, 0x52DF,	0xB6D3, 0x52E6, 0xB6D4, 0x52E4, 0xB6D5, 0x52E2, 0xB6D6, 0x52E3,
+	0xB6D7, 0x532F, 0xB6D8, 0x55DF, 0xB6D9, 0x55E8, 0xB6DA, 0x55D3,	0xB6DB, 0x55E6, 0xB6DC, 0x55CE, 0xB6DD, 0x55DC, 0xB6DE, 0x55C7,
+	0xB6DF, 0x55D1, 0xB6E0, 0x55E3, 0xB6E1, 0x55E4, 0xB6E2, 0x55EF,	0xB6E3, 0x55DA, 0xB6E4, 0x55E1, 0xB6E5, 0x55C5, 0xB6E6, 0x55C6,
+	0xB6E7, 0x55E5, 0xB6E8, 0x55C9, 0xB6E9, 0x5712, 0xB6EA, 0x5713,	0xB6EB, 0x585E, 0xB6EC, 0x5851, 0xB6ED, 0x5858, 0xB6EE, 0x5857,
+	0xB6EF, 0x585A, 0xB6F0, 0x5854, 0xB6F1, 0x586B, 0xB6F2, 0x584C,	0xB6F3, 0x586D, 0xB6F4, 0x584A, 0xB6F5, 0x5862, 0xB6F6, 0x5852,
+	0xB6F7, 0x584B, 0xB6F8, 0x5967, 0xB6F9, 0x5AC1, 0xB6FA, 0x5AC9,	0xB6FB, 0x5ACC, 0xB6FC, 0x5ABE, 0xB6FD, 0x5ABD, 0xB6FE, 0x5ABC,
+	0xB740, 0x5AB3, 0xB741, 0x5AC2, 0xB742, 0x5AB2, 0xB743, 0x5D69,	0xB744, 0x5D6F, 0xB745, 0x5E4C, 0xB746, 0x5E79, 0xB747, 0x5EC9,
+	0xB748, 0x5EC8, 0xB749, 0x5F12, 0xB74A, 0x5F59, 0xB74B, 0x5FAC,	0xB74C, 0x5FAE, 0xB74D, 0x611A, 0xB74E, 0x610F, 0xB74F, 0x6148,
+	0xB750, 0x611F, 0xB751, 0x60F3, 0xB752, 0x611B, 0xB753, 0x60F9,	0xB754, 0x6101, 0xB755, 0x6108, 0xB756, 0x614E, 0xB757, 0x614C,
+	0xB758, 0x6144, 0xB759, 0x614D, 0xB75A, 0x613E, 0xB75B, 0x6134,	0xB75C, 0x6127, 0xB75D, 0x610D, 0xB75E, 0x6106, 0xB75F, 0x6137,
+	0xB760, 0x6221, 0xB761, 0x6222, 0xB762, 0x6413, 0xB763, 0x643E,	0xB764, 0x641E, 0xB765, 0x642A, 0xB766, 0x642D, 0xB767, 0x643D,
+	0xB768, 0x642C, 0xB769, 0x640F, 0xB76A, 0x641C, 0xB76B, 0x6414,	0xB76C, 0x640D, 0xB76D, 0x6436, 0xB76E, 0x6416, 0xB76F, 0x6417,
+	0xB770, 0x6406, 0xB771, 0x656C, 0xB772, 0x659F, 0xB773, 0x65B0,	0xB774, 0x6697, 0xB775, 0x6689, 0xB776, 0x6687, 0xB777, 0x6688,
+	0xB778, 0x6696, 0xB779, 0x6684, 0xB77A, 0x6698, 0xB77B, 0x668D,	0xB77C, 0x6703, 0xB77D, 0x6994, 0xB77E, 0x696D, 0xB7A1, 0x695A,
+	0xB7A2, 0x6977, 0xB7A3, 0x6960, 0xB7A4, 0x6954, 0xB7A5, 0x6975,	0xB7A6, 0x6930, 0xB7A7, 0x6982, 0xB7A8, 0x694A, 0xB7A9, 0x6968,
+	0xB7AA, 0x696B, 0xB7AB, 0x695E, 0xB7AC, 0x6953, 0xB7AD, 0x6979,	0xB7AE, 0x6986, 0xB7AF, 0x695D, 0xB7B0, 0x6963, 0xB7B1, 0x695B,
+	0xB7B2, 0x6B47, 0xB7B3, 0x6B72, 0xB7B4, 0x6BC0, 0xB7B5, 0x6BBF,	0xB7B6, 0x6BD3, 0xB7B7, 0x6BFD, 0xB7B8, 0x6EA2, 0xB7B9, 0x6EAF,
+	0xB7BA, 0x6ED3, 0xB7BB, 0x6EB6, 0xB7BC, 0x6EC2, 0xB7BD, 0x6E90,	0xB7BE, 0x6E9D, 0xB7BF, 0x6EC7, 0xB7C0, 0x6EC5, 0xB7C1, 0x6EA5,
+	0xB7C2, 0x6E98, 0xB7C3, 0x6EBC, 0xB7C4, 0x6EBA, 0xB7C5, 0x6EAB,	0xB7C6, 0x6ED1, 0xB7C7, 0x6E96, 0xB7C8, 0x6E9C, 0xB7C9, 0x6EC4,
+	0xB7CA, 0x6ED4, 0xB7CB, 0x6EAA, 0xB7CC, 0x6EA7, 0xB7CD, 0x6EB4,	0xB7CE, 0x714E, 0xB7CF, 0x7159, 0xB7D0, 0x7169, 0xB7D1, 0x7164,
+	0xB7D2, 0x7149, 0xB7D3, 0x7167, 0xB7D4, 0x715C, 0xB7D5, 0x716C,	0xB7D6, 0x7166, 0xB7D7, 0x714C, 0xB7D8, 0x7165, 0xB7D9, 0x715E,
+	0xB7DA, 0x7146, 0xB7DB, 0x7168, 0xB7DC, 0x7156, 0xB7DD, 0x723A,	0xB7DE, 0x7252, 0xB7DF, 0x7337, 0xB7E0, 0x7345, 0xB7E1, 0x733F,
+	0xB7E2, 0x733E, 0xB7E3, 0x746F, 0xB7E4, 0x745A, 0xB7E5, 0x7455,	0xB7E6, 0x745F, 0xB7E7, 0x745E, 0xB7E8, 0x7441, 0xB7E9, 0x743F,
+	0xB7EA, 0x7459, 0xB7EB, 0x745B, 0xB7EC, 0x745C, 0xB7ED, 0x7576,	0xB7EE, 0x7578, 0xB7EF, 0x7600, 0xB7F0, 0x75F0, 0xB7F1, 0x7601,
+	0xB7F2, 0x75F2, 0xB7F3, 0x75F1, 0xB7F4, 0x75FA, 0xB7F5, 0x75FF,	0xB7F6, 0x75F4, 0xB7F7, 0x75F3, 0xB7F8, 0x76DE, 0xB7F9, 0x76DF,
+	0xB7FA, 0x775B, 0xB7FB, 0x776B, 0xB7FC, 0x7766, 0xB7FD, 0x775E,	0xB7FE, 0x7763, 0xB840, 0x7779, 0xB841, 0x776A, 0xB842, 0x776C,
+	0xB843, 0x775C, 0xB844, 0x7765, 0xB845, 0x7768, 0xB846, 0x7762,	0xB847, 0x77EE, 0xB848, 0x788E, 0xB849, 0x78B0, 0xB84A, 0x7897,
+	0xB84B, 0x7898, 0xB84C, 0x788C, 0xB84D, 0x7889, 0xB84E, 0x787C,	0xB84F, 0x7891, 0xB850, 0x7893, 0xB851, 0x787F, 0xB852, 0x797A,
+	0xB853, 0x797F, 0xB854, 0x7981, 0xB855, 0x842C, 0xB856, 0x79BD,	0xB857, 0x7A1C, 0xB858, 0x7A1A, 0xB859, 0x7A20, 0xB85A, 0x7A14,
+	0xB85B, 0x7A1F, 0xB85C, 0x7A1E, 0xB85D, 0x7A9F, 0xB85E, 0x7AA0,	0xB85F, 0x7B77, 0xB860, 0x7BC0, 0xB861, 0x7B60, 0xB862, 0x7B6E,
+	0xB863, 0x7B67, 0xB864, 0x7CB1, 0xB865, 0x7CB3, 0xB866, 0x7CB5,	0xB867, 0x7D93, 0xB868, 0x7D79, 0xB869, 0x7D91, 0xB86A, 0x7D81,
+	0xB86B, 0x7D8F, 0xB86C, 0x7D5B, 0xB86D, 0x7F6E, 0xB86E, 0x7F69,	0xB86F, 0x7F6A, 0xB870, 0x7F72, 0xB871, 0x7FA9, 0xB872, 0x7FA8,
+	0xB873, 0x7FA4, 0xB874, 0x8056, 0xB875, 0x8058, 0xB876, 0x8086,	0xB877, 0x8084, 0xB878, 0x8171, 0xB879, 0x8170, 0xB87A, 0x8178,
+	0xB87B, 0x8165, 0xB87C, 0x816E, 0xB87D, 0x8173, 0xB87E, 0x816B,	0xB8A1, 0x8179, 0xB8A2, 0x817A, 0xB8A3, 0x8166, 0xB8A4, 0x8205,
+	0xB8A5, 0x8247, 0xB8A6, 0x8482, 0xB8A7, 0x8477, 0xB8A8, 0x843D,	0xB8A9, 0x8431, 0xB8AA, 0x8475, 0xB8AB, 0x8466, 0xB8AC, 0x846B,
+	0xB8AD, 0x8449, 0xB8AE, 0x846C, 0xB8AF, 0x845B, 0xB8B0, 0x843C,	0xB8B1, 0x8435, 0xB8B2, 0x8461, 0xB8B3, 0x8463, 0xB8B4, 0x8469,
+	0xB8B5, 0x846D, 0xB8B6, 0x8446, 0xB8B7, 0x865E, 0xB8B8, 0x865C,	0xB8B9, 0x865F, 0xB8BA, 0x86F9, 0xB8BB, 0x8713, 0xB8BC, 0x8708,
+	0xB8BD, 0x8707, 0xB8BE, 0x8700, 0xB8BF, 0x86FE, 0xB8C0, 0x86FB,	0xB8C1, 0x8702, 0xB8C2, 0x8703, 0xB8C3, 0x8706, 0xB8C4, 0x870A,
+	0xB8C5, 0x8859, 0xB8C6, 0x88DF, 0xB8C7, 0x88D4, 0xB8C8, 0x88D9,	0xB8C9, 0x88DC, 0xB8CA, 0x88D8, 0xB8CB, 0x88DD, 0xB8CC, 0x88E1,
+	0xB8CD, 0x88CA, 0xB8CE, 0x88D5, 0xB8CF, 0x88D2, 0xB8D0, 0x899C,	0xB8D1, 0x89E3, 0xB8D2, 0x8A6B, 0xB8D3, 0x8A72, 0xB8D4, 0x8A73,
+	0xB8D5, 0x8A66, 0xB8D6, 0x8A69, 0xB8D7, 0x8A70, 0xB8D8, 0x8A87,	0xB8D9, 0x8A7C, 0xB8DA, 0x8A63, 0xB8DB, 0x8AA0, 0xB8DC, 0x8A71,
+	0xB8DD, 0x8A85, 0xB8DE, 0x8A6D, 0xB8DF, 0x8A62, 0xB8E0, 0x8A6E,	0xB8E1, 0x8A6C, 0xB8E2, 0x8A79, 0xB8E3, 0x8A7B, 0xB8E4, 0x8A3E,
+	0xB8E5, 0x8A68, 0xB8E6, 0x8C62, 0xB8E7, 0x8C8A, 0xB8E8, 0x8C89,	0xB8E9, 0x8CCA, 0xB8EA, 0x8CC7, 0xB8EB, 0x8CC8, 0xB8EC, 0x8CC4,
+	0xB8ED, 0x8CB2, 0xB8EE, 0x8CC3, 0xB8EF, 0x8CC2, 0xB8F0, 0x8CC5,	0xB8F1, 0x8DE1, 0xB8F2, 0x8DDF, 0xB8F3, 0x8DE8, 0xB8F4, 0x8DEF,
+	0xB8F5, 0x8DF3, 0xB8F6, 0x8DFA, 0xB8F7, 0x8DEA, 0xB8F8, 0x8DE4,	0xB8F9, 0x8DE6, 0xB8FA, 0x8EB2, 0xB8FB, 0x8F03, 0xB8FC, 0x8F09,
+	0xB8FD, 0x8EFE, 0xB8FE, 0x8F0A, 0xB940, 0x8F9F, 0xB941, 0x8FB2,	0xB942, 0x904B, 0xB943, 0x904A, 0xB944, 0x9053, 0xB945, 0x9042,
+	0xB946, 0x9054, 0xB947, 0x903C, 0xB948, 0x9055, 0xB949, 0x9050,	0xB94A, 0x9047, 0xB94B, 0x904F, 0xB94C, 0x904E, 0xB94D, 0x904D,
+	0xB94E, 0x9051, 0xB94F, 0x903E, 0xB950, 0x9041, 0xB951, 0x9112,	0xB952, 0x9117, 0xB953, 0x916C, 0xB954, 0x916A, 0xB955, 0x9169,
+	0xB956, 0x91C9, 0xB957, 0x9237, 0xB958, 0x9257, 0xB959, 0x9238,	0xB95A, 0x923D, 0xB95B, 0x9240, 0xB95C, 0x923E, 0xB95D, 0x925B,
+	0xB95E, 0x924B, 0xB95F, 0x9264, 0xB960, 0x9251, 0xB961, 0x9234,	0xB962, 0x9249, 0xB963, 0x924D, 0xB964, 0x9245, 0xB965, 0x9239,
+	0xB966, 0x923F, 0xB967, 0x925A, 0xB968, 0x9598, 0xB969, 0x9698,	0xB96A, 0x9694, 0xB96B, 0x9695, 0xB96C, 0x96CD, 0xB96D, 0x96CB,
+	0xB96E, 0x96C9, 0xB96F, 0x96CA, 0xB970, 0x96F7, 0xB971, 0x96FB,	0xB972, 0x96F9, 0xB973, 0x96F6, 0xB974, 0x9756, 0xB975, 0x9774,
+	0xB976, 0x9776, 0xB977, 0x9810, 0xB978, 0x9811, 0xB979, 0x9813,	0xB97A, 0x980A, 0xB97B, 0x9812, 0xB97C, 0x980C, 0xB97D, 0x98FC,
+	0xB97E, 0x98F4, 0xB9A1, 0x98FD, 0xB9A2, 0x98FE, 0xB9A3, 0x99B3,	0xB9A4, 0x99B1, 0xB9A5, 0x99B4, 0xB9A6, 0x9AE1, 0xB9A7, 0x9CE9,
+	0xB9A8, 0x9E82, 0xB9A9, 0x9F0E, 0xB9AA, 0x9F13, 0xB9AB, 0x9F20,	0xB9AC, 0x50E7, 0xB9AD, 0x50EE, 0xB9AE, 0x50E5, 0xB9AF, 0x50D6,
+	0xB9B0, 0x50ED, 0xB9B1, 0x50DA, 0xB9B2, 0x50D5, 0xB9B3, 0x50CF,	0xB9B4, 0x50D1, 0xB9B5, 0x50F1, 0xB9B6, 0x50CE, 0xB9B7, 0x50E9,
+	0xB9B8, 0x5162, 0xB9B9, 0x51F3, 0xB9BA, 0x5283, 0xB9BB, 0x5282,	0xB9BC, 0x5331, 0xB9BD, 0x53AD, 0xB9BE, 0x55FE, 0xB9BF, 0x5600,
+	0xB9C0, 0x561B, 0xB9C1, 0x5617, 0xB9C2, 0x55FD, 0xB9C3, 0x5614,	0xB9C4, 0x5606, 0xB9C5, 0x5609, 0xB9C6, 0x560D, 0xB9C7, 0x560E,
+	0xB9C8, 0x55F7, 0xB9C9, 0x5616, 0xB9CA, 0x561F, 0xB9CB, 0x5608,	0xB9CC, 0x5610, 0xB9CD, 0x55F6, 0xB9CE, 0x5718, 0xB9CF, 0x5716,
+	0xB9D0, 0x5875, 0xB9D1, 0x587E, 0xB9D2, 0x5883, 0xB9D3, 0x5893,	0xB9D4, 0x588A, 0xB9D5, 0x5879, 0xB9D6, 0x5885, 0xB9D7, 0x587D,
+	0xB9D8, 0x58FD, 0xB9D9, 0x5925, 0xB9DA, 0x5922, 0xB9DB, 0x5924,	0xB9DC, 0x596A, 0xB9DD, 0x5969, 0xB9DE, 0x5AE1, 0xB9DF, 0x5AE6,
+	0xB9E0, 0x5AE9, 0xB9E1, 0x5AD7, 0xB9E2, 0x5AD6, 0xB9E3, 0x5AD8,	0xB9E4, 0x5AE3, 0xB9E5, 0x5B75, 0xB9E6, 0x5BDE, 0xB9E7, 0x5BE7,
+	0xB9E8, 0x5BE1, 0xB9E9, 0x5BE5, 0xB9EA, 0x5BE6, 0xB9EB, 0x5BE8,	0xB9EC, 0x5BE2, 0xB9ED, 0x5BE4, 0xB9EE, 0x5BDF, 0xB9EF, 0x5C0D,
+	0xB9F0, 0x5C62, 0xB9F1, 0x5D84, 0xB9F2, 0x5D87, 0xB9F3, 0x5E5B,	0xB9F4, 0x5E63, 0xB9F5, 0x5E55, 0xB9F6, 0x5E57, 0xB9F7, 0x5E54,
+	0xB9F8, 0x5ED3, 0xB9F9, 0x5ED6, 0xB9FA, 0x5F0A, 0xB9FB, 0x5F46,	0xB9FC, 0x5F70, 0xB9FD, 0x5FB9, 0xB9FE, 0x6147, 0xBA40, 0x613F,
+	0xBA41, 0x614B, 0xBA42, 0x6177, 0xBA43, 0x6162, 0xBA44, 0x6163,	0xBA45, 0x615F, 0xBA46, 0x615A, 0xBA47, 0x6158, 0xBA48, 0x6175,
+	0xBA49, 0x622A, 0xBA4A, 0x6487, 0xBA4B, 0x6458, 0xBA4C, 0x6454,	0xBA4D, 0x64A4, 0xBA4E, 0x6478, 0xBA4F, 0x645F, 0xBA50, 0x647A,
+	0xBA51, 0x6451, 0xBA52, 0x6467, 0xBA53, 0x6434, 0xBA54, 0x646D,	0xBA55, 0x647B, 0xBA56, 0x6572, 0xBA57, 0x65A1, 0xBA58, 0x65D7,
+	0xBA59, 0x65D6, 0xBA5A, 0x66A2, 0xBA5B, 0x66A8, 0xBA5C, 0x669D,	0xBA5D, 0x699C, 0xBA5E, 0x69A8, 0xBA5F, 0x6995, 0xBA60, 0x69C1,
+	0xBA61, 0x69AE, 0xBA62, 0x69D3, 0xBA63, 0x69CB, 0xBA64, 0x699B,	0xBA65, 0x69B7, 0xBA66, 0x69BB, 0xBA67, 0x69AB, 0xBA68, 0x69B4,
+	0xBA69, 0x69D0, 0xBA6A, 0x69CD, 0xBA6B, 0x69AD, 0xBA6C, 0x69CC,	0xBA6D, 0x69A6, 0xBA6E, 0x69C3, 0xBA6F, 0x69A3, 0xBA70, 0x6B49,
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+	0xBECF, 0x61CD, 0xBED0, 0x61B6, 0xBED1, 0x61BE, 0xBED2, 0x61CA,	0xBED3, 0x61C8, 0xBED4, 0x6230, 0xBED5, 0x64C5, 0xBED6, 0x64C1,
+	0xBED7, 0x64CB, 0xBED8, 0x64BB, 0xBED9, 0x64BC, 0xBEDA, 0x64DA,	0xBEDB, 0x64C4, 0xBEDC, 0x64C7, 0xBEDD, 0x64C2, 0xBEDE, 0x64CD,
+	0xBEDF, 0x64BF, 0xBEE0, 0x64D2, 0xBEE1, 0x64D4, 0xBEE2, 0x64BE,	0xBEE3, 0x6574, 0xBEE4, 0x66C6, 0xBEE5, 0x66C9, 0xBEE6, 0x66B9,
+	0xBEE7, 0x66C4, 0xBEE8, 0x66C7, 0xBEE9, 0x66B8, 0xBEEA, 0x6A3D,	0xBEEB, 0x6A38, 0xBEEC, 0x6A3A, 0xBEED, 0x6A59, 0xBEEE, 0x6A6B,
+	0xBEEF, 0x6A58, 0xBEF0, 0x6A39, 0xBEF1, 0x6A44, 0xBEF2, 0x6A62,	0xBEF3, 0x6A61, 0xBEF4, 0x6A4B, 0xBEF5, 0x6A47, 0xBEF6, 0x6A35,
+	0xBEF7, 0x6A5F, 0xBEF8, 0x6A48, 0xBEF9, 0x6B59, 0xBEFA, 0x6B77,	0xBEFB, 0x6C05, 0xBEFC, 0x6FC2, 0xBEFD, 0x6FB1, 0xBEFE, 0x6FA1,
+	0xBF40, 0x6FC3, 0xBF41, 0x6FA4, 0xBF42, 0x6FC1, 0xBF43, 0x6FA7,	0xBF44, 0x6FB3, 0xBF45, 0x6FC0, 0xBF46, 0x6FB9, 0xBF47, 0x6FB6,
+	0xBF48, 0x6FA6, 0xBF49, 0x6FA0, 0xBF4A, 0x6FB4, 0xBF4B, 0x71BE,	0xBF4C, 0x71C9, 0xBF4D, 0x71D0, 0xBF4E, 0x71D2, 0xBF4F, 0x71C8,
+	0xBF50, 0x71D5, 0xBF51, 0x71B9, 0xBF52, 0x71CE, 0xBF53, 0x71D9,	0xBF54, 0x71DC, 0xBF55, 0x71C3, 0xBF56, 0x71C4, 0xBF57, 0x7368,
+	0xBF58, 0x749C, 0xBF59, 0x74A3, 0xBF5A, 0x7498, 0xBF5B, 0x749F,	0xBF5C, 0x749E, 0xBF5D, 0x74E2, 0xBF5E, 0x750C, 0xBF5F, 0x750D,
+	0xBF60, 0x7634, 0xBF61, 0x7638, 0xBF62, 0x763A, 0xBF63, 0x76E7,	0xBF64, 0x76E5, 0xBF65, 0x77A0, 0xBF66, 0x779E, 0xBF67, 0x779F,
+	0xBF68, 0x77A5, 0xBF69, 0x78E8, 0xBF6A, 0x78DA, 0xBF6B, 0x78EC,	0xBF6C, 0x78E7, 0xBF6D, 0x79A6, 0xBF6E, 0x7A4D, 0xBF6F, 0x7A4E,
+	0xBF70, 0x7A46, 0xBF71, 0x7A4C, 0xBF72, 0x7A4B, 0xBF73, 0x7ABA,	0xBF74, 0x7BD9, 0xBF75, 0x7C11, 0xBF76, 0x7BC9, 0xBF77, 0x7BE4,
+	0xBF78, 0x7BDB, 0xBF79, 0x7BE1, 0xBF7A, 0x7BE9, 0xBF7B, 0x7BE6,	0xBF7C, 0x7CD5, 0xBF7D, 0x7CD6, 0xBF7E, 0x7E0A, 0xBFA1, 0x7E11,
+	0xBFA2, 0x7E08, 0xBFA3, 0x7E1B, 0xBFA4, 0x7E23, 0xBFA5, 0x7E1E,	0xBFA6, 0x7E1D, 0xBFA7, 0x7E09, 0xBFA8, 0x7E10, 0xBFA9, 0x7F79,
+	0xBFAA, 0x7FB2, 0xBFAB, 0x7FF0, 0xBFAC, 0x7FF1, 0xBFAD, 0x7FEE,	0xBFAE, 0x8028, 0xBFAF, 0x81B3, 0xBFB0, 0x81A9, 0xBFB1, 0x81A8,
+	0xBFB2, 0x81FB, 0xBFB3, 0x8208, 0xBFB4, 0x8258, 0xBFB5, 0x8259,	0xBFB6, 0x854A, 0xBFB7, 0x8559, 0xBFB8, 0x8548, 0xBFB9, 0x8568,
+	0xBFBA, 0x8569, 0xBFBB, 0x8543, 0xBFBC, 0x8549, 0xBFBD, 0x856D,	0xBFBE, 0x856A, 0xBFBF, 0x855E, 0xBFC0, 0x8783, 0xBFC1, 0x879F,
+	0xBFC2, 0x879E, 0xBFC3, 0x87A2, 0xBFC4, 0x878D, 0xBFC5, 0x8861,	0xBFC6, 0x892A, 0xBFC7, 0x8932, 0xBFC8, 0x8925, 0xBFC9, 0x892B,
+	0xBFCA, 0x8921, 0xBFCB, 0x89AA, 0xBFCC, 0x89A6, 0xBFCD, 0x8AE6,	0xBFCE, 0x8AFA, 0xBFCF, 0x8AEB, 0xBFD0, 0x8AF1, 0xBFD1, 0x8B00,
+	0xBFD2, 0x8ADC, 0xBFD3, 0x8AE7, 0xBFD4, 0x8AEE, 0xBFD5, 0x8AFE,	0xBFD6, 0x8B01, 0xBFD7, 0x8B02, 0xBFD8, 0x8AF7, 0xBFD9, 0x8AED,
+	0xBFDA, 0x8AF3, 0xBFDB, 0x8AF6, 0xBFDC, 0x8AFC, 0xBFDD, 0x8C6B,	0xBFDE, 0x8C6D, 0xBFDF, 0x8C93, 0xBFE0, 0x8CF4, 0xBFE1, 0x8E44,
+	0xBFE2, 0x8E31, 0xBFE3, 0x8E34, 0xBFE4, 0x8E42, 0xBFE5, 0x8E39,	0xBFE6, 0x8E35, 0xBFE7, 0x8F3B, 0xBFE8, 0x8F2F, 0xBFE9, 0x8F38,
+	0xBFEA, 0x8F33, 0xBFEB, 0x8FA8, 0xBFEC, 0x8FA6, 0xBFED, 0x9075,	0xBFEE, 0x9074, 0xBFEF, 0x9078, 0xBFF0, 0x9072, 0xBFF1, 0x907C,
+	0xBFF2, 0x907A, 0xBFF3, 0x9134, 0xBFF4, 0x9192, 0xBFF5, 0x9320,	0xBFF6, 0x9336, 0xBFF7, 0x92F8, 0xBFF8, 0x9333, 0xBFF9, 0x932F,
+	0xBFFA, 0x9322, 0xBFFB, 0x92FC, 0xBFFC, 0x932B, 0xBFFD, 0x9304,	0xBFFE, 0x931A, 0xC040, 0x9310, 0xC041, 0x9326, 0xC042, 0x9321,
+	0xC043, 0x9315, 0xC044, 0x932E, 0xC045, 0x9319, 0xC046, 0x95BB,	0xC047, 0x96A7, 0xC048, 0x96A8, 0xC049, 0x96AA, 0xC04A, 0x96D5,
+	0xC04B, 0x970E, 0xC04C, 0x9711, 0xC04D, 0x9716, 0xC04E, 0x970D,	0xC04F, 0x9713, 0xC050, 0x970F, 0xC051, 0x975B, 0xC052, 0x975C,
+	0xC053, 0x9766, 0xC054, 0x9798, 0xC055, 0x9830, 0xC056, 0x9838,	0xC057, 0x983B, 0xC058, 0x9837, 0xC059, 0x982D, 0xC05A, 0x9839,
+	0xC05B, 0x9824, 0xC05C, 0x9910, 0xC05D, 0x9928, 0xC05E, 0x991E,	0xC05F, 0x991B, 0xC060, 0x9921, 0xC061, 0x991A, 0xC062, 0x99ED,
+	0xC063, 0x99E2, 0xC064, 0x99F1, 0xC065, 0x9AB8, 0xC066, 0x9ABC,	0xC067, 0x9AFB, 0xC068, 0x9AED, 0xC069, 0x9B28, 0xC06A, 0x9B91,
+	0xC06B, 0x9D15, 0xC06C, 0x9D23, 0xC06D, 0x9D26, 0xC06E, 0x9D28,	0xC06F, 0x9D12, 0xC070, 0x9D1B, 0xC071, 0x9ED8, 0xC072, 0x9ED4,
+	0xC073, 0x9F8D, 0xC074, 0x9F9C, 0xC075, 0x512A, 0xC076, 0x511F,	0xC077, 0x5121, 0xC078, 0x5132, 0xC079, 0x52F5, 0xC07A, 0x568E,
+	0xC07B, 0x5680, 0xC07C, 0x5690, 0xC07D, 0x5685, 0xC07E, 0x5687,	0xC0A1, 0x568F, 0xC0A2, 0x58D5, 0xC0A3, 0x58D3, 0xC0A4, 0x58D1,
+	0xC0A5, 0x58CE, 0xC0A6, 0x5B30, 0xC0A7, 0x5B2A, 0xC0A8, 0x5B24,	0xC0A9, 0x5B7A, 0xC0AA, 0x5C37, 0xC0AB, 0x5C68, 0xC0AC, 0x5DBC,
+	0xC0AD, 0x5DBA, 0xC0AE, 0x5DBD, 0xC0AF, 0x5DB8, 0xC0B0, 0x5E6B,	0xC0B1, 0x5F4C, 0xC0B2, 0x5FBD, 0xC0B3, 0x61C9, 0xC0B4, 0x61C2,
+	0xC0B5, 0x61C7, 0xC0B6, 0x61E6, 0xC0B7, 0x61CB, 0xC0B8, 0x6232,	0xC0B9, 0x6234, 0xC0BA, 0x64CE, 0xC0BB, 0x64CA, 0xC0BC, 0x64D8,
+	0xC0BD, 0x64E0, 0xC0BE, 0x64F0, 0xC0BF, 0x64E6, 0xC0C0, 0x64EC,	0xC0C1, 0x64F1, 0xC0C2, 0x64E2, 0xC0C3, 0x64ED, 0xC0C4, 0x6582,
+	0xC0C5, 0x6583, 0xC0C6, 0x66D9, 0xC0C7, 0x66D6, 0xC0C8, 0x6A80,	0xC0C9, 0x6A94, 0xC0CA, 0x6A84, 0xC0CB, 0x6AA2, 0xC0CC, 0x6A9C,
+	0xC0CD, 0x6ADB, 0xC0CE, 0x6AA3, 0xC0CF, 0x6A7E, 0xC0D0, 0x6A97,	0xC0D1, 0x6A90, 0xC0D2, 0x6AA0, 0xC0D3, 0x6B5C, 0xC0D4, 0x6BAE,
+	0xC0D5, 0x6BDA, 0xC0D6, 0x6C08, 0xC0D7, 0x6FD8, 0xC0D8, 0x6FF1,	0xC0D9, 0x6FDF, 0xC0DA, 0x6FE0, 0xC0DB, 0x6FDB, 0xC0DC, 0x6FE4,
+	0xC0DD, 0x6FEB, 0xC0DE, 0x6FEF, 0xC0DF, 0x6F80, 0xC0E0, 0x6FEC,	0xC0E1, 0x6FE1, 0xC0E2, 0x6FE9, 0xC0E3, 0x6FD5, 0xC0E4, 0x6FEE,
+	0xC0E5, 0x6FF0, 0xC0E6, 0x71E7, 0xC0E7, 0x71DF, 0xC0E8, 0x71EE,	0xC0E9, 0x71E6, 0xC0EA, 0x71E5, 0xC0EB, 0x71ED, 0xC0EC, 0x71EC,
+	0xC0ED, 0x71F4, 0xC0EE, 0x71E0, 0xC0EF, 0x7235, 0xC0F0, 0x7246,	0xC0F1, 0x7370, 0xC0F2, 0x7372, 0xC0F3, 0x74A9, 0xC0F4, 0x74B0,
+	0xC0F5, 0x74A6, 0xC0F6, 0x74A8, 0xC0F7, 0x7646, 0xC0F8, 0x7642,	0xC0F9, 0x764C, 0xC0FA, 0x76EA, 0xC0FB, 0x77B3, 0xC0FC, 0x77AA,
+	0xC0FD, 0x77B0, 0xC0FE, 0x77AC, 0xC140, 0x77A7, 0xC141, 0x77AD,	0xC142, 0x77EF, 0xC143, 0x78F7, 0xC144, 0x78FA, 0xC145, 0x78F4,
+	0xC146, 0x78EF, 0xC147, 0x7901, 0xC148, 0x79A7, 0xC149, 0x79AA,	0xC14A, 0x7A57, 0xC14B, 0x7ABF, 0xC14C, 0x7C07, 0xC14D, 0x7C0D,
+	0xC14E, 0x7BFE, 0xC14F, 0x7BF7, 0xC150, 0x7C0C, 0xC151, 0x7BE0,	0xC152, 0x7CE0, 0xC153, 0x7CDC, 0xC154, 0x7CDE, 0xC155, 0x7CE2,
+	0xC156, 0x7CDF, 0xC157, 0x7CD9, 0xC158, 0x7CDD, 0xC159, 0x7E2E,	0xC15A, 0x7E3E, 0xC15B, 0x7E46, 0xC15C, 0x7E37, 0xC15D, 0x7E32,
+	0xC15E, 0x7E43, 0xC15F, 0x7E2B, 0xC160, 0x7E3D, 0xC161, 0x7E31,	0xC162, 0x7E45, 0xC163, 0x7E41, 0xC164, 0x7E34, 0xC165, 0x7E39,
+	0xC166, 0x7E48, 0xC167, 0x7E35, 0xC168, 0x7E3F, 0xC169, 0x7E2F,	0xC16A, 0x7F44, 0xC16B, 0x7FF3, 0xC16C, 0x7FFC, 0xC16D, 0x8071,
+	0xC16E, 0x8072, 0xC16F, 0x8070, 0xC170, 0x806F, 0xC171, 0x8073,	0xC172, 0x81C6, 0xC173, 0x81C3, 0xC174, 0x81BA, 0xC175, 0x81C2,
+	0xC176, 0x81C0, 0xC177, 0x81BF, 0xC178, 0x81BD, 0xC179, 0x81C9,	0xC17A, 0x81BE, 0xC17B, 0x81E8, 0xC17C, 0x8209, 0xC17D, 0x8271,
+	0xC17E, 0x85AA, 0xC1A1, 0x8584, 0xC1A2, 0x857E, 0xC1A3, 0x859C,	0xC1A4, 0x8591, 0xC1A5, 0x8594, 0xC1A6, 0x85AF, 0xC1A7, 0x859B,
+	0xC1A8, 0x8587, 0xC1A9, 0x85A8, 0xC1AA, 0x858A, 0xC1AB, 0x8667,	0xC1AC, 0x87C0, 0xC1AD, 0x87D1, 0xC1AE, 0x87B3, 0xC1AF, 0x87D2,
+	0xC1B0, 0x87C6, 0xC1B1, 0x87AB, 0xC1B2, 0x87BB, 0xC1B3, 0x87BA,	0xC1B4, 0x87C8, 0xC1B5, 0x87CB, 0xC1B6, 0x893B, 0xC1B7, 0x8936,
+	0xC1B8, 0x8944, 0xC1B9, 0x8938, 0xC1BA, 0x893D, 0xC1BB, 0x89AC,	0xC1BC, 0x8B0E, 0xC1BD, 0x8B17, 0xC1BE, 0x8B19, 0xC1BF, 0x8B1B,
+	0xC1C0, 0x8B0A, 0xC1C1, 0x8B20, 0xC1C2, 0x8B1D, 0xC1C3, 0x8B04,	0xC1C4, 0x8B10, 0xC1C5, 0x8C41, 0xC1C6, 0x8C3F, 0xC1C7, 0x8C73,
+	0xC1C8, 0x8CFA, 0xC1C9, 0x8CFD, 0xC1CA, 0x8CFC, 0xC1CB, 0x8CF8,	0xC1CC, 0x8CFB, 0xC1CD, 0x8DA8, 0xC1CE, 0x8E49, 0xC1CF, 0x8E4B,
+	0xC1D0, 0x8E48, 0xC1D1, 0x8E4A, 0xC1D2, 0x8F44, 0xC1D3, 0x8F3E,	0xC1D4, 0x8F42, 0xC1D5, 0x8F45, 0xC1D6, 0x8F3F, 0xC1D7, 0x907F,
+	0xC1D8, 0x907D, 0xC1D9, 0x9084, 0xC1DA, 0x9081, 0xC1DB, 0x9082,	0xC1DC, 0x9080, 0xC1DD, 0x9139, 0xC1DE, 0x91A3, 0xC1DF, 0x919E,
+	0xC1E0, 0x919C, 0xC1E1, 0x934D, 0xC1E2, 0x9382, 0xC1E3, 0x9328,	0xC1E4, 0x9375, 0xC1E5, 0x934A, 0xC1E6, 0x9365, 0xC1E7, 0x934B,
+	0xC1E8, 0x9318, 0xC1E9, 0x937E, 0xC1EA, 0x936C, 0xC1EB, 0x935B,	0xC1EC, 0x9370, 0xC1ED, 0x935A, 0xC1EE, 0x9354, 0xC1EF, 0x95CA,
+	0xC1F0, 0x95CB, 0xC1F1, 0x95CC, 0xC1F2, 0x95C8, 0xC1F3, 0x95C6,	0xC1F4, 0x96B1, 0xC1F5, 0x96B8, 0xC1F6, 0x96D6, 0xC1F7, 0x971C,
+	0xC1F8, 0x971E, 0xC1F9, 0x97A0, 0xC1FA, 0x97D3, 0xC1FB, 0x9846,	0xC1FC, 0x98B6, 0xC1FD, 0x9935, 0xC1FE, 0x9A01, 0xC240, 0x99FF,
+	0xC241, 0x9BAE, 0xC242, 0x9BAB, 0xC243, 0x9BAA, 0xC244, 0x9BAD,	0xC245, 0x9D3B, 0xC246, 0x9D3F, 0xC247, 0x9E8B, 0xC248, 0x9ECF,
+	0xC249, 0x9EDE, 0xC24A, 0x9EDC, 0xC24B, 0x9EDD, 0xC24C, 0x9EDB,	0xC24D, 0x9F3E, 0xC24E, 0x9F4B, 0xC24F, 0x53E2, 0xC250, 0x5695,
+	0xC251, 0x56AE, 0xC252, 0x58D9, 0xC253, 0x58D8, 0xC254, 0x5B38,	0xC255, 0x5F5D, 0xC256, 0x61E3, 0xC257, 0x6233, 0xC258, 0x64F4,
+	0xC259, 0x64F2, 0xC25A, 0x64FE, 0xC25B, 0x6506, 0xC25C, 0x64FA,	0xC25D, 0x64FB, 0xC25E, 0x64F7, 0xC25F, 0x65B7, 0xC260, 0x66DC,
+	0xC261, 0x6726, 0xC262, 0x6AB3, 0xC263, 0x6AAC, 0xC264, 0x6AC3,	0xC265, 0x6ABB, 0xC266, 0x6AB8, 0xC267, 0x6AC2, 0xC268, 0x6AAE,
+	0xC269, 0x6AAF, 0xC26A, 0x6B5F, 0xC26B, 0x6B78, 0xC26C, 0x6BAF,	0xC26D, 0x7009, 0xC26E, 0x700B, 0xC26F, 0x6FFE, 0xC270, 0x7006,
+	0xC271, 0x6FFA, 0xC272, 0x7011, 0xC273, 0x700F, 0xC274, 0x71FB,	0xC275, 0x71FC, 0xC276, 0x71FE, 0xC277, 0x71F8, 0xC278, 0x7377,
+	0xC279, 0x7375, 0xC27A, 0x74A7, 0xC27B, 0x74BF, 0xC27C, 0x7515,	0xC27D, 0x7656, 0xC27E, 0x7658, 0xC2A1, 0x7652, 0xC2A2, 0x77BD,
+	0xC2A3, 0x77BF, 0xC2A4, 0x77BB, 0xC2A5, 0x77BC, 0xC2A6, 0x790E,	0xC2A7, 0x79AE, 0xC2A8, 0x7A61, 0xC2A9, 0x7A62, 0xC2AA, 0x7A60,
+	0xC2AB, 0x7AC4, 0xC2AC, 0x7AC5, 0xC2AD, 0x7C2B, 0xC2AE, 0x7C27,	0xC2AF, 0x7C2A, 0xC2B0, 0x7C1E, 0xC2B1, 0x7C23, 0xC2B2, 0x7C21,
+	0xC2B3, 0x7CE7, 0xC2B4, 0x7E54, 0xC2B5, 0x7E55, 0xC2B6, 0x7E5E,	0xC2B7, 0x7E5A, 0xC2B8, 0x7E61, 0xC2B9, 0x7E52, 0xC2BA, 0x7E59,
+	0xC2BB, 0x7F48, 0xC2BC, 0x7FF9, 0xC2BD, 0x7FFB, 0xC2BE, 0x8077,	0xC2BF, 0x8076, 0xC2C0, 0x81CD, 0xC2C1, 0x81CF, 0xC2C2, 0x820A,
+	0xC2C3, 0x85CF, 0xC2C4, 0x85A9, 0xC2C5, 0x85CD, 0xC2C6, 0x85D0,	0xC2C7, 0x85C9, 0xC2C8, 0x85B0, 0xC2C9, 0x85BA, 0xC2CA, 0x85B9,
+	0xC2CB, 0x85A6, 0xC2CC, 0x87EF, 0xC2CD, 0x87EC, 0xC2CE, 0x87F2,	0xC2CF, 0x87E0, 0xC2D0, 0x8986, 0xC2D1, 0x89B2, 0xC2D2, 0x89F4,
+	0xC2D3, 0x8B28, 0xC2D4, 0x8B39, 0xC2D5, 0x8B2C, 0xC2D6, 0x8B2B,	0xC2D7, 0x8C50, 0xC2D8, 0x8D05, 0xC2D9, 0x8E59, 0xC2DA, 0x8E63,
+	0xC2DB, 0x8E66, 0xC2DC, 0x8E64, 0xC2DD, 0x8E5F, 0xC2DE, 0x8E55,	0xC2DF, 0x8EC0, 0xC2E0, 0x8F49, 0xC2E1, 0x8F4D, 0xC2E2, 0x9087,
+	0xC2E3, 0x9083, 0xC2E4, 0x9088, 0xC2E5, 0x91AB, 0xC2E6, 0x91AC,	0xC2E7, 0x91D0, 0xC2E8, 0x9394, 0xC2E9, 0x938A, 0xC2EA, 0x9396,
+	0xC2EB, 0x93A2, 0xC2EC, 0x93B3, 0xC2ED, 0x93AE, 0xC2EE, 0x93AC,	0xC2EF, 0x93B0, 0xC2F0, 0x9398, 0xC2F1, 0x939A, 0xC2F2, 0x9397,
+	0xC2F3, 0x95D4, 0xC2F4, 0x95D6, 0xC2F5, 0x95D0, 0xC2F6, 0x95D5,	0xC2F7, 0x96E2, 0xC2F8, 0x96DC, 0xC2F9, 0x96D9, 0xC2FA, 0x96DB,
+	0xC2FB, 0x96DE, 0xC2FC, 0x9724, 0xC2FD, 0x97A3, 0xC2FE, 0x97A6,	0xC340, 0x97AD, 0xC341, 0x97F9, 0xC342, 0x984D, 0xC343, 0x984F,
+	0xC344, 0x984C, 0xC345, 0x984E, 0xC346, 0x9853, 0xC347, 0x98BA,	0xC348, 0x993E, 0xC349, 0x993F, 0xC34A, 0x993D, 0xC34B, 0x992E,
+	0xC34C, 0x99A5, 0xC34D, 0x9A0E, 0xC34E, 0x9AC1, 0xC34F, 0x9B03,	0xC350, 0x9B06, 0xC351, 0x9B4F, 0xC352, 0x9B4E, 0xC353, 0x9B4D,
+	0xC354, 0x9BCA, 0xC355, 0x9BC9, 0xC356, 0x9BFD, 0xC357, 0x9BC8,	0xC358, 0x9BC0, 0xC359, 0x9D51, 0xC35A, 0x9D5D, 0xC35B, 0x9D60,
+	0xC35C, 0x9EE0, 0xC35D, 0x9F15, 0xC35E, 0x9F2C, 0xC35F, 0x5133,	0xC360, 0x56A5, 0xC361, 0x58DE, 0xC362, 0x58DF, 0xC363, 0x58E2,
+	0xC364, 0x5BF5, 0xC365, 0x9F90, 0xC366, 0x5EEC, 0xC367, 0x61F2,	0xC368, 0x61F7, 0xC369, 0x61F6, 0xC36A, 0x61F5, 0xC36B, 0x6500,
+	0xC36C, 0x650F, 0xC36D, 0x66E0, 0xC36E, 0x66DD, 0xC36F, 0x6AE5,	0xC370, 0x6ADD, 0xC371, 0x6ADA, 0xC372, 0x6AD3, 0xC373, 0x701B,
+	0xC374, 0x701F, 0xC375, 0x7028, 0xC376, 0x701A, 0xC377, 0x701D,	0xC378, 0x7015, 0xC379, 0x7018, 0xC37A, 0x7206, 0xC37B, 0x720D,
+	0xC37C, 0x7258, 0xC37D, 0x72A2, 0xC37E, 0x7378, 0xC3A1, 0x737A,	0xC3A2, 0x74BD, 0xC3A3, 0x74CA, 0xC3A4, 0x74E3, 0xC3A5, 0x7587,
+	0xC3A6, 0x7586, 0xC3A7, 0x765F, 0xC3A8, 0x7661, 0xC3A9, 0x77C7,	0xC3AA, 0x7919, 0xC3AB, 0x79B1, 0xC3AC, 0x7A6B, 0xC3AD, 0x7A69,
+	0xC3AE, 0x7C3E, 0xC3AF, 0x7C3F, 0xC3B0, 0x7C38, 0xC3B1, 0x7C3D,	0xC3B2, 0x7C37, 0xC3B3, 0x7C40, 0xC3B4, 0x7E6B, 0xC3B5, 0x7E6D,
+	0xC3B6, 0x7E79, 0xC3B7, 0x7E69, 0xC3B8, 0x7E6A, 0xC3B9, 0x7F85,	0xC3BA, 0x7E73, 0xC3BB, 0x7FB6, 0xC3BC, 0x7FB9, 0xC3BD, 0x7FB8,
+	0xC3BE, 0x81D8, 0xC3BF, 0x85E9, 0xC3C0, 0x85DD, 0xC3C1, 0x85EA,	0xC3C2, 0x85D5, 0xC3C3, 0x85E4, 0xC3C4, 0x85E5, 0xC3C5, 0x85F7,
+	0xC3C6, 0x87FB, 0xC3C7, 0x8805, 0xC3C8, 0x880D, 0xC3C9, 0x87F9,	0xC3CA, 0x87FE, 0xC3CB, 0x8960, 0xC3CC, 0x895F, 0xC3CD, 0x8956,
+	0xC3CE, 0x895E, 0xC3CF, 0x8B41, 0xC3D0, 0x8B5C, 0xC3D1, 0x8B58,	0xC3D2, 0x8B49, 0xC3D3, 0x8B5A, 0xC3D4, 0x8B4E, 0xC3D5, 0x8B4F,
+	0xC3D6, 0x8B46, 0xC3D7, 0x8B59, 0xC3D8, 0x8D08, 0xC3D9, 0x8D0A,	0xC3DA, 0x8E7C, 0xC3DB, 0x8E72, 0xC3DC, 0x8E87, 0xC3DD, 0x8E76,
+	0xC3DE, 0x8E6C, 0xC3DF, 0x8E7A, 0xC3E0, 0x8E74, 0xC3E1, 0x8F54,	0xC3E2, 0x8F4E, 0xC3E3, 0x8FAD, 0xC3E4, 0x908A, 0xC3E5, 0x908B,
+	0xC3E6, 0x91B1, 0xC3E7, 0x91AE, 0xC3E8, 0x93E1, 0xC3E9, 0x93D1,	0xC3EA, 0x93DF, 0xC3EB, 0x93C3, 0xC3EC, 0x93C8, 0xC3ED, 0x93DC,
+	0xC3EE, 0x93DD, 0xC3EF, 0x93D6, 0xC3F0, 0x93E2, 0xC3F1, 0x93CD,	0xC3F2, 0x93D8, 0xC3F3, 0x93E4, 0xC3F4, 0x93D7, 0xC3F5, 0x93E8,
+	0xC3F6, 0x95DC, 0xC3F7, 0x96B4, 0xC3F8, 0x96E3, 0xC3F9, 0x972A,	0xC3FA, 0x9727, 0xC3FB, 0x9761, 0xC3FC, 0x97DC, 0xC3FD, 0x97FB,
+	0xC3FE, 0x985E, 0xC440, 0x9858, 0xC441, 0x985B, 0xC442, 0x98BC,	0xC443, 0x9945, 0xC444, 0x9949, 0xC445, 0x9A16, 0xC446, 0x9A19,
+	0xC447, 0x9B0D, 0xC448, 0x9BE8, 0xC449, 0x9BE7, 0xC44A, 0x9BD6,	0xC44B, 0x9BDB, 0xC44C, 0x9D89, 0xC44D, 0x9D61, 0xC44E, 0x9D72,
+	0xC44F, 0x9D6A, 0xC450, 0x9D6C, 0xC451, 0x9E92, 0xC452, 0x9E97,	0xC453, 0x9E93, 0xC454, 0x9EB4, 0xC455, 0x52F8, 0xC456, 0x56A8,
+	0xC457, 0x56B7, 0xC458, 0x56B6, 0xC459, 0x56B4, 0xC45A, 0x56BC,	0xC45B, 0x58E4, 0xC45C, 0x5B40, 0xC45D, 0x5B43, 0xC45E, 0x5B7D,
+	0xC45F, 0x5BF6, 0xC460, 0x5DC9, 0xC461, 0x61F8, 0xC462, 0x61FA,	0xC463, 0x6518, 0xC464, 0x6514, 0xC465, 0x6519, 0xC466, 0x66E6,
+	0xC467, 0x6727, 0xC468, 0x6AEC, 0xC469, 0x703E, 0xC46A, 0x7030,	0xC46B, 0x7032, 0xC46C, 0x7210, 0xC46D, 0x737B, 0xC46E, 0x74CF,
+	0xC46F, 0x7662, 0xC470, 0x7665, 0xC471, 0x7926, 0xC472, 0x792A,	0xC473, 0x792C, 0xC474, 0x792B, 0xC475, 0x7AC7, 0xC476, 0x7AF6,
+	0xC477, 0x7C4C, 0xC478, 0x7C43, 0xC479, 0x7C4D, 0xC47A, 0x7CEF,	0xC47B, 0x7CF0, 0xC47C, 0x8FAE, 0xC47D, 0x7E7D, 0xC47E, 0x7E7C,
+	0xC4A1, 0x7E82, 0xC4A2, 0x7F4C, 0xC4A3, 0x8000, 0xC4A4, 0x81DA,	0xC4A5, 0x8266, 0xC4A6, 0x85FB, 0xC4A7, 0x85F9, 0xC4A8, 0x8611,
+	0xC4A9, 0x85FA, 0xC4AA, 0x8606, 0xC4AB, 0x860B, 0xC4AC, 0x8607,	0xC4AD, 0x860A, 0xC4AE, 0x8814, 0xC4AF, 0x8815, 0xC4B0, 0x8964,
+	0xC4B1, 0x89BA, 0xC4B2, 0x89F8, 0xC4B3, 0x8B70, 0xC4B4, 0x8B6C,	0xC4B5, 0x8B66, 0xC4B6, 0x8B6F, 0xC4B7, 0x8B5F, 0xC4B8, 0x8B6B,
+	0xC4B9, 0x8D0F, 0xC4BA, 0x8D0D, 0xC4BB, 0x8E89, 0xC4BC, 0x8E81,	0xC4BD, 0x8E85, 0xC4BE, 0x8E82, 0xC4BF, 0x91B4, 0xC4C0, 0x91CB,
+	0xC4C1, 0x9418, 0xC4C2, 0x9403, 0xC4C3, 0x93FD, 0xC4C4, 0x95E1,	0xC4C5, 0x9730, 0xC4C6, 0x98C4, 0xC4C7, 0x9952, 0xC4C8, 0x9951,
+	0xC4C9, 0x99A8, 0xC4CA, 0x9A2B, 0xC4CB, 0x9A30, 0xC4CC, 0x9A37,	0xC4CD, 0x9A35, 0xC4CE, 0x9C13, 0xC4CF, 0x9C0D, 0xC4D0, 0x9E79,
+	0xC4D1, 0x9EB5, 0xC4D2, 0x9EE8, 0xC4D3, 0x9F2F, 0xC4D4, 0x9F5F,	0xC4D5, 0x9F63, 0xC4D6, 0x9F61, 0xC4D7, 0x5137, 0xC4D8, 0x5138,
+	0xC4D9, 0x56C1, 0xC4DA, 0x56C0, 0xC4DB, 0x56C2, 0xC4DC, 0x5914,	0xC4DD, 0x5C6C, 0xC4DE, 0x5DCD, 0xC4DF, 0x61FC, 0xC4E0, 0x61FE,
+	0xC4E1, 0x651D, 0xC4E2, 0x651C, 0xC4E3, 0x6595, 0xC4E4, 0x66E9,	0xC4E5, 0x6AFB, 0xC4E6, 0x6B04, 0xC4E7, 0x6AFA, 0xC4E8, 0x6BB2,
+	0xC4E9, 0x704C, 0xC4EA, 0x721B, 0xC4EB, 0x72A7, 0xC4EC, 0x74D6,	0xC4ED, 0x74D4, 0xC4EE, 0x7669, 0xC4EF, 0x77D3, 0xC4F0, 0x7C50,
+	0xC4F1, 0x7E8F, 0xC4F2, 0x7E8C, 0xC4F3, 0x7FBC, 0xC4F4, 0x8617,	0xC4F5, 0x862D, 0xC4F6, 0x861A, 0xC4F7, 0x8823, 0xC4F8, 0x8822,
+	0xC4F9, 0x8821, 0xC4FA, 0x881F, 0xC4FB, 0x896A, 0xC4FC, 0x896C,	0xC4FD, 0x89BD, 0xC4FE, 0x8B74, 0xC540, 0x8B77, 0xC541, 0x8B7D,
+	0xC542, 0x8D13, 0xC543, 0x8E8A, 0xC544, 0x8E8D, 0xC545, 0x8E8B,	0xC546, 0x8F5F, 0xC547, 0x8FAF, 0xC548, 0x91BA, 0xC549, 0x942E,
+	0xC54A, 0x9433, 0xC54B, 0x9435, 0xC54C, 0x943A, 0xC54D, 0x9438,	0xC54E, 0x9432, 0xC54F, 0x942B, 0xC550, 0x95E2, 0xC551, 0x9738,
+	0xC552, 0x9739, 0xC553, 0x9732, 0xC554, 0x97FF, 0xC555, 0x9867,	0xC556, 0x9865, 0xC557, 0x9957, 0xC558, 0x9A45, 0xC559, 0x9A43,
+	0xC55A, 0x9A40, 0xC55B, 0x9A3E, 0xC55C, 0x9ACF, 0xC55D, 0x9B54,	0xC55E, 0x9B51, 0xC55F, 0x9C2D, 0xC560, 0x9C25, 0xC561, 0x9DAF,
+	0xC562, 0x9DB4, 0xC563, 0x9DC2, 0xC564, 0x9DB8, 0xC565, 0x9E9D,	0xC566, 0x9EEF, 0xC567, 0x9F19, 0xC568, 0x9F5C, 0xC569, 0x9F66,
+	0xC56A, 0x9F67, 0xC56B, 0x513C, 0xC56C, 0x513B, 0xC56D, 0x56C8,	0xC56E, 0x56CA, 0xC56F, 0x56C9, 0xC570, 0x5B7F, 0xC571, 0x5DD4,
+	0xC572, 0x5DD2, 0xC573, 0x5F4E, 0xC574, 0x61FF, 0xC575, 0x6524,	0xC576, 0x6B0A, 0xC577, 0x6B61, 0xC578, 0x7051, 0xC579, 0x7058,
+	0xC57A, 0x7380, 0xC57B, 0x74E4, 0xC57C, 0x758A, 0xC57D, 0x766E,	0xC57E, 0x766C, 0xC5A1, 0x79B3, 0xC5A2, 0x7C60, 0xC5A3, 0x7C5F,
+	0xC5A4, 0x807E, 0xC5A5, 0x807D, 0xC5A6, 0x81DF, 0xC5A7, 0x8972,	0xC5A8, 0x896F, 0xC5A9, 0x89FC, 0xC5AA, 0x8B80, 0xC5AB, 0x8D16,
+	0xC5AC, 0x8D17, 0xC5AD, 0x8E91, 0xC5AE, 0x8E93, 0xC5AF, 0x8F61,	0xC5B0, 0x9148, 0xC5B1, 0x9444, 0xC5B2, 0x9451, 0xC5B3, 0x9452,
+	0xC5B4, 0x973D, 0xC5B5, 0x973E, 0xC5B6, 0x97C3, 0xC5B7, 0x97C1,	0xC5B8, 0x986B, 0xC5B9, 0x9955, 0xC5BA, 0x9A55, 0xC5BB, 0x9A4D,
+	0xC5BC, 0x9AD2, 0xC5BD, 0x9B1A, 0xC5BE, 0x9C49, 0xC5BF, 0x9C31,	0xC5C0, 0x9C3E, 0xC5C1, 0x9C3B, 0xC5C2, 0x9DD3, 0xC5C3, 0x9DD7,
+	0xC5C4, 0x9F34, 0xC5C5, 0x9F6C, 0xC5C6, 0x9F6A, 0xC5C7, 0x9F94,	0xC5C8, 0x56CC, 0xC5C9, 0x5DD6, 0xC5CA, 0x6200, 0xC5CB, 0x6523,
+	0xC5CC, 0x652B, 0xC5CD, 0x652A, 0xC5CE, 0x66EC, 0xC5CF, 0x6B10,	0xC5D0, 0x74DA, 0xC5D1, 0x7ACA, 0xC5D2, 0x7C64, 0xC5D3, 0x7C63,
+	0xC5D4, 0x7C65, 0xC5D5, 0x7E93, 0xC5D6, 0x7E96, 0xC5D7, 0x7E94,	0xC5D8, 0x81E2, 0xC5D9, 0x8638, 0xC5DA, 0x863F, 0xC5DB, 0x8831,
+	0xC5DC, 0x8B8A, 0xC5DD, 0x9090, 0xC5DE, 0x908F, 0xC5DF, 0x9463,	0xC5E0, 0x9460, 0xC5E1, 0x9464, 0xC5E2, 0x9768, 0xC5E3, 0x986F,
+	0xC5E4, 0x995C, 0xC5E5, 0x9A5A, 0xC5E6, 0x9A5B, 0xC5E7, 0x9A57,	0xC5E8, 0x9AD3, 0xC5E9, 0x9AD4, 0xC5EA, 0x9AD1, 0xC5EB, 0x9C54,
+	0xC5EC, 0x9C57, 0xC5ED, 0x9C56, 0xC5EE, 0x9DE5, 0xC5EF, 0x9E9F,	0xC5F0, 0x9EF4, 0xC5F1, 0x56D1, 0xC5F2, 0x58E9, 0xC5F3, 0x652C,
+	0xC5F4, 0x705E, 0xC5F5, 0x7671, 0xC5F6, 0x7672, 0xC5F7, 0x77D7,	0xC5F8, 0x7F50, 0xC5F9, 0x7F88, 0xC5FA, 0x8836, 0xC5FB, 0x8839,
+	0xC5FC, 0x8862, 0xC5FD, 0x8B93, 0xC5FE, 0x8B92, 0xC640, 0x8B96,	0xC641, 0x8277, 0xC642, 0x8D1B, 0xC643, 0x91C0, 0xC644, 0x946A,
+	0xC645, 0x9742, 0xC646, 0x9748, 0xC647, 0x9744, 0xC648, 0x97C6,	0xC649, 0x9870, 0xC64A, 0x9A5F, 0xC64B, 0x9B22, 0xC64C, 0x9B58,
+	0xC64D, 0x9C5F, 0xC64E, 0x9DF9, 0xC64F, 0x9DFA, 0xC650, 0x9E7C,	0xC651, 0x9E7D, 0xC652, 0x9F07, 0xC653, 0x9F77, 0xC654, 0x9F72,
+	0xC655, 0x5EF3, 0xC656, 0x6B16, 0xC657, 0x7063, 0xC658, 0x7C6C,	0xC659, 0x7C6E, 0xC65A, 0x883B, 0xC65B, 0x89C0, 0xC65C, 0x8EA1,
+	0xC65D, 0x91C1, 0xC65E, 0x9472, 0xC65F, 0x9470, 0xC660, 0x9871,	0xC661, 0x995E, 0xC662, 0x9AD6, 0xC663, 0x9B23, 0xC664, 0x9ECC,
+	0xC665, 0x7064, 0xC666, 0x77DA, 0xC667, 0x8B9A, 0xC668, 0x9477,	0xC669, 0x97C9, 0xC66A, 0x9A62, 0xC66B, 0x9A65, 0xC66C, 0x7E9C,
+	0xC66D, 0x8B9C, 0xC66E, 0x8EAA, 0xC66F, 0x91C5, 0xC670, 0x947D,	0xC671, 0x947E, 0xC672, 0x947C, 0xC673, 0x9C77, 0xC674, 0x9C78,
+	0xC675, 0x9EF7, 0xC676, 0x8C54, 0xC677, 0x947F, 0xC678, 0x9E1A,	0xC679, 0x7228, 0xC67A, 0x9A6A, 0xC67B, 0x9B31, 0xC67C, 0x9E1B,
+	0xC67D, 0x9E1E, 0xC67E, 0x7C72, 0xC940, 0x4E42, 0xC941, 0x4E5C,	0xC942, 0x51F5, 0xC943, 0x531A, 0xC944, 0x5382, 0xC945, 0x4E07,
+	0xC946, 0x4E0C, 0xC947, 0x4E47, 0xC948, 0x4E8D, 0xC949, 0x56D7,	0xC94A, 0xFA0C, 0xC94B, 0x5C6E, 0xC94C, 0x5F73, 0xC94D, 0x4E0F,
+	0xC94E, 0x5187, 0xC94F, 0x4E0E, 0xC950, 0x4E2E, 0xC951, 0x4E93,	0xC952, 0x4EC2, 0xC953, 0x4EC9, 0xC954, 0x4EC8, 0xC955, 0x5198,
+	0xC956, 0x52FC, 0xC957, 0x536C, 0xC958, 0x53B9, 0xC959, 0x5720,	0xC95A, 0x5903, 0xC95B, 0x592C, 0xC95C, 0x5C10, 0xC95D, 0x5DFF,
+	0xC95E, 0x65E1, 0xC95F, 0x6BB3, 0xC960, 0x6BCC, 0xC961, 0x6C14,	0xC962, 0x723F, 0xC963, 0x4E31, 0xC964, 0x4E3C, 0xC965, 0x4EE8,
+	0xC966, 0x4EDC, 0xC967, 0x4EE9, 0xC968, 0x4EE1, 0xC969, 0x4EDD,	0xC96A, 0x4EDA, 0xC96B, 0x520C, 0xC96C, 0x531C, 0xC96D, 0x534C,
+	0xC96E, 0x5722, 0xC96F, 0x5723, 0xC970, 0x5917, 0xC971, 0x592F,	0xC972, 0x5B81, 0xC973, 0x5B84, 0xC974, 0x5C12, 0xC975, 0x5C3B,
+	0xC976, 0x5C74, 0xC977, 0x5C73, 0xC978, 0x5E04, 0xC979, 0x5E80,	0xC97A, 0x5E82, 0xC97B, 0x5FC9, 0xC97C, 0x6209, 0xC97D, 0x6250,
+	0xC97E, 0x6C15, 0xC9A1, 0x6C36, 0xC9A2, 0x6C43, 0xC9A3, 0x6C3F,	0xC9A4, 0x6C3B, 0xC9A5, 0x72AE, 0xC9A6, 0x72B0, 0xC9A7, 0x738A,
+	0xC9A8, 0x79B8, 0xC9A9, 0x808A, 0xC9AA, 0x961E, 0xC9AB, 0x4F0E,	0xC9AC, 0x4F18, 0xC9AD, 0x4F2C, 0xC9AE, 0x4EF5, 0xC9AF, 0x4F14,
+	0xC9B0, 0x4EF1, 0xC9B1, 0x4F00, 0xC9B2, 0x4EF7, 0xC9B3, 0x4F08,	0xC9B4, 0x4F1D, 0xC9B5, 0x4F02, 0xC9B6, 0x4F05, 0xC9B7, 0x4F22,
+	0xC9B8, 0x4F13, 0xC9B9, 0x4F04, 0xC9BA, 0x4EF4, 0xC9BB, 0x4F12,	0xC9BC, 0x51B1, 0xC9BD, 0x5213, 0xC9BE, 0x5209, 0xC9BF, 0x5210,
+	0xC9C0, 0x52A6, 0xC9C1, 0x5322, 0xC9C2, 0x531F, 0xC9C3, 0x534D,	0xC9C4, 0x538A, 0xC9C5, 0x5407, 0xC9C6, 0x56E1, 0xC9C7, 0x56DF,
+	0xC9C8, 0x572E, 0xC9C9, 0x572A, 0xC9CA, 0x5734, 0xC9CB, 0x593C,	0xC9CC, 0x5980, 0xC9CD, 0x597C, 0xC9CE, 0x5985, 0xC9CF, 0x597B,
+	0xC9D0, 0x597E, 0xC9D1, 0x5977, 0xC9D2, 0x597F, 0xC9D3, 0x5B56,	0xC9D4, 0x5C15, 0xC9D5, 0x5C25, 0xC9D6, 0x5C7C, 0xC9D7, 0x5C7A,
+	0xC9D8, 0x5C7B, 0xC9D9, 0x5C7E, 0xC9DA, 0x5DDF, 0xC9DB, 0x5E75,	0xC9DC, 0x5E84, 0xC9DD, 0x5F02, 0xC9DE, 0x5F1A, 0xC9DF, 0x5F74,
+	0xC9E0, 0x5FD5, 0xC9E1, 0x5FD4, 0xC9E2, 0x5FCF, 0xC9E3, 0x625C,	0xC9E4, 0x625E, 0xC9E5, 0x6264, 0xC9E6, 0x6261, 0xC9E7, 0x6266,
+	0xC9E8, 0x6262, 0xC9E9, 0x6259, 0xC9EA, 0x6260, 0xC9EB, 0x625A,	0xC9EC, 0x6265, 0xC9ED, 0x65EF, 0xC9EE, 0x65EE, 0xC9EF, 0x673E,
+	0xC9F0, 0x6739, 0xC9F1, 0x6738, 0xC9F2, 0x673B, 0xC9F3, 0x673A,	0xC9F4, 0x673F, 0xC9F5, 0x673C, 0xC9F6, 0x6733, 0xC9F7, 0x6C18,
+	0xC9F8, 0x6C46, 0xC9F9, 0x6C52, 0xC9FA, 0x6C5C, 0xC9FB, 0x6C4F,	0xC9FC, 0x6C4A, 0xC9FD, 0x6C54, 0xC9FE, 0x6C4B, 0xCA40, 0x6C4C,
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+	0xCE7D, 0x5CCB, 0xCE7E, 0x5CDB, 0xCEA1, 0x5CDE, 0xCEA2, 0x5CDA,	0xCEA3, 0x5CC9, 0xCEA4, 0x5CC7, 0xCEA5, 0x5CCA, 0xCEA6, 0x5CD6,
+	0xCEA7, 0x5CD3, 0xCEA8, 0x5CD4, 0xCEA9, 0x5CCF, 0xCEAA, 0x5CC8,	0xCEAB, 0x5CC6, 0xCEAC, 0x5CCE, 0xCEAD, 0x5CDF, 0xCEAE, 0x5CF8,
+	0xCEAF, 0x5DF9, 0xCEB0, 0x5E21, 0xCEB1, 0x5E22, 0xCEB2, 0x5E23,	0xCEB3, 0x5E20, 0xCEB4, 0x5E24, 0xCEB5, 0x5EB0, 0xCEB6, 0x5EA4,
+	0xCEB7, 0x5EA2, 0xCEB8, 0x5E9B, 0xCEB9, 0x5EA3, 0xCEBA, 0x5EA5,	0xCEBB, 0x5F07, 0xCEBC, 0x5F2E, 0xCEBD, 0x5F56, 0xCEBE, 0x5F86,
+	0xCEBF, 0x6037, 0xCEC0, 0x6039, 0xCEC1, 0x6054, 0xCEC2, 0x6072,	0xCEC3, 0x605E, 0xCEC4, 0x6045, 0xCEC5, 0x6053, 0xCEC6, 0x6047,
+	0xCEC7, 0x6049, 0xCEC8, 0x605B, 0xCEC9, 0x604C, 0xCECA, 0x6040,	0xCECB, 0x6042, 0xCECC, 0x605F, 0xCECD, 0x6024, 0xCECE, 0x6044,
+	0xCECF, 0x6058, 0xCED0, 0x6066, 0xCED1, 0x606E, 0xCED2, 0x6242,	0xCED3, 0x6243, 0xCED4, 0x62CF, 0xCED5, 0x630D, 0xCED6, 0x630B,
+	0xCED7, 0x62F5, 0xCED8, 0x630E, 0xCED9, 0x6303, 0xCEDA, 0x62EB,	0xCEDB, 0x62F9, 0xCEDC, 0x630F, 0xCEDD, 0x630C, 0xCEDE, 0x62F8,
+	0xCEDF, 0x62F6, 0xCEE0, 0x6300, 0xCEE1, 0x6313, 0xCEE2, 0x6314,	0xCEE3, 0x62FA, 0xCEE4, 0x6315, 0xCEE5, 0x62FB, 0xCEE6, 0x62F0,
+	0xCEE7, 0x6541, 0xCEE8, 0x6543, 0xCEE9, 0x65AA, 0xCEEA, 0x65BF,	0xCEEB, 0x6636, 0xCEEC, 0x6621, 0xCEED, 0x6632, 0xCEEE, 0x6635,
+	0xCEEF, 0x661C, 0xCEF0, 0x6626, 0xCEF1, 0x6622, 0xCEF2, 0x6633,	0xCEF3, 0x662B, 0xCEF4, 0x663A, 0xCEF5, 0x661D, 0xCEF6, 0x6634,
+	0xCEF7, 0x6639, 0xCEF8, 0x662E, 0xCEF9, 0x670F, 0xCEFA, 0x6710,	0xCEFB, 0x67C1, 0xCEFC, 0x67F2, 0xCEFD, 0x67C8, 0xCEFE, 0x67BA,
+	0xCF40, 0x67DC, 0xCF41, 0x67BB, 0xCF42, 0x67F8, 0xCF43, 0x67D8,	0xCF44, 0x67C0, 0xCF45, 0x67B7, 0xCF46, 0x67C5, 0xCF47, 0x67EB,
+	0xCF48, 0x67E4, 0xCF49, 0x67DF, 0xCF4A, 0x67B5, 0xCF4B, 0x67CD,	0xCF4C, 0x67B3, 0xCF4D, 0x67F7, 0xCF4E, 0x67F6, 0xCF4F, 0x67EE,
+	0xCF50, 0x67E3, 0xCF51, 0x67C2, 0xCF52, 0x67B9, 0xCF53, 0x67CE,	0xCF54, 0x67E7, 0xCF55, 0x67F0, 0xCF56, 0x67B2, 0xCF57, 0x67FC,
+	0xCF58, 0x67C6, 0xCF59, 0x67ED, 0xCF5A, 0x67CC, 0xCF5B, 0x67AE,	0xCF5C, 0x67E6, 0xCF5D, 0x67DB, 0xCF5E, 0x67FA, 0xCF5F, 0x67C9,
+	0xCF60, 0x67CA, 0xCF61, 0x67C3, 0xCF62, 0x67EA, 0xCF63, 0x67CB,	0xCF64, 0x6B28, 0xCF65, 0x6B82, 0xCF66, 0x6B84, 0xCF67, 0x6BB6,
+	0xCF68, 0x6BD6, 0xCF69, 0x6BD8, 0xCF6A, 0x6BE0, 0xCF6B, 0x6C20,	0xCF6C, 0x6C21, 0xCF6D, 0x6D28, 0xCF6E, 0x6D34, 0xCF6F, 0x6D2D,
+	0xCF70, 0x6D1F, 0xCF71, 0x6D3C, 0xCF72, 0x6D3F, 0xCF73, 0x6D12,	0xCF74, 0x6D0A, 0xCF75, 0x6CDA, 0xCF76, 0x6D33, 0xCF77, 0x6D04,
+	0xCF78, 0x6D19, 0xCF79, 0x6D3A, 0xCF7A, 0x6D1A, 0xCF7B, 0x6D11,	0xCF7C, 0x6D00, 0xCF7D, 0x6D1D, 0xCF7E, 0x6D42, 0xCFA1, 0x6D01,
+	0xCFA2, 0x6D18, 0xCFA3, 0x6D37, 0xCFA4, 0x6D03, 0xCFA5, 0x6D0F,	0xCFA6, 0x6D40, 0xCFA7, 0x6D07, 0xCFA8, 0x6D20, 0xCFA9, 0x6D2C,
+	0xCFAA, 0x6D08, 0xCFAB, 0x6D22, 0xCFAC, 0x6D09, 0xCFAD, 0x6D10,	0xCFAE, 0x70B7, 0xCFAF, 0x709F, 0xCFB0, 0x70BE, 0xCFB1, 0x70B1,
+	0xCFB2, 0x70B0, 0xCFB3, 0x70A1, 0xCFB4, 0x70B4, 0xCFB5, 0x70B5,	0xCFB6, 0x70A9, 0xCFB7, 0x7241, 0xCFB8, 0x7249, 0xCFB9, 0x724A,
+	0xCFBA, 0x726C, 0xCFBB, 0x7270, 0xCFBC, 0x7273, 0xCFBD, 0x726E,	0xCFBE, 0x72CA, 0xCFBF, 0x72E4, 0xCFC0, 0x72E8, 0xCFC1, 0x72EB,
+	0xCFC2, 0x72DF, 0xCFC3, 0x72EA, 0xCFC4, 0x72E6, 0xCFC5, 0x72E3,	0xCFC6, 0x7385, 0xCFC7, 0x73CC, 0xCFC8, 0x73C2, 0xCFC9, 0x73C8,
+	0xCFCA, 0x73C5, 0xCFCB, 0x73B9, 0xCFCC, 0x73B6, 0xCFCD, 0x73B5,	0xCFCE, 0x73B4, 0xCFCF, 0x73EB, 0xCFD0, 0x73BF, 0xCFD1, 0x73C7,
+	0xCFD2, 0x73BE, 0xCFD3, 0x73C3, 0xCFD4, 0x73C6, 0xCFD5, 0x73B8,	0xCFD6, 0x73CB, 0xCFD7, 0x74EC, 0xCFD8, 0x74EE, 0xCFD9, 0x752E,
+	0xCFDA, 0x7547, 0xCFDB, 0x7548, 0xCFDC, 0x75A7, 0xCFDD, 0x75AA,	0xCFDE, 0x7679, 0xCFDF, 0x76C4, 0xCFE0, 0x7708, 0xCFE1, 0x7703,
+	0xCFE2, 0x7704, 0xCFE3, 0x7705, 0xCFE4, 0x770A, 0xCFE5, 0x76F7,	0xCFE6, 0x76FB, 0xCFE7, 0x76FA, 0xCFE8, 0x77E7, 0xCFE9, 0x77E8,
+	0xCFEA, 0x7806, 0xCFEB, 0x7811, 0xCFEC, 0x7812, 0xCFED, 0x7805,	0xCFEE, 0x7810, 0xCFEF, 0x780F, 0xCFF0, 0x780E, 0xCFF1, 0x7809,
+	0xCFF2, 0x7803, 0xCFF3, 0x7813, 0xCFF4, 0x794A, 0xCFF5, 0x794C,	0xCFF6, 0x794B, 0xCFF7, 0x7945, 0xCFF8, 0x7944, 0xCFF9, 0x79D5,
+	0xCFFA, 0x79CD, 0xCFFB, 0x79CF, 0xCFFC, 0x79D6, 0xCFFD, 0x79CE,	0xCFFE, 0x7A80, 0xD040, 0x7A7E, 0xD041, 0x7AD1, 0xD042, 0x7B00,
+	0xD043, 0x7B01, 0xD044, 0x7C7A, 0xD045, 0x7C78, 0xD046, 0x7C79,	0xD047, 0x7C7F, 0xD048, 0x7C80, 0xD049, 0x7C81, 0xD04A, 0x7D03,
+	0xD04B, 0x7D08, 0xD04C, 0x7D01, 0xD04D, 0x7F58, 0xD04E, 0x7F91,	0xD04F, 0x7F8D, 0xD050, 0x7FBE, 0xD051, 0x8007, 0xD052, 0x800E,
+	0xD053, 0x800F, 0xD054, 0x8014, 0xD055, 0x8037, 0xD056, 0x80D8,	0xD057, 0x80C7, 0xD058, 0x80E0, 0xD059, 0x80D1, 0xD05A, 0x80C8,
+	0xD05B, 0x80C2, 0xD05C, 0x80D0, 0xD05D, 0x80C5, 0xD05E, 0x80E3,	0xD05F, 0x80D9, 0xD060, 0x80DC, 0xD061, 0x80CA, 0xD062, 0x80D5,
+	0xD063, 0x80C9, 0xD064, 0x80CF, 0xD065, 0x80D7, 0xD066, 0x80E6,	0xD067, 0x80CD, 0xD068, 0x81FF, 0xD069, 0x8221, 0xD06A, 0x8294,
+	0xD06B, 0x82D9, 0xD06C, 0x82FE, 0xD06D, 0x82F9, 0xD06E, 0x8307,	0xD06F, 0x82E8, 0xD070, 0x8300, 0xD071, 0x82D5, 0xD072, 0x833A,
+	0xD073, 0x82EB, 0xD074, 0x82D6, 0xD075, 0x82F4, 0xD076, 0x82EC,	0xD077, 0x82E1, 0xD078, 0x82F2, 0xD079, 0x82F5, 0xD07A, 0x830C,
+	0xD07B, 0x82FB, 0xD07C, 0x82F6, 0xD07D, 0x82F0, 0xD07E, 0x82EA,	0xD0A1, 0x82E4, 0xD0A2, 0x82E0, 0xD0A3, 0x82FA, 0xD0A4, 0x82F3,
+	0xD0A5, 0x82ED, 0xD0A6, 0x8677, 0xD0A7, 0x8674, 0xD0A8, 0x867C,	0xD0A9, 0x8673, 0xD0AA, 0x8841, 0xD0AB, 0x884E, 0xD0AC, 0x8867,
+	0xD0AD, 0x886A, 0xD0AE, 0x8869, 0xD0AF, 0x89D3, 0xD0B0, 0x8A04,	0xD0B1, 0x8A07, 0xD0B2, 0x8D72, 0xD0B3, 0x8FE3, 0xD0B4, 0x8FE1,
+	0xD0B5, 0x8FEE, 0xD0B6, 0x8FE0, 0xD0B7, 0x90F1, 0xD0B8, 0x90BD,	0xD0B9, 0x90BF, 0xD0BA, 0x90D5, 0xD0BB, 0x90C5, 0xD0BC, 0x90BE,
+	0xD0BD, 0x90C7, 0xD0BE, 0x90CB, 0xD0BF, 0x90C8, 0xD0C0, 0x91D4,	0xD0C1, 0x91D3, 0xD0C2, 0x9654, 0xD0C3, 0x964F, 0xD0C4, 0x9651,
+	0xD0C5, 0x9653, 0xD0C6, 0x964A, 0xD0C7, 0x964E, 0xD0C8, 0x501E,	0xD0C9, 0x5005, 0xD0CA, 0x5007, 0xD0CB, 0x5013, 0xD0CC, 0x5022,
+	0xD0CD, 0x5030, 0xD0CE, 0x501B, 0xD0CF, 0x4FF5, 0xD0D0, 0x4FF4,	0xD0D1, 0x5033, 0xD0D2, 0x5037, 0xD0D3, 0x502C, 0xD0D4, 0x4FF6,
+	0xD0D5, 0x4FF7, 0xD0D6, 0x5017, 0xD0D7, 0x501C, 0xD0D8, 0x5020,	0xD0D9, 0x5027, 0xD0DA, 0x5035, 0xD0DB, 0x502F, 0xD0DC, 0x5031,
+	0xD0DD, 0x500E, 0xD0DE, 0x515A, 0xD0DF, 0x5194, 0xD0E0, 0x5193,	0xD0E1, 0x51CA, 0xD0E2, 0x51C4, 0xD0E3, 0x51C5, 0xD0E4, 0x51C8,
+	0xD0E5, 0x51CE, 0xD0E6, 0x5261, 0xD0E7, 0x525A, 0xD0E8, 0x5252,	0xD0E9, 0x525E, 0xD0EA, 0x525F, 0xD0EB, 0x5255, 0xD0EC, 0x5262,
+	0xD0ED, 0x52CD, 0xD0EE, 0x530E, 0xD0EF, 0x539E, 0xD0F0, 0x5526,	0xD0F1, 0x54E2, 0xD0F2, 0x5517, 0xD0F3, 0x5512, 0xD0F4, 0x54E7,
+	0xD0F5, 0x54F3, 0xD0F6, 0x54E4, 0xD0F7, 0x551A, 0xD0F8, 0x54FF,	0xD0F9, 0x5504, 0xD0FA, 0x5508, 0xD0FB, 0x54EB, 0xD0FC, 0x5511,
+	0xD0FD, 0x5505, 0xD0FE, 0x54F1, 0xD140, 0x550A, 0xD141, 0x54FB,	0xD142, 0x54F7, 0xD143, 0x54F8, 0xD144, 0x54E0, 0xD145, 0x550E,
+	0xD146, 0x5503, 0xD147, 0x550B, 0xD148, 0x5701, 0xD149, 0x5702,	0xD14A, 0x57CC, 0xD14B, 0x5832, 0xD14C, 0x57D5, 0xD14D, 0x57D2,
+	0xD14E, 0x57BA, 0xD14F, 0x57C6, 0xD150, 0x57BD, 0xD151, 0x57BC,	0xD152, 0x57B8, 0xD153, 0x57B6, 0xD154, 0x57BF, 0xD155, 0x57C7,
+	0xD156, 0x57D0, 0xD157, 0x57B9, 0xD158, 0x57C1, 0xD159, 0x590E,	0xD15A, 0x594A, 0xD15B, 0x5A19, 0xD15C, 0x5A16, 0xD15D, 0x5A2D,
+	0xD15E, 0x5A2E, 0xD15F, 0x5A15, 0xD160, 0x5A0F, 0xD161, 0x5A17,	0xD162, 0x5A0A, 0xD163, 0x5A1E, 0xD164, 0x5A33, 0xD165, 0x5B6C,
+	0xD166, 0x5BA7, 0xD167, 0x5BAD, 0xD168, 0x5BAC, 0xD169, 0x5C03,	0xD16A, 0x5C56, 0xD16B, 0x5C54, 0xD16C, 0x5CEC, 0xD16D, 0x5CFF,
+	0xD16E, 0x5CEE, 0xD16F, 0x5CF1, 0xD170, 0x5CF7, 0xD171, 0x5D00,	0xD172, 0x5CF9, 0xD173, 0x5E29, 0xD174, 0x5E28, 0xD175, 0x5EA8,
+	0xD176, 0x5EAE, 0xD177, 0x5EAA, 0xD178, 0x5EAC, 0xD179, 0x5F33,	0xD17A, 0x5F30, 0xD17B, 0x5F67, 0xD17C, 0x605D, 0xD17D, 0x605A,
+	0xD17E, 0x6067, 0xD1A1, 0x6041, 0xD1A2, 0x60A2, 0xD1A3, 0x6088,	0xD1A4, 0x6080, 0xD1A5, 0x6092, 0xD1A6, 0x6081, 0xD1A7, 0x609D,
+	0xD1A8, 0x6083, 0xD1A9, 0x6095, 0xD1AA, 0x609B, 0xD1AB, 0x6097,	0xD1AC, 0x6087, 0xD1AD, 0x609C, 0xD1AE, 0x608E, 0xD1AF, 0x6219,
+	0xD1B0, 0x6246, 0xD1B1, 0x62F2, 0xD1B2, 0x6310, 0xD1B3, 0x6356,	0xD1B4, 0x632C, 0xD1B5, 0x6344, 0xD1B6, 0x6345, 0xD1B7, 0x6336,
+	0xD1B8, 0x6343, 0xD1B9, 0x63E4, 0xD1BA, 0x6339, 0xD1BB, 0x634B,	0xD1BC, 0x634A, 0xD1BD, 0x633C, 0xD1BE, 0x6329, 0xD1BF, 0x6341,
+	0xD1C0, 0x6334, 0xD1C1, 0x6358, 0xD1C2, 0x6354, 0xD1C3, 0x6359,	0xD1C4, 0x632D, 0xD1C5, 0x6347, 0xD1C6, 0x6333, 0xD1C7, 0x635A,
+	0xD1C8, 0x6351, 0xD1C9, 0x6338, 0xD1CA, 0x6357, 0xD1CB, 0x6340,	0xD1CC, 0x6348, 0xD1CD, 0x654A, 0xD1CE, 0x6546, 0xD1CF, 0x65C6,
+	0xD1D0, 0x65C3, 0xD1D1, 0x65C4, 0xD1D2, 0x65C2, 0xD1D3, 0x664A,	0xD1D4, 0x665F, 0xD1D5, 0x6647, 0xD1D6, 0x6651, 0xD1D7, 0x6712,
+	0xD1D8, 0x6713, 0xD1D9, 0x681F, 0xD1DA, 0x681A, 0xD1DB, 0x6849,	0xD1DC, 0x6832, 0xD1DD, 0x6833, 0xD1DE, 0x683B, 0xD1DF, 0x684B,
+	0xD1E0, 0x684F, 0xD1E1, 0x6816, 0xD1E2, 0x6831, 0xD1E3, 0x681C,	0xD1E4, 0x6835, 0xD1E5, 0x682B, 0xD1E6, 0x682D, 0xD1E7, 0x682F,
+	0xD1E8, 0x684E, 0xD1E9, 0x6844, 0xD1EA, 0x6834, 0xD1EB, 0x681D,	0xD1EC, 0x6812, 0xD1ED, 0x6814, 0xD1EE, 0x6826, 0xD1EF, 0x6828,
+	0xD1F0, 0x682E, 0xD1F1, 0x684D, 0xD1F2, 0x683A, 0xD1F3, 0x6825,	0xD1F4, 0x6820, 0xD1F5, 0x6B2C, 0xD1F6, 0x6B2F, 0xD1F7, 0x6B2D,
+	0xD1F8, 0x6B31, 0xD1F9, 0x6B34, 0xD1FA, 0x6B6D, 0xD1FB, 0x8082,	0xD1FC, 0x6B88, 0xD1FD, 0x6BE6, 0xD1FE, 0x6BE4, 0xD240, 0x6BE8,
+	0xD241, 0x6BE3, 0xD242, 0x6BE2, 0xD243, 0x6BE7, 0xD244, 0x6C25,	0xD245, 0x6D7A, 0xD246, 0x6D63, 0xD247, 0x6D64, 0xD248, 0x6D76,
+	0xD249, 0x6D0D, 0xD24A, 0x6D61, 0xD24B, 0x6D92, 0xD24C, 0x6D58,	0xD24D, 0x6D62, 0xD24E, 0x6D6D, 0xD24F, 0x6D6F, 0xD250, 0x6D91,
+	0xD251, 0x6D8D, 0xD252, 0x6DEF, 0xD253, 0x6D7F, 0xD254, 0x6D86,	0xD255, 0x6D5E, 0xD256, 0x6D67, 0xD257, 0x6D60, 0xD258, 0x6D97,
+	0xD259, 0x6D70, 0xD25A, 0x6D7C, 0xD25B, 0x6D5F, 0xD25C, 0x6D82,	0xD25D, 0x6D98, 0xD25E, 0x6D2F, 0xD25F, 0x6D68, 0xD260, 0x6D8B,
+	0xD261, 0x6D7E, 0xD262, 0x6D80, 0xD263, 0x6D84, 0xD264, 0x6D16,	0xD265, 0x6D83, 0xD266, 0x6D7B, 0xD267, 0x6D7D, 0xD268, 0x6D75,
+	0xD269, 0x6D90, 0xD26A, 0x70DC, 0xD26B, 0x70D3, 0xD26C, 0x70D1,	0xD26D, 0x70DD, 0xD26E, 0x70CB, 0xD26F, 0x7F39, 0xD270, 0x70E2,
+	0xD271, 0x70D7, 0xD272, 0x70D2, 0xD273, 0x70DE, 0xD274, 0x70E0,	0xD275, 0x70D4, 0xD276, 0x70CD, 0xD277, 0x70C5, 0xD278, 0x70C6,
+	0xD279, 0x70C7, 0xD27A, 0x70DA, 0xD27B, 0x70CE, 0xD27C, 0x70E1,	0xD27D, 0x7242, 0xD27E, 0x7278, 0xD2A1, 0x7277, 0xD2A2, 0x7276,
+	0xD2A3, 0x7300, 0xD2A4, 0x72FA, 0xD2A5, 0x72F4, 0xD2A6, 0x72FE,	0xD2A7, 0x72F6, 0xD2A8, 0x72F3, 0xD2A9, 0x72FB, 0xD2AA, 0x7301,
+	0xD2AB, 0x73D3, 0xD2AC, 0x73D9, 0xD2AD, 0x73E5, 0xD2AE, 0x73D6,	0xD2AF, 0x73BC, 0xD2B0, 0x73E7, 0xD2B1, 0x73E3, 0xD2B2, 0x73E9,
+	0xD2B3, 0x73DC, 0xD2B4, 0x73D2, 0xD2B5, 0x73DB, 0xD2B6, 0x73D4,	0xD2B7, 0x73DD, 0xD2B8, 0x73DA, 0xD2B9, 0x73D7, 0xD2BA, 0x73D8,
+	0xD2BB, 0x73E8, 0xD2BC, 0x74DE, 0xD2BD, 0x74DF, 0xD2BE, 0x74F4,	0xD2BF, 0x74F5, 0xD2C0, 0x7521, 0xD2C1, 0x755B, 0xD2C2, 0x755F,
+	0xD2C3, 0x75B0, 0xD2C4, 0x75C1, 0xD2C5, 0x75BB, 0xD2C6, 0x75C4,	0xD2C7, 0x75C0, 0xD2C8, 0x75BF, 0xD2C9, 0x75B6, 0xD2CA, 0x75BA,
+	0xD2CB, 0x768A, 0xD2CC, 0x76C9, 0xD2CD, 0x771D, 0xD2CE, 0x771B,	0xD2CF, 0x7710, 0xD2D0, 0x7713, 0xD2D1, 0x7712, 0xD2D2, 0x7723,
+	0xD2D3, 0x7711, 0xD2D4, 0x7715, 0xD2D5, 0x7719, 0xD2D6, 0x771A,	0xD2D7, 0x7722, 0xD2D8, 0x7727, 0xD2D9, 0x7823, 0xD2DA, 0x782C,
+	0xD2DB, 0x7822, 0xD2DC, 0x7835, 0xD2DD, 0x782F, 0xD2DE, 0x7828,	0xD2DF, 0x782E, 0xD2E0, 0x782B, 0xD2E1, 0x7821, 0xD2E2, 0x7829,
+	0xD2E3, 0x7833, 0xD2E4, 0x782A, 0xD2E5, 0x7831, 0xD2E6, 0x7954,	0xD2E7, 0x795B, 0xD2E8, 0x794F, 0xD2E9, 0x795C, 0xD2EA, 0x7953,
+	0xD2EB, 0x7952, 0xD2EC, 0x7951, 0xD2ED, 0x79EB, 0xD2EE, 0x79EC,	0xD2EF, 0x79E0, 0xD2F0, 0x79EE, 0xD2F1, 0x79ED, 0xD2F2, 0x79EA,
+	0xD2F3, 0x79DC, 0xD2F4, 0x79DE, 0xD2F5, 0x79DD, 0xD2F6, 0x7A86,	0xD2F7, 0x7A89, 0xD2F8, 0x7A85, 0xD2F9, 0x7A8B, 0xD2FA, 0x7A8C,
+	0xD2FB, 0x7A8A, 0xD2FC, 0x7A87, 0xD2FD, 0x7AD8, 0xD2FE, 0x7B10,	0xD340, 0x7B04, 0xD341, 0x7B13, 0xD342, 0x7B05, 0xD343, 0x7B0F,
+	0xD344, 0x7B08, 0xD345, 0x7B0A, 0xD346, 0x7B0E, 0xD347, 0x7B09,	0xD348, 0x7B12, 0xD349, 0x7C84, 0xD34A, 0x7C91, 0xD34B, 0x7C8A,
+	0xD34C, 0x7C8C, 0xD34D, 0x7C88, 0xD34E, 0x7C8D, 0xD34F, 0x7C85,	0xD350, 0x7D1E, 0xD351, 0x7D1D, 0xD352, 0x7D11, 0xD353, 0x7D0E,
+	0xD354, 0x7D18, 0xD355, 0x7D16, 0xD356, 0x7D13, 0xD357, 0x7D1F,	0xD358, 0x7D12, 0xD359, 0x7D0F, 0xD35A, 0x7D0C, 0xD35B, 0x7F5C,
+	0xD35C, 0x7F61, 0xD35D, 0x7F5E, 0xD35E, 0x7F60, 0xD35F, 0x7F5D,	0xD360, 0x7F5B, 0xD361, 0x7F96, 0xD362, 0x7F92, 0xD363, 0x7FC3,
+	0xD364, 0x7FC2, 0xD365, 0x7FC0, 0xD366, 0x8016, 0xD367, 0x803E,	0xD368, 0x8039, 0xD369, 0x80FA, 0xD36A, 0x80F2, 0xD36B, 0x80F9,
+	0xD36C, 0x80F5, 0xD36D, 0x8101, 0xD36E, 0x80FB, 0xD36F, 0x8100,	0xD370, 0x8201, 0xD371, 0x822F, 0xD372, 0x8225, 0xD373, 0x8333,
+	0xD374, 0x832D, 0xD375, 0x8344, 0xD376, 0x8319, 0xD377, 0x8351,	0xD378, 0x8325, 0xD379, 0x8356, 0xD37A, 0x833F, 0xD37B, 0x8341,
+	0xD37C, 0x8326, 0xD37D, 0x831C, 0xD37E, 0x8322, 0xD3A1, 0x8342,	0xD3A2, 0x834E, 0xD3A3, 0x831B, 0xD3A4, 0x832A, 0xD3A5, 0x8308,
+	0xD3A6, 0x833C, 0xD3A7, 0x834D, 0xD3A8, 0x8316, 0xD3A9, 0x8324,	0xD3AA, 0x8320, 0xD3AB, 0x8337, 0xD3AC, 0x832F, 0xD3AD, 0x8329,
+	0xD3AE, 0x8347, 0xD3AF, 0x8345, 0xD3B0, 0x834C, 0xD3B1, 0x8353,	0xD3B2, 0x831E, 0xD3B3, 0x832C, 0xD3B4, 0x834B, 0xD3B5, 0x8327,
+	0xD3B6, 0x8348, 0xD3B7, 0x8653, 0xD3B8, 0x8652, 0xD3B9, 0x86A2,	0xD3BA, 0x86A8, 0xD3BB, 0x8696, 0xD3BC, 0x868D, 0xD3BD, 0x8691,
+	0xD3BE, 0x869E, 0xD3BF, 0x8687, 0xD3C0, 0x8697, 0xD3C1, 0x8686,	0xD3C2, 0x868B, 0xD3C3, 0x869A, 0xD3C4, 0x8685, 0xD3C5, 0x86A5,
+	0xD3C6, 0x8699, 0xD3C7, 0x86A1, 0xD3C8, 0x86A7, 0xD3C9, 0x8695,	0xD3CA, 0x8698, 0xD3CB, 0x868E, 0xD3CC, 0x869D, 0xD3CD, 0x8690,
+	0xD3CE, 0x8694, 0xD3CF, 0x8843, 0xD3D0, 0x8844, 0xD3D1, 0x886D,	0xD3D2, 0x8875, 0xD3D3, 0x8876, 0xD3D4, 0x8872, 0xD3D5, 0x8880,
+	0xD3D6, 0x8871, 0xD3D7, 0x887F, 0xD3D8, 0x886F, 0xD3D9, 0x8883,	0xD3DA, 0x887E, 0xD3DB, 0x8874, 0xD3DC, 0x887C, 0xD3DD, 0x8A12,
+	0xD3DE, 0x8C47, 0xD3DF, 0x8C57, 0xD3E0, 0x8C7B, 0xD3E1, 0x8CA4,	0xD3E2, 0x8CA3, 0xD3E3, 0x8D76, 0xD3E4, 0x8D78, 0xD3E5, 0x8DB5,
+	0xD3E6, 0x8DB7, 0xD3E7, 0x8DB6, 0xD3E8, 0x8ED1, 0xD3E9, 0x8ED3,	0xD3EA, 0x8FFE, 0xD3EB, 0x8FF5, 0xD3EC, 0x9002, 0xD3ED, 0x8FFF,
+	0xD3EE, 0x8FFB, 0xD3EF, 0x9004, 0xD3F0, 0x8FFC, 0xD3F1, 0x8FF6,	0xD3F2, 0x90D6, 0xD3F3, 0x90E0, 0xD3F4, 0x90D9, 0xD3F5, 0x90DA,
+	0xD3F6, 0x90E3, 0xD3F7, 0x90DF, 0xD3F8, 0x90E5, 0xD3F9, 0x90D8,	0xD3FA, 0x90DB, 0xD3FB, 0x90D7, 0xD3FC, 0x90DC, 0xD3FD, 0x90E4,
+	0xD3FE, 0x9150, 0xD440, 0x914E, 0xD441, 0x914F, 0xD442, 0x91D5,	0xD443, 0x91E2, 0xD444, 0x91DA, 0xD445, 0x965C, 0xD446, 0x965F,
+	0xD447, 0x96BC, 0xD448, 0x98E3, 0xD449, 0x9ADF, 0xD44A, 0x9B2F,	0xD44B, 0x4E7F, 0xD44C, 0x5070, 0xD44D, 0x506A, 0xD44E, 0x5061,
+	0xD44F, 0x505E, 0xD450, 0x5060, 0xD451, 0x5053, 0xD452, 0x504B,	0xD453, 0x505D, 0xD454, 0x5072, 0xD455, 0x5048, 0xD456, 0x504D,
+	0xD457, 0x5041, 0xD458, 0x505B, 0xD459, 0x504A, 0xD45A, 0x5062,	0xD45B, 0x5015, 0xD45C, 0x5045, 0xD45D, 0x505F, 0xD45E, 0x5069,
+	0xD45F, 0x506B, 0xD460, 0x5063, 0xD461, 0x5064, 0xD462, 0x5046,	0xD463, 0x5040, 0xD464, 0x506E, 0xD465, 0x5073, 0xD466, 0x5057,
+	0xD467, 0x5051, 0xD468, 0x51D0, 0xD469, 0x526B, 0xD46A, 0x526D,	0xD46B, 0x526C, 0xD46C, 0x526E, 0xD46D, 0x52D6, 0xD46E, 0x52D3,
+	0xD46F, 0x532D, 0xD470, 0x539C, 0xD471, 0x5575, 0xD472, 0x5576,	0xD473, 0x553C, 0xD474, 0x554D, 0xD475, 0x5550, 0xD476, 0x5534,
+	0xD477, 0x552A, 0xD478, 0x5551, 0xD479, 0x5562, 0xD47A, 0x5536,	0xD47B, 0x5535, 0xD47C, 0x5530, 0xD47D, 0x5552, 0xD47E, 0x5545,
+	0xD4A1, 0x550C, 0xD4A2, 0x5532, 0xD4A3, 0x5565, 0xD4A4, 0x554E,	0xD4A5, 0x5539, 0xD4A6, 0x5548, 0xD4A7, 0x552D, 0xD4A8, 0x553B,
+	0xD4A9, 0x5540, 0xD4AA, 0x554B, 0xD4AB, 0x570A, 0xD4AC, 0x5707,	0xD4AD, 0x57FB, 0xD4AE, 0x5814, 0xD4AF, 0x57E2, 0xD4B0, 0x57F6,
+	0xD4B1, 0x57DC, 0xD4B2, 0x57F4, 0xD4B3, 0x5800, 0xD4B4, 0x57ED,	0xD4B5, 0x57FD, 0xD4B6, 0x5808, 0xD4B7, 0x57F8, 0xD4B8, 0x580B,
+	0xD4B9, 0x57F3, 0xD4BA, 0x57CF, 0xD4BB, 0x5807, 0xD4BC, 0x57EE,	0xD4BD, 0x57E3, 0xD4BE, 0x57F2, 0xD4BF, 0x57E5, 0xD4C0, 0x57EC,
+	0xD4C1, 0x57E1, 0xD4C2, 0x580E, 0xD4C3, 0x57FC, 0xD4C4, 0x5810,	0xD4C5, 0x57E7, 0xD4C6, 0x5801, 0xD4C7, 0x580C, 0xD4C8, 0x57F1,
+	0xD4C9, 0x57E9, 0xD4CA, 0x57F0, 0xD4CB, 0x580D, 0xD4CC, 0x5804,	0xD4CD, 0x595C, 0xD4CE, 0x5A60, 0xD4CF, 0x5A58, 0xD4D0, 0x5A55,
+	0xD4D1, 0x5A67, 0xD4D2, 0x5A5E, 0xD4D3, 0x5A38, 0xD4D4, 0x5A35,	0xD4D5, 0x5A6D, 0xD4D6, 0x5A50, 0xD4D7, 0x5A5F, 0xD4D8, 0x5A65,
+	0xD4D9, 0x5A6C, 0xD4DA, 0x5A53, 0xD4DB, 0x5A64, 0xD4DC, 0x5A57,	0xD4DD, 0x5A43, 0xD4DE, 0x5A5D, 0xD4DF, 0x5A52, 0xD4E0, 0x5A44,
+	0xD4E1, 0x5A5B, 0xD4E2, 0x5A48, 0xD4E3, 0x5A8E, 0xD4E4, 0x5A3E,	0xD4E5, 0x5A4D, 0xD4E6, 0x5A39, 0xD4E7, 0x5A4C, 0xD4E8, 0x5A70,
+	0xD4E9, 0x5A69, 0xD4EA, 0x5A47, 0xD4EB, 0x5A51, 0xD4EC, 0x5A56,	0xD4ED, 0x5A42, 0xD4EE, 0x5A5C, 0xD4EF, 0x5B72, 0xD4F0, 0x5B6E,
+	0xD4F1, 0x5BC1, 0xD4F2, 0x5BC0, 0xD4F3, 0x5C59, 0xD4F4, 0x5D1E,	0xD4F5, 0x5D0B, 0xD4F6, 0x5D1D, 0xD4F7, 0x5D1A, 0xD4F8, 0x5D20,
+	0xD4F9, 0x5D0C, 0xD4FA, 0x5D28, 0xD4FB, 0x5D0D, 0xD4FC, 0x5D26,	0xD4FD, 0x5D25, 0xD4FE, 0x5D0F, 0xD540, 0x5D30, 0xD541, 0x5D12,
+	0xD542, 0x5D23, 0xD543, 0x5D1F, 0xD544, 0x5D2E, 0xD545, 0x5E3E,	0xD546, 0x5E34, 0xD547, 0x5EB1, 0xD548, 0x5EB4, 0xD549, 0x5EB9,
+	0xD54A, 0x5EB2, 0xD54B, 0x5EB3, 0xD54C, 0x5F36, 0xD54D, 0x5F38,	0xD54E, 0x5F9B, 0xD54F, 0x5F96, 0xD550, 0x5F9F, 0xD551, 0x608A,
+	0xD552, 0x6090, 0xD553, 0x6086, 0xD554, 0x60BE, 0xD555, 0x60B0,	0xD556, 0x60BA, 0xD557, 0x60D3, 0xD558, 0x60D4, 0xD559, 0x60CF,
+	0xD55A, 0x60E4, 0xD55B, 0x60D9, 0xD55C, 0x60DD, 0xD55D, 0x60C8,	0xD55E, 0x60B1, 0xD55F, 0x60DB, 0xD560, 0x60B7, 0xD561, 0x60CA,
+	0xD562, 0x60BF, 0xD563, 0x60C3, 0xD564, 0x60CD, 0xD565, 0x60C0,	0xD566, 0x6332, 0xD567, 0x6365, 0xD568, 0x638A, 0xD569, 0x6382,
+	0xD56A, 0x637D, 0xD56B, 0x63BD, 0xD56C, 0x639E, 0xD56D, 0x63AD,	0xD56E, 0x639D, 0xD56F, 0x6397, 0xD570, 0x63AB, 0xD571, 0x638E,
+	0xD572, 0x636F, 0xD573, 0x6387, 0xD574, 0x6390, 0xD575, 0x636E,	0xD576, 0x63AF, 0xD577, 0x6375, 0xD578, 0x639C, 0xD579, 0x636D,
+	0xD57A, 0x63AE, 0xD57B, 0x637C, 0xD57C, 0x63A4, 0xD57D, 0x633B,	0xD57E, 0x639F, 0xD5A1, 0x6378, 0xD5A2, 0x6385, 0xD5A3, 0x6381,
+	0xD5A4, 0x6391, 0xD5A5, 0x638D, 0xD5A6, 0x6370, 0xD5A7, 0x6553,	0xD5A8, 0x65CD, 0xD5A9, 0x6665, 0xD5AA, 0x6661, 0xD5AB, 0x665B,
+	0xD5AC, 0x6659, 0xD5AD, 0x665C, 0xD5AE, 0x6662, 0xD5AF, 0x6718,	0xD5B0, 0x6879, 0xD5B1, 0x6887, 0xD5B2, 0x6890, 0xD5B3, 0x689C,
+	0xD5B4, 0x686D, 0xD5B5, 0x686E, 0xD5B6, 0x68AE, 0xD5B7, 0x68AB,	0xD5B8, 0x6956, 0xD5B9, 0x686F, 0xD5BA, 0x68A3, 0xD5BB, 0x68AC,
+	0xD5BC, 0x68A9, 0xD5BD, 0x6875, 0xD5BE, 0x6874, 0xD5BF, 0x68B2,	0xD5C0, 0x688F, 0xD5C1, 0x6877, 0xD5C2, 0x6892, 0xD5C3, 0x687C,
+	0xD5C4, 0x686B, 0xD5C5, 0x6872, 0xD5C6, 0x68AA, 0xD5C7, 0x6880,	0xD5C8, 0x6871, 0xD5C9, 0x687E, 0xD5CA, 0x689B, 0xD5CB, 0x6896,
+	0xD5CC, 0x688B, 0xD5CD, 0x68A0, 0xD5CE, 0x6889, 0xD5CF, 0x68A4,	0xD5D0, 0x6878, 0xD5D1, 0x687B, 0xD5D2, 0x6891, 0xD5D3, 0x688C,
+	0xD5D4, 0x688A, 0xD5D5, 0x687D, 0xD5D6, 0x6B36, 0xD5D7, 0x6B33,	0xD5D8, 0x6B37, 0xD5D9, 0x6B38, 0xD5DA, 0x6B91, 0xD5DB, 0x6B8F,
+	0xD5DC, 0x6B8D, 0xD5DD, 0x6B8E, 0xD5DE, 0x6B8C, 0xD5DF, 0x6C2A,	0xD5E0, 0x6DC0, 0xD5E1, 0x6DAB, 0xD5E2, 0x6DB4, 0xD5E3, 0x6DB3,
+	0xD5E4, 0x6E74, 0xD5E5, 0x6DAC, 0xD5E6, 0x6DE9, 0xD5E7, 0x6DE2,	0xD5E8, 0x6DB7, 0xD5E9, 0x6DF6, 0xD5EA, 0x6DD4, 0xD5EB, 0x6E00,
+	0xD5EC, 0x6DC8, 0xD5ED, 0x6DE0, 0xD5EE, 0x6DDF, 0xD5EF, 0x6DD6,	0xD5F0, 0x6DBE, 0xD5F1, 0x6DE5, 0xD5F2, 0x6DDC, 0xD5F3, 0x6DDD,
+	0xD5F4, 0x6DDB, 0xD5F5, 0x6DF4, 0xD5F6, 0x6DCA, 0xD5F7, 0x6DBD,	0xD5F8, 0x6DED, 0xD5F9, 0x6DF0, 0xD5FA, 0x6DBA, 0xD5FB, 0x6DD5,
+	0xD5FC, 0x6DC2, 0xD5FD, 0x6DCF, 0xD5FE, 0x6DC9, 0xD640, 0x6DD0,	0xD641, 0x6DF2, 0xD642, 0x6DD3, 0xD643, 0x6DFD, 0xD644, 0x6DD7,
+	0xD645, 0x6DCD, 0xD646, 0x6DE3, 0xD647, 0x6DBB, 0xD648, 0x70FA,	0xD649, 0x710D, 0xD64A, 0x70F7, 0xD64B, 0x7117, 0xD64C, 0x70F4,
+	0xD64D, 0x710C, 0xD64E, 0x70F0, 0xD64F, 0x7104, 0xD650, 0x70F3,	0xD651, 0x7110, 0xD652, 0x70FC, 0xD653, 0x70FF, 0xD654, 0x7106,
+	0xD655, 0x7113, 0xD656, 0x7100, 0xD657, 0x70F8, 0xD658, 0x70F6,	0xD659, 0x710B, 0xD65A, 0x7102, 0xD65B, 0x710E, 0xD65C, 0x727E,
+	0xD65D, 0x727B, 0xD65E, 0x727C, 0xD65F, 0x727F, 0xD660, 0x731D,	0xD661, 0x7317, 0xD662, 0x7307, 0xD663, 0x7311, 0xD664, 0x7318,
+	0xD665, 0x730A, 0xD666, 0x7308, 0xD667, 0x72FF, 0xD668, 0x730F,	0xD669, 0x731E, 0xD66A, 0x7388, 0xD66B, 0x73F6, 0xD66C, 0x73F8,
+	0xD66D, 0x73F5, 0xD66E, 0x7404, 0xD66F, 0x7401, 0xD670, 0x73FD,	0xD671, 0x7407, 0xD672, 0x7400, 0xD673, 0x73FA, 0xD674, 0x73FC,
+	0xD675, 0x73FF, 0xD676, 0x740C, 0xD677, 0x740B, 0xD678, 0x73F4,	0xD679, 0x7408, 0xD67A, 0x7564, 0xD67B, 0x7563, 0xD67C, 0x75CE,
+	0xD67D, 0x75D2, 0xD67E, 0x75CF, 0xD6A1, 0x75CB, 0xD6A2, 0x75CC,	0xD6A3, 0x75D1, 0xD6A4, 0x75D0, 0xD6A5, 0x768F, 0xD6A6, 0x7689,
+	0xD6A7, 0x76D3, 0xD6A8, 0x7739, 0xD6A9, 0x772F, 0xD6AA, 0x772D,	0xD6AB, 0x7731, 0xD6AC, 0x7732, 0xD6AD, 0x7734, 0xD6AE, 0x7733,
+	0xD6AF, 0x773D, 0xD6B0, 0x7725, 0xD6B1, 0x773B, 0xD6B2, 0x7735,	0xD6B3, 0x7848, 0xD6B4, 0x7852, 0xD6B5, 0x7849, 0xD6B6, 0x784D,
+	0xD6B7, 0x784A, 0xD6B8, 0x784C, 0xD6B9, 0x7826, 0xD6BA, 0x7845,	0xD6BB, 0x7850, 0xD6BC, 0x7964, 0xD6BD, 0x7967, 0xD6BE, 0x7969,
+	0xD6BF, 0x796A, 0xD6C0, 0x7963, 0xD6C1, 0x796B, 0xD6C2, 0x7961,	0xD6C3, 0x79BB, 0xD6C4, 0x79FA, 0xD6C5, 0x79F8, 0xD6C6, 0x79F6,
+	0xD6C7, 0x79F7, 0xD6C8, 0x7A8F, 0xD6C9, 0x7A94, 0xD6CA, 0x7A90,	0xD6CB, 0x7B35, 0xD6CC, 0x7B47, 0xD6CD, 0x7B34, 0xD6CE, 0x7B25,
+	0xD6CF, 0x7B30, 0xD6D0, 0x7B22, 0xD6D1, 0x7B24, 0xD6D2, 0x7B33,	0xD6D3, 0x7B18, 0xD6D4, 0x7B2A, 0xD6D5, 0x7B1D, 0xD6D6, 0x7B31,
+	0xD6D7, 0x7B2B, 0xD6D8, 0x7B2D, 0xD6D9, 0x7B2F, 0xD6DA, 0x7B32,	0xD6DB, 0x7B38, 0xD6DC, 0x7B1A, 0xD6DD, 0x7B23, 0xD6DE, 0x7C94,
+	0xD6DF, 0x7C98, 0xD6E0, 0x7C96, 0xD6E1, 0x7CA3, 0xD6E2, 0x7D35,	0xD6E3, 0x7D3D, 0xD6E4, 0x7D38, 0xD6E5, 0x7D36, 0xD6E6, 0x7D3A,
+	0xD6E7, 0x7D45, 0xD6E8, 0x7D2C, 0xD6E9, 0x7D29, 0xD6EA, 0x7D41,	0xD6EB, 0x7D47, 0xD6EC, 0x7D3E, 0xD6ED, 0x7D3F, 0xD6EE, 0x7D4A,
+	0xD6EF, 0x7D3B, 0xD6F0, 0x7D28, 0xD6F1, 0x7F63, 0xD6F2, 0x7F95,	0xD6F3, 0x7F9C, 0xD6F4, 0x7F9D, 0xD6F5, 0x7F9B, 0xD6F6, 0x7FCA,
+	0xD6F7, 0x7FCB, 0xD6F8, 0x7FCD, 0xD6F9, 0x7FD0, 0xD6FA, 0x7FD1,	0xD6FB, 0x7FC7, 0xD6FC, 0x7FCF, 0xD6FD, 0x7FC9, 0xD6FE, 0x801F,
+	0xD740, 0x801E, 0xD741, 0x801B, 0xD742, 0x8047, 0xD743, 0x8043,	0xD744, 0x8048, 0xD745, 0x8118, 0xD746, 0x8125, 0xD747, 0x8119,
+	0xD748, 0x811B, 0xD749, 0x812D, 0xD74A, 0x811F, 0xD74B, 0x812C,	0xD74C, 0x811E, 0xD74D, 0x8121, 0xD74E, 0x8115, 0xD74F, 0x8127,
+	0xD750, 0x811D, 0xD751, 0x8122, 0xD752, 0x8211, 0xD753, 0x8238,	0xD754, 0x8233, 0xD755, 0x823A, 0xD756, 0x8234, 0xD757, 0x8232,
+	0xD758, 0x8274, 0xD759, 0x8390, 0xD75A, 0x83A3, 0xD75B, 0x83A8,	0xD75C, 0x838D, 0xD75D, 0x837A, 0xD75E, 0x8373, 0xD75F, 0x83A4,
+	0xD760, 0x8374, 0xD761, 0x838F, 0xD762, 0x8381, 0xD763, 0x8395,	0xD764, 0x8399, 0xD765, 0x8375, 0xD766, 0x8394, 0xD767, 0x83A9,
+	0xD768, 0x837D, 0xD769, 0x8383, 0xD76A, 0x838C, 0xD76B, 0x839D,	0xD76C, 0x839B, 0xD76D, 0x83AA, 0xD76E, 0x838B, 0xD76F, 0x837E,
+	0xD770, 0x83A5, 0xD771, 0x83AF, 0xD772, 0x8388, 0xD773, 0x8397,	0xD774, 0x83B0, 0xD775, 0x837F, 0xD776, 0x83A6, 0xD777, 0x8387,
+	0xD778, 0x83AE, 0xD779, 0x8376, 0xD77A, 0x839A, 0xD77B, 0x8659,	0xD77C, 0x8656, 0xD77D, 0x86BF, 0xD77E, 0x86B7, 0xD7A1, 0x86C2,
+	0xD7A2, 0x86C1, 0xD7A3, 0x86C5, 0xD7A4, 0x86BA, 0xD7A5, 0x86B0,	0xD7A6, 0x86C8, 0xD7A7, 0x86B9, 0xD7A8, 0x86B3, 0xD7A9, 0x86B8,
+	0xD7AA, 0x86CC, 0xD7AB, 0x86B4, 0xD7AC, 0x86BB, 0xD7AD, 0x86BC,	0xD7AE, 0x86C3, 0xD7AF, 0x86BD, 0xD7B0, 0x86BE, 0xD7B1, 0x8852,
+	0xD7B2, 0x8889, 0xD7B3, 0x8895, 0xD7B4, 0x88A8, 0xD7B5, 0x88A2,	0xD7B6, 0x88AA, 0xD7B7, 0x889A, 0xD7B8, 0x8891, 0xD7B9, 0x88A1,
+	0xD7BA, 0x889F, 0xD7BB, 0x8898, 0xD7BC, 0x88A7, 0xD7BD, 0x8899,	0xD7BE, 0x889B, 0xD7BF, 0x8897, 0xD7C0, 0x88A4, 0xD7C1, 0x88AC,
+	0xD7C2, 0x888C, 0xD7C3, 0x8893, 0xD7C4, 0x888E, 0xD7C5, 0x8982,	0xD7C6, 0x89D6, 0xD7C7, 0x89D9, 0xD7C8, 0x89D5, 0xD7C9, 0x8A30,
+	0xD7CA, 0x8A27, 0xD7CB, 0x8A2C, 0xD7CC, 0x8A1E, 0xD7CD, 0x8C39,	0xD7CE, 0x8C3B, 0xD7CF, 0x8C5C, 0xD7D0, 0x8C5D, 0xD7D1, 0x8C7D,
+	0xD7D2, 0x8CA5, 0xD7D3, 0x8D7D, 0xD7D4, 0x8D7B, 0xD7D5, 0x8D79,	0xD7D6, 0x8DBC, 0xD7D7, 0x8DC2, 0xD7D8, 0x8DB9, 0xD7D9, 0x8DBF,
+	0xD7DA, 0x8DC1, 0xD7DB, 0x8ED8, 0xD7DC, 0x8EDE, 0xD7DD, 0x8EDD,	0xD7DE, 0x8EDC, 0xD7DF, 0x8ED7, 0xD7E0, 0x8EE0, 0xD7E1, 0x8EE1,
+	0xD7E2, 0x9024, 0xD7E3, 0x900B, 0xD7E4, 0x9011, 0xD7E5, 0x901C,	0xD7E6, 0x900C, 0xD7E7, 0x9021, 0xD7E8, 0x90EF, 0xD7E9, 0x90EA,
+	0xD7EA, 0x90F0, 0xD7EB, 0x90F4, 0xD7EC, 0x90F2, 0xD7ED, 0x90F3,	0xD7EE, 0x90D4, 0xD7EF, 0x90EB, 0xD7F0, 0x90EC, 0xD7F1, 0x90E9,
+	0xD7F2, 0x9156, 0xD7F3, 0x9158, 0xD7F4, 0x915A, 0xD7F5, 0x9153,	0xD7F6, 0x9155, 0xD7F7, 0x91EC, 0xD7F8, 0x91F4, 0xD7F9, 0x91F1,
+	0xD7FA, 0x91F3, 0xD7FB, 0x91F8, 0xD7FC, 0x91E4, 0xD7FD, 0x91F9,	0xD7FE, 0x91EA, 0xD840, 0x91EB, 0xD841, 0x91F7, 0xD842, 0x91E8,
+	0xD843, 0x91EE, 0xD844, 0x957A, 0xD845, 0x9586, 0xD846, 0x9588,	0xD847, 0x967C, 0xD848, 0x966D, 0xD849, 0x966B, 0xD84A, 0x9671,
+	0xD84B, 0x966F, 0xD84C, 0x96BF, 0xD84D, 0x976A, 0xD84E, 0x9804,	0xD84F, 0x98E5, 0xD850, 0x9997, 0xD851, 0x509B, 0xD852, 0x5095,
+	0xD853, 0x5094, 0xD854, 0x509E, 0xD855, 0x508B, 0xD856, 0x50A3,	0xD857, 0x5083, 0xD858, 0x508C, 0xD859, 0x508E, 0xD85A, 0x509D,
+	0xD85B, 0x5068, 0xD85C, 0x509C, 0xD85D, 0x5092, 0xD85E, 0x5082,	0xD85F, 0x5087, 0xD860, 0x515F, 0xD861, 0x51D4, 0xD862, 0x5312,
+	0xD863, 0x5311, 0xD864, 0x53A4, 0xD865, 0x53A7, 0xD866, 0x5591,	0xD867, 0x55A8, 0xD868, 0x55A5, 0xD869, 0x55AD, 0xD86A, 0x5577,
+	0xD86B, 0x5645, 0xD86C, 0x55A2, 0xD86D, 0x5593, 0xD86E, 0x5588,	0xD86F, 0x558F, 0xD870, 0x55B5, 0xD871, 0x5581, 0xD872, 0x55A3,
+	0xD873, 0x5592, 0xD874, 0x55A4, 0xD875, 0x557D, 0xD876, 0x558C,	0xD877, 0x55A6, 0xD878, 0x557F, 0xD879, 0x5595, 0xD87A, 0x55A1,
+	0xD87B, 0x558E, 0xD87C, 0x570C, 0xD87D, 0x5829, 0xD87E, 0x5837,	0xD8A1, 0x5819, 0xD8A2, 0x581E, 0xD8A3, 0x5827, 0xD8A4, 0x5823,
+	0xD8A5, 0x5828, 0xD8A6, 0x57F5, 0xD8A7, 0x5848, 0xD8A8, 0x5825,	0xD8A9, 0x581C, 0xD8AA, 0x581B, 0xD8AB, 0x5833, 0xD8AC, 0x583F,
+	0xD8AD, 0x5836, 0xD8AE, 0x582E, 0xD8AF, 0x5839, 0xD8B0, 0x5838,	0xD8B1, 0x582D, 0xD8B2, 0x582C, 0xD8B3, 0x583B, 0xD8B4, 0x5961,
+	0xD8B5, 0x5AAF, 0xD8B6, 0x5A94, 0xD8B7, 0x5A9F, 0xD8B8, 0x5A7A,	0xD8B9, 0x5AA2, 0xD8BA, 0x5A9E, 0xD8BB, 0x5A78, 0xD8BC, 0x5AA6,
+	0xD8BD, 0x5A7C, 0xD8BE, 0x5AA5, 0xD8BF, 0x5AAC, 0xD8C0, 0x5A95,	0xD8C1, 0x5AAE, 0xD8C2, 0x5A37, 0xD8C3, 0x5A84, 0xD8C4, 0x5A8A,
+	0xD8C5, 0x5A97, 0xD8C6, 0x5A83, 0xD8C7, 0x5A8B, 0xD8C8, 0x5AA9,	0xD8C9, 0x5A7B, 0xD8CA, 0x5A7D, 0xD8CB, 0x5A8C, 0xD8CC, 0x5A9C,
+	0xD8CD, 0x5A8F, 0xD8CE, 0x5A93, 0xD8CF, 0x5A9D, 0xD8D0, 0x5BEA,	0xD8D1, 0x5BCD, 0xD8D2, 0x5BCB, 0xD8D3, 0x5BD4, 0xD8D4, 0x5BD1,
+	0xD8D5, 0x5BCA, 0xD8D6, 0x5BCE, 0xD8D7, 0x5C0C, 0xD8D8, 0x5C30,	0xD8D9, 0x5D37, 0xD8DA, 0x5D43, 0xD8DB, 0x5D6B, 0xD8DC, 0x5D41,
+	0xD8DD, 0x5D4B, 0xD8DE, 0x5D3F, 0xD8DF, 0x5D35, 0xD8E0, 0x5D51,	0xD8E1, 0x5D4E, 0xD8E2, 0x5D55, 0xD8E3, 0x5D33, 0xD8E4, 0x5D3A,
+	0xD8E5, 0x5D52, 0xD8E6, 0x5D3D, 0xD8E7, 0x5D31, 0xD8E8, 0x5D59,	0xD8E9, 0x5D42, 0xD8EA, 0x5D39, 0xD8EB, 0x5D49, 0xD8EC, 0x5D38,
+	0xD8ED, 0x5D3C, 0xD8EE, 0x5D32, 0xD8EF, 0x5D36, 0xD8F0, 0x5D40,	0xD8F1, 0x5D45, 0xD8F2, 0x5E44, 0xD8F3, 0x5E41, 0xD8F4, 0x5F58,
+	0xD8F5, 0x5FA6, 0xD8F6, 0x5FA5, 0xD8F7, 0x5FAB, 0xD8F8, 0x60C9,	0xD8F9, 0x60B9, 0xD8FA, 0x60CC, 0xD8FB, 0x60E2, 0xD8FC, 0x60CE,
+	0xD8FD, 0x60C4, 0xD8FE, 0x6114, 0xD940, 0x60F2, 0xD941, 0x610A,	0xD942, 0x6116, 0xD943, 0x6105, 0xD944, 0x60F5, 0xD945, 0x6113,
+	0xD946, 0x60F8, 0xD947, 0x60FC, 0xD948, 0x60FE, 0xD949, 0x60C1,	0xD94A, 0x6103, 0xD94B, 0x6118, 0xD94C, 0x611D, 0xD94D, 0x6110,
+	0xD94E, 0x60FF, 0xD94F, 0x6104, 0xD950, 0x610B, 0xD951, 0x624A,	0xD952, 0x6394, 0xD953, 0x63B1, 0xD954, 0x63B0, 0xD955, 0x63CE,
+	0xD956, 0x63E5, 0xD957, 0x63E8, 0xD958, 0x63EF, 0xD959, 0x63C3,	0xD95A, 0x649D, 0xD95B, 0x63F3, 0xD95C, 0x63CA, 0xD95D, 0x63E0,
+	0xD95E, 0x63F6, 0xD95F, 0x63D5, 0xD960, 0x63F2, 0xD961, 0x63F5,	0xD962, 0x6461, 0xD963, 0x63DF, 0xD964, 0x63BE, 0xD965, 0x63DD,
+	0xD966, 0x63DC, 0xD967, 0x63C4, 0xD968, 0x63D8, 0xD969, 0x63D3,	0xD96A, 0x63C2, 0xD96B, 0x63C7, 0xD96C, 0x63CC, 0xD96D, 0x63CB,
+	0xD96E, 0x63C8, 0xD96F, 0x63F0, 0xD970, 0x63D7, 0xD971, 0x63D9,	0xD972, 0x6532, 0xD973, 0x6567, 0xD974, 0x656A, 0xD975, 0x6564,
+	0xD976, 0x655C, 0xD977, 0x6568, 0xD978, 0x6565, 0xD979, 0x658C,	0xD97A, 0x659D, 0xD97B, 0x659E, 0xD97C, 0x65AE, 0xD97D, 0x65D0,
+	0xD97E, 0x65D2, 0xD9A1, 0x667C, 0xD9A2, 0x666C, 0xD9A3, 0x667B,	0xD9A4, 0x6680, 0xD9A5, 0x6671, 0xD9A6, 0x6679, 0xD9A7, 0x666A,
+	0xD9A8, 0x6672, 0xD9A9, 0x6701, 0xD9AA, 0x690C, 0xD9AB, 0x68D3,	0xD9AC, 0x6904, 0xD9AD, 0x68DC, 0xD9AE, 0x692A, 0xD9AF, 0x68EC,
+	0xD9B0, 0x68EA, 0xD9B1, 0x68F1, 0xD9B2, 0x690F, 0xD9B3, 0x68D6,	0xD9B4, 0x68F7, 0xD9B5, 0x68EB, 0xD9B6, 0x68E4, 0xD9B7, 0x68F6,
+	0xD9B8, 0x6913, 0xD9B9, 0x6910, 0xD9BA, 0x68F3, 0xD9BB, 0x68E1,	0xD9BC, 0x6907, 0xD9BD, 0x68CC, 0xD9BE, 0x6908, 0xD9BF, 0x6970,
+	0xD9C0, 0x68B4, 0xD9C1, 0x6911, 0xD9C2, 0x68EF, 0xD9C3, 0x68C6,	0xD9C4, 0x6914, 0xD9C5, 0x68F8, 0xD9C6, 0x68D0, 0xD9C7, 0x68FD,
+	0xD9C8, 0x68FC, 0xD9C9, 0x68E8, 0xD9CA, 0x690B, 0xD9CB, 0x690A,	0xD9CC, 0x6917, 0xD9CD, 0x68CE, 0xD9CE, 0x68C8, 0xD9CF, 0x68DD,
+	0xD9D0, 0x68DE, 0xD9D1, 0x68E6, 0xD9D2, 0x68F4, 0xD9D3, 0x68D1,	0xD9D4, 0x6906, 0xD9D5, 0x68D4, 0xD9D6, 0x68E9, 0xD9D7, 0x6915,
+	0xD9D8, 0x6925, 0xD9D9, 0x68C7, 0xD9DA, 0x6B39, 0xD9DB, 0x6B3B,	0xD9DC, 0x6B3F, 0xD9DD, 0x6B3C, 0xD9DE, 0x6B94, 0xD9DF, 0x6B97,
+	0xD9E0, 0x6B99, 0xD9E1, 0x6B95, 0xD9E2, 0x6BBD, 0xD9E3, 0x6BF0,	0xD9E4, 0x6BF2, 0xD9E5, 0x6BF3, 0xD9E6, 0x6C30, 0xD9E7, 0x6DFC,
+	0xD9E8, 0x6E46, 0xD9E9, 0x6E47, 0xD9EA, 0x6E1F, 0xD9EB, 0x6E49,	0xD9EC, 0x6E88, 0xD9ED, 0x6E3C, 0xD9EE, 0x6E3D, 0xD9EF, 0x6E45,
+	0xD9F0, 0x6E62, 0xD9F1, 0x6E2B, 0xD9F2, 0x6E3F, 0xD9F3, 0x6E41,	0xD9F4, 0x6E5D, 0xD9F5, 0x6E73, 0xD9F6, 0x6E1C, 0xD9F7, 0x6E33,
+	0xD9F8, 0x6E4B, 0xD9F9, 0x6E40, 0xD9FA, 0x6E51, 0xD9FB, 0x6E3B,	0xD9FC, 0x6E03, 0xD9FD, 0x6E2E, 0xD9FE, 0x6E5E, 0xDA40, 0x6E68,
+	0xDA41, 0x6E5C, 0xDA42, 0x6E61, 0xDA43, 0x6E31, 0xDA44, 0x6E28,	0xDA45, 0x6E60, 0xDA46, 0x6E71, 0xDA47, 0x6E6B, 0xDA48, 0x6E39,
+	0xDA49, 0x6E22, 0xDA4A, 0x6E30, 0xDA4B, 0x6E53, 0xDA4C, 0x6E65,	0xDA4D, 0x6E27, 0xDA4E, 0x6E78, 0xDA4F, 0x6E64, 0xDA50, 0x6E77,
+	0xDA51, 0x6E55, 0xDA52, 0x6E79, 0xDA53, 0x6E52, 0xDA54, 0x6E66,	0xDA55, 0x6E35, 0xDA56, 0x6E36, 0xDA57, 0x6E5A, 0xDA58, 0x7120,
+	0xDA59, 0x711E, 0xDA5A, 0x712F, 0xDA5B, 0x70FB, 0xDA5C, 0x712E,	0xDA5D, 0x7131, 0xDA5E, 0x7123, 0xDA5F, 0x7125, 0xDA60, 0x7122,
+	0xDA61, 0x7132, 0xDA62, 0x711F, 0xDA63, 0x7128, 0xDA64, 0x713A,	0xDA65, 0x711B, 0xDA66, 0x724B, 0xDA67, 0x725A, 0xDA68, 0x7288,
+	0xDA69, 0x7289, 0xDA6A, 0x7286, 0xDA6B, 0x7285, 0xDA6C, 0x728B,	0xDA6D, 0x7312, 0xDA6E, 0x730B, 0xDA6F, 0x7330, 0xDA70, 0x7322,
+	0xDA71, 0x7331, 0xDA72, 0x7333, 0xDA73, 0x7327, 0xDA74, 0x7332,	0xDA75, 0x732D, 0xDA76, 0x7326, 0xDA77, 0x7323, 0xDA78, 0x7335,
+	0xDA79, 0x730C, 0xDA7A, 0x742E, 0xDA7B, 0x742C, 0xDA7C, 0x7430,	0xDA7D, 0x742B, 0xDA7E, 0x7416, 0xDAA1, 0x741A, 0xDAA2, 0x7421,
+	0xDAA3, 0x742D, 0xDAA4, 0x7431, 0xDAA5, 0x7424, 0xDAA6, 0x7423,	0xDAA7, 0x741D, 0xDAA8, 0x7429, 0xDAA9, 0x7420, 0xDAAA, 0x7432,
+	0xDAAB, 0x74FB, 0xDAAC, 0x752F, 0xDAAD, 0x756F, 0xDAAE, 0x756C,	0xDAAF, 0x75E7, 0xDAB0, 0x75DA, 0xDAB1, 0x75E1, 0xDAB2, 0x75E6,
+	0xDAB3, 0x75DD, 0xDAB4, 0x75DF, 0xDAB5, 0x75E4, 0xDAB6, 0x75D7,	0xDAB7, 0x7695, 0xDAB8, 0x7692, 0xDAB9, 0x76DA, 0xDABA, 0x7746,
+	0xDABB, 0x7747, 0xDABC, 0x7744, 0xDABD, 0x774D, 0xDABE, 0x7745,	0xDABF, 0x774A, 0xDAC0, 0x774E, 0xDAC1, 0x774B, 0xDAC2, 0x774C,
+	0xDAC3, 0x77DE, 0xDAC4, 0x77EC, 0xDAC5, 0x7860, 0xDAC6, 0x7864,	0xDAC7, 0x7865, 0xDAC8, 0x785C, 0xDAC9, 0x786D, 0xDACA, 0x7871,
+	0xDACB, 0x786A, 0xDACC, 0x786E, 0xDACD, 0x7870, 0xDACE, 0x7869,	0xDACF, 0x7868, 0xDAD0, 0x785E, 0xDAD1, 0x7862, 0xDAD2, 0x7974,
+	0xDAD3, 0x7973, 0xDAD4, 0x7972, 0xDAD5, 0x7970, 0xDAD6, 0x7A02,	0xDAD7, 0x7A0A, 0xDAD8, 0x7A03, 0xDAD9, 0x7A0C, 0xDADA, 0x7A04,
+	0xDADB, 0x7A99, 0xDADC, 0x7AE6, 0xDADD, 0x7AE4, 0xDADE, 0x7B4A,	0xDADF, 0x7B3B, 0xDAE0, 0x7B44, 0xDAE1, 0x7B48, 0xDAE2, 0x7B4C,
+	0xDAE3, 0x7B4E, 0xDAE4, 0x7B40, 0xDAE5, 0x7B58, 0xDAE6, 0x7B45,	0xDAE7, 0x7CA2, 0xDAE8, 0x7C9E, 0xDAE9, 0x7CA8, 0xDAEA, 0x7CA1,
+	0xDAEB, 0x7D58, 0xDAEC, 0x7D6F, 0xDAED, 0x7D63, 0xDAEE, 0x7D53,	0xDAEF, 0x7D56, 0xDAF0, 0x7D67, 0xDAF1, 0x7D6A, 0xDAF2, 0x7D4F,
+	0xDAF3, 0x7D6D, 0xDAF4, 0x7D5C, 0xDAF5, 0x7D6B, 0xDAF6, 0x7D52,	0xDAF7, 0x7D54, 0xDAF8, 0x7D69, 0xDAF9, 0x7D51, 0xDAFA, 0x7D5F,
+	0xDAFB, 0x7D4E, 0xDAFC, 0x7F3E, 0xDAFD, 0x7F3F, 0xDAFE, 0x7F65,	0xDB40, 0x7F66, 0xDB41, 0x7FA2, 0xDB42, 0x7FA0, 0xDB43, 0x7FA1,
+	0xDB44, 0x7FD7, 0xDB45, 0x8051, 0xDB46, 0x804F, 0xDB47, 0x8050,	0xDB48, 0x80FE, 0xDB49, 0x80D4, 0xDB4A, 0x8143, 0xDB4B, 0x814A,
+	0xDB4C, 0x8152, 0xDB4D, 0x814F, 0xDB4E, 0x8147, 0xDB4F, 0x813D,	0xDB50, 0x814D, 0xDB51, 0x813A, 0xDB52, 0x81E6, 0xDB53, 0x81EE,
+	0xDB54, 0x81F7, 0xDB55, 0x81F8, 0xDB56, 0x81F9, 0xDB57, 0x8204,	0xDB58, 0x823C, 0xDB59, 0x823D, 0xDB5A, 0x823F, 0xDB5B, 0x8275,
+	0xDB5C, 0x833B, 0xDB5D, 0x83CF, 0xDB5E, 0x83F9, 0xDB5F, 0x8423,	0xDB60, 0x83C0, 0xDB61, 0x83E8, 0xDB62, 0x8412, 0xDB63, 0x83E7,
+	0xDB64, 0x83E4, 0xDB65, 0x83FC, 0xDB66, 0x83F6, 0xDB67, 0x8410,	0xDB68, 0x83C6, 0xDB69, 0x83C8, 0xDB6A, 0x83EB, 0xDB6B, 0x83E3,
+	0xDB6C, 0x83BF, 0xDB6D, 0x8401, 0xDB6E, 0x83DD, 0xDB6F, 0x83E5,	0xDB70, 0x83D8, 0xDB71, 0x83FF, 0xDB72, 0x83E1, 0xDB73, 0x83CB,
+	0xDB74, 0x83CE, 0xDB75, 0x83D6, 0xDB76, 0x83F5, 0xDB77, 0x83C9,	0xDB78, 0x8409, 0xDB79, 0x840F, 0xDB7A, 0x83DE, 0xDB7B, 0x8411,
+	0xDB7C, 0x8406, 0xDB7D, 0x83C2, 0xDB7E, 0x83F3, 0xDBA1, 0x83D5,	0xDBA2, 0x83FA, 0xDBA3, 0x83C7, 0xDBA4, 0x83D1, 0xDBA5, 0x83EA,
+	0xDBA6, 0x8413, 0xDBA7, 0x83C3, 0xDBA8, 0x83EC, 0xDBA9, 0x83EE,	0xDBAA, 0x83C4, 0xDBAB, 0x83FB, 0xDBAC, 0x83D7, 0xDBAD, 0x83E2,
+	0xDBAE, 0x841B, 0xDBAF, 0x83DB, 0xDBB0, 0x83FE, 0xDBB1, 0x86D8,	0xDBB2, 0x86E2, 0xDBB3, 0x86E6, 0xDBB4, 0x86D3, 0xDBB5, 0x86E3,
+	0xDBB6, 0x86DA, 0xDBB7, 0x86EA, 0xDBB8, 0x86DD, 0xDBB9, 0x86EB,	0xDBBA, 0x86DC, 0xDBBB, 0x86EC, 0xDBBC, 0x86E9, 0xDBBD, 0x86D7,
+	0xDBBE, 0x86E8, 0xDBBF, 0x86D1, 0xDBC0, 0x8848, 0xDBC1, 0x8856,	0xDBC2, 0x8855, 0xDBC3, 0x88BA, 0xDBC4, 0x88D7, 0xDBC5, 0x88B9,
+	0xDBC6, 0x88B8, 0xDBC7, 0x88C0, 0xDBC8, 0x88BE, 0xDBC9, 0x88B6,	0xDBCA, 0x88BC, 0xDBCB, 0x88B7, 0xDBCC, 0x88BD, 0xDBCD, 0x88B2,
+	0xDBCE, 0x8901, 0xDBCF, 0x88C9, 0xDBD0, 0x8995, 0xDBD1, 0x8998,	0xDBD2, 0x8997, 0xDBD3, 0x89DD, 0xDBD4, 0x89DA, 0xDBD5, 0x89DB,
+	0xDBD6, 0x8A4E, 0xDBD7, 0x8A4D, 0xDBD8, 0x8A39, 0xDBD9, 0x8A59,	0xDBDA, 0x8A40, 0xDBDB, 0x8A57, 0xDBDC, 0x8A58, 0xDBDD, 0x8A44,
+	0xDBDE, 0x8A45, 0xDBDF, 0x8A52, 0xDBE0, 0x8A48, 0xDBE1, 0x8A51,	0xDBE2, 0x8A4A, 0xDBE3, 0x8A4C, 0xDBE4, 0x8A4F, 0xDBE5, 0x8C5F,
+	0xDBE6, 0x8C81, 0xDBE7, 0x8C80, 0xDBE8, 0x8CBA, 0xDBE9, 0x8CBE,	0xDBEA, 0x8CB0, 0xDBEB, 0x8CB9, 0xDBEC, 0x8CB5, 0xDBED, 0x8D84,
+	0xDBEE, 0x8D80, 0xDBEF, 0x8D89, 0xDBF0, 0x8DD8, 0xDBF1, 0x8DD3,	0xDBF2, 0x8DCD, 0xDBF3, 0x8DC7, 0xDBF4, 0x8DD6, 0xDBF5, 0x8DDC,
+	0xDBF6, 0x8DCF, 0xDBF7, 0x8DD5, 0xDBF8, 0x8DD9, 0xDBF9, 0x8DC8,	0xDBFA, 0x8DD7, 0xDBFB, 0x8DC5, 0xDBFC, 0x8EEF, 0xDBFD, 0x8EF7,
+	0xDBFE, 0x8EFA, 0xDC40, 0x8EF9, 0xDC41, 0x8EE6, 0xDC42, 0x8EEE,	0xDC43, 0x8EE5, 0xDC44, 0x8EF5, 0xDC45, 0x8EE7, 0xDC46, 0x8EE8,
+	0xDC47, 0x8EF6, 0xDC48, 0x8EEB, 0xDC49, 0x8EF1, 0xDC4A, 0x8EEC,	0xDC4B, 0x8EF4, 0xDC4C, 0x8EE9, 0xDC4D, 0x902D, 0xDC4E, 0x9034,
+	0xDC4F, 0x902F, 0xDC50, 0x9106, 0xDC51, 0x912C, 0xDC52, 0x9104,	0xDC53, 0x90FF, 0xDC54, 0x90FC, 0xDC55, 0x9108, 0xDC56, 0x90F9,
+	0xDC57, 0x90FB, 0xDC58, 0x9101, 0xDC59, 0x9100, 0xDC5A, 0x9107,	0xDC5B, 0x9105, 0xDC5C, 0x9103, 0xDC5D, 0x9161, 0xDC5E, 0x9164,
+	0xDC5F, 0x915F, 0xDC60, 0x9162, 0xDC61, 0x9160, 0xDC62, 0x9201,	0xDC63, 0x920A, 0xDC64, 0x9225, 0xDC65, 0x9203, 0xDC66, 0x921A,
+	0xDC67, 0x9226, 0xDC68, 0x920F, 0xDC69, 0x920C, 0xDC6A, 0x9200,	0xDC6B, 0x9212, 0xDC6C, 0x91FF, 0xDC6D, 0x91FD, 0xDC6E, 0x9206,
+	0xDC6F, 0x9204, 0xDC70, 0x9227, 0xDC71, 0x9202, 0xDC72, 0x921C,	0xDC73, 0x9224, 0xDC74, 0x9219, 0xDC75, 0x9217, 0xDC76, 0x9205,
+	0xDC77, 0x9216, 0xDC78, 0x957B, 0xDC79, 0x958D, 0xDC7A, 0x958C,	0xDC7B, 0x9590, 0xDC7C, 0x9687, 0xDC7D, 0x967E, 0xDC7E, 0x9688,
+	0xDCA1, 0x9689, 0xDCA2, 0x9683, 0xDCA3, 0x9680, 0xDCA4, 0x96C2,	0xDCA5, 0x96C8, 0xDCA6, 0x96C3, 0xDCA7, 0x96F1, 0xDCA8, 0x96F0,
+	0xDCA9, 0x976C, 0xDCAA, 0x9770, 0xDCAB, 0x976E, 0xDCAC, 0x9807,	0xDCAD, 0x98A9, 0xDCAE, 0x98EB, 0xDCAF, 0x9CE6, 0xDCB0, 0x9EF9,
+	0xDCB1, 0x4E83, 0xDCB2, 0x4E84, 0xDCB3, 0x4EB6, 0xDCB4, 0x50BD,	0xDCB5, 0x50BF, 0xDCB6, 0x50C6, 0xDCB7, 0x50AE, 0xDCB8, 0x50C4,
+	0xDCB9, 0x50CA, 0xDCBA, 0x50B4, 0xDCBB, 0x50C8, 0xDCBC, 0x50C2,	0xDCBD, 0x50B0, 0xDCBE, 0x50C1, 0xDCBF, 0x50BA, 0xDCC0, 0x50B1,
+	0xDCC1, 0x50CB, 0xDCC2, 0x50C9, 0xDCC3, 0x50B6, 0xDCC4, 0x50B8,	0xDCC5, 0x51D7, 0xDCC6, 0x527A, 0xDCC7, 0x5278, 0xDCC8, 0x527B,
+	0xDCC9, 0x527C, 0xDCCA, 0x55C3, 0xDCCB, 0x55DB, 0xDCCC, 0x55CC,	0xDCCD, 0x55D0, 0xDCCE, 0x55CB, 0xDCCF, 0x55CA, 0xDCD0, 0x55DD,
+	0xDCD1, 0x55C0, 0xDCD2, 0x55D4, 0xDCD3, 0x55C4, 0xDCD4, 0x55E9,	0xDCD5, 0x55BF, 0xDCD6, 0x55D2, 0xDCD7, 0x558D, 0xDCD8, 0x55CF,
+	0xDCD9, 0x55D5, 0xDCDA, 0x55E2, 0xDCDB, 0x55D6, 0xDCDC, 0x55C8,	0xDCDD, 0x55F2, 0xDCDE, 0x55CD, 0xDCDF, 0x55D9, 0xDCE0, 0x55C2,
+	0xDCE1, 0x5714, 0xDCE2, 0x5853, 0xDCE3, 0x5868, 0xDCE4, 0x5864,	0xDCE5, 0x584F, 0xDCE6, 0x584D, 0xDCE7, 0x5849, 0xDCE8, 0x586F,
+	0xDCE9, 0x5855, 0xDCEA, 0x584E, 0xDCEB, 0x585D, 0xDCEC, 0x5859,	0xDCED, 0x5865, 0xDCEE, 0x585B, 0xDCEF, 0x583D, 0xDCF0, 0x5863,
+	0xDCF1, 0x5871, 0xDCF2, 0x58FC, 0xDCF3, 0x5AC7, 0xDCF4, 0x5AC4,	0xDCF5, 0x5ACB, 0xDCF6, 0x5ABA, 0xDCF7, 0x5AB8, 0xDCF8, 0x5AB1,
+	0xDCF9, 0x5AB5, 0xDCFA, 0x5AB0, 0xDCFB, 0x5ABF, 0xDCFC, 0x5AC8,	0xDCFD, 0x5ABB, 0xDCFE, 0x5AC6, 0xDD40, 0x5AB7, 0xDD41, 0x5AC0,
+	0xDD42, 0x5ACA, 0xDD43, 0x5AB4, 0xDD44, 0x5AB6, 0xDD45, 0x5ACD,	0xDD46, 0x5AB9, 0xDD47, 0x5A90, 0xDD48, 0x5BD6, 0xDD49, 0x5BD8,
+	0xDD4A, 0x5BD9, 0xDD4B, 0x5C1F, 0xDD4C, 0x5C33, 0xDD4D, 0x5D71,	0xDD4E, 0x5D63, 0xDD4F, 0x5D4A, 0xDD50, 0x5D65, 0xDD51, 0x5D72,
+	0xDD52, 0x5D6C, 0xDD53, 0x5D5E, 0xDD54, 0x5D68, 0xDD55, 0x5D67,	0xDD56, 0x5D62, 0xDD57, 0x5DF0, 0xDD58, 0x5E4F, 0xDD59, 0x5E4E,
+	0xDD5A, 0x5E4A, 0xDD5B, 0x5E4D, 0xDD5C, 0x5E4B, 0xDD5D, 0x5EC5,	0xDD5E, 0x5ECC, 0xDD5F, 0x5EC6, 0xDD60, 0x5ECB, 0xDD61, 0x5EC7,
+	0xDD62, 0x5F40, 0xDD63, 0x5FAF, 0xDD64, 0x5FAD, 0xDD65, 0x60F7,	0xDD66, 0x6149, 0xDD67, 0x614A, 0xDD68, 0x612B, 0xDD69, 0x6145,
+	0xDD6A, 0x6136, 0xDD6B, 0x6132, 0xDD6C, 0x612E, 0xDD6D, 0x6146,	0xDD6E, 0x612F, 0xDD6F, 0x614F, 0xDD70, 0x6129, 0xDD71, 0x6140,
+	0xDD72, 0x6220, 0xDD73, 0x9168, 0xDD74, 0x6223, 0xDD75, 0x6225,	0xDD76, 0x6224, 0xDD77, 0x63C5, 0xDD78, 0x63F1, 0xDD79, 0x63EB,
+	0xDD7A, 0x6410, 0xDD7B, 0x6412, 0xDD7C, 0x6409, 0xDD7D, 0x6420,	0xDD7E, 0x6424, 0xDDA1, 0x6433, 0xDDA2, 0x6443, 0xDDA3, 0x641F,
+	0xDDA4, 0x6415, 0xDDA5, 0x6418, 0xDDA6, 0x6439, 0xDDA7, 0x6437,	0xDDA8, 0x6422, 0xDDA9, 0x6423, 0xDDAA, 0x640C, 0xDDAB, 0x6426,
+	0xDDAC, 0x6430, 0xDDAD, 0x6428, 0xDDAE, 0x6441, 0xDDAF, 0x6435,	0xDDB0, 0x642F, 0xDDB1, 0x640A, 0xDDB2, 0x641A, 0xDDB3, 0x6440,
+	0xDDB4, 0x6425, 0xDDB5, 0x6427, 0xDDB6, 0x640B, 0xDDB7, 0x63E7,	0xDDB8, 0x641B, 0xDDB9, 0x642E, 0xDDBA, 0x6421, 0xDDBB, 0x640E,
+	0xDDBC, 0x656F, 0xDDBD, 0x6592, 0xDDBE, 0x65D3, 0xDDBF, 0x6686,	0xDDC0, 0x668C, 0xDDC1, 0x6695, 0xDDC2, 0x6690, 0xDDC3, 0x668B,
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+	0xDDD4, 0x6957, 0xDDD5, 0x6959, 0xDDD6, 0x697A, 0xDDD7, 0x6948,	0xDDD8, 0x6949, 0xDDD9, 0x6935, 0xDDDA, 0x696C, 0xDDDB, 0x6933,
+	0xDDDC, 0x693D, 0xDDDD, 0x6965, 0xDDDE, 0x68F0, 0xDDDF, 0x6978,	0xDDE0, 0x6934, 0xDDE1, 0x6969, 0xDDE2, 0x6940, 0xDDE3, 0x696F,
+	0xDDE4, 0x6944, 0xDDE5, 0x6976, 0xDDE6, 0x6958, 0xDDE7, 0x6941,	0xDDE8, 0x6974, 0xDDE9, 0x694C, 0xDDEA, 0x693B, 0xDDEB, 0x694B,
+	0xDDEC, 0x6937, 0xDDED, 0x695C, 0xDDEE, 0x694F, 0xDDEF, 0x6951,	0xDDF0, 0x6932, 0xDDF1, 0x6952, 0xDDF2, 0x692F, 0xDDF3, 0x697B,
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+	0xDE45, 0x6EC8, 0xDE46, 0x6E8F, 0xDE47, 0x6EC0, 0xDE48, 0x6E9F,	0xDE49, 0x6E93, 0xDE4A, 0x6E94, 0xDE4B, 0x6EA0, 0xDE4C, 0x6EB1,
+	0xDE4D, 0x6EB9, 0xDE4E, 0x6EC6, 0xDE4F, 0x6ED2, 0xDE50, 0x6EBD,	0xDE51, 0x6EC1, 0xDE52, 0x6E9E, 0xDE53, 0x6EC9, 0xDE54, 0x6EB7,
+	0xDE55, 0x6EB0, 0xDE56, 0x6ECD, 0xDE57, 0x6EA6, 0xDE58, 0x6ECF,	0xDE59, 0x6EB2, 0xDE5A, 0x6EBE, 0xDE5B, 0x6EC3, 0xDE5C, 0x6EDC,
+	0xDE5D, 0x6ED8, 0xDE5E, 0x6E99, 0xDE5F, 0x6E92, 0xDE60, 0x6E8E,	0xDE61, 0x6E8D, 0xDE62, 0x6EA4, 0xDE63, 0x6EA1, 0xDE64, 0x6EBF,
+	0xDE65, 0x6EB3, 0xDE66, 0x6ED0, 0xDE67, 0x6ECA, 0xDE68, 0x6E97,	0xDE69, 0x6EAE, 0xDE6A, 0x6EA3, 0xDE6B, 0x7147, 0xDE6C, 0x7154,
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+	0xDE7D, 0x7150, 0xDE7E, 0x7153, 0xDEA1, 0x7144, 0xDEA2, 0x714D,	0xDEA3, 0x715A, 0xDEA4, 0x724F, 0xDEA5, 0x728D, 0xDEA6, 0x728C,
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+	0xDEC7, 0x75EF, 0xDEC8, 0x760F, 0xDEC9, 0x7603, 0xDECA, 0x75F7,	0xDECB, 0x75FE, 0xDECC, 0x75FC, 0xDECD, 0x75F9, 0xDECE, 0x75F8,
+	0xDECF, 0x7610, 0xDED0, 0x75FB, 0xDED1, 0x75F6, 0xDED2, 0x75ED,	0xDED3, 0x75F5, 0xDED4, 0x75FD, 0xDED5, 0x7699, 0xDED6, 0x76B5,
+	0xDED7, 0x76DD, 0xDED8, 0x7755, 0xDED9, 0x775F, 0xDEDA, 0x7760,	0xDEDB, 0x7752, 0xDEDC, 0x7756, 0xDEDD, 0x775A, 0xDEDE, 0x7769,
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+	0xDF48, 0x7B6D, 0xDF49, 0x7B74, 0xDF4A, 0x7B69, 0xDF4B, 0x7B72,	0xDF4C, 0x7B65, 0xDF4D, 0x7B73, 0xDF4E, 0x7B71, 0xDF4F, 0x7B70,
+	0xDF50, 0x7B61, 0xDF51, 0x7B78, 0xDF52, 0x7B76, 0xDF53, 0x7B63,	0xDF54, 0x7CB2, 0xDF55, 0x7CB4, 0xDF56, 0x7CAF, 0xDF57, 0x7D88,
+	0xDF58, 0x7D86, 0xDF59, 0x7D80, 0xDF5A, 0x7D8D, 0xDF5B, 0x7D7F,	0xDF5C, 0x7D85, 0xDF5D, 0x7D7A, 0xDF5E, 0x7D8E, 0xDF5F, 0x7D7B,
+	0xDF60, 0x7D83, 0xDF61, 0x7D7C, 0xDF62, 0x7D8C, 0xDF63, 0x7D94,	0xDF64, 0x7D84, 0xDF65, 0x7D7D, 0xDF66, 0x7D92, 0xDF67, 0x7F6D,
+	0xDF68, 0x7F6B, 0xDF69, 0x7F67, 0xDF6A, 0x7F68, 0xDF6B, 0x7F6C,	0xDF6C, 0x7FA6, 0xDF6D, 0x7FA5, 0xDF6E, 0x7FA7, 0xDF6F, 0x7FDB,
+	0xDF70, 0x7FDC, 0xDF71, 0x8021, 0xDF72, 0x8164, 0xDF73, 0x8160,	0xDF74, 0x8177, 0xDF75, 0x815C, 0xDF76, 0x8169, 0xDF77, 0x815B,
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+	0xDFA2, 0x8161, 0xDFA3, 0x821D, 0xDFA4, 0x8249, 0xDFA5, 0x8244,	0xDFA6, 0x8240, 0xDFA7, 0x8242, 0xDFA8, 0x8245, 0xDFA9, 0x84F1,
+	0xDFAA, 0x843F, 0xDFAB, 0x8456, 0xDFAC, 0x8476, 0xDFAD, 0x8479,	0xDFAE, 0x848F, 0xDFAF, 0x848D, 0xDFB0, 0x8465, 0xDFB1, 0x8451,
+	0xDFB2, 0x8440, 0xDFB3, 0x8486, 0xDFB4, 0x8467, 0xDFB5, 0x8430,	0xDFB6, 0x844D, 0xDFB7, 0x847D, 0xDFB8, 0x845A, 0xDFB9, 0x8459,
+	0xDFBA, 0x8474, 0xDFBB, 0x8473, 0xDFBC, 0x845D, 0xDFBD, 0x8507,	0xDFBE, 0x845E, 0xDFBF, 0x8437, 0xDFC0, 0x843A, 0xDFC1, 0x8434,
+	0xDFC2, 0x847A, 0xDFC3, 0x8443, 0xDFC4, 0x8478, 0xDFC5, 0x8432,	0xDFC6, 0x8445, 0xDFC7, 0x8429, 0xDFC8, 0x83D9, 0xDFC9, 0x844B,
+	0xDFCA, 0x842F, 0xDFCB, 0x8442, 0xDFCC, 0x842D, 0xDFCD, 0x845F,	0xDFCE, 0x8470, 0xDFCF, 0x8439, 0xDFD0, 0x844E, 0xDFD1, 0x844C,
+	0xDFD2, 0x8452, 0xDFD3, 0x846F, 0xDFD4, 0x84C5, 0xDFD5, 0x848E,	0xDFD6, 0x843B, 0xDFD7, 0x8447, 0xDFD8, 0x8436, 0xDFD9, 0x8433,
+	0xDFDA, 0x8468, 0xDFDB, 0x847E, 0xDFDC, 0x8444, 0xDFDD, 0x842B,	0xDFDE, 0x8460, 0xDFDF, 0x8454, 0xDFE0, 0x846E, 0xDFE1, 0x8450,
+	0xDFE2, 0x870B, 0xDFE3, 0x8704, 0xDFE4, 0x86F7, 0xDFE5, 0x870C,	0xDFE6, 0x86FA, 0xDFE7, 0x86D6, 0xDFE8, 0x86F5, 0xDFE9, 0x874D,
+	0xDFEA, 0x86F8, 0xDFEB, 0x870E, 0xDFEC, 0x8709, 0xDFED, 0x8701,	0xDFEE, 0x86F6, 0xDFEF, 0x870D, 0xDFF0, 0x8705, 0xDFF1, 0x88D6,
+	0xDFF2, 0x88CB, 0xDFF3, 0x88CD, 0xDFF4, 0x88CE, 0xDFF5, 0x88DE,	0xDFF6, 0x88DB, 0xDFF7, 0x88DA, 0xDFF8, 0x88CC, 0xDFF9, 0x88D0,
+	0xDFFA, 0x8985, 0xDFFB, 0x899B, 0xDFFC, 0x89DF, 0xDFFD, 0x89E5,	0xDFFE, 0x89E4, 0xE040, 0x89E1, 0xE041, 0x89E0, 0xE042, 0x89E2,
+	0xE043, 0x89DC, 0xE044, 0x89E6, 0xE045, 0x8A76, 0xE046, 0x8A86,	0xE047, 0x8A7F, 0xE048, 0x8A61, 0xE049, 0x8A3F, 0xE04A, 0x8A77,
+	0xE04B, 0x8A82, 0xE04C, 0x8A84, 0xE04D, 0x8A75, 0xE04E, 0x8A83,	0xE04F, 0x8A81, 0xE050, 0x8A74, 0xE051, 0x8A7A, 0xE052, 0x8C3C,
+	0xE053, 0x8C4B, 0xE054, 0x8C4A, 0xE055, 0x8C65, 0xE056, 0x8C64,	0xE057, 0x8C66, 0xE058, 0x8C86, 0xE059, 0x8C84, 0xE05A, 0x8C85,
+	0xE05B, 0x8CCC, 0xE05C, 0x8D68, 0xE05D, 0x8D69, 0xE05E, 0x8D91,	0xE05F, 0x8D8C, 0xE060, 0x8D8E, 0xE061, 0x8D8F, 0xE062, 0x8D8D,
+	0xE063, 0x8D93, 0xE064, 0x8D94, 0xE065, 0x8D90, 0xE066, 0x8D92,	0xE067, 0x8DF0, 0xE068, 0x8DE0, 0xE069, 0x8DEC, 0xE06A, 0x8DF1,
+	0xE06B, 0x8DEE, 0xE06C, 0x8DD0, 0xE06D, 0x8DE9, 0xE06E, 0x8DE3,	0xE06F, 0x8DE2, 0xE070, 0x8DE7, 0xE071, 0x8DF2, 0xE072, 0x8DEB,
+	0xE073, 0x8DF4, 0xE074, 0x8F06, 0xE075, 0x8EFF, 0xE076, 0x8F01,	0xE077, 0x8F00, 0xE078, 0x8F05, 0xE079, 0x8F07, 0xE07A, 0x8F08,
+	0xE07B, 0x8F02, 0xE07C, 0x8F0B, 0xE07D, 0x9052, 0xE07E, 0x903F,	0xE0A1, 0x9044, 0xE0A2, 0x9049, 0xE0A3, 0x903D, 0xE0A4, 0x9110,
+	0xE0A5, 0x910D, 0xE0A6, 0x910F, 0xE0A7, 0x9111, 0xE0A8, 0x9116,	0xE0A9, 0x9114, 0xE0AA, 0x910B, 0xE0AB, 0x910E, 0xE0AC, 0x916E,
+	0xE0AD, 0x916F, 0xE0AE, 0x9248, 0xE0AF, 0x9252, 0xE0B0, 0x9230,	0xE0B1, 0x923A, 0xE0B2, 0x9266, 0xE0B3, 0x9233, 0xE0B4, 0x9265,
+	0xE0B5, 0x925E, 0xE0B6, 0x9283, 0xE0B7, 0x922E, 0xE0B8, 0x924A,	0xE0B9, 0x9246, 0xE0BA, 0x926D, 0xE0BB, 0x926C, 0xE0BC, 0x924F,
+	0xE0BD, 0x9260, 0xE0BE, 0x9267, 0xE0BF, 0x926F, 0xE0C0, 0x9236,	0xE0C1, 0x9261, 0xE0C2, 0x9270, 0xE0C3, 0x9231, 0xE0C4, 0x9254,
+	0xE0C5, 0x9263, 0xE0C6, 0x9250, 0xE0C7, 0x9272, 0xE0C8, 0x924E,	0xE0C9, 0x9253, 0xE0CA, 0x924C, 0xE0CB, 0x9256, 0xE0CC, 0x9232,
+	0xE0CD, 0x959F, 0xE0CE, 0x959C, 0xE0CF, 0x959E, 0xE0D0, 0x959B,	0xE0D1, 0x9692, 0xE0D2, 0x9693, 0xE0D3, 0x9691, 0xE0D4, 0x9697,
+	0xE0D5, 0x96CE, 0xE0D6, 0x96FA, 0xE0D7, 0x96FD, 0xE0D8, 0x96F8,	0xE0D9, 0x96F5, 0xE0DA, 0x9773, 0xE0DB, 0x9777, 0xE0DC, 0x9778,
+	0xE0DD, 0x9772, 0xE0DE, 0x980F, 0xE0DF, 0x980D, 0xE0E0, 0x980E,	0xE0E1, 0x98AC, 0xE0E2, 0x98F6, 0xE0E3, 0x98F9, 0xE0E4, 0x99AF,
+	0xE0E5, 0x99B2, 0xE0E6, 0x99B0, 0xE0E7, 0x99B5, 0xE0E8, 0x9AAD,	0xE0E9, 0x9AAB, 0xE0EA, 0x9B5B, 0xE0EB, 0x9CEA, 0xE0EC, 0x9CED,
+	0xE0ED, 0x9CE7, 0xE0EE, 0x9E80, 0xE0EF, 0x9EFD, 0xE0F0, 0x50E6,	0xE0F1, 0x50D4, 0xE0F2, 0x50D7, 0xE0F3, 0x50E8, 0xE0F4, 0x50F3,
+	0xE0F5, 0x50DB, 0xE0F6, 0x50EA, 0xE0F7, 0x50DD, 0xE0F8, 0x50E4,	0xE0F9, 0x50D3, 0xE0FA, 0x50EC, 0xE0FB, 0x50F0, 0xE0FC, 0x50EF,
+	0xE0FD, 0x50E3, 0xE0FE, 0x50E0, 0xE140, 0x51D8, 0xE141, 0x5280,	0xE142, 0x5281, 0xE143, 0x52E9, 0xE144, 0x52EB, 0xE145, 0x5330,
+	0xE146, 0x53AC, 0xE147, 0x5627, 0xE148, 0x5615, 0xE149, 0x560C,	0xE14A, 0x5612, 0xE14B, 0x55FC, 0xE14C, 0x560F, 0xE14D, 0x561C,
+	0xE14E, 0x5601, 0xE14F, 0x5613, 0xE150, 0x5602, 0xE151, 0x55FA,	0xE152, 0x561D, 0xE153, 0x5604, 0xE154, 0x55FF, 0xE155, 0x55F9,
+	0xE156, 0x5889, 0xE157, 0x587C, 0xE158, 0x5890, 0xE159, 0x5898,	0xE15A, 0x5886, 0xE15B, 0x5881, 0xE15C, 0x587F, 0xE15D, 0x5874,
+	0xE15E, 0x588B, 0xE15F, 0x587A, 0xE160, 0x5887, 0xE161, 0x5891,	0xE162, 0x588E, 0xE163, 0x5876, 0xE164, 0x5882, 0xE165, 0x5888,
+	0xE166, 0x587B, 0xE167, 0x5894, 0xE168, 0x588F, 0xE169, 0x58FE,	0xE16A, 0x596B, 0xE16B, 0x5ADC, 0xE16C, 0x5AEE, 0xE16D, 0x5AE5,
+	0xE16E, 0x5AD5, 0xE16F, 0x5AEA, 0xE170, 0x5ADA, 0xE171, 0x5AED,	0xE172, 0x5AEB, 0xE173, 0x5AF3, 0xE174, 0x5AE2, 0xE175, 0x5AE0,
+	0xE176, 0x5ADB, 0xE177, 0x5AEC, 0xE178, 0x5ADE, 0xE179, 0x5ADD,	0xE17A, 0x5AD9, 0xE17B, 0x5AE8, 0xE17C, 0x5ADF, 0xE17D, 0x5B77,
+	0xE17E, 0x5BE0, 0xE1A1, 0x5BE3, 0xE1A2, 0x5C63, 0xE1A3, 0x5D82,	0xE1A4, 0x5D80, 0xE1A5, 0x5D7D, 0xE1A6, 0x5D86, 0xE1A7, 0x5D7A,
+	0xE1A8, 0x5D81, 0xE1A9, 0x5D77, 0xE1AA, 0x5D8A, 0xE1AB, 0x5D89,	0xE1AC, 0x5D88, 0xE1AD, 0x5D7E, 0xE1AE, 0x5D7C, 0xE1AF, 0x5D8D,
+	0xE1B0, 0x5D79, 0xE1B1, 0x5D7F, 0xE1B2, 0x5E58, 0xE1B3, 0x5E59,	0xE1B4, 0x5E53, 0xE1B5, 0x5ED8, 0xE1B6, 0x5ED1, 0xE1B7, 0x5ED7,
+	0xE1B8, 0x5ECE, 0xE1B9, 0x5EDC, 0xE1BA, 0x5ED5, 0xE1BB, 0x5ED9,	0xE1BC, 0x5ED2, 0xE1BD, 0x5ED4, 0xE1BE, 0x5F44, 0xE1BF, 0x5F43,
+	0xE1C0, 0x5F6F, 0xE1C1, 0x5FB6, 0xE1C2, 0x612C, 0xE1C3, 0x6128,	0xE1C4, 0x6141, 0xE1C5, 0x615E, 0xE1C6, 0x6171, 0xE1C7, 0x6173,
+	0xE1C8, 0x6152, 0xE1C9, 0x6153, 0xE1CA, 0x6172, 0xE1CB, 0x616C,	0xE1CC, 0x6180, 0xE1CD, 0x6174, 0xE1CE, 0x6154, 0xE1CF, 0x617A,
+	0xE1D0, 0x615B, 0xE1D1, 0x6165, 0xE1D2, 0x613B, 0xE1D3, 0x616A,	0xE1D4, 0x6161, 0xE1D5, 0x6156, 0xE1D6, 0x6229, 0xE1D7, 0x6227,
+	0xE1D8, 0x622B, 0xE1D9, 0x642B, 0xE1DA, 0x644D, 0xE1DB, 0x645B,	0xE1DC, 0x645D, 0xE1DD, 0x6474, 0xE1DE, 0x6476, 0xE1DF, 0x6472,
+	0xE1E0, 0x6473, 0xE1E1, 0x647D, 0xE1E2, 0x6475, 0xE1E3, 0x6466,	0xE1E4, 0x64A6, 0xE1E5, 0x644E, 0xE1E6, 0x6482, 0xE1E7, 0x645E,
+	0xE1E8, 0x645C, 0xE1E9, 0x644B, 0xE1EA, 0x6453, 0xE1EB, 0x6460,	0xE1EC, 0x6450, 0xE1ED, 0x647F, 0xE1EE, 0x643F, 0xE1EF, 0x646C,
+	0xE1F0, 0x646B, 0xE1F1, 0x6459, 0xE1F2, 0x6465, 0xE1F3, 0x6477,	0xE1F4, 0x6573, 0xE1F5, 0x65A0, 0xE1F6, 0x66A1, 0xE1F7, 0x66A0,
+	0xE1F8, 0x669F, 0xE1F9, 0x6705, 0xE1FA, 0x6704, 0xE1FB, 0x6722,	0xE1FC, 0x69B1, 0xE1FD, 0x69B6, 0xE1FE, 0x69C9, 0xE240, 0x69A0,
+	0xE241, 0x69CE, 0xE242, 0x6996, 0xE243, 0x69B0, 0xE244, 0x69AC,	0xE245, 0x69BC, 0xE246, 0x6991, 0xE247, 0x6999, 0xE248, 0x698E,
+	0xE249, 0x69A7, 0xE24A, 0x698D, 0xE24B, 0x69A9, 0xE24C, 0x69BE,	0xE24D, 0x69AF, 0xE24E, 0x69BF, 0xE24F, 0x69C4, 0xE250, 0x69BD,
+	0xE251, 0x69A4, 0xE252, 0x69D4, 0xE253, 0x69B9, 0xE254, 0x69CA,	0xE255, 0x699A, 0xE256, 0x69CF, 0xE257, 0x69B3, 0xE258, 0x6993,
+	0xE259, 0x69AA, 0xE25A, 0x69A1, 0xE25B, 0x699E, 0xE25C, 0x69D9,	0xE25D, 0x6997, 0xE25E, 0x6990, 0xE25F, 0x69C2, 0xE260, 0x69B5,
+	0xE261, 0x69A5, 0xE262, 0x69C6, 0xE263, 0x6B4A, 0xE264, 0x6B4D,	0xE265, 0x6B4B, 0xE266, 0x6B9E, 0xE267, 0x6B9F, 0xE268, 0x6BA0,
+	0xE269, 0x6BC3, 0xE26A, 0x6BC4, 0xE26B, 0x6BFE, 0xE26C, 0x6ECE,	0xE26D, 0x6EF5, 0xE26E, 0x6EF1, 0xE26F, 0x6F03, 0xE270, 0x6F25,
+	0xE271, 0x6EF8, 0xE272, 0x6F37, 0xE273, 0x6EFB, 0xE274, 0x6F2E,	0xE275, 0x6F09, 0xE276, 0x6F4E, 0xE277, 0x6F19, 0xE278, 0x6F1A,
+	0xE279, 0x6F27, 0xE27A, 0x6F18, 0xE27B, 0x6F3B, 0xE27C, 0x6F12,	0xE27D, 0x6EED, 0xE27E, 0x6F0A, 0xE2A1, 0x6F36, 0xE2A2, 0x6F73,
+	0xE2A3, 0x6EF9, 0xE2A4, 0x6EEE, 0xE2A5, 0x6F2D, 0xE2A6, 0x6F40,	0xE2A7, 0x6F30, 0xE2A8, 0x6F3C, 0xE2A9, 0x6F35, 0xE2AA, 0x6EEB,
+	0xE2AB, 0x6F07, 0xE2AC, 0x6F0E, 0xE2AD, 0x6F43, 0xE2AE, 0x6F05,	0xE2AF, 0x6EFD, 0xE2B0, 0x6EF6, 0xE2B1, 0x6F39, 0xE2B2, 0x6F1C,
+	0xE2B3, 0x6EFC, 0xE2B4, 0x6F3A, 0xE2B5, 0x6F1F, 0xE2B6, 0x6F0D,	0xE2B7, 0x6F1E, 0xE2B8, 0x6F08, 0xE2B9, 0x6F21, 0xE2BA, 0x7187,
+	0xE2BB, 0x7190, 0xE2BC, 0x7189, 0xE2BD, 0x7180, 0xE2BE, 0x7185,	0xE2BF, 0x7182, 0xE2C0, 0x718F, 0xE2C1, 0x717B, 0xE2C2, 0x7186,
+	0xE2C3, 0x7181, 0xE2C4, 0x7197, 0xE2C5, 0x7244, 0xE2C6, 0x7253,	0xE2C7, 0x7297, 0xE2C8, 0x7295, 0xE2C9, 0x7293, 0xE2CA, 0x7343,
+	0xE2CB, 0x734D, 0xE2CC, 0x7351, 0xE2CD, 0x734C, 0xE2CE, 0x7462,	0xE2CF, 0x7473, 0xE2D0, 0x7471, 0xE2D1, 0x7475, 0xE2D2, 0x7472,
+	0xE2D3, 0x7467, 0xE2D4, 0x746E, 0xE2D5, 0x7500, 0xE2D6, 0x7502,	0xE2D7, 0x7503, 0xE2D8, 0x757D, 0xE2D9, 0x7590, 0xE2DA, 0x7616,
+	0xE2DB, 0x7608, 0xE2DC, 0x760C, 0xE2DD, 0x7615, 0xE2DE, 0x7611,	0xE2DF, 0x760A, 0xE2E0, 0x7614, 0xE2E1, 0x76B8, 0xE2E2, 0x7781,
+	0xE2E3, 0x777C, 0xE2E4, 0x7785, 0xE2E5, 0x7782, 0xE2E6, 0x776E,	0xE2E7, 0x7780, 0xE2E8, 0x776F, 0xE2E9, 0x777E, 0xE2EA, 0x7783,
+	0xE2EB, 0x78B2, 0xE2EC, 0x78AA, 0xE2ED, 0x78B4, 0xE2EE, 0x78AD,	0xE2EF, 0x78A8, 0xE2F0, 0x787E, 0xE2F1, 0x78AB, 0xE2F2, 0x789E,
+	0xE2F3, 0x78A5, 0xE2F4, 0x78A0, 0xE2F5, 0x78AC, 0xE2F6, 0x78A2,	0xE2F7, 0x78A4, 0xE2F8, 0x7998, 0xE2F9, 0x798A, 0xE2FA, 0x798B,
+	0xE2FB, 0x7996, 0xE2FC, 0x7995, 0xE2FD, 0x7994, 0xE2FE, 0x7993,	0xE340, 0x7997, 0xE341, 0x7988, 0xE342, 0x7992, 0xE343, 0x7990,
+	0xE344, 0x7A2B, 0xE345, 0x7A4A, 0xE346, 0x7A30, 0xE347, 0x7A2F,	0xE348, 0x7A28, 0xE349, 0x7A26, 0xE34A, 0x7AA8, 0xE34B, 0x7AAB,
+	0xE34C, 0x7AAC, 0xE34D, 0x7AEE, 0xE34E, 0x7B88, 0xE34F, 0x7B9C,	0xE350, 0x7B8A, 0xE351, 0x7B91, 0xE352, 0x7B90, 0xE353, 0x7B96,
+	0xE354, 0x7B8D, 0xE355, 0x7B8C, 0xE356, 0x7B9B, 0xE357, 0x7B8E,	0xE358, 0x7B85, 0xE359, 0x7B98, 0xE35A, 0x5284, 0xE35B, 0x7B99,
+	0xE35C, 0x7BA4, 0xE35D, 0x7B82, 0xE35E, 0x7CBB, 0xE35F, 0x7CBF,	0xE360, 0x7CBC, 0xE361, 0x7CBA, 0xE362, 0x7DA7, 0xE363, 0x7DB7,
+	0xE364, 0x7DC2, 0xE365, 0x7DA3, 0xE366, 0x7DAA, 0xE367, 0x7DC1,	0xE368, 0x7DC0, 0xE369, 0x7DC5, 0xE36A, 0x7D9D, 0xE36B, 0x7DCE,
+	0xE36C, 0x7DC4, 0xE36D, 0x7DC6, 0xE36E, 0x7DCB, 0xE36F, 0x7DCC,	0xE370, 0x7DAF, 0xE371, 0x7DB9, 0xE372, 0x7D96, 0xE373, 0x7DBC,
+	0xE374, 0x7D9F, 0xE375, 0x7DA6, 0xE376, 0x7DAE, 0xE377, 0x7DA9,	0xE378, 0x7DA1, 0xE379, 0x7DC9, 0xE37A, 0x7F73, 0xE37B, 0x7FE2,
+	0xE37C, 0x7FE3, 0xE37D, 0x7FE5, 0xE37E, 0x7FDE, 0xE3A1, 0x8024,	0xE3A2, 0x805D, 0xE3A3, 0x805C, 0xE3A4, 0x8189, 0xE3A5, 0x8186,
+	0xE3A6, 0x8183, 0xE3A7, 0x8187, 0xE3A8, 0x818D, 0xE3A9, 0x818C,	0xE3AA, 0x818B, 0xE3AB, 0x8215, 0xE3AC, 0x8497, 0xE3AD, 0x84A4,
+	0xE3AE, 0x84A1, 0xE3AF, 0x849F, 0xE3B0, 0x84BA, 0xE3B1, 0x84CE,	0xE3B2, 0x84C2, 0xE3B3, 0x84AC, 0xE3B4, 0x84AE, 0xE3B5, 0x84AB,
+	0xE3B6, 0x84B9, 0xE3B7, 0x84B4, 0xE3B8, 0x84C1, 0xE3B9, 0x84CD,	0xE3BA, 0x84AA, 0xE3BB, 0x849A, 0xE3BC, 0x84B1, 0xE3BD, 0x84D0,
+	0xE3BE, 0x849D, 0xE3BF, 0x84A7, 0xE3C0, 0x84BB, 0xE3C1, 0x84A2,	0xE3C2, 0x8494, 0xE3C3, 0x84C7, 0xE3C4, 0x84CC, 0xE3C5, 0x849B,
+	0xE3C6, 0x84A9, 0xE3C7, 0x84AF, 0xE3C8, 0x84A8, 0xE3C9, 0x84D6,	0xE3CA, 0x8498, 0xE3CB, 0x84B6, 0xE3CC, 0x84CF, 0xE3CD, 0x84A0,
+	0xE3CE, 0x84D7, 0xE3CF, 0x84D4, 0xE3D0, 0x84D2, 0xE3D1, 0x84DB,	0xE3D2, 0x84B0, 0xE3D3, 0x8491, 0xE3D4, 0x8661, 0xE3D5, 0x8733,
+	0xE3D6, 0x8723, 0xE3D7, 0x8728, 0xE3D8, 0x876B, 0xE3D9, 0x8740,	0xE3DA, 0x872E, 0xE3DB, 0x871E, 0xE3DC, 0x8721, 0xE3DD, 0x8719,
+	0xE3DE, 0x871B, 0xE3DF, 0x8743, 0xE3E0, 0x872C, 0xE3E1, 0x8741,	0xE3E2, 0x873E, 0xE3E3, 0x8746, 0xE3E4, 0x8720, 0xE3E5, 0x8732,
+	0xE3E6, 0x872A, 0xE3E7, 0x872D, 0xE3E8, 0x873C, 0xE3E9, 0x8712,	0xE3EA, 0x873A, 0xE3EB, 0x8731, 0xE3EC, 0x8735, 0xE3ED, 0x8742,
+	0xE3EE, 0x8726, 0xE3EF, 0x8727, 0xE3F0, 0x8738, 0xE3F1, 0x8724,	0xE3F2, 0x871A, 0xE3F3, 0x8730, 0xE3F4, 0x8711, 0xE3F5, 0x88F7,
+	0xE3F6, 0x88E7, 0xE3F7, 0x88F1, 0xE3F8, 0x88F2, 0xE3F9, 0x88FA,	0xE3FA, 0x88FE, 0xE3FB, 0x88EE, 0xE3FC, 0x88FC, 0xE3FD, 0x88F6,
+	0xE3FE, 0x88FB, 0xE440, 0x88F0, 0xE441, 0x88EC, 0xE442, 0x88EB,	0xE443, 0x899D, 0xE444, 0x89A1, 0xE445, 0x899F, 0xE446, 0x899E,
+	0xE447, 0x89E9, 0xE448, 0x89EB, 0xE449, 0x89E8, 0xE44A, 0x8AAB,	0xE44B, 0x8A99, 0xE44C, 0x8A8B, 0xE44D, 0x8A92, 0xE44E, 0x8A8F,
+	0xE44F, 0x8A96, 0xE450, 0x8C3D, 0xE451, 0x8C68, 0xE452, 0x8C69,	0xE453, 0x8CD5, 0xE454, 0x8CCF, 0xE455, 0x8CD7, 0xE456, 0x8D96,
+	0xE457, 0x8E09, 0xE458, 0x8E02, 0xE459, 0x8DFF, 0xE45A, 0x8E0D,	0xE45B, 0x8DFD, 0xE45C, 0x8E0A, 0xE45D, 0x8E03, 0xE45E, 0x8E07,
+	0xE45F, 0x8E06, 0xE460, 0x8E05, 0xE461, 0x8DFE, 0xE462, 0x8E00,	0xE463, 0x8E04, 0xE464, 0x8F10, 0xE465, 0x8F11, 0xE466, 0x8F0E,
+	0xE467, 0x8F0D, 0xE468, 0x9123, 0xE469, 0x911C, 0xE46A, 0x9120,	0xE46B, 0x9122, 0xE46C, 0x911F, 0xE46D, 0x911D, 0xE46E, 0x911A,
+	0xE46F, 0x9124, 0xE470, 0x9121, 0xE471, 0x911B, 0xE472, 0x917A,	0xE473, 0x9172, 0xE474, 0x9179, 0xE475, 0x9173, 0xE476, 0x92A5,
+	0xE477, 0x92A4, 0xE478, 0x9276, 0xE479, 0x929B, 0xE47A, 0x927A,	0xE47B, 0x92A0, 0xE47C, 0x9294, 0xE47D, 0x92AA, 0xE47E, 0x928D,
+	0xE4A1, 0x92A6, 0xE4A2, 0x929A, 0xE4A3, 0x92AB, 0xE4A4, 0x9279,	0xE4A5, 0x9297, 0xE4A6, 0x927F, 0xE4A7, 0x92A3, 0xE4A8, 0x92EE,
+	0xE4A9, 0x928E, 0xE4AA, 0x9282, 0xE4AB, 0x9295, 0xE4AC, 0x92A2,	0xE4AD, 0x927D, 0xE4AE, 0x9288, 0xE4AF, 0x92A1, 0xE4B0, 0x928A,
+	0xE4B1, 0x9286, 0xE4B2, 0x928C, 0xE4B3, 0x9299, 0xE4B4, 0x92A7,	0xE4B5, 0x927E, 0xE4B6, 0x9287, 0xE4B7, 0x92A9, 0xE4B8, 0x929D,
+	0xE4B9, 0x928B, 0xE4BA, 0x922D, 0xE4BB, 0x969E, 0xE4BC, 0x96A1,	0xE4BD, 0x96FF, 0xE4BE, 0x9758, 0xE4BF, 0x977D, 0xE4C0, 0x977A,
+	0xE4C1, 0x977E, 0xE4C2, 0x9783, 0xE4C3, 0x9780, 0xE4C4, 0x9782,	0xE4C5, 0x977B, 0xE4C6, 0x9784, 0xE4C7, 0x9781, 0xE4C8, 0x977F,
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+	0xE4D1, 0x999D, 0xE4D2, 0x999C, 0xE4D3, 0x99C3, 0xE4D4, 0x99B9,	0xE4D5, 0x99BB, 0xE4D6, 0x99BA, 0xE4D7, 0x99C2, 0xE4D8, 0x99BD,
+	0xE4D9, 0x99C7, 0xE4DA, 0x9AB1, 0xE4DB, 0x9AE3, 0xE4DC, 0x9AE7,	0xE4DD, 0x9B3E, 0xE4DE, 0x9B3F, 0xE4DF, 0x9B60, 0xE4E0, 0x9B61,
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+	0xE562, 0x5D99, 0xE563, 0x5D97, 0xE564, 0x5D9F, 0xE565, 0x5D92,	0xE566, 0x5DA2, 0xE567, 0x5D93, 0xE568, 0x5D95, 0xE569, 0x5DA0,
+	0xE56A, 0x5D9C, 0xE56B, 0x5DA1, 0xE56C, 0x5D9A, 0xE56D, 0x5D9E,	0xE56E, 0x5E69, 0xE56F, 0x5E5D, 0xE570, 0x5E60, 0xE571, 0x5E5C,
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+	0xE5A4, 0x61AD, 0xE5A5, 0x619F, 0xE5A6, 0x6192, 0xE5A7, 0x61AA,	0xE5A8, 0x61A1, 0xE5A9, 0x618D, 0xE5AA, 0x6166, 0xE5AB, 0x61B3,
+	0xE5AC, 0x622D, 0xE5AD, 0x646E, 0xE5AE, 0x6470, 0xE5AF, 0x6496,	0xE5B0, 0x64A0, 0xE5B1, 0x6485, 0xE5B2, 0x6497, 0xE5B3, 0x649C,
+	0xE5B4, 0x648F, 0xE5B5, 0x648B, 0xE5B6, 0x648A, 0xE5B7, 0x648C,	0xE5B8, 0x64A3, 0xE5B9, 0x649F, 0xE5BA, 0x6468, 0xE5BB, 0x64B1,
+	0xE5BC, 0x6498, 0xE5BD, 0x6576, 0xE5BE, 0x657A, 0xE5BF, 0x6579,	0xE5C0, 0x657B, 0xE5C1, 0x65B2, 0xE5C2, 0x65B3, 0xE5C3, 0x66B5,
+	0xE5C4, 0x66B0, 0xE5C5, 0x66A9, 0xE5C6, 0x66B2, 0xE5C7, 0x66B7,	0xE5C8, 0x66AA, 0xE5C9, 0x66AF, 0xE5CA, 0x6A00, 0xE5CB, 0x6A06,
+	0xE5CC, 0x6A17, 0xE5CD, 0x69E5, 0xE5CE, 0x69F8, 0xE5CF, 0x6A15,	0xE5D0, 0x69F1, 0xE5D1, 0x69E4, 0xE5D2, 0x6A20, 0xE5D3, 0x69FF,
+	0xE5D4, 0x69EC, 0xE5D5, 0x69E2, 0xE5D6, 0x6A1B, 0xE5D7, 0x6A1D,	0xE5D8, 0x69FE, 0xE5D9, 0x6A27, 0xE5DA, 0x69F2, 0xE5DB, 0x69EE,
+	0xE5DC, 0x6A14, 0xE5DD, 0x69F7, 0xE5DE, 0x69E7, 0xE5DF, 0x6A40,	0xE5E0, 0x6A08, 0xE5E1, 0x69E6, 0xE5E2, 0x69FB, 0xE5E3, 0x6A0D,
+	0xE5E4, 0x69FC, 0xE5E5, 0x69EB, 0xE5E6, 0x6A09, 0xE5E7, 0x6A04,	0xE5E8, 0x6A18, 0xE5E9, 0x6A25, 0xE5EA, 0x6A0F, 0xE5EB, 0x69F6,
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+	0xE8CD, 0x99D6, 0xE8CE, 0x99D8, 0xE8CF, 0x99CB, 0xE8D0, 0x99D7,	0xE8D1, 0x99CC, 0xE8D2, 0x9AB3, 0xE8D3, 0x9AEC, 0xE8D4, 0x9AEB,
+	0xE8D5, 0x9AF3, 0xE8D6, 0x9AF2, 0xE8D7, 0x9AF1, 0xE8D8, 0x9B46,	0xE8D9, 0x9B43, 0xE8DA, 0x9B67, 0xE8DB, 0x9B74, 0xE8DC, 0x9B71,
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+	0xF07B, 0x7FF8, 0xF07C, 0x8075, 0xF07D, 0x81D1, 0xF07E, 0x81D2,	0xF0A1, 0x81D0, 0xF0A2, 0x825F, 0xF0A3, 0x825E, 0xF0A4, 0x85B4,
+	0xF0A5, 0x85C6, 0xF0A6, 0x85C0, 0xF0A7, 0x85C3, 0xF0A8, 0x85C2,	0xF0A9, 0x85B3, 0xF0AA, 0x85B5, 0xF0AB, 0x85BD, 0xF0AC, 0x85C7,
+	0xF0AD, 0x85C4, 0xF0AE, 0x85BF, 0xF0AF, 0x85CB, 0xF0B0, 0x85CE,	0xF0B1, 0x85C8, 0xF0B2, 0x85C5, 0xF0B3, 0x85B1, 0xF0B4, 0x85B6,
+	0xF0B5, 0x85D2, 0xF0B6, 0x8624, 0xF0B7, 0x85B8, 0xF0B8, 0x85B7,	0xF0B9, 0x85BE, 0xF0BA, 0x8669, 0xF0BB, 0x87E7, 0xF0BC, 0x87E6,
+	0xF0BD, 0x87E2, 0xF0BE, 0x87DB, 0xF0BF, 0x87EB, 0xF0C0, 0x87EA,	0xF0C1, 0x87E5, 0xF0C2, 0x87DF, 0xF0C3, 0x87F3, 0xF0C4, 0x87E4,
+	0xF0C5, 0x87D4, 0xF0C6, 0x87DC, 0xF0C7, 0x87D3, 0xF0C8, 0x87ED,	0xF0C9, 0x87D8, 0xF0CA, 0x87E3, 0xF0CB, 0x87A4, 0xF0CC, 0x87D7,
+	0xF0CD, 0x87D9, 0xF0CE, 0x8801, 0xF0CF, 0x87F4, 0xF0D0, 0x87E8,	0xF0D1, 0x87DD, 0xF0D2, 0x8953, 0xF0D3, 0x894B, 0xF0D4, 0x894F,
+	0xF0D5, 0x894C, 0xF0D6, 0x8946, 0xF0D7, 0x8950, 0xF0D8, 0x8951,	0xF0D9, 0x8949, 0xF0DA, 0x8B2A, 0xF0DB, 0x8B27, 0xF0DC, 0x8B23,
+	0xF0DD, 0x8B33, 0xF0DE, 0x8B30, 0xF0DF, 0x8B35, 0xF0E0, 0x8B47,	0xF0E1, 0x8B2F, 0xF0E2, 0x8B3C, 0xF0E3, 0x8B3E, 0xF0E4, 0x8B31,
+	0xF0E5, 0x8B25, 0xF0E6, 0x8B37, 0xF0E7, 0x8B26, 0xF0E8, 0x8B36,	0xF0E9, 0x8B2E, 0xF0EA, 0x8B24, 0xF0EB, 0x8B3B, 0xF0EC, 0x8B3D,
+	0xF0ED, 0x8B3A, 0xF0EE, 0x8C42, 0xF0EF, 0x8C75, 0xF0F0, 0x8C99,	0xF0F1, 0x8C98, 0xF0F2, 0x8C97, 0xF0F3, 0x8CFE, 0xF0F4, 0x8D04,
+	0xF0F5, 0x8D02, 0xF0F6, 0x8D00, 0xF0F7, 0x8E5C, 0xF0F8, 0x8E62,	0xF0F9, 0x8E60, 0xF0FA, 0x8E57, 0xF0FB, 0x8E56, 0xF0FC, 0x8E5E,
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+	0xF146, 0x8F46, 0xF147, 0x8F47, 0xF148, 0x8F48, 0xF149, 0x8F4B,	0xF14A, 0x9128, 0xF14B, 0x913A, 0xF14C, 0x913B, 0xF14D, 0x913E,
+	0xF14E, 0x91A8, 0xF14F, 0x91A5, 0xF150, 0x91A7, 0xF151, 0x91AF,	0xF152, 0x91AA, 0xF153, 0x93B5, 0xF154, 0x938C, 0xF155, 0x9392,
+	0xF156, 0x93B7, 0xF157, 0x939B, 0xF158, 0x939D, 0xF159, 0x9389,	0xF15A, 0x93A7, 0xF15B, 0x938E, 0xF15C, 0x93AA, 0xF15D, 0x939E,
+	0xF15E, 0x93A6, 0xF15F, 0x9395, 0xF160, 0x9388, 0xF161, 0x9399,	0xF162, 0x939F, 0xF163, 0x938D, 0xF164, 0x93B1, 0xF165, 0x9391,
+	0xF166, 0x93B2, 0xF167, 0x93A4, 0xF168, 0x93A8, 0xF169, 0x93B4,	0xF16A, 0x93A3, 0xF16B, 0x93A5, 0xF16C, 0x95D2, 0xF16D, 0x95D3,
+	0xF16E, 0x95D1, 0xF16F, 0x96B3, 0xF170, 0x96D7, 0xF171, 0x96DA,	0xF172, 0x5DC2, 0xF173, 0x96DF, 0xF174, 0x96D8, 0xF175, 0x96DD,
+	0xF176, 0x9723, 0xF177, 0x9722, 0xF178, 0x9725, 0xF179, 0x97AC,	0xF17A, 0x97AE, 0xF17B, 0x97A8, 0xF17C, 0x97AB, 0xF17D, 0x97A4,
+	0xF17E, 0x97AA, 0xF1A1, 0x97A2, 0xF1A2, 0x97A5, 0xF1A3, 0x97D7,	0xF1A4, 0x97D9, 0xF1A5, 0x97D6, 0xF1A6, 0x97D8, 0xF1A7, 0x97FA,
+	0xF1A8, 0x9850, 0xF1A9, 0x9851, 0xF1AA, 0x9852, 0xF1AB, 0x98B8,	0xF1AC, 0x9941, 0xF1AD, 0x993C, 0xF1AE, 0x993A, 0xF1AF, 0x9A0F,
+	0xF1B0, 0x9A0B, 0xF1B1, 0x9A09, 0xF1B2, 0x9A0D, 0xF1B3, 0x9A04,	0xF1B4, 0x9A11, 0xF1B5, 0x9A0A, 0xF1B6, 0x9A05, 0xF1B7, 0x9A07,
+	0xF1B8, 0x9A06, 0xF1B9, 0x9AC0, 0xF1BA, 0x9ADC, 0xF1BB, 0x9B08,	0xF1BC, 0x9B04, 0xF1BD, 0x9B05, 0xF1BE, 0x9B29, 0xF1BF, 0x9B35,
+	0xF1C0, 0x9B4A, 0xF1C1, 0x9B4C, 0xF1C2, 0x9B4B, 0xF1C3, 0x9BC7,	0xF1C4, 0x9BC6, 0xF1C5, 0x9BC3, 0xF1C6, 0x9BBF, 0xF1C7, 0x9BC1,
+	0xF1C8, 0x9BB5, 0xF1C9, 0x9BB8, 0xF1CA, 0x9BD3, 0xF1CB, 0x9BB6,	0xF1CC, 0x9BC4, 0xF1CD, 0x9BB9, 0xF1CE, 0x9BBD, 0xF1CF, 0x9D5C,
+	0xF1D0, 0x9D53, 0xF1D1, 0x9D4F, 0xF1D2, 0x9D4A, 0xF1D3, 0x9D5B,	0xF1D4, 0x9D4B, 0xF1D5, 0x9D59, 0xF1D6, 0x9D56, 0xF1D7, 0x9D4C,
+	0xF1D8, 0x9D57, 0xF1D9, 0x9D52, 0xF1DA, 0x9D54, 0xF1DB, 0x9D5F,	0xF1DC, 0x9D58, 0xF1DD, 0x9D5A, 0xF1DE, 0x9E8E, 0xF1DF, 0x9E8C,
+	0xF1E0, 0x9EDF, 0xF1E1, 0x9F01, 0xF1E2, 0x9F00, 0xF1E3, 0x9F16,	0xF1E4, 0x9F25, 0xF1E5, 0x9F2B, 0xF1E6, 0x9F2A, 0xF1E7, 0x9F29,
+	0xF1E8, 0x9F28, 0xF1E9, 0x9F4C, 0xF1EA, 0x9F55, 0xF1EB, 0x5134,	0xF1EC, 0x5135, 0xF1ED, 0x5296, 0xF1EE, 0x52F7, 0xF1EF, 0x53B4,
+	0xF1F0, 0x56AB, 0xF1F1, 0x56AD, 0xF1F2, 0x56A6, 0xF1F3, 0x56A7,	0xF1F4, 0x56AA, 0xF1F5, 0x56AC, 0xF1F6, 0x58DA, 0xF1F7, 0x58DD,
+	0xF1F8, 0x58DB, 0xF1F9, 0x5912, 0xF1FA, 0x5B3D, 0xF1FB, 0x5B3E,	0xF1FC, 0x5B3F, 0xF1FD, 0x5DC3, 0xF1FE, 0x5E70, 0xF240, 0x5FBF,
+	0xF241, 0x61FB, 0xF242, 0x6507, 0xF243, 0x6510, 0xF244, 0x650D,	0xF245, 0x6509, 0xF246, 0x650C, 0xF247, 0x650E, 0xF248, 0x6584,
+	0xF249, 0x65DE, 0xF24A, 0x65DD, 0xF24B, 0x66DE, 0xF24C, 0x6AE7,	0xF24D, 0x6AE0, 0xF24E, 0x6ACC, 0xF24F, 0x6AD1, 0xF250, 0x6AD9,
+	0xF251, 0x6ACB, 0xF252, 0x6ADF, 0xF253, 0x6ADC, 0xF254, 0x6AD0,	0xF255, 0x6AEB, 0xF256, 0x6ACF, 0xF257, 0x6ACD, 0xF258, 0x6ADE,
+	0xF259, 0x6B60, 0xF25A, 0x6BB0, 0xF25B, 0x6C0C, 0xF25C, 0x7019,	0xF25D, 0x7027, 0xF25E, 0x7020, 0xF25F, 0x7016, 0xF260, 0x702B,
+	0xF261, 0x7021, 0xF262, 0x7022, 0xF263, 0x7023, 0xF264, 0x7029,	0xF265, 0x7017, 0xF266, 0x7024, 0xF267, 0x701C, 0xF268, 0x702A,
+	0xF269, 0x720C, 0xF26A, 0x720A, 0xF26B, 0x7207, 0xF26C, 0x7202,	0xF26D, 0x7205, 0xF26E, 0x72A5, 0xF26F, 0x72A6, 0xF270, 0x72A4,
+	0xF271, 0x72A3, 0xF272, 0x72A1, 0xF273, 0x74CB, 0xF274, 0x74C5,	0xF275, 0x74B7, 0xF276, 0x74C3, 0xF277, 0x7516, 0xF278, 0x7660,
+	0xF279, 0x77C9, 0xF27A, 0x77CA, 0xF27B, 0x77C4, 0xF27C, 0x77F1,	0xF27D, 0x791D, 0xF27E, 0x791B, 0xF2A1, 0x7921, 0xF2A2, 0x791C,
+	0xF2A3, 0x7917, 0xF2A4, 0x791E, 0xF2A5, 0x79B0, 0xF2A6, 0x7A67,	0xF2A7, 0x7A68, 0xF2A8, 0x7C33, 0xF2A9, 0x7C3C, 0xF2AA, 0x7C39,
+	0xF2AB, 0x7C2C, 0xF2AC, 0x7C3B, 0xF2AD, 0x7CEC, 0xF2AE, 0x7CEA,	0xF2AF, 0x7E76, 0xF2B0, 0x7E75, 0xF2B1, 0x7E78, 0xF2B2, 0x7E70,
+	0xF2B3, 0x7E77, 0xF2B4, 0x7E6F, 0xF2B5, 0x7E7A, 0xF2B6, 0x7E72,	0xF2B7, 0x7E74, 0xF2B8, 0x7E68, 0xF2B9, 0x7F4B, 0xF2BA, 0x7F4A,
+	0xF2BB, 0x7F83, 0xF2BC, 0x7F86, 0xF2BD, 0x7FB7, 0xF2BE, 0x7FFD,	0xF2BF, 0x7FFE, 0xF2C0, 0x8078, 0xF2C1, 0x81D7, 0xF2C2, 0x81D5,
+	0xF2C3, 0x8264, 0xF2C4, 0x8261, 0xF2C5, 0x8263, 0xF2C6, 0x85EB,	0xF2C7, 0x85F1, 0xF2C8, 0x85ED, 0xF2C9, 0x85D9, 0xF2CA, 0x85E1,
+	0xF2CB, 0x85E8, 0xF2CC, 0x85DA, 0xF2CD, 0x85D7, 0xF2CE, 0x85EC,	0xF2CF, 0x85F2, 0xF2D0, 0x85F8, 0xF2D1, 0x85D8, 0xF2D2, 0x85DF,
+	0xF2D3, 0x85E3, 0xF2D4, 0x85DC, 0xF2D5, 0x85D1, 0xF2D6, 0x85F0,	0xF2D7, 0x85E6, 0xF2D8, 0x85EF, 0xF2D9, 0x85DE, 0xF2DA, 0x85E2,
+	0xF2DB, 0x8800, 0xF2DC, 0x87FA, 0xF2DD, 0x8803, 0xF2DE, 0x87F6,	0xF2DF, 0x87F7, 0xF2E0, 0x8809, 0xF2E1, 0x880C, 0xF2E2, 0x880B,
+	0xF2E3, 0x8806, 0xF2E4, 0x87FC, 0xF2E5, 0x8808, 0xF2E6, 0x87FF,	0xF2E7, 0x880A, 0xF2E8, 0x8802, 0xF2E9, 0x8962, 0xF2EA, 0x895A,
+	0xF2EB, 0x895B, 0xF2EC, 0x8957, 0xF2ED, 0x8961, 0xF2EE, 0x895C,	0xF2EF, 0x8958, 0xF2F0, 0x895D, 0xF2F1, 0x8959, 0xF2F2, 0x8988,
+	0xF2F3, 0x89B7, 0xF2F4, 0x89B6, 0xF2F5, 0x89F6, 0xF2F6, 0x8B50,	0xF2F7, 0x8B48, 0xF2F8, 0x8B4A, 0xF2F9, 0x8B40, 0xF2FA, 0x8B53,
+	0xF2FB, 0x8B56, 0xF2FC, 0x8B54, 0xF2FD, 0x8B4B, 0xF2FE, 0x8B55,	0xF340, 0x8B51, 0xF341, 0x8B42, 0xF342, 0x8B52, 0xF343, 0x8B57,
+	0xF344, 0x8C43, 0xF345, 0x8C77, 0xF346, 0x8C76, 0xF347, 0x8C9A,	0xF348, 0x8D06, 0xF349, 0x8D07, 0xF34A, 0x8D09, 0xF34B, 0x8DAC,
+	0xF34C, 0x8DAA, 0xF34D, 0x8DAD, 0xF34E, 0x8DAB, 0xF34F, 0x8E6D,	0xF350, 0x8E78, 0xF351, 0x8E73, 0xF352, 0x8E6A, 0xF353, 0x8E6F,
+	0xF354, 0x8E7B, 0xF355, 0x8EC2, 0xF356, 0x8F52, 0xF357, 0x8F51,	0xF358, 0x8F4F, 0xF359, 0x8F50, 0xF35A, 0x8F53, 0xF35B, 0x8FB4,
+	0xF35C, 0x9140, 0xF35D, 0x913F, 0xF35E, 0x91B0, 0xF35F, 0x91AD,	0xF360, 0x93DE, 0xF361, 0x93C7, 0xF362, 0x93CF, 0xF363, 0x93C2,
+	0xF364, 0x93DA, 0xF365, 0x93D0, 0xF366, 0x93F9, 0xF367, 0x93EC,	0xF368, 0x93CC, 0xF369, 0x93D9, 0xF36A, 0x93A9, 0xF36B, 0x93E6,
+	0xF36C, 0x93CA, 0xF36D, 0x93D4, 0xF36E, 0x93EE, 0xF36F, 0x93E3,	0xF370, 0x93D5, 0xF371, 0x93C4, 0xF372, 0x93CE, 0xF373, 0x93C0,
+	0xF374, 0x93D2, 0xF375, 0x93E7, 0xF376, 0x957D, 0xF377, 0x95DA,	0xF378, 0x95DB, 0xF379, 0x96E1, 0xF37A, 0x9729, 0xF37B, 0x972B,
+	0xF37C, 0x972C, 0xF37D, 0x9728, 0xF37E, 0x9726, 0xF3A1, 0x97B3,	0xF3A2, 0x97B7, 0xF3A3, 0x97B6, 0xF3A4, 0x97DD, 0xF3A5, 0x97DE,
+	0xF3A6, 0x97DF, 0xF3A7, 0x985C, 0xF3A8, 0x9859, 0xF3A9, 0x985D,	0xF3AA, 0x9857, 0xF3AB, 0x98BF, 0xF3AC, 0x98BD, 0xF3AD, 0x98BB,
+	0xF3AE, 0x98BE, 0xF3AF, 0x9948, 0xF3B0, 0x9947, 0xF3B1, 0x9943,	0xF3B2, 0x99A6, 0xF3B3, 0x99A7, 0xF3B4, 0x9A1A, 0xF3B5, 0x9A15,
+	0xF3B6, 0x9A25, 0xF3B7, 0x9A1D, 0xF3B8, 0x9A24, 0xF3B9, 0x9A1B,	0xF3BA, 0x9A22, 0xF3BB, 0x9A20, 0xF3BC, 0x9A27, 0xF3BD, 0x9A23,
+	0xF3BE, 0x9A1E, 0xF3BF, 0x9A1C, 0xF3C0, 0x9A14, 0xF3C1, 0x9AC2,	0xF3C2, 0x9B0B, 0xF3C3, 0x9B0A, 0xF3C4, 0x9B0E, 0xF3C5, 0x9B0C,
+	0xF3C6, 0x9B37, 0xF3C7, 0x9BEA, 0xF3C8, 0x9BEB, 0xF3C9, 0x9BE0,	0xF3CA, 0x9BDE, 0xF3CB, 0x9BE4, 0xF3CC, 0x9BE6, 0xF3CD, 0x9BE2,
+	0xF3CE, 0x9BF0, 0xF3CF, 0x9BD4, 0xF3D0, 0x9BD7, 0xF3D1, 0x9BEC,	0xF3D2, 0x9BDC, 0xF3D3, 0x9BD9, 0xF3D4, 0x9BE5, 0xF3D5, 0x9BD5,
+	0xF3D6, 0x9BE1, 0xF3D7, 0x9BDA, 0xF3D8, 0x9D77, 0xF3D9, 0x9D81,	0xF3DA, 0x9D8A, 0xF3DB, 0x9D84, 0xF3DC, 0x9D88, 0xF3DD, 0x9D71,
+	0xF3DE, 0x9D80, 0xF3DF, 0x9D78, 0xF3E0, 0x9D86, 0xF3E1, 0x9D8B,	0xF3E2, 0x9D8C, 0xF3E3, 0x9D7D, 0xF3E4, 0x9D6B, 0xF3E5, 0x9D74,
+	0xF3E6, 0x9D75, 0xF3E7, 0x9D70, 0xF3E8, 0x9D69, 0xF3E9, 0x9D85,	0xF3EA, 0x9D73, 0xF3EB, 0x9D7B, 0xF3EC, 0x9D82, 0xF3ED, 0x9D6F,
+	0xF3EE, 0x9D79, 0xF3EF, 0x9D7F, 0xF3F0, 0x9D87, 0xF3F1, 0x9D68,	0xF3F2, 0x9E94, 0xF3F3, 0x9E91, 0xF3F4, 0x9EC0, 0xF3F5, 0x9EFC,
+	0xF3F6, 0x9F2D, 0xF3F7, 0x9F40, 0xF3F8, 0x9F41, 0xF3F9, 0x9F4D,	0xF3FA, 0x9F56, 0xF3FB, 0x9F57, 0xF3FC, 0x9F58, 0xF3FD, 0x5337,
+	0xF3FE, 0x56B2, 0xF440, 0x56B5, 0xF441, 0x56B3, 0xF442, 0x58E3,	0xF443, 0x5B45, 0xF444, 0x5DC6, 0xF445, 0x5DC7, 0xF446, 0x5EEE,
+	0xF447, 0x5EEF, 0xF448, 0x5FC0, 0xF449, 0x5FC1, 0xF44A, 0x61F9,	0xF44B, 0x6517, 0xF44C, 0x6516, 0xF44D, 0x6515, 0xF44E, 0x6513,
+	0xF44F, 0x65DF, 0xF450, 0x66E8, 0xF451, 0x66E3, 0xF452, 0x66E4,	0xF453, 0x6AF3, 0xF454, 0x6AF0, 0xF455, 0x6AEA, 0xF456, 0x6AE8,
+	0xF457, 0x6AF9, 0xF458, 0x6AF1, 0xF459, 0x6AEE, 0xF45A, 0x6AEF,	0xF45B, 0x703C, 0xF45C, 0x7035, 0xF45D, 0x702F, 0xF45E, 0x7037,
+	0xF45F, 0x7034, 0xF460, 0x7031, 0xF461, 0x7042, 0xF462, 0x7038,	0xF463, 0x703F, 0xF464, 0x703A, 0xF465, 0x7039, 0xF466, 0x7040,
+	0xF467, 0x703B, 0xF468, 0x7033, 0xF469, 0x7041, 0xF46A, 0x7213,	0xF46B, 0x7214, 0xF46C, 0x72A8, 0xF46D, 0x737D, 0xF46E, 0x737C,
+	0xF46F, 0x74BA, 0xF470, 0x76AB, 0xF471, 0x76AA, 0xF472, 0x76BE,	0xF473, 0x76ED, 0xF474, 0x77CC, 0xF475, 0x77CE, 0xF476, 0x77CF,
+	0xF477, 0x77CD, 0xF478, 0x77F2, 0xF479, 0x7925, 0xF47A, 0x7923,	0xF47B, 0x7927, 0xF47C, 0x7928, 0xF47D, 0x7924, 0xF47E, 0x7929,
+	0xF4A1, 0x79B2, 0xF4A2, 0x7A6E, 0xF4A3, 0x7A6C, 0xF4A4, 0x7A6D,	0xF4A5, 0x7AF7, 0xF4A6, 0x7C49, 0xF4A7, 0x7C48, 0xF4A8, 0x7C4A,
+	0xF4A9, 0x7C47, 0xF4AA, 0x7C45, 0xF4AB, 0x7CEE, 0xF4AC, 0x7E7B,	0xF4AD, 0x7E7E, 0xF4AE, 0x7E81, 0xF4AF, 0x7E80, 0xF4B0, 0x7FBA,
+	0xF4B1, 0x7FFF, 0xF4B2, 0x8079, 0xF4B3, 0x81DB, 0xF4B4, 0x81D9,	0xF4B5, 0x820B, 0xF4B6, 0x8268, 0xF4B7, 0x8269, 0xF4B8, 0x8622,
+	0xF4B9, 0x85FF, 0xF4BA, 0x8601, 0xF4BB, 0x85FE, 0xF4BC, 0x861B,	0xF4BD, 0x8600, 0xF4BE, 0x85F6, 0xF4BF, 0x8604, 0xF4C0, 0x8609,
+	0xF4C1, 0x8605, 0xF4C2, 0x860C, 0xF4C3, 0x85FD, 0xF4C4, 0x8819,	0xF4C5, 0x8810, 0xF4C6, 0x8811, 0xF4C7, 0x8817, 0xF4C8, 0x8813,
+	0xF4C9, 0x8816, 0xF4CA, 0x8963, 0xF4CB, 0x8966, 0xF4CC, 0x89B9,	0xF4CD, 0x89F7, 0xF4CE, 0x8B60, 0xF4CF, 0x8B6A, 0xF4D0, 0x8B5D,
+	0xF4D1, 0x8B68, 0xF4D2, 0x8B63, 0xF4D3, 0x8B65, 0xF4D4, 0x8B67,	0xF4D5, 0x8B6D, 0xF4D6, 0x8DAE, 0xF4D7, 0x8E86, 0xF4D8, 0x8E88,
+	0xF4D9, 0x8E84, 0xF4DA, 0x8F59, 0xF4DB, 0x8F56, 0xF4DC, 0x8F57,	0xF4DD, 0x8F55, 0xF4DE, 0x8F58, 0xF4DF, 0x8F5A, 0xF4E0, 0x908D,
+	0xF4E1, 0x9143, 0xF4E2, 0x9141, 0xF4E3, 0x91B7, 0xF4E4, 0x91B5,	0xF4E5, 0x91B2, 0xF4E6, 0x91B3, 0xF4E7, 0x940B, 0xF4E8, 0x9413,
+	0xF4E9, 0x93FB, 0xF4EA, 0x9420, 0xF4EB, 0x940F, 0xF4EC, 0x9414,	0xF4ED, 0x93FE, 0xF4EE, 0x9415, 0xF4EF, 0x9410, 0xF4F0, 0x9428,
+	0xF4F1, 0x9419, 0xF4F2, 0x940D, 0xF4F3, 0x93F5, 0xF4F4, 0x9400,	0xF4F5, 0x93F7, 0xF4F6, 0x9407, 0xF4F7, 0x940E, 0xF4F8, 0x9416,
+	0xF4F9, 0x9412, 0xF4FA, 0x93FA, 0xF4FB, 0x9409, 0xF4FC, 0x93F8,	0xF4FD, 0x940A, 0xF4FE, 0x93FF, 0xF540, 0x93FC, 0xF541, 0x940C,
+	0xF542, 0x93F6, 0xF543, 0x9411, 0xF544, 0x9406, 0xF545, 0x95DE,	0xF546, 0x95E0, 0xF547, 0x95DF, 0xF548, 0x972E, 0xF549, 0x972F,
+	0xF54A, 0x97B9, 0xF54B, 0x97BB, 0xF54C, 0x97FD, 0xF54D, 0x97FE,	0xF54E, 0x9860, 0xF54F, 0x9862, 0xF550, 0x9863, 0xF551, 0x985F,
+	0xF552, 0x98C1, 0xF553, 0x98C2, 0xF554, 0x9950, 0xF555, 0x994E,	0xF556, 0x9959, 0xF557, 0x994C, 0xF558, 0x994B, 0xF559, 0x9953,
+	0xF55A, 0x9A32, 0xF55B, 0x9A34, 0xF55C, 0x9A31, 0xF55D, 0x9A2C,	0xF55E, 0x9A2A, 0xF55F, 0x9A36, 0xF560, 0x9A29, 0xF561, 0x9A2E,
+	0xF562, 0x9A38, 0xF563, 0x9A2D, 0xF564, 0x9AC7, 0xF565, 0x9ACA,	0xF566, 0x9AC6, 0xF567, 0x9B10, 0xF568, 0x9B12, 0xF569, 0x9B11,
+	0xF56A, 0x9C0B, 0xF56B, 0x9C08, 0xF56C, 0x9BF7, 0xF56D, 0x9C05,	0xF56E, 0x9C12, 0xF56F, 0x9BF8, 0xF570, 0x9C40, 0xF571, 0x9C07,
+	0xF572, 0x9C0E, 0xF573, 0x9C06, 0xF574, 0x9C17, 0xF575, 0x9C14,	0xF576, 0x9C09, 0xF577, 0x9D9F, 0xF578, 0x9D99, 0xF579, 0x9DA4,
+	0xF57A, 0x9D9D, 0xF57B, 0x9D92, 0xF57C, 0x9D98, 0xF57D, 0x9D90,	0xF57E, 0x9D9B, 0xF5A1, 0x9DA0, 0xF5A2, 0x9D94, 0xF5A3, 0x9D9C,
+	0xF5A4, 0x9DAA, 0xF5A5, 0x9D97, 0xF5A6, 0x9DA1, 0xF5A7, 0x9D9A,	0xF5A8, 0x9DA2, 0xF5A9, 0x9DA8, 0xF5AA, 0x9D9E, 0xF5AB, 0x9DA3,
+	0xF5AC, 0x9DBF, 0xF5AD, 0x9DA9, 0xF5AE, 0x9D96, 0xF5AF, 0x9DA6,	0xF5B0, 0x9DA7, 0xF5B1, 0x9E99, 0xF5B2, 0x9E9B, 0xF5B3, 0x9E9A,
+	0xF5B4, 0x9EE5, 0xF5B5, 0x9EE4, 0xF5B6, 0x9EE7, 0xF5B7, 0x9EE6,	0xF5B8, 0x9F30, 0xF5B9, 0x9F2E, 0xF5BA, 0x9F5B, 0xF5BB, 0x9F60,
+	0xF5BC, 0x9F5E, 0xF5BD, 0x9F5D, 0xF5BE, 0x9F59, 0xF5BF, 0x9F91,	0xF5C0, 0x513A, 0xF5C1, 0x5139, 0xF5C2, 0x5298, 0xF5C3, 0x5297,
+	0xF5C4, 0x56C3, 0xF5C5, 0x56BD, 0xF5C6, 0x56BE, 0xF5C7, 0x5B48,	0xF5C8, 0x5B47, 0xF5C9, 0x5DCB, 0xF5CA, 0x5DCF, 0xF5CB, 0x5EF1,
+	0xF5CC, 0x61FD, 0xF5CD, 0x651B, 0xF5CE, 0x6B02, 0xF5CF, 0x6AFC,	0xF5D0, 0x6B03, 0xF5D1, 0x6AF8, 0xF5D2, 0x6B00, 0xF5D3, 0x7043,
+	0xF5D4, 0x7044, 0xF5D5, 0x704A, 0xF5D6, 0x7048, 0xF5D7, 0x7049,	0xF5D8, 0x7045, 0xF5D9, 0x7046, 0xF5DA, 0x721D, 0xF5DB, 0x721A,
+	0xF5DC, 0x7219, 0xF5DD, 0x737E, 0xF5DE, 0x7517, 0xF5DF, 0x766A,	0xF5E0, 0x77D0, 0xF5E1, 0x792D, 0xF5E2, 0x7931, 0xF5E3, 0x792F,
+	0xF5E4, 0x7C54, 0xF5E5, 0x7C53, 0xF5E6, 0x7CF2, 0xF5E7, 0x7E8A,	0xF5E8, 0x7E87, 0xF5E9, 0x7E88, 0xF5EA, 0x7E8B, 0xF5EB, 0x7E86,
+	0xF5EC, 0x7E8D, 0xF5ED, 0x7F4D, 0xF5EE, 0x7FBB, 0xF5EF, 0x8030,	0xF5F0, 0x81DD, 0xF5F1, 0x8618, 0xF5F2, 0x862A, 0xF5F3, 0x8626,
+	0xF5F4, 0x861F, 0xF5F5, 0x8623, 0xF5F6, 0x861C, 0xF5F7, 0x8619,	0xF5F8, 0x8627, 0xF5F9, 0x862E, 0xF5FA, 0x8621, 0xF5FB, 0x8620,
+	0xF5FC, 0x8629, 0xF5FD, 0x861E, 0xF5FE, 0x8625, 0xF640, 0x8829,	0xF641, 0x881D, 0xF642, 0x881B, 0xF643, 0x8820, 0xF644, 0x8824,
+	0xF645, 0x881C, 0xF646, 0x882B, 0xF647, 0x884A, 0xF648, 0x896D,	0xF649, 0x8969, 0xF64A, 0x896E, 0xF64B, 0x896B, 0xF64C, 0x89FA,
+	0xF64D, 0x8B79, 0xF64E, 0x8B78, 0xF64F, 0x8B45, 0xF650, 0x8B7A,	0xF651, 0x8B7B, 0xF652, 0x8D10, 0xF653, 0x8D14, 0xF654, 0x8DAF,
+	0xF655, 0x8E8E, 0xF656, 0x8E8C, 0xF657, 0x8F5E, 0xF658, 0x8F5B,	0xF659, 0x8F5D, 0xF65A, 0x9146, 0xF65B, 0x9144, 0xF65C, 0x9145,
+	0xF65D, 0x91B9, 0xF65E, 0x943F, 0xF65F, 0x943B, 0xF660, 0x9436,	0xF661, 0x9429, 0xF662, 0x943D, 0xF663, 0x943C, 0xF664, 0x9430,
+	0xF665, 0x9439, 0xF666, 0x942A, 0xF667, 0x9437, 0xF668, 0x942C,	0xF669, 0x9440, 0xF66A, 0x9431, 0xF66B, 0x95E5, 0xF66C, 0x95E4,
+	0xF66D, 0x95E3, 0xF66E, 0x9735, 0xF66F, 0x973A, 0xF670, 0x97BF,	0xF671, 0x97E1, 0xF672, 0x9864, 0xF673, 0x98C9, 0xF674, 0x98C6,
+	0xF675, 0x98C0, 0xF676, 0x9958, 0xF677, 0x9956, 0xF678, 0x9A39,	0xF679, 0x9A3D, 0xF67A, 0x9A46, 0xF67B, 0x9A44, 0xF67C, 0x9A42,
+	0xF67D, 0x9A41, 0xF67E, 0x9A3A, 0xF6A1, 0x9A3F, 0xF6A2, 0x9ACD,	0xF6A3, 0x9B15, 0xF6A4, 0x9B17, 0xF6A5, 0x9B18, 0xF6A6, 0x9B16,
+	0xF6A7, 0x9B3A, 0xF6A8, 0x9B52, 0xF6A9, 0x9C2B, 0xF6AA, 0x9C1D,	0xF6AB, 0x9C1C, 0xF6AC, 0x9C2C, 0xF6AD, 0x9C23, 0xF6AE, 0x9C28,
+	0xF6AF, 0x9C29, 0xF6B0, 0x9C24, 0xF6B1, 0x9C21, 0xF6B2, 0x9DB7,	0xF6B3, 0x9DB6, 0xF6B4, 0x9DBC, 0xF6B5, 0x9DC1, 0xF6B6, 0x9DC7,
+	0xF6B7, 0x9DCA, 0xF6B8, 0x9DCF, 0xF6B9, 0x9DBE, 0xF6BA, 0x9DC5,	0xF6BB, 0x9DC3, 0xF6BC, 0x9DBB, 0xF6BD, 0x9DB5, 0xF6BE, 0x9DCE,
+	0xF6BF, 0x9DB9, 0xF6C0, 0x9DBA, 0xF6C1, 0x9DAC, 0xF6C2, 0x9DC8,	0xF6C3, 0x9DB1, 0xF6C4, 0x9DAD, 0xF6C5, 0x9DCC, 0xF6C6, 0x9DB3,
+	0xF6C7, 0x9DCD, 0xF6C8, 0x9DB2, 0xF6C9, 0x9E7A, 0xF6CA, 0x9E9C,	0xF6CB, 0x9EEB, 0xF6CC, 0x9EEE, 0xF6CD, 0x9EED, 0xF6CE, 0x9F1B,
+	0xF6CF, 0x9F18, 0xF6D0, 0x9F1A, 0xF6D1, 0x9F31, 0xF6D2, 0x9F4E,	0xF6D3, 0x9F65, 0xF6D4, 0x9F64, 0xF6D5, 0x9F92, 0xF6D6, 0x4EB9,
+	0xF6D7, 0x56C6, 0xF6D8, 0x56C5, 0xF6D9, 0x56CB, 0xF6DA, 0x5971,	0xF6DB, 0x5B4B, 0xF6DC, 0x5B4C, 0xF6DD, 0x5DD5, 0xF6DE, 0x5DD1,
+	0xF6DF, 0x5EF2, 0xF6E0, 0x6521, 0xF6E1, 0x6520, 0xF6E2, 0x6526,	0xF6E3, 0x6522, 0xF6E4, 0x6B0B, 0xF6E5, 0x6B08, 0xF6E6, 0x6B09,
+	0xF6E7, 0x6C0D, 0xF6E8, 0x7055, 0xF6E9, 0x7056, 0xF6EA, 0x7057,	0xF6EB, 0x7052, 0xF6EC, 0x721E, 0xF6ED, 0x721F, 0xF6EE, 0x72A9,
+	0xF6EF, 0x737F, 0xF6F0, 0x74D8, 0xF6F1, 0x74D5, 0xF6F2, 0x74D9,	0xF6F3, 0x74D7, 0xF6F4, 0x766D, 0xF6F5, 0x76AD, 0xF6F6, 0x7935,
+	0xF6F7, 0x79B4, 0xF6F8, 0x7A70, 0xF6F9, 0x7A71, 0xF6FA, 0x7C57,	0xF6FB, 0x7C5C, 0xF6FC, 0x7C59, 0xF6FD, 0x7C5B, 0xF6FE, 0x7C5A,
+	0xF740, 0x7CF4, 0xF741, 0x7CF1, 0xF742, 0x7E91, 0xF743, 0x7F4F,	0xF744, 0x7F87, 0xF745, 0x81DE, 0xF746, 0x826B, 0xF747, 0x8634,
+	0xF748, 0x8635, 0xF749, 0x8633, 0xF74A, 0x862C, 0xF74B, 0x8632,	0xF74C, 0x8636, 0xF74D, 0x882C, 0xF74E, 0x8828, 0xF74F, 0x8826,
+	0xF750, 0x882A, 0xF751, 0x8825, 0xF752, 0x8971, 0xF753, 0x89BF,	0xF754, 0x89BE, 0xF755, 0x89FB, 0xF756, 0x8B7E, 0xF757, 0x8B84,
+	0xF758, 0x8B82, 0xF759, 0x8B86, 0xF75A, 0x8B85, 0xF75B, 0x8B7F,	0xF75C, 0x8D15, 0xF75D, 0x8E95, 0xF75E, 0x8E94, 0xF75F, 0x8E9A,
+	0xF760, 0x8E92, 0xF761, 0x8E90, 0xF762, 0x8E96, 0xF763, 0x8E97,	0xF764, 0x8F60, 0xF765, 0x8F62, 0xF766, 0x9147, 0xF767, 0x944C,
+	0xF768, 0x9450, 0xF769, 0x944A, 0xF76A, 0x944B, 0xF76B, 0x944F,	0xF76C, 0x9447, 0xF76D, 0x9445, 0xF76E, 0x9448, 0xF76F, 0x9449,
+	0xF770, 0x9446, 0xF771, 0x973F, 0xF772, 0x97E3, 0xF773, 0x986A,	0xF774, 0x9869, 0xF775, 0x98CB, 0xF776, 0x9954, 0xF777, 0x995B,
+	0xF778, 0x9A4E, 0xF779, 0x9A53, 0xF77A, 0x9A54, 0xF77B, 0x9A4C,	0xF77C, 0x9A4F, 0xF77D, 0x9A48, 0xF77E, 0x9A4A, 0xF7A1, 0x9A49,
+	0xF7A2, 0x9A52, 0xF7A3, 0x9A50, 0xF7A4, 0x9AD0, 0xF7A5, 0x9B19,	0xF7A6, 0x9B2B, 0xF7A7, 0x9B3B, 0xF7A8, 0x9B56, 0xF7A9, 0x9B55,
+	0xF7AA, 0x9C46, 0xF7AB, 0x9C48, 0xF7AC, 0x9C3F, 0xF7AD, 0x9C44,	0xF7AE, 0x9C39, 0xF7AF, 0x9C33, 0xF7B0, 0x9C41, 0xF7B1, 0x9C3C,
+	0xF7B2, 0x9C37, 0xF7B3, 0x9C34, 0xF7B4, 0x9C32, 0xF7B5, 0x9C3D,	0xF7B6, 0x9C36, 0xF7B7, 0x9DDB, 0xF7B8, 0x9DD2, 0xF7B9, 0x9DDE,
+	0xF7BA, 0x9DDA, 0xF7BB, 0x9DCB, 0xF7BC, 0x9DD0, 0xF7BD, 0x9DDC,	0xF7BE, 0x9DD1, 0xF7BF, 0x9DDF, 0xF7C0, 0x9DE9, 0xF7C1, 0x9DD9,
+	0xF7C2, 0x9DD8, 0xF7C3, 0x9DD6, 0xF7C4, 0x9DF5, 0xF7C5, 0x9DD5,	0xF7C6, 0x9DDD, 0xF7C7, 0x9EB6, 0xF7C8, 0x9EF0, 0xF7C9, 0x9F35,
+	0xF7CA, 0x9F33, 0xF7CB, 0x9F32, 0xF7CC, 0x9F42, 0xF7CD, 0x9F6B,	0xF7CE, 0x9F95, 0xF7CF, 0x9FA2, 0xF7D0, 0x513D, 0xF7D1, 0x5299,
+	0xF7D2, 0x58E8, 0xF7D3, 0x58E7, 0xF7D4, 0x5972, 0xF7D5, 0x5B4D,	0xF7D6, 0x5DD8, 0xF7D7, 0x882F, 0xF7D8, 0x5F4F, 0xF7D9, 0x6201,
+	0xF7DA, 0x6203, 0xF7DB, 0x6204, 0xF7DC, 0x6529, 0xF7DD, 0x6525,	0xF7DE, 0x6596, 0xF7DF, 0x66EB, 0xF7E0, 0x6B11, 0xF7E1, 0x6B12,
+	0xF7E2, 0x6B0F, 0xF7E3, 0x6BCA, 0xF7E4, 0x705B, 0xF7E5, 0x705A,	0xF7E6, 0x7222, 0xF7E7, 0x7382, 0xF7E8, 0x7381, 0xF7E9, 0x7383,
+	0xF7EA, 0x7670, 0xF7EB, 0x77D4, 0xF7EC, 0x7C67, 0xF7ED, 0x7C66,	0xF7EE, 0x7E95, 0xF7EF, 0x826C, 0xF7F0, 0x863A, 0xF7F1, 0x8640,
+	0xF7F2, 0x8639, 0xF7F3, 0x863C, 0xF7F4, 0x8631, 0xF7F5, 0x863B,	0xF7F6, 0x863E, 0xF7F7, 0x8830, 0xF7F8, 0x8832, 0xF7F9, 0x882E,
+	0xF7FA, 0x8833, 0xF7FB, 0x8976, 0xF7FC, 0x8974, 0xF7FD, 0x8973,	0xF7FE, 0x89FE, 0xF840, 0x8B8C, 0xF841, 0x8B8E, 0xF842, 0x8B8B,
+	0xF843, 0x8B88, 0xF844, 0x8C45, 0xF845, 0x8D19, 0xF846, 0x8E98,	0xF847, 0x8F64, 0xF848, 0x8F63, 0xF849, 0x91BC, 0xF84A, 0x9462,
+	0xF84B, 0x9455, 0xF84C, 0x945D, 0xF84D, 0x9457, 0xF84E, 0x945E,	0xF84F, 0x97C4, 0xF850, 0x97C5, 0xF851, 0x9800, 0xF852, 0x9A56,
+	0xF853, 0x9A59, 0xF854, 0x9B1E, 0xF855, 0x9B1F, 0xF856, 0x9B20,	0xF857, 0x9C52, 0xF858, 0x9C58, 0xF859, 0x9C50, 0xF85A, 0x9C4A,
+	0xF85B, 0x9C4D, 0xF85C, 0x9C4B, 0xF85D, 0x9C55, 0xF85E, 0x9C59,	0xF85F, 0x9C4C, 0xF860, 0x9C4E, 0xF861, 0x9DFB, 0xF862, 0x9DF7,
+	0xF863, 0x9DEF, 0xF864, 0x9DE3, 0xF865, 0x9DEB, 0xF866, 0x9DF8,	0xF867, 0x9DE4, 0xF868, 0x9DF6, 0xF869, 0x9DE1, 0xF86A, 0x9DEE,
+	0xF86B, 0x9DE6, 0xF86C, 0x9DF2, 0xF86D, 0x9DF0, 0xF86E, 0x9DE2,	0xF86F, 0x9DEC, 0xF870, 0x9DF4, 0xF871, 0x9DF3, 0xF872, 0x9DE8,
+	0xF873, 0x9DED, 0xF874, 0x9EC2, 0xF875, 0x9ED0, 0xF876, 0x9EF2,	0xF877, 0x9EF3, 0xF878, 0x9F06, 0xF879, 0x9F1C, 0xF87A, 0x9F38,
+	0xF87B, 0x9F37, 0xF87C, 0x9F36, 0xF87D, 0x9F43, 0xF87E, 0x9F4F,	0xF8A1, 0x9F71, 0xF8A2, 0x9F70, 0xF8A3, 0x9F6E, 0xF8A4, 0x9F6F,
+	0xF8A5, 0x56D3, 0xF8A6, 0x56CD, 0xF8A7, 0x5B4E, 0xF8A8, 0x5C6D,	0xF8A9, 0x652D, 0xF8AA, 0x66ED, 0xF8AB, 0x66EE, 0xF8AC, 0x6B13,
+	0xF8AD, 0x705F, 0xF8AE, 0x7061, 0xF8AF, 0x705D, 0xF8B0, 0x7060,	0xF8B1, 0x7223, 0xF8B2, 0x74DB, 0xF8B3, 0x74E5, 0xF8B4, 0x77D5,
+	0xF8B5, 0x7938, 0xF8B6, 0x79B7, 0xF8B7, 0x79B6, 0xF8B8, 0x7C6A,	0xF8B9, 0x7E97, 0xF8BA, 0x7F89, 0xF8BB, 0x826D, 0xF8BC, 0x8643,
+	0xF8BD, 0x8838, 0xF8BE, 0x8837, 0xF8BF, 0x8835, 0xF8C0, 0x884B,	0xF8C1, 0x8B94, 0xF8C2, 0x8B95, 0xF8C3, 0x8E9E, 0xF8C4, 0x8E9F,
+	0xF8C5, 0x8EA0, 0xF8C6, 0x8E9D, 0xF8C7, 0x91BE, 0xF8C8, 0x91BD,	0xF8C9, 0x91C2, 0xF8CA, 0x946B, 0xF8CB, 0x9468, 0xF8CC, 0x9469,
+	0xF8CD, 0x96E5, 0xF8CE, 0x9746, 0xF8CF, 0x9743, 0xF8D0, 0x9747,	0xF8D1, 0x97C7, 0xF8D2, 0x97E5, 0xF8D3, 0x9A5E, 0xF8D4, 0x9AD5,
+	0xF8D5, 0x9B59, 0xF8D6, 0x9C63, 0xF8D7, 0x9C67, 0xF8D8, 0x9C66,	0xF8D9, 0x9C62, 0xF8DA, 0x9C5E, 0xF8DB, 0x9C60, 0xF8DC, 0x9E02,
+	0xF8DD, 0x9DFE, 0xF8DE, 0x9E07, 0xF8DF, 0x9E03, 0xF8E0, 0x9E06,	0xF8E1, 0x9E05, 0xF8E2, 0x9E00, 0xF8E3, 0x9E01, 0xF8E4, 0x9E09,
+	0xF8E5, 0x9DFF, 0xF8E6, 0x9DFD, 0xF8E7, 0x9E04, 0xF8E8, 0x9EA0,	0xF8E9, 0x9F1E, 0xF8EA, 0x9F46, 0xF8EB, 0x9F74, 0xF8EC, 0x9F75,
+	0xF8ED, 0x9F76, 0xF8EE, 0x56D4, 0xF8EF, 0x652E, 0xF8F0, 0x65B8,	0xF8F1, 0x6B18, 0xF8F2, 0x6B19, 0xF8F3, 0x6B17, 0xF8F4, 0x6B1A,
+	0xF8F5, 0x7062, 0xF8F6, 0x7226, 0xF8F7, 0x72AA, 0xF8F8, 0x77D8,	0xF8F9, 0x77D9, 0xF8FA, 0x7939, 0xF8FB, 0x7C69, 0xF8FC, 0x7C6B,
+	0xF8FD, 0x7CF6, 0xF8FE, 0x7E9A, 0xF940, 0x7E98, 0xF941, 0x7E9B,	0xF942, 0x7E99, 0xF943, 0x81E0, 0xF944, 0x81E1, 0xF945, 0x8646,
+	0xF946, 0x8647, 0xF947, 0x8648, 0xF948, 0x8979, 0xF949, 0x897A,	0xF94A, 0x897C, 0xF94B, 0x897B, 0xF94C, 0x89FF, 0xF94D, 0x8B98,
+	0xF94E, 0x8B99, 0xF94F, 0x8EA5, 0xF950, 0x8EA4, 0xF951, 0x8EA3,	0xF952, 0x946E, 0xF953, 0x946D, 0xF954, 0x946F, 0xF955, 0x9471,
+	0xF956, 0x9473, 0xF957, 0x9749, 0xF958, 0x9872, 0xF959, 0x995F,	0xF95A, 0x9C68, 0xF95B, 0x9C6E, 0xF95C, 0x9C6D, 0xF95D, 0x9E0B,
+	0xF95E, 0x9E0D, 0xF95F, 0x9E10, 0xF960, 0x9E0F, 0xF961, 0x9E12,	0xF962, 0x9E11, 0xF963, 0x9EA1, 0xF964, 0x9EF5, 0xF965, 0x9F09,
+	0xF966, 0x9F47, 0xF967, 0x9F78, 0xF968, 0x9F7B, 0xF969, 0x9F7A,	0xF96A, 0x9F79, 0xF96B, 0x571E, 0xF96C, 0x7066, 0xF96D, 0x7C6F,
+	0xF96E, 0x883C, 0xF96F, 0x8DB2, 0xF970, 0x8EA6, 0xF971, 0x91C3,	0xF972, 0x9474, 0xF973, 0x9478, 0xF974, 0x9476, 0xF975, 0x9475,
+	0xF976, 0x9A60, 0xF977, 0x9C74, 0xF978, 0x9C73, 0xF979, 0x9C71,	0xF97A, 0x9C75, 0xF97B, 0x9E14, 0xF97C, 0x9E13, 0xF97D, 0x9EF6,
+	0xF97E, 0x9F0A, 0xF9A1, 0x9FA4, 0xF9A2, 0x7068, 0xF9A3, 0x7065,	0xF9A4, 0x7CF7, 0xF9A5, 0x866A, 0xF9A6, 0x883E, 0xF9A7, 0x883D,
+	0xF9A8, 0x883F, 0xF9A9, 0x8B9E, 0xF9AA, 0x8C9C, 0xF9AB, 0x8EA9,	0xF9AC, 0x8EC9, 0xF9AD, 0x974B, 0xF9AE, 0x9873, 0xF9AF, 0x9874,
+	0xF9B0, 0x98CC, 0xF9B1, 0x9961, 0xF9B2, 0x99AB, 0xF9B3, 0x9A64,	0xF9B4, 0x9A66, 0xF9B5, 0x9A67, 0xF9B6, 0x9B24, 0xF9B7, 0x9E15,
+	0xF9B8, 0x9E17, 0xF9B9, 0x9F48, 0xF9BA, 0x6207, 0xF9BB, 0x6B1E,	0xF9BC, 0x7227, 0xF9BD, 0x864C, 0xF9BE, 0x8EA8, 0xF9BF, 0x9482,
+	0xF9C0, 0x9480, 0xF9C1, 0x9481, 0xF9C2, 0x9A69, 0xF9C3, 0x9A68,	0xF9C4, 0x9B2E, 0xF9C5, 0x9E19, 0xF9C6, 0x7229, 0xF9C7, 0x864B,
+	0xF9C8, 0x8B9F, 0xF9C9, 0x9483, 0xF9CA, 0x9C79, 0xF9CB, 0x9EB7,	0xF9CC, 0x7675, 0xF9CD, 0x9A6B, 0xF9CE, 0x9C7A, 0xF9CF, 0x9E1D,
+	0xF9D0, 0x7069, 0xF9D1, 0x706A, 0xF9D2, 0x9EA4, 0xF9D3, 0x9F7E,	0xF9D4, 0x9F49, 0xF9D5, 0x9F98, 0xF9D6, 0x7881, 0xF9D7, 0x92B9,
+	0xF9D8, 0x88CF, 0xF9D9, 0x58BB, 0xF9DA, 0x6052, 0xF9DB, 0x7CA7,	0xF9DC, 0x5AFA, 0xF9DD, 0x2554, 0xF9DE, 0x2566, 0xF9DF, 0x2557,
+	0xF9E0, 0x2560, 0xF9E1, 0x256C, 0xF9E2, 0x2563, 0xF9E3, 0x255A,	0xF9E4, 0x2569, 0xF9E5, 0x255D, 0xF9E6, 0x2552, 0xF9E7, 0x2564,
+	0xF9E8, 0x2555, 0xF9E9, 0x255E, 0xF9EA, 0x256A, 0xF9EB, 0x2561,	0xF9EC, 0x2558, 0xF9ED, 0x2567, 0xF9EE, 0x255B, 0xF9EF, 0x2553,
+	0xF9F0, 0x2565, 0xF9F1, 0x2556, 0xF9F2, 0x255F, 0xF9F3, 0x256B,	0xF9F4, 0x2562, 0xF9F5, 0x2559, 0xF9F6, 0x2568, 0xF9F7, 0x255C,
+	0xF9F8, 0x2551, 0xF9F9, 0x2550, 0xF9FA, 0x256D, 0xF9FB, 0x256E,	0xF9FC, 0x2570, 0xF9FD, 0x256F, 0xF9FE, 0x2593, 0, 0
+};
+#endif
+
+#if FF_CODE_PAGE == 437 || FF_CODE_PAGE == 0
+static const WCHAR uc437[] = {	/*  CP437(U.S.) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 720 || FF_CODE_PAGE == 0
+static const WCHAR uc720[] = {	/*  CP720(Arabic) to Unicode conversion table */
+	0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
+	0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
+	0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
+	0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 737 || FF_CODE_PAGE == 0
+static const WCHAR uc737[] = {	/*  CP737(Greek) to Unicode conversion table */
+	0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
+	0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
+	0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
+	0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 771 || FF_CODE_PAGE == 0
+static const WCHAR uc771[] = {	/*  CP771(KBL) to Unicode conversion table */
+	0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+	0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+	0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x0104, 0x0105, 0x010C, 0x010D,
+	0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+	0x0118, 0x0119, 0x0116, 0x0117, 0x012E, 0x012F, 0x0160, 0x0161, 0x0172, 0x0173, 0x016A, 0x016B, 0x017D, 0x017E, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 775 || FF_CODE_PAGE == 0
+static const WCHAR uc775[] = {	/*  CP775(Baltic) to Unicode conversion table */
+	0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
+	0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
+	0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
+	0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 850 || FF_CODE_PAGE == 0
+static const WCHAR uc850[] = {	/*  CP850(Latin 1) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+	0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 852 || FF_CODE_PAGE == 0
+static const WCHAR uc852[] = {	/*  CP852(Latin 2) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
+	0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
+	0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
+	0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 855 || FF_CODE_PAGE == 0
+static const WCHAR uc855[] = {	/*  CP855(Cyrillic) to Unicode conversion table */
+	0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
+	0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
+	0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
+	0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
+	0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 857 || FF_CODE_PAGE == 0
+static const WCHAR uc857[] = {	/*  CP857(Turkish) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+	0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
+	0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 860 || FF_CODE_PAGE == 0
+static const WCHAR uc860[] = {	/*  CP860(Portuguese) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E3, 0x00E0, 0x00C1, 0x00E7, 0x00EA, 0x00CA, 0x00E8, 0x00CD, 0x00D4, 0x00EC, 0x00C3, 0x00C2,
+	0x00C9, 0x00C0, 0x00C8, 0x00F4, 0x00F5, 0x00F2, 0x00DA, 0x00F9, 0x00CC, 0x00D5, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x20A7, 0x00D3,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x00D2, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 861 || FF_CODE_PAGE == 0
+static const WCHAR uc861[] = {	/*  CP861(Icelandic) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00D0, 0x00F0, 0x00DE, 0x00C4, 0x00C5,
+	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00FE, 0x00FB, 0x00DD, 0x00FD, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00C1, 0x00CD, 0x00D3, 0x00DA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 862 || FF_CODE_PAGE == 0
+static const WCHAR uc862[] = {	/*  CP862(Hebrew) to Unicode conversion table */
+	0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+	0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 863 || FF_CODE_PAGE == 0
+static const WCHAR uc863[] = {	/*  CP863(Canadian French) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00C2, 0x00E0, 0x00B6, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x2017, 0x00C0,
+	0x00C9, 0x00C8, 0x00CA, 0x00F4, 0x00CB, 0x00CF, 0x00FB, 0x00F9, 0x00A4, 0x00D4, 0x00DC, 0x00A2, 0x00A3, 0x00D9, 0x00DB, 0x0192,
+	0x00A6, 0x00B4, 0x00F3, 0x00FA, 0x00A8, 0x00BB, 0x00B3, 0x00AF, 0x00CE, 0x3210, 0x00AC, 0x00BD, 0x00BC, 0x00BE, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2219,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 864 || FF_CODE_PAGE == 0
+static const WCHAR uc864[] = {	/*  CP864(Arabic) to Unicode conversion table */
+	0x00B0, 0x00B7, 0x2219, 0x221A, 0x2592, 0x2500, 0x2502, 0x253C, 0x2524, 0x252C, 0x251C, 0x2534, 0x2510, 0x250C, 0x2514, 0x2518,
+	0x03B2, 0x221E, 0x03C6, 0x00B1, 0x00BD, 0x00BC, 0x2248, 0x00AB, 0x00BB, 0xFEF7, 0xFEF8, 0x0000, 0x0000, 0xFEFB, 0xFEFC, 0x0000,
+	0x00A0, 0x00AD, 0xFE82, 0x00A3, 0x00A4, 0xFE84, 0x0000, 0x20AC, 0xFE8E, 0xFE8F, 0xFE95, 0xFE99, 0x060C, 0xFE9D, 0xFEA1, 0xFEA5,
+	0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667, 0x0668, 0x0669, 0xFED1, 0x061B, 0xFEB1, 0xFEB5, 0xFEB9, 0x061F,
+	0x00A2, 0xFE80, 0xFE81, 0xFE83, 0xFE85, 0xFECA, 0xFE8B, 0xFE8D, 0xFE91, 0xFE93, 0xFE97, 0xFE9B, 0xFE9F, 0xFEA3, 0xFEA7, 0xFEA9,
+	0xFEAB, 0xFEAD, 0xFEAF, 0xFEB3, 0xFEB7, 0xFEBB, 0xFEBF, 0xFEC1, 0xFEC5, 0xFECB, 0xFECF, 0x00A6, 0x00AC, 0x00F7, 0x00D7, 0xFEC9,
+	0x0640, 0xFED3, 0xFED7, 0xFEDB, 0xFEDF, 0xFEE3, 0xFEE7, 0xFEEB, 0xFEED, 0xFEEF, 0xFEF3, 0xFEBD, 0xFECC, 0xFECE, 0xFECD, 0xFEE1,
+	0xFE7D, 0x0651, 0xFEE5, 0xFEE9, 0xFEEC, 0xFEF0, 0xFEF2, 0xFED0, 0xFED5, 0xFEF5, 0xFEF6, 0xFEDD, 0xFED9, 0xFEF1, 0x25A0, 0x0000
+};
+#endif
+#if FF_CODE_PAGE == 865 || FF_CODE_PAGE == 0
+static const WCHAR uc865[] = {	/*  CP865(Nordic) to Unicode conversion table */
+	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+	0x00C5, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x20A7, 0x0192,
+	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00A4,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x2558, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 866 || FF_CODE_PAGE == 0
+static const WCHAR uc866[] = {	/*  CP866(Russian) to Unicode conversion table */
+	0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+	0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+	0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+	0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+	0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
+};
+#endif
+#if FF_CODE_PAGE == 869 || FF_CODE_PAGE == 0
+static const WCHAR uc869[] = {	/*  CP869(Greek 2) to Unicode conversion table */
+	0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x00B7, 0x0386, 0x00B7, 0x00B7, 0x00AC, 0x00A6, 0x2018, 0x2019, 0x0388, 0x2015, 0x0389,
+	0x038A, 0x03AA, 0x038C, 0x00B7, 0x00B7, 0x038E, 0x03AB, 0x00A9, 0x038F, 0x00B2, 0x00B3, 0x03AC, 0x00A3, 0x03AD, 0x03AE, 0x03AF,
+	0x03CA, 0x0390, 0x03CC, 0x03CD, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x00BD, 0x0398, 0x0399, 0x00AB, 0x00BB,
+	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x039A, 0x039B, 0x039C, 0x039D, 0x2563, 0x2551, 0x2557, 0x255D, 0x039E, 0x039F, 0x2510,
+	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0A30, 0x03A1, 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x03A3,
+	0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, 0x03B1, 0x03B2, 0x03B3, 0x2518, 0x250C, 0x2588, 0x2584, 0x03B4, 0x03B5, 0x2580,
+	0x03B6, 0x03B7, 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x0384,
+	0x00AD, 0x00B1, 0x03C5, 0x03C6, 0x03C7, 0x00A7, 0x03C8, 0x0385, 0x00B0, 0x00A8, 0x03C9, 0x03CB, 0x03B0, 0x03CE, 0x25A0, 0x00A0
+};
+#endif
+
+
+
+
+/*------------------------------------------------------------------------*/
+/* OEM <==> Unicode Conversions for Static Code Page Configuration with   */
+/* SBCS Fixed Code Page                                                   */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE != 0 && FF_CODE_PAGE < 900
+WCHAR ff_uni2oem (	/* Returns OEM code character, zero on error */
+	DWORD	uni,	/* UTF-16 encoded character to be converted */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	WCHAR c = 0;
+	const WCHAR* p = CVTBL(uc, FF_CODE_PAGE);
+
+
+	if (uni < 0x80) {	/* ASCII? */
+		c = (WCHAR)uni;
+
+	} else {			/* Non-ASCII */
+		if (uni < 0x10000 && cp == FF_CODE_PAGE) {	/* Is it in BMP and valid code page? */
+			for (c = 0; c < 0x80 && uni != p[c]; c++) ;
+			c = (c + 0x80) & 0xFF;
+		}
+	}
+
+	return c;
+}
+
+WCHAR ff_oem2uni (	/* Returns Unicode character in UTF-16, zero on error */
+	WCHAR	oem,	/* OEM code to be converted */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	WCHAR c = 0;
+	const WCHAR* p = CVTBL(uc, FF_CODE_PAGE);
+
+
+	if (oem < 0x80) {	/* ASCII? */
+		c = oem;
+
+	} else {			/* Extended char */
+		if (cp == FF_CODE_PAGE) {	/* Is it a valid code page? */
+			if (oem < 0x100) c = p[oem - 0x80];
+		}
+	}
+
+	return c;
+}
+
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* OEM <==> Unicode Conversions for Static Code Page Configuration with   */
+/* DBCS Fixed Code Page                                                   */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE >= 900
+WCHAR ff_uni2oem (	/* Returns OEM code character, zero on error */
+	DWORD	uni,	/* UTF-16 encoded character to be converted */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	const WCHAR* p;
+	WCHAR c = 0, uc;
+	UINT i = 0, n, li, hi;
+
+
+	if (uni < 0x80) {	/* ASCII? */
+		c = (WCHAR)uni;
+
+	} else {			/* Non-ASCII */
+		if (uni < 0x10000 && cp == FF_CODE_PAGE) {	/* Is it in BMP and valid code page? */
+			uc = (WCHAR)uni;
+			p = CVTBL(uni2oem, FF_CODE_PAGE);
+			hi = sizeof CVTBL(uni2oem, FF_CODE_PAGE) / 4 - 1;
+			li = 0;
+			for (n = 16; n; n--) {
+				i = li + (hi - li) / 2;
+				if (uc == p[i * 2]) break;
+				if (uc > p[i * 2]) {
+					li = i;
+				} else {
+					hi = i;
+				}
+			}
+			if (n != 0) c = p[i * 2 + 1];
+		}
+	}
+
+	return c;
+}
+
+
+WCHAR ff_oem2uni (	/* Returns Unicode character in UTF-16, zero on error */
+	WCHAR	oem,	/* OEM code to be converted */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	const WCHAR* p;
+	WCHAR c = 0;
+	UINT i = 0, n, li, hi;
+
+
+	if (oem < 0x80) {	/* ASCII? */
+		c = oem;
+
+	} else {			/* Extended char */
+		if (cp == FF_CODE_PAGE) {	/* Is it valid code page? */
+			p = CVTBL(oem2uni, FF_CODE_PAGE);
+			hi = sizeof CVTBL(oem2uni, FF_CODE_PAGE) / 4 - 1;
+			li = 0;
+			for (n = 16; n; n--) {
+				i = li + (hi - li) / 2;
+				if (oem == p[i * 2]) break;
+				if (oem > p[i * 2]) {
+					li = i;
+				} else {
+					hi = i;
+				}
+			}
+			if (n != 0) c = p[i * 2 + 1];
+		}
+	}
+
+	return c;
+}
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* OEM <==> Unicode Conversions for Dynamic Code Page Configuration       */
+/*------------------------------------------------------------------------*/
+
+#if FF_CODE_PAGE == 0
+
+static const WORD cp_code[]          = {  437,   720,   737,   771,   775,   850,   852,   855,   857,   860,   861,   862,   863,   864,   865,   866,   869, 0};
+static const WCHAR* const cp_table[] = {uc437, uc720, uc737, uc771, uc775, uc850, uc852, uc855, uc857, uc860, uc861, uc862, uc863, uc864, uc865, uc866, uc869, 0};
+
+
+WCHAR ff_uni2oem (	/* Returns OEM code character, zero on error */
+	DWORD	uni,	/* UTF-16 encoded character to be converted */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	const WCHAR* p;
+	WCHAR c = 0, uc;
+	UINT i, n, li, hi;
+
+
+	if (uni < 0x80) {	/* ASCII? */
+		c = (WCHAR)uni;
+
+	} else {			/* Non-ASCII */
+		if (uni < 0x10000) { /* Is it in BMP? */
+			uc = (WCHAR)uni;
+			p = 0;
+			if (cp < 900) {	/* SBCS */
+				for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ;		/* Get conversion table */
+				p = cp_table[i];
+				if (p) {	/* Is it valid code page ? */
+					for (c = 0; c < 0x80 && uc != p[c]; c++) ;	/* Find OEM code in the table */
+					c = (c + 0x80) & 0xFF;
+				}
+			} else {	/* DBCS */
+				switch (cp) {	/* Get conversion table */
+				case 932 : p = uni2oem932; hi = sizeof uni2oem932 / 4 - 1; break;
+				case 936 : p = uni2oem936; hi = sizeof uni2oem936 / 4 - 1; break;
+				case 949 : p = uni2oem949; hi = sizeof uni2oem949 / 4 - 1; break;
+				case 950 : p = uni2oem950; hi = sizeof uni2oem950 / 4 - 1; break;
+				}
+				if (p) {	/* Is it valid code page? */
+					li = 0;
+					for (n = 16; n; n--) {	/* Find OEM code */
+						i = li + (hi - li) / 2;
+						if (uc == p[i * 2]) break;
+						if (uc > p[i * 2]) {
+							li = i;
+						} else {
+							hi = i;
+						}
+					}
+					if (n != 0) c = p[i * 2 + 1];
+				}
+			}
+		}
+	}
+
+	return c;
+}
+
+
+WCHAR ff_oem2uni (	/* Returns Unicode character in UTF-16, zero on error */
+	WCHAR	oem,	/* OEM code to be converted (DBC if >=0x100) */
+	WORD	cp		/* Code page for the conversion */
+)
+{
+	const WCHAR* p;
+	WCHAR c = 0;
+	UINT i, n, li, hi;
+
+
+	if (oem < 0x80) {	/* ASCII? */
+		c = oem;
+
+	} else {			/* Extended char */
+		p = 0;
+		if (cp < 900) {	/* SBCS */
+			for (i = 0; cp_code[i] != 0 && cp_code[i] != cp; i++) ;		/* Get table */
+			p = cp_table[i];
+			if (p) {	/* Is it a valid CP ? */
+				if (oem < 0x100) c = p[oem - 0x80];
+			}
+		} else {	/* DBCS */
+			switch (cp) {
+			case 932 : p = oem2uni932; hi = sizeof oem2uni932 / 4 - 1; break;
+			case 936 : p = oem2uni936; hi = sizeof oem2uni936 / 4 - 1; break;
+			case 949 : p = oem2uni949; hi = sizeof oem2uni949 / 4 - 1; break;
+			case 950 : p = oem2uni950; hi = sizeof oem2uni950 / 4 - 1; break;
+			}
+			if (p) {
+				li = 0;
+				for (n = 16; n; n--) {
+					i = li + (hi - li) / 2;
+					if (oem == p[i * 2]) break;
+					if (oem > p[i * 2]) {
+						li = i;
+					} else {
+						hi = i;
+					}
+				}
+				if (n != 0) c = p[i * 2 + 1];
+			}
+		}
+	}
+
+	return c;
+}
+#endif
+
+
+
+/*------------------------------------------------------------------------*/
+/* Unicode Up-case Conversion                                             */
+/*------------------------------------------------------------------------*/
+
+DWORD ff_wtoupper (	/* Returns up-converted code point */
+	DWORD uni		/* Unicode code point to be up-converted */
+)
+{
+	const WORD* p;
+	WORD uc, bc, nc, cmd;
+	static const WORD cvt1[] = {	/* Compressed up conversion table for U+0000 - U+0FFF */
+		/* Basic Latin */
+		0x0061,0x031A,
+		/* Latin-1 Supplement */
+		0x00E0,0x0317,
+		0x00F8,0x0307,
+		0x00FF,0x0001,0x0178,
+		/* Latin Extended-A */
+		0x0100,0x0130,
+		0x0132,0x0106,
+		0x0139,0x0110,
+		0x014A,0x012E,
+		0x0179,0x0106,
+		/* Latin Extended-B */
+		0x0180,0x004D,0x0243,0x0181,0x0182,0x0182,0x0184,0x0184,0x0186,0x0187,0x0187,0x0189,0x018A,0x018B,0x018B,0x018D,0x018E,0x018F,0x0190,0x0191,0x0191,0x0193,0x0194,0x01F6,0x0196,0x0197,0x0198,0x0198,0x023D,0x019B,0x019C,0x019D,0x0220,0x019F,0x01A0,0x01A0,0x01A2,0x01A2,0x01A4,0x01A4,0x01A6,0x01A7,0x01A7,0x01A9,0x01AA,0x01AB,0x01AC,0x01AC,0x01AE,0x01AF,0x01AF,0x01B1,0x01B2,0x01B3,0x01B3,0x01B5,0x01B5,0x01B7,0x01B8,0x01B8,0x01BA,0x01BB,0x01BC,0x01BC,0x01BE,0x01F7,0x01C0,0x01C1,0x01C2,0x01C3,0x01C4,0x01C5,0x01C4,0x01C7,0x01C8,0x01C7,0x01CA,0x01CB,0x01CA,
+		0x01CD,0x0110,
+		0x01DD,0x0001,0x018E,
+		0x01DE,0x0112,
+		0x01F3,0x0003,0x01F1,0x01F4,0x01F4,
+		0x01F8,0x0128,
+		0x0222,0x0112,
+		0x023A,0x0009,0x2C65,0x023B,0x023B,0x023D,0x2C66,0x023F,0x0240,0x0241,0x0241,
+		0x0246,0x010A,
+		/* IPA Extensions */
+		0x0253,0x0040,0x0181,0x0186,0x0255,0x0189,0x018A,0x0258,0x018F,0x025A,0x0190,0x025C,0x025D,0x025E,0x025F,0x0193,0x0261,0x0262,0x0194,0x0264,0x0265,0x0266,0x0267,0x0197,0x0196,0x026A,0x2C62,0x026C,0x026D,0x026E,0x019C,0x0270,0x0271,0x019D,0x0273,0x0274,0x019F,0x0276,0x0277,0x0278,0x0279,0x027A,0x027B,0x027C,0x2C64,0x027E,0x027F,0x01A6,0x0281,0x0282,0x01A9,0x0284,0x0285,0x0286,0x0287,0x01AE,0x0244,0x01B1,0x01B2,0x0245,0x028D,0x028E,0x028F,0x0290,0x0291,0x01B7,
+		/* Greek, Coptic */
+		0x037B,0x0003,0x03FD,0x03FE,0x03FF,
+		0x03AC,0x0004,0x0386,0x0388,0x0389,0x038A,
+		0x03B1,0x0311,
+		0x03C2,0x0002,0x03A3,0x03A3,
+		0x03C4,0x0308,
+		0x03CC,0x0003,0x038C,0x038E,0x038F,
+		0x03D8,0x0118,
+		0x03F2,0x000A,0x03F9,0x03F3,0x03F4,0x03F5,0x03F6,0x03F7,0x03F7,0x03F9,0x03FA,0x03FA,
+		/* Cyrillic */
+		0x0430,0x0320,
+		0x0450,0x0710,
+		0x0460,0x0122,
+		0x048A,0x0136,
+		0x04C1,0x010E,
+		0x04CF,0x0001,0x04C0,
+		0x04D0,0x0144,
+		/* Armenian */
+		0x0561,0x0426,
+
+		0x0000	/* EOT */
+	};
+	static const WORD cvt2[] = {	/* Compressed up conversion table for U+1000 - U+FFFF */
+		/* Phonetic Extensions */
+		0x1D7D,0x0001,0x2C63,
+		/* Latin Extended Additional */
+		0x1E00,0x0196,
+		0x1EA0,0x015A,
+		/* Greek Extended */
+		0x1F00,0x0608,
+		0x1F10,0x0606,
+		0x1F20,0x0608,
+		0x1F30,0x0608,
+		0x1F40,0x0606,
+		0x1F51,0x0007,0x1F59,0x1F52,0x1F5B,0x1F54,0x1F5D,0x1F56,0x1F5F,
+		0x1F60,0x0608,
+		0x1F70,0x000E,0x1FBA,0x1FBB,0x1FC8,0x1FC9,0x1FCA,0x1FCB,0x1FDA,0x1FDB,0x1FF8,0x1FF9,0x1FEA,0x1FEB,0x1FFA,0x1FFB,
+		0x1F80,0x0608,
+		0x1F90,0x0608,
+		0x1FA0,0x0608,
+		0x1FB0,0x0004,0x1FB8,0x1FB9,0x1FB2,0x1FBC,
+		0x1FCC,0x0001,0x1FC3,
+		0x1FD0,0x0602,
+		0x1FE0,0x0602,
+		0x1FE5,0x0001,0x1FEC,
+		0x1FF3,0x0001,0x1FFC,
+		/* Letterlike Symbols */
+		0x214E,0x0001,0x2132,
+		/* Number forms */
+		0x2170,0x0210,
+		0x2184,0x0001,0x2183,
+		/* Enclosed Alphanumerics */
+		0x24D0,0x051A,
+		0x2C30,0x042F,
+		/* Latin Extended-C */
+		0x2C60,0x0102,
+		0x2C67,0x0106, 0x2C75,0x0102,
+		/* Coptic */
+		0x2C80,0x0164,
+		/* Georgian Supplement */
+		0x2D00,0x0826,
+		/* Full-width */
+		0xFF41,0x031A,
+
+		0x0000	/* EOT */
+	};
+
+
+	if (uni < 0x10000) {	/* Is it in BMP? */
+		uc = (WORD)uni;
+		p = uc < 0x1000 ? cvt1 : cvt2;
+		for (;;) {
+			bc = *p++;								/* Get the block base */
+			if (bc == 0 || uc < bc) break;			/* Not matched? */
+			nc = *p++; cmd = nc >> 8; nc &= 0xFF;	/* Get processing command and block size */
+			if (uc < bc + nc) {	/* In the block? */
+				switch (cmd) {
+				case 0:	uc = p[uc - bc]; break;		/* Table conversion */
+				case 1:	uc -= (uc - bc) & 1; break;	/* Case pairs */
+				case 2: uc -= 16; break;			/* Shift -16 */
+				case 3:	uc -= 32; break;			/* Shift -32 */
+				case 4:	uc -= 48; break;			/* Shift -48 */
+				case 5:	uc -= 26; break;			/* Shift -26 */
+				case 6:	uc += 8; break;				/* Shift +8 */
+				case 7: uc -= 80; break;			/* Shift -80 */
+				case 8:	uc -= 0x1C60; break;		/* Shift -0x1C60 */
+				}
+				break;
+			}
+			if (cmd == 0) p += nc;	/* Skip table if needed */
+		}
+		uni = uc;
+	}
+
+	return uni;
+}
+
+
+#endif /* #if FF_USE_LFN != 0 */

From a6001fc8f2cfe0db2cf5ba410b49961781ce1803 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Nov 2022 21:50:00 +0700
Subject: [PATCH 1223/2085] update uart read for lpc18/43 for testing

---
 examples/device/board_test/src/main.c | 9 ++++++++-
 hw/bsp/board.c                        | 6 ++++--
 hw/bsp/board.h                        | 2 ++
 hw/bsp/ea4357/ea4357.c                | 4 +---
 hw/bsp/lpc18/family.c                 | 4 +---
 hw/bsp/rp2040/board.h                 | 2 +-
 6 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index 5e28cbb27..74beda55f 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -56,7 +56,7 @@ int main(void)
   {
     uint32_t interval_ms = board_button_read() ? BLINK_PRESSED : BLINK_UNPRESSED;
 
-    // Blink every interval ms
+    // Blink and print every interval ms
     if ( !(board_millis() - start_ms < interval_ms) )
     {
       board_uart_write(HELLO_STR, strlen(HELLO_STR));
@@ -66,6 +66,13 @@ int main(void)
       board_led_write(led_state);
       led_state = 1 - led_state; // toggle
     }
+
+    // echo
+    uint8_t ch;
+    if ( board_uart_read(&ch, 1) )
+    {
+      board_uart_write(&ch, 1);
+    }
   }
 
   return 0;
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index e208624ba..a22b462d9 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -103,7 +103,8 @@ TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
 TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 {
   (void) fhdl;
-  return SEGGER_RTT_Read(0, buf, count);
+  int rd = (int) SEGGER_RTT_Read(0, buf, count);
+  return (rd > 0) ? rd : -1;
 }
 #endif
 
@@ -143,7 +144,8 @@ TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
 TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 {
   (void) fhdl;
-  return board_uart_read((uint8_t*) buf, (int) count);
+  int rd = board_uart_read((uint8_t*) buf, (int) count);
+  return (rd > 0) ? rd : -1;
 }
 
 #endif
diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index 339e2e3b5..0826d7786 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -66,9 +66,11 @@ void board_led_write(bool state);
 uint32_t board_button_read(void);
 
 // Get characters from UART
+// Return number of read bytes
 int board_uart_read(uint8_t* buf, int len);
 
 // Send characters to UART
+// Return number of sent bytes
 int board_uart_write(void const * buf, int len);
 
 #if CFG_TUSB_OS == OPT_OS_NONE
diff --git a/hw/bsp/ea4357/ea4357.c b/hw/bsp/ea4357/ea4357.c
index 2c1d08770..f88d3b89e 100644
--- a/hw/bsp/ea4357/ea4357.c
+++ b/hw/bsp/ea4357/ea4357.c
@@ -272,9 +272,7 @@ uint32_t board_button_read(void)
 
 int board_uart_read(uint8_t* buf, int len)
 {
-  //return UART_ReceiveByte(BOARD_UART_DEV);
-  (void) buf; (void) len;
-  return 0;
+  return Chip_UART_Read(UART_DEV, buf, len);
 }
 
 int board_uart_write(void const * buf, int len)
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index 0fc788873..72c20e034 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -141,9 +141,7 @@ uint32_t board_button_read(void)
 
 int board_uart_read(uint8_t* buf, int len)
 {
-  //return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
-  return 0;
+  return Chip_UART_Read(UART_DEV, buf, len);
 }
 
 int board_uart_write(void const * buf, int len)
diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index 56b8fec84..f25f80e09 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -52,7 +52,7 @@
 #endif
 
 // VBUS enable pin and its active state
-// #define PIO_USB_VBUSEN_PIN    22
+#define PIO_USB_VBUSEN_PIN    22
 
 #ifndef PIO_USB_VBUSEN_STATE
 #define PIO_USB_VBUSEN_STATE  1

From bb570e02d6a8b34fe00c90f5cd8ad736d990ed42 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Nov 2022 13:44:07 +0700
Subject: [PATCH 1224/2085] msc explorer ls work great

---
 examples/host/msc_file_explorer/src/main.c    |    2 +-
 examples/host/msc_file_explorer/src/msc_app.c |  216 +-
 .../host/msc_file_explorer/src/tusb_config.h  |    5 +-
 lib/fatfs/00readme.txt                        |  138 -
 lib/fatfs/ccsbcs.c                            |  543 ---
 lib/fatfs/diskio.c                            |  193 -
 lib/fatfs/diskio.h                            |   95 -
 lib/fatfs/ff.c                                | 4330 -----------------
 lib/fatfs/ff.h                                |  342 --
 lib/fatfs/ffconf.h                            |  193 -
 lib/fatfs/integer.h                           |   36 -
 lib/fatfs/source/ffconf.h                     |    6 +-
 12 files changed, 197 insertions(+), 5902 deletions(-)
 delete mode 100644 lib/fatfs/00readme.txt
 delete mode 100644 lib/fatfs/ccsbcs.c
 delete mode 100644 lib/fatfs/diskio.c
 delete mode 100644 lib/fatfs/diskio.h
 delete mode 100644 lib/fatfs/ff.c
 delete mode 100644 lib/fatfs/ff.h
 delete mode 100644 lib/fatfs/ffconf.h
 delete mode 100644 lib/fatfs/integer.h

diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index 13c473d9b..f46e5092b 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -43,7 +43,7 @@ int main(void)
 {
   board_init();
 
-  printf("TinyUSB Host CDC MSC HID Example\r\n");
+  printf("TinyUSB Host MSC Explorer Example\r\n");
 
   // init host stack on configured roothub port
   tuh_init(BOARD_TUH_RHPORT);
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index a9976be23..a8603c9df 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -25,14 +25,18 @@
 
 #include "tusb.h"
 
+#include "ff.h"
+#include "diskio.h"
+
+// lib/embedded-cli
 #define EMBEDDED_CLI_IMPL
-#include "embedded_cli.h" // lib/embedded-cli
+#include "embedded_cli.h"
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
-// embedded cli configuration
+//------------- embedded-cli -------------//
 #define CLI_BUFFER_SIZE     256
 #define CLI_RX_BUFFER_SIZE  16
 #define CLI_CMD_BUFFER_SIZE 32
@@ -42,12 +46,18 @@
 static EmbeddedCli *_cli;
 static CLI_UINT cli_buffer[BYTES_TO_CLI_UINTS(CLI_BUFFER_SIZE)];
 
+//------------- Elm Chan FatFS -------------//
+static FATFS fatfs[CFG_TUH_DEVICE_MAX]; // for simplicity only support 1 LUN per device
+static volatile bool _disk_busy[CFG_TUH_DEVICE_MAX];
+
 static scsi_inquiry_resp_t inquiry_resp;
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
+void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context);
+
 void cli_write_char(EmbeddedCli *cli, char c)
 {
   (void) cli;
@@ -62,6 +72,8 @@ void cli_cmd_unknown(EmbeddedCli *cli, CliCommand *command)
 
 bool msc_app_init(void)
 {
+  for(size_t i=0; i<CFG_TUH_DEVICE_MAX; i++) _disk_busy[i] = false;
+
   // disable stdout buffered for echoing typing command
   setbuf(stdout, NULL);
 
@@ -78,6 +90,14 @@ bool msc_app_init(void)
 
   _cli->writeChar = cli_write_char;
 
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "ls",
+    "Usage: ls [FILE]...\r\n\tList information about the FILEs (the current directory by default).",
+    true,
+    NULL,
+    cli_cmd_ls
+  });
+
   return true;
 }
 
@@ -117,6 +137,19 @@ bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const
   printf("Disk Size: %lu MB\r\n", block_count / ((1024*1024)/block_size));
   printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
 
+  // For simplicity: we only mount 1 LUN per device
+  uint8_t const drive_num = dev_addr-1;
+  char drive_path[3] = "0:";
+  drive_path[0] += drive_num;
+
+  if ( f_mount(&fatfs[drive_num], drive_path, 1) != FR_OK )
+  {
+    puts("mount failed");
+  }
+
+  f_chdrive(drive_path); // change to newly mounted drive
+  f_chdir("/"); // root as current dir
+
   return true;
 }
 
@@ -127,24 +160,6 @@ void tuh_msc_mount_cb(uint8_t dev_addr)
 
   uint8_t const lun = 0;
   tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb);
-//
-//  //------------- file system (only 1 LUN support) -------------//
-//  uint8_t phy_disk = dev_addr-1;
-//  disk_initialize(phy_disk);
-//
-//  if ( disk_is_ready(phy_disk) )
-//  {
-//    if ( f_mount(phy_disk, &fatfs[phy_disk]) != FR_OK )
-//    {
-//      puts("mount failed");
-//      return;
-//    }
-//
-//    f_chdrive(phy_disk); // change to newly mounted drive
-//    f_chdir("/"); // root as current dir
-//
-//    cli_init();
-//  }
 }
 
 void tuh_msc_umount_cb(uint8_t dev_addr)
@@ -152,11 +167,12 @@ void tuh_msc_umount_cb(uint8_t dev_addr)
   (void) dev_addr;
   printf("A MassStorage device is unmounted\r\n");
 
-//  uint8_t phy_disk = dev_addr-1;
-//
-//  f_mount(phy_disk, NULL); // unmount disk
-//  disk_deinitialize(phy_disk);
-//
+  uint8_t const drive_num = dev_addr-1;
+  char drive_path[3] = "0:";
+  drive_path[0] += drive_num;
+
+  f_unmount(drive_path);
+
 //  if ( phy_disk == f_get_current_drive() )
 //  { // active drive is unplugged --> change to other drive
 //    for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
@@ -169,3 +185,153 @@ void tuh_msc_umount_cb(uint8_t dev_addr)
 //    }
 //  }
 }
+
+//--------------------------------------------------------------------+
+// DiskIO
+//--------------------------------------------------------------------+
+
+static void wait_for_disk_io(BYTE pdrv)
+{
+  while(_disk_busy[pdrv])
+  {
+    tuh_task();
+  }
+}
+
+static bool disk_io_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
+{
+  (void) dev_addr; (void) cbw; (void) csw;
+  _disk_busy[dev_addr-1] = false;
+  return true;
+}
+
+DSTATUS disk_status (
+	BYTE pdrv		/* Physical drive nmuber to identify the drive */
+)
+{
+  uint8_t dev_addr = pdrv + 1;
+  return tuh_msc_mounted(dev_addr) ? 0 : STA_NODISK;
+}
+
+DSTATUS disk_initialize (
+	BYTE pdrv				/* Physical drive nmuber to identify the drive */
+)
+{
+  (void) pdrv;
+	return 0; // nothing to do
+}
+
+DRESULT disk_read (
+	BYTE pdrv,		/* Physical drive nmuber to identify the drive */
+	BYTE *buff,		/* Data buffer to store read data */
+	LBA_t sector,	/* Start sector in LBA */
+	UINT count		/* Number of sectors to read */
+)
+{
+	uint8_t const dev_addr = pdrv + 1;
+	uint8_t const lun = 0;
+
+	_disk_busy[pdrv] = true;
+	tuh_msc_read10(dev_addr, lun, buff, sector, count, disk_io_complete);
+	wait_for_disk_io(pdrv);
+
+	return RES_OK;
+}
+
+#if FF_FS_READONLY == 0
+
+DRESULT disk_write (
+	BYTE pdrv,			/* Physical drive nmuber to identify the drive */
+	const BYTE *buff,	/* Data to be written */
+	LBA_t sector,		/* Start sector in LBA */
+	UINT count			/* Number of sectors to write */
+)
+{
+	uint8_t const dev_addr = pdrv + 1;
+	uint8_t const lun = 0;
+
+	_disk_busy[pdrv] = true;
+	tuh_msc_write10(dev_addr, lun, buff, sector, count, disk_io_complete);
+	wait_for_disk_io(pdrv);
+
+	return RES_OK;
+}
+
+#endif
+
+DRESULT disk_ioctl (
+	BYTE pdrv,		/* Physical drive nmuber (0..) */
+	BYTE cmd,		/* Control code */
+	void *buff		/* Buffer to send/receive control data */
+)
+{
+  uint8_t const dev_addr = pdrv + 1;
+  uint8_t const lun = 0;
+  switch ( cmd )
+  {
+    case CTRL_SYNC:
+      // nothing to do since we do blocking
+      return RES_OK;
+
+    case GET_SECTOR_COUNT:
+      *((DWORD*) buff) = tuh_msc_get_block_count(dev_addr, lun);
+      return RES_OK;
+
+    case GET_SECTOR_SIZE:
+      *((WORD*) buff) = tuh_msc_get_block_size(dev_addr, lun);
+      return RES_OK;
+
+    case GET_BLOCK_SIZE:
+      *((DWORD*) buff) = 1;    // erase block size in units of sector size
+      return RES_OK;
+
+    default:
+      return RES_PARERR;
+  }
+
+	return RES_OK;
+}
+
+//--------------------------------------------------------------------+
+// CLI Commands
+//--------------------------------------------------------------------+
+
+void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
+{
+  (void) cli;
+  (void) context;
+
+  uint16_t argc = embeddedCliGetTokenCount(args);
+
+  // only support 1 argument
+  if ( argc > 1 ) return;
+
+  // default is current directory
+  const char* dpath = ".";
+  if (argc) dpath = args;
+
+  DIR dir;
+  if ( FR_OK != f_opendir(&dir, dpath) )
+  {
+    printf("cannot access '%s': No such file or directory", dpath);
+    return;
+  }
+
+  FILINFO fno;
+  while( (f_readdir(&dir, &fno) == FR_OK) && (fno.fname[0] != 0) )
+  {
+    if ( fno.fname[0] != '.' ) // ignore . and .. entry
+    {
+      if ( fno.fattrib & AM_DIR )
+      {
+        // directory
+        printf("/%s\n", fno.fname);
+      }else
+      {
+        printf("%-40s%lu KB\n", fno.fname, fno.fsize / 1000);
+      }
+    }
+  }
+
+  f_closedir(&dir);
+}
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index fd1215388..ddf8368f4 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -104,9 +104,8 @@
 // max device support (excluding hub device)
 #define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
 
-//------------- HID -------------//
-#define CFG_TUH_HID_EPIN_BUFSIZE    64
-#define CFG_TUH_HID_EPOUT_BUFSIZE   64
+//------------- MSC -------------//
+#define CFG_TUH_MSC_MAXLUN    4 // typical for most card reader
 
 #ifdef __cplusplus
  }
diff --git a/lib/fatfs/00readme.txt b/lib/fatfs/00readme.txt
deleted file mode 100644
index f7330e924..000000000
--- a/lib/fatfs/00readme.txt
+++ /dev/null
@@ -1,138 +0,0 @@
-FatFs Module Source Files R0.09b                       (C)ChaN, 2013
-
-
-FILES
-
-  ffconf.h   Configuration file for FatFs module.
-  ff.h       Common include file for FatFs and application module.
-  ff.c       FatFs module.
-  diskio.h   Common include file for FatFs and disk I/O module.
-  diskio.c   An example of glue function to attach existing disk I/O module to FatFs.
-  integer.h  Integer type definitions for FatFs.
-  option     Optional external functions.
-
-  Low level disk I/O module is not included in this archive because the FatFs
-  module is only a generic file system layer and not depend on any specific
-  storage device. You have to provide a low level disk I/O module that written
-  to control your storage device.
-
-
-
-AGREEMENTS
-
- FatFs module is an open source software to implement FAT file system to
- small embedded systems. This is a free software and is opened for education,
- research and commercial developments under license policy of following trems.
-
-  Copyright (C) 2012, ChaN, all right reserved.
-
- * The FatFs module is a free software and there is NO WARRANTY.
- * No restriction on use. You can use, modify and redistribute it for
-   personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
- * Redistributions of source code must retain the above copyright notice.
-
-
-
-REVISION HISTORY
-
-  Feb 26, 2006  R0.00  Prototype
-
-  Apr 29, 2006  R0.01  First release.
-
-  Jun 01, 2006  R0.02  Added FAT12.
-                       Removed unbuffered mode.
-                       Fixed a problem on small (<32M) patition.
-
-  Jun 10, 2006  R0.02a Added a configuration option _FS_MINIMUM.
-
-  Sep 22, 2006  R0.03  Added f_rename.
-                       Changed option _FS_MINIMUM to _FS_MINIMIZE.
-
-  Dec 11, 2006  R0.03a Improved cluster scan algolithm to write files fast.
-                       Fixed f_mkdir creates incorrect directory on FAT32.
-
-  Feb 04, 2007  R0.04  Supported multiple drive system. (FatFs)
-                       Changed some APIs for multiple drive system.
-                       Added f_mkfs. (FatFs)
-                       Added _USE_FAT32 option. (Tiny-FatFs)
-
-  Apr 01, 2007  R0.04a Supported multiple partitions on a plysical drive. (FatFs)
-                       Fixed an endian sensitive code in f_mkfs. (FatFs)
-                       Added a capability of extending the file size to f_lseek.
-                       Added minimization level 3.
-                       Fixed a problem that can collapse a sector when recreate an
-                       existing file in any sub-directory at non FAT32 cfg. (Tiny-FatFs)
-
-  May 05, 2007  R0.04b Added _USE_NTFLAG option.
-                       Added FSInfo support.
-                       Fixed some problems corresponds to FAT32. (Tiny-FatFs)
-                       Fixed DBCS name can result FR_INVALID_NAME.
-                       Fixed short seek (0 < ofs <= csize) collapses the file object.
-
-  Aug 25, 2007  R0.05  Changed arguments of f_read, f_write.
-                       Changed arguments of f_mkfs. (FatFs)
-                       Fixed f_mkfs on FAT32 creates incorrect FSInfo. (FatFs)
-                       Fixed f_mkdir on FAT32 creates incorrect directory. (FatFs)
-
-  Feb 03, 2008  R0.05a Added f_truncate().
-                       Added f_utime().
-                       Fixed off by one error at FAT sub-type determination.
-                       Fixed btr in f_read() can be mistruncated.
-                       Fixed cached sector is not flushed when create and close without write.
-
-  Apr 01, 2008  R0.06  Added f_forward(). (Tiny-FatFs)
-                       Added string functions: fputc(), fputs(), fprintf() and fgets().
-                       Improved performance of f_lseek() on move to the same or following cluster.
-
-  Apr 01, 2009, R0.07  Merged Tiny-FatFs as a buffer configuration option.
-                       Added long file name support.
-                       Added multiple code page support.
-                       Added re-entrancy for multitask operation.
-                       Added auto cluster size selection to f_mkfs().
-                       Added rewind option to f_readdir().
-                       Changed result code of critical errors.
-                       Renamed string functions to avoid name collision.
-
-  Apr 14, 2009, R0.07a Separated out OS dependent code on reentrant cfg.
-                       Added multiple sector size support.
-
-  Jun 21, 2009, R0.07c Fixed f_unlink() may return FR_OK on error.
-                       Fixed wrong cache control in f_lseek().
-                       Added relative path feature.
-                       Added f_chdir().
-                       Added f_chdrive().
-                       Added proper case conversion for extended characters.
-
-  Nov 03, 2009 R0.07e  Separated out configuration options from ff.h to ffconf.h.
-                       Added a configuration option, _LFN_UNICODE.
-                       Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH.
-                       Fixed name matching error on the 13 char boundary.
-                       Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
-
-  May 15, 2010, R0.08  Added a memory configuration option. (_USE_LFN)
-                       Added file lock feature. (_FS_SHARE)
-                       Added fast seek feature. (_USE_FASTSEEK)
-                       Changed some types on the API, XCHAR->TCHAR.
-                       Changed fname member in the FILINFO structure on Unicode cfg.
-                       String functions support UTF-8 encoding files on Unicode cfg.
-
-  Aug 16,'10 R0.08a    Added f_getcwd(). (_FS_RPATH = 2)
-                       Added sector erase feature. (_USE_ERASE)
-                       Moved file lock semaphore table from fs object to the bss.
-                       Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'.
-                       Fixed f_mkfs() creates wrong FAT32 volume.
-
-  Jan 15,'11 R0.08b    Fast seek feature is also applied to f_read() and f_write().
-                       f_lseek() reports required table size on creating CLMP.
-                       Extended format syntax of f_printf function.
-                       Ignores duplicated directory separators in given path names.
-
-  Sep 06,'11 R0.09     f_mkfs() supports multiple partition to finish the multiple partition feature.
-                       Added f_fdisk(). (_MULTI_PARTITION = 2)
-
-  Aug 27,'12 R0.09a    Fixed assertion failure due to OS/2 EA on FAT12/16.
-                       Changed f_open() and f_opendir() reject null object pointer to avoid crash.
-                       Changed option name _FS_SHARE to _FS_LOCK.
-
-  Jan 23,'13 R0.09b    Added f_getlabel() and f_setlabel(). (_USE_LABEL == 1)
-
diff --git a/lib/fatfs/ccsbcs.c b/lib/fatfs/ccsbcs.c
deleted file mode 100644
index 07d6f0983..000000000
--- a/lib/fatfs/ccsbcs.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/*------------------------------------------------------------------------*/
-/* Unicode - Local code bidirectional converter  (C)ChaN, 2012            */
-/* (SBCS code pages)                                                      */
-/*------------------------------------------------------------------------*/
-/*  437   U.S. (OEM)
-/   720   Arabic (OEM)
-/   1256  Arabic (Windows)
-/   737   Greek (OEM)
-/   1253  Greek (Windows)
-/   1250  Central Europe (Windows)
-/   775   Baltic (OEM)
-/   1257  Baltic (Windows)
-/   850   Multilingual Latin 1 (OEM)
-/   852   Latin 2 (OEM)
-/   1252  Latin 1 (Windows)
-/   855   Cyrillic (OEM)
-/   1251  Cyrillic (Windows)
-/   866   Russian (OEM)
-/   857   Turkish (OEM)
-/   1254  Turkish (Windows)
-/   858   Multilingual Latin 1 + Euro (OEM)
-/   862   Hebrew (OEM)
-/   1255  Hebrew (Windows)
-/   874   Thai (OEM, Windows)
-/   1258  Vietnam (OEM, Windows)
-*/
-
-#include "ff.h"
-
-#if CFG_TUH_MSC
-
-#if _CODE_PAGE == 437
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP437(0x80-0xFF) to Unicode conversion table */
-	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
-	0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
-	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
-	0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
-	0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
-	0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
-	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
-	0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
-	0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
-	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
-	0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 720
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP720(0x80-0xFF) to Unicode conversion table */
-	0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7,
-	0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9,
-	0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
-	0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
-	0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
-	0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
-	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
-	0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642,
-	0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
-	0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248,
-	0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 737
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP737(0x80-0xFF) to Unicode conversion table */
-	0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398,
-	0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
-	0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9,
-	0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
-	0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0,
-	0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
-	0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
-	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
-	0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD,
-	0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
-	0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248,
-	0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 775
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP775(0x80-0xFF) to Unicode conversion table */
-	0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107,
-	0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
-	0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A,
-	0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
-	0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6,
-	0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118,
-	0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
-	0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B,
-	0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144,
-	0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
-	0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E,
-	0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 850
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP850(0x80-0xFF) to Unicode conversion table */
-	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
-	0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
-	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
-	0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
-	0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
-	0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
-	0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE,
-	0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
-	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
-	0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
-	0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
-	0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 852
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP852(0x80-0xFF) to Unicode conversion table */
-	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7,
-	0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
-	0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A,
-	0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E,
-	0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A,
-	0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
-	0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE,
-	0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
-	0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161,
-	0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
-	0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8,
-	0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 855
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP855(0x80-0xFF) to Unicode conversion table */
-	0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404,
-	0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
-	0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C,
-	0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
-	0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414,
-	0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438,
-	0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
-	0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E,
-	0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
-	0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443,
-	0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
-	0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D,
-	0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 857
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP857(0x80-0xFF) to Unicode conversion table */
-	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
-	0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
-	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
-	0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F,
-	0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
-	0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
-	0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE,
-	0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
-	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000,
-	0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
-	0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
-	0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 858
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP858(0x80-0xFF) to Unicode conversion table */
-	0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
-	0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
-	0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
-	0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
-	0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
-	0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
-	0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE,
-	0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580,
-	0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
-	0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
-	0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
-	0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 862
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP862(0x80-0xFF) to Unicode conversion table */
-	0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
-	0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
-	0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
-	0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
-	0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
-	0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
-	0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
-	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
-	0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
-	0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
-	0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
-	0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 866
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP866(0x80-0xFF) to Unicode conversion table */
-	0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
-	0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
-	0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
-	0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
-	0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
-	0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
-	0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
-	0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
-	0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
-	0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
-	0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
-	0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
-	0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
-	0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
-	0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E,
-	0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
-};
-
-#elif _CODE_PAGE == 874
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP874(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000,
-	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07,
-	0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F,
-	0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17,
-	0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F,
-	0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27,
-	0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F,
-	0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37,
-	0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F,
-	0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47,
-	0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F,
-	0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57,
-	0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000
-};
-
-#elif _CODE_PAGE == 1250
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP1250(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A,
-	0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B,
-	0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C,
-	0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7,
-	0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E,
-	0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7,
-	0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF,
-	0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7,
-	0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F,
-	0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7,
-	0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9
-};
-
-#elif _CODE_PAGE == 1251
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP1251(0x80-0xFF) to Unicode conversion table */
-	0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F,
-	0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F,
-	0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7,
-	0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407,
-	0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7,
-	0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457,
-	0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
-	0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
-	0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
-	0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
-	0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
-	0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
-	0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
-	0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F
-};
-
-#elif _CODE_PAGE == 1252
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP1252(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178,
-	0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
-	0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
-	0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
-	0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
-	0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF,
-	0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
-	0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
-	0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
-	0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF
-};
-
-#elif _CODE_PAGE == 1253
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP1253(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7,
-	0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F,
-	0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397,
-	0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F,
-	0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7,
-	0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF,
-	0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7,
-	0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF,
-	0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7,
-	0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000
-};
-
-#elif _CODE_PAGE == 1254
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP1254(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
-	0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
-	0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
-	0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
-	0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
-	0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF,
-	0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
-	0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
-	0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
-	0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF
-};
-
-#elif _CODE_PAGE == 1255
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP1255(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
-	0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7,
-	0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF,
-	0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3,
-	0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-	0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
-	0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
-	0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
-	0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000
-};
-
-#elif _CODE_PAGE == 1256
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP1256(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688,
-	0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA,
-	0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F,
-	0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627,
-	0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
-	0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7,
-	0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643,
-	0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7,
-	0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF,
-	0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7,
-	0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2
-}
-
-#elif _CODE_PAGE == 1257
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP1257(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000,
-	0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7,
-	0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6,
-	0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112,
-	0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B,
-	0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7,
-	0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF,
-	0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113,
-	0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C,
-	0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7,
-	0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9
-};
-
-#elif _CODE_PAGE == 1258
-#define _TBLDEF 1
-static
-const WCHAR Tbl[] = {	/*  CP1258(0x80-0xFF) to Unicode conversion table */
-	0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
-	0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
-	0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
-	0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
-	0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
-	0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
-	0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
-	0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
-	0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
-	0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF,
-	0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7,
-	0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF,
-	0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
-	0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF,
-	0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7,
-	0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF
-};
-
-#endif
-
-
-#if !_TBLDEF || !_USE_LFN
-#error This file is not needed in current configuration. Remove from the project.
-#endif
-
-
-WCHAR ff_convert (	/* Converted character, Returns zero on error */
-	WCHAR	chr,	/* Character code to be converted */
-	UINT	dir		/* 0: Unicode to OEMCP, 1: OEMCP to Unicode */
-)
-{
-	WCHAR c;
-
-
-	if (chr < 0x80) {	/* ASCII */
-		c = chr;
-
-	} else {
-		if (dir) {		/* OEMCP to Unicode */
-			c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80];
-
-		} else {		/* Unicode to OEMCP */
-			for (c = 0; c < 0x80; c++) {
-				if (chr == Tbl[c]) break;
-			}
-			c = (c + 0x80) & 0xFF;
-		}
-	}
-
-	return c;
-}
-
-
-WCHAR ff_wtoupper (	/* Upper converted character */
-	WCHAR chr		/* Input character */
-)
-{
-	static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 };
-	static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 };
-	int i;
-
-
-	for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ;
-
-	return tbl_lower[i] ? tbl_upper[i] : chr;
-}
-
-#endif // CFG_TUH_MSC
diff --git a/lib/fatfs/diskio.c b/lib/fatfs/diskio.c
deleted file mode 100644
index a6132f27b..000000000
--- a/lib/fatfs/diskio.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* 
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb.h"
-
-#if CFG_TUH_MSC
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#include "ffconf.h"
-#include "diskio.h"
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-// TODO change it to portable init
-static DSTATUS disk_state[CFG_TUH_DEVICE_MAX];
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-
-//--------------------------------------------------------------------+
-// IMPLEMENTATION
-//--------------------------------------------------------------------+
-static DRESULT wait_for_io_complete(uint8_t usb_addr)
-{
-  // TODO with RTOS, this should use semaphore instead of blocking
-  while ( !tuh_msc_ready(usb_addr) )
-  {
-    // TODO should have timeout here
-    #if CFG_TUSB_OS != OPT_OS_NONE
-    osal_task_delay(10);
-    #endif
-  }
-
-  return RES_OK;
-}
-
-void diskio_init(void)
-{
-  memset(disk_state, STA_NOINIT, CFG_TUH_DEVICE_MAX);
-}
-
-//pdrv Specifies the physical drive number.
-DSTATUS disk_initialize ( BYTE pdrv )
-{
-  disk_state[pdrv] &= (~STA_NOINIT); // clear NOINIT bit
-  return disk_state[pdrv];
-}
-
-void disk_deinitialize ( BYTE pdrv )
-{
-  disk_state[pdrv] |= STA_NOINIT; // set NOINIT bit
-}
-
-DSTATUS disk_status (BYTE pdrv)
-{
-  return disk_state[pdrv];
-}
-
-//pdrv
-//    Specifies the physical drive number -->  == dev_addr-1
-//buff
-//    Pointer to the byte array to store the read data. The size of buffer must be in sector size * sector count.
-//sector
-//    Specifies the start sector number in logical block address (LBA).
-//count
-//    Specifies number of sectors to read. The value can be 1 to 128. Generally, a multiple sector transfer request
-//    must not be split into single sector transactions to the device, or you may not get good read performance.
-DRESULT disk_read (BYTE pdrv, BYTE*buff, DWORD sector, BYTE count)
-{
-  uint8_t usb_addr = pdrv+1;
-
-	if ( TUSB_ERROR_NONE != tuh_msc_read10(usb_addr, 0, buff, sector, count) )		return RES_ERROR;
-
-	return wait_for_io_complete(usb_addr);
-}
-
-
-DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, BYTE count)
-{
-  uint8_t usb_addr = pdrv+1;
-
-	if ( TUSB_ERROR_NONE != tuh_msc_write10(usb_addr, 0, buff, sector, count) )		return RES_ERROR;
-
-	return wait_for_io_complete(usb_addr);
-}
-
-/* [IN] Drive number */
-/* [IN] Control command code */
-/* [I/O] Parameter and data buffer */
-DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff)
-{
-  (void) buff; (void) pdrv; // compiler warnings
-
-  if (cmd != CTRL_SYNC) return RES_ERROR;
-  return RES_OK;
-}
-
-static inline uint8_t month2number(char* p_ch)
-{
-  char const * const month_str[] = { "Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec" };
-
-  for(uint8_t i=0; i<12; i++)
-  {
-    if ( strncmp(p_ch, month_str[i], 3) == 0 ) return i+1;
-  }
-
-  return 1;
-}
-
-static inline uint8_t c2i(char ch)
-{
-  return ch - '0';
-}
-
-DWORD get_fattime (void)
-{
-  union {
-    struct {
-      DWORD second       : 5;
-      DWORD minute       : 6;
-      DWORD hour         : 5;
-      DWORD day_in_month : 5;
-      DWORD month        : 4;
-      DWORD year         : 7;
-    };
-
-    DWORD value;
-  } timestamp;
-
-  //------------- Date is compiled date-------------//
-  char compile_date[] = __DATE__; // eg. "Sep 26 2013"
-  char* p_ch;
-
-  p_ch = strtok (compile_date, " ");
-  timestamp.month = month2number(p_ch);
-
-  p_ch = strtok (NULL, " ");
-  timestamp.day_in_month = 10*c2i(p_ch[0])+ c2i(p_ch[1]);
-
-  p_ch = strtok (NULL, " ");
-  timestamp.year = 1000*c2i(p_ch[0]) + 100*c2i(p_ch[1]) + 10*c2i(p_ch[2]) + c2i(p_ch[3]) - 1980;
-
-  //------------- Time each time this function call --> sec ++ -------------//
-  static uint8_t sec = 0;
-  static uint8_t min = 0;
-  static uint8_t hour = 0;
-
-  if (++sec >= 60)
-  {
-    sec = 0;
-    if (++min >= 60)
-    {
-      min = 0;
-      if (++hour >= 24)
-      {
-        hour = 0; // assume demo wont call this function more than 24*60*60 times
-      }
-    }
-  }
-
-  timestamp.hour   = hour;
-  timestamp.minute = min;
-  timestamp.second = sec;
-
-  return timestamp.value;
-}
-
-#endif // CFG_TUH_MSC
diff --git a/lib/fatfs/diskio.h b/lib/fatfs/diskio.h
deleted file mode 100644
index f1f4bd327..000000000
--- a/lib/fatfs/diskio.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*-----------------------------------------------------------------------
-/  Low level disk interface modlue include file   (C)ChaN, 2013
-/-----------------------------------------------------------------------*/
-
-#ifndef _DISKIO_DEFINED
-#define _DISKIO_DEFINED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define _USE_WRITE	1	/* 1: Enable disk_write function */
-#define _USE_IOCTL	1	/* 1: Enable disk_ioctl fucntion */
-
-#include "integer.h"
-#include <stdbool.h>
-
-/* Status of Disk Functions */
-typedef BYTE	DSTATUS;
-
-/* Results of Disk Functions */
-typedef enum {
-	RES_OK = 0,		/* 0: Successful */
-	RES_ERROR,		/* 1: R/W Error */
-	RES_WRPRT,		/* 2: Write Protected */
-	RES_NOTRDY,		/* 3: Not Ready */
-	RES_PARERR		/* 4: Invalid Parameter */
-} DRESULT;
-
-
-/* Disk Status Bits (DSTATUS) */
-#define STA_NOINIT		0x01	/* Drive not initialized */
-#define STA_NODISK		0x02	/* No medium in the drive */
-#define STA_PROTECT		0x04	/* Write protected */
-
-
-/* Command code for disk_ioctrl fucntion */
-
-/* Generic command (used by FatFs) */
-#define CTRL_SYNC			0	/* Flush disk cache (for write functions) */
-#define GET_SECTOR_COUNT	1	/* Get media size (for only f_mkfs()) */
-#define GET_SECTOR_SIZE		2	/* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
-#define GET_BLOCK_SIZE		3	/* Get erase block size (for only f_mkfs()) */
-#define CTRL_ERASE_SECTOR	4	/* Force erased a block of sectors (for only _USE_ERASE) */
-
-/* Generic command (not used by FatFs) */
-#define CTRL_POWER			5	/* Get/Set power status */
-#define CTRL_LOCK			6	/* Lock/Unlock media removal */
-#define CTRL_EJECT			7	/* Eject media */
-#define CTRL_FORMAT			8	/* Create physical format on the media */
-
-/* MMC/SDC specific ioctl command */
-#define MMC_GET_TYPE		10	/* Get card type */
-#define MMC_GET_CSD			11	/* Get CSD */
-#define MMC_GET_CID			12	/* Get CID */
-#define MMC_GET_OCR			13	/* Get OCR */
-#define MMC_GET_SDSTAT		14	/* Get SD status */
-
-/* ATA/CF specific ioctl command */
-#define ATA_GET_REV			20	/* Get F/W revision */
-#define ATA_GET_MODEL		21	/* Get model name */
-#define ATA_GET_SN			22	/* Get serial number */
-
-
-/* MMC card type flags (MMC_GET_TYPE) */
-#define CT_MMC		0x01		/* MMC ver 3 */
-#define CT_SD1		0x02		/* SD ver 1 */
-#define CT_SD2		0x04		/* SD ver 2 */
-#define CT_SDC		(CT_SD1|CT_SD2)	/* SD */
-#define CT_BLOCK	0x08		/* Block addressing */
-
-/*---------------------------------------*/
-/* Prototypes for disk control functions */
-
-void diskio_init(void);
-void disk_deinitialize ( BYTE pdrv );
-DSTATUS disk_initialize (BYTE pdrv);
-DSTATUS disk_status (BYTE pdrv);
-DRESULT disk_read (BYTE pdrv, BYTE*buff, DWORD sector, BYTE count);
-DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, BYTE count);
-DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
-
-static inline bool disk_is_ready(BYTE pdrv);
-static inline bool disk_is_ready(BYTE pdrv)
-{
-  return (pdrv < CFG_TUH_DEVICE_MAX) &&
-         ( (disk_status(pdrv) & (STA_NOINIT | STA_NODISK)) == 0 );
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/lib/fatfs/ff.c b/lib/fatfs/ff.c
deleted file mode 100644
index 79414af07..000000000
--- a/lib/fatfs/ff.c
+++ /dev/null
@@ -1,4330 +0,0 @@
-/*----------------------------------------------------------------------------/
-/  FatFs - FAT file system module  R0.09b                 (C)ChaN, 2013
-/-----------------------------------------------------------------------------/
-/ FatFs module is a generic FAT file system module for small embedded systems.
-/ This is a free software that opened for education, research and commercial
-/ developments under license policy of following terms.
-/
-/  Copyright (C) 2013, ChaN, all right reserved.
-/
-/ * The FatFs module is a free software and there is NO WARRANTY.
-/ * No restriction on use. You can use, modify and redistribute it for
-/   personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
-/ * Redistributions of source code must retain the above copyright notice.
-/
-/-----------------------------------------------------------------------------/
-/ Feb 26,'06 R0.00  Prototype.
-/
-/ Apr 29,'06 R0.01  First stable version.
-/
-/ Jun 01,'06 R0.02  Added FAT12 support.
-/                   Removed unbuffered mode.
-/                   Fixed a problem on small (<32M) partition.
-/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM).
-/
-/ Sep 22,'06 R0.03  Added f_rename().
-/                   Changed option _FS_MINIMUM to _FS_MINIMIZE.
-/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast.
-/                   Fixed f_mkdir() creates incorrect directory on FAT32.
-/
-/ Feb 04,'07 R0.04  Supported multiple drive system.
-/                   Changed some interfaces for multiple drive system.
-/                   Changed f_mountdrv() to f_mount().
-/                   Added f_mkfs().
-/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive.
-/                   Added a capability of extending file size to f_lseek().
-/                   Added minimization level 3.
-/                   Fixed an endian sensitive code in f_mkfs().
-/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG.
-/                   Added FSInfo support.
-/                   Fixed DBCS name can result FR_INVALID_NAME.
-/                   Fixed short seek (<= csize) collapses the file object.
-/
-/ Aug 25,'07 R0.05  Changed arguments of f_read(), f_write() and f_mkfs().
-/                   Fixed f_mkfs() on FAT32 creates incorrect FSInfo.
-/                   Fixed f_mkdir() on FAT32 creates incorrect directory.
-/ Feb 03,'08 R0.05a Added f_truncate() and f_utime().
-/                   Fixed off by one error at FAT sub-type determination.
-/                   Fixed btr in f_read() can be mistruncated.
-/                   Fixed cached sector is not flushed when create and close without write.
-/
-/ Apr 01,'08 R0.06  Added fputc(), fputs(), fprintf() and fgets().
-/                   Improved performance of f_lseek() on moving to the same or following cluster.
-/
-/ Apr 01,'09 R0.07  Merged Tiny-FatFs as a configuration option. (_FS_TINY)
-/                   Added long file name feature.
-/                   Added multiple code page feature.
-/                   Added re-entrancy for multitask operation.
-/                   Added auto cluster size selection to f_mkfs().
-/                   Added rewind option to f_readdir().
-/                   Changed result code of critical errors.
-/                   Renamed string functions to avoid name collision.
-/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg.
-/                   Added multiple sector size feature.
-/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error.
-/                   Fixed wrong cache control in f_lseek().
-/                   Added relative path feature.
-/                   Added f_chdir() and f_chdrive().
-/                   Added proper case conversion to extended char.
-/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h.
-/                   Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH.
-/                   Fixed name matching error on the 13 char boundary.
-/                   Added a configuration option, _LFN_UNICODE.
-/                   Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
-/
-/ May 15,'10 R0.08  Added a memory configuration option. (_USE_LFN = 3)
-/                   Added file lock feature. (_FS_SHARE)
-/                   Added fast seek feature. (_USE_FASTSEEK)
-/                   Changed some types on the API, XCHAR->TCHAR.
-/                   Changed fname member in the FILINFO structure on Unicode cfg.
-/                   String functions support UTF-8 encoding files on Unicode cfg.
-/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2)
-/                   Added sector erase feature. (_USE_ERASE)
-/                   Moved file lock semaphore table from fs object to the bss.
-/                   Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'.
-/                   Fixed f_mkfs() creates wrong FAT32 volume.
-/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write().
-/                   f_lseek() reports required table size on creating CLMP.
-/                   Extended format syntax of f_printf function.
-/                   Ignores duplicated directory separators in given path name.
-/
-/ Sep 06,'11 R0.09  f_mkfs() supports multiple partition to finish the multiple partition feature.
-/                   Added f_fdisk(). (_MULTI_PARTITION = 2)
-/ Aug 27,'12 R0.09a Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
-/                   Changed f_open() and f_opendir reject null object pointer to avoid crash.
-/                   Changed option name _FS_SHARE to _FS_LOCK.
-/ Jan 24,'13 R0.09b Added f_setlabel() and f_getlabel(). (_USE_LABEL = 1)
-/---------------------------------------------------------------------------*/
-
-#include "ff.h"			/* FatFs configurations and declarations */
-#include "diskio.h"		/* Declarations of low level disk I/O functions */
-
-#if CFG_TUH_MSC
-/*--------------------------------------------------------------------------
-
-   Module Private Definitions
-
----------------------------------------------------------------------------*/
-
-#if _FATFS != 82786	/* Revision ID */
-#error Wrong include file (ff.h).
-#endif
-
-
-/* Definitions on sector size */
-#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096
-#error Wrong sector size.
-#endif
-#if _MAX_SS != 512
-#define	SS(fs)	((fs)->ssize)	/* Variable sector size */
-#else
-#define	SS(fs)	512U			/* Fixed sector size */
-#endif
-
-
-/* Reentrancy related */
-#if _FS_REENTRANT
-#if _USE_LFN == 1
-#error Static LFN work area must not be used in re-entrant configuration.
-#endif
-#define	ENTER_FF(fs)		{ if (!lock_fs(fs)) return FR_TIMEOUT; }
-#define	LEAVE_FF(fs, res)	{ unlock_fs(fs, res); return res; }
-#else
-#define	ENTER_FF(fs)
-#define LEAVE_FF(fs, res)	return res
-#endif
-
-#define	ABORT(fs, res)		{ fp->flag |= FA__ERROR; LEAVE_FF(fs, res); }
-
-
-/* File access control feature */
-#if _FS_LOCK
-#if _FS_READONLY
-#error _FS_LOCK must be 0 on read-only cfg.
-#endif
-typedef struct {
-	FATFS *fs;				/* File ID 1, volume (NULL:blank entry) */
-	DWORD clu;				/* File ID 2, directory */
-	WORD idx;				/* File ID 3, directory index */
-	WORD ctr;				/* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */
-} FILESEM;
-#endif
-
-
-
-/* DBCS code ranges and SBCS extend char conversion table */
-
-#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
-#define _DF1S	0x81	/* DBC 1st byte range 1 start */
-#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
-#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
-#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
-#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
-#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
-#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
-#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
-
-#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
-#define _DF1S	0x81
-#define _DF1E	0xFE
-#define _DS1S	0x40
-#define _DS1E	0x7E
-#define _DS2S	0x80
-#define _DS2E	0xFE
-
-#elif _CODE_PAGE == 949	/* Korean */
-#define _DF1S	0x81
-#define _DF1E	0xFE
-#define _DS1S	0x41
-#define _DS1E	0x5A
-#define _DS2S	0x61
-#define _DS2E	0x7A
-#define _DS3S	0x81
-#define _DS3E	0xFE
-
-#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
-#define _DF1S	0x81
-#define _DF1E	0xFE
-#define _DS1S	0x40
-#define _DS1E	0x7E
-#define _DS2S	0xA1
-#define _DS2E	0xFE
-
-#elif _CODE_PAGE == 437	/* U.S. (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
-				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 720	/* Arabic (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
-				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 737	/* Greek (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
-				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 775	/* Baltic (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
-				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 850	/* Multilingual Latin 1 (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
-				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 852	/* Latin 2 (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
-				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
-
-#elif _CODE_PAGE == 855	/* Cyrillic (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
-				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
-				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 857	/* Turkish (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
-				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 858	/* Multilingual Latin 1 + Euro (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
-				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 862	/* Hebrew (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
-				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 866	/* Russian (OEM) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
-				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 874	/* Thai (OEM, Windows) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
-				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
-				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
-
-#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
-				0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
-
-#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
-				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
-
-#elif _CODE_PAGE == 1253 /* Greek (Windows) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
-				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
-				0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
-
-#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
-				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
-
-#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
-				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
-				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
-
-#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
-				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
-
-#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
-#define _DF1S	0
-#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
-				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
-				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
-
-#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
-#if _USE_LFN
-#error Cannot use LFN feature without valid code page.
-#endif
-#define _DF1S	0
-
-#else
-#error Unknown code page
-
-#endif
-
-
-/* Character code support macros */
-#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
-#define IsLower(c)	(((c)>='a')&&((c)<='z'))
-#define IsDigit(c)	(((c)>='0')&&((c)<='9'))
-
-#if _DF1S		/* Code page is DBCS */
-
-#ifdef _DF2S	/* Two 1st byte areas */
-#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
-#else			/* One 1st byte area */
-#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
-#endif
-
-#ifdef _DS3S	/* Three 2nd byte areas */
-#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
-#else			/* Two 2nd byte areas */
-#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
-#endif
-
-#else			/* Code page is SBCS */
-
-#define IsDBCS1(c)	0
-#define IsDBCS2(c)	0
-
-#endif /* _DF1S */
-
-
-/* Name status flags */
-#define NS			11		/* Index of name status byte in fn[] */
-#define NS_LOSS		0x01	/* Out of 8.3 format */
-#define NS_LFN		0x02	/* Force to create LFN entry */
-#define NS_LAST		0x04	/* Last segment */
-#define NS_BODY		0x08	/* Lower case flag (body) */
-#define NS_EXT		0x10	/* Lower case flag (ext) */
-#define NS_DOT		0x20	/* Dot entry */
-
-
-/* FAT sub-type boundaries */
-/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */
-#define MIN_FAT16	4086	/* Minimum number of clusters for FAT16 */
-#define	MIN_FAT32	65526	/* Minimum number of clusters for FAT32 */
-
-
-/* FatFs refers the members in the FAT structures as byte array instead of
-/ structure member because the structure is not binary compatible between
-/ different platforms */
-
-#define BS_jmpBoot			0	/* Jump instruction (3) */
-#define BS_OEMName			3	/* OEM name (8) */
-#define BPB_BytsPerSec		11	/* Sector size [byte] (2) */
-#define BPB_SecPerClus		13	/* Cluster size [sector] (1) */
-#define BPB_RsvdSecCnt		14	/* Size of reserved area [sector] (2) */
-#define BPB_NumFATs			16	/* Number of FAT copies (1) */
-#define BPB_RootEntCnt		17	/* Number of root dir entries for FAT12/16 (2) */
-#define BPB_TotSec16		19	/* Volume size [sector] (2) */
-#define BPB_Media			21	/* Media descriptor (1) */
-#define BPB_FATSz16			22	/* FAT size [sector] (2) */
-#define BPB_SecPerTrk		24	/* Track size [sector] (2) */
-#define BPB_NumHeads		26	/* Number of heads (2) */
-#define BPB_HiddSec			28	/* Number of special hidden sectors (4) */
-#define BPB_TotSec32		32	/* Volume size [sector] (4) */
-#define BS_DrvNum			36	/* Physical drive number (2) */
-#define BS_BootSig			38	/* Extended boot signature (1) */
-#define BS_VolID			39	/* Volume serial number (4) */
-#define BS_VolLab			43	/* Volume label (8) */
-#define BS_FilSysType		54	/* File system type (1) */
-#define BPB_FATSz32			36	/* FAT size [sector] (4) */
-#define BPB_ExtFlags		40	/* Extended flags (2) */
-#define BPB_FSVer			42	/* File system version (2) */
-#define BPB_RootClus		44	/* Root dir first cluster (4) */
-#define BPB_FSInfo			48	/* Offset of FSInfo sector (2) */
-#define BPB_BkBootSec		50	/* Offset of backup boot sector (2) */
-#define BS_DrvNum32			64	/* Physical drive number (2) */
-#define BS_BootSig32		66	/* Extended boot signature (1) */
-#define BS_VolID32			67	/* Volume serial number (4) */
-#define BS_VolLab32			71	/* Volume label (8) */
-#define BS_FilSysType32		82	/* File system type (1) */
-#define	FSI_LeadSig			0	/* FSI: Leading signature (4) */
-#define	FSI_StrucSig		484	/* FSI: Structure signature (4) */
-#define	FSI_Free_Count		488	/* FSI: Number of free clusters (4) */
-#define	FSI_Nxt_Free		492	/* FSI: Last allocated cluster (4) */
-#define MBR_Table			446	/* MBR: Partition table offset (2) */
-#define	SZ_PTE				16	/* MBR: Size of a partition table entry */
-#define BS_55AA				510	/* Boot sector signature (2) */
-
-#define	DIR_Name			0	/* Short file name (11) */
-#define	DIR_Attr			11	/* Attribute (1) */
-#define	DIR_NTres			12	/* NT flag (1) */
-#define DIR_CrtTimeTenth	13	/* Created time sub-second (1) */
-#define	DIR_CrtTime			14	/* Created time (2) */
-#define	DIR_CrtDate			16	/* Created date (2) */
-#define DIR_LstAccDate		18	/* Last accessed date (2) */
-#define	DIR_FstClusHI		20	/* Higher 16-bit of first cluster (2) */
-#define	DIR_WrtTime			22	/* Modified time (2) */
-#define	DIR_WrtDate			24	/* Modified date (2) */
-#define	DIR_FstClusLO		26	/* Lower 16-bit of first cluster (2) */
-#define	DIR_FileSize		28	/* File size (4) */
-#define	LDIR_Ord			0	/* LFN entry order and LLE flag (1) */
-#define	LDIR_Attr			11	/* LFN attribute (1) */
-#define	LDIR_Type			12	/* LFN type (1) */
-#define	LDIR_Chksum			13	/* Sum of corresponding SFN entry */
-#define	LDIR_FstClusLO		26	/* Filled by zero (0) */
-#define	SZ_DIR				32		/* Size of a directory entry */
-#define	LLE					0x40	/* Last long entry flag in LDIR_Ord */
-#define	DDE					0xE5	/* Deleted directory entry mark in DIR_Name[0] */
-#define	NDDE				0x05	/* Replacement of the character collides with DDE */
-
-
-/*------------------------------------------------------------*/
-/* Module private work area                                   */
-/*------------------------------------------------------------*/
-/* Note that uninitialized variables with static duration are
-/  zeroed/nulled at start-up. If not, the compiler or start-up
-/  routine is out of ANSI-C standard.
-*/
-
-#if _VOLUMES
-static
-FATFS *FatFs[_VOLUMES];	/* Pointer to the file system objects (logical drives) */
-#else
-#error Number of volumes must not be 0.
-#endif
-
-static
-WORD Fsid;				/* File system mount ID */
-
-#if _FS_RPATH
-static
-BYTE CurrVol;			/* Current drive */
-#endif
-
-#if _FS_LOCK
-static
-FILESEM	Files[_FS_LOCK];	/* File lock semaphores */
-#endif
-
-#if _USE_LFN == 0			/* No LFN feature */
-#define	DEF_NAMEBUF			BYTE sfn[12]
-#define INIT_BUF(dobj)		(dobj).fn = sfn
-#define	FREE_BUF()
-
-#elif _USE_LFN == 1			/* LFN feature with static working buffer */
-static WCHAR LfnBuf[_MAX_LFN+1];
-#define	DEF_NAMEBUF			BYTE sfn[12]
-#define INIT_BUF(dobj)		{ (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
-#define	FREE_BUF()
-
-#elif _USE_LFN == 2 		/* LFN feature with dynamic working buffer on the stack */
-#define	DEF_NAMEBUF			BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1]
-#define INIT_BUF(dobj)		{ (dobj).fn = sfn; (dobj).lfn = lbuf; }
-#define	FREE_BUF()
-
-#elif _USE_LFN == 3 		/* LFN feature with dynamic working buffer on the heap */
-#define	DEF_NAMEBUF			BYTE sfn[12]; WCHAR *lfn
-#define INIT_BUF(dobj)		{ lfn = ff_memalloc((_MAX_LFN + 1) * 2); \
-							  if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \
-							  (dobj).lfn = lfn;	(dobj).fn = sfn; }
-#define	FREE_BUF()			ff_memfree(lfn)
-
-#else
-#error Wrong LFN configuration.
-#endif
-
-
-#ifdef _EXCVT
-static
-const BYTE ExCvt[] = _EXCVT;	/* Upper conversion table for extended chars */
-#endif
-
-
-
-
-
-
-/*--------------------------------------------------------------------------
-
-   Module Private Functions
-
----------------------------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------------------*/
-/* String functions                                                      */
-/*-----------------------------------------------------------------------*/
-
-/* Copy memory to memory */
-static
-void mem_cpy (void* dst, const void* src, UINT cnt) {
-	BYTE *d = (BYTE*)dst;
-	const BYTE *s = (const BYTE*)src;
-
-#if _WORD_ACCESS == 1
-	while (cnt >= sizeof (int)) {
-		*(int*)d = *(int*)s;
-		d += sizeof (int); s += sizeof (int);
-		cnt -= sizeof (int);
-	}
-#endif
-	while (cnt--)
-		*d++ = *s++;
-}
-
-/* Fill memory */
-static
-void mem_set (void* dst, int val, UINT cnt) {
-	BYTE *d = (BYTE*)dst;
-
-	while (cnt--)
-		*d++ = (BYTE)val;
-}
-
-/* Compare memory to memory */
-static
-int mem_cmp (const void* dst, const void* src, UINT cnt) {
-	const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
-	int r = 0;
-
-	while (cnt-- && (r = *d++ - *s++) == 0) ;
-	return r;
-}
-
-/* Check if chr is contained in the string */
-static
-int chk_chr (const char* str, int chr) {
-	while (*str && *str != chr) str++;
-	return *str;
-}
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Request/Release grant to access the volume                            */
-/*-----------------------------------------------------------------------*/
-#if _FS_REENTRANT
-
-static
-int lock_fs (
-	FATFS *fs		/* File system object */
-)
-{
-	return ff_req_grant(fs->sobj);
-}
-
-
-static
-void unlock_fs (
-	FATFS *fs,		/* File system object */
-	FRESULT res		/* Result code to be returned */
-)
-{
-	if (fs &&
-		res != FR_NOT_ENABLED &&
-		res != FR_INVALID_DRIVE &&
-		res != FR_INVALID_OBJECT &&
-		res != FR_TIMEOUT) {
-		ff_rel_grant(fs->sobj);
-	}
-}
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* File lock control functions                                           */
-/*-----------------------------------------------------------------------*/
-#if _FS_LOCK
-
-static
-FRESULT chk_lock (	/* Check if the file can be accessed */
-	DIR* dj,		/* Directory object pointing the file to be checked */
-	int acc			/* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
-)
-{
-	UINT i, be;
-
-	/* Search file semaphore table */
-	for (i = be = 0; i < _FS_LOCK; i++) {
-		if (Files[i].fs) {	/* Existing entry */
-			if (Files[i].fs == dj->fs &&	 	/* Check if the file matched with an open file */
-				Files[i].clu == dj->sclust &&
-				Files[i].idx == dj->index) break;
-		} else {			/* Blank entry */
-			be++;
-		}
-	}
-	if (i == _FS_LOCK)	/* The file is not opened */
-		return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES;	/* Is there a blank entry for new file? */
-
-	/* The file has been opened. Reject any open against writing file and all write mode open */
-	return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
-}
-
-
-static
-int enq_lock (void)	/* Check if an entry is available for a new file */
-{
-	UINT i;
-
-	for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
-	return (i == _FS_LOCK) ? 0 : 1;
-}
-
-
-static
-UINT inc_lock (	/* Increment file open counter and returns its index (0:int error) */
-	DIR* dj,	/* Directory object pointing the file to register or increment */
-	int acc		/* Desired access mode (0:Read, !0:Write) */
-)
-{
-	UINT i;
-
-
-	for (i = 0; i < _FS_LOCK; i++) {	/* Find the file */
-		if (Files[i].fs == dj->fs &&
-			Files[i].clu == dj->sclust &&
-			Files[i].idx == dj->index) break;
-	}
-
-	if (i == _FS_LOCK) {				/* Not opened. Register it as new. */
-		for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
-		if (i == _FS_LOCK) return 0;	/* No space to register (int err) */
-		Files[i].fs = dj->fs;
-		Files[i].clu = dj->sclust;
-		Files[i].idx = dj->index;
-		Files[i].ctr = 0;
-	}
-
-	if (acc && Files[i].ctr) return 0;	/* Access violation (int err) */
-
-	Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1;	/* Set semaphore value */
-
-	return i + 1;
-}
-
-
-static
-FRESULT dec_lock (	/* Decrement file open counter */
-	UINT i			/* Semaphore index */
-)
-{
-	WORD n;
-	FRESULT res;
-
-
-	if (--i < _FS_LOCK) {
-		n = Files[i].ctr;
-		if (n == 0x100) n = 0;
-		if (n) n--;
-		Files[i].ctr = n;
-		if (!n) Files[i].fs = 0;
-		res = FR_OK;
-	} else {
-		res = FR_INT_ERR;
-	}
-	return res;
-}
-
-
-static
-void clear_lock (	/* Clear lock entries of the volume */
-	FATFS *fs
-)
-{
-	UINT i;
-
-	for (i = 0; i < _FS_LOCK; i++) {
-		if (Files[i].fs == fs) Files[i].fs = 0;
-	}
-}
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Move/Flush disk access window                                         */
-/*-----------------------------------------------------------------------*/
-
-
-#if !_FS_READONLY
-static
-FRESULT sync_window (
-	FATFS *fs		/* File system object */
-)
-{
-	DWORD wsect;
-	UINT nf;
-
-
-	if (fs->wflag) {	/* Write back the sector if it is dirty */
-		wsect = fs->winsect;	/* Current sector number */
-		if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK)
-			return FR_DISK_ERR;
-		fs->wflag = 0;
-		if (wsect >= fs->fatbase && wsect < (fs->fatbase + fs->fsize)) {	/* In FAT area? */
-			for (nf = fs->n_fats; nf >= 2; nf--) {	/* Reflect the change to all FAT copies */
-				wsect += fs->fsize;
-				disk_write(fs->drv, fs->win, wsect, 1);
-			}
-		}
-	}
-	return FR_OK;
-}
-#endif
-
-
-static
-FRESULT move_window (
-	FATFS *fs,		/* File system object */
-	DWORD sector	/* Sector number to make appearance in the fs->win[] */
-)
-{
-	if (sector != fs->winsect) {	/* Changed current window */
-#if !_FS_READONLY
-		if (sync_window(fs) != FR_OK)
-			return FR_DISK_ERR;
-#endif
-		if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK)
-			return FR_DISK_ERR;
-		fs->winsect = sector;
-	}
-
-	return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Synchronize file system and strage device                             */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-FRESULT sync_fs (	/* FR_OK: successful, FR_DISK_ERR: failed */
-	FATFS *fs		/* File system object */
-)
-{
-	FRESULT res;
-
-
-	res = sync_window(fs);
-	if (res == FR_OK) {
-		/* Update FSInfo sector if needed */
-		if (fs->fs_type == FS_FAT32 && fs->fsi_flag) {
-			fs->winsect = 0;
-			/* Create FSInfo structure */
-			mem_set(fs->win, 0, 512);
-			ST_WORD(fs->win+BS_55AA, 0xAA55);
-			ST_DWORD(fs->win+FSI_LeadSig, 0x41615252);
-			ST_DWORD(fs->win+FSI_StrucSig, 0x61417272);
-			ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust);
-			ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust);
-			/* Write it into the FSInfo sector */
-			disk_write(fs->drv, fs->win, fs->fsi_sector, 1);
-			fs->fsi_flag = 0;
-		}
-		/* Make sure that no pending write process in the physical drive */
-		if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK)
-			res = FR_DISK_ERR;
-	}
-
-	return res;
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Get sector# from cluster#                                             */
-/*-----------------------------------------------------------------------*/
-
-
-DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
-	FATFS *fs,		/* File system object */
-	DWORD clst		/* Cluster# to be converted */
-)
-{
-	clst -= 2;
-	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
-	return clst * fs->csize + fs->database;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT access - Read value of a FAT entry                                */
-/*-----------------------------------------------------------------------*/
-
-
-DWORD get_fat (	/* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */
-	FATFS *fs,	/* File system object */
-	DWORD clst	/* Cluster# to get the link information */
-)
-{
-	UINT wc, bc;
-	BYTE *p;
-
-
-	if (clst < 2 || clst >= fs->n_fatent)	/* Check range */
-		return 1;
-
-	switch (fs->fs_type) {
-	case FS_FAT12 :
-		bc = (UINT)clst; bc += bc / 2;
-		if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
-		wc = fs->win[bc % SS(fs)]; bc++;
-		if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
-		wc |= fs->win[bc % SS(fs)] << 8;
-		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
-
-	case FS_FAT16 :
-		if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break;
-		p = &fs->win[clst * 2 % SS(fs)];
-		return LD_WORD(p);
-
-	case FS_FAT32 :
-		if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break;
-		p = &fs->win[clst * 4 % SS(fs)];
-		return LD_DWORD(p) & 0x0FFFFFFF;
-	}
-
-	return 0xFFFFFFFF;	/* An error occurred at the disk I/O layer */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT access - Change value of a FAT entry                              */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-
-FRESULT put_fat (
-	FATFS *fs,	/* File system object */
-	DWORD clst,	/* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */
-	DWORD val	/* New value to mark the cluster */
-)
-{
-	UINT bc;
-	BYTE *p;
-	FRESULT res;
-
-
-	if (clst < 2 || clst >= fs->n_fatent) {	/* Check range */
-		res = FR_INT_ERR;
-
-	} else {
-		switch (fs->fs_type) {
-		case FS_FAT12 :
-			bc = (UINT)clst; bc += bc / 2;
-			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
-			if (res != FR_OK) break;
-			p = &fs->win[bc % SS(fs)];
-			*p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
-			bc++;
-			fs->wflag = 1;
-			res = move_window(fs, fs->fatbase + (bc / SS(fs)));
-			if (res != FR_OK) break;
-			p = &fs->win[bc % SS(fs)];
-			*p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
-			break;
-
-		case FS_FAT16 :
-			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
-			if (res != FR_OK) break;
-			p = &fs->win[clst * 2 % SS(fs)];
-			ST_WORD(p, (WORD)val);
-			break;
-
-		case FS_FAT32 :
-			res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
-			if (res != FR_OK) break;
-			p = &fs->win[clst * 4 % SS(fs)];
-			val |= LD_DWORD(p) & 0xF0000000;
-			ST_DWORD(p, val);
-			break;
-
-		default :
-			res = FR_INT_ERR;
-		}
-		fs->wflag = 1;
-	}
-
-	return res;
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT handling - Remove a cluster chain                                 */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-FRESULT remove_chain (
-	FATFS *fs,			/* File system object */
-	DWORD clst			/* Cluster# to remove a chain from */
-)
-{
-	FRESULT res;
-	DWORD nxt;
-#if _USE_ERASE
-	DWORD scl = clst, ecl = clst, rt[2];
-#endif
-
-	if (clst < 2 || clst >= fs->n_fatent) {	/* Check range */
-		res = FR_INT_ERR;
-
-	} else {
-		res = FR_OK;
-		while (clst < fs->n_fatent) {			/* Not a last link? */
-			nxt = get_fat(fs, clst);			/* Get cluster status */
-			if (nxt == 0) break;				/* Empty cluster? */
-			if (nxt == 1) { res = FR_INT_ERR; break; }	/* Internal error? */
-			if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }	/* Disk error? */
-			res = put_fat(fs, clst, 0);			/* Mark the cluster "empty" */
-			if (res != FR_OK) break;
-			if (fs->free_clust != 0xFFFFFFFF) {	/* Update FSInfo */
-				fs->free_clust++;
-				fs->fsi_flag = 1;
-			}
-#if _USE_ERASE
-			if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
-				ecl = nxt;
-			} else {				/* End of contiguous clusters */
-				rt[0] = clust2sect(fs, scl);					/* Start sector */
-				rt[1] = clust2sect(fs, ecl) + fs->csize - 1;	/* End sector */
-				disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt);		/* Erase the block */
-				scl = ecl = nxt;
-			}
-#endif
-			clst = nxt;	/* Next cluster */
-		}
-	}
-
-	return res;
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT handling - Stretch or Create a cluster chain                      */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-DWORD create_chain (	/* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
-	FATFS *fs,			/* File system object */
-	DWORD clst			/* Cluster# to stretch. 0 means create a new chain. */
-)
-{
-	DWORD cs, ncl, scl;
-	FRESULT res;
-
-
-	if (clst == 0) {		/* Create a new chain */
-		scl = fs->last_clust;			/* Get suggested start point */
-		if (!scl || scl >= fs->n_fatent) scl = 1;
-	}
-	else {					/* Stretch the current chain */
-		cs = get_fat(fs, clst);			/* Check the cluster status */
-		if (cs < 2) return 1;			/* It is an invalid cluster */
-		if (cs < fs->n_fatent) return cs;	/* It is already followed by next cluster */
-		scl = clst;
-	}
-
-	ncl = scl;				/* Start cluster */
-	for (;;) {
-		ncl++;							/* Next cluster */
-		if (ncl >= fs->n_fatent) {		/* Wrap around */
-			ncl = 2;
-			if (ncl > scl) return 0;	/* No free cluster */
-		}
-		cs = get_fat(fs, ncl);			/* Get the cluster status */
-		if (cs == 0) break;				/* Found a free cluster */
-		if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */
-			return cs;
-		if (ncl == scl) return 0;		/* No free cluster */
-	}
-
-	res = put_fat(fs, ncl, 0x0FFFFFFF);	/* Mark the new cluster "last link" */
-	if (res == FR_OK && clst != 0) {
-		res = put_fat(fs, clst, ncl);	/* Link it to the previous one if needed */
-	}
-	if (res == FR_OK) {
-		fs->last_clust = ncl;			/* Update FSINFO */
-		if (fs->free_clust != 0xFFFFFFFF) {
-			fs->free_clust--;
-			fs->fsi_flag = 1;
-		}
-	} else {
-		ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;
-	}
-
-	return ncl;		/* Return new cluster number or error code */
-}
-#endif /* !_FS_READONLY */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* FAT handling - Convert offset into cluster with link map table        */
-/*-----------------------------------------------------------------------*/
-
-#if _USE_FASTSEEK
-static
-DWORD clmt_clust (	/* <2:Error, >=2:Cluster number */
-	FIL* fp,		/* Pointer to the file object */
-	DWORD ofs		/* File offset to be converted to cluster# */
-)
-{
-	DWORD cl, ncl, *tbl;
-
-
-	tbl = fp->cltbl + 1;	/* Top of CLMT */
-	cl = ofs / SS(fp->fs) / fp->fs->csize;	/* Cluster order from top of the file */
-	for (;;) {
-		ncl = *tbl++;			/* Number of cluters in the fragment */
-		if (!ncl) return 0;		/* End of table? (error) */
-		if (cl < ncl) break;	/* In this fragment? */
-		cl -= ncl; tbl++;		/* Next fragment */
-	}
-	return cl + *tbl;	/* Return the cluster number */
-}
-#endif	/* _USE_FASTSEEK */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Set directory index                              */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT dir_sdi (
-	DIR *dj,		/* Pointer to directory object */
-	WORD idx		/* Index of directory table */
-)
-{
-	DWORD clst;
-	WORD ic;
-
-
-	dj->index = idx;
-	clst = dj->sclust;
-	if (clst == 1 || clst >= dj->fs->n_fatent)	/* Check start cluster range */
-		return FR_INT_ERR;
-	if (!clst && dj->fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
-		clst = dj->fs->dirbase;
-
-	if (clst == 0) {	/* Static table (root-dir in FAT12/16) */
-		dj->clust = clst;
-		if (idx >= dj->fs->n_rootdir)		/* Index is out of range */
-			return FR_INT_ERR;
-		dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / SZ_DIR);	/* Sector# */
-	}
-	else {				/* Dynamic table (sub-dirs or root-dir in FAT32) */
-		ic = SS(dj->fs) / SZ_DIR * dj->fs->csize;	/* Entries per cluster */
-		while (idx >= ic) {	/* Follow cluster chain */
-			clst = get_fat(dj->fs, clst);				/* Get next cluster */
-			if (clst == 0xFFFFFFFF) return FR_DISK_ERR;	/* Disk error */
-			if (clst < 2 || clst >= dj->fs->n_fatent)	/* Reached to end of table or int error */
-				return FR_INT_ERR;
-			idx -= ic;
-		}
-		dj->clust = clst;
-		dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / SZ_DIR);	/* Sector# */
-	}
-
-	dj->dir = dj->fs->win + (idx % (SS(dj->fs) / SZ_DIR)) * SZ_DIR;	/* Ptr to the entry in the sector */
-
-	return FR_OK;	/* Seek succeeded */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Move directory table index next                  */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
-	DIR *dj,		/* Pointer to the directory object */
-	int stretch		/* 0: Do not stretch table, 1: Stretch table if needed */
-)
-{
-	DWORD clst;
-	WORD i;
-
-
-	stretch = stretch;		/* To suppress warning on read-only cfg. */
-	i = dj->index + 1;
-	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
-		return FR_NO_FILE;
-
-	if (!(i % (SS(dj->fs) / SZ_DIR))) {	/* Sector changed? */
-		dj->sect++;					/* Next sector */
-
-		if (dj->clust == 0) {	/* Static table */
-			if (i >= dj->fs->n_rootdir)	/* Report EOT when end of table */
-				return FR_NO_FILE;
-		}
-		else {					/* Dynamic table */
-			if (((i / (SS(dj->fs) / SZ_DIR)) & (dj->fs->csize - 1)) == 0) {	/* Cluster changed? */
-				clst = get_fat(dj->fs, dj->clust);				/* Get next cluster */
-				if (clst <= 1) return FR_INT_ERR;
-				if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
-				if (clst >= dj->fs->n_fatent) {					/* When it reached end of dynamic table */
-#if !_FS_READONLY
-					BYTE c;
-					if (!stretch) return FR_NO_FILE;			/* When do not stretch, report EOT */
-					clst = create_chain(dj->fs, dj->clust);		/* Stretch cluster chain */
-					if (clst == 0) return FR_DENIED;			/* No free cluster */
-					if (clst == 1) return FR_INT_ERR;
-					if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
-					/* Clean-up stretched table */
-					if (sync_window(dj->fs)) return FR_DISK_ERR;	/* Flush active window */
-					mem_set(dj->fs->win, 0, SS(dj->fs));			/* Clear window buffer */
-					dj->fs->winsect = clust2sect(dj->fs, clst);	/* Cluster start sector */
-					for (c = 0; c < dj->fs->csize; c++) {		/* Fill the new cluster with 0 */
-						dj->fs->wflag = 1;
-						if (sync_window(dj->fs)) return FR_DISK_ERR;
-						dj->fs->winsect++;
-					}
-					dj->fs->winsect -= c;						/* Rewind window address */
-#else
-					return FR_NO_FILE;			/* Report EOT */
-#endif
-				}
-				dj->clust = clst;				/* Initialize data for new cluster */
-				dj->sect = clust2sect(dj->fs, clst);
-			}
-		}
-	}
-
-	dj->index = i;
-	dj->dir = dj->fs->win + (i % (SS(dj->fs) / SZ_DIR)) * SZ_DIR;
-
-	return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Reserve directory entry                          */
-/*-----------------------------------------------------------------------*/
-
-#if !_FS_READONLY
-static
-FRESULT dir_alloc (
-	DIR* dj,	/* Pointer to the directory object */
-	UINT nent	/* Number of contiguous entries to allocate (1-21) */
-)
-{
-	FRESULT res;
-	UINT n;
-
-
-	res = dir_sdi(dj, 0);
-	if (res == FR_OK) {
-		n = 0;
-		do {
-			res = move_window(dj->fs, dj->sect);
-			if (res != FR_OK) break;
-			if (dj->dir[0] == DDE || dj->dir[0] == 0) {	/* Is it a blank entry? */
-				if (++n == nent) break;	/* A block of contiguous entry is found */
-			} else {
-				n = 0;					/* Not a blank entry. Restart to search */
-			}
-			res = dir_next(dj, 1);		/* Next entry with table stretch enabled */
-		} while (res == FR_OK);
-	}
-	return res;
-}
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Load/Store start cluster number                  */
-/*-----------------------------------------------------------------------*/
-
-static
-DWORD ld_clust (
-	FATFS *fs,	/* Pointer to the fs object */
-	BYTE *dir	/* Pointer to the directory entry */
-)
-{
-	DWORD cl;
-
-	cl = LD_WORD(dir+DIR_FstClusLO);
-	if (fs->fs_type == FS_FAT32)
-		cl |= (DWORD)LD_WORD(dir+DIR_FstClusHI) << 16;
-
-	return cl;
-}
-
-
-#if !_FS_READONLY
-static
-void st_clust (
-	BYTE *dir,	/* Pointer to the directory entry */
-	DWORD cl	/* Value to be set */
-)
-{
-	ST_WORD(dir+DIR_FstClusLO, cl);
-	ST_WORD(dir+DIR_FstClusHI, cl >> 16);
-}
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry   */
-/*-----------------------------------------------------------------------*/
-#if _USE_LFN
-static
-const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30};	/* Offset of LFN chars in the directory entry */
-
-
-static
-int cmp_lfn (			/* 1:Matched, 0:Not matched */
-	WCHAR *lfnbuf,		/* Pointer to the LFN to be compared */
-	BYTE *dir			/* Pointer to the directory entry containing a part of LFN */
-)
-{
-	UINT i, s;
-	WCHAR wc, uc;
-
-
-	i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13;	/* Get offset in the LFN buffer */
-	s = 0; wc = 1;
-	do {
-		uc = LD_WORD(dir+LfnOfs[s]);	/* Pick an LFN character from the entry */
-		if (wc) {	/* Last char has not been processed */
-			wc = ff_wtoupper(uc);		/* Convert it to upper case */
-			if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++]))	/* Compare it */
-				return 0;				/* Not matched */
-		} else {
-			if (uc != 0xFFFF) return 0;	/* Check filler */
-		}
-	} while (++s < 13);				/* Repeat until all chars in the entry are checked */
-
-	if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i])	/* Last segment matched but different length */
-		return 0;
-
-	return 1;						/* The part of LFN matched */
-}
-
-
-
-static
-int pick_lfn (			/* 1:Succeeded, 0:Buffer overflow */
-	WCHAR *lfnbuf,		/* Pointer to the Unicode-LFN buffer */
-	BYTE *dir			/* Pointer to the directory entry */
-)
-{
-	UINT i, s;
-	WCHAR wc, uc;
-
-
-	i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13;	/* Offset in the LFN buffer */
-
-	s = 0; wc = 1;
-	do {
-		uc = LD_WORD(dir+LfnOfs[s]);		/* Pick an LFN character from the entry */
-		if (wc) {	/* Last char has not been processed */
-			if (i >= _MAX_LFN) return 0;	/* Buffer overflow? */
-			lfnbuf[i++] = wc = uc;			/* Store it */
-		} else {
-			if (uc != 0xFFFF) return 0;		/* Check filler */
-		}
-	} while (++s < 13);						/* Read all character in the entry */
-
-	if (dir[LDIR_Ord] & LLE) {				/* Put terminator if it is the last LFN part */
-		if (i >= _MAX_LFN) return 0;		/* Buffer overflow? */
-		lfnbuf[i] = 0;
-	}
-
-	return 1;
-}
-
-
-#if !_FS_READONLY
-static
-void fit_lfn (
-	const WCHAR *lfnbuf,	/* Pointer to the LFN buffer */
-	BYTE *dir,				/* Pointer to the directory entry */
-	BYTE ord,				/* LFN order (1-20) */
-	BYTE sum				/* SFN sum */
-)
-{
-	UINT i, s;
-	WCHAR wc;
-
-
-	dir[LDIR_Chksum] = sum;			/* Set check sum */
-	dir[LDIR_Attr] = AM_LFN;		/* Set attribute. LFN entry */
-	dir[LDIR_Type] = 0;
-	ST_WORD(dir+LDIR_FstClusLO, 0);
-
-	i = (ord - 1) * 13;				/* Get offset in the LFN buffer */
-	s = wc = 0;
-	do {
-		if (wc != 0xFFFF) wc = lfnbuf[i++];	/* Get an effective char */
-		ST_WORD(dir+LfnOfs[s], wc);	/* Put it */
-		if (!wc) wc = 0xFFFF;		/* Padding chars following last char */
-	} while (++s < 13);
-	if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE;	/* Bottom LFN part is the start of LFN sequence */
-	dir[LDIR_Ord] = ord;			/* Set the LFN order */
-}
-
-#endif
-#endif
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Create numbered name                                                  */
-/*-----------------------------------------------------------------------*/
-#if _USE_LFN
-void gen_numname (
-	BYTE *dst,			/* Pointer to generated SFN */
-	const BYTE *src,	/* Pointer to source SFN to be modified */
-	const WCHAR *lfn,	/* Pointer to LFN */
-	WORD seq			/* Sequence number */
-)
-{
-	BYTE ns[8], c;
-	UINT i, j;
-
-
-	mem_cpy(dst, src, 11);
-
-	if (seq > 5) {	/* On many collisions, generate a hash number instead of sequential number */
-		do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn);
-	}
-
-	/* itoa (hexdecimal) */
-	i = 7;
-	do {
-		c = (seq % 16) + '0';
-		if (c > '9') c += 7;
-		ns[i--] = c;
-		seq /= 16;
-	} while (seq);
-	ns[i] = '~';
-
-	/* Append the number */
-	for (j = 0; j < i && dst[j] != ' '; j++) {
-		if (IsDBCS1(dst[j])) {
-			if (j == i - 1) break;
-			j++;
-		}
-	}
-	do {
-		dst[j++] = (i < 8) ? ns[i++] : ' ';
-	} while (j < 8);
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Calculate sum of an SFN                                               */
-/*-----------------------------------------------------------------------*/
-#if _USE_LFN
-static
-BYTE sum_sfn (
-	const BYTE *dir		/* Ptr to directory entry */
-)
-{
-	BYTE sum = 0;
-	UINT n = 11;
-
-	do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n);
-	return sum;
-}
-#endif
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Directory handling - Find an object in the directory                  */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT dir_find (
-	DIR *dj			/* Pointer to the directory object linked to the file name */
-)
-{
-	FRESULT res;
-	BYTE c, *dir;
-#if _USE_LFN
-	BYTE a, ord, sum;
-#endif
-
-	res = dir_sdi(dj, 0);			/* Rewind directory object */
-	if (res != FR_OK) return res;
-
-#if _USE_LFN
-	ord = sum = 0xFF;
-#endif
-	do {
-		res = move_window(dj->fs, dj->sect);
-		if (res != FR_OK) break;
-		dir = dj->dir;					/* Ptr to the directory entry of current index */
-		c = dir[DIR_Name];
-		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
-#if _USE_LFN	/* LFN configuration */
-		a = dir[DIR_Attr] & AM_MASK;
-		if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) {	/* An entry without valid data */
-			ord = 0xFF;
-		} else {
-			if (a == AM_LFN) {			/* An LFN entry is found */
-				if (dj->lfn) {
-					if (c & LLE) {		/* Is it start of LFN sequence? */
-						sum = dir[LDIR_Chksum];
-						c &= ~LLE; ord = c;	/* LFN start order */
-						dj->lfn_idx = dj->index;
-					}
-					/* Check validity of the LFN entry and compare it with given name */
-					ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
-				}
-			} else {					/* An SFN entry is found */
-				if (!ord && sum == sum_sfn(dir)) break;	/* LFN matched? */
-				ord = 0xFF; dj->lfn_idx = 0xFFFF;	/* Reset LFN sequence */
-				if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break;	/* SFN matched? */
-			}
-		}
-#else		/* Non LFN configuration */
-		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
-			break;
-#endif
-		res = dir_next(dj, 0);		/* Next entry */
-	} while (res == FR_OK);
-
-	return res;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read an object from the directory                                     */
-/*-----------------------------------------------------------------------*/
-#if _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2
-static
-FRESULT dir_read (
-	DIR *dj,		/* Pointer to the directory object */
-	int vol			/* Filtered by 0:file/dir or 1:volume label */
-)
-{
-	FRESULT res;
-	BYTE a, c, *dir;
-#if _USE_LFN
-	BYTE ord = 0xFF, sum = 0xFF;
-#endif
-
-	res = FR_NO_FILE;
-	while (dj->sect) {
-		res = move_window(dj->fs, dj->sect);
-		if (res != FR_OK) break;
-		dir = dj->dir;					/* Ptr to the directory entry of current index */
-		c = dir[DIR_Name];
-		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
-		a = dir[DIR_Attr] & AM_MASK;
-#if _USE_LFN	/* LFN configuration */
-		if (c == DDE || (!_FS_RPATH && c == '.') || (a == AM_VOL) != vol) {	/* An entry without valid data */
-			ord = 0xFF;
-		} else {
-			if (a == AM_LFN) {			/* An LFN entry is found */
-				if (c & LLE) {			/* Is it start of LFN sequence? */
-					sum = dir[LDIR_Chksum];
-					c &= ~LLE; ord = c;
-					dj->lfn_idx = dj->index;
-				}
-				/* Check LFN validity and capture it */
-				ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
-			} else {					/* An SFN entry is found */
-				if (ord || sum != sum_sfn(dir))	/* Is there a valid LFN? */
-					dj->lfn_idx = 0xFFFF;		/* It has no LFN. */
-				break;
-			}
-		}
-#else		/* Non LFN configuration */
-		if (c != DDE && (_FS_RPATH || c != '.') && a != AM_LFN && (a == AM_VOL) == vol)	/* Is it a valid entry? */
-			break;
-#endif
-		res = dir_next(dj, 0);				/* Next entry */
-		if (res != FR_OK) break;
-	}
-
-	if (res != FR_OK) dj->sect = 0;
-
-	return res;
-}
-#endif	/* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Register an object to the directory                                   */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY
-static
-FRESULT dir_register (	/* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */
-	DIR *dj				/* Target directory with object name to be created */
-)
-{
-	FRESULT res;
-#if _USE_LFN	/* LFN configuration */
-	WORD n, ne;
-	BYTE sn[12], *fn, sum;
-	WCHAR *lfn;
-
-
-	fn = dj->fn; lfn = dj->lfn;
-	mem_cpy(sn, fn, 12);
-
-	if (_FS_RPATH && (sn[NS] & NS_DOT))		/* Cannot create dot entry */
-		return FR_INVALID_NAME;
-
-	if (sn[NS] & NS_LOSS) {			/* When LFN is out of 8.3 format, generate a numbered name */
-		fn[NS] = 0; dj->lfn = 0;			/* Find only SFN */
-		for (n = 1; n < 100; n++) {
-			gen_numname(fn, sn, lfn, n);	/* Generate a numbered name */
-			res = dir_find(dj);				/* Check if the name collides with existing SFN */
-			if (res != FR_OK) break;
-		}
-		if (n == 100) return FR_DENIED;		/* Abort if too many collisions */
-		if (res != FR_NO_FILE) return res;	/* Abort if the result is other than 'not collided' */
-		fn[NS] = sn[NS]; dj->lfn = lfn;
-	}
-
-	if (sn[NS] & NS_LFN) {			/* When LFN is to be created, allocate entries for an SFN + LFNs. */
-		for (n = 0; lfn[n]; n++) ;
-		ne = (n + 25) / 13;
-	} else {						/* Otherwise allocate an entry for an SFN  */
-		ne = 1;
-	}
-	res = dir_alloc(dj, ne);		/* Allocate entries */
-
-	if (res == FR_OK && --ne) {		/* Set LFN entry if needed */
-		res = dir_sdi(dj, (WORD)(dj->index - ne));
-		if (res == FR_OK) {
-			sum = sum_sfn(dj->fn);	/* Sum value of the SFN tied to the LFN */
-			do {					/* Store LFN entries in bottom first */
-				res = move_window(dj->fs, dj->sect);
-				if (res != FR_OK) break;
-				fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum);
-				dj->fs->wflag = 1;
-				res = dir_next(dj, 0);	/* Next entry */
-			} while (res == FR_OK && --ne);
-		}
-	}
-#else	/* Non LFN configuration */
-	res = dir_alloc(dj, 1);		/* Allocate an entry for SFN */
-#endif
-
-	if (res == FR_OK) {				/* Set SFN entry */
-		res = move_window(dj->fs, dj->sect);
-		if (res == FR_OK) {
-			mem_set(dj->dir, 0, SZ_DIR);	/* Clean the entry */
-			mem_cpy(dj->dir, dj->fn, 11);	/* Put SFN */
-#if _USE_LFN
-			dj->dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT);	/* Put NT flag */
-#endif
-			dj->fs->wflag = 1;
-		}
-	}
-
-	return res;
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Remove an object from the directory                                   */
-/*-----------------------------------------------------------------------*/
-#if !_FS_READONLY && !_FS_MINIMIZE
-static
-FRESULT dir_remove (	/* FR_OK: Successful, FR_DISK_ERR: A disk error */
-	DIR *dj				/* Directory object pointing the entry to be removed */
-)
-{
-	FRESULT res;
-#if _USE_LFN	/* LFN configuration */
-	WORD i;
-
-	i = dj->index;	/* SFN index */
-	res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx));	/* Goto the SFN or top of the LFN entries */
-	if (res == FR_OK) {
-		do {
-			res = move_window(dj->fs, dj->sect);
-			if (res != FR_OK) break;
-			*dj->dir = DDE;			/* Mark the entry "deleted" */
-			dj->fs->wflag = 1;
-			if (dj->index >= i) break;	/* When reached SFN, all entries of the object has been deleted. */
-			res = dir_next(dj, 0);		/* Next entry */
-		} while (res == FR_OK);
-		if (res == FR_NO_FILE) res = FR_INT_ERR;
-	}
-
-#else			/* Non LFN configuration */
-	res = dir_sdi(dj, dj->index);
-	if (res == FR_OK) {
-		res = move_window(dj->fs, dj->sect);
-		if (res == FR_OK) {
-			*dj->dir = DDE;			/* Mark the entry "deleted" */
-			dj->fs->wflag = 1;
-		}
-	}
-#endif
-
-	return res;
-}
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Pick a segment and create the object name in directory form           */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT create_name (
-	DIR *dj,			/* Pointer to the directory object */
-	const TCHAR **path	/* Pointer to pointer to the segment in the path string */
-)
-{
-#if _USE_LFN	/* LFN configuration */
-	BYTE b, cf;
-	WCHAR w, *lfn;
-	UINT i, ni, si, di;
-	const TCHAR *p;
-
-	/* Create LFN in Unicode */
-	for (p = *path; *p == '/' || *p == '\\'; p++) ;	/* Strip duplicated separator */
-	lfn = dj->lfn;
-	si = di = 0;
-	for (;;) {
-		w = p[si++];					/* Get a character */
-		if (w < ' ' || w == '/' || w == '\\') break;	/* Break on end of segment */
-		if (di >= _MAX_LFN)				/* Reject too long name */
-			return FR_INVALID_NAME;
-#if !_LFN_UNICODE
-		w &= 0xFF;
-		if (IsDBCS1(w)) {				/* Check if it is a DBC 1st byte (always false on SBCS cfg) */
-			b = (BYTE)p[si++];			/* Get 2nd byte */
-			if (!IsDBCS2(b))
-				return FR_INVALID_NAME;	/* Reject invalid sequence */
-			w = (w << 8) + b;			/* Create a DBC */
-		}
-		w = ff_convert(w, 1);			/* Convert ANSI/OEM to Unicode */
-		if (!w) return FR_INVALID_NAME;	/* Reject invalid code */
-#endif
-		if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */
-			return FR_INVALID_NAME;
-		lfn[di++] = w;					/* Store the Unicode char */
-	}
-	*path = &p[si];						/* Return pointer to the next segment */
-	cf = (w < ' ') ? NS_LAST : 0;		/* Set last segment flag if end of path */
-#if _FS_RPATH
-	if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */
-		(di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) {
-		lfn[di] = 0;
-		for (i = 0; i < 11; i++)
-			dj->fn[i] = (i < di) ? '.' : ' ';
-		dj->fn[i] = cf | NS_DOT;		/* This is a dot entry */
-		return FR_OK;
-	}
-#endif
-	while (di) {						/* Strip trailing spaces and dots */
-		w = lfn[di-1];
-		if (w != ' ' && w != '.') break;
-		di--;
-	}
-	if (!di) return FR_INVALID_NAME;	/* Reject nul string */
-
-	lfn[di] = 0;						/* LFN is created */
-
-	/* Create SFN in directory form */
-	mem_set(dj->fn, ' ', 11);
-	for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ;	/* Strip leading spaces and dots */
-	if (si) cf |= NS_LOSS | NS_LFN;
-	while (di && lfn[di - 1] != '.') di--;	/* Find extension (di<=si: no extension) */
-
-	b = i = 0; ni = 8;
-	for (;;) {
-		w = lfn[si++];					/* Get an LFN char */
-		if (!w) break;					/* Break on end of the LFN */
-		if (w == ' ' || (w == '.' && si != di)) {	/* Remove spaces and dots */
-			cf |= NS_LOSS | NS_LFN; continue;
-		}
-
-		if (i >= ni || si == di) {		/* Extension or end of SFN */
-			if (ni == 11) {				/* Long extension */
-				cf |= NS_LOSS | NS_LFN; break;
-			}
-			if (si != di) cf |= NS_LOSS | NS_LFN;	/* Out of 8.3 format */
-			if (si > di) break;			/* No extension */
-			si = di; i = 8; ni = 11;	/* Enter extension section */
-			b <<= 2; continue;
-		}
-
-		if (w >= 0x80) {				/* Non ASCII char */
-#ifdef _EXCVT
-			w = ff_convert(w, 0);		/* Unicode -> OEM code */
-			if (w) w = ExCvt[w - 0x80];	/* Convert extended char to upper (SBCS) */
-#else
-			w = ff_convert(ff_wtoupper(w), 0);	/* Upper converted Unicode -> OEM code */
-#endif
-			cf |= NS_LFN;				/* Force create LFN entry */
-		}
-
-		if (_DF1S && w >= 0x100) {		/* Double byte char (always false on SBCS cfg) */
-			if (i >= ni - 1) {
-				cf |= NS_LOSS | NS_LFN; i = ni; continue;
-			}
-			dj->fn[i++] = (BYTE)(w >> 8);
-		} else {						/* Single byte char */
-			if (!w || chk_chr("+,;=[]", w)) {	/* Replace illegal chars for SFN */
-				w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
-			} else {
-				if (IsUpper(w)) {		/* ASCII large capital */
-					b |= 2;
-				} else {
-					if (IsLower(w)) {	/* ASCII small capital */
-						b |= 1; w -= 0x20;
-					}
-				}
-			}
-		}
-		dj->fn[i++] = (BYTE)w;
-	}
-
-	if (dj->fn[0] == DDE) dj->fn[0] = NDDE;	/* If the first char collides with deleted mark, replace it with 0x05 */
-
-	if (ni == 8) b <<= 2;
-	if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03)	/* Create LFN entry when there are composite capitals */
-		cf |= NS_LFN;
-	if (!(cf & NS_LFN)) {						/* When LFN is in 8.3 format without extended char, NT flags are created */
-		if ((b & 0x03) == 0x01) cf |= NS_EXT;	/* NT flag (Extension has only small capital) */
-		if ((b & 0x0C) == 0x04) cf |= NS_BODY;	/* NT flag (Filename has only small capital) */
-	}
-
-	dj->fn[NS] = cf;	/* SFN is created */
-
-	return FR_OK;
-
-
-#else	/* Non-LFN configuration */
-	BYTE b, c, d, *sfn;
-	UINT ni, si, i;
-	const char *p;
-
-	/* Create file name in directory form */
-	for (p = *path; *p == '/' || *p == '\\'; p++) ;	/* Strip duplicated separator */
-	sfn = dj->fn;
-	mem_set(sfn, ' ', 11);
-	si = i = b = 0; ni = 8;
-#if _FS_RPATH
-	if (p[si] == '.') { /* Is this a dot entry? */
-		for (;;) {
-			c = (BYTE)p[si++];
-			if (c != '.' || si >= 3) break;
-			sfn[i++] = c;
-		}
-		if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
-		*path = &p[si];									/* Return pointer to the next segment */
-		sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT;	/* Set last segment flag if end of path */
-		return FR_OK;
-	}
-#endif
-	for (;;) {
-		c = (BYTE)p[si++];
-		if (c <= ' ' || c == '/' || c == '\\') break;	/* Break on end of segment */
-		if (c == '.' || i >= ni) {
-			if (ni != 8 || c != '.') return FR_INVALID_NAME;
-			i = 8; ni = 11;
-			b <<= 2; continue;
-		}
-		if (c >= 0x80) {				/* Extended char? */
-			b |= 3;						/* Eliminate NT flag */
-#ifdef _EXCVT
-			c = ExCvt[c - 0x80];		/* To upper extended chars (SBCS cfg) */
-#else
-#if !_DF1S
-			return FR_INVALID_NAME;		/* Reject extended chars (ASCII cfg) */
-#endif
-#endif
-		}
-		if (IsDBCS1(c)) {				/* Check if it is a DBC 1st byte (always false on SBCS cfg) */
-			d = (BYTE)p[si++];			/* Get 2nd byte */
-			if (!IsDBCS2(d) || i >= ni - 1)	/* Reject invalid DBC */
-				return FR_INVALID_NAME;
-			sfn[i++] = c;
-			sfn[i++] = d;
-		} else {						/* Single byte code */
-			if (chk_chr("\"*+,:;<=>\?[]|\x7F", c))	/* Reject illegal chrs for SFN */
-				return FR_INVALID_NAME;
-			if (IsUpper(c)) {			/* ASCII large capital? */
-				b |= 2;
-			} else {
-				if (IsLower(c)) {		/* ASCII small capital? */
-					b |= 1; c -= 0x20;
-				}
-			}
-			sfn[i++] = c;
-		}
-	}
-	*path = &p[si];						/* Return pointer to the next segment */
-	c = (c <= ' ') ? NS_LAST : 0;		/* Set last segment flag if end of path */
-
-	if (!i) return FR_INVALID_NAME;		/* Reject nul string */
-	if (sfn[0] == DDE) sfn[0] = NDDE;	/* When first char collides with DDE, replace it with 0x05 */
-
-	if (ni == 8) b <<= 2;
-	if ((b & 0x03) == 0x01) c |= NS_EXT;	/* NT flag (Name extension has only small capital) */
-	if ((b & 0x0C) == 0x04) c |= NS_BODY;	/* NT flag (Name body has only small capital) */
-
-	sfn[NS] = c;		/* Store NT flag, File name is created */
-
-	return FR_OK;
-#endif
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Get file information from directory entry                             */
-/*-----------------------------------------------------------------------*/
-#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2
-static
-void get_fileinfo (		/* No return code */
-	DIR *dj,			/* Pointer to the directory object */
-	FILINFO *fno	 	/* Pointer to the file information to be filled */
-)
-{
-	UINT i;
-	BYTE nt, *dir;
-	TCHAR *p, c;
-
-
-	p = fno->fname;
-	if (dj->sect) {
-		dir = dj->dir;
-		nt = dir[DIR_NTres];		/* NT flag */
-		for (i = 0; i < 8; i++) {	/* Copy name body */
-			c = dir[i];
-			if (c == ' ') break;
-			if (c == NDDE) c = (TCHAR)DDE;
-			if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20;
-#if _LFN_UNICODE
-			if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1]))
-				c = (c << 8) | dir[++i];
-			c = ff_convert(c, 1);
-			if (!c) c = '?';
-#endif
-			*p++ = c;
-		}
-		if (dir[8] != ' ') {		/* Copy name extension */
-			*p++ = '.';
-			for (i = 8; i < 11; i++) {
-				c = dir[i];
-				if (c == ' ') break;
-				if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20;
-#if _LFN_UNICODE
-				if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1]))
-					c = (c << 8) | dir[++i];
-				c = ff_convert(c, 1);
-				if (!c) c = '?';
-#endif
-				*p++ = c;
-			}
-		}
-		fno->fattrib = dir[DIR_Attr];				/* Attribute */
-		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
-		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
-		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
-	}
-	*p = 0;		/* Terminate SFN str by a \0 */
-
-#if _USE_LFN
-	if (fno->lfname && fno->lfsize) {
-		TCHAR *tp = fno->lfname;
-		WCHAR w, *lfn;
-
-		i = 0;
-		if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */
-			lfn = dj->lfn;
-			while ((w = *lfn++) != 0) {			/* Get an LFN char */
-#if !_LFN_UNICODE
-				w = ff_convert(w, 0);			/* Unicode -> OEM conversion */
-				if (!w) { i = 0; break; }		/* Could not convert, no LFN */
-				if (_DF1S && w >= 0x100)		/* Put 1st byte if it is a DBC (always false on SBCS cfg) */
-					tp[i++] = (TCHAR)(w >> 8);
-#endif
-				if (i >= fno->lfsize - 1) { i = 0; break; }	/* Buffer overflow, no LFN */
-				tp[i++] = (TCHAR)w;
-			}
-		}
-		tp[i] = 0;	/* Terminate the LFN str by a \0 */
-	}
-#endif
-}
-#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2*/
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Follow a file path                                                    */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
-	DIR *dj,			/* Directory object to return last directory and found object */
-	const TCHAR *path	/* Full-path string to find a file or directory */
-)
-{
-	FRESULT res;
-	BYTE *dir, ns;
-
-
-#if _FS_RPATH
-	if (*path == '/' || *path == '\\') { /* There is a heading separator */
-		path++;	dj->sclust = 0;		/* Strip it and start from the root dir */
-	} else {							/* No heading separator */
-		dj->sclust = dj->fs->cdir;	/* Start from the current dir */
-	}
-#else
-	if (*path == '/' || *path == '\\')	/* Strip heading separator if exist */
-		path++;
-	dj->sclust = 0;						/* Start from the root dir */
-#endif
-
-	if ((UINT)*path < ' ') {			/* Nul path means the start directory itself */
-		res = dir_sdi(dj, 0);
-		dj->dir = 0;
-	} else {							/* Follow path */
-		for (;;) {
-			res = create_name(dj, &path);	/* Get a segment */
-			if (res != FR_OK) break;
-			res = dir_find(dj);				/* Find it */
-			ns = *(dj->fn+NS);
-			if (res != FR_OK) {				/* Failed to find the object */
-				if (res != FR_NO_FILE) break;	/* Abort if any hard error occurred */
-				/* Object not found */
-				if (_FS_RPATH && (ns & NS_DOT)) {	/* If dot entry is not exit */
-					dj->sclust = 0; dj->dir = 0;	/* It is the root dir */
-					res = FR_OK;
-					if (!(ns & NS_LAST)) continue;
-				} else {							/* Could not find the object */
-					if (!(ns & NS_LAST)) res = FR_NO_PATH;
-				}
-				break;
-			}
-			if (ns & NS_LAST) break;			/* Last segment match. Function completed. */
-			dir = dj->dir;						/* There is next segment. Follow the sub directory */
-			if (!(dir[DIR_Attr] & AM_DIR)) {	/* Cannot follow because it is a file */
-				res = FR_NO_PATH; break;
-			}
-			dj->sclust = ld_clust(dj->fs, dir);
-		}
-	}
-
-	return res;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Load a sector and check if it is an FAT Volume Boot Record            */
-/*-----------------------------------------------------------------------*/
-
-static
-BYTE check_fs (	/* 0:FAT-VBR, 1:Any BR but not FAT, 2:Not a BR, 3:Disk error */
-	FATFS *fs,	/* File system object */
-	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
-)
-{
-	if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK)	/* Load boot record */
-		return 3;
-	if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55)		/* Check record signature (always placed at offset 510 even if the sector size is >512) */
-		return 2;
-
-	if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146)	/* Check "FAT" string */
-		return 0;
-	if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146)
-		return 0;
-
-	return 1;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Check if the file system object is valid or not                       */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT chk_mounted (	/* FR_OK(0): successful, !=0: any error occurred */
-	const TCHAR **path,	/* Pointer to pointer to the path name (drive number) */
-	FATFS **rfs,		/* Pointer to pointer to the found file system object */
-	BYTE wmode			/* !=0: Check write protection for write access */
-)
-{
-	BYTE fmt, b, pi, *tbl;
-	UINT vol;
-	DSTATUS stat;
-	DWORD bsect, fasize, tsect, sysect, nclst, szbfat;
-	WORD nrsv;
-	const TCHAR *p = *path;
-	FATFS *fs;
-
-
-	/* Get logical drive number from the path name */
-	vol = p[0] - '0';					/* Is there a drive number? */
-	if (vol <= 9 && p[1] == ':') {		/* Found a drive number, get and strip it */
-		p += 2; *path = p;				/* Return pointer to the path name */
-	} else {							/* No drive number, use default drive */
-#if _FS_RPATH
-		vol = CurrVol;					/* Use current drive */
-#else
-		vol = 0;						/* Use drive 0 */
-#endif
-	}
-
-	/* Check if the file system object is valid or not */
-	*rfs = 0;
-	if (vol >= _VOLUMES) 				/* Is the drive number valid? */
-		return FR_INVALID_DRIVE;
-	fs = FatFs[vol];					/* Get corresponding file system object */
-	if (!fs) return FR_NOT_ENABLED;		/* Is the file system object available? */
-
-	ENTER_FF(fs);						/* Lock volume */
-
-	*rfs = fs;							/* Return pointer to the corresponding file system object */
-	if (fs->fs_type) {					/* If the volume has been mounted */
-		stat = disk_status(fs->drv);
-		if (!(stat & STA_NOINIT)) {		/* and the physical drive is kept initialized (has not been changed), */
-			if (!_FS_READONLY && wmode && (stat & STA_PROTECT))	/* Check write protection if needed */
-				return FR_WRITE_PROTECTED;
-			return FR_OK;				/* The file system object is valid */
-		}
-	}
-
-	/* The file system object is not valid. */
-	/* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
-
-	fs->fs_type = 0;					/* Clear the file system object */
-	fs->drv = LD2PD(vol);				/* Bind the logical drive and a physical drive */
-	stat = disk_initialize(fs->drv);	/* Initialize the physical drive */
-	if (stat & STA_NOINIT)				/* Check if the initialization succeeded */
-		return FR_NOT_READY;			/* Failed to initialize due to no medium or hard error */
-	if (!_FS_READONLY && wmode && (stat & STA_PROTECT))	/* Check disk write protection if needed */
-		return FR_WRITE_PROTECTED;
-#if _MAX_SS != 512						/* Get disk sector size (variable sector size cfg only) */
-	if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK)
-		return FR_DISK_ERR;
-#endif
-	/* Search FAT partition on the drive. Supports only generic partitions, FDISK and SFD. */
-	fmt = check_fs(fs, bsect = 0);		/* Load sector 0 and check if it is an FAT-VBR (in SFD) */
-	if (LD2PT(vol) && !fmt) fmt = 1;	/* Force non-SFD if the volume is forced partition */
-	if (fmt == 1) {						/* Not an FAT-VBR, the physical drive can be partitioned */
-		/* Check the partition listed in the partition table */
-		pi = LD2PT(vol);
-		if (pi) pi--;
-		tbl = &fs->win[MBR_Table + pi * SZ_PTE];/* Partition table */
-		if (tbl[4]) {						/* Is the partition existing? */
-			bsect = LD_DWORD(&tbl[8]);		/* Partition offset in LBA */
-			fmt = check_fs(fs, bsect);		/* Check the partition */
-		}
-	}
-	if (fmt == 3) return FR_DISK_ERR;
-	if (fmt) return FR_NO_FILESYSTEM;		/* No FAT volume is found */
-
-	/* An FAT volume is found. Following code initializes the file system object */
-
-	if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs))		/* (BPB_BytsPerSec must be equal to the physical sector size) */
-		return FR_NO_FILESYSTEM;
-
-	fasize = LD_WORD(fs->win+BPB_FATSz16);				/* Number of sectors per FAT */
-	if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32);
-	fs->fsize = fasize;
-
-	fs->n_fats = b = fs->win[BPB_NumFATs];				/* Number of FAT copies */
-	if (b != 1 && b != 2) return FR_NO_FILESYSTEM;		/* (Must be 1 or 2) */
-	fasize *= b;										/* Number of sectors for FAT area */
-
-	fs->csize = b = fs->win[BPB_SecPerClus];			/* Number of sectors per cluster */
-	if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM;	/* (Must be power of 2) */
-
-	fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt);	/* Number of root directory entries */
-	if (fs->n_rootdir % (SS(fs) / SZ_DIR)) return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must be sector aligned) */
-
-	tsect = LD_WORD(fs->win+BPB_TotSec16);				/* Number of sectors on the volume */
-	if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32);
-
-	nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt);				/* Number of reserved sectors */
-	if (!nrsv) return FR_NO_FILESYSTEM;					/* (BPB_RsvdSecCnt must not be 0) */
-
-	/* Determine the FAT sub type */
-	sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR);	/* RSV+FAT+DIR */
-	if (tsect < sysect) return FR_NO_FILESYSTEM;		/* (Invalid volume size) */
-	nclst = (tsect - sysect) / fs->csize;				/* Number of clusters */
-	if (!nclst) return FR_NO_FILESYSTEM;				/* (Invalid volume size) */
-	fmt = FS_FAT12;
-	if (nclst >= MIN_FAT16) fmt = FS_FAT16;
-	if (nclst >= MIN_FAT32) fmt = FS_FAT32;
-
-	/* Boundaries and Limits */
-	fs->n_fatent = nclst + 2;							/* Number of FAT entries */
-	fs->volbase = bsect;								/* Volume start sector */
-	fs->fatbase = bsect + nrsv; 						/* FAT start sector */
-	fs->database = bsect + sysect;						/* Data start sector */
-	if (fmt == FS_FAT32) {
-		if (fs->n_rootdir) return FR_NO_FILESYSTEM;		/* (BPB_RootEntCnt must be 0) */
-		fs->dirbase = LD_DWORD(fs->win+BPB_RootClus);	/* Root directory start cluster */
-		szbfat = fs->n_fatent * 4;						/* (Required FAT size) */
-	} else {
-		if (!fs->n_rootdir)	return FR_NO_FILESYSTEM;	/* (BPB_RootEntCnt must not be 0) */
-		fs->dirbase = fs->fatbase + fasize;				/* Root directory start sector */
-		szbfat = (fmt == FS_FAT16) ?					/* (Required FAT size) */
-			fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
-	}
-	if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs))	/* (BPB_FATSz must not be less than required) */
-		return FR_NO_FILESYSTEM;
-
-#if !_FS_READONLY
-	/* Initialize cluster allocation information */
-	fs->free_clust = 0xFFFFFFFF;
-	fs->last_clust = 0;
-
-	/* Get fsinfo if available */
-	if (fmt == FS_FAT32) {
-	 	fs->fsi_flag = 0;
-		fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
-		if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
-			LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
-			LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 &&
-			LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) {
-				fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free);
-				fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count);
-		}
-	}
-#endif
-	fs->fs_type = fmt;		/* FAT sub-type */
-	fs->id = ++Fsid;		/* File system mount ID */
-	fs->winsect = 0;		/* Invalidate sector cache */
-	fs->wflag = 0;
-#if _FS_RPATH
-	fs->cdir = 0;			/* Current directory (root dir) */
-#endif
-#if _FS_LOCK				/* Clear file lock semaphores */
-	clear_lock(fs);
-#endif
-
-	return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Check if the file/dir object is valid or not                          */
-/*-----------------------------------------------------------------------*/
-
-static
-FRESULT validate (	/* FR_OK(0): The object is valid, !=0: Invalid */
-	void* obj		/* Pointer to the object FIL/DIR to check validity */
-)
-{
-	FIL *fil = (FIL*)obj;	/* Assuming offset of fs and id in the FIL/DIR is identical */
-
-
-	if (!fil || !fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id)
-		return FR_INVALID_OBJECT;
-
-	ENTER_FF(fil->fs);		/* Lock file system */
-
-	if (disk_status(fil->fs->drv) & STA_NOINIT)
-		return FR_NOT_READY;
-
-	return FR_OK;
-}
-
-
-
-
-/*--------------------------------------------------------------------------
-
-   Public Functions
-
---------------------------------------------------------------------------*/
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Mount/Unmount a Logical Drive                                         */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_mount (
-	BYTE vol,		/* Logical drive number to be mounted/unmounted */
-	FATFS *fs		/* Pointer to new file system object (NULL for unmount)*/
-)
-{
-	FATFS *rfs;
-
-
-	if (vol >= _VOLUMES)		/* Check if the drive number is valid */
-		return FR_INVALID_DRIVE;
-	rfs = FatFs[vol];			/* Get current fs object */
-
-	if (rfs) {
-#if _FS_LOCK
-		clear_lock(rfs);
-#endif
-#if _FS_REENTRANT				/* Discard sync object of the current volume */
-		if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR;
-#endif
-		rfs->fs_type = 0;		/* Clear old fs object */
-	}
-
-	if (fs) {
-		fs->fs_type = 0;		/* Clear new fs object */
-#if _FS_REENTRANT				/* Create sync object for the new volume */
-		if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR;
-#endif
-	}
-	FatFs[vol] = fs;			/* Register new fs object */
-
-	return FR_OK;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Open or Create a File                                                 */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_open (
-	FIL *fp,			/* Pointer to the blank file object */
-	const TCHAR *path,	/* Pointer to the file name */
-	BYTE mode			/* Access mode and file open mode flags */
-)
-{
-	FRESULT res;
-	DIR dj;
-	BYTE *dir;
-	DEF_NAMEBUF;
-
-
-	if (!fp) return FR_INVALID_OBJECT;
-	fp->fs = 0;			/* Clear file object */
-
-#if !_FS_READONLY
-	mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW;
-	res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ));
-#else
-	mode &= FA_READ;
-	res = chk_mounted(&path, &dj.fs, 0);
-#endif
-	if (res == FR_OK) {
-		INIT_BUF(dj);
-		res = follow_path(&dj, path);	/* Follow the file path */
-		dir = dj.dir;
-#if !_FS_READONLY	/* R/W configuration */
-		if (res == FR_OK) {
-			if (!dir)	/* Current dir itself */
-				res = FR_INVALID_NAME;
-#if _FS_LOCK
-			else
-				res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
-#endif
-		}
-		/* Create or Open a file */
-		if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
-			DWORD dw, cl;
-
-			if (res != FR_OK) {					/* No file, create new */
-				if (res == FR_NO_FILE)			/* There is no file to open, create a new entry */
-#if _FS_LOCK
-					res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
-#else
-					res = dir_register(&dj);
-#endif
-				mode |= FA_CREATE_ALWAYS;		/* File is created */
-				dir = dj.dir;					/* New entry */
-			}
-			else {								/* Any object is already existing */
-				if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) {	/* Cannot overwrite it (R/O or DIR) */
-					res = FR_DENIED;
-				} else {
-					if (mode & FA_CREATE_NEW)	/* Cannot create as new file */
-						res = FR_EXIST;
-				}
-			}
-			if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) {	/* Truncate it if overwrite mode */
-				dw = get_fattime();					/* Created time */
-				ST_DWORD(dir+DIR_CrtTime, dw);
-				dir[DIR_Attr] = 0;					/* Reset attribute */
-				ST_DWORD(dir+DIR_FileSize, 0);		/* size = 0 */
-				cl = ld_clust(dj.fs, dir);			/* Get start cluster */
-				st_clust(dir, 0);					/* cluster = 0 */
-				dj.fs->wflag = 1;
-				if (cl) {							/* Remove the cluster chain if exist */
-					dw = dj.fs->winsect;
-					res = remove_chain(dj.fs, cl);
-					if (res == FR_OK) {
-						dj.fs->last_clust = cl - 1;	/* Reuse the cluster hole */
-						res = move_window(dj.fs, dw);
-					}
-				}
-			}
-		}
-		else {	/* Open an existing file */
-			if (res == FR_OK) {						/* Follow succeeded */
-				if (dir[DIR_Attr] & AM_DIR) {		/* It is a directory */
-					res = FR_NO_FILE;
-				} else {
-					if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */
-						res = FR_DENIED;
-				}
-			}
-		}
-		if (res == FR_OK) {
-			if (mode & FA_CREATE_ALWAYS)			/* Set file change flag if created or overwritten */
-				mode |= FA__WRITTEN;
-			fp->dir_sect = dj.fs->winsect;			/* Pointer to the directory entry */
-			fp->dir_ptr = dir;
-#if _FS_LOCK
-			fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
-			if (!fp->lockid) res = FR_INT_ERR;
-#endif
-		}
-
-#else				/* R/O configuration */
-		if (res == FR_OK) {					/* Follow succeeded */
-			dir = dj.dir;
-			if (!dir) {						/* Current dir itself */
-				res = FR_INVALID_NAME;
-			} else {
-				if (dir[DIR_Attr] & AM_DIR)	/* It is a directory */
-					res = FR_NO_FILE;
-			}
-		}
-#endif
-		FREE_BUF();
-
-		if (res == FR_OK) {
-			fp->flag = mode;					/* File access mode */
-			fp->sclust = ld_clust(dj.fs, dir);	/* File start cluster */
-			fp->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
-			fp->fptr = 0;						/* File pointer */
-			fp->dsect = 0;
-#if _USE_FASTSEEK
-			fp->cltbl = 0;						/* Normal seek mode */
-#endif
-			fp->fs = dj.fs; fp->id = dj.fs->id;	/* Validate file object */
-		}
-	}
-
-	LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read File                                                             */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_read (
-	FIL *fp, 		/* Pointer to the file object */
-	void *buff,		/* Pointer to data buffer */
-	UINT btr,		/* Number of bytes to read */
-	UINT *br		/* Pointer to number of bytes read */
-)
-{
-	FRESULT res;
-	DWORD clst, sect, remain;
-	UINT rcnt, cc;
-	BYTE csect, *rbuff = (BYTE*)buff;
-
-
-	*br = 0;	/* Clear read byte counter */
-
-	res = validate(fp);							/* Check validity */
-	if (res != FR_OK) LEAVE_FF(fp->fs, res);
-	if (fp->flag & FA__ERROR)					/* Aborted file? */
-		LEAVE_FF(fp->fs, FR_INT_ERR);
-	if (!(fp->flag & FA_READ)) 					/* Check access mode */
-		LEAVE_FF(fp->fs, FR_DENIED);
-	remain = fp->fsize - fp->fptr;
-	if (btr > remain) btr = (UINT)remain;		/* Truncate btr by remaining bytes */
-
-	for ( ;  btr;								/* Repeat until all data read */
-		rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
-		if ((fp->fptr % SS(fp->fs)) == 0) {		/* On the sector boundary? */
-			csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));	/* Sector offset in the cluster */
-			if (!csect) {						/* On the cluster boundary? */
-				if (fp->fptr == 0) {			/* On the top of the file? */
-					clst = fp->sclust;			/* Follow from the origin */
-				} else {						/* Middle or end of the file */
-#if _USE_FASTSEEK
-					if (fp->cltbl)
-						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
-					else
-#endif
-						clst = get_fat(fp->fs, fp->clust);	/* Follow cluster chain on the FAT */
-				}
-				if (clst < 2) ABORT(fp->fs, FR_INT_ERR);
-				if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
-				fp->clust = clst;				/* Update current cluster */
-			}
-			sect = clust2sect(fp->fs, fp->clust);	/* Get current sector */
-			if (!sect) ABORT(fp->fs, FR_INT_ERR);
-			sect += csect;
-			cc = btr / SS(fp->fs);				/* When remaining bytes >= sector size, */
-			if (cc) {							/* Read maximum contiguous sectors directly */
-				if (csect + cc > fp->fs->csize)	/* Clip at cluster boundary */
-					cc = fp->fs->csize - csect;
-				if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK)
-					ABORT(fp->fs, FR_DISK_ERR);
-#if !_FS_READONLY && _FS_MINIMIZE <= 2			/* Replace one of the read sectors with cached data if it contains a dirty sector */
-#if _FS_TINY
-				if (fp->fs->wflag && fp->fs->winsect - sect < cc)
-					mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs));
-#else
-				if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc)
-					mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs));
-#endif
-#endif
-				rcnt = SS(fp->fs) * cc;			/* Number of bytes transferred */
-				continue;
-			}
-#if !_FS_TINY
-			if (fp->dsect != sect) {			/* Load data sector if not in cache */
-#if !_FS_READONLY
-				if (fp->flag & FA__DIRTY) {		/* Write-back dirty sector cache */
-					if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
-						ABORT(fp->fs, FR_DISK_ERR);
-					fp->flag &= ~FA__DIRTY;
-				}
-#endif
-				if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)	/* Fill sector cache */
-					ABORT(fp->fs, FR_DISK_ERR);
-			}
-#endif
-			fp->dsect = sect;
-		}
-		rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));	/* Get partial sector data from sector buffer */
-		if (rcnt > btr) rcnt = btr;
-#if _FS_TINY
-		if (move_window(fp->fs, fp->dsect))		/* Move sector window */
-			ABORT(fp->fs, FR_DISK_ERR);
-		mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt);	/* Pick partial sector */
-#else
-		mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt);	/* Pick partial sector */
-#endif
-	}
-
-	LEAVE_FF(fp->fs, FR_OK);
-}
-
-
-
-
-#if !_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Write File                                                            */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_write (
-	FIL *fp,			/* Pointer to the file object */
-	const void *buff,	/* Pointer to the data to be written */
-	UINT btw,			/* Number of bytes to write */
-	UINT *bw			/* Pointer to number of bytes written */
-)
-{
-	FRESULT res;
-	DWORD clst, sect;
-	UINT wcnt, cc;
-	const BYTE *wbuff = (const BYTE*)buff;
-	BYTE csect;
-
-
-	*bw = 0;	/* Clear write byte counter */
-
-	res = validate(fp);						/* Check validity */
-	if (res != FR_OK) LEAVE_FF(fp->fs, res);
-	if (fp->flag & FA__ERROR)				/* Aborted file? */
-		LEAVE_FF(fp->fs, FR_INT_ERR);
-	if (!(fp->flag & FA_WRITE))				/* Check access mode */
-		LEAVE_FF(fp->fs, FR_DENIED);
-	if ((DWORD)(fp->fsize + btw) < fp->fsize) btw = 0;	/* File size cannot reach 4GB */
-
-	for ( ;  btw;							/* Repeat until all data written */
-		wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) {
-		if ((fp->fptr % SS(fp->fs)) == 0) {	/* On the sector boundary? */
-			csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));	/* Sector offset in the cluster */
-			if (!csect) {					/* On the cluster boundary? */
-				if (fp->fptr == 0) {		/* On the top of the file? */
-					clst = fp->sclust;		/* Follow from the origin */
-					if (clst == 0)			/* When no cluster is allocated, */
-						fp->sclust = clst = create_chain(fp->fs, 0);	/* Create a new cluster chain */
-				} else {					/* Middle or end of the file */
-#if _USE_FASTSEEK
-					if (fp->cltbl)
-						clst = clmt_clust(fp, fp->fptr);	/* Get cluster# from the CLMT */
-					else
-#endif
-						clst = create_chain(fp->fs, fp->clust);	/* Follow or stretch cluster chain on the FAT */
-				}
-				if (clst == 0) break;		/* Could not allocate a new cluster (disk full) */
-				if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
-				if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
-				fp->clust = clst;			/* Update current cluster */
-			}
-#if _FS_TINY
-			if (fp->fs->winsect == fp->dsect && sync_window(fp->fs))	/* Write-back sector cache */
-				ABORT(fp->fs, FR_DISK_ERR);
-#else
-			if (fp->flag & FA__DIRTY) {		/* Write-back sector cache */
-				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
-					ABORT(fp->fs, FR_DISK_ERR);
-				fp->flag &= ~FA__DIRTY;
-			}
-#endif
-			sect = clust2sect(fp->fs, fp->clust);	/* Get current sector */
-			if (!sect) ABORT(fp->fs, FR_INT_ERR);
-			sect += csect;
-			cc = btw / SS(fp->fs);			/* When remaining bytes >= sector size, */
-			if (cc) {						/* Write maximum contiguous sectors directly */
-				if (csect + cc > fp->fs->csize)	/* Clip at cluster boundary */
-					cc = fp->fs->csize - csect;
-				if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK)
-					ABORT(fp->fs, FR_DISK_ERR);
-#if _FS_TINY
-				if (fp->fs->winsect - sect < cc) {	/* Refill sector cache if it gets invalidated by the direct write */
-					mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs));
-					fp->fs->wflag = 0;
-				}
-#else
-				if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
-					mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs));
-					fp->flag &= ~FA__DIRTY;
-				}
-#endif
-				wcnt = SS(fp->fs) * cc;		/* Number of bytes transferred */
-				continue;
-			}
-#if _FS_TINY
-			if (fp->fptr >= fp->fsize) {	/* Avoid silly cache filling at growing edge */
-				if (sync_window(fp->fs)) ABORT(fp->fs, FR_DISK_ERR);
-				fp->fs->winsect = sect;
-			}
-#else
-			if (fp->dsect != sect) {		/* Fill sector cache with file data */
-				if (fp->fptr < fp->fsize &&
-					disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
-						ABORT(fp->fs, FR_DISK_ERR);
-			}
-#endif
-			fp->dsect = sect;
-		}
-		wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
-		if (wcnt > btw) wcnt = btw;
-#if _FS_TINY
-		if (move_window(fp->fs, fp->dsect))	/* Move sector window */
-			ABORT(fp->fs, FR_DISK_ERR);
-		mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt);	/* Fit partial sector */
-		fp->fs->wflag = 1;
-#else
-		mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt);	/* Fit partial sector */
-		fp->flag |= FA__DIRTY;
-#endif
-	}
-
-	if (fp->fptr > fp->fsize) fp->fsize = fp->fptr;	/* Update file size if needed */
-	fp->flag |= FA__WRITTEN;						/* Set file change flag */
-
-	LEAVE_FF(fp->fs, FR_OK);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Synchronize the File Object                                           */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_sync (
-	FIL *fp		/* Pointer to the file object */
-)
-{
-	FRESULT res;
-	DWORD tm;
-	BYTE *dir;
-
-
-	res = validate(fp);					/* Check validity of the object */
-	if (res == FR_OK) {
-		if (fp->flag & FA__WRITTEN) {	/* Has the file been written? */
-#if !_FS_TINY	/* Write-back dirty buffer */
-			if (fp->flag & FA__DIRTY) {
-				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
-					LEAVE_FF(fp->fs, FR_DISK_ERR);
-				fp->flag &= ~FA__DIRTY;
-			}
-#endif
-			/* Update the directory entry */
-			res = move_window(fp->fs, fp->dir_sect);
-			if (res == FR_OK) {
-				dir = fp->dir_ptr;
-				dir[DIR_Attr] |= AM_ARC;					/* Set archive bit */
-				ST_DWORD(dir+DIR_FileSize, fp->fsize);		/* Update file size */
-				st_clust(dir, fp->sclust);					/* Update start cluster */
-				tm = get_fattime();							/* Update updated time */
-				ST_DWORD(dir+DIR_WrtTime, tm);
-				ST_WORD(dir+DIR_LstAccDate, 0);
-				fp->flag &= ~FA__WRITTEN;
-				fp->fs->wflag = 1;
-				res = sync_fs(fp->fs);
-			}
-		}
-	}
-
-	LEAVE_FF(fp->fs, res);
-}
-
-#endif /* !_FS_READONLY */
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Close File                                                            */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_close (
-	FIL *fp		/* Pointer to the file object to be closed */
-)
-{
-	FRESULT res;
-
-
-#if _FS_READONLY
-	res = validate(fp);
-	{
-#if _FS_REENTRANT
-		FATFS *fs = fp->fs;
-#endif
-		if (res == FR_OK) fp->fs = 0;	/* Discard file object */
-		LEAVE_FF(fs, res);
-	}
-#else
-	res = f_sync(fp);		/* Flush cached data */
-#if _FS_LOCK
-	if (res == FR_OK) {		/* Decrement open counter */
-#if _FS_REENTRANT
-		FATFS *fs = fp->fs;;
-		res = validate(fp);
-		if (res == FR_OK) {
-			res = dec_lock(fp->lockid);
-			unlock_fs(fs, FR_OK);
-		}
-#else
-		res = dec_lock(fp->lockid);
-#endif
-	}
-#endif
-	if (res == FR_OK) fp->fs = 0;	/* Discard file object */
-	return res;
-#endif
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Current Drive/Directory Handlings                                     */
-/*-----------------------------------------------------------------------*/
-
-#if _FS_RPATH >= 1
-
-FRESULT f_chdrive (
-	BYTE drv		/* Drive number */
-)
-{
-	if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
-
-	CurrVol = drv;
-
-	return FR_OK;
-}
-
-BYTE f_get_current_drive(void)
-{
-  return CurrVol;
-}
-
-FRESULT f_chdir (
-	const TCHAR *path	/* Pointer to the directory path */
-)
-{
-	FRESULT res;
-	DIR dj;
-	DEF_NAMEBUF;
-
-
-	res = chk_mounted(&path, &dj.fs, 0);
-	if (res == FR_OK) {
-		INIT_BUF(dj);
-		res = follow_path(&dj, path);		/* Follow the path */
-		FREE_BUF();
-		if (res == FR_OK) {					/* Follow completed */
-			if (!dj.dir) {
-				dj.fs->cdir = dj.sclust;	/* Start directory itself */
-			} else {
-				if (dj.dir[DIR_Attr] & AM_DIR)	/* Reached to the directory */
-					dj.fs->cdir = ld_clust(dj.fs, dj.dir);
-				else
-					res = FR_NO_PATH;		/* Reached but a file */
-			}
-		}
-		if (res == FR_NO_FILE) res = FR_NO_PATH;
-	}
-
-	LEAVE_FF(dj.fs, res);
-}
-
-
-#if _FS_RPATH >= 2
-FRESULT f_getcwd (
-	TCHAR *buff,	/* Pointer to the directory path */
-	UINT len		/* Size of path */
-)
-{
-	FRESULT res;
-	DIR dj;
-	UINT i, n;
-	DWORD ccl;
-	TCHAR *tp;
-	FILINFO fno;
-	DEF_NAMEBUF;
-
-
-	*buff = 0;
-	res = chk_mounted((const TCHAR**)&buff, &dj.fs, 0);	/* Get current volume */
-	if (res == FR_OK) {
-		INIT_BUF(dj);
-		i = len;			/* Bottom of buffer (dir stack base) */
-		dj.sclust = dj.fs->cdir;			/* Start to follow upper dir from current dir */
-		while ((ccl = dj.sclust) != 0) {	/* Repeat while current dir is a sub-dir */
-			res = dir_sdi(&dj, 1);			/* Get parent dir */
-			if (res != FR_OK) break;
-			res = dir_read(&dj, 0);
-			if (res != FR_OK) break;
-			dj.sclust = ld_clust(dj.fs, dj.dir);	/* Goto parent dir */
-			res = dir_sdi(&dj, 0);
-			if (res != FR_OK) break;
-			do {							/* Find the entry links to the child dir */
-				res = dir_read(&dj, 0);
-				if (res != FR_OK) break;
-				if (ccl == ld_clust(dj.fs, dj.dir)) break;	/* Found the entry */
-				res = dir_next(&dj, 0);
-			} while (res == FR_OK);
-			if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
-			if (res != FR_OK) break;
-#if _USE_LFN
-			fno.lfname = buff;
-			fno.lfsize = i;
-#endif
-			get_fileinfo(&dj, &fno);		/* Get the dir name and push it to the buffer */
-			tp = fno.fname;
-			if (_USE_LFN && *buff) tp = buff;
-			for (n = 0; tp[n]; n++) ;
-			if (i < n + 3) {
-				res = FR_NOT_ENOUGH_CORE; break;
-			}
-			while (n) buff[--i] = tp[--n];
-			buff[--i] = '/';
-		}
-		tp = buff;
-		if (res == FR_OK) {
-			*tp++ = '0' + CurrVol;			/* Put drive number */
-			*tp++ = ':';
-			if (i == len) {					/* Root-dir */
-				*tp++ = '/';
-			} else {						/* Sub-dir */
-				do		/* Add stacked path str */
-					*tp++ = buff[i++];
-				while (i < len);
-			}
-		}
-		*tp = 0;
-		FREE_BUF();
-	}
-
-	LEAVE_FF(dj.fs, res);
-}
-#endif /* _FS_RPATH >= 2 */
-#endif /* _FS_RPATH >= 1 */
-
-
-
-#if _FS_MINIMIZE <= 2
-/*-----------------------------------------------------------------------*/
-/* Seek File R/W Pointer                                                 */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_lseek (
-	FIL *fp,		/* Pointer to the file object */
-	DWORD ofs		/* File pointer from top of file */
-)
-{
-	FRESULT res;
-
-
-	res = validate(fp);					/* Check validity of the object */
-	if (res != FR_OK) LEAVE_FF(fp->fs, res);
-	if (fp->flag & FA__ERROR)			/* Check abort flag */
-		LEAVE_FF(fp->fs, FR_INT_ERR);
-
-#if _USE_FASTSEEK
-	if (fp->cltbl) {	/* Fast seek */
-		DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
-
-		if (ofs == CREATE_LINKMAP) {	/* Create CLMT */
-			tbl = fp->cltbl;
-			tlen = *tbl++; ulen = 2;	/* Given table size and required table size */
-			cl = fp->sclust;			/* Top of the chain */
-			if (cl) {
-				do {
-					/* Get a fragment */
-					tcl = cl; ncl = 0; ulen += 2;	/* Top, length and used items */
-					do {
-						pcl = cl; ncl++;
-						cl = get_fat(fp->fs, cl);
-						if (cl <= 1) ABORT(fp->fs, FR_INT_ERR);
-						if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
-					} while (cl == pcl + 1);
-					if (ulen <= tlen) {		/* Store the length and top of the fragment */
-						*tbl++ = ncl; *tbl++ = tcl;
-					}
-				} while (cl < fp->fs->n_fatent);	/* Repeat until end of chain */
-			}
-			*fp->cltbl = ulen;	/* Number of items used */
-			if (ulen <= tlen)
-				*tbl = 0;		/* Terminate table */
-			else
-				res = FR_NOT_ENOUGH_CORE;	/* Given table size is smaller than required */
-
-		} else {						/* Fast seek */
-			if (ofs > fp->fsize)		/* Clip offset at the file size */
-				ofs = fp->fsize;
-			fp->fptr = ofs;				/* Set file pointer */
-			if (ofs) {
-				fp->clust = clmt_clust(fp, ofs - 1);
-				dsc = clust2sect(fp->fs, fp->clust);
-				if (!dsc) ABORT(fp->fs, FR_INT_ERR);
-				dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1);
-				if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) {	/* Refill sector cache if needed */
-#if !_FS_TINY
-#if !_FS_READONLY
-					if (fp->flag & FA__DIRTY) {		/* Write-back dirty sector cache */
-						if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
-							ABORT(fp->fs, FR_DISK_ERR);
-						fp->flag &= ~FA__DIRTY;
-					}
-#endif
-					if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK)	/* Load current sector */
-						ABORT(fp->fs, FR_DISK_ERR);
-#endif
-					fp->dsect = dsc;
-				}
-			}
-		}
-	} else
-#endif
-
-	/* Normal Seek */
-	{
-		DWORD clst, bcs, nsect, ifptr;
-
-		if (ofs > fp->fsize					/* In read-only mode, clip offset with the file size */
-#if !_FS_READONLY
-			 && !(fp->flag & FA_WRITE)
-#endif
-			) ofs = fp->fsize;
-
-		ifptr = fp->fptr;
-		fp->fptr = nsect = 0;
-		if (ofs) {
-			bcs = (DWORD)fp->fs->csize * SS(fp->fs);	/* Cluster size (byte) */
-			if (ifptr > 0 &&
-				(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
-				fp->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
-				ofs -= fp->fptr;
-				clst = fp->clust;
-			} else {									/* When seek to back cluster, */
-				clst = fp->sclust;						/* start from the first cluster */
-#if !_FS_READONLY
-				if (clst == 0) {						/* If no cluster chain, create a new chain */
-					clst = create_chain(fp->fs, 0);
-					if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
-					if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
-					fp->sclust = clst;
-				}
-#endif
-				fp->clust = clst;
-			}
-			if (clst != 0) {
-				while (ofs > bcs) {						/* Cluster following loop */
-#if !_FS_READONLY
-					if (fp->flag & FA_WRITE) {			/* Check if in write mode or not */
-						clst = create_chain(fp->fs, clst);	/* Force stretch if in write mode */
-						if (clst == 0) {				/* When disk gets full, clip file size */
-							ofs = bcs; break;
-						}
-					} else
-#endif
-						clst = get_fat(fp->fs, clst);	/* Follow cluster chain if not in write mode */
-					if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
-					if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR);
-					fp->clust = clst;
-					fp->fptr += bcs;
-					ofs -= bcs;
-				}
-				fp->fptr += ofs;
-				if (ofs % SS(fp->fs)) {
-					nsect = clust2sect(fp->fs, clst);	/* Current sector */
-					if (!nsect) ABORT(fp->fs, FR_INT_ERR);
-					nsect += ofs / SS(fp->fs);
-				}
-			}
-		}
-		if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) {	/* Fill sector cache if needed */
-#if !_FS_TINY
-#if !_FS_READONLY
-			if (fp->flag & FA__DIRTY) {			/* Write-back dirty sector cache */
-				if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
-					ABORT(fp->fs, FR_DISK_ERR);
-				fp->flag &= ~FA__DIRTY;
-			}
-#endif
-			if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK)	/* Fill sector cache */
-				ABORT(fp->fs, FR_DISK_ERR);
-#endif
-			fp->dsect = nsect;
-		}
-#if !_FS_READONLY
-		if (fp->fptr > fp->fsize) {			/* Set file change flag if the file size is extended */
-			fp->fsize = fp->fptr;
-			fp->flag |= FA__WRITTEN;
-		}
-#endif
-	}
-
-	LEAVE_FF(fp->fs, res);
-}
-
-
-
-#if _FS_MINIMIZE <= 1
-/*-----------------------------------------------------------------------*/
-/* Create a Directory Object                                             */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_opendir (
-	DIR *dj,			/* Pointer to directory object to create */
-	const TCHAR *path	/* Pointer to the directory path */
-)
-{
-	FRESULT res;
-	FATFS *fs;
-	DEF_NAMEBUF;
-
-
-	if (!dj) return FR_INVALID_OBJECT;
-
-	res = chk_mounted(&path, &dj->fs, 0);
-	fs = dj->fs;
-	if (res == FR_OK) {
-		INIT_BUF(*dj);
-		res = follow_path(dj, path);			/* Follow the path to the directory */
-		FREE_BUF();
-		if (res == FR_OK) {						/* Follow completed */
-			if (dj->dir) {						/* It is not the root dir */
-				if (dj->dir[DIR_Attr] & AM_DIR) {	/* The object is a directory */
-					dj->sclust = ld_clust(fs, dj->dir);
-				} else {						/* The object is not a directory */
-					res = FR_NO_PATH;
-				}
-			}
-			if (res == FR_OK) {
-				dj->id = fs->id;
-				res = dir_sdi(dj, 0);			/* Rewind dir */
-			}
-		}
-		if (res == FR_NO_FILE) res = FR_NO_PATH;
-		if (res != FR_OK) dj->fs = 0;			/* Invalidate the dir object if function faild */
-	} else {
-		dj->fs = 0;
-	}
-
-	LEAVE_FF(fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Read Directory Entry in Sequence                                      */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_readdir (
-	DIR *dj,			/* Pointer to the open directory object */
-	FILINFO *fno		/* Pointer to file information to return */
-)
-{
-	FRESULT res;
-	DEF_NAMEBUF;
-
-
-	res = validate(dj);						/* Check validity of the object */
-	if (res == FR_OK) {
-		if (!fno) {
-			res = dir_sdi(dj, 0);			/* Rewind the directory object */
-		} else {
-			INIT_BUF(*dj);
-			res = dir_read(dj, 0);			/* Read an item */
-			if (res == FR_NO_FILE) {		/* Reached end of dir */
-				dj->sect = 0;
-				res = FR_OK;
-			}
-			if (res == FR_OK) {				/* A valid entry is found */
-				get_fileinfo(dj, fno);		/* Get the object information */
-				res = dir_next(dj, 0);		/* Increment index for next */
-				if (res == FR_NO_FILE) {
-					dj->sect = 0;
-					res = FR_OK;
-				}
-			}
-			FREE_BUF();
-		}
-	}
-
-	LEAVE_FF(dj->fs, res);
-}
-
-
-
-#if _FS_MINIMIZE == 0
-/*-----------------------------------------------------------------------*/
-/* Get File Status                                                       */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_stat (
-	const TCHAR *path,	/* Pointer to the file path */
-	FILINFO *fno		/* Pointer to file information to return */
-)
-{
-	FRESULT res;
-	DIR dj;
-	DEF_NAMEBUF;
-
-
-	res = chk_mounted(&path, &dj.fs, 0);
-	if (res == FR_OK) {
-		INIT_BUF(dj);
-		res = follow_path(&dj, path);	/* Follow the file path */
-		if (res == FR_OK) {				/* Follow completed */
-			if (dj.dir)		/* Found an object */
-				get_fileinfo(&dj, fno);
-			else			/* It is root dir */
-				res = FR_INVALID_NAME;
-		}
-		FREE_BUF();
-	}
-
-	LEAVE_FF(dj.fs, res);
-}
-
-
-
-#if !_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Get Number of Free Clusters                                           */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_getfree (
-	const TCHAR *path,	/* Path name of the logical drive number */
-	DWORD *nclst,		/* Pointer to a variable to return number of free clusters */
-	FATFS **fatfs		/* Pointer to return pointer to corresponding file system object */
-)
-{
-	FRESULT res;
-	FATFS *fs;
-	DWORD n, clst, sect, stat;
-	UINT i;
-	BYTE fat, *p;
-
-
-	/* Get drive number */
-	res = chk_mounted(&path, fatfs, 0);
-	fs = *fatfs;
-	if (res == FR_OK) {
-		/* If free_clust is valid, return it without full cluster scan */
-		if (fs->free_clust <= fs->n_fatent - 2) {
-			*nclst = fs->free_clust;
-		} else {
-			/* Get number of free clusters */
-			fat = fs->fs_type;
-			n = 0;
-			if (fat == FS_FAT12) {
-				clst = 2;
-				do {
-					stat = get_fat(fs, clst);
-					if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
-					if (stat == 1) { res = FR_INT_ERR; break; }
-					if (stat == 0) n++;
-				} while (++clst < fs->n_fatent);
-			} else {
-				clst = fs->n_fatent;
-				sect = fs->fatbase;
-				i = 0; p = 0;
-				do {
-					if (!i) {
-						res = move_window(fs, sect++);
-						if (res != FR_OK) break;
-						p = fs->win;
-						i = SS(fs);
-					}
-					if (fat == FS_FAT16) {
-						if (LD_WORD(p) == 0) n++;
-						p += 2; i -= 2;
-					} else {
-						if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++;
-						p += 4; i -= 4;
-					}
-				} while (--clst);
-			}
-			fs->free_clust = n;
-			if (fat == FS_FAT32) fs->fsi_flag = 1;
-			*nclst = n;
-		}
-	}
-	LEAVE_FF(fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Truncate File                                                         */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_truncate (
-	FIL *fp		/* Pointer to the file object */
-)
-{
-	FRESULT res;
-	DWORD ncl;
-
-
-	res = validate(fp);						/* Check validity of the object */
-	if (res == FR_OK) {
-		if (fp->flag & FA__ERROR) {			/* Check abort flag */
-			res = FR_INT_ERR;
-		} else {
-			if (!(fp->flag & FA_WRITE))		/* Check access mode */
-				res = FR_DENIED;
-		}
-	}
-	if (res == FR_OK) {
-		if (fp->fsize > fp->fptr) {
-			fp->fsize = fp->fptr;	/* Set file size to current R/W point */
-			fp->flag |= FA__WRITTEN;
-			if (fp->fptr == 0) {	/* When set file size to zero, remove entire cluster chain */
-				res = remove_chain(fp->fs, fp->sclust);
-				fp->sclust = 0;
-			} else {				/* When truncate a part of the file, remove remaining clusters */
-				ncl = get_fat(fp->fs, fp->clust);
-				res = FR_OK;
-				if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
-				if (ncl == 1) res = FR_INT_ERR;
-				if (res == FR_OK && ncl < fp->fs->n_fatent) {
-					res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF);
-					if (res == FR_OK) res = remove_chain(fp->fs, ncl);
-				}
-			}
-		}
-		if (res != FR_OK) fp->flag |= FA__ERROR;
-	}
-
-	LEAVE_FF(fp->fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Delete a File or Directory                                            */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_unlink (
-	const TCHAR *path		/* Pointer to the file or directory path */
-)
-{
-	FRESULT res;
-	DIR dj, sdj;
-	BYTE *dir;
-	DWORD dclst;
-	DEF_NAMEBUF;
-
-
-	res = chk_mounted(&path, &dj.fs, 1);
-	if (res == FR_OK) {
-		INIT_BUF(dj);
-		res = follow_path(&dj, path);		/* Follow the file path */
-		if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
-			res = FR_INVALID_NAME;			/* Cannot remove dot entry */
-#if _FS_LOCK
-		if (res == FR_OK) res = chk_lock(&dj, 2);	/* Cannot remove open file */
-#endif
-		if (res == FR_OK) {					/* The object is accessible */
-			dir = dj.dir;
-			if (!dir) {
-				res = FR_INVALID_NAME;		/* Cannot remove the start directory */
-			} else {
-				if (dir[DIR_Attr] & AM_RDO)
-					res = FR_DENIED;		/* Cannot remove R/O object */
-			}
-			dclst = ld_clust(dj.fs, dir);
-			if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) {	/* Is it a sub-dir? */
-				if (dclst < 2) {
-					res = FR_INT_ERR;
-				} else {
-					mem_cpy(&sdj, &dj, sizeof (DIR));	/* Check if the sub-dir is empty or not */
-					sdj.sclust = dclst;
-					res = dir_sdi(&sdj, 2);		/* Exclude dot entries */
-					if (res == FR_OK) {
-						res = dir_read(&sdj, 0);	/* Read an item */
-						if (res == FR_OK		/* Not empty dir */
-#if _FS_RPATH
-						|| dclst == dj.fs->cdir	/* Current dir */
-#endif
-						) res = FR_DENIED;
-						if (res == FR_NO_FILE) res = FR_OK;	/* Empty */
-					}
-				}
-			}
-			if (res == FR_OK) {
-				res = dir_remove(&dj);		/* Remove the directory entry */
-				if (res == FR_OK) {
-					if (dclst)				/* Remove the cluster chain if exist */
-						res = remove_chain(dj.fs, dclst);
-					if (res == FR_OK) res = sync_fs(dj.fs);
-				}
-			}
-		}
-		FREE_BUF();
-	}
-
-	LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Create a Directory                                                    */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_mkdir (
-	const TCHAR *path		/* Pointer to the directory path */
-)
-{
-	FRESULT res;
-	DIR dj;
-	BYTE *dir, n;
-	DWORD dsc, dcl, pcl, tm = get_fattime();
-	DEF_NAMEBUF;
-
-
-	res = chk_mounted(&path, &dj.fs, 1);
-	if (res == FR_OK) {
-		INIT_BUF(dj);
-		res = follow_path(&dj, path);			/* Follow the file path */
-		if (res == FR_OK) res = FR_EXIST;		/* Any object with same name is already existing */
-		if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT))
-			res = FR_INVALID_NAME;
-		if (res == FR_NO_FILE) {				/* Can create a new directory */
-			dcl = create_chain(dj.fs, 0);		/* Allocate a cluster for the new directory table */
-			res = FR_OK;
-			if (dcl == 0) res = FR_DENIED;		/* No space to allocate a new cluster */
-			if (dcl == 1) res = FR_INT_ERR;
-			if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
-			if (res == FR_OK)					/* Flush FAT */
-				res = sync_window(dj.fs);
-			if (res == FR_OK) {					/* Initialize the new directory table */
-				dsc = clust2sect(dj.fs, dcl);
-				dir = dj.fs->win;
-				mem_set(dir, 0, SS(dj.fs));
-				mem_set(dir+DIR_Name, ' ', 11);	/* Create "." entry */
-				dir[DIR_Name] = '.';
-				dir[DIR_Attr] = AM_DIR;
-				ST_DWORD(dir+DIR_WrtTime, tm);
-				st_clust(dir, dcl);
-				mem_cpy(dir+SZ_DIR, dir, SZ_DIR); 	/* Create ".." entry */
-				dir[33] = '.'; pcl = dj.sclust;
-				if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase)
-					pcl = 0;
-				st_clust(dir+SZ_DIR, pcl);
-				for (n = dj.fs->csize; n; n--) {	/* Write dot entries and clear following sectors */
-					dj.fs->winsect = dsc++;
-					dj.fs->wflag = 1;
-					res = sync_window(dj.fs);
-					if (res != FR_OK) break;
-					mem_set(dir, 0, SS(dj.fs));
-				}
-			}
-			if (res == FR_OK) res = dir_register(&dj);	/* Register the object to the directoy */
-			if (res != FR_OK) {
-				remove_chain(dj.fs, dcl);			/* Could not register, remove cluster chain */
-			} else {
-				dir = dj.dir;
-				dir[DIR_Attr] = AM_DIR;				/* Attribute */
-				ST_DWORD(dir+DIR_WrtTime, tm);		/* Created time */
-				st_clust(dir, dcl);					/* Table start cluster */
-				dj.fs->wflag = 1;
-				res = sync_fs(dj.fs);
-			}
-		}
-		FREE_BUF();
-	}
-
-	LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Change Attribute                                                      */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_chmod (
-	const TCHAR *path,	/* Pointer to the file path */
-	BYTE value,			/* Attribute bits */
-	BYTE mask			/* Attribute mask to change */
-)
-{
-	FRESULT res;
-	DIR dj;
-	BYTE *dir;
-	DEF_NAMEBUF;
-
-
-	res = chk_mounted(&path, &dj.fs, 1);
-	if (res == FR_OK) {
-		INIT_BUF(dj);
-		res = follow_path(&dj, path);		/* Follow the file path */
-		FREE_BUF();
-		if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
-			res = FR_INVALID_NAME;
-		if (res == FR_OK) {
-			dir = dj.dir;
-			if (!dir) {						/* Is it a root directory? */
-				res = FR_INVALID_NAME;
-			} else {						/* File or sub directory */
-				mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC;	/* Valid attribute mask */
-				dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask);	/* Apply attribute change */
-				dj.fs->wflag = 1;
-				res = sync_fs(dj.fs);
-			}
-		}
-	}
-
-	LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Change Timestamp                                                      */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_utime (
-	const TCHAR *path,	/* Pointer to the file/directory name */
-	const FILINFO *fno	/* Pointer to the time stamp to be set */
-)
-{
-	FRESULT res;
-	DIR dj;
-	BYTE *dir;
-	DEF_NAMEBUF;
-
-
-	res = chk_mounted(&path, &dj.fs, 1);
-	if (res == FR_OK) {
-		INIT_BUF(dj);
-		res = follow_path(&dj, path);	/* Follow the file path */
-		FREE_BUF();
-		if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
-			res = FR_INVALID_NAME;
-		if (res == FR_OK) {
-			dir = dj.dir;
-			if (!dir) {					/* Root directory */
-				res = FR_INVALID_NAME;
-			} else {					/* File or sub-directory */
-				ST_WORD(dir+DIR_WrtTime, fno->ftime);
-				ST_WORD(dir+DIR_WrtDate, fno->fdate);
-				dj.fs->wflag = 1;
-				res = sync_fs(dj.fs);
-			}
-		}
-	}
-
-	LEAVE_FF(dj.fs, res);
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Rename File/Directory                                                 */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_rename (
-	const TCHAR *path_old,	/* Pointer to the old name */
-	const TCHAR *path_new	/* Pointer to the new name */
-)
-{
-	FRESULT res;
-	DIR djo, djn;
-	BYTE buf[21], *dir;
-	DWORD dw;
-	DEF_NAMEBUF;
-
-
-	res = chk_mounted(&path_old, &djo.fs, 1);
-	if (res == FR_OK) {
-		djn.fs = djo.fs;
-		INIT_BUF(djo);
-		res = follow_path(&djo, path_old);		/* Check old object */
-		if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT))
-			res = FR_INVALID_NAME;
-#if _FS_LOCK
-		if (res == FR_OK) res = chk_lock(&djo, 2);
-#endif
-		if (res == FR_OK) {						/* Old object is found */
-			if (!djo.dir) {						/* Is root dir? */
-				res = FR_NO_FILE;
-			} else {
-				mem_cpy(buf, djo.dir+DIR_Attr, 21);		/* Save the object information except for name */
-				mem_cpy(&djn, &djo, sizeof (DIR));		/* Check new object */
-				res = follow_path(&djn, path_new);
-				if (res == FR_OK) res = FR_EXIST;		/* The new object name is already existing */
-				if (res == FR_NO_FILE) { 				/* Is it a valid path and no name collision? */
-/* Start critical section that any interruption can cause a cross-link */
-					res = dir_register(&djn);			/* Register the new entry */
-					if (res == FR_OK) {
-						dir = djn.dir;					/* Copy object information except for name */
-						mem_cpy(dir+13, buf+2, 19);
-						dir[DIR_Attr] = buf[0] | AM_ARC;
-						djo.fs->wflag = 1;
-						if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) {		/* Update .. entry in the directory if needed */
-							dw = clust2sect(djo.fs, ld_clust(djo.fs, dir));
-							if (!dw) {
-								res = FR_INT_ERR;
-							} else {
-								res = move_window(djo.fs, dw);
-								dir = djo.fs->win+SZ_DIR;	/* .. entry */
-								if (res == FR_OK && dir[1] == '.') {
-									dw = (djo.fs->fs_type == FS_FAT32 && djn.sclust == djo.fs->dirbase) ? 0 : djn.sclust;
-									st_clust(dir, dw);
-									djo.fs->wflag = 1;
-								}
-							}
-						}
-						if (res == FR_OK) {
-							res = dir_remove(&djo);		/* Remove old entry */
-							if (res == FR_OK)
-								res = sync_fs(djo.fs);
-						}
-					}
-/* End critical section */
-				}
-			}
-		}
-		FREE_BUF();
-	}
-
-	LEAVE_FF(djo.fs, res);
-}
-
-#endif /* !_FS_READONLY */
-#endif /* _FS_MINIMIZE == 0 */
-#endif /* _FS_MINIMIZE <= 1 */
-#endif /* _FS_MINIMIZE <= 2 */
-
-
-
-#if _USE_LABEL
-/*-----------------------------------------------------------------------*/
-/* Get volume label                                                      */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_getlabel (
-	const TCHAR* path,	/* Path name of the logical drive number */
-	TCHAR* label,		/* Pointer to a buffer to return the volume label */
-	DWORD* sn			/* Pointer to a variable to return the volume serial number */
-)
-{
-	FRESULT res;
-	DIR dj;
-	UINT i, j;
-
-
-	/* Get logical drive */
-	res = chk_mounted(&path, &dj.fs, 0);
-
-	/* Get volume label */
-	if (res == FR_OK && label) {
-		dj.sclust = 0;					/* Open root dir */
-		res = dir_sdi(&dj, 0);
-		if (res == FR_OK) {
-			res = dir_read(&dj, 1);		/* Get an entry with AM_VOL */
-			if (res == FR_OK) {			/* A volume label is exist */
-#if _LFN_UNICODE
-				WCHAR w;
-				i = j = 0;
-				do {
-					w = (i < 11) ? dj.dir[i++] : ' ';
-					if (IsDBCS1(w) && i < 11 && IsDBCS2(dj.dir[i]))
-						w = (w << 8) | dj.dir[i++];
-					label[j++] = ff_convert(w, 1);
-				} while (j < 11);
-#else
-				mem_cpy(label, dj.dir, 11);
-#endif
-				j = 11;
-				do {
-					label[j] = 0;
-					if (!j) break;
-				} while (label[--j] == ' ');
-			}
-			if (res == FR_NO_FILE) {	/* No label, return nul string */
-				label[0] = 0;
-				res = FR_OK;
-			}
-		}
-	}
-
-	/* Get volume serial number */
-	if (res == FR_OK && sn) {
-		res = move_window(dj.fs, dj.fs->volbase);
-		if (res == FR_OK) {
-			i = dj.fs->fs_type == FS_FAT32 ? BS_VolID32 : BS_VolID;
-			*sn = LD_DWORD(&dj.fs->win[i]);
-		}
-	}
-
-	LEAVE_FF(dj.fs, res);
-}
-
-
-
-#if !_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Set volume label                                                      */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_setlabel (
-	const TCHAR* label	/* Pointer to the volume label to set */
-)
-{
-	FRESULT res;
-	DIR dj;
-	BYTE vn[11];
-	UINT i, j, sl;
-	WCHAR w;
-	DWORD tm;
-
-
-	/* Get logical drive */
-	res = chk_mounted(&label, &dj.fs, 1);
-	if (res) LEAVE_FF(dj.fs, res);
-
-	/* Create a volume label in directory form */
-	vn[0] = 0;
-	for (sl = 0; label[sl]; sl++) ;				/* Get name length */
-	for ( ; sl && label[sl-1] == ' '; sl--) ;	/* Remove trailing spaces */
-	if (sl) {	/* Create volume label in directory form */
-		i = j = 0;
-		do {
-#if _LFN_UNICODE
-			w = ff_convert(ff_wtoupper(label[i++]), 0);
-#else
-			w = (BYTE)label[i++];
-			if (IsDBCS1(w))
-				w = (j < 10 && i < sl && IsDBCS2(label[i])) ? (w << 8) | (BYTE)label[i++] : 0;
-#if _USE_LFN
-			w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0);
-#else
-			if (IsLower(w)) w -= 0x20;			/* To upper ASCII chars */
-#ifdef _EXCVT
-			if (w >= 0x80) w = ExCvt[w - 0x80];	/* To upper extended chars (SBCS cfg) */
-#else
-			if (!_DF1S && w >= 0x80) w = 0;		/* Reject extended chars (ASCII cfg) */
-#endif
-#endif
-#endif
-			if (!w || chk_chr("\"*+,.:;<=>\?[]|\x7F", w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) /* Reject invalid chars for volume label */
-				LEAVE_FF(dj.fs, FR_INVALID_NAME);
-			if (w >= 0x100) vn[j++] = (BYTE)(w >> 8);
-			vn[j++] = (BYTE)w;
-		} while (i < sl);
-		while (j < 11) vn[j++] = ' ';
-	}
-
-	/* Set volume label */
-	dj.sclust = 0;					/* Open root dir */
-	res = dir_sdi(&dj, 0);
-	if (res == FR_OK) {
-		res = dir_read(&dj, 1);		/* Get an entry with AM_VOL */
-		if (res == FR_OK) {			/* A volume label is found */
-			if (vn[0]) {
-				mem_cpy(dj.dir, vn, 11);	/* Change the volume label name */
-				tm = get_fattime();
-				ST_DWORD(dj.dir+DIR_WrtTime, tm);
-			} else {
-				dj.dir[0] = DDE;			/* Remove the volume label */
-			}
-			dj.fs->wflag = 1;
-			res = sync_fs(dj.fs);
-		} else {					/* No volume label is found or error */
-			if (res == FR_NO_FILE) {
-				res = FR_OK;
-				if (vn[0]) {				/* Create volume label as new */
-					res = dir_alloc(&dj, 1);	/* Allocate an entry for volume label */
-					if (res == FR_OK) {
-						mem_set(dj.dir, 0, SZ_DIR);	/* Set volume label */
-						mem_cpy(dj.dir, vn, 11);
-						dj.dir[DIR_Attr] = AM_VOL;
-						tm = get_fattime();
-						ST_DWORD(dj.dir+DIR_WrtTime, tm);
-						dj.fs->wflag = 1;
-						res = sync_fs(dj.fs);
-					}
-				}
-			}
-		}
-	}
-
-	LEAVE_FF(dj.fs, res);
-}
-
-#endif /* !_FS_READONLY */
-#endif /* _USE_LABEL */
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Forward data to the stream directly (available on only tiny cfg)      */
-/*-----------------------------------------------------------------------*/
-#if _USE_FORWARD && _FS_TINY
-
-FRESULT f_forward (
-	FIL *fp, 						/* Pointer to the file object */
-	UINT (*func)(const BYTE*,UINT),	/* Pointer to the streaming function */
-	UINT btf,						/* Number of bytes to forward */
-	UINT *bf						/* Pointer to number of bytes forwarded */
-)
-{
-	FRESULT res;
-	DWORD remain, clst, sect;
-	UINT rcnt;
-	BYTE csect;
-
-
-	*bf = 0;	/* Clear transfer byte counter */
-
-	res = validate(fp);								/* Check validity of the object */
-	if (res != FR_OK) LEAVE_FF(fp->fs, res);
-	if (fp->flag & FA__ERROR)						/* Check error flag */
-		LEAVE_FF(fp->fs, FR_INT_ERR);
-	if (!(fp->flag & FA_READ))						/* Check access mode */
-		LEAVE_FF(fp->fs, FR_DENIED);
-
-	remain = fp->fsize - fp->fptr;
-	if (btf > remain) btf = (UINT)remain;			/* Truncate btf by remaining bytes */
-
-	for ( ;  btf && (*func)(0, 0);					/* Repeat until all data transferred or stream becomes busy */
-		fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) {
-		csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1));	/* Sector offset in the cluster */
-		if ((fp->fptr % SS(fp->fs)) == 0) {			/* On the sector boundary? */
-			if (!csect) {							/* On the cluster boundary? */
-				clst = (fp->fptr == 0) ?			/* On the top of the file? */
-					fp->sclust : get_fat(fp->fs, fp->clust);
-				if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
-				if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
-				fp->clust = clst;					/* Update current cluster */
-			}
-		}
-		sect = clust2sect(fp->fs, fp->clust);		/* Get current data sector */
-		if (!sect) ABORT(fp->fs, FR_INT_ERR);
-		sect += csect;
-		if (move_window(fp->fs, sect))				/* Move sector window */
-			ABORT(fp->fs, FR_DISK_ERR);
-		fp->dsect = sect;
-		rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs));	/* Forward data from sector window */
-		if (rcnt > btf) rcnt = btf;
-		rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt);
-		if (!rcnt) ABORT(fp->fs, FR_INT_ERR);
-	}
-
-	LEAVE_FF(fp->fs, FR_OK);
-}
-#endif /* _USE_FORWARD */
-
-
-
-#if _USE_MKFS && !_FS_READONLY
-/*-----------------------------------------------------------------------*/
-/* Create File System on the Drive                                       */
-/*-----------------------------------------------------------------------*/
-#define N_ROOTDIR	512		/* Number of root dir entries for FAT12/16 */
-#define N_FATS		1		/* Number of FAT copies (1 or 2) */
-
-
-FRESULT f_mkfs (
-	BYTE vol,		/* Logical drive number */
-	BYTE sfd,		/* Partitioning rule 0:FDISK, 1:SFD */
-	UINT au			/* Allocation unit size [bytes] */
-)
-{
-	static const WORD vst[] = { 1024,   512,  256,  128,   64,    32,   16,    8,    4,    2,   0};
-	static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512};
-	BYTE fmt, md, sys, *tbl, pdrv, part;
-	DWORD n_clst, vs, n, wsect;
-	UINT i;
-	DWORD b_vol, b_fat, b_dir, b_data;	/* LBA */
-	DWORD n_vol, n_rsv, n_fat, n_dir;	/* Size */
-	FATFS *fs;
-	DSTATUS stat;
-
-
-	/* Check mounted drive and clear work area */
-	if (vol >= _VOLUMES) return FR_INVALID_DRIVE;
-	if (sfd > 1) return FR_INVALID_PARAMETER;
-	if (au & (au - 1)) return FR_INVALID_PARAMETER;
-	fs = FatFs[vol];
-	if (!fs) return FR_NOT_ENABLED;
-	fs->fs_type = 0;
-	pdrv = LD2PD(vol);	/* Physical drive */
-	part = LD2PT(vol);	/* Partition (0:auto detect, 1-4:get from partition table)*/
-
-	/* Get disk statics */
-	stat = disk_initialize(pdrv);
-	if (stat & STA_NOINIT) return FR_NOT_READY;
-	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
-#if _MAX_SS != 512					/* Get disk sector size */
-	if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS)
-		return FR_DISK_ERR;
-#endif
-	if (_MULTI_PARTITION && part) {
-		/* Get partition information from partition table in the MBR */
-		if (disk_read(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
-		if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;
-		tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
-		if (!tbl[4]) return FR_MKFS_ABORTED;	/* No partition? */
-		b_vol = LD_DWORD(tbl+8);	/* Volume start sector */
-		n_vol = LD_DWORD(tbl+12);	/* Volume size */
-	} else {
-		/* Create a partition in this function */
-		if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128)
-			return FR_DISK_ERR;
-		b_vol = (sfd) ? 0 : 63;		/* Volume start sector */
-		n_vol -= b_vol;				/* Volume size */
-	}
-
-	if (!au) {				/* AU auto selection */
-		vs = n_vol / (2000 / (SS(fs) / 512));
-		for (i = 0; vs < vst[i]; i++) ;
-		au = cst[i];
-	}
-	au /= SS(fs);		/* Number of sectors per cluster */
-	if (au == 0) au = 1;
-	if (au > 128) au = 128;
-
-	/* Pre-compute number of clusters and FAT sub-type */
-	n_clst = n_vol / au;
-	fmt = FS_FAT12;
-	if (n_clst >= MIN_FAT16) fmt = FS_FAT16;
-	if (n_clst >= MIN_FAT32) fmt = FS_FAT32;
-
-	/* Determine offset and size of FAT structure */
-	if (fmt == FS_FAT32) {
-		n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs);
-		n_rsv = 32;
-		n_dir = 0;
-	} else {
-		n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4;
-		n_fat = (n_fat + SS(fs) - 1) / SS(fs);
-		n_rsv = 1;
-		n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs);
-	}
-	b_fat = b_vol + n_rsv;				/* FAT area start sector */
-	b_dir = b_fat + n_fat * N_FATS;		/* Directory area start sector */
-	b_data = b_dir + n_dir;				/* Data area start sector */
-	if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED;	/* Too small volume */
-
-	/* Align data start sector to erase block boundary (for flash memory media) */
-	if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1;
-	n = (b_data + n - 1) & ~(n - 1);	/* Next nearest erase block from current data start */
-	n = (n - b_data) / N_FATS;
-	if (fmt == FS_FAT32) {		/* FAT32: Move FAT offset */
-		n_rsv += n;
-		b_fat += n;
-	} else {					/* FAT12/16: Expand FAT size */
-		n_fat += n;
-	}
-
-	/* Determine number of clusters and final check of validity of the FAT sub-type */
-	n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au;
-	if (   (fmt == FS_FAT16 && n_clst < MIN_FAT16)
-		|| (fmt == FS_FAT32 && n_clst < MIN_FAT32))
-		return FR_MKFS_ABORTED;
-
-	switch (fmt) {	/* Determine system ID for partition table */
-	case FS_FAT12:	sys = 0x01; break;
-	case FS_FAT16:	sys = (n_vol < 0x10000) ? 0x04 : 0x06; break;
-	default: 		sys = 0x0C;
-	}
-
-	if (_MULTI_PARTITION && part) {
-		/* Update system ID in the partition table */
-		tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
-		tbl[4] = sys;
-		if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
-		md = 0xF8;
-	} else {
-		if (sfd) {	/* No partition table (SFD) */
-			md = 0xF0;
-		} else {	/* Create partition table (FDISK) */
-			mem_set(fs->win, 0, SS(fs));
-			tbl = fs->win+MBR_Table;	/* Create partition table for single partition in the drive */
-			tbl[1] = 1;						/* Partition start head */
-			tbl[2] = 1;						/* Partition start sector */
-			tbl[3] = 0;						/* Partition start cylinder */
-			tbl[4] = sys;					/* System type */
-			tbl[5] = 254;					/* Partition end head */
-			n = (b_vol + n_vol) / 63 / 255;
-			tbl[6] = (BYTE)((n >> 2) | 63);	/* Partition end sector */
-			tbl[7] = (BYTE)n;				/* End cylinder */
-			ST_DWORD(tbl+8, 63);			/* Partition start in LBA */
-			ST_DWORD(tbl+12, n_vol);		/* Partition size in LBA */
-			ST_WORD(fs->win+BS_55AA, 0xAA55);	/* MBR signature */
-			if (disk_write(pdrv, fs->win, 0, 1) != RES_OK)	/* Write it to the MBR sector */
-				return FR_DISK_ERR;
-			md = 0xF8;
-		}
-	}
-
-	/* Create BPB in the VBR */
-	tbl = fs->win;							/* Clear sector */
-	mem_set(tbl, 0, SS(fs));
-	mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */
-	i = SS(fs);								/* Sector size */
-	ST_WORD(tbl+BPB_BytsPerSec, i);
-	tbl[BPB_SecPerClus] = (BYTE)au;			/* Sectors per cluster */
-	ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv);		/* Reserved sectors */
-	tbl[BPB_NumFATs] = N_FATS;				/* Number of FATs */
-	i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR;	/* Number of rootdir entries */
-	ST_WORD(tbl+BPB_RootEntCnt, i);
-	if (n_vol < 0x10000) {					/* Number of total sectors */
-		ST_WORD(tbl+BPB_TotSec16, n_vol);
-	} else {
-		ST_DWORD(tbl+BPB_TotSec32, n_vol);
-	}
-	tbl[BPB_Media] = md;					/* Media descriptor */
-	ST_WORD(tbl+BPB_SecPerTrk, 63);			/* Number of sectors per track */
-	ST_WORD(tbl+BPB_NumHeads, 255);			/* Number of heads */
-	ST_DWORD(tbl+BPB_HiddSec, b_vol);		/* Hidden sectors */
-	n = get_fattime();						/* Use current time as VSN */
-	if (fmt == FS_FAT32) {
-		ST_DWORD(tbl+BS_VolID32, n);		/* VSN */
-		ST_DWORD(tbl+BPB_FATSz32, n_fat);	/* Number of sectors per FAT */
-		ST_DWORD(tbl+BPB_RootClus, 2);		/* Root directory start cluster (2) */
-		ST_WORD(tbl+BPB_FSInfo, 1);			/* FSInfo record offset (VBR+1) */
-		ST_WORD(tbl+BPB_BkBootSec, 6);		/* Backup boot record offset (VBR+6) */
-		tbl[BS_DrvNum32] = 0x80;			/* Drive number */
-		tbl[BS_BootSig32] = 0x29;			/* Extended boot signature */
-		mem_cpy(tbl+BS_VolLab32, "NO NAME    " "FAT32   ", 19);	/* Volume label, FAT signature */
-	} else {
-		ST_DWORD(tbl+BS_VolID, n);			/* VSN */
-		ST_WORD(tbl+BPB_FATSz16, n_fat);	/* Number of sectors per FAT */
-		tbl[BS_DrvNum] = 0x80;				/* Drive number */
-		tbl[BS_BootSig] = 0x29;				/* Extended boot signature */
-		mem_cpy(tbl+BS_VolLab, "NO NAME    " "FAT     ", 19);	/* Volume label, FAT signature */
-	}
-	ST_WORD(tbl+BS_55AA, 0xAA55);			/* Signature (Offset is fixed here regardless of sector size) */
-	if (disk_write(pdrv, tbl, b_vol, 1) != RES_OK)	/* Write it to the VBR sector */
-		return FR_DISK_ERR;
-	if (fmt == FS_FAT32)							/* Write backup VBR if needed (VBR+6) */
-		disk_write(pdrv, tbl, b_vol + 6, 1);
-
-	/* Initialize FAT area */
-	wsect = b_fat;
-	for (i = 0; i < N_FATS; i++) {		/* Initialize each FAT copy */
-		mem_set(tbl, 0, SS(fs));			/* 1st sector of the FAT  */
-		n = md;								/* Media descriptor byte */
-		if (fmt != FS_FAT32) {
-			n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00;
-			ST_DWORD(tbl+0, n);				/* Reserve cluster #0-1 (FAT12/16) */
-		} else {
-			n |= 0xFFFFFF00;
-			ST_DWORD(tbl+0, n);				/* Reserve cluster #0-1 (FAT32) */
-			ST_DWORD(tbl+4, 0xFFFFFFFF);
-			ST_DWORD(tbl+8, 0x0FFFFFFF);	/* Reserve cluster #2 for root dir */
-		}
-		if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
-			return FR_DISK_ERR;
-		mem_set(tbl, 0, SS(fs));			/* Fill following FAT entries with zero */
-		for (n = 1; n < n_fat; n++) {		/* This loop may take a time on FAT32 volume due to many single sector writes */
-			if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
-				return FR_DISK_ERR;
-		}
-	}
-
-	/* Initialize root directory */
-	i = (fmt == FS_FAT32) ? au : n_dir;
-	do {
-		if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
-			return FR_DISK_ERR;
-	} while (--i);
-
-#if _USE_ERASE	/* Erase data area if needed */
-	{
-		DWORD eb[2];
-
-		eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1;
-		disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb);
-	}
-#endif
-
-	/* Create FSInfo if needed */
-	if (fmt == FS_FAT32) {
-		ST_DWORD(tbl+FSI_LeadSig, 0x41615252);
-		ST_DWORD(tbl+FSI_StrucSig, 0x61417272);
-		ST_DWORD(tbl+FSI_Free_Count, n_clst - 1);	/* Number of free clusters */
-		ST_DWORD(tbl+FSI_Nxt_Free, 2);				/* Last allocated cluster# */
-		ST_WORD(tbl+BS_55AA, 0xAA55);
-		disk_write(pdrv, tbl, b_vol + 1, 1);	/* Write original (VBR+1) */
-		disk_write(pdrv, tbl, b_vol + 7, 1);	/* Write backup (VBR+7) */
-	}
-
-	return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR;
-}
-
-
-#if _MULTI_PARTITION
-/*-----------------------------------------------------------------------*/
-/* Divide Physical Drive                                                 */
-/*-----------------------------------------------------------------------*/
-
-FRESULT f_fdisk (
-	BYTE pdrv,			/* Physical drive number */
-	const DWORD szt[],	/* Pointer to the size table for each partitions */
-	void* work			/* Pointer to the working buffer */
-)
-{
-	UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
-	BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
-	DSTATUS stat;
-	DWORD sz_disk, sz_part, s_part;
-
-
-	stat = disk_initialize(pdrv);
-	if (stat & STA_NOINIT) return FR_NOT_READY;
-	if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
-	if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
-
-	/* Determine CHS in the table regardless of the drive geometry */
-	for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
-	if (n == 256) n--;
-	e_hd = n - 1;
-	sz_cyl = 63 * n;
-	tot_cyl = sz_disk / sz_cyl;
-
-	/* Create partition table */
-	mem_set(buf, 0, _MAX_SS);
-	p = buf + MBR_Table; b_cyl = 0;
-	for (i = 0; i < 4; i++, p += SZ_PTE) {
-		p_cyl = (szt[i] <= 100) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl;
-		if (!p_cyl) continue;
-		s_part = (DWORD)sz_cyl * b_cyl;
-		sz_part = (DWORD)sz_cyl * p_cyl;
-		if (i == 0) {	/* Exclude first track of cylinder 0 */
-			s_hd = 1;
-			s_part += 63; sz_part -= 63;
-		} else {
-			s_hd = 0;
-		}
-		e_cyl = b_cyl + p_cyl - 1;
-		if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER;
-
-		/* Set partition table */
-		p[1] = s_hd;						/* Start head */
-		p[2] = (BYTE)((b_cyl >> 2) + 1);	/* Start sector */
-		p[3] = (BYTE)b_cyl;					/* Start cylinder */
-		p[4] = 0x06;						/* System type (temporary setting) */
-		p[5] = e_hd;						/* End head */
-		p[6] = (BYTE)((e_cyl >> 2) + 63);	/* End sector */
-		p[7] = (BYTE)e_cyl;					/* End cylinder */
-		ST_DWORD(p + 8, s_part);			/* Start sector in LBA */
-		ST_DWORD(p + 12, sz_part);			/* Partition size */
-
-		/* Next partition */
-		b_cyl += p_cyl;
-	}
-	ST_WORD(p, 0xAA55);
-
-	/* Write it to the MBR */
-	return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK;
-}
-
-
-#endif /* _MULTI_PARTITION */
-#endif /* _USE_MKFS && !_FS_READONLY */
-
-
-
-
-#if _USE_STRFUNC
-/*-----------------------------------------------------------------------*/
-/* Get a string from the file                                            */
-/*-----------------------------------------------------------------------*/
-
-TCHAR* f_gets (
-	TCHAR* buff,	/* Pointer to the string buffer to read */
-	int len,		/* Size of string buffer (characters) */
-	FIL* fp			/* Pointer to the file object */
-)
-{
-	int n = 0;
-	TCHAR c, *p = buff;
-	BYTE s[2];
-	UINT rc;
-
-
-	while (n < len - 1) {			/* Read bytes until buffer gets filled */
-		f_read(fp, s, 1, &rc);
-		if (rc != 1) break;			/* Break on EOF or error */
-		c = s[0];
-#if _LFN_UNICODE					/* Read a character in UTF-8 encoding */
-		if (c >= 0x80) {
-			if (c < 0xC0) continue;	/* Skip stray trailer */
-			if (c < 0xE0) {			/* Two-byte sequence */
-				f_read(fp, s, 1, &rc);
-				if (rc != 1) break;
-				c = ((c & 0x1F) << 6) | (s[0] & 0x3F);
-				if (c < 0x80) c = '?';
-			} else {
-				if (c < 0xF0) {		/* Three-byte sequence */
-					f_read(fp, s, 2, &rc);
-					if (rc != 2) break;
-					c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F);
-					if (c < 0x800) c = '?';
-				} else {			/* Reject four-byte sequence */
-					c = '?';
-				}
-			}
-		}
-#endif
-#if _USE_STRFUNC >= 2
-		if (c == '\r') continue;	/* Strip '\r' */
-#endif
-		*p++ = c;
-		n++;
-		if (c == '\n') break;		/* Break on EOL */
-	}
-	*p = 0;
-	return n ? buff : 0;			/* When no data read (eof or error), return with error. */
-}
-
-
-
-#if !_FS_READONLY
-#include <stdarg.h>
-/*-----------------------------------------------------------------------*/
-/* Put a character to the file                                           */
-/*-----------------------------------------------------------------------*/
-
-int f_putc (
-	TCHAR c,	/* A character to be output */
-	FIL* fp		/* Pointer to the file object */
-)
-{
-	UINT bw, btw;
-	BYTE s[3];
-
-
-#if _USE_STRFUNC >= 2
-	if (c == '\n') f_putc ('\r', fp);	/* LF -> CRLF conversion */
-#endif
-
-#if _LFN_UNICODE	/* Write the character in UTF-8 encoding */
-	if (c < 0x80) {			/* 7-bit */
-		s[0] = (BYTE)c;
-		btw = 1;
-	} else {
-		if (c < 0x800) {	/* 11-bit */
-			s[0] = (BYTE)(0xC0 | (c >> 6));
-			s[1] = (BYTE)(0x80 | (c & 0x3F));
-			btw = 2;
-		} else {			/* 16-bit */
-			s[0] = (BYTE)(0xE0 | (c >> 12));
-			s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F));
-			s[2] = (BYTE)(0x80 | (c & 0x3F));
-			btw = 3;
-		}
-	}
-#else				/* Write the character without conversion */
-	s[0] = (BYTE)c;
-	btw = 1;
-#endif
-	f_write(fp, s, btw, &bw);		/* Write the char to the file */
-	return (bw == btw) ? 1 : EOF;	/* Return the result */
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Put a string to the file                                              */
-/*-----------------------------------------------------------------------*/
-
-int f_puts (
-	const TCHAR* str,	/* Pointer to the string to be output */
-	FIL* fp				/* Pointer to the file object */
-)
-{
-	int n;
-
-
-	for (n = 0; *str; str++, n++) {
-		if (f_putc(*str, fp) == EOF) return EOF;
-	}
-	return n;
-}
-
-
-
-
-/*-----------------------------------------------------------------------*/
-/* Put a formatted string to the file                                    */
-/*-----------------------------------------------------------------------*/
-
-int f_printf (
-	FIL* fp,			/* Pointer to the file object */
-	const TCHAR* str,	/* Pointer to the format string */
-	...					/* Optional arguments... */
-)
-{
-	va_list arp;
-	BYTE f, r;
-	UINT i, j, w;
-	ULONG v;
-	TCHAR c, d, s[16], *p;
-	int res, chc, cc;
-
-
-	va_start(arp, str);
-
-	for (cc = res = 0; cc != EOF; res += cc) {
-		c = *str++;
-		if (c == 0) break;			/* End of string */
-		if (c != '%') {				/* Non escape character */
-			cc = f_putc(c, fp);
-			if (cc != EOF) cc = 1;
-			continue;
-		}
-		w = f = 0;
-		c = *str++;
-		if (c == '0') {				/* Flag: '0' padding */
-			f = 1; c = *str++;
-		} else {
-			if (c == '-') {			/* Flag: left justified */
-				f = 2; c = *str++;
-			}
-		}
-		while (IsDigit(c)) {		/* Precision */
-			w = w * 10 + c - '0';
-			c = *str++;
-		}
-		if (c == 'l' || c == 'L') {	/* Prefix: Size is long int */
-			f |= 4; c = *str++;
-		}
-		if (!c) break;
-		d = c;
-		if (IsLower(d)) d -= 0x20;
-		switch (d) {				/* Type is... */
-		case 'S' :					/* String */
-			p = va_arg(arp, TCHAR*);
-			for (j = 0; p[j]; j++) ;
-			chc = 0;
-			if (!(f & 2)) {
-				while (j++ < w) chc += (cc = f_putc(' ', fp));
-			}
-			chc += (cc = f_puts(p, fp));
-			while (j++ < w) chc += (cc = f_putc(' ', fp));
-			if (cc != EOF) cc = chc;
-			continue;
-		case 'C' :					/* Character */
-			cc = f_putc((TCHAR)va_arg(arp, int), fp); continue;
-		case 'B' :					/* Binary */
-			r = 2; break;
-		case 'O' :					/* Octal */
-			r = 8; break;
-		case 'D' :					/* Signed decimal */
-		case 'U' :					/* Unsigned decimal */
-			r = 10; break;
-		case 'X' :					/* Hexdecimal */
-			r = 16; break;
-		default:					/* Unknown type (pass-through) */
-			cc = f_putc(c, fp); continue;
-		}
-
-		/* Get an argument and put it in numeral */
-		v = (f & 4) ? (ULONG)va_arg(arp, long) : ((d == 'D') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_arg(arp, unsigned int));
-		if (d == 'D' && (v & 0x80000000)) {
-			v = 0 - v;
-			f |= 8;
-		}
-		i = 0;
-		do {
-			d = (TCHAR)(v % r); v /= r;
-			if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
-			s[i++] = d + '0';
-		} while (v && i < sizeof s / sizeof s[0]);
-		if (f & 8) s[i++] = '-';
-		j = i; d = (f & 1) ? '0' : ' ';
-		chc = 0;
-		while (!(f & 2) && j++ < w) chc += (cc = f_putc(d, fp));
-		do chc += (cc = f_putc(s[--i], fp)); while(i);
-		while (j++ < w) chc += (cc = f_putc(' ', fp));
-		if (cc != EOF) cc = chc;
-	}
-
-	va_end(arp);
-	return (cc == EOF) ? cc : res;
-}
-
-#endif /* !_FS_READONLY */
-#endif /* _USE_STRFUNC */
-
-#endif // CFG_TUH_MSC
diff --git a/lib/fatfs/ff.h b/lib/fatfs/ff.h
deleted file mode 100644
index 5c2a611ae..000000000
--- a/lib/fatfs/ff.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/*---------------------------------------------------------------------------/
-/  FatFs - FAT file system module include file  R0.09b    (C)ChaN, 2013
-/----------------------------------------------------------------------------/
-/ FatFs module is a generic FAT file system module for small embedded systems.
-/ This is a free software that opened for education, research and commercial
-/ developments under license policy of following terms.
-/
-/  Copyright (C) 2013, ChaN, all right reserved.
-/
-/ * The FatFs module is a free software and there is NO WARRANTY.
-/ * No restriction on use. You can use, modify and redistribute it for
-/   personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
-/ * Redistributions of source code must retain the above copyright notice.
-/
-/----------------------------------------------------------------------------*/
-
-#ifndef _FATFS
-#define _FATFS	82786	/* Revision ID */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "integer.h"	/* Basic integer types */
-#include "ffconf.h"		/* FatFs configuration options */
-#include "tusb_config.h"
-
-#if _FATFS != _FFCONF
-#error Wrong configuration file (ffconf.h).
-#endif
-
-
-
-/* Definitions of volume management */
-
-#if _MULTI_PARTITION		/* Multiple partition configuration */
-typedef struct {
-	BYTE pd;	/* Physical drive number */
-	BYTE pt;	/* Partition: 0:Auto detect, 1-4:Forced partition) */
-} PARTITION;
-extern PARTITION VolToPart[];	/* Volume - Partition resolution table */
-#define LD2PD(vol) (VolToPart[vol].pd)	/* Get physical drive number */
-#define LD2PT(vol) (VolToPart[vol].pt)	/* Get partition index */
-
-#else							/* Single partition configuration */
-#define LD2PD(vol) (BYTE)(vol)	/* Each logical drive is bound to the same physical drive number */
-#define LD2PT(vol) 0			/* Always mounts the 1st partition or in SFD */
-
-#endif
-
-
-
-/* Type of path name strings on FatFs API */
-
-#if _LFN_UNICODE			/* Unicode string */
-#if !_USE_LFN
-#error _LFN_UNICODE must be 0 in non-LFN cfg.
-#endif
-#ifndef _INC_TCHAR
-typedef WCHAR TCHAR;
-#define _T(x) L ## x
-#define _TEXT(x) L ## x
-#endif
-
-#else						/* ANSI/OEM string */
-#ifndef _INC_TCHAR
-typedef char TCHAR;
-#define _T(x) x
-#define _TEXT(x) x
-#endif
-
-#endif
-
-
-
-/* File system object structure (FATFS) */
-
-typedef struct {
-	BYTE	fs_type;		/* FAT sub-type (0:Not mounted) */
-	BYTE	drv;			/* Physical drive number */
-	BYTE	csize;			/* Sectors per cluster (1,2,4...128) */
-	BYTE	n_fats;			/* Number of FAT copies (1,2) */
-	BYTE	wflag;			/* win[] dirty flag (1:must be written back) */
-	BYTE	fsi_flag;		/* fsinfo dirty flag (1:must be written back) */
-	WORD	id;				/* File system mount ID */
-	WORD	n_rootdir;		/* Number of root directory entries (FAT12/16) */
-#if _MAX_SS != 512
-	WORD	ssize;			/* Bytes per sector (512, 1024, 2048 or 4096) */
-#endif
-#if _FS_REENTRANT
-	_SYNC_t	sobj;			/* Identifier of sync object */
-#endif
-#if !_FS_READONLY
-	DWORD	last_clust;		/* Last allocated cluster */
-	DWORD	free_clust;		/* Number of free clusters */
-	DWORD	fsi_sector;		/* fsinfo sector (FAT32) */
-#endif
-#if _FS_RPATH
-	DWORD	cdir;			/* Current directory start cluster (0:root) */
-#endif
-	DWORD	n_fatent;		/* Number of FAT entries (= number of clusters + 2) */
-	DWORD	fsize;			/* Sectors per FAT */
-	DWORD	volbase;		/* Volume start sector */
-	DWORD	fatbase;		/* FAT start sector */
-	DWORD	dirbase;		/* Root directory start sector (FAT32:Cluster#) */
-	DWORD	database;		/* Data start sector */
-	DWORD	winsect;		/* Current sector appearing in the win[] */
-	BYTE	win[_MAX_SS];	/* Disk access window for Directory, FAT (and Data on tiny cfg) */
-} FATFS;
-
-
-
-/* File object structure (FIL) */
-
-typedef struct {
-	FATFS*	fs;				/* Pointer to the related file system object (**do not change order**) */
-	WORD	id;				/* Owner file system mount ID (**do not change order**) */
-	BYTE	flag;			/* File status flags */
-	BYTE	pad1;
-	DWORD	fptr;			/* File read/write pointer (0ed on file open) */
-	DWORD	fsize;			/* File size */
-	DWORD	sclust;			/* File data start cluster (0:no data cluster, always 0 when fsize is 0) */
-	DWORD	clust;			/* Current cluster of fpter */
-	DWORD	dsect;			/* Current data sector of fpter */
-#if !_FS_READONLY
-	DWORD	dir_sect;		/* Sector containing the directory entry */
-	BYTE*	dir_ptr;		/* Pointer to the directory entry in the window */
-#endif
-#if _USE_FASTSEEK
-	DWORD*	cltbl;			/* Pointer to the cluster link map table (null on file open) */
-#endif
-#if _FS_LOCK
-	UINT	lockid;			/* File lock ID (index of file semaphore table Files[]) */
-#endif
-#if !_FS_TINY
-	BYTE	buf[_MAX_SS];	/* File data read/write buffer */
-#endif
-} FIL;
-
-
-
-/* Directory object structure (DIR) */
-
-typedef struct {
-	FATFS*	fs;				/* Pointer to the owner file system object (**do not change order**) */
-	WORD	id;				/* Owner file system mount ID (**do not change order**) */
-	WORD	index;			/* Current read/write index number */
-	DWORD	sclust;			/* Table start cluster (0:Root dir) */
-	DWORD	clust;			/* Current cluster */
-	DWORD	sect;			/* Current sector */
-	BYTE*	dir;			/* Pointer to the current SFN entry in the win[] */
-	BYTE*	fn;				/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
-#if _USE_LFN
-	WCHAR*	lfn;			/* Pointer to the LFN working buffer */
-	WORD	lfn_idx;		/* Last matched LFN index number (0xFFFF:No LFN) */
-#endif
-} DIR;
-
-
-
-/* File status structure (FILINFO) */
-
-typedef struct {
-	DWORD	fsize;			/* File size */
-	WORD	fdate;			/* Last modified date */
-	WORD	ftime;			/* Last modified time */
-	BYTE	fattrib;		/* Attribute */
-	TCHAR	fname[13];		/* Short file name (8.3 format) */
-#if _USE_LFN
-	TCHAR*	lfname;			/* Pointer to the LFN buffer */
-	UINT 	lfsize;			/* Size of LFN buffer in TCHAR */
-#endif
-} FILINFO;
-
-
-
-/* File function return code (FRESULT) */
-
-typedef enum {
-	FR_OK = 0,				/* (0) Succeeded */
-	FR_DISK_ERR,			/* (1) A hard error occurred in the low level disk I/O layer */
-	FR_INT_ERR,				/* (2) Assertion failed */
-	FR_NOT_READY,			/* (3) The physical drive cannot work */
-	FR_NO_FILE,				/* (4) Could not find the file */
-	FR_NO_PATH,				/* (5) Could not find the path */
-	FR_INVALID_NAME,		/* (6) The path name format is invalid */
-	FR_DENIED,				/* (7) Access denied due to prohibited access or directory full */
-	FR_EXIST,				/* (8) Access denied due to prohibited access */
-	FR_INVALID_OBJECT,		/* (9) The file/directory object is invalid */
-	FR_WRITE_PROTECTED,		/* (10) The physical drive is write protected */
-	FR_INVALID_DRIVE,		/* (11) The logical drive number is invalid */
-	FR_NOT_ENABLED,			/* (12) The volume has no work area */
-	FR_NO_FILESYSTEM,		/* (13) There is no valid FAT volume */
-	FR_MKFS_ABORTED,		/* (14) The f_mkfs() aborted due to any parameter error */
-	FR_TIMEOUT,				/* (15) Could not get a grant to access the volume within defined period */
-	FR_LOCKED,				/* (16) The operation is rejected according to the file sharing policy */
-	FR_NOT_ENOUGH_CORE,		/* (17) LFN working buffer could not be allocated */
-	FR_TOO_MANY_OPEN_FILES,	/* (18) Number of open files > _FS_SHARE */
-	FR_INVALID_PARAMETER	/* (19) Given parameter is invalid */
-} FRESULT;
-
-
-
-/*--------------------------------------------------------------*/
-/* FatFs module application interface                           */
-
-FRESULT f_mount (BYTE vol, FATFS* fs);								/* Mount/Unmount a logical drive */
-FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode);				/* Open or create a file */
-FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br);			/* Read data from a file */
-FRESULT f_lseek (FIL* fp, DWORD ofs);								/* Move file pointer of a file object */
-FRESULT f_close (FIL* fp);											/* Close an open file object */
-FRESULT f_opendir (DIR* dj, const TCHAR* path);						/* Open an existing directory */
-FRESULT f_readdir (DIR* dj, FILINFO* fno);							/* Read a directory item */
-FRESULT f_stat (const TCHAR* path, FILINFO* fno);					/* Get file status */
-FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw);	/* Write data to a file */
-FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs);	/* Get number of free clusters on the drive */
-FRESULT f_truncate (FIL* fp);										/* Truncate file */
-FRESULT f_sync (FIL* fp);											/* Flush cached data of a writing file */
-FRESULT f_unlink (const TCHAR* path);								/* Delete an existing file or directory */
-FRESULT	f_mkdir (const TCHAR* path);								/* Create a new directory */
-FRESULT f_chmod (const TCHAR* path, BYTE value, BYTE mask);			/* Change attribute of the file/dir */
-FRESULT f_utime (const TCHAR* path, const FILINFO* fno);			/* Change times-tamp of the file/dir */
-FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new);	/* Rename/Move a file or directory */
-FRESULT f_chdrive (BYTE drv);										/* Change current drive */
-BYTE    f_get_current_drive(void);
-FRESULT f_chdir (const TCHAR* path);								/* Change current directory */
-FRESULT f_getcwd (TCHAR* buff, UINT len);							/* Get current directory */
-FRESULT	f_getlabel (const TCHAR* path, TCHAR* label, DWORD* sn);	/* Get volume label */
-FRESULT	f_setlabel (const TCHAR* label);							/* Set volume label */
-FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf);	/* Forward data to the stream */
-FRESULT f_mkfs (BYTE vol, BYTE sfd, UINT au);						/* Create a file system on the drive */
-FRESULT	f_fdisk (BYTE pdrv, const DWORD szt[], void* work);			/* Divide a physical drive into some partitions */
-int f_putc (TCHAR c, FIL* fp);										/* Put a character to the file */
-int f_puts (const TCHAR* str, FIL* cp);								/* Put a string to the file */
-int f_printf (FIL* fp, const TCHAR* str, ...);						/* Put a formatted string to the file */
-TCHAR* f_gets (TCHAR* buff, int len, FIL* fp);						/* Get a string from the file */
-
-#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
-#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
-#define f_tell(fp) ((fp)->fptr)
-#define f_size(fp) ((fp)->fsize)
-
-#ifndef EOF
-#define EOF (-1)
-#endif
-
-
-
-
-/*--------------------------------------------------------------*/
-/* Additional user defined functions                            */
-
-/* RTC function */
-#if !_FS_READONLY
-DWORD get_fattime (void);
-#endif
-
-/* Unicode support functions */
-#if _USE_LFN							/* Unicode - OEM code conversion */
-WCHAR ff_convert (WCHAR chr, UINT dir);	/* OEM-Unicode bidirectional conversion */
-WCHAR ff_wtoupper (WCHAR chr);			/* Unicode upper-case conversion */
-#if _USE_LFN == 3						/* Memory functions */
-void* ff_memalloc (UINT msize);			/* Allocate memory block */
-void ff_memfree (void* mblock);			/* Free memory block */
-#endif
-#endif
-
-/* Sync functions */
-#if _FS_REENTRANT
-int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj);	/* Create a sync object */
-int ff_req_grant (_SYNC_t sobj);				/* Lock sync object */
-void ff_rel_grant (_SYNC_t sobj);				/* Unlock sync object */
-int ff_del_syncobj (_SYNC_t sobj);				/* Delete a sync object */
-#endif
-
-
-
-
-/*--------------------------------------------------------------*/
-/* Flags and offset address                                     */
-
-
-/* File access control and file status flags (FIL.flag) */
-
-#define	FA_READ				0x01
-#define	FA_OPEN_EXISTING	0x00
-#define FA__ERROR			0x80
-
-#if !_FS_READONLY
-#define	FA_WRITE			0x02
-#define	FA_CREATE_NEW		0x04
-#define	FA_CREATE_ALWAYS	0x08
-#define	FA_OPEN_ALWAYS		0x10
-#define FA__WRITTEN			0x20
-#define FA__DIRTY			0x40
-#endif
-
-
-/* FAT sub type (FATFS.fs_type) */
-
-#define FS_FAT12	1
-#define FS_FAT16	2
-#define FS_FAT32	3
-
-
-/* File attribute bits for directory entry */
-
-#define	AM_RDO	0x01	/* Read only */
-#define	AM_HID	0x02	/* Hidden */
-#define	AM_SYS	0x04	/* System */
-#define	AM_VOL	0x08	/* Volume label */
-#define AM_LFN	0x0F	/* LFN entry */
-#define AM_DIR	0x10	/* Directory */
-#define AM_ARC	0x20	/* Archive */
-#define AM_MASK	0x3F	/* Mask of defined bits */
-
-
-/* Fast seek feature */
-#define CREATE_LINKMAP	0xFFFFFFFF
-
-
-
-/*--------------------------------*/
-/* Multi-byte word access macros  */
-
-#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
-#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
-#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
-#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
-#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
-#else					/* Use byte-by-byte access to the FAT structure */
-#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
-#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
-#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
-#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _FATFS */
diff --git a/lib/fatfs/ffconf.h b/lib/fatfs/ffconf.h
deleted file mode 100644
index 782057ea4..000000000
--- a/lib/fatfs/ffconf.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*---------------------------------------------------------------------------/
-/  FatFs - FAT file system module configuration file  R0.09b (C)ChaN, 2013
-/----------------------------------------------------------------------------/
-/
-/ CAUTION! Do not forget to make clean the project after any changes to
-/ the configuration options.
-/
-/----------------------------------------------------------------------------*/
-#ifndef _FFCONF
-#define _FFCONF 82786	/* Revision ID */
-
-#include "tusb_config.h"
-
-/*---------------------------------------------------------------------------/
-/ Functions and Buffer Configurations
-/----------------------------------------------------------------------------*/
-
-#define	_FS_TINY		0	/* 0:Normal or 1:Tiny */
-/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
-/  object instead of the sector buffer in the individual file object for file
-/  data transfer. This reduces memory consumption 512 bytes each file object. */
-
-
-#define _FS_READONLY	0	/* 0:Read/Write or 1:Read only */
-/* Setting _FS_READONLY to 1 defines read only configuration. This removes
-/  writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
-/  f_truncate and useless f_getfree. */
-
-
-#define _FS_MINIMIZE	0	/* 0 to 3 */
-/* The _FS_MINIMIZE option defines minimization level to remove some functions.
-/
-/   0: Full function.
-/   1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
-/      are removed.
-/   2: f_opendir and f_readdir are removed in addition to 1.
-/   3: f_lseek is removed in addition to 2. */
-
-
-#define	_USE_STRFUNC	0	/* 0:Disable or 1-2:Enable */
-/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
-
-
-#define	_USE_MKFS		0	/* 0:Disable or 1:Enable */
-/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
-
-
-#define	_USE_FASTSEEK	0	/* 0:Disable or 1:Enable */
-/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
-
-
-#define _USE_LABEL		1	/* 0:Disable or 1:Enable */
-/* To enable volume label functions, set _USE_LAVEL to 1 */
-
-
-#define	_USE_FORWARD	0	/* 0:Disable or 1:Enable */
-/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
-
-
-/*---------------------------------------------------------------------------/
-/ Locale and Namespace Configurations
-/----------------------------------------------------------------------------*/
-
-#define _CODE_PAGE	437
-/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
-/  Incorrect setting of the code page can cause a file open failure.
-/
-/   932  - Japanese Shift-JIS (DBCS, OEM, Windows)
-/   936  - Simplified Chinese GBK (DBCS, OEM, Windows)
-/   949  - Korean (DBCS, OEM, Windows)
-/   950  - Traditional Chinese Big5 (DBCS, OEM, Windows)
-/   1250 - Central Europe (Windows)
-/   1251 - Cyrillic (Windows)
-/   1252 - Latin 1 (Windows)
-/   1253 - Greek (Windows)
-/   1254 - Turkish (Windows)
-/   1255 - Hebrew (Windows)
-/   1256 - Arabic (Windows)
-/   1257 - Baltic (Windows)
-/   1258 - Vietnam (OEM, Windows)
-/   437  - U.S. (OEM)
-/   720  - Arabic (OEM)
-/   737  - Greek (OEM)
-/   775  - Baltic (OEM)
-/   850  - Multilingual Latin 1 (OEM)
-/   858  - Multilingual Latin 1 + Euro (OEM)
-/   852  - Latin 2 (OEM)
-/   855  - Cyrillic (OEM)
-/   866  - Russian (OEM)
-/   857  - Turkish (OEM)
-/   862  - Hebrew (OEM)
-/   874  - Thai (OEM, Windows)
-/	1    - ASCII only (Valid for non LFN cfg.)
-*/
-
-
-#define	_USE_LFN	1		/* 0 to 3 */
-#define	_MAX_LFN	255		/* Maximum LFN length to handle (12 to 255) */
-/* The _USE_LFN option switches the LFN support.
-/
-/   0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
-/   1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
-/   2: Enable LFN with dynamic working buffer on the STACK.
-/   3: Enable LFN with dynamic working buffer on the HEAP.
-/
-/  The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
-/  Unicode handling functions ff_convert() and ff_wtoupper() must be added
-/  to the project. When enable to use heap, memory control functions
-/  ff_memalloc() and ff_memfree() must be added to the project. */
-
-
-#define	_LFN_UNICODE	0	/* 0:ANSI/OEM or 1:Unicode */
-/* To switch the character code set on FatFs API to Unicode,
-/  enable LFN feature and set _LFN_UNICODE to 1. */
-
-
-#define _FS_RPATH		2	/* 0 to 2 */
-/* The _FS_RPATH option configures relative path feature.
-/
-/   0: Disable relative path feature and remove related functions.
-/   1: Enable relative path. f_chdrive() and f_chdir() are available.
-/   2: f_getcwd() is available in addition to 1.
-/
-/  Note that output of the f_readdir fnction is affected by this option. */
-
-
-/*---------------------------------------------------------------------------/
-/ Physical Drive Configurations
-/----------------------------------------------------------------------------*/
-
-#define _VOLUMES	CFG_TUH_DEVICE_MAX
-/* Number of volumes (logical drives) to be used. */
-
-
-#define	_MAX_SS		512		/* 512, 1024, 2048 or 4096 */
-/* Maximum sector size to be handled.
-/  Always set 512 for memory card and hard disk but a larger value may be
-/  required for on-board flash memory, floppy disk and optical disk.
-/  When _MAX_SS is larger than 512, it configures FatFs to variable sector size
-/  and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */
-
-
-#define	_MULTI_PARTITION	0	/* 0:Single partition, 1:Enable multiple partition */
-/* When set to 0, each volume is bound to the same physical drive number and
-/ it can mount only first primaly partition. When it is set to 1, each volume
-/ is tied to the partitions listed in VolToPart[]. */
-
-
-#define	_USE_ERASE	0	/* 0:Disable or 1:Enable */
-/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command
-/  should be added to the disk_ioctl functio. */
-
-
-
-/*---------------------------------------------------------------------------/
-/ System Configurations
-/----------------------------------------------------------------------------*/
-
-#define _WORD_ACCESS	0	/* 0 or 1 */
-/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
-/  option defines which access method is used to the word data on the FAT volume.
-/
-/   0: Byte-by-byte access.
-/   1: Word access. Do not choose this unless following condition is met.
-/
-/  When the byte order on the memory is big-endian or address miss-aligned word
-/  access results incorrect behavior, the _WORD_ACCESS must be set to 0.
-/  If it is not the case, the value can also be set to 1 to improve the
-/  performance and code size.
-*/
-
-
-/* A header file that defines sync object types on the O/S, such as
-/  windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */
-
-#define _FS_REENTRANT	0		/* 0:Disable or 1:Enable */
-#define _FS_TIMEOUT		1000	/* Timeout period in unit of time ticks */
-#define	_SYNC_t			HANDLE	/* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
-
-/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module.
-/
-/   0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
-/   1: Enable reentrancy. Also user provided synchronization handlers,
-/      ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
-/      function must be added to the project. */
-
-
-#define	_FS_LOCK	0	/* 0:Disable or >=1:Enable */
-/* To enable file lock control feature, set _FS_LOCK to 1 or greater.
-   The value defines how many files can be opened simultaneously. */
-
-
-#endif /* _FFCONFIG */
diff --git a/lib/fatfs/integer.h b/lib/fatfs/integer.h
deleted file mode 100644
index f34f56d92..000000000
--- a/lib/fatfs/integer.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*-------------------------------------------*/
-/* Integer type definitions for FatFs module */
-/*-------------------------------------------*/
-
-#ifndef _INTEGER
-#define _INTEGER
-
-#ifdef _WIN32	/* FatFs development platform */
-
-#include <windows.h>
-#include <tchar.h>
-
-#else			/* Embedded platform */
-
-/* These types must be 16-bit, 32-bit or larger integer */
-typedef int				INT;
-typedef unsigned int	UINT;
-
-/* These types must be 8-bit integer */
-typedef unsigned char	UCHAR;
-typedef unsigned char	BYTE;
-
-/* These types must be 16-bit integer */
-typedef short			SHORT;
-typedef unsigned short	USHORT;
-typedef unsigned short	WORD;
-typedef unsigned short	WCHAR;
-
-/* These types must be 32-bit integer */
-typedef long			LONG;
-typedef unsigned long	ULONG;
-typedef unsigned long	DWORD;
-
-#endif
-
-#endif
diff --git a/lib/fatfs/source/ffconf.h b/lib/fatfs/source/ffconf.h
index 80b20efa1..c99498cda 100644
--- a/lib/fatfs/source/ffconf.h
+++ b/lib/fatfs/source/ffconf.h
@@ -113,7 +113,7 @@
 */
 
 
-#define FF_USE_LFN		0
+#define FF_USE_LFN		1
 #define FF_MAX_LFN		255
 /* The FF_USE_LFN switches the support for LFN (long file name).
 /
@@ -153,7 +153,7 @@
 /  on character encoding. When LFN is not enabled, these options have no effect. */
 
 
-#define FF_FS_RPATH		0
+#define FF_FS_RPATH		1
 /* This option configures support for relative path.
 /
 /   0: Disable relative path and remove related functions.
@@ -166,7 +166,7 @@
 / Drive/Volume Configurations
 /---------------------------------------------------------------------------*/
 
-#define FF_VOLUMES		1
+#define FF_VOLUMES		4
 /* Number of volumes (logical drives) to be used. (1-10) */
 
 

From 083ed364ba6dcf5baa2fa2587f94060ef3b33a59 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Nov 2022 13:56:33 +0700
Subject: [PATCH 1225/2085] add cd command

---
 examples/host/msc_file_explorer/src/msc_app.c | 50 ++++++++++++++++---
 1 file changed, 44 insertions(+), 6 deletions(-)

diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index a8603c9df..76308cf5b 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -57,6 +57,7 @@ static scsi_inquiry_resp_t inquiry_resp;
 //--------------------------------------------------------------------+
 
 void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context);
 
 void cli_write_char(EmbeddedCli *cli, char c)
 {
@@ -67,7 +68,7 @@ void cli_write_char(EmbeddedCli *cli, char c)
 void cli_cmd_unknown(EmbeddedCli *cli, CliCommand *command)
 {
   (void) cli;
-  printf("Unknown commands: %s\r\n", command->name);
+  printf("%s: command not found\r\n", command->name);
 }
 
 bool msc_app_init(void)
@@ -90,14 +91,23 @@ bool msc_app_init(void)
 
   _cli->writeChar = cli_write_char;
 
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "cd",
+    "Usage: cd [DIR]...\r\n\tChange the current directory to DIR.",
+    true,
+    NULL,
+    cli_cmd_cd
+  });
+
   embeddedCliAddBinding(_cli, (CliCommandBinding) {
     "ls",
-    "Usage: ls [FILE]...\r\n\tList information about the FILEs (the current directory by default).",
+    "Usage: ls [DIR]...\r\n\tList information about the FILEs (the current directory by default).",
     true,
     NULL,
     cli_cmd_ls
   });
 
+
   return true;
 }
 
@@ -304,7 +314,11 @@ void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
   uint16_t argc = embeddedCliGetTokenCount(args);
 
   // only support 1 argument
-  if ( argc > 1 ) return;
+  if ( argc > 1 )
+  {
+    printf("invalid arguments\r\n");
+    return;
+  }
 
   // default is current directory
   const char* dpath = ".";
@@ -313,7 +327,7 @@ void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
   DIR dir;
   if ( FR_OK != f_opendir(&dir, dpath) )
   {
-    printf("cannot access '%s': No such file or directory", dpath);
+    printf("cannot access '%s': No such file or directory\r\n", dpath);
     return;
   }
 
@@ -325,13 +339,37 @@ void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
       if ( fno.fattrib & AM_DIR )
       {
         // directory
-        printf("/%s\n", fno.fname);
+        printf("/%s\r\n", fno.fname);
       }else
       {
-        printf("%-40s%lu KB\n", fno.fname, fno.fsize / 1000);
+        printf("%-40s%lu KB\r\n", fno.fname, fno.fsize / 1000);
       }
     }
   }
 
   f_closedir(&dir);
 }
+
+void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context)
+{
+  (void) cli;
+  (void) context;
+
+  uint16_t argc = embeddedCliGetTokenCount(args);
+
+  // only support 1 argument
+  if ( argc != 1 )
+  {
+    printf("invalid arguments\r\n");
+    return;
+  }
+
+  // default is current directory
+  const char* dpath = args;
+
+  if ( FR_OK != f_chdir(dpath) )
+  {
+    printf("%s: No such file or directory\r\n", dpath);
+    return;
+  }
+}

From 16e18388624bbb83f582c016cf4768875ed44b3d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Nov 2022 15:27:07 +0700
Subject: [PATCH 1226/2085] implement cat command

---
 examples/host/msc_file_explorer/src/msc_app.c | 75 ++++++++++++++++---
 lib/fatfs/source/ffconf.h                     |  2 +-
 2 files changed, 67 insertions(+), 10 deletions(-)

diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 76308cf5b..83074d89a 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include <ctype.h>
 #include "tusb.h"
 
 #include "ff.h"
@@ -32,6 +33,7 @@
 #define EMBEDDED_CLI_IMPL
 #include "embedded_cli.h"
 
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
@@ -58,6 +60,7 @@ static scsi_inquiry_resp_t inquiry_resp;
 
 void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context);
 
 void cli_write_char(EmbeddedCli *cli, char c)
 {
@@ -91,6 +94,14 @@ bool msc_app_init(void)
 
   _cli->writeChar = cli_write_char;
 
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "cat",
+    "Usage: cat [FILE]...\r\n\tConcatenate FILE(s) to standard output..",
+    true,
+    NULL,
+    cli_cmd_cat
+  });
+
   embeddedCliAddBinding(_cli, (CliCommandBinding) {
     "cd",
     "Usage: cd [DIR]...\r\n\tChange the current directory to DIR.",
@@ -115,13 +126,16 @@ void msc_app_task(void)
 {
   if (!_cli) return;
 
-  int ch;
-  while( (ch = getchar()) > 0 )
+  int ch = getchar();
+  if ( ch > 0 )
   {
-    embeddedCliReceiveChar(_cli, (char) ch);
+    while( ch > 0 )
+    {
+      embeddedCliReceiveChar(_cli, (char) ch);
+      ch = getchar();
+    }
+    embeddedCliProcess(_cli);
   }
-
-  embeddedCliProcess(_cli);
 }
 
 //--------------------------------------------------------------------+
@@ -308,8 +322,7 @@ DRESULT disk_ioctl (
 
 void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
 {
-  (void) cli;
-  (void) context;
+  (void) cli; (void) context;
 
   uint16_t argc = embeddedCliGetTokenCount(args);
 
@@ -352,8 +365,7 @@ void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
 
 void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context)
 {
-  (void) cli;
-  (void) context;
+  (void) cli; (void) context;
 
   uint16_t argc = embeddedCliGetTokenCount(args);
 
@@ -373,3 +385,48 @@ void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context)
     return;
   }
 }
+
+void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context)
+{
+  (void) cli; (void) context;
+
+  uint16_t argc = embeddedCliGetTokenCount(args);
+
+  // need at least 1 argument
+  if ( argc == 0 )
+  {
+    printf("invalid arguments\r\n");
+    return;
+  }
+
+  for(uint16_t i=0; i<argc; i++)
+  {
+    FIL fi;
+    const char* fpath = embeddedCliGetToken(args, i+1); // token count from 1
+
+    if ( FR_OK != f_open(&fi, fpath, FA_READ) )
+    {
+      printf("%s: No such file or directory\r\n", fpath);
+    }else
+    {
+      uint8_t buf[64];
+      size_t count = 0;
+      while ( (FR_OK == f_read(&fi, buf, sizeof(buf), &count)) && (count > 0) )
+      {
+        for(size_t c = 0; c < count; c++)
+        {
+          const char ch = buf[c];
+          if (isprint(ch) || iscntrl(ch))
+          {
+            putchar(ch);
+          }else
+          {
+            putchar('.');
+          }
+        }
+      }
+    }
+
+    f_close(&fi);
+  }
+}
diff --git a/lib/fatfs/source/ffconf.h b/lib/fatfs/source/ffconf.h
index c99498cda..9298ef897 100644
--- a/lib/fatfs/source/ffconf.h
+++ b/lib/fatfs/source/ffconf.h
@@ -237,7 +237,7 @@
 /  Note that enabling exFAT discards ANSI C (C89) compatibility. */
 
 
-#define FF_FS_NORTC		0
+#define FF_FS_NORTC		1
 #define FF_NORTC_MON	1
 #define FF_NORTC_MDAY	1
 #define FF_NORTC_YEAR	2022

From daeaea9556a8175f554375e5d6845bf0caaf3859 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Nov 2022 15:37:23 +0700
Subject: [PATCH 1227/2085] add mkdir

---
 examples/host/msc_file_explorer/src/msc_app.c | 171 +++++++++++-------
 1 file changed, 102 insertions(+), 69 deletions(-)

diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 83074d89a..415e7c94e 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -39,11 +39,11 @@
 //--------------------------------------------------------------------+
 
 //------------- embedded-cli -------------//
-#define CLI_BUFFER_SIZE     256
+#define CLI_BUFFER_SIZE     512
 #define CLI_RX_BUFFER_SIZE  16
 #define CLI_CMD_BUFFER_SIZE 32
 #define CLI_HISTORY_SIZE    32
-#define CLI_BINDING_COUNT   3
+#define CLI_BINDING_COUNT   8
 
 static EmbeddedCli *_cli;
 static CLI_UINT cli_buffer[BYTES_TO_CLI_UINTS(CLI_BUFFER_SIZE)];
@@ -58,9 +58,10 @@ static scsi_inquiry_resp_t inquiry_resp;
 //
 //--------------------------------------------------------------------+
 
-void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context);
 
 void cli_write_char(EmbeddedCli *cli, char c)
 {
@@ -89,6 +90,8 @@ bool msc_app_init(void)
   config->historyBufferSize = CLI_HISTORY_SIZE;
   config->maxBindingCount   = CLI_BINDING_COUNT;
 
+  TU_ASSERT(embeddedCliRequiredSize(config) <= CLI_BUFFER_SIZE);
+
   _cli = embeddedCliNew(config);
   TU_ASSERT(_cli != NULL);
 
@@ -118,6 +121,13 @@ bool msc_app_init(void)
     cli_cmd_ls
   });
 
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "mkdir",
+    "Usage: mkdir [DIR]...\r\n\tCreate the DIRECTORY(ies), if they do not already exist..",
+    true,
+    NULL,
+    cli_cmd_mkdir
+  });
 
   return true;
 }
@@ -320,72 +330,6 @@ DRESULT disk_ioctl (
 // CLI Commands
 //--------------------------------------------------------------------+
 
-void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
-{
-  (void) cli; (void) context;
-
-  uint16_t argc = embeddedCliGetTokenCount(args);
-
-  // only support 1 argument
-  if ( argc > 1 )
-  {
-    printf("invalid arguments\r\n");
-    return;
-  }
-
-  // default is current directory
-  const char* dpath = ".";
-  if (argc) dpath = args;
-
-  DIR dir;
-  if ( FR_OK != f_opendir(&dir, dpath) )
-  {
-    printf("cannot access '%s': No such file or directory\r\n", dpath);
-    return;
-  }
-
-  FILINFO fno;
-  while( (f_readdir(&dir, &fno) == FR_OK) && (fno.fname[0] != 0) )
-  {
-    if ( fno.fname[0] != '.' ) // ignore . and .. entry
-    {
-      if ( fno.fattrib & AM_DIR )
-      {
-        // directory
-        printf("/%s\r\n", fno.fname);
-      }else
-      {
-        printf("%-40s%lu KB\r\n", fno.fname, fno.fsize / 1000);
-      }
-    }
-  }
-
-  f_closedir(&dir);
-}
-
-void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context)
-{
-  (void) cli; (void) context;
-
-  uint16_t argc = embeddedCliGetTokenCount(args);
-
-  // only support 1 argument
-  if ( argc != 1 )
-  {
-    printf("invalid arguments\r\n");
-    return;
-  }
-
-  // default is current directory
-  const char* dpath = args;
-
-  if ( FR_OK != f_chdir(dpath) )
-  {
-    printf("%s: No such file or directory\r\n", dpath);
-    return;
-  }
-}
-
 void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context)
 {
   (void) cli; (void) context;
@@ -430,3 +374,92 @@ void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context)
     f_close(&fi);
   }
 }
+
+void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context)
+{
+  (void) cli; (void) context;
+
+  uint16_t argc = embeddedCliGetTokenCount(args);
+
+  // only support 1 argument
+  if ( argc != 1 )
+  {
+    printf("invalid arguments\r\n");
+    return;
+  }
+
+  // default is current directory
+  const char* dpath = args;
+
+  if ( FR_OK != f_chdir(dpath) )
+  {
+    printf("%s: No such file or directory\r\n", dpath);
+    return;
+  }
+}
+
+void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
+{
+  (void) cli; (void) context;
+
+  uint16_t argc = embeddedCliGetTokenCount(args);
+
+  // only support 1 argument
+  if ( argc > 1 )
+  {
+    printf("invalid arguments\r\n");
+    return;
+  }
+
+  // default is current directory
+  const char* dpath = ".";
+  if (argc) dpath = args;
+
+  DIR dir;
+  if ( FR_OK != f_opendir(&dir, dpath) )
+  {
+    printf("cannot access '%s': No such file or directory\r\n", dpath);
+    return;
+  }
+
+  FILINFO fno;
+  while( (f_readdir(&dir, &fno) == FR_OK) && (fno.fname[0] != 0) )
+  {
+    if ( fno.fname[0] != '.' ) // ignore . and .. entry
+    {
+      if ( fno.fattrib & AM_DIR )
+      {
+        // directory
+        printf("/%s\r\n", fno.fname);
+      }else
+      {
+        printf("%-40s%lu KB\r\n", fno.fname, fno.fsize / 1000);
+      }
+    }
+  }
+
+  f_closedir(&dir);
+}
+
+void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context)
+{
+  (void) cli; (void) context;
+
+  uint16_t argc = embeddedCliGetTokenCount(args);
+
+  // only support 1 argument
+  if ( argc != 1 )
+  {
+    printf("invalid arguments\r\n");
+    return;
+  }
+
+  // default is current directory
+  const char* dpath = args;
+
+  if ( FR_OK != f_mkdir(dpath) )
+  {
+    printf("%s: cannot create this directory\r\n", dpath);
+    return;
+  }
+}

From bf69ffb8f7cf2068baff34a197b6770332ddb794 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 19 Nov 2022 15:53:55 +0700
Subject: [PATCH 1228/2085] add mv command

---
 examples/host/msc_file_explorer/src/msc_app.c | 176 +++++++++++-------
 1 file changed, 111 insertions(+), 65 deletions(-)

diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 415e7c94e..f435e6b96 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -41,7 +41,7 @@
 //------------- embedded-cli -------------//
 #define CLI_BUFFER_SIZE     512
 #define CLI_RX_BUFFER_SIZE  16
-#define CLI_CMD_BUFFER_SIZE 32
+#define CLI_CMD_BUFFER_SIZE 64
 #define CLI_HISTORY_SIZE    32
 #define CLI_BINDING_COUNT   8
 
@@ -58,22 +58,7 @@ static scsi_inquiry_resp_t inquiry_resp;
 //
 //--------------------------------------------------------------------+
 
-void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context);
-void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context);
-void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context);
-void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context);
-
-void cli_write_char(EmbeddedCli *cli, char c)
-{
-  (void) cli;
-  putchar((int) c);
-}
-
-void cli_cmd_unknown(EmbeddedCli *cli, CliCommand *command)
-{
-  (void) cli;
-  printf("%s: command not found\r\n", command->name);
-}
+bool cli_init(void);
 
 bool msc_app_init(void)
 {
@@ -81,53 +66,7 @@ bool msc_app_init(void)
 
   // disable stdout buffered for echoing typing command
   setbuf(stdout, NULL);
-
-  EmbeddedCliConfig *config = embeddedCliDefaultConfig();
-  config->cliBuffer         = cli_buffer;
-  config->cliBufferSize     = CLI_BUFFER_SIZE;
-  config->rxBufferSize      = CLI_RX_BUFFER_SIZE;
-  config->cmdBufferSize     = CLI_CMD_BUFFER_SIZE;
-  config->historyBufferSize = CLI_HISTORY_SIZE;
-  config->maxBindingCount   = CLI_BINDING_COUNT;
-
-  TU_ASSERT(embeddedCliRequiredSize(config) <= CLI_BUFFER_SIZE);
-
-  _cli = embeddedCliNew(config);
-  TU_ASSERT(_cli != NULL);
-
-  _cli->writeChar = cli_write_char;
-
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "cat",
-    "Usage: cat [FILE]...\r\n\tConcatenate FILE(s) to standard output..",
-    true,
-    NULL,
-    cli_cmd_cat
-  });
-
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "cd",
-    "Usage: cd [DIR]...\r\n\tChange the current directory to DIR.",
-    true,
-    NULL,
-    cli_cmd_cd
-  });
-
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "ls",
-    "Usage: ls [DIR]...\r\n\tList information about the FILEs (the current directory by default).",
-    true,
-    NULL,
-    cli_cmd_ls
-  });
-
-  embeddedCliAddBinding(_cli, (CliCommandBinding) {
-    "mkdir",
-    "Usage: mkdir [DIR]...\r\n\tCreate the DIRECTORY(ies), if they do not already exist..",
-    true,
-    NULL,
-    cli_cmd_mkdir
-  });
+  cli_init();
 
   return true;
 }
@@ -330,6 +269,84 @@ DRESULT disk_ioctl (
 // CLI Commands
 //--------------------------------------------------------------------+
 
+void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context);
+
+void cli_write_char(EmbeddedCli *cli, char c)
+{
+  (void) cli;
+  putchar((int) c);
+}
+
+void cli_cmd_unknown(EmbeddedCli *cli, CliCommand *command)
+{
+  (void) cli;
+  printf("%s: command not found\r\n", command->name);
+}
+
+bool cli_init(void)
+{
+  EmbeddedCliConfig *config = embeddedCliDefaultConfig();
+  config->cliBuffer         = cli_buffer;
+  config->cliBufferSize     = CLI_BUFFER_SIZE;
+  config->rxBufferSize      = CLI_RX_BUFFER_SIZE;
+  config->cmdBufferSize     = CLI_CMD_BUFFER_SIZE;
+  config->historyBufferSize = CLI_HISTORY_SIZE;
+  config->maxBindingCount   = CLI_BINDING_COUNT;
+
+  TU_ASSERT(embeddedCliRequiredSize(config) <= CLI_BUFFER_SIZE);
+
+  _cli = embeddedCliNew(config);
+  TU_ASSERT(_cli != NULL);
+
+  _cli->writeChar = cli_write_char;
+
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "cat",
+    "Usage: cat [FILE]...\r\n\tConcatenate FILE(s) to standard output..",
+    true,
+    NULL,
+    cli_cmd_cat
+  });
+
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "cd",
+    "Usage: cd [DIR]...\r\n\tChange the current directory to DIR.",
+    true,
+    NULL,
+    cli_cmd_cd
+  });
+
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "ls",
+    "Usage: ls [DIR]...\r\n\tList information about the FILEs (the current directory by default).",
+    true,
+    NULL,
+    cli_cmd_ls
+  });
+
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "mkdir",
+    "Usage: mkdir DIR...\r\n\tCreate the DIRECTORY(ies), if they do not already exist..",
+    true,
+    NULL,
+    cli_cmd_mkdir
+  });
+
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "mv",
+    "Usage: mv SOURCE DEST...\r\n\tRename SOURCE to DEST",
+    true,
+    NULL,
+    cli_cmd_mv
+  });
+
+  return true;
+}
+
 void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context)
 {
   (void) cli; (void) context;
@@ -433,7 +450,14 @@ void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
         printf("/%s\r\n", fno.fname);
       }else
       {
-        printf("%-40s%lu KB\r\n", fno.fname, fno.fsize / 1000);
+        printf("%-40s", fno.fname);
+        if (fno.fsize < 1024)
+        {
+          printf("%lu B\r\n", fno.fsize);
+        }else
+        {
+          printf("%lu KB\r\n", fno.fsize / 1024);
+        }
       }
     }
   }
@@ -463,3 +487,25 @@ void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context)
     return;
   }
 }
+
+void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context)
+{
+  (void) cli; (void) context;
+
+  uint16_t argc = embeddedCliGetTokenCount(args);
+  if ( argc != 2 )
+  {
+    printf("invalid arguments\r\n");
+    return;
+  }
+
+  // default is current directory
+  const char* src = embeddedCliGetToken(args, 1);
+  const char* dst = embeddedCliGetToken(args, 2);
+
+  if ( FR_OK != f_rename(src, dst) )
+  {
+    printf("cannot mv %s to %s\r\n", src, dst);
+    return;
+  }
+}

From 2312bfe3c4be116403974f922d08e5f5cf8a166c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 20 Nov 2022 16:40:15 +0700
Subject: [PATCH 1229/2085] implement cp command

---
 examples/host/msc_file_explorer/src/msc_app.c | 61 ++++++++++++++++++-
 1 file changed, 59 insertions(+), 2 deletions(-)

diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index f435e6b96..5b9b72d43 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -269,8 +269,9 @@ DRESULT disk_ioctl (
 // CLI Commands
 //--------------------------------------------------------------------+
 
-void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_cp(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context);
@@ -320,6 +321,14 @@ bool cli_init(void)
     cli_cmd_cd
   });
 
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "cp",
+    "Usage: cp SOURCE DEST\r\n\tCopy SOURCE to DEST.",
+    true,
+    NULL,
+    cli_cmd_cp
+  });
+
   embeddedCliAddBinding(_cli, (CliCommandBinding) {
     "ls",
     "Usage: ls [DIR]...\r\n\tList information about the FILEs (the current directory by default).",
@@ -370,7 +379,7 @@ void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context)
       printf("%s: No such file or directory\r\n", fpath);
     }else
     {
-      uint8_t buf[64];
+      uint8_t buf[512];
       size_t count = 0;
       while ( (FR_OK == f_read(&fi, buf, sizeof(buf), &count)) && (count > 0) )
       {
@@ -415,6 +424,54 @@ void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context)
   }
 }
 
+void cli_cmd_cp(EmbeddedCli *cli, char *args, void *context)
+{
+  (void) cli; (void) context;
+
+  uint16_t argc = embeddedCliGetTokenCount(args);
+  if ( argc != 2 )
+  {
+    printf("invalid arguments\r\n");
+    return;
+  }
+
+  // default is current directory
+  const char* src = embeddedCliGetToken(args, 1);
+  const char* dst = embeddedCliGetToken(args, 2);
+
+  FIL f_src;
+  FIL f_dst;
+
+  if ( FR_OK != f_open(&f_src, src, FA_READ) )
+  {
+    printf("cannot stat '%s': No such file or directory\r\n", src);
+    return;
+  }
+
+  if ( FR_OK != f_open(&f_dst, dst, FA_WRITE | FA_CREATE_ALWAYS) )
+  {
+    printf("cannot create '%s'\r\n", dst);
+    return;
+  }else
+  {
+    uint8_t buf[512];
+    size_t rd_count = 0;
+    while ( (FR_OK == f_read(&f_src, buf, sizeof(buf), &rd_count)) && (rd_count > 0) )
+    {
+      size_t wr_count = 0;
+
+      if ( FR_OK != f_write(&f_dst, buf, rd_count, &wr_count) )
+      {
+        printf("cannot write to '%s'\r\n", dst);
+        break;
+      }
+    }
+  }
+
+  f_close(&f_src);
+  f_close(&f_dst);
+}
+
 void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
 {
   (void) cli; (void) context;

From 47bc269b50eb0fab9ac2f708cecdce2e2df601d9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 21 Nov 2022 11:12:10 +0700
Subject: [PATCH 1230/2085] fix build with rp2040 and rx65

---
 examples/host/msc_file_explorer/CMakeLists.txt |  7 ++++++-
 examples/host/msc_file_explorer/src/msc_app.c  | 16 ++++++++--------
 examples/make.mk                               |  3 ++-
 3 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index fc4765cdc..5d443ea9b 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -16,11 +16,16 @@ add_executable(${PROJECT})
 target_sources(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
         ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+        ${TOP}/lib/fatfs/source/ff.c
+        ${TOP}/lib/fatfs/source/ffsystem.c
+        ${TOP}/lib/fatfs/source/ffunicode.c
         )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
+        ${TOP}/lib/fatfs/source
+        ${TOP}/lib/embedded-cli
         )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
@@ -30,7 +35,7 @@ family_configure_host_example(${PROJECT})
 # For rp2040, un-comment to enable pico-pio-usb
 family_add_pico_pio_usb(${PROJECT})
 
-# due to warnings from Pico-PIO-USB
+# due to warnings from Pico-PIO-USB and fatfs
 target_compile_options(${PROJECT} PUBLIC
         -Wno-error=shadow
         -Wno-error=cast-align
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 5b9b72d43..a1822b422 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -205,7 +205,7 @@ DRESULT disk_read (
 	uint8_t const lun = 0;
 
 	_disk_busy[pdrv] = true;
-	tuh_msc_read10(dev_addr, lun, buff, sector, count, disk_io_complete);
+	tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete);
 	wait_for_disk_io(pdrv);
 
 	return RES_OK;
@@ -224,7 +224,7 @@ DRESULT disk_write (
 	uint8_t const lun = 0;
 
 	_disk_busy[pdrv] = true;
-	tuh_msc_write10(dev_addr, lun, buff, sector, count, disk_io_complete);
+	tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete);
 	wait_for_disk_io(pdrv);
 
 	return RES_OK;
@@ -247,11 +247,11 @@ DRESULT disk_ioctl (
       return RES_OK;
 
     case GET_SECTOR_COUNT:
-      *((DWORD*) buff) = tuh_msc_get_block_count(dev_addr, lun);
+      *((DWORD*) buff) = (WORD) tuh_msc_get_block_count(dev_addr, lun);
       return RES_OK;
 
     case GET_SECTOR_SIZE:
-      *((WORD*) buff) = tuh_msc_get_block_size(dev_addr, lun);
+      *((WORD*) buff) = (WORD) tuh_msc_get_block_size(dev_addr, lun);
       return RES_OK;
 
     case GET_BLOCK_SIZE:
@@ -380,10 +380,10 @@ void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context)
     }else
     {
       uint8_t buf[512];
-      size_t count = 0;
+      UINT count = 0;
       while ( (FR_OK == f_read(&fi, buf, sizeof(buf), &count)) && (count > 0) )
       {
-        for(size_t c = 0; c < count; c++)
+        for(UINT c = 0; c < count; c++)
         {
           const char ch = buf[c];
           if (isprint(ch) || iscntrl(ch))
@@ -455,10 +455,10 @@ void cli_cmd_cp(EmbeddedCli *cli, char *args, void *context)
   }else
   {
     uint8_t buf[512];
-    size_t rd_count = 0;
+    UINT rd_count = 0;
     while ( (FR_OK == f_read(&f_src, buf, sizeof(buf), &rd_count)) && (rd_count > 0) )
     {
-      size_t wr_count = 0;
+      UINT wr_count = 0;
 
       if ( FR_OK != f_write(&f_dst, buf, rd_count, &wr_count) )
       {
diff --git a/examples/make.mk b/examples/make.mk
index 47520d660..73a39a8fe 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -113,7 +113,8 @@ CFLAGS += \
   
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
-  CFLAGS += -Og
+  CFLAGS += -O0
+  NO_LTO = 1
 else
   CFLAGS += $(CFLAGS_OPTIMIZED)
 endif

From 51873cd1be5291c15a24054e464d98d4953eebfa Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 21 Nov 2022 11:24:58 +0700
Subject: [PATCH 1231/2085] implement rm command

---
 examples/host/msc_file_explorer/src/msc_app.c | 35 ++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index a1822b422..4500aedd2 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -275,6 +275,7 @@ void cli_cmd_cp(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context);
 
 void cli_write_char(EmbeddedCli *cli, char c)
 {
@@ -347,12 +348,20 @@ bool cli_init(void)
 
   embeddedCliAddBinding(_cli, (CliCommandBinding) {
     "mv",
-    "Usage: mv SOURCE DEST...\r\n\tRename SOURCE to DEST",
+    "Usage: mv SOURCE DEST...\r\n\tRename SOURCE to DEST.",
     true,
     NULL,
     cli_cmd_mv
   });
 
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "rm",
+    "Usage: rm [FILE]...\r\n\tRemove (unlink) the FILE(s).",
+    true,
+    NULL,
+    cli_cmd_rm
+  });
+
   return true;
 }
 
@@ -566,3 +575,27 @@ void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context)
     return;
   }
 }
+
+void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context)
+{
+  (void) cli; (void) context;
+
+  uint16_t argc = embeddedCliGetTokenCount(args);
+
+  // need at least 1 argument
+  if ( argc == 0 )
+  {
+    printf("invalid arguments\r\n");
+    return;
+  }
+
+  for(uint16_t i=0; i<argc; i++)
+  {
+    const char* fpath = embeddedCliGetToken(args, i+1); // token count from 1
+
+    if ( FR_OK != f_unlink(fpath) )
+    {
+      printf("cannot remove '%s': No such file or directory\r\n", fpath);
+    }
+  }
+}

From cab65acc464ca5876bd3682587ee2670268b13d2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 21 Nov 2022 11:52:51 +0700
Subject: [PATCH 1232/2085] add pwd

---
 examples/host/msc_file_explorer/src/main.c    |  8 ++--
 examples/host/msc_file_explorer/src/msc_app.c | 43 +++++++++++++++++--
 lib/fatfs/source/ffconf.h                     |  2 +-
 3 files changed, 43 insertions(+), 10 deletions(-)

diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index f46e5092b..652986b7c 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -43,7 +43,7 @@ int main(void)
 {
   board_init();
 
-  printf("TinyUSB Host MSC Explorer Example\r\n");
+  printf("TinyUSB Host MassStorage Explorer Example\r\n");
 
   // init host stack on configured roothub port
   tuh_init(BOARD_TUH_RHPORT);
@@ -67,14 +67,12 @@ int main(void)
 
 void tuh_mount_cb(uint8_t dev_addr)
 {
-  // application set-up
-  printf("A device with address %d is mounted\r\n", dev_addr);
+  (void) dev_addr;
 }
 
 void tuh_umount_cb(uint8_t dev_addr)
 {
-  // application tear-down
-  printf("A device with address %d is unmounted \r\n", dev_addr);
+  (void) dev_addr;
 }
 
 
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 4500aedd2..6e5cb672a 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -108,7 +108,7 @@ bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const
   uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
 
   printf("Disk Size: %lu MB\r\n", block_count / ((1024*1024)/block_size));
-  printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
+  // printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
 
   // For simplicity: we only mount 1 LUN per device
   uint8_t const drive_num = dev_addr-1;
@@ -120,8 +120,15 @@ bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const
     puts("mount failed");
   }
 
-  f_chdrive(drive_path); // change to newly mounted drive
-  f_chdir("/"); // root as current dir
+  // change to newly mounted drive
+  f_chdir(drive_path);
+
+  // print the drive label
+//  char label[34];
+//  if ( FR_OK == f_getlabel(drive_path, label, NULL) )
+//  {
+//    puts(label);
+//  }
 
   return true;
 }
@@ -137,7 +144,6 @@ void tuh_msc_mount_cb(uint8_t dev_addr)
 
 void tuh_msc_umount_cb(uint8_t dev_addr)
 {
-  (void) dev_addr;
   printf("A MassStorage device is unmounted\r\n");
 
   uint8_t const drive_num = dev_addr-1;
@@ -273,6 +279,7 @@ void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_cd(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_cp(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context);
+void cli_cmd_pwd(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context);
 void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context);
@@ -338,6 +345,14 @@ bool cli_init(void)
     cli_cmd_ls
   });
 
+  embeddedCliAddBinding(_cli, (CliCommandBinding) {
+    "pwd",
+    "Usage: pwd\r\n\tPrint the name of the current working directory.",
+    true,
+    NULL,
+    cli_cmd_pwd
+  });
+
   embeddedCliAddBinding(_cli, (CliCommandBinding) {
     "mkdir",
     "Usage: mkdir DIR...\r\n\tCreate the DIRECTORY(ies), if they do not already exist..",
@@ -531,6 +546,26 @@ void cli_cmd_ls(EmbeddedCli *cli, char *args, void *context)
   f_closedir(&dir);
 }
 
+void cli_cmd_pwd(EmbeddedCli *cli, char *args, void *context)
+{
+  (void) cli; (void) context;
+  uint16_t argc = embeddedCliGetTokenCount(args);
+
+  if (argc != 0)
+  {
+    printf("invalid arguments\r\n");
+    return;
+  }
+
+  char path[256];
+  if (FR_OK != f_getcwd(path, sizeof(path)))
+  {
+    printf("cannot get current working directory\r\n");
+  }
+
+  puts(path);
+}
+
 void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context)
 {
   (void) cli; (void) context;
diff --git a/lib/fatfs/source/ffconf.h b/lib/fatfs/source/ffconf.h
index 9298ef897..96ff77155 100644
--- a/lib/fatfs/source/ffconf.h
+++ b/lib/fatfs/source/ffconf.h
@@ -153,7 +153,7 @@
 /  on character encoding. When LFN is not enabled, these options have no effect. */
 
 
-#define FF_FS_RPATH		1
+#define FF_FS_RPATH		2
 /* This option configures support for relative path.
 /
 /   0: Disable relative path and remove related functions.

From 64ecf43663dcc4f441a4b66c6b07661944ff4d97 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 21 Nov 2022 11:53:15 +0700
Subject: [PATCH 1233/2085] whitespace

---
 src/class/msc/msc_host.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index 7718ad4fe..8d95980f9 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -82,7 +82,7 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_ms
 
 // Perform SCSI Read 10 command. Read n blocks starting from LBA to buffer
 // Complete callback is invoked when SCSI op is complete.
-bool  tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb);
+bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb);
 
 // Perform SCSI Write 10 command. Write n blocks starting from LBA to device
 // Complete callback is invoked when SCSI op is complete.

From 53677d484419d292f1a4841a5c928baddeb1c28a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 21 Nov 2022 12:28:33 +0700
Subject: [PATCH 1234/2085] house keeping

---
 examples/dual/host_hid_to_device_cdc/CMakeLists.txt | 2 +-
 examples/host/CMakeLists.txt                        | 2 ++
 examples/host/bare_api/Makefile                     | 3 ---
 examples/host/cdc_msc_hid/Makefile                  | 9 +++++----
 examples/host/hid_controller/Makefile               | 3 ---
 examples/host/msc_file_explorer/Makefile            | 3 ---
 6 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index fc9bbfc13..724d1e119 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -27,7 +27,7 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_dual_usb_example(${PROJECT})
 
-# due to warnings from other net source, we need to prevent error from some of the warnings options
+# due to warnings from Pico-PIO-USB
 target_compile_options(${PROJECT} PUBLIC
         -Wno-error=shadow
         -Wno-error=cast-align
diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt
index 5c63ec0c0..758973ab2 100644
--- a/examples/host/CMakeLists.txt
+++ b/examples/host/CMakeLists.txt
@@ -6,5 +6,7 @@ project(tinyusb_host_examples)
 family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
 
 # family_add_subdirectory will filter what to actually add based on selected FAMILY
+family_add_subdirectory(bare_api)
 family_add_subdirectory(cdc_msc_hid)
 family_add_subdirectory(hid_controller)
+family_add_subdirectory(msc_file_explorer)
diff --git a/examples/host/bare_api/Makefile b/examples/host/bare_api/Makefile
index 13e14df53..84555a889 100644
--- a/examples/host/bare_api/Makefile
+++ b/examples/host/bare_api/Makefile
@@ -11,9 +11,6 @@ EXAMPLE_SOURCE += \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TODO: suppress warning caused by host stack
-CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
-
 # TinyUSB Host Stack source
 SRC_C += \
 	src/class/cdc/cdc_host.c \
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index 272acbac8..ad28076a0 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -6,11 +6,12 @@ INC += \
 	$(TOP)/hw \
 
 # Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
-SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+EXAMPLE_SOURCE = \
+	src/hid_app.c \
+  src/main.c \
+  src/msc_app.c \
 
-# TODO: suppress warning caused by host stack
-CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 # TinyUSB Host Stack source
 SRC_C += \
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index 06dc56914..e7fbd741f 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -12,9 +12,6 @@ EXAMPLE_SOURCE += \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TODO: suppress warning caused by host stack
-CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
-
 # TinyUSB Host Stack source
 SRC_C += \
 	src/class/cdc/cdc_host.c \
diff --git a/examples/host/msc_file_explorer/Makefile b/examples/host/msc_file_explorer/Makefile
index 518d75063..b0f9959fc 100644
--- a/examples/host/msc_file_explorer/Makefile
+++ b/examples/host/msc_file_explorer/Makefile
@@ -22,9 +22,6 @@ SRC_C += \
   $(FATFS_PATH)/ffsystem.c \
   $(FATFS_PATH)/ffunicode.c \
 
-# TODO: suppress warning caused by host stack
-CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference
-
 # TinyUSB Host Stack source
 SRC_C += \
 	src/class/cdc/cdc_host.c \

From ba9f88f18c222d9e74e483340ade4a420ad49f01 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 21 Nov 2022 12:33:31 +0700
Subject: [PATCH 1235/2085] suppress fatfs cast-qual

---
 examples/host/msc_file_explorer/Makefile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/examples/host/msc_file_explorer/Makefile b/examples/host/msc_file_explorer/Makefile
index b0f9959fc..de2f9c01c 100644
--- a/examples/host/msc_file_explorer/Makefile
+++ b/examples/host/msc_file_explorer/Makefile
@@ -22,6 +22,9 @@ SRC_C += \
   $(FATFS_PATH)/ffsystem.c \
   $(FATFS_PATH)/ffunicode.c \
 
+# suppress warning caused by fatfs
+CFLAGS += -Wno-error=cast-qual
+
 # TinyUSB Host Stack source
 SRC_C += \
 	src/class/cdc/cdc_host.c \

From 460bef9dbb40d1c6990c1bfd2f8da48978550932 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 21 Nov 2022 15:49:38 +0700
Subject: [PATCH 1236/2085] host msc example work well with rp2040 pio-usb

---
 examples/device/board_test/src/main.c         |  2 +-
 examples/host/cdc_msc_hid/CMakeLists.txt      | 14 ++++++++-
 examples/host/cdc_msc_hid/src/main.c          |  8 -----
 examples/host/cdc_msc_hid/src/msc_app.c       |  3 --
 examples/host/cdc_msc_hid/src/tusb_config.h   |  6 ++++
 examples/host/hid_controller/src/hid_app.c    |  1 -
 examples/host/msc_file_explorer/src/main.c    |  2 +-
 examples/host/msc_file_explorer/src/msc_app.c |  5 ++--
 hw/bsp/board.h                                |  8 ++---
 hw/bsp/rp2040/family.c                        | 29 ++++++++++---------
 src/host/usbh.h                               |  2 +-
 11 files changed, 43 insertions(+), 37 deletions(-)

diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index 74beda55f..0289ca15f 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -69,7 +69,7 @@ int main(void)
 
     // echo
     uint8_t ch;
-    if ( board_uart_read(&ch, 1) )
+    if ( board_uart_read(&ch, 1) > 0 )
     {
       board_uart_write(&ch, 1);
     }
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index c4a4d8e63..5b44ef217 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -29,4 +29,16 @@ target_include_directories(${PROJECT} PUBLIC
 family_configure_host_example(${PROJECT})
 
 # For rp2040, un-comment to enable pico-pio-usb
-# family_add_pico_pio_usb(${PROJECT})
+family_add_pico_pio_usb(${PROJECT})
+
+# due to warnings from Pico-PIO-USB
+target_compile_options(${PROJECT} PUBLIC
+        -Wno-error=shadow
+        -Wno-error=cast-align
+        -Wno-error=cast-qual
+        -Wno-error=redundant-decls
+        -Wno-error=sign-conversion
+        -Wno-error=conversion
+        -Wno-error=sign-compare
+        -Wno-error=unused-function
+        )
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index 664cbf035..d26e41e8d 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -54,13 +54,8 @@ int main(void)
     tuh_task();
     led_blinking_task();
 
-#if CFG_TUH_CDC
     cdc_task();
-#endif
-
-#if CFG_TUH_HID
     hid_app_task();
-#endif
   }
 
   return 0;
@@ -69,7 +64,6 @@ int main(void)
 //--------------------------------------------------------------------+
 // USB CDC
 //--------------------------------------------------------------------+
-#if CFG_TUH_CDC
 CFG_TUSB_MEM_SECTION static char serial_in_buffer[64] = { 0 };
 
 // invoked ISR context
@@ -90,8 +84,6 @@ void cdc_task(void)
 
 }
 
-#endif
-
 //--------------------------------------------------------------------+
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c
index 77a72052d..80a5eab6f 100644
--- a/examples/host/cdc_msc_hid/src/msc_app.c
+++ b/examples/host/cdc_msc_hid/src/msc_app.c
@@ -25,8 +25,6 @@
 
 #include "tusb.h"
 
-#if CFG_TUH_MSC
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
@@ -103,4 +101,3 @@ void tuh_msc_umount_cb(uint8_t dev_addr)
 //  }
 }
 
-#endif
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 33f34315b..c515405cb 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -34,6 +34,12 @@
 // Board Specific Configuration
 //--------------------------------------------------------------------+
 
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+#define CFG_TUH_RPI_PIO_USB   0
+#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+#endif
+
 // RHPort number used for host can be defined by board.mk, default to port 0
 #ifndef BOARD_TUH_RHPORT
 #define BOARD_TUH_RHPORT      0
diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index 582e01959..75c91400e 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -162,7 +162,6 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
 void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
 {
   printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
-
 }
 
 // check if different than 2
diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index 652986b7c..ab2cfd498 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -35,6 +35,7 @@
 //--------------------------------------------------------------------+
 void led_blinking_task(void);
 
+// from msc_app.c
 extern bool msc_app_init(void);
 extern void msc_app_task(void);
 
@@ -75,7 +76,6 @@ void tuh_umount_cb(uint8_t dev_addr)
   (void) dev_addr;
 }
 
-
 //--------------------------------------------------------------------+
 // Blinking Task
 //--------------------------------------------------------------------+
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 6e5cb672a..b7c9212ee 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -25,6 +25,7 @@
 
 #include <ctype.h>
 #include "tusb.h"
+#include "bsp/board.h"
 
 #include "ff.h"
 #include "diskio.h"
@@ -75,13 +76,13 @@ void msc_app_task(void)
 {
   if (!_cli) return;
 
-  int ch = getchar();
+  int ch = board_uart_getchar();
   if ( ch > 0 )
   {
     while( ch > 0 )
     {
       embeddedCliReceiveChar(_cli, (char) ch);
-      ch = getchar();
+      ch = board_uart_getchar();
     }
     embeddedCliProcess(_cli);
   }
diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index 0826d7786..52c64a1cc 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -132,15 +132,11 @@ static inline void board_delay(uint32_t ms)
   }
 }
 
+// stdio getchar() is blocking, this is non-blocking version for uart
 static inline int board_uart_getchar(void)
 {
   uint8_t c;
-  return board_uart_read(&c, 1) ? (int) c : (-1);
-}
-
-static inline int board_uart_putchar(uint8_t c)
-{
-  return board_uart_write(&c, 1);
+  return ( board_uart_read(&c, 1) > 0 ) ? (int) c : (-1);
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index ee5a73ff6..d78e2c754 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -121,16 +121,6 @@ static uart_inst_t *uart_inst;
 
 void board_init(void)
 {
-#ifdef LED_PIN
-  bi_decl(bi_1pin_with_name(LED_PIN, "LED"));
-  gpio_init(LED_PIN);
-  gpio_set_dir(LED_PIN, GPIO_OUT);
-#endif
-
-  // Button
-#ifndef BUTTON_BOOTSEL
-#endif
-
 #if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
   // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb
   set_sys_clock_khz(120000, true);
@@ -148,6 +138,16 @@ void board_init(void)
   tuh_configure(BOARD_TUH_RHPORT, TUH_CFGID_RPI_PIO_USB_CONFIGURATION, &pio_cfg);
 #endif
 
+#ifdef LED_PIN
+  bi_decl(bi_1pin_with_name(LED_PIN, "LED"));
+  gpio_init(LED_PIN);
+  gpio_set_dir(LED_PIN, GPIO_OUT);
+#endif
+
+  // Button
+#ifndef BUTTON_BOOTSEL
+#endif
+
 #if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
   bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_TX_PIN, GPIO_FUNC_UART));
   uart_inst = uart_get_instance(UART_DEV);
@@ -192,10 +192,13 @@ uint32_t board_button_read(void)
 int board_uart_read(uint8_t* buf, int len)
 {
 #ifdef UART_DEV
-  for(int i=0;i<len;i++) {
-    buf[i] = uart_getc(uart_inst);
+  int count = 0;
+  while ( (count < len) && uart_is_readable(uart_inst) )
+  {
+    buf[count] = uart_getc(uart_inst);
+    count++;
   }
-  return len;
+  return count;
 #else
   (void) buf; (void) len;
   return 0;
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 560a1ea23..1a26a69b4 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -71,7 +71,7 @@ struct tuh_xfer_s
 // ConfigID for tuh_config()
 enum
 {
-  TUH_CFGID_RPI_PIO_USB_CONFIGURATION = OPT_MCU_RP2040 // cfg_param: pio_usb_configuration_t
+  TUH_CFGID_RPI_PIO_USB_CONFIGURATION = OPT_MCU_RP2040 << 8 // cfg_param: pio_usb_configuration_t
 };
 
 //--------------------------------------------------------------------+

From a394273ed28bdbd9ed5cf4ba94a99204bdd841e9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 21 Nov 2022 16:28:54 +0700
Subject: [PATCH 1237/2085] add board_getchar() for non-blocking getchar()

---
 examples/host/msc_file_explorer/src/msc_app.c | 4 ++--
 hw/bsp/board.c                                | 7 +++++++
 hw/bsp/board.h                                | 8 ++------
 hw/bsp/rp2040/family.c                        | 5 +++++
 4 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index b7c9212ee..aa193f3ce 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -76,13 +76,13 @@ void msc_app_task(void)
 {
   if (!_cli) return;
 
-  int ch = board_uart_getchar();
+  int ch = board_getchar();
   if ( ch > 0 )
   {
     while( ch > 0 )
     {
       embeddedCliReceiveChar(_cli, (char) ch);
-      ch = board_uart_getchar();
+      ch = board_getchar();
     }
     embeddedCliProcess(_cli);
   }
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index a22b462d9..7e96735bd 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -106,6 +106,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
   int rd = (int) SEGGER_RTT_Read(0, buf, count);
   return (rd > 0) ? rd : -1;
 }
+
 #endif
 
 #elif defined(LOGGER_SWO)
@@ -149,3 +150,9 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 }
 
 #endif
+
+int board_getchar(void)
+{
+  char c;
+  return ( sys_read(0, &c, 1) > 0 ) ? (int) c : (-1);
+}
diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index 52c64a1cc..0a10294d0 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -132,12 +132,8 @@ static inline void board_delay(uint32_t ms)
   }
 }
 
-// stdio getchar() is blocking, this is non-blocking version for uart
-static inline int board_uart_getchar(void)
-{
-  uint8_t c;
-  return ( board_uart_read(&c, 1) > 0 ) ? (int) c : (-1);
-}
+// stdio getchar() is blocking, this is non-blocking version
+int board_getchar(void);
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index d78e2c754..26008168d 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -219,6 +219,11 @@ int board_uart_write(void const * buf, int len)
 #endif
 }
 
+int board_getchar(void)
+{
+  return getchar_timeout_us(0);
+}
+
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 // rp2040 implementation will install approriate handler when initializing

From 21d552bbdff19abe3ab46b23468d719be5aa2a55 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 23 Nov 2022 12:30:10 +0700
Subject: [PATCH 1238/2085] allow all host examples to use pico-pio-usb for
 rp2040

---
 examples/host/bare_api/CMakeLists.txt         | 17 ++++++++++--
 examples/host/bare_api/src/tusb_config.h      |  6 +++++
 examples/host/cdc_msc_hid/CMakeLists.txt      | 27 ++++++++++---------
 examples/host/hid_controller/CMakeLists.txt   | 17 ++++++++++--
 .../host/hid_controller/src/tusb_config.h     |  6 +++++
 .../host/msc_file_explorer/CMakeLists.txt     | 27 ++++++++++---------
 6 files changed, 70 insertions(+), 30 deletions(-)

diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index bc04b01a7..019adaacd 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -26,5 +26,18 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
 
-# For rp2040, un-comment to enable pico-pio-usb
-# family_add_pico_pio_usb(${PROJECT})
\ No newline at end of file
+# For rp2040 enable pico-pio-usb
+if(FAMILY STREQUAL "rp2040")
+  family_add_pico_pio_usb(${PROJECT})
+
+  # due to warnings from Pico-PIO-USB
+  target_compile_options(${PROJECT} PUBLIC
+          -Wno-error=shadow
+          -Wno-error=cast-align
+          -Wno-error=cast-qual
+          -Wno-error=redundant-decls
+          -Wno-error=sign-conversion
+          -Wno-error=conversion
+          -Wno-error=unused-function
+          )
+endif()
\ No newline at end of file
diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index ed0aaf7da..701aa6d90 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -34,6 +34,12 @@
 // Board Specific Configuration
 //--------------------------------------------------------------------+
 
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+#define CFG_TUH_RPI_PIO_USB   0
+#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+#endif
+
 // RHPort number used for host can be defined by board.mk, default to port 0
 #ifndef BOARD_TUH_RHPORT
 #define BOARD_TUH_RHPORT      0
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 5b44ef217..870134376 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -28,17 +28,18 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
 
-# For rp2040, un-comment to enable pico-pio-usb
-family_add_pico_pio_usb(${PROJECT})
+# For rp2040 enable pico-pio-usb
+if(FAMILY STREQUAL "rp2040")
+  family_add_pico_pio_usb(${PROJECT})
 
-# due to warnings from Pico-PIO-USB
-target_compile_options(${PROJECT} PUBLIC
-        -Wno-error=shadow
-        -Wno-error=cast-align
-        -Wno-error=cast-qual
-        -Wno-error=redundant-decls
-        -Wno-error=sign-conversion
-        -Wno-error=conversion
-        -Wno-error=sign-compare
-        -Wno-error=unused-function
-        )
+  # due to warnings from Pico-PIO-USB
+  target_compile_options(${PROJECT} PUBLIC
+          -Wno-error=shadow
+          -Wno-error=cast-align
+          -Wno-error=cast-qual
+          -Wno-error=redundant-decls
+          -Wno-error=sign-conversion
+          -Wno-error=conversion
+          -Wno-error=unused-function
+          )
+endif()
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index 6153d399a..aea99e404 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -27,5 +27,18 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
 
-# For rp2040, un-comment to enable pico-pio-usb
-# family_add_pico_pio_usb(${PROJECT})
+# For rp2040 enable pico-pio-usb
+if(FAMILY STREQUAL "rp2040")
+  family_add_pico_pio_usb(${PROJECT})
+
+  # due to warnings from Pico-PIO-USB
+  target_compile_options(${PROJECT} PUBLIC
+          -Wno-error=shadow
+          -Wno-error=cast-align
+          -Wno-error=cast-qual
+          -Wno-error=redundant-decls
+          -Wno-error=sign-conversion
+          -Wno-error=conversion
+          -Wno-error=unused-function
+          )
+endif()
\ No newline at end of file
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index 475b9ca8f..e6d6f873d 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -34,6 +34,12 @@
 // Board Specific Configuration
 //--------------------------------------------------------------------+
 
+ #if CFG_TUSB_MCU == OPT_MCU_RP2040
+// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+#define CFG_TUH_RPI_PIO_USB   0
+#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+#endif
+
 // RHPort number used for host can be defined by board.mk, default to port 0
 #ifndef BOARD_TUH_RHPORT
 #define BOARD_TUH_RHPORT      0
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 5d443ea9b..e51a170d3 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -32,17 +32,18 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
 
-# For rp2040, un-comment to enable pico-pio-usb
-family_add_pico_pio_usb(${PROJECT})
+# For rp2040 enable pico-pio-usb
+if(FAMILY STREQUAL "rp2040")
+  family_add_pico_pio_usb(${PROJECT})
 
-# due to warnings from Pico-PIO-USB and fatfs
-target_compile_options(${PROJECT} PUBLIC
-        -Wno-error=shadow
-        -Wno-error=cast-align
-        -Wno-error=cast-qual
-        -Wno-error=redundant-decls
-        -Wno-error=sign-conversion
-        -Wno-error=conversion
-        -Wno-error=sign-compare
-        -Wno-error=unused-function
-        )
+  # due to warnings from Pico-PIO-USB
+  target_compile_options(${PROJECT} PUBLIC
+          -Wno-error=shadow
+          -Wno-error=cast-align
+          -Wno-error=cast-qual
+          -Wno-error=redundant-decls
+          -Wno-error=sign-conversion
+          -Wno-error=conversion
+          -Wno-error=unused-function
+          )
+endif()

From 7298923927c2955fd67227e3941bde74a2f0c689 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 23 Nov 2022 16:01:48 +0700
Subject: [PATCH 1239/2085] rework tuh_msc_complete_cb_t signature to use new
 tuh_msc_complete_data_t

add user arg to all scsi command API that support complete callback
---
 examples/host/cdc_msc_hid/src/msc_app.c       | 42 ++---------
 examples/host/msc_file_explorer/src/msc_app.c | 15 ++--
 src/class/msc/msc_host.c                      | 69 ++++++++++++-------
 src/class/msc/msc_host.h                      | 23 ++++---
 4 files changed, 74 insertions(+), 75 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c
index 80a5eab6f..797d55f8a 100644
--- a/examples/host/cdc_msc_hid/src/msc_app.c
+++ b/examples/host/cdc_msc_hid/src/msc_app.c
@@ -30,8 +30,11 @@
 //--------------------------------------------------------------------+
 static scsi_inquiry_resp_t inquiry_resp;
 
-bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
+bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
 {
+  msc_cbw_t const* cbw = cb_data->cbw;
+  msc_csw_t const* csw = cb_data->csw;
+
   if (csw->status != 0)
   {
     printf("Inquiry failed\r\n");
@@ -57,47 +60,12 @@ void tuh_msc_mount_cb(uint8_t dev_addr)
   printf("A MassStorage device is mounted\r\n");
 
   uint8_t const lun = 0;
-  tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb);
-//
-//  //------------- file system (only 1 LUN support) -------------//
-//  uint8_t phy_disk = dev_addr-1;
-//  disk_initialize(phy_disk);
-//
-//  if ( disk_is_ready(phy_disk) )
-//  {
-//    if ( f_mount(phy_disk, &fatfs[phy_disk]) != FR_OK )
-//    {
-//      puts("mount failed");
-//      return;
-//    }
-//
-//    f_chdrive(phy_disk); // change to newly mounted drive
-//    f_chdir("/"); // root as current dir
-//
-//    cli_init();
-//  }
+  tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0);
 }
 
 void tuh_msc_umount_cb(uint8_t dev_addr)
 {
   (void) dev_addr;
   printf("A MassStorage device is unmounted\r\n");
-
-//  uint8_t phy_disk = dev_addr-1;
-//
-//  f_mount(phy_disk, NULL); // unmount disk
-//  disk_deinitialize(phy_disk);
-//
-//  if ( phy_disk == f_get_current_drive() )
-//  { // active drive is unplugged --> change to other drive
-//    for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
-//    {
-//      if ( disk_is_ready(i) )
-//      {
-//        f_chdrive(i);
-//        cli_init(); // refractor, rename
-//      }
-//    }
-//  }
 }
 
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index aa193f3ce..5a1635015 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -93,8 +93,11 @@ void msc_app_task(void)
 //--------------------------------------------------------------------+
 
 
-bool inquiry_complete_cb(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
+bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
 {
+  msc_cbw_t const* cbw = cb_data->cbw;
+  msc_csw_t const* csw = cb_data->csw;
+
   if (csw->status != 0)
   {
     printf("Inquiry failed\r\n");
@@ -140,7 +143,7 @@ void tuh_msc_mount_cb(uint8_t dev_addr)
   printf("A MassStorage device is mounted\r\n");
 
   uint8_t const lun = 0;
-  tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb);
+  tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0);
 }
 
 void tuh_msc_umount_cb(uint8_t dev_addr)
@@ -178,9 +181,9 @@ static void wait_for_disk_io(BYTE pdrv)
   }
 }
 
-static bool disk_io_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
+static bool disk_io_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
 {
-  (void) dev_addr; (void) cbw; (void) csw;
+  (void) dev_addr; (void) cb_data;
   _disk_busy[dev_addr-1] = false;
   return true;
 }
@@ -212,7 +215,7 @@ DRESULT disk_read (
 	uint8_t const lun = 0;
 
 	_disk_busy[pdrv] = true;
-	tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete);
+	tuh_msc_read10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete, 0);
 	wait_for_disk_io(pdrv);
 
 	return RES_OK;
@@ -231,7 +234,7 @@ DRESULT disk_write (
 	uint8_t const lun = 0;
 
 	_disk_busy[pdrv] = true;
-	tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete);
+	tuh_msc_write10(dev_addr, lun, buff, sector, (uint16_t) count, disk_io_complete, 0);
 	wait_for_disk_io(pdrv);
 
 	return RES_OK;
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 934f79ff7..9e88ebc30 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -64,6 +64,7 @@ typedef struct
   uint8_t stage;
   void*   buffer;
   tuh_msc_complete_cb_t complete_cb;
+  uintptr_t complete_arg;
 
   msc_cbw_t cbw;
   msc_csw_t csw;
@@ -126,7 +127,7 @@ static inline void cbw_init(msc_cbw_t *cbw, uint8_t lun)
   cbw->lun       = lun;
 }
 
-bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb)
+bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->configured);
@@ -137,13 +138,14 @@ bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tu
   p_msc->stage = MSC_STAGE_CMD;
   p_msc->buffer = data;
   p_msc->complete_cb = complete_cb;
+  p_msc->complete_arg = arg;
 
   TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)));
 
   return true;
 }
 
-bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb)
+bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
 {
    msch_interface_t* p_msc = get_itf(dev_addr);
    TU_VERIFY(p_msc->configured);
@@ -156,10 +158,10 @@ bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_r
   cbw.cmd_len    = sizeof(scsi_read_capacity10_t);
   cbw.command[0] = SCSI_CMD_READ_CAPACITY_10;
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb)
+bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
@@ -178,10 +180,10 @@ bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* respons
   };
   memcpy(cbw.command, &cmd_inquiry, cbw.cmd_len);
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb)
+bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->configured);
@@ -195,10 +197,10 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_
   cbw.command[0]  = SCSI_CMD_TEST_UNIT_READY;
   cbw.command[1]  = lun; // according to wiki TODO need verification
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb, arg);
 }
 
-bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb)
+bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
 {
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
@@ -215,10 +217,10 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_ms
 
   memcpy(cbw.command, &cmd_request_sense, cbw.cmd_len);
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, resposne, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, resposne, complete_cb, arg);
 }
 
-bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb)
+bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
@@ -239,10 +241,10 @@ bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba,
  
   memcpy(cbw.command, &cmd_read10, cbw.cmd_len);
  
-  return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb, arg);
 }
  
-bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb)
+bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
@@ -263,7 +265,7 @@ bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_
 
   memcpy(cbw.command, &cmd_write10, cbw.cmd_len);
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb);
+  return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb, arg);
 }
 
 #if 0
@@ -344,7 +346,17 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
       // SCSI op is complete
       p_msc->stage = MSC_STAGE_IDLE;
 
-      if (p_msc->complete_cb) p_msc->complete_cb(dev_addr, cbw, csw);
+      if (p_msc->complete_cb)
+      {
+        tuh_msc_complete_data_t const cb_data =
+        {
+          .cbw = cbw,
+          .csw = csw,
+          .scsi_data = p_msc->buffer,
+          .user_arg = p_msc->complete_arg
+        };
+        p_msc->complete_cb(dev_addr, &cb_data);
+      }
     break;
 
     // unknown state
@@ -359,9 +371,9 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 //--------------------------------------------------------------------+
 
 static void config_get_maxlun_complete (tuh_xfer_t* xfer);
-static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
-static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
-static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
+static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data);
+static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
+static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
 
 bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
@@ -446,37 +458,46 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer)
   // TODO multiple LUN support
   TU_LOG2("SCSI Test Unit Ready\r\n");
   uint8_t const lun = 0;
-  tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete);
+  tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0);
 }
 
-static bool config_test_unit_ready_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
+static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
 {
+  msc_cbw_t const* cbw = cb_data->cbw;
+  msc_csw_t const* csw = cb_data->csw;
+
   if (csw->status == 0)
   {
     // Unit is ready, read its capacity
     TU_LOG2("SCSI Read Capacity\r\n");
-    tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete);
+    tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0);
   }else
   {
     // Note: During enumeration, some device fails Test Unit Ready and require a few retries
     // with Request Sense to start working !!
     // TODO limit number of retries
     TU_LOG2("SCSI Request Sense\r\n");
-    TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete));
+    TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete, 0));
   }
 
   return true;
 }
 
-static bool config_request_sense_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
+static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
 {
+  msc_cbw_t const* cbw = cb_data->cbw;
+  msc_csw_t const* csw = cb_data->csw;
+
   TU_ASSERT(csw->status == 0);
-  TU_ASSERT(tuh_msc_test_unit_ready(dev_addr, cbw->lun, config_test_unit_ready_complete));
+  TU_ASSERT(tuh_msc_test_unit_ready(dev_addr, cbw->lun, config_test_unit_ready_complete, 0));
   return true;
 }
 
-static bool config_read_capacity_complete(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw)
+static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
 {
+  msc_cbw_t const* cbw = cb_data->cbw;
+  msc_csw_t const* csw = cb_data->csw;
+
   TU_ASSERT(csw->status == 0);
 
   msch_interface_t* p_msc = get_itf(dev_addr);
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index 8d95980f9..416e4318b 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -41,7 +41,14 @@
 #define CFG_TUH_MSC_MAXLUN  4
 #endif
 
-typedef bool (*tuh_msc_complete_cb_t)(uint8_t dev_addr, msc_cbw_t const* cbw, msc_csw_t const* csw);
+typedef struct {
+  msc_cbw_t const* cbw; // SCSI command
+  msc_csw_t const* csw; // SCSI status
+  void* scsi_data;      // SCSI Data
+  uintptr_t user_arg;   // user argument
+}tuh_msc_complete_data_t;
+
+typedef bool (*tuh_msc_complete_cb_t)(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
 
 //--------------------------------------------------------------------+
 // Application API
@@ -66,33 +73,33 @@ uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun);
 // Perform a full SCSI command (cbw, data, csw) in non-blocking manner.
 // Complete callback is invoked when SCSI op is complete.
 // return true if success, false if there is already pending operation.
-bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb);
+bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Inquiry command
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb);
+bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Test Unit Ready command
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb);
+bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Request Sense 10 command
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb);
+bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Read 10 command. Read n blocks starting from LBA to buffer
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb);
+bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Write 10 command. Write n blocks starting from LBA to device
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb);
+bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Read Capacity 10 command
 // Complete callback is invoked when SCSI op is complete.
 // Note: during enumeration, host stack already carried out this request. Application can retrieve capacity by
 // simply call tuh_msc_get_block_count() and tuh_msc_get_block_size()
-bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb);
+bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 //------------- Application Callback -------------//
 

From 9825fbe9ac69cea94942361ac47080b7f5a0a1cd Mon Sep 17 00:00:00 2001
From: rppicomidi <rppicomidi@gmail.com>
Date: Wed, 23 Nov 2022 13:12:31 -0800
Subject: [PATCH 1240/2085] Fix RP2040 Issue 1721

---
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 25c013bd2..d7895175e 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -155,7 +155,9 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo
   // For now: skip double buffered for Device mode, OUT endpoint since
   // host could send < 64 bytes and cause short packet on buffer0
   // NOTE this could happen to Host mode IN endpoint
-  bool const force_single = !(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr);
+  // Also, Host mode interrupt endpoint hardware is only single buffered
+  bool const force_single = (!(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr)) ||
+    ((usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && tu_edpt_number(ep->ep_addr) != 0);
 
   if(ep->remaining_len && !force_single)
   {

From 8ef32617ba43120b63de64149d221c792f1f0752 Mon Sep 17 00:00:00 2001
From: Adrian Scripca <benishor@gmail.com>
Date: Thu, 24 Nov 2022 13:06:25 +0200
Subject: [PATCH 1241/2085] Added board description for electro-smith daisy
 seed

---
 hw/bsp/stm32h7/boards/daisyseed/board.h       | 140 ++++++++++++++
 hw/bsp/stm32h7/boards/daisyseed/board.mk      |  14 ++
 .../boards/daisyseed/stm32h750ibkx_flash.ld   | 176 ++++++++++++++++++
 .../boards/daisyseed/stm32h750ibkx_ram.ld     | 173 +++++++++++++++++
 4 files changed, 503 insertions(+)
 create mode 100644 hw/bsp/stm32h7/boards/daisyseed/board.h
 create mode 100644 hw/bsp/stm32h7/boards/daisyseed/board.mk
 create mode 100644 hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld
 create mode 100644 hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_ram.ld

diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.h b/hw/bsp/stm32h7/boards/daisyseed/board.h
new file mode 100644
index 000000000..579c09727
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.h
@@ -0,0 +1,140 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              GPIOC
+#define LED_PIN               GPIO_PIN_7
+#define LED_STATE_ON          1
+
+// Blue push-button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+// UART
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOB
+#define UART_GPIO_AF          GPIO_AF7_USART3
+#define UART_TX_PIN           GPIO_PIN_10
+#define UART_RX_PIN           GPIO_PIN_11
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     0
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32h7_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+  /*!< Supply configuration update enable */
+  /* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */
+//  HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+  /* The voltage scaling allows optimizing the power consumption when the
+     device is clocked below the maximum system frequency, to update the
+     voltage scaling value regarding system frequency refer to product
+     datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+
+  /* PLL1 for System Clock */
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 160;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* PLL3 for USB Clock */
+  PeriphClkInitStruct.PLL3.PLL3M = 25;
+  PeriphClkInitStruct.PLL3.PLL3N = 336;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.PLL3.PLL3P = 2;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+  PeriphClkInitStruct.PLL3.PLL3Q = 7;
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+  /* Select PLL as system clock source and configure  bus clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
+  RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_D3PCLK1);
+
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+
+  /*activate CSI clock mondatory for I/O Compensation Cell*/
+  __HAL_RCC_CSI_ENABLE() ;
+
+  /* Enable SYSCFG clock mondatory for I/O Compensation Cell */
+  __HAL_RCC_SYSCFG_CLK_ENABLE() ;
+
+  /* Enables the I/O Compensation Cell */
+  HAL_EnableCompensationCell();
+}
+
+static inline void board_stm32h7_post_init(void)
+{
+  // For this board does nothing
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.mk b/hw/bsp/stm32h7/boards/daisyseed/board.mk
new file mode 100644
index 000000000..68c62968e
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=16000000
+
+# Default is FulSpeed port
+PORT ?= 0
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h750xx.s
+LD_FILE = $(BOARD_PATH)/stm32h750ibkx_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h750ibk6_m7
+
+# flash target using on-board stlink
+flash: flash-stlink
+
diff --git a/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld
new file mode 100644
index 000000000..83904067a
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld
@@ -0,0 +1,176 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32H7 series
+**                128Kbytes FLASH and 1056Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x2000 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x4000 ; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 128K
+  DTCMRAM (xrw)  : ORIGIN = 0x20000000, LENGTH = 128K
+  RAM_D1 (xrw)   : ORIGIN = 0x24000000, LENGTH = 512K
+  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K
+  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K
+  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM_D1 AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM_D1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM_D1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_ram.ld b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_ram.ld
new file mode 100644
index 000000000..16f48b10a
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_ram.ld
@@ -0,0 +1,173 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld (debug in RAM dedicated)
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32H7 series
+**                128Kbytes RAM_EXEC and 544Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x2000 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x4000 ; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  RAM_EXEC (xrw)  : ORIGIN = 0x24000000, LENGTH = 128K
+  DTCMRAM (xrw)   : ORIGIN = 0x20000000, LENGTH = 128K
+  RAM_D2 (xrw)    : ORIGIN = 0x30000000, LENGTH = 288K
+  RAM_D3 (xrw)    : ORIGIN = 0x38000000, LENGTH = 64K
+  ITCMRAM (xrw)   : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into RAM_EXEC */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >RAM_EXEC
+
+  /* The program code and other data goes into RAM_EXEC */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >RAM_EXEC
+
+  /* Constant data goes into RAM_EXEC */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >RAM_EXEC
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >RAM_EXEC
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >RAM_EXEC
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >RAM_EXEC
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >RAM_EXEC
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >DTCMRAM AT> RAM_EXEC
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >DTCMRAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >DTCMRAM
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

From 9ccfb384e8dcbed314c25af698969bb5a17f3810 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Thu, 24 Nov 2022 12:17:55 +0000
Subject: [PATCH 1242/2085] Update to v2.6.0 library

---
 hw/mcu/bridgetek/ft9xx/ft90x-sdk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/bridgetek/ft9xx/ft90x-sdk b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
index e8122eb6b..c810d1312 160000
--- a/hw/mcu/bridgetek/ft9xx/ft90x-sdk
+++ b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
@@ -1 +1 @@
-Subproject commit e8122eb6bd6286a1fe31f175a3e3eb0e7770c3e3
+Subproject commit c810d1312ded923c3c2ed9035c97bd0db4f35b5f

From 5785467016f4f2d0f5e52cec70f4f2328a5d326a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Nov 2022 23:21:17 +0700
Subject: [PATCH 1243/2085] update pico-pio-usb submodule and its warnings
 suppress

---
 examples/host/bare_api/CMakeLists.txt          | 4 ----
 examples/host/cdc_msc_hid/CMakeLists.txt       | 4 ----
 examples/host/hid_controller/CMakeLists.txt    | 4 ----
 examples/host/msc_file_explorer/CMakeLists.txt | 4 ----
 hw/mcu/raspberry_pi/Pico-PIO-USB               | 2 +-
 5 files changed, 1 insertion(+), 17 deletions(-)

diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 019adaacd..31a8aa222 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -32,12 +32,8 @@ if(FAMILY STREQUAL "rp2040")
 
   # due to warnings from Pico-PIO-USB
   target_compile_options(${PROJECT} PUBLIC
-          -Wno-error=shadow
-          -Wno-error=cast-align
           -Wno-error=cast-qual
-          -Wno-error=redundant-decls
           -Wno-error=sign-conversion
           -Wno-error=conversion
-          -Wno-error=unused-function
           )
 endif()
\ No newline at end of file
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 870134376..d84457bc9 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -34,12 +34,8 @@ if(FAMILY STREQUAL "rp2040")
 
   # due to warnings from Pico-PIO-USB
   target_compile_options(${PROJECT} PUBLIC
-          -Wno-error=shadow
-          -Wno-error=cast-align
           -Wno-error=cast-qual
-          -Wno-error=redundant-decls
           -Wno-error=sign-conversion
           -Wno-error=conversion
-          -Wno-error=unused-function
           )
 endif()
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index aea99e404..39adf9093 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -33,12 +33,8 @@ if(FAMILY STREQUAL "rp2040")
 
   # due to warnings from Pico-PIO-USB
   target_compile_options(${PROJECT} PUBLIC
-          -Wno-error=shadow
-          -Wno-error=cast-align
           -Wno-error=cast-qual
-          -Wno-error=redundant-decls
           -Wno-error=sign-conversion
           -Wno-error=conversion
-          -Wno-error=unused-function
           )
 endif()
\ No newline at end of file
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index e51a170d3..326286b3f 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -38,12 +38,8 @@ if(FAMILY STREQUAL "rp2040")
 
   # due to warnings from Pico-PIO-USB
   target_compile_options(${PROJECT} PUBLIC
-          -Wno-error=shadow
-          -Wno-error=cast-align
           -Wno-error=cast-qual
-          -Wno-error=redundant-decls
           -Wno-error=sign-conversion
           -Wno-error=conversion
-          -Wno-error=unused-function
           )
 endif()
diff --git a/hw/mcu/raspberry_pi/Pico-PIO-USB b/hw/mcu/raspberry_pi/Pico-PIO-USB
index f78dc9b2c..52805e6d9 160000
--- a/hw/mcu/raspberry_pi/Pico-PIO-USB
+++ b/hw/mcu/raspberry_pi/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit f78dc9b2c7fa9b82587e43babdc1d21294a32985
+Subproject commit 52805e6d92556e67d3738bd8fb10227a45b13a08

From b2a3f33046fe736557ad1a4bc9c0da76e47e68f3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Nov 2022 23:22:10 +0700
Subject: [PATCH 1244/2085] Retry a few times with transfers in enumeration
 since device can be unstable when starting up

---
 src/common/tusb_types.h |  2 +-
 src/host/usbh.c         | 24 +++++++++++++++++++-----
 src/host/usbh.h         | 12 ++++++++----
 3 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index e11f08dd1..1bfa7c7d1 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -225,7 +225,7 @@ enum {
 
 typedef enum
 {
-  XFER_RESULT_SUCCESS,
+  XFER_RESULT_SUCCESS = 0,
   XFER_RESULT_FAILED,
   XFER_RESULT_STALLED,
   XFER_RESULT_TIMEOUT,
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 9d618db92..a5abac843 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -620,9 +620,7 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result)
     .user_data   = _ctrl_xfer.user_data
   };
 
-  usbh_lock();
-  _ctrl_xfer.stage = CONTROL_STAGE_IDLE;
-  usbh_unlock();
+  _set_control_xfer_stage(CONTROL_STAGE_IDLE);
 
   if (xfer_temp.complete_cb)
   {
@@ -1182,12 +1180,28 @@ static void enum_full_complete(void);
 // process device enumeration
 static void process_enumeration(tuh_xfer_t* xfer)
 {
+  // Retry a few times with transfers in enumeration since device can be unstable when starting up
+  enum {
+    ATTEMPT_COUNT_MAX = 3,
+    ATTEMPT_DELAY_MS = 10
+  };
+  static uint8_t failed_count = 0;
+
   if (XFER_RESULT_SUCCESS != xfer->result)
   {
-    // stop enumeration, maybe we could retry this
-    enum_full_complete();
+    // retry if not reaching max attempt
+    if ( failed_count < ATTEMPT_COUNT_MAX )
+    {
+      failed_count++;
+      osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit
+      TU_ASSERT(tuh_control_xfer(xfer), );
+    }else
+    {
+      enum_full_complete();
+    }
     return;
   }
+  failed_count = 0;
 
   uint8_t const daddr = xfer->daddr;
   uintptr_t const state = xfer->user_data;
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 1a26a69b4..37de7093c 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -51,14 +51,15 @@ struct tuh_xfer_s
 {
   uint8_t daddr;
   uint8_t ep_addr;
-
+  uint8_t TU_RESERVED;      // reserved
   xfer_result_t result;
+
   uint32_t actual_len;      // excluding setup packet
 
   union
   {
     tusb_control_request_t const* setup; // setup packet pointer if control transfer
-    uint32_t buflen;        // expected length if not control transfer (not available in callback)
+    uint32_t buflen;                     // expected length if not control transfer (not available in callback)
   };
 
   uint8_t* buffer;           // not available in callback if not control transfer
@@ -80,10 +81,13 @@ enum
 
 //TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device);
 
-// Invoked when device is mounted (configured)
+// Invoked when a device is mounted (configured)
 TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);
 
-/// Invoked when device is unmounted (bus reset/unplugged)
+// Invoked when a device failed to mount during enumeration process
+// TU_ATTR_WEAK void tuh_mount_failed_cb (uint8_t daddr);
+
+/// Invoked when a device is unmounted (detached)
 TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
 
 //--------------------------------------------------------------------+

From be6f6f2c99dde762a70c1c3206e75f5765039bf1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Nov 2022 23:43:52 +0700
Subject: [PATCH 1245/2085] increase delay between attempts to 100ms

---
 src/host/usbh.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index a5abac843..d97b160c9 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1183,7 +1183,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
   // Retry a few times with transfers in enumeration since device can be unstable when starting up
   enum {
     ATTEMPT_COUNT_MAX = 3,
-    ATTEMPT_DELAY_MS = 10
+    ATTEMPT_DELAY_MS = 100
   };
   static uint8_t failed_count = 0;
 

From 1fce76ad472fe1936eedea0688960c76bd42fd40 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Mon, 28 Nov 2022 17:41:00 +0000
Subject: [PATCH 1246/2085] Fix issue with the CDC SetLineCoding request

The SetLineCoding would fail as host would send the SETUP OUT phase before tinyUSB had setup a transaction for it. ft9xx port would ignore the transfer since there was no valid transaction setup for it. One SETUP data phase packet is cached now.
---
 .../cdc_dual_ports/src/usb_descriptors.c      |  2 +-
 hw/bsp/brtmm90x/family.c                      | 17 +++-
 hw/bsp/brtmm90x/family.mk                     | 10 +--
 hw/mcu/bridgetek/ft9xx/ft90x-sdk              |  2 +-
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c      | 82 +++++++++++++++----
 5 files changed, 87 insertions(+), 26 deletions(-)

diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index cda1b63b6..9f212c78f 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -97,7 +97,7 @@ enum
   #define EPNUM_CDC_1_OUT     0x05
   #define EPNUM_CDC_1_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X || CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
   // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_0_NOTIF   0x81
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 6b3c1f56c..77a03e909 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -27,8 +27,8 @@
 #include "bsp/board.h"
 #include "board.h"
 
-#include <registers/ft900_registers.h>
 #include <ft900.h>
+#include <registers/ft900_registers.h>
 
 #if CFG_TUD_ENABLED
 int8_t board_ft90x_vbus(void); // Board specific implementation of VBUS detection for USB device.
@@ -213,3 +213,18 @@ uint32_t board_millis(void)
 
     return safe_ms;
 }
+
+// Restart the program
+// Called in the event of a watchdog timeout
+void chip_reboot(void)
+{
+    // SOFT reset
+    __asm__("call 0");
+ #if 0
+    // HARD reset
+    // Initiates data transfer from Flash Memory to Data Memory (DBG_CMDF2D3)
+    // followed by a system reboot
+ 	dbg_memory_copy(0xfe, 0, 0, 255);
+#endif
+}
+
diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index 3933f15cc..a476cfc06 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -21,7 +21,7 @@ endif
 
 # Add include files which are within the TinyUSB directory structure.
 INC += \
-	$(TOP)/$(BOARD_PATH)
+	$(TOP)/$(BOARD_PATH) 
 
 # Add required C Compiler flags for FT90X.
 CFLAGS += \
@@ -30,14 +30,14 @@ CFLAGS += \
 	-fvar-tracking-assignments \
 	-fmessage-length=0 \
 	-ffunction-sections \
-	-DCFG_TUSB_MCU=OPT_MCU_FT90X
+	-DCFG_TUSB_MCU=OPT_MCU_FT90X 
+
+# Maximum USB device speed supported by the board
+CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
 
 # lwip/src/core/raw.c:334:43: error: declaration of 'recv' shadows a global declaration
 CFLAGS += -Wno-error=shadow
 
-# Add include files outside the TinyUSB structure that are added manually.
-CFLAGS += -I"$(FT9XX_SDK)/include"
-
 # Set Linker flags.
 LD_FILE = hw/mcu/bridgetek/ft9xx/scripts/ldscript.ld
 LDFLAGS += $(addprefix -L,$(LDINC)) \
diff --git a/hw/mcu/bridgetek/ft9xx/ft90x-sdk b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
index c810d1312..0ea80ceaf 160000
--- a/hw/mcu/bridgetek/ft9xx/ft90x-sdk
+++ b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
@@ -1 +1 @@
-Subproject commit c810d1312ded923c3c2ed9035c97bd0db4f35b5f
+Subproject commit 0ea80ceafdf32e4e496cacc94178417e2ef4bf9c
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 2445593fe..080d633fa 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -38,9 +38,6 @@
 #include <ft900.h>
 #include <registers/ft900_registers.h>
 
-#include "board.h"
-#include "bsp/board.h"
-
 #define USBD_USE_STREAMS
 
 #include "device/dcd.h"
@@ -53,14 +50,20 @@
 extern int8_t board_ft90x_vbus(void);
 
 // Static array to store an incoming SETUP request for processing by tinyusb.
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
 static uint8_t _ft90x_setup_packet[8];
 
+// Static array to store one SETUP DATA packet until required by dcd_edpt_xfer.
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
+static uint8_t _ft90x_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
+static uint8_t _ft90x_ctrl_buf_complete;
+
 struct ft90x_xfer_state
 {
   volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
-  volatile int16_t total_size; // Total transfer size in bytes for this transfer.
-  volatile int16_t remain_size; // Total remaining in transfer.
-  volatile uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
+  int16_t total_size; // Total transfer size in bytes for this transfer.
+  int16_t remain_size; // Total remaining in transfer.
+  uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
 
   uint8_t type; // Endpoint type. Of type USBD_ENDPOINT_TYPE from endpoint descriptor.
   uint8_t dir; // Endpoint direction. TUSB_DIR_OUT or TUSB_DIR_IN. For control endpoint this is the current direction.
@@ -766,13 +769,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     USBD_EP_CR_REG(USBD_EP_0) = (ep_reg_size << BIT_USBD_EP0_MAX_SIZE);
   }
 
+  CRITICAL_SECTION_BEGIN
   // Store the endpoint characteristics for later reference.
   ep_xfer[ep_number].dir = ep_dir;
   ep_xfer[ep_number].type = ep_type;
   ep_xfer[ep_number].size = ep_size;
   ep_xfer[ep_number].buff_size = ep_buff_size;
 
-  CRITICAL_SECTION_BEGIN
   // Clear register transaction continuation and signalling state.
   ep_xfer[ep_number].valid = 0;
   ep_xfer[ep_number].buff_ptr = NULL;
@@ -809,12 +812,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
   // Transfer currently in progress.
   if (ep_xfer[ep_number].valid == 0)
   {
-    status = true;
-
     ep_xfer[ep_number].total_size = total_bytes;
     ep_xfer[ep_number].remain_size = total_bytes;
     ep_xfer[ep_number].buff_ptr = buffer;
-    ep_xfer[ep_number].valid = 1;
     
     if (ep_number == USBD_EP_0)
     {
@@ -835,10 +835,33 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
 
       ep_xfer[ep_number].buff_ptr += xfer_bytes;
       ep_xfer[ep_number].remain_size -= xfer_bytes;
+
+      // Tell the interrupt handler to signal dcd_event_xfer_complete on completion.
+      ep_xfer[ep_number].valid = 1;
     }
+    else
+    {
+      // For OUT transfers on the control endpoint.
+      // The host may already have performed the first data transfer after the SETUP packet
+      // before the transfer is setup for it.
+      if ((ep_number == USBD_EP_0) && (_ft90x_ctrl_buf_complete))
+      {
+        // Pull the received data packet from the packet cache and complete the transfer
+        // immediately.
+        memcpy(buffer, _ft90x_ctrl_buf, _ft90x_ctrl_buf_complete);
+        dcd_event_xfer_complete(BOARD_TUD_RHPORT, TUSB_DIR_OUT, _ft90x_ctrl_buf_complete, XFER_RESULT_SUCCESS, false);
+      }
+      else
+      {
+        // Tell the interrupt handler to wait for the packet to be received.
+        ep_xfer[ep_number].valid = 1;
+      }
+    } 
+    status = true;
   }
+
   CRITICAL_SECTION_END
-  
+
   return status;
 }
 
@@ -899,7 +922,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
 void _ft90x_usbd_ISR(void)
 {
-  tud_int_handler(BOARD_TUD_RHPORT); // Resolves to dcd_int_handler().
+  dcd_int_handler(BOARD_TUD_RHPORT);
 }
 
 void dcd_int_handler(uint8_t rhport)
@@ -962,7 +985,6 @@ void dcd_int_handler(uint8_t rhport)
     {
       // Clear interrupt register.
       USBD_REG(epif) = MASK_USBD_EPIF_EP0IRQ;
-
       // Test for an incoming SETUP request on the control endpoint.
       if (USBD_EP_SR_REG(USBD_EP_0) & MASK_USBD_EP0SR_SETUP)
       {
@@ -976,7 +998,7 @@ void dcd_int_handler(uint8_t rhport)
           USBD_EP_SR_REG(USBD_EP_0) = MASK_USBD_EP0SR_STALL;
         }
 
-        // Host has sent a SETUP packet. Recieve this into the setup packet store.
+        // Host has sent a SETUP packet. Recieve this into the SETUP packet store.
         _ft90x_dusb_out(USBD_EP_0, (uint8_t *)_ft90x_setup_packet, sizeof(USB_device_request));
         
         // Send the packet to tinyusb.
@@ -985,6 +1007,9 @@ void dcd_int_handler(uint8_t rhport)
         // Clear the interrupt that signals a SETUP packet is received.
         USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_SETUP);
 
+        // Invalidate cache packet.
+        _ft90x_ctrl_buf_complete = 0;
+
         // Allow new transfers on the control endpoint.
         ep_xfer[USBD_EP_0].valid = 0;
         return;
@@ -998,15 +1023,36 @@ void dcd_int_handler(uint8_t rhport)
 
           // Transfer incoming data from an OUT packet to the buffer supplied.        
           if (ep_xfer[USBD_EP_0].dir == TUSB_DIR_OUT)
-          { 
-            xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, (uint8_t *)ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
+          {
+            xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
           }
           // Now signal completion of data packet.
           dcd_event_xfer_complete(BOARD_TUD_RHPORT, (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true);
 
+          // Invalidate cache packet.
+          _ft90x_ctrl_buf_complete = 0;
+
           // Allow new transfers on the control endpoint.
           ep_xfer[USBD_EP_0].valid = 0;
         }
+        else
+        {
+          // We have received a data packet on the control endpoint without a transfer
+          // being initialised. This can be because the host has sent this packet before
+          // a new transfer has been initiated on the control endpoint.
+          // We will cache upto the maximum packet size for the control endpoint and
+          // use it later in dcd_edpt_xfer.
+          xfer_bytes = CFG_TUD_ENDPOINT0_SIZE;
+
+          // Transfer incoming data from an OUT packet to the cache packet.
+          xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, _ft90x_ctrl_buf, xfer_bytes);
+          
+          // Set the size of the cache packet.
+          _ft90x_ctrl_buf_complete = xfer_bytes;
+        }
+
+        // Clear the interrupt that signals a SETUP DATA packet is received.
+        USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_OPRDY);
       }
     }
     else // !(epif & MASK_USBD_EPIF_EP0IRQ)
@@ -1035,7 +1081,7 @@ void dcd_int_handler(uint8_t rhport)
           if (ep_xfer[ep_number].dir == TUSB_DIR_OUT)
           {
             xfer_bytes = _ft90x_edpt_xfer_out(ep_number, 
-                            (uint8_t *)ep_xfer[ep_number].buff_ptr, 
+                            ep_xfer[ep_number].buff_ptr, 
                             (uint16_t)ep_xfer[ep_number].remain_size);
 
             ep_xfer[ep_number].buff_ptr += xfer_bytes;
@@ -1047,7 +1093,7 @@ void dcd_int_handler(uint8_t rhport)
             if (ep_xfer[ep_number].remain_size > 0)
             {
               xfer_bytes = _ft90x_edpt_xfer_in(ep_number, 
-                            (uint8_t *)ep_xfer[ep_number].buff_ptr, 
+                            ep_xfer[ep_number].buff_ptr, 
                             (uint16_t)ep_xfer[ep_number].remain_size);
 
               ep_xfer[ep_number].buff_ptr += xfer_bytes;

From 7d8d3eca730552355b5ad442f58b5a6b070d4d03 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Tue, 29 Nov 2022 18:49:23 +0000
Subject: [PATCH 1247/2085] Fix transfers issues with FT9xx

Correct USB FIFO use for setup data phases (OUT transfers). We cannot stop traffic on the control endpoint so we set a flag and pull data from host when tinyUSB requests it from the USB FIFO. Extend this for all endpoints although currently not required.
Rename all instances of ft90x which can apply to ft93x as ft9xx.
Add support for the cdc_dual_ports example for ft9xx.
Add LED pin definition for board LED in a simple to access place on the Bridgetek MM900EVx boards.
---
 .../cdc_dual_ports/src/usb_descriptors.c      |  12 +-
 hw/bsp/brtmm90x/boards/mm900evxb/board.h      |  18 +-
 hw/bsp/brtmm90x/family.c                      |  22 +-
 hw/bsp/brtmm90x/family.mk                     |   6 +-
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c      | 225 ++++++++++--------
 5 files changed, 167 insertions(+), 116 deletions(-)

diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index 9f212c78f..5a8dea553 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -97,7 +97,7 @@ enum
   #define EPNUM_CDC_1_OUT     0x05
   #define EPNUM_CDC_1_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X || CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
   // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_0_NOTIF   0x81
@@ -108,6 +108,16 @@ enum
   #define EPNUM_CDC_1_OUT     0x05
   #define EPNUM_CDC_1_IN      0x86
 
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_NOTIF     0x81
+  #define EPNUM_CDC_OUT       0x02
+  #define EPNUM_CDC_IN        0x83
+
+  #define EPNUM_MSC_OUT       0x04
+  #define EPNUM_MSC_IN        0x85
+
 #else
   #define EPNUM_CDC_0_NOTIF   0x81
   #define EPNUM_CDC_0_OUT     0x02
diff --git a/hw/bsp/brtmm90x/boards/mm900evxb/board.h b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
index 57936fda5..930cb9d33 100644
--- a/hw/bsp/brtmm90x/boards/mm900evxb/board.h
+++ b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
@@ -27,20 +27,28 @@
 #ifndef BOARD_H_
 #define BOARD_H_
 
-// Note: This definition file covers all MM900EV1B, MM900EV2B, and MM900EV3B boards.
+// Note: This definition file covers all MM900EV1B, MM900EV2B, MM900EV3B,
+// MM900EV-Lite boards.
 // Each of these boards has an FT900 device.
 
 #ifdef __cplusplus
  extern "C" {
 #endif
 
-#define GPIO_UART0_TX 48
-#define GPIO_UART0_RX 49
-#define GPIO_ETH_LED0 61
-#define GPIO_ETH_LED1 62
+// UART is on connector CN1.
+#define GPIO_UART0_TX 48 // Pin 4 of CN1.
+#define GPIO_UART0_RX 49 // Pin 6 of CN1.
+
+// LED is connected to pins 4 (signal) and 2 (GND) of CN2.
+#define GPIO_LED 36
+
+// Remote wakeup is wired to pin 40 of CN1.
 #define GPIO_REMOTE_WAKEUP_PIN 18
+
+// USB VBus signal is connected directly to the FT900.
 #define USBD_VBUS_DTC_PIN 3
 
+// Enable the Remote Wakeup signalling.
 #define GPIO_REMOTE_WAKEUP
 
 #ifdef __cplusplus
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 77a03e909..cc28cb69b 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -31,8 +31,8 @@
 #include <registers/ft900_registers.h>
 
 #if CFG_TUD_ENABLED
-int8_t board_ft90x_vbus(void); // Board specific implementation of VBUS detection for USB device.
-extern void ft90x_usbd_pm_ISR(uint16_t pmcfg); // Interrupt handler for USB device power management
+int8_t board_ft9xx_vbus(void); // Board specific implementation of VBUS detection for USB device.
+extern void ft9xx_usbd_pm_ISR(uint16_t pmcfg); // Interrupt handler for USB device power management
 #endif
 
 #ifdef GPIO_REMOTE_WAKEUP
@@ -64,12 +64,10 @@ void board_init(void)
     // Use sizeof to avoid pulling in strlen unnecessarily.
     board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG));
 
-#if 0
-    // Ethernet LEDs
-    gpio_function(GPIO_ETH_LED0, pad_gpio4); /* ETH LED0 */
-    gpio_dir(GPIO_ETH_LED0, pad_dir_open_drain);
-    gpio_function(GPIO_ETH_LED1, pad_gpio5); /* ETH LED1 */
-    gpio_dir(GPIO_ETH_LED1, pad_dir_output);
+#ifdef GPIO_LED
+    gpio_function(GPIO_LED, pad_func_0); /* CN2 connector pin 4  */
+    gpio_idrive(GPIO_LED, pad_drive_12mA);
+    gpio_dir(GPIO_LED, pad_dir_output);
 #endif
 
 	sys_enable(sys_device_timer_wdt);
@@ -153,14 +151,14 @@ void board_pm_ISR(void)
     )
     {
 #if CFG_TUD_ENABLED
-        ft90x_usbd_pm_ISR(pmcfg);
+        ft9xx_usbd_pm_ISR(pmcfg);
 #endif
     }
 #endif
 }
 
 #if CFG_TUD_ENABLED
-int8_t board_ft90x_vbus(void)
+int8_t board_ft9xx_vbus(void)
 {
 	return gpio_read(USBD_VBUS_DTC_PIN);
 }
@@ -173,7 +171,11 @@ int8_t board_ft90x_vbus(void)
 // Turn LED on or off
 void board_led_write(bool state)
 {
+#if 0
     gpio_write(GPIO_ETH_LED0, state);
+#else
+    gpio_write(GPIO_LED, state);
+#endif
 }
 
 // Get the current state of button
diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index a476cfc06..f45e27cb5 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -3,8 +3,8 @@ CROSS_COMPILE = ft32-elf-
 SKIP_NANOLIB = 1
 
 # Set to use FT90X prebuilt libraries.
-FT90X_PREBUILT_LIBS = 0
-ifeq ($(FT90X_PREBUILT_LIBS),1)
+FT9XX_PREBUILT_LIBS = 0
+ifeq ($(FT9XX_PREBUILT_LIBS),1)
 # If the FT90X toolchain is installed on Windows systems then the SDK 
 # include files and prebuilt libraries are at: %FT90X_TOOLCHAIN%/hardware
 FT9XX_SDK = $(FT90X_TOOLCHAIN)/hardware
@@ -48,7 +48,7 @@ LDFLAGS += $(addprefix -L,$(LDINC)) \
 SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c 
 
 # Linker library.
-ifneq ($(FT90X_PREBUILT_LIBS),1)
+ifneq ($(FT9XX_PREBUILT_LIBS),1)
 # Optionally add in files from the Bridgetek SDK instead of the prebuilt
 # library. These are the minimum required.
 SRC_C += $(FT9XX_SDK)/src/sys.c
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 080d633fa..50f7018db 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -47,20 +47,17 @@
 //--------------------------------------------------------------------+
 
 // Board code will determine the state of VBUS from USB host.
-extern int8_t board_ft90x_vbus(void);
+extern int8_t board_ft9xx_vbus(void);
 
 // Static array to store an incoming SETUP request for processing by tinyusb.
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
-static uint8_t _ft90x_setup_packet[8];
+static uint8_t _ft9xx_setup_packet[8];
 
-// Static array to store one SETUP DATA packet until required by dcd_edpt_xfer.
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
-static uint8_t _ft90x_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
-static uint8_t _ft90x_ctrl_buf_complete;
-
-struct ft90x_xfer_state
+struct ft9xx_xfer_state
 {
+  volatile uint8_t ready; // OUT Transfer has been received and waiting for transfer.
   volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
+  
   int16_t total_size; // Total transfer size in bytes for this transfer.
   int16_t remain_size; // Total remaining in transfer.
   uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
@@ -71,24 +68,24 @@ struct ft90x_xfer_state
   uint16_t size; // Max packet size for endpoint from endpoint descriptor.
 };
 // Endpoint description array for each endpoint.
-static struct ft90x_xfer_state ep_xfer[USBD_MAX_ENDPOINT_COUNT];
+static struct ft9xx_xfer_state ep_xfer[USBD_MAX_ENDPOINT_COUNT];
 // USB speed.
 static tusb_speed_t _speed;
 
 // Interrupt handlers.
-void _ft90x_usbd_ISR(void); // Interrupt handler for USB device.
-void ft90x_usbd_pm_ISR(void); // Interrupt handler for USB device for power management (called by board).
+void _ft9xx_usbd_ISR(void); // Interrupt handler for USB device.
+void ft9xx_usbd_pm_ISR(void); // Interrupt handler for USB device for power management (called by board).
 
 // Internal functions forward declarations.
-static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes);
-static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes);
-static void _ft90x_reset_edpts(void);
-static inline void _ft90x_phy_enable(bool en);
-static void _ft90x_usb_speed(void);
-static void _dcd_ft90x_attach(void);
-static void _dcd_ft90x_detach(void) __attribute__((unused));
-static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length);
-static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length);
+static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes);
+static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes);
+static void _ft9xx_reset_edpts(void);
+static inline void _ft9xx_phy_enable(bool en);
+static void _ft9xx_usb_speed(void);
+static void _dcd_ft9xx_attach(void);
+static void _dcd_ft9xx_detach(void) __attribute__((unused));
+static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length);
+static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length);
 
 // Internal functions.
 
@@ -96,7 +93,7 @@ static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len
 // This can be up-to the maximum packet size of the endpoint.
 // Continuation of a transfer beyond the maximum packet size is performed 
 // by the interrupt handler.
-static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
+static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
 {
   //Note: this is called from only the interrupt handler when an OUT transfer is called.
   uint16_t ep_size = ep_xfer[ep_number].size;
@@ -111,7 +108,7 @@ static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_
     //;
 
   // Send the first packet of max packet size
-  xfer_bytes = _ft90x_dusb_out(ep_number, (uint8_t *)buffer, xfer_bytes);
+  xfer_bytes = _ft9xx_dusb_out(ep_number, (uint8_t *)buffer, xfer_bytes);
   if (ep_number == USBD_EP_0)
   {
     // Set flags to indicate data ready.
@@ -129,7 +126,7 @@ static uint16_t _ft90x_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_
 // This can be up-to the maximum packet size of the endpoint.
 // Continuation of a transfer beyond the maximum packet size is performed 
 // by the interrupt handler.
-static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
+static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
 {
   //Note: this may be called from the interrupt handler or from normal code.
   uint8_t end = 0;
@@ -167,7 +164,7 @@ static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
     
   }
 
-  xfer_bytes = _ft90x_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes);
+  xfer_bytes = _ft9xx_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes);
 
   if (ep_number == USBD_EP_0)
   {
@@ -193,13 +190,13 @@ static uint16_t _ft90x_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
 
 // Reset all non-control endpoints to a default state. 
 // Control endpoint is always enabled and ready. All others disabled.
-static void _ft90x_reset_edpts(void)
+static void _ft9xx_reset_edpts(void)
 {
   // Disable all endpoints and remove configuration values.
   for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++)
   {
     // Clear settings.
-    tu_memclr(&ep_xfer[i], sizeof(struct ft90x_xfer_state));
+    tu_memclr(&ep_xfer[i], sizeof(struct ft9xx_xfer_state));
     // Disable hardware.
     USBD_EP_CR_REG(i) = 0;
   }
@@ -209,7 +206,7 @@ static void _ft90x_reset_edpts(void)
 }
 
 // Enable or disable the USB PHY.
-static inline void _ft90x_phy_enable(bool en)
+static inline void _ft9xx_phy_enable(bool en)
 {
   if (en)
     SYS->PMCFG_L |= MASK_SYS_PMCFG_DEV_PHY_EN;
@@ -218,7 +215,7 @@ static inline void _ft90x_phy_enable(bool en)
 }
 
 // Safely connect to the USB.
-static void _dcd_ft90x_attach(void)
+static void _dcd_ft9xx_attach(void)
 {
   uint8_t reg;
 
@@ -274,7 +271,7 @@ static void _dcd_ft90x_attach(void)
 }
 
 // Gracefully disconnect from the USB.
-static void _dcd_ft90x_detach(void)
+static void _dcd_ft9xx_detach(void)
 {
   // Disable device connect/disconnect/host reset detection.
   SYS->PMCFG_L = SYS->PMCFG_L & (~MASK_SYS_PMCFG_DEV_DETECT_EN);
@@ -316,7 +313,7 @@ static void _dcd_ft90x_detach(void)
 // Determine the speed of the USB to which we are connected.
 // Set the speed of the PHY accordingly. 
 // High speed can be disabled through CFG_TUSB_RHPORT0_MODE or CFG_TUD_MAX_SPEED settings.
-static void _ft90x_usb_speed(void)
+static void _ft9xx_usb_speed(void)
 {
 	uint8_t  fctrl_val;
 
@@ -379,7 +376,7 @@ static void _ft90x_usb_speed(void)
 // If streaming is disabled then it will send each byte of the buffer in turn 
 // to the FIFO. The is no reason to not stream.
 // The total number of bytes sent to the FIFO is returned.
-static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length)
+static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length)
 {
   uint16_t bytes_read = 0;
   uint16_t buff_size = length;
@@ -436,7 +433,7 @@ static uint16_t _ft90x_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_
 // If streaming is disabled then it will receive each byte from the FIFO in turn 
 // to the buffer. The is no reason to not stream.
 // The total number of bytes received from the FIFO is returned.
-static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length)
+static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length)
 {
 #ifdef USBD_USE_STREAMS
   volatile uint8_t *data_reg;
@@ -514,11 +511,11 @@ static uint16_t _ft90x_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len
 // Initialize controller to device mode
 void dcd_init(uint8_t rhport)
 {
-  TU_LOG2("FT90x initialisation\r\n");
+  TU_LOG2("FT9xx initialisation\r\n");
 
-  _dcd_ft90x_attach();
+  _dcd_ft9xx_attach();
 
-  interrupt_attach(interrupt_usb_device, (int8_t)interrupt_usb_device, _ft90x_usbd_ISR);
+  interrupt_attach(interrupt_usb_device, (int8_t)interrupt_usb_device, _ft9xx_usbd_ISR);
 
   dcd_connect(rhport);
 }
@@ -527,7 +524,7 @@ void dcd_init(uint8_t rhport)
 void dcd_int_enable(uint8_t rhport)
 {
   (void)rhport;
-  TU_LOG3("FT90x int enable\r\n");
+  TU_LOG3("FT9xx int enable\r\n");
 
   // Peripheral devices interrupt enable.
   interrupt_enable_globally();
@@ -537,7 +534,7 @@ void dcd_int_enable(uint8_t rhport)
 void dcd_int_disable(uint8_t rhport)
 {
   (void)rhport;
-  TU_LOG3("FT90x int disable\r\n");
+  TU_LOG3("FT9xx int disable\r\n");
 
   // Peripheral devices interrupt disable.
   interrupt_disable_globally();
@@ -603,18 +600,18 @@ void dcd_remote_wakeup(uint8_t rhport)
 void dcd_connect(uint8_t rhport)
 {
   (void)rhport;
-  TU_LOG2("FT90x connect\r\n");
+  TU_LOG2("FT9xx connect\r\n");
 
   CRITICAL_SECTION_BEGIN
   // Is device connected?
-  if (board_ft90x_vbus())
+  if (board_ft9xx_vbus())
   {
     // Clear/disable address register.
     USBD_REG(faddr) = 0;
-    _ft90x_phy_enable(true);
+    _ft9xx_phy_enable(true);
 
     // Determine bus speed and signal speed to tusb.
-    _ft90x_usb_speed();
+    _ft9xx_usb_speed();
   }
   
   // Setup the control endpoint only.
@@ -639,17 +636,17 @@ void dcd_connect(uint8_t rhport)
   USBD_REG(epie) = (MASK_USBD_EPIE_EP0IE);
 
   // Restore default endpoint state.
-  _ft90x_reset_edpts();
+  _ft9xx_reset_edpts();
 }
 
 // Disconnect by disabling internal pull-up resistor on D+/D-
 void dcd_disconnect(uint8_t rhport)
 {
   (void)rhport;
-  TU_LOG2("FT90x disconnect\r\n");
+  TU_LOG2("FT9xx disconnect\r\n");
 
   // Disable the USB PHY.
-  _ft90x_phy_enable(false);
+  _ft9xx_phy_enable(false);
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -677,12 +674,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
   uint8_t ep_reg_data = 0;
   int16_t total_ram;
 
-  TU_LOG2("FT90x endpoint open %d %c\r\n", ep_number, ep_dir?'I':'O');
+  TU_LOG2("FT9xx endpoint open %d %c\r\n", ep_number, ep_dir?'I':'O');
 
   // Check that the requested endpoint number is allowable.
   if (ep_number >= USBD_MAX_ENDPOINT_COUNT)
   {
-    TU_LOG1("FT90x endpoint not valid: requested %d max %d\r\n", ep_number, USBD_MAX_ENDPOINT_COUNT);
+    TU_LOG1("FT9xx endpoint not valid: requested %d max %d\r\n", ep_number, USBD_MAX_ENDPOINT_COUNT);
     return false;
   }
 
@@ -694,7 +691,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
   }
   if (ep_reg_size > USBD_EP_MAX_SIZE_1024)
   {
-    TU_LOG1("FT90x endpoint size not valid: requested %d max 1024\r\n", ep_size);
+    TU_LOG1("FT9xx endpoint size not valid: requested %d max 1024\r\n", ep_size);
     return false;
   }
   // Calculate actual amount of buffer RAM used by this endpoint. This may be more than the 
@@ -709,9 +706,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     if (ep_xfer[ep_number].type != USBD_EP_TYPE_DISABLED)
     {
       // This could be because an endpoint has been assigned with the same number.
-      // On FT90x, IN and OUT endpoints may not have the same number. e.g. There 
+      // On FT9xx, IN and OUT endpoints may not have the same number. e.g. There 
       // cannot been an 0x81 and 0x01 endpoint.
-      TU_LOG1("FT90x endpoint %d already assigned\r\n", ep_number);
+      TU_LOG1("FT9xx endpoint %d already assigned\r\n", ep_number);
       return false;
     }
 
@@ -723,7 +720,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     else
       total_ram = USBD_RAMTOTAL_OUT;
     // Work out how much has been allocated to existing endpoints.
-    // The total RAM allocated shoudl alsyes be a positive number as this
+    // The total RAM allocated should always be a positive number as this
     // algorithm should not let it go below zero.
     for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++)
     {
@@ -735,14 +732,19 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
         }
       }
     }
-    // The control endpoint is taken into account as well.
-    total_ram -= ep_xfer[0].buff_size;
+
+    if (sys_check_ft900_revB())
+    {
+      // The control endpoint is taken into account as well on RevB silicon.
+      total_ram -= ep_xfer[0].buff_size;
+    }
+
     // Make sure we have enough space. The corner case is having zero bytes
     // free which means that total_ram must be signed as zero bytes free is
     // allowable.
     if (total_ram < ep_buff_size)
     {
-      TU_LOG1("FT90x insufficient buffer RAM for endpoint %d\r\n", ep_number);
+      TU_LOG1("FT9xx insufficient buffer RAM for endpoint %d\r\n", ep_number);
       return false;    
     }
 
@@ -761,7 +763,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     //ep_reg_data |= MASK_USBD_EPxCR_DB;
     // Set the control endpoint for this endpoint.
     USBD_EP_CR_REG(ep_number) = ep_reg_data;
-    TU_LOG2("FT90x endpoint setting %x\r\n", ep_reg_data);
+    TU_LOG2("FT9xx endpoint setting %x\r\n", ep_reg_data);
   }
   else
   {
@@ -777,6 +779,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
   ep_xfer[ep_number].buff_size = ep_buff_size;
 
   // Clear register transaction continuation and signalling state.
+  ep_xfer[ep_number].ready = 0;
   ep_xfer[ep_number].valid = 0;
   ep_xfer[ep_number].buff_ptr = NULL;
   ep_xfer[ep_number].total_size = 0;
@@ -791,7 +794,7 @@ void dcd_edpt_close_all(uint8_t rhport)
 {
   (void)rhport;
   // Reset the endpoint configurations.
-  _ft90x_reset_edpts();
+  _ft9xx_reset_edpts();
 }
 
 // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
@@ -799,7 +802,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
 {
   (void)rhport;
   uint8_t ep_number = tu_edpt_number(ep_addr);
-  uint8_t dir = tu_edpt_dir(ep_addr);
+  uint8_t ep_dir = tu_edpt_dir(ep_addr);
   uint16_t xfer_bytes;
   bool status = false;
 
@@ -809,6 +812,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
   // ep_xfer is used to tell the interrupt handler what to do.
   // ep_xfer can be used at interrupt level to continue transfers.
   CRITICAL_SECTION_BEGIN
+
   // Transfer currently in progress.
   if (ep_xfer[ep_number].valid == 0)
   {
@@ -818,7 +822,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
     
     if (ep_number == USBD_EP_0)
     {
-      ep_xfer[USBD_EP_0].dir = dir;
+      ep_xfer[USBD_EP_0].dir = ep_dir;
     }
     else
     {
@@ -827,11 +831,11 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
       USBD_REG(epie) = USBD_REG(epie) | (1 << ep_number);
     }
 
-    if (dir == TUSB_DIR_IN)
+    if (ep_dir == TUSB_DIR_IN)
     {
       // For IN transfers send the first packet as a starter. Interrupt handler to complete
       // this if it is larger than one packet.
-      xfer_bytes = _ft90x_edpt_xfer_in(ep_number, buffer, total_bytes);
+      xfer_bytes = _ft9xx_edpt_xfer_in(ep_number, buffer, total_bytes);
 
       ep_xfer[ep_number].buff_ptr += xfer_bytes;
       ep_xfer[ep_number].remain_size -= xfer_bytes;
@@ -839,26 +843,37 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
       // Tell the interrupt handler to signal dcd_event_xfer_complete on completion.
       ep_xfer[ep_number].valid = 1;
     }
-    else
+    else // (dir == TUSB_DIR_OUT)
     {
       // For OUT transfers on the control endpoint.
       // The host may already have performed the first data transfer after the SETUP packet
       // before the transfer is setup for it.
-      if ((ep_number == USBD_EP_0) && (_ft90x_ctrl_buf_complete))
+      if (ep_xfer[ep_number].ready)
       {
-        // Pull the received data packet from the packet cache and complete the transfer
-        // immediately.
-        memcpy(buffer, _ft90x_ctrl_buf, _ft90x_ctrl_buf_complete);
-        dcd_event_xfer_complete(BOARD_TUD_RHPORT, TUSB_DIR_OUT, _ft90x_ctrl_buf_complete, XFER_RESULT_SUCCESS, false);
+        // We have received a data packet on the endpoint without a transfer
+        // being initialised. This can be because the host has sent this packet before
+        // a new transfer has been initiated on the endpoint.
+        // We will now stream the data from the FIFO.
+        ep_xfer[ep_number].ready = 0;
+
+        // Transfer incoming data from an OUT packet to the buffer.
+        xfer_bytes = _ft9xx_edpt_xfer_out(ep_number, buffer, total_bytes);
+        // Report completion of the transfer.
+        dcd_event_xfer_complete(BOARD_TUD_RHPORT, ep_number /*| TUSB_DIR_OUT_MASK */, xfer_bytes, XFER_RESULT_SUCCESS, false);
       }
       else
       {
-        // Tell the interrupt handler to wait for the packet to be received.
+        // Tell the interrupt handler to wait for the packet to be received and
+        // then report the transfer complete with dcd_event_xfer_complete.
         ep_xfer[ep_number].valid = 1;
       }
     } 
     status = true;
   }
+  else
+  {
+    // Note: should not arrive here.
+  }
 
   CRITICAL_SECTION_END
 
@@ -912,6 +927,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
     USBD_EP_SR_REG(ep_number) = MASK_USBD_EPxSR_CLR_TOGGLE;
 
     // Allow transfers to restart.
+    ep_xfer[ep_number].ready = 0;
     ep_xfer[ep_number].valid = 0;
     ep_xfer[ep_number].remain_size = 0;
     CRITICAL_SECTION_END
@@ -920,7 +936,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
 // Interrupt handling.
 
-void _ft90x_usbd_ISR(void)
+void _ft9xx_usbd_ISR(void)
 {
   dcd_int_handler(BOARD_TUD_RHPORT);
 }
@@ -959,7 +975,7 @@ void dcd_int_handler(uint8_t rhport)
     if (cmif & MASK_USBD_CMIF_RSTIRQ) //Handle Reset interrupt
     {
       // Reset endpoints to default state.
-      _ft90x_reset_edpts();
+      _ft9xx_reset_edpts();
       dcd_event_bus_reset(BOARD_TUD_RHPORT, _speed, true);
     }
     if (cmif & MASK_USBD_CMIF_SUSIRQ) //Handle Suspend interrupt
@@ -999,18 +1015,18 @@ void dcd_int_handler(uint8_t rhport)
         }
 
         // Host has sent a SETUP packet. Recieve this into the SETUP packet store.
-        _ft90x_dusb_out(USBD_EP_0, (uint8_t *)_ft90x_setup_packet, sizeof(USB_device_request));
+        _ft9xx_dusb_out(USBD_EP_0, (uint8_t *)_ft9xx_setup_packet, sizeof(USB_device_request));
         
         // Send the packet to tinyusb.
-        dcd_event_setup_received(BOARD_TUD_RHPORT, _ft90x_setup_packet, true);
+        dcd_event_setup_received(BOARD_TUD_RHPORT, _ft9xx_setup_packet, true);
 
         // Clear the interrupt that signals a SETUP packet is received.
         USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_SETUP);
 
-        // Invalidate cache packet.
-        _ft90x_ctrl_buf_complete = 0;
+        // Any SETUP packet will clear the incoming FIFO.
+        ep_xfer[USBD_EP_0].ready = 0;
 
-        // Allow new transfers on the control endpoint.
+        // Allow new DATA and ACK transfers on the control endpoint.
         ep_xfer[USBD_EP_0].valid = 0;
         return;
       }
@@ -1024,35 +1040,28 @@ void dcd_int_handler(uint8_t rhport)
           // Transfer incoming data from an OUT packet to the buffer supplied.        
           if (ep_xfer[USBD_EP_0].dir == TUSB_DIR_OUT)
           {
-            xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
+            xfer_bytes = _ft9xx_edpt_xfer_out(USBD_EP_0, ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
           }
           // Now signal completion of data packet.
-          dcd_event_xfer_complete(BOARD_TUD_RHPORT, (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), xfer_bytes, XFER_RESULT_SUCCESS, true);
+          dcd_event_xfer_complete(BOARD_TUD_RHPORT, USBD_EP_0 | (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), 
+            xfer_bytes, XFER_RESULT_SUCCESS, true);
 
-          // Invalidate cache packet.
-          _ft90x_ctrl_buf_complete = 0;
+          // Incoming FIFO has been cleared.
+          ep_xfer[USBD_EP_0].ready = 0;
 
           // Allow new transfers on the control endpoint.
           ep_xfer[USBD_EP_0].valid = 0;
         }
+        // No transfer is in flight for EP0.
         else
         {
           // We have received a data packet on the control endpoint without a transfer
           // being initialised. This can be because the host has sent this packet before
           // a new transfer has been initiated on the control endpoint.
-          // We will cache upto the maximum packet size for the control endpoint and
-          // use it later in dcd_edpt_xfer.
-          xfer_bytes = CFG_TUD_ENDPOINT0_SIZE;
-
-          // Transfer incoming data from an OUT packet to the cache packet.
-          xfer_bytes = _ft90x_edpt_xfer_out(USBD_EP_0, _ft90x_ctrl_buf, xfer_bytes);
-          
-          // Set the size of the cache packet.
-          _ft90x_ctrl_buf_complete = xfer_bytes;
+          // We will record that there is data in the FIFO for dcd_edpt_xfer to obtain
+          // once the transfer is initiated.
+          ep_xfer[USBD_EP_0].ready = 1;
         }
-
-        // Clear the interrupt that signals a SETUP DATA packet is received.
-        USBD_EP_SR_REG(USBD_EP_0) = (MASK_USBD_EP0SR_OPRDY);
       }
     }
     else // !(epif & MASK_USBD_EPIF_EP0IRQ)
@@ -1072,7 +1081,6 @@ void dcd_int_handler(uint8_t rhport)
         if (ep_xfer[ep_number].valid)
         {
           xfer_bytes = 0;
-          uint8_t ep_dirmask = (ep_xfer[ep_number].dir ? TUSB_DIR_IN_MASK : 0);
 
           // Clear interrupt register for this endpoint.
           USBD_REG(epif) = MASK_USBD_EPIF_IRQ(ep_number);
@@ -1080,10 +1088,15 @@ void dcd_int_handler(uint8_t rhport)
           // Start or continue an OUT transfer.
           if (ep_xfer[ep_number].dir == TUSB_DIR_OUT)
           {
-            xfer_bytes = _ft90x_edpt_xfer_out(ep_number, 
+            xfer_bytes = _ft9xx_edpt_xfer_out(ep_number, 
                             ep_xfer[ep_number].buff_ptr, 
                             (uint16_t)ep_xfer[ep_number].remain_size);
 
+            // Report each OUT packet received to the stack.
+            dcd_event_xfer_complete(BOARD_TUD_RHPORT, 
+                                      ep_number /* | TUSB_DIR_OUT_MASK */, 
+                                      xfer_bytes, XFER_RESULT_SUCCESS, true);
+
             ep_xfer[ep_number].buff_ptr += xfer_bytes;
             ep_xfer[ep_number].remain_size -= xfer_bytes;
           }
@@ -1092,27 +1105,45 @@ void dcd_int_handler(uint8_t rhport)
           {
             if (ep_xfer[ep_number].remain_size > 0)
             {
-              xfer_bytes = _ft90x_edpt_xfer_in(ep_number, 
+              xfer_bytes = _ft9xx_edpt_xfer_in(ep_number, 
                             ep_xfer[ep_number].buff_ptr, 
                             (uint16_t)ep_xfer[ep_number].remain_size);
 
               ep_xfer[ep_number].buff_ptr += xfer_bytes;
               ep_xfer[ep_number].remain_size -= xfer_bytes;
             }
+
+            if (ep_xfer[ep_number].remain_size == 0)
+            {
+              dcd_event_xfer_complete(BOARD_TUD_RHPORT, 
+                                      ep_number | TUSB_DIR_IN_MASK, 
+                                      ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
+            }
           }
 
           // When the transfer is complete...
           if (ep_xfer[ep_number].remain_size == 0)
           {
-            // Signal tinyUSB.
-            dcd_event_xfer_complete(BOARD_TUD_RHPORT, ep_number | ep_dirmask, ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
-
-            // Allow new transfers on this endpoint.
+            // Finish this transfer and allow new transfers on this endpoint.
             ep_xfer[ep_number].valid = 0;
 
             // Disable the interrupt for this endpoint now it is complete.
             USBD_REG(epie) = USBD_REG(epie) & (~(1 << ep_number));
           }
+
+          ep_xfer[ep_number].ready = 0;
+        }
+        // No OUT transfer is in flight for this endpoint.
+        else
+        {
+          if (ep_xfer[ep_number].dir == TUSB_DIR_OUT)
+          {
+            // We will record that there is data in the FIFO for dcd_edpt_xfer to obtain
+            // once the transfer is initiated.
+            // Strictly this should not happen for a non-control endpoint. Interrupts
+            // are disabled when there are no transfers setup for an endpoint.
+            ep_xfer[ep_number].ready = 1;          
+          }
         }
       }
     }
@@ -1121,7 +1152,7 @@ void dcd_int_handler(uint8_t rhport)
 
 // Power management interrupt handler. 
 // This handles USB device related power management interrupts only.
-void ft90x_usbd_pm_ISR(void)
+void ft9xx_usbd_pm_ISR(void)
 {
     uint16_t pmcfg = SYS->PMCFG_H;
 

From d588167a39fd01e5cea718deb1917e74c6a801ab Mon Sep 17 00:00:00 2001
From: pete-pjb <petebone00@gmail.com>
Date: Wed, 30 Nov 2022 11:33:24 +0000
Subject: [PATCH 1248/2085] Modify FreeRTOS integration to allow non-static
 allocation.

---
 src/osal/osal_freertos.h | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 52db336f5..a2b0573f8 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -62,12 +62,20 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 //--------------------------------------------------------------------+
 // Semaphore API
 //--------------------------------------------------------------------+
+#if configSUPPORT_STATIC_ALLOCATION	== 1
 typedef StaticSemaphore_t osal_semaphore_def_t;
+#else
+typedef SemaphoreHandle_t osal_semaphore_def_t;
+#endif
 typedef SemaphoreHandle_t osal_semaphore_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
 {
+#if configSUPPORT_STATIC_ALLOCATION	== 1
   return xSemaphoreCreateBinaryStatic(semdef);
+#else
+  return xSemaphoreCreateBinary();
+#endif
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
@@ -105,12 +113,21 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c
 //--------------------------------------------------------------------+
 // MUTEX API (priority inheritance)
 //--------------------------------------------------------------------+
+#if configSUPPORT_STATIC_ALLOCATION	== 1
 typedef StaticSemaphore_t osal_mutex_def_t;
+#else
+typedef SemaphoreHandle_t osal_mutex_def_t;
+#endif
 typedef SemaphoreHandle_t osal_mutex_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
+#if configSUPPORT_STATIC_ALLOCATION	== 1
   return xSemaphoreCreateMutexStatic(mdef);
+#else
+  return xSemaphoreCreateMutex();
+#endif
+
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
@@ -145,7 +162,11 @@ typedef QueueHandle_t osal_queue_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
-  return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
+#if configSUPPORT_STATIC_ALLOCATION	== 1
+	return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
+#else
+  return xQueueCreate(qdef->depth, qdef->item_sz);
+#endif
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)

From fe63e30a4408dacc714ad9fcf39cf6fcf7c7d865 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 30 Nov 2022 11:46:13 +0000
Subject: [PATCH 1249/2085] Add FT9xx for cdc_dual_ports

Fix handling of interrupt endpoints. i.e. no ZLPs.
Fix the assignation of endpoint types.
Add button support for MM900evx boards.
On board support do not block for UART input.
---
 .../cdc_dual_ports/src/usb_descriptors.c      | 11 ++++---
 hw/bsp/brtmm90x/boards/mm900evxb/board.h      |  2 ++
 hw/bsp/brtmm90x/family.c                      | 31 +++++++++++++++----
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c      | 29 +++++++++++------
 4 files changed, 52 insertions(+), 21 deletions(-)

diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index 5a8dea553..4eb8c7c27 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -111,12 +111,13 @@ enum
 #elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
   // FT9XX doesn't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
-  #define EPNUM_CDC_NOTIF     0x81
-  #define EPNUM_CDC_OUT       0x02
-  #define EPNUM_CDC_IN        0x83
+  #define EPNUM_CDC_0_NOTIF   0x81
+  #define EPNUM_CDC_0_OUT     0x02
+  #define EPNUM_CDC_0_IN      0x83
 
-  #define EPNUM_MSC_OUT       0x04
-  #define EPNUM_MSC_IN        0x85
+  #define EPNUM_CDC_1_NOTIF   0x84
+  #define EPNUM_CDC_1_OUT     0x05
+  #define EPNUM_CDC_1_IN      0x86
 
 #else
   #define EPNUM_CDC_0_NOTIF   0x81
diff --git a/hw/bsp/brtmm90x/boards/mm900evxb/board.h b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
index 930cb9d33..76813b116 100644
--- a/hw/bsp/brtmm90x/boards/mm900evxb/board.h
+++ b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
@@ -41,6 +41,8 @@
 
 // LED is connected to pins 4 (signal) and 2 (GND) of CN2.
 #define GPIO_LED 36
+// Button is connected to pins 6 (signal) and 2 (GND) of CN2.
+#define GPIO_BUTTON 37
 
 // Remote wakeup is wired to pin 40 of CN1.
 #define GPIO_REMOTE_WAKEUP_PIN 18
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index cc28cb69b..8155c0afc 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -49,11 +49,16 @@ void board_pm_ISR(void);
 void board_init(void)
 {
 	sys_reset_all();
+
     // Enable the UART Device.
     sys_enable(sys_device_uart0);
     // Set UART0 GPIO functions to UART0_TXD and UART0_RXD.
+#ifdef GPIO_UART0_TX
     gpio_function(GPIO_UART0_TX, pad_uart0_txd); /* UART0 TXD */
+#endif
+#ifdef GPIO_UART0_RX
     gpio_function(GPIO_UART0_RX, pad_uart0_rxd); /* UART0 RXD */
+#endif
     uart_open(UART0,                             /* Device */
               1,                                 /* Prescaler = 1 */
               UART_DIVIDER_19200_BAUD,           /* Divider = 1302 */
@@ -65,11 +70,17 @@ void board_init(void)
     board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG));
 
 #ifdef GPIO_LED
-    gpio_function(GPIO_LED, pad_func_0); /* CN2 connector pin 4  */
+    gpio_function(GPIO_LED, pad_func_0); 
     gpio_idrive(GPIO_LED, pad_drive_12mA);
     gpio_dir(GPIO_LED, pad_dir_output);
 #endif
 
+#ifdef GPIO_BUTTON
+    gpio_function(GPIO_BUTTON, pad_func_0);
+    gpio_pull(GPIO_BUTTON, pad_pull_pullup);
+    gpio_dir(GPIO_BUTTON, pad_dir_input);
+#endif
+
 	sys_enable(sys_device_timer_wdt);
 	/* Timer A = 1ms */
 	timer_prescaler(timer_select_a, 1000);
@@ -171,9 +182,7 @@ int8_t board_ft9xx_vbus(void)
 // Turn LED on or off
 void board_led_write(bool state)
 {
-#if 0
-    gpio_write(GPIO_ETH_LED0, state);
-#else
+#ifdef GPIO_LED
     gpio_write(GPIO_LED, state);
 #endif
 }
@@ -182,13 +191,23 @@ void board_led_write(bool state)
 // a '1' means active (pressed), a '0' means inactive.
 uint32_t board_button_read(void)
 {
-    return 0;
+    uint32_t state = 0;
+#ifdef GPIO_BUTTON
+    state = gpio_read(GPIO_BUTTON);
+    state = !state;
+#endif
+    return state;
 }
 
 // Get characters from UART
 int board_uart_read(uint8_t *buf, int len)
 {
-    int r = uart_readn(UART0, (uint8_t *)buf, len);
+    int r = 0;
+
+    if (uart_rx_has_data(UART0))
+    {
+        r = uart_readn(UART0, (uint8_t *)buf, len);
+    }
 
     return r;
 }
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 50f7018db..fabe7910b 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -48,6 +48,7 @@
 
 // Board code will determine the state of VBUS from USB host.
 extern int8_t board_ft9xx_vbus(void);
+extern int board_uart_write(void const *buf, int len);
 
 // Static array to store an incoming SETUP request for processing by tinyusb.
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
@@ -154,17 +155,24 @@ static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
   }
   else
   {
-    uint8_t sr_reg;
     // If there is data to transmit then wait until the IN buffer
     // for the endpoint is empty.
-    do
+    // This does not apply to interrupt endpoints.
+    if (ep_xfer[ep_number].type != TUSB_XFER_INTERRUPT)
     {
-      sr_reg = USBD_EP_SR_REG(ep_number);
-    } while (sr_reg & MASK_USBD_EPxSR_INPRDY);
-    
+      uint8_t sr_reg;
+      do
+      {
+        sr_reg = USBD_EP_SR_REG(ep_number);
+      } while (sr_reg & MASK_USBD_EPxSR_INPRDY);
+    }
   }
 
-  xfer_bytes = _ft9xx_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes);
+  // Do not send a ZLP for interrupt endpoints.
+  if ((ep_xfer[ep_number].type != TUSB_XFER_INTERRUPT) || (xfer_bytes > 0))
+  {
+    xfer_bytes = _ft9xx_dusb_in(ep_number, (uint8_t *)buffer, xfer_bytes);
+  }
 
   if (ep_number == USBD_EP_0)
   {
@@ -749,11 +757,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     }
 
     // Set the type of this endpoint in the control register.
-    if (ep_type == USBD_EP_BULK)
+    if (ep_type == TUSB_XFER_BULK)
       ep_reg_data |= (USBD_EP_DIS_BULK << BIT_USBD_EP_CONTROL_DIS);
-    else if (ep_type == USBD_EP_INT)
+    else if (ep_type == TUSB_XFER_INTERRUPT)
       ep_reg_data |= (USBD_EP_DIS_INT << BIT_USBD_EP_CONTROL_DIS);
-    else if (ep_type == USBD_EP_ISOC)
+    else if (ep_type == TUSB_XFER_ISOCHRONOUS)
       ep_reg_data |= (USBD_EP_DIS_ISO << BIT_USBD_EP_CONTROL_DIS);
     // Set the direction of this endpoint in the control register.
     if (ep_dir == USBD_DIR_IN)
@@ -761,7 +769,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     // Do not perform double buffering.
     //if (<double buffering flag> != USBD_DB_OFF)
     //ep_reg_data |= MASK_USBD_EPxCR_DB;
-    // Set the control endpoint for this endpoint.
+    // Set the control register for this endpoint.
     USBD_EP_CR_REG(ep_number) = ep_reg_data;
     TU_LOG2("FT9xx endpoint setting %x\r\n", ep_reg_data);
   }
@@ -858,6 +866,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
 
         // Transfer incoming data from an OUT packet to the buffer.
         xfer_bytes = _ft9xx_edpt_xfer_out(ep_number, buffer, total_bytes);
+
         // Report completion of the transfer.
         dcd_event_xfer_complete(BOARD_TUD_RHPORT, ep_number /*| TUSB_DIR_OUT_MASK */, xfer_bytes, XFER_RESULT_SUCCESS, false);
       }

From 069215c538cc1b615f18a6af055026267d56581c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 30 Nov 2022 18:36:01 +0700
Subject: [PATCH 1250/2085] white spaces

---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 583 ++++++++++---------
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  54 +-
 2 files changed, 328 insertions(+), 309 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 10237d1f9..9e6bdad44 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -81,89 +81,90 @@ static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
 
 TU_ATTR_ALWAYS_INLINE static inline uint8_t dev_speed(void)
 {
-    return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
+  return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
 }
 
-static bool need_pre(uint8_t dev_addr)
+TU_ATTR_ALWAYS_INLINE static inline bool need_pre(uint8_t dev_addr)
 {
-    // If this device is different to the speed of the root device
-    // (i.e. is a low speed device on a full speed hub) then need pre
-    return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
+  // If this device is different to the speed of the root device
+  // (i.e. is a low speed device on a full speed hub) then need pre
+  return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
 }
 
 static void __tusb_irq_path_func(hw_xfer_complete)(struct hw_endpoint *ep, xfer_result_t xfer_result)
 {
-    // Mark transfer as done before we tell the tinyusb stack
-    uint8_t dev_addr = ep->dev_addr;
-    uint8_t ep_addr = ep->ep_addr;
-    uint xferred_len = ep->xferred_len;
-    hw_endpoint_reset_transfer(ep);
-    hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
+  // Mark transfer as done before we tell the tinyusb stack
+  uint8_t dev_addr = ep->dev_addr;
+  uint8_t ep_addr = ep->ep_addr;
+  uint xferred_len = ep->xferred_len;
+  hw_endpoint_reset_transfer(ep);
+  hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
 }
 
 static void __tusb_irq_path_func(_handle_buff_status_bit)(uint bit, struct hw_endpoint *ep)
 {
-    usb_hw_clear->buf_status = bit;
-    // EP may have been stalled?
-    assert(ep->active);
-    bool done = hw_endpoint_xfer_continue(ep);
-    if (done)
-    {
-        hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
-    }
+  usb_hw_clear->buf_status = bit;
+  // EP may have been stalled?
+  assert(ep->active);
+  bool done = hw_endpoint_xfer_continue(ep);
+  if ( done )
+  {
+    hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
+  }
 }
 
 static void __tusb_irq_path_func(hw_handle_buff_status)(void)
 {
-    uint32_t remaining_buffers = usb_hw->buf_status;
-    pico_trace("buf_status 0x%08x\n", remaining_buffers);
+  uint32_t remaining_buffers = usb_hw->buf_status;
+  pico_trace("buf_status 0x%08x\n", remaining_buffers);
 
-    // Check EPX first
-    uint bit = 0b1;
-    if (remaining_buffers & bit)
+  // Check EPX first
+  uint bit = 0b1;
+  if ( remaining_buffers & bit )
+  {
+    remaining_buffers &= ~bit;
+    struct hw_endpoint * ep = &epx;
+
+    uint32_t ep_ctrl = *ep->endpoint_control;
+    if ( ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS )
     {
+      TU_LOG(3, "Double Buffered: ");
+    }
+    else
+    {
+      TU_LOG(3, "Single Buffered: ");
+    }
+    TU_LOG_HEX(3, ep_ctrl);
+
+    _handle_buff_status_bit(bit, ep);
+  }
+
+  // Check "interrupt" (asynchronous) endpoints for both IN and OUT
+  for ( uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++ )
+  {
+    // EPX is bit 0 & 1
+    // IEP1 IN  is bit 2
+    // IEP1 OUT is bit 3
+    // IEP2 IN  is bit 4
+    // IEP2 OUT is bit 5
+    // IEP3 IN  is bit 6
+    // IEP3 OUT is bit 7
+    // etc
+    for ( uint j = 0; j < 2; j++ )
+    {
+      bit = 1 << (i * 2 + j);
+      if ( remaining_buffers & bit )
+      {
         remaining_buffers &= ~bit;
-        struct hw_endpoint *ep = &epx;
-
-        uint32_t ep_ctrl = *ep->endpoint_control;
-        if (ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS)
-        {
-          TU_LOG(3, "Double Buffered: ");
-        }else
-        {
-          TU_LOG(3, "Single Buffered: ");
-        }
-        TU_LOG_HEX(3, ep_ctrl);
-
-        _handle_buff_status_bit(bit, ep);
+        _handle_buff_status_bit(bit, &ep_pool[i]);
+      }
     }
+  }
 
-    // Check "interrupt" (asynchronous) endpoints for both IN and OUT
-    for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++)
-    {
-        // EPX is bit 0 & 1
-        // IEP1 IN  is bit 2
-        // IEP1 OUT is bit 3
-        // IEP2 IN  is bit 4
-        // IEP2 OUT is bit 5
-        // IEP3 IN  is bit 6
-        // IEP3 OUT is bit 7
-        // etc
-        for(uint j = 0; j < 2; j++)
-        {
-            bit = 1 << (i*2+j);
-            if (remaining_buffers & bit)
-            {
-                remaining_buffers &= ~bit;
-                _handle_buff_status_bit(bit, &ep_pool[i]);
-            }
-        }
-    }
-
-    if (remaining_buffers)
-    {
-        panic("Unhandled buffer %d\n", remaining_buffers);
-    }
+  if ( remaining_buffers )
+  {
+    panic("Unhandled buffer %d\n", remaining_buffers);
+  }
 }
 
 static void __tusb_irq_path_func(hw_trans_complete)(void)
@@ -186,70 +187,72 @@ static void __tusb_irq_path_func(hw_trans_complete)(void)
 
 static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
 {
-    uint32_t status = usb_hw->ints;
-    uint32_t handled = 0;
+  uint32_t status = usb_hw->ints;
+  uint32_t handled = 0;
 
-    if (status & USB_INTS_HOST_CONN_DIS_BITS)
+  if ( status & USB_INTS_HOST_CONN_DIS_BITS )
+  {
+    handled |= USB_INTS_HOST_CONN_DIS_BITS;
+
+    if ( dev_speed() )
     {
-        handled |= USB_INTS_HOST_CONN_DIS_BITS;
-        
-        if (dev_speed())
-        {
-            hcd_event_device_attach(RHPORT_NATIVE, true);
-        }
-        else
-        {
-            hcd_event_device_remove(RHPORT_NATIVE, true);
-        }
-
-        // Clear speed change interrupt
-        usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS;
+      hcd_event_device_attach(RHPORT_NATIVE, true);
+    }
+    else
+    {
+      hcd_event_device_remove(RHPORT_NATIVE, true);
     }
 
-    if (status & USB_INTS_STALL_BITS)
-    {
-        // We have rx'd a stall from the device
-        // NOTE THIS SHOULD HAVE PRIORITY OVER BUFF_STATUS
-        // AND TRANS_COMPLETE as the stall is an alternative response
-        // to one of those events
-        pico_trace("Stall REC\n");
-        handled |= USB_INTS_STALL_BITS;
-        usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS;
-        hw_xfer_complete(&epx, XFER_RESULT_STALLED);
-    }
+    // Clear speed change interrupt
+    usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS;
+  }
 
-    if (status & USB_INTS_BUFF_STATUS_BITS)
-    {
-        handled |= USB_INTS_BUFF_STATUS_BITS;
-        TU_LOG(2, "Buffer complete\n");
-        hw_handle_buff_status();
-    }
+  if ( status & USB_INTS_STALL_BITS )
+  {
+    // We have rx'd a stall from the device
+    // NOTE THIS SHOULD HAVE PRIORITY OVER BUFF_STATUS
+    // AND TRANS_COMPLETE as the stall is an alternative response
+    // to one of those events
+    pico_trace("Stall REC\n");
+    handled |= USB_INTS_STALL_BITS;
+    usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS;
+    hw_xfer_complete(&epx, XFER_RESULT_STALLED);
+  }
 
-    if (status & USB_INTS_TRANS_COMPLETE_BITS)
-    {
-        handled |= USB_INTS_TRANS_COMPLETE_BITS;
-        usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
-        TU_LOG(2, "Transfer complete\n");
-        hw_trans_complete();
-    }
+  if ( status & USB_INTS_BUFF_STATUS_BITS )
+  {
+    handled |= USB_INTS_BUFF_STATUS_BITS;
+    TU_LOG(2, "Buffer complete\n");
+    hw_handle_buff_status();
+  }
 
-    if (status & USB_INTS_ERROR_RX_TIMEOUT_BITS)
-    {
-        handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS;
-        usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS;
-    }
+  if ( status & USB_INTS_TRANS_COMPLETE_BITS )
+  {
+    handled |= USB_INTS_TRANS_COMPLETE_BITS;
+    usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
+    TU_LOG(2, "Transfer complete\n");
+    hw_trans_complete();
+  }
 
-    if (status & USB_INTS_ERROR_DATA_SEQ_BITS)
-    {
-        usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
-        TU_LOG(3, "  Seq Error: [0] = 0x%04u  [1] = 0x%04x\r\n", tu_u32_low16(*epx.buffer_control), tu_u32_high16(*epx.buffer_control));
-        panic("Data Seq Error \n");
-    }
+  if ( status & USB_INTS_ERROR_RX_TIMEOUT_BITS )
+  {
+    handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS;
+    usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS;
+  }
 
-    if (status ^ handled)
-    {
-        panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
-    }
+  if ( status & USB_INTS_ERROR_DATA_SEQ_BITS )
+  {
+    usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
+    TU_LOG(3, "  Seq Error: [0] = 0x%04u  [1] = 0x%04x\r\n",
+           tu_u32_low16(*epx.buffer_control),
+           tu_u32_high16(*epx.buffer_control));
+    panic("Data Seq Error \n");
+  }
+
+  if ( status ^ handled )
+  {
+    panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
+  }
 }
 
 void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport)
@@ -260,116 +263,118 @@ void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport)
 
 static struct hw_endpoint *_next_free_interrupt_ep(void)
 {
-    struct hw_endpoint *ep = NULL;
-    for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++)
+  struct hw_endpoint * ep = NULL;
+  for ( uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++ )
+  {
+    ep = &ep_pool[i];
+    if ( !ep->configured )
     {
-        ep = &ep_pool[i];
-        if (!ep->configured)
-        {
-            // Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
-            ep->interrupt_num = (uint8_t) (i - 1);
-            return ep;
-        }
+      // Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
+      ep->interrupt_num = (uint8_t) (i - 1);
+      return ep;
     }
-    return ep;
+  }
+  return ep;
 }
 
 static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
 {
-    struct hw_endpoint *ep = NULL;
+  struct hw_endpoint * ep = NULL;
 
-    if (transfer_type != TUSB_XFER_CONTROL)
-    {
-        // Note: even though datasheet name these "Interrupt" endpoints. These are actually
-        // "Asynchronous" endpoints and can be used for other type such as: Bulk  (ISO need confirmation)
-        ep = _next_free_interrupt_ep();
-        pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num);
-        assert(ep);
-        ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
-        ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
-        // 0 for epx (double buffered): TODO increase to 1024 for ISO
-        // 2x64 for intep0
-        // 3x64 for intep1
-        // etc
-        ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)];
-    }
-    else
-    {
-        ep = &epx;
-        ep->buffer_control = &usbh_dpram->epx_buf_ctrl;
-        ep->endpoint_control = &usbh_dpram->epx_ctrl;
-        ep->hw_data_buf = &usbh_dpram->epx_data[0];
-    }
+  if ( transfer_type != TUSB_XFER_CONTROL )
+  {
+    // Note: even though datasheet name these "Interrupt" endpoints. These are actually
+    // "Asynchronous" endpoints and can be used for other type such as: Bulk  (ISO need confirmation)
+    ep = _next_free_interrupt_ep();
+    pico_info("Allocate %s ep %d\n", tu_edpt_type_str(transfer_type), ep->interrupt_num);
+    assert(ep);
+    ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
+    ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
+    // 0 for epx (double buffered): TODO increase to 1024 for ISO
+    // 2x64 for intep0
+    // 3x64 for intep1
+    // etc
+    ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)];
+  }
+  else
+  {
+    ep = &epx;
+    ep->buffer_control = &usbh_dpram->epx_buf_ctrl;
+    ep->endpoint_control = &usbh_dpram->epx_ctrl;
+    ep->hw_data_buf = &usbh_dpram->epx_data[0];
+  }
 
-    return ep;
+  return ep;
 }
 
 static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval)
 {
-    // Already has data buffer, endpoint control, and buffer control allocated at this point
-    assert(ep->endpoint_control);
-    assert(ep->buffer_control);
-    assert(ep->hw_data_buf);
+  // Already has data buffer, endpoint control, and buffer control allocated at this point
+  assert(ep->endpoint_control);
+  assert(ep->buffer_control);
+  assert(ep->hw_data_buf);
 
-    uint8_t const num = tu_edpt_number(ep_addr);
-    tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+  uint8_t const num = tu_edpt_number(ep_addr);
+  tusb_dir_t const dir = tu_edpt_dir(ep_addr);
 
-    ep->ep_addr = ep_addr;
-    ep->dev_addr = dev_addr;
+  ep->ep_addr = ep_addr;
+  ep->dev_addr = dev_addr;
 
-    // For host, IN to host == RX, anything else rx == false
-    ep->rx = (dir == TUSB_DIR_IN);
+  // For host, IN to host == RX, anything else rx == false
+  ep->rx = (dir == TUSB_DIR_IN);
 
-    // Response to a setup packet on EP0 starts with pid of 1
-    ep->next_pid = (num == 0 ? 1u : 0u);
-    ep->wMaxPacketSize = wMaxPacketSize;
-    ep->transfer_type = transfer_type;
+  // Response to a setup packet on EP0 starts with pid of 1
+  ep->next_pid = (num == 0 ? 1u : 0u);
+  ep->wMaxPacketSize = wMaxPacketSize;
+  ep->transfer_type = transfer_type;
 
-    pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type);
-    pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf);
-    uint dpram_offset = hw_data_offset(ep->hw_data_buf);
-    // Bits 0-5 should be 0
-    assert(!(dpram_offset & 0b111111));
+  pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr),
+             ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type);
+  pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr),
+             ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf);
+  uint dpram_offset = hw_data_offset(ep->hw_data_buf);
+  // Bits 0-5 should be 0
+  assert(!(dpram_offset & 0b111111));
 
-    // Fill in endpoint control register with buffer offset
-    uint32_t ep_reg =  EP_CTRL_ENABLE_BITS
-                  | EP_CTRL_INTERRUPT_PER_BUFFER
-                  | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
-                  | dpram_offset;
-    if (bmInterval)
+  // Fill in endpoint control register with buffer offset
+  uint32_t ep_reg = EP_CTRL_ENABLE_BITS
+                    | EP_CTRL_INTERRUPT_PER_BUFFER
+                    | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
+                    | dpram_offset;
+  if ( bmInterval )
+  {
+    ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
+  }
+  *ep->endpoint_control = ep_reg;
+  pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
+  ep->configured = true;
+
+  if ( ep != &epx )
+  {
+    // Endpoint has its own addr_endp and interrupt bits to be setup!
+    // This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with:
+    // - device address
+    // - endpoint number / direction
+    // - preamble
+    uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
+
+    if ( dir == TUSB_DIR_OUT )
     {
-      ep_reg |= (uint32_t) ((bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB);
+      reg |= USB_ADDR_ENDP1_INTEP_DIR_BITS;
     }
-    *ep->endpoint_control = ep_reg;
-    pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
-    ep->configured = true;
 
-    if (ep != &epx)
+    if ( need_pre(dev_addr) )
     {
-        // Endpoint has its own addr_endp and interrupt bits to be setup!
-        // This is an interrupt/async endpoint. so need to set up ADDR_ENDP register with:
-        // - device address
-        // - endpoint number / direction
-        // - preamble
-        uint32_t reg = (uint32_t) (dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB));
-
-        if (dir == TUSB_DIR_OUT)
-        {
-            reg |= USB_ADDR_ENDP1_INTEP_DIR_BITS;
-        }
-
-        if (need_pre(dev_addr))
-        {
-            reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS;
-        }
-        usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg;
-
-        // Finally, enable interrupt that endpoint
-        usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1);
-
-        // If it's an interrupt endpoint we need to set up the buffer control
-        // register
+      reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS;
     }
+    usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg;
+
+    // Finally, enable interrupt that endpoint
+    usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1);
+
+    // If it's an interrupt endpoint we need to set up the buffer control
+    // register
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -434,16 +439,17 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   (void) rhport;
   assert(rhport == 0);
+
   // TODO: Should enumval this register
-  switch (dev_speed())
+  switch ( dev_speed() )
   {
-      case 1:
-          return TUSB_SPEED_LOW;
-      case 2:
-          return TUSB_SPEED_FULL;
-      default:
-          panic("Invalid speed\n");
-          return TUSB_SPEED_INVALID;
+    case 1:
+      return TUSB_SPEED_LOW;
+    case 2:
+      return TUSB_SPEED_FULL;
+    default:
+      panic("Invalid speed\n");
+      return TUSB_SPEED_INVALID;
   }
 }
 
@@ -476,8 +482,8 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 
 uint32_t hcd_frame_number(uint8_t rhport)
 {
-    (void) rhport;
-    return usb_hw->sof_rd;
+  (void) rhport;
+  return usb_hw->sof_rd;
 }
 
 void hcd_int_enable(uint8_t rhport)
@@ -501,117 +507,116 @@ void hcd_int_disable(uint8_t rhport)
 
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
-    (void) rhport;
+  (void) rhport;
 
-    pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
+  pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
 
-    // Allocated differently based on if it's an interrupt endpoint or not
-    struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
-    TU_ASSERT(ep);
+  // Allocated differently based on if it's an interrupt endpoint or not
+  struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
+  TU_ASSERT(ep);
 
-    _hw_endpoint_init(ep,
-        dev_addr,
-        ep_desc->bEndpointAddress,
-        tu_edpt_packet_size(ep_desc),
-        ep_desc->bmAttributes.xfer,
-        ep_desc->bInterval);
+  _hw_endpoint_init(ep,
+                    dev_addr,
+                    ep_desc->bEndpointAddress,
+                    tu_edpt_packet_size(ep_desc),
+                    ep_desc->bmAttributes.xfer,
+                    ep_desc->bInterval);
 
-    return true;
+  return true;
 }
 
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
-    (void) rhport;
+  (void) rhport;
 
-    pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
-    
-    uint8_t const ep_num = tu_edpt_number(ep_addr);
-    tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
+  pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
 
-    // Get appropriate ep. Either EPX or interrupt endpoint
-    struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
 
-    TU_ASSERT(ep);
+  // Get appropriate ep. Either EPX or interrupt endpoint
+  struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
 
-    // EP should be inactive
-    assert(!ep->active);
+  TU_ASSERT(ep);
 
-    // Control endpoint can change direction 0x00 <-> 0x80
-    if ( ep_addr != ep->ep_addr )
-    {
-      assert(ep_num == 0);
+  // EP should be inactive
+  assert(!ep->active);
 
-      // Direction has flipped on endpoint control so re init it but with same properties
-      _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
-    }
+  // Control endpoint can change direction 0x00 <-> 0x80
+  if ( ep_addr != ep->ep_addr )
+  {
+    assert(ep_num == 0);
 
-    // If a normal transfer (non-interrupt) then initiate using
-    // sie ctrl registers. Otherwise interrupt ep registers should
-    // already be configured
-    if (ep == &epx) {
-        hw_endpoint_xfer_start(ep, buffer, buflen);
+    // Direction has flipped on endpoint control so re init it but with same properties
+    _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
+  }
 
-        // That has set up buffer control, endpoint control etc
-        // for host we have to initiate the transfer
-        usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB));
+  // If a normal transfer (non-interrupt) then initiate using
+  // sie ctrl registers. Otherwise interrupt ep registers should
+  // already be configured
+  if ( ep == &epx )
+  {
+    hw_endpoint_xfer_start(ep, buffer, buflen);
 
-        uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
-                         (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS);
-        // Set pre if we are a low speed device on full speed hub
-        flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
+    // That has set up buffer control, endpoint control etc
+    // for host we have to initiate the transfer
+    usb_hw->dev_addr_ctrl = (uint32_t) (dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB));
 
-        usb_hw->sie_ctrl = flags;
-    }else
-    {
-      hw_endpoint_xfer_start(ep, buffer, buflen);
-    }
+    uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
+                     (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS) |
+                     (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
+    usb_hw->sie_ctrl = flags;
+  }else
+  {
+    hw_endpoint_xfer_start(ep, buffer, buflen);
+  }
 
-    return true;
+  return true;
 }
 
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
-    (void) rhport;
+  (void) rhport;
 
-    // Copy data into setup packet buffer
-    for(uint8_t i=0; i<8; i++)
-    {
-      usbh_dpram->setup_packet[i] = setup_packet[i];
-    }
+  // Copy data into setup packet buffer
+  for ( uint8_t i = 0; i < 8; i++ )
+  {
+    usbh_dpram->setup_packet[i] = setup_packet[i];
+  }
 
-    // Configure EP0 struct with setup info for the trans complete
-    struct hw_endpoint *ep = _hw_endpoint_allocate(0);
-    TU_ASSERT(ep);
+  // Configure EP0 struct with setup info for the trans complete
+  struct hw_endpoint * ep = _hw_endpoint_allocate(0);
+  TU_ASSERT(ep);
 
-    // EPX should be inactive
-    assert(!ep->active);
+  // EPX should be inactive
+  assert(!ep->active);
 
-    // EP0 out
-    _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
-    assert(ep->configured);
+  // EP0 out
+  _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
+  assert(ep->configured);
 
-    ep->remaining_len = 8;
-    ep->active        = true;
+  ep->remaining_len = 8;
+  ep->active = true;
 
-    // Set device address
-    usb_hw->dev_addr_ctrl = dev_addr;
+  // Set device address
+  usb_hw->dev_addr_ctrl = dev_addr;
 
-    // Set pre if we are a low speed device on full speed hub
-    uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
-                           (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
+  // Set pre if we are a low speed device on full speed hub
+  uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
+                         (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
 
-    usb_hw->sie_ctrl = flags;
+  usb_hw->sie_ctrl = flags;
 
-    return true;
+  return true;
 }
 
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
-    (void) dev_addr;
-    (void) ep_addr;
+  (void) dev_addr;
+  (void) ep_addr;
 
-    panic("hcd_clear_stall");
-    return true;
+  panic("hcd_clear_stall");
+  return true;
 }
 
 #endif
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index d7895175e..5c7645902 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -47,6 +47,12 @@ TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_lock_update(__unused struc
 static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
 static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
 
+// if usb hardware is in host mode
+TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void)
+{
+  return (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) ? true : false;
+}
+
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
@@ -69,6 +75,8 @@ void rp2040_usb_init(void)
 
   // Mux the controller to the onboard usb phy
   usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;
+
+  TU_LOG2_INT(sizeof(hw_endpoint_t));
 }
 
 void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
@@ -80,19 +88,23 @@ void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
 }
 
 void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
-    uint32_t value = 0;
-    if (and_mask) {
-        value = *ep->buffer_control & and_mask;
-    }
-    if (or_mask) {
-        value |= or_mask;
-        if (or_mask & USB_BUF_CTRL_AVAIL) {
-            if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) {
-                panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
-            }
-            *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
-            // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz)
-            // Don't need delay in host mode as host is in charge
+  uint32_t value = 0;
+  if ( and_mask )
+  {
+    value = *ep->buffer_control & and_mask;
+  }
+  if ( or_mask )
+  {
+    value |= or_mask;
+    if ( or_mask & USB_BUF_CTRL_AVAIL )
+    {
+      if ( *ep->buffer_control & USB_BUF_CTRL_AVAIL )
+      {
+        panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+      }
+      *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
+      // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz)
+      // Don't need delay in host mode as host is in charge
 #if !CFG_TUH_ENABLED
             __asm volatile (
                     "b 1f\n"
@@ -104,9 +116,9 @@ void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoi
                     "1:\n"
                     : : : "memory");
 #endif
-        }
     }
-    *ep->buffer_control = value;
+  }
+  *ep->buffer_control = value;
 }
 
 // prepare buffer, return buffer control
@@ -152,12 +164,14 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo
   // always compute and start with buffer 0
   uint32_t buf_ctrl = prepare_ep_buffer(ep, 0) | USB_BUF_CTRL_SEL;
 
-  // For now: skip double buffered for Device mode, OUT endpoint since
+  // For now: skip double buffered for OUT endpoint in Device mode, since
   // host could send < 64 bytes and cause short packet on buffer0
-  // NOTE this could happen to Host mode IN endpoint
-  // Also, Host mode interrupt endpoint hardware is only single buffered
-  bool const force_single = (!(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr)) ||
-    ((usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && tu_edpt_number(ep->ep_addr) != 0);
+  // NOTE: this could happen to Host mode IN endpoint
+  // Also, Host mode "interrupt" endpoint hardware is only single buffered,
+  // NOTE2: Currently Host bulk is implemented using "interrupt" endpoint
+  bool const is_host = is_host_mode();
+  bool const force_single = (!is_host && !tu_edpt_dir(ep->ep_addr)) ||
+                            (is_host && tu_edpt_number(ep->ep_addr) != 0);
 
   if(ep->remaining_len && !force_single)
   {

From c9c7dfa868ea78afd6b3bb490542e65660c39149 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 30 Nov 2022 18:59:58 +0700
Subject: [PATCH 1251/2085] more clean up

---
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 42 +++++++++++---------
 1 file changed, 23 insertions(+), 19 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index c72dae64c..b65d32fd4 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -82,26 +82,30 @@ void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
 
 void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask);
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32(struct hw_endpoint *ep) {
-    return *ep->buffer_control;
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32(struct hw_endpoint *ep, uint32_t value) {
-    return _hw_endpoint_buffer_control_update32(ep, 0, value);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32(struct hw_endpoint *ep, uint32_t value) {
-    return _hw_endpoint_buffer_control_update32(ep, ~value, value);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32(struct hw_endpoint *ep, uint32_t value) {
-    return _hw_endpoint_buffer_control_update32(ep, ~value, 0);
-}
-
-static inline uintptr_t hw_data_offset(uint8_t *buf)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t _hw_endpoint_buffer_control_get_value32 (struct hw_endpoint *ep)
 {
-    // Remove usb base from buffer pointer
-    return (uintptr_t)buf ^ (uintptr_t)usb_dpram;
+  return *ep->buffer_control;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_value32 (struct hw_endpoint *ep, uint32_t value)
+{
+  return _hw_endpoint_buffer_control_update32(ep, 0, value);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_set_mask32 (struct hw_endpoint *ep, uint32_t value)
+{
+  return _hw_endpoint_buffer_control_update32(ep, ~value, value);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_buffer_control_clear_mask32 (struct hw_endpoint *ep, uint32_t value)
+{
+  return _hw_endpoint_buffer_control_update32(ep, ~value, 0);
+}
+
+static inline uintptr_t hw_data_offset (uint8_t *buf)
+{
+  // Remove usb base from buffer pointer
+  return (uintptr_t) buf ^ (uintptr_t) usb_dpram;
 }
 
 extern const char *ep_dir_string[];

From 1437ad1dfb5b48169f680253707821bd9751fc65 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 30 Nov 2022 12:15:27 +0000
Subject: [PATCH 1252/2085] Add endpoint definitions for more example projects.

---
 .../dynamic_configuration/src/usb_descriptors.c     | 13 +++++++++++++
 examples/device/msc_dual_lun/src/usb_descriptors.c  |  6 ++++++
 examples/device/uac2_headset/src/usb_descriptors.c  |  6 ++++++
 examples/device/webusb_serial/src/usb_descriptors.c |  7 +++++++
 4 files changed, 32 insertions(+)

diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index 457f774d0..092229b99 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -145,6 +145,19 @@ enum
   #define EPNUM_1_MSC_OUT     0x01
   #define EPNUM_1_MSC_IN      0x82
 
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_0_CDC_NOTIF   0x81
+  #define EPNUM_0_CDC_OUT     0x02
+  #define EPNUM_0_CDC_IN      0x83
+
+  #define EPNUM_0_MIDI_OUT    0x04
+  #define EPNUM_0_MIDI_IN     0x85
+
+  #define EPNUM_1_MSC_OUT     0x01
+  #define EPNUM_1_MSC_IN      0x82
+
 #else
   #define EPNUM_0_CDC_NOTIF   0x81
   #define EPNUM_0_CDC_OUT     0x02
diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c
index 68a671c91..d8dbb5ce3 100644
--- a/examples/device/msc_dual_lun/src/usb_descriptors.c
+++ b/examples/device/msc_dual_lun/src/usb_descriptors.c
@@ -90,6 +90,12 @@ enum
   #define EPNUM_MSC_OUT   0x01
   #define EPNUM_MSC_IN    0x82
 
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_MSC_OUT   0x01
+  #define EPNUM_MSC_IN    0x82
+
 #else
   #define EPNUM_MSC_OUT   0x01
   #define EPNUM_MSC_IN    0x81
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 10f5cbd27..07c86b903 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -93,6 +93,12 @@ uint8_t const * tud_descriptor_device_cb(void)
   #define EPNUM_AUDIO_IN    0x01
   #define EPNUM_AUDIO_OUT   0x02
 
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_AUDIO_IN    0x01
+  #define EPNUM_AUDIO_OUT   0x02
+
 #else
   #define EPNUM_AUDIO_IN    0x01
   #define EPNUM_AUDIO_OUT   0x01
diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c
index cafe2c22b..99f5caaf9 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.c
+++ b/examples/device/webusb_serial/src/usb_descriptors.c
@@ -97,6 +97,13 @@ enum
   #define EPNUM_CDC_OUT    3
   #define EPNUM_VENDOR_IN  4
   #define EPNUM_VENDOR_OUT 5
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_CDC_IN     2
+  #define EPNUM_CDC_OUT    3
+  #define EPNUM_VENDOR_IN  4
+  #define EPNUM_VENDOR_OUT 5
 #else
   #define EPNUM_CDC_IN     2
   #define EPNUM_CDC_OUT    2

From d3c4f66d3587f4a733ba974d6ab4f4cb96ffde29 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 30 Nov 2022 12:49:15 +0000
Subject: [PATCH 1253/2085] Fix script issues with paths including spaces from
 env variable.

$(FT90X_TOOLCHAIN) or even $(TOP) may have spaces. Quote to fix.
---
 hw/bsp/brtmm90x/family.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index f45e27cb5..0ddf47a3a 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -8,7 +8,7 @@ ifeq ($(FT9XX_PREBUILT_LIBS),1)
 # If the FT90X toolchain is installed on Windows systems then the SDK 
 # include files and prebuilt libraries are at: %FT90X_TOOLCHAIN%/hardware
 FT9XX_SDK = $(FT90X_TOOLCHAIN)/hardware
-INC += $(FT9XX_SDK)/include
+INC += "$(FT9XX_SDK)/include"
 else
 # The submodule BRTSG-FOSS/ft90x-sdk contains header files and source
 # code for the Bridgetek SDK. This can be used instead of the prebuilt
@@ -16,7 +16,7 @@ else
 DEPS_SUBMODULES += hw/mcu/bridgetek/ft9xx/ft90x-sdk
 # The SDK can be used to load specific files from the Bridgetek SDK.
 FT9XX_SDK = hw/mcu/bridgetek/ft9xx/ft90x-sdk/Source
-INC += $(TOP)/$(FT9XX_SDK)/include
+INC += "$(TOP)/$(FT9XX_SDK)/include"
 endif
 
 # Add include files which are within the TinyUSB directory structure.

From 25abb10de17ed868b2189ae5038a7c47aab19ae5 Mon Sep 17 00:00:00 2001
From: pete-pjb <petebone00@gmail.com>
Date: Wed, 30 Nov 2022 13:26:59 +0000
Subject: [PATCH 1254/2085] Fix white space issue.

---
 src/osal/osal_freertos.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index a2b0573f8..fed70400e 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -62,7 +62,7 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 //--------------------------------------------------------------------+
 // Semaphore API
 //--------------------------------------------------------------------+
-#if configSUPPORT_STATIC_ALLOCATION	== 1
+#if configSUPPORT_STATIC_ALLOCATION == 1
 typedef StaticSemaphore_t osal_semaphore_def_t;
 #else
 typedef SemaphoreHandle_t osal_semaphore_def_t;
@@ -71,7 +71,7 @@ typedef SemaphoreHandle_t osal_semaphore_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
 {
-#if configSUPPORT_STATIC_ALLOCATION	== 1
+#if configSUPPORT_STATIC_ALLOCATION == 1
   return xSemaphoreCreateBinaryStatic(semdef);
 #else
   return xSemaphoreCreateBinary();
@@ -113,7 +113,7 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c
 //--------------------------------------------------------------------+
 // MUTEX API (priority inheritance)
 //--------------------------------------------------------------------+
-#if configSUPPORT_STATIC_ALLOCATION	== 1
+#if configSUPPORT_STATIC_ALLOCATION == 1
 typedef StaticSemaphore_t osal_mutex_def_t;
 #else
 typedef SemaphoreHandle_t osal_mutex_def_t;
@@ -122,7 +122,7 @@ typedef SemaphoreHandle_t osal_mutex_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
-#if configSUPPORT_STATIC_ALLOCATION	== 1
+#if configSUPPORT_STATIC_ALLOCATION == 1
   return xSemaphoreCreateMutexStatic(mdef);
 #else
   return xSemaphoreCreateMutex();
@@ -162,7 +162,7 @@ typedef QueueHandle_t osal_queue_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
-#if configSUPPORT_STATIC_ALLOCATION	== 1
+#if configSUPPORT_STATIC_ALLOCATION == 1
 	return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
 #else
   return xQueueCreate(qdef->depth, qdef->item_sz);

From 8cce9385e20986e0f59f9b1ee54331a09d3193de Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Wed, 30 Nov 2022 16:18:07 +0000
Subject: [PATCH 1255/2085] More configurable board options

---
 hw/bsp/brtmm90x/boards/mm900evxb/board.h | 50 +++++++++++----
 hw/bsp/brtmm90x/family.c                 | 80 +++++++++++++-----------
 2 files changed, 80 insertions(+), 50 deletions(-)

diff --git a/hw/bsp/brtmm90x/boards/mm900evxb/board.h b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
index 76813b116..191803ddf 100644
--- a/hw/bsp/brtmm90x/boards/mm900evxb/board.h
+++ b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
@@ -35,23 +35,47 @@
  extern "C" {
 #endif
 
+#include <tinyprintf.h>
+
+// UART to use on this board.
+#ifndef BOARD_UART
+#define BOARD_UART UART0
+#endif
+
 // UART is on connector CN1.
-#define GPIO_UART0_TX 48 // Pin 4 of CN1.
-#define GPIO_UART0_RX 49 // Pin 6 of CN1.
+#ifndef BOARD_GPIO_UART0_TX
+#define BOARD_GPIO_UART0_TX 48 // Pin 4 of CN1.
+#endif
+#ifndef BOARD_GPIO_UART0_RX
+#define BOARD_GPIO_UART0_RX 49 // Pin 6 of CN1.
+#endif
 
-// LED is connected to pins 4 (signal) and 2 (GND) of CN2.
-#define GPIO_LED 36
-// Button is connected to pins 6 (signal) and 2 (GND) of CN2.
-#define GPIO_BUTTON 37
-
-// Remote wakeup is wired to pin 40 of CN1.
-#define GPIO_REMOTE_WAKEUP_PIN 18
-
-// USB VBus signal is connected directly to the FT900.
-#define USBD_VBUS_DTC_PIN 3
+// LED is connected to pins 17 (signal) and 15 (GND) of CN1.
+#ifndef BOARD_GPIO_LED
+#define BOARD_GPIO_LED 35
+#endif
+#ifndef BOARD_GPIO_LED_STATE_ON
+#define BOARD_GPIO_LED_STATE_ON 1
+#endif
+// Button is connected to pins 13 (signal) and 15 (GND) of CN1.
+#ifndef BOARD_GPIO_BUTTON
+#define BOARD_GPIO_BUTTON 56
+#endif
+// Button is pulled up and grounded for active.
+#ifndef BOARD_GPIO_BUTTON_STATE_ACTIVE
+#define BOARD_GPIO_BUTTON_STATE_ACTIVE 0
+#endif
 
 // Enable the Remote Wakeup signalling.
-#define GPIO_REMOTE_WAKEUP
+// Remote wakeup is wired to pin 40 of CN1.
+#ifndef BOARD_GPIO_REMOTE_WAKEUP
+#define BOARD_GPIO_REMOTE_WAKEUP 18
+#endif
+
+// USB VBus signal is connected directly to the FT900.
+#ifndef BOARD_USBD_VBUS_DTC_PIN
+#define BOARD_USBD_VBUS_DTC_PIN 3
+#endif
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 8155c0afc..3b6b03904 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -35,7 +35,7 @@ int8_t board_ft9xx_vbus(void); // Board specific implementation of VBUS detectio
 extern void ft9xx_usbd_pm_ISR(uint16_t pmcfg); // Interrupt handler for USB device power management
 #endif
 
-#ifdef GPIO_REMOTE_WAKEUP
+#ifdef BOARD_GPIO_REMOTE_WAKEUP
 void gpio_ISR(void);
 #endif
 void timer_ISR(void);
@@ -52,14 +52,14 @@ void board_init(void)
 
     // Enable the UART Device.
     sys_enable(sys_device_uart0);
-    // Set UART0 GPIO functions to UART0_TXD and UART0_RXD.
-#ifdef GPIO_UART0_TX
-    gpio_function(GPIO_UART0_TX, pad_uart0_txd); /* UART0 TXD */
+    // Set BOARD_UART GPIO function pins for TXD and RXD.
+#ifdef BOARD_GPIO_UART_TX
+    gpio_function(BOARD_GPIO_UART_TX, pad_uart0_txd); /* UART0 TXD */
 #endif
-#ifdef GPIO_UART0_RX
-    gpio_function(GPIO_UART0_RX, pad_uart0_rxd); /* UART0 RXD */
+#ifdef BOARD_GPIO_UART_RX
+    gpio_function(BOARD_GPIO_UART_RX, pad_uart0_rxd); /* UART0 RXD */
 #endif
-    uart_open(UART0,                             /* Device */
+    uart_open(BOARD_UART,                             /* Device */
               1,                                 /* Prescaler = 1 */
               UART_DIVIDER_19200_BAUD,           /* Divider = 1302 */
               uart_data_bits_8,                  /* No. Data Bits */
@@ -69,16 +69,17 @@ void board_init(void)
     // Use sizeof to avoid pulling in strlen unnecessarily.
     board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG));
 
-#ifdef GPIO_LED
-    gpio_function(GPIO_LED, pad_func_0); 
-    gpio_idrive(GPIO_LED, pad_drive_12mA);
-    gpio_dir(GPIO_LED, pad_dir_output);
+#ifdef BOARD_GPIO_LED
+    gpio_function(BOARD_GPIO_LED, pad_func_0); 
+    gpio_idrive(BOARD_GPIO_LED, pad_drive_12mA);
+    gpio_dir(BOARD_GPIO_LED, pad_dir_output);
 #endif
 
-#ifdef GPIO_BUTTON
-    gpio_function(GPIO_BUTTON, pad_func_0);
-    gpio_pull(GPIO_BUTTON, pad_pull_pullup);
-    gpio_dir(GPIO_BUTTON, pad_dir_input);
+#ifdef BOARD_GPIO_BUTTON
+    gpio_function(BOARD_GPIO_BUTTON, pad_func_0);
+    // Pull up if active low. Down if active high.
+    gpio_pull(BOARD_GPIO_BUTTON, (BOARD_GPIO_BUTTON_STATE_ACTIVE == 0)?pad_pull_pullup:pad_pull_pulldown);
+    gpio_dir(BOARD_GPIO_BUTTON, pad_dir_input);
 #endif
 
 	sys_enable(sys_device_timer_wdt);
@@ -91,26 +92,26 @@ void board_init(void)
 
     // Setup VBUS detect GPIO. If the device is connected then this
     // will set the MASK_SYS_PMCFG_DEV_DETECT_EN bit in PMCFG.
-    gpio_interrupt_disable(USBD_VBUS_DTC_PIN);
-    gpio_function(USBD_VBUS_DTC_PIN, pad_vbus_dtc);
-    gpio_pull(USBD_VBUS_DTC_PIN, pad_pull_pulldown);
-    gpio_dir(USBD_VBUS_DTC_PIN, pad_dir_input);
+    gpio_interrupt_disable(BOARD_USBD_VBUS_DTC_PIN);
+    gpio_function(BOARD_USBD_VBUS_DTC_PIN, pad_vbus_dtc);
+    gpio_pull(BOARD_USBD_VBUS_DTC_PIN, pad_pull_pulldown);
+    gpio_dir(BOARD_USBD_VBUS_DTC_PIN, pad_dir_input);
 
     interrupt_attach(interrupt_0, (int8_t)interrupt_0, board_pm_ISR);
 
-#ifdef GPIO_REMOTE_WAKEUP
-    //Configuring GPIO pin to wakeup.
+#ifdef BOARD_GPIO_REMOTE_WAKEUP
+    // Configuring GPIO pin to wakeup.
     // Set up the wakeup pin.
-    gpio_dir(GPIO_REMOTE_WAKEUP_PIN, pad_dir_input);
-    gpio_pull(GPIO_REMOTE_WAKEUP_PIN, pad_pull_pullup);
+    gpio_dir(BOARD_GPIO_REMOTE_WAKEUP, pad_dir_input);
+    gpio_pull(BOARD_GPIO_REMOTE_WAKEUP, pad_pull_pullup);
 
     // Attach an interrupt handler.
     interrupt_attach(interrupt_gpio, (uint8_t)interrupt_gpio, gpio_ISR);
-    gpio_interrupt_enable(GPIO_REMOTE_WAKEUP_PIN, gpio_int_edge_falling);
+    gpio_interrupt_enable(BOARD_GPIO_REMOTE_WAKEUP, gpio_int_edge_falling);
 #endif
 
-	uart_disable_interrupt(UART0, uart_interrupt_tx);
-	uart_disable_interrupt(UART0, uart_interrupt_rx);
+	uart_disable_interrupt(BOARD_UART, uart_interrupt_tx);
+	uart_disable_interrupt(BOARD_UART, uart_interrupt_rx);
 
     // Enable all peripheral interrupts.
     interrupt_enable_globally();
@@ -126,10 +127,10 @@ void timer_ISR(void)
     }
 }
 
-#ifdef GPIO_REMOTE_WAKEUP
+#ifdef BOARD_GPIO_REMOTE_WAKEUP
 void gpio_ISR(void)
 {
-    if (gpio_is_interrupted(GPIO_REMOTE_WAKEUP_PIN))
+    if (gpio_is_interrupted(BOARD_GPIO_REMOTE_WAKEUP))
     {
     }
 }
@@ -171,7 +172,7 @@ void board_pm_ISR(void)
 #if CFG_TUD_ENABLED
 int8_t board_ft9xx_vbus(void)
 {
-	return gpio_read(USBD_VBUS_DTC_PIN);
+	return gpio_read(BOARD_USBD_VBUS_DTC_PIN);
 }
 #endif
 
@@ -182,8 +183,8 @@ int8_t board_ft9xx_vbus(void)
 // Turn LED on or off
 void board_led_write(bool state)
 {
-#ifdef GPIO_LED
-    gpio_write(GPIO_LED, state);
+#ifdef BOARD_GPIO_LED
+    gpio_write(BOARD_GPIO_LED, (state == 0)?(BOARD_GPIO_LED_STATE_ON?0:1):BOARD_GPIO_LED_STATE_ON);
 #endif
 }
 
@@ -192,9 +193,8 @@ void board_led_write(bool state)
 uint32_t board_button_read(void)
 {
     uint32_t state = 0;
-#ifdef GPIO_BUTTON
-    state = gpio_read(GPIO_BUTTON);
-    state = !state;
+#ifdef BOARD_GPIO_BUTTON
+    state = (gpio_read(BOARD_GPIO_BUTTON) == BOARD_GPIO_BUTTON_STATE_ACTIVE)?1:0;
 #endif
     return state;
 }
@@ -204,10 +204,12 @@ int board_uart_read(uint8_t *buf, int len)
 {
     int r = 0;
 
-    if (uart_rx_has_data(UART0))
+#ifdef BOARD_UART
+    if (uart_rx_has_data(BOARD_UART))
     {
-        r = uart_readn(UART0, (uint8_t *)buf, len);
+        r = uart_readn(BOARD_UART, (uint8_t *)buf, len);
     }
+#endif
 
     return r;
 }
@@ -215,10 +217,14 @@ int board_uart_read(uint8_t *buf, int len)
 // Send characters to UART
 int board_uart_write(void const *buf, int len)
 {
+    int r = 0;
+
+#ifdef BOARD_UART
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wcast-qual" // uart_writen does not have const for buffer parameter.
-    int r = uart_writen(UART0, (uint8_t *)((const void *)buf), len);
+    r = uart_writen(BOARD_UART, (uint8_t *)((const void *)buf), len);
 #pragma GCC diagnostic pop
+#endif
 
     return r;
 }

From ae588d796e1b035c7efd582a4e4f3fc28b3a5ac0 Mon Sep 17 00:00:00 2001
From: PeterB <PeterB@PETE-LT.otg.local>
Date: Thu, 1 Dec 2022 16:06:15 +0000
Subject: [PATCH 1256/2085] Alter tuh_task_ext() function so no need to return
 when using FreeRTOS

---
 src/host/usbh.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index d97b160c9..a90b54924 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -509,7 +509,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
       default: break;
     }
 
-#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
+#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO && CFG_TUSB_OS != OPT_OS_FREERTOS
     // return if there is no more events, for application to run other background
     if (osal_queue_empty(_usbh_q)) return;
 #endif

From c31b95c91652f58b8b991a5481c9f7c37be7f09a Mon Sep 17 00:00:00 2001
From: pete-pjb <petebone00@gmail.com>
Date: Thu, 1 Dec 2022 17:53:35 +0000
Subject: [PATCH 1257/2085] Added CFG_TUSB_MEM_SECTION define to struct
 _ctrl_xfer in usbh.c

---
 src/host/usbh.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index a90b54924..f28554b81 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -246,8 +246,8 @@ static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
 // Control transfer: since most controller does not support multiple control transfer
 // on multiple devices concurrently. And control transfer is not used much except enumeration
-// We will only execute control transfer one at a time.
-struct
+// We will only execute control transfer one at a time.CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4096)
+CFG_TUSB_MEM_SECTION struct
 {
   tusb_control_request_t request TU_ATTR_ALIGNED(4);
   uint8_t* buffer;

From 3816869fce15509fd43eb5a6d14de76478f86cf1 Mon Sep 17 00:00:00 2001
From: pete-pjb <petebone00@gmail.com>
Date: Fri, 2 Dec 2022 10:00:19 +0000
Subject: [PATCH 1258/2085] Some reverts and changes after discussion.

---
 src/host/usbh.c          | 6 +++---
 src/osal/osal_freertos.h | 5 ++++-
 src/portable/ehci/ehci.c | 3 ++-
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index f28554b81..d97b160c9 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -246,8 +246,8 @@ static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
 // Control transfer: since most controller does not support multiple control transfer
 // on multiple devices concurrently. And control transfer is not used much except enumeration
-// We will only execute control transfer one at a time.CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4096)
-CFG_TUSB_MEM_SECTION struct
+// We will only execute control transfer one at a time.
+struct
 {
   tusb_control_request_t request TU_ATTR_ALIGNED(4);
   uint8_t* buffer;
@@ -509,7 +509,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
       default: break;
     }
 
-#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO && CFG_TUSB_OS != OPT_OS_FREERTOS
+#if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO
     // return if there is no more events, for application to run other background
     if (osal_queue_empty(_usbh_q)) return;
 #endif
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index fed70400e..ccb98cc99 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -74,6 +74,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_
 #if configSUPPORT_STATIC_ALLOCATION == 1
   return xSemaphoreCreateBinaryStatic(semdef);
 #else
+  (void)(semdef);
   return xSemaphoreCreateBinary();
 #endif
 }
@@ -125,6 +126,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_de
 #if configSUPPORT_STATIC_ALLOCATION == 1
   return xSemaphoreCreateMutexStatic(mdef);
 #else
+  (void)(mdef);
   return xSemaphoreCreateMutex();
 #endif
 
@@ -154,8 +156,9 @@ typedef struct
   uint16_t depth;
   uint16_t item_sz;
   void*    buf;
-
+#if configSUPPORT_STATIC_ALLOCATION == 1
   StaticQueue_t sq;
+#endif
 }osal_queue_def_t;
 
 typedef QueueHandle_t osal_queue_t;
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 76ba2a921..0af8c3b2d 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -193,7 +193,8 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
   {
     // TODO check type for ISO iTD and siTD
     // TODO Suppress cast-align warning
-    #pragma GCC diagnostic push
+	if( prev == NULL ) break;
+	#pragma GCC diagnostic push
     #pragma GCC diagnostic ignored "-Wcast-align"
     ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev);
     #pragma GCC diagnostic pop

From 52261ac02dfbe58f35f959be852f0949cc0744cd Mon Sep 17 00:00:00 2001
From: pete-pjb <petebone00@gmail.com>
Date: Fri, 2 Dec 2022 10:13:35 +0000
Subject: [PATCH 1259/2085] Back out another of my changes I am still
 investigating.

---
 src/portable/ehci/ehci.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 0af8c3b2d..361015964 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -193,7 +193,6 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
   {
     // TODO check type for ISO iTD and siTD
     // TODO Suppress cast-align warning
-	if( prev == NULL ) break;
 	#pragma GCC diagnostic push
     #pragma GCC diagnostic ignored "-Wcast-align"
     ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev);

From 6a2cf6728906aa61b44ecfe43b4ceef287b29bf8 Mon Sep 17 00:00:00 2001
From: Bastien Nocera <hadess@hadess.net>
Date: Sun, 4 Dec 2022 13:58:47 +0700
Subject: [PATCH 1260/2085] Fix typos

---
 .github/ISSUE_TEMPLATE/bug_report.yml         |  2 +-
 docs/contributing/porting.rst                 |  4 ++--
 docs/info/changelog.rst                       | 22 +++++++++----------
 examples/device/cdc_msc/src/main.c            |  2 +-
 .../device/cdc_msc_freertos/CMakeLists.txt    |  2 +-
 examples/device/dfu_runtime/src/main.c        |  2 +-
 examples/device/hid_boot_interface/src/main.c |  6 ++---
 examples/host/cdc_msc_hid/src/hid_app.c       |  2 +-
 hw/bsp/ansi_escape.h                          |  2 +-
 .../led_strip/src/led_strip_rmt_ws2812.c      |  2 +-
 .../led_strip/src/led_strip_rmt_ws2812.c      |  2 +-
 hw/bsp/family_support.cmake                   |  4 ++--
 hw/bsp/gd32vf103/family.c                     |  2 +-
 hw/bsp/gd32vf103/system_gd32vf103.c           |  2 +-
 .../evkmimxrt1010_flexspi_nor_config.h        | 10 ++++-----
 .../evkmimxrt1015_flexspi_nor_config.h        | 10 ++++-----
 .../evkmimxrt1020_flexspi_nor_config.h        | 10 ++++-----
 .../evkbimxrt1050_flexspi_nor_config.h        | 10 ++++-----
 .../evkmimxrt1060_flexspi_nor_config.h        | 10 ++++-----
 .../evkmimxrt1064_flexspi_nor_config.h        | 10 ++++-----
 .../teensy_40/teensy40_flexspi_nor_config.h   | 10 ++++-----
 .../teensy_41/teensy41_flexspi_nor_config.h   | 10 ++++-----
 hw/bsp/imxrt/family.mk                        |  2 +-
 hw/bsp/lpc54/family.c                         |  4 ++--
 hw/bsp/lpc55/family.c                         |  4 ++--
 hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld    |  2 +-
 hw/bsp/rp2040/family.c                        |  2 +-
 .../stm32f070rbnucleo/stm32F070rbtx_flash.ld  |  2 +-
 .../stm32f072disco/STM32F072RBTx_FLASH.ld     |  2 +-
 .../stm32f103_bluepill/STM32F103X8_FLASH.ld   |  2 +-
 .../stm32f103_mini_2/STM32F103XC_FLASH.ld     |  2 +-
 hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld |  2 +-
 hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld  |  2 +-
 .../feather_stm32f405/STM32F405RGTx_FLASH.ld  |  2 +-
 .../boards/pyboardv11/STM32F405RGTx_FLASH.ld  |  2 +-
 .../stm32f401blackpill/STM32F401VCTx_FLASH.ld |  2 +-
 .../stm32f4/boards/stm32f401blackpill/board.h |  2 +-
 .../stm32f407disco/STM32F407VGTx_FLASH.ld     |  2 +-
 .../stm32f411blackpill/STM32F411CEUx_FLASH.ld |  2 +-
 .../stm32f4/boards/stm32f411blackpill/board.h |  2 +-
 .../stm32f411disco/STM32F411VETx_FLASH.ld     |  2 +-
 .../stm32f412disco/STM32F412ZGTx_FLASH.ld     |  2 +-
 .../stm32f412nucleo/STM32F412ZGTx_FLASH.ld    |  2 +-
 .../boards/stlinkv3mini/STM32F723xE_FLASH.ld  |  2 +-
 .../stm32f723disco/STM32F723xE_FLASH.ld       |  2 +-
 .../stm32f746disco/STM32F746ZGTx_FLASH.ld     |  2 +-
 .../stm32f746nucleo/STM32F746ZGTx_FLASH.ld    |  2 +-
 .../stm32f767nucleo/STM32F767ZITx_FLASH.ld    |  2 +-
 .../stm32f769disco/STM32F769ZITx_FLASH.ld     |  2 +-
 hw/bsp/stm32g4/boards/stm32g474nucleo/board.h |  4 ++--
 .../boards/stm32h743eval/stm32h743xx_flash.ld |  2 +-
 .../stm32h743nucleo/stm32h743xx_flash.ld      |  2 +-
 .../STM32H743IITX_FLASH.ld                    |  2 +-
 .../boards/waveshare_openh743i/board.h        |  2 +-
 .../stm32l052dap52/STM32L052K8Ux_FLASH.ld     |  2 +-
 hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld |  2 +-
 .../stm32l476disco/STM32L476VGTx_FLASH.ld     |  2 +-
 .../stm32l4r5nucleo/STM32L4RXxI_FLASH.ld      |  2 +-
 hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h |  4 ++--
 hw/bsp/tm4c123/family.c                       |  2 +-
 lib/SEGGER_RTT/RTT/SEGGER_RTT.c               |  2 +-
 lib/networking/dnserver.c                     |  8 +++----
 lib/networking/ndis.h                         |  2 +-
 lib/networking/rndis_reports.c                |  2 +-
 src/class/cdc/cdc.h                           |  2 +-
 src/class/cdc/cdc_rndis_host.c                |  2 +-
 src/class/hid/hid_host.h                      |  2 +-
 src/class/msc/msc_host.c                      |  4 ++--
 src/class/msc/msc_host.h                      |  2 +-
 src/class/net/ecm_rndis_device.c              |  2 +-
 src/class/usbtmc/usbtmc.h                     |  2 +-
 src/class/usbtmc/usbtmc_device.h              |  2 +-
 src/common/tusb_fifo.c                        |  8 +++----
 src/common/tusb_fifo.h                        |  4 ++--
 src/device/usbd.h                             |  2 +-
 src/host/usbh.c                               |  4 ++--
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c      |  6 ++---
 src/portable/ehci/ehci.c                      |  4 ++--
 src/portable/ehci/ehci.h                      | 10 ++++-----
 src/portable/espressif/esp32sx/dcd_esp32sx.c  |  2 +-
 .../microchip/pic32mz/usbhs_registers.h       |  6 ++---
 src/portable/microchip/samx7x/dcd_samx7x.c    |  6 ++---
 src/portable/nuvoton/nuc505/dcd_nuc505.c      |  2 +-
 src/portable/ohci/ohci.c                      |  2 +-
 src/portable/ohci/ohci.h                      |  2 +-
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |  2 +-
 src/portable/sunxi/dcd_sunxi_musb.c           |  2 +-
 src/portable/sunxi/musb_def.h                 |  2 +-
 src/portable/synopsys/dwc2/dcd_dwc2.c         |  2 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h       |  2 +-
 90 files changed, 160 insertions(+), 160 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index 2958d3b12..8c39b95e1 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -64,7 +64,7 @@ body:
       placeholder: |
         Attach your debug log txt file here, where the issue occurred, best with comments to explain the actual events.
         
-        Note1: Please DO NOT paste your lengthy log contents here since it hurts the readibility.
+        Note1: Please DO NOT paste your lengthy log contents here since it hurts the readability.
         Note2: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. 
         More information can be found at [example's readme](https://github.com/hathach/tinyusb/blob/master/docs/getting_started.md)
     validations:
diff --git a/docs/contributing/porting.rst b/docs/contributing/porting.rst
index 7e9e462f0..710af51c3 100644
--- a/docs/contributing/porting.rst
+++ b/docs/contributing/porting.rst
@@ -195,7 +195,7 @@ Others (like the nRF52) may need each USB packet queued individually. To make th
 some state for yourself and queue up an intermediate USB packet from the interrupt handler.
 
 Once the transaction is going, the interrupt handler will notify TinyUSB of transfer completion.
-During transmission, the IN data buffer is guarenteed to remain unchanged in memory until the ``dcd_xfer_complete`` function is called.
+During transmission, the IN data buffer is guaranteed to remain unchanged in memory until the ``dcd_xfer_complete`` function is called.
 
 The dcd_edpt_xfer function must never add zero-length-packets (ZLP) on its own to a transfer. If a ZLP is required,
 then it must be explicitly sent by the stack calling dcd_edpt_xfer(), by calling dcd_edpt_xfer() a second time with len=0.
@@ -238,4 +238,4 @@ Use `WireShark <https://www.wireshark.org/>`_ or `a Beagle <https://www.totalpha
 
 * If the host sends a SETUP packet and its not ACKed then your USB peripheral probably isn't started correctly.
 * If the peripheral is started correctly but it still didn't work, then verify your usb clock is correct. (You did output a PWM based on it right? ;-) )
-* If the SETUP packet is ACKed but nothing is sent back then you interrupt handler isn't queueing the setup packet correctly. (Also, if you are using your own code instead of an example ``tud_task`` may not be called.) If thats OK, the ``dcd_xfer_complete`` may not be setting up the next transaction correctly.
+* If the SETUP packet is ACKed but nothing is sent back then you interrupt handler isn't queueing the setup packet correctly. (Also, if you are using your own code instead of an example ``tud_task`` may not be called.) If that's OK, the ``dcd_xfer_complete`` may not be setting up the next transaction correctly.
diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index da29e04fb..bbd182866 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -78,14 +78,14 @@ Controller Driver (DCD & HCD)
 - [MUSB] Add new DCD and HCD for Mentor musb with TI MSP432E4
 - [F1C100s] Add new DCD for Allwinner F1C100s family
 - [PIC32MZ] Add new DCD for PIC32MZ
-- [nRF] Fix/Enhance varous race condtion with: EASY DMA, request HFXO, EPOUT
+- [nRF] Fix/Enhance various race condition with: EASY DMA, request HFXO, EPOUT
 - [ChipIdea] rename Transdimension to more popular ChipIdea Highspeed, 
 - [RP2040] various update/fix for hcd/dcd
 - [FT9XX] new DCD port for Bridgetek FT90x and FT93x devices
 - [DA1469X] Fix resume
 - [OHCI] Fix device array out of bound
 
-Note: legacy drivers such as st/synopsys, nxp/transdimension are still present in this release but won't recieve more update and could be removed in the future.
+Note: legacy drivers such as st/synopsys, nxp/transdimension are still present in this release but won't receive more update and could be removed in the future.
 
 Device Stack
 ------------
@@ -166,7 +166,7 @@ RP2040
 ^^^^^^
 
 - Add RP2040 suspend & resume support
-- Implement double buffer for both host and device (#891). Howver device EPOUT is still single bufferred due to techinical issue with short packet 
+- Implement double buffer for both host and device (#891). However device EPOUT is still single buffered due to techinical issue with short packet 
 
 Device Stack
 ------------
@@ -175,7 +175,7 @@ USBD
 ^^^^
 
 - Better support big endian mcu
-- Add tuh_inited() and tud_inited(), will separte tusb_init/inited() to tud/tuh init/inited
+- Add tuh_inited() and tud_inited(), will separate tusb_init/inited() to tud/tuh init/inited
 - Add dcd_attr.h for defining common controller attribute such as max endpoints
 
 Bluetooth
@@ -220,8 +220,8 @@ Host Controller Driver (HCD)
 RP2040
 ^^^^^^
 
-- Implement double bufferred to fix E4 errata and boost performance
-- Lots of rp2040 update and enhancment
+- Implement double buffered to fix E4 errata and boost performance
+- Lots of rp2040 update and enhancement
 
 Host Stack
 ----------
@@ -229,7 +229,7 @@ Host Stack
 - Major update and rework most of host stack, still needs more improvement
 - Lots of improvement and update in parsing configuration and control
 - Rework and major update to HID driver. Will default to enable boot interface if available
-- Sepearate CFG_TUH_DEVICE_MAX and CFG_TUH_HUB for better management and reduce SRAM usage
+- Separate CFG_TUH_DEVICE_MAX and CFG_TUH_HUB for better management and reduce SRAM usage
 
 0.10.1 (2021-06-03)
 ===================
@@ -306,12 +306,12 @@ MIDI
 Host Controller Driver (HCD)
 ----------------------------
 
-- No noticable changes
+- No noticeable changes
 
 USB Host Driver (USBH)
 ----------------------
 
-- No noticable changes
+- No noticeable changes
 
 Host Class Driver
 -----------------
@@ -384,7 +384,7 @@ HID
 MIDI
 
 - Fix dropping MIDI sysex message when fifo is full
-- Fix typo in tud_midi_write24(), make example less ambigous for cable and channel
+- Fix typo in tud_midi_write24(), make example less ambiguous for cable and channel
 - Fix incorrect endpoint descriptor length, MIDI v1 use Audio v1 which has 9-byte endpoint descriptor (instead of 7)
 
 Host Stack
@@ -699,7 +699,7 @@ Changed
 - Generalized dcd_stm32f4.c to dcd_synopsys.c
 - Changed cdc_msc_hid to cdc_msc (drop hid) due to limited endpoints number of some MCUs
 - Improved DCD SAMD stability, fix missing setup packet occasionally
-- Improved usbd/usbd_control with proper hanlding of zero-length packet (ZLP)
+- Improved usbd/usbd_control with proper handling of zero-length packet (ZLP)
 - Improved STM32 DCD FSDev
 - Improved STM32 DCD Synopsys
 - Migrated CI from Travis to Github Action
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index c3666763b..c83299e59 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -113,7 +113,7 @@ void cdc_task(void)
     // connected and there are data available
     if ( tud_cdc_available() )
     {
-      // read datas
+      // read data
       char buf[64];
       uint32_t count = tud_cdc_read(buf, sizeof(buf));
       (void) count;
diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 639dde99a..cbd75efd6 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 3.5)
 
 # TOP is absolute path to root directory of TinyUSB git repo
-# needed for esp32sx build. TOOD could be removed later on
+# needed for esp32sx build. TODO could be removed later on
 set(TOP "../../..")
 get_filename_component(TOP "${TOP}" REALPATH)
 
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index 55b380353..bd9a91c27 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -31,7 +31,7 @@
  *
  * $ dfu-util -e
  *
- * This will send DETTACH command to put device into bootloader. Since this example
+ * This will send DETACH command to put device into bootloader. Since this example
  * is minimal, it doesn't actually go into DFU mode but rather change the LED blinking
  * pattern to fast rate as indicator.
  */
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 71afa3f46..ef072019c 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -157,11 +157,11 @@ void hid_task(void)
       {
         uint8_t const report_id   = 0;
         uint8_t const button_mask = 0;
-        uint8_t const veritical   = 0;
+        uint8_t const vertical    = 0;
         uint8_t const horizontal  = 0;
         int8_t  const delta       = 5;
 
-        tud_hid_n_mouse_report(ITF_NUM_MOUSE, report_id, button_mask, delta, delta, veritical, horizontal);
+        tud_hid_n_mouse_report(ITF_NUM_MOUSE, report_id, button_mask, delta, delta, vertical, horizontal);
       }
     }
   }
@@ -175,7 +175,7 @@ void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol)
   (void) protocol;
 
   // nothing to do since we use the same compatible boot report for both Boot and Report mode.
-  // TOOD set a indicator for user
+  // TODO set a indicator for user
 }
 
 // Invoked when sent REPORT successfully to host
diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index 11437c2b4..ed53c502d 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -247,7 +247,7 @@ static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t c
     // Composite report, 1st byte is report ID, data starts from 2nd byte
     uint8_t const rpt_id = report[0];
 
-    // Find report id in the arrray
+    // Find report id in the array
     for(uint8_t i=0; i<rpt_count; i++)
     {
       if (rpt_id == rpt_info_arr[i].report_id )
diff --git a/hw/bsp/ansi_escape.h b/hw/bsp/ansi_escape.h
index 35342cfe5..6e62ee20a 100644
--- a/hw/bsp/ansi_escape.h
+++ b/hw/bsp/ansi_escape.h
@@ -25,7 +25,7 @@
  */
 
 /** \ingroup group_board
- *  \defgroup group_ansi_esc ANSI Esacpe Code
+ *  \defgroup group_ansi_esc ANSI Escape Code
  *  @{ */
 
 #ifndef _TUSB_ANSI_ESC_CODE_H_
diff --git a/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c b/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c
index 025d3c590..fd1746cad 100644
--- a/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c
+++ b/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c
@@ -50,7 +50,7 @@ typedef struct {
 } ws2812_t;
 
 /**
- * @brief Conver RGB data to RMT format.
+ * @brief Convert RGB data to RMT format.
  *
  * @note For WS2812, R,G,B each contains 256 different choices (i.e. uint8_t)
  *
diff --git a/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c b/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
index 025d3c590..fd1746cad 100644
--- a/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
+++ b/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
@@ -50,7 +50,7 @@ typedef struct {
 } ws2812_t;
 
 /**
- * @brief Conver RGB data to RMT format.
+ * @brief Convert RGB data to RMT format.
  *
  * @note For WS2812, R,G,B each contains 256 different choices (i.e. uint8_t)
  *
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index c5311b63f..601cd54f5 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -123,12 +123,12 @@ if (NOT TARGET _family_support_marker)
 
     # configure an executable target to link to tinyusb in device mode, and add the board implementation
     function(family_configure_device_example TARGET)
-        # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
+        # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
     endfunction()
 
     # configure an executable target to link to tinyusb in host mode, and add the board implementation
     function(family_configure_host_example TARGET)
-        # default implentation is empty, the function should be redefined in the FAMILY/family.cmake
+        # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
     endfunction()
 
     include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c
index c20732302..5427c8dd0 100644
--- a/hw/bsp/gd32vf103/family.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -120,7 +120,7 @@ void gd32vf103_reset(void) {
   /* The MTIMER unit of the GD32VF103 doesn't have the MSFRST
    * register to generate a software reset request.
    * BUT instead two undocumented registers in the debug peripheral
-   * that allow issueing a software reset.
+   * that allow issuing a software reset.
    * https://github.com/esmil/gd32vf103inator/blob/master/include/gd32vf103/dbg.h
    */
   DBG_KEY = DBG_KEY_UNLOCK;
diff --git a/hw/bsp/gd32vf103/system_gd32vf103.c b/hw/bsp/gd32vf103/system_gd32vf103.c
index 29518a54a..c2001a980 100644
--- a/hw/bsp/gd32vf103/system_gd32vf103.c
+++ b/hw/bsp/gd32vf103/system_gd32vf103.c
@@ -574,7 +574,7 @@ void ECLIC_Init(void)
  * \param [in]  IRQn        NMI interrupt handler address
  * \param [in]  shv         \ref ECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and \ref ECLIC_VECTOR_INTERRUPT is vector mode
  * \param [in]  trig_mode   see \ref ECLIC_TRIGGER_Type
- * \param [in]  lvl         interupt level
+ * \param [in]  lvl         interrupt level
  * \param [in]  priority    interrupt priority
  * \param [in]  handler     interrupt handler, if NULL, handler will not be installed
  * \return       -1 means invalid input parameter. 0 means successful.
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h
index 4be2760be..bb5a64448 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -123,7 +123,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -184,7 +184,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -252,7 +252,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h
index 94af5a115..f1415aeec 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h
index f5e1aca5c..ad79d5002 100644
--- a/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h
index fe40e7ed7..7a14360e4 100644
--- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.h
@@ -19,7 +19,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -27,7 +27,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -125,7 +125,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -186,7 +186,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -254,7 +254,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h
index 28d7db57d..b4ef4ad4f 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h
index efdfe583f..995e88cb9 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h b/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h
index 56068ec6a..d24d4f10a 100644
--- a/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h
index 56068ec6a..d24d4f10a 100644
--- a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ 0
 #define CMD_INDEX_READSTATUS 1
 #define CMD_INDEX_WRITEENABLE 2
@@ -124,7 +124,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -185,7 +185,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -253,7 +253,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 846ecd255..0642e52e3 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -30,7 +30,7 @@ MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx_flexspi_nor.ld
 
-# TODO for net_lwip_webserver exmaple, but may not needed !! 
+# TODO for net_lwip_webserver example, but may not needed !! 
 LDFLAGS += \
 	-Wl,--defsym,__stack_size__=0x800 \
 
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index 9bb341e73..621788948 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -170,7 +170,7 @@ void board_init(void)
     CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
     CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
 
-    /*According to reference mannual, device mode setting has to be set by access usb host register */
+    /*According to reference manual, device mode setting has to be set by access usb host register */
     CLOCK_EnableClock(kCLOCK_Usbhsl0); /* enable usb0 host clock */
     USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
     CLOCK_DisableClock(kCLOCK_Usbhsl0); /* disable usb0 host clock */
@@ -182,7 +182,7 @@ void board_init(void)
     // Port1 is High Speed
     POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
 
-    /*According to reference mannual, device mode setting has to be set by access usb host register */
+    /*According to reference manual, device mode setting has to be set by access usb host register */
     CLOCK_EnableClock(kCLOCK_Usbh1); /* enable usb1 host clock */
     USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
     CLOCK_DisableClock(kCLOCK_Usbh1); /* enable usb1 host clock */
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index e7aed5759..5b6c56dd3 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -192,7 +192,7 @@ void board_init(void)
   CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
   CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
 
-  /*According to reference mannual, device mode setting has to be set by access usb host register */
+  /*According to reference manual, device mode setting has to be set by access usb host register */
   CLOCK_EnableClock(kCLOCK_Usbhsl0);  // enable usb0 host clock
   USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
   CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
@@ -213,7 +213,7 @@ void board_init(void)
   RESET_PeripheralReset(kUSB1_RST_SHIFT_RSTn);
   RESET_PeripheralReset(kUSB1RAM_RST_SHIFT_RSTn);
 
-  /* According to reference mannual, device mode setting has to be set by access usb host register */
+  /* According to reference manual, device mode setting has to be set by access usb host register */
   CLOCK_EnableClock(kCLOCK_Usbh1); // enable usb0 host clock
 
   USBHSH->PORTMODE = USBHSH_PORTMODE_SW_PDCOM_MASK; // Put PHY powerdown under software control
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
index d96d6e43d..0b45ee7bd 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
@@ -126,7 +126,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 26008168d..f7ee56990 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -226,6 +226,6 @@ int board_getchar(void)
 
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
-// rp2040 implementation will install approriate handler when initializing
+// rp2040 implementation will install appropriate handler when initializing
 // tinyusb. There is no need to forward IRQ from application
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
index 59e18f375..4a6491510 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
@@ -165,7 +165,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
index 8d31f6a00..f0879e929 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
index ca1804905..c434ca038 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
index da40d1eb2..da637d1b0 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld b/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
index 29e387f28..5010435ae 100644
--- a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld b/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
index ca9046d29..7f46c71b2 100644
--- a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
+++ b/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
@@ -150,7 +150,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld b/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
index 57ef61e26..9eb53bcc0 100644
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
@@ -150,7 +150,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld b/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
index 57ef61e26..9eb53bcc0 100644
--- a/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
@@ -150,7 +150,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
index f51f1ab41..2bc5f6c14 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
index 0f820512c..e1fef7277 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
@@ -93,7 +93,7 @@ static inline void board_clock_init(void)
 
 static inline void board_vbus_sense_init(void)
 {
-  // Blackpill doens't use VBUS sense (B device) explicitly disable it
+  // Blackpill doesn't use VBUS sense (B device) explicitly disable it
   USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
   USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
   USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
index c41602720..aac6577ea 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
@@ -150,7 +150,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
index efea1e067..56dcea605 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
index 0f820512c..e1fef7277 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
@@ -93,7 +93,7 @@ static inline void board_clock_init(void)
 
 static inline void board_vbus_sense_init(void)
 {
-  // Blackpill doens't use VBUS sense (B device) explicitly disable it
+  // Blackpill doesn't use VBUS sense (B device) explicitly disable it
   USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
   USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
   USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
index 3a0ce526f..4477229ea 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
index b00b5dbe0..2372cc1d9 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
index b00b5dbe0..2372cc1d9 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld b/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld
index 8645ce5c5..f4be85703 100644
--- a/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/STM32F723xE_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld
index 8645ce5c5..f4be85703 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/STM32F723xE_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld
index 045ec76f9..eeb0e29f3 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/STM32F746ZGTx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
index b434a01b7..e1e60bc78 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
index 0b6d5a494..3785f9cbf 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld
index 378ed80dd..520a75539 100644
--- a/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f769disco/STM32F769ZITx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
index eab0bd5f0..aa2bf20bb 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h
@@ -66,7 +66,7 @@ static inline void board_clock_init(void)
   // Configure the main internal regulator output voltage
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
 
-  // Initializes the CPU, AHB and APB busses clocks
+  // Initializes the CPU, AHB and APB buses clocks
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState       = RCC_HSE_ON;
   RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
@@ -79,7 +79,7 @@ static inline void board_clock_init(void)
   RCC_OscInitStruct.PLL.PLLR       = RCC_PLLR_DIV2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
-  // Initializes the CPU, AHB and APB busses clocks
+  // Initializes the CPU, AHB and APB buses clocks
   RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
index 59b9ff4df..7ee40671c 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
@@ -134,7 +134,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
index 59b9ff4df..7ee40671c 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
@@ -134,7 +134,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld b/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
index 73d2dedb2..e99bb977b 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
@@ -138,7 +138,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
index 09442c233..2b072e07c 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
@@ -186,7 +186,7 @@ static inline void timer_board_delay(TIM_HandleTypeDef* tim_hdl, uint32_t ms)
 
 static inline void board_stm32h7_post_init(void)
 {
-  // walkaround for reseting the ULPI PHY using Timer since systick is not
+  // walkaround for resetting the ULPI PHY using Timer since systick is not
   // available when RTOS is used.
 
   // Init timer
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
index 1bc16cc7b..dfefe59f1 100644
--- a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld b/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
index 787418e09..79427d80b 100644
--- a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
+++ b/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
index 98f468ac0..d6865f49d 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
@@ -144,7 +144,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
index f93a16041..f77c72d1b 100644
--- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
@@ -130,7 +130,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h
index f42c7d6dd..ea975df03 100644
--- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h
+++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h
@@ -59,7 +59,7 @@ static inline void board_clock_init(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  // Initializes the CPU, AHB and APB busses clocks
+  // Initializes the CPU, AHB and APB buses clocks
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState       = RCC_HSE_ON;
   RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
@@ -72,7 +72,7 @@ static inline void board_clock_init(void)
   RCC_OscInitStruct.PLL.PLLR       = RCC_PLLR_DIV3;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
-  // Initializes the CPU, AHB and APB busses clocks
+  // Initializes the CPU, AHB and APB buses clocks
   RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c
index b0947d6c4..87b94289b 100644
--- a/hw/bsp/tm4c123/family.c
+++ b/hw/bsp/tm4c123/family.c
@@ -39,7 +39,7 @@ static void board_uart_init (void)
   UART0->LCRH = (0x3 << 5);                    // 8-bit, no parity, 1 stop bit
   UART0->CC = 0x0;                             // Configure the UART clock source as system clock
 
-  UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Recieve Enable
+  UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Receive Enable
 }
 
 static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirmsk)
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
index 3ad2b1a12..a7ae013dd 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
@@ -1404,7 +1404,7 @@ int SEGGER_RTT_GetKey(void) {
 *       SEGGER_RTT_WaitKey
 *
 *  Function description
-*    Waits until at least one character is avaible in the SEGGER RTT buffer.
+*    Waits until at least one character is available in the SEGGER RTT buffer.
 *    Once a character is available, it is read and this function returns.
 *
 *  Return value
diff --git a/lib/networking/dnserver.c b/lib/networking/dnserver.c
index e4e7c3492..539cc2cea 100644
--- a/lib/networking/dnserver.c
+++ b/lib/networking/dnserver.c
@@ -93,11 +93,11 @@ static uint16_t get_uint16(const uint8_t *pnt)
 static int parse_next_query(void *data, int size, dns_query_t *query)
 {
 	int len;
-	int lables;
+	int labels;
 	uint8_t *ptr;
 
 	len = 0;
-	lables = 0;
+	labels = 0;
 	ptr = (uint8_t *)data;
 
 	while (true)
@@ -107,7 +107,7 @@ static int parse_next_query(void *data, int size, dns_query_t *query)
 		lable_len = *ptr++;
 		size--;
 		if (lable_len == 0) break;
-		if (lables > 0)
+		if (labels > 0)
 		{
 			if (len == DNS_MAX_HOST_NAME_LEN) return -2;
 			query->name[len++] = '.';
@@ -118,7 +118,7 @@ static int parse_next_query(void *data, int size, dns_query_t *query)
 		len += lable_len;
 		ptr += lable_len;
 		size -= lable_len;
-		lables++;
+		labels++;
 	}
 
 	if (size < 4) return -1;
diff --git a/lib/networking/ndis.h b/lib/networking/ndis.h
index 1c737574c..06258e6bb 100644
--- a/lib/networking/ndis.h
+++ b/lib/networking/ndis.h
@@ -22,7 +22,7 @@
  * ntddndis.h modified by Benedikt Spranger <b.spranger@pengutronix.de>
  * 
  * Thanks to the cygwin development team, 
- * espacially to Casper S. Hornstrup <chorns@users.sourceforge.net>
+ * especially to Casper S. Hornstrup <chorns@users.sourceforge.net>
  * 
  * THIS SOFTWARE IS NOT COPYRIGHTED
  *
diff --git a/lib/networking/rndis_reports.c b/lib/networking/rndis_reports.c
index ee611c883..d129466c8 100644
--- a/lib/networking/rndis_reports.c
+++ b/lib/networking/rndis_reports.c
@@ -220,7 +220,7 @@ static void rndis_handle_set_msg(void)
     case OID_802_3_MULTICAST_LIST:
       break;
 
-    /* Power Managment: fails for now */
+    /* Power Management: fails for now */
     case OID_PNP_ADD_WAKE_UP_PATTERN:
     case OID_PNP_REMOVE_WAKE_UP_PATTERN:
     case OID_PNP_ENABLE_WAKE_UP:
diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index e345139ea..c428af865 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -193,7 +193,7 @@ typedef enum
 }cdc_management_request_t;
 
 //--------------------------------------------------------------------+
-// Management Elemenent Notification (Notification Endpoint)
+// Management Element Notification (Notification Endpoint)
 //--------------------------------------------------------------------+
 
 /// 6.3 Notification Codes
diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c
index 8f28f51ac..44de85b45 100644
--- a/src/class/cdc/cdc_rndis_host.c
+++ b/src/class/cdc/cdc_rndis_host.c
@@ -117,7 +117,7 @@ void rndish_init(void)
 
   //------------- Task creation -------------//
 
-  //------------- semaphore creation for notificaiton pipe -------------//
+  //------------- semaphore creation for notification pipe -------------//
   for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
   {
     rndish_data[i].sem_notification_hdl = osal_semaphore_create( OSAL_SEM_REF(rndish_data[i].semaphore_notification) );
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index fe09b03b2..ffc601d77 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -89,7 +89,7 @@ uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance);
 bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol);
 
 // Set Report using control endpoint
-// report_type is either Intput, Output or Feature, (value from hid_report_type_t)
+// report_type is either Input, Output or Feature, (value from hid_report_type_t)
 bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, void* report, uint16_t len);
 
 //--------------------------------------------------------------------+
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 9e88ebc30..32f75a84b 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -200,7 +200,7 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_
   return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb, arg);
 }
 
-bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
+bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
 {
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
@@ -217,7 +217,7 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_ms
 
   memcpy(cbw.command, &cmd_request_sense, cbw.cmd_len);
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, resposne, complete_cb, arg);
+  return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
 bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index 416e4318b..5134b63c2 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -85,7 +85,7 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_
 
 // Perform SCSI Request Sense 10 command
 // Complete callback is invoked when SCSI op is complete.
-bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *resposne, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
+bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Read 10 command. Read n blocks starting from LBA to buffer
 // Complete callback is invoked when SCSI op is complete.
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index 5f316762f..c7428bcda 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -51,7 +51,7 @@ typedef struct
 
   bool ecm_mode;
 
-  // Endpoint descriptor use to open/close when receving SetInterface
+  // Endpoint descriptor use to open/close when receiving SetInterface
   // TODO since configuration descriptor may not be long-lived memory, we should
   // keep a copy of endpoint attribute instead
   uint8_t const * ecm_desc_epdata;
diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h
index e7016ae24..fd52d766e 100644
--- a/src/class/usbtmc/usbtmc.h
+++ b/src/class/usbtmc/usbtmc.h
@@ -158,7 +158,7 @@ enum {
   USBTMC_BULK_IN_ERR_DATA_TOO_SHORT = 4u,
   USBTMC_BULK_IN_ERR_DATA_TOO_LONG = 5u,
 };
-// bult-in halt errors
+// built-in halt errors
 enum {
   USBTMC_BULK_IN_ERR = 1u, ///< receives a USBTMC command message that expects a response while a
                            /// Bulk-IN transfer is in progress
diff --git a/src/class/usbtmc/usbtmc_device.h b/src/class/usbtmc/usbtmc_device.h
index 144b3315d..c1298ddb8 100644
--- a/src/class/usbtmc/usbtmc_device.h
+++ b/src/class/usbtmc/usbtmc_device.h
@@ -36,7 +36,7 @@
 #endif
 
 /***********************************************
- *  Functions to be implemeted by the class implementation
+ *  Functions to be implemented by the class implementation
  */
 
 // In order to proceed, app must call call tud_usbtmc_start_bus_read(rhport) during or soon after:
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 895b9208b..b857c6444 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -28,7 +28,7 @@
 #include "osal/osal.h"
 #include "tusb_fifo.h"
 
-// Supress IAR warning
+// Suppress IAR warning
 // Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement
 #if defined(__ICCARM__)
 #pragma diag_suppress = Pa082
@@ -98,7 +98,7 @@ static inline uint16_t _ff_mod(uint16_t idx, uint16_t depth)
 }
 
 // Intended to be used to read from hardware USB FIFO in e.g. STM32 where all data is read from a constant address
-// Code adapted from dcd_synopsis.c
+// Code adapted from dcd_synopsys.c
 // TODO generalize with configurable 1 byte or 4 byte each read
 static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t len)
 {
@@ -857,7 +857,7 @@ bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable)
     As long as the DMA is the only process writing into the FIFO this is safe
     to use.
 
-    USE WITH CARE - WE DO NOT CONDUCT SAFTY CHECKS HERE!
+    USE WITH CARE - WE DO NOT CONDUCT SAFETY CHECKS HERE!
 
     @param[in]  f
                 Pointer to the FIFO buffer to manipulate
@@ -878,7 +878,7 @@ void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n)
     FIFO. As long as the DMA is the only process reading from the FIFO this is
     safe to use.
 
-    USE WITH CARE - WE DO NOT CONDUCT SAFTY CHECKS HERE!
+    USE WITH CARE - WE DO NOT CONDUCT SAFETY CHECKS HERE!
 
     @param[in]  f
                 Pointer to the FIFO buffer to manipulate
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 18db289a1..e64ab4b6d 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -32,7 +32,7 @@
 extern "C" {
 #endif
 
-// Due to the use of unmasked pointers, this FIFO does not suffer from loosing
+// Due to the use of unmasked pointers, this FIFO does not suffer from losing
 // one item slice. Furthermore, write and read operations are completely
 // decoupled as write and read functions do not modify a common state. Henceforth,
 // writing or reading from the FIFO within an ISR is safe as long as no other
@@ -133,7 +133,7 @@ uint16_t tu_fifo_depth(tu_fifo_t* f)
 }
 
 // Pointer modifications intended to be used in combinations with DMAs.
-// USE WITH CARE - NO SAFTY CHECKS CONDUCTED HERE! NOT MUTEX PROTECTED!
+// USE WITH CARE - NO SAFETY CHECKS CONDUCTED HERE! NOT MUTEX PROTECTED!
 void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n);
 void tu_fifo_advance_read_pointer (tu_fifo_t *f, uint16_t n);
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 731c57aad..dc5b35ffd 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -648,7 +648,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 #define TUD_DFU_DESC_LEN(_alt_count)    (9 + (_alt_count) * 9)
 
 // Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size
-// Note: Alternate count must be numberic or macro, string index is increased by one for each Alt interface
+// Note: Alternate count must be numeric or macro, string index is increased by one for each Alt interface
 #define TUD_DFU_DESCRIPTOR(_itfnum, _alt_count, _stridx, _attr, _timeout, _xfer_size) \
   TU_XSTRCAT(_TUD_DFU_ALT_,_alt_count)(_itfnum, 0, _stridx), \
   /* Function */ \
diff --git a/src/host/usbh.c b/src/host/usbh.c
index d97b160c9..9065e5241 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1275,7 +1275,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
         // connected directly to roothub
         hcd_port_reset( _dev0.rhport );
         osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
-                                      // sof of controller may not running while reseting
+                                      // sof of controller may not running while resetting
         hcd_port_reset_end(_dev0.rhport);
         // TODO: fall through to SET ADDRESS, refactor later
       }
@@ -1395,7 +1395,7 @@ static bool enum_new_device(hcd_event_t* event)
     // wait until device is stable TODO non blocking
     hcd_port_reset(_dev0.rhport);
     osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
-                                  // sof of controller may not running while reseting
+                                  // sof of controller may not running while resetting
     hcd_port_reset_end( _dev0.rhport);
 
     // device unplugged while delaying
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 2445593fe..261a3c9c2 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -587,7 +587,7 @@ void dcd_remote_wakeup(uint8_t rhport)
 
   SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
 
-  // Atleast 2 ms of delay needed for RESUME Data K state.
+  // At least 2 ms of delay needed for RESUME Data K state.
   delayms(2); 
 
   SYS->MSC0CFG &= ~MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
@@ -720,7 +720,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     else
       total_ram = USBD_RAMTOTAL_OUT;
     // Work out how much has been allocated to existing endpoints.
-    // The total RAM allocated shoudl alsyes be a positive number as this
+    // The total RAM allocated should always be a positive number as this
     // algorithm should not let it go below zero.
     for (int i = 1; i < USBD_MAX_ENDPOINT_COUNT; i++)
     {
@@ -976,7 +976,7 @@ void dcd_int_handler(uint8_t rhport)
           USBD_EP_SR_REG(USBD_EP_0) = MASK_USBD_EP0SR_STALL;
         }
 
-        // Host has sent a SETUP packet. Recieve this into the setup packet store.
+        // Host has sent a SETUP packet. Receive this into the setup packet store.
         _ft90x_dusb_out(USBD_EP_0, (uint8_t *)_ft90x_setup_packet, sizeof(USB_device_request));
         
         // Send the packet to tinyusb.
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 76ba2a921..80f616478 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -199,7 +199,7 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
     #pragma GCC diagnostic pop
     if ( qhd->dev_addr == dev_addr )
     {
-      // TODO deactive all TD, wait for QHD to inactive before removal
+      // TODO deactivate all TD, wait for QHD to inactive before removal
       prev->address = qhd->next.address;
 
       // EHCI 4.8.2 link the removed qhd to async head (which always reachable by Host Controller)
@@ -839,7 +839,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
     if (TUSB_SPEED_HIGH == p_qhd->ep_speed)
     {
       TU_ASSERT( interval <= 16, );
-      if ( interval < 4) // sub milisecond interval
+      if ( interval < 4) // sub millisecond interval
       {
         p_qhd->interval_ms = 0;
         p_qhd->int_smask   = (interval == 1) ? TU_BIN8(11111111) :
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index ff9ae12e7..36f8649be 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -114,7 +114,7 @@ typedef struct
 	volatile uint32_t current_page         : 3  ; ///< Index into the qTD buffer pointer list
 	uint32_t int_on_complete               : 1  ; ///< Interrupt on complete
 	volatile uint32_t total_bytes          : 15 ; ///< Transfer bytes, decreased during transaction
-	volatile uint32_t data_toggle          : 1  ; ///< Data Toogle bit
+	volatile uint32_t data_toggle          : 1  ; ///< Data Toggle bit
 
 
 	/// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
@@ -160,7 +160,7 @@ typedef struct TU_ATTR_ALIGNED(32)
 	uint8_t used;
 	uint8_t removing; // removed from asyn list, waiting for async advance
 	uint8_t pid;
-	uint8_t interval_ms; // polling interval in frames (or milisecond)
+	uint8_t interval_ms; // polling interval in frames (or millisecond)
 
 	uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set
 	uint8_t reserved2[2];
@@ -225,7 +225,7 @@ typedef struct TU_ATTR_ALIGNED(32)
 	uint16_t reserved ; ///< reserved
 
 	// Word 3: siTD Transfer Status and Control
-	// Status [7:0] TODO indentical to qTD Token'status --> refractor later
+	// Status [7:0] TODO identical to qTD Token'status --> refactor later
 	volatile uint32_t                 : 1  ; // reserved
 	volatile uint32_t split_state     : 1  ;
 	volatile uint32_t missed_uframe   : 1  ;
@@ -350,8 +350,8 @@ typedef volatile struct
       uint32_t periodic_status       : 1  ; ///< Periodic schedule status
       uint32_t async_status          : 1  ; ///< Async schedule status
       uint32_t                       : 2  ;
-      uint32_t nxp_int_async         : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected andthe packet is on the asynchronous schedule.
-      uint32_t nxp_int_period        : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set andthe TD was from the periodic schedule.
+      uint32_t nxp_int_async         : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule.
+      uint32_t nxp_int_period        : 1  ; ///< NXP customized: This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule.
       uint32_t                       : 12 ;
     }status_bm;
   };
diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index 0b75af627..41240f737 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -741,7 +741,7 @@ static void handle_epin_ints(void)
 
       // XFER Timeout
       if (USB0.in_ep_reg[n].diepint & USB_D_TIMEOUT0_M) {
-        // Clear interrupt or enpoint will hang.
+        // Clear interrupt or endpoint will hang.
         USB0.in_ep_reg[n].diepint = USB_D_TIMEOUT0_M;
         // Maybe retry?
       }
diff --git a/src/portable/microchip/pic32mz/usbhs_registers.h b/src/portable/microchip/pic32mz/usbhs_registers.h
index 757e3f083..93b552322 100644
--- a/src/portable/microchip/pic32mz/usbhs_registers.h
+++ b/src/portable/microchip/pic32mz/usbhs_registers.h
@@ -21,16 +21,16 @@
 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
 *******************************************************************************/
 /*******************************************************************************
-  USBHS Peripheral Library Register Defintions 
+  USBHS Peripheral Library Register Definitions 
 
   File Name:
     usbhs_registers.h
 
   Summary:
-    USBHS PLIB Register Defintions
+    USBHS PLIB Register Definitions
 
   Description:
-    This file contains the constants and defintions which are required by the
+    This file contains the constants and definitions which are required by the
     the USBHS library.
 *******************************************************************************/
 
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 7507c0f69..24657872b 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -42,7 +42,7 @@
 #  define USE_SOF         0
 #endif
 
-// Dual bank can imporve performance, but need 2 times bigger packet buffer
+// Dual bank can improve performance, but need 2 times bigger packet buffer
 // As SAM7x has only 4KB packet buffer, use with caution !
 // Enable in FS mode as packets are smaller
 #ifndef USE_DUAL_BANK
@@ -644,7 +644,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     }
     __set_PRIMASK(irq_state);
 
-    // Here a ZLP has been recieved
+    // Here a ZLP has been received
     // and the DMA transfer must be not started.
     // It is the end of transfer
     return false;
@@ -734,7 +734,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
     }
     __set_PRIMASK(irq_state);
 
-    // Here a ZLP has been recieved
+    // Here a ZLP has been received
     // and the DMA transfer must be not started.
     // It is the end of transfer
     return false;
diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c
index 886720e33..3fa7c1ec1 100644
--- a/src/portable/nuvoton/nuc505/dcd_nuc505.c
+++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c
@@ -181,7 +181,7 @@ static void dcd_userEP_in_xfer(struct xfer_ctl_t *xfer, USBD_EP_T *ep)
     ep->EPINTEN = USBD_EPINTEN_TXPKIEN_Msk;
   }
 
-  /* provided buffers are thankfully 32-bit aligned, allowing most data to be transfered as 32-bit */
+  /* provided buffers are thankfully 32-bit aligned, allowing most data to be transferred as 32-bit */
 #if 0 // TODO support dcd_edpt_xfer_fifo API
   if (xfer->ff)
   {
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 3e523ebc2..228da6ae0 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -165,7 +165,7 @@ bool hcd_init(uint8_t rhport)
   //------------- Data Structure init -------------//
   tu_memclr(&ohci_data, sizeof(ohci_data_t));
   for(uint8_t i=0; i<32; i++)
-  { // assign all interrupt pointes to period head ed
+  { // assign all interrupt pointers to period head ed
     ohci_data.hcca.interrupt_table[i] = (uint32_t) &ohci_data.period_head_ed;
   }
 
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index 9fc954c8f..f40ae24cc 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -34,7 +34,7 @@
 //--------------------------------------------------------------------+
 // OHCI CONFIGURATION & CONSTANTS
 //--------------------------------------------------------------------+
-#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enalbed
+#define HOST_HCD_XFER_INTERRUPT // TODO interrupt is used widely, should always be enabled
 #define OHCI_PERIODIC_LIST (defined HOST_HCD_XFER_INTERRUPT || defined HOST_HCD_XFER_ISOCHRONOUS)
 
 // TODO merge OHCI with EHCI
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index c88a8a3a2..54c3c95e7 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -122,7 +122,7 @@
         (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV)) \
       )
 
-// In order to reduce the dependance on HAL, we undefine this.
+// In order to reduce the dependence on HAL, we undefine this.
 // Some definitions are copied to our private include file.
 #undef USE_HAL_DRIVER
 
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index a0be846a5..2d0e379ad 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -243,7 +243,7 @@ static void USBC_Dev_SetAddress(u8 address)
 
 static void __USBC_Dev_Tx_SendStall(void)
 {
-	//send stall, and fifo is flushed automaticly
+	//send stall, and fifo is flushed automatically
 	USBC_REG_set_bit_w(USBC_BP_TXCSR_D_SEND_STALL, USBC_REG_TXCSR(USBC0_BASE));
 }
 static u32 __USBC_Dev_Tx_IsEpStall(void)
diff --git a/src/portable/sunxi/musb_def.h b/src/portable/sunxi/musb_def.h
index 602b4f113..53da5ded2 100644
--- a/src/portable/sunxi/musb_def.h
+++ b/src/portable/sunxi/musb_def.h
@@ -93,7 +93,7 @@
 #define  USBC1_BASE                 0x01c14000
 #define  USBC2_BASE                 0x01c1E000
 
-//Some reg whithin musb
+//Some reg within musb
 #define USBPHY_CLK_REG 		0x01c200CC
 #define USBPHY_CLK_RST_BIT 0
 #define USBPHY_CLK_GAT_BIT 1
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index f5ecdfe4f..b53735a5e 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -1003,7 +1003,7 @@ static void handle_rxflvl_irq(uint8_t rhport)
 
   switch ( pktsts )
   {
-    // Global OUT NAK: do nothign
+    // Global OUT NAK: do nothing
     case GRXSTS_PKTSTS_GLOBALOUTNAK: break;
 
     case GRXSTS_PKTSTS_SETUPRX:
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index ea786362e..b63d1fcd0 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -116,7 +116,7 @@ static const dwc2_controller_t _dwc2_controller[] =
 //
 //--------------------------------------------------------------------+
 
-// SystemCoreClock is alrady included by family header
+// SystemCoreClock is already included by family header
 // extern uint32_t SystemCoreClock;
 
 TU_ATTR_ALWAYS_INLINE

From 43b255f413e08b9e567a23b24701efbdaebcb824 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 4 Dec 2022 18:51:52 +0700
Subject: [PATCH 1261/2085] more typos

---
 docs/contributing/index.rst                                  | 2 +-
 examples/device/hid_generic_inout/hid_test.py                | 4 ++--
 hw/bsp/gd32vf103/family.c                                    | 2 +-
 hw/bsp/sltb009a/sltb009a.c                                   | 2 +-
 hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld | 4 ++--
 hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld | 2 +-
 hw/bsp/stm32u5/boards/stm32u575eval/board.h                  | 4 ++--
 src/class/hid/hid_device.h                                   | 2 +-
 src/class/usbtmc/usbtmc_device.c                             | 2 +-
 src/portable/dialog/da146xx/dcd_da146xx.c                    | 2 +-
 src/portable/nordic/nrf5x/dcd_nrf5x.c                        | 2 +-
 src/portable/renesas/usba/hcd_usba.c                         | 2 +-
 src/portable/valentyusb/eptri/dcd_eptri.c                    | 2 +-
 13 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/docs/contributing/index.rst b/docs/contributing/index.rst
index c572894ad..7ff79cb32 100644
--- a/docs/contributing/index.rst
+++ b/docs/contributing/index.rst
@@ -6,7 +6,7 @@ Contributing can be highly rewarding, but it can also be frustrating at times.
 It takes time to review patches, and as this is an open source project, that
 sometimes can take a while. The reviewing process depends on the availability
 of the maintainers, who may not be always available. Please try to be
-understanding throught the process.
+understanding through the process.
 
 There a few guidelines you need to keep in mind when contributing. Please have
 a look at them as that will make the contribution process easier for all
diff --git a/examples/device/hid_generic_inout/hid_test.py b/examples/device/hid_generic_inout/hid_test.py
index 21fd3f421..5bdba9db0 100644
--- a/examples/device/hid_generic_inout/hid_test.py
+++ b/examples/device/hid_generic_inout/hid_test.py
@@ -13,8 +13,8 @@ for vid in  USB_VID:
         if dev:
             while True:
                 # Get input from console and encode to UTF8 for array of chars.
-                # hid generic inout is single report therefore by HIDAPI requirement
-                # it must be preceeded with 0x00 as dummy reportID
+                # hid generic in/out is single report therefore by HIDAPI requirement
+                # it must be preceded, with 0x00 as dummy reportID
                 str_out = b'\x00'
                 str_out += input("Send text to HID Device : ").encode('utf-8')
                 dev.write(str_out)
diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c
index 5427c8dd0..60a326d27 100644
--- a/hw/bsp/gd32vf103/family.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -112,7 +112,7 @@ void board_init(void) {
   otg_core_regs->GCCFG &= ~GCCFG_VBUSIG;
 #endif
 
-  /* Enable interrupts globaly */
+  /* Enable interrupts globally */
   __enable_irq();
 }
 
diff --git a/hw/bsp/sltb009a/sltb009a.c b/hw/bsp/sltb009a/sltb009a.c
index b929adb13..b5eb5ed5d 100644
--- a/hw/bsp/sltb009a/sltb009a.c
+++ b/hw/bsp/sltb009a/sltb009a.c
@@ -397,7 +397,7 @@ void cmu_init(void)
     CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO;
     while((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) != CMU_HFCLKSTATUS_SELECTED_HFXO);
 
-    // Calibrate HFRCO for 72MHz and enable tunning by PLL
+    // Calibrate HFRCO for 72MHz and enable tuning by PLL
     cmu_hfrco_calib((DEVINFO->HFRCOCAL16) | CMU_HFRCOCTRL_FINETUNINGEN);
 
     // Setup the PLL
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
index 935d97c87..9c327483b 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
@@ -16,7 +16,7 @@
 **
 **  Target      : STMicroelectronics STM32
 **
-**  Distribution: The file is distributed “as is,” without any warranty
+**  Distribution: The file is distributed �as is,� without any warranty
 **                of any kind.
 **
 *****************************************************************************
@@ -151,7 +151,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
index 28cd96131..d4b86b3e3 100644
--- a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
@@ -145,7 +145,7 @@ SECTIONS
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.h b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
index 5c348b812..5562b95a8 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.h
@@ -69,7 +69,7 @@ static inline void board_clock_init(void)
    */
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
 
-  /** Initializes the CPU, AHB and APB busses clocks
+  /** Initializes the CPU, AHB and APB buses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -92,7 +92,7 @@ static inline void board_clock_init(void)
 
   HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
 
-  /** Initializes the CPU, AHB and APB busses clocks
+  /** Initializes the CPU, AHB and APB buses clocks
    */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index 3143b1024..fa41ebf8a 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -182,7 +182,7 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
   HID_COLLECTION ( HID_COLLECTION_APPLICATION )                    ,\
     /* Report ID if any */\
     __VA_ARGS__ \
-    /* 8 bits Modifier Keys (Shfit, Control, Alt) */ \
+    /* 8 bits Modifier Keys (Shift, Control, Alt) */ \
     HID_USAGE_PAGE ( HID_USAGE_PAGE_KEYBOARD )                     ,\
       HID_USAGE_MIN    ( 224                                    )  ,\
       HID_USAGE_MAX    ( 231                                    )  ,\
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index af4a92732..0f6d3f60d 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -599,7 +599,7 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
 
     // At this point, a transfer MAY be in progress. Based on USB spec, when clearing bulk EP HALT,
     // the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if 
-    // the EP is not halted. The only USBD API interface to do this is to stall and then unstall the EP.
+    // the EP is not halted. The only USBD API interface to do this is to stall and then un-stall the EP.
     if(ep_addr == usbtmc_state.ep_bulk_out)
     {
       criticalEnter();
diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 0bb8b6e41..961da81d6 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -243,7 +243,7 @@ static struct
 
 // Converts xfer pointer to epnum (0,1,2,3) regardless of xfer direction
 #define XFER_EPNUM(xfer)      ((xfer - &_dcd.xfer_status[0][0]) >> 1)
-// Converts xfer pinter to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number)
+// Converts xfer pointer to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number)
 #define XFER_REGS(xfer)       ep_regs[XFER_EPNUM(xfer)]
 // Converts epnum (0,1,2,3) to EPx_REGS pointer
 #define EPNUM_REGS(epnum)     ep_regs[epnum]
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index ca37d799f..afc14b010 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -170,7 +170,7 @@ static void xact_out_dma(uint8_t epnum)
   uint32_t xact_len;
 
   // DMA can't be active during read of SIZE.EPOUT or SIZE.ISOOUT, so try to lock,
-  // If already running deffer call regardless if it was called from ISR or task,
+  // If already running defer call regardless if it was called from ISR or task,
   if ( atomic_flag_test_and_set(&_dcd.dma_running) )
   {
     usbd_defer_func((osal_task_func_t)xact_out_dma_wrapper, (void *)(uint32_t)epnum, is_in_isr());
diff --git a/src/portable/renesas/usba/hcd_usba.c b/src/portable/renesas/usba/hcd_usba.c
index 5246ecb94..18cd5f148 100644
--- a/src/portable/renesas/usba/hcd_usba.c
+++ b/src/portable/renesas/usba/hcd_usba.c
@@ -600,7 +600,7 @@ uint32_t hcd_frame_number(uint8_t rhport)
 bool hcd_port_connect_status(uint8_t rhport)
 {
   (void)rhport;
-  return USB0.INTSTS1.BIT.ATTCH ? true: false;
+  return USB0.INTSTS1.BIT.ATTCH ? true : false;
 }
 
 void hcd_port_reset(uint8_t rhport)
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c
index e368b5f39..a3f228dd9 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.c
+++ b/src/portable/valentyusb/eptri/dcd_eptri.c
@@ -465,7 +465,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
       enable = 1;
     usb_out_ctrl_write((0 << CSR_USB_OUT_CTRL_STALL_OFFSET) | (enable << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | tu_edpt_number(ep_addr));
   }
-  // IN endpoints will get unstalled when more data is written.
+  // IN endpoints will get un-stalled when more data is written.
 }
 
 bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)

From e3df3ac5ce3d8ccb4c8b52eeaf0fef3ebd91eb14 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 4 Dec 2022 20:29:24 +0700
Subject: [PATCH 1262/2085] add codespell config and ci run

---
 .codespell/exclude-file.txt      |  1 +
 .codespellrc                     |  8 ++++++++
 .github/workflows/build_arm.yml  |  4 ++++
 .github/workflows/pre-commit.yml | 24 ++++++++++++++++++++++++
 4 files changed, 37 insertions(+)
 create mode 100644 .codespell/exclude-file.txt
 create mode 100644 .codespellrc
 create mode 100644 .github/workflows/pre-commit.yml

diff --git a/.codespell/exclude-file.txt b/.codespell/exclude-file.txt
new file mode 100644
index 000000000..af8265cc7
--- /dev/null
+++ b/.codespell/exclude-file.txt
@@ -0,0 +1 @@
+  return USB0.INTSTS1.BIT.ATTCH ? true : false;
diff --git a/.codespellrc b/.codespellrc
new file mode 100644
index 000000000..0e1bc1483
--- /dev/null
+++ b/.codespellrc
@@ -0,0 +1,8 @@
+# See: https://github.com/codespell-project/codespell#using-a-config-file
+[codespell]
+# In the event of a false positive, add the problematic word, in all lowercase, to a comma-separated list here:
+ignore-words-list = synopsys, sie, tre, hsi, fro, dout, mot, te
+check-filenames =
+check-hidden =
+skip = .cproject,./.git,./hw/mcu,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./test/vendor,./tests_obsolete
+exclude-file = .codespell/exclude-file.txt
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 369048fc6..0dab46d0f 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -7,6 +7,10 @@ on:
     types:
       - created
 
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
 jobs:
   # ---------------------------------------
   # Unit testing with Ceedling
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
new file mode 100644
index 000000000..7baf66e72
--- /dev/null
+++ b/.github/workflows/pre-commit.yml
@@ -0,0 +1,24 @@
+name: pre-commit
+
+on:
+  pull_request:
+  push:
+
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
+jobs:
+  pre-commit:
+    runs-on: ubuntu-latest
+    steps:
+    - name: Setup Python
+      uses: actions/setup-python@v4
+      with:
+        python-version: '3.x'
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v3
+
+    - name: Check Code Spelling
+      uses: codespell-project/actions-codespell@master
\ No newline at end of file

From b9314bddc5ca53c277a4472d7d162067c5e28604 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 4 Dec 2022 20:52:02 +0700
Subject: [PATCH 1263/2085] check exclude file

---
 .codespell/exclude-file.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.codespell/exclude-file.txt b/.codespell/exclude-file.txt
index af8265cc7..8b1378917 100644
--- a/.codespell/exclude-file.txt
+++ b/.codespell/exclude-file.txt
@@ -1 +1 @@
-  return USB0.INTSTS1.BIT.ATTCH ? true : false;
+

From b37870c964e9fafe8cdd4ff6e48fa072ca59858b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 4 Dec 2022 21:08:47 +0700
Subject: [PATCH 1264/2085] test exclude-file.txt, add action concurrency

---
 .codespell/exclude-file.txt         |  2 +-
 .codespellrc                        |  2 +-
 .github/workflows/build_aarch64.yml |  4 ++++
 .github/workflows/build_arm.yml     | 21 ---------------------
 .github/workflows/build_esp.yml     |  4 ++++
 .github/workflows/build_msp430.yml  |  4 ++++
 .github/workflows/build_renesas.yml |  4 ++++
 .github/workflows/build_riscv.yml   |  4 ++++
 .github/workflows/pre-commit.yml    | 16 ++++++++++++++--
 9 files changed, 36 insertions(+), 25 deletions(-)

diff --git a/.codespell/exclude-file.txt b/.codespell/exclude-file.txt
index 8b1378917..af8265cc7 100644
--- a/.codespell/exclude-file.txt
+++ b/.codespell/exclude-file.txt
@@ -1 +1 @@
-
+  return USB0.INTSTS1.BIT.ATTCH ? true : false;
diff --git a/.codespellrc b/.codespellrc
index 0e1bc1483..19a877e2a 100644
--- a/.codespellrc
+++ b/.codespellrc
@@ -5,4 +5,4 @@ ignore-words-list = synopsys, sie, tre, hsi, fro, dout, mot, te
 check-filenames =
 check-hidden =
 skip = .cproject,./.git,./hw/mcu,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./test/vendor,./tests_obsolete
-exclude-file = .codespell/exclude-file.txt
+exclude-file = ./.codespell/exclude-file.txt
diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index af26f33f2..49973fe41 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -7,6 +7,10 @@ on:
     types:
       - created
 
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
 jobs:
   # ---------------------------------------
   # Build AARCH64 family
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 0dab46d0f..56200465b 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -12,27 +12,6 @@ concurrency:
   cancel-in-progress: true
 
 jobs:
-  # ---------------------------------------
-  # Unit testing with Ceedling
-  # ---------------------------------------
-  unit-test:
-    runs-on: ubuntu-latest
-    steps:
-    - name: Setup Ruby
-      uses: ruby/setup-ruby@v1
-      with:
-        ruby-version: '2.7'
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Unit Tests
-      run: |
-        # Install Ceedling
-        gem install ceedling
-        cd test
-        ceedling test:all
-
   # ---------------------------------------
   # Build ARM family
   # ---------------------------------------
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 51d91de49..d775e50b6 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -7,6 +7,10 @@ on:
     types:
       - created
 
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
 jobs:
   build-esp:
     runs-on: ubuntu-latest
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 1ef25a6a0..d28341e5b 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -7,6 +7,10 @@ on:
     types:
       - created
 
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
 jobs:  
   build-msp430:
     runs-on: ubuntu-latest
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 2e272c832..6cb873dd8 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -7,6 +7,10 @@ on:
     types:
       - created
 
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
 jobs:
   build-rx:
     runs-on: ubuntu-latest
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 61c1c60c5..18e952d92 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -7,6 +7,10 @@ on:
     types:
       - created
 
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
 jobs:
   build-riscv:
     runs-on: ubuntu-latest
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index 7baf66e72..2463903f8 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -17,8 +17,20 @@ jobs:
       with:
         python-version: '3.x'
 
+    - name: Setup Ruby
+      uses: ruby/setup-ruby@v1
+      with:
+        ruby-version: '2.7'
+
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Check Code Spelling
-      uses: codespell-project/actions-codespell@master
\ No newline at end of file
+    - name: Run codespell
+      uses: codespell-project/actions-codespell@master
+
+    - name: Run Unit Tests
+      run: |
+        # Install Ceedling
+        gem install ceedling
+        cd test
+        ceedling test:all
\ No newline at end of file

From feed1a83a9e7b63563278d4e86919077b4de2d72 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 4 Dec 2022 21:28:20 +0700
Subject: [PATCH 1265/2085] add ignore-words to make it easier to

---
 .codespell/ignore-words.txt |  8 ++++++++
 .codespellrc                | 10 ++++++----
 2 files changed, 14 insertions(+), 4 deletions(-)
 create mode 100644 .codespell/ignore-words.txt

diff --git a/.codespell/ignore-words.txt b/.codespell/ignore-words.txt
new file mode 100644
index 000000000..e37d97a9f
--- /dev/null
+++ b/.codespell/ignore-words.txt
@@ -0,0 +1,8 @@
+synopsys
+sie
+tre
+hsi
+fro
+dout
+mot
+te
diff --git a/.codespellrc b/.codespellrc
index 19a877e2a..142bbbe1a 100644
--- a/.codespellrc
+++ b/.codespellrc
@@ -1,8 +1,10 @@
 # See: https://github.com/codespell-project/codespell#using-a-config-file
 [codespell]
-# In the event of a false positive, add the problematic word, in all lowercase, to a comma-separated list here:
-ignore-words-list = synopsys, sie, tre, hsi, fro, dout, mot, te
+# In the event of a false positive, add the problematic word, in all lowercase, to 'ignore-words.txt' (one word per line).
+# Or copy & paste the whole problematic line to 'exclude-file.txt'
+ignore-words = .codespell/ignore-words.txt
+exclude-file = .codespell/exclude-file.txt
 check-filenames =
 check-hidden =
-skip = .cproject,./.git,./hw/mcu,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./test/vendor,./tests_obsolete
-exclude-file = ./.codespell/exclude-file.txt
+count =
+skip = .cproject,./.git,./hw/mcu,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./test/vendor,./tests_obsolete,./tools/uf2

From de5a67bf3b8737a580539c5fbc6a054c90e4a084 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 5 Dec 2022 12:09:41 +0700
Subject: [PATCH 1266/2085] clean osal_freertos, update freertos examples to
 work with configSUPPORT_DYNAMIC_ALLOCATION only

note: for example to build with configSUPPORT_STATIC_ALLOCATION = 0, one
of heap_n.c must be included in makefile/cmake
---
 examples/device/cdc_msc_freertos/Makefile     | 11 ++-
 .../src/FreeRTOSConfig/FreeRTOSConfig.h       |  2 +-
 examples/device/cdc_msc_freertos/src/main.c   | 24 ++++--
 .../device/hid_composite_freertos/Makefile    | 11 ++-
 .../src/FreeRTOSConfig/FreeRTOSConfig.h       |  7 +-
 .../device/hid_composite_freertos/src/main.c  | 24 ++++--
 src/osal/osal_freertos.h                      | 84 ++++++++++---------
 src/portable/ehci/ehci.c                      |  2 +-
 8 files changed, 100 insertions(+), 65 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 3352dd37d..ff4b41108 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -29,8 +29,15 @@ SRC_C += \
 	$(FREERTOS_SRC)/timers.c \
 	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
 
-# Suppress FreeRTOS warnings
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+# include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
+# SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
+# CFLAGS += -Wno-error=sign-compare
+
+# Suppress FreeRTOSConfig.h warnings
+CFLAGS += -Wno-error=redundant-decls
+
+# Suppress FreeRTOS source warnings
+CFLAGS += -Wno-error=cast-qual
 
 # FreeRTOS (lto + Os) linker issue
 LDFLAGS += -Wl,--undefined=vTaskSwitchContext
diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 6a3630dbc..968c59749 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -69,7 +69,7 @@
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
 #define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( 0*1024 ) // dynamic is not used
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
 #define configIDLE_SHOULD_YIELD                 1
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 755220c13..cfb14aa2b 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -51,6 +51,8 @@
   #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
+#define CDC_STACK_SZIE      configMINIMAL_STACK_SIZE
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
@@ -66,19 +68,18 @@ enum  {
   BLINK_SUSPENDED = 2500,
 };
 
-// static timer
+// static timer & task
+#if configSUPPORT_STATIC_ALLOCATION
 StaticTimer_t blinky_tmdef;
-TimerHandle_t blinky_tm;
 
-// static task
 StackType_t  usb_device_stack[USBD_STACK_SIZE];
 StaticTask_t usb_device_taskdef;
 
-// static task for cdc
-#define CDC_STACK_SZIE      configMINIMAL_STACK_SIZE
 StackType_t  cdc_stack[CDC_STACK_SZIE];
 StaticTask_t cdc_taskdef;
+#endif
 
+TimerHandle_t blinky_tm;
 
 void led_blinky_cb(TimerHandle_t xTimer);
 void usb_device_task(void* param);
@@ -92,15 +93,22 @@ int main(void)
 {
   board_init();
 
+#if configSUPPORT_STATIC_ALLOCATION
   // soft timer for blinky
   blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
-  xTimerStart(blinky_tm, 0);
 
   // Create a task for tinyusb device stack
-  (void) xTaskCreateStatic( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
 
   // Create CDC task
-  (void) xTaskCreateStatic( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+  xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+#else
+  blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
+  xTaskCreate( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
+  xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+#endif
+
+  xTimerStart(blinky_tm, 0);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
 #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index 6c8c43ddd..9c66b896d 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -28,8 +28,15 @@ SRC_C += \
 	$(FREERTOS_SRC)/timers.c \
 	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
 
-# Suppress FreeRTOS warnings
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+# include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
+# SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
+# CFLAGS += -Wno-error=sign-compare
+
+# Suppress FreeRTOSConfig.h warnings
+CFLAGS += -Wno-error=redundant-decls
+
+# Suppress FreeRTOS source warnings
+CFLAGS += -Wno-error=cast-qual
 
 # FreeRTOS (lto + Os) linker issue
 LDFLAGS += -Wl,--undefined=vTaskSwitchContext
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index bfdf1e926..968c59749 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -46,13 +46,14 @@
 #include "bsp/board_mcu.h"
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
-#error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
+  #error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
 #endif
 
+// TODO fix later
 #if CFG_TUSB_MCU == OPT_MCU_MM32F327X
-  // TODO fix/remove later  
   extern u32 SystemCoreClock;
 #else
+  // FIXME cause redundant-decls warnings
   extern uint32_t SystemCoreClock;
 #endif
 
@@ -68,7 +69,7 @@
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
 #define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( 0*1024 ) // dynamic is not used
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
 #define configIDLE_SHOULD_YIELD                 1
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index b67c10937..fb0d69258 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -53,6 +53,8 @@
   #define USBD_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
+#define HID_STACK_SZIE      configMINIMAL_STACK_SIZE
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
@@ -68,19 +70,18 @@ enum  {
   BLINK_SUSPENDED = 2500,
 };
 
-// static timer
+// static timer & task
+#if configSUPPORT_STATIC_ALLOCATION
 StaticTimer_t blinky_tmdef;
-TimerHandle_t blinky_tm;
 
-// static task
 StackType_t  usb_device_stack[USBD_STACK_SIZE];
 StaticTask_t usb_device_taskdef;
 
-// static task for hid
-#define HID_STACK_SZIE      configMINIMAL_STACK_SIZE
 StackType_t  hid_stack[HID_STACK_SZIE];
 StaticTask_t hid_taskdef;
+#endif
 
+TimerHandle_t blinky_tm;
 
 void led_blinky_cb(TimerHandle_t xTimer);
 void usb_device_task(void* param);
@@ -94,15 +95,22 @@ int main(void)
 {
   board_init();
 
+#if configSUPPORT_STATIC_ALLOCATION
   // soft timer for blinky
   blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
-  xTimerStart(blinky_tm, 0);
 
   // Create a task for tinyusb device stack
-  (void) xTaskCreateStatic( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
+  xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef);
 
   // Create HID task
-  (void) xTaskCreateStatic( hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef);
+  xTaskCreateStatic(hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, hid_stack, &hid_taskdef);
+#else
+  blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
+  xTaskCreate(hid_task, "hid", HID_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+#endif
+
+  xTimerStart(blinky_tm, 0);
 
   // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
 #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index ccb98cc99..327aa9970 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -37,6 +37,43 @@
 extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+#if configSUPPORT_STATIC_ALLOCATION
+  typedef StaticSemaphore_t osal_semaphore_def_t;
+  typedef StaticSemaphore_t osal_mutex_def_t;
+#else
+  // not used therefore defined to smallest possible type to save space
+  typedef uint8_t osal_semaphore_def_t;
+  typedef uint8_t osal_mutex_def_t;
+#endif
+
+typedef SemaphoreHandle_t osal_semaphore_t;
+typedef SemaphoreHandle_t osal_mutex_t;
+
+// _int_set is not used with an RTOS
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
+  static _type _name##_##buf[_depth];\
+  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
+
+typedef struct
+{
+  uint16_t depth;
+  uint16_t item_sz;
+  void*    buf;
+#if configSUPPORT_STATIC_ALLOCATION
+  StaticQueue_t sq;
+#endif
+}osal_queue_def_t;
+
+typedef QueueHandle_t osal_queue_t;
+
+//--------------------------------------------------------------------+
+// TASK API
+//--------------------------------------------------------------------+
+
 TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec)
 {
   if (msec == OSAL_TIMEOUT_WAIT_FOREVER) return portMAX_DELAY;
@@ -51,9 +88,6 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec)
   return ticks;
 }
 
-//--------------------------------------------------------------------+
-// TASK API
-//--------------------------------------------------------------------+
 TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 {
   vTaskDelay( pdMS_TO_TICKS(msec) );
@@ -62,19 +96,13 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
 //--------------------------------------------------------------------+
 // Semaphore API
 //--------------------------------------------------------------------+
-#if configSUPPORT_STATIC_ALLOCATION == 1
-typedef StaticSemaphore_t osal_semaphore_def_t;
-#else
-typedef SemaphoreHandle_t osal_semaphore_def_t;
-#endif
-typedef SemaphoreHandle_t osal_semaphore_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
 {
-#if configSUPPORT_STATIC_ALLOCATION == 1
+#if configSUPPORT_STATIC_ALLOCATION
   return xSemaphoreCreateBinaryStatic(semdef);
 #else
-  (void)(semdef);
+  (void) semdef;
   return xSemaphoreCreateBinary();
 #endif
 }
@@ -101,7 +129,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t se
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec)
 {
   return xSemaphoreTake(sem_hdl, _osal_ms2tick(msec));
 }
@@ -114,25 +142,18 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c
 //--------------------------------------------------------------------+
 // MUTEX API (priority inheritance)
 //--------------------------------------------------------------------+
-#if configSUPPORT_STATIC_ALLOCATION == 1
-typedef StaticSemaphore_t osal_mutex_def_t;
-#else
-typedef SemaphoreHandle_t osal_mutex_def_t;
-#endif
-typedef SemaphoreHandle_t osal_mutex_t;
 
 TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
-#if configSUPPORT_STATIC_ALLOCATION == 1
+#if configSUPPORT_STATIC_ALLOCATION
   return xSemaphoreCreateMutexStatic(mdef);
 #else
-  (void)(mdef);
+  (void) mdef;
   return xSemaphoreCreateMutex();
 #endif
-
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec)
 {
   return osal_semaphore_wait(mutex_hdl, msec);
 }
@@ -146,26 +167,9 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 // QUEUE API
 //--------------------------------------------------------------------+
 
-// _int_set is not used with an RTOS
-#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
-  static _type _name##_##buf[_depth];\
-  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
-
-typedef struct
-{
-  uint16_t depth;
-  uint16_t item_sz;
-  void*    buf;
-#if configSUPPORT_STATIC_ALLOCATION == 1
-  StaticQueue_t sq;
-#endif
-}osal_queue_def_t;
-
-typedef QueueHandle_t osal_queue_t;
-
 TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
-#if configSUPPORT_STATIC_ALLOCATION == 1
+#if configSUPPORT_STATIC_ALLOCATION
 	return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
 #else
   return xQueueCreate(qdef->depth, qdef->item_sz);
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 361015964..76ba2a921 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -193,7 +193,7 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
   {
     // TODO check type for ISO iTD and siTD
     // TODO Suppress cast-align warning
-	#pragma GCC diagnostic push
+    #pragma GCC diagnostic push
     #pragma GCC diagnostic ignored "-Wcast-align"
     ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev);
     #pragma GCC diagnostic pop

From d58120647aef366de7a57e40b2572da03efdb415 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 5 Dec 2022 13:18:05 +0700
Subject: [PATCH 1267/2085] rename to match fido sample uf2_hid..h

---
 src/class/hid/hid.h        |  8 ++++----
 src/class/hid/hid_device.h | 10 +++++-----
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index 296664f62..d9b0ead10 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -708,7 +708,7 @@ enum {
   HID_USAGE_PAGE_MSR             = 0x8e,
   HID_USAGE_PAGE_CAMERA          = 0x90,
   HID_USAGE_PAGE_ARCADE          = 0x91,
-  HID_USAGE_PAGE_FIDO_ALLIANCE   = 0xF1D0,
+  HID_USAGE_PAGE_FIDO            = 0xF1D0, // FIDO alliance HID usage page
   HID_USAGE_PAGE_VENDOR          = 0xFF00 // 0xFF00 - 0xFFFF
 };
 
@@ -848,9 +848,9 @@ enum
 /// HID Usage Table: FIDO Alliance Page (0xF1D0)
 enum
 {
-  HID_USAGE_FIDO_U2F_AUTHENTICATOR_DEVICE  = 0x01,
-  HID_USAGE_FIDO_INPUT_REPORT_DATA         = 0x20,
-  HID_USAGE_FIDO_OUTPUT_REPORT_DATA        = 0x21
+  HID_USAGE_FIDO_U2FHID   = 0x01, // U2FHID usage for top-level collection
+  HID_USAGE_FIDO_DATA_IN  = 0x20, // Raw IN data report
+  HID_USAGE_FIDO_DATA_OUT = 0x21  // Raw OUT data report
 };
 
 /*--------------------------------------------------------------------
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index a9f47d644..025394126 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -356,20 +356,20 @@ static inline bool  tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
 // - 1st parameter is report size, which is 64 bytes maximum in U2F
 // - 2nd parameter is HID_REPORT_ID(n) (optional)
 #define TUD_HID_REPORT_DESC_FIDO_U2F(report_size, ...) \
-  HID_USAGE_PAGE_N ( HID_USAGE_PAGE_FIDO_ALLIANCE, 2          ) ,\
-  HID_USAGE      ( HID_USAGE_FIDO_U2F_AUTHENTICATOR_DEVICE    ) ,\
-  HID_COLLECTION ( HID_COLLECTION_APPLICATION                 ) ,\
+  HID_USAGE_PAGE_N ( HID_USAGE_PAGE_FIDO, 2                    ) ,\
+  HID_USAGE      ( HID_USAGE_FIDO_U2FHID                       ) ,\
+  HID_COLLECTION ( HID_COLLECTION_APPLICATION                  ) ,\
     /* Report ID if any */ \
     __VA_ARGS__ \
     /* Usage Data In */ \
-    HID_USAGE         ( HID_USAGE_FIDO_INPUT_REPORT_DATA       ) ,\
+    HID_USAGE         ( HID_USAGE_FIDO_DATA_IN                 ) ,\
     HID_LOGICAL_MIN   ( 0                                      ) ,\
     HID_LOGICAL_MAX_N ( 0xff, 2                                ) ,\
     HID_REPORT_SIZE   ( 8                                      ) ,\
     HID_REPORT_COUNT  ( report_size                            ) ,\
     HID_INPUT         ( HID_DATA | HID_VARIABLE | HID_ABSOLUTE ) ,\
     /* Usage Data Out */ \
-    HID_USAGE         ( HID_USAGE_FIDO_OUTPUT_REPORT_DATA      ) ,\
+    HID_USAGE         ( HID_USAGE_FIDO_DATA_OUT                ) ,\
     HID_LOGICAL_MIN   ( 0                                      ) ,\
     HID_LOGICAL_MAX_N ( 0xff, 2                                ) ,\
     HID_REPORT_SIZE   ( 8                                      ) ,\

From 603effbb77ab587bae9800993a53599a9dbff97e Mon Sep 17 00:00:00 2001
From: Tomas Rezucha <tomas.rezucha@espressif.com>
Date: Thu, 2 Jun 2022 13:22:53 +0200
Subject: [PATCH 1268/2085] cdc: Fix autoflush for FIFO < MPS

---
 src/class/cdc/cdc_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index fab6f0035..77c73030a 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -171,7 +171,7 @@ uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
   uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) bufsize);
 
   // flush if queue more than packet size
-  if ( tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE )
+  if ( (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE) || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) )
   {
     tud_cdc_n_write_flush(itf);
   }

From a652212f274bdbeb55bcc7e4276037393d76d77b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 09:14:38 +0700
Subject: [PATCH 1269/2085] update ceedling to 0.31.1

---
 test/project.yml                              |    1 +
 test/test/support/tusb_config.h               |    2 +-
 test/vendor/ceedling/bin/ceedling             |   79 +-
 test/vendor/ceedling/docs/CException.md       |  292 ---
 test/vendor/ceedling/docs/CMock_Summary.md    |  603 -----
 test/vendor/ceedling/docs/CeedlingPacket.md   | 2060 -----------------
 .../docs/ThrowTheSwitchCodingStandard.md      |  206 --
 ...tSuitableforPrintingandPossiblyFraming.pdf |  Bin 144467 -> 0 bytes
 .../ceedling/docs/UnityAssertionsReference.md |  779 -------
 .../ceedling/docs/UnityConfigurationGuide.md  |  433 ----
 .../ceedling/docs/UnityGettingStartedGuide.md |  192 --
 .../ceedling/docs/UnityHelperScriptsGuide.md  |  260 ---
 .../lib/ceedling/build_invoker_utils.rb       |    2 +-
 .../lib/ceedling/cacheinator_helper.rb        |   24 +-
 .../ceedling/lib/ceedling/configurator.rb     |   33 +-
 .../lib/ceedling/configurator_builder.rb      |   45 +-
 .../lib/ceedling/configurator_plugins.rb      |   22 +-
 .../lib/ceedling/configurator_setup.rb        |    1 +
 .../vendor/ceedling/lib/ceedling/constants.rb |    2 +
 test/vendor/ceedling/lib/ceedling/defaults.rb |   77 +-
 .../ceedling/lib/ceedling/dependinator.rb     |    7 +-
 .../lib/ceedling/file_finder_helper.rb        |   10 +-
 .../ceedling/lib/ceedling/file_path_utils.rb  |    8 +-
 .../ceedling/lib/ceedling/file_wrapper.rb     |    8 +-
 .../vendor/ceedling/lib/ceedling/generator.rb |    9 +-
 .../lib/ceedling/generator_test_results.rb    |   15 +-
 .../lib/ceedling/generator_test_runner.rb     |    6 +-
 test/vendor/ceedling/lib/ceedling/objects.yml |   49 +-
 .../ceedling/lib/ceedling/preprocessinator.rb |   30 +-
 .../ceedling/preprocessinator_extractor.rb    |   25 +
 .../ceedling/preprocessinator_file_handler.rb |   13 +
 .../lib/ceedling/preprocessinator_helper.rb   |    4 +
 .../preprocessinator_includes_handler.rb      |  140 +-
 .../lib/ceedling/project_config_manager.rb    |   12 +-
 test/vendor/ceedling/lib/ceedling/rakefile.rb |    1 -
 .../ceedling/lib/ceedling/release_invoker.rb  |   29 +-
 .../ceedling/lib/ceedling/rules_release.rake  |   21 +-
 .../ceedling/lib/ceedling/rules_tests.rake    |    9 +-
 .../ceedling/lib/ceedling/setupinator.rb      |    2 +-
 .../ceedling/lib/ceedling/task_invoker.rb     |   21 +-
 .../ceedling/lib/ceedling/tasks_base.rake     |   53 +-
 .../lib/ceedling/tasks_filesystem.rake        |   34 +-
 .../ceedling/lib/ceedling/tasks_tests.rake    |   14 +-
 .../lib/ceedling/test_includes_extractor.rb   |   26 +
 .../ceedling/lib/ceedling/test_invoker.rb     |   95 +-
 .../lib/ceedling/test_invoker_helper.rb       |    2 +-
 test/vendor/ceedling/lib/ceedling/version.rb  |   52 +-
 .../ceedling/lib/ceedling/version.rb.erb      |   15 -
 .../ceedling/plugins/bullseye/bullseye.rake   |   34 +-
 .../ceedling/plugins/bullseye/readme.txt      |    0
 test/vendor/ceedling/plugins/gcov/README.md   |  420 +++-
 .../ceedling/plugins/gcov/config/defaults.yml |   73 -
 test/vendor/ceedling/plugins/gcov/gcov.rake   |   99 +-
 test/vendor/ceedling/plugins/gcov/lib/gcov.rb |   33 +-
 .../plugins/gcov/lib/gcov_constants.rb        |   53 +-
 .../lib/junit_tests_report.rb                 |   19 +-
 .../module_generator/lib/module_generator.rb  |   16 +-
 .../module_generator/module_generator.rake    |   15 +
 .../plugins/subprojects/lib/subprojects.rb    |    4 +-
 .../plugins/xml_tests_report/README.md        |    2 +-
 .../vendor/c_exception/lib/CException.h       |    2 +-
 .../vendor/c_exception/release/build.info     |    2 -
 .../vendor/c_exception/release/version.info   |    2 -
 .../cmock/config/production_environment.rb    |   12 +-
 .../vendor/cmock/config/test_environment.rb   |    2 +-
 .../vendor/ceedling/vendor/cmock/lib/cmock.rb |   81 +-
 .../ceedling/vendor/cmock/lib/cmock_config.rb |  135 +-
 .../vendor/cmock/lib/cmock_file_writer.rb     |   31 +-
 .../vendor/cmock/lib/cmock_generator.rb       |  272 ++-
 .../cmock/lib/cmock_generator_plugin_array.rb |   30 +-
 .../lib/cmock_generator_plugin_callback.rb    |   24 +-
 .../lib/cmock_generator_plugin_cexception.rb  |   33 +-
 .../lib/cmock_generator_plugin_expect.rb      |   71 +-
 .../cmock_generator_plugin_expect_any_args.rb |   41 +-
 .../lib/cmock_generator_plugin_ignore.rb      |   61 +-
 .../lib/cmock_generator_plugin_ignore_arg.rb  |   12 +-
 .../cmock_generator_plugin_return_thru_ptr.rb |   84 +-
 .../vendor/cmock/lib/cmock_generator_utils.rb |  247 +-
 .../vendor/cmock/lib/cmock_header_parser.rb   |  533 +++--
 .../vendor/cmock/lib/cmock_plugin_manager.rb  |   45 +-
 .../cmock/lib/cmock_unityhelper_parser.rb     |   78 +-
 .../ceedling/vendor/cmock/release/build.info  |    2 -
 .../vendor/cmock/release/version.info         |    2 -
 test/vendor/ceedling/vendor/cmock/src/cmock.c |   90 +-
 test/vendor/ceedling/vendor/cmock/src/cmock.h |   33 +-
 .../vendor/cmock/src/cmock_internals.h        |   16 +-
 .../ceedling/vendor/cmock/src/meson.build     |   19 +-
 .../vendor/deep_merge/lib/deep_merge.rb       |  211 --
 .../vendor/unity/auto/generate_module.rb      |   42 +-
 .../vendor/unity/auto/generate_test_runner.rb |   56 +-
 .../ceedling/vendor/unity/auto/run_test.erb   |    7 +-
 .../ceedling/vendor/unity/release/build.info  |    2 -
 .../vendor/unity/release/version.info         |    2 -
 .../ceedling/vendor/unity/src/CMakeLists.txt  |   22 -
 .../ceedling/vendor/unity/src/meson.build     |   19 +-
 test/vendor/ceedling/vendor/unity/src/unity.c |  273 ++-
 test/vendor/ceedling/vendor/unity/src/unity.h |   56 +-
 .../vendor/unity/src/unity_internals.h        |   71 +-
 98 files changed, 2703 insertions(+), 6609 deletions(-)
 delete mode 100644 test/vendor/ceedling/docs/CException.md
 delete mode 100644 test/vendor/ceedling/docs/CMock_Summary.md
 delete mode 100644 test/vendor/ceedling/docs/CeedlingPacket.md
 delete mode 100644 test/vendor/ceedling/docs/ThrowTheSwitchCodingStandard.md
 delete mode 100644 test/vendor/ceedling/docs/UnityAssertionsCheatSheetSuitableforPrintingandPossiblyFraming.pdf
 delete mode 100644 test/vendor/ceedling/docs/UnityAssertionsReference.md
 delete mode 100644 test/vendor/ceedling/docs/UnityConfigurationGuide.md
 delete mode 100644 test/vendor/ceedling/docs/UnityGettingStartedGuide.md
 delete mode 100644 test/vendor/ceedling/docs/UnityHelperScriptsGuide.md
 delete mode 100644 test/vendor/ceedling/lib/ceedling/version.rb.erb
 delete mode 100644 test/vendor/ceedling/plugins/bullseye/readme.txt
 delete mode 100644 test/vendor/ceedling/plugins/gcov/config/defaults.yml
 delete mode 100644 test/vendor/ceedling/vendor/c_exception/release/build.info
 delete mode 100644 test/vendor/ceedling/vendor/c_exception/release/version.info
 delete mode 100644 test/vendor/ceedling/vendor/cmock/release/build.info
 delete mode 100644 test/vendor/ceedling/vendor/cmock/release/version.info
 delete mode 100644 test/vendor/ceedling/vendor/deep_merge/lib/deep_merge.rb
 delete mode 100644 test/vendor/ceedling/vendor/unity/release/build.info
 delete mode 100644 test/vendor/ceedling/vendor/unity/release/version.info
 delete mode 100644 test/vendor/ceedling/vendor/unity/src/CMakeLists.txt

diff --git a/test/project.yml b/test/project.yml
index dc4a9cb28..1bccc517f 100644
--- a/test/project.yml
+++ b/test/project.yml
@@ -15,6 +15,7 @@
 #  :release_build: TRUE
   :test_file_prefix: test_
   :which_ceedling: vendor/ceedling
+  :ceedling_version: 0.31.1
   :default_tasks:
     - test:all
 
diff --git a/test/test/support/tusb_config.h b/test/test/support/tusb_config.h
index 0455f933b..00818fae5 100644
--- a/test/test/support/tusb_config.h
+++ b/test/test/support/tusb_config.h
@@ -51,7 +51,7 @@
 
 // CFG_TUSB_DEBUG is defined by compiler in DEBUG build
 #ifndef CFG_TUSB_DEBUG
-#define CFG_TUSB_DEBUG           0
+#define CFG_TUSB_DEBUG           1
 #endif
 
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
diff --git a/test/vendor/ceedling/bin/ceedling b/test/vendor/ceedling/bin/ceedling
index fa099590a..d110f3d4c 100644
--- a/test/vendor/ceedling/bin/ceedling
+++ b/test/vendor/ceedling/bin/ceedling
@@ -49,16 +49,16 @@ unless (project_found)
     end
 
     desc "upgrade PROJECT_NAME", "upgrade ceedling for a project (not req'd if gem used)"
-    method_option :docs, :type => :boolean, :default => false, :desc => "Add docs in project vendor directory"
-    method_option :local, :type => :boolean, :default => false, :desc => "Create a copy of Ceedling in the project vendor directory"
-    method_option :no_configs, :type => :boolean, :default => false, :desc => "Don't install starter configuration files"
-    method_option :noconfigs, :type => :boolean, :default => false
-
-    #deprecated:
-    method_option :no_docs, :type => :boolean, :default => false
-    method_option :nodocs, :type => :boolean, :default => false
     def upgrade(name, silent = false)
-      copy_assets_and_create_structure(name, silent, true, options || {:upgrade => true})
+      as_local = true
+      begin
+        require "yaml"
+        as_local = (YAML.load_file(File.join(name, "project.yml"))[:project][:which_ceedling] != 'gem')
+      rescue
+        raise "ERROR: Could not find valid project file '#{yaml_path}'"
+      end
+      found_docs = File.exists?( File.join(name, "docs", "CeedlingPacket.md") )
+      copy_assets_and_create_structure(name, silent, true, {:upgrade => true, :no_configs => true, :local => as_local, :docs => found_docs})
     end
 
     no_commands do
@@ -90,26 +90,30 @@ unless (project_found)
         FileUtils.touch(File.join(test_support_path, '.gitkeep'))
 
         # If documentation requested, create a place to dump them and do so
+        doc_path = ""
         if use_docs
-          doc_path = File.join(ceedling_path, 'docs')
+          doc_path = use_gem ? File.join(name, 'docs') : File.join(ceedling_path, 'docs')
           FileUtils.mkdir_p doc_path
 
           in_doc_path = lambda {|f| File.join(doc_path, f)}
 
-          doc_files = [
-                        'docs/CeedlingPacket.md',
-                        'vendor/c_exception/docs/CException.md',
-                        'vendor/cmock/docs/CMock_Summary.md',
-                        'vendor/unity/docs/UnityAssertionsCheatSheetSuitableforPrintingandPossiblyFraming.pdf',
-                        'vendor/unity/docs/UnityAssertionsReference.md',
-                        'vendor/unity/docs/UnityConfigurationGuide.md',
-                        'vendor/unity/docs/UnityGettingStartedGuide.md',
-                        'vendor/unity/docs/UnityHelperScriptsGuide.md',
-                        'vendor/unity/docs/ThrowTheSwitchCodingStandard.md',
-                      ]
+          # Add documentation from main projects to list
+          doc_files = {}
+          ['docs','vendor/unity/docs','vendor/cmock/docs','vendor/cexception/docs'].each do |p|
+            Dir[ File.expand_path(File.join(here, p, '*.md')) ].each do |f|
+              doc_files[ File.basename(f) ] = f unless(doc_files.include? f)
+            end
+          end
 
-          doc_files.each do |f|
-            copy_file(f, in_doc_path.call(File.basename(f)), :force => force)
+          # Add documentation from plugins to list
+          Dir[ File.join(here, 'plugins/**/README.md') ].each do |plugin_path|
+            k = "plugin_" + plugin_path.split(/\\|\//)[-2] + ".md"
+            doc_files[ k ] = File.expand_path(plugin_path)
+          end
+
+          # Copy all documentation
+          doc_files.each_pair do |k, v|
+            copy_file(v, in_doc_path.call(k), :force => force)
           end
         end
 
@@ -133,7 +137,6 @@ unless (project_found)
             {:src => 'vendor/cmock/config/',        :dst => 'vendor/cmock/config'},
             {:src => 'vendor/cmock/lib/',           :dst => 'vendor/cmock/lib'},
             {:src => 'vendor/cmock/src/',           :dst => 'vendor/cmock/src'},
-            {:src => 'vendor/deep_merge/lib/',      :dst => 'vendor/deep_merge/lib'},
             {:src => 'vendor/diy/lib',              :dst => 'vendor/diy/lib'},
             {:src => 'vendor/unity/auto/',          :dst => 'vendor/unity/auto'},
             {:src => 'vendor/unity/src/',           :dst => 'vendor/unity/src'},
@@ -146,16 +149,24 @@ unless (project_found)
 
         # We're copying in a configuration file if we haven't said not to
         if (use_configs)
-          if use_gem
-            copy_file(File.join('assets', 'project_as_gem.yml'), File.join(name, 'project.yml'), :force => force)
+          dst_yaml = File.join(name, 'project.yml')
+          src_yaml = if use_gem
+            File.join(here, 'assets', 'project_as_gem.yml')
           else
-            copy_file(File.join('assets', 'project_with_guts.yml'), File.join(name, 'project.yml'), :force => force)
             if is_windows?
               copy_file(File.join('assets', 'ceedling.cmd'), File.join(name, 'ceedling.cmd'), :force => force)
             else
               copy_file(File.join('assets', 'ceedling'), File.join(name, 'ceedling'), :force => force)
               File.chmod(0755, File.join(name, 'ceedling'))
             end
+            File.join(here, 'assets', 'project_with_guts.yml')
+          end
+
+          # Perform the actual clone of the config file, while updating the version
+          File.open(dst_yaml,'w') do |dst|
+            require File.expand_path(File.join(File.dirname(__FILE__),"..","lib","ceedling","version.rb"))
+            dst << File.read(src_yaml).gsub(":ceedling_version: '?'",":ceedling_version: #{Ceedling::Version::CEEDLING}")
+            puts "      create  #{dst_yaml}"
           end
         end
 
@@ -167,8 +178,8 @@ unless (project_found)
         unless silent
           puts "\n"
           puts "Project '#{name}' #{force ? "upgraded" : "created"}!"
-          puts " - Tool documentation is located in vendor/ceedling/docs" if use_docs
-          puts " - Execute 'ceedling help' to view available test & build tasks"
+          puts " - Tool documentation is located in #{doc_path}" if use_docs
+          puts " - Execute 'ceedling help' from #{name} to view available test & build tasks"
           puts ''
         end
       end
@@ -206,10 +217,10 @@ unless (project_found)
 
     desc "version", "return the version of the tools installed"
     def version()
-      require 'ceedling/version.rb'
-      puts "  Ceedling::   #{Ceedling::Version::CEEDLING}"
-      puts "  CMock::      #{Ceedling::Version::CMOCK}"
-      puts "  Unity::      #{Ceedling::Version::UNITY}"
+      require File.expand_path(File.join(File.dirname(__FILE__),"..","lib","ceedling","version.rb"))
+      puts "    Ceedling:: #{Ceedling::Version::CEEDLING}"
+      puts "       CMock:: #{Ceedling::Version::CMOCK}"
+      puts "       Unity:: #{Ceedling::Version::UNITY}"
       puts "  CException:: #{Ceedling::Version::CEXCEPTION}"
     end
   end
@@ -287,6 +298,8 @@ else
         options[:list_tasks] = true
       when /^-T$/
         options[:list_tasks] = true
+      when /^--tasks$/
+        options[:list_tasks] = true
       when /^project:(\w+)/
         ENV['CEEDLING_USER_PROJECT_FILE'] = "#{$1}.yml"
       else
diff --git a/test/vendor/ceedling/docs/CException.md b/test/vendor/ceedling/docs/CException.md
deleted file mode 100644
index c3718191f..000000000
--- a/test/vendor/ceedling/docs/CException.md
+++ /dev/null
@@ -1,292 +0,0 @@
-
-CException
-==========
-
-CException is a basic exception framework for C, suitable for use in
-embedded applications.  It provides an exception framework similar in
-use to C++, but with much less overhead.
-
-
-CException uses C standard library functions `setjmp` and `longjmp` to
-operate.  As long as the target system has these two functions defined,
-this library should be useable with very little configuration.  It
-even supports environments where multiple program flows are in use,
-such as real-time operating systems.
-
-
-There are about a gabillion exception frameworks using a similar
-setjmp/longjmp method out there... and there will probably be more
-in the future. Unfortunately, when we started our last embedded
-project, all those that existed either (a) did not support multiple
-tasks (therefore multiple stacks) or (b) were way more complex than
-we really wanted.  CException was born.
-
-
-*Why use CException?*
-
-
-0. It's ANSI C, and it beats passing error codes around.
-1. You want something simple... CException throws a single id. You can
-   define those ID's to be whatever you like. You might even choose which
-   type that number is for your project. But that's as far as it goes.
-   We weren't interested in passing objects or structs or strings...
-   just simple error codes.
-2. Performance... CException can be configured for single tasking or
-   multitasking. In single tasking, there is very little overhead past
-   the setjmp/longjmp calls (which are already fast). In multitasking,
-   your only additional overhead is the time it takes you to determine
-   a unique task id 0 - num_tasks.
-
-
-For the latest version, go to [ThrowTheSwitch.org](http://throwtheswitch.org)
-
-
-CONTENTS OF THIS DOCUMENT
-=========================
-
-* Usage
-* Limitations
-*API
-* Configuration
-* Testing
-* License
-
-
-Usage
------
-
-Code that is to be protected are wrapped in `Try { } Catch { }` blocks.
-The code directly following the Try call is "protected", meaning that
-if any Throws occur, program control is directly transferred to the
-start of the Catch block.
-
-
-A numerical exception ID is included with Throw, and is made accessible
-from the Catch block.
-
-
-Throws can occur from within function calls (nested as deeply as you
-like) or directly from within the function itself.
-
-
-
-Limitations
------------
-
-
-This library was made to be as fast as possible, and provide basic
-exception handling.  It is not a full-blown exception library.  Because
-of this, there are a few limitations that should be observed in order
-to successfully utilize this library:
-
-1. Do not directly "return" from within a `Try` block, nor `goto`
-   into or out of a `Try` block.
-
-   *Why?*
-
-   The `Try` macro allocates some local memory and alters a global
-   pointer.  These are cleaned up at the top of the `Catch` macro.
-   Gotos and returns would bypass some of these steps, resulting in
-   memory leaks or unpredictable behavior.
-
-
-2. If (a) you change local (stack) variables within your `Try` block,
-   AND (b) wish to make use of the updated values after an exception
-   is thrown, those variables should be made `volatile`. Note that this
-   is ONLY for locals and ONLY when you need access to them after a
-   `Throw`.
-
-   *Why?*
-
-   Compilers optimize.  There is no way to guarantee that the actual
-   memory location was updated and not just a register unless the
-   variable is marked volatile.
-
-
-3. Memory which is `malloc`'d or `new`'d is not automatically released
-   when an error is thrown.  This will sometimes be desirable, and
-   othertimes may not.  It will be the responsibility of the `Catch`
-   block to perform this kind of cleanup.
-
-   *Why?*
-
-   There's just no easy way to track `malloc`'d memory, etc., without
-   replacing or wrapping malloc calls or something like that.  This
-   is a light framework, so these options were not desirable.
-
-
-
-API
----
-
-###Try
-
-`Try` is a macro which starts a protected block.  It MUST be followed by
-a pair of braces or a single protected line (similar to an 'if'),
-enclosing the data that is to be protected.  It **must** be followed by a
-`Catch` block (don't worry, you'll get compiler errors to let you know if
-you mess any of that up).
-
-
-###Catch(e)
-
-`Catch` is a macro which ends the `Try` block and starts the error handling
-block. The `Catch` block is called if and only if an exception was thrown
-while within the `Try` block.  This error was thrown by a `Throw` call
-somewhere within `Try` (or within a function called within `Try`, or a function
-called by a function called within `Try`, etc).
-
-The single parameter `e` is filled with the error code which was thrown.
-This can be used for reporting, conditional cleanup, etc. (or you can just
-ignore it if you really want... people ignore return codes all the time,
-right?).  `e` should be of type `EXCEPTION_T`
-
-
-###Throw(e)
-
-This is the method of throwing an error. A `Throw` should only occur from within a
-protected (`Try` ... `Catch`) block, though it may easily be nested many function
-calls deep without an impact on performance or functionality. `Throw` takes
-a single argument, which is an exception id which will be passed to `Catch`
-as the reason for the error.
-
-If you wish to rethrow an error, this can be done by calling `Throw(e)` with
-the error code you just caught.  It **is** valid to throw from a catch block.
-
-
-###ExitTry()
-
-On rare occasion, you might want to immediately exit your current `Try` block
-but **not** treat this as an error. Don't run the `Catch`. Just start executing
-from after the `Catch` as if nothing had happened... That's what `ExitTry` is
-for.
-
-
-CONFIGURATION
--------------
-
-CException is a mostly portable library.  It has one universal
-dependency, and some macros which are required if working in a
-multi-tasking environment.
-
-1. The standard C library setjmp must be available.  Since this is part
-   of the standard library, chances are good that you'll be fine.
-
-2. If working in a multitasking environment, methods for obtaining an
-   index into an array of frames and to get the overall number of
-   id's are required.  If the OS supports a method to retrieve Task
-   ID's, and those Tasks are number 0, 1, 2... you are in an ideal
-   situation.  Otherwise, a more creative mapping function may be
-   required.  Note that this function is likely to be called twice
-   for each protected block and once during a throw.  This is the
-   only overhead in the system.
-
-
-Exception.h
------------
-
-By convention, most projects include `Exception.h` which defines any
-further requirements, then calls `CException.h` to do the gruntwork.  All
-of these are optional.  You could directly include `CException.h` if
-you wanted and just use the defaults provided.
-
-* `EXCEPTION_T`
-  * Set this to the type you want your exception id's to be.  Defaults to 'unsigned int'.
-
-* `EXCEPTION_NONE`
-  * Set this to a number which will never be an exception id in your system.  Defaults to `0x5a5a5a5a`.
-
-* `EXCEPTION_GET_ID`
-  * If in a multi-tasking environment, this should be
-    set to be a call to the function described in #2 above.
-    Defaults to just return `0` all the time (good for
-    single tasking environments)
-
-* `EXCEPTION_NUM_ID`
-  * If in a multi-tasking environment, this should be set
-    to the number of ID's required (usually the number of
-    tasks in the system).  Defaults to `1` (for single
-    tasking environments).
-
-* `CEXCEPTION_NO_CATCH_HANDLER(id)`
-  * This macro can be optionally specified.
-    It allows you to specify code to be called when a Throw
-    is made outside of `Try` ... `Catch` protection.  Consider
-    this the emergency fallback plan for when something has
-    gone terribly wrong.
-
-
-You may also want to include any header files which will commonly be
-needed by the rest of your application where it uses exception handling
-here.  For example, OS header files or exception codes would be useful.
-
-
-Finally, there are some hook macros which you can implement to inject
-your own target-specific code in particular places. It is a rare instance
-where you will need these, but they are here if you need them:
-
-
-* `CEXCEPTION_HOOK_START_TRY`
-  * called immediately before the Try block
-
-* `CEXCEPTION_HOOK_HAPPY_TRY`
-  * called immediately after the Try block if no exception was thrown
-
-* `CEXCEPTION_HOOK_AFTER_TRY`
-  * called immediately after the Try block OR before an exception is caught
-
-* `CEXCEPTION_HOOK_START_CATCH`
-  * called immediately before the catch
-
-
-
-TESTING
--------
-
-
-If you want to validate that CException works with your tools or that
-it works with your custom configuration, you may want to run the test
-suite.
-
-
-The test suite included makes use of the `Unity` Test Framework.  It will
-require a native C compiler. The example makefile uses MinGW's gcc.
-Modify the makefile to include the proper paths to tools, then run `make`
-to compile and run the test application.
-
-* `C_COMPILER`
-  * The C compiler to use to perform the tests
-
-* `C_LIBS`
-  * The path to the C libraries (including setjmp)
-
-* `UNITY_DIR`
-  * The path to the Unity framework (required to run tests)
-    (get it at [ThrowTheSwitch.org](http://throwtheswitch.org))
-
-
-
-LICENSE
--------
-
-This software is licensed under the MIT License
-
-Copyright (c) 2007-2017 Mark VanderVoord
-
-Permission is hereby granted, free of charge, to any person obtaining a copy
-of this software and associated documentation files (the "Software"), to deal
-in the Software without restriction, including without limitation the rights
-to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-copies of the Software, and to permit persons to whom the Software is
-furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in
-all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-THE SOFTWARE.
diff --git a/test/vendor/ceedling/docs/CMock_Summary.md b/test/vendor/ceedling/docs/CMock_Summary.md
deleted file mode 100644
index 87f9c00b8..000000000
--- a/test/vendor/ceedling/docs/CMock_Summary.md
+++ /dev/null
@@ -1,603 +0,0 @@
-CMock: A Summary
-================
-
-*[ThrowTheSwitch.org](http://throwtheswitch.org)*
-
-*This documentation is released under a Creative Commons 3.0 Attribution Share-Alike License*
-
-
-What Exactly Are We Talking About Here?
----------------------------------------
-
-CMock is a nice little tool which takes your header files and creates
-a Mock interface for it so that you can more easily unit test modules
-that touch other modules. For each function prototype in your
-header, like this one:
-
-    int DoesSomething(int a, int b);
-
-
-...you get an automatically generated DoesSomething function
-that you can link to instead of your real DoesSomething function.
-By using this Mocked version, you can then verify that it receives
-the data you want, and make it return whatever data you desire,
-make it throw errors when you want, and more... Create these for
-everything your latest real module touches, and you're suddenly
-in a position of power: You can control and verify every detail
-of your latest creation.
-
-To make that easier, CMock also gives you a bunch of functions
-like the ones below, so you can tell that generated DoesSomething
-function how to behave for each test:
-
-    void DoesSomething_ExpectAndReturn(int a, int b, int toReturn);
-    void DoesSomething_ExpectAndThrow(int a, int b, EXCEPTION_T error);
-    void DoesSomething_StubWithCallback(CMOCK_DoesSomething_CALLBACK YourCallback);
-    void DoesSomething_IgnoreAndReturn(int toReturn);
-
-
-You can pile a bunch of these back to back, and it remembers what
-you wanted to pass when, like so:
-
-    test_CallsDoesSomething_ShouldDoJustThat(void)
-    {
-        DoesSomething_ExpectAndReturn(1,2,3);
-        DoesSomething_ExpectAndReturn(4,5,6);
-        DoesSomething_ExpectAndThrow(7,8, STATUS_ERROR_OOPS);
-
-        CallsDoesSomething( );
-    }
-
-
-This test will call CallsDoesSomething, which is the function
-we are testing. We are expecting that function to call DoesSomething
-three times. The first time, we check to make sure it's called
-as DoesSomething(1, 2) and we'll magically return a 3. The second
-time we check for DoesSomething(4, 5) and we'll return a 6. The
-third time we verify DoesSomething(7, 8) and we'll throw an error
-instead of returning anything. If CallsDoesSomething gets
-any of this wrong, it fails the test. It will fail if you didn't
-call DoesSomething enough, or too much, or with the wrong arguments,
-or in the wrong order.
-
-CMock is based on Unity, which it uses for all internal testing.
-It uses Ruby to do all the main work (versions 2.0.0 and above).
-
-
-Installing
-==========
-
-The first thing you need to do to install CMock is to get yourself
-a copy of Ruby. If you're on linux or osx, you probably already
-have it. You can prove it by typing the following:
-
-    ruby --version
-
-
-If it replied in a way that implies ignorance, then you're going to
-need to install it. You can go to [ruby-lang](https://ruby-lang.org)
-to get the latest version. You're also going to need to do that if it
-replied with a version that is older than 2.0.0. Go ahead. We'll wait.
-
-Once you have Ruby, you have three options:
-
-* Clone the latest [CMock repo on github](https://github.com/ThrowTheSwitch/CMock/)
-* Download the latest [CMock zip from github](https://github.com/ThrowTheSwitch/CMock/)
-* Install Ceedling (which has it built in!) through your commandline using `gem install ceedling`.
-
-
-Generated Mock Module Summary
-=============================
-
-In addition to the mocks themselves, CMock will generate the
-following functions for use in your tests. The expect functions
-are always generated. The other functions are only generated
-if those plugins are enabled:
-
-
-Expect:
--------
-
-Your basic staple Expects which will be used for most of your day
-to day CMock work. By calling this, you are telling CMock that you
-expect that function to be called during your test. It also specifies
-which arguments you expect it to be called with, and what return
-value you want returned when that happens. You can call this function
-multiple times back to back in order to queue up multiple calls.
-
-* `void func(void)` => `void func_Expect(void)`
-* `void func(params)` => `void func_Expect(expected_params)`
-* `retval func(void)` => `void func_ExpectAndReturn(retval_to_return)`
-* `retval func(params)` => `void func_ExpectAndReturn(expected_params, retval_to_return)`
-
-
-ExpectAnyArgs:
---------------
-
-This behaves just like the Expects calls, except that it doesn't really
-care what the arguments are that the mock gets called with. It still counts
-the number of times the mock is called and it still handles return values
-if there are some.
-
-* `void func(void)` => `void func_ExpectAnyArgs(void)`
-* `void func(params)` => `void func_ExpectAnyArgs(void)`
-* `retval func(void)` => `void func_ExpectAnyArgsAndReturn(retval_to_return)`
-* `retval func(params)` => `void func_ExpectAnyArgsAndReturn(retval_to_return)`
-
-
-Array:
-------
-
-An ExpectWithArray is another variant of Expect. Like expect, it cares about
-the number of times a mock is called, the arguments it is called with, and the
-values it is to return. This variant has another feature, though. For anything
-that resembles a pointer or array, it breaks the argument into TWO arguments.
-The first is the original pointer. The second specify the number of elements
-it is to verify of that array. If you specify 1, it'll check one object. If 2,
-it'll assume your pointer is pointing at the first of two elements in an array.
-If you specify zero elements, it will check just the pointer if
-`:smart` mode is configured or fail if `:compare_data` is set.
-
-* `void func(void)` => (nothing. In fact, an additional function is only generated if the params list contains pointers)
-* `void func(ptr * param, other)` => `void func_ExpectWithArray(ptr* param, int param_depth, other)`
-* `retval func(void)` => (nothing. In fact, an additional function is only generated if the params list contains pointers)
-* `retval func(other, ptr* param)` => `void func_ExpectWithArrayAndReturn(other, ptr* param, int param_depth, retval_to_return)`
-
-
-Ignore:
--------
-
-Maybe you don't care about the number of times a particular function is called or
-the actual arguments it is called with. In that case, you want to use Ignore. Ignore
-only needs to be called once per test. It will then ignore any further calls to that
-particular mock. The IgnoreAndReturn works similarly, except that it has the added
-benefit of knowing what to return when that call happens. If the mock is called more
-times than IgnoreAndReturn was called, it will keep returning the last value without
-complaint. If it's called less times, it will also ignore that. You SAID you didn't
-care how many times it was called, right?
-
-* `void func(void)` => `void func_Ignore(void)`
-* `void func(params)` => `void func_Ignore(void)`
-* `retval func(void)` => `void func_IgnoreAndReturn(retval_to_return)`
-* `retval func(params)` => `void func_IgnoreAndReturn(retval_to_return)`
-
-
-Ignore Arg:
-------------
-
-Maybe you overall want to use Expect and its similar variations, but you don't care
-what is passed to a particular argument. This is particularly useful when that argument
-is a pointer to a value that is supposed to be filled in by the function. You don't want
-to use ExpectAnyArgs, because you still care about the other arguments. Instead, before
-any of your Expect calls are made, you can call this function. It tells CMock to ignore
-a particular argument for the rest of this test, for this mock function.
-
-* `void func(params)` => `void func_IgnoreArg_paramName(void)`
-
-
-ReturnThruPtr:
---------------
-
-Another option which operates on a particular argument of a function is the ReturnThruPtr
-plugin. For every argument that resembles a pointer or reference, CMock generates an
-instance of this function. Just as the AndReturn functions support injecting one or more
-return values into a queue, this function lets you specify one or more return values which
-are queued up and copied into the space being pointed at each time the mock is called.
-
-* `void func(param1)` => `void func_ReturnThruPtr_paramName(val_to_return)`
-* => `void func_ReturnArrayThruPtr_paramName(cal_to_return, len)`
-* => `void func_ReturnMemThruPtr_paramName(val_to_return, size)`
-
-
-Callback:
----------
-
-If all those other options don't work, and you really need to do something custom, you
-still have a choice. As soon as you stub a callback in a test, it will call the callback
-whenever the mock is encountered and return the retval returned from the callback (if any)
-instead of performing the usual expect checks. It can be configured to check the arguments
-first (like expects) or just jump directly to the callback.
-
-* `void func(void)` => `void func_StubWithCallback(CMOCK_func_CALLBACK callback)`
-where `CMOCK_func_CALLBACK` looks like: `void func(int NumCalls)`
-* `void func(params)` => `void func_StubWithCallback(CMOCK_func_CALLBACK callback)`
-where `CMOCK_func_CALLBACK` looks like: `void func(params, int NumCalls)`
-* `retval func(void)` => `void func_StubWithCallback(CMOCK_func_CALLBACK callback)`
-where `CMOCK_func_CALLBACK` looks like: `retval func(int NumCalls)`
-* `retval func(params)` => `void func_StubWithCallback(CMOCK_func_CALLBACK callback)`
-where `CMOCK_func_CALLBACK` looks like: `retval func(params, int NumCalls)`
-
-
-Cexception:
------------
-
-Finally, if you are using Cexception for error handling, you can use this to throw errors
-from inside mocks. Like Expects, it remembers which call was supposed to throw the error,
-and it still checks parameters first.
-
-* `void func(void)` => `void func_ExpectAndThrow(value_to_throw)`
-* `void func(params)` => `void func_ExpectAndThrow(expected_params, value_to_throw)`
-* `retval func(void)` => `void func_ExpectAndThrow(value_to_throw)`
-* `retval func(params)` => `void func_ExpectAndThrow(expected_params, value_to_throw)`
-
-
-
-Running CMock
-=============
-
-CMock is a Ruby script and class. You can therefore use it directly
-from the command line, or include it in your own scripts or rakefiles.
-
-
-Mocking from the Command Line
------------------------------
-
-After unpacking CMock, you will find cmock.rb in the 'lib' directory.
-This is the file that you want to run. It takes a list of header files
-to be mocked, as well as an optional yaml file for a more detailed
-configuration (see config options below).
-
-For example, this will create three mocks using the configuration
-specified in MyConfig.yml:
-
-    ruby cmock.rb -oMyConfig.yml super.h duper.h awesome.h
-
-And this will create two mocks using the default configuration:
-
-    ruby cmock.rb ../mocking/stuff/is/fun.h ../try/it/yourself.h
-
-
-Mocking From Scripts or Rake
-----------------------------
-
-CMock can be used directly from your own scripts or from a rakefile.
-Start by including cmock.rb, then create an instance of CMock.
-When you create your instance, you may initialize it in one of
-three ways.
-
-You may specify nothing, allowing it to run with default settings:
-
-    require 'cmock.rb'
-    cmock = CMock.new
-
-You may specify a YAML file containing the configuration options
-you desire:
-
-    cmock = CMock.new('../MyConfig.yml')
-
-You may specify the options explicitly:
-
-    cmock = Cmock.new(:plugins => [:cexception, :ignore], :mock_path => 'my/mocks/')
-
-
-Config Options:
----------------
-
-The following configuration options can be specified in the
-yaml file or directly when instantiating.
-
-Passed as Ruby, they look like this:
-
-        { :attributes => [“__funky�, “__intrinsic�], :when_ptr => :compare }
-
-Defined in the yaml file, they look more like this:
-
-        :cmock:
-          :attributes:
-            - __funky
-            - __intrinsic
-          :when_ptr: :compare
-
-In all cases, you can just include the things that you want to override
-from the defaults. We've tried to specify what the defaults are below.
-
-* `:attributes`:
-  These are attributes that CMock should ignore for you for testing
-  purposes. Custom compiler extensions and externs are handy things to
-  put here. If your compiler is choking on some extended syntax, this
-  is often a good place to look.
-
-  * defaults: ['__ramfunc', '__irq', '__fiq', 'register', 'extern']
-  * **note:** this option will reinsert these attributes onto the mock's calls.
-    If that isn't what you are looking for, check out :strippables.
-
-* `:c_calling_conventions`:
-  Similarly, CMock may need to understand which C calling conventions
-  might show up in your codebase. If it encounters something it doesn't
-  recognize, it's not going to mock it. We have the most common covered,
-  but there are many compilers out there, and therefore many other options.
-
-  * defaults: ['__stdcall', '__cdecl', '__fastcall']
-  * **note:** this option will reinsert these attributes onto the mock's calls.
-    If that isn't what you are looking for, check out :strippables.
-
-* `:callback_after_arg_check`:
-  Tell `:callback` plugin to do the normal argument checking **before** it
-  calls the callback function by setting this to true. When false, the
-  callback function is called **instead** of the argument verification.
-
-  * default: false
-
-* `:callback_include_count`:
-  Tell `:callback` plugin to include an extra parameter to specify the
-  number of times the callback has been called. If set to false, the
-  callback has the same interface as the mocked function. This can be
-  handy when you're wanting to use callback as a stub.
-
-  * default: true
-
-* `:cexception_include`:
-  Tell `:cexception` plugin where to find CException.h... You only need to
-  define this if it's not in your build path already... which it usually
-  will be for the purpose of your builds.
-
-  * default: *nil*
-
-* `:enforce_strict_ordering`:
-  CMock always enforces the order that you call a particular function,
-  so if you expect GrabNabber(int size) to be called three times, it
-  will verify that the sizes are in the order you specified. You might
-  *also* want to make sure that all different functions are called in a
-  particular order. If so, set this to true.
-
-  * default: false
-
-* `:framework`:
-  Currently the only option is `:unity.` Eventually if we support other
-  unity test frameworks (or if you write one for us), they'll get added
-  here.
-
-  : default: :unity
-
-* `:includes`:
-  An array of additional include files which should be added to the
-  mocks. Useful for global types and definitions used in your project.
-  There are more specific versions if you care WHERE in the mock files
-  the includes get placed. You can define any or all of these options.
-
-  * `:includes`
-  * `:includes_h_pre_orig_header`
-  * `:includes_h_post_orig_header`
-  * `:includes_c_pre_header`
-  * `:includes_c_post_header`
-  * default: nil #for all 5 options
-
-* `:memcmp_if_unknown`:
-  C developers create a lot of types, either through typedef or preprocessor
-  macros. CMock isn't going to automatically know what you were thinking all
-  the time (though it tries its best). If it comes across a type it doesn't
-  recognize, you have a choice on how you want it to handle it. It can either
-  perform a raw memory comparison and report any differences, or it can fail
-  with a meaningful message. Either way, this feature will only happen after
-  all other mechanisms have failed (The thing encountered isn't a standard
-  type. It isn't in the :treat_as list. It isn't in a custom unity_helper).
-
-  * default: true
-
-* `:mock_path`:
-  The directory where you would like the mock files generated to be
-  placed.
-
-  * default: mocks
-
-* `:mock_prefix`:
-  The prefix to prepend to your mock files. For example, if it's “Mock�, a file
-  “USART.h� will get a mock called “MockUSART.c�. This CAN be used with a suffix
-  at the same time.
-
-  * default: Mock
-
-* `:mock_suffix`:
-  The suffix to append to your mock files. For example, it it's "_Mock", a file
-  "USART.h" will get a mock called "USART_Mock.h". This CAN be used with a prefix
-  at the same time.
-
-  * default: ""
-
-* `:plugins`:
-  An array of which plugins to enable. ':expect' is always active. Also
-  available currently:
-
-  * `:ignore`
-  * `:ignore_arg`
-  * `:expect_any_args`
-  * `:array`
-  * `:cexception`
-  * `:callback`
-  * `:return_thru_ptr`
-
-* `:strippables`:
-  An array containing a list of items to remove from the header
-  before deciding what should be mocked. This can be something simple
-  like a compiler extension CMock wouldn't recognize, or could be a
-  regex to reject certain function name patterns. This is a great way to
-  get rid of compiler extensions when your test compiler doesn't support
-  them. For example, use `:strippables: ['(?:functionName\s*\(+.*?\)+)']`
-  to prevent a function `functionName` from being mocked. By default, it
-  is ignoring all gcc attribute extensions.
-
-  * default: ['(?:__attribute__\s*\(+.*?\)+)']
-
-* `:subdir`:
-  This is a relative subdirectory for your mocks.  Set this to e.g. "sys" in
-  order to create a mock for `sys/types.h` in `(:mock_path)/sys/`.
-
-  * default: ""
-
-* `:treat_as`:
-  The `:treat_as` list is a shortcut for when you have created typedefs
-  of standard types. Why create a custom unity helper for UINT16 when
-  the unity function TEST_ASSERT_EQUAL_HEX16 will work just perfectly?
-  Just add 'UINT16' => 'HEX16' to your list (actually, don't. We already
-  did that one for you). Maybe you have a type that is a pointer to an
-  array of unsigned characters? No problem, just add 'UINT8_T*' =>
-  'HEX8*'
-
-  * NOTE: unlike the other options, your specifications MERGE with the
-    default list. Therefore, if you want to override something, you must
-    reassign it to something else (or to *nil* if you don't want it)
-
-  * default:
-    * 'int': 'INT'
-    * 'char': 'INT8'
-    * 'short': 'INT16'
-    * 'long': 'INT'
-    * 'int8': 'INT8'
-    * 'int16': 'INT16'
-    * 'int32': 'INT'
-    * 'int8_t': 'INT8'
-    * 'int16_t': 'INT16'
-    * 'int32_t': 'INT'
-    * 'INT8_T': 'INT8'
-    * 'INT16_T': 'INT16'
-    * 'INT32_T': 'INT'
-    * 'bool': 'INT'
-    * 'bool_t': 'INT'
-    * 'BOOL': 'INT'
-    * 'BOOL_T': 'INT'
-    * 'unsigned int': 'HEX32'
-    * 'unsigned long': 'HEX32'
-    * 'uint32': 'HEX32'
-    * 'uint32_t': 'HEX32'
-    * 'UINT32': 'HEX32'
-    * 'UINT32_T': 'HEX32'
-    * 'void*': 'HEX8_ARRAY'
-    * 'unsigned short': 'HEX16'
-    * 'uint16': 'HEX16'
-    * 'uint16_t': 'HEX16'
-    * 'UINT16': 'HEX16'
-    * 'UINT16_T': 'HEX16'
-    * 'unsigned char': 'HEX8'
-    * 'uint8': 'HEX8'
-    * 'uint8_t': 'HEX8'
-    * 'UINT8': 'HEX8'
-    * 'UINT8_T': 'HEX8'
-    * 'char*': 'STRING'
-    * 'pCHAR': 'STRING'
-    * 'cstring': 'STRING'
-    * 'CSTRING': 'STRING'
-    * 'float': 'FLOAT'
-    * 'double': 'FLOAT'
-
-* `:treat_as_void`:
-  We've seen "fun" legacy systems typedef 'void' with a custom type,
-  like MY_VOID. Add any instances of those to this list to help CMock
-  understand how to deal with your code.
-
-  * default: []
-
-* `:treat_externs`:
-  This specifies how you want CMock to handle functions that have been
-  marked as extern in the header file. Should it mock them?
-
-  * `:include` will mock externed functions
-  * `:exclude` will ignore externed functions (default).
-
-* `:unity_helper_path`:
-  If you have created a header with your own extensions to unity to
-  handle your own types, you can set this argument to that path. CMock
-  will then automagically pull in your helpers and use them. The only
-  trick is that you make sure you follow the naming convention:
-  `UNITY_TEST_ASSERT_EQUAL_YourType`. If it finds macros of the right
-  shape that match that pattern, it'll use them.
-
-  * default: []
-
-* `:verbosity`:
-  How loud should CMock be?
-
-  * 0 for errors only
-  * 1 for errors and warnings
-  * 2 for normal (default)
-  * 3 for verbose
-
-* `:weak`:
-  When set this to some value, the generated mocks are defined as weak
-  symbols using the configured format. This allows them to be overridden
-  in particular tests.
-
-  * Set to '__attribute ((weak))' for weak mocks when using GCC.
-  * Set to any non-empty string for weak mocks when using IAR.
-  * default: ""
-
-* `:when_no_prototypes`:
-  When you give CMock a header file and ask it to create a mock out of
-  it, it usually contains function prototypes (otherwise what was the
-  point?). You can control what happens when this isn't true. You can
-  set this to `:warn,` `:ignore,` or `:error`
-
-  * default: :warn
-
-* `:when_ptr`:
-  You can customize how CMock deals with pointers (c strings result in
-  string comparisons... we're talking about **other** pointers here). Your
-  options are `:compare_ptr` to just verify the pointers are the same,
-  `:compare_data` or `:smart` to verify that the data is the same.
-  `:compare_data` and `:smart` behaviors will change slightly based on
-  if you have the array plugin enabled. By default, they compare a
-  single element of what is being pointed to. So if you have a pointer
-  to a struct called ORGAN_T, it will compare one ORGAN_T (whatever that
-  is).
-
-  * default: :smart
-
-* `:fail_on_unexpected_calls`:
-  By default, CMock will fail a test if a mock is called without _Expect and _Ignore
-  called first. While this forces test writers to be more explicit in their expectations,
-  it can clutter tests with _Expect or _Ignore calls for functions which are not the focus
-  of the test. While this is a good indicator that this module should be refactored, some
-  users are not fans of the additional noise.
-
-  Therefore, :fail_on_unexpected_calls can be set to false to force all mocks to start with
-  the assumption that they are operating as _Ignore unless otherwise specified.
-
-  * default: true
-  * **note:**
-    If this option is disabled, the mocked functions will return
-    a default value (0) when called (and only if they have to return something of course).
-
-
-Compiled Options:
------------------
-
-A number of #defines also exist for customizing the cmock experience.
-Feel free to pass these into your compiler or whatever is most
-convenient. CMock will otherwise do its best to guess what you want
-based on other settings, particularly Unity's settings.
-
-* `CMOCK_MEM_STATIC` or `CMOCK_MEM_DYNAMIC`
-  Define one of these to determine if you want to dynamically add
-  memory during tests as required from the heap. If static, you
-  can control the total footprint of Cmock. If dynamic, you will
-  need to make sure you make some heap space available for Cmock.
-
-* `CMOCK_MEM_SIZE`
-  In static mode this is the total amount of memory you are allocating
-  to Cmock. In Dynamic mode this is the size of each chunk allocated
-  at once (larger numbers grab more memory but require less mallocs).
-
-* `CMOCK_MEM_ALIGN`
-  The way to align your data to. Not everything is as flexible as
-  a PC, as most embedded designers know. This defaults to 2, meaning
-  align to the closest 2^2 -> 4 bytes (32 bits). You can turn off alignment
-  by setting 0, force alignment to the closest uint16 with 1 or even
-  to the closest uint64 with 3.
-
-* `CMOCK_MEM_PTR_AS_INT`
-  This is used internally to hold pointers... it needs to be big
-  enough. On most processors a pointer is the same as an unsigned
-  long... but maybe that's not true for yours?
-
-* `CMOCK_MEM_INDEX_TYPE`
-  This needs to be something big enough to point anywhere in Cmock's
-  memory space... usually it's an unsigned int.
-
-Examples
-========
-
-You can look in the [examples directory](/examples/) for a couple of examples on how
-you might tool CMock into your build process. You may also want to consider
-using [Ceedling](https://throwtheswitch.org/ceedling). Please note that
-these examples are meant to show how the build process works. They have
-failing tests ON PURPOSE to show what that would look like. Don't be alarmed. ;)
-
diff --git a/test/vendor/ceedling/docs/CeedlingPacket.md b/test/vendor/ceedling/docs/CeedlingPacket.md
deleted file mode 100644
index 88cd02025..000000000
--- a/test/vendor/ceedling/docs/CeedlingPacket.md
+++ /dev/null
@@ -1,2060 +0,0 @@
-[All code is copyright © 2010-2012 Ceedling Project
-by Mike Karlesky, Mark VanderVoord, and Greg Williams.
-
-This Documentation Is Released Under a
-Creative Commons 3.0 Attribution Share-Alike License]
-
-What the What?
-
-Assembling build environments for C projects - especially with
-automated unit tests - is a pain. Whether it's Make or Rake or Premake
-or what-have-you, set up with an all-purpose build environment
-tool is tedious and requires considerable glue code to pull together
-the necessary tools and libraries. Ceedling allows you to generate
-an entire test and build environment for a C project from a single
-YAML configuration file. Ceedling is written in Ruby and works
-with the Rake build tool plus other goodness like Unity and CMock
-- the unit testing and mocking frameworks for C. Ceedling and
-its complementary tools can support the tiniest of embedded
-processors, the beefiest 64 bit power houses available, and
-everything in between.
-
-For a build project including unit tests and using the default
-toolchain gcc, the configuration file could be as simple as this:
-
-```yaml
-:project:
-  :build_root: project/build/
-  :release_build: TRUE
-
-:paths:
-  :test:
-    - tests/**
-  :source:
-    - source/**
-```
-
-From the command line, to build the release version of your project,
-you would simply run `ceedling release`. To run all your unit tests,
-you would run `ceedling test:all`. That's it!
-
-Of course, many more advanced options allow you to configure
-your project with a variety of features to meet a variety of needs.
-Ceedling can work with practically any command line toolchain
-and directory structure – all by way of the configuration file.
-Further, because Ceedling piggy backs on Rake, you can add your
-own Rake tasks to accomplish project tasks outside of testing
-and release builds. A facility for plugins also allows you to
-extend Ceedling's capabilities for needs such as custom code
-metrics reporting and coverage testing.
-
-What's with this Name?
-
-Glad you asked. Ceedling is tailored for unit tested C projects
-and is built upon / around Rake (Rake is a Make replacement implemented
-in the Ruby scripting language). So, we've got C, our Rake, and
-the fertile soil of a build environment in which to grow and tend
-your project and its unit tests. Ta da - _Ceedling_.
-
-What Do You Mean "tailored for unit tested C projects"?
-
-Well, we like to write unit tests for our C code to make it lean and
-mean (that whole [Test-Driven Development][tdd]
-thing). Along the way, this style of writing C code spawned two
-tools to make the job easier: a unit test framework for C called
-_Unity_ and a mocking library called _CMock_. And, though it's
-not directly related to testing, a C framework for exception
-handling called _CException_ also came along.
-
-[tdd]: http://en.wikipedia.org/wiki/Test-driven_development
-
-These tools and frameworks are great, but they require quite
-a bit of environment support to pull them all together in a convenient,
-usable fashion. We started off with Rakefiles to assemble everything.
-These ended up being quite complicated and had to be hand-edited
-or created anew for each new project. Ceedling replaces all that
-tedium and rework with a configuration file that ties everything
-together.
-
-Though Ceedling is tailored for unit testing, it can also go right ahead
-and build your final binary release artifact for you as well. Or,
-Ceedling and your tests can live alongside your existing release build
-setup. That said, Ceedling is more powerful as a unit test build
-environment than it is a general purpose release build environment;
-complicated projects including separate bootloaders or multiple library
-builds, etc. are not its strong suit.
-
-Hold on. Back up. Ruby? Rake? YAML? Unity? CMock? CException?
-
-Seem overwhelming? It's not bad at all, and for the benefits tests
-bring us, it's all worth it.
-
-[Ruby][] is a handy scripting
-language like Perl or Python. It's a modern, full featured language
-that happens to be quite handy for accomplishing tasks like code
-generation or automating one's workflow while developing in
-a compiled language such as C.
-
-[Ruby]: http://www.ruby-lang.org/en/
-
-[Rake][] is a utility written in Ruby
-for accomplishing dependency tracking and task automation
-common to building software. It's a modern, more flexible replacement
-for [Make][]).
-Rakefiles are Ruby files, but they contain build targets similar
-in nature to that of Makefiles (but you can also run Ruby code in
-your Rakefile).
-
-[Rake]: http://rubyrake.org/
-[Make]: http://en.wikipedia.org/wiki/Make_(software)
-
-[YAML][] is a "human friendly data serialization standard for all
-programming languages." It's kinda like a markup language, but don't
-call it that. With a YAML library, you can [serialize][] data structures
-to and from the file system in a textual, human readable form. Ceedling
-uses a serialized data structure as its configuration input.
-
-[YAML]: http://en.wikipedia.org/wiki/Yaml
-[serialize]: http://en.wikipedia.org/wiki/Serialization
-
-[Unity] is a [unit test framework][test] for C. It provides facilities
-for test assertions, executing tests, and collecting / reporting test
-results. Unity derives its name from its implementation in a single C
-source file (plus two C header files) and from the nature of its
-implementation - Unity will build in any C toolchain and is configurable
-for even the very minimalist of processors.
-
-[Unity]: http://github.com/ThrowTheSwitch/Unity
-[test]: http://en.wikipedia.org/wiki/Unit_testing
-
-[CMock] is a tool written in Ruby able to generate entire
-[mock functions][mock] in C code from a given C header file. Mock
-functions are invaluable in [interaction-based unit testing][ut].
-CMock's generated C code uses Unity.
-
-[CMock]: http://github.com/ThrowTheSwitch/CMock
-[mock]: http://en.wikipedia.org/wiki/Mock_object
-[ut]: http://martinfowler.com/articles/mocksArentStubs.html
-
-[CException] is a C source and header file that provide a simple
-[exception mechanism][exn] for C by way of wrapping up the
-[setjmp / longjmp][setjmp] standard library calls. Exceptions are a much
-cleaner and preferable alternative to managing and passing error codes
-up your return call trace.
-
-[CException]: http://github.com/ThrowTheSwitch/CException
-[exn]: http://en.wikipedia.org/wiki/Exception_handling
-[setjmp]: http://en.wikipedia.org/wiki/Setjmp.h
-
-Notes
------
-
-* YAML support is included with Ruby - requires no special installation
-  or configuration.
-
-* Unity, CMock, and CException are bundled with Ceedling, and
-  Ceedling is designed to glue them all together for your project
-  as seamlessly as possible.
-
-
-Installation & Setup: What Exactly Do I Need to Get Started?
-------------------------------------------------------------
-
-As a [Ruby gem](http://docs.rubygems.org/read/chapter/1):
-
-1. [Download and install Ruby](http://www.ruby-lang.org/en/downloads/)
-
-2. Use Ruby's command line gem package manager to install Ceedling:
-   `gem install ceedling`
-   (Unity, CMock, and CException come along with Ceedling for free)
-
-3. Execute Ceedling at command line to create example project
-   or an empty Ceedling project in your filesystem (executing
-   `ceedling help` first is, well, helpful).
-
-Gem install notes:
-
-1. Steps 1-2 are a one time affair for your local environment.
-   When steps 1-2 are completed once, only step 3 is needed for
-   each new project.
-
-
-
-General notes:
-
-1. Certain advanced features of Ceedling rely on gcc and cpp
-   as preprocessing tools. In most *nix systems, these tools
-   are already available. For Windows environments, we recommend
-   the [mingw project](http://www.mingw.org/) (Minimalist
-   GNU for Windows). This represents an optional, additional
-   setup / installation step to complement the list above. Upon
-   installing mingw ensure your system path is updated or set
-   [:environment][:path] in your `project.yml` file (see
-   environment section later in this document).
-
-2. To use a project file name other than the default `project.yml`
-   or place the project file in a directory other than the one
-   in which you'll run Rake, create an environment variable
-   `CEEDLING_MAIN_PROJECT_FILE` with your desired project
-   file path.
-
-3. To better understand Rake conventions, Rake execution,
-   and Rakefiles, consult the [Rake tutorial, examples, and
-   user guide](http://rubyrake.org/).
-
-4. When using Ceedling in Windows environments, a test file name may 
-   not include the sequences “patch� or “setup�. The Windows Installer 
-   Detection Technology (part of UAC), requires administrator 
-   privileges to execute file names with these strings.
-
-
-
-Now What? How Do I Make It GO?
-------------------------------
-
-We're getting a little ahead of ourselves here, but it's good
-context on how to drive this bus. Everything is done via the command
-line. We'll cover conventions and how to actually configure
-your project in later sections.
-
-To run tests, build your release artifact, etc., you will be interacting
-with Rake on the command line. Ceedling works with Rake to present
-you with named tasks that coordinate the file generation and
-build steps needed to accomplish something useful. You can also
-add your own independent Rake tasks or create plugins to extend
-Ceedling (more on this later).
-
-
-* `ceedling [no arguments]`:
-
-  Run the default Rake task (conveniently recognized by the name default
-  by Rake). Neither Rake nor Ceedling provide a default task. Rake will
-  abort if run without arguments when no default task is defined. You can
-  conveniently define a default task in the Rakefile discussed in the
-  preceding setup & installation section of this document.
-
-* `ceedling -T`:
-
-  List all available Rake tasks with descriptions (Rake tasks without
-  descriptions are not listed). -T is a command line switch for Rake and
-  not the same as tasks that follow.
-
-* `ceedling <tasks...> --trace`:
-
-  For advanced users troubleshooting a confusing build error, debug
-  Ceedling or a plugin, --trace provides a stack trace of dependencies
-  walked during task execution and any Ruby failures along the way. Note
-  that --trace is a command line switch for Rake and is not the same as
-  tasks that follow.
-
-* `ceedling environment`:
-
-  List all configured environment variable names and string values. This
-  task is helpful in verifying the evaluatio of any Ruby expressions in
-  the [:environment] section of your config file.`: Note: Ceedling may
-  set some convenience environment variables by default.
-
-* `ceedling paths:*`:
-
-  List all paths collected from [:paths] entries in your YAML config
-  file where * is the name of any section contained in [:paths]. This
-  task is helpful in verifying the expansion of path wildcards / globs
-  specified in the [:paths] section of your config file.
-
-* `ceedling files:assembly`
-* `ceedling files:header`
-* `ceedling files:source`
-* `ceedling files:test`
-
-  List all files and file counts collected from the relevant search
-  paths specified by the [:paths] entries of your YAML config file. The
-  files:assembly task will only be available if assembly support is
-  enabled in the [:release_build] section of your configuration file.
-
-* `ceedling options:*`:
-
-  Load and merge configuration settings into the main project
-  configuration. Each task is named after a *.yml file found in the
-  configured options directory. See documentation for the configuration
-  setting [:project][:options_path] and for options files in advanced
-  topics.
-
-* `ceedling test:all`:
-
-  Run all unit tests (rebuilding anything that's changed along the way).
-
-* `ceedling test:delta`:
-
-  Run only those unit tests for which the source or test files have
-  changed (i.e. incremental build). Note: with the
-  [:project][:use_test_preprocessor] configuration file option set,
-  runner files are always regenerated limiting the total efficiency this
-  text execution option can afford.
-
-* `ceedling test:*`:
-
-  Execute the named test file or the named source file that has an
-  accompanying test. No path. Examples: ceedling test:foo.c or ceed
-  test:test_foo.c
-
-* `ceedling test:pattern[*]`:
-
-  Execute any tests whose name and/or path match the regular expression
-  pattern (case sensitive). Example: ceedling "test:pattern[(I|i)nit]" will
-  execute all tests named for initialization testing. Note: quotes may
-  be necessary around the ceedling parameter to distinguish regex characters
-  from command line operators.
-
-* `ceedling test:path[*]`:
-
-  Execute any tests whose path contains the given string (case
-  sensitive). Example: ceedling test:path[foo/bar] will execute all tests
-  whose path contains foo/bar. Note: both directory separator characters
-  / and \ are valid.
-
-* `ceedling release`:
-
-  Build all source into a release artifact (if the release build option
-  is configured).
-
-* `ceedling release:compile:*`:
-
-  Sometimes you just need to compile a single file dagnabit. Example:
-  ceedling release:compile:foo.c
-
-* `ceedling release:assemble:*`:
-
-  Sometimes you just need to assemble a single file doggonit. Example:
-  ceedling release:assemble:foo.s
-
-* `ceedling module:create[Filename]`:
-* `ceedling module:create[<Path:>Filename]`:
-
-  It's often helpful to create a file automatically. What's better than
-  that? Creating a source file, a header file, and a corresponding test
-  file all in one step!
-
-  There are also patterns which can be specified to automatically generate
-  a bunch of files. Try `ceedling module:create[Poodles,mch]` for example!
-
-  The module generator has several options you can configure.
-  F.e. Generating the source/header/test file in a subdirectory (by adding <Path> when calling module:create).
-  For more info, refer to the [Module Generator](https://github.com/ThrowTheSwitch/Ceedling/blob/master/docs/CeedlingPacket.md#module-generator) section.
-
-* `ceedling logging <tasks...>`:
-
-  Enable logging to <build path>/logs. Must come before test and release
-  tasks to log their steps and output. Log names are a concatenation of
-  project, user, and option files loaded. User and option files are
-  documented in the advanced topics section of this document.
-
-* `ceedling verbosity[x] <tasks...>`:
-
-  Change the default verbosity level. [x] ranges from 0 (quiet) to 4
-  (obnoxious). Level [3] is the default. The verbosity task must precede
-  all tasks in the command line list for which output is desired to be
-  seen. Verbosity settings are generally most meaningful in conjunction
-  with test and release tasks.
-
-* `ceedling summary`:
-
-  If plugins are enabled, this task will execute the summary method of
-  any plugins supporting it. This task is intended to provide a quick
-  roundup of build artifact metrics without re-running any part of the
-  build.
-
-* `ceedling clean`:
-
-  Deletes all toolchain binary artifacts (object files, executables),
-  test results, and any temporary files. Clean produces no output at the
-  command line unless verbosity has been set to an appreciable level.
-
-* `ceedling clobber`:
-
-  Extends clean task's behavior to also remove generated files: test
-  runners, mocks, preprocessor output. Clobber produces no output at the
-  command line unless verbosity has been set to an appreciable level.
-
-To better understand Rake conventions, Rake execution, and
-Rakefiles, consult the [Rake tutorial, examples, and user guide][guide].
-
-[guide]: http://rubyrake.org/
-
-At present, none of Ceedling's commands provide persistence.
-That is, they must each be specified at the command line each time
-they are needed. For instance, Ceedling's verbosity command
-only affects output at the time it's run.
-
-Individual test and release file tasks
-are not listed in `-T` output. Because so many files may be present
-it's unwieldy to list them all.
-
-Multiple rake tasks can be executed at the command line (order
-is executed as provided). For example, `ceed
-clobber test:all release` will removed all generated files;
-build and run all tests; and then build all source - in that order.
-If any Rake task fails along the way, execution halts before the
-next task.
-
-The `clobber` task removes certain build directories in the
-course of deleting generated files. In general, it's best not
-to add to source control any Ceedling generated directories
-below the root of your top-level build directory. That is, leave
-anything Ceedling & its accompanying tools generate out of source
-control (but go ahead and add the top-level build directory that
-holds all that stuff). Also, since Ceedling is pretty smart about
-what it rebuilds and regenerates, you needn't clobber often.
-
-Important Conventions
-=====================
-
-Directory Structure, Filenames & Extensions
--------------------------------------------
-
-Much of Ceedling's functionality is driven by collecting files
-matching certain patterns inside the paths it's configured
-to search. See the documentation for the [:extensions] section
-of your configuration file (found later in this document) to
-configure the file extensions Ceedling uses to match and collect
-files. Test file naming is covered later in this section.
-
-Test files and source files must be segregated by directories.
-Any directory structure will do. Tests can be held in subdirectories
-within source directories, or tests and source directories
-can be wholly separated at the top of your project's directory
-tree.
-
-Search Path Order
------------------
-
-When Ceedling searches for files (e.g. looking for header files
-to mock) or when it provides search paths to any of the default
-gcc toolchain executables, it organizes / prioritizes its search
-paths. The order is always: test paths, support paths, source
-paths, and then include paths. This can be useful, for instance,
-in certain testing scenarios where we desire Ceedling or a compiler
-to find a stand-in header file in our support directory before
-the actual source header file of the same name.
-
-This convention only holds when Ceedling is using its default
-tool configurations and / or when tests are involved. If you define
-your own tools in the configuration file (see the [:tools] section
-documented later in this here document), you have complete control
-over what directories are searched and in what order. Further,
-test and support directories are only searched when appropriate.
-That is, when running a release build, test and support directories
-are not used at all.
-
-Source Files & Binary Release Artifacts
----------------------------------------
-
-Your binary release artifact results from the compilation and
-linking of all source files Ceedling finds in the specified source
-directories. At present only source files with a single (configurable)
-extension are recognized. That is, *.c and *.cc files will not
-both be recognized - only one or the other. See the configuration
-options and defaults in the documentation for the [:extensions]
-sections of your configuration file (found later in this document).
-
-Test Files & Executable Test Fixtures
--------------------------------------
-
-Ceedling builds each individual test file with its accompanying
-source file(s) into a single, monolithic test fixture executable.
-Test files are recognized by a naming convention: a (configurable)
-prefix such as "`test_`" in the file name with the same file extension
-as used by your C source files. See the configuration options
-and defaults in the documentation for the [:project] and [:extensions]
-sections of your configuration file (found later in this document).
-Depending on your configuration options, Ceedling can recognize
-a variety of test file naming patterns in your test search paths.
-For example: `test_some_super_functionality.c`, `TestYourSourceFile.cc`,
-or `testing_MyAwesomeCode.C` could each be valid test file
-names. Note, however, that Ceedling can recognize only one test
-file naming convention per project.
-
-Ceedling knows what files to compile and link into each individual
-test executable by way of the #include list contained in each
-test file. Any C source files in the configured search directories
-that correspond to the header files included in a test file will
-be compiled and linked into the resulting test fixture executable.
-From this same #include list, Ceedling knows which files to mock
-and compile and link into the test executable (if you use mocks
-in your tests). That was a lot of clauses and information in a very
-few sentences; the example that follows in a bit will make it clearer.
-
-By naming your test functions according to convention, Ceedling
-will extract and collect into a runner C file calls to all your
-test case functions. This runner file handles all the execution
-minutiae so that your test file can be quite simple and so that
-you never forget to wire up a test function to be executed. In this
-generated runner lives the `main()` entry point for the resulting
-test executable. There are no configuration options for the
-naming convention of your test case functions. A test case function
-signature must have these three elements: void return, void
-parameter list, and the function name prepended with lowercase
-"`test`". In other words, a test function signature should look
-like this: `void test``[any name you like]``(void)`.
-
-A commented sample test file follows on the next page. Also, see
-the sample project contained in the Ceedling documentation
-bundle.
-
-```c
-// test_foo.c -----------------------------------------------
-#include "unity.h"     // compile/link in Unity test framework
-#include "types.h"     // header file with no *.c file -- no compilation/linking
-#include "foo.h"       // source file foo.c under test
-#include "mock_bar.h"  // bar.h will be found and mocked as mock_bar.c + compiled/linked in;
-                       // foo.c includes bar.h and uses functions declared in it
-#include "mock_baz.h"  // baz.h will be found and mocked as mock_baz.c + compiled/linked in
-                       // foo.c includes baz.h and uses functions declared in it
-
-
-void setUp(void) {}    // every test file requires this function;
-                       // setUp() is called by the generated runner before each test case function
-
-void tearDown(void) {} // every test file requires this function;
-                       // tearDown() is called by the generated runner before each test case function
-
-// a test case function
-void test_Foo_Function1_should_Call_Bar_AndGrill(void)
-{
-    Bar_AndGrill_Expect();                    // setup function from mock_bar.c that instructs our
-                                              // framework to expect Bar_AndGrill() to be called once
-    TEST_ASSERT_EQUAL(0xFF, Foo_Function1()); // assertion provided by Unity
-                                              // Foo_Function1() calls Bar_AndGrill() & returns a byte
-}
-
-// another test case function
-void test_Foo_Function2_should_Call_Baz_Tec(void)
-{
-    Baz_Tec_ExpectAnd_Return(1);       // setup function provided by mock_baz.c that instructs our
-                                       // framework to expect Baz_Tec() to be called once and return 1
-    TEST_ASSERT_TRUE(Foo_Function2()); // assertion provided by Unity
-}
-
-// end of test_foo.c ----------------------------------------
-```
-
-From the test file specified above Ceedling will generate `test_foo_runner.c`;
-this runner file will contain `main()` and call both of the example
-test case functions.
-
-The final test executable will be `test_foo.exe` (for Windows
-machines or `test_foo.out` for *nix systems - depending on default
-or configured file extensions). Based on the #include list above,
-the test executable will be the output of the linker having processed
-`unity.o`, `foo.o`, `mock_bar.o`, `mock_baz.o`, `test_foo.o`,
-and `test_foo_runner.o`. Ceedling finds the files, generates
-mocks, generates a runner, compiles all the files, and links
-everything into the test executable. Ceedling will then run
-the test executable and collect test results from it to be reported
-to the developer at the command line.
-
-For more on the assertions and mocks shown, consult the documentation
-for Unity and CMock.
-
-The Magic of Dependency Tracking
---------------------------------
-
-Ceedling is pretty smart in using Rake to build up your project's
-dependencies. This means that Ceedling automagically rebuilds
-all the appropriate files in your project when necessary: when
-your configuration changes, Ceedling or any of the other tools
-are updated, or your source or test files change. For instance,
-if you modify a header file that is mocked, Ceedling will ensure
-that the mock is regenerated and all tests that use that mock are
-rebuilt and re-run when you initiate a relevant testing task.
-When you see things rebuilding, it's for a good reason. Ceedling
-attempts to regenerate and rebuild only what's needed for a given
-execution of a task. In the case of large projects, assembling
-dependencies and acting upon them can cause some delay in executing
-tasks.
-
-With one exception, the trigger to rebuild or regenerate a file
-is always a disparity in timestamps between a target file and
-its source - if an input file is newer than its target dependency,
-the target is rebuilt or regenerated. For example, if the C source
-file from which an object file is compiled is newer than that object
-file on disk, recompilation will occur (of course, if no object
-file exists on disk, compilation will always occur). The one
-exception to this dependency behavior is specific to your input
-configuration. Only if your logical configuration changes
-will a system-wide rebuild occur. Reorganizing your input configuration
-or otherwise updating its file timestamp without modifying
-the values within the file will not trigger a rebuild. This behavior
-handles the various ways in which your input configuration can
-change (discussed later in this document) without having changed
-your actual project YAML file.
-
-Ceedling needs a bit of help to accomplish its magic with deep
-dependencies. Shallow dependencies are straightforward:
-a mock is dependent on the header file from which it's generated,
-a test file is dependent upon the source files it includes (see
-the preceding conventions section), etc. Ceedling handles
-these "out of the box." Deep dependencies are specifically a
-C-related phenomenon and occur as a consequence of include statements
-within C source files. Say a source file includes a header file
-and that header file in turn includes another header file which
-includes still another header file. A change to the deepest header
-file should trigger a recompilation of the source file, a relinking
-of all the object files comprising a test fixture, and a new execution
-of that test fixture.
-
-Ceedling can handle deep dependencies but only with the help
-of a C preprocessor. Ceedling is quite capable, but a full C preprocessor
-it ain't. Your project can be configured to use a C preprocessor
-or not. Simple projects or large projects constructed so as to
-be quite flat in their include structure generally don't need
-deep dependency preprocessing - and can enjoy the benefits of
-faster execution. Legacy code, on the other hand, will almost
-always want to be tested with deep preprocessing enabled. Set
-up of the C preprocessor is covered in the documentation for the
-[:project] and [:tools] section of the configuration file (later
-in this document). Ceedling contains all the configuration
-necessary to use the gcc preprocessor by default. That is, as
-long as gcc is in your system search path, deep preprocessing
-of deep dependencies is available to you by simply enabling it
-in your project configuration file.
-
-Ceedling's Build Output
------------------------
-
-Ceedling requires a top-level build directory for all the stuff
-that it, the accompanying test tools, and your toolchain generate.
-That build directory's location is configured in the [:project]
-section of your configuration file (discussed later). There
-can be a ton of generated files. By and large, you can live a full
-and meaningful life knowing absolutely nothing at all about
-the files and directories generated below the root build directory.
-
-As noted already, it's good practice to add your top-level build
-directory to source control but nothing generated beneath it.
-You'll spare yourself headache if you let Ceedling delete and
-regenerate files and directories in a non-versioned corner
-of your project's filesystem beneath the top-level build directory.
-
-The `artifacts` directory is the one and only directory you may
-want to know about beneath the top-level build directory. The
-subdirectories beneath `artifacts` will hold your binary release
-target output (if your project is configured for release builds)
-and will serve as the conventional location for plugin output.
-This directory structure was chosen specifically because it
-tends to work nicely with Continuous Integration setups that
-recognize and list build artifacts for retrieval / download.
-
-The Almighty Project Configuration File (in Glorious YAML)
-----------------------------------------------------------
-
-Please consult YAML documentation for the finer points of format
-and to understand details of our YAML-based configuration file.
-We recommend [Wikipedia's entry on YAML](http://en.wikipedia.org/wiki/Yaml)
-for this. A few highlights from that reference page:
-
-* YAML streams are encoded using the set of printable Unicode
-  characters, either in UTF-8 or UTF-16
-
-* Whitespace indentation is used to denote structure; however
-  tab characters are never allowed as indentation
-
-* Comments begin with the number sign ( # ), can start anywhere
-  on a line, and continue until the end of the line unless enclosed
-  by quotes
-
-* List members are denoted by a leading hyphen ( - ) with one member
-  per line, or enclosed in square brackets ( [ ] ) and separated
-  by comma space ( , )
-
-* Hashes are represented using the colon space ( : ) in the form
-  key: value, either one per line or enclosed in curly braces
-  ( { } ) and separated by comma space ( , )
-
-* Strings (scalars) are ordinarily unquoted, but may be enclosed
-  in double-quotes ( " ), or single-quotes ( ' )
-
-* YAML requires that colons and commas used as list separators
-  be followed by a space so that scalar values containing embedded
-  punctuation can generally be represented without needing
-  to be enclosed in quotes
-
-* Repeated nodes are initially denoted by an ampersand ( & ) and
-  thereafter referenced with an asterisk ( * )
-
-
-Notes on what follows:
-
-* Each of the following sections represent top-level entries
-  in the YAML configuration file.
-
-* Unless explicitly specified in the configuration file, default
-  values are used by Ceedling.
-
-* These three settings, at minimum, must be specified:
-  * [:project][:build_root]
-  * [:paths][:source]
-  * [:paths][:test]
-
-* As much as is possible, Ceedling validates your settings in
-  properly formed YAML.
-
-* Improperly formed YAML will cause a Ruby error when the YAML
-  is parsed. This is usually accompanied by a complaint with
-  line and column number pointing into the project file.
-
-* Certain advanced features rely on gcc and cpp as preprocessing
-  tools. In most *nix systems, these tools are already available.
-  For Windows environments, we recommend the [mingw project](http://www.mingw.org/)
-  (Minimalist GNU for Windows).
-
-* Ceedling is primarily meant as a build tool to support automated
-  unit testing. All the heavy lifting is involved there. Creating
-  a simple binary release build artifact is quite trivial in
-  comparison. Consequently, most default options and the construction
-  of Ceedling itself is skewed towards supporting testing though
-  Ceedling can, of course, build your binary release artifact
-  as well. Note that complex binary release artifacts (e.g.
-  application + bootloader or multiple libraries) are beyond
-  Ceedling's release build ability.
-
-
-Conventions / features of Ceedling-specific YAML:
-
-* Any second tier setting keys anywhere in YAML whose names end
-  in `_path` or `_paths` are automagically processed like all
-  Ceedling-specific paths in the YAML to have consistent directory
-  separators (i.e. "/") and to take advantage of inline Ruby
-  string expansion (see [:environment] setting below for further
-  explanation of string expansion).
-
-
-**Let's Be Careful Out There:** Ceedling performs validation
-on the values you set in your configuration file (this assumes
-your YAML is correct and will not fail format parsing, of course).
-That said, validation is limited to only those settings Ceedling
-uses and those that can be reasonably validated. Ceedling does
-not limit what can exist within your configuration file. In this
-way, you can take full advantage of YAML as well as add sections
-and values for use in your own custom plugins (documented later).
-The consequence of this is simple but important. A misspelled
-configuration section name or value name is unlikely to cause
-Ceedling any trouble. Ceedling will happily process that section
-or value and simply use the properly spelled default maintained
-internally - thus leading to unexpected behavior without warning.
-
-project: global project settings
-
-
-* `build_root`:
-
-  Top level directory into which generated path structure and files are
-  placed. Note: this is one of the handful of configuration values that
-  must be set. The specified path can be absolute or relative to your
-  working directory.
-
-  **Default**: (none)
-
-* `use_exceptions`:
-
-  Configures the build environment to make use of CException. Note that
-  if you do not use exceptions, there's no harm in leaving this as its
-  default value.
-
-  **Default**: TRUE
-
-* `use_mocks`:
-
-  Configures the build environment to make use of CMock. Note that if
-  you do not use mocks, there's no harm in leaving this setting as its
-  default value.
-
-  **Default**: TRUE
-
-* `use_test_preprocessor`:
-
-  This option allows Ceedling to work with test files that contain
-  conditional compilation statements (e.g. #ifdef) and header files you
-  wish to mock that contain conditional preprocessor statements and/or
-  macros.
-
-  Ceedling and CMock are advanced tools with sophisticated parsers.
-  However, they do not include entire C language preprocessors.
-  Consequently, with this option enabled, Ceedling will use gcc's
-  preprocessing mode and the cpp preprocessor tool to strip down /
-  expand test files and headers to their applicable content which can
-  then be processed by Ceedling and CMock.
-
-  With this option enabled, the gcc & cpp tools must exist in an
-  accessible system search path and test runner files are always
-  regenerated.
-
-  **Default**: FALSE
-
-* `use_deep_dependencies`:
-
-  The base rules and tasks that Ceedling creates using Rake capture most
-  of the dependencies within a standard project (e.g. when the source
-  file accompanying a test file changes, the corresponding test fixture
-  executable will be rebuilt when tests are re-run). However, deep
-  dependencies cannot be captured this way. If a typedef or macro
-  changes in a header file three levels of #include statements deep,
-  this option allows the appropriate incremental build actions to occur
-  for both test execution and release builds.
-
-  This is accomplished by using the dependencies discovery mode of gcc.
-  With this option enabled, gcc must exist in an accessible system
-  search path.
-
-  **Default**: FALSE
-
-* `generate_deep_dependencies`:
-
-  When `use_deep_dependencies` is set to TRUE, Ceedling will run a separate
-  build step to generate the deep dependencies. If you are using gcc as your
-  primary compiler, or another compiler that can generate makefile rules as
-  a side effect of compilation, then you can set this to FALSE to avoid the
-  extra build step but still use the deep dependencies data when deciding
-  which source files to rebuild.
-
-  **Default**: TRUE
-
-* `test_file_prefix`:
-
-  Ceedling collects test files by convention from within the test file
-  search paths. The convention includes a unique name prefix and a file
-  extension matching that of source files.
-
-  Why not simply recognize all files in test directories as test files?
-  By using the given convention, we have greater flexibility in what we
-  do with C files in the test directories.
-
-  **Default**: "test_"
-
-* `options_paths`:
-
-  Just as you may have various build configurations for your source
-  codebase, you may need variations of your project configuration.
-
-  By specifying options paths, Ceedling will search for other project
-  YAML files, make command line tasks available (ceedling options:variation
-  for a variation.yml file), and merge the project configuration of
-  these option files in with the main project file at runtime. See
-  advanced topics.
-
-  Note these Rake tasks at the command line - like verbosity or logging
-  control - must come before the test or release task they are meant to
-  modify.
-
-  **Default**: [] (empty)
-
-* `release_build`:
-
-  When enabled, a release Rake task is exposed. This configuration
-  option requires a corresponding release compiler and linker to be
-  defined (gcc is used as the default).
-
-  More release configuration options are available in the release_build
-  section.
-
-  **Default**: FALSE
-
-
-Example `[:project]` YAML blurb
-
-```yaml
-:project:
-  :build_root: project_awesome/build
-  :use_exceptions: FALSE
-  :use_test_preprocessor: TRUE
-  :use_deep_dependencies: TRUE
-  :options_paths:
-    - project/options
-    - external/shared/options
-  :release_build: TRUE
-```
-
-Ceedling is primarily concerned with facilitating the somewhat
-complicated mechanics of automating unit tests. The same mechanisms
-are easily capable of building a final release binary artifact
-(i.e. non test code; the thing that is your final working software
-that you execute on target hardware).
-
-
-* `output`:
-
-  The name of your release build binary artifact to be found in <build
-  path>/artifacts/release. Ceedling sets the default artifact file
-  extension to that as is explicitly specified in the [:extensions]
-  section or as is system specific otherwise.
-
-  **Default**: `project.exe` or `project.out`
-
-* `use_assembly`:
-
-  If assembly code is present in the source tree, this option causes
-  Ceedling to create appropriate build directories and use an assembler
-  tool (default is the GNU tool as - override available in the [:tools]
-  section.
-
-  **Default**: FALSE
-
-* `artifacts`:
-
-  By default, Ceedling copies to the <build path>/artifacts/release
-  directory the output of the release linker and (optionally) a map
-  file. Many toolchains produce other important output files as well.
-  Adding a file path to this list will cause Ceedling to copy that file
-  to the artifacts directory. The artifacts directory is helpful for
-  organizing important build output files and provides a central place
-  for tools such as Continuous Integration servers to point to build
-  output. Selectively copying files prevents incidental build cruft from
-  needlessly appearing in the artifacts directory. Note that inline Ruby
-  string replacement is available in the artifacts paths (see discussion
-  in the [:environment] section).
-
-  **Default**: [] (empty)
-
-Example `[:release_build]` YAML blurb
-
-```yaml
-:release_build:
-  :output: top_secret.bin
-  :use_assembly: TRUE
-  :artifacts:
-    - build/release/out/c/top_secret.s19
-```
-
-**paths**: options controlling search paths for source and header
-(and assembly) files
-
-* `test`:
-
-  All C files containing unit test code. Note: this is one of the
-  handful of configuration values that must be set.
-
-  **Default**: [] (empty)
-
-* `source`:
-
-  All C files containing release code (code to be tested). Note: this is
-  one of the handful of configuration values that must be set.
-
-  **Default**: [] (empty)
-
-* `support`:
-
-  Any C files you might need to aid your unit testing. For example, on
-  occasion, you may need to create a header file containing a subset of
-  function signatures matching those elsewhere in your code (e.g. a
-  subset of your OS functions, a portion of a library API, etc.). Why?
-  To provide finer grained control over mock function substitution or
-  limiting the size of the generated mocks.
-
-  **Default**: [] (empty)
-
-* `include`:
-
-  Any header files not already in the source search path. Note there's
-    no practical distinction between this search path and the source
-    search path; it's merely to provide options or to support any
-    peculiar source tree organization.
-
-  **Default**: [] (empty)
-
-* `test_toolchain_include`:
-
-  System header files needed by the test toolchain - should your
-  compiler be unable to find them, finds the wrong system include search
-  path, or you need a creative solution to a tricky technical problem.
-  Note that if you configure your own toolchain in the [:tools] section,
-  this search path is largely meaningless to you. However, this is a
-  convenient way to control the system include path should you rely on
-  the default gcc tools.
-
-  **Default**: [] (empty)
-
-* `release_toolchain_include`:
-
-  Same as preceding albeit related to the release toolchain.
-
-  **Default**: [] (empty)
-
-* `<custom>`
-
-  Any paths you specify for custom list. List is available to tool
-  configurations and/or plugins. Note a distinction. The preceding names
-  are recognized internally to Ceedling and the path lists are used to
-  build collections of files contained in those paths. A custom list is
-  just that - a custom list of paths.
-
-Notes on path grammar within the [:paths] section:
-
-* Order of search paths listed in [:paths] is preserved when used by an
-  entry in the [:tools] section
-
-* Wherever multiple path lists are combined for use Ceedling prioritizes
-  path groups as follows:
-  test paths, support paths, source paths, include paths.
-
-  This can be useful, for instance, in certain testing scenarios where
-  we desire Ceedling or the compiler to find a stand-in header file before
-  the actual source header file of the same name.
-
-* Paths:
-
-  1. can be absolute or relative
-
-  2. can be singly explicit - a single fully specified path
-
-  3. can include a glob operator (more on this below)
-
-  4. can use inline Ruby string replacement (see [:environment]
-     section for more)
-
-  5. default as an addition to a specific search list (more on this
-     in the examples)
-
-  6. can act to subtract from a glob included in the path list (more
-     on this in the examples)
-
-
-[Globs](http://ruby.about.com/od/beginningruby/a/dir2.htm)
-as used by Ceedling are wildcards for specifying directories
-without the need to list each and every required search path.
-Ceedling globs operate just as Ruby globs except that they are
-limited to matching directories and not files. Glob operators
-include the following * ** ? [-] {,} (note: this list is space separated
-and not comma separated as commas are used within the bracket
-operators).
-
-* `*`:
-
-  All subdirectories of depth 1 below the parent path and including the
-  parent path
-
-* `**`:
-
-  All subdirectories recursively discovered below the parent path and
-  including the parent path
-
-* `?`:
-
-  Single alphanumeric character wildcard
-
-* `[x-y]`:
-
-  Single alphanumeric character as found in the specified range
-
-* `{x,y}`:
-
-  Single alphanumeric character from the specified list
-
-Example [:paths] YAML blurbs
-
-```yaml
-:paths:
-  :source:              #together the following comprise all source search paths
-    - project/source/*  #expansion yields all subdirectories of depth 1 plus parent directory
-    - project/lib       #single path
-  :test:                #all test search paths
-    - project/**/test?  #expansion yields any subdirectory found anywhere in the project that
-                        #begins with "test" and contains 5 characters
-
-:paths:
-  :source:                           #all source search paths
-    - +:project/source/**            #all subdirectories recursively discovered plus parent directory
-    - -:project/source/os/generated  #subtract os/generated directory from expansion of above glob
-                                     #note that '+:' notation is merely aesthetic; default is to add
-
-  :test:                             #all test search paths
-    - project/test/bootloader        #explicit, single search paths (searched in the order specified)
-    - project/test/application
-    - project/test/utilities
-
-  :custom:                           #custom path list
-    - "#{PROJECT_ROOT}/other"        #inline Ruby string expansion
-```
-
-Globs and inline Ruby string expansion can require trial and
-error to arrive at your intended results. Use the `ceedling paths:*`
-command line options (documented in preceding section) to verify
-your settings.
-
-Ceedling relies on file collections automagically assembled
-from paths, globs, and file extensions. File collections greatly
-simplify project set up. However, sometimes you need to remove
-from or add individual files to those collections.
-
-
-* `test`:
-
-  Modify the collection of unit test C files.
-
-  **Default**: [] (empty)
-
-* `source`:
-
-  Modify the collection of all source files used in unit test builds and release builds.
-
-  **Default**: [] (empty)
-
-* `assembly`:
-
-  Modify the (optional) collection of assembly files used in release builds.
-
-  **Default**: [] (empty)
-
-* `include`:
-
-  Modify the collection of all source header files used in unit test builds (e.g. for mocking) and release builds.
-
-  **Default**: [] (empty)
-
-* `support`:
-
-  Modify the collection of supporting C files available to unit tests builds.
-
-  **Default**: [] (empty)
-
-
-Note: All path grammar documented in [:paths] section applies
-to [:files] path entries - albeit at the file path level and not
-the directory level.
-
-Example [:files] YAML blurb
-
-```yaml
-:files:
-  :source:
-    - callbacks/comm.c        # entry defaults to file addition
-    - +:callbacks/comm*.c     # add all comm files matching glob pattern
-    - -:source/board/atm134.c # not our board
-  :test:
-    - -:test/io/test_output_manager.c # remove unit tests from test build
-```
-
-**environment:** inserts environment variables into the shell
-instance executing configured tools
-
-Ceedling creates environment variables from any key / value
-pairs in the environment section. Keys become an environment
-variable name in uppercase. The values are strings assigned
-to those environment variables. These value strings are either
-simple string values in YAML or the concatenation of a YAML array.
-
-Ceedling is able to execute inline Ruby string substitution
-code to set environment variables. This evaluation occurs when
-the project file is first processed for any environment pair's
-value string including the Ruby string substitution pattern
-`#{…}`. Note that environment value strings that _begin_ with
-this pattern should always be enclosed in quotes. YAML defaults
-to processing unquoted text as a string; quoting text is optional.
-If an environment pair's value string begins with the Ruby string
-substitution pattern, YAML will interpret the string as a Ruby
-comment (because of the `#`). Enclosing each environment value
-string in quotes is a safe practice.
-
-[:environment] entries are processed in the configured order
-(later entries can reference earlier entries).
-
-Special case: PATH handling
-
-In the specific case of specifying an environment key named _path_,
-an array of string values will be concatenated with the appropriate
-platform-specific path separation character (e.g. ':' on *nix,
-';' on Windows). All other instances of environment keys assigned
-YAML arrays use simple concatenation.
-
-Example [:environment] YAML blurb
-
-```yaml
-:environment:
-  - :license_server: gizmo.intranet        #LICENSE_SERVER set with value "gizmo.intranet"
-  - :license: "#{`license.exe`}"           #LICENSE set to string generated from shelling out to
-                                           #execute license.exe; note use of enclosing quotes
-
-  - :path:                                 #concatenated with path separator (see special case above)
-     - Tools/gizmo/bin                     #prepend existing PATH with gizmo path
-     - "#{ENV['PATH']}"                    #pattern #{…} triggers ruby evaluation string substitution
-                                           #note: value string must be quoted because of '#'
-
-  - :logfile: system/logs/thingamabob.log  #LOGFILE set with path for a log file
-```
-
-**extension**: configure file name extensions used to collect lists of files searched in [:paths]
-
-* `header`:
-
-  C header files
-
-  **Default**: .h
-
-* `source`:
-
-  C code files (whether source or test files)
-
-  **Default**: .c
-
-* `assembly`:
-
-  Assembly files (contents wholly assembly instructions)
-
-  **Default**: .s
-
-* `object`:
-
-  Resulting binary output of C code compiler (and assembler)
-
-  **Default**: .o
-
-* `executable`:
-
-  Binary executable to be loaded and executed upon target hardware
-
-  **Default**: .exe or .out (Win or *nix)
-
-* `testpass`:
-
-  Test results file (not likely to ever need a new value)
-
-  **Default**: .pass
-
-* `testfail`:
-
-  Test results file (not likely to ever need a new value)
-
-  **Default**: .fail
-
-* `dependencies`:
-
-  File containing make-style dependency rules created by gcc preprocessor
-
-  **Default**: .d
-
-
-Example [:extension] YAML blurb
-
-    :extension:
-      :source: .cc
-      :executable: .bin
-
-**defines**: command line defines used in test and release compilation by configured tools
-
-* `test`:
-
-  Defines needed for testing. Useful for:
-
-  1. test files containing conditional compilation statements (i.e.
-  tests active in only certain contexts)
-
-  2. testing legacy source wherein the isolation of source under test
-  afforded by Ceedling and its complementary tools leaves certain
-  symbols unset when source files are compiled in isolation
-
-  **Default**: [] (empty)
-
-* `test_preprocess`:
-
-  If [:project][:use_test_preprocessor] or
-  [:project][:use_deep_dependencies] is set and code is structured in a
-  certain way, the gcc preprocessor may need symbol definitions to
-  properly preprocess files to extract function signatures for mocking
-  and extract deep dependencies for incremental builds.
-
-  **Default**: [] (empty)
-
-* `release`:
-
-  Defines needed for the release build binary artifact.
-
-  **Default**: [] (empty)
-
-* `release_preprocess`:
-
-  If [:project][:use_deep_dependencies] is set and code is structured in
-  a certain way, the gcc preprocessor may need symbol definitions to
-  properly preprocess files for incremental release builds due to deep
-  dependencies.
-
-  **Default**: [] (empty)
-
-
-Example [:defines] YAML blurb
-
-```yaml
-:defines:
-  :test:
-    - UNIT_TESTING  #for select cases in source to allow testing with a changed behavior or interface
-    - OFF=0
-    - ON=1
-    - FEATURE_X=ON
-  :source:
-    - FEATURE_X=ON
-```
-
-
-**libraries**: command line defines used in test and release compilation by configured tools
-
-Ceedling allows you to pull in specific libraries for the purpose of release and test builds.
-It has a few levels of support for this. Start by adding a :libraries main section in your
-configuration. In this section, you can optionally have the following subsections:
-
-* `test`:
-
-  Library files that should be injected into your tests when linking occurs.
-  These can be specified as either relative or absolute paths. These files MUST
-  exist when the test attempts to build.
-
-* `source`:
-
-  Library files that should be injected into your release when linking occurs. These
-  can be specified as either relative or absolute paths. These files MUST exist when
-  the release attempts to build UNLESS you are using the subprojects plugin. In that
-  case, it will attempt to build that library for you as a dynamic dependency.
-
-* `system`:
-
-  These libraries are assumed to be in the tool path somewhere and shouldn't need to be
-  specified. The libraries added here will be injected into releases and tests.
-
-* `flag`:
-
-  This is the method of adding an argument for each library. For example, gcc really likes
-  it when you specify “-l${1}�
-
-Notes:
-
-* If you've specified your own link step, you are going to want to add ${4} to your argument
-list in the place where library files should be added to the command call. For gcc, this is
-often the very end. Other tools may vary.
-
-
-**flags**: configure per-file compilation and linking flags
-
-Ceedling tools (see later [:tools] section) are used to configure
-compilation and linking of test and source files. These tool
-configurations are a one-size-fits-all approach. Should individual files
-require special compilation or linking flags, the settings in the
-[:flags] section work in conjunction with tool definitions by way of
-argument substitution to achieve this.
-
-* `release`:
-
-  [:compile] or [:link] flags for release build
-
-* `test`:
-
-  [:compile] or [:link] flags for test build
-
-Notes:
-
-* Ceedling works with the [:release] and [:test] build contexts
-  as-is; plugins can add additional contexts
-
-* Only [:compile] and [:link] are recognized operations beneath
-  a context
-
-* File specifiers do not include a path or file extension
-
-* File specifiers are case sensitive (must match original file
-  name)
-
-* File specifiers do support regular expressions if encased in quotes
-
-* '*' is a special (optional) file specifier to provide flags
-  to all files not otherwise specified
-
-
-Example [:flags] YAML blurb
-
-```yaml
-:flags:
-  :release:
-    :compile:
-      :main:       # add '-Wall' to compilation of main.c
-        - -Wall
-      :fan:        # add '--O2' to compilation of fan.c
-        - --O2
-      :'test_.+':   # add '-pedantic' to all test-files
-        - -pedantic
-      :*:          # add '-foo' to compilation of all files not main.c or fan.c
-        - -foo
-  :test:
-    :compile:
-      :main:       # add '--O1' to compilation of main.c as part of test builds including main.c
-        - --O1
-    :link:
-      :test_main:  # add '--bar --baz' to linking of test_main.exe
-        - --bar
-        - --baz
-```
-
-Ceedling sets values for a subset of CMock settings. All CMock
-options are available to be set, but only those options set by
-Ceedling in an automated fashion are documented below. See CMock
-documentation.
-
-**cmock**: configure CMock's code generation options and set symbols used to modify CMock's compiled features
-Ceedling sets values for a subset of CMock settings. All CMock options are available to be set, but only those options set by Ceedling in an automated fashion are documented below. See CMock documentation.
-
-* `enforce_strict_ordering`:
-
-  Tests fail if expected call order is not same as source order
-
-  **Default**: TRUE
-
-* `mock_path`:
-
-  Path for generated mocks
-
-  **Default**: <build path>/tests/mocks
-
-* `defines`:
-
-  List of conditional compilation symbols used to configure CMock's
-  compiled features. See CMock documentation to understand available
-  options. No symbols must be set unless defaults are inappropriate for
-  your specific environment. All symbols are used only by Ceedling to
-  compile CMock C code; contents of [:defines] are ignored by CMock's
-  Ruby code when instantiated.
-
-  **Default**: [] (empty)
-
-* `verbosity`:
-
-  If not set, defaults to Ceedling's verbosity level
-
-* `plugins`:
-
-  If [:project][:use_exceptions] is enabled, the internal plugins list is pre-populated with 'cexception'.
-
-  Whether or not you have included [:cmock][:plugins] in your
-  configuration file, Ceedling automatically adds 'cexception' to the
-  plugin list if exceptions are enabled. To add to the list Ceedling
-  provides CMock, simply add [:cmock][:plugins] to your configuration
-  and specify your desired additional plugins.
-
-* `includes`:
-
-  If [:cmock][:unity_helper] set, pre-populated with unity_helper file
-  name (no path).
-
-  The [:cmock][:includes] list works identically to the plugins list
-  above with regard to adding additional files to be inserted within
-  mocks as #include statements.
-
-
-The last four settings above are directly tied to other Ceedling
-settings; hence, why they are listed and explained here. The
-first setting above, [:enforce_strict_ordering], defaults
-to FALSE within CMock. It is set to TRUE by default in Ceedling
-as our way of encouraging you to use strict ordering. It's a teeny
-bit more expensive in terms of code generated, test execution
-time, and complication in deciphering test failures. However,
-it's good practice. And, of course, you can always disable it
-by overriding the value in the Ceedling YAML configuration file.
-
-
-**cexception**: configure symbols used to modify CException's compiled features
-
-* `defines`:
-
-  List of conditional compilation symbols used to configure CException's
-  features in its source and header files. See CException documentation
-  to understand available options. No symbols must be set unless the
-  defaults are inappropriate for your specific environment.
-
-  **Default**: [] (empty)
-
-
-**unity**: configure symbols used to modify Unity's compiled features
-
-* `defines`:
-
-  List of conditional compilation symbols used to configure Unity's
-  features in its source and header files. See Unity documentation to
-  understand available options. No symbols must be set unless the
-  defaults are inappropriate for your specific environment. Most Unity 
-  defines can be easily configured through the YAML file.
-
-  **Default**: [] (empty)
-
-Example [:unity] YAML blurbs
-```yaml
-:unity: #itty bitty processor & toolchain with limited test execution options
-  :defines:
-    - UNITY_INT_WIDTH=16           #16 bit processor without support for 32 bit instructions
-    - UNITY_EXCLUDE_FLOAT          #no floating point unit
-
-:unity: #great big gorilla processor that grunts and scratches
-  :defines:
-    - UNITY_SUPPORT_64                    #big memory, big counters, big registers
-    - UNITY_LINE_TYPE=\"unsigned int\"    #apparently we're using really long test files,
-    - UNITY_COUNTER_TYPE=\"unsigned int\" #and we've got a ton of test cases in those test files
-    - UNITY_FLOAT_TYPE=\"double\"         #you betcha
-```
-
-
-Notes on Unity configuration:
-
-* **Verification** - Ceedling does no verification of your configuration
-  values. In a properly configured setup, your Unity configuration
-  values are processed, collected together with any test define symbols
-  you specify elsewhere, and then passed to your toolchain during test
-  compilation. Unity's conditional compilation statements, your
-  toolchain's preprocessor, and/or your toolchain's compiler will
-  complain appropriately if your specified configuration values are
-  incorrect, incomplete, or incompatible.
-
-* **Routing $stdout** - Unity defaults to using `putchar()` in C's
-  standard library to display test results. For more exotic environments
-  than a desktop with a terminal (e.g. running tests directly on a
-  non-PC target), you have options. For example, you could create a
-  routine that transmits a character via RS232 or USB. Once you have
-  that routine, you can replace `putchar()` calls in Unity by overriding
-  the function-like macro `UNITY_OUTPUT_CHAR`. Consult your toolchain
-  and shell documentation. Eventhough this can also be defined in the YAML file
-  most shell environments do not handle parentheses as command line arguments 
-  very well. To still be able to add this functionality all necessary 
-  options can be defined in the `unity_config.h`. Unity needs to be told to look for 
-  the `unity_config.h` in the YAML file, though. 
-
-Example [:unity] YAML blurbs
-```yaml
-:unity:
-  :defines:
-  	- UNITY_INCLUDE_CONFIG_H
-```
-
-Example unity_config.h
-```
-#ifndef UNITY_CONFIG_H
-#define UNITY_CONFIG_H
-
-#include "uart_output.h" //Helper library for your custom environment
-
-#define UNITY_INT_WIDTH 16
-#define UNITY_OUTPUT_START() uart_init(F_CPU, BAUD) //Helperfunction to init UART
-#define UNITY_OUTPUT_CHAR(a) uart_putchar(a) //Helperfunction to forward char via UART
-#define UNITY_OUTPUT_COMPLETE() uart_complete() //Helperfunction to inform that test has ended
-
-#endif
-```
-
-
-**tools**: a means for representing command line tools for use under
-Ceedling's automation framework
-
-Ceedling requires a variety of tools to work its magic. By default,
-the GNU toolchain (gcc, cpp, as) are configured and ready for
-use with no additions to the project configuration YAML file.
-However, as most work will require a project-specific toolchain,
-Ceedling provides a generic means for specifying / overriding
-tools.
-
-* `test_compiler`:
-
-  Compiler for test & source-under-test code
-  ${1}: input source ${2}: output object ${3}: optional output list ${4}: optional output dependencies file
-
-  **Default**: gcc
-
-* `test_linker`:
-
-  Linker to generate test fixture executables
-  ${1}: input objects ${2}: output binary ${3}: optional output map ${4}: optional library list
-
-  **Default**: gcc
-
-* `test_fixture`:
-
-  Executable test fixture
-  ${1}: simulator as executable with ${1} as input binary file argument or native test executable
-
-  **Default**: ${1}
-
-* `test_includes_preprocessor`:
-
-  Extractor of #include statements
-  ${1}: input source file
-
-  **Default**: cpp
-
-* `test_file_preprocessor`:
-
-  Preprocessor of test files (macros, conditional compilation statements)
-  ${1}: input source file ${2}: preprocessed output source file
-
-  **Default**: gcc
-
-* `test_dependencies_generator`:
-
-  Discovers deep dependencies of source & test (for incremental builds)
-  ${1}: input source file ${2}: compiled object filepath ${3}: output dependencies file
-
-  **Default**: gcc
-
-* `release_compiler`:
-
-  Compiler for release source code
-  ${1}: input source ${2}: output object ${3}: optional output list ${4}: optional output dependencies file
-
-  **Default**: gcc
-
-* `release_assembler`:
-
-  Assembler for release assembly code
-  ${1}: input assembly source file ${2}: output object file
-
-  **Default**: as
-
-* `release_linker`:
-
-  Linker for release source code
-  ${1}: input objects ${2}: output binary ${3}: optional output map ${4}: optional library list
-
-  **Default**: gcc
-
-* `release_dependencies_generator`:
-
-  Discovers deep dependencies of source files (for incremental builds)
-  ${1}: input source file ${2}: compiled object filepath ${3}: output dependencies file
-
-  **Default**: gcc
-
-
-A Ceedling tool has a handful of configurable elements:
-
-1. [:executable] (required) - Command line executable having
-   the form of:
-
-2. [:arguments] (required) - List of command line arguments
-   and substitutions
-
-3. [:name] - Simple name (e.g. "nickname") of tool beyond its
-   executable name (if not explicitly set then Ceedling will
-   form a name from the tool's YAML entry name)
-
-4. [:stderr_redirect] - Control of capturing $stderr messages
-   {:none, :auto, :win, :unix, :tcsh}.
-   Defaults to :none if unspecified; create a custom entry by
-   specifying a simple string instead of any of the available
-   symbols.
-
-5. [:background_exec] - Control execution as background process
-   {:none, :auto, :win, :unix}.
-   Defaults to :none if unspecified.
-
-
-Tool Element Runtime Substitution
----------------------------------
-
-To accomplish useful work on multiple files, a configured tool will most
-often require that some number of its arguments or even the executable
-itself change for each run. Consequently, every tool's argument list and
-executable field possess two means for substitution at runtime. Ceedling
-provides two kinds of inline Ruby execution and a notation for
-populating elements with dynamically gathered values within the build
-environment.
-
-Tool Element Runtime Substitution: Inline Ruby Execution
---------------------------------------------------------
-
-In-line Ruby execution works similarly to that demonstrated for the
-[:environment] section except that substitution occurs as the tool is
-executed and not at the time the configuration file is first scanned.
-
-* `#{...}`:
-
-  Ruby string substitution pattern wherein the containing string is
-  expanded to include the string generated by Ruby code between the
-  braces. Multiple instances of this expansion can occur within a single
-  tool element entry string. Note that if this string substitution
-  pattern occurs at the very beginning of a string in the YAML
-  configuration the entire string should be enclosed in quotes (see the
-  [:environment] section for further explanation on this point).
-
-* `{...} `:
-
-  If an entire tool element string is enclosed with braces, it signifies
-  that Ceedling should execute the Ruby code contained within those
-  braces. Say you have a collection of paths on disk and some of those
-  paths include spaces. Further suppose that a single tool that must use
-  those paths requires those spaces to be escaped, but all other uses of
-  those paths requires the paths to remain unchanged. You could use this
-  Ceedling feature to insert Ruby code that iterates those paths and
-  escapes those spaces in the array as used by the tool of this example.
-
-Tool Element Runtime Substitution: Notational Substitution
-----------------------------------------------------------
-
-A Ceedling tool's other form of dynamic substitution relies on a '$'
-notation. These '$' operators can exist anywhere in a string and can be
-decorated in any way needed. To use a literal '$', escape it as '\\$'.
-
-* `$`:
-
-  Simple substitution for value(s) globally available within the runtime
-  (most often a string or an array).
-
-* `${#}`:
-
-  When a Ceedling tool's command line is expanded from its configured
-  representation and used within Ceedling Ruby code, certain calls to
-  that tool will be made with a parameter list of substitution values.
-  Each numbered substitution corresponds to a position in a parameter
-  list. Ceedling Ruby code expects that configured compiler and linker
-  tools will contain ${1} and ${2} replacement arguments. In the case of
-  a compiler ${1} will be a C code file path, and ${2} will be the file
-  path of the resulting object file. For a linker ${1} will be an array
-  of object files to link, and ${2} will be the resulting binary
-  executable. For an executable test fixture ${1} is either the binary
-  executable itself (when using a local toolchain such as gcc) or a
-  binary input file given to a simulator in its arguments.
-
-
-Example [:tools] YAML blurbs
-
-```yaml
-:tools:
-  :test_compiler:
-     :executable: compiler              #exists in system search path
-     :name: 'acme test compiler'
-     :arguments:
-        - -I"$": COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE               #expands to -I search paths
-        - -I"$": COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR   #expands to -I search paths
-        - -D$: COLLECTION_DEFINES_TEST_AND_VENDOR  #expands to all -D defined symbols
-        - --network-license             #simple command line argument
-        - -optimize-level 4             #simple command line argument
-        - "#{`args.exe -m acme.prj`}"   #in-line ruby sub to shell out & build string of arguments
-        - -c ${1}                       #source code input file (Ruby method call param list sub)
-        - -o ${2}                       #object file output (Ruby method call param list sub)
-  :test_linker:
-     :executable: /programs/acme/bin/linker.exe    #absolute file path
-     :name: 'acme test linker'
-     :arguments:
-        - ${1}               #list of object files to link (Ruby method call param list sub)
-        - -l$-lib:           #inline yaml array substitution to link in foo-lib and bar-lib
-           - foo
-           - bar
-        - -o ${2}            #executable file output (Ruby method call param list sub)
-  :test_fixture:
-     :executable: tools/bin/acme_simulator.exe  #relative file path to command line simulator
-     :name: 'acme test fixture'
-     :stderr_redirect: :win                     #inform Ceedling what model of $stderr capture to use
-     :arguments:
-        - -mem large   #simple command line argument
-        - -f "${1}"    #binary executable input file to simulator (Ruby method call param list sub)
-```
-
-Resulting command line constructions from preceding example [:tools] YAML blurbs
-
-    > compiler -I"/usr/include� -I�project/tests�
-      -I"project/tests/support� -I�project/source� -I�project/include�
-      -DTEST -DLONG_NAMES -network-license -optimize-level 4 arg-foo
-      arg-bar arg-baz -c project/source/source.c -o
-      build/tests/out/source.o
-
-[notes: (1.) "arg-foo arg-bar arg-baz" is a fabricated example
-string collected from $stdout as a result of shell execution
-of args.exe
-(2.) the -c and -o arguments are
-fabricated examples simulating a single compilation step for
-a test; ${1} & ${2} are single files]
-
-    > \programs\acme\bin\linker.exe thing.o unity.o
-      test_thing_runner.o test_thing.o mock_foo.o mock_bar.o -lfoo-lib
-      -lbar-lib -o build\tests\out\test_thing.exe
-
-[note: in this scenario ${1} is an array of all the object files
-needed to link a test fixture executable]
-
-    > tools\bin\acme_simulator.exe -mem large -f "build\tests\out\test_thing.bin 2>&1�
-
-[note: (1.) :executable could have simply been ${1} - if we were compiling
-and running native executables instead of cross compiling (2.) we're using
-$stderr redirection to allow us to capture simulator error messages to
-$stdout for display at the run's conclusion]
-
-
-Notes:
-
-* The upper case names are Ruby global constants that Ceedling
-  builds
-
-* "COLLECTION_" indicates that Ceedling did some work to assemble
-  the list. For instance, expanding path globs, combining multiple
-  path globs into a convenient summation, etc.
-
-* At present, $stderr redirection is primarily used to capture
-  errors from test fixtures so that they can be displayed at the
-  conclusion of a test run. For instance, if a simulator detects
-  a memory access violation or a divide by zero error, this notice
-  might go unseen in all the output scrolling past in a terminal.
-
-* The preprocessing tools can each be overridden with non-gcc
-  equivalents. However, this is an advanced feature not yet
-  documented and requires that the replacement toolchain conform
-  to the same conventions used by gcc.
-
-**Ceedling Collection Used in Compilation**:
-
-* `COLLECTION_PATHS_TEST`:
-
-  All test paths
-
-* `COLLECTION_PATHS_SOURCE`:
-
-  All source paths
-
-* `COLLECTION_PATHS_INCLUDE`:
-
-  All include paths
-
-* `COLLECTION_PATHS_SUPPORT`:
-
-  All test support paths
-
-* `COLLECTION_PATHS_SOURCE_AND_INCLUDE`:
-
-  All source and include paths
-
-* `COLLECTION_PATHS_SOURCE_INCLUDE_VENDOR`:
-
-  All source and include paths + applicable vendor paths (e.g.
-  CException's source path if exceptions enabled)
-
-* `COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE`:
-
-  All test toolchain include paths
-
-* `COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE`:
-
-  All test, source, and include paths
-
-* `COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR`:
-
-  All test, source, include, and applicable vendor paths (e.g. Unity's
-  source path plus CMock and CException's source paths if mocks and
-  exceptions are enabled)
-
-* `COLLECTION_PATHS_RELEASE_TOOLCHAIN_INCLUDE`:
-
-  All release toolchain include paths
-
-* `COLLECTION_DEFINES_TEST_AND_VENDOR`:
-
-  All symbols specified in [:defines][:test] + symbols defined for
-  enabled vendor tools - e.g. [:unity][:defines], [:cmock][:defines],
-  and [:cexception][:defines]
-
-* `COLLECTION_DEFINES_RELEASE_AND_VENDOR`:
-
-  All symbols specified in [:defines][:release] plus symbols defined by
-[:cexception][:defines] if exceptions are ena bled
-
-
-Notes:
-
-* Other collections exist within Ceedling. However, they are
-  only useful for advanced features not yet documented.
-
-* Wherever multiple path lists are combined for use Ceedling prioritizes
-  path groups as follows: test paths, support paths, source paths, include
-  paths.
-  This can be useful, for instance, in certain testing scenarios
-  where we desire Ceedling or the compiler to find a stand-in header file
-  before the actual source header file of the same name.
-
-
-**plugins**: Ceedling extensions
-
-* `load_paths`:
-
-  Base paths to search for plugin subdirectories or extra ruby functionalit
-
-  **Default**: [] (empty)
-
-* `enabled`:
-
-  List of plugins to be used - a plugin's name is identical to the
-  subdirectory that contains it (and the name of certain files within
-  that subdirectory)
-
-  **Default**: [] (empty)
-
-
-Plugins can provide a variety of added functionality to Ceedling. In
-general use, it's assumed that at least one reporting plugin will be
-used to format test results. However, if no reporting plugins are
-specified, Ceedling will print to `$stdout` the (quite readable) raw
-test results from all test fixtures executed.
-
-Example [:plugins] YAML blurb
-
-```yaml
-:plugins:
-  :load_paths:
-    - project/tools/ceedling/plugins  #home to your collection of plugin directories
-    - project/support                 #maybe home to some ruby code your custom plugins share
-  :enabled:
-    - stdout_pretty_tests_report      #nice test results at your command line
-    - our_custom_code_metrics_report  #maybe you needed line count and complexity metrics, so you
-                                      #created a plugin to scan all your code and collect that info
-```
-
-* `stdout_pretty_tests_report`:
-
-  Prints to $stdout a well-formatted list of ignored and failed tests,
-  final test counts, and any extraneous output (e.g. printf statements
-  or simulator memory errors) collected from executing the test
-  fixtures. Meant to be used with runs at the command line.
-
-* `stdout_ide_tests_report`:
-
-  Prints to $stdout simple test results formatted such that an IDE
-  executing test-related Rake tasks can recognize file paths and line
-  numbers in test failures, etc. Thus, you can click a test result in
-  your IDE's execution window and jump to the failure (or ignored test)
-  in your test file (obviously meant to be used with an [IDE like
-  Eclipse][ide], etc).
-
-  [ide]: http://throwtheswitch.org/white-papers/using-with-ides.html
-
-* `xml_tests_report`:
-
-  Creates an XML file of test results in the xUnit format (handy for
-  Continuous Integration build servers or as input to other reporting
-  tools). Produces a file report.xml in <build root>/artifacts/tests.
-
-* `bullseye`:
-
-  Adds additional Rake tasks to execute tests with the commercial code
-  coverage tool provided by [Bullseye][]. See readme.txt inside the bullseye
-  plugin directory for configuration and use instructions. Note:
-  Bullseye only works with certain compilers and linkers (healthy list
-  of supported toolchains though).
-
-  [bullseye]: http://www.bullseye.com
-
-* `gcov`:
-
-  Adds additional Rake tasks to execute tests with the GNU code coverage
-  tool [gcov][]. See readme.txt inside the gcov directory for configuration
-  and use instructions. Only works with GNU compiler and linker.
-
-  [gcov]: http://gcc.gnu.org/onlinedocs/gcc/Gcov.html
-
-* `warnings_report`:
-
-  Scans compiler and linker `$stdout / $stderr` output for the word
-  'warning' (case insensitive). All code warnings (or tool warnings) are
-  logged to a file warnings.log in the appropriate `<build
-  root>/artifacts` directory (e.g. test/ for test tasks, `release/` for a
-  release build, or even `bullseye/` for bullseye runs).
-
-Module Generator
-========================
-Ceedling includes a plugin called module_generator that will create a source, header and test file for you.
-There are several possibilities to configure this plugin through your project.yml to suit your project's needs.
-
-Directory Structure
--------------------------------------------
-
-The default configuration for directory/project structure is:
-```yaml
-:module_generator:
-  :project_root: ./
-  :source_root: src/
-  :test_root: test/
-```
-You can change these variables in your project.yml file to comply with your project's directory structure.
-
-If you call `ceedling module:create`, it will create three files:
-1. A source file in the source_root
-2. A header file in the source_root
-3. A test file in the test_root
-
-If you want your header file to be in another location,
-you can specify the ':inc_root:" in your project.yml file:
-```yaml
-:module_generator:
-  :inc_root: inc/
-```
-The module_generator will then create the header file in your defined ':inc_root:'.
-By default, ':inc_root:' is not defined so the module_generator will use the source_root.
-
-Sometimes, your project can't be divided into a single src, inc, and test folder. You have several directories
-with sources/..., something like this for example:
-<project_root>
- - myDriver
-   - src
-   - inc
-   - test
- - myOtherDriver
-   - src
-   - inc
-   - test
- - ...
-
-Don't worry, you don't have to manually create the source/header/test files.
-The module_generator can accept a path to create a source_root/inc_root/test_root folder with your files:
-`ceedling module:create[<module_root_path>:<module_name>]`
-
-F.e., applied to the above project structure:
-`ceedling module:create[myOtherDriver:driver]`
-This will make the module_generator run in the subdirectory 'myOtherDriver' and generate the module files
-for you in that directory. So, this command will generate the following files:
-1. A source file 'driver.c' in <project_root>/myOtherDriver/<source_root>
-2. A header file 'driver.h' in <project_root>/myOtherDriver/<source_root> (or <inc_root> if specified)
-3. A test file 'test_driver.c' in <project_root>/myOtherDriver/<test_root>
-
-Naming
--------------------------------------------
-By default, the module_generator will generate your files in lowercase.
-`ceedling module:create[mydriver]` and `ceedling module:create[myDriver]`(note the uppercase) will generate the same files:
-1. mydriver.c
-2. mydriver.h
-3. test_mydriver.c
-
-You can configure the module_generator to use a differect naming mechanism through the project.yml:
-```yaml
-:module_generator:
-  :naming: "camel"
-```
-There are other possibilities as well (bumpy, camel, snake, caps).
-Refer to the unity module generator for more info (the unity module generator is used under the hood by module_generator).
-
-Advanced Topics (Coming)
-========================
-
-Modifying Your Configuration without Modifying Your Project File: Option Files & User Files
--------------------------------------------------------------------------------------------
-
-Modifying your project file without modifying your project file
-
-Debugging and/or printf()
--------------------------
-
-When you gotta get your hands dirty...
-
-Ceedling Plays Nice with Others - Using Ceedling for Tests Alongside Another Release Build Setup
-------------------------------------------------------------------------------------------------
-
-You've got options.
-
-Adding Handy Rake Tasks for Your Project (without Fancy Pants Custom Plugins)
------------------------------------------------------------------------------
-
-Simple as snot.
-
-Working with Non-Desktop Testing Environments
----------------------------------------------
-
-For those crazy platforms lacking command line simulators and for which
-cross-compiling on the desktop just ain't gonna get it done.
-
-Creating Custom Plugins
------------------------
-
-Oh boy. This is going to take some explaining.
diff --git a/test/vendor/ceedling/docs/ThrowTheSwitchCodingStandard.md b/test/vendor/ceedling/docs/ThrowTheSwitchCodingStandard.md
deleted file mode 100644
index bf4c099bb..000000000
--- a/test/vendor/ceedling/docs/ThrowTheSwitchCodingStandard.md
+++ /dev/null
@@ -1,206 +0,0 @@
-# ThrowTheSwitch.org Coding Standard
-
-Hi. Welcome to the coding standard for ThrowTheSwitch.org. For the most part,
-we try to follow these standards to unify our contributors' code into a cohesive
-unit (puns intended). You might find places where these standards aren't
-followed. We're not perfect. Please be polite where you notice these discrepancies
-and we'll try to be polite when we notice yours.
-
-;)
-
-
-## Why Have A Coding Standard?
-
-Being consistent makes code easier to understand. We've tried to keep
-our standard simple because we also believe that we can only expect someone to
-follow something that is understandable. Please do your best.
-
-
-## Our Philosophy
-
-Before we get into details on syntax, let's take a moment to talk about our
-vision for these tools. We're C developers and embedded software developers.
-These tools are great to test any C code, but catering to embedded software has
-made us more tolerant of compiler quirks. There are a LOT of quirky compilers
-out there. By quirky I mean "doesn't follow standards because they feel like
-they have a license to do as they wish."
-
-Our philosophy is "support every compiler we can". Most often, this means that
-we aim for writing C code that is standards compliant (often C89... that seems
-to be a sweet spot that is almost always compatible). But it also means these
-tools are tolerant of things that aren't common. Some that aren't even
-compliant. There are configuration options to override the size of standard
-types. There are configuration options to force Unity to not use certain
-standard library functions. A lot of Unity is configurable and we have worked
-hard to make it not TOO ugly in the process.
-
-Similarly, our tools that parse C do their best. They aren't full C parsers
-(yet) and, even if they were, they would still have to accept non-standard
-additions like gcc extensions or specifying `@0x1000` to force a variable to
-compile to a particular location. It's just what we do, because we like
-everything to Just Workâ„¢.
-
-Speaking of having things Just Workâ„¢, that's our second philosophy. By that, we
-mean that we do our best to have EVERY configuration option have a logical
-default. We believe that if you're working with a simple compiler and target,
-you shouldn't need to configure very much... we try to make the tools guess as
-much as they can, but give the user the power to override it when it's wrong.
-
-
-## Naming Things
-
-Let's talk about naming things. Programming is all about naming things. We name
-files, functions, variables, and so much more. While we're not always going to
-find the best name for something, we actually put a bit of effort into
-finding *What Something WANTS to be Called*â„¢.
-
-When naming things, we follow this hierarchy, the first being the
-most important to us (but we do all four when possible):
-1. Readable
-2. Descriptive
-3. Consistent
-4. Memorable
-
-
-#### Readable
-
-We want to read our code. This means we like names and flow that are more
-naturally read. We try to avoid double negatives. We try to avoid cryptic
-abbreviations (sticking to ones we feel are common).
-
-
-#### Descriptive
-
-We like descriptive names for things, especially functions and variables.
-Finding the right name for something is an important endeavor. You might notice
-from poking around our code that this often results in names that are a little
-longer than the average. Guilty. We're okay with a bit more typing if it
-means our code is easier to understand.
-
-There are two exceptions to this rule that we also stick to as religiously as
-possible:
-
-First, while we realize hungarian notation (and similar systems for encoding
-type information into variable names) is providing a more descriptive name, we
-feel that (for the average developer) it takes away from readability and is to be avoided.
-
-Second, loop counters and other local throw-away variables often have a purpose
-which is obvious. There's no need, therefore, to get carried away with complex
-naming. We find i, j, and k are better loop counters than loopCounterVar or
-whatnot. We only break this rule when we see that more description could improve
-understanding of an algorithm.
-
-
-#### Consistent
-
-We like consistency, but we're not really obsessed with it. We try to name our
-configuration macros in a consistent fashion... you'll notice a repeated use of
-UNITY_EXCLUDE_BLAH or UNITY_USES_BLAH macros. This helps users avoid having to
-remember each macro's details.
-
-
-#### Memorable
-
-Where ever it doesn't violate the above principles, we try to apply memorable
-names. Sometimes this means using something that is simply descriptive, but
-often we strive for descriptive AND unique... we like quirky names that stand
-out in our memory and are easier to search for. Take a look through the file
-names in Ceedling and you'll get a good idea of what we are talking about here.
-Why use preprocess when you can use preprocessinator? Or what better describes a
-module in charge of invoking tasks during releases than release_invoker? Don't
-get carried away. The names are still descriptive and fulfill the above
-requirements, but they don't feel stale.
-
-
-## C and C++ Details
-
-We don't really want to add to the style battles out there. Tabs or spaces?
-How many spaces? Where do the braces go? These are age-old questions that will
-never be answered... or at least not answered in a way that will make everyone
-happy.
-
-We've decided on our own style preferences. If you'd like to contribute to these
-projects (and we hope that you do), then we ask if you do your best to follow
-the same. It will only hurt a little. We promise.
-
-
-#### Whitespace
-
-Our C-style is to use spaces and to use 4 of them per indent level. It's a nice
-power-of-2 number that looks decent on a wide-screen. We have no more reason
-than that. We break that rule when we have lines that wrap (macros or function
-arguments or whatnot). When that happens, we like to indent further to line
-things up in nice tidy columns.
-
-```C
-    if (stuff_happened)
-    {
-        do_something();
-    }
-```
-
-
-#### Case
-
-- Files - all lower case with underscores.
-- Variables - all lower case with underscores
-- Macros - all caps with underscores.
-- Typedefs - all caps with underscores. (also ends with _T).
-- Functions - camel cased. Usually named ModuleName_FuncName
-- Constants and Globals - camel cased.
-
-
-#### Braces
-
-The left brace is on the next line after the declaration. The right brace is
-directly below that. Everything in between in indented one level. If you're
-catching an error and you have a one-line, go ahead and to it on the same line.
-
-```C
-    while (blah)
-    {
-        //Like so. Even if only one line, we use braces.
-    }
-```
-
-
-#### Comments
-
-Do you know what we hate? Old-school C block comments. BUT, we're using them
-anyway. As we mentioned, our goal is to support every compiler we can,
-especially embedded compilers. There are STILL C compilers out there that only
-support old-school block comments. So that is what we're using. We apologize. We
-think they are ugly too.
-
-
-## Ruby Details
-
-Is there really such thing as a Ruby coding standard? Ruby is such a free form
-language, it seems almost sacrilegious to suggest that people should comply to
-one method! We'll keep it really brief!
-
-
-#### Whitespace
-
-Our Ruby style is to use spaces and to use 2 of them per indent level. It's a
-nice power-of-2 number that really grooves with Ruby's compact style. We have no
-more reason than that. We break that rule when we have lines that wrap. When
-that happens, we like to indent further to line things up in nice tidy columns.
-
-
-#### Case
-
-- Files - all lower case with underscores.
-- Variables - all lower case with underscores
-- Classes, Modules, etc - Camel cased.
-- Functions - all lower case with underscores
-- Constants - all upper case with underscores
-
-
-## Documentation
-
-Egad. Really? We use mark down and we like pdf files because they can be made to
-look nice while still being portable. Good enough?
-
-
-*Find The Latest of This And More at [ThrowTheSwitch.org](https://throwtheswitch.org)*
diff --git a/test/vendor/ceedling/docs/UnityAssertionsCheatSheetSuitableforPrintingandPossiblyFraming.pdf b/test/vendor/ceedling/docs/UnityAssertionsCheatSheetSuitableforPrintingandPossiblyFraming.pdf
deleted file mode 100644
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diff --git a/test/vendor/ceedling/docs/UnityAssertionsReference.md b/test/vendor/ceedling/docs/UnityAssertionsReference.md
deleted file mode 100644
index eb855f3c0..000000000
--- a/test/vendor/ceedling/docs/UnityAssertionsReference.md
+++ /dev/null
@@ -1,779 +0,0 @@
-# Unity Assertions Reference
-
-## Background and Overview
-
-### Super Condensed Version
-
-- An assertion establishes truth (i.e. boolean True) for a single condition.
-Upon boolean False, an assertion stops execution and reports the failure.
-- Unity is mainly a rich collection of assertions and the support to gather up
-and easily execute those assertions.
-- The structure of Unity allows you to easily separate test assertions from
-source code in, well, test code.
-- Unity's assertions:
-- Come in many, many flavors to handle different C types and assertion cases.
-- Use context to provide detailed and helpful failure messages.
-- Document types, expected values, and basic behavior in your source code for
-free.
-
-
-### Unity Is Several Things But Mainly It's Assertions
-
-One way to think of Unity is simply as a rich collection of assertions you can
-use to establish whether your source code behaves the way you think it does.
-Unity provides a framework to easily organize and execute those assertions in
-test code separate from your source code.
-
-
-### What's an Assertion?
-
-At their core, assertions are an establishment of truth - boolean truth. Was this
-thing equal to that thing? Does that code doohickey have such-and-such property
-or not? You get the idea. Assertions are executable code (to appreciate the big
-picture on this read up on the difference between
-[link:Dynamic Verification and Static Analysis]). A failing assertion stops
-execution and reports an error through some appropriate I/O channel (e.g.
-stdout, GUI, file, blinky light).
-
-Fundamentally, for dynamic verification all you need is a single assertion
-mechanism. In fact, that's what the [assert() macro in C's standard library](http://en.wikipedia.org/en/wiki/Assert.h)
-is for. So why not just use it? Well, we can do far better in the reporting
-department. C's `assert()` is pretty dumb as-is and is particularly poor for
-handling common data types like arrays, structs, etc. And, without some other
-support, it's far too tempting to litter source code with C's `assert()`'s. It's
-generally much cleaner, manageable, and more useful to separate test and source
-code in the way Unity facilitates.
-
-
-### Unity's Assertions: Helpful Messages _and_ Free Source Code Documentation
-
-Asserting a simple truth condition is valuable, but using the context of the
-assertion is even more valuable. For instance, if you know you're comparing bit
-flags and not just integers, then why not use that context to give explicit,
-readable, bit-level feedback when an assertion fails?
-
-That's what Unity's collection of assertions do - capture context to give you
-helpful, meaningful assertion failure messages. In fact, the assertions
-themselves also serve as executable documentation about types and values in your
-source code. So long as your tests remain current with your source and all those
-tests pass, you have a detailed, up-to-date view of the intent and mechanisms in
-your source code. And due to a wondrous mystery, well-tested code usually tends
-to be well designed code.
-
-
-## Assertion Conventions and Configurations
-
-### Naming and Parameter Conventions
-
-The convention of assertion parameters generally follows this order:
-
-    TEST_ASSERT_X( {modifiers}, {expected}, actual, {size/count} )
-
-The very simplest assertion possible uses only a single "actual" parameter (e.g.
-a simple null check).
-
-"Actual" is the value being tested and unlike the other parameters in an
-assertion construction is the only parameter present in all assertion variants.
-"Modifiers" are masks, ranges, bit flag specifiers, floating point deltas.
-"Expected" is your expected value (duh) to compare to an "actual" value; it's
-marked as an optional parameter because some assertions only need a single
-"actual" parameter (e.g. null check).
-"Size/count" refers to string lengths, number of array elements, etc.
-
-Many of Unity's assertions are clear duplications in that the same data type
-is handled by several assertions. The differences among these are in how failure
-messages are presented. For instance, a `_HEX` variant of an assertion prints
-the expected and actual values of that assertion formatted as hexadecimal.
-
-
-#### TEST_ASSERT_X_MESSAGE Variants
-
-_All_ assertions are complemented with a variant that includes a simple string
-message as a final parameter. The string you specify is appended to an assertion
-failure message in Unity output.
-
-For brevity, the assertion variants with a message parameter are not listed
-below. Just tack on `_MESSAGE` as the final component to any assertion name in
-the reference list below and add a string as the final parameter.
-
-_Example:_
-
-    TEST_ASSERT_X( {modifiers}, {expected}, actual, {size/count} )
-
-becomes messageified like thus...
-
-    TEST_ASSERT_X_MESSAGE( {modifiers}, {expected}, actual, {size/count}, message )
-
-Notes:
-- The `_MESSAGE` variants intentionally do not support `printf` style formatting 
-  since many embedded projects don't support or avoid `printf` for various reasons.
-  It is possible to use `sprintf` before the assertion to assemble a complex fail
-  message, if necessary.
-- If you want to output a counter value within an assertion fail message (e.g. from 
-  a loop) , building up an array of results and then using one of the `_ARRAY` 
-  assertions (see below) might be a handy alternative to `sprintf`.
-
-
-#### TEST_ASSERT_X_ARRAY Variants
-
-Unity provides a collection of assertions for arrays containing a variety of
-types. These are documented in the Array section below. These are almost on par
-with the `_MESSAGE`variants of Unity's Asserts in that for pretty much any Unity
-type assertion you can tack on `_ARRAY` and run assertions on an entire block of
-memory.
-
-    TEST_ASSERT_EQUAL_TYPEX_ARRAY( expected, actual, {size/count} )
-
-"Expected" is an array itself.
-"Size/count" is one or two parameters necessary to establish the number of array
-elements and perhaps the length of elements within the array.
-
-Notes:
-- The `_MESSAGE` variant convention still applies here to array assertions. The
-`_MESSAGE` variants of the `_ARRAY` assertions have names ending with
-`_ARRAY_MESSAGE`.
-- Assertions for handling arrays of floating point values are grouped with float
-and double assertions (see immediately following section).
-
-
-### TEST_ASSERT_EACH_EQUAL_X Variants
-
-Unity provides a collection of assertions for arrays containing a variety of
-types which can be compared to a single value as well. These are documented in
-the Each Equal section below. these are almost on par with the `_MESSAGE`
-variants of Unity's Asserts in that for pretty much any Unity type assertion you
-can inject _EACH_EQUAL and run assertions on an entire block of memory.
-
-    TEST_ASSERT_EACH_EQUAL_TYPEX( expected, actual, {size/count} )
-
-"Expected" is a single value to compare to.
-"Actual" is an array where each element will be compared to the expected value.
-"Size/count" is one of two parameters necessary to establish the number of array
-elements and perhaps the length of elements within the array.
-
-Notes:
-- The `_MESSAGE` variant convention still applies here to Each Equal assertions.
-- Assertions for handling Each Equal of floating point values are grouped with
-float and double assertions (see immediately following section).
-
-
-### Configuration
-
-#### Floating Point Support Is Optional
-
-Support for floating point types is configurable. That is, by defining the
-appropriate preprocessor symbols, floats and doubles can be individually enabled
-or disabled in Unity code. This is useful for embedded targets with no floating
-point math support (i.e. Unity compiles free of errors for fixed point only
-platforms). See Unity documentation for specifics.
-
-
-#### Maximum Data Type Width Is Configurable
-
-Not all targets support 64 bit wide types or even 32 bit wide types. Define the
-appropriate preprocessor symbols and Unity will omit all operations from
-compilation that exceed the maximum width of your target. See Unity
-documentation for specifics.
-
-
-## The Assertions in All Their Blessed Glory
-
-### Basic Fail and Ignore
-
-##### `TEST_FAIL()`
-
-This fella is most often used in special conditions where your test code is
-performing logic beyond a simple assertion. That is, in practice, `TEST_FAIL()`
-will always be found inside a conditional code block.
-
-_Examples:_
-- Executing a state machine multiple times that increments a counter your test
-code then verifies as a final step.
-- Triggering an exception and verifying it (as in Try / Catch / Throw - see the
-[CException](https://github.com/ThrowTheSwitch/CException) project).
-
-##### `TEST_IGNORE()`
-
-Marks a test case (i.e. function meant to contain test assertions) as ignored.
-Usually this is employed as a breadcrumb to come back and implement a test case.
-An ignored test case has effects if other assertions are in the enclosing test
-case (see Unity documentation for more).
-
-### Boolean
-
-##### `TEST_ASSERT (condition)`
-
-##### `TEST_ASSERT_TRUE (condition)`
-
-##### `TEST_ASSERT_FALSE (condition)`
-
-##### `TEST_ASSERT_UNLESS (condition)`
-
-A simple wording variation on `TEST_ASSERT_FALSE`.The semantics of
-`TEST_ASSERT_UNLESS` aid readability in certain test constructions or
-conditional statements.
-
-##### `TEST_ASSERT_NULL (pointer)`
-
-##### `TEST_ASSERT_NOT_NULL (pointer)`
-
-
-### Signed and Unsigned Integers (of all sizes)
-
-Large integer sizes can be disabled for build targets that do not support them.
-For example, if your target only supports up to 16 bit types, by defining the
-appropriate symbols Unity can be configured to omit 32 and 64 bit operations
-that would break compilation (see Unity documentation for more). Refer to
-Advanced Asserting later in this document for advice on dealing with other word
-sizes.
-
-##### `TEST_ASSERT_EQUAL_INT (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_INT8 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_INT16 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_INT32 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_INT64 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL (expected, actual)`
-
-##### `TEST_ASSERT_NOT_EQUAL (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_UINT (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_UINT8 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_UINT16 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_UINT32 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_UINT64 (expected, actual)`
-
-
-### Unsigned Integers (of all sizes) in Hexadecimal
-
-All `_HEX` assertions are identical in function to unsigned integer assertions
-but produce failure messages with the `expected` and `actual` values formatted
-in hexadecimal. Unity output is big endian.
-
-##### `TEST_ASSERT_EQUAL_HEX (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_HEX8 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_HEX16 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_HEX32 (expected, actual)`
-
-##### `TEST_ASSERT_EQUAL_HEX64 (expected, actual)`
-
-
-### Masked and Bit-level Assertions
-
-Masked and bit-level assertions produce output formatted in hexadecimal. Unity
-output is big endian.
-
-
-##### `TEST_ASSERT_BITS (mask, expected, actual)`
-
-Only compares the masked (i.e. high) bits of `expected` and `actual` parameters.
-
-
-##### `TEST_ASSERT_BITS_HIGH (mask, actual)`
-
-Asserts the masked bits of the `actual` parameter are high.
-
-
-##### `TEST_ASSERT_BITS_LOW (mask, actual)`
-
-Asserts the masked bits of the `actual` parameter are low.
-
-
-##### `TEST_ASSERT_BIT_HIGH (bit, actual)`
-
-Asserts the specified bit of the `actual` parameter is high.
-
-
-##### `TEST_ASSERT_BIT_LOW (bit, actual)`
-
-Asserts the specified bit of the `actual` parameter is low.
-
-### Integer Less Than / Greater Than
-
-These assertions verify that the `actual` parameter is less than or greater
-than `threshold` (exclusive). For example, if the threshold value is 0 for the
-greater than assertion will fail if it is 0 or less.
-
-##### `TEST_ASSERT_GREATER_THAN (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_INT (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_INT8 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_INT16 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_INT32 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_UINT (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_UINT8 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_UINT16 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_UINT32 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_HEX8 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_HEX16 (threshold, actual)`
-
-##### `TEST_ASSERT_GREATER_THAN_HEX32 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_INT (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_INT8 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_INT16 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_INT32 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_UINT (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_UINT8 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_UINT16 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_UINT32 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_HEX8 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_HEX16 (threshold, actual)`
-
-##### `TEST_ASSERT_LESS_THAN_HEX32 (threshold, actual)`
-
-
-### Integer Ranges (of all sizes)
-
-These assertions verify that the `expected` parameter is within +/- `delta`
-(inclusive) of the `actual` parameter. For example, if the expected value is 10
-and the delta is 3 then the assertion will fail for any value outside the range
-of 7 - 13.
-
-##### `TEST_ASSERT_INT_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_INT8_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_INT16_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_INT32_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_INT64_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_UINT_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_UINT8_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_UINT16_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_UINT32_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_UINT64_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_HEX_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_HEX8_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_HEX16_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_HEX32_WITHIN (delta, expected, actual)`
-
-##### `TEST_ASSERT_HEX64_WITHIN (delta, expected, actual)`
-
-
-### Structs and Strings
-
-##### `TEST_ASSERT_EQUAL_PTR (expected, actual)`
-
-Asserts that the pointers point to the same memory location.
-
-
-##### `TEST_ASSERT_EQUAL_STRING (expected, actual)`
-
-Asserts that the null terminated (`'\0'`)strings are identical. If strings are
-of different lengths or any portion of the strings before their terminators
-differ, the assertion fails. Two NULL strings (i.e. zero length) are considered
-equivalent.
-
-
-##### `TEST_ASSERT_EQUAL_MEMORY (expected, actual, len)`
-
-Asserts that the contents of the memory specified by the `expected` and `actual`
-pointers is identical. The size of the memory blocks in bytes is specified by
-the `len` parameter.
-
-
-### Arrays
-
-`expected` and `actual` parameters are both arrays. `num_elements` specifies the
-number of elements in the arrays to compare.
-
-`_HEX` assertions produce failure messages with expected and actual array
-contents formatted in hexadecimal.
-
-For array of strings comparison behavior, see comments for
-`TEST_ASSERT_EQUAL_STRING` in the preceding section.
-
-Assertions fail upon the first element in the compared arrays found not to
-match. Failure messages specify the array index of the failed comparison.
-
-##### `TEST_ASSERT_EQUAL_INT_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_INT8_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_INT16_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_INT32_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_INT64_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_UINT_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_UINT8_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_UINT16_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_UINT32_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_UINT64_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_HEX_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_HEX8_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_HEX16_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_HEX32_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_HEX64_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_PTR_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_STRING_ARRAY (expected, actual, num_elements)`
-
-##### `TEST_ASSERT_EQUAL_MEMORY_ARRAY (expected, actual, len, num_elements)`
-
-`len` is the memory in bytes to be compared at each array element.
-
-
-### Each Equal (Arrays to Single Value)
-
-`expected` are single values and `actual` are arrays. `num_elements` specifies
-the number of elements in the arrays to compare.
-
-`_HEX` assertions produce failure messages with expected and actual array
-contents formatted in hexadecimal.
-
-Assertions fail upon the first element in the compared arrays found not to
-match. Failure messages specify the array index of the failed comparison.
-
-#### `TEST_ASSERT_EACH_EQUAL_INT (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_INT8 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_INT16 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_INT32 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_INT64 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_UINT (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_UINT8 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_UINT16 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_UINT32 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_UINT64 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_HEX (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_HEX8 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_HEX16 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_HEX32 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_HEX64 (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_PTR (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_STRING (expected, actual, num_elements)`
-
-#### `TEST_ASSERT_EACH_EQUAL_MEMORY (expected, actual, len, num_elements)`
-
-`len` is the memory in bytes to be compared at each array element.
-
-
-### Floating Point (If enabled)
-
-##### `TEST_ASSERT_FLOAT_WITHIN (delta, expected, actual)`
-
-Asserts that the `actual` value is within +/- `delta` of the `expected` value.
-The nature of floating point representation is such that exact evaluations of
-equality are not guaranteed.
-
-
-##### `TEST_ASSERT_EQUAL_FLOAT (expected, actual)`
-
-Asserts that the ?actual?value is "close enough to be considered equal" to the
-`expected` value. If you are curious about the details, refer to the Advanced
-Asserting section for more details on this. Omitting a user-specified delta in a
-floating point assertion is both a shorthand convenience and a requirement of
-code generation conventions for CMock.
-
-
-##### `TEST_ASSERT_EQUAL_FLOAT_ARRAY (expected, actual, num_elements)`
-
-See Array assertion section for details. Note that individual array element
-float comparisons are executed using T?EST_ASSERT_EQUAL_FLOAT?.That is, user
-specified delta comparison values requires a custom-implemented floating point
-array assertion.
-
-
-##### `TEST_ASSERT_FLOAT_IS_INF (actual)`
-
-Asserts that `actual` parameter is equivalent to positive infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NEG_INF (actual)`
-
-Asserts that `actual` parameter is equivalent to negative infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NAN (actual)`
-
-Asserts that `actual` parameter is a Not A Number floating point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_DETERMINATE (actual)`
-
-Asserts that ?actual?parameter is a floating point representation usable for
-mathematical operations. That is, the `actual` parameter is neither positive
-infinity nor negative infinity nor Not A Number floating point representations.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NOT_INF (actual)`
-
-Asserts that `actual` parameter is a value other than positive infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NOT_NEG_INF (actual)`
-
-Asserts that `actual` parameter is a value other than negative infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NOT_NAN (actual)`
-
-Asserts that `actual` parameter is a value other than Not A Number floating
-point representation.
-
-
-##### `TEST_ASSERT_FLOAT_IS_NOT_DETERMINATE (actual)`
-
-Asserts that `actual` parameter is not usable for mathematical operations. That
-is, the `actual` parameter is either positive infinity or negative infinity or
-Not A Number floating point representations.
-
-
-### Double (If enabled)
-
-##### `TEST_ASSERT_DOUBLE_WITHIN (delta, expected, actual)`
-
-Asserts that the `actual` value is within +/- `delta` of the `expected` value.
-The nature of floating point representation is such that exact evaluations of
-equality are not guaranteed.
-
-
-##### `TEST_ASSERT_EQUAL_DOUBLE (expected, actual)`
-
-Asserts that the `actual` value is "close enough to be considered equal" to the
-`expected` value. If you are curious about the details, refer to the Advanced
-Asserting section for more details. Omitting a user-specified delta in a
-floating point assertion is both a shorthand convenience and a requirement of
-code generation conventions for CMock.
-
-
-##### `TEST_ASSERT_EQUAL_DOUBLE_ARRAY (expected, actual, num_elements)`
-
-See Array assertion section for details. Note that individual array element
-double comparisons are executed using `TEST_ASSERT_EQUAL_DOUBLE`.That is, user
-specified delta comparison values requires a custom implemented double array
-assertion.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_INF (actual)`
-
-Asserts that `actual` parameter is equivalent to positive infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NEG_INF (actual)`
-
-Asserts that `actual` parameter is equivalent to negative infinity floating point
-representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NAN (actual)`
-
-Asserts that `actual` parameter is a Not A Number floating point representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_DETERMINATE (actual)`
-
-Asserts that `actual` parameter is a floating point representation usable for
-mathematical operations. That is, the ?actual?parameter is neither positive
-infinity nor negative infinity nor Not A Number floating point representations.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NOT_INF (actual)`
-
-Asserts that `actual` parameter is a value other than positive infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NOT_NEG_INF (actual)`
-
-Asserts that `actual` parameter is a value other than negative infinity floating
-point representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NOT_NAN (actual)`
-
-Asserts that `actual` parameter is a value other than Not A Number floating
-point representation.
-
-
-##### `TEST_ASSERT_DOUBLE_IS_NOT_DETERMINATE (actual)`
-
-Asserts that `actual` parameter is not usable for mathematical operations. That
-is, the `actual` parameter is either positive infinity or negative infinity or
-Not A Number floating point representations.
-
-
-## Advanced Asserting: Details On Tricky Assertions
-
-This section helps you understand how to deal with some of the trickier
-assertion situations you may run into. It will give you a glimpse into some of
-the under-the-hood details of Unity's assertion mechanisms. If you're one of
-those people who likes to know what is going on in the background, read on. If
-not, feel free to ignore the rest of this document until you need it.
-
-
-### How do the EQUAL assertions work for FLOAT and DOUBLE?
-
-As you may know, directly checking for equality between a pair of floats or a
-pair of doubles is sloppy at best and an outright no-no at worst. Floating point
-values can often be represented in multiple ways, particularly after a series of
-operations on a value. Initializing a variable to the value of 2.0 is likely to
-result in a floating point representation of 2 x 20,but a series of
-mathematical operations might result in a representation of 8 x 2-2
-that also evaluates to a value of 2. At some point repeated operations cause
-equality checks to fail.
-
-So Unity doesn't do direct floating point comparisons for equality. Instead, it
-checks if two floating point values are "really close." If you leave Unity
-running with defaults, "really close" means "within a significant bit or two."
-Under the hood, `TEST_ASSERT_EQUAL_FLOAT` is really `TEST_ASSERT_FLOAT_WITHIN`
-with the `delta` parameter calculated on the fly. For single precision, delta is
-the expected value multiplied by 0.00001, producing a very small proportional
-range around the expected value.
-
-If you are expecting a value of 20,000.0 the delta is calculated to be 0.2. So
-any value between 19,999.8 and 20,000.2 will satisfy the equality check. This
-works out to be roughly a single bit of range for a single-precision number, and
-that's just about as tight a tolerance as you can reasonably get from a floating
-point value.
-
-So what happens when it's zero? Zero - even more than other floating point
-values - can be represented many different ways. It doesn't matter if you have
-0 x 20 or 0 x 263.It's still zero, right? Luckily, if you
-subtract these values from each other, they will always produce a difference of
-zero, which will still fall between 0 plus or minus a delta of 0. So it still
-works!
-
-Double precision floating point numbers use a much smaller multiplier, again
-approximating a single bit of error.
-
-If you don't like these ranges and you want to make your floating point equality
-assertions less strict, you can change these multipliers to whatever you like by
-defining UNITY_FLOAT_PRECISION and UNITY_DOUBLE_PRECISION. See Unity
-documentation for more.
-
-
-### How do we deal with targets with non-standard int sizes?
-
-It's "fun" that C is a standard where something as fundamental as an integer
-varies by target. According to the C standard, an `int` is to be the target's
-natural register size, and it should be at least 16-bits and a multiple of a
-byte. It also guarantees an order of sizes:
-
-```C
-char <= short <= int <= long <= long long
-```
-
-Most often, `int` is 32-bits. In many cases in the embedded world, `int` is
-16-bits. There are rare microcontrollers out there that have 24-bit integers,
-and this remains perfectly standard C.
-
-To make things even more interesting, there are compilers and targets out there
-that have a hard choice to make. What if their natural register size is 10-bits
-or 12-bits? Clearly they can't fulfill _both_ the requirement to be at least
-16-bits AND the requirement to match the natural register size. In these
-situations, they often choose the natural register size, leaving us with
-something like this:
-
-```C
-char (8 bit) <= short (12 bit) <= int (12 bit) <= long (16 bit)
-```
-
-Um... yikes. It's obviously breaking a rule or two... but they had to break SOME
-rules, so they made a choice.
-
-When the C99 standard rolled around, it introduced alternate standard-size types.
-It also introduced macros for pulling in MIN/MAX values for your integer types.
-It's glorious! Unfortunately, many embedded compilers can't be relied upon to
-use the C99 types (Sometimes because they have weird register sizes as described
-above. Sometimes because they don't feel like it?).
-
-A goal of Unity from the beginning was to support every combination of
-microcontroller or microprocessor and C compiler. Over time, we've gotten really
-close to this. There are a few tricks that you should be aware of, though, if
-you're going to do this effectively on some of these more idiosyncratic targets.
-
-First, when setting up Unity for a new target, you're going to want to pay
-special attention to the macros for automatically detecting types
-(where available) or manually configuring them yourself. You can get information
-on both of these in Unity's documentation.
-
-What about the times where you suddenly need to deal with something odd, like a
-24-bit `int`? The simplest solution is to use the next size up. If you have a
-24-bit `int`, configure Unity to use 32-bit integers. If you have a 12-bit
-`int`, configure Unity to use 16 bits. There are two ways this is going to
-affect you:
-
-1. When Unity displays errors for you, it's going to pad the upper unused bits
-with zeros.
-2. You're going to have to be careful of assertions that perform signed
-operations, particularly `TEST_ASSERT_INT_WITHIN`.Such assertions might wrap
-your `int` in the wrong place, and you could experience false failures. You can
-always back down to a simple `TEST_ASSERT` and do the operations yourself.
-
-
-*Find The Latest of This And More at [ThrowTheSwitch.org](https://throwtheswitch.org)*
diff --git a/test/vendor/ceedling/docs/UnityConfigurationGuide.md b/test/vendor/ceedling/docs/UnityConfigurationGuide.md
deleted file mode 100644
index dace20c54..000000000
--- a/test/vendor/ceedling/docs/UnityConfigurationGuide.md
+++ /dev/null
@@ -1,433 +0,0 @@
-# Unity Configuration Guide
-
-## C Standards, Compilers and Microcontrollers
-
-The embedded software world contains its challenges. Compilers support different
-revisions of the C Standard. They ignore requirements in places, sometimes to
-make the language more usable in some special regard. Sometimes it's to simplify
-their support. Sometimes it's due to specific quirks of the microcontroller they
-are targeting. Simulators add another dimension to this menagerie.
-
-Unity is designed to run on almost anything that is targeted by a C compiler. It
-would be awesome if this could be done with zero configuration. While there are
-some targets that come close to this dream, it is sadly not universal. It is
-likely that you are going to need at least a couple of the configuration options
-described in this document.
-
-All of Unity's configuration options are `#defines`. Most of these are simple
-definitions. A couple are macros with arguments. They live inside the
-unity_internals.h header file. We don't necessarily recommend opening that file
-unless you really need to. That file is proof that a cross-platform library is
-challenging to build. From a more positive perspective, it is also proof that a
-great deal of complexity can be centralized primarily to one place to
-provide a more consistent and simple experience elsewhere.
-
-
-### Using These Options
-
-It doesn't matter if you're using a target-specific compiler and a simulator or
-a native compiler. In either case, you've got a couple choices for configuring
-these options:
-
-1. Because these options are specified via C defines, you can pass most of these
-options to your compiler through command line compiler flags. Even if you're
-using an embedded target that forces you to use their overbearing IDE for all
-configuration, there will be a place somewhere in your project to configure
-defines for your compiler.
-2. You can create a custom `unity_config.h` configuration file (present in your
-toolchain's search paths). In this file, you will list definitions and macros
-specific to your target. All you must do is define `UNITY_INCLUDE_CONFIG_H` and
-Unity will rely on `unity_config.h` for any further definitions it may need.
-
-
-## The Options
-
-### Integer Types
-
-If you've been a C developer for long, you probably already know that C's
-concept of an integer varies from target to target. The C Standard has rules
-about the `int` matching the register size of the target microprocessor. It has
-rules about the `int` and how its size relates to other integer types. An `int`
-on one target might be 16 bits while on another target it might be 64. There are
-more specific types in compilers compliant with C99 or later, but that's
-certainly not every compiler you are likely to encounter. Therefore, Unity has a
-number of features for helping to adjust itself to match your required integer
-sizes. It starts off by trying to do it automatically.
-
-
-##### `UNITY_EXCLUDE_STDINT_H`
-
-The first thing that Unity does to guess your types is check `stdint.h`.
-This file includes defines like `UINT_MAX` that Unity can use to
-learn a lot about your system. It's possible you don't want it to do this
-(um. why not?) or (more likely) it's possible that your system doesn't
-support `stdint.h`. If that's the case, you're going to want to define this.
-That way, Unity will know to skip the inclusion of this file and you won't
-be left with a compiler error.
-
-_Example:_
-        #define UNITY_EXCLUDE_STDINT_H
-
-
-##### `UNITY_EXCLUDE_LIMITS_H`
-
-The second attempt to guess your types is to check `limits.h`. Some compilers
-that don't support `stdint.h` could include `limits.h` instead. If you don't
-want Unity to check this file either, define this to make it skip the inclusion.
-
-_Example:_
-        #define UNITY_EXCLUDE_LIMITS_H
-
-
-If you've disabled both of the automatic options above, you're going to have to
-do the configuration yourself. Don't worry. Even this isn't too bad... there are
-just a handful of defines that you are going to specify if you don't like the
-defaults.
-
-
-##### `UNITY_INT_WIDTH`
-
-Define this to be the number of bits an `int` takes up on your system. The
-default, if not autodetected, is 32 bits.
-
-_Example:_
-        #define UNITY_INT_WIDTH 16
-
-
-##### `UNITY_LONG_WIDTH`
-
-Define this to be the number of bits a `long` takes up on your system. The
-default, if not autodetected, is 32 bits. This is used to figure out what kind
-of 64-bit support your system can handle. Does it need to specify a `long` or a
-`long long` to get a 64-bit value. On 16-bit systems, this option is going to be
-ignored.
-
-_Example:_
-        #define UNITY_LONG_WIDTH 16
-
-
-##### `UNITY_POINTER_WIDTH`
-
-Define this to be the number of bits a pointer takes up on your system. The
-default, if not autodetected, is 32-bits. If you're getting ugly compiler
-warnings about casting from pointers, this is the one to look at.
-
-_Example:_
-        #define UNITY_POINTER_WIDTH 64
-
-
-##### `UNITY_SUPPORT_64`
-
-Unity will automatically include 64-bit support if it auto-detects it, or if
-your `int`, `long`, or pointer widths are greater than 32-bits. Define this to
-enable 64-bit support if none of the other options already did it for you. There
-can be a significant size and speed impact to enabling 64-bit support on small
-targets, so don't define it if you don't need it.
-
-_Example:_
-        #define UNITY_SUPPORT_64
-
-
-### Floating Point Types
-
-In the embedded world, it's not uncommon for targets to have no support for
-floating point operations at all or to have support that is limited to only
-single precision. We are able to guess integer sizes on the fly because integers
-are always available in at least one size. Floating point, on the other hand, is
-sometimes not available at all. Trying to include `float.h` on these platforms
-would result in an error. This leaves manual configuration as the only option.
-
-
-##### `UNITY_INCLUDE_FLOAT`
-
-##### `UNITY_EXCLUDE_FLOAT`
-
-##### `UNITY_INCLUDE_DOUBLE`
-
-##### `UNITY_EXCLUDE_DOUBLE`
-
-By default, Unity guesses that you will want single precision floating point
-support, but not double precision. It's easy to change either of these using the
-include and exclude options here. You may include neither, either, or both, as
-suits your needs. For features that are enabled, the following floating point
-options also become available.
-
-_Example:_
-
-        //what manner of strange processor is this?
-        #define UNITY_EXCLUDE_FLOAT
-        #define UNITY_INCLUDE_DOUBLE
-
-
-##### `UNITY_EXCLUDE_FLOAT_PRINT`
-
-Unity aims for as small of a footprint as possible and avoids most standard
-library calls (some embedded platforms don’t have a standard library!). Because
-of this, its routines for printing integer values are minimalist and hand-coded.
-Therefore, the display of floating point values during a failure are optional.
-By default, Unity will print the actual results of floating point assertion
-failure (e.g. �Expected 4.56 Was 4.68�). To not include this extra support, you
-can use this define to instead respond to a failed assertion with a message like
-�Values Not Within Delta�. If you would like verbose failure messages for floating
-point assertions, use these options to give more explicit failure messages.
-
-_Example:_
-        #define UNITY_EXCLUDE_FLOAT_PRINT
-
-
-##### `UNITY_FLOAT_TYPE`
-
-If enabled, Unity assumes you want your `FLOAT` asserts to compare standard C
-floats. If your compiler supports a specialty floating point type, you can
-always override this behavior by using this definition.
-
-_Example:_
-        #define UNITY_FLOAT_TYPE float16_t
-
-
-##### `UNITY_DOUBLE_TYPE`
-
-If enabled, Unity assumes you want your `DOUBLE` asserts to compare standard C
-doubles. If you would like to change this, you can specify something else by
-using this option. For example, defining `UNITY_DOUBLE_TYPE` to `long double`
-could enable gargantuan floating point types on your 64-bit processor instead of
-the standard `double`.
-
-_Example:_
-        #define UNITY_DOUBLE_TYPE long double
-
-
-##### `UNITY_FLOAT_PRECISION`
-
-##### `UNITY_DOUBLE_PRECISION`
-
-If you look up `UNITY_ASSERT_EQUAL_FLOAT` and `UNITY_ASSERT_EQUAL_DOUBLE` as
-documented in the big daddy Unity Assertion Guide, you will learn that they are
-not really asserting that two values are equal but rather that two values are
-"close enough" to equal. "Close enough" is controlled by these precision
-configuration options. If you are working with 32-bit floats and/or 64-bit
-doubles (the normal on most processors), you should have no need to change these
-options. They are both set to give you approximately 1 significant bit in either
-direction. The float precision is 0.00001 while the double is 10-12.
-For further details on how this works, see the appendix of the Unity Assertion
-Guide.
-
-_Example:_
-        #define UNITY_FLOAT_PRECISION 0.001f
-
-
-### Toolset Customization
-
-In addition to the options listed above, there are a number of other options
-which will come in handy to customize Unity's behavior for your specific
-toolchain. It is possible that you may not need to touch any of these... but
-certain platforms, particularly those running in simulators, may need to jump
-through extra hoops to run properly. These macros will help in those
-situations.
-
-
-##### `UNITY_OUTPUT_CHAR(a)`
-
-##### `UNITY_OUTPUT_FLUSH()`
-
-##### `UNITY_OUTPUT_START()`
-
-##### `UNITY_OUTPUT_COMPLETE()`
-
-By default, Unity prints its results to `stdout` as it runs. This works
-perfectly fine in most situations where you are using a native compiler for
-testing. It works on some simulators as well so long as they have `stdout`
-routed back to the command line. There are times, however, where the simulator
-will lack support for dumping results or you will want to route results
-elsewhere for other reasons. In these cases, you should define the
-`UNITY_OUTPUT_CHAR` macro. This macro accepts a single character at a time (as
-an `int`, since this is the parameter type of the standard C `putchar` function
-most commonly used). You may replace this with whatever function call you like.
-
-_Example:_
-Say you are forced to run your test suite on an embedded processor with no
-`stdout` option. You decide to route your test result output to a custom serial
-`RS232_putc()` function you wrote like thus:
-        #include "RS232_header.h"
-        ...
-        #define UNITY_OUTPUT_CHAR(a) RS232_putc(a)
-        #define UNITY_OUTPUT_START() RS232_config(115200,1,8,0)
-        #define UNITY_OUTPUT_FLUSH() RS232_flush()
-        #define UNITY_OUTPUT_COMPLETE() RS232_close()
-
-_Note:_
-`UNITY_OUTPUT_FLUSH()` can be set to the standard out flush function simply by
-specifying `UNITY_USE_FLUSH_STDOUT`. No other defines are required.
-
-
-##### `UNITY_WEAK_ATTRIBUTE`
-
-##### `UNITY_WEAK_PRAGMA`
-
-##### `UNITY_NO_WEAK`
-
-For some targets, Unity can make the otherwise required setUp() and tearDown()
-functions optional. This is a nice convenience for test writers since setUp and
-tearDown don’t often actually do anything. If you’re using gcc or clang, this
-option is automatically defined for you. Other compilers can also support this
-behavior, if they support a C feature called weak functions. A weak function is
-a function that is compiled into your executable unless a non-weak version of
-the same function is defined elsewhere. If a non-weak version is found, the weak
-version is ignored as if it never existed. If your compiler supports this feature,
-you can let Unity know by defining UNITY_WEAK_ATTRIBUTE or UNITY_WEAK_PRAGMA as
-the function attributes that would need to be applied to identify a function as
-weak. If your compiler lacks support for weak functions, you will always need to
-define setUp and tearDown functions (though they can be and often will be just
-empty). You can also force Unity to NOT use weak functions by defining
-UNITY_NO_WEAK. The most common options for this feature are:
-
-_Example:_
-        #define UNITY_WEAK_ATTRIBUTE weak
-        #define UNITY_WEAK_ATTRIBUTE __attribute__((weak))
-        #define UNITY_WEAK_PRAGMA
-        #define UNITY_NO_WEAK
-
-
-##### `UNITY_PTR_ATTRIBUTE`
-
-Some compilers require a custom attribute to be assigned to pointers, like
-`near` or `far`. In these cases, you can give Unity a safe default for these by
-defining this option with the attribute you would like.
-
-_Example:_
-        #define UNITY_PTR_ATTRIBUTE __attribute__((far))
-        #define UNITY_PTR_ATTRIBUTE near
-
-
-##### `UNITY_PRINT_EOL`
-
-By default, Unity outputs \n at the end of each line of output. This is easy
-to parse by the scripts, by Ceedling, etc, but it might not be ideal for YOUR
-system. Feel free to override this and to make it whatever you wish.
-
-_Example:_
-        #define UNITY_PRINT_EOL { UNITY_OUTPUT_CHAR('\r'); UNITY_OUTPUT_CHAR('\n') }
-
-
-
-##### `UNITY_EXCLUDE_DETAILS`
-
-This is an option for if you absolutely must squeeze every byte of memory out of
-your system. Unity stores a set of internal scratchpads which are used to pass
-extra detail information around. It's used by systems like CMock in order to
-report which function or argument flagged an error. If you're not using CMock and
-you're not using these details for other things, then you can exclude them.
-
-_Example:_
-        #define UNITY_EXCLUDE_DETAILS
-
-
-
-##### `UNITY_EXCLUDE_SETJMP`
-
-If your embedded system doesn't support the standard library setjmp, you can
-exclude Unity's reliance on this by using this define. This dropped dependence
-comes at a price, though. You will be unable to use custom helper functions for
-your tests, and you will be unable to use tools like CMock. Very likely, if your
-compiler doesn't support setjmp, you wouldn't have had the memory space for those
-things anyway, though... so this option exists for those situations.
-
-_Example:_
-        #define UNITY_EXCLUDE_SETJMP
-
-##### `UNITY_OUTPUT_COLOR`
-
-If you want to add color using ANSI escape codes you can use this define.
-t
-_Example:_
-        #define UNITY_OUTPUT_COLOR
-
-
-
-## Getting Into The Guts
-
-There will be cases where the options above aren't quite going to get everything
-perfect. They are likely sufficient for any situation where you are compiling
-and executing your tests with a native toolchain (e.g. clang on Mac). These
-options may even get you through the majority of cases encountered in working
-with a target simulator run from your local command line. But especially if you
-must run your test suite on your target hardware, your Unity configuration will
-require special help. This special help will usually reside in one of two
-places: the `main()` function or the `RUN_TEST` macro. Let's look at how these
-work.
-
-
-##### `main()`
-
-Each test module is compiled and run on its own, separate from the other test
-files in your project. Each test file, therefore, has a `main` function. This
-`main` function will need to contain whatever code is necessary to initialize
-your system to a workable state. This is particularly true for situations where
-you must set up a memory map or initialize a communication channel for the
-output of your test results.
-
-A simple main function looks something like this:
-
-        int main(void) {
-            UNITY_BEGIN();
-            RUN_TEST(test_TheFirst);
-            RUN_TEST(test_TheSecond);
-            RUN_TEST(test_TheThird);
-            return UNITY_END();
-        }
-
-You can see that our main function doesn't bother taking any arguments. For our
-most barebones case, we'll never have arguments because we just run all the
-tests each time. Instead, we start by calling `UNITY_BEGIN`. We run each test
-(in whatever order we wish). Finally, we call `UNITY_END`, returning its return
-value (which is the total number of failures).
-
-It should be easy to see that you can add code before any test cases are run or
-after all the test cases have completed. This allows you to do any needed
-system-wide setup or teardown that might be required for your special
-circumstances.
-
-
-##### `RUN_TEST`
-
-The `RUN_TEST` macro is called with each test case function. Its job is to
-perform whatever setup and teardown is necessary for executing a single test
-case function. This includes catching failures, calling the test module's
-`setUp()` and `tearDown()` functions, and calling `UnityConcludeTest()`. If
-using CMock or test coverage, there will be additional stubs in use here. A
-simple minimalist RUN_TEST macro looks something like this:
-
-        #define RUN_TEST(testfunc) \
-            UNITY_NEW_TEST(#testfunc) \
-            if (TEST_PROTECT()) { \
-                setUp(); \
-                testfunc(); \
-            } \
-            if (TEST_PROTECT() && (!TEST_IS_IGNORED)) \
-                tearDown(); \
-            UnityConcludeTest();
-
-So that's quite a macro, huh? It gives you a glimpse of what kind of stuff Unity
-has to deal with for every single test case. For each test case, we declare that
-it is a new test. Then we run `setUp` and our test function. These are run
-within a `TEST_PROTECT` block, the function of which is to handle failures that
-occur during the test. Then, assuming our test is still running and hasn't been
-ignored, we run `tearDown`. No matter what, our last step is to conclude this
-test before moving on to the next.
-
-Let's say you need to add a call to `fsync` to force all of your output data to
-flush to a file after each test. You could easily insert this after your
-`UnityConcludeTest` call. Maybe you want to write an xml tag before and after
-each result set. Again, you could do this by adding lines to this macro. Updates
-to this macro are for the occasions when you need an action before or after
-every single test case throughout your entire suite of tests.
-
-
-## Happy Porting
-
-The defines and macros in this guide should help you port Unity to just about
-any C target we can imagine. If you run into a snag or two, don't be afraid of
-asking for help on the forums. We love a good challenge!
-
-
-*Find The Latest of This And More at [ThrowTheSwitch.org](https://throwtheswitch.org)*
diff --git a/test/vendor/ceedling/docs/UnityGettingStartedGuide.md b/test/vendor/ceedling/docs/UnityGettingStartedGuide.md
deleted file mode 100644
index 5e4427ce9..000000000
--- a/test/vendor/ceedling/docs/UnityGettingStartedGuide.md
+++ /dev/null
@@ -1,192 +0,0 @@
-# Unity - Getting Started
-
-## Welcome
-
-Congratulations. You're now the proud owner of your very own pile of bits! What
-are you going to do with all these ones and zeros? This document should be able
-to help you decide just that.
-
-Unity is a unit test framework. The goal has been to keep it small and
-functional. The core Unity test framework is three files: a single C file and a
-couple header files. These team up to provide functions and macros to make
-testing easier.
-
-Unity was designed to be cross-platform. It works hard to stick with C standards
-while still providing support for the many embedded C compilers that bend the
-rules. Unity has been used with many compilers, including GCC, IAR, Clang,
-Green Hills, Microchip, and MS Visual Studio. It's not much work to get it to
-work with a new target.
-
-
-### Overview of the Documents
-
-#### Unity Assertions reference
-
-This document will guide you through all the assertion options provided by
-Unity. This is going to be your unit testing bread and butter. You'll spend more
-time with assertions than any other part of Unity.
-
-
-#### Unity Assertions Cheat Sheet
-
-This document contains an abridged summary of the assertions described in the
-previous document. It's perfect for printing and referencing while you
-familiarize yourself with Unity's options.
-
-
-#### Unity Configuration Guide
-
-This document is the one to reference when you are going to use Unity with a new
-target or compiler. It'll guide you through the configuration options and will
-help you customize your testing experience to meet your needs.
-
-
-#### Unity Helper Scripts
-
-This document describes the helper scripts that are available for simplifying
-your testing workflow. It describes the collection of optional Ruby scripts
-included in the auto directory of your Unity installation. Neither Ruby nor
-these scripts are necessary for using Unity. They are provided as a convenience
-for those who wish to use them.
-
-
-#### Unity License
-
-What's an open source project without a license file? This brief document
-describes the terms you're agreeing to when you use this software. Basically, we
-want it to be useful to you in whatever context you want to use it, but please
-don't blame us if you run into problems.
-
-
-### Overview of the Folders
-
-If you have obtained Unity through Github or something similar, you might be
-surprised by just how much stuff you suddenly have staring you in the face.
-Don't worry, Unity itself is very small. The rest of it is just there to make
-your life easier. You can ignore it or use it at your convenience. Here's an
-overview of everything in the project.
-
-- `src` - This is the code you care about! This folder contains a C file and two
-header files. These three files _are_ Unity.
-- `docs` - You're reading this document, so it's possible you have found your way
-into this folder already. This is where all the handy documentation can be
-found.
-- `examples` - This contains a few examples of using Unity.
-- `extras` - These are optional add ons to Unity that are not part of the core
-project. If you've reached us through James Grenning's book, you're going to
-want to look here.
-- `test` - This is how Unity and its scripts are all tested. If you're just using
-Unity, you'll likely never need to go in here. If you are the lucky team member
-who gets to port Unity to a new toolchain, this is a good place to verify
-everything is configured properly.
-- `auto` - Here you will find helpful Ruby scripts for simplifying your test
-workflow. They are purely optional and are not required to make use of Unity.
-
-
-## How to Create A Test File
-
-Test files are C files. Most often you will create a single test file for each C
-module that you want to test. The test file should include unity.h and the
-header for your C module to be tested.
-
-Next, a test file will include a `setUp()` and `tearDown()` function. The setUp
-function can contain anything you would like to run before each test. The
-tearDown function can contain anything you would like to run after each test.
-Both functions accept no arguments and return nothing. You may leave either or
-both of these blank if you have no need for them. If you're using a compiler
-that is configured to make these functions optional, you may leave them off
-completely. Not sure? Give it a try. If you compiler complains that it can't
-find setUp or tearDown when it links, you'll know you need to at least include
-an empty function for these.
-
-The majority of the file will be a series of test functions. Test functions
-follow the convention of starting with the word "test_" or "spec_". You don't HAVE
-to name them this way, but it makes it clear what functions are tests for other
-developers.  Also, the automated scripts that come with Unity or Ceedling will default
-to looking for test functions to be prefixed this way. Test functions take no arguments 
-and return nothing. All test accounting is handled internally in Unity.
-
-Finally, at the bottom of your test file, you will write a `main()` function.
-This function will call `UNITY_BEGIN()`, then `RUN_TEST` for each test, and
-finally `UNITY_END()`.This is what will actually trigger each of those test
-functions to run, so it is important that each function gets its own `RUN_TEST`
-call.
-
-Remembering to add each test to the main function can get to be tedious. If you
-enjoy using helper scripts in your build process, you might consider making use
-of our handy generate_test_runner.rb script. This will create the main function
-and all the calls for you, assuming that you have followed the suggested naming
-conventions. In this case, there is no need for you to include the main function
-in your test file at all.
-
-When you're done, your test file will look something like this:
-
-```C
-#include "unity.h"
-#include "file_to_test.h"
-
-void setUp(void) {
-    // set stuff up here
-}
-
-void tearDown(void) {
-    // clean stuff up here
-}
-
-void test_function_should_doBlahAndBlah(void) {
-    //test stuff
-}
-
-void test_function_should_doAlsoDoBlah(void) {
-    //more test stuff
-}
-
-int main(void) {
-    UNITY_BEGIN();
-    RUN_TEST(test_function_should_doBlahAndBlah);
-    RUN_TEST(test_function_should_doAlsoDoBlah);
-    return UNITY_END();
-}
-```
-
-It's possible that you will need more customization than this, eventually.
-For that sort of thing, you're going to want to look at the configuration guide.
-This should be enough to get you going, though.
-
-
-## How to Build and Run A Test File
-
-This is the single biggest challenge to picking up a new unit testing framework,
-at least in a language like C or C++. These languages are REALLY good at getting
-you "close to the metal" (why is the phrase metal? Wouldn't it be more accurate
-to say "close to the silicon"?). While this feature is usually a good thing, it
-can make testing more challenging.
-
-You have two really good options for toolchains. Depending on where you're
-coming from, it might surprise you that neither of these options is running the
-unit tests on your hardware.
-There are many reasons for this, but here's a short version:
-- On hardware, you have too many constraints (processing power, memory, etc),
-- On hardware, you don't have complete control over all registers,
-- On hardware, unit testing is more challenging,
-- Unit testing isn't System testing. Keep them separate.
-
-Instead of running your tests on your actual hardware, most developers choose to
-develop them as native applications (using gcc or MSVC for example) or as
-applications running on a simulator. Either is a good option. Native apps have
-the advantages of being faster and easier to set up. Simulator apps have the
-advantage of working with the same compiler as your target application. The
-options for configuring these are discussed in the configuration guide.
-
-To get either to work, you might need to make a few changes to the file
-containing your register set (discussed later).
-
-In either case, a test is built by linking unity, the test file, and the C
-file(s) being tested. These files create an executable which can be run as the
-test set for that module. Then, this process is repeated for the next test file.
-This flexibility of separating tests into individual executables allows us to
-much more thoroughly unit test our system and it keeps all the test code out of
-our final release!
-
-
-*Find The Latest of This And More at [ThrowTheSwitch.org](https://throwtheswitch.org)*
diff --git a/test/vendor/ceedling/docs/UnityHelperScriptsGuide.md b/test/vendor/ceedling/docs/UnityHelperScriptsGuide.md
deleted file mode 100644
index 12d68d30e..000000000
--- a/test/vendor/ceedling/docs/UnityHelperScriptsGuide.md
+++ /dev/null
@@ -1,260 +0,0 @@
-# Unity Helper Scripts
-
-## With a Little Help From Our Friends
-
-Sometimes what it takes to be a really efficient C programmer is a little non-C.
-The Unity project includes a couple of Ruby scripts for making your life just a tad
-easier. They are completely optional. If you choose to use them, you'll need a
-copy of Ruby, of course. Just install whatever the latest version is, and it is
-likely to work. You can find Ruby at [ruby-lang.org](https://ruby-labg.org/).
-
-
-### `generate_test_runner.rb`
-
-Are you tired of creating your own `main` function in your test file? Do you
-keep forgetting to add a `RUN_TEST` call when you add a new test case to your
-suite? Do you want to use CMock or other fancy add-ons but don't want to figure
-out how to create your own `RUN_TEST` macro?
-
-Well then we have the perfect script for you!
-
-The `generate_test_runner` script processes a given test file and automatically
-creates a separate test runner file that includes ?main?to execute the test
-cases within the scanned test file. All you do then is add the generated runner
-to your list of files to be compiled and linked, and presto you're done!
-
-This script searches your test file for void function signatures having a
-function name beginning with "test" or "spec". It treats each of these
-functions as a test case and builds up a test suite of them. For example, the
-following includes three test cases:
-
-```C
-void testVerifyThatUnityIsAwesomeAndWillMakeYourLifeEasier(void)
-{
-  ASSERT_TRUE(1);
-}
-void test_FunctionName_should_WorkProperlyAndReturn8(void) {
-  ASSERT_EQUAL_INT(8, FunctionName());
-}
-void spec_Function_should_DoWhatItIsSupposedToDo(void) {
-  ASSERT_NOT_NULL(Function(5));
-}
-```
-
-You can run this script a couple of ways. The first is from the command line:
-
-```Shell
-ruby generate_test_runner.rb TestFile.c NameOfRunner.c
-```
-
-Alternatively, if you include only the test file parameter, the script will copy
-the name of the test file and automatically append "_Runner" to the name of the
-generated file. The example immediately below will create TestFile_Runner.c.
-
-```Shell
-ruby generate_test_runner.rb TestFile.c
-```
-
-You can also add a [YAML](http://www.yaml.org/) file to configure extra options.
-Conveniently, this YAML file is of the same format as that used by Unity and
-CMock. So if you are using YAML files already, you can simply pass the very same
-file into the generator script.
-
-```Shell
-ruby generate_test_runner.rb TestFile.c my_config.yml
-```
-
-The contents of the YAML file `my_config.yml` could look something like the
-example below. If you're wondering what some of these options do, you're going
-to love the next section of this document.
-
-```YAML
-:unity:
-  :includes:
-    - stdio.h
-    - microdefs.h
-  :cexception: 1
-  :suit_setup: "blah = malloc(1024);"
-  :suite_teardown: "free(blah);"
-```
-
-If you would like to force your generated test runner to include one or more
-header files, you can just include those at the command line too. Just make sure
-these are _after_ the YAML file, if you are using one:
-
-```Shell
-ruby generate_test_runner.rb TestFile.c my_config.yml extras.h
-```
-
-Another option, particularly if you are already using Ruby to orchestrate your
-builds - or more likely the Ruby-based build tool Rake - is requiring this
-script directly. Anything that you would have specified in a YAML file can be
-passed to the script as part of a hash. Let's push the exact same requirement
-set as we did above but this time through Ruby code directly:
-
-```Ruby
-require "generate_test_runner.rb"
-options = {
-  :includes => ["stdio.h", "microdefs.h"],
-  :cexception => 1,
-  :suite_setup => "blah = malloc(1024);",
-  :suite_teardown => "free(blah);"
-}
-UnityTestRunnerGenerator.new.run(testfile, runner_name, options)
-```
-
-If you have multiple files to generate in a build script (such as a Rakefile),
-you might want to instantiate a generator object with your options and call it
-to generate each runner afterwards. Like thus:
-
-```Ruby
-gen = UnityTestRunnerGenerator.new(options)
-test_files.each do |f|
-  gen.run(f, File.basename(f,'.c')+"Runner.c"
-end
-```
-
-#### Options accepted by generate_test_runner.rb:
-
-The following options are available when executing `generate_test_runner`. You
-may pass these as a Ruby hash directly or specify them in a YAML file, both of
-which are described above. In the `examples` directory, Example 3's Rakefile
-demonstrates using a Ruby hash.
-
-
-##### `:includes`
-
-This option specifies an array of file names to be `#include`'d at the top of
-your runner C file. You might use it to reference custom types or anything else
-universally needed in your generated runners.
-
-
-##### `:suite_setup`
-
-Define this option with C code to be executed _before any_ test cases are run.
-
-Alternatively, if your C compiler supports weak symbols, you can leave this
-option unset and instead provide a `void suiteSetUp(void)` function in your test
-suite.  The linker will look for this symbol and fall back to a Unity-provided
-stub if it is not found.
-
-
-##### `:suite_teardown`
-
-Define this option with C code to be executed _after all_ test cases have
-finished.  An integer variable `num_failures` is available for diagnostics.
-The code should end with a `return` statement; the value returned will become
-the exit code of `main`.  You can normally just return `num_failures`.
-
-Alternatively, if your C compiler supports weak symbols, you can leave this
-option unset and instead provide a `int suiteTearDown(int num_failures)`
-function in your test suite.  The linker will look for this symbol and fall
-back to a Unity-provided stub if it is not found.
-
-
-##### `:enforce_strict_ordering`
-
-This option should be defined if you have the strict order feature enabled in
-CMock (see CMock documentation). This generates extra variables required for
-everything to run smoothly. If you provide the same YAML to the generator as
-used in CMock's configuration, you've already configured the generator properly.
-
-##### `:mock_prefix` and `:mock_suffix`
-
-Unity automatically generates calls to Init, Verify and Destroy for every file
-included in the main test file that starts with the given mock prefix and ends
-with the given mock suffix, file extension not included. By default, Unity
-assumes a `Mock` prefix and no suffix.
-
-##### `:plugins`
-
-This option specifies an array of plugins to be used (of course, the array can
-contain only a single plugin). This is your opportunity to enable support for
-CException support, which will add a check for unhandled exceptions in each
-test, reporting a failure if one is detected. To enable this feature using Ruby:
-
-```Ruby
-:plugins => [ :cexception ]
-```
-
-Or as a yaml file:
-
-```YAML
-:plugins:
-  -:cexception
-```
-
-If you are using CMock, it is very likely that you are already passing an array
-of plugins to CMock. You can just use the same array here. This script will just
-ignore the plugins that don't require additional support.
-
-
-### `unity_test_summary.rb`
-
-A Unity test file contains one or more test case functions. Each test case can
-pass, fail, or be ignored. Each test file is run individually producing results
-for its collection of test cases. A given project will almost certainly be
-composed of multiple test files. Therefore, the suite of tests is comprised of
-one or more test cases spread across one or more test files. This script
-aggregates individual test file results to generate a summary of all executed
-test cases. The output includes how many tests were run, how many were ignored,
-and how many failed. In addition, the output includes a listing of which
-specific tests were ignored and failed. A good example of the breadth and
-details of these results can be found in the `examples` directory. Intentionally
-ignored and failing tests in this project generate corresponding entries in the
-summary report.
-
-If you're interested in other (prettier?) output formats, check into the
-Ceedling build tool project (ceedling.sourceforge.net) that works with Unity and
-CMock and supports xunit-style xml as well as other goodies.
-
-This script assumes the existence of files ending with the extensions
-`.testpass` and `.testfail`.The contents of these files includes the test
-results summary corresponding to each test file executed with the extension set
-according to the presence or absence of failures for that test file. The script
-searches a specified path for these files, opens each one it finds, parses the
-results, and aggregates and prints a summary. Calling it from the command line
-looks like this:
-
-```Shell
-ruby unity_test_summary.rb build/test/
-```
-
-You can optionally specify a root path as well. This is really helpful when you
-are using relative paths in your tools' setup, but you want to pull the summary
-into an IDE like Eclipse for clickable shortcuts.
-
-```Shell
-ruby unity_test_summary.rb build/test/ ~/projects/myproject/
-```
-
-Or, if you're more of a Windows sort of person:
-
-```Shell
-ruby unity_test_summary.rb build\teat\ C:\projects\myproject\
-```
-
-When configured correctly, you'll see a final summary, like so:
-
-```Shell
---------------------------
-UNITY IGNORED TEST SUMMARY
---------------------------
-blah.c:22:test_sandwiches_should_HaveBreadOnTwoSides:IGNORE
-
--------------------------
-UNITY FAILED TEST SUMMARY
--------------------------
-blah.c:87:test_sandwiches_should_HaveCondiments:FAIL:Expected 1 was 0
-meh.c:38:test_soda_should_BeCalledPop:FAIL:Expected "pop" was "coke"
-
---------------------------
-OVERALL UNITY TEST SUMMARY
---------------------------
-45 TOTAL TESTS 2 TOTAL FAILURES 1 IGNORED
-```
-
-How convenient is that?
-
-
-*Find The Latest of This And More at [ThrowTheSwitch.org](https://throwtheswitch.org)*
diff --git a/test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb b/test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
index b7d57f8f4..5727bcabc 100644
--- a/test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
+++ b/test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
@@ -9,7 +9,7 @@ class BuildInvokerUtils
   ##
   # Processes exceptions and tries to display a useful message for the user.
   #
-  # ==== Attriboops...utes
+  # ==== Attributes
   #
   # * _exception_:  The exception given by a rescue statement.
   # * _context_:    A symbol representing where in the build the exception
diff --git a/test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb b/test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
index 2a161854b..14e8a6ef0 100644
--- a/test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
+++ b/test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
@@ -4,28 +4,32 @@ class CacheinatorHelper
   constructor :file_wrapper, :yaml_wrapper
   
   def diff_cached_config?(cached_filepath, hash)
-    return true if ( not @file_wrapper.exist?(cached_filepath) )
-    return true if ( (@file_wrapper.exist?(cached_filepath)) and (!(@yaml_wrapper.load(cached_filepath) == hash)) )
+    return false if ( not @file_wrapper.exist?(cached_filepath) )
+    return true if (@yaml_wrapper.load(cached_filepath) != hash)
     return false
   end
 
   def diff_cached_defines?(cached_filepath, files)
+    changed_defines = false
     current_defines = COLLECTION_DEFINES_TEST_AND_VENDOR.reject(&:empty?)
 
-    current_dependency = Hash[files.collect { |source| [source, current_defines.dup] }]
+    current_dependencies = Hash[files.collect { |source| [source, current_defines.dup] }]
     if not @file_wrapper.exist?(cached_filepath)
-      @yaml_wrapper.dump(cached_filepath, current_dependency)
-      return false
+      @yaml_wrapper.dump(cached_filepath, current_dependencies)
+      return changed_defines
     end
 
     dependencies = @yaml_wrapper.load(cached_filepath)
-    if dependencies.values_at(*current_dependency.keys) != current_dependency.values
-      dependencies.merge!(current_dependency)
-      @yaml_wrapper.dump(cached_filepath, dependencies)
-      return true
+    common_dependencies = current_dependencies.select { |file, defines| dependencies.has_key?(file) }
+
+    if dependencies.values_at(*common_dependencies.keys) != common_dependencies.values
+      changed_defines = true
     end
 
-    return false
+    dependencies.merge!(current_dependencies)
+    @yaml_wrapper.dump(cached_filepath, dependencies)
+
+    return changed_defines
   end
 
 end
diff --git a/test/vendor/ceedling/lib/ceedling/configurator.rb b/test/vendor/ceedling/lib/ceedling/configurator.rb
index b5ad8982e..0ae4d04a8 100644
--- a/test/vendor/ceedling/lib/ceedling/configurator.rb
+++ b/test/vendor/ceedling/lib/ceedling/configurator.rb
@@ -54,6 +54,7 @@ class Configurator
      :test_fixture,
      :test_includes_preprocessor,
      :test_file_preprocessor,
+     :test_file_preprocessor_directives,
      :test_dependencies_generator,
      :release_compiler,
      :release_assembler,
@@ -183,17 +184,22 @@ class Configurator
     @rake_plugins   = @configurator_plugins.find_rake_plugins(config, paths_hash)
     @script_plugins = @configurator_plugins.find_script_plugins(config, paths_hash)
     config_plugins  = @configurator_plugins.find_config_plugins(config, paths_hash)
-    plugin_defaults = @configurator_plugins.find_plugin_defaults(config, paths_hash)
+    plugin_yml_defaults = @configurator_plugins.find_plugin_yml_defaults(config, paths_hash)
+    plugin_hash_defaults = @configurator_plugins.find_plugin_hash_defaults(config, paths_hash)
 
     config_plugins.each do |plugin|
       plugin_config = @yaml_wrapper.load(plugin)
       config.deep_merge(plugin_config)
     end
 
-    plugin_defaults.each do |defaults|
+    plugin_yml_defaults.each do |defaults|
       @configurator_builder.populate_defaults( config, @yaml_wrapper.load(defaults) )
     end
 
+    plugin_hash_defaults.each do |defaults|
+      @configurator_builder.populate_defaults( config, defaults )
+    end
+
     # special plugin setting for results printing
     config[:plugins][:display_raw_test_results] = true if (config[:plugins][:display_raw_test_results].nil?)
 
@@ -203,10 +209,19 @@ class Configurator
 
   def merge_imports(config)
     if config[:import]
-      until config[:import].empty?
-        path = config[:import].shift
-        path = @system_wrapper.module_eval(path) if (path =~ RUBY_STRING_REPLACEMENT_PATTERN)
-        config.deep_merge!(@yaml_wrapper.load(path))
+      if config[:import].is_a? Array
+        until config[:import].empty?
+          path = config[:import].shift
+          path = @system_wrapper.module_eval(path) if (path =~ RUBY_STRING_REPLACEMENT_PATTERN)
+          config.deep_merge!(@yaml_wrapper.load(path))
+        end
+      else
+        config[:import].each_value do |path|
+          if !path.nil?
+            path = @system_wrapper.module_eval(path) if (path =~ RUBY_STRING_REPLACEMENT_PATTERN)
+            config.deep_merge!(@yaml_wrapper.load(path))
+          end
+        end
       end
     end
     config.delete(:import)
@@ -222,7 +237,11 @@ class Configurator
       interstitial = ((key == :path) ? File::PATH_SEPARATOR : '')
       items = ((value.class == Array) ? hash[key] : [value])
 
-      items.each { |item| item.replace( @system_wrapper.module_eval( item ) ) if (item =~ RUBY_STRING_REPLACEMENT_PATTERN) }
+      items.each do |item|
+        if item.is_a? String and item =~ RUBY_STRING_REPLACEMENT_PATTERN
+          item.replace( @system_wrapper.module_eval( item ) )
+        end
+      end
       hash[key] = items.join( interstitial )
 
       @system_wrapper.env_set( key.to_s.upcase, hash[key] )
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_builder.rb b/test/vendor/ceedling/lib/ceedling/configurator_builder.rb
index da8a816f5..f202d8a65 100644
--- a/test/vendor/ceedling/lib/ceedling/configurator_builder.rb
+++ b/test/vendor/ceedling/lib/ceedling/configurator_builder.rb
@@ -250,8 +250,8 @@ class ConfiguratorBuilder
   def collect_test_support_source_include_vendor_paths(in_hash)
     return {
       :collection_paths_test_support_source_include_vendor =>
-        in_hash[:collection_paths_test_support_source_include] +
-        get_vendor_paths(in_hash)
+        get_vendor_paths(in_hash) +
+        in_hash[:collection_paths_test_support_source_include]
       }
   end
 
@@ -384,14 +384,26 @@ class ConfiguratorBuilder
   end
 
 
+  def get_vendor_defines(in_hash)
+    defines = in_hash[:unity_defines].clone
+    defines.concat(in_hash[:cmock_defines])      if (in_hash[:project_use_mocks])
+    defines.concat(in_hash[:cexception_defines]) if (in_hash[:project_use_exceptions])
+
+    return defines
+  end
+
+
+  def collect_vendor_defines(in_hash)
+    return {:collection_defines_vendor => get_vendor_defines(in_hash)}
+  end
+
+
   def collect_test_and_vendor_defines(in_hash)
-    test_defines = in_hash[:defines_test].clone
+    defines = in_hash[:defines_test].clone
+    vendor_defines = get_vendor_defines(in_hash)
+    defines.concat(vendor_defines) if vendor_defines
 
-    test_defines.concat(in_hash[:unity_defines])
-    test_defines.concat(in_hash[:cmock_defines])      if (in_hash[:project_use_mocks])
-    test_defines.concat(in_hash[:cexception_defines]) if (in_hash[:project_use_exceptions])
-
-    return {:collection_defines_test_and_vendor => test_defines}
+    return {:collection_defines_test_and_vendor => defines}
   end
 
 
@@ -418,28 +430,33 @@ class ConfiguratorBuilder
     #  Note: Symbols passed to compiler at command line can change Unity and CException behavior / configuration;
     #    we also handle those dependencies elsewhere in compilation dependencies
 
-    objects = [UNITY_C_FILE]
+    sources = [UNITY_C_FILE]
 
-    in_hash[:files_support].each { |file| objects << File.basename(file) }
+    in_hash[:files_support].each { |file| sources << file }
 
     # we don't include paths here because use of plugins or mixing different compilers may require different build paths
-    objects << CEXCEPTION_C_FILE if (in_hash[:project_use_exceptions])
-    objects << CMOCK_C_FILE      if (in_hash[:project_use_mocks])
+    sources << CEXCEPTION_C_FILE if (in_hash[:project_use_exceptions])
+    sources << CMOCK_C_FILE      if (in_hash[:project_use_mocks])
 
     # if we're using mocks & a unity helper is defined & that unity helper includes a source file component (not only a header of macros),
     # then link in the unity_helper object file too
     if ( in_hash[:project_use_mocks] and in_hash[:cmock_unity_helper] )
       in_hash[:cmock_unity_helper].each do |helper|
         if @file_wrapper.exist?(helper.ext(in_hash[:extension_source]))
-          objects << File.basename(helper)
+          sources << helper
         end
       end
     end
 
+    # create object files from all the sources
+    objects = sources.map { |file| File.basename(file) }
+
     # no build paths here so plugins can remap if necessary (i.e. path mapping happens at runtime)
     objects.map! { |object| object.ext(in_hash[:extension_object]) }
 
-    return { :collection_test_fixture_extra_link_objects => objects }
+    return { :collection_all_support => sources,
+             :collection_test_fixture_extra_link_objects => objects
+           }
   end
 
 
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_plugins.rb b/test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
index 70ca884a2..75bcd982d 100644
--- a/test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
+++ b/test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
@@ -26,6 +26,7 @@ class ConfiguratorPlugins
 
           if is_script_plugin
             @system_wrapper.add_load_path( File.join( path, 'lib') )
+            @system_wrapper.add_load_path( File.join( path, 'config') )
           end
           break
         end
@@ -92,7 +93,7 @@ class ConfiguratorPlugins
 
 
   # gather up and return default .yml filepaths that exist on-disk
-  def find_plugin_defaults(config, plugin_paths)
+  def find_plugin_yml_defaults(config, plugin_paths)
     defaults_with_path = []
 
     config[:plugins][:enabled].each do |plugin|
@@ -108,4 +109,23 @@ class ConfiguratorPlugins
     return defaults_with_path
   end
 
+  # gather up and return 
+  def find_plugin_hash_defaults(config, plugin_paths)
+    defaults_hash= []
+
+    config[:plugins][:enabled].each do |plugin|
+      if path = plugin_paths[(plugin + '_path').to_sym]
+        default_path = File.join(path, "config", "defaults_#{plugin}.rb")
+        if @file_wrapper.exist?(default_path)
+          @system_wrapper.require_file( "defaults_#{plugin}.rb")
+
+          object = eval("get_default_config()")
+          defaults_hash << object
+        end
+      end
+    end
+
+    return defaults_hash
+  end
+
 end
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_setup.rb b/test/vendor/ceedling/lib/ceedling/configurator_setup.rb
index 1d029b065..c43bb5c12 100644
--- a/test/vendor/ceedling/lib/ceedling/configurator_setup.rb
+++ b/test/vendor/ceedling/lib/ceedling/configurator_setup.rb
@@ -39,6 +39,7 @@ class ConfiguratorSetup
     flattened_config.merge!(@configurator_builder.collect_headers(flattened_config))
     flattened_config.merge!(@configurator_builder.collect_release_existing_compilation_input(flattened_config))
     flattened_config.merge!(@configurator_builder.collect_all_existing_compilation_input(flattened_config))
+    flattened_config.merge!(@configurator_builder.collect_vendor_defines(flattened_config))
     flattened_config.merge!(@configurator_builder.collect_test_and_vendor_defines(flattened_config))
     flattened_config.merge!(@configurator_builder.collect_release_and_vendor_defines(flattened_config))
     flattened_config.merge!(@configurator_builder.collect_release_artifact_extra_link_objects(flattened_config))
diff --git a/test/vendor/ceedling/lib/ceedling/constants.rb b/test/vendor/ceedling/lib/ceedling/constants.rb
index 993ce8db2..19484f063 100644
--- a/test/vendor/ceedling/lib/ceedling/constants.rb
+++ b/test/vendor/ceedling/lib/ceedling/constants.rb
@@ -95,3 +95,5 @@ NULL_FILE_PATH = '/dev/null'
 
 TESTS_BASE_PATH   = TEST_ROOT_NAME
 RELEASE_BASE_PATH = RELEASE_ROOT_NAME
+
+VENDORS_FILES = %w(unity UnityHelper cmock CException).freeze
diff --git a/test/vendor/ceedling/lib/ceedling/defaults.rb b/test/vendor/ceedling/lib/ceedling/defaults.rb
index 9e391fa09..1300a1aab 100644
--- a/test/vendor/ceedling/lib/ceedling/defaults.rb
+++ b/test/vendor/ceedling/lib/ceedling/defaults.rb
@@ -7,17 +7,20 @@ CEEDLING_VENDOR = File.expand_path(File.dirname(__FILE__) + '/../../vendor') unl
 CEEDLING_PLUGINS = [] unless defined? CEEDLING_PLUGINS
 
 DEFAULT_TEST_COMPILER_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
+  :executable => ENV['CC'].nil? ? FilePathUtils.os_executable_ext('gcc').freeze : ENV['CC'].split[0],
   :name => 'default_test_compiler'.freeze,
   :stderr_redirect => StdErrRedirect::NONE.freeze,
   :background_exec => BackgroundExec::NONE.freeze,
   :optional => false.freeze,
   :arguments => [
+    ENV['CC'].nil? ? "" : ENV['CC'].split[1..-1],
+    ENV['CPPFLAGS'].nil? ? "" : ENV['CPPFLAGS'].split,
     {"-I\"$\"" => 'COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR'}.freeze,
     {"-I\"$\"" => 'COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE'}.freeze,
     {"-D$" => 'COLLECTION_DEFINES_TEST_AND_VENDOR'}.freeze,
     "-DGNU_COMPILER".freeze,
     "-g".freeze,
+    ENV['CFLAGS'].nil? ? "" : ENV['CFLAGS'].split,
     "-c \"${1}\"".freeze,
     "-o \"${2}\"".freeze,
     # gcc's list file output options are complex; no use of ${3} parameter in default config
@@ -27,16 +30,21 @@ DEFAULT_TEST_COMPILER_TOOL = {
   }
 
 DEFAULT_TEST_LINKER_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
+  :executable => ENV['CCLD'].nil? ? FilePathUtils.os_executable_ext('gcc').freeze : ENV['CCLD'].split[0],
   :name => 'default_test_linker'.freeze,
   :stderr_redirect => StdErrRedirect::NONE.freeze,
   :background_exec => BackgroundExec::NONE.freeze,
   :optional => false.freeze,
   :arguments => [
+    ENV['CCLD'].nil? ? "" : ENV['CCLD'].split[1..-1],
+    ENV['CFLAGS'].nil? ? "" : ENV['CFLAGS'].split,
+    ENV['LDFLAGS'].nil? ? "" : ENV['LDFLAGS'].split,
     "\"${1}\"".freeze,
+    "${5}".freeze,
     "-o \"${2}\"".freeze,
     "".freeze,
-    "${4}".freeze
+    "${4}".freeze,
+    ENV['LDLIBS'].nil? ? "" : ENV['LDLIBS'].split
     ].freeze
   }
 
@@ -50,12 +58,14 @@ DEFAULT_TEST_FIXTURE_TOOL = {
   }
 
 DEFAULT_TEST_INCLUDES_PREPROCESSOR_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
+  :executable => ENV['CC'].nil? ? FilePathUtils.os_executable_ext('gcc').freeze : ENV['CC'].split[0],
   :name => 'default_test_includes_preprocessor'.freeze,
   :stderr_redirect => StdErrRedirect::NONE.freeze,
   :background_exec => BackgroundExec::NONE.freeze,
   :optional => false.freeze,
   :arguments => [
+    ENV['CC'].nil? ? "" : ENV['CC'].split[1..-1],
+    ENV['CPPFLAGS'].nil? ? "" : ENV['CPPFLAGS'].split,
     '-E'.freeze, # OSX clang
     '-MM'.freeze,
     '-MG'.freeze,
@@ -67,18 +77,38 @@ DEFAULT_TEST_INCLUDES_PREPROCESSOR_TOOL = {
     {"-D$" => 'COLLECTION_DEFINES_TEST_AND_VENDOR'}.freeze,
     {"-D$" => 'DEFINES_TEST_PREPROCESS'}.freeze,
     "-DGNU_COMPILER".freeze, # OSX clang
-    '-w'.freeze,
     # '-nostdinc'.freeze, # disabled temporarily due to stdio access violations on OSX
     "\"${1}\"".freeze
     ].freeze
   }
 
 DEFAULT_TEST_FILE_PREPROCESSOR_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
+  :executable => ENV['CC'].nil? ? FilePathUtils.os_executable_ext('gcc').freeze : ENV['CC'].split[0],
   :name => 'default_test_file_preprocessor'.freeze,
   :stderr_redirect => StdErrRedirect::NONE.freeze,
   :background_exec => BackgroundExec::NONE.freeze,
   :optional => false.freeze,
+  :arguments => [
+    ENV['CC'].nil? ? "" : ENV['CC'].split[1..-1],
+    ENV['CPPFLAGS'].nil? ? "" : ENV['CPPFLAGS'].split,
+    '-E'.freeze,
+    {"-I\"$\"" => 'COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR'}.freeze,
+    {"-I\"$\"" => 'COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE'}.freeze,
+    {"-D$" => 'COLLECTION_DEFINES_TEST_AND_VENDOR'}.freeze,
+    {"-D$" => 'DEFINES_TEST_PREPROCESS'}.freeze,
+    "-DGNU_COMPILER".freeze,
+    # '-nostdinc'.freeze, # disabled temporarily due to stdio access violations on OSX
+    "\"${1}\"".freeze,
+    "-o \"${2}\"".freeze
+    ].freeze
+  }
+
+DEFAULT_TEST_FILE_PREPROCESSOR_DIRECTIVES_TOOL = {
+  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
+  :name => 'default_test_file_preprocessor_directives'.freeze,
+  :stderr_redirect => StdErrRedirect::NONE.freeze,
+  :background_exec => BackgroundExec::NONE.freeze,
+  :optional => false.freeze,
   :arguments => [
     '-E'.freeze,
     {"-I\"$\"" => 'COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR'}.freeze,
@@ -86,6 +116,7 @@ DEFAULT_TEST_FILE_PREPROCESSOR_TOOL = {
     {"-D$" => 'COLLECTION_DEFINES_TEST_AND_VENDOR'}.freeze,
     {"-D$" => 'DEFINES_TEST_PREPROCESS'}.freeze,
     "-DGNU_COMPILER".freeze,
+    '-fdirectives-only'.freeze,
     # '-nostdinc'.freeze, # disabled temporarily due to stdio access violations on OSX
     "\"${1}\"".freeze,
     "-o \"${2}\"".freeze
@@ -100,12 +131,14 @@ else
 end
 
 DEFAULT_TEST_DEPENDENCIES_GENERATOR_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
+  :executable => ENV['CC'].nil? ? FilePathUtils.os_executable_ext('gcc').freeze : ENV['CC'].split[0],
   :name => 'default_test_dependencies_generator'.freeze,
   :stderr_redirect => StdErrRedirect::NONE.freeze,
   :background_exec => BackgroundExec::NONE.freeze,
   :optional => false.freeze,
   :arguments => [
+    ENV['CC'].nil? ? "" : ENV['CC'].split[1..-1],
+    ENV['CPPFLAGS'].nil? ? "" : ENV['CPPFLAGS'].split,
     '-E'.freeze,
     {"-I\"$\"" => 'COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR'}.freeze,
     {"-I\"$\"" => 'COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE'}.freeze,
@@ -123,12 +156,14 @@ DEFAULT_TEST_DEPENDENCIES_GENERATOR_TOOL = {
   }
 
 DEFAULT_RELEASE_DEPENDENCIES_GENERATOR_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
+  :executable => ENV['CC'].nil? ? FilePathUtils.os_executable_ext('gcc').freeze : ENV['CC'].split[0],
   :name => 'default_release_dependencies_generator'.freeze,
   :stderr_redirect => StdErrRedirect::NONE.freeze,
   :background_exec => BackgroundExec::NONE.freeze,
   :optional => false.freeze,
   :arguments => [
+    ENV['CC'].nil? ? "" : ENV['CC'].split[1..-1],
+    ENV['CPPFLAGS'].nil? ? "" : ENV['CPPFLAGS'].split,
     '-E'.freeze,
     {"-I\"$\"" => 'COLLECTION_PATHS_SOURCE_INCLUDE_VENDOR'}.freeze,
     {"-I\"$\"" => 'COLLECTION_PATHS_RELEASE_TOOLCHAIN_INCLUDE'}.freeze,
@@ -147,16 +182,19 @@ DEFAULT_RELEASE_DEPENDENCIES_GENERATOR_TOOL = {
 
 
 DEFAULT_RELEASE_COMPILER_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
+  :executable => ENV['CC'].nil? ? FilePathUtils.os_executable_ext('gcc').freeze : ENV['CC'].split[0],
   :name => 'default_release_compiler'.freeze,
   :stderr_redirect => StdErrRedirect::NONE.freeze,
   :background_exec => BackgroundExec::NONE.freeze,
   :optional => false.freeze,
   :arguments => [
+    ENV['CC'].nil? ? "" : ENV['CC'].split[1..-1],
+    ENV['CPPFLAGS'].nil? ? "" : ENV['CPPFLAGS'].split,
     {"-I\"$\"" => 'COLLECTION_PATHS_SOURCE_INCLUDE_VENDOR'}.freeze,
     {"-I\"$\"" => 'COLLECTION_PATHS_RELEASE_TOOLCHAIN_INCLUDE'}.freeze,
     {"-D$" => 'COLLECTION_DEFINES_RELEASE_AND_VENDOR'}.freeze,
     "-DGNU_COMPILER".freeze,
+    ENV['CFLAGS'].nil? ? "" : ENV['CFLAGS'].split,
     "-c \"${1}\"".freeze,
     "-o \"${2}\"".freeze,
     # gcc's list file output options are complex; no use of ${3} parameter in default config
@@ -166,12 +204,14 @@ DEFAULT_RELEASE_COMPILER_TOOL = {
   }
 
 DEFAULT_RELEASE_ASSEMBLER_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('as').freeze,
+  :executable => ENV['AS'].nil? ? FilePathUtils.os_executable_ext('as').freeze : ENV['AS'].split[0],
   :name => 'default_release_assembler'.freeze,
   :stderr_redirect => StdErrRedirect::NONE.freeze,
   :background_exec => BackgroundExec::NONE.freeze,
   :optional => false.freeze,
   :arguments => [
+    ENV['AS'].nil? ? "" : ENV['AS'].split[1..-1],
+    ENV['ASFLAGS'].nil? ? "" : ENV['ASFLAGS'].split,
     {"-I\"$\"" => 'COLLECTION_PATHS_SOURCE_AND_INCLUDE'}.freeze,
     "\"${1}\"".freeze,
     "-o \"${2}\"".freeze,
@@ -179,16 +219,21 @@ DEFAULT_RELEASE_ASSEMBLER_TOOL = {
   }
 
 DEFAULT_RELEASE_LINKER_TOOL = {
-  :executable => FilePathUtils.os_executable_ext('gcc').freeze,
+  :executable => ENV['CCLD'].nil? ? FilePathUtils.os_executable_ext('gcc').freeze : ENV['CCLD'].split[0],
   :name => 'default_release_linker'.freeze,
   :stderr_redirect => StdErrRedirect::NONE.freeze,
   :background_exec => BackgroundExec::NONE.freeze,
   :optional => false.freeze,
   :arguments => [
+    ENV['CCLD'].nil? ? "" : ENV['CCLD'].split[1..-1],
+    ENV['CFLAGS'].nil? ? "" : ENV['CFLAGS'].split,
+    ENV['LDFLAGS'].nil? ? "" : ENV['LDFLAGS'].split,
     "\"${1}\"".freeze,
+    "${5}".freeze,
     "-o \"${2}\"".freeze,
     "".freeze,
-    "${4}".freeze
+    "${4}".freeze,
+    ENV['LDLIBS'].nil? ? "" : ENV['LDLIBS'].split
     ].freeze
   }
 
@@ -205,6 +250,7 @@ DEFAULT_TOOLS_TEST_PREPROCESSORS = {
   :tools => {
     :test_includes_preprocessor => DEFAULT_TEST_INCLUDES_PREPROCESSOR_TOOL,
     :test_file_preprocessor     => DEFAULT_TEST_FILE_PREPROCESSOR_TOOL,
+    :test_file_preprocessor_directives => DEFAULT_TEST_FILE_PREPROCESSOR_DIRECTIVES_TOOL,
     }
   }
 
@@ -245,8 +291,10 @@ DEFAULT_CEEDLING_CONFIG = {
       :compile_threads => 1,
       :test_threads => 1,
       :use_test_preprocessor => false,
+      :use_preprocessor_directives => false,
       :use_deep_dependencies => false,
       :generate_deep_dependencies => true, # only applicable if use_deep_dependencies is true
+      :auto_link_deep_dependencies => false,
       :test_file_prefix => 'test_',
       :options_paths => [],
       :release_build => false,
@@ -263,6 +311,7 @@ DEFAULT_CEEDLING_CONFIG = {
       :source => [], # must be populated by user
       :support => [],
       :include => [],
+      :libraries => [],
       :test_toolchain_include => [],
       :release_toolchain_include => [],
     },
@@ -290,6 +339,8 @@ DEFAULT_CEEDLING_CONFIG = {
     },
 
     :libraries => {
+      :flag => '-l${1}',
+      :path_flag => '-L ${1}',
       :test => [],
       :test_preprocess => [],
       :release => [],
@@ -303,6 +354,7 @@ DEFAULT_CEEDLING_CONFIG = {
       :source => '.c',
       :assembly => '.s',
       :object => '.o',
+      :libraries => ['.a','.so'],
       :executable => ( SystemWrapper.windows? ? EXTENSION_WIN_EXE : EXTENSION_NONWIN_EXE ),
       :map => '.map',
       :list => '.lst',
@@ -345,6 +397,7 @@ DEFAULT_CEEDLING_CONFIG = {
     },
     :test_includes_preprocessor  => { :arguments => [] },
     :test_file_preprocessor      => { :arguments => [] },
+    :test_file_preprocessor_directives => { :arguments => [] },
     :test_dependencies_generator => { :arguments => [] },
     :release_compiler  => { :arguments => [] },
     :release_linker    => { :arguments => [] },
diff --git a/test/vendor/ceedling/lib/ceedling/dependinator.rb b/test/vendor/ceedling/lib/ceedling/dependinator.rb
index ebd123772..accfe80c9 100644
--- a/test/vendor/ceedling/lib/ceedling/dependinator.rb
+++ b/test/vendor/ceedling/lib/ceedling/dependinator.rb
@@ -86,13 +86,12 @@ class Dependinator
 
 
   def enhance_results_dependencies(result_filepath)
-    @rake_wrapper[result_filepath].enhance( [@configurator.project_test_force_rebuild_filepath] ) if (@project_config_manager.test_config_changed ||
-      @project_config_manager.test_defines_changed)
+    @rake_wrapper[result_filepath].enhance( [@configurator.project_test_force_rebuild_filepath] ) if @project_config_manager.test_config_changed
   end
 
 
-  def setup_test_executable_dependencies(test, objects)
-    @rake_wrapper.create_file_task( @file_path_utils.form_test_executable_filepath(test), objects )
+  def enhance_test_executable_dependencies(test, objects)
+    @rake_wrapper[ @file_path_utils.form_test_executable_filepath(test) ].enhance( objects )
   end
 
 end
diff --git a/test/vendor/ceedling/lib/ceedling/file_finder_helper.rb b/test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
index 0a31b44bd..a168e5cb5 100644
--- a/test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
+++ b/test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
@@ -25,10 +25,12 @@ class FileFinderHelper
       
     end
     
-    case (complain)
-      when :error then blow_up(file_name, extra_message) if (file_to_find.nil?)
-      when :warn  then gripe(file_name, extra_message)   if (file_to_find.nil?)
-      #when :ignore then      
+    if file_to_find.nil?
+      case (complain)
+        when :error then blow_up(file_name, extra_message) 
+        when :warn  then gripe(file_name, extra_message)
+        #when :ignore then      
+      end
     end
     
     return file_to_find
diff --git a/test/vendor/ceedling/lib/ceedling/file_path_utils.rb b/test/vendor/ceedling/lib/ceedling/file_path_utils.rb
index 607039fd5..89a28ba7f 100644
--- a/test/vendor/ceedling/lib/ceedling/file_path_utils.rb
+++ b/test/vendor/ceedling/lib/ceedling/file_path_utils.rb
@@ -21,9 +21,11 @@ class FilePathUtils
 
   # standardize path to use '/' path separator & have no trailing path separator
   def self.standardize(path)
-    path.strip!
-    path.gsub!(/\\/, '/')
-    path.chomp!('/')
+    if path.is_a? String
+      path.strip!
+      path.gsub!(/\\/, '/')
+      path.chomp!('/')
+    end
     return path
   end
 
diff --git a/test/vendor/ceedling/lib/ceedling/file_wrapper.rb b/test/vendor/ceedling/lib/ceedling/file_wrapper.rb
index 1680ca520..9e5a909b4 100644
--- a/test/vendor/ceedling/lib/ceedling/file_wrapper.rb
+++ b/test/vendor/ceedling/lib/ceedling/file_wrapper.rb
@@ -33,15 +33,15 @@ class FileWrapper
   end
 
   def rm_f(filepath, options={})
-    FileUtils.rm_f(filepath, options)
+    FileUtils.rm_f(filepath, **options)
   end
 
   def rm_r(filepath, options={})
-    FileUtils.rm_r(filepath, options={})
+    FileUtils.rm_r(filepath, **options={})
   end
 
   def cp(source, destination, options={})
-    FileUtils.cp(source, destination, options)
+    FileUtils.cp(source, destination, **options)
   end
 
   def compare(from, to)
@@ -59,7 +59,7 @@ class FileWrapper
   end
 
   def touch(filepath, options={})
-    FileUtils.touch(filepath, options)
+    FileUtils.touch(filepath, **options)
   end
 
   def write(filepath, contents, flags='w')
diff --git a/test/vendor/ceedling/lib/ceedling/generator.rb b/test/vendor/ceedling/lib/ceedling/generator.rb
index 828a0c025..0b8902475 100644
--- a/test/vendor/ceedling/lib/ceedling/generator.rb
+++ b/test/vendor/ceedling/lib/ceedling/generator.rb
@@ -101,19 +101,21 @@ class Generator
       shell_result = ex.shell_result
       raise ex
     ensure
+      arg_hash[:shell_command] = command[:line]
       arg_hash[:shell_result] = shell_result
       @plugin_manager.post_compile_execute(arg_hash)
     end
   end
 
-  def generate_executable_file(tool, context, objects, executable, map='', libraries=[])
+  def generate_executable_file(tool, context, objects, executable, map='', libraries=[], libpaths=[])
     shell_result = {}
     arg_hash = { :tool => tool,
                  :context => context,
                  :objects => objects,
                  :executable => executable,
                  :map => map,
-                 :libraries => libraries
+                 :libraries => libraries,
+                 :libpaths => libpaths
                }
 
     @plugin_manager.pre_link_execute(arg_hash)
@@ -125,7 +127,8 @@ class Generator
                                          arg_hash[:objects],
                                          arg_hash[:executable],
                                          arg_hash[:map],
-                                         arg_hash[:libraries]
+                                         arg_hash[:libraries],
+                                         arg_hash[:libpaths]
                                        )
     @streaminator.stdout_puts("Command: #{command}", Verbosity::DEBUG)
 
diff --git a/test/vendor/ceedling/lib/ceedling/generator_test_results.rb b/test/vendor/ceedling/lib/ceedling/generator_test_results.rb
index 1d0c5201f..3af2d720a 100644
--- a/test/vendor/ceedling/lib/ceedling/generator_test_results.rb
+++ b/test/vendor/ceedling/lib/ceedling/generator_test_results.rb
@@ -37,6 +37,10 @@ class GeneratorTestResults
         elements = extract_line_elements(line, results[:source][:file])
         results[:successes] << elements[0]
         results[:stdout] << elements[1] if (!elements[1].nil?)
+      when /(:PASS \(.* ms\)$)/
+        elements = extract_line_elements(line, results[:source][:file])
+        results[:successes] << elements[0]
+        results[:stdout] << elements[1] if (!elements[1].nil?)
       when /(:FAIL)/
         elements = extract_line_elements(line, results[:source][:file])
         results[:failures] << elements[0]
@@ -73,6 +77,7 @@ class GeneratorTestResults
     # handle anything preceding filename in line as extra output to be collected
     stdout = nil
     stdout_regex = /(.+)#{Regexp.escape(filename)}.+/i
+    unity_test_time = 0 
 
     if (line =~ stdout_regex)
       stdout = $1.clone
@@ -82,8 +87,14 @@ class GeneratorTestResults
     # collect up test results minus and extra output
     elements = (line.strip.split(':'))[1..-1]
 
-    return {:test => elements[1], :line => elements[0].to_i, :message => (elements[3..-1].join(':')).strip}, stdout if elements.size >= 3
-    return {:test => '???', :line => -1, :message => nil} #fallback safe option. TODO better handling
+    # find timestamp if available
+    if (elements[-1] =~ / \((\d*(?:\.\d*)?) ms\)/)
+      unity_test_time = $1.to_f / 1000
+      elements[-1].sub!(/ \((\d*(?:\.\d*)?) ms\)/, '')
+    end
+
+    return {:test => elements[1], :line => elements[0].to_i, :message => (elements[3..-1].join(':')).strip, :unity_test_time => unity_test_time}, stdout if elements.size >= 3
+    return {:test => '???', :line => -1, :message => nil, :unity_test_time => unity_test_time} #fallback safe option. TODO better handling
   end
 
 end
diff --git a/test/vendor/ceedling/lib/ceedling/generator_test_runner.rb b/test/vendor/ceedling/lib/ceedling/generator_test_runner.rb
index 6999faf96..79ed7140f 100644
--- a/test/vendor/ceedling/lib/ceedling/generator_test_runner.rb
+++ b/test/vendor/ceedling/lib/ceedling/generator_test_runner.rb
@@ -44,13 +44,15 @@ class GeneratorTestRunner
   def generate(module_name, runner_filepath, test_cases, mock_list, test_file_includes=[])
     require 'generate_test_runner.rb'
 
+    header_extension = @configurator.extension_header
+
     #actually build the test runner using Unity's test runner generator
     #(there is no need to use preprocessor here because we've already looked up test cases and are passing them in here)
     @test_runner_generator ||= UnityTestRunnerGenerator.new( @configurator.get_runner_config )
     @test_runner_generator.generate( module_name,
                                      runner_filepath,
                                      test_cases,
-                                     mock_list,
-                                     test_file_includes)
+                                     mock_list.map{|f| File.basename(f,'.*')+header_extension},
+                                     test_file_includes.map{|f| File.basename(f,'.*')+header_extension})
   end
 end
diff --git a/test/vendor/ceedling/lib/ceedling/objects.yml b/test/vendor/ceedling/lib/ceedling/objects.yml
index 2e2e9b9d2..43bbc066c 100644
--- a/test/vendor/ceedling/lib/ceedling/objects.yml
+++ b/test/vendor/ceedling/lib/ceedling/objects.yml
@@ -17,11 +17,11 @@ reportinator:
 
 rake_utils:
   compose:
-    - rake_wrapper  
+    - rake_wrapper
 
 system_utils:
   compose:
-    - system_wrapper  
+    - system_wrapper
 
 file_path_utils:
   compose:
@@ -203,13 +203,13 @@ generator_helper:
 
 generator_test_results:
   compose:
-    - configurator  
+    - configurator
     - generator_test_results_sanity_checker
-    - yaml_wrapper  
+    - yaml_wrapper
 
 generator_test_results_sanity_checker:
   compose:
-    - configurator  
+    - configurator
     - streaminator
 
 generator_test_runner:
@@ -223,43 +223,46 @@ dependinator:
     - configurator
     - project_config_manager
     - test_includes_extractor
-    - file_path_utils        
+    - file_path_utils 
     - rake_wrapper
     - file_wrapper
 
 preprocessinator:
   compose:
-    - preprocessinator_helper          
+    - preprocessinator_helper
     - preprocessinator_includes_handler
     - preprocessinator_file_handler
-    - task_invoker    
+    - task_invoker
     - file_path_utils
     - yaml_wrapper
+    - project_config_manager
+    - configurator
 
 preprocessinator_helper:
-  compose:                    
-    - configurator            
-    - test_includes_extractor 
-    - task_invoker            
-    - file_finder             
-    - file_path_utils         
+  compose:
+    - configurator
+    - test_includes_extractor
+    - task_invoker
+    - file_finder
+    - file_path_utils
 
 preprocessinator_includes_handler:
   compose:
-    - configurator    
-    - tool_executor   
-    - task_invoker    
-    - file_path_utils 
-    - yaml_wrapper    
-    - file_wrapper    
+    - configurator
+    - tool_executor
+    - task_invoker
+    - file_path_utils
+    - yaml_wrapper
+    - file_wrapper
+    - file_finder
 
 preprocessinator_file_handler:
   compose:
     - preprocessinator_extractor
-    - configurator   
-    - tool_executor  
+    - configurator
+    - tool_executor
     - file_path_utils
-    - file_wrapper   
+    - file_wrapper
 
 preprocessinator_extractor:
 
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator.rb b/test/vendor/ceedling/lib/ceedling/preprocessinator.rb
index f07750dd2..52d82ca29 100644
--- a/test/vendor/ceedling/lib/ceedling/preprocessinator.rb
+++ b/test/vendor/ceedling/lib/ceedling/preprocessinator.rb
@@ -1,29 +1,38 @@
 
 class Preprocessinator
 
-  attr_reader :preprocess_file_proc
-  
-  constructor :preprocessinator_helper, :preprocessinator_includes_handler, :preprocessinator_file_handler, :task_invoker, :file_path_utils, :yaml_wrapper
+  constructor :preprocessinator_helper, :preprocessinator_includes_handler, :preprocessinator_file_handler, :task_invoker, :file_path_utils, :yaml_wrapper, :project_config_manager, :configurator
 
 
   def setup
     # fashion ourselves callbacks @preprocessinator_helper can use
-    @preprocess_includes_proc = Proc.new { |filepath| self.preprocess_shallow_includes(filepath) }
-    @preprocess_file_proc     = Proc.new { |filepath| self.preprocess_file(filepath) }
+    @preprocess_includes_proc  = Proc.new { |filepath| self.preprocess_shallow_includes(filepath) }
+    @preprocess_mock_file_proc = Proc.new { |filepath| self.preprocess_file(filepath) }
+    @preprocess_test_file_directives_proc = Proc.new { |filepath| self.preprocess_file_directives(filepath) }
+    @preprocess_test_file_proc = Proc.new { |filepath| self.preprocess_file(filepath) }
   end
 
+  def preprocess_shallow_source_includes(test)
+    @preprocessinator_helper.preprocess_source_includes(test)
+  end
 
   def preprocess_test_and_invoke_test_mocks(test)
     @preprocessinator_helper.preprocess_includes(test, @preprocess_includes_proc)
 
     mocks_list = @preprocessinator_helper.assemble_mocks_list(test)
 
-    @preprocessinator_helper.preprocess_mockable_headers(mocks_list, @preprocess_file_proc)
+    @project_config_manager.process_test_defines_change(mocks_list)
+
+    @preprocessinator_helper.preprocess_mockable_headers(mocks_list, @preprocess_mock_file_proc)
 
     @task_invoker.invoke_test_mocks(mocks_list)
 
-    @preprocessinator_helper.preprocess_test_file(test, @preprocess_file_proc)
-    
+    if (@configurator.project_use_preprocessor_directives)
+      @preprocessinator_helper.preprocess_test_file(test, @preprocess_test_file_directives_proc)
+    else
+      @preprocessinator_helper.preprocess_test_file(test, @preprocess_test_file_proc)
+    end
+
     return mocks_list
   end
 
@@ -39,4 +48,9 @@ class Preprocessinator
     @preprocessinator_file_handler.preprocess_file( filepath, @yaml_wrapper.load(@file_path_utils.form_preprocessed_includes_list_filepath(filepath)) )
   end
 
+  def preprocess_file_directives(filepath)
+    @preprocessinator_includes_handler.invoke_shallow_includes_list( filepath )
+    @preprocessinator_file_handler.preprocess_file_directives( filepath,
+      @yaml_wrapper.load( @file_path_utils.form_preprocessed_includes_list_filepath( filepath ) ) )
+  end
 end
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb b/test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb
index 49509a8b0..62026e15a 100644
--- a/test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb
+++ b/test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb
@@ -16,6 +16,7 @@ class PreprocessinatorExtractor
 
     lines = []
     File.readlines(filepath).each do |line|
+      line.encode!('UTF-8', 'binary', invalid: :replace, undef: :replace, replace: '')
       if found_file and not line =~ not_pragma
         lines << line
       else
@@ -27,4 +28,28 @@ class PreprocessinatorExtractor
 
     return lines
   end
+
+  def extract_base_file_from_preprocessed_directives(filepath)
+    # preprocessing by way of toolchain preprocessor eliminates directives only
+    # like #ifdef's and leave other code
+
+    # iterate through all lines and only get last chunk of file after a last
+    # '#'line containing file name of our filepath
+
+    base_name  = File.basename(filepath)
+    pattern    = /^#.*(\s|\/|\\|\")#{Regexp.escape(base_name)}/
+    found_file = false # have we found the file we care about?
+
+    lines = []
+    File.readlines(filepath).each do |line|
+      line.encode!('UTF-8', 'binary', invalid: :replace, undef: :replace, replace: '')
+      lines << line
+
+      if line =~ pattern
+        lines = []
+      end
+    end
+
+    return lines
+  end
 end
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb b/test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb
index b6b5efbc6..978fa0d05 100644
--- a/test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb
+++ b/test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb
@@ -18,4 +18,17 @@ class PreprocessinatorFileHandler
     @file_wrapper.write(preprocessed_filepath, contents.join("\n"))
   end
 
+  def preprocess_file_directives(filepath, includes)
+    preprocessed_filepath = @file_path_utils.form_preprocessed_file_filepath(filepath)
+
+    command = @tool_executor.build_command_line(@configurator.tools_test_file_preprocessor_directives, [], filepath, preprocessed_filepath)
+    @tool_executor.exec(command[:line], command[:options])
+
+    contents = @preprocessinator_extractor.extract_base_file_from_preprocessed_directives(preprocessed_filepath)
+
+    includes.each{|include| contents.unshift("#include \"#{include}\"")}
+
+    @file_wrapper.write(preprocessed_filepath, contents.join("\n"))
+  end
+
 end
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb b/test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb
index 1419a5616..4bbda67fc 100644
--- a/test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb
+++ b/test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb
@@ -15,6 +15,10 @@ class PreprocessinatorHelper
     end
   end
 
+  def preprocess_source_includes(test)
+    @test_includes_extractor.parse_test_file_source_include(test)
+  end
+
   def assemble_mocks_list(test)
     return @file_path_utils.form_mocks_source_filelist( @test_includes_extractor.lookup_raw_mock_list(test) )
   end
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb b/test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
index 703c84f3c..8b89c0b3a 100644
--- a/test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
+++ b/test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
@@ -2,7 +2,7 @@
 
 class PreprocessinatorIncludesHandler
 
-  constructor :configurator, :tool_executor, :task_invoker, :file_path_utils, :yaml_wrapper, :file_wrapper
+  constructor :configurator, :tool_executor, :task_invoker, :file_path_utils, :yaml_wrapper, :file_wrapper, :file_finder
   @@makefile_cache = {}
 
   # shallow includes: only those headers a source file explicitly includes
@@ -65,6 +65,7 @@ class PreprocessinatorIncludesHandler
     to_process = [filepath]
     ignore_list = []
     list = []
+    all_mocks = []
 
     include_paths = @configurator.project_config_hash[:collection_paths_include]
     include_paths = [] if include_paths.nil?
@@ -73,12 +74,10 @@ class PreprocessinatorIncludesHandler
     while to_process.length > 0
       target = to_process.shift()
       ignore_list << target
-      # puts "[HELL] Processing: \t\t#{target}"
-      new_deps, new_to_process = extract_includes_helper(target, include_paths, ignore_list)
+      new_deps, new_to_process, all_mocks = extract_includes_helper(target, include_paths, ignore_list, all_mocks)
       list += new_deps
       to_process += new_to_process
-      if (!@configurator.project_config_hash.has_key?(:project_auto_link_deep_dependencies) or
-          !@configurator.project_config_hash[:project_auto_link_deep_dependencies])
+      if !@configurator.project_config_hash[:project_auto_link_deep_dependencies]
         break
       else
         list = list.uniq()
@@ -89,93 +88,102 @@ class PreprocessinatorIncludesHandler
     return list
   end
 
-  def extract_includes_helper(filepath, include_paths, ignore_list)
+  def extract_includes_helper(filepath, include_paths, ignore_list, mocks)
     # Extract the dependencies from the make rule
-    hdr_ext = @configurator.extension_header
     make_rule = self.form_shallow_dependencies_rule(filepath)
-    dependencies = make_rule.split.find_all {|path| path.end_with?(hdr_ext) }.uniq
-    dependencies.map! {|hdr| hdr.gsub('\\','/') }
+    target_file = make_rule.split[0].gsub(':', '').gsub('\\','/')
+    base = File.basename(target_file, File.extname(target_file))
+    make_rule_dependencies = make_rule.gsub(/.*\b#{Regexp.escape(base)}\S*/, '').gsub(/\\$/, '')
+    
+    # Extract the headers dependencies from the make rule
+    hdr_ext = @configurator.extension_header
+    headers_dependencies = make_rule_dependencies.split.find_all {|path| path.end_with?(hdr_ext) }.uniq
+    headers_dependencies.map! {|hdr| hdr.gsub('\\','/') }
+    full_path_headers_dependencies = extract_full_path_dependencies(headers_dependencies)
 
-    # Separate the real files form the annotated ones and remove the '@@@@'
-    annotated_headers, real_headers = dependencies.partition {|hdr| hdr =~ /^@@@@/ }
-    annotated_headers.map! {|hdr| hdr.gsub('@@@@','') }
-    # Matching annotated_headers values against real_headers to ensure that
-    # annotated_headers contain full path entries (as returned by make rule)
-    annotated_headers.map! {|hdr| real_headers.find {|real_hdr| !real_hdr.match(/(.*\/)?#{Regexp.escape(hdr)}/).nil? } }
-    annotated_headers = annotated_headers.compact
+    # Extract the sources dependencies from the make rule
+    src_ext = @configurator.extension_source
+    sources_dependencies = make_rule_dependencies.split.find_all {|path| path.end_with?(src_ext) }.uniq
+    sources_dependencies.map! {|src| src.gsub('\\','/') }
+    full_path_sources_dependencies = extract_full_path_dependencies(sources_dependencies)
 
-    # Find which of our annotated headers are "real" dependencies. This is
-    # intended to weed out dependencies that have been removed due to build
-    # options defined in the project yaml and/or in the headers themselves.
-    list = annotated_headers.find_all do |annotated_header|
-      # find the index of the "real" include that matches the annotated one.
-      idx = real_headers.find_index do |real_header|
-        real_header =~ /^(.*\/)?#{Regexp.escape(annotated_header)}$/
-      end
-      # If we found a real include, delete it from the array and return it,
-      # otherwise return nil. Since nil is falsy this has the effect of making
-      # find_all return only the annotated headers for which a real include was
-      # found/deleted
-      idx ? real_headers.delete_at(idx) : nil
+    list = full_path_headers_dependencies + full_path_sources_dependencies
+
+    mock_prefix = @configurator.project_config_hash[:cmock_mock_prefix]
+    # Creating list of mocks
+    mocks += full_path_headers_dependencies.find_all do |header|
+      File.basename(header) =~ /^#{mock_prefix}.*$/
     end.compact
 
-    # Extract direct dependencies that were also added
-    src_ext = @configurator.extension_source
-    sdependencies = make_rule.split.find_all {|path| path.end_with?(src_ext) }.uniq
-    sdependencies.map! {|hdr| hdr.gsub('\\','/') }
-    list += sdependencies
+    # ignore real file when both mock and real file exist
+    mocks.each do |mock|
+      list.each do |filename|
+        if File.basename(filename) == File.basename(mock).sub(mock_prefix, '')
+          ignore_list << filename
+        end
+      end
+    end.compact
+
+    # Filtering list of final includes to only include mocks and anything that is NOT in the ignore_list
+    list = list.select do |item|
+      mocks.include? item or !(ignore_list.any? { |ignore_item| !item.match(/^(.*\/)?#{Regexp.escape(ignore_item)}$/).nil? })
+    end
 
     to_process = []
 
-    if @configurator.project_config_hash.has_key?(:project_auto_link_deep_dependencies) && @configurator.project_config_hash[:project_auto_link_deep_dependencies]
-      # Creating list of mocks
-      mocks = annotated_headers.find_all do |annotated_header|
-        File.basename(annotated_header) =~ /^#{@configurator.project_config_hash[:cmock_mock_prefix]}.*$/
-      end.compact
-
+    if @configurator.project_config_hash[:project_auto_link_deep_dependencies]
       # Creating list of headers that should be recursively pre-processed
-      # Skipping mocks and unity.h
-      headers_to_deep_link = annotated_headers.select do |annotated_header|
-        !(mocks.include? annotated_header) and (annotated_header.match(/^(.*\/)?unity\.h$/).nil?)
-      end
-      headers_to_deep_link.map! {|hdr| File.expand_path(hdr)}
-
-      mocks.each do |mock|
-        dirname = File.dirname(mock)
-        #basename = File.basename(mock).delete_prefix(@configurator.project_config_hash[:cmock_mock_prefix])
-        basename = File.basename(mock).sub(@configurator.project_config_hash[:cmock_mock_prefix], '')
-        if dirname != "."
-          ignore_list << File.join(dirname, basename)
-        else
-          ignore_list << basename
-        end
-      end.compact
-
-      # Filtering list of final includes to only include mocks and anything that is NOT in the ignore_list
-      list = list.select do |item|
-        mocks.include? item or !(ignore_list.any? { |ignore_item| !item.match(/^(.*\/)?#{Regexp.escape(ignore_item)}$/).nil? })
+      # Skipping mocks and vendor headers
+      headers_to_deep_link = full_path_headers_dependencies.select do |hdr|
+        !(mocks.include? hdr) and (hdr.match(/^(.*\/)(#{VENDORS_FILES.join('|')}) + #{Regexp.escape(hdr_ext)}$/).nil?)
       end
+      headers_to_deep_link.map! {|hdr| File.expand_path(hdr) }
+      headers_to_deep_link.compact!
 
       headers_to_deep_link.each do |hdr|
         if (ignore_list.none? {|ignore_header| hdr.match(/^(.*\/)?#{Regexp.escape(ignore_header)}$/)} and
             include_paths.none? {|include_path| hdr =~ /^#{include_path}\.*/})
           if File.exist?(hdr)
             to_process << hdr
-            #source_file = hdr.delete_suffix(hdr_ext) + src_ext
-            source_file = hdr.chomp(hdr_ext) + src_ext
-            if source_file != hdr and File.exist?(source_file)
-              to_process << source_file
-            end
+            src = @file_finder.find_compilation_input_file(hdr, :ignore)
+            to_process << src if src
           end
         end
       end
     end
 
-    return list, to_process
+    return list, to_process, mocks
 
   end
 
   def write_shallow_includes_list(filepath, list)
     @yaml_wrapper.dump(filepath, list)
   end
+
+  private
+
+  def extract_full_path_dependencies(dependencies)
+    # Separate the real files form the annotated ones and remove the '@@@@'
+    annotated_files, real_files = dependencies.partition {|file| file =~ /^@@@@/}
+    annotated_files.map! {|file| file.gsub('@@@@','') }
+    # Matching annotated_files values against real_files to ensure that
+    # annotated_files contain full path entries (as returned by make rule)
+    annotated_files.map! {|file| real_files.find {|real| !real.match(/^(.*\/)?#{Regexp.escape(file)}$/).nil?}}
+    annotated_files = annotated_files.compact
+
+    # Find which of our annotated files are "real" dependencies. This is
+    # intended to weed out dependencies that have been removed due to build
+    # options defined in the project yaml and/or in the files themselves.
+    return annotated_files.find_all do |annotated_file|
+      # find the index of the "real" file that matches the annotated one.
+      idx = real_files.find_index do |real_file|
+        real_file =~ /^(.*\/)?#{Regexp.escape(annotated_file)}$/
+      end
+      # If we found a real file, delete it from the array and return it,
+      # otherwise return nil. Since nil is falsy this has the effect of making
+      # find_all return only the annotated filess for which a real file was
+      # found/deleted
+      idx ? real_files.delete_at(idx) : nil
+    end.compact
+  end
 end
diff --git a/test/vendor/ceedling/lib/ceedling/project_config_manager.rb b/test/vendor/ceedling/lib/ceedling/project_config_manager.rb
index 31f7e3a68..ed7a73b8c 100644
--- a/test/vendor/ceedling/lib/ceedling/project_config_manager.rb
+++ b/test/vendor/ceedling/lib/ceedling/project_config_manager.rb
@@ -21,9 +21,15 @@ class ProjectConfigManager
     @options_files << File.basename( option_filepath )
     config_hash.deep_merge!( @yaml_wrapper.load( option_filepath ) )
   end 
-  
 
-  
+
+  def filter_internal_sources(sources)
+    filtered_sources = sources.clone
+    filtered_sources.delete_if { |item| item =~ /#{CMOCK_MOCK_PREFIX}.+#{Regexp.escape(EXTENSION_SOURCE)}$/ }
+    filtered_sources.delete_if { |item| item =~ /#{VENDORS_FILES.map{|source| '\b' + Regexp.escape(source.ext(EXTENSION_SOURCE)) + '\b'}.join('|')}$/ }
+    return filtered_sources
+  end
+
   def process_release_config_change
     # has project configuration changed since last release build
     @release_config_changed = @cacheinator.diff_cached_release_config?( @config_hash )
@@ -40,7 +46,7 @@ class ProjectConfigManager
     @test_defines_changed = @cacheinator.diff_cached_test_defines?( files )
     if @test_defines_changed
       # update timestamp for rake task prerequisites
-      @file_wrapper.touch( @configurator.project_test_force_rebuild_filepath )
+      @file_wrapper.touch( @configurator.project_test_force_rebuild_filepath, :mtime => Time.now + 10 )
     end
   end
 end
diff --git a/test/vendor/ceedling/lib/ceedling/rakefile.rb b/test/vendor/ceedling/lib/ceedling/rakefile.rb
index 37001bacc..1bcb82491 100644
--- a/test/vendor/ceedling/lib/ceedling/rakefile.rb
+++ b/test/vendor/ceedling/lib/ceedling/rakefile.rb
@@ -10,7 +10,6 @@ $LOAD_PATH.unshift( CEEDLING_LIB )
 $LOAD_PATH.unshift( File.join(CEEDLING_VENDOR, 'unity/auto') )
 $LOAD_PATH.unshift( File.join(CEEDLING_VENDOR, 'diy/lib') )
 $LOAD_PATH.unshift( File.join(CEEDLING_VENDOR, 'cmock/lib') )
-$LOAD_PATH.unshift( File.join(CEEDLING_VENDOR, 'deep_merge/lib') )
 
 require 'rake'
 
diff --git a/test/vendor/ceedling/lib/ceedling/release_invoker.rb b/test/vendor/ceedling/lib/ceedling/release_invoker.rb
index 5bfb6cd70..19bbca727 100644
--- a/test/vendor/ceedling/lib/ceedling/release_invoker.rb
+++ b/test/vendor/ceedling/lib/ceedling/release_invoker.rb
@@ -56,15 +56,40 @@ class ReleaseInvoker
   end
 
   def convert_libraries_to_arguments(libraries)
-    args = (libraries || []) + ((defined? LIBRARIES_SYSTEM) ? LIBRARIES_SYSTEM : [])
+    args = ((libraries || []) + ((defined? LIBRARIES_SYSTEM) ? LIBRARIES_SYSTEM : [])).flatten
     if (defined? LIBRARIES_FLAG)
       args.map! {|v| LIBRARIES_FLAG.gsub(/\$\{1\}/, v) }
     end
     return args
   end
 
+  def get_library_paths_to_arguments()
+    paths = (defined? PATHS_LIBRARIES) ? (PATHS_LIBRARIES || []).clone : []
+    if (defined? LIBRARIES_PATH_FLAG)
+      paths.map! {|v| LIBRARIES_PATH_FLAG.gsub(/\$\{1\}/, v) }
+    end
+    return paths
+  end
+
   def sort_objects_and_libraries(both)
-    extension = "\\" + ((defined? EXTENSION_SUBPROJECTS) ? EXTENSION_SUBPROJECTS : ".LIBRARY")
+    extension = if ((defined? EXTENSION_SUBPROJECTS) && (defined? EXTENSION_LIBRARIES))
+      extension_libraries = if (EXTENSION_LIBRARIES.class == Array)
+                              EXTENSION_LIBRARIES.join(")|(?:\\")
+                            else
+                              EXTENSION_LIBRARIES
+                            end
+      "(?:\\#{EXTENSION_SUBPROJECTS})|(?:\\#{extension_libraries})"
+    elsif (defined? EXTENSION_SUBPROJECTS)
+      "\\#{EXTENSION_SUBPROJECTS}"
+    elsif (defined? EXTENSION_LIBRARIES)
+      if (EXTENSION_LIBRARIES.class == Array)
+        "(?:\\#{EXTENSION_LIBRARIES.join(")|(?:\\")})"
+      else
+        "\\#{EXTENSION_LIBRARIES}"
+      end
+    else
+      "\\.LIBRARY"
+    end
     sorted_objects = both.group_by {|v| v.match(/.+#{extension}$/) ? :libraries : :objects }
     libraries = sorted_objects[:libraries] || []
     objects   = sorted_objects[:objects]   || []
diff --git a/test/vendor/ceedling/lib/ceedling/rules_release.rake b/test/vendor/ceedling/lib/ceedling/rules_release.rake
index ae39a76e3..4a583bd6c 100644
--- a/test/vendor/ceedling/lib/ceedling/rules_release.rake
+++ b/test/vendor/ceedling/lib/ceedling/rules_release.rake
@@ -2,6 +2,17 @@
 RELEASE_COMPILE_TASK_ROOT  = RELEASE_TASK_ROOT + 'compile:'  unless defined?(RELEASE_COMPILE_TASK_ROOT)
 RELEASE_ASSEMBLE_TASK_ROOT = RELEASE_TASK_ROOT + 'assemble:' unless defined?(RELEASE_ASSEMBLE_TASK_ROOT)
 
+# If GCC and Releasing a Library, Update Tools to Automatically Have Necessary Tags
+if (TOOLS_RELEASE_COMPILER[:executable] == DEFAULT_RELEASE_COMPILER_TOOL[:executable])
+  if (File.extname(PROJECT_RELEASE_BUILD_TARGET) == '.so')
+    TOOLS_RELEASE_COMPILER[:arguments] << "-fPIC" unless TOOLS_RELEASE_COMPILER[:arguments].include?("-fPIC")
+    TOOLS_RELEASE_LINKER[:arguments] << "-shared" unless TOOLS_RELEASE_LINKER[:arguments].include?("-shared")
+  elsif (File.extname(PROJECT_RELEASE_BUILD_TARGET) == '.a')
+    TOOLS_RELEASE_COMPILER[:arguments] << "-fPIC" unless TOOLS_RELEASE_COMPILER[:arguments].include?("-fPIC")
+    TOOLS_RELEASE_LINKER[:executable] = 'ar'
+    TOOLS_RELEASE_LINKER[:arguments] = ['rcs', '${2}', '${1}'].compact
+  end
+end
 
 if (RELEASE_BUILD_USE_ASSEMBLY)
 rule(/#{PROJECT_RELEASE_BUILD_OUTPUT_ASM_PATH}\/#{'.+\\'+EXTENSION_OBJECT}$/ => [
@@ -37,16 +48,18 @@ end
 
 rule(/#{PROJECT_RELEASE_BUILD_TARGET}/) do |bin_file|
   objects, libraries = @ceedling[:release_invoker].sort_objects_and_libraries(bin_file.prerequisites)
-  tool     = TOOLS_RELEASE_LINKER.clone
-  lib_args = @ceedling[:release_invoker].convert_libraries_to_arguments(libraries)
-  map_file = @ceedling[:configurator].project_release_build_map
+  tool      = TOOLS_RELEASE_LINKER.clone
+  lib_args  = @ceedling[:release_invoker].convert_libraries_to_arguments(libraries)
+  lib_paths = @ceedling[:release_invoker].get_library_paths_to_arguments()
+  map_file  = @ceedling[:configurator].project_release_build_map
   @ceedling[:generator].generate_executable_file(
     tool,
     RELEASE_SYM,
     objects,
     bin_file.name,
     map_file,
-    lib_args )
+    lib_args,
+    lib_paths )
   @ceedling[:release_invoker].artifactinate( bin_file.name, map_file, @ceedling[:configurator].release_build_artifacts )
 end
 
diff --git a/test/vendor/ceedling/lib/ceedling/rules_tests.rake b/test/vendor/ceedling/lib/ceedling/rules_tests.rake
index 2b8f7af5b..61e15e2cc 100644
--- a/test/vendor/ceedling/lib/ceedling/rules_tests.rake
+++ b/test/vendor/ceedling/lib/ceedling/rules_tests.rake
@@ -34,16 +34,16 @@ end
 
 
 rule(/#{PROJECT_TEST_BUILD_OUTPUT_PATH}\/#{'.+\\'+EXTENSION_EXECUTABLE}$/) do |bin_file|
-
   lib_args = @ceedling[:test_invoker].convert_libraries_to_arguments()
-
+  lib_paths = @ceedling[:test_invoker].get_library_paths_to_arguments()
   @ceedling[:generator].generate_executable_file(
     TOOLS_TEST_LINKER,
     TEST_SYM,
     bin_file.prerequisites,
     bin_file.name,
     @ceedling[:file_path_utils].form_test_build_map_filepath( bin_file.name ),
-    lib_args )
+    lib_args,
+    lib_paths )
 end
 
 
@@ -66,8 +66,7 @@ namespace TEST_SYM do
         @ceedling[:file_finder].find_test_from_file_path(test)
       end
   ]) do |test|
-    @ceedling[:rake_wrapper][:directories].reenable if @ceedling[:task_invoker].first_run == false && @ceedling[:project_config_manager].test_defines_changed
-    @ceedling[:rake_wrapper][:directories].invoke
+    @ceedling[:rake_wrapper][:test_deps].invoke
     @ceedling[:test_invoker].setup_and_invoke([test.source])
   end
 end
diff --git a/test/vendor/ceedling/lib/ceedling/setupinator.rb b/test/vendor/ceedling/lib/ceedling/setupinator.rb
index 8347b42ab..ea78fd97e 100644
--- a/test/vendor/ceedling/lib/ceedling/setupinator.rb
+++ b/test/vendor/ceedling/lib/ceedling/setupinator.rb
@@ -25,8 +25,8 @@ class Setupinator
     @ceedling[:configurator].populate_cmock_defaults( config_hash )
     @ceedling[:configurator].find_and_merge_plugins( config_hash )
     @ceedling[:configurator].merge_imports( config_hash )
-    @ceedling[:configurator].tools_setup( config_hash )
     @ceedling[:configurator].eval_environment_variables( config_hash )
+    @ceedling[:configurator].tools_setup( config_hash )
     @ceedling[:configurator].eval_paths( config_hash )
     @ceedling[:configurator].standardize_paths( config_hash )
     @ceedling[:configurator].validate( config_hash )
diff --git a/test/vendor/ceedling/lib/ceedling/task_invoker.rb b/test/vendor/ceedling/lib/ceedling/task_invoker.rb
index 642695c46..7bfabbb12 100644
--- a/test/vendor/ceedling/lib/ceedling/task_invoker.rb
+++ b/test/vendor/ceedling/lib/ceedling/task_invoker.rb
@@ -46,25 +46,31 @@ class TaskInvoker
     return @rake_utils.task_invoked?(regex)
   end
 
-  
+  def reset_rake_task_for_changed_defines(file)
+    if !(file =~ /#{VENDORS_FILES.map{|ignore| '\b' + ignore.ext(File.extname(file)) + '\b'}.join('|')}$/)
+      @rake_wrapper[file].clear_actions if @first_run == false && @project_config_manager.test_defines_changed
+      @rake_wrapper[file].reenable if @first_run == false && @project_config_manager.test_defines_changed
+    end
+  end
+
   def invoke_test_mocks(mocks)
     @dependinator.enhance_mock_dependencies( mocks )
     mocks.each { |mock|
-      @rake_wrapper[mock].reenable if @first_run == false && @project_config_manager.test_defines_changed
+      reset_rake_task_for_changed_defines( mock )
       @rake_wrapper[mock].invoke
     }
   end
   
   def invoke_test_runner(runner)
     @dependinator.enhance_runner_dependencies( runner )
-    @rake_wrapper[runner].reenable if @first_run == false && @project_config_manager.test_defines_changed
+    reset_rake_task_for_changed_defines( runner )
     @rake_wrapper[runner].invoke
   end
 
   def invoke_test_shallow_include_lists(files)
     @dependinator.enhance_shallow_include_lists_dependencies( files )
     par_map(PROJECT_COMPILE_THREADS, files) do |file|
-      @rake_wrapper[file].reenable if @first_run == false && @project_config_manager.test_defines_changed
+      reset_rake_task_for_changed_defines( file )
       @rake_wrapper[file].invoke
     end
   end
@@ -72,7 +78,7 @@ class TaskInvoker
   def invoke_test_preprocessed_files(files)
     @dependinator.enhance_preprocesed_file_dependencies( files )
     par_map(PROJECT_COMPILE_THREADS, files) do |file|
-      @rake_wrapper[file].reenable if @first_run == false && @project_config_manager.test_defines_changed
+      reset_rake_task_for_changed_defines( file )
       @rake_wrapper[file].invoke
     end
   end
@@ -80,14 +86,14 @@ class TaskInvoker
   def invoke_test_dependencies_files(files)
     @dependinator.enhance_dependencies_dependencies( files )
     par_map(PROJECT_COMPILE_THREADS, files) do |file|
-      @rake_wrapper[file].reenable if @first_run == false && @project_config_manager.test_defines_changed
+      reset_rake_task_for_changed_defines( file )
       @rake_wrapper[file].invoke
     end
   end
 
   def invoke_test_objects(objects)
     par_map(PROJECT_COMPILE_THREADS, objects) do |object|
-      @rake_wrapper[object].reenable if @first_run == false && @project_config_manager.test_defines_changed
+      reset_rake_task_for_changed_defines( object )
       @rake_wrapper[object].invoke
     end
   end
@@ -98,7 +104,6 @@ class TaskInvoker
 
   def invoke_test_results(result)
     @dependinator.enhance_results_dependencies( result )
-    @rake_wrapper[result].reenable if @first_run == false && @project_config_manager.test_defines_changed
     @rake_wrapper[result].invoke
   end
 
diff --git a/test/vendor/ceedling/lib/ceedling/tasks_base.rake b/test/vendor/ceedling/lib/ceedling/tasks_base.rake
index 8c8253099..a35cde75e 100644
--- a/test/vendor/ceedling/lib/ceedling/tasks_base.rake
+++ b/test/vendor/ceedling/lib/ceedling/tasks_base.rake
@@ -4,28 +4,10 @@ require 'ceedling/version'
 
 desc "Display build environment version info."
 task :version do
-  puts "  Ceedling:: #{Ceedling::Version::CEEDLING}"
-
-  [
-      ['CException', File.join( CEEDLING_VENDOR, CEXCEPTION_ROOT_PATH)],
-      ['     CMock', File.join( CEEDLING_VENDOR, CMOCK_ROOT_PATH)],
-      ['     Unity', File.join( CEEDLING_VENDOR, UNITY_ROOT_PATH)],
-  ].each do |tool|
-    name      = tool[0]
-    base_path = tool[1]
-
-    version_string = begin
-      @ceedling[:file_wrapper].read( File.join(base_path, 'release', 'version.info') ).strip
-    rescue
-      "UNKNOWN"
-    end
-    build_string = begin
-      @ceedling[:file_wrapper].read( File.join(base_path, 'release', 'build.info') ).strip
-    rescue
-      "UNKNOWN"
-    end
-    puts "#{name}:: #{version_string.empty? ? '#.#.' : (version_string + '.')}#{build_string.empty? ? '?' : build_string}"
-  end
+  puts "   Ceedling:: #{Ceedling::Version::CEEDLING}"
+  puts "      Unity:: #{Ceedling::Version::UNITY}"
+  puts "      CMock:: #{Ceedling::Version::CMOCK}"
+  puts " CException:: #{Ceedling::Version::CEXCEPTION}"
 end
 
 desc "Set verbose output (silent:[#{Verbosity::SILENT}] - obnoxious:[#{Verbosity::OBNOXIOUS}])."
@@ -65,6 +47,12 @@ task :sanity_checks, :level do |t, args|
   @ceedling[:configurator].sanity_checks = check_level
 end
 
+# non advertised catch for calling upgrade in the wrong place
+task :upgrade do
+  puts "WARNING: You're currently IN your project directory. Take a step out and try"
+  puts "again if you'd like to perform an upgrade."
+end
+
 # list expanded environment variables
 if (not ENVIRONMENT.empty?)
 desc "List all configured environment variables."
@@ -73,7 +61,7 @@ task :environment do
   ENVIRONMENT.each do |env|
     env.each_key do |key|
       name = key.to_s.upcase
-	  env_list.push(" - #{name}: \"#{env[key]}\"")      
+	  env_list.push(" - #{name}: \"#{env[key]}\"")
     end
   end
   env_list.sort.each do |env_line|
@@ -88,7 +76,7 @@ namespace :options do
     option = File.basename(option_path, '.yml')
 
     desc "Merge #{option} project options."
-    task option.downcase.to_sym do
+    task option.to_sym do
       hash = @ceedling[:project_config_manager].merge_options( @ceedling[:setupinator].config_hash, option_path )
       @ceedling[:setupinator].do_setup( hash )
       if @ceedling[:configurator].project_release_build
@@ -97,6 +85,23 @@ namespace :options do
     end
   end
 
+  # This is to give nice errors when typing options
+  rule /^options:.*/ do |t, args|
+    filename = t.to_s.split(':')[-1] + '.yml'
+    filelist = COLLECTION_PROJECT_OPTIONS.map{|s| File.basename(s) }
+    @ceedling[:file_finder].find_file_from_list(filename, filelist, :error)
+  end
+
+  # This will output the fully-merged tools options to their own project.yml file
+  desc "Export tools options to a new project file"
+  task :export, :filename do |t, args|
+    outfile = args.filename || 'tools.yml'
+    toolcfg = {}
+    @ceedling[:configurator].project_config_hash.each_pair do |k,v|
+      toolcfg[k] = v if (k.to_s[0..5] == 'tools_')
+    end
+    File.open(outfile,'w') {|f| f << toolcfg.to_yaml({:indentation => 2})}
+  end
 end
 
 
diff --git a/test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake b/test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake
index 58fa6511f..7b950ca0b 100644
--- a/test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake
+++ b/test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake
@@ -45,26 +45,35 @@ task(:clobber => [:clean]) do
   @ceedling[:streaminator].stdout_puts("\nClobbering all generated files...\n(For large projects, this task may take a long time to complete)\n\n")
   begin
     CLOBBER.each { |fn| REMOVE_FILE_PROC.call(fn) }
+    @ceedling[:rake_wrapper][:directories].invoke
+    @ceedling[:dependinator].touch_force_rebuild_files
   rescue
   end
 end
 
-
+# create a directory task for each of the paths, so we know how to build them
 PROJECT_BUILD_PATHS.each { |path| directory(path) }
 
-# create directories that hold build output and generated files & touching rebuild dependency sources
-task(:directories => PROJECT_BUILD_PATHS) { @ceedling[:dependinator].touch_force_rebuild_files }
+# create a single directory task which verifies all the others get built
+task :directories => PROJECT_BUILD_PATHS
 
+# when the force file doesn't exist, it probably means we clobbered or are on a fresh
+# install. In either case, stuff was deleted, so assume we want to rebuild it all
+file @ceedling[:configurator].project_test_force_rebuild_filepath do
+  unless File.exists?(@ceedling[:configurator].project_test_force_rebuild_filepath)
+    @ceedling[:dependinator].touch_force_rebuild_files
+  end
+end
 
 # list paths discovered at load time
 namespace :paths do
-
-  paths = @ceedling[:setupinator].config_hash[:paths]
-  paths.each_key do |section|
-    name = section.to_s.downcase
+  standard_paths = ['test','source','include']
+  paths = @ceedling[:setupinator].config_hash[:paths].keys.map{|n| n.to_s.downcase}
+  paths = (paths + standard_paths).uniq
+  paths.each do |name|
     path_list = Object.const_get("COLLECTION_PATHS_#{name.upcase}")
 
-    if (path_list.size != 0)
+    if (path_list.size != 0) || (standard_paths.include?(name))
       desc "List all collected #{name} paths."
       task(name.to_sym) { puts "#{name} paths:"; path_list.sort.each {|path| puts " - #{path}" } }
     end
@@ -77,10 +86,11 @@ end
 namespace :files do
 
   categories = [
-    ['test',   COLLECTION_ALL_TESTS],
-    ['source', COLLECTION_ALL_SOURCE],
-    ['header', COLLECTION_ALL_HEADERS]
-    ]
+    ['test',    COLLECTION_ALL_TESTS],
+    ['source',  COLLECTION_ALL_SOURCE],
+    ['include', COLLECTION_ALL_HEADERS],
+    ['support', COLLECTION_ALL_SUPPORT]
+  ]
 
   using_assembly = (defined?(TEST_BUILD_USE_ASSEMBLY) && TEST_BUILD_USE_ASSEMBLY) ||
                    (defined?(RELEASE_BUILD_USE_ASSEMBLY) && RELEASE_BUILD_USE_ASSEMBLY)
diff --git a/test/vendor/ceedling/lib/ceedling/tasks_tests.rake b/test/vendor/ceedling/lib/ceedling/tasks_tests.rake
index 5d09c1aff..6c51ebcc9 100644
--- a/test/vendor/ceedling/lib/ceedling/tasks_tests.rake
+++ b/test/vendor/ceedling/lib/ceedling/tasks_tests.rake
@@ -1,13 +1,15 @@
 require 'ceedling/constants'
 
-task :test => [:directories] do
+task :test_deps => [:directories]
+
+task :test => [:test_deps] do
   Rake.application['test:all'].invoke
 end
 
 namespace TEST_SYM do
 
   desc "Run all unit tests (also just 'test' works)."
-  task :all => [:directories] do
+  task :all => [:test_deps] do
     @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS)
   end
 
@@ -21,17 +23,17 @@ namespace TEST_SYM do
   end
 
   desc "Run tests for changed files."
-  task :delta => [:directories] do
+  task :delta => [:test_deps] do
     @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, TEST_SYM, {:force_run => false})
   end
 
   desc "Just build tests without running."
-  task :build_only => [:directories] do
+  task :build_only => [:test_deps] do
     @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, TEST_SYM, {:build_only => true})
   end
 
   desc "Run tests by matching regular expression pattern."
-  task :pattern, [:regex] => [:directories] do |t, args|
+  task :pattern, [:regex] => [:test_deps] do |t, args|
     matches = []
 
     COLLECTION_ALL_TESTS.each { |test| matches << test if (test =~ /#{args.regex}/) }
@@ -44,7 +46,7 @@ namespace TEST_SYM do
   end
 
   desc "Run tests whose test path contains [dir] or [dir] substring."
-  task :path, [:dir] => [:directories] do |t, args|
+  task :path, [:dir] => [:test_deps] do |t, args|
     matches = []
 
     COLLECTION_ALL_TESTS.each { |test| matches << test if File.dirname(test).include?(args.dir.gsub(/\\/, '/')) }
diff --git a/test/vendor/ceedling/lib/ceedling/test_includes_extractor.rb b/test/vendor/ceedling/lib/ceedling/test_includes_extractor.rb
index 50cc7c041..393b0be8b 100644
--- a/test/vendor/ceedling/lib/ceedling/test_includes_extractor.rb
+++ b/test/vendor/ceedling/lib/ceedling/test_includes_extractor.rb
@@ -19,6 +19,11 @@ class TestIncludesExtractor
     gather_and_store_includes( test, extract_from_file(test) )
   end
 
+  # open, scan for, and sort & store includes of test file
+  def parse_test_file_source_include(test)
+    return extract_source_include_from_file(test)
+  end
+
   # mocks with no file extension
   def lookup_raw_mock_list(test)
     file_key = form_file_key(test)
@@ -65,6 +70,27 @@ class TestIncludesExtractor
     return includes.uniq
   end
 
+  def extract_source_include_from_file(file)
+    source_includes = []
+    source_extension = @configurator.extension_source
+
+    contents = @file_wrapper.read(file)
+
+    # remove line comments
+    contents = contents.gsub(/\/\/.*$/, '')
+    # remove block comments
+    contents = contents.gsub(/\/\*.*?\*\//m, '')
+
+    contents.split("\n").each do |line|
+      # look for include statement
+      scan_results = line.scan(/#include\s+\"\s*(.+#{'\\'+source_extension})\s*\"/)
+
+      source_includes << scan_results[0][0] if (scan_results.size > 0)
+    end
+
+    return source_includes.uniq
+  end
+
   def gather_and_store_includes(file, includes)
     mock_prefix      = @configurator.cmock_mock_prefix
     header_extension = @configurator.extension_header
diff --git a/test/vendor/ceedling/lib/ceedling/test_invoker.rb b/test/vendor/ceedling/lib/ceedling/test_invoker.rb
index 652cb318b..ae686a110 100644
--- a/test/vendor/ceedling/lib/ceedling/test_invoker.rb
+++ b/test/vendor/ceedling/lib/ceedling/test_invoker.rb
@@ -23,49 +23,24 @@ class TestInvoker
     @mocks   = []
   end
 
-  def get_test_definition_str(test)
-    return "-D" + File.basename(test, File.extname(test)).upcase.sub(/@.*$/, "")
-  end
-
-  def get_tools_compilers
-    tools_compilers = Hash.new
-    tools_compilers["for unit test"] = TOOLS_TEST_COMPILER if defined? TOOLS_TEST_COMPILER
-    tools_compilers["for gcov"]      = TOOLS_GCOV_COMPILER if defined? TOOLS_GCOV_COMPILER
-    return tools_compilers
-  end
-
-  def add_test_definition(test)
-    test_definition_str = get_test_definition_str(test)
-    get_tools_compilers.each do |tools_compiler_key, tools_compiler_value|
-      tools_compiler_value[:arguments].push("-D#{File.basename(test, ".*").strip.upcase.sub(/@.*$/, "")}")
-      @streaminator.stdout_puts("Add the definition value in the build option #{tools_compiler_value[:arguments][-1]} #{tools_compiler_key}", Verbosity::OBNOXIOUS)
-    end
-  end
-
-  def delete_test_definition(test)
-    test_definition_str = get_test_definition_str(test)
-    get_tools_compilers.each do |tools_compiler_key, tools_compiler_value|
-      num_options = tools_compiler_value[:arguments].size
-      @streaminator.stdout_puts("Delete the definition value in the build option #{tools_compiler_value[:arguments][-1]} #{tools_compiler_key}", Verbosity::OBNOXIOUS)
-      tools_compiler_value[:arguments].delete_if{|i| i == test_definition_str}
-      if num_options > tools_compiler_value[:arguments].size + 1
-        @streaminator.stderr_puts("WARNING: duplicated test definition.")
-      end
-    end
-  end
 
   # Convert libraries configuration form YAML configuration
   # into a string that can be given to the compiler.
   def convert_libraries_to_arguments()
-    if @configurator.project_config_hash.has_key?(:libraries_test)
-      lib_args = @configurator.project_config_hash[:libraries_test]
-      lib_args.flatten!
-      lib_flag = @configurator.project_config_hash[:libraries_flag]
-      lib_args.map! {|v| lib_flag.gsub(/\$\{1\}/, v) } if (defined? lib_flag)
-      return lib_args
+    args = ((@configurator.project_config_hash[:libraries_test] || []) + ((defined? LIBRARIES_SYSTEM) ? LIBRARIES_SYSTEM : [])).flatten
+    if (defined? LIBRARIES_FLAG)
+      args.map! {|v| LIBRARIES_FLAG.gsub(/\$\{1\}/, v) }
     end
+    return args
   end
 
+  def get_library_paths_to_arguments()
+    paths = (defined? PATHS_LIBRARIES) ? (PATHS_LIBRARIES || []).clone : []
+    if (defined? LIBRARIES_PATH_FLAG)
+      paths.map! {|v| LIBRARIES_PATH_FLAG.gsub(/\$\{1\}/, v) }
+    end
+    return paths
+  end
 
   def setup_and_invoke(tests, context=TEST_SYM, options={:force_run => true, :build_only => false})
 
@@ -83,18 +58,25 @@ class TestInvoker
         test_name ="#{File.basename(test)}".chomp('.c')
         def_test_key="defines_#{test_name.downcase}"
 
-        # Re-define the project out path and pre-processor defines.
-        if @configurator.project_config_hash.has_key?(def_test_key.to_sym)
-          @project_config_manager.test_config_changed
+        if @configurator.project_config_hash.has_key?(def_test_key.to_sym) || @configurator.defines_use_test_definition
           defs_bkp = Array.new(COLLECTION_DEFINES_TEST_AND_VENDOR)
-          printf " ************** Specific test definitions for #{test_name} !!! \n"
-          tst_defs_cfg = @configurator.project_config_hash[def_test_key.to_sym]
+          tst_defs_cfg = Array.new(defs_bkp)
+          if @configurator.project_config_hash.has_key?(def_test_key.to_sym)
+            tst_defs_cfg.replace(@configurator.project_config_hash[def_test_key.to_sym])
+            tst_defs_cfg .concat(COLLECTION_DEFINES_VENDOR) if COLLECTION_DEFINES_VENDOR
+          end
+          if @configurator.defines_use_test_definition
+            tst_defs_cfg << File.basename(test, ".*").strip.upcase.sub(/@.*$/, "")
+          end
+          COLLECTION_DEFINES_TEST_AND_VENDOR.replace(tst_defs_cfg)
+        end
 
+        # redefine the project out path and preprocessor defines
+        if @configurator.project_config_hash.has_key?(def_test_key.to_sym)
+          @streaminator.stdout_puts("Updating test definitions for #{test_name}", Verbosity::NORMAL)
           orig_path = @configurator.project_test_build_output_path
           @configurator.project_config_hash[:project_test_build_output_path] = File.join(@configurator.project_test_build_output_path, test_name)
           @file_wrapper.mkdir(@configurator.project_test_build_output_path)
-          COLLECTION_DEFINES_TEST_AND_VENDOR.replace(tst_defs_cfg)
-          # printf " *  new defines = #{COLLECTION_DEFINES_TEST_AND_VENDOR}\n"
         end
 
         # collect up test fixture pieces & parts
@@ -103,16 +85,15 @@ class TestInvoker
         sources      = @test_invoker_helper.extract_sources( test )
         extras       = @configurator.collection_test_fixture_extra_link_objects
         core         = [test] + mock_list + sources
-        objects      = @file_path_utils.form_test_build_objects_filelist( [runner] + core + extras )
+        objects      = @file_path_utils.form_test_build_objects_filelist( [runner] + core + extras ).uniq
         results_pass = @file_path_utils.form_pass_results_filepath( test )
         results_fail = @file_path_utils.form_fail_results_filepath( test )
 
-        @project_config_manager.process_test_defines_change(sources)
+        # identify all the objects shall not be linked and then remove them from objects list.
+        no_link_objects = @file_path_utils.form_test_build_objects_filelist(@preprocessinator.preprocess_shallow_source_includes( test ))
+        objects = objects.uniq - no_link_objects
 
-        # add the definition value in the build option for the unit test
-        if @configurator.defines_use_test_definition
-          add_test_definition(test)
-        end
+        @project_config_manager.process_test_defines_change(@project_config_manager.filter_internal_sources(sources))
 
         # clean results files so we have a missing file with which to kick off rake's dependency rules
         @test_invoker_helper.clean_results( {:pass => results_pass, :fail => results_fail}, options )
@@ -129,7 +110,7 @@ class TestInvoker
         @dependinator.enhance_test_build_object_dependencies( objects )
 
         # associate object files with executable
-        @dependinator.setup_test_executable_dependencies( test, objects )
+        @dependinator.enhance_test_executable_dependencies( test, objects )
 
         # build test objects
         @task_invoker.invoke_test_objects( objects )
@@ -146,18 +127,14 @@ class TestInvoker
       rescue => e
         @build_invoker_utils.process_exception( e, context )
       ensure
-        # delete the definition value in the build option for the unit test
-        if @configurator.defines_use_test_definition
-          delete_test_definition(test)
-        end
         @plugin_manager.post_test( test )
         # restore the project test defines
-        if @configurator.project_config_hash.has_key?(def_test_key.to_sym)
-          # @configurator.project_config_hash[:defines_test] =
+        if @configurator.project_config_hash.has_key?(def_test_key.to_sym) || @configurator.defines_use_test_definition
           COLLECTION_DEFINES_TEST_AND_VENDOR.replace(defs_bkp)
-          # printf " ---- Restored defines at #{defs_bkp}"
-          @configurator.project_config_hash[:project_test_build_output_path] = orig_path
-          printf " ************** Restored defines and build path\n"
+          if @configurator.project_config_hash.has_key?(def_test_key.to_sym)
+            @configurator.project_config_hash[:project_test_build_output_path] = orig_path
+            @streaminator.stdout_puts("Restored defines and build path to standard", Verbosity::NORMAL)
+          end
         end
       end
 
diff --git a/test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb b/test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb
index b0a223f56..403d93e3e 100644
--- a/test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb
+++ b/test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb
@@ -11,7 +11,7 @@ class TestInvokerHelper
   def process_deep_dependencies(files)
     return if (not @configurator.project_use_deep_dependencies)
 
-    dependencies_list = @file_path_utils.form_test_dependencies_filelist( files )
+    dependencies_list = @file_path_utils.form_test_dependencies_filelist( files ).uniq
 
     if @configurator.project_generate_deep_dependencies
       @task_invoker.invoke_test_dependencies_files( dependencies_list )
diff --git a/test/vendor/ceedling/lib/ceedling/version.rb b/test/vendor/ceedling/lib/ceedling/version.rb
index ba917df5a..ebda10b78 100644
--- a/test/vendor/ceedling/lib/ceedling/version.rb
+++ b/test/vendor/ceedling/lib/ceedling/version.rb
@@ -2,35 +2,53 @@
 # @private
 module Ceedling
   module Version
-    # Check for local or global version of vendor directory in order to look up versions
-    { 
-      "CEXCEPTION" => File.join("vendor","c_exception","lib","CException.h"),
-      "CMOCK"      => File.join("vendor","cmock","src","cmock.h"),
-      "UNITY"      => File.join("vendor","unity","src","unity.h"),
+    { "UNITY" => File.join("unity","src","unity.h"),
+      "CMOCK" => File.join("cmock","src","cmock.h"),
+      "CEXCEPTION" => File.join("c_exception","lib","CException.h")
     }.each_pair do |name, path|
-      filename = if (File.exist?(File.join("..","..",path)))
-        File.join("..","..",path)
-      elsif (File.exist?(File.join(File.dirname(__FILE__),"..","..",path)))
-        File.join(File.dirname(__FILE__),"..","..",path)
+      # Check for local or global version of vendor directory in order to look up versions
+      path1 = File.expand_path( File.join("..","..","vendor",path) )
+      path2 = File.expand_path( File.join(File.dirname(__FILE__),"..","..","vendor",path) )
+      filename = if (File.exists?(path1))
+        path1
+      elsif (File.exists?(path2))
+        path2
+      elsif File.exists?(CEEDLING_VENDOR)
+        path3 = File.expand_path( File.join(CEEDLING_VENDOR,path) )
+        if (File.exists?(path3))
+          path3
+        else
+          basepath = File.join( CEEDLING_VENDOR, path.split(/\\\//)[0], 'release')
+          begin
+            [ @ceedling[:file_wrapper].read( File.join(base_path, 'release', 'version.info') ).strip,
+              @ceedling[:file_wrapper].read( File.join(base_path, 'release', 'build.info') ).strip ].join('.')
+          rescue
+            "#{name}"
+          end
+        end
       else
-        eval "#{name} = 'unknown'"
+        module_eval("#{name} = 'unknown'")
         continue
       end
 
       # Actually look up the versions
       a = [0,0,0]
-      File.readlines(filename) do |line|
-        ["VERSION_MAJOR", "VERSION_MINOR", "VERSION_BUILD"].each_with_index do |field, i|
-          m = line.match(/#{name}_#{field}\s+(\d+)/)
-          a[i] = m[1] unless (m.nil?)
+      begin
+        File.readlines(filename).each do |line|
+          ["VERSION_MAJOR", "VERSION_MINOR", "VERSION_BUILD"].each_with_index do |field, i|
+            m = line.match(/#{name}_#{field}\s+(\d+)/)
+            a[i] = m[1] unless (m.nil?)
+          end
         end
+      rescue
+        abort("Can't collect data for vendor component: \"#{filename}\" . \nPlease check your setup.")
       end
 
-      # Make a constant from each, so that we can use it elsewhere
-      eval "#{name} = '#{a.join(".")}'"
+      # splat it to return the final value
+      eval("#{name} = '#{a.join(".")}'")
     end
 
-    GEM = "0.29.0"
+    GEM = "0.31.1"
     CEEDLING = GEM
   end
 end
diff --git a/test/vendor/ceedling/lib/ceedling/version.rb.erb b/test/vendor/ceedling/lib/ceedling/version.rb.erb
deleted file mode 100644
index a31e3abb3..000000000
--- a/test/vendor/ceedling/lib/ceedling/version.rb.erb
+++ /dev/null
@@ -1,15 +0,0 @@
-# @private
-module Ceedling
-  module Version
-    # @private
-    GEM = "0.27.0"
-    # @private
-    CEEDLING = "<%= versions["CEEDLING"] %>"
-    # @private
-    CEXCEPTION = "<%= versions["CEXCEPTION"] %>"
-    # @private
-    CMOCK = "<%= versions["CMOCK"] %>"
-    # @private
-    UNITY = "<%= versions["UNITY"] %>"
-  end
-end
diff --git a/test/vendor/ceedling/plugins/bullseye/bullseye.rake b/test/vendor/ceedling/plugins/bullseye/bullseye.rake
index a7bbebe3a..11073e786 100644
--- a/test/vendor/ceedling/plugins/bullseye/bullseye.rake
+++ b/test/vendor/ceedling/plugins/bullseye/bullseye.rake
@@ -32,12 +32,16 @@ rule(/#{BULLSEYE_BUILD_OUTPUT_PATH}\/#{'.+\\'+EXTENSION_OBJECT}$/ => [
 end
 
 rule(/#{BULLSEYE_BUILD_OUTPUT_PATH}\/#{'.+\\'+EXTENSION_EXECUTABLE}$/) do |bin_file|
+  lib_args = @ceedling[:test_invoker].convert_libraries_to_arguments()
+  lib_paths = @ceedling[:test_invoker].get_library_paths_to_arguments()
   @ceedling[:generator].generate_executable_file(
     TOOLS_BULLSEYE_LINKER,
     BULLSEYE_SYM,
     bin_file.prerequisites,
     bin_file.name,
-    @ceedling[:file_path_utils].form_test_build_map_filepath(bin_file.name)
+    @ceedling[:file_path_utils].form_test_build_map_filepath(bin_file.name),
+    lib_args,
+    lib_paths
   )
 end
 
@@ -69,7 +73,7 @@ namespace BULLSEYE_SYM do
   task source_coverage: COLLECTION_ALL_SOURCE.pathmap("#{BULLSEYE_BUILD_OUTPUT_PATH}/%n#{@ceedling[:configurator].extension_object}")
 
   desc 'Run code coverage for all tests'
-  task all: [:directories] do
+  task all: [:test_deps] do
     @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
     @ceedling[BULLSEYE_SYM].enableBullseye(true)
     @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, BULLSEYE_SYM)
@@ -81,18 +85,18 @@ namespace BULLSEYE_SYM do
     message = "\nOops! '#{BULLSEYE_ROOT_NAME}:*' isn't a real task. " +
               "Use a real test or source file name (no path) in place of the wildcard.\n" +
               "Example: rake #{BULLSEYE_ROOT_NAME}:foo.c\n\n"
-  
+
     @ceedling[:streaminator].stdout_puts( message )
   end
-  
+
   desc 'Run tests by matching regular expression pattern.'
-  task :pattern, [:regex] => [:directories] do |_t, args|
+  task :pattern, [:regex] => [:test_deps] do |_t, args|
     matches = []
-    
+
     COLLECTION_ALL_TESTS.each do |test|
       matches << test if test =~ /#{args.regex}/
     end
-  
+
     if !matches.empty?
       @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
       @ceedling[BULLSEYE_SYM].enableBullseye(true)
@@ -104,13 +108,13 @@ namespace BULLSEYE_SYM do
   end
 
   desc 'Run tests whose test path contains [dir] or [dir] substring.'
-  task :path, [:dir] => [:directories] do |_t, args|
+  task :path, [:dir] => [:test_deps] do |_t, args|
     matches = []
-    
+
     COLLECTION_ALL_TESTS.each do |test|
       matches << test if File.dirname(test).include?(args.dir.tr('\\', '/'))
     end
-  
+
     if !matches.empty?
       @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
       @ceedling[BULLSEYE_SYM].enableBullseye(true)
@@ -122,13 +126,13 @@ namespace BULLSEYE_SYM do
   end
 
   desc 'Run code coverage for changed files'
-  task delta: [:directories] do
+  task delta: [:test_deps] do
     @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
     @ceedling[BULLSEYE_SYM].enableBullseye(true)
     @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, BULLSEYE_SYM, {:force_run => false})
     @ceedling[:configurator].restore_config
   end
-  
+
   # use a rule to increase efficiency for large projects
   # bullseye test tasks by regex
   rule(/^#{BULLSEYE_TASK_ROOT}\S+$/ => [
@@ -138,7 +142,7 @@ namespace BULLSEYE_SYM do
         @ceedling[:file_finder].find_test_from_file_path(test)
       end
   ]) do |test|
-    @ceedling[:rake_wrapper][:directories].invoke
+    @ceedling[:rake_wrapper][:test_deps].invoke
     @ceedling[:configurator].replace_flattened_config(@ceedling[BULLSEYE_SYM].config)
     @ceedling[BULLSEYE_SYM].enableBullseye(true)
     @ceedling[:test_invoker].setup_and_invoke([test.source], BULLSEYE_SYM)
@@ -159,11 +163,11 @@ end
 end
 
 namespace UTILS_SYM do
-  
+
   desc "Open Bullseye code coverage browser"
   task BULLSEYE_SYM do
     command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_BROWSER, [])
     @ceedling[:tool_executor].exec(command[:line], command[:options])
   end
-  
+
 end
diff --git a/test/vendor/ceedling/plugins/bullseye/readme.txt b/test/vendor/ceedling/plugins/bullseye/readme.txt
deleted file mode 100644
index e69de29bb..000000000
diff --git a/test/vendor/ceedling/plugins/gcov/README.md b/test/vendor/ceedling/plugins/gcov/README.md
index 096ffa100..b144e3b74 100644
--- a/test/vendor/ceedling/plugins/gcov/README.md
+++ b/test/vendor/ceedling/plugins/gcov/README.md
@@ -7,95 +7,427 @@ Plugin for integrating GNU GCov code coverage tool into Ceedling projects.
 Currently only designed for the gcov command (like LCOV for example). In the
 future we could configure this to work with other code coverage tools.
 
-This plugin currently uses `gcovr` to generate HTML and/or XML reports as a
-utility. The normal gcov plugin _must_ be run first for this report to generate.
+This plugin currently uses [gcovr](https://www.gcovr.com/) and / or
+[ReportGenerator](https://danielpalme.github.io/ReportGenerator/)
+as utilities to generate HTML, XML, JSON, or Text reports. The normal gcov
+plugin _must_ be run first for these reports to generate.
 
 ## Installation
 
-Gcovr can be installed via pip like so:
+gcovr can be installed via pip like so:
 
-```
+```sh
 pip install gcovr
 ```
 
+ReportGenerator can be installed via .NET Core like so:
+
+```sh
+dotnet tool install -g dotnet-reportgenerator-globaltool
+```
+
+It is not required to install both `gcovr` and `ReportGenerator`. Either utility
+may be installed to create reports.
+
 ## Configuration
 
 The gcov plugin supports configuration options via your `project.yml` provided
 by Ceedling.
 
-Generation of HTML reports may be enabled or disabled with the following
-config. Set to `true` to enable or set to `false` to disable.
+### Utilities
 
-```
+Gcovr and / or ReportGenerator may be enabled to create coverage reports.
+
+```yaml
 :gcov:
-  :html_report: true
+  :utilities:
+    - gcovr           # Use gcovr to create the specified reports (default).
+    - ReportGenerator # Use ReportGenerator to create the specified reports.
 ```
 
-Generation of XML reports may be enabled or disabled with the following
-config. Set to `true` to enable or set to `false` to disable.
+### Reports
 
-```
+Various reports are available and may be enabled with the following
+configuration item. See the specific report sections in this README
+for additional options and information. All generated reports will be found in `build/artifacts/gcov`.
+
+```yaml
 :gcov:
-  :xml_report: true
+  # Specify one or more reports to generate.
+  # Defaults to HtmlBasic.
+  :reports:
+    # Make an HTML summary report.
+    # Supported utilities: gcovr, ReportGenerator
+    - HtmlBasic
+
+    # Make an HTML report with line by line coverage of each source file.
+    # Supported utilities: gcovr, ReportGenerator
+    - HtmlDetailed
+
+    # Make a Text report, which may be output to the console with gcovr or a file in both gcovr and ReportGenerator.
+    # Supported utilities: gcovr, ReportGenerator
+    - Text
+
+    # Make a Cobertura XML report.
+    # Supported utilities: gcovr, ReportGenerator
+    - Cobertura
+
+    # Make a SonarQube XML report.
+    # Supported utilities: gcovr, ReportGenerator
+    - SonarQube
+
+    # Make a JSON report.
+    # Supported utilities: gcovr
+    - JSON
+
+    # Make a detailed HTML report with CSS and JavaScript included in every HTML page. Useful for build servers.
+    # Supported utilities: ReportGenerator
+    - HtmlInline
+
+    # Make a detailed HTML report with a light theme and CSS and JavaScript included in every HTML page for Azure DevOps.
+    # Supported utilities: ReportGenerator
+    - HtmlInlineAzure
+
+    # Make a detailed HTML report with a dark theme and CSS and JavaScript included in every HTML page for Azure DevOps.
+    # Supported utilities: ReportGenerator
+    - HtmlInlineAzureDark
+
+    # Make a single HTML file containing a chart with historic coverage information.
+    # Supported utilities: ReportGenerator
+    - HtmlChart
+
+    # Make a detailed HTML report in a single file.
+    # Supported utilities: ReportGenerator
+    - MHtml
+
+    # Make SVG and PNG files that show line and / or branch coverage information.
+    # Supported utilities: ReportGenerator
+    - Badges
+
+    # Make a single CSV file containing coverage information per file.
+    # Supported utilities: ReportGenerator
+    - CsvSummary
+
+    # Make a single TEX file containing a summary for all files and detailed reports for each files.
+    # Supported utilities: ReportGenerator
+    - Latex
+
+    # Make a single TEX file containing a summary for all files.
+    # Supported utilities: ReportGenerator
+    - LatexSummary
+
+    # Make a single PNG file containing a chart with historic coverage information.
+    # Supported utilities: ReportGenerator
+    - PngChart
+
+    # Command line output interpreted by TeamCity.
+    # Supported utilities: ReportGenerator
+    - TeamCitySummary
+
+    # Make a text file in lcov format.
+    # Supported utilities: ReportGenerator
+    - lcov
+
+    # Make a XML file containing a summary for all classes and detailed reports for each class.
+    # Supported utilities: ReportGenerator
+    - Xml
+
+    # Make a single XML file containing a summary for all files.
+    # Supported utilities: ReportGenerator
+    - XmlSummary
 ```
 
-There are two types of gcovr HTML reports that can be configured in your
-`project.yml`. To create a basic HTML report, with only the overall file
-information, use the following config.
+### Gcovr HTML Reports
 
-```
+Generation of Gcovr HTML reports may be modified with the following configuration items.
+
+```yaml
 :gcov:
-  :html_report_type: basic
+  # Set to 'true' to enable HTML reports or set to 'false' to disable.
+  # Defaults to enabled. (gcovr --html)
+  # Deprecated - See the :reports: configuration option.
+  :html_report: [true|false]
+
+  # Gcovr supports generating two types of HTML reports. Use 'basic' to create
+  # an HTML report with only the overall file information. Use 'detailed' to create
+  # an HTML report with line by line coverage of each source file.
+  # Defaults to 'basic'. Set to 'detailed' for (gcovr --html-details).
+  # Deprecated - See the :reports: configuration option.
+  :html_report_type: [basic|detailed]
+
+
+  :gcovr:
+    # HTML report filename.
+    :html_artifact_filename: <output>
+
+    # Use 'title' as title for the HTML report.
+    # Default is 'Head'. (gcovr --html-title)
+    :html_title: <title>
+
+    # If the coverage is below MEDIUM, the value is marked as low coverage in the HTML report.
+    # MEDIUM has to be lower than or equal to value of html_high_threshold.
+    # If MEDIUM is equal to value of html_high_threshold the report has only high and low coverage.
+    # Default is 75.0. (gcovr --html-medium-threshold)
+    :html_medium_threshold: 75
+
+    # If the coverage is below HIGH, the value is marked as medium coverage in the HTML report.
+    # HIGH has to be greater than or equal to value of html_medium_threshold.
+    # If HIGH is equal to value of html_medium_threshold the report has only high and low coverage.
+    # Default is 90.0. (gcovr -html-high-threshold)
+    :html_high_threshold: 90
+
+    # Set to 'true' to use absolute paths to link the 'detailed' reports.
+    # Defaults to relative links. (gcovr --html-absolute-paths)
+    :html_absolute_paths: [true|false]
+
+    # Override the declared HTML report encoding. Defaults to UTF-8. (gcovr --html-encoding)
+    :html_encoding: <html_encoding>
 ```
 
-To create a detailed HTML report, with line by line breakdown of the
-coverage, use the following config.
+### Cobertura XML Reports
 
-```
+Generation of Cobertura XML reports may be modified with the following configuration items.
+
+```yaml
 :gcov:
-  :html_report_type: detailed
+  # Set to 'true' to enable Cobertura XML reports or set to 'false' to disable.
+  # Defaults to disabled. (gcovr --xml)
+  # Deprecated - See the :reports: configuration option.
+  :xml_report: [true|false]
+
+
+  :gcovr:
+    # Set to 'true' to pretty-print the Cobertura XML report, otherwise set to 'false'.
+    # Defaults to disabled. (gcovr --xml-pretty)
+    :xml_pretty: [true|false]
+    :cobertura_pretty: [true|false]
+
+    # Cobertura XML report filename.
+    :xml_artifact_filename: <output>
+    :cobertura_artifact_filename: <output>
 ```
 
+### SonarQube XML Reports
+
+Generation of SonarQube XML reports may be modified with the following configuration items.
+
+```yaml
+:gcov:
+  :gcovr:
+    # SonarQube XML report filename.
+    :sonarqube_artifact_filename: <output>
+```
+
+### JSON Reports
+
+Generation of JSON reports may be modified with the following configuration items.
+
+```yaml
+:gcov:
+  :gcovr:
+    # Set to 'true' to pretty-print the JSON report, otherwise set 'false'.
+    # Defaults to disabled. (gcovr --json-pretty)
+    :json_pretty: [true|false]
+
+    # JSON report filename.
+    :json_artifact_filename: <output>
+```
+
+### Text Reports
+
+Generation of text reports may be modified with the following configuration items.
+Text reports may be printed to the console or output to a file.
+
+```yaml
+:gcov:
+  :gcovr:
+    # Text report filename.
+    # The text report is printed to the console when no filename is provided.
+    :text_artifact_filename: <output>
+```
+
+### Common Report Options
+
 There are a number of options to control which files are considered part of
 the coverage report. Most often, we only care about coverage on our source code, and not
-on tests or automatically generated mocks, runners, etc. However, there are times 
-where this isn't true... or there are times where we've moved ceedling's directory 
+on tests or automatically generated mocks, runners, etc. However, there are times
+where this isn't true... or there are times where we've moved ceedling's directory
 structure so that the project file isn't at the root of the project anymore. In these
-cases, you may need to tweak the following:
+cases, you may need to tweak `report_include`, `report_exclude`, and `exclude_directories`.
 
-```
-:gcov:
-  :report_root: "."
-  :report_exclude: "^build|^vendor|^test|^support"
-  :report_include: "^src"
-```
-
-One important note about html_report_root: gcovr will only take a single root folder, unlike 
-Ceedling's ability to take as many as you like. So you will need to choose a folder which is 
+One important note about `report_root`: gcovr will take only a single root folder, unlike
+Ceedling's ability to take as many as you like. So you will need to choose a folder which is
 a superset of ALL the folders you want, and then use the include or exclude options to set up
 patterns of files to pay attention to or ignore. It's not ideal, but it works.
 
-Finally, there are a number of settings which can be specified in order to adjust the
-default behaviors of gcov:
+Finally, there are a number of settings which can be specified to adjust the
+default behaviors of gcovr:
 
-```
+```yaml
 :gcov:
-  :html_medium_threshold: 75
-  :html_high_threshold: 90
-  :fail_under_line: 30
-  :fail_under_branch: 30
+  :gcovr:
+    # The root directory of your source files. Defaults to ".", the current directory.
+    # File names are reported relative to this root. The report_root is the default report_include.
+    :report_root: "."
+
+    # Load the specified configuration file.
+    # Defaults to gcovr.cfg in the report_root directory. (gcovr --config)
+    :config_file: <config_file>
+
+    # Exit with a status of 2 if the total line coverage is less than MIN.
+    # Can be ORed with exit status of 'fail_under_branch' option. (gcovr --fail-under-line)
+    :fail_under_line: 30
+
+    # Exit with a status of 4 if the total branch coverage is less than MIN.
+    # Can be ORed with exit status of 'fail_under_line' option. (gcovr --fail-under-branch)
+    :fail_under_branch: 30
+
+    # Select the source file encoding.
+    # Defaults to the system default encoding (UTF-8). (gcovr --source-encoding)
+    :source_encoding: <source_encoding>
+
+    # Report the branch coverage instead of the line coverage. For text report only. (gcovr --branches).
+    :branches: [true|false]
+
+    # Sort entries by increasing number of uncovered lines.
+    # For text and HTML report. (gcovr --sort-uncovered)
+    :sort_uncovered: [true|false]
+
+    # Sort entries by increasing percentage of uncovered lines.
+    # For text and HTML report. (gcovr --sort-percentage)
+    :sort_percentage: [true|false]
+
+    # Print a small report to stdout with line & branch percentage coverage.
+    # This is in addition to other reports. (gcovr --print-summary).
+    :print_summary: [true|false]
+
+    # Keep only source files that match this filter. (gcovr --filter).
+    :report_include: "^src"
+
+    # Exclude source files that match this filter. (gcovr --exclude).
+    :report_exclude: "^vendor.*|^build.*|^test.*|^lib.*"
+
+    # Keep only gcov data files that match this filter. (gcovr --gcov-filter).
+    :gcov_filter: <gcov_filter>
+
+    # Exclude gcov data files that match this filter. (gcovr --gcov-exclude).
+    :gcov_exclude: <gcov_exclude>
+
+    # Exclude directories that match this regex while searching
+    # raw coverage files. (gcovr --exclude-directories).
+    :exclude_directories: <exclude_dirs>
+
+    # Use a particular gcov executable. (gcovr --gcov-executable).
+    :gcov_executable: <gcov_cmd>
+
+    # Exclude branch coverage from lines without useful
+    # source code. (gcovr --exclude-unreachable-branches).
+    :exclude_unreachable_branches: [true|false]
+
+    # For branch coverage, exclude branches that the compiler
+    # generates for exception handling. (gcovr --exclude-throw-branches).
+    :exclude_throw_branches: [true|false]
+
+    # Use existing gcov files for analysis. Default: False. (gcovr --use-gcov-files)
+    :use_gcov_files: [true|false]
+
+    # Skip lines with parse errors in GCOV files instead of
+    # exiting with an error. (gcovr --gcov-ignore-parse-errors).
+    :gcov_ignore_parse_errors: [true|false]
+
+    # Override normal working directory detection. (gcovr --object-directory)
+    :object_directory: <objdir>
+
+    # Keep gcov files after processing. (gcovr --keep).
+    :keep: [true|false]
+
+    # Delete gcda files after processing. (gcovr --delete).
+    :delete: [true|false]
+
+    # Set the number of threads to use in parallel. (gcovr -j).
+    :num_parallel_threads: <num_threads>
+
+  # When scanning the code coverage, if any files are found that do not have
+  # associated coverage data, the command will abort with an error message.
+  :abort_on_uncovered: true
+
+  # When using the ``abort_on_uncovered`` option, the files in this list will not
+  # trigger a failure.
+  # Ceedling globs described in the Ceedling packet ``Path`` section can be used
+  # when directories are placed on the list. Globs are limited to matching directories
+  # and not files.
+  :uncovered_ignore_list: []
 ```
 
-These HTML and XML reports will be found in `build/artifacts/gcov`.
+### ReportGenerator Configuration
+
+The ReportGenerator utility may be configured with the following configuration items.
+All generated reports may be found in `build/artifacts/gcov/ReportGenerator`.
+
+```yaml
+:gcov:
+  :report_generator:
+    # Optional directory for storing persistent coverage information.
+    # Can be used in future reports to show coverage evolution.
+    :history_directory: <history_directory>
+
+    # Optional plugin files for custom reports or custom history storage (separated by semicolon).
+    :plugins: CustomReports.dll
+
+    # Optional list of assemblies that should be included or excluded in the report (separated by semicolon)..
+    # Exclusion filters take precedence over inclusion filters.
+    # Wildcards are allowed, but not regular expressions.
+    :assembly_filters: "+Included;-Excluded"
+
+    # Optional list of classes that should be included or excluded in the report (separated by semicolon)..
+    # Exclusion filters take precedence over inclusion filters.
+    # Wildcards are allowed, but not regular expressions.
+    :class_filters: "+Included;-Excluded"
+
+    # Optional list of files that should be included or excluded in the report (separated by semicolon)..
+    # Exclusion filters take precedence over inclusion filters.
+    # Wildcards are allowed, but not regular expressions.
+    :file_filters: "-./vendor/*;-./build/*;-./test/*;-./lib/*;+./src/*"
+
+    # The verbosity level of the log messages.
+    # Values: Verbose, Info, Warning, Error, Off
+    :verbosity: Warning
+
+    # Optional tag or build version.
+    :tag: <tag>
+
+    # Optional list of one or more regular expressions to exclude gcov notes files that match these filters.
+    :gcov_exclude:
+      - <exclude_regex1>
+      - <exclude_regex2>
+
+    # Optionally use a particular gcov executable. Defaults to gcov.
+    :gcov_executable: <gcov_cmd>
+
+    # Optionally set the number of threads to use in parallel. Defaults to 1.
+    :num_parallel_threads: <num_threads>
+
+    # Optional list of one or more command line arguments to pass to Report Generator.
+    # Useful for configuring Risk Hotspots and Other Settings.
+    # https://github.com/danielpalme/ReportGenerator/wiki/Settings
+    :custom_args:
+      - <custom_arg1>
+      - <custom_arg2>
+```
 
 ## Example Usage
 
-```
+```sh
 ceedling gcov:all utils:gcov
 ```
 
 ## To-Do list
 
 - Generate overall report (combined statistics from all files with coverage)
-- Generate coverage output files
-- Easier option override for better customisation 
+
+## Citations
+
+Most of the comment text which describes the options was taken from the
+[Gcovr User Guide](https://www.gcovr.com/en/stable/guide.html) and the
+[ReportGenerator Wiki](https://github.com/danielpalme/ReportGenerator/wiki).
+The text is repeated here to provide the most accurate option functionality.
diff --git a/test/vendor/ceedling/plugins/gcov/config/defaults.yml b/test/vendor/ceedling/plugins/gcov/config/defaults.yml
deleted file mode 100644
index 13bac556e..000000000
--- a/test/vendor/ceedling/plugins/gcov/config/defaults.yml
+++ /dev/null
@@ -1,73 +0,0 @@
----
-
-:tools:
-  :gcov_compiler:
-    :executable: gcc
-    :arguments:
-      - -g
-      - -fprofile-arcs
-      - -ftest-coverage
-      - -I"$": COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR
-      - -I"$": COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE
-      - -D$: COLLECTION_DEFINES_TEST_AND_VENDOR
-      - -DGCOV_COMPILER
-      - -DCODE_COVERAGE
-      - -c "${1}"
-      - -o "${2}"
-  :gcov_linker:
-    :executable: gcc
-    :arguments:
-      - -fprofile-arcs
-      - -ftest-coverage
-      - ${1}
-      - -o ${2}
-      - ${3}
-  :gcov_fixture:
-    :executable: ${1}
-  :gcov_report:
-    :executable: gcov
-    :arguments:
-      - -n
-      - -p
-      - -b
-      - -o "$": GCOV_BUILD_OUTPUT_PATH
-      - "\"${1}\""
-  :gcov_post_report:
-    :executable: gcovr
-    :optional: TRUE
-    :arguments:
-        - -p
-        - -b
-        - ${1}
-        - --html
-        - -o GcovCoverageResults.html
-  :gcov_post_report_basic:
-    :executable: gcovr
-    :optional: TRUE
-    :arguments:
-        - -p
-        - -b
-        - ${1}
-        - --html
-        - -o  "$": GCOV_ARTIFACTS_FILE
-  :gcov_post_report_advanced:
-    :executable: gcovr
-    :optional: TRUE
-    :arguments:
-        - -p
-        - -b
-        - ${1}
-        - --html
-        - --html-details
-        - -o  "$": GCOV_ARTIFACTS_FILE
-  :gcov_post_report_xml:
-    :executable: gcovr
-    :optional: TRUE
-    :arguments:
-        - -p
-        - -b
-        - ${1}
-        - --xml
-        - -o  "$": GCOV_ARTIFACTS_FILE_XML
-
-...
diff --git a/test/vendor/ceedling/plugins/gcov/gcov.rake b/test/vendor/ceedling/plugins/gcov/gcov.rake
index 3acab8566..1467564a8 100644
--- a/test/vendor/ceedling/plugins/gcov/gcov.rake
+++ b/test/vendor/ceedling/plugins/gcov/gcov.rake
@@ -1,3 +1,6 @@
+require 'reportgenerator_reportinator'
+require 'gcovr_reportinator'
+
 directory(GCOV_BUILD_OUTPUT_PATH)
 directory(GCOV_RESULTS_PATH)
 directory(GCOV_ARTIFACTS_PATH)
@@ -16,7 +19,7 @@ rule(/#{GCOV_BUILD_OUTPUT_PATH}\/#{'.+\\' + EXTENSION_OBJECT}$/ => [
        end
      ]) do |object|
 
-  if File.basename(object.source) =~ /^(#{PROJECT_TEST_FILE_PREFIX}|#{CMOCK_MOCK_PREFIX}|#{GCOV_IGNORE_SOURCES.join('|')})/i
+  if File.basename(object.source) =~ /^(#{PROJECT_TEST_FILE_PREFIX}|#{CMOCK_MOCK_PREFIX})|(#{VENDORS_FILES.map{|source| '\b' + source + '\b'}.join('|')})/
     @ceedling[:generator].generate_object_file(
       TOOLS_GCOV_COMPILER,
       OPERATION_COMPILE_SYM,
@@ -32,14 +35,15 @@ end
 
 rule(/#{GCOV_BUILD_OUTPUT_PATH}\/#{'.+\\' + EXTENSION_EXECUTABLE}$/) do |bin_file|
   lib_args = @ceedling[:test_invoker].convert_libraries_to_arguments()
-
+  lib_paths = @ceedling[:test_invoker].get_library_paths_to_arguments()
   @ceedling[:generator].generate_executable_file(
     TOOLS_GCOV_LINKER,
     GCOV_SYM,
     bin_file.prerequisites,
     bin_file.name,
+    @ceedling[:file_path_utils].form_test_build_map_filepath(bin_file.name),
     lib_args,
-    @ceedling[:file_path_utils].form_test_build_map_filepath(bin_file.name)
+    lib_paths
   )
 end
 
@@ -71,7 +75,7 @@ namespace GCOV_SYM do
   task source_coverage: COLLECTION_ALL_SOURCE.pathmap("#{GCOV_BUILD_OUTPUT_PATH}/%n#{@ceedling[:configurator].extension_object}")
 
   desc 'Run code coverage for all tests'
-  task all: [:directories] do
+  task all: [:test_deps] do
     @ceedling[:configurator].replace_flattened_config(@ceedling[GCOV_SYM].config)
     @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, GCOV_SYM)
     @ceedling[:configurator].restore_config
@@ -87,7 +91,7 @@ namespace GCOV_SYM do
   end
 
   desc 'Run tests by matching regular expression pattern.'
-  task :pattern, [:regex] => [:directories] do |_t, args|
+  task :pattern, [:regex] => [:test_deps] do |_t, args|
     matches = []
 
     COLLECTION_ALL_TESTS.each do |test|
@@ -104,7 +108,7 @@ namespace GCOV_SYM do
   end
 
   desc 'Run tests whose test path contains [dir] or [dir] substring.'
-  task :path, [:dir] => [:directories] do |_t, args|
+  task :path, [:dir] => [:test_deps] do |_t, args|
     matches = []
 
     COLLECTION_ALL_TESTS.each do |test|
@@ -121,7 +125,7 @@ namespace GCOV_SYM do
   end
 
   desc 'Run code coverage for changed files'
-  task delta: [:directories] do
+  task delta: [:test_deps] do
     @ceedling[:configurator].replace_flattened_config(@ceedling[GCOV_SYM].config)
     @ceedling[:test_invoker].setup_and_invoke(COLLECTION_ALL_TESTS, GCOV_SYM, force_run: false)
     @ceedling[:configurator].restore_config
@@ -136,7 +140,7 @@ namespace GCOV_SYM do
            @ceedling[:file_finder].find_test_from_file_path(test)
          end
        ]) do |test|
-    @ceedling[:rake_wrapper][:directories].invoke
+    @ceedling[:rake_wrapper][:test_deps].invoke
     @ceedling[:configurator].replace_flattened_config(@ceedling[GCOV_SYM].config)
     @ceedling[:test_invoker].setup_and_invoke([test.source], GCOV_SYM)
     @ceedling[:configurator].restore_config
@@ -154,67 +158,52 @@ if PROJECT_USE_DEEP_DEPENDENCIES
 end
 
 namespace UTILS_SYM do
-  def gcov_args_builder(opts)
-    args = ""
-    args += "-r \"#{opts[:gcov_report_root] || '.'}\" " 
-    args += "-f \"#{opts[:gcov_report_include]}\" " unless opts[:gcov_report_include].nil?
-    args += "-e \"#{opts[:gcov_report_exclude] || GCOV_FILTER_EXCLUDE}\" "
-    [ :gcov_fail_under_line, :gcov_fail_under_branch, :gcov_html_medium_threshold, :gcov_html_high_threshold].each do |opt|
-      args += "--#{opt.to_s.gsub('_','-').sub(/:?gcov-/,'')} #{opts[opt]} " unless opts[opt].nil?
-    end
-    return args
+  # Report Creation Utilities
+  UTILITY_NAME_GCOVR = "gcovr"
+  UTILITY_NAME_REPORT_GENERATOR = "ReportGenerator"
+  UTILITY_NAMES = [UTILITY_NAME_GCOVR, UTILITY_NAME_REPORT_GENERATOR]
+
+  # Returns true is the given utility is enabled, otherwise returns false.
+  def is_utility_enabled(opts, utility_name)
+    return !(opts.nil?) && !(opts[:gcov_utilities].nil?) && (opts[:gcov_utilities].map(&:upcase).include? utility_name.upcase)
   end
 
-  desc 'Create gcov code coverage html report (must run ceedling gcov first)'
-  task GCOV_SYM do
 
+  desc "Create gcov code coverage html/xml/json/text report(s). (Note: Must run 'ceedling gcov' first)."
+  task GCOV_SYM do
+    # Get the gcov options from project.yml.
+    opts = @ceedling[:configurator].project_config_hash
+
+    # Create the artifacts output directory.
     if !File.directory? GCOV_ARTIFACTS_PATH
       FileUtils.mkdir_p GCOV_ARTIFACTS_PATH
     end
 
-    args = gcov_args_builder(@ceedling[:configurator].project_config_hash)
-
-    if @ceedling[:configurator].project_config_hash[:gcov_html_report].nil?
-      puts "In your project.yml, define: \n\n:gcov:\n  :html_report:\n\n to true or false to refine this feature."
-      puts "For now, assumimg you want an html report generated."
-      html_enabled = true
-    else
-      html_enabled = @ceedling[:configurator].project_config_hash[:gcov_html_report]
+    # Remove unsupported reporting utilities.
+    if !(opts[:gcov_utilities].nil?)
+      opts[:gcov_utilities].reject! { |item| !(UTILITY_NAMES.map(&:upcase).include? item.upcase) }
     end
 
-    if @ceedling[:configurator].project_config_hash[:gcov_xml_report].nil?
-      puts "In your project.yml, define: \n\n:gcov:\n  :xml_report:\n\n to true or false to refine this feature."
-      puts "For now, assumimg you do not want an xml report generated."
-      xml_enabled = false
-    else
-      xml_enabled = @ceedling[:configurator].project_config_hash[:gcov_xml_report]
+    # Default to gcovr when no reporting utilities are specified.
+    if opts[:gcov_utilities].nil? || opts[:gcov_utilities].empty?
+      opts[:gcov_utilities] = [UTILITY_NAME_GCOVR]
     end
 
-    if html_enabled
-      if @ceedling[:configurator].project_config_hash[:gcov_html_report_type] == 'basic'
-        puts "Creating a basic html report of gcov results in #{GCOV_ARTIFACTS_FILE}..."
-        command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_POST_REPORT_BASIC, [], args)
-        @ceedling[:tool_executor].exec(command[:line], command[:options])
-      elsif @ceedling[:configurator].project_config_hash[:gcov_html_report_type] == 'detailed'
-        puts "Creating a detailed html report of gcov results in #{GCOV_ARTIFACTS_FILE}..."
-        command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_POST_REPORT_ADVANCED, [], args)
-        @ceedling[:tool_executor].exec(command[:line], command[:options])
-
-      else
-        puts "In your project.yml, define: \n\n:gcov:\n  :html_report_type:\n\n to basic or detailed to refine this feature."
-        puts "For now, just creating basic."
-        puts "Creating a basic html report of gcov results in #{GCOV_ARTIFACTS_FILE}..."
-        command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_POST_REPORT_BASIC, [], args)
-        @ceedling[:tool_executor].exec(command[:line], command[:options])
-      end
+    if opts[:gcov_reports].nil?
+      opts[:gcov_reports] = []
     end
 
-    if xml_enabled
-      puts "Creating an xml report of gcov results in #{GCOV_ARTIFACTS_FILE_XML}..."
-      command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_POST_REPORT_XML, [], filter)
-      @ceedling[:tool_executor].exec(command[:line], command[:options])
+    gcovr_reportinator = GcovrReportinator.new(@ceedling)
+    gcovr_reportinator.support_deprecated_options(opts)
+
+    if is_utility_enabled(opts, UTILITY_NAME_GCOVR)
+      gcovr_reportinator.make_reports(opts)
+    end
+
+    if is_utility_enabled(opts, UTILITY_NAME_REPORT_GENERATOR)
+      reportgenerator_reportinator = ReportGeneratorReportinator.new(@ceedling)
+      reportgenerator_reportinator.make_reports(opts)
     end
 
-    puts "Done."
   end
 end
diff --git a/test/vendor/ceedling/plugins/gcov/lib/gcov.rb b/test/vendor/ceedling/plugins/gcov/lib/gcov.rb
index 15a1b4cfa..30c6326b8 100644
--- a/test/vendor/ceedling/plugins/gcov/lib/gcov.rb
+++ b/test/vendor/ceedling/plugins/gcov/lib/gcov.rb
@@ -82,10 +82,7 @@ class Gcov < Plugin
     banner = @ceedling[:plugin_reportinator].generate_banner "#{GCOV_ROOT_NAME.upcase}: CODE COVERAGE SUMMARY"
     @ceedling[:streaminator].stdout_puts "\n" + banner
 
-    coverage_sources = sources.clone
-    coverage_sources.delete_if { |item| item =~ /#{CMOCK_MOCK_PREFIX}.+#{EXTENSION_SOURCE}$/ }
-    coverage_sources.delete_if { |item| item =~ /#{GCOV_IGNORE_SOURCES.join('|')}#{EXTENSION_SOURCE}$/ }
-
+    coverage_sources = @ceedling[:project_config_manager].filter_internal_sources(sources)
     coverage_sources.each do |source|
       basename         = File.basename(source)
       command          = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_REPORT, [], [basename])
@@ -98,9 +95,35 @@ class Gcov < Plugin
       end
     end
 
+    ignore_path_list = @ceedling[:file_system_utils].collect_paths(@ceedling[:configurator].project_config_hash[:gcov_uncovered_ignore_list] || [])
+    ignore_uncovered_list = @ceedling[:file_wrapper].instantiate_file_list
+    ignore_path_list.each do |path|
+      if File.exists?(path) and not File.directory?(path)
+        ignore_uncovered_list.include(path)
+      else
+        ignore_uncovered_list.include(File.join(path, "*#{EXTENSION_SOURCE}"))
+      end
+    end
+
+    found_uncovered = false
     COLLECTION_ALL_SOURCE.each do |source|
       unless coverage_sources.include?(source)
-        @ceedling[:streaminator].stdout_puts("Could not find coverage results for " + source + "\n")
+        v = Verbosity::DEBUG
+        msg = "Could not find coverage results for " + source
+        if ignore_uncovered_list.include?(source)
+          msg += " [IGNORED]"
+        else
+          found_uncovered = true
+          v = Verbosity::NORMAL
+        end
+        msg += "\n"
+        @ceedling[:streaminator].stdout_puts(msg, v)
+      end
+    end
+    if found_uncovered
+      if @ceedling[:configurator].project_config_hash[:gcov_abort_on_uncovered]
+        @ceedling[:streaminator].stderr_puts("There were files with no coverage results: aborting.\n")
+        exit(-1)
       end
     end
   end
diff --git a/test/vendor/ceedling/plugins/gcov/lib/gcov_constants.rb b/test/vendor/ceedling/plugins/gcov/lib/gcov_constants.rb
index 539d46f75..74c9bbda8 100644
--- a/test/vendor/ceedling/plugins/gcov/lib/gcov_constants.rb
+++ b/test/vendor/ceedling/plugins/gcov/lib/gcov_constants.rb
@@ -1,19 +1,48 @@
 
-GCOV_ROOT_NAME         = 'gcov'.freeze
-GCOV_TASK_ROOT         = GCOV_ROOT_NAME + ':'
-GCOV_SYM               = GCOV_ROOT_NAME.to_sym
+GCOV_ROOT_NAME                  = 'gcov'.freeze
+GCOV_TASK_ROOT                  = GCOV_ROOT_NAME + ':'
+GCOV_SYM                        = GCOV_ROOT_NAME.to_sym
 
-GCOV_BUILD_PATH        = File.join(PROJECT_BUILD_ROOT, GCOV_ROOT_NAME)
-GCOV_BUILD_OUTPUT_PATH = File.join(GCOV_BUILD_PATH, "out")
-GCOV_RESULTS_PATH      = File.join(GCOV_BUILD_PATH, "results")
-GCOV_DEPENDENCIES_PATH = File.join(GCOV_BUILD_PATH, "dependencies")
-GCOV_ARTIFACTS_PATH    = File.join(PROJECT_BUILD_ARTIFACTS_ROOT, GCOV_ROOT_NAME)
+GCOV_BUILD_PATH                 = File.join(PROJECT_BUILD_ROOT, GCOV_ROOT_NAME)
+GCOV_BUILD_OUTPUT_PATH          = File.join(GCOV_BUILD_PATH, "out")
+GCOV_RESULTS_PATH               = File.join(GCOV_BUILD_PATH, "results")
+GCOV_DEPENDENCIES_PATH          = File.join(GCOV_BUILD_PATH, "dependencies")
+GCOV_ARTIFACTS_PATH             = File.join(PROJECT_BUILD_ARTIFACTS_ROOT, GCOV_ROOT_NAME)
+GCOV_REPORT_GENERATOR_PATH      = File.join(GCOV_ARTIFACTS_PATH, "ReportGenerator")
 
-GCOV_ARTIFACTS_FILE    = File.join(GCOV_ARTIFACTS_PATH, "GcovCoverageResults.html")
-GCOV_ARTIFACTS_FILE_XML    = File.join(GCOV_ARTIFACTS_PATH, "GcovCoverageResults.xml")
+GCOV_ARTIFACTS_FILE_HTML        = File.join(GCOV_ARTIFACTS_PATH, "GcovCoverageResults.html")
+GCOV_ARTIFACTS_FILE_COBERTURA   = File.join(GCOV_ARTIFACTS_PATH, "GcovCoverageCobertura.xml")
+GCOV_ARTIFACTS_FILE_SONARQUBE   = File.join(GCOV_ARTIFACTS_PATH, "GcovCoverageSonarQube.xml")
+GCOV_ARTIFACTS_FILE_JSON        = File.join(GCOV_ARTIFACTS_PATH, "GcovCoverage.json")
 
-GCOV_IGNORE_SOURCES    = %w(unity cmock cexception).freeze
+GCOV_FILTER_EXCLUDE_PATHS       = ['vendor', 'build', 'test', 'lib']
 
-GCOV_FILTER_EXCLUDE    = '^vendor.*|^build.*|^test.*|^lib.*'
+# gcovr supports regular expressions.
+GCOV_FILTER_EXCLUDE = GCOV_FILTER_EXCLUDE_PATHS.map{|path| '^'.concat(*path).concat('.*')}.join('|')
 
+# ReportGenerator supports text with wildcard characters.
+GCOV_REPORT_GENERATOR_FILE_FILTERS = GCOV_FILTER_EXCLUDE_PATHS.map{|path| File.join('-.', *path, '*')}.join(';')
 
+# Report Types
+class ReportTypes
+  HTML_BASIC = "HtmlBasic"
+  HTML_DETAILED = "HtmlDetailed"
+  HTML_CHART = "HtmlChart"
+  HTML_INLINE = "HtmlInline"
+  HTML_INLINE_AZURE = "HtmlInlineAzure"
+  HTML_INLINE_AZURE_DARK = "HtmlInlineAzureDark"
+  MHTML = "MHtml"
+  TEXT = "Text"
+  COBERTURA = "Cobertura"
+  SONARQUBE = "SonarQube"
+  JSON = "JSON"
+  BADGES = "Badges"
+  CSV_SUMMARY = "CsvSummary"
+  LATEX = "Latex"
+  LATEX_SUMMARY = "LatexSummary"
+  PNG_CHART = "PngChart"
+  TEAM_CITY_SUMMARY = "TeamCitySummary"
+  LCOV = "lcov"
+  XML = "Xml"
+  XML_SUMMARY = "XmlSummary"
+end
diff --git a/test/vendor/ceedling/plugins/junit_tests_report/lib/junit_tests_report.rb b/test/vendor/ceedling/plugins/junit_tests_report/lib/junit_tests_report.rb
index a777d07d7..310439380 100644
--- a/test/vendor/ceedling/plugins/junit_tests_report/lib/junit_tests_report.rb
+++ b/test/vendor/ceedling/plugins/junit_tests_report/lib/junit_tests_report.rb
@@ -44,7 +44,7 @@ class JunitTestsReport < Plugin
   def write_header( results, stream )
     results[:counts][:time] = @time_result.reduce(0, :+)
     stream.puts '<?xml version="1.0" encoding="utf-8" ?>'
-    stream.puts('<testsuites tests="%<total>d" failures="%<failed>d" skipped="%<ignored>d" time="%<time>f">' % results[:counts])
+    stream.puts('<testsuites tests="%<total>d" failures="%<failed>d" time="%<time>.3f">' % results[:counts])
   end
 
   def write_footer( stream )
@@ -53,7 +53,7 @@ class JunitTestsReport < Plugin
 
   def reorganise_results( results )
     # Reorganise the output by test suite instead of by result
-    suites = Hash.new{ |h,k| h[k] = {collection: [], total: 0, success: 0, failed: 0, ignored: 0, stdout: []} }
+    suites = Hash.new{ |h,k| h[k] = {collection: [], total: 0, success: 0, failed: 0, ignored: 0, errors: 0, stdout: []} }
     results[:successes].each do |result|
       source = result[:source]
       name = source[:file].sub(/\..{1,4}$/, "")
@@ -85,7 +85,7 @@ class JunitTestsReport < Plugin
 
   def write_suite( suite, stream )
     suite[:time] = @time_result.shift
-    stream.puts('  <testsuite name="%<name>s" tests="%<total>d" failures="%<failed>d" skipped="%<ignored>d" time="%<time>f">' % suite)
+    stream.puts('  <testsuite name="%<name>s" tests="%<total>d" failures="%<failed>d" skipped="%<ignored>d" errors="%<errors>d" time="%<time>.3f">' % suite)
 
     suite[:collection].each do |test|
       write_test( test, stream )
@@ -108,12 +108,17 @@ class JunitTestsReport < Plugin
   end
 
   def write_test( test, stream )
-    test[:test].gsub!('"', '&quot;')
+    test[:test].gsub!(/&/, '&amp;')
+    test[:test].gsub!(/</, '&lt;')
+    test[:test].gsub!(/>/, '&gt;')
+    test[:test].gsub!(/"/, '&quot;')
+    test[:test].gsub!(/'/, '&apos;')
+
     case test[:result]
     when :success
-      stream.puts('    <testcase name="%<test>s" />' % test)
+      stream.puts('    <testcase name="%<test>s" time="%<unity_test_time>.3f"/>' % test)
     when :failed
-      stream.puts('    <testcase name="%<test>s">' % test)
+      stream.puts('    <testcase name="%<test>s" time="%<unity_test_time>.3f">' % test)
       if test[:message].empty?
         stream.puts('      <failure />')
       else
@@ -121,7 +126,7 @@ class JunitTestsReport < Plugin
       end
       stream.puts('    </testcase>')
     when :ignored
-      stream.puts('    <testcase name="%<test>s">' % test)
+      stream.puts('    <testcase name="%<test>s" time="%<unity_test_time>.3f">' % test)
       stream.puts('      <skipped />')
       stream.puts('    </testcase>')
     end
diff --git a/test/vendor/ceedling/plugins/module_generator/lib/module_generator.rb b/test/vendor/ceedling/plugins/module_generator/lib/module_generator.rb
index b2fac006d..d14288c36 100644
--- a/test/vendor/ceedling/plugins/module_generator/lib/module_generator.rb
+++ b/test/vendor/ceedling/plugins/module_generator/lib/module_generator.rb
@@ -18,6 +18,14 @@ class ModuleGenerator < Plugin
     end
   end
 
+  def stub_from_header(module_name, optz={})
+    require "cmock.rb" #From CMock
+    stuboptz = divine_options(optz)
+    pathname = optz[:path_inc] || optz[:path_src] || "src"
+    filename = File.expand_path(optz[:module_root_path], File.join(pathname, module_name + ".h"))
+    CMock.new(stuboptz).setup_skeletons(filename)
+  end
+
   private
 
   def divine_options(optz={})
@@ -37,6 +45,8 @@ class ModuleGenerator < Plugin
       :boilerplates => ((defined? MODULE_GENERATOR_BOILERPLATES) ? MODULE_GENERATOR_BOILERPLATES : {} ),
       :naming       => ((defined? MODULE_GENERATOR_NAMING      ) ? MODULE_GENERATOR_NAMING : nil ),
       :update_svn   => ((defined? MODULE_GENERATOR_UPDATE_SVN  ) ? MODULE_GENERATOR_UPDATE_SVN : false ),
+      :skeleton_path=> ((defined? MODULE_GENERATOR_SOURCE_ROOT ) ? MODULE_GENERATOR_SOURCE_ROOT.gsub('\\', '/').sub(/^\//, '').sub(/\/$/, '') : "src" ),
+      :test_define  => ((defined? MODULE_GENERATOR_TEST_DEFINE ) ? MODULE_GENERATOR_TEST_DEFINE : "TEST" ),
     }
 
     # Read Boilerplate template file.
@@ -44,15 +54,15 @@ class ModuleGenerator < Plugin
 
       bf = MODULE_GENERATOR_BOILERPLATE_FILES
 
-      if !bf[:src].nil? && File.exists?(bf[:src]) 
+      if !bf[:src].nil? && File.exists?(bf[:src])
         unity_generator_options[:boilerplates][:src] = File.read(bf[:src])
       end
 
-      if !bf[:inc].nil? && File.exists?(bf[:inc]) 
+      if !bf[:inc].nil? && File.exists?(bf[:inc])
         unity_generator_options[:boilerplates][:inc] = File.read(bf[:inc])
       end
 
-      if !bf[:tst].nil? && File.exists?(bf[:tst]) 
+      if !bf[:tst].nil? && File.exists?(bf[:tst])
         unity_generator_options[:boilerplates][:tst] = File.read(bf[:tst])
       end
     end
diff --git a/test/vendor/ceedling/plugins/module_generator/module_generator.rake b/test/vendor/ceedling/plugins/module_generator/module_generator.rake
index e88e346aa..f4ed9f113 100644
--- a/test/vendor/ceedling/plugins/module_generator/module_generator.rake
+++ b/test/vendor/ceedling/plugins/module_generator/module_generator.rake
@@ -26,6 +26,21 @@ namespace :module do
     end
   end
 
+  desc "Generate module stubs from header"
+  task :stub, :module_path do |t, args|
+    files = [args[:module_path]] + (args.extras || [])
+    optz = { :module_root_path => "" }
+    files.each do |v|
+      module_root_path, module_name = v.split(module_root_separator, 2)
+      if module_name
+        optz[:module_root_path] = module_root_path
+        v = module_name
+      end
+      # Otherwise, go through the normal procedure
+      @ceedling[:module_generator].stub_from_header(v, optz)
+    end
+  end
+
   desc "Destroy module (source, header and test files)"
   task :destroy, :module_path do |t, args|
     files = [args[:module_path]] + (args.extras || [])
diff --git a/test/vendor/ceedling/plugins/subprojects/lib/subprojects.rb b/test/vendor/ceedling/plugins/subprojects/lib/subprojects.rb
index 1f5d4c2f7..559251ed8 100644
--- a/test/vendor/ceedling/plugins/subprojects/lib/subprojects.rb
+++ b/test/vendor/ceedling/plugins/subprojects/lib/subprojects.rb
@@ -20,7 +20,7 @@ class Subprojects < Plugin
       end
     end
 
-    #gather information about the subprojects
+    # Gather information about the subprojects
     @subprojects = {}
     @subproject_lookup_by_path = {}
     SUBPROJECTS_PATHS.each do |subproj|
@@ -84,7 +84,7 @@ class Subprojects < Plugin
     Object.send(:remove_const, constant.to_sym) if (Object.const_defined? constant)
     Object.const_set(constant, new_value)
   end
- 
+
 end
 
 # end blocks always executed following rake run
diff --git a/test/vendor/ceedling/plugins/xml_tests_report/README.md b/test/vendor/ceedling/plugins/xml_tests_report/README.md
index ce81eadf3..6200c7dea 100644
--- a/test/vendor/ceedling/plugins/xml_tests_report/README.md
+++ b/test/vendor/ceedling/plugins/xml_tests_report/README.md
@@ -1,5 +1,5 @@
 xml_tests_report
-====================
+================
 
 ## Overview
 
diff --git a/test/vendor/ceedling/vendor/c_exception/lib/CException.h b/test/vendor/ceedling/vendor/c_exception/lib/CException.h
index 78f2f940c..be9e18695 100644
--- a/test/vendor/ceedling/vendor/c_exception/lib/CException.h
+++ b/test/vendor/ceedling/vendor/c_exception/lib/CException.h
@@ -11,7 +11,7 @@ extern "C"
 
 #define CEXCEPTION_VERSION_MAJOR    1
 #define CEXCEPTION_VERSION_MINOR    3
-#define CEXCEPTION_VERSION_BUILD    2
+#define CEXCEPTION_VERSION_BUILD    3
 #define CEXCEPTION_VERSION          ((CEXCEPTION_VERSION_MAJOR << 16) | (CEXCEPTION_VERSION_MINOR << 8) | CEXCEPTION_VERSION_BUILD)
 
 //To Use CException, you have a number of options:
diff --git a/test/vendor/ceedling/vendor/c_exception/release/build.info b/test/vendor/ceedling/vendor/c_exception/release/build.info
deleted file mode 100644
index 0cd525d8c..000000000
--- a/test/vendor/ceedling/vendor/c_exception/release/build.info
+++ /dev/null
@@ -1,2 +0,0 @@
-18
-
diff --git a/test/vendor/ceedling/vendor/c_exception/release/version.info b/test/vendor/ceedling/vendor/c_exception/release/version.info
deleted file mode 100644
index 1527a8de2..000000000
--- a/test/vendor/ceedling/vendor/c_exception/release/version.info
+++ /dev/null
@@ -1,2 +0,0 @@
-1.3.1
-
diff --git a/test/vendor/ceedling/vendor/cmock/config/production_environment.rb b/test/vendor/ceedling/vendor/cmock/config/production_environment.rb
index 915582b79..082b63fde 100644
--- a/test/vendor/ceedling/vendor/cmock/config/production_environment.rb
+++ b/test/vendor/ceedling/vendor/cmock/config/production_environment.rb
@@ -2,13 +2,11 @@
 #   CMock Project - Automatic Mock Generation for C
 #   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
 #   [Released under MIT License. Please refer to license.txt for details]
-# ========================================== 
- 
+# ==========================================
+
 # Setup our load path:
-[ 
- 'lib',
+[
+  'lib'
 ].each do |dir|
-  $LOAD_PATH.unshift( File.join( File.expand_path(File.dirname(__FILE__)) + '/../', dir) )
+  $:.unshift(File.join(__dir__ + '/../', dir))
 end
-
-
diff --git a/test/vendor/ceedling/vendor/cmock/config/test_environment.rb b/test/vendor/ceedling/vendor/cmock/config/test_environment.rb
index fe1ed817a..aeae3a342 100644
--- a/test/vendor/ceedling/vendor/cmock/config/test_environment.rb
+++ b/test/vendor/ceedling/vendor/cmock/config/test_environment.rb
@@ -12,5 +12,5 @@
   './vendor/unity/auto/',
   './test/system/'
 ].each do |dir|
-  $LOAD_PATH.unshift( File.join( File.expand_path(File.dirname(__FILE__) + "/../"), dir) )
+  $:.unshift(File.join(File.expand_path(File.dirname(__FILE__) + '/../'), dir))
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock.rb
index 8243ce58a..72f864189 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock.rb
@@ -4,49 +4,63 @@
 #   [Released under MIT License. Please refer to license.txt for details]
 # ==========================================
 
-[ "../config/production_environment",
-  "cmock_header_parser",
-  "cmock_generator",
-  "cmock_file_writer",
-  "cmock_config",
-  "cmock_plugin_manager",
-  "cmock_generator_utils",
-  "cmock_unityhelper_parser"].each {|req| require "#{File.expand_path(File.dirname(__FILE__))}/#{req}"}
+['../config/production_environment',
+ 'cmock_header_parser',
+ 'cmock_generator',
+ 'cmock_file_writer',
+ 'cmock_config',
+ 'cmock_plugin_manager',
+ 'cmock_generator_utils',
+ 'cmock_unityhelper_parser'].each { |req| require "#{__dir__}/#{req}" }
 
 class CMock
-
-  def initialize(options=nil)
+  def initialize(options = nil)
     cm_config      = CMockConfig.new(options)
     cm_unityhelper = CMockUnityHelperParser.new(cm_config)
     cm_writer      = CMockFileWriter.new(cm_config)
-    cm_gen_utils   = CMockGeneratorUtils.new(cm_config, {:unity_helper => cm_unityhelper})
+    cm_gen_utils   = CMockGeneratorUtils.new(cm_config,
+                                             :unity_helper => cm_unityhelper)
     cm_gen_plugins = CMockPluginManager.new(cm_config, cm_gen_utils)
     @cm_parser     = CMockHeaderParser.new(cm_config)
-    @cm_generator  = CMockGenerator.new(cm_config, cm_writer, cm_gen_utils, cm_gen_plugins)
+    @cm_generator  = CMockGenerator.new(cm_config, cm_writer, cm_gen_utils,
+                                        cm_gen_plugins)
     @silent        = (cm_config.verbosity < 2)
   end
 
-  def setup_mocks(files)
+  def setup_mocks(files, folder = nil)
     [files].flatten.each do |src|
-      generate_mock src
+      generate_mock(src, folder)
+    end
+  end
+
+  def setup_skeletons(files)
+    [files].flatten.each do |src|
+      generate_skeleton src
     end
   end
 
   private ###############################
 
-  def generate_mock(src)
-    name = File.basename(src, '.h')
+  def generate_mock(src, folder)
+    name = File.basename(src, '.*')
+    ext = File.extname(src)
     puts "Creating mock for #{name}..." unless @silent
-    @cm_generator.create_mock(name, @cm_parser.parse(name, File.read(src)))
+    @cm_generator.create_mock(name, @cm_parser.parse(name, File.read(src)), ext, folder)
+  end
+
+  def generate_skeleton(src)
+    name = File.basename(src, '.*')
+    puts "Creating skeleton for #{name}..." unless @silent
+    @cm_generator.create_skeleton(name, @cm_parser.parse(name, File.read(src)))
   end
 end
 
 def option_maker(options, key, val)
-  options = options || {}
+  options ||= {}
   options[key.to_sym] =
-    if val.chr == ":"
+    if val.chr == ':'
       val[1..-1].to_sym
-    elsif val.include? ";"
+    elsif val.include? ';'
       val.split(';')
     elsif val == 'true'
       true
@@ -60,12 +74,12 @@ def option_maker(options, key, val)
   options
 end
 
-  # Command Line Support ###############################
+# Command Line Support ###############################
 
-if ($0 == __FILE__)
+if $0 == __FILE__
   usage = "usage: ruby #{__FILE__} (-oOptionsFile) File(s)ToMock"
 
-  if (!ARGV[0])
+  unless ARGV[0]
     puts usage
     exit 1
   end
@@ -73,14 +87,25 @@ if ($0 == __FILE__)
   options = {}
   filelist = []
   ARGV.each do |arg|
-    if (arg =~ /^-o\"?([a-zA-Z0-9._\\\/:\s]+)\"?/)
-      options.merge! CMockConfig.load_config_file_from_yaml( arg.gsub(/^-o/,'') )
-    elsif (arg =~ /^--([a-zA-Z0-9._\\\/:\s]+)=\"?([a-zA-Z0-9._\-\\\/:\s\;]+)\"?/)
-      options = option_maker(options, $1, $2)
+    if arg =~ /^-o\"?([a-zA-Z0-9@._\\\/:\s]+)\"?/
+      options.merge! CMockConfig.load_config_file_from_yaml(arg.gsub(/^-o/, ''))
+    elsif arg == '--skeleton'
+      options[:skeleton] = true
+    elsif arg =~ /^--strippables=\"?(.*)\"?/
+      # --strippables are dealt with separately since the user is allowed to
+      # enter any valid regular expression as argument
+      options = option_maker(options, 'strippables', Regexp.last_match(1))
+    elsif arg =~ /^--([a-zA-Z0-9._\\\/:\s]+)=\"?([a-zA-Z0-9._\-\\\/:\s\;]*)\"?/x
+      options = option_maker(options, Regexp.last_match(1),
+                             Regexp.last_match(2))
     else
       filelist << arg
     end
   end
 
-  CMock.new(options).setup_mocks(filelist)
+  if options[:skeleton]
+    CMock.new(options).setup_skeletons(filelist)
+  else
+    CMock.new(options).setup_mocks(filelist)
+  end
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_config.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_config.rb
index b21b61ed2..716a0c55e 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_config.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_config.rb
@@ -5,99 +5,120 @@
 # ==========================================
 
 class CMockConfig
+  CMOCK_DEFAULT_OPTIONS =
+    {
+      :framework                   => :unity,
+      :mock_path                   => 'mocks',
+      :mock_prefix                 => 'Mock',
+      :mock_suffix                 => '',
+      :skeleton_path               => '',
+      :weak                        => '',
+      :subdir                      => nil,
+      :plugins                     => [],
+      :strippables                 => ['(?:__attribute__\s*\(+.*?\)+)'],
+      :attributes                  => %w[__ramfunc __irq __fiq register extern],
+      :c_calling_conventions       => %w[__stdcall __cdecl __fastcall],
+      :enforce_strict_ordering     => false,
+      :fail_on_unexpected_calls    => true,
+      :unity_helper_path           => false,
+      :treat_as                    => {},
+      :treat_as_array              => {},
+      :treat_as_void               => [],
+      :memcmp_if_unknown           => true,
+      :when_no_prototypes          => :warn,           # the options being :ignore, :warn, or :error
+      :when_ptr                    => :compare_data,   # the options being :compare_ptr, :compare_data, or :smart
+      :verbosity                   => 2,               # the options being 0 errors only, 1 warnings and errors, 2 normal info, 3 verbose
+      :treat_externs               => :exclude,        # the options being :include or :exclude
+      :treat_inlines               => :exclude,        # the options being :include or :exclude
+      :callback_include_count      => true,
+      :callback_after_arg_check    => false,
+      :includes                    => nil,
+      :includes_h_pre_orig_header  => nil,
+      :includes_h_post_orig_header => nil,
+      :includes_c_pre_header       => nil,
+      :includes_c_post_header      => nil,
+      :orig_header_include_fmt     => '#include "%s"',
+      :array_size_type             => [],
+      :array_size_name             => 'size|len',
+      :skeleton                    => false,
+      :exclude_setjmp_h            => false,
 
-  CMockDefaultOptions =
-  {
-    :framework                   => :unity,
-    :mock_path                   => 'mocks',
-    :mock_prefix                 => 'Mock',
-    :mock_suffix                 => '',
-    :weak                        => '',
-    :subdir                      => nil,
-    :plugins                     => [],
-    :strippables                 => ['(?:__attribute__\s*\(+.*?\)+)'],
-    :attributes                  => ['__ramfunc', '__irq', '__fiq', 'register', 'extern'],
-    :c_calling_conventions       => ['__stdcall', '__cdecl', '__fastcall'],
-    :enforce_strict_ordering     => false,
-    :fail_on_unexpected_calls    => true,
-    :unity_helper_path           => false,
-    :treat_as                    => {},
-    :treat_as_array              => {},
-    :treat_as_void               => [],
-    :memcmp_if_unknown           => true,
-    :when_no_prototypes          => :warn,           #the options being :ignore, :warn, or :error
-    :when_ptr                    => :compare_data,   #the options being :compare_ptr, :compare_data, or :smart
-    :verbosity                   => 2,               #the options being 0 errors only, 1 warnings and errors, 2 normal info, 3 verbose
-    :treat_externs               => :exclude,        #the options being :include or :exclude
-    :callback_include_count      => true,
-    :callback_after_arg_check    => false,
-    :includes                    => nil,
-    :includes_h_pre_orig_header  => nil,
-    :includes_h_post_orig_header => nil,
-    :includes_c_pre_header       => nil,
-    :includes_c_post_header      => nil,
-    :orig_header_include_fmt     => "#include \"%s\"",
-    :array_size_type             => [],
-    :array_size_name             => 'size|len',
-  }
+      # Format to look for inline functions.
+      # This is a combination of "static" and "inline" keywords ("static inline", "inline static", "inline", "static")
+      # There are several possibilities:
+      # - sometimes they appear together, sometimes individually,
+      # - The keywords can appear before or after the return type (this is a compiler warning but people do weird stuff),
+      #   so we check for word boundaries when searching for them
+      # - We first remove "static inline" combinations and boil down to single inline or static statements
+      :inline_function_patterns    => ['(static\s+inline|inline\s+static)\s*', '(\bstatic\b|\binline\b)\s*'] # Last part (\s*) is just to remove whitespaces (only to prettify the output)
+    }.freeze
 
-  def initialize(options=nil)
-    case(options)
-      when NilClass then options = CMockDefaultOptions.clone
-      when String   then options = CMockDefaultOptions.clone.merge(load_config_file_from_yaml(options))
-      when Hash     then options = CMockDefaultOptions.clone.merge(options)
-      else          raise "If you specify arguments, it should be a filename or a hash of options"
+  def initialize(options = nil)
+    case options
+    when NilClass then options = CMOCK_DEFAULT_OPTIONS.dup
+    when String   then options = CMOCK_DEFAULT_OPTIONS.dup.merge(load_config_file_from_yaml(options))
+    when Hash     then options = CMOCK_DEFAULT_OPTIONS.dup.merge(options)
+    else raise 'If you specify arguments, it should be a filename or a hash of options'
     end
 
-    #do some quick type verification
-    [:plugins, :attributes, :treat_as_void].each do |opt|
-      unless (options[opt].class == Array)
+    # do some quick type verification
+    %i[plugins attributes treat_as_void].each do |opt|
+      unless options[opt].class == Array
         options[opt] = []
-        puts "WARNING: :#{opt.to_s} should be an array." unless (options[:verbosity] < 1)
+        puts "WARNING: :#{opt} should be an array." unless options[:verbosity] < 1
       end
     end
-    [:includes, :includes_h_pre_orig_header, :includes_h_post_orig_header, :includes_c_pre_header, :includes_c_post_header].each do |opt|
-      unless (options[opt].nil? or (options[opt].class == Array))
+    %i[includes includes_h_pre_orig_header includes_h_post_orig_header includes_c_pre_header includes_c_post_header].each do |opt|
+      unless options[opt].nil? || (options[opt].class == Array)
         options[opt] = []
-        puts "WARNING: :#{opt.to_s} should be an array." unless (options[:verbosity] < 1)
+        puts "WARNING: :#{opt} should be an array." unless options[:verbosity] < 1
       end
     end
     options[:unity_helper_path] ||= options[:unity_helper]
     options[:unity_helper_path] = [options[:unity_helper_path]] if options[:unity_helper_path].is_a? String
-    options[:includes_c_post_header] = ((options[:includes_c_post_header] || []) + (options[:unity_helper_path] || [])).uniq
+
+    if options[:unity_helper_path]
+      require 'pathname'
+      includes1 = options[:includes_c_post_header] || []
+      includes2 = options[:unity_helper_path].map do |path|
+        Pathname(path).relative_path_from(Pathname(options[:mock_path])).to_s
+      end
+      options[:includes_c_post_header] = (includes1 + includes2).uniq
+    end
+
     options[:plugins].compact!
-    options[:plugins].map! {|p| p.to_sym}
+    options[:plugins].map!(&:to_sym)
     @options = options
 
-    treat_as_map = standard_treat_as_map()#.clone
+    treat_as_map = standard_treat_as_map # .clone
     treat_as_map.merge!(@options[:treat_as])
     @options[:treat_as] = treat_as_map
 
     @options.each_key do |key|
       unless methods.include?(key)
-        eval("def #{key.to_s}() return @options[:#{key.to_s}] end")
+        eval("def #{key}() return @options[:#{key}] end")
       end
     end
   end
 
-  def load_config_file_from_yaml yaml_filename
+  def load_config_file_from_yaml(yaml_filename)
     self.class.load_config_file_from_yaml yaml_filename
   end
 
-  def self.load_config_file_from_yaml yaml_filename
+  def self.load_config_file_from_yaml(yaml_filename)
     require 'yaml'
     require 'fileutils'
     YAML.load_file(yaml_filename)[:cmock]
   end
 
-  def set_path(path)
-    @src_path = path
+  def path(new_path)
+    @src_path = new_path
   end
 
   def load_unity_helper
-    return nil unless (@options[:unity_helper_path])
+    return nil unless @options[:unity_helper_path]
 
-    return @options[:unity_helper_path].inject("") do |unity_helper, filename|
+    @options[:unity_helper_path].inject('') do |unity_helper, filename|
       unity_helper + "\n" + File.new(filename).read
     end
   end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_file_writer.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_file_writer.rb
index d2d954cbc..f30c44b24 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_file_writer.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_file_writer.rb
@@ -5,7 +5,6 @@
 # ==========================================
 
 class CMockFileWriter
-
   attr_reader :config
 
   def initialize(config)
@@ -13,32 +12,36 @@ class CMockFileWriter
   end
 
   def create_subdir(subdir)
-    if !Dir.exists?("#{@config.mock_path}/")
-      require 'fileutils'
-      FileUtils.mkdir_p "#{@config.mock_path}/"
-    end
-    if subdir && !Dir.exists?("#{@config.mock_path}/#{subdir+'/' if subdir}")
-      require 'fileutils'
-      FileUtils.mkdir_p "#{@config.mock_path}/#{subdir+'/' if subdir}"
-    end
+    require 'fileutils'
+    FileUtils.mkdir_p "#{@config.mock_path}/" unless Dir.exist?("#{@config.mock_path}/")
+    FileUtils.mkdir_p "#{@config.mock_path}/#{subdir + '/' if subdir}" if subdir && !Dir.exist?("#{@config.mock_path}/#{subdir + '/' if subdir}")
   end
 
   def create_file(filename, subdir)
     raise "Where's the block of data to create?" unless block_given?
-    full_file_name_temp = "#{@config.mock_path}/#{subdir+'/' if subdir}#{filename}.new"
-    full_file_name_done = "#{@config.mock_path}/#{subdir+'/' if subdir}#{filename}"
+
+    full_file_name_temp = "#{@config.mock_path}/#{subdir + '/' if subdir}#{filename}.new"
+    full_file_name_done = "#{@config.mock_path}/#{subdir + '/' if subdir}#{filename}"
     File.open(full_file_name_temp, 'w') do |file|
       yield(file, filename)
     end
     update_file(full_file_name_done, full_file_name_temp)
   end
 
+  def append_file(filename, subdir)
+    raise "Where's the block of data to create?" unless block_given?
+
+    full_file_name = "#{@config.skeleton_path}/#{subdir + '/' if subdir}#{filename}"
+    File.open(full_file_name, 'a') do |file|
+      yield(file, filename)
+    end
+  end
+
   private ###################################
 
   def update_file(dest, src)
     require 'fileutils'
-    FileUtils.rm(dest) if (File.exist?(dest))
-    FileUtils.cp(src, dest)
-    FileUtils.rm(src)
+    FileUtils.rm(dest, :force => true)
+    FileUtils.mv(src, dest)
   end
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator.rb
index 42725a60d..6ed51109f 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator.rb
@@ -5,8 +5,7 @@
 # ==========================================
 
 class CMockGenerator
-
-  attr_accessor :config, :file_writer, :module_name, :clean_mock_name, :mock_name, :utils, :plugins, :weak, :ordered
+  attr_accessor :config, :file_writer, :module_name, :module_ext, :clean_mock_name, :mock_name, :utils, :plugins, :weak, :ordered
 
   def initialize(config, file_writer, utils, plugins)
     @file_writer = file_writer
@@ -16,89 +15,147 @@ class CMockGenerator
     @prefix      = @config.mock_prefix
     @suffix      = @config.mock_suffix
     @weak        = @config.weak
-    @ordered     = @config.enforce_strict_ordering
-    @framework   = @config.framework.to_s
+    @include_inline = @config.treat_inlines
+    @ordered = @config.enforce_strict_ordering
+    @framework = @config.framework.to_s
     @fail_on_unexpected_calls = @config.fail_on_unexpected_calls
+    @exclude_setjmp_h = @config.exclude_setjmp_h
+    @subdir = @config.subdir
 
-    @subdir      = @config.subdir
-
-    @includes_h_pre_orig_header  = (@config.includes || @config.includes_h_pre_orig_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-    @includes_h_post_orig_header = (@config.includes_h_post_orig_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-    @includes_c_pre_header       = (@config.includes_c_pre_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
-    @includes_c_post_header      = (@config.includes_c_post_header || []).map{|h| h =~ /</ ? h : "\"#{h}\""}
+    @includes_h_pre_orig_header  = (@config.includes || @config.includes_h_pre_orig_header || []).map { |h| h =~ /</ ? h : "\"#{h}\"" }
+    @includes_h_post_orig_header = (@config.includes_h_post_orig_header || []).map { |h| h =~ /</ ? h : "\"#{h}\"" }
+    @includes_c_pre_header       = (@config.includes_c_pre_header || []).map { |h| h =~ /</ ? h : "\"#{h}\"" }
+    @includes_c_post_header      = (@config.includes_c_post_header || []).map { |h| h =~ /</ ? h : "\"#{h}\"" }
 
     here = File.dirname __FILE__
     unity_path_in_ceedling = "#{here}/../../unity" # path to Unity from within Ceedling
     unity_path_in_cmock = "#{here}/../vendor/unity" # path to Unity from within CMock
     # path to Unity as specified by env var
-    unity_path_in_env = ENV.has_key?("UNITY_DIR") ? File.expand_path(ENV.fetch("UNITY_DIR")) : nil
+    unity_path_in_env = ENV.key?('UNITY_DIR') ? File.expand_path(ENV.fetch('UNITY_DIR')) : nil
 
-    if unity_path_in_env and File.exist? unity_path_in_env
+    if unity_path_in_env && File.exist?(unity_path_in_env)
       require "#{unity_path_in_env}/auto/type_sanitizer"
     elsif File.exist? unity_path_in_ceedling
       require "#{unity_path_in_ceedling}/auto/type_sanitizer"
     elsif File.exist? unity_path_in_cmock
       require "#{unity_path_in_cmock}/auto/type_sanitizer"
     else
-      raise "Failed to find an instance of Unity to pull in type_sanitizer module!"
+      raise 'Failed to find an instance of Unity to pull in type_sanitizer module!'
     end
-
   end
 
-  def create_mock(module_name, parsed_stuff)
-    @module_name = module_name
-    @mock_name   = @prefix + @module_name + @suffix
-    @clean_mock_name = TypeSanitizer.sanitize_c_identifier(@mock_name)
-    create_mock_subdir()
-    create_mock_header_file(parsed_stuff)
-    create_mock_source_file(parsed_stuff)
+  def create_mock(module_name, parsed_stuff, module_ext = nil, folder = nil)
+    # determine the name for our new mock
+    mock_name = @prefix + module_name + @suffix
+
+    # determine the folder our mock will reside
+    mock_folder = if folder && @subdir
+                    File.join(@subdir, folder)
+                  elsif @subdir
+                    @subdir
+                  else
+                    folder
+                  end
+
+    # adds a trailing slash to the folder output
+    mock_folder = File.join(mock_folder, '') if mock_folder
+
+    # create out mock project from incoming data
+    mock_project = {
+      :module_name  => module_name,
+      :module_ext   => (module_ext || '.h'),
+      :mock_name    => mock_name,
+      :clean_name   => TypeSanitizer.sanitize_c_identifier(mock_name),
+      :folder       => mock_folder,
+      :parsed_stuff => parsed_stuff,
+      :skeleton     => false
+    }
+
+    create_mock_subdir(mock_project)
+    create_mock_header_file(mock_project)
+    create_mock_source_file(mock_project)
+  end
+
+  def create_skeleton(module_name, parsed_stuff)
+    mock_project = {
+      :module_name  => module_name,
+      :module_ext   => '.h',
+      :parsed_stuff => parsed_stuff,
+      :skeleton     => true
+    }
+
+    create_skeleton_source_file(mock_project)
   end
 
   private if $ThisIsOnlyATest.nil? ##############################
 
-  def create_mock_subdir()
-    @file_writer.create_subdir(@subdir)
+  def create_mock_subdir(mock_project)
+    @file_writer.create_subdir(mock_project[:folder])
   end
 
-  def create_mock_header_file(parsed_stuff)
-    @file_writer.create_file(@mock_name + ".h", @subdir) do |file, filename|
-      create_mock_header_header(file, filename)
-      create_mock_header_service_call_declarations(file)
-      create_typedefs(file, parsed_stuff[:typedefs])
-      parsed_stuff[:functions].each do |function|
+  def create_using_statement(file, function)
+    file << "using namespace #{function[:namespace].join('::')};\n" unless function[:namespace].empty?
+  end
+
+  def create_mock_header_file(mock_project)
+    if @include_inline == :include
+      @file_writer.create_file(mock_project[:module_name] + (mock_project[:module_ext]), mock_project[:folder]) do |file, _filename|
+        file << mock_project[:parsed_stuff][:normalized_source]
+      end
+    end
+
+    @file_writer.create_file(mock_project[:mock_name] + mock_project[:module_ext], mock_project[:folder]) do |file, filename|
+      create_mock_header_header(file, filename, mock_project)
+      create_mock_header_service_call_declarations(file, mock_project)
+      create_typedefs(file, mock_project)
+      mock_project[:parsed_stuff][:functions].each do |function|
+        create_using_statement(file, function)
         file << @plugins.run(:mock_function_declarations, function)
       end
       create_mock_header_footer(file)
     end
   end
 
-  def create_mock_source_file(parsed_stuff)
-    @file_writer.create_file(@mock_name + ".c", @subdir) do |file, filename|
-      create_source_header_section(file, filename, parsed_stuff[:functions])
-      create_instance_structure(file, parsed_stuff[:functions])
+  def create_mock_source_file(mock_project)
+    @file_writer.create_file(mock_project[:mock_name] + '.c', mock_project[:folder]) do |file, filename|
+      create_source_header_section(file, filename, mock_project)
+      create_instance_structure(file, mock_project)
       create_extern_declarations(file)
-      create_mock_verify_function(file, parsed_stuff[:functions])
-      create_mock_init_function(file)
-      create_mock_destroy_function(file, parsed_stuff[:functions])
-      parsed_stuff[:functions].each do |function|
+      create_mock_verify_function(file, mock_project)
+      create_mock_init_function(file, mock_project)
+      create_mock_destroy_function(file, mock_project)
+      mock_project[:parsed_stuff][:functions].each do |function|
         create_mock_implementation(file, function)
         create_mock_interfaces(file, function)
       end
     end
   end
 
-  def create_mock_header_header(file, filename)
-    define_name   = @clean_mock_name.upcase
-    orig_filename = (@subdir ? @subdir + "/" : "") + @module_name + ".h"
+  def create_skeleton_source_file(mock_project)
+    filename = "#{@config.mock_path}/#{@subdir + '/' if @subdir}#{mock_project[:module_name]}.c"
+    existing = File.exist?(filename) ? File.read(filename) : ''
+    @file_writer.append_file(mock_project[:module_name] + '.c', @subdir) do |file, fullname|
+      blank_project = mock_project.clone
+      blank_project[:parsed_stuff] = { :functions => [] }
+      create_source_header_section(file, fullname, blank_project) if existing.empty?
+      mock_project[:parsed_stuff][:functions].each do |function|
+        create_function_skeleton(file, function, existing)
+      end
+    end
+  end
+
+  def create_mock_header_header(file, _filename, mock_project)
+    define_name = mock_project[:clean_name].upcase
+    orig_filename = (mock_project[:folder] || '') + mock_project[:module_name] + mock_project[:module_ext]
     file << "/* AUTOGENERATED FILE. DO NOT EDIT. */\n"
     file << "#ifndef _#{define_name}_H\n"
     file << "#define _#{define_name}_H\n\n"
     file << "#include \"#{@framework}.h\"\n"
-    @includes_h_pre_orig_header.each {|inc| file << "#include #{inc}\n"}
-    file << @config.orig_header_include_fmt.gsub(/%s/, "#{orig_filename}") + "\n"
-    @includes_h_post_orig_header.each {|inc| file << "#include #{inc}\n"}
+    @includes_h_pre_orig_header.each { |inc| file << "#include #{inc}\n" }
+    file << @config.orig_header_include_fmt.gsub(/%s/, orig_filename.to_s) + "\n"
+    @includes_h_post_orig_header.each { |inc| file << "#include #{inc}\n" }
     plugin_includes = @plugins.run(:include_files)
-    file << plugin_includes if (!plugin_includes.empty?)
+    file << plugin_includes unless plugin_includes.empty?
     file << "\n"
     file << "/* Ignore the following warnings, since we are copying code */\n"
     file << "#if defined(__GNUC__) && !defined(__ICC) && !defined(__TMS470__)\n"
@@ -114,16 +171,16 @@ class CMockGenerator
     file << "\n"
   end
 
-  def create_typedefs(file, typedefs)
+  def create_typedefs(file, mock_project)
     file << "\n"
-    typedefs.each {|typedef| file << "#{typedef}\n" }
+    mock_project[:parsed_stuff][:typedefs].each { |typedef| file << "#{typedef}\n" }
     file << "\n\n"
   end
 
-  def create_mock_header_service_call_declarations(file)
-    file << "void #{@clean_mock_name}_Init(void);\n"
-    file << "void #{@clean_mock_name}_Destroy(void);\n"
-    file << "void #{@clean_mock_name}_Verify(void);\n\n"
+  def create_mock_header_service_call_declarations(file, mock_project)
+    file << "void #{mock_project[:clean_name]}_Init(void);\n"
+    file << "void #{mock_project[:clean_name]}_Destroy(void);\n"
+    file << "void #{mock_project[:clean_name]}_Verify(void);\n\n"
   end
 
   def create_mock_header_footer(header)
@@ -137,21 +194,23 @@ class CMockGenerator
     header << "#endif\n"
   end
 
-  def create_source_header_section(file, filename, functions)
-    header_file = (@subdir ? @subdir + '/' : '') + filename.gsub(".c",".h")
-    file << "/* AUTOGENERATED FILE. DO NOT EDIT. */\n"
+  def create_source_header_section(file, filename, mock_project)
+    header_file = (mock_project[:folder] || '') + filename.gsub('.c', mock_project[:module_ext])
+    file << "/* AUTOGENERATED FILE. DO NOT EDIT. */\n" unless mock_project[:parsed_stuff][:functions].empty?
     file << "#include <string.h>\n"
     file << "#include <stdlib.h>\n"
-    file << "#include <setjmp.h>\n"
+    unless @exclude_setjmp_h
+      file << "#include <setjmp.h>\n"
+    end
     file << "#include \"cmock.h\"\n"
-    @includes_c_pre_header.each {|inc| file << "#include #{inc}\n"}
+    @includes_c_pre_header.each { |inc| file << "#include #{inc}\n" }
     file << "#include \"#{header_file}\"\n"
-    @includes_c_post_header.each {|inc| file << "#include #{inc}\n"}
+    @includes_c_post_header.each { |inc| file << "#include #{inc}\n" }
     file << "\n"
     strs = []
-    functions.each do |func|
+    mock_project[:parsed_stuff][:functions].each do |func|
       strs << func[:name]
-      func[:args].each {|arg| strs << arg[:name] }
+      func[:args].each { |arg| strs << arg[:name] }
     end
     strs.uniq.sort.each do |str|
       file << "static const char* CMockString_#{str} = \"#{str}\";\n"
@@ -159,15 +218,16 @@ class CMockGenerator
     file << "\n"
   end
 
-  def create_instance_structure(file, functions)
+  def create_instance_structure(file, mock_project)
+    functions = mock_project[:parsed_stuff][:functions]
     functions.each do |function|
       file << "typedef struct _CMOCK_#{function[:name]}_CALL_INSTANCE\n{\n"
       file << "  UNITY_LINE_TYPE LineNumber;\n"
       file << @plugins.run(:instance_typedefs, function)
       file << "\n} CMOCK_#{function[:name]}_CALL_INSTANCE;\n\n"
     end
-    file << "static struct #{@clean_mock_name}Instance\n{\n"
-    if (functions.size == 0)
+    file << "static struct #{mock_project[:clean_name]}Instance\n{\n"
+    if functions.empty?
       file << "  unsigned char placeHolder;\n"
     end
     functions.each do |function|
@@ -178,17 +238,19 @@ class CMockGenerator
   end
 
   def create_extern_declarations(file)
-    file << "extern jmp_buf AbortFrame;\n"
-    if (@ordered)
+    unless @exclude_setjmp_h
+      file << "extern jmp_buf AbortFrame;\n"
+    end
+    if @ordered
       file << "extern int GlobalExpectCount;\n"
       file << "extern int GlobalVerifyOrder;\n"
     end
     file << "\n"
   end
 
-  def create_mock_verify_function(file, functions)
-    file << "void #{@clean_mock_name}_Verify(void)\n{\n"
-    verifications = functions.collect do |function|
+  def create_mock_verify_function(file, mock_project)
+    file << "void #{mock_project[:clean_name]}_Verify(void)\n{\n"
+    verifications = mock_project[:parsed_stuff][:functions].collect do |function|
       v = @plugins.run(:mock_verify, function)
       v.empty? ? v : ["  call_instance = Mock.#{function[:name]}_CallInstance;\n", v]
     end.join
@@ -200,23 +262,23 @@ class CMockGenerator
     file << "}\n\n"
   end
 
-  def create_mock_init_function(file)
-    file << "void #{@clean_mock_name}_Init(void)\n{\n"
-    file << "  #{@clean_mock_name}_Destroy();\n"
+  def create_mock_init_function(file, mock_project)
+    file << "void #{mock_project[:clean_name]}_Init(void)\n{\n"
+    file << "  #{mock_project[:clean_name]}_Destroy();\n"
     file << "}\n\n"
   end
 
-  def create_mock_destroy_function(file, functions)
-    file << "void #{@clean_mock_name}_Destroy(void)\n{\n"
+  def create_mock_destroy_function(file, mock_project)
+    file << "void #{mock_project[:clean_name]}_Destroy(void)\n{\n"
     file << "  CMock_Guts_MemFreeAll();\n"
     file << "  memset(&Mock, 0, sizeof(Mock));\n"
-    file << functions.collect {|function| @plugins.run(:mock_destroy, function)}.join
+    file << mock_project[:parsed_stuff][:functions].collect { |function| @plugins.run(:mock_destroy, function) }.join
 
-    unless (@fail_on_unexpected_calls)
-      file << functions.collect {|function| @plugins.run(:mock_ignore, function)}.join
+    unless @fail_on_unexpected_calls
+      file << mock_project[:parsed_stuff][:functions].collect { |function| @plugins.run(:mock_ignore, function) }.join
     end
 
-    if (@ordered)
+    if @ordered
       file << "  GlobalExpectCount = 0;\n"
       file << "  GlobalVerifyOrder = 0;\n"
     end
@@ -229,17 +291,28 @@ class CMockGenerator
                                (function[:return][:type]) +
                                (function[:c_calling_convention] ? " #{function[:c_calling_convention]}" : '')
     args_string = function[:args_string]
-    args_string += (", " + function[:var_arg]) unless (function[:var_arg].nil?)
+    args_string += (', ' + function[:var_arg]) unless function[:var_arg].nil?
+
+    # Encapsulate in namespace(s) if applicable
+    function[:namespace].each do |ns|
+      file << "namespace #{ns} {\n"
+    end
+
+    # Determine class prefix (if any)
+    cls_pre = ''
+    unless function[:class].nil?
+      cls_pre = "#{function[:class]}::"
+    end
 
     # Create mock function
-    if (not @weak.empty?)
-        file << "#if defined (__IAR_SYSTEMS_ICC__)\n"
-        file << "#pragma weak #{function[:name]}\n"
-        file << "#else\n"
-        file << "#{function_mod_and_rettype} #{function[:name]}(#{args_string}) #{weak};\n"
-        file << "#endif\n\n"
+    unless @weak.empty?
+      file << "#if defined (__IAR_SYSTEMS_ICC__)\n"
+      file << "#pragma weak #{function[:unscoped_name]}\n"
+      file << "#else\n"
+      file << "#{function_mod_and_rettype} #{function[:unscoped_name]}(#{args_string}) #{weak};\n"
+      file << "#endif\n\n"
     end
-    file << "#{function_mod_and_rettype} #{function[:name]}(#{args_string})\n"
+    file << "#{function_mod_and_rettype} #{cls_pre}#{function[:unscoped_name]}(#{args_string})\n"
     file << "{\n"
     file << "  UNITY_LINE_TYPE cmock_line = TEST_LINE_NUM;\n"
     file << "  CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance;\n"
@@ -249,7 +322,7 @@ class CMockGenerator
     file << @plugins.run(:mock_implementation_precheck, function)
     file << "  UNITY_TEST_ASSERT_NOT_NULL(cmock_call_instance, cmock_line, CMockStringCalledMore);\n"
     file << "  cmock_line = cmock_call_instance->LineNumber;\n"
-    if (@ordered)
+    if @ordered
       file << "  if (cmock_call_instance->CallOrder > ++GlobalVerifyOrder)\n"
       file << "    UNITY_TEST_FAIL(cmock_line, CMockStringCalledEarly);\n"
       file << "  if (cmock_call_instance->CallOrder < GlobalVerifyOrder)\n"
@@ -257,12 +330,39 @@ class CMockGenerator
     end
     file << @plugins.run(:mock_implementation, function)
     file << "  UNITY_CLR_DETAILS();\n"
-    file << "  return cmock_call_instance->ReturnVal;\n" unless (function[:return][:void?])
-    file << "}\n\n"
+    file << "  return cmock_call_instance->ReturnVal;\n" unless function[:return][:void?]
+    file << "}\n"
+
+    # Close any namespace(s) opened above
+    function[:namespace].each do
+      file << "}\n"
+    end
+
+    file << "\n"
   end
 
   def create_mock_interfaces(file, function)
     file << @utils.code_add_argument_loader(function)
     file << @plugins.run(:mock_interfaces, function)
   end
+
+  def create_function_skeleton(file, function, existing)
+    # prepare return value and arguments
+    function_mod_and_rettype = (function[:modifier].empty? ? '' : "#{function[:modifier]} ") +
+                               (function[:return][:type]) +
+                               (function[:c_calling_convention] ? " #{function[:c_calling_convention]}" : '')
+    args_string = function[:args_string]
+    args_string += (', ' + function[:var_arg]) unless function[:var_arg].nil?
+
+    decl = "#{function_mod_and_rettype} #{function[:name]}(#{args_string})"
+
+    return if existing.include?(decl)
+
+    file << "#{decl}\n"
+    file << "{\n"
+    file << "  /*TODO: Implement Me!*/\n"
+    function[:args].each { |arg| file << "  (void)#{arg[:name]};\n" }
+    file << "  return (#{(function[:return][:type])})0;\n" unless function[:return][:void?]
+    file << "}\n\n"
+  end
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_array.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_array.rb
index 3b73708e7..a9864ab74 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_array.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_array.rb
@@ -5,7 +5,6 @@
 # ==========================================
 
 class CMockGeneratorPluginArray
-
   attr_reader :priority
   attr_accessor :config, :utils, :unity_helper, :ordered
   def initialize(config, utils)
@@ -18,46 +17,47 @@ class CMockGeneratorPluginArray
   end
 
   def instance_typedefs(function)
-    function[:args].inject("") do |all, arg|
-      (arg[:ptr?]) ? all + "  int Expected_#{arg[:name]}_Depth;\n" : all
+    function[:args].inject('') do |all, arg|
+      arg[:ptr?] ? all + "  int Expected_#{arg[:name]}_Depth;\n" : all
     end
   end
 
   def mock_function_declarations(function)
     return nil unless function[:contains_ptr?]
-    args_call   = function[:args].map{|m| m[:ptr?] ? "#{m[:name]}, #{m[:name]}_Depth" : "#{m[:name]}"}.join(', ')
+
+    args_call   = function[:args].map { |m| m[:ptr?] ? "#{m[:name]}, #{m[:name]}_Depth" : (m[:name]).to_s }.join(', ')
     args_string = function[:args].map do |m|
       type = @utils.arg_type_with_const(m)
       m[:ptr?] ? "#{type} #{m[:name]}, int #{m[:name]}_Depth" : "#{type} #{m[:name]}"
     end.join(', ')
-    if (function[:return][:void?])
-      return "#define #{function[:name]}_ExpectWithArray(#{args_call}) #{function[:name]}_CMockExpectWithArray(__LINE__, #{args_call})\n" +
+    if function[:return][:void?]
+      return "#define #{function[:name]}_ExpectWithArray(#{args_call}) #{function[:name]}_CMockExpectWithArray(__LINE__, #{args_call})\n" \
              "void #{function[:name]}_CMockExpectWithArray(UNITY_LINE_TYPE cmock_line, #{args_string});\n"
     else
-      return "#define #{function[:name]}_ExpectWithArrayAndReturn(#{args_call}, cmock_retval) #{function[:name]}_CMockExpectWithArrayAndReturn(__LINE__, #{args_call}, cmock_retval)\n" +
+      return "#define #{function[:name]}_ExpectWithArrayAndReturn(#{args_call}, cmock_retval) #{function[:name]}_CMockExpectWithArrayAndReturn(__LINE__, #{args_call}, cmock_retval)\n" \
              "void #{function[:name]}_CMockExpectWithArrayAndReturn(UNITY_LINE_TYPE cmock_line, #{args_string}, #{function[:return][:str]});\n"
     end
   end
 
   def mock_interfaces(function)
     return nil unless function[:contains_ptr?]
+
     lines = []
     func_name = function[:name]
     args_string = function[:args].map do |m|
       type = @utils.arg_type_with_const(m)
       m[:ptr?] ? "#{type} #{m[:name]}, int #{m[:name]}_Depth" : "#{type} #{m[:name]}"
     end.join(', ')
-    call_string = function[:args].map{|m| m[:ptr?] ? "#{m[:name]}, #{m[:name]}_Depth" : m[:name]}.join(', ')
-    if (function[:return][:void?])
-      lines << "void #{func_name}_CMockExpectWithArray(UNITY_LINE_TYPE cmock_line, #{args_string})\n"
-    else
-      lines << "void #{func_name}_CMockExpectWithArrayAndReturn(UNITY_LINE_TYPE cmock_line, #{args_string}, #{function[:return][:str]})\n"
-    end
+    call_string = function[:args].map { |m| m[:ptr?] ? "#{m[:name]}, #{m[:name]}_Depth" : m[:name] }.join(', ')
+    lines << if function[:return][:void?]
+               "void #{func_name}_CMockExpectWithArray(UNITY_LINE_TYPE cmock_line, #{args_string})\n"
+             else
+               "void #{func_name}_CMockExpectWithArrayAndReturn(UNITY_LINE_TYPE cmock_line, #{args_string}, #{function[:return][:str]})\n"
+             end
     lines << "{\n"
     lines << @utils.code_add_base_expectation(func_name)
     lines << "  CMockExpectParameters_#{func_name}(cmock_call_instance, #{call_string});\n"
-    lines << "  cmock_call_instance->ReturnVal = cmock_to_return;\n" unless (function[:return][:void?])
+    lines << "  cmock_call_instance->ReturnVal = cmock_to_return;\n" unless function[:return][:void?]
     lines << "}\n\n"
   end
-
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_callback.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_callback.rb
index 564e0ac2b..6ba8e9bd9 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_callback.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_callback.rb
@@ -5,7 +5,6 @@
 # ==========================================
 
 class CMockGeneratorPluginCallback
-
   attr_accessor :include_count
   attr_reader :priority
   attr_reader :config, :utils
@@ -20,7 +19,7 @@ class CMockGeneratorPluginCallback
 
   def instance_structure(function)
     func_name = function[:name]
-    "  int #{func_name}_CallbackBool;\n" \
+    "  char #{func_name}_CallbackBool;\n" \
     "  CMOCK_#{func_name}_CALLBACK #{func_name}_CallbackFunctionPointer;\n" \
     "  int #{func_name}_CallbackCalls;\n"
   end
@@ -30,7 +29,7 @@ class CMockGeneratorPluginCallback
     return_type = function[:return][:type]
     action = @config.callback_after_arg_check ? 'AddCallback' : 'Stub'
     style  = (@include_count ? 1 : 0) | (function[:args].empty? ? 0 : 2)
-    styles = [ "void", "int cmock_num_calls", function[:args_string], "#{function[:args_string]}, int cmock_num_calls" ]
+    styles = ['void', 'int cmock_num_calls', function[:args_string], "#{function[:args_string]}, int cmock_num_calls"]
     "typedef #{return_type} (* CMOCK_#{func_name}_CALLBACK)(#{styles[style]});\n" \
     "void #{func_name}_AddCallback(CMOCK_#{func_name}_CALLBACK Callback);\n" \
     "void #{func_name}_Stub(CMOCK_#{func_name}_CALLBACK Callback);\n" \
@@ -60,29 +59,30 @@ class CMockGeneratorPluginCallback
         "    UNITY_CLR_DETAILS();\n" \
         "    return;\n  }\n"
       else
-        "    #{function[:return][:type]} ret = #{generate_call(function)};\n" \
+        "    #{function[:return][:type]} cmock_cb_ret = #{generate_call(function)};\n" \
         "    UNITY_CLR_DETAILS();\n" \
-        "    return ret;\n  }\n"
+        "    return cmock_cb_ret;\n  }\n"
       end
   end
 
   def mock_interfaces(function)
     func_name = function[:name]
     has_ignore = @config.plugins.include? :ignore
-    lines = ""
+    lines = ''
     lines << "void #{func_name}_AddCallback(CMOCK_#{func_name}_CALLBACK Callback)\n{\n"
-    lines << "  Mock.#{func_name}_IgnoreBool = (int)0;\n" if has_ignore
-    lines << "  Mock.#{func_name}_CallbackBool = (int)1;\n"
+    lines << "  Mock.#{func_name}_IgnoreBool = (char)0;\n" if has_ignore
+    lines << "  Mock.#{func_name}_CallbackBool = (char)1;\n"
     lines << "  Mock.#{func_name}_CallbackFunctionPointer = Callback;\n}\n\n"
     lines << "void #{func_name}_Stub(CMOCK_#{func_name}_CALLBACK Callback)\n{\n"
-    lines << "  Mock.#{func_name}_IgnoreBool = (int)0;\n" if has_ignore
-    lines << "  Mock.#{func_name}_CallbackBool = (int)0;\n"
+    lines << "  Mock.#{func_name}_IgnoreBool = (char)0;\n" if has_ignore
+    lines << "  Mock.#{func_name}_CallbackBool = (char)0;\n"
     lines << "  Mock.#{func_name}_CallbackFunctionPointer = Callback;\n}\n\n"
   end
 
   def mock_verify(function)
     func_name = function[:name]
-    "  if (Mock.#{func_name}_CallbackFunctionPointer != NULL)\n    call_instance = CMOCK_GUTS_NONE;\n"
+    "  if (Mock.#{func_name}_CallbackFunctionPointer != NULL)\n  {\n" \
+    "    call_instance = CMOCK_GUTS_NONE;\n" \
+    "    (void)call_instance;\n  }\n"
   end
-
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_cexception.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_cexception.rb
index 39d36d64c..7e2d7b628 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_cexception.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_cexception.rb
@@ -5,7 +5,6 @@
 # ==========================================
 
 class CMockGeneratorPluginCexception
-
   attr_reader :priority
   attr_reader :config, :utils
 
@@ -13,39 +12,39 @@ class CMockGeneratorPluginCexception
     @config = config
     @utils = utils
     @priority = 7
+    raise 'Error: cexception is not supported without setjmp support' if @config.exclude_setjmp_h
   end
 
   def include_files
-    return "#include \"CException.h\"\n"
+    "#include \"CException.h\"\n"
   end
 
-  def instance_typedefs(function)
+  def instance_typedefs(_function)
     "  CEXCEPTION_T ExceptionToThrow;\n"
   end
 
   def mock_function_declarations(function)
-    if (function[:args_string] == "void")
-      return "#define #{function[:name]}_ExpectAndThrow(cmock_to_throw) #{function[:name]}_CMockExpectAndThrow(__LINE__, cmock_to_throw)\n" +
+    if function[:args_string] == 'void'
+      "#define #{function[:name]}_ExpectAndThrow(cmock_to_throw) #{function[:name]}_CMockExpectAndThrow(__LINE__, cmock_to_throw)\n" \
              "void #{function[:name]}_CMockExpectAndThrow(UNITY_LINE_TYPE cmock_line, CEXCEPTION_T cmock_to_throw);\n"
     else
-      return "#define #{function[:name]}_ExpectAndThrow(#{function[:args_call]}, cmock_to_throw) #{function[:name]}_CMockExpectAndThrow(__LINE__, #{function[:args_call]}, cmock_to_throw)\n" +
+      "#define #{function[:name]}_ExpectAndThrow(#{function[:args_call]}, cmock_to_throw) #{function[:name]}_CMockExpectAndThrow(__LINE__, #{function[:args_call]}, cmock_to_throw)\n" \
              "void #{function[:name]}_CMockExpectAndThrow(UNITY_LINE_TYPE cmock_line, #{function[:args_string]}, CEXCEPTION_T cmock_to_throw);\n"
     end
   end
 
-  def mock_implementation(function)
-    "  if (cmock_call_instance->ExceptionToThrow != CEXCEPTION_NONE)\n  {\n" +
-    "    UNITY_CLR_DETAILS();\n" +
-    "    Throw(cmock_call_instance->ExceptionToThrow);\n  }\n"
+  def mock_implementation(_function)
+    "  if (cmock_call_instance->ExceptionToThrow != CEXCEPTION_NONE)\n  {\n" \
+      "    UNITY_CLR_DETAILS();\n" \
+      "    Throw(cmock_call_instance->ExceptionToThrow);\n  }\n"
   end
 
   def mock_interfaces(function)
-    arg_insert = (function[:args_string] == "void") ? "" : "#{function[:args_string]}, "
-    [ "void #{function[:name]}_CMockExpectAndThrow(UNITY_LINE_TYPE cmock_line, #{arg_insert}CEXCEPTION_T cmock_to_throw)\n{\n",
-      @utils.code_add_base_expectation(function[:name]),
-      @utils.code_call_argument_loader(function),
-      "  cmock_call_instance->ExceptionToThrow = cmock_to_throw;\n",
-      "}\n\n" ].join
+    arg_insert = function[:args_string] == 'void' ? '' : "#{function[:args_string]}, "
+    ["void #{function[:name]}_CMockExpectAndThrow(UNITY_LINE_TYPE cmock_line, #{arg_insert}CEXCEPTION_T cmock_to_throw)\n{\n",
+     @utils.code_add_base_expectation(function[:name]),
+     @utils.code_call_argument_loader(function),
+     "  cmock_call_instance->ExceptionToThrow = cmock_to_throw;\n",
+     "}\n\n"].join
   end
-
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect.rb
index dcf96f2ed..3a79c1a4d 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect.rb
@@ -5,7 +5,6 @@
 # ==========================================
 
 class CMockGeneratorPluginExpect
-
   attr_reader :priority
   attr_accessor :config, :utils, :unity_helper, :ordered
 
@@ -17,7 +16,7 @@ class CMockGeneratorPluginExpect
     @unity_helper = @utils.helpers[:unity_helper]
     @priority     = 5
 
-    if (@config.plugins.include? :expect_any_args)
+    if @config.plugins.include? :expect_any_args
       alias :mock_implementation :mock_implementation_might_check_args
     else
       alias :mock_implementation :mock_implementation_always_check_args
@@ -25,9 +24,9 @@ class CMockGeneratorPluginExpect
   end
 
   def instance_typedefs(function)
-    lines = ""
-    lines << "  #{function[:return][:type]} ReturnVal;\n"  unless (function[:return][:void?])
-    lines << "  int CallOrder;\n"                          if (@ordered)
+    lines = ''
+    lines << "  #{function[:return][:type]} ReturnVal;\n"  unless function[:return][:void?]
+    lines << "  int CallOrder;\n"                          if @ordered
     function[:args].each do |arg|
       lines << "  #{arg[:type]} Expected_#{arg[:name]};\n"
     end
@@ -35,27 +34,25 @@ class CMockGeneratorPluginExpect
   end
 
   def mock_function_declarations(function)
-    if (function[:args].empty?)
-      if (function[:return][:void?])
-        return "#define #{function[:name]}_Expect() #{function[:name]}_CMockExpect(__LINE__)\n" +
+    if function[:args].empty?
+      if function[:return][:void?]
+        "#define #{function[:name]}_Expect() #{function[:name]}_CMockExpect(__LINE__)\n" \
                "void #{function[:name]}_CMockExpect(UNITY_LINE_TYPE cmock_line);\n"
       else
-        return "#define #{function[:name]}_ExpectAndReturn(cmock_retval) #{function[:name]}_CMockExpectAndReturn(__LINE__, cmock_retval)\n" +
+        "#define #{function[:name]}_ExpectAndReturn(cmock_retval) #{function[:name]}_CMockExpectAndReturn(__LINE__, cmock_retval)\n" \
                "void #{function[:name]}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]});\n"
       end
+    elsif function[:return][:void?]
+      "#define #{function[:name]}_Expect(#{function[:args_call]}) #{function[:name]}_CMockExpect(__LINE__, #{function[:args_call]})\n" \
+             "void #{function[:name]}_CMockExpect(UNITY_LINE_TYPE cmock_line, #{function[:args_string]});\n"
     else
-      if (function[:return][:void?])
-        return "#define #{function[:name]}_Expect(#{function[:args_call]}) #{function[:name]}_CMockExpect(__LINE__, #{function[:args_call]})\n" +
-               "void #{function[:name]}_CMockExpect(UNITY_LINE_TYPE cmock_line, #{function[:args_string]});\n"
-      else
-        return "#define #{function[:name]}_ExpectAndReturn(#{function[:args_call]}, cmock_retval) #{function[:name]}_CMockExpectAndReturn(__LINE__, #{function[:args_call]}, cmock_retval)\n" +
-               "void #{function[:name]}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:args_string]}, #{function[:return][:str]});\n"
-      end
+      "#define #{function[:name]}_ExpectAndReturn(#{function[:args_call]}, cmock_retval) #{function[:name]}_CMockExpectAndReturn(__LINE__, #{function[:args_call]}, cmock_retval)\n" \
+             "void #{function[:name]}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:args_string]}, #{function[:return][:str]});\n"
     end
   end
 
   def mock_implementation_always_check_args(function)
-    lines = ""
+    lines = ''
     function[:args].each do |arg|
       lines << @utils.code_verify_an_arg_expectation(function, arg)
     end
@@ -63,7 +60,8 @@ class CMockGeneratorPluginExpect
   end
 
   def mock_implementation_might_check_args(function)
-    return "" if (function[:args].empty?)
+    return '' if function[:args].empty?
+
     lines = "  if (!cmock_call_instance->ExpectAnyArgsBool)\n  {\n"
     function[:args].each do |arg|
       lines << @utils.code_verify_an_arg_expectation(function, arg)
@@ -73,31 +71,30 @@ class CMockGeneratorPluginExpect
   end
 
   def mock_interfaces(function)
-    lines = ""
+    lines = ''
     func_name = function[:name]
-    if (function[:return][:void?])
-      if (function[:args_string] == "void")
-        lines << "void #{func_name}_CMockExpect(UNITY_LINE_TYPE cmock_line)\n{\n"
-      else
-        lines << "void #{func_name}_CMockExpect(UNITY_LINE_TYPE cmock_line, #{function[:args_string]})\n{\n"
-      end
-    else
-      if (function[:args_string] == "void")
-        lines << "void #{func_name}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]})\n{\n"
-      else
-        lines << "void #{func_name}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:args_string]}, #{function[:return][:str]})\n{\n"
-      end
-    end
+    lines << if function[:return][:void?]
+               if function[:args_string] == 'void'
+                 "void #{func_name}_CMockExpect(UNITY_LINE_TYPE cmock_line)\n{\n"
+               else
+                 "void #{func_name}_CMockExpect(UNITY_LINE_TYPE cmock_line, #{function[:args_string]})\n{\n"
+               end
+             elsif function[:args_string] == 'void'
+               "void #{func_name}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]})\n{\n"
+             else
+               "void #{func_name}_CMockExpectAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:args_string]}, #{function[:return][:str]})\n{\n"
+             end
     lines << @utils.code_add_base_expectation(func_name)
     lines << @utils.code_call_argument_loader(function)
-    lines << @utils.code_assign_argument_quickly("cmock_call_instance->ReturnVal", function[:return]) unless (function[:return][:void?])
+    lines << @utils.code_assign_argument_quickly('cmock_call_instance->ReturnVal', function[:return]) unless function[:return][:void?]
     lines << "}\n\n"
   end
 
   def mock_verify(function)
-    "  UNITY_SET_DETAIL(CMockString_#{function[:name]});\n" +
-    "  UNITY_TEST_ASSERT(CMOCK_GUTS_NONE == call_instance, cmock_line, CMockStringCalledLess);\n" +
-    "  UNITY_CLR_DETAILS();\n"
+    "  if (CMOCK_GUTS_NONE != call_instance)\n" \
+    "  {\n" \
+    "    UNITY_SET_DETAIL(CMockString_#{function[:name]});\n" \
+    "    UNITY_TEST_FAIL(cmock_line, CMockStringCalledLess);\n" \
+    "  }\n"
   end
-
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect_any_args.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect_any_args.rb
index 0c1c74e95..0fc88e124 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect_any_args.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect_any_args.rb
@@ -5,7 +5,6 @@
 # ==========================================
 
 class CMockGeneratorPluginExpectAnyArgs
-
   attr_reader :priority
   attr_reader :config, :utils
 
@@ -15,39 +14,37 @@ class CMockGeneratorPluginExpectAnyArgs
     @priority = 3
   end
 
-  def instance_typedefs(function)
-    "  int ExpectAnyArgsBool;\n"
+  def instance_typedefs(_function)
+    "  char ExpectAnyArgsBool;\n"
   end
 
   def mock_function_declarations(function)
-    unless (function[:args].empty?)
-      if (function[:return][:void?])
-        return "#define #{function[:name]}_ExpectAnyArgs() #{function[:name]}_CMockExpectAnyArgs(__LINE__)\n" +
-               "void #{function[:name]}_CMockExpectAnyArgs(UNITY_LINE_TYPE cmock_line);\n"
-      else
-        return "#define #{function[:name]}_ExpectAnyArgsAndReturn(cmock_retval) #{function[:name]}_CMockExpectAnyArgsAndReturn(__LINE__, cmock_retval)\n" +
-               "void #{function[:name]}_CMockExpectAnyArgsAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]});\n"
-      end
+    if function[:args].empty?
+      ''
+    elsif function[:return][:void?]
+      "#define #{function[:name]}_ExpectAnyArgs() #{function[:name]}_CMockExpectAnyArgs(__LINE__)\n" \
+             "void #{function[:name]}_CMockExpectAnyArgs(UNITY_LINE_TYPE cmock_line);\n"
     else
-      ""
+      "#define #{function[:name]}_ExpectAnyArgsAndReturn(cmock_retval) #{function[:name]}_CMockExpectAnyArgsAndReturn(__LINE__, cmock_retval)\n" \
+             "void #{function[:name]}_CMockExpectAnyArgsAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]});\n"
     end
   end
 
   def mock_interfaces(function)
-    lines = ""
-    unless (function[:args].empty?)
-      if (function[:return][:void?])
-        lines << "void #{function[:name]}_CMockExpectAnyArgs(UNITY_LINE_TYPE cmock_line)\n{\n"
-      else
-        lines << "void #{function[:name]}_CMockExpectAnyArgsAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]})\n{\n"
-      end
+    lines = ''
+    unless function[:args].empty?
+      lines << if function[:return][:void?]
+                 "void #{function[:name]}_CMockExpectAnyArgs(UNITY_LINE_TYPE cmock_line)\n{\n"
+               else
+                 "void #{function[:name]}_CMockExpectAnyArgsAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]})\n{\n"
+               end
       lines << @utils.code_add_base_expectation(function[:name], true)
-      unless (function[:return][:void?])
+      unless function[:return][:void?]
         lines << "  cmock_call_instance->ReturnVal = cmock_to_return;\n"
       end
-      lines << "  cmock_call_instance->ExpectAnyArgsBool = (int)1;\n"
+      lines << "  cmock_call_instance->ExpectAnyArgsBool = (char)1;\n"
       lines << "}\n\n"
     end
-    return lines
+    lines
   end
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb
index 8f31967a1..b292f3d4f 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb
@@ -5,7 +5,6 @@
 # ==========================================
 
 class CMockGeneratorPluginIgnore
-
   attr_reader :priority
   attr_reader :config, :utils
 
@@ -16,56 +15,70 @@ class CMockGeneratorPluginIgnore
   end
 
   def instance_structure(function)
-    if (function[:return][:void?])
-      "  int #{function[:name]}_IgnoreBool;\n"
+    if function[:return][:void?]
+      "  char #{function[:name]}_IgnoreBool;\n"
     else
-      "  int #{function[:name]}_IgnoreBool;\n  #{function[:return][:type]} #{function[:name]}_FinalReturn;\n"
+      "  char #{function[:name]}_IgnoreBool;\n  #{function[:return][:type]} #{function[:name]}_FinalReturn;\n"
     end
   end
 
   def mock_function_declarations(function)
-    if (function[:return][:void?])
-      return "#define #{function[:name]}_Ignore() #{function[:name]}_CMockIgnore()\n" +
-             "void #{function[:name]}_CMockIgnore(void);\n"
-    else
-      return "#define #{function[:name]}_IgnoreAndReturn(cmock_retval) #{function[:name]}_CMockIgnoreAndReturn(__LINE__, cmock_retval)\n" +
-             "void #{function[:name]}_CMockIgnoreAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]});\n"
-    end
+    lines = if function[:return][:void?]
+              "#define #{function[:name]}_Ignore() #{function[:name]}_CMockIgnore()\n" \
+              "void #{function[:name]}_CMockIgnore(void);\n"
+            else
+              "#define #{function[:name]}_IgnoreAndReturn(cmock_retval) #{function[:name]}_CMockIgnoreAndReturn(__LINE__, cmock_retval)\n" \
+              "void #{function[:name]}_CMockIgnoreAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]});\n"
+            end
+
+    # Add stop ignore function. it does not matter if there are any args
+    lines << "#define #{function[:name]}_StopIgnore() #{function[:name]}_CMockStopIgnore()\n" \
+                "void #{function[:name]}_CMockStopIgnore(void);\n"
+    lines
   end
 
   def mock_implementation_precheck(function)
     lines = "  if (Mock.#{function[:name]}_IgnoreBool)\n  {\n"
     lines << "    UNITY_CLR_DETAILS();\n"
-    if (function[:return][:void?])
+    if function[:return][:void?]
       lines << "    return;\n  }\n"
     else
-      retval = function[:return].merge( { :name => "cmock_call_instance->ReturnVal"} )
+      retval = function[:return].merge(:name => 'cmock_call_instance->ReturnVal')
       lines << "    if (cmock_call_instance == NULL)\n      return Mock.#{function[:name]}_FinalReturn;\n"
-      lines << "  " + @utils.code_assign_argument_quickly("Mock.#{function[:name]}_FinalReturn", retval) unless (retval[:void?])
+      lines << '  ' + @utils.code_assign_argument_quickly("Mock.#{function[:name]}_FinalReturn", retval) unless retval[:void?]
       lines << "    return cmock_call_instance->ReturnVal;\n  }\n"
     end
     lines
   end
 
   def mock_interfaces(function)
-    lines = ""
-    if (function[:return][:void?])
-      lines << "void #{function[:name]}_CMockIgnore(void)\n{\n"
-    else
-      lines << "void #{function[:name]}_CMockIgnoreAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]})\n{\n"
-    end
-    if (!function[:return][:void?])
+    lines = ''
+    lines << if function[:return][:void?]
+               "void #{function[:name]}_CMockIgnore(void)\n{\n"
+             else
+               "void #{function[:name]}_CMockIgnoreAndReturn(UNITY_LINE_TYPE cmock_line, #{function[:return][:str]})\n{\n"
+             end
+    unless function[:return][:void?]
       lines << @utils.code_add_base_expectation(function[:name], false)
     end
-    unless (function[:return][:void?])
+    unless function[:return][:void?]
       lines << "  cmock_call_instance->ReturnVal = cmock_to_return;\n"
     end
-    lines << "  Mock.#{function[:name]}_IgnoreBool = (int)1;\n"
+    lines << "  Mock.#{function[:name]}_IgnoreBool = (char)1;\n"
+    lines << "}\n\n"
+
+    # Add stop ignore function. it does not matter if there are any args
+    lines << "void #{function[:name]}_CMockStopIgnore(void)\n{\n"
+    unless function[:return][:void?]
+      lines << "  if(Mock.#{function[:name]}_IgnoreBool)\n"
+      lines << "    Mock.#{function[:name]}_CallInstance = CMock_Guts_MemNext(Mock.#{function[:name]}_CallInstance);\n"
+    end
+    lines << "  Mock.#{function[:name]}_IgnoreBool = (char)0;\n"
     lines << "}\n\n"
   end
 
   def mock_ignore(function)
-    "  Mock.#{function[:name]}_IgnoreBool = (int) 1;\n"
+    "  Mock.#{function[:name]}_IgnoreBool = (char) 1;\n"
   end
 
   def mock_verify(function)
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_arg.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_arg.rb
index ef40e503d..d55e84c25 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_arg.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_arg.rb
@@ -2,21 +2,21 @@ class CMockGeneratorPluginIgnoreArg
   attr_reader :priority
   attr_accessor :utils
 
-  def initialize(config, utils)
+  def initialize(_config, utils)
     @utils        = utils
     @priority     = 10
   end
 
   def instance_typedefs(function)
-    lines = ""
+    lines = ''
     function[:args].each do |arg|
-      lines << "  int IgnoreArg_#{arg[:name]};\n"
+      lines << "  char IgnoreArg_#{arg[:name]};\n"
     end
     lines
   end
 
   def mock_function_declarations(function)
-    lines = ""
+    lines = ''
     function[:args].each do |arg|
       lines << "#define #{function[:name]}_IgnoreArg_#{arg[:name]}()"
       lines << " #{function[:name]}_CMockIgnoreArg_#{arg[:name]}(__LINE__)\n"
@@ -31,8 +31,8 @@ class CMockGeneratorPluginIgnoreArg
     function[:args].each do |arg|
       lines << "void #{func_name}_CMockIgnoreArg_#{arg[:name]}(UNITY_LINE_TYPE cmock_line)\n"
       lines << "{\n"
-      lines << "  CMOCK_#{func_name}_CALL_INSTANCE* cmock_call_instance = " +
-        "(CMOCK_#{func_name}_CALL_INSTANCE*)CMock_Guts_GetAddressFor(CMock_Guts_MemEndOfChain(Mock.#{func_name}_CallInstance));\n"
+      lines << "  CMOCK_#{func_name}_CALL_INSTANCE* cmock_call_instance = " \
+               "(CMOCK_#{func_name}_CALL_INSTANCE*)CMock_Guts_GetAddressFor(CMock_Guts_MemEndOfChain(Mock.#{func_name}_CallInstance));\n"
       lines << "  UNITY_TEST_ASSERT_NOT_NULL(cmock_call_instance, cmock_line, CMockStringIgnPreExp);\n"
       lines << "  cmock_call_instance->IgnoreArg_#{arg[:name]} = 1;\n"
       lines << "}\n\n"
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb
index 1c1af0610..96b20035e 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb
@@ -2,41 +2,41 @@ class CMockGeneratorPluginReturnThruPtr
   attr_reader :priority
   attr_accessor :utils
 
-  def initialize(config, utils)
+  def initialize(_config, utils)
     @utils        = utils
     @priority     = 9
   end
 
   def instance_typedefs(function)
-    lines = ""
+    lines = ''
     function[:args].each do |arg|
-      if (@utils.ptr_or_str?(arg[:type]) and not arg[:const?])
-        lines << "  int ReturnThruPtr_#{arg[:name]}_Used;\n"
-        lines << "  #{arg[:type]} ReturnThruPtr_#{arg[:name]}_Val;\n"
-        lines << "  int ReturnThruPtr_#{arg[:name]}_Size;\n"
-      end
+      next unless @utils.ptr_or_str?(arg[:type]) && !(arg[:const?])
+
+      lines << "  char ReturnThruPtr_#{arg[:name]}_Used;\n"
+      lines << "  #{arg[:type]} ReturnThruPtr_#{arg[:name]}_Val;\n"
+      lines << "  size_t ReturnThruPtr_#{arg[:name]}_Size;\n"
     end
     lines
   end
 
   def mock_function_declarations(function)
-    lines = ""
+    lines = ''
     function[:args].each do |arg|
-      if (@utils.ptr_or_str?(arg[:type]) and not arg[:const?])
-        lines << "#define #{function[:name]}_ReturnThruPtr_#{arg[:name]}(#{arg[:name]})"
-        # If the pointer type actually contains an asterisk, we can do sizeof the type (super safe), otherwise
-        # we need to do a sizeof the dereferenced pointer (which could be a problem if give the wrong size
-        if (arg[:type][-1] == '*')
-          lines << " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, sizeof(#{arg[:type][0..-2]}))\n"
-        else
-          lines << " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, sizeof(*#{arg[:name]}))\n"
-        end
-        lines << "#define #{function[:name]}_ReturnArrayThruPtr_#{arg[:name]}(#{arg[:name]}, cmock_len)"
-        lines << " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, (int)(cmock_len * (int)sizeof(*#{arg[:name]})))\n"
-        lines << "#define #{function[:name]}_ReturnMemThruPtr_#{arg[:name]}(#{arg[:name]}, cmock_size)"
-        lines << " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, cmock_size)\n"
-        lines << "void #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(UNITY_LINE_TYPE cmock_line, #{arg[:type]} #{arg[:name]}, int cmock_size);\n"
-      end
+      next unless @utils.ptr_or_str?(arg[:type]) && !(arg[:const?])
+
+      lines << "#define #{function[:name]}_ReturnThruPtr_#{arg[:name]}(#{arg[:name]})"
+      # If the pointer type actually contains an asterisk, we can do sizeof the type (super safe), otherwise
+      # we need to do a sizeof the dereferenced pointer (which could be a problem if give the wrong size
+      lines << if arg[:type][-1] == '*'
+                 " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, sizeof(#{arg[:type][0..-2]}))\n"
+               else
+                 " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, sizeof(*#{arg[:name]}))\n"
+               end
+      lines << "#define #{function[:name]}_ReturnArrayThruPtr_#{arg[:name]}(#{arg[:name]}, cmock_len)"
+      lines << " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, cmock_len * sizeof(*#{arg[:name]}))\n"
+      lines << "#define #{function[:name]}_ReturnMemThruPtr_#{arg[:name]}(#{arg[:name]}, cmock_size)"
+      lines << " #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(__LINE__, #{arg[:name]}, cmock_size)\n"
+      lines << "void #{function[:name]}_CMockReturnMemThruPtr_#{arg[:name]}(UNITY_LINE_TYPE cmock_line, #{arg[:type]} #{arg[:name]}, size_t cmock_size);\n"
     end
     lines
   end
@@ -46,17 +46,17 @@ class CMockGeneratorPluginReturnThruPtr
     func_name = function[:name]
     function[:args].each do |arg|
       arg_name = arg[:name]
-      if (@utils.ptr_or_str?(arg[:type]) and not arg[:const?])
-        lines << "void #{func_name}_CMockReturnMemThruPtr_#{arg_name}(UNITY_LINE_TYPE cmock_line, #{arg[:type]} #{arg_name}, int cmock_size)\n"
-        lines << "{\n"
-        lines << "  CMOCK_#{func_name}_CALL_INSTANCE* cmock_call_instance = " +
-          "(CMOCK_#{func_name}_CALL_INSTANCE*)CMock_Guts_GetAddressFor(CMock_Guts_MemEndOfChain(Mock.#{func_name}_CallInstance));\n"
-        lines << "  UNITY_TEST_ASSERT_NOT_NULL(cmock_call_instance, cmock_line, CMockStringPtrPreExp);\n"
-        lines << "  cmock_call_instance->ReturnThruPtr_#{arg_name}_Used = 1;\n"
-        lines << "  cmock_call_instance->ReturnThruPtr_#{arg_name}_Val = #{arg_name};\n"
-        lines << "  cmock_call_instance->ReturnThruPtr_#{arg_name}_Size = cmock_size;\n"
-        lines << "}\n\n"
-      end
+      next unless @utils.ptr_or_str?(arg[:type]) && !(arg[:const?])
+
+      lines << "void #{func_name}_CMockReturnMemThruPtr_#{arg_name}(UNITY_LINE_TYPE cmock_line, #{arg[:type]} #{arg_name}, size_t cmock_size)\n"
+      lines << "{\n"
+      lines << "  CMOCK_#{func_name}_CALL_INSTANCE* cmock_call_instance = " \
+               "(CMOCK_#{func_name}_CALL_INSTANCE*)CMock_Guts_GetAddressFor(CMock_Guts_MemEndOfChain(Mock.#{func_name}_CallInstance));\n"
+      lines << "  UNITY_TEST_ASSERT_NOT_NULL(cmock_call_instance, cmock_line, CMockStringPtrPreExp);\n"
+      lines << "  cmock_call_instance->ReturnThruPtr_#{arg_name}_Used = 1;\n"
+      lines << "  cmock_call_instance->ReturnThruPtr_#{arg_name}_Val = #{arg_name};\n"
+      lines << "  cmock_call_instance->ReturnThruPtr_#{arg_name}_Size = cmock_size;\n"
+      lines << "}\n\n"
     end
     lines
   end
@@ -65,14 +65,14 @@ class CMockGeneratorPluginReturnThruPtr
     lines = []
     function[:args].each do |arg|
       arg_name = arg[:name]
-      if (@utils.ptr_or_str?(arg[:type]) and not arg[:const?])
-        lines << "  if (cmock_call_instance->ReturnThruPtr_#{arg_name}_Used)\n"
-        lines << "  {\n"
-        lines << "    UNITY_TEST_ASSERT_NOT_NULL(#{arg_name}, cmock_line, CMockStringPtrIsNULL);\n"
-        lines << "    memcpy((void*)#{arg_name}, (void*)cmock_call_instance->ReturnThruPtr_#{arg_name}_Val,\n"
-        lines << "      cmock_call_instance->ReturnThruPtr_#{arg_name}_Size);\n"
-        lines << "  }\n"
-      end
+      next unless @utils.ptr_or_str?(arg[:type]) && !(arg[:const?])
+
+      lines << "  if (cmock_call_instance->ReturnThruPtr_#{arg_name}_Used)\n"
+      lines << "  {\n"
+      lines << "    UNITY_TEST_ASSERT_NOT_NULL(#{arg_name}, cmock_line, CMockStringPtrIsNULL);\n"
+      lines << "    memcpy((void*)#{arg_name}, (void*)cmock_call_instance->ReturnThruPtr_#{arg_name}_Val,\n"
+      lines << "      cmock_call_instance->ReturnThruPtr_#{arg_name}_Size);\n"
+      lines << "  }\n"
     end
     lines
   end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_utils.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_utils.rb
index 994e85c5d..ecbc37e51 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_utils.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_utils.rb
@@ -5,10 +5,9 @@
 # ==========================================
 
 class CMockGeneratorUtils
-
   attr_accessor :config, :helpers, :ordered, :ptr_handling, :arrays, :cexception
 
-  def initialize(config, helpers={})
+  def initialize(config, helpers = {})
     @config = config
     @ptr_handling = @config.when_ptr
     @ordered      = @config.enforce_strict_ordering
@@ -16,9 +15,10 @@ class CMockGeneratorUtils
     @cexception   = @config.plugins.include? :cexception
     @expect_any   = @config.plugins.include? :expect_any_args
     @return_thru_ptr = @config.plugins.include? :return_thru_ptr
-    @ignore_arg   = @config.plugins.include? :ignore_arg
-    @ignore       = @config.plugins.include? :ignore
-    @treat_as     = @config.treat_as
+    @ignore_arg = @config.plugins.include? :ignore_arg
+    @ignore = @config.plugins.include? :ignore
+    @ignore_stateless = @config.plugins.include? :ignore_stateless
+    @treat_as = @config.treat_as
     @helpers = helpers
   end
 
@@ -36,78 +36,78 @@ class CMockGeneratorUtils
   end
 
   def code_verify_an_arg_expectation(function, arg)
-    if (@arrays)
-      case(@ptr_handling)
-        when :smart        then code_verify_an_arg_expectation_with_smart_arrays(function, arg)
-        when :compare_data then code_verify_an_arg_expectation_with_normal_arrays(function, arg)
-        when :compare_ptr  then raise "ERROR: the array plugin doesn't enjoy working with :compare_ptr only.  Disable one option."
+    if @arrays
+      case @ptr_handling
+      when :smart        then code_verify_an_arg_expectation_with_smart_arrays(function, arg)
+      when :compare_data then code_verify_an_arg_expectation_with_normal_arrays(function, arg)
+      when :compare_ptr  then raise "ERROR: the array plugin doesn't enjoy working with :compare_ptr only.  Disable one option."
       end
     else
       code_verify_an_arg_expectation_with_no_arrays(function, arg)
     end
   end
 
-  def code_add_base_expectation(func_name, global_ordering_supported=true)
+  def code_add_base_expectation(func_name, global_ordering_supported = true)
     lines =  "  CMOCK_MEM_INDEX_TYPE cmock_guts_index = CMock_Guts_MemNew(sizeof(CMOCK_#{func_name}_CALL_INSTANCE));\n"
     lines << "  CMOCK_#{func_name}_CALL_INSTANCE* cmock_call_instance = (CMOCK_#{func_name}_CALL_INSTANCE*)CMock_Guts_GetAddressFor(cmock_guts_index);\n"
     lines << "  UNITY_TEST_ASSERT_NOT_NULL(cmock_call_instance, cmock_line, CMockStringOutOfMemory);\n"
     lines << "  memset(cmock_call_instance, 0, sizeof(*cmock_call_instance));\n"
     lines << "  Mock.#{func_name}_CallInstance = CMock_Guts_MemChain(Mock.#{func_name}_CallInstance, cmock_guts_index);\n"
-    lines << "  Mock.#{func_name}_IgnoreBool = (int)0;\n" if (@ignore)
+    lines << "  Mock.#{func_name}_IgnoreBool = (char)0;\n" if @ignore || @ignore_stateless
     lines << "  cmock_call_instance->LineNumber = cmock_line;\n"
-    lines << "  cmock_call_instance->CallOrder = ++GlobalExpectCount;\n" if (@ordered and global_ordering_supported)
-    lines << "  cmock_call_instance->ExceptionToThrow = CEXCEPTION_NONE;\n" if (@cexception)
-    lines << "  cmock_call_instance->ExpectAnyArgsBool = (int)0;\n" if (@expect_any)
+    lines << "  cmock_call_instance->CallOrder = ++GlobalExpectCount;\n" if @ordered && global_ordering_supported
+    lines << "  cmock_call_instance->ExceptionToThrow = CEXCEPTION_NONE;\n" if @cexception
+    lines << "  cmock_call_instance->ExpectAnyArgsBool = (char)0;\n" if @expect_any
     lines
   end
 
-  def code_add_an_arg_expectation(arg, depth=1)
+  def code_add_an_arg_expectation(arg, depth = 1)
     lines =  code_assign_argument_quickly("cmock_call_instance->Expected_#{arg[:name]}", arg)
-    lines << "  cmock_call_instance->Expected_#{arg[:name]}_Depth = #{arg[:name]}_Depth;\n" if (@arrays and (depth.class == String))
-    lines << "  cmock_call_instance->IgnoreArg_#{arg[:name]} = 0;\n" if (@ignore_arg)
-    lines << "  cmock_call_instance->ReturnThruPtr_#{arg[:name]}_Used = 0;\n" if (@return_thru_ptr and ptr_or_str?(arg[:type]) and not arg[:const?])
+    lines << "  cmock_call_instance->Expected_#{arg[:name]}_Depth = #{arg[:name]}_Depth;\n" if @arrays && (depth.class == String)
+    lines << "  cmock_call_instance->IgnoreArg_#{arg[:name]} = 0;\n" if @ignore_arg
+    lines << "  cmock_call_instance->ReturnThruPtr_#{arg[:name]}_Used = 0;\n" if @return_thru_ptr && ptr_or_str?(arg[:type]) && !(arg[:const?])
     lines
   end
 
   def code_assign_argument_quickly(dest, arg)
-    if (arg[:ptr?] or @treat_as.include?(arg[:type]))
+    if arg[:ptr?] || @treat_as.include?(arg[:type])
       "  #{dest} = #{arg[:name]};\n"
     else
       assert_expr = "sizeof(#{arg[:name]}) == sizeof(#{arg[:type]}) ? 1 : -1"
       comment = "/* add #{arg[:type]} to :treat_as_array if this causes an error */"
-      "  memcpy((void*)(&#{dest}), (void*)(&#{arg[:name]}),\n" +
-      "         sizeof(#{arg[:type]}[#{assert_expr}])); #{comment}\n"
+      "  memcpy((void*)(&#{dest}), (void*)(&#{arg[:name]}),\n" \
+        "         sizeof(#{arg[:type]}[#{assert_expr}])); #{comment}\n"
     end
   end
 
   def code_add_argument_loader(function)
-    if (function[:args_string] != "void")
-      if (@arrays)
+    if function[:args_string] != 'void'
+      if @arrays
         args_string = function[:args].map do |m|
           type = arg_type_with_const(m)
           m[:ptr?] ? "#{type} #{m[:name]}, int #{m[:name]}_Depth" : "#{type} #{m[:name]}"
         end.join(', ')
-        "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{args_string});\n" +
-        "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{args_string})\n{\n" +
-        function[:args].inject("") { |all, arg| all + code_add_an_arg_expectation(arg, (arg[:ptr?] ? "#{arg[:name]}_Depth" : 1) ) } +
-        "}\n\n"
+        "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{args_string});\n" \
+          "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{args_string})\n{\n" +
+          function[:args].inject('') { |all, arg| all + code_add_an_arg_expectation(arg, (arg[:ptr?] ? "#{arg[:name]}_Depth" : 1)) } +
+          "}\n\n"
       else
-        "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{function[:args_string]});\n" +
-        "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{function[:args_string]})\n{\n" +
-        function[:args].inject("") { |all, arg| all + code_add_an_arg_expectation(arg) } +
-        "}\n\n"
+        "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{function[:args_string]});\n" \
+          "void CMockExpectParameters_#{function[:name]}(CMOCK_#{function[:name]}_CALL_INSTANCE* cmock_call_instance, #{function[:args_string]})\n{\n" +
+          function[:args].inject('') { |all, arg| all + code_add_an_arg_expectation(arg) } +
+          "}\n\n"
       end
     else
-      ""
+      ''
     end
   end
 
   def code_call_argument_loader(function)
-    if (function[:args_string] != "void")
+    if function[:args_string] != 'void'
       args = function[:args].map do |m|
-        if (@arrays and m[:ptr?] and not m[:array_data?])
+        if @arrays && m[:ptr?] && !(m[:array_data?])
           "#{m[:name]}, 1"
-        elsif (@arrays and m[:array_size?])
+        elsif @arrays && m[:array_size?]
           "#{m[:name]}, #{m[:name]}"
         else
           m[:name]
@@ -115,60 +115,60 @@ class CMockGeneratorUtils
       end
       "  CMockExpectParameters_#{function[:name]}(cmock_call_instance, #{args.join(', ')});\n"
     else
-      ""
+      ''
     end
   end
 
   def ptr_or_str?(arg_type)
-    return (arg_type.include? '*' or
-            @treat_as.fetch(arg_type, "").include? '*')
+    (arg_type.include?('*') ||
+            @treat_as.fetch(arg_type, '').include?('*'))
   end
 
-  #private ######################
+  # private ######################
 
-  def lookup_expect_type(function, arg)
+  def lookup_expect_type(_function, arg)
     c_type     = arg[:type]
     arg_name   = arg[:name]
     expected   = "cmock_call_instance->Expected_#{arg_name}"
     ignore     = "cmock_call_instance->IgnoreArg_#{arg_name}"
-    unity_func = if ((arg[:ptr?]) and ((c_type =~ /\*\*/) or (@ptr_handling == :compare_ptr)))
+    unity_func = if (arg[:ptr?]) && ((c_type =~ /\*\*/) || (@ptr_handling == :compare_ptr))
                    ['UNITY_TEST_ASSERT_EQUAL_PTR', '']
                  else
-                   (@helpers.nil? or @helpers[:unity_helper].nil?) ? ["UNITY_TEST_ASSERT_EQUAL",''] : @helpers[:unity_helper].get_helper(c_type)
+                   @helpers.nil? || @helpers[:unity_helper].nil? ? ['UNITY_TEST_ASSERT_EQUAL', ''] : @helpers[:unity_helper].get_helper(c_type)
                  end
-    return c_type, arg_name, expected, ignore, unity_func[0], unity_func[1]
+    [c_type, arg_name, expected, ignore, unity_func[0], unity_func[1]]
   end
 
   def code_verify_an_arg_expectation_with_no_arrays(function, arg)
     c_type, arg_name, expected, ignore, unity_func, pre = lookup_expect_type(function, arg)
-    lines = ""
+    lines = ''
     lines << "  if (!#{ignore})\n" if @ignore_arg
     lines << "  {\n"
     lines << "    UNITY_SET_DETAILS(CMockString_#{function[:name]},CMockString_#{arg_name});\n"
-    case(unity_func)
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY"
-        c_type_local = c_type.gsub(/\*$/,'')
-        lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type_local}), cmock_line, CMockStringMismatch);\n"
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY"
-        if (pre == '&')
-          lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << "    else\n"
-          lines << "      { UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), cmock_line, CMockStringMismatch); }\n"
-        end
-      when /_ARRAY/
-        if (pre == '&')
-          lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, 1, cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << "    else\n"
-          lines << "      { #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, 1, cmock_line, CMockStringMismatch); }\n"
-        end
+    case unity_func
+    when 'UNITY_TEST_ASSERT_EQUAL_MEMORY'
+      c_type_local = c_type.gsub(/\*$/, '')
+      lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type_local}), cmock_line, CMockStringMismatch);\n"
+    when 'UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY'
+      if pre == '&'
+        lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*', '')}), cmock_line, CMockStringMismatch);\n"
       else
-        lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch);\n"
+        lines << "    if (#{pre}#{expected} == NULL)\n"
+        lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
+        lines << "    else\n"
+        lines << "      { UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*', '')}), cmock_line, CMockStringMismatch); }\n"
+      end
+    when /_ARRAY/
+      if pre == '&'
+        lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, 1, cmock_line, CMockStringMismatch);\n"
+      else
+        lines << "    if (#{pre}#{expected} == NULL)\n"
+        lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
+        lines << "    else\n"
+        lines << "      { #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, 1, cmock_line, CMockStringMismatch); }\n"
+      end
+    else
+      lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch);\n"
     end
     lines << "  }\n"
     lines
@@ -176,78 +176,75 @@ class CMockGeneratorUtils
 
   def code_verify_an_arg_expectation_with_normal_arrays(function, arg)
     c_type, arg_name, expected, ignore, unity_func, pre = lookup_expect_type(function, arg)
-    depth_name = (arg[:ptr?]) ? "cmock_call_instance->Expected_#{arg_name}_Depth" : 1
-    lines = ""
+    depth_name = arg[:ptr?] ? "cmock_call_instance->Expected_#{arg_name}_Depth" : 1
+    lines = ''
     lines << "  if (!#{ignore})\n" if @ignore_arg
     lines << "  {\n"
     lines << "    UNITY_SET_DETAILS(CMockString_#{function[:name]},CMockString_#{arg_name});\n"
-    lines << "    if (#{pre}#{expected} != #{pre}#{arg_name}) {\n"
-    case(unity_func)
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY"
-        c_type_local = c_type.gsub(/\*$/,'')
-        lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type_local}), cmock_line, CMockStringMismatch);\n"
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY"
-        if (pre == '&')
-          lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << "    else\n"
-          lines << "      { UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), #{depth_name}, cmock_line, CMockStringMismatch); }\n"
-        end
-      when /_ARRAY/
-        if (pre == '&')
-          lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << "    else\n"
-          lines << "      { #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch); }\n"
-        end
+    case unity_func
+    when 'UNITY_TEST_ASSERT_EQUAL_MEMORY'
+      c_type_local = c_type.gsub(/\*$/, '')
+      lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type_local}), cmock_line, CMockStringMismatch);\n"
+    when 'UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY'
+      if pre == '&'
+        lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*', '')}), cmock_line, CMockStringMismatch);\n"
       else
-        lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch);\n"
+        lines << "    if (#{pre}#{expected} == NULL)\n"
+        lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
+        lines << "    else\n"
+        lines << "      { UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*', '')}), #{depth_name}, cmock_line, CMockStringMismatch); }\n"
+      end
+    when /_ARRAY/
+      if pre == '&'
+        lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch);\n"
+      else
+        lines << "    if (#{pre}#{expected} == NULL)\n"
+        lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
+        lines << "    else\n"
+        lines << "      { #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch); }\n"
+      end
+    else
+      lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch);\n"
     end
-    lines << "      }\n  }\n"
+    lines << "  }\n"
     lines
   end
 
   def code_verify_an_arg_expectation_with_smart_arrays(function, arg)
     c_type, arg_name, expected, ignore, unity_func, pre = lookup_expect_type(function, arg)
-    depth_name = (arg[:ptr?]) ? "cmock_call_instance->Expected_#{arg_name}_Depth" : 1
-    lines = ""
+    depth_name = arg[:ptr?] ? "cmock_call_instance->Expected_#{arg_name}_Depth" : 1
+    lines = ''
     lines << "  if (!#{ignore})\n" if @ignore_arg
     lines << "  {\n"
     lines << "    UNITY_SET_DETAILS(CMockString_#{function[:name]},CMockString_#{arg_name});\n"
-    lines << "    if (#{pre}#{expected} != #{pre}#{arg_name}) {\n"
-    case(unity_func)
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY"
-        c_type_local = c_type.gsub(/\*$/,'')
-        lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type_local}), cmock_line, CMockStringMismatch);\n"
-      when "UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY"
-        if (pre == '&')
-          lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), #{depth_name}, cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << ((depth_name != 1) ? "    else if (#{depth_name} == 0)\n      { UNITY_TEST_ASSERT_EQUAL_PTR(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch); }\n" : "")
-          lines << "    else\n"
-          lines << "      { UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*','')}), #{depth_name}, cmock_line, CMockStringMismatch); }\n"
-        end
-      when /_ARRAY/
-        if (pre == '&')
-          lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch);\n"
-        else
-          lines << "    if (#{pre}#{expected} == NULL)\n"
-          lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
-          lines << ((depth_name != 1) ? "    else if (#{depth_name} == 0)\n      { UNITY_TEST_ASSERT_EQUAL_PTR(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch); }\n" : "")
-          lines << "    else\n"
-          lines << "      { #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch); }\n"
-        end
+    case unity_func
+    when 'UNITY_TEST_ASSERT_EQUAL_MEMORY'
+      c_type_local = c_type.gsub(/\*$/, '')
+      lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type_local}), cmock_line, CMockStringMismatch);\n"
+    when 'UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY'
+      if pre == '&'
+        lines << "    UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*', '')}), #{depth_name}, cmock_line, CMockStringMismatch);\n"
       else
-        lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch);\n"
+        lines << "    if (#{pre}#{expected} == NULL)\n"
+        lines << "      { UNITY_TEST_ASSERT_NULL(#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
+        lines << (depth_name != 1 ? "    else if (#{depth_name} == 0)\n      { UNITY_TEST_ASSERT_EQUAL_PTR(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch); }\n" : '')
+        lines << "    else\n"
+        lines << "      { UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY((void*)(#{pre}#{expected}), (void*)(#{pre}#{arg_name}), sizeof(#{c_type.sub('*', '')}), #{depth_name}, cmock_line, CMockStringMismatch); }\n"
+      end
+    when /_ARRAY/
+      if pre == '&'
+        lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch);\n"
+      else
+        lines << "    if (#{pre}#{expected} == NULL)\n"
+        lines << "      { UNITY_TEST_ASSERT_NULL(#{pre}#{arg_name}, cmock_line, CMockStringExpNULL); }\n"
+        lines << (depth_name != 1 ? "    else if (#{depth_name} == 0)\n      { UNITY_TEST_ASSERT_EQUAL_PTR(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch); }\n" : '')
+        lines << "    else\n"
+        lines << "      { #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, #{depth_name}, cmock_line, CMockStringMismatch); }\n"
+      end
+    else
+      lines << "    #{unity_func}(#{pre}#{expected}, #{pre}#{arg_name}, cmock_line, CMockStringMismatch);\n"
     end
-    lines << "    }\n  }\n"
+    lines << "  }\n"
     lines
   end
-
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb
index 0cf19478d..9730bf40b 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb
@@ -5,54 +5,217 @@
 # ==========================================
 
 class CMockHeaderParser
-
-  attr_accessor :funcs, :c_attr_noconst, :c_attributes, :treat_as_void, :treat_externs
+  attr_accessor :funcs, :c_attr_noconst, :c_attributes, :treat_as_void, :treat_externs, :treat_inlines, :inline_function_patterns
 
   def initialize(cfg)
-    @funcs = []
     @c_strippables = cfg.strippables
     @c_attr_noconst = cfg.attributes.uniq - ['const']
     @c_attributes = ['const'] + c_attr_noconst
     @c_calling_conventions = cfg.c_calling_conventions.uniq
     @treat_as_array = cfg.treat_as_array
     @treat_as_void = (['void'] + cfg.treat_as_void).uniq
-    @declaration_parse_matcher = /([\w\s\*\(\),\[\]]+??)\(([\w\s\*\(\),\.\[\]+-]*)\)$/m
-    @standards = (['int','short','char','long','unsigned','signed'] + cfg.treat_as.keys).uniq
+    @function_declaration_parse_base_match = '([\w\s\*\(\),\[\]]+??)\(([\w\s\*\(\),\.\[\]+\-\/]*)\)'
+    @declaration_parse_matcher = /#{@function_declaration_parse_base_match}$/m
+    @standards = (%w[int short char long unsigned signed] + cfg.treat_as.keys).uniq
     @array_size_name = cfg.array_size_name
-    @array_size_type = (['int', 'size_t'] + cfg.array_size_type).uniq
+    @array_size_type = (%w[int size_t] + cfg.array_size_type).uniq
     @when_no_prototypes = cfg.when_no_prototypes
     @local_as_void = @treat_as_void
     @verbosity = cfg.verbosity
     @treat_externs = cfg.treat_externs
-    @c_strippables += ['extern'] if (@treat_externs == :include) #we'll need to remove the attribute if we're allowing externs
+    @treat_inlines = cfg.treat_inlines
+    @inline_function_patterns = cfg.inline_function_patterns
+    @c_strippables += ['extern'] if @treat_externs == :include # we'll need to remove the attribute if we're allowing externs
+    @c_strippables += ['inline'] if @treat_inlines == :include # we'll need to remove the attribute if we're allowing inlines
   end
 
   def parse(name, source)
-    @module_name = name.gsub(/\W/,'')
-    @typedefs = []
-    @funcs = []
+    parse_project = {
+      :module_name       => name.gsub(/\W/, ''),
+      :typedefs          => [],
+      :functions         => [],
+      :normalized_source => nil
+    }
+
     function_names = []
 
-    parse_functions( import_source(source) ).map do |decl|
-      func = parse_declaration(decl)
-      unless (function_names.include? func[:name])
-        @funcs << func
+    all_funcs = parse_functions(import_source(source, parse_project)).map { |item| [item] }
+    all_funcs += parse_cpp_functions(import_source(source, parse_project, true))
+    all_funcs.map do |decl|
+      func = parse_declaration(parse_project, *decl)
+      unless function_names.include? func[:name]
+        parse_project[:functions] << func
         function_names << func[:name]
       end
     end
 
+    parse_project[:normalized_source] = if @treat_inlines == :include
+                                          transform_inline_functions(source)
+                                        else
+                                          ''
+                                        end
+
     { :includes  => nil,
-      :functions => @funcs,
-      :typedefs  => @typedefs
-    }
+      :functions => parse_project[:functions],
+      :typedefs  => parse_project[:typedefs],
+      :normalized_source    => parse_project[:normalized_source] }
   end
 
   private if $ThisIsOnlyATest.nil? ################
 
-  def import_source(source)
+  # Remove C/C++ comments from a string
+  # +source+:: String which will have the comments removed
+  def remove_comments_from_source(source)
+    # remove comments (block and line, in three steps to ensure correct precedence)
+    source.gsub!(/(?<!\*)\/\/(?:.+\/\*|\*(?:$|[^\/])).*$/, '')  # remove line comments that comment out the start of blocks
+    source.gsub!(/\/\*.*?\*\//m, '')                            # remove block comments
+    source.gsub!(/\/\/.*$/, '')                                 # remove line comments (all that remain)
+  end
+
+  def remove_nested_pairs_of_braces(source)
+    # remove nested pairs of braces because no function declarations will be inside of them (leave outer pair for function definition detection)
+    if RUBY_VERSION.split('.')[0].to_i > 1
+      # we assign a string first because (no joke) if Ruby 1.9.3 sees this line as a regex, it will crash.
+      r = '\\{([^\\{\\}]*|\\g<0>)*\\}'
+      source.gsub!(/#{r}/m, '{ }')
+    else
+      while source.gsub!(/\{[^\{\}]*\{[^\{\}]*\}[^\{\}]*\}/m, '{ }')
+      end
+    end
+
+    source
+  end
+
+  # Return the number of pairs of braces/square brackets in the function provided by the user
+  # +source+:: String containing the function to be processed
+  def count_number_of_pairs_of_braces_in_function(source)
+    is_function_start_found = false
+    curr_level = 0
+    total_pairs = 0
+
+    source.each_char do |c|
+      if c == '{'
+        curr_level += 1
+        total_pairs += 1
+        is_function_start_found = true
+      elsif c == '}'
+        curr_level -= 1
+      end
+
+      break if is_function_start_found && curr_level == 0 # We reached the end of the inline function body
+    end
+
+    if curr_level != 0
+      total_pairs = 0 # Something is fishy about this source, not enough closing braces?
+    end
+
+    total_pairs
+  end
+
+  # Transform inline functions to regular functions in the source by the user
+  # +source+:: String containing the source to be processed
+  def transform_inline_functions(source)
+    inline_function_regex_formats = []
+    square_bracket_pair_regex_format = /\{[^\{\}]*\}/ # Regex to match one whole block enclosed by two square brackets
+
+    # Convert user provided string patterns to regex
+    # Use word bounderies before and after the user regex to limit matching to actual word iso part of a word
+    @inline_function_patterns.each do |user_format_string|
+      user_regex = Regexp.new(user_format_string)
+      word_boundary_before_user_regex = /\b/
+      cleanup_spaces_after_user_regex = /[ ]*\b/
+      inline_function_regex_formats << Regexp.new(word_boundary_before_user_regex.source + user_regex.source + cleanup_spaces_after_user_regex.source)
+    end
 
     # let's clean up the encoding in case they've done anything weird with the characters we might find
-    source = source.force_encoding("ISO-8859-1").encode("utf-8", :replace => nil)
+    source = source.force_encoding('ISO-8859-1').encode('utf-8', :replace => nil)
+
+    # Comments can contain words that will trigger the parser (static|inline|<user_defined_static_keyword>)
+    remove_comments_from_source(source)
+
+    # smush multiline macros into single line (checking for continuation character at end of line '\')
+    # If the user uses a macro to declare an inline function,
+    # smushing the macros makes it easier to recognize them as a macro and if required,
+    # remove them later on in this function
+    source.gsub!(/\s*\\\s*/m, ' ')
+
+    # Just looking for static|inline in the gsub is a bit too aggressive (functions that are named like this, ...), so we try to be a bit smarter
+    # Instead, look for an inline pattern (f.e. "static inline") and parse it.
+    # Below is a small explanation on how the general mechanism works:
+    #  - Everything before the match should just be copied, we don't want
+    #    to touch anything but the inline functions.
+    #  - Remove the implementation of the inline function (this is enclosed
+    #    in square brackets) and replace it with ";" to complete the
+    #    transformation to normal/non-inline function.
+    #    To ensure proper removal of the function body, we count the number of square-bracket pairs
+    #    and remove the pairs one-by-one.
+    #  - Copy everything after the inline function implementation and start the parsing of the next inline function
+    # There are ofcourse some special cases (inline macro declarations, inline function declarations, ...) which are handled and explained below
+    inline_function_regex_formats.each do |format|
+      inspected_source = ''
+      regex_matched = false
+      loop do
+        inline_function_match = source.match(/#{format}/) # Search for inline function declaration
+
+        if inline_function_match.nil? # No inline functions so nothing to do
+          # Join pre and post match stripped parts for the next inline function detection regex
+          source = inspected_source + source if regex_matched == true
+          break
+        end
+
+        regex_matched = true
+        # 1. Determine if we are dealing with a user defined macro to declare inline functions
+        # If the end of the pre-match string is a macro-declaration-like string,
+        # we are dealing with a user defined macro to declare inline functions
+        if /(#define\s*)\z/ =~ inline_function_match.pre_match
+          # Remove the macro from the source
+          stripped_pre_match = inline_function_match.pre_match.sub(/(#define\s*)\z/, '')
+          stripped_post_match = inline_function_match.post_match.sub(/\A(.*[\n]?)/, '')
+          inspected_source += stripped_pre_match
+          source = stripped_post_match
+          next
+        end
+
+        # 2. Determine if we are dealing with an inline function declaration iso function definition
+        # If the start of the post-match string is a function-declaration-like string (something ending with semicolon after the function arguments),
+        # we are dealing with a inline function declaration
+        if /\A#{@function_declaration_parse_base_match}\s*;/m =~ inline_function_match.post_match
+          # Only remove the inline part from the function declaration, leaving the function declaration won't do any harm
+          inspected_source += inline_function_match.pre_match
+          source = inline_function_match.post_match
+          next
+        end
+
+        # 3. If we get here, we found an inline function declaration AND inline function body.
+        # Remove the function body to transform it into a 'normal' function declaration.
+        if /\A#{@function_declaration_parse_base_match}\s*\{/m =~ inline_function_match.post_match
+          total_pairs_to_remove = count_number_of_pairs_of_braces_in_function(inline_function_match.post_match)
+
+          break if total_pairs_to_remove == 0 # Bad source?
+
+          inline_function_stripped = inline_function_match.post_match
+
+          total_pairs_to_remove.times do
+            inline_function_stripped.sub!(/\s*#{square_bracket_pair_regex_format}/, ';') # Remove inline implementation (+ some whitespace because it's prettier)
+          end
+          inspected_source += inline_function_match.pre_match
+          source = inline_function_stripped
+          next
+        end
+
+        # 4. If we get here, it means the regex match, but it is not related to the function (ex. static variable in header)
+        # Leave this code as it is.
+        inspected_source += inline_function_match.pre_match + inline_function_match[0]
+        source = inline_function_match.post_match
+      end
+    end
+
+    source
+  end
+
+  def import_source(source, parse_project, cpp = false)
+    # let's clean up the encoding in case they've done anything weird with the characters we might find
+    source = source.force_encoding('ISO-8859-1').encode('utf-8', :replace => nil)
 
     # void must be void for cmock _ExpectAndReturn calls to process properly, not some weird typedef which equates to void
     # to a certain extent, this action assumes we're chewing on pre-processed header files, otherwise we'll most likely just get stuff from @treat_as_void
@@ -62,13 +225,18 @@ class CMockHeaderParser
       @local_as_void += void_types.flatten.uniq.compact
     end
 
+    # If user wants to mock inline functions,
+    # remove the (user specific) inline keywords before removing anything else to avoid missing an inline function
+    if @treat_inlines == :include
+      @inline_function_patterns.each do |user_format_string|
+        source.gsub!(/#{user_format_string}/, '') # remove user defined inline function patterns
+      end
+    end
+
     # smush multiline macros into single line (checking for continuation character at end of line '\')
     source.gsub!(/\s*\\\s*/m, ' ')
 
-    #remove comments (block and line, in three steps to ensure correct precedence)
-    source.gsub!(/(?<!\*)\/\/(?:.+\/\*|\*(?:$|[^\/])).*$/, '')  # remove line comments that comment out the start of blocks
-    source.gsub!(/\/\*.*?\*\//m, '')                            # remove block comments
-    source.gsub!(/\/\/.*$/, '')                                 # remove line comments (all that remain)
+    remove_comments_from_source(source)
 
     # remove assembler pragma sections
     source.gsub!(/^\s*#\s*pragma\s+asm\s+.*?#\s*pragma\s+endasm/m, '')
@@ -84,66 +252,123 @@ class CMockHeaderParser
     # forward declared structs are removed before struct definitions so they don't mess up real thing later. we leave structs keywords in function prototypes
     source.gsub!(/^[\w\s]*struct[^;\{\}\(\)]+;/m, '')                                      # remove forward declared structs
     source.gsub!(/^[\w\s]*(enum|union|struct|typedef)[\w\s]*\{[^\}]+\}[\w\s\*\,]*;/m, '')  # remove struct, union, and enum definitions and typedefs with braces
-    source.gsub!(/(\W)(?:register|auto|static|restrict)(\W)/, '\1\2')                      # remove problem keywords
+    # remove problem keywords
+    source.gsub!(/(\W)(?:register|auto|restrict)(\W)/, '\1\2')
+    source.gsub!(/(\W)(?:static)(\W)/, '\1\2') unless cpp
+
     source.gsub!(/\s*=\s*['"a-zA-Z0-9_\.]+\s*/, '')                                        # remove default value statements from argument lists
     source.gsub!(/^(?:[\w\s]*\W)?typedef\W[^;]*/m, '')                                     # remove typedef statements
     source.gsub!(/\)(\w)/, ') \1')                                                         # add space between parenthese and alphanumeric
-    source.gsub!(/(^|\W+)(?:#{@c_strippables.join('|')})(?=$|\W+)/,'\1') unless @c_strippables.empty? # remove known attributes slated to be stripped
+    source.gsub!(/(^|\W+)(?:#{@c_strippables.join('|')})(?=$|\W+)/, '\1') unless @c_strippables.empty? # remove known attributes slated to be stripped
 
-    #scan standalone function pointers and remove them, because they can just be ignored
-    source.gsub!(/\w+\s*\(\s*\*\s*\w+\s*\)\s*\([^)]*\)\s*;/,';')
+    # scan standalone function pointers and remove them, because they can just be ignored
+    source.gsub!(/\w+\s*\(\s*\*\s*\w+\s*\)\s*\([^)]*\)\s*;/, ';')
 
-    #scan for functions which return function pointers, because they are a pain
-    source.gsub!(/([\w\s\*]+)\(*\(\s*\*([\w\s\*]+)\s*\(([\w\s\*,]*)\)\)\s*\(([\w\s\*,]*)\)\)*/) do |m|
-      functype = "cmock_#{@module_name}_func_ptr#{@typedefs.size + 1}"
-      @typedefs << "typedef #{$1.strip}(*#{functype})(#{$4});"
-      "#{functype} #{$2.strip}(#{$3});"
-    end
-
-    # remove nested pairs of braces because no function declarations will be inside of them (leave outer pair for function definition detection)
-    if (RUBY_VERSION.split('.')[0].to_i > 1)
-      #we assign a string first because (no joke) if Ruby 1.9.3 sees this line as a regex, it will crash.
-      r = "\\{([^\\{\\}]*|\\g<0>)*\\}"
-      source.gsub!(/#{r}/m, '{ }')
-    else
-      while source.gsub!(/\{[^\{\}]*\{[^\{\}]*\}[^\{\}]*\}/m, '{ }')
+    # scan for functions which return function pointers, because they are a pain
+    source.gsub!(/([\w\s\*]+)\(*\(\s*\*([\w\s\*]+)\s*\(([\w\s\*,]*)\)\)\s*\(([\w\s\*,]*)\)\)*/) do |_m|
+      functype = "cmock_#{parse_project[:module_name]}_func_ptr#{parse_project[:typedefs].size + 1}"
+      unless cpp # only collect once
+        parse_project[:typedefs] << "typedef #{Regexp.last_match(1).strip}(*#{functype})(#{Regexp.last_match(4)});"
+        "#{functype} #{Regexp.last_match(2).strip}(#{Regexp.last_match(3)});"
       end
     end
 
-    # remove function definitions by stripping off the arguments right now
-    source.gsub!(/\([^\)]*\)\s*\{[^\}]*\}/m, ";")
+    source = remove_nested_pairs_of_braces(source) unless cpp
 
-    #drop extra white space to make the rest go faster
+    if @treat_inlines == :include
+      # Functions having "{ }" at this point are/were inline functions,
+      # User wants them in so 'disguise' them as normal functions with the ";"
+      source.gsub!('{ }', ';')
+    end
+
+    # remove function definitions by stripping off the arguments right now
+    source.gsub!(/\([^\)]*\)\s*\{[^\}]*\}/m, ';')
+
+    # drop extra white space to make the rest go faster
     source.gsub!(/^\s+/, '')          # remove extra white space from beginning of line
     source.gsub!(/\s+$/, '')          # remove extra white space from end of line
     source.gsub!(/\s*\(\s*/, '(')     # remove extra white space from before left parens
     source.gsub!(/\s*\)\s*/, ')')     # remove extra white space from before right parens
     source.gsub!(/\s+/, ' ')          # remove remaining extra white space
 
-    #split lines on semicolons and remove things that are obviously not what we are looking for
-    src_lines = source.split(/\s*;\s*/).uniq
-    src_lines.delete_if {|line| line.strip.length == 0}                            # remove blank lines
-    src_lines.delete_if {|line| !(line =~ /[\w\s\*]+\(+\s*\*[\*\s]*[\w\s]+(?:\[[\w\s]*\]\s*)+\)+\s*\((?:[\w\s\*]*,?)*\s*\)/).nil?}     #remove function pointer arrays
-    if (@treat_externs == :include)
-      src_lines.delete_if {|line| !(line =~ /(?:^|\s+)(?:inline)\s+/).nil?}        # remove inline functions
-    else
-      src_lines.delete_if {|line| !(line =~ /(?:^|\s+)(?:extern|inline)\s+/).nil?} # remove inline and extern functions
+    # split lines on semicolons and remove things that are obviously not what we are looking for
+    src_lines = source.split(/\s*;\s*/)
+    src_lines = src_lines.uniq unless cpp # must retain closing braces for class/namespace
+    src_lines.delete_if { |line| line.strip.empty? } # remove blank lines
+    src_lines.delete_if { |line| !(line =~ /[\w\s\*]+\(+\s*\*[\*\s]*[\w\s]+(?:\[[\w\s]*\]\s*)+\)+\s*\((?:[\w\s\*]*,?)*\s*\)/).nil? } # remove function pointer arrays
+
+    unless @treat_externs == :include
+      src_lines.delete_if { |line| !(line =~ /(?:^|\s+)(?:extern)\s+/).nil? } # remove extern functions
     end
-    src_lines.delete_if {|line| line.empty? } #drop empty lines
+
+    unless @treat_inlines == :include
+      src_lines.delete_if { |line| !(line =~ /(?:^|\s+)(?:inline)\s+/).nil? } # remove inline functions
+    end
+
+    src_lines.delete_if(&:empty?) # drop empty lines
+  end
+
+  # Rudimentary C++ parser - does not handle all situations - e.g.:
+  #  * A namespace function appears after a class with private members (should be parsed)
+  #  * Anonymous namespace (shouldn't parse anything - no matter how nested - within it)
+  #  * A class nested within another class
+  def parse_cpp_functions(source)
+    funcs = []
+
+    ns = []
+    pub = false
+    source.each do |line|
+      # Search for namespace, class, opening and closing braces
+      line.scan(/(?:(?:\b(?:namespace|class)\s+(?:\S+)\s*)?{)|}/).each do |item|
+        if item == '}'
+          ns.pop
+        else
+          token = item.strip.sub(/\s+/, ' ')
+          ns << token
+
+          pub = false if token.start_with? 'class'
+          pub = true if token.start_with? 'namespace'
+        end
+      end
+
+      pub = true if line =~ /public:/
+      pub = false if line =~ /private:/ || line =~ /protected:/
+
+      # ignore non-public and non-static
+      next unless pub
+      next unless line =~ /\bstatic\b/
+
+      line.sub!(/^.*static/, '')
+      next unless line =~ @declaration_parse_matcher
+
+      tmp = ns.reject { |item| item == '{' }
+
+      # Identify class name, if any
+      cls = nil
+      if tmp[-1].start_with? 'class '
+        cls = tmp.pop.sub(/class (\S+) {/, '\1')
+      end
+
+      # Assemble list of namespaces
+      tmp.each { |item| item.sub!(/(?:namespace|class) (\S+) {/, '\1') }
+
+      funcs << [line.strip.gsub(/\s+/, ' '), tmp, cls]
+    end
+    funcs
   end
 
   def parse_functions(source)
     funcs = []
-    source.each {|line| funcs << line.strip.gsub(/\s+/, ' ') if (line =~ @declaration_parse_matcher)}
+    source.each { |line| funcs << line.strip.gsub(/\s+/, ' ') if line =~ @declaration_parse_matcher }
     if funcs.empty?
       case @when_no_prototypes
-        when :error
-          raise "ERROR: No function prototypes found!"
-        when :warn
-          puts "WARNING: No function prototypes found!" unless (@verbosity < 1)
+      when :error
+        raise 'ERROR: No function prototypes found!'
+      when :warn
+        puts 'WARNING: No function prototypes found!' unless @verbosity < 1
       end
     end
-    return funcs
+    funcs
   end
 
   def parse_type_and_name(arg)
@@ -151,8 +376,8 @@ class CMockHeaderParser
     # to remove 'const' only when it applies to the pointer itself, not when it
     # applies to the type pointed to.  For non-pointer types, remove any
     # occurrence of 'const'.
-    arg.gsub!(/(\w)\*/,'\1 *') # pull asterisks away from preceding word
-    arg.gsub!(/\*(\w)/,'* \1') # pull asterisks away from following word
+    arg.gsub!(/(\w)\*/, '\1 *') # pull asterisks away from preceding word
+    arg.gsub!(/\*(\w)/, '* \1') # pull asterisks away from following word
     arg_array = arg.split
     arg_info = divine_ptr_and_const(arg)
     arg_info[:name] = arg_array[-1]
@@ -177,15 +402,15 @@ class CMockHeaderParser
     end
 
     arg_info[:modifier] = attr_array.join(' ')
-    arg_info[:type] = type_array.join(' ').gsub(/\s+\*/,'*') # remove space before asterisks
-    return arg_info
+    arg_info[:type] = type_array.join(' ').gsub(/\s+\*/, '*') # remove space before asterisks
+    arg_info
   end
 
   def parse_args(arg_list)
     args = []
     arg_list.split(',').each do |arg|
       arg.strip!
-      return args if (arg =~ /^\s*((\.\.\.)|(void))\s*$/)   # we're done if we reach void by itself or ...
+      return args if arg =~ /^\s*((\.\.\.)|(void))\s*$/ # we're done if we reach void by itself or ...
 
       arg_info = parse_type_and_name(arg)
       arg_info.delete(:modifier)             # don't care about this
@@ -193,7 +418,7 @@ class CMockHeaderParser
 
       # in C, array arguments implicitly degrade to pointers
       # make the translation explicit here to simplify later logic
-      if @treat_as_array[arg_info[:type]] and not arg_info[:ptr?] then
+      if @treat_as_array[arg_info[:type]] && !(arg_info[:ptr?])
         arg_info[:type] = "#{@treat_as_array[arg_info[:type]]}*"
         arg_info[:type] = "const #{arg_info[:type]}" if arg_info[:const?]
         arg_info[:ptr?] = true
@@ -203,31 +428,35 @@ class CMockHeaderParser
     end
 
     # Try to find array pair in parameters following this pattern : <type> * <name>, <@array_size_type> <@array_size_name>
-    args.each_with_index {|val, index|
+    args.each_with_index do |val, index|
       next_index = index + 1
-      if (args.length > next_index)
-        if (val[:ptr?] == true and args[next_index][:name].match(@array_size_name) and @array_size_type.include?(args[next_index][:type]))
-          val[:array_data?] = true
-          args[next_index][:array_size?] = true
-        end
-      end
-    }
+      next unless args.length > next_index
 
-    return args
+      if (val[:ptr?] == true) && args[next_index][:name].match(@array_size_name) && @array_size_type.include?(args[next_index][:type])
+        val[:array_data?] = true
+        args[next_index][:array_size?] = true
+      end
+    end
+
+    args
   end
 
   def divine_ptr(arg)
     return false unless arg.include? '*'
     # treat "const char *" and similar as a string, not a pointer
     return false if /(^|\s)(const\s+)?char(\s+const)?\s*\*(?!.*\*)/ =~ arg
-    return true
+
+    true
   end
 
   def divine_const(arg)
     # a non-pointer arg containing "const" is a constant
     # an arg containing "const" before the last * is a pointer to a constant
-    return ( arg.include?('*') ? (/(^|\s|\*)const(\s(\w|\s)*)?\*(?!.*\*)/ =~ arg)
-                               : (/(^|\s)const(\s|$)/ =~ arg) ) ? true : false
+    if arg.include?('*') ? (/(^|\s|\*)const(\s(\w|\s)*)?\*(?!.*\*)/ =~ arg) : (/(^|\s)const(\s|$)/ =~ arg)
+      true
+    else
+      false
+    end
   end
 
   def divine_ptr_and_const(arg)
@@ -237,128 +466,158 @@ class CMockHeaderParser
     divination[:const?] = divine_const(arg)
 
     # an arg containing "const" after the last * is a constant pointer
-    divination[:const_ptr?] = (/\*(?!.*\*)\s*const(\s|$)/ =~ arg) ? true : false
+    divination[:const_ptr?] = /\*(?!.*\*)\s*const(\s|$)/ =~ arg ? true : false
 
-    return divination
+    divination
   end
 
-  def clean_args(arg_list)
-    if ((@local_as_void.include?(arg_list.strip)) or (arg_list.empty?))
-      return 'void'
+  def clean_args(arg_list, parse_project)
+    if @local_as_void.include?(arg_list.strip) || arg_list.empty?
+      'void'
     else
-      c=0
-      arg_list.gsub!(/(\w+)(?:\s*\[\s*\(*[\s\w+-]*\)*\s*\])+/,'*\1')  # magically turn brackets into asterisks, also match for parentheses that come from macros
-      arg_list.gsub!(/\s+\*/,'*')                                       # remove space to place asterisks with type (where they belong)
-      arg_list.gsub!(/\*(\w)/,'* \1')                                   # pull asterisks away from arg to place asterisks with type (where they belong)
+      c = 0
+      # magically turn brackets into asterisks, also match for parentheses that come from macros
+      arg_list.gsub!(/(\w+)(?:\s*\[[^\[\]]*\])+/, '*\1')
+      # remove space to place asterisks with type (where they belong)
+      arg_list.gsub!(/\s+\*/, '*')
+      # pull asterisks away from arg to place asterisks with type (where they belong)
+      arg_list.gsub!(/\*(\w)/, '* \1')
 
-      #scan argument list for function pointers and replace them with custom types
-      arg_list.gsub!(/([\w\s\*]+)\(+\s*\*[\*\s]*([\w\s]*)\s*\)+\s*\(((?:[\w\s\*]*,?)*)\s*\)*/) do |m|
-
-        functype = "cmock_#{@module_name}_func_ptr#{@typedefs.size + 1}"
-        funcret  = $1.strip
-        funcname = $2.strip
-        funcargs = $3.strip
+      # scan argument list for function pointers and replace them with custom types
+      arg_list.gsub!(/([\w\s\*]+)\(+\s*\*[\*\s]*([\w\s]*)\s*\)+\s*\(((?:[\w\s\*]*,?)*)\s*\)*/) do |_m|
+        functype = "cmock_#{parse_project[:module_name]}_func_ptr#{parse_project[:typedefs].size + 1}"
+        funcret  = Regexp.last_match(1).strip
+        funcname = Regexp.last_match(2).strip
+        funcargs = Regexp.last_match(3).strip
         funconst = ''
-        if (funcname.include? 'const')
-          funcname.gsub!('const','').strip!
+        if funcname.include? 'const'
+          funcname.gsub!('const', '').strip!
           funconst = 'const '
         end
-        @typedefs << "typedef #{funcret}(*#{functype})(#{funcargs});"
-        funcname = "cmock_arg#{c+=1}" if (funcname.empty?)
+        parse_project[:typedefs] << "typedef #{funcret}(*#{functype})(#{funcargs});"
+        funcname = "cmock_arg#{c += 1}" if funcname.empty?
         "#{functype} #{funconst}#{funcname}"
       end
 
-      #automatically name unnamed arguments (those that only had a type)
-      arg_list.split(/\s*,\s*/).map { |arg|
+      # scan argument list for function pointers with shorthand notation and replace them with custom types
+      arg_list.gsub!(/([\w\s\*]+)+\s+(\w+)\s*\(((?:[\w\s\*]*,?)*)\s*\)*/) do |_m|
+        functype = "cmock_#{parse_project[:module_name]}_func_ptr#{parse_project[:typedefs].size + 1}"
+        funcret  = Regexp.last_match(1).strip
+        funcname = Regexp.last_match(2).strip
+        funcargs = Regexp.last_match(3).strip
+        funconst = ''
+        if funcname.include? 'const'
+          funcname.gsub!('const', '').strip!
+          funconst = 'const '
+        end
+        parse_project[:typedefs] << "typedef #{funcret}(*#{functype})(#{funcargs});"
+        funcname = "cmock_arg#{c += 1}" if funcname.empty?
+        "#{functype} #{funconst}#{funcname}"
+      end
+
+      # automatically name unnamed arguments (those that only had a type)
+      arg_list.split(/\s*,\s*/).map do |arg|
         parts = (arg.split - ['struct', 'union', 'enum', 'const', 'const*'])
-        if ((parts.size < 2) or (parts[-1][-1].chr == '*') or (@standards.include?(parts[-1])))
-          "#{arg} cmock_arg#{c+=1}"
+        if (parts.size < 2) || (parts[-1][-1].chr == '*') || @standards.include?(parts[-1])
+          "#{arg} cmock_arg#{c += 1}"
         else
           arg
         end
-      }.join(', ')
+      end.join(', ')
     end
   end
 
-  def parse_declaration(declaration)
+  def parse_declaration(parse_project, declaration, namespace = [], classname = nil)
     decl = {}
+    decl[:namespace] = namespace
+    decl[:class] = classname
 
     regex_match = @declaration_parse_matcher.match(declaration)
     raise "Failed parsing function declaration: '#{declaration}'" if regex_match.nil?
 
-    #grab argument list
+    # grab argument list
     args = regex_match[2].strip
 
-    #process function attributes, return type, and name
+    # process function attributes, return type, and name
     parsed = parse_type_and_name(regex_match[1])
 
-    decl[:name] = parsed[:name]
+    # Record original name without scope prefix
+    decl[:unscoped_name] = parsed[:name]
+
+    # Prefix name with namespace scope (if any) and then class
+    decl[:name] = namespace.join('_')
+    unless classname.nil?
+      decl[:name] << '_' unless decl[:name].empty?
+      decl[:name] << classname
+    end
+    # Add original name to complete fully scoped name
+    decl[:name] << '_' unless decl[:name].empty?
+    decl[:name] << decl[:unscoped_name]
+
     decl[:modifier] = parsed[:modifier]
     unless parsed[:c_calling_convention].nil?
       decl[:c_calling_convention] = parsed[:c_calling_convention]
     end
 
     rettype = parsed[:type]
-    rettype = 'void' if (@local_as_void.include?(rettype.strip))
+    rettype = 'void' if @local_as_void.include?(rettype.strip)
     decl[:return] = { :type       => rettype,
                       :name       => 'cmock_to_return',
                       :str        => "#{rettype} cmock_to_return",
                       :void?      => (rettype == 'void'),
-                      :ptr?       => parsed[:ptr?],
-                      :const?     => parsed[:const?],
-                      :const_ptr? => parsed[:const_ptr?]
-                    }
+                      :ptr?       => parsed[:ptr?]       || false,
+                      :const?     => parsed[:const?]     || false,
+                      :const_ptr? => parsed[:const_ptr?] || false }
 
-    #remove default argument statements from mock definitions
+    # remove default argument statements from mock definitions
     args.gsub!(/=\s*[a-zA-Z0-9_\.]+\s*/, ' ')
 
-    #check for var args
-    if (args =~ /\.\.\./)
-      decl[:var_arg] = args.match( /[\w\s]*\.\.\./ ).to_s.strip
-      if (args =~ /\,[\w\s]*\.\.\./)
-        args = args.gsub!(/\,[\w\s]*\.\.\./,'')
-      else
-        args = 'void'
-      end
+    # check for var args
+    if args =~ /\.\.\./
+      decl[:var_arg] = args.match(/[\w\s]*\.\.\./).to_s.strip
+      args = if args =~ /\,[\w\s]*\.\.\./
+               args.gsub!(/\,[\w\s]*\.\.\./, '')
+             else
+               'void'
+             end
     else
       decl[:var_arg] = nil
     end
-    args = clean_args(args)
+    args = clean_args(args, parse_project)
     decl[:args_string] = args
     decl[:args] = parse_args(args)
-    decl[:args_call] = decl[:args].map{|a| a[:name]}.join(', ')
-    decl[:contains_ptr?] = decl[:args].inject(false) {|ptr, arg| arg[:ptr?] ? true : ptr }
+    decl[:args_call] = decl[:args].map { |a| a[:name] }.join(', ')
+    decl[:contains_ptr?] = decl[:args].inject(false) { |ptr, arg| arg[:ptr?] ? true : ptr }
 
-    if (decl[:return][:type].nil?   or decl[:name].nil?   or decl[:args].nil? or
-        decl[:return][:type].empty? or decl[:name].empty?)
-      raise "Failed Parsing Declaration Prototype!\n" +
-        "  declaration: '#{declaration}'\n" +
-        "  modifier: '#{decl[:modifier]}'\n" +
-        "  return: #{prototype_inspect_hash(decl[:return])}\n" +
-        "  function: '#{decl[:name]}'\n" +
-        "  args: #{prototype_inspect_array_of_hashes(decl[:args])}\n"
+    if decl[:return][:type].nil? || decl[:name].nil? || decl[:args].nil? ||
+       decl[:return][:type].empty? || decl[:name].empty?
+      raise "Failed Parsing Declaration Prototype!\n" \
+            "  declaration: '#{declaration}'\n" \
+            "  modifier: '#{decl[:modifier]}'\n" \
+            "  return: #{prototype_inspect_hash(decl[:return])}\n" \
+            "  function: '#{decl[:name]}'\n" \
+            "  args: #{prototype_inspect_array_of_hashes(decl[:args])}\n"
     end
 
-    return decl
+    decl
   end
 
   def prototype_inspect_hash(hash)
     pairs = []
-    hash.each_pair { |name, value| pairs << ":#{name} => #{"'" if (value.class == String)}#{value}#{"'" if (value.class == String)}" }
-    return "{#{pairs.join(', ')}}"
+    hash.each_pair { |name, value| pairs << ":#{name} => #{"'" if value.class == String}#{value}#{"'" if value.class == String}" }
+    "{#{pairs.join(', ')}}"
   end
 
   def prototype_inspect_array_of_hashes(array)
     hashes = []
     array.each { |hash| hashes << prototype_inspect_hash(hash) }
-    case (array.size)
+    case array.size
     when 0
-      return "[]"
+      return '[]'
     when 1
       return "[#{hashes[0]}]"
     else
       return "[\n    #{hashes.join("\n    ")}\n  ]\n"
     end
   end
-
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_plugin_manager.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_plugin_manager.rb
index cc5ced2ad..342014e22 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_plugin_manager.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_plugin_manager.rb
@@ -4,10 +4,7 @@
 #   [Released under MIT License. Please refer to license.txt for details]
 # ==========================================
 
-require 'thread'
-
 class CMockPluginManager
-
   attr_accessor :plugins
 
   def initialize(config, utils)
@@ -15,41 +12,39 @@ class CMockPluginManager
     plugins_to_load = [:expect, config.plugins].flatten.uniq.compact
     plugins_to_load.each do |plugin|
       plugin_name = plugin.to_s
-      object_name = "CMockGeneratorPlugin" + camelize(plugin_name)
-      self.class.plugin_require_mutex.synchronize { load_plugin(plugin_name, object_name, config, utils) }
+      object_name = 'CMockGeneratorPlugin' + camelize(plugin_name)
+      self.class.mutex.synchronize { load_plugin(plugin_name, object_name, config, utils) }
     end
-    @plugins.sort! {|a,b| a.priority <=> b.priority }
+    @plugins.sort! { |a, b| a.priority <=> b.priority }
   end
 
-  def run(method, args=nil)
+  def run(method, args = nil)
     if args.nil?
-      return @plugins.collect{ |plugin| plugin.send(method) if plugin.respond_to?(method) }.flatten.join
+      @plugins.collect { |plugin| plugin.send(method) if plugin.respond_to?(method) }.flatten.join
     else
-      return @plugins.collect{ |plugin| plugin.send(method, args) if plugin.respond_to?(method) }.flatten.join
+      @plugins.collect { |plugin| plugin.send(method, args) if plugin.respond_to?(method) }.flatten.join
     end
   end
 
   def camelize(lower_case_and_underscored_word)
-    lower_case_and_underscored_word.gsub(/\/(.?)/) { "::" + $1.upcase }.gsub(/(^|_)(.)/) { $2.upcase }
+    lower_case_and_underscored_word.gsub(/\/(.?)/) { '::' + Regexp.last_match(1).upcase }.gsub(/(^|_)(.)/) { Regexp.last_match(2).upcase }
   end
-  
-  private
-  
-  def self.plugin_require_mutex
+
+  def self.mutex
     @mutex ||= Mutex.new
   end
-  
+
+  private
+
   def load_plugin(plugin_name, object_name, config, utils)
-    begin
-      unless (Object.const_defined? object_name)
-        file_name = "#{File.expand_path(File.dirname(__FILE__))}/cmock_generator_plugin_#{plugin_name.downcase}.rb"
-        require file_name
-      end
-      class_name = Object.const_get(object_name)
-      @plugins << class_name.new(config, utils)
-    rescue
-      file_name = "#{File.expand_path(File.dirname(__FILE__))}/cmock_generator_plugin_#{plugin_name.downcase}.rb"
-      raise "ERROR: CMock unable to load plugin '#{plugin_name}' '#{object_name}' #{file_name}"
+    unless Object.const_defined? object_name
+      file_name = "#{__dir__}/cmock_generator_plugin_#{plugin_name.downcase}.rb"
+      require file_name
     end
+    class_name = Object.const_get(object_name)
+    @plugins << class_name.new(config, utils)
+  rescue StandardError
+    file_name = "#{__dir__}/cmock_generator_plugin_#{plugin_name.downcase}.rb"
+    raise "ERROR: CMock unable to load plugin '#{plugin_name}' '#{object_name}' #{file_name}"
   end
 end
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_unityhelper_parser.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_unityhelper_parser.rb
index c22db7aa9..9f4beb770 100644
--- a/test/vendor/ceedling/vendor/cmock/lib/cmock_unityhelper_parser.rb
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_unityhelper_parser.rb
@@ -2,74 +2,76 @@
 #   CMock Project - Automatic Mock Generation for C
 #   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
 #   [Released under MIT License. Please refer to license.txt for details]
-# ========================================== 
+# ==========================================
 
 class CMockUnityHelperParser
-  
   attr_accessor :c_types
-  
+
   def initialize(config)
     @config = config
     @fallback = @config.plugins.include?(:array) ? 'UNITY_TEST_ASSERT_EQUAL_MEMORY_ARRAY' : 'UNITY_TEST_ASSERT_EQUAL_MEMORY'
-    @c_types = map_C_types.merge(import_source)
+    @c_types = map_c_types.merge(import_source)
   end
 
   def get_helper(ctype)
-    lookup = ctype.gsub(/(?:^|(\S?)(\s*)|(\W))const(?:$|(\s*)(\S)|(\W))/,'\1\3\5\6').strip.gsub(/\s+/,'_')
-    return [@c_types[lookup], ''] if (@c_types[lookup])
-    if (lookup =~ /\*$/)
-      lookup = lookup.gsub(/\*$/,'')
-      return [@c_types[lookup], '*'] if (@c_types[lookup])
+    lookup = ctype.gsub(/(?:^|(\S?)(\s*)|(\W))const(?:$|(\s*)(\S)|(\W))/, '\1\3\5\6').strip.gsub(/\s+/, '_')
+    return [@c_types[lookup], ''] if @c_types[lookup]
+
+    if lookup =~ /\*$/
+      lookup = lookup.gsub(/\*$/, '')
+      return [@c_types[lookup], '*'] if @c_types[lookup]
     else
-      lookup = lookup + '*'
-      return [@c_types[lookup], '&'] if (@c_types[lookup])
+      lookup += '*'
+      return [@c_types[lookup], '&'] if @c_types[lookup]
     end
-    return ['UNITY_TEST_ASSERT_EQUAL_PTR', ''] if (ctype =~ /cmock_\w+_ptr\d+/)
+    return ['UNITY_TEST_ASSERT_EQUAL_PTR', ''] if ctype =~ /cmock_\w+_ptr\d+/
     raise("Don't know how to test #{ctype} and memory tests are disabled!") unless @config.memcmp_if_unknown
-    return (lookup =~ /\*$/) ? [@fallback, '&'] : [@fallback, '']
+
+    lookup =~ /\*$/ ? [@fallback, '&'] : [@fallback, '']
   end
-  
+
   private ###########################
-  
-  def map_C_types
+
+  def map_c_types
     c_types = {}
     @config.treat_as.each_pair do |ctype, expecttype|
-      c_type = ctype.gsub(/\s+/,'_')
-      if (expecttype =~ /\*/)
-        c_types[c_type] = "UNITY_TEST_ASSERT_EQUAL_#{expecttype.gsub(/\*/,'')}_ARRAY"
+      c_type = ctype.gsub(/\s+/, '_')
+      if expecttype =~ /\*/
+        c_types[c_type] = "UNITY_TEST_ASSERT_EQUAL_#{expecttype.delete('*')}_ARRAY"
       else
         c_types[c_type] = "UNITY_TEST_ASSERT_EQUAL_#{expecttype}"
-        c_types[c_type+'*'] ||= "UNITY_TEST_ASSERT_EQUAL_#{expecttype}_ARRAY"
+        c_types[c_type + '*'] ||= "UNITY_TEST_ASSERT_EQUAL_#{expecttype}_ARRAY"
       end
     end
     c_types
   end
-  
+
   def import_source
     source = @config.load_unity_helper
     return {} if source.nil?
+
     c_types = {}
-    source = source.gsub(/\/\/.*$/, '') #remove line comments
-    source = source.gsub(/\/\*.*?\*\//m, '') #remove block comments
-     
-    #scan for comparison helpers
-    match_regex = Regexp.new('^\s*#define\s+(UNITY_TEST_ASSERT_EQUAL_(\w+))\s*\(' + Array.new(4,'\s*\w+\s*').join(',') + '\)')
+    source = source.gsub(/\/\/.*$/, '') # remove line comments
+    source = source.gsub(/\/\*.*?\*\//m, '') # remove block comments
+
+    # scan for comparison helpers
+    match_regex = Regexp.new('^\s*#define\s+(UNITY_TEST_ASSERT_EQUAL_(\w+))\s*\(' + Array.new(4, '\s*\w+\s*').join(',') + '\)')
     pairs = source.scan(match_regex).flatten.compact
-    (pairs.size/2).times do |i|
-      expect = pairs[i*2]
-      ctype = pairs[(i*2)+1]
-      c_types[ctype] = expect unless expect.include?("_ARRAY")
+    (pairs.size / 2).times do |i|
+      expect = pairs[i * 2]
+      ctype = pairs[(i * 2) + 1]
+      c_types[ctype] = expect unless expect.include?('_ARRAY')
     end
-      
-    #scan for array variants of those helpers
-    match_regex = Regexp.new('^\s*#define\s+(UNITY_TEST_ASSERT_EQUAL_(\w+_ARRAY))\s*\(' + Array.new(5,'\s*\w+\s*').join(',') + '\)')
+
+    # scan for array variants of those helpers
+    match_regex = Regexp.new('^\s*#define\s+(UNITY_TEST_ASSERT_EQUAL_(\w+_ARRAY))\s*\(' + Array.new(5, '\s*\w+\s*').join(',') + '\)')
     pairs = source.scan(match_regex).flatten.compact
-    (pairs.size/2).times do |i|
-      expect = pairs[i*2]
-      ctype = pairs[(i*2)+1]
-      c_types[ctype.gsub('_ARRAY','*')] = expect
+    (pairs.size / 2).times do |i|
+      expect = pairs[i * 2]
+      ctype = pairs[(i * 2) + 1]
+      c_types[ctype.gsub('_ARRAY', '*')] = expect
     end
-    
+
     c_types
   end
 end
diff --git a/test/vendor/ceedling/vendor/cmock/release/build.info b/test/vendor/ceedling/vendor/cmock/release/build.info
deleted file mode 100644
index a62fe1172..000000000
--- a/test/vendor/ceedling/vendor/cmock/release/build.info
+++ /dev/null
@@ -1,2 +0,0 @@
-217
-
diff --git a/test/vendor/ceedling/vendor/cmock/release/version.info b/test/vendor/ceedling/vendor/cmock/release/version.info
deleted file mode 100644
index 1b6799f80..000000000
--- a/test/vendor/ceedling/vendor/cmock/release/version.info
+++ /dev/null
@@ -1,2 +0,0 @@
-2.4.6
-
diff --git a/test/vendor/ceedling/vendor/cmock/src/cmock.c b/test/vendor/ceedling/vendor/cmock/src/cmock.c
index 5e5cb6c72..88f2c2b25 100644
--- a/test/vendor/ceedling/vendor/cmock/src/cmock.c
+++ b/test/vendor/ceedling/vendor/cmock/src/cmock.c
@@ -6,7 +6,7 @@
 
 #include "cmock.h"
 
-//public constants to be used by mocks
+/* public constants to be used by mocks */
 const char* CMockStringOutOfMemory = "CMock has run out of memory. Please allocate more.";
 const char* CMockStringCalledMore  = "Called more times than expected.";
 const char* CMockStringCalledLess  = "Called fewer times than expected.";
@@ -19,7 +19,7 @@ const char* CMockStringPtrIsNULL   = "Pointer is NULL.";
 const char* CMockStringExpNULL     = "Expected NULL.";
 const char* CMockStringMismatch    = "Function called with unexpected argument value.";
 
-//private variables
+/* private variables */
 #ifdef CMOCK_MEM_DYNAMIC
 static unsigned char*         CMock_Guts_Buffer = NULL;
 static CMOCK_MEM_INDEX_TYPE   CMock_Guts_BufferSize = CMOCK_MEM_ALIGN_SIZE;
@@ -30,37 +30,37 @@ static CMOCK_MEM_INDEX_TYPE   CMock_Guts_BufferSize = CMOCK_MEM_SIZE + CMOCK_MEM
 static CMOCK_MEM_INDEX_TYPE   CMock_Guts_FreePtr = CMOCK_MEM_ALIGN_SIZE;
 #endif
 
-//-------------------------------------------------------
-// CMock_Guts_MemNew
-//-------------------------------------------------------
+/*-------------------------------------------------------
+ * CMock_Guts_MemNew
+ *-------------------------------------------------------*/
 CMOCK_MEM_INDEX_TYPE CMock_Guts_MemNew(CMOCK_MEM_INDEX_TYPE size)
 {
   CMOCK_MEM_INDEX_TYPE index;
 
-  //verify arguments valid (we must be allocating space for at least 1 byte, and the existing chain must be in memory somewhere)
+  /* verify arguments valid (we must be allocating space for at least 1 byte, and the existing chain must be in memory somewhere) */
   if (size < 1)
     return CMOCK_GUTS_NONE;
 
-  //verify we have enough room
+  /* verify we have enough room */
   size = size + CMOCK_MEM_INDEX_SIZE;
   if (size & CMOCK_MEM_ALIGN_MASK)
     size = (size + CMOCK_MEM_ALIGN_MASK) & ~CMOCK_MEM_ALIGN_MASK;
   if ((CMock_Guts_BufferSize - CMock_Guts_FreePtr) < size)
   {
 #ifndef CMOCK_MEM_DYNAMIC
-    return CMOCK_GUTS_NONE; // nothing we can do; our static buffer is out of memory
+    return CMOCK_GUTS_NONE; /* nothing we can do; our static buffer is out of memory */
 #else
-    // our dynamic buffer does not have enough room; request more via realloc()
+    /* our dynamic buffer does not have enough room; request more via realloc() */
     CMOCK_MEM_INDEX_TYPE new_buffersize = CMock_Guts_BufferSize + CMOCK_MEM_SIZE + size;
     unsigned char* new_buffer = realloc(CMock_Guts_Buffer, (size_t)new_buffersize);
     if (new_buffer == NULL)
-      return CMOCK_GUTS_NONE; // realloc() failed; out of memory
+      return CMOCK_GUTS_NONE; /* realloc() failed; out of memory */
     CMock_Guts_Buffer = new_buffer;
     CMock_Guts_BufferSize = new_buffersize;
 #endif
   }
 
-  //determine where we're putting this new block, and init its pointer to be the end of the line
+  /* determine where we're putting this new block, and init its pointer to be the end of the line */
   index = CMock_Guts_FreePtr + CMOCK_MEM_INDEX_SIZE;
   *(CMOCK_MEM_INDEX_TYPE*)(&CMock_Guts_Buffer[CMock_Guts_FreePtr]) = CMOCK_GUTS_NONE;
   CMock_Guts_FreePtr += size;
@@ -68,9 +68,9 @@ CMOCK_MEM_INDEX_TYPE CMock_Guts_MemNew(CMOCK_MEM_INDEX_TYPE size)
   return index;
 }
 
-//-------------------------------------------------------
-// CMock_Guts_MemChain
-//-------------------------------------------------------
+/*-------------------------------------------------------
+ * CMock_Guts_MemChain
+ *-------------------------------------------------------*/
 CMOCK_MEM_INDEX_TYPE CMock_Guts_MemChain(CMOCK_MEM_INDEX_TYPE root_index, CMOCK_MEM_INDEX_TYPE obj_index)
 {
   CMOCK_MEM_INDEX_TYPE index;
@@ -80,12 +80,12 @@ CMOCK_MEM_INDEX_TYPE CMock_Guts_MemChain(CMOCK_MEM_INDEX_TYPE root_index, CMOCK_
 
   if (root_index == CMOCK_GUTS_NONE)
   {
-    //if there is no root currently, we return this object as the root of the chain
+    /* if there is no root currently, we return this object as the root of the chain */
     return obj_index;
   }
   else
   {
-    //reject illegal nodes
+    /* reject illegal nodes */
     if ((root_index < CMOCK_MEM_ALIGN_SIZE) || (root_index >= CMock_Guts_FreePtr))
     {
       return CMOCK_GUTS_NONE;
@@ -98,7 +98,7 @@ CMOCK_MEM_INDEX_TYPE CMock_Guts_MemChain(CMOCK_MEM_INDEX_TYPE root_index, CMOCK_
     root = (void*)(&CMock_Guts_Buffer[root_index]);
     obj  = (void*)(&CMock_Guts_Buffer[obj_index]);
 
-    //find the end of the existing chain and add us
+    /* find the end of the existing chain and add us */
     next = root;
     do {
       index = *(CMOCK_MEM_INDEX_TYPE*)((CMOCK_MEM_PTR_AS_INT)next - CMOCK_MEM_INDEX_SIZE);
@@ -112,21 +112,21 @@ CMOCK_MEM_INDEX_TYPE CMock_Guts_MemChain(CMOCK_MEM_INDEX_TYPE root_index, CMOCK_
   }
 }
 
-//-------------------------------------------------------
-// CMock_Guts_MemNext
-//-------------------------------------------------------
+/*-------------------------------------------------------
+ * CMock_Guts_MemNext
+ *-------------------------------------------------------*/
 CMOCK_MEM_INDEX_TYPE CMock_Guts_MemNext(CMOCK_MEM_INDEX_TYPE previous_item_index)
 {
   CMOCK_MEM_INDEX_TYPE index;
   void* previous_item;
 
-  //There is nothing "next" if the pointer isn't from our buffer
+  /* There is nothing "next" if the pointer isn't from our buffer */
   if ((previous_item_index < CMOCK_MEM_ALIGN_SIZE) || (previous_item_index  >= CMock_Guts_FreePtr))
     return CMOCK_GUTS_NONE;
   previous_item = (void*)(&CMock_Guts_Buffer[previous_item_index]);
 
-  //if the pointer is good, then use it to look up the next index
-  //(we know the first element always goes in zero, so NEXT must always be > 1)
+  /* if the pointer is good, then use it to look up the next index
+   * (we know the first element always goes in zero, so NEXT must always be > 1) */
   index = *(CMOCK_MEM_INDEX_TYPE*)((CMOCK_MEM_PTR_AS_INT)previous_item - CMOCK_MEM_INDEX_SIZE);
   if ((index > 1) && (index < CMock_Guts_FreePtr))
     return index;
@@ -134,9 +134,9 @@ CMOCK_MEM_INDEX_TYPE CMock_Guts_MemNext(CMOCK_MEM_INDEX_TYPE previous_item_index
     return CMOCK_GUTS_NONE;
 }
 
-//-------------------------------------------------------
-// CMock_Guts_MemEndOfChain
-//-------------------------------------------------------
+/*-------------------------------------------------------
+ * CMock_Guts_MemEndOfChain
+ *-------------------------------------------------------*/
 CMOCK_MEM_INDEX_TYPE CMock_Guts_MemEndOfChain(CMOCK_MEM_INDEX_TYPE root_index)
 {
   CMOCK_MEM_INDEX_TYPE index = root_index;
@@ -152,9 +152,9 @@ CMOCK_MEM_INDEX_TYPE CMock_Guts_MemEndOfChain(CMOCK_MEM_INDEX_TYPE root_index)
   return index;
 }
 
-//-------------------------------------------------------
-// CMock_GetAddressFor
-//-------------------------------------------------------
+/*-------------------------------------------------------
+ * CMock_GetAddressFor
+ *-------------------------------------------------------*/
 void* CMock_Guts_GetAddressFor(CMOCK_MEM_INDEX_TYPE index)
 {
   if ((index >= CMOCK_MEM_ALIGN_SIZE) && (index < CMock_Guts_FreePtr))
@@ -167,41 +167,41 @@ void* CMock_Guts_GetAddressFor(CMOCK_MEM_INDEX_TYPE index)
   }
 }
 
-//-------------------------------------------------------
-// CMock_Guts_MemBytesCapacity
-//-------------------------------------------------------
+/*-------------------------------------------------------
+ * CMock_Guts_MemBytesCapacity
+ *-------------------------------------------------------*/
 CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesCapacity(void)
 {
   return (sizeof(CMock_Guts_Buffer) - CMOCK_MEM_ALIGN_SIZE);
 }
 
-//-------------------------------------------------------
-// CMock_Guts_MemBytesFree
-//-------------------------------------------------------
+/*-------------------------------------------------------
+ * CMock_Guts_MemBytesFree
+ *-------------------------------------------------------*/
 CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesFree(void)
 {
   return CMock_Guts_BufferSize - CMock_Guts_FreePtr;
 }
 
-//-------------------------------------------------------
-// CMock_Guts_MemBytesUsed
-//-------------------------------------------------------
+/*-------------------------------------------------------
+ * CMock_Guts_MemBytesUsed
+ *-------------------------------------------------------*/
 CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesUsed(void)
 {
   return CMock_Guts_FreePtr - CMOCK_MEM_ALIGN_SIZE;
 }
 
-//-------------------------------------------------------
-// CMock_Guts_MemFreeAll
-//-------------------------------------------------------
+/*-------------------------------------------------------
+ * CMock_Guts_MemFreeAll
+ *-------------------------------------------------------*/
 void CMock_Guts_MemFreeAll(void)
 {
-  CMock_Guts_FreePtr = CMOCK_MEM_ALIGN_SIZE; //skip the very beginning
+  CMock_Guts_FreePtr = CMOCK_MEM_ALIGN_SIZE; /* skip the very beginning */
 }
 
-//-------------------------------------------------------
-// CMock_Guts_MemFreeFinal
-//-------------------------------------------------------
+/*-------------------------------------------------------
+ * CMock_Guts_MemFreeFinal
+ *-------------------------------------------------------*/
 void CMock_Guts_MemFreeFinal(void)
 {
   CMock_Guts_FreePtr = CMOCK_MEM_ALIGN_SIZE;
diff --git a/test/vendor/ceedling/vendor/cmock/src/cmock.h b/test/vendor/ceedling/vendor/cmock/src/cmock.h
index e96546dab..45bab1829 100644
--- a/test/vendor/ceedling/vendor/cmock/src/cmock.h
+++ b/test/vendor/ceedling/vendor/cmock/src/cmock.h
@@ -11,30 +11,37 @@
 
 #define CMOCK_VERSION_MAJOR    2
 #define CMOCK_VERSION_MINOR    5
-#define CMOCK_VERSION_BUILD    0
+#define CMOCK_VERSION_BUILD    4
 #define CMOCK_VERSION          ((CMOCK_VERSION_MAJOR << 16) | (CMOCK_VERSION_MINOR << 8) | CMOCK_VERSION_BUILD)
 
-//should be big enough to index full range of CMOCK_MEM_MAX
+/* should be big enough to index full range of CMOCK_MEM_MAX */
 #ifndef CMOCK_MEM_INDEX_TYPE
-#define CMOCK_MEM_INDEX_TYPE  unsigned int
+#include <stddef.h>
+#define CMOCK_MEM_INDEX_TYPE  size_t
 #endif
 
 #define CMOCK_GUTS_NONE   (0)
 
-//-------------------------------------------------------
-// Memory API
-//-------------------------------------------------------
+#if defined __GNUC__
+#    define CMOCK_FUNCTION_ATTR(a) __attribute__((a))
+#else
+#    define CMOCK_FUNCTION_ATTR(a) /* ignore */
+#endif
+
+/*-------------------------------------------------------
+ * Memory API
+ *-------------------------------------------------------*/
 CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemNew(CMOCK_MEM_INDEX_TYPE size);
 CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemChain(CMOCK_MEM_INDEX_TYPE root_index, CMOCK_MEM_INDEX_TYPE obj_index);
-CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemNext(CMOCK_MEM_INDEX_TYPE previous_item_index);
-CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemEndOfChain(CMOCK_MEM_INDEX_TYPE root_index);
+CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemNext(CMOCK_MEM_INDEX_TYPE previous_item_index) CMOCK_FUNCTION_ATTR(pure);
+CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemEndOfChain(CMOCK_MEM_INDEX_TYPE root_index) CMOCK_FUNCTION_ATTR(pure);
 
-void*                 CMock_Guts_GetAddressFor(CMOCK_MEM_INDEX_TYPE index);
+void*                 CMock_Guts_GetAddressFor(CMOCK_MEM_INDEX_TYPE index) CMOCK_FUNCTION_ATTR(pure);
 
-CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesCapacity(void);
-CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemBytesFree(void);
-CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemBytesUsed(void);
+CMOCK_MEM_INDEX_TYPE CMock_Guts_MemBytesCapacity(void) CMOCK_FUNCTION_ATTR(const);
+CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemBytesFree(void) CMOCK_FUNCTION_ATTR(pure);
+CMOCK_MEM_INDEX_TYPE  CMock_Guts_MemBytesUsed(void) CMOCK_FUNCTION_ATTR(pure);
 void                  CMock_Guts_MemFreeAll(void);
 void                  CMock_Guts_MemFreeFinal(void);
 
-#endif //CMOCK_FRAMEWORK
+#endif /* end of CMOCK_FRAMEWORK_H */
diff --git a/test/vendor/ceedling/vendor/cmock/src/cmock_internals.h b/test/vendor/ceedling/vendor/cmock/src/cmock_internals.h
index ae2e4962f..56fb33b1a 100644
--- a/test/vendor/ceedling/vendor/cmock/src/cmock_internals.h
+++ b/test/vendor/ceedling/vendor/cmock/src/cmock_internals.h
@@ -9,7 +9,7 @@
 
 #include "unity.h"
 
-//These are constants that the generated mocks have access to
+/* These are constants that the generated mocks have access to */
 extern const char* CMockStringOutOfMemory;
 extern const char* CMockStringCalledMore;
 extern const char* CMockStringCalledLess;
@@ -22,8 +22,8 @@ extern const char* CMockStringPtrIsNULL;
 extern const char* CMockStringExpNULL;
 extern const char* CMockStringMismatch;
 
-//define CMOCK_MEM_DYNAMIC to grab memory as needed with malloc
-//when you do that, CMOCK_MEM_SIZE is used for incremental size instead of total
+/* define CMOCK_MEM_DYNAMIC to grab memory as needed with malloc
+ * when you do that, CMOCK_MEM_SIZE is used for incremental size instead of total */
 #ifdef CMOCK_MEM_STATIC
 #undef CMOCK_MEM_DYNAMIC
 #endif
@@ -32,7 +32,7 @@ extern const char* CMockStringMismatch;
 #include <stdlib.h>
 #endif
 
-//this is used internally during pointer arithmetic. make sure this type is the same size as the target's pointer type
+/* this is used internally during pointer arithmetic. make sure this type is the same size as the target's pointer type */
 #ifndef CMOCK_MEM_PTR_AS_INT
 #ifdef UNITY_POINTER_WIDTH
 #ifdef UNITY_INT_WIDTH
@@ -60,7 +60,7 @@ extern const char* CMockStringMismatch;
 #define CMOCK_MEM_PTR_AS_INT unsigned long
 #endif
 
-//0 for no alignment, 1 for 16-bit, 2 for 32-bit, 3 for 64-bit
+/* 0 for no alignment, 1 for 16-bit, 2 for 32-bit, 3 for 64-bit */
 #ifndef CMOCK_MEM_ALIGN
   #ifdef UNITY_LONG_WIDTH
     #if (UNITY_LONG_WIDTH == 16)
@@ -77,15 +77,15 @@ extern const char* CMockStringMismatch;
   #endif
 #endif
 
-//amount of memory to allow cmock to use in its internal heap
+/* amount of memory to allow cmock to use in its internal heap */
 #ifndef CMOCK_MEM_SIZE
 #define CMOCK_MEM_SIZE (32768)
 #endif
 
-//automatically calculated defs for easier reading
+/* automatically calculated defs for easier reading */
 #define CMOCK_MEM_ALIGN_SIZE  (CMOCK_MEM_INDEX_TYPE)(1u << CMOCK_MEM_ALIGN)
 #define CMOCK_MEM_ALIGN_MASK  (CMOCK_MEM_INDEX_TYPE)(CMOCK_MEM_ALIGN_SIZE - 1)
 #define CMOCK_MEM_INDEX_SIZE  (CMOCK_MEM_INDEX_TYPE)(CMOCK_MEM_PTR_AS_INT)((sizeof(CMOCK_MEM_INDEX_TYPE) > CMOCK_MEM_ALIGN_SIZE) ? sizeof(CMOCK_MEM_INDEX_TYPE) : CMOCK_MEM_ALIGN_SIZE)
 
 
-#endif //CMOCK_FRAMEWORK_INTERNALS
+#endif /* end of CMOCK_FRAMEWORK_INTERNALS_H */
diff --git a/test/vendor/ceedling/vendor/cmock/src/meson.build b/test/vendor/ceedling/vendor/cmock/src/meson.build
index e375e81a1..c03c4e5bb 100644
--- a/test/vendor/ceedling/vendor/cmock/src/meson.build
+++ b/test/vendor/ceedling/vendor/cmock/src/meson.build
@@ -1,17 +1,12 @@
-###################################################################################
-#                                                                                 #
-# NAME: meson.build                                                               #
-#                                                                                 #
-# AUTHOR: Mike Karlesky, Mark VanderVoord, Greg Williams.                         #
-# WRITTEN BY: Michael Brockus.                                                    #
-#                                                                                 #
-# License: MIT                                                                    #
-#                                                                                 #
-###################################################################################
-
+#
+# build script written by : Michael Brockus.
+# github repo author: Mike Karlesky, Mark VanderVoord, Greg Williams.
+#
+# license: MIT
+#
 cmock_dir = include_directories('.')
 
 cmock_lib = static_library(meson.project_name(), 
-    sources: ['cmock.c'],
+    files('cmock.c'),
     dependencies: [unity_dep],
     include_directories: cmock_dir)
diff --git a/test/vendor/ceedling/vendor/deep_merge/lib/deep_merge.rb b/test/vendor/ceedling/vendor/deep_merge/lib/deep_merge.rb
deleted file mode 100644
index 4c4b7610b..000000000
--- a/test/vendor/ceedling/vendor/deep_merge/lib/deep_merge.rb
+++ /dev/null
@@ -1,211 +0,0 @@
-module DeepMerge
-
-  MAJOR_VERSION = 0
-  MINOR_VERSION = 1
-  FIX_VERSION = 0
-  VERSION = "#{MAJOR_VERSION}.#{MINOR_VERSION}.#{FIX_VERSION}"
-
-  class InvalidParameter < StandardError; end
-  
-  DEFAULT_FIELD_KNOCKOUT_PREFIX = '--'
-
-  module DeepMergeHash
-    # ko_hash_merge! will merge and knockout elements prefixed with DEFAULT_FIELD_KNOCKOUT_PREFIX
-    def ko_deep_merge!(source, options = {})
-      default_opts = {:knockout_prefix => "--", :preserve_unmergeables => false}
-      DeepMerge::deep_merge!(source, self, default_opts.merge(options))
-    end
-
-    # deep_merge! will merge and overwrite any unmergeables in destination hash
-    def deep_merge!(source, options = {})
-      default_opts = {:preserve_unmergeables => false}
-      DeepMerge::deep_merge!(source, self, default_opts.merge(options))
-    end
-
-    # deep_merge will merge and skip any unmergeables in destination hash
-    def deep_merge(source, options = {})
-      default_opts = {:preserve_unmergeables => true}
-      DeepMerge::deep_merge!(source, self, default_opts.merge(options))
-    end
-
-  end # DeepMergeHashExt
-  
-  # Deep Merge core documentation.
-  # deep_merge! method permits merging of arbitrary child elements. The two top level
-  # elements must be hashes. These hashes can contain unlimited (to stack limit) levels
-  # of child elements. These child elements to not have to be of the same types.
-  # Where child elements are of the same type, deep_merge will attempt to merge them together.
-  # Where child elements are not of the same type, deep_merge will skip or optionally overwrite
-  # the destination element with the contents of the source element at that level.
-  # So if you have two hashes like this:
-  #   source = {:x => [1,2,3], :y => 2}
-  #   dest =   {:x => [4,5,'6'], :y => [7,8,9]}
-  #   dest.deep_merge!(source)
-  #   Results: {:x => [1,2,3,4,5,'6'], :y => 2}
-  # By default, "deep_merge!" will overwrite any unmergeables and merge everything else.
-  # To avoid this, use "deep_merge" (no bang/exclamation mark)
-  # 
-  # Options:
-  #   Options are specified in the last parameter passed, which should be in hash format:
-  #   hash.deep_merge!({:x => [1,2]}, {:knockout_prefix => '--'})
-  #   :preserve_unmergeables  DEFAULT: false
-  #      Set to true to skip any unmergeable elements from source
-  #   :knockout_prefix        DEFAULT: nil
-  #      Set to string value to signify prefix which deletes elements from existing element
-  #   :sort_merged_arrays     DEFAULT: false
-  #      Set to true to sort all arrays that are merged together
-  #   :unpack_arrays          DEFAULT: nil
-  #      Set to string value to run "Array::join" then "String::split" against all arrays
-  #   :merge_debug            DEFAULT: false
-  #      Set to true to get console output of merge process for debugging
-  #
-  # Selected Options Details:
-  # :knockout_prefix => The purpose of this is to provide a way to remove elements 
-  #   from existing Hash by specifying them in a special way in incoming hash
-  #    source = {:x => ['--1', '2']}
-  #    dest   = {:x => ['1', '3']}
-  #    dest.ko_deep_merge!(source)
-  #    Results: {:x => ['2','3']}
-  #   Additionally, if the knockout_prefix is passed alone as a string, it will cause
-  #   the entire element to be removed:
-  #    source = {:x => '--'}
-  #    dest   = {:x => [1,2,3]}
-  #    dest.ko_deep_merge!(source)
-  #    Results: {:x => ""}
-  # :unpack_arrays => The purpose of this is to permit compound elements to be passed
-  #   in as strings and to be converted into discrete array elements
-  #   irsource = {:x => ['1,2,3', '4']}
-  #   dest   = {:x => ['5','6','7,8']}
-  #   dest.deep_merge!(source, {:unpack_arrays => ','})
-  #   Results: {:x => ['1','2','3','4','5','6','7','8'}
-  #   Why: If receiving data from an HTML form, this makes it easy for a checkbox 
-  #    to pass multiple values from within a single HTML element
-  # 
-  # There are many tests for this library - and you can learn more about the features
-  # and usages of deep_merge! by just browsing the test examples
-  def DeepMerge.deep_merge!(source, dest, options = {})
-    # turn on this line for stdout debugging text
-    merge_debug = options[:merge_debug] || false
-    overwrite_unmergeable = !options[:preserve_unmergeables]
-    knockout_prefix = options[:knockout_prefix] || nil
-    if knockout_prefix == "" then raise InvalidParameter, "knockout_prefix cannot be an empty string in deep_merge!"; end
-    if knockout_prefix && !overwrite_unmergeable then raise InvalidParameter, "overwrite_unmergeable must be true if knockout_prefix is specified in deep_merge!"; end
-    # if present: we will split and join arrays on this char before merging
-    array_split_char = options[:unpack_arrays] || false
-    # request that we sort together any arrays when they are merged
-    sort_merged_arrays = options[:sort_merged_arrays] || false
-    di = options[:debug_indent] || ''
-    # do nothing if source is nil
-    if source.nil? || (source.respond_to?(:blank?) && source.blank?) then return dest; end
-    # if dest doesn't exist, then simply copy source to it
-    if dest.nil? && overwrite_unmergeable then dest = source; return dest; end
-
-    puts "#{di}Source class: #{source.class.inspect} :: Dest class: #{dest.class.inspect}" if merge_debug
-    if source.kind_of?(Hash)
-      puts "#{di}Hashes: #{source.inspect} :: #{dest.inspect}" if merge_debug
-      source.each do |src_key, src_value|
-        if dest.kind_of?(Hash)
-          puts "#{di} looping: #{src_key.inspect} => #{src_value.inspect} :: #{dest.inspect}" if merge_debug
-          if not dest[src_key].nil?
-            puts "#{di} ==>merging: #{src_key.inspect} => #{src_value.inspect} :: #{dest[src_key].inspect}" if merge_debug
-            dest[src_key] = deep_merge!(src_value, dest[src_key], options.merge(:debug_indent => di + '  '))
-          else # dest[src_key] doesn't exist so we want to create and overwrite it (but we do this via deep_merge!)
-            puts "#{di} ==>merging over: #{src_key.inspect} => #{src_value.inspect}" if merge_debug
-            # note: we rescue here b/c some classes respond to "dup" but don't implement it (Numeric, TrueClass, FalseClass, NilClass among maybe others)
-            begin
-              src_dup = src_value.dup # we dup src_value if possible because we're going to merge into it (since dest is empty)
-            rescue TypeError
-              src_dup = src_value
-            end
-            dest[src_key] = deep_merge!(src_value, src_dup, options.merge(:debug_indent => di + '  '))
-          end
-        else # dest isn't a hash, so we overwrite it completely (if permitted)
-          if overwrite_unmergeable
-            puts "#{di}  overwriting dest: #{src_key.inspect} => #{src_value.inspect} -over->  #{dest.inspect}" if merge_debug
-            dest = overwrite_unmergeables(source, dest, options)
-          end
-        end
-      end
-    elsif source.kind_of?(Array)
-      puts "#{di}Arrays: #{source.inspect} :: #{dest.inspect}" if merge_debug
-      # if we are instructed, join/split any source arrays before processing
-      if array_split_char
-        puts "#{di} split/join on source: #{source.inspect}" if merge_debug
-        source = source.join(array_split_char).split(array_split_char)
-        if dest.kind_of?(Array) then dest = dest.join(array_split_char).split(array_split_char); end
-      end
-      # if there's a naked knockout_prefix in source, that means we are to truncate dest
-      if source.index(knockout_prefix) then dest = clear_or_nil(dest); source.delete(knockout_prefix); end
-      if dest.kind_of?(Array)
-        if knockout_prefix
-          print "#{di} knocking out: " if merge_debug
-          # remove knockout prefix items from both source and dest
-          source.delete_if do |ko_item|
-            retval = false
-            item = ko_item.respond_to?(:gsub) ? ko_item.gsub(%r{^#{knockout_prefix}}, "") : ko_item
-            if item != ko_item
-              print "#{ko_item} - " if merge_debug
-              dest.delete(item)
-              dest.delete(ko_item)
-              retval = true
-            end
-            retval
-          end
-          puts if merge_debug
-        end
-        puts "#{di} merging arrays: #{source.inspect} :: #{dest.inspect}" if merge_debug
-        dest = dest | source
-        if sort_merged_arrays then dest.sort!; end
-      elsif overwrite_unmergeable
-        puts "#{di} overwriting dest: #{source.inspect} -over-> #{dest.inspect}" if merge_debug
-        dest = overwrite_unmergeables(source, dest, options)
-      end
-    else # src_hash is not an array or hash, so we'll have to overwrite dest
-      puts "#{di}Others: #{source.inspect} :: #{dest.inspect}" if merge_debug
-      dest = overwrite_unmergeables(source, dest, options)
-    end
-    puts "#{di}Returning #{dest.inspect}" if merge_debug
-    dest
-  end # deep_merge!
-
-  # allows deep_merge! to uniformly handle overwriting of unmergeable entities
-  def DeepMerge::overwrite_unmergeables(source, dest, options)
-    merge_debug = options[:merge_debug] || false
-    overwrite_unmergeable = !options[:preserve_unmergeables]
-    knockout_prefix = options[:knockout_prefix] || false
-    di = options[:debug_indent] || ''
-    if knockout_prefix && overwrite_unmergeable
-      if source.kind_of?(String) # remove knockout string from source before overwriting dest
-        src_tmp = source.gsub(%r{^#{knockout_prefix}},"")
-      elsif source.kind_of?(Array) # remove all knockout elements before overwriting dest
-        src_tmp = source.delete_if {|ko_item| ko_item.kind_of?(String) && ko_item.match(%r{^#{knockout_prefix}}) }
-      else
-        src_tmp = source
-      end
-      if src_tmp == source # if we didn't find a knockout_prefix then we just overwrite dest
-        puts "#{di}#{src_tmp.inspect} -over-> #{dest.inspect}" if merge_debug
-        dest = src_tmp
-      else # if we do find a knockout_prefix, then we just delete dest
-        puts "#{di}\"\" -over-> #{dest.inspect}" if merge_debug
-        dest = ""
-      end
-    elsif overwrite_unmergeable
-      dest = source
-    end
-    dest
-  end
-
-  def DeepMerge::clear_or_nil(obj)
-    if obj.respond_to?(:clear)
-      obj.clear
-    else
-      obj = nil
-    end
-    obj
-  end
-
-end # module DeepMerge
-
-class Hash
-  include DeepMerge::DeepMergeHash
-end
diff --git a/test/vendor/ceedling/vendor/unity/auto/generate_module.rb b/test/vendor/ceedling/vendor/unity/auto/generate_module.rb
index eb2cebd47..0a88becc9 100644
--- a/test/vendor/ceedling/vendor/unity/auto/generate_module.rb
+++ b/test/vendor/ceedling/vendor/unity/auto/generate_module.rb
@@ -13,7 +13,9 @@ require 'fileutils'
 require 'pathname'
 
 # TEMPLATE_TST
-TEMPLATE_TST ||= '#include "unity.h"
+TEMPLATE_TST ||= '#ifdef TEST
+
+#include "unity.h"
 
 %2$s#include "%1$s.h"
 
@@ -25,10 +27,12 @@ void tearDown(void)
 {
 }
 
-void test_%1$s_NeedToImplement(void)
+void test_%4$s_NeedToImplement(void)
 {
     TEST_IGNORE_MESSAGE("Need to Implement %1$s");
 }
+
+#endif // TEST
 '.freeze
 
 # TEMPLATE_SRC
@@ -163,24 +167,23 @@ class UnityModuleGenerator
     files
   end
 
+  ############################
+  def neutralize_filename(name, start_cap = true)
+    return name if name.empty?
+    name = name.split(/(?:\s+|_|(?=[A-Z][a-z]))|(?<=[a-z])(?=[A-Z])/).map { |v| v.capitalize }.join('_')
+    name = name[0].downcase + name[1..-1] unless start_cap
+    return name
+  end
+
   ############################
   def create_filename(part1, part2 = '')
-    if part2.empty?
-      case (@options[:naming])
-      when 'bumpy' then part1
-      when 'camel' then part1
-      when 'snake' then part1.downcase
-      when 'caps'  then part1.upcase
-      else              part1
-      end
-    else
-      case (@options[:naming])
-      when 'bumpy' then part1 + part2
-      when 'camel' then part1 + part2
-      when 'snake' then part1.downcase + '_' + part2.downcase
-      when 'caps'  then part1.upcase + '_' + part2.upcase
-      else              part1 + '_' + part2
-      end
+    name = part2.empty? ? part1 : part1 + '_' + part2
+    case (@options[:naming])
+    when 'bumpy' then neutralize_filename(name,false).delete('_')
+    when 'camel' then neutralize_filename(name).delete('_')
+    when 'snake' then neutralize_filename(name).downcase
+    when 'caps'  then neutralize_filename(name).upcase
+    else              name
     end
   end
 
@@ -208,7 +211,8 @@ class UnityModuleGenerator
         f.write("#{file[:boilerplate]}\n" % [file[:name]]) unless file[:boilerplate].nil?
         f.write(file[:template] % [file[:name],
                                    file[:includes].map { |ff| "#include \"#{ff}\"\n" }.join,
-                                   file[:name].upcase])
+                                   file[:name].upcase.gsub(/-/, '_'),
+                                   file[:name].gsub(/-/, '_')])
       end
       if @options[:update_svn]
         `svn add \"#{file[:path]}\"`
diff --git a/test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb b/test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
index 5053210d0..d1d8f91af 100644
--- a/test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
+++ b/test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
@@ -42,7 +42,9 @@ class UnityTestRunnerGenerator
       main_export_decl: '',
       cmdline_args: false,
       omit_begin_end: false,
-      use_param_tests: false
+      use_param_tests: false,
+      include_extensions: '(?:hpp|hh|H|h)',
+      source_extensions: '(?:cpp|cc|ino|C|c)'
     }
   end
 
@@ -92,7 +94,7 @@ class UnityTestRunnerGenerator
       create_suite_setup(output)
       create_suite_teardown(output)
       create_reset(output)
-      create_run_test(output)
+      create_run_test(output) unless tests.empty?
       create_args_wrappers(output, tests)
       create_main(output, input_file, tests, used_mocks)
     end
@@ -108,7 +110,7 @@ class UnityTestRunnerGenerator
     tests_and_line_numbers = []
 
     # contains characters which will be substituted from within strings, doing
-    # this prevents these characters from interferring with scrubbers
+    # this prevents these characters from interfering with scrubbers
     # @ is not a valid C character, so there should be no clashes with files genuinely containing these markers
     substring_subs = { '{' => '@co@', '}' => '@cc@', ';' => '@ss@', '/' => '@fs@' }
     substring_re = Regexp.union(substring_subs.keys)
@@ -128,7 +130,7 @@ class UnityTestRunnerGenerator
 
     lines.each_with_index do |line, _index|
       # find tests
-      next unless line =~ /^((?:\s*TEST_CASE\s*\(.*?\)\s*)*)\s*void\s+((?:#{@options[:test_prefix]}).*)\s*\(\s*(.*)\s*\)/m
+      next unless line =~ /^((?:\s*(?:TEST_CASE|TEST_RANGE)\s*\(.*?\)\s*)*)\s*void\s+((?:#{@options[:test_prefix]}).*)\s*\(\s*(.*)\s*\)/m
 
       arguments = Regexp.last_match(1)
       name = Regexp.last_match(2)
@@ -139,6 +141,20 @@ class UnityTestRunnerGenerator
       if @options[:use_param_tests] && !arguments.empty?
         args = []
         arguments.scan(/\s*TEST_CASE\s*\((.*)\)\s*$/) { |a| args << a[0] }
+
+        arguments.scan(/\s*TEST_RANGE\s*\((.*)\)\s*$/).flatten.each do |range_str|
+          args += range_str.scan(/\[\s*(-?\d+.?\d*),\s*(-?\d+.?\d*),\s*(-?\d+.?\d*)\s*\]/).map do |arg_values_str|
+            arg_values_str.map do |arg_value_str|
+              arg_value_str.include?('.') ? arg_value_str.to_f : arg_value_str.to_i
+            end
+          end.map do |arg_values|
+            (arg_values[0]..arg_values[1]).step(arg_values[2]).to_a
+          end.reduce do |result, arg_range_expanded|
+            result.product(arg_range_expanded)
+          end.map do |arg_combinations|
+            arg_combinations.flatten.join(', ')
+          end
+        end
       end
 
       tests_and_line_numbers << { test: name, args: args, call: call, params: params, line_number: 0 }
@@ -170,9 +186,9 @@ class UnityTestRunnerGenerator
 
     # parse out includes
     includes = {
-      local: source.scan(/^\s*#include\s+\"\s*(.+)\.[hH]\s*\"/).flatten,
+      local: source.scan(/^\s*#include\s+\"\s*(.+\.#{@options[:include_extensions]})\s*\"/).flatten,
       system: source.scan(/^\s*#include\s+<\s*(.+)\s*>/).flatten.map { |inc| "<#{inc}>" },
-      linkonly: source.scan(/^TEST_FILE\(\s*\"\s*(.+)\.[cC]\w*\s*\"/).flatten
+      linkonly: source.scan(/^TEST_FILE\(\s*\"\s*(.+\.#{@options[:source_extensions]})\s*\"/).flatten
     }
     includes
   end
@@ -181,7 +197,7 @@ class UnityTestRunnerGenerator
     mock_headers = []
     includes.each do |include_path|
       include_file = File.basename(include_path)
-      mock_headers << include_path if include_file =~ /^#{@options[:mock_prefix]}.*#{@options[:mock_suffix]}$/i
+      mock_headers << include_path if include_file =~ /^#{@options[:mock_prefix]}.*#{@options[:mock_suffix]}\.h$/i
     end
     mock_headers
   end
@@ -190,7 +206,7 @@ class UnityTestRunnerGenerator
     @options[:has_setup] = source =~ /void\s+#{@options[:setup_name]}\s*\(/
     @options[:has_teardown] = source =~ /void\s+#{@options[:teardown_name]}\s*\(/
     @options[:has_suite_setup] ||= (source =~ /void\s+suiteSetUp\s*\(/)
-    @options[:has_suite_teardown] ||= (source =~ /void\s+suiteTearDown\s*\(/)
+    @options[:has_suite_teardown] ||= (source =~ /int\s+suiteTearDown\s*\(int\s+([a-zA-Z0-9_])+\s*\)/)
   end
 
   def create_header(output, mocks, testfile_includes = [])
@@ -205,14 +221,14 @@ class UnityTestRunnerGenerator
       output.puts("#include \"#{File.basename(@options[:header_file])}\"")
     else
       @options[:includes].flatten.uniq.compact.each do |inc|
-        output.puts("#include #{inc.include?('<') ? inc : "\"#{inc.gsub('.h', '')}.h\""}")
+        output.puts("#include #{inc.include?('<') ? inc : "\"#{inc}\""}")
       end
       testfile_includes.each do |inc|
-        output.puts("#include #{inc.include?('<') ? inc : "\"#{inc.gsub('.h', '')}.h\""}")
+        output.puts("#include #{inc.include?('<') ? inc : "\"#{inc}\""}")
       end
     end
     mocks.each do |mock|
-      output.puts("#include \"#{mock.gsub('.h', '')}.h\"")
+      output.puts("#include \"#{mock}\"")
     end
     output.puts('#include "CException.h"') if @options[:plugins].include?(:cexception)
 
@@ -247,7 +263,7 @@ class UnityTestRunnerGenerator
       output.puts('  GlobalOrderError = NULL;')
     end
 
-    mocks = mock_headers.map { |mock| File.basename(mock) }
+    mocks = mock_headers.map { |mock| File.basename(mock, '.*') }
     mocks.each do |mock|
       mock_clean = TypeSanitizer.sanitize_c_identifier(mock)
       output.puts("  #{mock_clean}_Init();")
@@ -325,8 +341,8 @@ class UnityTestRunnerGenerator
 
   def create_run_test(output)
     require 'erb'
-    template = ERB.new(File.read(File.join(__dir__, 'run_test.erb')))
-    output.puts(template.result(binding))
+    template = ERB.new(File.read(File.join(__dir__, 'run_test.erb')), nil, '<>')
+    output.puts("\n" + template.result(binding))
   end
 
   def create_args_wrappers(output, tests)
@@ -346,7 +362,7 @@ class UnityTestRunnerGenerator
   end
 
   def create_main(output, filename, tests, used_mocks)
-    output.puts("\n\n/*=======MAIN=====*/")
+    output.puts("\n/*=======MAIN=====*/")
     main_name = @options[:main_name].to_sym == :auto ? "main_#{filename.gsub('.c', '')}" : (@options[:main_name]).to_s
     if @options[:cmdline_args]
       if main_name != 'main'
@@ -410,7 +426,7 @@ class UnityTestRunnerGenerator
         output.puts('  return suiteTearDown(UnityEnd());')
       end
     else
-      output.puts('  return UnityEnd();') if not @options[:omit_begin_end]
+      output.puts('  return UnityEnd();') unless @options[:omit_begin_end]
     end
     output.puts('}')
   end
@@ -423,10 +439,10 @@ class UnityTestRunnerGenerator
     output.puts("#include \"#{@options[:framework]}.h\"")
     output.puts('#include "cmock.h"') unless used_mocks.empty?
     @options[:includes].flatten.uniq.compact.each do |inc|
-      output.puts("#include #{inc.include?('<') ? inc : "\"#{inc.gsub('.h', '')}.h\""}")
+      output.puts("#include #{inc.include?('<') ? inc : "\"#{inc}\""}")
     end
     testfile_includes.each do |inc|
-      output.puts("#include #{inc.include?('<') ? inc : "\"#{inc.gsub('.h', '')}.h\""}")
+      output.puts("#include #{inc.include?('<') ? inc : "\"#{inc}\""}")
     end
     output.puts "\n"
     tests.each do |test|
@@ -449,13 +465,13 @@ if $0 == __FILE__
     when '-cexception'
       options[:plugins] = [:cexception]
       true
-    when /\.*\.ya?ml/
+    when /\.*\.ya?ml$/
       options = UnityTestRunnerGenerator.grab_config(arg)
       true
     when /--(\w+)=\"?(.*)\"?/
       options[Regexp.last_match(1).to_sym] = Regexp.last_match(2)
       true
-    when /\.*\.h/
+    when /\.*\.(?:hpp|hh|H|h)$/
       options[:includes] << arg
       true
     else false
diff --git a/test/vendor/ceedling/vendor/unity/auto/run_test.erb b/test/vendor/ceedling/vendor/unity/auto/run_test.erb
index 3d3b6d1e8..f91b56691 100644
--- a/test/vendor/ceedling/vendor/unity/auto/run_test.erb
+++ b/test/vendor/ceedling/vendor/unity/auto/run_test.erb
@@ -1,5 +1,5 @@
 /*=======Test Runner Used To Run Each Test=====*/
-static void run_test(UnityTestFunction func, const char* name, int line_num)
+static void run_test(UnityTestFunction func, const char* name, UNITY_LINE_TYPE line_num)
 {
     Unity.CurrentTestName = name;
     Unity.CurrentTestLineNumber = line_num;
@@ -16,13 +16,14 @@ static void run_test(UnityTestFunction func, const char* name, int line_num)
 <% if @options[:plugins].include?(:cexception) %>
         CEXCEPTION_T e;
         Try {
-<% end %>
             <%= @options[:setup_name] %>();
             func();
-<% if @options[:plugins].include?(:cexception) %>
         } Catch(e) {
             TEST_ASSERT_EQUAL_HEX32_MESSAGE(CEXCEPTION_NONE, e, "Unhandled Exception!");
         }
+<% else %>
+        <%= @options[:setup_name] %>();
+        func();
 <% end %>
     }
     if (TEST_PROTECT())
diff --git a/test/vendor/ceedling/vendor/unity/release/build.info b/test/vendor/ceedling/vendor/unity/release/build.info
deleted file mode 100644
index 56d591286..000000000
--- a/test/vendor/ceedling/vendor/unity/release/build.info
+++ /dev/null
@@ -1,2 +0,0 @@
-122
-
diff --git a/test/vendor/ceedling/vendor/unity/release/version.info b/test/vendor/ceedling/vendor/unity/release/version.info
deleted file mode 100644
index cf12b30d2..000000000
--- a/test/vendor/ceedling/vendor/unity/release/version.info
+++ /dev/null
@@ -1,2 +0,0 @@
-2.4.3
-
diff --git a/test/vendor/ceedling/vendor/unity/src/CMakeLists.txt b/test/vendor/ceedling/vendor/unity/src/CMakeLists.txt
deleted file mode 100644
index c747cb0ae..000000000
--- a/test/vendor/ceedling/vendor/unity/src/CMakeLists.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-###################################################################################
-#                                                                                 #
-# NAME: CMakeLists.txt                                                            #
-#                                                                                 #
-# AUTHOR: Mike Karlesky, Mark VanderVoord, Greg Williams.                         #
-# WRITTEN BY: Michael Brockus.                                                    #
-#                                                                                 #
-# License: MIT                                                                    #
-#                                                                                 #
-###################################################################################
-cmake_minimum_required(VERSION 3.0 FATAL_ERROR)
-
-
-add_library(unity STATIC "unity.c")
-
-install(TARGETS unity EXPORT unityConfig
-    ARCHIVE  DESTINATION "${CMAKE_CURRENT_SOURCE_DIR}/${CMAKE_INSTALL_LIBDIR}"
-    LIBRARY  DESTINATION "${CMAKE_CURRENT_SOURCE_DIR}/${CMAKE_INSTALL_LIBDIR}"
-    RUNTIME  DESTINATION "${CMAKE_CURRENT_SOURCE_DIR}/${CMAKE_INSTALL_BINDIR}"
-    INCLUDES DESTINATION "${CMAKE_INSTALL_LIBDIR}")
-
-
diff --git a/test/vendor/ceedling/vendor/unity/src/meson.build b/test/vendor/ceedling/vendor/unity/src/meson.build
index f5e014653..1c7b426ff 100644
--- a/test/vendor/ceedling/vendor/unity/src/meson.build
+++ b/test/vendor/ceedling/vendor/unity/src/meson.build
@@ -1,16 +1,11 @@
-###################################################################################
-#                                                                                 #
-# NAME: meson.build                                                               #
-#                                                                                 #
-# AUTHOR: Mike Karlesky, Mark VanderVoord, Greg Williams.                         #
-# WRITTEN BY: Michael Brockus.                                                    #
-#                                                                                 #
-# License: MIT                                                                    #
-#                                                                                 #
-###################################################################################
-
+#
+# build script written by : Michael Brockus.
+# github repo author: Mike Karlesky, Mark VanderVoord, Greg Williams.
+#
+# license: MIT
+#
 unity_dir = include_directories('.')
 
 unity_lib = static_library(meson.project_name(), 
-    sources: ['unity.c'],
+    files('unity.c'),
     include_directories: unity_dir)
diff --git a/test/vendor/ceedling/vendor/unity/src/unity.c b/test/vendor/ceedling/vendor/unity/src/unity.c
index c7be02cc6..764a42b18 100644
--- a/test/vendor/ceedling/vendor/unity/src/unity.c
+++ b/test/vendor/ceedling/vendor/unity/src/unity.c
@@ -1,6 +1,6 @@
 /* =========================================================================
     Unity Project - A Test Framework for C
-    Copyright (c) 2007-19 Mike Karlesky, Mark VanderVoord, Greg Williams
+    Copyright (c) 2007-21 Mike Karlesky, Mark VanderVoord, Greg Williams
     [Released under MIT License. Please refer to license.txt for details]
 ============================================================================ */
 
@@ -21,7 +21,7 @@ void UNITY_OUTPUT_CHAR(int);
 /* Helpful macros for us to use here in Assert functions */
 #define UNITY_FAIL_AND_BAIL   { Unity.CurrentTestFailed  = 1; UNITY_OUTPUT_FLUSH(); TEST_ABORT(); }
 #define UNITY_IGNORE_AND_BAIL { Unity.CurrentTestIgnored = 1; UNITY_OUTPUT_FLUSH(); TEST_ABORT(); }
-#define RETURN_IF_FAIL_OR_IGNORE if (Unity.CurrentTestFailed || Unity.CurrentTestIgnored) return
+#define RETURN_IF_FAIL_OR_IGNORE if (Unity.CurrentTestFailed || Unity.CurrentTestIgnored) TEST_ABORT()
 
 struct UNITY_STORAGE_T Unity;
 
@@ -43,6 +43,7 @@ static const char PROGMEM UnityStrWas[]                    = " Was ";
 static const char PROGMEM UnityStrGt[]                     = " to be greater than ";
 static const char PROGMEM UnityStrLt[]                     = " to be less than ";
 static const char PROGMEM UnityStrOrEqual[]                = "or equal to ";
+static const char PROGMEM UnityStrNotEqual[]               = " to be not equal to ";
 static const char PROGMEM UnityStrElement[]                = " Element ";
 static const char PROGMEM UnityStrByte[]                   = " Byte ";
 static const char PROGMEM UnityStrMemory[]                 = " Memory Mismatch.";
@@ -66,9 +67,10 @@ static const char PROGMEM UnityStrBreaker[]                = "------------------
 static const char PROGMEM UnityStrResultsTests[]           = " Tests ";
 static const char PROGMEM UnityStrResultsFailures[]        = " Failures ";
 static const char PROGMEM UnityStrResultsIgnored[]         = " Ignored ";
+#ifndef UNITY_EXCLUDE_DETAILS
 static const char PROGMEM UnityStrDetail1Name[]            = UNITY_DETAIL1_NAME " ";
 static const char PROGMEM UnityStrDetail2Name[]            = " " UNITY_DETAIL2_NAME " ";
-
+#endif
 /*-----------------------------------------------
  * Pretty Printers & Test Result Output Handlers
  *-----------------------------------------------*/
@@ -146,121 +148,6 @@ void UnityPrint(const char* string)
         }
     }
 }
-
-/*-----------------------------------------------*/
-#ifdef UNITY_INCLUDE_PRINT_FORMATTED
-void UnityPrintFormatted(const char* format, ...)
-{
-    const char* pch = format;
-    va_list va;
-    va_start(va, format);
-
-    if (pch != NULL)
-    {
-        while (*pch)
-        {
-            /* format identification character */
-            if (*pch == '%')
-            {
-                pch++;
-
-                if (pch != NULL)
-                {
-                    switch (*pch)
-                    {
-                        case 'd':
-                        case 'i':
-                            {
-                                const int number = va_arg(va, int);
-                                UnityPrintNumber((UNITY_INT)number);
-                                break;
-                            }
-#ifndef UNITY_EXCLUDE_FLOAT_PRINT
-                        case 'f':
-                        case 'g':
-                            {
-                                const double number = va_arg(va, double);
-                                UnityPrintFloat((UNITY_DOUBLE)number);
-                                break;
-                            }
-#endif
-                        case 'u':
-                            {
-                                const unsigned int number = va_arg(va, unsigned int);
-                                UnityPrintNumberUnsigned((UNITY_UINT)number);
-                                break;
-                            }
-                        case 'b':
-                            {
-                                const unsigned int number = va_arg(va, unsigned int);
-                                const UNITY_UINT mask = (UNITY_UINT)0 - (UNITY_UINT)1;
-                                UNITY_OUTPUT_CHAR('0');
-                                UNITY_OUTPUT_CHAR('b');
-                                UnityPrintMask(mask, (UNITY_UINT)number);
-                                break;
-                            }
-                        case 'x':
-                        case 'X':
-                        case 'p':
-                            {
-                                const unsigned int number = va_arg(va, unsigned int);
-                                UNITY_OUTPUT_CHAR('0');
-                                UNITY_OUTPUT_CHAR('x');
-                                UnityPrintNumberHex((UNITY_UINT)number, 8);
-                                break;
-                            }
-                        case 'c':
-                            {
-                                const int ch = va_arg(va, int);
-                                UnityPrintChar((const char *)&ch);
-                                break;
-                            }
-                        case 's':
-                            {
-                                const char * string = va_arg(va, const char *);
-                                UnityPrint(string);
-                                break;
-                            }
-                        case '%':
-                            {
-                                UnityPrintChar(pch);
-                                break;
-                            }
-                        default:
-                            {
-                                /* print the unknown format character */
-                                UNITY_OUTPUT_CHAR('%');
-                                UnityPrintChar(pch);
-                                break;
-                            }
-                    }
-                }
-            }
-#ifdef UNITY_OUTPUT_COLOR
-            /* print ANSI escape code */
-            else if ((*pch == 27) && (*(pch + 1) == '['))
-            {
-                pch += UnityPrintAnsiEscapeString(pch);
-                continue;
-            }
-#endif
-            else if (*pch == '\n')
-            {
-                UNITY_PRINT_EOL();
-            }
-            else
-            {
-                UnityPrintChar(pch);
-            }
-
-            pch++;
-        }
-    }
-
-    va_end(va);
-}
-#endif /* ! UNITY_INCLUDE_PRINT_FORMATTED */
-
 /*-----------------------------------------------*/
 void UnityPrintLen(const char* string, const UNITY_UINT32 length)
 {
@@ -558,7 +445,7 @@ void UnityPrintFloat(const UNITY_DOUBLE input_number)
 
         /* build up buffer in reverse order */
         digits = 0;
-        while ((n != 0) || (digits < (decimals + 1)))
+        while ((n != 0) || (digits <= decimals))
         {
             buf[digits++] = (char)('0' + n % 10);
             n /= 10;
@@ -680,6 +567,10 @@ static void UnityAddMsgIfSpecified(const char* msg)
     if (msg)
     {
         UnityPrint(UnityStrSpacer);
+
+#ifdef UNITY_PRINT_TEST_CONTEXT
+        UNITY_PRINT_TEST_CONTEXT();
+#endif
 #ifndef UNITY_EXCLUDE_DETAILS
         if (Unity.CurrentDetail1)
         {
@@ -863,9 +754,10 @@ void UnityAssertGreaterOrLessOrEqualNumber(const UNITY_INT threshold,
         UnityTestResultsFailBegin(lineNumber);
         UnityPrint(UnityStrExpected);
         UnityPrintNumberByStyle(actual, style);
-        if (compare & UNITY_GREATER_THAN) { UnityPrint(UnityStrGt);      }
-        if (compare & UNITY_SMALLER_THAN) { UnityPrint(UnityStrLt);      }
-        if (compare & UNITY_EQUAL_TO)     { UnityPrint(UnityStrOrEqual); }
+        if (compare & UNITY_GREATER_THAN) { UnityPrint(UnityStrGt);       }
+        if (compare & UNITY_SMALLER_THAN) { UnityPrint(UnityStrLt);       }
+        if (compare & UNITY_EQUAL_TO)     { UnityPrint(UnityStrOrEqual);  }
+        if (compare == UNITY_NOT_EQUAL)   { UnityPrint(UnityStrNotEqual); }
         UnityPrintNumberByStyle(threshold, style);
         UnityAddMsgIfSpecified(msg);
         UNITY_FAIL_AND_BAIL;
@@ -1110,7 +1002,7 @@ void UnityAssertFloatSpecial(const UNITY_FLOAT actual,
             is_trait = !isinf(actual) && !isnan(actual);
             break;
 
-        default:
+        default: /* including UNITY_FLOAT_INVALID_TRAIT */
             trait_index = 0;
             trait_names[0] = UnityStrInvalidFloatTrait;
             break;
@@ -1250,7 +1142,7 @@ void UnityAssertDoubleSpecial(const UNITY_DOUBLE actual,
             is_trait = !isinf(actual) && !isnan(actual);
             break;
 
-        default:
+        default: /* including UNITY_FLOAT_INVALID_TRAIT */
             trait_index = 0;
             trait_names[0] = UnityStrInvalidFloatTrait;
             break;
@@ -1731,6 +1623,133 @@ UNITY_INTERNAL_PTR UnityDoubleToPtr(const double num)
 }
 #endif
 
+/*-----------------------------------------------
+ * printf helper function
+ *-----------------------------------------------*/
+#ifdef UNITY_INCLUDE_PRINT_FORMATTED
+static void UnityPrintFVA(const char* format, va_list va)
+{
+    const char* pch = format;
+    if (pch != NULL)
+    {
+        while (*pch)
+        {
+            /* format identification character */
+            if (*pch == '%')
+            {
+                pch++;
+
+                if (pch != NULL)
+                {
+                    switch (*pch)
+                    {
+                        case 'd':
+                        case 'i':
+                            {
+                                const int number = va_arg(va, int);
+                                UnityPrintNumber((UNITY_INT)number);
+                                break;
+                            }
+#ifndef UNITY_EXCLUDE_FLOAT_PRINT
+                        case 'f':
+                        case 'g':
+                            {
+                                const double number = va_arg(va, double);
+                                UnityPrintFloat((UNITY_DOUBLE)number);
+                                break;
+                            }
+#endif
+                        case 'u':
+                            {
+                                const unsigned int number = va_arg(va, unsigned int);
+                                UnityPrintNumberUnsigned((UNITY_UINT)number);
+                                break;
+                            }
+                        case 'b':
+                            {
+                                const unsigned int number = va_arg(va, unsigned int);
+                                const UNITY_UINT mask = (UNITY_UINT)0 - (UNITY_UINT)1;
+                                UNITY_OUTPUT_CHAR('0');
+                                UNITY_OUTPUT_CHAR('b');
+                                UnityPrintMask(mask, (UNITY_UINT)number);
+                                break;
+                            }
+                        case 'x':
+                        case 'X':
+                        case 'p':
+                            {
+                                const unsigned int number = va_arg(va, unsigned int);
+                                UNITY_OUTPUT_CHAR('0');
+                                UNITY_OUTPUT_CHAR('x');
+                                UnityPrintNumberHex((UNITY_UINT)number, 8);
+                                break;
+                            }
+                        case 'c':
+                            {
+                                const int ch = va_arg(va, int);
+                                UnityPrintChar((const char *)&ch);
+                                break;
+                            }
+                        case 's':
+                            {
+                                const char * string = va_arg(va, const char *);
+                                UnityPrint(string);
+                                break;
+                            }
+                        case '%':
+                            {
+                                UnityPrintChar(pch);
+                                break;
+                            }
+                        default:
+                            {
+                                /* print the unknown format character */
+                                UNITY_OUTPUT_CHAR('%');
+                                UnityPrintChar(pch);
+                                break;
+                            }
+                    }
+                }
+            }
+#ifdef UNITY_OUTPUT_COLOR
+            /* print ANSI escape code */
+            else if ((*pch == 27) && (*(pch + 1) == '['))
+            {
+                pch += UnityPrintAnsiEscapeString(pch);
+                continue;
+            }
+#endif
+            else if (*pch == '\n')
+            {
+                UNITY_PRINT_EOL();
+            }
+            else
+            {
+                UnityPrintChar(pch);
+            }
+
+            pch++;
+        }
+    }
+}
+
+void UnityPrintF(const UNITY_LINE_TYPE line, const char* format, ...)
+{
+    UnityTestResultsBegin(Unity.TestFile, line);
+    UnityPrint("INFO");
+    if(format != NULL)
+    {
+        UnityPrint(": ");
+        va_list va;
+        va_start(va, format);
+        UnityPrintFVA(format, va);
+        va_end(va);
+    }
+    UNITY_PRINT_EOL();
+}
+#endif /* ! UNITY_INCLUDE_PRINT_FORMATTED */
+
+
 /*-----------------------------------------------
  * Control Functions
  *-----------------------------------------------*/
@@ -1746,6 +1765,9 @@ void UnityFail(const char* msg, const UNITY_LINE_TYPE line)
     {
         UNITY_OUTPUT_CHAR(':');
 
+#ifdef UNITY_PRINT_TEST_CONTEXT
+        UNITY_PRINT_TEST_CONTEXT();
+#endif
 #ifndef UNITY_EXCLUDE_DETAILS
         if (Unity.CurrentDetail1)
         {
@@ -1800,6 +1822,8 @@ void UnityMessage(const char* msg, const UNITY_LINE_TYPE line)
 }
 
 /*-----------------------------------------------*/
+/* If we have not defined our own test runner, then include our default test runner to make life easier */
+#ifndef UNITY_SKIP_DEFAULT_RUNNER
 void UnityDefaultTestRun(UnityTestFunction Func, const char* FuncName, const int FuncLineNum)
 {
     Unity.CurrentTestName = FuncName;
@@ -1819,6 +1843,7 @@ void UnityDefaultTestRun(UnityTestFunction Func, const char* FuncName, const int
     UNITY_EXEC_TIME_STOP();
     UnityConcludeTest();
 }
+#endif
 
 /*-----------------------------------------------*/
 void UnitySetTestFile(const char* filename)
diff --git a/test/vendor/ceedling/vendor/unity/src/unity.h b/test/vendor/ceedling/vendor/unity/src/unity.h
index 34d7f93aa..338df0b55 100644
--- a/test/vendor/ceedling/vendor/unity/src/unity.h
+++ b/test/vendor/ceedling/vendor/unity/src/unity.h
@@ -1,6 +1,6 @@
 /* ==========================================
     Unity Project - A Test Framework for C
-    Copyright (c) 2007-19 Mike Karlesky, Mark VanderVoord, Greg Williams
+    Copyright (c) 2007-21 Mike Karlesky, Mark VanderVoord, Greg Williams
     [Released under MIT License. Please refer to license.txt for details]
 ========================================== */
 
@@ -10,7 +10,7 @@
 
 #define UNITY_VERSION_MAJOR    2
 #define UNITY_VERSION_MINOR    5
-#define UNITY_VERSION_BUILD    0
+#define UNITY_VERSION_BUILD    4
 #define UNITY_VERSION          ((UNITY_VERSION_MAJOR << 16) | (UNITY_VERSION_MINOR << 8) | UNITY_VERSION_BUILD)
 
 #ifdef __cplusplus
@@ -104,6 +104,9 @@ void verifyTest(void);
 #define TEST_IGNORE()                                                                              UNITY_TEST_IGNORE(__LINE__, NULL)
 #define TEST_MESSAGE(message)                                                                      UnityMessage((message), __LINE__)
 #define TEST_ONLY()
+#ifdef UNITY_INCLUDE_PRINT_FORMATTED
+#define TEST_PRINTF(message, ...)                                                                  UnityPrintF(__LINE__, (message), __VA_ARGS__)
+#endif
 
 /* It is not necessary for you to call PASS. A PASS condition is assumed if nothing fails.
  * This method allows you to abort a test immediately with a PASS state, ignoring the remainder of the test. */
@@ -125,6 +128,8 @@ void verifyTest(void);
 #define TEST_ASSERT_FALSE(condition)                                                               UNITY_TEST_ASSERT(      !(condition), __LINE__, " Expected FALSE Was TRUE")
 #define TEST_ASSERT_NULL(pointer)                                                                  UNITY_TEST_ASSERT_NULL(    (pointer), __LINE__, " Expected NULL")
 #define TEST_ASSERT_NOT_NULL(pointer)                                                              UNITY_TEST_ASSERT_NOT_NULL((pointer), __LINE__, " Expected Non-NULL")
+#define TEST_ASSERT_EMPTY(pointer)                                                                 UNITY_TEST_ASSERT_EMPTY(    (pointer), __LINE__, " Expected Empty")
+#define TEST_ASSERT_NOT_EMPTY(pointer)                                                             UNITY_TEST_ASSERT_NOT_EMPTY((pointer), __LINE__, " Expected Non-Empty")
 
 /* Integers (of all sizes) */
 #define TEST_ASSERT_EQUAL_INT(expected, actual)                                                    UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, NULL)
@@ -145,10 +150,28 @@ void verifyTest(void);
 #define TEST_ASSERT_EQUAL_HEX64(expected, actual)                                                  UNITY_TEST_ASSERT_EQUAL_HEX64((expected), (actual), __LINE__, NULL)
 #define TEST_ASSERT_EQUAL_CHAR(expected, actual)                                                   UNITY_TEST_ASSERT_EQUAL_CHAR((expected), (actual), __LINE__, NULL)
 #define TEST_ASSERT_BITS(mask, expected, actual)                                                   UNITY_TEST_ASSERT_BITS((mask), (expected), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS_HIGH(mask, actual)                                                        UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(-1), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BITS_LOW(mask, actual)                                                         UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT32)(0), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BIT_HIGH(bit, actual)                                                          UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(-1), (actual), __LINE__, NULL)
-#define TEST_ASSERT_BIT_LOW(bit, actual)                                                           UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(0), (actual), __LINE__, NULL)
+#define TEST_ASSERT_BITS_HIGH(mask, actual)                                                        UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT)(-1), (actual), __LINE__, NULL)
+#define TEST_ASSERT_BITS_LOW(mask, actual)                                                         UNITY_TEST_ASSERT_BITS((mask), (UNITY_UINT)(0), (actual), __LINE__, NULL)
+#define TEST_ASSERT_BIT_HIGH(bit, actual)                                                          UNITY_TEST_ASSERT_BITS(((UNITY_UINT)1 << (bit)), (UNITY_UINT)(-1), (actual), __LINE__, NULL)
+#define TEST_ASSERT_BIT_LOW(bit, actual)                                                           UNITY_TEST_ASSERT_BITS(((UNITY_UINT)1 << (bit)), (UNITY_UINT)(0), (actual), __LINE__, NULL)
+
+/* Integer Not Equal To (of all sizes) */
+#define TEST_ASSERT_NOT_EQUAL_INT(threshold, actual)                                               UNITY_TEST_ASSERT_NOT_EQUAL_INT((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_INT8(threshold, actual)                                              UNITY_TEST_ASSERT_NOT_EQUAL_INT8((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_INT16(threshold, actual)                                             UNITY_TEST_ASSERT_NOT_EQUAL_INT16((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_INT32(threshold, actual)                                             UNITY_TEST_ASSERT_NOT_EQUAL_INT32((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_INT64(threshold, actual)                                             UNITY_TEST_ASSERT_NOT_EQUAL_INT64((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_UINT(threshold, actual)                                              UNITY_TEST_ASSERT_NOT_EQUAL_UINT((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_UINT8(threshold, actual)                                             UNITY_TEST_ASSERT_NOT_EQUAL_UINT8((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_UINT16(threshold, actual)                                            UNITY_TEST_ASSERT_NOT_EQUAL_UINT16((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_UINT32(threshold, actual)                                            UNITY_TEST_ASSERT_NOT_EQUAL_UINT32((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_UINT64(threshold, actual)                                            UNITY_TEST_ASSERT_NOT_EQUAL_UINT64((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_size_t(threshold, actual)                                            UNITY_TEST_ASSERT_NOT_EQUAL_UINT((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_HEX8(threshold, actual)                                              UNITY_TEST_ASSERT_NOT_EQUAL_HEX8((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_HEX16(threshold, actual)                                             UNITY_TEST_ASSERT_NOT_EQUAL_HEX16((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_HEX32(threshold, actual)                                             UNITY_TEST_ASSERT_NOT_EQUAL_HEX32((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_HEX64(threshold, actual)                                             UNITY_TEST_ASSERT_NOT_EQUAL_HEX64((threshold), (actual), __LINE__, NULL)
+#define TEST_ASSERT_NOT_EQUAL_CHAR(threshold, actual)                                              UNITY_TEST_ASSERT_NOT_EQUAL_CHAR((threshold), (actual), __LINE__, NULL)
 
 /* Integer Greater Than/ Less Than (of all sizes) */
 #define TEST_ASSERT_GREATER_THAN(threshold, actual)                                                UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, NULL)
@@ -373,6 +396,8 @@ void verifyTest(void);
 #define TEST_ASSERT_FALSE_MESSAGE(condition, message)                                              UNITY_TEST_ASSERT(      !(condition), __LINE__, (message))
 #define TEST_ASSERT_NULL_MESSAGE(pointer, message)                                                 UNITY_TEST_ASSERT_NULL(    (pointer), __LINE__, (message))
 #define TEST_ASSERT_NOT_NULL_MESSAGE(pointer, message)                                             UNITY_TEST_ASSERT_NOT_NULL((pointer), __LINE__, (message))
+#define TEST_ASSERT_EMPTY_MESSAGE(pointer, message)                                                UNITY_TEST_ASSERT_EMPTY(    (pointer), __LINE__, (message))
+#define TEST_ASSERT_NOT_EMPTY_MESSAGE(pointer, message)                                            UNITY_TEST_ASSERT_NOT_EMPTY((pointer), __LINE__, (message))
 
 /* Integers (of all sizes) */
 #define TEST_ASSERT_EQUAL_INT_MESSAGE(expected, actual, message)                                   UNITY_TEST_ASSERT_EQUAL_INT((expected), (actual), __LINE__, (message))
@@ -398,6 +423,25 @@ void verifyTest(void);
 #define TEST_ASSERT_BIT_LOW_MESSAGE(bit, actual, message)                                          UNITY_TEST_ASSERT_BITS(((UNITY_UINT32)1 << (bit)), (UNITY_UINT32)(0), (actual), __LINE__, (message))
 #define TEST_ASSERT_EQUAL_CHAR_MESSAGE(expected, actual, message)                                  UNITY_TEST_ASSERT_EQUAL_CHAR((expected), (actual), __LINE__, (message))
 
+/* Integer Not Equal To (of all sizes) */
+#define TEST_ASSERT_NOT_EQUAL_INT_MESSAGE(threshold, actual, message)                              UNITY_TEST_ASSERT_NOT_EQUAL_INT((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_INT8_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_NOT_EQUAL_INT8((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_INT16_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_NOT_EQUAL_INT16((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_INT32_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_NOT_EQUAL_INT32((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_INT64_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_NOT_EQUAL_INT64((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_UINT_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_NOT_EQUAL_UINT((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_UINT8_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_NOT_EQUAL_UINT8((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_UINT16_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_NOT_EQUAL_UINT16((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_UINT32_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_NOT_EQUAL_UINT32((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_UINT64_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_NOT_EQUAL_UINT64((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_size_t_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_NOT_EQUAL_UINT((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_HEX8_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_NOT_EQUAL_HEX8((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_HEX16_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_NOT_EQUAL_HEX16((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_HEX32_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_NOT_EQUAL_HEX32((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_HEX64_MESSAGE(threshold, actual, message)                            UNITY_TEST_ASSERT_NOT_EQUAL_HEX64((threshold), (actual), __LINE__, (message))
+#define TEST_ASSERT_NOT_EQUAL_CHAR_MESSAGE(threshold, actual, message)                             UNITY_TEST_ASSERT_NOT_EQUAL_CHAR((threshold), (actual), __LINE__, (message))
+
+
 /* Integer Greater Than/ Less Than (of all sizes) */
 #define TEST_ASSERT_GREATER_THAN_MESSAGE(threshold, actual, message)                               UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, (message))
 #define TEST_ASSERT_GREATER_THAN_INT_MESSAGE(threshold, actual, message)                           UNITY_TEST_ASSERT_GREATER_THAN_INT((threshold), (actual), __LINE__, (message))
diff --git a/test/vendor/ceedling/vendor/unity/src/unity_internals.h b/test/vendor/ceedling/vendor/unity/src/unity_internals.h
index a9a7ea237..2c91b6db1 100644
--- a/test/vendor/ceedling/vendor/unity/src/unity_internals.h
+++ b/test/vendor/ceedling/vendor/unity/src/unity_internals.h
@@ -1,6 +1,6 @@
 /* ==========================================
     Unity Project - A Test Framework for C
-    Copyright (c) 2007-19 Mike Karlesky, Mark VanderVoord, Greg Williams
+    Copyright (c) 2007-21 Mike Karlesky, Mark VanderVoord, Greg Williams
     [Released under MIT License. Please refer to license.txt for details]
 ========================================== */
 
@@ -40,6 +40,26 @@
 #include <limits.h>
 #endif
 
+#if defined(__GNUC__) || defined(__clang__)
+  #define UNITY_FUNCTION_ATTR(a)    __attribute__((a))
+#else
+  #define UNITY_FUNCTION_ATTR(a)    /* ignore */
+#endif
+
+#ifndef UNITY_NORETURN
+  #if defined(__cplusplus)
+    #if __cplusplus >= 201103L
+      #define UNITY_NORETURN [[ noreturn ]]
+    #endif
+  #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
+    #include <stdnoreturn.h>
+    #define UNITY_NORETURN noreturn
+  #endif
+#endif
+#ifndef UNITY_NORETURN
+  #define UNITY_NORETURN UNITY_FUNCTION_ATTR(noreturn)
+#endif
+
 /*-------------------------------------------------------
  * Guess Widths If Not Specified
  *-------------------------------------------------------*/
@@ -327,7 +347,7 @@ typedef UNITY_FLOAT_TYPE UNITY_FLOAT;
         UnityPrintNumberUnsigned(execTimeMs); \
         UnityPrint(" ms)"); \
         }
-    #elif defined(__unix__)
+    #elif defined(__unix__) || defined(__APPLE__)
       #include <time.h>
       #define UNITY_TIME_TYPE struct timespec
       #define UNITY_GET_TIME(t) clock_gettime(CLOCK_MONOTONIC, &t)
@@ -421,6 +441,7 @@ typedef enum
     UNITY_GREATER_OR_EQUAL = 0x2 + UNITY_EQUAL_TO,
     UNITY_SMALLER_THAN     = 0x4,
     UNITY_SMALLER_OR_EQUAL = 0x4 + UNITY_EQUAL_TO,
+    UNITY_NOT_EQUAL        = 0x0,
     UNITY_UNKNOWN
 } UNITY_COMPARISON_T;
 
@@ -479,7 +500,12 @@ void UnityBegin(const char* filename);
 int  UnityEnd(void);
 void UnitySetTestFile(const char* filename);
 void UnityConcludeTest(void);
+
+#ifndef RUN_TEST
 void UnityDefaultTestRun(UnityTestFunction Func, const char* FuncName, const int FuncLineNum);
+#else
+#define UNITY_SKIP_DEFAULT_RUNNER
+#endif
 
 /*-------------------------------------------------------
  * Details Support
@@ -503,6 +529,10 @@ void UnityDefaultTestRun(UnityTestFunction Func, const char* FuncName, const int
 #endif
 #endif
 
+#ifdef UNITY_PRINT_TEST_CONTEXT
+void UNITY_PRINT_TEST_CONTEXT(void);
+#endif
+
 /*-------------------------------------------------------
  * Test Output
  *-------------------------------------------------------*/
@@ -510,7 +540,7 @@ void UnityDefaultTestRun(UnityTestFunction Func, const char* FuncName, const int
 void UnityPrint(const char* string);
 
 #ifdef UNITY_INCLUDE_PRINT_FORMATTED
-void UnityPrintFormatted(const char* format, ...);
+void UnityPrintF(const UNITY_LINE_TYPE line, const char* format, ...);
 #endif
 
 void UnityPrintLen(const char* string, const UNITY_UINT32 length);
@@ -601,8 +631,14 @@ void UnityAssertNumbersArrayWithin(const UNITY_UINT delta,
                                    const UNITY_DISPLAY_STYLE_T style,
                                    const UNITY_FLAGS_T flags);
 
+#ifndef UNITY_EXCLUDE_SETJMP_H
+UNITY_NORETURN void UnityFail(const char* message, const UNITY_LINE_TYPE line);
+UNITY_NORETURN void UnityIgnore(const char* message, const UNITY_LINE_TYPE line);
+#else
 void UnityFail(const char* message, const UNITY_LINE_TYPE line);
 void UnityIgnore(const char* message, const UNITY_LINE_TYPE line);
+#endif
+
 void UnityMessage(const char* message, const UNITY_LINE_TYPE line);
 
 #ifndef UNITY_EXCLUDE_FLOAT
@@ -691,11 +727,8 @@ extern const char UnityStrErrShorthand[];
 #endif
 #endif
 #ifdef UNITY_SUPPORT_VARIADIC_MACROS
-#define RUN_TEST(...) UnityDefaultTestRun(RUN_TEST_FIRST(__VA_ARGS__), RUN_TEST_SECOND(__VA_ARGS__))
-#define RUN_TEST_FIRST(...) RUN_TEST_FIRST_HELPER(__VA_ARGS__, throwaway)
-#define RUN_TEST_FIRST_HELPER(first, ...) (first), #first
-#define RUN_TEST_SECOND(...) RUN_TEST_SECOND_HELPER(__VA_ARGS__, __LINE__, throwaway)
-#define RUN_TEST_SECOND_HELPER(first, second, ...) (second)
+#define RUN_TEST(...) RUN_TEST_AT_LINE(__VA_ARGS__, __LINE__, throwaway)
+#define RUN_TEST_AT_LINE(func, line, ...) UnityDefaultTestRun(func, #func, line)
 #endif
 #endif
 
@@ -753,9 +786,11 @@ int UnityTestMatches(void);
  * Test Asserts
  *-------------------------------------------------------*/
 
-#define UNITY_TEST_ASSERT(condition, line, message)                                              if (condition) {} else {UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), (message));}
+#define UNITY_TEST_ASSERT(condition, line, message)                                              do {if (condition) {} else {UNITY_TEST_FAIL((UNITY_LINE_TYPE)(line), (message));}} while(0)
 #define UNITY_TEST_ASSERT_NULL(pointer, line, message)                                           UNITY_TEST_ASSERT(((pointer) == NULL),  (UNITY_LINE_TYPE)(line), (message))
 #define UNITY_TEST_ASSERT_NOT_NULL(pointer, line, message)                                       UNITY_TEST_ASSERT(((pointer) != NULL),  (UNITY_LINE_TYPE)(line), (message))
+#define UNITY_TEST_ASSERT_EMPTY(pointer, line, message)                                          UNITY_TEST_ASSERT(((pointer[0]) == 0),  (UNITY_LINE_TYPE)(line), (message))
+#define UNITY_TEST_ASSERT_NOT_EMPTY(pointer, line, message)                                      UNITY_TEST_ASSERT(((pointer[0]) != 0),  (UNITY_LINE_TYPE)(line), (message))
 
 #define UNITY_TEST_ASSERT_EQUAL_INT(expected, actual, line, message)                             UnityAssertEqualNumber((UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
 #define UNITY_TEST_ASSERT_EQUAL_INT8(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
@@ -771,6 +806,19 @@ int UnityTestMatches(void);
 #define UNITY_TEST_ASSERT_EQUAL_CHAR(expected, actual, line, message)                            UnityAssertEqualNumber((UNITY_INT)(UNITY_INT8 )(expected), (UNITY_INT)(UNITY_INT8 )(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR)
 #define UNITY_TEST_ASSERT_BITS(mask, expected, actual, line, message)                            UnityAssertBits((UNITY_INT)(mask), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line))
 
+#define UNITY_TEST_ASSERT_NOT_EQUAL_INT(threshold, actual, line, message)                        UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),               (UNITY_INT)(actual),               UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_INT8(threshold, actual, line, message)                       UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold),  (UNITY_INT)(UNITY_INT8 )(actual),  UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_INT16(threshold, actual, line, message)                      UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold),  (UNITY_INT)(UNITY_INT16)(actual),  UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_INT32(threshold, actual, line, message)                      UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT32)(threshold),  (UNITY_INT)(UNITY_INT32)(actual),  UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_UINT(threshold, actual, line, message)                       UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),               (UNITY_INT)(actual),               UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_UINT8(threshold, actual, line, message)                      UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_UINT16(threshold, actual, line, message)                     UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_UINT32(threshold, actual, line, message)                     UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_HEX8(threshold, actual, line, message)                       UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT8 )(threshold), (UNITY_INT)(UNITY_UINT8 )(actual), UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_HEX16(threshold, actual, line, message)                      UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT16)(threshold), (UNITY_INT)(UNITY_UINT16)(actual), UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX16)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_HEX32(threshold, actual, line, message)                      UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_UINT32)(threshold), (UNITY_INT)(UNITY_UINT32)(actual), UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX32)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_CHAR(threshold, actual, line, message)                       UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold),  (UNITY_INT)(UNITY_INT8 )(actual),  UNITY_NOT_EQUAL, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_CHAR)
+
 #define UNITY_TEST_ASSERT_GREATER_THAN_INT(threshold, actual, line, message)                     UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold),              (UNITY_INT)(actual),              UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT)
 #define UNITY_TEST_ASSERT_GREATER_THAN_INT8(threshold, actual, line, message)                    UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT8 )(threshold), (UNITY_INT)(UNITY_INT8 )(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT8)
 #define UNITY_TEST_ASSERT_GREATER_THAN_INT16(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(UNITY_INT16)(threshold), (UNITY_INT)(UNITY_INT16)(actual), UNITY_GREATER_THAN, (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16)
@@ -841,7 +889,7 @@ int UnityTestMatches(void);
 #define UNITY_TEST_ASSERT_INT16_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UnityAssertNumbersArrayWithin((UNITY_UINT16)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT16, UNITY_ARRAY_TO_ARRAY)
 #define UNITY_TEST_ASSERT_INT32_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UnityAssertNumbersArrayWithin((UNITY_UINT32)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT32, UNITY_ARRAY_TO_ARRAY)
 #define UNITY_TEST_ASSERT_UINT_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)    UnityAssertNumbersArrayWithin(              (delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT, UNITY_ARRAY_TO_ARRAY)
-#define UNITY_TEST_ASSERT_UINT8_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)  UnityAssertNumbersArrayWithin( (UNITY_UINT16)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8, UNITY_ARRAY_TO_ARRAY)
+#define UNITY_TEST_ASSERT_UINT8_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)   UnityAssertNumbersArrayWithin((UNITY_UINT16)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT8, UNITY_ARRAY_TO_ARRAY)
 #define UNITY_TEST_ASSERT_UINT16_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)  UnityAssertNumbersArrayWithin((UNITY_UINT16)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT16, UNITY_ARRAY_TO_ARRAY)
 #define UNITY_TEST_ASSERT_UINT32_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)  UnityAssertNumbersArrayWithin((UNITY_UINT32)(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT32, UNITY_ARRAY_TO_ARRAY)
 #define UNITY_TEST_ASSERT_HEX8_ARRAY_WITHIN(delta, expected, actual, num_elements, line, message)    UnityAssertNumbersArrayWithin((UNITY_UINT8 )(delta), (UNITY_INTERNAL_PTR)(expected), (UNITY_INTERNAL_PTR)(actual), ((UNITY_UINT32)(num_elements)), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX8, UNITY_ARRAY_TO_ARRAY)
@@ -900,6 +948,9 @@ int UnityTestMatches(void);
 #define UNITY_TEST_ASSERT_INT64_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
 #define UNITY_TEST_ASSERT_UINT64_WITHIN(delta, expected, actual, line, message)                  UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
 #define UNITY_TEST_ASSERT_HEX64_WITHIN(delta, expected, actual, line, message)                   UnityAssertNumbersWithin((delta), (UNITY_INT)(expected), (UNITY_INT)(actual), (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_INT64(threshold, actual, line, message)                      UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_NOT_EQUAL,        (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_UINT64(threshold, actual, line, message)                     UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_NOT_EQUAL,        (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
+#define UNITY_TEST_ASSERT_NOT_EQUAL_HEX64(threshold, actual, line, message)                      UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_NOT_EQUAL,        (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)
 #define UNITY_TEST_ASSERT_GREATER_THAN_INT64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_INT64)
 #define UNITY_TEST_ASSERT_GREATER_THAN_UINT64(threshold, actual, line, message)                  UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_UINT64)
 #define UNITY_TEST_ASSERT_GREATER_THAN_HEX64(threshold, actual, line, message)                   UnityAssertGreaterOrLessOrEqualNumber((UNITY_INT)(threshold), (UNITY_INT)(actual), UNITY_GREATER_THAN,     (message), (UNITY_LINE_TYPE)(line), UNITY_DISPLAY_STYLE_HEX64)

From a3827b87fe6504bdb5acde3d09a49044498467ef Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 09:30:42 +0700
Subject: [PATCH 1270/2085] test ci paths

---
 .github/workflows/build_arm.yml | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 56200465b..56ba88669 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -1,11 +1,14 @@
 name: Build ARM
 
 on:
-  pull_request:
   push:
-  release:
-    types:
-      - created
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
+  pull_request:
+    branches: [ master ]
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}

From 91d5fa5639a2330793b8e8828c4077911cdd2acd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 09:44:26 +0700
Subject: [PATCH 1271/2085] add paths to all workflows

---
 .github/workflows/build_aarch64.yml | 16 ++++++++++++----
 .github/workflows/build_arm.yml     |  5 +++++
 .github/workflows/build_esp.yml     | 16 ++++++++++++----
 .github/workflows/build_msp430.yml  | 16 ++++++++++++----
 .github/workflows/build_renesas.yml | 16 ++++++++++++----
 .github/workflows/build_riscv.yml   | 16 ++++++++++++----
 .github/workflows/pre-commit.yml    |  2 +-
 .github/workflows/test_hardware.yml | 17 +++++++++++++----
 8 files changed, 79 insertions(+), 25 deletions(-)

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 49973fe41..ccfca6316 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -1,11 +1,19 @@
 name: Build AArch64
 
 on:
-  pull_request:
   push:
-  release:
-    types:
-      - created
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 56ba88669..d1b94c47b 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -9,6 +9,11 @@ on:
       - 'hw'
   pull_request:
     branches: [ master ]
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index d775e50b6..7f2c292fa 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -1,11 +1,19 @@
 name: Build ESP
 
 on:
-  pull_request:
   push:
-  release:
-    types:
-      - created
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index d28341e5b..f41344e30 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -1,11 +1,19 @@
 name: Build MSP430
 
 on:
-  pull_request:
   push:
-  release:
-    types:
-      - created
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 6cb873dd8..d6550ed6d 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -1,11 +1,19 @@
 name: Build Renesas
 
 on:
-  pull_request:
   push:
-  release:
-    types:
-      - created
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 18e952d92..257050a53 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -1,11 +1,19 @@
 name: Build RISC-V
 
 on:
-  pull_request:
   push:
-  release:
-    types:
-      - created
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index 2463903f8..c0261ec66 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -20,7 +20,7 @@ jobs:
     - name: Setup Ruby
       uses: ruby/setup-ruby@v1
       with:
-        ruby-version: '2.7'
+        ruby-version: '3.0'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 3ef1fdc56..622b079da 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -1,10 +1,19 @@
 name: Hardware Test
+
 on:
-  pull_request:
   push:
-  release:
-    types:
-      - created
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src'
+      - 'examples'
+      - 'lib'
+      - 'hw'
 
 # Hardware in the loop (HIL)
 # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user

From 4b50ca2a6167ceb7eb3e07b8d1d716152fc7d189 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 09:54:15 +0700
Subject: [PATCH 1272/2085] add missing ceedling files

---
 .../ceedling/plugins/bullseye/README.md       |  76 ++++
 .../ceedling/plugins/colour_report/README.md  |  20 ++
 .../plugins/compile_commands_json/README.md   |  29 ++
 .../lib/compile_commands_json.rb              |  35 ++
 .../ceedling/plugins/dependencies/README.md   | 254 ++++++++++++++
 .../plugins/dependencies/config/defaults.yml  |   5 +
 .../plugins/dependencies/dependencies.rake    | 147 ++++++++
 .../plugins/dependencies/lib/dependencies.rb  | 237 +++++++++++++
 .../plugins/gcov/config/defaults_gcov.rb      | 118 +++++++
 .../plugins/gcov/lib/gcovr_reportinator.rb    | 331 ++++++++++++++++++
 .../gcov/lib/reportgenerator_reportinator.rb  | 195 +++++++++++
 .../plugins/gcov/lib/reportinator_helper.rb   |  15 +
 .../plugins/json_tests_report/README.md       |  36 ++
 .../lib/json_tests_report.rb                  |  83 +++++
 .../plugins/module_generator/README.md        | 119 +++++++
 .../plugins/raw_output_report/README.md       |  19 +
 .../stdout_gtestlike_tests_report/README.md   |  19 +
 .../plugins/stdout_ide_tests_report/README.md |  18 +
 .../stdout_pretty_tests_report/README.md      |  20 ++
 .../plugins/teamcity_tests_report/README.md   |  18 +
 .../plugins/warnings_report/README.md         |  19 +
 .../vendor/c_exception/lib/meson.build        |  11 +
 ...cmock_generator_plugin_ignore_stateless.rb |  85 +++++
 23 files changed, 1909 insertions(+)
 create mode 100644 test/vendor/ceedling/plugins/bullseye/README.md
 create mode 100644 test/vendor/ceedling/plugins/colour_report/README.md
 create mode 100644 test/vendor/ceedling/plugins/compile_commands_json/README.md
 create mode 100644 test/vendor/ceedling/plugins/compile_commands_json/lib/compile_commands_json.rb
 create mode 100644 test/vendor/ceedling/plugins/dependencies/README.md
 create mode 100644 test/vendor/ceedling/plugins/dependencies/config/defaults.yml
 create mode 100644 test/vendor/ceedling/plugins/dependencies/dependencies.rake
 create mode 100644 test/vendor/ceedling/plugins/dependencies/lib/dependencies.rb
 create mode 100644 test/vendor/ceedling/plugins/gcov/config/defaults_gcov.rb
 create mode 100644 test/vendor/ceedling/plugins/gcov/lib/gcovr_reportinator.rb
 create mode 100644 test/vendor/ceedling/plugins/gcov/lib/reportgenerator_reportinator.rb
 create mode 100644 test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb
 create mode 100644 test/vendor/ceedling/plugins/json_tests_report/README.md
 create mode 100644 test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb
 create mode 100644 test/vendor/ceedling/plugins/module_generator/README.md
 create mode 100644 test/vendor/ceedling/plugins/raw_output_report/README.md
 create mode 100644 test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md
 create mode 100644 test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md
 create mode 100644 test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md
 create mode 100644 test/vendor/ceedling/plugins/teamcity_tests_report/README.md
 create mode 100644 test/vendor/ceedling/plugins/warnings_report/README.md
 create mode 100644 test/vendor/ceedling/vendor/c_exception/lib/meson.build
 create mode 100644 test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_stateless.rb

diff --git a/test/vendor/ceedling/plugins/bullseye/README.md b/test/vendor/ceedling/plugins/bullseye/README.md
new file mode 100644
index 000000000..ab0b53b45
--- /dev/null
+++ b/test/vendor/ceedling/plugins/bullseye/README.md
@@ -0,0 +1,76 @@
+ceedling-bullseye
+=================
+
+# Plugin Overview
+
+Plugin for integrating Bullseye code coverage tool into Ceedling projects.
+This plugin requires a working license to Bullseye code coverage tools. The tools
+must be within the path or the path should be added to the environment in the 
+`project.yml file`.
+
+## Configuration
+
+The bullseye plugin supports configuration options via your `project.yml` provided
+by Ceedling. The following is a typical configuration example:
+
+```
+:bullseye:
+  :auto_license: TRUE
+:plugins:
+  :bullseye_lib_path: []
+:paths:
+  :bullseye_toolchain_include: []
+
+:tools:
+  :bullseye_instrumentation:
+    :executable: covc
+    :arguments:
+      - '--file $': ENVIRONMENT_COVFILE
+      - -q
+      - ${1}
+  :bullseye_compiler:
+    :executable: gcc
+    :arguments:
+      - -g
+      - -I"$": COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR
+      - -I"$": COLLECTION_PATHS_BULLSEYE_TOOLCHAIN_INCLUDE
+      - -D$: COLLECTION_DEFINES_TEST_AND_VENDOR
+      - -DBULLSEYE_COMPILER
+      - -c "${1}"
+      - -o "${2}"
+  :bullseye_linker:
+    :executable: gcc
+    :arguments:
+      - ${1}
+      - -o ${2}
+      - -L$: PLUGINS_BULLSEYE_LIB_PATH
+      - -lcov
+  :bullseye_fixture:
+    :executable: ${1}
+  :bullseye_report_covsrc:
+    :executable: covsrc
+    :arguments:
+      - '--file $': ENVIRONMENT_COVFILE
+      - -q
+      - -w140
+  :bullseye_report_covfn:
+    :executable: covfn
+    :stderr_redirect: :auto
+    :arguments:
+      - '--file $': ENVIRONMENT_COVFILE
+      - --width 120
+      - --no-source
+      - '"${1}"'
+  :bullseye_browser:
+    :executable: CoverageBrowser
+    :background_exec: :auto
+    :optional: TRUE
+    :arguments:
+      - '"$"': ENVIRONMENT_COVFILE
+```
+
+## Example Usage
+
+```sh
+ceedling bullseye:all utils:bullseye
+```
diff --git a/test/vendor/ceedling/plugins/colour_report/README.md b/test/vendor/ceedling/plugins/colour_report/README.md
new file mode 100644
index 000000000..4e0fcd45e
--- /dev/null
+++ b/test/vendor/ceedling/plugins/colour_report/README.md
@@ -0,0 +1,20 @@
+ceedling-colour-report
+======================
+
+## Overview
+
+The colour_report replaces the normal ceedling "pretty" output with 
+a colorized variant, in order to make the results easier to read from
+a standard command line. This is very useful on developer machines, but
+can occasionally cause problems with parsing on CI servers.
+
+## Setup
+
+Enable the plugin in your project.yml by adding `colour_report`
+to the list of enabled plugins.
+
+``` YAML
+:plugins:
+  :enabled:
+    - colour_report
+```
diff --git a/test/vendor/ceedling/plugins/compile_commands_json/README.md b/test/vendor/ceedling/plugins/compile_commands_json/README.md
new file mode 100644
index 000000000..ea80b7397
--- /dev/null
+++ b/test/vendor/ceedling/plugins/compile_commands_json/README.md
@@ -0,0 +1,29 @@
+compile_commands_json
+=====================
+
+## Overview
+
+Syntax highlighting and code completion are hard. Historically each editor or IDE has implemented their own and then competed amongst themselves to offer the best experience for developers. Often developers would still to an IDE that felt cumbersome and slow just because it had the best syntax highlighting on the market. If doing it for one language is hard (and it is) imagine doing it for dozens of them. Imagine a full stack developer who has to work with CSS, HTML, JavaScript and some Ruby - they need excellent support in all those languages which just made things even harder.
+
+In June of 2016, Microsoft with Red Hat and Codenvy got together to create a standard called the Language Server Protocol (LSP). The idea was simple, by standardising on one protocol, all the IDEs and editors out there would only have to support LSP, and not have custom plugins for each language. In turn, the backend code that actually does the highlighting can be written once and used by any IDE that supports LSP. Many editors already support it such as Sublime Text, vim and emacs. This means that if you're using a crufty old IDE or worse, you're using a shiny new editor without code completion, then this could be just the upgrade you're looking for!
+
+For C and C++ projects, many people use the `clangd` backend. So that it can do things like "go to definition", `clangd` needs to know how to build the project so that it can figure out all the pieces to the puzzle. There are manual tools such as `bear` which can be run with `gcc` or `clang` to extract this information it has a big limitation in that if run with `ceedling release` you won't get any auto completion for Unity and you'll also get error messages reported by your IDE because of what it perceives as missing headers. If you do the same with `ceedling test` now you get Unity but you might miss things that are only seen in the release build.
+
+This plugin resolves that issue. As it is run by Ceedling, it has access to all the build information it needs to create the perfect `compile_commands.json`. Once enabled, this plugin will generate that file and place it in `./build/artifacts/compile_commands.json`. `clangd` will search your project for this file, but it is easier to symlink it into the root directory (for example `ln -s ./build/artifacts/compile_commands.json`. 
+
+For more information on LSP and to find out if your editor supports it, check out https://langserver.org/
+
+## Setup
+
+Enable the plugin in your project.yml by adding `compile_commands_json` to the list
+of enabled plugins.
+
+``` YAML
+:plugins:
+  :enabled:
+    - compile_commands_json
+```
+
+## Configuration
+
+There is no additional configuration necessary to run this plugin.
diff --git a/test/vendor/ceedling/plugins/compile_commands_json/lib/compile_commands_json.rb b/test/vendor/ceedling/plugins/compile_commands_json/lib/compile_commands_json.rb
new file mode 100644
index 000000000..269cea4de
--- /dev/null
+++ b/test/vendor/ceedling/plugins/compile_commands_json/lib/compile_commands_json.rb
@@ -0,0 +1,35 @@
+require 'ceedling/plugin'
+require 'ceedling/constants'
+require 'json'
+
+class CompileCommandsJson < Plugin
+  def setup
+    @fullpath = File.join(PROJECT_BUILD_ARTIFACTS_ROOT, "compile_commands.json")
+    @database = if (File.exists?(@fullpath))
+                  JSON.parse( File.read(@fullpath) )
+                else
+                  []
+                end
+  end
+
+  def post_compile_execute(arg_hash)
+
+    # Create the new Entry
+    value = {
+      "directory" => Dir.pwd,
+      "command" => arg_hash[:shell_command],
+      "file" => arg_hash[:source]
+    }
+
+    # Determine if we're updating an existing file description or adding a new one
+    index = @database.index {|h| h["file"] == arg_hash[:source]}
+    if index
+      @database[index] = value
+    else
+      @database << value
+    end
+
+    # Update the Actual compile_commands.json file
+    File.open(@fullpath,'w') {|f| f << JSON.pretty_generate(@database)}
+  end
+end
diff --git a/test/vendor/ceedling/plugins/dependencies/README.md b/test/vendor/ceedling/plugins/dependencies/README.md
new file mode 100644
index 000000000..256467dfa
--- /dev/null
+++ b/test/vendor/ceedling/plugins/dependencies/README.md
@@ -0,0 +1,254 @@
+ceedling-dependencies
+=====================
+
+Plugin for supporting release dependencies. It's rare for an embedded project to
+be built completely free of other libraries and modules. Some of these may be
+standard internal libraries. Some of these may be 3rd party libraries. In either
+case, they become part of the project's ecosystem.
+
+This plugin is intended to make that relationship easier. It allows you to specify
+a source for dependencies. If required, it will automatically grab the appropriate
+version of that dependency.
+
+Most 3rd party libraries have a method of building already in place. While we'd
+love to convert the world to a place where everything downloads with a test suite
+in Ceedling, that's not likely to happen anytime soon. Until then, this plugin
+will allow the developer to specify what calls Ceedling should make to oversee
+the build process of those third party utilities. Are they using Make? CMake? A
+custom series of scripts that only a mad scientist could possibly understand? No
+matter. Ceedling has you covered. Just specify what should be called, and Ceedling
+will make it happen whenever it notices that the output artifacts are missing.
+
+Output artifacts? Sure! Things like static and dynamic libraries, or folders
+containing header files that might want to be included by your release project.
+
+So how does all this magic work?
+
+First, you need to add the `:dependencies` plugin to your list. Then, we'll add a new
+section called :dependencies. There, you can list as many dependencies as you desire. Each
+has a series of fields which help Ceedling to understand your needs. Many of them are
+optional. If you don't need that feature, just don't include it! In the end, it'll look
+something like this:
+
+```
+:dependencies:
+  :libraries:
+    - :name: WolfSSL
+      :source_path:   third_party/wolfssl/source
+      :build_path:    third_party/wolfssl/build
+      :artifact_path: third_party/wolfssl/install
+      :fetch:
+        :method: :zip
+        :source: \\shared_drive\third_party_libs\wolfssl\wolfssl-4.2.0.zip
+      :environment:
+        - CFLAGS+=-DWOLFSSL_DTLS_ALLOW_FUTURE
+      :build:
+        - "autoreconf -i"
+        - "./configure --enable-tls13 --enable-singlethreaded"
+        - make
+        - make install
+      :artifacts:
+        :static_libraries:
+          - lib/wolfssl.a
+        :dynamic_libraries:
+          - lib/wolfssl.so
+        :includes:
+          - include/**
+```
+
+Let's take a deeper look at each of these features.
+
+The Starting Dash & Name
+------------------------
+
+Yes, that opening dash tells the dependencies plugin that the rest of these fields
+belong to our first dependency. If we had a second dependency, we'd have another
+dash, lined up with the first, and followed by all the fields indented again.
+
+By convention, we use the `:name` field as the first field for each tool. Ceedling
+honestly doesn't care which order the fields are given... but as humans, it makes
+it easier for us to see the name of each dependency with starting dash.
+
+The name field is only used to print progress while we're running Ceedling. You may
+call the name of the field whatever you wish.
+
+Working Folders
+---------------
+
+The `:source_path` field allows us to specify where the source code for each of our
+dependencies is stored. If fetching the dependency from elsewhere, it will be fetched
+to this location. All commands to build this dependency will be executed from
+this location (override this by specifying a `:build_path`). Finally, the output
+artifacts will be referenced to this location (override this by specifying a `:artifact_path`)
+
+If unspecified, the `:source_path` will be `dependencies\dep_name` where `dep_name`
+is the name specified in `:name` above (with special characters removed). It's best,
+though, if you specify exactly where you want your dependencies to live.
+
+If the dependency is directly included in your project (you've specified `:none` as the
+`:method` for fetching), then `:source_path` should be where your Ceedling can find the
+source for your dependency in you repo.
+
+All artifacts are relative to the `:artifact_path` (which defaults to be the same as
+`:source_path`)
+
+Fetching Dependencies
+---------------------
+
+The `:dependencies` plugin supports the ability to automatically fetch your dependencies
+for you... using some common methods of fetching source. This section contains only a
+couple of fields:
+
+- `:method` -- This is the method that this dependency is fetched.
+  - `:none` -- This tells Ceedling that the code is already included in the project.
+  - `:zip` -- This tells Ceedling that we want to unpack a zip file to our source path.
+  - `:git` -- This tells Ceedling that we want to clone a git repo to our source path.
+  - `:svn` -- This tells Ceedling that we want to checkout a subversion repo to our source path.
+  - `:custom` -- This tells Ceedling that we want to use a custom command or commands to fetch the code.
+- `:source` -- This is the path or url to fetch code when using the zip or git method.
+- `:tag`/`:branch` -- This is the specific tag or branch that you wish to retrieve (git only. optional).
+- `:hash` -- This is the specific SHA1 hash you want to fetch (git only. optional, requires a deep clone).
+- `:revision` -- This is the specific revision you want to fetch (svn only. optional).
+- `:executable` -- This is a list of commands to execute when using the `:custom` method
+
+
+Environment Variables
+---------------------
+
+Many build systems support customization through environment variables. By specifying
+an array of environment variables, Ceedling will customize the shell environment before
+calling the build process.
+
+Environment variables may be specified in three ways. Let's look at one of each:
+
+```
+  :environment:
+    - ARCHITECTURE=ARM9
+    - CFLAGS+=-DADD_AWESOMENESS
+    - CFLAGS-=-DWASTE
+```
+
+In the first example, you see the most straightforward method. The environment variable
+`ARCHITECTURE` is set to the value `ARM9`. That's it. Simple.
+
+The next two options modify an existing symbol. In the first one, we use `+=`, which tells
+Ceedling to add the define `ADD_AWESOMENESS` to the environment variable `CFLAGS`. The second
+tells Ceedling to remove the define `WASTE` from the same environment variable.
+
+There are a couple of things to note here.
+
+First, when adding to a variable, Ceedling has no way of knowing
+what delimiter you are expecting. In this example you can see we manually added some whitespace.
+If we had been modifying `PATH` instead, we might have had to use a `:` on a unux or `;` on
+Windows.
+
+Second, removing an argument will have no effect on the argument if that argument isn't found
+precisely. It's case sensitive and the entire string must match. If symbol doesn't already exist,
+it WILL after executing this command... however it will be assigned to nothing.
+
+Building Dependencies
+---------------------
+
+The heart of the `:dependencies` plugin is the ability for you, the developer, to specify the
+build process for each of your dependencies. You will need to have any required tools installed
+before using this feature.
+
+The steps are specified as an array of strings. Ceedling will execute those steps in the order
+specified, moving from step to step unless an error is encountered. By the end of the process,
+the artifacts should have been created by your process... otherwise an error will be produced.
+
+Artifacts
+---------
+
+These are the outputs of the build process. There are there types of artifacts. Any dependency
+may have none or some of these. Calling out these files tells Ceedling that they are important.
+Your dependency's build process may produce many other files... but these are the files that
+Ceedling understands it needs to act on.
+
+### `static_libraries`
+
+Specifying one or more static libraries will tell Ceedling where it should find static libraries
+output by your build process. These libraries are automatically added to the list of dependencies
+and will be linked with the rest of your code to produce the final release.
+
+If any of these libraries don't exist, Ceedling will trigger your build process in order for it
+to produce them.
+
+### `dynamic_libraries`
+
+Specifying one or more dynamic libraries will tell Ceedling where it should find dynamic libraries
+output by your build process. These libraries are automatically copied to the same folder as your
+final release binary.
+
+If any of these libraries don't exist, Ceedling will trigger your build process in order for it
+to produce them.
+
+### `includes`
+
+Often when libraries are built, the same process will output a collection of includes so that
+your release code knows how to interact with that library. It's the public API for that library.
+By specifying the directories that will contain these includes (don't specify the files themselves,
+Ceedling only needs the directories), Ceedling is able to automatically add these to its internal
+include list. This allows these files to be used while building your release code, as well we making
+them mockable during unit testing.
+
+### `source`
+
+It's possible that your external dependency will just produce additional C files as its output.
+In this case, Ceedling is able to automatically add these to its internal source list. This allows
+these files to be used while building your release code.
+
+Tasks
+-----
+
+Once configured correctly, the `:dependencies` plugin should integrate seamlessly into your
+workflow and you shouldn't have to think about it. In the real world, that doesn't always happen.
+Here are a number of tasks that are added or modified by this plugin.
+
+### `ceedling dependencies:clean`
+
+This can be issued in order to completely remove the dependency from its source path. On the
+next build, it will be refetched and rebuilt from scratch. This can also apply to a particular
+dependency. For example, by specifying `dependencies:clean:DepName`.
+
+### `ceedling dependencies:fetch`
+
+This can be issued in order to fetch each dependency from its origin. This will have no effect on
+dependencies that don't have fetch instructions specified. This can also apply to a particular
+dependency. For example, by specifying `dependencies:fetch:DepName`.
+
+### `ceedling dependencies:make`
+
+This will force the dependencies to all build. This should happen automatically when a release
+has been triggered... but if you're just getting your dependency configured at this moment, you
+may want to just use this feature instead. A single dependency can also be built by specifying its
+name, like `dependencies:make:MyTunaBoat`.
+
+### `ceedling dependencies:deploy`
+
+This will force any dynamic libraries produced by your dependencies to be copied to your release
+build directory... just in case you clobbered them.
+
+### `paths:include`
+
+Maybe you want to verify that all the include paths are correct. If you query Ceedling with this
+request, it will list all the header file paths that it's found, including those produced by
+dependencies.
+
+### `files:include`
+
+Maybe you want to take that query further and actually get a list of ALL the header files
+Ceedling has found, including those belonging to your dependencies.
+
+Testing
+=======
+
+Hopefully all your dependencies are fully tested... but we can't always depend on that.
+In the event that they are tested with Ceedling, you'll probably want to consider using
+the `:subprojects` plugin instead of this one. The purpose of this plugin is to pull in
+third party code for release... and to provide a mockable interface for Ceedling to use
+during its tests of other modules.
+
+If that's what you're after... you've found the right plugin!
+
+Happy Testing!
diff --git a/test/vendor/ceedling/plugins/dependencies/config/defaults.yml b/test/vendor/ceedling/plugins/dependencies/config/defaults.yml
new file mode 100644
index 000000000..0415f8ea1
--- /dev/null
+++ b/test/vendor/ceedling/plugins/dependencies/config/defaults.yml
@@ -0,0 +1,5 @@
+---
+:dependencies:
+  :libraries: []
+
+...
diff --git a/test/vendor/ceedling/plugins/dependencies/dependencies.rake b/test/vendor/ceedling/plugins/dependencies/dependencies.rake
new file mode 100644
index 000000000..08a1a48eb
--- /dev/null
+++ b/test/vendor/ceedling/plugins/dependencies/dependencies.rake
@@ -0,0 +1,147 @@
+
+DEPENDENCIES_LIBRARIES.each do |deplib|
+
+  # Look up the name of this dependency library
+  deplib_name = @ceedling[DEPENDENCIES_SYM].get_name(deplib)
+
+  # Make sure the required working directories exists
+  # (don't worry about the subdirectories. That's the job of the dep's build tool)
+  paths = @ceedling[DEPENDENCIES_SYM].get_working_paths(deplib)
+  paths.each {|path| directory(path) }
+  task :directories => paths
+
+  all_deps = @ceedling[DEPENDENCIES_SYM].get_static_libraries_for_dependency(deplib) +
+             @ceedling[DEPENDENCIES_SYM].get_dynamic_libraries_for_dependency(deplib) +
+             @ceedling[DEPENDENCIES_SYM].get_include_directories_for_dependency(deplib) +
+             @ceedling[DEPENDENCIES_SYM].get_source_files_for_dependency(deplib)
+
+  # Add a rule for building the actual libraries from dependency list
+  (@ceedling[DEPENDENCIES_SYM].get_static_libraries_for_dependency(deplib) +
+   @ceedling[DEPENDENCIES_SYM].get_dynamic_libraries_for_dependency(deplib)
+  ).each do |libpath|
+    file libpath do |filetask|
+      path = filetask.name
+
+      # We double-check that it doesn't already exist, because this process sometimes
+      # produces multiple files, but they may have already been flagged as invoked
+      unless (File.exists?(path))
+
+        # Set Environment Variables, Fetch, and Build
+        @ceedling[DEPENDENCIES_SYM].set_env_if_required(path)
+        @ceedling[DEPENDENCIES_SYM].fetch_if_required(path)
+        @ceedling[DEPENDENCIES_SYM].build_if_required(path)
+      end
+    end
+  end
+
+  # Add a rule for building the source and includes from dependency list
+  (@ceedling[DEPENDENCIES_SYM].get_include_directories_for_dependency(deplib) +
+   @ceedling[DEPENDENCIES_SYM].get_source_files_for_dependency(deplib)
+  ).each do |libpath|
+    task libpath do |filetask|
+      path = filetask.name
+
+      unless (File.file?(path) || File.directory?(path))
+
+        # Set Environment Variables, Fetch, and Build
+        @ceedling[DEPENDENCIES_SYM].set_env_if_required(path)
+        @ceedling[DEPENDENCIES_SYM].fetch_if_required(path)
+        @ceedling[DEPENDENCIES_SYM].build_if_required(path)
+      end
+    end
+  end
+
+  # Give ourselves a way to trigger individual dependencies
+  namespace DEPENDENCIES_SYM do
+    namespace :deploy do
+      # Add task to directly just build this dependency
+      task(deplib_name => @ceedling[DEPENDENCIES_SYM].get_dynamic_libraries_for_dependency(deplib)) do |t,args|
+        @ceedling[DEPENDENCIES_SYM].deploy_if_required(deplib_name)
+      end
+    end
+
+    namespace :make do
+      # Add task to directly just build this dependency
+      task(deplib_name => all_deps)
+    end
+
+    namespace :clean do
+      # Add task to directly clobber this dependency
+      task(deplib_name) do
+        @ceedling[DEPENDENCIES_SYM].clean_if_required(deplib_name)
+      end
+    end
+
+    namespace :fetch do
+      # Add task to directly clobber this dependency
+      task(deplib_name) do
+        @ceedling[DEPENDENCIES_SYM].fetch_if_required(deplib_name)
+      end
+    end
+  end
+
+  # Add source files to our list of things to build during release
+  source_files = @ceedling[DEPENDENCIES_SYM].get_source_files_for_dependency(deplib)
+  task PROJECT_RELEASE_BUILD_TARGET => source_files
+
+  # Finally, add the static libraries to our RELEASE build dependency list
+  static_libs = @ceedling[DEPENDENCIES_SYM].get_static_libraries_for_dependency(deplib)
+  task RELEASE_SYM => static_libs
+
+  # Add the dynamic libraries to our RELEASE task dependency list so that they will be copied automatically
+  dynamic_libs = @ceedling[DEPENDENCIES_SYM].get_dynamic_libraries_for_dependency(deplib)
+  task RELEASE_SYM => dynamic_libs
+
+  # Add the include dirs / files to our list of dependencies for release
+  headers = @ceedling[DEPENDENCIES_SYM].get_include_directories_for_dependency(deplib)
+  task RELEASE_SYM => headers
+
+  # Paths to Libraries need to be Added to the Lib Path List
+  all_libs = static_libs + dynamic_libs
+  PATHS_LIBRARIES ||= []
+  all_libs.each {|lib| PATHS_LIBRARIES << File.dirname(lib) }
+  PATHS_LIBRARIES.uniq!
+  PATHS_LIBRARIES.reject!{|s| s.empty?}
+
+  # Libraries Need to be Added to the Library List
+  LIBRARIES_SYSTEM ||= []
+  all_libs.each {|lib| LIBRARIES_SYSTEM << File.basename(lib,'.*').sub(/^lib/,'') }
+  LIBRARIES_SYSTEM.uniq!
+  LIBRARIES_SYSTEM.reject!{|s| s.empty?}
+end
+
+# Add any artifact:include or :source folders to our release & test includes paths so linking and mocking work.
+@ceedling[DEPENDENCIES_SYM].add_headers_and_sources()
+
+# Add tasks for building or cleaning ALL depencies
+namespace DEPENDENCIES_SYM do
+  desc "Deploy missing dependencies."
+  task :deploy => DEPENDENCIES_LIBRARIES.map{|deplib| "#{DEPENDENCIES_SYM}:deploy:#{@ceedling[DEPENDENCIES_SYM].get_name(deplib)}"}
+
+  desc "Build any missing dependencies."
+  task :make => DEPENDENCIES_LIBRARIES.map{|deplib| "#{DEPENDENCIES_SYM}:make:#{@ceedling[DEPENDENCIES_SYM].get_name(deplib)}"}
+
+  desc "Clean all dependencies."
+  task :clean => DEPENDENCIES_LIBRARIES.map{|deplib| "#{DEPENDENCIES_SYM}:clean:#{@ceedling[DEPENDENCIES_SYM].get_name(deplib)}"}
+
+  desc "Fetch all dependencies."
+  task :fetch => DEPENDENCIES_LIBRARIES.map{|deplib| "#{DEPENDENCIES_SYM}:fetch:#{@ceedling[DEPENDENCIES_SYM].get_name(deplib)}"}
+end
+
+namespace :files do
+  desc "List all collected dependency libraries."
+  task :dependencies do
+    puts "dependency files:"
+    deps = []
+    DEPENDENCIES_LIBRARIES.each do |deplib|
+      deps << @ceedling[DEPENDENCIES_SYM].get_static_libraries_for_dependency(deplib)
+      deps << @ceedling[DEPENDENCIES_SYM].get_dynamic_libraries_for_dependency(deplib)
+    end
+    deps.flatten!
+    deps.sort.each {|dep| puts " - #{dep}"}
+    puts "file count: #{deps.size}"
+  end
+end
+
+# Make sure that we build dependencies before attempting to tackle any of the unit tests
+Rake::Task[:test_deps].enhance ['dependencies:make']
diff --git a/test/vendor/ceedling/plugins/dependencies/lib/dependencies.rb b/test/vendor/ceedling/plugins/dependencies/lib/dependencies.rb
new file mode 100644
index 000000000..fc8ae9968
--- /dev/null
+++ b/test/vendor/ceedling/plugins/dependencies/lib/dependencies.rb
@@ -0,0 +1,237 @@
+require 'ceedling/plugin'
+require 'ceedling/constants'
+
+DEPENDENCIES_ROOT_NAME         = 'dependencies'
+DEPENDENCIES_TASK_ROOT         = DEPENDENCIES_ROOT_NAME + ':'
+DEPENDENCIES_SYM               = DEPENDENCIES_ROOT_NAME.to_sym
+
+class Dependencies < Plugin
+
+  def setup
+    @plugin_root = File.expand_path(File.join(File.dirname(__FILE__), '..'))
+
+    # Set up a fast way to look up dependencies by name or static lib path
+    @dependencies = {}
+    @dynamic_libraries = []
+    DEPENDENCIES_LIBRARIES.each do |deplib|
+
+      @dependencies[ deplib[:name] ] = deplib.clone
+      all_deps = get_static_libraries_for_dependency(deplib) +
+                 get_dynamic_libraries_for_dependency(deplib) +
+                 get_include_directories_for_dependency(deplib) +
+                 get_source_files_for_dependency(deplib)
+      all_deps.each do |key|
+        @dependencies[key] = @dependencies[ deplib[:name] ]
+      end
+
+      @dynamic_libraries += get_dynamic_libraries_for_dependency(deplib)
+    end
+  end
+
+  def config
+    updates = {
+      :collection_paths_include => COLLECTION_PATHS_INCLUDE,
+      :collection_all_headers => COLLECTION_ALL_HEADERS,
+    }
+
+    @ceedling[DEPENDENCIES_SYM].get_include_directories_for_dependency(deplib).each do |incpath|
+      updates[:collection_paths_include] << incpath
+      Dir[ File.join(incpath, "*#{EXTENSION_HEADER}") ].each do |f|
+        updates[:collection_all_headers] << f
+      end
+    end
+
+    return updates
+  end
+
+  def get_name(deplib)
+    raise "Each dependency must have a name!" if deplib[:name].nil?
+    return deplib[:name].gsub(/\W*/,'')
+  end
+
+  def get_source_path(deplib)
+    return deplib[:source_path] || File.join('dependencies', get_name(deplib))
+  end
+
+  def get_build_path(deplib)
+    return deplib[:build_path] || deplib[:source_path] || File.join('dependencies', get_name(deplib))
+  end
+
+  def get_artifact_path(deplib)
+    return deplib[:artifact_path] || deplib[:source_path] || File.join('dependencies', get_name(deplib))
+  end
+
+  def get_working_paths(deplib)
+    paths = [deplib[:source_path], deplib[:build_path], deplib[:artifact_paths]].compact.uniq
+    paths = [ File.join('dependencies', get_name(deplib)) ] if (paths.empty?)
+    return paths
+  end
+
+  def get_static_libraries_for_dependency(deplib)
+    (deplib[:artifacts][:static_libraries] || []).map {|path| File.join(get_artifact_path(deplib), path)}
+  end
+
+  def get_dynamic_libraries_for_dependency(deplib)
+    (deplib[:artifacts][:dynamic_libraries] || []).map {|path| File.join(get_artifact_path(deplib), path)}
+  end
+
+  def get_source_files_for_dependency(deplib)
+    (deplib[:artifacts][:source] || []).map {|path| File.join(get_artifact_path(deplib), path)}
+  end
+
+  def get_include_directories_for_dependency(deplib)
+    paths = (deplib[:artifacts][:includes] || []).map {|path| File.join(get_artifact_path(deplib), path)}
+    @ceedling[:file_system_utils].collect_paths(paths)
+  end
+
+  def set_env_if_required(lib_path)
+    blob = @dependencies[lib_path]
+    raise "Could not find dependency '#{lib_path}'" if blob.nil?
+    return if (blob[:environment].nil?)
+    return if (blob[:environment].empty?)
+
+    blob[:environment].each do |e|
+      m = e.match(/^(\w+)\s*(\+?\-?=)\s*(.*)$/)
+      unless m.nil?
+        case m[2]
+        when "+="
+          ENV[m[1]] = (ENV[m[1]] || "") + m[3]
+        when "-="
+          ENV[m[1]] = (ENV[m[1]] || "").gsub(m[3],'')
+        else
+          ENV[m[1]] = m[3]
+        end
+      end
+    end
+  end
+
+  def fetch_if_required(lib_path)
+    blob = @dependencies[lib_path]
+    raise "Could not find dependency '#{lib_path}'" if blob.nil?
+    return if (blob[:fetch].nil?)
+    return if (blob[:fetch][:method].nil?)
+    return if (directory(blob[:source_path]) && !Dir.empty?(blob[:source_path]))
+
+    steps = case blob[:fetch][:method]
+            when :none
+              return
+            when :zip
+              [ "gzip -d #{blob[:fetch][:source]}" ]
+            when :git
+              branch = blob[:fetch][:tag] || blob[:fetch][:branch] || ''
+              branch = ("-b " + branch) unless branch.empty?
+              unless blob[:fetch][:hash].nil?
+                # Do a deep clone to ensure the commit we want is available
+                retval = [ "git clone #{branch} #{blob[:fetch][:source]} ." ]
+                # Checkout the specified commit
+                retval << "git checkout #{blob[:fetch][:hash]}"
+              else
+                # Do a thin clone
+                retval = [ "git clone #{branch} --depth 1 #{blob[:fetch][:source]} ." ]
+              end
+            when :svn
+              revision = blob[:fetch][:revision] || ''
+              revision = ("--revision " + branch) unless branch.empty?
+              retval = [ "svn checkout #{revision} #{blob[:fetch][:source]} ." ]
+              retval
+            when :custom
+              blob[:fetch][:executable]
+            else
+              raise "Unknown fetch method '#{blob[:fetch][:method].to_s}' for dependency '#{blob[:name]}'"
+            end
+
+    # Perform the actual fetching
+    @ceedling[:streaminator].stdout_puts("Fetching dependency #{blob[:name]}...", Verbosity::NORMAL)
+    Dir.chdir(get_source_path(blob)) do
+      steps.each do |step|
+        @ceedling[:tool_executor].exec( step )
+      end
+    end
+  end
+
+  def build_if_required(lib_path)
+    blob = @dependencies[lib_path]
+    raise "Could not find dependency '#{lib_path}'" if blob.nil?
+
+    # We don't clean anything unless we know how to fetch a new copy
+    if (blob[:build].nil? || blob[:build].empty?)
+      @ceedling[:streaminator].stdout_puts("Nothing to build for dependency #{blob[:name]}", Verbosity::NORMAL)
+      return
+    end
+
+    # Perform the build
+    @ceedling[:streaminator].stdout_puts("Building dependency #{blob[:name]}...", Verbosity::NORMAL)
+    Dir.chdir(get_build_path(blob)) do
+      blob[:build].each do |step|
+        @ceedling[:tool_executor].exec( step )
+      end
+    end
+  end
+
+  def clean_if_required(lib_path)
+    blob = @dependencies[lib_path]
+    raise "Could not find dependency '#{lib_path}'" if blob.nil?
+
+    # We don't clean anything unless we know how to fetch a new copy
+    if (blob[:fetch].nil? || blob[:fetch][:method].nil? || (blob[:fetch][:method] == :none))
+      @ceedling[:streaminator].stdout_puts("Nothing to clean for dependency #{blob[:name]}", Verbosity::NORMAL)
+      return
+    end
+
+    # Perform the actual Cleaning
+    @ceedling[:streaminator].stdout_puts("Cleaning dependency #{blob[:name]}...", Verbosity::NORMAL)
+    get_working_paths(blob).each do |path|
+      FileUtils.rm_rf(path) if File.directory?(path)
+    end
+  end
+
+  def deploy_if_required(lib_path)
+    blob = @dependencies[lib_path]
+    raise "Could not find dependency '#{lib_path}'" if blob.nil?
+
+    # We don't need to deploy anything if there isn't anything to deploy
+    if (blob[:artifacts].nil? || blob[:artifacts][:dynamic_libraries].nil?  || blob[:artifacts][:dynamic_libraries].empty?)
+      @ceedling[:streaminator].stdout_puts("Nothing to deploy for dependency #{blob[:name]}", Verbosity::NORMAL)
+      return
+    end
+
+    # Perform the actual Deploying
+    @ceedling[:streaminator].stdout_puts("Deploying dependency #{blob[:name]}...", Verbosity::NORMAL)
+    FileUtils.cp( lib_path, File.dirname(PROJECT_RELEASE_BUILD_TARGET) )
+  end
+
+  def add_headers_and_sources()
+    # Search for header file paths and files to add to our collections
+    DEPENDENCIES_LIBRARIES.each do |deplib|
+      get_include_directories_for_dependency(deplib).each do |header|
+        cfg = @ceedling[:configurator].project_config_hash
+        cfg[:collection_paths_include] << header
+        cfg[:collection_paths_source_and_include] << header
+        cfg[:collection_paths_test_support_source_include] << header
+        cfg[:collection_paths_test_support_source_include_vendor] << header
+        cfg[:collection_paths_release_toolchain_include] << header
+        Dir[ File.join(header, "*#{EXTENSION_HEADER}") ].each do |f|
+          cfg[:collection_all_headers] << f
+        end
+      end
+
+      get_source_files_for_dependency(deplib).each do |source|
+        cfg = @ceedling[:configurator].project_config_hash
+        cfg[:collection_paths_source_and_include] << source
+        cfg[:collection_paths_test_support_source_include] << source
+        cfg[:collection_paths_test_support_source_include_vendor] << source
+        cfg[:collection_paths_release_toolchain_include] << source
+        Dir[ File.join(source, "*#{EXTENSION_SOURCE}") ].each do |f|
+          cfg[:collection_all_source] << f
+        end
+      end
+    end
+
+    # Make all these updated files findable by Ceedling
+    @ceedling[:file_finder].prepare_search_sources()
+  end
+end
+
+# end blocks always executed following rake run
+END {
+}
diff --git a/test/vendor/ceedling/plugins/gcov/config/defaults_gcov.rb b/test/vendor/ceedling/plugins/gcov/config/defaults_gcov.rb
new file mode 100644
index 000000000..e3ce340dd
--- /dev/null
+++ b/test/vendor/ceedling/plugins/gcov/config/defaults_gcov.rb
@@ -0,0 +1,118 @@
+
+DEFAULT_GCOV_COMPILER_TOOL = {
+    :executable => ENV['CC'].nil? ? FilePathUtils.os_executable_ext('gcc').freeze : ENV['CC'].split[0],
+    :name => 'default_gcov_compiler'.freeze,
+    :stderr_redirect => StdErrRedirect::NONE.freeze,
+    :background_exec => BackgroundExec::NONE.freeze,
+    :optional => false.freeze,
+    :arguments => [
+      "-g".freeze,
+      "-fprofile-arcs".freeze,
+      "-ftest-coverage".freeze,
+      ENV['CC'].nil? ? "" : ENV['CC'].split[1..-1],
+      ENV['CPPFLAGS'].nil? ? "" : ENV['CPPFLAGS'].split,
+      {"-I\"$\"" => 'COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR'}.freeze,
+      {"-I\"$\"" => 'COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE'}.freeze,
+      {"-D$" => 'COLLECTION_DEFINES_TEST_AND_VENDOR'}.freeze,
+      "-DGCOV_COMPILER".freeze,
+      "-DCODE_COVERAGE".freeze,
+      ENV['CFLAGS'].nil? ? "" : ENV['CFLAGS'].split,
+      "-c \"${1}\"".freeze,
+      "-o \"${2}\"".freeze
+      ].freeze
+    }
+
+
+DEFAULT_GCOV_LINKER_TOOL = {
+    :executable => ENV['CCLD'].nil? ? FilePathUtils.os_executable_ext('gcc').freeze : ENV['CCLD'].split[0],
+    :name => 'default_gcov_linker'.freeze,
+    :stderr_redirect => StdErrRedirect::NONE.freeze,
+    :background_exec => BackgroundExec::NONE.freeze,
+    :optional => false.freeze,
+    :arguments => [
+        "-g".freeze,
+        "-fprofile-arcs".freeze,
+        "-ftest-coverage".freeze,
+        ENV['CCLD'].nil? ? "" : ENV['CCLD'].split[1..-1],
+        ENV['CFLAGS'].nil? ? "" : ENV['CFLAGS'].split,
+        ENV['LDFLAGS'].nil? ? "" : ENV['LDFLAGS'].split,
+        "\"${1}\"".freeze,
+        "-o \"${2}\"".freeze,
+        "${4}".freeze,
+        "${5}".freeze,
+        ENV['LDLIBS'].nil? ? "" : ENV['LDLIBS'].split
+        ].freeze
+    }
+
+DEFAULT_GCOV_FIXTURE_TOOL = {
+    :executable => '${1}'.freeze,
+    :name => 'default_gcov_fixture'.freeze,
+    :stderr_redirect => StdErrRedirect::NONE.freeze,
+    :background_exec => BackgroundExec::NONE.freeze,
+    :optional => false.freeze,
+    :arguments => [].freeze
+    }
+
+DEFAULT_GCOV_REPORT_TOOL = {
+    :executable => ENV['GCOV'].nil? ? FilePathUtils.os_executable_ext('gcov').freeze : ENV['GCOV'].split[0],
+    :name => 'default_gcov_report'.freeze,
+    :stderr_redirect => StdErrRedirect::NONE.freeze,
+    :background_exec => BackgroundExec::NONE.freeze,
+    :optional => false.freeze,
+    :arguments => [
+        "-n".freeze,
+        "-p".freeze,
+        "-b".freeze,
+        {"-o \"$\"" => 'GCOV_BUILD_OUTPUT_PATH'}.freeze,
+        "\"${1}\"".freeze
+        ].freeze
+    }
+
+DEFAULT_GCOV_GCOV_POST_REPORT_TOOL = {
+    :executable => ENV['GCOV'].nil? ? FilePathUtils.os_executable_ext('gcov').freeze : ENV['GCOV'].split[0],
+    :name => 'default_gcov_gcov_post_report'.freeze,
+    :stderr_redirect => StdErrRedirect::NONE.freeze,
+    :background_exec => BackgroundExec::NONE.freeze,
+    :optional => true.freeze,
+    :arguments => [
+        "-b".freeze,
+        "-c".freeze,
+        "-r".freeze,
+        "-x".freeze,
+        "${1}".freeze
+        ].freeze
+    }
+
+DEFAULT_GCOV_GCOVR_POST_REPORT_TOOL = {
+    :executable => 'gcovr'.freeze,
+    :name => 'default_gcov_gcovr_post_report'.freeze,
+    :stderr_redirect => StdErrRedirect::NONE.freeze,
+    :background_exec => BackgroundExec::NONE.freeze,
+    :optional => true.freeze,
+    :arguments => [
+        "${1}".freeze
+        ].freeze
+    }
+
+DEFAULT_GCOV_REPORTGENERATOR_POST_REPORT = {
+    :executable => 'reportgenerator'.freeze,
+    :name => 'default_gcov_reportgenerator_post_report'.freeze,
+    :stderr_redirect => StdErrRedirect::NONE.freeze,
+    :background_exec => BackgroundExec::NONE.freeze,
+    :optional => true.freeze,
+    :arguments => [
+        "${1}".freeze
+        ].freeze
+    }
+
+def get_default_config
+    return :tools => {
+        :gcov_compiler => DEFAULT_GCOV_COMPILER_TOOL,
+        :gcov_linker   => DEFAULT_GCOV_LINKER_TOOL,
+        :gcov_fixture  => DEFAULT_GCOV_FIXTURE_TOOL,
+        :gcov_report   => DEFAULT_GCOV_REPORT_TOOL,
+        :gcov_gcov_post_report => DEFAULT_GCOV_GCOV_POST_REPORT_TOOL,
+        :gcov_gcovr_post_report => DEFAULT_GCOV_GCOVR_POST_REPORT_TOOL,
+        :gcov_reportgenerator_post_report => DEFAULT_GCOV_REPORTGENERATOR_POST_REPORT
+    }
+end
diff --git a/test/vendor/ceedling/plugins/gcov/lib/gcovr_reportinator.rb b/test/vendor/ceedling/plugins/gcov/lib/gcovr_reportinator.rb
new file mode 100644
index 000000000..5317c5d24
--- /dev/null
+++ b/test/vendor/ceedling/plugins/gcov/lib/gcovr_reportinator.rb
@@ -0,0 +1,331 @@
+require 'reportinator_helper'
+
+class GcovrReportinator
+
+  def initialize(system_objects)
+    @ceedling = system_objects
+    @reportinator_helper = ReportinatorHelper.new
+  end
+
+
+  # Generate the gcovr report(s) specified in the options.
+  def make_reports(opts)
+    # Get the gcovr version number.
+    gcovr_version_info = get_gcovr_version()
+
+    # Build the common gcovr arguments.
+    args_common = args_builder_common(opts)
+
+    if ((gcovr_version_info[0] == 4) && (gcovr_version_info[1] >= 2)) || (gcovr_version_info[0] > 4)
+      # gcovr version 4.2 and later supports generating multiple reports with a single call.
+      args = args_common
+      args += args_builder_cobertura(opts, false)
+      args += args_builder_sonarqube(opts, false)
+      args += args_builder_json(opts, true)
+      # As of gcovr version 4.2, the --html argument must appear last.
+      args += args_builder_html(opts, false)
+
+      print "Creating gcov results report(s) in '#{GCOV_ARTIFACTS_PATH}'... "
+      STDOUT.flush
+
+      # Generate the report(s).
+      run(args)
+    else
+      # gcovr version 4.1 and earlier supports HTML and Cobertura XML reports.
+      # It does not support SonarQube and JSON reports.
+      # Reports must also be generated separately.
+      args_cobertura = args_builder_cobertura(opts, true)
+      args_html = args_builder_html(opts, true)
+
+      if args_html.length > 0
+        print "Creating a gcov HTML report in '#{GCOV_ARTIFACTS_PATH}'... "
+        STDOUT.flush
+
+        # Generate the HTML report.
+        run(args_common + args_html)
+      end
+
+      if args_cobertura.length > 0
+        print "Creating a gcov XML report in '#{GCOV_ARTIFACTS_PATH}'... "
+        STDOUT.flush
+
+        # Generate the Cobertura XML report.
+        run(args_common + args_cobertura)
+      end
+    end
+
+    # Determine if the gcovr text report is enabled. Defaults to disabled.
+    if is_report_enabled(opts, ReportTypes::TEXT)
+      make_text_report(opts, args_common)
+    end
+  end
+
+
+  def support_deprecated_options(opts)
+    # Support deprecated :html_report: and ":html_report_type: basic" options.
+    if !is_report_enabled(opts, ReportTypes::HTML_BASIC) && (opts[:gcov_html_report] || (opts[:gcov_html_report_type].is_a? String) && (opts[:gcov_html_report_type].casecmp("basic") == 0))
+      opts[:gcov_reports].push(ReportTypes::HTML_BASIC)
+    end
+
+    # Support deprecated ":html_report_type: detailed" option.
+    if !is_report_enabled(opts, ReportTypes::HTML_DETAILED) && (opts[:gcov_html_report_type].is_a? String) && (opts[:gcov_html_report_type].casecmp("detailed") == 0)
+      opts[:gcov_reports].push(ReportTypes::HTML_DETAILED)
+    end
+
+    # Support deprecated :xml_report: option.
+    if opts[:gcov_xml_report]
+      opts[:gcov_reports].push(ReportTypes::COBERTURA)
+    end
+
+    # Default to HTML basic report when no report types are defined.
+    if opts[:gcov_reports].empty? && opts[:gcov_html_report_type].nil? && opts[:gcov_xml_report].nil?
+      opts[:gcov_reports] = [ReportTypes::HTML_BASIC]
+
+      puts "In your project.yml, define one or more of the"
+      puts "following to specify which reports to generate."
+      puts "For now, creating only an #{ReportTypes::HTML_BASIC} report."
+      puts ""
+      puts ":gcov:"
+      puts "  :reports:"
+      puts "    - #{ReportTypes::HTML_BASIC}"
+      puts "    - #{ReportTypes::HTML_DETAILED}"
+      puts "    - #{ReportTypes::TEXT}"
+      puts "    - #{ReportTypes::COBERTURA}"
+      puts "    - #{ReportTypes::SONARQUBE}"
+      puts "    - #{ReportTypes::JSON}"
+      puts ""
+    end
+  end
+
+
+  private
+
+  GCOVR_SETTING_PREFIX = "gcov_gcovr"
+
+  # Build the gcovr report generation common arguments.
+  def args_builder_common(opts)
+    gcovr_opts = get_opts(opts)
+
+    args = ""
+    args += "--root \"#{gcovr_opts[:report_root] || '.'}\" "
+    args += "--config \"#{gcovr_opts[:config_file]}\" " unless gcovr_opts[:config_file].nil?
+    args += "--filter \"#{gcovr_opts[:report_include]}\" " unless gcovr_opts[:report_include].nil?
+    args += "--exclude \"#{gcovr_opts[:report_exclude] || GCOV_FILTER_EXCLUDE}\" "
+    args += "--gcov-filter \"#{gcovr_opts[:gcov_filter]}\" " unless gcovr_opts[:gcov_filter].nil?
+    args += "--gcov-exclude \"#{gcovr_opts[:gcov_exclude]}\" " unless gcovr_opts[:gcov_exclude].nil?
+    args += "--exclude-directories \"#{gcovr_opts[:exclude_directories]}\" " unless gcovr_opts[:exclude_directories].nil?
+    args += "--branches " if gcovr_opts[:branches].nil? || gcovr_opts[:branches] # Defaults to enabled.
+    args += "--sort-uncovered " if gcovr_opts[:sort_uncovered]
+    args += "--sort-percentage " if gcovr_opts[:sort_percentage].nil? || gcovr_opts[:sort_percentage] # Defaults to enabled.
+    args += "--print-summary " if gcovr_opts[:print_summary]
+    args += "--gcov-executable \"#{gcovr_opts[:gcov_executable]}\" " unless gcovr_opts[:gcov_executable].nil?
+    args += "--exclude-unreachable-branches " if gcovr_opts[:exclude_unreachable_branches]
+    args += "--exclude-throw-branches " if gcovr_opts[:exclude_throw_branches]
+    args += "--use-gcov-files " if gcovr_opts[:use_gcov_files]
+    args += "--gcov-ignore-parse-errors " if gcovr_opts[:gcov_ignore_parse_errors]
+    args += "--keep " if gcovr_opts[:keep]
+    args += "--delete " if gcovr_opts[:delete]
+    args += "-j #{gcovr_opts[:num_parallel_threads]} " if !(gcovr_opts[:num_parallel_threads].nil?) && (gcovr_opts[:num_parallel_threads].is_a? Integer)
+
+    [:fail_under_line, :fail_under_branch, :source_encoding, :object_directory].each do |opt|
+      unless gcovr_opts[opt].nil?
+
+        value = gcovr_opts[opt]
+        if (opt == :fail_under_line) || (opt == :fail_under_branch)
+          if not value.is_a? Integer
+            puts "Option value #{opt} has to be an integer"
+            value = nil
+          elsif (value < 0) || (value > 100)
+            puts "Option value #{opt} has to be a percentage from 0 to 100"
+            value = nil
+          end
+        end
+        args += "--#{opt.to_s.gsub('_','-')} #{value} " unless value.nil?
+      end
+    end
+
+    return args
+  end
+
+
+  # Build the gcovr Cobertura XML report generation arguments.
+  def args_builder_cobertura(opts, use_output_option=false)
+    gcovr_opts = get_opts(opts)
+    args = ""
+
+    # Determine if the Cobertura XML report is enabled. Defaults to disabled.
+    if is_report_enabled(opts, ReportTypes::COBERTURA)
+      # Determine the Cobertura XML report file name.
+      artifacts_file_cobertura = GCOV_ARTIFACTS_FILE_COBERTURA
+      if !(gcovr_opts[:cobertura_artifact_filename].nil?)
+        artifacts_file_cobertura = File.join(GCOV_ARTIFACTS_PATH, gcovr_opts[:cobertura_artifact_filename])
+      elsif !(gcovr_opts[:xml_artifact_filename].nil?)
+        artifacts_file_cobertura = File.join(GCOV_ARTIFACTS_PATH, gcovr_opts[:xml_artifact_filename])
+      end
+
+      args += "--xml-pretty " if gcovr_opts[:xml_pretty] || gcovr_opts[:cobertura_pretty]
+      args += "--xml #{use_output_option ? "--output " : ""} \"#{artifacts_file_cobertura}\" "
+    end
+
+    return args
+  end
+
+
+  # Build the gcovr SonarQube report generation arguments.
+  def args_builder_sonarqube(opts, use_output_option=false)
+    gcovr_opts = get_opts(opts)
+    args = ""
+
+    # Determine if the gcovr SonarQube XML report is enabled. Defaults to disabled.
+    if is_report_enabled(opts, ReportTypes::SONARQUBE)
+      # Determine the SonarQube XML report file name.
+      artifacts_file_sonarqube = GCOV_ARTIFACTS_FILE_SONARQUBE
+      if !(gcovr_opts[:sonarqube_artifact_filename].nil?)
+        artifacts_file_sonarqube = File.join(GCOV_ARTIFACTS_PATH, gcovr_opts[:sonarqube_artifact_filename])
+      end
+
+      args += "--sonarqube #{use_output_option ? "--output " : ""} \"#{artifacts_file_sonarqube}\" "
+    end
+
+    return args
+  end
+
+
+  # Build the gcovr JSON report generation arguments.
+  def args_builder_json(opts, use_output_option=false)
+    gcovr_opts = get_opts(opts)
+    args = ""
+
+    # Determine if the gcovr JSON report is enabled. Defaults to disabled.
+    if is_report_enabled(opts, ReportTypes::JSON)
+      # Determine the JSON report file name.
+      artifacts_file_json = GCOV_ARTIFACTS_FILE_JSON
+      if !(gcovr_opts[:json_artifact_filename].nil?)
+        artifacts_file_json = File.join(GCOV_ARTIFACTS_PATH, gcovr_opts[:json_artifact_filename])
+      end
+
+      args += "--json-pretty " if gcovr_opts[:json_pretty]
+      # Note: In gcovr 4.2, the JSON report is output only when the --output option is specified.
+      # Hopefully we can remove --output after a future gcovr release.
+      args += "--json #{use_output_option ? "--output " : ""} \"#{artifacts_file_json}\" "
+    end
+
+    return args
+  end
+
+
+  # Build the gcovr HTML report generation arguments.
+  def args_builder_html(opts, use_output_option=false)
+    gcovr_opts = get_opts(opts)
+    args = ""
+
+    # Determine if the gcovr HTML report is enabled. Defaults to enabled.
+    html_enabled = (opts[:gcov_html_report].nil? && opts[:gcov_reports].empty?) ||
+                   is_report_enabled(opts, ReportTypes::HTML_BASIC) ||
+                   is_report_enabled(opts, ReportTypes::HTML_DETAILED)
+
+    if html_enabled
+      # Determine the HTML report file name.
+      artifacts_file_html = GCOV_ARTIFACTS_FILE_HTML
+      if !(gcovr_opts[:html_artifact_filename].nil?)
+        artifacts_file_html = File.join(GCOV_ARTIFACTS_PATH, gcovr_opts[:html_artifact_filename])
+      end
+
+      is_html_report_type_detailed = (opts[:gcov_html_report_type].is_a? String) && (opts[:gcov_html_report_type].casecmp("detailed") == 0)
+
+      args += "--html-details " if is_html_report_type_detailed || is_report_enabled(opts, ReportTypes::HTML_DETAILED)
+      args += "--html-title \"#{gcovr_opts[:html_title]}\" " unless gcovr_opts[:html_title].nil?
+      args += "--html-absolute-paths " if !(gcovr_opts[:html_absolute_paths].nil?) && gcovr_opts[:html_absolute_paths]
+      args += "--html-encoding \"#{gcovr_opts[:html_encoding]}\" " unless gcovr_opts[:html_encoding].nil?
+
+      [:html_medium_threshold, :html_high_threshold].each do |opt|
+        args += "--#{opt.to_s.gsub('_','-')} #{gcovr_opts[opt]} " unless gcovr_opts[opt].nil?
+      end
+
+      # The following option must be appended last for gcovr version <= 4.2 to properly work.
+      args += "--html #{use_output_option ? "--output " : ""} \"#{artifacts_file_html}\" "
+    end
+
+    return args
+  end
+
+
+  # Generate a gcovr text report.
+  def make_text_report(opts, args_common)
+    gcovr_opts = get_opts(opts)
+    args_text = ""
+    message_text = "Creating a gcov text report"
+
+    if !(gcovr_opts[:text_artifact_filename].nil?)
+      artifacts_file_txt = File.join(GCOV_ARTIFACTS_PATH, gcovr_opts[:text_artifact_filename])
+      args_text += "--output \"#{artifacts_file_txt}\" "
+      message_text += " in '#{GCOV_ARTIFACTS_PATH}'... "
+    else
+      message_text += "... "
+    end
+
+    print message_text
+    STDOUT.flush
+
+    # Generate the text report.
+    run(args_common + args_text)
+  end
+
+
+  # Get the gcovr options from the project options.
+  def get_opts(opts)
+    return opts[GCOVR_SETTING_PREFIX.to_sym] || {}
+  end
+
+
+  # Run gcovr with the given arguments.
+  def run(args)
+    begin
+      command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_GCOVR_POST_REPORT, [], args)
+      shell_result = @ceedling[:tool_executor].exec(command[:line], command[:options])
+      @reportinator_helper.print_shell_result(shell_result)
+    rescue
+      # handle any unforeseen issues with called tool
+      exitcode = $?.exitstatus
+      show_gcovr_message(exitcode)
+      exit(exitcode)
+    end
+  end
+
+
+  # Get the gcovr version number as components.
+  # Returns [major, minor].
+  def get_gcovr_version()
+    version_number_major = 0
+    version_number_minor = 0
+
+    command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_GCOVR_POST_REPORT, [], "--version")
+    shell_result = @ceedling[:tool_executor].exec(command[:line], command[:options])
+    version_number_match_data = shell_result[:output].match(/gcovr ([0-9]+)\.([0-9]+)/)
+
+    if !(version_number_match_data.nil?) && !(version_number_match_data[1].nil?) && !(version_number_match_data[2].nil?)
+        version_number_major = version_number_match_data[1].to_i
+        version_number_minor = version_number_match_data[2].to_i
+    end
+
+    return version_number_major, version_number_minor
+  end
+
+
+  # Show a more human-friendly message on gcovr return code
+  def show_gcovr_message(exitcode)
+    if ((exitcode & 2) == 2)
+      puts "The line coverage is less than the minimum"
+    end
+    if ((exitcode & 4) == 4)
+      puts "The branch coverage is less than the minimum"
+    end
+  end
+
+
+  # Returns true if the given report type is enabled, otherwise returns false.
+  def is_report_enabled(opts, report_type)
+    return !(opts.nil?) && !(opts[:gcov_reports].nil?) && (opts[:gcov_reports].map(&:upcase).include? report_type.upcase)
+  end
+
+end
diff --git a/test/vendor/ceedling/plugins/gcov/lib/reportgenerator_reportinator.rb b/test/vendor/ceedling/plugins/gcov/lib/reportgenerator_reportinator.rb
new file mode 100644
index 000000000..d4a885c97
--- /dev/null
+++ b/test/vendor/ceedling/plugins/gcov/lib/reportgenerator_reportinator.rb
@@ -0,0 +1,195 @@
+require 'benchmark'
+require 'reportinator_helper'
+
+class ReportGeneratorReportinator
+
+  def initialize(system_objects)
+    @ceedling = system_objects
+    @reportinator_helper = ReportinatorHelper.new
+  end
+
+
+  # Generate the ReportGenerator report(s) specified in the options.
+  def make_reports(opts)
+    shell_result = nil
+    total_time = Benchmark.realtime do
+      rg_opts = get_opts(opts)
+
+      print "Creating gcov results report(s) with ReportGenerator in '#{GCOV_REPORT_GENERATOR_PATH}'... "
+      STDOUT.flush
+
+      # Cleanup any existing .gcov files to avoid reporting old coverage results.
+      for gcov_file in Dir.glob("*.gcov")
+        File.delete(gcov_file)
+      end
+
+      # Use a custom gcov executable, if specified.
+      GCOV_TOOL_CONFIG[:executable] = rg_opts[:gcov_executable] unless rg_opts[:gcov_executable].nil?
+
+      # Avoid running gcov on the mock, test, unity, and cexception gcov notes files to save time.
+      gcno_exclude_str = "#{opts[:cmock_mock_prefix]}.*"
+      gcno_exclude_str += "|#{opts[:project_test_file_prefix]}.*"
+      gcno_exclude_str += "|#{VENDORS_FILES.join('|')}"
+
+      # Avoid running gcov on custom specified .gcno files.
+      if !(rg_opts.nil?) && !(rg_opts[:gcov_exclude].nil?) && !(rg_opts[:gcov_exclude].empty?)
+        for gcno_exclude_expression in rg_opts[:gcov_exclude]
+          if !(gcno_exclude_expression.nil?) && !(gcno_exclude_expression.empty?)
+            # We want to filter .gcno files, not .gcov files.
+            # We will generate .gcov files from .gcno files.
+            gcno_exclude_expression = gcno_exclude_expression.chomp("\\.gcov")
+            gcno_exclude_expression = gcno_exclude_expression.chomp(".gcov")
+            # The .gcno extension will be added later as we create the regex.
+            gcno_exclude_expression = gcno_exclude_expression.chomp("\\.gcno")
+            gcno_exclude_expression = gcno_exclude_expression.chomp(".gcno")
+            # Append the custom expression.
+            gcno_exclude_str += "|#{gcno_exclude_expression}"
+          end
+        end
+      end
+
+      gcno_exclude_regex = /(\/|\\)(#{gcno_exclude_str})\.gcno/
+
+      # Generate .gcov files by running gcov on gcov notes files (*.gcno).
+      for gcno_filepath in Dir.glob(File.join(GCOV_BUILD_PATH, "**", "*.gcno"))
+        match_data = gcno_filepath.match(gcno_exclude_regex)
+        if match_data.nil? || (match_data[1].nil? && match_data[1].nil?)
+          # Ensure there is a matching gcov data file.
+          if File.file?(gcno_filepath.gsub(".gcno", ".gcda"))
+            run_gcov("\"#{gcno_filepath}\"")
+          end
+        end
+      end
+
+      if Dir.glob("*.gcov").length > 0
+        # Build the command line arguments.
+        args = args_builder(opts)
+
+        # Generate the report(s).
+        shell_result = run(args)
+      else
+        puts "\nWarning: No matching .gcno coverage files found."
+      end
+
+      # Cleanup .gcov files.
+      for gcov_file in Dir.glob("*.gcov")
+        File.delete(gcov_file)
+      end
+    end
+
+    if shell_result
+      shell_result[:time] = total_time
+      @reportinator_helper.print_shell_result(shell_result)
+    end
+  end
+
+
+  private
+
+  # A dictionary of report types defined in this plugin to ReportGenerator report types.
+  REPORT_TYPE_TO_REPORT_GENERATOR_REPORT_NAME = {
+    ReportTypes::HTML_BASIC.upcase => "HtmlSummary",
+    ReportTypes::HTML_DETAILED.upcase => "Html",
+    ReportTypes::HTML_CHART.upcase => "HtmlChart",
+    ReportTypes::HTML_INLINE.upcase => "HtmlInline",
+    ReportTypes::HTML_INLINE_AZURE.upcase => "HtmlInline_AzurePipelines",
+    ReportTypes::HTML_INLINE_AZURE_DARK.upcase => "HtmlInline_AzurePipelines_Dark",
+    ReportTypes::MHTML.upcase => "MHtml",
+    ReportTypes::TEXT.upcase => "TextSummary",
+    ReportTypes::COBERTURA.upcase => "Cobertura",
+    ReportTypes::SONARQUBE.upcase => "SonarQube",
+    ReportTypes::BADGES.upcase => "Badges",
+    ReportTypes::CSV_SUMMARY.upcase => "CsvSummary",
+    ReportTypes::LATEX.upcase => "Latex",
+    ReportTypes::LATEX_SUMMARY.upcase => "LatexSummary",
+    ReportTypes::PNG_CHART.upcase => "PngChart",
+    ReportTypes::TEAM_CITY_SUMMARY.upcase => "TeamCitySummary",
+    ReportTypes::LCOV.upcase => "lcov",
+    ReportTypes::XML.upcase => "Xml",
+    ReportTypes::XML_SUMMARY.upcase => "XmlSummary",
+  }
+
+  REPORT_GENERATOR_SETTING_PREFIX = "gcov_report_generator"
+
+  # Deep clone the gcov tool config, so we can modify it locally if specified via options.
+  GCOV_TOOL_CONFIG = Marshal.load(Marshal.dump(TOOLS_GCOV_GCOV_POST_REPORT))
+
+  # Build the ReportGenerator arguments.
+  def args_builder(opts)
+    rg_opts = get_opts(opts)
+    report_type_count = 0
+
+    args = ""
+    args += "\"-reports:*.gcov\" "
+    args += "\"-targetdir:\"#{GCOV_REPORT_GENERATOR_PATH}\"\" "
+
+    # Build the report types argument.
+    if !(opts.nil?) && !(opts[:gcov_reports].nil?) && !(opts[:gcov_reports].empty?)
+      args += "\"-reporttypes:"
+
+      for report_type in opts[:gcov_reports]
+        rg_report_type = REPORT_TYPE_TO_REPORT_GENERATOR_REPORT_NAME[report_type.upcase]
+        if !(rg_report_type.nil?)
+          args += rg_report_type + ";"
+          report_type_count = report_type_count + 1
+        end
+      end
+
+      # Removing trailing ';' after the last report type.
+      args = args.chomp(";")
+
+      # Append a space seperator after the report type.
+      args += "\" "
+    end
+
+    # Build the source directories argument.
+    args += "\"-sourcedirs:.;"
+    if !(opts[:collection_paths_source].nil?)
+      args += opts[:collection_paths_source].join(';')
+    end
+    args = args.chomp(";")
+    args += "\" "
+
+    args += "\"-historydir:#{rg_opts[:history_directory]}\" " unless rg_opts[:history_directory].nil?
+    args += "\"-plugins:#{rg_opts[:plugins]}\" " unless rg_opts[:plugins].nil?
+    args += "\"-assemblyfilters:#{rg_opts[:assembly_filters]}\" " unless rg_opts[:assembly_filters].nil?
+    args += "\"-classfilters:#{rg_opts[:class_filters]}\" " unless rg_opts[:class_filters].nil?
+    file_filters = rg_opts[:file_filters] || @ceedling[:tool_executor_helper].osify_path_separators(GCOV_REPORT_GENERATOR_FILE_FILTERS)
+    args += "\"-filefilters:#{file_filters}\" "
+    args += "\"-verbosity:#{rg_opts[:verbosity] || "Warning"}\" "
+    args += "\"-tag:#{rg_opts[:tag]}\" " unless rg_opts[:tag].nil?
+    args += "\"settings:createSubdirectoryForAllReportTypes=true\" " unless report_type_count <= 1
+    args += "\"settings:numberOfReportsParsedInParallel=#{rg_opts[:num_parallel_threads]}\" " unless rg_opts[:num_parallel_threads].nil?
+    args += "\"settings:numberOfReportsMergedInParallel=#{rg_opts[:num_parallel_threads]}\" " unless rg_opts[:num_parallel_threads].nil?
+
+    # Append custom arguments.
+    if !(rg_opts[:custom_args].nil?) && !(rg_opts[:custom_args].empty?)
+      for custom_arg in rg_opts[:custom_args]
+        args += "\"#{custom_arg}\" " unless custom_arg.nil? || custom_arg.empty?
+      end
+    end
+
+    return args
+  end
+
+
+  # Get the ReportGenerator options from the project options.
+  def get_opts(opts)
+    return opts[REPORT_GENERATOR_SETTING_PREFIX.to_sym] || {}
+  end
+
+
+  # Run ReportGenerator with the given arguments.
+  def run(args)
+    command = @ceedling[:tool_executor].build_command_line(TOOLS_GCOV_REPORTGENERATOR_POST_REPORT, [], args)
+    return @ceedling[:tool_executor].exec(command[:line], command[:options])
+  end
+
+
+  # Run gcov with the given arguments.
+  def run_gcov(args)
+    command = @ceedling[:tool_executor].build_command_line(GCOV_TOOL_CONFIG, [], args)
+    return @ceedling[:tool_executor].exec(command[:line], command[:options])
+  end
+
+end
diff --git a/test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb b/test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb
new file mode 100644
index 000000000..92617fba5
--- /dev/null
+++ b/test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb
@@ -0,0 +1,15 @@
+
+class ReportinatorHelper
+
+    # Output the shell result to the console.
+    def print_shell_result(shell_result)
+      if !(shell_result.nil?)
+        puts "Done in %.3f seconds." % shell_result[:time]
+  
+        if !(shell_result[:output].nil?) && (shell_result[:output].length > 0)
+          puts shell_result[:output]
+        end
+      end
+    end
+
+end
diff --git a/test/vendor/ceedling/plugins/json_tests_report/README.md b/test/vendor/ceedling/plugins/json_tests_report/README.md
new file mode 100644
index 000000000..8e5a1e571
--- /dev/null
+++ b/test/vendor/ceedling/plugins/json_tests_report/README.md
@@ -0,0 +1,36 @@
+json_tests_report
+=================
+
+## Overview
+
+The json_tests_report plugin creates a JSON file of test results, which is 
+handy for Continuous Integration build servers or as input into other 
+reporting tools. The JSON file is output to the appropriate
+`<build_root>/artifacts/` directory (e.g. `artifacts/test/` for test tasks,
+`artifacts/gcov/` for gcov, or `artifacts/bullseye/` for bullseye runs).
+
+## Setup
+
+Enable the plugin in your project.yml by adding `json_tests_report` to the list
+of enabled plugins.
+
+``` YAML
+:plugins:
+  :enabled:
+    - json_tests_report
+```
+
+## Configuration
+
+Optionally configure the output / artifact filename in your project.yml with
+the `artifact_filename` configuration option. The default filename is
+`report.json`.
+
+You can also configure the path that this artifact is stored. This can be done
+by setting `path`. The default is that it will be placed in a subfolder under
+the `build` directory.
+
+``` YAML
+:json_tests_report:
+  :artifact_filename: report_spectuluarly.json
+```
diff --git a/test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb b/test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb
new file mode 100644
index 000000000..e7023db7b
--- /dev/null
+++ b/test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb
@@ -0,0 +1,83 @@
+require 'ceedling/plugin'
+require 'ceedling/constants'
+require 'json'
+
+class JsonTestsReport < Plugin
+  def setup
+    @results_list = {}
+    @test_counter = 0
+  end
+
+  def post_test_fixture_execute(arg_hash)
+    context = arg_hash[:context]
+
+    @results_list[context] = [] if @results_list[context].nil?
+
+    @results_list[context] << arg_hash[:result_file]
+  end
+
+  def post_build
+    @results_list.each_key do |context|
+      results = @ceedling[:plugin_reportinator].assemble_test_results(@results_list[context])
+
+      artifact_filename = @ceedling[:configurator].project_config_hash[:json_tests_report_artifact_filename] || 'report.json'
+      artifact_fullpath = @ceedling[:configurator].project_config_hash[:json_tests_report_path] || File.join(PROJECT_BUILD_ARTIFACTS_ROOT, context.to_s)
+      file_path = File.join(artifact_fullpath, artifact_filename)
+
+      @ceedling[:file_wrapper].open(file_path, 'w') do |f|
+        @test_counter = 1
+
+        json = {
+          "FailedTests" => write_failures(results[:failures]),
+          "PassedTests" => write_tests(results[:successes]),
+          "IgnoredTests" => write_tests(results[:ignores]),
+          "Summary" => write_statistics(results[:counts])
+        }
+        
+        f << JSON.pretty_generate(json)
+      end
+    end
+  end
+
+  private
+
+  def write_failures(results)
+    retval = []
+    results.each do |result|
+      result[:collection].each do |item|
+        @test_counter += 1
+        retval << {
+          "file" => File.join(result[:source][:path], result[:source][:file]),
+          "test" => item[:test],
+          "line" => item[:line],
+          "message" => item[:message]
+        }
+      end
+    end
+    return retval.uniq
+  end
+
+  def write_tests(results)
+    retval = []
+    results.each do |result|
+      result[:collection].each do |item|
+        @test_counter += 1
+        retval << { 
+          "file" => File.join(result[:source][:path], result[:source][:file]),
+          "test" => item[:test]
+        }
+      end
+    end
+    return retval
+  end
+
+  def write_statistics(counts)
+    return {
+      "total_tests" => counts[:total],
+      "passed" => (counts[:total] - counts[:ignored] - counts[:failed]),
+      "ignored" => counts[:ignored],
+      "failures" => counts[:failed]
+    }
+  end
+
+end
diff --git a/test/vendor/ceedling/plugins/module_generator/README.md b/test/vendor/ceedling/plugins/module_generator/README.md
new file mode 100644
index 000000000..a3c2c7ad9
--- /dev/null
+++ b/test/vendor/ceedling/plugins/module_generator/README.md
@@ -0,0 +1,119 @@
+ceedling-module-generator
+=========================
+
+## Overview
+
+The module_generator plugin adds a pair of new commands to Ceedling, allowing
+you to make or remove modules according to predefined templates. WIth a single call,
+Ceedling can generate a source, header, and test file for a new module. If given a
+pattern, it can even create a series of submodules to support specific design patterns.
+Finally, it can just as easily remove related modules, avoiding the need to delete
+each individually.
+
+Let's say, for example, that you want to create a single module named `MadScience`.
+
+```
+ceedling module:create[MadScience]
+```
+
+It says we're speaking to the module plugin, and we want to create a new module. The
+name of that module is between the brackets. It will keep this case, unless you have
+specified a different default (see configuration). It will create three files:
+`MadScience.c`, `MadScience.h`, and `TestMadScience.c`. *NOTE* that it is important that
+there are no spaces between the brackets. We know, it's annoying... but it's the rules.
+
+You can also create an entire pattern of files. To do that, just add a second argument
+to the pattern ID. Something like this:
+
+```
+ceedling module:create[SecretLair,mch]
+```
+
+In this example, we'd create 9 files total: 3 headers, 3 source files, and 3 test files. These
+files would be named `SecretLairModel`, `SecretLairConductor`, and `SecretLairHardware`. Isn't
+that nice?
+
+Similarly, you can create stubs for all functions in a header file just by making a single call
+to your handy `stub` feature, like this:
+
+```
+ceedling module:stub[SecretLair]
+```
+
+This call will look in SecretLair.h and will generate a file SecretLair.c that contains a stub
+for each function declared in the header! Even better, if SecretLair.c already exists, it will
+add only new functions, leaving your existing calls alone so that it doesn't cause any problems.
+
+## Configuration
+
+Enable the plugin in your project.yml by adding `module_generator`
+to the list of enabled plugins.
+
+Then, like much of Ceedling, you can just run as-is with the defaults, or you can override those
+defaults for your own needs. For example, new source and header files will be automatically
+placed in the `src/` folder while tests will go in the `test/` folder. That's great if your project
+follows the default ceedling structure... but what if you have a different structure?
+
+```
+:module_generator:
+  :project_root: ./
+  :source_root: source/
+  :inc_root: includes/
+  :test_root: tests/
+```
+
+Now I've redirected the location where modules are going to be generated.
+
+### Includes
+
+You can make it so that all of your files are generated with a standard include list. This is done
+by adding to the `:includes` array. For example:
+
+```
+:module_generator:
+  :includes:
+    :tst:
+      - defs.h
+      - board.h
+    :src:
+      - board.h
+```
+
+### Boilerplates
+
+You can specify the actual boilerplate used for each of your files. This is the handy place to
+put that corporate copyright notice (or maybe a copyleft notice, if that's your perference?)
+
+```
+:module_generator:
+  :boilerplates: |
+    /***************************
+    * This file is Awesome.    *
+    * That is All.             *
+    ***************************/
+```
+
+### Test Defines
+
+You can specify the "#ifdef TEST" at the top of the test files with a custom define.
+This example will put a "#ifdef CEEDLING_TEST" at the top of the test files.  
+
+```
+:module_generator:
+  :test_define: CEEDLING_TEST
+```
+
+### Naming Convention
+
+Finally, you can force a particular naming convention. Even if someone calls the generator
+with something like `MyNewModule`, if they have the naming convention set to `:caps`, it will
+generate files like `MY_NEW_MODULE.c`. This keeps everyone on your team behaving the same way.
+
+Your options are as follows:
+
+  - `:bumpy` - BumpyFilesLooksLikeSo
+  - `:camel` - camelFilesAreSimilarButStartLow
+  - `:snake` - snake_case_is_all_lower_and_uses_underscores
+  - `:caps`  - CAPS_FEELS_LIKE_YOU_ARE_SCREAMING
+
+
diff --git a/test/vendor/ceedling/plugins/raw_output_report/README.md b/test/vendor/ceedling/plugins/raw_output_report/README.md
new file mode 100644
index 000000000..330e87d39
--- /dev/null
+++ b/test/vendor/ceedling/plugins/raw_output_report/README.md
@@ -0,0 +1,19 @@
+ceedling-raw-output-report
+==========================
+
+## Overview
+
+The raw-output-report allows you to capture all the output from the called
+tools in a single document, so you can trace back through it later. This is
+useful for debugging... but can eat through memory quickly if left running.
+
+## Setup
+
+Enable the plugin in your project.yml by adding `raw_output_report`
+to the list of enabled plugins.
+
+``` YAML
+:plugins:
+  :enabled:
+    - raw_output_report
+```
diff --git a/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md b/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md
new file mode 100644
index 000000000..9ab60847e
--- /dev/null
+++ b/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md
@@ -0,0 +1,19 @@
+ceedling-stdout-gtestlike-tests-report
+======================
+
+## Overview
+
+The stdout_gtestlike_tests_report replaces the normal ceedling "pretty" output with 
+a variant that resembles the output of gtest. This is most helpful when trying to 
+integrate into an IDE or CI that is meant to work with google test.
+
+## Setup
+
+Enable the plugin in your project.yml by adding `stdout_gtestlike_tests_report`
+to the list of enabled plugins.
+
+``` YAML
+:plugins:
+  :enabled:
+    - stdout_gtestlike_tests_report
+```
diff --git a/test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md b/test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md
new file mode 100644
index 000000000..ed6c65582
--- /dev/null
+++ b/test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md
@@ -0,0 +1,18 @@
+ceedling-stdout-ide-tests-report
+================================
+
+## Overview
+
+The stdout_ide_tests_report replaces the normal ceedling "pretty" output with 
+a simplified variant intended to be easily parseable.
+
+## Setup
+
+Enable the plugin in your project.yml by adding `stdout_ide_tests_report`
+to the list of enabled plugins.
+
+``` YAML
+:plugins:
+  :enabled:
+    - stdout_ide_tests_report
+```
diff --git a/test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md b/test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md
new file mode 100644
index 000000000..7e1be2382
--- /dev/null
+++ b/test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md
@@ -0,0 +1,20 @@
+ceedling-pretty-tests-report
+============================
+
+## Overview
+
+The stdout_pretty_tests_report is the default output of ceedling. Instead of
+showing most of the raw output of CMock, Ceedling, etc., it shows a simplified
+view. It also creates a nice summary at the end of execution which groups the 
+results into ignored and failed tests.
+
+## Setup
+
+Enable the plugin in your project.yml by adding `stdout_pretty_tests_report`
+to the list of enabled plugins.
+
+``` YAML
+:plugins:
+  :enabled:
+    - stdout_pretty_tests_report
+```
diff --git a/test/vendor/ceedling/plugins/teamcity_tests_report/README.md b/test/vendor/ceedling/plugins/teamcity_tests_report/README.md
new file mode 100644
index 000000000..9fcda7d5b
--- /dev/null
+++ b/test/vendor/ceedling/plugins/teamcity_tests_report/README.md
@@ -0,0 +1,18 @@
+ceedling-teamcity-tests-report
+==============================
+
+## Overview
+
+The teamcity_tests_report replaces the normal ceedling "pretty" output with 
+a version that has results tagged to be consumed with the teamcity CI server.
+
+## Setup
+
+Enable the plugin in your project.yml by adding `teamcity_tests_report`
+to the list of enabled plugins.
+
+``` YAML
+:plugins:
+  :enabled:
+    - teamcity_tests_report
+```
diff --git a/test/vendor/ceedling/plugins/warnings_report/README.md b/test/vendor/ceedling/plugins/warnings_report/README.md
new file mode 100644
index 000000000..fd7fae5d9
--- /dev/null
+++ b/test/vendor/ceedling/plugins/warnings_report/README.md
@@ -0,0 +1,19 @@
+warnings-report
+===============
+
+## Overview
+
+The warnings_report captures all warnings throughout the build process
+and collects them into a single report at the end of execution. It places all
+of this into a warnings file in the output artifact directory.
+
+## Setup
+
+Enable the plugin in your project.yml by adding `warnings_report`
+to the list of enabled plugins.
+
+``` YAML
+:plugins:
+  :enabled:
+    - warnings_report
+```
diff --git a/test/vendor/ceedling/vendor/c_exception/lib/meson.build b/test/vendor/ceedling/vendor/c_exception/lib/meson.build
new file mode 100644
index 000000000..2770122af
--- /dev/null
+++ b/test/vendor/ceedling/vendor/c_exception/lib/meson.build
@@ -0,0 +1,11 @@
+#
+# build script written by : Michael Brockus.
+# github repo author: Mark VanderVoord.
+#
+# license: MIT
+#
+cexception_dir = include_directories('.')
+
+cexception_lib = static_library(meson.project_name(), 
+    files('CException.c'),
+    include_directories : cexception_dir)
diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_stateless.rb b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_stateless.rb
new file mode 100644
index 000000000..9196edea4
--- /dev/null
+++ b/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_stateless.rb
@@ -0,0 +1,85 @@
+# ==========================================
+#   CMock Project - Automatic Mock Generation for C
+#   Copyright (c) 2007 Mike Karlesky, Mark VanderVoord, Greg Williams
+#   [Released under MIT License. Please refer to license.txt for details]
+# ==========================================
+
+class CMockGeneratorPluginIgnoreStateless
+  attr_reader :priority
+  attr_reader :config, :utils
+
+  def initialize(config, utils)
+    @config = config
+    @utils = utils
+    @priority = 2
+  end
+
+  def instance_structure(function)
+    if function[:return][:void?]
+      "  char #{function[:name]}_IgnoreBool;\n"
+    else
+      "  char #{function[:name]}_IgnoreBool;\n  #{function[:return][:type]} #{function[:name]}_FinalReturn;\n"
+    end
+  end
+
+  def mock_function_declarations(function)
+    lines = if function[:return][:void?]
+              "#define #{function[:name]}_Ignore() #{function[:name]}_CMockIgnore()\n" \
+              "void #{function[:name]}_CMockIgnore(void);\n"
+            else
+              "#define #{function[:name]}_IgnoreAndReturn(cmock_retval) #{function[:name]}_CMockIgnoreAndReturn(cmock_retval)\n" \
+              "void #{function[:name]}_CMockIgnoreAndReturn(#{function[:return][:str]});\n"
+            end
+
+    # Add stop ignore function. it does not matter if there are any args
+    lines << "#define #{function[:name]}_StopIgnore() #{function[:name]}_CMockStopIgnore()\n" \
+                "void #{function[:name]}_CMockStopIgnore(void);\n"
+    lines
+  end
+
+  def mock_implementation_precheck(function)
+    lines = "  if (Mock.#{function[:name]}_IgnoreBool)\n  {\n"
+    lines << "    UNITY_CLR_DETAILS();\n"
+    if function[:return][:void?]
+      lines << "    return;\n  }\n"
+    else
+      retval = function[:return].merge(:name => 'cmock_call_instance->ReturnVal')
+      lines << "    if (cmock_call_instance == NULL)\n      return Mock.#{function[:name]}_FinalReturn;\n"
+      lines << '  ' + @utils.code_assign_argument_quickly("Mock.#{function[:name]}_FinalReturn", retval) unless retval[:void?]
+      lines << "    return cmock_call_instance->ReturnVal;\n  }\n"
+    end
+    lines
+  end
+
+  # this function is adjusted
+  def mock_interfaces(function)
+    lines = ''
+    lines << if function[:return][:void?]
+               "void #{function[:name]}_CMockIgnore(void)\n{\n"
+             else
+               "void #{function[:name]}_CMockIgnoreAndReturn(#{function[:return][:str]})\n{\n"
+             end
+    unless function[:return][:void?]
+      lines << "  Mock.#{function[:name]}_CallInstance = CMOCK_GUTS_NONE;\n"
+      lines << "  Mock.#{function[:name]}_FinalReturn = cmock_to_return;\n"
+    end
+    lines << "  Mock.#{function[:name]}_IgnoreBool = (char)1;\n"
+    lines << "}\n\n"
+
+    # Add stop ignore function. it does not matter if there are any args
+    lines << "void #{function[:name]}_CMockStopIgnore(void)\n{\n"
+    lines << "  Mock.#{function[:name]}_IgnoreBool = (char)0;\n"
+    lines << "}\n\n"
+
+    lines
+  end
+
+  def mock_ignore(function)
+    "  Mock.#{function[:name]}_IgnoreBool = (char)1;\n"
+  end
+
+  def mock_verify(function)
+    func_name = function[:name]
+    "  if (Mock.#{func_name}_IgnoreBool)\n    call_instance = CMOCK_GUTS_NONE;\n"
+  end
+end

From be4f4e4f79c2342bda3b42653332129332a58d0b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 09:59:02 +0700
Subject: [PATCH 1273/2085] move ceedling tests to test/unit-test

---
 test/{ => unit-test}/ceedling                                   | 0
 test/{ => unit-test}/project.yml                                | 2 +-
 test/{ => unit-test}/test/device/msc/test_msc_device.c          | 0
 test/{ => unit-test}/test/device/usbd/test_usbd.c               | 0
 test/{ => unit-test}/test/support/tusb_config.h                 | 0
 test/{ => unit-test}/test/test_fifo.c                           | 0
 test/{ => unit-test}/vendor/ceedling/bin/ceedling               | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling.rb            | 0
 .../vendor/ceedling/lib/ceedling/build_invoker_utils.rb         | 0
 .../{ => unit-test}/vendor/ceedling/lib/ceedling/cacheinator.rb | 0
 .../vendor/ceedling/lib/ceedling/cacheinator_helper.rb          | 0
 .../vendor/ceedling/lib/ceedling/cmock_builder.rb               | 0
 .../vendor/ceedling/lib/ceedling/configurator.rb                | 0
 .../vendor/ceedling/lib/ceedling/configurator_builder.rb        | 0
 .../vendor/ceedling/lib/ceedling/configurator_plugins.rb        | 0
 .../vendor/ceedling/lib/ceedling/configurator_setup.rb          | 0
 .../vendor/ceedling/lib/ceedling/configurator_validator.rb      | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/constants.rb  | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/defaults.rb   | 0
 .../vendor/ceedling/lib/ceedling/dependinator.rb                | 0
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 .../{ => unit-test}/vendor/ceedling/lib/ceedling/file_finder.rb | 0
 .../vendor/ceedling/lib/ceedling/file_finder_helper.rb          | 0
 .../vendor/ceedling/lib/ceedling/file_path_utils.rb             | 0
 .../vendor/ceedling/lib/ceedling/file_system_utils.rb           | 0
 .../vendor/ceedling/lib/ceedling/file_system_wrapper.rb         | 0
 .../vendor/ceedling/lib/ceedling/file_wrapper.rb                | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/flaginator.rb | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/generator.rb  | 0
 .../vendor/ceedling/lib/ceedling/generator_helper.rb            | 0
 .../vendor/ceedling/lib/ceedling/generator_test_results.rb      | 0
 .../lib/ceedling/generator_test_results_sanity_checker.rb       | 0
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 test/{ => unit-test}/vendor/ceedling/lib/ceedling/loginator.rb  | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/makefile.rb   | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/objects.yml   | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/par_map.rb    | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/plugin.rb     | 0
 .../vendor/ceedling/lib/ceedling/plugin_builder.rb              | 0
 .../vendor/ceedling/lib/ceedling/plugin_manager.rb              | 0
 .../vendor/ceedling/lib/ceedling/plugin_manager_helper.rb       | 0
 .../vendor/ceedling/lib/ceedling/plugin_reportinator.rb         | 0
 .../vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb  | 0
 .../vendor/ceedling/lib/ceedling/preprocessinator.rb            | 0
 .../vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb  | 0
 .../ceedling/lib/ceedling/preprocessinator_file_handler.rb      | 0
 .../vendor/ceedling/lib/ceedling/preprocessinator_helper.rb     | 0
 .../ceedling/lib/ceedling/preprocessinator_includes_handler.rb  | 0
 .../vendor/ceedling/lib/ceedling/project_config_manager.rb      | 0
 .../vendor/ceedling/lib/ceedling/project_file_loader.rb         | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/rake_utils.rb | 0
 .../vendor/ceedling/lib/ceedling/rake_wrapper.rb                | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/rakefile.rb   | 0
 .../vendor/ceedling/lib/ceedling/release_invoker.rb             | 0
 .../vendor/ceedling/lib/ceedling/release_invoker_helper.rb      | 0
 .../vendor/ceedling/lib/ceedling/reportinator.rb                | 0
 .../vendor/ceedling/lib/ceedling/rules_cmock.rake               | 0
 .../vendor/ceedling/lib/ceedling/rules_preprocess.rake          | 0
 .../vendor/ceedling/lib/ceedling/rules_release.rake             | 0
 .../ceedling/lib/ceedling/rules_release_deep_dependencies.rake  | 0
 .../vendor/ceedling/lib/ceedling/rules_tests.rake               | 0
 .../ceedling/lib/ceedling/rules_tests_deep_dependencies.rake    | 0
 .../{ => unit-test}/vendor/ceedling/lib/ceedling/setupinator.rb | 0
 .../vendor/ceedling/lib/ceedling/stream_wrapper.rb              | 0
 .../vendor/ceedling/lib/ceedling/streaminator.rb                | 0
 .../vendor/ceedling/lib/ceedling/streaminator_helper.rb         | 0
 .../vendor/ceedling/lib/ceedling/system_utils.rb                | 0
 .../vendor/ceedling/lib/ceedling/system_wrapper.rb              | 0
 .../vendor/ceedling/lib/ceedling/target_loader.rb               | 0
 .../vendor/ceedling/lib/ceedling/task_invoker.rb                | 0
 .../vendor/ceedling/lib/ceedling/tasks_base.rake                | 0
 .../vendor/ceedling/lib/ceedling/tasks_filesystem.rake          | 0
 .../vendor/ceedling/lib/ceedling/tasks_release.rake             | 0
 .../ceedling/lib/ceedling/tasks_release_deep_dependencies.rake  | 0
 .../vendor/ceedling/lib/ceedling/tasks_tests.rake               | 0
 .../ceedling/lib/ceedling/tasks_tests_deep_dependencies.rake    | 0
 .../vendor/ceedling/lib/ceedling/tasks_vendor.rake              | 0
 .../vendor/ceedling/lib/ceedling/test_includes_extractor.rb     | 0
 .../vendor/ceedling/lib/ceedling/test_invoker.rb                | 0
 .../vendor/ceedling/lib/ceedling/test_invoker_helper.rb         | 0
 .../vendor/ceedling/lib/ceedling/tool_executor.rb               | 0
 .../vendor/ceedling/lib/ceedling/tool_executor_helper.rb        | 0
 .../vendor/ceedling/lib/ceedling/verbosinator.rb                | 0
 test/{ => unit-test}/vendor/ceedling/lib/ceedling/version.rb    | 0
 .../vendor/ceedling/lib/ceedling/yaml_wrapper.rb                | 0
 test/{ => unit-test}/vendor/ceedling/plugins/beep/README.md     | 0
 test/{ => unit-test}/vendor/ceedling/plugins/beep/lib/beep.rb   | 0
 test/{ => unit-test}/vendor/ceedling/plugins/bullseye/README.md | 0
 .../vendor/ceedling/plugins/bullseye/assets/template.erb        | 0
 .../vendor/ceedling/plugins/bullseye/bullseye.rake              | 0
 .../vendor/ceedling/plugins/bullseye/config/defaults.yml        | 0
 .../vendor/ceedling/plugins/bullseye/lib/bullseye.rb            | 0
 .../vendor/ceedling/plugins/colour_report/README.md             | 0
 .../vendor/ceedling/plugins/colour_report/lib/colour_report.rb  | 0
 .../vendor/ceedling/plugins/command_hooks/README.md             | 0
 .../vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb  | 0
 .../vendor/ceedling/plugins/compile_commands_json/README.md     | 0
 .../plugins/compile_commands_json/lib/compile_commands_json.rb  | 0
 .../vendor/ceedling/plugins/dependencies/README.md              | 0
 .../vendor/ceedling/plugins/dependencies/config/defaults.yml    | 0
 .../vendor/ceedling/plugins/dependencies/dependencies.rake      | 0
 .../vendor/ceedling/plugins/dependencies/lib/dependencies.rb    | 0
 .../vendor/ceedling/plugins/fake_function_framework/README.md   | 0
 .../vendor/ceedling/plugins/fake_function_framework/Rakefile    | 0
 .../fake_function_framework/examples/fff_example/project.yml    | 0
 .../fake_function_framework/examples/fff_example/rakefile.rb    | 0
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 .../fake_function_framework/examples/fff_example/src/display.c  | 0
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 .../fake_function_framework/lib/fake_function_framework.rb      | 0
 .../plugins/fake_function_framework/lib/fff_mock_generator.rb   | 0
 .../spec/fff_mock_header_generator_spec.rb                      | 0
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 .../plugins/fake_function_framework/spec/header_generator.rb    | 0
 .../plugins/fake_function_framework/spec/spec_helper.rb         | 0
 .../plugins/fake_function_framework/src/fff_unity_helper.h      | 0
 test/{ => unit-test}/vendor/ceedling/plugins/gcov/README.md     | 0
 .../vendor/ceedling/plugins/gcov/assets/template.erb            | 0
 .../vendor/ceedling/plugins/gcov/config/defaults_gcov.rb        | 0
 test/{ => unit-test}/vendor/ceedling/plugins/gcov/gcov.rake     | 0
 test/{ => unit-test}/vendor/ceedling/plugins/gcov/lib/gcov.rb   | 0
 .../vendor/ceedling/plugins/gcov/lib/gcov_constants.rb          | 0
 .../vendor/ceedling/plugins/gcov/lib/gcovr_reportinator.rb      | 0
 .../ceedling/plugins/gcov/lib/reportgenerator_reportinator.rb   | 0
 .../vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb     | 0
 .../vendor/ceedling/plugins/json_tests_report/README.md         | 0
 .../ceedling/plugins/json_tests_report/lib/json_tests_report.rb | 0
 .../vendor/ceedling/plugins/junit_tests_report/README.md        | 0
 .../plugins/junit_tests_report/lib/junit_tests_report.rb        | 0
 .../vendor/ceedling/plugins/module_generator/README.md          | 0
 .../plugins/module_generator/config/module_generator.yml        | 0
 .../ceedling/plugins/module_generator/lib/module_generator.rb   | 0
 .../ceedling/plugins/module_generator/module_generator.rake     | 0
 .../vendor/ceedling/plugins/raw_output_report/README.md         | 0
 .../ceedling/plugins/raw_output_report/lib/raw_output_report.rb | 0
 .../ceedling/plugins/stdout_gtestlike_tests_report/README.md    | 0
 .../plugins/stdout_gtestlike_tests_report/assets/template.erb   | 0
 .../stdout_gtestlike_tests_report/assets/template.erb copy      | 0
 .../config/stdout_gtestlike_tests_report.yml                    | 0
 .../lib/stdout_gtestlike_tests_report.rb                        | 0
 .../vendor/ceedling/plugins/stdout_ide_tests_report/README.md   | 0
 .../stdout_ide_tests_report/config/stdout_ide_tests_report.yml  | 0
 .../stdout_ide_tests_report/lib/stdout_ide_tests_report.rb      | 0
 .../ceedling/plugins/stdout_pretty_tests_report/README.md       | 0
 .../plugins/stdout_pretty_tests_report/assets/template.erb      | 0
 .../config/stdout_pretty_tests_report.yml                       | 0
 .../lib/stdout_pretty_tests_report.rb                           | 0
 .../vendor/ceedling/plugins/subprojects/README.md               | 0
 .../vendor/ceedling/plugins/subprojects/config/defaults.yml     | 0
 .../vendor/ceedling/plugins/subprojects/lib/subprojects.rb      | 0
 .../vendor/ceedling/plugins/subprojects/subprojects.rake        | 0
 .../vendor/ceedling/plugins/teamcity_tests_report/README.md     | 0
 .../teamcity_tests_report/config/teamcity_tests_report.yml      | 0
 .../plugins/teamcity_tests_report/lib/teamcity_tests_report.rb  | 0
 .../vendor/ceedling/plugins/warnings_report/README.md           | 0
 .../ceedling/plugins/warnings_report/lib/warnings_report.rb     | 0
 .../vendor/ceedling/plugins/xml_tests_report/README.md          | 0
 .../ceedling/plugins/xml_tests_report/lib/xml_tests_report.rb   | 0
 .../vendor/ceedling/vendor/c_exception/lib/CException.c         | 0
 .../vendor/ceedling/vendor/c_exception/lib/CException.h         | 0
 .../vendor/ceedling/vendor/c_exception/lib/meson.build          | 0
 .../ceedling/vendor/cmock/config/production_environment.rb      | 0
 .../vendor/ceedling/vendor/cmock/config/test_environment.rb     | 0
 test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock.rb  | 0
 .../vendor/ceedling/vendor/cmock/lib/cmock_config.rb            | 0
 .../vendor/ceedling/vendor/cmock/lib/cmock_file_writer.rb       | 0
 .../vendor/ceedling/vendor/cmock/lib/cmock_generator.rb         | 0
 .../ceedling/vendor/cmock/lib/cmock_generator_plugin_array.rb   | 0
 .../vendor/cmock/lib/cmock_generator_plugin_callback.rb         | 0
 .../vendor/cmock/lib/cmock_generator_plugin_cexception.rb       | 0
 .../ceedling/vendor/cmock/lib/cmock_generator_plugin_expect.rb  | 0
 .../vendor/cmock/lib/cmock_generator_plugin_expect_any_args.rb  | 0
 .../ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb  | 0
 .../vendor/cmock/lib/cmock_generator_plugin_ignore_arg.rb       | 0
 .../vendor/cmock/lib/cmock_generator_plugin_ignore_stateless.rb | 0
 .../vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb  | 0
 .../vendor/ceedling/vendor/cmock/lib/cmock_generator_utils.rb   | 0
 .../vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb     | 0
 .../vendor/ceedling/vendor/cmock/lib/cmock_plugin_manager.rb    | 0
 .../ceedling/vendor/cmock/lib/cmock_unityhelper_parser.rb       | 0
 test/{ => unit-test}/vendor/ceedling/vendor/cmock/src/cmock.c   | 0
 test/{ => unit-test}/vendor/ceedling/vendor/cmock/src/cmock.h   | 0
 .../vendor/ceedling/vendor/cmock/src/cmock_internals.h          | 0
 .../vendor/ceedling/vendor/cmock/src/meson.build                | 0
 test/{ => unit-test}/vendor/ceedling/vendor/diy/lib/diy.rb      | 0
 .../vendor/ceedling/vendor/diy/lib/diy/factory.rb               | 0
 .../vendor/ceedling/vendor/unity/auto/colour_prompt.rb          | 0
 .../vendor/ceedling/vendor/unity/auto/colour_reporter.rb        | 0
 .../vendor/ceedling/vendor/unity/auto/generate_config.yml       | 0
 .../vendor/ceedling/vendor/unity/auto/generate_module.rb        | 0
 .../vendor/ceedling/vendor/unity/auto/generate_test_runner.rb   | 0
 .../vendor/ceedling/vendor/unity/auto/parse_output.rb           | 0
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 .../vendor/ceedling/vendor/unity/auto/type_sanitizer.rb         | 0
 .../vendor/ceedling/vendor/unity/auto/unity_test_summary.py     | 0
 .../vendor/ceedling/vendor/unity/auto/unity_test_summary.rb     | 0
 .../vendor/ceedling/vendor/unity/auto/unity_to_junit.py         | 0
 .../vendor/ceedling/vendor/unity/src/meson.build                | 0
 test/{ => unit-test}/vendor/ceedling/vendor/unity/src/unity.c   | 0
 test/{ => unit-test}/vendor/ceedling/vendor/unity/src/unity.h   | 0
 .../vendor/ceedling/vendor/unity/src/unity_internals.h          | 0
 213 files changed, 1 insertion(+), 1 deletion(-)
 rename test/{ => unit-test}/ceedling (100%)
 rename test/{ => unit-test}/project.yml (99%)
 rename test/{ => unit-test}/test/device/msc/test_msc_device.c (100%)
 rename test/{ => unit-test}/test/device/usbd/test_usbd.c (100%)
 rename test/{ => unit-test}/test/support/tusb_config.h (100%)
 rename test/{ => unit-test}/test/test_fifo.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/bin/ceedling (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/build_invoker_utils.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/cacheinator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/cacheinator_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/cmock_builder.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/configurator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/configurator_builder.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/configurator_plugins.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/configurator_setup.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/configurator_validator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/constants.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/defaults.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/dependinator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/erb_wrapper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/file_finder.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/file_finder_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/file_path_utils.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/file_system_utils.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/file_system_wrapper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/file_wrapper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/flaginator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/generator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/generator_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/generator_test_results.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/generator_test_runner.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/loginator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/makefile.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/objects.yml (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/par_map.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/plugin.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/plugin_builder.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/plugin_manager.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/plugin_manager_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/plugin_reportinator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/preprocessinator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/project_config_manager.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/project_file_loader.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/rake_utils.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/rake_wrapper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/rakefile.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/release_invoker.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/release_invoker_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/reportinator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/rules_cmock.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/rules_preprocess.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/rules_release.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/rules_tests.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/setupinator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/stream_wrapper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/streaminator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/streaminator_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/system_utils.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/system_wrapper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/target_loader.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/task_invoker.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/tasks_base.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/tasks_filesystem.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/tasks_release.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/tasks_release_deep_dependencies.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/tasks_tests.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/tasks_tests_deep_dependencies.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/tasks_vendor.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/test_includes_extractor.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/test_invoker.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/test_invoker_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/tool_executor.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/tool_executor_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/verbosinator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/version.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/lib/ceedling/yaml_wrapper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/beep/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/beep/lib/beep.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/bullseye/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/bullseye/assets/template.erb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/bullseye/bullseye.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/bullseye/config/defaults.yml (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/bullseye/lib/bullseye.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/colour_report/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/colour_report/lib/colour_report.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/command_hooks/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/compile_commands_json/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/compile_commands_json/lib/compile_commands_json.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/dependencies/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/dependencies/config/defaults.yml (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/dependencies/dependencies.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/dependencies/lib/dependencies.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/Rakefile (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/rakefile.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/bar.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/bar.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/custom_types.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/event_processor.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/event_processor.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/foo.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/foo.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/subfolder/zzz.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/subfolder/zzz.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_event_processor.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_foo.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/lib/fake_function_framework.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/spec/spec_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/gcov/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/gcov/assets/template.erb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/gcov/config/defaults_gcov.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/gcov/gcov.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/gcov/lib/gcov.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/gcov/lib/gcov_constants.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/gcov/lib/gcovr_reportinator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/gcov/lib/reportgenerator_reportinator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/json_tests_report/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/junit_tests_report/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/junit_tests_report/lib/junit_tests_report.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/module_generator/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/module_generator/config/module_generator.yml (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/module_generator/lib/module_generator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/module_generator/module_generator.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/raw_output_report/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/raw_output_report/lib/raw_output_report.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/stdout_gtestlike_tests_report/assets/template.erb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/stdout_gtestlike_tests_report/assets/template.erb copy (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/stdout_gtestlike_tests_report/config/stdout_gtestlike_tests_report.yml (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/stdout_gtestlike_tests_report/lib/stdout_gtestlike_tests_report.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/stdout_ide_tests_report/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/stdout_ide_tests_report/config/stdout_ide_tests_report.yml (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/stdout_ide_tests_report/lib/stdout_ide_tests_report.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md (100%)
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 rename test/{ => unit-test}/vendor/ceedling/plugins/stdout_pretty_tests_report/config/stdout_pretty_tests_report.yml (100%)
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 rename test/{ => unit-test}/vendor/ceedling/plugins/subprojects/README.md (100%)
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 rename test/{ => unit-test}/vendor/ceedling/plugins/subprojects/subprojects.rake (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/teamcity_tests_report/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/teamcity_tests_report/config/teamcity_tests_report.yml (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/teamcity_tests_report/lib/teamcity_tests_report.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/warnings_report/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/warnings_report/lib/warnings_report.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/xml_tests_report/README.md (100%)
 rename test/{ => unit-test}/vendor/ceedling/plugins/xml_tests_report/lib/xml_tests_report.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/c_exception/lib/CException.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/c_exception/lib/CException.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/c_exception/lib/meson.build (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/config/production_environment.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/config/test_environment.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_config.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_file_writer.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_array.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_callback.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_cexception.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_expect_any_args.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_arg.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_stateless.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_generator_utils.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_plugin_manager.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/lib/cmock_unityhelper_parser.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/src/cmock.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/src/cmock.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/src/cmock_internals.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/cmock/src/meson.build (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/diy/lib/diy.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/diy/lib/diy/factory.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/colour_prompt.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/colour_reporter.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/generate_config.yml (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/generate_module.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/parse_output.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/run_test.erb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/stylize_as_junit.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/test_file_filter.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/type_sanitizer.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/unity_test_summary.py (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/unity_test_summary.rb (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/auto/unity_to_junit.py (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/src/meson.build (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/src/unity.c (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/src/unity.h (100%)
 rename test/{ => unit-test}/vendor/ceedling/vendor/unity/src/unity_internals.h (100%)

diff --git a/test/ceedling b/test/unit-test/ceedling
similarity index 100%
rename from test/ceedling
rename to test/unit-test/ceedling
diff --git a/test/project.yml b/test/unit-test/project.yml
similarity index 99%
rename from test/project.yml
rename to test/unit-test/project.yml
index 1bccc517f..7708123d5 100644
--- a/test/project.yml
+++ b/test/unit-test/project.yml
@@ -36,7 +36,7 @@
     - +:test/**
     - -:test/support
   :source:
-    - ../src/**
+    - ../../src/**
   :support:
     - test/support
 
diff --git a/test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c
similarity index 100%
rename from test/test/device/msc/test_msc_device.c
rename to test/unit-test/test/device/msc/test_msc_device.c
diff --git a/test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c
similarity index 100%
rename from test/test/device/usbd/test_usbd.c
rename to test/unit-test/test/device/usbd/test_usbd.c
diff --git a/test/test/support/tusb_config.h b/test/unit-test/test/support/tusb_config.h
similarity index 100%
rename from test/test/support/tusb_config.h
rename to test/unit-test/test/support/tusb_config.h
diff --git a/test/test/test_fifo.c b/test/unit-test/test/test_fifo.c
similarity index 100%
rename from test/test/test_fifo.c
rename to test/unit-test/test/test_fifo.c
diff --git a/test/vendor/ceedling/bin/ceedling b/test/unit-test/vendor/ceedling/bin/ceedling
similarity index 100%
rename from test/vendor/ceedling/bin/ceedling
rename to test/unit-test/vendor/ceedling/bin/ceedling
diff --git a/test/vendor/ceedling/lib/ceedling.rb b/test/unit-test/vendor/ceedling/lib/ceedling.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling.rb
diff --git a/test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
diff --git a/test/vendor/ceedling/lib/ceedling/cacheinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/cacheinator.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/cacheinator.rb
diff --git a/test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/cmock_builder.rb b/test/unit-test/vendor/ceedling/lib/ceedling/cmock_builder.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/cmock_builder.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/cmock_builder.rb
diff --git a/test/vendor/ceedling/lib/ceedling/configurator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/configurator.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/configurator.rb
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_builder.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_builder.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/configurator_builder.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/configurator_builder.rb
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_plugins.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_setup.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_setup.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/configurator_setup.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/configurator_setup.rb
diff --git a/test/vendor/ceedling/lib/ceedling/configurator_validator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_validator.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/configurator_validator.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/configurator_validator.rb
diff --git a/test/vendor/ceedling/lib/ceedling/constants.rb b/test/unit-test/vendor/ceedling/lib/ceedling/constants.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/constants.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/constants.rb
diff --git a/test/vendor/ceedling/lib/ceedling/defaults.rb b/test/unit-test/vendor/ceedling/lib/ceedling/defaults.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/defaults.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/defaults.rb
diff --git a/test/vendor/ceedling/lib/ceedling/dependinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/dependinator.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/dependinator.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/dependinator.rb
diff --git a/test/vendor/ceedling/lib/ceedling/erb_wrapper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/erb_wrapper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/erb_wrapper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/erb_wrapper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/file_finder.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_finder.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/file_finder.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/file_finder.rb
diff --git a/test/vendor/ceedling/lib/ceedling/file_finder_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/file_path_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_path_utils.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/file_path_utils.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/file_path_utils.rb
diff --git a/test/vendor/ceedling/lib/ceedling/file_system_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_system_utils.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/file_system_utils.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/file_system_utils.rb
diff --git a/test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/file_wrapper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_wrapper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/file_wrapper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/file_wrapper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/flaginator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/flaginator.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/flaginator.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/flaginator.rb
diff --git a/test/vendor/ceedling/lib/ceedling/generator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/generator.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/generator.rb
diff --git a/test/vendor/ceedling/lib/ceedling/generator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator_helper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/generator_helper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/generator_helper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/generator_test_results.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/generator_test_results.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results.rb
diff --git a/test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb
diff --git a/test/vendor/ceedling/lib/ceedling/generator_test_runner.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_runner.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/generator_test_runner.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/generator_test_runner.rb
diff --git a/test/vendor/ceedling/lib/ceedling/loginator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/loginator.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/loginator.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/loginator.rb
diff --git a/test/vendor/ceedling/lib/ceedling/makefile.rb b/test/unit-test/vendor/ceedling/lib/ceedling/makefile.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/makefile.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/makefile.rb
diff --git a/test/vendor/ceedling/lib/ceedling/objects.yml b/test/unit-test/vendor/ceedling/lib/ceedling/objects.yml
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/objects.yml
rename to test/unit-test/vendor/ceedling/lib/ceedling/objects.yml
diff --git a/test/vendor/ceedling/lib/ceedling/par_map.rb b/test/unit-test/vendor/ceedling/lib/ceedling/par_map.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/par_map.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/par_map.rb
diff --git a/test/vendor/ceedling/lib/ceedling/plugin.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/plugin.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/plugin.rb
diff --git a/test/vendor/ceedling/lib/ceedling/plugin_builder.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_builder.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/plugin_builder.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/plugin_builder.rb
diff --git a/test/vendor/ceedling/lib/ceedling/plugin_manager.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_manager.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/plugin_manager.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/plugin_manager.rb
diff --git a/test/vendor/ceedling/lib/ceedling/plugin_manager_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_manager_helper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/plugin_manager_helper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/plugin_manager_helper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb
diff --git a/test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/preprocessinator.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator.rb
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_extractor.rb
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_file_handler.rb
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_helper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
diff --git a/test/vendor/ceedling/lib/ceedling/project_config_manager.rb b/test/unit-test/vendor/ceedling/lib/ceedling/project_config_manager.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/project_config_manager.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/project_config_manager.rb
diff --git a/test/vendor/ceedling/lib/ceedling/project_file_loader.rb b/test/unit-test/vendor/ceedling/lib/ceedling/project_file_loader.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/project_file_loader.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/project_file_loader.rb
diff --git a/test/vendor/ceedling/lib/ceedling/rake_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/rake_utils.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/rake_utils.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/rake_utils.rb
diff --git a/test/vendor/ceedling/lib/ceedling/rake_wrapper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/rake_wrapper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/rake_wrapper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/rake_wrapper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/rakefile.rb b/test/unit-test/vendor/ceedling/lib/ceedling/rakefile.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/rakefile.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/rakefile.rb
diff --git a/test/vendor/ceedling/lib/ceedling/release_invoker.rb b/test/unit-test/vendor/ceedling/lib/ceedling/release_invoker.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/release_invoker.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/release_invoker.rb
diff --git a/test/vendor/ceedling/lib/ceedling/release_invoker_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/release_invoker_helper.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/release_invoker_helper.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/release_invoker_helper.rb
diff --git a/test/vendor/ceedling/lib/ceedling/reportinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/reportinator.rb
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/reportinator.rb
rename to test/unit-test/vendor/ceedling/lib/ceedling/reportinator.rb
diff --git a/test/vendor/ceedling/lib/ceedling/rules_cmock.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_cmock.rake
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/rules_cmock.rake
rename to test/unit-test/vendor/ceedling/lib/ceedling/rules_cmock.rake
diff --git a/test/vendor/ceedling/lib/ceedling/rules_preprocess.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
rename to test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
diff --git a/test/vendor/ceedling/lib/ceedling/rules_release.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_release.rake
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/rules_release.rake
rename to test/unit-test/vendor/ceedling/lib/ceedling/rules_release.rake
diff --git a/test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake
rename to test/unit-test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake
diff --git a/test/vendor/ceedling/lib/ceedling/rules_tests.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests.rake
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/rules_tests.rake
rename to test/unit-test/vendor/ceedling/lib/ceedling/rules_tests.rake
diff --git a/test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake
similarity index 100%
rename from test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake
rename to test/unit-test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake
diff --git a/test/vendor/ceedling/lib/ceedling/setupinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/setupinator.rb
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diff --git a/test/vendor/ceedling/plugins/module_generator/README.md b/test/unit-test/vendor/ceedling/plugins/module_generator/README.md
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diff --git a/test/vendor/ceedling/plugins/raw_output_report/README.md b/test/unit-test/vendor/ceedling/plugins/raw_output_report/README.md
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diff --git a/test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md
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diff --git a/test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md
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diff --git a/test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md
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diff --git a/test/vendor/ceedling/plugins/subprojects/README.md b/test/unit-test/vendor/ceedling/plugins/subprojects/README.md
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diff --git a/test/vendor/ceedling/plugins/teamcity_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/teamcity_tests_report/README.md
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diff --git a/test/vendor/ceedling/plugins/warnings_report/README.md b/test/unit-test/vendor/ceedling/plugins/warnings_report/README.md
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diff --git a/test/vendor/ceedling/plugins/xml_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/xml_tests_report/README.md
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diff --git a/test/vendor/ceedling/vendor/c_exception/lib/CException.c b/test/unit-test/vendor/ceedling/vendor/c_exception/lib/CException.c
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diff --git a/test/vendor/ceedling/vendor/cmock/config/production_environment.rb b/test/unit-test/vendor/ceedling/vendor/cmock/config/production_environment.rb
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diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb b/test/unit-test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore.rb
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diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_stateless.rb b/test/unit-test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_ignore_stateless.rb
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diff --git a/test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb b/test/unit-test/vendor/ceedling/vendor/cmock/lib/cmock_generator_plugin_return_thru_ptr.rb
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similarity index 100%
rename from test/vendor/ceedling/vendor/unity/auto/generate_module.rb
rename to test/unit-test/vendor/ceedling/vendor/unity/auto/generate_module.rb
diff --git a/test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb b/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
rename to test/unit-test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
diff --git a/test/vendor/ceedling/vendor/unity/auto/parse_output.rb b/test/unit-test/vendor/ceedling/vendor/unity/auto/parse_output.rb
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/auto/parse_output.rb
rename to test/unit-test/vendor/ceedling/vendor/unity/auto/parse_output.rb
diff --git a/test/vendor/ceedling/vendor/unity/auto/run_test.erb b/test/unit-test/vendor/ceedling/vendor/unity/auto/run_test.erb
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/auto/run_test.erb
rename to test/unit-test/vendor/ceedling/vendor/unity/auto/run_test.erb
diff --git a/test/vendor/ceedling/vendor/unity/auto/stylize_as_junit.rb b/test/unit-test/vendor/ceedling/vendor/unity/auto/stylize_as_junit.rb
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/auto/stylize_as_junit.rb
rename to test/unit-test/vendor/ceedling/vendor/unity/auto/stylize_as_junit.rb
diff --git a/test/vendor/ceedling/vendor/unity/auto/test_file_filter.rb b/test/unit-test/vendor/ceedling/vendor/unity/auto/test_file_filter.rb
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/auto/test_file_filter.rb
rename to test/unit-test/vendor/ceedling/vendor/unity/auto/test_file_filter.rb
diff --git a/test/vendor/ceedling/vendor/unity/auto/type_sanitizer.rb b/test/unit-test/vendor/ceedling/vendor/unity/auto/type_sanitizer.rb
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/auto/type_sanitizer.rb
rename to test/unit-test/vendor/ceedling/vendor/unity/auto/type_sanitizer.rb
diff --git a/test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py
rename to test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py
diff --git a/test/vendor/ceedling/vendor/unity/auto/unity_test_summary.rb b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.rb
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/auto/unity_test_summary.rb
rename to test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.rb
diff --git a/test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py
rename to test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py
diff --git a/test/vendor/ceedling/vendor/unity/src/meson.build b/test/unit-test/vendor/ceedling/vendor/unity/src/meson.build
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/src/meson.build
rename to test/unit-test/vendor/ceedling/vendor/unity/src/meson.build
diff --git a/test/vendor/ceedling/vendor/unity/src/unity.c b/test/unit-test/vendor/ceedling/vendor/unity/src/unity.c
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/src/unity.c
rename to test/unit-test/vendor/ceedling/vendor/unity/src/unity.c
diff --git a/test/vendor/ceedling/vendor/unity/src/unity.h b/test/unit-test/vendor/ceedling/vendor/unity/src/unity.h
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/src/unity.h
rename to test/unit-test/vendor/ceedling/vendor/unity/src/unity.h
diff --git a/test/vendor/ceedling/vendor/unity/src/unity_internals.h b/test/unit-test/vendor/ceedling/vendor/unity/src/unity_internals.h
similarity index 100%
rename from test/vendor/ceedling/vendor/unity/src/unity_internals.h
rename to test/unit-test/vendor/ceedling/vendor/unity/src/unity_internals.h

From 34081f6c5c0fa4541a2eba5fdd8cc0cfbfe35951 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 10:00:25 +0700
Subject: [PATCH 1274/2085] update ci

---
 .github/workflows/pre-commit.yml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index c0261ec66..96a59069b 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -1,8 +1,9 @@
 name: pre-commit
 
 on:
-  pull_request:
   push:
+  pull_request:
+    branches: [ master ]
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
@@ -32,5 +33,5 @@ jobs:
       run: |
         # Install Ceedling
         gem install ceedling
-        cd test
+        cd test/unit-test
         ceedling test:all
\ No newline at end of file

From a29b3dd690d4ccc9f3432ca5ec5d702b1ae80e78 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 10:05:52 +0700
Subject: [PATCH 1275/2085] update .codespell

---
 .codespellrc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.codespellrc b/.codespellrc
index 142bbbe1a..8c32ed706 100644
--- a/.codespellrc
+++ b/.codespellrc
@@ -7,4 +7,4 @@ exclude-file = .codespell/exclude-file.txt
 check-filenames =
 check-hidden =
 count =
-skip = .cproject,./.git,./hw/mcu,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./test/vendor,./tests_obsolete,./tools/uf2
+skip = .cproject,./.git,./hw/mcu,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./test/unit-test/vendor,./tests_obsolete,./tools/uf2

From aedae6201b2e328baf557f1417bb5c83615ca640 Mon Sep 17 00:00:00 2001
From: Nathaniel Brough <nathaniel.brough@gmail.com>
Date: Thu, 27 Oct 2022 22:56:31 +0000
Subject: [PATCH 1276/2085] fuzz: Add support for fuzzing

Adds support for fuzzing with basic cdc fuzzer.
---
 fuzz/dcd_fuzz.cc                       | 202 ++++++++++++++++++++++
 fuzz/device/cdc/CMakeLists.txt         |  29 ++++
 fuzz/device/cdc/Makefile               |  12 ++
 fuzz/device/cdc/skip.txt               |   1 +
 fuzz/device/cdc/src/fuzz.cc            | 174 +++++++++++++++++++
 fuzz/device/cdc/src/tusb_config.h      | 114 ++++++++++++
 fuzz/device/cdc/src/usb_descriptors.cc | 229 +++++++++++++++++++++++++
 fuzz/dicts/cdc.dict                    |  74 ++++++++
 fuzz/fuzz.cc                           |  34 ++++
 fuzz/fuzz.h                            |  37 ++++
 fuzz/fuzz_private.h                    |  30 ++++
 fuzz/make.mk                           | 100 +++++++++++
 fuzz/rules.mk                          | 160 +++++++++++++++++
 fuzz/usbd_fuzz.cc                      |  73 ++++++++
 14 files changed, 1269 insertions(+)
 create mode 100644 fuzz/dcd_fuzz.cc
 create mode 100644 fuzz/device/cdc/CMakeLists.txt
 create mode 100644 fuzz/device/cdc/Makefile
 create mode 100644 fuzz/device/cdc/skip.txt
 create mode 100644 fuzz/device/cdc/src/fuzz.cc
 create mode 100644 fuzz/device/cdc/src/tusb_config.h
 create mode 100644 fuzz/device/cdc/src/usb_descriptors.cc
 create mode 100644 fuzz/dicts/cdc.dict
 create mode 100644 fuzz/fuzz.cc
 create mode 100644 fuzz/fuzz.h
 create mode 100644 fuzz/fuzz_private.h
 create mode 100644 fuzz/make.mk
 create mode 100644 fuzz/rules.mk
 create mode 100644 fuzz/usbd_fuzz.cc

diff --git a/fuzz/dcd_fuzz.cc b/fuzz/dcd_fuzz.cc
new file mode 100644
index 000000000..94d504a2c
--- /dev/null
+++ b/fuzz/dcd_fuzz.cc
@@ -0,0 +1,202 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+#include "device/dcd.h"
+#include "fuzz/fuzz_private.h"
+#include <assert.h>
+#include <cstdint>
+#include <limits>
+
+#define UNUSED(x) (void)(x)
+
+//--------------------------------------------------------------------+
+// State tracker
+//--------------------------------------------------------------------+
+struct State {
+  bool interrupts_enabled;
+  bool sof_enabled;
+  uint8_t address;
+};
+
+static State state = {false, 0, 0};
+
+//--------------------------------------------------------------------+
+// Controller API
+// All no-ops as we are fuzzing.
+//--------------------------------------------------------------------+
+extern "C" {
+void dcd_init(uint8_t rhport) {
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_int_handler(uint8_t rhport) {
+  assert(_fuzz_data_provider.has_value());
+
+  if (!state.interrupts_enabled) {
+    return;
+  }
+
+  // Choose if we want to generate a signal based on the fuzzed data.
+  if (_fuzz_data_provider->ConsumeBool()) {
+    dcd_event_bus_signal(
+        rhport,
+        // Choose a random event based on the fuzz data.
+        (dcd_eventid_t)_fuzz_data_provider->ConsumeIntegralInRange<uint8_t>(
+            DCD_EVENT_INVALID + 1, DCD_EVENT_COUNT - 1),
+        // Identify trigger as either an interrupt or a syncrhonous call
+        // depending on fuzz data.
+        _fuzz_data_provider->ConsumeBool());
+  }
+
+  if (_fuzz_data_provider->ConsumeBool()) {
+    constexpr size_t kSetupFrameLength = 8;
+    std::vector<uint8_t> setup =
+        _fuzz_data_provider->ConsumeBytes<uint8_t>(kSetupFrameLength);
+    // Fuzz consumer may return less than requested. If this is the case
+    // we want to make sure that at least that length is allocated and available
+    // to the signal handler.
+    if (setup.size() != kSetupFrameLength) {
+      setup.resize(kSetupFrameLength);
+    }
+    dcd_event_setup_received(rhport, setup.data(),
+                             // Identify trigger as either an interrupt or a
+                             // syncrhonous call depending on fuzz data.
+                             _fuzz_data_provider->ConsumeBool());
+  }
+}
+
+void dcd_int_enable(uint8_t rhport) {
+  state.interrupts_enabled = true;
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_int_disable(uint8_t rhport) {
+  state.interrupts_enabled = false;
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  UNUSED(rhport);
+  state.address = dev_addr;
+  // Respond with status.
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  return;
+}
+
+void dcd_remote_wakeup(uint8_t rhport) {
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_connect(uint8_t rhport) {
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_disconnect(uint8_t rhport) {
+  UNUSED(rhport);
+  return;
+}
+
+void dcd_sof_enable(uint8_t rhport, bool en) {
+  state.sof_enabled = en;
+  UNUSED(rhport);
+  return;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
+  UNUSED(rhport);
+  UNUSED(desc_ep);
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+// Close all non-control endpoints, cancel all pending transfers if any.
+// Invoked when switching from a non-zero Configuration by SET_CONFIGURE
+// therefore required for multiple configuration support.
+void dcd_edpt_close_all(uint8_t rhport) {
+  UNUSED(rhport);
+  return;
+}
+
+// Close an endpoint.
+// Since it is weak, caller must TU_ASSERT this function's existence before
+// calling it.
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
+  UNUSED(rhport);
+  UNUSED(ep_addr);
+  return;
+}
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to
+// notify the stack
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer,
+                   uint16_t total_bytes) {
+  UNUSED(rhport);
+  UNUSED(buffer);
+  UNUSED(total_bytes);
+
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+
+  if (dir == TUSB_DIR_IN) {
+    std::vector<uint8_t> temp =
+        _fuzz_data_provider->ConsumeBytes<uint8_t>(total_bytes);
+    std::copy(temp.begin(), temp.end(), buffer);
+  }
+  // Ignore output data as it's not useful for fuzzing without a more
+  // complex fuzzed backend.
+
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+/* TODO: implement a fuzzed version of this.
+bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff,
+                        uint16_t total_bytes) {} 
+*/
+
+// Stall endpoint, any queuing transfer should be removed from endpoint
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
+
+  UNUSED(rhport);
+  UNUSED(ep_addr);
+  return;
+}
+
+// clear stall, data toggle is also reset to DATA0
+// This API never calls with control endpoints, since it is auto cleared when
+// receiving setup packet
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
+
+  UNUSED(rhport);
+  UNUSED(ep_addr);
+  return;
+}
+}
\ No newline at end of file
diff --git a/fuzz/device/cdc/CMakeLists.txt b/fuzz/device/cdc/CMakeLists.txt
new file mode 100644
index 000000000..fa6e83b7e
--- /dev/null
+++ b/fuzz/device/cdc/CMakeLists.txt
@@ -0,0 +1,29 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/fuzz/device/cdc/Makefile b/fuzz/device/cdc/Makefile
new file mode 100644
index 000000000..76a43923f
--- /dev/null
+++ b/fuzz/device/cdc/Makefile
@@ -0,0 +1,12 @@
+include ../../../tools/top.mk
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.c))
+SRC_CXX += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.cc))
+
+include ../../rules.mk
diff --git a/fuzz/device/cdc/skip.txt b/fuzz/device/cdc/skip.txt
new file mode 100644
index 000000000..d844feae8
--- /dev/null
+++ b/fuzz/device/cdc/skip.txt
@@ -0,0 +1 @@
+mcu:SAMD11
\ No newline at end of file
diff --git a/fuzz/device/cdc/src/fuzz.cc b/fuzz/device/cdc/src/fuzz.cc
new file mode 100644
index 000000000..f783125f9
--- /dev/null
+++ b/fuzz/device/cdc/src/fuzz.cc
@@ -0,0 +1,174 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <cassert>
+#include <fuzzer/FuzzedDataProvider.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "class/cdc/cdc_device.h"
+#include "fuzz/fuzz.h"
+#include "tusb.h"
+#include <cstdint>
+#include <string>
+#include <vector>
+
+extern "C" {
+
+#define FUZZ_ITERATIONS 500
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+void cdc_task(FuzzedDataProvider *provider);
+
+extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) {
+  FuzzedDataProvider provider(Data, Size);
+  std::vector<uint8_t> callback_data = provider.ConsumeBytes<uint8_t>(
+      provider.ConsumeIntegralInRange<size_t>(0, Size));
+  fuzz_init(callback_data.data(), callback_data.size());
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
+
+  for (int i = 0; i < FUZZ_ITERATIONS; i++) {
+    if (provider.remaining_bytes() == 0) {
+      return 0;
+    }
+    tud_int_handler(provider.ConsumeIntegral<uint8_t>());
+    tud_task(); // tinyusb device task
+    cdc_task(&provider);
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// USB CDC
+//--------------------------------------------------------------------+
+enum CdcApiFuncs {
+  kCdcNConnected,
+  kCdcNGetLineState,
+  kCdcNGetLineCoding,
+  kCdcNSetWantedChar,
+  kCdcNAvailable,
+  kCdcNRead,
+  kCdcNReadChar,
+  kCdcNReadFlush,
+  kCdcNPeek,
+  kCdcNWrite,
+  kCdcNWriteChar,
+  kCdcNWriteStr,
+  kCdcNWriteFlush,
+  kCdcNWriteAvailable,
+  kCdcNWriteClear,
+  // We don't need to fuzz tud_cdc_<not n>* as they are just wrappers
+  // calling with n==0.
+  kMaxValue,
+};
+
+void cdc_task(FuzzedDataProvider *provider) {
+
+  assert(provider != NULL);
+  const int kMaxBufferSize = 4096;
+  switch (provider->ConsumeEnum<CdcApiFuncs>()) {
+  case kCdcNConnected:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_connected(0);
+    break;
+  case kCdcNGetLineState:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_get_line_state(0);
+    break;
+  case kCdcNGetLineCoding: {
+    cdc_line_coding_t coding;
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_get_line_coding(0, &coding);
+  } break;
+  case kCdcNSetWantedChar:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_set_wanted_char(0, provider->ConsumeIntegral<char>());
+    break;
+  case kCdcNAvailable:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_available(0);
+    break;
+  case kCdcNRead: {
+    std::vector<uint8_t> buffer;
+    buffer.resize(provider->ConsumeIntegralInRange<size_t>(0, kMaxBufferSize));
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_read(0, buffer.data(), buffer.size());
+    break;
+  }
+  case kCdcNReadChar:
+    // TODO: Fuzz interface number
+    tud_cdc_n_read_char(0);
+    break;
+  case kCdcNReadFlush:
+    // TODO: Fuzz interface number
+    tud_cdc_n_read_flush(0);
+    break;
+  case kCdcNPeek: {
+    uint8_t peak = 0;
+    tud_cdc_n_peek(0, &peak);
+    break;
+  }
+  case kCdcNWrite: {
+    std::vector<uint8_t> buffer = provider->ConsumeBytes<uint8_t>(
+        provider->ConsumeIntegralInRange<size_t>(0, kMaxBufferSize));
+
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_write(0, buffer.data(), buffer.size());
+    break;
+  }
+  case kCdcNWriteChar:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_write_char(0, provider->ConsumeIntegral<char>());
+    break;
+  case kCdcNWriteStr: {
+    std::string str = provider->ConsumeRandomLengthString(kMaxBufferSize);
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_write_str(0, str.c_str());
+    break;
+  }
+  case kCdcNWriteFlush:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_write_flush(0);
+    break;
+  case kCdcNWriteAvailable:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_write_available(0);
+    break;
+  case kCdcNWriteClear:
+    // TODO: Fuzz interface number
+    (void)tud_cdc_n_write_clear(0);
+    break;
+  case kMaxValue:
+    // Noop.
+    break;
+  }
+}
+}
\ No newline at end of file
diff --git a/fuzz/device/cdc/src/tusb_config.h b/fuzz/device/cdc/src/tusb_config.h
new file mode 100644
index 000000000..10a8a825a
--- /dev/null
+++ b/fuzz/device/cdc/src/tusb_config.h
@@ -0,0 +1,114 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN    __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC              1
+#define CFG_TUD_MSC              0
+#define CFG_TUD_HID              0
+#define CFG_TUD_MIDI             0
+#define CFG_TUD_VENDOR           0
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// MSC Buffer size of Device Mass storage
+#define CFG_TUD_MSC_EP_BUFSIZE   512
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/fuzz/device/cdc/src/usb_descriptors.cc b/fuzz/device/cdc/src/usb_descriptors.cc
new file mode 100644
index 000000000..0f636f05d
--- /dev/null
+++ b/fuzz/device/cdc/src/usb_descriptors.cc
@@ -0,0 +1,229 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save
+ * device driver after the first plug.
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]         HID | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n))
+#define USB_PID                                                                \
+  (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(HID, 2) | _PID_MAP(MIDI, 3) |          \
+   _PID_MAP(VENDOR, 4))
+
+#define USB_VID 0xCafe
+#define USB_BCD 0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const *tud_descriptor_device_cb(void) {
+  static tusb_desc_device_t const desc_device = {
+      .bLength = sizeof(tusb_desc_device_t),
+      .bDescriptorType = TUSB_DESC_DEVICE,
+      .bcdUSB = USB_BCD,
+
+      // Use Interface Association Descriptor (IAD) for CDC
+      // As required by USB Specs IAD's subclass must be common class (2) and
+      // protocol must be IAD (1)
+      .bDeviceClass = TUSB_CLASS_MISC,
+      .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+      .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+      .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+      .idVendor = USB_VID,
+      .idProduct = USB_PID,
+      .bcdDevice = 0x0100,
+
+      .iManufacturer = 0x01,
+      .iProduct = 0x02,
+      .iSerialNumber = 0x03,
+
+      .bNumConfigurations = 0x01};
+
+  return (uint8_t const *)&desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+enum { ITF_NUM_CDC = 0, ITF_NUM_CDC_DATA, ITF_NUM_TOTAL };
+
+#define EPNUM_CDC_NOTIF 0x81
+#define EPNUM_CDC_OUT 0x02
+#define EPNUM_CDC_IN 0x82
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
+
+// full speed configuration
+uint8_t const desc_fs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP notification address and size, EP data
+    // address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT,
+                       EPNUM_CDC_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and
+// other_speed_configuration
+
+// high speed configuration
+uint8_t const desc_hs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP notification address and size, EP data
+    // address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT,
+                       EPNUM_CDC_IN, 512),
+};
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change
+// configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength = sizeof(tusb_desc_device_qualifier_t),
+    .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
+    .bcdUSB = USB_BCD,
+
+    .bDeviceClass = TUSB_CLASS_MISC,
+    .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved = 0x00};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete. device_qualifier descriptor describes
+// information about a high-speed capable device that would change if the device
+// were operating at the other speed. If not highspeed capable stall this
+// request.
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const *)&desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete Configuration descriptor in the other speed
+// e.g if high speed then this is for full speed and vice versa
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration
+                                              : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration
+                                              : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] = {
+    (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                  // 1: Manufacturer
+    "TinyUSB Device",           // 2: Product
+    "123456789012",             // 3: Serials, should use chip ID
+    "TinyUSB CDC",              // 4: CDC Interface
+};
+
+static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void)langid;
+
+  uint8_t chr_count;
+
+  if (index == 0) {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  } else {
+    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+    if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])))
+      return NULL;
+
+    const char *str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = (uint8_t)strlen(str);
+    if (chr_count > 31)
+      chr_count = 31;
+
+    // Convert ASCII string into UTF-16
+    for (uint8_t i = 0; i < chr_count; i++) {
+      _desc_str[1 + i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/fuzz/dicts/cdc.dict b/fuzz/dicts/cdc.dict
new file mode 100644
index 000000000..138775cdc
--- /dev/null
+++ b/fuzz/dicts/cdc.dict
@@ -0,0 +1,74 @@
+# List of supported OIDs
+RNDIS_OID_GEN_SUPPORTED_LIST="\x00\x01\x01\x01"
+# Hardware status
+RNDIS_OID_GEN_HARDWARE_STATUS="\x00\x01\x01\x02"
+# Media types supported (encoded)
+RNDIS_OID_GEN_MEDIA_SUPPORTED="\x00\x01\x01\x03"
+# Media types in use (encoded)
+RNDIS_OID_GEN_MEDIA_IN_USE="\x00\x01\x01\x04"
+RNDIS_OID_GEN_MAXIMUM_LOOKAHEAD="\x00\x01\x01\x05"
+# Maximum frame size in bytes
+RNDIS_OID_GEN_MAXIMUM_FRAME_SIZE="\x00\x01\x01\x06"
+# Link speed in units of 100 bps
+RNDIS_OID_GEN_LINK_SPEED="\x00\x01\x01\x07"
+# Transmit buffer space
+RNDIS_OID_GEN_TRANSMIT_BUFFER_SPACE="\x00\x01\x01\x08"
+# Receive buffer space
+RNDIS_OID_GEN_RECEIVE_BUFFER_SPACE="\x00\x01\x01\x09"
+# NDIS version number used by the driver
+RNDIS_OID_GEN_DRIVER_VERSION="\x00\x01\x01\x10"
+# Maximum total packet length in bytes
+RNDIS_OID_GEN_MAXIMUM_TOTAL_SIZE="\x00\x01\x01\x11"
+# Optional protocol flags (encoded)
+RNDIS_OID_GEN_PROTOCOL_OPTIONS="\x00\x01\x01\x12"
+# Optional NIC flags (encoded)
+RNDIS_OID_GEN_MAC_OPTIONS="\x00\x01\x01\x13"
+# Whether the NIC is connected to the network
+RNDIS_OID_GEN_MEDIA_CONNECT_STATUS="\x00\x01\x01\x14"
+# The maximum number of send packets the driver can accept per call to its MiniportSendPacketsfunction
+RNDIS_OID_GEN_MAXIMUM_SEND_PACKETS="\x00\x01\x01\x15"
+# Vendor-assigned version number of the driver
+RNDIS_OID_GEN_VENDOR_DRIVER_VERSION="\x00\x01\x01\x16"
+# The custom GUIDs (Globally Unique Identifier) supported by the miniport driver
+RNDIS_OID_GEN_SUPPORTED_GUIDS="\x00\x01\x01\x17"
+# List of network-layer addresses associated with the binding between a transport and the driver
+RNDIS_OID_GEN_NETWORK_LAYER_ADDRESSES="\x00\x01\x01\x18"
+# Size of packets' additional headers
+RNDIS_OID_GEN_TRANSPORT_HEADER_OFFSET="\x00\x01\x01\x19"
+RNDIS_OID_GEN_MEDIA_CAPABILITIES="\x00\x01\x02\x01"
+# Physical media supported by the miniport driver (encoded)
+RNDIS_OID_GEN_PHYSICAL_MEDIUM="\x00\x01\x02\x02"
+# Permanent station address
+RNDIS_OID_802_3_PERMANENT_ADDRESS="\x01\x01\x01\x01"
+# Current station address
+RNDIS_OID_802_3_CURRENT_ADDRESS="\x01\x01\x01\x02"
+# Current multicast address list
+RNDIS_OID_802_3_MULTICAST_LIST="\x01\x01\x01\x03"
+# Maximum size of multicast address list
+RNDIS_OID_802_3_MAXIMUM_LIST_SIZE="\x01\x01\x01\x04"
+# Directed packets. Directed packets contain a destination address equal to the station address of the NIC.
+RNDIS_PACKET_TYPE_DIRECTED="\x00\x00\x00\x01"
+# Multicast address packets sent to addresses in the multicast address list.
+RNDIS_PACKET_TYPE_MULTICAST="\x00\x00\x00\x02"
+# All multicast address packets, not just the ones enumerated in the multicast address list.
+RNDIS_PACKET_TYPE_ALL_MULTICAST="\x00\x00\x00\x04"
+# Broadcast packets.
+RNDIS_PACKET_TYPE_BROADCAST="\x00\x00\x00\x08"
+# All source routing packets. If the protocol driver sets this bit, the NDIS library attempts to act as a source routing bridge.
+RNDIS_PACKET_TYPE_SOURCE_ROUTING="\x00\x00\x00\x10"
+# Specifies all packets regardless of whether VLAN filtering is enabled or not and whether the VLAN identifier matches or not.
+RNDIS_PACKET_TYPE_PROMISCUOUS="\x00\x00\x00\x20"
+# SMT packets that an FDDI NIC receives.
+RNDIS_PACKET_TYPE_SMT="\x00\x00\x00\x40"
+# All packets sent by installed protocols and all packets indicated by the NIC that is identified by a given NdisBindingHandle.
+RNDIS_PACKET_TYPE_ALL_LOCAL="\x00\x00\x00\x80"
+# Packets sent to the current group address.
+RNDIS_PACKET_TYPE_GROUP="\x00\x00\x10\x00"
+# All functional address packets, not just the ones in the current functional address.
+RNDIS_PACKET_TYPE_ALL_FUNCTIONAL="\x00\x00\x20\x00"
+# Functional address packets sent to addresses included in the current functional address.
+RNDIS_PACKET_TYPE_FUNCTIONAL="\x00\x00\x40\x00"
+# NIC driver frames that a Token Ring NIC receives.
+RNDIS_PACKET_TYPE_MAC_FRAME="\x00\x00\x80\x00"
+RNDIS_PACKET_TYPE_NO_LOCAL="\x00\x01\x00\x00"
+
diff --git a/fuzz/fuzz.cc b/fuzz/fuzz.cc
new file mode 100644
index 000000000..2e4186f1a
--- /dev/null
+++ b/fuzz/fuzz.cc
@@ -0,0 +1,34 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "fuzzer/FuzzedDataProvider.h"
+#include <optional>
+
+std::optional<FuzzedDataProvider> _fuzz_data_provider;
+
+extern "C" int fuzz_init(const uint8_t *data, size_t size) {
+  _fuzz_data_provider.emplace(data, size);
+  return 0;
+}
diff --git a/fuzz/fuzz.h b/fuzz/fuzz.h
new file mode 100644
index 000000000..6aa4949a1
--- /dev/null
+++ b/fuzz/fuzz.h
@@ -0,0 +1,37 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#pragma once
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int fuzz_init(const uint8_t *data, size_t size);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/fuzz/fuzz_private.h b/fuzz/fuzz_private.h
new file mode 100644
index 000000000..0d791fcdc
--- /dev/null
+++ b/fuzz/fuzz_private.h
@@ -0,0 +1,30 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#pragma once
+#include "fuzzer/FuzzedDataProvider.h"
+#include <optional>
+
+extern std::optional<FuzzedDataProvider> _fuzz_data_provider;
diff --git a/fuzz/make.mk b/fuzz/make.mk
new file mode 100644
index 000000000..0921fc8f3
--- /dev/null
+++ b/fuzz/make.mk
@@ -0,0 +1,100 @@
+# ---------------------------------------
+# Common make definition for all examples
+# ---------------------------------------
+
+# Build directory
+BUILD := _build
+PROJECT := $(notdir $(CURDIR))
+
+# Handy check parameter function
+check_defined = \
+    $(strip $(foreach 1,$1, \
+    $(call __check_defined,$1,$(strip $(value 2)))))
+__check_defined = \
+    $(if $(value $1),, \
+    $(error Undefined make flag: $1$(if $2, ($2))))
+
+#-------------- Fuzz harness compiler  ------------
+
+CC ?=  clang
+CXX ?= clang++
+GDB ?= gdb
+OBJCOPY = objcopy
+SIZE = size
+MKDIR = mkdir
+
+ifeq ($(CMDEXE),1)
+  CP = copy
+  RM = del
+  PYTHON = python
+else
+  SED = sed
+  CP = cp
+  RM = rm
+  PYTHON = python3
+endif
+
+#-------------- Source files and compiler flags --------------
+
+
+INC   += $(TOP)/$(FAMILY_PATH)
+
+# Compiler Flags
+CFLAGS += \
+  -ggdb \
+  -fsanitize=fuzzer \
+  -fdata-sections \
+  -ffunction-sections \
+  -fno-strict-aliasing \
+  -Wall \
+  -Wextra \
+  -Werror \
+  -Wfatal-errors \
+  -Wdouble-promotion \
+  -Wstrict-prototypes \
+  -Wstrict-overflow \
+  -Werror-implicit-function-declaration \
+  -Wfloat-equal \
+  -Wundef \
+  -Wshadow \
+  -Wwrite-strings \
+  -Wsign-compare \
+  -Wmissing-format-attribute \
+  -Wunreachable-code \
+  -Wcast-align \
+  -Wcast-qual \
+  -Wnull-dereference \
+  -Wuninitialized \
+  -Wunused \
+  -Wredundant-decls
+
+CFLAGS += \
+  -DOPT_MCU_FUZZ=1 \
+  -DCFG_TUSB_MCU=OPT_MCU_FUZZ 
+
+CXXFLAGS += \
+  -xc++ \
+  -Wno-c++11-narrowing \
+  -fno-implicit-templates
+
+# conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion
+#  -Wconversion
+  
+# Debugging/Optimization
+ifeq ($(DEBUG), 1)
+  CFLAGS += -Og
+else
+  CFLAGS += $(CFLAGS_OPTIMIZED)
+endif
+
+# Log level is mapped to TUSB DEBUG option
+ifneq ($(LOG),)
+  CMAKE_DEFSYM +=	-DLOG=$(LOG)
+  CFLAGS += -DCFG_TUSB_DEBUG=$(LOG)
+endif
+
+# Logger: default is uart, can be set to rtt or swo
+ifneq ($(LOGGER),)
+	CMAKE_DEFSYM +=	-DLOGGER=$(LOGGER)
+endif
+
diff --git a/fuzz/rules.mk b/fuzz/rules.mk
new file mode 100644
index 000000000..aedc7fe83
--- /dev/null
+++ b/fuzz/rules.mk
@@ -0,0 +1,160 @@
+# ---------------------------------------
+# Common make rules for all examples
+# ---------------------------------------
+
+# Set all as default goal
+.DEFAULT_GOAL := all
+
+# ---------------------------------------
+# Compiler Flags
+# ---------------------------------------
+
+LIBS_GCC ?=  -lm
+
+# libc
+LIBS += $(LIBS_GCC)
+
+ifneq ($(BOARD), spresense)
+LIBS += -lc -Wl,-Bstatic -lc++ -lc++abi -Wl,-Bdynamic
+endif
+
+# TinyUSB Stack source
+SRC_C += \
+	src/tusb.c \
+	src/common/tusb_fifo.c \
+	src/device/usbd.c \
+	src/device/usbd_control.c \
+	src/class/audio/audio_device.c \
+	src/class/cdc/cdc_device.c \
+	src/class/dfu/dfu_device.c \
+	src/class/dfu/dfu_rt_device.c \
+	src/class/hid/hid_device.c \
+	src/class/midi/midi_device.c \
+	src/class/msc/msc_device.c \
+	src/class/net/ecm_rndis_device.c \
+	src/class/net/ncm_device.c \
+	src/class/usbtmc/usbtmc_device.c \
+	src/class/video/video_device.c \
+	src/class/vendor/vendor_device.c
+
+
+# Fuzzers are c++
+SRC_CXX += \
+	fuzz/dcd_fuzz.cc \
+	fuzz/fuzz.cc \
+	fuzz/msc_fuzz.cc \
+	fuzz/usbd_fuzz.cc
+
+# TinyUSB stack include
+INC += $(TOP)/src
+
+CFLAGS += $(addprefix -I,$(INC))
+CXXFLAGS += -std=c++17
+
+# LTO makes it difficult to analyze map file for optimizing size purpose
+# We will run this option in ci
+ifeq ($(NO_LTO),1)
+CFLAGS := $(filter-out -flto,$(CFLAGS))
+endif
+
+ifneq ($(LD_FILE),)
+LDFLAGS_LD_FILE ?= -Wl,-T,$(TOP)/$(LD_FILE)
+endif
+
+LDFLAGS += $(CFLAGS) $(LDFLAGS_LD_FILE) -fuse-ld=lld -Wl,-Map=$@.map -Wl,--cref -Wl,-gc-sections
+ifneq ($(SKIP_NANOLIB), 1)
+endif
+
+ASFLAGS += $(CFLAGS)
+
+# Assembly files can be name with upper case .S, convert it to .s
+SRC_S := $(SRC_S:.S=.s)
+
+# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
+# assembly file should be placed first in linking order
+# '_asm' suffix is added to object of assembly file
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_CXX:.cc=_cxx.o))
+
+# Verbose mode
+ifeq ("$(V)","1")
+$(info CFLAGS  $(CFLAGS) ) $(info )
+$(info LDFLAGS $(LDFLAGS)) $(info )
+$(info ASFLAGS $(ASFLAGS)) $(info )
+endif
+
+# ---------------------------------------
+# Rules
+# ---------------------------------------
+
+all: $(BUILD)/$(PROJECT) 
+
+OBJ_DIRS = $(sort $(dir $(OBJ)))
+$(OBJ): | $(OBJ_DIRS)
+$(OBJ_DIRS):
+ifeq ($(CMDEXE),1)
+	@$(MKDIR) $(subst /,\,$@)
+else
+	@$(MKDIR) -p $@
+endif
+
+$(BUILD)/$(PROJECT): $(OBJ)
+	@echo LINK $@
+	@ $(CXX) -o $@  $(LIB_FUZZING_ENGINE) $^ $(LIBS) $(LDFLAGS)
+
+# We set vpath to point to the top of the tree so that the source files
+# can be located. By following this scheme, it allows a single build rule
+# to be used to compile all .c files.
+vpath %.c . $(TOP)
+$(BUILD)/obj/%.o: %.c
+	@echo CC $(notdir $@)
+	@$(CC) $(CFLAGS) -c -MD -o $@ $<
+	
+# All cpp srcs
+vpath %.cc . $(TOP)
+$(BUILD)/obj/%_cxx.o: %.cc
+	@echo CXX $(notdir $@)
+	@$(CXX) $(CFLAGS) $(CXXFLAGS) -c -MD -o $@ $<
+
+# ASM sources lower case .s
+vpath %.s . $(TOP)
+$(BUILD)/obj/%_asm.o: %.s
+	@echo AS $(notdir $@)
+	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
+
+# ASM sources upper case .S
+vpath %.S . $(TOP)
+$(BUILD)/obj/%_asm.o: %.S
+	@echo AS $(notdir $@)
+	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
+
+.PHONY: clean
+clean:
+ifeq ($(CMDEXE),1)
+	rd /S /Q $(subst /,\,$(BUILD))
+else
+	$(RM) -rf $(BUILD)
+endif
+# ---------------- GNU Make End -----------------------
+
+# get depenecies
+.PHONY: get-deps
+get-deps:
+  ifdef DEPS_SUBMODULES
+	git -C $(TOP) submodule update --init $(DEPS_SUBMODULES)
+  endif
+
+size: $(BUILD)/$(PROJECT)
+	-@echo ''
+	@$(SIZE) $<
+	-@echo ''
+
+# linkermap must be install previously at https://github.com/hathach/linkermap
+linkermap: $(BUILD)/$(PROJECT)
+	@linkermap -v $<.map
+
+# Print out the value of a make variable.
+# https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile
+print-%:
+	@echo $* = $($*)
\ No newline at end of file
diff --git a/fuzz/usbd_fuzz.cc b/fuzz/usbd_fuzz.cc
new file mode 100644
index 000000000..45c5fd7ea
--- /dev/null
+++ b/fuzz/usbd_fuzz.cc
@@ -0,0 +1,73 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "fuzz/fuzz_private.h"
+#include "tusb.h"
+// #include "usb_descriptors.h"
+
+#ifndef CFG_FUZZ_MAX_STRING_LEN
+#define CFG_FUZZ_MAX_STRING_LEN 1000
+#endif
+
+extern "C" {
+
+/* TODO: Implement a fuzzed version of this.
+uint8_t const *tud_descriptor_bos_cb(void) {  }
+*/
+
+/* TODO: Implement a fuzzed version of this.
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {}
+*/
+
+/* TODO: Implement a fuzzed version of this.
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {}
+*/
+
+void tud_mount_cb(void) {
+  // NOOP
+}
+
+void tud_umount_cb(void) {
+  // NOOP
+}
+
+void tud_suspend_cb(bool remote_wakeup_en) {
+  (void)remote_wakeup_en;
+  // NOOP
+}
+
+void tud_resume_cb(void) {
+  // NOOP
+}
+
+/* TODO: Implement a fuzzed version of this.
+bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage,
+                                tusb_control_request_t const *request) {}
+*/
+
+/* TODO: Implement a fuzzed version of this.
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {}
+*/
+}

From 92b5f2d2e823b6da019749cf7f4548f78d1ce0cd Mon Sep 17 00:00:00 2001
From: Nathaniel Brough <nathaniel.brough@gmail.com>
Date: Thu, 10 Nov 2022 02:09:58 +0000
Subject: [PATCH 1277/2085] fuzz: Add msc fuzz harness

---
 fuzz/device/msc/CMakeLists.txt         |  29 ++++
 fuzz/device/msc/Makefile               |  12 ++
 fuzz/device/msc/skip.txt               |   1 +
 fuzz/device/msc/src/fuzz.cc            |  62 +++++++
 fuzz/device/msc/src/tusb_config.h      | 114 +++++++++++++
 fuzz/device/msc/src/usb_descriptors.cc | 224 +++++++++++++++++++++++++
 fuzz/msc_fuzz.cc                       | 162 ++++++++++++++++++
 7 files changed, 604 insertions(+)
 create mode 100644 fuzz/device/msc/CMakeLists.txt
 create mode 100644 fuzz/device/msc/Makefile
 create mode 100644 fuzz/device/msc/skip.txt
 create mode 100644 fuzz/device/msc/src/fuzz.cc
 create mode 100644 fuzz/device/msc/src/tusb_config.h
 create mode 100644 fuzz/device/msc/src/usb_descriptors.cc
 create mode 100644 fuzz/msc_fuzz.cc

diff --git a/fuzz/device/msc/CMakeLists.txt b/fuzz/device/msc/CMakeLists.txt
new file mode 100644
index 000000000..fa6e83b7e
--- /dev/null
+++ b/fuzz/device/msc/CMakeLists.txt
@@ -0,0 +1,29 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/fuzz/device/msc/Makefile b/fuzz/device/msc/Makefile
new file mode 100644
index 000000000..76a43923f
--- /dev/null
+++ b/fuzz/device/msc/Makefile
@@ -0,0 +1,12 @@
+include ../../../tools/top.mk
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.c))
+SRC_CXX += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.cc))
+
+include ../../rules.mk
diff --git a/fuzz/device/msc/skip.txt b/fuzz/device/msc/skip.txt
new file mode 100644
index 000000000..d844feae8
--- /dev/null
+++ b/fuzz/device/msc/skip.txt
@@ -0,0 +1 @@
+mcu:SAMD11
\ No newline at end of file
diff --git a/fuzz/device/msc/src/fuzz.cc b/fuzz/device/msc/src/fuzz.cc
new file mode 100644
index 000000000..568900452
--- /dev/null
+++ b/fuzz/device/msc/src/fuzz.cc
@@ -0,0 +1,62 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <cassert>
+#include <fuzzer/FuzzedDataProvider.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "class/cdc/cdc_device.h"
+#include "fuzz/fuzz.h"
+#include "tusb.h"
+#include <cstdint>
+#include <string>
+#include <vector>
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+#define FUZZ_ITERATIONS 500
+
+extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) {
+  FuzzedDataProvider provider(Data, Size);
+  std::vector<uint8_t> callback_data = provider.ConsumeBytes<uint8_t>(
+      provider.ConsumeIntegralInRange<size_t>(0, Size));
+  fuzz_init(callback_data.data(), callback_data.size());
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
+
+  for (int i = 0; i < FUZZ_ITERATIONS; i++) {
+    if (provider.remaining_bytes() == 0) {
+      return 0;
+    }
+    tud_int_handler(provider.ConsumeIntegral<uint8_t>());
+    tud_task(); // tinyusb device task
+  }
+
+  return 0;
+}
+
diff --git a/fuzz/device/msc/src/tusb_config.h b/fuzz/device/msc/src/tusb_config.h
new file mode 100644
index 000000000..ca39c6b0a
--- /dev/null
+++ b/fuzz/device/msc/src/tusb_config.h
@@ -0,0 +1,114 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN    __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC              0
+#define CFG_TUD_MSC              1
+#define CFG_TUD_HID              0
+#define CFG_TUD_MIDI             0
+#define CFG_TUD_VENDOR           0
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// MSC Buffer size of Device Mass storage
+#define CFG_TUD_MSC_EP_BUFSIZE   512
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/fuzz/device/msc/src/usb_descriptors.cc b/fuzz/device/msc/src/usb_descriptors.cc
new file mode 100644
index 000000000..ded401fc9
--- /dev/null
+++ b/fuzz/device/msc/src/usb_descriptors.cc
@@ -0,0 +1,224 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save
+ * device driver after the first plug.
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]         HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n))
+#define USB_PID                                                                \
+  (0x4000 | _PID_MAP(MSC, 0) | _PID_MAP(HID, 1) | _PID_MAP(MIDI, 2) |          \
+   _PID_MAP(VENDOR, 3))
+#define USB_VID 0xCafe
+#define USB_BCD 0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const *tud_descriptor_device_cb(void) {
+  static tusb_desc_device_t const desc_device = {
+      .bLength = sizeof(tusb_desc_device_t),
+      .bDescriptorType = TUSB_DESC_DEVICE,
+      .bcdUSB = USB_BCD,
+
+      // Use Interface Association Descriptor (IAD) for CDC
+      // As required by USB Specs IAD's subclass must be common class (2) and
+      // protocol must be IAD (1)
+      .bDeviceClass = TUSB_CLASS_MISC,
+      .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+      .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+      .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+      .idVendor = USB_VID,
+      .idProduct = USB_PID,
+      .bcdDevice = 0x0100,
+
+      .iManufacturer = 0x01,
+      .iProduct = 0x02,
+      .iSerialNumber = 0x03,
+
+      .bNumConfigurations = 0x01};
+
+  return (uint8_t const *)&desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+enum { ITF_NUM_MSC = 0, ITF_NUM_TOTAL };
+
+#define EPNUM_MSC_OUT 0x05
+#define EPNUM_MSC_IN 0x85
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_MSC_DESC_LEN)
+
+// full speed configuration
+uint8_t const desc_fs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 4, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and
+// other_speed_configuration
+
+// high speed configuration
+uint8_t const desc_hs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 4, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
+};
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change
+// configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength = sizeof(tusb_desc_device_qualifier_t),
+    .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
+    .bcdUSB = USB_BCD,
+
+    .bDeviceClass = TUSB_CLASS_MISC,
+    .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved = 0x00};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete. device_qualifier descriptor describes
+// information about a high-speed capable device that would change if the device
+// were operating at the other speed. If not highspeed capable stall this
+// request.
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const *)&desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete Configuration descriptor in the other speed
+// e.g if high speed then this is for full speed and vice versa
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration
+                                              : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration
+                                              : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] = {
+    (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                  // 1: Manufacturer
+    "TinyUSB Device",           // 2: Product
+    "123456789012",             // 3: Serials, should use chip ID
+    "TinyUSB MSC",              // 4: MSC Interface
+
+};
+
+static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void)langid;
+
+  uint8_t chr_count;
+
+  if (index == 0) {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  } else {
+    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+    if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])))
+      return NULL;
+
+    const char *str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = (uint8_t)strlen(str);
+    if (chr_count > 31)
+      chr_count = 31;
+
+    // Convert ASCII string into UTF-16
+    for (uint8_t i = 0; i < chr_count; i++) {
+      _desc_str[1 + i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/fuzz/msc_fuzz.cc b/fuzz/msc_fuzz.cc
new file mode 100644
index 000000000..e906ca971
--- /dev/null
+++ b/fuzz/msc_fuzz.cc
@@ -0,0 +1,162 @@
+#include "fuzz/fuzz_private.h"
+#include "tusb.h"
+#include <cassert>
+#include <array>
+#include <limits>
+
+#if CFG_TUD_MSC==1
+
+// Whether host does safe eject.
+// tud_msc_get_maxlun_cb returns a uint8_t so the max logical units that are
+// allowed is 255, so we need to keep track of 255 fuzzed logical units.
+static std::array<bool, std::numeric_limits<uint8_t>::max()> ejected = {false};
+
+extern "C" {
+// Invoked when received SCSI_CMD_INQUIRY
+// Application fill vendor id, product id and revision with string up to 8, 16,
+// 4 characters respectively
+void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8],
+                        uint8_t product_id[16], uint8_t product_rev[4]) {
+  (void)lun;
+  assert(_fuzz_data_provider.has_value());
+
+  std::string vid = _fuzz_data_provider->ConsumeBytesAsString(8);
+  std::string pid = _fuzz_data_provider->ConsumeBytesAsString(16);
+  std::string rev = _fuzz_data_provider->ConsumeBytesAsString(4);
+
+  memcpy(vendor_id, vid.c_str(), strlen(vid.c_str()));
+  memcpy(product_id, pid.c_str(), strlen(pid.c_str()));
+  memcpy(product_rev, rev.c_str(), strlen(rev.c_str()));
+}
+
+// Invoked when received Test Unit Ready command.
+// return true allowing host to read/write this LUN e.g SD card inserted
+bool tud_msc_test_unit_ready_cb(uint8_t lun) {
+  // RAM disk is ready until ejected
+  if (ejected[lun]) {
+    // Additional Sense 3A-00 is NOT_FOUND
+    tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3a, 0x00);
+    return false;
+  }
+
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+// Invoked when received SCSI_CMD_READ_CAPACITY_10 and
+// SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size Application update
+// block count and block size
+void tud_msc_capacity_cb(uint8_t lun, uint32_t *block_count,
+                         uint16_t *block_size) {
+  (void)lun;
+  *block_count = _fuzz_data_provider->ConsumeIntegral<uint32_t>();
+  *block_size = _fuzz_data_provider->ConsumeIntegral<uint16_t>();
+}
+
+// Invoked when received Start Stop Unit command
+// - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage
+// - Start = 1 : active mode, if load_eject = 1 : load disk storage
+bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start,
+                           bool load_eject) {
+  (void)power_condition;
+  assert(_fuzz_data_provider.has_value());
+
+  if (load_eject) {
+    if (start) {
+      // load disk storage
+    } else {
+      // unload disk storage
+      ejected[lun] = true;
+    }
+  }
+
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+// Callback invoked when received READ10 command.
+// Copy disk's data to buffer (up to bufsize) and return number of copied bytes.
+int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset,
+                          void *buffer, uint32_t bufsize) {
+  assert(_fuzz_data_provider.has_value());
+  (void)lun;
+  (void)lba;
+  (void)offset;
+
+  std::vector<uint8_t> consumed_buffer = _fuzz_data_provider->ConsumeBytes<uint8_t>(
+      _fuzz_data_provider->ConsumeIntegralInRange<uint32_t>(0, bufsize));
+  memcpy(buffer, consumed_buffer.data(), consumed_buffer.size());
+
+  // Sometimes return an error code;
+  if (_fuzz_data_provider->ConsumeBool()) {
+    return _fuzz_data_provider->ConsumeIntegralInRange(
+        std::numeric_limits<int32_t>::min(), -1);
+  }
+
+  return consumed_buffer.size();
+}
+
+bool tud_msc_is_writable_cb(uint8_t lun) {
+  assert(_fuzz_data_provider.has_value());
+  (void)lun;
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+// Callback invoked when received WRITE10 command.
+// Process data in buffer to disk's storage and return number of written bytes
+int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset,
+                           uint8_t *buffer, uint32_t bufsize) {
+  // Ignore these as they are outputs and don't affect the return value.
+  (void)lun;
+  (void)lba;
+  (void)offset;
+  (void)buffer;
+  assert(_fuzz_data_provider.has_value());
+
+  // -ve error codes -> bufsize.
+  return _fuzz_data_provider->ConsumeIntegralInRange<int32_t>(
+      std::numeric_limits<int32_t>::min(), bufsize);
+}
+
+// Callback invoked when received an SCSI command not in built-in list below
+// - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE
+// - READ10 and WRITE10 has their own callbacks
+int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer,
+                        uint16_t bufsize) {
+  (void)buffer;
+  (void)bufsize;
+  assert(_fuzz_data_provider.has_value());
+
+  switch (scsi_cmd[0]) {
+  case SCSI_CMD_TEST_UNIT_READY:
+    break;
+  case SCSI_CMD_INQUIRY:
+    break;
+  case SCSI_CMD_MODE_SELECT_6:
+    break;
+  case SCSI_CMD_MODE_SENSE_6:
+    break;
+  case SCSI_CMD_START_STOP_UNIT:
+    break;
+  case SCSI_CMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
+    break;
+  case SCSI_CMD_READ_CAPACITY_10:
+    break;
+  case SCSI_CMD_REQUEST_SENSE:
+    break;
+  case SCSI_CMD_READ_FORMAT_CAPACITY:
+    break;
+  case SCSI_CMD_READ_10:
+    break;
+  case SCSI_CMD_WRITE_10:
+    break;
+  default:
+    // Set Sense = Invalid Command Operation
+    tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00);
+    return _fuzz_data_provider->ConsumeIntegralInRange<int32_t>(
+        std::numeric_limits<int32_t>::min(), -1);
+  }
+
+  return 0;
+}
+}
+
+#endif
\ No newline at end of file

From 9cc93e6d4161239f1a99f3e456282d38b9487650 Mon Sep 17 00:00:00 2001
From: Nathaniel Brough <nathaniel.brough@gmail.com>
Date: Thu, 10 Nov 2022 02:40:13 +0000
Subject: [PATCH 1278/2085] .github: Add fuzzer builder

---
 .github/workflows/build_fuzzers.yml | 33 +++++++++++++++++++++++++++++
 fuzz/rules.mk                       |  2 +-
 2 files changed, 34 insertions(+), 1 deletion(-)
 create mode 100644 .github/workflows/build_fuzzers.yml

diff --git a/.github/workflows/build_fuzzers.yml b/.github/workflows/build_fuzzers.yml
new file mode 100644
index 000000000..2a892d59a
--- /dev/null
+++ b/.github/workflows/build_fuzzers.yml
@@ -0,0 +1,33 @@
+name: Build Fuzzer
+
+on:
+  pull_request:
+  push:
+  release:
+    types:
+      - created
+
+jobs:
+  # ---------------------------------------
+  # Build all no-family (orphaned) boards
+  # ---------------------------------------
+  build-board:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        fuzz_harness:
+        - "device/cdc"
+        - "device/msc"
+
+    steps:
+    - name: Setup Python
+      uses: actions/setup-python@v3
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v3
+
+    - name: Fetch deps
+      run: sudo apt update && sudo apt install libc++abi-dev libc++-dev
+    - name: Build Fuzzer
+      run: make CC=clang CXX=clang++ -C fuzz/${{ matrix.fuzz_harness }}
diff --git a/fuzz/rules.mk b/fuzz/rules.mk
index aedc7fe83..ee4d3130b 100644
--- a/fuzz/rules.mk
+++ b/fuzz/rules.mk
@@ -15,7 +15,7 @@ LIBS_GCC ?=  -lm
 LIBS += $(LIBS_GCC)
 
 ifneq ($(BOARD), spresense)
-LIBS += -lc -Wl,-Bstatic -lc++ -lc++abi -Wl,-Bdynamic
+LIBS += -lc -Wl,-Bstatic -lc++ -Wl,-Bdynamic
 endif
 
 # TinyUSB Stack source

From 6492f4a18d55219299832f40835d204fcdccb797 Mon Sep 17 00:00:00 2001
From: Nathaniel Brough <nathaniel.brough@gmail.com>
Date: Wed, 16 Nov 2022 02:24:59 +0000
Subject: [PATCH 1279/2085] feat(fuzz): Adds net class fuzzer

---
 .github/workflows/build_fuzzers.yml    |   6 +-
 fuzz/dcd_fuzz.cc                       |   8 +-
 fuzz/device/cdc/src/fuzz.cc            |  56 +++---
 fuzz/device/net/CMakeLists.txt         |  29 ++++
 fuzz/device/net/Makefile               |  71 ++++++++
 fuzz/device/net/skip.txt               |   1 +
 fuzz/device/net/src/arch/cc.h          |  75 ++++++++
 fuzz/device/net/src/fuzz.cc            |  99 +++++++++++
 fuzz/device/net/src/lwipopts.h         |  71 ++++++++
 fuzz/device/net/src/tusb_config.h      | 122 +++++++++++++
 fuzz/device/net/src/usb_descriptors.cc | 229 +++++++++++++++++++++++++
 fuzz/make.mk                           |   5 +-
 fuzz/net_fuzz.cc                       |  82 +++++++++
 fuzz/rules.mk                          |   1 +
 14 files changed, 824 insertions(+), 31 deletions(-)
 create mode 100644 fuzz/device/net/CMakeLists.txt
 create mode 100644 fuzz/device/net/Makefile
 create mode 100644 fuzz/device/net/skip.txt
 create mode 100644 fuzz/device/net/src/arch/cc.h
 create mode 100644 fuzz/device/net/src/fuzz.cc
 create mode 100644 fuzz/device/net/src/lwipopts.h
 create mode 100644 fuzz/device/net/src/tusb_config.h
 create mode 100644 fuzz/device/net/src/usb_descriptors.cc
 create mode 100644 fuzz/net_fuzz.cc

diff --git a/.github/workflows/build_fuzzers.yml b/.github/workflows/build_fuzzers.yml
index 2a892d59a..fd15d937b 100644
--- a/.github/workflows/build_fuzzers.yml
+++ b/.github/workflows/build_fuzzers.yml
@@ -19,6 +19,7 @@ jobs:
         fuzz_harness:
         - "device/cdc"
         - "device/msc"
+        - "device/net"
 
     steps:
     - name: Setup Python
@@ -28,6 +29,9 @@ jobs:
       uses: actions/checkout@v3
 
     - name: Fetch deps
-      run: sudo apt update && sudo apt install libc++abi-dev libc++-dev
+      run: | 
+       sudo apt update && sudo apt install libc++abi-dev libc++-dev
+       make CC=clang CXX=clang++ -C fuzz/${{ matrix.fuzz_harness }} get-deps
+
     - name: Build Fuzzer
       run: make CC=clang CXX=clang++ -C fuzz/${{ matrix.fuzz_harness }}
diff --git a/fuzz/dcd_fuzz.cc b/fuzz/dcd_fuzz.cc
index 94d504a2c..7153e20f0 100644
--- a/fuzz/dcd_fuzz.cc
+++ b/fuzz/dcd_fuzz.cc
@@ -172,7 +172,13 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer,
     std::copy(temp.begin(), temp.end(), buffer);
   }
   // Ignore output data as it's not useful for fuzzing without a more
-  // complex fuzzed backend.
+  // complex fuzzed backend. But we need to make sure it's not
+  // optimised out.
+  volatile uint8_t *dont_optimise0 = buffer;
+  volatile uint16_t dont_optimise1 = total_bytes;
+  UNUSED(dont_optimise0);
+  UNUSED(dont_optimise1);
+
 
   return _fuzz_data_provider->ConsumeBool();
 }
diff --git a/fuzz/device/cdc/src/fuzz.cc b/fuzz/device/cdc/src/fuzz.cc
index f783125f9..d40483ca6 100644
--- a/fuzz/device/cdc/src/fuzz.cc
+++ b/fuzz/device/cdc/src/fuzz.cc
@@ -142,33 +142,33 @@ void cdc_task(FuzzedDataProvider *provider) {
 
     // TODO: Fuzz interface number
     (void)tud_cdc_n_write(0, buffer.data(), buffer.size());
-    break;
-  }
-  case kCdcNWriteChar:
-    // TODO: Fuzz interface number
-    (void)tud_cdc_n_write_char(0, provider->ConsumeIntegral<char>());
-    break;
-  case kCdcNWriteStr: {
-    std::string str = provider->ConsumeRandomLengthString(kMaxBufferSize);
-    // TODO: Fuzz interface number
-    (void)tud_cdc_n_write_str(0, str.c_str());
-    break;
-  }
-  case kCdcNWriteFlush:
-    // TODO: Fuzz interface number
-    (void)tud_cdc_n_write_flush(0);
-    break;
-  case kCdcNWriteAvailable:
-    // TODO: Fuzz interface number
-    (void)tud_cdc_n_write_available(0);
-    break;
-  case kCdcNWriteClear:
-    // TODO: Fuzz interface number
-    (void)tud_cdc_n_write_clear(0);
-    break;
-  case kMaxValue:
-    // Noop.
-    break;
-  }
+  } break;
+  
+case kCdcNWriteChar:
+  // TODO: Fuzz interface number
+  (void)tud_cdc_n_write_char(0, provider->ConsumeIntegral<char>());
+  break;
+case kCdcNWriteStr: {
+  std::string str = provider->ConsumeRandomLengthString(kMaxBufferSize);
+  // TODO: Fuzz interface number
+  (void)tud_cdc_n_write_str(0, str.c_str());
+  break;
+}
+case kCdcNWriteFlush:
+  // TODO: Fuzz interface number
+  (void)tud_cdc_n_write_flush(0);
+  break;
+case kCdcNWriteAvailable:
+  // TODO: Fuzz interface number
+  (void)tud_cdc_n_write_available(0);
+  break;
+case kCdcNWriteClear:
+  // TODO: Fuzz interface number
+  (void)tud_cdc_n_write_clear(0);
+  break;
+case kMaxValue:
+  // Noop.
+  break;
+}
 }
 }
\ No newline at end of file
diff --git a/fuzz/device/net/CMakeLists.txt b/fuzz/device/net/CMakeLists.txt
new file mode 100644
index 000000000..fa6e83b7e
--- /dev/null
+++ b/fuzz/device/net/CMakeLists.txt
@@ -0,0 +1,29 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/fuzz/device/net/Makefile b/fuzz/device/net/Makefile
new file mode 100644
index 000000000..42601e73e
--- /dev/null
+++ b/fuzz/device/net/Makefile
@@ -0,0 +1,71 @@
+DEPS_SUBMODULES += lib/lwip
+
+include ../../../tools/top.mk
+include ../../make.mk
+
+# suppress warning caused by lwip
+CFLAGS += \
+  -Wno-error=null-dereference \
+  -Wno-error=unused-parameter \
+  -Wno-error=unused-variable
+
+INC += \
+  src \
+  $(TOP)/hw \
+  $(TOP)/lib/lwip/src/include \
+  $(TOP)/lib/lwip/src/include/ipv4 \
+  $(TOP)/lib/lwip/src/include/lwip/apps \
+  $(TOP)/lib/networking
+
+# Example source
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.c))
+SRC_CXX += $(addprefix $(CURRENT_PATH)/, $(wildcard src/*.cc))
+
+# lwip sources
+SRC_C += \
+  lib/lwip/src/core/altcp.c \
+  lib/lwip/src/core/altcp_alloc.c \
+  lib/lwip/src/core/altcp_tcp.c \
+  lib/lwip/src/core/def.c \
+  lib/lwip/src/core/dns.c \
+  lib/lwip/src/core/inet_chksum.c \
+  lib/lwip/src/core/init.c \
+  lib/lwip/src/core/ip.c \
+  lib/lwip/src/core/mem.c \
+  lib/lwip/src/core/memp.c \
+  lib/lwip/src/core/netif.c \
+  lib/lwip/src/core/pbuf.c \
+  lib/lwip/src/core/raw.c \
+  lib/lwip/src/core/stats.c \
+  lib/lwip/src/core/sys.c \
+  lib/lwip/src/core/tcp.c \
+  lib/lwip/src/core/tcp_in.c \
+  lib/lwip/src/core/tcp_out.c \
+  lib/lwip/src/core/timeouts.c \
+  lib/lwip/src/core/udp.c \
+  lib/lwip/src/core/ipv4/autoip.c \
+  lib/lwip/src/core/ipv4/dhcp.c \
+  lib/lwip/src/core/ipv4/etharp.c \
+  lib/lwip/src/core/ipv4/icmp.c \
+  lib/lwip/src/core/ipv4/igmp.c \
+  lib/lwip/src/core/ipv4/ip4.c \
+  lib/lwip/src/core/ipv4/ip4_addr.c \
+  lib/lwip/src/core/ipv4/ip4_frag.c \
+  lib/lwip/src/core/ipv6/dhcp6.c \
+  lib/lwip/src/core/ipv6/ethip6.c \
+  lib/lwip/src/core/ipv6/icmp6.c \
+  lib/lwip/src/core/ipv6/inet6.c \
+  lib/lwip/src/core/ipv6/ip6.c \
+  lib/lwip/src/core/ipv6/ip6_addr.c \
+  lib/lwip/src/core/ipv6/ip6_frag.c \
+  lib/lwip/src/core/ipv6/mld6.c \
+  lib/lwip/src/core/ipv6/nd6.c \
+  lib/lwip/src/netif/ethernet.c \
+  lib/lwip/src/netif/slipif.c \
+  lib/lwip/src/apps/http/httpd.c \
+  lib/lwip/src/apps/http/fs.c \
+  lib/networking/dhserver.c \
+  lib/networking/dnserver.c \
+  lib/networking/rndis_reports.c
+
+include ../../rules.mk
diff --git a/fuzz/device/net/skip.txt b/fuzz/device/net/skip.txt
new file mode 100644
index 000000000..d844feae8
--- /dev/null
+++ b/fuzz/device/net/skip.txt
@@ -0,0 +1 @@
+mcu:SAMD11
\ No newline at end of file
diff --git a/fuzz/device/net/src/arch/cc.h b/fuzz/device/net/src/arch/cc.h
new file mode 100644
index 000000000..56a0cacf7
--- /dev/null
+++ b/fuzz/device/net/src/arch/cc.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __CC_H__
+#define __CC_H__
+
+//#include "cpu.h"
+
+typedef int sys_prot_t;
+
+
+
+/* define compiler specific symbols */
+#if defined (__ICCARM__)
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT 
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+#define PACK_STRUCT_USE_INCLUDES
+
+#elif defined (__CC_ARM)
+
+#define PACK_STRUCT_BEGIN __packed
+#define PACK_STRUCT_STRUCT 
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#elif defined (__GNUC__)
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#elif defined (__TASKING__)
+
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#endif
+
+#define LWIP_PLATFORM_ASSERT(x) do { if(!(x)) while(1); } while(0)
+
+#endif /* __CC_H__ */
diff --git a/fuzz/device/net/src/fuzz.cc b/fuzz/device/net/src/fuzz.cc
new file mode 100644
index 000000000..1013cf7f7
--- /dev/null
+++ b/fuzz/device/net/src/fuzz.cc
@@ -0,0 +1,99 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <cassert>
+#include <fuzzer/FuzzedDataProvider.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "class/cdc/cdc_device.h"
+#include "class/net/net_device.h"
+#include "fuzz/fuzz.h"
+#include "tusb.h"
+#include <cstdint>
+#include <string>
+#include <vector>
+
+extern "C" {
+
+#define FUZZ_ITERATIONS 500
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+void net_task(FuzzedDataProvider *provider);
+
+extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) {
+  FuzzedDataProvider provider(Data, Size);
+  std::vector<uint8_t> callback_data = provider.ConsumeBytes<uint8_t>(
+      provider.ConsumeIntegralInRange<size_t>(0, Size));
+  fuzz_init(callback_data.data(), callback_data.size());
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
+
+  for (int i = 0; i < FUZZ_ITERATIONS; i++) {
+    if (provider.remaining_bytes() == 0) {
+      return 0;
+    }
+    tud_int_handler(provider.ConsumeIntegral<uint8_t>());
+    tud_task(); // tinyusb device task
+    net_task(&provider);
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// USB CDC
+//--------------------------------------------------------------------+
+enum NetApiFuncs {
+  kNetworkRecvRenew,
+  kNetworkCanXmit,
+  kNetworkXmit,
+  kMaxValue,
+};
+
+void net_task(FuzzedDataProvider *provider) {
+
+  assert(provider != NULL);
+  switch (provider->ConsumeEnum<NetApiFuncs>()) {
+  
+  case kNetworkRecvRenew:
+    tud_network_recv_renew();
+    break;
+  case kNetworkCanXmit:
+ (void)tud_network_can_xmit(provider->ConsumeIntegral<uint16_t>());
+  case kNetworkXmit:
+    // TODO: Actuall pass real values here later.
+    tud_network_xmit(NULL, 0);
+
+  case kMaxValue:
+    // Noop.
+    break;
+  }
+}
+}
\ No newline at end of file
diff --git a/fuzz/device/net/src/lwipopts.h b/fuzz/device/net/src/lwipopts.h
new file mode 100644
index 000000000..a215017c7
--- /dev/null
+++ b/fuzz/device/net/src/lwipopts.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Simon Goldschmidt
+ *
+ */
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+/* Prevent having to link sys_arch.c (we don't test the API layers in unit tests) */
+#define NO_SYS                          1
+#define MEM_ALIGNMENT                   4
+#define LWIP_RAW                        0
+#define LWIP_NETCONN                    0
+#define LWIP_SOCKET                     0
+#define LWIP_DHCP                       0
+#define LWIP_ICMP                       1
+#define LWIP_UDP                        1
+#define LWIP_TCP                        1
+#define LWIP_IPV4                       1
+#define LWIP_IPV6                       0
+#define ETH_PAD_SIZE                    0
+#define LWIP_IP_ACCEPT_UDP_PORT(p)      ((p) == PP_NTOHS(67))
+
+#define TCP_MSS                         (1500 /*mtu*/ - 20 /*iphdr*/ - 20 /*tcphhr*/)
+#define TCP_SND_BUF                     (2 * TCP_MSS)
+#define TCP_WND                         (TCP_MSS)
+
+#define ETHARP_SUPPORT_STATIC_ENTRIES   1
+
+#define LWIP_HTTPD_CGI                  0
+#define LWIP_HTTPD_SSI                  0
+#define LWIP_HTTPD_SSI_INCLUDE_TAG      0
+
+#define LWIP_SINGLE_NETIF               1
+
+#define PBUF_POOL_SIZE                  2
+
+#define HTTPD_USE_CUSTOM_FSDATA         0
+
+#define LWIP_MULTICAST_PING             1
+#define LWIP_BROADCAST_PING             1
+#define LWIP_IPV6_MLD                   0
+#define LWIP_IPV6_SEND_ROUTER_SOLICIT   0
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/fuzz/device/net/src/tusb_config.h b/fuzz/device/net/src/tusb_config.h
new file mode 100644
index 000000000..6ad859337
--- /dev/null
+++ b/fuzz/device/net/src/tusb_config.h
@@ -0,0 +1,122 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN    __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC              1
+#define CFG_TUD_MSC              0
+#define CFG_TUD_HID              0
+#define CFG_TUD_MIDI             0
+#define CFG_TUD_VENDOR           0
+
+// Network class has 2 drivers: ECM/RNDIS and NCM.
+// Only one of the drivers can be enabled
+#define CFG_TUD_ECM_RNDIS     1
+#define CFG_TUD_NCM           (1-CFG_TUD_ECM_RNDIS)
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#define CFG_TUD_CDC_TX_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// CDC Endpoint transfer buffer size, more is faster
+#define CFG_TUD_CDC_EP_BUFSIZE   (TUD_OPT_HIGH_SPEED ? 512 : 64)
+
+// MSC Buffer size of Device Mass storage
+#define CFG_TUD_MSC_EP_BUFSIZE   512
+
+
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/fuzz/device/net/src/usb_descriptors.cc b/fuzz/device/net/src/usb_descriptors.cc
new file mode 100644
index 000000000..c600bd801
--- /dev/null
+++ b/fuzz/device/net/src/usb_descriptors.cc
@@ -0,0 +1,229 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save
+ * device driver after the first plug.
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]         HID | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n))
+#define USB_PID                                                                \
+  (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(HID, 2) | _PID_MAP(MIDI, 3) |          \
+   _PID_MAP(VENDOR, 4))
+
+#define USB_VID 0xCafe
+#define USB_BCD 0x0200
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const *tud_descriptor_device_cb(void) {
+  static tusb_desc_device_t const desc_device = {
+      .bLength = sizeof(tusb_desc_device_t),
+      .bDescriptorType = TUSB_DESC_DEVICE,
+      .bcdUSB = USB_BCD,
+
+      // Use Interface Association Descriptor (IAD) for CDC
+      // As required by USB Specs IAD's subclass must be common class (2) and
+      // protocol must be IAD (1)
+      .bDeviceClass = TUSB_CLASS_MISC,
+      .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+      .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+      .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+
+      .idVendor = USB_VID,
+      .idProduct = USB_PID,
+      .bcdDevice = 0x0100,
+
+      .iManufacturer = 0x01,
+      .iProduct = 0x02,
+      .iSerialNumber = 0x03,
+
+      .bNumConfigurations = 0x01};
+
+  return (uint8_t const *)&desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+
+enum { ITF_NUM_CDC = 0, ITF_NUM_CDC_DATA, ITF_NUM_TOTAL };
+
+#define EPNUM_CDC_NOTIF 0x81
+#define EPNUM_CDC_OUT 0x02
+#define EPNUM_CDC_IN 0x82
+
+#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
+
+// full speed configuration
+uint8_t const desc_fs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP notification address and size, EP data
+    // address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT,
+                       EPNUM_CDC_IN, 64),
+};
+
+#if TUD_OPT_HIGH_SPEED
+// Per USB specs: high speed capable device must report device_qualifier and
+// other_speed_configuration
+
+// high speed configuration
+uint8_t const desc_hs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute,
+    // power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP notification address and size, EP data
+    // address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT,
+                       EPNUM_CDC_IN, 512),
+};
+
+// other speed configuration
+uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
+
+// device qualifier is mostly similar to device descriptor since we don't change
+// configuration based on speed
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength = sizeof(tusb_desc_device_qualifier_t),
+    .bDescriptorType = TUSB_DESC_DEVICE_QUALIFIER,
+    .bcdUSB = USB_BCD,
+
+    .bDeviceClass = TUSB_CLASS_MISC,
+    .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol = MISC_PROTOCOL_IAD,
+
+    .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved = 0x00};
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete. device_qualifier descriptor describes
+// information about a high-speed capable device that would change if the device
+// were operating at the other speed. If not highspeed capable stall this
+// request.
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const *)&desc_device_qualifier;
+}
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete Configuration descriptor in the other speed
+// e.g if high speed then this is for full speed and vice versa
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+  // if link speed is high return fullspeed config, and vice versa
+  // Note: the descriptor type is OHER_SPEED_CONFIG instead of CONFIG
+  memcpy(desc_other_speed_config,
+         (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration
+                                              : desc_hs_configuration,
+         CONFIG_TOTAL_LEN);
+
+  desc_other_speed_config[1] = TUSB_DESC_OTHER_SPEED_CONFIG;
+
+  return desc_other_speed_config;
+}
+
+#endif // highspeed
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
+  (void)index; // for multiple configurations
+
+#if TUD_OPT_HIGH_SPEED
+  // Although we are highspeed, host may be fullspeed.
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration
+                                              : desc_fs_configuration;
+#else
+  return desc_fs_configuration;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const *string_desc_arr[] = {
+    (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409)
+    "TinyUSB",                  // 1: Manufacturer
+    "TinyUSB Device",           // 2: Product
+    "123456789012",             // 3: Serials, should use chip ID
+    "TinyUSB CDC",              // 4: CDC Interface
+};
+
+static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long
+// enough for transfer to complete
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void)langid;
+
+  uint8_t chr_count;
+
+  if (index == 0) {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  } else {
+    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+
+    if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])))
+      return NULL;
+
+    const char *str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = (uint8_t)strlen(str);
+    if (chr_count > 31)
+      chr_count = 31;
+
+    // Convert ASCII string into UTF-16
+    for (uint8_t i = 0; i < chr_count; i++) {
+      _desc_str[1 + i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t)((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/fuzz/make.mk b/fuzz/make.mk
index 0921fc8f3..299d2c843 100644
--- a/fuzz/make.mk
+++ b/fuzz/make.mk
@@ -43,6 +43,8 @@ INC   += $(TOP)/$(FAMILY_PATH)
 CFLAGS += \
   -ggdb \
   -fsanitize=fuzzer \
+  -fsanitize=address \
+  -fsanitize=undefined \
   -fdata-sections \
   -ffunction-sections \
   -fno-strict-aliasing \
@@ -66,7 +68,8 @@ CFLAGS += \
   -Wnull-dereference \
   -Wuninitialized \
   -Wunused \
-  -Wredundant-decls
+  -Wredundant-decls \
+  -O1
 
 CFLAGS += \
   -DOPT_MCU_FUZZ=1 \
diff --git a/fuzz/net_fuzz.cc b/fuzz/net_fuzz.cc
new file mode 100644
index 000000000..8467d6d8e
--- /dev/null
+++ b/fuzz/net_fuzz.cc
@@ -0,0 +1,82 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 Nathaniel Brough
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb_config.h"
+#if defined(CFG_TUD_ECM_RNDIS) || defined(CFG_TUD_NCM)
+
+#include "class/net/net_device.h"
+#include "fuzz_private.h"
+#include <cassert>
+#include <cstdint>
+#include <vector>
+#include "lwip/sys.h"
+
+extern "C" {
+bool tud_network_recv_cb(const uint8_t *src, uint16_t size) {
+  assert(_fuzz_data_provider.has_value());
+  (void)src;
+  (void)size;
+  return _fuzz_data_provider->ConsumeBool();
+}
+
+// client must provide this: copy from network stack packet pointer to dst
+uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg) {
+  (void)ref;
+  (void)arg;
+
+  assert(_fuzz_data_provider.has_value());
+
+  uint16_t size = _fuzz_data_provider->ConsumeIntegral<uint16_t>();
+  std::vector<uint8_t> temp = _fuzz_data_provider->ConsumeBytes<uint8_t>(size);
+  memcpy(dst, temp.data(), temp.size());
+  return size;
+}
+
+/* lwip has provision for using a mutex, when applicable */
+sys_prot_t sys_arch_protect(void) { return 0; }
+void sys_arch_unprotect(sys_prot_t pval) { (void)pval; }
+
+//------------- ECM/RNDIS -------------//
+
+// client must provide this: initialize any network state back to the beginning
+void tud_network_init_cb(void) {
+  // NoOp.
+}
+
+// client must provide this: 48-bit MAC address
+// TODO removed later since it is not part of tinyusb stack
+const uint8_t tud_network_mac_address[6] = {0};
+
+//------------- NCM -------------//
+
+// callback to client providing optional indication of internal state of network
+// driver
+void tud_network_link_state_cb(bool state) {
+  (void)state;
+  // NoOp.
+}
+}
+
+#endif
\ No newline at end of file
diff --git a/fuzz/rules.mk b/fuzz/rules.mk
index ee4d3130b..1d65adbb7 100644
--- a/fuzz/rules.mk
+++ b/fuzz/rules.mk
@@ -43,6 +43,7 @@ SRC_CXX += \
 	fuzz/dcd_fuzz.cc \
 	fuzz/fuzz.cc \
 	fuzz/msc_fuzz.cc \
+	fuzz/net_fuzz.cc \
 	fuzz/usbd_fuzz.cc
 
 # TinyUSB stack include

From 19400c8556ce4bf5e40653d0c87a9f07db0870a3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 10:30:22 +0700
Subject: [PATCH 1280/2085] fix typo, add -Wno-error=unreachable-code  for fuzz
 due to latest cdc changes

---
 fuzz/device/net/src/fuzz.cc | 4 ++--
 fuzz/make.mk                | 1 +
 src/class/cdc/cdc_device.c  | 1 +
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/fuzz/device/net/src/fuzz.cc b/fuzz/device/net/src/fuzz.cc
index 1013cf7f7..ea4943665 100644
--- a/fuzz/device/net/src/fuzz.cc
+++ b/fuzz/device/net/src/fuzz.cc
@@ -88,7 +88,7 @@ void net_task(FuzzedDataProvider *provider) {
   case kNetworkCanXmit:
  (void)tud_network_can_xmit(provider->ConsumeIntegral<uint16_t>());
   case kNetworkXmit:
-    // TODO: Actuall pass real values here later.
+    // TODO: Actually pass real values here later.
     tud_network_xmit(NULL, 0);
 
   case kMaxValue:
@@ -96,4 +96,4 @@ void net_task(FuzzedDataProvider *provider) {
     break;
   }
 }
-}
\ No newline at end of file
+}
diff --git a/fuzz/make.mk b/fuzz/make.mk
index 299d2c843..796ddc443 100644
--- a/fuzz/make.mk
+++ b/fuzz/make.mk
@@ -72,6 +72,7 @@ CFLAGS += \
   -O1
 
 CFLAGS += \
+	-Wno-error=unreachable-code \
   -DOPT_MCU_FUZZ=1 \
   -DCFG_TUSB_MCU=OPT_MCU_FUZZ 
 
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 77c73030a..7b1e08d5d 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -171,6 +171,7 @@ uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
   uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) bufsize);
 
   // flush if queue more than packet size
+  // may need to suppress -Wunreachable-code since most of the time CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE
   if ( (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE) || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) )
   {
     tud_cdc_n_write_flush(itf);

From 56f846cf74961eecd00242276dd566e1b6134e10 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 10:39:54 +0700
Subject: [PATCH 1281/2085] move fuzz into test/fuzz

---
 fuzz/device/cdc/skip.txt                              |  1 -
 fuzz/device/msc/skip.txt                              |  1 -
 fuzz/device/net/skip.txt                              |  1 -
 {fuzz => test/fuzz}/dcd_fuzz.cc                       |  0
 {fuzz => test/fuzz}/device/cdc/CMakeLists.txt         |  0
 {fuzz => test/fuzz}/device/cdc/Makefile               |  2 +-
 {fuzz => test/fuzz}/device/cdc/src/fuzz.cc            |  0
 {fuzz => test/fuzz}/device/cdc/src/tusb_config.h      |  0
 {fuzz => test/fuzz}/device/cdc/src/usb_descriptors.cc |  0
 {fuzz => test/fuzz}/device/msc/CMakeLists.txt         |  0
 {fuzz => test/fuzz}/device/msc/Makefile               |  2 +-
 {fuzz => test/fuzz}/device/msc/src/fuzz.cc            |  0
 {fuzz => test/fuzz}/device/msc/src/tusb_config.h      |  0
 {fuzz => test/fuzz}/device/msc/src/usb_descriptors.cc |  0
 {fuzz => test/fuzz}/device/net/CMakeLists.txt         |  0
 {fuzz => test/fuzz}/device/net/Makefile               |  2 +-
 {fuzz => test/fuzz}/device/net/src/arch/cc.h          |  0
 {fuzz => test/fuzz}/device/net/src/fuzz.cc            |  0
 {fuzz => test/fuzz}/device/net/src/lwipopts.h         |  0
 {fuzz => test/fuzz}/device/net/src/tusb_config.h      |  0
 {fuzz => test/fuzz}/device/net/src/usb_descriptors.cc |  0
 {fuzz => test/fuzz}/dicts/cdc.dict                    |  0
 {fuzz => test/fuzz}/fuzz.cc                           |  0
 {fuzz => test/fuzz}/fuzz.h                            |  0
 {fuzz => test/fuzz}/fuzz_private.h                    |  0
 {fuzz => test/fuzz}/make.mk                           |  2 +-
 {fuzz => test/fuzz}/msc_fuzz.cc                       |  0
 {fuzz => test/fuzz}/net_fuzz.cc                       |  0
 {fuzz => test/fuzz}/rules.mk                          | 10 +++++-----
 {fuzz => test/fuzz}/usbd_fuzz.cc                      |  0
 30 files changed, 9 insertions(+), 12 deletions(-)
 delete mode 100644 fuzz/device/cdc/skip.txt
 delete mode 100644 fuzz/device/msc/skip.txt
 delete mode 100644 fuzz/device/net/skip.txt
 rename {fuzz => test/fuzz}/dcd_fuzz.cc (100%)
 rename {fuzz => test/fuzz}/device/cdc/CMakeLists.txt (100%)
 rename {fuzz => test/fuzz}/device/cdc/Makefile (86%)
 rename {fuzz => test/fuzz}/device/cdc/src/fuzz.cc (100%)
 rename {fuzz => test/fuzz}/device/cdc/src/tusb_config.h (100%)
 rename {fuzz => test/fuzz}/device/cdc/src/usb_descriptors.cc (100%)
 rename {fuzz => test/fuzz}/device/msc/CMakeLists.txt (100%)
 rename {fuzz => test/fuzz}/device/msc/Makefile (86%)
 rename {fuzz => test/fuzz}/device/msc/src/fuzz.cc (100%)
 rename {fuzz => test/fuzz}/device/msc/src/tusb_config.h (100%)
 rename {fuzz => test/fuzz}/device/msc/src/usb_descriptors.cc (100%)
 rename {fuzz => test/fuzz}/device/net/CMakeLists.txt (100%)
 rename {fuzz => test/fuzz}/device/net/Makefile (98%)
 rename {fuzz => test/fuzz}/device/net/src/arch/cc.h (100%)
 rename {fuzz => test/fuzz}/device/net/src/fuzz.cc (100%)
 rename {fuzz => test/fuzz}/device/net/src/lwipopts.h (100%)
 rename {fuzz => test/fuzz}/device/net/src/tusb_config.h (100%)
 rename {fuzz => test/fuzz}/device/net/src/usb_descriptors.cc (100%)
 rename {fuzz => test/fuzz}/dicts/cdc.dict (100%)
 rename {fuzz => test/fuzz}/fuzz.cc (100%)
 rename {fuzz => test/fuzz}/fuzz.h (100%)
 rename {fuzz => test/fuzz}/fuzz_private.h (100%)
 rename {fuzz => test/fuzz}/make.mk (98%)
 rename {fuzz => test/fuzz}/msc_fuzz.cc (100%)
 rename {fuzz => test/fuzz}/net_fuzz.cc (100%)
 rename {fuzz => test/fuzz}/rules.mk (96%)
 rename {fuzz => test/fuzz}/usbd_fuzz.cc (100%)

diff --git a/fuzz/device/cdc/skip.txt b/fuzz/device/cdc/skip.txt
deleted file mode 100644
index d844feae8..000000000
--- a/fuzz/device/cdc/skip.txt
+++ /dev/null
@@ -1 +0,0 @@
-mcu:SAMD11
\ No newline at end of file
diff --git a/fuzz/device/msc/skip.txt b/fuzz/device/msc/skip.txt
deleted file mode 100644
index d844feae8..000000000
--- a/fuzz/device/msc/skip.txt
+++ /dev/null
@@ -1 +0,0 @@
-mcu:SAMD11
\ No newline at end of file
diff --git a/fuzz/device/net/skip.txt b/fuzz/device/net/skip.txt
deleted file mode 100644
index d844feae8..000000000
--- a/fuzz/device/net/skip.txt
+++ /dev/null
@@ -1 +0,0 @@
-mcu:SAMD11
\ No newline at end of file
diff --git a/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc
similarity index 100%
rename from fuzz/dcd_fuzz.cc
rename to test/fuzz/dcd_fuzz.cc
diff --git a/fuzz/device/cdc/CMakeLists.txt b/test/fuzz/device/cdc/CMakeLists.txt
similarity index 100%
rename from fuzz/device/cdc/CMakeLists.txt
rename to test/fuzz/device/cdc/CMakeLists.txt
diff --git a/fuzz/device/cdc/Makefile b/test/fuzz/device/cdc/Makefile
similarity index 86%
rename from fuzz/device/cdc/Makefile
rename to test/fuzz/device/cdc/Makefile
index 76a43923f..ee51936b5 100644
--- a/fuzz/device/cdc/Makefile
+++ b/test/fuzz/device/cdc/Makefile
@@ -1,4 +1,4 @@
-include ../../../tools/top.mk
+include ../../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/fuzz/device/cdc/src/fuzz.cc b/test/fuzz/device/cdc/src/fuzz.cc
similarity index 100%
rename from fuzz/device/cdc/src/fuzz.cc
rename to test/fuzz/device/cdc/src/fuzz.cc
diff --git a/fuzz/device/cdc/src/tusb_config.h b/test/fuzz/device/cdc/src/tusb_config.h
similarity index 100%
rename from fuzz/device/cdc/src/tusb_config.h
rename to test/fuzz/device/cdc/src/tusb_config.h
diff --git a/fuzz/device/cdc/src/usb_descriptors.cc b/test/fuzz/device/cdc/src/usb_descriptors.cc
similarity index 100%
rename from fuzz/device/cdc/src/usb_descriptors.cc
rename to test/fuzz/device/cdc/src/usb_descriptors.cc
diff --git a/fuzz/device/msc/CMakeLists.txt b/test/fuzz/device/msc/CMakeLists.txt
similarity index 100%
rename from fuzz/device/msc/CMakeLists.txt
rename to test/fuzz/device/msc/CMakeLists.txt
diff --git a/fuzz/device/msc/Makefile b/test/fuzz/device/msc/Makefile
similarity index 86%
rename from fuzz/device/msc/Makefile
rename to test/fuzz/device/msc/Makefile
index 76a43923f..ee51936b5 100644
--- a/fuzz/device/msc/Makefile
+++ b/test/fuzz/device/msc/Makefile
@@ -1,4 +1,4 @@
-include ../../../tools/top.mk
+include ../../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/fuzz/device/msc/src/fuzz.cc b/test/fuzz/device/msc/src/fuzz.cc
similarity index 100%
rename from fuzz/device/msc/src/fuzz.cc
rename to test/fuzz/device/msc/src/fuzz.cc
diff --git a/fuzz/device/msc/src/tusb_config.h b/test/fuzz/device/msc/src/tusb_config.h
similarity index 100%
rename from fuzz/device/msc/src/tusb_config.h
rename to test/fuzz/device/msc/src/tusb_config.h
diff --git a/fuzz/device/msc/src/usb_descriptors.cc b/test/fuzz/device/msc/src/usb_descriptors.cc
similarity index 100%
rename from fuzz/device/msc/src/usb_descriptors.cc
rename to test/fuzz/device/msc/src/usb_descriptors.cc
diff --git a/fuzz/device/net/CMakeLists.txt b/test/fuzz/device/net/CMakeLists.txt
similarity index 100%
rename from fuzz/device/net/CMakeLists.txt
rename to test/fuzz/device/net/CMakeLists.txt
diff --git a/fuzz/device/net/Makefile b/test/fuzz/device/net/Makefile
similarity index 98%
rename from fuzz/device/net/Makefile
rename to test/fuzz/device/net/Makefile
index 42601e73e..22241fcdc 100644
--- a/fuzz/device/net/Makefile
+++ b/test/fuzz/device/net/Makefile
@@ -1,6 +1,6 @@
 DEPS_SUBMODULES += lib/lwip
 
-include ../../../tools/top.mk
+include ../../../../tools/top.mk
 include ../../make.mk
 
 # suppress warning caused by lwip
diff --git a/fuzz/device/net/src/arch/cc.h b/test/fuzz/device/net/src/arch/cc.h
similarity index 100%
rename from fuzz/device/net/src/arch/cc.h
rename to test/fuzz/device/net/src/arch/cc.h
diff --git a/fuzz/device/net/src/fuzz.cc b/test/fuzz/device/net/src/fuzz.cc
similarity index 100%
rename from fuzz/device/net/src/fuzz.cc
rename to test/fuzz/device/net/src/fuzz.cc
diff --git a/fuzz/device/net/src/lwipopts.h b/test/fuzz/device/net/src/lwipopts.h
similarity index 100%
rename from fuzz/device/net/src/lwipopts.h
rename to test/fuzz/device/net/src/lwipopts.h
diff --git a/fuzz/device/net/src/tusb_config.h b/test/fuzz/device/net/src/tusb_config.h
similarity index 100%
rename from fuzz/device/net/src/tusb_config.h
rename to test/fuzz/device/net/src/tusb_config.h
diff --git a/fuzz/device/net/src/usb_descriptors.cc b/test/fuzz/device/net/src/usb_descriptors.cc
similarity index 100%
rename from fuzz/device/net/src/usb_descriptors.cc
rename to test/fuzz/device/net/src/usb_descriptors.cc
diff --git a/fuzz/dicts/cdc.dict b/test/fuzz/dicts/cdc.dict
similarity index 100%
rename from fuzz/dicts/cdc.dict
rename to test/fuzz/dicts/cdc.dict
diff --git a/fuzz/fuzz.cc b/test/fuzz/fuzz.cc
similarity index 100%
rename from fuzz/fuzz.cc
rename to test/fuzz/fuzz.cc
diff --git a/fuzz/fuzz.h b/test/fuzz/fuzz.h
similarity index 100%
rename from fuzz/fuzz.h
rename to test/fuzz/fuzz.h
diff --git a/fuzz/fuzz_private.h b/test/fuzz/fuzz_private.h
similarity index 100%
rename from fuzz/fuzz_private.h
rename to test/fuzz/fuzz_private.h
diff --git a/fuzz/make.mk b/test/fuzz/make.mk
similarity index 98%
rename from fuzz/make.mk
rename to test/fuzz/make.mk
index 796ddc443..3da79e8ff 100644
--- a/fuzz/make.mk
+++ b/test/fuzz/make.mk
@@ -37,7 +37,7 @@ endif
 #-------------- Source files and compiler flags --------------
 
 
-INC   += $(TOP)/$(FAMILY_PATH)
+INC += $(TOP)/test
 
 # Compiler Flags
 CFLAGS += \
diff --git a/fuzz/msc_fuzz.cc b/test/fuzz/msc_fuzz.cc
similarity index 100%
rename from fuzz/msc_fuzz.cc
rename to test/fuzz/msc_fuzz.cc
diff --git a/fuzz/net_fuzz.cc b/test/fuzz/net_fuzz.cc
similarity index 100%
rename from fuzz/net_fuzz.cc
rename to test/fuzz/net_fuzz.cc
diff --git a/fuzz/rules.mk b/test/fuzz/rules.mk
similarity index 96%
rename from fuzz/rules.mk
rename to test/fuzz/rules.mk
index 1d65adbb7..d9c2a1a77 100644
--- a/fuzz/rules.mk
+++ b/test/fuzz/rules.mk
@@ -40,11 +40,11 @@ SRC_C += \
 
 # Fuzzers are c++
 SRC_CXX += \
-	fuzz/dcd_fuzz.cc \
-	fuzz/fuzz.cc \
-	fuzz/msc_fuzz.cc \
-	fuzz/net_fuzz.cc \
-	fuzz/usbd_fuzz.cc
+	test/fuzz/dcd_fuzz.cc \
+	test/fuzz/fuzz.cc \
+	test/fuzz/msc_fuzz.cc \
+	test/fuzz/net_fuzz.cc \
+	test/fuzz/usbd_fuzz.cc
 
 # TinyUSB stack include
 INC += $(TOP)/src
diff --git a/fuzz/usbd_fuzz.cc b/test/fuzz/usbd_fuzz.cc
similarity index 100%
rename from fuzz/usbd_fuzz.cc
rename to test/fuzz/usbd_fuzz.cc

From 86a3315bcf981642b05c9d8388647cbe90a21251 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 10:42:29 +0700
Subject: [PATCH 1282/2085] update fuzzer ci

---
 .github/workflows/build_fuzzers.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build_fuzzers.yml b/.github/workflows/build_fuzzers.yml
index fd15d937b..efa4cc9c0 100644
--- a/.github/workflows/build_fuzzers.yml
+++ b/.github/workflows/build_fuzzers.yml
@@ -31,7 +31,7 @@ jobs:
     - name: Fetch deps
       run: | 
        sudo apt update && sudo apt install libc++abi-dev libc++-dev
-       make CC=clang CXX=clang++ -C fuzz/${{ matrix.fuzz_harness }} get-deps
+       make CC=clang CXX=clang++ -C test/fuzz/${{ matrix.fuzz_harness }} get-deps
 
     - name: Build Fuzzer
-      run: make CC=clang CXX=clang++ -C fuzz/${{ matrix.fuzz_harness }}
+      run: make CC=clang CXX=clang++ -C test/fuzz/${{ matrix.fuzz_harness }}

From bf8f4f95211c286d1ff1def3f140e1e304e76b4d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 11:31:39 +0700
Subject: [PATCH 1283/2085] move build Fuzzer into pre-commit

---
 .github/workflows/build_fuzzers.yml | 37 -----------------------------
 .github/workflows/pre-commit.yml    | 19 ++++++++++++++-
 test/fuzz/make.mk                   |  6 ++---
 3 files changed, 21 insertions(+), 41 deletions(-)
 delete mode 100644 .github/workflows/build_fuzzers.yml

diff --git a/.github/workflows/build_fuzzers.yml b/.github/workflows/build_fuzzers.yml
deleted file mode 100644
index efa4cc9c0..000000000
--- a/.github/workflows/build_fuzzers.yml
+++ /dev/null
@@ -1,37 +0,0 @@
-name: Build Fuzzer
-
-on:
-  pull_request:
-  push:
-  release:
-    types:
-      - created
-
-jobs:
-  # ---------------------------------------
-  # Build all no-family (orphaned) boards
-  # ---------------------------------------
-  build-board:
-    runs-on: ubuntu-latest
-    strategy:
-      fail-fast: false
-      matrix:
-        fuzz_harness:
-        - "device/cdc"
-        - "device/msc"
-        - "device/net"
-
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v3
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Fetch deps
-      run: | 
-       sudo apt update && sudo apt install libc++abi-dev libc++-dev
-       make CC=clang CXX=clang++ -C test/fuzz/${{ matrix.fuzz_harness }} get-deps
-
-    - name: Build Fuzzer
-      run: make CC=clang CXX=clang++ -C test/fuzz/${{ matrix.fuzz_harness }}
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index 96a59069b..ff52606e3 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -34,4 +34,21 @@ jobs:
         # Install Ceedling
         gem install ceedling
         cd test/unit-test
-        ceedling test:all
\ No newline at end of file
+        ceedling test:all
+
+    - name: Fetch deps
+      run: |
+        sudo apt update && sudo apt install libc++abi-dev libc++-dev
+        fuzz_harness=$(ls -d test/fuzz/device/*/ test/fuzz/host/*/)
+        for h in $fuzz_harness
+        do
+          make $h get-deps
+        done
+
+    - name: Build Fuzzer
+      run: |
+        fuzz_harness=$(ls -d test/fuzz/device/*/ test/fuzz/host/*/)
+        for h in $fuzz_harness
+        do
+          make $h all
+        done
diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk
index 3da79e8ff..03254112f 100644
--- a/test/fuzz/make.mk
+++ b/test/fuzz/make.mk
@@ -16,9 +16,9 @@ __check_defined = \
 
 #-------------- Fuzz harness compiler  ------------
 
-CC ?=  clang
-CXX ?= clang++
-GDB ?= gdb
+CC = clang
+CXX = clang++
+GDB = gdb
 OBJCOPY = objcopy
 SIZE = size
 MKDIR = mkdir

From ffd008dc75d1a04b9a0664b339342fb494356f46 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 11:36:19 +0700
Subject: [PATCH 1284/2085] update build fuzzer

---
 .github/workflows/pre-commit.yml | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index ff52606e3..29a412bcf 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -38,8 +38,7 @@ jobs:
 
     - name: Fetch deps
       run: |
-        sudo apt update && sudo apt install libc++abi-dev libc++-dev
-        fuzz_harness=$(ls -d test/fuzz/device/*/ test/fuzz/host/*/)
+        fuzz_harness=$(ls -d test/fuzz/device/*/)
         for h in $fuzz_harness
         do
           make $h get-deps
@@ -47,7 +46,7 @@ jobs:
 
     - name: Build Fuzzer
       run: |
-        fuzz_harness=$(ls -d test/fuzz/device/*/ test/fuzz/host/*/)
+        fuzz_harness=$(ls -d test/fuzz/device/*/)
         for h in $fuzz_harness
         do
           make $h all

From 33ea178cd9b7c2fdab1a677d2e676a94d131dbb0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 11:37:13 +0700
Subject: [PATCH 1285/2085] update build fuzzer step

---
 .github/workflows/pre-commit.yml | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index 29a412bcf..653084ca6 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -36,18 +36,11 @@ jobs:
         cd test/unit-test
         ceedling test:all
 
-    - name: Fetch deps
-      run: |
-        fuzz_harness=$(ls -d test/fuzz/device/*/)
-        for h in $fuzz_harness
-        do
-          make $h get-deps
-        done
-
     - name: Build Fuzzer
       run: |
         fuzz_harness=$(ls -d test/fuzz/device/*/)
         for h in $fuzz_harness
         do
+          make $h get-deps
           make $h all
         done

From 4deec2f4be2bf48e47dae4df969f4f0ecd042d94 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 11:40:43 +0700
Subject: [PATCH 1286/2085] fix ci

---
 .github/workflows/pre-commit.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index 653084ca6..8a1101ac0 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -41,6 +41,6 @@ jobs:
         fuzz_harness=$(ls -d test/fuzz/device/*/)
         for h in $fuzz_harness
         do
-          make $h get-deps
-          make $h all
+          make -C $h get-deps
+          make -C $h all
         done

From d0758d0733019debc7a61bf554d14b9a1f16c0cb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 11:47:01 +0700
Subject: [PATCH 1287/2085] correct ci paths filter

---
 .github/workflows/build_aarch64.yml | 16 ++++++++--------
 .github/workflows/build_arm.yml     | 16 ++++++++--------
 .github/workflows/build_esp.yml     | 16 ++++++++--------
 .github/workflows/build_msp430.yml  | 16 ++++++++--------
 .github/workflows/build_renesas.yml | 16 ++++++++--------
 .github/workflows/build_riscv.yml   | 16 ++++++++--------
 .github/workflows/test_hardware.yml | 16 ++++++++--------
 7 files changed, 56 insertions(+), 56 deletions(-)

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index ccfca6316..c552a9574 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -3,17 +3,17 @@ name: Build AArch64
 on:
   push:
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
   pull_request:
     branches: [ master ]
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index d1b94c47b..c16fc0d45 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -3,17 +3,17 @@ name: Build ARM
 on:
   push:
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
   pull_request:
     branches: [ master ]
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 7f2c292fa..df4d3d1f5 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -3,17 +3,17 @@ name: Build ESP
 on:
   push:
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'      
   pull_request:
     branches: [ master ]
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index f41344e30..7e1c5b128 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -3,17 +3,17 @@ name: Build MSP430
 on:
   push:
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
   pull_request:
     branches: [ master ]
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index d6550ed6d..d9254dea8 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -3,17 +3,17 @@ name: Build Renesas
 on:
   push:
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
   pull_request:
     branches: [ master ]
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 257050a53..026da7bdc 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -3,17 +3,17 @@ name: Build RISC-V
 on:
   push:
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
   pull_request:
     branches: [ master ]
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 622b079da..601a97e99 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -3,17 +3,17 @@ name: Hardware Test
 on:
   push:
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
   pull_request:
     branches: [ master ]
     paths:
-      - 'src'
-      - 'examples'
-      - 'lib'
-      - 'hw'
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
 
 # Hardware in the loop (HIL)
 # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user

From c19bffb1d91dd7dad3365fce938b6d6687d4e5b0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 11:48:53 +0700
Subject: [PATCH 1288/2085] clean up

---
 .github/workflows/build_esp.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index df4d3d1f5..2e2859c95 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -6,7 +6,7 @@ on:
       - 'src/**'
       - 'examples/**'
       - 'lib/**'
-      - 'hw/**'      
+      - 'hw/**'
   pull_request:
     branches: [ master ]
     paths:

From bae7fe5be7f8a29a4b0951c7270718f20110a394 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 13:10:24 +0700
Subject: [PATCH 1289/2085] add test fifo overwritable + overflow, that cause
 buffer overflow

---
 test/unit-test/test/test_fifo.c | 111 ++++++++++++++++++++------------
 1 file changed, 69 insertions(+), 42 deletions(-)

diff --git a/test/unit-test/test/test_fifo.c b/test/unit-test/test/test_fifo.c
index 0a5f4d3b9..5e639401d 100644
--- a/test/unit-test/test/test_fifo.c
+++ b/test/unit-test/test/test_fifo.c
@@ -28,15 +28,21 @@
 #include "unity.h"
 #include "tusb_fifo.h"
 
-#define FIFO_SIZE 10
+#define FIFO_SIZE 64
 TU_FIFO_DEF(tu_ff, FIFO_SIZE, uint8_t, false);
 tu_fifo_t* ff = &tu_ff;
 tu_fifo_buffer_info_t info;
 
+uint8_t test_data[4096];
+uint8_t rd_buf[FIFO_SIZE];
+
 void setUp(void)
 {
   tu_fifo_clear(ff);
   memset(&info, 0, sizeof(tu_fifo_buffer_info_t));
+
+  for(int i=0; i<sizeof(test_data); i++) test_data[i] = i;
+  memset(rd_buf, 0, sizeof(rd_buf));
 }
 
 void tearDown(void)
@@ -61,85 +67,106 @@ void test_normal(void)
 void test_item_size(void)
 {
   TU_FIFO_DEF(ff4, FIFO_SIZE, uint32_t, false);
-  tu_fifo_clear(&ff4);
 
-  uint32_t data[20];
-  for(uint32_t i=0; i<sizeof(data)/4; i++) data[i] = i;
+  uint32_t data4[2*FIFO_SIZE];
+  for(uint32_t i=0; i<sizeof(data4)/4; i++) data4[i] = i;
 
-  tu_fifo_write_n(&ff4, data, 10);
+  // fill up fifo
+  tu_fifo_write_n(&ff4, data4, FIFO_SIZE);
 
-  uint32_t rd[10];
+  uint32_t rd_buf4[FIFO_SIZE];
   uint16_t rd_count;
 
   // read 0 -> 4
-  rd_count = tu_fifo_read_n(&ff4, rd, 5);
+  rd_count = tu_fifo_read_n(&ff4, rd_buf4, 5);
   TEST_ASSERT_EQUAL( 5, rd_count );
-  TEST_ASSERT_EQUAL_UINT32_ARRAY( data, rd, rd_count ); // 0 -> 4
+  TEST_ASSERT_EQUAL_UINT32_ARRAY( data4, rd_buf4, rd_count ); // 0 -> 4
 
-  tu_fifo_write_n(&ff4, data+10, 5);
+  tu_fifo_write_n(&ff4, data4+FIFO_SIZE, 5);
 
-  // read 5 -> 14
-  rd_count = tu_fifo_read_n(&ff4, rd, 10);
-  TEST_ASSERT_EQUAL( 10, rd_count );
-  TEST_ASSERT_EQUAL_UINT32_ARRAY( data+5, rd, rd_count ); // 5 -> 14
+  // read all 5 -> 68
+  rd_count = tu_fifo_read_n(&ff4, rd_buf4, FIFO_SIZE);
+  TEST_ASSERT_EQUAL( FIFO_SIZE, rd_count );
+  TEST_ASSERT_EQUAL_UINT32_ARRAY( data4+5, rd_buf4, rd_count ); // 5 -> 68
 }
 
 void test_read_n(void)
 {
-  // prepare data
-  uint8_t data[20];
-  for(int i=0; i<sizeof(data); i++) data[i] = i;
-
-  for(uint8_t i=0; i < FIFO_SIZE; i++) tu_fifo_write(ff, data+i);
-
-  uint8_t rd[10];
   uint16_t rd_count;
 
+  // fill up fifo
+  for(uint8_t i=0; i < FIFO_SIZE; i++) tu_fifo_write(ff, test_data+i);
+
   // case 1: Read index + count < depth
   // read 0 -> 4
-  rd_count = tu_fifo_read_n(ff, rd, 5);
+  rd_count = tu_fifo_read_n(ff, rd_buf, 5);
   TEST_ASSERT_EQUAL( 5, rd_count );
-  TEST_ASSERT_EQUAL_MEMORY( data, rd, rd_count ); // 0 -> 4
+  TEST_ASSERT_EQUAL_MEMORY( test_data, rd_buf, rd_count ); // 0 -> 4
 
   // case 2: Read index + count > depth
   // write 10, 11, 12
-  tu_fifo_write(ff, data+10);
-  tu_fifo_write(ff, data+11);
-  tu_fifo_write(ff, data+12);
+  tu_fifo_write(ff, test_data+FIFO_SIZE);
+  tu_fifo_write(ff, test_data+FIFO_SIZE+1);
+  tu_fifo_write(ff, test_data+FIFO_SIZE+2);
 
-  rd_count = tu_fifo_read_n(ff, rd, 7);
+  rd_count = tu_fifo_read_n(ff, rd_buf, 7);
   TEST_ASSERT_EQUAL( 7, rd_count );
 
-  TEST_ASSERT_EQUAL_MEMORY( data+5, rd, rd_count ); // 5 -> 11
+  TEST_ASSERT_EQUAL_MEMORY( test_data+5, rd_buf, rd_count ); // 5 -> 11
 
   // Should only read until empty
-  TEST_ASSERT_EQUAL( 1, tu_fifo_read_n(ff, rd, 100) );
+  TEST_ASSERT_EQUAL( FIFO_SIZE-5+3-7, tu_fifo_read_n(ff, rd_buf, 100) );
 }
 
 void test_write_n(void)
 {
-  // prepare data
-  uint8_t data[20];
-  for(int i=0; i<sizeof(data); i++) data[i] = i;
-
   // case 1: wr + count < depth
-  tu_fifo_write_n(ff, data, 8); // wr = 8, count = 8
+  tu_fifo_write_n(ff, test_data, 32); // wr = 32, count = 32
 
-  uint8_t rd[10];
   uint16_t rd_count;
 
-  rd_count = tu_fifo_read_n(ff, rd, 5); // wr = 8, count = 3
-  TEST_ASSERT_EQUAL( 5, rd_count );
-  TEST_ASSERT_EQUAL_MEMORY( data, rd, rd_count ); // 0 -> 4
+  rd_count = tu_fifo_read_n(ff, rd_buf, 16); // wr = 32, count = 16
+  TEST_ASSERT_EQUAL( 16, rd_count );
+  TEST_ASSERT_EQUAL_MEMORY( test_data, rd_buf, rd_count );
 
   // case 2: wr + count > depth
-  tu_fifo_write_n(ff, data+8, 6); // wr = 3, count = 9
+  tu_fifo_write_n(ff, test_data+32, 40); // wr = 72 -> 8, count = 56
 
-  for(rd_count=0; rd_count<7; rd_count++) tu_fifo_read(ff, rd+rd_count); // wr = 3, count = 2
+  tu_fifo_read_n(ff, rd_buf, 32); // count = 24
+  TEST_ASSERT_EQUAL_MEMORY( test_data+16, rd_buf, rd_count);
 
-  TEST_ASSERT_EQUAL_MEMORY( data+5, rd, rd_count); // 5 -> 11
+  TEST_ASSERT_EQUAL(24, tu_fifo_count(ff));
+}
 
-  TEST_ASSERT_EQUAL(2, tu_fifo_count(ff));
+static uint16_t help_write(uint16_t total, uint16_t n)
+{
+  tu_fifo_write_n(ff, test_data, n);
+  total = tu_min16(FIFO_SIZE, total + n);
+
+  TEST_ASSERT_EQUAL(total, tu_fifo_count(ff));
+  TEST_ASSERT_EQUAL(FIFO_SIZE - total, tu_fifo_remaining(ff));
+
+  return total;
+}
+
+void test_write_overwritable(void)
+{
+  tu_fifo_set_overwritable(ff, true);
+
+  // based on actual crash tests detected by fuzzing
+  uint16_t total = 0;
+
+  total = help_write(total, 12);
+  total = help_write(total, 55);
+  total = help_write(total, 73);
+  total = help_write(total, 55);
+  total = help_write(total, 75);
+  total = help_write(total, 84);
+  total = help_write(total, 1);
+  total = help_write(total, 10);
+  total = help_write(total, 12);
+  total = help_write(total, 25);
+  total = help_write(total, 192);
 }
 
 void test_peek(void)
@@ -315,4 +342,4 @@ void test_rd_idx_wrap()
   n = tu_fifo_read_n(&ff10, dst, 4);
   TEST_ASSERT_EQUAL(n, 2);
   TEST_ASSERT_EQUAL(ff10.rd_idx, 6);
-}
\ No newline at end of file
+}

From 3e32fa36b86c502a35341f7f1aba62b89dae8fcb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Dec 2022 16:39:24 +0700
Subject: [PATCH 1290/2085] enhance tu fifo

- rename wr/rd absolute to index, and rel to pointer.
- fix crash with _tu_fifo_remaining()
- change get_relative_pointer() to idx2ptr() and merge with _ff_mod()
---
 src/common/tusb_fifo.c | 205 ++++++++++++++++++++++++-----------------
 src/common/tusb_fifo.h |   6 +-
 2 files changed, 124 insertions(+), 87 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index b857c6444..853614d28 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -34,6 +34,8 @@
 #pragma diag_suppress = Pa082
 #endif
 
+#define TU_FIFO_DBG   0
+
 // implement mutex lock and unlock
 #if CFG_FIFO_MUTEX
 
@@ -90,12 +92,9 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
   return true;
 }
 
-// Static functions are intended to work on local variables
-static inline uint16_t _ff_mod(uint16_t idx, uint16_t depth)
-{
-  while ( idx >= depth) idx -= depth;
-  return idx;
-}
+//--------------------------------------------------------------------+
+// Pull & Push
+//--------------------------------------------------------------------+
 
 // Intended to be used to read from hardware USB FIFO in e.g. STM32 where all data is read from a constant address
 // Code adapted from dcd_synopsys.c
@@ -179,7 +178,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         // Write data to linear part of buffer
         memcpy(ff_buf, app_buf, nLin_bytes);
 
-        // Write data wrapped around
+        TU_ASSERT(nWrap_bytes <= f->depth, );
         memcpy(f->buffer, ((uint8_t const*) app_buf) + nLin_bytes, nWrap_bytes);
       }
       break;
@@ -317,21 +316,24 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
   }
 }
 
+//--------------------------------------------------------------------+
+// Index (free-running and real buffer pointer)
+//--------------------------------------------------------------------+
+
 // Advance an absolute pointer
+// "absolute" index is only in the range of [0..2*depth)
 static uint16_t advance_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
 {
   // We limit the index space of p such that a correct wrap around happens
   // Check for a wrap around or if we are in unused index space - This has to be checked first!!
   // We are exploiting the wrap around to the correct index
-  if ((p > (uint16_t)(p + offset)) || ((uint16_t)(p + offset) > f->max_pointer_idx))
+  uint16_t next_p = (uint16_t) (p + offset);
+  if ( (p > next_p) || (next_p > f->max_pointer_idx) )
   {
-    p = (uint16_t) ((p + offset) + f->non_used_index_space);
+    next_p = (uint16_t) (next_p + f->non_used_index_space);
   }
-  else
-  {
-    p += offset;
-  }
-  return p;
+
+  return next_p;
 }
 
 // Backward an absolute pointer
@@ -340,30 +342,33 @@ static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
   // We limit the index space of p such that a correct wrap around happens
   // Check for a wrap around or if we are in unused index space - This has to be checked first!!
   // We are exploiting the wrap around to the correct index
-  if ((p < (uint16_t)(p - offset)) || ((uint16_t)(p - offset) > f->max_pointer_idx))
+  uint16_t new_p = (uint16_t) (p - offset);
+  if ( (p < new_p) || (new_p > f->max_pointer_idx) )
   {
-    p = (uint16_t) ((p - offset) - f->non_used_index_space);
+    new_p = (uint16_t) (new_p - f->non_used_index_space);
   }
-  else
-  {
-    p -= offset;
-  }
-  return p;
+
+  return new_p;
 }
 
-// get relative from absolute pointer
-static uint16_t get_relative_pointer(tu_fifo_t* f, uint16_t p)
+// index to pointer, simply an modulo with minus
+static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth)
 {
-  return _ff_mod(p, f->depth);
+  while ( idx >= depth ) idx -= depth;
+  return idx;
 }
 
 // Works on local copies of w and r - return only the difference and as such can be used to determine an overflow
-static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
+static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx)
 {
-  uint16_t cnt = wAbs-rAbs;
+  uint16_t cnt = (uint16_t) (wr_idx-rd_idx);
 
   // In case we have non-power of two depth we need a further modification
-  if (rAbs > wAbs) cnt -= f->non_used_index_space;
+  if (rd_idx > wr_idx)
+  {
+    // 2*f->depth - (rd_idx - wr_idx);
+    cnt = (uint16_t) (cnt - f->non_used_index_space);
+  }
 
   return cnt;
 }
@@ -400,39 +405,39 @@ static inline void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs)
 
 // Works on local copies of w and r
 // Must be protected by mutexes since in case of an overflow read pointer gets modified
-static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wAbs, uint16_t rAbs)
+static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16_t rd_idx)
 {
-  uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs);
+  uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx);
 
   // Check overflow and correct if required
   if (cnt > f->depth)
   {
-    _tu_fifo_correct_read_pointer(f, wAbs);
+    _tu_fifo_correct_read_pointer(f, wr_idx);
     cnt = f->depth;
   }
 
   // Skip beginning of buffer
   if (cnt == 0) return false;
 
-  uint16_t rRel = get_relative_pointer(f, rAbs);
+  uint16_t rd_ptr = idx2ptr(rd_idx, f->depth);
 
   // Peek data
-  _ff_pull(f, p_buffer, rRel);
+  _ff_pull(f, p_buffer, rd_ptr);
 
   return true;
 }
 
 // Works on local copies of w and r
 // Must be protected by mutexes since in case of an overflow read pointer gets modified
-static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t wAbs, uint16_t rAbs, tu_fifo_copy_mode_t copy_mode)
+static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t wr_idx, uint16_t rd_idx, tu_fifo_copy_mode_t copy_mode)
 {
-  uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs);
+  uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx);
 
   // Check overflow and correct if required
   if (cnt > f->depth)
   {
-    _tu_fifo_correct_read_pointer(f, wAbs);
-    rAbs = f->rd_idx;
+    _tu_fifo_correct_read_pointer(f, wr_idx);
+    rd_idx = f->rd_idx;
     cnt = f->depth;
   }
 
@@ -442,53 +447,80 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1
   // Check if we can read something at and after offset - if too less is available we read what remains
   if (cnt < n) n = cnt;
 
-  uint16_t rRel = get_relative_pointer(f, rAbs);
+  uint16_t rd_ptr = idx2ptr(rd_idx, f->depth);
 
   // Peek data
-  _ff_pull_n(f, p_buffer, n, rRel, copy_mode);
+  _ff_pull_n(f, p_buffer, n, rd_ptr, copy_mode);
 
   return n;
 }
 
 // Works on local copies of w and r
-static inline uint16_t _tu_fifo_remaining(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
+static inline uint16_t _tu_fifo_remaining(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx)
 {
-  return f->depth - _tu_fifo_count(f, wAbs, rAbs);
+  uint16_t const count = _tu_fifo_count(f, wr_idx, rd_idx);
+  return (f->depth > count) ? (f->depth - count) : 0;
 }
 
 static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu_fifo_copy_mode_t copy_mode)
 {
   if ( n == 0 ) return 0;
 
+  TU_LOG(TU_FIFO_DBG, "rd = %u, wr = %02u, n = %u:  ", f->rd_idx, f->wr_idx, n);
+
   _ff_lock(f->mutex_wr);
 
-  uint16_t w = f->wr_idx, r = f->rd_idx;
+  uint16_t wr_idx = f->wr_idx;
+  uint16_t rd_idx = f->rd_idx;
+
   uint8_t const* buf8 = (uint8_t const*) data;
+  uint16_t const remain = _tu_fifo_remaining(f, wr_idx, rd_idx);
 
-  if (!f->overwritable)
+  if ( n > remain)
   {
-    // Not overwritable limit up to full
-    n = tu_min16(n, _tu_fifo_remaining(f, w, r));
-  }
-  else if (n >= f->depth)
-  {
-    // Only copy last part
-    buf8 = buf8 + (n - f->depth) * f->item_size;
-    n = f->depth;
+    if ( !f->overwritable )
+    {
+      // limit up to full
+      n = remain;
+    }
+    else
+    {
+      // oldest data in fifo i.e read pointer data will be overwritten
+      // Note: we modify read data but we do not want to modify the read pointer within a write function!
+      // since it would end up in a race condition with read functions!
+      // Note2: race condition could still occur if tu_fifo_read() is called while we modify its buffer (corrupted data)
 
-    // We start writing at the read pointer's position since we fill the complete
-    // buffer and we do not want to modify the read pointer within a write function!
-    // This would end up in a race condition with read functions!
-    w = r;
+      if ( n >= f->depth )
+      {
+        // Only copy last part
+        buf8 = buf8 + (n - f->depth) * f->item_size;
+        n = f->depth;
+
+        // We start writing at the read pointer's position since we fill the complete
+        // buffer and we do not want to modify the read pointer within a write function!
+        // This would end up in a race condition with read functions!
+        wr_idx = rd_idx;
+      }else
+      {
+        // TODO shift out oldest data from read pointer !!!
+      }
+    }
   }
 
-  uint16_t wRel = get_relative_pointer(f, w);
+  if (n)
+  {
+    uint16_t wr_ptr = idx2ptr(wr_idx, f->depth);
 
-  // Write data
-  _ff_push_n(f, buf8, n, wRel, copy_mode);
+    TU_LOG(TU_FIFO_DBG, "actual_n = %u, wr_rel = %u", n, wr_ptr);
 
-  // Advance pointer
-  f->wr_idx = advance_pointer(f, w, n);
+    // Write data
+    _ff_push_n(f, buf8, n, wr_ptr, copy_mode);
+
+    // Advance pointer
+    f->wr_idx = advance_pointer(f, wr_idx, n);
+
+    TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\n", f->wr_idx);
+  }
 
   _ff_unlock(f->mutex_wr);
 
@@ -742,20 +774,20 @@ bool tu_fifo_write(tu_fifo_t* f, const void * data)
   _ff_lock(f->mutex_wr);
 
   bool ret;
-  uint16_t const w = f->wr_idx;
+  uint16_t const wr_idx = f->wr_idx;
 
-  if ( _tu_fifo_full(f, w, f->rd_idx) && !f->overwritable )
+  if ( _tu_fifo_full(f, wr_idx, f->rd_idx) && !f->overwritable )
   {
     ret = false;
   }else
   {
-    uint16_t wRel = get_relative_pointer(f, w);
+    uint16_t wr_ptr = idx2ptr(wr_idx, f->depth);
 
     // Write data
-    _ff_push(f, data, wRel);
+    _ff_push(f, data, wr_ptr);
 
     // Advance pointer
-    f->wr_idx = advance_pointer(f, w, 1);
+    f->wr_idx = advance_pointer(f, wr_idx, 1);
 
     ret = true;
   }
@@ -909,17 +941,19 @@ void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n)
 void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
 {
   // Operate on temporary values in case they change in between
-  uint16_t w = f->wr_idx, r = f->rd_idx;
+  uint16_t wr_idx = f->wr_idx;
+  uint16_t rd_idx = f->rd_idx;
 
-  uint16_t cnt = _tu_fifo_count(f, w, r);
+  uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx);
 
   // Check overflow and correct if required - may happen in case a DMA wrote too fast
   if (cnt > f->depth)
   {
     _ff_lock(f->mutex_rd);
-    _tu_fifo_correct_read_pointer(f, w);
+    _tu_fifo_correct_read_pointer(f, wr_idx);
     _ff_unlock(f->mutex_rd);
-    r = f->rd_idx;
+
+    rd_idx = f->rd_idx;
     cnt = f->depth;
   }
 
@@ -934,22 +968,24 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
   }
 
   // Get relative pointers
-  w = get_relative_pointer(f, w);
-  r = get_relative_pointer(f, r);
+  uint16_t wr_ptr = idx2ptr(wr_idx, f->depth);
+  uint16_t rd_ptr = idx2ptr(rd_idx, f->depth);
 
   // Copy pointer to buffer to start reading from
-  info->ptr_lin = &f->buffer[r];
+  info->ptr_lin = &f->buffer[rd_ptr];
 
   // Check if there is a wrap around necessary
-  if (w > r) {
+  if (wr_ptr > rd_ptr) {
     // Non wrapping case
     info->len_lin  = cnt;
+
     info->len_wrap = 0;
     info->ptr_wrap = NULL;
   }
   else
   {
-    info->len_lin  = f->depth - r;         // Also the case if FIFO was full
+    info->len_lin  = f->depth - rd_ptr;   // Also the case if FIFO was full
+
     info->len_wrap = cnt - info->len_lin;
     info->ptr_wrap = f->buffer;
   }
@@ -972,10 +1008,11 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
 /******************************************************************************/
 void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
 {
-  uint16_t w = f->wr_idx, r = f->rd_idx;
-  uint16_t free = _tu_fifo_remaining(f, w, r);
+  uint16_t wr_idx = f->wr_idx;
+  uint16_t rd_idx = f->rd_idx;
+  uint16_t remain = _tu_fifo_remaining(f, wr_idx, rd_idx);
 
-  if (free == 0)
+  if (remain == 0)
   {
     info->len_lin = 0;
     info->len_wrap = 0;
@@ -985,23 +1022,23 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
   }
 
   // Get relative pointers
-  w = get_relative_pointer(f, w);
-  r = get_relative_pointer(f, r);
+  uint16_t wr_ptr = idx2ptr(wr_idx, f->depth);
+  uint16_t rd_ptr = idx2ptr(rd_idx, f->depth);
 
   // Copy pointer to buffer to start writing to
-  info->ptr_lin = &f->buffer[w];
+  info->ptr_lin = &f->buffer[wr_ptr];
 
-  if (w < r)
+  if (wr_ptr < rd_ptr)
   {
     // Non wrapping case
-    info->len_lin = r-w;
+    info->len_lin  = rd_ptr-wr_ptr;
     info->len_wrap = 0;
     info->ptr_wrap = NULL;
   }
   else
   {
-    info->len_lin = f->depth - w;
-    info->len_wrap = free - info->len_lin; // Remaining length - n already was limited to free or FIFO depth
-    info->ptr_wrap = f->buffer;            // Always start of buffer
+    info->len_lin  = f->depth - wr_ptr;
+    info->len_wrap = remain - info->len_lin; // Remaining length - n already was limited to remain or FIFO depth
+    info->ptr_wrap = f->buffer;              // Always start of buffer
   }
 }
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index e64ab4b6d..204d53081 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -101,10 +101,10 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
 
 #if CFG_FIFO_MUTEX
 TU_ATTR_ALWAYS_INLINE static inline
-void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t write_mutex_hdl, tu_fifo_mutex_t read_mutex_hdl)
+void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t wr_mutex, tu_fifo_mutex_t rd_mutex)
 {
-  f->mutex_wr = write_mutex_hdl;
-  f->mutex_rd = read_mutex_hdl;
+  f->mutex_wr = wr_mutex;
+  f->mutex_rd = rd_mutex;
 }
 #endif
 

From 15ab35d9b82590e49937457efd2654adb2dd8b65 Mon Sep 17 00:00:00 2001
From: Sebastien COUDREAU <sebastien.coudreau@fastlite.com>
Date: Thu, 8 Dec 2022 11:18:28 +0100
Subject: [PATCH 1291/2085] usbtmc: correct packet size bug

Code was only reading the first 64 bytes of a 512 bytes packet.
---
 src/class/usbtmc/usbtmc_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 0f6d3f60d..0b7c28b6e 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -364,7 +364,7 @@ bool tud_usbtmc_start_bus_read()
   default:
     TU_VERIFY(false);
   }
-  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, 64));
+  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, usbtmc_state.ep_bulk_out_wMaxPacketSize));
   return true;
 }
 

From 071da47944a4345b41328dc514d8a73a537072a9 Mon Sep 17 00:00:00 2001
From: Sebastien COUDREAU <sebastien.coudreau@fastlite.com>
Date: Thu, 8 Dec 2022 11:36:48 +0100
Subject: [PATCH 1292/2085] Correct interrupt polling interval in descriptor

Use macro argument instead of 0x16 constant value.
At least Linux kernel was complaining about this value:
"config 1 interface 0 altsetting 0 endpoint 0x82 has an invalid bInterval 22, changing to 8"
(warning obtained using usbtmc device config)
---
 src/device/usbd.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/device/usbd.h b/src/device/usbd.h
index dc5b35ffd..118e53ce4 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -603,7 +603,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 /* optional interrupt endpoint */ \
 // _int_pollingInterval : for LS/FS, expressed in frames (1ms each). 16 may be a good number?
 #define TUD_USBTMC_INT_DESCRIPTOR(_ep_interrupt, _ep_interrupt_size, _int_pollingInterval ) \
-  7, TUSB_DESC_ENDPOINT, _ep_interrupt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_interrupt_size), 0x16
+  7, TUSB_DESC_ENDPOINT, _ep_interrupt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_interrupt_size), _int_pollingInterval
 
 #define TUD_USBTMC_INT_DESCRIPTOR_LEN (7u)
 

From 007ed1f0fe84c13567c7a4ccda79d71a05d79aec Mon Sep 17 00:00:00 2001
From: scoudreau <95369154+scoudreau@users.noreply.github.com>
Date: Thu, 8 Dec 2022 14:50:34 +0100
Subject: [PATCH 1293/2085] Added missing typecast to pass build checks

---
 src/class/usbtmc/usbtmc_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 0b7c28b6e..122b3f3cf 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -364,7 +364,7 @@ bool tud_usbtmc_start_bus_read()
   default:
     TU_VERIFY(false);
   }
-  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, usbtmc_state.ep_bulk_out_wMaxPacketSize));
+  TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, (uint16_t)usbtmc_state.ep_bulk_out_wMaxPacketSize));
   return true;
 }
 

From 75989673e5246756beda3a3d816575ce0a77f315 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 9 Dec 2022 15:39:57 +0700
Subject: [PATCH 1294/2085] add test_write_double_overflowed for fifo

---
 test/unit-test/test/test_fifo.c | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/test/unit-test/test/test_fifo.c b/test/unit-test/test/test_fifo.c
index 5e639401d..55bc24b7e 100644
--- a/test/unit-test/test/test_fifo.c
+++ b/test/unit-test/test/test_fifo.c
@@ -138,6 +138,34 @@ void test_write_n(void)
   TEST_ASSERT_EQUAL(24, tu_fifo_count(ff));
 }
 
+void test_write_double_overflowed(void)
+{
+  tu_fifo_set_overwritable(ff, true);
+
+  uint8_t rd_buf[FIFO_SIZE] = { 0 };
+  uint8_t* buf = test_data;
+
+  // full
+  buf += tu_fifo_write_n(ff, buf, FIFO_SIZE);
+  TEST_ASSERT_EQUAL(FIFO_SIZE, tu_fifo_count(ff));
+
+  // write more, should still full
+  buf += tu_fifo_write_n(ff, buf, FIFO_SIZE-8);
+  TEST_ASSERT_EQUAL(FIFO_SIZE, tu_fifo_count(ff));
+
+  // double overflowed: in total, write more than > 2*FIFO_SIZE
+  buf += tu_fifo_write_n(ff, buf, 16);
+  TEST_ASSERT_EQUAL(FIFO_SIZE, tu_fifo_count(ff));
+
+  // reading back should give back data from last FIFO_SIZE write
+  tu_fifo_read_n(ff, rd_buf, FIFO_SIZE);
+
+  TEST_ASSERT_EQUAL_MEMORY(buf-16, rd_buf+FIFO_SIZE-16, 16);
+
+  // TODO whole buffer should match, but we deliberately not implement it
+  // TEST_ASSERT_EQUAL_MEMORY(buf-FIFO_SIZE, rd_buf, FIFO_SIZE);
+}
+
 static uint16_t help_write(uint16_t total, uint16_t n)
 {
   tu_fifo_write_n(ff, test_data, n);
@@ -149,7 +177,7 @@ static uint16_t help_write(uint16_t total, uint16_t n)
   return total;
 }
 
-void test_write_overwritable(void)
+void test_write_overwritable2(void)
 {
   tu_fifo_set_overwritable(ff, true);
 

From 82852774a74631e0916254022339c9713c44cb57 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 9 Dec 2022 18:20:09 +0700
Subject: [PATCH 1295/2085] add fifo implementation note

- handle/fix double overflowed with write()
- other minor clean upp
---
 src/common/tusb_fifo.c | 94 ++++++++++++++++++++++++------------------
 src/common/tusb_fifo.h | 63 ++++++++++++++++++++++++++--
 2 files changed, 113 insertions(+), 44 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 853614d28..df07a990c 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -81,8 +81,8 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
   // Limit index space to 2*depth - this allows for a fast "modulo" calculation
   // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable
   // only if overflow happens once (important for unsupervised DMA applications)
-  f->max_pointer_idx = (uint16_t) (2*depth - 1);
-  f->non_used_index_space = UINT16_MAX - f->max_pointer_idx;
+  //f->max_pointer_idx = (uint16_t) (2*depth - 1);
+  f->non_used_index_space = UINT16_MAX - (2*f->depth-1);
 
   f->rd_idx = f->wr_idx = 0;
 
@@ -320,15 +320,15 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
 // Index (free-running and real buffer pointer)
 //--------------------------------------------------------------------+
 
-// Advance an absolute pointer
+// Advance an absolute index
 // "absolute" index is only in the range of [0..2*depth)
-static uint16_t advance_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
+static uint16_t advance_pointer(tu_fifo_t* f, uint16_t idx, uint16_t offset)
 {
   // We limit the index space of p such that a correct wrap around happens
   // Check for a wrap around or if we are in unused index space - This has to be checked first!!
   // We are exploiting the wrap around to the correct index
-  uint16_t next_p = (uint16_t) (p + offset);
-  if ( (p > next_p) || (next_p > f->max_pointer_idx) )
+  uint16_t next_p = (uint16_t) (idx + offset);
+  if ( (idx > next_p) || (next_p >= 2*f->depth) )
   {
     next_p = (uint16_t) (next_p + f->non_used_index_space);
   }
@@ -343,7 +343,7 @@ static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
   // Check for a wrap around or if we are in unused index space - This has to be checked first!!
   // We are exploiting the wrap around to the correct index
   uint16_t new_p = (uint16_t) (p - offset);
-  if ( (p < new_p) || (new_p > f->max_pointer_idx) )
+  if ( (p < new_p) || (new_p >= 2*f->depth) )
   {
     new_p = (uint16_t) (new_p - f->non_used_index_space);
   }
@@ -374,15 +374,15 @@ static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd
 }
 
 // Works on local copies of w and r
-static inline bool _tu_fifo_empty(uint16_t wAbs, uint16_t rAbs)
+static inline bool _tu_fifo_empty(uint16_t wr_idx, uint16_t rd_idx)
 {
-  return wAbs == rAbs;
+  return wr_idx == rd_idx;
 }
 
 // Works on local copies of w and r
 static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
 {
-  return (_tu_fifo_count(f, wAbs, rAbs) == f->depth);
+  return _tu_fifo_count(f, wAbs, rAbs) == f->depth;
 }
 
 // Works on local copies of w and r
@@ -391,9 +391,9 @@ static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
 // write more than 2*depth-1 items in one rush without updating write pointer. Otherwise
 // write pointer wraps and you pointer states are messed up. This can only happen if you
 // use DMAs, write functions do not allow such an error.
-static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
+static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx)
 {
-  return (_tu_fifo_count(f, wAbs, rAbs) > f->depth);
+  return (_tu_fifo_count(f, wr_idx, rd_idx) > f->depth);
 }
 
 // Works on local copies of w
@@ -466,44 +466,58 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
 {
   if ( n == 0 ) return 0;
 
-  TU_LOG(TU_FIFO_DBG, "rd = %u, wr = %02u, n = %u:  ", f->rd_idx, f->wr_idx, n);
-
   _ff_lock(f->mutex_wr);
 
   uint16_t wr_idx = f->wr_idx;
   uint16_t rd_idx = f->rd_idx;
 
   uint8_t const* buf8 = (uint8_t const*) data;
+  uint16_t overflowable_count = _tu_fifo_count(f, wr_idx, rd_idx);
   uint16_t const remain = _tu_fifo_remaining(f, wr_idx, rd_idx);
 
-  if ( n > remain)
+  TU_LOG(TU_FIFO_DBG, "rd = %3u, wr = %3u, count = %3u, remain = %3u, n = %3u:  ", rd_idx, wr_idx, _tu_fifo_count(f, wr_idx, rd_idx), remain, n);
+
+  if ( !f->overwritable )
   {
-    if ( !f->overwritable )
+    // limit up to full
+    n = tu_min16(n, remain);
+  }
+  else
+  {
+    // In over-writable mode, fifo_write() is allowed even when fifo is full. In such case,
+    // oldest data in fifo i.e at read pointer data will be overwritten
+    // Note: we can modify read buffer contents but we must not modify the read index itself within a write function!
+    // Since it would end up in a race condition with read functions!
+    if ( n >= f->depth )
     {
-      // limit up to full
-      n = remain;
-    }
-    else
-    {
-      // oldest data in fifo i.e read pointer data will be overwritten
-      // Note: we modify read data but we do not want to modify the read pointer within a write function!
-      // since it would end up in a race condition with read functions!
-      // Note2: race condition could still occur if tu_fifo_read() is called while we modify its buffer (corrupted data)
-
-      if ( n >= f->depth )
+      // Only copy last part
+      if ( copy_mode == TU_FIFO_COPY_INC )
       {
-        // Only copy last part
-        buf8 = buf8 + (n - f->depth) * f->item_size;
-        n = f->depth;
-
-        // We start writing at the read pointer's position since we fill the complete
-        // buffer and we do not want to modify the read pointer within a write function!
-        // This would end up in a race condition with read functions!
-        wr_idx = rd_idx;
+        buf8 += (n - f->depth) * f->item_size;
       }else
       {
-        // TODO shift out oldest data from read pointer !!!
+        // TODO should read from hw fifo to discard data, however reading an odd number could
+        // accidentally discard data.
       }
+
+      n = f->depth;
+
+      // We start writing at the read pointer's position since we fill the whole buffer
+      wr_idx = rd_idx;
+    }else if (overflowable_count + n >= 2*f->depth)
+    {
+      // Double overflowed
+      // re-position write index to have a full fifo after pushed
+      wr_idx = advance_pointer(f, rd_idx, f->depth - n);
+
+      // TODO we should also shift out n bytes from read index since we avoid changing rd index !!
+      // However memmove() is expensive due to actual copying + wrapping consideration.
+      // Also race condition could happen anyway if read() is invoke while moving result in corrupted memory
+      // currently deliberately not implemented --> result in incorrect data read back
+    }else
+    {
+      // normal + single overflowed: just increase write index
+      // we will correct (re-position) read index later on in fifo_read() function
     }
   }
 
@@ -511,12 +525,12 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
   {
     uint16_t wr_ptr = idx2ptr(wr_idx, f->depth);
 
-    TU_LOG(TU_FIFO_DBG, "actual_n = %u, wr_rel = %u", n, wr_ptr);
+    TU_LOG(TU_FIFO_DBG, "actual_n = %u, wr_ptr = %u", n, wr_ptr);
 
     // Write data
     _ff_push_n(f, buf8, n, wr_ptr, copy_mode);
 
-    // Advance pointer
+    // Advance index
     f->wr_idx = advance_pointer(f, wr_idx, n);
 
     TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\n", f->wr_idx);
@@ -850,8 +864,8 @@ bool tu_fifo_clear(tu_fifo_t *f)
   _ff_lock(f->mutex_rd);
 
   f->rd_idx = f->wr_idx = 0;
-  f->max_pointer_idx = (uint16_t) (2*f->depth-1);
-  f->non_used_index_space = UINT16_MAX - f->max_pointer_idx;
+  //f->max_pointer_idx = (uint16_t) (2*f->depth-1);
+  f->non_used_index_space = UINT16_MAX - (2*f->depth-1);
 
   _ff_unlock(f->mutex_wr);
   _ff_unlock(f->mutex_rd);
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 204d53081..fd149b75c 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -52,18 +52,74 @@ extern "C" {
 #define tu_fifo_mutex_t  osal_mutex_t
 #endif
 
+/* Write/Read index is always in the range of:
+ *      0 .. 2*depth-1
+ * The extra window allow us to determine the fifo state of empty or full with only 2 indexes
+ * Following are examples with depth = 3
+ *
+ * - empty: W = R
+ *                |
+ *    -------------------------
+ *    | 0 | RW| 2 | 3 | 4 | 5 |
+ *
+ * - full 1: W > R
+ *                |
+ *    -------------------------
+ *    | 0 | R | 2 | 3 | W | 5 |
+ *
+ * - full 2: W < R
+ *                |
+ *    -------------------------
+ *    | 0 | 1 | W | 3 | 4 | R |
+ *
+ * - Number of items in the fifo can be determined in either cases:
+ *    - case W > R: Count = W - R
+ *    - case W < R: Count = 2*depth - (R - W)
+ *
+ * In non-overwritable mode, computed Count (in above 2 cases) is at most equal to depth.
+ * However, in over-writable mode, write index can be repeatedly increased and count can be
+ * temporarily larger than depth (overflowed condition) e.g
+ *
+ *  - Overflowed 1: write(3), write(1)
+ *    In this case we will adjust Read index when read()/peek() is called so that count = depth.
+ *                  |
+ *      -------------------------
+ *      | R | 1 | 2 | 3 | W | 5 |
+ *
+ *  - Double Overflowed: write(3), write(1), write(2)
+ *    Continue to write after overflowed to 2nd overflowed.
+ *    We must prevent 2nd overflowed since it will cause incorrect computed of count, in above example
+ *    if not handled the fifo will be empty instead of continue-to-be full. Since we must not modify
+ *    read index in write() function, which cause race condition. We will re-position write index so that
+ *    after data is written it is a full fifo i.e W = depth - R
+ *
+ *      re-position W = 1 before write(2)
+ *      Note: we should also move data from mem[4] to read index as well, but deliberately skipped here
+ *      since it is an expensive operation !!!
+ *                  |
+ *      -------------------------
+ *      | R | W | 2 | 3 | 4 | 5 |
+ *
+ *      perform write(2), result is still a full fifo.
+ *
+ *                  |
+ *      -------------------------
+ *      | R | 1 | 2 | W | 4 | 5 |
+
+ */
 typedef struct
 {
   uint8_t* buffer               ; ///< buffer pointer
   uint16_t depth                ; ///< max items
   uint16_t item_size            ; ///< size of each item
+
   bool overwritable             ;
 
   uint16_t non_used_index_space ; ///< required for non-power-of-two buffer length
-  uint16_t max_pointer_idx      ; ///< maximum absolute pointer index
+  //uint16_t max_pointer_idx      ; ///< maximum absolute pointer index
 
-  volatile uint16_t wr_idx      ; ///< write pointer
-  volatile uint16_t rd_idx      ; ///< read pointer
+  volatile uint16_t wr_idx      ; ///< write index
+  volatile uint16_t rd_idx      ; ///< read index
 
 #if CFG_FIFO_MUTEX
   tu_fifo_mutex_t mutex_wr;
@@ -87,7 +143,6 @@ typedef struct
   .item_size            = sizeof(_type),                    \
   .overwritable         = _overwritable,                    \
   .non_used_index_space = UINT16_MAX - (2*(_depth)-1),      \
-  .max_pointer_idx      = 2*(_depth)-1,                     \
 }
 
 #define TU_FIFO_DEF(_name, _depth, _type, _overwritable)                      \

From ce064de6fd4416bb5368a2aaff4283f8e4b9fc36 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 10 Dec 2022 00:18:11 +0700
Subject: [PATCH 1296/2085] clean up

---
 src/common/tusb_fifo.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index df07a990c..a3933416c 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -178,7 +178,8 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         // Write data to linear part of buffer
         memcpy(ff_buf, app_buf, nLin_bytes);
 
-        TU_ASSERT(nWrap_bytes <= f->depth, );
+        // Write data wrapped around
+        // TU_ASSERT(nWrap_bytes <= f->depth, );
         memcpy(f->buffer, ((uint8_t const*) app_buf) + nLin_bytes, nWrap_bytes);
       }
       break;
@@ -504,7 +505,8 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
 
       // We start writing at the read pointer's position since we fill the whole buffer
       wr_idx = rd_idx;
-    }else if (overflowable_count + n >= 2*f->depth)
+    }
+    else if (overflowable_count + n >= 2*f->depth)
     {
       // Double overflowed
       // re-position write index to have a full fifo after pushed

From 04a5c03ea8ea70510c332f0fafb44daf0ec7c7fb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Dec 2022 11:54:33 +0700
Subject: [PATCH 1297/2085] fix int conversion warnings

---
 src/common/tusb_fifo.c |  4 ++--
 src/common/tusb_fifo.h | 14 +++++++-------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index a3933416c..70f514df2 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -82,7 +82,7 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
   // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable
   // only if overflow happens once (important for unsupervised DMA applications)
   //f->max_pointer_idx = (uint16_t) (2*depth - 1);
-  f->non_used_index_space = UINT16_MAX - (2*f->depth-1);
+  f->non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1));
 
   f->rd_idx = f->wr_idx = 0;
 
@@ -867,7 +867,7 @@ bool tu_fifo_clear(tu_fifo_t *f)
 
   f->rd_idx = f->wr_idx = 0;
   //f->max_pointer_idx = (uint16_t) (2*f->depth-1);
-  f->non_used_index_space = UINT16_MAX - (2*f->depth-1);
+  f->non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1));
 
   _ff_unlock(f->mutex_wr);
   _ff_unlock(f->mutex_rd);
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index fd149b75c..932214c81 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -136,13 +136,13 @@ typedef struct
   void * ptr_wrap   ; ///< wrapped part start pointer
 } tu_fifo_buffer_info_t;
 
-#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \
-{                                                           \
-  .buffer               = _buffer,                          \
-  .depth                = _depth,                           \
-  .item_size            = sizeof(_type),                    \
-  .overwritable         = _overwritable,                    \
-  .non_used_index_space = UINT16_MAX - (2*(_depth)-1),      \
+#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable)        \
+{                                                                  \
+  .buffer               = _buffer,                                 \
+  .depth                = _depth,                                  \
+  .item_size            = sizeof(_type),                           \
+  .overwritable         = _overwritable,                           \
+  .non_used_index_space = (uint16_t)(UINT16_MAX - (2*(_depth)-1)), \
 }
 
 #define TU_FIFO_DEF(_name, _depth, _type, _overwritable)                      \

From 9e7e8908a34a4ef2a4b271b9d6b0598ed72e064f Mon Sep 17 00:00:00 2001
From: Louis Burda <quent.burda@gmail.com>
Date: Tue, 13 Dec 2022 11:00:03 +0100
Subject: [PATCH 1298/2085] Fix ifdefs for disabled uart stdio in rp2040 family

---
 hw/bsp/rp2040/family.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index f7ee56990..75328027b 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -115,7 +115,7 @@ void stdio_rtt_init(void)
 
 #endif
 
-#ifdef UART_DEV
+#if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
 static uart_inst_t *uart_inst;
 #endif
 
@@ -191,7 +191,7 @@ uint32_t board_button_read(void)
 
 int board_uart_read(uint8_t* buf, int len)
 {
-#ifdef UART_DEV
+#if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
   int count = 0;
   while ( (count < len) && uart_is_readable(uart_inst) )
   {
@@ -207,7 +207,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-#ifdef UART_DEV
+#if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
   char const* bufch = (char const*) buf;
   for(int i=0;i<len;i++) {
     uart_putc(uart_inst, bufch[i]);

From a05adfce86104c8ad217993db2707e1112918be3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Dec 2022 14:38:40 +0700
Subject: [PATCH 1299/2085] fix midi MS Header wTotalLength computation

---
 src/device/usbd.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/device/usbd.h b/src/device/usbd.h
index 118e53ce4..ad19d1045 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -293,7 +293,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* MIDI Streaming (MS) Interface */\
   9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 0, 2, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_MIDI_STREAMING, AUDIO_FUNC_PROTOCOL_CODE_UNDEF, 0,\
   /* MS Header */\
-  7, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(7 + (_numcables) * TUD_MIDI_DESC_JACK_LEN)
+  7, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(7 + (_numcables) * TUD_MIDI_DESC_JACK_LEN + 2 * TUD_MIDI_DESC_EP_LEN(_numcables))
 
 #define TUD_MIDI_JACKID_IN_EMB(_cablenum) \
   (uint8_t)(((_cablenum) - 1) * 4 + 1)
@@ -317,6 +317,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_OUT_EMB(_cablenum), 1, TUD_MIDI_JACKID_IN_EXT(_cablenum), 1, _stridx,\
   /* MS Out Jack (External), connected to In Jack Embedded */\
   9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_OUT_EXT(_cablenum), 1, TUD_MIDI_JACKID_IN_EMB(_cablenum), 1, _stridx
+
 #define TUD_MIDI_DESC_JACK(_cablenum) TUD_MIDI_DESC_JACK_DESC(_cablenum, 0)
 
 #define TUD_MIDI_DESC_EP_LEN(_numcables) (9 + 4 + (_numcables))

From 9f440e5c6946f46d2fa09af1f4c42768ac64ef78 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Thu, 15 Dec 2022 10:27:49 +0000
Subject: [PATCH 1300/2085] Update SDK for FT9xx to include 3rdparty sources

---
 hw/mcu/bridgetek/ft9xx/ft90x-sdk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/bridgetek/ft9xx/ft90x-sdk b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
index 0ea80ceaf..91060164a 160000
--- a/hw/mcu/bridgetek/ft9xx/ft90x-sdk
+++ b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
@@ -1 +1 @@
-Subproject commit 0ea80ceafdf32e4e496cacc94178417e2ef4bf9c
+Subproject commit 91060164afe239fcb394122e8bf9eb24d3194eb1

From 88e6da727370114b427287e74c3ade176c483b17 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Dec 2022 18:03:01 +0700
Subject: [PATCH 1301/2085] use OSAL_MUTEX_REQUIRED to replace
 CFG_FIFO_MUTEX/TUSB_OPT_MUTEX

add macro to swallow mutex API in order to simplify code with mutex
---
 src/class/cdc/cdc_device.c |  8 ++------
 src/common/tusb_fifo.h     | 19 ++++++++++--------
 src/common/tusb_mcu.h      |  4 ++++
 src/device/usbd.c          | 20 +++++++------------
 src/host/usbh.c            | 41 ++++++++++----------------------------
 src/osal/osal.h            | 25 ++++++++++++++---------
 src/osal/osal_none.h       | 12 +++++++++++
 src/tusb.c                 | 16 ++++-----------
 src/tusb_option.h          |  3 ---
 9 files changed, 67 insertions(+), 81 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 7b1e08d5d..0bbbaaa83 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -62,10 +62,8 @@ typedef struct
   uint8_t rx_ff_buf[CFG_TUD_CDC_RX_BUFSIZE];
   uint8_t tx_ff_buf[CFG_TUD_CDC_TX_BUFSIZE];
 
-#if CFG_FIFO_MUTEX
-  osal_mutex_def_t rx_ff_mutex;
-  osal_mutex_def_t tx_ff_mutex;
-#endif
+  OSAL_MUTEX_DEF(rx_ff_mutex);
+  OSAL_MUTEX_DEF(tx_ff_mutex);
 
   // Endpoint Transfer buffer
   CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
@@ -248,10 +246,8 @@ void cdcd_init(void)
     // In this way, the most current data is prioritized.
     tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true);
 
-#if CFG_FIFO_MUTEX
     tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, osal_mutex_create(&p_cdc->rx_ff_mutex));
     tu_fifo_config_mutex(&p_cdc->tx_ff, osal_mutex_create(&p_cdc->tx_ff_mutex), NULL);
-#endif
   }
 }
 
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index e64ab4b6d..e36e3a7f3 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -42,15 +42,13 @@ extern "C" {
 // within a certain number (see tu_fifo_overflow()).
 
 #include "common/tusb_common.h"
+#include "osal/osal.h"
+
+#define tu_fifo_mutex_t  osal_mutex_t
 
 // mutex is only needed for RTOS
 // for OS None, we don't get preempted
-#define CFG_FIFO_MUTEX      (CFG_TUSB_OS != OPT_OS_NONE)
-
-#if CFG_FIFO_MUTEX
-#include "osal/osal.h"
-#define tu_fifo_mutex_t  osal_mutex_t
-#endif
+#define CFG_FIFO_MUTEX      OSAL_MUTEX_REQUIRED
 
 typedef struct
 {
@@ -65,7 +63,7 @@ typedef struct
   volatile uint16_t wr_idx      ; ///< write pointer
   volatile uint16_t rd_idx      ; ///< read pointer
 
-#if CFG_FIFO_MUTEX
+#if OSAL_MUTEX_REQUIRED
   tu_fifo_mutex_t mutex_wr;
   tu_fifo_mutex_t mutex_rd;
 #endif
@@ -99,13 +97,18 @@ bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable);
 bool tu_fifo_clear(tu_fifo_t *f);
 bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable);
 
-#if CFG_FIFO_MUTEX
+#if OSAL_MUTEX_REQUIRED
 TU_ATTR_ALWAYS_INLINE static inline
 void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t write_mutex_hdl, tu_fifo_mutex_t read_mutex_hdl)
 {
   f->mutex_wr = write_mutex_hdl;
   f->mutex_rd = read_mutex_hdl;
 }
+
+#else
+
+#define tu_fifo_config_mutex(_f, _wr_mutex, _rd_mutex)
+
 #endif
 
 bool     tu_fifo_write                  (tu_fifo_t* f, void const * p_data);
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 86c68baf8..bb4225ad5 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -281,6 +281,10 @@
 // Default Values
 //--------------------------------------------------------------------+
 
+#ifndef TUP_MCU_MULTIPLE_CORE
+#define TUP_MCU_MULTIPLE_CORE 0
+#endif
+
 #ifndef TUP_DCD_ENDPOINT_MAX
   #warning "TUP_DCD_ENDPOINT_MAX is not defined for this MCU, default to 8"
   #define TUP_DCD_ENDPOINT_MAX    8
diff --git a/src/device/usbd.c b/src/device/usbd.c
index c199e647e..f9a7af21b 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -272,10 +272,12 @@ static uint8_t _usbd_rhport = RHPORT_INVALID;
 OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
 static osal_queue_t _usbd_q;
 
-// Mutex for claiming endpoint, only needed when using with preempted RTOS
-#if CFG_TUSB_OS != OPT_OS_NONE
-static osal_mutex_def_t _ubsd_mutexdef;
-static osal_mutex_t _usbd_mutex;
+// Mutex for claiming endpoint
+#if OSAL_MUTEX_REQUIRED
+  static osal_mutex_def_t _ubsd_mutexdef;
+  static osal_mutex_t _usbd_mutex;
+#else
+  #define _usbd_mutex   NULL
 #endif
 
 
@@ -389,7 +391,7 @@ bool tud_init (uint8_t rhport)
 
   tu_varclr(&_usbd_dev);
 
-#if CFG_TUSB_OS != OPT_OS_NONE
+#if OSAL_MUTEX_REQUIRED
   // Init device mutex
   _usbd_mutex = osal_mutex_create(&_ubsd_mutexdef);
   TU_ASSERT(_usbd_mutex);
@@ -1209,11 +1211,7 @@ bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr)
   uint8_t const dir         = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir];
 
-#if TUSB_OPT_MUTEX
   return tu_edpt_claim(ep_state, _usbd_mutex);
-#else
-  return tu_edpt_claim(ep_state, NULL);
-#endif
 }
 
 bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr)
@@ -1224,11 +1222,7 @@ bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr)
   uint8_t const dir         = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &_usbd_dev.ep_status[epnum][dir];
 
-#if TUSB_OPT_MUTEX
   return tu_edpt_release(ep_state, _usbd_mutex);
-#else
-  return tu_edpt_release(ep_state, NULL);
-#endif
 }
 
 bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 9065e5241..ff8fbaef3 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -212,28 +212,12 @@ static usbh_dev0_t _dev0;
 // TODO: hub can has its own simpler struct to save memory
 CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[TOTAL_DEVICES];
 
-// Mutex for claiming endpoint, only needed when using with preempted RTOS
-#if TUSB_OPT_MUTEX
-static osal_mutex_def_t _usbh_mutexdef;
-static osal_mutex_t _usbh_mutex;
-
-TU_ATTR_ALWAYS_INLINE static inline void usbh_lock(void)
-{
-  osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline void usbh_unlock(void)
-{
-  osal_mutex_unlock(_usbh_mutex);
-}
-
+// Mutex for claiming endpoint
+#if OSAL_MUTEX_REQUIRED
+  static osal_mutex_def_t _usbh_mutexdef;
+  static osal_mutex_t _usbh_mutex;
 #else
-
-#define _usbh_mutex   NULL
-
-#define usbh_lock()
-#define usbh_unlock()
-
+  #define _usbh_mutex   NULL
 #endif
 
 // Event queue
@@ -277,8 +261,6 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
 // TODO rework time-related function later
 void osal_task_delay(uint32_t msec)
 {
-  (void) msec;
-
   const uint32_t start = hcd_frame_number(_usbh_controller);
   while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}
 }
@@ -352,8 +334,8 @@ bool tuh_init(uint8_t controller_id)
   _usbh_q = osal_queue_create( &_usbh_qdef );
   TU_ASSERT(_usbh_q != NULL);
 
-#if TUSB_OPT_MUTEX
-  // Mutex
+#if OSAL_MUTEX_REQUIRED
+  // Init mutex
   _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
   TU_ASSERT(_usbh_mutex);
 #endif
@@ -537,8 +519,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
 
   uint8_t const daddr = xfer->daddr;
 
-  // TODO probably better to use semaphore as resource management than mutex
-  usbh_lock();
+  (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
   if (is_idle)
@@ -553,7 +534,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
     _ctrl_xfer.user_data   = xfer->user_data;
   }
 
-  usbh_unlock();
+  (void) osal_mutex_unlock(_usbh_mutex);
 
   TU_VERIFY(is_idle);
   const uint8_t rhport = usbh_get_rhport(daddr);
@@ -597,9 +578,9 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
 
 TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
 {
-  usbh_lock();
+  osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
   _ctrl_xfer.stage = stage;
-  usbh_unlock();
+  osal_mutex_unlock(_usbh_mutex);
 }
 
 static void _xfer_complete(uint8_t daddr, xfer_result_t result)
diff --git a/src/osal/osal.h b/src/osal/osal.h
index 9d11866df..9cdab2882 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -33,17 +33,24 @@
 
 #include "common/tusb_common.h"
 
-// Return immediately
-#define OSAL_TIMEOUT_NOTIMEOUT     (0)
-// Default timeout
-#define OSAL_TIMEOUT_NORMAL        (10)
-// Wait forever
-#define OSAL_TIMEOUT_WAIT_FOREVER  (UINT32_MAX)
-
-#define OSAL_TIMEOUT_CONTROL_XFER  OSAL_TIMEOUT_WAIT_FOREVER
-
 typedef void (*osal_task_func_t)( void * );
 
+// Timeout
+#define OSAL_TIMEOUT_NOTIMEOUT     (0)          // Return immediately
+#define OSAL_TIMEOUT_NORMAL        (10)         // Default timeout
+#define OSAL_TIMEOUT_WAIT_FOREVER  (UINT32_MAX) // Wait forever
+#define OSAL_TIMEOUT_CONTROL_XFER  OSAL_TIMEOUT_WAIT_FOREVER
+
+// Mutex is required when using a preempted RTOS or MCU has multiple cores
+#if (CFG_TUSB_OS == OPT_OS_NONE) && !TUP_MCU_MULTIPLE_CORE
+  #define OSAL_MUTEX_REQUIRED   0
+  #define OSAL_MUTEX_DEF(_name)
+#else
+  #define OSAL_MUTEX_REQUIRED   1
+  #define OSAL_MUTEX_DEF(_name) osal_mutex_def_t _name
+#endif
+
+// OS thin implementation
 #if CFG_TUSB_OS == OPT_OS_NONE
   #include "osal_none.h"
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 9c80e4548..1ad130557 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -82,6 +82,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t s
 typedef osal_semaphore_def_t osal_mutex_def_t;
 typedef osal_semaphore_t osal_mutex_t;
 
+#if OSAL_MUTEX_REQUIRED
+// Note: multiple cores MCUs usually do provide IPC API for mutex
+// or we can use std atomic function
+
 TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
 {
   mdef->count = 1;
@@ -98,6 +102,14 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
   return osal_semaphore_post(mutex_hdl, false);
 }
 
+#else
+
+#define osal_mutex_create(_mdef)          (NULL)
+#define osal_mutex_lock(_mutex_hdl, _ms)  (true)
+#define osal_mutex_unlock(_mutex_hdl)     (true)
+
+#endif
+
 //--------------------------------------------------------------------+
 // QUEUE API
 //--------------------------------------------------------------------+
diff --git a/src/tusb.c b/src/tusb.c
index c3787ff8f..f4380f89c 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -74,11 +74,9 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
 {
   (void) mutex;
 
-#if TUSB_OPT_MUTEX
   // pre-check to help reducing mutex lock
   TU_VERIFY((ep_state->busy == 0) && (ep_state->claimed == 0));
-  osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-#endif
+  (void) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   // can only claim the endpoint if it is not busy and not claimed yet.
   bool const available = (ep_state->busy == 0) && (ep_state->claimed == 0);
@@ -87,9 +85,7 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
     ep_state->claimed = 1;
   }
 
-#if TUSB_OPT_MUTEX
-  osal_mutex_unlock(mutex);
-#endif
+  (void) osal_mutex_unlock(mutex);
 
   return available;
 }
@@ -98,9 +94,7 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
 {
   (void) mutex;
 
-#if TUSB_OPT_MUTEX
-  osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-#endif
+  (void) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   // can only release the endpoint if it is claimed and not busy
   bool const ret = (ep_state->claimed == 1) && (ep_state->busy == 0);
@@ -109,9 +103,7 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
     ep_state->claimed = 0;
   }
 
-#if TUSB_OPT_MUTEX
-  osal_mutex_unlock(mutex);
-#endif
+  (void) osal_mutex_unlock(mutex);
 
   return ret;
 }
diff --git a/src/tusb_option.h b/src/tusb_option.h
index f95ae6273..9ca6c794b 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -299,9 +299,6 @@ typedef int make_iso_compilers_happy;
   #define CFG_TUSB_OS_INC_PATH
 #endif
 
-// mutex is only needed for RTOS TODO also required with multiple core MCUs
-#define TUSB_OPT_MUTEX      (CFG_TUSB_OS != OPT_OS_NONE)
-
 //--------------------------------------------------------------------
 // Device Options (Default)
 //--------------------------------------------------------------------

From 96d2be905ba331419a34a64bba6baaaf006ae26f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Dec 2022 18:47:54 +0700
Subject: [PATCH 1302/2085] fix build with usbtmc

---
 src/class/usbtmc/usbtmc_device.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 122b3f3cf..07c7c28a6 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -157,12 +157,12 @@ static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t pack
 static uint8_t termChar;
 static uint8_t termCharRequested = false;
 
-osal_mutex_def_t usbtmcLockBuffer;
+OSAL_MUTEX_DEF(usbtmcLockBuffer);
 static osal_mutex_t usbtmcLock;
 
 // Our own private lock, mostly for the state variable.
-#define criticalEnter() do {osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0)
-#define criticalLeave() do {osal_mutex_unlock(usbtmcLock); } while (0)
+#define criticalEnter() do { (void) osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0)
+#define criticalLeave() do { (void) osal_mutex_unlock(usbtmcLock); } while (0)
 
 bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_enum newState)
 {

From 1e99480ad28808a29938673d5b05d9461da5d1c1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Dec 2022 15:19:40 +0700
Subject: [PATCH 1303/2085] fix ci with usbh and unit test

---
 src/host/usbh.c                                  | 4 ++--
 test/unit-test/test/device/msc/test_msc_device.c | 1 +
 test/unit-test/test/device/usbd/test_usbd.c      | 1 +
 test/unit-test/test/test_fifo.c                  | 4 +++-
 4 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index ff8fbaef3..ca42a523c 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -578,9 +578,9 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
 
 TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
 {
-  osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+  (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
   _ctrl_xfer.stage = stage;
-  osal_mutex_unlock(_usbh_mutex);
+  (void) osal_mutex_unlock(_usbh_mutex);
 }
 
 static void _xfer_complete(uint8_t daddr, xfer_result_t result)
diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c
index 00bb86ccf..63684e76a 100644
--- a/test/unit-test/test/device/msc/test_msc_device.c
+++ b/test/unit-test/test/device/msc/test_msc_device.c
@@ -28,6 +28,7 @@
 #include "unity.h"
 
 // Files to test
+#include "osal/osal.h"
 #include "tusb_fifo.h"
 #include "tusb.h"
 #include "usbd.h"
diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c
index c90383b57..ad95eb47a 100644
--- a/test/unit-test/test/device/usbd/test_usbd.c
+++ b/test/unit-test/test/device/usbd/test_usbd.c
@@ -25,6 +25,7 @@
 #include "unity.h"
 
 // Files to test
+#include "osal/osal.h"
 #include "tusb_fifo.h"
 #include "tusb.h"
 #include "usbd.h"
diff --git a/test/unit-test/test/test_fifo.c b/test/unit-test/test/test_fifo.c
index 0a5f4d3b9..1d87081bb 100644
--- a/test/unit-test/test/test_fifo.c
+++ b/test/unit-test/test/test_fifo.c
@@ -26,6 +26,8 @@
 
 #include <string.h>
 #include "unity.h"
+
+#include "osal/osal.h"
 #include "tusb_fifo.h"
 
 #define FIFO_SIZE 10
@@ -315,4 +317,4 @@ void test_rd_idx_wrap()
   n = tu_fifo_read_n(&ff10, dst, 4);
   TEST_ASSERT_EQUAL(n, 2);
   TEST_ASSERT_EQUAL(ff10.rd_idx, 6);
-}
\ No newline at end of file
+}

From 660343d2001c0ee943bf3e24cab6f235d3930b33 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Dec 2022 16:55:25 +0700
Subject: [PATCH 1304/2085] update fifo per PanRe review

---
 src/common/tusb_fifo.c | 8 ++++++--
 src/common/tusb_fifo.h | 7 ++++---
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 70f514df2..bbdd82982 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -352,9 +352,10 @@ static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
   return new_p;
 }
 
-// index to pointer, simply an modulo with minus
+// index to pointer, simply an modulo with minus.
 static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth)
 {
+  // Only run at most 3 times since index is limit in the range of [0..2*depth)
   while ( idx >= depth ) idx -= depth;
   return idx;
 }
@@ -509,6 +510,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
     else if (overflowable_count + n >= 2*f->depth)
     {
       // Double overflowed
+      // Index is bigger than the allowed range [0,2*depth)
       // re-position write index to have a full fifo after pushed
       wr_idx = advance_pointer(f, rd_idx, f->depth - n);
 
@@ -518,7 +520,9 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
       // currently deliberately not implemented --> result in incorrect data read back
     }else
     {
-      // normal + single overflowed: just increase write index
+      // normal + single overflowed:
+      // Index is in the range of [0,2*depth) and thus detect and recoverable. Recovering is handled in read()
+      // Therefore we just increase write index
       // we will correct (re-position) read index later on in fifo_read() function
     }
   }
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index 932214c81..972d29d50 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -54,7 +54,7 @@ extern "C" {
 
 /* Write/Read index is always in the range of:
  *      0 .. 2*depth-1
- * The extra window allow us to determine the fifo state of empty or full with only 2 indexes
+ * The extra window allow us to determine the fifo state of empty or full with only 2 indices
  * Following are examples with depth = 3
  *
  * - empty: W = R
@@ -86,7 +86,8 @@ extern "C" {
  *      -------------------------
  *      | R | 1 | 2 | 3 | W | 5 |
  *
- *  - Double Overflowed: write(3), write(1), write(2)
+ *  - Double Overflowed i.e index is out of allowed range [0,2*depth) e.g:
+ *      write(3), write(1), write(2)
  *    Continue to write after overflowed to 2nd overflowed.
  *    We must prevent 2nd overflowed since it will cause incorrect computed of count, in above example
  *    if not handled the fifo will be empty instead of continue-to-be full. Since we must not modify
@@ -94,7 +95,7 @@ extern "C" {
  *    after data is written it is a full fifo i.e W = depth - R
  *
  *      re-position W = 1 before write(2)
- *      Note: we should also move data from mem[4] to read index as well, but deliberately skipped here
+ *      Note: we should also move data from mem[3] to read index as well, but deliberately skipped here
  *      since it is an expensive operation !!!
  *                  |
  *      -------------------------

From 4f0369508450883504e377b40aaec8860c8cb256 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Dec 2022 16:52:28 +0700
Subject: [PATCH 1305/2085] adding tuh_cdc_mount_cb/tuh_cdc_umount_cb

start adding cdc_app.c to example
---
 examples/host/cdc_msc_hid/CMakeLists.txt |  3 +-
 examples/host/cdc_msc_hid/Makefile       |  3 +-
 examples/host/cdc_msc_hid/src/cdc_app.c  | 51 ++++++++++++++++++++++++
 examples/host/cdc_msc_hid/src/main.c     | 11 ++---
 src/class/cdc/cdc_host.c                 | 12 ++++++
 src/class/cdc/cdc_host.h                 | 17 +++++---
 6 files changed, 81 insertions(+), 16 deletions(-)
 create mode 100644 examples/host/cdc_msc_hid/src/cdc_app.c

diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index d84457bc9..2e89817a5 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -14,8 +14,9 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
         ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
         ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
         )
 
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index ad28076a0..9adccfa3a 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -7,7 +7,8 @@ INC += \
 
 # Example source
 EXAMPLE_SOURCE = \
-	src/hid_app.c \
+  src/cdc_app.c \
+  src/hid_app.c \
   src/main.c \
   src/msc_app.c \
 
diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
new file mode 100644
index 000000000..29da02abc
--- /dev/null
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -0,0 +1,51 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+
+//------------- IMPLEMENTATION -------------//
+
+void cdc_app_task(void)
+{
+
+}
+
+void tuh_cdc_mount_cb(uint8_t dev_addr)
+{
+  (void) dev_addr;
+  printf("A CDC device is mounted\r\n");
+}
+
+void tuh_cdc_umount_cb(uint8_t dev_addr)
+{
+  (void) dev_addr;
+  printf("A CDC device is unmounted\r\n");
+}
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index d26e41e8d..465e457f7 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -35,7 +35,7 @@
 //--------------------------------------------------------------------+
 void led_blinking_task(void);
 
-extern void cdc_task(void);
+extern void cdc_app_task(void);
 extern void hid_app_task(void);
 
 /*------------- MAIN -------------*/
@@ -52,9 +52,9 @@ int main(void)
   {
     // tinyusb host task
     tuh_task();
-    led_blinking_task();
 
-    cdc_task();
+    led_blinking_task();
+    cdc_app_task();
     hid_app_task();
   }
 
@@ -79,11 +79,6 @@ void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_i
   tuh_cdc_receive(dev_addr, serial_in_buffer, sizeof(serial_in_buffer), true); // waiting for next data
 }
 
-void cdc_task(void)
-{
-
-}
-
 //--------------------------------------------------------------------+
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index ee824cb4e..aa3a7e1e5 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -239,6 +239,8 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
 bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
   (void) dev_addr; (void) itf_num;
+
+  if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(dev_addr);
   return true;
 }
 
@@ -254,6 +256,16 @@ void cdch_close(uint8_t dev_addr)
   TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
 
   cdch_data_t * p_cdc = get_itf(dev_addr);
+
+  // Invoke application callback
+  if (tuh_cdc_umount_cb)
+  {
+    if (p_cdc->ep_out || p_cdc->ep_in || p_cdc->ep_notif)
+    {
+      tuh_cdc_umount_cb(dev_addr);
+    }
+  }
+
   tu_memclr(p_cdc, sizeof(cdch_data_t));
 }
 
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 33dbd2efb..c3b601b34 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -34,13 +34,18 @@
 #endif
 
 //--------------------------------------------------------------------+
-// CDC APPLICATION PUBLIC API
+// Application API
 //--------------------------------------------------------------------+
-/** \ingroup ClassDriver_CDC Communication Device Class (CDC)
- * \addtogroup CDC_Serial Serial
- * @{
- * \defgroup   CDC_Serial_Host Host
- * @{ */
+
+
+//------------- Application Callback -------------//
+
+// Invoked when a device with CDC interface is mounted
+TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t dev_addr);
+
+// Invoked when a device with CDC interface is unmounted
+TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t dev_addr);
+
 
 bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb);
 

From f0c51eae44e4cd8f38fdba6469e49b1d98100d7c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Dec 2022 17:35:01 +0700
Subject: [PATCH 1306/2085] cdc check for bNumEndpoints before checking for
 endpoint descriptor

---
 src/class/cdc/cdc_host.c | 64 ++++++++++++++++++++++------------------
 src/host/usbh.c          |  3 +-
 2 files changed, 36 insertions(+), 31 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index aa3a7e1e5..83fa1bf5e 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -152,13 +152,43 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xf
 }
 
 //--------------------------------------------------------------------+
-// USBH-CLASS DRIVER API
+// CLASS-USBH API
 //--------------------------------------------------------------------+
+
 void cdch_init(void)
 {
   tu_memclr(cdch_data, sizeof(cdch_data));
 }
 
+void cdch_close(uint8_t dev_addr)
+{
+  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
+
+  cdch_data_t * p_cdc = get_itf(dev_addr);
+
+  // Invoke application callback
+  if (tuh_cdc_umount_cb)
+  {
+    if (p_cdc->ep_out || p_cdc->ep_in || p_cdc->ep_notif)
+    {
+      tuh_cdc_umount_cb(dev_addr);
+    }
+  }
+
+  tu_memclr(p_cdc, sizeof(cdch_data_t));
+}
+
+bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
+{
+  (void) ep_addr;
+  tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes );
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// Enumeration
+//--------------------------------------------------------------------+
+
 bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
   (void) rhport;
@@ -175,7 +205,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
   p_cdc->itf_num      = itf_desc->bInterfaceNumber;
   p_cdc->itf_protocol = itf_desc->bInterfaceProtocol;
 
-  //------------- Communication Interface -------------//
+  //------------- Control Interface -------------//
   uint16_t drv_len = tu_desc_len(itf_desc);
   uint8_t const * p_desc = tu_desc_next(itf_desc);
 
@@ -192,9 +222,10 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
     p_desc = tu_desc_next(p_desc);
   }
 
-  if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
+  // Open notification endpoint of control interface if any
+  if (itf_desc->bNumEndpoints == 1)
   {
-    // notification endpoint
+    TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc));
     tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
 
     TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) );
@@ -244,29 +275,4 @@ bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
   return true;
 }
 
-bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
-{
-  (void) ep_addr;
-  tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes );
-  return true;
-}
-
-void cdch_close(uint8_t dev_addr)
-{
-  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
-
-  cdch_data_t * p_cdc = get_itf(dev_addr);
-
-  // Invoke application callback
-  if (tuh_cdc_umount_cb)
-  {
-    if (p_cdc->ep_out || p_cdc->ep_in || p_cdc->ep_notif)
-    {
-      tuh_cdc_umount_cb(dev_addr);
-    }
-  }
-
-  tu_memclr(p_cdc, sizeof(cdch_data_t));
-}
-
 #endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index ca42a523c..b0cd62bac 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1524,8 +1524,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
     // Find driver for this interface
-    uint8_t drv_id;
-    for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+    for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
     {
       usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
 

From f62f97395626f316f1670f1777a0a75877e8e773 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Dec 2022 23:19:47 +0700
Subject: [PATCH 1307/2085] minor rename

---
 src/class/cdc/cdc_host.c | 51 +++++++++++++++++++++++++++++++++-------
 src/class/cdc/cdc_host.h | 26 +++++++++++++++-----
 src/class/hid/hid_host.c |  1 +
 src/tusb_option.h        |  4 ++++
 4 files changed, 67 insertions(+), 15 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 83fa1bf5e..9678b756c 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -37,6 +37,7 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 typedef struct {
+  // uint8_t daddr;
   uint8_t itf_num;
   uint8_t itf_protocol;
 
@@ -46,21 +47,42 @@ typedef struct {
 
   cdc_acm_capability_t acm_capability;
 
-} cdch_data_t;
+  // Bit 0:  DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
+  // uint8_t line_state;
+#if 0
+
+  // FIFO
+  tu_fifo_t rx_ff;
+  tu_fifo_t tx_ff;
+
+  uint8_t rx_ff_buf[CFG_TUH_CDC_RX_BUFSIZE];
+  uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
+
+#if CFG_FIFO_MUTEX
+  osal_mutex_def_t rx_ff_mutex;
+  osal_mutex_def_t tx_ff_mutex;
+#endif
+
+  // Endpoint Transfer buffer
+  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUH_CDC_EP_BUFSIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUH_CDC_EP_BUFSIZE];
+#endif
+
+} cdch_interface_t;
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-static cdch_data_t cdch_data[CFG_TUH_DEVICE_MAX];
+static cdch_interface_t cdch_data[CFG_TUH_DEVICE_MAX];
 
-static inline cdch_data_t* get_itf(uint8_t dev_addr)
+static inline cdch_interface_t* get_itf(uint8_t dev_addr)
 {
   return &cdch_data[dev_addr-1];
 }
 
 bool tuh_cdc_mounted(uint8_t dev_addr)
 {
-  cdch_data_t* cdc = get_itf(dev_addr);
+  cdch_interface_t* cdc = get_itf(dev_addr);
   return cdc->ep_in && cdc->ep_out;
 }
 
@@ -68,7 +90,7 @@ bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid)
 {
   if ( !tuh_cdc_mounted(dev_addr) ) return false;
 
-  cdch_data_t const * p_cdc = get_itf(dev_addr);
+  cdch_interface_t const * p_cdc = get_itf(dev_addr);
 
   switch (pipeid)
   {
@@ -89,6 +111,17 @@ bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid)
 //--------------------------------------------------------------------+
 // APPLICATION API (parameter validation needed)
 //--------------------------------------------------------------------+
+
+uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize)
+{
+  (void) dev_addr;
+  (void) buffer;
+  (void) bufsize;
+
+  return 0;
+}
+
+
 bool tuh_cdc_serial_is_mounted(uint8_t dev_addr)
 {
   // TODO consider all AT Command as serial candidate
@@ -122,7 +155,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
 
 bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb)
 {
-  cdch_data_t const * p_cdc = get_itf(dev_addr);
+  cdch_interface_t const * p_cdc = get_itf(dev_addr);
 
   tusb_control_request_t const request =
   {
@@ -164,7 +197,7 @@ void cdch_close(uint8_t dev_addr)
 {
   TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
 
-  cdch_data_t * p_cdc = get_itf(dev_addr);
+  cdch_interface_t * p_cdc = get_itf(dev_addr);
 
   // Invoke application callback
   if (tuh_cdc_umount_cb)
@@ -175,7 +208,7 @@ void cdch_close(uint8_t dev_addr)
     }
   }
 
-  tu_memclr(p_cdc, sizeof(cdch_data_t));
+  tu_memclr(p_cdc, sizeof(cdch_interface_t));
 }
 
 bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
@@ -200,7 +233,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
              CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass &&
              0xFF                                     != itf_desc->bInterfaceProtocol);
 
-  cdch_data_t * p_cdc = get_itf(dev_addr);
+  cdch_interface_t * p_cdc = get_itf(dev_addr);
 
   p_cdc->itf_num      = itf_desc->bInterfaceNumber;
   p_cdc->itf_protocol = itf_desc->bInterfaceProtocol;
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index c3b601b34..ce1f0f309 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -34,19 +34,24 @@
 #endif
 
 //--------------------------------------------------------------------+
-// Application API
+// Class Driver Configuration
 //--------------------------------------------------------------------+
 
 
-//------------- Application Callback -------------//
+//--------------------------------------------------------------------+
+// Application API
+//--------------------------------------------------------------------+
 
-// Invoked when a device with CDC interface is mounted
-TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t dev_addr);
+bool tuh_cdc_mounted(uint8_t dev_addr);
 
-// Invoked when a device with CDC interface is unmounted
-TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t dev_addr);
+uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize);
+//uint32_t tuh_cdc_read(uint8_t dev_addr, void* buffer, uint32_t bufsize);
 
+//--------------------------------------------------------------------+
+// Control Endpoint (Request) API
+//--------------------------------------------------------------------+
 
+// Set Control Line State (DTR, RTS)
 bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb);
 
 static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_xfer_cb_t complete_cb)
@@ -59,6 +64,15 @@ static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_xfer_cb_t complete_c
   return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb);
 }
 
+//------------- Application Callback -------------//
+
+// Invoked when a device with CDC interface is mounted
+TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t dev_addr);
+
+// Invoked when a device with CDC interface is unmounted
+TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t dev_addr);
+
+
 /** \brief 			Check if device support CDC Serial interface or not
  * \param[in]		dev_addr	device address
  * \retval      true if device supports
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index ca745464c..504ddca1e 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -62,6 +62,7 @@ typedef struct
   hidh_interface_t instances[CFG_TUH_HID];
 } hidh_device_t;
 
+CFG_TUSB_MEM_SECTION
 static hidh_device_t _hidh_dev[CFG_TUH_DEVICE_MAX];
 
 //------------- Internal prototypes -------------//
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 9ca6c794b..69972c630 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -256,6 +256,10 @@ typedef int make_iso_compilers_happy;
 // For backward compatible
 #define TUSB_OPT_HOST_ENABLED   CFG_TUH_ENABLED
 
+// highspeed support indicator
+#define TUH_OPT_HIGH_SPEED    (CFG_TUH_MAX_SPEED ? (CFG_TUH_MAX_SPEED & OPT_MODE_HIGH_SPEED) : TUP_RHPORT_HIGHSPEED)
+
+
 //--------------------------------------------------------------------+
 // TODO move later
 //--------------------------------------------------------------------+

From bd1f7f86ce1b6e82c3942d545e984b74b050004e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Dec 2022 15:27:39 +0700
Subject: [PATCH 1308/2085] add common EPSIZE for bulk/iso in full and
 highspeed

adding cdc host fifo tx/rx
---
 src/class/cdc/cdc_device.h  |  1 -
 src/class/cdc/cdc_host.c    | 79 +++++++++++++++++--------------------
 src/class/cdc/cdc_host.h    | 19 +++++++++
 src/common/tusb_types.h     | 10 ++++-
 src/host/usbh_classdriver.h |  4 ++
 5 files changed, 68 insertions(+), 45 deletions(-)

diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index fbc7162a3..f625a7554 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -27,7 +27,6 @@
 #ifndef _TUSB_CDC_DEVICE_H_
 #define _TUSB_CDC_DEVICE_H_
 
-#include "common/tusb_common.h"
 #include "cdc.h"
 
 //--------------------------------------------------------------------+
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 9678b756c..da8ad726b 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -37,7 +37,7 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 typedef struct {
-  // uint8_t daddr;
+  uint8_t daddr;
   uint8_t itf_num;
   uint8_t itf_protocol;
 
@@ -49,7 +49,6 @@ typedef struct {
 
   // Bit 0:  DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
   // uint8_t line_state;
-#if 0
 
   // FIFO
   tu_fifo_t rx_ff;
@@ -64,54 +63,48 @@ typedef struct {
 #endif
 
   // Endpoint Transfer buffer
-  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUH_CDC_EP_BUFSIZE];
-  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUH_CDC_EP_BUFSIZE];
-#endif
+  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUH_CDC_RX_EPSIZE];
+  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUH_CDC_TX_EPSIZE];
 
 } cdch_interface_t;
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-static cdch_interface_t cdch_data[CFG_TUH_DEVICE_MAX];
+
+CFG_TUSB_MEM_SECTION
+static cdch_interface_t cdch_data[CFG_TUH_CDC];
 
 static inline cdch_interface_t* get_itf(uint8_t dev_addr)
 {
-  return &cdch_data[dev_addr-1];
-}
-
-bool tuh_cdc_mounted(uint8_t dev_addr)
-{
-  cdch_interface_t* cdc = get_itf(dev_addr);
-  return cdc->ep_in && cdc->ep_out;
-}
-
-bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid)
-{
-  if ( !tuh_cdc_mounted(dev_addr) ) return false;
-
-  cdch_interface_t const * p_cdc = get_itf(dev_addr);
-
-  switch (pipeid)
+  for(size_t i=0; i<CFG_TUH_CDC; i++)
   {
-    case CDC_PIPE_NOTIFICATION:
-      return usbh_edpt_busy(dev_addr, p_cdc->ep_notif );
-
-    case CDC_PIPE_DATA_IN:
-      return usbh_edpt_busy(dev_addr, p_cdc->ep_in );
-
-    case CDC_PIPE_DATA_OUT:
-      return usbh_edpt_busy(dev_addr, p_cdc->ep_out );
-
-    default:
-      return false;
+    if (cdch_data[i].daddr == dev_addr) return &cdch_data[i];
   }
+
+  return NULL;
+}
+
+static cdch_interface_t* find_new_itf(void)
+{
+  for(size_t i=0; i<CFG_TUH_CDC; i++)
+  {
+    if (cdch_data[i].daddr == 0) return &cdch_data[i];
+  }
+
+  return NULL;
 }
 
 //--------------------------------------------------------------------+
 // APPLICATION API (parameter validation needed)
 //--------------------------------------------------------------------+
 
+bool tuh_cdc_mounted(uint8_t dev_addr)
+{
+  cdch_interface_t* p_cdc = get_itf(dev_addr);
+  return p_cdc != NULL;
+}
+
 uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize)
 {
   (void) dev_addr;
@@ -121,7 +114,6 @@ uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize)
   return 0;
 }
 
-
 bool tuh_cdc_serial_is_mounted(uint8_t dev_addr)
 {
   // TODO consider all AT Command as serial candidate
@@ -156,6 +148,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
 bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb)
 {
   cdch_interface_t const * p_cdc = get_itf(dev_addr);
+  TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request);
 
   tusb_control_request_t const request =
   {
@@ -195,17 +188,13 @@ void cdch_init(void)
 
 void cdch_close(uint8_t dev_addr)
 {
-  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
-
   cdch_interface_t * p_cdc = get_itf(dev_addr);
+  TU_VERIFY(p_cdc, );
 
   // Invoke application callback
   if (tuh_cdc_umount_cb)
   {
-    if (p_cdc->ep_out || p_cdc->ep_in || p_cdc->ep_notif)
-    {
-      tuh_cdc_umount_cb(dev_addr);
-    }
+    tuh_cdc_umount_cb(dev_addr);
   }
 
   tu_memclr(p_cdc, sizeof(cdch_interface_t));
@@ -233,8 +222,10 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
              CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass &&
              0xFF                                     != itf_desc->bInterfaceProtocol);
 
-  cdch_interface_t * p_cdc = get_itf(dev_addr);
+  cdch_interface_t * p_cdc = find_new_itf();
+  TU_VERIFY(p_cdc);
 
+  p_cdc->daddr        = dev_addr;
   p_cdc->itf_num      = itf_desc->bInterfaceNumber;
   p_cdc->itf_protocol = itf_desc->bInterfaceProtocol;
 
@@ -302,9 +293,11 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
 
 bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
 {
-  (void) dev_addr; (void) itf_num;
-
   if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(dev_addr);
+
+  // notify usbh that driver enumeration is complete
+  usbh_driver_set_config_complete(dev_addr, itf_num);
+
   return true;
 }
 
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index ce1f0f309..b2e75902d 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -37,6 +37,25 @@
 // Class Driver Configuration
 //--------------------------------------------------------------------+
 
+// RX FIFO size
+#ifndef CFG_TUH_CDC_RX_BUFSIZE
+#define CFG_TUH_CDC_RX_BUFSIZE USBH_EPSIZE_BULK_MAX
+#endif
+
+// RX Endpoint size
+#ifndef CFG_TUH_CDC_RX_EPSIZE
+#define CFG_TUH_CDC_RX_EPSIZE USBH_EPSIZE_BULK_MAX
+#endif
+
+// TX FIFO size
+#ifndef CFG_TUH_CDC_TX_BUFSIZE
+#define CFG_TUH_CDC_TX_BUFSIZE USBH_EPSIZE_BULK_MAX
+#endif
+
+// TX Endpoint size
+#ifndef CFG_TUH_CDC_TX_EPSIZE
+#define CFG_TUH_CDC_TX_EPSIZE USBH_EPSIZE_BULK_MAX
+#endif
 
 //--------------------------------------------------------------------+
 // Application API
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 1bfa7c7d1..c4c9d4133 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -69,6 +69,15 @@ typedef enum
   TUSB_DIR_IN_MASK = 0x80
 }tusb_dir_t;
 
+enum
+{
+  TUSB_EPSIZE_BULK_FS = 64,
+  TUSB_EPSIZE_BULK_HS= 512,
+
+  TUSB_EPSIZE_ISO_FS_MAX = 1023,
+  TUSB_EPSIZE_ISO_HS_MAX = 1024,
+};
+
 /// Isochronous End Point Attributes
 typedef enum
 {
@@ -243,7 +252,6 @@ enum
   INTERFACE_INVALID_NUMBER = 0xff
 };
 
-
 typedef enum
 {
   MS_OS_20_SET_HEADER_DESCRIPTOR       = 0x00,
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index c156afea0..7f72560c3 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -34,6 +34,10 @@
  extern "C" {
 #endif
 
+enum {
+  USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
+};
+
 //--------------------------------------------------------------------+
 // Class Driver API
 //--------------------------------------------------------------------+

From 4811b3463ff20fb6eee551b42d66a6e74b411746 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Dec 2022 17:16:19 +0700
Subject: [PATCH 1309/2085] stub

---
 src/class/cdc/cdc_host.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index da8ad726b..cb0794fa3 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -36,6 +36,14 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
+
+//typedef struct {
+//  tu_fifo_t fifo;
+//  OSAL_MUTEX_DEF(ff_mutex);
+//
+//
+//}usbh_edpt_stream_t;
+
 typedef struct {
   uint8_t daddr;
   uint8_t itf_num;
@@ -184,6 +192,13 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xf
 void cdch_init(void)
 {
   tu_memclr(cdch_data, sizeof(cdch_data));
+
+//  for(size_t i=0; i<CFG_TUH_CDC; i++)
+//  {
+//    cdch_interface_t* p_cdc = &cdch_data[i];
+//
+//
+//  }
 }
 
 void cdch_close(uint8_t dev_addr)

From fc9321ce26ed5662cfa6a48b52507b4a39a8cc08 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Dec 2022 23:54:21 +0700
Subject: [PATCH 1310/2085] correct cdc usbh_driver_set_config_complete()

---
 src/class/cdc/cdc_host.c | 32 +++++++++++++++++++++-----------
 src/host/usbh.c          |  3 ++-
 2 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index cb0794fa3..482ccf4be 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -36,13 +36,24 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
+#if 0
+typedef struct {
+  tu_fifo_t ff;
+  OSAL_MUTEX_DEF(ff_mutex);
+}tu_edpt_stream_t;
 
-//typedef struct {
-//  tu_fifo_t fifo;
-//  OSAL_MUTEX_DEF(ff_mutex);
-//
-//
-//}usbh_edpt_stream_t;
+uint32_t tud_cdc_read_available (void);
+uint32_t tud_cdc_read (void *buffer, uint32_t bufsize);
+void tud_cdc_read_flush (void);
+bool tud_cdc_peek (uint8_t *ui8);
+
+uint32_t tud_cdc_write (void const *buffer, uint32_t bufsize);
+uint32_t tud_cdc_write_flush (void);
+uint32_t tud_cdc_write_available (void);
+
+//--------------------------------------------------------
+tu_edpt_stream_write()
+#endif
 
 typedef struct {
   uint8_t daddr;
@@ -65,10 +76,8 @@ typedef struct {
   uint8_t rx_ff_buf[CFG_TUH_CDC_RX_BUFSIZE];
   uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
 
-#if CFG_FIFO_MUTEX
-  osal_mutex_def_t rx_ff_mutex;
-  osal_mutex_def_t tx_ff_mutex;
-#endif
+  OSAL_MUTEX_DEF(rx_ff_mutex);
+  OSAL_MUTEX_DEF(tx_ff_mutex);
 
   // Endpoint Transfer buffer
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUH_CDC_RX_EPSIZE];
@@ -311,7 +320,8 @@ bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
   if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(dev_addr);
 
   // notify usbh that driver enumeration is complete
-  usbh_driver_set_config_complete(dev_addr, itf_num);
+  // itf_num+1 to account for data interface as well
+  usbh_driver_set_config_complete(dev_addr, itf_num+1);
 
   return true;
 }
diff --git a/src/host/usbh.c b/src/host/usbh.c
index b0cd62bac..4b278f2da 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1570,7 +1570,8 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
   for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++)
   {
     // continue with next valid interface
-    // TODO skip IAD binding interface such as CDCs
+    // IAD binding interface such as CDCs should return itf_num + 1 when complete
+    // with usbh_driver_set_config_complete()
     uint8_t const drv_id = dev->itf2drv[itf_num];
     if (drv_id != DRVID_INVALID)
     {

From 7d76c172db2f45846c9db45ceed4d879be96296d Mon Sep 17 00:00:00 2001
From: tyustli <43946994+tyustli@users.noreply.github.com>
Date: Mon, 19 Dec 2022 17:18:47 +0800
Subject: [PATCH 1311/2085] [add] semaphore reset support for rt-thread

add  semaphore reset support for rt-thread
---
 src/osal/osal_rtthread.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index f8452bfb2..c0d6e91a1 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -63,7 +63,8 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t se
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
-    // TODO: implement
+    rt_ubase_t value = 0;
+    rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, &value);
 }
 
 //--------------------------------------------------------------------+

From e992ff46d24984a8e1143d6d6c1c5aba8c93266f Mon Sep 17 00:00:00 2001
From: tyustli <43946994+tyustli@users.noreply.github.com>
Date: Mon, 19 Dec 2022 17:25:35 +0800
Subject: [PATCH 1312/2085] Update osal_rtthread.h

---
 src/osal/osal_rtthread.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h
index c0d6e91a1..18eb9c693 100644
--- a/src/osal/osal_rtthread.h
+++ b/src/osal/osal_rtthread.h
@@ -63,8 +63,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t se
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
-    rt_ubase_t value = 0;
-    rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, &value);
+    rt_sem_control(sem_hdl, RT_IPC_CMD_RESET, 0);
 }
 
 //--------------------------------------------------------------------+

From a46ad8fcdfef8c742933843b9c237778fc5ea0a0 Mon Sep 17 00:00:00 2001
From: jbruneaux31 <96246761+jbruneaux31@users.noreply.github.com>
Date: Mon, 19 Dec 2022 13:58:54 +0100
Subject: [PATCH 1313/2085] Update osal_freertos.h

Fix FreeRTOS task switch even if not required (unitialized variable usage)
---
 src/osal/osal_freertos.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 327aa9970..9393d1f26 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -115,7 +115,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t se
   }
   else
   {
-    BaseType_t xHigherPriorityTaskWoken;
+    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
     BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken);
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
@@ -189,7 +189,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void
   }
   else
   {
-    BaseType_t xHigherPriorityTaskWoken;
+    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
     BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken);
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3

From 7004914d8c6c7d88908776eb153661b6b987e513 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 20 Dec 2022 12:06:59 +0700
Subject: [PATCH 1314/2085] fix hid host incorrect edpt release if failed to
 transmit

add CDC_CONTROL_LINE_STATE_DTR/RTS, TUSB_INDEX_INVALID enum
---
 src/class/cdc/cdc.h      | 10 ++++++++--
 src/class/hid/hid_host.c |  2 +-
 src/common/tusb_types.h  |  5 +++++
 3 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index c428af865..6a9669cf2 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -192,6 +192,12 @@ typedef enum
   CDC_REQUEST_MDLM_SEMANTIC_MODEL                          = 0x60,
 }cdc_management_request_t;
 
+enum
+{
+  CDC_CONTROL_LINE_STATE_DTR = 0x01,
+  CDC_CONTROL_LINE_STATE_RTS = 0x02,
+};
+
 //--------------------------------------------------------------------+
 // Management Element Notification (Notification Endpoint)
 //--------------------------------------------------------------------+
@@ -390,8 +396,8 @@ TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct");
 
 typedef struct TU_ATTR_PACKED
 {
-  uint16_t dte_is_present : 1; ///< Indicates to DCE if DTE is presentor not. This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR.
-  uint16_t half_duplex_carrier_control : 1;
+  uint16_t dtr : 1;
+  uint16_t rts : 1;
   uint16_t : 14;
 } cdc_line_control_state_t;
 
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 504ddca1e..42b5e2f4e 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -259,7 +259,7 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance)
 
   if ( !usbh_edpt_xfer(dev_addr, hid_itf->ep_in, hid_itf->epin_buf, hid_itf->epin_size) )
   {
-    usbh_edpt_claim(dev_addr, hid_itf->ep_in);
+    usbh_edpt_release(dev_addr, hid_itf->ep_in);
     return false;
   }
 
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index c4c9d4133..32cdba450 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -273,6 +273,11 @@ enum
   CONTROL_STAGE_ACK
 };
 
+enum
+{
+  TUSB_INDEX_INVALID = 0xff
+};
+
 //--------------------------------------------------------------------+
 // USB Descriptors
 //--------------------------------------------------------------------+

From 854e5222aea570a2be2201d8c460f54b87c9108a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 00:26:46 +0700
Subject: [PATCH 1315/2085] finalizing cdc host, has a working read/write

TODO: first character seems not to get echoed. set control line state
seems to failed with LOG < 2
---
 examples/host/cdc_msc_hid/src/main.c |  18 --
 src/class/cdc/cdc_host.c             | 466 +++++++++++++++++++++------
 src/class/cdc/cdc_host.h             |  84 +++--
 3 files changed, 423 insertions(+), 145 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index 465e457f7..b34810252 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -61,24 +61,6 @@ int main(void)
   return 0;
 }
 
-//--------------------------------------------------------------------+
-// USB CDC
-//--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION static char serial_in_buffer[64] = { 0 };
-
-// invoked ISR context
-void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes)
-{
-  (void) event;
-  (void) pipe_id;
-  (void) xferred_bytes;
-
-  printf(serial_in_buffer);
-  tu_memclr(serial_in_buffer, sizeof(serial_in_buffer));
-
-  tuh_cdc_receive(dev_addr, serial_in_buffer, sizeof(serial_in_buffer), true); // waiting for next data
-}
-
 //--------------------------------------------------------------------+
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 482ccf4be..bdfbe3e74 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -36,52 +36,157 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-#if 0
 typedef struct {
   tu_fifo_t ff;
+
+  // mutex: read if ep rx, write if e tx
   OSAL_MUTEX_DEF(ff_mutex);
+
+  // TODO xfer_fifo can skip this buffer
+  uint8_t* ep_buf;
+  uint16_t ep_bufsize;
+  uint8_t ep_addr;
 }tu_edpt_stream_t;
 
-uint32_t tud_cdc_read_available (void);
-uint32_t tud_cdc_read (void *buffer, uint32_t bufsize);
-void tud_cdc_read_flush (void);
-bool tud_cdc_peek (uint8_t *ui8);
+bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool use_wr_mutex, bool overwritable,
+                         void* ff_buf, uint16_t ff_bufsize,
+                         uint8_t* ep_buf, uint16_t ep_bufsize)
+{
+  osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex);
+  (void) new_mutex;
 
-uint32_t tud_cdc_write (void const *buffer, uint32_t bufsize);
-uint32_t tud_cdc_write_flush (void);
-uint32_t tud_cdc_write_available (void);
+  tu_fifo_config(&s->ff, ff_buf, ff_bufsize, 1, overwritable);
+  tu_fifo_config_mutex(&s->ff, use_wr_mutex ? new_mutex : NULL, use_wr_mutex ? NULL : new_mutex);
 
-//--------------------------------------------------------
-tu_edpt_stream_write()
-#endif
+  s->ep_buf = ep_buf;
+  s->ep_bufsize = ep_bufsize;
+
+  return true;
+}
+
+bool tu_edpt_stream_clear(tu_edpt_stream_t* s)
+{
+  return tu_fifo_clear(&s->ff);
+}
+
+uint32_t tud_edpt_stream_write_flush(uint8_t dev_addr, tu_edpt_stream_t* s)
+{
+  // No data to send
+  if ( !tu_fifo_count(&s->ff) ) return 0;
+
+  // Claim the endpoint
+  // uint8_t const rhport = 0;
+  // TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 );
+  TU_VERIFY( usbh_edpt_claim(dev_addr, s->ep_addr) );
+
+  // Pull data from FIFO -> EP buf
+  uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize);
+
+  if ( count )
+  {
+    //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
+    TU_ASSERT( usbh_edpt_xfer(dev_addr, s->ep_addr, s->ep_buf, count), 0 );
+    return count;
+  }else
+  {
+    // Release endpoint since we don't make any transfer
+    // Note: data is dropped if terminal is not connected
+    //usbd_edpt_release(rhport, p_cdc->ep_in);
+
+    usbh_edpt_release(dev_addr, s->ep_addr);
+    return 0;
+  }
+}
+
+uint32_t tu_edpt_stream_write(uint8_t daddr, tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize)
+{
+  uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
+
+  // flush if queue more than packet size
+  uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+  if ( (tu_fifo_count(&s->ff) >= bulk_packet_size)
+      /* || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) */ )
+  {
+    tud_edpt_stream_write_flush(daddr, s);
+  }
+
+  return ret;
+}
+
+void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes)
+{
+  tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes);
+}
+
+uint32_t tu_edpt_stream_read_xfer(uint8_t daddr, tu_edpt_stream_t* s)
+{
+  uint16_t available = tu_fifo_remaining(&s->ff);
+
+  // Prepare for incoming data but only allow what we can store in the ring buffer.
+  // TODO Actually we can still carry out the transfer, keeping count of received bytes
+  // and slowly move it to the FIFO when read().
+  // This pre-check reduces endpoint claiming
+  uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+  TU_VERIFY(available >= bulk_packet_size);
+
+  // claim endpoint
+  TU_VERIFY(usbh_edpt_claim(daddr, s->ep_addr), 0);
+
+  // fifo can be changed before endpoint is claimed
+  available = tu_fifo_remaining(&s->ff);
+
+  if ( available >= bulk_packet_size )
+  {
+    // multiple of packet size limit by ep bufsize
+    uint16_t count = (uint16_t) (available & (bulk_packet_size -1));
+    count = tu_min16(count, s->ep_bufsize);
+
+    TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, s->ep_buf, count), 0 );
+    return count;
+  }else
+  {
+    // Release endpoint since we don't make any transfer
+    usbh_edpt_release(daddr, s->ep_addr);
+    return 0;
+  }
+}
+
+uint32_t tu_edpt_stream_read(uint8_t daddr, tu_edpt_stream_t* s, void* buffer, uint32_t bufsize)
+{
+  uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize);
+  tu_edpt_stream_read_xfer(daddr, s);
+  return num_read;
+}
+
+uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s)
+{
+  return (uint32_t) tu_fifo_count(&s->ff);
+}
 
 typedef struct {
   uint8_t daddr;
-  uint8_t itf_num;
-  uint8_t itf_protocol;
-
-  uint8_t ep_notif;
-  uint8_t ep_in;
-  uint8_t ep_out;
+  uint8_t bInterfaceNumber;
+  uint8_t bInterfaceSubClass;
+  uint8_t bInterfaceProtocol;
 
   cdc_acm_capability_t acm_capability;
+  uint8_t ep_notif;
 
   // Bit 0:  DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
-  // uint8_t line_state;
+  uint8_t line_state;
 
-  // FIFO
-  tu_fifo_t rx_ff;
-  tu_fifo_t tx_ff;
+  tuh_xfer_cb_t user_control_cb;
 
-  uint8_t rx_ff_buf[CFG_TUH_CDC_RX_BUFSIZE];
-  uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
+  struct {
+    tu_edpt_stream_t tx;
+    tu_edpt_stream_t rx;
 
-  OSAL_MUTEX_DEF(rx_ff_mutex);
-  OSAL_MUTEX_DEF(tx_ff_mutex);
+    uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
+    CFG_TUSB_MEM_ALIGN uint8_t tx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
 
-  // Endpoint Transfer buffer
-  CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUH_CDC_RX_EPSIZE];
-  CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUH_CDC_TX_EPSIZE];
+    uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
+    CFG_TUSB_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
+  } stream;
 
 } cdch_interface_t;
 
@@ -92,19 +197,33 @@ typedef struct {
 CFG_TUSB_MEM_SECTION
 static cdch_interface_t cdch_data[CFG_TUH_CDC];
 
-static inline cdch_interface_t* get_itf(uint8_t dev_addr)
+static inline cdch_interface_t* get_itf(uint8_t idx)
 {
-  for(size_t i=0; i<CFG_TUH_CDC; i++)
+  TU_ASSERT(idx < CFG_TUH_CDC, NULL);
+  cdch_interface_t* p_cdc = &cdch_data[idx];
+
+  return (p_cdc->daddr != 0) ? p_cdc : NULL;
+}
+
+static inline cdch_interface_t* get_itf_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
+{
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
   {
-    if (cdch_data[i].daddr == dev_addr) return &cdch_data[i];
+    cdch_interface_t* p_cdc = &cdch_data[i];
+    if ( (p_cdc->daddr == daddr) &&
+         (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr))
+    {
+      return p_cdc;
+    }
   }
 
   return NULL;
 }
 
+
 static cdch_interface_t* find_new_itf(void)
 {
-  for(size_t i=0; i<CFG_TUH_CDC; i++)
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
   {
     if (cdch_data[i].daddr == 0) return &cdch_data[i];
   }
@@ -113,58 +232,119 @@ static cdch_interface_t* find_new_itf(void)
 }
 
 //--------------------------------------------------------------------+
-// APPLICATION API (parameter validation needed)
+// APPLICATION API
 //--------------------------------------------------------------------+
 
-bool tuh_cdc_mounted(uint8_t dev_addr)
+uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num)
 {
-  cdch_interface_t* p_cdc = get_itf(dev_addr);
+  for(uint8_t i=0; i<CFG_TUH_CDC; i++)
+  {
+    const cdch_interface_t* p_cdc = &cdch_data[i];
+
+    if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i;
+  }
+
+  return TUSB_INDEX_INVALID;
+}
+
+bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info)
+{
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && info);
+
+  info->daddr              = p_cdc->daddr;
+  info->bInterfaceNumber   = p_cdc->bInterfaceNumber;
+  info->bInterfaceSubClass = p_cdc->bInterfaceSubClass;
+  info->bInterfaceProtocol = p_cdc->bInterfaceProtocol;
+
+  return true;
+}
+
+bool tuh_cdc_mounted(uint8_t idx)
+{
+  cdch_interface_t* p_cdc = get_itf(idx);
   return p_cdc != NULL;
 }
 
-uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize)
+bool tuh_cdc_get_dtr(uint8_t idx)
 {
-  (void) dev_addr;
-  (void) buffer;
-  (void) bufsize;
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
 
-  return 0;
+  return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false;
 }
 
-bool tuh_cdc_serial_is_mounted(uint8_t dev_addr)
+bool tuh_cdc_get_rts(uint8_t idx)
 {
-  // TODO consider all AT Command as serial candidate
-  return tuh_cdc_mounted(dev_addr)                                         &&
-      (cdch_data[dev_addr-1].itf_protocol <= CDC_COMM_PROTOCOL_ATCOMMAND_CDMA);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false;
 }
 
-bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify)
+uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize)
 {
-  (void) is_notify;
-  TU_VERIFY( tuh_cdc_mounted(dev_addr) );
-  TU_VERIFY( p_data != NULL && length);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
 
-  uint8_t const ep_out = cdch_data[dev_addr-1].ep_out;
-  if ( usbh_edpt_busy(dev_addr, ep_out) ) return false;
-
-  return usbh_edpt_xfer(dev_addr, ep_out, (void*)(uintptr_t) p_data, (uint16_t) length);
+  return tu_edpt_stream_write(p_cdc->daddr, &p_cdc->stream.tx, buffer, bufsize);
 }
 
-bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify)
+uint32_t tuh_cdc_write_flush(uint8_t idx)
 {
-  (void) is_notify;
-  TU_VERIFY( tuh_cdc_mounted(dev_addr) );
-  TU_VERIFY( p_buffer != NULL && length );
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
 
-  uint8_t const ep_in = cdch_data[dev_addr-1].ep_in;
-  if ( usbh_edpt_busy(dev_addr, ep_in) ) return false;
-
-  return usbh_edpt_xfer(dev_addr, ep_in, p_buffer, (uint16_t) length);
+  return tud_edpt_stream_write_flush(p_cdc->daddr, &p_cdc->stream.tx);
 }
 
-bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb)
+uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize)
 {
-  cdch_interface_t const * p_cdc = get_itf(dev_addr);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_read(p_cdc->daddr, &p_cdc->stream.rx, buffer, bufsize);
+}
+
+uint32_t tuh_cdc_read_available(uint8_t idx)
+{
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_read_available(&p_cdc->stream.rx);
+}
+
+//--------------------------------------------------------------------+
+// Control Endpoint API
+//--------------------------------------------------------------------+
+
+// internal control complete to update state such as line state, encoding
+static void cdch_internal_control_complete(tuh_xfer_t* xfer)
+{
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc, );
+
+  if (xfer->result == XFER_RESULT_SUCCESS)
+  {
+    switch(xfer->setup->bRequest)
+    {
+      case CDC_REQUEST_SET_CONTROL_LINE_STATE:
+        p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
+      break;
+
+      default: break;
+    }
+  }
+
+  xfer->complete_cb = p_cdc->user_control_cb;
+  xfer->complete_cb(xfer);
+}
+
+bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request);
 
   tusb_control_request_t const request =
@@ -176,19 +356,20 @@ bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xf
       .direction = TUSB_DIR_OUT
     },
     .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
-    .wValue   = tu_htole16((uint16_t) ((dtr ? 1u : 0u) | (rts ? 2u : 0u))),
-    .wIndex   = tu_htole16(p_cdc->itf_num),
+    .wValue   = tu_htole16(line_state),
+    .wIndex   = tu_htole16(p_cdc->bInterfaceNumber),
     .wLength  = 0
   };
 
+  p_cdc->user_control_cb = complete_cb;
   tuh_xfer_t xfer =
   {
-    .daddr       = dev_addr,
+    .daddr       = p_cdc->daddr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
-    .complete_cb = complete_cb,
-    .user_data    = 0
+    .complete_cb = cdch_internal_control_complete,
+    .user_data   = user_data
   };
 
   return tuh_control_xfer(&xfer);
@@ -202,32 +383,79 @@ void cdch_init(void)
 {
   tu_memclr(cdch_data, sizeof(cdch_data));
 
-//  for(size_t i=0; i<CFG_TUH_CDC; i++)
-//  {
-//    cdch_interface_t* p_cdc = &cdch_data[i];
-//
-//
-//  }
+  for(size_t i=0; i<CFG_TUH_CDC; i++)
+  {
+    cdch_interface_t* p_cdc = &cdch_data[i];
+
+    tu_edpt_stream_init(&p_cdc->stream.tx, true, false,
+                        p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
+                        p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
+
+    tu_edpt_stream_init(&p_cdc->stream.rx, false, false,
+                        p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
+                        p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
+  }
 }
 
-void cdch_close(uint8_t dev_addr)
+void cdch_close(uint8_t daddr)
 {
-  cdch_interface_t * p_cdc = get_itf(dev_addr);
-  TU_VERIFY(p_cdc, );
-
-  // Invoke application callback
-  if (tuh_cdc_umount_cb)
+  for(uint8_t idx=0; idx<CFG_TUH_CDC; idx++)
   {
-    tuh_cdc_umount_cb(dev_addr);
+    cdch_interface_t* p_cdc = &cdch_data[idx];
+    if (p_cdc->daddr == daddr)
+    {
+      // Invoke application callback
+      if (tuh_cdc_umount_cb) tuh_cdc_umount_cb(idx);
+
+      //tu_memclr(p_cdc, sizeof(cdch_interface_t));
+      p_cdc->daddr = 0;
+      p_cdc->bInterfaceNumber = 0;
+      tu_edpt_stream_clear(&p_cdc->stream.tx);
+      tu_edpt_stream_clear(&p_cdc->stream.rx);
+    }
+  }
+}
+
+bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
+{
+  // TODO handle stall response, retry failed transfer ...
+  TU_ASSERT(event == XFER_RESULT_SUCCESS);
+
+  cdch_interface_t * p_cdc = get_itf_by_ep_addr(daddr, ep_addr);
+  TU_ASSERT(p_cdc);
+
+  if ( ep_addr == p_cdc->stream.tx.ep_addr )
+  {
+    if ( 0 == tud_edpt_stream_write_flush(daddr, &p_cdc->stream.tx) )
+    {
+      // If there is no data left, a ZLP should be sent if
+      // xferred_bytes is multiple of EP Packet size and not zero
+      uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+      if ( !tu_fifo_count(&p_cdc->stream.tx.ff) && xferred_bytes && (0 == (xferred_bytes & (bulk_packet_size-1))) )
+      {
+        if ( usbh_edpt_claim(daddr, p_cdc->stream.tx.ep_addr) )
+        {
+          usbh_edpt_xfer(daddr, p_cdc->stream.tx.ep_addr, NULL, 0);
+        }
+      }
+    }
+  }
+  else if ( ep_addr == p_cdc->stream.rx.ep_addr )
+  {
+    tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
+
+    // invoke receive callback
+
+    // prepare for next transfer if needed
+    tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx);
+  }else if ( ep_addr == p_cdc->ep_notif )
+  {
+    // TODO handle notification endpoint
+  }else
+  {
+    TU_ASSERT(false);
   }
 
-  tu_memclr(p_cdc, sizeof(cdch_interface_t));
-}
-
-bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
-{
-  (void) ep_addr;
-  tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes );
   return true;
 }
 
@@ -238,7 +466,6 @@ bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
   (void) rhport;
-  (void) max_len;
 
   // Only support ACM subclass
   // Protocol 0xFF can be RNDIS device for windows XP
@@ -246,19 +473,22 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
              CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass &&
              0xFF                                     != itf_desc->bInterfaceProtocol);
 
+  uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len;
+
   cdch_interface_t * p_cdc = find_new_itf();
   TU_VERIFY(p_cdc);
 
-  p_cdc->daddr        = dev_addr;
-  p_cdc->itf_num      = itf_desc->bInterfaceNumber;
-  p_cdc->itf_protocol = itf_desc->bInterfaceProtocol;
+  p_cdc->daddr              = dev_addr;
+  p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
+  p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
+  p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol;
+  p_cdc->line_state         = 0;
 
   //------------- Control Interface -------------//
-  uint16_t drv_len = tu_desc_len(itf_desc);
   uint8_t const * p_desc = tu_desc_next(itf_desc);
 
   // Communication Functional Descriptors
-  while( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
+  while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) )
   {
     if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
     {
@@ -266,7 +496,6 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
       p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
     }
 
-    drv_len += tu_desc_len(p_desc);
     p_desc = tu_desc_next(p_desc);
   }
 
@@ -279,7 +508,6 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
     TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) );
     p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
-    drv_len += tu_desc_len(p_desc);
     p_desc = tu_desc_next(p_desc);
   }
 
@@ -288,42 +516,72 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
        (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
   {
     // next to endpoint descriptor
-    drv_len += tu_desc_len(p_desc);
     p_desc = tu_desc_next(p_desc);
 
     // data endpoints expected to be in pairs
     for(uint32_t i=0; i<2; i++)
     {
       tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-      TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
+      TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType &&
+                TUSB_XFER_BULK     == desc_ep->bmAttributes.xfer);
 
       TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep));
 
       if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
       {
-        p_cdc->ep_in = desc_ep->bEndpointAddress;
+        p_cdc->stream.rx.ep_addr = desc_ep->bEndpointAddress;
       }else
       {
-        p_cdc->ep_out = desc_ep->bEndpointAddress;
+        p_cdc->stream.tx.ep_addr = desc_ep->bEndpointAddress;
       }
 
-      drv_len += tu_desc_len(p_desc);
-      p_desc = tu_desc_next( p_desc );
+      p_desc = tu_desc_next(p_desc);
     }
   }
 
   return true;
 }
 
-bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
+static void config_cdc_complete(uint8_t daddr, uint8_t itf_num)
 {
-  if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(dev_addr);
+  uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num);
+
+  if (idx != TUSB_INDEX_INVALID)
+  {
+    if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
+
+    // Prepare for incoming data
+    cdch_interface_t* p_cdc = get_itf(idx);
+    tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx);
+  }
 
   // notify usbh that driver enumeration is complete
   // itf_num+1 to account for data interface as well
-  usbh_driver_set_config_complete(dev_addr, itf_num+1);
+  usbh_driver_set_config_complete(daddr, itf_num+1);
+}
 
+#if CFG_TUH_CDC_SET_DTRRTS_ON_ENUM
+
+static void config_set_dtr_rts_complete (tuh_xfer_t* xfer)
+{
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  config_cdc_complete(xfer->daddr, itf_num);
+}
+
+bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
+{
+  uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num);
+  return tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_SET_DTRRTS_ON_ENUM, config_set_dtr_rts_complete, 0);
+}
+
+#else
+
+bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
+{
+  config_cdc_complete(daddr, itf_num);
   return true;
 }
 
 #endif
+
+#endif
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index b2e75902d..54e082e7d 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -37,6 +37,11 @@
 // Class Driver Configuration
 //--------------------------------------------------------------------+
 
+// Set DTR ( bit 0), RTS (bit 1) on enumeration/mounted
+#ifndef CFG_TUH_CDC_SET_DTRRTS_ON_ENUM
+#define CFG_TUH_CDC_SET_DTRRTS_ON_ENUM    0
+#endif
+
 // RX FIFO size
 #ifndef CFG_TUH_CDC_RX_BUFSIZE
 #define CFG_TUH_CDC_RX_BUFSIZE USBH_EPSIZE_BULK_MAX
@@ -61,43 +66,76 @@
 // Application API
 //--------------------------------------------------------------------+
 
-bool tuh_cdc_mounted(uint8_t dev_addr);
+typedef struct
+{
+  uint8_t daddr;
+  uint8_t bInterfaceNumber;
+  uint8_t bInterfaceSubClass;
+  uint8_t bInterfaceProtocol;
+} tuh_cdc_itf_info_t;
 
-uint32_t tuh_cdc_write(uint8_t dev_addr, void const* buffer, uint32_t bufsize);
-//uint32_t tuh_cdc_read(uint8_t dev_addr, void* buffer, uint32_t bufsize);
+// Get Interface index from device address + interface number
+// return TUSB_INDEX_INVALID (0xFF) if not found
+uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num);
+
+// Get Interface information
+// return true if index is correct and interface is currently mounted
+bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info);
+
+// Check if a interface is mounted
+bool tuh_cdc_mounted(uint8_t idx);
+
+// Get current DTR status
+bool tuh_cdc_get_dtr(uint8_t idx);
+
+// Get current RTS status
+bool tuh_cdc_get_rts(uint8_t idx);
+
+// Check if interface is connected (DTR active)
+TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx)
+{
+  return tuh_cdc_get_dtr(idx);
+}
+
+// Write to cdc interface
+uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize);
+
+// Force sending data if possible, return number of forced bytes
+uint32_t tuh_cdc_write_flush(uint8_t idx);
+
+// Read from cdc interface
+uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize);
+
+// Get the number of bytes available for reading
+uint32_t tuh_cdc_read_available(uint8_t idx);
 
 //--------------------------------------------------------------------+
 // Control Endpoint (Request) API
 //--------------------------------------------------------------------+
 
-// Set Control Line State (DTR, RTS)
-bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_xfer_cb_t complete_cb);
+// Send control request to Set Control Line State: DTR (bit 0), RTS (bit 1)
+bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
-static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_xfer_cb_t complete_cb)
+// Connect by set both DTR, RTS
+static inline bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  return tuh_cdc_set_control_line_state(dev_addr, true, true, complete_cb);
+  return tuh_cdc_set_control_line_state(idx, CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS, complete_cb, user_data);
 }
 
-static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_xfer_cb_t complete_cb)
+// Disconnect by clear both DTR, RTS
+static inline bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb);
+  return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data);
 }
 
 //------------- Application Callback -------------//
 
 // Invoked when a device with CDC interface is mounted
-TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t dev_addr);
+// idx is index of cdc interface in the internal pool.
+TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t idx);
 
 // Invoked when a device with CDC interface is unmounted
-TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t dev_addr);
-
-
-/** \brief 			Check if device support CDC Serial interface or not
- * \param[in]		dev_addr	device address
- * \retval      true if device supports
- * \retval      false if device does not support or is not mounted
- */
-bool tuh_cdc_serial_is_mounted(uint8_t dev_addr);
+TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t idx);
 
 /** \brief      Check if the interface is currently busy or not
  * \param[in]   dev_addr device address
@@ -108,7 +146,7 @@ bool tuh_cdc_serial_is_mounted(uint8_t dev_addr);
  *              can be scheduled. User needs to make sure the corresponding interface is mounted
  *              (by \ref tuh_cdc_serial_is_mounted) before calling this function.
  */
-bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid);
+// bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid);
 
 /** \brief 			Perform USB OUT transfer to device
  * \param[in]		dev_addr	device address
@@ -121,7 +159,7 @@ bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid);
  * \note        This function is non-blocking and returns immediately. The result of USB transfer will be reported by the
  *              interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION.
  */
-bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify);
+// bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify);
 
 /** \brief 			Perform USB IN transfer to get data from device
  * \param[in]		dev_addr	device address
@@ -134,7 +172,7 @@ bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool i
  * \note        This function is non-blocking and returns immediately. The result of USB transfer will be reported by the
  *              interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION.
  */
-bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify);
+// bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify);
 
 //--------------------------------------------------------------------+
 // CDC APPLICATION CALLBACKS
@@ -151,7 +189,7 @@ bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is
  *              - XFER_RESULT_STALLED : previously scheduled transfer is stalled by device.
  * \note
  */
-void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes);
+// void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes);
 
 /// @} // group CDC_Serial_Host
 /// @}

From 37529c41da3884c235ac4f582b7202331877142c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 10:46:47 +0700
Subject: [PATCH 1316/2085] fix ci

---
 src/class/cdc/cdc_host.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index bdfbe3e74..5aec41cbc 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -54,6 +54,7 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool use_wr_mutex, bool overwritab
 {
   osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex);
   (void) new_mutex;
+  (void) use_wr_mutex;
 
   tu_fifo_config(&s->ff, ff_buf, ff_bufsize, 1, overwritable);
   tu_fifo_config_mutex(&s->ff, use_wr_mutex ? new_mutex : NULL, use_wr_mutex ? NULL : new_mutex);

From d1ea3844f70a5add6e073aa8fa6b562413db4929 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 11:04:57 +0700
Subject: [PATCH 1317/2085] rename TU_LOG_VAR to TU_LOG_PTR, print out setup of
 failed control transfer when LOG=1

---
 src/common/tusb_debug.h | 18 +++++++++---------
 src/host/usbh.c         |  8 ++++++--
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index ac5bee6ec..65fd1920d 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -66,7 +66,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 #define TU_LOG(n, ...)        TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
 #define TU_LOG_MEM(n, ...)    TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
 #define TU_LOG_ARR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _ARR)(__VA_ARGS__)
-#define TU_LOG_VAR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _VAR)(__VA_ARGS__)
+#define TU_LOG_PTR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _PTR)(__VA_ARGS__)
 #define TU_LOG_INT(n, ...)    TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
 #define TU_LOG_HEX(n, ...)    TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
 #define TU_LOG_LOCATION()     tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
@@ -76,7 +76,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 #define TU_LOG1               tu_printf
 #define TU_LOG1_MEM           tu_print_mem
 #define TU_LOG1_ARR(_x, _n)   tu_print_arr((uint8_t const*)(_x), _n)
-#define TU_LOG1_VAR(_x)       tu_print_arr((uint8_t const*)(_x), sizeof(*(_x)))
+#define TU_LOG1_PTR(_x)       tu_print_arr((uint8_t const*)(_x), sizeof(*(_x)))
 #define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
 #define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
 
@@ -85,7 +85,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
   #define TU_LOG2             TU_LOG1
   #define TU_LOG2_MEM         TU_LOG1_MEM
   #define TU_LOG2_ARR         TU_LOG1_ARR
-  #define TU_LOG2_VAR         TU_LOG1_VAR
+  #define TU_LOG2_PTR         TU_LOG1_PTR
   #define TU_LOG2_INT         TU_LOG1_INT
   #define TU_LOG2_HEX         TU_LOG1_HEX
 #endif
@@ -95,7 +95,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
   #define TU_LOG3             TU_LOG1
   #define TU_LOG3_MEM         TU_LOG1_MEM
   #define TU_LOG3_ARR         TU_LOG1_ARR
-  #define TU_LOG3_VAR         TU_LOG1_VAR
+  #define TU_LOG3_PTR         TU_LOG1_PTR
   #define TU_LOG3_INT         TU_LOG1_INT
   #define TU_LOG3_HEX         TU_LOG1_HEX
 #endif
@@ -132,7 +132,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG
   #define TU_LOG(n, ...)
   #define TU_LOG_MEM(n, ...)
-  #define TU_LOG_VAR(n, ...)
+  #define TU_LOG_PTR(n, ...)
   #define TU_LOG_INT(n, ...)
   #define TU_LOG_HEX(n, ...)
   #define TU_LOG_LOCATION()
@@ -143,14 +143,14 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 
 #define TU_LOG0(...)
 #define TU_LOG0_MEM(...)
-#define TU_LOG0_VAR(...)
+#define TU_LOG0_PTR(...)
 #define TU_LOG0_INT(...)
 #define TU_LOG0_HEX(...)
 
 #ifndef TU_LOG1
   #define TU_LOG1(...)
   #define TU_LOG1_MEM(...)
-  #define TU_LOG1_VAR(...)
+  #define TU_LOG1_PTR(...)
   #define TU_LOG1_INT(...)
   #define TU_LOG1_HEX(...)
 #endif
@@ -158,7 +158,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG2
   #define TU_LOG2(...)
   #define TU_LOG2_MEM(...)
-  #define TU_LOG2_VAR(...)
+  #define TU_LOG2_PTR(...)
   #define TU_LOG2_INT(...)
   #define TU_LOG2_HEX(...)
 #endif
@@ -166,7 +166,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG3
   #define TU_LOG3(...)
   #define TU_LOG3_MEM(...)
-  #define TU_LOG3_VAR(...)
+  #define TU_LOG3_PTR(...)
   #define TU_LOG3_INT(...)
   #define TU_LOG3_HEX(...)
 #endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 4b278f2da..59b1c3280 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -540,7 +540,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
   const uint8_t rhport = usbh_get_rhport(daddr);
 
   TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request");
-  TU_LOG2_VAR(xfer->setup);
+  TU_LOG2_PTR(xfer->setup);
   TU_LOG2("\r\n");
 
   if (xfer->complete_cb)
@@ -618,7 +618,11 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 
   if (XFER_RESULT_SUCCESS != result)
   {
-    TU_LOG1("[%u:%u] Control %s\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED");
+    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
+    #if CFG_TUSB_DEBUG == 1
+    TU_LOG1_PTR(request);
+    TU_LOG1("\r\n");
+    #endif
 
     // terminate transfer if any stage failed
     _xfer_complete(dev_addr, result);

From cb2af4c0bc096e57c3486945eda43dbc26b3829a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 11:46:58 +0700
Subject: [PATCH 1318/2085] minor debug log

---
 src/class/cdc/cdc_host.c |  8 ++++
 src/class/msc/msc_host.c | 13 ++++--
 src/host/usbh.c          | 85 ++++++++++++++++++++++------------------
 3 files changed, 63 insertions(+), 43 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 5aec41cbc..83c623884 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -33,6 +33,12 @@
 
 #include "cdc_host.h"
 
+
+// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
+#define CDCH_DEBUG   2
+
+#define TU_LOG_CDCH(...)   TU_LOG(CDCH_DEBUG, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -348,6 +354,8 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request);
 
+  TU_LOG_CDCH("CDC Set Control Line State\r\n");
+
   tusb_control_request_t const request =
   {
     .bmRequestType_bit =
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 32f75a84b..6724e486c 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -33,6 +33,11 @@
 
 #include "msc_host.h"
 
+// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
+#define MSCH_DEBUG   2
+
+#define TU_LOG_MSCH(...)   TU_LOG(MSCH_DEBUG, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -417,7 +422,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
   p_msc->configured = true;
 
   //------------- Get Max Lun -------------//
-  TU_LOG2("MSC Get Max Lun\r\n");
+  TU_LOG_MSCH("MSC Get Max Lun\r\n");
   tusb_control_request_t const request =
   {
     .bmRequestType_bit =
@@ -456,7 +461,7 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer)
   p_msc->max_lun++; // MAX LUN is minus 1 by specs
 
   // TODO multiple LUN support
-  TU_LOG2("SCSI Test Unit Ready\r\n");
+  TU_LOG_MSCH("SCSI Test Unit Ready\r\n");
   uint8_t const lun = 0;
   tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0);
 }
@@ -469,14 +474,14 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_d
   if (csw->status == 0)
   {
     // Unit is ready, read its capacity
-    TU_LOG2("SCSI Read Capacity\r\n");
+    TU_LOG_MSCH("SCSI Read Capacity\r\n");
     tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0);
   }else
   {
     // Note: During enumeration, some device fails Test Unit Ready and require a few retries
     // with Request Sense to start working !!
     // TODO limit number of retries
-    TU_LOG2("SCSI Request Sense\r\n");
+    TU_LOG_MSCH("SCSI Request Sense\r\n");
     TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete, 0));
   }
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 59b1c3280..36fc5fded 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -46,8 +46,10 @@
 #define CFG_TUH_INTERFACE_MAX   8
 #endif
 
-// Debug level of USBD
-#define USBH_DBG_LVL   2
+// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
+#define USBH_DEBUG   2
+
+#define TU_LOG_USBH(...)   TU_LOG(USBH_DEBUG, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
 // USBH-HCD common data structure
@@ -324,11 +326,11 @@ bool tuh_init(uint8_t controller_id)
   // skip if already initialized
   if ( tuh_inited() ) return true;
 
-  TU_LOG2("USBH init on controller %u\r\n", controller_id);
-  TU_LOG2_INT(sizeof(usbh_device_t));
-  TU_LOG2_INT(sizeof(hcd_event_t));
-  TU_LOG2_INT(sizeof(_ctrl_xfer));
-  TU_LOG2_INT(sizeof(tuh_xfer_t));
+  TU_LOG_USBH("USBH init on controller %u\r\n", controller_id);
+  TU_LOG_INT(USBH_DEBUG, sizeof(usbh_device_t));
+  TU_LOG_INT(USBH_DEBUG, sizeof(hcd_event_t));
+  TU_LOG_INT(USBH_DEBUG, sizeof(_ctrl_xfer));
+  TU_LOG_INT(USBH_DEBUG, sizeof(tuh_xfer_t));
 
   // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -353,7 +355,7 @@ bool tuh_init(uint8_t controller_id)
   // Class drivers
   for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
   {
-    TU_LOG2("%s init\r\n", usbh_class_drivers[drv_id].name);
+    TU_LOG_USBH("%s init\r\n", usbh_class_drivers[drv_id].name);
     usbh_class_drivers[drv_id].init();
   }
 
@@ -401,12 +403,12 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
       case HCD_EVENT_DEVICE_ATTACH:
         // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
         // one device before enumerating another one.
-        TU_LOG2("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
+        TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
         enum_new_device(&event);
       break;
 
       case HCD_EVENT_DEVICE_REMOVE:
-        TU_LOG2("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
+        TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
         process_device_unplugged(event.rhport, event.connection.hub_addr, event.connection.hub_port);
 
         #if CFG_TUH_HUB
@@ -425,7 +427,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
         uint8_t const epnum   = tu_edpt_number(ep_addr);
         uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
-        TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
+        TU_LOG_USBH("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
 
         if (event.dev_addr == 0)
         {
@@ -449,7 +451,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
             uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
             if(drv_id < USBH_CLASS_DRIVER_COUNT)
             {
-              TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
+              TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
               usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
             }
             else
@@ -539,9 +541,11 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
   TU_VERIFY(is_idle);
   const uint8_t rhport = usbh_get_rhport(daddr);
 
-  TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request");
-  TU_LOG2_PTR(xfer->setup);
-  TU_LOG2("\r\n");
+  TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr,
+              (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
+                  tu_str_std_request[xfer->setup->bRequest] : "Class Request");
+  TU_LOG_PTR(USBH_DEBUG, xfer->setup);
+  TU_LOG_USBH("\r\n");
 
   if (xfer->complete_cb)
   {
@@ -585,7 +589,7 @@ TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
 
 static void _xfer_complete(uint8_t daddr, xfer_result_t result)
 {
-  TU_LOG2("\r\n");
+  TU_LOG_USBH("\r\n");
 
   // duplicate xfer since user can execute control transfer within callback
   tusb_control_request_t const request = _ctrl_xfer.request;
@@ -643,8 +647,8 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
       case CONTROL_STAGE_DATA:
         if (request->wLength)
         {
-          TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
-          TU_LOG2_MEM(_ctrl_xfer.buffer, xferred_bytes, 2);
+          TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr);
+          TU_LOG_MEM(USBH_DEBUG, _ctrl_xfer.buffer, xferred_bytes, 2);
         }
 
         _ctrl_xfer.actual_len = (uint16_t) xferred_bytes;
@@ -760,7 +764,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
   uint8_t const dir   = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
-  TU_LOG2("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
+  TU_LOG_USBH("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(ep_state->busy == 0);
@@ -776,7 +780,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
 
   if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
   {
-    TU_LOG2("OK\r\n");
+    TU_LOG_USBH("OK\r\n");
     return true;
   }else
   {
@@ -791,7 +795,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
 
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
 {
-  TU_LOG2("[%u:%u] Open EP0 with Size = %u\r\n", usbh_get_rhport(dev_addr), dev_addr, max_packet_size);
+  TU_LOG_USBH("[%u:%u] Open EP0 with Size = %u\r\n", usbh_get_rhport(dev_addr), dev_addr, max_packet_size);
 
   tusb_desc_endpoint_t ep0_desc =
   {
@@ -960,7 +964,7 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void*
 bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
                                    tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  TU_LOG2("HID Get Report Descriptor\r\n");
+  TU_LOG_USBH("HID Get Report Descriptor\r\n");
   tusb_control_request_t const request =
   {
     .bmRequestType_bit =
@@ -999,7 +1003,7 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
                            tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  TU_LOG2("Set Configuration = %d\r\n", config_num);
+  TU_LOG_USBH("Set Configuration = %d\r\n", config_num);
 
   tusb_control_request_t const request =
   {
@@ -1103,11 +1107,11 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
         (hub_port == 0 || dev->hub_port == hub_port) && // hub_port = 0 means all devices of downstream hub
         dev->connected)
     {
-      TU_LOG2("  Address = %u\r\n", dev_addr);
+      TU_LOG_USBH("  Address = %u\r\n", dev_addr);
 
       if (is_hub_addr(dev_addr))
       {
-        TU_LOG(USBH_DBG_LVL, "HUB address = %u is unmounted\r\n", dev_addr);
+        TU_LOG(USBH_DEBUG, "HUB address = %u is unmounted\r\n", dev_addr);
         // If the device itself is a usb hub, unplug downstream devices.
         // FIXME un-roll recursive calls to prevent potential stack overflow
         process_device_unplugged(rhport, dev_addr, 0);
@@ -1120,7 +1124,7 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
       // Close class driver
       for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
       {
-        TU_LOG2("%s close\r\n", usbh_class_drivers[drv_id].name);
+        TU_LOG_USBH("%s close\r\n", usbh_class_drivers[drv_id].name);
         usbh_class_drivers[drv_id].close(dev_addr);
       }
 
@@ -1245,7 +1249,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
       TU_ASSERT( usbh_edpt_control_open(addr0, 8), );
 
       // Get first 8 bytes of device descriptor for Control Endpoint size
-      TU_LOG2("Get 8 byte of Device Descriptor\r\n");
+      TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n");
       TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, process_enumeration, ENUM_SET_ADDR), );
     }
     break;
@@ -1254,7 +1258,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
     case ENUM_RESET_2:
       // TODO not used by now, but may be needed for some devices !?
       // Reset device again before Set Address
-      TU_LOG2("Port reset2 \r\n");
+      TU_LOG_USBH("Port reset2 \r\n");
       if (_dev0.hub_addr == 0)
       {
         // connected directly to roothub
@@ -1294,7 +1298,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
       TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size), );
 
       // Get full device descriptor
-      TU_LOG2("Get Device Descriptor\r\n");
+      TU_LOG_USBH("Get Device Descriptor\r\n");
       TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC), );
     }
     break;
@@ -1315,7 +1319,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
 
       // Get 9-byte for total length
       uint8_t const config_idx = CONFIG_NUM - 1;
-      TU_LOG2("Get Configuration[0] Descriptor (9 bytes)\r\n");
+      TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n");
       TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC), );
     }
     break;
@@ -1332,7 +1336,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
 
       // Get full configuration descriptor
       uint8_t const config_idx = CONFIG_NUM - 1;
-      TU_LOG2("Get Configuration[0] Descriptor\r\n");
+      TU_LOG_USBH("Get Configuration[0] Descriptor\r\n");
       TU_ASSERT( tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len, process_enumeration, ENUM_SET_CONFIG), );
     }
     break;
@@ -1347,7 +1351,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
 
     case ENUM_CONFIG_DRIVER:
     {
-      TU_LOG2("Device configured\r\n");
+      TU_LOG_USBH("Device configured\r\n");
       usbh_device_t* dev = get_device(daddr);
       TU_ASSERT(dev, );
 
@@ -1387,7 +1391,7 @@ static bool enum_new_device(hcd_event_t* event)
     if ( !hcd_port_connect_status(_dev0.rhport) ) return true;
 
     _dev0.speed = hcd_port_speed_get(_dev0.rhport );
-    TU_LOG2("%s Speed\r\n", tu_str_speed[_dev0.speed]);
+    TU_LOG_USBH("%s Speed\r\n", tu_str_speed[_dev0.speed]);
 
     // fake transfer to kick-off the enumeration process
     tuh_xfer_t xfer;
@@ -1444,7 +1448,7 @@ static bool enum_request_set_addr(void)
   uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
   TU_ASSERT(new_addr != 0);
 
-  TU_LOG2("Set Address = %d\r\n", new_addr);
+  TU_LOG_USBH("Set Address = %d\r\n", new_addr);
 
   usbh_device_t* new_dev = get_device(new_addr);
 
@@ -1488,9 +1492,12 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
 {
   usbh_device_t* dev = get_device(dev_addr);
 
-  uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
+  uint16_t const total_len = tu_le16toh(desc_cfg->wTotalLength);
+  uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + total_len;
   uint8_t const* p_desc   = tu_desc_next(desc_cfg);
 
+  TU_LOG_USBH("Parsing Configuration descriptor (wTotalLength = %u)\r\n", total_len);
+
   // parse each interfaces
   while( p_desc < desc_end )
   {
@@ -1535,7 +1542,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
       if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
       {
         // open successfully
-        TU_LOG2("  %s opened\r\n", driver->name);
+        TU_LOG_USBH("  %s opened\r\n", driver->name);
 
         // bind (associated) interfaces to found driver
         for(uint8_t i=0; i<assoc_itf_count; i++)
@@ -1555,7 +1562,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
 
       if( drv_id >= USBH_CLASS_DRIVER_COUNT )
       {
-        TU_LOG(USBH_DBG_LVL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+        TU_LOG(USBH_DEBUG, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
                desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
       }
     }
@@ -1580,7 +1587,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
     if (drv_id != DRVID_INVALID)
     {
       usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
-      TU_LOG2("%s set config: itf = %u\r\n", driver->name, itf_num);
+      TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num);
       driver->set_config(dev_addr, itf_num);
       break;
     }
@@ -1593,7 +1600,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
 
     if (is_hub_addr(dev_addr))
     {
-      TU_LOG(USBH_DBG_LVL, "HUB address = %u is mounted\r\n", dev_addr);
+      TU_LOG(USBH_DEBUG, "HUB address = %u is mounted\r\n", dev_addr);
     }else
     {
       // Invoke callback if available

From b3e63c335af9345e505575e5bc8ba0281ac73692 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 11:47:07 +0700
Subject: [PATCH 1319/2085] updat cdc host app

---
 examples/host/cdc_msc_hid/src/cdc_app.c | 55 ++++++++++++++++++++++---
 1 file changed, 49 insertions(+), 6 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index 29da02abc..123cb33f0 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -25,6 +25,7 @@
  */
 
 #include "tusb.h"
+#include "bsp/board.h"
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
@@ -33,19 +34,61 @@
 
 //------------- IMPLEMENTATION -------------//
 
+size_t get_console_inputs(uint8_t* buf, size_t bufsize)
+{
+  size_t count = 0;
+  while (count < bufsize)
+  {
+    int ch = board_getchar();
+    if ( ch <= 0 ) break;
+
+    buf[count] = (uint8_t) ch;
+    count++;
+  }
+
+  return count;
+}
+
 void cdc_app_task(void)
 {
+  uint8_t buf[64+1]; // +1 for extra null character
+  memset(buf, 0, sizeof(buf));
 
+  size_t count = get_console_inputs(buf, sizeof(buf)-1);
+
+  // loop over all mounted interfaces
+  for(size_t idx=0; idx<CFG_TUH_CDC; idx++)
+  {
+    if ( tuh_cdc_mounted(idx) )
+    {
+      // console --> cdc interfaces
+      if (count)
+      {
+        tuh_cdc_write(idx, buf, count);
+        tuh_cdc_write_flush(idx);
+      }
+
+      // cdc interfaces -> console
+      if ( tuh_cdc_read_available(idx) )
+      {
+        printf((char*) buf);
+      }
+    }
+  }
 }
 
-void tuh_cdc_mount_cb(uint8_t dev_addr)
+void tuh_cdc_mount_cb(uint8_t idx)
 {
-  (void) dev_addr;
-  printf("A CDC device is mounted\r\n");
+  tuh_cdc_itf_info_t itf_info;
+  tuh_cdc_itf_get_info(idx, &itf_info);
+
+  printf("CDC Interface is mounted: device address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
 }
 
-void tuh_cdc_umount_cb(uint8_t dev_addr)
+void tuh_cdc_umount_cb(uint8_t idx)
 {
-  (void) dev_addr;
-  printf("A CDC device is unmounted\r\n");
+  tuh_cdc_itf_info_t itf_info;
+  tuh_cdc_itf_get_info(idx, &itf_info);
+
+  printf("CDC Interface is unmounted: device address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
 }

From 76021c7359fd330f547a1c22c5c00a23aa5c2bf0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 11:49:28 +0700
Subject: [PATCH 1320/2085] rename tud_edpt_stream_write_xfer

---
 src/class/cdc/cdc_host.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 83c623884..79e29796c 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -76,7 +76,7 @@ bool tu_edpt_stream_clear(tu_edpt_stream_t* s)
   return tu_fifo_clear(&s->ff);
 }
 
-uint32_t tud_edpt_stream_write_flush(uint8_t dev_addr, tu_edpt_stream_t* s)
+uint32_t tud_edpt_stream_write_xfer(uint8_t dev_addr, tu_edpt_stream_t* s)
 {
   // No data to send
   if ( !tu_fifo_count(&s->ff) ) return 0;
@@ -114,7 +114,7 @@ uint32_t tu_edpt_stream_write(uint8_t daddr, tu_edpt_stream_t* s, void const *bu
   if ( (tu_fifo_count(&s->ff) >= bulk_packet_size)
       /* || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) */ )
   {
-    tud_edpt_stream_write_flush(daddr, s);
+    tud_edpt_stream_write_xfer(daddr, s);
   }
 
   return ret;
@@ -302,7 +302,7 @@ uint32_t tuh_cdc_write_flush(uint8_t idx)
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
-  return tud_edpt_stream_write_flush(p_cdc->daddr, &p_cdc->stream.tx);
+  return tud_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx);
 }
 
 uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize)
@@ -435,7 +435,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 
   if ( ep_addr == p_cdc->stream.tx.ep_addr )
   {
-    if ( 0 == tud_edpt_stream_write_flush(daddr, &p_cdc->stream.tx) )
+    if ( 0 == tud_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) )
     {
       // If there is no data left, a ZLP should be sent if
       // xferred_bytes is multiple of EP Packet size and not zero

From 22b62f871263ae170965a037e4f677a8a8e49709 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 12:07:12 +0700
Subject: [PATCH 1321/2085] add tu_edpt_stream_write_zlp_if_needed()

---
 src/class/cdc/cdc_host.c | 44 ++++++++++++++++++++++++----------------
 1 file changed, 26 insertions(+), 18 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 79e29796c..f8d996e17 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -76,15 +76,30 @@ bool tu_edpt_stream_clear(tu_edpt_stream_t* s)
   return tu_fifo_clear(&s->ff);
 }
 
-uint32_t tud_edpt_stream_write_xfer(uint8_t dev_addr, tu_edpt_stream_t* s)
+bool tu_edpt_stream_write_zlp_if_needed(uint8_t daddr, tu_edpt_stream_t* s, uint32_t last_xferred_bytes)
 {
-  // No data to send
-  if ( !tu_fifo_count(&s->ff) ) return 0;
+  uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+
+  // ZLP condition: no pending data, last transferred bytes is multiple of packet size
+  TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (bulk_packet_size-1))) );
+
+  if ( usbh_edpt_claim(daddr, s->ep_addr) )
+  {
+    TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, NULL, 0) );
+  }
+
+  return true;
+}
+
+uint32_t tu_edpt_stream_write_xfer(uint8_t daddr, tu_edpt_stream_t* s)
+{
+  // skip if no data
+  TU_VERIFY( tu_fifo_count(&s->ff), 0 );
 
   // Claim the endpoint
   // uint8_t const rhport = 0;
   // TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 );
-  TU_VERIFY( usbh_edpt_claim(dev_addr, s->ep_addr) );
+  TU_VERIFY( usbh_edpt_claim(daddr, s->ep_addr) );
 
   // Pull data from FIFO -> EP buf
   uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize);
@@ -92,7 +107,7 @@ uint32_t tud_edpt_stream_write_xfer(uint8_t dev_addr, tu_edpt_stream_t* s)
   if ( count )
   {
     //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
-    TU_ASSERT( usbh_edpt_xfer(dev_addr, s->ep_addr, s->ep_buf, count), 0 );
+    TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, s->ep_buf, count), 0 );
     return count;
   }else
   {
@@ -100,7 +115,7 @@ uint32_t tud_edpt_stream_write_xfer(uint8_t dev_addr, tu_edpt_stream_t* s)
     // Note: data is dropped if terminal is not connected
     //usbd_edpt_release(rhport, p_cdc->ep_in);
 
-    usbh_edpt_release(dev_addr, s->ep_addr);
+    usbh_edpt_release(daddr, s->ep_addr);
     return 0;
   }
 }
@@ -114,7 +129,7 @@ uint32_t tu_edpt_stream_write(uint8_t daddr, tu_edpt_stream_t* s, void const *bu
   if ( (tu_fifo_count(&s->ff) >= bulk_packet_size)
       /* || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) */ )
   {
-    tud_edpt_stream_write_xfer(daddr, s);
+    tu_edpt_stream_write_xfer(daddr, s);
   }
 
   return ret;
@@ -302,7 +317,7 @@ uint32_t tuh_cdc_write_flush(uint8_t idx)
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
-  return tud_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx);
+  return tu_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx);
 }
 
 uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize)
@@ -435,18 +450,11 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 
   if ( ep_addr == p_cdc->stream.tx.ep_addr )
   {
-    if ( 0 == tud_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) )
+    if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) )
     {
-      // If there is no data left, a ZLP should be sent if
+      // If there is no data left, a ZLP should be sent if needed
       // xferred_bytes is multiple of EP Packet size and not zero
-      uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
-      if ( !tu_fifo_count(&p_cdc->stream.tx.ff) && xferred_bytes && (0 == (xferred_bytes & (bulk_packet_size-1))) )
-      {
-        if ( usbh_edpt_claim(daddr, p_cdc->stream.tx.ep_addr) )
-        {
-          usbh_edpt_xfer(daddr, p_cdc->stream.tx.ep_addr, NULL, 0);
-        }
-      }
+      tu_edpt_stream_write_zlp_if_needed(daddr, &p_cdc->stream.tx, xferred_bytes);
     }
   }
   else if ( ep_addr == p_cdc->stream.rx.ep_addr )

From badb30a6c3d0748b52d7c9db5a48b7bef21b4c1a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 12:25:13 +0700
Subject: [PATCH 1322/2085] correct cdc host app

---
 examples/host/cdc_msc_hid/src/cdc_app.c | 17 +++++++++++------
 src/class/cdc/cdc_host.c                |  3 ++-
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index 123cb33f0..db652efde 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -52,26 +52,31 @@ size_t get_console_inputs(uint8_t* buf, size_t bufsize)
 void cdc_app_task(void)
 {
   uint8_t buf[64+1]; // +1 for extra null character
-  memset(buf, 0, sizeof(buf));
+  uint32_t const bufsize = sizeof(buf)-1;
 
-  size_t count = get_console_inputs(buf, sizeof(buf)-1);
+  uint32_t console_count = get_console_inputs(buf, bufsize);
+  buf[console_count] = 0;
 
   // loop over all mounted interfaces
-  for(size_t idx=0; idx<CFG_TUH_CDC; idx++)
+  for(uint8_t idx=0; idx<CFG_TUH_CDC; idx++)
   {
     if ( tuh_cdc_mounted(idx) )
     {
       // console --> cdc interfaces
-      if (count)
+      if (console_count)
       {
-        tuh_cdc_write(idx, buf, count);
+        tuh_cdc_write(idx, buf, console_count);
         tuh_cdc_write_flush(idx);
       }
 
       // cdc interfaces -> console
       if ( tuh_cdc_read_available(idx) )
       {
-        printf((char*) buf);
+        uint8_t buf_cdc[64+1];
+        uint32_t cdc_count = tuh_cdc_read(idx, buf_cdc, sizeof(buf_cdc)-1);
+        buf_cdc[cdc_count] = 0;
+
+        printf((char*) buf_cdc);
       }
     }
   }
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index f8d996e17..326567689 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -459,7 +459,8 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
   }
   else if ( ep_addr == p_cdc->stream.rx.ep_addr )
   {
-    tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
+    // skip if ZLP
+    if (xferred_bytes) tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
 
     // invoke receive callback
 

From edc559cb4d9c0c940387b514f2e66c4a2f3a9c1c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 12:29:51 +0700
Subject: [PATCH 1323/2085] fix ci

---
 src/device/usbd.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index f9a7af21b..f652a878e 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -39,13 +39,13 @@
 // USBD Configuration
 //--------------------------------------------------------------------+
 
-// Debug level of USBD
-#define USBD_DBG   2
-
 #ifndef CFG_TUD_TASK_QUEUE_SZ
   #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
 
+// Debug level of USBD
+#define USBD_DBG   2
+
 //--------------------------------------------------------------------+
 // Device Data
 //--------------------------------------------------------------------+
@@ -506,7 +506,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
       break;
 
       case DCD_EVENT_SETUP_RECEIVED:
-        TU_LOG_VAR(USBD_DBG, &event.setup_received);
+        TU_LOG_PTR(USBD_DBG, &event.setup_received);
         TU_LOG(USBD_DBG, "\r\n");
 
         // Mark as connected after receiving 1st setup packet.

From 84a483f5ea7446a5cc1a9fe957379dd1f0a6fd4c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 12:47:00 +0700
Subject: [PATCH 1324/2085] add more host cdc API

tuh_cdc_write_available(), tuh_cdc_read_flush(), tuh_cdc_rx_cb()
callback
---
 examples/host/cdc_msc_hid/src/cdc_app.c | 31 +++++++------
 src/class/cdc/cdc_host.c                | 34 ++++++++++++++
 src/class/cdc/cdc_host.h                | 60 +++++++++----------------
 3 files changed, 71 insertions(+), 54 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index db652efde..23ea05b2b 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -54,8 +54,8 @@ void cdc_app_task(void)
   uint8_t buf[64+1]; // +1 for extra null character
   uint32_t const bufsize = sizeof(buf)-1;
 
-  uint32_t console_count = get_console_inputs(buf, bufsize);
-  buf[console_count] = 0;
+  uint32_t count = get_console_inputs(buf, bufsize);
+  buf[count] = 0;
 
   // loop over all mounted interfaces
   for(uint8_t idx=0; idx<CFG_TUH_CDC; idx++)
@@ -63,25 +63,28 @@ void cdc_app_task(void)
     if ( tuh_cdc_mounted(idx) )
     {
       // console --> cdc interfaces
-      if (console_count)
+      if (count)
       {
-        tuh_cdc_write(idx, buf, console_count);
+        tuh_cdc_write(idx, buf, count);
         tuh_cdc_write_flush(idx);
       }
-
-      // cdc interfaces -> console
-      if ( tuh_cdc_read_available(idx) )
-      {
-        uint8_t buf_cdc[64+1];
-        uint32_t cdc_count = tuh_cdc_read(idx, buf_cdc, sizeof(buf_cdc)-1);
-        buf_cdc[cdc_count] = 0;
-
-        printf((char*) buf_cdc);
-      }
     }
   }
 }
 
+// Invoked when received new data
+void tuh_cdc_rx_cb(uint8_t idx)
+{
+  uint8_t buf[64+1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf)-1;
+
+  // forward cdc interfaces -> console
+  uint32_t count = tuh_cdc_read(idx, buf, bufsize);
+  buf[count] = 0;
+
+  printf((char*) buf);
+}
+
 void tuh_cdc_mount_cb(uint8_t idx)
 {
   tuh_cdc_itf_info_t itf_info;
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 326567689..ba2e9e1b7 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -185,6 +185,17 @@ uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s)
   return (uint32_t) tu_fifo_count(&s->ff);
 }
 
+uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s)
+{
+  return (uint32_t) tu_fifo_remaining(&s->ff);
+}
+
+void tu_edpt_stream_read_clear(uint8_t daddr, tu_edpt_stream_t* s)
+{
+  tu_fifo_clear(&s->ff);
+  tu_edpt_stream_read_xfer(daddr, s);
+}
+
 typedef struct {
   uint8_t daddr;
   uint8_t bInterfaceNumber;
@@ -227,6 +238,12 @@ static inline cdch_interface_t* get_itf(uint8_t idx)
   return (p_cdc->daddr != 0) ? p_cdc : NULL;
 }
 
+TU_ATTR_ALWAYS_INLINE
+static inline uint8_t itf2idx(cdch_interface_t* p_cdc)
+{
+  return (uint8_t) (p_cdc - cdch_data);
+}
+
 static inline cdch_interface_t* get_itf_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
 {
   for(uint8_t i=0; i<CFG_TUH_CDC; i++)
@@ -320,6 +337,14 @@ uint32_t tuh_cdc_write_flush(uint8_t idx)
   return tu_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx);
 }
 
+uint32_t tuh_cdc_write_available(uint8_t idx)
+{
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_write_available(&p_cdc->stream.tx);
+}
+
 uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
@@ -336,6 +361,14 @@ uint32_t tuh_cdc_read_available(uint8_t idx)
   return tu_edpt_stream_read_available(&p_cdc->stream.rx);
 }
 
+void tuh_cdc_read_flush (uint8_t idx)
+{
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc, );
+
+  tu_edpt_stream_read_clear(p_cdc->daddr, &p_cdc->stream.rx);
+}
+
 //--------------------------------------------------------------------+
 // Control Endpoint API
 //--------------------------------------------------------------------+
@@ -463,6 +496,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
     if (xferred_bytes) tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
 
     // invoke receive callback
+    if (tuh_cdc_rx_cb)  tuh_cdc_rx_cb(itf2idx(p_cdc));
 
     // prepare for next transfer if needed
     tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx);
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 54e082e7d..dd8ae80ce 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -97,18 +97,32 @@ TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx)
   return tuh_cdc_get_dtr(idx);
 }
 
+//--------------------------------------------------------------------+
+// Write API
+//--------------------------------------------------------------------+
+
+// Get the number of bytes available for writing
+uint32_t tuh_cdc_write_available(uint8_t idx);
+
 // Write to cdc interface
 uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize);
 
 // Force sending data if possible, return number of forced bytes
 uint32_t tuh_cdc_write_flush(uint8_t idx);
 
-// Read from cdc interface
-uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize);
+//--------------------------------------------------------------------+
+// Read API
+//--------------------------------------------------------------------+
 
 // Get the number of bytes available for reading
 uint32_t tuh_cdc_read_available(uint8_t idx);
 
+// Read from cdc interface
+uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize);
+
+// Clear the received FIFO
+void tuh_cdc_read_flush (uint8_t idx);
+
 //--------------------------------------------------------------------+
 // Control Endpoint (Request) API
 //--------------------------------------------------------------------+
@@ -132,47 +146,13 @@ static inline bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, ui
 
 // Invoked when a device with CDC interface is mounted
 // idx is index of cdc interface in the internal pool.
-TU_ATTR_WEAK void tuh_cdc_mount_cb(uint8_t idx);
+TU_ATTR_WEAK extern void tuh_cdc_mount_cb(uint8_t idx);
 
 // Invoked when a device with CDC interface is unmounted
-TU_ATTR_WEAK void tuh_cdc_umount_cb(uint8_t idx);
+TU_ATTR_WEAK extern void tuh_cdc_umount_cb(uint8_t idx);
 
-/** \brief      Check if the interface is currently busy or not
- * \param[in]   dev_addr device address
- * \param[in]   pipeid value from \ref cdc_pipeid_t to indicate target pipe.
- * \retval      true if the interface is busy, meaning the stack is still transferring/waiting data from/to device
- * \retval      false if the interface is not busy, meaning the stack successfully transferred data from/to device
- * \note        This function is used to check if previous transfer is complete (success or error), so that the next transfer
- *              can be scheduled. User needs to make sure the corresponding interface is mounted
- *              (by \ref tuh_cdc_serial_is_mounted) before calling this function.
- */
-// bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid);
-
-/** \brief 			Perform USB OUT transfer to device
- * \param[in]		dev_addr	device address
- * \param[in]	  p_data    Buffer containing data. Must be accessible by USB controller (see \ref CFG_TUSB_MEM_SECTION)
- * \param[in]		length    Number of bytes to be transferred via USB bus
- * \retval      TUSB_ERROR_NONE on success
- * \retval      TUSB_ERROR_INTERFACE_IS_BUSY if the interface is already transferring data with device
- * \retval      TUSB_ERROR_DEVICE_NOT_READY if device is not yet configured (by SET CONFIGURED request)
- * \retval      TUSB_ERROR_INVALID_PARA if input parameters are not correct
- * \note        This function is non-blocking and returns immediately. The result of USB transfer will be reported by the
- *              interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION.
- */
-// bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify);
-
-/** \brief 			Perform USB IN transfer to get data from device
- * \param[in]		dev_addr	device address
- * \param[in]	  p_buffer  Buffer containing received data. Must be accessible by USB controller (see \ref CFG_TUSB_MEM_SECTION)
- * \param[in]		length    Number of bytes to be transferred via USB bus
- * \retval      TUSB_ERROR_NONE on success
- * \retval      TUSB_ERROR_INTERFACE_IS_BUSY if the interface is already transferring data with device
- * \retval      TUSB_ERROR_DEVICE_NOT_READY if device is not yet configured (by SET CONFIGURED request)
- * \retval      TUSB_ERROR_INVALID_PARA if input parameters are not correct
- * \note        This function is non-blocking and returns immediately. The result of USB transfer will be reported by the
- *              interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION.
- */
-// bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify);
+// Invoked when received new data
+TU_ATTR_WEAK extern void tuh_cdc_rx_cb(uint8_t idx);
 
 //--------------------------------------------------------------------+
 // CDC APPLICATION CALLBACKS

From cd9008e5a9c8da81d9736f7e0bf72c5ba409a7f1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 13:05:45 +0700
Subject: [PATCH 1325/2085] add tuh_cdc_tx_complete_cb() callback

---
 examples/host/cdc_msc_hid/src/cdc_app.c |  4 ++--
 src/class/cdc/cdc_host.c                | 20 +++++++++-----------
 src/class/cdc/cdc_host.h                |  3 +++
 3 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index 23ea05b2b..dd3196146 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -87,7 +87,7 @@ void tuh_cdc_rx_cb(uint8_t idx)
 
 void tuh_cdc_mount_cb(uint8_t idx)
 {
-  tuh_cdc_itf_info_t itf_info;
+  tuh_cdc_itf_info_t itf_info = { 0 };
   tuh_cdc_itf_get_info(idx, &itf_info);
 
   printf("CDC Interface is mounted: device address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
@@ -95,7 +95,7 @@ void tuh_cdc_mount_cb(uint8_t idx)
 
 void tuh_cdc_umount_cb(uint8_t idx)
 {
-  tuh_cdc_itf_info_t itf_info;
+  tuh_cdc_itf_info_t itf_info = { 0 };
   tuh_cdc_itf_get_info(idx, &itf_info);
 
   printf("CDC Interface is unmounted: device address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index ba2e9e1b7..ce0efe6e3 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -238,13 +238,7 @@ static inline cdch_interface_t* get_itf(uint8_t idx)
   return (p_cdc->daddr != 0) ? p_cdc : NULL;
 }
 
-TU_ATTR_ALWAYS_INLINE
-static inline uint8_t itf2idx(cdch_interface_t* p_cdc)
-{
-  return (uint8_t) (p_cdc - cdch_data);
-}
-
-static inline cdch_interface_t* get_itf_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
+static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
 {
   for(uint8_t i=0; i<CFG_TUH_CDC; i++)
   {
@@ -252,11 +246,11 @@ static inline cdch_interface_t* get_itf_by_ep_addr(uint8_t daddr, uint8_t ep_add
     if ( (p_cdc->daddr == daddr) &&
          (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr))
     {
-      return p_cdc;
+      return i;
     }
   }
 
-  return NULL;
+  return TUSB_INDEX_INVALID;
 }
 
 
@@ -478,11 +472,15 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
   // TODO handle stall response, retry failed transfer ...
   TU_ASSERT(event == XFER_RESULT_SUCCESS);
 
-  cdch_interface_t * p_cdc = get_itf_by_ep_addr(daddr, ep_addr);
+  uint8_t const idx = get_idx_by_ep_addr(daddr, ep_addr);
+  cdch_interface_t * p_cdc = get_itf(idx);
   TU_ASSERT(p_cdc);
 
   if ( ep_addr == p_cdc->stream.tx.ep_addr )
   {
+    // invoke tx complete callback to possibly refill tx fifo
+    if (tuh_cdc_tx_complete_cb) tuh_cdc_tx_complete_cb(idx);
+
     if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) )
     {
       // If there is no data left, a ZLP should be sent if needed
@@ -496,7 +494,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
     if (xferred_bytes) tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
 
     // invoke receive callback
-    if (tuh_cdc_rx_cb)  tuh_cdc_rx_cb(itf2idx(p_cdc));
+    if (tuh_cdc_rx_cb)  tuh_cdc_rx_cb(idx);
 
     // prepare for next transfer if needed
     tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx);
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index dd8ae80ce..476431cc5 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -154,6 +154,9 @@ TU_ATTR_WEAK extern void tuh_cdc_umount_cb(uint8_t idx);
 // Invoked when received new data
 TU_ATTR_WEAK extern void tuh_cdc_rx_cb(uint8_t idx);
 
+// Invoked when a TX is complete and therefore space becomes available in TX buffer
+TU_ATTR_WEAK extern void tuh_cdc_tx_complete_cb(uint8_t idx);
+
 //--------------------------------------------------------------------+
 // CDC APPLICATION CALLBACKS
 //--------------------------------------------------------------------+

From 9e8ea44925e80abd7189ed7a673762527ee3adfd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 21 Dec 2022 17:46:11 +0700
Subject: [PATCH 1326/2085] add tuh_cdc_write_clear, rename read_flush() to
 read_clear()

---
 src/class/cdc/cdc_host.c | 24 +++++++++++++++++++-----
 src/class/cdc/cdc_host.h |  5 ++++-
 2 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index ce0efe6e3..2f3406378 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -190,10 +190,16 @@ uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s)
   return (uint32_t) tu_fifo_remaining(&s->ff);
 }
 
-void tu_edpt_stream_read_clear(uint8_t daddr, tu_edpt_stream_t* s)
+bool tu_edpt_stream_read_clear(uint8_t daddr, tu_edpt_stream_t* s)
 {
-  tu_fifo_clear(&s->ff);
+  bool ret = tu_fifo_clear(&s->ff);
   tu_edpt_stream_read_xfer(daddr, s);
+  return ret;
+}
+
+bool tu_edpt_stream_write_clear(tu_edpt_stream_t* s)
+{
+  return tu_fifo_clear(&s->ff);
 }
 
 typedef struct {
@@ -331,6 +337,14 @@ uint32_t tuh_cdc_write_flush(uint8_t idx)
   return tu_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx);
 }
 
+bool tuh_cdc_write_clear(uint8_t idx)
+{
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_write_clear(&p_cdc->stream.tx);
+}
+
 uint32_t tuh_cdc_write_available(uint8_t idx)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
@@ -355,12 +369,12 @@ uint32_t tuh_cdc_read_available(uint8_t idx)
   return tu_edpt_stream_read_available(&p_cdc->stream.rx);
 }
 
-void tuh_cdc_read_flush (uint8_t idx)
+bool tuh_cdc_read_clear (uint8_t idx)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
-  TU_VERIFY(p_cdc, );
+  TU_VERIFY(p_cdc);
 
-  tu_edpt_stream_read_clear(p_cdc->daddr, &p_cdc->stream.rx);
+  return tu_edpt_stream_read_clear(p_cdc->daddr, &p_cdc->stream.rx);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 476431cc5..02ae69111 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -110,6 +110,9 @@ uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize);
 // Force sending data if possible, return number of forced bytes
 uint32_t tuh_cdc_write_flush(uint8_t idx);
 
+// Clear the transmit FIFO
+bool tuh_cdc_write_clear(uint8_t idx);
+
 //--------------------------------------------------------------------+
 // Read API
 //--------------------------------------------------------------------+
@@ -121,7 +124,7 @@ uint32_t tuh_cdc_read_available(uint8_t idx);
 uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize);
 
 // Clear the received FIFO
-void tuh_cdc_read_flush (uint8_t idx);
+bool tuh_cdc_read_clear (uint8_t idx);
 
 //--------------------------------------------------------------------+
 // Control Endpoint (Request) API

From 8323e4b79a2052aee814ca8811e841bceb6a7a7d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Dec 2022 00:34:35 +0700
Subject: [PATCH 1327/2085] moving edpt_stream API into common tusb.c

---
 src/class/cdc/cdc_host.c    | 179 ++++++++----------------------------
 src/common/tusb_private.h   |  92 +++++++++++++++++-
 src/host/usbh.c             |   1 -
 src/host/usbh_classdriver.h |   1 +
 src/tusb.c                  | 112 +++++++++++++++++++++-
 5 files changed, 239 insertions(+), 146 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 2f3406378..54d81dc0d 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -42,56 +42,23 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-typedef struct {
-  tu_fifo_t ff;
 
-  // mutex: read if ep rx, write if e tx
-  OSAL_MUTEX_DEF(ff_mutex);
-
-  // TODO xfer_fifo can skip this buffer
-  uint8_t* ep_buf;
-  uint16_t ep_bufsize;
-  uint8_t ep_addr;
-}tu_edpt_stream_t;
-
-bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool use_wr_mutex, bool overwritable,
-                         void* ff_buf, uint16_t ff_bufsize,
-                         uint8_t* ep_buf, uint16_t ep_bufsize)
+bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes)
 {
-  osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex);
-  (void) new_mutex;
-  (void) use_wr_mutex;
-
-  tu_fifo_config(&s->ff, ff_buf, ff_bufsize, 1, overwritable);
-  tu_fifo_config_mutex(&s->ff, use_wr_mutex ? new_mutex : NULL, use_wr_mutex ? NULL : new_mutex);
-
-  s->ep_buf = ep_buf;
-  s->ep_bufsize = ep_bufsize;
-
-  return true;
-}
-
-bool tu_edpt_stream_clear(tu_edpt_stream_t* s)
-{
-  return tu_fifo_clear(&s->ff);
-}
-
-bool tu_edpt_stream_write_zlp_if_needed(uint8_t daddr, tu_edpt_stream_t* s, uint32_t last_xferred_bytes)
-{
-  uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+  uint16_t const bulk_packet_size = (s->ep_speed == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
 
   // ZLP condition: no pending data, last transferred bytes is multiple of packet size
   TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (bulk_packet_size-1))) );
 
-  if ( usbh_edpt_claim(daddr, s->ep_addr) )
+  if ( usbh_edpt_claim(s->daddr, s->ep_addr) )
   {
-    TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, NULL, 0) );
+    TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, NULL, 0) );
   }
 
   return true;
 }
 
-uint32_t tu_edpt_stream_write_xfer(uint8_t daddr, tu_edpt_stream_t* s)
+uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s)
 {
   // skip if no data
   TU_VERIFY( tu_fifo_count(&s->ff), 0 );
@@ -99,7 +66,7 @@ uint32_t tu_edpt_stream_write_xfer(uint8_t daddr, tu_edpt_stream_t* s)
   // Claim the endpoint
   // uint8_t const rhport = 0;
   // TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 );
-  TU_VERIFY( usbh_edpt_claim(daddr, s->ep_addr) );
+  TU_VERIFY( usbh_edpt_claim(s->daddr, s->ep_addr) );
 
   // Pull data from FIFO -> EP buf
   uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize);
@@ -107,7 +74,7 @@ uint32_t tu_edpt_stream_write_xfer(uint8_t daddr, tu_edpt_stream_t* s)
   if ( count )
   {
     //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
-    TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, s->ep_buf, count), 0 );
+    TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 );
     return count;
   }else
   {
@@ -115,93 +82,28 @@ uint32_t tu_edpt_stream_write_xfer(uint8_t daddr, tu_edpt_stream_t* s)
     // Note: data is dropped if terminal is not connected
     //usbd_edpt_release(rhport, p_cdc->ep_in);
 
-    usbh_edpt_release(daddr, s->ep_addr);
+    usbh_edpt_release(s->daddr, s->ep_addr);
     return 0;
   }
 }
 
-uint32_t tu_edpt_stream_write(uint8_t daddr, tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize)
+uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize)
 {
+  TU_VERIFY(bufsize); // TODO support ZLP
+
   uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
 
-  // flush if queue more than packet size
-  uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
-  if ( (tu_fifo_count(&s->ff) >= bulk_packet_size)
-      /* || ((CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE) && tu_fifo_full(&p_cdc->tx_ff)) */ )
+  // flush if fifo has more than packet size or
+  // in rare case: fifo depth is configured too small (which never reach packet size)
+  uint16_t const bulk_packet_size = (s->ep_speed == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
+  if ( (tu_fifo_count(&s->ff) >= bulk_packet_size) || ( tu_fifo_depth(&s->ff) < bulk_packet_size) )
   {
-    tu_edpt_stream_write_xfer(daddr, s);
+    tu_edpt_stream_write_xfer(s);
   }
 
   return ret;
 }
 
-void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes)
-{
-  tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes);
-}
-
-uint32_t tu_edpt_stream_read_xfer(uint8_t daddr, tu_edpt_stream_t* s)
-{
-  uint16_t available = tu_fifo_remaining(&s->ff);
-
-  // Prepare for incoming data but only allow what we can store in the ring buffer.
-  // TODO Actually we can still carry out the transfer, keeping count of received bytes
-  // and slowly move it to the FIFO when read().
-  // This pre-check reduces endpoint claiming
-  uint16_t const bulk_packet_size = (tuh_speed_get(daddr) == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
-  TU_VERIFY(available >= bulk_packet_size);
-
-  // claim endpoint
-  TU_VERIFY(usbh_edpt_claim(daddr, s->ep_addr), 0);
-
-  // fifo can be changed before endpoint is claimed
-  available = tu_fifo_remaining(&s->ff);
-
-  if ( available >= bulk_packet_size )
-  {
-    // multiple of packet size limit by ep bufsize
-    uint16_t count = (uint16_t) (available & (bulk_packet_size -1));
-    count = tu_min16(count, s->ep_bufsize);
-
-    TU_ASSERT( usbh_edpt_xfer(daddr, s->ep_addr, s->ep_buf, count), 0 );
-    return count;
-  }else
-  {
-    // Release endpoint since we don't make any transfer
-    usbh_edpt_release(daddr, s->ep_addr);
-    return 0;
-  }
-}
-
-uint32_t tu_edpt_stream_read(uint8_t daddr, tu_edpt_stream_t* s, void* buffer, uint32_t bufsize)
-{
-  uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize);
-  tu_edpt_stream_read_xfer(daddr, s);
-  return num_read;
-}
-
-uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s)
-{
-  return (uint32_t) tu_fifo_count(&s->ff);
-}
-
-uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s)
-{
-  return (uint32_t) tu_fifo_remaining(&s->ff);
-}
-
-bool tu_edpt_stream_read_clear(uint8_t daddr, tu_edpt_stream_t* s)
-{
-  bool ret = tu_fifo_clear(&s->ff);
-  tu_edpt_stream_read_xfer(daddr, s);
-  return ret;
-}
-
-bool tu_edpt_stream_write_clear(tu_edpt_stream_t* s)
-{
-  return tu_fifo_clear(&s->ff);
-}
-
 typedef struct {
   uint8_t daddr;
   uint8_t bInterfaceNumber;
@@ -326,7 +228,7 @@ uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize)
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
-  return tu_edpt_stream_write(p_cdc->daddr, &p_cdc->stream.tx, buffer, bufsize);
+  return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize);
 }
 
 uint32_t tuh_cdc_write_flush(uint8_t idx)
@@ -334,7 +236,7 @@ uint32_t tuh_cdc_write_flush(uint8_t idx)
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
-  return tu_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx);
+  return tu_edpt_stream_write_xfer(&p_cdc->stream.tx);
 }
 
 bool tuh_cdc_write_clear(uint8_t idx)
@@ -342,7 +244,7 @@ bool tuh_cdc_write_clear(uint8_t idx)
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
-  return tu_edpt_stream_write_clear(&p_cdc->stream.tx);
+  return tu_edpt_stream_clear(&p_cdc->stream.tx);
 }
 
 uint32_t tuh_cdc_write_available(uint8_t idx)
@@ -358,7 +260,7 @@ uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize)
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
-  return tu_edpt_stream_read(p_cdc->daddr, &p_cdc->stream.rx, buffer, bufsize);
+  return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize);
 }
 
 uint32_t tuh_cdc_read_available(uint8_t idx)
@@ -374,7 +276,9 @@ bool tuh_cdc_read_clear (uint8_t idx)
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
 
-  return tu_edpt_stream_read_clear(p_cdc->daddr, &p_cdc->stream.rx);
+  bool ret = tu_edpt_stream_clear(&p_cdc->stream.rx);
+  tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
+  return ret;
 }
 
 //--------------------------------------------------------------------+
@@ -452,13 +356,13 @@ void cdch_init(void)
   {
     cdch_interface_t* p_cdc = &cdch_data[i];
 
-    tu_edpt_stream_init(&p_cdc->stream.tx, true, false,
-                        p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
-                        p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
+    tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false,
+                          p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
+                          p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
 
-    tu_edpt_stream_init(&p_cdc->stream.rx, false, false,
-                        p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
-                        p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
+    tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false,
+                          p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
+                          p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
   }
 }
 
@@ -475,8 +379,6 @@ void cdch_close(uint8_t daddr)
       //tu_memclr(p_cdc, sizeof(cdch_interface_t));
       p_cdc->daddr = 0;
       p_cdc->bInterfaceNumber = 0;
-      tu_edpt_stream_clear(&p_cdc->stream.tx);
-      tu_edpt_stream_clear(&p_cdc->stream.rx);
     }
   }
 }
@@ -495,23 +397,22 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
     // invoke tx complete callback to possibly refill tx fifo
     if (tuh_cdc_tx_complete_cb) tuh_cdc_tx_complete_cb(idx);
 
-    if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) )
+    if ( 0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx) )
     {
       // If there is no data left, a ZLP should be sent if needed
       // xferred_bytes is multiple of EP Packet size and not zero
-      tu_edpt_stream_write_zlp_if_needed(daddr, &p_cdc->stream.tx, xferred_bytes);
+      tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes);
     }
   }
   else if ( ep_addr == p_cdc->stream.rx.ep_addr )
   {
-    // skip if ZLP
-    if (xferred_bytes) tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
+    tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
 
     // invoke receive callback
     if (tuh_cdc_rx_cb)  tuh_cdc_rx_cb(idx);
 
     // prepare for next transfer if needed
-    tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx);
+    tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
   }else if ( ep_addr == p_cdc->ep_notif )
   {
     // TODO handle notification endpoint
@@ -527,7 +428,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 // Enumeration
 //--------------------------------------------------------------------+
 
-bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
+bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
   (void) rhport;
 
@@ -542,7 +443,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
   cdch_interface_t * p_cdc = find_new_itf();
   TU_VERIFY(p_cdc);
 
-  p_cdc->daddr              = dev_addr;
+  p_cdc->daddr              = daddr;
   p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
   p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
   p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol;
@@ -569,7 +470,7 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
     TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc));
     tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
 
-    TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) );
+    TU_ASSERT( tuh_edpt_open(daddr, desc_ep) );
     p_cdc->ep_notif = desc_ep->bEndpointAddress;
 
     p_desc = tu_desc_next(p_desc);
@@ -589,14 +490,14 @@ bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *it
       TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType &&
                 TUSB_XFER_BULK     == desc_ep->bmAttributes.xfer);
 
-      TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep));
+      TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
 
       if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
       {
-        p_cdc->stream.rx.ep_addr = desc_ep->bEndpointAddress;
+        tu_edpt_stream_open(&p_cdc->stream.rx, daddr, desc_ep);
       }else
       {
-        p_cdc->stream.tx.ep_addr = desc_ep->bEndpointAddress;
+        tu_edpt_stream_open(&p_cdc->stream.tx, daddr, desc_ep);
       }
 
       p_desc = tu_desc_next(p_desc);
@@ -616,7 +517,7 @@ static void config_cdc_complete(uint8_t daddr, uint8_t itf_num)
 
     // Prepare for incoming data
     cdch_interface_t* p_cdc = get_itf(idx);
-    tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx);
+    tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
   }
 
   // notify usbh that driver enumeration is complete
diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
index b34506f65..01078eed3 100644
--- a/src/common/tusb_private.h
+++ b/src/common/tusb_private.h
@@ -28,6 +28,8 @@
 #ifndef _TUSB_PRIVATE_H_
 #define _TUSB_PRIVATE_H_
 
+// Internal Helper used by Host and Device Stack
+
 #ifdef __cplusplus
  extern "C" {
 #endif
@@ -39,8 +41,31 @@ typedef struct TU_ATTR_PACKED
   volatile uint8_t claimed : 1;
 }tu_edpt_state_t;
 
+typedef struct {
+  bool is_host; // host or device most
+  union {
+      uint8_t daddr;
+      uint8_t rhport;
+      uint8_t hwid;
+  };
+  uint8_t ep_addr;
+  uint8_t ep_speed;
+
+  uint16_t ep_packetsize;
+  uint16_t ep_bufsize;
+
+  // TODO xfer_fifo can skip this buffer
+  uint8_t* ep_buf;
+
+  tu_fifo_t ff;
+
+  // mutex: read if ep rx, write if e tx
+  OSAL_MUTEX_DEF(ff_mutex);
+
+}tu_edpt_stream_t;
+
 //--------------------------------------------------------------------+
-// Internal Helper used by Host and Device Stack
+// Endpoint
 //--------------------------------------------------------------------+
 
 // Check if endpoint descriptor is valid per USB specs
@@ -58,6 +83,71 @@ bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
 // Release an endpoint with provided mutex
 bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
 
+//--------------------------------------------------------------------+
+// Endpoint Stream
+//--------------------------------------------------------------------+
+
+// Init an stream, should only called once
+bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable,
+                         void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize);
+
+// Open an stream for an endpoint
+// hwid is either device address (host mode) or rhport (device mode)
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t const *desc_ep)
+{
+  tu_fifo_clear(&s->ff);
+  s->hwid = hwid;
+  s->ep_addr = desc_ep->bEndpointAddress;
+  s->ep_packetsize = tu_edpt_packet_size(desc_ep);
+}
+
+// Clear fifo
+TU_ATTR_ALWAYS_INLINE static inline
+bool tu_edpt_stream_clear(tu_edpt_stream_t* s)
+{
+  return tu_fifo_clear(&s->ff);
+}
+
+//------------- Write -------------//
+
+// Write to stream
+uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize);
+
+// Start an usb transfer if endpoint is not busy
+uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s);
+
+// Get the number of bytes available for writing
+TU_ATTR_ALWAYS_INLINE static inline
+uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s)
+{
+  return (uint32_t) tu_fifo_remaining(&s->ff);
+}
+
+
+//------------- Read -------------//
+
+// Read from stream
+uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize);
+
+// Start an usb transfer if endpoint is not busy
+uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s);
+
+// Must be called in the transfer complete callback
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes)
+{
+  tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes);
+}
+
+// Get the number of bytes available for reading
+TU_ATTR_ALWAYS_INLINE static inline
+uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s)
+{
+  return (uint32_t) tu_fifo_count(&s->ff);
+}
+
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 36fc5fded..f0ca7be2e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -30,7 +30,6 @@
 
 #include "host/hcd.h"
 #include "tusb.h"
-#include "common/tusb_private.h"
 #include "host/usbh_classdriver.h"
 #include "hub.h"
 
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index 7f72560c3..be9811641 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -29,6 +29,7 @@
 
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
+#include "common/tusb_private.h"
 
 #ifdef __cplusplus
  extern "C" {
diff --git a/src/tusb.c b/src/tusb.c
index f4380f89c..05e0d4c1f 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -31,11 +31,18 @@
 #include "tusb.h"
 #include "common/tusb_private.h"
 
-// TODO clean up
 #if CFG_TUD_ENABLED
 #include "device/usbd_pvt.h"
 #endif
 
+#if CFG_TUH_ENABLED
+#include "host/usbh_classdriver.h"
+#endif
+
+//--------------------------------------------------------------------+
+// Public API
+//--------------------------------------------------------------------+
+
 bool tusb_init(void)
 {
 #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT)
@@ -67,7 +74,7 @@ bool tusb_inited(void)
 }
 
 //--------------------------------------------------------------------+
-// Internal Helper for both Host and Device stack
+// Endpoint Helper for both Host and Device stack
 //--------------------------------------------------------------------+
 
 bool tu_edpt_claim(tu_edpt_state_t* ep_state, osal_mutex_t mutex)
@@ -196,9 +203,104 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf,
   return len;
 }
 
-/*------------------------------------------------------------------*/
-/* Debug
- *------------------------------------------------------------------*/
+//--------------------------------------------------------------------+
+// Endpoint Stream Helper for both Host and Device stack
+//--------------------------------------------------------------------+
+
+bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable,
+                         void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize)
+{
+  osal_mutex_t new_mutex = osal_mutex_create(&s->ff_mutex);
+  (void) new_mutex;
+  (void) is_tx;
+
+  s->is_host = is_host;
+  tu_fifo_config(&s->ff, ff_buf, ff_bufsize, 1, overwritable);
+  tu_fifo_config_mutex(&s->ff, is_tx ? new_mutex : NULL, is_tx ? NULL : new_mutex);
+
+  s->ep_buf = ep_buf;
+  s->ep_bufsize = ep_bufsize;
+
+  return true;
+}
+
+//------------- Stream Write -------------//
+
+//------------- Stream Read -------------//
+
+uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s)
+{
+  uint16_t available = tu_fifo_remaining(&s->ff);
+
+  // Prepare for incoming data but only allow what we can store in the ring buffer.
+  // TODO Actually we can still carry out the transfer, keeping count of received bytes
+  // and slowly move it to the FIFO when read().
+  // This pre-check reduces endpoint claiming
+  TU_VERIFY(available >= s->ep_packetsize);
+
+  // claim endpoint
+  if (s->is_host)
+  {
+    #if CFG_TUH_ENABLED
+    TU_VERIFY(usbh_edpt_claim(s->daddr, s->ep_addr), 0);
+    #endif
+  }else
+  {
+    #if CFG_TUD_ENABLED
+    TU_VERIFY(usbd_edpt_claim(s->rhport, s->ep_addr), 0);
+    #endif
+  }
+
+  // get available again since fifo can be changed before endpoint is claimed
+  available = tu_fifo_remaining(&s->ff);
+
+  if ( available >= s->ep_packetsize )
+  {
+    // multiple of packet size limit by ep bufsize
+    uint16_t count = (uint16_t) (available & (s->ep_packetsize -1));
+    count = tu_min16(count, s->ep_bufsize);
+
+    if (s->is_host)
+    {
+      #if CFG_TUH_ENABLED
+      TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 );
+      #endif
+    }else
+    {
+      #if CFG_TUD_ENABLED
+      TU_ASSERT( usbd_edpt_xfer(s->rhport, s->ep_addr, s->ep_buf, count), 0 );
+      #endif
+    }
+    return count;
+  }else
+  {
+    // Release endpoint since we don't make any transfer
+    if (s->is_host)
+    {
+      #if CFG_TUH_ENABLED
+      usbh_edpt_release(s->daddr, s->ep_addr);
+      #endif
+    }else
+    {
+      #if CFG_TUD_ENABLED
+      usbd_edpt_release(s->rhport, s->ep_addr);
+      #endif
+    }
+
+    return 0;
+  }
+}
+
+uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize)
+{
+  uint32_t num_read = tu_fifo_read_n(&s->ff, buffer, (uint16_t) bufsize);
+  tu_edpt_stream_read_xfer(s);
+  return num_read;
+}
+
+//--------------------------------------------------------------------+
+// Debug
+//--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG
 #include <ctype.h>
 

From e3c9d9450009f757b9ddf5f94a00f14e7cfb0471 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Dec 2022 11:16:39 +0700
Subject: [PATCH 1328/2085] fix stream read count computation

---
 src/class/cdc/cdc_host.c  | 63 +------------------------
 src/common/tusb_private.h | 21 +++++++--
 src/tusb.c                | 96 +++++++++++++++++++++++++++++++++------
 3 files changed, 101 insertions(+), 79 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 54d81dc0d..469725e72 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -43,67 +43,6 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes)
-{
-  uint16_t const bulk_packet_size = (s->ep_speed == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
-
-  // ZLP condition: no pending data, last transferred bytes is multiple of packet size
-  TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (bulk_packet_size-1))) );
-
-  if ( usbh_edpt_claim(s->daddr, s->ep_addr) )
-  {
-    TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, NULL, 0) );
-  }
-
-  return true;
-}
-
-uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s)
-{
-  // skip if no data
-  TU_VERIFY( tu_fifo_count(&s->ff), 0 );
-
-  // Claim the endpoint
-  // uint8_t const rhport = 0;
-  // TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 );
-  TU_VERIFY( usbh_edpt_claim(s->daddr, s->ep_addr) );
-
-  // Pull data from FIFO -> EP buf
-  uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize);
-
-  if ( count )
-  {
-    //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
-    TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 );
-    return count;
-  }else
-  {
-    // Release endpoint since we don't make any transfer
-    // Note: data is dropped if terminal is not connected
-    //usbd_edpt_release(rhport, p_cdc->ep_in);
-
-    usbh_edpt_release(s->daddr, s->ep_addr);
-    return 0;
-  }
-}
-
-uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize)
-{
-  TU_VERIFY(bufsize); // TODO support ZLP
-
-  uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
-
-  // flush if fifo has more than packet size or
-  // in rare case: fifo depth is configured too small (which never reach packet size)
-  uint16_t const bulk_packet_size = (s->ep_speed == TUSB_SPEED_HIGH) ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS;
-  if ( (tu_fifo_count(&s->ff) >= bulk_packet_size) || ( tu_fifo_depth(&s->ff) < bulk_packet_size) )
-  {
-    tu_edpt_stream_write_xfer(s);
-  }
-
-  return ret;
-}
-
 typedef struct {
   uint8_t daddr;
   uint8_t bInterfaceNumber;
@@ -379,6 +318,8 @@ void cdch_close(uint8_t daddr)
       //tu_memclr(p_cdc, sizeof(cdch_interface_t));
       p_cdc->daddr = 0;
       p_cdc->bInterfaceNumber = 0;
+      tu_edpt_stream_close(&p_cdc->stream.tx);
+      tu_edpt_stream_close(&p_cdc->stream.rx);
     }
   }
 }
diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
index 01078eed3..d0c7a84fb 100644
--- a/src/common/tusb_private.h
+++ b/src/common/tusb_private.h
@@ -87,7 +87,7 @@ bool tu_edpt_release(tu_edpt_state_t* ep_state, osal_mutex_t mutex);
 // Endpoint Stream
 //--------------------------------------------------------------------+
 
-// Init an stream, should only called once
+// Init an stream, should only be called once
 bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool overwritable,
                          void* ff_buf, uint16_t ff_bufsize, uint8_t* ep_buf, uint16_t ep_bufsize);
 
@@ -102,6 +102,13 @@ void tu_edpt_stream_open(tu_edpt_stream_t* s, uint8_t hwid, tusb_desc_endpoint_t
   s->ep_packetsize = tu_edpt_packet_size(desc_ep);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_edpt_stream_close(tu_edpt_stream_t* s)
+{
+  s->hwid = 0;
+  s->ep_addr = 0;
+}
+
 // Clear fifo
 TU_ATTR_ALWAYS_INLINE static inline
 bool tu_edpt_stream_clear(tu_edpt_stream_t* s)
@@ -109,7 +116,9 @@ bool tu_edpt_stream_clear(tu_edpt_stream_t* s)
   return tu_fifo_clear(&s->ff);
 }
 
-//------------- Write -------------//
+//--------------------------------------------------------------------+
+// Stream Write
+//--------------------------------------------------------------------+
 
 // Write to stream
 uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize);
@@ -117,6 +126,9 @@ uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t
 // Start an usb transfer if endpoint is not busy
 uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s);
 
+// Start an zero-length packet if needed
+bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes);
+
 // Get the number of bytes available for writing
 TU_ATTR_ALWAYS_INLINE static inline
 uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s)
@@ -124,8 +136,9 @@ uint32_t tu_edpt_stream_write_available(tu_edpt_stream_t* s)
   return (uint32_t) tu_fifo_remaining(&s->ff);
 }
 
-
-//------------- Read -------------//
+//--------------------------------------------------------------------+
+// Stream Read
+//--------------------------------------------------------------------+
 
 // Read from stream
 uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize);
diff --git a/src/tusb.c b/src/tusb.c
index 05e0d4c1f..0d0e84a49 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -224,9 +224,86 @@ bool tu_edpt_stream_init(tu_edpt_stream_t* s, bool is_host, bool is_tx, bool ove
   return true;
 }
 
-//------------- Stream Write -------------//
+TU_ATTR_ALWAYS_INLINE static inline
+bool stream_claim(tu_edpt_stream_t* s)
+{
+  if (s->is_host)
+  {
+    #if CFG_TUH_ENABLED
+    return usbh_edpt_claim(s->daddr, s->ep_addr);
+    #endif
+  }else
+  {
+    #if CFG_TUD_ENABLED
+    return usbd_edpt_claim(s->rhport, s->ep_addr);
+    #endif
+  }
 
-//------------- Stream Read -------------//
+  return false;
+}
+
+
+//--------------------------------------------------------------------+
+// Stream Write
+//--------------------------------------------------------------------+
+
+bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferred_bytes)
+{
+  // ZLP condition: no pending data, last transferred bytes is multiple of packet size
+  TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize-1))) );
+
+  TU_VERIFY( stream_claim(s) );
+  TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, NULL, 0) );
+
+  return true;
+}
+
+uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s)
+{
+  // skip if no data
+  TU_VERIFY( tu_fifo_count(&s->ff), 0 );
+
+  // Claim the endpoint
+  TU_VERIFY( stream_claim(s), 0 );
+
+  // Pull data from FIFO -> EP buf
+  uint16_t const count = tu_fifo_read_n(&s->ff, s->ep_buf, s->ep_bufsize);
+
+  if ( count )
+  {
+    //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
+    TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 );
+    return count;
+  }else
+  {
+    // Release endpoint since we don't make any transfer
+    // Note: data is dropped if terminal is not connected
+    //usbd_edpt_release(rhport, p_cdc->ep_in);
+
+    usbh_edpt_release(s->daddr, s->ep_addr);
+    return 0;
+  }
+}
+
+uint32_t tu_edpt_stream_write(tu_edpt_stream_t* s, void const *buffer, uint32_t bufsize)
+{
+  TU_VERIFY(bufsize); // TODO support ZLP
+
+  uint16_t ret = tu_fifo_write_n(&s->ff, buffer, (uint16_t) bufsize);
+
+  // flush if fifo has more than packet size or
+  // in rare case: fifo depth is configured too small (which never reach packet size)
+  if ( (tu_fifo_count(&s->ff) >= s->ep_packetsize) || (tu_fifo_depth(&s->ff) < s->ep_packetsize) )
+  {
+    tu_edpt_stream_write_xfer(s);
+  }
+
+  return ret;
+}
+
+//--------------------------------------------------------------------+
+// Stream Read
+//--------------------------------------------------------------------+
 
 uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s)
 {
@@ -239,17 +316,7 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s)
   TU_VERIFY(available >= s->ep_packetsize);
 
   // claim endpoint
-  if (s->is_host)
-  {
-    #if CFG_TUH_ENABLED
-    TU_VERIFY(usbh_edpt_claim(s->daddr, s->ep_addr), 0);
-    #endif
-  }else
-  {
-    #if CFG_TUD_ENABLED
-    TU_VERIFY(usbd_edpt_claim(s->rhport, s->ep_addr), 0);
-    #endif
-  }
+  TU_VERIFY(stream_claim(s), 0);
 
   // get available again since fifo can be changed before endpoint is claimed
   available = tu_fifo_remaining(&s->ff);
@@ -257,7 +324,7 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s)
   if ( available >= s->ep_packetsize )
   {
     // multiple of packet size limit by ep bufsize
-    uint16_t count = (uint16_t) (available & (s->ep_packetsize -1));
+    uint16_t count = (uint16_t) (available & ~(s->ep_packetsize -1));
     count = tu_min16(count, s->ep_bufsize);
 
     if (s->is_host)
@@ -301,6 +368,7 @@ uint32_t tu_edpt_stream_read(tu_edpt_stream_t* s, void* buffer, uint32_t bufsize
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
+
 #if CFG_TUSB_DEBUG
 #include <ctype.h>
 

From 2d536123c8ff8dd233656f0a9d7c16aff606302d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Dec 2022 11:31:37 +0700
Subject: [PATCH 1329/2085] finish moving edpt stream to tusb.c

---
 src/class/cdc/cdc_host.c |  4 +--
 src/tusb.c               | 69 ++++++++++++++++++++++++----------------
 2 files changed, 43 insertions(+), 30 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 469725e72..de1466cb1 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -340,8 +340,8 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 
     if ( 0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx) )
     {
-      // If there is no data left, a ZLP should be sent if needed
-      // xferred_bytes is multiple of EP Packet size and not zero
+      // If there is no data left, a ZLP should be sent if:
+      // - xferred_bytes is multiple of EP Packet size and not zero
       tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes);
     }
   }
diff --git a/src/tusb.c b/src/tusb.c
index 0d0e84a49..8f64f4acf 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -242,6 +242,41 @@ bool stream_claim(tu_edpt_stream_t* s)
   return false;
 }
 
+TU_ATTR_ALWAYS_INLINE static inline
+bool stream_xfer(tu_edpt_stream_t* s, uint16_t count)
+{
+  if (s->is_host)
+  {
+    #if CFG_TUH_ENABLED
+    return usbh_edpt_xfer(s->daddr, s->ep_addr, count ? s->ep_buf : NULL, count);
+    #endif
+  }else
+  {
+    #if CFG_TUD_ENABLED
+    return usbd_edpt_xfer(s->rhport, s->ep_addr, cont ? s->ep_buf : NULL, count);
+    #endif
+  }
+
+  return false;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline
+bool stream_release(tu_edpt_stream_t* s)
+{
+  if (s->is_host)
+  {
+    #if CFG_TUH_ENABLED
+    return usbh_edpt_release(s->daddr, s->ep_addr);
+    #endif
+  }else
+  {
+    #if CFG_TUD_ENABLED
+    return usbd_edpt_release(s->rhport, s->ep_addr);
+    #endif
+  }
+
+  return false;
+}
 
 //--------------------------------------------------------------------+
 // Stream Write
@@ -253,7 +288,7 @@ bool tu_edpt_stream_write_zlp_if_needed(tu_edpt_stream_t* s, uint32_t last_xferr
   TU_VERIFY( !tu_fifo_count(&s->ff) && last_xferred_bytes && (0 == (last_xferred_bytes & (s->ep_packetsize-1))) );
 
   TU_VERIFY( stream_claim(s) );
-  TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, NULL, 0) );
+  TU_ASSERT( stream_xfer(s, 0) );
 
   return true;
 }
@@ -271,16 +306,13 @@ uint32_t tu_edpt_stream_write_xfer(tu_edpt_stream_t* s)
 
   if ( count )
   {
-    //TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
-    TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 );
+    TU_ASSERT( stream_xfer(s, count), 0 );
     return count;
   }else
   {
     // Release endpoint since we don't make any transfer
     // Note: data is dropped if terminal is not connected
-    //usbd_edpt_release(rhport, p_cdc->ep_in);
-
-    usbh_edpt_release(s->daddr, s->ep_addr);
+    stream_release(s);
     return 0;
   }
 }
@@ -327,32 +359,13 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s)
     uint16_t count = (uint16_t) (available & ~(s->ep_packetsize -1));
     count = tu_min16(count, s->ep_bufsize);
 
-    if (s->is_host)
-    {
-      #if CFG_TUH_ENABLED
-      TU_ASSERT( usbh_edpt_xfer(s->daddr, s->ep_addr, s->ep_buf, count), 0 );
-      #endif
-    }else
-    {
-      #if CFG_TUD_ENABLED
-      TU_ASSERT( usbd_edpt_xfer(s->rhport, s->ep_addr, s->ep_buf, count), 0 );
-      #endif
-    }
+    TU_ASSERT( stream_xfer(s, count), 0 );
+
     return count;
   }else
   {
     // Release endpoint since we don't make any transfer
-    if (s->is_host)
-    {
-      #if CFG_TUH_ENABLED
-      usbh_edpt_release(s->daddr, s->ep_addr);
-      #endif
-    }else
-    {
-      #if CFG_TUD_ENABLED
-      usbd_edpt_release(s->rhport, s->ep_addr);
-      #endif
-    }
+    stream_release(s);
 
     return 0;
   }

From c99af908f10103c0829c4adc1ef74832c3ca4482 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Dec 2022 11:41:27 +0700
Subject: [PATCH 1330/2085] fix typo

---
 src/tusb.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/tusb.c b/src/tusb.c
index 8f64f4acf..a5c820b8d 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -253,7 +253,7 @@ bool stream_xfer(tu_edpt_stream_t* s, uint16_t count)
   }else
   {
     #if CFG_TUD_ENABLED
-    return usbd_edpt_xfer(s->rhport, s->ep_addr, cont ? s->ep_buf : NULL, count);
+    return usbd_edpt_xfer(s->rhport, s->ep_addr, count ? s->ep_buf : NULL, count);
     #endif
   }
 
@@ -366,7 +366,6 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s)
   {
     // Release endpoint since we don't make any transfer
     stream_release(s);
-
     return 0;
   }
 }

From 11233e4d3e04ceab1ad6e33d37a166aa48c436de Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Dec 2022 11:43:57 +0700
Subject: [PATCH 1331/2085] minor clean up

---
 examples/host/cdc_msc_hid/src/tusb_config.h |  4 +++
 src/class/cdc/cdc_host.h                    | 28 ++++-----------------
 2 files changed, 9 insertions(+), 23 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index c515405cb..e3d9356f6 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -108,6 +108,10 @@
 #define CFG_TUH_HID_EPIN_BUFSIZE    64
 #define CFG_TUH_HID_EPOUT_BUFSIZE   64
 
+//------------- CDC -------------//
+// Set both DTR ( bit 0), RTS (bit 1) on enumeration/mounted
+#define CFG_TUH_CDC_SET_DTRRTS_ON_ENUM    0x03
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 02ae69111..5407c646d 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -49,7 +49,7 @@
 
 // RX Endpoint size
 #ifndef CFG_TUH_CDC_RX_EPSIZE
-#define CFG_TUH_CDC_RX_EPSIZE USBH_EPSIZE_BULK_MAX
+#define CFG_TUH_CDC_RX_EPSIZE  USBH_EPSIZE_BULK_MAX
 #endif
 
 // TX FIFO size
@@ -59,7 +59,7 @@
 
 // TX Endpoint size
 #ifndef CFG_TUH_CDC_TX_EPSIZE
-#define CFG_TUH_CDC_TX_EPSIZE USBH_EPSIZE_BULK_MAX
+#define CFG_TUH_CDC_TX_EPSIZE  USBH_EPSIZE_BULK_MAX
 #endif
 
 //--------------------------------------------------------------------+
@@ -145,7 +145,9 @@ static inline bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, ui
   return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data);
 }
 
-//------------- Application Callback -------------//
+//--------------------------------------------------------------------+
+// CDC APPLICATION CALLBACKS
+//--------------------------------------------------------------------+
 
 // Invoked when a device with CDC interface is mounted
 // idx is index of cdc interface in the internal pool.
@@ -160,26 +162,6 @@ TU_ATTR_WEAK extern void tuh_cdc_rx_cb(uint8_t idx);
 // Invoked when a TX is complete and therefore space becomes available in TX buffer
 TU_ATTR_WEAK extern void tuh_cdc_tx_complete_cb(uint8_t idx);
 
-//--------------------------------------------------------------------+
-// CDC APPLICATION CALLBACKS
-//--------------------------------------------------------------------+
-
-/** \brief      Callback function that is invoked when an transferring event occurred
- * \param[in]		dev_addr	Address of device
- * \param[in]   event an value from \ref xfer_result_t
- * \param[in]   pipe_id value from \ref cdc_pipeid_t indicate the pipe
- * \param[in]   xferred_bytes Number of bytes transferred via USB bus
- * \note        event can be one of following
- *              - XFER_RESULT_SUCCESS : previously scheduled transfer completes successfully.
- *              - XFER_RESULT_FAILED   : previously scheduled transfer encountered a transaction error.
- *              - XFER_RESULT_STALLED : previously scheduled transfer is stalled by device.
- * \note
- */
-// void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes);
-
-/// @} // group CDC_Serial_Host
-/// @}
-
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+

From 05c119ce975668eff814c78d5306589fc2d24530 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Dec 2022 18:28:06 +0700
Subject: [PATCH 1332/2085] cdc host, add set line coding API

---
 examples/host/cdc_msc_hid/src/tusb_config.h |  11 +-
 src/class/cdc/cdc.h                         |  28 +++-
 src/class/cdc/cdc_host.c                    | 135 +++++++++++++++-----
 src/class/cdc/cdc_host.h                    |  16 ++-
 4 files changed, 146 insertions(+), 44 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index e3d9356f6..139a921d1 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -109,8 +109,15 @@
 #define CFG_TUH_HID_EPOUT_BUFSIZE   64
 
 //------------- CDC -------------//
-// Set both DTR ( bit 0), RTS (bit 1) on enumeration/mounted
-#define CFG_TUH_CDC_SET_DTRRTS_ON_ENUM    0x03
+
+// Set Line Control state on enumeration/mounted:
+// DTR ( bit 0), RTS (bit 1)
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0x03
+
+// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
+// bit rate = 115200, 1 stop bit, no parity, 8 bit data width
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+
 
 #ifdef __cplusplus
  }
diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index 6a9669cf2..9a3fc21ee 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -198,6 +198,22 @@ enum
   CDC_CONTROL_LINE_STATE_RTS = 0x02,
 };
 
+enum
+{
+  CDC_LINE_CONDING_STOP_BITS_1   = 0, // 1   bit
+  CDC_LINE_CONDING_STOP_BITS_1_5 = 1, // 1.5 bits
+  CDC_LINE_CONDING_STOP_BITS_2   = 2, // 2   bits
+};
+
+enum
+{
+  CDC_LINE_CODING_PARITY_NONE  = 0,
+  CDC_LINE_CODING_PARITY_ODD   = 1,
+  CDC_LINE_CODING_PARITY_EVEN  = 2,
+  CDC_LINE_CODING_PARITY_MARK  = 3,
+  CDC_LINE_CODING_PARITY_SPACE = 4,
+};
+
 //--------------------------------------------------------------------+
 // Management Element Notification (Notification Endpoint)
 //--------------------------------------------------------------------+
@@ -207,13 +223,13 @@ typedef enum
 {
   CDC_NOTIF_NETWORK_CONNECTION               = 0x00, ///< This notification allows the device to notify the host about network connection status.
   CDC_NOTIF_RESPONSE_AVAILABLE               = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request.
-  CDC_NOTIF_AUX_JACK_HOOK_STATE              = 0x08,
-  CDC_NOTIF_RING_DETECT                      = 0x09,
-  CDC_NOTIF_SERIAL_STATE                     = 0x20,
-  CDC_NOTIF_CALL_STATE_CHANGE                = 0x28,
-  CDC_NOTIF_LINE_STATE_CHANGE                = 0x29,
+  CDC_NOTIF_AUX_JACK_HOOK_STATE              = 0x08,///< CDC_NOTIF_AUX_JACK_HOOK_STATE
+  CDC_NOTIF_RING_DETECT                      = 0x09,///< CDC_NOTIF_RING_DETECT
+  CDC_NOTIF_SERIAL_STATE                     = 0x20,///< CDC_NOTIF_SERIAL_STATE
+  CDC_NOTIF_CALL_STATE_CHANGE                = 0x28,///< CDC_NOTIF_CALL_STATE_CHANGE
+  CDC_NOTIF_LINE_STATE_CHANGE                = 0x29,///< CDC_NOTIF_LINE_STATE_CHANGE
   CDC_NOTIF_CONNECTION_SPEED_CHANGE          = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred
-  CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40,
+  CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40,///< CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION
 }cdc_notification_request_t;
 
 //--------------------------------------------------------------------+
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index de1466cb1..fcabb922a 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -52,8 +52,8 @@ typedef struct {
   cdc_acm_capability_t acm_capability;
   uint8_t ep_notif;
 
-  // Bit 0:  DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
-  uint8_t line_state;
+  cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width
+  uint8_t line_state; // DTR (bit0), RTS (bit1)
 
   tuh_xfer_cb_t user_control_cb;
 
@@ -240,6 +240,13 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
         p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
       break;
 
+      case CDC_REQUEST_SET_LINE_CODING:
+      {
+        uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
+        memcpy(&p_cdc->line_coding, xfer->buffer, len);
+      }
+      break;
+
       default: break;
     }
   }
@@ -265,7 +272,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
     },
     .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
     .wValue   = tu_htole16(line_state),
-    .wIndex   = tu_htole16(p_cdc->bInterfaceNumber),
+    .wIndex   = tu_htole16((uint16_t) p_cdc->bInterfaceNumber),
     .wLength  = 0
   };
 
@@ -283,6 +290,46 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
   return tuh_control_xfer(&xfer);
 }
 
+bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request);
+
+  TU_LOG_CDCH("CDC Set Line Conding\r\n");
+
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = CDC_REQUEST_SET_LINE_CODING,
+    .wValue   = 0,
+    .wIndex   = tu_htole16(p_cdc->bInterfaceNumber),
+    .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
+  };
+
+  // use usbh enum buf to hold line coding since user line_coding variable may not live long enough
+  // for the transfer to complete
+  uint8_t* enum_buf = usbh_get_enum_buf();
+  memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t));
+
+  p_cdc->user_control_cb = complete_cb;
+  tuh_xfer_t xfer =
+  {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = enum_buf,
+    .complete_cb = cdch_internal_control_complete,
+    .user_data   = user_data
+  };
+
+  return tuh_control_xfer(&xfer);
+}
+
 //--------------------------------------------------------------------+
 // CLASS-USBH API
 //--------------------------------------------------------------------+
@@ -448,46 +495,70 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
   return true;
 }
 
-static void config_cdc_complete(uint8_t daddr, uint8_t itf_num)
+enum
 {
-  uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num);
+  CONFIG_SET_CONTROL_LINE_STATE,
+  CONFIG_SET_LINE_CODING,
+  CONFIG_COMPLETE
+};
 
-  if (idx != TUSB_INDEX_INVALID)
-  {
-    if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
-
-    // Prepare for incoming data
-    cdch_interface_t* p_cdc = get_itf(idx);
-    tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
-  }
-
-  // notify usbh that driver enumeration is complete
-  // itf_num+1 to account for data interface as well
-  usbh_driver_set_config_complete(daddr, itf_num+1);
-}
-
-#if CFG_TUH_CDC_SET_DTRRTS_ON_ENUM
-
-static void config_set_dtr_rts_complete (tuh_xfer_t* xfer)
+static void process_cdc_config(tuh_xfer_t* xfer)
 {
+  uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  config_cdc_complete(xfer->daddr, itf_num);
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  TU_ASSERT(idx != TUSB_INDEX_INVALID, );
+
+  switch(state)
+  {
+    case CONFIG_SET_CONTROL_LINE_STATE:
+    #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+      TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), );
+      break;
+    #endif
+    TU_ATTR_FALLTHROUGH;
+
+    case CONFIG_SET_LINE_CODING:
+    #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+    {
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, 0), );
+      break;
+    }
+    #endif
+    TU_ATTR_FALLTHROUGH;
+
+    case CONFIG_COMPLETE:
+      if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
+
+      // Prepare for incoming data
+      cdch_interface_t* p_cdc = get_itf(idx);
+      tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
+
+      // notify usbh that driver enumeration is complete
+      // itf_num+1 to account for data interface as well
+      usbh_driver_set_config_complete(xfer->daddr, itf_num+1);
+    break;
+
+    default: break;
+  }
 }
 
 bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
 {
-  uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num);
-  return tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_SET_DTRRTS_ON_ENUM, config_set_dtr_rts_complete, 0);
-}
+  // fake transfer to kick-off process
+  tusb_control_request_t request;
+  request.wIndex = tu_htole16((uint16_t) itf_num);
 
-#else
+  tuh_xfer_t xfer;
+  xfer.daddr     = daddr;
+  xfer.result    = XFER_RESULT_SUCCESS;
+  xfer.setup     = &request;
+  xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE;
+
+  process_cdc_config(&xfer);
 
-bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
-{
-  config_cdc_complete(daddr, itf_num);
   return true;
 }
 
 #endif
-
-#endif
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 5407c646d..9bf5af46c 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -37,11 +37,16 @@
 // Class Driver Configuration
 //--------------------------------------------------------------------+
 
-// Set DTR ( bit 0), RTS (bit 1) on enumeration/mounted
-#ifndef CFG_TUH_CDC_SET_DTRRTS_ON_ENUM
-#define CFG_TUH_CDC_SET_DTRRTS_ON_ENUM    0
+// Set Line Control state on enumeration/mounted: DTR ( bit 0), RTS (bit 1)
+#ifndef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0
 #endif
 
+// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
+//#ifndef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+//#endif
+
 // RX FIFO size
 #ifndef CFG_TUH_CDC_RX_BUFSIZE
 #define CFG_TUH_CDC_RX_BUFSIZE USBH_EPSIZE_BULK_MAX
@@ -130,9 +135,12 @@ bool tuh_cdc_read_clear (uint8_t idx);
 // Control Endpoint (Request) API
 //--------------------------------------------------------------------+
 
-// Send control request to Set Control Line State: DTR (bit 0), RTS (bit 1)
+// Request to Set Control Line State: DTR (bit 0), RTS (bit 1)
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
+// Request to Set Line Coding
+bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
 // Connect by set both DTR, RTS
 static inline bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {

From 14d45b580e0cd82e77e36ecb152f7c001d860ce7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Dec 2022 19:17:09 +0700
Subject: [PATCH 1333/2085] correct host cdc enum

---
 src/class/cdc/cdc_host.c | 2 +-
 src/host/usbh.c          | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index fcabb922a..05e0bdfc7 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -522,7 +522,7 @@ static void process_cdc_config(tuh_xfer_t* xfer)
     #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
     {
       cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-      TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, 0), );
+      TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), );
       break;
     }
     #endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index f0ca7be2e..af1e67d4d 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -330,6 +330,8 @@ bool tuh_init(uint8_t controller_id)
   TU_LOG_INT(USBH_DEBUG, sizeof(hcd_event_t));
   TU_LOG_INT(USBH_DEBUG, sizeof(_ctrl_xfer));
   TU_LOG_INT(USBH_DEBUG, sizeof(tuh_xfer_t));
+  TU_LOG_INT(USBH_DEBUG, sizeof(tu_fifo_t));
+  TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t));
 
   // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -1275,7 +1277,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
         break;
       }
       #endif
-      __attribute__((fallthrough));
+      TU_ATTR_FALLTHROUGH;
 #endif
 
     case ENUM_SET_ADDR:

From f33883c308959aa2ca08ef55282c82c54f929226 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Dec 2022 19:41:39 +0700
Subject: [PATCH 1334/2085] add tuh_cdc_get_local_line_coding()

---
 examples/host/cdc_msc_hid/src/cdc_app.c | 15 +++++++++++++--
 src/class/cdc/cdc_host.c                | 22 ++++++++++++++++++++--
 src/class/cdc/cdc_host.h                | 12 ++++++++++++
 3 files changed, 45 insertions(+), 4 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index dd3196146..b1b137e0e 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -90,7 +90,18 @@ void tuh_cdc_mount_cb(uint8_t idx)
   tuh_cdc_itf_info_t itf_info = { 0 };
   tuh_cdc_itf_get_info(idx, &itf_info);
 
-  printf("CDC Interface is mounted: device address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
+  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
+
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+  // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
+  // otherwise you need to call tuh_cdc_set_line_coding() first
+  cdc_line_coding_t line_coding = { 0 };
+  if ( tuh_cdc_get_local_line_coding(idx, &line_coding) )
+  {
+    printf("  Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
+    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity  , line_coding.data_bits);
+  }
+#endif
 }
 
 void tuh_cdc_umount_cb(uint8_t idx)
@@ -98,5 +109,5 @@ void tuh_cdc_umount_cb(uint8_t idx)
   tuh_cdc_itf_info_t itf_info = { 0 };
   tuh_cdc_itf_get_info(idx, &itf_info);
 
-  printf("CDC Interface is unmounted: device address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
+  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
 }
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 05e0bdfc7..17dc877f8 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -52,8 +52,8 @@ typedef struct {
   cdc_acm_capability_t acm_capability;
   uint8_t ep_notif;
 
-  cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width
-  uint8_t line_state; // DTR (bit0), RTS (bit1)
+  cdc_line_coding_t line_coding;  // Baudrate, stop bits, parity, data width
+  uint8_t line_state;             // DTR (bit0), RTS (bit1)
 
   tuh_xfer_cb_t user_control_cb;
 
@@ -162,6 +162,20 @@ bool tuh_cdc_get_rts(uint8_t idx)
   return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false;
 }
 
+bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding)
+{
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  *line_coding = p_cdc->line_coding;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// Write
+//--------------------------------------------------------------------+
+
 uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
@@ -194,6 +208,10 @@ uint32_t tuh_cdc_write_available(uint8_t idx)
   return tu_edpt_stream_write_available(&p_cdc->stream.tx);
 }
 
+//--------------------------------------------------------------------+
+// Read
+//--------------------------------------------------------------------+
+
 uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 9bf5af46c..502ad430d 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -102,6 +102,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx)
   return tuh_cdc_get_dtr(idx);
 }
 
+// Get local (saved/cached) version of line coding.
+// This function should return correct values if tuh_cdc_set_line_coding() / tuh_cdc_get_line_coding()
+// are invoked previously or CFG_TUH_CDC_LINE_CODING_ON_ENUM is defined.
+// NOTE: This function does not make any USB transfer request to device.
+bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding);
+
 //--------------------------------------------------------------------+
 // Write API
 //--------------------------------------------------------------------+
@@ -133,6 +139,7 @@ bool tuh_cdc_read_clear (uint8_t idx);
 
 //--------------------------------------------------------------------+
 // Control Endpoint (Request) API
+// Each Function will make a USB transfer request to/from device
 //--------------------------------------------------------------------+
 
 // Request to Set Control Line State: DTR (bit 0), RTS (bit 1)
@@ -141,6 +148,11 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
 // Request to Set Line Coding
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
+// Request to Get Line Coding
+// Should only use if tuh_cdc_set_line_coding() / tuh_cdc_get_line_coding() never got invoked and
+// CFG_TUH_CDC_LINE_CODING_ON_ENUM is not defined
+// bool tuh_cdc_get_line_coding(uint8_t idx, cdc_line_coding_t* coding);
+
 // Connect by set both DTR, RTS
 static inline bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {

From 396716cc2c29b151556d554c560307afcadd7252 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Dec 2022 20:26:32 +0700
Subject: [PATCH 1335/2085] clean up

---
 examples/host/cdc_msc_hid/CMakeLists.txt |  2 +-
 src/class/cdc/cdc.h                      | 22 ++++++----------------
 2 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 2e89817a5..7af6b738e 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -15,8 +15,8 @@ add_executable(${PROJECT})
 # Example source
 target_sources(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
         ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
         ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
         )
 
diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index 9a3fc21ee..2fecde3ca 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -41,16 +41,6 @@
 /** \defgroup ClassDriver_CDC_Common Common Definitions
  *  @{ */
 
-// TODO remove
-/// CDC Pipe ID, used to indicate which pipe the API is addressing to (Notification, Out, In)
-typedef enum
-{
-  CDC_PIPE_NOTIFICATION , ///< Notification pipe
-  CDC_PIPE_DATA_IN      , ///< Data in pipe
-  CDC_PIPE_DATA_OUT     , ///< Data out pipe
-  CDC_PIPE_ERROR        , ///< Invalid Pipe ID
-}cdc_pipeid_t;
-
 //--------------------------------------------------------------------+
 // CDC Communication Interface Class
 //--------------------------------------------------------------------+
@@ -223,13 +213,13 @@ typedef enum
 {
   CDC_NOTIF_NETWORK_CONNECTION               = 0x00, ///< This notification allows the device to notify the host about network connection status.
   CDC_NOTIF_RESPONSE_AVAILABLE               = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request.
-  CDC_NOTIF_AUX_JACK_HOOK_STATE              = 0x08,///< CDC_NOTIF_AUX_JACK_HOOK_STATE
-  CDC_NOTIF_RING_DETECT                      = 0x09,///< CDC_NOTIF_RING_DETECT
-  CDC_NOTIF_SERIAL_STATE                     = 0x20,///< CDC_NOTIF_SERIAL_STATE
-  CDC_NOTIF_CALL_STATE_CHANGE                = 0x28,///< CDC_NOTIF_CALL_STATE_CHANGE
-  CDC_NOTIF_LINE_STATE_CHANGE                = 0x29,///< CDC_NOTIF_LINE_STATE_CHANGE
+  CDC_NOTIF_AUX_JACK_HOOK_STATE              = 0x08,
+  CDC_NOTIF_RING_DETECT                      = 0x09,
+  CDC_NOTIF_SERIAL_STATE                     = 0x20,
+  CDC_NOTIF_CALL_STATE_CHANGE                = 0x28,
+  CDC_NOTIF_LINE_STATE_CHANGE                = 0x29,
   CDC_NOTIF_CONNECTION_SPEED_CHANGE          = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred
-  CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40,///< CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION
+  CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40,
 }cdc_notification_request_t;
 
 //--------------------------------------------------------------------+

From 15a02d04df33afdeddc751453bbaefd4bc895939 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 22 Dec 2022 21:35:55 +0700
Subject: [PATCH 1336/2085] fix incorrect rx buf in cdc

---
 src/class/cdc/cdc_device.c | 2 +-
 src/class/cdc/cdc_device.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 0bbbaaa83..8d10a416c 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -432,7 +432,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   // Received new data
   if ( ep_addr == p_cdc->ep_out )
   {
-    tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, (uint16_t) xferred_bytes);
+    tu_fifo_write_n(&p_cdc->rx_ff, p_cdc->epout_buf, (uint16_t) xferred_bytes);
     
     // Check for wanted char and invoke callback if needed
     if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) )
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index f625a7554..a7d25bd32 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -134,7 +134,7 @@ TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf);
 // Invoked when received `wanted_char`
 TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char);
 
-// Invoked when space becomes available in TX buffer
+// Invoked when a TX is complete and therefore space becomes available in TX buffer
 TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf);
 
 // Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE

From 48d4a67ec5468f9fd7c073acd599a1271b9e877f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Dec 2022 01:11:13 +0700
Subject: [PATCH 1337/2085] add tuh_cdc_peek()

---
 src/class/cdc/cdc_device.h | 2 +-
 src/class/cdc/cdc_host.c   | 8 ++++++++
 src/class/cdc/cdc_host.h   | 3 +++
 src/common/tusb_fifo.c     | 2 --
 src/common/tusb_private.h  | 5 +++++
 5 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index a7d25bd32..f8a004df4 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -80,7 +80,7 @@ int32_t  tud_cdc_n_read_char       (uint8_t itf);
 // Clear the received FIFO
 void     tud_cdc_n_read_flush      (uint8_t itf);
 
-// Get a byte from FIFO at the specified position without removing it
+// Get a byte from FIFO without removing it
 bool     tud_cdc_n_peek            (uint8_t itf, uint8_t* ui8);
 
 // Write bytes to TX FIFO, data may remain in the FIFO for a while
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 17dc877f8..e9c3d34cb 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -228,6 +228,14 @@ uint32_t tuh_cdc_read_available(uint8_t idx)
   return tu_edpt_stream_read_available(&p_cdc->stream.rx);
 }
 
+bool tuh_cdc_peek(uint8_t idx, uint8_t* ch)
+{
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  return tu_edpt_stream_peek(&p_cdc->stream.rx, ch);
+}
+
 bool tuh_cdc_read_clear (uint8_t idx)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 502ad430d..c759527e6 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -134,6 +134,9 @@ uint32_t tuh_cdc_read_available(uint8_t idx);
 // Read from cdc interface
 uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize);
 
+// Get a byte from RX FIFO without removing it
+bool tuh_cdc_peek(uint8_t idx, uint8_t* ch);
+
 // Clear the received FIFO
 bool tuh_cdc_read_clear (uint8_t idx);
 
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index b857c6444..d45ca09ed 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -682,8 +682,6 @@ uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t* f, void * buffer, uint1
 
     @param[in]  f
                 Pointer to the FIFO buffer to manipulate
-    @param[in]  offset
-                Position to read from in the FIFO buffer with respect to read pointer
     @param[in]  p_buffer
                 Pointer to the place holder for data read from the buffer
 
diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
index d0c7a84fb..d5541856c 100644
--- a/src/common/tusb_private.h
+++ b/src/common/tusb_private.h
@@ -160,6 +160,11 @@ uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s)
   return (uint32_t) tu_fifo_count(&s->ff);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline
+bool tu_edpt_stream_peek(tu_edpt_stream_t* s, uint8_t* ch)
+{
+  return tu_fifo_peek(&s->ff, ch);
+}
 
 #ifdef __cplusplus
  }

From d0ca6ca8f728fadcc12053c24ada23e328f2180a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 27 Dec 2022 18:21:56 +0700
Subject: [PATCH 1338/2085] fix ncm warning

---
 src/class/net/ncm_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 00892b49c..1cbc0ce01 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -392,7 +392,7 @@ bool netd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
 
       if (NCM_GET_NTB_PARAMETERS == request->bRequest)
       {
-        tud_control_xfer(rhport, request, (void*)&ntb_parameters, sizeof(ntb_parameters));
+        tud_control_xfer(rhport, request, (void*)(uintptr_t) &ntb_parameters, sizeof(ntb_parameters));
       }
 
       break;

From 95ba158a1070635551b01d921cb4c5eeb7734989 Mon Sep 17 00:00:00 2001
From: Staacks <staacks@physik.rwth-aachen.de>
Date: Tue, 27 Dec 2022 23:02:33 +0100
Subject: [PATCH 1339/2085] Fix UVC probe and commit on MacOS

---
 src/class/video/video_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index a6d2724c1..e17d0a90f 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -917,7 +917,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
       switch (request->bRequest) {
         case VIDEO_REQUEST_SET_CUR:
           if (stage == CONTROL_STAGE_SETUP) {
-            TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(sizeof(video_probe_and_commit_control_t) >= request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)),
                       VIDEO_ERROR_UNKNOWN);
           } else if (stage == CONTROL_STAGE_DATA) {
@@ -973,7 +973,7 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
       switch (request->bRequest) {
         case VIDEO_REQUEST_SET_CUR:
           if (stage == CONTROL_STAGE_SETUP) {
-            TU_VERIFY(sizeof(video_probe_and_commit_control_t) == request->wLength, VIDEO_ERROR_UNKNOWN);
+            TU_VERIFY(sizeof(video_probe_and_commit_control_t) >= request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           } else if (stage == CONTROL_STAGE_DATA) {
             TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);

From 1dcffc655d8b42a850c8cd16cdf66caab1c9549d Mon Sep 17 00:00:00 2001
From: Nathaniel Brough <nathaniel.brough@gmail.com>
Date: Wed, 28 Dec 2022 20:37:12 +0000
Subject: [PATCH 1340/2085] fix(fuzz): Make sanitizer flags optional

Currently OSS fuzz expects to have complete control over the
sanitizer flags. As we currently have these set it's causing
problems with the OSS fuzz build. Instead we should use the
provided variables from the OSS fuzz build environment. For
local testing we'll create a set a well defined defaults.
---
 .github/workflows/pre-commit.yml |  2 ++
 test/fuzz/make.mk                | 16 ++++++++++------
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index 8a1101ac0..d2150d13f 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -38,6 +38,8 @@ jobs:
 
     - name: Build Fuzzer
       run: |
+        export CC=clang
+        export CXX=clang++
         fuzz_harness=$(ls -d test/fuzz/device/*/)
         for h in $fuzz_harness
         do
diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk
index 03254112f..6717ebc80 100644
--- a/test/fuzz/make.mk
+++ b/test/fuzz/make.mk
@@ -16,9 +16,9 @@ __check_defined = \
 
 #-------------- Fuzz harness compiler  ------------
 
-CC = clang
-CXX = clang++
-GDB = gdb
+CC ?= clang
+CXX ?= clang++
+GDB ?= gdb
 OBJCOPY = objcopy
 SIZE = size
 MKDIR = mkdir
@@ -34,6 +34,13 @@ else
   PYTHON = python3
 endif
 
+#-------------- Fuzz harness flags ------------
+COVERAGE_FLAGS ?= -fsanitize-coverage=trace-pc-guard
+SANITIZER_FLAGS ?= -fsanitize=fuzzer \
+                   -fsanitize=address
+
+CFLAGS += $(COVERAGE_FLAGS) $(SANITIZER_FLAGS)
+
 #-------------- Source files and compiler flags --------------
 
 
@@ -42,9 +49,6 @@ INC += $(TOP)/test
 # Compiler Flags
 CFLAGS += \
   -ggdb \
-  -fsanitize=fuzzer \
-  -fsanitize=address \
-  -fsanitize=undefined \
   -fdata-sections \
   -ffunction-sections \
   -fno-strict-aliasing \

From 6d65eaf7a18a498ef686a21e3d3ccb98dd42ec03 Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Mon, 24 Oct 2022 19:59:59 +0200
Subject: [PATCH 1341/2085] Implemented very rudimentary support for
 isochronous transfer buffer handling

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 134 ++++++++++--------
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   |   2 +
 2 files changed, 75 insertions(+), 61 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 0e78c796e..17b5c7068 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -163,7 +163,7 @@ TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligne
 typedef struct
 {
   uint8_t * buffer;
-  // tu_fifo_t * ff;  // TODO support dcd_edpt_xfer_fifo API
+  tu_fifo_t * ff;
   uint16_t total_len;
   uint16_t queued_len;
   uint16_t pma_ptr;
@@ -196,8 +196,8 @@ static void dcd_pma_free(uint8_t ep_addr);
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes);
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes);
 
-//static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes);
-//static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes);
+static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes);
+static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes);
 
 // Using a function due to better type checks
 // This seems better than having to do type casts everywhere else
@@ -222,7 +222,7 @@ void dcd_init (uint8_t rhport)
   {
     asm("NOP");
   }
-	// Perform USB peripheral reset
+  // Perform USB peripheral reset
   USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
   for(uint32_t i = 0; i<200; i++) // should be a few us
   {
@@ -526,15 +526,15 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
 
     if (count != 0U)
     {
-#if 0 // TODO support dcd_edpt_xfer_fifo API
+      uint16_t addr = *pcd_ep_rx_address_ptr(USB, EPindex);
+
       if (xfer->ff)
       {
-        dcd_read_packet_memory_ff(xfer->ff, *pcd_ep_rx_address_ptr(USB,EPindex), count);
+        dcd_read_packet_memory_ff(xfer->ff, addr, count);
       }
       else
-#endif
       {
-        dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]), *pcd_ep_rx_address_ptr(USB,EPindex), count);
+        dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]), addr, count);
       }
 
       xfer->queued_len = (uint16_t)(xfer->queued_len + count);
@@ -683,6 +683,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
 
 static void dcd_pma_alloc_reset(void)
 {
+  open_ep_count = 0;
   ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each)
   //TU_LOG2("dcd_pma_alloc_reset()\r\n");
   for(uint32_t i=0; i<MAX_EP_COUNT; i++)
@@ -709,6 +710,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
   uint8_t const dir   = tu_edpt_dir(ep_addr);
   xfer_ctl_t* epXferCtl = xfer_ctl_ptr(epnum,dir);
 
+  open_ep_count++;
   if(epXferCtl->pma_alloc_size != 0U)
   {
     //TU_LOG2("dcd_pma_alloc(%x,%x)=%x (cached)\r\n",ep_addr,length,epXferCtl->pma_ptr);
@@ -771,9 +773,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc);
   uint16_t pma_addr;
   uint32_t wType;
-  
+
   // Isochronous not supported (yet), and some other driver assumptions.
-  TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
   TU_ASSERT(epnum < MAX_EP_COUNT);
 
   // Set type
@@ -781,12 +782,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   case TUSB_XFER_CONTROL:
     wType = USB_EP_CONTROL;
     break;
-#if (0)
-  case TUSB_XFER_ISOCHRONOUS: // FIXME: Not yet supported
+  case TUSB_XFER_ISOCHRONOUS:
     wType = USB_EP_ISOCHRONOUS;
     break;
-#endif
-
   case TUSB_XFER_BULK:
     wType = USB_EP_CONTROL;
     break;
@@ -805,21 +803,41 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   // or being double-buffered (bulk endpoints)
   pcd_clear_ep_kind(USB,0);
 
+  /* Create a packet memory buffer area. For isochronous endpoints,
+   * use the same buffer as the double buffer, essentially disabling double buffering */
   pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, epMaxPktSize);
 
+#if defined(ISOCHRONOUS_DOUBLEBUFFER)
+  if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) )
+#else
   if(dir == TUSB_DIR_IN)
+#endif
   {
     *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
     pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize);
     pcd_clear_tx_dtog(USB, epnum);
-    pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_NAK);
+
+    if(wType == USB_EP_ISOCHRONOUS) {
+      pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS);
+    } else {
+      pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK);
+    }
   }
+#if defined(ISOCHRONOUS_DOUBLEBUFFER)
+  if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) )
+#else
   else
+#endif
   {
     *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
     pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize);
     pcd_clear_rx_dtog(USB, epnum);
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
+
+    if(wType == USB_EP_ISOCHRONOUS) {
+      pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS);
+    } else {
+      pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
+    }
   }
 
   xfer_ctl_ptr(epnum, dir)->max_packet_size = epMaxPktSize;
@@ -845,10 +863,10 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
   (void)rhport;
   uint32_t const epnum = tu_edpt_number(ep_addr);
   uint32_t const dir   = tu_edpt_dir(ep_addr);
-  
+
   if(dir == TUSB_DIR_IN)
   {
-    pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_DIS);
+    pcd_set_ep_tx_status(USB,epnum, USB_EP_TX_DIS);
   }
   else
   {
@@ -868,15 +886,14 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
   {
     len = xfer->max_packet_size;
   }
+
   uint16_t oldAddr = *pcd_ep_tx_address_ptr(USB,ep_ix);
 
-#if 0 // TODO support dcd_edpt_xfer_fifo API
   if (xfer->ff)
   {
     dcd_write_packet_memory_ff(xfer->ff, oldAddr, len);
   }
   else
-#endif
   {
     dcd_write_packet_memory(oldAddr, &(xfer->buffer[xfer->queued_len]), len);
   }
@@ -896,7 +913,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
 
   xfer->buffer = buffer;
-  // xfer->ff     = NULL; // TODO support dcd_edpt_xfer_fifo API
+  xfer->ff     = NULL; // TODO support dcd_edpt_xfer_fifo API
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
 
@@ -908,6 +925,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     {
         xfer->buffer = (uint8_t*)_setup_packet;
     }
+
     if(total_bytes > xfer->max_packet_size)
     {
       pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size);
@@ -923,7 +941,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   return true;
 }
 
-#if 0 // TODO support dcd_edpt_xfer_fifo API
 bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
 {
   (void) rhport;
@@ -934,7 +951,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
 
   xfer->buffer = NULL;
-  // xfer->ff     = ff; // TODO support dcd_edpt_xfer_fifo API
+  xfer->ff     = ff; // TODO support dcd_edpt_xfer_fifo API
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
 
@@ -954,7 +971,6 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   }
   return true;
 }
-#endif
 
 void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
@@ -978,7 +994,10 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   { // IN
     ep_addr &= 0x7F;
 
-    pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK);
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    if (pcd_get_eptype(USB, epnum) !=  USB_EP_ISOCHRONOUS) {
+      pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK);
+    }
 
     /* Reset to DATA0 if clearing stall condition. */
     pcd_clear_tx_dtog(USB,ep_addr);
@@ -1029,7 +1048,6 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
   return true;
 }
 
-#if 0 // TODO support dcd_edpt_xfer_fifo API
 /**
   * @brief Copy from FIFO to packet memory area (PMA).
   *        Uses byte-access of system memory and 16-bit access of packet memory
@@ -1043,38 +1061,36 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
 {
   // Since we copy from a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
   // Check for first linear part
-  void * src;
-  uint16_t len = tu_fifo_get_linear_read_info(ff, 0, &src, wNBytes);  // We want to read from the FIFO        - THIS FUNCTION CHANGED!!!
-  TU_VERIFY(len && dcd_write_packet_memory(dst, src, len));           // and write it into the PMA
-  tu_fifo_advance_read_pointer(ff, len);
+  tu_fifo_buffer_info_t info;
+  tu_fifo_get_read_info(ff, &info);  // We want to read from the FIFO
+  TU_VERIFY(info.len_lin && dcd_write_packet_memory(dst, info.ptr_lin, info.len_lin));           // and write it into the PMA
+  tu_fifo_advance_read_pointer(ff, info.len_lin);
 
   // Check for wrapped part
-  if (len < wNBytes)
+  if (info.len_wrap)
   {
-    // Get remaining wrapped length
-    uint16_t len2 = tu_fifo_get_linear_read_info(ff, 0, &src, wNBytes - len);
-    TU_VERIFY(len2);
-
     // Update destination pointer
-    dst += len;
+    dst += info.len_lin;
+    uint8_t* src = (uint8_t*)info.ptr_wrap;
+    uint16_t len2 = info.len_wrap;
 
     // Since PMA is accessed 16-bit wise we need to handle the case when a 16 bit value was split
-    if (len % 2)    // If len is uneven there is a byte left to copy
+    if (info.len_lin % 2)    // If len is uneven there is a byte left to copy
     {
-      // Since PMA can accessed only 16 bit-wise we copy the last byte again
-      tu_fifo_backward_read_pointer(ff, 1);                 // Move one byte back and copy two bytes for the PMA
-      tu_fifo_read_n(ff, (void *) &pma[PMA_STRIDE*(dst>>1)], 2);     // Since EP FIFOs must be of item size 1 this is safe to do
-      dst++;
+      TU_ASSERT(false); // TODO: Step through and check -> untested
+
+      uint16_t temp = ((uint8_t *)info.ptr_lin)[info.len_lin-1] | src[0] << 16; // CHECK endianess
+      pma[PMA_STRIDE*(dst>>1)] = temp;
+      src++;
       len2--;
     }
 
     TU_VERIFY(dcd_write_packet_memory(dst, src, len2));
-    tu_fifo_advance_write_pointer(ff, len2);
+    tu_fifo_advance_write_pointer(ff, info.len_wrap);
   }
 
   return true;
 }
-#endif
 
 /**
   * @brief Copy a buffer from packet memory area (PMA) to user memory area.
@@ -1111,7 +1127,6 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
   return true;
 }
 
-#if 0 // TODO support dcd_edpt_xfer_fifo API
 /**
   * @brief Copy a buffer from user packet memory area (PMA) to FIFO.
   *        Uses byte-access of system memory and 16-bit access of packet memory
@@ -1125,32 +1140,31 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
 {
   // Since we copy into a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
   // Check for first linear part
-  void * dst;
-  uint16_t len = tu_fifo_get_linear_write_info(ff, 0, &dst, wNBytes);           // THIS FUNCTION CHANGED!!!!
-  TU_VERIFY(len && dcd_read_packet_memory(dst, src, len));
-  tu_fifo_advance_write_pointer(ff, len);
+  tu_fifo_buffer_info_t info;
+  tu_fifo_get_write_info(ff, &info);  // We want to read from the FIFO
+
+  TU_VERIFY(info.len_lin && dcd_read_packet_memory(info.ptr_lin, src, info.len_lin));
+  tu_fifo_advance_write_pointer(ff, info.len_lin);
 
   // Check for wrapped part
-  if (len < wNBytes)
+  if (info.len_wrap)
   {
-    // Get remaining wrapped length
-    uint16_t len2 = tu_fifo_get_linear_write_info(ff, 0, &dst, wNBytes - len);
-    TU_VERIFY(len2);
-
     // Update source pointer
-    src += len;
+    src += info.len_lin;
 
     // Since PMA is accessed 16-bit wise we need to handle the case when a 16 bit value was split
-    if (len % 2)    // If len is uneven there is a byte left to copy
+    if (info.len_lin % 2)    // If len is uneven there is a byte left to copy
     {
+      TU_ASSERT(false); //TODO: step through -> untested
       uint32_t temp = pma[PMA_STRIDE*(src>>1)];
-      *((uint8_t *)dst++) = ((temp >> 8) & 0xFF);
+      *((uint8_t *)info.ptr_wrap++) = ((temp >> 8) & 0xFF);
       src++;
-      len2--;
+      tu_fifo_advance_write_pointer(ff, 1);
+      info.len_wrap--;
     }
 
-    TU_VERIFY(dcd_read_packet_memory(dst, src, len2));
-    tu_fifo_advance_write_pointer(ff, len2);
+    TU_VERIFY(dcd_read_packet_memory(info.ptr_wrap, src, info.len_wrap));
+    tu_fifo_advance_write_pointer(ff, info.len_wrap);
   }
 
   return true;
@@ -1158,5 +1172,3 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
 
 #endif
 
-#endif
-
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index bffae4500..40c4003c5 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -66,6 +66,7 @@
       defined(STM32F373xC)
   #include "stm32f3xx.h"
   #define PMA_LENGTH (512u)
+  #define ISOCHRONOUS_DOUBLEBUFFER
   // NO internal Pull-ups
   //         *B, and *C:    1 x 16 bits/word
   // PMA dedicated to USB (no sharing with CAN)
@@ -75,6 +76,7 @@
       defined(STM32F303xD) || defined(STM32F303xE)
   #include "stm32f3xx.h"
   #define PMA_LENGTH (1024u)
+  #define ISOCHRONOUS_DOUBLEBUFFER
   // NO internal Pull-ups
   // *6, *8, *D, and *E:    2 x 16 bits/word     LPM Support
   // When CAN clock is enabled, USB can use first 768 bytes ONLY.

From d9b2c9934a5a7051e6f6c19fa4047109c3e056fb Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Mon, 24 Oct 2022 22:07:45 +0200
Subject: [PATCH 1342/2085] Implemented an optional callback function that is
 used instead of tu_edpt_number in the stm32 device driver as a crude tool to
 control mapping of the endpoint address to actual endpoint register

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 48 ++++++++++---------
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   |  9 ++++
 2 files changed, 35 insertions(+), 22 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 17b5c7068..73fecb750 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -400,7 +400,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   (void) dev_addr;
 
   // Respond with status
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  dcd_edpt_xfer(rhport, TUSB_DIR_IN_MASK | 0x00, NULL, 0);
 
   // DCD can only set address after status for this request is complete.
   // do it at dcd_edpt0_status_complete()
@@ -479,7 +479,8 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
   }
   else /* TX Complete */
   {
-    dcd_event_xfer_complete(0, (uint8_t)(0x80 + EPindex), xfer->total_len, XFER_RESULT_SUCCESS, true);
+    uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD;
+    dcd_event_xfer_complete(0, (uint8_t)(TUSB_DIR_IN_MASK | ep_addr), xfer->total_len, XFER_RESULT_SUCCESS, true);
   }
 }
 
@@ -543,7 +544,8 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
     if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
     {
       /* RX COMPLETE */
-      dcd_event_xfer_complete(0, EPindex, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+      uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD;
+      dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true);
       // Though the host could still send, we don't know.
       // Does the bulk pipe need to be reset to valid to allow for a ZLP?
     }
@@ -706,7 +708,7 @@ static void dcd_pma_alloc_reset(void)
  */
 static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
 {
-  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
   xfer_ctl_t* epXferCtl = xfer_ctl_ptr(epnum,dir);
 
@@ -737,7 +739,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
  */
 static void dcd_pma_free(uint8_t ep_addr)
 {
-  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   // Presently, this should never be called for EP0 IN/OUT
@@ -768,7 +770,7 @@ static void dcd_pma_free(uint8_t ep_addr)
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   (void)rhport;
-  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(p_endpoint_desc->bEndpointAddress) : tu_edpt_number(p_endpoint_desc->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc);
   uint16_t pma_addr;
@@ -798,7 +800,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   }
 
   pcd_set_eptype(USB, epnum, wType);
-  pcd_set_ep_address(USB, epnum, epnum);
+  pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
   // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
   // or being double-buffered (bulk endpoints)
   pcd_clear_ep_kind(USB,0);
@@ -861,7 +863,7 @@ void dcd_edpt_close_all (uint8_t rhport)
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
-  uint32_t const epnum = tu_edpt_number(ep_addr);
+  uint32_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
   uint32_t const dir   = tu_edpt_dir(ep_addr);
 
   if(dir == TUSB_DIR_IN)
@@ -907,7 +909,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 {
   (void) rhport;
 
-  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
@@ -945,7 +947,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 {
   (void) rhport;
 
-  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
@@ -976,13 +978,16 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
 
-  if (ep_addr & 0x80)
+  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  if (dir == TUSB_DIR_IN)
   { // IN
-    pcd_set_ep_tx_status(USB, ep_addr & 0x7F, USB_EP_TX_STALL);
+    pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_STALL);
   }
   else
   { // OUT
-    pcd_set_ep_rx_status(USB, ep_addr, USB_EP_RX_STALL);
+    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_STALL);
   }
 }
 
@@ -990,24 +995,23 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
 
-  if (ep_addr & 0x80)
-  { // IN
-    ep_addr &= 0x7F;
+  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-    uint8_t const epnum = tu_edpt_number(ep_addr);
+  if (dir == TUSB_DIR_IN)
+  { // IN
     if (pcd_get_eptype(USB, epnum) !=  USB_EP_ISOCHRONOUS) {
-      pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK);
+      pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK);
     }
 
     /* Reset to DATA0 if clearing stall condition. */
-    pcd_clear_tx_dtog(USB,ep_addr);
+    pcd_clear_tx_dtog(USB, epnum);
   }
   else
   { // OUT
     /* Reset to DATA0 if clearing stall condition. */
-    pcd_clear_rx_dtog(USB,ep_addr);
-
-    pcd_set_ep_rx_status(USB,ep_addr, USB_EP_RX_NAK);
+    pcd_clear_rx_dtog(USB, epnum);
+    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
   }
 }
 
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 40c4003c5..5d26d3525 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -117,6 +117,15 @@
 // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
 static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
 
+// This array maps the endpoint address to a endpoint register in hardware
+// By default the tinyusb stack chooses the endpoint register using the endpoint number
+// However when using ISOCHRONOUS endpoints, the entire endpoint register (RX _and_ TX)
+// are used for a double buffer in a single direction. If you now want to use the same endpoint number with
+// different directions (e.g. 0x02 and 0x82), they would be mapped to the same register
+// In this case, this serves as a crude helper to overcome this limitation by implementing
+// this callback and defining a custom mapping in your application
+TU_ATTR_WEAK uint8_t tu_stm32_edpt_number_cb(uint8_t addr);
+
 // prototypes
 static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
 static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);

From 8c0388f477839810260f578922f17a5197294cc1 Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Mon, 24 Oct 2022 22:39:38 +0200
Subject: [PATCH 1343/2085] Fixed wrongly enabling RX and TX status
 simultaneously on ISOCHRONOUS endpoints

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 73fecb750..d2fefde82 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -818,12 +818,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
     *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
     pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize);
     pcd_clear_tx_dtog(USB, epnum);
-
-    if(wType == USB_EP_ISOCHRONOUS) {
-      pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS);
-    } else {
-      pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK);
-    }
   }
 #if defined(ISOCHRONOUS_DOUBLEBUFFER)
   if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) )
@@ -834,7 +828,18 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
     *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
     pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize);
     pcd_clear_rx_dtog(USB, epnum);
+  }
 
+  /* Enable endpoint */
+  if (dir == TUSB_DIR_IN)
+  {
+    if(wType == USB_EP_ISOCHRONOUS) {
+      pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS);
+    } else {
+      pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK);
+    }
+  } else
+  {
     if(wType == USB_EP_ISOCHRONOUS) {
       pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS);
     } else {

From abf53f927067f84d057d54e31d44d5fc40c76cf7 Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Tue, 25 Oct 2022 17:45:04 +0200
Subject: [PATCH 1344/2085] Changed indirection from actual endpoint address to
 hardware endpoint through lookup table. Allocation of endpoint is now only
 performed in dcd_edpt_open

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 71 ++++++++++---------
 1 file changed, 38 insertions(+), 33 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index d2fefde82..7ebaa826c 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -169,12 +169,17 @@ typedef struct
   uint16_t pma_ptr;
   uint8_t max_packet_size;
   uint8_t pma_alloc_size;
+  uint8_t epnum;
 } xfer_ctl_t;
 
 static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
 
-static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t epnum, uint32_t dir)
+static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr)
 {
+  uint8_t epnum = tu_edpt_number(ep_addr);
+  uint8_t dir = tu_edpt_dir(ep_addr);
+  TU_ASSERT(epnum < MAX_EP_COUNT);
+
   return &xfer_status[epnum][dir];
 }
 
@@ -461,6 +466,7 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
 {
   uint32_t EPindex = wIstr & USB_ISTR_EP_ID;
   uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex);
+  uint8_t ep_addr = (wEPRegVal & USB_EPADDR_FIELD) | TUSB_DIR_IN_MASK;
 
   // Verify the CTR_TX bit is set. This was in the ST Micro code,
   // but I'm not sure it's actually necessary?
@@ -472,15 +478,14 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr)
   /* clear int flag */
   pcd_clear_tx_ep_ctr(USB, EPindex);
 
-  xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_IN);
+  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
   if((xfer->total_len != xfer->queued_len)) /* TX not complete */
   {
       dcd_transmit_packet(xfer, EPindex);
   }
   else /* TX Complete */
   {
-    uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD;
-    dcd_event_xfer_complete(0, (uint8_t)(TUSB_DIR_IN_MASK | ep_addr), xfer->total_len, XFER_RESULT_SUCCESS, true);
+    dcd_event_xfer_complete(0, ep_addr, xfer->total_len, XFER_RESULT_SUCCESS, true);
   }
 }
 
@@ -492,8 +497,9 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
   uint32_t EPindex = wIstr & USB_ISTR_EP_ID;
   uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex);
   uint32_t count = pcd_get_ep_rx_cnt(USB,EPindex);
+  uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD;
 
-  xfer_ctl_t *xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_OUT);
+  xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
 
   // Verify the CTR_RX bit is set. This was in the ST Micro code,
   // but I'm not sure it's actually necessary?
@@ -544,7 +550,6 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
     if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
     {
       /* RX COMPLETE */
-      uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD;
       dcd_event_xfer_complete(0, ep_addr, xfer->queued_len, XFER_RESULT_SUCCESS, true);
       // Though the host could still send, we don't know.
       // Does the bulk pipe need to be reset to valid to allow for a ZLP?
@@ -690,10 +695,10 @@ static void dcd_pma_alloc_reset(void)
   //TU_LOG2("dcd_pma_alloc_reset()\r\n");
   for(uint32_t i=0; i<MAX_EP_COUNT; i++)
   {
-    xfer_ctl_ptr(i,TUSB_DIR_OUT)->pma_alloc_size = 0U;
-    xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_alloc_size = 0U;
-    xfer_ctl_ptr(i,TUSB_DIR_OUT)->pma_ptr = 0U;
-    xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_ptr = 0U;
+    xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_alloc_size = 0U;
+    xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_alloc_size = 0U;
+    xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_ptr = 0U;
+    xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_ptr = 0U;
   }
 }
 
@@ -708,11 +713,8 @@ static void dcd_pma_alloc_reset(void)
  */
 static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
 {
-  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-  xfer_ctl_t* epXferCtl = xfer_ctl_ptr(epnum,dir);
+  xfer_ctl_t* epXferCtl = xfer_ctl_ptr(ep_addr);
 
-  open_ep_count++;
   if(epXferCtl->pma_alloc_size != 0U)
   {
     //TU_LOG2("dcd_pma_alloc(%x,%x)=%x (cached)\r\n",ep_addr,length,epXferCtl->pma_ptr);
@@ -739,12 +741,9 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
  */
 static void dcd_pma_free(uint8_t ep_addr)
 {
-  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
   // Presently, this should never be called for EP0 IN/OUT
   TU_ASSERT(open_ep_count > 2, /**/);
-  TU_ASSERT(xfer_ctl_ptr(epnum,dir)->max_packet_size != 0, /**/);
+  TU_ASSERT(xfer_ctl_ptr(ep_addr)->max_packet_size != 0, /**/);
   open_ep_count--;
 
   // If count is 2, only EP0 should be open, so allocations can be mostly reset.
@@ -756,10 +755,10 @@ static void dcd_pma_free(uint8_t ep_addr)
     // Skip EP0
     for(uint32_t i=1; i<MAX_EP_COUNT; i++)
     {
-      xfer_ctl_ptr(i,TUSB_DIR_OUT)->pma_alloc_size = 0U;
-      xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_alloc_size = 0U;
-      xfer_ctl_ptr(i,TUSB_DIR_OUT)->pma_ptr = 0U;
-      xfer_ctl_ptr(i,TUSB_DIR_IN)->pma_ptr = 0U;
+      xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_alloc_size = 0U;
+      xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_alloc_size = 0U;
+      xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_OUT))->pma_ptr = 0U;
+      xfer_ctl_ptr(tu_edpt_addr(i,TUSB_DIR_IN))->pma_ptr = 0U;
     }
   }
 }
@@ -770,6 +769,7 @@ static void dcd_pma_free(uint8_t ep_addr)
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   (void)rhport;
+  /* TODO: This hardware endpoint allocation could be more sensible. For now, simple allocation or manual allocation using callback */
   uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(p_endpoint_desc->bEndpointAddress) : tu_edpt_number(p_endpoint_desc->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc);
@@ -799,6 +799,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
     TU_ASSERT(false);
   }
 
+  open_ep_count++;
+
   pcd_set_eptype(USB, epnum, wType);
   pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
   // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
@@ -847,7 +849,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
     }
   }
 
-  xfer_ctl_ptr(epnum, dir)->max_packet_size = epMaxPktSize;
+  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = epMaxPktSize;
+  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum = epnum;
 
   return true;
 }
@@ -868,8 +871,10 @@ void dcd_edpt_close_all (uint8_t rhport)
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
-  uint32_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
-  uint32_t const dir   = tu_edpt_dir(ep_addr);
+
+  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  uint8_t const epnum = xfer->epnum;
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   if(dir == TUSB_DIR_IN)
   {
@@ -914,11 +919,10 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 {
   (void) rhport;
 
-  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
+  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  uint8_t const epnum = xfer->epnum;
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
-
   xfer->buffer = buffer;
   xfer->ff     = NULL; // TODO support dcd_edpt_xfer_fifo API
   xfer->total_len = total_bytes;
@@ -952,11 +956,10 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 {
   (void) rhport;
 
-  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
+  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  uint8_t const epnum = xfer->epnum;
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
-
   xfer->buffer = NULL;
   xfer->ff     = ff; // TODO support dcd_edpt_xfer_fifo API
   xfer->total_len = total_bytes;
@@ -983,7 +986,8 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
 
-  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
+  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  uint8_t const epnum = xfer->epnum;
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   if (dir == TUSB_DIR_IN)
@@ -1000,7 +1004,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 {
   (void)rhport;
 
-  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(ep_addr) : tu_edpt_number(ep_addr);
+  xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
+  uint8_t const epnum = xfer->epnum;
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   if (dir == TUSB_DIR_IN)

From ec826732fccf070b4de1369d0ee50d653689bb9c Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Tue, 25 Oct 2022 18:32:10 +0200
Subject: [PATCH 1345/2085] Fixed non-aligned allocated memory sizes

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 11 +++--
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   | 44 +++++++++----------
 2 files changed, 26 insertions(+), 29 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 7ebaa826c..cb2b5a029 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -723,7 +723,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
     return epXferCtl->pma_ptr;
   }
   
-  uint16_t addr = ep_buf_ptr; 
+  uint16_t addr = ep_buf_ptr;
   ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
   
   // Verify no overflow
@@ -772,7 +772,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   /* TODO: This hardware endpoint allocation could be more sensible. For now, simple allocation or manual allocation using callback */
   uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(p_endpoint_desc->bEndpointAddress) : tu_edpt_number(p_endpoint_desc->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc);
+  const uint16_t buffer_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc));
   uint16_t pma_addr;
   uint32_t wType;
 
@@ -809,7 +809,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
 
   /* Create a packet memory buffer area. For isochronous endpoints,
    * use the same buffer as the double buffer, essentially disabling double buffering */
-  pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, epMaxPktSize);
+  pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, buffer_size);
 
 #if defined(ISOCHRONOUS_DOUBLEBUFFER)
   if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) )
@@ -818,7 +818,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
 #endif
   {
     *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
-    pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize);
     pcd_clear_tx_dtog(USB, epnum);
   }
 #if defined(ISOCHRONOUS_DOUBLEBUFFER)
@@ -828,7 +827,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
 #endif
   {
     *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
-    pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize);
+    pcd_set_ep_rx_cnt(USB, epnum, buffer_size);
     pcd_clear_rx_dtog(USB, epnum);
   }
 
@@ -849,7 +848,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
     }
   }
 
-  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = epMaxPktSize;
+  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = buffer_size;
   xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum = epnum;
 
   return true;
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 5d26d3525..17726e521 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -131,6 +131,18 @@ static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpN
 static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
 static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue);
 
+/* Aligned buffer size according to hardware */
+static inline uint16_t pcd_aligned_buffer_size(uint16_t size)
+{
+  /* The STM32 full speed USB peripheral supports only a limited set of
+   * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
+  uint16_t blocksize = (size > 62) ? 32 : 2;
+
+  // Round up while dividing requested size by blocksize
+  uint16_t numblocks = (size + blocksize - 1) / blocksize ;
+
+  return numblocks * blocksize;
+}
 
 /* SetENDPOINT */
 static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue)
@@ -207,32 +219,18 @@ static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
   * @param  wNBlocks no. of Blocks.
   * @retval None
   */
+static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t * pdwReg, size_t wCount)
+{
+  /* We assume that the buffer size is already aligned to hardware requirements. */
+  uint16_t blocksize = (wCount > 62) ? 1 : 0;
+  uint16_t numblocks = wCount / (blocksize ? 32 : 2);
 
-static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t * pdwReg, size_t wCount)  {
-  uint32_t wNBlocks;
-  if(wCount > 62u)
-  {
-    wNBlocks = wCount >> 5u;
-    if((wCount & 0x1fU) == 0u)
-    {
-      wNBlocks--;
-    }
-    wNBlocks = wNBlocks << 10u;
-    wNBlocks |= 0x8000u; // Mark block size as 32byte
-    *pdwReg = (uint16_t)wNBlocks;
-  }
-  else
-  {
-    wNBlocks = wCount >> 1u;
-    if((wCount & 0x1U) != 0u)
-    {
-      wNBlocks++;
-    }
-    *pdwReg = (uint16_t)((wNBlocks) << 10u);
-  }
+  /* There should be no remainder in the above calculation */
+  TU_VERIFY((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/);
+
+  *pdwReg = (blocksize << 15) | (numblocks << 10);
 }
 
-
 /**
   * @brief  Sets address in an endpoint register.
   * @param  USBx USB peripheral instance register address.

From 9a8439087864e2c1e19412fb5ce329cf720f5005 Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Tue, 25 Oct 2022 18:39:09 +0200
Subject: [PATCH 1346/2085] Changed comments, added define to fail if
 ISOCHRONOUS endpoint is not available but requested

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index cb2b5a029..736150fcd 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -64,10 +64,9 @@
  * - STALL handled, but not tested.
  *   - Does it work? No clue.
  * - All EP BTABLE buffers are created based on max packet size of first EP opened with that address.
- * - No isochronous endpoints
  * - Endpoint index is the ID of the endpoint
  *   - This means that priority is given to endpoints with lower ID numbers
- *   - Code is mixing up EP IX with EP ID. Everywhere.
+ *   - Manual override of this mapping is possible through callback
  * - Packet buffer memory is copied in the interrupt.
  *   - This is better for performance, but means interrupts are disabled for longer
  *   - DMA may be the best choice, but it could also be pushed to the USBD task.
@@ -776,17 +775,19 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   uint16_t pma_addr;
   uint32_t wType;
 
-  // Isochronous not supported (yet), and some other driver assumptions.
   TU_ASSERT(epnum < MAX_EP_COUNT);
+  TU_ASSERT(buffer_size <= 1024);
 
   // Set type
   switch(p_endpoint_desc->bmAttributes.xfer) {
   case TUSB_XFER_CONTROL:
     wType = USB_EP_CONTROL;
     break;
+#if defined(ISOCHRONOUS_DOUBLEBUFFER)
   case TUSB_XFER_ISOCHRONOUS:
     wType = USB_EP_ISOCHRONOUS;
     break;
+#endif
   case TUSB_XFER_BULK:
     wType = USB_EP_CONTROL;
     break;

From 510720b396eaa610e6ae688d5f46198de4aaee29 Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Thu, 27 Oct 2022 18:51:16 +0200
Subject: [PATCH 1347/2085] Renamed pcd_set_ep_rx_cnt because it actually sets
 the maximum buffer size

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c    | 16 ++++++++--------
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h      | 10 +++++++++-
 2 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 736150fcd..9ec8ef592 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -557,9 +557,9 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
     {
       uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len;
       if(remaining >= xfer->max_packet_size) {
-        pcd_set_ep_rx_cnt(USB, EPindex,xfer->max_packet_size);
+        pcd_set_ep_rx_bufsize(USB, EPindex,xfer->max_packet_size);
       } else {
-        pcd_set_ep_rx_cnt(USB, EPindex,remaining);
+        pcd_set_ep_rx_bufsize(USB, EPindex,remaining);
       }
       pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
     }
@@ -571,7 +571,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
   if(EPindex == 0u)
   {
       // Always be prepared for a status packet...
-    pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
+    pcd_set_ep_rx_bufsize(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
     pcd_clear_rx_ep_ctr(USB, EPindex);
   }
 }
@@ -828,7 +828,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
 #endif
   {
     *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
-    pcd_set_ep_rx_cnt(USB, epnum, buffer_size);
+    pcd_set_ep_rx_bufsize(USB, epnum, buffer_size);
     pcd_clear_rx_dtog(USB, epnum);
   }
 
@@ -939,9 +939,9 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 
     if(total_bytes > xfer->max_packet_size)
     {
-      pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size);
+      pcd_set_ep_rx_bufsize(USB,epnum,xfer->max_packet_size);
     } else {
-      pcd_set_ep_rx_cnt(USB,epnum,total_bytes);
+      pcd_set_ep_rx_bufsize(USB,epnum,total_bytes);
     }
     pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID);
   }
@@ -969,9 +969,9 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   {
     if(total_bytes > xfer->max_packet_size)
     {
-      pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size);
+      pcd_set_ep_rx_bufsize(USB,epnum,xfer->max_packet_size);
     } else {
-      pcd_set_ep_rx_cnt(USB,epnum,total_bytes);
+      pcd_set_ep_rx_bufsize(USB,epnum,total_bytes);
     }
     pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID);
   }
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 17726e521..3130953b4 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -276,12 +276,20 @@ static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpN
 
 static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
 {
-  *pcd_ep_tx_cnt_ptr(USBx, bEpNum) = (uint16_t)wCount;
+  __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpNum);
+  *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
 }
 
 static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
+{
+  __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpNum);
+  *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
+}
+
+static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
 {
   __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum));
+  wCount = pcd_aligned_buffer_size(wCount);
   pcd_set_ep_cnt_rx_reg(pdwReg, wCount);
 }
 

From d584b07e2c8068a51c89421be2ddc116f4fc9d3e Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Thu, 27 Oct 2022 19:09:48 +0200
Subject: [PATCH 1348/2085] Fixed problem where the transmit byte count was
 written into the wrong register on ISOCHRONOUS endpoints

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 9ec8ef592..36548975e 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -899,19 +899,26 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
     len = xfer->max_packet_size;
   }
 
-  uint16_t oldAddr = *pcd_ep_tx_address_ptr(USB,ep_ix);
+  uint16_t ep_reg = pcd_get_endpoint(USB, ep_ix);
+  uint16_t addr_ptr = *pcd_ep_tx_address_ptr(USB,ep_ix);
 
   if (xfer->ff)
   {
-    dcd_write_packet_memory_ff(xfer->ff, oldAddr, len);
+    dcd_write_packet_memory_ff(xfer->ff, addr_ptr, len);
   }
   else
   {
-    dcd_write_packet_memory(oldAddr, &(xfer->buffer[xfer->queued_len]), len);
+    dcd_write_packet_memory(addr_ptr, &(xfer->buffer[xfer->queued_len]), len);
   }
   xfer->queued_len = (uint16_t)(xfer->queued_len + len);
 
-  pcd_set_ep_tx_cnt(USB,ep_ix,len);
+  /* Write into correct register when ISOCHRONOUS (double buffered) */
+  if ( (ep_reg & USB_EP_DTOG_TX) && ( (ep_reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) ) {
+    pcd_set_ep_rx_cnt(USB, ep_ix, len);
+  } else {
+    pcd_set_ep_tx_cnt(USB, ep_ix, len);
+  }
+
   pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID);
 }
 

From b4b619abd6badd664149604c77a0bb05ea579f86 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 29 Dec 2022 12:29:28 +0100
Subject: [PATCH 1349/2085] SHA-1: 5cb3ed518301e2237ee4e468e97e51ece0ba3838

* Correct handling of SOF interrupt
---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 21 +++++++++----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index ee188b65c..ae22bb455 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -149,12 +149,6 @@
 #  define DCD_STM32_BTABLE_LENGTH (PMA_LENGTH - DCD_STM32_BTABLE_BASE)
 #endif
 
-// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
-// We disable SOF for now until needed later on
-#ifndef USE_SOF
-#  define USE_SOF     0
-#endif
-
 /***************************************************
  * Checks, structs, defines, function definitions, etc.
  */
@@ -259,7 +253,7 @@ void dcd_init (uint8_t rhport)
     pcd_set_endpoint(USB,i,0u);
   }
 
-  USB->CNTR |= USB_CNTR_RESETM | (USE_SOF ? USB_CNTR_SOFM : 0) | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
+  USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
   dcd_handle_bus_reset();
   
   // Enable pull-up if supported
@@ -304,7 +298,14 @@ void dcd_sof_enable(uint8_t rhport, bool en)
   (void) rhport;
   (void) en;
 
-  // TODO implement later
+  if (en)
+  {
+    USB->CNTR |= USB_CNTR_SOFM;
+  }
+  else
+  {
+    USB->CNTR &= (uint16_t) ~USB_CNTR_SOFM;
+  }
 }
 
 // Enable device interrupt
@@ -655,12 +656,10 @@ void dcd_int_handler(uint8_t rhport) {
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 
-#if USE_SOF
   if(int_status & USB_ISTR_SOF) {
     clear_istr_bits(USB_ISTR_SOF);
-    dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
+    dcd_event_sof(0, USB->FNR & USB_FNR_FN, true);
   }
-#endif 
 
   if(int_status & USB_ISTR_ESOF) {
     if(remoteWakeCountdown == 1u)

From 9ec21248d7f11e14f5011ea015c5ecfba8e0632b Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Mon, 31 Oct 2022 13:42:52 +0100
Subject: [PATCH 1350/2085] Fixed various small problems and inaccuracies
 regarding ISOCHRONOUS endpoint

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c    | 16 ++++++++++++----
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h      |  9 +++++----
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index ae22bb455..8e8ffec76 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -506,7 +506,6 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
 {
   uint32_t EPindex = wIstr & USB_ISTR_EP_ID;
   uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex);
-  uint32_t count = pcd_get_ep_rx_cnt(USB,EPindex);
   uint8_t ep_addr = wEPRegVal & USB_EPADDR_FIELD;
 
   xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
@@ -518,11 +517,12 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
     return;
   }
   
-  if((EPindex == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */
+  if((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */
   {
     // The setup_received function uses memcpy, so this must first copy the setup data into
     // user memory, to allow for the 32-bit access that memcpy performs.
     uint8_t userMemBuf[8];
+    uint32_t count = pcd_get_ep_rx_cnt(USB, EPindex);
     /* Get SETUP Packet*/
     if(count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again.
     {
@@ -535,8 +535,16 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
   }
   else
   {
+    uint32_t count;
+    /* Read from correct register when ISOCHRONOUS (double buffered) */
+    if ( (wEPRegVal & USB_EP_DTOG_RX) && ( (wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS) ) {
+      count = pcd_get_ep_tx_cnt(USB, EPindex);
+    } else {
+      count = pcd_get_ep_rx_cnt(USB, EPindex);
+    }
+
     // Clear RX CTR interrupt flag
-    if(EPindex != 0u)
+    if(ep_addr != 0u)
     {
       pcd_clear_rx_ep_ctr(USB, EPindex);
     }
@@ -579,7 +587,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
   // For EP0, prepare to receive another SETUP packet.
   // Clear CTR last so that a new packet does not overwrite the packing being read.
   // (Based on the docs, it seems SETUP will always be accepted after CTR is cleared)
-  if(EPindex == 0u)
+  if(ep_addr == 0u)
   {
       // Always be prepared for a status packet...
     pcd_set_ep_rx_bufsize(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 8acce3c71..8ea659124 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -223,16 +223,17 @@ static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
   * @param  wNBlocks no. of Blocks.
   * @retval None
   */
-static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t * pdwReg, size_t wCount)
+static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwReg, size_t wCount)
 {
   /* We assume that the buffer size is already aligned to hardware requirements. */
   uint16_t blocksize = (wCount > 62) ? 1 : 0;
   uint16_t numblocks = wCount / (blocksize ? 32 : 2);
 
   /* There should be no remainder in the above calculation */
-  TU_VERIFY((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/);
+  TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/);
 
-  *pdwReg = (blocksize << 15) | (numblocks << 10);
+  /* Encode into register. When BLSIZE==1, we need to substract 1 block count */
+  *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10);
 }
 
 /**
@@ -294,7 +295,7 @@ static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx,  uint32_t bEpNum, u
 {
   __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum));
   wCount = pcd_aligned_buffer_size(wCount);
-  pcd_set_ep_cnt_rx_reg(pdwReg, wCount);
+  pcd_set_ep_cnt_reg(pdwReg, wCount);
 }
 
 /**

From 76413a95d4463d11232810e42d4f1a64a30aed2b Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Mon, 31 Oct 2022 13:47:24 +0100
Subject: [PATCH 1351/2085] Added TU_ATTR_ALWAYS_INLINE to all static inline
 functions

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |  6 +-
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   | 63 ++++++++++---------
 2 files changed, 35 insertions(+), 34 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 8e8ffec76..fefa7a330 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -175,7 +175,7 @@ typedef struct
 
 static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
 
-static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr)
+TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr)
 {
   uint8_t epnum = tu_edpt_number(ep_addr);
   uint8_t dir = tu_edpt_dir(ep_addr);
@@ -207,12 +207,12 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
 
 // Using a function due to better type checks
 // This seems better than having to do type casts everywhere else
-static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) {
+TU_ATTR_ALWAYS_INLINE static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) {
   *reg = (uint16_t)(*reg & ~mask);
 }
 
 // Bits in ISTR are cleared upon writing 0
-static inline void clear_istr_bits(uint16_t mask) {
+TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits(uint16_t mask) {
   USB->ISTR = ~mask;
 }
 
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 8ea659124..d6f10c5a9 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -131,12 +131,12 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
 TU_ATTR_WEAK uint8_t tu_stm32_edpt_number_cb(uint8_t addr);
 
 // prototypes
-static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
-static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
-static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue);
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue);
 
 /* Aligned buffer size according to hardware */
-static inline uint16_t pcd_aligned_buffer_size(uint16_t size)
+TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size)
 {
   /* The STM32 full speed USB peripheral supports only a limited set of
    * buffer sizes given by the RX buffer entry format in the USB_BTABLE. */
@@ -149,19 +149,19 @@ static inline uint16_t pcd_aligned_buffer_size(uint16_t size)
 }
 
 /* SetENDPOINT */
-static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue)
 {
   __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpNum*2u);
   *reg = (uint16_t)wRegValue;
 }
 
 /* GetENDPOINT */
-static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpNum) {
+TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpNum) {
   __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpNum*2u);
   return *reg;
 }
 
-static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wType)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wType)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal &= (uint32_t)USB_EP_T_MASK;
@@ -170,7 +170,7 @@ static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t
   pcd_set_endpoint(USBx, bEpNum, regVal);
 }
 
-static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal &= USB_EP_T_FIELD;
@@ -182,7 +182,7 @@ static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum)
   * @param  bEpNum Endpoint Number.
   * @retval None
   */
-static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal &= USB_EPREG_MASK;
@@ -190,7 +190,8 @@ static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
   regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0)
   pcd_set_endpoint(USBx, bEpNum, regVal);
 }
-static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal &= USB_EPREG_MASK;
@@ -204,13 +205,13 @@ static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
   * @param  bEpNum Endpoint Number.
   * @retval Counter value
   */
-static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
 {
   __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpNum);
   return *regPtr & 0x3ffU;
 }
 
-static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
 {
   __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpNum);
   return *regPtr & 0x3ffU;
@@ -223,7 +224,7 @@ static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
   * @param  wNBlocks no. of Blocks.
   * @retval None
   */
-static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwReg, size_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwReg, size_t wCount)
 {
   /* We assume that the buffer size is already aligned to hardware requirements. */
   uint16_t blocksize = (wCount > 62) ? 1 : 0;
@@ -243,7 +244,7 @@ static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwReg, size_t wCount)
   * @param  bAddr Address.
   * @retval None
   */
-static inline void pcd_set_ep_address(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t bAddr)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t bAddr)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal &= USB_EPREG_MASK;
@@ -252,7 +253,7 @@ static inline void pcd_set_ep_address(USB_TypeDef * USBx,  uint32_t bEpNum, uint
   pcd_set_endpoint(USBx, bEpNum,regVal);
 }
 
-static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
 {
   size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
   total_word_offset *= PMA_STRIDE;
@@ -260,38 +261,38 @@ static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
 }
 
 // Pointers to the PMA table entries (using the ARM address space)
-static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
 {
   return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 0u);
 }
-static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
 {
   return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 1u);
 }
 
-static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
 {
   return  pcd_btable_word_ptr(USBx,(bEpNum)*4u + 2u);
 }
 
-static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
 {
   return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 3u);
 }
 
-static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
 {
   __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpNum);
   *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
 }
 
-static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
 {
   __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpNum);
   *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
 }
 
-static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
 {
   __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum));
   wCount = pcd_aligned_buffer_size(wCount);
@@ -305,7 +306,7 @@ static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx,  uint32_t bEpNum, u
   * @param  wState new state
   * @retval None
   */
-static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wState)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wState)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal &= USB_EPTX_DTOGMASK;
@@ -332,7 +333,7 @@ static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx,  uint32_t bEpNum, ui
   * @retval None
   */
 
-static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wState)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wState)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal &= USB_EPRX_DTOGMASK;
@@ -351,7 +352,7 @@ static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpNum, ui
   pcd_set_endpoint(USBx, bEpNum, regVal);
 } /* pcd_set_ep_rx_status */
 
-static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpNum)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   return (regVal & USB_EPRX_STAT) >> (12u);
@@ -364,7 +365,7 @@ static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpNum
   * @param  bEpNum Endpoint Number.
   * @retval None
   */
-static inline void pcd_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal &= USB_EPREG_MASK;
@@ -372,7 +373,7 @@ static inline void pcd_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
   pcd_set_endpoint(USBx, bEpNum, regVal);
 }
 
-static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal &= USB_EPREG_MASK;
@@ -387,7 +388,7 @@ static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
   * @retval None
   */
 
-static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   if((regVal & USB_EP_DTOG_RX) != 0)
@@ -396,7 +397,7 @@ static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
   }
 }
 
-static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   if((regVal & USB_EP_DTOG_TX) != 0)
@@ -412,7 +413,7 @@ static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
   * @retval None
   */
 
-static inline void pcd_set_ep_kind(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx,  uint32_t bEpNum)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal |= USB_EP_KIND;
@@ -420,7 +421,7 @@ static inline void pcd_set_ep_kind(USB_TypeDef * USBx,  uint32_t bEpNum)
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
   pcd_set_endpoint(USBx, bEpNum, regVal);
 }
-static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum)
 {
   uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
   regVal &= USB_EPKIND_MASK;

From 1d37f5ef9b94d53d8a90b73934913aa4252011e5 Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Sun, 6 Nov 2022 12:40:14 +0100
Subject: [PATCH 1352/2085] Added improvements with regards to SOF timing
 jitter

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c        | 12 +++++++-----
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h |  3 +++
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index fefa7a330..d6ca59756 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -627,6 +627,13 @@ void dcd_int_handler(uint8_t rhport) {
   // dcd_ep_ctr_handler(), so less need to loop here. The other interrupts shouldn't
   // be triggered repeatedly.
 
+  /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
+  if(int_status & USB_ISTR_SOF) {
+    clear_istr_bits(USB_ISTR_SOF);
+    if (tu_stm32_sof_cb) tu_stm32_sof_cb();
+    dcd_event_sof(0, USB->FNR & USB_FNR_FN, true);
+  }
+
   if(int_status & USB_ISTR_RESET) {
     // USBRST is start of reset.
     clear_istr_bits(USB_ISTR_RESET);
@@ -664,11 +671,6 @@ void dcd_int_handler(uint8_t rhport) {
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 
-  if(int_status & USB_ISTR_SOF) {
-    clear_istr_bits(USB_ISTR_SOF);
-    dcd_event_sof(0, USB->FNR & USB_FNR_FN, true);
-  }
-
   if(int_status & USB_ISTR_ESOF) {
     if(remoteWakeCountdown == 1u)
     {
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index d6f10c5a9..40af9b3a5 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -130,6 +130,9 @@ static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
 // this callback and defining a custom mapping in your application
 TU_ATTR_WEAK uint8_t tu_stm32_edpt_number_cb(uint8_t addr);
 
+// This callback is called on SOF and can be used to e.g. capture a timer value for timing purposes
+TU_ATTR_WEAK void tu_stm32_sof_cb(void);
+
 // prototypes
 TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
 TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);

From 17990025bbe9017eb5a8b636cbf5345a58812587 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 28 Dec 2022 17:14:23 +0100
Subject: [PATCH 1353/2085] dcd_stm32_fsdev : Fix index out of bound in
 dcd_write_packet_memory() If src is odd then src[wNBytes] is accessed.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index d6ca59756..e5006809d 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -1064,8 +1064,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   */
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
 {
-  uint32_t n =  ((uint32_t)wNBytes + 1U) >> 1U;
-  uint32_t i;
+  uint32_t n = (uint32_t)wNBytes >> 1U;
   uint16_t temp1, temp2;
   const uint8_t * srcVal;
 
@@ -1076,15 +1075,22 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
   srcVal = src;
   pdwVal = &pma[PMA_STRIDE*(dst>>1)];
 
-  for (i = n; i != 0; i--)
+  while (n--)
   {
-    temp1 = (uint16_t) *srcVal;
+    temp1 = (uint16_t)*srcVal;
     srcVal++;
-    temp2 = temp1 | ((uint16_t)((uint16_t) ((*srcVal) << 8U))) ;
+    temp2 = temp1 | ((uint16_t)(((uint16_t)(*srcVal)) << 8U)) ;
     *pdwVal = temp2;
     pdwVal += PMA_STRIDE;
     srcVal++;
   }
+
+  if (wNBytes & 0x01)
+  {
+    temp1 = *srcVal;
+    *pdwVal = temp2;
+  }
+
   return true;
 }
 
@@ -1141,7 +1147,6 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes)
 {
   uint32_t n = (uint32_t)wNBytes >> 1U;
-  uint32_t i;
   // The GCC optimizer will combine access to 32-bit sizes if we let it. Force
   // it volatile so that it won't do that.
   __IO const uint16_t *pdwVal;
@@ -1150,7 +1155,7 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
   pdwVal = &pma[PMA_STRIDE*(src>>1)];
   uint8_t *dstVal = (uint8_t*)dst;
 
-  for (i = n; i != 0U; i--)
+  while (n--)
   {
     temp = *pdwVal;
     pdwVal += PMA_STRIDE;

From b156a8b78c5ede08849bd30a05c4e43ac211b068 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 28 Dec 2022 17:16:49 +0100
Subject: [PATCH 1354/2085] dcd_stm32_fsdev : Implement FIFO transfer
 correctly.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 117 ++++++++++--------
 1 file changed, 68 insertions(+), 49 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index e5006809d..e259991ae 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -6,6 +6,8 @@
  * Portions:
  * Copyright (c) 2016 STMicroelectronics
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2022 Simon Küppers (skuep)
+ * Copyright (c) 2022 HiFiPhile
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -987,7 +989,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   xfer->buffer = NULL;
-  xfer->ff     = ff; // TODO support dcd_edpt_xfer_fifo API
+  xfer->ff     = ff;
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
 
@@ -1088,7 +1090,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
   if (wNBytes & 0x01)
   {
     temp1 = *srcVal;
-    *pdwVal = temp2;
+    *pdwVal = temp1;
   }
 
   return true;
@@ -1100,40 +1102,46 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
   * @param   wNBytes no. of bytes to be copied.
   * @retval None
   */
-
-// THIS FUNCTION IS UNTESTED
-
 static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes)
 {
   // Since we copy from a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
-  // Check for first linear part
   tu_fifo_buffer_info_t info;
-  tu_fifo_get_read_info(ff, &info);  // We want to read from the FIFO
-  TU_VERIFY(info.len_lin && dcd_write_packet_memory(dst, info.ptr_lin, info.len_lin));           // and write it into the PMA
-  tu_fifo_advance_read_pointer(ff, info.len_lin);
-
-  // Check for wrapped part
-  if (info.len_wrap)
+  tu_fifo_get_read_info(ff, &info); 
+  
+  uint16_t cnt_lin =  TU_MIN(wNBytes, info.len_lin);
+  uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap);
+  
+  // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
+  // last lin byte will be combined with wrapped part
+  // To ensure PMA is always access 16bit aligned (dst aligned to 16 bit)
+  if((cnt_lin & 0x01) && cnt_wrap)
   {
-    // Update destination pointer
-    dst += info.len_lin;
-    uint8_t* src = (uint8_t*)info.ptr_wrap;
-    uint16_t len2 = info.len_wrap;
+    // Copy first linear part
+    dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin &~0x01);
+    dst += cnt_lin &~0x01;
 
-    // Since PMA is accessed 16-bit wise we need to handle the case when a 16 bit value was split
-    if (info.len_lin % 2)    // If len is uneven there is a byte left to copy
-    {
-      TU_ASSERT(false); // TODO: Step through and check -> untested
+    // Copy last linear byte & first wrapped byte
+    uint16_t tmp = ((uint8_t*)info.ptr_lin)[cnt_lin - 1] | ((uint16_t)(((uint8_t*)info.ptr_wrap)[0]) << 8U);
+    dcd_write_packet_memory(dst, &tmp, 2);
+    dst += 2;
 
-      uint16_t temp = ((uint8_t *)info.ptr_lin)[info.len_lin-1] | src[0] << 16; // CHECK endianess
-      pma[PMA_STRIDE*(dst>>1)] = temp;
-      src++;
-      len2--;
-    }
-
-    TU_VERIFY(dcd_write_packet_memory(dst, src, len2));
-    tu_fifo_advance_write_pointer(ff, info.len_wrap);
+    // Copy rest of wrapped byte
+    dcd_write_packet_memory(dst, ((uint8_t*)info.ptr_wrap) + 1, cnt_wrap - 1);
   }
+  else
+  {
+    // Copy linear part
+    dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin);
+    dst += info.len_lin;
+
+    if(info.len_wrap)
+    {
+      // Copy wrapped byte
+      dcd_write_packet_memory(dst, info.ptr_wrap, cnt_wrap);
+    }
+  }
+
+  tu_fifo_advance_read_pointer(ff, cnt_lin + cnt_wrap);
 
   return true;
 }
@@ -1178,9 +1186,6 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
   * @param   wNBytes no. of bytes to be copied.
   * @retval None
   */
-
-// THIS FUNCTION IS UNTESTED
-
 static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes)
 {
   // Since we copy into a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
@@ -1188,29 +1193,43 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
   tu_fifo_buffer_info_t info;
   tu_fifo_get_write_info(ff, &info);  // We want to read from the FIFO
 
-  TU_VERIFY(info.len_lin && dcd_read_packet_memory(info.ptr_lin, src, info.len_lin));
-  tu_fifo_advance_write_pointer(ff, info.len_lin);
+  uint16_t cnt_lin =  TU_MIN(wNBytes, info.len_lin);
+  uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap);
 
-  // Check for wrapped part
-  if (info.len_wrap)
+  // We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part,
+  // last lin byte will be combined with wrapped part
+  // To ensure PMA is always access 16bit aligned (src aligned to 16 bit)
+  if((cnt_lin & 0x01) && cnt_wrap)
   {
-    // Update source pointer
-    src += info.len_lin;
+    // Copy first linear part
+    dcd_read_packet_memory(info.ptr_lin, src, cnt_lin &~0x01);
+    src += cnt_lin &~0x01;
 
-    // Since PMA is accessed 16-bit wise we need to handle the case when a 16 bit value was split
-    if (info.len_lin % 2)    // If len is uneven there is a byte left to copy
-    {
-      TU_ASSERT(false); //TODO: step through -> untested
-      uint32_t temp = pma[PMA_STRIDE*(src>>1)];
-      *((uint8_t *)info.ptr_wrap++) = ((temp >> 8) & 0xFF);
-      src++;
-      tu_fifo_advance_write_pointer(ff, 1);
-      info.len_wrap--;
-    }
+    // Copy last linear byte & first wrapped byte
+    uint16_t tmp;
+    dcd_read_packet_memory(&tmp, src, 2);
+    
+    ((uint8_t*)info.ptr_lin)[cnt_lin - 1] = (uint8_t)tmp;
+    ((uint8_t*)info.ptr_wrap)[0] = (uint8_t)(tmp >> 8U);
+    src += 2;
 
-    TU_VERIFY(dcd_read_packet_memory(info.ptr_wrap, src, info.len_wrap));
-    tu_fifo_advance_write_pointer(ff, info.len_wrap);
+    // Copy rest of wrapped byte
+    dcd_read_packet_memory(((uint8_t*)info.ptr_wrap) + 1, src, cnt_wrap - 1);
   }
+  else
+  {
+    // Copy linear part
+    dcd_read_packet_memory(info.ptr_lin, src, cnt_lin);
+    src += cnt_lin;
+
+    if(info.len_wrap)
+    {
+      // Copy wrapped byte
+      dcd_read_packet_memory(info.ptr_wrap, src, cnt_wrap);
+    }
+  }
+
+  tu_fifo_advance_write_pointer(ff, cnt_lin + cnt_wrap);
 
   return true;
 }

From ef2f17a514fb0967261c3a8308af017b5d911e15 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 28 Dec 2022 23:45:10 +0100
Subject: [PATCH 1355/2085] Add hardware endpoint allocator.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 97 +++++++++++++++++--
 1 file changed, 90 insertions(+), 7 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index e259991ae..0d566da12 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -66,9 +66,6 @@
  * - STALL handled, but not tested.
  *   - Does it work? No clue.
  * - All EP BTABLE buffers are created based on max packet size of first EP opened with that address.
- * - Endpoint index is the ID of the endpoint
- *   - This means that priority is given to endpoints with lower ID numbers
- *   - Manual override of this mapping is possible through callback
  * - Packet buffer memory is copied in the interrupt.
  *   - This is better for performance, but means interrupts are disabled for longer
  *   - DMA may be the best choice, but it could also be pushed to the USBD task.
@@ -186,6 +183,16 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr)
   return &xfer_status[epnum][dir];
 }
 
+// EP allocator
+typedef struct
+{
+  uint8_t ep_num;
+  uint8_t ep_type;
+  bool allocated[2];
+} ep_alloc_t;
+
+static ep_alloc_t ep_alloc_status[STFSDEV_EP_COUNT];
+
 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
 
 static uint8_t remoteWakeCountdown; // When wake is requested
@@ -201,6 +208,8 @@ static uint16_t ep_buf_ptr; ///< Points to first free memory location
 static void dcd_pma_alloc_reset(void);
 static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length);
 static void dcd_pma_free(uint8_t ep_addr);
+static void dcd_ep_free(uint8_t ep_addr);
+static uint8_t dcd_ep_alloc(tusb_desc_endpoint_t const * p_endpoint_desc);
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes);
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes);
 
@@ -458,10 +467,17 @@ static void dcd_handle_bus_reset(void)
   //__IO uint16_t * const epreg = &(EPREG(0));
   USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
 
-  // Clear all EPREG (or maybe this is automatic? I'm not sure)
+  
   for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
   {
+    // Clear all EPREG (or maybe this is automatic? I'm not sure)
     pcd_set_endpoint(USB,i,0u);
+    
+    // Clear EP allocation status
+    ep_alloc_status[i].ep_num = 0xFF;
+    ep_alloc_status[i].ep_type = 0xFF;
+    ep_alloc_status[i].allocated[0] = false;
+    ep_alloc_status[i].allocated[1] = false;
   }
 
   dcd_pma_alloc_reset();
@@ -783,20 +799,85 @@ static void dcd_pma_free(uint8_t ep_addr)
   }
 }
 
+/***
+ * Allocate hardware endpoint
+ */
+static uint8_t dcd_ep_alloc(tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  uint8_t const eptype = p_endpoint_desc->bmAttributes.xfer;
+
+  for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++)
+  {
+    // If EP of current direction is not allocated
+    // Except for ISO endpoint, both direction should be free
+    if(!ep_alloc_status[i].allocated[dir] &&
+       (eptype != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1]))
+    {
+      // Check if EP number is the same
+      if(ep_alloc_status[i].ep_num == 0xFF ||
+         ep_alloc_status[i].ep_num == epnum)
+      {
+        // One EP pair has to be the same type
+        if(ep_alloc_status[i].ep_type == 0xFF ||
+           ep_alloc_status[i].ep_type == eptype)
+        {
+          ep_alloc_status[i].ep_num = epnum;
+          ep_alloc_status[i].ep_type = eptype;
+          ep_alloc_status[i].allocated[dir] = true;
+          
+          return i;
+        }
+      }
+    }
+  }
+
+  // Allocation failed
+  TU_ASSERT(0);
+}
+
+/***
+ * Free hardware endpoint
+ */
+static void dcd_ep_free(uint8_t ep_addr)
+{
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++)
+  {
+    // Check if EP number & dir are the same
+    if(ep_alloc_status[i].ep_num == epnum && 
+       ep_alloc_status[i].allocated[dir] == dir)
+    {
+      ep_alloc_status[i].allocated[dir] = false;
+      // Reset entry if ISO endpoint or both direction are free
+      if(ep_alloc_status[i].ep_type == TUSB_XFER_ISOCHRONOUS ||
+         !ep_alloc_status[i].allocated[dir ^ 1])
+      {
+        ep_alloc_status[i].ep_num = 0xFF;
+        ep_alloc_status[i].ep_type = 0xFF;
+
+        return;
+      }
+    }
+  }
+}
+
 // The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers,
 // so I'm using the #define from HAL here, instead.
 
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   (void)rhport;
-  /* TODO: This hardware endpoint allocation could be more sensible. For now, simple allocation or manual allocation using callback */
-  uint8_t const epnum = tu_stm32_edpt_number_cb ? tu_stm32_edpt_number_cb(p_endpoint_desc->bEndpointAddress) : tu_edpt_number(p_endpoint_desc->bEndpointAddress);
+  uint8_t const epnum = dcd_ep_alloc(p_endpoint_desc);
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   const uint16_t buffer_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc));
   uint16_t pma_addr;
   uint32_t wType;
 
-  TU_ASSERT(epnum < MAX_EP_COUNT);
+  TU_ASSERT(epnum < STFSDEV_EP_COUNT);
   TU_ASSERT(buffer_size <= 1024);
 
   // Set type
@@ -906,6 +987,8 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
     pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS);
   }
 
+  dcd_ep_free(ep_addr);
+
   dcd_pma_free(ep_addr);
 }
 

From cece59df22cdd6d07f49676ff356a781d4536245 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 29 Dec 2022 11:44:10 +0100
Subject: [PATCH 1356/2085] Generally enable ISO xfer.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c       | 13 ++-----------
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h         |  2 --
 2 files changed, 2 insertions(+), 13 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 0d566da12..de8802d15 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -885,11 +885,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   case TUSB_XFER_CONTROL:
     wType = USB_EP_CONTROL;
     break;
-#if defined(ISOCHRONOUS_DOUBLEBUFFER)
   case TUSB_XFER_ISOCHRONOUS:
     wType = USB_EP_ISOCHRONOUS;
     break;
-#endif
   case TUSB_XFER_BULK:
     wType = USB_EP_CONTROL;
     break;
@@ -914,20 +912,13 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
    * use the same buffer as the double buffer, essentially disabling double buffering */
   pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, buffer_size);
 
-#if defined(ISOCHRONOUS_DOUBLEBUFFER)
   if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) )
-#else
-  if(dir == TUSB_DIR_IN)
-#endif
   {
     *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
     pcd_clear_tx_dtog(USB, epnum);
   }
-#if defined(ISOCHRONOUS_DOUBLEBUFFER)
+
   if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) )
-#else
-  else
-#endif
   {
     *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
     pcd_set_ep_rx_bufsize(USB, epnum, buffer_size);
@@ -1035,7 +1026,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   xfer->buffer = buffer;
-  xfer->ff     = NULL; // TODO support dcd_edpt_xfer_fifo API
+  xfer->ff     = NULL;
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
 
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 40af9b3a5..b64776fc9 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -66,7 +66,6 @@
       defined(STM32F373xC)
   #include "stm32f3xx.h"
   #define PMA_LENGTH (512u)
-  #define ISOCHRONOUS_DOUBLEBUFFER
   // NO internal Pull-ups
   //         *B, and *C:    1 x 16 bits/word
   // PMA dedicated to USB (no sharing with CAN)
@@ -76,7 +75,6 @@
       defined(STM32F303xD) || defined(STM32F303xE)
   #include "stm32f3xx.h"
   #define PMA_LENGTH (1024u)
-  #define ISOCHRONOUS_DOUBLEBUFFER
   // NO internal Pull-ups
   // *6, *8, *D, and *E:    2 x 16 bits/word     LPM Support
   // When CAN clock is enabled, USB can use first 768 bytes ONLY.

From 8a1184e7b3092d96325f7e252b527d3d0755c727 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 29 Dec 2022 14:17:43 +0100
Subject: [PATCH 1357/2085] Minor audio_test example fix. Fix
 CFG_TUD_AUDIO_EP_SZ_IN size.

---
 examples/device/audio_test/src/main.c                | 6 +++---
 examples/device/audio_test/src/plot_audio_samples.py | 4 ++++
 examples/device/audio_test/src/tusb_config.h         | 2 +-
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index d0849c7ac..56961e427 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -71,7 +71,7 @@ audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1];
 audio_control_range_4_n_t(1) sampleFreqRng; 						// Sample frequency range state
 
 // Audio test data
-uint16_t test_buffer_audio[CFG_TUD_AUDIO_EP_SZ_IN/2];
+uint16_t test_buffer_audio[(CFG_TUD_AUDIO_EP_SZ_IN - 2) / 2];
 uint16_t startVal = 0;
 
 void led_blinking_task(void);
@@ -400,7 +400,7 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
   (void) ep_in;
   (void) cur_alt_setting;
 
-  tud_audio_write ((uint8_t *)test_buffer_audio, CFG_TUD_AUDIO_EP_SZ_IN);
+  tud_audio_write ((uint8_t *)test_buffer_audio, CFG_TUD_AUDIO_EP_SZ_IN - 2);
 
   return true;
 }
@@ -413,7 +413,7 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin
   (void) ep_in;
   (void) cur_alt_setting;
 
-  for (size_t cnt = 0; cnt < CFG_TUD_AUDIO_EP_SZ_IN/2; cnt++)
+  for (size_t cnt = 0; cnt < (CFG_TUD_AUDIO_EP_SZ_IN - 2) / 2; cnt++)
   {
     test_buffer_audio[cnt] = startVal++;
   }
diff --git a/examples/device/audio_test/src/plot_audio_samples.py b/examples/device/audio_test/src/plot_audio_samples.py
index 6e3c4978e..2303df3d0 100644
--- a/examples/device/audio_test/src/plot_audio_samples.py
+++ b/examples/device/audio_test/src/plot_audio_samples.py
@@ -2,6 +2,7 @@ import sounddevice as sd
 import matplotlib.pyplot as plt
 import numpy as np
 import platform
+import csv
 
 if __name__ == '__main__':
 
@@ -31,4 +32,7 @@ if __name__ == '__main__':
     plt.ylabel('Amplitude')
     plt.title('MicNode')
     plt.show()
+    
+    samples = np.array(myrecording)
+    np.savetxt('Output.csv', samples, delimiter=",", fmt='%s')
     
\ No newline at end of file
diff --git a/examples/device/audio_test/src/tusb_config.h b/examples/device/audio_test/src/tusb_config.h
index 355ed1011..9f38612a9 100644
--- a/examples/device/audio_test/src/tusb_config.h
+++ b/examples/device/audio_test/src/tusb_config.h
@@ -114,7 +114,7 @@ extern "C" {
 #define CFG_TUD_AUDIO_ENABLE_EP_IN                                    1
 #define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX                    2                                       // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                            1                                       // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below - be aware: for different number of channels you need another descriptor!
-#define CFG_TUD_AUDIO_EP_SZ_IN                                        48 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX      // 48 Samples (48 kHz) x 2 Bytes/Sample x 1 Channel
+#define CFG_TUD_AUDIO_EP_SZ_IN                                        (48 + 1) * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX      // 48 Samples (48 kHz) x 2 Bytes/Sample x CFG_TUD_AUDIO_N_CHANNELS_TX Channels - One extra sample is needed for asynchronous transfer adjustment, see feedback EP
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX                             CFG_TUD_AUDIO_EP_SZ_IN                  // Maximum EP IN size for all AS alternate settings used
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ                          CFG_TUD_AUDIO_EP_SZ_IN + 1
 

From fe8c170c98c40a2fb517cbeaa49336b5af572c0f Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 29 Dec 2022 19:19:27 +0100
Subject: [PATCH 1358/2085] Add dcd_edpt_iso_alloc() / dcd_edpt_iso_activate()
 for ISO EP buffer management.

---
 src/device/dcd.h                              |  6 ++
 src/device/usbd.c                             | 19 +++++
 src/device/usbd_pvt.h                         |  6 ++
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 77 +++++++++++++++----
 4 files changed, 94 insertions(+), 14 deletions(-)

diff --git a/src/device/dcd.h b/src/device/dcd.h
index c1780f656..ef92d71d0 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -167,6 +167,12 @@ void dcd_edpt_stall           (uint8_t rhport, uint8_t ep_addr);
 // This API never calls with control endpoints, since it is auto cleared when receiving setup packet
 void dcd_edpt_clear_stall     (uint8_t rhport, uint8_t ep_addr);
 
+// Allocate packet buffer used by ISO endpoints
+// Some MCU need manual packet buffer allocation, we allocation largest size to avoid clustering
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
+
+// Configure and enable an ISO endpoint according to descriptor
+bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc);
 //--------------------------------------------------------------------+
 // Event API (implemented by stack)
 //--------------------------------------------------------------------+
diff --git a/src/device/usbd.c b/src/device/usbd.c
index f652a878e..8b5e4d745 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1380,4 +1380,23 @@ void usbd_sof_enable(uint8_t rhport, bool en)
   dcd_sof_enable(rhport, en);
 }
 
+bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size)
+{
+  rhport = _usbd_rhport;
+
+  TU_ASSERT(tu_edpt_number(ep_addr) < CFG_TUD_ENDPPOINT_MAX);
+
+  return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size);
+}
+
+bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
+{
+  rhport = _usbd_rhport;
+
+  TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX);
+  TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
+
+  return dcd_edpt_iso_activate(rhport, desc_ep);
+}
+
 #endif
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 6fad46db3..f860ab0a1 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -96,6 +96,12 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr);
 // Check if endpoint is stalled
 bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr);
 
+// Allocate packet buffer used by ISO endpoints
+bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
+
+// Configure and enable an ISO endpoint according to descriptor
+bool usbd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc);
+
 // Check if endpoint is ready (not busy and not stalled)
 TU_ATTR_ALWAYS_INLINE static inline
 bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr)
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index de8802d15..59f155111 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -209,7 +209,7 @@ static void dcd_pma_alloc_reset(void);
 static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length);
 static void dcd_pma_free(uint8_t ep_addr);
 static void dcd_ep_free(uint8_t ep_addr);
-static uint8_t dcd_ep_alloc(tusb_desc_endpoint_t const * p_endpoint_desc);
+static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type);
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes);
 static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes);
 
@@ -758,13 +758,15 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
     TU_ASSERT(length <= epXferCtl->pma_alloc_size, 0xFFFF);  // Verify no larger than previous alloc
     return epXferCtl->pma_ptr;
   }
-  
+
+  open_ep_count++;
+
   uint16_t addr = ep_buf_ptr;
   ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer
-  
+
   // Verify no overflow
   TU_ASSERT(ep_buf_ptr <= PMA_LENGTH, 0xFFFF);
-  
+
   epXferCtl->pma_ptr = addr;
   epXferCtl->pma_alloc_size = length;
   //TU_LOG2("dcd_pma_alloc(%x,%x)=%x\r\n",ep_addr,length,addr);
@@ -802,18 +804,17 @@ static void dcd_pma_free(uint8_t ep_addr)
 /***
  * Allocate hardware endpoint
  */
-static uint8_t dcd_ep_alloc(tusb_desc_endpoint_t const * p_endpoint_desc)
+static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
 {
-  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  uint8_t const eptype = p_endpoint_desc->bmAttributes.xfer;
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++)
   {
     // If EP of current direction is not allocated
     // Except for ISO endpoint, both direction should be free
     if(!ep_alloc_status[i].allocated[dir] &&
-       (eptype != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1]))
+       (ep_type != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1]))
     {
       // Check if EP number is the same
       if(ep_alloc_status[i].ep_num == 0xFF ||
@@ -821,10 +822,10 @@ static uint8_t dcd_ep_alloc(tusb_desc_endpoint_t const * p_endpoint_desc)
       {
         // One EP pair has to be the same type
         if(ep_alloc_status[i].ep_type == 0xFF ||
-           ep_alloc_status[i].ep_type == eptype)
+           ep_alloc_status[i].ep_type == ep_type)
         {
           ep_alloc_status[i].ep_num = epnum;
-          ep_alloc_status[i].ep_type = eptype;
+          ep_alloc_status[i].ep_type = ep_type;
           ep_alloc_status[i].allocated[dir] = true;
           
           return i;
@@ -871,7 +872,7 @@ static void dcd_ep_free(uint8_t ep_addr)
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   (void)rhport;
-  uint8_t const epnum = dcd_ep_alloc(p_endpoint_desc);
+  uint8_t const epnum = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer);
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   const uint16_t buffer_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc));
   uint16_t pma_addr;
@@ -900,8 +901,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
     TU_ASSERT(false);
   }
 
-  open_ep_count++;
-
   pcd_set_eptype(USB, epnum, wType);
   pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
   // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
@@ -983,6 +982,56 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
   dcd_pma_free(ep_addr);
 }
 
+bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size)
+{
+  (void)rhport;
+  
+  TU_ASSERT(largest_packet_size <= 1024);
+  
+  uint8_t const epnum = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
+  const uint16_t buffer_size = pcd_aligned_buffer_size(largest_packet_size);
+
+  /* Create a packet memory buffer area. For isochronous endpoints,
+   * use the same buffer as the double buffer, essentially disabling double buffering */
+  dcd_pma_alloc(ep_addr, buffer_size);
+
+  xfer_ctl_ptr(ep_addr)->epnum = epnum;
+
+  return true;
+}
+
+bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc)
+{
+  (void)rhport;
+  uint8_t const epnum = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum;
+  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
+  uint16_t pma_addr;
+
+  /* Disable endpoint */
+  pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS);
+  pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS);
+
+  pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS);
+  pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
+  // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
+  // or being double-buffered (bulk endpoints)
+  pcd_clear_ep_kind(USB,0);
+
+  pma_addr = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->pma_ptr;
+
+  *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
+  pcd_clear_tx_dtog(USB, epnum);
+
+  *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
+  pcd_set_ep_rx_bufsize(USB, epnum, packet_size);
+  pcd_clear_rx_dtog(USB, epnum);
+
+  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size;
+
+  return true;
+}
+
 // Currently, single-buffered, and only 64 bytes at a time (max)
 
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)

From e4f07206f8cbb177f3515f1fdbd5ed1f8cc9f668 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 29 Dec 2022 19:34:12 +0100
Subject: [PATCH 1359/2085] UAC : Enable fifo based transfer on stm32_fsdev

---
 src/class/audio/audio_device.c | 25 +++++++++----------------
 src/device/dcd.h               |  4 ++--
 2 files changed, 11 insertions(+), 18 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 698fba566..82682f162 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -76,26 +76,19 @@
 // Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer
 // is available or driver is would need to be changed dramatically
 
-// Only STM32 synopsys and dcd_transdimension use non-linear buffer for now
-// Synopsys detection copied from dcd_synopsys.c (refactor later on)
-#if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
-    defined (STM32F107xB) || defined (STM32F107xC)
-#define STM32F1_SYNOPSYS
-#endif
-
-#if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
-    defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
-    defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
-    defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
-#define STM32L4_SYNOPSYS
-#endif
-
-#if (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \
+// Only STM32 and dcd_transdimension use non-linear buffer for now
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32F1                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32F2                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32F3                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32F4                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32F7                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32H7                               || \
-    (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) || \
+    CFG_TUSB_MCU == OPT_MCU_STM32L0                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32L1                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32L4                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32G4                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32WB                               || \
     CFG_TUSB_MCU == OPT_MCU_RX63X                                 || \
     CFG_TUSB_MCU == OPT_MCU_RX65X                                 || \
     CFG_TUSB_MCU == OPT_MCU_RX72N                                 || \
diff --git a/src/device/dcd.h b/src/device/dcd.h
index ef92d71d0..2980cc4e6 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -169,10 +169,10 @@ void dcd_edpt_clear_stall     (uint8_t rhport, uint8_t ep_addr);
 
 // Allocate packet buffer used by ISO endpoints
 // Some MCU need manual packet buffer allocation, we allocation largest size to avoid clustering
-bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
+TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
 
 // Configure and enable an ISO endpoint according to descriptor
-bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc);
+TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc);
 //--------------------------------------------------------------------+
 // Event API (implemented by stack)
 //--------------------------------------------------------------------+

From 0bd41d53549183576553ec2fb84f00926c25e44c Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 29 Dec 2022 21:02:10 +0100
Subject: [PATCH 1360/2085] Fix CI.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c        | 4 ++--
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 59f155111..f3b55cd75 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -178,7 +178,8 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr)
 {
   uint8_t epnum = tu_edpt_number(ep_addr);
   uint8_t dir = tu_edpt_dir(ep_addr);
-  TU_ASSERT(epnum < MAX_EP_COUNT);
+  // Fix -Werror=null-dereference
+  TU_ASSERT(epnum < MAX_EP_COUNT, &xfer_status[0][0]);
 
   return &xfer_status[epnum][dir];
 }
@@ -1004,7 +1005,6 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
 {
   (void)rhport;
   uint8_t const epnum = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum;
-  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
   uint16_t pma_addr;
 
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index b64776fc9..382374614 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -234,7 +234,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwRe
   /* There should be no remainder in the above calculation */
   TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/);
 
-  /* Encode into register. When BLSIZE==1, we need to substract 1 block count */
+  /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
   *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10);
 }
 

From db65759b1eb24c8dc20dfd77f2ff0ea07914e9d2 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 29 Dec 2022 23:29:50 +0100
Subject: [PATCH 1361/2085] Use weak for
 dcd_edpt_iso_alloc/dcd_edpt_iso_activate

---
 src/device/usbd.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 8b5e4d745..ea9ab91b6 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1386,7 +1386,10 @@ bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packe
 
   TU_ASSERT(tu_edpt_number(ep_addr) < CFG_TUD_ENDPPOINT_MAX);
 
-  return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size);
+  if (dcd_edpt_iso_alloc)
+    return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size);
+  else
+    return false;
 }
 
 bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
@@ -1396,7 +1399,10 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep
   TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX);
   TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
 
-  return dcd_edpt_iso_activate(rhport, desc_ep);
+  if (dcd_edpt_iso_activate)
+    return dcd_edpt_iso_activate(rhport, desc_ep);
+  else
+    return false;
 }
 
 #endif

From 07ad64adfe192a3cdc6dc20088d98dbb6beb0f58 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 29 Dec 2022 23:30:24 +0100
Subject: [PATCH 1362/2085] Do not set USB_EP_RX_NAK for ISO EP.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index f3b55cd75..d462fc649 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -1170,9 +1170,11 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   }
   else
   { // OUT
+    if (pcd_get_eptype(USB, epnum) !=  USB_EP_ISOCHRONOUS) {
+      pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
+    }
     /* Reset to DATA0 if clearing stall condition. */
     pcd_clear_rx_dtog(USB, epnum);
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
   }
 }
 

From 21bdafcfef4cfdbd77277da1717c8a33544b8721 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Fri, 30 Dec 2022 01:05:12 +0100
Subject: [PATCH 1363/2085] Add ISO buffer allocation.

---
 src/class/audio/audio_device.c                | 123 +++++++++++++++++-
 src/device/usbd.c                             |  12 +-
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |  37 ++++--
 3 files changed, 155 insertions(+), 17 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 82682f162..a8a2439bc 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -106,6 +106,18 @@
 #define  USE_LINEAR_BUFFER     1
 #endif
 
+// Temporarily put the check here for stm32_fsdev
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32F3                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32L0                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32L1                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32G4                               || \
+    CFG_TUSB_MCU == OPT_MCU_STM32WB
+#define  USE_ISO_EP_ALLOCATION   1
+#else
+#define  USE_ISO_EP_ALLOCATION   0
+#endif
+
 // Declaration of buffers
 
 // Check for maximum supported numbers
@@ -1467,6 +1479,104 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 #endif
       }
 
+#if USE_ISO_EP_ALLOCATION
+#if CFG_TUD_AUDIO_ENABLE_EP_IN
+      uint8_t ep_in = 0;
+      uint16_t ep_in_size = 0;
+#endif
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+      uint8_t ep_out = 0;
+      uint16_t ep_out_size = 0;
+#endif
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+      uint8_t ep_fb = 0;
+#endif
+
+      // First find EP addr
+      uint8_t const *p_desc = _audiod_fct[i].p_desc;
+      uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
+      while (p_desc < p_desc_end)
+      {
+        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
+        {
+          tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+          if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
+          {
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+            // Explicit feedback EP
+            if (desc_ep->bmAttributes.usage == 1)
+            {
+              ep_fb = desc_ep->bEndpointAddress;
+            }
+#endif      
+            // Data EP
+            if (desc_ep->bmAttributes.usage == 0)
+            {
+              if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
+              {
+#if CFG_TUD_AUDIO_ENABLE_EP_IN
+                ep_in = desc_ep->bEndpointAddress;
+#endif
+              } else
+              {
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+                ep_out = desc_ep->bEndpointAddress;
+#endif
+              }
+            }
+            
+          }
+        }
+        p_desc = tu_desc_next(p_desc);
+      }
+
+      // Then find EP max size
+      p_desc = _audiod_fct[i].p_desc;
+      while (p_desc < p_desc_end)
+      {
+        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
+        {
+          tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+          if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
+          {
+#if CFG_TUD_AUDIO_ENABLE_EP_IN
+            if (desc_ep->bEndpointAddress == ep_in)
+            {
+              ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
+            }
+#endif
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+            if (desc_ep->bEndpointAddress == ep_out)
+            {
+              ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size);
+            }
+#endif
+          }
+        }
+        p_desc = tu_desc_next(p_desc);
+      }
+
+#if CFG_TUD_AUDIO_ENABLE_EP_IN
+      if (ep_in)
+      {
+        usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size);
+      }
+#endif
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+      if (ep_out)
+      {
+        usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size);
+      }
+#endif
+#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+      if (ep_fb)
+      {
+        usbd_edpt_iso_alloc(rhport, ep_fb, 4);
+      }
+#endif
+
+#endif
+
       break;
     }
   }
@@ -1528,8 +1638,9 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   if (audio->ep_in_as_intf_num == itf)
   {
     audio->ep_in_as_intf_num = 0;
+#if !USE_ISO_EP_ALLOCATION
     usbd_edpt_close(rhport, audio->ep_in);
-
+#endif
     // Clear FIFOs, since data is no longer valid
 #if !CFG_TUD_AUDIO_ENABLE_ENCODING
     tu_fifo_clear(&audio->ep_in_ff);
@@ -1552,8 +1663,9 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   if (audio->ep_out_as_intf_num == itf)
   {
     audio->ep_out_as_intf_num = 0;
+#if !USE_ISO_EP_ALLOCATION
     usbd_edpt_close(rhport, audio->ep_out);
-
+#endif
     // Clear FIFOs, since data is no longer valid
 #if !CFG_TUD_AUDIO_ENABLE_DECODING
     tu_fifo_clear(&audio->ep_out_ff);
@@ -1571,7 +1683,9 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
     // Close corresponding feedback EP
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+#if !USE_ISO_EP_ALLOCATION
     usbd_edpt_close(rhport, audio->ep_fb);
+#endif
     audio->ep_fb = 0;
     tu_memclr(&audio->feedback, sizeof(audio->feedback));
 #endif
@@ -1601,8 +1715,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
         if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
         {
           tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+#if USE_ISO_EP_ALLOCATION
+          TU_ASSERT(usbd_edpt_iso_activate(rhport, desc_ep));
+#else
           TU_ASSERT(usbd_edpt_open(rhport, desc_ep));
-
+#endif
           uint8_t const ep_addr = desc_ep->bEndpointAddress;
 
           //TODO: We need to set EP non busy since this is not taken care of right now in ep_close() - THIS IS A WORKAROUND!
diff --git a/src/device/usbd.c b/src/device/usbd.c
index ea9ab91b6..fd4414559 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1396,11 +1396,19 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep
 {
   rhport = _usbd_rhport;
 
-  TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX);
+  uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress);
+  uint8_t const dir   = tu_edpt_dir(desc_ep->bEndpointAddress);
+  
+  TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX);
   TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
-
+  
   if (dcd_edpt_iso_activate)
+  {
+    _usbd_dev.ep_status[epnum][dir].stalled = false;
+    _usbd_dev.ep_status[epnum][dir].busy = false;
+    _usbd_dev.ep_status[epnum][dir].claimed = false;
     return dcd_edpt_iso_activate(rhport, desc_ep);
+  }
   else
     return false;
 }
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index d462fc649..a428d546d 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -812,6 +812,13 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
 
   for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++)
   {
+    // Check if already allocated
+    if(ep_alloc_status[i].allocated[dir] &&
+       ep_alloc_status[i].ep_type == ep_type &&
+       ep_alloc_status[i].ep_num == epnum)
+    {
+      return i;
+    }
     // If EP of current direction is not allocated
     // Except for ISO endpoint, both direction should be free
     if(!ep_alloc_status[i].allocated[dir] &&
@@ -971,7 +978,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 
   if(dir == TUSB_DIR_IN)
   {
-    pcd_set_ep_tx_status(USB,epnum, USB_EP_TX_DIS);
+    pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS);
   }
   else
   {
@@ -994,10 +1001,15 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
 
   /* Create a packet memory buffer area. For isochronous endpoints,
    * use the same buffer as the double buffer, essentially disabling double buffering */
-  dcd_pma_alloc(ep_addr, buffer_size);
+  uint16_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size);
 
   xfer_ctl_ptr(ep_addr)->epnum = epnum;
 
+  pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS);
+  
+  *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
+  *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
+  
   return true;
 }
 
@@ -1005,25 +1017,26 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
 {
   (void)rhport;
   uint8_t const epnum = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum;
-  const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
-  uint16_t pma_addr;
+  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  const uint16_t packet_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc));
 
   /* Disable endpoint */
-  pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS);
-  pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS);
-
-  pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS);
+  if(dir == TUSB_DIR_IN)
+  {
+    pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS);
+  }
+  else
+  {
+    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS);
+  }
+  
   pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
   // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
   // or being double-buffered (bulk endpoints)
   pcd_clear_ep_kind(USB,0);
 
-  pma_addr = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->pma_ptr;
-
-  *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
   pcd_clear_tx_dtog(USB, epnum);
 
-  *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
   pcd_set_ep_rx_bufsize(USB, epnum, packet_size);
   pcd_clear_rx_dtog(USB, epnum);
 

From 7ff2f43bfd9a9dd36b3c3aadcd0362db509b367c Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Fri, 30 Dec 2022 15:09:50 +0100
Subject: [PATCH 1364/2085] Add multi-rate audio test example for new ISO
 buffer allocation.

---
 examples/device/CMakeLists.txt                |   1 +
 .../audio_test_multi_rate/CMakeLists.txt      |  28 +
 .../device/audio_test_multi_rate/Makefile     |  12 +
 .../device/audio_test_multi_rate/skip.txt     |   3 +
 .../device/audio_test_multi_rate/src/main.c   | 521 ++++++++++++++++++
 .../src/plot_audio_samples.py                 |  38 ++
 .../audio_test_multi_rate/src/tusb_config.h   | 141 +++++
 .../src/usb_descriptors.c                     | 169 ++++++
 .../src/usb_descriptors.h                     | 102 ++++
 9 files changed, 1015 insertions(+)
 create mode 100644 examples/device/audio_test_multi_rate/CMakeLists.txt
 create mode 100644 examples/device/audio_test_multi_rate/Makefile
 create mode 100644 examples/device/audio_test_multi_rate/skip.txt
 create mode 100644 examples/device/audio_test_multi_rate/src/main.c
 create mode 100644 examples/device/audio_test_multi_rate/src/plot_audio_samples.py
 create mode 100644 examples/device/audio_test_multi_rate/src/tusb_config.h
 create mode 100644 examples/device/audio_test_multi_rate/src/usb_descriptors.c
 create mode 100644 examples/device/audio_test_multi_rate/src/usb_descriptors.h

diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index edf5ab805..5520209e0 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -8,6 +8,7 @@ family_initialize_project(tinyusb_device_examples ${CMAKE_CURRENT_LIST_DIR})
 # family_add_subdirectory will filter what to actually add based on selected FAMILY
 family_add_subdirectory(audio_4_channel_mic)
 family_add_subdirectory(audio_test)
+family_add_subdirectory(audio_test_multi_rate)
 family_add_subdirectory(board_test)
 family_add_subdirectory(cdc_dual_ports)
 family_add_subdirectory(cdc_msc)
diff --git a/examples/device/audio_test_multi_rate/CMakeLists.txt b/examples/device/audio_test_multi_rate/CMakeLists.txt
new file mode 100644
index 000000000..cb321f9a8
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/CMakeLists.txt
@@ -0,0 +1,28 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+)
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+)
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
\ No newline at end of file
diff --git a/examples/device/audio_test_multi_rate/Makefile b/examples/device/audio_test_multi_rate/Makefile
new file mode 100644
index 000000000..5a455078e
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/Makefile
@@ -0,0 +1,12 @@
+include ../../../tools/top.mk
+include ../../make.mk
+
+INC += \
+  src \
+  $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../rules.mk
diff --git a/examples/device/audio_test_multi_rate/skip.txt b/examples/device/audio_test_multi_rate/skip.txt
new file mode 100644
index 000000000..ae9b57f1f
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/skip.txt
@@ -0,0 +1,3 @@
+mcu:SAMD11
+mcu:SAME5X
+mcu:SAMG
\ No newline at end of file
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
new file mode 100644
index 000000000..e4d2d0253
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -0,0 +1,521 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Reinhard Panhuber
+ * Copyright (c) 2022 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+/* plot_audio_samples.py requires following modules:
+ * $ sudo apt install libportaudio
+ * $ pip3 install sounddevice matplotlib
+ *
+ * Then run
+ * $ python3 plot_audio_samples.py
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+bool mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; 				          // +1 for master channel 0
+uint16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; 					// +1 for master channel 0
+uint32_t sampFreq;
+uint8_t bytesPerSample;
+uint8_t clkValid;
+
+// Range states
+// List of supported sample rates
+static const uint32_t sampleRatesList[] =
+{
+    32000, 48000, 96000
+};
+
+#define N_sampleRates  TU_ARRAY_SIZE(sampleRatesList)
+
+// Bytes per format of every Alt settings
+static const uint8_t bytesPerSampleAltList[CFG_TUD_AUDIO_FUNC_1_N_FORMATS] =
+{
+    CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX,
+    CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX,
+};
+
+audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; 			// Volume range state
+
+
+// Audio test data
+CFG_TUSB_MEM_ALIGN uint8_t test_buffer_audio[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
+uint16_t startVal = 0;
+
+void led_blinking_task(void);
+void audio_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
+
+  // Init values
+  sampFreq = sampleRatesList[0];
+  clkValid = 1;
+
+  while (1)
+  {
+    tud_task(); // tinyusb device task
+    led_blinking_task();
+    audio_task();
+  }
+
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+  (void) remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+//--------------------------------------------------------------------+
+// AUDIO Task
+//--------------------------------------------------------------------+
+
+void audio_task(void)
+{
+  // Yet to be filled - e.g. put meas data into TX FIFOs etc.
+  // asm("nop");
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Invoked when set interface is called, typically on start/stop streaming or format change
+bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void)rhport;
+  //uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+  uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+  
+  // Clear buffer when streaming format is changed
+  if(alt != 0)
+  {
+    bytesPerSample = bytesPerSampleAltList[alt-1];
+  }
+  return true;
+}
+
+// Invoked when audio class specific set request received for an EP
+bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+  (void) pBuff;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) ep;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an interface
+bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+  (void) pBuff;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) itf;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+  uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+  (void) itf;
+
+  // We do not support any set range requests here, only current value requests
+  TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
+
+  // If request is for our feature unit
+  if ( entityID == UAC2_ENTITY_FEATURE_UNIT )
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_FU_CTRL_MUTE:
+        // Request uses format layout 1
+        TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_1_t));
+
+        mute[channelNum] = ((audio_control_cur_1_t*) pBuff)->bCur;
+
+        TU_LOG2("    Set Mute: %d of channel: %u\r\n", mute[channelNum], channelNum);
+      return true;
+
+      case AUDIO_FU_CTRL_VOLUME:
+        // Request uses format layout 2
+        TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_2_t));
+
+        volume[channelNum] = (uint16_t) ((audio_control_cur_2_t*) pBuff)->bCur;
+
+        TU_LOG2("    Set Volume: %d dB of channel: %u\r\n", volume[channelNum], channelNum);
+      return true;
+
+        // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+      return false;
+    }
+  }
+  
+  // Clock Source unit
+  if ( entityID == UAC2_ENTITY_CLOCK )
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_CS_CTRL_SAM_FREQ:
+        TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_4_t));
+
+        sampFreq = ((audio_control_cur_4_t *)pBuff)->bCur;
+
+        TU_LOG2("Clock set current freq: %d\r\n", sampFreq);
+
+        return true;
+      break;
+
+      // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+  
+  return false;    // Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an EP
+bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t ep = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) ep;
+
+  //	return tud_control_xfer(rhport, p_request, &tmp, 1);
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an interface
+bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  uint8_t itf = TU_U16_LOW(p_request->wIndex);
+
+  (void) channelNum; (void) ctrlSel; (void) itf;
+
+  return false; 	// Yet not implemented
+}
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+
+  // Page 91 in UAC2 specification
+  uint8_t channelNum = TU_U16_LOW(p_request->wValue);
+  uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+  // uint8_t itf = TU_U16_LOW(p_request->wIndex); 			// Since we have only one audio function implemented, we do not need the itf value
+  uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+
+  // Input terminal (Microphone input)
+  if (entityID == UAC2_ENTITY_INPUT_TERMINAL)
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_TE_CTRL_CONNECTOR:
+      {
+        // The terminal connector control only has a get request with only the CUR attribute.
+        audio_desc_channel_cluster_t ret;
+
+        // Those are dummy values for now
+        ret.bNrChannels = 1;
+        ret.bmChannelConfig = 0;
+        ret.iChannelNames = 0;
+
+        TU_LOG2("    Get terminal connector\r\n");
+
+        return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+      }
+      break;
+
+        // Unknown/Unsupported control selector
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  // Feature unit
+  if (entityID == UAC2_ENTITY_FEATURE_UNIT)
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_FU_CTRL_MUTE:
+        // Audio control mute cur parameter block consists of only one byte - we thus can send it right away
+        // There does not exist a range parameter block for mute
+        TU_LOG2("    Get Mute of channel: %u\r\n", channelNum);
+        return tud_control_xfer(rhport, p_request, &mute[channelNum], 1);
+
+      case AUDIO_FU_CTRL_VOLUME:
+        switch ( p_request->bRequest )
+        {
+          case AUDIO_CS_REQ_CUR:
+            TU_LOG2("    Get Volume of channel: %u\r\n", channelNum);
+            return tud_control_xfer(rhport, p_request, &volume[channelNum], sizeof(volume[channelNum]));
+
+          case AUDIO_CS_REQ_RANGE:
+            TU_LOG2("    Get Volume range of channel: %u\r\n", channelNum);
+
+            // Copy values - only for testing - better is version below
+            audio_control_range_2_n_t(1)
+            ret;
+
+            ret.wNumSubRanges = 1;
+            ret.subrange[0].bMin = -90;    // -90 dB
+            ret.subrange[0].bMax = 30;		// +30 dB
+            ret.subrange[0].bRes = 1; 		// 1 dB steps
+
+            return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
+
+            // Unknown/Unsupported control
+          default:
+            TU_BREAKPOINT();
+            return false;
+        }
+      break;
+
+        // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  // Clock Source unit
+  if ( entityID == UAC2_ENTITY_CLOCK )
+  {
+    switch ( ctrlSel )
+    {
+      case AUDIO_CS_CTRL_SAM_FREQ:
+        // channelNum is always zero in this case
+        switch ( p_request->bRequest )
+        {
+          case AUDIO_CS_REQ_CUR:
+            TU_LOG2("    Get Sample Freq.\r\n");
+            return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+
+          case AUDIO_CS_REQ_RANGE:
+          {
+            TU_LOG2("    Get Sample Freq. range\r\n");
+            audio_control_range_4_n_t(N_sampleRates) rangef =
+            {
+                .wNumSubRanges = tu_htole16(N_sampleRates)
+            };
+            TU_LOG1("Clock get %d freq ranges\r\n", N_sampleRates);
+            for(uint8_t i = 0; i < N_sampleRates; i++)
+            {
+                rangef.subrange[i].bMin = sampleRatesList[i];
+                rangef.subrange[i].bMax = sampleRatesList[i];
+                rangef.subrange[i].bRes = 0;
+                TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
+            }
+            return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, &rangef, sizeof(rangef));
+          }
+           // Unknown/Unsupported control
+          default:
+            TU_BREAKPOINT();
+            return false;
+        }
+      break;
+
+      case AUDIO_CS_CTRL_CLK_VALID:
+        // Only cur attribute exists for this request
+        TU_LOG2("    Get Sample Freq. valid\r\n");
+        return tud_control_xfer(rhport, p_request, &clkValid, sizeof(clkValid));
+
+      // Unknown/Unsupported control
+      default:
+        TU_BREAKPOINT();
+        return false;
+    }
+  }
+
+  TU_LOG2("  Unsupported entity: %d\r\n", entityID);
+  return false; 	// Yet not implemented
+}
+
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+  (void) rhport;
+  (void) itf;
+  (void) ep_in;
+  (void) cur_alt_setting;
+
+  tud_audio_write ((uint8_t *)test_buffer_audio, sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000) * bytesPerSample);
+
+  return true;
+}
+
+bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+  (void) rhport;
+  (void) n_bytes_copied;
+  (void) itf;
+  (void) ep_in;
+  (void) cur_alt_setting;
+
+  // 16bit
+  if(bytesPerSample == 2)
+  {
+    uint16_t* pData_16 = (uint16_t*)test_buffer_audio;
+    for (size_t cnt = 0; cnt < sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000); cnt++)
+    {
+      pData_16[cnt] = startVal++;
+    }
+  }
+  // 24bit in 32bit slot
+  else if(bytesPerSample == 4)
+  {
+    uint32_t* pData_32 = (uint32_t*)test_buffer_audio;
+    for (size_t cnt = 0; cnt < sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000); cnt++)
+    {
+      pData_32[cnt] = (uint32_t)startVal++ << 16U;
+    }
+  }
+  
+  return true;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void) rhport;
+  (void) p_request;
+  startVal = 0;
+
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
new file mode 100644
index 000000000..4a5f15a9c
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
@@ -0,0 +1,38 @@
+import sounddevice as sd
+import matplotlib.pyplot as plt
+import numpy as np
+import platform
+import csv
+
+if __name__ == '__main__':
+
+    # If you got "ValueError: No input device matching", that is because your PC name example device
+    # differently from tested list below. Uncomment the next line to see full list and try to pick correct one
+    # print(sd.query_devices())
+
+    fs = 96000           # Sample rate
+    duration = 100e-3    # Duration of recording
+
+    if platform.system() == 'Windows':
+        # MME is needed since there are more than one MicNode device APIs (at least in Windows)
+        device = 'Microphone (MicNode) MME'
+    elif platform.system() == 'Darwin':
+        device = 'MicNode'
+    else:
+        device ='default'
+
+    myrecording = sd.rec(int(duration * fs), samplerate=fs, channels=1, dtype='int16', device=device)
+    print('Waiting...')
+    sd.wait()  # Wait until recording is finished
+    print('Done!')
+
+    time = np.arange(0, duration, 1 / fs)  # time vector
+    plt.plot(time, myrecording)
+    plt.xlabel('Time [s]')
+    plt.ylabel('Amplitude')
+    plt.title('MicNode')
+    plt.show()
+    
+    samples = np.array(myrecording)
+    np.savetxt('Output.csv', samples, delimiter=",", fmt='%s')
+    
\ No newline at end of file
diff --git a/examples/device/audio_test_multi_rate/src/tusb_config.h b/examples/device/audio_test_multi_rate/src/tusb_config.h
new file mode 100644
index 000000000..d8b6511d6
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/tusb_config.h
@@ -0,0 +1,141 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS                 OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG              0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_AUDIO             1
+#define CFG_TUD_CDC               0
+#define CFG_TUD_MSC               0
+#define CFG_TUD_HID               0
+#define CFG_TUD_MIDI              0
+#define CFG_TUD_VENDOR            0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000
+
+// How many formats are used, need to adjust USB descriptor if changed
+#define CFG_TUD_AUDIO_FUNC_1_N_FORMATS                               2
+  
+// 16bit in 16bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX          2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX                  16
+
+// 24bit in 32bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX          4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX                  24
+
+// Have a look into audio_device.h for all configurations
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                 TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESC_LEN
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT                                 1                                       // Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ                              64                                      // Size of control request buffer
+
+#define CFG_TUD_AUDIO_ENABLE_EP_IN                                    1
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                            1                                       // Driver gets this info from the descriptors - we define it here to use it to setup the descriptors and to do calculations with it below - be aware: for different number of channels you need another descriptor!
+
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX                             TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN)                  // Maximum EP IN size for all AS alternate settings used
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ                          CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.c b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
new file mode 100644
index 000000000..92e791a72
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
@@ -0,0 +1,169 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2022 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]     AUDIO | MIDI | HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+    _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = 0x0200,
+
+    // Use Interface Association Descriptor (IAD) for CDC
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = 0xCafe,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+  return (uint8_t const *) &desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+enum
+{
+  ITF_NUM_AUDIO_CONTROL = 0,
+  ITF_NUM_AUDIO_STREAMING,
+  ITF_NUM_TOTAL
+};
+
+#define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_AUDIO   0x03
+
+#elif TU_CHECK_MCU(OPT_MCU_NRF5X)
+  // nRF5x ISO can only be endpoint 8
+  #define EPNUM_AUDIO   0x08
+
+#else
+  #define EPNUM_AUDIO   0x01
+#endif
+
+uint8_t const desc_configuration[] =
+{
+    // Interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESCRIPTOR(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_stridx*/ 0, /*_epin*/ 0x80 | EPNUM_AUDIO)
+};
+
+TU_VERIFY_STATIC(sizeof(desc_configuration) == CONFIG_TOTAL_LEN, "Incorrect size");
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+  (void) index; // for multiple configurations
+  return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] =
+{
+    (const char[]) { 0x09, 0x04 }, 	// 0: is supported language is English (0x0409)
+    "PaniRCorp",                   	// 1: Manufacturer
+    "MicNode",              		// 2: Product
+    "123456",                      	// 3: Serials, should use chip ID
+    "UAC2",                 	 	// 4: Audio Interface
+};
+
+static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
+{
+  (void) langid;
+
+  uint8_t chr_count;
+
+  if ( index == 0)
+  {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  }else
+  {
+    // Convert ASCII string into UTF-16
+
+    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+
+    const char* str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = (uint8_t) strlen(str);
+    if ( chr_count > 31 ) chr_count = 31;
+
+    for(uint8_t i=0; i<chr_count; i++)
+    {
+      _desc_str[1+i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.h b/examples/device/audio_test_multi_rate/src/usb_descriptors.h
new file mode 100644
index 000000000..77e2fe6c1
--- /dev/null
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.h
@@ -0,0 +1,102 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _USB_DESCRIPTORS_H_
+#define _USB_DESCRIPTORS_H_
+
+// #include "tusb.h"
+
+// Unit numbers are arbitrary selected
+#define UAC2_ENTITY_CLOCK                   0x04
+#define UAC2_ENTITY_INPUT_TERMINAL          0x01
+#define UAC2_ENTITY_OUTPUT_TERMINAL         0x03
+#define UAC2_ENTITY_FEATURE_UNIT            0x02
+
+
+#define TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+    + TUD_AUDIO_DESC_STD_AC_LEN\
+    + TUD_AUDIO_DESC_CS_AC_LEN\
+    + TUD_AUDIO_DESC_CLK_SRC_LEN\
+    + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    /* Interface 1, Alternate 1 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 1, Alternate 2 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
+
+
+#define TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESCRIPTOR(_itfnum, _stridx, _epin) \
+  /* Standard Interface Association Descriptor (IAD) */\
+  TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+  /* Standard AC Interface Descriptor(4.7.1) */\
+  TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+  /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+  TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_MICROPHONE, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+  /* Clock Source Descriptor(4.7.2.1) */\
+  TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ UAC2_ENTITY_CLOCK, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_PRO_CLK, /*_ctrl*/ AUDIO_CTRL_RW << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS | AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_VAL_POS, /*_assocTerm*/ 0x01,  /*_stridx*/ 0x00),\
+  /* Input Terminal Descriptor(4.7.2.4) */\
+  TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS, /*_stridx*/ 0x00),\
+  /* Output Terminal Descriptor(4.7.2.5) */\
+  TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ UAC2_ENTITY_INPUT_TERMINAL, /*_srcid*/ UAC2_ENTITY_FEATURE_UNIT, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+  /* Feature Unit Descriptor(4.7.2.8) */\
+  TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ UAC2_ENTITY_FEATURE_UNIT, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00),\
+  /* Standard AS Interface Descriptor(4.9.1) */\
+  /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+  TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\
+  /* Standard AS Interface Descriptor(4.9.1) */\
+  /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+  TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x00),\
+  /* Class-Specific AS Interface Descriptor(4.9.2) */\
+  TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+  /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+  TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
+  /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, /*_interval*/ 0x01),\
+  /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+  TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
+  /* Interface 1, Alternate 2 - alternate interface for data streaming */\
+  TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x00),\
+  /* Class-Specific AS Interface Descriptor(4.9.2) */\
+  TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+  /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+  TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
+  /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN, /*_interval*/ 0x01),\
+  /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+  TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
+
+
+#endif
\ No newline at end of file

From fc32280f42e03ef78e8d43bb9e8382ad4c9b19c0 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Fri, 30 Dec 2022 15:10:00 +0100
Subject: [PATCH 1365/2085] Fix buffer allocation overflow.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index a428d546d..702b32f9c 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -167,8 +167,8 @@ typedef struct
   uint16_t total_len;
   uint16_t queued_len;
   uint16_t pma_ptr;
-  uint8_t max_packet_size;
-  uint8_t pma_alloc_size;
+  uint16_t max_packet_size;
+  uint16_t pma_alloc_size;
   uint8_t epnum;
 } xfer_ctl_t;
 

From 35fa6b660a09ea1b56cfd02e32dbd0e8dd6374fc Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Fri, 30 Dec 2022 15:18:31 +0100
Subject: [PATCH 1366/2085] Fix CI.

---
 examples/device/audio_test_multi_rate/src/main.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
index e4d2d0253..0e11a509b 100644
--- a/examples/device/audio_test_multi_rate/src/main.c
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -266,7 +266,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
       case AUDIO_CS_CTRL_SAM_FREQ:
         TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_4_t));
 
-        sampFreq = ((audio_control_cur_4_t *)pBuff)->bCur;
+        sampFreq = (uint32_t)((audio_control_cur_4_t *)pBuff)->bCur;
 
         TU_LOG2("Clock set current freq: %d\r\n", sampFreq);
 
@@ -423,8 +423,8 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
             TU_LOG1("Clock get %d freq ranges\r\n", N_sampleRates);
             for(uint8_t i = 0; i < N_sampleRates; i++)
             {
-                rangef.subrange[i].bMin = sampleRatesList[i];
-                rangef.subrange[i].bMax = sampleRatesList[i];
+                rangef.subrange[i].bMin = (int32_t)sampleRatesList[i];
+                rangef.subrange[i].bMax = (int32_t)sampleRatesList[i];
                 rangef.subrange[i].bRes = 0;
                 TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
             }
@@ -460,7 +460,7 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
   (void) ep_in;
   (void) cur_alt_setting;
 
-  tud_audio_write ((uint8_t *)test_buffer_audio, sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000) * bytesPerSample);
+  tud_audio_write((uint8_t *)test_buffer_audio, (uint16_t)(sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000) * bytesPerSample));
 
   return true;
 }
@@ -476,7 +476,7 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin
   // 16bit
   if(bytesPerSample == 2)
   {
-    uint16_t* pData_16 = (uint16_t*)test_buffer_audio;
+    uint16_t* pData_16 = (uint16_t*)((void*)test_buffer_audio);
     for (size_t cnt = 0; cnt < sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000); cnt++)
     {
       pData_16[cnt] = startVal++;
@@ -485,7 +485,7 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin
   // 24bit in 32bit slot
   else if(bytesPerSample == 4)
   {
-    uint32_t* pData_32 = (uint32_t*)test_buffer_audio;
+    uint32_t* pData_32 = (uint32_t*)((void*)test_buffer_audio);
     for (size_t cnt = 0; cnt < sampFreq / (TUD_OPT_HIGH_SPEED ? 8000 : 1000); cnt++)
     {
       pData_32[cnt] = (uint32_t)startVal++ << 16U;

From 51bb27a131ca57f8f7c7c971024f90e77b81d11a Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Sat, 31 Dec 2022 13:37:22 +0100
Subject: [PATCH 1367/2085] Optimize descriptor looping.

---
 src/class/audio/audio_device.c | 50 ++++++++++++++--------------------
 1 file changed, 20 insertions(+), 30 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index a8a2439bc..31c4783eb 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -106,13 +106,28 @@
 #define  USE_LINEAR_BUFFER     1
 #endif
 
+#if defined(STM32F102x6) || defined(STM32F102xB) || \
+    defined(STM32F103x6) || defined(STM32F103xB) || \
+    defined(STM32F103xE) || defined(STM32F103xG)
+#define STM32F1_FSDEV
+#endif
+
+#if defined(STM32L412xx) || defined(STM32L422xx) || \
+    defined(STM32L432xx) || defined(STM32L433xx) || \
+    defined(STM32L442xx) || defined(STM32L443xx) || \
+    defined(STM32L452xx) || defined(STM32L462xx)
+#define STM32L4_FSDEV
+#endif
+
 // Temporarily put the check here for stm32_fsdev
 #if CFG_TUSB_MCU == OPT_MCU_STM32F0                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32F3                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32L0                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32L1                               || \
     CFG_TUSB_MCU == OPT_MCU_STM32G4                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32WB
+    CFG_TUSB_MCU == OPT_MCU_STM32WB                               || \
+    (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV))     || \
+    (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV))
 #define  USE_ISO_EP_ALLOCATION   1
 #else
 #define  USE_ISO_EP_ALLOCATION   0
@@ -1481,18 +1496,17 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
 
 #if USE_ISO_EP_ALLOCATION
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
-      uint8_t ep_in = 0;
+      uint8_t  ep_in = 0;
       uint16_t ep_in_size = 0;
 #endif
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-      uint8_t ep_out = 0;
+      uint8_t  ep_out = 0;
       uint16_t ep_out_size = 0;
 #endif
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
       uint8_t ep_fb = 0;
 #endif
 
-      // First find EP addr
       uint8_t const *p_desc = _audiod_fct[i].p_desc;
       uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
       while (p_desc < p_desc_end)
@@ -1516,11 +1530,13 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
               {
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
                 ep_in = desc_ep->bEndpointAddress;
+                ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
 #endif
               } else
               {
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
                 ep_out = desc_ep->bEndpointAddress;
+                ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size);
 #endif
               }
             }
@@ -1530,32 +1546,6 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
         p_desc = tu_desc_next(p_desc);
       }
 
-      // Then find EP max size
-      p_desc = _audiod_fct[i].p_desc;
-      while (p_desc < p_desc_end)
-      {
-        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
-        {
-          tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-          if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
-          {
-#if CFG_TUD_AUDIO_ENABLE_EP_IN
-            if (desc_ep->bEndpointAddress == ep_in)
-            {
-              ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
-            }
-#endif
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
-            if (desc_ep->bEndpointAddress == ep_out)
-            {
-              ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size);
-            }
-#endif
-          }
-        }
-        p_desc = tu_desc_next(p_desc);
-      }
-
 #if CFG_TUD_AUDIO_ENABLE_EP_IN
       if (ep_in)
       {

From 7228239eb94f16281fe98ca3a612ba89995f7b47 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Mon, 2 Jan 2023 09:43:48 +0100
Subject: [PATCH 1368/2085] Clean up.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 382374614..ded13ae14 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -119,15 +119,6 @@
 // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
 static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
 
-// This array maps the endpoint address to a endpoint register in hardware
-// By default the tinyusb stack chooses the endpoint register using the endpoint number
-// However when using ISOCHRONOUS endpoints, the entire endpoint register (RX _and_ TX)
-// are used for a double buffer in a single direction. If you now want to use the same endpoint number with
-// different directions (e.g. 0x02 and 0x82), they would be mapped to the same register
-// In this case, this serves as a crude helper to overcome this limitation by implementing
-// this callback and defining a custom mapping in your application
-TU_ATTR_WEAK uint8_t tu_stm32_edpt_number_cb(uint8_t addr);
-
 // This callback is called on SOF and can be used to e.g. capture a timer value for timing purposes
 TU_ATTR_WEAK void tu_stm32_sof_cb(void);
 

From 69475cd1bf6c4937bd2bc6570f611a700022cdac Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Mon, 2 Jan 2023 12:06:26 +0100
Subject: [PATCH 1369/2085] Remove tu_stm32_sof_cb

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c        | 1 -
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 3 ---
 2 files changed, 4 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 702b32f9c..648e8f8d0 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -649,7 +649,6 @@ void dcd_int_handler(uint8_t rhport) {
   /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
   if(int_status & USB_ISTR_SOF) {
     clear_istr_bits(USB_ISTR_SOF);
-    if (tu_stm32_sof_cb) tu_stm32_sof_cb();
     dcd_event_sof(0, USB->FNR & USB_FNR_FN, true);
   }
 
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index ded13ae14..98cf008d4 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -119,9 +119,6 @@
 // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
 static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
 
-// This callback is called on SOF and can be used to e.g. capture a timer value for timing purposes
-TU_ATTR_WEAK void tu_stm32_sof_cb(void);
-
 // prototypes
 TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
 TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);

From 82f105e32b3b299509daa1dc24d6aa94f5ce63fb Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Mon, 2 Jan 2023 17:12:03 +0100
Subject: [PATCH 1370/2085] Fix IAR warning: Warning[Pe381]: extra ";" ignored

---
 src/class/usbtmc/usbtmc_device.c | 6 ++++--
 src/osal/osal.h                  | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 07c7c28a6..ba38bfca8 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -157,8 +157,10 @@ static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t pack
 static uint8_t termChar;
 static uint8_t termCharRequested = false;
 
-OSAL_MUTEX_DEF(usbtmcLockBuffer);
-static osal_mutex_t usbtmcLock;
+#if OSAL_MUTEX_REQUIRED
+static OSAL_MUTEX_DEF(usbtmcLockBuffer);
+#endif
+osal_mutex_t usbtmcLock;
 
 // Our own private lock, mostly for the state variable.
 #define criticalEnter() do { (void) osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0)
diff --git a/src/osal/osal.h b/src/osal/osal.h
index 9cdab2882..afa3826fc 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -44,7 +44,7 @@ typedef void (*osal_task_func_t)( void * );
 // Mutex is required when using a preempted RTOS or MCU has multiple cores
 #if (CFG_TUSB_OS == OPT_OS_NONE) && !TUP_MCU_MULTIPLE_CORE
   #define OSAL_MUTEX_REQUIRED   0
-  #define OSAL_MUTEX_DEF(_name)
+  #define OSAL_MUTEX_DEF(_name) uint8_t :0
 #else
   #define OSAL_MUTEX_REQUIRED   1
   #define OSAL_MUTEX_DEF(_name) osal_mutex_def_t _name

From f5cffeedec863c1efd59688fa79a8455046e8377 Mon Sep 17 00:00:00 2001
From: pete-pjb <petebone00@gmail.com>
Date: Tue, 3 Jan 2023 10:33:36 +0000
Subject: [PATCH 1371/2085] Fix typo in audio.h. Specifiy _ctrl_xfer struct in
 CFG_TUSB_MEM_SECTION

Add NULL check to loop in list_remove_qhd_by_addr() function in ehci.c
---
 src/class/audio/audio.h  | 2 ++
 src/host/usbh.c          | 8 ++++----
 src/portable/ehci/ehci.c | 2 +-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h
index 6f9c1a6b5..ba497906b 100644
--- a/src/class/audio/audio.h
+++ b/src/class/audio/audio.h
@@ -721,11 +721,13 @@ typedef struct TU_ATTR_PACKED
   uint8_t bLength            ; ///< Size of this descriptor, in bytes: 17.
   uint8_t bDescriptorType    ; ///< Descriptor Type. Value: TUSB_DESC_CS_INTERFACE.
   uint8_t bDescriptorSubType ; ///< Descriptor SubType. Value: AUDIO_CS_AC_INTERFACE_INPUT_TERMINAL.
+  uint8_t bTerminalID        ; ///< Constant uniquely identifying the Terminal within the audio function. This value is used in all requests to address this terminal.
   uint16_t wTerminalType     ; ///< Constant characterizing the type of Terminal. See: audio_terminal_type_t for USB streaming and audio_terminal_input_type_t for other input types.
   uint8_t bAssocTerminal     ; ///< ID of the Output Terminal to which this Input Terminal is associated.
   uint8_t bCSourceID         ; ///< ID of the Clock Entity to which this Input Terminal is connected.
   uint8_t bNrChannels        ; ///< Number of logical output channels in the Terminal’s output audio channel cluster.
   uint32_t bmChannelConfig   ; ///< Describes the spatial location of the logical channels. See:audio_channel_config_t.
+  uint8_t iChannelNames      ; ///< Index of a string descriptor, describing the name of the first logical channel.
   uint16_t bmControls        ; ///< See: audio_terminal_input_control_pos_t.
   uint8_t iTerminal          ; ///< Index of a string descriptor, describing the Input Terminal.
 } audio_desc_input_terminal_t;
diff --git a/src/host/usbh.c b/src/host/usbh.c
index af1e67d4d..5ac9e9cca 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -229,10 +229,10 @@ static osal_queue_t _usbh_q;
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
 static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
-// Control transfer: since most controller does not support multiple control transfer
-// on multiple devices concurrently. And control transfer is not used much except enumeration
-// We will only execute control transfer one at a time.
-struct
+// Control transfers: since most controllers do not support multiple control transfers
+// on multiple devices concurrently and control transfers are not used much except for
+// enumeration, we will only execute control transfers one at a time.
+CFG_TUSB_MEM_SECTION struct
 {
   tusb_control_request_t request TU_ATTR_ALIGNED(4);
   uint8_t* buffer;
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 80f616478..7140897a1 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -188,7 +188,7 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
 {
   for(ehci_link_t* prev = list_head;
-      !prev->terminate && (tu_align32(prev->address) != (uint32_t) list_head);
+      !prev->terminate && (tu_align32(prev->address) != (uint32_t) list_head) && prev != NULL;
       prev = list_next(prev) )
   {
     // TODO check type for ISO iTD and siTD

From 8c591e2c45f80f41d2704ae3b3ce5bde8550ecb9 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 4 Jan 2023 10:19:34 +0100
Subject: [PATCH 1372/2085] More warning fixes

---
 src/class/usbtmc/usbtmc_device.c | 71 +++++++++++++++-----------------
 1 file changed, 33 insertions(+), 38 deletions(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index ba38bfca8..0cf0743a7 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -364,7 +364,7 @@ bool tud_usbtmc_start_bus_read()
   case STATE_RCV:
     break;
   default:
-    TU_VERIFY(false);
+    return false;
   }
   TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_state.ep_bulk_out_buf, (uint16_t)usbtmc_state.ep_bulk_out_wMaxPacketSize));
   return true;
@@ -466,53 +466,52 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
     switch(usbtmc_state.state)
     {
     case STATE_IDLE:
-      TU_VERIFY(xferred_bytes >= sizeof(usbtmc_msg_generic_t));
-      msg = (usbtmc_msg_generic_t*)(usbtmc_state.ep_bulk_out_buf);
-      uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse);
-      TU_VERIFY(msg->header.bTag == invInvTag);
-      TU_VERIFY(msg->header.bTag != 0x00);
+      {
+        TU_VERIFY(xferred_bytes >= sizeof(usbtmc_msg_generic_t));
+        msg = (usbtmc_msg_generic_t*)(usbtmc_state.ep_bulk_out_buf);
+        uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse);
+        TU_VERIFY(msg->header.bTag == invInvTag);
+        TU_VERIFY(msg->header.bTag != 0x00);
 
-      switch(msg->header.MsgID) {
-      case USBTMC_MSGID_DEV_DEP_MSG_OUT:
-        if(!handle_devMsgOutStart(rhport, msg, xferred_bytes))
-        {
-          usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
-          TU_VERIFY(false);
-        }
-        break;
+        switch(msg->header.MsgID) {
+        case USBTMC_MSGID_DEV_DEP_MSG_OUT:
+          if(!handle_devMsgOutStart(rhport, msg, xferred_bytes))
+          {
+            usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
+            return false;
+          }
+          break;
 
-      case USBTMC_MSGID_DEV_DEP_MSG_IN:
-        TU_VERIFY(handle_devMsgIn(msg, xferred_bytes));
-        break;
+        case USBTMC_MSGID_DEV_DEP_MSG_IN:
+          TU_VERIFY(handle_devMsgIn(msg, xferred_bytes));
+          break;
 
 #if (CFG_TUD_USBTMC_ENABLE_488)
-      case USBTMC_MSGID_USB488_TRIGGER:
-        // Spec says we halt the EP if we didn't declare we support it.
-        TU_VERIFY(usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger);
-        TU_VERIFY(tud_usbtmc_msg_trigger_cb(msg));
+        case USBTMC_MSGID_USB488_TRIGGER:
+          // Spec says we halt the EP if we didn't declare we support it.
+          TU_VERIFY(usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger);
+          TU_VERIFY(tud_usbtmc_msg_trigger_cb(msg));
 
-        break;
+          break;
 #endif
-      case USBTMC_MSGID_VENDOR_SPECIFIC_MSG_OUT:
-      case USBTMC_MSGID_VENDOR_SPECIFIC_IN:
-      default:
-        usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
-        TU_VERIFY(false);
-        return false;
+        case USBTMC_MSGID_VENDOR_SPECIFIC_MSG_OUT:
+        case USBTMC_MSGID_VENDOR_SPECIFIC_IN:
+        default:
+          usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
+          return false;
+        }
+        return true;
       }
-      return true;
-
     case STATE_RCV:
       if(!handle_devMsgOut(rhport, usbtmc_state.ep_bulk_out_buf, xferred_bytes, xferred_bytes))
       {
         usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out);
-        TU_VERIFY(false);
+        return false;
       }
       return true;
 
     case STATE_ABORTING_BULK_OUT:
-      TU_VERIFY(false);
-      return false; // Should be stalled by now, shouldn't have received a packet.
+      return false;
 
     case STATE_TX_REQUESTED:
     case STATE_TX_INITIATED:
@@ -520,7 +519,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
     case STATE_ABORTING_BULK_IN_SHORTED:
     case STATE_ABORTING_BULK_IN_ABORTED:
     default:
-      TU_VERIFY(false);
+      return false;
     }
   }
   else if(ep_addr == usbtmc_state.ep_bulk_in)
@@ -569,7 +568,6 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
 
     default:
       TU_ASSERT(false);
-      return false;
     }
   }
   else if (ep_addr == usbtmc_state.ep_int_in) {
@@ -873,16 +871,13 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
   case USB488_bREQUEST_LOCAL_LOCKOUT:
     {
       TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface
-      TU_VERIFY(false);
       return false;
     }
 #endif
 
   default:
-    TU_VERIFY(false);
     return false;
   }
-  TU_VERIFY(false);
 }
 
 #endif /* CFG_TUD_TSMC */

From d6b612257ed1026cccd18c620d3d6cb51d5b2cb2 Mon Sep 17 00:00:00 2001
From: Simon Kueppers <simon.kueppers@skueppers.de>
Date: Thu, 5 Jan 2023 14:39:23 +0100
Subject: [PATCH 1373/2085] Fixed bug where with some devices, the TU_ASSERT
 inserted with this commit gets triggered for ISOCHRONOUS endpoints. It is
 necessary for those endpoints to set the NUM_BLOCK and BLSIZE for the
 receiving buffer in both, USB_COUNTn_TX and USB_COUNTn_RX. Despite the
 datasheet showing those fields only for the USB_COUNTn_RX register

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c     | 15 ++++++++++++---
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h       |  9 +++++++++
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 648e8f8d0..fdcb2c48d 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -562,6 +562,8 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
       count = pcd_get_ep_rx_cnt(USB, EPindex);
     }
 
+    TU_ASSERT(count <= xfer->max_packet_size, /**/);
+
     // Clear RX CTR interrupt flag
     if(ep_addr != 0u)
     {
@@ -599,7 +601,12 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
       } else {
         pcd_set_ep_rx_bufsize(USB, EPindex,remaining);
       }
-      pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
+
+      if (!((wEPRegVal & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS)) {
+        /* Set endpoint active again for receiving more data.
+         * Note that isochronous endpoints stay active always */
+        pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
+      }
     }
   }
 
@@ -881,7 +888,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   (void)rhport;
   uint8_t const epnum = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer);
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  const uint16_t buffer_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc));
+  const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
+  const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size);
   uint16_t pma_addr;
   uint32_t wType;
 
@@ -921,6 +929,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
   if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) )
   {
     *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
+    pcd_set_ep_tx_bufsize(USB, epnum, buffer_size);
     pcd_clear_tx_dtog(USB, epnum);
   }
 
@@ -948,7 +957,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
     }
   }
 
-  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = buffer_size;
+  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size;
   xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum = epnum;
 
   return true;
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 98cf008d4..f4966907a 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -281,6 +281,13 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx,
   *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
+{
+  __IO uint16_t *pdwReg = pcd_ep_tx_cnt_ptr((USBx),(bEpNum));
+  wCount = pcd_aligned_buffer_size(wCount);
+  pcd_set_ep_cnt_reg(pdwReg, wCount);
+}
+
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
 {
   __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum));
@@ -310,6 +317,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx
   {
     regVal ^= USB_EPTX_DTOG2;
   }
+
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
   pcd_set_endpoint(USBx, bEpNum, regVal);
 } /* pcd_set_ep_tx_status */
@@ -337,6 +345,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx
   {
     regVal ^= USB_EPRX_DTOG2;
   }
+
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
   pcd_set_endpoint(USBx, bEpNum, regVal);
 } /* pcd_set_ep_rx_status */

From 8db462bf6e2cd6d244ab9b3a69471ad085478bf6 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Thu, 5 Jan 2023 16:54:42 +0100
Subject: [PATCH 1374/2085] Add fix to dcd_edpt_iso_activate()

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index fdcb2c48d..c9b244c8c 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -1026,7 +1026,8 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
   (void)rhport;
   uint8_t const epnum = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum;
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-  const uint16_t packet_size = pcd_aligned_buffer_size(tu_edpt_packet_size(p_endpoint_desc));
+  const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
+  const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size);
 
   /* Disable endpoint */
   if(dir == TUSB_DIR_IN)
@@ -1043,9 +1044,9 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
   // or being double-buffered (bulk endpoints)
   pcd_clear_ep_kind(USB,0);
 
+  pcd_set_ep_tx_bufsize(USB, epnum, buffer_size);
+  pcd_set_ep_rx_bufsize(USB, epnum, buffer_size);
   pcd_clear_tx_dtog(USB, epnum);
-
-  pcd_set_ep_rx_bufsize(USB, epnum, packet_size);
   pcd_clear_rx_dtog(USB, epnum);
 
   xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size;

From 9c73c1a532649630de5e55400632bcca90ebea06 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 6 Jan 2023 10:56:19 +0700
Subject: [PATCH 1375/2085] minor clean up

---
 src/common/tusb_fifo.c | 4 ++--
 src/common/tusb_fifo.h | 8 +++-----
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 6862a6f43..d3875a7d4 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -39,12 +39,12 @@
 // implement mutex lock and unlock
 #if CFG_FIFO_MUTEX
 
-static inline void _ff_lock(tu_fifo_mutex_t mutex)
+static inline void _ff_lock(osal_mutex_t mutex)
 {
   if (mutex) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 }
 
-static inline void _ff_unlock(tu_fifo_mutex_t mutex)
+static inline void _ff_unlock(osal_mutex_t mutex)
 {
   if (mutex) osal_mutex_unlock(mutex);
 }
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index f1810e39c..f72ff295b 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -44,8 +44,6 @@ extern "C" {
 #include "common/tusb_common.h"
 #include "osal/osal.h"
 
-#define tu_fifo_mutex_t  osal_mutex_t
-
 // mutex is only needed for RTOS
 // for OS None, we don't get preempted
 #define CFG_FIFO_MUTEX      OSAL_MUTEX_REQUIRED
@@ -121,8 +119,8 @@ typedef struct
   volatile uint16_t rd_idx      ; ///< read index
 
 #if OSAL_MUTEX_REQUIRED
-  tu_fifo_mutex_t mutex_wr;
-  tu_fifo_mutex_t mutex_rd;
+  osal_mutex_t mutex_wr;
+  osal_mutex_t mutex_rd;
 #endif
 
 } tu_fifo_t;
@@ -155,7 +153,7 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
 
 #if OSAL_MUTEX_REQUIRED
 TU_ATTR_ALWAYS_INLINE static inline
-void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t wr_mutex, tu_fifo_mutex_t rd_mutex)
+void tu_fifo_config_mutex(tu_fifo_t *f, osal_mutex_t wr_mutex, osal_mutex_t rd_mutex)
 {
   f->mutex_wr = wr_mutex;
   f->mutex_rd = rd_mutex;

From 2a1b81e3c50f5e37530c8318b7fb7767ba771979 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 6 Jan 2023 11:51:17 +0700
Subject: [PATCH 1376/2085] minimize tu_fifo size to 16

- remove non_used_index_space
- packed overwritable with item_size
---
 src/common/tusb_fifo.c | 37 ++++++++++++++++++-------------------
 src/common/tusb_fifo.h | 40 +++++++++++++++++++---------------------
 src/device/usbd.c      |  2 ++
 3 files changed, 39 insertions(+), 40 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index d3875a7d4..4dfe7bd81 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -68,22 +68,19 @@ typedef enum
 
 bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable)
 {
-  if (depth > 0x8000) return false;               // Maximum depth is 2^15 items
+  // Limit index space to 2*depth - this allows for a fast "modulo" calculation
+  // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable
+  // only if overflow happens once (important for unsupervised DMA applications)
+  if (depth > 0x8000) return false;
 
   _ff_lock(f->mutex_wr);
   _ff_lock(f->mutex_rd);
 
-  f->buffer = (uint8_t*) buffer;
-  f->depth  = depth;
-  f->item_size = item_size;
+  f->buffer       = (uint8_t*) buffer;
+  f->depth        = depth;
+  f->item_size    = (uint16_t) (item_size & 0x7FFF);
   f->overwritable = overwritable;
 
-  // Limit index space to 2*depth - this allows for a fast "modulo" calculation
-  // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable
-  // only if overflow happens once (important for unsupervised DMA applications)
-  //f->max_pointer_idx = (uint16_t) (2*depth - 1);
-  f->non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1));
-
   f->rd_idx = f->wr_idx = 0;
 
   _ff_unlock(f->mutex_wr);
@@ -331,7 +328,8 @@ static uint16_t advance_pointer(tu_fifo_t* f, uint16_t idx, uint16_t offset)
   uint16_t next_p = (uint16_t) (idx + offset);
   if ( (idx > next_p) || (next_p >= 2*f->depth) )
   {
-    next_p = (uint16_t) (next_p + f->non_used_index_space);
+    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1));
+    next_p = (uint16_t) (next_p + non_used_index_space);
   }
 
   return next_p;
@@ -346,7 +344,8 @@ static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
   uint16_t new_p = (uint16_t) (p - offset);
   if ( (p < new_p) || (new_p >= 2*f->depth) )
   {
-    new_p = (uint16_t) (new_p - f->non_used_index_space);
+    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1));
+    new_p = (uint16_t) (new_p - non_used_index_space);
   }
 
   return new_p;
@@ -363,13 +362,15 @@ static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth)
 // Works on local copies of w and r - return only the difference and as such can be used to determine an overflow
 static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx)
 {
-  uint16_t cnt = (uint16_t) (wr_idx-rd_idx);
+  uint16_t cnt;
 
   // In case we have non-power of two depth we need a further modification
-  if (rd_idx > wr_idx)
+  if (wr_idx >= rd_idx)
   {
-    // 2*f->depth - (rd_idx - wr_idx);
-    cnt = (uint16_t) (cnt - f->non_used_index_space);
+    cnt = (uint16_t) (wr_idx - rd_idx);
+  } else
+  {
+    cnt = (uint16_t) (2*f->depth - (rd_idx - wr_idx));
   }
 
   return cnt;
@@ -395,7 +396,7 @@ static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
 // use DMAs, write functions do not allow such an error.
 static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx)
 {
-  return (_tu_fifo_count(f, wr_idx, rd_idx) > f->depth);
+  return _tu_fifo_count(f, wr_idx, rd_idx) > f->depth;
 }
 
 // Works on local copies of w
@@ -868,8 +869,6 @@ bool tu_fifo_clear(tu_fifo_t *f)
   _ff_lock(f->mutex_rd);
 
   f->rd_idx = f->wr_idx = 0;
-  //f->max_pointer_idx = (uint16_t) (2*f->depth-1);
-  f->non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1));
 
   _ff_unlock(f->mutex_wr);
   _ff_unlock(f->mutex_rd);
diff --git a/src/common/tusb_fifo.h b/src/common/tusb_fifo.h
index f72ff295b..2f60ec2f4 100644
--- a/src/common/tusb_fifo.h
+++ b/src/common/tusb_fifo.h
@@ -69,8 +69,8 @@ extern "C" {
  *    | 0 | 1 | W | 3 | 4 | R |
  *
  * - Number of items in the fifo can be determined in either cases:
- *    - case W > R: Count = W - R
- *    - case W < R: Count = 2*depth - (R - W)
+ *    - case W >= R: Count = W - R
+ *    - case W <  R: Count = 2*depth - (R - W)
  *
  * In non-overwritable mode, computed Count (in above 2 cases) is at most equal to depth.
  * However, in over-writable mode, write index can be repeatedly increased and count can be
@@ -82,10 +82,10 @@ extern "C" {
  *      -------------------------
  *      | R | 1 | 2 | 3 | W | 5 |
  *
- *  - Double Overflowed i.e index is out of allowed range [0,2*depth) e.g:
+ *  - Double Overflowed i.e index is out of allowed range [0,2*depth)
+ *    This occurs when we continue to write after 1st overflowed to 2nd overflowed. e.g:
  *      write(3), write(1), write(2)
- *    Continue to write after overflowed to 2nd overflowed.
- *    We must prevent 2nd overflowed since it will cause incorrect computed of count, in above example
+ *    This must be prevented since it will cause unrecoverable state, in above example
  *    if not handled the fifo will be empty instead of continue-to-be full. Since we must not modify
  *    read index in write() function, which cause race condition. We will re-position write index so that
  *    after data is written it is a full fifo i.e W = depth - R
@@ -106,17 +106,16 @@ extern "C" {
  */
 typedef struct
 {
-  uint8_t* buffer               ; ///< buffer pointer
-  uint16_t depth                ; ///< max items
-  uint16_t item_size            ; ///< size of each item
+  uint8_t* buffer          ; // buffer pointer
+  uint16_t depth           ; // max items
 
-  bool overwritable             ;
+  struct TU_ATTR_PACKED {
+    uint16_t item_size : 15; // size of each item
+    bool overwritable  : 1 ; // ovwerwritable when full
+  };
 
-  uint16_t non_used_index_space ; ///< required for non-power-of-two buffer length
-  //uint16_t max_pointer_idx      ; ///< maximum absolute pointer index
-
-  volatile uint16_t wr_idx      ; ///< write index
-  volatile uint16_t rd_idx      ; ///< read index
+  volatile uint16_t wr_idx ; // write index
+  volatile uint16_t rd_idx ; // read index
 
 #if OSAL_MUTEX_REQUIRED
   osal_mutex_t mutex_wr;
@@ -133,13 +132,12 @@ typedef struct
   void * ptr_wrap   ; ///< wrapped part start pointer
 } tu_fifo_buffer_info_t;
 
-#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable)        \
-{                                                                  \
-  .buffer               = _buffer,                                 \
-  .depth                = _depth,                                  \
-  .item_size            = sizeof(_type),                           \
-  .overwritable         = _overwritable,                           \
-  .non_used_index_space = (uint16_t)(UINT16_MAX - (2*(_depth)-1)), \
+#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \
+{                                                           \
+  .buffer               = _buffer,                          \
+  .depth                = _depth,                           \
+  .item_size            = sizeof(_type),                    \
+  .overwritable         = _overwritable,                    \
 }
 
 #define TU_FIFO_DEF(_name, _depth, _type, _overwritable)                      \
diff --git a/src/device/usbd.c b/src/device/usbd.c
index f652a878e..6e0c6710d 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -388,6 +388,8 @@ bool tud_init (uint8_t rhport)
 
   TU_LOG(USBD_DBG, "USBD init on controller %u\r\n", rhport);
   TU_LOG_INT(USBD_DBG, sizeof(usbd_device_t));
+  TU_LOG_INT(USBD_DBG, sizeof(tu_fifo_t));
+  TU_LOG_INT(USBD_DBG, sizeof(tu_edpt_stream_t));
 
   tu_varclr(&_usbd_dev);
 

From 82457519fa050b2efd1b462ba88f7f258047c715 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 6 Jan 2023 12:11:55 +0700
Subject: [PATCH 1377/2085] minor clean up

---
 src/common/tusb_fifo.c | 66 ++++++++++++++++++++++--------------------
 1 file changed, 35 insertions(+), 31 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 4dfe7bd81..f72c8a12f 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -28,16 +28,15 @@
 #include "osal/osal.h"
 #include "tusb_fifo.h"
 
+#define TU_FIFO_DBG   0
+
 // Suppress IAR warning
 // Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement
 #if defined(__ICCARM__)
 #pragma diag_suppress = Pa082
 #endif
 
-#define TU_FIFO_DBG   0
-
-// implement mutex lock and unlock
-#if CFG_FIFO_MUTEX
+#if OSAL_MUTEX_REQUIRED
 
 static inline void _ff_lock(osal_mutex_t mutex)
 {
@@ -80,8 +79,8 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
   f->depth        = depth;
   f->item_size    = (uint16_t) (item_size & 0x7FFF);
   f->overwritable = overwritable;
-
-  f->rd_idx = f->wr_idx = 0;
+  f->rd_idx       = 0;
+  f->wr_idx       = 0;
 
   _ff_unlock(f->mutex_wr);
   _ff_unlock(f->mutex_rd);
@@ -142,13 +141,13 @@ static void _ff_pull_const_addr(void * app_buf, const uint8_t * ff_buf, uint16_t
   }
 }
 
-// send one item to FIFO WITHOUT updating write pointer
+// send one item to fifo WITHOUT updating write pointer
 static inline void _ff_push(tu_fifo_t* f, void const * app_buf, uint16_t rel)
 {
   memcpy(f->buffer + (rel * f->item_size), app_buf, f->item_size);
 }
 
-// send n items to FIFO WITHOUT updating write pointer
+// send n items to fifo WITHOUT updating write pointer
 static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode)
 {
   uint16_t const nLin = f->depth - rel;
@@ -227,13 +226,13 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
   }
 }
 
-// get one item from FIFO WITHOUT updating read pointer
+// get one item from fifo WITHOUT updating read pointer
 static inline void _ff_pull(tu_fifo_t* f, void * app_buf, uint16_t rel)
 {
   memcpy(app_buf, f->buffer + (rel * f->item_size), f->item_size);
 }
 
-// get n items from FIFO WITHOUT updating read pointer
+// get n items from fifo WITHOUT updating read pointer
 static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode)
 {
   uint16_t const nLin = f->depth - rel;
@@ -475,14 +474,14 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
   uint16_t rd_idx = f->rd_idx;
 
   uint8_t const* buf8 = (uint8_t const*) data;
-  uint16_t overflowable_count = _tu_fifo_count(f, wr_idx, rd_idx);
-  uint16_t const remain = _tu_fifo_remaining(f, wr_idx, rd_idx);
 
-  TU_LOG(TU_FIFO_DBG, "rd = %3u, wr = %3u, count = %3u, remain = %3u, n = %3u:  ", rd_idx, wr_idx, _tu_fifo_count(f, wr_idx, rd_idx), remain, n);
+  TU_LOG(TU_FIFO_DBG, "rd = %3u, wr = %3u, count = %3u, remain = %3u, n = %3u:  ",
+                       rd_idx, wr_idx, _tu_fifo_count(f, wr_idx, rd_idx), _tu_fifo_remaining(f, wr_idx, rd_idx), n);
 
   if ( !f->overwritable )
   {
     // limit up to full
+    uint16_t const remain = _tu_fifo_remaining(f, wr_idx, rd_idx);
     n = tu_min16(n, remain);
   }
   else
@@ -508,23 +507,27 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
       // We start writing at the read pointer's position since we fill the whole buffer
       wr_idx = rd_idx;
     }
-    else if (overflowable_count + n >= 2*f->depth)
+    else
     {
-      // Double overflowed
-      // Index is bigger than the allowed range [0,2*depth)
-      // re-position write index to have a full fifo after pushed
-      wr_idx = advance_pointer(f, rd_idx, f->depth - n);
+      uint16_t const overflowable_count = _tu_fifo_count(f, wr_idx, rd_idx);
+      if (overflowable_count + n >= 2*f->depth)
+      {
+        // Double overflowed
+        // Index is bigger than the allowed range [0,2*depth)
+        // re-position write index to have a full fifo after pushed
+        wr_idx = advance_pointer(f, rd_idx, f->depth - n);
 
-      // TODO we should also shift out n bytes from read index since we avoid changing rd index !!
-      // However memmove() is expensive due to actual copying + wrapping consideration.
-      // Also race condition could happen anyway if read() is invoke while moving result in corrupted memory
-      // currently deliberately not implemented --> result in incorrect data read back
-    }else
-    {
-      // normal + single overflowed:
-      // Index is in the range of [0,2*depth) and thus detect and recoverable. Recovering is handled in read()
-      // Therefore we just increase write index
-      // we will correct (re-position) read index later on in fifo_read() function
+        // TODO we should also shift out n bytes from read index since we avoid changing rd index !!
+        // However memmove() is expensive due to actual copying + wrapping consideration.
+        // Also race condition could happen anyway if read() is invoke while moving result in corrupted memory
+        // currently deliberately not implemented --> result in incorrect data read back
+      }else
+      {
+        // normal + single overflowed:
+        // Index is in the range of [0,2*depth) and thus detect and recoverable. Recovering is handled in read()
+        // Therefore we just increase write index
+        // we will correct (re-position) read index later on in fifo_read() function
+      }
     }
   }
 
@@ -868,7 +871,8 @@ bool tu_fifo_clear(tu_fifo_t *f)
   _ff_lock(f->mutex_wr);
   _ff_lock(f->mutex_rd);
 
-  f->rd_idx = f->wr_idx = 0;
+  f->rd_idx = 0;
+  f->wr_idx = 0;
 
   _ff_unlock(f->mutex_wr);
   _ff_unlock(f->mutex_rd);
@@ -1031,9 +1035,9 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
 
   if (remain == 0)
   {
-    info->len_lin = 0;
+    info->len_lin  = 0;
     info->len_wrap = 0;
-    info->ptr_lin = NULL;
+    info->ptr_lin  = NULL;
     info->ptr_wrap = NULL;
     return;
   }

From e885ced0fed0a59d093db09c3e7325457d863fc1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 7 Jan 2023 16:24:05 +0700
Subject: [PATCH 1378/2085] using clang with ceedling unit-test with
 -fsanitize=address

---
 test/unit-test/project.yml | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/test/unit-test/project.yml b/test/unit-test/project.yml
index 7708123d5..562dbca09 100644
--- a/test/unit-test/project.yml
+++ b/test/unit-test/project.yml
@@ -78,10 +78,24 @@
     :html_high_threshold: 90
     :xml_report: FALSE
 
-#:tools:
-# Ceedling defaults to using gcc for compiling, linking, etc.
-# As [:tools] is blank, gcc will be used (so long as it's in your system path)
-# See documentation to configure a given toolchain for use
+:tools:
+  :test_compiler:
+     :executable: clang
+     :name: 'clang compiler'
+     :arguments:
+        - -I"$": COLLECTION_PATHS_TEST_TOOLCHAIN_INCLUDE               #expands to -I search paths
+        - -I"$": COLLECTION_PATHS_TEST_SUPPORT_SOURCE_INCLUDE_VENDOR   #expands to -I search paths
+        - -D$: COLLECTION_DEFINES_TEST_AND_VENDOR  #expands to all -D defined symbols
+        - -fsanitize=address
+        - -c ${1}                       #source code input file (Ruby method call param list sub)
+        - -o ${2}                       #object file output (Ruby method call param list sub)
+  :test_linker:
+     :executable: clang
+     :name: 'clang linker'
+     :arguments:
+        - -fsanitize=address
+        - ${1}               #list of object files to link (Ruby method call param list sub)
+        - -o ${2}            #executable file output (Ruby method call param list sub)
 
 # LIBRARIES
 # These libraries are automatically injected into the build process. Those specified as

From 2d7849282a8e3137107d92a99418dd8996163193 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 7 Jan 2023 16:33:11 +0700
Subject: [PATCH 1379/2085] use TU_FIFO_INIT to replace TU_FIFO_DEF

---
 test/unit-test/test/test_fifo.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/test/unit-test/test/test_fifo.c b/test/unit-test/test/test_fifo.c
index 2726ac59a..28be6d8fc 100644
--- a/test/unit-test/test/test_fifo.c
+++ b/test/unit-test/test/test_fifo.c
@@ -30,8 +30,10 @@
 #include "osal/osal.h"
 #include "tusb_fifo.h"
 
-#define FIFO_SIZE 64
-TU_FIFO_DEF(tu_ff, FIFO_SIZE, uint8_t, false);
+#define FIFO_SIZE   64
+uint8_t tu_ff_buf[FIFO_SIZE * sizeof(uint8_t)];
+tu_fifo_t tu_ff = TU_FIFO_INIT(tu_ff_buf, FIFO_SIZE, uint8_t, false);
+
 tu_fifo_t* ff = &tu_ff;
 tu_fifo_buffer_info_t info;
 
@@ -68,7 +70,8 @@ void test_normal(void)
 
 void test_item_size(void)
 {
-  TU_FIFO_DEF(ff4, FIFO_SIZE, uint32_t, false);
+  uint8_t ff4_buf[FIFO_SIZE * sizeof(uint32_t)];
+  tu_fifo_t ff4 = TU_FIFO_INIT(ff4_buf, FIFO_SIZE, uint32_t, false);
 
   uint32_t data4[2*FIFO_SIZE];
   for(uint32_t i=0; i<sizeof(data4)/4; i++) data4[i] = i;

From a804a1ac09c34a4f69c0d2873a552a2a505d0492 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 7 Jan 2023 16:48:07 +0700
Subject: [PATCH 1380/2085] simplify and remove _tu_fifo_empty, _tu_fifo_full.
 Also correct full condition check

---
 src/common/tusb_fifo.c | 30 +++++++-----------------------
 1 file changed, 7 insertions(+), 23 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index f72c8a12f..4b27bc589 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -38,12 +38,12 @@
 
 #if OSAL_MUTEX_REQUIRED
 
-static inline void _ff_lock(osal_mutex_t mutex)
+TU_ATTR_ALWAYS_INLINE static inline void _ff_lock(osal_mutex_t mutex)
 {
   if (mutex) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 }
 
-static inline void _ff_unlock(osal_mutex_t mutex)
+TU_ATTR_ALWAYS_INLINE static inline void _ff_unlock(osal_mutex_t mutex)
 {
   if (mutex) osal_mutex_unlock(mutex);
 }
@@ -361,30 +361,14 @@ static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth)
 // Works on local copies of w and r - return only the difference and as such can be used to determine an overflow
 static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx)
 {
-  uint16_t cnt;
-
   // In case we have non-power of two depth we need a further modification
   if (wr_idx >= rd_idx)
   {
-    cnt = (uint16_t) (wr_idx - rd_idx);
+    return (uint16_t) (wr_idx - rd_idx);
   } else
   {
-    cnt = (uint16_t) (2*f->depth - (rd_idx - wr_idx));
+    return (uint16_t) (2*f->depth - (rd_idx - wr_idx));
   }
-
-  return cnt;
-}
-
-// Works on local copies of w and r
-static inline bool _tu_fifo_empty(uint16_t wr_idx, uint16_t rd_idx)
-{
-  return wr_idx == rd_idx;
-}
-
-// Works on local copies of w and r
-static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
-{
-  return _tu_fifo_count(f, wAbs, rAbs) == f->depth;
 }
 
 // Works on local copies of w and r
@@ -601,7 +585,7 @@ uint16_t tu_fifo_count(tu_fifo_t* f)
 /******************************************************************************/
 bool tu_fifo_empty(tu_fifo_t* f)
 {
-  return _tu_fifo_empty(f->wr_idx, f->rd_idx);
+  return f->wr_idx == f->rd_idx;
 }
 
 /******************************************************************************/
@@ -619,7 +603,7 @@ bool tu_fifo_empty(tu_fifo_t* f)
 /******************************************************************************/
 bool tu_fifo_full(tu_fifo_t* f)
 {
-  return _tu_fifo_full(f, f->wr_idx, f->rd_idx);
+  return _tu_fifo_count(f, f->wr_idx, f->rd_idx) >= f->depth;
 }
 
 /******************************************************************************/
@@ -798,7 +782,7 @@ bool tu_fifo_write(tu_fifo_t* f, const void * data)
   bool ret;
   uint16_t const wr_idx = f->wr_idx;
 
-  if ( _tu_fifo_full(f, wr_idx, f->rd_idx) && !f->overwritable )
+  if ( tu_fifo_full(f) && !f->overwritable )
   {
     ret = false;
   }else

From 507d5b10b049d865e5bb24f99038eed07d092e8f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 7 Jan 2023 17:14:17 +0700
Subject: [PATCH 1381/2085] simplify _tu_fifo_count() and _tu_fifo_remaining(),
 also rename to _ff_count() and _ff_remaining()

---
 src/common/tusb_fifo.c | 57 ++++++++++++++++++++++++------------------
 1 file changed, 32 insertions(+), 25 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 4b27bc589..cdb0df73f 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -358,8 +358,9 @@ static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth)
   return idx;
 }
 
-// Works on local copies of w and r - return only the difference and as such can be used to determine an overflow
-static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx)
+// return only the index difference and as such can be used to determine an overflow i.e overflowable count
+TU_ATTR_ALWAYS_INLINE static inline
+uint16_t _ff_count(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
 {
   // In case we have non-power of two depth we need a further modification
   if (wr_idx >= rd_idx)
@@ -367,24 +368,33 @@ static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd
     return (uint16_t) (wr_idx - rd_idx);
   } else
   {
-    return (uint16_t) (2*f->depth - (rd_idx - wr_idx));
+    return (uint16_t) (2*depth - (rd_idx - wr_idx));
   }
 }
 
-// Works on local copies of w and r
 // BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS"
 // Only one overflow is allowed for this function to work e.g. if depth = 100, you must not
 // write more than 2*depth-1 items in one rush without updating write pointer. Otherwise
 // write pointer wraps and you pointer states are messed up. This can only happen if you
 // use DMAs, write functions do not allow such an error.
-static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx)
+TU_ATTR_ALWAYS_INLINE static inline
+bool _ff_overflowed(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
 {
-  return _tu_fifo_count(f, wr_idx, rd_idx) > f->depth;
+  return _ff_count(depth, wr_idx, rd_idx) > depth;
+}
+
+// return remaining slot in fifo
+TU_ATTR_ALWAYS_INLINE static inline
+uint16_t _ff_remaining(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
+{
+  uint16_t const count = _ff_count(depth, wr_idx, rd_idx);
+  return (depth > count) ? (depth - count) : 0;
 }
 
 // Works on local copies of w
 // For more details see _tu_fifo_overflow()!
-static inline void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs)
+TU_ATTR_ALWAYS_INLINE static inline
+void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs)
 {
   f->rd_idx = backward_pointer(f, wAbs, f->depth);
 }
@@ -393,7 +403,7 @@ static inline void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs)
 // Must be protected by mutexes since in case of an overflow read pointer gets modified
 static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16_t rd_idx)
 {
-  uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx);
+  uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx);
 
   // Check overflow and correct if required
   if (cnt > f->depth)
@@ -417,7 +427,7 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16
 // Must be protected by mutexes since in case of an overflow read pointer gets modified
 static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t wr_idx, uint16_t rd_idx, tu_fifo_copy_mode_t copy_mode)
 {
-  uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx);
+  uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx);
 
   // Check overflow and correct if required
   if (cnt > f->depth)
@@ -441,13 +451,6 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1
   return n;
 }
 
-// Works on local copies of w and r
-static inline uint16_t _tu_fifo_remaining(tu_fifo_t* f, uint16_t wr_idx, uint16_t rd_idx)
-{
-  uint16_t const count = _tu_fifo_count(f, wr_idx, rd_idx);
-  return (f->depth > count) ? (f->depth - count) : 0;
-}
-
 static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu_fifo_copy_mode_t copy_mode)
 {
   if ( n == 0 ) return 0;
@@ -460,12 +463,12 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
   uint8_t const* buf8 = (uint8_t const*) data;
 
   TU_LOG(TU_FIFO_DBG, "rd = %3u, wr = %3u, count = %3u, remain = %3u, n = %3u:  ",
-                       rd_idx, wr_idx, _tu_fifo_count(f, wr_idx, rd_idx), _tu_fifo_remaining(f, wr_idx, rd_idx), n);
+                       rd_idx, wr_idx, _ff_count(f->depth, wr_idx, rd_idx), _ff_remaining(f->depth, wr_idx, rd_idx), n);
 
   if ( !f->overwritable )
   {
     // limit up to full
-    uint16_t const remain = _tu_fifo_remaining(f, wr_idx, rd_idx);
+    uint16_t const remain = _ff_remaining(f->depth, wr_idx, rd_idx);
     n = tu_min16(n, remain);
   }
   else
@@ -493,7 +496,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
     }
     else
     {
-      uint16_t const overflowable_count = _tu_fifo_count(f, wr_idx, rd_idx);
+      uint16_t const overflowable_count = _ff_count(f->depth, wr_idx, rd_idx);
       if (overflowable_count + n >= 2*f->depth)
       {
         // Double overflowed
@@ -550,6 +553,10 @@ static uint16_t _tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n, tu_fifo
   return n;
 }
 
+//--------------------------------------------------------------------+
+// Application API
+//--------------------------------------------------------------------+
+
 /******************************************************************************/
 /*!
     @brief Get number of items in FIFO.
@@ -567,7 +574,7 @@ static uint16_t _tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n, tu_fifo
 /******************************************************************************/
 uint16_t tu_fifo_count(tu_fifo_t* f)
 {
-  return tu_min16(_tu_fifo_count(f, f->wr_idx, f->rd_idx), f->depth);
+  return tu_min16(_ff_count(f->depth, f->wr_idx, f->rd_idx), f->depth);
 }
 
 /******************************************************************************/
@@ -603,7 +610,7 @@ bool tu_fifo_empty(tu_fifo_t* f)
 /******************************************************************************/
 bool tu_fifo_full(tu_fifo_t* f)
 {
-  return _tu_fifo_count(f, f->wr_idx, f->rd_idx) >= f->depth;
+  return _ff_count(f->depth, f->wr_idx, f->rd_idx) >= f->depth;
 }
 
 /******************************************************************************/
@@ -621,7 +628,7 @@ bool tu_fifo_full(tu_fifo_t* f)
 /******************************************************************************/
 uint16_t tu_fifo_remaining(tu_fifo_t* f)
 {
-  return _tu_fifo_remaining(f, f->wr_idx, f->rd_idx);
+  return _ff_remaining(f->depth, f->wr_idx, f->rd_idx);
 }
 
 /******************************************************************************/
@@ -647,7 +654,7 @@ uint16_t tu_fifo_remaining(tu_fifo_t* f)
 /******************************************************************************/
 bool tu_fifo_overflowed(tu_fifo_t* f)
 {
-  return _tu_fifo_overflowed(f, f->wr_idx, f->rd_idx);
+  return _ff_overflowed(f->depth, f->wr_idx, f->rd_idx);
 }
 
 // Only use in case tu_fifo_overflow() returned true!
@@ -949,7 +956,7 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
   uint16_t wr_idx = f->wr_idx;
   uint16_t rd_idx = f->rd_idx;
 
-  uint16_t cnt = _tu_fifo_count(f, wr_idx, rd_idx);
+  uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx);
 
   // Check overflow and correct if required - may happen in case a DMA wrote too fast
   if (cnt > f->depth)
@@ -1015,7 +1022,7 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
 {
   uint16_t wr_idx = f->wr_idx;
   uint16_t rd_idx = f->rd_idx;
-  uint16_t remain = _tu_fifo_remaining(f, wr_idx, rd_idx);
+  uint16_t remain = _ff_remaining(f->depth, wr_idx, rd_idx);
 
   if (remain == 0)
   {

From 24bd1c95623377a81286f9d516da57c34451c515 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 7 Jan 2023 17:27:26 +0700
Subject: [PATCH 1382/2085] update advance_pointer/backward_pointer to use
 depth instead of fifo, also rename to advance/backward_index

---
 src/common/tusb_fifo.c | 44 +++++++++++++++++++++---------------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index cdb0df73f..8de58c4a4 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -319,35 +319,35 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
 
 // Advance an absolute index
 // "absolute" index is only in the range of [0..2*depth)
-static uint16_t advance_pointer(tu_fifo_t* f, uint16_t idx, uint16_t offset)
+static uint16_t advance_index(uint16_t depth, uint16_t idx, uint16_t offset)
 {
   // We limit the index space of p such that a correct wrap around happens
   // Check for a wrap around or if we are in unused index space - This has to be checked first!!
   // We are exploiting the wrap around to the correct index
-  uint16_t next_p = (uint16_t) (idx + offset);
-  if ( (idx > next_p) || (next_p >= 2*f->depth) )
+  uint16_t new_idx = (uint16_t) (idx + offset);
+  if ( (idx > new_idx) || (new_idx >= 2*depth) )
   {
-    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1));
-    next_p = (uint16_t) (next_p + non_used_index_space);
+    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*depth-1));
+    new_idx = (uint16_t) (new_idx + non_used_index_space);
   }
 
-  return next_p;
+  return new_idx;
 }
 
-// Backward an absolute pointer
-static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
+// Backward an absolute index
+static uint16_t backward_index(uint16_t depth, uint16_t idx, uint16_t offset)
 {
   // We limit the index space of p such that a correct wrap around happens
   // Check for a wrap around or if we are in unused index space - This has to be checked first!!
   // We are exploiting the wrap around to the correct index
-  uint16_t new_p = (uint16_t) (p - offset);
-  if ( (p < new_p) || (new_p >= 2*f->depth) )
+  uint16_t new_idx = (uint16_t) (idx - offset);
+  if ( (idx < new_idx) || (new_idx >= 2*depth) )
   {
-    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*f->depth-1));
-    new_p = (uint16_t) (new_p - non_used_index_space);
+    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*depth-1));
+    new_idx = (uint16_t) (new_idx - non_used_index_space);
   }
 
-  return new_p;
+  return new_idx;
 }
 
 // index to pointer, simply an modulo with minus.
@@ -394,9 +394,9 @@ uint16_t _ff_remaining(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
 // Works on local copies of w
 // For more details see _tu_fifo_overflow()!
 TU_ATTR_ALWAYS_INLINE static inline
-void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs)
+void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wr_idx)
 {
-  f->rd_idx = backward_pointer(f, wAbs, f->depth);
+  f->rd_idx = backward_index(f->depth, wr_idx, f->depth);
 }
 
 // Works on local copies of w and r
@@ -502,7 +502,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
         // Double overflowed
         // Index is bigger than the allowed range [0,2*depth)
         // re-position write index to have a full fifo after pushed
-        wr_idx = advance_pointer(f, rd_idx, f->depth - n);
+        wr_idx = advance_index(f->depth, rd_idx, f->depth - n);
 
         // TODO we should also shift out n bytes from read index since we avoid changing rd index !!
         // However memmove() is expensive due to actual copying + wrapping consideration.
@@ -528,7 +528,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
     _ff_push_n(f, buf8, n, wr_ptr, copy_mode);
 
     // Advance index
-    f->wr_idx = advance_pointer(f, wr_idx, n);
+    f->wr_idx = advance_index(f->depth, wr_idx, n);
 
     TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\n", f->wr_idx);
   }
@@ -547,7 +547,7 @@ static uint16_t _tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n, tu_fifo
   n = _tu_fifo_peek_n(f, buffer, n, f->wr_idx, f->rd_idx, copy_mode);
 
   // Advance read pointer
-  f->rd_idx = advance_pointer(f, f->rd_idx, n);
+  f->rd_idx = advance_index(f->depth, f->rd_idx, n);
 
   _ff_unlock(f->mutex_rd);
   return n;
@@ -690,7 +690,7 @@ bool tu_fifo_read(tu_fifo_t* f, void * buffer)
   bool ret = _tu_fifo_peek(f, buffer, f->wr_idx, f->rd_idx);
 
   // Advance pointer
-  f->rd_idx = advance_pointer(f, f->rd_idx, ret);
+  f->rd_idx = advance_index(f->depth, f->rd_idx, ret);
 
   _ff_unlock(f->mutex_rd);
   return ret;
@@ -800,7 +800,7 @@ bool tu_fifo_write(tu_fifo_t* f, const void * data)
     _ff_push(f, data, wr_ptr);
 
     // Advance pointer
-    f->wr_idx = advance_pointer(f, wr_idx, 1);
+    f->wr_idx = advance_index(f->depth, wr_idx, 1);
 
     ret = true;
   }
@@ -911,7 +911,7 @@ bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable)
 /******************************************************************************/
 void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n)
 {
-  f->wr_idx = advance_pointer(f, f->wr_idx, n);
+  f->wr_idx = advance_index(f->depth, f->wr_idx, n);
 }
 
 /******************************************************************************/
@@ -932,7 +932,7 @@ void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n)
 /******************************************************************************/
 void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n)
 {
-  f->rd_idx = advance_pointer(f, f->rd_idx, n);
+  f->rd_idx = advance_index(f->depth, f->rd_idx, n);
 }
 
 /******************************************************************************/

From 248025bb6cdf361e93603204d89cbf58e9e3b0af Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 7 Jan 2023 17:29:43 +0700
Subject: [PATCH 1383/2085] reverse idx2ptr() arguments to be consistent

---
 src/common/tusb_fifo.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 8de58c4a4..a0ce73ba0 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -351,7 +351,8 @@ static uint16_t backward_index(uint16_t depth, uint16_t idx, uint16_t offset)
 }
 
 // index to pointer, simply an modulo with minus.
-static inline uint16_t idx2ptr(uint16_t idx, uint16_t depth)
+TU_ATTR_ALWAYS_INLINE static inline
+uint16_t idx2ptr(uint16_t depth, uint16_t idx)
 {
   // Only run at most 3 times since index is limit in the range of [0..2*depth)
   while ( idx >= depth ) idx -= depth;
@@ -415,7 +416,7 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16
   // Skip beginning of buffer
   if (cnt == 0) return false;
 
-  uint16_t rd_ptr = idx2ptr(rd_idx, f->depth);
+  uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
   // Peek data
   _ff_pull(f, p_buffer, rd_ptr);
@@ -443,7 +444,7 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1
   // Check if we can read something at and after offset - if too less is available we read what remains
   if (cnt < n) n = cnt;
 
-  uint16_t rd_ptr = idx2ptr(rd_idx, f->depth);
+  uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
   // Peek data
   _ff_pull_n(f, p_buffer, n, rd_ptr, copy_mode);
@@ -520,7 +521,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
 
   if (n)
   {
-    uint16_t wr_ptr = idx2ptr(wr_idx, f->depth);
+    uint16_t wr_ptr = idx2ptr(f->depth, wr_idx);
 
     TU_LOG(TU_FIFO_DBG, "actual_n = %u, wr_ptr = %u", n, wr_ptr);
 
@@ -794,7 +795,7 @@ bool tu_fifo_write(tu_fifo_t* f, const void * data)
     ret = false;
   }else
   {
-    uint16_t wr_ptr = idx2ptr(wr_idx, f->depth);
+    uint16_t wr_ptr = idx2ptr(f->depth, wr_idx);
 
     // Write data
     _ff_push(f, data, wr_ptr);
@@ -980,8 +981,8 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
   }
 
   // Get relative pointers
-  uint16_t wr_ptr = idx2ptr(wr_idx, f->depth);
-  uint16_t rd_ptr = idx2ptr(rd_idx, f->depth);
+  uint16_t wr_ptr = idx2ptr(f->depth, wr_idx);
+  uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
   // Copy pointer to buffer to start reading from
   info->ptr_lin = &f->buffer[rd_ptr];
@@ -1034,8 +1035,8 @@ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
   }
 
   // Get relative pointers
-  uint16_t wr_ptr = idx2ptr(wr_idx, f->depth);
-  uint16_t rd_ptr = idx2ptr(rd_idx, f->depth);
+  uint16_t wr_ptr = idx2ptr(f->depth, wr_idx);
+  uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
   // Copy pointer to buffer to start writing to
   info->ptr_lin = &f->buffer[wr_ptr];

From c29b7643a59f4baa266d13ef0a7bed864ad83eb2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 7 Jan 2023 18:50:19 +0700
Subject: [PATCH 1384/2085] simplify _ff_correct_read_index()

---
 src/common/tusb_fifo.c | 137 +++++++++++++++++++++++------------------
 1 file changed, 77 insertions(+), 60 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index a0ce73ba0..22d6e8e55 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -314,51 +314,9 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
 }
 
 //--------------------------------------------------------------------+
-// Index (free-running and real buffer pointer)
+// Helper
 //--------------------------------------------------------------------+
 
-// Advance an absolute index
-// "absolute" index is only in the range of [0..2*depth)
-static uint16_t advance_index(uint16_t depth, uint16_t idx, uint16_t offset)
-{
-  // We limit the index space of p such that a correct wrap around happens
-  // Check for a wrap around or if we are in unused index space - This has to be checked first!!
-  // We are exploiting the wrap around to the correct index
-  uint16_t new_idx = (uint16_t) (idx + offset);
-  if ( (idx > new_idx) || (new_idx >= 2*depth) )
-  {
-    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*depth-1));
-    new_idx = (uint16_t) (new_idx + non_used_index_space);
-  }
-
-  return new_idx;
-}
-
-// Backward an absolute index
-static uint16_t backward_index(uint16_t depth, uint16_t idx, uint16_t offset)
-{
-  // We limit the index space of p such that a correct wrap around happens
-  // Check for a wrap around or if we are in unused index space - This has to be checked first!!
-  // We are exploiting the wrap around to the correct index
-  uint16_t new_idx = (uint16_t) (idx - offset);
-  if ( (idx < new_idx) || (new_idx >= 2*depth) )
-  {
-    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*depth-1));
-    new_idx = (uint16_t) (new_idx - non_used_index_space);
-  }
-
-  return new_idx;
-}
-
-// index to pointer, simply an modulo with minus.
-TU_ATTR_ALWAYS_INLINE static inline
-uint16_t idx2ptr(uint16_t depth, uint16_t idx)
-{
-  // Only run at most 3 times since index is limit in the range of [0..2*depth)
-  while ( idx >= depth ) idx -= depth;
-  return idx;
-}
-
 // return only the index difference and as such can be used to determine an overflow i.e overflowable count
 TU_ATTR_ALWAYS_INLINE static inline
 uint16_t _ff_count(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
@@ -392,12 +350,72 @@ uint16_t _ff_remaining(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
   return (depth > count) ? (depth - count) : 0;
 }
 
-// Works on local copies of w
-// For more details see _tu_fifo_overflow()!
-TU_ATTR_ALWAYS_INLINE static inline
-void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wr_idx)
+//--------------------------------------------------------------------+
+// Index Helper
+//--------------------------------------------------------------------+
+
+// Advance an absolute index
+// "absolute" index is only in the range of [0..2*depth)
+static uint16_t advance_index(uint16_t depth, uint16_t idx, uint16_t offset)
 {
-  f->rd_idx = backward_index(f->depth, wr_idx, f->depth);
+  // We limit the index space of p such that a correct wrap around happens
+  // Check for a wrap around or if we are in unused index space - This has to be checked first!!
+  // We are exploiting the wrap around to the correct index
+  uint16_t new_idx = (uint16_t) (idx + offset);
+  if ( (idx > new_idx) || (new_idx >= 2*depth) )
+  {
+    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*depth-1));
+    new_idx = (uint16_t) (new_idx + non_used_index_space);
+  }
+
+  return new_idx;
+}
+
+#if 0 // not used but
+// Backward an absolute index
+static uint16_t backward_index(uint16_t depth, uint16_t idx, uint16_t offset)
+{
+  // We limit the index space of p such that a correct wrap around happens
+  // Check for a wrap around or if we are in unused index space - This has to be checked first!!
+  // We are exploiting the wrap around to the correct index
+  uint16_t new_idx = (uint16_t) (idx - offset);
+  if ( (idx < new_idx) || (new_idx >= 2*depth) )
+  {
+    uint16_t const non_used_index_space = (uint16_t) (UINT16_MAX - (2*depth-1));
+    new_idx = (uint16_t) (new_idx - non_used_index_space);
+  }
+
+  return new_idx;
+}
+#endif
+
+// index to pointer, simply an modulo with minus.
+TU_ATTR_ALWAYS_INLINE static inline
+uint16_t idx2ptr(uint16_t depth, uint16_t idx)
+{
+  // Only run at most 3 times since index is limit in the range of [0..2*depth)
+  while ( idx >= depth ) idx -= depth;
+  return idx;
+}
+
+// Works on local copies of w
+// When an overwritable fifo is overflowed, rd_idx will be re-index so that it forms
+// an full fifo i.e _ff_count() = depth
+TU_ATTR_ALWAYS_INLINE static inline
+uint16_t _ff_correct_read_index(tu_fifo_t* f, uint16_t wr_idx)
+{
+  uint16_t rd_idx;
+  if ( wr_idx >= f->depth )
+  {
+    rd_idx = wr_idx - f->depth;
+  }else
+  {
+    rd_idx = wr_idx + f->depth;
+  }
+
+  f->rd_idx = rd_idx;
+
+  return rd_idx;
 }
 
 // Works on local copies of w and r
@@ -407,14 +425,14 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16
   uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx);
 
   // Check overflow and correct if required
-  if (cnt > f->depth)
+  if ( cnt > f->depth )
   {
-    _tu_fifo_correct_read_pointer(f, wr_idx);
+    rd_idx = _ff_correct_read_index(f, wr_idx);
     cnt = f->depth;
   }
 
   // Skip beginning of buffer
-  if (cnt == 0) return false;
+  if ( cnt == 0 ) return false;
 
   uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
@@ -431,18 +449,17 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1
   uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx);
 
   // Check overflow and correct if required
-  if (cnt > f->depth)
+  if ( cnt > f->depth )
   {
-    _tu_fifo_correct_read_pointer(f, wr_idx);
-    rd_idx = f->rd_idx;
+    rd_idx = _ff_correct_read_index(f, wr_idx);
     cnt = f->depth;
   }
 
   // Skip beginning of buffer
-  if (cnt == 0) return 0;
+  if ( cnt == 0 ) return 0;
 
   // Check if we can read something at and after offset - if too less is available we read what remains
-  if (cnt < n) n = cnt;
+  if ( cnt < n ) n = cnt;
 
   uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
@@ -662,7 +679,7 @@ bool tu_fifo_overflowed(tu_fifo_t* f)
 void tu_fifo_correct_read_pointer(tu_fifo_t* f)
 {
   _ff_lock(f->mutex_rd);
-  _tu_fifo_correct_read_pointer(f, f->wr_idx);
+  _ff_correct_read_index(f, f->wr_idx);
   _ff_unlock(f->mutex_rd);
 }
 
@@ -963,10 +980,9 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
   if (cnt > f->depth)
   {
     _ff_lock(f->mutex_rd);
-    _tu_fifo_correct_read_pointer(f, wr_idx);
+    rd_idx = _ff_correct_read_index(f, wr_idx);
     _ff_unlock(f->mutex_rd);
 
-    rd_idx = f->rd_idx;
     cnt = f->depth;
   }
 
@@ -988,7 +1004,8 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
   info->ptr_lin = &f->buffer[rd_ptr];
 
   // Check if there is a wrap around necessary
-  if (wr_ptr > rd_ptr) {
+  if (wr_ptr > rd_ptr)
+  {
     // Non wrapping case
     info->len_lin  = cnt;
 

From 9e551c9f5cda2bd2bb1f53e34c5010babc534eb9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 7 Jan 2023 19:00:04 +0700
Subject: [PATCH 1385/2085] remove _ff_overflowed() due to lack of use

---
 src/common/tusb_fifo.c | 13 +------------
 1 file changed, 1 insertion(+), 12 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index 22d6e8e55..d5eea83f7 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -331,17 +331,6 @@ uint16_t _ff_count(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
   }
 }
 
-// BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS"
-// Only one overflow is allowed for this function to work e.g. if depth = 100, you must not
-// write more than 2*depth-1 items in one rush without updating write pointer. Otherwise
-// write pointer wraps and you pointer states are messed up. This can only happen if you
-// use DMAs, write functions do not allow such an error.
-TU_ATTR_ALWAYS_INLINE static inline
-bool _ff_overflowed(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
-{
-  return _ff_count(depth, wr_idx, rd_idx) > depth;
-}
-
 // return remaining slot in fifo
 TU_ATTR_ALWAYS_INLINE static inline
 uint16_t _ff_remaining(uint16_t depth, uint16_t wr_idx, uint16_t rd_idx)
@@ -672,7 +661,7 @@ uint16_t tu_fifo_remaining(tu_fifo_t* f)
 /******************************************************************************/
 bool tu_fifo_overflowed(tu_fifo_t* f)
 {
-  return _ff_overflowed(f->depth, f->wr_idx, f->rd_idx);
+  return _ff_count(f->depth, f->wr_idx, f->rd_idx) > f->depth;
 }
 
 // Only use in case tu_fifo_overflow() returned true!

From c84de8f06bb42de78fec22dec8026f3a0c0899cc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 7 Jan 2023 19:40:06 +0700
Subject: [PATCH 1386/2085] minor clean up

---
 src/common/tusb_fifo.c | 100 +++++++++++++++++++++--------------------
 1 file changed, 51 insertions(+), 49 deletions(-)

diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index d5eea83f7..a52c92267 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -97,13 +97,13 @@ bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_si
 // TODO generalize with configurable 1 byte or 4 byte each read
 static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t len)
 {
-  volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf;
+  volatile const uint32_t * reg_rx = (volatile const uint32_t *) app_buf;
 
   // Reading full available 32 bit words from const app address
   uint16_t full_words = len >> 2;
   while(full_words--)
   {
-    tu_unaligned_write32(ff_buf, *rx_fifo);
+    tu_unaligned_write32(ff_buf, *reg_rx);
     ff_buf += 4;
   }
 
@@ -111,7 +111,7 @@ static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t
   uint8_t const bytes_rem = len & 0x03;
   if ( bytes_rem )
   {
-    uint32_t tmp32 = *rx_fifo;
+    uint32_t tmp32 = *reg_rx;
     memcpy(ff_buf, &tmp32, bytes_rem);
   }
 }
@@ -120,24 +120,24 @@ static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t
 // where all data is written to a constant address in full word copies
 static void _ff_pull_const_addr(void * app_buf, const uint8_t * ff_buf, uint16_t len)
 {
-  volatile uint32_t * tx_fifo = (volatile uint32_t *) app_buf;
+  volatile uint32_t * reg_tx = (volatile uint32_t *) app_buf;
 
-  // Pushing full available 32 bit words to const app address
+  // Write full available 32 bit words to const address
   uint16_t full_words = len >> 2;
   while(full_words--)
   {
-    *tx_fifo = tu_unaligned_read32(ff_buf);
+    *reg_tx = tu_unaligned_read32(ff_buf);
     ff_buf += 4;
   }
 
-  // Write the remaining 1-3 bytes into const app address
+  // Write the remaining 1-3 bytes into const address
   uint8_t const bytes_rem = len & 0x03;
   if ( bytes_rem )
   {
     uint32_t tmp32 = 0;
     memcpy(&tmp32, ff_buf, bytes_rem);
 
-    *tx_fifo = tmp32;
+    *reg_tx = tmp32;
   }
 }
 
@@ -148,21 +148,21 @@ static inline void _ff_push(tu_fifo_t* f, void const * app_buf, uint16_t rel)
 }
 
 // send n items to fifo WITHOUT updating write pointer
-static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode)
+static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t wr_ptr, tu_fifo_copy_mode_t copy_mode)
 {
-  uint16_t const nLin = f->depth - rel;
-  uint16_t const nWrap = n - nLin;
+  uint16_t const lin_count = f->depth - wr_ptr;
+  uint16_t const wrap_count = n - lin_count;
 
-  uint16_t nLin_bytes = nLin * f->item_size;
-  uint16_t nWrap_bytes = nWrap * f->item_size;
+  uint16_t lin_bytes = lin_count * f->item_size;
+  uint16_t wrap_bytes = wrap_count * f->item_size;
 
   // current buffer of fifo
-  uint8_t* ff_buf = f->buffer + (rel * f->item_size);
+  uint8_t* ff_buf = f->buffer + (wr_ptr * f->item_size);
 
   switch (copy_mode)
   {
     case TU_FIFO_COPY_INC:
-      if(n <= nLin)
+      if(n <= lin_count)
       {
         // Linear only
         memcpy(ff_buf, app_buf, n*f->item_size);
@@ -172,17 +172,17 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         // Wrap around
 
         // Write data to linear part of buffer
-        memcpy(ff_buf, app_buf, nLin_bytes);
+        memcpy(ff_buf, app_buf, lin_bytes);
 
         // Write data wrapped around
         // TU_ASSERT(nWrap_bytes <= f->depth, );
-        memcpy(f->buffer, ((uint8_t const*) app_buf) + nLin_bytes, nWrap_bytes);
+        memcpy(f->buffer, ((uint8_t const*) app_buf) + lin_bytes, wrap_bytes);
       }
       break;
 
     case TU_FIFO_COPY_CST_FULL_WORDS:
       // Intended for hardware buffers from which it can be read word by word only
-      if(n <= nLin)
+      if(n <= lin_count)
       {
         // Linear only
         _ff_push_const_addr(ff_buf, app_buf, n*f->item_size);
@@ -192,17 +192,18 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         // Wrap around case
 
         // Write full words to linear part of buffer
-        uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC;
+        uint16_t nLin_4n_bytes = lin_bytes & 0xFFFC;
         _ff_push_const_addr(ff_buf, app_buf, nLin_4n_bytes);
         ff_buf += nLin_4n_bytes;
 
         // There could be odd 1-3 bytes before the wrap-around boundary
-        volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf;
-        uint8_t rem = nLin_bytes & 0x03;
+        uint8_t rem = lin_bytes & 0x03;
         if (rem > 0)
         {
-          uint8_t remrem = (uint8_t) tu_min16(nWrap_bytes, 4-rem);
-          nWrap_bytes -= remrem;
+          volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf;
+
+          uint8_t remrem = (uint8_t) tu_min16(wrap_bytes, 4-rem);
+          wrap_bytes -= remrem;
 
           uint32_t tmp32 = *rx_fifo;
           uint8_t * src_u8 = ((uint8_t *) &tmp32);
@@ -220,7 +221,7 @@ static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t
         }
 
         // Write data wrapped part
-        if (nWrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, nWrap_bytes);
+        if (wrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, wrap_bytes);
       }
       break;
   }
@@ -233,21 +234,21 @@ static inline void _ff_pull(tu_fifo_t* f, void * app_buf, uint16_t rel)
 }
 
 // get n items from fifo WITHOUT updating read pointer
-static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode)
+static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rd_ptr, tu_fifo_copy_mode_t copy_mode)
 {
-  uint16_t const nLin = f->depth - rel;
-  uint16_t const nWrap = n - nLin; // only used if wrapped
+  uint16_t const lin_count = f->depth - rd_ptr;
+  uint16_t const wrap_count = n - lin_count; // only used if wrapped
 
-  uint16_t nLin_bytes = nLin * f->item_size;
-  uint16_t nWrap_bytes = nWrap * f->item_size;
+  uint16_t lin_bytes = lin_count * f->item_size;
+  uint16_t wrap_bytes = wrap_count * f->item_size;
 
   // current buffer of fifo
-  uint8_t* ff_buf = f->buffer + (rel * f->item_size);
+  uint8_t* ff_buf = f->buffer + (rd_ptr * f->item_size);
 
   switch (copy_mode)
   {
     case TU_FIFO_COPY_INC:
-      if ( n <= nLin )
+      if ( n <= lin_count )
       {
         // Linear only
         memcpy(app_buf, ff_buf, n*f->item_size);
@@ -257,15 +258,15 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
         // Wrap around
 
         // Read data from linear part of buffer
-        memcpy(app_buf, ff_buf, nLin_bytes);
+        memcpy(app_buf, ff_buf, lin_bytes);
 
         // Read data wrapped part
-        memcpy((uint8_t*) app_buf + nLin_bytes, f->buffer, nWrap_bytes);
+        memcpy((uint8_t*) app_buf + lin_bytes, f->buffer, wrap_bytes);
       }
     break;
 
     case TU_FIFO_COPY_CST_FULL_WORDS:
-      if ( n <= nLin )
+      if ( n <= lin_count )
       {
         // Linear only
         _ff_pull_const_addr(app_buf, ff_buf, n*f->item_size);
@@ -275,17 +276,18 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
         // Wrap around case
 
         // Read full words from linear part of buffer
-        uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC;
-        _ff_pull_const_addr(app_buf, ff_buf, nLin_4n_bytes);
-        ff_buf += nLin_4n_bytes;
+        uint16_t lin_4n_bytes = lin_bytes & 0xFFFC;
+        _ff_pull_const_addr(app_buf, ff_buf, lin_4n_bytes);
+        ff_buf += lin_4n_bytes;
 
         // There could be odd 1-3 bytes before the wrap-around boundary
-        volatile uint32_t * tx_fifo = (volatile uint32_t *) app_buf;
-        uint8_t rem = nLin_bytes & 0x03;
+        uint8_t rem = lin_bytes & 0x03;
         if (rem > 0)
         {
-          uint8_t remrem = (uint8_t) tu_min16(nWrap_bytes, 4-rem);
-          nWrap_bytes -= remrem;
+          volatile uint32_t * reg_tx = (volatile uint32_t *) app_buf;
+
+          uint8_t remrem = (uint8_t) tu_min16(wrap_bytes, 4-rem);
+          wrap_bytes -= remrem;
 
           uint32_t tmp32=0;
           uint8_t * dst_u8 = (uint8_t *)&tmp32;
@@ -297,7 +299,7 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
           ff_buf = f->buffer;
           while(remrem--) *dst_u8++ = *ff_buf++;
 
-          *tx_fifo = tmp32;
+          *reg_tx = tmp32;
         }
         else
         {
@@ -305,7 +307,7 @@ static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu
         }
 
         // Read data wrapped part
-        if (nWrap_bytes > 0) _ff_pull_const_addr(app_buf, ff_buf, nWrap_bytes);
+        if (wrap_bytes > 0) _ff_pull_const_addr(app_buf, ff_buf, wrap_bytes);
       }
     break;
 
@@ -413,6 +415,9 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16
 {
   uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx);
 
+  // nothing to peek
+  if ( cnt == 0 ) return false;
+
   // Check overflow and correct if required
   if ( cnt > f->depth )
   {
@@ -420,9 +425,6 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16
     cnt = f->depth;
   }
 
-  // Skip beginning of buffer
-  if ( cnt == 0 ) return false;
-
   uint16_t rd_ptr = idx2ptr(f->depth, rd_idx);
 
   // Peek data
@@ -437,6 +439,9 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1
 {
   uint16_t cnt = _ff_count(f->depth, wr_idx, rd_idx);
 
+  // nothing to peek
+  if ( cnt == 0 ) return 0;
+
   // Check overflow and correct if required
   if ( cnt > f->depth )
   {
@@ -444,9 +449,6 @@ static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint1
     cnt = f->depth;
   }
 
-  // Skip beginning of buffer
-  if ( cnt == 0 ) return 0;
-
   // Check if we can read something at and after offset - if too less is available we read what remains
   if ( cnt < n ) n = cnt;
 

From a7e1de1e837961b33021a8ae4ca63571fbf1f4a2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 8 Jan 2023 00:02:17 +0700
Subject: [PATCH 1387/2085] temporarily suppress redundant-decls due to
 USART_Printf_Init()

fix codespell
---
 hw/bsp/ch32v307/family.c  | 2 +-
 hw/bsp/ch32v307/family.mk | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
index ea1c252c4..428466ad7 100644
--- a/hw/bsp/ch32v307/family.c
+++ b/hw/bsp/ch32v307/family.c
@@ -85,7 +85,7 @@ void board_init(void) {
   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
   GPIO_Init(GPIOC, &GPIO_InitStructure);
 
-  /* Enable interrupts globaly */
+  /* Enable interrupts globally */
   __enable_irq();
 
   board_delay(2);
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index ef2af26e6..12565016d 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -30,7 +30,10 @@ CFLAGS += \
 	-nostdlib -nostartfiles \
 	-DCFG_TUSB_MCU=OPT_MCU_CH32V307 \
 	-Xlinker --gc-sections \
-    -DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+	-DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+
+# caused by extra void USART_Printf_Init() in debug_uart.h and EVT/EXAME/SRC/DEBUG/debug.h
+CFLAGS += -Wno-error=redundant-decls
 
 LDFLAGS += \
   -Xlinker --gc-sections --specs=nano.specs --specs=nosys.specs

From 57de6016f9470904228f7b8d6dbe467251922757 Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Sun, 8 Jan 2023 11:20:15 +0100
Subject: [PATCH 1388/2085] ip3511 : Fix IAR build.

---
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 34 ++++++++++----------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 9b490c48c..124656307 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -139,7 +139,7 @@ typedef union TU_ATTR_PACKED
     uint32_t stall        : 1 ;
     uint32_t disable      : 1 ;
     uint32_t active       : 1 ;
-  };
+  } cmd_sts;
 }ep_cmd_sts_t;
 
 TU_VERIFY_STATIC( sizeof(ep_cmd_sts_t) == 4, "size is not correct" );
@@ -329,7 +329,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
   // TODO cannot able to STALL Control OUT endpoint !!!!! FIXME try some walk-around
   uint8_t const ep_id = ep_addr2id(ep_addr);
-  _dcd.ep[ep_id][0].stall = 1;
+  _dcd.ep[ep_id][0].cmd_sts.stall = 1;
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
@@ -338,9 +338,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
   uint8_t const ep_id = ep_addr2id(ep_addr);
 
-  _dcd.ep[ep_id][0].stall        = 0;
-  _dcd.ep[ep_id][0].toggle_reset = 1;
-  _dcd.ep[ep_id][0].toggle_mode  = 0;
+  _dcd.ep[ep_id][0].cmd_sts.stall        = 0;
+  _dcd.ep[ep_id][0].cmd_sts.toggle_reset = 1;
+  _dcd.ep[ep_id][0].cmd_sts.toggle_mode  = 0;
 }
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
@@ -349,10 +349,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
 
   // Check if endpoint is available
-  TU_ASSERT( _dcd.ep[ep_id][0].disable && _dcd.ep[ep_id][1].disable );
+  TU_ASSERT( _dcd.ep[ep_id][0].cmd_sts.disable && _dcd.ep[ep_id][1].cmd_sts.disable );
 
   edpt_reset(rhport, ep_id);
-  _dcd.ep[ep_id][0].is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+  _dcd.ep[ep_id][0].cmd_sts.is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
 
   // Enable EP interrupt
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -365,8 +365,8 @@ void dcd_edpt_close_all (uint8_t rhport)
 {
   for (uint8_t ep_id = 0; ep_id < 2*_dcd_controller[rhport].ep_pairs; ++ep_id)
   {
-    _dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
-    _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
+    _dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
+    _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
   }
 }
 
@@ -375,8 +375,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   (void) rhport;
   
   uint8_t ep_id = ep_addr2id(ep_addr);
-  _dcd.ep[ep_id][0].active = _dcd.ep[ep_id][0].active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
-  _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
+  _dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
+  _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
 }
 
 static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
@@ -385,7 +385,7 @@ static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset,
 
   if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
   {
-    nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
+    nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].cmd_sts.is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
     _dcd.ep[ep_id][0].buffer_fs.offset = buf_offset;
     _dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes;
   }else
@@ -397,7 +397,7 @@ static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset,
 
   _dcd.dma[ep_id].nbytes = nbytes;
 
-  _dcd.ep[ep_id][0].active = 1;
+  _dcd.ep[ep_id][0].cmd_sts.active = 1;
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
@@ -431,7 +431,7 @@ static void bus_reset(uint8_t rhport)
   // disable all endpoints as specified by LPC55S69 UM Table 778
   for(uint8_t ep_id = 0; ep_id < 2*MAX_EP_PAIRS; ep_id++)
   {
-    _dcd.ep[ep_id][0].disable = _dcd.ep[ep_id][1].disable = 1;
+    _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
   }
 
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -459,7 +459,7 @@ static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
       if ( ep_id == 0 || ep_id == 1)
       {
         // For control endpoint, we need to manually clear Active bit
-        ep_cs->active = 0;
+        ep_cs->cmd_sts.active = 0;
       }
 
       uint16_t buf_offset;
@@ -556,8 +556,8 @@ void dcd_int_handler(uint8_t rhport)
   if ( tu_bit_test(int_status, 0) && (cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
   {
     // Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
-    _dcd.ep[0][0].active = _dcd.ep[1][0].active = 0;
-    _dcd.ep[0][0].stall = _dcd.ep[1][0].stall = 0;
+    _dcd.ep[0][0].cmd_sts.active = _dcd.ep[1][0].cmd_sts.active = 0;
+    _dcd.ep[0][0].cmd_sts.stall = _dcd.ep[1][0].cmd_sts.stall = 0;
 
     dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
 

From abb95fc4b3529ef49c0c822bfe43048ea55048b6 Mon Sep 17 00:00:00 2001
From: Nathaniel Brough <nathaniel.brough@gmail.com>
Date: Mon, 9 Jan 2023 13:02:06 -0800
Subject: [PATCH 1389/2085] feat(ci): Adds oss-fuzz integration on PRs

---
 .github/workflows/cifuzz.yml | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 .github/workflows/cifuzz.yml

diff --git a/.github/workflows/cifuzz.yml b/.github/workflows/cifuzz.yml
new file mode 100644
index 000000000..7314fd9e6
--- /dev/null
+++ b/.github/workflows/cifuzz.yml
@@ -0,0 +1,33 @@
+name: CIFuzz
+on:
+  pull_request:
+    branches:
+      - master
+    paths:
+      - '**.c'
+      - '**.cc'
+      - '**.cpp'
+      - '**.cxx'
+      - '**.h'
+jobs:
+ Fuzzing:
+   runs-on: ubuntu-latest
+   steps:
+   - name: Build Fuzzers
+     id: build
+     uses: google/oss-fuzz/infra/cifuzz/actions/build_fuzzers@master
+     with:
+       oss-fuzz-project-name: 'tinyusb'
+       language: c++
+   - name: Run Fuzzers
+     uses: google/oss-fuzz/infra/cifuzz/actions/run_fuzzers@master
+     with:
+       oss-fuzz-project-name: 'tinyusb'
+       language: c++
+       fuzz-seconds: 600
+   - name: Upload Crash
+     uses: actions/upload-artifact@v3
+     if: failure() && steps.build.outcome == 'success'
+     with:
+       name: artifacts
+       path: ./out/artifacts

From 9d19ed940e303ea01a685ebba986b24713f5febd Mon Sep 17 00:00:00 2001
From: MasterPhi <admin@hifiphile.com>
Date: Wed, 11 Jan 2023 18:49:15 +0100
Subject: [PATCH 1390/2085] dwc2: fix IAR warnings.

---
 src/portable/synopsys/dwc2/dcd_dwc2.c   | 9 ++++++---
 src/portable/synopsys/dwc2/dwc2_stm32.h | 4 ++--
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index b53735a5e..c6132a1f5 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -529,8 +529,10 @@ void dcd_init (uint8_t rhport)
   dwc2->dcfg |= DCFG_NZLSOHSK;
 
   // Clear all interrupts
-  dwc2->gintsts |= dwc2->gintsts;
-  dwc2->gotgint |= dwc2->gotgint;
+  uint32_t int_mask = dwc2->gintsts;
+  dwc2->gintsts |= int_mask;
+  int_mask = dwc2->gotgint;
+  dwc2->gotgint |= int_mask;
 
   // Required as part of core initialization.
   // TODO: How should mode mismatch be handled? It will cause
@@ -1219,7 +1221,8 @@ void dcd_int_handler(uint8_t rhport)
 {
   dwc2_regs_t *dwc2 = DWC2_REG(rhport);
 
-  uint32_t const int_status = dwc2->gintsts & dwc2->gintmsk;
+  uint32_t const int_mask = dwc2->gintmsk;
+  uint32_t const int_status = dwc2->gintsts & int_mask;
 
   if(int_status & GINTSTS_USBRST)
   {
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index b63d1fcd0..cb455bd90 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -122,13 +122,13 @@ static const dwc2_controller_t _dwc2_controller[] =
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_enable(uint8_t rhport)
 {
-  NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
+  NVIC_EnableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum);
 }
 
 TU_ATTR_ALWAYS_INLINE
 static inline void dwc2_dcd_int_disable (uint8_t rhport)
 {
-  NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
+  NVIC_DisableIRQ((IRQn_Type)_dwc2_controller[rhport].irqnum);
 }
 
 TU_ATTR_ALWAYS_INLINE

From 3cc6cece0783e893d9fadc868f7fb58c81625fe0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Jan 2023 10:25:48 +0700
Subject: [PATCH 1391/2085] add note for openocd with wch, also add
 wch-riscv.cfg

---
 hw/bsp/ch32v307/family.mk                | 18 +++++++++++++++---
 hw/bsp/ch32v307/wch-riscv.cfg            | 15 +++++++++++++++
 src/portable/wch/ch32v307/usb_dc_usbhs.c |  4 ++--
 3 files changed, 32 insertions(+), 5 deletions(-)
 create mode 100644 hw/bsp/ch32v307/wch-riscv.cfg

diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index 12565016d..58542041f 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -30,7 +30,7 @@ CFLAGS += \
 	-nostdlib -nostartfiles \
 	-DCFG_TUSB_MCU=OPT_MCU_CH32V307 \
 	-Xlinker --gc-sections \
-	-DBOARD_DEVICE_RHPORT_SPEED=OPT_MODE_HIGH_SPEED
+	-DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
 
 # caused by extra void USART_Printf_Init() in debug_uart.h and EVT/EXAME/SRC/DEBUG/debug.h
 CFLAGS += -Wno-error=redundant-decls
@@ -51,7 +51,6 @@ SRC_S += \
 
 INC += \
 	src/portable/wch/ch32v307 \
-	$(TOP)/$(BOARD_PATH)/.. \
 	$(TOP)/$(BOARD_PATH) \
 	$(CH32V307_SDK_SRC_TOP)/Peripheral/inc \
 	$(CH32V307_SDK_SRC_TOP)/Debug \
@@ -60,6 +59,19 @@ INC += \
 # For freeRTOS port source
 FREERTOS_PORT = RISC-V
 
+# wch-link is not supported yet in official openOCD yet. We need to either use
+# 1. download openocd as part of mounriver studio http://www.mounriver.com/download or
+# 2. compiled from modified source https://github.com/kprasadvnsi/riscv-openocd-wch
+#
+# Note: For Linux, somehow openocd in mounriver studio does not seem to have wch-link enable, 
+# therefore we need to compile it from source as follows:
+# 	git clone https://github.com/kprasadvnsi/riscv-openocd-wch
+# 	cd riscv-openocd-wch
+#		./bootstrap
+#		./configure CFLAGS="-Wno-error" --enable-wlink
+#		make
+# openocd binaries will be generated in riscv-openocd-wch/src
+
 # flash target ROM bootloader
 flash: $(BUILD)/$(PROJECT).elf
-	openocd -f wch-riscv.cfg  -c init -c halt  -c "program  $<  0x08000000"  -c reset -c exit
+	openocd -f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -c init -c halt -c "program $<" -c reset -c exit
diff --git a/hw/bsp/ch32v307/wch-riscv.cfg b/hw/bsp/ch32v307/wch-riscv.cfg
new file mode 100644
index 000000000..0d24d16ca
--- /dev/null
+++ b/hw/bsp/ch32v307/wch-riscv.cfg
@@ -0,0 +1,15 @@
+#interface wlink
+adapter driver wlink
+wlink_set
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
diff --git a/src/portable/wch/ch32v307/usb_dc_usbhs.c b/src/portable/wch/ch32v307/usb_dc_usbhs.c
index e647389ee..39fd41392 100644
--- a/src/portable/wch/ch32v307/usb_dc_usbhs.c
+++ b/src/portable/wch/ch32v307/usb_dc_usbhs.c
@@ -70,7 +70,7 @@ void dcd_init(uint8_t rhport) {
 
     USBHSD->CONTROL = 0;
 
-#if (BOARD_DEVICE_RHPORT_SPEED == OPT_MODE_HIGH_SPEED)
+#if TUD_OPT_HIGH_SPEED
     USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
 #else
     #error OPT_MODE_FULL_SPEED not currently supported on CH32V307
@@ -383,4 +383,4 @@ void dcd_int_handler(uint8_t rhport) {
     }
 }
 
-#endif
\ No newline at end of file
+#endif

From e61d4aefe6b9fbab862e7c440ff9ff25ebb5092c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Jan 2023 12:08:56 +0700
Subject: [PATCH 1392/2085] rename driver with dcd_ to be consitent with other
 ports

---
 hw/bsp/ch32v307/family.mk                     | 22 ++++++++-----------
 ...{usb_ch32_usbhs_reg.h => ch32_usbhs_reg.h} |  0
 .../ch32v307/{usb_dc_usbhs.c => dcd_usbhs.c}  |  2 +-
 3 files changed, 10 insertions(+), 14 deletions(-)
 rename src/portable/wch/ch32v307/{usb_ch32_usbhs_reg.h => ch32_usbhs_reg.h} (100%)
 rename src/portable/wch/ch32v307/{usb_dc_usbhs.c => dcd_usbhs.c} (99%)

diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index 58542041f..ffc992f21 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -10,8 +10,6 @@ DEPS_SUBMODULES += $(CH32V307_SDK)
 
 # WCH-SDK paths
 CH32V307_SDK_SRC = $(CH32V307_SDK)/EVT/EXAM/SRC
-CH32V307_SDK_SRC_TOP = $(TOP)/$(CH32V307_SDK_SRC)
-CH32V307_STARTUP_ASM = $(CH32V307_SDK_SRC)/Startup
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
@@ -39,22 +37,20 @@ LDFLAGS += \
   -Xlinker --gc-sections --specs=nano.specs --specs=nosys.specs
 
 SRC_C += \
-	src/portable/wch/ch32v307/usb_dc_usbhs.c \
-	$(CH32V307_SDK_SRC_TOP)/Core/core_riscv.c \
-	$(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_gpio.c \
-	$(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_misc.c \
-	$(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_rcc.c \
-	$(CH32V307_SDK_SRC_TOP)/Peripheral/src/ch32v30x_usart.c 
+	src/portable/wch/ch32v307/dcd_usbhs.c \
+	$(CH32V307_SDK_SRC)/Core/core_riscv.c \
+	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_gpio.c \
+	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_misc.c \
+	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_rcc.c \
+	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_usart.c 
 	
 SRC_S += \
-	$(CH32V307_STARTUP_ASM)/startup_ch32v30x_D8C.S 
+	$(CH32V307_SDK_SRC)/Startup/startup_ch32v30x_D8C.S 
 
 INC += \
-	src/portable/wch/ch32v307 \
 	$(TOP)/$(BOARD_PATH) \
-	$(CH32V307_SDK_SRC_TOP)/Peripheral/inc \
-	$(CH32V307_SDK_SRC_TOP)/Debug \
-	$(CH32V307_SDK_SRC_TOP)
+	$(TOP)/$(CH32V307_SDK_SRC)/Peripheral/inc \
+	$(TOP)/$(CH32V307_SDK_SRC)/Debug
 
 # For freeRTOS port source
 FREERTOS_PORT = RISC-V
diff --git a/src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h b/src/portable/wch/ch32v307/ch32_usbhs_reg.h
similarity index 100%
rename from src/portable/wch/ch32v307/usb_ch32_usbhs_reg.h
rename to src/portable/wch/ch32v307/ch32_usbhs_reg.h
diff --git a/src/portable/wch/ch32v307/usb_dc_usbhs.c b/src/portable/wch/ch32v307/dcd_usbhs.c
similarity index 99%
rename from src/portable/wch/ch32v307/usb_dc_usbhs.c
rename to src/portable/wch/ch32v307/dcd_usbhs.c
index 39fd41392..7a0dcfc23 100644
--- a/src/portable/wch/ch32v307/usb_dc_usbhs.c
+++ b/src/portable/wch/ch32v307/dcd_usbhs.c
@@ -29,7 +29,7 @@
 #if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307)
 #include "device/dcd.h"
 
-#include "usb_ch32_usbhs_reg.h"
+#include "ch32_usbhs_reg.h"
 #include "core_riscv.h"
 
 // Max number of bi-directional endpoints including EP0

From 658897cf4e3058aee66f65c17a152ef65b1671c1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Jan 2023 12:30:18 +0700
Subject: [PATCH 1393/2085] fix redundant-decls warnings with
 USART_Printf_Init()

---
 hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c | 2 +-
 hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h | 2 +-
 hw/bsp/ch32v307/ch32v30x_it.h                        | 2 +-
 hw/bsp/ch32v307/family.c                             | 2 +-
 hw/bsp/ch32v307/family.mk                            | 6 +-----
 5 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c
index 416782d0e..ad8b32957 100644
--- a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c
+++ b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c
@@ -75,7 +75,7 @@ void uart_sync(void)
 }
 
 
-void USART_Printf_Init(uint32_t baudrate)
+void usart_printf_init(uint32_t baudrate)
 {
     GPIO_InitTypeDef  GPIO_InitStructure;
     USART_InitTypeDef USART_InitStructure;
diff --git a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h
index 4348438bb..a7e070585 100644
--- a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h
+++ b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h
@@ -28,4 +28,4 @@
 
 void uart_write(char c);
 void uart_sync(void);
-void USART_Printf_Init(uint32_t baudrate);
+void usart_printf_init(uint32_t baudrate);
diff --git a/hw/bsp/ch32v307/ch32v30x_it.h b/hw/bsp/ch32v307/ch32v30x_it.h
index 6475c5f11..42f285edf 100644
--- a/hw/bsp/ch32v307/ch32v30x_it.h
+++ b/hw/bsp/ch32v307/ch32v30x_it.h
@@ -10,7 +10,7 @@
 #ifndef __CH32V30x_IT_H
 #define __CH32V30x_IT_H
 
-#include "debug.h"
+// #include "debug.h"
 
 
 #endif /* __CH32V30x_IT_H */
diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
index 428466ad7..0260918ab 100644
--- a/hw/bsp/ch32v307/family.c
+++ b/hw/bsp/ch32v307/family.c
@@ -68,7 +68,7 @@ void board_init(void) {
   SysTick_Config(SystemCoreClock / 1000);
 #endif
 
-	USART_Printf_Init(115200);
+	usart_printf_init(115200);
 
   RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
   RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index ffc992f21..93370fc57 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -30,9 +30,6 @@ CFLAGS += \
 	-Xlinker --gc-sections \
 	-DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
 
-# caused by extra void USART_Printf_Init() in debug_uart.h and EVT/EXAME/SRC/DEBUG/debug.h
-CFLAGS += -Wno-error=redundant-decls
-
 LDFLAGS += \
   -Xlinker --gc-sections --specs=nano.specs --specs=nosys.specs
 
@@ -49,8 +46,7 @@ SRC_S += \
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(CH32V307_SDK_SRC)/Peripheral/inc \
-	$(TOP)/$(CH32V307_SDK_SRC)/Debug
+	$(TOP)/$(CH32V307_SDK_SRC)/Peripheral/inc
 
 # For freeRTOS port source
 FREERTOS_PORT = RISC-V

From e6a3cfb3506fdd908c47ad0cf63fc67a1ef2455c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Jan 2023 13:12:37 +0700
Subject: [PATCH 1394/2085] rename link file

---
 hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk | 4 +---
 hw/bsp/ch32v307/{Link.ld => ch32v307.ld}         | 0
 2 files changed, 1 insertion(+), 3 deletions(-)
 rename hw/bsp/ch32v307/{Link.ld => ch32v307.ld} (100%)

diff --git a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk
index a7c359588..4e91d8938 100644
--- a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk
+++ b/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk
@@ -1,3 +1 @@
-LINKER_SCRIPTS = $(BOARD_PATH)/../..
-
-LD_FILE = $(LINKER_SCRIPTS)/Link.ld # CH32V307
+LD_FILE = $(FAMILY_PATH)/ch32v307.ld
diff --git a/hw/bsp/ch32v307/Link.ld b/hw/bsp/ch32v307/ch32v307.ld
similarity index 100%
rename from hw/bsp/ch32v307/Link.ld
rename to hw/bsp/ch32v307/ch32v307.ld

From 65f7a8006cdeae74e5258657250ae7568b607cd1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Jan 2023 13:31:36 +0700
Subject: [PATCH 1395/2085] rename board to lower case ch32v307v-r1-1v0

---
 .../boards/{CH32V307V-R1-1v0 => ch32v307v-r1-1v0}/board.mk      | 0
 .../boards/{CH32V307V-R1-1v0 => ch32v307v-r1-1v0}/debug_uart.c  | 0
 .../boards/{CH32V307V-R1-1v0 => ch32v307v-r1-1v0}/debug_uart.h  | 0
 hw/bsp/ch32v307/family.mk                                       | 2 +-
 4 files changed, 1 insertion(+), 1 deletion(-)
 rename hw/bsp/ch32v307/boards/{CH32V307V-R1-1v0 => ch32v307v-r1-1v0}/board.mk (100%)
 rename hw/bsp/ch32v307/boards/{CH32V307V-R1-1v0 => ch32v307v-r1-1v0}/debug_uart.c (100%)
 rename hw/bsp/ch32v307/boards/{CH32V307V-R1-1v0 => ch32v307v-r1-1v0}/debug_uart.h (100%)

diff --git a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.mk
similarity index 100%
rename from hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/board.mk
rename to hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.mk
diff --git a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
similarity index 100%
rename from hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.c
rename to hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
diff --git a/hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.h
similarity index 100%
rename from hw/bsp/ch32v307/boards/CH32V307V-R1-1v0/debug_uart.h
rename to hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.h
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index 93370fc57..49e496853 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -66,4 +66,4 @@ FREERTOS_PORT = RISC-V
 
 # flash target ROM bootloader
 flash: $(BUILD)/$(PROJECT).elf
-	openocd -f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -c init -c halt -c "program $<" -c reset -c exit
+	openocd -f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -c init -c halt -c "program $<" -c wlink_reset_resume -c exit

From f05f81e8b3d7ac6b061eaab20fc456fbed89d690 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Jan 2023 15:19:26 +0700
Subject: [PATCH 1396/2085] add button support

---
 .../ch32v307/boards/ch32v307v-r1-1v0/board.h  | 50 +++++++++++++
 hw/bsp/ch32v307/family.c                      | 71 +++++++++++--------
 2 files changed, 92 insertions(+), 29 deletions(-)
 create mode 100644 hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h

diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h
new file mode 100644
index 000000000..0eab34916
--- /dev/null
+++ b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h
@@ -0,0 +1,50 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED: need to wire pin LED1 to PC0 in the J3 header
+#define LED_PORT              GPIOC
+#define LED_PIN               GPIO_Pin_0
+#define LED_STATE_ON          0
+#define LED_CLOCK_EN()        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE)
+
+// Button: need to wire pin KEY to PC1 in the J3 header
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_Pin_1
+#define BUTTON_STATE_ACTIVE   0
+#define BUTTON_CLOCK_EN()     do { } while(0) // same as LED clock, no need to do anything
+
+// TODO UART port
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
index 0260918ab..65519ce50 100644
--- a/hw/bsp/ch32v307/family.c
+++ b/hw/bsp/ch32v307/family.c
@@ -28,19 +28,22 @@
 #include "debug_uart.h"
 #include "ch32v30x.h"
 
-#include "../board.h"
+#include "bsp/board.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
 
-void USBHS_IRQHandler(void) __attribute__((naked));
-void USBHS_IRQHandler(void) { 
-        __asm volatile ("call USBHS_IRQHandler_impl; mret");
+void USBHS_IRQHandler (void) __attribute__((naked));
+void USBHS_IRQHandler (void)
+{
+  __asm volatile ("call USBHS_IRQHandler_impl; mret");
 }
 
-__attribute__ ((used)) void USBHS_IRQHandler_impl(void) { 
-  tud_int_handler(0); 
+__attribute__ ((used)) void USBHS_IRQHandler_impl (void)
+{
+  tud_int_handler(0);
 }
 
 //--------------------------------------------------------------------+
@@ -49,13 +52,13 @@ __attribute__ ((used)) void USBHS_IRQHandler_impl(void) {
 
 uint32_t SysTick_Config(uint32_t ticks)
 {
-    NVIC_EnableIRQ(SysTicK_IRQn);
-    SysTick->CTLR=0;
-    SysTick->SR=0;
-    SysTick->CNT=0;
-    SysTick->CMP=ticks-1;
-    SysTick->CTLR=0xF;
-    return 0;
+  NVIC_EnableIRQ(SysTicK_IRQn);
+  SysTick->CTLR=0;
+  SysTick->SR=0;
+  SysTick->CNT=0;
+  SysTick->CMP=ticks-1;
+  SysTick->CTLR=0xF;
+  return 0;
 }
 
 void board_init(void) {
@@ -63,7 +66,6 @@ void board_init(void) {
   /* Disable interrupts during init */
   __disable_irq();
 
-
 #if CFG_TUSB_OS == OPT_OS_NONE
   SysTick_Config(SystemCoreClock / 1000);
 #endif
@@ -79,11 +81,19 @@ void board_init(void) {
 
   GPIO_InitTypeDef GPIO_InitStructure = {0};
 
-  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
-  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
+  // LED
+  LED_CLOCK_EN();
+  GPIO_InitStructure.GPIO_Pin = LED_PIN;
   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_Init(GPIOC, &GPIO_InitStructure);
+  GPIO_Init(LED_PORT, &GPIO_InitStructure);
+
+  // Button
+  BUTTON_CLOCK_EN();
+  GPIO_InitStructure.GPIO_Pin = BUTTON_PIN;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_Init(BUTTON_PORT, &GPIO_InitStructure);
 
   /* Enable interrupts globally */
   __enable_irq();
@@ -114,26 +124,29 @@ uint32_t board_millis(void) { return system_ticks; }
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state) {
-  (void) state;
-
-  GPIO_WriteBit(GPIOC, GPIO_Pin_0, state);
+void board_led_write (bool state)
+{
+  GPIO_WriteBit(LED_PORT, LED_PIN, state);
 }
 
-uint32_t board_button_read(void) {
-  return false;
+uint32_t board_button_read (void)
+{
+  return BUTTON_STATE_ACTIVE == GPIO_ReadInputDataBit(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len) {
-  (void)buf;
-  (void)len;
+int board_uart_read (uint8_t *buf, int len)
+{
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const* buf, int len) {
+int board_uart_write (void const *buf, int len)
+{
   int txsize = len;
-  while (txsize--) {
-    uart_write(*(uint8_t const*)buf);
+  while ( txsize-- )
+  {
+    uart_write(*(uint8_t const*) buf);
     buf++;
   }
   return len;

From 3cf21c66b6ef19c6dd648f952e8679a654b15803 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Jan 2023 15:26:48 +0700
Subject: [PATCH 1397/2085] add dcd_remote_wakeup() stub

---
 src/portable/wch/ch32v307/dcd_usbhs.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/portable/wch/ch32v307/dcd_usbhs.c b/src/portable/wch/ch32v307/dcd_usbhs.c
index 7a0dcfc23..b7a79e166 100644
--- a/src/portable/wch/ch32v307/dcd_usbhs.c
+++ b/src/portable/wch/ch32v307/dcd_usbhs.c
@@ -130,6 +130,11 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
     dcd_edpt_xfer(rhport, 0x80, NULL, 0);
 }
 
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+}
+
 void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
     (void)rhport;
 

From 160d64b00a1b4ad46cd61cba3b649a07901d3c65 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Jan 2023 15:34:29 +0700
Subject: [PATCH 1398/2085] minor clean up. ch32v307 has issue with uart LOG=2
 (skipping characters)

---
 .../boards/ch32v307v-r1-1v0/debug_uart.c      | 48 +++++++++----------
 hw/bsp/ch32v307/family.c                      | 17 ++++---
 hw/bsp/ch32v307/family.mk                     |  5 --
 3 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
index ad8b32957..45fc9e3aa 100644
--- a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
+++ b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
@@ -77,34 +77,34 @@ void uart_sync(void)
 
 void usart_printf_init(uint32_t baudrate)
 {
-    GPIO_InitTypeDef  GPIO_InitStructure;
-    USART_InitTypeDef USART_InitStructure;
+  GPIO_InitTypeDef GPIO_InitStructure;
+  USART_InitTypeDef USART_InitStructure;
 
-	tx_produce = 0;
-	tx_consume = 0;
+  tx_produce = 0;
+  tx_consume = 0;
 
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
 
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
-    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-    GPIO_Init(GPIOA, &GPIO_InitStructure);
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
 
-    USART_InitStructure.USART_BaudRate = baudrate;
-    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-    USART_InitStructure.USART_StopBits = USART_StopBits_1;
-    USART_InitStructure.USART_Parity = USART_Parity_No;
-    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-    USART_InitStructure.USART_Mode = USART_Mode_Tx;
+  USART_InitStructure.USART_BaudRate = baudrate;
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_No;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Tx;
 
-    USART_Init(USART1, &USART_InitStructure);
-    USART_ITConfig(USART1, USART_IT_TC, ENABLE);
-    USART_Cmd(USART1, ENABLE);
+  USART_Init(USART1, &USART_InitStructure);
+  USART_ITConfig(USART1, USART_IT_TC, ENABLE);
+  USART_Cmd(USART1, ENABLE);
 
-    NVIC_InitTypeDef  NVIC_InitStructure = {0};
-    NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-    NVIC_Init(&NVIC_InitStructure);
+  NVIC_InitTypeDef NVIC_InitStructure = { 0 };
+  NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
+  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
+  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+  NVIC_Init(&NVIC_InitStructure);
 }
diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
index 65519ce50..d5602c7b4 100644
--- a/hw/bsp/ch32v307/family.c
+++ b/hw/bsp/ch32v307/family.c
@@ -106,17 +106,22 @@ void board_init(void) {
 volatile uint32_t system_ticks = 0;
 
 /* Small workaround to support HW stack save/restore */
-void SysTick_Handler(void) __attribute__((naked));
-void SysTick_Handler(void) { 
-      __asm volatile ("call SysTick_Handler_impl; mret");
+void SysTick_Handler (void) __attribute__((naked));
+void SysTick_Handler (void)
+{
+  __asm volatile ("call SysTick_Handler_impl; mret");
 }
 
-__attribute__((used)) void SysTick_Handler_impl(void) { 
-  SysTick->SR=0;
+__attribute__((used)) void SysTick_Handler_impl (void)
+{
+  SysTick->SR = 0;
   system_ticks++;
 }
 
-uint32_t board_millis(void) { return system_ticks; }
+uint32_t board_millis (void)
+{
+  return system_ticks;
+}
 
 #endif
 
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index 49e496853..15f6724a8 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -13,8 +13,6 @@ CH32V307_SDK_SRC = $(CH32V307_SDK)/EVT/EXAM/SRC
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
-SKIP_NANOLIB = 1
-
 CFLAGS += \
 	-flto \
 	-march=rv32imac \
@@ -30,9 +28,6 @@ CFLAGS += \
 	-Xlinker --gc-sections \
 	-DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
 
-LDFLAGS += \
-  -Xlinker --gc-sections --specs=nano.specs --specs=nosys.specs
-
 SRC_C += \
 	src/portable/wch/ch32v307/dcd_usbhs.c \
 	$(CH32V307_SDK_SRC)/Core/core_riscv.c \

From b1021d53f3617491656c50f6a1cb2c21da029f6a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 12 Jan 2023 15:38:18 +0700
Subject: [PATCH 1399/2085] add TUP_RHPORT_HIGHSPEED for ch32v307

---
 src/common/tusb_mcu.h | 2 +-
 src/tusb_option.h     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index b37ce9a34..0b10c5118 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -278,7 +278,7 @@
 //------------- WCH -------------//
 #elif TU_CHECK_MCU(OPT_MCU_CH32V307)
   #define TUP_DCD_ENDPOINT_MAX    16
-
+  #define TUP_RHPORT_HIGHSPEED    1
 #endif
 
 //--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 92fbbd33f..67377b7ec 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -161,7 +161,7 @@ typedef int make_iso_compilers_happy;
 #define OPT_MCU_F1C100S          2100 ///< Allwinner F1C100s family
 
 // WCH
-#define OPT_MCU_CH32V307        2200 ///< WCH CH32V307 config
+#define OPT_MCU_CH32V307         2200 ///< WCH CH32V307
 
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input

From 546dd6038c57e1a1db2a6711e64bddd869f5667a Mon Sep 17 00:00:00 2001
From: Malik Enes Safak <e.maliksafak@gmail.com>
Date: Fri, 13 Jan 2023 18:28:10 +0300
Subject: [PATCH 1400/2085] examples/uac2: Fix mute and volume array lengths

---
 examples/device/uac2_headset/src/main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 003dc2a74..01707d51b 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -79,8 +79,8 @@ static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
 
 // Audio controls
 // Current states
-int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];       // +1 for master channel 0
-int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1];    // +1 for master channel 0
+int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];       // +1 for master channel 0
+int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];    // +1 for master channel 0
 
 // Buffer for microphone data
 int32_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ / 4];

From 2e47210c1af88b88b6f2d92fe2b6d08117041363 Mon Sep 17 00:00:00 2001
From: Nathaniel Brough <nathaniel.brough@gmail.com>
Date: Fri, 13 Jan 2023 13:37:55 -0800
Subject: [PATCH 1401/2085] fix: Replace device calls to memcpy with
 tu_memcpy_s

Introduces a new function tu_memcpy_s, which is effectively
a backport of memcpy_s. The change also refactors calls
to memcpy over to the more secure tu_memcpy_s.
---
 src/class/audio/audio_device.c |  7 ++-----
 src/class/dfu/dfu_rt_device.c  |  2 +-
 src/class/hid/hid_device.c     | 18 +++++++-----------
 src/class/midi/midi_device.c   |  2 +-
 src/class/msc/msc_device.c     | 10 +++++-----
 src/common/tusb_common.h       |  8 ++++++++
 src/device/dcd.h               |  2 +-
 src/device/usbd_control.c      |  4 +++-
 src/tusb.c                     | 23 ++++++++++++++++++++++-
 9 files changed, 50 insertions(+), 26 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 698fba566..81df95139 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -823,10 +823,7 @@ uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint1
   // We write directly into the EP's buffer - abort if previous transfer not complete
   TU_VERIFY(!usbd_edpt_busy(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int_ctr));
 
-  // Check length
-  TU_VERIFY(len <= CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE);
-
-  memcpy(_audiod_fct[func_id].ep_int_ctr_buf, buffer, len);
+  TU_VERIFY(tu_memcpy_s(_audiod_fct[func_id].ep_int_ctr_buf, CFG_TUD_AUDIO_INT_CTR_EP_IN_SW_BUFFER_SIZE,  buffer, len)==0);
 
   // Schedule transmit
   TU_VERIFY(usbd_edpt_xfer(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int_ctr, _audiod_fct[func_id].ep_int_ctr_buf, len));
@@ -2202,7 +2199,7 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req
   if (len > _audiod_fct[func_id].ctrl_buf_sz) len = _audiod_fct[func_id].ctrl_buf_sz;
 
   // Copy into buffer
-  memcpy((void *)_audiod_fct[func_id].ctrl_buf, data, (size_t)len);
+  TU_VERIFY(tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, sizeof(_audiod_fct[func_id].ctrl_buf), data, (size_t)len)==0);
 
   // Schedule transmit
   return tud_control_xfer(rhport, p_request, (void*)_audiod_fct[func_id].ctrl_buf, len);
diff --git a/src/class/dfu/dfu_rt_device.c b/src/class/dfu/dfu_rt_device.c
index b9cd6096b..7b77b3f8f 100644
--- a/src/class/dfu/dfu_rt_device.c
+++ b/src/class/dfu/dfu_rt_device.c
@@ -110,7 +110,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
       TU_LOG2("  DFU RT Request: GETSTATUS\r\n");
       dfu_status_response_t resp;
       // Status = OK, Poll timeout is ignored during RT, State = APP_IDLE, IString = 0
-      memset(&resp, 0x00, sizeof(dfu_status_response_t));
+      TU_VERIFY(tu_memset_s(&resp, sizeof(resp), 0x00, sizeof(resp))==0);
       tud_control_xfer(rhport, request, &resp, sizeof(dfu_status_response_t));
     }
     break;
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 8077e4deb..40654eef9 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -92,16 +92,12 @@ bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, u
   // prepare data
   if (report_id)
   {
-    len = tu_min16(len, CFG_TUD_HID_EP_BUFSIZE-1);
-
     p_hid->epin_buf[0] = report_id;
-    memcpy(p_hid->epin_buf+1, report, len);
+    TU_VERIFY(tu_memcpy_s(p_hid->epin_buf+1, CFG_TUD_HID_EP_BUFSIZE-1, report, len)==0);
     len++;
   }else
   {
-    // If report id = 0, skip ID field
-    len = tu_min16(len, CFG_TUD_HID_EP_BUFSIZE);
-    memcpy(p_hid->epin_buf, report, len);
+    TU_VERIFY(tu_memcpy_s(p_hid->epin_buf, CFG_TUD_HID_EP_BUFSIZE, report, len)==0);
   }
 
   return usbd_edpt_xfer(rhport, p_hid->ep_in, p_hid->epin_buf, len);
@@ -126,7 +122,7 @@ bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modi
 
   if ( keycode )
   {
-    memcpy(report.keycode, keycode, 6);
+    TU_VERIFY(tu_memcpy_s(report.keycode, sizeof(report.keycode), keycode, sizeof(report.keycode))==0);
   }else
   {
     tu_memclr(report.keycode, 6);
@@ -151,8 +147,7 @@ bool tud_hid_n_mouse_report(uint8_t instance, uint8_t report_id,
 }
 
 bool tud_hid_n_gamepad_report(uint8_t instance, uint8_t report_id,
-                              int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons)
-{
+                              int8_t x, int8_t y, int8_t z, int8_t rz, int8_t rx, int8_t ry, uint8_t hat, uint32_t buttons) {
   hid_gamepad_report_t report =
   {
     .x       = x,
@@ -183,11 +178,12 @@ void hidd_reset(uint8_t rhport)
 }
 
 uint16_t hidd_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len)
-{
+ {
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass, 0);
 
   // len = interface + hid + n*endpoints
-  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
+  uint16_t const drv_len =
+      (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
                                        desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
   TU_ASSERT(max_len >= drv_len, 0);
 
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index de41706e8..0b52be181 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -182,7 +182,7 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, ui
     uint8_t const count = (uint8_t) tu_min32(stream->total - stream->index, bufsize);
 
     // Skip the header (1st byte) in the buffer
-    memcpy(buf8, stream->buffer + 1 + stream->index, count);
+    TU_VERIFY(tu_memcpy_s(buf8, bufsize, stream->buffer + 1 + stream->index, count)==0);
 
     total_read += count;
     stream->index += count;
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 00b0a1d06..ed4a3e86c 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -707,7 +707,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         read_capa10.block_size = tu_htonl(block_size);
 
         resplen = sizeof(read_capa10);
-        memcpy(buffer, &read_capa10, (size_t) resplen);
+        TU_VERIFY(tu_memcpy_s(buffer, bufsize, &read_capa10, (size_t) resplen));
       }
     }
     break;
@@ -741,7 +741,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         read_fmt_capa.block_size_u16 = tu_htons(block_size);
 
         resplen = sizeof(read_fmt_capa);
-        memcpy(buffer, &read_fmt_capa, (size_t) resplen);
+        TU_VERIFY(tu_memcpy_s(buffer, bufsize, &read_fmt_capa, (size_t) resplen)==0);
       }
     }
     break;
@@ -764,7 +764,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       tud_msc_inquiry_cb(lun, inquiry_rsp.vendor_id, inquiry_rsp.product_id, inquiry_rsp.product_rev);
 
       resplen = sizeof(inquiry_rsp);
-      memcpy(buffer, &inquiry_rsp, (size_t) resplen);
+      TU_VERIFY(tu_memcpy_s(buffer, bufsize, &inquiry_rsp, (size_t) resplen)==0);
     }
     break;
 
@@ -788,7 +788,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       mode_resp.write_protected = !writable;
 
       resplen = sizeof(mode_resp);
-      memcpy(buffer, &mode_resp, (size_t) resplen);
+      TU_VERIFY(tu_memcpy_s(buffer, bufsize, &mode_resp, (size_t) resplen)==0);
     }
     break;
 
@@ -806,7 +806,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       sense_rsp.add_sense_qualifier = p_msc->add_sense_qualifier;
 
       resplen = sizeof(sense_rsp);
-      memcpy(buffer, &sense_rsp, (size_t) resplen);
+      TU_VERIFY(tu_memcpy_s(buffer, bufsize, &sense_rsp, (size_t) resplen)==0);
 
       // request sense callback could overwrite the sense data
       if (tud_msc_request_sense_cb)
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index b1ee40a1a..78fdcfe36 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -83,6 +83,14 @@
 #define tu_memclr(buffer, size)  memset((buffer), 0, (size))
 #define tu_varclr(_var)          tu_memclr(_var, sizeof(*(_var)))
 
+// This is a backport of memset_s from c11
+int32_t tu_memset_s(void *dest, size_t destsz, int ch, size_t count); 
+
+// This is a backport of memcpy_s from c11
+int32_t tu_memcpy_s(void *dest, size_t destsz,
+                  const void * src, size_t count );
+
+
 //------------- Bytes -------------//
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0)
 {
diff --git a/src/device/dcd.h b/src/device/dcd.h
index c1780f656..3a7e6c5df 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -193,7 +193,7 @@ TU_ATTR_ALWAYS_INLINE static inline  void dcd_event_bus_reset (uint8_t rhport, t
 TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr)
 {
   dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED };
-  memcpy(&event.setup_received, setup, 8);
+  memcpy(&event.setup_received, setup, sizeof(tusb_control_request_t));
 
   dcd_event_handler(&event, in_isr);
 }
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 0995ef669..ce4ddab66 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -93,7 +93,9 @@ static bool _data_stage_xact(uint8_t rhport)
   if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN )
   {
     ep_addr = EDPT_CTRL_IN;
-    if ( xact_len ) memcpy(_usbd_ctrl_buf, _ctrl_xfer.buffer, xact_len);
+    if ( xact_len ) {
+      TU_VERIFY(tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)==0);
+    }
   }
 
   return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _usbd_ctrl_buf : NULL, xact_len);
diff --git a/src/tusb.c b/src/tusb.c
index a5c820b8d..c918b0248 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -24,6 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
+#include "common/tusb_common.h"
 #include "tusb_option.h"
 
 #if CFG_TUH_ENABLED || CFG_TUD_ENABLED
@@ -460,7 +461,7 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
       tu_printf("%04X: ", 16*i/item_per_line);
     }
 
-    memcpy(&value, buf8, size);
+    tu_memcpy_s(&value, sizeof(value), buf8, size);
     buf8 += size;
 
     tu_printf(" ");
@@ -486,3 +487,23 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
 #endif
 
 #endif // host or device enabled
+
+//--------------------------------------------------------------------+
+// Common
+//--------------------------------------------------------------------+
+
+int32_t tu_memset_s(void *dest, size_t destsz, int ch, size_t count) {
+  if (count > destsz) {
+    return -1;
+  }
+  memset(dest, ch, count);
+  return 0;
+}
+
+int32_t tu_memcpy_s(void *dest, size_t destsz, const void *src, size_t count) {
+  if (count > destsz) {
+    return -1;
+  }
+  memcpy(dest, src, count);
+  return 0;
+}
\ No newline at end of file

From 3fee8b402e3efefc341a0c1ce0474deb748858b2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Jan 2023 16:20:04 +0700
Subject: [PATCH 1402/2085] update makefile to support iar build starting with
 stm32f070

---
 examples/make.mk                              |  37 ++++--
 examples/rules.mk                             | 124 +++++++++++++-----
 .../stm32f0/boards/stm32f070rbnucleo/board.mk |   6 +-
 hw/bsp/stm32f0/family.c                       |   2 +-
 hw/bsp/stm32f0/family.mk                      |  17 ++-
 5 files changed, 135 insertions(+), 51 deletions(-)

diff --git a/examples/make.mk b/examples/make.mk
index 73a39a8fe..dd7a5cf4e 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -49,14 +49,31 @@ endif
 #-------------- Cross Compiler  ------------
 # Can be set by board, default to ARM GCC
 CROSS_COMPILE ?= arm-none-eabi-
+
 # Allow for -Os to be changed by board makefiles in case -Os is not allowed
 CFLAGS_OPTIMIZED ?= -Os
 
-CC = $(CROSS_COMPILE)gcc
-CXX = $(CROSS_COMPILE)g++
-GDB = $(CROSS_COMPILE)gdb
-OBJCOPY = $(CROSS_COMPILE)objcopy
-SIZE = $(CROSS_COMPILE)size
+ifeq ($(CC),iccarm)
+USE_IAR = 1
+endif
+
+ifdef USE_IAR
+  AS = iasmarm
+  LD = ilinkarm
+  OBJCOPY = ielftool
+  SIZE = echo "size not available for IAR"
+
+else
+  CC = $(CROSS_COMPILE)gcc
+  CXX = $(CROSS_COMPILE)g++
+  AS = $(CC) -x assembler-with-cpp
+  LD = $(CC)
+  
+  GDB = $(CROSS_COMPILE)gdb
+  OBJCOPY = $(CROSS_COMPILE)objcopy
+  SIZE = $(CROSS_COMPILE)size
+endif
+
 MKDIR = mkdir
 
 ifeq ($(CMDEXE),1)
@@ -78,8 +95,8 @@ SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(BOARD_PATH)/*.c))
 
 INC   += $(TOP)/$(FAMILY_PATH)
 
-# Compiler Flags
-CFLAGS += \
+# GCC Compiler Flags
+GCC_CFLAGS += \
   -ggdb \
   -fdata-sections \
   -ffunction-sections \
@@ -110,13 +127,13 @@ CFLAGS += \
 
 # conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion
 #  -Wconversion
-  
+
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
-  CFLAGS += -O0
+  GCC_CFLAGS += -O0
   NO_LTO = 1
 else
-  CFLAGS += $(CFLAGS_OPTIMIZED)
+  GCC_CFLAGS += $(CFLAGS_OPTIMIZED)
 endif
 
 # Log level is mapped to TUSB DEBUG option
diff --git a/examples/rules.mk b/examples/rules.mk
index c3134056a..2c4df85ba 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -46,31 +46,34 @@ INC += $(TOP)/src
 
 CFLAGS += $(addprefix -I,$(INC))
 
+ifdef USE_IAR
+
+IAR_CFLAGS += $(CFLAGS) -e --debug
+IAR_LDFLAGS += --config $(TOP)/$(IAR_LD_FILE)
+
+else
+
+CFLAGS += $(GCC_CFLAGS)
+
 # LTO makes it difficult to analyze map file for optimizing size purpose
 # We will run this option in ci
 ifeq ($(NO_LTO),1)
 CFLAGS := $(filter-out -flto,$(CFLAGS))
 endif
 
-ifneq ($(LD_FILE),)
-LDFLAGS_LD_FILE ?= -Wl,-T,$(TOP)/$(LD_FILE)
+LDFLAGS += $(CFLAGS) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections
+
+ifdef LD_FILE
+LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE)
 endif
 
-LDFLAGS += $(CFLAGS) $(LDFLAGS_LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections
 ifneq ($(SKIP_NANOLIB), 1)
 LDFLAGS += -specs=nosys.specs -specs=nano.specs
 endif
 
 ASFLAGS += $(CFLAGS)
 
-# Assembly files can be name with upper case .S, convert it to .s
-SRC_S := $(SRC_S:.S=.s)
-
-# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
-# assembly file should be placed first in linking order
-# '_asm' suffix is added to object of assembly file
-OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
-OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
+endif
 
 # Verbose mode
 ifeq ("$(V)","1")
@@ -79,6 +82,21 @@ $(info LDFLAGS $(LDFLAGS)) $(info )
 $(info ASFLAGS $(ASFLAGS)) $(info )
 endif
 
+# Assembly files can be name with upper case .S, convert it to .s
+SRC_S := $(SRC_S:.S=.s)
+IAR_SRC_S := $(IAR_SRC_S:.S=.s)
+
+# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
+# assembly file should be placed first in linking order
+# '_asm' suffix is added to object of assembly file
+ifdef USE_IAR
+OBJ += $(addprefix $(BUILD)/obj/, $(IAR_SRC_S:.s=_asm.o))
+else
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
+endif
+
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
+
 # ---------------------------------------
 # Rules
 # ---------------------------------------
@@ -96,9 +114,15 @@ else
 	@$(MKDIR) -p $@
 endif
 
-$(BUILD)/$(PROJECT).elf: $(OBJ)
-	@echo LINK $@
-	@$(CC) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group
+# We set vpath to point to the top of the tree so that the source files
+# can be located. By following this scheme, it allows a single build rule
+# to be used to compile all .c files.
+vpath %.c . $(TOP)
+vpath %.s . $(TOP)
+vpath %.S . $(TOP)
+
+ifndef USE_IAR
+# GCC based compiler
 
 $(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
@@ -108,6 +132,56 @@ $(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
 	@$(OBJCOPY) -O ihex $^ $@
 
+$(BUILD)/$(PROJECT).elf: $(OBJ)
+	@echo LINK $@
+	@$(LD) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group
+
+$(BUILD)/obj/%.o: %.c
+	@echo CC $(notdir $@)
+	@$(CC) $(CFLAGS) -c -MD -o $@ $<
+
+# ASM sources lower case .s
+$(BUILD)/obj/%_asm.o: %.s
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+# ASM sources upper case .S
+$(BUILD)/obj/%_asm.o: %.S
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+else
+
+# IAR Compiler
+
+$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) --bin $^ $@
+
+$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) --ihex $^ $@
+
+$(BUILD)/$(PROJECT).elf: $(OBJ)
+	@echo LINK $@
+	@$(LD) $(IAR_LDFLAGS) $^ -o $@
+
+$(BUILD)/obj/%.o: %.c
+	@echo CC $(notdir $@)
+	@$(CC) $(IAR_CFLAGS) -c -o $@ $<
+
+# ASM sources lower case .s
+$(BUILD)/obj/%_asm.o: %.s
+	@echo AS $(notdir $@)
+	@$(AS) $(IAR_ASFLAGS) -c -o $@ $<
+
+# ASM sources upper case .S
+$(BUILD)/obj/%_asm.o: %.S
+	@echo AS $(notdir $@)
+	@$(AS) $(IAR_ASFLAGS) -c -o $@ $<
+
+endif
+
 # UF2 generation, iMXRT need to strip to text only before conversion
 ifeq ($(FAMILY),imxrt)
 $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).elf
@@ -122,27 +196,8 @@ endif
 
 copy-artifact: $(BUILD)/$(PROJECT).bin $(BUILD)/$(PROJECT).hex $(BUILD)/$(PROJECT).uf2
 
-# We set vpath to point to the top of the tree so that the source files
-# can be located. By following this scheme, it allows a single build rule
-# to be used to compile all .c files.
-vpath %.c . $(TOP)
-$(BUILD)/obj/%.o: %.c
-	@echo CC $(notdir $@)
-	@$(CC) $(CFLAGS) -c -MD -o $@ $<
-
-# ASM sources lower case .s
-vpath %.s . $(TOP)
-$(BUILD)/obj/%_asm.o: %.s
-	@echo AS $(notdir $@)
-	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
-
-# ASM sources upper case .S
-vpath %.S . $(TOP)
-$(BUILD)/obj/%_asm.o: %.S
-	@echo AS $(notdir $@)
-	@$(CC) -x assembler-with-cpp $(ASFLAGS) -c -o $@ $<
-
 endif
+# ---------------- GNU Make End -----------------------
 
 .PHONY: clean
 clean:
@@ -151,7 +206,6 @@ ifeq ($(CMDEXE),1)
 else
 	$(RM) -rf $(BUILD)
 endif
-# ---------------- GNU Make End -----------------------
 
 # get depenecies
 .PHONY: get-deps
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
index 7c0ee40b6..242b5a034 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
@@ -1,11 +1,13 @@
 CFLAGS += -DSTM32F070xB -DCFG_EXAMPLE_VIDEO_READONLY
 
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
 LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f070xb.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f070xb_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f070rb
 
 # flash target using on-board stlink
-flash: flash-stlink
+flash: flash-stlink
\ No newline at end of file
diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index 8de3147e2..806c4af51 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -153,7 +153,7 @@ uint32_t board_millis(void)
 
 void HardFault_Handler (void)
 {
-  asm("bkpt");
+   __asm("BKPT #0\n");
 }
 
 #ifdef  USE_FULL_ASSERT
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 39831e154..a81ab426f 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -8,17 +8,28 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 include $(TOP)/$(BOARD_PATH)/board.mk
 
 CFLAGS += \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F0
+
+# --------------
+# GCC Flags
+# --------------
+GCC_CFLAGS += \
   -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m0 \
   -mfloat-abi=soft \
   -nostdlib -nostartfiles \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F0
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
+GCC_CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
+
+# --------------
+# IAR Flags
+# --------------
+IAR_CFLAGS += --cpu cortex-m0
+IAR_ASFLAGS += --cpu cortex-m0
 
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \

From c414cc650e995c9136afcb291434c3af99abd178 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Jan 2023 16:30:33 +0700
Subject: [PATCH 1403/2085] try running iar build with self-host

---
 .github/workflows/build_iar_arm.yml | 54 +++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 .github/workflows/build_iar_arm.yml

diff --git a/.github/workflows/build_iar_arm.yml b/.github/workflows/build_iar_arm.yml
new file mode 100644
index 000000000..65ab6e5c8
--- /dev/null
+++ b/.github/workflows/build_iar_arm.yml
@@ -0,0 +1,54 @@
+name: Build IAR for ARM
+
+on:
+  push:
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
+jobs:
+  build-arm:
+    runs-on: [self-hosted, Linux, X64, hifiphile]
+    strategy:
+      fail-fast: false
+      matrix:
+        family:
+        # Alphabetical order
+        - 'stm32f0'
+    steps:
+    - name: Clean workspace
+      run: |
+        echo "Cleaning up previous run"
+        rm -rf "${{ github.workspace }}"
+        mkdir -p "${{ github.workspace }}"
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v3
+
+    - name: Checkout submodules and dependencies
+      run: |
+        git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
+        python3 tools/get_dependencies.py ${{ matrix.family }}
+
+    - name: Checkout pico-sdk for rp2040
+      if: matrix.family == 'rp2040'
+      run: |
+        git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
+        echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
+
+    - name: Build
+      #run: python3 tools/build_family.py ${{ matrix.family }}
+      run: make -j -C examples/device/cdc_msc BOARD=stm32f070rbnucleo CC=iccarm all

From 1891802f081e586ad5e992a4e498a069d28f529e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Jan 2023 16:38:02 +0700
Subject: [PATCH 1404/2085] update all f0 board to build with iar

---
 .github/workflows/build_iar_arm.yml           | 5 ++++-
 hw/bsp/stm32f0/boards/stm32f072disco/board.mk | 4 +++-
 hw/bsp/stm32f0/boards/stm32f072eval/board.mk  | 4 +++-
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/build_iar_arm.yml b/.github/workflows/build_iar_arm.yml
index 65ab6e5c8..ed75eca5b 100644
--- a/.github/workflows/build_iar_arm.yml
+++ b/.github/workflows/build_iar_arm.yml
@@ -51,4 +51,7 @@ jobs:
 
     - name: Build
       #run: python3 tools/build_family.py ${{ matrix.family }}
-      run: make -j -C examples/device/cdc_msc BOARD=stm32f070rbnucleo CC=iccarm all
+      run: |
+        make -j -C examples/device/cdc_msc BOARD=stm32f070rbnucleo CC=iccarm all
+        make -j -C examples/device/cdc_msc BOARD=stm32f072disco CC=iccarm all
+        make -j -C examples/device/cdc_msc BOARD=stm32f072eval CC=iccarm all
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
index 7c72d8f4c..1003be553 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
@@ -1,8 +1,10 @@
 CFLAGS += -DSTM32F072xB -DCFG_EXAMPLE_VIDEO_READONLY
 
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
 LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f072rb
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
index b625c3ebd..4134c1f45 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
@@ -1,8 +1,10 @@
 CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY
 
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
 LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f072vb

From c86e628a4c199a39f8317a0d4b5dd96e9692e544 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Jan 2023 23:37:00 +0700
Subject: [PATCH 1405/2085] update build script to support iar with CC=iccarm
 option

---
 .github/workflows/build_iar_arm.yml |  2 +-
 tools/build_board.py                |  2 +-
 tools/build_family.py               | 11 ++++++++---
 tools/build_utils.py                |  6 +++---
 4 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/.github/workflows/build_iar_arm.yml b/.github/workflows/build_iar_arm.yml
index ed75eca5b..bcf560024 100644
--- a/.github/workflows/build_iar_arm.yml
+++ b/.github/workflows/build_iar_arm.yml
@@ -1,4 +1,4 @@
-name: Build IAR for ARM
+name: Build ARM with IAR
 
 on:
   push:
diff --git a/tools/build_board.py b/tools/build_board.py
index 8d10ef820..4593dafa5 100644
--- a/tools/build_board.py
+++ b/tools/build_board.py
@@ -52,7 +52,7 @@ if __name__ == '__main__':
     for example in all_examples:
         print(build_separator)
         with Pool(processes=os.cpu_count()) as pool:
-            pool_args = list((map(lambda b, e=example: [e, b], all_boards)))
+            pool_args = list((map(lambda b, e=example, o='': [e, b, o], all_boards)))
             result = pool.starmap(build_utils.build_example, pool_args)
             # sum all element of same index (column sum)
             result = list(map(sum, list(zip(*result))))
diff --git a/tools/build_family.py b/tools/build_family.py
index c6c64d2b3..cdc099691 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -11,6 +11,7 @@ SKIPPED = "\033[33mskipped\033[0m"
 
 build_separator = '-' * 106
 
+make_iar_option = 'CC=iccarm'
 
 def filter_with_input(mylist):
     if len(sys.argv) > 1:
@@ -19,7 +20,7 @@ def filter_with_input(mylist):
             mylist[:] = input_args
 
 
-def build_family(example, family):
+def build_family(example, family, make_option):
     all_boards = []
     for entry in os.scandir("hw/bsp/{}/boards".format(family)):
         if entry.is_dir() and entry.name != 'pico_sdk':
@@ -28,13 +29,17 @@ def build_family(example, family):
     all_boards.sort()
 
     with Pool(processes=os.cpu_count()) as pool:
-        pool_args = list((map(lambda b, e=example: [e, b], all_boards)))
+        pool_args = list((map(lambda b, e=example, o=make_option: [e, b, o], all_boards)))
         result = pool.starmap(build_utils.build_example, pool_args)
         # sum all element of same index (column sum)
         return list(map(sum, list(zip(*result))))
 
 
 if __name__ == '__main__':
+    # IAR CC
+    if make_iar_option not in sys.argv:
+        make_iar_option = ''
+
     # If examples are not specified in arguments, build all
     all_examples = []
     for dir1 in os.scandir("examples"):
@@ -62,7 +67,7 @@ if __name__ == '__main__':
     for example in all_examples:
         print(build_separator)
         for family in all_families:
-            fret = build_family(example, family)
+            fret = build_family(example, family, make_iar_option)
             total_result = list(map(lambda x, y: x + y, total_result, fret))
 
     total_time = time.monotonic() - total_time
diff --git a/tools/build_utils.py b/tools/build_utils.py
index f457c7986..ad1daf8c7 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -77,7 +77,7 @@ def skip_example(example, board):
     return False
 
 
-def build_example(example, board):
+def build_example(example, board, make_option):
     start_time = time.monotonic()
     flash_size = "-"
     sram_size = "-"
@@ -91,14 +91,14 @@ def build_example(example, board):
         ret[2] = 1
         print(build_format.format(example, board, status, '-', flash_size, sram_size))
     else:
-        build_result = subprocess.run("make -j -C examples/{} BOARD={} all".format(example, board), shell=True,
+        build_result = subprocess.run("make -j -C examples/{} BOARD={} {} all".format(example, board, make_option), shell=True,
                                       stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
 
         if build_result.returncode == 0:
             status = SUCCEEDED
             ret[0] = 1
             (flash_size, sram_size) = build_size(example, board)
-            subprocess.run("make -j -C examples/{} BOARD={} copy-artifact".format(example, board), shell=True,
+            subprocess.run("make -j -C examples/{} BOARD={} {} copy-artifact".format(example, board, make_option), shell=True,
                            stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
         else:
             status = FAILED

From 8df2fd1916d5e69cfaad7516399a8d7da5060f57 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Jan 2023 23:38:10 +0700
Subject: [PATCH 1406/2085] update freertos example to build with iar

---
 examples/device/cdc_msc_freertos/Makefile     | 12 ++++++++----
 .../src/FreeRTOSConfig/FreeRTOSConfig.h       |  7 ++++++-
 .../device/hid_composite_freertos/Makefile    | 12 ++++++++----
 .../src/FreeRTOSConfig/FreeRTOSConfig.h       |  7 ++++++-
 examples/rules.mk                             | 19 +++++++++----------
 .../stm32f0/boards/stm32f070rbnucleo/board.mk |  2 +-
 hw/bsp/stm32f0/boards/stm32f072disco/board.mk |  2 +-
 hw/bsp/stm32f0/boards/stm32f072eval/board.mk  |  2 +-
 8 files changed, 40 insertions(+), 23 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index ff4b41108..4ee816880 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -4,13 +4,14 @@ include ../../../tools/top.mk
 include ../../make.mk
 
 FREERTOS_SRC = lib/FreeRTOS-Kernel
+FREERTOS_PORTABLE_SRC= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)/$(FREERTOS_PORT)
 
 INC += \
 	src \
 	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
-	$(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)
+	$(TOP)/$(FREERTOS_PORTABLE_SRC)
 	
 # Example source
 EXAMPLE_SOURCE = \
@@ -27,17 +28,20 @@ SRC_C += \
 	$(FREERTOS_SRC)/queue.c \
 	$(FREERTOS_SRC)/tasks.c \
 	$(FREERTOS_SRC)/timers.c \
-	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
+	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_PORTABLE_SRC)/*.c))
+
+SRC_S += \
+	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_PORTABLE_SRC)/*.s))
 
 # include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
 # SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
 # CFLAGS += -Wno-error=sign-compare
 
 # Suppress FreeRTOSConfig.h warnings
-CFLAGS += -Wno-error=redundant-decls
+GCC_CFLAGS += -Wno-error=redundant-decls
 
 # Suppress FreeRTOS source warnings
-CFLAGS += -Wno-error=cast-qual
+GCC_CFLAGS += -Wno-error=cast-qual
 
 # FreeRTOS (lto + Os) linker issue
 LDFLAGS += -Wl,--undefined=vTaskSwitchContext
diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 968c59749..efd527ed2 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,6 +42,9 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
+// skip if is compiled with assembler
+#if !defined(__ASSEMBLER__) && !defined(__IASMARM__)
+
 // Include MCU header
 #include "bsp/board_mcu.h"
 
@@ -57,6 +60,8 @@
   extern uint32_t SystemCoreClock;
 #endif
 
+#endif
+
 /* Cortex M23/M33 port configuration. */
 #define configENABLE_MPU								        0
 #define configENABLE_FPU								        1
@@ -166,7 +171,7 @@
 #elif defined(__ECLIC_INTCTLBITS)
   // RISC-V Bumblebee core from nuclei
   #define configPRIO_BITS       __ECLIC_INTCTLBITS
-#else
+#elif !defined(__ASSEMBLER__) && !defined(__IASMARM__)
   #error "FreeRTOS configPRIO_BITS to be defined"
 #endif
 
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index 9c66b896d..a354a90b6 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -4,13 +4,14 @@ include ../../../tools/top.mk
 include ../../make.mk
 
 FREERTOS_SRC = lib/FreeRTOS-Kernel
+FREERTOS_PORTABLE_SRC= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)/$(FREERTOS_PORT)
 
 INC += \
 	src \
 	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
-	$(TOP)/$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)	
+	$(TOP)/$(FREERTOS_PORTABLE_SRC)
 
 # Example source
 EXAMPLE_SOURCE = \
@@ -26,17 +27,20 @@ SRC_C += \
 	$(FREERTOS_SRC)/queue.c \
 	$(FREERTOS_SRC)/tasks.c \
 	$(FREERTOS_SRC)/timers.c \
-	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_SRC)/portable/GCC/$(FREERTOS_PORT)/*.c))
+	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_PORTABLE_SRC)/*.c))
+
+SRC_S += \
+	$(subst ../../../,,$(wildcard ../../../$(FREERTOS_PORTABLE_SRC)/*.s))
 
 # include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
 # SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
 # CFLAGS += -Wno-error=sign-compare
 
 # Suppress FreeRTOSConfig.h warnings
-CFLAGS += -Wno-error=redundant-decls
+GCC_CFLAGS += -Wno-error=redundant-decls
 
 # Suppress FreeRTOS source warnings
-CFLAGS += -Wno-error=cast-qual
+GCC_CFLAGS += -Wno-error=cast-qual
 
 # FreeRTOS (lto + Os) linker issue
 LDFLAGS += -Wl,--undefined=vTaskSwitchContext
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 968c59749..efd527ed2 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,6 +42,9 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
+// skip if is compiled with assembler
+#if !defined(__ASSEMBLER__) && !defined(__IASMARM__)
+
 // Include MCU header
 #include "bsp/board_mcu.h"
 
@@ -57,6 +60,8 @@
   extern uint32_t SystemCoreClock;
 #endif
 
+#endif
+
 /* Cortex M23/M33 port configuration. */
 #define configENABLE_MPU								        0
 #define configENABLE_FPU								        1
@@ -166,7 +171,7 @@
 #elif defined(__ECLIC_INTCTLBITS)
   // RISC-V Bumblebee core from nuclei
   #define configPRIO_BITS       __ECLIC_INTCTLBITS
-#else
+#elif !defined(__ASSEMBLER__) && !defined(__IASMARM__)
   #error "FreeRTOS configPRIO_BITS to be defined"
 #endif
 
diff --git a/examples/rules.mk b/examples/rules.mk
index 2c4df85ba..c3b757eec 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -48,8 +48,11 @@ CFLAGS += $(addprefix -I,$(INC))
 
 ifdef USE_IAR
 
-IAR_CFLAGS += $(CFLAGS) -e --debug
+IAR_CFLAGS += $(CFLAGS) -e --debug --silent
 IAR_LDFLAGS += --config $(TOP)/$(IAR_LD_FILE)
+IAR_ASFLAGS += $(CFLAGS) -S
+
+SRC_S += $(IAR_SRC_S)
 
 else
 
@@ -73,7 +76,9 @@ endif
 
 ASFLAGS += $(CFLAGS)
 
-endif
+SRC_S += $(GCC_SRC_S)
+
+endif # USE_IAR
 
 # Verbose mode
 ifeq ("$(V)","1")
@@ -84,17 +89,11 @@ endif
 
 # Assembly files can be name with upper case .S, convert it to .s
 SRC_S := $(SRC_S:.S=.s)
-IAR_SRC_S := $(IAR_SRC_S:.S=.s)
 
 # Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
 # assembly file should be placed first in linking order
 # '_asm' suffix is added to object of assembly file
-ifdef USE_IAR
-OBJ += $(addprefix $(BUILD)/obj/, $(IAR_SRC_S:.s=_asm.o))
-else
 OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
-endif
-
 OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
 
 # ---------------------------------------
@@ -156,11 +155,11 @@ else
 
 $(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
-	@$(OBJCOPY) --bin $^ $@
+	@$(OBJCOPY) --silent --bin $^ $@
 
 $(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
-	@$(OBJCOPY) --ihex $^ $@
+	@$(OBJCOPY) --silent --ihex $^ $@
 
 $(BUILD)/$(PROJECT).elf: $(OBJ)
 	@echo LINK $@
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
index 242b5a034..f470b80f0 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
@@ -1,6 +1,6 @@
 CFLAGS += -DSTM32F070xB -DCFG_EXAMPLE_VIDEO_READONLY
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
 LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld
 
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f070xb.s
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
index 1003be553..edee9b0e8 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
@@ -1,6 +1,6 @@
 CFLAGS += -DSTM32F072xB -DCFG_EXAMPLE_VIDEO_READONLY
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
 LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
 
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
index 4134c1f45..6503d3273 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
@@ -1,6 +1,6 @@
 CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
 LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
 
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s

From eb7aacb51f00a55867304d6217dcaaf39f7019c0 Mon Sep 17 00:00:00 2001
From: Howard Su <howard0su@gmail.com>
Date: Sat, 7 Jan 2023 07:01:14 +0000
Subject: [PATCH 1407/2085] Allow config OS for RP2040

---
 hw/bsp/rp2040/family.cmake | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 5dba9dc39..350e8bc65 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -23,6 +23,10 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		set(PICO_TINYUSB_PATH ${TOP})
 	endif()
 
+	if (NOT TINYUSB_OPT_OS)
+		set(TINYUSB_OPT_OS OPT_OS_PICO)
+	endif()
+
 	#------------------------------------
 	# Base config for both device and host; wrapped by SDK's tinyusb_common
 	#------------------------------------
@@ -54,7 +58,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	
 	target_compile_definitions(tinyusb_common_base INTERFACE
 			CFG_TUSB_MCU=OPT_MCU_RP2040
-			CFG_TUSB_OS=OPT_OS_PICO
+			CFG_TUSB_OS=${TINYUSB_OPT_OS}
 			#CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
 	)
 

From ecfd57e6f12b16c1d7f8cfe2ff6b70e387b38119 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 18 Jan 2023 10:31:00 +0700
Subject: [PATCH 1408/2085] get most examples build with iar

---
 examples/device/dfu/Makefile                  |  5 ++-
 examples/device/net_lwip_webserver/Makefile   |  2 +-
 .../net_lwip_webserver/src/arch/bpstruct.h    | 35 +++++++++++++++++++
 .../net_lwip_webserver/src/arch/epstruct.h    | 35 +++++++++++++++++++
 examples/device/usbtmc/src/usbtmc_app.c       |  2 +-
 hw/bsp/board.c                                |  6 ++--
 6 files changed, 80 insertions(+), 5 deletions(-)
 create mode 100644 examples/device/net_lwip_webserver/src/arch/bpstruct.h
 create mode 100644 examples/device/net_lwip_webserver/src/arch/epstruct.h

diff --git a/examples/device/dfu/Makefile b/examples/device/dfu/Makefile
index 69b633fea..5148ed55a 100644
--- a/examples/device/dfu/Makefile
+++ b/examples/device/dfu/Makefile
@@ -6,7 +6,10 @@ INC += \
 	$(TOP)/hw \
 
 # Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
+EXAMPLE_SOURCE = \
+	src/main.c \
+	src/usb_descriptors.c
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 include ../../rules.mk
diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile
index 881866a56..55bd820bd 100644
--- a/examples/device/net_lwip_webserver/Makefile
+++ b/examples/device/net_lwip_webserver/Makefile
@@ -4,7 +4,7 @@ include ../../../tools/top.mk
 include ../../make.mk
 
 # suppress warning caused by lwip
-CFLAGS += \
+GCC_CFLAGS += \
   -Wno-error=null-dereference \
   -Wno-error=unused-parameter \
   -Wno-error=unused-variable
diff --git a/examples/device/net_lwip_webserver/src/arch/bpstruct.h b/examples/device/net_lwip_webserver/src/arch/bpstruct.h
new file mode 100644
index 000000000..74ead358f
--- /dev/null
+++ b/examples/device/net_lwip_webserver/src/arch/bpstruct.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#if defined(__ICCARM__)
+#pragma pack(1)
+#endif
diff --git a/examples/device/net_lwip_webserver/src/arch/epstruct.h b/examples/device/net_lwip_webserver/src/arch/epstruct.h
new file mode 100644
index 000000000..f6390959e
--- /dev/null
+++ b/examples/device/net_lwip_webserver/src/arch/epstruct.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+
+#if defined(__ICCARM__)
+#pragma pack()
+#endif
diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index 8f87a6dca..4700656cb 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include <strings.h>
+#include <string.h>
 #include <stdlib.h>     /* atoi */
 #include "tusb.h"
 #include "bsp/board.h"
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 7e96735bd..14858c2b6 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -77,8 +77,10 @@ void board_led_task(void)
 //--------------------------------------------------------------------+
 // newlib read()/write() retarget
 //--------------------------------------------------------------------+
-
-#if defined(__MSP430__) || defined(__RX__)
+#ifdef __ICCARM__
+  #define sys_write   __write
+  #define sys_read    __read
+#elif defined(__MSP430__) || defined(__RX__)
   #define sys_write   write
   #define sys_read    read
 #else

From fb7122f07d2b6cc064e4898735fdb6c63f14df8e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 18 Jan 2023 10:33:26 +0700
Subject: [PATCH 1409/2085] update iar ci

---
 .github/workflows/{build_iar_arm.yml => build_iar.yml} | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)
 rename .github/workflows/{build_iar_arm.yml => build_iar.yml} (78%)

diff --git a/.github/workflows/build_iar_arm.yml b/.github/workflows/build_iar.yml
similarity index 78%
rename from .github/workflows/build_iar_arm.yml
rename to .github/workflows/build_iar.yml
index bcf560024..4c43400ab 100644
--- a/.github/workflows/build_iar_arm.yml
+++ b/.github/workflows/build_iar.yml
@@ -1,4 +1,4 @@
-name: Build ARM with IAR
+name: Build IAR
 
 on:
   push:
@@ -50,8 +50,4 @@ jobs:
         echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
 
     - name: Build
-      #run: python3 tools/build_family.py ${{ matrix.family }}
-      run: |
-        make -j -C examples/device/cdc_msc BOARD=stm32f070rbnucleo CC=iccarm all
-        make -j -C examples/device/cdc_msc BOARD=stm32f072disco CC=iccarm all
-        make -j -C examples/device/cdc_msc BOARD=stm32f072eval CC=iccarm all
+      run: python3 tools/build_family.py ${{ matrix.family }} CC=iccarm

From 075095554aee6b72f7678c4db881162f533cbb13 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 18 Jan 2023 11:47:24 +0700
Subject: [PATCH 1410/2085] dont use non-std strncasecmp

---
 examples/device/usbtmc/src/usbtmc_app.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index 4700656cb..503ee3071 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -148,11 +148,12 @@ bool tud_usbtmc_msg_data_cb(void *data, size_t len, bool transfer_complete)
   queryState = transfer_complete;
   idnQuery = 0;
 
-  if(transfer_complete && (len >=4) && !strncasecmp("*idn?",data,4))
+  if ( transfer_complete && (len >= 4) && (!strncmp("*idn?", data, 4) || !strncmp("*IDN?", data, 4)) )
   {
     idnQuery = 1;
   }
-  if(transfer_complete && !strncasecmp("delay ",data,5))
+
+  if ( transfer_complete && (!strncmp("delay ", data, 5) || !strncmp("DELAY ", data, 5)) )
   {
     queryState = 0;
     int d = atoi((char*)data + 5);

From 84be70baf5eaada4317c0483c33580bcde4116de Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 18 Jan 2023 13:17:53 +0700
Subject: [PATCH 1411/2085] fix iar build with board_test

---
 examples/device/board_test/Makefile          | 6 ------
 examples/device/board_test/src/tusb_config.h | 5 +++++
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/examples/device/board_test/Makefile b/examples/device/board_test/Makefile
index b65575ce6..5a455078e 100644
--- a/examples/device/board_test/Makefile
+++ b/examples/device/board_test/Makefile
@@ -9,10 +9,4 @@ INC += \
 EXAMPLE_SOURCE += $(wildcard src/*.c)
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# board_test example is special example that doesn't enable device or host stack
-# This can cause some TinyUSB API missing, this hack to allow us to fill those API
-# to pass the compilation process
-CFLAGS +=	\
-	-D"tud_int_handler(x)= " \
-
 include ../../rules.mk
diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h
index 5aea4fd2c..2c2eb5280 100644
--- a/examples/device/board_test/src/tusb_config.h
+++ b/examples/device/board_test/src/tusb_config.h
@@ -30,6 +30,11 @@
  extern "C" {
 #endif
 
+// board_test example is special example that doesn't enable device or host stack
+// This can cause some TinyUSB API missing, this define hack to allow us to fill those API
+// to pass the compilation process
+#define tud_int_handler(x)
+
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------

From 3fd075b48bfe80ef7d7f61c1f6229c3aa413383e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 20 Jan 2023 15:29:23 +0700
Subject: [PATCH 1412/2085] fix warning

---
 examples/device/video_capture/src/usb_descriptors.c | 1 +
 hw/bsp/stm32f0/family.c                             | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 499ee311c..0cf772010 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -99,6 +99,7 @@ uint8_t const desc_fs_configuration[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0, 500),
+
   // IAD for Video Control
 #if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
   TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(4, EPNUM_VIDEO_IN,
diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index 806c4af51..a7e914128 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -118,7 +118,8 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
 uint32_t board_button_read(void)

From 074289caa31297b7261d9484f529f481d0fc9f06 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 20 Jan 2023 15:30:24 +0700
Subject: [PATCH 1413/2085] add helper tu_desc_find/find2/find3

---
 src/common/tusb_types.h | 13 +++++++++++++
 src/tusb.c              | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 32cdba450..82798a484 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -543,22 +543,35 @@ TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_
 //--------------------------------------------------------------------+
 // Descriptor helper
 //--------------------------------------------------------------------+
+
+// return next descriptor
 TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc)
 {
   uint8_t const* desc8 = (uint8_t const*) desc;
   return desc8 + desc8[DESC_OFFSET_LEN];
 }
 
+// get descriptor type
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc)
 {
   return ((uint8_t const*) desc)[DESC_OFFSET_TYPE];
 }
 
+// get descriptor length
 TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc)
 {
   return ((uint8_t const*) desc)[DESC_OFFSET_LEN];
 }
 
+// find descriptor that match byte1 (type)
+uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1);
+
+// find descriptor that match byte1 (type) and byte2
+uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2);
+
+// find descriptor that match byte1 (type) and byte2
+uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3);
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/tusb.c b/src/tusb.c
index a5c820b8d..44b34b0e6 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -73,6 +73,41 @@ bool tusb_inited(void)
   return ret;
 }
 
+//--------------------------------------------------------------------+
+// Descriptor helper
+//--------------------------------------------------------------------+
+
+uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1)
+{
+  while(desc+1 < end)
+  {
+    if ( desc[1] == byte1 ) return desc;
+    desc += desc[DESC_OFFSET_LEN];
+  }
+  return NULL;
+}
+
+uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2)
+{
+  while(desc+2 < end)
+  {
+    if ( desc[1] == byte1 && desc[2] == byte2) return desc;
+    desc += desc[DESC_OFFSET_LEN];
+  }
+  return NULL;
+}
+
+uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3)
+{
+  while(desc+3 < end)
+  {
+    if (desc[1] == byte1 && desc[2] == byte2 && desc[3] == byte3) return desc;
+    desc += desc[DESC_OFFSET_LEN];
+  }
+  return NULL;
+}
+
+
 //--------------------------------------------------------------------+
 // Endpoint Helper for both Host and Device stack
 //--------------------------------------------------------------------+

From daec3c24d86682946aea5d9c38623b466851836e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 20 Jan 2023 15:30:45 +0700
Subject: [PATCH 1414/2085] fix warnings with arithmetic on void* pointer

---
 src/class/video/video_device.c | 51 +++++++++++++++++++---------------
 1 file changed, 29 insertions(+), 22 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index e17d0a90f..257285126 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -108,7 +108,7 @@ typedef struct TU_ATTR_PACKED {
 
 /* video control interface */
 typedef struct TU_ATTR_PACKED {
-  void const *beg;  /* The head of the first video control interface descriptor */
+  uint8_t const *beg;  /* The head of the first video control interface descriptor */
   uint16_t    len;  /* Byte length of the descriptors */
   uint16_t    cur;  /* offset for current video control interface */
   uint8_t     stm[CFG_TUD_VIDEO_STREAMING]; /* Indices of streaming interface */
@@ -174,7 +174,7 @@ static tusb_desc_vc_itf_t const* _get_desc_vc(videod_interface_t const *self)
 static tusb_desc_vs_itf_t const* _get_desc_vs(videod_streaming_interface_t const *self)
 {
   if (!self->desc.cur) return NULL;
-  void const *desc = _videod_itf[self->index_vc].beg;
+  uint8_t const *desc = _videod_itf[self->index_vc].beg;
   return (tusb_desc_vs_itf_t const*)(desc + self->desc.cur);
 }
 
@@ -247,9 +247,9 @@ static void const* _next_desc_itf(void const *beg, void const *end)
  *
  * @return The pointer for interface descriptor.
  * @retval end   did not found interface descriptor */
-static inline void const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum)
+static inline uint8_t const* _find_desc_itf(void const *beg, void const *end, uint_fast8_t itfnum, uint_fast8_t altnum)
 {
-  return _find_desc_3(beg, end, TUSB_DESC_INTERFACE, itfnum, altnum);
+  return (uint8_t const*) _find_desc_3(beg, end, TUSB_DESC_INTERFACE, itfnum, altnum);
 }
 
 /** Find the first endpoint descriptor belonging to the current interface descriptor.
@@ -275,7 +275,7 @@ static void const* _find_desc_ep(void const *beg, void const *end)
 static inline void const* _end_of_control_descriptor(void const *desc)
 {
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)desc;
-  return desc + vc->std.bLength + vc->ctl.wTotalLength;
+  return ((uint8_t const*) desc) + vc->std.bLength + tu_le16toh(vc->ctl.wTotalLength);
 }
 
 /** Find the first entity descriptor with the entity ID
@@ -305,7 +305,7 @@ static void const* _find_desc_entity(void const *desc, uint_fast8_t entityid)
 static inline void const* _end_of_streaming_descriptor(void const *desc)
 {
   tusb_desc_vs_itf_t const *vs = (tusb_desc_vs_itf_t const *)desc;
-  return desc + vs->std.bLength + vs->stm.wTotalLength;
+  return ((uint8_t const*) desc) + vs->std.bLength + tu_le16toh(vs->stm.wTotalLength);
 }
 
 /** Find the first format descriptor with the specified format number. */
@@ -581,8 +581,10 @@ static bool _negotiate_streaming_parameters(videod_streaming_interface_t const *
 static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
 {
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
+
   /* The next descriptor after the class-specific VC interface header descriptor. */
-  void const *cur = (void const*)vc + vc->std.bLength + vc->ctl.bLength;
+  void const *cur = (uint8_t const*)vc + vc->std.bLength + vc->ctl.bLength;
+
   /* The end of the video control interface descriptor. */
   void const *end = _end_of_control_descriptor(vc);
   if (vc->std.bNumEndpoints) {
@@ -603,10 +605,11 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum)
 {
   TU_LOG2("    open VC %d\n", altnum);
-  void const *beg = self->beg;
-  void const *end = beg + self->len;
+  uint8_t const *beg = self->beg;
+  uint8_t const *end = beg + self->len;
+
   /* The first descriptor is a video control interface descriptor. */
-  void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
+  uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
   TU_LOG2("    cur %d\n", cur - beg);
   TU_VERIFY(cur < end);
 
@@ -616,7 +619,8 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
   TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING);
 
   /* Update to point the end of the video control interface descriptor. */
-  end  = _end_of_control_descriptor(cur);
+  end = _end_of_control_descriptor(cur);
+
   /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
   cur += vc->std.bLength + vc->ctl.bLength;
   TU_LOG2("    bNumEndpoints %d\n", vc->std.bNumEndpoints);
@@ -631,7 +635,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
     /* Open the notification endpoint */
     TU_ASSERT(usbd_edpt_open(rhport, notif));
   }
-  self->cur = (uint16_t) ((void const*)vc - beg);
+  self->cur = (uint16_t) ((uint8_t const*)vc - beg);
   return true;
 }
 
@@ -643,7 +647,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
 {
   uint_fast8_t i;
   TU_LOG2("    reopen VS %d\n", altnum);
-  void const *desc = _videod_itf[stm->index_vc].beg;
+  uint8_t const *desc = _videod_itf[stm->index_vc].beg;
 
   /* Close endpoints of previous settings. */
   for (i = 0; i < TU_ARRAY_SIZE(stm->desc.ep); ++i) {
@@ -654,16 +658,18 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     stm->desc.ep[i] = 0;
     TU_LOG2("    close EP%02x\n", ep_adr);
   }
+
   /* clear transfer management information */
   stm->buffer  = NULL;
   stm->bufsize = 0;
   stm->offset  = 0;
 
   /* Find a alternate interface */
-  void const *beg = desc + stm->desc.beg;
-  void const *end = desc + stm->desc.end;
-  void const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
+  uint8_t const *beg = desc + stm->desc.beg;
+  uint8_t const *end = desc + stm->desc.end;
+  uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
   TU_VERIFY(cur < end);
+
   uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints;
   TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep));
   stm->desc.cur = (uint16_t) (cur - desc); /* Save the offset of the new settings */
@@ -1043,7 +1049,6 @@ static int handle_video_stm_req(uint8_t rhport, uint8_t stage,
 
     default: return VIDEO_ERROR_INVALID_REQUEST;
   }
-  return VIDEO_ERROR_UNKNOWN;
 }
 
 //--------------------------------------------------------------------+
@@ -1076,7 +1081,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
   if (!stm || !stm->desc.ep[0] || stm->buffer) return false;
 
   /* Find EP address */
-  void const *desc = _videod_itf[stm->index_vc].beg;
+  uint8_t const *desc = _videod_itf[stm->index_vc].beg;
   uint8_t ep_addr = 0;
   for (uint_fast8_t i = 0; i < CFG_TUD_VIDEO_STREAMING; ++i) {
     uint_fast16_t ofs_ep = stm->desc.ep[i];
@@ -1143,13 +1148,15 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   }
   TU_ASSERT(ctl_idx < CFG_TUD_VIDEO, 0);
 
-  void const *end = (void const*)itf_desc + max_len;
-  self->beg = itf_desc;
+  uint8_t const *end = (uint8_t const*)itf_desc + max_len;
+  self->beg = (uint8_t const*) itf_desc;
   self->len = max_len;
+
   /*------------- Video Control Interface -------------*/
   TU_VERIFY(_open_vc_itf(rhport, self, 0), 0);
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
   uint_fast8_t bInCollection   = vc->ctl.bInCollection;
+
   /* Find the end of the video interface descriptor */
   void const *cur = _next_desc_itf(itf_desc, end);
   for (uint8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) {
@@ -1200,7 +1207,7 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   for (itf = 0; itf < CFG_TUD_VIDEO_STREAMING; ++itf) {
     videod_streaming_interface_t *stm = &_videod_streaming_itf[itf];
     if (!stm->desc.beg) continue;
-    void const *desc = _videod_itf[stm->index_vc].beg;
+    uint8_t const *desc = _videod_itf[stm->index_vc].beg;
     if (itfnum == _desc_itfnum(desc + stm->desc.beg)) break;
   }
 
@@ -1226,7 +1233,7 @@ bool videod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     uint_fast16_t const ep_ofs = stm->desc.ep[0];
     if (!ep_ofs) continue;
     ctl = &_videod_itf[stm->index_vc];
-    void const *desc = ctl->beg;
+    uint8_t const *desc = ctl->beg;
     if (ep_addr == _desc_ep_addr(desc + ep_ofs)) break;
   }
 

From cb34cb2a9397eeeeff9bacd212914477c6e76ff9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 20 Jan 2023 15:56:32 +0700
Subject: [PATCH 1415/2085] slightly update rule.mk for IAR

---
 examples/rules.mk | 62 ++++++++++++++++++-----------------------------
 1 file changed, 23 insertions(+), 39 deletions(-)

diff --git a/examples/rules.mk b/examples/rules.mk
index c3b757eec..19ecbc9e1 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -48,15 +48,17 @@ CFLAGS += $(addprefix -I,$(INC))
 
 ifdef USE_IAR
 
-IAR_CFLAGS += $(CFLAGS) -e --debug --silent
-IAR_LDFLAGS += --config $(TOP)/$(IAR_LD_FILE)
-IAR_ASFLAGS += $(CFLAGS) -S
-
 SRC_S += $(IAR_SRC_S)
 
+ASFLAGS := $(CFLAGS) $(IAR_ASFLAGS) $(ASFLAGS) -S
+IAR_LDFLAGS += --config $(TOP)/$(IAR_LD_FILE)
+CFLAGS += $(IAR_CFLAGS) -e --debug --silent
+
 else
 
-CFLAGS += $(GCC_CFLAGS)
+SRC_S += $(GCC_SRC_S)
+
+CFLAGS += $(GCC_CFLAGS) -MD
 
 # LTO makes it difficult to analyze map file for optimizing size purpose
 # We will run this option in ci
@@ -76,8 +78,6 @@ endif
 
 ASFLAGS += $(CFLAGS)
 
-SRC_S += $(GCC_SRC_S)
-
 endif # USE_IAR
 
 # Verbose mode
@@ -120,9 +120,23 @@ vpath %.c . $(TOP)
 vpath %.s . $(TOP)
 vpath %.S . $(TOP)
 
+# Compile .c file
+$(BUILD)/obj/%.o: %.c
+	@echo CC $(notdir $@)
+	@$(CC) $(CFLAGS) -c -o $@ $<
+
+# ASM sources lower case .s
+$(BUILD)/obj/%_asm.o: %.s
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+# ASM sources upper case .S
+$(BUILD)/obj/%_asm.o: %.S
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
 ifndef USE_IAR
 # GCC based compiler
-
 $(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
 	@$(OBJCOPY) -O binary $^ $@
@@ -135,24 +149,9 @@ $(BUILD)/$(PROJECT).elf: $(OBJ)
 	@echo LINK $@
 	@$(LD) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group
 
-$(BUILD)/obj/%.o: %.c
-	@echo CC $(notdir $@)
-	@$(CC) $(CFLAGS) -c -MD -o $@ $<
-
-# ASM sources lower case .s
-$(BUILD)/obj/%_asm.o: %.s
-	@echo AS $(notdir $@)
-	@$(AS) $(ASFLAGS) -c -o $@ $<
-
-# ASM sources upper case .S
-$(BUILD)/obj/%_asm.o: %.S
-	@echo AS $(notdir $@)
-	@$(AS) $(ASFLAGS) -c -o $@ $<
-
 else
 
 # IAR Compiler
-
 $(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
 	@$(OBJCOPY) --silent --bin $^ $@
@@ -163,22 +162,7 @@ $(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
 
 $(BUILD)/$(PROJECT).elf: $(OBJ)
 	@echo LINK $@
-	@$(LD) $(IAR_LDFLAGS) $^ -o $@
-
-$(BUILD)/obj/%.o: %.c
-	@echo CC $(notdir $@)
-	@$(CC) $(IAR_CFLAGS) -c -o $@ $<
-
-# ASM sources lower case .s
-$(BUILD)/obj/%_asm.o: %.s
-	@echo AS $(notdir $@)
-	@$(AS) $(IAR_ASFLAGS) -c -o $@ $<
-
-# ASM sources upper case .S
-$(BUILD)/obj/%_asm.o: %.S
-	@echo AS $(notdir $@)
-	@$(AS) $(IAR_ASFLAGS) -c -o $@ $<
-
+	@$(LD) -o $@ $(IAR_LDFLAGS) $^
 endif
 
 # UF2 generation, iMXRT need to strip to text only before conversion

From 456a8b208b4b9e7ce08c9f4515f4b616cbbe5d6d Mon Sep 17 00:00:00 2001
From: Dave Nadler <drn@nadler.com>
Date: Fri, 20 Jan 2023 12:59:16 -0500
Subject: [PATCH 1416/2085] Add support for NXP's mimxrt1024_evk evaluation
 board. Tested AOK with device\cdc_msc_freertos example.

---
 .../mimxrt1024_evk/mimxrt1024_evk/board.h     |  52 ++++
 .../mimxrt1024_evk/mimxrt1024_evk/board.mk    |  11 +
 .../evkmimxrt1024_flexspi_nor_config.c        |  48 ++++
 .../evkmimxrt1024_flexspi_nor_config.h        | 266 ++++++++++++++++++
 4 files changed, 377 insertions(+)
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.h
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.mk
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h

diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.h
new file mode 100644
index 000000000..152c9ab18
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.h
@@ -0,0 +1,52 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+// required since iMX RT10xx SDK include this file for board size
+// RT1020-EVK #define BOARD_FLASH_SIZE (0x800000U)
+#define BOARD_FLASH_SIZE (0x400000U) // builtin flash of RT1024
+
+// LED - DRN updated for RT1024EVK
+#define LED_PINMUX            IOMUXC_GPIO_AD_B1_08_GPIO1_IO24
+#define LED_PORT              GPIO1
+#define LED_PIN               24
+#define LED_STATE_ON          1
+
+// SW8 button - DRN verified
+#define BUTTON_PINMUX         IOMUXC_SNVS_WAKEUP_GPIO5_IO00
+#define BUTTON_PORT           GPIO5
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+// UART - DRN verified
+#define UART_PORT             LPUART1
+#define UART_RX_PINMUX        IOMUXC_GPIO_AD_B0_07_LPUART1_RX
+#define UART_TX_PINMUX        IOMUXC_GPIO_AD_B0_06_LPUART1_TX
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.mk
new file mode 100644
index 000000000..18b704510
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.mk
@@ -0,0 +1,11 @@
+CFLAGS += -DCPU_MIMXRT1024DAG5A
+MCU_VARIANT = MIMXRT1024
+
+# For flash-jlink target
+JLINK_DEVICE = MIMXRT1024DAG5A
+
+# For flash-pyocd target
+PYOCD_TARGET = mimxrt1024
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c
new file mode 100644
index 000000000..43dc1e823
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "evkmimxrt1024_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf"), used))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig =
+        {
+            .tag              = FLEXSPI_CFG_BLK_TAG,
+            .version          = FLEXSPI_CFG_BLK_VERSION,
+            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
+            .csHoldTime       = 3u,
+            .csSetupTime      = 3u,
+            .sflashPadType    = kSerialFlash_4Pads,
+            .serialClkFreq    = kFlexSpiSerialClk_60MHz,
+            .sflashA1Size     = 4u * 1024u * 1024u,
+            .lookupTable =
+                {
+                    // Read LUTs
+                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+                },
+        },
+    .pageSize           = 256u,
+    .sectorSize         = 4u * 1024u,
+    .blockSize          = 64u * 1024u,
+    .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h
new file mode 100644
index 000000000..987a46466
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.1. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/* FLEXSPI memory config block related defintions */
+#define FLEXSPI_CFG_BLK_TAG     (0x42464346UL) // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE    (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related defintions */
+#define CMD_INDEX_READ        0
+#define CMD_INDEX_READSTATUS  1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE       4
+
+#define CMD_LUT_SEQ_IDX_READ        0
+#define CMD_LUT_SEQ_IDX_READSTATUS  1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE       9
+
+#define CMD_SDR        0x01
+#define CMD_DDR        0x21
+#define RADDR_SDR      0x02
+#define RADDR_DDR      0x22
+#define CADDR_SDR      0x03
+#define CADDR_DDR      0x23
+#define MODE1_SDR      0x04
+#define MODE1_DDR      0x24
+#define MODE2_SDR      0x05
+#define MODE2_DDR      0x25
+#define MODE4_SDR      0x06
+#define MODE4_DDR      0x26
+#define MODE8_SDR      0x07
+#define MODE8_DDR      0x27
+#define WRITE_SDR      0x08
+#define WRITE_DDR      0x28
+#define READ_SDR       0x09
+#define READ_DDR       0x29
+#define LEARN_SDR      0x0A
+#define LEARN_DDR      0x2A
+#define DATSZ_SDR      0x0B
+#define DATSZ_DDR      0x2B
+#define DUMMY_SDR      0x0C
+#define DUMMY_DDR      0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS      0x1F
+#define STOP           0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz  = 1,
+    kFlexSpiSerialClk_50MHz  = 2,
+    kFlexSpiSerialClk_60MHz  = 3,
+    kFlexSpiSerialClk_75MHz  = 4,
+    kFlexSpiSerialClk_80MHz  = 5,
+    kFlexSpiSerialClk_100MHz = 6,
+    kFlexSpiSerialClk_133MHz = 7,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad  = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ        CMD_INDEX_READ        //!< 0
+#define NOR_CMD_INDEX_READSTATUS  CMD_INDEX_READSTATUS  //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE   5                     //!< 5
+#define NOR_CMD_INDEX_DUMMY       6                     //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK  7                     //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK  8 //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t reserved0[2];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t reserve2[11];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__ */

From a6e0b598faf31a326f031e0386afe97de1712025 Mon Sep 17 00:00:00 2001
From: Dave Nadler <drn@nadler.com>
Date: Fri, 20 Jan 2023 13:15:42 -0500
Subject: [PATCH 1417/2085] Add support for NXP's mimxrt1024_evk evaluation
 board. Tested AOK with device\cdc_msc_freertos example.

---
 hw/bsp/imxrt/boards/mimxrt1024_evk/{mimxrt1024_evk => }/board.h   | 0
 hw/bsp/imxrt/boards/mimxrt1024_evk/{mimxrt1024_evk => }/board.mk  | 0
 .../{mimxrt1024_evk => }/evkmimxrt1024_flexspi_nor_config.c       | 0
 .../{mimxrt1024_evk => }/evkmimxrt1024_flexspi_nor_config.h       | 0
 4 files changed, 0 insertions(+), 0 deletions(-)
 rename hw/bsp/imxrt/boards/mimxrt1024_evk/{mimxrt1024_evk => }/board.h (100%)
 rename hw/bsp/imxrt/boards/mimxrt1024_evk/{mimxrt1024_evk => }/board.mk (100%)
 rename hw/bsp/imxrt/boards/mimxrt1024_evk/{mimxrt1024_evk => }/evkmimxrt1024_flexspi_nor_config.c (100%)
 rename hw/bsp/imxrt/boards/mimxrt1024_evk/{mimxrt1024_evk => }/evkmimxrt1024_flexspi_nor_config.h (100%)

diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
similarity index 100%
rename from hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.h
rename to hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
similarity index 100%
rename from hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/board.mk
rename to hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c b/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c
similarity index 100%
rename from hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c
rename to hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h
similarity index 100%
rename from hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h
rename to hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h

From 18c3095346159a4f5c3db9775b4f7c6aebca77c2 Mon Sep 17 00:00:00 2001
From: Nathaniel Brough <nathaniel.brough@gmail.com>
Date: Fri, 20 Jan 2023 15:40:32 -0800
Subject: [PATCH 1418/2085] fix: Change all static variables to thread when
 fuzzing

---
 .vscode/settings.json                       |  3 +++
 src/class/cdc/cdc_device.c                  |  2 +-
 src/class/dfu/dfu_device.c                  | 14 +++++++-------
 src/class/hid/hid_device.c                  |  2 +-
 src/class/msc/msc_device.c                  |  8 ++++----
 src/class/net/ecm_rndis_device.c            | 14 +++++++-------
 src/class/net/ncm_device.c                  | 12 ++++++------
 src/class/usbtmc/usbtmc_device.c            |  8 ++++----
 src/class/vendor/vendor_device.c            |  2 +-
 src/class/vendor/vendor_device.h            |  2 +-
 src/class/video/video_device.c              |  8 ++++----
 src/common/tusb_compiler.h                  |  7 +++++++
 src/common/tusb_debug.h                     |  2 +-
 src/common/tusb_types.h                     |  4 ++--
 src/device/usbd.c                           | 18 +++++++++---------
 src/device/usbd_control.c                   |  4 ++--
 test/fuzz/dcd_fuzz.cc                       |  2 +-
 test/fuzz/device/msc/src/usb_descriptors.cc |  4 ++--
 test/fuzz/device/net/src/usb_descriptors.cc |  4 ++--
 test/fuzz/make.mk                           |  3 ++-
 20 files changed, 67 insertions(+), 56 deletions(-)
 create mode 100644 .vscode/settings.json

diff --git a/.vscode/settings.json b/.vscode/settings.json
new file mode 100644
index 000000000..97924983a
--- /dev/null
+++ b/.vscode/settings.json
@@ -0,0 +1,3 @@
+{
+    "editor.formatOnSave": false
+}
\ No newline at end of file
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 8d10a416c..b943c1caf 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -76,7 +76,7 @@ typedef struct
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
+CFG_TUSB_MEM_SECTION TU_STATIC cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
 
 static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
 {
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index aa5891ca9..a318603d3 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -56,7 +56,7 @@ typedef struct
 } dfu_state_ctx_t;
 
 // Only a single dfu state is allowed
-CFG_TUSB_MEM_SECTION static dfu_state_ctx_t _dfu_ctx;
+CFG_TUSB_MEM_SECTION TU_STATIC dfu_state_ctx_t _dfu_ctx;
 
 static void reset_state(void)
 {
@@ -74,7 +74,7 @@ static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_cont
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
 
-static tu_lookup_entry_t const _dfu_request_lookup[] =
+TU_STATIC tu_lookup_entry_t const _dfu_request_lookup[] =
 {
   { .key = DFU_REQUEST_DETACH         , .data = "DETACH"    },
   { .key = DFU_REQUEST_DNLOAD         , .data = "DNLOAD"    },
@@ -85,13 +85,13 @@ static tu_lookup_entry_t const _dfu_request_lookup[] =
   { .key = DFU_REQUEST_ABORT          , .data = "ABORT"     },
 };
 
-static tu_lookup_table_t const _dfu_request_table =
+TU_STATIC tu_lookup_table_t const _dfu_request_table =
 {
   .count = TU_ARRAY_SIZE(_dfu_request_lookup),
   .items = _dfu_request_lookup
 };
 
-static tu_lookup_entry_t const _dfu_state_lookup[] =
+TU_STATIC tu_lookup_entry_t const _dfu_state_lookup[] =
 {
   { .key = APP_IDLE                   , .data = "APP_IDLE"                },
   { .key = APP_DETACH                 , .data = "APP_DETACH"              },
@@ -106,13 +106,13 @@ static tu_lookup_entry_t const _dfu_state_lookup[] =
   { .key = DFU_ERROR                  , .data = "ERROR"               },
 };
 
-static tu_lookup_table_t const _dfu_state_table =
+TU_STATIC tu_lookup_table_t const _dfu_state_table =
 {
   .count = TU_ARRAY_SIZE(_dfu_state_lookup),
   .items = _dfu_state_lookup
 };
 
-static tu_lookup_entry_t const _dfu_status_lookup[] =
+TU_STATIC tu_lookup_entry_t const _dfu_status_lookup[] =
 {
   { .key = DFU_STATUS_OK               , .data = "OK"              },
   { .key = DFU_STATUS_ERR_TARGET       , .data = "errTARGET"       },
@@ -132,7 +132,7 @@ static tu_lookup_entry_t const _dfu_status_lookup[] =
   { .key = DFU_STATUS_ERR_STALLEDPKT   , .data = "errSTALLEDPKT"   },
 };
 
-static tu_lookup_table_t const _dfu_status_table =
+TU_STATIC tu_lookup_table_t const _dfu_status_table =
 {
   .count = TU_ARRAY_SIZE(_dfu_status_lookup),
   .items = _dfu_status_lookup
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 8077e4deb..c42d1b6de 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -58,7 +58,7 @@ typedef struct
   tusb_hid_descriptor_hid_t const * hid_descriptor;
 } hidd_interface_t;
 
-CFG_TUSB_MEM_SECTION static hidd_interface_t _hidd_itf[CFG_TUD_HID];
+CFG_TUSB_MEM_SECTION TU_STATIC hidd_interface_t _hidd_itf[CFG_TUD_HID];
 
 /*------------- Helpers -------------*/
 static inline uint8_t get_index_by_itfnum(uint8_t itf_num)
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 00b0a1d06..bf56ed9bf 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -71,8 +71,8 @@ typedef struct
   uint8_t add_sense_qualifier;
 }mscd_interface_t;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static mscd_interface_t _mscd_itf;
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC mscd_interface_t _mscd_itf;
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE];
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -202,7 +202,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
 
-TU_ATTR_UNUSED static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
+TU_ATTR_UNUSED TU_STATIC tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
 {
   { .key = SCSI_CMD_TEST_UNIT_READY              , .data = "Test Unit Ready" },
   { .key = SCSI_CMD_INQUIRY                      , .data = "Inquiry" },
@@ -217,7 +217,7 @@ TU_ATTR_UNUSED static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
   { .key = SCSI_CMD_WRITE_10                     , .data = "Write10" }
 };
 
-TU_ATTR_UNUSED static tu_lookup_table_t const _msc_scsi_cmd_table =
+TU_ATTR_UNUSED TU_STATIC tu_lookup_table_t const _msc_scsi_cmd_table =
 {
   .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup),
   .items = _msc_scsi_cmd_lookup
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index c7428bcda..560e1768d 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -61,8 +61,8 @@ typedef struct
 #define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t)
 #define CFG_TUD_NET_PACKET_SUFFIX_LEN 0
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
 
 struct ecm_notify_struct
 {
@@ -70,7 +70,7 @@ struct ecm_notify_struct
   uint32_t downlink, uplink;
 };
 
-static const struct ecm_notify_struct ecm_notify_nc =
+TU_STATIC const struct ecm_notify_struct ecm_notify_nc =
 {
   .header = {
     .bmRequestType = 0xA1,
@@ -80,7 +80,7 @@ static const struct ecm_notify_struct ecm_notify_nc =
   },
 };
 
-static const struct ecm_notify_struct ecm_notify_csc =
+TU_STATIC const struct ecm_notify_struct ecm_notify_csc =
 {
   .header = {
     .bmRequestType = 0xA1,
@@ -92,7 +92,7 @@ static const struct ecm_notify_struct ecm_notify_csc =
 };
 
 // TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static union
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC union
 {
   uint8_t rndis_buf[120];
   struct ecm_notify_struct ecm_buf;
@@ -102,9 +102,9 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static union
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // TODO remove CFG_TUSB_MEM_SECTION
-CFG_TUSB_MEM_SECTION static netd_interface_t _netd_itf;
+CFG_TUSB_MEM_SECTION TU_STATIC netd_interface_t _netd_itf;
 
-static bool can_xmit;
+TU_STATIC bool can_xmit;
 
 void tud_network_recv_renew(void)
 {
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 1cbc0ce01..236232191 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -130,7 +130,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parameters = {
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC const ntb_parameters_t ntb_parameters = {
     .wLength                 = sizeof(ntb_parameters_t),
     .bmNtbFormatsSupported   = 0x01,
     .dwNtbInMaxSize          = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
@@ -145,11 +145,11 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static const ntb_parameters_t ntb_parame
     .wNtbOutMaxDatagrams     = 0
 };
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static transmit_ntb_t transmit_ntb[2];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC transmit_ntb_t transmit_ntb[2];
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
 
-static ncm_interface_t ncm_interface;
+TU_STATIC ncm_interface_t ncm_interface;
 
 /*
  * Set up the NTB state in ncm_interface to be ready to add datagrams.
@@ -196,7 +196,7 @@ static void ncm_start_tx(void) {
   ncm_prepare_for_tx();
 }
 
-static struct ecm_notify_struct ncm_notify_connected =
+TU_STATIC struct ecm_notify_struct ncm_notify_connected =
 {
     .header = {
         .bmRequestType_bit = {
@@ -210,7 +210,7 @@ static struct ecm_notify_struct ncm_notify_connected =
     },
 };
 
-static struct ecm_notify_struct ncm_notify_speed_change =
+TU_STATIC struct ecm_notify_struct ncm_notify_speed_change =
 {
     .header = {
         .bmRequestType_bit = {
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 0cf0743a7..fd8220c1f 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -78,7 +78,7 @@
 
 #ifdef xDEBUG
 #include "uart_util.h"
-static char logMsg[150];
+TU_STATIC char logMsg[150];
 #endif
 
 // Buffer size must be an exact multiple of the max packet size for both
@@ -143,7 +143,7 @@ typedef struct
   usbtmc_capabilities_specific_t const * capabilities;
 } usbtmc_interface_state_t;
 
-CFG_TUSB_MEM_SECTION static usbtmc_interface_state_t usbtmc_state =
+CFG_TUSB_MEM_SECTION TU_STATIC usbtmc_interface_state_t usbtmc_state =
 {
     .itf_id = 0xFF,
 };
@@ -154,8 +154,8 @@ TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small");
 static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len);
 static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen);
 
-static uint8_t termChar;
-static uint8_t termCharRequested = false;
+TU_STATIC uint8_t termChar;
+TU_STATIC uint8_t termCharRequested = false;
 
 #if OSAL_MUTEX_REQUIRED
 static OSAL_MUTEX_DEF(usbtmcLockBuffer);
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 3b81a108f..b33cbcf13 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -59,7 +59,7 @@ typedef struct
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE];
 } vendord_interface_t;
 
-CFG_TUSB_MEM_SECTION static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
+CFG_TUSB_MEM_SECTION TU_STATIC vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
 
 #define ITF_MEM_RESET_SIZE   offsetof(vendord_interface_t, rx_ff)
 
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index 4a873e5fc..543500f0c 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -50,7 +50,7 @@ void     tud_vendor_n_read_flush      (uint8_t itf);
 uint32_t tud_vendor_n_write           (uint8_t itf, void const* buffer, uint32_t bufsize);
 uint32_t tud_vendor_n_write_available (uint8_t itf);
 
-static inline
+TU_STATIC inline
 uint32_t tud_vendor_n_write_str       (uint8_t itf, char const* str);
 uint32_t tud_vendor_n_flush           (uint8_t itf);
 
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index e17d0a90f..14518deac 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -125,11 +125,11 @@ typedef struct TU_ATTR_PACKED {
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
-CFG_TUSB_MEM_SECTION static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
+CFG_TUSB_MEM_SECTION TU_STATIC videod_interface_t _videod_itf[CFG_TUD_VIDEO];
+CFG_TUSB_MEM_SECTION TU_STATIC videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
 
-static uint8_t const _cap_get     = 0x1u; /* support for GET */
-static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
+TU_STATIC uint8_t const _cap_get     = 0x1u; /* support for GET */
+TU_STATIC uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
 
 /** Get interface number from the interface descriptor
  *
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 2c30daf6f..6a02959ca 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -61,6 +61,13 @@
   #define TU_VERIFY_STATIC(const_expr, _mess) enum { TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1/(!!(const_expr)) }
 #endif
 
+/* --------------------- Fuzzing types -------------------------------------- */
+#ifdef FUZZ
+  #define TU_STATIC __thread static
+#else
+  #define TU_STATIC static
+#endif
+
 // for declaration of reserved field, make use of _TU_COUNTER_
 #define TU_RESERVED           TU_XSTRCAT(reserved, _TU_COUNTER_)
 
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 65fd1920d..8587b6771 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -114,7 +114,7 @@ typedef struct
 
 static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
 {
-  static char not_found[11];
+  TU_STATIC char not_found[11];
 
   for(uint16_t i=0; i<p_table->count; i++)
   {
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 32cdba450..56f782ca3 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -529,13 +529,13 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpo
 #if CFG_TUSB_DEBUG
 TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir)
 {
-  static const char *str[] = {"out", "in"};
+  TU_STATIC const char *str[] = {"out", "in"};
   return str[dir];
 }
 
 TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t)
 {
-  static const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
+  TU_STATIC const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
   return str[t];
 }
 #endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 6e0c6710d..72fa2bd4c 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -76,7 +76,7 @@ typedef struct
 
 }usbd_device_t;
 
-static usbd_device_t _usbd_dev;
+TU_STATIC usbd_device_t _usbd_dev;
 
 //--------------------------------------------------------------------+
 // Class Driver
@@ -88,7 +88,7 @@ static usbd_device_t _usbd_dev;
 #endif
 
 // Built-in class drivers
-static usbd_class_driver_t const _usbd_driver[] =
+TU_STATIC usbd_class_driver_t const _usbd_driver[] =
 {
   #if CFG_TUD_CDC
   {
@@ -238,8 +238,8 @@ static usbd_class_driver_t const _usbd_driver[] =
 enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) };
 
 // Additional class drivers implemented by application
-static usbd_class_driver_t const * _app_driver = NULL;
-static uint8_t _app_driver_count = 0;
+TU_STATIC usbd_class_driver_t const * _app_driver = NULL;
+TU_STATIC uint8_t _app_driver_count = 0;
 
 // virtually joins built-in and application drivers together.
 // Application is positioned first to allow overwriting built-in ones.
@@ -265,17 +265,17 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 //--------------------------------------------------------------------+
 
 enum { RHPORT_INVALID = 0xFFu };
-static uint8_t _usbd_rhport = RHPORT_INVALID;
+TU_STATIC uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // usbd_int_set() is used as mutex in OS NONE config
 OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
-static osal_queue_t _usbd_q;
+TU_STATIC osal_queue_t _usbd_q;
 
 // Mutex for claiming endpoint
 #if OSAL_MUTEX_REQUIRED
-  static osal_mutex_def_t _ubsd_mutexdef;
-  static osal_mutex_t _usbd_mutex;
+  TU_STATIC osal_mutex_def_t _ubsd_mutexdef;
+  TU_STATIC osal_mutex_t _usbd_mutex;
 #else
   #define _usbd_mutex   NULL
 #endif
@@ -299,7 +299,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event,
 // Debug
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
-static char const* const _usbd_event_str[DCD_EVENT_COUNT] =
+TU_STATIC char const* const _usbd_event_str[DCD_EVENT_COUNT] =
 {
   "Invalid"        ,
   "Bus Reset"      ,
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 0995ef669..c3ff7459d 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -53,10 +53,10 @@ typedef struct
   usbd_control_xfer_cb_t complete_cb;
 } usbd_control_xfer_t;
 
-static usbd_control_xfer_t _ctrl_xfer;
+TU_STATIC usbd_control_xfer_t _ctrl_xfer;
 
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
-static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
+TU_STATIC uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
 
 //--------------------------------------------------------------------+
 // Application API
diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc
index 7153e20f0..04b5ce6d7 100644
--- a/test/fuzz/dcd_fuzz.cc
+++ b/test/fuzz/dcd_fuzz.cc
@@ -39,7 +39,7 @@ struct State {
   uint8_t address;
 };
 
-static State state = {false, 0, 0};
+TU_STATIC State state = {false, 0, 0};
 
 //--------------------------------------------------------------------+
 // Controller API
diff --git a/test/fuzz/device/msc/src/usb_descriptors.cc b/test/fuzz/device/msc/src/usb_descriptors.cc
index ded401fc9..91db232ac 100644
--- a/test/fuzz/device/msc/src/usb_descriptors.cc
+++ b/test/fuzz/device/msc/src/usb_descriptors.cc
@@ -44,7 +44,7 @@
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
 uint8_t const *tud_descriptor_device_cb(void) {
-  static tusb_desc_device_t const desc_device = {
+  TU_STATIC tusb_desc_device_t const desc_device = {
       .bLength = sizeof(tusb_desc_device_t),
       .bDescriptorType = TUSB_DESC_DEVICE,
       .bcdUSB = USB_BCD,
@@ -184,7 +184,7 @@ char const *string_desc_arr[] = {
 
 };
 
-static uint16_t _desc_str[32];
+TU_STATIC uint16_t _desc_str[32];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long
diff --git a/test/fuzz/device/net/src/usb_descriptors.cc b/test/fuzz/device/net/src/usb_descriptors.cc
index c600bd801..0223ed298 100644
--- a/test/fuzz/device/net/src/usb_descriptors.cc
+++ b/test/fuzz/device/net/src/usb_descriptors.cc
@@ -45,7 +45,7 @@
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
 uint8_t const *tud_descriptor_device_cb(void) {
-  static tusb_desc_device_t const desc_device = {
+  TU_STATIC tusb_desc_device_t const desc_device = {
       .bLength = sizeof(tusb_desc_device_t),
       .bDescriptorType = TUSB_DESC_DEVICE,
       .bcdUSB = USB_BCD,
@@ -189,7 +189,7 @@ char const *string_desc_arr[] = {
     "TinyUSB CDC",              // 4: CDC Interface
 };
 
-static uint16_t _desc_str[32];
+TU_STATIC uint16_t _desc_str[32];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long
diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk
index 6717ebc80..5e8658ad0 100644
--- a/test/fuzz/make.mk
+++ b/test/fuzz/make.mk
@@ -78,7 +78,8 @@ CFLAGS += \
 CFLAGS += \
 	-Wno-error=unreachable-code \
   -DOPT_MCU_FUZZ=1 \
-  -DCFG_TUSB_MCU=OPT_MCU_FUZZ 
+  -DCFG_TUSB_MCU=OPT_MCU_FUZZ \
+  -DFUZZ
 
 CXXFLAGS += \
   -xc++ \

From 1bbeb6ad79fa1e76c109592773e0834e1ec00a0c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 21 Jan 2023 11:32:37 +0700
Subject: [PATCH 1419/2085] update stm32f1 to support iar build

---
 .github/workflows/build_iar.yml               |  1 +
 examples/rules.mk                             |  4 +++
 .../stm32f0/boards/stm32f070rbnucleo/board.mk |  4 ++-
 hw/bsp/stm32f0/boards/stm32f072disco/board.mk |  2 +-
 hw/bsp/stm32f0/boards/stm32f072eval/board.mk  |  2 +-
 hw/bsp/stm32f0/family.mk                      | 11 ++++---
 .../boards/stm32f103_bluepill/board.mk        | 10 ++++--
 .../stm32f103_bluepill/stm32f103x8_flash.icf  | 31 +++++++++++++++++++
 .../stm32f1/boards/stm32f103_mini_2/board.mk  | 10 ++++--
 hw/bsp/stm32f1/family.c                       |  5 +--
 hw/bsp/stm32f1/family.mk                      | 15 +++++++--
 src/common/tusb_compiler.h                    |  4 +--
 12 files changed, 79 insertions(+), 20 deletions(-)
 create mode 100644 hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 4c43400ab..40c7d7f26 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -28,6 +28,7 @@ jobs:
         family:
         # Alphabetical order
         - 'stm32f0'
+        - 'stm32f1'
     steps:
     - name: Clean workspace
       run: |
diff --git a/examples/rules.mk b/examples/rules.mk
index 19ecbc9e1..6a62288ce 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -72,6 +72,10 @@ ifdef LD_FILE
 LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE)
 endif
 
+ifdef GCC_LD_FILE
+LDFLAGS += -Wl,-T,$(TOP)/$(GCC_LD_FILE)
+endif
+
 ifneq ($(SKIP_NANOLIB), 1)
 LDFLAGS += -specs=nosys.specs -specs=nano.specs
 endif
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
index f470b80f0..cf787a103 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
@@ -1,8 +1,10 @@
 CFLAGS += -DSTM32F070xB -DCFG_EXAMPLE_VIDEO_READONLY
 
+# GCC
 GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
-LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld
+GCC_LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld
 
+# IAR
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f070xb.s
 IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f070xb_flash.icf
 
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
index edee9b0e8..4216ba186 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
@@ -1,7 +1,7 @@
 CFLAGS += -DSTM32F072xB -DCFG_EXAMPLE_VIDEO_READONLY
 
 GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
-LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
+GCC_LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
 
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
 IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
index 6503d3273..bb9cba22a 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
@@ -1,7 +1,7 @@
 CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY
 
 GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
-LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
+GCC_LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
 
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
 IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index a81ab426f..2983af49e 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -7,13 +7,14 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
   -DCFG_EXAMPLE_MSC_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F0
 
-# --------------
 # GCC Flags
-# --------------
 GCC_CFLAGS += \
   -flto \
   -mthumb \
@@ -25,12 +26,14 @@ GCC_CFLAGS += \
 # suppress warning caused by vendor mcu driver
 GCC_CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
 
-# --------------
 # IAR Flags
-# --------------
 IAR_CFLAGS += --cpu cortex-m0
 IAR_ASFLAGS += --cpu cortex-m0
 
+# ------------------------
+# All source paths should be relative to the top level.
+# ------------------------
+
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
index db64b3a3f..159b3ecb6 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U -DCFG_EXAMPLE_VIDEO_READONLY
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f103xb.s
+IAR_LD_FILE = $(BOARD_PATH)/stm32f103x8_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f103c8
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf b/hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf
new file mode 100644
index 000000000..07601c2e8
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/stm32f103x8_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0800FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x20004FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
index eeda87080..efea75be7 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32F103XC_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F103XC_FLASH.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f103xb.s
+IAR_LD_FILE = $(BOARD_PATH)/stm32f103xc_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f103rc
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index 8fcf9ebd6..246d496c8 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -104,7 +104,8 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
 uint32_t board_button_read(void)
@@ -139,7 +140,7 @@ uint32_t board_millis(void)
 
 void HardFault_Handler (void)
 {
-  asm("bkpt");
+  __asm("BKPT #0\n");
 }
 
 #ifdef  USE_FULL_ASSERT
diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index 3fb2e6e70..4327f1cf8 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -6,19 +6,28 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F1
+
+# GCC Flags
+GCC_CFLAGS += \
   -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m3 \
   -mfloat-abi=soft \
   -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F1
 
-# mcu driver cause following warnings
-#CFLAGS += -Wno-error=unused-parameter
+# IAR Flags
+IAR_CFLAGS += --cpu cortex-m3
+IAR_ASFLAGS += --cpu cortex-m3
 
+# ------------------------
 # All source paths should be relative to the top level.
+# ------------------------
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 2c30daf6f..a0a49d7ec 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -76,9 +76,9 @@
  * - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma)
  *------------------------------------------------------------------*/
 #if !defined(__CCRX__)
-#define TU_ARGS_NUM(...)   _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N())
+#define TU_ARGS_NUM(...)   _TU_NARG(_0, ##__VA_ARGS__, _RSEQ_N())
 #else
-#define TU_ARGS_NUM(...)   _TU_NARG(_0, __VA_ARGS__,_RSEQ_N())
+#define TU_ARGS_NUM(...)   _TU_NARG(_0, __VA_ARGS__, _RSEQ_N())
 #endif
 
 #define _TU_NARG(...)      _GET_NTH_ARG(__VA_ARGS__)

From 436cd5b9b841b37ab16f9d6d378475b2c12d48a5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 21 Jan 2023 14:26:46 +0700
Subject: [PATCH 1420/2085] add icf for f1 mini2

---
 .../stm32f103_mini_2/stm32f103xc_flash.icf    | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 hw/bsp/stm32f1/boards/stm32f103_mini_2/stm32f103xc_flash.icf

diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/stm32f103xc_flash.icf b/hw/bsp/stm32f1/boards/stm32f103_mini_2/stm32f103xc_flash.icf
new file mode 100644
index 000000000..5f8a5ecad
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/stm32f103xc_flash.icf
@@ -0,0 +1,31 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x08000000 ;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2000BFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x400;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

From f4c3f0800d44e19ede428c4d5995910573cf6341 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 21 Jan 2023 17:47:40 +0700
Subject: [PATCH 1421/2085] add test_common_func.c

---
 test/unit-test/test/test_common_func.c | 82 ++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)
 create mode 100644 test/unit-test/test/test_common_func.c

diff --git a/test/unit-test/test/test_common_func.c b/test/unit-test/test/test_common_func.c
new file mode 100644
index 000000000..981531dd7
--- /dev/null
+++ b/test/unit-test/test/test_common_func.c
@@ -0,0 +1,82 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <string.h>
+#include "unity.h"
+
+#include "tusb_common.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+
+//------------- IMPLEMENTATION -------------//
+
+void setUp(void)
+{
+}
+
+void tearDown(void)
+{
+}
+
+void test_TU_ARGS_NUM(void)
+{
+  TEST_ASSERT_EQUAL( 0, TU_ARGS_NUM());
+  TEST_ASSERT_EQUAL( 1, TU_ARGS_NUM(a1));
+  TEST_ASSERT_EQUAL( 2, TU_ARGS_NUM(a1, a2));
+  TEST_ASSERT_EQUAL( 3, TU_ARGS_NUM(a1, a2, a3));
+  TEST_ASSERT_EQUAL( 4, TU_ARGS_NUM(a1, a2, a3, a4));
+  TEST_ASSERT_EQUAL( 5, TU_ARGS_NUM(a1, a2, a3, a4, a5));
+  TEST_ASSERT_EQUAL( 6, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6));
+  TEST_ASSERT_EQUAL( 7, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7));
+  TEST_ASSERT_EQUAL( 8, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8));
+  TEST_ASSERT_EQUAL( 9, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9));
+  TEST_ASSERT_EQUAL(10, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10));
+  TEST_ASSERT_EQUAL(11, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11));
+  TEST_ASSERT_EQUAL(12, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12));
+  TEST_ASSERT_EQUAL(13, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13));
+  TEST_ASSERT_EQUAL(14, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14));
+  TEST_ASSERT_EQUAL(15, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15));
+  TEST_ASSERT_EQUAL(16, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16));
+  TEST_ASSERT_EQUAL(17, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17));
+  TEST_ASSERT_EQUAL(18, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18));
+  TEST_ASSERT_EQUAL(19, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19));
+  TEST_ASSERT_EQUAL(20, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20));
+  TEST_ASSERT_EQUAL(21, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21));
+  TEST_ASSERT_EQUAL(22, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22));
+  TEST_ASSERT_EQUAL(23, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23));
+  TEST_ASSERT_EQUAL(24, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24));
+  TEST_ASSERT_EQUAL(25, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25));
+  TEST_ASSERT_EQUAL(26, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26));
+  TEST_ASSERT_EQUAL(27, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27));
+  TEST_ASSERT_EQUAL(28, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28));
+  TEST_ASSERT_EQUAL(29, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29));
+  TEST_ASSERT_EQUAL(30, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29, a30));
+  TEST_ASSERT_EQUAL(31, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29, a30, a31));
+  TEST_ASSERT_EQUAL(32, TU_ARGS_NUM(a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a20, a21, a22, a23, a24, a25, a26, a27, a28, a29, a30, a31, a32));
+}

From db36075721b266d40703e4f57683858acb4112fc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 22 Jan 2023 11:56:50 +0700
Subject: [PATCH 1422/2085] update f4 to build with iar

---
 hw/bsp/stm32f4/boards/feather_stm32f405/board.mk |  8 ++++++--
 hw/bsp/stm32f4/boards/pyboardv11/board.mk        |  8 ++++++--
 .../stm32f4/boards/stm32f401blackpill/board.mk   |  8 ++++++--
 hw/bsp/stm32f4/boards/stm32f407disco/board.mk    |  9 +++++++--
 .../stm32f4/boards/stm32f411blackpill/board.mk   |  8 ++++++--
 hw/bsp/stm32f4/boards/stm32f411disco/board.mk    |  8 ++++++--
 hw/bsp/stm32f4/boards/stm32f412disco/board.mk    |  8 ++++++--
 hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk   |  8 ++++++--
 hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk   |  8 ++++++--
 hw/bsp/stm32f4/family.c                          |  5 +++--
 hw/bsp/stm32f4/family.mk                         | 16 +++++++++++++---
 11 files changed, 71 insertions(+), 23 deletions(-)

diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk b/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
index 1de56fe5a..1962dd9d8 100644
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F405xx
 
-LD_FILE = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f405xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f405xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f405rg
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.mk b/hw/bsp/stm32f4/boards/pyboardv11/board.mk
index 02dcd1219..0a9100e1e 100644
--- a/hw/bsp/stm32f4/boards/pyboardv11/board.mk
+++ b/hw/bsp/stm32f4/boards/pyboardv11/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F405xx
 
-LD_FILE = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f405xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f405xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f405rg
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
index de0f3d4c7..11f9b81aa 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F401xC
 
-LD_FILE = $(BOARD_PATH)/STM32F401VCTx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f401xc.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F401VCTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f401xc.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f401xc.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f401xc_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f401cc
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.mk b/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
index 212b924b4..a184804d3 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
@@ -1,8 +1,13 @@
 CFLAGS += -DSTM32F407xx
 
-LD_FILE = $(BOARD_PATH)/STM32F407VGTx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F407VGTx_FLASH.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f407xx_flash.icf
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f407vg
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
index 78be4348a..ac15eaa5d 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F411xE
 
-LD_FILE = $(BOARD_PATH)/STM32F411CEUx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F411CEUx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f411xe.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f411xe_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f411ce
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.mk b/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
index 48272acff..c5736050c 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F411xE
 
-LD_FILE = $(BOARD_PATH)/STM32F411VETx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F411VETx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f411xe.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f411xe_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f411ve
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.mk b/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
index 50973f737..7dc3699e0 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F412Zx
 
-LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f412zx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f412zx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f412zg
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
index 50973f737..7dc3699e0 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F412Zx
 
-LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f412zx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f412zx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f412zg
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
index b7b36a8a6..e1f337a7e 100644
--- a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
@@ -1,8 +1,12 @@
 CFLAGS += -DSTM32F439xx
 
-LD_FILE = $(BOARD_PATH)/STM32F439ZITX_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f439xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F439ZITX_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f439xx.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f439xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f439xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f439zi
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index 82d4957e7..674058f50 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -150,7 +150,8 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
 uint32_t board_button_read(void)
@@ -190,7 +191,7 @@ uint32_t board_millis(void)
 
 void HardFault_Handler (void)
 {
-  asm("bkpt");
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 9811d3371..333857499 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -7,18 +7,28 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F4
+
+# GCC Flags
+GCC_CFLAGS += \
   -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F4
+  -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-align
+GCC_CFLAGS += -Wno-error=cast-align
+
+# IAR Flags
+IAR_CFLAGS += --cpu cortex-m4
+IAR_ASFLAGS += --cpu cortex-m4
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \

From 0a4e611e3738189f00ec17ebd831436ed51e15ec Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 22 Jan 2023 12:10:27 +0700
Subject: [PATCH 1423/2085] update stm32f7 to build with iar

---
 .github/workflows/build_iar.yml               |  2 ++
 hw/bsp/stm32f4/family.mk                      |  4 +++
 hw/bsp/stm32f7/boards/stlinkv3mini/board.mk   | 10 +++++--
 hw/bsp/stm32f7/boards/stm32f723disco/board.mk |  9 ++++--
 hw/bsp/stm32f7/boards/stm32f746disco/board.mk |  9 ++++--
 .../stm32f7/boards/stm32f746nucleo/board.mk   |  9 ++++--
 .../stm32f7/boards/stm32f767nucleo/board.mk   |  9 ++++--
 hw/bsp/stm32f7/boards/stm32f769disco/board.mk |  9 ++++--
 hw/bsp/stm32f7/family.c                       |  5 ++--
 hw/bsp/stm32f7/family.mk                      | 30 ++++++++++++++-----
 10 files changed, 73 insertions(+), 23 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 40c7d7f26..1facd8ab9 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -29,6 +29,8 @@ jobs:
         # Alphabetical order
         - 'stm32f0'
         - 'stm32f1'
+        - 'stm32f4'
+        - 'stm32f7'
     steps:
     - name: Clean workspace
       run: |
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 333857499..3da4f7bf8 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -30,6 +30,10 @@ GCC_CFLAGS += -Wno-error=cast-align
 IAR_CFLAGS += --cpu cortex-m4
 IAR_ASFLAGS += --cpu cortex-m4
 
+# -----------------
+# Sources & Include
+# -----------------
+
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
index a18b3231d..c28dae9bf 100644
--- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
@@ -6,9 +6,13 @@ CFLAGS += \
   -DSTM32F723xx \
   -DHSE_VALUE=25000000 \
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
+# GCC
+GCC_LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f723xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f723xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
index 66d9ff8fb..6ddb727c7 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
@@ -5,8 +5,13 @@ CFLAGS += \
   -DSTM32F723xx \
   -DHSE_VALUE=25000000 \
 
-LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
+# GCC
+GCC_LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f723xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f723xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.mk b/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
index 2ba59f67a..ba31baa16 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
@@ -5,8 +5,13 @@ CFLAGS += \
   -DSTM32F746xx \
   -DHSE_VALUE=25000000
 
-LD_FILE = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
+# GCC
+GCC_LD_FILE = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f746xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f746xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
index 3dcf4817e..e4d31040e 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
@@ -5,8 +5,13 @@ CFLAGS += \
   -DSTM32F746xx \
   -DHSE_VALUE=8000000
 
-LD_FILE = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
+# GCC
+GCC_LD_FILE = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f746xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f746xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
index 7710619e5..a460245b2 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
@@ -5,8 +5,13 @@ CFLAGS += \
   -DSTM32F767xx \
 	-DHSE_VALUE=8000000 \
 
-LD_FILE = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f767xx.s
+# GCC
+GCC_LD_FILE = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f767xx.s
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f767xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f767xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f767zi
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.mk b/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
index 45b4a78c7..18f59e8b2 100644
--- a/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
@@ -6,8 +6,13 @@ CFLAGS += \
   -DSTM32F769xx \
   -DHSE_VALUE=25000000 \
 
-LD_FILE = $(BOARD_PATH)/STM32F769ZITx_FLASH.ld
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f769xx.s
+# GCC
+GCC_LD_FILE = $(BOARD_PATH)/STM32F769ZITx_FLASH.ld
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f769xx.s
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f769xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f769xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index 425e6e1bc..536eb0554 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -268,7 +268,8 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
 uint32_t board_button_read(void)
@@ -303,7 +304,7 @@ uint32_t board_millis(void)
 
 void HardFault_Handler (void)
 {
-  asm("bkpt");
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index b8a5d7ead..733769d8b 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -7,14 +7,10 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F7 \
   -DBOARD_TUD_RHPORT=$(PORT)
 
@@ -30,8 +26,26 @@ else
   $(info "Using OTG_FS")
 endif
 
+# GCC Flags
+GCC_CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m7 \
+  -mfloat-abi=hard \
+  -mfpu=fpv5-d16 \
+  -nostdlib -nostartfiles
+
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=shadow -Wno-error=cast-align
+GCC_CFLAGS += -Wno-error=shadow -Wno-error=cast-align
+
+# IAR Flags
+IAR_CFLAGS += --cpu cortex-m7
+IAR_ASFLAGS += --cpu cortex-m7
+
+# -----------------
+# Sources & Include
+# -----------------
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \

From 9b6ef4fcbc6f634d2c20a2c16409fbbf50fca4c6 Mon Sep 17 00:00:00 2001
From: Dave Nadler <drn@nadler.com>
Date: Sun, 22 Jan 2023 12:11:50 -0500
Subject: [PATCH 1424/2085] When tools/top.mk finds it is running on Windows,
 it expects SHELL set to cmd.exe. Some Windows development environments invoke
 a mingw version of gnu make with SHELL set to /bin/sh or /bin/bash (either
 explicitly or by default), in which case tinyUSB make fails when a
 $(shell...) command feeds DOS syntax to sh. We can't just use sh, as many
 Windows environments won't have unix utilities like realpath (used by this
 makefile for sh shell commands).

This fix forces SHELL=cmd.exe on Windows and documents the issue.
Also adds additional documentation to help the next person...

With this fix, tinyUSB can be easily built and debugged in environments like
NXP's MCUxpresso (import as a makefile project).
---
 tools/top.mk | 25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/tools/top.mk b/tools/top.mk
index 84523a557..cefe9884c 100644
--- a/tools/top.mk
+++ b/tools/top.mk
@@ -1,30 +1,41 @@
 ifneq ($(lastword a b),b)
-$(error This Makefile require make 3.81 or newer)
+$(error This Makefile requires make 3.81 or newer)
 endif
 
 # Detect whether shell style is windows or not
 # https://stackoverflow.com/questions/714100/os-detecting-makefile/52062069#52062069
 ifeq '$(findstring ;,$(PATH))' ';'
-CMDEXE := 1
+# PATH contains semicolon - so we're definitely on Windows.
+CMDEXE := 1# makefile shell commands should use syntax for DOS CMD, not unix sh
+# Unfortunately, SHELL may point to sh or bash, which can't accept DOS syntax.
+# $(info top.mk: SHELL=$(SHELL))
+# We can't just use sh, because while sh and/or bash shell may be available,
+# many Windows environments won't have utilities like realpath used below, so...
+SHELL := cmd.exe# Force DOS command shell on Windows.
 endif
 
+#$(info top.mk: SHELL=$(SHELL))
+#$(info top.mk: CMDEXE=$(CMDEXE)...)
+
 # Set TOP to be the path to get from the current directory (where make was
 # invoked) to the top of the tree. $(lastword $(MAKEFILE_LIST)) returns
 # the name of this makefile relative to where make was invoked.
+THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))# this makefile is the one most recently appended to the list of makefiles
+TOP := $(patsubst %/tools/top.mk,%,$(THIS_MAKEFILE))# strip off /tools/top.mk to get for example ../../..
+#$(info top.mk: Initial TOP=$(TOP))
 
-THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
-TOP := $(patsubst %/tools/top.mk,%,$(THIS_MAKEFILE))
-
+# Set TOP to an absolute path, for example /tinyUSB (from ../../..)
 ifeq ($(CMDEXE),1)
 TOP := $(subst \,/,$(shell for %%i in ( $(TOP) ) do echo %%~fi))
 else
 TOP := $(shell realpath $(TOP))
 endif
-#$(info Top directory is $(TOP))
+#$(info top.mk: Top directory is $(TOP))
 
+# Set CURRENT_PATH to the relative path from TOP to the current directory, ie examples/device/cdc_msc_freertos
 ifeq ($(CMDEXE),1)
 CURRENT_PATH := $(subst $(TOP)/,,$(subst \,/,$(shell echo %CD%)))
 else
 CURRENT_PATH := $(shell realpath --relative-to=$(TOP) `pwd`)
 endif
-#$(info Path from top is $(CURRENT_PATH))
+#$(info top.mk: Path from top is $(CURRENT_PATH))

From c3e47c31ccd42b144a8a770ed56b8cdc4c2932cc Mon Sep 17 00:00:00 2001
From: Jonathan Bell <jonathan@raspberrypi.com>
Date: Mon, 5 Dec 2022 11:56:42 +0000
Subject: [PATCH 1425/2085] rp2040: export hw_endpoint_start_next_buffer() and
 hw_endpoint_lock_update()

The next change to the driver requires the export of these functions. Leave the
lock unimplemented for now.

Also move hw_set and hw_clear aliases into the top-level header file.
---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c |  3 ---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |  3 ---
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 25 +++++++++-----------
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 10 ++++++++
 4 files changed, 21 insertions(+), 20 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 4952d29b1..33edf0f1e 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -46,9 +46,6 @@
 /* Low level controller
  *------------------------------------------------------------------*/
 
-#define usb_hw_set hw_set_alias(usb_hw)
-#define usb_hw_clear hw_clear_alias(usb_hw)
-
 // Init these in dcd_init
 static uint8_t *next_buffer_ptr;
 
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 9e6bdad44..28abd7939 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -56,9 +56,6 @@ static_assert(PICO_USB_HOST_INTERRUPT_ENDPOINTS <= USB_MAX_ENDPOINTS, "");
 static struct hw_endpoint ep_pool[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
 #define epx (ep_pool[0])
 
-#define usb_hw_set   hw_set_alias(usb_hw)
-#define usb_hw_clear hw_clear_alias(usb_hw)
-
 // Flags we set by default in sie_ctrl (we add other bits on top)
 enum {
   SIE_CTRL_BASE = USB_SIE_CTRL_SOF_EN_BITS      | USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 5c7645902..77d5f2f8f 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -38,14 +38,11 @@ const char *ep_dir_string[] = {
         "in",
 };
 
-TU_ATTR_ALWAYS_INLINE static inline void _hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) {
-    // todo add critsec as necessary to prevent issues between worker and IRQ...
-    //  note that this is perhaps as simple as disabling IRQs because it would make
-    //  sense to have worker and IRQ on same core, however I think using critsec is about equivalent.
-}
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+volatile uint32_t last_sof = 0;
+#endif
 
 static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
-static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
 
 // if usb hardware is in host mode
 TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void)
@@ -157,7 +154,7 @@ static uint32_t __tusb_irq_path_func(prepare_ep_buffer)(struct hw_endpoint *ep,
 }
 
 // Prepare buffer control register value
-static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpoint *ep)
+void __tusb_irq_path_func(hw_endpoint_start_next_buffer)(struct hw_endpoint *ep)
 {
   uint32_t ep_ctrl = *ep->endpoint_control;
 
@@ -201,7 +198,7 @@ static void __tusb_irq_path_func(_hw_endpoint_start_next_buffer)(struct hw_endpo
 
 void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len)
 {
-  _hw_endpoint_lock_update(ep, 1);
+  hw_endpoint_lock_update(ep, 1);
 
   if ( ep->active )
   {
@@ -218,8 +215,8 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
   ep->active        = true;
   ep->user_buf      = buffer;
 
-  _hw_endpoint_start_next_buffer(ep);
-  _hw_endpoint_lock_update(ep, -1);
+  hw_endpoint_start_next_buffer(ep);
+  hw_endpoint_lock_update(ep, -1);
 }
 
 // sync endpoint buffer and return transferred bytes
@@ -312,7 +309,7 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep
 // Returns true if transfer is complete
 bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
 {
-  _hw_endpoint_lock_update(ep, 1);
+  hw_endpoint_lock_update(ep, 1);
   // Part way through a transfer
   if (!ep->active)
   {
@@ -329,15 +326,15 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
     pico_trace("Completed transfer of %d bytes on ep %d %s\n",
                ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
     // Notify caller we are done so it can notify the tinyusb stack
-    _hw_endpoint_lock_update(ep, -1);
+    hw_endpoint_lock_update(ep, -1);
     return true;
   }
   else
   {
-    _hw_endpoint_start_next_buffer(ep);
+    hw_endpoint_start_next_buffer(ep);
   }
 
-  _hw_endpoint_lock_update(ep, -1);
+  hw_endpoint_lock_update(ep, -1);
   // More work to do
   return false;
 }
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index b65d32fd4..be1f1e5ec 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -26,6 +26,9 @@
 #define __tusb_irq_path_func(x) x
 #endif
 
+#define usb_hw_set hw_set_alias(usb_hw)
+#define usb_hw_clear hw_clear_alias(usb_hw)
+
 #define pico_info(...)  TU_LOG(2, __VA_ARGS__)
 #define pico_trace(...) TU_LOG(3, __VA_ARGS__)
 
@@ -79,6 +82,13 @@ void rp2040_usb_init(void);
 void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len);
 bool hw_endpoint_xfer_continue(struct hw_endpoint *ep);
 void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
+void hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
+
+TU_ATTR_ALWAYS_INLINE static inline void hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) {
+  // todo add critsec as necessary to prevent issues between worker and IRQ...
+  //  note that this is perhaps as simple as disabling IRQs because it would make
+  //  sense to have worker and IRQ on same core, however I think using critsec is about equivalent.
+}
 
 void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask);
 

From df2ebe5d1a5da6b232704c2b6a35e66823f4127d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 24 Jan 2023 12:57:07 +0700
Subject: [PATCH 1426/2085] add iar --fpu option

---
 hw/bsp/stm32f4/family.mk | 4 ++--
 hw/bsp/stm32f7/family.mk | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 3da4f7bf8..e8352bad7 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -27,8 +27,8 @@ GCC_CFLAGS += \
 GCC_CFLAGS += -Wno-error=cast-align
 
 # IAR Flags
-IAR_CFLAGS += --cpu cortex-m4
-IAR_ASFLAGS += --cpu cortex-m4
+IAR_CFLAGS += --cpu cortex-m4 --fpu VFPv4
+IAR_ASFLAGS += --cpu cortex-m4 --fpu VFPv4
 
 # -----------------
 # Sources & Include
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index 733769d8b..781b8bb18 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -40,8 +40,8 @@ GCC_CFLAGS += \
 GCC_CFLAGS += -Wno-error=shadow -Wno-error=cast-align
 
 # IAR Flags
-IAR_CFLAGS += --cpu cortex-m7
-IAR_ASFLAGS += --cpu cortex-m7
+IAR_CFLAGS += --cpu cortex-m7 --fpu VFPv5_D16
+IAR_ASFLAGS += --cpu cortex-m7 --fpu VFPv5_D16
 
 # -----------------
 # Sources & Include

From 73b0047efc4cc657a92b356dd9b5046a44277b33 Mon Sep 17 00:00:00 2001
From: Jonathan Bell <jonathan@raspberrypi.com>
Date: Thu, 5 Jan 2023 13:36:51 +0000
Subject: [PATCH 1427/2085] rp2040: avoid device-mode state machine hang

Don't mark IN buffers as available during the last 200us of a full-speed
frame. This avoids a situation seen with the USB2.0 hub on a Raspberry
Pi 4 where a late IN token before the next full-speed SOF can cause port
babble and a corrupt ACK packet. The nature of the data corruption has a
chance to cause device lockup.

Use the next SOF to mark delayed buffers as available. This reduces
available Bulk IN bandwidth by approximately 20%, and requires that the
SOF interrupt is enabled while these transfers are ongoing.

Inherit the top-level enable from the corresponding Pico-SDK flag.
Applications that will not use the device in a situation where it could
be plugged into a Pi 4 or Pi 400 (for example, when directly connected
to a commodity hub or other host) can turn off the flag in the SDK.

v2: use a field in hw_endpoint to mark pending.

v3: Partial rewrite following review comments

- Stub functions out if the workaround is not required
- Only force-enable SOF while any vulnerable endpoints are active
- Respect dcd_sof_enable() functionality
- Get rid of all but necessary ifdef hackery
- Fix a bug where the "endpoint lock" was used with an uninitialised pointer.
---
 hw/bsp/rp2040/family.cmake                   |  1 +
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 25 ++++++++-
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 54 +++++++++++++++++---
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 24 ++++++++-
 4 files changed, 96 insertions(+), 8 deletions(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 5dba9dc39..f83120567 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -116,6 +116,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 
 	target_compile_definitions(tinyusb_additions INTERFACE
 		PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1
+		PICO_RP2040_USB_DEVICE_UFRAME_FIX=1
 	)
 
 	if(DEFINED LOG)
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 33edf0f1e..35faba628 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -246,13 +246,32 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
 {
     uint32_t const status = usb_hw->ints;
     uint32_t handled = 0;
+    bool keep_sof_alive = false;
 
     if (status & USB_INTF_DEV_SOF_BITS)
     {
       handled |= USB_INTF_DEV_SOF_BITS;
 
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+      last_sof = time_us_32();
+
+      for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++) {
+        struct hw_endpoint *ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN);
+        hw_endpoint_lock_update(ep, 1);
+        // Bulk IN endpoint in a transfer?
+        if (rp2040_ep_needs_sof(ep) && ep->active)
+          keep_sof_alive = true;
+        // Deferred enable?
+        if (ep->pending) {
+          hw_endpoint_start_next_buffer(ep);
+          ep->pending = 0;
+        }
+        hw_endpoint_lock_update(ep, -1);
+      }
+#endif
       // disable SOF interrupt if it is used for RESUME in remote wakeup
-      if (!_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
+      if (!keep_sof_alive && !_sof_enable)
+        usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
 
       dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true);
     }
@@ -449,7 +468,11 @@ void dcd_sof_enable(uint8_t rhport, bool en)
     usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
   }else
   {
+    // Don't clear immediately if the SOF workaround is in use.
+    // The SOF handler will conditionally disable the interrupt.
+#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
     usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
+#endif
   }
 }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 77d5f2f8f..6a9f162a5 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -38,10 +38,6 @@ const char *ep_dir_string[] = {
         "in",
 };
 
-#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
-volatile uint32_t last_sof = 0;
-#endif
-
 static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
 
 // if usb hardware is in host mode
@@ -54,6 +50,41 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void)
 //
 //--------------------------------------------------------------------+
 
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+volatile uint32_t last_sof = 0;
+
+bool rp2040_critical_frame_period(struct hw_endpoint *ep)
+{
+  uint32_t delta;
+
+  if (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS)
+    return false;
+
+  if (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_OUT ||
+      ep->transfer_type == TUSB_XFER_INTERRUPT ||
+      ep->transfer_type == TUSB_XFER_ISOCHRONOUS)
+    return false;
+
+  /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point.
+   * The device state machine cannot recover from receiving an incorrect PID
+   * when it is expecting an ACK.
+   */
+  delta = time_us_32() - last_sof;
+  if (delta < 800 || delta > 998) {
+    return false;
+  }
+  TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, now, last_sof);
+  return true;
+}
+
+bool rp2040_ep_needs_sof(struct hw_endpoint *ep) {
+  if (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN &&
+      ep->transfer_type == TUSB_XFER_BULK)
+    return true;
+  return false;
+}
+#endif
+
 void rp2040_usb_init(void)
 {
   // Reset usb controller
@@ -215,7 +246,14 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
   ep->active        = true;
   ep->user_buf      = buffer;
 
-  hw_endpoint_start_next_buffer(ep);
+  if (rp2040_ep_needs_sof(ep))
+    usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
+
+  if(!rp2040_critical_frame_period(ep)) {
+    hw_endpoint_start_next_buffer(ep);
+  } else {
+    ep->pending = 1;
+  }
   hw_endpoint_lock_update(ep, -1);
 }
 
@@ -331,7 +369,11 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
   }
   else
   {
-    hw_endpoint_start_next_buffer(ep);
+    if(!rp2040_critical_frame_period(ep)) {
+      hw_endpoint_start_next_buffer(ep);
+    } else {
+      ep->pending = 1;
+    }
   }
 
   hw_endpoint_lock_update(ep, -1);
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index be1f1e5ec..717ec3514 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -11,11 +11,21 @@
 #include "hardware/structs/usb.h"
 #include "hardware/irq.h"
 #include "hardware/resets.h"
+#include "hardware/timer.h"
 
 #if defined(PICO_RP2040_USB_DEVICE_ENUMERATION_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX)
 #define TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX PICO_RP2040_USB_DEVICE_ENUMERATION_FIX
 #endif
 
+#if defined(PICO_RP2040_USB_DEVICE_UFRAME_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX)
+#define TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX PICO_RP2040_USB_DEVICE_UFRAME_FIX
+#endif
+
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+#undef PICO_RP2040_USB_FAST_IRQ
+#define PICO_RP2040_USB_FAST_IRQ 1
+#endif
+
 #ifndef PICO_RP2040_USB_FAST_IRQ
 #define PICO_RP2040_USB_FAST_IRQ 0
 #endif
@@ -67,7 +77,9 @@ typedef struct hw_endpoint
 
     // Interrupt, bulk, etc
     uint8_t transfer_type;
-    
+
+    // Transfer scheduled but not active
+    uint8_t pending;
 #if CFG_TUH_ENABLED
     // Only needed for host
     uint8_t dev_addr;
@@ -77,6 +89,16 @@ typedef struct hw_endpoint
 #endif
 } hw_endpoint_t;
 
+#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+#define rp2040_critical_frame_period(x) false
+#define rp2040_ep_needs_sof(x) false
+#else
+extern volatile uint32_t last_sof;
+
+bool rp2040_critical_frame_period(struct hw_endpoint *ep);
+bool rp2040_ep_needs_sof(struct hw_endpoint *ep);
+#endif
+
 void rp2040_usb_init(void);
 
 void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len);

From 0d2078d295667ef985675c398db7fd6a893be895 Mon Sep 17 00:00:00 2001
From: Jonathan Bell <jonathan@raspberrypi.com>
Date: Tue, 24 Jan 2023 12:02:32 +0000
Subject: [PATCH 1428/2085] rp2040: shuffle hw_endpoint members

Ordering by element size prevents alignment holes, and as a consequence the
host mode version of the struct is the same size as device, as pad bytes at
the end are used instead.
---
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 717ec3514..e7fee3e3a 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -51,7 +51,7 @@ typedef struct hw_endpoint
     // Transfer direction (i.e. IN is rx for host but tx for device)
     // allows us to common up transfer functions
     bool rx;
-    
+
     uint8_t ep_addr;
     uint8_t next_pid;
 
@@ -64,17 +64,19 @@ typedef struct hw_endpoint
     // Buffer pointer in usb dpram
     uint8_t *hw_data_buf;
 
-    // Current transfer information
-    bool active;
-    uint16_t remaining_len;
-    uint16_t xferred_len;
-
     // User buffer in main memory
     uint8_t *user_buf;
 
+    // Current transfer information
+    uint16_t remaining_len;
+    uint16_t xferred_len;
+
     // Data needed from EP descriptor
     uint16_t wMaxPacketSize;
 
+    // Endpoint is in use
+    bool active;
+
     // Interrupt, bulk, etc
     uint8_t transfer_type;
 

From ba017d06693db1e0adb7e2457a22a74b80fe8508 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 26 Jan 2023 12:00:13 +0100
Subject: [PATCH 1429/2085] boards/stm32h7 update gpio clocks

GPIOE was turned on twice, changed to missing GPIOF.
GPIOI is not present on all boards notably STM32H723
so clock in turned on only if present.
---
 hw/bsp/stm32h7/family.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 3964f427a..d55480b4c 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -66,10 +66,12 @@ void board_init(void)
   __HAL_RCC_GPIOC_CLK_ENABLE(); // USB ULPI NXT
   __HAL_RCC_GPIOD_CLK_ENABLE();
   __HAL_RCC_GPIOE_CLK_ENABLE();
-  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
   __HAL_RCC_GPIOG_CLK_ENABLE();
   __HAL_RCC_GPIOH_CLK_ENABLE(); // USB ULPI NXT
+#ifdef __HAL_RCC_GPIOI_CLK_ENABLE
   __HAL_RCC_GPIOI_CLK_ENABLE(); // USB ULPI NXT
+#endif
   __HAL_RCC_GPIOJ_CLK_ENABLE();
 
   // Enable UART Clock

From 42230df71a10254346ea734c3dd48bf5c6c5f3d5 Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 26 Jan 2023 11:49:05 +0100
Subject: [PATCH 1430/2085] Add support for nucleo-h723zg

Mostly copy of stm32h743nucleo.
Linker script generated by STM32CubeIDE.

Since this device has only one HS USB
board.h contains few defines that map on
board HS USB to FS because there is no
ULPI chip mounted on Nucleo board.

For FreeRTOS build:
Set interrupt priority for HS always and for FS if exists.
---
 hw/bsp/stm32h7/boards/stm32h723nucleo/board.h | 131 ++++++++++++
 .../stm32h7/boards/stm32h723nucleo/board.mk   |  13 ++
 .../stm32h723nucleo/stm32h723xx_flash.ld      | 192 ++++++++++++++++++
 hw/bsp/stm32h7/family.c                       |   2 +
 4 files changed, 338 insertions(+)
 create mode 100644 hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
 create mode 100644 hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
 create mode 100644 hw/bsp/stm32h7/boards/stm32h723nucleo/stm32h723xx_flash.ld

diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
new file mode 100644
index 000000000..56a48ec24
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
@@ -0,0 +1,131 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_0
+#define LED_STATE_ON          1
+
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOD
+#define UART_GPIO_AF          GPIO_AF7_USART3
+#define UART_TX_PIN           GPIO_PIN_8
+#define UART_RX_PIN           GPIO_PIN_9
+
+// VBUS Sense detection
+#define OTG_FS_VBUS_SENSE     1
+#define OTG_HS_VBUS_SENSE     0
+
+// STM32F723 has only one USB HS peripheral
+// Nucleo board does not have ULPI so USB will operate in FS mode only
+// For the rest of the synopsys driver it is FS device however there
+// is only USB_OTG_HS defined. Here are required conversions to
+// make peripheral FS.
+#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE __HAL_RCC_USB1_OTG_HS_CLK_ENABLE
+#define GPIO_AF10_OTG2_HS               GPIO_AF10_OTG1_HS
+#define USB_OTG_FS                      USB_OTG_HS
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32h7_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* The PWR block is always enabled on the H7 series- there is no clock
+     enable. For now, use the default VOS3 scale mode (lowest) and limit clock
+     frequencies to avoid potential current draw problems from bus
+     power when using the max clock speeds throughout the chip. */
+
+  /* Enable HSE Oscillator and activate PLL1 with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+  RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000;
+  RCC_OscInitStruct.PLL.PLLN = 336;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  RCC_OscInitStruct.PLL.PLLR = 2; /* Unused */
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | \
+    RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | \
+    RCC_CLOCKTYPE_D3PCLK1);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
+
+  /* Unlike on the STM32F4 family, it appears the maximum APB frequencies are
+     device-dependent- 120 MHz for this board according to Figure 2 of
+     the datasheet. Dividing by half will be safe for now. */
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+
+  /* 4 wait states required for 168MHz and VOS3. */
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+
+  /* Like on F4, on H7, USB's actual peripheral clock and bus clock are
+     separate. However, the main system PLL (PLL1) doesn't have a direct
+     connection to the USB peripheral clock to generate 48 MHz, so we do this
+     dance. This will connect PLL1's Q output to the USB peripheral clock. */
+  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct;
+
+  RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+  HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct);
+}
+
+static inline void board_stm32h7_post_init(void)
+{
+  // For this board does nothing
+}
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
new file mode 100644
index 000000000..bbd0a0e58
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
@@ -0,0 +1,13 @@
+CFLAGS += -DSTM32H723xx -DHSE_VALUE=8000000
+
+# Default is FulSpeed port
+PORT ?= 0
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h723xx.s
+LD_FILE = $(BOARD_PATH)/stm32h723xx_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = stm32h723zg
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/stm32h723xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h723nucleo/stm32h723xx_flash.ld
new file mode 100644
index 000000000..05e0d4e26
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/stm32h723xx_flash.ld
@@ -0,0 +1,192 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32H7 series
+**                1024Kbytes FLASH and 560Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2021 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200 ;      /* required amount of heap  */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+  ITCMRAM (xrw)    : ORIGIN = 0x00000000,   LENGTH = 64K
+  DTCMRAM (xrw)    : ORIGIN = 0x20000000,   LENGTH = 128K
+  FLASH    (rx)    : ORIGIN = 0x08000000,   LENGTH = 1024K
+  RAM_D1  (xrw)    : ORIGIN = 0x24000000,   LENGTH = 320K
+  RAM_D2  (xrw)    : ORIGIN = 0x30000000,   LENGTH = 32K
+  RAM_D3  (xrw)    : ORIGIN = 0x38000000,   LENGTH = 16K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM_D1 AT> FLASH
+
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM_D1
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM_D1
+
+  .usbx_data 0x24027000 (NOLOAD):
+  {
+    *(.UsbHpcdSection)
+
+  } >RAM_D1
+
+  .uart_bss 0x24028000 (NOLOAD):
+  {
+    *(.UsbxAppSection)
+
+  } >RAM_D1
+
+  .usbx_bss 0x24029000 (NOLOAD):
+  {
+    *(.UsbxPoolSection)
+
+  } >RAM_D1
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index d55480b4c..0aa8fe47f 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -86,7 +86,9 @@ void board_init(void)
   SysTick->CTRL &= ~1U;
 
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+#ifdef USB_OTG_FS_PERIPH_BASE
   NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
   

From 02f1f0569723611d591b8bdd72b12a084a4f39d0 Mon Sep 17 00:00:00 2001
From: Nathaniel Brough <nathaniel.brough@gmail.com>
Date: Sun, 29 Jan 2023 09:38:05 -0800
Subject: [PATCH 1431/2085] feat(fuzz): Adds seed corpus for cdc and msc
 classes

---
 test/fuzz/device/cdc/cdc_seed_corpus.zip | Bin 0 -> 50127 bytes
 test/fuzz/device/msc/msc_seed_corpus.zip | Bin 0 -> 50127 bytes
 tools/pcapng_to_corpus.py                |  46 +++++++++++++++++++++++
 3 files changed, 46 insertions(+)
 create mode 100644 test/fuzz/device/cdc/cdc_seed_corpus.zip
 create mode 100644 test/fuzz/device/msc/msc_seed_corpus.zip
 create mode 100755 tools/pcapng_to_corpus.py

diff --git a/test/fuzz/device/cdc/cdc_seed_corpus.zip b/test/fuzz/device/cdc/cdc_seed_corpus.zip
new file mode 100644
index 0000000000000000000000000000000000000000..81bc2240de2701fde0023c5c84ad33d69dadbf9f
GIT binary patch
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zz5Nw;%~L!1C}a}NfW_pVB_be1E>>{9GQ%G88j6!bO3;XmLQptGQdyvETBO5G4hCPZ
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zp#fIn$)PQ@i)iJ(643L92!Z=Np%YFnET-6~8B$h&a&8gh^xdwx>r;2lYp$m-tYzTl
z4rS64WE*l$gw+wuIGhmTfT0L(j7$qk623o$R(Y)_P+IgfZe>#|Q)=dhQ{FQFZtsQ~
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zQ2qrv*b;gvrEMCCCc>tw8=|J`2hcN#@QHc{yd@;4081vgo#j>qM`E2;e%|Z8a{l-t
zW^uZy7wFKkH55?)$XT#ibSRRaXpN;@XK@zmKsbt_rbG{<*nsm4d|T5u3Lq{r9&WmC
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zfK)LBihDfLM$}h=j0{qw;KtgJF<Ey4PP^lh@6U7ca;TBWvJFX=1E=v0U?9;hfsdE;
zIRgbq;#K05_1MzpLJ;NQO#)~fvm*FfA5p#Jd$)gi+^V~flB1r=321>Z`7NSNk_p@+
zbE(_o8k6{`hLi;=k)*RE!lw=s9R^w<J~~&cXg7S=brIEclK6t!ANBYp+ng&tm6GXv
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zbV2Qpp|)M<(kZnmLdk;K(Z7e3Y!k0!N^OcevY>V&)V7O4GNm>J8(C2M)l1noJdy1{
zk4&jeAw(9`J_5Dv0*XwjP5Xux)a<o*LEG#ino^r~11+fiZ>VjzH)u+2+5)to_8YG!
z(@Utaora((wP|C|g4&m$w%s<LDYa=g$Aa1m{ypbyo4p-VYSSK#1+{NMZMz*CQ)<(~
z`~|g_{s*XSvrK<VZCY->pw?YSrgxjg_fu-q8tVnM%ie<K+GfS|l-jhgdO_`8sBO2*
zdP;3tF1?`khPUD?Z?kxMN^M#ry`XmZe{8v+?Nv-qsZA@N7u4Pfwe8kHPpM7Iofp)O
zxgO7ao5jylYSSX-1+|-?w%wBEDYa>7@`Bp#w{ZftS*SdvHZ3?_Q2Qd(wp)ID)@cu+
TCZ_Ao<G=j0t~=+Q?YsXEJ0DX0

literal 0
HcmV?d00001

diff --git a/tools/pcapng_to_corpus.py b/tools/pcapng_to_corpus.py
new file mode 100755
index 000000000..78b1f77a2
--- /dev/null
+++ b/tools/pcapng_to_corpus.py
@@ -0,0 +1,46 @@
+#!/bin/python3
+import argparse
+import pcapng
+import zipfile
+import hashlib
+
+def extract_packets(pcap_file):
+    """Reads a wireshark packet capture and extracts the binary packets"""
+    packets = []
+    with open(pcap_file, 'rb') as fp:
+        scanner = pcapng.FileScanner(fp)
+        for block in scanner:
+            if isinstance(block, pcapng.blocks.EnhancedPacket):
+                packets.append(block.packet_data)
+    return packets
+
+def build_corpus_zip(zip_file_output, packets):
+    """Builds a zip file with a file per packet
+    
+    The structure of this zip corpus is a simple content addressable storage
+    i.e. seed_file_name == sha256_digest(packet).
+    """
+    with zipfile.ZipFile(zip_file_output, 'a') as out:
+        for packet in packets:
+            hash = hashlib.sha256(packet).hexdigest()
+            if hash not in out.namelist():
+                out.writestr(hash, packet)
+    
+
+def main(pcap_file, output_zip_file):
+    packets = extract_packets(pcap_file)
+    build_corpus_zip(output_zip_file, packets)
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(
+        prog = "pcapng_to_corpus.py",
+        description="""Converts a wireshark capture to a zip of binary packet
+                    files suitable for an oss-fuzz corpus. In the case the 
+                    zip corpus already exists, this script will modify 
+                    the zip file in place adding seed entries.""")
+    parser.add_argument('pcapng_capture_file')
+    parser.add_argument('oss_fuzz_corpus_zip')
+    args = parser.parse_args()
+    main(args.pcapng_capture_file, args.oss_fuzz_corpus_zip)
+    
+    

From 11384159e1137860f197fd8f0232c259a1cc3820 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Jan 2023 10:16:57 +0700
Subject: [PATCH 1432/2085] suppress rt1024 warnings and fix typo

---
 hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk            |  3 +++
 .../mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h  | 10 +++++-----
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
index 18b704510..92209992d 100644
--- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
@@ -1,6 +1,9 @@
 CFLAGS += -DCPU_MIMXRT1024DAG5A
 MCU_VARIANT = MIMXRT1024
 
+# warnings caused by mcu driver
+CFLAGS += -Wno-error=array-bounds
+
 # For flash-jlink target
 JLINK_DEVICE = MIMXRT1024DAG5A
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h
index 987a46466..5231dc034 100644
--- a/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.h
@@ -18,7 +18,7 @@
 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
-/* FLEXSPI memory config block related defintions */
+/* FLEXSPI memory config block related definitions */
 #define FLEXSPI_CFG_BLK_TAG     (0x42464346UL) // ascii "FCFB" Big Endian
 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
 #define FLEXSPI_CFG_BLK_SIZE    (512)
@@ -26,7 +26,7 @@
 /* FLEXSPI Feature related definitions */
 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
 
-/* Lookup table related defintions */
+/* Lookup table related definitions */
 #define CMD_INDEX_READ        0
 #define CMD_INDEX_READSTATUS  1
 #define CMD_INDEX_WRITEENABLE 2
@@ -122,7 +122,7 @@ enum
     kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
     kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
     kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
-    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
 };
 
 //!@brief Flash Pad Definitions
@@ -183,7 +183,7 @@ typedef struct _FlexSPIConfig
     //! details
     uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
     uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
-    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
     //! Chapter for more details
     uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
     //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
@@ -251,7 +251,7 @@ typedef struct _flexspi_nor_config
     uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
     uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
     uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
-    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP commmand execution
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
     uint32_t blockSize;             //!< Block size
     uint32_t reserve2[11];          //!< Reserved for future use
 } flexspi_nor_config_t;

From 6dd40603f92a04d695b78a3ee6c0276525960aef Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Jan 2023 11:46:52 +0700
Subject: [PATCH 1433/2085] fix typo

---
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index f4c9b2b27..efca5bdcb 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -1023,7 +1023,7 @@ void dcd_int_handler(uint8_t rhport)
           USBD_EP_SR_REG(USBD_EP_0) = MASK_USBD_EP0SR_STALL;
         }
 
-        // Host has sent a SETUP packet. Recieve this into the SETUP packet store.
+        // Host has sent a SETUP packet. Receive this into the SETUP packet store.
         _ft9xx_dusb_out(USBD_EP_0, (uint8_t *)_ft9xx_setup_packet, sizeof(USB_device_request));
         
         // Send the packet to tinyusb.

From cc1878447990aa01a99351cafe8bd899bd37b4e0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Jan 2023 16:42:56 +0700
Subject: [PATCH 1434/2085] hardcoded configPRIO_BITS for IAR build to pass CI

---
 .../src/FreeRTOSConfig/FreeRTOSConfig.h       | 23 +++++++++++++------
 .../src/FreeRTOSConfig/FreeRTOSConfig.h       | 23 +++++++++++++------
 src/tusb_option.h                             |  6 ++---
 3 files changed, 35 insertions(+), 17 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index efd527ed2..9bef9bbbf 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,8 +42,8 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
-// skip if is compiled with assembler
-#if !defined(__ASSEMBLER__) && !defined(__IASMARM__)
+// skip if included from IAR assembler
+#ifndef __IASMARM__
 
 // Include MCU header
 #include "bsp/board_mcu.h"
@@ -149,10 +149,10 @@
 
 #ifdef __RX__
 /* Renesas RX series */
-#define vSoftwareInterruptISR					INT_Excep_ICU_SWINT
-#define vTickISR								INT_Excep_CMT0_CMI0
-#define configPERIPHERAL_CLOCK_HZ				(configCPU_CLOCK_HZ/2)
-#define configKERNEL_INTERRUPT_PRIORITY			1
+#define vSoftwareInterruptISR					        INT_Excep_ICU_SWINT
+#define vTickISR								              INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ				      (configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY			  1
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
 
 #else
@@ -168,10 +168,19 @@
 #if defined(__NVIC_PRIO_BITS)
   // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
 	#define configPRIO_BITS       __NVIC_PRIO_BITS
+
 #elif defined(__ECLIC_INTCTLBITS)
   // RISC-V Bumblebee core from nuclei
   #define configPRIO_BITS       __ECLIC_INTCTLBITS
-#elif !defined(__ASSEMBLER__) && !defined(__IASMARM__)
+
+#elif defined(__IASMARM__)
+  // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
+  // Therefore we will hard coded it to minimum value of 2 to get pass ci build.
+  // IAR user must update this to correct value of the target MCU
+  #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
+  #define configPRIO_BITS       2
+
+#else
   #error "FreeRTOS configPRIO_BITS to be defined"
 #endif
 
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index efd527ed2..9bef9bbbf 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,8 +42,8 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
-// skip if is compiled with assembler
-#if !defined(__ASSEMBLER__) && !defined(__IASMARM__)
+// skip if included from IAR assembler
+#ifndef __IASMARM__
 
 // Include MCU header
 #include "bsp/board_mcu.h"
@@ -149,10 +149,10 @@
 
 #ifdef __RX__
 /* Renesas RX series */
-#define vSoftwareInterruptISR					INT_Excep_ICU_SWINT
-#define vTickISR								INT_Excep_CMT0_CMI0
-#define configPERIPHERAL_CLOCK_HZ				(configCPU_CLOCK_HZ/2)
-#define configKERNEL_INTERRUPT_PRIORITY			1
+#define vSoftwareInterruptISR					        INT_Excep_ICU_SWINT
+#define vTickISR								              INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ				      (configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY			  1
 #define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
 
 #else
@@ -168,10 +168,19 @@
 #if defined(__NVIC_PRIO_BITS)
   // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
 	#define configPRIO_BITS       __NVIC_PRIO_BITS
+
 #elif defined(__ECLIC_INTCTLBITS)
   // RISC-V Bumblebee core from nuclei
   #define configPRIO_BITS       __ECLIC_INTCTLBITS
-#elif !defined(__ASSEMBLER__) && !defined(__IASMARM__)
+
+#elif defined(__IASMARM__)
+  // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
+  // Therefore we will hard coded it to minimum value of 2 to get pass ci build.
+  // IAR user must update this to correct value of the target MCU
+  #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
+  #define configPRIO_BITS       2
+
+#else
   #error "FreeRTOS configPRIO_BITS to be defined"
 #endif
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 67377b7ec..cf5b21c9c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -27,9 +27,6 @@
 #ifndef _TUSB_OPTION_H_
 #define _TUSB_OPTION_H_
 
-// To avoid GCC compiler warnings when -pedantic option is used (strict ISO C)
-typedef int make_iso_compilers_happy;
-
 #include "common/tusb_compiler.h"
 
 #define TUSB_VERSION_MAJOR     0
@@ -435,6 +432,9 @@ typedef int make_iso_compilers_happy;
   #error Control Endpoint Max Packet Size cannot be larger than 64
 #endif
 
+// To avoid GCC compiler warnings when -pedantic option is used (strict ISO C)
+typedef int make_iso_compilers_happy;
+
 #endif /* _TUSB_OPTION_H_ */
 
 /** @} */

From 63e6aea5ac4aed5a7b405a42c888cec66432ee26 Mon Sep 17 00:00:00 2001
From: Gordon McNab <gordon.mcnab@brtchip.com>
Date: Mon, 30 Jan 2023 10:04:34 +0000
Subject: [PATCH 1435/2085] Removed unrequired header file from debugging.

---
 hw/bsp/brtmm90x/boards/mm900evxb/board.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/hw/bsp/brtmm90x/boards/mm900evxb/board.h b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
index 191803ddf..771779108 100644
--- a/hw/bsp/brtmm90x/boards/mm900evxb/board.h
+++ b/hw/bsp/brtmm90x/boards/mm900evxb/board.h
@@ -35,8 +35,6 @@
  extern "C" {
 #endif
 
-#include <tinyprintf.h>
-
 // UART to use on this board.
 #ifndef BOARD_UART
 #define BOARD_UART UART0

From b464f91a6e6e6cc4975b4acd442133422482daf1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Jan 2023 17:04:39 +0700
Subject: [PATCH 1436/2085] iar h7

---
 .github/workflows/build_iar.yml               |  1 +
 hw/bsp/stm32f7/boards/stlinkv3mini/board.mk   |  2 +-
 hw/bsp/stm32h7/boards/daisyseed/board.mk      |  9 ++++--
 .../stm32h7/boards/stm32h723nucleo/board.mk   |  9 ++++--
 hw/bsp/stm32h7/boards/stm32h743eval/board.mk  |  9 ++++--
 .../stm32h7/boards/stm32h743nucleo/board.mk   |  9 ++++--
 hw/bsp/stm32h7/boards/stm32h745disco/board.mk |  9 ++++--
 .../boards/waveshare_openh743i/board.h        |  4 +--
 .../boards/waveshare_openh743i/board.mk       | 11 +++++--
 hw/bsp/stm32h7/family.c                       |  5 +--
 hw/bsp/stm32h7/family.mk                      | 32 +++++++++++++------
 11 files changed, 72 insertions(+), 28 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 1facd8ab9..e4b449528 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -31,6 +31,7 @@ jobs:
         - 'stm32f1'
         - 'stm32f4'
         - 'stm32f7'
+        - 'stm32h7'
     steps:
     - name: Clean workspace
       run: |
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
index c28dae9bf..e1d352cc9 100644
--- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
@@ -7,8 +7,8 @@ CFLAGS += \
   -DHSE_VALUE=25000000 \
 
 # GCC
-GCC_LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
 GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
 
 # IAR
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f723xx.s
diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.mk b/hw/bsp/stm32h7/boards/daisyseed/board.mk
index 68c62968e..4d718f04e 100644
--- a/hw/bsp/stm32h7/boards/daisyseed/board.mk
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.mk
@@ -3,8 +3,13 @@ CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=16000000
 # Default is FulSpeed port
 PORT ?= 0
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h750xx.s
-LD_FILE = $(BOARD_PATH)/stm32h750ibkx_flash.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h750xx.s
+GCC_LD_FILE = $(BOARD_PATH)/stm32h750ibkx_flash.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h750ibk6_m7
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
index bbd0a0e58..57dfb7e64 100644
--- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
@@ -3,8 +3,13 @@ CFLAGS += -DSTM32H723xx -DHSE_VALUE=8000000
 # Default is FulSpeed port
 PORT ?= 0
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h723xx.s
-LD_FILE = $(BOARD_PATH)/stm32h723xx_flash.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h723xx.s
+GCC_LD_FILE = $(BOARD_PATH)/stm32h723xx_flash.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h723xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h723xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h723zg
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
index b768a0ee6..78ff47c09 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
@@ -4,8 +4,13 @@ CFLAGS += -DSTM32H743xx -DHSE_VALUE=25000000
 PORT ?= 1
 SPEED ?= high
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
+GCC_LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h743xi
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
index fc670fe76..4bdd5b6a8 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
@@ -3,8 +3,13 @@ CFLAGS += -DSTM32H743xx -DHSE_VALUE=8000000
 # Default is FulSpeed port
 PORT ?= 0
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
+GCC_LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h743zi
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
index 384065bde..b51b109f6 100644
--- a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
@@ -6,8 +6,13 @@ CFLAGS += -DSTM32H745xx -DCORE_CM7 -DHSE_VALUE=25000000
 # Default is FulSpeed port
 PORT ?= 0
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h745xx.s
-LD_FILE = $(ST_CMSIS)/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h745xx.s
+GCC_LD_FILE = $(ST_CMSIS)/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h745xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h745xi_m7
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
index 2b072e07c..cf6ad762e 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
@@ -212,9 +212,9 @@ static inline void board_stm32h7_post_init(void)
 
   // Reset PHY, change the delays as you see fit
   timer_board_delay(&tim2Handle, 5U);
-  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 1U);
+  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, GPIO_PIN_SET);
   timer_board_delay(&tim2Handle, 20U);
-  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, 0U);
+  HAL_GPIO_WritePin(ULPI_RST_PORT, ULPI_RST_PIN, GPIO_PIN_RESET);
   timer_board_delay(&tim2Handle, 20U);
 
   //Disable the timer used for delays
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
index 4dfcc1cac..fbf4b55c6 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
@@ -3,15 +3,20 @@ CFLAGS += -DSTM32H743xx -DHSE_VALUE=8000000
 # Default is HS port
 PORT ?= 1
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-LD_FILE = $(BOARD_PATH)/STM32H743IITX_FLASH.ld
-
 # Use Timer module for ULPI PHY reset
 CFLAGS += -DHAL_TIM_MODULE_ENABLED
 SRC_C += \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim_ex.c
 
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32H743IITX_FLASH.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf
+
 # For flash-jlink target
 JLINK_DEVICE = stm32h743ii
 
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 0aa8fe47f..28a2568fa 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -225,7 +225,8 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
 uint32_t board_button_read(void)
@@ -261,7 +262,7 @@ uint32_t board_millis(void)
 
 void HardFault_Handler(void)
 {
-  asm("bkpt");
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index a1cd93b27..834347b4b 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -7,14 +7,10 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32H7 \
 	-DBOARD_TUD_RHPORT=$(PORT)
 
@@ -30,10 +26,26 @@ else
   $(info "Using OTG_FS")
 endif
 
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
+# GCC Flags
+GCC_CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m7 \
+  -mfloat-abi=hard \
+  -mfpu=fpv5-d16 \
+  -nostdlib -nostartfiles
 
-# All source paths should be relative to the top level.
+# suppress warning caused by vendor mcu driver
+GCC_CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
+
+# IAR Flags
+IAR_CFLAGS += --cpu cortex-m7 --fpu VFPv5_D16
+IAR_ASFLAGS += --cpu cortex-m7 --fpu VFPv5_D16
+
+# -----------------
+# Sources & Include
+# -----------------
 
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \

From 63a6fd36890f01ba8e1ed559c53ce2bdd2042475 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Jan 2023 17:07:06 +0700
Subject: [PATCH 1437/2085] iar g4

---
 .github/workflows/build_iar.yml                |  1 +
 hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk |  8 ++++++--
 hw/bsp/stm32g4/family.c                        |  5 +++--
 hw/bsp/stm32g4/family.mk                       | 18 ++++++++++++++++--
 4 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index e4b449528..c948b5d8d 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -31,6 +31,7 @@ jobs:
         - 'stm32f1'
         - 'stm32f4'
         - 'stm32f7'
+        - 'stm32g4'
         - 'stm32h7'
     steps:
     - name: Clean workspace
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
index e41edd3b7..2f6ec0ed6 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
@@ -2,9 +2,13 @@ CFLAGS += \
 	-DSTM32G474xx \
 	-DHSE_VALUE=24000000
 
-LD_FILE = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g474xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g474xx.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32g474xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32g474xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32g474re
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index a2312b0d8..32c46b7d8 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -137,7 +137,8 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
 uint32_t board_button_read(void)
@@ -177,7 +178,7 @@ uint32_t board_millis(void)
 
 void HardFault_Handler (void)
 {
-  asm("bkpt");
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk
index 04222f3bb..79defac56 100644
--- a/hw/bsp/stm32g4/family.mk
+++ b/hw/bsp/stm32g4/family.mk
@@ -7,7 +7,14 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32G4
+  
+# GCC Flags
+GCC_CFLAGS += \
   -flto \
   -mthumb \
   -mabi=aapcs \
@@ -15,10 +22,17 @@ CFLAGS += \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32G4
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-align
+GCC_CFLAGS += -Wno-error=cast-align
+
+# IAR Flags
+IAR_CFLAGS += --cpu cortex-m4 --fpu VFPv4
+IAR_ASFLAGS += --cpu cortex-m4 --fpu VFPv4
+
+# -----------------
+# Sources & Include
+# -----------------
 
 SRC_C += \
 	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \

From 39eb1ce70e6a2246498a4cd2add3516dd9a62a5c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Jan 2023 17:21:48 +0700
Subject: [PATCH 1438/2085] minor clean up

---
 tools/top.mk | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/tools/top.mk b/tools/top.mk
index cefe9884c..af8d698f5 100644
--- a/tools/top.mk
+++ b/tools/top.mk
@@ -6,22 +6,26 @@ endif
 # https://stackoverflow.com/questions/714100/os-detecting-makefile/52062069#52062069
 ifeq '$(findstring ;,$(PATH))' ';'
 # PATH contains semicolon - so we're definitely on Windows.
-CMDEXE := 1# makefile shell commands should use syntax for DOS CMD, not unix sh
+CMDEXE := 1
+
+# makefile shell commands should use syntax for DOS CMD, not unix sh
 # Unfortunately, SHELL may point to sh or bash, which can't accept DOS syntax.
-# $(info top.mk: SHELL=$(SHELL))
 # We can't just use sh, because while sh and/or bash shell may be available,
 # many Windows environments won't have utilities like realpath used below, so...
-SHELL := cmd.exe# Force DOS command shell on Windows.
+# Force DOS command shell on Windows.
+SHELL := cmd.exe
 endif
 
 #$(info top.mk: SHELL=$(SHELL))
-#$(info top.mk: CMDEXE=$(CMDEXE)...)
+#$(info top.mk: CMDEXE=$(CMDEXE))
 
 # Set TOP to be the path to get from the current directory (where make was
 # invoked) to the top of the tree. $(lastword $(MAKEFILE_LIST)) returns
 # the name of this makefile relative to where make was invoked.
-THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))# this makefile is the one most recently appended to the list of makefiles
-TOP := $(patsubst %/tools/top.mk,%,$(THIS_MAKEFILE))# strip off /tools/top.mk to get for example ../../..
+THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
+
+# strip off /tools/top.mk to get for example ../../..
+TOP := $(patsubst %/tools/top.mk,%,$(THIS_MAKEFILE))
 #$(info top.mk: Initial TOP=$(TOP))
 
 # Set TOP to an absolute path, for example /tinyUSB (from ../../..)

From 25603c7269172f64b1dfe55e1224964cc20529ec Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 30 Jan 2023 20:11:59 +0700
Subject: [PATCH 1439/2085] iar L4

---
 .github/workflows/build_iar.yml               |  1 +
 .../stm32l4/boards/stm32l412nucleo/board.mk   |  9 +++++---
 hw/bsp/stm32l4/boards/stm32l476disco/board.mk |  9 +++++---
 .../stm32l4/boards/stm32l4p5nucleo/board.mk   |  9 +++++---
 .../stm32l4/boards/stm32l4r5nucleo/board.mk   |  9 +++++---
 hw/bsp/stm32l4/family.c                       |  5 ++--
 hw/bsp/stm32l4/family.mk                      | 23 +++++++++++++++----
 7 files changed, 46 insertions(+), 19 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index c948b5d8d..9c1bfa18a 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -33,6 +33,7 @@ jobs:
         - 'stm32f7'
         - 'stm32g4'
         - 'stm32h7'
+        - 'stm32l4'
     steps:
     - name: Clean workspace
       run: |
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
index 841ee4948..854397fc8 100644
--- a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
@@ -1,10 +1,13 @@
 CFLAGS += \
   -DSTM32L412xx \
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32L412KBUx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l412xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32L412KBUx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l412xx.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l412xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l412xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l412kb
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.mk b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
index e7b8557a5..125f1f106 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
@@ -1,10 +1,13 @@
 CFLAGS += \
   -DSTM32L476xx \
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l476xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l476xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l476vg
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
index 8252dd838..11edcd9a8 100644
--- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
@@ -1,10 +1,13 @@
 CFLAGS += \
   -DSTM32L4P5xx \
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l4p5xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l4p5xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l4p5zg
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
index 3d7fa227b..6dca88a8b 100644
--- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
@@ -2,10 +2,13 @@ CFLAGS += \
   -DHSE_VALUE=8000000 \
   -DSTM32L4R5xx \
 
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld
 
-SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l4r5xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l4r5xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l4r5zi
diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c
index 0b1443aa0..19b84c086 100644
--- a/hw/bsp/stm32l4/family.c
+++ b/hw/bsp/stm32l4/family.c
@@ -179,7 +179,8 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
 uint32_t board_button_read(void)
@@ -214,7 +215,7 @@ uint32_t board_millis(void)
 
 void HardFault_Handler (void)
 {
-  asm("bkpt 0x10");
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index 1361e184c..4fab7dc0d 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -6,23 +6,36 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# --------------
+# Compiler Flags
+# --------------
 CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32L4
+
+# GCC Flags
+GCC_CFLAGS += \
   -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m4 \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32L4
+  -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
+GCC_CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
+
+# IAR Flags
+IAR_CFLAGS += --cpu cortex-m4 --fpu VFPv4
+IAR_ASFLAGS += --cpu cortex-m4 --fpu VFPv4
+
+# -----------------
+# Sources & Include
+# -----------------
 
-#src/portable/st/synopsys/dcd_synopsys.c
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
-    src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \

From 0cce42fcc672cb3e0d2fe16c20b46aab9d8f94d5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Jan 2023 11:38:15 +0700
Subject: [PATCH 1440/2085] minor clean up

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 19 ++++++++------
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 26 +++++++++++++-------
 src/portable/raspberrypi/rp2040/rp2040_usb.h |  2 ++
 3 files changed, 31 insertions(+), 16 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 35faba628..d5a105a29 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -246,32 +246,37 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
 {
     uint32_t const status = usb_hw->ints;
     uint32_t handled = 0;
-    bool keep_sof_alive = false;
 
     if (status & USB_INTF_DEV_SOF_BITS)
     {
+      bool keep_sof_alive = false;
+
       handled |= USB_INTF_DEV_SOF_BITS;
 
 #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
       last_sof = time_us_32();
 
-      for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++) {
+      for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++)
+      {
         struct hw_endpoint *ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN);
         hw_endpoint_lock_update(ep, 1);
+
         // Bulk IN endpoint in a transfer?
-        if (rp2040_ep_needs_sof(ep) && ep->active)
-          keep_sof_alive = true;
+        if (rp2040_ep_needs_sof(ep) && ep->active) keep_sof_alive = true;
+
         // Deferred enable?
-        if (ep->pending) {
+        if (ep->pending)
+        {
           hw_endpoint_start_next_buffer(ep);
           ep->pending = 0;
         }
+
         hw_endpoint_lock_update(ep, -1);
       }
 #endif
+
       // disable SOF interrupt if it is used for RESUME in remote wakeup
-      if (!keep_sof_alive && !_sof_enable)
-        usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
+      if (!keep_sof_alive && !_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
 
       dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true);
     }
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 6a9f162a5..b7790e0c1 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -57,13 +57,14 @@ bool rp2040_critical_frame_period(struct hw_endpoint *ep)
 {
   uint32_t delta;
 
-  if (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS)
-    return false;
+  if (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) return false;
 
   if (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_OUT ||
       ep->transfer_type == TUSB_XFER_INTERRUPT ||
       ep->transfer_type == TUSB_XFER_ISOCHRONOUS)
+  {
     return false;
+  }
 
   /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point.
    * The device state machine cannot recover from receiving an incorrect PID
@@ -78,10 +79,8 @@ bool rp2040_critical_frame_period(struct hw_endpoint *ep)
 }
 
 bool rp2040_ep_needs_sof(struct hw_endpoint *ep) {
-  if (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN &&
-      ep->transfer_type == TUSB_XFER_BULK)
-    return true;
-  return false;
+  return (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN &&
+          ep->transfer_type == TUSB_XFER_BULK);
 }
 #endif
 
@@ -115,12 +114,15 @@ void __tusb_irq_path_func(hw_endpoint_reset_transfer)(struct hw_endpoint *ep)
   ep->user_buf = 0;
 }
 
-void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
+void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask)
+{
   uint32_t value = 0;
+
   if ( and_mask )
   {
     value = *ep->buffer_control & and_mask;
   }
+
   if ( or_mask )
   {
     value |= or_mask;
@@ -146,6 +148,7 @@ void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoi
 #endif
     }
   }
+
   *ep->buffer_control = value;
 }
 
@@ -247,13 +250,18 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
   ep->user_buf      = buffer;
 
   if (rp2040_ep_needs_sof(ep))
+  {
     usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
+  }
 
-  if(!rp2040_critical_frame_period(ep)) {
+  if(!rp2040_critical_frame_period(ep))
+  {
     hw_endpoint_start_next_buffer(ep);
-  } else {
+  } else
+  {
     ep->pending = 1;
   }
+
   hw_endpoint_lock_update(ep, -1);
 }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index e7fee3e3a..d41abfee0 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -82,6 +82,7 @@ typedef struct hw_endpoint
 
     // Transfer scheduled but not active
     uint8_t pending;
+
 #if CFG_TUH_ENABLED
     // Only needed for host
     uint8_t dev_addr;
@@ -89,6 +90,7 @@ typedef struct hw_endpoint
     // If interrupt endpoint
     uint8_t interrupt_num;
 #endif
+
 } hw_endpoint_t;
 
 #if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX

From 19b6cbc616e65dcb2ecdcac66f873ce416a4bf25 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Jan 2023 14:48:11 +0700
Subject: [PATCH 1441/2085] add e15 prefix or walkaround related functions,
 also minor refactor

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 177 ++++++++++---------
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  57 +++---
 src/portable/raspberrypi/rp2040/rp2040_usb.h |  10 +-
 3 files changed, 125 insertions(+), 119 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index d5a105a29..ab1185102 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -244,128 +244,133 @@ static void __tusb_irq_path_func(reset_non_control_endpoints)(void)
 
 static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
 {
-    uint32_t const status = usb_hw->ints;
-    uint32_t handled = 0;
+  uint32_t const status = usb_hw->ints;
+  uint32_t handled = 0;
 
-    if (status & USB_INTF_DEV_SOF_BITS)
-    {
-      bool keep_sof_alive = false;
+  if ( status & USB_INTF_DEV_SOF_BITS )
+  {
+    bool keep_sof_alive = false;
 
-      handled |= USB_INTF_DEV_SOF_BITS;
+    handled |= USB_INTF_DEV_SOF_BITS;
 
 #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
-      last_sof = time_us_32();
+    // Errata 15 Walkaround for Device Bulk-In endpoint
+    e15_last_sof = time_us_32();
 
-      for (uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++)
+    for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++ )
+    {
+      struct hw_endpoint * ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN);
+
+      // Active Bulk IN endpoint requires SOF
+      if ( (ep->transfer_type == TUSB_XFER_BULK) && ep->active )
       {
-        struct hw_endpoint *ep = hw_endpoint_get_by_num(i, TUSB_DIR_IN);
+        keep_sof_alive = true;
+
         hw_endpoint_lock_update(ep, 1);
 
-        // Bulk IN endpoint in a transfer?
-        if (rp2040_ep_needs_sof(ep) && ep->active) keep_sof_alive = true;
-
         // Deferred enable?
-        if (ep->pending)
+        if ( ep->pending )
         {
-          hw_endpoint_start_next_buffer(ep);
           ep->pending = 0;
+          hw_endpoint_start_next_buffer(ep);
         }
 
         hw_endpoint_lock_update(ep, -1);
       }
+    }
 #endif
 
-      // disable SOF interrupt if it is used for RESUME in remote wakeup
-      if (!keep_sof_alive && !_sof_enable) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
+    // disable SOF interrupt if it is used for RESUME in remote wakeup
+    if ( !keep_sof_alive && !_sof_enable ) usb_hw_clear->inte = USB_INTS_DEV_SOF_BITS;
 
-      dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true);
-    }
+    dcd_event_sof(0, usb_hw->sof_rd & USB_SOF_RD_BITS, true);
+  }
 
-    // xfer events are handled before setup req. So if a transfer completes immediately
-    // before closing the EP, the events will be delivered in same order.
-    if (status & USB_INTS_BUFF_STATUS_BITS)
-    {
-        handled |= USB_INTS_BUFF_STATUS_BITS;
-        hw_handle_buff_status();
-    }
+  // xfer events are handled before setup req. So if a transfer completes immediately
+  // before closing the EP, the events will be delivered in same order.
+  if ( status & USB_INTS_BUFF_STATUS_BITS )
+  {
+    handled |= USB_INTS_BUFF_STATUS_BITS;
+    hw_handle_buff_status();
+  }
 
-    if (status & USB_INTS_SETUP_REQ_BITS)
-    {
-        handled |= USB_INTS_SETUP_REQ_BITS;
-        uint8_t const *setup = (uint8_t const *)&usb_dpram->setup_packet;
+  if ( status & USB_INTS_SETUP_REQ_BITS )
+  {
+    handled |= USB_INTS_SETUP_REQ_BITS;
+    uint8_t const * setup = (uint8_t const*) &usb_dpram->setup_packet;
 
-        // reset pid to both 1 (data and ack)
-        reset_ep0_pid();
+    // reset pid to both 1 (data and ack)
+    reset_ep0_pid();
 
-        // Pass setup packet to tiny usb
-        dcd_event_setup_received(0, setup, true);
-        usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS;
-    }
+    // Pass setup packet to tiny usb
+    dcd_event_setup_received(0, setup, true);
+    usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS;
+  }
 
 #if FORCE_VBUS_DETECT == 0
-    // Since we force VBUS detect On, device will always think it is connected and
-    // couldn't distinguish between disconnect and suspend
-    if (status & USB_INTS_DEV_CONN_DIS_BITS)
+  // Since we force VBUS detect On, device will always think it is connected and
+  // couldn't distinguish between disconnect and suspend
+  if (status & USB_INTS_DEV_CONN_DIS_BITS)
+  {
+    handled |= USB_INTS_DEV_CONN_DIS_BITS;
+
+    if ( usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS )
     {
-        handled |= USB_INTS_DEV_CONN_DIS_BITS;
-
-        if ( usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS )
-        {
-          // Connected: nothing to do
-        }else
-        {
-          // Disconnected
-          dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
-        }
-
-        usb_hw_clear->sie_status = USB_SIE_STATUS_CONNECTED_BITS;
+      // Connected: nothing to do
+    }else
+    {
+      // Disconnected
+      dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
     }
+
+    usb_hw_clear->sie_status = USB_SIE_STATUS_CONNECTED_BITS;
+  }
 #endif
 
-    // SE0 for 2.5 us or more (will last at least 10ms)
-    if (status & USB_INTS_BUS_RESET_BITS)
-    {
-        pico_trace("BUS RESET\n");
+  // SE0 for 2.5 us or more (will last at least 10ms)
+  if ( status & USB_INTS_BUS_RESET_BITS )
+  {
+    pico_trace("BUS RESET\n");
 
-        handled |= USB_INTS_BUS_RESET_BITS;
+    handled |= USB_INTS_BUS_RESET_BITS;
 
-        usb_hw->dev_addr_ctrl = 0;
-        reset_non_control_endpoints();
-        dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
-        usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
+    usb_hw->dev_addr_ctrl = 0;
+    reset_non_control_endpoints();
+    dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
+    usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
 
 #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
-        // Only run enumeration walk-around if pull up is enabled
-        if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix();
+    // Only run enumeration walk-around if pull up is enabled
+    if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix();
 #endif
-    }
+  }
 
-    /* Note from pico datasheet 4.1.2.6.4 (v1.2)
-     * If you enable the suspend interrupt, it is likely you will see a suspend interrupt when
-     * the device is first connected but the bus is idle. The bus can be idle for a few ms before
-     * the host begins sending start of frame packets. You will also see a suspend interrupt
-     * when the device is disconnected if you do not have a VBUS detect circuit connected. This is
-     * because without VBUS detection, it is impossible to tell the difference between
-     * being disconnected and suspended.
-     */
-    if (status & USB_INTS_DEV_SUSPEND_BITS)
-    {
-        handled |= USB_INTS_DEV_SUSPEND_BITS;
-        dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
-        usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS;
-    }
+  /* Note from pico datasheet 4.1.2.6.4 (v1.2)
+   * If you enable the suspend interrupt, it is likely you will see a suspend interrupt when
+   * the device is first connected but the bus is idle. The bus can be idle for a few ms before
+   * the host begins sending start of frame packets. You will also see a suspend interrupt
+   * when the device is disconnected if you do not have a VBUS detect circuit connected. This is
+   * because without VBUS detection, it is impossible to tell the difference between
+   * being disconnected and suspended.
+   */
+  if ( status & USB_INTS_DEV_SUSPEND_BITS )
+  {
+    handled |= USB_INTS_DEV_SUSPEND_BITS;
+    dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+    usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS;
+  }
 
-    if (status & USB_INTS_DEV_RESUME_FROM_HOST_BITS)
-    {
-        handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS;
-        dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
-        usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS;
-    }
+  if ( status & USB_INTS_DEV_RESUME_FROM_HOST_BITS )
+  {
+    handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS;
+    dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+    usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS;
+  }
 
-    if (status ^ handled)
-    {
-        panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
-    }
+  if ( status ^ handled )
+  {
+    panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
+  }
 }
 
 #define USB_INTS_ERROR_BITS ( \
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index b7790e0c1..d25e6c8fb 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -51,37 +51,41 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void)
 //--------------------------------------------------------------------+
 
 #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
-volatile uint32_t last_sof = 0;
+// Errata 15 Walkaround for Device Bulk-In endpoint to avoid schedule an transfer
+// within last 20% of an USB frame.
 
-bool rp2040_critical_frame_period(struct hw_endpoint *ep)
+volatile uint32_t e15_last_sof = 0;
+
+// check if Errata 15 walkround is needed for this endpoint
+static bool __tusb_irq_path_func(e15_is_bulkin_ep) (struct hw_endpoint *ep)
 {
-  uint32_t delta;
+  return (!is_host_mode() && tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN &&
+          ep->transfer_type == TUSB_XFER_BULK);
+}
 
-  if (usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) return false;
-
-  if (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_OUT ||
-      ep->transfer_type == TUSB_XFER_INTERRUPT ||
-      ep->transfer_type == TUSB_XFER_ISOCHRONOUS)
-  {
-    return false;
-  }
+// check if we need to apply Errata 15 workaround: ie.g
+// Enpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame
+static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoint *ep)
+{
+  TU_VERIFY(e15_is_bulkin_ep(ep));
 
   /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point.
    * The device state machine cannot recover from receiving an incorrect PID
    * when it is expecting an ACK.
    */
-  delta = time_us_32() - last_sof;
+  uint32_t delta = time_us_32() - e15_last_sof;
   if (delta < 800 || delta > 998) {
     return false;
   }
-  TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, now, last_sof);
+  TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof);
   return true;
 }
 
-bool rp2040_ep_needs_sof(struct hw_endpoint *ep) {
-  return (tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN &&
-          ep->transfer_type == TUSB_XFER_BULK);
-}
+#else
+
+#define e15_is_bulkin_ep(x)             false
+#define e15_is_critical_frame_period(x) false
+
 #endif
 
 void rp2040_usb_init(void)
@@ -249,17 +253,17 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
   ep->active        = true;
   ep->user_buf      = buffer;
 
-  if (rp2040_ep_needs_sof(ep))
+  if ( e15_is_bulkin_ep(ep) )
   {
     usb_hw_set->inte = USB_INTS_DEV_SOF_BITS;
   }
 
-  if(!rp2040_critical_frame_period(ep))
-  {
-    hw_endpoint_start_next_buffer(ep);
-  } else
+  if ( e15_is_critical_frame_period(ep) )
   {
     ep->pending = 1;
+  } else
+  {
+    hw_endpoint_start_next_buffer(ep);
   }
 
   hw_endpoint_lock_update(ep, -1);
@@ -356,6 +360,7 @@ static void __tusb_irq_path_func(_hw_endpoint_xfer_sync) (struct hw_endpoint *ep
 bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
 {
   hw_endpoint_lock_update(ep, 1);
+
   // Part way through a transfer
   if (!ep->active)
   {
@@ -377,10 +382,12 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
   }
   else
   {
-    if(!rp2040_critical_frame_period(ep)) {
-      hw_endpoint_start_next_buffer(ep);
-    } else {
+    if ( e15_is_critical_frame_period(ep) )
+    {
       ep->pending = 1;
+    } else
+    {
+      hw_endpoint_start_next_buffer(ep);
     }
   }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index d41abfee0..a06407f23 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -93,14 +93,8 @@ typedef struct hw_endpoint
 
 } hw_endpoint_t;
 
-#if !TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
-#define rp2040_critical_frame_period(x) false
-#define rp2040_ep_needs_sof(x) false
-#else
-extern volatile uint32_t last_sof;
-
-bool rp2040_critical_frame_period(struct hw_endpoint *ep);
-bool rp2040_ep_needs_sof(struct hw_endpoint *ep);
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+extern volatile uint32_t e15_last_sof;
 #endif
 
 void rp2040_usb_init(void);

From 6759721e9aceb52f176f3068438c103739c29768 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Jan 2023 17:37:14 +0700
Subject: [PATCH 1442/2085] move errata to end of c file

---
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 104 ++++++++++++-------
 1 file changed, 65 insertions(+), 39 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index d25e6c8fb..6f9cf34be 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -32,6 +32,10 @@
 #include <stdlib.h>
 #include "rp2040_usb.h"
 
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPE
+//--------------------------------------------------------------------+
+
 // Direction strings for debug
 const char *ep_dir_string[] = {
         "out",
@@ -40,6 +44,14 @@ const char *ep_dir_string[] = {
 
 static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
 
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+  static bool e15_is_bulkin_ep(struct hw_endpoint *ep);
+  static bool e15_is_critical_frame_period(struct hw_endpoint *ep);
+#else
+  #define e15_is_bulkin_ep(x)             (false)
+  #define e15_is_critical_frame_period(x) (false)
+#endif
+
 // if usb hardware is in host mode
 TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void)
 {
@@ -47,47 +59,9 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_host_mode(void)
 }
 
 //--------------------------------------------------------------------+
-//
+// Implementation
 //--------------------------------------------------------------------+
 
-#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
-// Errata 15 Walkaround for Device Bulk-In endpoint to avoid schedule an transfer
-// within last 20% of an USB frame.
-
-volatile uint32_t e15_last_sof = 0;
-
-// check if Errata 15 walkround is needed for this endpoint
-static bool __tusb_irq_path_func(e15_is_bulkin_ep) (struct hw_endpoint *ep)
-{
-  return (!is_host_mode() && tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN &&
-          ep->transfer_type == TUSB_XFER_BULK);
-}
-
-// check if we need to apply Errata 15 workaround: ie.g
-// Enpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame
-static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoint *ep)
-{
-  TU_VERIFY(e15_is_bulkin_ep(ep));
-
-  /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point.
-   * The device state machine cannot recover from receiving an incorrect PID
-   * when it is expecting an ACK.
-   */
-  uint32_t delta = time_us_32() - e15_last_sof;
-  if (delta < 800 || delta > 998) {
-    return false;
-  }
-  TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof);
-  return true;
-}
-
-#else
-
-#define e15_is_bulkin_ep(x)             false
-#define e15_is_critical_frame_period(x) false
-
-#endif
-
 void rp2040_usb_init(void)
 {
   // Reset usb controller
@@ -396,4 +370,56 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
   return false;
 }
 
+//--------------------------------------------------------------------+
+// Errata 15
+//--------------------------------------------------------------------+
+
+#if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
+
+/* Don't mark IN buffers as available during the last 200us of a full-speed
+   frame. This avoids a situation seen with the USB2.0 hub on a Raspberry
+   Pi 4 where a late IN token before the next full-speed SOF can cause port
+   babble and a corrupt ACK packet. The nature of the data corruption has a
+   chance to cause device lockup.
+
+   Use the next SOF to mark delayed buffers as available. This reduces
+   available Bulk IN bandwidth by approximately 20%, and requires that the
+   SOF interrupt is enabled while these transfers are ongoing.
+
+   Inherit the top-level enable from the corresponding Pico-SDK flag.
+   Applications that will not use the device in a situation where it could
+   be plugged into a Pi 4 or Pi 400 (for example, when directly connected
+   to a commodity hub or other host) can turn off the flag in the SDK.
+*/
+
+volatile uint32_t e15_last_sof = 0;
+
+// check if Errata 15 is needed for this endpoint i.e device bulk-in
+static bool __tusb_irq_path_func(e15_is_bulkin_ep) (struct hw_endpoint *ep)
+{
+  return (!is_host_mode() && tu_edpt_dir(ep->ep_addr) == TUSB_DIR_IN &&
+          ep->transfer_type == TUSB_XFER_BULK);
+}
+
+// check if we need to apply Errata 15 walk-around : i.e
+// Endpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame
+static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoint *ep)
+{
+  TU_VERIFY(e15_is_bulkin_ep(ep));
+
+  /* Avoid the last 200us (uframe 6.5-7) of a frame, up to the EOF2 point.
+   * The device state machine cannot recover from receiving an incorrect PID
+   * when it is expecting an ACK.
+   */
+  uint32_t delta = time_us_32() - e15_last_sof;
+  if (delta < 800 || delta > 998) {
+    return false;
+  }
+  TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof);
+  return true;
+}
+
+#endif
+
+
 #endif

From 95403ed9ac88077062c03525d44818b10be1cf6f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Jan 2023 18:40:07 +0700
Subject: [PATCH 1443/2085] fix host issue when mounting an CDC device without
 IAD

---
 src/host/usbh.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 5ac9e9cca..12b0ed203 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1522,7 +1522,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
 
 #if CFG_TUH_MIDI
     // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD
-    // manually increase the associated count
+    // manually force associated count = 2
     if (1                              == assoc_itf_count              &&
         TUSB_CLASS_AUDIO               == desc_itf->bInterfaceClass    &&
         AUDIO_SUBCLASS_CONTROL         == desc_itf->bInterfaceSubClass &&
@@ -1532,6 +1532,17 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     }
 #endif
 
+#if CFG_TUH_CDC
+    // Some legacy CDC device does not use IAD but rather use device class as hint to combine 2 interfaces
+    // manually force associated count = 2
+    if (1                                        == assoc_itf_count              &&
+        TUSB_CLASS_CDC                           == desc_itf->bInterfaceClass    &&
+        CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == desc_itf->bInterfaceSubClass)
+    {
+      assoc_itf_count = 2;
+    }
+#endif
+
     uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end-p_desc));
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 

From 5f4701bb3e83c8f205c670cfa9cca833b34434d3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Jan 2023 18:40:49 +0700
Subject: [PATCH 1444/2085] added fuzzing status

---
 README.rst | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index 8504b92c8..7825a1b0a 100644
--- a/README.rst
+++ b/README.rst
@@ -1,7 +1,7 @@
 .. figure:: docs/assets/logo.svg
    :alt: TinyUSB
 
-|Build Status| |Documentation Status| |License|
+|Build Status| |Documentation Status| |Fuzzing Status| |License|
 
 TinyUSB is an open-source cross-platform USB Host/Device stack for
 embedded system, designed to be memory-safe with no dynamic allocation
@@ -130,6 +130,8 @@ in your project.
    :target: https://github.com/hathach/tinyusb/actions
 .. |Documentation Status| image:: https://readthedocs.org/projects/tinyusb/badge/?version=latest
    :target: https://docs.tinyusb.org/en/latest/?badge=latest
+.. |Fuzzing Status| image:: https://oss-fuzz-build-logs.storage.googleapis.com/badges/tinyusb.svg
+   :target: https://oss-fuzz-build-logs.storage.googleapis.com/index.html#tinyusb
 .. |License| image:: https://img.shields.io/badge/license-MIT-brightgreen.svg
    :target: https://opensource.org/licenses/MIT
 

From 9b6d6a983a32ecbfe6c5f09e1380549e45abe16f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Jan 2023 18:42:02 +0700
Subject: [PATCH 1445/2085] fix typo issue #1859

---
 examples/device/hid_generic_inout/src/usb_descriptors.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/device/hid_generic_inout/src/usb_descriptors.c b/examples/device/hid_generic_inout/src/usb_descriptors.c
index c2b4792c8..cd4838407 100644
--- a/examples/device/hid_generic_inout/src/usb_descriptors.c
+++ b/examples/device/hid_generic_inout/src/usb_descriptors.c
@@ -103,7 +103,7 @@ uint8_t const desc_configuration[] =
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
-  // Interface number, string index, protocol, report descriptor len, EP In & Out address, size & polling interval
+  // Interface number, string index, protocol, report descriptor len, EP Out & In address, size & polling interval
   TUD_HID_INOUT_DESCRIPTOR(ITF_NUM_HID, 0, HID_ITF_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_HID, 0x80 | EPNUM_HID, CFG_TUD_HID_EP_BUFSIZE, 10)
 };
 

From ddb061f639956781ac5644e5c9ec2371c534ea57 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 31 Jan 2023 19:03:31 +0700
Subject: [PATCH 1446/2085] fix typos

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 4 ++--
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index ab1185102..b5fa90c92 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -254,7 +254,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
     handled |= USB_INTF_DEV_SOF_BITS;
 
 #if TUD_OPT_RP2040_USB_DEVICE_UFRAME_FIX
-    // Errata 15 Walkaround for Device Bulk-In endpoint
+    // Errata 15 workaround for Device Bulk-In endpoint
     e15_last_sof = time_us_32();
 
     for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS; i++ )
@@ -340,7 +340,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
     usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
 
 #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
-    // Only run enumeration walk-around if pull up is enabled
+    // Only run enumeration workaround if pull up is enabled
     if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix();
 #endif
   }
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 6f9cf34be..df05697fe 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -401,7 +401,7 @@ static bool __tusb_irq_path_func(e15_is_bulkin_ep) (struct hw_endpoint *ep)
           ep->transfer_type == TUSB_XFER_BULK);
 }
 
-// check if we need to apply Errata 15 walk-around : i.e
+// check if we need to apply Errata 15 workaround : i.e
 // Endpoint is BULK IN and is currently in critical frame period i.e 20% of last usb frame
 static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoint *ep)
 {

From 6ec0537408e95ada3ee85eac5d502bd3d7d20d23 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Feb 2023 15:14:35 +0700
Subject: [PATCH 1447/2085] move hw-stm32l412nucleo-test into build-arm to
 reduce self-host compile time

reduce IAR build to only f0, h7, l4
---
 .github/workflows/build_arm.yml     | 89 ++++++++++++++++++++++++++---
 .github/workflows/build_iar.yml     |  9 +--
 .github/workflows/test_hardware.yml |  1 +
 3 files changed, 87 insertions(+), 12 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index c16fc0d45..cba9b6d99 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -7,6 +7,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_arm.yml'
   pull_request:
     branches: [ master ]
     paths:
@@ -14,6 +15,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_arm.yml'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
@@ -98,13 +100,12 @@ jobs:
           find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
         done
 
-    # Following steps are for Hardware Test with self-hosted
-
-    - name: Prepare Artifacts
+    # Upload binaries for rp2040 hardware test with self-hosted
+    - name: Prepare rp2040 Artifacts
       if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
       run: find examples/ -name "*.elf" -exec mv {} . \;
 
-    - name: Upload Artifacts for Hardware Test
+    - name: Upload rp2040 Artifacts
       if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
       uses: actions/upload-artifact@v3
       with:
@@ -112,6 +113,19 @@ jobs:
         path: |
           *.elf
 
+    # Upload binaries for stm32l412nucleo hardware test with self-hosted
+    - name: Prepare stm32l4 Artifacts
+      if: matrix.family == 'stm32l4'
+      run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
+
+    - name: Upload stm32l4 Artifacts
+      if: matrix.family == 'stm32l4'
+      uses: actions/upload-artifact@v3
+      with:
+        name: ${{ matrix.family }}
+        path: |
+          *.elf
+
   # ---------------------------------------
   # Build all no-family (orphaned) boards
   # disable this workflow since it is often failed randomly
@@ -210,8 +224,67 @@ jobs:
         ./flash.sh dfu_runtime.elf
         while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
 
-#    - name: Test hid_boot_interface
-#      run: |
-#        ./flash.sh hid_boot_interface.elf
-#        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
+  # ---------------------------------------
+  # Hardware in the loop (HIL)
+  # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
+  # - STM32L412 Nucleo with on-board jlink as ttyACM0
+  # ---------------------------------------
+  hw-stm32l412nucleo-test:
+    needs: build-arm
+    runs-on: [self-hosted, Linux, X64, hifiphile]
 
+    steps:
+    - name: Clean workspace
+      run: |
+        echo "Cleaning up previous run"
+        rm -rf "${{ github.workspace }}"
+        mkdir -p "${{ github.workspace }}"
+
+    - name: Download stm32l4 Artifacts
+      uses: actions/download-artifact@v3
+      with:
+        name: stm32l4
+
+    - name: Create flash.sh
+      run: |
+        echo > flash.sh 'echo halt > flash.jlink'
+        echo >> flash.sh 'echo r >> flash.jlink'
+        echo >> flash.sh 'echo loadfile $1 >> flash.jlink'
+        echo >> flash.sh 'echo r >> flash.jlink'
+        echo >> flash.sh 'echo go >> flash.jlink'
+        echo >> flash.sh 'echo exit >> flash.jlink'
+        echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
+        echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
+        chmod +x flash.sh
+
+    - name: Test cdc_dual_ports
+      run: |
+        ./flash.sh cdc_dual_ports.elf
+        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
+        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
+
+      # Debian does not auto mount usb drive. skip this test for now
+    - name: Test cdc_msc
+      if: false
+      run: |
+        ./flash.sh cdc_msc.elf
+        readme='/media/pi/TinyUSB MSC/README.TXT'
+        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
+        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+        test -f "$readme" && echo "$readme exists"
+        cat "$readme"
+
+    - name: Test dfu
+      run: |
+        ./flash.sh dfu.elf
+        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
+        dfu-util -d cafe -a 0 -U dfu0
+        dfu-util -d cafe -a 1 -U dfu1
+        grep "TinyUSB DFU! - Partition 0" dfu0
+        grep "TinyUSB DFU! - Partition 1" dfu1
+
+    - name: Test dfu_runtime
+      run: |
+        ./flash.sh dfu_runtime.elf
+        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done  
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 9c1bfa18a..85183751b 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -27,11 +27,12 @@ jobs:
       matrix:
         family:
         # Alphabetical order
+        # Due to long build time, we only enable build with different usb controller
         - 'stm32f0'
-        - 'stm32f1'
-        - 'stm32f4'
-        - 'stm32f7'
-        - 'stm32g4'
+        #- 'stm32f1'
+        #- 'stm32f4'
+        #- 'stm32f7'
+        #- 'stm32g4'
         - 'stm32h7'
         - 'stm32l4'
     steps:
diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
index 601a97e99..ca626926d 100644
--- a/.github/workflows/test_hardware.yml
+++ b/.github/workflows/test_hardware.yml
@@ -21,6 +21,7 @@ on:
 
 jobs:
   stm32l412nucleo-test:
+    if: false
     runs-on: [self-hosted, Linux, X64, hifiphile]
 
     steps:

From 3846da69d38c824fc9609f60380b864d4376b70e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Feb 2023 16:36:39 +0700
Subject: [PATCH 1448/2085] run workflow if its yml is updated

---
 .github/workflows/build_aarch64.yml |  2 +
 .github/workflows/build_arm.yml     |  8 +--
 .github/workflows/build_esp.yml     |  2 +
 .github/workflows/build_iar.yml     |  2 +
 .github/workflows/build_msp430.yml  |  2 +
 .github/workflows/build_renesas.yml |  2 +
 .github/workflows/build_riscv.yml   |  2 +
 .github/workflows/test_hardware.yml | 95 -----------------------------
 8 files changed, 16 insertions(+), 99 deletions(-)
 delete mode 100644 .github/workflows/test_hardware.yml

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index c552a9574..800a54380 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -7,6 +7,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_aarch64.yml'
   pull_request:
     branches: [ master ]
     paths:
@@ -14,6 +15,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_aarch64.yml'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index cba9b6d99..29c41a8eb 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -114,15 +114,15 @@ jobs:
           *.elf
 
     # Upload binaries for stm32l412nucleo hardware test with self-hosted
-    - name: Prepare stm32l4 Artifacts
+    - name: Prepare stm32l412nucleo Artifacts
       if: matrix.family == 'stm32l4'
       run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
 
-    - name: Upload stm32l4 Artifacts
+    - name: Upload stm32l412nucleo Artifacts
       if: matrix.family == 'stm32l4'
       uses: actions/upload-artifact@v3
       with:
-        name: ${{ matrix.family }}
+        name: stm32l412nucleo
         path: |
           *.elf
 
@@ -243,7 +243,7 @@ jobs:
     - name: Download stm32l4 Artifacts
       uses: actions/download-artifact@v3
       with:
-        name: stm32l4
+        name: stm32l412nucleo
 
     - name: Create flash.sh
       run: |
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 2e2859c95..dbc51a60f 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -7,6 +7,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_esp.yml'
   pull_request:
     branches: [ master ]
     paths:
@@ -14,6 +15,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_esp.yml'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 85183751b..c644bdc51 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -7,6 +7,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_iar.yml'
   pull_request:
     branches: [ master ]
     paths:
@@ -14,6 +15,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_iar.yml'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 7e1c5b128..2c7785806 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -7,6 +7,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_msp430.yml'
   pull_request:
     branches: [ master ]
     paths:
@@ -14,6 +15,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_msp430.yml'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index d9254dea8..3a961d327 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -7,6 +7,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_renesas.yml'
   pull_request:
     branches: [ master ]
     paths:
@@ -14,6 +15,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_renesas.yml'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 66f4fd153..fb4d4d28c 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -7,6 +7,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_riscv.yml'
   pull_request:
     branches: [ master ]
     paths:
@@ -14,6 +15,7 @@ on:
       - 'examples/**'
       - 'lib/**'
       - 'hw/**'
+      - '.github/workflows/build_riscv.yml'
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
diff --git a/.github/workflows/test_hardware.yml b/.github/workflows/test_hardware.yml
deleted file mode 100644
index ca626926d..000000000
--- a/.github/workflows/test_hardware.yml
+++ /dev/null
@@ -1,95 +0,0 @@
-name: Hardware Test
-
-on:
-  push:
-    paths:
-      - 'src/**'
-      - 'examples/**'
-      - 'lib/**'
-      - 'hw/**'
-  pull_request:
-    branches: [ master ]
-    paths:
-      - 'src/**'
-      - 'examples/**'
-      - 'lib/**'
-      - 'hw/**'
-
-# Hardware in the loop (HIL)
-# Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
-# - STM32L412 Nucleo with on-board jlink as ttyACM0
-
-jobs:
-  stm32l412nucleo-test:
-    if: false
-    runs-on: [self-hosted, Linux, X64, hifiphile]
-
-    steps:
-    - name: Clean workspace
-      run: |
-        echo "Cleaning up previous run"
-        rm -rf "${{ github.workspace }}"
-        mkdir -p "${{ github.workspace }}"
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Get Dependencies and Build
-      run: |
-        git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-        python3 tools/get_dependencies.py stm32l4
-        python3 tools/build_family.py stm32l4
-
-    - name: Pick-up elf files
-      run: |
-        mkdir stm32l412nucleo/
-        find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} stm32l412nucleo/ \;
-
-    - name: Create flash.sh
-      run: |
-        echo > flash.sh 'echo halt > flash.jlink'
-        echo >> flash.sh 'echo r >> flash.jlink'
-        echo >> flash.sh 'echo loadfile stm32l412nucleo/$1 >> flash.jlink'
-        echo >> flash.sh 'echo r >> flash.jlink'
-        echo >> flash.sh 'echo go >> flash.jlink'
-        echo >> flash.sh 'echo exit >> flash.jlink'
-        echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
-        echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
-        chmod +x flash.sh
-
-    - name: Test cdc_dual_ports
-      run: |
-        ./flash.sh cdc_dual_ports.elf
-        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-
-      # Debian does not auto mount usb drive. skip this test for now
-    - name: Test cdc_msc
-      if: false
-      run: |
-        ./flash.sh cdc_msc.elf
-        readme='/media/pi/TinyUSB MSC/README.TXT'
-        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -f "$readme" && echo "$readme exists"
-        cat "$readme"
-
-    - name: Test dfu
-      run: |
-        ./flash.sh dfu.elf
-        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
-        dfu-util -d cafe -a 0 -U dfu0
-        dfu-util -d cafe -a 1 -U dfu1
-        grep "TinyUSB DFU! - Partition 0" dfu0
-        grep "TinyUSB DFU! - Partition 1" dfu1
-
-    - name: Test dfu_runtime
-      run: |
-        ./flash.sh dfu_runtime.elf
-        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
-
-#    - name: Test hid_boot_interface
-#      run: |
-#        ./flash.sh hid_boot_interface.elf
-#        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done

From 647fd030ffe698409f20ebf28f6eea1ba7604348 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Feb 2023 18:45:50 +0700
Subject: [PATCH 1449/2085] merge multiple matrix with IAR build

---
 .github/workflows/build_iar.yml | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index c644bdc51..c7824d5a2 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -29,14 +29,7 @@ jobs:
       matrix:
         family:
         # Alphabetical order
-        # Due to long build time, we only enable build with different usb controller
-        - 'stm32f0'
-        #- 'stm32f1'
-        #- 'stm32f4'
-        #- 'stm32f7'
-        #- 'stm32g4'
-        - 'stm32h7'
-        - 'stm32l4'
+        - 'stm32f0 stm32f1 stm32f4 stm32f7 stm32g4 stm32h7 stm32l4'
     steps:
     - name: Clean workspace
       run: |

From 172770221732030f14d5d3311d25509cbd7117f9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Feb 2023 19:29:37 +0700
Subject: [PATCH 1450/2085] add note for iar workflow

---
 .github/workflows/build_iar.yml | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index c7824d5a2..33e77c3dc 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -29,6 +29,8 @@ jobs:
       matrix:
         family:
         # Alphabetical order
+        # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
+        # run IAR build. Too many matrix can hurt due to setup/teardown overhead. 
         - 'stm32f0 stm32f1 stm32f4 stm32f7 stm32g4 stm32h7 stm32l4'
     steps:
     - name: Clean workspace
@@ -45,11 +47,11 @@ jobs:
         git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
         python3 tools/get_dependencies.py ${{ matrix.family }}
 
-    - name: Checkout pico-sdk for rp2040
-      if: matrix.family == 'rp2040'
-      run: |
-        git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
-        echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
+    #- name: Checkout pico-sdk for rp2040
+    #  if: matrix.family == 'rp2040'
+    #  run: |
+    #    git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
+    #    echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }} CC=iccarm

From 3422e0568431079715acabc63f1899578ef6240d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 4 Feb 2023 11:43:23 +0700
Subject: [PATCH 1451/2085] change length in tud_hid_report_complete_cb() from
 uint8 to uint16

---
 examples/device/hid_boot_interface/src/main.c     | 2 +-
 examples/device/hid_composite/src/main.c          | 2 +-
 examples/device/hid_composite_freertos/src/main.c | 2 +-
 src/class/hid/hid_device.c                        | 2 +-
 src/class/hid/hid_device.h                        | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index ef072019c..b13428041 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -181,7 +181,7 @@ void tud_hid_set_protocol_cb(uint8_t instance, uint8_t protocol)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
 {
   (void) instance;
   (void) report;
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index f7d76cfc7..05315f266 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -225,7 +225,7 @@ void hid_task(void)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
 {
   (void) instance;
   (void) len;
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index fb0d69258..7c9619c4b 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -302,7 +302,7 @@ void hid_task(void* param)
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len)
+void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len)
 {
   (void) instance;
   (void) len;
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 8077e4deb..2d46d760f 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -403,7 +403,7 @@ bool hidd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   {
     if (tud_hid_report_complete_cb)
     {
-      tud_hid_report_complete_cb(instance, p_hid->epin_buf, (/*uint16_t*/ uint8_t) xferred_bytes);
+      tud_hid_report_complete_cb(instance, p_hid->epin_buf, (uint16_t) xferred_bytes);
     }
   }
   // Received report
diff --git a/src/class/hid/hid_device.h b/src/class/hid/hid_device.h
index eeef6d3ba..17b24def1 100644
--- a/src/class/hid/hid_device.h
+++ b/src/class/hid/hid_device.h
@@ -116,7 +116,7 @@ TU_ATTR_WEAK bool tud_hid_set_idle_cb(uint8_t instance, uint8_t idle_rate);
 // Invoked when sent REPORT successfully to host
 // Application can use this to send the next report
 // Note: For composite reports, report[0] is report ID
-TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, /*uint16_t*/ uint8_t len );
+TU_ATTR_WEAK void tud_hid_report_complete_cb(uint8_t instance, uint8_t const* report, uint16_t len);
 
 
 //--------------------------------------------------------------------+

From 830849211d866fcafef555269b1376f15802cc68 Mon Sep 17 00:00:00 2001
From: Jannis Achstetter <kripton@kripserver.net>
Date: Sat, 4 Feb 2023 22:37:39 +0100
Subject: [PATCH 1452/2085] dhserver: Fix a potential DoS vulnerability
 accidentially introduced by #1712

---
 lib/networking/dhserver.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/lib/networking/dhserver.c b/lib/networking/dhserver.c
index def431f75..8cd22ddb9 100644
--- a/lib/networking/dhserver.c
+++ b/lib/networking/dhserver.c
@@ -86,7 +86,7 @@ typedef struct
     uint8_t  dp_giaddr[4];    /* gateway IP address */
     uint8_t  dp_chaddr[16];   /* client hardware address */
     uint8_t  dp_legacy[192];
-    uint8_t  dp_magic[4];     
+    uint8_t  dp_magic[4];
     uint8_t  dp_options[275]; /* options area */
 } DHCP_TYPE;
 
@@ -242,7 +242,11 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const
 	memcpy(&dhcp_data, p->payload, n);
 
 	ptr = find_dhcp_option(dhcp_data.dp_options, sizeof(dhcp_data.dp_options), DHCP_MESSAGETYPE);
-	if (ptr == NULL) return;
+	if (ptr == NULL)
+	{
+		pbuf_free(p);
+		return;
+	}
 
 	switch (ptr[2])
 	{

From 8d3f0ffb9599d1834d797d6f965a7f5f619c290a Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Fri, 3 Feb 2023 11:05:32 -0600
Subject: [PATCH 1453/2085] * don't force dependency on pico-pio-usb submodule
 * suppress compiler warning/errors especially in pico-pio-usb * disable use
 of pico-pio-usb on gcc 11.3+ for now as it doesn't compile

---
 examples/host/bare_api/CMakeLists.txt         | 12 -----
 examples/host/cdc_msc_hid/CMakeLists.txt      | 12 -----
 examples/host/hid_controller/CMakeLists.txt   | 12 -----
 .../host/msc_file_explorer/CMakeLists.txt     | 11 -----
 hw/bsp/rp2040/family.cmake                    | 44 ++++++++++++++++---
 5 files changed, 39 insertions(+), 52 deletions(-)

diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 31a8aa222..4879613b4 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -25,15 +25,3 @@ target_include_directories(${PROJECT} PUBLIC
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
-
-# For rp2040 enable pico-pio-usb
-if(FAMILY STREQUAL "rp2040")
-  family_add_pico_pio_usb(${PROJECT})
-
-  # due to warnings from Pico-PIO-USB
-  target_compile_options(${PROJECT} PUBLIC
-          -Wno-error=cast-qual
-          -Wno-error=sign-conversion
-          -Wno-error=conversion
-          )
-endif()
\ No newline at end of file
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 7af6b738e..dbba6bf44 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -28,15 +28,3 @@ target_include_directories(${PROJECT} PUBLIC
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
-
-# For rp2040 enable pico-pio-usb
-if(FAMILY STREQUAL "rp2040")
-  family_add_pico_pio_usb(${PROJECT})
-
-  # due to warnings from Pico-PIO-USB
-  target_compile_options(${PROJECT} PUBLIC
-          -Wno-error=cast-qual
-          -Wno-error=sign-conversion
-          -Wno-error=conversion
-          )
-endif()
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index 39adf9093..aa50b5a52 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -26,15 +26,3 @@ target_include_directories(${PROJECT} PUBLIC
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
-
-# For rp2040 enable pico-pio-usb
-if(FAMILY STREQUAL "rp2040")
-  family_add_pico_pio_usb(${PROJECT})
-
-  # due to warnings from Pico-PIO-USB
-  target_compile_options(${PROJECT} PUBLIC
-          -Wno-error=cast-qual
-          -Wno-error=sign-conversion
-          -Wno-error=conversion
-          )
-endif()
\ No newline at end of file
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 326286b3f..2c06eafee 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -32,14 +32,3 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
 
-# For rp2040 enable pico-pio-usb
-if(FAMILY STREQUAL "rp2040")
-  family_add_pico_pio_usb(${PROJECT})
-
-  # due to warnings from Pico-PIO-USB
-  target_compile_options(${PROJECT} PUBLIC
-          -Wno-error=cast-qual
-          -Wno-error=sign-conversion
-          -Wno-error=conversion
-          )
-endif()
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index f83120567..1eab95304 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -161,14 +161,22 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		rp2040_family_configure_example_warnings(${TARGET})
 	endfunction()
 
+	function(family_add_pico_pio_usb TARGET)
+		target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb)
+	endfunction()
+
 	function(family_configure_host_example TARGET)
 		family_configure_target(${TARGET})
 		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
 		rp2040_family_configure_example_warnings(${TARGET})
-	endfunction()
 
-	function(family_add_pico_pio_usb TARGET)
-		target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb)
+		# For rp2040 enable pico-pio-usb
+		if (TARGET tinyusb_pico_pio_usb)
+			# code does not compile with GCC 12+
+			if (NOT (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3))
+				family_add_pico_pio_usb(${PROJECT})
+			endif()
+		endif()
 	endfunction()
 
 	function(family_configure_dual_usb_example TARGET)
@@ -272,10 +280,36 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 			endif()
 			if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0)
 				set_source_files_properties(
-						${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/rp2040_usb.c
-						PROPERTIES
+						${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
 						COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds")
 			endif()
+			set_source_files_properties(
+					${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual")
+
+			set_source_files_properties(
+					${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_in.c
+					${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_out.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-conversion")
+
+			set_source_files_properties(
+					${PICO_TINYUSB_PATH}/lib/networking/dnserver.c
+					${PICO_TINYUSB_PATH}/lib/networking/dhserver.c
+					${PICO_TINYUSB_PATH}/lib/networking/rndis_reports.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-conversion -Wno-sign-conversion")
+
+			if (TARGET tinyusb_pico_pio_usb)
+				set_source_files_properties(
+						${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_device.c
+						${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb.c
+						${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_host.c
+						${PICO_TINYUSB_PATH}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+						PROPERTIES
+						COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-attributes")
+			endif()
 		endif()
 	endfunction()
 endif()

From 7e48da5b44e2f30095a9de42c43381b9194cfd54 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Feb 2023 12:47:33 +0700
Subject: [PATCH 1454/2085] update version to 0.15.0

add changelog
---
 docs/info/changelog.rst | 82 ++++++++++++++++++++++++++++++++++++++++-
 repository.yml          |  7 ++--
 src/tusb_option.h       |  2 +-
 tools/make_release.py   | 40 ++++++++++++++++++++
 4 files changed, 125 insertions(+), 6 deletions(-)
 create mode 100644 tools/make_release.py

diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index bbd182866..129538f3d 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -2,6 +2,78 @@
 Changelog
 *********
 
+0.15.0
+======
+
+- Add codespell to detect typo
+- Add support for fuzzing and bagde for oss-fuzz
+- [osal]
+
+  - Allow the use of non-static allocation for FreeRTOS
+  - Fix FreeRTOS wrong task switch in some cases
+
+- Fix tu_fifo memory overflown when repeatedly write to overwritable fifo (accumulated more than 2 depths)
+- Better support for IAR (ARM) with ci build check for stm32 mcus.
+- Fix Windows build for some mingw gnu make situations
+  
+Controller Driver (DCD & HCD)
+-----------------------------
+
+- Add new port support (WIP) for WCH CH32V307 USB Highspeed
+- Add new port support (WIP) for PIC32MM/MX & PIC24
+
+- [nRF]
+
+  - Fix endpoint internal state when closed
+  - Fix reception of large ISO packets
+
+- [rp2040] 
+
+  - [dcd] Implement workaround for Errata 15. This enable SOF when bulk-in endpoint is in use and reduce its bandwidth to only 80%
+  - [hcd] Fix shared irq slots filling up when hcd_init() is called multiple times
+  - [hcd] Support host bulk endpoint using hw "interrupt" endpoint. Note speed limit is 64KB/s
+
+- [samd][dcd] Add support for ISO endpoint
+- [dwc2][dcd] Add support for stm32u5xx
+- [esp32sx] Fix Isochronous transfers only transmitted on even frame
+- [lpc_ip3511][dcd] Add isochronous support and fix endpoint accidental write
+- [ft90x] Improve and enhance support for FT9xx MCU, tested with more examples
+
+Device Stack
+------------
+
+- [Video]
+
+  - Add support for MJPEG
+  - Fix probe on macOS
+
+- [MIDI]
+
+  - Support port name strings
+  - fix MS Header wTotalLength computation
+ 
+- [HID]
+
+  - Add FIDO descriptor template
+  - change length in tud_hid_report_complete_cb() from uint8 to uint16
+
+- [CDC]
+
+  - Fix autoflush for FIFO < MPS
+  - Fix tx fifo memory overflown when DTR is not set and tud_cdc_write() is called repeatedly with large enough data  
+
+- [USBTMC] Fix packet size with highspeed
+
+Host Stack
+----------
+
+- Retry a few times with transfers in enumeration since device can be unstable when starting up
+- [MSC] Rework host masstorage API. Add new **host/msc_file_explorer** example
+- [CDC]
+
+  - Add suport for host cdc
+  - Fix host cdc with device without IAD e.g Arduino Due
+
 0.14.0
 ======
 
@@ -9,7 +81,8 @@ Changelog
 - Add timeout to osal_queue_receive()
 - Add tud_task_ext(timeout, in_isr) as generic version of tud_task(). Same as tuh_task_ext(), tuh_task()
 - Enable more warnings -Wnull-dereference -Wuninitialized -Wunused -Wredundant-decls -Wconversion
-- Add new examples 
+- Add new examples
+
   - host/bare_api to demonstrate generic (app-level) enumeration and endpoint transfer
   - dual/host_hid_to_device_cdc to run both device and host stack concurrently, get HID report from host and print out to device CDC. This example only work with multiple-controller MCUs and rp2040 with the help of pio-usb as added controller.
 
@@ -17,10 +90,12 @@ Controller Driver (DCD & HCD)
 -----------------------------
 
 - Enhance rhports management to better support dual roles
+
   - CFG_TUD_ENABLED/CFG_TUH_ENABLED, CFG_TUD_MAX_SPEED/CFG_TUH_MAX_SPEED can be used to replace CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE
   - tud_init(rphort), tuh_init(rhport) can be used to init stack on specified roothub port (controller) instead of tusb_init(void)
 - Add dcd/hcd port specific defines TUP_ (stand for tinyusb port-specific)
 - [dwc2]
+
   - Update to support stm32 h72x, h73x with only 1 otg controller
   - Fix overwrite with grstctl when disable endpoint
 - [EHCI] Fix an issue with EHCI driver
@@ -28,6 +103,7 @@ Controller Driver (DCD & HCD)
 - [nrf5x] Fix DMA access race condition using atomic function 
 - [pic32] Fix PIC32 santiy
 - [rp2040]
+
   - Add PICO-PIO-USB as controller (device/host) support for rp2040
   - Use shared IRQ handlers, so user can also hook the USB IRQ
   - Fix resumed signal not reported to device stack
@@ -37,10 +113,12 @@ Device Stack
 ------------
 
 - [Audio] Add support for feedback endpoint computation
+
   - New API tud_audio_feedback_params_cb(), tud_audio_feedback_interval_isr().
   - Supported computation method are: frequency with fixed/float or power of 2. Feedback with fifo count is not yet supported.
   - Fix nitfs (should be 3) in TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR
   - Fix typo in audiod_rx_done_cb()
+
 - [DFU] Fix coexistence with other interfaces BTH, RNDIS
 - [MSC] Fix inquiry response additional length field
 - [Venndor] Improve write performance
@@ -52,9 +130,11 @@ Host Stack
 - [HID] Open OUT endpoint if available
 - [Hub] hub clear port and device interrupts
 - [USBH] Major improvement
+
   - Rework usbh control transfer with complete callback. New API tuh_control_xfer() though still only carry 1 usbh (no queueing) at a time.
   - Add generic endpoint transfer with tuh_edpt_open(), tuh_edpt_xfer(). Require `CFG_TUH_API_EDPT_XFER=1`
   - Support app-level enumeration with new APIs
+
     - tuh_descriptor_get(), tuh_descriptor_get_device(), tuh_descriptor_get_configuration(), tuh_descriptor_get_hid_report()
     - tuh_descriptor_get_string(), tuh_descriptor_get_manufacturer_string(), tuh_descriptor_get_product_string(), tuh_descriptor_get_serial_string()
     - Also add _sync() as sync/blocking version for above APIs
diff --git a/repository.yml b/repository.yml
index dc341a3c1..702753a90 100644
--- a/repository.yml
+++ b/repository.yml
@@ -12,7 +12,6 @@ repo.versions:
     "0.12.0": "0.12.0"
     "0.13.0": "0.13.0"
     "0.14.0": "0.14.0"
-
-    "0-dev": "0.0.0"        # master
-    "0-latest": "0.14.0"    # latest stable release
-
+    "0.15.0": "0.15.0"
+    "0-latest": "0.15.0"
+    "0-dev": "0.0.0"
diff --git a/src/tusb_option.h b/src/tusb_option.h
index cf5b21c9c..eb46ce295 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -30,7 +30,7 @@
 #include "common/tusb_compiler.h"
 
 #define TUSB_VERSION_MAJOR     0
-#define TUSB_VERSION_MINOR     14
+#define TUSB_VERSION_MINOR     15
 #define TUSB_VERSION_REVISION  0
 #define TUSB_VERSION_STRING    TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
 
diff --git a/tools/make_release.py b/tools/make_release.py
new file mode 100644
index 000000000..7481e8864
--- /dev/null
+++ b/tools/make_release.py
@@ -0,0 +1,40 @@
+import re
+
+version = '0.15.0'
+
+print('version {}'.format(version))
+ver_id = version.split('.')
+
+###################
+# src/tusb_option.h
+###################
+f_option_h = 'src/tusb_option.h'
+
+with open(f_option_h) as f:
+    fdata = f.read()
+
+fdata = re.sub(r'(#define TUSB_VERSION_MAJOR *) \d+', r"\1 {}".format(ver_id[0]), fdata)
+fdata = re.sub(r'(#define TUSB_VERSION_MINOR *) \d+', r"\1 {}".format(ver_id[1]), fdata)
+fdata = re.sub(r'(#define TUSB_VERSION_REVISION *) \d+', r"\1 {}".format(ver_id[2]), fdata)
+
+# Write the file out again
+with open(f_option_h, 'w') as f:
+    f.write(fdata)
+
+###################
+# repository.yml
+###################
+f_repository_yml = 'repository.yml'
+with open(f_repository_yml) as f:
+    fdata = f.read()
+
+if fdata.find(version) < 0:
+    fdata = re.sub(r'("0-latest"): "\d+\.\d+\.\d+"', r'"{}": "{}"\r\n    \1: "{}"'.format(version, version, version), fdata)
+    with open(f_repository_yml, 'w') as f:
+        f.write(fdata)
+
+###################
+# docs/info/changelog.rst
+###################
+
+print("Update docs/info/changelog.rst")

From cf162e2c54025a9d361d85cecba3d46315f38b45 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Feb 2023 13:03:43 +0700
Subject: [PATCH 1455/2085] fix typo

---
 docs/info/changelog.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index 129538f3d..451e3dace 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -71,7 +71,7 @@ Host Stack
 - [MSC] Rework host masstorage API. Add new **host/msc_file_explorer** example
 - [CDC]
 
-  - Add suport for host cdc
+  - Add support for host cdc
   - Fix host cdc with device without IAD e.g Arduino Due
 
 0.14.0

From 39a37d82ceac9e208d931a7647c5545b36dd6b4a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Feb 2023 14:56:32 +0700
Subject: [PATCH 1456/2085] change rp2040 hw test to use pyocd for better
 stability/performance than openocd

---
 .github/workflows/build_arm.yml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 29c41a8eb..3bbd30e51 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -171,7 +171,7 @@ jobs:
   # - pico-probe is /dev/ttyACM0
   # ---------------------------------------
   hw-rp2040-test:
-    # Limit the run to only hathach due to limited resource on RPI4
+    # run only with hathach's commit due to limited resource on RPI4
     if: github.repository_owner == 'hathach'
     needs: build-arm
     runs-on: [self-hosted, Linux, ARM64, rp2040]
@@ -190,7 +190,8 @@ jobs:
 
     - name: Create flash.sh
       run: |
-        echo > flash.sh 'cmdout=$(openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit")'
+        #echo > flash.sh 'cmdout=$(openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit")'
+        echo > flash.sh 'pyocd flash -t rp2040 $1'
         echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
         chmod +x flash.sh
 

From f0ab6d824eace8d3e8dc8da47fb072ddb1986ac9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Feb 2023 15:41:48 +0700
Subject: [PATCH 1457/2085] increase hw test timeout to 10s since pyocd seems
 to take longer to flash

---
 .github/workflows/build_arm.yml | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 3bbd30e51..96c337462 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -198,7 +198,7 @@ jobs:
     - name: Test cdc_dual_ports
       run: |
         ./flash.sh cdc_dual_ports.elf
-        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
+        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
@@ -206,7 +206,7 @@ jobs:
       run: |
         ./flash.sh cdc_msc.elf
         readme='/media/pi/TinyUSB MSC/README.TXT'
-        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
+        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -f "$readme" && echo "$readme exists"
         cat "$readme"
@@ -214,7 +214,7 @@ jobs:
     - name: Test dfu
       run: |
         ./flash.sh dfu.elf
-        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
+        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
         dfu-util -d cafe -a 0 -U dfu0
         dfu-util -d cafe -a 1 -U dfu1
         grep "TinyUSB DFU! - Partition 0" dfu0
@@ -223,7 +223,7 @@ jobs:
     - name: Test dfu_runtime
       run: |
         ./flash.sh dfu_runtime.elf
-        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done
+        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
 
   # ---------------------------------------
   # Hardware in the loop (HIL)
@@ -261,7 +261,7 @@ jobs:
     - name: Test cdc_dual_ports
       run: |
         ./flash.sh cdc_dual_ports.elf
-        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 5 ]; do :; done
+        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -e /dev/ttyACM2 && echo "ttyACM2 exists"
 
@@ -271,7 +271,7 @@ jobs:
       run: |
         ./flash.sh cdc_msc.elf
         readme='/media/pi/TinyUSB MSC/README.TXT'
-        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 5 ]; do :; done
+        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
         test -e /dev/ttyACM1 && echo "ttyACM1 exists"
         test -f "$readme" && echo "$readme exists"
         cat "$readme"
@@ -279,7 +279,7 @@ jobs:
     - name: Test dfu
       run: |
         ./flash.sh dfu.elf
-        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 5 ]; do :; done
+        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
         dfu-util -d cafe -a 0 -U dfu0
         dfu-util -d cafe -a 1 -U dfu1
         grep "TinyUSB DFU! - Partition 0" dfu0
@@ -288,4 +288,4 @@ jobs:
     - name: Test dfu_runtime
       run: |
         ./flash.sh dfu_runtime.elf
-        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 5 ]; do :; done  
+        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done  

From f48ae4aad7dea10e318bf82d1b59a75a3c325697 Mon Sep 17 00:00:00 2001
From: Jeff Trull <edaskel@att.net>
Date: Fri, 10 Feb 2023 15:54:04 -0800
Subject: [PATCH 1458/2085] Adjust reserved bitfields to make SDCC happy

- keep each field at or under 16b
- For optimal packing, segment fields to 8b boundaries
---
 src/class/cdc/cdc.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index 2fecde3ca..842ea4dfe 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -377,7 +377,9 @@ typedef struct TU_ATTR_PACKED
     uint32_t incoming_distinctive   : 1; ///< 0 : Reports only incoming ringing. 1 : Reports incoming distinctive ringing patterns.
     uint32_t dual_tone_multi_freq   : 1; ///< 0 : Cannot report dual tone multi-frequency (DTMF) digits input remotely over the telephone line. 1 : Can report DTMF digits input remotely over the telephone line.
     uint32_t line_state_change      : 1; ///< 0 : Does not support line state change notification. 1 : Does support line state change notification
-    uint32_t TU_RESERVED            : 26;
+    uint32_t TU_RESERVED0           : 2;
+    uint32_t TU_RESERVED1           : 16;
+    uint32_t TU_RESERVED2           : 4;
   } bmCapabilities;
 }cdc_desc_func_telephone_call_state_reporting_capabilities_t;
 
@@ -404,7 +406,8 @@ typedef struct TU_ATTR_PACKED
 {
   uint16_t dtr : 1;
   uint16_t rts : 1;
-  uint16_t : 14;
+  uint16_t : 6;
+  uint16_t : 8;
 } cdc_line_control_state_t;
 
 TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct");

From ec26c6163c9d1cf0422537e8f167a783736aca0c Mon Sep 17 00:00:00 2001
From: caleb crome <caleb@crome.org>
Date: Sun, 12 Feb 2023 11:24:21 -0800
Subject: [PATCH 1459/2085] Turn data cache on This fixes
 https://github.com/hathach/tinyusb/issues/1894.  I'm not really sure if this
 is the correct way to fix it, and I have not tested on all the rest of the
 family members, however, this lets the i.MX1010 work again.

The problem:  the latest SDK update does not enable the data cache by default
This causes an assert in board_init() when attemping to control clock
gating.  I haven't investigated further as to *why* it's a problem, but it
is a problem.
---
 hw/bsp/imxrt/family.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index fc6e9e266..ecd18bad3 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -55,6 +55,12 @@ const uint8_t dcd_data[] = { 0x00 };
 
 void board_init(void)
 {
+  // make sure the dcache is on.
+#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
+    if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR))
+        SCB_EnableDCache();
+#endif
+
   // Init clock
   BOARD_BootClockRUN();
   SystemCoreClockUpdate();

From 7e2c5fcc8aa7c39f6c65d7cb85c7d4522b0050be Mon Sep 17 00:00:00 2001
From: Jeff Trull <edaskel@att.net>
Date: Sun, 12 Feb 2023 20:52:17 -0800
Subject: [PATCH 1460/2085] Correct bitfields for
 cdc_desc_func_telephone_call_state_reporting_capabilities_t

---
 src/class/cdc/cdc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h
index 842ea4dfe..4658e43af 100644
--- a/src/class/cdc/cdc.h
+++ b/src/class/cdc/cdc.h
@@ -379,7 +379,7 @@ typedef struct TU_ATTR_PACKED
     uint32_t line_state_change      : 1; ///< 0 : Does not support line state change notification. 1 : Does support line state change notification
     uint32_t TU_RESERVED0           : 2;
     uint32_t TU_RESERVED1           : 16;
-    uint32_t TU_RESERVED2           : 4;
+    uint32_t TU_RESERVED2           : 8;
   } bmCapabilities;
 }cdc_desc_func_telephone_call_state_reporting_capabilities_t;
 

From 105f108661b894b3a3bc9fe2e173556099bbd745 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Feb 2023 11:44:03 +0700
Subject: [PATCH 1461/2085] add metro m7 1011 board def (not running yet)

---
 examples/rules.mk                             |   7 +-
 hw/bsp/imxrt/boards/metro_m7_10111/board.h    |  53 ++++
 hw/bsp/imxrt/boards/metro_m7_10111/board.mk   |  14 +
 .../evkmimxrt1010_flexspi_nor_config.c        |  48 ++++
 .../evkmimxrt1010_flexspi_nor_config.h        | 267 ++++++++++++++++++
 hw/bsp/imxrt/family.mk                        |   5 +
 6 files changed, 388 insertions(+), 6 deletions(-)
 create mode 100644 hw/bsp/imxrt/boards/metro_m7_10111/board.h
 create mode 100644 hw/bsp/imxrt/boards/metro_m7_10111/board.mk
 create mode 100644 hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.c
 create mode 100644 hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.h

diff --git a/examples/rules.mk b/examples/rules.mk
index 6a62288ce..dcef934ab 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -170,12 +170,7 @@ $(BUILD)/$(PROJECT).elf: $(OBJ)
 endif
 
 # UF2 generation, iMXRT need to strip to text only before conversion
-ifeq ($(FAMILY),imxrt)
-$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	@$(OBJCOPY) -O ihex -R .flash_config -R .ivt $^ $(BUILD)/$(PROJECT)-textonly.hex
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -c -o $@ $(BUILD)/$(PROJECT)-textonly.hex
-else
+ifneq ($(FAMILY),imxrt)
 $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).hex
 	@echo CREATE $@
 	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -c -o $@ $^
diff --git a/hw/bsp/imxrt/boards/metro_m7_10111/board.h b/hw/bsp/imxrt/boards/metro_m7_10111/board.h
new file mode 100644
index 000000000..7fa2f8541
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_10111/board.h
@@ -0,0 +1,53 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "fsl_device_registers.h"
+
+// required since iMX RT10xx SDK include this file for board size
+#define BOARD_FLASH_SIZE     (8*1024*1024)
+
+// LED
+#define LED_PINMUX          IOMUXC_GPIO_03_GPIOMUX_IO03
+#define LED_PORT            GPIO1
+#define LED_PIN             3
+#define LED_STATE_ON        1
+
+// D2 as button
+#define BUTTON_PINMUX         IOMUXC_GPIO_13_GPIOMUX_IO13
+#define BUTTON_PORT           GPIO1
+#define BUTTON_PIN            13
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_PORT             LPUART1
+#define UART_RX_PINMUX        IOMUXC_GPIO_09_LPUART1_RXD
+#define UART_TX_PINMUX        IOMUXC_GPIO_10_LPUART1_TXD
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/imxrt/boards/metro_m7_10111/board.mk b/hw/bsp/imxrt/boards/metro_m7_10111/board.mk
new file mode 100644
index 000000000..7f1861ecc
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_10111/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
+MCU_VARIANT = MIMXRT1011
+
+# For flash-jlink target
+JLINK_DEVICE = MIMXRT1011DAE5A
+
+# For flash-pyocd target
+PYOCD_TARGET = mimxrt1010
+
+# flash using pyocd
+flash: flash-pyocd
+flash-uf2: $(BUILD)/$(PROJECT).uf2
+	@echo copying $<
+	@$(CP) $< /media/$(USER)/METROM7BOOT
diff --git a/hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.c b/hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.c
new file mode 100644
index 000000000..752a65629
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "evkmimxrt1010_flexspi_nor_config.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.xip_board"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
+__attribute__((section(".boot_hdr.conf")))
+#elif defined(__ICCARM__)
+#pragma location = ".boot_hdr.conf"
+#endif
+
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig =
+        {
+            .tag              = FLEXSPI_CFG_BLK_TAG,
+            .version          = FLEXSPI_CFG_BLK_VERSION,
+            .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+            .csHoldTime       = 3u,
+            .csSetupTime      = 3u,
+            .sflashPadType    = kSerialFlash_4Pads,
+            .serialClkFreq    = kFlexSpiSerialClk_100MHz,
+            .sflashA1Size     = 16u * 1024u * 1024u,
+            .lookupTable =
+                {
+                    // Read LUTs
+                    FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 24),
+                    FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
+                },
+        },
+    .pageSize           = 256u,
+    .sectorSize         = 4u * 1024u,
+    .blockSize          = 64u * 1024u,
+    .isUniformBlockSize = false,
+};
+#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.h b/hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.h
new file mode 100644
index 000000000..bb5a64448
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
+#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fsl_common.h"
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief XIP_BOARD driver version 2.0.0. */
+#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/* FLEXSPI memory config block related definitions */
+#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)     // ascii "FCFB" Big Endian
+#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
+#define FLEXSPI_CFG_BLK_SIZE (512)
+
+/* FLEXSPI Feature related definitions */
+#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
+
+/* Lookup table related definitions */
+#define CMD_INDEX_READ 0
+#define CMD_INDEX_READSTATUS 1
+#define CMD_INDEX_WRITEENABLE 2
+#define CMD_INDEX_WRITE 4
+
+#define CMD_LUT_SEQ_IDX_READ 0
+#define CMD_LUT_SEQ_IDX_READSTATUS 1
+#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
+#define CMD_LUT_SEQ_IDX_WRITE 9
+
+#define CMD_SDR 0x01
+#define CMD_DDR 0x21
+#define RADDR_SDR 0x02
+#define RADDR_DDR 0x22
+#define CADDR_SDR 0x03
+#define CADDR_DDR 0x23
+#define MODE1_SDR 0x04
+#define MODE1_DDR 0x24
+#define MODE2_SDR 0x05
+#define MODE2_DDR 0x25
+#define MODE4_SDR 0x06
+#define MODE4_DDR 0x26
+#define MODE8_SDR 0x07
+#define MODE8_DDR 0x27
+#define WRITE_SDR 0x08
+#define WRITE_DDR 0x28
+#define READ_SDR 0x09
+#define READ_DDR 0x29
+#define LEARN_SDR 0x0A
+#define LEARN_DDR 0x2A
+#define DATSZ_SDR 0x0B
+#define DATSZ_DDR 0x2B
+#define DUMMY_SDR 0x0C
+#define DUMMY_DDR 0x2C
+#define DUMMY_RWDS_SDR 0x0D
+#define DUMMY_RWDS_DDR 0x2D
+#define JMP_ON_CS 0x1F
+#define STOP 0
+
+#define FLEXSPI_1PAD 0
+#define FLEXSPI_2PAD 1
+#define FLEXSPI_4PAD 2
+#define FLEXSPI_8PAD 3
+
+#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
+    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
+     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
+
+//!@brief Definitions for FlexSPI Serial Clock Frequency
+typedef enum _FlexSpiSerialClockFreq
+{
+    kFlexSpiSerialClk_30MHz  = 1,
+    kFlexSpiSerialClk_50MHz  = 2,
+    kFlexSpiSerialClk_60MHz  = 3,
+    kFlexSpiSerialClk_75MHz  = 4,
+    kFlexSpiSerialClk_80MHz  = 5,
+    kFlexSpiSerialClk_100MHz = 6,
+    kFlexSpiSerialClk_120MHz = 7,
+    kFlexSpiSerialClk_133MHz = 8,
+} flexspi_serial_clk_freq_t;
+
+//!@brief FlexSPI clock configuration type
+enum
+{
+    kFlexSpiClk_SDR, //!< Clock configure for SDR mode
+    kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
+};
+
+//!@brief FlexSPI Read Sample Clock Source definition
+typedef enum _FlashReadSampleClkSource
+{
+    kFlexSPIReadSampleClk_LoopbackInternally      = 0,
+    kFlexSPIReadSampleClk_LoopbackFromDqsPad      = 1,
+    kFlexSPIReadSampleClk_LoopbackFromSckPad      = 2,
+    kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
+} flexspi_read_sample_clk_t;
+
+//!@brief Misc feature bit definitions
+enum
+{
+    kFlexSpiMiscOffset_DiffClkEnable            = 0, //!< Bit for Differential clock enable
+    kFlexSpiMiscOffset_Ck2Enable                = 1, //!< Bit for CK2 enable
+    kFlexSpiMiscOffset_ParallelEnable           = 2, //!< Bit for Parallel mode enable
+    kFlexSpiMiscOffset_WordAddressableEnable    = 3, //!< Bit for Word Addressable enable
+    kFlexSpiMiscOffset_SafeConfigFreqEnable     = 4, //!< Bit for Safe Configuration Frequency enable
+    kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
+    kFlexSpiMiscOffset_DdrModeEnable            = 6, //!< Bit for DDR clock confiuration indication.
+};
+
+//!@brief Flash Type Definition
+enum
+{
+    kFlexSpiDeviceType_SerialNOR    = 1,    //!< Flash devices are Serial NOR
+    kFlexSpiDeviceType_SerialNAND   = 2,    //!< Flash devices are Serial NAND
+    kFlexSpiDeviceType_SerialRAM    = 3,    //!< Flash devices are Serial RAM/HyperFLASH
+    kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
+    kFlexSpiDeviceType_MCP_NOR_RAM  = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
+};
+
+//!@brief Flash Pad Definitions
+enum
+{
+    kSerialFlash_1Pad  = 1,
+    kSerialFlash_2Pads = 2,
+    kSerialFlash_4Pads = 4,
+    kSerialFlash_8Pads = 8,
+};
+
+//!@brief FlexSPI LUT Sequence structure
+typedef struct _lut_sequence
+{
+    uint8_t seqNum; //!< Sequence Number, valid number: 1-16
+    uint8_t seqId;  //!< Sequence Index, valid number: 0-15
+    uint16_t reserved;
+} flexspi_lut_seq_t;
+
+//!@brief Flash Configuration Command Type
+enum
+{
+    kDeviceConfigCmdType_Generic,    //!< Generic command, for example: configure dummy cycles, drive strength, etc
+    kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
+    kDeviceConfigCmdType_Spi2Xpi,    //!< Switch from SPI to DPI/QPI/OPI mode
+    kDeviceConfigCmdType_Xpi2Spi,    //!< Switch from DPI/QPI/OPI to SPI mode
+    kDeviceConfigCmdType_Spi2NoCmd,  //!< Switch to 0-4-4/0-8-8 mode
+    kDeviceConfigCmdType_Reset,      //!< Reset device command
+};
+
+//!@brief FlexSPI Memory Configuration Block
+typedef struct _FlexSPIConfig
+{
+    uint32_t tag;               //!< [0x000-0x003] Tag, fixed value 0x42464346UL
+    uint32_t version;           //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
+    uint32_t reserved0;         //!< [0x008-0x00b] Reserved for future use
+    uint8_t readSampleClkSrc;   //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
+    uint8_t csHoldTime;         //!< [0x00d-0x00d] CS hold time, default value: 3
+    uint8_t csSetupTime;        //!< [0x00e-0x00e] CS setup time, default value: 3
+    uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
+    //! Serial NAND, need to refer to datasheet
+    uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
+    uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
+    //! Generic configuration, etc.
+    uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
+    //! DPI/QPI/OPI switch or reset command
+    flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
+    //! sequence number, [31:16] Reserved
+    uint32_t deviceModeArg;    //!< [0x018-0x01b] Argument/Parameter for device configuration
+    uint8_t configCmdEnable;   //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
+    uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
+    flexspi_lut_seq_t
+        configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
+    uint32_t reserved1;   //!< [0x02c-0x02f] Reserved for future use
+    uint32_t configCmdArgs[3];     //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
+    uint32_t reserved2;            //!< [0x03c-0x03f] Reserved for future use
+    uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
+    //! details
+    uint8_t deviceType;    //!< [0x044-0x044] Device Type:  See Flash Type Definition for more details
+    uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
+    uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
+    //! Chapter for more details
+    uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
+    //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
+    uint32_t reserved3[2];           //!< [0x048-0x04f] Reserved for future use
+    uint32_t sflashA1Size;           //!< [0x050-0x053] Size of Flash connected to A1
+    uint32_t sflashA2Size;           //!< [0x054-0x057] Size of Flash connected to A2
+    uint32_t sflashB1Size;           //!< [0x058-0x05b] Size of Flash connected to B1
+    uint32_t sflashB2Size;           //!< [0x05c-0x05f] Size of Flash connected to B2
+    uint32_t csPadSettingOverride;   //!< [0x060-0x063] CS pad setting override value
+    uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
+    uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
+    uint32_t dqsPadSettingOverride;  //!< [0x06c-0x06f] DQS pad setting override value
+    uint32_t timeoutInMs;            //!< [0x070-0x073] Timeout threshold for read status command
+    uint32_t commandInterval;        //!< [0x074-0x077] CS deselect interval between two commands
+    uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
+    uint16_t busyOffset;       //!< [0x07c-0x07d] Busy offset, valid value: 0-31
+    uint16_t busyBitPolarity;  //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
+    //! busy flag is 0 when flash device is busy
+    uint32_t lookupTable[64];           //!< [0x080-0x17f] Lookup table holds Flash command sequences
+    flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
+    uint32_t reserved4[4];              //!< [0x1b0-0x1bf] Reserved for future use
+} flexspi_mem_config_t;
+
+/*  */
+#define NOR_CMD_INDEX_READ CMD_INDEX_READ               //!< 0
+#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS   //!< 1
+#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
+#define NOR_CMD_INDEX_ERASESECTOR 3                     //!< 3
+#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE       //!< 4
+#define NOR_CMD_INDEX_CHIPERASE 5                       //!< 5
+#define NOR_CMD_INDEX_DUMMY 6                           //!< 6
+#define NOR_CMD_INDEX_ERASEBLOCK 7                      //!< 7
+
+#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0  READ LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
+    CMD_LUT_SEQ_IDX_READSTATUS //!< 1  Read Status LUT sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
+    2 //!< 2  Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
+    CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3  Write Enable sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
+    4 //!< 4  Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5  Erase Sector sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8  //!< 8 Erase Block sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
+    CMD_LUT_SEQ_IDX_WRITE                //!< 9  Program sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
+    14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
+#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
+    15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
+
+/*
+ *  Serial NOR configuration block
+ */
+typedef struct _flexspi_nor_config
+{
+    flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
+    uint32_t pageSize;              //!< Page size of Serial NOR
+    uint32_t sectorSize;            //!< Sector size of Serial NOR
+    uint8_t ipcmdSerialClkFreq;     //!< Clock frequency for IP command
+    uint8_t isUniformBlockSize;     //!< Sector/Block size is the same
+    uint8_t reserved0[2];           //!< Reserved for future use
+    uint8_t serialNorType;          //!< Serial NOR Flash type: 0/1/2/3
+    uint8_t needExitNoCmdMode;      //!< Need to exit NoCmd mode before other IP command
+    uint8_t halfClkForNonReadCmd;   //!< Half the Serial Clock for non-read command: true/false
+    uint8_t needRestoreNoCmdMode;   //!< Need to Restore NoCmd mode after IP command execution
+    uint32_t blockSize;             //!< Block size
+    uint32_t reserve2[11];          //!< Reserved for future use
+} flexspi_nor_config_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 0642e52e3..e9eeb42f1 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -61,3 +61,8 @@ SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
 # For freeRTOS port source
 FREERTOS_PORT = ARM_CM7/r0p1
 
+# UF2 generation, iMXRT need to strip to text only before conversion
+$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) -O ihex -R .flash_config -R .ivt $^ $(BUILD)/$(PROJECT)-textonly.hex
+	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -c -o $@ $(BUILD)/$(PROJECT)-textonly.hex

From 3e86f0532aae522513b5a5acdce71438dcca14fb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Feb 2023 12:03:04 +0700
Subject: [PATCH 1462/2085] fix release trigger body

---
 .github/workflows/trigger.yml | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/.github/workflows/trigger.yml b/.github/workflows/trigger.yml
index e434ca238..11e58d86c 100644
--- a/.github/workflows/trigger.yml
+++ b/.github/workflows/trigger.yml
@@ -55,6 +55,5 @@ jobs:
         git push origin ${{ github.event.release.tag_name }}
         
         # Send POST reqwuest to release https://docs.github.com/en/rest/reference/repos#create-a-release
-        bb={{ github.event.release.body }}
-        bb=${bb//\n/\\\n}
+        bb="For release note, please checkout https://github.com/hathach/tinyusb/releases/tag/${{ github.event.release.tag_name }}"
         curl -X POST -H "Authorization: token ${{ secrets.API_TOKEN_GITHUB }}" -H "Accept: application/vnd.github.v3+json" --data '{"tag_name": "${{ github.event.release.tag_name }}", "name": "${{ github.event.release.name }}", "body": "$bb", "draft": ${{ github.event.release.draft }}, "prerelease": ${{ github.event.release.prerelease }}}' https://api.github.com/repos/hathach/tinyusb_src/releases

From 49c621d51058289464abbcea5e7542b12b0a3bf8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Feb 2023 12:04:33 +0700
Subject: [PATCH 1463/2085] fix typo

---
 hw/bsp/imxrt/boards/{metro_m7_10111 => metro_m7_1011}/board.h     | 0
 hw/bsp/imxrt/boards/{metro_m7_10111 => metro_m7_1011}/board.mk    | 0
 .../evkmimxrt1010_flexspi_nor_config.c                            | 0
 .../evkmimxrt1010_flexspi_nor_config.h                            | 0
 4 files changed, 0 insertions(+), 0 deletions(-)
 rename hw/bsp/imxrt/boards/{metro_m7_10111 => metro_m7_1011}/board.h (100%)
 rename hw/bsp/imxrt/boards/{metro_m7_10111 => metro_m7_1011}/board.mk (100%)
 rename hw/bsp/imxrt/boards/{metro_m7_10111 => metro_m7_1011}/evkmimxrt1010_flexspi_nor_config.c (100%)
 rename hw/bsp/imxrt/boards/{metro_m7_10111 => metro_m7_1011}/evkmimxrt1010_flexspi_nor_config.h (100%)

diff --git a/hw/bsp/imxrt/boards/metro_m7_10111/board.h b/hw/bsp/imxrt/boards/metro_m7_1011/board.h
similarity index 100%
rename from hw/bsp/imxrt/boards/metro_m7_10111/board.h
rename to hw/bsp/imxrt/boards/metro_m7_1011/board.h
diff --git a/hw/bsp/imxrt/boards/metro_m7_10111/board.mk b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk
similarity index 100%
rename from hw/bsp/imxrt/boards/metro_m7_10111/board.mk
rename to hw/bsp/imxrt/boards/metro_m7_1011/board.mk
diff --git a/hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.c b/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.c
similarity index 100%
rename from hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.c
rename to hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.c
diff --git a/hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.h b/hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.h
similarity index 100%
rename from hw/bsp/imxrt/boards/metro_m7_10111/evkmimxrt1010_flexspi_nor_config.h
rename to hw/bsp/imxrt/boards/metro_m7_1011/evkmimxrt1010_flexspi_nor_config.h

From fb5fd22c730c58c5049ffb70a785d39f2d3daaba Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Feb 2023 12:29:31 +0700
Subject: [PATCH 1464/2085] add uf2 linker for metro m7 1011

---
 hw/bsp/imxrt/boards/metro_m7_1011/board.mk | 5 ++++-
 hw/bsp/imxrt/family.c                      | 3 +--
 hw/bsp/imxrt/family.mk                     | 7 ++++---
 3 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk
index 7f1861ecc..89a459958 100644
--- a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk
@@ -1,6 +1,9 @@
 CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
 MCU_VARIANT = MIMXRT1011
 
+# LD file with uf2
+LD_FILE = $(BOARD_PATH)/$(BOARD).ld
+
 # For flash-jlink target
 JLINK_DEVICE = MIMXRT1011DAE5A
 
@@ -8,7 +11,7 @@ JLINK_DEVICE = MIMXRT1011DAE5A
 PYOCD_TARGET = mimxrt1010
 
 # flash using pyocd
-flash: flash-pyocd
+flash: flash-uf2
 flash-uf2: $(BUILD)/$(PROJECT).uf2
 	@echo copying $<
 	@$(CP) $< /media/$(USER)/METROM7BOOT
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index ecd18bad3..e28a6174a 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -57,8 +57,7 @@ void board_init(void)
 {
   // make sure the dcache is on.
 #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
-    if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR))
-        SCB_EnableDCache();
+  if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) SCB_EnableDCache();
 #endif
 
   // Init clock
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index e9eeb42f1..99bb0a0f7 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -28,7 +28,7 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough -Wno-error
 MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
 
 # All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx_flexspi_nor.ld
+LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx_flexspi_nor.ld
 
 # TODO for net_lwip_webserver example, but may not needed !! 
 LDFLAGS += \
@@ -62,7 +62,8 @@ SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
 FREERTOS_PORT = ARM_CM7/r0p1
 
 # UF2 generation, iMXRT need to strip to text only before conversion
+APPLICATION_ADDR = 0x6000C000
 $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
-	@$(OBJCOPY) -O ihex -R .flash_config -R .ivt $^ $(BUILD)/$(PROJECT)-textonly.hex
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -c -o $@ $(BUILD)/$(PROJECT)-textonly.hex
+	@$(OBJCOPY) -O binary -R .flash_config -R .ivt $^ $(BUILD)/$(PROJECT)-textonly.bin
+	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b $(APPLICATION_ADDR) -c -o $@ $(BUILD)/$(PROJECT)-textonly.bin

From fbf99b8e53d05cdc7c79dd2397320f71a393e4b9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 13 Feb 2023 13:33:03 +0700
Subject: [PATCH 1465/2085] forget to add metro 1011 linker

---
 .../boards/metro_m7_1011/metro_m7_1011.ld     | 270 ++++++++++++++++++
 1 file changed, 270 insertions(+)
 create mode 100644 hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld

diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld
new file mode 100644
index 000000000..30dd84373
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld
@@ -0,0 +1,270 @@
+/*
+** ###################################################################
+**     Processors:          MIMXRT1011CAE4A
+**                          MIMXRT1011DAE5A
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    IMXRT1010RM Rev.0, 09/2019
+**     Version:             rev. 1.0, 2019-08-01
+**     Build:               b210709
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2021 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_flash_config        (RX)  : ORIGIN = 0x60000400, LENGTH = 0x00000C00
+  m_ivt                 (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
+  
+  m_interrupts          (RX)  : ORIGIN = 0x6000C000, LENGTH = 0x00000400
+  m_text                (RX)  : ORIGIN = 0x6000C400, LENGTH = (8*1024*1024 - 0xC400)
+  m_qacode              (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
+  m_data                (RW)  : ORIGIN = 0x20000000, LENGTH = 0x00008000
+  m_data2               (RW)  : ORIGIN = 0x20200000, LENGTH = 0x00010000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  __NCACHE_REGION_START = ORIGIN(m_data2);
+  __NCACHE_REGION_SIZE  = 0;
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    __FLASH_BASE = .;
+    KEEP(* (.boot_hdr.conf))     /* flash config section */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config);
+
+  .ivt : AT(ivt_begin)
+  {
+    . = ALIGN(4);
+    KEEP(* (.boot_hdr.ivt))           /* ivt section */
+    KEEP(* (.boot_hdr.boot_data))     /* boot section */
+    KEEP(* (.boot_hdr.dcd_data))      /* dcd section */
+    . = ALIGN(4);
+  } > m_ivt
+
+  /* The startup code goes first into internal RAM */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    __Vectors = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  /* The program code and other data goes into internal RAM */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(m_usb_dma_init_data)
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    *(DataQuickAccess)       /* quick access data section */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
+
+  .ram_function : AT(__ram_function_flash_start)
+  {
+    . = ALIGN(32);
+    __ram_function_start__ = .;
+    *(CodeQuickAccess)
+    . = ALIGN(128);
+    __ram_function_end__ = .;
+  } > m_qacode
+
+  __NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
+  .ncache.init : AT(__NDATA_ROM)
+  {
+    __noncachedata_start__ = .;   /* create a global symbol at ncache data start */
+    *(NonCacheable.init)
+    . = ALIGN(4);
+    __noncachedata_init_end__ = .;   /* create a global symbol at initialized ncache data end */
+  } > m_data
+  . = __noncachedata_init_end__;
+  .ncache :
+  {
+    *(NonCacheable)
+    . = ALIGN(4);
+    __noncachedata_end__ = .;     /* define a global symbol at ncache data end */
+  } > m_data
+
+  __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(m_usb_dma_noninit_data)
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}

From 95acf3960d343b3b8c1c52b1f7a1472885b968bd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 14 Feb 2023 16:11:33 +0700
Subject: [PATCH 1466/2085] update pico-pio-usb to include data pid fix (0.5.1)

---
 hw/mcu/raspberry_pi/Pico-PIO-USB | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mcu/raspberry_pi/Pico-PIO-USB b/hw/mcu/raspberry_pi/Pico-PIO-USB
index 52805e6d9..9ff3f52fd 160000
--- a/hw/mcu/raspberry_pi/Pico-PIO-USB
+++ b/hw/mcu/raspberry_pi/Pico-PIO-USB
@@ -1 +1 @@
-Subproject commit 52805e6d92556e67d3738bd8fb10227a45b13a08
+Subproject commit 9ff3f52fd3c1f81532bce8dd311aa8fc8d9b2665

From fde757711785670a005095454cc0b06129f8ae80 Mon Sep 17 00:00:00 2001
From: rppicomidi <rppicomidi@gmail.com>
Date: Wed, 15 Feb 2023 20:02:12 -0800
Subject: [PATCH 1467/2085] Fix issue 1909

---
 src/class/midi/midi_device.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index de41706e8..eb1a770dd 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -261,11 +261,11 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
       stream->buffer[1] = data;
 
       // Check to see if we're still in a SysEx transmit.
-      if ( stream->buffer[0] == MIDI_CIN_SYSEX_START )
+      if ( ((stream->buffer[0]) & 0xF) == MIDI_CIN_SYSEX_START )
       {
         if ( data == MIDI_STATUS_SYSEX_END )
         {
-          stream->buffer[0] = MIDI_CIN_SYSEX_END_1BYTE;
+          stream->buffer[0] = (uint8_t) ((cable_num << 4) | MIDI_CIN_SYSEX_END_1BYTE);
           stream->total = 2;
         }
         else
@@ -308,6 +308,7 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
           stream->buffer[0] = MIDI_CIN_SYSEX_END_1BYTE;
           stream->total = 2;
         }
+        stream->buffer[0] |= (uint8_t)(cable_num << 4);
       }
       else
       {
@@ -328,9 +329,9 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const*
       stream->index++;
 
       // See if this byte ends a SysEx.
-      if ( stream->buffer[0] == MIDI_CIN_SYSEX_START && data == MIDI_STATUS_SYSEX_END )
+      if ( (stream->buffer[0] & 0xF) == MIDI_CIN_SYSEX_START && data == MIDI_STATUS_SYSEX_END )
       {
-        stream->buffer[0] = MIDI_CIN_SYSEX_START + (stream->index - 1);
+        stream->buffer[0] = (uint8_t) ((cable_num << 4) | (MIDI_CIN_SYSEX_START + (stream->index - 1)));
         stream->total = stream->index;
       }
     }

From d367e8f8a8acd82c89ba3c029495b9404c3b7fdb Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sat, 4 Jun 2022 13:44:22 +0930
Subject: [PATCH 1468/2085] ohci: Expand roothub descriptors into unions

---
 src/portable/ohci/ohci.h | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index f40ae24cc..c42db141a 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -230,8 +230,27 @@ typedef volatile struct
   uint32_t periodic_start;
   uint32_t lowspeed_threshold;
 
-  uint32_t rh_descriptorA;
-  uint32_t rh_descriptorB;
+  union {
+    uint32_t rh_descriptorA;
+    struct {
+      uint32_t number_downstream_ports     : 8;
+      uint32_t power_switching_mode        : 1;
+      uint32_t no_power_switching          : 1;
+      uint32_t device_type                 : 1;
+      uint32_t overcurrent_protection_mode : 1;
+      uint32_t no_over_current_protection  : 1;
+      uint32_t reserved                    : 11;
+      uint32_t power_on_to_good_time       : 8;
+    } rh_descriptorA_bit;
+  };
+
+  union {
+    uint32_t rh_descriptorB;
+    struct {
+      uint32_t device_removable        : 16;
+      uint32_t port_power_control_mask : 16;
+    } rh_descriptorB_bit;
+  };
 
   union {
     uint32_t rh_status;

From c820c8769267644af049e0be73b04b45d57e8d98 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sat, 4 Jun 2022 13:47:02 +0930
Subject: [PATCH 1469/2085] ohci: Support configurable number of roothub ports

---
 src/common/tusb_mcu.h    |  1 +
 src/portable/ohci/ohci.c | 43 ++++++++++++++++++++++------------------
 src/portable/ohci/ohci.h |  6 +++---
 3 files changed, 28 insertions(+), 22 deletions(-)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 0b10c5118..ee2b896ac 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -55,6 +55,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   #define TUP_DCD_ENDPOINT_MAX    16
   #define TUP_USBIP_OHCI
+  #define OHCI_RHPORTS            2
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 228da6ae0..45600c03b 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -28,6 +28,10 @@
 
 #if CFG_TUH_ENABLED && defined(TUP_USBIP_OHCI)
 
+#ifndef OHCI_RHPORTS
+#error  OHCI is enabled, but OHCI_RHPORTS is not defined.
+#endif
+
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+
@@ -620,29 +624,30 @@ void hcd_int_handler(uint8_t hostid)
   //------------- RootHub status -------------//
   if ( int_status & OHCI_INT_RHPORT_STATUS_CHANGE_MASK )
   {
-    uint32_t const rhport_status = OHCI_REG->rhport_status[0] & RHPORT_ALL_CHANGE_MASK;
-
-    // TODO dual port is not yet supported
-    if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK )
+    for (int i = 0; i < OHCI_RHPORTS; i++)
     {
-      // TODO check if remote wake-up
-      if ( OHCI_REG->rhport_status_bit[0].current_connect_status )
+      uint32_t const rhport_status = OHCI_REG->rhport_status[i] & RHPORT_ALL_CHANGE_MASK;
+      if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK )
       {
-        // TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
-        OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK;
-        hcd_event_device_attach(hostid, true);
-      }else
-      {
-        hcd_event_device_remove(hostid, true);
+        // TODO check if remote wake-up
+        if ( OHCI_REG->rhport_status_bit[i].current_connect_status )
+        {
+          // TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
+          OHCI_REG->rhport_status[i] = RHPORT_PORT_RESET_STATUS_MASK;
+          hcd_event_device_attach(i, true);
+        }else
+        {
+          hcd_event_device_remove(i, true);
+        }
       }
+
+      if ( rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK)
+      {
+
+      }
+
+      OHCI_REG->rhport_status[i] = rhport_status; // acknowledge all interrupt
     }
-
-    if ( rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK)
-    {
-
-    }
-
-    OHCI_REG->rhport_status[0] = rhport_status; // acknowledge all interrupt
   }
 
   //------------- Transfer Complete -------------//
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index c42db141a..b7706b636 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -267,7 +267,7 @@ typedef volatile struct
   };
 
   union {
-    uint32_t rhport_status[2]; // TODO NXP OHCI controller only has 2 ports
+    uint32_t rhport_status[OHCI_RHPORTS];
     struct {
       uint32_t current_connect_status             : 1;
       uint32_t port_enable_status                 : 1;
@@ -284,11 +284,11 @@ typedef volatile struct
       uint32_t port_over_current_indicator_change : 1;
       uint32_t port_reset_status_change           : 1;
       uint32_t TU_RESERVED                        : 11;
-    }rhport_status_bit[2];
+    }rhport_status_bit[OHCI_RHPORTS];
   };
 }ohci_registers_t;
 
-TU_VERIFY_STATIC( sizeof(ohci_registers_t) == 0x5c, "size is not correct");
+TU_VERIFY_STATIC( sizeof(ohci_registers_t) == (0x54 + (4 * OHCI_RHPORTS)), "size is not correct");
 
 #ifdef __cplusplus
  }

From d5e6d028171a38e435ac1ab7c18ae5615f8af5cf Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sat, 4 Jun 2022 14:06:23 +0930
Subject: [PATCH 1470/2085] ohci: Leave SMM or bios mode during init

---
 src/portable/ohci/ohci.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 45600c03b..364f61cf1 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -177,6 +177,22 @@ bool hcd_init(uint8_t rhport)
   ohci_data.bulk_head_ed.skip   = 1;
   ohci_data.period_head_ed.skip = 1;
 
+  //If OHCI hardware is in SMM mode, gain ownership (Ref OHCI spec 5.1.1.3.3)
+  if (OHCI_REG->control_bit.interrupt_routing == 1)
+  {
+    OHCI_REG->command_status_bit.ownership_change_request = 1;
+    while (OHCI_REG->control_bit.interrupt_routing == 1) {}
+  }
+
+  //If OHCI hardware has come from warm-boot, signal resume (Ref OHCI spec 5.1.1.3.4)
+  else if (OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_RESET &&
+           OHCI_REG->control_bit.hc_functional_state != OHCI_CONTROL_FUNCSTATE_OPERATIONAL)
+  {
+    //Wait 20 ms. (Ref Usb spec 7.1.7.7)
+    OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_RESUME;
+    osal_task_delay(20);
+  }
+
   // reset controller
   OHCI_REG->command_status_bit.controller_reset = 1;
   while( OHCI_REG->command_status_bit.controller_reset ) {} // should not take longer than 10 us

From 2063ee5f1592979cc858b748aff51dba7cb3bcd5 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sat, 4 Jun 2022 14:09:21 +0930
Subject: [PATCH 1471/2085] ohci: Toggle frameinterval bit on update

---
 src/portable/ohci/ohci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 364f61cf1..cf6cff364 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -212,6 +212,7 @@ bool hcd_init(uint8_t rhport)
        OHCI_CONTROL_LIST_BULK_ENABLE_MASK | OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK; // TODO Isochronous
 
   OHCI_REG->frame_interval = (OHCI_FMINTERVAL_FSMPS << 16) | OHCI_FMINTERVAL_FI;
+  OHCI_REG->frame_interval ^= (1 << 31); //Must toggle when frame_interval is updated.
   OHCI_REG->periodic_start = (OHCI_FMINTERVAL_FI * 9) / 10; // Periodic start is 90% of frame interval
 
   OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power)

From c1d0fd1bd747bfc4881ecf69bc60fbcb106a7afd Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sat, 4 Jun 2022 14:11:34 +0930
Subject: [PATCH 1472/2085] ohci: Wait POTG time after port power

---
 src/portable/ohci/ohci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index cf6cff364..0a715a962 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -217,6 +217,7 @@ bool hcd_init(uint8_t rhport)
 
   OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power)
   OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports
+  osal_task_delay(OHCI_REG->rh_descriptorA_bit.power_on_to_good_time * 2); // Wait POTG after power up
 
   return true;
 }

From 5d3c0fb922604989e7f7e7f628fe43553ac78df7 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sat, 4 Jun 2022 14:14:53 +0930
Subject: [PATCH 1473/2085] ohci: Force reset of devices already connected on
 power up

---
 src/portable/ohci/ohci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 0a715a962..85795c5b4 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -208,7 +208,7 @@ bool hcd_init(uint8_t rhport)
       OHCI_INT_UNRECOVERABLE_ERROR_MASK | OHCI_INT_FRAME_OVERFLOW_MASK | OHCI_INT_RHPORT_STATUS_CHANGE_MASK |
       OHCI_INT_MASTER_ENABLE_MASK;
 
-  OHCI_REG->control |= OHCI_CONTROL_CONTROL_BULK_RATIO | OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK |
+  OHCI_REG->control = OHCI_CONTROL_CONTROL_BULK_RATIO | OHCI_CONTROL_LIST_CONTROL_ENABLE_MASK |
        OHCI_CONTROL_LIST_BULK_ENABLE_MASK | OHCI_CONTROL_LIST_PERIODIC_ENABLE_MASK; // TODO Isochronous
 
   OHCI_REG->frame_interval = (OHCI_FMINTERVAL_FSMPS << 16) | OHCI_FMINTERVAL_FI;

From e89e8ba392dae795663169d02952116b3f3980f3 Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Sat, 4 Jun 2022 14:18:53 +0930
Subject: [PATCH 1474/2085] ohci: Direct port commands to the correct rhport.

---
 src/portable/ohci/ohci.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 85795c5b4..b0c6bb63c 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -234,8 +234,7 @@ uint32_t hcd_frame_number(uint8_t rhport)
 //--------------------------------------------------------------------+
 void hcd_port_reset(uint8_t hostid)
 {
-  (void) hostid;
-  OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK;
+  OHCI_REG->rhport_status[hostid] = RHPORT_PORT_RESET_STATUS_MASK;
 }
 
 void hcd_port_reset_end(uint8_t rhport)
@@ -245,14 +244,12 @@ void hcd_port_reset_end(uint8_t rhport)
 
 bool hcd_port_connect_status(uint8_t hostid)
 {
-  (void) hostid;
-  return OHCI_REG->rhport_status_bit[0].current_connect_status;
+  return OHCI_REG->rhport_status_bit[hostid].current_connect_status;
 }
 
 tusb_speed_t hcd_port_speed_get(uint8_t hostid)
 {
-  (void) hostid;
-  return OHCI_REG->rhport_status_bit[0].low_speed_device_attached ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
+  return OHCI_REG->rhport_status_bit[hostid].low_speed_device_attached ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
 }
 
 // endpoints are tied to an address, which only reclaim after a long delay when enumerating

From cc9c3feeaee69b369aea4fb4f70e4f0fb1033990 Mon Sep 17 00:00:00 2001
From: Ryan Wendland <wendland@live.com.au>
Date: Sat, 4 Jun 2022 22:40:06 +0930
Subject: [PATCH 1475/2085] ohci: Fix bug in ed removal

---
 src/portable/ohci/ohci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index b0c6bb63c..59ffd2725 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -383,6 +383,7 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
       // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
       ed->next = (uint32_t) p_head;
       ed->used = 0;
+      continue;
     }
 
     // check next valid since we could remove it

From f87262185ec64e6ad616972720a72ffed65708ac Mon Sep 17 00:00:00 2001
From: Ryan Wendland <wendland@live.com.au>
Date: Sat, 4 Jun 2022 22:49:07 +0930
Subject: [PATCH 1476/2085] ohci: Set skip on ed prior to removal

---
 src/portable/ohci/ohci.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 59ffd2725..d51b9a883 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -377,12 +377,16 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
 
     if (ed->dev_addr == dev_addr)
     {
+      //Prevent Host Controller from processing this ED while we remove it
+      ed->skip = 1;
+
       // unlink ed
       p_prev->next = ed->next;
 
       // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
       ed->next = (uint32_t) p_head;
       ed->used = 0;
+      ed->skip = 0;
       continue;
     }
 

From f2a6af05b1cd7c298e6781e4374d744e2625c63f Mon Sep 17 00:00:00 2001
From: Ryan Wendland <wendland@live.com.au>
Date: Thu, 9 Jun 2022 08:32:49 +0930
Subject: [PATCH 1477/2085] ohci: Add ability to separate physical and virtual
 memory

---
 src/portable/ohci/ohci.c | 51 ++++++++++++++++++++++++++--------------
 1 file changed, 34 insertions(+), 17 deletions(-)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index d51b9a883..d85550d80 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -161,6 +161,22 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr);
 //--------------------------------------------------------------------+
 // USBH-HCD API
 //--------------------------------------------------------------------+
+
+//If your system requires separation of virtual and physical memory, implement
+//tuh_get_phys_addr and tuh_get_virt_addr in your application.
+TU_ATTR_WEAK void *tuh_get_phys_addr(void *virtual_address);
+TU_ATTR_WEAK void *tuh_get_virt_addr(void *physical_address);
+TU_ATTR_ALWAYS_INLINE static void *_phys_addr(void *virtual_address)
+{
+  if (tuh_get_phys_addr) return tuh_get_phys_addr(virtual_address);
+  return virtual_address;
+}
+TU_ATTR_ALWAYS_INLINE static void *_virt_addr(void *physical_address)
+{
+  if (tuh_get_virt_addr) return tuh_get_virt_addr(physical_address);
+  return physical_address;
+}
+
 // Initialization according to 5.1.1.4
 bool hcd_init(uint8_t rhport)
 {
@@ -170,7 +186,7 @@ bool hcd_init(uint8_t rhport)
   tu_memclr(&ohci_data, sizeof(ohci_data_t));
   for(uint8_t i=0; i<32; i++)
   { // assign all interrupt pointers to period head ed
-    ohci_data.hcca.interrupt_table[i] = (uint32_t) &ohci_data.period_head_ed;
+    ohci_data.hcca.interrupt_table[i] = (uint32_t) _phys_addr(&ohci_data.period_head_ed);
   }
 
   ohci_data.control[0].ed.skip  = 1;
@@ -198,9 +214,9 @@ bool hcd_init(uint8_t rhport)
   while( OHCI_REG->command_status_bit.controller_reset ) {} // should not take longer than 10 us
 
   //------------- init ohci registers -------------//
-  OHCI_REG->control_head_ed = (uint32_t) &ohci_data.control[0].ed;
-  OHCI_REG->bulk_head_ed    = (uint32_t) &ohci_data.bulk_head_ed;
-  OHCI_REG->hcca            = (uint32_t) &ohci_data.hcca;
+  OHCI_REG->control_head_ed = (uint32_t) _phys_addr(&ohci_data.control[0].ed);
+  OHCI_REG->bulk_head_ed    = (uint32_t) _phys_addr(&ohci_data.bulk_head_ed);
+  OHCI_REG->hcca            = (uint32_t) _phys_addr(&ohci_data.hcca);
 
   OHCI_REG->interrupt_disable = OHCI_REG->interrupt_enable; // disable all interrupts
   OHCI_REG->interrupt_status  = OHCI_REG->interrupt_status; // clear current set bits
@@ -327,8 +343,8 @@ static void gtd_init(ohci_gtd_t* p_td, uint8_t* data_ptr, uint16_t total_bytes)
   p_td->delay_interrupt        = OHCI_INT_ON_COMPLETE_NO;
   p_td->condition_code         = OHCI_CCODE_NOT_ACCESSED;
 
-  p_td->current_buffer_pointer = data_ptr;
-  p_td->buffer_end             = total_bytes ? (data_ptr + total_bytes-1) : data_ptr;
+  p_td->current_buffer_pointer = _phys_addr(data_ptr);
+  p_td->buffer_end             = total_bytes ? (_phys_addr(data_ptr + total_bytes - 1)) : (uint8_t *)p_td->current_buffer_pointer;
 }
 
 static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
@@ -364,7 +380,7 @@ static ohci_ed_t * ed_find_free(void)
 static void ed_list_insert(ohci_ed_t * p_pre, ohci_ed_t * p_ed)
 {
   p_ed->next = p_pre->next;
-  p_pre->next = (uint32_t) p_ed;
+  p_pre->next = (uint32_t) _phys_addr(p_ed);
 }
 
 static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
@@ -373,7 +389,7 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
 
   while( p_prev->next )
   {
-    ohci_ed_t* ed = (ohci_ed_t*) p_prev->next;
+    ohci_ed_t* ed = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
 
     if (ed->dev_addr == dev_addr)
     {
@@ -384,14 +400,14 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
       p_prev->next = ed->next;
 
       // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
-      ed->next = (uint32_t) p_head;
+      ed->next = (uint32_t) _phys_addr(p_head);
       ed->used = 0;
       ed->skip = 0;
       continue;
     }
 
     // check next valid since we could remove it
-    if (p_prev->next) p_prev = (ohci_ed_t*) p_prev->next;
+    if (p_prev->next) p_prev = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
   }
 }
 
@@ -410,11 +426,11 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
   // tail is always NULL
   if ( tu_align16(p_ed->td_head.address) == 0 )
   { // TD queue is empty --> head = TD
-    p_ed->td_head.address |= (uint32_t) p_gtd;
+    p_ed->td_head.address |= (uint32_t) _phys_addr(p_gtd);
   }
   else
   { // TODO currently only support queue up to 2 TD each endpoint at a time
-    ((ohci_gtd_t*) tu_align16(p_ed->td_head.address))->next = (uint32_t) p_gtd;
+    ((ohci_gtd_t*) tu_align16((uint32_t)_virt_addr((void *)p_ed->td_head.address)))->next = (uint32_t) _phys_addr(p_gtd);
   }
 }
 
@@ -470,7 +486,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   qtd->delay_interrupt = 0;
 
   //------------- Attach TDs list to Control Endpoint -------------//
-  ed->td_head.address = (uint32_t) qtd;
+  ed->td_head.address = (uint32_t) _phys_addr(qtd);
 
   OHCI_REG->command_status_bit.control_list_filled = 1;
 
@@ -496,7 +512,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     gtd->data_toggle     = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1
     gtd->delay_interrupt = 0;
 
-    ed->td_head.address = (uint32_t) gtd;
+    ed->td_head.address = (uint32_t) _phys_addr(gtd);
 
     OHCI_REG->command_status_bit.control_list_filled = 1;
   }else
@@ -544,16 +560,17 @@ static ohci_td_item_t* list_reverse(ohci_td_item_t* td_head)
 
   while(td_head != NULL)
   {
+    td_head = _virt_addr(td_head);
     uint32_t next = td_head->next;
 
     // make current's item become reverse's first item
     td_head->next = (uint32_t) td_reverse_head;
-    td_reverse_head  = td_head;
+    td_reverse_head  = _phys_addr(td_head);
 
     td_head = (ohci_td_item_t*) next; // advance to next item
   }
 
-  return td_reverse_head;
+  return _virt_addr(td_reverse_head);
 }
 
 static inline bool gtd_is_control(ohci_gtd_t const * const p_qtd)
@@ -624,7 +641,7 @@ static void done_queue_isr(uint8_t hostid)
       hcd_event_xfer_complete(ed->dev_addr, tu_edpt_addr(ed->ep_number, dir), xferred_bytes, event, true);
     }
 
-    td_head = (ohci_td_item_t*) td_head->next;
+    td_head = (ohci_td_item_t*) _virt_addr((void *)td_head->next);
   }
 }
 

From 75f6583c1c9ad3e0c2fc9e3427a649edbf765bef Mon Sep 17 00:00:00 2001
From: Ryzee119 <wendland@live.com.au>
Date: Mon, 13 Jun 2022 13:01:41 +0930
Subject: [PATCH 1478/2085] ohci: Use enum instead of magic number

---
 src/portable/ohci/ohci.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index d85550d80..d16de0cca 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -483,7 +483,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   qtd->index           = dev_addr;
   qtd->pid             = PID_SETUP;
   qtd->data_toggle     = GTD_DT_DATA0;
-  qtd->delay_interrupt = 0;
+  qtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
 
   //------------- Attach TDs list to Control Endpoint -------------//
   ed->td_head.address = (uint32_t) _phys_addr(qtd);
@@ -510,7 +510,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     gtd->index           = dev_addr;
     gtd->pid             = dir ? PID_IN : PID_OUT;
     gtd->data_toggle     = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1
-    gtd->delay_interrupt = 0;
+    gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
 
     ed->td_head.address = (uint32_t) _phys_addr(gtd);
 
@@ -524,7 +524,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
     gtd_init(gtd, buffer, buflen);
     gtd->index = ed-ohci_data.ed_pool;
-    gtd->delay_interrupt = 0;
+    gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
 
     td_insert_to_ed(ed, gtd);
 

From 4e2afdf5e1d72a2232f349a878c3d4147fc43cd6 Mon Sep 17 00:00:00 2001
From: wooyay <7655456+wooyay@users.noreply.github.com>
Date: Tue, 14 Feb 2023 17:03:19 +0000
Subject: [PATCH 1479/2085] ohci: Disable MIE interrupt during IRQ processing,
 zero HccADoneHead on completion

---
 src/portable/ohci/ohci.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index d16de0cca..76f97844c 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -606,6 +606,7 @@ static void done_queue_isr(uint8_t hostid)
 
   // done head is written in reversed order of completion --> need to reverse the done queue first
   ohci_td_item_t* td_head = list_reverse ( (ohci_td_item_t*) tu_align16(ohci_data.hcca.done_head) );
+  ohci_data.hcca.done_head = 0;
 
   while( td_head != NULL )
   {
@@ -652,6 +653,9 @@ void hcd_int_handler(uint8_t hostid)
 
   if (int_status == 0) return;
 
+  // Disable MIE as per OHCI spec 5.3
+  OHCI_REG->interrupt_disable = OHCI_INT_MASTER_ENABLE_MASK;
+
   // Frame number overflow
   if ( int_status & OHCI_INT_FRAME_OVERFLOW_MASK )
   {
@@ -694,6 +698,8 @@ void hcd_int_handler(uint8_t hostid)
   }
 
   OHCI_REG->interrupt_status = int_status; // Acknowledge handled interrupt
+
+  OHCI_REG->interrupt_enable = OHCI_INT_MASTER_ENABLE_MASK; // Enable MIE
 }
 //--------------------------------------------------------------------+
 // HELPER

From 03ec49450d2109a0e6ede3672e95426fd87aa48f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Feb 2023 11:47:09 +0700
Subject: [PATCH 1480/2085] rename maros from FUZZ to _FUZZ, change TU_STATIC
 to static _fuzz_thread

---
 .vscode/settings.json            |  3 ---
 src/class/cdc/cdc_device.c       |  2 +-
 src/class/dfu/dfu_device.c       | 14 +++++++-------
 src/class/hid/hid_device.c       |  2 +-
 src/class/msc/msc_device.c       |  8 ++++----
 src/class/net/ecm_rndis_device.c | 17 ++++++++++-------
 src/class/net/ncm_device.c       | 12 ++++++------
 src/class/usbtmc/usbtmc_device.c |  8 ++++----
 src/class/vendor/vendor_device.c |  2 +-
 src/class/vendor/vendor_device.h |  3 +--
 src/class/video/video_device.c   |  8 ++++----
 src/common/tusb_compiler.h       |  6 +++---
 src/common/tusb_debug.h          |  2 +-
 src/common/tusb_types.h          |  4 ++--
 src/device/usbd.c                | 18 +++++++++---------
 src/device/usbd_control.c        |  4 ++--
 test/fuzz/make.mk                |  2 +-
 17 files changed, 57 insertions(+), 58 deletions(-)
 delete mode 100644 .vscode/settings.json

diff --git a/.vscode/settings.json b/.vscode/settings.json
deleted file mode 100644
index 97924983a..000000000
--- a/.vscode/settings.json
+++ /dev/null
@@ -1,3 +0,0 @@
-{
-    "editor.formatOnSave": false
-}
\ No newline at end of file
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index b943c1caf..59ed2a74c 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -76,7 +76,7 @@ typedef struct
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION TU_STATIC cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
+CFG_TUSB_MEM_SECTION static _fuzz_thread cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
 
 static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
 {
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index a318603d3..9e7b8b5b1 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -56,7 +56,7 @@ typedef struct
 } dfu_state_ctx_t;
 
 // Only a single dfu state is allowed
-CFG_TUSB_MEM_SECTION TU_STATIC dfu_state_ctx_t _dfu_ctx;
+CFG_TUSB_MEM_SECTION static _fuzz_thread dfu_state_ctx_t _dfu_ctx;
 
 static void reset_state(void)
 {
@@ -74,7 +74,7 @@ static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_cont
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
 
-TU_STATIC tu_lookup_entry_t const _dfu_request_lookup[] =
+static _fuzz_thread tu_lookup_entry_t const _dfu_request_lookup[] =
 {
   { .key = DFU_REQUEST_DETACH         , .data = "DETACH"    },
   { .key = DFU_REQUEST_DNLOAD         , .data = "DNLOAD"    },
@@ -85,13 +85,13 @@ TU_STATIC tu_lookup_entry_t const _dfu_request_lookup[] =
   { .key = DFU_REQUEST_ABORT          , .data = "ABORT"     },
 };
 
-TU_STATIC tu_lookup_table_t const _dfu_request_table =
+static _fuzz_thread tu_lookup_table_t const _dfu_request_table =
 {
   .count = TU_ARRAY_SIZE(_dfu_request_lookup),
   .items = _dfu_request_lookup
 };
 
-TU_STATIC tu_lookup_entry_t const _dfu_state_lookup[] =
+static _fuzz_thread tu_lookup_entry_t const _dfu_state_lookup[] =
 {
   { .key = APP_IDLE                   , .data = "APP_IDLE"                },
   { .key = APP_DETACH                 , .data = "APP_DETACH"              },
@@ -106,13 +106,13 @@ TU_STATIC tu_lookup_entry_t const _dfu_state_lookup[] =
   { .key = DFU_ERROR                  , .data = "ERROR"               },
 };
 
-TU_STATIC tu_lookup_table_t const _dfu_state_table =
+static _fuzz_thread tu_lookup_table_t const _dfu_state_table =
 {
   .count = TU_ARRAY_SIZE(_dfu_state_lookup),
   .items = _dfu_state_lookup
 };
 
-TU_STATIC tu_lookup_entry_t const _dfu_status_lookup[] =
+static _fuzz_thread tu_lookup_entry_t const _dfu_status_lookup[] =
 {
   { .key = DFU_STATUS_OK               , .data = "OK"              },
   { .key = DFU_STATUS_ERR_TARGET       , .data = "errTARGET"       },
@@ -132,7 +132,7 @@ TU_STATIC tu_lookup_entry_t const _dfu_status_lookup[] =
   { .key = DFU_STATUS_ERR_STALLEDPKT   , .data = "errSTALLEDPKT"   },
 };
 
-TU_STATIC tu_lookup_table_t const _dfu_status_table =
+static _fuzz_thread tu_lookup_table_t const _dfu_status_table =
 {
   .count = TU_ARRAY_SIZE(_dfu_status_lookup),
   .items = _dfu_status_lookup
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index c42d1b6de..546c93010 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -58,7 +58,7 @@ typedef struct
   tusb_hid_descriptor_hid_t const * hid_descriptor;
 } hidd_interface_t;
 
-CFG_TUSB_MEM_SECTION TU_STATIC hidd_interface_t _hidd_itf[CFG_TUD_HID];
+CFG_TUSB_MEM_SECTION static _fuzz_thread hidd_interface_t _hidd_itf[CFG_TUD_HID];
 
 /*------------- Helpers -------------*/
 static inline uint8_t get_index_by_itfnum(uint8_t itf_num)
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index bf56ed9bf..e77342777 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -71,8 +71,8 @@ typedef struct
   uint8_t add_sense_qualifier;
 }mscd_interface_t;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC mscd_interface_t _mscd_itf;
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread mscd_interface_t _mscd_itf;
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE];
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -202,7 +202,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
 
-TU_ATTR_UNUSED TU_STATIC tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
+TU_ATTR_UNUSED static _fuzz_thread tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
 {
   { .key = SCSI_CMD_TEST_UNIT_READY              , .data = "Test Unit Ready" },
   { .key = SCSI_CMD_INQUIRY                      , .data = "Inquiry" },
@@ -217,7 +217,7 @@ TU_ATTR_UNUSED TU_STATIC tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
   { .key = SCSI_CMD_WRITE_10                     , .data = "Write10" }
 };
 
-TU_ATTR_UNUSED TU_STATIC tu_lookup_table_t const _msc_scsi_cmd_table =
+TU_ATTR_UNUSED static _fuzz_thread tu_lookup_table_t const _msc_scsi_cmd_table =
 {
   .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup),
   .items = _msc_scsi_cmd_lookup
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index 560e1768d..e2a57cb50 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -61,8 +61,11 @@ typedef struct
 #define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t)
 #define CFG_TUD_NET_PACKET_SUFFIX_LEN 0
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread 
+uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
+
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread 
+uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
 
 struct ecm_notify_struct
 {
@@ -70,7 +73,7 @@ struct ecm_notify_struct
   uint32_t downlink, uplink;
 };
 
-TU_STATIC const struct ecm_notify_struct ecm_notify_nc =
+static _fuzz_thread const struct ecm_notify_struct ecm_notify_nc =
 {
   .header = {
     .bmRequestType = 0xA1,
@@ -80,7 +83,7 @@ TU_STATIC const struct ecm_notify_struct ecm_notify_nc =
   },
 };
 
-TU_STATIC const struct ecm_notify_struct ecm_notify_csc =
+static _fuzz_thread const struct ecm_notify_struct ecm_notify_csc =
 {
   .header = {
     .bmRequestType = 0xA1,
@@ -92,7 +95,7 @@ TU_STATIC const struct ecm_notify_struct ecm_notify_csc =
 };
 
 // TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC union
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread union
 {
   uint8_t rndis_buf[120];
   struct ecm_notify_struct ecm_buf;
@@ -102,9 +105,9 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC union
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // TODO remove CFG_TUSB_MEM_SECTION
-CFG_TUSB_MEM_SECTION TU_STATIC netd_interface_t _netd_itf;
+CFG_TUSB_MEM_SECTION static _fuzz_thread netd_interface_t _netd_itf;
 
-TU_STATIC bool can_xmit;
+static _fuzz_thread bool can_xmit;
 
 void tud_network_recv_renew(void)
 {
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 236232191..b8a5c6d3a 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -130,7 +130,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC const ntb_parameters_t ntb_parameters = {
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread const ntb_parameters_t ntb_parameters = {
     .wLength                 = sizeof(ntb_parameters_t),
     .bmNtbFormatsSupported   = 0x01,
     .dwNtbInMaxSize          = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
@@ -145,11 +145,11 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC const ntb_parameters_t ntb_par
     .wNtbOutMaxDatagrams     = 0
 };
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC transmit_ntb_t transmit_ntb[2];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread transmit_ntb_t transmit_ntb[2];
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN TU_STATIC uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
 
-TU_STATIC ncm_interface_t ncm_interface;
+static _fuzz_thread ncm_interface_t ncm_interface;
 
 /*
  * Set up the NTB state in ncm_interface to be ready to add datagrams.
@@ -196,7 +196,7 @@ static void ncm_start_tx(void) {
   ncm_prepare_for_tx();
 }
 
-TU_STATIC struct ecm_notify_struct ncm_notify_connected =
+static _fuzz_thread struct ecm_notify_struct ncm_notify_connected =
 {
     .header = {
         .bmRequestType_bit = {
@@ -210,7 +210,7 @@ TU_STATIC struct ecm_notify_struct ncm_notify_connected =
     },
 };
 
-TU_STATIC struct ecm_notify_struct ncm_notify_speed_change =
+static _fuzz_thread struct ecm_notify_struct ncm_notify_speed_change =
 {
     .header = {
         .bmRequestType_bit = {
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index fd8220c1f..416cb9bb9 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -78,7 +78,7 @@
 
 #ifdef xDEBUG
 #include "uart_util.h"
-TU_STATIC char logMsg[150];
+static _fuzz_thread char logMsg[150];
 #endif
 
 // Buffer size must be an exact multiple of the max packet size for both
@@ -143,7 +143,7 @@ typedef struct
   usbtmc_capabilities_specific_t const * capabilities;
 } usbtmc_interface_state_t;
 
-CFG_TUSB_MEM_SECTION TU_STATIC usbtmc_interface_state_t usbtmc_state =
+CFG_TUSB_MEM_SECTION static _fuzz_thread usbtmc_interface_state_t usbtmc_state =
 {
     .itf_id = 0xFF,
 };
@@ -154,8 +154,8 @@ TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small");
 static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len);
 static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen);
 
-TU_STATIC uint8_t termChar;
-TU_STATIC uint8_t termCharRequested = false;
+static _fuzz_thread uint8_t termChar;
+static _fuzz_thread uint8_t termCharRequested = false;
 
 #if OSAL_MUTEX_REQUIRED
 static OSAL_MUTEX_DEF(usbtmcLockBuffer);
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index b33cbcf13..22124d193 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -59,7 +59,7 @@ typedef struct
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE];
 } vendord_interface_t;
 
-CFG_TUSB_MEM_SECTION TU_STATIC vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
+CFG_TUSB_MEM_SECTION static _fuzz_thread vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
 
 #define ITF_MEM_RESET_SIZE   offsetof(vendord_interface_t, rx_ff)
 
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index 543500f0c..2bb6afa67 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -50,8 +50,7 @@ void     tud_vendor_n_read_flush      (uint8_t itf);
 uint32_t tud_vendor_n_write           (uint8_t itf, void const* buffer, uint32_t bufsize);
 uint32_t tud_vendor_n_write_available (uint8_t itf);
 
-TU_STATIC inline
-uint32_t tud_vendor_n_write_str       (uint8_t itf, char const* str);
+static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str);
 uint32_t tud_vendor_n_flush           (uint8_t itf);
 
 //--------------------------------------------------------------------+
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 14518deac..54b45bc8e 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -125,11 +125,11 @@ typedef struct TU_ATTR_PACKED {
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION TU_STATIC videod_interface_t _videod_itf[CFG_TUD_VIDEO];
-CFG_TUSB_MEM_SECTION TU_STATIC videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
+CFG_TUSB_MEM_SECTION static _fuzz_thread videod_interface_t _videod_itf[CFG_TUD_VIDEO];
+CFG_TUSB_MEM_SECTION static _fuzz_thread videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
 
-TU_STATIC uint8_t const _cap_get     = 0x1u; /* support for GET */
-TU_STATIC uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
+static _fuzz_thread uint8_t const _cap_get     = 0x1u; /* support for GET */
+static _fuzz_thread uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
 
 /** Get interface number from the interface descriptor
  *
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 6a02959ca..c1a321a40 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -62,10 +62,10 @@
 #endif
 
 /* --------------------- Fuzzing types -------------------------------------- */
-#ifdef FUZZ
-  #define TU_STATIC __thread static
+#ifdef _FUZZ
+  #define _fuzz_thread __thread
 #else
-  #define TU_STATIC static
+  #define _fuzz_thread
 #endif
 
 // for declaration of reserved field, make use of _TU_COUNTER_
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 8587b6771..e5f718f79 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -114,7 +114,7 @@ typedef struct
 
 static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
 {
-  TU_STATIC char not_found[11];
+  static _fuzz_thread char not_found[11];
 
   for(uint16_t i=0; i<p_table->count; i++)
   {
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 56f782ca3..c4e131134 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -529,13 +529,13 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpo
 #if CFG_TUSB_DEBUG
 TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir)
 {
-  TU_STATIC const char *str[] = {"out", "in"};
+  static _fuzz_thread const char *str[] = {"out", "in"};
   return str[dir];
 }
 
 TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t)
 {
-  TU_STATIC const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
+  static _fuzz_thread const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
   return str[t];
 }
 #endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 72fa2bd4c..3176239e7 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -76,7 +76,7 @@ typedef struct
 
 }usbd_device_t;
 
-TU_STATIC usbd_device_t _usbd_dev;
+static _fuzz_thread usbd_device_t _usbd_dev;
 
 //--------------------------------------------------------------------+
 // Class Driver
@@ -88,7 +88,7 @@ TU_STATIC usbd_device_t _usbd_dev;
 #endif
 
 // Built-in class drivers
-TU_STATIC usbd_class_driver_t const _usbd_driver[] =
+static _fuzz_thread usbd_class_driver_t const _usbd_driver[] =
 {
   #if CFG_TUD_CDC
   {
@@ -238,8 +238,8 @@ TU_STATIC usbd_class_driver_t const _usbd_driver[] =
 enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) };
 
 // Additional class drivers implemented by application
-TU_STATIC usbd_class_driver_t const * _app_driver = NULL;
-TU_STATIC uint8_t _app_driver_count = 0;
+static _fuzz_thread usbd_class_driver_t const * _app_driver = NULL;
+static _fuzz_thread uint8_t _app_driver_count = 0;
 
 // virtually joins built-in and application drivers together.
 // Application is positioned first to allow overwriting built-in ones.
@@ -265,17 +265,17 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 //--------------------------------------------------------------------+
 
 enum { RHPORT_INVALID = 0xFFu };
-TU_STATIC uint8_t _usbd_rhport = RHPORT_INVALID;
+static _fuzz_thread uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // usbd_int_set() is used as mutex in OS NONE config
 OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
-TU_STATIC osal_queue_t _usbd_q;
+static _fuzz_thread osal_queue_t _usbd_q;
 
 // Mutex for claiming endpoint
 #if OSAL_MUTEX_REQUIRED
-  TU_STATIC osal_mutex_def_t _ubsd_mutexdef;
-  TU_STATIC osal_mutex_t _usbd_mutex;
+  static _fuzz_thread osal_mutex_def_t _ubsd_mutexdef;
+  static _fuzz_thread osal_mutex_t _usbd_mutex;
 #else
   #define _usbd_mutex   NULL
 #endif
@@ -299,7 +299,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event,
 // Debug
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
-TU_STATIC char const* const _usbd_event_str[DCD_EVENT_COUNT] =
+static _fuzz_thread char const* const _usbd_event_str[DCD_EVENT_COUNT] =
 {
   "Invalid"        ,
   "Bus Reset"      ,
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index c3ff7459d..8b071d9c6 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -53,10 +53,10 @@ typedef struct
   usbd_control_xfer_cb_t complete_cb;
 } usbd_control_xfer_t;
 
-TU_STATIC usbd_control_xfer_t _ctrl_xfer;
+static _fuzz_thread usbd_control_xfer_t _ctrl_xfer;
 
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
-TU_STATIC uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
+static _fuzz_thread uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
 
 //--------------------------------------------------------------------+
 // Application API
diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk
index 5e8658ad0..e7c5518e7 100644
--- a/test/fuzz/make.mk
+++ b/test/fuzz/make.mk
@@ -79,7 +79,7 @@ CFLAGS += \
 	-Wno-error=unreachable-code \
   -DOPT_MCU_FUZZ=1 \
   -DCFG_TUSB_MCU=OPT_MCU_FUZZ \
-  -DFUZZ
+  -D_FUZZ
 
 CXXFLAGS += \
   -xc++ \

From bcf5e5f72918a7f5ee991f8d1cc3d4f9a3b2b306 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Feb 2023 12:10:22 +0700
Subject: [PATCH 1481/2085] missing some files

---
 test/fuzz/dcd_fuzz.cc                       | 2 +-
 test/fuzz/device/msc/src/usb_descriptors.cc | 4 ++--
 test/fuzz/device/net/src/usb_descriptors.cc | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc
index 04b5ce6d7..294977269 100644
--- a/test/fuzz/dcd_fuzz.cc
+++ b/test/fuzz/dcd_fuzz.cc
@@ -39,7 +39,7 @@ struct State {
   uint8_t address;
 };
 
-TU_STATIC State state = {false, 0, 0};
+static _fuzz_thread State state = {false, 0, 0};
 
 //--------------------------------------------------------------------+
 // Controller API
diff --git a/test/fuzz/device/msc/src/usb_descriptors.cc b/test/fuzz/device/msc/src/usb_descriptors.cc
index 91db232ac..8f4be9655 100644
--- a/test/fuzz/device/msc/src/usb_descriptors.cc
+++ b/test/fuzz/device/msc/src/usb_descriptors.cc
@@ -44,7 +44,7 @@
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
 uint8_t const *tud_descriptor_device_cb(void) {
-  TU_STATIC tusb_desc_device_t const desc_device = {
+  static _fuzz_thread tusb_desc_device_t const desc_device = {
       .bLength = sizeof(tusb_desc_device_t),
       .bDescriptorType = TUSB_DESC_DEVICE,
       .bcdUSB = USB_BCD,
@@ -184,7 +184,7 @@ char const *string_desc_arr[] = {
 
 };
 
-TU_STATIC uint16_t _desc_str[32];
+static _fuzz_thread uint16_t _desc_str[32];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long
diff --git a/test/fuzz/device/net/src/usb_descriptors.cc b/test/fuzz/device/net/src/usb_descriptors.cc
index 0223ed298..903d49271 100644
--- a/test/fuzz/device/net/src/usb_descriptors.cc
+++ b/test/fuzz/device/net/src/usb_descriptors.cc
@@ -45,7 +45,7 @@
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
 uint8_t const *tud_descriptor_device_cb(void) {
-  TU_STATIC tusb_desc_device_t const desc_device = {
+  static _fuzz_thread tusb_desc_device_t const desc_device = {
       .bLength = sizeof(tusb_desc_device_t),
       .bDescriptorType = TUSB_DESC_DEVICE,
       .bcdUSB = USB_BCD,
@@ -189,7 +189,7 @@ char const *string_desc_arr[] = {
     "TinyUSB CDC",              // 4: CDC Interface
 };
 
-TU_STATIC uint16_t _desc_str[32];
+static _fuzz_thread uint16_t _desc_str[32];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long

From 78a014ef187666da82c348b10958503c4c1d0e2b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Feb 2023 15:13:27 +0700
Subject: [PATCH 1482/2085] move check LIB_PICO_STDIO_UART to board.h

---
 hw/bsp/rp2040/board.h  | 3 ++-
 hw/bsp/rp2040/family.c | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index f25f80e09..e7eab088e 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -40,7 +40,8 @@
 #define BUTTON_BOOTSEL
 #define BUTTON_STATE_ACTIVE   0
 
-#if defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) && defined(PICO_DEFAULT_UART)
+#if defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) && \
+    defined(PICO_DEFAULT_UART) && defined(LIB_PICO_STDIO_UART)
 #define UART_DEV              PICO_DEFAULT_UART
 #define UART_TX_PIN           PICO_DEFAULT_UART_TX_PIN
 #define UART_RX_PIN           PICO_DEFAULT_UART_RX_PIN
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 75328027b..8a426d655 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -115,7 +115,7 @@ void stdio_rtt_init(void)
 
 #endif
 
-#if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
+#if defined(UART_DEV)
 static uart_inst_t *uart_inst;
 #endif
 
@@ -148,7 +148,7 @@ void board_init(void)
 #ifndef BUTTON_BOOTSEL
 #endif
 
-#if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
+#if defined(UART_DEV)
   bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_TX_PIN, GPIO_FUNC_UART));
   uart_inst = uart_get_instance(UART_DEV);
   stdio_uart_init_full(uart_inst, CFG_BOARD_UART_BAUDRATE, UART_TX_PIN, UART_RX_PIN);
@@ -191,7 +191,7 @@ uint32_t board_button_read(void)
 
 int board_uart_read(uint8_t* buf, int len)
 {
-#if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
+#if defined(UART_DEV)
   int count = 0;
   while ( (count < len) && uart_is_readable(uart_inst) )
   {
@@ -207,7 +207,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-#if defined(UART_DEV) && defined(LIB_PICO_STDIO_UART)
+#if defined(UART_DEV)
   char const* bufch = (char const*) buf;
   for(int i=0;i<len;i++) {
     uart_putc(uart_inst, bufch[i]);

From c01aee6c1a01884d84b399c005dcfed6e67a908c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Feb 2023 15:14:56 +0700
Subject: [PATCH 1483/2085] revert some changes

---
 hw/bsp/rp2040/family.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 8a426d655..f9fa88ac4 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -115,7 +115,7 @@ void stdio_rtt_init(void)
 
 #endif
 
-#if defined(UART_DEV)
+#ifdef UART_DEV
 static uart_inst_t *uart_inst;
 #endif
 
@@ -148,7 +148,7 @@ void board_init(void)
 #ifndef BUTTON_BOOTSEL
 #endif
 
-#if defined(UART_DEV)
+#ifdef UART_DEV
   bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_TX_PIN, GPIO_FUNC_UART));
   uart_inst = uart_get_instance(UART_DEV);
   stdio_uart_init_full(uart_inst, CFG_BOARD_UART_BAUDRATE, UART_TX_PIN, UART_RX_PIN);
@@ -191,7 +191,7 @@ uint32_t board_button_read(void)
 
 int board_uart_read(uint8_t* buf, int len)
 {
-#if defined(UART_DEV)
+#ifdef UART_DEV
   int count = 0;
   while ( (count < len) && uart_is_readable(uart_inst) )
   {
@@ -207,7 +207,7 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
-#if defined(UART_DEV)
+#ifdef UART_DEV
   char const* bufch = (char const*) buf;
   for(int i=0;i<len;i++) {
     uart_putc(uart_inst, bufch[i]);

From 4c846af53e993d635e6fff7e2611a554b55fc441 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Feb 2023 16:18:45 +0700
Subject: [PATCH 1484/2085] rename OHCI_RHPORTS to TUP_OHCI_RHPORTS

---
 src/common/tusb_mcu.h    |  2 +-
 src/portable/ohci/ohci.c | 17 ++++++++---------
 src/portable/ohci/ohci.h |  6 +++---
 3 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index ee2b896ac..a599c4fe9 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -55,7 +55,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   #define TUP_DCD_ENDPOINT_MAX    16
   #define TUP_USBIP_OHCI
-  #define OHCI_RHPORTS            2
+  #define TUP_OHCI_RHPORTS            2
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 76f97844c..792ef65ff 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -28,8 +28,8 @@
 
 #if CFG_TUH_ENABLED && defined(TUP_USBIP_OHCI)
 
-#ifndef OHCI_RHPORTS
-#error  OHCI is enabled, but OHCI_RHPORTS is not defined.
+#ifndef TUP_OHCI_RHPORTS
+#error  OHCI is enabled, but TUP_OHCI_RHPORTS is not defined.
 #endif
 
 //--------------------------------------------------------------------+
@@ -393,21 +393,20 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
 
     if (ed->dev_addr == dev_addr)
     {
-      //Prevent Host Controller from processing this ED while we remove it
+      // Prevent Host Controller from processing this ED while we remove it
       ed->skip = 1;
 
-      // unlink ed
+      // unlink ed, will also move up p_prev
       p_prev->next = ed->next;
 
       // point the removed ED's next pointer to list head to make sure HC can always safely move away from this ED
       ed->next = (uint32_t) _phys_addr(p_head);
       ed->used = 0;
       ed->skip = 0;
-      continue;
+    }else
+    {
+      p_prev = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
     }
-
-    // check next valid since we could remove it
-    if (p_prev->next) p_prev = (ohci_ed_t*) _virt_addr((void *)p_prev->next);
   }
 }
 
@@ -665,7 +664,7 @@ void hcd_int_handler(uint8_t hostid)
   //------------- RootHub status -------------//
   if ( int_status & OHCI_INT_RHPORT_STATUS_CHANGE_MASK )
   {
-    for (int i = 0; i < OHCI_RHPORTS; i++)
+    for (int i = 0; i < TUP_OHCI_RHPORTS; i++)
     {
       uint32_t const rhport_status = OHCI_REG->rhport_status[i] & RHPORT_ALL_CHANGE_MASK;
       if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK )
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index b7706b636..38c258e80 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -267,7 +267,7 @@ typedef volatile struct
   };
 
   union {
-    uint32_t rhport_status[OHCI_RHPORTS];
+    uint32_t rhport_status[TUP_OHCI_RHPORTS];
     struct {
       uint32_t current_connect_status             : 1;
       uint32_t port_enable_status                 : 1;
@@ -284,11 +284,11 @@ typedef volatile struct
       uint32_t port_over_current_indicator_change : 1;
       uint32_t port_reset_status_change           : 1;
       uint32_t TU_RESERVED                        : 11;
-    }rhport_status_bit[OHCI_RHPORTS];
+    }rhport_status_bit[TUP_OHCI_RHPORTS];
   };
 }ohci_registers_t;
 
-TU_VERIFY_STATIC( sizeof(ohci_registers_t) == (0x54 + (4 * OHCI_RHPORTS)), "size is not correct");
+TU_VERIFY_STATIC( sizeof(ohci_registers_t) == (0x54 + (4 * TUP_OHCI_RHPORTS)), "size is not correct");
 
 #ifdef __cplusplus
  }

From 498989ee009c388a770e7a312ae04d0a51ba745a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Feb 2023 16:23:40 +0700
Subject: [PATCH 1485/2085] use tu_static instead of static _fuzz_thread

---
 src/class/cdc/cdc_device.c                  |  2 +-
 src/class/dfu/dfu_device.c                  | 14 +++++++-------
 src/class/hid/hid_device.c                  |  2 +-
 src/class/msc/msc_device.c                  |  8 ++++----
 src/class/net/ecm_rndis_device.c            | 14 +++++++-------
 src/class/net/ncm_device.c                  | 12 ++++++------
 src/class/usbtmc/usbtmc_device.c            |  8 ++++----
 src/class/vendor/vendor_device.c            |  2 +-
 src/class/video/video_device.c              |  8 ++++----
 src/common/tusb_compiler.h                  |  4 ++--
 src/common/tusb_debug.h                     |  2 +-
 src/common/tusb_types.h                     |  4 ++--
 src/device/usbd.c                           | 18 +++++++++---------
 src/device/usbd_control.c                   |  4 ++--
 test/fuzz/dcd_fuzz.cc                       |  2 +-
 test/fuzz/device/msc/src/usb_descriptors.cc |  4 ++--
 test/fuzz/device/net/src/usb_descriptors.cc |  4 ++--
 17 files changed, 56 insertions(+), 56 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 59ed2a74c..f372fe462 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -76,7 +76,7 @@ typedef struct
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION static _fuzz_thread cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
+CFG_TUSB_MEM_SECTION tu_static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
 
 static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
 {
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 9e7b8b5b1..464c4bd6b 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -56,7 +56,7 @@ typedef struct
 } dfu_state_ctx_t;
 
 // Only a single dfu state is allowed
-CFG_TUSB_MEM_SECTION static _fuzz_thread dfu_state_ctx_t _dfu_ctx;
+CFG_TUSB_MEM_SECTION tu_static dfu_state_ctx_t _dfu_ctx;
 
 static void reset_state(void)
 {
@@ -74,7 +74,7 @@ static bool process_manifest_get_status(uint8_t rhport, uint8_t stage, tusb_cont
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
 
-static _fuzz_thread tu_lookup_entry_t const _dfu_request_lookup[] =
+tu_static tu_lookup_entry_t const _dfu_request_lookup[] =
 {
   { .key = DFU_REQUEST_DETACH         , .data = "DETACH"    },
   { .key = DFU_REQUEST_DNLOAD         , .data = "DNLOAD"    },
@@ -85,13 +85,13 @@ static _fuzz_thread tu_lookup_entry_t const _dfu_request_lookup[] =
   { .key = DFU_REQUEST_ABORT          , .data = "ABORT"     },
 };
 
-static _fuzz_thread tu_lookup_table_t const _dfu_request_table =
+tu_static tu_lookup_table_t const _dfu_request_table =
 {
   .count = TU_ARRAY_SIZE(_dfu_request_lookup),
   .items = _dfu_request_lookup
 };
 
-static _fuzz_thread tu_lookup_entry_t const _dfu_state_lookup[] =
+tu_static tu_lookup_entry_t const _dfu_state_lookup[] =
 {
   { .key = APP_IDLE                   , .data = "APP_IDLE"                },
   { .key = APP_DETACH                 , .data = "APP_DETACH"              },
@@ -106,13 +106,13 @@ static _fuzz_thread tu_lookup_entry_t const _dfu_state_lookup[] =
   { .key = DFU_ERROR                  , .data = "ERROR"               },
 };
 
-static _fuzz_thread tu_lookup_table_t const _dfu_state_table =
+tu_static tu_lookup_table_t const _dfu_state_table =
 {
   .count = TU_ARRAY_SIZE(_dfu_state_lookup),
   .items = _dfu_state_lookup
 };
 
-static _fuzz_thread tu_lookup_entry_t const _dfu_status_lookup[] =
+tu_static tu_lookup_entry_t const _dfu_status_lookup[] =
 {
   { .key = DFU_STATUS_OK               , .data = "OK"              },
   { .key = DFU_STATUS_ERR_TARGET       , .data = "errTARGET"       },
@@ -132,7 +132,7 @@ static _fuzz_thread tu_lookup_entry_t const _dfu_status_lookup[] =
   { .key = DFU_STATUS_ERR_STALLEDPKT   , .data = "errSTALLEDPKT"   },
 };
 
-static _fuzz_thread tu_lookup_table_t const _dfu_status_table =
+tu_static tu_lookup_table_t const _dfu_status_table =
 {
   .count = TU_ARRAY_SIZE(_dfu_status_lookup),
   .items = _dfu_status_lookup
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 6fae5862d..ef44585f9 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -58,7 +58,7 @@ typedef struct
   tusb_hid_descriptor_hid_t const * hid_descriptor;
 } hidd_interface_t;
 
-CFG_TUSB_MEM_SECTION static _fuzz_thread hidd_interface_t _hidd_itf[CFG_TUD_HID];
+CFG_TUSB_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID];
 
 /*------------- Helpers -------------*/
 static inline uint8_t get_index_by_itfnum(uint8_t itf_num)
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index e77342777..d3c8124df 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -71,8 +71,8 @@ typedef struct
   uint8_t add_sense_qualifier;
 }mscd_interface_t;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread mscd_interface_t _mscd_itf;
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static mscd_interface_t _mscd_itf;
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE];
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -202,7 +202,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
 
-TU_ATTR_UNUSED static _fuzz_thread tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
+TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] =
 {
   { .key = SCSI_CMD_TEST_UNIT_READY              , .data = "Test Unit Ready" },
   { .key = SCSI_CMD_INQUIRY                      , .data = "Inquiry" },
@@ -217,7 +217,7 @@ TU_ATTR_UNUSED static _fuzz_thread tu_lookup_entry_t const _msc_scsi_cmd_lookup[
   { .key = SCSI_CMD_WRITE_10                     , .data = "Write10" }
 };
 
-TU_ATTR_UNUSED static _fuzz_thread tu_lookup_table_t const _msc_scsi_cmd_table =
+TU_ATTR_UNUSED tu_static tu_lookup_table_t const _msc_scsi_cmd_table =
 {
   .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup),
   .items = _msc_scsi_cmd_lookup
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index e2a57cb50..a072bfd79 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -61,10 +61,10 @@ typedef struct
 #define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t)
 #define CFG_TUD_NET_PACKET_SUFFIX_LEN 0
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread 
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static
 uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread 
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static
 uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
 
 struct ecm_notify_struct
@@ -73,7 +73,7 @@ struct ecm_notify_struct
   uint32_t downlink, uplink;
 };
 
-static _fuzz_thread const struct ecm_notify_struct ecm_notify_nc =
+tu_static const struct ecm_notify_struct ecm_notify_nc =
 {
   .header = {
     .bmRequestType = 0xA1,
@@ -83,7 +83,7 @@ static _fuzz_thread const struct ecm_notify_struct ecm_notify_nc =
   },
 };
 
-static _fuzz_thread const struct ecm_notify_struct ecm_notify_csc =
+tu_static const struct ecm_notify_struct ecm_notify_csc =
 {
   .header = {
     .bmRequestType = 0xA1,
@@ -95,7 +95,7 @@ static _fuzz_thread const struct ecm_notify_struct ecm_notify_csc =
 };
 
 // TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread union
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static union
 {
   uint8_t rndis_buf[120];
   struct ecm_notify_struct ecm_buf;
@@ -105,9 +105,9 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread union
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // TODO remove CFG_TUSB_MEM_SECTION
-CFG_TUSB_MEM_SECTION static _fuzz_thread netd_interface_t _netd_itf;
+CFG_TUSB_MEM_SECTION tu_static netd_interface_t _netd_itf;
 
-static _fuzz_thread bool can_xmit;
+tu_static bool can_xmit;
 
 void tud_network_recv_renew(void)
 {
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index b8a5c6d3a..aa13c9535 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -130,7 +130,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread const ntb_parameters_t ntb_parameters = {
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = {
     .wLength                 = sizeof(ntb_parameters_t),
     .bmNtbFormatsSupported   = 0x01,
     .dwNtbInMaxSize          = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
@@ -145,11 +145,11 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread const ntb_parameters
     .wNtbOutMaxDatagrams     = 0
 };
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread transmit_ntb_t transmit_ntb[2];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static transmit_ntb_t transmit_ntb[2];
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static _fuzz_thread uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
 
-static _fuzz_thread ncm_interface_t ncm_interface;
+tu_static ncm_interface_t ncm_interface;
 
 /*
  * Set up the NTB state in ncm_interface to be ready to add datagrams.
@@ -196,7 +196,7 @@ static void ncm_start_tx(void) {
   ncm_prepare_for_tx();
 }
 
-static _fuzz_thread struct ecm_notify_struct ncm_notify_connected =
+tu_static struct ecm_notify_struct ncm_notify_connected =
 {
     .header = {
         .bmRequestType_bit = {
@@ -210,7 +210,7 @@ static _fuzz_thread struct ecm_notify_struct ncm_notify_connected =
     },
 };
 
-static _fuzz_thread struct ecm_notify_struct ncm_notify_speed_change =
+tu_static struct ecm_notify_struct ncm_notify_speed_change =
 {
     .header = {
         .bmRequestType_bit = {
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 416cb9bb9..a4e6eaeb3 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -78,7 +78,7 @@
 
 #ifdef xDEBUG
 #include "uart_util.h"
-static _fuzz_thread char logMsg[150];
+tu_static char logMsg[150];
 #endif
 
 // Buffer size must be an exact multiple of the max packet size for both
@@ -143,7 +143,7 @@ typedef struct
   usbtmc_capabilities_specific_t const * capabilities;
 } usbtmc_interface_state_t;
 
-CFG_TUSB_MEM_SECTION static _fuzz_thread usbtmc_interface_state_t usbtmc_state =
+CFG_TUSB_MEM_SECTION tu_static usbtmc_interface_state_t usbtmc_state =
 {
     .itf_id = 0xFF,
 };
@@ -154,8 +154,8 @@ TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small");
 static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len);
 static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen);
 
-static _fuzz_thread uint8_t termChar;
-static _fuzz_thread uint8_t termCharRequested = false;
+tu_static uint8_t termChar;
+tu_static uint8_t termCharRequested = false;
 
 #if OSAL_MUTEX_REQUIRED
 static OSAL_MUTEX_DEF(usbtmcLockBuffer);
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 22124d193..d07bd75ec 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -59,7 +59,7 @@ typedef struct
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE];
 } vendord_interface_t;
 
-CFG_TUSB_MEM_SECTION static _fuzz_thread vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
+CFG_TUSB_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
 
 #define ITF_MEM_RESET_SIZE   offsetof(vendord_interface_t, rx_ff)
 
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index ecee73d51..02a490aee 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -125,11 +125,11 @@ typedef struct TU_ATTR_PACKED {
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION static _fuzz_thread videod_interface_t _videod_itf[CFG_TUD_VIDEO];
-CFG_TUSB_MEM_SECTION static _fuzz_thread videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
+CFG_TUSB_MEM_SECTION tu_static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
+CFG_TUSB_MEM_SECTION tu_static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
 
-static _fuzz_thread uint8_t const _cap_get     = 0x1u; /* support for GET */
-static _fuzz_thread uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
+tu_static uint8_t const _cap_get     = 0x1u; /* support for GET */
+tu_static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
 
 /** Get interface number from the interface descriptor
  *
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 3eb6b41f7..30478ba6d 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -63,9 +63,9 @@
 
 /* --------------------- Fuzzing types -------------------------------------- */
 #ifdef _FUZZ
-  #define _fuzz_thread __thread
+  #define tu_static static __thread
 #else
-  #define _fuzz_thread
+  #define tu_static static
 #endif
 
 // for declaration of reserved field, make use of _TU_COUNTER_
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index e5f718f79..82f682043 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -114,7 +114,7 @@ typedef struct
 
 static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
 {
-  static _fuzz_thread char not_found[11];
+  tu_static char not_found[11];
 
   for(uint16_t i=0; i<p_table->count; i++)
   {
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 14d4365a0..7266a525e 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -529,13 +529,13 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_edpt_packet_size(tusb_desc_endpo
 #if CFG_TUSB_DEBUG
 TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_dir_str(tusb_dir_t dir)
 {
-  static _fuzz_thread const char *str[] = {"out", "in"};
+  tu_static const char *str[] = {"out", "in"};
   return str[dir];
 }
 
 TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_t t)
 {
-  static _fuzz_thread const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
+  tu_static const char *str[] = {"control", "isochronous", "bulk", "interrupt"};
   return str[t];
 }
 #endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 3176239e7..384daccb8 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -76,7 +76,7 @@ typedef struct
 
 }usbd_device_t;
 
-static _fuzz_thread usbd_device_t _usbd_dev;
+tu_static usbd_device_t _usbd_dev;
 
 //--------------------------------------------------------------------+
 // Class Driver
@@ -88,7 +88,7 @@ static _fuzz_thread usbd_device_t _usbd_dev;
 #endif
 
 // Built-in class drivers
-static _fuzz_thread usbd_class_driver_t const _usbd_driver[] =
+tu_static usbd_class_driver_t const _usbd_driver[] =
 {
   #if CFG_TUD_CDC
   {
@@ -238,8 +238,8 @@ static _fuzz_thread usbd_class_driver_t const _usbd_driver[] =
 enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) };
 
 // Additional class drivers implemented by application
-static _fuzz_thread usbd_class_driver_t const * _app_driver = NULL;
-static _fuzz_thread uint8_t _app_driver_count = 0;
+tu_static usbd_class_driver_t const * _app_driver = NULL;
+tu_static uint8_t _app_driver_count = 0;
 
 // virtually joins built-in and application drivers together.
 // Application is positioned first to allow overwriting built-in ones.
@@ -265,17 +265,17 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 //--------------------------------------------------------------------+
 
 enum { RHPORT_INVALID = 0xFFu };
-static _fuzz_thread uint8_t _usbd_rhport = RHPORT_INVALID;
+tu_static uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // usbd_int_set() is used as mutex in OS NONE config
 OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
-static _fuzz_thread osal_queue_t _usbd_q;
+tu_static osal_queue_t _usbd_q;
 
 // Mutex for claiming endpoint
 #if OSAL_MUTEX_REQUIRED
-  static _fuzz_thread osal_mutex_def_t _ubsd_mutexdef;
-  static _fuzz_thread osal_mutex_t _usbd_mutex;
+  tu_static osal_mutex_def_t _ubsd_mutexdef;
+  tu_static osal_mutex_t _usbd_mutex;
 #else
   #define _usbd_mutex   NULL
 #endif
@@ -299,7 +299,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event,
 // Debug
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= 2
-static _fuzz_thread char const* const _usbd_event_str[DCD_EVENT_COUNT] =
+tu_static char const* const _usbd_event_str[DCD_EVENT_COUNT] =
 {
   "Invalid"        ,
   "Bus Reset"      ,
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 8b071d9c6..e709658b9 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -53,10 +53,10 @@ typedef struct
   usbd_control_xfer_cb_t complete_cb;
 } usbd_control_xfer_t;
 
-static _fuzz_thread usbd_control_xfer_t _ctrl_xfer;
+tu_static usbd_control_xfer_t _ctrl_xfer;
 
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
-static _fuzz_thread uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
+tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
 
 //--------------------------------------------------------------------+
 // Application API
diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc
index 294977269..6403015dd 100644
--- a/test/fuzz/dcd_fuzz.cc
+++ b/test/fuzz/dcd_fuzz.cc
@@ -39,7 +39,7 @@ struct State {
   uint8_t address;
 };
 
-static _fuzz_thread State state = {false, 0, 0};
+tu_static State state = {false, 0, 0};
 
 //--------------------------------------------------------------------+
 // Controller API
diff --git a/test/fuzz/device/msc/src/usb_descriptors.cc b/test/fuzz/device/msc/src/usb_descriptors.cc
index 8f4be9655..efe4d0a3c 100644
--- a/test/fuzz/device/msc/src/usb_descriptors.cc
+++ b/test/fuzz/device/msc/src/usb_descriptors.cc
@@ -44,7 +44,7 @@
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
 uint8_t const *tud_descriptor_device_cb(void) {
-  static _fuzz_thread tusb_desc_device_t const desc_device = {
+  tu_static tusb_desc_device_t const desc_device = {
       .bLength = sizeof(tusb_desc_device_t),
       .bDescriptorType = TUSB_DESC_DEVICE,
       .bcdUSB = USB_BCD,
@@ -184,7 +184,7 @@ char const *string_desc_arr[] = {
 
 };
 
-static _fuzz_thread uint16_t _desc_str[32];
+tu_static uint16_t _desc_str[32];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long
diff --git a/test/fuzz/device/net/src/usb_descriptors.cc b/test/fuzz/device/net/src/usb_descriptors.cc
index 903d49271..5597d49d5 100644
--- a/test/fuzz/device/net/src/usb_descriptors.cc
+++ b/test/fuzz/device/net/src/usb_descriptors.cc
@@ -45,7 +45,7 @@
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
 uint8_t const *tud_descriptor_device_cb(void) {
-  static _fuzz_thread tusb_desc_device_t const desc_device = {
+  tu_static tusb_desc_device_t const desc_device = {
       .bLength = sizeof(tusb_desc_device_t),
       .bDescriptorType = TUSB_DESC_DEVICE,
       .bcdUSB = USB_BCD,
@@ -189,7 +189,7 @@ char const *string_desc_arr[] = {
     "TinyUSB CDC",              // 4: CDC Interface
 };
 
-static _fuzz_thread uint16_t _desc_str[32];
+tu_static uint16_t _desc_str[32];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long

From 302b9562dc6963fcb3f85571cb515f322f6d2226 Mon Sep 17 00:00:00 2001
From: mikee47 <mike@silyhouse.net>
Date: Wed, 22 Feb 2023 09:58:30 +0000
Subject: [PATCH 1486/2085] MIDI_CIN_NOTE_ON definition transposed with
 MIDI_CIN_NOTE_OFF

---
 src/class/midi/midi.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/midi/midi.h b/src/class/midi/midi.h
index 74dc41749..57875b1e4 100644
--- a/src/class/midi/midi.h
+++ b/src/class/midi/midi.h
@@ -71,8 +71,8 @@ typedef enum
   MIDI_CIN_SYSEX_END_1BYTE   = 5, // SysEx ends with 1 data, or 1 byte system common message
   MIDI_CIN_SYSEX_END_2BYTE   = 6, // SysEx ends with 2 data
   MIDI_CIN_SYSEX_END_3BYTE   = 7, // SysEx ends with 3 data
-  MIDI_CIN_NOTE_ON           = 8,
-  MIDI_CIN_NOTE_OFF          = 9,
+  MIDI_CIN_NOTE_OFF          = 8,
+  MIDI_CIN_NOTE_ON           = 9,
   MIDI_CIN_POLY_KEYPRESS     = 10,
   MIDI_CIN_CONTROL_CHANGE    = 11,
   MIDI_CIN_PROGRAM_CHANGE    = 12,

From 1466afafeb927621f9cbb6efd2a0d7e4b6cf8d41 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Feb 2023 22:14:50 +0700
Subject: [PATCH 1487/2085] move and add optional
 tusb_app_virt_to_phys/tusb_app_phys_to_virt

also add place holder for tusb_app_dcache_flush() and
tusb_app_dcache_invalidate()
---
 src/common/tusb_common.h | 15 +++++++++++++++
 src/common/tusb_mcu.h    |  4 ++--
 src/host/hcd.h           |  2 +-
 src/osal/osal_none.h     |  4 ++++
 src/portable/ohci/ohci.c | 21 +++++++++++++--------
 src/portable/ohci/ohci.h |  4 +++-
 6 files changed, 38 insertions(+), 12 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index b1ee40a1a..270339cca 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -75,6 +75,21 @@
 
 #include "tusb_timeout.h" // TODO remove
 
+//--------------------------------------------------------------------+
+// Optional API implemented by application if needed
+// TODO move to a more ovious place/file
+//--------------------------------------------------------------------+
+
+// flush data cache
+TU_ATTR_WEAK extern void tusb_app_dcache_flush(uintptr_t addr, uint32_t data_size);
+
+// invalidate data cache
+TU_ATTR_WEAK extern void tusb_app_dcache_invalidate(uintptr_t addr, uint32_t data_size);
+
+// Optional physical <-> virtual address translation
+TU_ATTR_WEAK extern void* tusb_app_virt_to_phys(void *virt_addr);
+TU_ATTR_WEAK extern void* tusb_app_phys_to_virt(void *phys_addr);
+
 //--------------------------------------------------------------------+
 // Internal Inline Functions
 //--------------------------------------------------------------------+
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index a599c4fe9..e7d4e2c32 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -28,8 +28,8 @@
 #define TUSB_MCU_H_
 
 //--------------------------------------------------------------------+
-// Port Specific
-// TUP stand for TinyUSB Port (can be renamed)
+// Port/Platform Specific
+// TUP stand for TinyUSB Port/Platform (can be renamed)
 //--------------------------------------------------------------------+
 
 //------------- Unaligned Memory Access -------------//
diff --git a/src/host/hcd.h b/src/host/hcd.h
index deebc59d4..a400626e4 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -106,7 +106,7 @@ typedef struct
 // Controller API
 //--------------------------------------------------------------------+
 
-// optional hcd configuration, called by tuh_config()
+// optional hcd configuration, called by tuh_configure()
 bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_ATTR_WEAK;
 
 // Initialize controller to host mode
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 1ad130557..2e2b3c7ce 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -35,6 +35,10 @@
 // TASK API
 //--------------------------------------------------------------------+
 
+#if CFG_TUH_ENABLED
+// currently only needed/available in host mode
+void osal_task_delay(uint32_t msec);
+#endif
 
 //--------------------------------------------------------------------+
 // Binary Semaphore API
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 792ef65ff..339f8e896 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -162,18 +162,16 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr);
 // USBH-HCD API
 //--------------------------------------------------------------------+
 
-//If your system requires separation of virtual and physical memory, implement
-//tuh_get_phys_addr and tuh_get_virt_addr in your application.
-TU_ATTR_WEAK void *tuh_get_phys_addr(void *virtual_address);
-TU_ATTR_WEAK void *tuh_get_virt_addr(void *physical_address);
-TU_ATTR_ALWAYS_INLINE static void *_phys_addr(void *virtual_address)
+// If your system requires separation of virtual and physical memory, implement
+// tusb_app_virt_to_phys and tusb_app_virt_to_phys in your application.
+TU_ATTR_ALWAYS_INLINE static inline void *_phys_addr(void *virtual_address)
 {
-  if (tuh_get_phys_addr) return tuh_get_phys_addr(virtual_address);
+  if (tusb_app_virt_to_phys) return tusb_app_virt_to_phys(virtual_address);
   return virtual_address;
 }
-TU_ATTR_ALWAYS_INLINE static void *_virt_addr(void *physical_address)
+TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address)
 {
-  if (tuh_get_virt_addr) return tuh_get_virt_addr(physical_address);
+  if (tusb_app_phys_to_virt) return tusb_app_phys_to_virt(physical_address);
   return physical_address;
 }
 
@@ -206,7 +204,13 @@ bool hcd_init(uint8_t rhport)
   {
     //Wait 20 ms. (Ref Usb spec 7.1.7.7)
     OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_RESUME;
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+    // os_none implement task delay using usb frame counter which is not started yet
+    // therefore cause infinite delay.
+    // TODO find a way to delay in case of os none e.g __nop
     osal_task_delay(20);
+#endif
   }
 
   // reset controller
@@ -233,6 +237,7 @@ bool hcd_init(uint8_t rhport)
 
   OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power)
   OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports
+
   osal_task_delay(OHCI_REG->rh_descriptorA_bit.power_on_to_good_time * 2); // Wait POTG after power up
 
   return true;
diff --git a/src/portable/ohci/ohci.h b/src/portable/ohci/ohci.h
index 38c258e80..2081ffabb 100644
--- a/src/portable/ohci/ohci.h
+++ b/src/portable/ohci/ohci.h
@@ -58,7 +58,9 @@ typedef struct {
 
 TU_VERIFY_STATIC( sizeof(ohci_hcca_t) == 256, "size is not correct" );
 
-typedef struct {
+// common link item for gtd and itd for list travel
+// use as pointer only
+typedef struct TU_ATTR_ALIGNED(16) {
   uint32_t reserved[2];
   volatile uint32_t next;
   uint32_t reserved2;

From 4caa6063b092de2a9efadb6a4ac247543662731f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Feb 2023 22:17:45 +0700
Subject: [PATCH 1488/2085] white space

---
 src/common/tusb_mcu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index e7d4e2c32..1f27afa4e 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -55,7 +55,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   #define TUP_DCD_ENDPOINT_MAX    16
   #define TUP_USBIP_OHCI
-  #define TUP_OHCI_RHPORTS            2
+  #define TUP_OHCI_RHPORTS        2
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   // TODO USB0 has 6, USB1 has 4

From eca96c635da52ab516e3dda47348ef8977ffd8ad Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Feb 2023 22:28:22 +0700
Subject: [PATCH 1489/2085] comment out osal_task_delay if using os none

---
 src/portable/ohci/ohci.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 339f8e896..b615743b8 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -169,6 +169,7 @@ TU_ATTR_ALWAYS_INLINE static inline void *_phys_addr(void *virtual_address)
   if (tusb_app_virt_to_phys) return tusb_app_virt_to_phys(virtual_address);
   return virtual_address;
 }
+
 TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address)
 {
   if (tusb_app_phys_to_virt) return tusb_app_phys_to_virt(physical_address);
@@ -238,7 +239,10 @@ bool hcd_init(uint8_t rhport)
   OHCI_REG->control_bit.hc_functional_state = OHCI_CONTROL_FUNCSTATE_OPERATIONAL; // make HC's state to operational state TODO use this to suspend (save power)
   OHCI_REG->rh_status_bit.local_power_status_change = 1; // set global power for ports
 
+#if CFG_TUSB_OS != OPT_OS_NONE
+  // TODO as above delay
   osal_task_delay(OHCI_REG->rh_descriptorA_bit.power_on_to_good_time * 2); // Wait POTG after power up
+#endif
 
   return true;
 }

From e34aeb5cf69315d2d7711f0a1d040a28492d026d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 27 Feb 2023 09:11:35 +0700
Subject: [PATCH 1490/2085] minor clean up

---
 src/class/audio/audio_device.c |  2 +-
 src/class/hid/hid_device.c     |  6 +++---
 src/class/midi/midi_device.c   |  2 +-
 src/class/msc/msc_device.c     | 10 +++++-----
 src/common/tusb_common.h       | 21 ++++++++++++++++++---
 src/device/usbd_control.c      |  2 +-
 src/tusb.c                     | 21 ---------------------
 7 files changed, 29 insertions(+), 35 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 81df95139..de5a20d6d 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2199,7 +2199,7 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req
   if (len > _audiod_fct[func_id].ctrl_buf_sz) len = _audiod_fct[func_id].ctrl_buf_sz;
 
   // Copy into buffer
-  TU_VERIFY(tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, sizeof(_audiod_fct[func_id].ctrl_buf), data, (size_t)len)==0);
+  TU_VERIFY(0 == tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, sizeof(_audiod_fct[func_id].ctrl_buf), data, (size_t)len));
 
   // Schedule transmit
   return tud_control_xfer(rhport, p_request, (void*)_audiod_fct[func_id].ctrl_buf, len);
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 40654eef9..37a22b609 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -93,11 +93,11 @@ bool tud_hid_n_report(uint8_t instance, uint8_t report_id, void const* report, u
   if (report_id)
   {
     p_hid->epin_buf[0] = report_id;
-    TU_VERIFY(tu_memcpy_s(p_hid->epin_buf+1, CFG_TUD_HID_EP_BUFSIZE-1, report, len)==0);
+    TU_VERIFY(0 == tu_memcpy_s(p_hid->epin_buf+1, CFG_TUD_HID_EP_BUFSIZE-1, report, len));
     len++;
   }else
   {
-    TU_VERIFY(tu_memcpy_s(p_hid->epin_buf, CFG_TUD_HID_EP_BUFSIZE, report, len)==0);
+    TU_VERIFY(0 == tu_memcpy_s(p_hid->epin_buf, CFG_TUD_HID_EP_BUFSIZE, report, len));
   }
 
   return usbd_edpt_xfer(rhport, p_hid->ep_in, p_hid->epin_buf, len);
@@ -122,7 +122,7 @@ bool tud_hid_n_keyboard_report(uint8_t instance, uint8_t report_id, uint8_t modi
 
   if ( keycode )
   {
-    TU_VERIFY(tu_memcpy_s(report.keycode, sizeof(report.keycode), keycode, sizeof(report.keycode))==0);
+    memcpy(report.keycode, keycode, sizeof(report.keycode));
   }else
   {
     tu_memclr(report.keycode, 6);
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 0b52be181..92689dfb0 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -182,7 +182,7 @@ uint32_t tud_midi_n_stream_read(uint8_t itf, uint8_t cable_num, void* buffer, ui
     uint8_t const count = (uint8_t) tu_min32(stream->total - stream->index, bufsize);
 
     // Skip the header (1st byte) in the buffer
-    TU_VERIFY(tu_memcpy_s(buf8, bufsize, stream->buffer + 1 + stream->index, count)==0);
+    TU_VERIFY(0 == tu_memcpy_s(buf8, bufsize, stream->buffer + 1 + stream->index, count));
 
     total_read += count;
     stream->index += count;
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index ed4a3e86c..ecc95377f 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -707,7 +707,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         read_capa10.block_size = tu_htonl(block_size);
 
         resplen = sizeof(read_capa10);
-        TU_VERIFY(tu_memcpy_s(buffer, bufsize, &read_capa10, (size_t) resplen));
+        TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &read_capa10, (size_t) resplen));
       }
     }
     break;
@@ -741,7 +741,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
         read_fmt_capa.block_size_u16 = tu_htons(block_size);
 
         resplen = sizeof(read_fmt_capa);
-        TU_VERIFY(tu_memcpy_s(buffer, bufsize, &read_fmt_capa, (size_t) resplen)==0);
+        TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &read_fmt_capa, (size_t) resplen));
       }
     }
     break;
@@ -764,7 +764,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       tud_msc_inquiry_cb(lun, inquiry_rsp.vendor_id, inquiry_rsp.product_id, inquiry_rsp.product_rev);
 
       resplen = sizeof(inquiry_rsp);
-      TU_VERIFY(tu_memcpy_s(buffer, bufsize, &inquiry_rsp, (size_t) resplen)==0);
+      TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &inquiry_rsp, (size_t) resplen));
     }
     break;
 
@@ -788,7 +788,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       mode_resp.write_protected = !writable;
 
       resplen = sizeof(mode_resp);
-      TU_VERIFY(tu_memcpy_s(buffer, bufsize, &mode_resp, (size_t) resplen)==0);
+      TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &mode_resp, (size_t) resplen));
     }
     break;
 
@@ -806,7 +806,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_
       sense_rsp.add_sense_qualifier = p_msc->add_sense_qualifier;
 
       resplen = sizeof(sense_rsp);
-      TU_VERIFY(tu_memcpy_s(buffer, bufsize, &sense_rsp, (size_t) resplen)==0);
+      TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &sense_rsp, (size_t) resplen));
 
       // request sense callback could overwrite the sense data
       if (tud_msc_request_sense_cb)
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 78fdcfe36..3e5e1d427 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -84,11 +84,26 @@
 #define tu_varclr(_var)          tu_memclr(_var, sizeof(*(_var)))
 
 // This is a backport of memset_s from c11
-int32_t tu_memset_s(void *dest, size_t destsz, int ch, size_t count); 
+TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count)
+{
+  // TODO may check if desst and src is not NULL
+  if (count > destsz) {
+    return -1;
+  }
+  memset(dest, ch, count);
+  return 0;
+}
 
 // This is a backport of memcpy_s from c11
-int32_t tu_memcpy_s(void *dest, size_t destsz,
-                  const void * src, size_t count );
+TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, const void * src, size_t count )
+{
+  // TODO may check if desst and src is not NULL
+  if (count > destsz) {
+    return -1;
+  }
+  memcpy(dest, src, count);
+  return 0;
+}
 
 
 //------------- Bytes -------------//
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index ce4ddab66..b8a200845 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -94,7 +94,7 @@ static bool _data_stage_xact(uint8_t rhport)
   {
     ep_addr = EDPT_CTRL_IN;
     if ( xact_len ) {
-      TU_VERIFY(tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)==0);
+      TU_VERIFY(0 == tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len));
     }
   }
 
diff --git a/src/tusb.c b/src/tusb.c
index c918b0248..8318e5275 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -24,7 +24,6 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "common/tusb_common.h"
 #include "tusb_option.h"
 
 #if CFG_TUH_ENABLED || CFG_TUD_ENABLED
@@ -487,23 +486,3 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
 #endif
 
 #endif // host or device enabled
-
-//--------------------------------------------------------------------+
-// Common
-//--------------------------------------------------------------------+
-
-int32_t tu_memset_s(void *dest, size_t destsz, int ch, size_t count) {
-  if (count > destsz) {
-    return -1;
-  }
-  memset(dest, ch, count);
-  return 0;
-}
-
-int32_t tu_memcpy_s(void *dest, size_t destsz, const void *src, size_t count) {
-  if (count > destsz) {
-    return -1;
-  }
-  memcpy(dest, src, count);
-  return 0;
-}
\ No newline at end of file

From ffdc100cb90eefd13da77a478527ea25d982416c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 28 Feb 2023 17:11:59 +0700
Subject: [PATCH 1491/2085] rename ep_num to ep_idx, minor clean up

---
 src/class/audio/audio_device.c                | 105 ++++++------
 src/device/usbd.c                             |  20 +--
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 153 ++++++++++--------
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   | 151 ++++++++---------
 4 files changed, 223 insertions(+), 206 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 31c4783eb..ee26eddf5 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1495,17 +1495,19 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
       }
 
 #if USE_ISO_EP_ALLOCATION
-#if CFG_TUD_AUDIO_ENABLE_EP_IN
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN
       uint8_t  ep_in = 0;
       uint16_t ep_in_size = 0;
-#endif
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+  #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_EP_OUT
       uint8_t  ep_out = 0;
       uint16_t ep_out_size = 0;
-#endif
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+  #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
       uint8_t ep_fb = 0;
-#endif
+  #endif
 
       uint8_t const *p_desc = _audiod_fct[i].p_desc;
       uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
@@ -1516,28 +1518,28 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
           tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
           if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
           {
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
             // Explicit feedback EP
             if (desc_ep->bmAttributes.usage == 1)
             {
               ep_fb = desc_ep->bEndpointAddress;
             }
-#endif      
+  #endif
             // Data EP
             if (desc_ep->bmAttributes.usage == 0)
             {
               if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
               {
-#if CFG_TUD_AUDIO_ENABLE_EP_IN
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN
                 ep_in = desc_ep->bEndpointAddress;
                 ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
-#endif
+  #endif
               } else
               {
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+  #if CFG_TUD_AUDIO_ENABLE_EP_OUT
                 ep_out = desc_ep->bEndpointAddress;
                 ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size);
-#endif
+  #endif
               }
             }
             
@@ -1546,26 +1548,28 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
         p_desc = tu_desc_next(p_desc);
       }
 
-#if CFG_TUD_AUDIO_ENABLE_EP_IN
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN
       if (ep_in)
       {
         usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size);
       }
-#endif
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+  #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_EP_OUT
       if (ep_out)
       {
         usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size);
       }
-#endif
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+  #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
       if (ep_fb)
       {
         usbd_edpt_iso_alloc(rhport, ep_fb, 4);
       }
-#endif
+  #endif
 
-#endif
+#endif // USE_ISO_EP_ALLOCATION
 
       break;
     }
@@ -1628,18 +1632,19 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   if (audio->ep_in_as_intf_num == itf)
   {
     audio->ep_in_as_intf_num = 0;
-#if !USE_ISO_EP_ALLOCATION
+  #if !USE_ISO_EP_ALLOCATION
     usbd_edpt_close(rhport, audio->ep_in);
-#endif
+  #endif
+
     // Clear FIFOs, since data is no longer valid
-#if !CFG_TUD_AUDIO_ENABLE_ENCODING
+  #if !CFG_TUD_AUDIO_ENABLE_ENCODING
     tu_fifo_clear(&audio->ep_in_ff);
-#else
+  #else
     for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
     {
       tu_fifo_clear(&audio->tx_supp_ff[cnt]);
     }
-#endif
+  #endif
 
     // Invoke callback - can be used to stop data sampling
     if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
@@ -1647,24 +1652,25 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     audio->ep_in = 0;                           // Necessary?
 
   }
-#endif
+#endif // CFG_TUD_AUDIO_ENABLE_EP_IN
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
   if (audio->ep_out_as_intf_num == itf)
   {
     audio->ep_out_as_intf_num = 0;
-#if !USE_ISO_EP_ALLOCATION
+  #if !USE_ISO_EP_ALLOCATION
     usbd_edpt_close(rhport, audio->ep_out);
-#endif
+  #endif
+
     // Clear FIFOs, since data is no longer valid
-#if !CFG_TUD_AUDIO_ENABLE_DECODING
+  #if !CFG_TUD_AUDIO_ENABLE_DECODING
     tu_fifo_clear(&audio->ep_out_ff);
-#else
+  #else
     for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++)
     {
       tu_fifo_clear(&audio->rx_supp_ff[cnt]);
     }
-#endif
+  #endif
 
     // Invoke callback - can be used to stop data sampling
     if (tud_audio_set_itf_close_EP_cb) TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request));
@@ -1672,15 +1678,15 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     audio->ep_out = 0;                          // Necessary?
 
     // Close corresponding feedback EP
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-#if !USE_ISO_EP_ALLOCATION
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+    #if !USE_ISO_EP_ALLOCATION
     usbd_edpt_close(rhport, audio->ep_fb);
-#endif
+    #endif
     audio->ep_fb = 0;
     tu_memclr(&audio->feedback, sizeof(audio->feedback));
-#endif
+  #endif
   }
-#endif
+#endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
 
   // Save current alternative interface setting
   audio->alt_setting[idxItf] = alt;
@@ -1724,11 +1730,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             audio->ep_in_sz = tu_edpt_packet_size(desc_ep);
 
             // If software encoding is enabled, parse for the corresponding parameters - doing this here means only AS interfaces with EPs get scanned for parameters
-#if CFG_TUD_AUDIO_ENABLE_ENCODING
+  #if CFG_TUD_AUDIO_ENABLE_ENCODING
             audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf);
 
             // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+    #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
             const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / audio->n_bytes_per_sampe_tx) * audio->n_bytes_per_sampe_tx);
             for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
             {
@@ -1736,9 +1742,8 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             }
             audio->n_ff_used_tx = audio->n_channels_tx / audio->n_channels_per_ff_tx;
             TU_ASSERT( audio->n_ff_used_tx <= audio->n_tx_supp_ff );
-#endif
-
-#endif
+    #endif
+  #endif
 
             // Schedule first transmit if alternate interface is not zero i.e. streaming is disabled - in case no sample data is available a ZLP is loaded
             // It is necessary to trigger this here since the refill is done with an RX FIFO empty interrupt which can only trigger if something was in there
@@ -1755,11 +1760,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             audio->ep_out_as_intf_num = itf;
             audio->ep_out_sz = tu_edpt_packet_size(desc_ep);
 
-#if CFG_TUD_AUDIO_ENABLE_DECODING
+  #if CFG_TUD_AUDIO_ENABLE_DECODING
             audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf);
 
             // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
+    #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
             const uint16_t active_fifo_depth = (audio->rx_supp_ff_sz_max / audio->n_bytes_per_sampe_rx) * audio->n_bytes_per_sampe_rx;
             for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++)
             {
@@ -1767,18 +1772,18 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             }
             audio->n_ff_used_rx = audio->n_channels_rx / audio->n_channels_per_ff_rx;
             TU_ASSERT( audio->n_ff_used_rx <= audio->n_rx_supp_ff );
-#endif
-#endif
+    #endif
+  #endif
 
             // Prepare for incoming data
-#if USE_LINEAR_BUFFER_RX
+  #if USE_LINEAR_BUFFER_RX
             TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false);
-#else
+  #else
             TU_VERIFY(usbd_edpt_xfer_fifo(rhport, audio->ep_out, &audio->ep_out_ff, audio->ep_out_sz), false);
-#endif
+  #endif
           }
 
-#if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
           if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1)   // Check if usage is explicit data feedback
           {
             audio->ep_fb = ep_addr;
@@ -1787,7 +1792,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             // Enable SOF interrupt if callback is implemented
             if (tud_audio_feedback_interval_isr) usbd_sof_enable(rhport, true);
           }
-#endif
+  #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT
 
           foundEPs += 1;
@@ -1838,7 +1843,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
           default: break;
         }
       }
-#endif
+#endif // CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
       // We are done - abort loop
       break;
diff --git a/src/device/usbd.c b/src/device/usbd.c
index fd4414559..b67d3e29f 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1384,12 +1384,10 @@ bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packe
 {
   rhport = _usbd_rhport;
 
+  TU_ASSERT(dcd_edpt_iso_alloc);
   TU_ASSERT(tu_edpt_number(ep_addr) < CFG_TUD_ENDPPOINT_MAX);
 
-  if (dcd_edpt_iso_alloc)
-    return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size);
-  else
-    return false;
+  return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size);
 }
 
 bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
@@ -1399,18 +1397,14 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep
   uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(desc_ep->bEndpointAddress);
   
+  TU_ASSERT(dcd_edpt_iso_activate);
   TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX);
   TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
   
-  if (dcd_edpt_iso_activate)
-  {
-    _usbd_dev.ep_status[epnum][dir].stalled = false;
-    _usbd_dev.ep_status[epnum][dir].busy = false;
-    _usbd_dev.ep_status[epnum][dir].claimed = false;
-    return dcd_edpt_iso_activate(rhport, desc_ep);
-  }
-  else
-    return false;
+  _usbd_dev.ep_status[epnum][dir].stalled = false;
+  _usbd_dev.ep_status[epnum][dir].busy = false;
+  _usbd_dev.ep_status[epnum][dir].claimed = false;
+  return dcd_edpt_iso_activate(rhport, desc_ep);
 }
 
 #endif
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index c9b244c8c..78da9d0e5 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -6,7 +6,7 @@
  * Portions:
  * Copyright (c) 2016 STMicroelectronics
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
- * Copyright (c) 2022 Simon Küppers (skuep)
+ * Copyright (c) 2022 Simon Küppers (skuep)
  * Copyright (c) 2022 HiFiPhile
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
@@ -159,6 +159,10 @@ TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LEN
 
 TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes");
 
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
 // One of these for every EP IN & OUT, uses a bit of RAM....
 typedef struct
 {
@@ -169,21 +173,9 @@ typedef struct
   uint16_t pma_ptr;
   uint16_t max_packet_size;
   uint16_t pma_alloc_size;
-  uint8_t epnum;
+  uint8_t ep_idx; // index for USB_EPnR register
 } xfer_ctl_t;
 
-static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
-
-TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr)
-{
-  uint8_t epnum = tu_edpt_number(ep_addr);
-  uint8_t dir = tu_edpt_dir(ep_addr);
-  // Fix -Werror=null-dereference
-  TU_ASSERT(epnum < MAX_EP_COUNT, &xfer_status[0][0]);
-
-  return &xfer_status[epnum][dir];
-}
-
 // EP allocator
 typedef struct
 {
@@ -192,12 +184,18 @@ typedef struct
   bool allocated[2];
 } ep_alloc_t;
 
+static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
+
 static ep_alloc_t ep_alloc_status[STFSDEV_EP_COUNT];
 
 static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
 
 static uint8_t remoteWakeCountdown; // When wake is requested
 
+//--------------------------------------------------------------------+
+// Prototypes
+//--------------------------------------------------------------------+
+
 // into the stack.
 static void dcd_handle_bus_reset(void);
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix);
@@ -217,6 +215,20 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
 static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes);
 static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes);
 
+//--------------------------------------------------------------------+
+// Inline helper
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr)
+{
+  uint8_t epnum = tu_edpt_number(ep_addr);
+  uint8_t dir = tu_edpt_dir(ep_addr);
+  // Fix -Werror=null-dereference
+  TU_ASSERT(epnum < MAX_EP_COUNT, &xfer_status[0][0]);
+
+  return &xfer_status[epnum][dir];
+}
+
 // Using a function due to better type checks
 // This seems better than having to do type casts everywhere else
 TU_ATTR_ALWAYS_INLINE static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) {
@@ -228,6 +240,10 @@ TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits(uint16_t mask) {
   USB->ISTR = ~mask;
 }
 
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
 void dcd_init (uint8_t rhport)
 {
   /* Clocks should already be enabled */
@@ -825,6 +841,7 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
     {
       return i;
     }
+
     // If EP of current direction is not allocated
     // Except for ISO endpoint, both direction should be free
     if(!ep_alloc_status[i].allocated[dir] &&
@@ -886,14 +903,14 @@ static void dcd_ep_free(uint8_t ep_addr)
 bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   (void)rhport;
-  uint8_t const epnum = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer);
+  uint8_t const ep_idx = dcd_ep_alloc(p_endpoint_desc->bEndpointAddress, p_endpoint_desc->bmAttributes.xfer);
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
   const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size);
   uint16_t pma_addr;
   uint32_t wType;
 
-  TU_ASSERT(epnum < STFSDEV_EP_COUNT);
+  TU_ASSERT(ep_idx < STFSDEV_EP_COUNT);
   TU_ASSERT(buffer_size <= 1024);
 
   // Set type
@@ -916,8 +933,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
     TU_ASSERT(false);
   }
 
-  pcd_set_eptype(USB, epnum, wType);
-  pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
+  pcd_set_eptype(USB, ep_idx, wType);
+  pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
   // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
   // or being double-buffered (bulk endpoints)
   pcd_clear_ep_kind(USB,0);
@@ -928,37 +945,37 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
 
   if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) )
   {
-    *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
-    pcd_set_ep_tx_bufsize(USB, epnum, buffer_size);
-    pcd_clear_tx_dtog(USB, epnum);
+    *pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr;
+    pcd_set_ep_tx_bufsize(USB, ep_idx, buffer_size);
+    pcd_clear_tx_dtog(USB, ep_idx);
   }
 
   if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) )
   {
-    *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
-    pcd_set_ep_rx_bufsize(USB, epnum, buffer_size);
-    pcd_clear_rx_dtog(USB, epnum);
+    *pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr;
+    pcd_set_ep_rx_bufsize(USB, ep_idx, buffer_size);
+    pcd_clear_rx_dtog(USB, ep_idx);
   }
 
   /* Enable endpoint */
   if (dir == TUSB_DIR_IN)
   {
     if(wType == USB_EP_ISOCHRONOUS) {
-      pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS);
+      pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
     } else {
-      pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK);
+      pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
     }
   } else
   {
     if(wType == USB_EP_ISOCHRONOUS) {
-      pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS);
+      pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
     } else {
-      pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
+      pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
     }
   }
 
   xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size;
-  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum = epnum;
+  xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->ep_idx = ep_idx;
 
   return true;
 }
@@ -981,16 +998,16 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
   (void)rhport;
 
   xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
-  uint8_t const epnum = xfer->epnum;
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const ep_idx = xfer->ep_idx;
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
 
   if(dir == TUSB_DIR_IN)
   {
-    pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS);
+    pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
   }
   else
   {
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS);
+    pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
   }
 
   dcd_ep_free(ep_addr);
@@ -1004,19 +1021,19 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
   
   TU_ASSERT(largest_packet_size <= 1024);
   
-  uint8_t const epnum = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
+  uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
   const uint16_t buffer_size = pcd_aligned_buffer_size(largest_packet_size);
 
   /* Create a packet memory buffer area. For isochronous endpoints,
    * use the same buffer as the double buffer, essentially disabling double buffering */
   uint16_t pma_addr = dcd_pma_alloc(ep_addr, buffer_size);
 
-  xfer_ctl_ptr(ep_addr)->epnum = epnum;
+  xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
 
-  pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS);
+  pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS);
   
-  *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr;
-  *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr;
+  *pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr;
+  *pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr;
   
   return true;
 }
@@ -1024,30 +1041,30 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
 bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   (void)rhport;
-  uint8_t const epnum = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->epnum;
-  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
+  uint8_t const ep_idx = xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->ep_idx;
+  uint8_t const dir    = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
   const uint16_t packet_size = tu_edpt_packet_size(p_endpoint_desc);
   const uint16_t buffer_size = pcd_aligned_buffer_size(packet_size);
 
   /* Disable endpoint */
   if(dir == TUSB_DIR_IN)
   {
-    pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS);
+    pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_DIS);
   }
   else
   {
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS);
+    pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
   }
   
-  pcd_set_ep_address(USB, epnum, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
+  pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
   // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
   // or being double-buffered (bulk endpoints)
   pcd_clear_ep_kind(USB,0);
 
-  pcd_set_ep_tx_bufsize(USB, epnum, buffer_size);
-  pcd_set_ep_rx_bufsize(USB, epnum, buffer_size);
-  pcd_clear_tx_dtog(USB, epnum);
-  pcd_clear_rx_dtog(USB, epnum);
+  pcd_set_ep_tx_bufsize(USB, ep_idx, buffer_size);
+  pcd_set_ep_rx_bufsize(USB, ep_idx, buffer_size);
+  pcd_clear_tx_dtog(USB, ep_idx);
+  pcd_clear_rx_dtog(USB, ep_idx);
 
   xfer_ctl_ptr(p_endpoint_desc->bEndpointAddress)->max_packet_size = packet_size;
 
@@ -1093,8 +1110,8 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   (void) rhport;
 
   xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
-  uint8_t const epnum = xfer->epnum;
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const ep_idx = xfer->ep_idx;
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
 
   xfer->buffer = buffer;
   xfer->ff     = NULL;
@@ -1105,22 +1122,22 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   {
     // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid
     // buffer for the control endpoint.
-    if (epnum == 0 && buffer == NULL)
+    if (ep_idx == 0 && buffer == NULL)
     {
         xfer->buffer = (uint8_t*)_setup_packet;
     }
 
     if(total_bytes > xfer->max_packet_size)
     {
-      pcd_set_ep_rx_bufsize(USB,epnum,xfer->max_packet_size);
+      pcd_set_ep_rx_bufsize(USB,ep_idx,xfer->max_packet_size);
     } else {
-      pcd_set_ep_rx_bufsize(USB,epnum,total_bytes);
+      pcd_set_ep_rx_bufsize(USB,ep_idx,total_bytes);
     }
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID);
+    pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_VALID);
   }
   else // IN
   {
-    dcd_transmit_packet(xfer,epnum);
+    dcd_transmit_packet(xfer,ep_idx);
   }
   return true;
 }
@@ -1130,7 +1147,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   (void) rhport;
 
   xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
-  uint8_t const epnum = xfer->epnum;
+  uint8_t const epnum = xfer->ep_idx;
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   xfer->buffer = NULL;
@@ -1160,16 +1177,16 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
   (void)rhport;
 
   xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
-  uint8_t const epnum = xfer->epnum;
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const ep_idx = xfer->ep_idx;
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
 
   if (dir == TUSB_DIR_IN)
   { // IN
-    pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_STALL);
+    pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_STALL);
   }
   else
   { // OUT
-    pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_STALL);
+    pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_STALL);
   }
 }
 
@@ -1178,25 +1195,25 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   (void)rhport;
 
   xfer_ctl_t * xfer = xfer_ctl_ptr(ep_addr);
-  uint8_t const epnum = xfer->epnum;
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
+  uint8_t const ep_idx = xfer->ep_idx;
+  uint8_t const dir    = tu_edpt_dir(ep_addr);
 
   if (dir == TUSB_DIR_IN)
   { // IN
-    if (pcd_get_eptype(USB, epnum) !=  USB_EP_ISOCHRONOUS) {
-      pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK);
+    if (pcd_get_eptype(USB, ep_idx) !=  USB_EP_ISOCHRONOUS) {
+      pcd_set_ep_tx_status(USB, ep_idx, USB_EP_TX_NAK);
     }
 
     /* Reset to DATA0 if clearing stall condition. */
-    pcd_clear_tx_dtog(USB, epnum);
+    pcd_clear_tx_dtog(USB, ep_idx);
   }
   else
   { // OUT
-    if (pcd_get_eptype(USB, epnum) !=  USB_EP_ISOCHRONOUS) {
-      pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
+    if (pcd_get_eptype(USB, ep_idx) !=  USB_EP_ISOCHRONOUS) {
+      pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_NAK);
     }
     /* Reset to DATA0 if clearing stall condition. */
-    pcd_clear_rx_dtog(USB, epnum);
+    pcd_clear_rx_dtog(USB, ep_idx);
   }
 }
 
@@ -1318,7 +1335,7 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
     *dstVal++ = ((temp >> 8) & 0xFF);
   }
 
-  if (wNBytes % 2)
+  if (wNBytes & 0x01)
   {
     temp = *pdwVal;
     pdwVal += PMA_STRIDE;
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index f4966907a..039fb13d2 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -120,9 +120,9 @@
 static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
 
 // prototypes
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum);
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue);
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx);
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx);
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue);
 
 /* Aligned buffer size according to hardware */
 TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size)
@@ -138,71 +138,71 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t si
 }
 
 /* SetENDPOINT */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue)
 {
-  __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpNum*2u);
+  __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
   *reg = (uint16_t)wRegValue;
 }
 
 /* GetENDPOINT */
-TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpNum) {
-  __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpNum*2u);
+TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) {
+  __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
   return *reg;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wType)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wType)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= (uint32_t)USB_EP_T_MASK;
   regVal |= wType;
   regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high
-  pcd_set_endpoint(USBx, bEpNum, regVal);
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EP_T_FIELD;
   return regVal;
 }
 /**
   * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
   * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
+  * @param  bEpIdx Endpoint Number.
   * @retval None
   */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPREG_MASK;
   regVal &= ~USB_EP_CTR_RX;
   regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0)
-  pcd_set_endpoint(USBx, bEpNum, regVal);
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPREG_MASK;
   regVal &= ~USB_EP_CTR_TX;
   regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0)
-  pcd_set_endpoint(USBx, bEpNum,regVal);
+  pcd_set_endpoint(USBx, bEpIdx,regVal);
 }
 /**
   * @brief  gets counter of the tx buffer.
   * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
+  * @param  bEpIdx Endpoint Number.
   * @retval Counter value
   */
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpNum);
+  __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
   return *regPtr & 0x3ffU;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpNum);
+  __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
   return *regPtr & 0x3ffU;
 }
 
@@ -229,17 +229,17 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwRe
 /**
   * @brief  Sets address in an endpoint register.
   * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
+  * @param  bEpIdx Endpoint Number.
   * @param  bAddr Address.
   * @retval None
   */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t bAddr)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t bAddr)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPREG_MASK;
   regVal |= bAddr;
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpNum,regVal);
+  pcd_set_endpoint(USBx, bEpIdx,regVal);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
@@ -250,47 +250,47 @@ TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_Type
 }
 
 // Pointers to the PMA table entries (using the ARM address space)
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 0u);
+  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u);
 }
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 1u);
+  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  return  pcd_btable_word_ptr(USBx,(bEpNum)*4u + 2u);
+  return  pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 3u);
+  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wCount)
 {
-  __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpNum);
+  __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
   *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wCount)
 {
-  __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpNum);
+  __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
   *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wCount)
 {
-  __IO uint16_t *pdwReg = pcd_ep_tx_cnt_ptr((USBx),(bEpNum));
+  __IO uint16_t *pdwReg = pcd_ep_tx_cnt_ptr((USBx),(bEpIdx));
   wCount = pcd_aligned_buffer_size(wCount);
   pcd_set_ep_cnt_reg(pdwReg, wCount);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wCount)
 {
-  __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum));
+  __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpIdx));
   wCount = pcd_aligned_buffer_size(wCount);
   pcd_set_ep_cnt_reg(pdwReg, wCount);
 }
@@ -298,13 +298,13 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USB
 /**
   * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
   * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
+  * @param  bEpIdx Endpoint Number.
   * @param  wState new state
   * @retval None
   */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wState)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wState)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPTX_DTOGMASK;
 
   /* toggle first bit ? */
@@ -319,20 +319,20 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx
   }
 
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
 } /* pcd_set_ep_tx_status */
 
 /**
   * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
   * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
+  * @param  bEpIdx Endpoint Number.
   * @param  wState new state
   * @retval None
   */
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpNum, uint32_t wState)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wState)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPRX_DTOGMASK;
 
   /* toggle first bit ? */
@@ -347,12 +347,12 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx
   }
 
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
 } /* pcd_set_ep_rx_status */
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx,  uint32_t bEpIdx)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   return (regVal & USB_EPRX_STAT) >> (12u);
 } /* pcd_get_ep_rx_status */
 
@@ -360,71 +360,71 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef *
 /**
   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
   * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
+  * @param  bEpIdx Endpoint Number.
   * @retval None
   */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPREG_MASK;
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPREG_MASK;
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
 }
 
 /**
   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
   * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
+  * @param  bEpIdx Endpoint Number.
   * @retval None
   */
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   if((regVal & USB_EP_DTOG_RX) != 0)
   {
-    pcd_rx_dtog(USBx,bEpNum);
+    pcd_rx_dtog(USBx,bEpIdx);
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx,  uint32_t bEpIdx)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   if((regVal & USB_EP_DTOG_TX) != 0)
   {
-    pcd_tx_dtog(USBx,bEpNum);
+    pcd_tx_dtog(USBx,bEpIdx);
   }
 }
 
 /**
   * @brief  set & clear EP_KIND bit.
   * @param  USBx USB peripheral instance register address.
-  * @param  bEpNum Endpoint Number.
+  * @param  bEpIdx Endpoint Number.
   * @retval None
   */
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx,  uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_kind(USB_TypeDef * USBx,  uint32_t bEpIdx)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal |= USB_EP_KIND;
   regVal &= USB_EPREG_MASK;
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
 }
-TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  uint32_t regVal = pcd_get_endpoint(USBx, bEpNum);
+  uint32_t regVal = pcd_get_endpoint(USBx, bEpIdx);
   regVal &= USB_EPKIND_MASK;
   regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX;
-  pcd_set_endpoint(USBx, bEpNum, regVal);
+  pcd_set_endpoint(USBx, bEpIdx, regVal);
 }
 
 // This checks if the device has "LPM"
@@ -438,6 +438,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, u
      USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
 
 // Number of endpoints in hardware
+// TODO should use TUP_DCD_ENDPOINT_MAX
 #define STFSDEV_EP_COUNT (8u)
 
 #endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */

From 787afbbcd0b178925fa1e429f7a650dd2146485b Mon Sep 17 00:00:00 2001
From: Brandon Alba <brandonealba@protonmail.com>
Date: Tue, 28 Feb 2023 10:25:06 -0800
Subject: [PATCH 1492/2085] Initialized all RCC init structs for all STM32H7
 BSP variants as empty

---
 hw/bsp/stm32h7/boards/daisyseed/board.h       | 6 +++---
 hw/bsp/stm32h7/boards/stm32h723nucleo/board.h | 4 ++--
 hw/bsp/stm32h7/boards/stm32h743eval/board.h   | 6 +++---
 hw/bsp/stm32h7/boards/stm32h743nucleo/board.h | 4 ++--
 hw/bsp/stm32h7/boards/stm32h745disco/board.h  | 6 +++---
 5 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.h b/hw/bsp/stm32h7/boards/daisyseed/board.h
index 579c09727..0ad809720 100644
--- a/hw/bsp/stm32h7/boards/daisyseed/board.h
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.h
@@ -57,9 +57,9 @@
 //--------------------------------------------------------------------+
 static inline void board_stm32h7_clock_init(void)
 {
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
 
   /*!< Supply configuration update enable */
   /* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
index 56a48ec24..71ca33447 100644
--- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
@@ -64,8 +64,8 @@
 //--------------------------------------------------------------------+
 static inline void board_stm32h7_clock_init(void)
 {
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
 
   /* The PWR block is always enabled on the H7 series- there is no clock
      enable. For now, use the default VOS3 scale mode (lowest) and limit clock
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
index af2063ce0..666bec9a1 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
@@ -63,9 +63,9 @@
 //--------------------------------------------------------------------+
 static inline void board_stm32h7_clock_init(void)
 {
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
 
   /*!< Supply configuration update enable */
   HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
index 06148c875..c101801eb 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
@@ -55,8 +55,8 @@
 //--------------------------------------------------------------------+
 static inline void board_stm32h7_clock_init(void)
 {
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
 
   /* The PWR block is always enabled on the H7 series- there is no clock
      enable. For now, use the default VOS3 scale mode (lowest) and limit clock
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.h b/hw/bsp/stm32h7/boards/stm32h745disco/board.h
index d33e0c8eb..d7d3e8723 100644
--- a/hw/bsp/stm32h7/boards/stm32h745disco/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.h
@@ -57,9 +57,9 @@
 //--------------------------------------------------------------------+
 static inline void board_stm32h7_clock_init(void)
 {
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
+  RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
 
   /*!< Supply configuration update enable */
   /* For STM32H750XB, use "HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);" */

From 8c8f26f14e6cb4561ed0a937739b926da27393ff Mon Sep 17 00:00:00 2001
From: Brandon Alba <brandonealba@protonmail.com>
Date: Tue, 28 Feb 2023 10:31:07 -0800
Subject: [PATCH 1493/2085] In some STM32H7 BSP variants, initialized
 RCC_PeriphCLKInitStruct instances as empty

---
 hw/bsp/stm32h7/boards/stm32h723nucleo/board.h | 2 +-
 hw/bsp/stm32h7/boards/stm32h743nucleo/board.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
index 71ca33447..0eb5e76ad 100644
--- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h
@@ -111,7 +111,7 @@ static inline void board_stm32h7_clock_init(void)
      separate. However, the main system PLL (PLL1) doesn't have a direct
      connection to the USB peripheral clock to generate 48 MHz, so we do this
      dance. This will connect PLL1's Q output to the USB peripheral clock. */
-  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct;
+  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
 
   RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
   RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
index c101801eb..8c6a7ce5a 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h
@@ -102,7 +102,7 @@ static inline void board_stm32h7_clock_init(void)
      separate. However, the main system PLL (PLL1) doesn't have a direct
      connection to the USB peripheral clock to generate 48 MHz, so we do this
      dance. This will connect PLL1's Q output to the USB peripheral clock. */
-  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct;
+  RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
 
   RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
   RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;

From 5d3084a714eaa16b04e222ac4dc965ef29499e06 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Mar 2023 11:21:46 +0700
Subject: [PATCH 1494/2085] add TUP_USBIP_FSDEV and TUP_USBIP_FSDEV_STM32,
 clean up ifdef with stm32

---
 src/class/audio/audio_device.c                | 284 +++++++++---------
 src/common/tusb_mcu.h                         | 100 ++++--
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |  34 +--
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   |  19 +-
 4 files changed, 227 insertions(+), 210 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 5bccc66b7..d9c873851 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -66,71 +66,41 @@
 
 // Use ring buffer if it's available, some MCUs need extra RAM requirements
 #ifndef TUD_AUDIO_PREFER_RING_BUFFER
-#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT
-#define TUD_AUDIO_PREFER_RING_BUFFER 0
-#else
-#define TUD_AUDIO_PREFER_RING_BUFFER 1
-#endif
+  #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT
+    #define TUD_AUDIO_PREFER_RING_BUFFER 0
+  #else
+    #define TUD_AUDIO_PREFER_RING_BUFFER 1
+  #endif
 #endif
 
 // Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer
 // is available or driver is would need to be changed dramatically
 
 // Only STM32 and dcd_transdimension use non-linear buffer for now
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32F1                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32F2                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32F3                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32F4                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32F7                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32H7                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32L0                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32L1                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32L4                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32G4                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32WB                               || \
-    CFG_TUSB_MCU == OPT_MCU_RX63X                                 || \
-    CFG_TUSB_MCU == OPT_MCU_RX65X                                 || \
-    CFG_TUSB_MCU == OPT_MCU_RX72N                                 || \
-    CFG_TUSB_MCU == OPT_MCU_GD32VF103                             || \
-    CFG_TUSB_MCU == OPT_MCU_LPC18XX                               || \
-    CFG_TUSB_MCU == OPT_MCU_LPC43XX                               || \
-    CFG_TUSB_MCU == OPT_MCU_MIMXRT                                || \
+// dwc2 except esp32sx (since it may use dcd_esp32sx)
+#if (defined(TUP_USBIP_DWC2) && !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)) || \
+    defined(TUP_USBIP_FSDEV)          || \
+    CFG_TUSB_MCU == OPT_MCU_RX63X     || \
+    CFG_TUSB_MCU == OPT_MCU_RX65X     || \
+    CFG_TUSB_MCU == OPT_MCU_RX72N     || \
+    CFG_TUSB_MCU == OPT_MCU_LPC18XX   || \
+    CFG_TUSB_MCU == OPT_MCU_LPC43XX   || \
+    CFG_TUSB_MCU == OPT_MCU_MIMXRT    || \
     CFG_TUSB_MCU == OPT_MCU_MSP432E4
-#if TUD_AUDIO_PREFER_RING_BUFFER
-#define  USE_LINEAR_BUFFER     0
+  #if TUD_AUDIO_PREFER_RING_BUFFER
+    #define  USE_LINEAR_BUFFER     0
+  #else
+    #define  USE_LINEAR_BUFFER     1
+  #endif
 #else
-#define  USE_LINEAR_BUFFER     1
-#endif
-#else
-#define  USE_LINEAR_BUFFER     1
-#endif
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
-    defined(STM32F103x6) || defined(STM32F103xB) || \
-    defined(STM32F103xE) || defined(STM32F103xG)
-#define STM32F1_FSDEV
-#endif
-
-#if defined(STM32L412xx) || defined(STM32L422xx) || \
-    defined(STM32L432xx) || defined(STM32L433xx) || \
-    defined(STM32L442xx) || defined(STM32L443xx) || \
-    defined(STM32L452xx) || defined(STM32L462xx)
-#define STM32L4_FSDEV
+  #define  USE_LINEAR_BUFFER     1
 #endif
 
 // Temporarily put the check here for stm32_fsdev
-#if CFG_TUSB_MCU == OPT_MCU_STM32F0                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32F3                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32L0                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32L1                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32G4                               || \
-    CFG_TUSB_MCU == OPT_MCU_STM32WB                               || \
-    (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV))     || \
-    (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV))
-#define  USE_ISO_EP_ALLOCATION   1
+#ifdef TUP_USBIP_FSDEV
+  #define  USE_ISO_EP_ALLOCATION   1
 #else
-#define  USE_ISO_EP_ALLOCATION   0
+  #define  USE_ISO_EP_ALLOCATION   0
 #endif
 
 // Declaration of buffers
@@ -142,143 +112,159 @@
 
 // EP IN software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
-#if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_in_ff_mutex_wr_1;                                                             // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_in_ff_mutex_wr_2;                                                             // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_in_ff_mutex_wr_3;                                                             // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
+  #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t ep_in_ff_mutex_wr_1; // No need for read mutex as only USB driver reads from FIFO
+    #endif
+  #endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
+
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t ep_in_ff_mutex_wr_2; // No need for read mutex as only USB driver reads from FIFO
+    #endif
+  #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
+
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t ep_in_ff_mutex_wr_3; // No need for read mutex as only USB driver reads from FIFO
+    #endif
+  #endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
 #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
 
 // Linear buffer TX in case:
 // - target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR
 // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING)
-#if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
-#endif
+  #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
+  #endif
+
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
+  #endif
+
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
+  #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 
 // EP OUT software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
-#if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_out_ff_mutex_rd_1;                                                            // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_out_ff_mutex_rd_2;                                                            // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t ep_out_ff_mutex_rd_3;                                                            // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
+  #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t ep_out_ff_mutex_rd_1; // No need for write mutex as only USB driver writes into FIFO
+    #endif
+  #endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
+
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t ep_out_ff_mutex_rd_2; // No need for write mutex as only USB driver writes into FIFO
+    #endif
+  #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
+
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t ep_out_ff_mutex_rd_3; // No need for write mutex as only USB driver writes into FIFO
+    #endif
+  #endif // CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
 
 // Linear buffer RX in case:
 // - target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR
 // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
-#if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
-#endif
+  #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
+  #endif
+
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
+  #endif
+
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
+  #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 
 // Control buffers
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
+
 #if CFG_TUD_AUDIO > 1
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
 #endif
+
 #if CFG_TUD_AUDIO > 2
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
 #endif
 
 // Active alternate setting of interfaces
 uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT];
+
 #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_N_AS_INT > 0
 uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT];
 #endif
+
 #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_N_AS_INT > 0
 uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 #endif
 
 // Software encoding/decoding support FIFOs
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
-#if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
-tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
-tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
-tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];                   // No need for read mutex as only USB driver reads from FIFO
-#endif
-#endif
+  #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
+    tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
+    #endif
+  #endif
+
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
+    tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
+    #endif
+  #endif
+
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
+    tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
+    #endif
+  #endif
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
-#if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
-tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif
-#if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
-tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif
-#if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
-tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
-#if CFG_FIFO_MUTEX
-osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];                   // No need for write mutex as only USB driver writes into FIFO
-#endif
-#endif
+  #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
+    tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
+    #endif
+  #endif
+
+  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
+    tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
+    #endif
+  #endif
+
+  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
+    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
+    tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
+    #if CFG_FIFO_MUTEX
+    osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
+    #endif
+  #endif
 #endif
 
 typedef struct
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 1f27afa4e..257d08a85 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -48,7 +48,9 @@
  * - RHPORT_HIGHSPEED: support highspeed with on-chip PHY
  */
 
-//------------- NXP -------------//
+//--------------------------------------------------------------------+
+// NXP
+//--------------------------------------------------------------------+
 #if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
   #define TUP_DCD_ENDPOINT_MAX    5
 
@@ -89,12 +91,16 @@
 #elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
   #define TUP_DCD_ENDPOINT_MAX    16
 
-//------------- Nordic -------------//
+//--------------------------------------------------------------------+
+// Nordic
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // 8 CBI + 1 ISO
   #define TUP_DCD_ENDPOINT_MAX    9
 
-//------------- Microchip -------------//
+//--------------------------------------------------------------------+
+// Microchip
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \
       TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22)
   #define TUP_DCD_ENDPOINT_MAX    8
@@ -117,19 +123,30 @@
   #define TUP_DCD_ENDPOINT_MAX    16
   #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
-//------------- ST -------------//
+//--------------------------------------------------------------------+
+// ST
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_STM32F0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F1)
+  // - F102, F103 use fsdev
+  // - F105, F107 use dwc2
   #if defined (STM32F105x8) || defined (STM32F105xB) || defined (STM32F105xC) || \
       defined (STM32F107xB) || defined (STM32F107xC)
     #define TUP_USBIP_DWC2
     #define TUP_USBIP_DWC2_STM32
 
     #define TUP_DCD_ENDPOINT_MAX  4
-  #else
+  #elif defined(STM32F102x6) || defined(STM32F102xB) || \
+        defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+    #define TUP_USBIP_FSDEV
+    #define TUP_USBIP_FSDEV_STM32
     #define TUP_DCD_ENDPOINT_MAX  8
+  #else
+    #error "Unsupported STM32F1 mcu"
   #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F2)
@@ -140,6 +157,8 @@
   #define TUP_DCD_ENDPOINT_MAX    6
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F3)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32F4)
@@ -168,12 +187,18 @@
   #define TUP_DCD_ENDPOINT_MAX    9
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32L4)
+  // - L4x2, L4x3 use fsdev
+  // - L4x4, L4x6, L4x7, L4x9 use dwc2
   #if defined (STM32L475xx) || defined (STM32L476xx) ||                          \
       defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
       defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || \
@@ -183,11 +208,18 @@
     #define TUP_USBIP_DWC2_STM32
 
     #define TUP_DCD_ENDPOINT_MAX  6
-  #else
+  #elif defined(STM32L412xx) || defined(STM32L422xx) || defined(STM32L432xx) || defined(STM32L433xx) || \
+        defined(STM32L442xx) || defined(STM32L443xx) || defined(STM32L452xx) || defined(STM32L462xx)
+    #define TUP_USBIP_FSDEV
+    #define TUP_USBIP_FSDEV_STM32
     #define TUP_DCD_ENDPOINT_MAX  8
+  #else
+    #error "Unsupported STM32L4 mcu"
   #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32WB)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32U5)
@@ -195,24 +227,32 @@
   #define TUP_USBIP_DWC2_STM32
   #define TUP_DCD_ENDPOINT_MAX    6
 
-//------------- Sony -------------//
+//--------------------------------------------------------------------+
+// Sony
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_CXD56)
   #define TUP_DCD_ENDPOINT_MAX    7
   #define TUP_RHPORT_HIGHSPEED    1
   #define TUP_DCD_ENDPOINT_EXCLUSIVE_NUMBER
 
-//------------- TI -------------//
+//--------------------------------------------------------------------+
+// TI
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_MSP430x5xx)
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129)
   #define TUP_DCD_ENDPOINT_MAX    8
 
-//------------- ValentyUSB -------------//
+//--------------------------------------------------------------------+
+// ValentyUSB (Litex)
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_VALENTYUSB_EPTRI)
   #define TUP_DCD_ENDPOINT_MAX    16
 
-//------------- Nuvoton -------------//
+//--------------------------------------------------------------------+
+// Nuvoton
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_NUC121, OPT_MCU_NUC126)
   #define TUP_DCD_ENDPOINT_MAX    8
 
@@ -223,47 +263,65 @@
   #define TUP_DCD_ENDPOINT_MAX    12
   #define TUP_RHPORT_HIGHSPEED    1
 
-//------------- Espressif -------------//
+//--------------------------------------------------------------------+
+// Espressif
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    6
 
-//------------- Dialog -------------//
+//--------------------------------------------------------------------+
+// Dialog
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_DA1469X)
   #define TUP_DCD_ENDPOINT_MAX    4
 
-//------------- Raspberry Pi -------------//
+//--------------------------------------------------------------------+
+// Raspberry Pi
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_RP2040)
   #define TUP_DCD_ENDPOINT_MAX    16
 
   #define TU_ATTR_FAST_FUNC       __attribute__((section(".time_critical.tinyusb")))
 
-//------------- Silabs -------------//
+//--------------------------------------------------------------------+
+// Silabs
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    7
 
-//------------- Renesas -------------//
+//--------------------------------------------------------------------+
+// Renesas
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #define TUP_DCD_ENDPOINT_MAX    10
 
-//------------- GigaDevice -------------//
+//--------------------------------------------------------------------+
+// GigaDevice
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    4
 
-//------------- Broadcom -------------//
+//--------------------------------------------------------------------+
+// Broadcom
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1
 
-//------------- Broadcom -------------//
+//--------------------------------------------------------------------+
+// Infineon
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_XMC4000)
   #define TUP_USBIP_DWC2
   #define TUP_DCD_ENDPOINT_MAX    8
 
-//------------- BridgeTek -------------//
+//--------------------------------------------------------------------+
+// BridgeTek
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_FT90X)
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1
@@ -272,7 +330,9 @@
   #define TUP_DCD_ENDPOINT_MAX    16
   #define TUP_RHPORT_HIGHSPEED    1
 
-//------------ Allwinner -------------//
+//--------------------------------------------------------------------+
+// Allwinner
+//--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_F1C100S)
   #define TUP_DCD_ENDPOINT_MAX    4
 
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 78da9d0e5..e49c0b52e 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -101,32 +101,15 @@
 
 #include "tusb_option.h"
 
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
-    defined(STM32F103x6) || defined(STM32F103xB) || \
-    defined(STM32F103xE) || defined(STM32F103xG)
-#define STM32F1_FSDEV
-#endif
-
-#if defined(STM32L412xx) || defined(STM32L422xx) || \
-    defined(STM32L432xx) || defined(STM32L433xx) || \
-    defined(STM32L442xx) || defined(STM32L443xx) || \
-    defined(STM32L452xx) || defined(STM32L462xx)
-#define STM32L4_FSDEV
-#endif
-
-#if CFG_TUD_ENABLED && \
-      ( TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4, OPT_MCU_STM32WB) || \
-        (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV)) || \
-        (TU_CHECK_MCU(OPT_MCU_STM32L4) && defined(STM32L4_FSDEV)) \
-      )
-
-// In order to reduce the dependence on HAL, we undefine this.
-// Some definitions are copied to our private include file.
-#undef USE_HAL_DRIVER
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_FSDEV)
 
 #include "device/dcd.h"
-#include "portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h"
 
+#ifdef TUP_USBIP_FSDEV_STM32
+  // Undefine to reduce the dependence on HAL
+  #undef USE_HAL_DRIVER
+  #include "portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h"
+#endif
 
 /*****************************************************
  * Configuration
@@ -153,10 +136,7 @@
  */
 
 TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware");
-
-TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH),
-    "BTABLE does not fit in PMA RAM");
-
+TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH), "BTABLE does not fit in PMA RAM");
 TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes");
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 039fb13d2..015b177cf 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -1,12 +1,6 @@
 /**
-  ******************************************************************************
-  * @file    dcd_stm32f0_pvt_st.h
-  * @brief   DCD utilities from ST code
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
-  * <h2><center>&copy; parts COPYRIGHT(c) N Conrad</center></h2>
+  * Copyright(c) 2016 STMicroelectronics
+  * Copyright(c) N Conrad
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -30,7 +24,7 @@
   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
-  **********/
+  */
 
 // This file contains source copied from ST's HAL, and thus should have their copyright statement.
 
@@ -41,10 +35,7 @@
 #ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
 #define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
 
-#if defined(STM32F042x6) || \
-    defined(STM32F070x6) || defined(STM32F070xB) || \
-    defined(STM32F072xB) || \
-    defined(STM32F078xx)
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0
   #include "stm32f0xx.h"
   #define PMA_LENGTH (1024u)
   // F0x2 models are crystal-less
@@ -52,7 +43,7 @@
   // 070RB:    2 x 16 bits/word memory     LPM Support, BCD Support
   // PMA dedicated to USB (no sharing with CAN)
 
-#elif defined(STM32F1_FSDEV)
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
   #include "stm32f1xx.h"
   #define PMA_LENGTH (512u)
   // NO internal Pull-ups

From b7fa90e7066fff8a529d02c2a51a3319f25c77f8 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Thu, 2 Mar 2023 14:32:22 -0600
Subject: [PATCH 1495/2085] rp2040: Fixup lib and example compile for LLVM
 Embedded Toolchain for ARM

---
 examples/host/msc_file_explorer/src/msc_app.c |  2 +-
 hw/bsp/rp2040/family.cmake                    | 20 ++++++++++++++++---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c  |  2 +-
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 5a1635015..eef28fe12 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -413,7 +413,7 @@ void cli_cmd_cat(EmbeddedCli *cli, char *args, void *context)
       {
         for(UINT c = 0; c < count; c++)
         {
-          const char ch = buf[c];
+          const uint8_t ch = buf[c];
           if (isprint(ch) || iscntrl(ch))
           {
             putchar(ch);
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 1eab95304..82010efef 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -152,6 +152,9 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS)
 			family_add_default_example_warnings(${TARGET})
 		endif()
+		if(CMAKE_C_COMPILER_ID STREQUAL "Clang")
+			target_compile_options(${TARGET} PRIVATE -Wno-unreachable-code)
+		endif()
 		suppress_tinyusb_warnings()
 	endfunction()
 
@@ -172,8 +175,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 
 		# For rp2040 enable pico-pio-usb
 		if (TARGET tinyusb_pico_pio_usb)
-			# code does not compile with GCC 12+
-			if (NOT (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3))
+			# code does not compile with non GCC, or GCC 11.3+
+			if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND NOT CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3)
 				family_add_pico_pio_usb(${PROJECT})
 			endif()
 		endif()
@@ -278,7 +281,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 							COMPILE_FLAGS "-Wno-conversion")
 				endforeach()
 			endif()
-			if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0)
+			if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0)
 				set_source_files_properties(
 						${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
 						COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds")
@@ -310,6 +313,17 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 						PROPERTIES
 						COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-attributes")
 			endif()
+		elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang")
+			set_source_files_properties(
+					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+					COMPILE_FLAGS "-Wno-unreachable-code")
+			set_source_files_properties(
+					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
+					COMPILE_FLAGS "-Wno-unreachable-code-fallthrough")
+			set_source_files_properties(
+					${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-cast-qual")
 		endif()
 	endfunction()
 endif()
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index b5fa90c92..8df7bef2b 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -297,7 +297,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
   if ( status & USB_INTS_SETUP_REQ_BITS )
   {
     handled |= USB_INTS_SETUP_REQ_BITS;
-    uint8_t const * setup = (uint8_t const*) &usb_dpram->setup_packet;
+    uint8_t const * setup = remove_volatile_cast(uint8_t const*, &usb_dpram->setup_packet);
 
     // reset pid to both 1 (data and ack)
     reset_ep0_pid();

From e92583ffd73d5307b918be2e4c7e39b978a804ed Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 3 Mar 2023 15:37:17 +0700
Subject: [PATCH 1496/2085] try adding build for windows and macos

---
 .github/workflows/build_win_mac.yml | 55 +++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 .github/workflows/build_win_mac.yml

diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
new file mode 100644
index 000000000..f41457617
--- /dev/null
+++ b/.github/workflows/build_win_mac.yml
@@ -0,0 +1,55 @@
+name: Build Windows/MacOS
+
+on:
+  push:
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+      - '.github/workflows/build_win_mac.yml'
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+      - '.github/workflows/build_win_mac.yml'
+
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
+jobs:
+  # ---------------------------------------
+  # Build ARM family
+  # ---------------------------------------
+  build-arm:
+    strategy:
+      matrix:
+        os: [windows-latest, macos-latest]
+    runs-on: ${{ matrix.os }}
+
+    steps:
+    - name: Setup Python
+      uses: actions/setup-python@v4
+      with:
+        python-version: '3.x'
+
+    - name: Install ARM GCC
+      uses: carlosperate/arm-none-eabi-gcc-action@v1
+      with:
+        release: '11.2-2022.02'
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v3
+
+    - name: Checkout common submodules in lib
+      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
+
+    - name: Get Dependencies
+      run: python3 tools/get_dependencies.py stm32f0
+
+    - name: Build
+      run: python3 tools/build_family.py stm32f0

From 9a8a9359e40c93c187743a469f3d984dbf2f6413 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 3 Mar 2023 15:55:34 +0700
Subject: [PATCH 1497/2085] use make abspath intead of shell realpath

---
 .github/workflows/build_win_mac.yml |  1 +
 tools/top.mk                        | 11 ++++++-----
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index f41457617..5ff7fa6f8 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -27,6 +27,7 @@ jobs:
   # ---------------------------------------
   build-arm:
     strategy:
+      fail-fast: false
       matrix:
         os: [windows-latest, macos-latest]
     runs-on: ${{ matrix.os }}
diff --git a/tools/top.mk b/tools/top.mk
index af8d698f5..2800f9571 100644
--- a/tools/top.mk
+++ b/tools/top.mk
@@ -26,20 +26,21 @@ THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
 
 # strip off /tools/top.mk to get for example ../../..
 TOP := $(patsubst %/tools/top.mk,%,$(THIS_MAKEFILE))
-#$(info top.mk: Initial TOP=$(TOP))
+$(info top.mk: Initial TOP=$(TOP))
 
 # Set TOP to an absolute path, for example /tinyUSB (from ../../..)
 ifeq ($(CMDEXE),1)
 TOP := $(subst \,/,$(shell for %%i in ( $(TOP) ) do echo %%~fi))
 else
-TOP := $(shell realpath $(TOP))
+TOP := $(abspath $(TOP))
 endif
-#$(info top.mk: Top directory is $(TOP))
+
+$(info top.mk: Top directory is $(TOP))
 
 # Set CURRENT_PATH to the relative path from TOP to the current directory, ie examples/device/cdc_msc_freertos
 ifeq ($(CMDEXE),1)
 CURRENT_PATH := $(subst $(TOP)/,,$(subst \,/,$(shell echo %CD%)))
 else
-CURRENT_PATH := $(shell realpath --relative-to=$(TOP) `pwd`)
+CURRENT_PATH = $(subst $(TOP)/,,$(abspath .))
 endif
-#$(info top.mk: Path from top is $(CURRENT_PATH))
+$(info top.mk: CURRENT_PATH = $(CURRENT_PATH))

From 70895358481255d5349461f99dc1f536aafec6ce Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 3 Mar 2023 16:13:12 +0700
Subject: [PATCH 1498/2085] clean up f0 warnings

---
 hw/bsp/stm32f0/family.c             | 2 +-
 hw/bsp/stm32f0/family.mk            | 2 +-
 hw/bsp/stm32f0/stm32f0xx_hal_conf.h | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index a7e914128..0765f361d 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -165,7 +165,7 @@ void HardFault_Handler (void)
   * @param  line: assert_param error line source number
   * @retval None
   */
-void assert_failed(uint8_t* file, uint32_t line)
+void assert_failed(const char* file, uint32_t line)
 {
   (void) file; (void) line;
   /* USER CODE BEGIN 6 */
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 2983af49e..a065e9221 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -24,7 +24,7 @@ GCC_CFLAGS += \
   -nostdlib -nostartfiles \
 
 # suppress warning caused by vendor mcu driver
-GCC_CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
+GCC_CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
 
 # IAR Flags
 IAR_CFLAGS += --cpu cortex-m0
diff --git a/hw/bsp/stm32f0/stm32f0xx_hal_conf.h b/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
index cfa66b366..0bf053e13 100644
--- a/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
+++ b/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
@@ -303,9 +303,9 @@
   *         If expr is true, it returns no value.
   * @retval None
   */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed(__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+  void assert_failed(const char* file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
 #endif /* USE_FULL_ASSERT */    

From 363fcc5b6816c98c0e3e951f17a108c35fbd86da Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 3 Mar 2023 16:24:33 +0700
Subject: [PATCH 1499/2085] only build 1 board on windows/macos

---
 .github/workflows/build_win_mac.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index 5ff7fa6f8..c3aaa316a 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -53,4 +53,4 @@ jobs:
       run: python3 tools/get_dependencies.py stm32f0
 
     - name: Build
-      run: python3 tools/build_family.py stm32f0
+      run: python3 tools/build_family.py stm32f0 stm32f072disco

From a99ee1b1a238b3edc6f2511543ffed2a3a1b657e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 4 Mar 2023 20:08:10 +0700
Subject: [PATCH 1500/2085] bump up gcc, test macos uname

---
 .github/workflows/build_win_mac.yml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index c3aaa316a..c2e961f23 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -38,10 +38,13 @@ jobs:
       with:
         python-version: '3.x'
 
+    - if: matrix.os == 'macos-latest'
+      run: uname -a
+
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
       with:
-        release: '11.2-2022.02'
+        release: '12.2.Rel1'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3

From b4ef98cbdcac8a6bec4caee05920afc37a745149 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 5 Mar 2023 10:57:16 +0700
Subject: [PATCH 1501/2085] fix ci build on windows

---
 examples/make.mk | 4 ++--
 tools/top.mk     | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/examples/make.mk b/examples/make.mk
index dd7a5cf4e..5b364baf7 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -74,16 +74,16 @@ else
   SIZE = $(CROSS_COMPILE)size
 endif
 
-MKDIR = mkdir
-
 ifeq ($(CMDEXE),1)
   CP = copy
   RM = del
   PYTHON = python
+  MKDIR = cmd /e /c mkdir
 else
   SED = sed
   CP = cp
   RM = rm
+  MKDIR = mkdir
   PYTHON = python3
 endif
 
diff --git a/tools/top.mk b/tools/top.mk
index 2800f9571..d2388201a 100644
--- a/tools/top.mk
+++ b/tools/top.mk
@@ -25,7 +25,7 @@ endif
 THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
 
 # strip off /tools/top.mk to get for example ../../..
-TOP := $(patsubst %/tools/top.mk,%,$(THIS_MAKEFILE))
+TOP := $(subst /tools/top.mk,,$(THIS_MAKEFILE))
 $(info top.mk: Initial TOP=$(TOP))
 
 # Set TOP to an absolute path, for example /tinyUSB (from ../../..)

From 8a493485e802673a877e43a53c7181a9668c7d51 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 5 Mar 2023 13:39:38 +0700
Subject: [PATCH 1502/2085] more ci test

---
 .github/workflows/build_win_mac.yml | 2 +-
 examples/make.mk                    | 3 +--
 examples/rules.mk                   | 4 ++++
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index c2e961f23..6d4f8ff80 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -44,7 +44,7 @@ jobs:
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
       with:
-        release: '12.2.Rel1'
+        release: '10.3-2021.10'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
diff --git a/examples/make.mk b/examples/make.mk
index 5b364baf7..8a0b6db6b 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -77,10 +77,9 @@ endif
 ifeq ($(CMDEXE),1)
   CP = copy
   RM = del
+  MKDIR = mkdir
   PYTHON = python
-  MKDIR = cmd /e /c mkdir
 else
-  SED = sed
   CP = cp
   RM = rm
   MKDIR = mkdir
diff --git a/examples/rules.mk b/examples/rules.mk
index dcef934ab..06bc593ba 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -265,7 +265,11 @@ debug-bmp: $(BUILD)/$(PROJECT).elf
 
 # Create binary directory
 $(BIN):
+ifeq ($(CMDEXE),1)
+	@$(MKDIR) $(subst /,\,$@)
+else
 	@$(MKDIR) -p $@
+endif
 
 # Copy binaries .elf, .bin, .hex, .uf2 to BIN for upload
 # due to large size of combined artifacts, only uf2 is uploaded for now

From 9824981ee80f38791ec8de2d26ab928a382e852f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 5 Mar 2023 15:35:02 +0700
Subject: [PATCH 1503/2085] ignore mkdir in windows ci

---
 .github/workflows/build_win_mac.yml | 2 +-
 examples/rules.mk                   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index 6d4f8ff80..46aa4a784 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -44,7 +44,7 @@ jobs:
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
       with:
-        release: '10.3-2021.10'
+        release: '11.2-2022.02'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
diff --git a/examples/rules.mk b/examples/rules.mk
index 06bc593ba..76be50b9c 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -112,7 +112,7 @@ OBJ_DIRS = $(sort $(dir $(OBJ)))
 $(OBJ): | $(OBJ_DIRS)
 $(OBJ_DIRS):
 ifeq ($(CMDEXE),1)
-	@$(MKDIR) $(subst /,\,$@)
+	-@$(MKDIR) $(subst /,\,$@)
 else
 	@$(MKDIR) -p $@
 endif

From 0a1a61bb6c921d033fc8bce0718b56e2d334323b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 5 Mar 2023 15:42:05 +0700
Subject: [PATCH 1504/2085] try gcc 12.2 with macos

---
 .github/workflows/build_win_mac.yml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index 46aa4a784..a4b0ad220 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -44,7 +44,7 @@ jobs:
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
       with:
-        release: '11.2-2022.02'
+        release: '12.2.Rel1'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
@@ -53,7 +53,7 @@ jobs:
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
     - name: Get Dependencies
-      run: python3 tools/get_dependencies.py stm32f0
+      run: python3 tools/get_dependencies.py stm32f4
 
     - name: Build
-      run: python3 tools/build_family.py stm32f0 stm32f072disco
+      run: python3 tools/build_family.py stm32f4 stm32f411disco

From 95cfa37bf56ee45f9bdd82e013c44604d29d7cb6 Mon Sep 17 00:00:00 2001
From: Nathaniel Brough <nathaniel.brough@gmail.com>
Date: Sun, 5 Mar 2023 18:47:48 -0800
Subject: [PATCH 1505/2085] fix: Fix wrong destsz used with tu_memcpy_s

Bug: #1935
---
 src/class/audio/audio_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index d9c873851..f21dfee64 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2290,7 +2290,7 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req
   if (len > _audiod_fct[func_id].ctrl_buf_sz) len = _audiod_fct[func_id].ctrl_buf_sz;
 
   // Copy into buffer
-  TU_VERIFY(0 == tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, sizeof(_audiod_fct[func_id].ctrl_buf), data, (size_t)len));
+  TU_VERIFY(0 == tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, _audiod_fct[func_id].ctrl_buf_sz, data, (size_t)len));
 
   // Schedule transmit
   return tud_control_xfer(rhport, p_request, (void*)_audiod_fct[func_id].ctrl_buf, len);

From 956d1c9c4e6c26e1c7de70c1c2e01a5380dd3dfe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Mar 2023 10:33:04 +0700
Subject: [PATCH 1506/2085] update size to fix macos ci

---
 examples/make.mk     |  2 +-
 tools/build_utils.py | 12 +++++++++---
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/examples/make.mk b/examples/make.mk
index 8a0b6db6b..e02d226b6 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -61,7 +61,7 @@ ifdef USE_IAR
   AS = iasmarm
   LD = ilinkarm
   OBJCOPY = ielftool
-  SIZE = echo "size not available for IAR"
+  SIZE = size
 
 else
   CC = $(CROSS_COMPILE)gcc
diff --git a/tools/build_utils.py b/tools/build_utils.py
index ad1daf8c7..0dbfd3356 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -114,9 +114,15 @@ def build_example(example, board, make_option):
 
 
 def build_size(example, board):
-    elf_file = 'examples/{}/_build/{}/*.elf'.format(example, board)
-    size_output = subprocess.run('size {}'.format(elf_file), shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8")
-    size_list = size_output.split('\n')[1].split('\t')
+    size_cmd = 'make -j -C examples/{} BOARD={} size'.format(example, board)
+    size_output = subprocess.run(size_cmd, shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8").splitlines()
+    for i, l in enumerate(size_output):
+        text_title = 'text	   data	    bss	    dec'
+        if text_title in l:
+            size_list = size_output[i+1].split('\t')
+            break
+
     flash_size = int(size_list[0])
     sram_size = int(size_list[1]) + int(size_list[2])
     return (flash_size, sram_size)
+

From 5c537c25f00dad43c4839ba1bffe7d9cd03cc87f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Mar 2023 11:16:21 +0700
Subject: [PATCH 1507/2085] change gcc to 10.3 due to freeRTOS warning

---
 .github/workflows/build_win_mac.yml | 2 +-
 hw/bsp/stm32f1/family.c             | 2 +-
 hw/bsp/stm32f1/stm32f1xx_hal_conf.h | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index a4b0ad220..4b899cfb6 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -44,7 +44,7 @@ jobs:
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
       with:
-        release: '12.2.Rel1'
+        release: '10.3-2021.10'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index 246d496c8..61b40badd 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -151,7 +151,7 @@ void HardFault_Handler (void)
   * @param  line: assert_param error line source number
   * @retval None
   */
-void assert_failed(char *file, uint32_t line)
+void assert_failed(const char *file, uint32_t line)
 { 
   /* USER CODE BEGIN 6 */
   /* User can add his own implementation to report the file name and line number,
diff --git a/hw/bsp/stm32f1/stm32f1xx_hal_conf.h b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
index a4a3f3086..5243e5bca 100644
--- a/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
+++ b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
@@ -362,9 +362,9 @@
   *         If expr is true, it returns no value.
   * @retval None
   */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed(__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+  void assert_failed(const char* file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
 #endif /* USE_FULL_ASSERT */    

From 9930863b412cc4e6b762a1a5aa300d94f2ea0518 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Mar 2023 12:45:47 +0700
Subject: [PATCH 1508/2085] fix iar ci

---
 examples/rules.mk        | 30 +++++++++++++++---------------
 hw/bsp/stm32f0/family.mk |  4 +++-
 hw/bsp/stm32f4/family.mk |  1 +
 hw/bsp/stm32f7/family.mk |  1 +
 hw/bsp/stm32g4/family.mk |  1 +
 hw/bsp/stm32h7/family.mk |  3 +++
 hw/bsp/stm32l4/family.mk |  4 +++-
 tools/build_utils.py     |  9 ++++-----
 8 files changed, 31 insertions(+), 22 deletions(-)

diff --git a/examples/rules.mk b/examples/rules.mk
index 76be50b9c..3254112cf 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -139,7 +139,21 @@ $(BUILD)/obj/%_asm.o: %.S
 	@echo AS $(notdir $@)
 	@$(AS) $(ASFLAGS) -c -o $@ $<
 
-ifndef USE_IAR
+ifdef USE_IAR
+# IAR Compiler
+$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) --silent --bin $^ $@
+
+$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) --silent --ihex $^ $@
+
+$(BUILD)/$(PROJECT).elf: $(OBJ)
+	@echo LINK $@
+	@$(LD) -o $@ $(IAR_LDFLAGS) $^
+
+else
 # GCC based compiler
 $(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
@@ -153,20 +167,6 @@ $(BUILD)/$(PROJECT).elf: $(OBJ)
 	@echo LINK $@
 	@$(LD) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group
 
-else
-
-# IAR Compiler
-$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	@$(OBJCOPY) --silent --bin $^ $@
-
-$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	@$(OBJCOPY) --silent --ihex $^ $@
-
-$(BUILD)/$(PROJECT).elf: $(OBJ)
-	@echo LINK $@
-	@$(LD) -o $@ $(IAR_LDFLAGS) $^
 endif
 
 # UF2 generation, iMXRT need to strip to text only before conversion
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index a065e9221..1ae2aa5fc 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -42,7 +42,9 @@ SRC_C += \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index e8352bad7..860955729 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -42,6 +42,7 @@ SRC_C += \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
 INC += \
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index 781b8bb18..a54e43780 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -52,6 +52,7 @@ SRC_C += \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk
index 79defac56..ad9babf3f 100644
--- a/hw/bsp/stm32g4/family.mk
+++ b/hw/bsp/stm32g4/family.mk
@@ -43,6 +43,7 @@ SRC_C += \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
 INC += \
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index 834347b4b..e1b2cd40e 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -52,10 +52,13 @@ SRC_C += \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c
 
 INC += \
diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index 4fab7dc0d..84aa357e9 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -39,12 +39,14 @@ SRC_C += \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c
 
 INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
diff --git a/tools/build_utils.py b/tools/build_utils.py
index 0dbfd3356..a24cea7bb 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -120,9 +120,8 @@ def build_size(example, board):
         text_title = 'text	   data	    bss	    dec'
         if text_title in l:
             size_list = size_output[i+1].split('\t')
-            break
-
-    flash_size = int(size_list[0])
-    sram_size = int(size_list[1]) + int(size_list[2])
-    return (flash_size, sram_size)
+            flash_size = int(size_list[0])
+            sram_size = int(size_list[1]) + int(size_list[2])
+            return (flash_size, sram_size)
 
+    return (0, 0)
\ No newline at end of file

From b6404d143ed218ad13dce62bd16b9a21de3bba79 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Mar 2023 13:03:55 +0700
Subject: [PATCH 1509/2085] clean up top

---
 tools/top.mk | 21 ++-------------------
 1 file changed, 2 insertions(+), 19 deletions(-)

diff --git a/tools/top.mk b/tools/top.mk
index d2388201a..fdae6337c 100644
--- a/tools/top.mk
+++ b/tools/top.mk
@@ -16,31 +16,14 @@ CMDEXE := 1
 SHELL := cmd.exe
 endif
 
-#$(info top.mk: SHELL=$(SHELL))
-#$(info top.mk: CMDEXE=$(CMDEXE))
-
 # Set TOP to be the path to get from the current directory (where make was
 # invoked) to the top of the tree. $(lastword $(MAKEFILE_LIST)) returns
 # the name of this makefile relative to where make was invoked.
 THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
 
 # strip off /tools/top.mk to get for example ../../..
-TOP := $(subst /tools/top.mk,,$(THIS_MAKEFILE))
-$(info top.mk: Initial TOP=$(TOP))
-
-# Set TOP to an absolute path, for example /tinyUSB (from ../../..)
-ifeq ($(CMDEXE),1)
-TOP := $(subst \,/,$(shell for %%i in ( $(TOP) ) do echo %%~fi))
-else
-TOP := $(abspath $(TOP))
-endif
-
-$(info top.mk: Top directory is $(TOP))
+# and Set TOP to an absolute path
+TOP = $(abspath $(subst /tools/top.mk,,$(THIS_MAKEFILE)))
 
 # Set CURRENT_PATH to the relative path from TOP to the current directory, ie examples/device/cdc_msc_freertos
-ifeq ($(CMDEXE),1)
-CURRENT_PATH := $(subst $(TOP)/,,$(subst \,/,$(shell echo %CD%)))
-else
 CURRENT_PATH = $(subst $(TOP)/,,$(abspath .))
-endif
-$(info top.mk: CURRENT_PATH = $(CURRENT_PATH))

From e62d1a03acfa2a3b8afa0568690fdcad5495c260 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Mar 2023 13:25:56 +0700
Subject: [PATCH 1510/2085] integrate top.mk into make.mk

---
 examples/device/audio_4_channel_mic/Makefile  |   1 -
 examples/device/audio_test/Makefile           |   1 -
 .../device/audio_test_multi_rate/Makefile     |   1 -
 examples/device/board_test/Makefile           |   1 -
 examples/device/cdc_dual_ports/Makefile       |   1 -
 examples/device/cdc_msc/Makefile              |   1 -
 examples/device/cdc_msc_freertos/Makefile     |   1 -
 examples/device/dfu/Makefile                  |   1 -
 examples/device/dfu_runtime/Makefile          |   1 -
 .../device/dynamic_configuration/Makefile     |   1 -
 examples/device/hid_boot_interface/Makefile   |   1 -
 examples/device/hid_composite/Makefile        |   1 -
 .../device/hid_composite_freertos/Makefile    |   1 -
 examples/device/hid_generic_inout/Makefile    |   1 -
 .../device/hid_multiple_interface/Makefile    |   1 -
 examples/device/midi_test/Makefile            |   1 -
 examples/device/msc_dual_lun/Makefile         |   1 -
 examples/device/net_lwip_webserver/Makefile   |   1 -
 examples/device/uac2_headset/Makefile         |   1 -
 examples/device/usbtmc/Makefile               |   1 -
 examples/device/video_capture/Makefile        |   1 -
 examples/device/webusb_serial/Makefile        |   1 -
 examples/dual/host_hid_to_device_cdc/Makefile |   1 -
 examples/host/bare_api/Makefile               |   1 -
 examples/host/cdc_msc_hid/Makefile            |   1 -
 examples/host/hid_controller/Makefile         |   1 -
 examples/host/msc_file_explorer/Makefile      |   1 -
 examples/make.mk                              | 110 +++++++++++-------
 test/fuzz/device/cdc/Makefile                 |   1 -
 test/fuzz/device/msc/Makefile                 |   1 -
 test/fuzz/device/net/Makefile                 |   1 -
 test/fuzz/make.mk                             |  30 ++++-
 tools/top.mk                                  |  29 -----
 33 files changed, 97 insertions(+), 102 deletions(-)
 delete mode 100644 tools/top.mk

diff --git a/examples/device/audio_4_channel_mic/Makefile b/examples/device/audio_4_channel_mic/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/audio_4_channel_mic/Makefile
+++ b/examples/device/audio_4_channel_mic/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/audio_test/Makefile b/examples/device/audio_test/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/audio_test/Makefile
+++ b/examples/device/audio_test/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/audio_test_multi_rate/Makefile b/examples/device/audio_test_multi_rate/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/audio_test_multi_rate/Makefile
+++ b/examples/device/audio_test_multi_rate/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/board_test/Makefile b/examples/device/board_test/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/board_test/Makefile
+++ b/examples/device/board_test/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/cdc_dual_ports/Makefile b/examples/device/cdc_dual_ports/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/cdc_dual_ports/Makefile
+++ b/examples/device/cdc_dual_ports/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/cdc_msc/Makefile b/examples/device/cdc_msc/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/cdc_msc/Makefile
+++ b/examples/device/cdc_msc/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 4ee816880..e2bbc2268 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -1,6 +1,5 @@
 DEPS_SUBMODULES += lib/FreeRTOS-Kernel
 
-include ../../../tools/top.mk
 include ../../make.mk
 
 FREERTOS_SRC = lib/FreeRTOS-Kernel
diff --git a/examples/device/dfu/Makefile b/examples/device/dfu/Makefile
index 5148ed55a..b3f2cc588 100644
--- a/examples/device/dfu/Makefile
+++ b/examples/device/dfu/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/dfu_runtime/Makefile b/examples/device/dfu_runtime/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/dfu_runtime/Makefile
+++ b/examples/device/dfu_runtime/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/dynamic_configuration/Makefile b/examples/device/dynamic_configuration/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/dynamic_configuration/Makefile
+++ b/examples/device/dynamic_configuration/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/hid_boot_interface/Makefile b/examples/device/hid_boot_interface/Makefile
index c6a9c5b21..d58a539e8 100644
--- a/examples/device/hid_boot_interface/Makefile
+++ b/examples/device/hid_boot_interface/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/hid_composite/Makefile b/examples/device/hid_composite/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/hid_composite/Makefile
+++ b/examples/device/hid_composite/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index a354a90b6..099a43893 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -1,6 +1,5 @@
 DEPS_SUBMODULES += lib/FreeRTOS-Kernel
 
-include ../../../tools/top.mk
 include ../../make.mk
 
 FREERTOS_SRC = lib/FreeRTOS-Kernel
diff --git a/examples/device/hid_generic_inout/Makefile b/examples/device/hid_generic_inout/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/hid_generic_inout/Makefile
+++ b/examples/device/hid_generic_inout/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/hid_multiple_interface/Makefile b/examples/device/hid_multiple_interface/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/hid_multiple_interface/Makefile
+++ b/examples/device/hid_multiple_interface/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/midi_test/Makefile b/examples/device/midi_test/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/midi_test/Makefile
+++ b/examples/device/midi_test/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/msc_dual_lun/Makefile b/examples/device/msc_dual_lun/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/msc_dual_lun/Makefile
+++ b/examples/device/msc_dual_lun/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile
index 55bd820bd..bc2914b36 100644
--- a/examples/device/net_lwip_webserver/Makefile
+++ b/examples/device/net_lwip_webserver/Makefile
@@ -1,6 +1,5 @@
 DEPS_SUBMODULES += lib/lwip
 
-include ../../../tools/top.mk
 include ../../make.mk
 
 # suppress warning caused by lwip
diff --git a/examples/device/uac2_headset/Makefile b/examples/device/uac2_headset/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/uac2_headset/Makefile
+++ b/examples/device/uac2_headset/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/usbtmc/Makefile b/examples/device/usbtmc/Makefile
index 69b633fea..da088ea6b 100644
--- a/examples/device/usbtmc/Makefile
+++ b/examples/device/usbtmc/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/device/video_capture/Makefile b/examples/device/video_capture/Makefile
index fda66bcc1..90d174c32 100644
--- a/examples/device/video_capture/Makefile
+++ b/examples/device/video_capture/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 ifeq ($(DISABLE_MJPEG),1)
diff --git a/examples/device/webusb_serial/Makefile b/examples/device/webusb_serial/Makefile
index 5a455078e..2a3d854fb 100644
--- a/examples/device/webusb_serial/Makefile
+++ b/examples/device/webusb_serial/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/dual/host_hid_to_device_cdc/Makefile b/examples/dual/host_hid_to_device_cdc/Makefile
index 3fe9b0888..95c88e7e8 100644
--- a/examples/dual/host_hid_to_device_cdc/Makefile
+++ b/examples/dual/host_hid_to_device_cdc/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/host/bare_api/Makefile b/examples/host/bare_api/Makefile
index 84555a889..058307c40 100644
--- a/examples/host/bare_api/Makefile
+++ b/examples/host/bare_api/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index 9adccfa3a..7c16b39d3 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index e7fbd741f..cda2977bc 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/examples/host/msc_file_explorer/Makefile b/examples/host/msc_file_explorer/Makefile
index de2f9c01c..1fda72b18 100644
--- a/examples/host/msc_file_explorer/Makefile
+++ b/examples/host/msc_file_explorer/Makefile
@@ -1,4 +1,3 @@
-include ../../../tools/top.mk
 include ../../make.mk
 
 FATFS_PATH = lib/fatfs/source
diff --git a/examples/make.mk b/examples/make.mk
index e02d226b6..d91263db9 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -2,6 +2,72 @@
 # Common make definition for all examples
 # ---------------------------------------
 
+#-------------- TOP and CURRENT_PATH ------------
+
+# Set TOP to be the path to get from the current directory (where make was
+# invoked) to the top of the tree. $(lastword $(MAKEFILE_LIST)) returns
+# the name of this makefile relative to where make was invoked.
+THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
+
+# strip off /tools/top.mk to get for example ../../..
+# and Set TOP to an absolute path
+TOP = $(abspath $(subst make.mk,..,$(THIS_MAKEFILE)))
+
+# Set CURRENT_PATH to the relative path from TOP to the current directory, ie examples/device/cdc_msc_freertos
+CURRENT_PATH = $(subst $(TOP)/,,$(abspath .))
+
+# Detect whether shell style is windows or not
+# https://stackoverflow.com/questions/714100/os-detecting-makefile/52062069#52062069
+ifeq '$(findstring ;,$(PATH))' ';'
+# PATH contains semicolon - so we're definitely on Windows.
+CMDEXE := 1
+
+# makefile shell commands should use syntax for DOS CMD, not unix sh
+# Unfortunately, SHELL may point to sh or bash, which can't accept DOS syntax.
+# We can't just use sh, because while sh and/or bash shell may be available,
+# many Windows environments won't have utilities like realpath used below, so...
+# Force DOS command shell on Windows.
+SHELL := cmd.exe
+endif
+
+#-------------- Cross Compiler  ------------
+# Can be set by board, default to ARM GCC
+CROSS_COMPILE ?= arm-none-eabi-
+
+ifeq ($(CC),iccarm)
+USE_IAR = 1
+endif
+
+ifdef USE_IAR
+  AS = iasmarm
+  LD = ilinkarm
+  OBJCOPY = ielftool
+  SIZE = size
+
+else
+  CC = $(CROSS_COMPILE)gcc
+  CXX = $(CROSS_COMPILE)g++
+  AS = $(CC) -x assembler-with-cpp
+  LD = $(CC)
+
+  GDB = $(CROSS_COMPILE)gdb
+  OBJCOPY = $(CROSS_COMPILE)objcopy
+  SIZE = $(CROSS_COMPILE)size
+endif
+
+ifeq ($(CMDEXE),1)
+  CP = copy
+  RM = del
+  MKDIR = mkdir
+  PYTHON = python
+else
+  CP = cp
+  RM = rm
+  MKDIR = mkdir
+  PYTHON = python3
+endif
+
+
 # Build directory
 BUILD := _build/$(BOARD)
 
@@ -45,47 +111,6 @@ else
   SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(FAMILY_PATH)/*.c))
 endif
 
-
-#-------------- Cross Compiler  ------------
-# Can be set by board, default to ARM GCC
-CROSS_COMPILE ?= arm-none-eabi-
-
-# Allow for -Os to be changed by board makefiles in case -Os is not allowed
-CFLAGS_OPTIMIZED ?= -Os
-
-ifeq ($(CC),iccarm)
-USE_IAR = 1
-endif
-
-ifdef USE_IAR
-  AS = iasmarm
-  LD = ilinkarm
-  OBJCOPY = ielftool
-  SIZE = size
-
-else
-  CC = $(CROSS_COMPILE)gcc
-  CXX = $(CROSS_COMPILE)g++
-  AS = $(CC) -x assembler-with-cpp
-  LD = $(CC)
-  
-  GDB = $(CROSS_COMPILE)gdb
-  OBJCOPY = $(CROSS_COMPILE)objcopy
-  SIZE = $(CROSS_COMPILE)size
-endif
-
-ifeq ($(CMDEXE),1)
-  CP = copy
-  RM = del
-  MKDIR = mkdir
-  PYTHON = python
-else
-  CP = cp
-  RM = rm
-  MKDIR = mkdir
-  PYTHON = python3
-endif
-
 #-------------- Source files and compiler flags --------------
 
 # Include all source C in family & board folder
@@ -94,6 +119,9 @@ SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(BOARD_PATH)/*.c))
 
 INC   += $(TOP)/$(FAMILY_PATH)
 
+# Allow for -Os to be changed by board makefiles in case -Os is not allowed
+CFLAGS_OPTIMIZED ?= -Os
+
 # GCC Compiler Flags
 GCC_CFLAGS += \
   -ggdb \
diff --git a/test/fuzz/device/cdc/Makefile b/test/fuzz/device/cdc/Makefile
index ee51936b5..7071df057 100644
--- a/test/fuzz/device/cdc/Makefile
+++ b/test/fuzz/device/cdc/Makefile
@@ -1,4 +1,3 @@
-include ../../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/test/fuzz/device/msc/Makefile b/test/fuzz/device/msc/Makefile
index ee51936b5..7071df057 100644
--- a/test/fuzz/device/msc/Makefile
+++ b/test/fuzz/device/msc/Makefile
@@ -1,4 +1,3 @@
-include ../../../../tools/top.mk
 include ../../make.mk
 
 INC += \
diff --git a/test/fuzz/device/net/Makefile b/test/fuzz/device/net/Makefile
index 22241fcdc..4e99604ad 100644
--- a/test/fuzz/device/net/Makefile
+++ b/test/fuzz/device/net/Makefile
@@ -1,6 +1,5 @@
 DEPS_SUBMODULES += lib/lwip
 
-include ../../../../tools/top.mk
 include ../../make.mk
 
 # suppress warning caused by lwip
diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk
index e7c5518e7..934819665 100644
--- a/test/fuzz/make.mk
+++ b/test/fuzz/make.mk
@@ -2,6 +2,34 @@
 # Common make definition for all examples
 # ---------------------------------------
 
+#-------------- TOP and CURRENT_PATH ------------
+
+# Set TOP to be the path to get from the current directory (where make was
+# invoked) to the top of the tree. $(lastword $(MAKEFILE_LIST)) returns
+# the name of this makefile relative to where make was invoked.
+THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
+
+# strip off /tools/top.mk to get for example ../../..
+# and Set TOP to an absolute path
+TOP = $(abspath $(subst make.mk,../..,$(THIS_MAKEFILE)))
+
+# Set CURRENT_PATH to the relative path from TOP to the current directory, ie examples/device/cdc_msc_freertos
+CURRENT_PATH = $(subst $(TOP)/,,$(abspath .))
+
+# Detect whether shell style is windows or not
+# https://stackoverflow.com/questions/714100/os-detecting-makefile/52062069#52062069
+ifeq '$(findstring ;,$(PATH))' ';'
+# PATH contains semicolon - so we're definitely on Windows.
+CMDEXE := 1
+
+# makefile shell commands should use syntax for DOS CMD, not unix sh
+# Unfortunately, SHELL may point to sh or bash, which can't accept DOS syntax.
+# We can't just use sh, because while sh and/or bash shell may be available,
+# many Windows environments won't have utilities like realpath used below, so...
+# Force DOS command shell on Windows.
+SHELL := cmd.exe
+endif
+
 # Build directory
 BUILD := _build
 PROJECT := $(notdir $(CURDIR))
@@ -42,8 +70,6 @@ SANITIZER_FLAGS ?= -fsanitize=fuzzer \
 CFLAGS += $(COVERAGE_FLAGS) $(SANITIZER_FLAGS)
 
 #-------------- Source files and compiler flags --------------
-
-
 INC += $(TOP)/test
 
 # Compiler Flags
diff --git a/tools/top.mk b/tools/top.mk
deleted file mode 100644
index fdae6337c..000000000
--- a/tools/top.mk
+++ /dev/null
@@ -1,29 +0,0 @@
-ifneq ($(lastword a b),b)
-$(error This Makefile requires make 3.81 or newer)
-endif
-
-# Detect whether shell style is windows or not
-# https://stackoverflow.com/questions/714100/os-detecting-makefile/52062069#52062069
-ifeq '$(findstring ;,$(PATH))' ';'
-# PATH contains semicolon - so we're definitely on Windows.
-CMDEXE := 1
-
-# makefile shell commands should use syntax for DOS CMD, not unix sh
-# Unfortunately, SHELL may point to sh or bash, which can't accept DOS syntax.
-# We can't just use sh, because while sh and/or bash shell may be available,
-# many Windows environments won't have utilities like realpath used below, so...
-# Force DOS command shell on Windows.
-SHELL := cmd.exe
-endif
-
-# Set TOP to be the path to get from the current directory (where make was
-# invoked) to the top of the tree. $(lastword $(MAKEFILE_LIST)) returns
-# the name of this makefile relative to where make was invoked.
-THIS_MAKEFILE := $(lastword $(MAKEFILE_LIST))
-
-# strip off /tools/top.mk to get for example ../../..
-# and Set TOP to an absolute path
-TOP = $(abspath $(subst /tools/top.mk,,$(THIS_MAKEFILE)))
-
-# Set CURRENT_PATH to the relative path from TOP to the current directory, ie examples/device/cdc_msc_freertos
-CURRENT_PATH = $(subst $(TOP)/,,$(abspath .))

From 02478c57e51fcb82c53530a03ca4cca296645f1c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Mar 2023 14:31:18 +0700
Subject: [PATCH 1511/2085] more ci fix

---
 examples/make.mk         | 74 ++++++++++++++++++++--------------------
 hw/bsp/stm32h7/family.mk |  2 +-
 2 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/examples/make.mk b/examples/make.mk
index d91263db9..0a07da21c 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -30,43 +30,6 @@ CMDEXE := 1
 SHELL := cmd.exe
 endif
 
-#-------------- Cross Compiler  ------------
-# Can be set by board, default to ARM GCC
-CROSS_COMPILE ?= arm-none-eabi-
-
-ifeq ($(CC),iccarm)
-USE_IAR = 1
-endif
-
-ifdef USE_IAR
-  AS = iasmarm
-  LD = ilinkarm
-  OBJCOPY = ielftool
-  SIZE = size
-
-else
-  CC = $(CROSS_COMPILE)gcc
-  CXX = $(CROSS_COMPILE)g++
-  AS = $(CC) -x assembler-with-cpp
-  LD = $(CC)
-
-  GDB = $(CROSS_COMPILE)gdb
-  OBJCOPY = $(CROSS_COMPILE)objcopy
-  SIZE = $(CROSS_COMPILE)size
-endif
-
-ifeq ($(CMDEXE),1)
-  CP = copy
-  RM = del
-  MKDIR = mkdir
-  PYTHON = python
-else
-  CP = cp
-  RM = rm
-  MKDIR = mkdir
-  PYTHON = python3
-endif
-
 
 # Build directory
 BUILD := _build/$(BOARD)
@@ -111,6 +74,43 @@ else
   SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(FAMILY_PATH)/*.c))
 endif
 
+#-------------- Cross Compiler  ------------
+# Can be set by board, default to ARM GCC
+CROSS_COMPILE ?= arm-none-eabi-
+
+ifeq ($(CC),iccarm)
+USE_IAR = 1
+endif
+
+ifdef USE_IAR
+  AS = iasmarm
+  LD = ilinkarm
+  OBJCOPY = ielftool
+  SIZE = size
+
+else
+  CC = $(CROSS_COMPILE)gcc
+  CXX = $(CROSS_COMPILE)g++
+  AS = $(CC) -x assembler-with-cpp
+  LD = $(CC)
+
+  GDB = $(CROSS_COMPILE)gdb
+  OBJCOPY = $(CROSS_COMPILE)objcopy
+  SIZE = $(CROSS_COMPILE)size
+endif
+
+ifeq ($(CMDEXE),1)
+  CP = copy
+  RM = del
+  MKDIR = mkdir
+  PYTHON = python
+else
+  CP = cp
+  RM = rm
+  MKDIR = mkdir
+  PYTHON = python3
+endif
+
 #-------------- Source files and compiler flags --------------
 
 # Include all source C in family & board folder
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index e1b2cd40e..9989b17a8 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -37,7 +37,7 @@ GCC_CFLAGS += \
   -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
-GCC_CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
+GCC_CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=unused-parameter
 
 # IAR Flags
 IAR_CFLAGS += --cpu cortex-m7 --fpu VFPv5_D16

From ec8c292bbebdbaebe39abef6e88c6a0fbb1f2be7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Mar 2023 14:37:40 +0700
Subject: [PATCH 1512/2085] clean up

---
 .github/workflows/build_win_mac.yml | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index 4b899cfb6..bad9f3162 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -38,9 +38,6 @@ jobs:
       with:
         python-version: '3.x'
 
-    - if: matrix.os == 'macos-latest'
-      run: uname -a
-
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
       with:

From 9e0ae5f29d507e29b7c548eb4b1aa1ca019de65b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Mar 2023 12:15:39 +0700
Subject: [PATCH 1513/2085] improve ci

---
 .github/workflows/build_arm.yml | 34 +++++++++++----------------------
 examples/rules.mk               |  1 +
 tools/build_utils.py            | 16 ++++++++--------
 3 files changed, 20 insertions(+), 31 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 96c337462..b598eff2a 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -34,10 +34,8 @@ jobs:
         # Alphabetical order
         - 'broadcom_32bit'
         - 'imxrt'
-        - 'lpc15'
-        - 'lpc18'
-        - 'lpc54'
-        - 'lpc55'
+        - 'lpc15 lpc18'
+        - 'lpc54 lpc55' 
         - 'mm32'
         - 'msp432e4'
         - 'nrf'
@@ -46,14 +44,12 @@ jobs:
         - 'samd21'
         - 'samd51'
         - 'saml2x'
-        - 'stm32f0'
-        - 'stm32f1'
+        - 'stm32f0 stm32f1'
         - 'stm32f4'
         - 'stm32f7'
-        - 'stm32g4'
+        - 'stm32g4 stm32wb'
         - 'stm32h7'
         - 'stm32l4'
-        - 'stm32wb'
         - 'tm4c123'
         - 'xmc4000'
     steps:
@@ -71,7 +67,7 @@ jobs:
       uses: actions/checkout@v3
 
     - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
+      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
     - name: Checkout hathach/linkermap
       uses: actions/checkout@v3
@@ -100,29 +96,21 @@ jobs:
           find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
         done
 
-    # Upload binaries for rp2040 hardware test with self-hosted
+    # Upload binaries for rp2040/stm32l412nucleo hardware test with self-hosted
+    
     - name: Prepare rp2040 Artifacts
       if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
       run: find examples/ -name "*.elf" -exec mv {} . \;
 
-    - name: Upload rp2040 Artifacts
-      if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
-      uses: actions/upload-artifact@v3
-      with:
-        name: ${{ matrix.family }}
-        path: |
-          *.elf
-
-    # Upload binaries for stm32l412nucleo hardware test with self-hosted
     - name: Prepare stm32l412nucleo Artifacts
       if: matrix.family == 'stm32l4'
       run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
 
-    - name: Upload stm32l412nucleo Artifacts
-      if: matrix.family == 'stm32l4'
+    - name: Upload Artifacts for hardware testing
+      if: matrix.family == 'stm32l4' || (matrix.family == 'rp2040' && github.repository_owner == 'hathach')
       uses: actions/upload-artifact@v3
       with:
-        name: stm32l412nucleo
+        name: ${{ matrix.family }}
         path: |
           *.elf
 
@@ -244,7 +232,7 @@ jobs:
     - name: Download stm32l4 Artifacts
       uses: actions/download-artifact@v3
       with:
-        name: stm32l412nucleo
+        name: stm32l4
 
     - name: Create flash.sh
       run: |
diff --git a/examples/rules.mk b/examples/rules.mk
index 3254112cf..7f3535bba 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -196,6 +196,7 @@ get-deps:
 	git -C $(TOP) submodule update --init $(DEPS_SUBMODULES)
   endif
 
+.PHONY: size
 size: $(BUILD)/$(PROJECT).elf
 	-@echo ''
 	@$(SIZE) $<
diff --git a/tools/build_utils.py b/tools/build_utils.py
index a24cea7bb..de9052d2d 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -85,21 +85,22 @@ def build_example(example, board, make_option):
     # succeeded, failed, skipped
     ret = [0, 0, 0]
 
+    make_cmd = "make -j -C examples/{} BOARD={} {}".format(example, board, make_option)
+
     # Check if board is skipped
     if skip_example(example, board):
         status = SKIPPED
         ret[2] = 1
         print(build_format.format(example, board, status, '-', flash_size, sram_size))
     else:
-        build_result = subprocess.run("make -j -C examples/{} BOARD={} {} all".format(example, board, make_option), shell=True,
-                                      stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        subprocess.run(make_cmd + " clean", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        build_result = subprocess.run(make_cmd + " all", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
 
         if build_result.returncode == 0:
             status = SUCCEEDED
             ret[0] = 1
-            (flash_size, sram_size) = build_size(example, board)
-            subprocess.run("make -j -C examples/{} BOARD={} {} copy-artifact".format(example, board, make_option), shell=True,
-                           stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+            (flash_size, sram_size) = build_size(make_cmd)
+            #subprocess.run(make_cmd + " copy-artifact", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
         else:
             status = FAILED
             ret[1] = 1
@@ -113,9 +114,8 @@ def build_example(example, board, make_option):
     return ret
 
 
-def build_size(example, board):
-    size_cmd = 'make -j -C examples/{} BOARD={} size'.format(example, board)
-    size_output = subprocess.run(size_cmd, shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8").splitlines()
+def build_size(make_cmd):
+    size_output = subprocess.run(make_cmd + ' size', shell=True, stdout=subprocess.PIPE).stdout.decode("utf-8").splitlines()
     for i, l in enumerate(size_output):
         text_title = 'text	   data	    bss	    dec'
         if text_title in l:

From 0957902c40633a21e7174cc4d59e6c4b34d1d52a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Mar 2023 12:28:30 +0700
Subject: [PATCH 1514/2085] more ci merge

---
 .github/workflows/build_arm.yml | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index b598eff2a..b1b88ec70 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -35,9 +35,8 @@ jobs:
         - 'broadcom_32bit'
         - 'imxrt'
         - 'lpc15 lpc18'
-        - 'lpc54 lpc55' 
-        - 'mm32'
-        - 'msp432e4'
+        - 'lpc54 lpc55'
+        - 'mm32 msp432e4'
         - 'nrf'
         - 'rp2040'
         - 'samd11'
@@ -50,8 +49,7 @@ jobs:
         - 'stm32g4 stm32wb'
         - 'stm32h7'
         - 'stm32l4'
-        - 'tm4c123'
-        - 'xmc4000'
+        - 'tm4c123 xmc4000'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
@@ -97,7 +95,7 @@ jobs:
         done
 
     # Upload binaries for rp2040/stm32l412nucleo hardware test with self-hosted
-    
+
     - name: Prepare rp2040 Artifacts
       if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
       run: find examples/ -name "*.elf" -exec mv {} . \;

From 410ad4d0f9ff166610655bae31328e4120b17ef2 Mon Sep 17 00:00:00 2001
From: Hubert Denkmair <xor@xor.wtf>
Date: Wed, 8 Mar 2023 12:05:58 +0100
Subject: [PATCH 1515/2085] add basic STM32G0 support

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |  86 +++++++--
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   | 180 +++++++++++++-----
 2 files changed, 198 insertions(+), 68 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index e49c0b52e..21ae8e6e8 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -216,7 +216,7 @@ TU_ATTR_ALWAYS_INLINE static inline void reg16_clear_bits(__IO uint16_t *reg, ui
 }
 
 // Bits in ISTR are cleared upon writing 0
-TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits(uint16_t mask) {
+TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits(uint32_t mask) {
   USB->ISTR = ~mask;
 }
 
@@ -242,16 +242,23 @@ void dcd_init (uint8_t rhport)
   {
     asm("NOP");
   }
+
+#ifdef PMA_32BIT_ACCESS // CNTR register is 32bits on STM32G0, 16bit on older versions
+  USB->CNTR &= ~USB_CNTR_PDWN;
+#else
   reg16_clear_bits(&USB->CNTR, USB_CNTR_PDWN);// Remove powerdown
+#endif
+
   // Wait startup time, for F042 and F070, this is <= 1 us.
   for(uint32_t i = 0; i<200; i++) // should be a few us
   {
     asm("NOP");
   }
   USB->CNTR = 0; // Enable USB
-  
-  USB->BTABLE = DCD_STM32_BTABLE_BASE;
 
+#ifndef STM32G0 // BTABLE register does not exist any more on STM32G0, it is fixed to USB SRAM base address
+  USB->BTABLE = DCD_STM32_BTABLE_BASE;
+#endif
   USB->ISTR = 0; // Clear pending interrupts
 
   // Reset endpoints to disabled
@@ -312,7 +319,7 @@ void dcd_sof_enable(uint8_t rhport, bool en)
   }
   else
   {
-    USB->CNTR &= (uint16_t) ~USB_CNTR_SOFM;
+    USB->CNTR &= ~USB_CNTR_SOFM;
   }
 }
 
@@ -358,6 +365,9 @@ void dcd_int_enable (uint8_t rhport)
   NVIC_EnableIRQ(USB_LP_IRQn);
   NVIC_EnableIRQ(USBWakeUp_IRQn);
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
+  NVIC_EnableIRQ(USB_UCPD1_2_IRQn);
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   NVIC_EnableIRQ(USB_HP_IRQn);
   NVIC_EnableIRQ(USB_LP_IRQn);
@@ -405,6 +415,9 @@ void dcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USB_LP_IRQn);
   NVIC_DisableIRQ(USBWakeUp_IRQn);
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
+  NVIC_DisableIRQ(USB_UCPD1_2_IRQn);
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   NVIC_DisableIRQ(USB_HP_IRQn);
   NVIC_DisableIRQ(USB_LP_IRQn);
@@ -433,7 +446,7 @@ void dcd_remote_wakeup(uint8_t rhport)
 {
   (void) rhport;
 
-  USB->CNTR |= (uint16_t) USB_CNTR_RESUME;
+  USB->CNTR |= USB_CNTR_RESUME;
   remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms.
 }
 
@@ -534,9 +547,6 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
   
   if((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */
   {
-    // The setup_received function uses memcpy, so this must first copy the setup data into
-    // user memory, to allow for the 32-bit access that memcpy performs.
-    uint8_t userMemBuf[8];
     uint32_t count = pcd_get_ep_rx_cnt(USB, EPindex);
     /* Get SETUP Packet*/
     if(count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again.
@@ -544,8 +554,15 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
       // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
       pcd_set_ep_rx_status(USB,0u,USB_EP_RX_NAK);
       pcd_set_ep_tx_status(USB,0u,USB_EP_TX_NAK);
-      dcd_read_packet_memory(userMemBuf, *pcd_ep_rx_address_ptr(USB,EPindex), 8);
+#ifdef PMA_32BIT_ACCESS
+      dcd_event_setup_received(0, (uint8_t*)(USB_PMAADDR + pcd_get_ep_rx_address(USB, EPindex)), true);
+#else
+      // The setup_received function uses memcpy, so this must first copy the setup data into
+      // user memory, to allow for the 32-bit access that memcpy performs.
+      uint8_t userMemBuf[8];
+      dcd_read_packet_memory(userMemBuf, pcd_get_ep_rx_address(USB,EPindex), 8);
       dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
+#endif
     }
   }
   else
@@ -568,7 +585,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
 
     if (count != 0U)
     {
-      uint16_t addr = *pcd_ep_rx_address_ptr(USB, EPindex);
+      uint16_t addr = pcd_get_ep_rx_address(USB, EPindex);
 
       if (xfer->ff)
       {
@@ -672,8 +689,13 @@ void dcd_int_handler(uint8_t rhport) {
 
   if (int_status & USB_ISTR_WKUP)
   {
+#ifdef PMA_32BIT_ACCESS // CNTR register is 32bits on STM32G0, 16bit on older versions
+    USB->CNTR &= ~USB_CNTR_LPMODE;
+    USB->CNTR &= ~USB_CNTR_FSUSP;
+#else
     reg16_clear_bits(&USB->CNTR, USB_CNTR_LPMODE);
     reg16_clear_bits(&USB->CNTR, USB_CNTR_FSUSP);
+#endif
     clear_istr_bits(USB_ISTR_WKUP);
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
   }
@@ -695,7 +717,7 @@ void dcd_int_handler(uint8_t rhport) {
   if(int_status & USB_ISTR_ESOF) {
     if(remoteWakeCountdown == 1u)
     {
-      USB->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
+      USB->CNTR &= ~USB_CNTR_RESUME;
     }
     if(remoteWakeCountdown > 0u)
     {
@@ -722,8 +744,13 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
     uint8_t const dev_addr = (uint8_t) request->wValue;
 
     // Setting new address after the whole request is complete
+#ifdef PMA_32BIT_ACCESS
+    USB->DADDR &= ~USB_DADDR_ADD;
+    USB->DADDR = (USB->DADDR & ~USB_DADDR_ADD_Msk) | dev_addr; // leave the enable bit set
+#else
     reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD);
     USB->DADDR = (uint16_t)(USB->DADDR | dev_addr); // leave the enable bit set
+#endif
   }
 }
 
@@ -925,14 +952,14 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
 
   if( (dir == TUSB_DIR_IN) || (wType == USB_EP_ISOCHRONOUS) )
   {
-    *pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr;
+    pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
     pcd_set_ep_tx_bufsize(USB, ep_idx, buffer_size);
     pcd_clear_tx_dtog(USB, ep_idx);
   }
 
   if( (dir == TUSB_DIR_OUT) || (wType == USB_EP_ISOCHRONOUS) )
   {
-    *pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr;
+    pcd_set_ep_rx_address(USB, ep_idx, pma_addr);
     pcd_set_ep_rx_bufsize(USB, ep_idx, buffer_size);
     pcd_clear_rx_dtog(USB, ep_idx);
   }
@@ -1011,10 +1038,10 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
   xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
 
   pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS);
-  
-  *pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr;
-  *pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr;
-  
+
+  pcd_set_ep_tx_address(USB, ep_idx, pma_addr);
+  pcd_set_ep_rx_address(USB, ep_idx, pma_addr);
+
   return true;
 }
 
@@ -1063,7 +1090,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
   }
 
   uint16_t ep_reg = pcd_get_endpoint(USB, ep_ix);
-  uint16_t addr_ptr = *pcd_ep_tx_address_ptr(USB,ep_ix);
+  uint16_t addr_ptr = pcd_get_ep_tx_address(USB, ep_ix);
 
   if (xfer->ff)
   {
@@ -1197,6 +1224,19 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   }
 }
 
+#ifdef PMA_32BIT_ACCESS
+static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
+{
+  // FIXME original function uses byte-access to source memory (to support non-aligned buffers)
+  const uint32_t* src32 = (uint32_t*)(src);
+  uint32_t* dst32 = (uint32_t*)(USB_PMAADDR + dst);
+  for (unsigned n=wNBytes/4; n>0; --n) {
+    *dst32++ = *src32++;
+  }
+  *dst32 = (*src32) & ((1<<8*(wNBytes % 4)) - 1);
+  return true;
+}
+#else
 // Packet buffer access can only be 8- or 16-bit.
 /**
   * @brief Copy a buffer from user memory area to packet memory area (PMA).
@@ -1239,6 +1279,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
 
   return true;
 }
+#endif
 
 /**
   * @brief Copy from FIFO to packet memory area (PMA).
@@ -1290,6 +1331,14 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
   return true;
 }
 
+#ifdef PMA_32BIT_ACCESS
+static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes)
+{
+    // FIXME this should probably be modified for possible unaligned access?
+    memcpy(dst, (void*)(USB_PMAADDR+src), wNBytes);
+    return true;
+}
+#else
 /**
   * @brief Copy a buffer from packet memory area (PMA) to user memory area.
   *        Uses byte-access of system memory and 16-bit access of packet memory
@@ -1323,6 +1372,7 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
   }
   return true;
 }
+#endif
 
 /**
   * @brief Copy a buffer from user packet memory area (PMA) to FIFO.
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 015b177cf..686bfaa66 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -82,6 +82,34 @@
   #include "stm32g4xx.h"
   #define PMA_LENGTH (1024u)
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
+  #include "STM32/stm32g0xx.h"
+  #define PMA_32BIT_ACCESS
+  #define PMA_LENGTH (1024u) // FIXME it is 2048, really
+  #undef USB_PMAADDR
+  #define USB_PMAADDR USB_DRD_PMAADDR
+  #define USB_TypeDef USB_DRD_TypeDef
+  #define EP0R CHEP0R
+  #define USB_EP_CTR_RX USB_EP_VTRX
+  #define USB_EP_CTR_TX USB_EP_VTTX
+  #define USB_EP_T_FIELD USB_CHEP_UTYPE
+  #define USB_EPREG_MASK USB_CHEP_REG_MASK
+  #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK
+  #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK
+  #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1
+  #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2
+  #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1
+  #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2
+  #define USB_EPRX_STAT USB_CH_RX_VALID
+  #define USB_EPKIND_MASK USB_EP_KIND_MASK
+  #define USB USB_DRD_FS
+  #define USB_CNTR_FRES USB_CNTR_USBRST
+  #define USB_CNTR_RESUME USB_CNTR_L2RES
+  #define USB_ISTR_EP_ID USB_ISTR_IDN
+  #define USB_EPADDR_FIELD USB_CHEP_ADDR
+  #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY
+  #define USB_CNTR_FSUSP USB_CNTR_SUSPEN
+
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   #include "stm32wbxx.h"
   #define PMA_LENGTH (1024u)
@@ -105,15 +133,31 @@
   #define PMA_STRIDE  (1u)
 #endif
 
-// And for type-safety create a new macro for the volatile address of PMAADDR
+// For type-safety create a new macro for the volatile address of PMAADDR
 // The compiler should warn us if we cast it to a non-volatile type?
+#ifdef PMA_32BIT_ACCESS
+static __IO uint32_t * const pma32 = (__IO uint32_t*)USB_PMAADDR;
+#else
 // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
 static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
 
-// prototypes
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx);
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx);
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue);
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
+{
+  size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
+  total_word_offset *= PMA_STRIDE;
+  return &(pma[total_word_offset]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
+{
+  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
+{
+  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u);
+}
+#endif
 
 /* Aligned buffer size according to hardware */
 TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t size)
@@ -131,13 +175,22 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t si
 /* SetENDPOINT */
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue)
 {
+#ifdef PMA_32BIT_ACCESS
+  __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4);
+  *reg = wRegValue;
+#else
   __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
   *reg = (uint16_t)wRegValue;
+#endif
 }
 
 /* GetENDPOINT */
-TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) {
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) {
+#ifdef PMA_32BIT_ACCESS
+  __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4);
+#else
   __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
+#endif
   return *reg;
 }
 
@@ -187,34 +240,22 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx,
   */
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
+#ifdef PMA_32BIT_ACCESS
+  return (pma32[2*bEpIdx] & 0x03FF0000) >> 16;
+#else
   __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
   return *regPtr & 0x3ffU;
+#endif
 }
 
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
+#ifdef PMA_32BIT_ACCESS
+  return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16;
+#else
   __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
   return *regPtr & 0x3ffU;
-}
-
-/**
-  * @brief  Sets counter of rx buffer with no. of blocks.
-  * @param  dwReg Register
-  * @param  wCount Counter.
-  * @param  wNBlocks no. of Blocks.
-  * @retval None
-  */
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_cnt_reg(__O uint16_t * pdwReg, size_t wCount)
-{
-  /* We assume that the buffer size is already aligned to hardware requirements. */
-  uint16_t blocksize = (wCount > 62) ? 1 : 0;
-  uint16_t numblocks = wCount / (blocksize ? 32 : 2);
-
-  /* There should be no remainder in the above calculation */
-  TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/);
-
-  /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
-  *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10);
+#endif
 }
 
 /**
@@ -233,57 +274,96 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,
   pcd_set_endpoint(USBx, bEpIdx,regVal);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  size_t total_word_offset = (((USBx)->BTABLE)>>1) + x;
-  total_word_offset *= PMA_STRIDE;
-  return &(pma[total_word_offset]);
+#ifdef PMA_32BIT_ACCESS
+  return pma32[2*bEpIdx] & 0x0000FFFFu ;
+#else
+  return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u);
+#endif
 }
 
-// Pointers to the PMA table entries (using the ARM address space)
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
+TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
-  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u);
-}
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
-{
-  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 1u);
+#ifdef PMA_32BIT_ACCESS
+  return pma32[2*bEpIdx + 1] & 0x0000FFFFu;
+#else
+  return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u);
+#endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr)
 {
-  return  pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u);
+#ifdef PMA_32BIT_ACCESS
+  pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
+#else
+  *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u) = addr;
+#endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpIdx)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr)
 {
-  return pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 3u);
+#ifdef PMA_32BIT_ACCESS
+  pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
+#else
+  *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u) = addr;
+#endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
 {
+#ifdef PMA_32BIT_ACCESS
+  pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
+#else
   __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
   *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
+#endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
 {
+#ifdef PMA_32BIT_ACCESS
+  pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
+#else
   __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
   *reg = (uint16_t) (*reg & (uint16_t) ~0x3FFU) | (wCount & 0x3FFU);
+#endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t blocksize, uint32_t numblocks)
 {
-  __IO uint16_t *pdwReg = pcd_ep_tx_cnt_ptr((USBx),(bEpIdx));
-  wCount = pcd_aligned_buffer_size(wCount);
-  pcd_set_ep_cnt_reg(pdwReg, wCount);
+  /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
+#ifdef PMA_32BIT_ACCESS
+  pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26);
+#else
+  __IO uint16_t *pdwReg = pcd_btable_word_ptr(USBx, rxtx_idx*2u + 1u);
+  *pdwReg = (blocksize << 15) | ((numblocks - blocksize) << 10);
+#endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx,  uint32_t bEpIdx, uint32_t wCount)
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_bufsize(USB_TypeDef * USBx, uint32_t rxtx_idx, uint32_t wCount)
 {
-  __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpIdx));
   wCount = pcd_aligned_buffer_size(wCount);
-  pcd_set_ep_cnt_reg(pdwReg, wCount);
+
+  /* We assume that the buffer size is already aligned to hardware requirements. */
+  uint16_t blocksize = (wCount > 62) ? 1 : 0;
+  uint16_t numblocks = wCount / (blocksize ? 32 : 2);
+
+  /* There should be no remainder in the above calculation */
+  TU_ASSERT((wCount - (numblocks * (blocksize ? 32 : 2))) == 0, /**/);
+
+  /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
+  pcd_set_ep_blsize_num_blocks(USBx, rxtx_idx, blocksize, numblocks);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
+{
+  pcd_set_ep_bufsize(USBx, 2*bEpIdx, wCount);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_bufsize(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
+{
+  pcd_set_ep_bufsize(USBx, 2*bEpIdx + 1, wCount);
 }
 
 /**

From 8ae4f8f0699351e5bba349ccb0fab65b557afed6 Mon Sep 17 00:00:00 2001
From: Hubert Denkmair <xor@xor.wtf>
Date: Wed, 8 Mar 2023 12:05:58 +0100
Subject: [PATCH 1516/2085] add basic STM32G0 support

---
 src/common/tusb_mcu.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 257d08a85..957df5e9e 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -191,6 +191,11 @@
   #define TUP_USBIP_FSDEV_STM32
   #define TUP_DCD_ENDPOINT_MAX    8
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32G0)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define TUP_DCD_ENDPOINT_MAX    8
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32

From b3ad560e629be18146fd52e32235cc2ed72dc70b Mon Sep 17 00:00:00 2001
From: Hubert Denkmair <xor@xor.wtf>
Date: Wed, 8 Mar 2023 14:22:11 +0100
Subject: [PATCH 1517/2085] fix path to stm32g0xx.h

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 686bfaa66..00791eeb7 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -83,7 +83,7 @@
   #define PMA_LENGTH (1024u)
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
-  #include "STM32/stm32g0xx.h"
+  #include "stm32g0xx.h"
   #define PMA_32BIT_ACCESS
   #define PMA_LENGTH (1024u) // FIXME it is 2048, really
   #undef USB_PMAADDR

From af577d2b6dc9523dc348b36e9e753adc00aec974 Mon Sep 17 00:00:00 2001
From: Hubert Denkmair <xor@xor.wtf>
Date: Wed, 8 Mar 2023 14:25:30 +0100
Subject: [PATCH 1518/2085] add G0 to supported platforms in README.rst :)

---
 README.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index 7825a1b0a..4f7546482 100644
--- a/README.rst
+++ b/README.rst
@@ -51,7 +51,7 @@ The stack supports the following MCUs:
 - **Renesas:** RX63N, RX65N, RX72N
 - **Silabs:** EFM32GG
 - **Sony:** CXD56
-- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G4, L0, L1, L4, L4+, WB
+- **ST:** STM32 series: F0, F1, F2, F3, F4, F7, H7, G0, G4, L0, L1, L4, L4+, WB
 - **TI:** MSP430, MSP432E4, TM4C123
 - **ValentyUSB:** eptri
 - **WCH:** CH32V307

From 2cf092464b5cfabcd0a5e507459e5658e2e0ff54 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Mar 2023 22:34:54 +0700
Subject: [PATCH 1519/2085] fix freertos build with iar, format/indent
 link_type

---
 .codespell/exclude-file.txt                   |    5 +-
 examples/device/cdc_msc_freertos/Makefile     |    2 +-
 .../device/hid_composite_freertos/Makefile    |    2 +-
 src/portable/renesas/link/link_type.h         | 1847 +++++++++--------
 4 files changed, 952 insertions(+), 904 deletions(-)

diff --git a/.codespell/exclude-file.txt b/.codespell/exclude-file.txt
index af8265cc7..660d2e07e 100644
--- a/.codespell/exclude-file.txt
+++ b/.codespell/exclude-file.txt
@@ -1 +1,4 @@
-  return USB0.INTSTS1.BIT.ATTCH ? true : false;
+  return LINK_REG->INTSTS1_b.ATTCH ? true : false;
+      volatile uint16_t ATTCH     : 1; /* [11..11] ATTCH Interrupt Status */
+#define LINK_REG_INTSTS1_ATTCH_Pos         (11UL)       /* ATTCH (Bit 11) */
+#define LINK_REG_INTSTS1_ATTCH_Msk         (0x800UL)    /* ATTCH (Bitfield-Mask: 0x01) */
diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 2d5d0cfcc..ed3b3f0ce 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -30,7 +30,7 @@ SRC_C += \
 	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c))
 
 SRC_S += \
-	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.s))
 
 # include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
 # SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index 9b9c4d1b3..f4410b202 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -29,7 +29,7 @@ SRC_C += \
 	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c))
 
 SRC_S += \
-	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.s))
 
 # include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
 # SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/link/link_type.h
index eaf0b1ec4..cb3db650a 100644
--- a/src/portable/renesas/link/link_type.h
+++ b/src/portable/renesas/link/link_type.h
@@ -62,25 +62,23 @@ typedef struct TU_ATTR_PACKED {
   };
 } LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */
 
-TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size");
-
 /* LINK_REG Structure */
 typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
 
     struct {
-      volatile uint16_t USBE : 1; /* [0..0] USB Operation Enable */
-      uint16_t : 2;
+      volatile uint16_t USBE  : 1; /* [0..0] USB Operation Enable */
+      uint16_t                : 2;
       volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */
       volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
-      volatile uint16_t DRPD : 1;  /* [5..5] D+/D- Line Resistor Control */
-      volatile uint16_t DCFM : 1;  /* [6..6] Controller Function Select */
-      uint16_t : 1;
-      volatile uint16_t CNEN : 1; /* [8..8] CNEN Single End Receiver Enable */
-      uint16_t : 1;
-      volatile uint16_t SCKE : 1; /* [10..10] USB Clock Enable */
-      uint16_t : 5;
+      volatile uint16_t DRPD  : 1; /* [5..5] D+/D- Line Resistor Control */
+      volatile uint16_t DCFM  : 1; /* [6..6] Controller Function Select */
+      uint16_t                : 1;
+      volatile uint16_t CNEN  : 1; /* [8..8] CNEN Single End Receiver Enable */
+      uint16_t                : 1;
+      volatile uint16_t SCKE  : 1; /* [10..10] USB Clock Enable */
+      uint16_t                : 5;
     } SYSCFG_b;
   };
 
@@ -88,8 +86,7 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */
 
     struct {
-      volatile uint16_t
-        BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
+      volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
       uint16_t : 12;
     } BUSWAIT_b;
   };
@@ -98,15 +95,14 @@ typedef struct TU_ATTR_PACKED {
     volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */
 
     struct {
-      volatile const uint16_t LNST : 2;  /* [1..0] USB Data Line Status Monitor */
-      volatile const uint16_t IDMON : 1; /* [2..2] External ID0 Input Pin Monitor */
-      uint16_t : 2;
+      volatile const uint16_t LNST   : 2; /* [1..0] USB Data Line Status Monitor */
+      volatile const uint16_t IDMON  : 1; /* [2..2] External ID0 Input Pin Monitor */
+      uint16_t                       : 2;
       volatile const uint16_t
-        SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
-      volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */
-      uint16_t : 7;
-      volatile const uint16_t
-        OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
+        SOFEA                        : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
+      volatile const uint16_t HTACT  : 1; /* [6..6] USB Host Sequencer Status Monitor */
+      uint16_t                       : 7;
+      volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
     } SYSSTS0_b;
   };
 
@@ -124,16 +120,16 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */
-      uint16_t : 1;
-      volatile uint16_t UACT : 1;    /* [4..4] USB Bus Enable */
-      volatile uint16_t RESUME : 1;  /* [5..5] Resume Output */
-      volatile uint16_t USBRST : 1;  /* [6..6] USB Bus Reset Output */
-      volatile uint16_t RWUPE : 1;   /* [7..7] Wakeup Detection Enable */
-      volatile uint16_t WKUP : 1;    /* [8..8] Wakeup Output */
-      volatile uint16_t VBUSEN : 1;  /* [9..9] USB_VBUSEN Output Pin Control */
-      volatile uint16_t EXICEN : 1;  /* [10..10] USB_EXICEN Output Pin Control */
-      volatile uint16_t HNPBTOA : 1; /* [11..11] Host Negotiation Protocol (HNP) */
-      uint16_t : 4;
+      uint16_t                     : 1;
+      volatile uint16_t UACT       : 1; /* [4..4] USB Bus Enable */
+      volatile uint16_t RESUME     : 1; /* [5..5] Resume Output */
+      volatile uint16_t USBRST     : 1; /* [6..6] USB Bus Reset Output */
+      volatile uint16_t RWUPE      : 1; /* [7..7] Wakeup Detection Enable */
+      volatile uint16_t WKUP       : 1; /* [8..8] Wakeup Output */
+      volatile uint16_t VBUSEN     : 1; /* [9..9] USB_VBUSEN Output Pin Control */
+      volatile uint16_t EXICEN     : 1; /* [10..10] USB_EXICEN Output Pin Control */
+      volatile uint16_t HNPBTOA    : 1; /* [11..11] Host Negotiation Protocol (HNP) */
+      uint16_t                     : 4;
     } DVSTCTR0_b;
   };
   volatile const uint16_t RESERVED;
@@ -214,15 +210,15 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */
-      uint16_t : 1;
-      volatile uint16_t ISEL : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */
-      uint16_t : 2;
-      volatile uint16_t BIGEND : 1; /* [8..8] CFIFO Port Endian Control */
-      uint16_t : 1;
-      volatile uint16_t MBW : 2; /* [11..10] CFIFO Port Access Bit Width */
-      uint16_t : 2;
-      volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
-      volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+      uint16_t                  : 1;
+      volatile uint16_t ISEL    : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */
+      uint16_t                  : 2;
+      volatile uint16_t BIGEND  : 1; /* [8..8] CFIFO Port Endian Control */
+      uint16_t                  : 1;
+      volatile uint16_t MBW     : 2; /* [11..10] CFIFO Port Access Bit Width */
+      uint16_t                  : 2;
+      volatile uint16_t REW     : 1; /* [14..14] Buffer Pointer Rewind */
+      volatile uint16_t RCNT    : 1; /* [15..15] Read Count Mode */
     } CFIFOSEL_b;
   };
 
@@ -230,12 +226,11 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */
 
     struct {
-      volatile const uint16_t
-        DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
-      uint16_t : 1;
-      volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
-      volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-      volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+      volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t                     : 1;
+      volatile const uint16_t FRDY : 1;  /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR       : 1;	 /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL       : 1;	 /* [15..15] Buffer Memory Valid Flag */
     } CFIFOCTR_b;
   };
   volatile const uint32_t RESERVED6;
@@ -245,15 +240,14 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
-      uint16_t : 4;
-      volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
-      uint16_t : 1;
-      volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
-      volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
-      volatile uint16_t
-        DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
-      volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
-      volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+      uint16_t                  : 4;
+      volatile uint16_t BIGEND  : 1; /* [8..8] FIFO Port Endian Control */
+      uint16_t                  : 1;
+      volatile uint16_t MBW     : 2; /* [11..10] FIFO Port Access Bit Width */
+      volatile uint16_t DREQE   : 1; /* [12..12] DMA/DTC Transfer Request Enable */
+      volatile uint16_t DCLRM   : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
+      volatile uint16_t REW     : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
+      volatile uint16_t RCNT    : 1; /* [15..15] Read Count Mode */
     } D0FIFOSEL_b;
   };
 
@@ -261,12 +255,11 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */
 
     struct {
-      volatile const uint16_t
-        DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
-      uint16_t : 1;
-      volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
-      volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-      volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+      volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t                     : 1;
+      volatile const uint16_t FRDY : 1;  /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR       : 1;	 /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL       : 1;	 /* [15..15] Buffer Memory Valid Flag */
     } D0FIFOCTR_b;
   };
 
@@ -275,15 +268,14 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
-      uint16_t : 4;
-      volatile uint16_t BIGEND : 1; /* [8..8] FIFO Port Endian Control */
-      uint16_t : 1;
-      volatile uint16_t MBW : 2;   /* [11..10] FIFO Port Access Bit Width */
-      volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
-      volatile uint16_t
-        DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
-      volatile uint16_t REW : 1;  /* [14..14] Buffer Pointer Rewind */
-      volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
+      uint16_t                  : 4;
+      volatile uint16_t BIGEND  : 1; /* [8..8] FIFO Port Endian Control */
+      uint16_t                  : 1;
+      volatile uint16_t MBW     : 2; /* [11..10] FIFO Port Access Bit Width */
+      volatile uint16_t DREQE   : 1; /* [12..12] DMA/DTC Transfer Request Enable */
+      volatile uint16_t DCLRM   : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
+      volatile uint16_t REW     : 1; /* [14..14] Buffer Pointer Rewind */
+      volatile uint16_t RCNT    : 1; /* [15..15] Read Count Mode */
     } D1FIFOSEL_b;
   };
 
@@ -291,12 +283,11 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */
 
     struct {
-      volatile const uint16_t
-        DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
-      uint16_t : 1;
-      volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
-      volatile uint16_t BCLR : 1;	  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-      volatile uint16_t BVAL : 1;	  /* [15..15] Buffer Memory Valid Flag */
+      volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
+      uint16_t                     : 1;
+      volatile const uint16_t FRDY : 1;  /* [13..13] FIFO Port Ready */
+      volatile uint16_t BCLR       : 1;  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL       : 1;  /* [15..15] Buffer Memory Valid Flag */
     } D1FIFOCTR_b;
   };
 
@@ -308,11 +299,11 @@ typedef struct TU_ATTR_PACKED {
       volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
       volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
       volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
-      volatile uint16_t CTRE : 1;  /* [11..11] Control Transfer Stage Transition Interrupt Enable */
-      volatile uint16_t DVSE : 1;  /* [12..12] Device State Transition Interrupt Enable */
-      volatile uint16_t SOFE : 1;  /* [13..13] Frame Number Update Interrupt Enable */
-      volatile uint16_t RSME : 1;  /* [14..14] Resume Interrupt Enable */
-      volatile uint16_t VBSE : 1;  /* [15..15] VBUS Interrupt Enable */
+      volatile uint16_t CTRE  : 1; /* [11..11] Control Transfer Stage Transition Interrupt Enable */
+      volatile uint16_t DVSE  : 1; /* [12..12] Device State Transition Interrupt Enable */
+      volatile uint16_t SOFE  : 1; /* [13..13] Frame Number Update Interrupt Enable */
+      volatile uint16_t RSME  : 1; /* [14..14] Resume Interrupt Enable */
+      volatile uint16_t VBSE  : 1; /* [15..15] VBUS Interrupt Enable */
     } INTENB0_b;
   };
 
@@ -321,16 +312,16 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */
-      uint16_t : 3;
-      volatile uint16_t SACKE : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Enable */
-      volatile uint16_t SIGNE : 1;   /* [5..5] Setup Transaction Error Interrupt Enable */
-      volatile uint16_t EOFERRE : 1; /* [6..6] EOF Error Detection Interrupt Enable */
-      uint16_t : 4;
-      volatile uint16_t ATTCHE : 1; /* [11..11] Connection Detection Interrupt Enable */
-      volatile uint16_t DTCHE : 1;  /* [12..12] Disconnection Detection Interrupt Enable */
-      uint16_t : 1;
-      volatile uint16_t BCHGE : 1;  /* [14..14] USB Bus Change Interrupt Enable */
-      volatile uint16_t OVRCRE : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */
+      uint16_t                     : 3;
+      volatile uint16_t SACKE      : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */
+      volatile uint16_t SIGNE      : 1; /* [5..5] Setup Transaction Error Interrupt Enable */
+      volatile uint16_t EOFERRE    : 1; /* [6..6] EOF Error Detection Interrupt Enable */
+      uint16_t                     : 4;
+      volatile uint16_t ATTCHE     : 1; /* [11..11] Connection Detection Interrupt Enable */
+      volatile uint16_t DTCHE      : 1; /* [12..12] Disconnection Detection Interrupt Enable */
+      uint16_t                     : 1;
+      volatile uint16_t BCHGE      : 1; /* [14..14] USB Bus Change Interrupt Enable */
+      volatile uint16_t OVRCRE     : 1; /* [15..15] Overcurrent Input Change Interrupt Enable */
     } INTENB1_b;
   };
   volatile const uint16_t RESERVED7;
@@ -393,12 +384,12 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */
 
     struct {
-      uint16_t : 4;
+      uint16_t                        : 4;
       volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */
-      volatile uint16_t INTL : 1;	     /* [5..5] Interrupt Output Sense Select */
-      volatile uint16_t BRDYM : 1;	     /* [6..6] BRDY Interrupt Status Clear Timing */
-      uint16_t : 1;
-      volatile uint16_t TRNENSEL : 1; /* [8..8] Transaction-Enabled Time Select */
+      volatile uint16_t INTL          : 1; /* [5..5] Interrupt Output Sense Select */
+      volatile uint16_t BRDYM         : 1; /* [6..6] BRDY Interrupt Status Clear Timing */
+      uint16_t                        : 1;
+      volatile uint16_t TRNENSEL      : 1; /* [8..8] Transaction-Enabled Time Select */
       uint16_t : 7;
     } SOFCFG_b;
   };
@@ -407,17 +398,17 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */
 
     struct {
-      volatile uint16_t DIRPD : 1;	/* [0..0] Power-Down Control */
+      volatile uint16_t DIRPD    : 1; /* [0..0] Power-Down Control */
       volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */
-      uint16_t : 1;
-      volatile uint16_t CDPEN : 1;  /* [3..3] Charging Downstream Port Enable */
-      volatile uint16_t CLKSEL : 2; /* [5..4] Input System Clock Frequency */
-      uint16_t : 2;
-      volatile uint16_t REPSEL : 2; /* [9..8] Terminating Resistance Adjustment Cycle */
-      uint16_t : 1;
+      uint16_t                   : 1;
+      volatile uint16_t CDPEN    : 1; /* [3..3] Charging Downstream Port Enable */
+      volatile uint16_t CLKSEL   : 2; /* [5..4] Input System Clock Frequency */
+      uint16_t                   : 2;
+      volatile uint16_t REPSEL   : 2; /* [9..8] Terminating Resistance Adjustment Cycle */
+      uint16_t                   : 1;
       volatile uint16_t REPSTART : 1; /* [11..11] Forcibly Start Terminating Resistance Adjustment */
-      uint16_t : 3;
-      volatile uint16_t HSEB : 1; /* [15..15] CL-Only Mode */
+      uint16_t                   : 3;
+      volatile uint16_t HSEB     : 1; /* [15..15] CL-Only Mode */
     } PHYSET_b;
   };
 
@@ -425,18 +416,18 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */
 
     struct {
-      volatile const uint16_t CTSQ : 3;  /* [2..0] Control Transfer Stage */
-      volatile uint16_t VALID : 1;	   /* [3..3] USB Request Reception */
-      volatile const uint16_t DVSQ : 3;  /* [6..4] Device State */
+      volatile const uint16_t CTSQ  : 3; /* [2..0] Control Transfer Stage */
+      volatile uint16_t VALID       : 1; /* [3..3] USB Request Reception */
+      volatile const uint16_t DVSQ  : 3; /* [6..4] Device State */
       volatile const uint16_t VBSTS : 1; /* [7..7] VBUS Input Status */
-      volatile const uint16_t BRDY : 1;  /* [8..8] Buffer Ready Interrupt Status */
-      volatile const uint16_t NRDY : 1;  /* [9..9] Buffer Not Ready Interrupt Status */
-      volatile const uint16_t BEMP : 1;  /* [10..10] Buffer Empty Interrupt Status */
-      volatile uint16_t CTRT : 1;	   /* [11..11] Control Transfer Stage Transition Interrupt Status */
-      volatile uint16_t DVST : 1;	   /* [12..12] Device State Transition Interrupt Status */
-      volatile uint16_t SOFR : 1;	   /* [13..13] Frame Number Refresh Interrupt Status */
-      volatile uint16_t RESM : 1;	   /* [14..14] Resume Interrupt Status */
-      volatile uint16_t VBINT : 1;	   /* [15..15] VBUS Interrupt Status */
+      volatile const uint16_t BRDY  : 1; /* [8..8] Buffer Ready Interrupt Status */
+      volatile const uint16_t NRDY  : 1; /* [9..9] Buffer Not Ready Interrupt Status */
+      volatile const uint16_t BEMP  : 1; /* [10..10] Buffer Empty Interrupt Status */
+      volatile uint16_t CTRT        : 1; /* [11..11] Control Transfer Stage Transition Interrupt Status */
+      volatile uint16_t DVST        : 1; /* [12..12] Device State Transition Interrupt Status */
+      volatile uint16_t SOFR        : 1; /* [13..13] Frame Number Refresh Interrupt Status */
+      volatile uint16_t RESM        : 1; /* [14..14] Resume Interrupt Status */
+      volatile uint16_t VBINT       : 1; /* [15..15] VBUS Interrupt Status */
     } INTSTS0_b;
   };
 
@@ -445,19 +436,19 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */
-      uint16_t : 3;
-      volatile uint16_t SACK : 1;   /* [4..4] Setup Transaction Normal Response Interrupt Status */
-      volatile uint16_t SIGN : 1;   /* [5..5] Setup Transaction Error Interrupt Status */
-      volatile uint16_t EOFERR : 1; /* [6..6] EOF Error Detection Interrupt Status */
-      uint16_t : 1;
-      volatile uint16_t LPMEND : 1;	/* [8..8] LPM Transaction End Interrupt Status */
-      volatile uint16_t L1RSMEND : 1; /* [9..9] L1 Resume End Interrupt Status */
-      uint16_t : 1;
-      volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */
-      volatile uint16_t DTCH : 1;  /* [12..12] USB Disconnection Detection Interrupt Status */
-      uint16_t : 1;
-      volatile uint16_t BCHG : 1;  /* [14..14] USB Bus Change Interrupt Status */
-      volatile uint16_t OVRCR : 1; /* [15..15] Overcurrent Input Change Interrupt Status */
+      uint16_t                    : 3;
+      volatile uint16_t SACK      : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */
+      volatile uint16_t SIGN      : 1; /* [5..5] Setup Transaction Error Interrupt Status */
+      volatile uint16_t EOFERR    : 1; /* [6..6] EOF Error Detection Interrupt Status */
+      uint16_t                    : 1;
+      volatile uint16_t LPMEND    : 1; /* [8..8] LPM Transaction End Interrupt Status */
+      volatile uint16_t L1RSMEND  : 1; /* [9..9] L1 Resume End Interrupt Status */
+      uint16_t                    : 1;
+      volatile uint16_t ATTCH     : 1; /* [11..11] ATTCH Interrupt Status */
+      volatile uint16_t DTCH      : 1; /* [12..12] USB Disconnection Detection Interrupt Status */
+      uint16_t                    : 1;
+      volatile uint16_t BCHG      : 1; /* [14..14] USB Bus Change Interrupt Status */
+      volatile uint16_t OVRCR     : 1; /* [15..15] Overcurrent Input Change Interrupt Status */
     } INTSTS1_b;
   };
   volatile const uint16_t RESERVED8;
@@ -521,9 +512,9 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */
-      uint16_t : 3;
-      volatile uint16_t CRCE : 1; /* [14..14] Receive Data Error */
-      volatile uint16_t OVRN : 1; /* [15..15] Overrun/Underrun Detection Status */
+      uint16_t                     : 3;
+      volatile uint16_t CRCE       : 1; /* [14..14] Receive Data Error */
+      volatile uint16_t OVRN       : 1; /* [15..15] Overrun/Underrun Detection Status */
     } FRMNUM_b;
   };
 
@@ -532,8 +523,8 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */
-      uint16_t : 12;
-      volatile uint16_t DVCHG : 1; /* [15..15] Device State Change */
+      uint16_t                      : 12;
+      volatile uint16_t DVCHG       : 1; /* [15..15] Device State Change */
     } UFRMNUM_b;
   };
 
@@ -542,9 +533,9 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */
-      uint16_t : 1;
-      volatile uint16_t STSRECOV0 : 3; /* [10..8] Status Recovery */
-      uint16_t : 5;
+      uint16_t                        : 1;
+      volatile uint16_t STSRECOV0     : 3; /* [10..8] Status Recovery */
+      uint16_t                        : 5;
     } USBADDR_b;
   };
   volatile const uint16_t RESERVED9;
@@ -553,9 +544,8 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */
 
     struct {
-      volatile uint16_t
-        BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
-      volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
+      volatile uint16_t BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
+      volatile uint16_t BREQUEST      : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
     } USBREQ_b;
   };
 
@@ -587,12 +577,12 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */
 
     struct {
-      uint16_t : 4;
-      volatile uint16_t DIR : 1; /* [4..4] Transfer Direction */
-      uint16_t : 2;
+      uint16_t                 : 4;
+      volatile uint16_t DIR    : 1; /* [4..4] Transfer Direction */
+      uint16_t                 : 2;
       volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
-      volatile uint16_t CNTMD : 1;  /* [8..8] Continuous Transfer Mode */
-      uint16_t : 7;
+      volatile uint16_t CNTMD  : 1; /* [8..8] Continuous Transfer Mode */
+      uint16_t                 : 7;
     } DCPCFG_b;
   };
 
@@ -600,8 +590,8 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */
 
     struct {
-      volatile uint16_t MXPS : 7; /* [6..0] Maximum Packet Size */
-      uint16_t : 5;
+      volatile uint16_t MXPS   : 7; /* [6..0] Maximum Packet Size */
+      uint16_t                 : 5;
       volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
     } DCPMAXP_b;
   };
@@ -610,18 +600,18 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */
 
     struct {
-      volatile uint16_t PID : 2;  /* [1..0] Response PID */
-      volatile uint16_t CCPL : 1; /* [2..2] Control Transfer End Enable */
-      uint16_t : 2;
+      volatile uint16_t PID         : 2; /* [1..0] Response PID */
+      volatile uint16_t CCPL        : 1; /* [2..2] Control Transfer End Enable */
+      uint16_t                      : 2;
       volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
       volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Monitor */
-      volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
-      volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
-      uint16_t : 2;
-      volatile uint16_t SUREQCLR : 1; /* [11..11] SUREQ Bit Clear */
-      uint16_t : 2;
-      volatile uint16_t SUREQ : 1;	  /* [14..14] Setup Token Transmission */
-      volatile const uint16_t BSTS : 1; /* [15..15] Buffer Status */
+      volatile uint16_t SQSET       : 1; /* [7..7] Sequence Toggle Bit Set */
+      volatile uint16_t SQCLR       : 1; /* [8..8] Sequence Toggle Bit Clear */
+      uint16_t                      : 2;
+      volatile uint16_t SUREQCLR    : 1; /* [11..11] SUREQ Bit Clear */
+      uint16_t                      : 2;
+      volatile uint16_t SUREQ       : 1; /* [14..14] Setup Token Transmission */
+      volatile const uint16_t BSTS  : 1; /* [15..15] Buffer Status */
     } DCPCTR_b;
   };
   volatile const uint16_t RESERVED10;
@@ -637,18 +627,18 @@ typedef struct TU_ATTR_PACKED {
   volatile const uint16_t RESERVED11;
 
   union {
-    volatile uint16_t PIPECFG; /* (@ 0x00000068) Pipe Configuration Register */
+    volatile uint16_t PIPECFG;      /* (@ 0x00000068) Pipe Configuration Register */
 
     struct {
-      volatile uint16_t EPNUM : 4; /* [3..0] Endpoint Number */
-      volatile uint16_t DIR : 1;   /* [4..4] Transfer Direction */
-      uint16_t : 2;
+      volatile uint16_t EPNUM  : 4; /* [3..0] Endpoint Number */
+      volatile uint16_t DIR    : 1; /* [4..4] Transfer Direction */
+      uint16_t                 : 2;
       volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
-      uint16_t : 1;
-      volatile uint16_t DBLB : 1; /* [9..9] Double Buffer Mode */
-      volatile uint16_t BFRE : 1; /* [10..10] BRDY Interrupt Operation Specification */
-      uint16_t : 3;
-      volatile uint16_t TYPE : 2; /* [15..14] Transfer Type */
+      uint16_t                 : 1;
+      volatile uint16_t DBLB   : 1; /* [9..9] Double Buffer Mode */
+      volatile uint16_t BFRE   : 1; /* [10..10] BRDY Interrupt Operation Specification */
+      uint16_t                 : 3;
+      volatile uint16_t TYPE   : 2; /* [15..14] Transfer Type */
     } PIPECFG_b;
   };
   volatile const uint16_t RESERVED12;
@@ -657,8 +647,8 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
 
     struct {
-      volatile uint16_t MXPS : 9; /* [8..0] Maximum Packet Size */
-      uint16_t : 3;
+      volatile uint16_t MXPS   : 9; /* [8..0] Maximum Packet Size */
+      uint16_t                 : 3;
       volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
     } PIPEMAXP_b;
   };
@@ -668,29 +658,29 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */
-      uint16_t : 9;
+      uint16_t               : 9;
       volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */
-      uint16_t : 3;
+      uint16_t               : 3;
     } PIPEPERI_b;
   };
 
   union {
-    volatile uint16_t PIPE_CTR[9]; /* (@ 0x00000070) Pipe [0..8] Control Register */
+    volatile uint16_t PIPE_CTR[9];        /* (@ 0x00000070) Pipe [0..8] Control Register */
 
     struct {
-      volatile uint16_t PID : 2; /* [1..0] Response PID */
-      uint16_t : 3;
-      volatile const uint16_t PBUSY : 1; /* [5..5] Pipe Busy */
-      volatile const uint16_t SQMON : 1; /* [6..6] Sequence Toggle Bit Confirmation */
-      volatile uint16_t SQSET : 1;	   /* [7..7] Sequence Toggle Bit Set */
-      volatile uint16_t SQCLR : 1;	   /* [8..8] Sequence Toggle Bit Clear */
-      volatile uint16_t ACLRM : 1;	   /* [9..9] Auto Buffer Clear Mode */
-      volatile uint16_t ATREPM : 1;	   /* [10..10] Auto Response Mode */
-      uint16_t : 1;
-      volatile const uint16_t CSSTS : 1;  /* [12..12] CSSTS Status */
-      volatile uint16_t CSCLR : 1;	    /* [13..13] CSPLIT Status Clear */
+      volatile uint16_t PID          : 2; /* [1..0] Response PID */
+      uint16_t                       : 3;
+      volatile const uint16_t PBUSY  : 1; /* [5..5] Pipe Busy */
+      volatile const uint16_t SQMON  : 1; /* [6..6] Sequence Toggle Bit Confirmation */
+      volatile uint16_t SQSET        : 1; /* [7..7] Sequence Toggle Bit Set */
+      volatile uint16_t SQCLR        : 1; /* [8..8] Sequence Toggle Bit Clear */
+      volatile uint16_t ACLRM        : 1; /* [9..9] Auto Buffer Clear Mode */
+      volatile uint16_t ATREPM       : 1; /* [10..10] Auto Response Mode */
+      uint16_t                       : 1;
+      volatile const uint16_t CSSTS  : 1; /* [12..12] CSSTS Status */
+      volatile uint16_t CSCLR        : 1; /* [13..13] CSPLIT Status Clear */
       volatile const uint16_t INBUFM : 1; /* [14..14] Transmit Buffer Monitor */
-      volatile const uint16_t BSTS : 1;   /* [15..15] Buffer Status */
+      volatile const uint16_t BSTS   : 1; /* [15..15] Buffer Status */
     } PIPE_CTR_b[9];
   };
   volatile const uint16_t RESERVED13;
@@ -699,22 +689,22 @@ typedef struct TU_ATTR_PACKED {
   volatile const uint32_t RESERVED15[3];
 
   union {
-    volatile uint16_t USBBCCTRL0; /* (@ 0x000000B0) BC Control Register 0 */
+    volatile uint16_t USBBCCTRL0;             /* (@ 0x000000B0) BC Control Register 0 */
 
     struct {
-      volatile uint16_t RPDME0 : 1;	/* [0..0] D- Pin Pull-Down Control */
-      volatile uint16_t IDPSRCE0 : 1; /* [1..1] D+ Pin IDPSRC Output Control */
+      volatile uint16_t RPDME0           : 1; /* [0..0] D- Pin Pull-Down Control */
+      volatile uint16_t IDPSRCE0         : 1; /* [1..1] D+ Pin IDPSRC Output Control */
       volatile uint16_t
-        IDMSINKE0 : 1;		/* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
-      volatile uint16_t VDPSRCE0 : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
+        IDMSINKE0                        : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t VDPSRCE0         : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
       volatile uint16_t
-        IDPSINKE0 : 1;		/* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
-      volatile uint16_t VDMSRCE0 : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
-      uint16_t : 1;
-      volatile uint16_t BATCHGE0 : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
+        IDPSINKE0                        : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t VDMSRCE0         : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
+      uint16_t                           : 1;
+      volatile uint16_t BATCHGE0         : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
       volatile const uint16_t CHGDETSTS0 : 1; /* [8..8] D- Pin 0.6 V Input Detection Status */
-      volatile const uint16_t PDDETSTS0 : 1;	/* [9..9] D+ Pin 0.6 V Input Detection Status */
-      uint16_t : 6;
+      volatile const uint16_t PDDETSTS0  : 1; /* [9..9] D+ Pin 0.6 V Input Detection Status */
+      uint16_t                           : 6;
     } USBBCCTRL0_b;
   };
   volatile const uint16_t RESERVED16;
@@ -736,9 +726,9 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */
-      uint16_t : 6;
-      volatile uint16_t VDCEN : 1; /* [7..7] USB Regulator On/Off Control */
-      uint16_t : 8;
+      uint16_t                  : 6;
+      volatile uint16_t VDCEN   : 1; /* [7..7] USB Regulator On/Off Control */
+      uint16_t                  : 8;
     } USBMC_b;
   };
   volatile const uint16_t RESERVED20;
@@ -748,9 +738,9 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       uint16_t : 6;
-      volatile uint16_t USBSPD : 2;  /* [7..6] Transfer Speed of Communication Target Device */
+      volatile uint16_t USBSPD  : 2; /* [7..6] Transfer Speed of Communication Target Device */
       volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
-      volatile uint16_t UPPHUB : 4;  /* [14..11] Communication Target Connecting Hub Register */
+      volatile uint16_t UPPHUB  : 4; /* [14..11] Communication Target Connecting Hub Register */
       uint16_t : 1;
     } DEVADD_b[10];
   };
@@ -794,15 +784,15 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */
 
     struct {
-      volatile uint16_t IDPSRCE : 1;	/* [0..0] IDPSRC Control */
-      volatile uint16_t IDMSINKE : 1; /* [1..1] IDMSINK Control */
-      volatile uint16_t VDPSRCE : 1;	/* [2..2] VDPSRC Control */
-      volatile uint16_t IDPSINKE : 1; /* [3..3] IDPSINK Control */
-      volatile uint16_t VDMSRCE : 1;	/* [4..4] VDMSRC Control */
-      volatile uint16_t DCPMODE : 1;	/* [5..5] DCP Mode Control */
-      uint16_t : 2;
+      volatile uint16_t IDPSRCE         : 1; /* [0..0] IDPSRC Control */
+      volatile uint16_t IDMSINKE        : 1; /* [1..1] IDMSINK Control */
+      volatile uint16_t VDPSRCE         : 1; /* [2..2] VDPSRC Control */
+      volatile uint16_t IDPSINKE        : 1; /* [3..3] IDPSINK Control */
+      volatile uint16_t VDMSRCE         : 1; /* [4..4] VDMSRC Control */
+      volatile uint16_t DCPMODE         : 1; /* [5..5] DCP Mode Control */
+      uint16_t                          : 2;
       volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
-      volatile const uint16_t PDDETSTS : 1;  /* [9..9] PDDET Status */
+      volatile const uint16_t PDDETSTS  : 1; /* [9..9] PDDET Status */
       uint16_t : 6;
     } BCCTRL_b;
   };
@@ -812,14 +802,13 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */
 
     struct {
-      volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */
-      volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */
-      volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */
-      volatile const uint16_t
-        DVSQ : 4;	       /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
-      volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */
-      uint16_t : 2;
-      volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */
+      volatile uint16_t L1RESPEN   : 1; /* [0..0] L1 Response Enable */
+      volatile uint16_t L1RESPMD   : 2; /* [2..1] L1 Response Mode */
+      volatile uint16_t L1NEGOMD   : 1; /* [3..3] L1 Response Negotiation Control. */
+      volatile const uint16_t DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
+      volatile uint16_t HIRDTHR    : 4; /* [11..8] L1 Response Negotiation Threshold Value */
+      uint16_t                     : 2;
+      volatile uint16_t L1EXTMD    : 1; /* [14..14] PHY Control Mode at L1 Return */
       uint16_t : 1;
     } PL1CTRL1_b;
   };
@@ -830,7 +819,7 @@ typedef struct TU_ATTR_PACKED {
     struct {
       uint16_t : 8;
       volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
-      volatile uint16_t RWEMON : 1;  /* [12..12] RWE Value Monitor */
+      volatile uint16_t RWEMON  : 1;  /* [12..12] RWE Value Monitor */
       uint16_t : 3;
     } PL1CTRL2_b;
   };
@@ -839,7 +828,7 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */
 
     struct {
-      volatile uint16_t L1REQ : 1;	      /* [0..0] L1 Transition Request */
+      volatile uint16_t L1REQ          : 1;	      /* [0..0] L1 Transition Request */
       volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
       uint16_t : 13;
     } HL1CTRL1_b;
@@ -850,11 +839,11 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */
-      uint16_t : 4;
-      volatile uint16_t HIRD : 4;  /* [11..8] LPM Token HIRD */
-      volatile uint16_t L1RWE : 1; /* [12..12] LPM Token L1 Remote Wake Enable */
-      uint16_t : 2;
-      volatile uint16_t BESL : 1; /* [15..15] BESL & Alternate HIRD */
+      uint16_t                 : 4;
+      volatile uint16_t HIRD   : 4; /* [11..8] LPM Token HIRD */
+      volatile uint16_t L1RWE  : 1; /* [12..12] LPM Token L1 Remote Wake Enable */
+      uint16_t                 : 2;
+      volatile uint16_t BESL   : 1; /* [15..15] BESL & Alternate HIRD */
     } HL1CTRL2_b;
   };
   volatile const uint32_t RESERVED25[5];
@@ -864,13 +853,10 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       uint32_t : 20;
-      volatile const uint32_t
-        DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
-      volatile const uint32_t
-        DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
-      uint32_t : 1;
-      volatile const uint32_t
-        DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
+      volatile const uint32_t DOVCAHM  : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
+      volatile const uint32_t DOVCBHM  : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
+      uint32_t                         : 1;
+      volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
       uint32_t : 8;
     } DPUSR0R_b;
   };
@@ -880,14 +866,14 @@ typedef struct TU_ATTR_PACKED {
 
     struct {
       uint32_t : 4;
-      volatile uint32_t DOVCAHE : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
-      volatile uint32_t DOVCBHE : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
-      uint32_t : 1;
-      volatile uint32_t DVBSTSHE : 1; /* [7..7] VBUS Interrupt Enable/Clear */
-      uint32_t : 12;
-      volatile const uint32_t DOVCAH : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */
-      volatile const uint32_t DOVCBH : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
-      uint32_t : 1;
+      volatile uint32_t DOVCAHE       : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
+      volatile uint32_t DOVCBHE       : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
+      uint32_t                        : 1;
+      volatile uint32_t DVBSTSHE      : 1; /* [7..7] VBUS Interrupt Enable/Clear */
+      uint32_t                        : 12;
+      volatile const uint32_t DOVCAH  : 1; /* [20..20] Indication of Return from OVRCURA Interrupt Source */
+      volatile const uint32_t DOVCBH  : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
+      uint32_t                        : 1;
       volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
       uint32_t : 8;
     } DPUSR1R_b;
@@ -899,14 +885,12 @@ typedef struct TU_ATTR_PACKED {
     struct {
       volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */
       volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */
-      uint16_t : 2;
-      volatile const uint16_t
-        DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
-      volatile const uint16_t
-        DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
-      uint16_t : 2;
-      volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */
-      volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */
+      uint16_t                      : 2;
+      volatile const uint16_t DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
+      volatile const uint16_t DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
+      uint16_t                      : 2;
+      volatile uint16_t DPINTE      : 1; /* [8..8] DP Interrupt Enable Clear */
+      volatile uint16_t DMINTE      : 1; /* [9..9] DM Interrupt Enable Clear */
       uint16_t : 6;
     } DPUSR2R_b;
   };
@@ -915,7 +899,7 @@ typedef struct TU_ATTR_PACKED {
     volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
 
     struct {
-      volatile uint16_t FIXPHY : 1;	/* [0..0] USB Transceiver Control Fix */
+      volatile uint16_t FIXPHY   : 1;	/* [0..0] USB Transceiver Control Fix */
       volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
       uint16_t : 14;
     } DPUSRCR_b;
@@ -927,22 +911,19 @@ typedef struct TU_ATTR_PACKED {
       DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */
 
     struct {
-      volatile uint32_t SRPC0 : 1; /* [0..0] USB Single End Receiver Control */
-      volatile uint32_t RPUE0 : 1; /* [1..1] DP Pull-Up Resistor Control */
-      uint32_t : 1;
-      volatile uint32_t DRPD0 : 1;   /* [3..3] D+/D- Pull-Down Resistor Control */
-      volatile uint32_t FIXPHY0 : 1; /* [4..4] USB Transceiver Output Fix */
-      uint32_t : 11;
-      volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
-      volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */
-      uint32_t : 2;
-      volatile const uint32_t
-        DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
-      volatile const uint32_t
-        DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
-      uint32_t : 1;
-      volatile const uint32_t
-        DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
+      volatile uint32_t SRPC0         : 1; /* [0..0] USB Single End Receiver Control */
+      volatile uint32_t RPUE0         : 1; /* [1..1] DP Pull-Up Resistor Control */
+      uint32_t                        : 1;
+      volatile uint32_t DRPD0         : 1; /* [3..3] D+/D- Pull-Down Resistor Control */
+      volatile uint32_t FIXPHY0       : 1; /* [4..4] USB Transceiver Output Fix */
+      uint32_t                        : 11;
+      volatile const uint32_t DP0     : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
+      volatile const uint32_t DM0     : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */
+      uint32_t                        : 2;
+      volatile const uint32_t DOVCA0  : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
+      volatile const uint32_t DOVCB0  : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
+      uint32_t                        : 1;
+      volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
       uint32_t : 8;
     } DPUSR0R_FS_b;
   };
@@ -951,88 +932,26 @@ typedef struct TU_ATTR_PACKED {
     volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */
 
     struct {
-      volatile uint32_t DPINTE0 : 1; /* [0..0] USB DP Interrupt Enable/Clear */
-      volatile uint32_t DMINTE0 : 1; /* [1..1] USB DM Interrupt Enable/Clear */
-      uint32_t : 2;
-      volatile uint32_t DOVRCRAE0 : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */
-      volatile uint32_t DOVRCRBE0 : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */
-      uint32_t : 1;
-      volatile uint32_t DVBSE0 : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */
-      uint32_t : 8;
-      volatile const uint32_t DPINT0 : 1; /* [16..16] USB DP Interrupt Source Recovery */
-      volatile const uint32_t DMINT0 : 1; /* [17..17] USB DM Interrupt Source Recovery */
-      uint32_t : 2;
+      volatile uint32_t DPINTE0        : 1; /* [0..0] USB DP Interrupt Enable/Clear */
+      volatile uint32_t DMINTE0        : 1; /* [1..1] USB DM Interrupt Enable/Clear */
+      uint32_t                         : 2;
+      volatile uint32_t DOVRCRAE0      : 1; /* [4..4] USB OVRCURA Interrupt Enable/Clear */
+      volatile uint32_t DOVRCRBE0      : 1; /* [5..5] USB OVRCURB Interrupt Enable/Clear */
+      uint32_t                         : 1;
+      volatile uint32_t DVBSE0         : 1; /* [7..7] USB VBUS Interrupt Enable/Clear */
+      uint32_t                         : 8;
+      volatile const uint32_t DPINT0   : 1; /* [16..16] USB DP Interrupt Source Recovery */
+      volatile const uint32_t DMINT0   : 1; /* [17..17] USB DM Interrupt Source Recovery */
+      uint32_t                         : 2;
       volatile const uint32_t DOVRCRA0 : 1; /* [20..20] USB OVRCURA Interrupt Source Recovery */
       volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
-      uint32_t : 1;
-      volatile const uint32_t DVBINT0 : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
+      uint32_t                         : 1;
+      volatile const uint32_t DVBINT0  : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
       uint32_t : 8;
     } DPUSR1R_FS_b;
   };
 } LINK_REG_t; /* Size = 1032 (0x408) */
 
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG) == 0x00000000, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT) == 0x00000002, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0) == 0x00000004, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA) == 0x00000006, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0) == 0x00000008, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE) == 0x0000000C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO) == 0x00000014, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO) == 0x00000018, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO) == 0x0000001C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL) == 0x00000020, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR) == 0x00000022, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL) == 0x00000028, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR) == 0x0000002A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL) == 0x0000002C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR) == 0x0000002E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0) == 0x00000030, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1) == 0x00000032, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB) == 0x00000036, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB) == 0x00000038, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB) == 0x0000003A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG) == 0x0000003C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET) == 0x0000003E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0) == 0x00000040, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1) == 0x00000042, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS) == 0x00000046, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS) == 0x00000048, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS) == 0x0000004A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM) == 0x0000004C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM) == 0x0000004E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR) == 0x00000050, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ) == 0x00000054, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL) == 0x00000056, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX) == 0x00000058, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG) == 0x0000005A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG) == 0x0000005C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP) == 0x0000005E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR) == 0x00000060, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL) == 0x00000064, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG) == 0x00000068, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP) == 0x0000006C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI) == 0x0000006E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR) == 0x00000070, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR) == 0x00000090, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0) == 0x000000B0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL) == 0x000000C4, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC) == 0x000000CC, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD) == 0x000000D0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW) == 0x000000F0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL) == 0x00000100, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS) == 0x00000102, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL) == 0x00000140, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1) == 0x00000144, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2) == 0x00000146, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1) == 0x00000148, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2) == 0x0000014A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R) == 0x00000160, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R) == 0x00000164, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R) == 0x00000168, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR) == 0x0000016A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS) == 0x00000400, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS) == 0x00000404, "incorrect offset");
-
 TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
 TU_ATTR_BIT_FIELD_ORDER_END
 
@@ -1040,582 +959,708 @@ TU_ATTR_BIT_FIELD_ORDER_END
 /* Register Bit Definitions                                           */
 /*--------------------------------------------------------------------*/
 
-/* PIPE_TR */
-/* E */
-#define LINK_REG_PIPE_TR_E_TRENB_Pos (9UL)     /* TRENB (Bit 9) */
-#define LINK_REG_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_TR_E_TRCLR_Pos (8UL)     /* TRCLR (Bit 8) */
-#define LINK_REG_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */
-/* N */
-#define LINK_REG_PIPE_TR_N_TRNCNT_Pos (0UL)	 /* TRNCNT (Bit 0) */
-#define LINK_REG_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */
+// PIPE_TR
+// E
+#define LINK_REG_PIPE_TR_E_TRENB_Pos       (9UL)        /* TRENB (Bit 9) */
+#define LINK_REG_PIPE_TR_E_TRENB_Msk       (0x200UL)    /* TRENB (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_TR_E_TRCLR_Pos       (8UL)        /* TRCLR (Bit 8) */
+#define LINK_REG_PIPE_TR_E_TRCLR_Msk       (0x100UL)    /* TRCLR (Bitfield-Mask: 0x01) */
 
-/* LINK_REG */
-/* SYSCFG */
-#define LINK_REG_SYSCFG_SCKE_Pos  (10UL)    /* SCKE (Bit 10) */
-#define LINK_REG_SYSCFG_SCKE_Msk  (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_CNEN_Pos  (8UL)	    /* CNEN (Bit 8) */
-#define LINK_REG_SYSCFG_CNEN_Msk  (0x100UL) /* CNEN (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_DCFM_Pos  (6UL)	    /* DCFM (Bit 6) */
-#define LINK_REG_SYSCFG_DCFM_Msk  (0x40UL)  /* DCFM (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_DRPD_Pos  (5UL)	    /* DRPD (Bit 5) */
-#define LINK_REG_SYSCFG_DRPD_Msk  (0x20UL)  /* DRPD (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_DPRPU_Pos (4UL)	    /* DPRPU (Bit 4) */
-#define LINK_REG_SYSCFG_DPRPU_Msk (0x10UL)  /* DPRPU (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_DMRPU_Pos (3UL)	    /* DMRPU (Bit 3) */
-#define LINK_REG_SYSCFG_DMRPU_Msk (0x8UL)   /* DMRPU (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_USBE_Pos  (0UL)	    /* USBE (Bit 0) */
-#define LINK_REG_SYSCFG_USBE_Msk  (0x1UL)   /* USBE (Bitfield-Mask: 0x01) */
-/* BUSWAIT */
-#define LINK_REG_BUSWAIT_BWAIT_Pos (0UL)   /* BWAIT (Bit 0) */
-#define LINK_REG_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */
-/* SYSSTS0 */
-#define LINK_REG_SYSSTS0_OVCMON_Pos (14UL)     /* OVCMON (Bit 14) */
-#define LINK_REG_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */
-#define LINK_REG_SYSSTS0_HTACT_Pos  (6UL)      /* HTACT (Bit 6) */
-#define LINK_REG_SYSSTS0_HTACT_Msk  (0x40UL)   /* HTACT (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSSTS0_SOFEA_Pos  (5UL)      /* SOFEA (Bit 5) */
-#define LINK_REG_SYSSTS0_SOFEA_Msk  (0x20UL)   /* SOFEA (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSSTS0_IDMON_Pos  (2UL)      /* IDMON (Bit 2) */
-#define LINK_REG_SYSSTS0_IDMON_Msk  (0x4UL)    /* IDMON (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSSTS0_LNST_Pos   (0UL)      /* LNST (Bit 0) */
-#define LINK_REG_SYSSTS0_LNST_Msk   (0x3UL)    /* LNST (Bitfield-Mask: 0x03) */
-/* PLLSTA */
-#define LINK_REG_PLLSTA_PLLLOCK_Pos (0UL)   /* PLLLOCK (Bit 0) */
-#define LINK_REG_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */
-/* DVSTCTR0 */
-#define LINK_REG_DVSTCTR0_HNPBTOA_Pos (11UL)	/* HNPBTOA (Bit 11) */
-#define LINK_REG_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_EXICEN_Pos  (10UL)	/* EXICEN (Bit 10) */
-#define LINK_REG_DVSTCTR0_EXICEN_Msk  (0x400UL) /* EXICEN (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_VBUSEN_Pos  (9UL)	/* VBUSEN (Bit 9) */
-#define LINK_REG_DVSTCTR0_VBUSEN_Msk  (0x200UL) /* VBUSEN (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_WKUP_Pos    (8UL)	/* WKUP (Bit 8) */
-#define LINK_REG_DVSTCTR0_WKUP_Msk    (0x100UL) /* WKUP (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_RWUPE_Pos   (7UL)	/* RWUPE (Bit 7) */
-#define LINK_REG_DVSTCTR0_RWUPE_Msk   (0x80UL)	/* RWUPE (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_USBRST_Pos  (6UL)	/* USBRST (Bit 6) */
-#define LINK_REG_DVSTCTR0_USBRST_Msk  (0x40UL)	/* USBRST (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_RESUME_Pos  (5UL)	/* RESUME (Bit 5) */
-#define LINK_REG_DVSTCTR0_RESUME_Msk  (0x20UL)	/* RESUME (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_UACT_Pos    (4UL)	/* UACT (Bit 4) */
-#define LINK_REG_DVSTCTR0_UACT_Msk    (0x10UL)	/* UACT (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_RHST_Pos    (0UL)	/* RHST (Bit 0) */
-#define LINK_REG_DVSTCTR0_RHST_Msk    (0x7UL)	/* RHST (Bitfield-Mask: 0x07) */
-/* TESTMODE */
-#define LINK_REG_TESTMODE_UTST_Pos (0UL)   /* UTST (Bit 0) */
-#define LINK_REG_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */
-/* CFIFOSEL */
-#define LINK_REG_CFIFOSEL_RCNT_Pos    (15UL)	 /* RCNT (Bit 15) */
-#define LINK_REG_CFIFOSEL_RCNT_Msk    (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOSEL_REW_Pos     (14UL)	 /* REW (Bit 14) */
-#define LINK_REG_CFIFOSEL_REW_Msk     (0x4000UL) /* REW (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOSEL_MBW_Pos     (10UL)	 /* MBW (Bit 10) */
-#define LINK_REG_CFIFOSEL_MBW_Msk     (0xc00UL)	 /* MBW (Bitfield-Mask: 0x03) */
-#define LINK_REG_CFIFOSEL_BIGEND_Pos  (8UL)	 /* BIGEND (Bit 8) */
-#define LINK_REG_CFIFOSEL_BIGEND_Msk  (0x100UL)	 /* BIGEND (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOSEL_ISEL_Pos    (5UL)	 /* ISEL (Bit 5) */
-#define LINK_REG_CFIFOSEL_ISEL_Msk    (0x20UL)	 /* ISEL (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOSEL_CURPIPE_Pos (0UL)	 /* CURPIPE (Bit 0) */
-#define LINK_REG_CFIFOSEL_CURPIPE_Msk (0xfUL)	 /* CURPIPE (Bitfield-Mask: 0x0f) */
-/* CFIFOCTR */
-#define LINK_REG_CFIFOCTR_BVAL_Pos (15UL)     /* BVAL (Bit 15) */
-#define LINK_REG_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOCTR_BCLR_Pos (14UL)     /* BCLR (Bit 14) */
-#define LINK_REG_CFIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOCTR_FRDY_Pos (13UL)     /* FRDY (Bit 13) */
-#define LINK_REG_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOCTR_DTLN_Pos (0UL)      /* DTLN (Bit 0) */
-#define LINK_REG_CFIFOCTR_DTLN_Msk (0xfffUL)  /* DTLN (Bitfield-Mask: 0xfff) */
-/* D0FIFOSEL */
-#define LINK_REG_D0FIFOSEL_RCNT_Pos    (15UL)	  /* RCNT (Bit 15) */
-#define LINK_REG_D0FIFOSEL_RCNT_Msk    (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOSEL_REW_Pos     (14UL)	  /* REW (Bit 14) */
-#define LINK_REG_D0FIFOSEL_REW_Msk     (0x4000UL) /* REW (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOSEL_DCLRM_Pos   (13UL)	  /* DCLRM (Bit 13) */
-#define LINK_REG_D0FIFOSEL_DCLRM_Msk   (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOSEL_DREQE_Pos   (12UL)	  /* DREQE (Bit 12) */
-#define LINK_REG_D0FIFOSEL_DREQE_Msk   (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOSEL_MBW_Pos     (10UL)	  /* MBW (Bit 10) */
-#define LINK_REG_D0FIFOSEL_MBW_Msk     (0xc00UL)  /* MBW (Bitfield-Mask: 0x03) */
-#define LINK_REG_D0FIFOSEL_BIGEND_Pos  (8UL)	  /* BIGEND (Bit 8) */
-#define LINK_REG_D0FIFOSEL_BIGEND_Msk  (0x100UL)  /* BIGEND (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOSEL_CURPIPE_Pos (0UL)	  /* CURPIPE (Bit 0) */
-#define LINK_REG_D0FIFOSEL_CURPIPE_Msk (0xfUL)	  /* CURPIPE (Bitfield-Mask: 0x0f) */
-/* D0FIFOCTR */
-#define LINK_REG_D0FIFOCTR_BVAL_Pos (15UL)     /* BVAL (Bit 15) */
-#define LINK_REG_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOCTR_BCLR_Pos (14UL)     /* BCLR (Bit 14) */
-#define LINK_REG_D0FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOCTR_FRDY_Pos (13UL)     /* FRDY (Bit 13) */
-#define LINK_REG_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOCTR_DTLN_Pos (0UL)      /* DTLN (Bit 0) */
-#define LINK_REG_D0FIFOCTR_DTLN_Msk (0xfffUL)  /* DTLN (Bitfield-Mask: 0xfff) */
-/* D1FIFOSEL */
-#define LINK_REG_D1FIFOSEL_RCNT_Pos    (15UL)	  /* RCNT (Bit 15) */
-#define LINK_REG_D1FIFOSEL_RCNT_Msk    (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOSEL_REW_Pos     (14UL)	  /* REW (Bit 14) */
-#define LINK_REG_D1FIFOSEL_REW_Msk     (0x4000UL) /* REW (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOSEL_DCLRM_Pos   (13UL)	  /* DCLRM (Bit 13) */
-#define LINK_REG_D1FIFOSEL_DCLRM_Msk   (0x2000UL) /* DCLRM (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOSEL_DREQE_Pos   (12UL)	  /* DREQE (Bit 12) */
-#define LINK_REG_D1FIFOSEL_DREQE_Msk   (0x1000UL) /* DREQE (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOSEL_MBW_Pos     (10UL)	  /* MBW (Bit 10) */
-#define LINK_REG_D1FIFOSEL_MBW_Msk     (0xc00UL)  /* MBW (Bitfield-Mask: 0x03) */
-#define LINK_REG_D1FIFOSEL_BIGEND_Pos  (8UL)	  /* BIGEND (Bit 8) */
-#define LINK_REG_D1FIFOSEL_BIGEND_Msk  (0x100UL)  /* BIGEND (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOSEL_CURPIPE_Pos (0UL)	  /* CURPIPE (Bit 0) */
-#define LINK_REG_D1FIFOSEL_CURPIPE_Msk (0xfUL)	  /* CURPIPE (Bitfield-Mask: 0x0f) */
-/* D1FIFOCTR */
-#define LINK_REG_D1FIFOCTR_BVAL_Pos (15UL)     /* BVAL (Bit 15) */
-#define LINK_REG_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOCTR_BCLR_Pos (14UL)     /* BCLR (Bit 14) */
-#define LINK_REG_D1FIFOCTR_BCLR_Msk (0x4000UL) /* BCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOCTR_FRDY_Pos (13UL)     /* FRDY (Bit 13) */
-#define LINK_REG_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOCTR_DTLN_Pos (0UL)      /* DTLN (Bit 0) */
-#define LINK_REG_D1FIFOCTR_DTLN_Msk (0xfffUL)  /* DTLN (Bitfield-Mask: 0xfff) */
-/* INTENB0 */
-#define LINK_REG_INTENB0_VBSE_Pos  (15UL)     /* VBSE (Bit 15) */
-#define LINK_REG_INTENB0_VBSE_Msk  (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_RSME_Pos  (14UL)     /* RSME (Bit 14) */
-#define LINK_REG_INTENB0_RSME_Msk  (0x4000UL) /* RSME (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_SOFE_Pos  (13UL)     /* SOFE (Bit 13) */
-#define LINK_REG_INTENB0_SOFE_Msk  (0x2000UL) /* SOFE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_DVSE_Pos  (12UL)     /* DVSE (Bit 12) */
-#define LINK_REG_INTENB0_DVSE_Msk  (0x1000UL) /* DVSE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_CTRE_Pos  (11UL)     /* CTRE (Bit 11) */
-#define LINK_REG_INTENB0_CTRE_Msk  (0x800UL)  /* CTRE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_BEMPE_Pos (10UL)     /* BEMPE (Bit 10) */
-#define LINK_REG_INTENB0_BEMPE_Msk (0x400UL)  /* BEMPE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_NRDYE_Pos (9UL)      /* NRDYE (Bit 9) */
-#define LINK_REG_INTENB0_NRDYE_Msk (0x200UL)  /* NRDYE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_BRDYE_Pos (8UL)      /* BRDYE (Bit 8) */
-#define LINK_REG_INTENB0_BRDYE_Msk (0x100UL)  /* BRDYE (Bitfield-Mask: 0x01) */
-/* INTENB1 */
-#define LINK_REG_INTENB1_OVRCRE_Pos	(15UL)	   /* OVRCRE (Bit 15) */
-#define LINK_REG_INTENB1_OVRCRE_Msk	(0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_BCHGE_Pos	(14UL)	   /* BCHGE (Bit 14) */
-#define LINK_REG_INTENB1_BCHGE_Msk	(0x4000UL) /* BCHGE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_DTCHE_Pos	(12UL)	   /* DTCHE (Bit 12) */
-#define LINK_REG_INTENB1_DTCHE_Msk	(0x1000UL) /* DTCHE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_ATTCHE_Pos	(11UL)	   /* ATTCHE (Bit 11) */
-#define LINK_REG_INTENB1_ATTCHE_Msk	(0x800UL)  /* ATTCHE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_EOFERRE_Pos	(6UL)	   /* EOFERRE (Bit 6) */
-#define LINK_REG_INTENB1_EOFERRE_Msk	(0x40UL)   /* EOFERRE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_SIGNE_Pos	(5UL)	   /* SIGNE (Bit 5) */
-#define LINK_REG_INTENB1_SIGNE_Msk	(0x20UL)   /* SIGNE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_SACKE_Pos	(4UL)	   /* SACKE (Bit 4) */
-#define LINK_REG_INTENB1_SACKE_Msk	(0x10UL)   /* SACKE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_PDDETINTE0_Pos (0UL)	   /* PDDETINTE0 (Bit 0) */
-#define LINK_REG_INTENB1_PDDETINTE0_Msk (0x1UL)	   /* PDDETINTE0 (Bitfield-Mask: 0x01) */
-/* BRDYENB */
-#define LINK_REG_BRDYENB_PIPEBRDYE_Pos (0UL)   /* PIPEBRDYE (Bit 0) */
-#define LINK_REG_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */
-/* NRDYENB */
-#define LINK_REG_NRDYENB_PIPENRDYE_Pos (0UL)   /* PIPENRDYE (Bit 0) */
-#define LINK_REG_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */
-/* BEMPENB */
-#define LINK_REG_BEMPENB_PIPEBEMPE_Pos (0UL)   /* PIPEBEMPE (Bit 0) */
-#define LINK_REG_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */
-/* SOFCFG */
-#define LINK_REG_SOFCFG_TRNENSEL_Pos (8UL)     /* TRNENSEL (Bit 8) */
-#define LINK_REG_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */
-#define LINK_REG_SOFCFG_BRDYM_Pos    (6UL)     /* BRDYM (Bit 6) */
-#define LINK_REG_SOFCFG_BRDYM_Msk    (0x40UL)  /* BRDYM (Bitfield-Mask: 0x01) */
-#define LINK_REG_SOFCFG_INTL_Pos     (5UL)     /* INTL (Bit 5) */
-#define LINK_REG_SOFCFG_INTL_Msk     (0x20UL)  /* INTL (Bitfield-Mask: 0x01) */
-#define LINK_REG_SOFCFG_EDGESTS_Pos  (4UL)     /* EDGESTS (Bit 4) */
-#define LINK_REG_SOFCFG_EDGESTS_Msk  (0x10UL)  /* EDGESTS (Bitfield-Mask: 0x01) */
-/* PHYSET */
-#define LINK_REG_PHYSET_HSEB_Pos     (15UL)	/* HSEB (Bit 15) */
-#define LINK_REG_PHYSET_HSEB_Msk     (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSET_REPSTART_Pos (11UL)	/* REPSTART (Bit 11) */
-#define LINK_REG_PHYSET_REPSTART_Msk (0x800UL)	/* REPSTART (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSET_REPSEL_Pos   (8UL)	/* REPSEL (Bit 8) */
-#define LINK_REG_PHYSET_REPSEL_Msk   (0x300UL)	/* REPSEL (Bitfield-Mask: 0x03) */
-#define LINK_REG_PHYSET_CLKSEL_Pos   (4UL)	/* CLKSEL (Bit 4) */
-#define LINK_REG_PHYSET_CLKSEL_Msk   (0x30UL)	/* CLKSEL (Bitfield-Mask: 0x03) */
-#define LINK_REG_PHYSET_CDPEN_Pos    (3UL)	/* CDPEN (Bit 3) */
-#define LINK_REG_PHYSET_CDPEN_Msk    (0x8UL)	/* CDPEN (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSET_PLLRESET_Pos (1UL)	/* PLLRESET (Bit 1) */
-#define LINK_REG_PHYSET_PLLRESET_Msk (0x2UL)	/* PLLRESET (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSET_DIRPD_Pos    (0UL)	/* DIRPD (Bit 0) */
-#define LINK_REG_PHYSET_DIRPD_Msk    (0x1UL)	/* DIRPD (Bitfield-Mask: 0x01) */
-/* INTSTS0 */
-#define LINK_REG_INTSTS0_VBINT_Pos (15UL)     /* VBINT (Bit 15) */
-#define LINK_REG_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_RESM_Pos  (14UL)     /* RESM (Bit 14) */
-#define LINK_REG_INTSTS0_RESM_Msk  (0x4000UL) /* RESM (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_SOFR_Pos  (13UL)     /* SOFR (Bit 13) */
-#define LINK_REG_INTSTS0_SOFR_Msk  (0x2000UL) /* SOFR (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_DVST_Pos  (12UL)     /* DVST (Bit 12) */
-#define LINK_REG_INTSTS0_DVST_Msk  (0x1000UL) /* DVST (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_CTRT_Pos  (11UL)     /* CTRT (Bit 11) */
-#define LINK_REG_INTSTS0_CTRT_Msk  (0x800UL)  /* CTRT (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_BEMP_Pos  (10UL)     /* BEMP (Bit 10) */
-#define LINK_REG_INTSTS0_BEMP_Msk  (0x400UL)  /* BEMP (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_NRDY_Pos  (9UL)      /* NRDY (Bit 9) */
-#define LINK_REG_INTSTS0_NRDY_Msk  (0x200UL)  /* NRDY (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_BRDY_Pos  (8UL)      /* BRDY (Bit 8) */
-#define LINK_REG_INTSTS0_BRDY_Msk  (0x100UL)  /* BRDY (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_VBSTS_Pos (7UL)      /* VBSTS (Bit 7) */
-#define LINK_REG_INTSTS0_VBSTS_Msk (0x80UL)   /* VBSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_DVSQ_Pos  (4UL)      /* DVSQ (Bit 4) */
-#define LINK_REG_INTSTS0_DVSQ_Msk  (0x70UL)   /* DVSQ (Bitfield-Mask: 0x07) */
-#define LINK_REG_INTSTS0_VALID_Pos (3UL)      /* VALID (Bit 3) */
-#define LINK_REG_INTSTS0_VALID_Msk (0x8UL)    /* VALID (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_CTSQ_Pos  (0UL)      /* CTSQ (Bit 0) */
-#define LINK_REG_INTSTS0_CTSQ_Msk  (0x7UL)    /* CTSQ (Bitfield-Mask: 0x07) */
-/* INTSTS1 */
-#define LINK_REG_INTSTS1_OVRCR_Pos     (15UL)	  /* OVRCR (Bit 15) */
-#define LINK_REG_INTSTS1_OVRCR_Msk     (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_BCHG_Pos      (14UL)	  /* BCHG (Bit 14) */
-#define LINK_REG_INTSTS1_BCHG_Msk      (0x4000UL) /* BCHG (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_DTCH_Pos      (12UL)	  /* DTCH (Bit 12) */
-#define LINK_REG_INTSTS1_DTCH_Msk      (0x1000UL) /* DTCH (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_ATTCH_Pos     (11UL)	  /* ATTCH (Bit 11) */
-#define LINK_REG_INTSTS1_ATTCH_Msk     (0x800UL)  /* ATTCH (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_L1RSMEND_Pos  (9UL)	  /* L1RSMEND (Bit 9) */
-#define LINK_REG_INTSTS1_L1RSMEND_Msk  (0x200UL)  /* L1RSMEND (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_LPMEND_Pos    (8UL)	  /* LPMEND (Bit 8) */
-#define LINK_REG_INTSTS1_LPMEND_Msk    (0x100UL)  /* LPMEND (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_EOFERR_Pos    (6UL)	  /* EOFERR (Bit 6) */
-#define LINK_REG_INTSTS1_EOFERR_Msk    (0x40UL)	  /* EOFERR (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_SIGN_Pos      (5UL)	  /* SIGN (Bit 5) */
-#define LINK_REG_INTSTS1_SIGN_Msk      (0x20UL)	  /* SIGN (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_SACK_Pos      (4UL)	  /* SACK (Bit 4) */
-#define LINK_REG_INTSTS1_SACK_Msk      (0x10UL)	  /* SACK (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_PDDETINT0_Pos (0UL)	  /* PDDETINT0 (Bit 0) */
-#define LINK_REG_INTSTS1_PDDETINT0_Msk (0x1UL)	  /* PDDETINT0 (Bitfield-Mask: 0x01) */
-/* BRDYSTS */
-#define LINK_REG_BRDYSTS_PIPEBRDY_Pos (0UL)   /* PIPEBRDY (Bit 0) */
-#define LINK_REG_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */
-/* NRDYSTS */
-#define LINK_REG_NRDYSTS_PIPENRDY_Pos (0UL)   /* PIPENRDY (Bit 0) */
-#define LINK_REG_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */
-/* BEMPSTS */
-#define LINK_REG_BEMPSTS_PIPEBEMP_Pos (0UL)   /* PIPEBEMP (Bit 0) */
-#define LINK_REG_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */
-/* FRMNUM */
-#define LINK_REG_FRMNUM_OVRN_Pos (15UL)	    /* OVRN (Bit 15) */
-#define LINK_REG_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */
-#define LINK_REG_FRMNUM_CRCE_Pos (14UL)	    /* CRCE (Bit 14) */
-#define LINK_REG_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */
-#define LINK_REG_FRMNUM_FRNM_Pos (0UL)	    /* FRNM (Bit 0) */
-#define LINK_REG_FRMNUM_FRNM_Msk (0x7ffUL)  /* FRNM (Bitfield-Mask: 0x7ff) */
-/* UFRMNUM */
-#define LINK_REG_UFRMNUM_DVCHG_Pos (15UL)     /* DVCHG (Bit 15) */
-#define LINK_REG_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */
-#define LINK_REG_UFRMNUM_UFRNM_Pos (0UL)      /* UFRNM (Bit 0) */
-#define LINK_REG_UFRMNUM_UFRNM_Msk (0x7UL)    /* UFRNM (Bitfield-Mask: 0x07) */
-/* USBADDR */
-#define LINK_REG_USBADDR_STSRECOV0_Pos (8UL)	 /* STSRECOV0 (Bit 8) */
-#define LINK_REG_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */
-#define LINK_REG_USBADDR_USBADDR_Pos   (0UL)	 /* USBADDR (Bit 0) */
-#define LINK_REG_USBADDR_USBADDR_Msk   (0x7fUL)	 /* USBADDR (Bitfield-Mask: 0x7f) */
-/* USBREQ */
-#define LINK_REG_USBREQ_BREQUEST_Pos	  (8UL)	     /* BREQUEST (Bit 8) */
-#define LINK_REG_USBREQ_BREQUEST_Msk	  (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */
-#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos (0UL)	     /* BMREQUESTTYPE (Bit 0) */
-#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk (0xffUL)   /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */
-/* USBVAL */
-#define LINK_REG_USBVAL_WVALUE_Pos (0UL)      /* WVALUE (Bit 0) */
-#define LINK_REG_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */
-/* USBINDX */
-#define LINK_REG_USBINDX_WINDEX_Pos (0UL)      /* WINDEX (Bit 0) */
-#define LINK_REG_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */
-/* USBLENG */
-#define LINK_REG_USBLENG_WLENGTH_Pos (0UL)	/* WLENGTH (Bit 0) */
-#define LINK_REG_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */
-/* DCPCFG */
-#define LINK_REG_DCPCFG_CNTMD_Pos  (8UL)     /* CNTMD (Bit 8) */
-#define LINK_REG_DCPCFG_CNTMD_Msk  (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCFG_SHTNAK_Pos (7UL)     /* SHTNAK (Bit 7) */
-#define LINK_REG_DCPCFG_SHTNAK_Msk (0x80UL)  /* SHTNAK (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCFG_DIR_Pos	   (4UL)     /* DIR (Bit 4) */
-#define LINK_REG_DCPCFG_DIR_Msk	   (0x10UL)  /* DIR (Bitfield-Mask: 0x01) */
-/* DCPMAXP */
-#define LINK_REG_DCPMAXP_DEVSEL_Pos (12UL)     /* DEVSEL (Bit 12) */
-#define LINK_REG_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */
-#define LINK_REG_DCPMAXP_MXPS_Pos   (0UL)      /* MXPS (Bit 0) */
-#define LINK_REG_DCPMAXP_MXPS_Msk   (0x7fUL)   /* MXPS (Bitfield-Mask: 0x7f) */
-/* DCPCTR */
-#define LINK_REG_DCPCTR_BSTS_Pos     (15UL)	/* BSTS (Bit 15) */
-#define LINK_REG_DCPCTR_BSTS_Msk     (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_SUREQ_Pos    (14UL)	/* SUREQ (Bit 14) */
-#define LINK_REG_DCPCTR_SUREQ_Msk    (0x4000UL) /* SUREQ (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_SUREQCLR_Pos (11UL)	/* SUREQCLR (Bit 11) */
-#define LINK_REG_DCPCTR_SUREQCLR_Msk (0x800UL)	/* SUREQCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_SQCLR_Pos    (8UL)	/* SQCLR (Bit 8) */
-#define LINK_REG_DCPCTR_SQCLR_Msk    (0x100UL)	/* SQCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_SQSET_Pos    (7UL)	/* SQSET (Bit 7) */
-#define LINK_REG_DCPCTR_SQSET_Msk    (0x80UL)	/* SQSET (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_SQMON_Pos    (6UL)	/* SQMON (Bit 6) */
-#define LINK_REG_DCPCTR_SQMON_Msk    (0x40UL)	/* SQMON (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_PBUSY_Pos    (5UL)	/* PBUSY (Bit 5) */
-#define LINK_REG_DCPCTR_PBUSY_Msk    (0x20UL)	/* PBUSY (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_CCPL_Pos     (2UL)	/* CCPL (Bit 2) */
-#define LINK_REG_DCPCTR_CCPL_Msk     (0x4UL)	/* CCPL (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_PID_Pos	     (0UL)	/* PID (Bit 0) */
-#define LINK_REG_DCPCTR_PID_Msk	     (0x3UL)	/* PID (Bitfield-Mask: 0x03) */
-/* PIPESEL */
-#define LINK_REG_PIPESEL_PIPESEL_Pos (0UL)   /* PIPESEL (Bit 0) */
-#define LINK_REG_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */
-/* PIPECFG */
-#define LINK_REG_PIPECFG_TYPE_Pos   (14UL)     /* TYPE (Bit 14) */
-#define LINK_REG_PIPECFG_TYPE_Msk   (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */
-#define LINK_REG_PIPECFG_BFRE_Pos   (10UL)     /* BFRE (Bit 10) */
-#define LINK_REG_PIPECFG_BFRE_Msk   (0x400UL)  /* BFRE (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPECFG_DBLB_Pos   (9UL)      /* DBLB (Bit 9) */
-#define LINK_REG_PIPECFG_DBLB_Msk   (0x200UL)  /* DBLB (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPECFG_SHTNAK_Pos (7UL)      /* SHTNAK (Bit 7) */
-#define LINK_REG_PIPECFG_SHTNAK_Msk (0x80UL)   /* SHTNAK (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPECFG_DIR_Pos    (4UL)      /* DIR (Bit 4) */
-#define LINK_REG_PIPECFG_DIR_Msk    (0x10UL)   /* DIR (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPECFG_EPNUM_Pos  (0UL)      /* EPNUM (Bit 0) */
-#define LINK_REG_PIPECFG_EPNUM_Msk  (0xfUL)    /* EPNUM (Bitfield-Mask: 0x0f) */
-/* PIPEMAXP */
-#define LINK_REG_PIPEMAXP_DEVSEL_Pos (12UL)	/* DEVSEL (Bit 12) */
-#define LINK_REG_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */
-#define LINK_REG_PIPEMAXP_MXPS_Pos   (0UL)	/* MXPS (Bit 0) */
-#define LINK_REG_PIPEMAXP_MXPS_Msk   (0x1ffUL)	/* MXPS (Bitfield-Mask: 0x1ff) */
-/* PIPEPERI */
-#define LINK_REG_PIPEPERI_IFIS_Pos (12UL)     /* IFIS (Bit 12) */
-#define LINK_REG_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPEPERI_IITV_Pos (0UL)      /* IITV (Bit 0) */
-#define LINK_REG_PIPEPERI_IITV_Msk (0x7UL)    /* IITV (Bitfield-Mask: 0x07) */
-/* PIPE_CTR */
-#define LINK_REG_PIPE_CTR_BSTS_Pos   (15UL)	/* BSTS (Bit 15) */
-#define LINK_REG_PIPE_CTR_BSTS_Msk   (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_INBUFM_Pos (14UL)	/* INBUFM (Bit 14) */
-#define LINK_REG_PIPE_CTR_INBUFM_Msk (0x4000UL) /* INBUFM (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_CSCLR_Pos  (13UL)	/* CSCLR (Bit 13) */
-#define LINK_REG_PIPE_CTR_CSCLR_Msk  (0x2000UL) /* CSCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_CSSTS_Pos  (12UL)	/* CSSTS (Bit 12) */
-#define LINK_REG_PIPE_CTR_CSSTS_Msk  (0x1000UL) /* CSSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_ATREPM_Pos (10UL)	/* ATREPM (Bit 10) */
-#define LINK_REG_PIPE_CTR_ATREPM_Msk (0x400UL)	/* ATREPM (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_ACLRM_Pos  (9UL)	/* ACLRM (Bit 9) */
-#define LINK_REG_PIPE_CTR_ACLRM_Msk  (0x200UL)	/* ACLRM (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_SQCLR_Pos  (8UL)	/* SQCLR (Bit 8) */
-#define LINK_REG_PIPE_CTR_SQCLR_Msk  (0x100UL)	/* SQCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_SQSET_Pos  (7UL)	/* SQSET (Bit 7) */
-#define LINK_REG_PIPE_CTR_SQSET_Msk  (0x80UL)	/* SQSET (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_SQMON_Pos  (6UL)	/* SQMON (Bit 6) */
-#define LINK_REG_PIPE_CTR_SQMON_Msk  (0x40UL)	/* SQMON (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_PBUSY_Pos  (5UL)	/* PBUSY (Bit 5) */
-#define LINK_REG_PIPE_CTR_PBUSY_Msk  (0x20UL)	/* PBUSY (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_PID_Pos    (0UL)	/* PID (Bit 0) */
-#define LINK_REG_PIPE_CTR_PID_Msk    (0x3UL)	/* PID (Bitfield-Mask: 0x03) */
-/* DEVADD */
-#define LINK_REG_DEVADD_UPPHUB_Pos  (11UL)     /* UPPHUB (Bit 11) */
-#define LINK_REG_DEVADD_UPPHUB_Msk  (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */
-#define LINK_REG_DEVADD_HUBPORT_Pos (8UL)      /* HUBPORT (Bit 8) */
-#define LINK_REG_DEVADD_HUBPORT_Msk (0x700UL)  /* HUBPORT (Bitfield-Mask: 0x07) */
-#define LINK_REG_DEVADD_USBSPD_Pos  (6UL)      /* USBSPD (Bit 6) */
-#define LINK_REG_DEVADD_USBSPD_Msk  (0xc0UL)   /* USBSPD (Bitfield-Mask: 0x03) */
-/* USBBCCTRL0 */
-#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos  (9UL)     /* PDDETSTS0 (Bit 9) */
-#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk  (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL)     /* CHGDETSTS0 (Bit 8) */
-#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL) /* CHGDETSTS0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_BATCHGE0_Pos   (7UL)     /* BATCHGE0 (Bit 7) */
-#define LINK_REG_USBBCCTRL0_BATCHGE0_Msk   (0x80UL)  /* BATCHGE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_VDMSRCE0_Pos   (5UL)     /* VDMSRCE0 (Bit 5) */
-#define LINK_REG_USBBCCTRL0_VDMSRCE0_Msk   (0x20UL)  /* VDMSRCE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_IDPSINKE0_Pos  (4UL)     /* IDPSINKE0 (Bit 4) */
-#define LINK_REG_USBBCCTRL0_IDPSINKE0_Msk  (0x10UL)  /* IDPSINKE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_VDPSRCE0_Pos   (3UL)     /* VDPSRCE0 (Bit 3) */
-#define LINK_REG_USBBCCTRL0_VDPSRCE0_Msk   (0x8UL)   /* VDPSRCE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_IDMSINKE0_Pos  (2UL)     /* IDMSINKE0 (Bit 2) */
-#define LINK_REG_USBBCCTRL0_IDMSINKE0_Msk  (0x4UL)   /* IDMSINKE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_IDPSRCE0_Pos   (1UL)     /* IDPSRCE0 (Bit 1) */
-#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk   (0x2UL)   /* IDPSRCE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_RPDME0_Pos	   (0UL)     /* RPDME0 (Bit 0) */
-#define LINK_REG_USBBCCTRL0_RPDME0_Msk	   (0x1UL)   /* RPDME0 (Bitfield-Mask: 0x01) */
-/* UCKSEL */
-#define LINK_REG_UCKSEL_UCKSELC_Pos (0UL)   /* UCKSELC (Bit 0) */
-#define LINK_REG_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */
-/* USBMC */
-#define LINK_REG_USBMC_VDCEN_Pos   (7UL)    /* VDCEN (Bit 7) */
-#define LINK_REG_USBMC_VDCEN_Msk   (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBMC_VDDUSBE_Pos (0UL)    /* VDDUSBE (Bit 0) */
-#define LINK_REG_USBMC_VDDUSBE_Msk (0x1UL)  /* VDDUSBE (Bitfield-Mask: 0x01) */
-/* PHYSLEW */
-#define LINK_REG_PHYSLEW_SLEWF01_Pos (3UL)   /* SLEWF01 (Bit 3) */
-#define LINK_REG_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSLEW_SLEWF00_Pos (2UL)   /* SLEWF00 (Bit 2) */
-#define LINK_REG_PHYSLEW_SLEWF00_Msk (0x4UL) /* SLEWF00 (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSLEW_SLEWR01_Pos (1UL)   /* SLEWR01 (Bit 1) */
-#define LINK_REG_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSLEW_SLEWR00_Pos (0UL)   /* SLEWR00 (Bit 0) */
-#define LINK_REG_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */
-/* LPCTRL */
-#define LINK_REG_LPCTRL_HWUPM_Pos (7UL)	   /* HWUPM (Bit 7) */
-#define LINK_REG_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */
-/* LPSTS */
-#define LINK_REG_LPSTS_SUSPENDM_Pos (14UL)     /* SUSPENDM (Bit 14) */
-#define LINK_REG_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */
-/* BCCTRL */
-#define LINK_REG_BCCTRL_PDDETSTS_Pos  (9UL)	/* PDDETSTS (Bit 9) */
-#define LINK_REG_BCCTRL_PDDETSTS_Msk  (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_CHGDETSTS_Pos (8UL)	/* CHGDETSTS (Bit 8) */
-#define LINK_REG_BCCTRL_CHGDETSTS_Msk (0x100UL) /* CHGDETSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_DCPMODE_Pos   (5UL)	/* DCPMODE (Bit 5) */
-#define LINK_REG_BCCTRL_DCPMODE_Msk   (0x20UL)	/* DCPMODE (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_VDMSRCE_Pos   (4UL)	/* VDMSRCE (Bit 4) */
-#define LINK_REG_BCCTRL_VDMSRCE_Msk   (0x10UL)	/* VDMSRCE (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_IDPSINKE_Pos  (3UL)	/* IDPSINKE (Bit 3) */
-#define LINK_REG_BCCTRL_IDPSINKE_Msk  (0x8UL)	/* IDPSINKE (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_VDPSRCE_Pos   (2UL)	/* VDPSRCE (Bit 2) */
-#define LINK_REG_BCCTRL_VDPSRCE_Msk   (0x4UL)	/* VDPSRCE (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_IDMSINKE_Pos  (1UL)	/* IDMSINKE (Bit 1) */
-#define LINK_REG_BCCTRL_IDMSINKE_Msk  (0x2UL)	/* IDMSINKE (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_IDPSRCE_Pos   (0UL)	/* IDPSRCE (Bit 0) */
-#define LINK_REG_BCCTRL_IDPSRCE_Msk   (0x1UL)	/* IDPSRCE (Bitfield-Mask: 0x01) */
-/* PL1CTRL1 */
-#define LINK_REG_PL1CTRL1_L1EXTMD_Pos  (14UL)	  /* L1EXTMD (Bit 14) */
-#define LINK_REG_PL1CTRL1_L1EXTMD_Msk  (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */
-#define LINK_REG_PL1CTRL1_HIRDTHR_Pos  (8UL)	  /* HIRDTHR (Bit 8) */
-#define LINK_REG_PL1CTRL1_HIRDTHR_Msk  (0xf00UL)  /* HIRDTHR (Bitfield-Mask: 0x0f) */
-#define LINK_REG_PL1CTRL1_DVSQ_Pos     (4UL)	  /* DVSQ (Bit 4) */
-#define LINK_REG_PL1CTRL1_DVSQ_Msk     (0xf0UL)	  /* DVSQ (Bitfield-Mask: 0x0f) */
-#define LINK_REG_PL1CTRL1_L1NEGOMD_Pos (3UL)	  /* L1NEGOMD (Bit 3) */
-#define LINK_REG_PL1CTRL1_L1NEGOMD_Msk (0x8UL)	  /* L1NEGOMD (Bitfield-Mask: 0x01) */
-#define LINK_REG_PL1CTRL1_L1RESPMD_Pos (1UL)	  /* L1RESPMD (Bit 1) */
-#define LINK_REG_PL1CTRL1_L1RESPMD_Msk (0x6UL)	  /* L1RESPMD (Bitfield-Mask: 0x03) */
-#define LINK_REG_PL1CTRL1_L1RESPEN_Pos (0UL)	  /* L1RESPEN (Bit 0) */
-#define LINK_REG_PL1CTRL1_L1RESPEN_Msk (0x1UL)	  /* L1RESPEN (Bitfield-Mask: 0x01) */
-/* PL1CTRL2 */
-#define LINK_REG_PL1CTRL2_RWEMON_Pos  (12UL)	 /* RWEMON (Bit 12) */
-#define LINK_REG_PL1CTRL2_RWEMON_Msk  (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */
-#define LINK_REG_PL1CTRL2_HIRDMON_Pos (8UL)	 /* HIRDMON (Bit 8) */
-#define LINK_REG_PL1CTRL2_HIRDMON_Msk (0xf00UL)	 /* HIRDMON (Bitfield-Mask: 0x0f) */
-/* HL1CTRL1 */
-#define LINK_REG_HL1CTRL1_L1STATUS_Pos (1UL)   /* L1STATUS (Bit 1) */
-#define LINK_REG_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */
-#define LINK_REG_HL1CTRL1_L1REQ_Pos    (0UL)   /* L1REQ (Bit 0) */
-#define LINK_REG_HL1CTRL1_L1REQ_Msk    (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */
-/* HL1CTRL2 */
-#define LINK_REG_HL1CTRL2_BESL_Pos   (15UL)	/* BESL (Bit 15) */
-#define LINK_REG_HL1CTRL2_BESL_Msk   (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */
-#define LINK_REG_HL1CTRL2_L1RWE_Pos  (12UL)	/* L1RWE (Bit 12) */
-#define LINK_REG_HL1CTRL2_L1RWE_Msk  (0x1000UL) /* L1RWE (Bitfield-Mask: 0x01) */
-#define LINK_REG_HL1CTRL2_HIRD_Pos   (8UL)	/* HIRD (Bit 8) */
-#define LINK_REG_HL1CTRL2_HIRD_Msk   (0xf00UL)	/* HIRD (Bitfield-Mask: 0x0f) */
-#define LINK_REG_HL1CTRL2_L1ADDR_Pos (0UL)	/* L1ADDR (Bit 0) */
-#define LINK_REG_HL1CTRL2_L1ADDR_Msk (0xfUL)	/* L1ADDR (Bitfield-Mask: 0x0f) */
-/* DPUSR0R */
-#define LINK_REG_DPUSR0R_DVBSTSHM_Pos (23UL)	   /* DVBSTSHM (Bit 23) */
-#define LINK_REG_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_DOVCBHM_Pos  (21UL)	   /* DOVCBHM (Bit 21) */
-#define LINK_REG_DPUSR0R_DOVCBHM_Msk  (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_DOVCAHM_Pos  (20UL)	   /* DOVCAHM (Bit 20) */
-#define LINK_REG_DPUSR0R_DOVCAHM_Msk  (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */
-/* DPUSR1R */
-#define LINK_REG_DPUSR1R_DVBSTSH_Pos  (23UL)	   /* DVBSTSH (Bit 23) */
-#define LINK_REG_DPUSR1R_DVBSTSH_Msk  (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_DOVCBH_Pos   (21UL)	   /* DOVCBH (Bit 21) */
-#define LINK_REG_DPUSR1R_DOVCBH_Msk   (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_DOVCAH_Pos   (20UL)	   /* DOVCAH (Bit 20) */
-#define LINK_REG_DPUSR1R_DOVCAH_Msk   (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_DVBSTSHE_Pos (7UL)	   /* DVBSTSHE (Bit 7) */
-#define LINK_REG_DPUSR1R_DVBSTSHE_Msk (0x80UL)	   /* DVBSTSHE (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_DOVCBHE_Pos  (5UL)	   /* DOVCBHE (Bit 5) */
-#define LINK_REG_DPUSR1R_DOVCBHE_Msk  (0x20UL)	   /* DOVCBHE (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_DOVCAHE_Pos  (4UL)	   /* DOVCAHE (Bit 4) */
-#define LINK_REG_DPUSR1R_DOVCAHE_Msk  (0x10UL)	   /* DOVCAHE (Bitfield-Mask: 0x01) */
-/* DPUSR2R */
-#define LINK_REG_DPUSR2R_DMINTE_Pos (9UL)     /* DMINTE (Bit 9) */
-#define LINK_REG_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR2R_DPINTE_Pos (8UL)     /* DPINTE (Bit 8) */
-#define LINK_REG_DPUSR2R_DPINTE_Msk (0x100UL) /* DPINTE (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR2R_DMVAL_Pos  (5UL)     /* DMVAL (Bit 5) */
-#define LINK_REG_DPUSR2R_DMVAL_Msk  (0x20UL)  /* DMVAL (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR2R_DPVAL_Pos  (4UL)     /* DPVAL (Bit 4) */
-#define LINK_REG_DPUSR2R_DPVAL_Msk  (0x10UL)  /* DPVAL (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR2R_DMINT_Pos  (1UL)     /* DMINT (Bit 1) */
-#define LINK_REG_DPUSR2R_DMINT_Msk  (0x2UL)   /* DMINT (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR2R_DPINT_Pos  (0UL)     /* DPINT (Bit 0) */
-#define LINK_REG_DPUSR2R_DPINT_Msk  (0x1UL)   /* DPINT (Bitfield-Mask: 0x01) */
-/* DPUSRCR */
-#define LINK_REG_DPUSRCR_FIXPHYPD_Pos (1UL)   /* FIXPHYPD (Bit 1) */
-#define LINK_REG_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSRCR_FIXPHY_Pos   (0UL)   /* FIXPHY (Bit 0) */
-#define LINK_REG_DPUSRCR_FIXPHY_Msk   (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */
-/* DPUSR0R_FS */
-#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos (23UL)	     /* DVBSTS0 (Bit 23) */
-#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos	(21UL)	     /* DOVCB0 (Bit 21) */
-#define LINK_REG_DPUSR0R_FS_DOVCB0_Msk	(0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_DOVCA0_Pos	(20UL)	     /* DOVCA0 (Bit 20) */
-#define LINK_REG_DPUSR0R_FS_DOVCA0_Msk	(0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_DM0_Pos	(17UL)	     /* DM0 (Bit 17) */
-#define LINK_REG_DPUSR0R_FS_DM0_Msk	(0x20000UL)  /* DM0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_DP0_Pos	(16UL)	     /* DP0 (Bit 16) */
-#define LINK_REG_DPUSR0R_FS_DP0_Msk	(0x10000UL)  /* DP0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_FIXPHY0_Pos (4UL)	     /* FIXPHY0 (Bit 4) */
-#define LINK_REG_DPUSR0R_FS_FIXPHY0_Msk (0x10UL)     /* FIXPHY0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_DRPD0_Pos	(3UL)	     /* DRPD0 (Bit 3) */
-#define LINK_REG_DPUSR0R_FS_DRPD0_Msk	(0x8UL)	     /* DRPD0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_RPUE0_Pos	(1UL)	     /* RPUE0 (Bit 1) */
-#define LINK_REG_DPUSR0R_FS_RPUE0_Msk	(0x2UL)	     /* RPUE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_SRPC0_Pos	(0UL)	     /* SRPC0 (Bit 0) */
-#define LINK_REG_DPUSR0R_FS_SRPC0_Msk	(0x1UL)	     /* SRPC0 (Bitfield-Mask: 0x01) */
-/* DPUSR1R_FS */
-#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos	  (23UL)       /* DVBINT0 (Bit 23) */
-#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk	  (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos  (21UL)       /* DOVRCRB0 (Bit 21) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Msk  (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Pos  (20UL)       /* DOVRCRA0 (Bit 20) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Msk  (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DMINT0_Pos	  (17UL)       /* DMINT0 (Bit 17) */
-#define LINK_REG_DPUSR1R_FS_DMINT0_Msk	  (0x20000UL)  /* DMINT0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DPINT0_Pos	  (16UL)       /* DPINT0 (Bit 16) */
-#define LINK_REG_DPUSR1R_FS_DPINT0_Msk	  (0x10000UL)  /* DPINT0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DVBSE0_Pos	  (7UL)	       /* DVBSE0 (Bit 7) */
-#define LINK_REG_DPUSR1R_FS_DVBSE0_Msk	  (0x80UL)     /* DVBSE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Pos (5UL)	       /* DOVRCRBE0 (Bit 5) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Msk (0x20UL)     /* DOVRCRBE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Pos (4UL)	       /* DOVRCRAE0 (Bit 4) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Msk (0x10UL)     /* DOVRCRAE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DMINTE0_Pos	  (1UL)	       /* DMINTE0 (Bit 1) */
-#define LINK_REG_DPUSR1R_FS_DMINTE0_Msk	  (0x2UL)      /* DMINTE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos	  (0UL)	       /* DPINTE0 (Bit 0) */
-#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk	  (0x1UL)      /* DPINTE0 (Bitfield-Mask: 0x01) */
+// N
+#define LINK_REG_PIPE_TR_N_TRNCNT_Pos      (0UL)        /* TRNCNT (Bit 0) */
+#define LINK_REG_PIPE_TR_N_TRNCNT_Msk      (0xffffUL)   /* TRNCNT (Bitfield-Mask: 0xffff) */
+
+// LINK_REG
+
+// SYSCFG
+#define LINK_REG_SYSCFG_SCKE_Pos           (10UL)       /* SCKE (Bit 10) */
+#define LINK_REG_SYSCFG_SCKE_Msk           (0x400UL)    /* SCKE (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_CNEN_Pos           (8UL)        /* CNEN (Bit 8) */
+#define LINK_REG_SYSCFG_CNEN_Msk           (0x100UL)    /* CNEN (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_DCFM_Pos           (6UL)        /* DCFM (Bit 6) */
+#define LINK_REG_SYSCFG_DCFM_Msk           (0x40UL)     /* DCFM (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_DRPD_Pos           (5UL)        /* DRPD (Bit 5) */
+#define LINK_REG_SYSCFG_DRPD_Msk           (0x20UL)     /* DRPD (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_DPRPU_Pos          (4UL)        /* DPRPU (Bit 4) */
+#define LINK_REG_SYSCFG_DPRPU_Msk          (0x10UL)     /* DPRPU (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_DMRPU_Pos          (3UL)        /* DMRPU (Bit 3) */
+#define LINK_REG_SYSCFG_DMRPU_Msk          (0x8UL)      /* DMRPU (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSCFG_USBE_Pos           (0UL)        /* USBE (Bit 0) */
+#define LINK_REG_SYSCFG_USBE_Msk           (0x1UL)      /* USBE (Bitfield-Mask: 0x01) */
+
+// BUSWAIT
+#define LINK_REG_BUSWAIT_BWAIT_Pos         (0UL)        /* BWAIT (Bit 0) */
+#define LINK_REG_BUSWAIT_BWAIT_Msk         (0xfUL)      /* BWAIT (Bitfield-Mask: 0x0f) */
+
+// SYSSTS0
+#define LINK_REG_SYSSTS0_OVCMON_Pos        (14UL)       /* OVCMON (Bit 14) */
+#define LINK_REG_SYSSTS0_OVCMON_Msk        (0xc000UL)   /* OVCMON (Bitfield-Mask: 0x03) */
+#define LINK_REG_SYSSTS0_HTACT_Pos         (6UL)        /* HTACT (Bit 6) */
+#define LINK_REG_SYSSTS0_HTACT_Msk         (0x40UL)     /* HTACT (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSSTS0_SOFEA_Pos         (5UL)        /* SOFEA (Bit 5) */
+#define LINK_REG_SYSSTS0_SOFEA_Msk         (0x20UL)     /* SOFEA (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSSTS0_IDMON_Pos         (2UL)        /* IDMON (Bit 2) */
+#define LINK_REG_SYSSTS0_IDMON_Msk         (0x4UL)      /* IDMON (Bitfield-Mask: 0x01) */
+#define LINK_REG_SYSSTS0_LNST_Pos          (0UL)        /* LNST (Bit 0) */
+#define LINK_REG_SYSSTS0_LNST_Msk          (0x3UL)      /* LNST (Bitfield-Mask: 0x03) */
+
+// PLLSTA
+#define LINK_REG_PLLSTA_PLLLOCK_Pos        (0UL)        /* PLLLOCK (Bit 0) */
+#define LINK_REG_PLLSTA_PLLLOCK_Msk        (0x1UL)      /* PLLLOCK (Bitfield-Mask: 0x01) */
+
+// DVSTCTR0
+#define LINK_REG_DVSTCTR0_HNPBTOA_Pos      (11UL)       /* HNPBTOA (Bit 11) */
+#define LINK_REG_DVSTCTR0_HNPBTOA_Msk      (0x800UL)    /* HNPBTOA (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_EXICEN_Pos       (10UL)       /* EXICEN (Bit 10) */
+#define LINK_REG_DVSTCTR0_EXICEN_Msk       (0x400UL)    /* EXICEN (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_VBUSEN_Pos       (9UL)        /* VBUSEN (Bit 9) */
+#define LINK_REG_DVSTCTR0_VBUSEN_Msk       (0x200UL)    /* VBUSEN (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_WKUP_Pos         (8UL)        /* WKUP (Bit 8) */
+#define LINK_REG_DVSTCTR0_WKUP_Msk         (0x100UL)    /* WKUP (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_RWUPE_Pos        (7UL)        /* RWUPE (Bit 7) */
+#define LINK_REG_DVSTCTR0_RWUPE_Msk        (0x80UL)     /* RWUPE (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_USBRST_Pos       (6UL)        /* USBRST (Bit 6) */
+#define LINK_REG_DVSTCTR0_USBRST_Msk       (0x40UL)     /* USBRST (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_RESUME_Pos       (5UL)        /* RESUME (Bit 5) */
+#define LINK_REG_DVSTCTR0_RESUME_Msk       (0x20UL)     /* RESUME (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_UACT_Pos         (4UL)        /* UACT (Bit 4) */
+#define LINK_REG_DVSTCTR0_UACT_Msk         (0x10UL)     /* UACT (Bitfield-Mask: 0x01) */
+#define LINK_REG_DVSTCTR0_RHST_Pos         (0UL)        /* RHST (Bit 0) */
+#define LINK_REG_DVSTCTR0_RHST_Msk         (0x7UL)      /* RHST (Bitfield-Mask: 0x07) */
+
+// TESTMODE
+#define LINK_REG_TESTMODE_UTST_Pos         (0UL)        /* UTST (Bit 0) */
+#define LINK_REG_TESTMODE_UTST_Msk         (0xfUL)      /* UTST (Bitfield-Mask: 0x0f) */
+
+// CFIFOSEL
+#define LINK_REG_CFIFOSEL_RCNT_Pos         (15UL)       /* RCNT (Bit 15) */
+#define LINK_REG_CFIFOSEL_RCNT_Msk         (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOSEL_REW_Pos          (14UL)       /* REW (Bit 14) */
+#define LINK_REG_CFIFOSEL_REW_Msk          (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOSEL_MBW_Pos          (10UL)       /* MBW (Bit 10) */
+#define LINK_REG_CFIFOSEL_MBW_Msk          (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define LINK_REG_CFIFOSEL_BIGEND_Pos       (8UL)        /* BIGEND (Bit 8) */
+#define LINK_REG_CFIFOSEL_BIGEND_Msk       (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOSEL_ISEL_Pos         (5UL)        /* ISEL (Bit 5) */
+#define LINK_REG_CFIFOSEL_ISEL_Msk         (0x20UL)     /* ISEL (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOSEL_CURPIPE_Pos      (0UL)        /* CURPIPE (Bit 0) */
+#define LINK_REG_CFIFOSEL_CURPIPE_Msk      (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+
+// CFIFOCTR
+#define LINK_REG_CFIFOCTR_BVAL_Pos         (15UL)       /* BVAL (Bit 15) */
+#define LINK_REG_CFIFOCTR_BVAL_Msk         (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOCTR_BCLR_Pos         (14UL)       /* BCLR (Bit 14) */
+#define LINK_REG_CFIFOCTR_BCLR_Msk         (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOCTR_FRDY_Pos         (13UL)       /* FRDY (Bit 13) */
+#define LINK_REG_CFIFOCTR_FRDY_Msk         (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define LINK_REG_CFIFOCTR_DTLN_Pos         (0UL)        /* DTLN (Bit 0) */
+#define LINK_REG_CFIFOCTR_DTLN_Msk         (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+
+// D0FIFOSEL
+#define LINK_REG_D0FIFOSEL_RCNT_Pos        (15UL)       /* RCNT (Bit 15) */
+#define LINK_REG_D0FIFOSEL_RCNT_Msk        (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOSEL_REW_Pos         (14UL)       /* REW (Bit 14) */
+#define LINK_REG_D0FIFOSEL_REW_Msk         (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOSEL_DCLRM_Pos       (13UL)       /* DCLRM (Bit 13) */
+#define LINK_REG_D0FIFOSEL_DCLRM_Msk       (0x2000UL)   /* DCLRM (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOSEL_DREQE_Pos       (12UL)       /* DREQE (Bit 12) */
+#define LINK_REG_D0FIFOSEL_DREQE_Msk       (0x1000UL)   /* DREQE (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOSEL_MBW_Pos         (10UL)       /* MBW (Bit 10) */
+#define LINK_REG_D0FIFOSEL_MBW_Msk         (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define LINK_REG_D0FIFOSEL_BIGEND_Pos      (8UL)        /* BIGEND (Bit 8) */
+#define LINK_REG_D0FIFOSEL_BIGEND_Msk      (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOSEL_CURPIPE_Pos     (0UL)        /* CURPIPE (Bit 0) */
+#define LINK_REG_D0FIFOSEL_CURPIPE_Msk     (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+
+// D0FIFOCTR
+#define LINK_REG_D0FIFOCTR_BVAL_Pos        (15UL)       /* BVAL (Bit 15) */
+#define LINK_REG_D0FIFOCTR_BVAL_Msk        (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOCTR_BCLR_Pos        (14UL)       /* BCLR (Bit 14) */
+#define LINK_REG_D0FIFOCTR_BCLR_Msk        (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOCTR_FRDY_Pos        (13UL)       /* FRDY (Bit 13) */
+#define LINK_REG_D0FIFOCTR_FRDY_Msk        (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define LINK_REG_D0FIFOCTR_DTLN_Pos        (0UL)        /* DTLN (Bit 0) */
+#define LINK_REG_D0FIFOCTR_DTLN_Msk        (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+
+// D1FIFOSEL
+#define LINK_REG_D1FIFOSEL_RCNT_Pos        (15UL)       /* RCNT (Bit 15) */
+#define LINK_REG_D1FIFOSEL_RCNT_Msk        (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOSEL_REW_Pos         (14UL)       /* REW (Bit 14) */
+#define LINK_REG_D1FIFOSEL_REW_Msk         (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOSEL_DCLRM_Pos       (13UL)       /* DCLRM (Bit 13) */
+#define LINK_REG_D1FIFOSEL_DCLRM_Msk       (0x2000UL)   /* DCLRM (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOSEL_DREQE_Pos       (12UL)       /* DREQE (Bit 12) */
+#define LINK_REG_D1FIFOSEL_DREQE_Msk       (0x1000UL)   /* DREQE (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOSEL_MBW_Pos         (10UL)       /* MBW (Bit 10) */
+#define LINK_REG_D1FIFOSEL_MBW_Msk         (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define LINK_REG_D1FIFOSEL_BIGEND_Pos      (8UL)        /* BIGEND (Bit 8) */
+#define LINK_REG_D1FIFOSEL_BIGEND_Msk      (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOSEL_CURPIPE_Pos     (0UL)        /* CURPIPE (Bit 0) */
+#define LINK_REG_D1FIFOSEL_CURPIPE_Msk     (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+
+// D1FIFOCTR
+#define LINK_REG_D1FIFOCTR_BVAL_Pos        (15UL)       /* BVAL (Bit 15) */
+#define LINK_REG_D1FIFOCTR_BVAL_Msk        (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOCTR_BCLR_Pos        (14UL)       /* BCLR (Bit 14) */
+#define LINK_REG_D1FIFOCTR_BCLR_Msk        (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOCTR_FRDY_Pos        (13UL)       /* FRDY (Bit 13) */
+#define LINK_REG_D1FIFOCTR_FRDY_Msk        (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define LINK_REG_D1FIFOCTR_DTLN_Pos        (0UL)        /* DTLN (Bit 0) */
+#define LINK_REG_D1FIFOCTR_DTLN_Msk        (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+
+// INTENB0
+#define LINK_REG_INTENB0_VBSE_Pos          (15UL)       /* VBSE (Bit 15) */
+#define LINK_REG_INTENB0_VBSE_Msk          (0x8000UL)   /* VBSE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_RSME_Pos          (14UL)       /* RSME (Bit 14) */
+#define LINK_REG_INTENB0_RSME_Msk          (0x4000UL)   /* RSME (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_SOFE_Pos          (13UL)       /* SOFE (Bit 13) */
+#define LINK_REG_INTENB0_SOFE_Msk          (0x2000UL)   /* SOFE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_DVSE_Pos          (12UL)       /* DVSE (Bit 12) */
+#define LINK_REG_INTENB0_DVSE_Msk          (0x1000UL)   /* DVSE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_CTRE_Pos          (11UL)       /* CTRE (Bit 11) */
+#define LINK_REG_INTENB0_CTRE_Msk          (0x800UL)    /* CTRE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_BEMPE_Pos         (10UL)       /* BEMPE (Bit 10) */
+#define LINK_REG_INTENB0_BEMPE_Msk         (0x400UL)    /* BEMPE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_NRDYE_Pos         (9UL)        /* NRDYE (Bit 9) */
+#define LINK_REG_INTENB0_NRDYE_Msk         (0x200UL)    /* NRDYE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB0_BRDYE_Pos         (8UL)        /* BRDYE (Bit 8) */
+#define LINK_REG_INTENB0_BRDYE_Msk         (0x100UL)    /* BRDYE (Bitfield-Mask: 0x01) */
+
+// INTENB1
+#define LINK_REG_INTENB1_OVRCRE_Pos        (15UL)       /* OVRCRE (Bit 15) */
+#define LINK_REG_INTENB1_OVRCRE_Msk        (0x8000UL)   /* OVRCRE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_BCHGE_Pos         (14UL)       /* BCHGE (Bit 14) */
+#define LINK_REG_INTENB1_BCHGE_Msk         (0x4000UL)   /* BCHGE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_DTCHE_Pos         (12UL)       /* DTCHE (Bit 12) */
+#define LINK_REG_INTENB1_DTCHE_Msk         (0x1000UL)   /* DTCHE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_ATTCHE_Pos        (11UL)       /* ATTCHE (Bit 11) */
+#define LINK_REG_INTENB1_ATTCHE_Msk        (0x800UL)    /* ATTCHE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_EOFERRE_Pos       (6UL)        /* EOFERRE (Bit 6) */
+#define LINK_REG_INTENB1_EOFERRE_Msk       (0x40UL)     /* EOFERRE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_SIGNE_Pos         (5UL)        /* SIGNE (Bit 5) */
+#define LINK_REG_INTENB1_SIGNE_Msk         (0x20UL)     /* SIGNE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_SACKE_Pos         (4UL)        /* SACKE (Bit 4) */
+#define LINK_REG_INTENB1_SACKE_Msk         (0x10UL)     /* SACKE (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTENB1_PDDETINTE0_Pos    (0UL)        /* PDDETINTE0 (Bit 0) */
+#define LINK_REG_INTENB1_PDDETINTE0_Msk    (0x1UL)      /* PDDETINTE0 (Bitfield-Mask: 0x01) */
+
+// BRDYENB
+#define LINK_REG_BRDYENB_PIPEBRDYE_Pos     (0UL)        /* PIPEBRDYE (Bit 0) */
+#define LINK_REG_BRDYENB_PIPEBRDYE_Msk     (0x1UL)      /* PIPEBRDYE (Bitfield-Mask: 0x01) */
+
+// NRDYENB
+#define LINK_REG_NRDYENB_PIPENRDYE_Pos     (0UL)        /* PIPENRDYE (Bit 0) */
+#define LINK_REG_NRDYENB_PIPENRDYE_Msk     (0x1UL)      /* PIPENRDYE (Bitfield-Mask: 0x01) */
+
+// BEMPENB
+#define LINK_REG_BEMPENB_PIPEBEMPE_Pos     (0UL)        /* PIPEBEMPE (Bit 0) */
+#define LINK_REG_BEMPENB_PIPEBEMPE_Msk     (0x1UL)      /* PIPEBEMPE (Bitfield-Mask: 0x01) */
+
+// SOFCFG
+#define LINK_REG_SOFCFG_TRNENSEL_Pos       (8UL)        /* TRNENSEL (Bit 8) */
+#define LINK_REG_SOFCFG_TRNENSEL_Msk       (0x100UL)    /* TRNENSEL (Bitfield-Mask: 0x01) */
+#define LINK_REG_SOFCFG_BRDYM_Pos          (6UL)        /* BRDYM (Bit 6) */
+#define LINK_REG_SOFCFG_BRDYM_Msk          (0x40UL)     /* BRDYM (Bitfield-Mask: 0x01) */
+#define LINK_REG_SOFCFG_INTL_Pos           (5UL)        /* INTL (Bit 5) */
+#define LINK_REG_SOFCFG_INTL_Msk           (0x20UL)     /* INTL (Bitfield-Mask: 0x01) */
+#define LINK_REG_SOFCFG_EDGESTS_Pos        (4UL)        /* EDGESTS (Bit 4) */
+#define LINK_REG_SOFCFG_EDGESTS_Msk        (0x10UL)     /* EDGESTS (Bitfield-Mask: 0x01) */
+
+// PHYSET
+#define LINK_REG_PHYSET_HSEB_Pos           (15UL)       /* HSEB (Bit 15) */
+#define LINK_REG_PHYSET_HSEB_Msk           (0x8000UL)   /* HSEB (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSET_REPSTART_Pos       (11UL)       /* REPSTART (Bit 11) */
+#define LINK_REG_PHYSET_REPSTART_Msk       (0x800UL)    /* REPSTART (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSET_REPSEL_Pos         (8UL)        /* REPSEL (Bit 8) */
+#define LINK_REG_PHYSET_REPSEL_Msk         (0x300UL)    /* REPSEL (Bitfield-Mask: 0x03) */
+#define LINK_REG_PHYSET_CLKSEL_Pos         (4UL)        /* CLKSEL (Bit 4) */
+#define LINK_REG_PHYSET_CLKSEL_Msk         (0x30UL)     /* CLKSEL (Bitfield-Mask: 0x03) */
+#define LINK_REG_PHYSET_CDPEN_Pos          (3UL)        /* CDPEN (Bit 3) */
+#define LINK_REG_PHYSET_CDPEN_Msk          (0x8UL)      /* CDPEN (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSET_PLLRESET_Pos       (1UL)        /* PLLRESET (Bit 1) */
+#define LINK_REG_PHYSET_PLLRESET_Msk       (0x2UL)      /* PLLRESET (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSET_DIRPD_Pos          (0UL)        /* DIRPD (Bit 0) */
+#define LINK_REG_PHYSET_DIRPD_Msk          (0x1UL)      /* DIRPD (Bitfield-Mask: 0x01) */
+
+// INTSTS0
+#define LINK_REG_INTSTS0_VBINT_Pos         (15UL)       /* VBINT (Bit 15) */
+#define LINK_REG_INTSTS0_VBINT_Msk         (0x8000UL)   /* VBINT (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_RESM_Pos          (14UL)       /* RESM (Bit 14) */
+#define LINK_REG_INTSTS0_RESM_Msk          (0x4000UL)   /* RESM (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_SOFR_Pos          (13UL)       /* SOFR (Bit 13) */
+#define LINK_REG_INTSTS0_SOFR_Msk          (0x2000UL)   /* SOFR (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_DVST_Pos          (12UL)       /* DVST (Bit 12) */
+#define LINK_REG_INTSTS0_DVST_Msk          (0x1000UL)   /* DVST (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_CTRT_Pos          (11UL)       /* CTRT (Bit 11) */
+#define LINK_REG_INTSTS0_CTRT_Msk          (0x800UL)    /* CTRT (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_BEMP_Pos          (10UL)       /* BEMP (Bit 10) */
+#define LINK_REG_INTSTS0_BEMP_Msk          (0x400UL)    /* BEMP (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_NRDY_Pos          (9UL)        /* NRDY (Bit 9) */
+#define LINK_REG_INTSTS0_NRDY_Msk          (0x200UL)    /* NRDY (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_BRDY_Pos          (8UL)        /* BRDY (Bit 8) */
+#define LINK_REG_INTSTS0_BRDY_Msk          (0x100UL)    /* BRDY (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_VBSTS_Pos         (7UL)        /* VBSTS (Bit 7) */
+#define LINK_REG_INTSTS0_VBSTS_Msk         (0x80UL)     /* VBSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_DVSQ_Pos          (4UL)        /* DVSQ (Bit 4) */
+#define LINK_REG_INTSTS0_DVSQ_Msk          (0x70UL)     /* DVSQ (Bitfield-Mask: 0x07) */
+#define LINK_REG_INTSTS0_VALID_Pos         (3UL)        /* VALID (Bit 3) */
+#define LINK_REG_INTSTS0_VALID_Msk         (0x8UL)      /* VALID (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS0_CTSQ_Pos          (0UL)        /* CTSQ (Bit 0) */
+#define LINK_REG_INTSTS0_CTSQ_Msk          (0x7UL)      /* CTSQ (Bitfield-Mask: 0x07) */
+
+// INTSTS1
+#define LINK_REG_INTSTS1_OVRCR_Pos         (15UL)       /* OVRCR (Bit 15) */
+#define LINK_REG_INTSTS1_OVRCR_Msk         (0x8000UL)   /* OVRCR (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_BCHG_Pos          (14UL)       /* BCHG (Bit 14) */
+#define LINK_REG_INTSTS1_BCHG_Msk          (0x4000UL)   /* BCHG (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_DTCH_Pos          (12UL)       /* DTCH (Bit 12) */
+#define LINK_REG_INTSTS1_DTCH_Msk          (0x1000UL)   /* DTCH (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_ATTCH_Pos         (11UL)       /* ATTCH (Bit 11) */
+#define LINK_REG_INTSTS1_ATTCH_Msk         (0x800UL)    /* ATTCH (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_L1RSMEND_Pos      (9UL)        /* L1RSMEND (Bit 9) */
+#define LINK_REG_INTSTS1_L1RSMEND_Msk      (0x200UL)    /* L1RSMEND (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_LPMEND_Pos        (8UL)        /* LPMEND (Bit 8) */
+#define LINK_REG_INTSTS1_LPMEND_Msk        (0x100UL)    /* LPMEND (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_EOFERR_Pos        (6UL)        /* EOFERR (Bit 6) */
+#define LINK_REG_INTSTS1_EOFERR_Msk        (0x40UL)     /* EOFERR (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_SIGN_Pos          (5UL)        /* SIGN (Bit 5) */
+#define LINK_REG_INTSTS1_SIGN_Msk          (0x20UL)     /* SIGN (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_SACK_Pos          (4UL)        /* SACK (Bit 4) */
+#define LINK_REG_INTSTS1_SACK_Msk          (0x10UL)     /* SACK (Bitfield-Mask: 0x01) */
+#define LINK_REG_INTSTS1_PDDETINT0_Pos     (0UL)        /* PDDETINT0 (Bit 0) */
+#define LINK_REG_INTSTS1_PDDETINT0_Msk     (0x1UL)      /* PDDETINT0 (Bitfield-Mask: 0x01) */
+
+// BRDYSTS
+#define LINK_REG_BRDYSTS_PIPEBRDY_Pos      (0UL)        /* PIPEBRDY (Bit 0) */
+#define LINK_REG_BRDYSTS_PIPEBRDY_Msk      (0x1UL)      /* PIPEBRDY (Bitfield-Mask: 0x01) */
+
+// NRDYSTS
+#define LINK_REG_NRDYSTS_PIPENRDY_Pos      (0UL)        /* PIPENRDY (Bit 0) */
+#define LINK_REG_NRDYSTS_PIPENRDY_Msk      (0x1UL)      /* PIPENRDY (Bitfield-Mask: 0x01) */
+
+// BEMPSTS
+#define LINK_REG_BEMPSTS_PIPEBEMP_Pos      (0UL)        /* PIPEBEMP (Bit 0) */
+#define LINK_REG_BEMPSTS_PIPEBEMP_Msk      (0x1UL)      /* PIPEBEMP (Bitfield-Mask: 0x01) */
+
+// FRMNUM
+#define LINK_REG_FRMNUM_OVRN_Pos           (15UL)       /* OVRN (Bit 15) */
+#define LINK_REG_FRMNUM_OVRN_Msk           (0x8000UL)   /* OVRN (Bitfield-Mask: 0x01) */
+#define LINK_REG_FRMNUM_CRCE_Pos           (14UL)       /* CRCE (Bit 14) */
+#define LINK_REG_FRMNUM_CRCE_Msk           (0x4000UL)   /* CRCE (Bitfield-Mask: 0x01) */
+#define LINK_REG_FRMNUM_FRNM_Pos           (0UL)        /* FRNM (Bit 0) */
+#define LINK_REG_FRMNUM_FRNM_Msk           (0x7ffUL)    /* FRNM (Bitfield-Mask: 0x7ff) */
+
+// UFRMNUM
+#define LINK_REG_UFRMNUM_DVCHG_Pos         (15UL)       /* DVCHG (Bit 15) */
+#define LINK_REG_UFRMNUM_DVCHG_Msk         (0x8000UL)   /* DVCHG (Bitfield-Mask: 0x01) */
+#define LINK_REG_UFRMNUM_UFRNM_Pos         (0UL)        /* UFRNM (Bit 0) */
+#define LINK_REG_UFRMNUM_UFRNM_Msk         (0x7UL)      /* UFRNM (Bitfield-Mask: 0x07) */
+
+// USBADDR
+#define LINK_REG_USBADDR_STSRECOV0_Pos     (8UL)        /* STSRECOV0 (Bit 8) */
+#define LINK_REG_USBADDR_STSRECOV0_Msk     (0x700UL)    /* STSRECOV0 (Bitfield-Mask: 0x07) */
+#define LINK_REG_USBADDR_USBADDR_Pos       (0UL)        /* USBADDR (Bit 0) */
+#define LINK_REG_USBADDR_USBADDR_Msk       (0x7fUL)     /* USBADDR (Bitfield-Mask: 0x7f) */
+
+// USBREQ
+#define LINK_REG_USBREQ_BREQUEST_Pos       (8UL)        /* BREQUEST (Bit 8) */
+#define LINK_REG_USBREQ_BREQUEST_Msk       (0xff00UL)   /* BREQUEST (Bitfield-Mask: 0xff) */
+#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos  (0UL)        /* BMREQUESTTYPE (Bit 0) */
+#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk  (0xffUL)     /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */
+
+// USBVAL
+#define LINK_REG_USBVAL_WVALUE_Pos         (0UL)        /* WVALUE (Bit 0) */
+#define LINK_REG_USBVAL_WVALUE_Msk         (0xffffUL)   /* WVALUE (Bitfield-Mask: 0xffff) */
+
+// USBINDX
+#define LINK_REG_USBINDX_WINDEX_Pos        (0UL)        /* WINDEX (Bit 0) */
+#define LINK_REG_USBINDX_WINDEX_Msk        (0xffffUL)   /* WINDEX (Bitfield-Mask: 0xffff) */
+
+// USBLENG
+#define LINK_REG_USBLENG_WLENGTH_Pos       (0UL)        /* WLENGTH (Bit 0) */
+#define LINK_REG_USBLENG_WLENGTH_Msk       (0xffffUL)   /* WLENGTH (Bitfield-Mask: 0xffff) */
+
+// DCPCFG
+#define LINK_REG_DCPCFG_CNTMD_Pos          (8UL)        /* CNTMD (Bit 8) */
+#define LINK_REG_DCPCFG_CNTMD_Msk          (0x100UL)    /* CNTMD (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCFG_SHTNAK_Pos         (7UL)        /* SHTNAK (Bit 7) */
+#define LINK_REG_DCPCFG_SHTNAK_Msk         (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCFG_DIR_Pos            (4UL)        /* DIR (Bit 4) */
+#define LINK_REG_DCPCFG_DIR_Msk            (0x10UL)     /* DIR (Bitfield-Mask: 0x01) */
+
+// DCPMAXP
+#define LINK_REG_DCPMAXP_DEVSEL_Pos        (12UL)       /* DEVSEL (Bit 12) */
+#define LINK_REG_DCPMAXP_DEVSEL_Msk        (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
+#define LINK_REG_DCPMAXP_MXPS_Pos          (0UL)        /* MXPS (Bit 0) */
+#define LINK_REG_DCPMAXP_MXPS_Msk          (0x7fUL)     /* MXPS (Bitfield-Mask: 0x7f) */
+
+// DCPCTR
+#define LINK_REG_DCPCTR_BSTS_Pos           (15UL)       /* BSTS (Bit 15) */
+#define LINK_REG_DCPCTR_BSTS_Msk           (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_SUREQ_Pos          (14UL)       /* SUREQ (Bit 14) */
+#define LINK_REG_DCPCTR_SUREQ_Msk          (0x4000UL)   /* SUREQ (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_SUREQCLR_Pos       (11UL)       /* SUREQCLR (Bit 11) */
+#define LINK_REG_DCPCTR_SUREQCLR_Msk       (0x800UL)    /* SUREQCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_SQCLR_Pos          (8UL)        /* SQCLR (Bit 8) */
+#define LINK_REG_DCPCTR_SQCLR_Msk          (0x100UL)    /* SQCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_SQSET_Pos          (7UL)        /* SQSET (Bit 7) */
+#define LINK_REG_DCPCTR_SQSET_Msk          (0x80UL)     /* SQSET (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_SQMON_Pos          (6UL)        /* SQMON (Bit 6) */
+#define LINK_REG_DCPCTR_SQMON_Msk          (0x40UL)     /* SQMON (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_PBUSY_Pos          (5UL)        /* PBUSY (Bit 5) */
+#define LINK_REG_DCPCTR_PBUSY_Msk          (0x20UL)     /* PBUSY (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_CCPL_Pos           (2UL)        /* CCPL (Bit 2) */
+#define LINK_REG_DCPCTR_CCPL_Msk           (0x4UL)      /* CCPL (Bitfield-Mask: 0x01) */
+#define LINK_REG_DCPCTR_PID_Pos            (0UL)        /* PID (Bit 0) */
+#define LINK_REG_DCPCTR_PID_Msk            (0x3UL)      /* PID (Bitfield-Mask: 0x03) */
+
+// PIPESEL
+#define LINK_REG_PIPESEL_PIPESEL_Pos       (0UL)        /* PIPESEL (Bit 0) */
+#define LINK_REG_PIPESEL_PIPESEL_Msk       (0xfUL)      /* PIPESEL (Bitfield-Mask: 0x0f) */
+
+// PIPECFG
+#define LINK_REG_PIPECFG_TYPE_Pos          (14UL)       /* TYPE (Bit 14) */
+#define LINK_REG_PIPECFG_TYPE_Msk          (0xc000UL)   /* TYPE (Bitfield-Mask: 0x03) */
+#define LINK_REG_PIPECFG_BFRE_Pos          (10UL)       /* BFRE (Bit 10) */
+#define LINK_REG_PIPECFG_BFRE_Msk          (0x400UL)    /* BFRE (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPECFG_DBLB_Pos          (9UL)        /* DBLB (Bit 9) */
+#define LINK_REG_PIPECFG_DBLB_Msk          (0x200UL)    /* DBLB (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPECFG_SHTNAK_Pos        (7UL)        /* SHTNAK (Bit 7) */
+#define LINK_REG_PIPECFG_SHTNAK_Msk        (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPECFG_DIR_Pos           (4UL)        /* DIR (Bit 4) */
+#define LINK_REG_PIPECFG_DIR_Msk           (0x10UL)     /* DIR (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPECFG_EPNUM_Pos         (0UL)        /* EPNUM (Bit 0) */
+#define LINK_REG_PIPECFG_EPNUM_Msk         (0xfUL)      /* EPNUM (Bitfield-Mask: 0x0f) */
+
+// PIPEMAXP
+#define LINK_REG_PIPEMAXP_DEVSEL_Pos       (12UL)       /* DEVSEL (Bit 12) */
+#define LINK_REG_PIPEMAXP_DEVSEL_Msk       (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
+#define LINK_REG_PIPEMAXP_MXPS_Pos         (0UL)        /* MXPS (Bit 0) */
+#define LINK_REG_PIPEMAXP_MXPS_Msk         (0x1ffUL)    /* MXPS (Bitfield-Mask: 0x1ff) */
+
+// PIPEPERI
+#define LINK_REG_PIPEPERI_IFIS_Pos         (12UL)       /* IFIS (Bit 12) */
+#define LINK_REG_PIPEPERI_IFIS_Msk         (0x1000UL)   /* IFIS (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPEPERI_IITV_Pos         (0UL)        /* IITV (Bit 0) */
+#define LINK_REG_PIPEPERI_IITV_Msk         (0x7UL)      /* IITV (Bitfield-Mask: 0x07) */
+
+// PIPE_CTR
+#define LINK_REG_PIPE_CTR_BSTS_Pos         (15UL)       /* BSTS (Bit 15) */
+#define LINK_REG_PIPE_CTR_BSTS_Msk         (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_INBUFM_Pos       (14UL)       /* INBUFM (Bit 14) */
+#define LINK_REG_PIPE_CTR_INBUFM_Msk       (0x4000UL)   /* INBUFM (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_CSCLR_Pos        (13UL)       /* CSCLR (Bit 13) */
+#define LINK_REG_PIPE_CTR_CSCLR_Msk        (0x2000UL)   /* CSCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_CSSTS_Pos        (12UL)       /* CSSTS (Bit 12) */
+#define LINK_REG_PIPE_CTR_CSSTS_Msk        (0x1000UL)   /* CSSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_ATREPM_Pos       (10UL)       /* ATREPM (Bit 10) */
+#define LINK_REG_PIPE_CTR_ATREPM_Msk       (0x400UL)    /* ATREPM (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_ACLRM_Pos        (9UL)        /* ACLRM (Bit 9) */
+#define LINK_REG_PIPE_CTR_ACLRM_Msk        (0x200UL)    /* ACLRM (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_SQCLR_Pos        (8UL)        /* SQCLR (Bit 8) */
+#define LINK_REG_PIPE_CTR_SQCLR_Msk        (0x100UL)    /* SQCLR (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_SQSET_Pos        (7UL)        /* SQSET (Bit 7) */
+#define LINK_REG_PIPE_CTR_SQSET_Msk        (0x80UL)     /* SQSET (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_SQMON_Pos        (6UL)        /* SQMON (Bit 6) */
+#define LINK_REG_PIPE_CTR_SQMON_Msk        (0x40UL)     /* SQMON (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_PBUSY_Pos        (5UL)        /* PBUSY (Bit 5) */
+#define LINK_REG_PIPE_CTR_PBUSY_Msk        (0x20UL)     /* PBUSY (Bitfield-Mask: 0x01) */
+#define LINK_REG_PIPE_CTR_PID_Pos          (0UL)        /* PID (Bit 0) */
+#define LINK_REG_PIPE_CTR_PID_Msk          (0x3UL)      /* PID (Bitfield-Mask: 0x03) */
+
+// DEVADD
+#define LINK_REG_DEVADD_UPPHUB_Pos         (11UL)       /* UPPHUB (Bit 11) */
+#define LINK_REG_DEVADD_UPPHUB_Msk         (0x7800UL)   /* UPPHUB (Bitfield-Mask: 0x0f) */
+#define LINK_REG_DEVADD_HUBPORT_Pos        (8UL)        /* HUBPORT (Bit 8) */
+#define LINK_REG_DEVADD_HUBPORT_Msk        (0x700UL)    /* HUBPORT (Bitfield-Mask: 0x07) */
+#define LINK_REG_DEVADD_USBSPD_Pos         (6UL)        /* USBSPD (Bit 6) */
+#define LINK_REG_DEVADD_USBSPD_Msk         (0xc0UL)     /* USBSPD (Bitfield-Mask: 0x03) */
+
+// USBBCCTRL0
+#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos  (9UL)        /* PDDETSTS0 (Bit 9) */
+#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk  (0x200UL)    /* PDDETSTS0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL)        /* CHGDETSTS0 (Bit 8) */
+#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL)    /* CHGDETSTS0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_BATCHGE0_Pos   (7UL)        /* BATCHGE0 (Bit 7) */
+#define LINK_REG_USBBCCTRL0_BATCHGE0_Msk   (0x80UL)     /* BATCHGE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_VDMSRCE0_Pos   (5UL)        /* VDMSRCE0 (Bit 5) */
+#define LINK_REG_USBBCCTRL0_VDMSRCE0_Msk   (0x20UL)     /* VDMSRCE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_IDPSINKE0_Pos  (4UL)        /* IDPSINKE0 (Bit 4) */
+#define LINK_REG_USBBCCTRL0_IDPSINKE0_Msk  (0x10UL)     /* IDPSINKE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_VDPSRCE0_Pos   (3UL)        /* VDPSRCE0 (Bit 3) */
+#define LINK_REG_USBBCCTRL0_VDPSRCE0_Msk   (0x8UL)      /* VDPSRCE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_IDMSINKE0_Pos  (2UL)        /* IDMSINKE0 (Bit 2) */
+#define LINK_REG_USBBCCTRL0_IDMSINKE0_Msk  (0x4UL)      /* IDMSINKE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_IDPSRCE0_Pos   (1UL)        /* IDPSRCE0 (Bit 1) */
+#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk   (0x2UL)      /* IDPSRCE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBBCCTRL0_RPDME0_Pos     (0UL)        /* RPDME0 (Bit 0) */
+#define LINK_REG_USBBCCTRL0_RPDME0_Msk     (0x1UL)      /* RPDME0 (Bitfield-Mask: 0x01) */
+
+// UCKSEL
+#define LINK_REG_UCKSEL_UCKSELC_Pos        (0UL)        /* UCKSELC (Bit 0) */
+#define LINK_REG_UCKSEL_UCKSELC_Msk        (0x1UL)      /* UCKSELC (Bitfield-Mask: 0x01) */
+
+// USBMC
+#define LINK_REG_USBMC_VDCEN_Pos           (7UL)        /* VDCEN (Bit 7) */
+#define LINK_REG_USBMC_VDCEN_Msk           (0x80UL)     /* VDCEN (Bitfield-Mask: 0x01) */
+#define LINK_REG_USBMC_VDDUSBE_Pos         (0UL)        /* VDDUSBE (Bit 0) */
+#define LINK_REG_USBMC_VDDUSBE_Msk         (0x1UL)      /* VDDUSBE (Bitfield-Mask: 0x01) */
+
+// PHYSLEW
+#define LINK_REG_PHYSLEW_SLEWF01_Pos       (3UL)        /* SLEWF01 (Bit 3) */
+#define LINK_REG_PHYSLEW_SLEWF01_Msk       (0x8UL)      /* SLEWF01 (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSLEW_SLEWF00_Pos       (2UL)        /* SLEWF00 (Bit 2) */
+#define LINK_REG_PHYSLEW_SLEWF00_Msk       (0x4UL)      /* SLEWF00 (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSLEW_SLEWR01_Pos       (1UL)        /* SLEWR01 (Bit 1) */
+#define LINK_REG_PHYSLEW_SLEWR01_Msk       (0x2UL)      /* SLEWR01 (Bitfield-Mask: 0x01) */
+#define LINK_REG_PHYSLEW_SLEWR00_Pos       (0UL)        /* SLEWR00 (Bit 0) */
+#define LINK_REG_PHYSLEW_SLEWR00_Msk       (0x1UL)      /* SLEWR00 (Bitfield-Mask: 0x01) */
+
+// LPCTRL
+#define LINK_REG_LPCTRL_HWUPM_Pos          (7UL)        /* HWUPM (Bit 7) */
+#define LINK_REG_LPCTRL_HWUPM_Msk          (0x80UL)     /* HWUPM (Bitfield-Mask: 0x01) */
+
+// LPSTS
+#define LINK_REG_LPSTS_SUSPENDM_Pos        (14UL)       /* SUSPENDM (Bit 14) */
+#define LINK_REG_LPSTS_SUSPENDM_Msk        (0x4000UL)   /* SUSPENDM (Bitfield-Mask: 0x01) */
+
+// BCCTRL
+#define LINK_REG_BCCTRL_PDDETSTS_Pos       (9UL)        /* PDDETSTS (Bit 9) */
+#define LINK_REG_BCCTRL_PDDETSTS_Msk       (0x200UL)    /* PDDETSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_CHGDETSTS_Pos      (8UL)        /* CHGDETSTS (Bit 8) */
+#define LINK_REG_BCCTRL_CHGDETSTS_Msk      (0x100UL)    /* CHGDETSTS (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_DCPMODE_Pos        (5UL)        /* DCPMODE (Bit 5) */
+#define LINK_REG_BCCTRL_DCPMODE_Msk        (0x20UL)     /* DCPMODE (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_VDMSRCE_Pos        (4UL)        /* VDMSRCE (Bit 4) */
+#define LINK_REG_BCCTRL_VDMSRCE_Msk        (0x10UL)     /* VDMSRCE (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_IDPSINKE_Pos       (3UL)        /* IDPSINKE (Bit 3) */
+#define LINK_REG_BCCTRL_IDPSINKE_Msk       (0x8UL)      /* IDPSINKE (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_VDPSRCE_Pos        (2UL)        /* VDPSRCE (Bit 2) */
+#define LINK_REG_BCCTRL_VDPSRCE_Msk        (0x4UL)      /* VDPSRCE (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_IDMSINKE_Pos       (1UL)        /* IDMSINKE (Bit 1) */
+#define LINK_REG_BCCTRL_IDMSINKE_Msk       (0x2UL)      /* IDMSINKE (Bitfield-Mask: 0x01) */
+#define LINK_REG_BCCTRL_IDPSRCE_Pos        (0UL)        /* IDPSRCE (Bit 0) */
+#define LINK_REG_BCCTRL_IDPSRCE_Msk        (0x1UL)      /* IDPSRCE (Bitfield-Mask: 0x01) */
+
+// PL1CTRL1
+#define LINK_REG_PL1CTRL1_L1EXTMD_Pos      (14UL)       /* L1EXTMD (Bit 14) */
+#define LINK_REG_PL1CTRL1_L1EXTMD_Msk      (0x4000UL)   /* L1EXTMD (Bitfield-Mask: 0x01) */
+#define LINK_REG_PL1CTRL1_HIRDTHR_Pos      (8UL)        /* HIRDTHR (Bit 8) */
+#define LINK_REG_PL1CTRL1_HIRDTHR_Msk      (0xf00UL)    /* HIRDTHR (Bitfield-Mask: 0x0f) */
+#define LINK_REG_PL1CTRL1_DVSQ_Pos         (4UL)        /* DVSQ (Bit 4) */
+#define LINK_REG_PL1CTRL1_DVSQ_Msk         (0xf0UL)     /* DVSQ (Bitfield-Mask: 0x0f) */
+#define LINK_REG_PL1CTRL1_L1NEGOMD_Pos     (3UL)        /* L1NEGOMD (Bit 3) */
+#define LINK_REG_PL1CTRL1_L1NEGOMD_Msk     (0x8UL)      /* L1NEGOMD (Bitfield-Mask: 0x01) */
+#define LINK_REG_PL1CTRL1_L1RESPMD_Pos     (1UL)        /* L1RESPMD (Bit 1) */
+#define LINK_REG_PL1CTRL1_L1RESPMD_Msk     (0x6UL)      /* L1RESPMD (Bitfield-Mask: 0x03) */
+#define LINK_REG_PL1CTRL1_L1RESPEN_Pos     (0UL)        /* L1RESPEN (Bit 0) */
+#define LINK_REG_PL1CTRL1_L1RESPEN_Msk     (0x1UL)      /* L1RESPEN (Bitfield-Mask: 0x01) */
+
+// PL1CTRL2
+#define LINK_REG_PL1CTRL2_RWEMON_Pos       (12UL)       /* RWEMON (Bit 12) */
+#define LINK_REG_PL1CTRL2_RWEMON_Msk       (0x1000UL)   /* RWEMON (Bitfield-Mask: 0x01) */
+#define LINK_REG_PL1CTRL2_HIRDMON_Pos      (8UL)        /* HIRDMON (Bit 8) */
+#define LINK_REG_PL1CTRL2_HIRDMON_Msk      (0xf00UL)    /* HIRDMON (Bitfield-Mask: 0x0f) */
+
+// HL1CTRL1
+#define LINK_REG_HL1CTRL1_L1STATUS_Pos     (1UL)        /* L1STATUS (Bit 1) */
+#define LINK_REG_HL1CTRL1_L1STATUS_Msk     (0x6UL)      /* L1STATUS (Bitfield-Mask: 0x03) */
+#define LINK_REG_HL1CTRL1_L1REQ_Pos        (0UL)        /* L1REQ (Bit 0) */
+#define LINK_REG_HL1CTRL1_L1REQ_Msk        (0x1UL)      /* L1REQ (Bitfield-Mask: 0x01) */
+
+// HL1CTRL2
+#define LINK_REG_HL1CTRL2_BESL_Pos         (15UL)       /* BESL (Bit 15) */
+#define LINK_REG_HL1CTRL2_BESL_Msk         (0x8000UL)   /* BESL (Bitfield-Mask: 0x01) */
+#define LINK_REG_HL1CTRL2_L1RWE_Pos        (12UL)       /* L1RWE (Bit 12) */
+#define LINK_REG_HL1CTRL2_L1RWE_Msk        (0x1000UL)   /* L1RWE (Bitfield-Mask: 0x01) */
+#define LINK_REG_HL1CTRL2_HIRD_Pos         (8UL)        /* HIRD (Bit 8) */
+#define LINK_REG_HL1CTRL2_HIRD_Msk         (0xf00UL)    /* HIRD (Bitfield-Mask: 0x0f) */
+#define LINK_REG_HL1CTRL2_L1ADDR_Pos       (0UL)        /* L1ADDR (Bit 0) */
+#define LINK_REG_HL1CTRL2_L1ADDR_Msk       (0xfUL)      /* L1ADDR (Bitfield-Mask: 0x0f) */
+
+// DPUSR0R
+#define LINK_REG_DPUSR0R_DVBSTSHM_Pos      (23UL)       /* DVBSTSHM (Bit 23) */
+#define LINK_REG_DPUSR0R_DVBSTSHM_Msk      (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_DOVCBHM_Pos       (21UL)       /* DOVCBHM (Bit 21) */
+#define LINK_REG_DPUSR0R_DOVCBHM_Msk       (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_DOVCAHM_Pos       (20UL)       /* DOVCAHM (Bit 20) */
+#define LINK_REG_DPUSR0R_DOVCAHM_Msk       (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */
+
+// DPUSR1R
+#define LINK_REG_DPUSR1R_DVBSTSH_Pos       (23UL)       /* DVBSTSH (Bit 23) */
+#define LINK_REG_DPUSR1R_DVBSTSH_Msk       (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_DOVCBH_Pos        (21UL)       /* DOVCBH (Bit 21) */
+#define LINK_REG_DPUSR1R_DOVCBH_Msk        (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_DOVCAH_Pos        (20UL)       /* DOVCAH (Bit 20) */
+#define LINK_REG_DPUSR1R_DOVCAH_Msk        (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_DVBSTSHE_Pos      (7UL)        /* DVBSTSHE (Bit 7) */
+#define LINK_REG_DPUSR1R_DVBSTSHE_Msk      (0x80UL)     /* DVBSTSHE (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_DOVCBHE_Pos       (5UL)        /* DOVCBHE (Bit 5) */
+#define LINK_REG_DPUSR1R_DOVCBHE_Msk       (0x20UL)     /* DOVCBHE (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_DOVCAHE_Pos       (4UL)        /* DOVCAHE (Bit 4) */
+#define LINK_REG_DPUSR1R_DOVCAHE_Msk       (0x10UL)     /* DOVCAHE (Bitfield-Mask: 0x01) */
+
+// DPUSR2R
+#define LINK_REG_DPUSR2R_DMINTE_Pos        (9UL)        /* DMINTE (Bit 9) */
+#define LINK_REG_DPUSR2R_DMINTE_Msk        (0x200UL)    /* DMINTE (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR2R_DPINTE_Pos        (8UL)        /* DPINTE (Bit 8) */
+#define LINK_REG_DPUSR2R_DPINTE_Msk        (0x100UL)    /* DPINTE (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR2R_DMVAL_Pos         (5UL)        /* DMVAL (Bit 5) */
+#define LINK_REG_DPUSR2R_DMVAL_Msk         (0x20UL)     /* DMVAL (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR2R_DPVAL_Pos         (4UL)        /* DPVAL (Bit 4) */
+#define LINK_REG_DPUSR2R_DPVAL_Msk         (0x10UL)     /* DPVAL (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR2R_DMINT_Pos         (1UL)        /* DMINT (Bit 1) */
+#define LINK_REG_DPUSR2R_DMINT_Msk         (0x2UL)      /* DMINT (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR2R_DPINT_Pos         (0UL)        /* DPINT (Bit 0) */
+#define LINK_REG_DPUSR2R_DPINT_Msk         (0x1UL)      /* DPINT (Bitfield-Mask: 0x01) */
+
+// DPUSRCR
+#define LINK_REG_DPUSRCR_FIXPHYPD_Pos      (1UL)        /* FIXPHYPD (Bit 1) */
+#define LINK_REG_DPUSRCR_FIXPHYPD_Msk      (0x2UL)      /* FIXPHYPD (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSRCR_FIXPHY_Pos        (0UL)        /* FIXPHY (Bit 0) */
+#define LINK_REG_DPUSRCR_FIXPHY_Msk        (0x1UL)      /* FIXPHY (Bitfield-Mask: 0x01) */
+
+// DPUSR0R_FS
+#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos    (23UL)       /* DVBSTS0 (Bit 23) */
+#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk    (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos     (21UL)       /* DOVCB0 (Bit 21) */
+#define LINK_REG_DPUSR0R_FS_DOVCB0_Msk     (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_DOVCA0_Pos     (20UL)       /* DOVCA0 (Bit 20) */
+#define LINK_REG_DPUSR0R_FS_DOVCA0_Msk     (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_DM0_Pos        (17UL)       /* DM0 (Bit 17) */
+#define LINK_REG_DPUSR0R_FS_DM0_Msk        (0x20000UL)  /* DM0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_DP0_Pos        (16UL)       /* DP0 (Bit 16) */
+#define LINK_REG_DPUSR0R_FS_DP0_Msk        (0x10000UL)  /* DP0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_FIXPHY0_Pos    (4UL)        /* FIXPHY0 (Bit 4) */
+#define LINK_REG_DPUSR0R_FS_FIXPHY0_Msk    (0x10UL)     /* FIXPHY0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_DRPD0_Pos      (3UL)        /* DRPD0 (Bit 3) */
+#define LINK_REG_DPUSR0R_FS_DRPD0_Msk      (0x8UL)      /* DRPD0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_RPUE0_Pos      (1UL)        /* RPUE0 (Bit 1) */
+#define LINK_REG_DPUSR0R_FS_RPUE0_Msk      (0x2UL)      /* RPUE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR0R_FS_SRPC0_Pos      (0UL)        /* SRPC0 (Bit 0) */
+#define LINK_REG_DPUSR0R_FS_SRPC0_Msk      (0x1UL)      /* SRPC0 (Bitfield-Mask: 0x01) */
+
+// DPUSR1R_FS
+#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos    (23UL)       /* DVBINT0 (Bit 23) */
+#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk    (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos   (21UL)       /* DOVRCRB0 (Bit 21) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Msk   (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Pos   (20UL)       /* DOVRCRA0 (Bit 20) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Msk   (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DMINT0_Pos     (17UL)       /* DMINT0 (Bit 17) */
+#define LINK_REG_DPUSR1R_FS_DMINT0_Msk     (0x20000UL)  /* DMINT0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DPINT0_Pos     (16UL)       /* DPINT0 (Bit 16) */
+#define LINK_REG_DPUSR1R_FS_DPINT0_Msk     (0x10000UL)  /* DPINT0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DVBSE0_Pos     (7UL)        /* DVBSE0 (Bit 7) */
+#define LINK_REG_DPUSR1R_FS_DVBSE0_Msk     (0x80UL)     /* DVBSE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Pos  (5UL)        /* DOVRCRBE0 (Bit 5) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Msk  (0x20UL)     /* DOVRCRBE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Pos  (4UL)        /* DOVRCRAE0 (Bit 4) */
+#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Msk  (0x10UL)     /* DOVRCRAE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DMINTE0_Pos    (1UL)        /* DMINTE0 (Bit 1) */
+#define LINK_REG_DPUSR1R_FS_DMINTE0_Msk    (0x2UL)      /* DMINTE0 (Bitfield-Mask: 0x01) */
+#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos    (0UL)        /* DPINTE0 (Bit 0) */
+#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk    (0x1UL)      /* DPINTE0 (Bitfield-Mask: 0x01) */
 
 /*--------------------------------------------------------------------*/
 /* Register Bit Utils                                           */
 /*--------------------------------------------------------------------*/
-#define LINK_REG_PIPE_CTR_PID_NAK   (0U << LINK_REG_PIPE_CTR_PID_Pos) /* NAK response */
-#define LINK_REG_PIPE_CTR_PID_BUF   (1U << LINK_REG_PIPE_CTR_PID_Pos) /* BUF response (depends buffer state) */
-#define LINK_REG_PIPE_CTR_PID_STALL (2U << LINK_REG_PIPE_CTR_PID_Pos) /* STALL response */
+#define LINK_REG_PIPE_CTR_PID_NAK          (0U << LINK_REG_PIPE_CTR_PID_Pos)    /* NAK response */
+#define LINK_REG_PIPE_CTR_PID_BUF          (1U << LINK_REG_PIPE_CTR_PID_Pos)    /* BUF response (depends buffer state) */
+#define LINK_REG_PIPE_CTR_PID_STALL        (2U << LINK_REG_PIPE_CTR_PID_Pos)    /* STALL response */
 
-#define LINK_REG_DVSTCTR0_RHST_LS	(1U << LINK_REG_DVSTCTR0_RHST_Pos) /*  Low-speed connection */
-#define LINK_REG_DVSTCTR0_RHST_FS	(2U << LINK_REG_DVSTCTR0_RHST_Pos) /*  Full-speed connection */
+#define LINK_REG_DVSTCTR0_RHST_LS          (1U << LINK_REG_DVSTCTR0_RHST_Pos)   /*  Low-speed connection */
+#define LINK_REG_DVSTCTR0_RHST_FS          (2U << LINK_REG_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
 
-#define LINK_REG_DEVADD_USBSPD_LS (1U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Low-speed */
-#define LINK_REG_DEVADD_USBSPD_FS (2U << LINK_REG_DEVADD_USBSPD_Pos) /* Target Device Full-speed */
+#define LINK_REG_DEVADD_USBSPD_LS          (1U << LINK_REG_DEVADD_USBSPD_Pos)   /* Target Device Low-speed */
+#define LINK_REG_DEVADD_USBSPD_FS          (2U << LINK_REG_DEVADD_USBSPD_Pos)   /* Target Device Full-speed */
 
-#define LINK_REG_CFIFOSEL_ISEL_WRITE	(1U << LINK_REG_CFIFOSEL_ISEL_Pos)	/* FIFO write AKA TX*/
+#define LINK_REG_CFIFOSEL_ISEL_WRITE       (1U << LINK_REG_CFIFOSEL_ISEL_Pos)   /* FIFO write AKA TX*/
 
-#define LINK_REG_FIFOSEL_BIGEND			(1U << LINK_REG_CFIFOSEL_BIGEND_Pos)	/* FIFO Big Endian */
-#define LINK_REG_FIFOSEL_MBW_8BIT			(0U << LINK_REG_CFIFOSEL_MBW_Pos)	/* 8-bit width */
-#define LINK_REG_FIFOSEL_MBW_16BIT			(1U << LINK_REG_CFIFOSEL_MBW_Pos)	/* 16-bit width */
+#define LINK_REG_FIFOSEL_BIGEND            (1U << LINK_REG_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */
+#define LINK_REG_FIFOSEL_MBW_8BIT          (0U << LINK_REG_CFIFOSEL_MBW_Pos)    /* 8-bit width */
+#define LINK_REG_FIFOSEL_MBW_16BIT         (1U << LINK_REG_CFIFOSEL_MBW_Pos)    /* 16-bit width */
 
-#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA (1U << LINK_REG_INTSTS0_CTSQ_Pos)
+#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA   (1U << LINK_REG_INTSTS0_CTSQ_Pos)
 
-#define LINK_REG_INTSTS0_DVSQ_STATE_DEF (1U << LINK_REG_INTSTS0_DVSQ_Pos) /* Default state */
-#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR (2U << LINK_REG_INTSTS0_DVSQ_Pos) /* Address state */
-#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0 (4U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
-#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1 (5U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
-#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2 (6U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
-#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3 (7U << LINK_REG_INTSTS0_DVSQ_Pos) /* Suspend state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_DEF    (1U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Default state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR   (2U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Address state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0  (4U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1  (5U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2  (6U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3  (7U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Suspend state */
 
-#define LINK_REG_PIPECFG_TYPE_BULK (1U << LINK_REG_PIPECFG_TYPE_Pos)
-#define LINK_REG_PIPECFG_TYPE_INT (2U << LINK_REG_PIPECFG_TYPE_Pos)
-#define LINK_REG_PIPECFG_TYPE_ISO (3U << LINK_REG_PIPECFG_TYPE_Pos)
+#define LINK_REG_PIPECFG_TYPE_BULK         (1U << LINK_REG_PIPECFG_TYPE_Pos)
+#define LINK_REG_PIPECFG_TYPE_INT          (2U << LINK_REG_PIPECFG_TYPE_Pos)
+#define LINK_REG_PIPECFG_TYPE_ISO          (3U << LINK_REG_PIPECFG_TYPE_Pos)
+
+//--------------------------------------------------------------------+
+// Static Assert
+//--------------------------------------------------------------------+
+
+TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size");
+
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG     ) == 0x00000000, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT    ) == 0x00000002, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0    ) == 0x00000004, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA     ) == 0x00000006, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0   ) == 0x00000008, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE   ) == 0x0000000C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO      ) == 0x00000014, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO     ) == 0x00000018, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO     ) == 0x0000001C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL   ) == 0x00000020, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR   ) == 0x00000022, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL  ) == 0x00000028, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR  ) == 0x0000002A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL  ) == 0x0000002C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR  ) == 0x0000002E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0    ) == 0x00000030, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1    ) == 0x00000032, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB    ) == 0x00000036, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB    ) == 0x00000038, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB    ) == 0x0000003A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG     ) == 0x0000003C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET     ) == 0x0000003E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0    ) == 0x00000040, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1    ) == 0x00000042, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS    ) == 0x00000046, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS    ) == 0x00000048, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS    ) == 0x0000004A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM     ) == 0x0000004C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM    ) == 0x0000004E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR    ) == 0x00000050, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ     ) == 0x00000054, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL     ) == 0x00000056, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX    ) == 0x00000058, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG    ) == 0x0000005A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG     ) == 0x0000005C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP    ) == 0x0000005E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR     ) == 0x00000060, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL    ) == 0x00000064, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG    ) == 0x00000068, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP   ) == 0x0000006C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI   ) == 0x0000006E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR   ) == 0x00000070, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR    ) == 0x00000090, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL     ) == 0x000000C4, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC      ) == 0x000000CC, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD     ) == 0x000000D0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW    ) == 0x000000F0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL     ) == 0x00000100, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS      ) == 0x00000102, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL     ) == 0x00000140, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1   ) == 0x00000144, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2   ) == 0x00000146, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1   ) == 0x00000148, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2   ) == 0x0000014A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R    ) == 0x00000160, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R    ) == 0x00000164, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R    ) == 0x00000168, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR    ) == 0x0000016A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset");
 
 #ifdef __cplusplus
 }

From 0f8e530de175e8fb289870fdd7c28ec0b16314e2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Mar 2023 23:00:01 +0700
Subject: [PATCH 1520/2085] fix incorrect merge of hcd link

---
 src/portable/renesas/link/hcd_link.c | 476 +++++++++++----------------
 1 file changed, 190 insertions(+), 286 deletions(-)

diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c
index a10fe54ea..f1ea2b821 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/link/hcd_link.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji Kitayama
@@ -27,86 +27,37 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
-                               CFG_TUSB_MCU == OPT_MCU_RX65X || \
-                               CFG_TUSB_MCU == OPT_MCU_RX72N )
+#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
+                        CFG_TUSB_MCU == OPT_MCU_RX65X || \
+                        CFG_TUSB_MCU == OPT_MCU_RX72N || \
+                        CFG_TUSB_MCU == OPT_MCU_RAXXX)
+
 #include "host/hcd.h"
-#include "iodefine.h"
+#include "link_type.h"
+
+#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+#include "link_rx.h"
+#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
+#include "link_ra.h"
+#else
+#error "Unsupported MCU"
+#endif
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
-#define SYSTEM_PRCR_PRC1     (1<<1)
-#define SYSTEM_PRCR_PRKEY    (0xA5u<<8)
 
-#define USB_DVSTCTR0_LOW     (1u)
-#define USB_DVSTCTR0_FULL    (2u)
+/* LINK core registers */
+#if defined(__CCRX__)
+#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE)
+#else
+#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE)
+#endif
 
-#define USB_FIFOSEL_TX       ((uint16_t)(1u<<5))
-#define USB_FIFOSEL_BIGEND   ((uint16_t)(1u<<8))
-#define USB_FIFOSEL_MBW_8    ((uint16_t)(0u<<10))
-#define USB_FIFOSEL_MBW_16   ((uint16_t)(1u<<10))
-#define USB_IS0_CTSQ         ((uint16_t)(7u))
-#define USB_IS0_DVSQ         ((uint16_t)(7u<<4))
-#define USB_IS0_VALID        ((uint16_t)(1u<<3))
-#define USB_IS0_BRDY         ((uint16_t)(1u<<8))
-#define USB_IS0_NRDY         ((uint16_t)(1u<<9))
-#define USB_IS0_BEMP         ((uint16_t)(1u<<10))
-#define USB_IS0_CTRT         ((uint16_t)(1u<<11))
-#define USB_IS0_DVST         ((uint16_t)(1u<<12))
-#define USB_IS0_SOFR         ((uint16_t)(1u<<13))
-#define USB_IS0_RESM         ((uint16_t)(1u<<14))
-#define USB_IS0_VBINT        ((uint16_t)(1u<<15))
-#define USB_IS1_SACK         ((uint16_t)(1u<<4))
-#define USB_IS1_SIGN         ((uint16_t)(1u<<5))
-#define USB_IS1_EOFERR       ((uint16_t)(1u<<6))
-#define USB_IS1_ATTCH        ((uint16_t)(1u<<11))
-#define USB_IS1_DTCH         ((uint16_t)(1u<<12))
-#define USB_IS1_BCHG         ((uint16_t)(1u<<14))
-#define USB_IS1_OVRCR        ((uint16_t)(1u<<15))
-
-#define USB_IS0_CTSQ_MSK     (7u)
-#define USB_IS0_CTSQ_SETUP   (1u)
-#define USB_IS0_DVSQ_DEF     (1u<<4)
-#define USB_IS0_DVSQ_ADDR    (2u<<4)
-#define USB_IS0_DVSQ_SUSP0   (4u<<4)
-#define USB_IS0_DVSQ_SUSP1   (5u<<4)
-#define USB_IS0_DVSQ_SUSP2   (6u<<4)
-#define USB_IS0_DVSQ_SUSP3   (7u<<4)
-
-#define USB_PIPECTR_PID_MSK   (3u)
-#define USB_PIPECTR_PID_NAK   (0u)
-#define USB_PIPECTR_PID_BUF   (1u)
-#define USB_PIPECTR_PID_STALL (2u)
-#define USB_PIPECTR_CCPL      (1u<<2)
-#define USB_PIPECTR_SQMON     (1u<<6)
-#define USB_PIPECTR_SQCLR     (1u<<8)
-#define USB_PIPECTR_ACLRM     (1u<<9)
-#define USB_PIPECTR_INBUFM    (1u<<14)
-#define USB_PIPECTR_BSTS      (1u<<15)
-
-#define USB_FIFOCTR_DTLN     (0x1FF)
-#define USB_FIFOCTR_FRDY     (1u<<13)
-#define USB_FIFOCTR_BCLR     (1u<<14)
-#define USB_FIFOCTR_BVAL     (1u<<15)
-
-#define USB_PIPECFG_SHTNAK   (1u<<7)
-#define USB_PIPECFG_DBLB     (1u<<9)
-#define USB_PIPECFG_BULK     (1u<<14)
-#define USB_PIPECFG_ISO      (3u<<14)
-#define USB_PIPECFG_INT      (2u<<14)
-
-#define USB_DEVADD_LOW       (1u<<6)
-#define USB_DEVADD_FULL      (2u<<6)
-
-#define FIFO_REQ_CLR         (1u)
-#define FIFO_COMPLETE        (1u<<1)
-
-// Start of definition of packed structs (used by the CCRX toolchain)
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
-typedef struct {
+typedef struct TU_ATTR_PACKED {
   union {
     struct {
       uint16_t      : 8;
@@ -119,7 +70,7 @@ typedef struct {
   uint16_t TRN;
 } reg_pipetre_t;
 
-typedef union {
+typedef union TU_ATTR_PACKED {
   struct {
     volatile uint16_t u8: 8;
     volatile uint16_t   : 0;
@@ -127,8 +78,7 @@ typedef union {
   volatile uint16_t u16;
 } hw_fifo_t;
 
-typedef struct TU_ATTR_PACKED
-{
+typedef struct TU_ATTR_PACKED {
   void      *buf;      /* the start address of a transfer data buffer */
   uint16_t  length;    /* the number of bytes in the buffer */
   uint16_t  remaining; /* the number of bytes remaining in the buffer */
@@ -156,28 +106,6 @@ typedef struct
 //--------------------------------------------------------------------+
 static hcd_data_t _hcd;
 
-static uint32_t disable_interrupt(void)
-{
-  uint32_t pswi;
-#if defined(__CCRX__)
-  pswi = get_psw() & 0x010000;
-  clrpsw_i();
-#else
-  pswi = __builtin_rx_mvfc(0) & 0x010000;
-  __builtin_rx_clrpsw('I');
-#endif
-  return pswi;
-}
-
-static void enable_interrupt(uint32_t pswi)
-{
-#if defined(__CCRX__)
-  set_psw(get_psw() | pswi);
-#else
-  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
-#endif
-}
-
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
@@ -208,58 +136,49 @@ static unsigned find_pipe(unsigned xfer)
 
 static volatile uint16_t* get_pipectr(unsigned num)
 {
-  volatile uint16_t *ctr = NULL;
   if (num) {
-    ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
-    ctr += num - 1;
+    return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]);
   } else {
-    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
+    return (volatile uint16_t*)&(LINK_REG->DCPCTR);
   }
-  return ctr;
 }
 
 static volatile reg_pipetre_t* get_pipetre(unsigned num)
 {
   volatile reg_pipetre_t* tre = NULL;
   if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD;
-    tre += num - 1;
+    tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E);
   }
   return tre;
 }
 
 static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr)
 {
-  volatile uint16_t *ctr = NULL;
-  const unsigned epn   = tu_edpt_number(ep_addr);
+  const unsigned epn = tu_edpt_number(ep_addr);
   if (epn) {
     const unsigned dir_in = tu_edpt_dir(ep_addr);
-    const unsigned num    = _hcd.ep[dev_addr][dir_in][epn - 1];
-    if (num) {
-      ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
-      ctr += num - 1;
-    }
+    const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1];
+    return get_pipectr(num);
   } else {
-    ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
+    return get_pipectr(0);
   }
-  return ctr;
 }
 
 static unsigned edpt0_max_packet_size(void)
 {
-  return USB0.DCPMAXP.BIT.MXPS;
+  return LINK_REG->DCPMAXP_b.MXPS;
 }
 
 static unsigned edpt_max_packet_size(unsigned num)
 {
-  USB0.PIPESEL.WORD = num;
-  return USB0.PIPEMAXP.BIT.MXPS;
+  LINK_REG->PIPESEL = num;
+  return LINK_REG->PIPEMAXP_b.MXPS;
 }
 
 static inline void pipe_wait_for_ready(unsigned num)
 {
-  while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
-  while (!USB0.D0FIFOCTR.BIT.FRDY) ;
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ;
+  while (!LINK_REG->D0FIFOCTR_b.FRDY) ;
 }
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -290,21 +209,22 @@ static bool pipe0_xfer_in(void)
   const unsigned rem = pipe->remaining;
 
   const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = USB0.CFIFOCTR.BIT.DTLN;
+  const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN;
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
-    USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
-    pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
+    LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
+    pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
+  if (len < mps)
+    LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return true;
   }
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
+  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
   return false;
 }
 
@@ -320,10 +240,11 @@ static bool pipe0_xfer_out(void)
   const unsigned len = TU_MIN(mps, rem);
   void          *buf = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
+    pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+  if (len < mps)
+    LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
   pipe->remaining = rem - len;
   return false;
 }
@@ -333,20 +254,21 @@ static bool pipe_xfer_in(unsigned num)
   pipe_state_t  *pipe = &_hcd.pipe[num];
   const unsigned rem  = pipe->remaining;
 
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
+  LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT;
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
-  const unsigned vld  = USB0.D0FIFOCTR.BIT.DTLN;
+  const unsigned vld  = LINK_REG->D0FIFOCTR_b.DTLN;
   const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
+    pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  pipe->remaining     = rem - len;
+  if (len < mps)
+    LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
+  LINK_REG->D0FIFOSEL = 0;
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return NULL != buf;
@@ -364,18 +286,19 @@ static bool pipe_xfer_out(unsigned num)
     return true;
   }
 
-  USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
+  LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
   const unsigned len  = TU_MIN(rem, mps);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
+    pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-  USB0.D0FIFOSEL.WORD = 0;
-  while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  if (len < mps)
+    LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
+  LINK_REG->D0FIFOSEL = 0;
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   return false;
 }
@@ -387,11 +310,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
 
   /* configure fifo direction and access unit settings */
   if (dir_in) { /* IN, a byte */
-    USB0.CFIFOSEL.WORD  = USB_FIFOSEL_MBW_8;
-    while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
-  } else {       /* OUT, 2 bytes */
-    USB0.CFIFOSEL.WORD  = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
-    while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
+    LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
+    while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
+  } else { /* OUT, 2 bytes */
+    LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
+             (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
+    while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
   }
 
   pipe_state_t *pipe = &_hcd.pipe[0];
@@ -401,25 +325,25 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
   if (buflen) {
     pipe->buf     = buffer;
     if (!dir_in) { /* OUT */
-      TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
+      TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80));
       pipe0_xfer_out();
     }
   } else { /* ZLP */
     pipe->buf        = NULL;
     if (!dir_in) { /* OUT */
-      USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
+      LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
     }
-    if (dir_in == USB0.DCPCFG.BIT.DIR) {
-      TU_ASSERT(USB_PIPECTR_PID_NAK == USB0.DCPCTR.BIT.PID);
-      USB0.DCPCTR.BIT.SQSET = 1;
-      USB0.DCPCFG.BIT.DIR = dir_in ^ 1;
+    if (dir_in == LINK_REG->DCPCFG_b.DIR) {
+      TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID);
+      LINK_REG->DCPCTR_b.SQSET = 1;
+      LINK_REG->DCPCFG_b.DIR = dir_in ^ 1;
     }
   }
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
+  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
   return true;
 }
 
-static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen)
 {
   const unsigned epn    = tu_edpt_number(ep_addr);
   const unsigned dir_in = tu_edpt_dir(ep_addr);
@@ -435,23 +359,23 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, u
     if (buflen) {
       pipe_xfer_out(num);
     } else { /* ZLP */
-      USB0.D0FIFOSEL.WORD = num;
+      LINK_REG->D0FIFOSEL = num;
       pipe_wait_for_ready(num);
-      USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
-      USB0.D0FIFOSEL.WORD = 0;
-      while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+      LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
+      LINK_REG->D0FIFOSEL = 0;
+      while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
     }
   } else {
     volatile uint16_t     *ctr = get_pipectr(num);
     volatile reg_pipetre_t *pt = get_pipetre(num);
     if (pt) {
       const unsigned     mps = edpt_max_packet_size(num);
-      if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
+      if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK;
       pt->TRE   = TU_BIT(8);
       pt->TRN   = (buflen + mps - 1) / mps;
       pt->TRENB = 1;
     }
-    *ctr = USB_PIPECTR_PID_BUF;
+    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
   }
   return true;
 }
@@ -485,10 +409,10 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
   unsigned result;
   uint16_t volatile *ctr = get_pipectr(num);
   // TU_LOG1("NRDY %d %x\n", num, *ctr);
-  switch (*ctr & USB_PIPECTR_PID_MSK) {
+  switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) {
     default: return;
-    case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break;
-    case USB_PIPECTR_PID_NAK:   result = XFER_RESULT_FAILED;  break;
+    case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
+    case LINK_REG_PIPE_CTR_PID_NAK:   result = XFER_RESULT_FAILED;  break;
   }
   pipe_state_t *pipe = &_hcd.pipe[num];
   hcd_event_xfer_complete(pipe->dev, pipe->ep,
@@ -520,78 +444,60 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
   }
 }
 
-
 /*------------------------------------------------------------------*/
 /* Host API
  *------------------------------------------------------------------*/
 bool hcd_init(uint8_t rhport)
 {
   (void)rhport;
-  /* Enable USB0 */
-  uint32_t pswi = disable_interrupt();
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(USB0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  enable_interrupt(pswi);
-  USB0.SYSCFG.BIT.SCKE = 1;
-  while (!USB0.SYSCFG.BIT.SCKE) ;
-  USB0.SYSCFG.BIT.DPRPU = 0;
-  USB0.SYSCFG.BIT.DRPD = 0;
-  USB0.SYSCFG.BIT.DCFM = 1;
 
-  USB0.DVSTCTR0.BIT.VBUSEN = 1;
+  LINK_REG->SYSCFG_b.SCKE = 1;
+  while (!LINK_REG->SYSCFG_b.SCKE) ;
+  LINK_REG->SYSCFG_b.DPRPU = 0;
+  LINK_REG->SYSCFG_b.DRPD = 0;
+  LINK_REG->SYSCFG_b.DCFM = 1;
 
-  USB0.SYSCFG.BIT.DRPD = 1;
+  LINK_REG->DVSTCTR0_b.VBUSEN = 1;
+
+  LINK_REG->SYSCFG_b.DRPD = 1;
   for (volatile int i = 0; i < 30000; ++i) ;
-  USB0.SYSCFG.BIT.USBE = 1;
+  LINK_REG->SYSCFG_b.USBE = 1;
 
-  USB.DPUSR0R.BIT.FIXPHY0 = 0u;    /* USB0 Transceiver Output fixed */
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  USB0.PHYSLEW.LONG = 0x5;
-  IR(PERIB, INTB185) = 0;
-#else
-  IR(USB0, USBI0)   = 0;
-#endif
+  // MCU specific PHY init
+  link_phy_init();
+
+  LINK_REG->PHYSLEW = 0x5;
+  LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
 
   /* Setup default control pipe */
-  USB0.DCPCFG.WORD  = USB_PIPECFG_SHTNAK;
-  USB0.DCPMAXP.WORD = 64;
-  USB0.INTENB0.WORD = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP;
-  USB0.INTENB1.WORD = USB_IS1_SACK | USB_IS1_SIGN |
-    USB_IS1_ATTCH | USB_IS1_DTCH;
-  USB0.BEMPENB.WORD = 1;
-  USB0.NRDYENB.WORD = 1;
-  USB0.BRDYENB.WORD = 1;
+  LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk;
+  LINK_REG->DCPMAXP = 64;
+  LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk;
+  LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk;
+  LINK_REG->BEMPENB = 1;
+  LINK_REG->NRDYENB = 1;
+  LINK_REG->BRDYENB = 1;
+
   return true;
 }
 
 void hcd_int_enable(uint8_t rhport)
 {
-  (void)rhport;
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  IEN(PERIB, INTB185) = 1;
-#else
-  IEN(USB0, USBI0) = 1;
-#endif
+  link_int_enable(rhport);
 }
 
 void hcd_int_disable(uint8_t rhport)
 {
-  (void)rhport;
-#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
-  IEN(PERIB, INTB185) = 0;
-#else
-  IEN(USB0, USBI0) = 0;
-#endif
+  link_int_disable(rhport);
 }
 
 uint32_t hcd_frame_number(uint8_t rhport)
 {
   (void)rhport;
-  /* The device must be reset at least once after connection 
+  /* The device must be reset at least once after connection
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
-  return USB0.FRMNUM.BIT.FRNM;
+  return LINK_REG->FRMNUM_b.FRNM;
 }
 
 /*--------------------------------------------------------------------+
@@ -605,18 +511,18 @@ bool hcd_port_connect_status(uint8_t rhport)
 
 void hcd_port_reset(uint8_t rhport)
 {
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
-  while (USB0.DCPCTR.BIT.PBUSY) ;
+  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
+  while (LINK_REG->DCPCTR_b.PBUSY) ;
   hcd_int_disable(rhport);
-  USB0.DVSTCTR0.BIT.UACT   = 0;
-  if (USB0.DCPCTR.BIT.SUREQ)
-    USB0.DCPCTR.BIT.SUREQCLR = 1;
+  LINK_REG->DVSTCTR0_b.UACT = 0;
+  if (LINK_REG->DCPCTR_b.SUREQ)
+    LINK_REG->DCPCTR_b.SUREQCLR = 1;
   hcd_int_enable(rhport);
   /* Reset should be asserted 10-20ms. */
-  USB0.DVSTCTR0.BIT.USBRST = 1;
+  LINK_REG->DVSTCTR0_b.USBRST = 1;
   for (volatile int i = 0; i < 2400000; ++i) ;
-  USB0.DVSTCTR0.BIT.USBRST = 0;
-  USB0.DVSTCTR0.BIT.UACT   = 1;
+  LINK_REG->DVSTCTR0_b.USBRST = 0;
+  LINK_REG->DVSTCTR0_b.UACT = 1;
   _hcd.need_reset = false;
 }
 
@@ -628,10 +534,10 @@ void hcd_port_reset_end(uint8_t rhport)
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   (void)rhport;
-  switch (USB0.DVSTCTR0.BIT.RHST) {
+  switch (LINK_REG->DVSTCTR0_b.RHST) {
     default: return TUSB_SPEED_INVALID;
-    case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL;
-    case USB_DVSTCTR0_LOW:  return TUSB_SPEED_LOW;
+    case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL;
+    case LINK_REG_DVSTCTR0_RHST_LS:  return TUSB_SPEED_LOW;
   }
 }
 
@@ -647,13 +553,13 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
     unsigned num = *ep;
     if (!num || dev_addr != _hcd.pipe[num].dev) continue;
 
-    ctr  = (uint16_t volatile*)&USB0.PIPE1CTR.WORD + num - 1;
+    ctr = (uint16_t volatile*)&LINK_REG->PIPE_CTR[num - 1];
     *ctr = 0;
-    USB0.NRDYENB.WORD &= ~TU_BIT(num);
-    USB0.BRDYENB.WORD &= ~TU_BIT(num);
-    USB0.PIPESEL.WORD  = num;
-    USB0.PIPECFG.WORD  = 0;
-    USB0.PIPEMAXP.WORD = 0;
+    LINK_REG->NRDYENB &= ~TU_BIT(num);
+    LINK_REG->BRDYENB &= ~TU_BIT(num);
+    LINK_REG->PIPESEL = num;
+    LINK_REG->PIPECFG = 0;
+    LINK_REG->PIPEMAXP = 0;
 
     _hcd.pipe[num].ep  = 0;
     _hcd.pipe[num].dev = 0;
@@ -667,36 +573,36 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void)rhport;
-  //  TU_LOG1("S %d %x\n", dev_addr, USB0.DCPCTR.WORD);
+  //  TU_LOG1("S %d %x\n", dev_addr, LINK_REG->DCPCTR);
 
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
-  TU_ASSERT(0 == USB0.DCPCTR.BIT.SUREQ);
+  TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ);
 
-  USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
+  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
 
-  _hcd.pipe[0].buf       = NULL;
-  _hcd.pipe[0].length    = 8;
+  _hcd.pipe[0].buf = NULL;
+  _hcd.pipe[0].length = 8;
   _hcd.pipe[0].remaining = 0;
-  _hcd.pipe[0].dev       = dev_addr;
+  _hcd.pipe[0].dev = dev_addr;
 
-  while (USB0.DCPCTR.BIT.PBUSY) ;
-  USB0.DCPMAXP.WORD      = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
+  while (LINK_REG->DCPCTR_b.PBUSY) ;
+  LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
 
   /* Set direction in advance for DATA stage */
   uint8_t const bmRequesttype = setup_packet[0];
-  USB0.DCPCFG.BIT.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
+  LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
 
   uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
-  USB0.USBREQ.WORD = tu_htole16(p[0]);
-  USB0.USBVAL      = p[1];
-  USB0.USBINDX     = p[2];
-  USB0.USBLENG     = p[3];
+  LINK_REG->USBREQ = tu_htole16(p[0]);
+  LINK_REG->USBVAL = p[1];
+  LINK_REG->USBINDX = p[2];
+  LINK_REG->USBLENG = p[3];
 
-  USB0.DCPCTR.BIT.SUREQ = 1;
+  LINK_REG->DCPCTR_b.SUREQ = 1;
   return true;
 }
 
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc)
 {
   (void)rhport;
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
@@ -705,14 +611,14 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   const unsigned epn     = tu_edpt_number(ep_addr);
   const unsigned mps     = tu_edpt_packet_size(ep_desc);
   if (0 == epn) {
-    USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
+    LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
     hcd_devtree_info_t devtree;
     hcd_devtree_get_info(dev_addr, &devtree);
-    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t)&USB0.DEVADD0.WORD;
+    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0];
     devadd += dev_addr;
-    while (USB0.DCPCTR.BIT.PBUSY) ;
-    USB0.DCPMAXP.WORD = (dev_addr << 12) | mps;
-    *devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW;
+    while (LINK_REG->DCPCTR_b.PBUSY) ;
+    LINK_REG->DCPMAXP = (dev_addr << 12) | mps;
+    *devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS;
     _hcd.ctl_mps[dev_addr] = mps;
     return true;
   }
@@ -731,25 +637,25 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 
   /* setup pipe */
   hcd_int_disable(rhport);
-  USB0.PIPESEL.WORD  = num;
-  USB0.PIPEMAXP.WORD = (dev_addr << 12) | mps;
+  LINK_REG->PIPESEL = num;
+  LINK_REG->PIPEMAXP = (dev_addr << 12) | mps;
   volatile uint16_t *ctr = get_pipectr(num);
-  *ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
+  *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk;
   *ctr = 0;
   unsigned cfg = ((1 ^ dir_in) << 4) | epn;
   if (xfer == TUSB_XFER_BULK) {
-    cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB;
+    cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk;
   } else if (xfer == TUSB_XFER_INTERRUPT) {
-    cfg |= USB_PIPECFG_INT;
+    cfg |= LINK_REG_PIPECFG_TYPE_INT;
   } else {
-    cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
+    cfg |= LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk;
   }
-  USB0.PIPECFG.WORD  = cfg;
-  USB0.BRDYSTS.WORD  = 0x1FFu ^ TU_BIT(num);
-  USB0.NRDYENB.WORD |= TU_BIT(num);
-  USB0.BRDYENB.WORD |= TU_BIT(num);
+  LINK_REG->PIPECFG = cfg;
+  LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  LINK_REG->NRDYENB |= TU_BIT(num);
+  LINK_REG->BRDYENB |= TU_BIT(num);
   if (!dir_in) {
-    *ctr = USB_PIPECTR_PID_BUF;
+    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
   }
   hcd_int_enable(rhport);
 
@@ -776,12 +682,12 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
     *ctr = pid & 2;
     *ctr = 0;
   }
-  *ctr = USB_PIPECTR_SQCLR;
+  *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk;
   unsigned const epn = tu_edpt_number(ep_addr);
   if (!epn) return true;
 
   if (!tu_edpt_dir(ep_addr)) { /* OUT */
-    *ctr = USB_PIPECTR_PID_BUF;
+    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
   }
   return true;
 }
@@ -799,52 +705,50 @@ void hcd_int_handler(uint8_t rhport)
     20, 8, 19, 18};
 #endif
 
-  unsigned is1 = USB0.INTSTS1.WORD;
-  unsigned is0 = USB0.INTSTS0.WORD;
+  unsigned is1 = LINK_REG->INTSTS1;
+  unsigned is0 = LINK_REG->INTSTS0;
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  USB0.INTSTS1.WORD = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1);
-  USB0.INTSTS0.WORD = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0);
+  LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1);
+  LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0);
   // TU_LOG1("IS %04x %04x\n", is0, is1);
-  is1 &= USB0.INTENB1.WORD;
-  is0 &= USB0.INTENB0.WORD;
+  is1 &= LINK_REG->INTENB1;
+  is0 &= LINK_REG->INTENB0;
 
-  if (is1 & USB_IS1_SACK) {
+  if (is1 & LINK_REG_INTSTS1_SACK_Msk) {
     /* Set DATA1 in advance for the next transfer. */
-    USB0.DCPCTR.BIT.SQSET = 1;
-    hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
-                            tu_edpt_addr(0, TUSB_DIR_OUT),
-                            8, XFER_RESULT_SUCCESS, true);
+    LINK_REG->DCPCTR_b.SQSET = 1;
+    hcd_event_xfer_complete(
+      LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
   }
-  if (is1 & USB_IS1_SIGN) {
-    hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
-                            tu_edpt_addr(0, TUSB_DIR_OUT),
-                            8, XFER_RESULT_FAILED, true);
+  if (is1 & LINK_REG_INTSTS1_SIGN_Msk) {
+    hcd_event_xfer_complete(
+      LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
   }
-  if (is1 & USB_IS1_ATTCH) {
-    USB0.DVSTCTR0.BIT.UACT = 1;
+  if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) {
+    LINK_REG->DVSTCTR0_b.UACT = 1;
     _hcd.need_reset = true;
-    USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_ATTCH) | USB_IS1_DTCH;
+    LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk;
     hcd_event_device_attach(rhport, true);
   }
-  if (is1 & USB_IS1_DTCH) {
-    USB0.DVSTCTR0.BIT.UACT = 0;
-    if (USB0.DCPCTR.BIT.SUREQ)
-      USB0.DCPCTR.BIT.SUREQCLR = 1;
-    USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_DTCH) | USB_IS1_ATTCH;
+  if (is1 & LINK_REG_INTSTS1_DTCH_Msk) {
+    LINK_REG->DVSTCTR0_b.UACT = 0;
+    if (LINK_REG->DCPCTR_b.SUREQ)
+      LINK_REG->DCPCTR_b.SUREQCLR = 1;
+    LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk;
     hcd_event_device_remove(rhport, true);
   }
 
-  if (is0 & USB_IS0_BEMP) {
-    const unsigned s = USB0.BEMPSTS.WORD;
-    USB0.BEMPSTS.WORD = 0;
+  if (is0 & LINK_REG_INTSTS0_BEMP_Msk) {
+    const unsigned s = LINK_REG->BEMPSTS;
+    LINK_REG->BEMPSTS = 0;
     if (s & 1) {
       process_pipe0_bemp(rhport);
     }
   }
-  if (is0 & USB_IS0_NRDY) {
-    const unsigned m = USB0.NRDYENB.WORD;
-    unsigned s       = USB0.NRDYSTS.WORD & m;
-    USB0.NRDYSTS.WORD = ~s;
+  if (is0 & LINK_REG_INTSTS0_NRDY_Msk) {
+    const unsigned m = LINK_REG->NRDYENB;
+    unsigned s = LINK_REG->NRDYSTS & m;
+    LINK_REG->NRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       const unsigned num = Mod37BitPosition[(-s & s) % 37];
@@ -855,11 +759,11 @@ void hcd_int_handler(uint8_t rhport)
       s &= ~TU_BIT(num);
     }
   }
-  if (is0 & USB_IS0_BRDY) {
-    const unsigned m = USB0.BRDYENB.WORD;
-    unsigned s       = USB0.BRDYSTS.WORD & m;
+  if (is0 & LINK_REG_INTSTS0_BRDY_Msk) {
+    const unsigned m = LINK_REG->BRDYENB;
+    unsigned s = LINK_REG->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    USB0.BRDYSTS.WORD = ~s;
+    LINK_REG->BRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       const unsigned num = Mod37BitPosition[(-s & s) % 37];

From f0ddf8d10f7d58592d2ebb60025b227c8047114d Mon Sep 17 00:00:00 2001
From: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Date: Thu, 9 Mar 2023 14:00:37 +0100
Subject: [PATCH 1521/2085] dcd_nrf5x: ISO OUT handling

For incoming ISO OUT packets it was possible to start
DMA from endpoint to RAM before transfer was started
resulting in unrelated memory corruption.
This is scenario that causes memory corruption:
- ISO OUT packet is received
- Packet is transferred by DMA to transfer buffer
- xfer->started is cleared and xfer->buffer is updated as
  it is in every case
- Application takes to long to handle it (it happens when debugger
  is connected breakpoint is hit slowing down software).
- Next ISO OUT packet arrives
At this point there was no check if transfer was started and packet
was copied by DMA to location beyond previous data, possibly overwriting
unrelated memory.

This solves the issue by checking that transfer was
started and there is buffer ready for incoming packet.
---
 src/portable/nordic/nrf5x/dcd_nrf5x.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index afc14b010..4aeb85fc0 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -187,11 +187,16 @@ static void xact_out_dma(uint8_t epnum)
     }
     else
     {
-      // Trigger DMA move data from Endpoint -> SRAM
-      NRF_USBD->ISOOUT.PTR = (uint32_t) xfer->buffer;
-      NRF_USBD->ISOOUT.MAXCNT = xact_len;
+      if (xfer->started)
+      {
+        // Trigger DMA move data from Endpoint -> SRAM
+        NRF_USBD->ISOOUT.PTR = (uint32_t) xfer->buffer;
+        NRF_USBD->ISOOUT.MAXCNT = xact_len;
 
-      start_dma(&NRF_USBD->TASKS_STARTISOOUT);
+        start_dma(&NRF_USBD->TASKS_STARTISOOUT);
+      } else {
+        atomic_flag_clear(&_dcd.dma_running);
+      }
     }
   }
   else

From 76f43a7a16ae814abfc7e4eec84088a4a8e70bb4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Mar 2023 19:23:23 +0700
Subject: [PATCH 1522/2085] starting to remove submodule cmsis5 and nrfx

---
 .gitmodules                                | 6 ------
 hw/mcu/nordic/nrfx                         | 1 -
 lib/CMSIS_5                                | 1 -
 tools/{get_dependencies.py => get_deps.py} | 0
 4 files changed, 8 deletions(-)
 delete mode 160000 hw/mcu/nordic/nrfx
 delete mode 160000 lib/CMSIS_5
 rename tools/{get_dependencies.py => get_deps.py} (100%)

diff --git a/.gitmodules b/.gitmodules
index 14f47746b..c3baaa1be 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,6 +1,3 @@
-[submodule "hw/mcu/nordic/nrfx"]
-	path = hw/mcu/nordic/nrfx
-	url = https://github.com/NordicSemiconductor/nrfx.git
 [submodule "tools/uf2"]
 	path = tools/uf2
 	url = https://github.com/microsoft/uf2.git
@@ -109,9 +106,6 @@
 [submodule "lib/FreeRTOS-Kernel"]
 	path = lib/FreeRTOS-Kernel
 	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
-[submodule "lib/CMSIS_5"]
-	path = lib/CMSIS_5
-	url = https://github.com/ARM-software/CMSIS_5.git
 [submodule "hw/mcu/silabs/cmsis-dfp-efm32gg12b"]
 	path = hw/mcu/silabs/cmsis-dfp-efm32gg12b
 	url = https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b
diff --git a/hw/mcu/nordic/nrfx b/hw/mcu/nordic/nrfx
deleted file mode 160000
index 281cc2e17..000000000
--- a/hw/mcu/nordic/nrfx
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 281cc2e178fd9a470d844b3afdea9eb322a0b0e8
diff --git a/lib/CMSIS_5 b/lib/CMSIS_5
deleted file mode 160000
index 202852626..000000000
--- a/lib/CMSIS_5
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 20285262657d1b482d132d20d755c8c330d55c1f
diff --git a/tools/get_dependencies.py b/tools/get_deps.py
similarity index 100%
rename from tools/get_dependencies.py
rename to tools/get_deps.py

From d41320a42eae7fd26075f7c91972254c7f03ede6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Mar 2023 20:49:11 +0700
Subject: [PATCH 1523/2085] adding python script to manage dependencies instead
 of submodule

---
 .github/workflows/build_aarch64.yml |   2 +-
 .github/workflows/build_arm.yml     |   2 +-
 .github/workflows/build_iar.yml     |   2 +-
 .github/workflows/build_msp430.yml  |   2 +-
 .github/workflows/build_renesas.yml |   2 +-
 .github/workflows/build_riscv.yml   |   2 +-
 .github/workflows/build_win_mac.yml |   2 +-
 examples/rules.mk                   |   2 +-
 tools/get_deps.py                   | 104 +++++++++++++++++++++++-----
 tools/get_family_deps.py            |  19 +++++
 10 files changed, 115 insertions(+), 24 deletions(-)
 create mode 100644 tools/get_family_deps.py

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 800a54380..5818ea432 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -72,7 +72,7 @@ jobs:
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
     - name: Get Dependencies
-      run: python3 tools/get_dependencies.py ${{ matrix.family }}
+      run: python3 tools/get_family_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index b1b88ec70..2ed40e186 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -80,7 +80,7 @@ jobs:
         echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
 
     - name: Get Dependencies
-      run: python3 tools/get_dependencies.py ${{ matrix.family }}
+      run: python3 tools/get_family_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 33e77c3dc..7f2a92010 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -45,7 +45,7 @@ jobs:
     - name: Checkout submodules and dependencies
       run: |
         git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
-        python3 tools/get_dependencies.py ${{ matrix.family }}
+        python3 tools/get_family_deps.py ${{ matrix.family }}
 
     #- name: Checkout pico-sdk for rp2040
     #  if: matrix.family == 'rp2040'
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 2c7785806..6832c54b3 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -70,7 +70,7 @@ jobs:
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
     - name: Get Dependencies
-      run: python3 tools/get_dependencies.py ${{ matrix.family }}
+      run: python3 tools/get_family_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 3a961d327..7ce674485 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -70,7 +70,7 @@ jobs:
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
     - name: Get Dependencies
-      run: python3 tools/get_dependencies.py ${{ matrix.family }}
+      run: python3 tools/get_family_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index fb4d4d28c..876ebbdef 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -71,7 +71,7 @@ jobs:
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
     - name: Get Dependencies
-      run: python3 tools/get_dependencies.py ${{ matrix.family }}
+      run: python3 tools/get_family_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index bad9f3162..7c884abd9 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -50,7 +50,7 @@ jobs:
       run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
     - name: Get Dependencies
-      run: python3 tools/get_dependencies.py stm32f4
+      run: python3 tools/get_family_deps.py stm32f4
 
     - name: Build
       run: python3 tools/build_family.py stm32f4 stm32f411disco
diff --git a/examples/rules.mk b/examples/rules.mk
index 7f3535bba..f8e4001ec 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -193,7 +193,7 @@ endif
 .PHONY: get-deps
 get-deps:
   ifdef DEPS_SUBMODULES
-	git -C $(TOP) submodule update --init $(DEPS_SUBMODULES)
+	$(PYTHON) $(TOP)/tools/get_deps.py $(DEPS_SUBMODULES)
   endif
 
 .PHONY: size
diff --git a/tools/get_deps.py b/tools/get_deps.py
index e7d3e0a76..7ce02cc33 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -1,25 +1,97 @@
-import os
 import sys
 import subprocess
+from pathlib import Path
+
+# path, url, commit
+deps_list = {
+    'hw/mcu/allwinner'                            : [ 'https://github.com/hathach/allwinner_driver.git',                '8e5e89e8e132c0fd90e72d5422e5d3d68232b756'],
+    'hw/mcu/bridgetek/ft9xx/ft90x-sdk'            : [ 'https://github.com/BRTSG-FOSS/ft90x-sdk.git',                    '91060164afe239fcb394122e8bf9eb24d3194eb1'],
+    'hw/mcu/broadcom'                             : [ 'https://github.com/adafruit/broadcom-peripherals.git',           '08370086080759ed54ac1136d62d2ad24c6fa267'],
+    'hw/mcu/gd/nuclei-sdk'                        : [ 'https://github.com/Nuclei-Software/nuclei-sdk.git',              '7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7'],
+    'hw/mcu/infineon/mtb-xmclib-cat3'             : [ 'https://github.com/Infineon/mtb-xmclib-cat3.git',                'daf5500d03cba23e68c2f241c30af79cd9d63880'],
+    'hw/mcu/microchip'                            : [ 'https://github.com/hathach/microchip_driver.git',                '9e8b37e307d8404033bb881623a113931e1edf27'],
+    'hw/mcu/mindmotion/mm32sdk'                   : [ 'https://github.com/hathach/mm32sdk.git',                         '708a7152952ac595d24837069dcc0f7f59a4c30b'],
+    'hw/mcu/nordic/nrfx'                          : [ 'https://github.com/NordicSemiconductor/nrfx.git',                '281cc2e178fd9a470d844b3afdea9eb322a0b0e8'],
+    'hw/mcu/nuvoton'                              : [ 'https://github.com/majbthrd/nuc_driver.git',                     '2204191ec76283371419fbcec207da02e1bc22fa'],
+    'hw/mcu/nxp/lpcopen'                          : [ 'https://github.com/hathach/nxp_lpcopen.git',                     '43c45c85405a5dd114fff0ea95cca62837740c13'],
+    'hw/mcu/nxp/mcux-sdk'                         : [ 'https://github.com/NXPmicro/mcux-sdk.git',                       'ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294'],
+    'hw/mcu/nxp/nxp_sdk'                          : [ 'https://github.com/hathach/nxp_sdk.git',                         '845c8fc49b6fb660f06a5c45225494eacb06f00c'],
+    'hw/mcu/raspberry_pi/Pico-PIO-USB'            : [ 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',             '9ff3f52fd3c1f81532bce8dd311aa8fc8d9b2665'],
+    'hw/mcu/renesas/rx'                           : [ 'https://github.com/kkitayam/rx_device.git',                      '706b4e0cf485605c32351e2f90f5698267996023'],
+    'hw/mcu/silabs/cmsis-dfp-efm32gg12b'          : [ 'https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git',        'f1c31b7887669cb230b3ea63f9b56769078960bc'],
+    'hw/mcu/sony/cxd56/spresense-exported-sdk'    : [ 'https://github.com/sonydevworld/spresense-exported-sdk.git',     '2ec2a1538362696118dc3fdf56f33dacaf8f4067'],
+    'hw/mcu/st/cmsis_device_f0'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f0.git',      '2fc25ee22264bc27034358be0bd400b893ef837e'],
+    'hw/mcu/st/cmsis_device_f1'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f1.git',      '6601104a6397299b7304fd5bcd9a491f56cb23a6'],
+    'hw/mcu/st/cmsis_device_f2'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f2.git',      '182fcb3681ce116816feb41b7764f1b019ce796f'],
+    'hw/mcu/st/cmsis_device_f3'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f3.git',      '5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b'],
+    'hw/mcu/st/cmsis_device_f4'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f4.git',      '2615e866fa48fe1ff1af9e31c348813f2b19e7ec'],
+    'hw/mcu/st/cmsis_device_f7'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f7.git',      'fc676ef1ad177eb874eaa06444d3d75395fc51f4'],
+    'hw/mcu/st/cmsis_device_g0'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_g0.git',      '08258b28ee95f50cb9624d152a1cbf084be1f9a5'],
+    'hw/mcu/st/cmsis_device_g4'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_g4.git',      'ce822adb1dc552b3aedd13621edbc7fdae124878'],
+    'hw/mcu/st/cmsis_device_h7'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_h7.git',      '60dc2c913203dc8629dc233d4384dcc41c91e77f'],
+    'hw/mcu/st/cmsis_device_l0'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_l0.git',      '06748ca1f93827befdb8b794402320d94d02004f'],
+    'hw/mcu/st/cmsis_device_l1'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_l1.git',      '7f16ec0a1c4c063f84160b4cc6bf88ad554a823e'],
+    'hw/mcu/st/cmsis_device_l4'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_l4.git',      '6ca7312fa6a5a460b5a5a63d66da527fdd8359a6'],
+    'hw/mcu/st/cmsis_device_l5'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_l5.git',      'd922865fc0326a102c26211c44b8e42f52c1e53d'],
+    'hw/mcu/st/cmsis_device_u5'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_u5.git',      'bc00f3c9d8a4e25220f84c26d414902cc6bdf566'],
+    'hw/mcu/st/cmsis_device_wb'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_wb.git',      '9c5d1920dd9fabbe2548e10561d63db829bb744f'],
+    'hw/mcu/st/stm32f0xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git', '0e95cd88657030f640a11e690a8a5186c7712ea5'],
+    'hw/mcu/st/stm32f1xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git', '1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29'],
+    'hw/mcu/st/stm32f2xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git', 'c75ace9b908a9aca631193ebf2466963b8ea33d0'],
+    'hw/mcu/st/stm32f3xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git', '1761b6207318ede021706e75aae78f452d72b6fa'],
+    'hw/mcu/st/stm32f4xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git', '04e99fbdabd00ab8f370f377c66b0a4570365b58'],
+    'hw/mcu/st/stm32f7xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git', 'f7ffdf6bf72110e58b42c632b0a051df5997e4ee'],
+    'hw/mcu/st/stm32g0xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git', '5b53e6cee664a82b16c86491aa0060e2110c00cb'],
+    'hw/mcu/st/stm32g4xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git', '8b4518417706d42eef5c14e56a650005abf478a8'],
+    'hw/mcu/st/stm32h7xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git', 'd8461b980b59b1625207d8c4f2ce0a9c2a7a3b04'],
+    'hw/mcu/st/stm32l0xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git', 'fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b'],
+    'hw/mcu/st/stm32l1xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git', '44efc446fa69ed8344e7fd966e68ed11043b35d9'],
+    'hw/mcu/st/stm32l4xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git', 'aee3d5bf283ae5df87532b781bdd01b7caf256fc'],
+    'hw/mcu/st/stm32l5xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git', '675c32a75df37f39d50d61f51cb0dcf53f07e1cb'],
+    'hw/mcu/st/stm32u5xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git', '2e1d4cdb386e33391cb261dfff4fefa92e4aa35a'],
+    'hw/mcu/st/stm32wbxx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git', '2c5f06638be516c1b772f768456ba637f077bac8'],
+    'hw/mcu/ti'                                   : [ 'https://github.com/hathach/ti_driver.git',                       '143ed6cc20a7615d042b03b21e070197d473e6e5'],
+    'hw/mcu/wch/ch32v307'                         : [ 'https://github.com/openwch/ch32v307.git',                        '17761f5cf9dbbf2dcf665b7c04934188add20082'],
+    'lib/CMSIS_5'                                 : [ 'https://github.com/ARM-software/CMSIS_5.git',                    '20285262657d1b482d132d20d755c8c330d55c1f'],
+    'lib/FreeRTOS-Kernel'                         : [ 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git',                '2a604f4a2818b8354b5e1a39e388eb5e16cfbc1f'],
+    'lib/lwip'                                    : [ 'https://github.com/lwip-tcpip/lwip.git',                         '159e31b689577dbf69cf0683bbaffbd71fa5ee10'],
+    'lib/sct_neopixel'                            : [ 'https://github.com/gsteiert/sct_neopixel.git',                   'e73e04ca63495672d955f9268e003cffe168fcd8'],
+    'tools/uf2'                                   : [ 'https://github.com/microsoft/uf2.git',                           '19615407727073e36d81bf239c52108ba92e7660'],
+}
+
+# TOP is tinyusb root dir
+TOP = Path(__file__).parent.parent.resolve()
 
 
-# dependency lookup (ABC sorted)
-# deps = {
-#    'LPC11UXX' : [ [] ]
-# }
+def get_a_dep(d):
+    if d not in deps_list.keys():
+        print('{} is not found in dependency list')
+        return 1
+    url = deps_list[d][0]
+    commit = deps_list[d][1]
+    print('cloning {} with {}'.format(d, url))
 
+    p = Path(TOP / d)
+    git_cmd = "git -C {}".format(p)
+
+    # Init git deps if not existed
+    if not p.exists():
+        p.mkdir(parents=True)
+        subprocess.run("{} init".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        subprocess.run("{} remote add origin {}".format(git_cmd, url), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+
+    # Check if commit is already fetched
+    result = subprocess.run("{} rev-parse HEAD".format(git_cmd, commit), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+    head = result.stdout.decode("utf-8").splitlines()[0]
+    if commit != head:
+        subprocess.run("{} fetch --depth 1 origin {}".format(git_cmd, commit), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        subprocess.run("{} checkout FETCH_HEAD".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+
+    return 0
 
-def get_family_dep(family):
-    for entry in os.scandir("hw/bsp/{}/boards".format(family)):
-        if entry.is_dir():
-            result = subprocess.run("make -C examples/device/board_test BOARD={} get-deps".format(entry.name),
-                                    shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-            print(result.stdout.decode("utf-8"))
-            return result.returncode
 
 status = 0
-all_family = sys.argv[1:]
-for f in all_family:
-    status += get_family_dep(f)
+for d in sys.argv[1:]:
+    status += get_a_dep(d)
 
-sys.exit(status)
\ No newline at end of file
+sys.exit(status)
diff --git a/tools/get_family_deps.py b/tools/get_family_deps.py
new file mode 100644
index 000000000..e382d709b
--- /dev/null
+++ b/tools/get_family_deps.py
@@ -0,0 +1,19 @@
+import sys
+import subprocess
+import os
+
+
+def get_family_dep(family):
+    for entry in os.scandir("hw/bsp/{}/boards".format(family)):
+        if entry.is_dir():
+            result = subprocess.run("make -C examples/device/board_test BOARD={} get-deps".format(entry.name),
+                                    shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+            print(result.stdout.decode("utf-8"))
+            return result.returncode
+
+
+status = 0
+for d in sys.argv[1:]:
+    status += get_family_dep(d)
+
+sys.exit(status)

From 7c9bd81eca6d9a405c8a3ee1d012f370b88b44d1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Mar 2023 22:49:49 +0700
Subject: [PATCH 1524/2085] update deps script

---
 tools/get_deps.py        | 30 +++++++++++++++++-------------
 tools/get_family_deps.py |  6 ++++--
 2 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index 7ce02cc33..6e7093816 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -1,8 +1,9 @@
 import sys
 import subprocess
 from pathlib import Path
+from multiprocessing import Pool
 
-# path, url, commit
+# path, url, commit (Alphabet sorted by path)
 deps_list = {
     'hw/mcu/allwinner'                            : [ 'https://github.com/hathach/allwinner_driver.git',                '8e5e89e8e132c0fd90e72d5422e5d3d68232b756'],
     'hw/mcu/bridgetek/ft9xx/ft90x-sdk'            : [ 'https://github.com/BRTSG-FOSS/ft90x-sdk.git',                    '91060164afe239fcb394122e8bf9eb24d3194eb1'],
@@ -53,10 +54,10 @@ deps_list = {
     'hw/mcu/ti'                                   : [ 'https://github.com/hathach/ti_driver.git',                       '143ed6cc20a7615d042b03b21e070197d473e6e5'],
     'hw/mcu/wch/ch32v307'                         : [ 'https://github.com/openwch/ch32v307.git',                        '17761f5cf9dbbf2dcf665b7c04934188add20082'],
     'lib/CMSIS_5'                                 : [ 'https://github.com/ARM-software/CMSIS_5.git',                    '20285262657d1b482d132d20d755c8c330d55c1f'],
-    'lib/FreeRTOS-Kernel'                         : [ 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git',                '2a604f4a2818b8354b5e1a39e388eb5e16cfbc1f'],
-    'lib/lwip'                                    : [ 'https://github.com/lwip-tcpip/lwip.git',                         '159e31b689577dbf69cf0683bbaffbd71fa5ee10'],
+    #'lib/FreeRTOS-Kernel'                         : [ 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git',                '2a604f4a2818b8354b5e1a39e388eb5e16cfbc1f'],
+    #'lib/lwip'                                    : [ 'https://github.com/lwip-tcpip/lwip.git',                         '159e31b689577dbf69cf0683bbaffbd71fa5ee10'],
     'lib/sct_neopixel'                            : [ 'https://github.com/gsteiert/sct_neopixel.git',                   'e73e04ca63495672d955f9268e003cffe168fcd8'],
-    'tools/uf2'                                   : [ 'https://github.com/microsoft/uf2.git',                           '19615407727073e36d81bf239c52108ba92e7660'],
+    #'tools/uf2'                                   : [ 'https://github.com/microsoft/uf2.git',                           '19615407727073e36d81bf239c52108ba92e7660'],
 }
 
 # TOP is tinyusb root dir
@@ -77,21 +78,24 @@ def get_a_dep(d):
     # Init git deps if not existed
     if not p.exists():
         p.mkdir(parents=True)
-        subprocess.run("{} init".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        subprocess.run("{} remote add origin {}".format(git_cmd, url), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        subprocess.run("{} init".format(git_cmd), shell=True)
+        subprocess.run("{} remote add origin {}".format(git_cmd, url), shell=True)
 
     # Check if commit is already fetched
     result = subprocess.run("{} rev-parse HEAD".format(git_cmd, commit), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
     head = result.stdout.decode("utf-8").splitlines()[0]
+
     if commit != head:
-        subprocess.run("{} fetch --depth 1 origin {}".format(git_cmd, commit), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        subprocess.run("{} checkout FETCH_HEAD".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        subprocess.run("{} fetch --depth 1 origin {}".format(git_cmd, commit), shell=True)
+        subprocess.run("{} checkout FETCH_HEAD".format(git_cmd), shell=True)
 
     return 0
 
 
-status = 0
-for d in sys.argv[1:]:
-    status += get_a_dep(d)
-
-sys.exit(status)
+if __name__ == "__main__":
+    status = 0
+    all_deps = sys.argv[1:]
+    with Pool() as pool:
+        result = pool.map(get_a_dep, all_deps)
+        status = sum(result)
+    sys.exit(status)
diff --git a/tools/get_family_deps.py b/tools/get_family_deps.py
index e382d709b..071d7b756 100644
--- a/tools/get_family_deps.py
+++ b/tools/get_family_deps.py
@@ -2,11 +2,13 @@ import sys
 import subprocess
 import os
 
+# TOP is tinyusb root dir
+TOP = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
 
 def get_family_dep(family):
-    for entry in os.scandir("hw/bsp/{}/boards".format(family)):
+    for entry in os.scandir("{}/hw/bsp/{}/boards".format(TOP, family)):
         if entry.is_dir():
-            result = subprocess.run("make -C examples/device/board_test BOARD={} get-deps".format(entry.name),
+            result = subprocess.run("make -C {}/examples/device/board_test BOARD={} get-deps".format(TOP, entry.name),
                                     shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
             print(result.stdout.decode("utf-8"))
             return result.returncode

From fb9180b6eb2ec1b76bf5b01d611901d986f85d83 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Mar 2023 23:36:53 +0700
Subject: [PATCH 1525/2085] remove most of the submodules

---
 .gitmodules                              | 138 -----------------------
 hw/mcu/allwinner                         |   1 -
 hw/mcu/bridgetek/ft9xx/ft90x-sdk         |   1 -
 hw/mcu/gd/nuclei-sdk                     |   1 -
 hw/mcu/infineon/mtb-xmclib-cat3          |   1 -
 hw/mcu/microchip                         |   1 -
 hw/mcu/mindmotion/mm32sdk                |   1 -
 hw/mcu/nuvoton                           |   1 -
 hw/mcu/nxp/lpcopen                       |   1 -
 hw/mcu/nxp/mcux-sdk                      |   1 -
 hw/mcu/nxp/nxp_sdk                       |   1 -
 hw/mcu/raspberry_pi/Pico-PIO-USB         |   1 -
 hw/mcu/renesas/rx                        |   1 -
 hw/mcu/silabs/cmsis-dfp-efm32gg12b       |   1 -
 hw/mcu/sony/cxd56/spresense-exported-sdk |   1 -
 hw/mcu/st/cmsis_device_f0                |   1 -
 hw/mcu/st/cmsis_device_f1                |   1 -
 hw/mcu/st/cmsis_device_f2                |   1 -
 hw/mcu/st/cmsis_device_f3                |   1 -
 hw/mcu/st/cmsis_device_f4                |   1 -
 hw/mcu/st/cmsis_device_f7                |   1 -
 hw/mcu/st/cmsis_device_g0                |   1 -
 hw/mcu/st/cmsis_device_g4                |   1 -
 hw/mcu/st/cmsis_device_h7                |   1 -
 hw/mcu/st/cmsis_device_l0                |   1 -
 hw/mcu/st/cmsis_device_l1                |   1 -
 hw/mcu/st/cmsis_device_l4                |   1 -
 hw/mcu/st/cmsis_device_l5                |   1 -
 hw/mcu/st/cmsis_device_u5                |   1 -
 hw/mcu/st/cmsis_device_wb                |   1 -
 hw/mcu/st/stm32f0xx_hal_driver           |   1 -
 hw/mcu/st/stm32f1xx_hal_driver           |   1 -
 hw/mcu/st/stm32f2xx_hal_driver           |   1 -
 hw/mcu/st/stm32f3xx_hal_driver           |   1 -
 hw/mcu/st/stm32f4xx_hal_driver           |   1 -
 hw/mcu/st/stm32f7xx_hal_driver           |   1 -
 hw/mcu/st/stm32g0xx_hal_driver           |   1 -
 hw/mcu/st/stm32g4xx_hal_driver           |   1 -
 hw/mcu/st/stm32h7xx_hal_driver           |   1 -
 hw/mcu/st/stm32l0xx_hal_driver           |   1 -
 hw/mcu/st/stm32l1xx_hal_driver           |   1 -
 hw/mcu/st/stm32l4xx_hal_driver           |   1 -
 hw/mcu/st/stm32l5xx_hal_driver           |   1 -
 hw/mcu/st/stm32u5xx_hal_driver           |   1 -
 hw/mcu/st/stm32wbxx_hal_driver           |   1 -
 hw/mcu/wch/ch32v307                      |   1 -
 lib/sct_neopixel                         |   1 -
 47 files changed, 184 deletions(-)
 delete mode 160000 hw/mcu/allwinner
 delete mode 160000 hw/mcu/bridgetek/ft9xx/ft90x-sdk
 delete mode 160000 hw/mcu/gd/nuclei-sdk
 delete mode 160000 hw/mcu/infineon/mtb-xmclib-cat3
 delete mode 160000 hw/mcu/microchip
 delete mode 160000 hw/mcu/mindmotion/mm32sdk
 delete mode 160000 hw/mcu/nuvoton
 delete mode 160000 hw/mcu/nxp/lpcopen
 delete mode 160000 hw/mcu/nxp/mcux-sdk
 delete mode 160000 hw/mcu/nxp/nxp_sdk
 delete mode 160000 hw/mcu/raspberry_pi/Pico-PIO-USB
 delete mode 160000 hw/mcu/renesas/rx
 delete mode 160000 hw/mcu/silabs/cmsis-dfp-efm32gg12b
 delete mode 160000 hw/mcu/sony/cxd56/spresense-exported-sdk
 delete mode 160000 hw/mcu/st/cmsis_device_f0
 delete mode 160000 hw/mcu/st/cmsis_device_f1
 delete mode 160000 hw/mcu/st/cmsis_device_f2
 delete mode 160000 hw/mcu/st/cmsis_device_f3
 delete mode 160000 hw/mcu/st/cmsis_device_f4
 delete mode 160000 hw/mcu/st/cmsis_device_f7
 delete mode 160000 hw/mcu/st/cmsis_device_g0
 delete mode 160000 hw/mcu/st/cmsis_device_g4
 delete mode 160000 hw/mcu/st/cmsis_device_h7
 delete mode 160000 hw/mcu/st/cmsis_device_l0
 delete mode 160000 hw/mcu/st/cmsis_device_l1
 delete mode 160000 hw/mcu/st/cmsis_device_l4
 delete mode 160000 hw/mcu/st/cmsis_device_l5
 delete mode 160000 hw/mcu/st/cmsis_device_u5
 delete mode 160000 hw/mcu/st/cmsis_device_wb
 delete mode 160000 hw/mcu/st/stm32f0xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32f1xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32f2xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32f3xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32f4xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32f7xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32g0xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32g4xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32h7xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32l0xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32l1xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32l4xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32l5xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32u5xx_hal_driver
 delete mode 160000 hw/mcu/st/stm32wbxx_hal_driver
 delete mode 160000 hw/mcu/wch/ch32v307
 delete mode 160000 lib/sct_neopixel

diff --git a/.gitmodules b/.gitmodules
index c3baaa1be..e0eb5fb35 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,154 +1,16 @@
 [submodule "tools/uf2"]
 	path = tools/uf2
 	url = https://github.com/microsoft/uf2.git
-[submodule "hw/mcu/sony/cxd56/spresense-exported-sdk"]
-	path = hw/mcu/sony/cxd56/spresense-exported-sdk
-	url = https://github.com/sonydevworld/spresense-exported-sdk.git
 [submodule "hw/mcu/ti"]
 	path = hw/mcu/ti
 	url = https://github.com/hathach/ti_driver.git
-[submodule "hw/mcu/microchip"]
-	path = hw/mcu/microchip
-	url = https://github.com/hathach/microchip_driver.git
-[submodule "hw/mcu/nuvoton"]
-	path = hw/mcu/nuvoton
-	url = https://github.com/majbthrd/nuc_driver.git
 [submodule "lib/lwip"]
 	path = lib/lwip
 	url = https://github.com/lwip-tcpip/lwip.git
-[submodule "hw/mcu/st/cmsis_device_f4"]
-	path = hw/mcu/st/cmsis_device_f4
-	url = https://github.com/STMicroelectronics/cmsis_device_f4.git
-[submodule "hw/mcu/st/stm32f4xx_hal_driver"]
-	path = hw/mcu/st/stm32f4xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f0"]
-	path = hw/mcu/st/cmsis_device_f0
-	url = https://github.com/STMicroelectronics/cmsis_device_f0.git
-[submodule "hw/mcu/st/stm32f0xx_hal_driver"]
-	path = hw/mcu/st/stm32f0xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f1"]
-	path = hw/mcu/st/cmsis_device_f1
-	url = https://github.com/STMicroelectronics/cmsis_device_f1.git
-[submodule "hw/mcu/st/stm32f1xx_hal_driver"]
-	path = hw/mcu/st/stm32f1xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f2"]
-	path = hw/mcu/st/cmsis_device_f2
-	url = https://github.com/STMicroelectronics/cmsis_device_f2.git
-[submodule "hw/mcu/st/stm32f2xx_hal_driver"]
-	path = hw/mcu/st/stm32f2xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f3"]
-	path = hw/mcu/st/cmsis_device_f3
-	url = https://github.com/STMicroelectronics/cmsis_device_f3.git
-[submodule "hw/mcu/st/stm32f3xx_hal_driver"]
-	path = hw/mcu/st/stm32f3xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_f7"]
-	path = hw/mcu/st/cmsis_device_f7
-	url = https://github.com/STMicroelectronics/cmsis_device_f7.git
-[submodule "hw/mcu/st/stm32f7xx_hal_driver"]
-	path = hw/mcu/st/stm32f7xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_h7"]
-	path = hw/mcu/st/cmsis_device_h7
-	url = https://github.com/STMicroelectronics/cmsis_device_h7.git
-[submodule "hw/mcu/st/stm32h7xx_hal_driver"]
-	path = hw/mcu/st/stm32h7xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l0"]
-	path = hw/mcu/st/cmsis_device_l0
-	url = https://github.com/STMicroelectronics/cmsis_device_l0.git
-[submodule "hw/mcu/st/stm32l0xx_hal_driver"]
-	path = hw/mcu/st/stm32l0xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l1"]
-	path = hw/mcu/st/cmsis_device_l1
-	url = https://github.com/STMicroelectronics/cmsis_device_l1.git
-[submodule "hw/mcu/st/stm32l1xx_hal_driver"]
-	path = hw/mcu/st/stm32l1xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l4"]
-	path = hw/mcu/st/cmsis_device_l4
-	url = https://github.com/STMicroelectronics/cmsis_device_l4.git
-[submodule "hw/mcu/st/stm32l4xx_hal_driver"]
-	path = hw/mcu/st/stm32l4xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_g0"]
-	path = hw/mcu/st/cmsis_device_g0
-	url = https://github.com/STMicroelectronics/cmsis_device_g0.git
-[submodule "hw/mcu/st/stm32g0xx_hal_driver"]
-	path = hw/mcu/st/stm32g0xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_g4"]
-	path = hw/mcu/st/cmsis_device_g4
-	url = https://github.com/STMicroelectronics/cmsis_device_g4.git
-[submodule "hw/mcu/st/stm32g4xx_hal_driver"]
-	path = hw/mcu/st/stm32g4xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_l5"]
-	path = hw/mcu/st/cmsis_device_l5
-	url = https://github.com/STMicroelectronics/cmsis_device_l5.git
-[submodule "hw/mcu/st/stm32l5xx_hal_driver"]
-	path = hw/mcu/st/stm32l5xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git
-[submodule "hw/mcu/st/cmsis_device_wb"]
-	path = hw/mcu/st/cmsis_device_wb
-	url = https://github.com/STMicroelectronics/cmsis_device_wb.git
-[submodule "hw/mcu/st/stm32wbxx_hal_driver"]
-	path = hw/mcu/st/stm32wbxx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git
-[submodule "lib/sct_neopixel"]
-	path = lib/sct_neopixel
-	url = https://github.com/gsteiert/sct_neopixel
 [submodule "lib/FreeRTOS-Kernel"]
 	path = lib/FreeRTOS-Kernel
 	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
-[submodule "hw/mcu/silabs/cmsis-dfp-efm32gg12b"]
-	path = hw/mcu/silabs/cmsis-dfp-efm32gg12b
-	url = https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b
-[submodule "hw/mcu/renesas/rx"]
-	path = hw/mcu/renesas/rx
-	url = https://github.com/kkitayam/rx_device.git
-[submodule "hw/mcu/nxp/lpcopen"]
-	path = hw/mcu/nxp/lpcopen
-	url = https://github.com/hathach/nxp_lpcopen.git
-[submodule "hw/mcu/nxp/mcux-sdk"]
-	path = hw/mcu/nxp/mcux-sdk
-	url = https://github.com/NXPmicro/mcux-sdk.git
-[submodule "hw/mcu/nxp/nxp_sdk"]
-	path = hw/mcu/nxp/nxp_sdk
-	url = https://github.com/hathach/nxp_sdk.git
-[submodule "hw/mcu/gd/nuclei-sdk"]
-	path = hw/mcu/gd/nuclei-sdk
-	url = https://github.com/Nuclei-Software/nuclei-sdk.git
-[submodule "hw/mcu/bridgetek/ft9xx/ft90x-sdk"]
-	path = hw/mcu/bridgetek/ft9xx/ft90x-sdk
-	url = https://github.com/BRTSG-FOSS/ft90x-sdk
-[submodule "hw/mcu/mindmotion/mm32sdk"]
-	path = hw/mcu/mindmotion/mm32sdk
-	url = https://github.com/hathach/mm32sdk.git
 [submodule "hw/mcu/broadcom"]
 	path = hw/mcu/broadcom
 	url = https://github.com/adafruit/broadcom-peripherals.git
 	branch = main-build
-[submodule "hw/mcu/infineon/mtb-xmclib-cat3"]
-	path = hw/mcu/infineon/mtb-xmclib-cat3
-	url = https://github.com/Infineon/mtb-xmclib-cat3.git
-[submodule "hw/mcu/allwinner"]
-	path = hw/mcu/allwinner
-	url = https://github.com/hathach/allwinner_driver.git
-[submodule "hw/mcu/wch/ch32v307"]
-	path = hw/mcu/wch/ch32v307
-	url = https://github.com/openwch/ch32v307.git
-[submodule "hw/mcu/raspberry_pi/Pico-PIO-USB"]
-	path = hw/mcu/raspberry_pi/Pico-PIO-USB
-	url = https://github.com/sekigon-gonnoc/Pico-PIO-USB.git
-[submodule "hw/mcu/st/cmsis_device_u5"]
-	path = hw/mcu/st/cmsis_device_u5
-	url = https://github.com/STMicroelectronics/cmsis_device_u5
-[submodule "hw/mcu/st/stm32u5xx_hal_driver"]
-	path = hw/mcu/st/stm32u5xx_hal_driver
-	url = https://github.com/STMicroelectronics/stm32u5xx_hal_driver
diff --git a/hw/mcu/allwinner b/hw/mcu/allwinner
deleted file mode 160000
index 8e5e89e8e..000000000
--- a/hw/mcu/allwinner
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 8e5e89e8e132c0fd90e72d5422e5d3d68232b756
diff --git a/hw/mcu/bridgetek/ft9xx/ft90x-sdk b/hw/mcu/bridgetek/ft9xx/ft90x-sdk
deleted file mode 160000
index 91060164a..000000000
--- a/hw/mcu/bridgetek/ft9xx/ft90x-sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 91060164afe239fcb394122e8bf9eb24d3194eb1
diff --git a/hw/mcu/gd/nuclei-sdk b/hw/mcu/gd/nuclei-sdk
deleted file mode 160000
index 7eb7bfa9e..000000000
--- a/hw/mcu/gd/nuclei-sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7
diff --git a/hw/mcu/infineon/mtb-xmclib-cat3 b/hw/mcu/infineon/mtb-xmclib-cat3
deleted file mode 160000
index daf5500d0..000000000
--- a/hw/mcu/infineon/mtb-xmclib-cat3
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit daf5500d03cba23e68c2f241c30af79cd9d63880
diff --git a/hw/mcu/microchip b/hw/mcu/microchip
deleted file mode 160000
index 9e8b37e30..000000000
--- a/hw/mcu/microchip
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9e8b37e307d8404033bb881623a113931e1edf27
diff --git a/hw/mcu/mindmotion/mm32sdk b/hw/mcu/mindmotion/mm32sdk
deleted file mode 160000
index 708a71529..000000000
--- a/hw/mcu/mindmotion/mm32sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 708a7152952ac595d24837069dcc0f7f59a4c30b
diff --git a/hw/mcu/nuvoton b/hw/mcu/nuvoton
deleted file mode 160000
index 2204191ec..000000000
--- a/hw/mcu/nuvoton
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2204191ec76283371419fbcec207da02e1bc22fa
diff --git a/hw/mcu/nxp/lpcopen b/hw/mcu/nxp/lpcopen
deleted file mode 160000
index 43c45c854..000000000
--- a/hw/mcu/nxp/lpcopen
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 43c45c85405a5dd114fff0ea95cca62837740c13
diff --git a/hw/mcu/nxp/mcux-sdk b/hw/mcu/nxp/mcux-sdk
deleted file mode 160000
index ae2ab01d9..000000000
--- a/hw/mcu/nxp/mcux-sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294
diff --git a/hw/mcu/nxp/nxp_sdk b/hw/mcu/nxp/nxp_sdk
deleted file mode 160000
index 845c8fc49..000000000
--- a/hw/mcu/nxp/nxp_sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 845c8fc49b6fb660f06a5c45225494eacb06f00c
diff --git a/hw/mcu/raspberry_pi/Pico-PIO-USB b/hw/mcu/raspberry_pi/Pico-PIO-USB
deleted file mode 160000
index 9ff3f52fd..000000000
--- a/hw/mcu/raspberry_pi/Pico-PIO-USB
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9ff3f52fd3c1f81532bce8dd311aa8fc8d9b2665
diff --git a/hw/mcu/renesas/rx b/hw/mcu/renesas/rx
deleted file mode 160000
index 706b4e0cf..000000000
--- a/hw/mcu/renesas/rx
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 706b4e0cf485605c32351e2f90f5698267996023
diff --git a/hw/mcu/silabs/cmsis-dfp-efm32gg12b b/hw/mcu/silabs/cmsis-dfp-efm32gg12b
deleted file mode 160000
index f1c31b788..000000000
--- a/hw/mcu/silabs/cmsis-dfp-efm32gg12b
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit f1c31b7887669cb230b3ea63f9b56769078960bc
diff --git a/hw/mcu/sony/cxd56/spresense-exported-sdk b/hw/mcu/sony/cxd56/spresense-exported-sdk
deleted file mode 160000
index 2ec2a1538..000000000
--- a/hw/mcu/sony/cxd56/spresense-exported-sdk
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2ec2a1538362696118dc3fdf56f33dacaf8f4067
diff --git a/hw/mcu/st/cmsis_device_f0 b/hw/mcu/st/cmsis_device_f0
deleted file mode 160000
index 2fc25ee22..000000000
--- a/hw/mcu/st/cmsis_device_f0
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2fc25ee22264bc27034358be0bd400b893ef837e
diff --git a/hw/mcu/st/cmsis_device_f1 b/hw/mcu/st/cmsis_device_f1
deleted file mode 160000
index 6601104a6..000000000
--- a/hw/mcu/st/cmsis_device_f1
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 6601104a6397299b7304fd5bcd9a491f56cb23a6
diff --git a/hw/mcu/st/cmsis_device_f2 b/hw/mcu/st/cmsis_device_f2
deleted file mode 160000
index 182fcb368..000000000
--- a/hw/mcu/st/cmsis_device_f2
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 182fcb3681ce116816feb41b7764f1b019ce796f
diff --git a/hw/mcu/st/cmsis_device_f3 b/hw/mcu/st/cmsis_device_f3
deleted file mode 160000
index 5e4ee5ed7..000000000
--- a/hw/mcu/st/cmsis_device_f3
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b
diff --git a/hw/mcu/st/cmsis_device_f4 b/hw/mcu/st/cmsis_device_f4
deleted file mode 160000
index 2615e866f..000000000
--- a/hw/mcu/st/cmsis_device_f4
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2615e866fa48fe1ff1af9e31c348813f2b19e7ec
diff --git a/hw/mcu/st/cmsis_device_f7 b/hw/mcu/st/cmsis_device_f7
deleted file mode 160000
index fc676ef1a..000000000
--- a/hw/mcu/st/cmsis_device_f7
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fc676ef1ad177eb874eaa06444d3d75395fc51f4
diff --git a/hw/mcu/st/cmsis_device_g0 b/hw/mcu/st/cmsis_device_g0
deleted file mode 160000
index 08258b28e..000000000
--- a/hw/mcu/st/cmsis_device_g0
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 08258b28ee95f50cb9624d152a1cbf084be1f9a5
diff --git a/hw/mcu/st/cmsis_device_g4 b/hw/mcu/st/cmsis_device_g4
deleted file mode 160000
index ce822adb1..000000000
--- a/hw/mcu/st/cmsis_device_g4
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit ce822adb1dc552b3aedd13621edbc7fdae124878
diff --git a/hw/mcu/st/cmsis_device_h7 b/hw/mcu/st/cmsis_device_h7
deleted file mode 160000
index 60dc2c913..000000000
--- a/hw/mcu/st/cmsis_device_h7
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 60dc2c913203dc8629dc233d4384dcc41c91e77f
diff --git a/hw/mcu/st/cmsis_device_l0 b/hw/mcu/st/cmsis_device_l0
deleted file mode 160000
index 06748ca1f..000000000
--- a/hw/mcu/st/cmsis_device_l0
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 06748ca1f93827befdb8b794402320d94d02004f
diff --git a/hw/mcu/st/cmsis_device_l1 b/hw/mcu/st/cmsis_device_l1
deleted file mode 160000
index 7f16ec0a1..000000000
--- a/hw/mcu/st/cmsis_device_l1
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 7f16ec0a1c4c063f84160b4cc6bf88ad554a823e
diff --git a/hw/mcu/st/cmsis_device_l4 b/hw/mcu/st/cmsis_device_l4
deleted file mode 160000
index 6ca7312fa..000000000
--- a/hw/mcu/st/cmsis_device_l4
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 6ca7312fa6a5a460b5a5a63d66da527fdd8359a6
diff --git a/hw/mcu/st/cmsis_device_l5 b/hw/mcu/st/cmsis_device_l5
deleted file mode 160000
index d922865fc..000000000
--- a/hw/mcu/st/cmsis_device_l5
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit d922865fc0326a102c26211c44b8e42f52c1e53d
diff --git a/hw/mcu/st/cmsis_device_u5 b/hw/mcu/st/cmsis_device_u5
deleted file mode 160000
index bc00f3c9d..000000000
--- a/hw/mcu/st/cmsis_device_u5
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit bc00f3c9d8a4e25220f84c26d414902cc6bdf566
diff --git a/hw/mcu/st/cmsis_device_wb b/hw/mcu/st/cmsis_device_wb
deleted file mode 160000
index 9c5d1920d..000000000
--- a/hw/mcu/st/cmsis_device_wb
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9c5d1920dd9fabbe2548e10561d63db829bb744f
diff --git a/hw/mcu/st/stm32f0xx_hal_driver b/hw/mcu/st/stm32f0xx_hal_driver
deleted file mode 160000
index 0e95cd886..000000000
--- a/hw/mcu/st/stm32f0xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 0e95cd88657030f640a11e690a8a5186c7712ea5
diff --git a/hw/mcu/st/stm32f1xx_hal_driver b/hw/mcu/st/stm32f1xx_hal_driver
deleted file mode 160000
index 1dd9d3662..000000000
--- a/hw/mcu/st/stm32f1xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29
diff --git a/hw/mcu/st/stm32f2xx_hal_driver b/hw/mcu/st/stm32f2xx_hal_driver
deleted file mode 160000
index c75ace9b9..000000000
--- a/hw/mcu/st/stm32f2xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit c75ace9b908a9aca631193ebf2466963b8ea33d0
diff --git a/hw/mcu/st/stm32f3xx_hal_driver b/hw/mcu/st/stm32f3xx_hal_driver
deleted file mode 160000
index 1761b6207..000000000
--- a/hw/mcu/st/stm32f3xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 1761b6207318ede021706e75aae78f452d72b6fa
diff --git a/hw/mcu/st/stm32f4xx_hal_driver b/hw/mcu/st/stm32f4xx_hal_driver
deleted file mode 160000
index 04e99fbda..000000000
--- a/hw/mcu/st/stm32f4xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 04e99fbdabd00ab8f370f377c66b0a4570365b58
diff --git a/hw/mcu/st/stm32f7xx_hal_driver b/hw/mcu/st/stm32f7xx_hal_driver
deleted file mode 160000
index f7ffdf6bf..000000000
--- a/hw/mcu/st/stm32f7xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit f7ffdf6bf72110e58b42c632b0a051df5997e4ee
diff --git a/hw/mcu/st/stm32g0xx_hal_driver b/hw/mcu/st/stm32g0xx_hal_driver
deleted file mode 160000
index 5b53e6cee..000000000
--- a/hw/mcu/st/stm32g0xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 5b53e6cee664a82b16c86491aa0060e2110c00cb
diff --git a/hw/mcu/st/stm32g4xx_hal_driver b/hw/mcu/st/stm32g4xx_hal_driver
deleted file mode 160000
index 8b4518417..000000000
--- a/hw/mcu/st/stm32g4xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 8b4518417706d42eef5c14e56a650005abf478a8
diff --git a/hw/mcu/st/stm32h7xx_hal_driver b/hw/mcu/st/stm32h7xx_hal_driver
deleted file mode 160000
index d8461b980..000000000
--- a/hw/mcu/st/stm32h7xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04
diff --git a/hw/mcu/st/stm32l0xx_hal_driver b/hw/mcu/st/stm32l0xx_hal_driver
deleted file mode 160000
index fbdacaf6f..000000000
--- a/hw/mcu/st/stm32l0xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b
diff --git a/hw/mcu/st/stm32l1xx_hal_driver b/hw/mcu/st/stm32l1xx_hal_driver
deleted file mode 160000
index 44efc446f..000000000
--- a/hw/mcu/st/stm32l1xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 44efc446fa69ed8344e7fd966e68ed11043b35d9
diff --git a/hw/mcu/st/stm32l4xx_hal_driver b/hw/mcu/st/stm32l4xx_hal_driver
deleted file mode 160000
index aee3d5bf2..000000000
--- a/hw/mcu/st/stm32l4xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit aee3d5bf283ae5df87532b781bdd01b7caf256fc
diff --git a/hw/mcu/st/stm32l5xx_hal_driver b/hw/mcu/st/stm32l5xx_hal_driver
deleted file mode 160000
index 675c32a75..000000000
--- a/hw/mcu/st/stm32l5xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 675c32a75df37f39d50d61f51cb0dcf53f07e1cb
diff --git a/hw/mcu/st/stm32u5xx_hal_driver b/hw/mcu/st/stm32u5xx_hal_driver
deleted file mode 160000
index 2e1d4cdb3..000000000
--- a/hw/mcu/st/stm32u5xx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2e1d4cdb386e33391cb261dfff4fefa92e4aa35a
diff --git a/hw/mcu/st/stm32wbxx_hal_driver b/hw/mcu/st/stm32wbxx_hal_driver
deleted file mode 160000
index 2c5f06638..000000000
--- a/hw/mcu/st/stm32wbxx_hal_driver
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2c5f06638be516c1b772f768456ba637f077bac8
diff --git a/hw/mcu/wch/ch32v307 b/hw/mcu/wch/ch32v307
deleted file mode 160000
index 17761f5cf..000000000
--- a/hw/mcu/wch/ch32v307
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 17761f5cf9dbbf2dcf665b7c04934188add20082
diff --git a/lib/sct_neopixel b/lib/sct_neopixel
deleted file mode 160000
index e73e04ca6..000000000
--- a/lib/sct_neopixel
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit e73e04ca63495672d955f9268e003cffe168fcd8

From 7e6a6e75bcdba408e6fd6dabc57d110b168e3d17 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Mar 2023 23:41:27 +0700
Subject: [PATCH 1526/2085] remove the rest of mcu submodules

---
 .gitmodules     | 7 -------
 hw/mcu/broadcom | 1 -
 hw/mcu/ti       | 1 -
 3 files changed, 9 deletions(-)
 delete mode 160000 hw/mcu/broadcom
 delete mode 160000 hw/mcu/ti

diff --git a/.gitmodules b/.gitmodules
index e0eb5fb35..469192026 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,16 +1,9 @@
 [submodule "tools/uf2"]
 	path = tools/uf2
 	url = https://github.com/microsoft/uf2.git
-[submodule "hw/mcu/ti"]
-	path = hw/mcu/ti
-	url = https://github.com/hathach/ti_driver.git
 [submodule "lib/lwip"]
 	path = lib/lwip
 	url = https://github.com/lwip-tcpip/lwip.git
 [submodule "lib/FreeRTOS-Kernel"]
 	path = lib/FreeRTOS-Kernel
 	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
-[submodule "hw/mcu/broadcom"]
-	path = hw/mcu/broadcom
-	url = https://github.com/adafruit/broadcom-peripherals.git
-	branch = main-build
diff --git a/hw/mcu/broadcom b/hw/mcu/broadcom
deleted file mode 160000
index 083700860..000000000
--- a/hw/mcu/broadcom
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 08370086080759ed54ac1136d62d2ad24c6fa267
diff --git a/hw/mcu/ti b/hw/mcu/ti
deleted file mode 160000
index 143ed6cc2..000000000
--- a/hw/mcu/ti
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 143ed6cc20a7615d042b03b21e070197d473e6e5

From 704f3ddeb5e6bfa3b4111a998564d979a9a95d1d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Mar 2023 23:43:07 +0700
Subject: [PATCH 1527/2085] add dependencies repo to git ignore

---
 .gitignore | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/.gitignore b/.gitignore
index 87a5faa80..ba3baa9b6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -28,3 +28,57 @@ cov-int
 /_bin/
 __pycache__
 
+# submodules
+hw/mcu/allwinner
+hw/mcu/bridgetek/ft9xx/ft90x-sdk
+hw/mcu/broadcom
+hw/mcu/gd/nuclei-sdk
+hw/mcu/infineon/mtb-xmclib-cat3
+hw/mcu/microchip
+hw/mcu/mindmotion/mm32sdk
+hw/mcu/nordic/nrfx
+hw/mcu/nuvoton
+hw/mcu/nxp/lpcopen
+hw/mcu/nxp/mcux-sdk
+hw/mcu/nxp/nxp_sdk
+hw/mcu/raspberry_pi/Pico-PIO-USB
+hw/mcu/renesas/rx
+hw/mcu/silabs/cmsis-dfp-efm32gg12b
+hw/mcu/sony/cxd56/spresense-exported-sdk
+hw/mcu/st/cmsis_device_f0
+hw/mcu/st/cmsis_device_f1
+hw/mcu/st/cmsis_device_f2
+hw/mcu/st/cmsis_device_f3
+hw/mcu/st/cmsis_device_f4
+hw/mcu/st/cmsis_device_f7
+hw/mcu/st/cmsis_device_g0
+hw/mcu/st/cmsis_device_g4
+hw/mcu/st/cmsis_device_h7
+hw/mcu/st/cmsis_device_l0
+hw/mcu/st/cmsis_device_l1
+hw/mcu/st/cmsis_device_l4
+hw/mcu/st/cmsis_device_l5
+hw/mcu/st/cmsis_device_u5
+hw/mcu/st/cmsis_device_wb
+hw/mcu/st/stm32f0xx_hal_driver
+hw/mcu/st/stm32f1xx_hal_driver
+hw/mcu/st/stm32f2xx_hal_driver
+hw/mcu/st/stm32f3xx_hal_driver
+hw/mcu/st/stm32f4xx_hal_driver
+hw/mcu/st/stm32f7xx_hal_driver
+hw/mcu/st/stm32g0xx_hal_driver
+hw/mcu/st/stm32g4xx_hal_driver
+hw/mcu/st/stm32h7xx_hal_driver
+hw/mcu/st/stm32l0xx_hal_driver
+hw/mcu/st/stm32l1xx_hal_driver
+hw/mcu/st/stm32l4xx_hal_driver
+hw/mcu/st/stm32l5xx_hal_driver
+hw/mcu/st/stm32u5xx_hal_driver
+hw/mcu/st/stm32wbxx_hal_driver
+hw/mcu/ti
+hw/mcu/wch/ch32v307
+lib/CMSIS_5
+lib/FreeRTOS-Kernel
+lib/lwip
+lib/sct_neopixel
+tools/uf2

From 206a9a21e6297b49287605ad8ddf1ab47124358e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Mar 2023 23:54:30 +0700
Subject: [PATCH 1528/2085] fix ci

---
 .github/workflows/build_aarch64.yml | 2 +-
 .github/workflows/build_iar.yml     | 8 +-------
 hw/bsp/rx/boards/gr_citrus/board.mk | 2 --
 3 files changed, 2 insertions(+), 10 deletions(-)

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 5818ea432..30df2bdf0 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -43,7 +43,7 @@ jobs:
       uses: actions/checkout@v3
 
     - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
+      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
 
     - name: Checkout hathach/linkermap
       uses: actions/checkout@v3
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 7f2a92010..afb6efb6b 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -44,14 +44,8 @@ jobs:
 
     - name: Checkout submodules and dependencies
       run: |
-        git submodule update --init lib/FreeRTOS-Kernel lib/lwip lib/sct_neopixel
+        git submodule update --init lib/FreeRTOS-Kernel lib/lwip
         python3 tools/get_family_deps.py ${{ matrix.family }}
 
-    #- name: Checkout pico-sdk for rp2040
-    #  if: matrix.family == 'rp2040'
-    #  run: |
-    #    git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
-    #    echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
-
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }} CC=iccarm
diff --git a/hw/bsp/rx/boards/gr_citrus/board.mk b/hw/bsp/rx/boards/gr_citrus/board.mk
index 0eba94610..235cefc61 100644
--- a/hw/bsp/rx/boards/gr_citrus/board.mk
+++ b/hw/bsp/rx/boards/gr_citrus/board.mk
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += hw/mcu/renesas/rx
-
 CFLAGS += \
   -mcpu=rx610 \
   -misa=v1 \

From 4857abdc6bc58ebd06ce87c0139ed8a789b0d440 Mon Sep 17 00:00:00 2001
From: Dan Halbert <halbert@halwitz.org>
Date: Fri, 10 Mar 2023 14:01:51 -0500
Subject: [PATCH 1529/2085] rp2040: include hardware/sync.h explicitly

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 8df7bef2b..37dec1cbf 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -29,6 +29,7 @@
 #if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RP2040) && !CFG_TUD_RPI_PIO_USB
 
 #include "pico.h"
+#include "hardware/sync.h"
 #include "rp2040_usb.h"
 
 #if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX

From 7428a16d2d5891b5ceadcd0530798c8933d02f6f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 11 Mar 2023 08:23:21 +0700
Subject: [PATCH 1530/2085] remove ra submodules

---
 .gitmodules         | 3 ---
 hw/bsp/ra/family.mk | 2 +-
 hw/mcu/renesas/fsp  | 1 -
 tools/get_deps.py   | 1 +
 4 files changed, 2 insertions(+), 5 deletions(-)
 delete mode 160000 hw/mcu/renesas/fsp

diff --git a/.gitmodules b/.gitmodules
index 320a5f7f6..469192026 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -7,6 +7,3 @@
 [submodule "lib/FreeRTOS-Kernel"]
 	path = lib/FreeRTOS-Kernel
 	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
-[submodule "hw/mcu/renesas/fsp"]
-	path = hw/mcu/renesas/fsp
-	url = https://github.com/renesas/fsp
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 6b7f43345..e75e74104 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -40,7 +40,7 @@ SRC_C += \
 	$(FSP_BOARD_DIR)/board_leds.c
 
 INC += \
-  	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(BOARD_PATH)/fsp_cfg \
diff --git a/hw/mcu/renesas/fsp b/hw/mcu/renesas/fsp
deleted file mode 160000
index 8dc14709f..000000000
--- a/hw/mcu/renesas/fsp
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 8dc14709f2a6518b43f71efad70d900b7718d9f1
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 6e7093816..df606bfab 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -18,6 +18,7 @@ deps_list = {
     'hw/mcu/nxp/mcux-sdk'                         : [ 'https://github.com/NXPmicro/mcux-sdk.git',                       'ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294'],
     'hw/mcu/nxp/nxp_sdk'                          : [ 'https://github.com/hathach/nxp_sdk.git',                         '845c8fc49b6fb660f06a5c45225494eacb06f00c'],
     'hw/mcu/raspberry_pi/Pico-PIO-USB'            : [ 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',             '9ff3f52fd3c1f81532bce8dd311aa8fc8d9b2665'],
+    'hw/mcu/renesas/fsp'                          : [ 'https://github.com/renesas/fsp.git',                             '8dc14709f2a6518b43f71efad70d900b7718d9f1'],
     'hw/mcu/renesas/rx'                           : [ 'https://github.com/kkitayam/rx_device.git',                      '706b4e0cf485605c32351e2f90f5698267996023'],
     'hw/mcu/silabs/cmsis-dfp-efm32gg12b'          : [ 'https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git',        'f1c31b7887669cb230b3ea63f9b56769078960bc'],
     'hw/mcu/sony/cxd56/spresense-exported-sdk'    : [ 'https://github.com/sonydevworld/spresense-exported-sdk.git',     '2ec2a1538362696118dc3fdf56f33dacaf8f4067'],

From cae05c65934384d2503baaad9ae55d4c68db6fdd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 11 Mar 2023 08:33:08 +0700
Subject: [PATCH 1531/2085] update get-deps.py

---
 tools/get_deps.py | 113 +++++++++++++++++++++++-----------------------
 1 file changed, 56 insertions(+), 57 deletions(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index 6e7093816..29bb35f15 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -5,59 +5,59 @@ from multiprocessing import Pool
 
 # path, url, commit (Alphabet sorted by path)
 deps_list = {
-    'hw/mcu/allwinner'                            : [ 'https://github.com/hathach/allwinner_driver.git',                '8e5e89e8e132c0fd90e72d5422e5d3d68232b756'],
-    'hw/mcu/bridgetek/ft9xx/ft90x-sdk'            : [ 'https://github.com/BRTSG-FOSS/ft90x-sdk.git',                    '91060164afe239fcb394122e8bf9eb24d3194eb1'],
-    'hw/mcu/broadcom'                             : [ 'https://github.com/adafruit/broadcom-peripherals.git',           '08370086080759ed54ac1136d62d2ad24c6fa267'],
-    'hw/mcu/gd/nuclei-sdk'                        : [ 'https://github.com/Nuclei-Software/nuclei-sdk.git',              '7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7'],
-    'hw/mcu/infineon/mtb-xmclib-cat3'             : [ 'https://github.com/Infineon/mtb-xmclib-cat3.git',                'daf5500d03cba23e68c2f241c30af79cd9d63880'],
-    'hw/mcu/microchip'                            : [ 'https://github.com/hathach/microchip_driver.git',                '9e8b37e307d8404033bb881623a113931e1edf27'],
-    'hw/mcu/mindmotion/mm32sdk'                   : [ 'https://github.com/hathach/mm32sdk.git',                         '708a7152952ac595d24837069dcc0f7f59a4c30b'],
-    'hw/mcu/nordic/nrfx'                          : [ 'https://github.com/NordicSemiconductor/nrfx.git',                '281cc2e178fd9a470d844b3afdea9eb322a0b0e8'],
-    'hw/mcu/nuvoton'                              : [ 'https://github.com/majbthrd/nuc_driver.git',                     '2204191ec76283371419fbcec207da02e1bc22fa'],
-    'hw/mcu/nxp/lpcopen'                          : [ 'https://github.com/hathach/nxp_lpcopen.git',                     '43c45c85405a5dd114fff0ea95cca62837740c13'],
-    'hw/mcu/nxp/mcux-sdk'                         : [ 'https://github.com/NXPmicro/mcux-sdk.git',                       'ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294'],
-    'hw/mcu/nxp/nxp_sdk'                          : [ 'https://github.com/hathach/nxp_sdk.git',                         '845c8fc49b6fb660f06a5c45225494eacb06f00c'],
-    'hw/mcu/raspberry_pi/Pico-PIO-USB'            : [ 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',             '9ff3f52fd3c1f81532bce8dd311aa8fc8d9b2665'],
-    'hw/mcu/renesas/rx'                           : [ 'https://github.com/kkitayam/rx_device.git',                      '706b4e0cf485605c32351e2f90f5698267996023'],
-    'hw/mcu/silabs/cmsis-dfp-efm32gg12b'          : [ 'https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git',        'f1c31b7887669cb230b3ea63f9b56769078960bc'],
-    'hw/mcu/sony/cxd56/spresense-exported-sdk'    : [ 'https://github.com/sonydevworld/spresense-exported-sdk.git',     '2ec2a1538362696118dc3fdf56f33dacaf8f4067'],
-    'hw/mcu/st/cmsis_device_f0'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f0.git',      '2fc25ee22264bc27034358be0bd400b893ef837e'],
-    'hw/mcu/st/cmsis_device_f1'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f1.git',      '6601104a6397299b7304fd5bcd9a491f56cb23a6'],
-    'hw/mcu/st/cmsis_device_f2'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f2.git',      '182fcb3681ce116816feb41b7764f1b019ce796f'],
-    'hw/mcu/st/cmsis_device_f3'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f3.git',      '5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b'],
-    'hw/mcu/st/cmsis_device_f4'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f4.git',      '2615e866fa48fe1ff1af9e31c348813f2b19e7ec'],
-    'hw/mcu/st/cmsis_device_f7'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_f7.git',      'fc676ef1ad177eb874eaa06444d3d75395fc51f4'],
-    'hw/mcu/st/cmsis_device_g0'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_g0.git',      '08258b28ee95f50cb9624d152a1cbf084be1f9a5'],
-    'hw/mcu/st/cmsis_device_g4'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_g4.git',      'ce822adb1dc552b3aedd13621edbc7fdae124878'],
-    'hw/mcu/st/cmsis_device_h7'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_h7.git',      '60dc2c913203dc8629dc233d4384dcc41c91e77f'],
-    'hw/mcu/st/cmsis_device_l0'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_l0.git',      '06748ca1f93827befdb8b794402320d94d02004f'],
-    'hw/mcu/st/cmsis_device_l1'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_l1.git',      '7f16ec0a1c4c063f84160b4cc6bf88ad554a823e'],
-    'hw/mcu/st/cmsis_device_l4'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_l4.git',      '6ca7312fa6a5a460b5a5a63d66da527fdd8359a6'],
-    'hw/mcu/st/cmsis_device_l5'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_l5.git',      'd922865fc0326a102c26211c44b8e42f52c1e53d'],
-    'hw/mcu/st/cmsis_device_u5'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_u5.git',      'bc00f3c9d8a4e25220f84c26d414902cc6bdf566'],
-    'hw/mcu/st/cmsis_device_wb'                   : [ 'https://github.com/STMicroelectronics/cmsis_device_wb.git',      '9c5d1920dd9fabbe2548e10561d63db829bb744f'],
-    'hw/mcu/st/stm32f0xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git', '0e95cd88657030f640a11e690a8a5186c7712ea5'],
-    'hw/mcu/st/stm32f1xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git', '1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29'],
-    'hw/mcu/st/stm32f2xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git', 'c75ace9b908a9aca631193ebf2466963b8ea33d0'],
-    'hw/mcu/st/stm32f3xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git', '1761b6207318ede021706e75aae78f452d72b6fa'],
-    'hw/mcu/st/stm32f4xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git', '04e99fbdabd00ab8f370f377c66b0a4570365b58'],
-    'hw/mcu/st/stm32f7xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git', 'f7ffdf6bf72110e58b42c632b0a051df5997e4ee'],
-    'hw/mcu/st/stm32g0xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git', '5b53e6cee664a82b16c86491aa0060e2110c00cb'],
-    'hw/mcu/st/stm32g4xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git', '8b4518417706d42eef5c14e56a650005abf478a8'],
-    'hw/mcu/st/stm32h7xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git', 'd8461b980b59b1625207d8c4f2ce0a9c2a7a3b04'],
-    'hw/mcu/st/stm32l0xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git', 'fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b'],
-    'hw/mcu/st/stm32l1xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git', '44efc446fa69ed8344e7fd966e68ed11043b35d9'],
-    'hw/mcu/st/stm32l4xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git', 'aee3d5bf283ae5df87532b781bdd01b7caf256fc'],
-    'hw/mcu/st/stm32l5xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git', '675c32a75df37f39d50d61f51cb0dcf53f07e1cb'],
-    'hw/mcu/st/stm32u5xx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git', '2e1d4cdb386e33391cb261dfff4fefa92e4aa35a'],
-    'hw/mcu/st/stm32wbxx_hal_driver'              : [ 'https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git', '2c5f06638be516c1b772f768456ba637f077bac8'],
-    'hw/mcu/ti'                                   : [ 'https://github.com/hathach/ti_driver.git',                       '143ed6cc20a7615d042b03b21e070197d473e6e5'],
-    'hw/mcu/wch/ch32v307'                         : [ 'https://github.com/openwch/ch32v307.git',                        '17761f5cf9dbbf2dcf665b7c04934188add20082'],
-    'lib/CMSIS_5'                                 : [ 'https://github.com/ARM-software/CMSIS_5.git',                    '20285262657d1b482d132d20d755c8c330d55c1f'],
-    #'lib/FreeRTOS-Kernel'                         : [ 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git',                '2a604f4a2818b8354b5e1a39e388eb5e16cfbc1f'],
-    #'lib/lwip'                                    : [ 'https://github.com/lwip-tcpip/lwip.git',                         '159e31b689577dbf69cf0683bbaffbd71fa5ee10'],
-    'lib/sct_neopixel'                            : [ 'https://github.com/gsteiert/sct_neopixel.git',                   'e73e04ca63495672d955f9268e003cffe168fcd8'],
-    #'tools/uf2'                                   : [ 'https://github.com/microsoft/uf2.git',                           '19615407727073e36d81bf239c52108ba92e7660'],
+    'hw/mcu/allwinner'                         : ['8e5e89e8e132c0fd90e72d5422e5d3d68232b756', 'https://github.com/hathach/allwinner_driver.git'               ],
+    'hw/mcu/bridgetek/ft9xx/ft90x-sdk'         : ['91060164afe239fcb394122e8bf9eb24d3194eb1', 'https://github.com/BRTSG-FOSS/ft90x-sdk.git'                   ],
+    'hw/mcu/broadcom'                          : ['08370086080759ed54ac1136d62d2ad24c6fa267', 'https://github.com/adafruit/broadcom-peripherals.git'          ],
+    'hw/mcu/gd/nuclei-sdk'                     : ['7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7', 'https://github.com/Nuclei-Software/nuclei-sdk.git'             ],
+    'hw/mcu/infineon/mtb-xmclib-cat3'          : ['daf5500d03cba23e68c2f241c30af79cd9d63880', 'https://github.com/Infineon/mtb-xmclib-cat3.git'               ],
+    'hw/mcu/microchip'                         : ['9e8b37e307d8404033bb881623a113931e1edf27', 'https://github.com/hathach/microchip_driver.git'               ],
+    'hw/mcu/mindmotion/mm32sdk'                : ['708a7152952ac595d24837069dcc0f7f59a4c30b', 'https://github.com/hathach/mm32sdk.git'                        ],
+    'hw/mcu/nordic/nrfx'                       : ['281cc2e178fd9a470d844b3afdea9eb322a0b0e8', 'https://github.com/NordicSemiconductor/nrfx.git'               ],
+    'hw/mcu/nuvoton'                           : ['2204191ec76283371419fbcec207da02e1bc22fa', 'https://github.com/majbthrd/nuc_driver.git'                    ],
+    'hw/mcu/nxp/lpcopen'                       : ['43c45c85405a5dd114fff0ea95cca62837740c13', 'https://github.com/hathach/nxp_lpcopen.git'                    ],
+    'hw/mcu/nxp/mcux-sdk'                      : ['ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294', 'https://github.com/NXPmicro/mcux-sdk.git'                      ],
+    'hw/mcu/nxp/nxp_sdk'                       : ['845c8fc49b6fb660f06a5c45225494eacb06f00c', 'https://github.com/hathach/nxp_sdk.git'                        ],
+    'hw/mcu/raspberry_pi/Pico-PIO-USB'         : ['9ff3f52fd3c1f81532bce8dd311aa8fc8d9b2665', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git'            ],
+    'hw/mcu/renesas/rx'                        : ['706b4e0cf485605c32351e2f90f5698267996023', 'https://github.com/kkitayam/rx_device.git'                     ],
+    'hw/mcu/silabs/cmsis-dfp-efm32gg12b'       : ['f1c31b7887669cb230b3ea63f9b56769078960bc', 'https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git'       ],
+    'hw/mcu/sony/cxd56/spresense-exported-sdk' : ['2ec2a1538362696118dc3fdf56f33dacaf8f4067', 'https://github.com/sonydevworld/spresense-exported-sdk.git'    ],
+    'hw/mcu/st/cmsis_device_f0'                : ['2fc25ee22264bc27034358be0bd400b893ef837e', 'https://github.com/STMicroelectronics/cmsis_device_f0.git'     ],
+    'hw/mcu/st/cmsis_device_f1'                : ['6601104a6397299b7304fd5bcd9a491f56cb23a6', 'https://github.com/STMicroelectronics/cmsis_device_f1.git'     ],
+    'hw/mcu/st/cmsis_device_f2'                : ['182fcb3681ce116816feb41b7764f1b019ce796f', 'https://github.com/STMicroelectronics/cmsis_device_f2.git'     ],
+    'hw/mcu/st/cmsis_device_f3'                : ['5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b', 'https://github.com/STMicroelectronics/cmsis_device_f3.git'     ],
+    'hw/mcu/st/cmsis_device_f4'                : ['2615e866fa48fe1ff1af9e31c348813f2b19e7ec', 'https://github.com/STMicroelectronics/cmsis_device_f4.git'     ],
+    'hw/mcu/st/cmsis_device_f7'                : ['fc676ef1ad177eb874eaa06444d3d75395fc51f4', 'https://github.com/STMicroelectronics/cmsis_device_f7.git'     ],
+    'hw/mcu/st/cmsis_device_g0'                : ['08258b28ee95f50cb9624d152a1cbf084be1f9a5', 'https://github.com/STMicroelectronics/cmsis_device_g0.git'     ],
+    'hw/mcu/st/cmsis_device_g4'                : ['ce822adb1dc552b3aedd13621edbc7fdae124878', 'https://github.com/STMicroelectronics/cmsis_device_g4.git'     ],
+    'hw/mcu/st/cmsis_device_h7'                : ['60dc2c913203dc8629dc233d4384dcc41c91e77f', 'https://github.com/STMicroelectronics/cmsis_device_h7.git'     ],
+    'hw/mcu/st/cmsis_device_l0'                : ['06748ca1f93827befdb8b794402320d94d02004f', 'https://github.com/STMicroelectronics/cmsis_device_l0.git'     ],
+    'hw/mcu/st/cmsis_device_l1'                : ['7f16ec0a1c4c063f84160b4cc6bf88ad554a823e', 'https://github.com/STMicroelectronics/cmsis_device_l1.git'     ],
+    'hw/mcu/st/cmsis_device_l4'                : ['6ca7312fa6a5a460b5a5a63d66da527fdd8359a6', 'https://github.com/STMicroelectronics/cmsis_device_l4.git'     ],
+    'hw/mcu/st/cmsis_device_l5'                : ['d922865fc0326a102c26211c44b8e42f52c1e53d', 'https://github.com/STMicroelectronics/cmsis_device_l5.git'     ],
+    'hw/mcu/st/cmsis_device_u5'                : ['bc00f3c9d8a4e25220f84c26d414902cc6bdf566', 'https://github.com/STMicroelectronics/cmsis_device_u5.git'     ],
+    'hw/mcu/st/cmsis_device_wb'                : ['9c5d1920dd9fabbe2548e10561d63db829bb744f', 'https://github.com/STMicroelectronics/cmsis_device_wb.git'     ],
+    'hw/mcu/st/stm32f0xx_hal_driver'           : ['0e95cd88657030f640a11e690a8a5186c7712ea5', 'https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git'],
+    'hw/mcu/st/stm32f1xx_hal_driver'           : ['1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29', 'https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git'],
+    'hw/mcu/st/stm32f2xx_hal_driver'           : ['c75ace9b908a9aca631193ebf2466963b8ea33d0', 'https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git'],
+    'hw/mcu/st/stm32f3xx_hal_driver'           : ['1761b6207318ede021706e75aae78f452d72b6fa', 'https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git'],
+    'hw/mcu/st/stm32f4xx_hal_driver'           : ['04e99fbdabd00ab8f370f377c66b0a4570365b58', 'https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git'],
+    'hw/mcu/st/stm32f7xx_hal_driver'           : ['f7ffdf6bf72110e58b42c632b0a051df5997e4ee', 'https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git'],
+    'hw/mcu/st/stm32g0xx_hal_driver'           : ['5b53e6cee664a82b16c86491aa0060e2110c00cb', 'https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git'],
+    'hw/mcu/st/stm32g4xx_hal_driver'           : ['8b4518417706d42eef5c14e56a650005abf478a8', 'https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git'],
+    'hw/mcu/st/stm32h7xx_hal_driver'           : ['d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04', 'https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git'],
+    'hw/mcu/st/stm32l0xx_hal_driver'           : ['fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b', 'https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git'],
+    'hw/mcu/st/stm32l1xx_hal_driver'           : ['44efc446fa69ed8344e7fd966e68ed11043b35d9', 'https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git'],
+    'hw/mcu/st/stm32l4xx_hal_driver'           : ['aee3d5bf283ae5df87532b781bdd01b7caf256fc', 'https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git'],
+    'hw/mcu/st/stm32l5xx_hal_driver'           : ['675c32a75df37f39d50d61f51cb0dcf53f07e1cb', 'https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git'],
+    'hw/mcu/st/stm32u5xx_hal_driver'           : ['2e1d4cdb386e33391cb261dfff4fefa92e4aa35a', 'https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git'],
+    'hw/mcu/st/stm32wbxx_hal_driver'           : ['2c5f06638be516c1b772f768456ba637f077bac8', 'https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git'],
+    'hw/mcu/ti'                                : ['143ed6cc20a7615d042b03b21e070197d473e6e5', 'https://github.com/hathach/ti_driver.git'                      ],
+    'hw/mcu/wch/ch32v307'                      : ['17761f5cf9dbbf2dcf665b7c04934188add20082', 'https://github.com/openwch/ch32v307.git'                       ],
+    'lib/CMSIS_5'                              : ['20285262657d1b482d132d20d755c8c330d55c1f', 'https://github.com/ARM-software/CMSIS_5.git'                   ],
+    'lib/FreeRTOS-Kernel'                      : ['2a604f4a2818b8354b5e1a39e388eb5e16cfbc1f', 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git'               ],
+    'lib/lwip'                                 : ['159e31b689577dbf69cf0683bbaffbd71fa5ee10', 'https://github.com/lwip-tcpip/lwip.git'                        ],
+    'lib/sct_neopixel'                         : ['e73e04ca63495672d955f9268e003cffe168fcd8', 'https://github.com/gsteiert/sct_neopixel.git'                  ],
+    'tools/uf2'                                : ['19615407727073e36d81bf239c52108ba92e7660', 'https://github.com/microsoft/uf2.git'                          ],
 }
 
 # TOP is tinyusb root dir
@@ -68,8 +68,8 @@ def get_a_dep(d):
     if d not in deps_list.keys():
         print('{} is not found in dependency list')
         return 1
-    url = deps_list[d][0]
-    commit = deps_list[d][1]
+    commit = deps_list[d][0]
+    url = deps_list[d][1]
     print('cloning {} with {}'.format(d, url))
 
     p = Path(TOP / d)
@@ -96,6 +96,5 @@ if __name__ == "__main__":
     status = 0
     all_deps = sys.argv[1:]
     with Pool() as pool:
-        result = pool.map(get_a_dep, all_deps)
-        status = sum(result)
+        status = sum(pool.map(get_a_dep, all_deps))
     sys.exit(status)

From e045995407e060800877d6a6421f83a413f9e084 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 11 Mar 2023 08:54:51 +0700
Subject: [PATCH 1532/2085] minor update get_deps

---
 tools/get_deps.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index 5c6bef389..3aa95ece5 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -79,8 +79,8 @@ def get_a_dep(d):
     # Init git deps if not existed
     if not p.exists():
         p.mkdir(parents=True)
-        subprocess.run("{} init".format(git_cmd), shell=True)
-        subprocess.run("{} remote add origin {}".format(git_cmd, url), shell=True)
+        subprocess.run("{} init".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        subprocess.run("{} remote add origin {}".format(git_cmd, url), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
 
     # Check if commit is already fetched
     result = subprocess.run("{} rev-parse HEAD".format(git_cmd, commit), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
@@ -88,7 +88,7 @@ def get_a_dep(d):
 
     if commit != head:
         subprocess.run("{} fetch --depth 1 origin {}".format(git_cmd, commit), shell=True)
-        subprocess.run("{} checkout FETCH_HEAD".format(git_cmd), shell=True)
+        subprocess.run("{} checkout FETCH_HEAD".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
 
     return 0
 

From 0a7c08d16e10b9a252c7daeb3fe9b3abdd6ff225 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 12 Mar 2023 16:01:24 +0700
Subject: [PATCH 1533/2085] minor format

---
 src/portable/renesas/link/dcd_link.c | 57 +++++++++++++++++----
 src/portable/renesas/link/hcd_link.c | 76 ++++++++++++++++++++--------
 src/portable/renesas/link/link_rx.h  |  6 +--
 3 files changed, 104 insertions(+), 35 deletions(-)

diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/link/dcd_link.c
index dcbd68b8d..ce29769e0 100644
--- a/src/portable/renesas/link/dcd_link.c
+++ b/src/portable/renesas/link/dcd_link.c
@@ -31,10 +31,8 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
-                        CFG_TUSB_MCU == OPT_MCU_RX65X || \
-                        CFG_TUSB_MCU == OPT_MCU_RX72N || \
-                        CFG_TUSB_MCU == OPT_MCU_RAXXX)
+#if CFG_TUD_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \
+                        TU_CHECK_MCU(OPT_MCU_RAXXX))
 
 #include "device/dcd.h"
 #include "link_type.h"
@@ -250,8 +248,9 @@ static bool pipe0_xfer_in(void)
       pipe->buf = (uint8_t*)buf + len;
     }
   }
-  if (len < mps)
+  if (len < mps) {
     LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
+  }
   pipe->remaining = rem - len;
   return false;
 }
@@ -273,8 +272,9 @@ static bool pipe0_xfer_out(void)
       pipe->buf = (uint8_t*)buf + len;
     }
   }
-  if (len < mps)
+  if (len < mps) {
     LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
+  }
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
@@ -306,10 +306,11 @@ static bool pipe_xfer_in(unsigned num)
       pipe->buf = (uint8_t*)buf + len;
     }
   }
-  if (len < mps)
+  if (len < mps) {
     LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
+  }
   LINK_REG->D0FIFOSEL = 0;
-  while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   return false;
 }
@@ -333,10 +334,11 @@ static bool pipe_xfer_out(unsigned num)
       pipe->buf = (uint8_t*)buf + len;
     }
   }
-  if (len < mps)
+  if (len < mps) {
     LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
+  }
   LINK_REG->D0FIFOSEL = 0;
-  while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
@@ -377,7 +379,7 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
   /* configure fifo direction and access unit settings */
   if (ep_addr) { /* IN, 2 bytes */
     LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
-             (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
+                         (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
     while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
   } else { /* OUT, a byte */
     LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
@@ -541,10 +543,43 @@ static void process_set_address(uint8_t rhport)
 /*------------------------------------------------------------------*/
 /* Device API
  *------------------------------------------------------------------*/
+
+#if 0 // previously present in the rx driver before generalization
+static uint32_t disable_interrupt(void)
+{
+  uint32_t pswi;
+#if defined(__CCRX__)
+  pswi = get_psw() & 0x010000;
+  clrpsw_i();
+#else
+  pswi = __builtin_rx_mvfc(0) & 0x010000;
+  __builtin_rx_clrpsw('I');
+#endif
+  return pswi;
+}
+
+static void enable_interrupt(uint32_t pswi)
+{
+#if defined(__CCRX__)
+  set_psw(get_psw() | pswi);
+#else
+  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
+#endif
+}
+#endif
+
 void dcd_init(uint8_t rhport)
 {
   (void)rhport;
 
+#if 0 // previously present in the rx driver before generalization
+  uint32_t pswi = disable_interrupt();
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(USB0) = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+  enable_interrupt(pswi);
+#endif
+
   LINK_REG->SYSCFG_b.SCKE = 1;
   while (!LINK_REG->SYSCFG_b.SCKE) ;
   LINK_REG->SYSCFG_b.DRPD = 0;
diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/link/hcd_link.c
index f1ea2b821..b16544c2f 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/link/hcd_link.c
@@ -27,10 +27,8 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
-                        CFG_TUSB_MCU == OPT_MCU_RX65X || \
-                        CFG_TUSB_MCU == OPT_MCU_RX72N || \
-                        CFG_TUSB_MCU == OPT_MCU_RAXXX)
+#if CFG_TUH_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \
+                        TU_CHECK_MCU(OPT_MCU_RAXXX))
 
 #include "host/hcd.h"
 #include "link_type.h"
@@ -217,8 +215,9 @@ static bool pipe0_xfer_in(void)
     pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps)
+  if (len < mps) {
     LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
+  }
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
@@ -243,8 +242,9 @@ static bool pipe0_xfer_out(void)
     pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps)
+  if (len < mps) {
     LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
+  }
   pipe->remaining = rem - len;
   return false;
 }
@@ -264,8 +264,9 @@ static bool pipe_xfer_in(unsigned num)
     pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps)
+  if (len < mps) {
     LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
+  }
   LINK_REG->D0FIFOSEL = 0;
   while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
@@ -314,7 +315,7 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
     while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
   } else { /* OUT, 2 bytes */
     LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
-             (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
+                         (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
     while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
   }
 
@@ -363,7 +364,7 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u
       pipe_wait_for_ready(num);
       LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
       LINK_REG->D0FIFOSEL = 0;
-      while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
+      while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
     }
   } else {
     volatile uint16_t     *ctr = get_pipectr(num);
@@ -447,10 +448,43 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
 /*------------------------------------------------------------------*/
 /* Host API
  *------------------------------------------------------------------*/
+
+#if 0 // previously present in the rx driver before generalization
+static uint32_t disable_interrupt(void)
+{
+  uint32_t pswi;
+#if defined(__CCRX__)
+  pswi = get_psw() & 0x010000;
+  clrpsw_i();
+#else
+  pswi = __builtin_rx_mvfc(0) & 0x010000;
+  __builtin_rx_clrpsw('I');
+#endif
+  return pswi;
+}
+
+static void enable_interrupt(uint32_t pswi)
+{
+#if defined(__CCRX__)
+  set_psw(get_psw() | pswi);
+#else
+  __builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
+#endif
+}
+#endif
+
 bool hcd_init(uint8_t rhport)
 {
   (void)rhport;
 
+#if 0 // previously present in the rx driver before generalization
+  uint32_t pswi = disable_interrupt();
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
+  MSTP(USB0) = 0;
+  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
+  enable_interrupt(pswi);
+#endif
+
   LINK_REG->SYSCFG_b.SCKE = 1;
   while (!LINK_REG->SYSCFG_b.SCKE) ;
   LINK_REG->SYSCFG_b.DPRPU = 0;
@@ -470,7 +504,7 @@ bool hcd_init(uint8_t rhport)
   LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
 
   /* Setup default control pipe */
-  LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk;
+  LINK_REG->DCPCFG  = LINK_REG_PIPECFG_SHTNAK_Msk;
   LINK_REG->DCPMAXP = 64;
   LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk;
   LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk;
@@ -515,8 +549,9 @@ void hcd_port_reset(uint8_t rhport)
   while (LINK_REG->DCPCTR_b.PBUSY) ;
   hcd_int_disable(rhport);
   LINK_REG->DVSTCTR0_b.UACT = 0;
-  if (LINK_REG->DCPCTR_b.SUREQ)
+  if (LINK_REG->DCPCTR_b.SUREQ) {
     LINK_REG->DCPCTR_b.SUREQCLR = 1;
+  }
   hcd_int_enable(rhport);
   /* Reset should be asserted 10-20ms. */
   LINK_REG->DVSTCTR0_b.USBRST = 1;
@@ -580,10 +615,10 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 
   LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
 
-  _hcd.pipe[0].buf = NULL;
-  _hcd.pipe[0].length = 8;
+  _hcd.pipe[0].buf       = NULL;
+  _hcd.pipe[0].length    = 8;
   _hcd.pipe[0].remaining = 0;
-  _hcd.pipe[0].dev = dev_addr;
+  _hcd.pipe[0].dev       = dev_addr;
 
   while (LINK_REG->DCPCTR_b.PBUSY) ;
   LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
@@ -593,8 +628,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
 
   uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
-  LINK_REG->USBREQ = tu_htole16(p[0]);
-  LINK_REG->USBVAL = p[1];
+  LINK_REG->USBREQ  = tu_htole16(p[0]);
+  LINK_REG->USBVAL  = p[1];
   LINK_REG->USBINDX = p[2];
   LINK_REG->USBLENG = p[3];
 
@@ -717,12 +752,10 @@ void hcd_int_handler(uint8_t rhport)
   if (is1 & LINK_REG_INTSTS1_SACK_Msk) {
     /* Set DATA1 in advance for the next transfer. */
     LINK_REG->DCPCTR_b.SQSET = 1;
-    hcd_event_xfer_complete(
-      LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
+    hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
   }
   if (is1 & LINK_REG_INTSTS1_SIGN_Msk) {
-    hcd_event_xfer_complete(
-      LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
+    hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
   }
   if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) {
     LINK_REG->DVSTCTR0_b.UACT = 1;
@@ -732,8 +765,9 @@ void hcd_int_handler(uint8_t rhport)
   }
   if (is1 & LINK_REG_INTSTS1_DTCH_Msk) {
     LINK_REG->DVSTCTR0_b.UACT = 0;
-    if (LINK_REG->DCPCTR_b.SUREQ)
+    if (LINK_REG->DCPCTR_b.SUREQ) {
       LINK_REG->DCPCTR_b.SUREQCLR = 1;
+    }
     LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk;
     hcd_event_device_remove(rhport, true);
   }
diff --git a/src/portable/renesas/link/link_rx.h b/src/portable/renesas/link/link_rx.h
index 62f2911c2..9e31c5b46 100644
--- a/src/portable/renesas/link/link_rx.h
+++ b/src/portable/renesas/link/link_rx.h
@@ -39,7 +39,7 @@ extern "C" {
 
 #define LINK_REG_BASE (0x000A0000)
 
-static inline void link_int_enable(uint8_t rhport)
+TU_ATTR_ALWAYS_INLINE static inline void link_int_enable(uint8_t rhport)
 {
   (void) rhport;
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
@@ -49,7 +49,7 @@ static inline void link_int_enable(uint8_t rhport)
 #endif
 }
 
-static inline void link_int_disable(uint8_t rhport)
+TU_ATTR_ALWAYS_INLINE static inline void link_int_disable(uint8_t rhport)
 {
   (void) rhport;
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
@@ -60,7 +60,7 @@ static inline void link_int_disable(uint8_t rhport)
 }
 
 // MCU specific PHY init
-static inline void link_phy_init(void)
+TU_ATTR_ALWAYS_INLINE static inline void link_phy_init(void)
 {
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
   IR(PERIB, INTB185) = 0;

From f8a21fff171aa272360c89dab5faca4f688a656a Mon Sep 17 00:00:00 2001
From: Hubert Denkmair <xor@xor.wtf>
Date: Sun, 12 Mar 2023 15:51:07 +0100
Subject: [PATCH 1534/2085] dcd_write_packet_memory: use volatile modifier for
 destination pointer

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 21ae8e6e8..e2e1cf484 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -1228,8 +1228,8 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
 {
   // FIXME original function uses byte-access to source memory (to support non-aligned buffers)
-  const uint32_t* src32 = (uint32_t*)(src);
-  uint32_t* dst32 = (uint32_t*)(USB_PMAADDR + dst);
+  const uint32_t* src32 = (const uint32_t*)(src);
+  volatile uint32_t* dst32 = (volatile uint32_t*)(USB_PMAADDR + dst);
   for (unsigned n=wNBytes/4; n>0; --n) {
     *dst32++ = *src32++;
   }

From f6774d561148c7c2f41b66234d080e9dfd514551 Mon Sep 17 00:00:00 2001
From: James Smith <jmsmith86@gmail.com>
Date: Tue, 7 Feb 2023 20:46:00 -0700
Subject: [PATCH 1535/2085] Implemented tuh_hid_send_report

---
 src/class/hid/hid_host.c | 48 +++++++++++++++++++++++++++++++++++++---
 src/class/hid/hid_host.h |  4 ++--
 2 files changed, 47 insertions(+), 5 deletions(-)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 42b5e2f4e..22569194f 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -274,7 +274,49 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance)
 //  return !usbh_edpt_busy(dev_addr, hid_itf->ep_in);
 //}
 
-//void tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len);
+bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len)
+{
+  TU_LOG2("HID Send Report %d\r\n", report_id);
+
+  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+
+  if (hid_itf->ep_out == 0)
+  {
+    // This HID does not have an out endpoint (other than control)
+    return false;
+  }
+  else if (len > CFG_TUH_HID_EPOUT_BUFSIZE
+           || (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1)))
+  {
+    // ep_out buffer is not large enough to hold contents
+    return false;
+  }
+
+  // claim endpoint
+  TU_VERIFY( usbh_edpt_claim(dev_addr, hid_itf->ep_out) );
+
+  if (report_id == 0)
+  {
+    // No report ID in transmission
+    memcpy(&hid_itf->epout_buf[0], report, len);
+  }
+  else
+  {
+    hid_itf->epout_buf[0] = report_id;
+    memcpy(&hid_itf->epout_buf[1], report, len);
+    ++len; // 1 more byte for report_id
+  }
+
+  TU_LOG3_MEM(hid_itf->epout_buf, len, 2);
+
+  if ( !usbh_edpt_xfer(dev_addr, hid_itf->ep_out, hid_itf->epout_buf, len) )
+  {
+    usbh_edpt_release(dev_addr, hid_itf->ep_out);
+    return false;
+  }
+
+  return true;
+}
 
 //--------------------------------------------------------------------+
 // USBH API
@@ -349,7 +391,7 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   hidh_device_t* hid_dev = get_dev(dev_addr);
   TU_ASSERT(hid_dev->inst_count < CFG_TUH_HID, 0);
 
-  hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count);  
+  hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count);
 
   //------------- Endpoint Descriptors -------------//
   p_desc = tu_desc_next(p_desc);
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index ffc601d77..e5f159ca8 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -106,7 +106,7 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance);
 
 // Send report using interrupt endpoint
 // If report_id > 0 (composite), it will be sent as 1st byte, then report contents. Otherwise only report content is sent.
-//void tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len);
+bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len);
 
 //--------------------------------------------------------------------+
 // Callbacks (Weak is optional)

From 296ce528fcc3632205cb7f6f5a2f386169fdbf36 Mon Sep 17 00:00:00 2001
From: James Smith <jmsmith86@gmail.com>
Date: Thu, 9 Feb 2023 19:42:36 -0700
Subject: [PATCH 1536/2085] Updated host hid_controller example to demo
 tuh_hid_send_report

---
 examples/host/hid_controller/src/hid_app.c | 87 +++++++++++++++++++---
 src/class/hid/hid_host.c                   |  2 +-
 src/class/hid/hid_host.h                   |  2 +-
 3 files changed, 80 insertions(+), 11 deletions(-)

diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index 75c91400e..0444d6eb5 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -91,9 +91,8 @@ typedef struct TU_ATTR_PACKED
     uint8_t counter : 6; // +1 each report
   };
 
-  // comment out since not used by this example
-  // uint8_t l2_trigger; // 0 released, 0xff fully pressed
-  // uint8_t r2_trigger; // as above
+  uint8_t l2_trigger; // 0 released, 0xff fully pressed
+  uint8_t r2_trigger; // as above
 
   //  uint16_t timestamp;
   //  uint8_t  battery;
@@ -105,15 +104,54 @@ typedef struct TU_ATTR_PACKED
 
 } sony_ds4_report_t;
 
+typedef struct TU_ATTR_PACKED {
+  // First 16 bits set what data is pertinent in this structure (1 = set; 0 = not set)
+	uint8_t set_rumble : 1;
+  uint8_t set_led : 1;
+  uint8_t set_led_blink : 1;
+  uint8_t set_ext_write : 1;
+  uint8_t set_left_volume : 1;
+  uint8_t set_right_volume : 1;
+  uint8_t set_mic_volume : 1;
+  uint8_t set_speaker_volume : 1;
+  uint8_t set_flags2;
+
+	uint8_t reserved;
+
+	uint8_t motor_right;
+	uint8_t motor_left;
+
+	uint8_t lightbar_red;
+	uint8_t lightbar_green;
+	uint8_t lightbar_blue;
+	uint8_t lightbar_blink_on;
+	uint8_t lightbar_blink_off;
+
+  uint8_t ext_data[8];
+
+  uint8_t volume_left;
+  uint8_t volume_right;
+  uint8_t volume_mic;
+  uint8_t volume_speaker;
+
+  uint8_t other[9];
+} sony_ds4_output_report_t;
+
+static bool ds4_mounted = false;
+static uint8_t ds4_dev_addr = 0;
+static uint8_t ds4_instance = 0;
+static uint8_t motor_left = 0;
+static uint8_t motor_right = 0;
+
 // check if device is Sony DualShock 4
 static inline bool is_sony_ds4(uint8_t dev_addr)
 {
   uint16_t vid, pid;
   tuh_vid_pid_get(dev_addr, &vid, &pid);
 
-  return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4 
-           || (vid == 0x0f0d && pid == 0x005e)                 // Hori FC4 
-           || (vid == 0x0f0d && pid == 0x00ee)                 // Hori PS4 Mini (PS4-099U) 
+  return ( (vid == 0x054c && (pid == 0x09cc || pid == 0x05c4)) // Sony DualShock4
+           || (vid == 0x0f0d && pid == 0x005e)                 // Hori FC4
+           || (vid == 0x0f0d && pid == 0x00ee)                 // Hori PS4 Mini (PS4-099U)
            || (vid == 0x1f4f && pid == 0x1002)                 // ASW GG xrd controller
          );
 }
@@ -124,7 +162,22 @@ static inline bool is_sony_ds4(uint8_t dev_addr)
 
 void hid_app_task(void)
 {
-  // nothing to do
+  if (ds4_mounted)
+  {
+    const uint32_t interval_ms = 200;
+    static uint32_t start_ms = 0;
+
+    if ( board_millis() - start_ms >= interval_ms)
+    {
+      start_ms += interval_ms;
+
+      sony_ds4_output_report_t output_report = {0};
+      output_report.set_rumble = 1;
+      output_report.motor_left = motor_left;
+      output_report.motor_right = motor_right;
+      tuh_hid_send_report(ds4_dev_addr, ds4_instance, 5, &output_report, sizeof(output_report));
+    }
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -149,6 +202,14 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
   // Sony DualShock 4 [CUH-ZCT2x]
   if ( is_sony_ds4(dev_addr) )
   {
+    if (!ds4_mounted)
+    {
+      ds4_dev_addr = dev_addr;
+      ds4_instance = instance;
+      motor_left = 0;
+      motor_right = 0;
+      ds4_mounted = true;
+    }
     // request to receive report
     // tuh_hid_report_received_cb() will be invoked when report is available
     if ( !tuh_hid_receive_report(dev_addr, instance) )
@@ -162,6 +223,10 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_re
 void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance)
 {
   printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+  if (ds4_mounted && ds4_dev_addr == dev_addr && ds4_instance == instance)
+  {
+    ds4_mounted = false;
+  }
 }
 
 // check if different than 2
@@ -179,8 +244,8 @@ bool diff_report(sony_ds4_report_t const* rpt1, sony_ds4_report_t const* rpt2)
   result = diff_than_2(rpt1->x, rpt2->x) || diff_than_2(rpt1->y , rpt2->y ) ||
            diff_than_2(rpt1->z, rpt2->z) || diff_than_2(rpt1->rz, rpt2->rz);
 
-  // check the reset with mem compare
-  result |= memcmp(&rpt1->rz + 1, &rpt2->rz + 1, sizeof(sony_ds4_report_t)-4);
+  // check the rest with mem compare
+  result |= memcmp(&rpt1->rz + 1, &rpt2->rz + 1, sizeof(sony_ds4_report_t)-6);
 
   return result;
 }
@@ -234,6 +299,10 @@ void process_sony_ds4(uint8_t const* report, uint16_t len)
       printf("\r\n");
     }
 
+    // The left and right triggers control the intensity of the left and right rumble motors
+    motor_left = ds4_report.l2_trigger;
+    motor_right = ds4_report.r2_trigger;
+
     prev_report = ds4_report;
   }
 }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 22569194f..e5fc86267 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -274,7 +274,7 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance)
 //  return !usbh_edpt_busy(dev_addr, hid_itf->ep_in);
 //}
 
-bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len)
+bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, const void* report, uint16_t len)
 {
   TU_LOG2("HID Send Report %d\r\n", report_id);
 
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index e5f159ca8..c152e527a 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -106,7 +106,7 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance);
 
 // Send report using interrupt endpoint
 // If report_id > 0 (composite), it will be sent as 1st byte, then report contents. Otherwise only report content is sent.
-bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t const* report, uint16_t len);
+bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, const void* report, uint16_t len);
 
 //--------------------------------------------------------------------+
 // Callbacks (Weak is optional)

From 43770802f9164f8bc3973719c25ba46ff4ba23ca Mon Sep 17 00:00:00 2001
From: James Smith <jmsmith86@gmail.com>
Date: Thu, 9 Feb 2023 19:52:42 -0700
Subject: [PATCH 1537/2085] Removed tabs from host hid_controller example

---
 examples/host/hid_controller/src/hid_app.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index 0444d6eb5..114768ab7 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -106,7 +106,7 @@ typedef struct TU_ATTR_PACKED
 
 typedef struct TU_ATTR_PACKED {
   // First 16 bits set what data is pertinent in this structure (1 = set; 0 = not set)
-	uint8_t set_rumble : 1;
+  uint8_t set_rumble : 1;
   uint8_t set_led : 1;
   uint8_t set_led_blink : 1;
   uint8_t set_ext_write : 1;
@@ -116,16 +116,16 @@ typedef struct TU_ATTR_PACKED {
   uint8_t set_speaker_volume : 1;
   uint8_t set_flags2;
 
-	uint8_t reserved;
+  uint8_t reserved;
 
-	uint8_t motor_right;
-	uint8_t motor_left;
+  uint8_t motor_right;
+  uint8_t motor_left;
 
-	uint8_t lightbar_red;
-	uint8_t lightbar_green;
-	uint8_t lightbar_blue;
-	uint8_t lightbar_blink_on;
-	uint8_t lightbar_blink_off;
+  uint8_t lightbar_red;
+  uint8_t lightbar_green;
+  uint8_t lightbar_blue;
+  uint8_t lightbar_blink_on;
+  uint8_t lightbar_blink_off;
 
   uint8_t ext_data[8];
 

From 9247131b1f6476c433ceb47d4746c9bc5baf8b65 Mon Sep 17 00:00:00 2001
From: James Smith <jmsmith86@gmail.com>
Date: Thu, 9 Feb 2023 21:21:57 -0700
Subject: [PATCH 1538/2085] Avoid spamming out endpoint on connect

---
 examples/host/hid_controller/src/hid_app.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index 114768ab7..76de97b41 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -167,9 +167,10 @@ void hid_app_task(void)
     const uint32_t interval_ms = 200;
     static uint32_t start_ms = 0;
 
-    if ( board_millis() - start_ms >= interval_ms)
+    uint32_t current_time_ms = board_millis();
+    if ( current_time_ms - start_ms >= interval_ms)
     {
-      start_ms += interval_ms;
+      start_ms = current_time_ms;
 
       sony_ds4_output_report_t output_report = {0};
       output_report.set_rumble = 1;

From d31aac453eaa0b56a998c3cca5d2efd4c55209af Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Mon, 13 Mar 2023 15:22:00 -0700
Subject: [PATCH 1539/2085] Flush the dcd data on reset

---
 src/portable/chipidea/ci_hs/dcd_ci_hs.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 32c2fc029..91d5524b6 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -48,6 +48,8 @@
 
 #define CI_HS_REG(_port)      ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
 
+// Clean means to push any cached changes to RAM and invalidate "removes" the
+// entry from the cache.
 #if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
   #define CleanInvalidateDCache_by_Addr   SCB_CleanInvalidateDCache_by_Addr
 #else
@@ -199,6 +201,8 @@ static void bus_reset(uint8_t rhport)
   _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID;
 
   _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
+
+  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
 }
 
 void dcd_init(uint8_t rhport)

From d9a9dc5ac0a9679403a75dbe3a32c4d4678998e6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Mar 2023 14:39:57 +0700
Subject: [PATCH 1540/2085] fix PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY
 not defined in old pico-sdk

---
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 37dec1cbf..4af8c2d71 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -385,6 +385,11 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
 /* Controller API
  *------------------------------------------------------------------*/
 
+// older SDK
+#ifndef PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY
+#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff
+#endif
+
 void dcd_init (uint8_t rhport)
 {
   assert(rhport == 0);

From ffa56a1beb724397e434e5e74e2a7b1d4583acd8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 15 Mar 2023 17:40:02 +0700
Subject: [PATCH 1541/2085] add pre-commit yaml

---
 .pre-commit-config.yaml | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 .pre-commit-config.yaml

diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
new file mode 100644
index 000000000..5a61f5282
--- /dev/null
+++ b/.pre-commit-config.yaml
@@ -0,0 +1,20 @@
+# SPDX-FileCopyrightText: 2020 Diego Elio Pettenò
+#
+# SPDX-License-Identifier: Unlicense
+
+repos:
+-   repo: local
+    hooks:
+    -   id: codespell
+        name: codespell
+        entry: codespell
+        types_or: [c, header]
+        language: system
+
+    -   id: unit-test
+        name: unit-test
+        files: ^(src/|test/unit-test/)
+        entry: sh -c "cd test/unit-test && ceedling test:all"
+        pass_filenames: false
+        types_or: [c, header]
+        language: system

From fabe86362b0cf914a80f27023775291ffabe9bbc Mon Sep 17 00:00:00 2001
From: tyustli <1225613647@qq.com>
Date: Thu, 16 Mar 2023 08:28:19 +0800
Subject: [PATCH 1542/2085] fix HAL_Delay no effect bug on st platform

---
 hw/bsp/stm32f0/family.c                  | 1 +
 hw/bsp/stm32f1/family.c                  | 1 +
 hw/bsp/stm32f207nucleo/stm32f207nucleo.c | 1 +
 hw/bsp/stm32f303disco/stm32f303disco.c   | 1 +
 hw/bsp/stm32f4/family.c                  | 1 +
 hw/bsp/stm32f7/family.c                  | 1 +
 hw/bsp/stm32g4/family.c                  | 1 +
 hw/bsp/stm32h7/family.c                  | 1 +
 hw/bsp/stm32l0/family.c                  | 1 +
 hw/bsp/stm32l0538disco/stm32l0538disco.c | 1 +
 hw/bsp/stm32l4/family.c                  | 1 +
 hw/bsp/stm32u5/family.c                  | 1 +
 hw/bsp/stm32wb/family.c                  | 1 +
 13 files changed, 13 insertions(+)

diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index 0765f361d..884208fb1 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -143,6 +143,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index 61b40badd..6f0471096 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -129,6 +129,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c b/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
index 619c90d68..d77643661 100644
--- a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
+++ b/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
@@ -191,6 +191,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32f303disco/stm32f303disco.c b/hw/bsp/stm32f303disco/stm32f303disco.c
index 33552bc07..940c49d26 100644
--- a/hw/bsp/stm32f303disco/stm32f303disco.c
+++ b/hw/bsp/stm32f303disco/stm32f303disco.c
@@ -193,6 +193,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index 674058f50..93ab5bb35 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -180,6 +180,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index 536eb0554..88cba2c7d 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -293,6 +293,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index 32c46b7d8..f3ba54576 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -167,6 +167,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 28a2568fa..65ffc8ef4 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -251,6 +251,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler(void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c
index 80a7c7435..dcd71a513 100644
--- a/hw/bsp/stm32l0/family.c
+++ b/hw/bsp/stm32l0/family.c
@@ -141,6 +141,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32l0538disco/stm32l0538disco.c b/hw/bsp/stm32l0538disco/stm32l0538disco.c
index f0f1d028b..f4c38d150 100644
--- a/hw/bsp/stm32l0538disco/stm32l0538disco.c
+++ b/hw/bsp/stm32l0538disco/stm32l0538disco.c
@@ -183,6 +183,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c
index 19b84c086..d661613af 100644
--- a/hw/bsp/stm32l4/family.c
+++ b/hw/bsp/stm32l4/family.c
@@ -204,6 +204,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index 9bc94cfa3..ee8a5d7ff 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -179,6 +179,7 @@ int board_uart_write(void const *buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler(void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 
diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c
index 9f1f46f4d..525d637ea 100644
--- a/hw/bsp/stm32wb/family.c
+++ b/hw/bsp/stm32wb/family.c
@@ -169,6 +169,7 @@ int board_uart_write(void const * buf, int len)
 volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
+  HAL_IncTick();
   system_ticks++;
 }
 

From 1117cf5729d5896d960285e3d522064c63e2a2cc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 16 Mar 2023 10:05:46 +0700
Subject: [PATCH 1543/2085] update pre-commit yaml

---
 .pre-commit-config.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index 5a61f5282..865307896 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -3,6 +3,13 @@
 # SPDX-License-Identifier: Unlicense
 
 repos:
+-   repo: https://github.com/pre-commit/pre-commit-hooks
+    rev: v4.0.1
+    hooks:
+    - id: check-yaml
+    - id: trailing-whitespace
+    - id: end-of-file-fixer
+
 -   repo: local
     hooks:
     -   id: codespell

From bc2127b3305f5a6e689c1a3264fdee06928cd60e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 16 Mar 2023 11:03:08 +0700
Subject: [PATCH 1544/2085] rename file link to rusb2

---
 .codespell/exclude-file.txt                               | 4 ----
 .codespell/ignore-words.txt                               | 1 +
 hw/bsp/ra/family.mk                                       | 4 ++--
 hw/bsp/rx/family.mk                                       | 4 ++--
 .../renesas/{link/dcd_link.c => rusb2/dcd_rusb2.c}        | 8 ++++----
 .../renesas/{link/hcd_link.c => rusb2/hcd_rusb2.c}        | 8 ++++----
 src/portable/renesas/{link/link_ra.h => rusb2/rusb2_ra.h} | 2 --
 src/portable/renesas/{link/link_rx.h => rusb2/rusb2_rx.h} | 2 --
 .../renesas/{link/link_type.h => rusb2/rusb2_type.h}      | 0
 9 files changed, 13 insertions(+), 20 deletions(-)
 rename src/portable/renesas/{link/dcd_link.c => rusb2/dcd_rusb2.c} (99%)
 rename src/portable/renesas/{link/hcd_link.c => rusb2/hcd_rusb2.c} (99%)
 rename src/portable/renesas/{link/link_ra.h => rusb2/rusb2_ra.h} (98%)
 rename src/portable/renesas/{link/link_rx.h => rusb2/rusb2_rx.h} (98%)
 rename src/portable/renesas/{link/link_type.h => rusb2/rusb2_type.h} (100%)

diff --git a/.codespell/exclude-file.txt b/.codespell/exclude-file.txt
index 660d2e07e..e69de29bb 100644
--- a/.codespell/exclude-file.txt
+++ b/.codespell/exclude-file.txt
@@ -1,4 +0,0 @@
-  return LINK_REG->INTSTS1_b.ATTCH ? true : false;
-      volatile uint16_t ATTCH     : 1; /* [11..11] ATTCH Interrupt Status */
-#define LINK_REG_INTSTS1_ATTCH_Pos         (11UL)       /* ATTCH (Bit 11) */
-#define LINK_REG_INTSTS1_ATTCH_Msk         (0x800UL)    /* ATTCH (Bitfield-Mask: 0x01) */
diff --git a/.codespell/ignore-words.txt b/.codespell/ignore-words.txt
index e37d97a9f..e1ad88a07 100644
--- a/.codespell/ignore-words.txt
+++ b/.codespell/ignore-words.txt
@@ -6,3 +6,4 @@ fro
 dout
 mot
 te
+attch
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index e75e74104..3c681a7c3 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -20,8 +20,8 @@ CFLAGS += \
 	-ffreestanding
 
 SRC_C += \
-	src/portable/renesas/link/dcd_link.c \
-	src/portable/renesas/link/hcd_link.c \
+	src/portable/renesas/rusb2/dcd_rusb2.c \
+	src/portable/renesas/rusb2/hcd_rusb2.c \
 	hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
 	hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \
 	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \
diff --git a/hw/bsp/rx/family.mk b/hw/bsp/rx/family.mk
index ef9db293a..3044167b9 100644
--- a/hw/bsp/rx/family.mk
+++ b/hw/bsp/rx/family.mk
@@ -17,8 +17,8 @@ CFLAGS += \
 CFLAGS += -Wno-error=redundant-decls
 
 SRC_C += \
-	src/portable/renesas/link/dcd_link.c \
-	src/portable/renesas/link/hcd_link.c \
+	src/portable/renesas/rusb2/dcd_rusb2.c \
+	src/portable/renesas/rusb2/hcd_rusb2.c \
 	$(MCU_DIR)/vects.c
 
 INC += \
diff --git a/src/portable/renesas/link/dcd_link.c b/src/portable/renesas/rusb2/dcd_rusb2.c
similarity index 99%
rename from src/portable/renesas/link/dcd_link.c
rename to src/portable/renesas/rusb2/dcd_rusb2.c
index ce29769e0..ec9caab2c 100644
--- a/src/portable/renesas/link/dcd_link.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -35,14 +35,14 @@
                         TU_CHECK_MCU(OPT_MCU_RAXXX))
 
 #include "device/dcd.h"
-#include "link_type.h"
+#include "rusb2_type.h"
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
-#include "link_rx.h"
+  #include "rusb2_rx.h"
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
-#include "link_ra.h"
+  #include "rusb2_ra.h"
 #else
-#error "Unsupported MCU"
+  #error "Unsupported MCU"
 #endif
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/renesas/link/hcd_link.c b/src/portable/renesas/rusb2/hcd_rusb2.c
similarity index 99%
rename from src/portable/renesas/link/hcd_link.c
rename to src/portable/renesas/rusb2/hcd_rusb2.c
index b16544c2f..7d14aad60 100644
--- a/src/portable/renesas/link/hcd_link.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -31,14 +31,14 @@
                         TU_CHECK_MCU(OPT_MCU_RAXXX))
 
 #include "host/hcd.h"
-#include "link_type.h"
+#include "rusb2_type.h"
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
-#include "link_rx.h"
+  #include "rusb2_rx.h"
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
-#include "link_ra.h"
+  #include "rusb2_ra.h"
 #else
-#error "Unsupported MCU"
+  #error "Unsupported MCU"
 #endif
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/renesas/link/link_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
similarity index 98%
rename from src/portable/renesas/link/link_ra.h
rename to src/portable/renesas/rusb2/rusb2_ra.h
index 97618ef8f..a73b13951 100644
--- a/src/portable/renesas/link/link_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -31,8 +31,6 @@
 extern "C" {
 #endif
 
-#include "link_type.h"
-
 /* renesas fsp api */
 #include "bsp_api.h"
 
diff --git a/src/portable/renesas/link/link_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
similarity index 98%
rename from src/portable/renesas/link/link_rx.h
rename to src/portable/renesas/rusb2/rusb2_rx.h
index 9e31c5b46..e43253569 100644
--- a/src/portable/renesas/link/link_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -33,8 +33,6 @@
 extern "C" {
 #endif
 
-#include "link_type.h"
-
 #include "iodefine.h"
 
 #define LINK_REG_BASE (0x000A0000)
diff --git a/src/portable/renesas/link/link_type.h b/src/portable/renesas/rusb2/rusb2_type.h
similarity index 100%
rename from src/portable/renesas/link/link_type.h
rename to src/portable/renesas/rusb2/rusb2_type.h

From 92aed7e3e0600570da239729d1e83ede69be8158 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 16 Mar 2023 11:28:10 +0700
Subject: [PATCH 1545/2085] rename symbols

---
 docs/reference/supported.rst            |    4 +-
 src/portable/renesas/rusb2/dcd_rusb2.c  |  274 +++---
 src/portable/renesas/rusb2/hcd_rusb2.c  |  294 +++---
 src/portable/renesas/rusb2/rusb2_ra.h   |   10 +-
 src/portable/renesas/rusb2/rusb2_rx.h   |    8 +-
 src/portable/renesas/rusb2/rusb2_type.h | 1136 +++++++++++------------
 6 files changed, 862 insertions(+), 864 deletions(-)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index 30a685854..ae16d361d 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -62,9 +62,9 @@ Supported MCUs
 +--------------+---------+-------------+--------+------+-----------+-------------------+--------------+
 | Raspberry Pi | RP2040                | ✔      | ✔    | ✖         | rp2040, pio_usb   |              |
 +--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
-| Renesas      | RX  | 63N, 65N, 72N   | ✔      | ✔    | ✖         | link              |              |
+| Renesas      | RX  | 63N, 65N, 72N   | ✔      | ✔    | ✖         | rusb2             |              |
 |              +-----+-----------------+--------+------+-----------+-------------------+--------------+
-|              | RA  | XXX             | ✔      | ✔    |           | link              |              |
+|              | RA  | XXX             | ✔      | ✔    |           | rusb2             |              |
 +--------------+-----+-----------------+--------+------+-----------+-------------------+--------------+
 | Silabs       | EFM32GG12             | ✔      |      | ✖         | dwc2              |              |
 +--------------+-----------------------+--------+------+-----------+-------------------+--------------+
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index ec9caab2c..78584125f 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -51,9 +51,9 @@
 
 /* LINK core registers */
 #if defined(__CCRX__)
-#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE)
+  #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
 #else
-#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE)
+  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
 #endif
 
 /* Start of definition of packed structs (used by the CCRX toolchain) */
@@ -138,9 +138,9 @@ static unsigned find_pipe(unsigned xfer)
 static volatile uint16_t* get_pipectr(unsigned num)
 {
   if (num) {
-    return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]);
+    return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]);
   } else {
-    return (volatile uint16_t*)&(LINK_REG->DCPCTR);
+    return (volatile uint16_t*)&(RUSB2->DCPCTR);
   }
 }
 
@@ -148,7 +148,7 @@ static volatile reg_pipetre_t* get_pipetre(unsigned num)
 {
   volatile reg_pipetre_t* tre = NULL;
   if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E);
+    tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E);
   }
   return tre;
 }
@@ -168,19 +168,19 @@ static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
 
 static unsigned edpt0_max_packet_size(void)
 {
-  return LINK_REG->DCPMAXP_b.MXPS;
+  return RUSB2->DCPMAXP_b.MXPS;
 }
 
 static unsigned edpt_max_packet_size(unsigned num)
 {
-  LINK_REG->PIPESEL = num;
-  return LINK_REG->PIPEMAXP;
+  RUSB2->PIPESEL = num;
+  return RUSB2->PIPEMAXP;
 }
 
 static inline void pipe_wait_for_ready(unsigned num)
 {
-  while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ;
-  while (!LINK_REG->D0FIFOCTR_b.FRDY) ;
+  while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ;
+  while (!RUSB2->D0FIFOCTR_b.FRDY) ;
 }
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -242,14 +242,14 @@ static bool pipe0_xfer_in(void)
   void          *buf = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
+      pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
   if (len < mps) {
-    LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
+    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
   pipe->remaining = rem - len;
   return false;
@@ -261,19 +261,19 @@ static bool pipe0_xfer_out(void)
   const unsigned rem = pipe->remaining;
 
   const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN;
+  const unsigned vld = RUSB2->CFIFOCTR_b.DTLN;
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->CFIFO, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
+      pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
   if (len < mps) {
-    LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
+    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
@@ -293,24 +293,24 @@ static bool pipe_xfer_in(unsigned num)
     return true;
   }
 
-  LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
+  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
   const unsigned len  = TU_MIN(rem, mps);
   void          *buf  = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
+      pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
   if (len < mps) {
-    LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
+    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
-  LINK_REG->D0FIFOSEL = 0;
-  while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+  RUSB2->D0FIFOSEL = 0;
+  while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   return false;
 }
@@ -320,25 +320,25 @@ static bool pipe_xfer_out(unsigned num)
   pipe_state_t  *pipe = &_dcd.pipe[num];
   const unsigned rem  = pipe->remaining;
 
-  LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT;
+  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
-  const unsigned vld  = LINK_REG->D0FIFOCTR_b.DTLN;
+  const unsigned vld  = RUSB2->D0FIFOCTR_b.DTLN;
   const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf  = pipe->buf;
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&LINK_REG->D0FIFO, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
+      pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
   if (len < mps) {
-    LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
+    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
-  LINK_REG->D0FIFOSEL = 0;
-  while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+  RUSB2->D0FIFOSEL = 0;
+  while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
@@ -350,13 +350,13 @@ static bool pipe_xfer_out(unsigned num)
 static void process_setup_packet(uint8_t rhport)
 {
   uint16_t setup_packet[4];
-  if (0 == (LINK_REG->INTSTS0 & LINK_REG_INTSTS0_VALID_Msk)) return;
-  LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
-  setup_packet[0] = tu_le16toh(LINK_REG->USBREQ);
-  setup_packet[1] = LINK_REG->USBVAL;
-  setup_packet[2] = LINK_REG->USBINDX;
-  setup_packet[3] = LINK_REG->USBLENG;
-  LINK_REG->INTSTS0 = ~((uint16_t)LINK_REG_INTSTS0_VALID_Msk);
+  if (0 == (RUSB2->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return;
+  RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+  setup_packet[0] = tu_le16toh(RUSB2->USBREQ);
+  setup_packet[1] = RUSB2->USBVAL;
+  setup_packet[2] = RUSB2->USBINDX;
+  setup_packet[3] = RUSB2->USBLENG;
+  RUSB2->INTSTS0 = ~((uint16_t)RUSB2_INTSTS0_VALID_Msk);
   dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
 }
 
@@ -364,7 +364,7 @@ static void process_status_completion(uint8_t rhport)
 {
   uint8_t ep_addr;
   /* Check the data stage direction */
-  if (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) {
+  if (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) {
     /* IN transfer. */
     ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
   } else {
@@ -378,12 +378,12 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
 {
   /* configure fifo direction and access unit settings */
   if (ep_addr) { /* IN, 2 bytes */
-    LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
-                         (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
-    while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
+    RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
+                         (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+    while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
   } else { /* OUT, a byte */
-    LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
-    while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
+    RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
+    while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
   }
 
   pipe_state_t *pipe = &_dcd.pipe[0];
@@ -393,14 +393,14 @@ static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, u
   if (total_bytes) {
     pipe->buf     = buffer;
     if (ep_addr) { /* IN */
-      TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80));
+      TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80));
       pipe0_xfer_in();
     }
-    LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
+    RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
   } else {
     /* ZLP */
     pipe->buf        = NULL;
-    LINK_REG->DCPCTR = LINK_REG_DCPCTR_CCPL_Msk | LINK_REG_PIPE_CTR_PID_BUF;
+    RUSB2->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF;
   }
   return true;
 }
@@ -422,11 +422,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
     if (total_bytes) {
       pipe_xfer_in(num);
     } else { /* ZLP */
-      LINK_REG->D0FIFOSEL = num;
+      RUSB2->D0FIFOSEL = num;
       pipe_wait_for_ready(num);
-      LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
-      LINK_REG->D0FIFOSEL = 0;
-      while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+      RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      RUSB2->D0FIFOSEL = 0;
+      while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
     }
   } else {
 #if defined(__CCRX__)
@@ -437,11 +437,11 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
     if (pt) {
       const unsigned     mps = edpt_max_packet_size(num);
       volatile uint16_t *ctr = get_pipectr(num);
-      if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK;
+      if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK;
       pt->TRE   = TU_BIT(8);
       pt->TRN   = (total_bytes + mps - 1) / mps;
       pt->TRENB = 1;
-      *ctr = LINK_REG_PIPE_CTR_PID_BUF;
+      *ctr = RUSB2_PIPE_CTR_PID_BUF;
     }
   }
   //  TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
@@ -493,28 +493,28 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
 
 static void process_bus_reset(uint8_t rhport)
 {
-  LINK_REG->BEMPENB = 1;
-  LINK_REG->BRDYENB = 1;
-  LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
-  LINK_REG->D0FIFOSEL = 0;
-  while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  LINK_REG->D1FIFOSEL = 0;
-  while (LINK_REG->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_CTR[0]));
-  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&LINK_REG->PIPE_TR[0].E));
+  RUSB2->BEMPENB = 1;
+  RUSB2->BRDYENB = 1;
+  RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+  RUSB2->D0FIFOSEL = 0;
+  while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  RUSB2->D1FIFOSEL = 0;
+  while (RUSB2->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_CTR[0]));
+  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_TR[0].E));
   for (int i = 1; i <= 5; ++i) {
-    LINK_REG->PIPESEL = i;
-    LINK_REG->PIPECFG = 0;
-    *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk;
+    RUSB2->PIPESEL = i;
+    RUSB2->PIPECFG = 0;
+    *ctr = RUSB2_PIPE_CTR_ACLRM_Msk;
     *ctr = 0;
     ++ctr;
     *tre = TU_BIT(8);
     tre += 2;
   }
   for (int i = 6; i <= 9; ++i) {
-    LINK_REG->PIPESEL = i;
-    LINK_REG->PIPECFG = 0;
-    *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk;
+    RUSB2->PIPESEL = i;
+    RUSB2->PIPECFG = 0;
+    *ctr = RUSB2_PIPE_CTR_ACLRM_Msk;
     *ctr = 0;
     ++ctr;
   }
@@ -524,7 +524,7 @@ static void process_bus_reset(uint8_t rhport)
 
 static void process_set_address(uint8_t rhport)
 {
-  const uint32_t addr = LINK_REG->USBADDR_b.USBADDR;
+  const uint32_t addr = RUSB2->USBADDR_b.USBADDR;
   if (!addr) return;
   const tusb_control_request_t setup_packet = {
 #if defined(__CCRX__)
@@ -580,39 +580,39 @@ void dcd_init(uint8_t rhport)
   enable_interrupt(pswi);
 #endif
 
-  LINK_REG->SYSCFG_b.SCKE = 1;
-  while (!LINK_REG->SYSCFG_b.SCKE) ;
-  LINK_REG->SYSCFG_b.DRPD = 0;
-  LINK_REG->SYSCFG_b.DCFM = 0;
-  LINK_REG->SYSCFG_b.USBE = 1;
+  RUSB2->SYSCFG_b.SCKE = 1;
+  while (!RUSB2->SYSCFG_b.SCKE) ;
+  RUSB2->SYSCFG_b.DRPD = 0;
+  RUSB2->SYSCFG_b.DCFM = 0;
+  RUSB2->SYSCFG_b.USBE = 1;
 
   // MCU specific PHY init
-  link_phy_init();
+  rusb2_phy_init();
 
-  LINK_REG->PHYSLEW = 0x5;
-  LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
+  RUSB2->PHYSLEW = 0x5;
+  RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
 
   /* Setup default control pipe */
-  LINK_REG->DCPMAXP_b.MXPS = 64;
-  LINK_REG->INTENB0 = LINK_REG_INTSTS0_VBINT_Msk | LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk |
-          LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_CTRT_Msk | (USE_SOF ? LINK_REG_INTSTS0_SOFR_Msk : 0) |
-          LINK_REG_INTSTS0_RESM_Msk;
-  LINK_REG->BEMPENB = 1;
-  LINK_REG->BRDYENB = 1;
+  RUSB2->DCPMAXP_b.MXPS = 64;
+  RUSB2->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
+          RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
+          RUSB2_INTSTS0_RESM_Msk;
+  RUSB2->BEMPENB = 1;
+  RUSB2->BRDYENB = 1;
 
-  if (LINK_REG->INTSTS0_b.VBSTS) {
+  if (RUSB2->INTSTS0_b.VBSTS) {
     dcd_connect(rhport);
   }
 }
 
 void dcd_int_enable(uint8_t rhport)
 {
-  link_int_enable(rhport);
+  rusb2_int_enable(rhport);
 }
 
 void dcd_int_disable(uint8_t rhport)
 {
-  link_int_disable(rhport);
+  rusb2_int_disable(rhport);
 }
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
@@ -624,19 +624,19 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 void dcd_remote_wakeup(uint8_t rhport)
 {
   (void)rhport;
-  LINK_REG->DVSTCTR0_b.WKUP = 1;
+  RUSB2->DVSTCTR0_b.WKUP = 1;
 }
 
 void dcd_connect(uint8_t rhport)
 {
   (void)rhport;
-  LINK_REG->SYSCFG_b.DPRPU = 1;
+  RUSB2->SYSCFG_b.DPRPU = 1;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
   (void)rhport;
-  LINK_REG->SYSCFG_b.DPRPU = 0;
+  RUSB2->SYSCFG_b.DPRPU = 0;
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -672,26 +672,26 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   /* setup pipe */
   dcd_int_disable(rhport);
-  LINK_REG->PIPESEL = num;
-  LINK_REG->PIPEMAXP = mps;
+  RUSB2->PIPESEL = num;
+  RUSB2->PIPEMAXP = mps;
   volatile uint16_t *ctr = get_pipectr(num);
-  *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk;
+  *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk;
   *ctr = 0;
   unsigned cfg = (dir << 4) | epn;
   if (xfer == TUSB_XFER_BULK) {
-    cfg |= (LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk);
+    cfg |= (RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk);
   } else if (xfer == TUSB_XFER_INTERRUPT) {
-    cfg |= LINK_REG_PIPECFG_TYPE_INT;
+    cfg |= RUSB2_PIPECFG_TYPE_INT;
   } else {
-    cfg |= (LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk);
+    cfg |= (RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk);
   }
-  LINK_REG->PIPECFG = cfg;
-  LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
-  LINK_REG->BRDYENB |= TU_BIT(num);
+  RUSB2->PIPECFG = cfg;
+  RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  RUSB2->BRDYENB |= TU_BIT(num);
   if (dir || (xfer != TUSB_XFER_BULK)) {
-    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
+    *ctr = RUSB2_PIPE_CTR_PID_BUF;
   }
-  // TU_LOG1("O %d %x %x\r\n", LINK_REG->PIPESEL, LINK_REG->PIPECFG, LINK_REG->PIPEMAXP);
+  // TU_LOG1("O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP);
   dcd_int_enable(rhport);
 
   return true;
@@ -716,11 +716,11 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   const unsigned dir = tu_edpt_dir(ep_addr);
   const unsigned num = _dcd.ep[dir][epn];
 
-  LINK_REG->BRDYENB &= ~TU_BIT(num);
+  RUSB2->BRDYENB &= ~TU_BIT(num);
   volatile uint16_t *ctr = get_pipectr(num);
   *ctr = 0;
-  LINK_REG->PIPESEL = num;
-  LINK_REG->PIPECFG = 0;
+  RUSB2->PIPESEL = num;
+  RUSB2->PIPECFG = 0;
   _dcd.pipe[num].ep = 0;
   _dcd.ep[dir][epn] = 0;
 }
@@ -751,8 +751,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   if (!ctr) return;
   dcd_int_disable(rhport);
   const uint32_t pid = *ctr & 0x3;
-  *ctr = pid | LINK_REG_PIPE_CTR_PID_STALL;
-  *ctr = LINK_REG_PIPE_CTR_PID_STALL;
+  *ctr = pid | RUSB2_PIPE_CTR_PID_STALL;
+  *ctr = RUSB2_PIPE_CTR_PID_STALL;
   dcd_int_enable(rhport);
 }
 
@@ -761,15 +761,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
   if (!ctr) return;
   dcd_int_disable(rhport);
-  *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk;
+  *ctr = RUSB2_PIPE_CTR_SQCLR_Msk;
 
   if (tu_edpt_dir(ep_addr)) { /* IN */
-    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
+    *ctr = RUSB2_PIPE_CTR_PID_BUF;
   } else {
     const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
-    LINK_REG->PIPESEL = num;
-    if (LINK_REG->PIPECFG_b.TYPE != 1) {
-      *ctr = LINK_REG_PIPE_CTR_PID_BUF;
+    RUSB2->PIPESEL = num;
+    if (RUSB2->PIPECFG_b.TYPE != 1) {
+      *ctr = RUSB2_PIPE_CTR_PID_BUF;
     }
   }
   dcd_int_enable(rhport);
@@ -782,71 +782,71 @@ void dcd_int_handler(uint8_t rhport)
 {
   (void)rhport;
 
-  unsigned is0 = LINK_REG->INTSTS0;
+  unsigned is0 = RUSB2->INTSTS0;
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_CTRT_Msk | LINK_REG_INTSTS0_DVST_Msk | LINK_REG_INTSTS0_SOFR_Msk |
-                         LINK_REG_INTSTS0_RESM_Msk | LINK_REG_INTSTS0_VBINT_Msk) & is0) | LINK_REG_INTSTS0_VALID_Msk;
-  if (is0 & LINK_REG_INTSTS0_VBINT_Msk) {
-    if (LINK_REG->INTSTS0_b.VBSTS) {
+  RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk |
+                         RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk;
+  if (is0 & RUSB2_INTSTS0_VBINT_Msk) {
+    if (RUSB2->INTSTS0_b.VBSTS) {
       dcd_connect(rhport);
     } else {
       dcd_disconnect(rhport);
     }
   }
-  if (is0 & LINK_REG_INTSTS0_RESM_Msk) {
+  if (is0 & RUSB2_INTSTS0_RESM_Msk) {
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
 #if (0==USE_SOF)
-    LINK_REG->INTENB0_b.SOFE = 0;
+    RUSB2->INTENB0_b.SOFE = 0;
 #endif
   }
-  if ((is0 & LINK_REG_INTSTS0_SOFR_Msk) && LINK_REG->INTENB0_b.SOFE) {
+  if ((is0 & RUSB2_INTSTS0_SOFR_Msk) && RUSB2->INTENB0_b.SOFE) {
     // USBD will exit suspended mode when SOF event is received
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
 #if (0 == USE_SOF)
-    LINK_REG->INTENB0_b.SOFE = 0;
+    RUSB2->INTENB0_b.SOFE = 0;
 #endif
   }
-  if (is0 & LINK_REG_INTSTS0_DVST_Msk) {
-    switch (is0 & LINK_REG_INTSTS0_DVSQ_Msk) {
-    case LINK_REG_INTSTS0_DVSQ_STATE_DEF:
+  if (is0 & RUSB2_INTSTS0_DVST_Msk) {
+    switch (is0 & RUSB2_INTSTS0_DVSQ_Msk) {
+    case RUSB2_INTSTS0_DVSQ_STATE_DEF:
       process_bus_reset(rhport);
       break;
-    case LINK_REG_INTSTS0_DVSQ_STATE_ADDR:
+    case RUSB2_INTSTS0_DVSQ_STATE_ADDR:
       process_set_address(rhport);
       break;
-    case LINK_REG_INTSTS0_DVSQ_STATE_SUSP0:
-    case LINK_REG_INTSTS0_DVSQ_STATE_SUSP1:
-    case LINK_REG_INTSTS0_DVSQ_STATE_SUSP2:
-    case LINK_REG_INTSTS0_DVSQ_STATE_SUSP3:
+    case RUSB2_INTSTS0_DVSQ_STATE_SUSP0:
+    case RUSB2_INTSTS0_DVSQ_STATE_SUSP1:
+    case RUSB2_INTSTS0_DVSQ_STATE_SUSP2:
+    case RUSB2_INTSTS0_DVSQ_STATE_SUSP3:
        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
 #if (0==USE_SOF)
-      LINK_REG->INTENB0_b.SOFE = 1;
+      RUSB2->INTENB0_b.SOFE = 1;
 #endif
     default:
       break;
     }
   }
-  if (is0 & LINK_REG_INTSTS0_CTRT_Msk) {
-    if (is0 & LINK_REG_INTSTS0_CTSQ_CTRL_RDATA) {
+  if (is0 & RUSB2_INTSTS0_CTRT_Msk) {
+    if (is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA) {
       /* A setup packet has been received. */
       process_setup_packet(rhport);
-    } else if (0 == (is0 & LINK_REG_INTSTS0_CTSQ_Msk)) {
+    } else if (0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk)) {
       /* A ZLP has been sent/received. */
       process_status_completion(rhport);
     }
   }
-  if (is0 & LINK_REG_INTSTS0_BEMP_Msk) {
-    const unsigned s = LINK_REG->BEMPSTS;
-    LINK_REG->BEMPSTS = 0;
+  if (is0 & RUSB2_INTSTS0_BEMP_Msk) {
+    const unsigned s = RUSB2->BEMPSTS;
+    RUSB2->BEMPSTS = 0;
     if (s & 1) {
       process_pipe0_bemp(rhport);
     }
   }
-  if (is0 & LINK_REG_INTSTS0_BRDY_Msk) {
-    const unsigned m = LINK_REG->BRDYENB;
-    unsigned s = LINK_REG->BRDYSTS & m;
+  if (is0 & RUSB2_INTSTS0_BRDY_Msk) {
+    const unsigned m = RUSB2->BRDYENB;
+    unsigned s = RUSB2->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    LINK_REG->BRDYSTS = ~s;
+    RUSB2->BRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       static const int Mod37BitPosition[] = {
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 7d14aad60..e4743223e 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -47,9 +47,9 @@
 
 /* LINK core registers */
 #if defined(__CCRX__)
-#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE)
+  #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
 #else
-#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE)
+  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
 #endif
 
 TU_ATTR_PACKED_BEGIN
@@ -135,9 +135,9 @@ static unsigned find_pipe(unsigned xfer)
 static volatile uint16_t* get_pipectr(unsigned num)
 {
   if (num) {
-    return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]);
+    return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]);
   } else {
-    return (volatile uint16_t*)&(LINK_REG->DCPCTR);
+    return (volatile uint16_t*)&(RUSB2->DCPCTR);
   }
 }
 
@@ -145,7 +145,7 @@ static volatile reg_pipetre_t* get_pipetre(unsigned num)
 {
   volatile reg_pipetre_t* tre = NULL;
   if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E);
+    tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E);
   }
   return tre;
 }
@@ -164,19 +164,19 @@ static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr)
 
 static unsigned edpt0_max_packet_size(void)
 {
-  return LINK_REG->DCPMAXP_b.MXPS;
+  return RUSB2->DCPMAXP_b.MXPS;
 }
 
 static unsigned edpt_max_packet_size(unsigned num)
 {
-  LINK_REG->PIPESEL = num;
-  return LINK_REG->PIPEMAXP_b.MXPS;
+  RUSB2->PIPESEL = num;
+  return RUSB2->PIPEMAXP_b.MXPS;
 }
 
 static inline void pipe_wait_for_ready(unsigned num)
 {
-  while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ;
-  while (!LINK_REG->D0FIFOCTR_b.FRDY) ;
+  while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ;
+  while (!RUSB2->D0FIFOCTR_b.FRDY) ;
 }
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -207,23 +207,23 @@ static bool pipe0_xfer_in(void)
   const unsigned rem = pipe->remaining;
 
   const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN;
+  const unsigned vld = RUSB2->CFIFOCTR_b.DTLN;
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
-    LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
-    pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
+    RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+    pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
+    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return true;
   }
-  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
+  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
   return false;
 }
 
@@ -239,11 +239,11 @@ static bool pipe0_xfer_out(void)
   const unsigned len = TU_MIN(mps, rem);
   void          *buf = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
+    pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
+    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
   pipe->remaining = rem - len;
   return false;
@@ -254,21 +254,21 @@ static bool pipe_xfer_in(unsigned num)
   pipe_state_t  *pipe = &_hcd.pipe[num];
   const unsigned rem  = pipe->remaining;
 
-  LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT;
+  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
-  const unsigned vld  = LINK_REG->D0FIFOCTR_b.DTLN;
+  const unsigned vld  = RUSB2->D0FIFOCTR_b.DTLN;
   const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
+    pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
+    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
-  LINK_REG->D0FIFOSEL = 0;
-  while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  RUSB2->D0FIFOSEL = 0;
+  while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
@@ -287,19 +287,19 @@ static bool pipe_xfer_out(unsigned num)
     return true;
   }
 
-  LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
+  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
   const unsigned mps  = edpt_max_packet_size(num);
   pipe_wait_for_ready(num);
   const unsigned len  = TU_MIN(rem, mps);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
+    pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps)
-    LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
-  LINK_REG->D0FIFOSEL = 0;
-  while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+  RUSB2->D0FIFOSEL = 0;
+  while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   return false;
 }
@@ -311,12 +311,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
 
   /* configure fifo direction and access unit settings */
   if (dir_in) { /* IN, a byte */
-    LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
-    while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
+    RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
+    while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
   } else { /* OUT, 2 bytes */
-    LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
-                         (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
-    while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
+    RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
+                         (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+    while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
   }
 
   pipe_state_t *pipe = &_hcd.pipe[0];
@@ -326,21 +326,21 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
   if (buflen) {
     pipe->buf     = buffer;
     if (!dir_in) { /* OUT */
-      TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80));
+      TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80));
       pipe0_xfer_out();
     }
   } else { /* ZLP */
     pipe->buf        = NULL;
     if (!dir_in) { /* OUT */
-      LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
+      RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
     }
-    if (dir_in == LINK_REG->DCPCFG_b.DIR) {
-      TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID);
-      LINK_REG->DCPCTR_b.SQSET = 1;
-      LINK_REG->DCPCFG_b.DIR = dir_in ^ 1;
+    if (dir_in == RUSB2->DCPCFG_b.DIR) {
+      TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == RUSB2->DCPCTR_b.PID);
+      RUSB2->DCPCTR_b.SQSET = 1;
+      RUSB2->DCPCFG_b.DIR = dir_in ^ 1;
     }
   }
-  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
+  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
   return true;
 }
 
@@ -360,23 +360,23 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u
     if (buflen) {
       pipe_xfer_out(num);
     } else { /* ZLP */
-      LINK_REG->D0FIFOSEL = num;
+      RUSB2->D0FIFOSEL = num;
       pipe_wait_for_ready(num);
-      LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
-      LINK_REG->D0FIFOSEL = 0;
-      while (LINK_REG->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+      RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      RUSB2->D0FIFOSEL = 0;
+      while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
     }
   } else {
     volatile uint16_t     *ctr = get_pipectr(num);
     volatile reg_pipetre_t *pt = get_pipetre(num);
     if (pt) {
       const unsigned     mps = edpt_max_packet_size(num);
-      if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK;
+      if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK;
       pt->TRE   = TU_BIT(8);
       pt->TRN   = (buflen + mps - 1) / mps;
       pt->TRENB = 1;
     }
-    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
+    *ctr = RUSB2_PIPE_CTR_PID_BUF;
   }
   return true;
 }
@@ -410,10 +410,10 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
   unsigned result;
   uint16_t volatile *ctr = get_pipectr(num);
   // TU_LOG1("NRDY %d %x\n", num, *ctr);
-  switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) {
+  switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) {
     default: return;
-    case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
-    case LINK_REG_PIPE_CTR_PID_NAK:   result = XFER_RESULT_FAILED;  break;
+    case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
+    case RUSB2_PIPE_CTR_PID_NAK:   result = XFER_RESULT_FAILED;  break;
   }
   pipe_state_t *pipe = &_hcd.pipe[num];
   hcd_event_xfer_complete(pipe->dev, pipe->ep,
@@ -485,44 +485,44 @@ bool hcd_init(uint8_t rhport)
   enable_interrupt(pswi);
 #endif
 
-  LINK_REG->SYSCFG_b.SCKE = 1;
-  while (!LINK_REG->SYSCFG_b.SCKE) ;
-  LINK_REG->SYSCFG_b.DPRPU = 0;
-  LINK_REG->SYSCFG_b.DRPD = 0;
-  LINK_REG->SYSCFG_b.DCFM = 1;
+  RUSB2->SYSCFG_b.SCKE = 1;
+  while (!RUSB2->SYSCFG_b.SCKE) ;
+  RUSB2->SYSCFG_b.DPRPU = 0;
+  RUSB2->SYSCFG_b.DRPD = 0;
+  RUSB2->SYSCFG_b.DCFM = 1;
 
-  LINK_REG->DVSTCTR0_b.VBUSEN = 1;
+  RUSB2->DVSTCTR0_b.VBUSEN = 1;
 
-  LINK_REG->SYSCFG_b.DRPD = 1;
+  RUSB2->SYSCFG_b.DRPD = 1;
   for (volatile int i = 0; i < 30000; ++i) ;
-  LINK_REG->SYSCFG_b.USBE = 1;
+  RUSB2->SYSCFG_b.USBE = 1;
 
   // MCU specific PHY init
-  link_phy_init();
+  rusb2_phy_init();
 
-  LINK_REG->PHYSLEW = 0x5;
-  LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
+  RUSB2->PHYSLEW = 0x5;
+  RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
 
   /* Setup default control pipe */
-  LINK_REG->DCPCFG  = LINK_REG_PIPECFG_SHTNAK_Msk;
-  LINK_REG->DCPMAXP = 64;
-  LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk;
-  LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk;
-  LINK_REG->BEMPENB = 1;
-  LINK_REG->NRDYENB = 1;
-  LINK_REG->BRDYENB = 1;
+  RUSB2->DCPCFG  = RUSB2_PIPECFG_SHTNAK_Msk;
+  RUSB2->DCPMAXP = 64;
+  RUSB2->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk;
+  RUSB2->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk;
+  RUSB2->BEMPENB = 1;
+  RUSB2->NRDYENB = 1;
+  RUSB2->BRDYENB = 1;
 
   return true;
 }
 
 void hcd_int_enable(uint8_t rhport)
 {
-  link_int_enable(rhport);
+  rusb2_int_enable(rhport);
 }
 
 void hcd_int_disable(uint8_t rhport)
 {
-  link_int_disable(rhport);
+  rusb2_int_disable(rhport);
 }
 
 uint32_t hcd_frame_number(uint8_t rhport)
@@ -531,7 +531,7 @@ uint32_t hcd_frame_number(uint8_t rhport)
   /* The device must be reset at least once after connection
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
-  return LINK_REG->FRMNUM_b.FRNM;
+  return RUSB2->FRMNUM_b.FRNM;
 }
 
 /*--------------------------------------------------------------------+
@@ -540,24 +540,24 @@ uint32_t hcd_frame_number(uint8_t rhport)
 bool hcd_port_connect_status(uint8_t rhport)
 {
   (void)rhport;
-  return LINK_REG->INTSTS1_b.ATTCH ? true : false;
+  return RUSB2->INTSTS1_b.ATTCH ? true : false;
 }
 
 void hcd_port_reset(uint8_t rhport)
 {
-  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
-  while (LINK_REG->DCPCTR_b.PBUSY) ;
+  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+  while (RUSB2->DCPCTR_b.PBUSY) ;
   hcd_int_disable(rhport);
-  LINK_REG->DVSTCTR0_b.UACT = 0;
-  if (LINK_REG->DCPCTR_b.SUREQ) {
-    LINK_REG->DCPCTR_b.SUREQCLR = 1;
+  RUSB2->DVSTCTR0_b.UACT = 0;
+  if (RUSB2->DCPCTR_b.SUREQ) {
+    RUSB2->DCPCTR_b.SUREQCLR = 1;
   }
   hcd_int_enable(rhport);
   /* Reset should be asserted 10-20ms. */
-  LINK_REG->DVSTCTR0_b.USBRST = 1;
+  RUSB2->DVSTCTR0_b.USBRST = 1;
   for (volatile int i = 0; i < 2400000; ++i) ;
-  LINK_REG->DVSTCTR0_b.USBRST = 0;
-  LINK_REG->DVSTCTR0_b.UACT = 1;
+  RUSB2->DVSTCTR0_b.USBRST = 0;
+  RUSB2->DVSTCTR0_b.UACT = 1;
   _hcd.need_reset = false;
 }
 
@@ -569,10 +569,10 @@ void hcd_port_reset_end(uint8_t rhport)
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   (void)rhport;
-  switch (LINK_REG->DVSTCTR0_b.RHST) {
+  switch (RUSB2->DVSTCTR0_b.RHST) {
     default: return TUSB_SPEED_INVALID;
-    case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL;
-    case LINK_REG_DVSTCTR0_RHST_LS:  return TUSB_SPEED_LOW;
+    case RUSB2_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL;
+    case RUSB2_DVSTCTR0_RHST_LS:  return TUSB_SPEED_LOW;
   }
 }
 
@@ -588,13 +588,13 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
     unsigned num = *ep;
     if (!num || dev_addr != _hcd.pipe[num].dev) continue;
 
-    ctr = (uint16_t volatile*)&LINK_REG->PIPE_CTR[num - 1];
+    ctr = (uint16_t volatile*)&RUSB2->PIPE_CTR[num - 1];
     *ctr = 0;
-    LINK_REG->NRDYENB &= ~TU_BIT(num);
-    LINK_REG->BRDYENB &= ~TU_BIT(num);
-    LINK_REG->PIPESEL = num;
-    LINK_REG->PIPECFG = 0;
-    LINK_REG->PIPEMAXP = 0;
+    RUSB2->NRDYENB &= ~TU_BIT(num);
+    RUSB2->BRDYENB &= ~TU_BIT(num);
+    RUSB2->PIPESEL = num;
+    RUSB2->PIPECFG = 0;
+    RUSB2->PIPEMAXP = 0;
 
     _hcd.pipe[num].ep  = 0;
     _hcd.pipe[num].dev = 0;
@@ -608,32 +608,32 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void)rhport;
-  //  TU_LOG1("S %d %x\n", dev_addr, LINK_REG->DCPCTR);
+  //  TU_LOG1("S %d %x\n", dev_addr, RUSB2->DCPCTR);
 
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
-  TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ);
+  TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ);
 
-  LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
+  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
 
   _hcd.pipe[0].buf       = NULL;
   _hcd.pipe[0].length    = 8;
   _hcd.pipe[0].remaining = 0;
   _hcd.pipe[0].dev       = dev_addr;
 
-  while (LINK_REG->DCPCTR_b.PBUSY) ;
-  LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
+  while (RUSB2->DCPCTR_b.PBUSY) ;
+  RUSB2->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
 
   /* Set direction in advance for DATA stage */
   uint8_t const bmRequesttype = setup_packet[0];
-  LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
+  RUSB2->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
 
   uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
-  LINK_REG->USBREQ  = tu_htole16(p[0]);
-  LINK_REG->USBVAL  = p[1];
-  LINK_REG->USBINDX = p[2];
-  LINK_REG->USBLENG = p[3];
+  RUSB2->USBREQ  = tu_htole16(p[0]);
+  RUSB2->USBVAL  = p[1];
+  RUSB2->USBINDX = p[2];
+  RUSB2->USBLENG = p[3];
 
-  LINK_REG->DCPCTR_b.SUREQ = 1;
+  RUSB2->DCPCTR_b.SUREQ = 1;
   return true;
 }
 
@@ -646,14 +646,14 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   const unsigned epn     = tu_edpt_number(ep_addr);
   const unsigned mps     = tu_edpt_packet_size(ep_desc);
   if (0 == epn) {
-    LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
+    RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
     hcd_devtree_info_t devtree;
     hcd_devtree_get_info(dev_addr, &devtree);
-    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0];
+    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &RUSB2->DEVADD[0];
     devadd += dev_addr;
-    while (LINK_REG->DCPCTR_b.PBUSY) ;
-    LINK_REG->DCPMAXP = (dev_addr << 12) | mps;
-    *devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS;
+    while (RUSB2->DCPCTR_b.PBUSY) ;
+    RUSB2->DCPMAXP = (dev_addr << 12) | mps;
+    *devadd = (TUSB_SPEED_FULL == devtree.speed) ? RUSB2_DEVADD_USBSPD_FS : RUSB2_DEVADD_USBSPD_LS;
     _hcd.ctl_mps[dev_addr] = mps;
     return true;
   }
@@ -672,25 +672,25 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 
   /* setup pipe */
   hcd_int_disable(rhport);
-  LINK_REG->PIPESEL = num;
-  LINK_REG->PIPEMAXP = (dev_addr << 12) | mps;
+  RUSB2->PIPESEL = num;
+  RUSB2->PIPEMAXP = (dev_addr << 12) | mps;
   volatile uint16_t *ctr = get_pipectr(num);
-  *ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk;
+  *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk;
   *ctr = 0;
   unsigned cfg = ((1 ^ dir_in) << 4) | epn;
   if (xfer == TUSB_XFER_BULK) {
-    cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk;
+    cfg |= RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk;
   } else if (xfer == TUSB_XFER_INTERRUPT) {
-    cfg |= LINK_REG_PIPECFG_TYPE_INT;
+    cfg |= RUSB2_PIPECFG_TYPE_INT;
   } else {
-    cfg |= LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk;
+    cfg |= RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk;
   }
-  LINK_REG->PIPECFG = cfg;
-  LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
-  LINK_REG->NRDYENB |= TU_BIT(num);
-  LINK_REG->BRDYENB |= TU_BIT(num);
+  RUSB2->PIPECFG = cfg;
+  RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  RUSB2->NRDYENB |= TU_BIT(num);
+  RUSB2->BRDYENB |= TU_BIT(num);
   if (!dir_in) {
-    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
+    *ctr = RUSB2_PIPE_CTR_PID_BUF;
   }
   hcd_int_enable(rhport);
 
@@ -717,12 +717,12 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
     *ctr = pid & 2;
     *ctr = 0;
   }
-  *ctr = LINK_REG_PIPE_CTR_SQCLR_Msk;
+  *ctr = RUSB2_PIPE_CTR_SQCLR_Msk;
   unsigned const epn = tu_edpt_number(ep_addr);
   if (!epn) return true;
 
   if (!tu_edpt_dir(ep_addr)) { /* OUT */
-    *ctr = LINK_REG_PIPE_CTR_PID_BUF;
+    *ctr = RUSB2_PIPE_CTR_PID_BUF;
   }
   return true;
 }
@@ -740,49 +740,49 @@ void hcd_int_handler(uint8_t rhport)
     20, 8, 19, 18};
 #endif
 
-  unsigned is1 = LINK_REG->INTSTS1;
-  unsigned is0 = LINK_REG->INTSTS0;
+  unsigned is1 = RUSB2->INTSTS1;
+  unsigned is0 = RUSB2->INTSTS0;
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1);
-  LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0);
+  RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
+  RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
   // TU_LOG1("IS %04x %04x\n", is0, is1);
-  is1 &= LINK_REG->INTENB1;
-  is0 &= LINK_REG->INTENB0;
+  is1 &= RUSB2->INTENB1;
+  is0 &= RUSB2->INTENB0;
 
-  if (is1 & LINK_REG_INTSTS1_SACK_Msk) {
+  if (is1 & RUSB2_INTSTS1_SACK_Msk) {
     /* Set DATA1 in advance for the next transfer. */
-    LINK_REG->DCPCTR_b.SQSET = 1;
-    hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
+    RUSB2->DCPCTR_b.SQSET = 1;
+    hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
   }
-  if (is1 & LINK_REG_INTSTS1_SIGN_Msk) {
-    hcd_event_xfer_complete(LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
+  if (is1 & RUSB2_INTSTS1_SIGN_Msk) {
+    hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
   }
-  if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) {
-    LINK_REG->DVSTCTR0_b.UACT = 1;
+  if (is1 & RUSB2_INTSTS1_ATTCH_Msk) {
+    RUSB2->DVSTCTR0_b.UACT = 1;
     _hcd.need_reset = true;
-    LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk;
+    RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
     hcd_event_device_attach(rhport, true);
   }
-  if (is1 & LINK_REG_INTSTS1_DTCH_Msk) {
-    LINK_REG->DVSTCTR0_b.UACT = 0;
-    if (LINK_REG->DCPCTR_b.SUREQ) {
-      LINK_REG->DCPCTR_b.SUREQCLR = 1;
+  if (is1 & RUSB2_INTSTS1_DTCH_Msk) {
+    RUSB2->DVSTCTR0_b.UACT = 0;
+    if (RUSB2->DCPCTR_b.SUREQ) {
+      RUSB2->DCPCTR_b.SUREQCLR = 1;
     }
-    LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk;
+    RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk;
     hcd_event_device_remove(rhport, true);
   }
 
-  if (is0 & LINK_REG_INTSTS0_BEMP_Msk) {
-    const unsigned s = LINK_REG->BEMPSTS;
-    LINK_REG->BEMPSTS = 0;
+  if (is0 & RUSB2_INTSTS0_BEMP_Msk) {
+    const unsigned s = RUSB2->BEMPSTS;
+    RUSB2->BEMPSTS = 0;
     if (s & 1) {
       process_pipe0_bemp(rhport);
     }
   }
-  if (is0 & LINK_REG_INTSTS0_NRDY_Msk) {
-    const unsigned m = LINK_REG->NRDYENB;
-    unsigned s = LINK_REG->NRDYSTS & m;
-    LINK_REG->NRDYSTS = ~s;
+  if (is0 & RUSB2_INTSTS0_NRDY_Msk) {
+    const unsigned m = RUSB2->NRDYENB;
+    unsigned s = RUSB2->NRDYSTS & m;
+    RUSB2->NRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       const unsigned num = Mod37BitPosition[(-s & s) % 37];
@@ -793,11 +793,11 @@ void hcd_int_handler(uint8_t rhport)
       s &= ~TU_BIT(num);
     }
   }
-  if (is0 & LINK_REG_INTSTS0_BRDY_Msk) {
-    const unsigned m = LINK_REG->BRDYENB;
-    unsigned s = LINK_REG->BRDYSTS & m;
+  if (is0 & RUSB2_INTSTS0_BRDY_Msk) {
+    const unsigned m = RUSB2->BRDYENB;
+    unsigned s = RUSB2->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    LINK_REG->BRDYSTS = ~s;
+    RUSB2->BRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       const unsigned num = Mod37BitPosition[(-s & s) % 37];
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index a73b13951..24658e95a 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -34,24 +34,22 @@ extern "C" {
 /* renesas fsp api */
 #include "bsp_api.h"
 
-#define LINK_REG_BASE (0x40090000)
+#define RUSB2_REG_BASE (0x40090000)
 
-TU_ATTR_ALWAYS_INLINE
-static inline void link_int_enable(uint8_t rhport)
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
   (void) rhport;
   NVIC_EnableIRQ(TU_IRQn);
 }
 
-TU_ATTR_ALWAYS_INLINE
-static inline void link_int_disable(uint8_t rhport)
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport)
 {
   (void) rhport;
   NVIC_DisableIRQ(TU_IRQn);
 }
 
 // MCU specific PHY init
-static inline void link_phy_init(void)
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void)
 {
 }
 
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
index e43253569..c28689df1 100644
--- a/src/portable/renesas/rusb2/rusb2_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -35,9 +35,9 @@ extern "C" {
 
 #include "iodefine.h"
 
-#define LINK_REG_BASE (0x000A0000)
+#define RUSB2_REG_BASE (0x000A0000)
 
-TU_ATTR_ALWAYS_INLINE static inline void link_int_enable(uint8_t rhport)
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
   (void) rhport;
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
@@ -47,7 +47,7 @@ TU_ATTR_ALWAYS_INLINE static inline void link_int_enable(uint8_t rhport)
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void link_int_disable(uint8_t rhport)
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport)
 {
   (void) rhport;
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
@@ -58,7 +58,7 @@ TU_ATTR_ALWAYS_INLINE static inline void link_int_disable(uint8_t rhport)
 }
 
 // MCU specific PHY init
-TU_ATTR_ALWAYS_INLINE static inline void link_phy_init(void)
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void)
 {
 #if (CFG_TUSB_MCU == OPT_MCU_RX72N)
   IR(PERIB, INTB185) = 0;
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index cb3db650a..6a5c7f8ff 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -60,7 +60,7 @@ typedef struct TU_ATTR_PACKED {
       volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */
     } N_b;
   };
-} LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */
+} RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */
 
 /* LINK_REG Structure */
 typedef struct TU_ATTR_PACKED {
@@ -685,7 +685,7 @@ typedef struct TU_ATTR_PACKED {
   };
   volatile const uint16_t RESERVED13;
   volatile const uint32_t RESERVED14[3];
-  volatile LINK_REG_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */
+  volatile RUSB2_PIPE_TR_t PIPE_TR[5]; /* (@ 0x00000090) Pipe Transaction Counter Registers */
   volatile const uint32_t RESERVED15[3];
 
   union {
@@ -950,7 +950,7 @@ typedef struct TU_ATTR_PACKED {
       uint32_t : 8;
     } DPUSR1R_FS_b;
   };
-} LINK_REG_t; /* Size = 1032 (0x408) */
+} RUSB2_REG_t; /* Size = 1032 (0x408) */
 
 TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
 TU_ATTR_BIT_FIELD_ORDER_END
@@ -961,706 +961,706 @@ TU_ATTR_BIT_FIELD_ORDER_END
 
 // PIPE_TR
 // E
-#define LINK_REG_PIPE_TR_E_TRENB_Pos       (9UL)        /* TRENB (Bit 9) */
-#define LINK_REG_PIPE_TR_E_TRENB_Msk       (0x200UL)    /* TRENB (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_TR_E_TRCLR_Pos       (8UL)        /* TRCLR (Bit 8) */
-#define LINK_REG_PIPE_TR_E_TRCLR_Msk       (0x100UL)    /* TRCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_TR_E_TRENB_Pos       (9UL)        /* TRENB (Bit 9) */
+#define RUSB2_PIPE_TR_E_TRENB_Msk       (0x200UL)    /* TRENB (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_TR_E_TRCLR_Pos       (8UL)        /* TRCLR (Bit 8) */
+#define RUSB2_PIPE_TR_E_TRCLR_Msk       (0x100UL)    /* TRCLR (Bitfield-Mask: 0x01) */
 
 // N
-#define LINK_REG_PIPE_TR_N_TRNCNT_Pos      (0UL)        /* TRNCNT (Bit 0) */
-#define LINK_REG_PIPE_TR_N_TRNCNT_Msk      (0xffffUL)   /* TRNCNT (Bitfield-Mask: 0xffff) */
+#define RUSB2_PIPE_TR_N_TRNCNT_Pos      (0UL)        /* TRNCNT (Bit 0) */
+#define RUSB2_PIPE_TR_N_TRNCNT_Msk      (0xffffUL)   /* TRNCNT (Bitfield-Mask: 0xffff) */
 
 // LINK_REG
 
 // SYSCFG
-#define LINK_REG_SYSCFG_SCKE_Pos           (10UL)       /* SCKE (Bit 10) */
-#define LINK_REG_SYSCFG_SCKE_Msk           (0x400UL)    /* SCKE (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_CNEN_Pos           (8UL)        /* CNEN (Bit 8) */
-#define LINK_REG_SYSCFG_CNEN_Msk           (0x100UL)    /* CNEN (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_DCFM_Pos           (6UL)        /* DCFM (Bit 6) */
-#define LINK_REG_SYSCFG_DCFM_Msk           (0x40UL)     /* DCFM (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_DRPD_Pos           (5UL)        /* DRPD (Bit 5) */
-#define LINK_REG_SYSCFG_DRPD_Msk           (0x20UL)     /* DRPD (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_DPRPU_Pos          (4UL)        /* DPRPU (Bit 4) */
-#define LINK_REG_SYSCFG_DPRPU_Msk          (0x10UL)     /* DPRPU (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_DMRPU_Pos          (3UL)        /* DMRPU (Bit 3) */
-#define LINK_REG_SYSCFG_DMRPU_Msk          (0x8UL)      /* DMRPU (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSCFG_USBE_Pos           (0UL)        /* USBE (Bit 0) */
-#define LINK_REG_SYSCFG_USBE_Msk           (0x1UL)      /* USBE (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_SCKE_Pos           (10UL)       /* SCKE (Bit 10) */
+#define RUSB2_SYSCFG_SCKE_Msk           (0x400UL)    /* SCKE (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_CNEN_Pos           (8UL)        /* CNEN (Bit 8) */
+#define RUSB2_SYSCFG_CNEN_Msk           (0x100UL)    /* CNEN (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_DCFM_Pos           (6UL)        /* DCFM (Bit 6) */
+#define RUSB2_SYSCFG_DCFM_Msk           (0x40UL)     /* DCFM (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_DRPD_Pos           (5UL)        /* DRPD (Bit 5) */
+#define RUSB2_SYSCFG_DRPD_Msk           (0x20UL)     /* DRPD (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_DPRPU_Pos          (4UL)        /* DPRPU (Bit 4) */
+#define RUSB2_SYSCFG_DPRPU_Msk          (0x10UL)     /* DPRPU (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_DMRPU_Pos          (3UL)        /* DMRPU (Bit 3) */
+#define RUSB2_SYSCFG_DMRPU_Msk          (0x8UL)      /* DMRPU (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_USBE_Pos           (0UL)        /* USBE (Bit 0) */
+#define RUSB2_SYSCFG_USBE_Msk           (0x1UL)      /* USBE (Bitfield-Mask: 0x01) */
 
 // BUSWAIT
-#define LINK_REG_BUSWAIT_BWAIT_Pos         (0UL)        /* BWAIT (Bit 0) */
-#define LINK_REG_BUSWAIT_BWAIT_Msk         (0xfUL)      /* BWAIT (Bitfield-Mask: 0x0f) */
+#define RUSB2_BUSWAIT_BWAIT_Pos         (0UL)        /* BWAIT (Bit 0) */
+#define RUSB2_BUSWAIT_BWAIT_Msk         (0xfUL)      /* BWAIT (Bitfield-Mask: 0x0f) */
 
 // SYSSTS0
-#define LINK_REG_SYSSTS0_OVCMON_Pos        (14UL)       /* OVCMON (Bit 14) */
-#define LINK_REG_SYSSTS0_OVCMON_Msk        (0xc000UL)   /* OVCMON (Bitfield-Mask: 0x03) */
-#define LINK_REG_SYSSTS0_HTACT_Pos         (6UL)        /* HTACT (Bit 6) */
-#define LINK_REG_SYSSTS0_HTACT_Msk         (0x40UL)     /* HTACT (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSSTS0_SOFEA_Pos         (5UL)        /* SOFEA (Bit 5) */
-#define LINK_REG_SYSSTS0_SOFEA_Msk         (0x20UL)     /* SOFEA (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSSTS0_IDMON_Pos         (2UL)        /* IDMON (Bit 2) */
-#define LINK_REG_SYSSTS0_IDMON_Msk         (0x4UL)      /* IDMON (Bitfield-Mask: 0x01) */
-#define LINK_REG_SYSSTS0_LNST_Pos          (0UL)        /* LNST (Bit 0) */
-#define LINK_REG_SYSSTS0_LNST_Msk          (0x3UL)      /* LNST (Bitfield-Mask: 0x03) */
+#define RUSB2_SYSSTS0_OVCMON_Pos        (14UL)       /* OVCMON (Bit 14) */
+#define RUSB2_SYSSTS0_OVCMON_Msk        (0xc000UL)   /* OVCMON (Bitfield-Mask: 0x03) */
+#define RUSB2_SYSSTS0_HTACT_Pos         (6UL)        /* HTACT (Bit 6) */
+#define RUSB2_SYSSTS0_HTACT_Msk         (0x40UL)     /* HTACT (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSSTS0_SOFEA_Pos         (5UL)        /* SOFEA (Bit 5) */
+#define RUSB2_SYSSTS0_SOFEA_Msk         (0x20UL)     /* SOFEA (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSSTS0_IDMON_Pos         (2UL)        /* IDMON (Bit 2) */
+#define RUSB2_SYSSTS0_IDMON_Msk         (0x4UL)      /* IDMON (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSSTS0_LNST_Pos          (0UL)        /* LNST (Bit 0) */
+#define RUSB2_SYSSTS0_LNST_Msk          (0x3UL)      /* LNST (Bitfield-Mask: 0x03) */
 
 // PLLSTA
-#define LINK_REG_PLLSTA_PLLLOCK_Pos        (0UL)        /* PLLLOCK (Bit 0) */
-#define LINK_REG_PLLSTA_PLLLOCK_Msk        (0x1UL)      /* PLLLOCK (Bitfield-Mask: 0x01) */
+#define RUSB2_PLLSTA_PLLLOCK_Pos        (0UL)        /* PLLLOCK (Bit 0) */
+#define RUSB2_PLLSTA_PLLLOCK_Msk        (0x1UL)      /* PLLLOCK (Bitfield-Mask: 0x01) */
 
 // DVSTCTR0
-#define LINK_REG_DVSTCTR0_HNPBTOA_Pos      (11UL)       /* HNPBTOA (Bit 11) */
-#define LINK_REG_DVSTCTR0_HNPBTOA_Msk      (0x800UL)    /* HNPBTOA (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_EXICEN_Pos       (10UL)       /* EXICEN (Bit 10) */
-#define LINK_REG_DVSTCTR0_EXICEN_Msk       (0x400UL)    /* EXICEN (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_VBUSEN_Pos       (9UL)        /* VBUSEN (Bit 9) */
-#define LINK_REG_DVSTCTR0_VBUSEN_Msk       (0x200UL)    /* VBUSEN (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_WKUP_Pos         (8UL)        /* WKUP (Bit 8) */
-#define LINK_REG_DVSTCTR0_WKUP_Msk         (0x100UL)    /* WKUP (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_RWUPE_Pos        (7UL)        /* RWUPE (Bit 7) */
-#define LINK_REG_DVSTCTR0_RWUPE_Msk        (0x80UL)     /* RWUPE (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_USBRST_Pos       (6UL)        /* USBRST (Bit 6) */
-#define LINK_REG_DVSTCTR0_USBRST_Msk       (0x40UL)     /* USBRST (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_RESUME_Pos       (5UL)        /* RESUME (Bit 5) */
-#define LINK_REG_DVSTCTR0_RESUME_Msk       (0x20UL)     /* RESUME (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_UACT_Pos         (4UL)        /* UACT (Bit 4) */
-#define LINK_REG_DVSTCTR0_UACT_Msk         (0x10UL)     /* UACT (Bitfield-Mask: 0x01) */
-#define LINK_REG_DVSTCTR0_RHST_Pos         (0UL)        /* RHST (Bit 0) */
-#define LINK_REG_DVSTCTR0_RHST_Msk         (0x7UL)      /* RHST (Bitfield-Mask: 0x07) */
+#define RUSB2_DVSTCTR0_HNPBTOA_Pos      (11UL)       /* HNPBTOA (Bit 11) */
+#define RUSB2_DVSTCTR0_HNPBTOA_Msk      (0x800UL)    /* HNPBTOA (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_EXICEN_Pos       (10UL)       /* EXICEN (Bit 10) */
+#define RUSB2_DVSTCTR0_EXICEN_Msk       (0x400UL)    /* EXICEN (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_VBUSEN_Pos       (9UL)        /* VBUSEN (Bit 9) */
+#define RUSB2_DVSTCTR0_VBUSEN_Msk       (0x200UL)    /* VBUSEN (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_WKUP_Pos         (8UL)        /* WKUP (Bit 8) */
+#define RUSB2_DVSTCTR0_WKUP_Msk         (0x100UL)    /* WKUP (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_RWUPE_Pos        (7UL)        /* RWUPE (Bit 7) */
+#define RUSB2_DVSTCTR0_RWUPE_Msk        (0x80UL)     /* RWUPE (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_USBRST_Pos       (6UL)        /* USBRST (Bit 6) */
+#define RUSB2_DVSTCTR0_USBRST_Msk       (0x40UL)     /* USBRST (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_RESUME_Pos       (5UL)        /* RESUME (Bit 5) */
+#define RUSB2_DVSTCTR0_RESUME_Msk       (0x20UL)     /* RESUME (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_UACT_Pos         (4UL)        /* UACT (Bit 4) */
+#define RUSB2_DVSTCTR0_UACT_Msk         (0x10UL)     /* UACT (Bitfield-Mask: 0x01) */
+#define RUSB2_DVSTCTR0_RHST_Pos         (0UL)        /* RHST (Bit 0) */
+#define RUSB2_DVSTCTR0_RHST_Msk         (0x7UL)      /* RHST (Bitfield-Mask: 0x07) */
 
 // TESTMODE
-#define LINK_REG_TESTMODE_UTST_Pos         (0UL)        /* UTST (Bit 0) */
-#define LINK_REG_TESTMODE_UTST_Msk         (0xfUL)      /* UTST (Bitfield-Mask: 0x0f) */
+#define RUSB2_TESTMODE_UTST_Pos         (0UL)        /* UTST (Bit 0) */
+#define RUSB2_TESTMODE_UTST_Msk         (0xfUL)      /* UTST (Bitfield-Mask: 0x0f) */
 
 // CFIFOSEL
-#define LINK_REG_CFIFOSEL_RCNT_Pos         (15UL)       /* RCNT (Bit 15) */
-#define LINK_REG_CFIFOSEL_RCNT_Msk         (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOSEL_REW_Pos          (14UL)       /* REW (Bit 14) */
-#define LINK_REG_CFIFOSEL_REW_Msk          (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOSEL_MBW_Pos          (10UL)       /* MBW (Bit 10) */
-#define LINK_REG_CFIFOSEL_MBW_Msk          (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
-#define LINK_REG_CFIFOSEL_BIGEND_Pos       (8UL)        /* BIGEND (Bit 8) */
-#define LINK_REG_CFIFOSEL_BIGEND_Msk       (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOSEL_ISEL_Pos         (5UL)        /* ISEL (Bit 5) */
-#define LINK_REG_CFIFOSEL_ISEL_Msk         (0x20UL)     /* ISEL (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOSEL_CURPIPE_Pos      (0UL)        /* CURPIPE (Bit 0) */
-#define LINK_REG_CFIFOSEL_CURPIPE_Msk      (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+#define RUSB2_CFIFOSEL_RCNT_Pos         (15UL)       /* RCNT (Bit 15) */
+#define RUSB2_CFIFOSEL_RCNT_Msk         (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOSEL_REW_Pos          (14UL)       /* REW (Bit 14) */
+#define RUSB2_CFIFOSEL_REW_Msk          (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOSEL_MBW_Pos          (10UL)       /* MBW (Bit 10) */
+#define RUSB2_CFIFOSEL_MBW_Msk          (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define RUSB2_CFIFOSEL_BIGEND_Pos       (8UL)        /* BIGEND (Bit 8) */
+#define RUSB2_CFIFOSEL_BIGEND_Msk       (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOSEL_ISEL_Pos         (5UL)        /* ISEL (Bit 5) */
+#define RUSB2_CFIFOSEL_ISEL_Msk         (0x20UL)     /* ISEL (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOSEL_CURPIPE_Pos      (0UL)        /* CURPIPE (Bit 0) */
+#define RUSB2_CFIFOSEL_CURPIPE_Msk      (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
 
 // CFIFOCTR
-#define LINK_REG_CFIFOCTR_BVAL_Pos         (15UL)       /* BVAL (Bit 15) */
-#define LINK_REG_CFIFOCTR_BVAL_Msk         (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOCTR_BCLR_Pos         (14UL)       /* BCLR (Bit 14) */
-#define LINK_REG_CFIFOCTR_BCLR_Msk         (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOCTR_FRDY_Pos         (13UL)       /* FRDY (Bit 13) */
-#define LINK_REG_CFIFOCTR_FRDY_Msk         (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
-#define LINK_REG_CFIFOCTR_DTLN_Pos         (0UL)        /* DTLN (Bit 0) */
-#define LINK_REG_CFIFOCTR_DTLN_Msk         (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+#define RUSB2_CFIFOCTR_BVAL_Pos         (15UL)       /* BVAL (Bit 15) */
+#define RUSB2_CFIFOCTR_BVAL_Msk         (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOCTR_BCLR_Pos         (14UL)       /* BCLR (Bit 14) */
+#define RUSB2_CFIFOCTR_BCLR_Msk         (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOCTR_FRDY_Pos         (13UL)       /* FRDY (Bit 13) */
+#define RUSB2_CFIFOCTR_FRDY_Msk         (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_CFIFOCTR_DTLN_Pos         (0UL)        /* DTLN (Bit 0) */
+#define RUSB2_CFIFOCTR_DTLN_Msk         (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
 
 // D0FIFOSEL
-#define LINK_REG_D0FIFOSEL_RCNT_Pos        (15UL)       /* RCNT (Bit 15) */
-#define LINK_REG_D0FIFOSEL_RCNT_Msk        (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOSEL_REW_Pos         (14UL)       /* REW (Bit 14) */
-#define LINK_REG_D0FIFOSEL_REW_Msk         (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOSEL_DCLRM_Pos       (13UL)       /* DCLRM (Bit 13) */
-#define LINK_REG_D0FIFOSEL_DCLRM_Msk       (0x2000UL)   /* DCLRM (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOSEL_DREQE_Pos       (12UL)       /* DREQE (Bit 12) */
-#define LINK_REG_D0FIFOSEL_DREQE_Msk       (0x1000UL)   /* DREQE (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOSEL_MBW_Pos         (10UL)       /* MBW (Bit 10) */
-#define LINK_REG_D0FIFOSEL_MBW_Msk         (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
-#define LINK_REG_D0FIFOSEL_BIGEND_Pos      (8UL)        /* BIGEND (Bit 8) */
-#define LINK_REG_D0FIFOSEL_BIGEND_Msk      (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOSEL_CURPIPE_Pos     (0UL)        /* CURPIPE (Bit 0) */
-#define LINK_REG_D0FIFOSEL_CURPIPE_Msk     (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+#define RUSB2_D0FIFOSEL_RCNT_Pos        (15UL)       /* RCNT (Bit 15) */
+#define RUSB2_D0FIFOSEL_RCNT_Msk        (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOSEL_REW_Pos         (14UL)       /* REW (Bit 14) */
+#define RUSB2_D0FIFOSEL_REW_Msk         (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOSEL_DCLRM_Pos       (13UL)       /* DCLRM (Bit 13) */
+#define RUSB2_D0FIFOSEL_DCLRM_Msk       (0x2000UL)   /* DCLRM (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOSEL_DREQE_Pos       (12UL)       /* DREQE (Bit 12) */
+#define RUSB2_D0FIFOSEL_DREQE_Msk       (0x1000UL)   /* DREQE (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOSEL_MBW_Pos         (10UL)       /* MBW (Bit 10) */
+#define RUSB2_D0FIFOSEL_MBW_Msk         (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define RUSB2_D0FIFOSEL_BIGEND_Pos      (8UL)        /* BIGEND (Bit 8) */
+#define RUSB2_D0FIFOSEL_BIGEND_Msk      (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOSEL_CURPIPE_Pos     (0UL)        /* CURPIPE (Bit 0) */
+#define RUSB2_D0FIFOSEL_CURPIPE_Msk     (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
 
 // D0FIFOCTR
-#define LINK_REG_D0FIFOCTR_BVAL_Pos        (15UL)       /* BVAL (Bit 15) */
-#define LINK_REG_D0FIFOCTR_BVAL_Msk        (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOCTR_BCLR_Pos        (14UL)       /* BCLR (Bit 14) */
-#define LINK_REG_D0FIFOCTR_BCLR_Msk        (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOCTR_FRDY_Pos        (13UL)       /* FRDY (Bit 13) */
-#define LINK_REG_D0FIFOCTR_FRDY_Msk        (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
-#define LINK_REG_D0FIFOCTR_DTLN_Pos        (0UL)        /* DTLN (Bit 0) */
-#define LINK_REG_D0FIFOCTR_DTLN_Msk        (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+#define RUSB2_D0FIFOCTR_BVAL_Pos        (15UL)       /* BVAL (Bit 15) */
+#define RUSB2_D0FIFOCTR_BVAL_Msk        (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOCTR_BCLR_Pos        (14UL)       /* BCLR (Bit 14) */
+#define RUSB2_D0FIFOCTR_BCLR_Msk        (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOCTR_FRDY_Pos        (13UL)       /* FRDY (Bit 13) */
+#define RUSB2_D0FIFOCTR_FRDY_Msk        (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_D0FIFOCTR_DTLN_Pos        (0UL)        /* DTLN (Bit 0) */
+#define RUSB2_D0FIFOCTR_DTLN_Msk        (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
 
 // D1FIFOSEL
-#define LINK_REG_D1FIFOSEL_RCNT_Pos        (15UL)       /* RCNT (Bit 15) */
-#define LINK_REG_D1FIFOSEL_RCNT_Msk        (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOSEL_REW_Pos         (14UL)       /* REW (Bit 14) */
-#define LINK_REG_D1FIFOSEL_REW_Msk         (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOSEL_DCLRM_Pos       (13UL)       /* DCLRM (Bit 13) */
-#define LINK_REG_D1FIFOSEL_DCLRM_Msk       (0x2000UL)   /* DCLRM (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOSEL_DREQE_Pos       (12UL)       /* DREQE (Bit 12) */
-#define LINK_REG_D1FIFOSEL_DREQE_Msk       (0x1000UL)   /* DREQE (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOSEL_MBW_Pos         (10UL)       /* MBW (Bit 10) */
-#define LINK_REG_D1FIFOSEL_MBW_Msk         (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
-#define LINK_REG_D1FIFOSEL_BIGEND_Pos      (8UL)        /* BIGEND (Bit 8) */
-#define LINK_REG_D1FIFOSEL_BIGEND_Msk      (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOSEL_CURPIPE_Pos     (0UL)        /* CURPIPE (Bit 0) */
-#define LINK_REG_D1FIFOSEL_CURPIPE_Msk     (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
+#define RUSB2_D1FIFOSEL_RCNT_Pos        (15UL)       /* RCNT (Bit 15) */
+#define RUSB2_D1FIFOSEL_RCNT_Msk        (0x8000UL)   /* RCNT (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOSEL_REW_Pos         (14UL)       /* REW (Bit 14) */
+#define RUSB2_D1FIFOSEL_REW_Msk         (0x4000UL)   /* REW (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOSEL_DCLRM_Pos       (13UL)       /* DCLRM (Bit 13) */
+#define RUSB2_D1FIFOSEL_DCLRM_Msk       (0x2000UL)   /* DCLRM (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOSEL_DREQE_Pos       (12UL)       /* DREQE (Bit 12) */
+#define RUSB2_D1FIFOSEL_DREQE_Msk       (0x1000UL)   /* DREQE (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOSEL_MBW_Pos         (10UL)       /* MBW (Bit 10) */
+#define RUSB2_D1FIFOSEL_MBW_Msk         (0xc00UL)    /* MBW (Bitfield-Mask: 0x03) */
+#define RUSB2_D1FIFOSEL_BIGEND_Pos      (8UL)        /* BIGEND (Bit 8) */
+#define RUSB2_D1FIFOSEL_BIGEND_Msk      (0x100UL)    /* BIGEND (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOSEL_CURPIPE_Pos     (0UL)        /* CURPIPE (Bit 0) */
+#define RUSB2_D1FIFOSEL_CURPIPE_Msk     (0xfUL)      /* CURPIPE (Bitfield-Mask: 0x0f) */
 
 // D1FIFOCTR
-#define LINK_REG_D1FIFOCTR_BVAL_Pos        (15UL)       /* BVAL (Bit 15) */
-#define LINK_REG_D1FIFOCTR_BVAL_Msk        (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOCTR_BCLR_Pos        (14UL)       /* BCLR (Bit 14) */
-#define LINK_REG_D1FIFOCTR_BCLR_Msk        (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOCTR_FRDY_Pos        (13UL)       /* FRDY (Bit 13) */
-#define LINK_REG_D1FIFOCTR_FRDY_Msk        (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
-#define LINK_REG_D1FIFOCTR_DTLN_Pos        (0UL)        /* DTLN (Bit 0) */
-#define LINK_REG_D1FIFOCTR_DTLN_Msk        (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
+#define RUSB2_D1FIFOCTR_BVAL_Pos        (15UL)       /* BVAL (Bit 15) */
+#define RUSB2_D1FIFOCTR_BVAL_Msk        (0x8000UL)   /* BVAL (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOCTR_BCLR_Pos        (14UL)       /* BCLR (Bit 14) */
+#define RUSB2_D1FIFOCTR_BCLR_Msk        (0x4000UL)   /* BCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOCTR_FRDY_Pos        (13UL)       /* FRDY (Bit 13) */
+#define RUSB2_D1FIFOCTR_FRDY_Msk        (0x2000UL)   /* FRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_D1FIFOCTR_DTLN_Pos        (0UL)        /* DTLN (Bit 0) */
+#define RUSB2_D1FIFOCTR_DTLN_Msk        (0xfffUL)    /* DTLN (Bitfield-Mask: 0xfff) */
 
 // INTENB0
-#define LINK_REG_INTENB0_VBSE_Pos          (15UL)       /* VBSE (Bit 15) */
-#define LINK_REG_INTENB0_VBSE_Msk          (0x8000UL)   /* VBSE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_RSME_Pos          (14UL)       /* RSME (Bit 14) */
-#define LINK_REG_INTENB0_RSME_Msk          (0x4000UL)   /* RSME (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_SOFE_Pos          (13UL)       /* SOFE (Bit 13) */
-#define LINK_REG_INTENB0_SOFE_Msk          (0x2000UL)   /* SOFE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_DVSE_Pos          (12UL)       /* DVSE (Bit 12) */
-#define LINK_REG_INTENB0_DVSE_Msk          (0x1000UL)   /* DVSE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_CTRE_Pos          (11UL)       /* CTRE (Bit 11) */
-#define LINK_REG_INTENB0_CTRE_Msk          (0x800UL)    /* CTRE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_BEMPE_Pos         (10UL)       /* BEMPE (Bit 10) */
-#define LINK_REG_INTENB0_BEMPE_Msk         (0x400UL)    /* BEMPE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_NRDYE_Pos         (9UL)        /* NRDYE (Bit 9) */
-#define LINK_REG_INTENB0_NRDYE_Msk         (0x200UL)    /* NRDYE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB0_BRDYE_Pos         (8UL)        /* BRDYE (Bit 8) */
-#define LINK_REG_INTENB0_BRDYE_Msk         (0x100UL)    /* BRDYE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_VBSE_Pos          (15UL)       /* VBSE (Bit 15) */
+#define RUSB2_INTENB0_VBSE_Msk          (0x8000UL)   /* VBSE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_RSME_Pos          (14UL)       /* RSME (Bit 14) */
+#define RUSB2_INTENB0_RSME_Msk          (0x4000UL)   /* RSME (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_SOFE_Pos          (13UL)       /* SOFE (Bit 13) */
+#define RUSB2_INTENB0_SOFE_Msk          (0x2000UL)   /* SOFE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_DVSE_Pos          (12UL)       /* DVSE (Bit 12) */
+#define RUSB2_INTENB0_DVSE_Msk          (0x1000UL)   /* DVSE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_CTRE_Pos          (11UL)       /* CTRE (Bit 11) */
+#define RUSB2_INTENB0_CTRE_Msk          (0x800UL)    /* CTRE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_BEMPE_Pos         (10UL)       /* BEMPE (Bit 10) */
+#define RUSB2_INTENB0_BEMPE_Msk         (0x400UL)    /* BEMPE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_NRDYE_Pos         (9UL)        /* NRDYE (Bit 9) */
+#define RUSB2_INTENB0_NRDYE_Msk         (0x200UL)    /* NRDYE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB0_BRDYE_Pos         (8UL)        /* BRDYE (Bit 8) */
+#define RUSB2_INTENB0_BRDYE_Msk         (0x100UL)    /* BRDYE (Bitfield-Mask: 0x01) */
 
 // INTENB1
-#define LINK_REG_INTENB1_OVRCRE_Pos        (15UL)       /* OVRCRE (Bit 15) */
-#define LINK_REG_INTENB1_OVRCRE_Msk        (0x8000UL)   /* OVRCRE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_BCHGE_Pos         (14UL)       /* BCHGE (Bit 14) */
-#define LINK_REG_INTENB1_BCHGE_Msk         (0x4000UL)   /* BCHGE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_DTCHE_Pos         (12UL)       /* DTCHE (Bit 12) */
-#define LINK_REG_INTENB1_DTCHE_Msk         (0x1000UL)   /* DTCHE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_ATTCHE_Pos        (11UL)       /* ATTCHE (Bit 11) */
-#define LINK_REG_INTENB1_ATTCHE_Msk        (0x800UL)    /* ATTCHE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_EOFERRE_Pos       (6UL)        /* EOFERRE (Bit 6) */
-#define LINK_REG_INTENB1_EOFERRE_Msk       (0x40UL)     /* EOFERRE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_SIGNE_Pos         (5UL)        /* SIGNE (Bit 5) */
-#define LINK_REG_INTENB1_SIGNE_Msk         (0x20UL)     /* SIGNE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_SACKE_Pos         (4UL)        /* SACKE (Bit 4) */
-#define LINK_REG_INTENB1_SACKE_Msk         (0x10UL)     /* SACKE (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTENB1_PDDETINTE0_Pos    (0UL)        /* PDDETINTE0 (Bit 0) */
-#define LINK_REG_INTENB1_PDDETINTE0_Msk    (0x1UL)      /* PDDETINTE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_OVRCRE_Pos        (15UL)       /* OVRCRE (Bit 15) */
+#define RUSB2_INTENB1_OVRCRE_Msk        (0x8000UL)   /* OVRCRE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_BCHGE_Pos         (14UL)       /* BCHGE (Bit 14) */
+#define RUSB2_INTENB1_BCHGE_Msk         (0x4000UL)   /* BCHGE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_DTCHE_Pos         (12UL)       /* DTCHE (Bit 12) */
+#define RUSB2_INTENB1_DTCHE_Msk         (0x1000UL)   /* DTCHE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_ATTCHE_Pos        (11UL)       /* ATTCHE (Bit 11) */
+#define RUSB2_INTENB1_ATTCHE_Msk        (0x800UL)    /* ATTCHE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_EOFERRE_Pos       (6UL)        /* EOFERRE (Bit 6) */
+#define RUSB2_INTENB1_EOFERRE_Msk       (0x40UL)     /* EOFERRE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_SIGNE_Pos         (5UL)        /* SIGNE (Bit 5) */
+#define RUSB2_INTENB1_SIGNE_Msk         (0x20UL)     /* SIGNE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_SACKE_Pos         (4UL)        /* SACKE (Bit 4) */
+#define RUSB2_INTENB1_SACKE_Msk         (0x10UL)     /* SACKE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_PDDETINTE0_Pos    (0UL)        /* PDDETINTE0 (Bit 0) */
+#define RUSB2_INTENB1_PDDETINTE0_Msk    (0x1UL)      /* PDDETINTE0 (Bitfield-Mask: 0x01) */
 
 // BRDYENB
-#define LINK_REG_BRDYENB_PIPEBRDYE_Pos     (0UL)        /* PIPEBRDYE (Bit 0) */
-#define LINK_REG_BRDYENB_PIPEBRDYE_Msk     (0x1UL)      /* PIPEBRDYE (Bitfield-Mask: 0x01) */
+#define RUSB2_BRDYENB_PIPEBRDYE_Pos     (0UL)        /* PIPEBRDYE (Bit 0) */
+#define RUSB2_BRDYENB_PIPEBRDYE_Msk     (0x1UL)      /* PIPEBRDYE (Bitfield-Mask: 0x01) */
 
 // NRDYENB
-#define LINK_REG_NRDYENB_PIPENRDYE_Pos     (0UL)        /* PIPENRDYE (Bit 0) */
-#define LINK_REG_NRDYENB_PIPENRDYE_Msk     (0x1UL)      /* PIPENRDYE (Bitfield-Mask: 0x01) */
+#define RUSB2_NRDYENB_PIPENRDYE_Pos     (0UL)        /* PIPENRDYE (Bit 0) */
+#define RUSB2_NRDYENB_PIPENRDYE_Msk     (0x1UL)      /* PIPENRDYE (Bitfield-Mask: 0x01) */
 
 // BEMPENB
-#define LINK_REG_BEMPENB_PIPEBEMPE_Pos     (0UL)        /* PIPEBEMPE (Bit 0) */
-#define LINK_REG_BEMPENB_PIPEBEMPE_Msk     (0x1UL)      /* PIPEBEMPE (Bitfield-Mask: 0x01) */
+#define RUSB2_BEMPENB_PIPEBEMPE_Pos     (0UL)        /* PIPEBEMPE (Bit 0) */
+#define RUSB2_BEMPENB_PIPEBEMPE_Msk     (0x1UL)      /* PIPEBEMPE (Bitfield-Mask: 0x01) */
 
 // SOFCFG
-#define LINK_REG_SOFCFG_TRNENSEL_Pos       (8UL)        /* TRNENSEL (Bit 8) */
-#define LINK_REG_SOFCFG_TRNENSEL_Msk       (0x100UL)    /* TRNENSEL (Bitfield-Mask: 0x01) */
-#define LINK_REG_SOFCFG_BRDYM_Pos          (6UL)        /* BRDYM (Bit 6) */
-#define LINK_REG_SOFCFG_BRDYM_Msk          (0x40UL)     /* BRDYM (Bitfield-Mask: 0x01) */
-#define LINK_REG_SOFCFG_INTL_Pos           (5UL)        /* INTL (Bit 5) */
-#define LINK_REG_SOFCFG_INTL_Msk           (0x20UL)     /* INTL (Bitfield-Mask: 0x01) */
-#define LINK_REG_SOFCFG_EDGESTS_Pos        (4UL)        /* EDGESTS (Bit 4) */
-#define LINK_REG_SOFCFG_EDGESTS_Msk        (0x10UL)     /* EDGESTS (Bitfield-Mask: 0x01) */
+#define RUSB2_SOFCFG_TRNENSEL_Pos       (8UL)        /* TRNENSEL (Bit 8) */
+#define RUSB2_SOFCFG_TRNENSEL_Msk       (0x100UL)    /* TRNENSEL (Bitfield-Mask: 0x01) */
+#define RUSB2_SOFCFG_BRDYM_Pos          (6UL)        /* BRDYM (Bit 6) */
+#define RUSB2_SOFCFG_BRDYM_Msk          (0x40UL)     /* BRDYM (Bitfield-Mask: 0x01) */
+#define RUSB2_SOFCFG_INTL_Pos           (5UL)        /* INTL (Bit 5) */
+#define RUSB2_SOFCFG_INTL_Msk           (0x20UL)     /* INTL (Bitfield-Mask: 0x01) */
+#define RUSB2_SOFCFG_EDGESTS_Pos        (4UL)        /* EDGESTS (Bit 4) */
+#define RUSB2_SOFCFG_EDGESTS_Msk        (0x10UL)     /* EDGESTS (Bitfield-Mask: 0x01) */
 
 // PHYSET
-#define LINK_REG_PHYSET_HSEB_Pos           (15UL)       /* HSEB (Bit 15) */
-#define LINK_REG_PHYSET_HSEB_Msk           (0x8000UL)   /* HSEB (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSET_REPSTART_Pos       (11UL)       /* REPSTART (Bit 11) */
-#define LINK_REG_PHYSET_REPSTART_Msk       (0x800UL)    /* REPSTART (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSET_REPSEL_Pos         (8UL)        /* REPSEL (Bit 8) */
-#define LINK_REG_PHYSET_REPSEL_Msk         (0x300UL)    /* REPSEL (Bitfield-Mask: 0x03) */
-#define LINK_REG_PHYSET_CLKSEL_Pos         (4UL)        /* CLKSEL (Bit 4) */
-#define LINK_REG_PHYSET_CLKSEL_Msk         (0x30UL)     /* CLKSEL (Bitfield-Mask: 0x03) */
-#define LINK_REG_PHYSET_CDPEN_Pos          (3UL)        /* CDPEN (Bit 3) */
-#define LINK_REG_PHYSET_CDPEN_Msk          (0x8UL)      /* CDPEN (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSET_PLLRESET_Pos       (1UL)        /* PLLRESET (Bit 1) */
-#define LINK_REG_PHYSET_PLLRESET_Msk       (0x2UL)      /* PLLRESET (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSET_DIRPD_Pos          (0UL)        /* DIRPD (Bit 0) */
-#define LINK_REG_PHYSET_DIRPD_Msk          (0x1UL)      /* DIRPD (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSET_HSEB_Pos           (15UL)       /* HSEB (Bit 15) */
+#define RUSB2_PHYSET_HSEB_Msk           (0x8000UL)   /* HSEB (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSET_REPSTART_Pos       (11UL)       /* REPSTART (Bit 11) */
+#define RUSB2_PHYSET_REPSTART_Msk       (0x800UL)    /* REPSTART (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSET_REPSEL_Pos         (8UL)        /* REPSEL (Bit 8) */
+#define RUSB2_PHYSET_REPSEL_Msk         (0x300UL)    /* REPSEL (Bitfield-Mask: 0x03) */
+#define RUSB2_PHYSET_CLKSEL_Pos         (4UL)        /* CLKSEL (Bit 4) */
+#define RUSB2_PHYSET_CLKSEL_Msk         (0x30UL)     /* CLKSEL (Bitfield-Mask: 0x03) */
+#define RUSB2_PHYSET_CDPEN_Pos          (3UL)        /* CDPEN (Bit 3) */
+#define RUSB2_PHYSET_CDPEN_Msk          (0x8UL)      /* CDPEN (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSET_PLLRESET_Pos       (1UL)        /* PLLRESET (Bit 1) */
+#define RUSB2_PHYSET_PLLRESET_Msk       (0x2UL)      /* PLLRESET (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSET_DIRPD_Pos          (0UL)        /* DIRPD (Bit 0) */
+#define RUSB2_PHYSET_DIRPD_Msk          (0x1UL)      /* DIRPD (Bitfield-Mask: 0x01) */
 
 // INTSTS0
-#define LINK_REG_INTSTS0_VBINT_Pos         (15UL)       /* VBINT (Bit 15) */
-#define LINK_REG_INTSTS0_VBINT_Msk         (0x8000UL)   /* VBINT (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_RESM_Pos          (14UL)       /* RESM (Bit 14) */
-#define LINK_REG_INTSTS0_RESM_Msk          (0x4000UL)   /* RESM (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_SOFR_Pos          (13UL)       /* SOFR (Bit 13) */
-#define LINK_REG_INTSTS0_SOFR_Msk          (0x2000UL)   /* SOFR (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_DVST_Pos          (12UL)       /* DVST (Bit 12) */
-#define LINK_REG_INTSTS0_DVST_Msk          (0x1000UL)   /* DVST (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_CTRT_Pos          (11UL)       /* CTRT (Bit 11) */
-#define LINK_REG_INTSTS0_CTRT_Msk          (0x800UL)    /* CTRT (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_BEMP_Pos          (10UL)       /* BEMP (Bit 10) */
-#define LINK_REG_INTSTS0_BEMP_Msk          (0x400UL)    /* BEMP (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_NRDY_Pos          (9UL)        /* NRDY (Bit 9) */
-#define LINK_REG_INTSTS0_NRDY_Msk          (0x200UL)    /* NRDY (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_BRDY_Pos          (8UL)        /* BRDY (Bit 8) */
-#define LINK_REG_INTSTS0_BRDY_Msk          (0x100UL)    /* BRDY (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_VBSTS_Pos         (7UL)        /* VBSTS (Bit 7) */
-#define LINK_REG_INTSTS0_VBSTS_Msk         (0x80UL)     /* VBSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_DVSQ_Pos          (4UL)        /* DVSQ (Bit 4) */
-#define LINK_REG_INTSTS0_DVSQ_Msk          (0x70UL)     /* DVSQ (Bitfield-Mask: 0x07) */
-#define LINK_REG_INTSTS0_VALID_Pos         (3UL)        /* VALID (Bit 3) */
-#define LINK_REG_INTSTS0_VALID_Msk         (0x8UL)      /* VALID (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS0_CTSQ_Pos          (0UL)        /* CTSQ (Bit 0) */
-#define LINK_REG_INTSTS0_CTSQ_Msk          (0x7UL)      /* CTSQ (Bitfield-Mask: 0x07) */
+#define RUSB2_INTSTS0_VBINT_Pos         (15UL)       /* VBINT (Bit 15) */
+#define RUSB2_INTSTS0_VBINT_Msk         (0x8000UL)   /* VBINT (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_RESM_Pos          (14UL)       /* RESM (Bit 14) */
+#define RUSB2_INTSTS0_RESM_Msk          (0x4000UL)   /* RESM (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_SOFR_Pos          (13UL)       /* SOFR (Bit 13) */
+#define RUSB2_INTSTS0_SOFR_Msk          (0x2000UL)   /* SOFR (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_DVST_Pos          (12UL)       /* DVST (Bit 12) */
+#define RUSB2_INTSTS0_DVST_Msk          (0x1000UL)   /* DVST (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_CTRT_Pos          (11UL)       /* CTRT (Bit 11) */
+#define RUSB2_INTSTS0_CTRT_Msk          (0x800UL)    /* CTRT (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_BEMP_Pos          (10UL)       /* BEMP (Bit 10) */
+#define RUSB2_INTSTS0_BEMP_Msk          (0x400UL)    /* BEMP (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_NRDY_Pos          (9UL)        /* NRDY (Bit 9) */
+#define RUSB2_INTSTS0_NRDY_Msk          (0x200UL)    /* NRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_BRDY_Pos          (8UL)        /* BRDY (Bit 8) */
+#define RUSB2_INTSTS0_BRDY_Msk          (0x100UL)    /* BRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_VBSTS_Pos         (7UL)        /* VBSTS (Bit 7) */
+#define RUSB2_INTSTS0_VBSTS_Msk         (0x80UL)     /* VBSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_DVSQ_Pos          (4UL)        /* DVSQ (Bit 4) */
+#define RUSB2_INTSTS0_DVSQ_Msk          (0x70UL)     /* DVSQ (Bitfield-Mask: 0x07) */
+#define RUSB2_INTSTS0_VALID_Pos         (3UL)        /* VALID (Bit 3) */
+#define RUSB2_INTSTS0_VALID_Msk         (0x8UL)      /* VALID (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS0_CTSQ_Pos          (0UL)        /* CTSQ (Bit 0) */
+#define RUSB2_INTSTS0_CTSQ_Msk          (0x7UL)      /* CTSQ (Bitfield-Mask: 0x07) */
 
 // INTSTS1
-#define LINK_REG_INTSTS1_OVRCR_Pos         (15UL)       /* OVRCR (Bit 15) */
-#define LINK_REG_INTSTS1_OVRCR_Msk         (0x8000UL)   /* OVRCR (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_BCHG_Pos          (14UL)       /* BCHG (Bit 14) */
-#define LINK_REG_INTSTS1_BCHG_Msk          (0x4000UL)   /* BCHG (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_DTCH_Pos          (12UL)       /* DTCH (Bit 12) */
-#define LINK_REG_INTSTS1_DTCH_Msk          (0x1000UL)   /* DTCH (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_ATTCH_Pos         (11UL)       /* ATTCH (Bit 11) */
-#define LINK_REG_INTSTS1_ATTCH_Msk         (0x800UL)    /* ATTCH (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_L1RSMEND_Pos      (9UL)        /* L1RSMEND (Bit 9) */
-#define LINK_REG_INTSTS1_L1RSMEND_Msk      (0x200UL)    /* L1RSMEND (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_LPMEND_Pos        (8UL)        /* LPMEND (Bit 8) */
-#define LINK_REG_INTSTS1_LPMEND_Msk        (0x100UL)    /* LPMEND (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_EOFERR_Pos        (6UL)        /* EOFERR (Bit 6) */
-#define LINK_REG_INTSTS1_EOFERR_Msk        (0x40UL)     /* EOFERR (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_SIGN_Pos          (5UL)        /* SIGN (Bit 5) */
-#define LINK_REG_INTSTS1_SIGN_Msk          (0x20UL)     /* SIGN (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_SACK_Pos          (4UL)        /* SACK (Bit 4) */
-#define LINK_REG_INTSTS1_SACK_Msk          (0x10UL)     /* SACK (Bitfield-Mask: 0x01) */
-#define LINK_REG_INTSTS1_PDDETINT0_Pos     (0UL)        /* PDDETINT0 (Bit 0) */
-#define LINK_REG_INTSTS1_PDDETINT0_Msk     (0x1UL)      /* PDDETINT0 (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_OVRCR_Pos         (15UL)       /* OVRCR (Bit 15) */
+#define RUSB2_INTSTS1_OVRCR_Msk         (0x8000UL)   /* OVRCR (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_BCHG_Pos          (14UL)       /* BCHG (Bit 14) */
+#define RUSB2_INTSTS1_BCHG_Msk          (0x4000UL)   /* BCHG (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_DTCH_Pos          (12UL)       /* DTCH (Bit 12) */
+#define RUSB2_INTSTS1_DTCH_Msk          (0x1000UL)   /* DTCH (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_ATTCH_Pos         (11UL)       /* ATTCH (Bit 11) */
+#define RUSB2_INTSTS1_ATTCH_Msk         (0x800UL)    /* ATTCH (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_L1RSMEND_Pos      (9UL)        /* L1RSMEND (Bit 9) */
+#define RUSB2_INTSTS1_L1RSMEND_Msk      (0x200UL)    /* L1RSMEND (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_LPMEND_Pos        (8UL)        /* LPMEND (Bit 8) */
+#define RUSB2_INTSTS1_LPMEND_Msk        (0x100UL)    /* LPMEND (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_EOFERR_Pos        (6UL)        /* EOFERR (Bit 6) */
+#define RUSB2_INTSTS1_EOFERR_Msk        (0x40UL)     /* EOFERR (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_SIGN_Pos          (5UL)        /* SIGN (Bit 5) */
+#define RUSB2_INTSTS1_SIGN_Msk          (0x20UL)     /* SIGN (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_SACK_Pos          (4UL)        /* SACK (Bit 4) */
+#define RUSB2_INTSTS1_SACK_Msk          (0x10UL)     /* SACK (Bitfield-Mask: 0x01) */
+#define RUSB2_INTSTS1_PDDETINT0_Pos     (0UL)        /* PDDETINT0 (Bit 0) */
+#define RUSB2_INTSTS1_PDDETINT0_Msk     (0x1UL)      /* PDDETINT0 (Bitfield-Mask: 0x01) */
 
 // BRDYSTS
-#define LINK_REG_BRDYSTS_PIPEBRDY_Pos      (0UL)        /* PIPEBRDY (Bit 0) */
-#define LINK_REG_BRDYSTS_PIPEBRDY_Msk      (0x1UL)      /* PIPEBRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_BRDYSTS_PIPEBRDY_Pos      (0UL)        /* PIPEBRDY (Bit 0) */
+#define RUSB2_BRDYSTS_PIPEBRDY_Msk      (0x1UL)      /* PIPEBRDY (Bitfield-Mask: 0x01) */
 
 // NRDYSTS
-#define LINK_REG_NRDYSTS_PIPENRDY_Pos      (0UL)        /* PIPENRDY (Bit 0) */
-#define LINK_REG_NRDYSTS_PIPENRDY_Msk      (0x1UL)      /* PIPENRDY (Bitfield-Mask: 0x01) */
+#define RUSB2_NRDYSTS_PIPENRDY_Pos      (0UL)        /* PIPENRDY (Bit 0) */
+#define RUSB2_NRDYSTS_PIPENRDY_Msk      (0x1UL)      /* PIPENRDY (Bitfield-Mask: 0x01) */
 
 // BEMPSTS
-#define LINK_REG_BEMPSTS_PIPEBEMP_Pos      (0UL)        /* PIPEBEMP (Bit 0) */
-#define LINK_REG_BEMPSTS_PIPEBEMP_Msk      (0x1UL)      /* PIPEBEMP (Bitfield-Mask: 0x01) */
+#define RUSB2_BEMPSTS_PIPEBEMP_Pos      (0UL)        /* PIPEBEMP (Bit 0) */
+#define RUSB2_BEMPSTS_PIPEBEMP_Msk      (0x1UL)      /* PIPEBEMP (Bitfield-Mask: 0x01) */
 
 // FRMNUM
-#define LINK_REG_FRMNUM_OVRN_Pos           (15UL)       /* OVRN (Bit 15) */
-#define LINK_REG_FRMNUM_OVRN_Msk           (0x8000UL)   /* OVRN (Bitfield-Mask: 0x01) */
-#define LINK_REG_FRMNUM_CRCE_Pos           (14UL)       /* CRCE (Bit 14) */
-#define LINK_REG_FRMNUM_CRCE_Msk           (0x4000UL)   /* CRCE (Bitfield-Mask: 0x01) */
-#define LINK_REG_FRMNUM_FRNM_Pos           (0UL)        /* FRNM (Bit 0) */
-#define LINK_REG_FRMNUM_FRNM_Msk           (0x7ffUL)    /* FRNM (Bitfield-Mask: 0x7ff) */
+#define RUSB2_FRMNUM_OVRN_Pos           (15UL)       /* OVRN (Bit 15) */
+#define RUSB2_FRMNUM_OVRN_Msk           (0x8000UL)   /* OVRN (Bitfield-Mask: 0x01) */
+#define RUSB2_FRMNUM_CRCE_Pos           (14UL)       /* CRCE (Bit 14) */
+#define RUSB2_FRMNUM_CRCE_Msk           (0x4000UL)   /* CRCE (Bitfield-Mask: 0x01) */
+#define RUSB2_FRMNUM_FRNM_Pos           (0UL)        /* FRNM (Bit 0) */
+#define RUSB2_FRMNUM_FRNM_Msk           (0x7ffUL)    /* FRNM (Bitfield-Mask: 0x7ff) */
 
 // UFRMNUM
-#define LINK_REG_UFRMNUM_DVCHG_Pos         (15UL)       /* DVCHG (Bit 15) */
-#define LINK_REG_UFRMNUM_DVCHG_Msk         (0x8000UL)   /* DVCHG (Bitfield-Mask: 0x01) */
-#define LINK_REG_UFRMNUM_UFRNM_Pos         (0UL)        /* UFRNM (Bit 0) */
-#define LINK_REG_UFRMNUM_UFRNM_Msk         (0x7UL)      /* UFRNM (Bitfield-Mask: 0x07) */
+#define RUSB2_UFRMNUM_DVCHG_Pos         (15UL)       /* DVCHG (Bit 15) */
+#define RUSB2_UFRMNUM_DVCHG_Msk         (0x8000UL)   /* DVCHG (Bitfield-Mask: 0x01) */
+#define RUSB2_UFRMNUM_UFRNM_Pos         (0UL)        /* UFRNM (Bit 0) */
+#define RUSB2_UFRMNUM_UFRNM_Msk         (0x7UL)      /* UFRNM (Bitfield-Mask: 0x07) */
 
 // USBADDR
-#define LINK_REG_USBADDR_STSRECOV0_Pos     (8UL)        /* STSRECOV0 (Bit 8) */
-#define LINK_REG_USBADDR_STSRECOV0_Msk     (0x700UL)    /* STSRECOV0 (Bitfield-Mask: 0x07) */
-#define LINK_REG_USBADDR_USBADDR_Pos       (0UL)        /* USBADDR (Bit 0) */
-#define LINK_REG_USBADDR_USBADDR_Msk       (0x7fUL)     /* USBADDR (Bitfield-Mask: 0x7f) */
+#define RUSB2_USBADDR_STSRECOV0_Pos     (8UL)        /* STSRECOV0 (Bit 8) */
+#define RUSB2_USBADDR_STSRECOV0_Msk     (0x700UL)    /* STSRECOV0 (Bitfield-Mask: 0x07) */
+#define RUSB2_USBADDR_USBADDR_Pos       (0UL)        /* USBADDR (Bit 0) */
+#define RUSB2_USBADDR_USBADDR_Msk       (0x7fUL)     /* USBADDR (Bitfield-Mask: 0x7f) */
 
 // USBREQ
-#define LINK_REG_USBREQ_BREQUEST_Pos       (8UL)        /* BREQUEST (Bit 8) */
-#define LINK_REG_USBREQ_BREQUEST_Msk       (0xff00UL)   /* BREQUEST (Bitfield-Mask: 0xff) */
-#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos  (0UL)        /* BMREQUESTTYPE (Bit 0) */
-#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk  (0xffUL)     /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */
+#define RUSB2_USBREQ_BREQUEST_Pos       (8UL)        /* BREQUEST (Bit 8) */
+#define RUSB2_USBREQ_BREQUEST_Msk       (0xff00UL)   /* BREQUEST (Bitfield-Mask: 0xff) */
+#define RUSB2_USBREQ_BMREQUESTTYPE_Pos  (0UL)        /* BMREQUESTTYPE (Bit 0) */
+#define RUSB2_USBREQ_BMREQUESTTYPE_Msk  (0xffUL)     /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */
 
 // USBVAL
-#define LINK_REG_USBVAL_WVALUE_Pos         (0UL)        /* WVALUE (Bit 0) */
-#define LINK_REG_USBVAL_WVALUE_Msk         (0xffffUL)   /* WVALUE (Bitfield-Mask: 0xffff) */
+#define RUSB2_USBVAL_WVALUE_Pos         (0UL)        /* WVALUE (Bit 0) */
+#define RUSB2_USBVAL_WVALUE_Msk         (0xffffUL)   /* WVALUE (Bitfield-Mask: 0xffff) */
 
 // USBINDX
-#define LINK_REG_USBINDX_WINDEX_Pos        (0UL)        /* WINDEX (Bit 0) */
-#define LINK_REG_USBINDX_WINDEX_Msk        (0xffffUL)   /* WINDEX (Bitfield-Mask: 0xffff) */
+#define RUSB2_USBINDX_WINDEX_Pos        (0UL)        /* WINDEX (Bit 0) */
+#define RUSB2_USBINDX_WINDEX_Msk        (0xffffUL)   /* WINDEX (Bitfield-Mask: 0xffff) */
 
 // USBLENG
-#define LINK_REG_USBLENG_WLENGTH_Pos       (0UL)        /* WLENGTH (Bit 0) */
-#define LINK_REG_USBLENG_WLENGTH_Msk       (0xffffUL)   /* WLENGTH (Bitfield-Mask: 0xffff) */
+#define RUSB2_USBLENG_WLENGTH_Pos       (0UL)        /* WLENGTH (Bit 0) */
+#define RUSB2_USBLENG_WLENGTH_Msk       (0xffffUL)   /* WLENGTH (Bitfield-Mask: 0xffff) */
 
 // DCPCFG
-#define LINK_REG_DCPCFG_CNTMD_Pos          (8UL)        /* CNTMD (Bit 8) */
-#define LINK_REG_DCPCFG_CNTMD_Msk          (0x100UL)    /* CNTMD (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCFG_SHTNAK_Pos         (7UL)        /* SHTNAK (Bit 7) */
-#define LINK_REG_DCPCFG_SHTNAK_Msk         (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCFG_DIR_Pos            (4UL)        /* DIR (Bit 4) */
-#define LINK_REG_DCPCFG_DIR_Msk            (0x10UL)     /* DIR (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCFG_CNTMD_Pos          (8UL)        /* CNTMD (Bit 8) */
+#define RUSB2_DCPCFG_CNTMD_Msk          (0x100UL)    /* CNTMD (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCFG_SHTNAK_Pos         (7UL)        /* SHTNAK (Bit 7) */
+#define RUSB2_DCPCFG_SHTNAK_Msk         (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCFG_DIR_Pos            (4UL)        /* DIR (Bit 4) */
+#define RUSB2_DCPCFG_DIR_Msk            (0x10UL)     /* DIR (Bitfield-Mask: 0x01) */
 
 // DCPMAXP
-#define LINK_REG_DCPMAXP_DEVSEL_Pos        (12UL)       /* DEVSEL (Bit 12) */
-#define LINK_REG_DCPMAXP_DEVSEL_Msk        (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
-#define LINK_REG_DCPMAXP_MXPS_Pos          (0UL)        /* MXPS (Bit 0) */
-#define LINK_REG_DCPMAXP_MXPS_Msk          (0x7fUL)     /* MXPS (Bitfield-Mask: 0x7f) */
+#define RUSB2_DCPMAXP_DEVSEL_Pos        (12UL)       /* DEVSEL (Bit 12) */
+#define RUSB2_DCPMAXP_DEVSEL_Msk        (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
+#define RUSB2_DCPMAXP_MXPS_Pos          (0UL)        /* MXPS (Bit 0) */
+#define RUSB2_DCPMAXP_MXPS_Msk          (0x7fUL)     /* MXPS (Bitfield-Mask: 0x7f) */
 
 // DCPCTR
-#define LINK_REG_DCPCTR_BSTS_Pos           (15UL)       /* BSTS (Bit 15) */
-#define LINK_REG_DCPCTR_BSTS_Msk           (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_SUREQ_Pos          (14UL)       /* SUREQ (Bit 14) */
-#define LINK_REG_DCPCTR_SUREQ_Msk          (0x4000UL)   /* SUREQ (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_SUREQCLR_Pos       (11UL)       /* SUREQCLR (Bit 11) */
-#define LINK_REG_DCPCTR_SUREQCLR_Msk       (0x800UL)    /* SUREQCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_SQCLR_Pos          (8UL)        /* SQCLR (Bit 8) */
-#define LINK_REG_DCPCTR_SQCLR_Msk          (0x100UL)    /* SQCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_SQSET_Pos          (7UL)        /* SQSET (Bit 7) */
-#define LINK_REG_DCPCTR_SQSET_Msk          (0x80UL)     /* SQSET (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_SQMON_Pos          (6UL)        /* SQMON (Bit 6) */
-#define LINK_REG_DCPCTR_SQMON_Msk          (0x40UL)     /* SQMON (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_PBUSY_Pos          (5UL)        /* PBUSY (Bit 5) */
-#define LINK_REG_DCPCTR_PBUSY_Msk          (0x20UL)     /* PBUSY (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_CCPL_Pos           (2UL)        /* CCPL (Bit 2) */
-#define LINK_REG_DCPCTR_CCPL_Msk           (0x4UL)      /* CCPL (Bitfield-Mask: 0x01) */
-#define LINK_REG_DCPCTR_PID_Pos            (0UL)        /* PID (Bit 0) */
-#define LINK_REG_DCPCTR_PID_Msk            (0x3UL)      /* PID (Bitfield-Mask: 0x03) */
+#define RUSB2_DCPCTR_BSTS_Pos           (15UL)       /* BSTS (Bit 15) */
+#define RUSB2_DCPCTR_BSTS_Msk           (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_SUREQ_Pos          (14UL)       /* SUREQ (Bit 14) */
+#define RUSB2_DCPCTR_SUREQ_Msk          (0x4000UL)   /* SUREQ (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_SUREQCLR_Pos       (11UL)       /* SUREQCLR (Bit 11) */
+#define RUSB2_DCPCTR_SUREQCLR_Msk       (0x800UL)    /* SUREQCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_SQCLR_Pos          (8UL)        /* SQCLR (Bit 8) */
+#define RUSB2_DCPCTR_SQCLR_Msk          (0x100UL)    /* SQCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_SQSET_Pos          (7UL)        /* SQSET (Bit 7) */
+#define RUSB2_DCPCTR_SQSET_Msk          (0x80UL)     /* SQSET (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_SQMON_Pos          (6UL)        /* SQMON (Bit 6) */
+#define RUSB2_DCPCTR_SQMON_Msk          (0x40UL)     /* SQMON (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_PBUSY_Pos          (5UL)        /* PBUSY (Bit 5) */
+#define RUSB2_DCPCTR_PBUSY_Msk          (0x20UL)     /* PBUSY (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_CCPL_Pos           (2UL)        /* CCPL (Bit 2) */
+#define RUSB2_DCPCTR_CCPL_Msk           (0x4UL)      /* CCPL (Bitfield-Mask: 0x01) */
+#define RUSB2_DCPCTR_PID_Pos            (0UL)        /* PID (Bit 0) */
+#define RUSB2_DCPCTR_PID_Msk            (0x3UL)      /* PID (Bitfield-Mask: 0x03) */
 
 // PIPESEL
-#define LINK_REG_PIPESEL_PIPESEL_Pos       (0UL)        /* PIPESEL (Bit 0) */
-#define LINK_REG_PIPESEL_PIPESEL_Msk       (0xfUL)      /* PIPESEL (Bitfield-Mask: 0x0f) */
+#define RUSB2_PIPESEL_PIPESEL_Pos       (0UL)        /* PIPESEL (Bit 0) */
+#define RUSB2_PIPESEL_PIPESEL_Msk       (0xfUL)      /* PIPESEL (Bitfield-Mask: 0x0f) */
 
 // PIPECFG
-#define LINK_REG_PIPECFG_TYPE_Pos          (14UL)       /* TYPE (Bit 14) */
-#define LINK_REG_PIPECFG_TYPE_Msk          (0xc000UL)   /* TYPE (Bitfield-Mask: 0x03) */
-#define LINK_REG_PIPECFG_BFRE_Pos          (10UL)       /* BFRE (Bit 10) */
-#define LINK_REG_PIPECFG_BFRE_Msk          (0x400UL)    /* BFRE (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPECFG_DBLB_Pos          (9UL)        /* DBLB (Bit 9) */
-#define LINK_REG_PIPECFG_DBLB_Msk          (0x200UL)    /* DBLB (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPECFG_SHTNAK_Pos        (7UL)        /* SHTNAK (Bit 7) */
-#define LINK_REG_PIPECFG_SHTNAK_Msk        (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPECFG_DIR_Pos           (4UL)        /* DIR (Bit 4) */
-#define LINK_REG_PIPECFG_DIR_Msk           (0x10UL)     /* DIR (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPECFG_EPNUM_Pos         (0UL)        /* EPNUM (Bit 0) */
-#define LINK_REG_PIPECFG_EPNUM_Msk         (0xfUL)      /* EPNUM (Bitfield-Mask: 0x0f) */
+#define RUSB2_PIPECFG_TYPE_Pos          (14UL)       /* TYPE (Bit 14) */
+#define RUSB2_PIPECFG_TYPE_Msk          (0xc000UL)   /* TYPE (Bitfield-Mask: 0x03) */
+#define RUSB2_PIPECFG_BFRE_Pos          (10UL)       /* BFRE (Bit 10) */
+#define RUSB2_PIPECFG_BFRE_Msk          (0x400UL)    /* BFRE (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPECFG_DBLB_Pos          (9UL)        /* DBLB (Bit 9) */
+#define RUSB2_PIPECFG_DBLB_Msk          (0x200UL)    /* DBLB (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPECFG_SHTNAK_Pos        (7UL)        /* SHTNAK (Bit 7) */
+#define RUSB2_PIPECFG_SHTNAK_Msk        (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPECFG_DIR_Pos           (4UL)        /* DIR (Bit 4) */
+#define RUSB2_PIPECFG_DIR_Msk           (0x10UL)     /* DIR (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPECFG_EPNUM_Pos         (0UL)        /* EPNUM (Bit 0) */
+#define RUSB2_PIPECFG_EPNUM_Msk         (0xfUL)      /* EPNUM (Bitfield-Mask: 0x0f) */
 
 // PIPEMAXP
-#define LINK_REG_PIPEMAXP_DEVSEL_Pos       (12UL)       /* DEVSEL (Bit 12) */
-#define LINK_REG_PIPEMAXP_DEVSEL_Msk       (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
-#define LINK_REG_PIPEMAXP_MXPS_Pos         (0UL)        /* MXPS (Bit 0) */
-#define LINK_REG_PIPEMAXP_MXPS_Msk         (0x1ffUL)    /* MXPS (Bitfield-Mask: 0x1ff) */
+#define RUSB2_PIPEMAXP_DEVSEL_Pos       (12UL)       /* DEVSEL (Bit 12) */
+#define RUSB2_PIPEMAXP_DEVSEL_Msk       (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
+#define RUSB2_PIPEMAXP_MXPS_Pos         (0UL)        /* MXPS (Bit 0) */
+#define RUSB2_PIPEMAXP_MXPS_Msk         (0x1ffUL)    /* MXPS (Bitfield-Mask: 0x1ff) */
 
 // PIPEPERI
-#define LINK_REG_PIPEPERI_IFIS_Pos         (12UL)       /* IFIS (Bit 12) */
-#define LINK_REG_PIPEPERI_IFIS_Msk         (0x1000UL)   /* IFIS (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPEPERI_IITV_Pos         (0UL)        /* IITV (Bit 0) */
-#define LINK_REG_PIPEPERI_IITV_Msk         (0x7UL)      /* IITV (Bitfield-Mask: 0x07) */
+#define RUSB2_PIPEPERI_IFIS_Pos         (12UL)       /* IFIS (Bit 12) */
+#define RUSB2_PIPEPERI_IFIS_Msk         (0x1000UL)   /* IFIS (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPEPERI_IITV_Pos         (0UL)        /* IITV (Bit 0) */
+#define RUSB2_PIPEPERI_IITV_Msk         (0x7UL)      /* IITV (Bitfield-Mask: 0x07) */
 
 // PIPE_CTR
-#define LINK_REG_PIPE_CTR_BSTS_Pos         (15UL)       /* BSTS (Bit 15) */
-#define LINK_REG_PIPE_CTR_BSTS_Msk         (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_INBUFM_Pos       (14UL)       /* INBUFM (Bit 14) */
-#define LINK_REG_PIPE_CTR_INBUFM_Msk       (0x4000UL)   /* INBUFM (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_CSCLR_Pos        (13UL)       /* CSCLR (Bit 13) */
-#define LINK_REG_PIPE_CTR_CSCLR_Msk        (0x2000UL)   /* CSCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_CSSTS_Pos        (12UL)       /* CSSTS (Bit 12) */
-#define LINK_REG_PIPE_CTR_CSSTS_Msk        (0x1000UL)   /* CSSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_ATREPM_Pos       (10UL)       /* ATREPM (Bit 10) */
-#define LINK_REG_PIPE_CTR_ATREPM_Msk       (0x400UL)    /* ATREPM (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_ACLRM_Pos        (9UL)        /* ACLRM (Bit 9) */
-#define LINK_REG_PIPE_CTR_ACLRM_Msk        (0x200UL)    /* ACLRM (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_SQCLR_Pos        (8UL)        /* SQCLR (Bit 8) */
-#define LINK_REG_PIPE_CTR_SQCLR_Msk        (0x100UL)    /* SQCLR (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_SQSET_Pos        (7UL)        /* SQSET (Bit 7) */
-#define LINK_REG_PIPE_CTR_SQSET_Msk        (0x80UL)     /* SQSET (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_SQMON_Pos        (6UL)        /* SQMON (Bit 6) */
-#define LINK_REG_PIPE_CTR_SQMON_Msk        (0x40UL)     /* SQMON (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_PBUSY_Pos        (5UL)        /* PBUSY (Bit 5) */
-#define LINK_REG_PIPE_CTR_PBUSY_Msk        (0x20UL)     /* PBUSY (Bitfield-Mask: 0x01) */
-#define LINK_REG_PIPE_CTR_PID_Pos          (0UL)        /* PID (Bit 0) */
-#define LINK_REG_PIPE_CTR_PID_Msk          (0x3UL)      /* PID (Bitfield-Mask: 0x03) */
+#define RUSB2_PIPE_CTR_BSTS_Pos         (15UL)       /* BSTS (Bit 15) */
+#define RUSB2_PIPE_CTR_BSTS_Msk         (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_INBUFM_Pos       (14UL)       /* INBUFM (Bit 14) */
+#define RUSB2_PIPE_CTR_INBUFM_Msk       (0x4000UL)   /* INBUFM (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_CSCLR_Pos        (13UL)       /* CSCLR (Bit 13) */
+#define RUSB2_PIPE_CTR_CSCLR_Msk        (0x2000UL)   /* CSCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_CSSTS_Pos        (12UL)       /* CSSTS (Bit 12) */
+#define RUSB2_PIPE_CTR_CSSTS_Msk        (0x1000UL)   /* CSSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_ATREPM_Pos       (10UL)       /* ATREPM (Bit 10) */
+#define RUSB2_PIPE_CTR_ATREPM_Msk       (0x400UL)    /* ATREPM (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_ACLRM_Pos        (9UL)        /* ACLRM (Bit 9) */
+#define RUSB2_PIPE_CTR_ACLRM_Msk        (0x200UL)    /* ACLRM (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_SQCLR_Pos        (8UL)        /* SQCLR (Bit 8) */
+#define RUSB2_PIPE_CTR_SQCLR_Msk        (0x100UL)    /* SQCLR (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_SQSET_Pos        (7UL)        /* SQSET (Bit 7) */
+#define RUSB2_PIPE_CTR_SQSET_Msk        (0x80UL)     /* SQSET (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_SQMON_Pos        (6UL)        /* SQMON (Bit 6) */
+#define RUSB2_PIPE_CTR_SQMON_Msk        (0x40UL)     /* SQMON (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_PBUSY_Pos        (5UL)        /* PBUSY (Bit 5) */
+#define RUSB2_PIPE_CTR_PBUSY_Msk        (0x20UL)     /* PBUSY (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPE_CTR_PID_Pos          (0UL)        /* PID (Bit 0) */
+#define RUSB2_PIPE_CTR_PID_Msk          (0x3UL)      /* PID (Bitfield-Mask: 0x03) */
 
 // DEVADD
-#define LINK_REG_DEVADD_UPPHUB_Pos         (11UL)       /* UPPHUB (Bit 11) */
-#define LINK_REG_DEVADD_UPPHUB_Msk         (0x7800UL)   /* UPPHUB (Bitfield-Mask: 0x0f) */
-#define LINK_REG_DEVADD_HUBPORT_Pos        (8UL)        /* HUBPORT (Bit 8) */
-#define LINK_REG_DEVADD_HUBPORT_Msk        (0x700UL)    /* HUBPORT (Bitfield-Mask: 0x07) */
-#define LINK_REG_DEVADD_USBSPD_Pos         (6UL)        /* USBSPD (Bit 6) */
-#define LINK_REG_DEVADD_USBSPD_Msk         (0xc0UL)     /* USBSPD (Bitfield-Mask: 0x03) */
+#define RUSB2_DEVADD_UPPHUB_Pos         (11UL)       /* UPPHUB (Bit 11) */
+#define RUSB2_DEVADD_UPPHUB_Msk         (0x7800UL)   /* UPPHUB (Bitfield-Mask: 0x0f) */
+#define RUSB2_DEVADD_HUBPORT_Pos        (8UL)        /* HUBPORT (Bit 8) */
+#define RUSB2_DEVADD_HUBPORT_Msk        (0x700UL)    /* HUBPORT (Bitfield-Mask: 0x07) */
+#define RUSB2_DEVADD_USBSPD_Pos         (6UL)        /* USBSPD (Bit 6) */
+#define RUSB2_DEVADD_USBSPD_Msk         (0xc0UL)     /* USBSPD (Bitfield-Mask: 0x03) */
 
 // USBBCCTRL0
-#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos  (9UL)        /* PDDETSTS0 (Bit 9) */
-#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk  (0x200UL)    /* PDDETSTS0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL)        /* CHGDETSTS0 (Bit 8) */
-#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL)    /* CHGDETSTS0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_BATCHGE0_Pos   (7UL)        /* BATCHGE0 (Bit 7) */
-#define LINK_REG_USBBCCTRL0_BATCHGE0_Msk   (0x80UL)     /* BATCHGE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_VDMSRCE0_Pos   (5UL)        /* VDMSRCE0 (Bit 5) */
-#define LINK_REG_USBBCCTRL0_VDMSRCE0_Msk   (0x20UL)     /* VDMSRCE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_IDPSINKE0_Pos  (4UL)        /* IDPSINKE0 (Bit 4) */
-#define LINK_REG_USBBCCTRL0_IDPSINKE0_Msk  (0x10UL)     /* IDPSINKE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_VDPSRCE0_Pos   (3UL)        /* VDPSRCE0 (Bit 3) */
-#define LINK_REG_USBBCCTRL0_VDPSRCE0_Msk   (0x8UL)      /* VDPSRCE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_IDMSINKE0_Pos  (2UL)        /* IDMSINKE0 (Bit 2) */
-#define LINK_REG_USBBCCTRL0_IDMSINKE0_Msk  (0x4UL)      /* IDMSINKE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_IDPSRCE0_Pos   (1UL)        /* IDPSRCE0 (Bit 1) */
-#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk   (0x2UL)      /* IDPSRCE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBBCCTRL0_RPDME0_Pos     (0UL)        /* RPDME0 (Bit 0) */
-#define LINK_REG_USBBCCTRL0_RPDME0_Msk     (0x1UL)      /* RPDME0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_PDDETSTS0_Pos  (9UL)        /* PDDETSTS0 (Bit 9) */
+#define RUSB2_USBBCCTRL0_PDDETSTS0_Msk  (0x200UL)    /* PDDETSTS0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_CHGDETSTS0_Pos (8UL)        /* CHGDETSTS0 (Bit 8) */
+#define RUSB2_USBBCCTRL0_CHGDETSTS0_Msk (0x100UL)    /* CHGDETSTS0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_BATCHGE0_Pos   (7UL)        /* BATCHGE0 (Bit 7) */
+#define RUSB2_USBBCCTRL0_BATCHGE0_Msk   (0x80UL)     /* BATCHGE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_VDMSRCE0_Pos   (5UL)        /* VDMSRCE0 (Bit 5) */
+#define RUSB2_USBBCCTRL0_VDMSRCE0_Msk   (0x20UL)     /* VDMSRCE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_IDPSINKE0_Pos  (4UL)        /* IDPSINKE0 (Bit 4) */
+#define RUSB2_USBBCCTRL0_IDPSINKE0_Msk  (0x10UL)     /* IDPSINKE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_VDPSRCE0_Pos   (3UL)        /* VDPSRCE0 (Bit 3) */
+#define RUSB2_USBBCCTRL0_VDPSRCE0_Msk   (0x8UL)      /* VDPSRCE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_IDMSINKE0_Pos  (2UL)        /* IDMSINKE0 (Bit 2) */
+#define RUSB2_USBBCCTRL0_IDMSINKE0_Msk  (0x4UL)      /* IDMSINKE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_IDPSRCE0_Pos   (1UL)        /* IDPSRCE0 (Bit 1) */
+#define RUSB2_USBBCCTRL0_IDPSRCE0_Msk   (0x2UL)      /* IDPSRCE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_USBBCCTRL0_RPDME0_Pos     (0UL)        /* RPDME0 (Bit 0) */
+#define RUSB2_USBBCCTRL0_RPDME0_Msk     (0x1UL)      /* RPDME0 (Bitfield-Mask: 0x01) */
 
 // UCKSEL
-#define LINK_REG_UCKSEL_UCKSELC_Pos        (0UL)        /* UCKSELC (Bit 0) */
-#define LINK_REG_UCKSEL_UCKSELC_Msk        (0x1UL)      /* UCKSELC (Bitfield-Mask: 0x01) */
+#define RUSB2_UCKSEL_UCKSELC_Pos        (0UL)        /* UCKSELC (Bit 0) */
+#define RUSB2_UCKSEL_UCKSELC_Msk        (0x1UL)      /* UCKSELC (Bitfield-Mask: 0x01) */
 
 // USBMC
-#define LINK_REG_USBMC_VDCEN_Pos           (7UL)        /* VDCEN (Bit 7) */
-#define LINK_REG_USBMC_VDCEN_Msk           (0x80UL)     /* VDCEN (Bitfield-Mask: 0x01) */
-#define LINK_REG_USBMC_VDDUSBE_Pos         (0UL)        /* VDDUSBE (Bit 0) */
-#define LINK_REG_USBMC_VDDUSBE_Msk         (0x1UL)      /* VDDUSBE (Bitfield-Mask: 0x01) */
+#define RUSB2_USBMC_VDCEN_Pos           (7UL)        /* VDCEN (Bit 7) */
+#define RUSB2_USBMC_VDCEN_Msk           (0x80UL)     /* VDCEN (Bitfield-Mask: 0x01) */
+#define RUSB2_USBMC_VDDUSBE_Pos         (0UL)        /* VDDUSBE (Bit 0) */
+#define RUSB2_USBMC_VDDUSBE_Msk         (0x1UL)      /* VDDUSBE (Bitfield-Mask: 0x01) */
 
 // PHYSLEW
-#define LINK_REG_PHYSLEW_SLEWF01_Pos       (3UL)        /* SLEWF01 (Bit 3) */
-#define LINK_REG_PHYSLEW_SLEWF01_Msk       (0x8UL)      /* SLEWF01 (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSLEW_SLEWF00_Pos       (2UL)        /* SLEWF00 (Bit 2) */
-#define LINK_REG_PHYSLEW_SLEWF00_Msk       (0x4UL)      /* SLEWF00 (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSLEW_SLEWR01_Pos       (1UL)        /* SLEWR01 (Bit 1) */
-#define LINK_REG_PHYSLEW_SLEWR01_Msk       (0x2UL)      /* SLEWR01 (Bitfield-Mask: 0x01) */
-#define LINK_REG_PHYSLEW_SLEWR00_Pos       (0UL)        /* SLEWR00 (Bit 0) */
-#define LINK_REG_PHYSLEW_SLEWR00_Msk       (0x1UL)      /* SLEWR00 (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSLEW_SLEWF01_Pos       (3UL)        /* SLEWF01 (Bit 3) */
+#define RUSB2_PHYSLEW_SLEWF01_Msk       (0x8UL)      /* SLEWF01 (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSLEW_SLEWF00_Pos       (2UL)        /* SLEWF00 (Bit 2) */
+#define RUSB2_PHYSLEW_SLEWF00_Msk       (0x4UL)      /* SLEWF00 (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSLEW_SLEWR01_Pos       (1UL)        /* SLEWR01 (Bit 1) */
+#define RUSB2_PHYSLEW_SLEWR01_Msk       (0x2UL)      /* SLEWR01 (Bitfield-Mask: 0x01) */
+#define RUSB2_PHYSLEW_SLEWR00_Pos       (0UL)        /* SLEWR00 (Bit 0) */
+#define RUSB2_PHYSLEW_SLEWR00_Msk       (0x1UL)      /* SLEWR00 (Bitfield-Mask: 0x01) */
 
 // LPCTRL
-#define LINK_REG_LPCTRL_HWUPM_Pos          (7UL)        /* HWUPM (Bit 7) */
-#define LINK_REG_LPCTRL_HWUPM_Msk          (0x80UL)     /* HWUPM (Bitfield-Mask: 0x01) */
+#define RUSB2_LPCTRL_HWUPM_Pos          (7UL)        /* HWUPM (Bit 7) */
+#define RUSB2_LPCTRL_HWUPM_Msk          (0x80UL)     /* HWUPM (Bitfield-Mask: 0x01) */
 
 // LPSTS
-#define LINK_REG_LPSTS_SUSPENDM_Pos        (14UL)       /* SUSPENDM (Bit 14) */
-#define LINK_REG_LPSTS_SUSPENDM_Msk        (0x4000UL)   /* SUSPENDM (Bitfield-Mask: 0x01) */
+#define RUSB2_LPSTS_SUSPENDM_Pos        (14UL)       /* SUSPENDM (Bit 14) */
+#define RUSB2_LPSTS_SUSPENDM_Msk        (0x4000UL)   /* SUSPENDM (Bitfield-Mask: 0x01) */
 
 // BCCTRL
-#define LINK_REG_BCCTRL_PDDETSTS_Pos       (9UL)        /* PDDETSTS (Bit 9) */
-#define LINK_REG_BCCTRL_PDDETSTS_Msk       (0x200UL)    /* PDDETSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_CHGDETSTS_Pos      (8UL)        /* CHGDETSTS (Bit 8) */
-#define LINK_REG_BCCTRL_CHGDETSTS_Msk      (0x100UL)    /* CHGDETSTS (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_DCPMODE_Pos        (5UL)        /* DCPMODE (Bit 5) */
-#define LINK_REG_BCCTRL_DCPMODE_Msk        (0x20UL)     /* DCPMODE (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_VDMSRCE_Pos        (4UL)        /* VDMSRCE (Bit 4) */
-#define LINK_REG_BCCTRL_VDMSRCE_Msk        (0x10UL)     /* VDMSRCE (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_IDPSINKE_Pos       (3UL)        /* IDPSINKE (Bit 3) */
-#define LINK_REG_BCCTRL_IDPSINKE_Msk       (0x8UL)      /* IDPSINKE (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_VDPSRCE_Pos        (2UL)        /* VDPSRCE (Bit 2) */
-#define LINK_REG_BCCTRL_VDPSRCE_Msk        (0x4UL)      /* VDPSRCE (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_IDMSINKE_Pos       (1UL)        /* IDMSINKE (Bit 1) */
-#define LINK_REG_BCCTRL_IDMSINKE_Msk       (0x2UL)      /* IDMSINKE (Bitfield-Mask: 0x01) */
-#define LINK_REG_BCCTRL_IDPSRCE_Pos        (0UL)        /* IDPSRCE (Bit 0) */
-#define LINK_REG_BCCTRL_IDPSRCE_Msk        (0x1UL)      /* IDPSRCE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_PDDETSTS_Pos       (9UL)        /* PDDETSTS (Bit 9) */
+#define RUSB2_BCCTRL_PDDETSTS_Msk       (0x200UL)    /* PDDETSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_CHGDETSTS_Pos      (8UL)        /* CHGDETSTS (Bit 8) */
+#define RUSB2_BCCTRL_CHGDETSTS_Msk      (0x100UL)    /* CHGDETSTS (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_DCPMODE_Pos        (5UL)        /* DCPMODE (Bit 5) */
+#define RUSB2_BCCTRL_DCPMODE_Msk        (0x20UL)     /* DCPMODE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_VDMSRCE_Pos        (4UL)        /* VDMSRCE (Bit 4) */
+#define RUSB2_BCCTRL_VDMSRCE_Msk        (0x10UL)     /* VDMSRCE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_IDPSINKE_Pos       (3UL)        /* IDPSINKE (Bit 3) */
+#define RUSB2_BCCTRL_IDPSINKE_Msk       (0x8UL)      /* IDPSINKE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_VDPSRCE_Pos        (2UL)        /* VDPSRCE (Bit 2) */
+#define RUSB2_BCCTRL_VDPSRCE_Msk        (0x4UL)      /* VDPSRCE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_IDMSINKE_Pos       (1UL)        /* IDMSINKE (Bit 1) */
+#define RUSB2_BCCTRL_IDMSINKE_Msk       (0x2UL)      /* IDMSINKE (Bitfield-Mask: 0x01) */
+#define RUSB2_BCCTRL_IDPSRCE_Pos        (0UL)        /* IDPSRCE (Bit 0) */
+#define RUSB2_BCCTRL_IDPSRCE_Msk        (0x1UL)      /* IDPSRCE (Bitfield-Mask: 0x01) */
 
 // PL1CTRL1
-#define LINK_REG_PL1CTRL1_L1EXTMD_Pos      (14UL)       /* L1EXTMD (Bit 14) */
-#define LINK_REG_PL1CTRL1_L1EXTMD_Msk      (0x4000UL)   /* L1EXTMD (Bitfield-Mask: 0x01) */
-#define LINK_REG_PL1CTRL1_HIRDTHR_Pos      (8UL)        /* HIRDTHR (Bit 8) */
-#define LINK_REG_PL1CTRL1_HIRDTHR_Msk      (0xf00UL)    /* HIRDTHR (Bitfield-Mask: 0x0f) */
-#define LINK_REG_PL1CTRL1_DVSQ_Pos         (4UL)        /* DVSQ (Bit 4) */
-#define LINK_REG_PL1CTRL1_DVSQ_Msk         (0xf0UL)     /* DVSQ (Bitfield-Mask: 0x0f) */
-#define LINK_REG_PL1CTRL1_L1NEGOMD_Pos     (3UL)        /* L1NEGOMD (Bit 3) */
-#define LINK_REG_PL1CTRL1_L1NEGOMD_Msk     (0x8UL)      /* L1NEGOMD (Bitfield-Mask: 0x01) */
-#define LINK_REG_PL1CTRL1_L1RESPMD_Pos     (1UL)        /* L1RESPMD (Bit 1) */
-#define LINK_REG_PL1CTRL1_L1RESPMD_Msk     (0x6UL)      /* L1RESPMD (Bitfield-Mask: 0x03) */
-#define LINK_REG_PL1CTRL1_L1RESPEN_Pos     (0UL)        /* L1RESPEN (Bit 0) */
-#define LINK_REG_PL1CTRL1_L1RESPEN_Msk     (0x1UL)      /* L1RESPEN (Bitfield-Mask: 0x01) */
+#define RUSB2_PL1CTRL1_L1EXTMD_Pos      (14UL)       /* L1EXTMD (Bit 14) */
+#define RUSB2_PL1CTRL1_L1EXTMD_Msk      (0x4000UL)   /* L1EXTMD (Bitfield-Mask: 0x01) */
+#define RUSB2_PL1CTRL1_HIRDTHR_Pos      (8UL)        /* HIRDTHR (Bit 8) */
+#define RUSB2_PL1CTRL1_HIRDTHR_Msk      (0xf00UL)    /* HIRDTHR (Bitfield-Mask: 0x0f) */
+#define RUSB2_PL1CTRL1_DVSQ_Pos         (4UL)        /* DVSQ (Bit 4) */
+#define RUSB2_PL1CTRL1_DVSQ_Msk         (0xf0UL)     /* DVSQ (Bitfield-Mask: 0x0f) */
+#define RUSB2_PL1CTRL1_L1NEGOMD_Pos     (3UL)        /* L1NEGOMD (Bit 3) */
+#define RUSB2_PL1CTRL1_L1NEGOMD_Msk     (0x8UL)      /* L1NEGOMD (Bitfield-Mask: 0x01) */
+#define RUSB2_PL1CTRL1_L1RESPMD_Pos     (1UL)        /* L1RESPMD (Bit 1) */
+#define RUSB2_PL1CTRL1_L1RESPMD_Msk     (0x6UL)      /* L1RESPMD (Bitfield-Mask: 0x03) */
+#define RUSB2_PL1CTRL1_L1RESPEN_Pos     (0UL)        /* L1RESPEN (Bit 0) */
+#define RUSB2_PL1CTRL1_L1RESPEN_Msk     (0x1UL)      /* L1RESPEN (Bitfield-Mask: 0x01) */
 
 // PL1CTRL2
-#define LINK_REG_PL1CTRL2_RWEMON_Pos       (12UL)       /* RWEMON (Bit 12) */
-#define LINK_REG_PL1CTRL2_RWEMON_Msk       (0x1000UL)   /* RWEMON (Bitfield-Mask: 0x01) */
-#define LINK_REG_PL1CTRL2_HIRDMON_Pos      (8UL)        /* HIRDMON (Bit 8) */
-#define LINK_REG_PL1CTRL2_HIRDMON_Msk      (0xf00UL)    /* HIRDMON (Bitfield-Mask: 0x0f) */
+#define RUSB2_PL1CTRL2_RWEMON_Pos       (12UL)       /* RWEMON (Bit 12) */
+#define RUSB2_PL1CTRL2_RWEMON_Msk       (0x1000UL)   /* RWEMON (Bitfield-Mask: 0x01) */
+#define RUSB2_PL1CTRL2_HIRDMON_Pos      (8UL)        /* HIRDMON (Bit 8) */
+#define RUSB2_PL1CTRL2_HIRDMON_Msk      (0xf00UL)    /* HIRDMON (Bitfield-Mask: 0x0f) */
 
 // HL1CTRL1
-#define LINK_REG_HL1CTRL1_L1STATUS_Pos     (1UL)        /* L1STATUS (Bit 1) */
-#define LINK_REG_HL1CTRL1_L1STATUS_Msk     (0x6UL)      /* L1STATUS (Bitfield-Mask: 0x03) */
-#define LINK_REG_HL1CTRL1_L1REQ_Pos        (0UL)        /* L1REQ (Bit 0) */
-#define LINK_REG_HL1CTRL1_L1REQ_Msk        (0x1UL)      /* L1REQ (Bitfield-Mask: 0x01) */
+#define RUSB2_HL1CTRL1_L1STATUS_Pos     (1UL)        /* L1STATUS (Bit 1) */
+#define RUSB2_HL1CTRL1_L1STATUS_Msk     (0x6UL)      /* L1STATUS (Bitfield-Mask: 0x03) */
+#define RUSB2_HL1CTRL1_L1REQ_Pos        (0UL)        /* L1REQ (Bit 0) */
+#define RUSB2_HL1CTRL1_L1REQ_Msk        (0x1UL)      /* L1REQ (Bitfield-Mask: 0x01) */
 
 // HL1CTRL2
-#define LINK_REG_HL1CTRL2_BESL_Pos         (15UL)       /* BESL (Bit 15) */
-#define LINK_REG_HL1CTRL2_BESL_Msk         (0x8000UL)   /* BESL (Bitfield-Mask: 0x01) */
-#define LINK_REG_HL1CTRL2_L1RWE_Pos        (12UL)       /* L1RWE (Bit 12) */
-#define LINK_REG_HL1CTRL2_L1RWE_Msk        (0x1000UL)   /* L1RWE (Bitfield-Mask: 0x01) */
-#define LINK_REG_HL1CTRL2_HIRD_Pos         (8UL)        /* HIRD (Bit 8) */
-#define LINK_REG_HL1CTRL2_HIRD_Msk         (0xf00UL)    /* HIRD (Bitfield-Mask: 0x0f) */
-#define LINK_REG_HL1CTRL2_L1ADDR_Pos       (0UL)        /* L1ADDR (Bit 0) */
-#define LINK_REG_HL1CTRL2_L1ADDR_Msk       (0xfUL)      /* L1ADDR (Bitfield-Mask: 0x0f) */
+#define RUSB2_HL1CTRL2_BESL_Pos         (15UL)       /* BESL (Bit 15) */
+#define RUSB2_HL1CTRL2_BESL_Msk         (0x8000UL)   /* BESL (Bitfield-Mask: 0x01) */
+#define RUSB2_HL1CTRL2_L1RWE_Pos        (12UL)       /* L1RWE (Bit 12) */
+#define RUSB2_HL1CTRL2_L1RWE_Msk        (0x1000UL)   /* L1RWE (Bitfield-Mask: 0x01) */
+#define RUSB2_HL1CTRL2_HIRD_Pos         (8UL)        /* HIRD (Bit 8) */
+#define RUSB2_HL1CTRL2_HIRD_Msk         (0xf00UL)    /* HIRD (Bitfield-Mask: 0x0f) */
+#define RUSB2_HL1CTRL2_L1ADDR_Pos       (0UL)        /* L1ADDR (Bit 0) */
+#define RUSB2_HL1CTRL2_L1ADDR_Msk       (0xfUL)      /* L1ADDR (Bitfield-Mask: 0x0f) */
 
 // DPUSR0R
-#define LINK_REG_DPUSR0R_DVBSTSHM_Pos      (23UL)       /* DVBSTSHM (Bit 23) */
-#define LINK_REG_DPUSR0R_DVBSTSHM_Msk      (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_DOVCBHM_Pos       (21UL)       /* DOVCBHM (Bit 21) */
-#define LINK_REG_DPUSR0R_DOVCBHM_Msk       (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_DOVCAHM_Pos       (20UL)       /* DOVCAHM (Bit 20) */
-#define LINK_REG_DPUSR0R_DOVCAHM_Msk       (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_DVBSTSHM_Pos      (23UL)       /* DVBSTSHM (Bit 23) */
+#define RUSB2_DPUSR0R_DVBSTSHM_Msk      (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_DOVCBHM_Pos       (21UL)       /* DOVCBHM (Bit 21) */
+#define RUSB2_DPUSR0R_DOVCBHM_Msk       (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_DOVCAHM_Pos       (20UL)       /* DOVCAHM (Bit 20) */
+#define RUSB2_DPUSR0R_DOVCAHM_Msk       (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */
 
 // DPUSR1R
-#define LINK_REG_DPUSR1R_DVBSTSH_Pos       (23UL)       /* DVBSTSH (Bit 23) */
-#define LINK_REG_DPUSR1R_DVBSTSH_Msk       (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_DOVCBH_Pos        (21UL)       /* DOVCBH (Bit 21) */
-#define LINK_REG_DPUSR1R_DOVCBH_Msk        (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_DOVCAH_Pos        (20UL)       /* DOVCAH (Bit 20) */
-#define LINK_REG_DPUSR1R_DOVCAH_Msk        (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_DVBSTSHE_Pos      (7UL)        /* DVBSTSHE (Bit 7) */
-#define LINK_REG_DPUSR1R_DVBSTSHE_Msk      (0x80UL)     /* DVBSTSHE (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_DOVCBHE_Pos       (5UL)        /* DOVCBHE (Bit 5) */
-#define LINK_REG_DPUSR1R_DOVCBHE_Msk       (0x20UL)     /* DOVCBHE (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_DOVCAHE_Pos       (4UL)        /* DOVCAHE (Bit 4) */
-#define LINK_REG_DPUSR1R_DOVCAHE_Msk       (0x10UL)     /* DOVCAHE (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DVBSTSH_Pos       (23UL)       /* DVBSTSH (Bit 23) */
+#define RUSB2_DPUSR1R_DVBSTSH_Msk       (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DOVCBH_Pos        (21UL)       /* DOVCBH (Bit 21) */
+#define RUSB2_DPUSR1R_DOVCBH_Msk        (0x200000UL) /* DOVCBH (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DOVCAH_Pos        (20UL)       /* DOVCAH (Bit 20) */
+#define RUSB2_DPUSR1R_DOVCAH_Msk        (0x100000UL) /* DOVCAH (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DVBSTSHE_Pos      (7UL)        /* DVBSTSHE (Bit 7) */
+#define RUSB2_DPUSR1R_DVBSTSHE_Msk      (0x80UL)     /* DVBSTSHE (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DOVCBHE_Pos       (5UL)        /* DOVCBHE (Bit 5) */
+#define RUSB2_DPUSR1R_DOVCBHE_Msk       (0x20UL)     /* DOVCBHE (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_DOVCAHE_Pos       (4UL)        /* DOVCAHE (Bit 4) */
+#define RUSB2_DPUSR1R_DOVCAHE_Msk       (0x10UL)     /* DOVCAHE (Bitfield-Mask: 0x01) */
 
 // DPUSR2R
-#define LINK_REG_DPUSR2R_DMINTE_Pos        (9UL)        /* DMINTE (Bit 9) */
-#define LINK_REG_DPUSR2R_DMINTE_Msk        (0x200UL)    /* DMINTE (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR2R_DPINTE_Pos        (8UL)        /* DPINTE (Bit 8) */
-#define LINK_REG_DPUSR2R_DPINTE_Msk        (0x100UL)    /* DPINTE (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR2R_DMVAL_Pos         (5UL)        /* DMVAL (Bit 5) */
-#define LINK_REG_DPUSR2R_DMVAL_Msk         (0x20UL)     /* DMVAL (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR2R_DPVAL_Pos         (4UL)        /* DPVAL (Bit 4) */
-#define LINK_REG_DPUSR2R_DPVAL_Msk         (0x10UL)     /* DPVAL (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR2R_DMINT_Pos         (1UL)        /* DMINT (Bit 1) */
-#define LINK_REG_DPUSR2R_DMINT_Msk         (0x2UL)      /* DMINT (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR2R_DPINT_Pos         (0UL)        /* DPINT (Bit 0) */
-#define LINK_REG_DPUSR2R_DPINT_Msk         (0x1UL)      /* DPINT (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DMINTE_Pos        (9UL)        /* DMINTE (Bit 9) */
+#define RUSB2_DPUSR2R_DMINTE_Msk        (0x200UL)    /* DMINTE (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DPINTE_Pos        (8UL)        /* DPINTE (Bit 8) */
+#define RUSB2_DPUSR2R_DPINTE_Msk        (0x100UL)    /* DPINTE (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DMVAL_Pos         (5UL)        /* DMVAL (Bit 5) */
+#define RUSB2_DPUSR2R_DMVAL_Msk         (0x20UL)     /* DMVAL (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DPVAL_Pos         (4UL)        /* DPVAL (Bit 4) */
+#define RUSB2_DPUSR2R_DPVAL_Msk         (0x10UL)     /* DPVAL (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DMINT_Pos         (1UL)        /* DMINT (Bit 1) */
+#define RUSB2_DPUSR2R_DMINT_Msk         (0x2UL)      /* DMINT (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR2R_DPINT_Pos         (0UL)        /* DPINT (Bit 0) */
+#define RUSB2_DPUSR2R_DPINT_Msk         (0x1UL)      /* DPINT (Bitfield-Mask: 0x01) */
 
 // DPUSRCR
-#define LINK_REG_DPUSRCR_FIXPHYPD_Pos      (1UL)        /* FIXPHYPD (Bit 1) */
-#define LINK_REG_DPUSRCR_FIXPHYPD_Msk      (0x2UL)      /* FIXPHYPD (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSRCR_FIXPHY_Pos        (0UL)        /* FIXPHY (Bit 0) */
-#define LINK_REG_DPUSRCR_FIXPHY_Msk        (0x1UL)      /* FIXPHY (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSRCR_FIXPHYPD_Pos      (1UL)        /* FIXPHYPD (Bit 1) */
+#define RUSB2_DPUSRCR_FIXPHYPD_Msk      (0x2UL)      /* FIXPHYPD (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSRCR_FIXPHY_Pos        (0UL)        /* FIXPHY (Bit 0) */
+#define RUSB2_DPUSRCR_FIXPHY_Msk        (0x1UL)      /* FIXPHY (Bitfield-Mask: 0x01) */
 
 // DPUSR0R_FS
-#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos    (23UL)       /* DVBSTS0 (Bit 23) */
-#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk    (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos     (21UL)       /* DOVCB0 (Bit 21) */
-#define LINK_REG_DPUSR0R_FS_DOVCB0_Msk     (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_DOVCA0_Pos     (20UL)       /* DOVCA0 (Bit 20) */
-#define LINK_REG_DPUSR0R_FS_DOVCA0_Msk     (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_DM0_Pos        (17UL)       /* DM0 (Bit 17) */
-#define LINK_REG_DPUSR0R_FS_DM0_Msk        (0x20000UL)  /* DM0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_DP0_Pos        (16UL)       /* DP0 (Bit 16) */
-#define LINK_REG_DPUSR0R_FS_DP0_Msk        (0x10000UL)  /* DP0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_FIXPHY0_Pos    (4UL)        /* FIXPHY0 (Bit 4) */
-#define LINK_REG_DPUSR0R_FS_FIXPHY0_Msk    (0x10UL)     /* FIXPHY0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_DRPD0_Pos      (3UL)        /* DRPD0 (Bit 3) */
-#define LINK_REG_DPUSR0R_FS_DRPD0_Msk      (0x8UL)      /* DRPD0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_RPUE0_Pos      (1UL)        /* RPUE0 (Bit 1) */
-#define LINK_REG_DPUSR0R_FS_RPUE0_Msk      (0x2UL)      /* RPUE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR0R_FS_SRPC0_Pos      (0UL)        /* SRPC0 (Bit 0) */
-#define LINK_REG_DPUSR0R_FS_SRPC0_Msk      (0x1UL)      /* SRPC0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DVBSTS0_Pos    (23UL)       /* DVBSTS0 (Bit 23) */
+#define RUSB2_DPUSR0R_FS_DVBSTS0_Msk    (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DOVCB0_Pos     (21UL)       /* DOVCB0 (Bit 21) */
+#define RUSB2_DPUSR0R_FS_DOVCB0_Msk     (0x200000UL) /* DOVCB0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DOVCA0_Pos     (20UL)       /* DOVCA0 (Bit 20) */
+#define RUSB2_DPUSR0R_FS_DOVCA0_Msk     (0x100000UL) /* DOVCA0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DM0_Pos        (17UL)       /* DM0 (Bit 17) */
+#define RUSB2_DPUSR0R_FS_DM0_Msk        (0x20000UL)  /* DM0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DP0_Pos        (16UL)       /* DP0 (Bit 16) */
+#define RUSB2_DPUSR0R_FS_DP0_Msk        (0x10000UL)  /* DP0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_FIXPHY0_Pos    (4UL)        /* FIXPHY0 (Bit 4) */
+#define RUSB2_DPUSR0R_FS_FIXPHY0_Msk    (0x10UL)     /* FIXPHY0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_DRPD0_Pos      (3UL)        /* DRPD0 (Bit 3) */
+#define RUSB2_DPUSR0R_FS_DRPD0_Msk      (0x8UL)      /* DRPD0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_RPUE0_Pos      (1UL)        /* RPUE0 (Bit 1) */
+#define RUSB2_DPUSR0R_FS_RPUE0_Msk      (0x2UL)      /* RPUE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR0R_FS_SRPC0_Pos      (0UL)        /* SRPC0 (Bit 0) */
+#define RUSB2_DPUSR0R_FS_SRPC0_Msk      (0x1UL)      /* SRPC0 (Bitfield-Mask: 0x01) */
 
 // DPUSR1R_FS
-#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos    (23UL)       /* DVBINT0 (Bit 23) */
-#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk    (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos   (21UL)       /* DOVRCRB0 (Bit 21) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Msk   (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Pos   (20UL)       /* DOVRCRA0 (Bit 20) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRA0_Msk   (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DMINT0_Pos     (17UL)       /* DMINT0 (Bit 17) */
-#define LINK_REG_DPUSR1R_FS_DMINT0_Msk     (0x20000UL)  /* DMINT0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DPINT0_Pos     (16UL)       /* DPINT0 (Bit 16) */
-#define LINK_REG_DPUSR1R_FS_DPINT0_Msk     (0x10000UL)  /* DPINT0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DVBSE0_Pos     (7UL)        /* DVBSE0 (Bit 7) */
-#define LINK_REG_DPUSR1R_FS_DVBSE0_Msk     (0x80UL)     /* DVBSE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Pos  (5UL)        /* DOVRCRBE0 (Bit 5) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRBE0_Msk  (0x20UL)     /* DOVRCRBE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Pos  (4UL)        /* DOVRCRAE0 (Bit 4) */
-#define LINK_REG_DPUSR1R_FS_DOVRCRAE0_Msk  (0x10UL)     /* DOVRCRAE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DMINTE0_Pos    (1UL)        /* DMINTE0 (Bit 1) */
-#define LINK_REG_DPUSR1R_FS_DMINTE0_Msk    (0x2UL)      /* DMINTE0 (Bitfield-Mask: 0x01) */
-#define LINK_REG_DPUSR1R_FS_DPINTE0_Pos    (0UL)        /* DPINTE0 (Bit 0) */
-#define LINK_REG_DPUSR1R_FS_DPINTE0_Msk    (0x1UL)      /* DPINTE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DVBINT0_Pos    (23UL)       /* DVBINT0 (Bit 23) */
+#define RUSB2_DPUSR1R_FS_DVBINT0_Msk    (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DOVRCRB0_Pos   (21UL)       /* DOVRCRB0 (Bit 21) */
+#define RUSB2_DPUSR1R_FS_DOVRCRB0_Msk   (0x200000UL) /* DOVRCRB0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DOVRCRA0_Pos   (20UL)       /* DOVRCRA0 (Bit 20) */
+#define RUSB2_DPUSR1R_FS_DOVRCRA0_Msk   (0x100000UL) /* DOVRCRA0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DMINT0_Pos     (17UL)       /* DMINT0 (Bit 17) */
+#define RUSB2_DPUSR1R_FS_DMINT0_Msk     (0x20000UL)  /* DMINT0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DPINT0_Pos     (16UL)       /* DPINT0 (Bit 16) */
+#define RUSB2_DPUSR1R_FS_DPINT0_Msk     (0x10000UL)  /* DPINT0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DVBSE0_Pos     (7UL)        /* DVBSE0 (Bit 7) */
+#define RUSB2_DPUSR1R_FS_DVBSE0_Msk     (0x80UL)     /* DVBSE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DOVRCRBE0_Pos  (5UL)        /* DOVRCRBE0 (Bit 5) */
+#define RUSB2_DPUSR1R_FS_DOVRCRBE0_Msk  (0x20UL)     /* DOVRCRBE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DOVRCRAE0_Pos  (4UL)        /* DOVRCRAE0 (Bit 4) */
+#define RUSB2_DPUSR1R_FS_DOVRCRAE0_Msk  (0x10UL)     /* DOVRCRAE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DMINTE0_Pos    (1UL)        /* DMINTE0 (Bit 1) */
+#define RUSB2_DPUSR1R_FS_DMINTE0_Msk    (0x2UL)      /* DMINTE0 (Bitfield-Mask: 0x01) */
+#define RUSB2_DPUSR1R_FS_DPINTE0_Pos    (0UL)        /* DPINTE0 (Bit 0) */
+#define RUSB2_DPUSR1R_FS_DPINTE0_Msk    (0x1UL)      /* DPINTE0 (Bitfield-Mask: 0x01) */
 
 /*--------------------------------------------------------------------*/
 /* Register Bit Utils                                           */
 /*--------------------------------------------------------------------*/
-#define LINK_REG_PIPE_CTR_PID_NAK          (0U << LINK_REG_PIPE_CTR_PID_Pos)    /* NAK response */
-#define LINK_REG_PIPE_CTR_PID_BUF          (1U << LINK_REG_PIPE_CTR_PID_Pos)    /* BUF response (depends buffer state) */
-#define LINK_REG_PIPE_CTR_PID_STALL        (2U << LINK_REG_PIPE_CTR_PID_Pos)    /* STALL response */
+#define RUSB2_PIPE_CTR_PID_NAK          (0U << RUSB2_PIPE_CTR_PID_Pos)    /* NAK response */
+#define RUSB2_PIPE_CTR_PID_BUF          (1U << RUSB2_PIPE_CTR_PID_Pos)    /* BUF response (depends buffer state) */
+#define RUSB2_PIPE_CTR_PID_STALL        (2U << RUSB2_PIPE_CTR_PID_Pos)    /* STALL response */
 
-#define LINK_REG_DVSTCTR0_RHST_LS          (1U << LINK_REG_DVSTCTR0_RHST_Pos)   /*  Low-speed connection */
-#define LINK_REG_DVSTCTR0_RHST_FS          (2U << LINK_REG_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
+#define RUSB2_DVSTCTR0_RHST_LS          (1U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Low-speed connection */
+#define RUSB2_DVSTCTR0_RHST_FS          (2U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
 
-#define LINK_REG_DEVADD_USBSPD_LS          (1U << LINK_REG_DEVADD_USBSPD_Pos)   /* Target Device Low-speed */
-#define LINK_REG_DEVADD_USBSPD_FS          (2U << LINK_REG_DEVADD_USBSPD_Pos)   /* Target Device Full-speed */
+#define RUSB2_DEVADD_USBSPD_LS          (1U << RUSB2_DEVADD_USBSPD_Pos)   /* Target Device Low-speed */
+#define RUSB2_DEVADD_USBSPD_FS          (2U << RUSB2_DEVADD_USBSPD_Pos)   /* Target Device Full-speed */
 
-#define LINK_REG_CFIFOSEL_ISEL_WRITE       (1U << LINK_REG_CFIFOSEL_ISEL_Pos)   /* FIFO write AKA TX*/
+#define RUSB2_CFIFOSEL_ISEL_WRITE       (1U << RUSB2_CFIFOSEL_ISEL_Pos)   /* FIFO write AKA TX*/
 
-#define LINK_REG_FIFOSEL_BIGEND            (1U << LINK_REG_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */
-#define LINK_REG_FIFOSEL_MBW_8BIT          (0U << LINK_REG_CFIFOSEL_MBW_Pos)    /* 8-bit width */
-#define LINK_REG_FIFOSEL_MBW_16BIT         (1U << LINK_REG_CFIFOSEL_MBW_Pos)    /* 16-bit width */
+#define RUSB2_FIFOSEL_BIGEND            (1U << RUSB2_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */
+#define RUSB2_FIFOSEL_MBW_8BIT          (0U << RUSB2_CFIFOSEL_MBW_Pos)    /* 8-bit width */
+#define RUSB2_FIFOSEL_MBW_16BIT         (1U << RUSB2_CFIFOSEL_MBW_Pos)    /* 16-bit width */
 
-#define LINK_REG_INTSTS0_CTSQ_CTRL_RDATA   (1U << LINK_REG_INTSTS0_CTSQ_Pos)
+#define RUSB2_INTSTS0_CTSQ_CTRL_RDATA   (1U << RUSB2_INTSTS0_CTSQ_Pos)
 
-#define LINK_REG_INTSTS0_DVSQ_STATE_DEF    (1U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Default state */
-#define LINK_REG_INTSTS0_DVSQ_STATE_ADDR   (2U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Address state */
-#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP0  (4U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Suspend state */
-#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP1  (5U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Suspend state */
-#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP2  (6U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Suspend state */
-#define LINK_REG_INTSTS0_DVSQ_STATE_SUSP3  (7U << LINK_REG_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define RUSB2_INTSTS0_DVSQ_STATE_DEF    (1U << RUSB2_INTSTS0_DVSQ_Pos)    /* Default state */
+#define RUSB2_INTSTS0_DVSQ_STATE_ADDR   (2U << RUSB2_INTSTS0_DVSQ_Pos)    /* Address state */
+#define RUSB2_INTSTS0_DVSQ_STATE_SUSP0  (4U << RUSB2_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define RUSB2_INTSTS0_DVSQ_STATE_SUSP1  (5U << RUSB2_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define RUSB2_INTSTS0_DVSQ_STATE_SUSP2  (6U << RUSB2_INTSTS0_DVSQ_Pos)    /* Suspend state */
+#define RUSB2_INTSTS0_DVSQ_STATE_SUSP3  (7U << RUSB2_INTSTS0_DVSQ_Pos)    /* Suspend state */
 
-#define LINK_REG_PIPECFG_TYPE_BULK         (1U << LINK_REG_PIPECFG_TYPE_Pos)
-#define LINK_REG_PIPECFG_TYPE_INT          (2U << LINK_REG_PIPECFG_TYPE_Pos)
-#define LINK_REG_PIPECFG_TYPE_ISO          (3U << LINK_REG_PIPECFG_TYPE_Pos)
+#define RUSB2_PIPECFG_TYPE_BULK         (1U << RUSB2_PIPECFG_TYPE_Pos)
+#define RUSB2_PIPECFG_TYPE_INT          (2U << RUSB2_PIPECFG_TYPE_Pos)
+#define RUSB2_PIPECFG_TYPE_ISO          (3U << RUSB2_PIPECFG_TYPE_Pos)
 
 //--------------------------------------------------------------------+
 // Static Assert
 //--------------------------------------------------------------------+
 
-TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size");
+TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size");
 
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG     ) == 0x00000000, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT    ) == 0x00000002, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0    ) == 0x00000004, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA     ) == 0x00000006, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0   ) == 0x00000008, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE   ) == 0x0000000C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO      ) == 0x00000014, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO     ) == 0x00000018, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO     ) == 0x0000001C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL   ) == 0x00000020, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR   ) == 0x00000022, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL  ) == 0x00000028, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR  ) == 0x0000002A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL  ) == 0x0000002C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR  ) == 0x0000002E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0    ) == 0x00000030, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1    ) == 0x00000032, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB    ) == 0x00000036, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB    ) == 0x00000038, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB    ) == 0x0000003A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG     ) == 0x0000003C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET     ) == 0x0000003E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0    ) == 0x00000040, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1    ) == 0x00000042, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS    ) == 0x00000046, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS    ) == 0x00000048, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS    ) == 0x0000004A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM     ) == 0x0000004C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM    ) == 0x0000004E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR    ) == 0x00000050, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ     ) == 0x00000054, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL     ) == 0x00000056, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX    ) == 0x00000058, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG    ) == 0x0000005A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG     ) == 0x0000005C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP    ) == 0x0000005E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR     ) == 0x00000060, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL    ) == 0x00000064, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG    ) == 0x00000068, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP   ) == 0x0000006C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI   ) == 0x0000006E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR   ) == 0x00000070, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR    ) == 0x00000090, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL     ) == 0x000000C4, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC      ) == 0x000000CC, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD     ) == 0x000000D0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW    ) == 0x000000F0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL     ) == 0x00000100, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS      ) == 0x00000102, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL     ) == 0x00000140, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1   ) == 0x00000144, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2   ) == 0x00000146, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1   ) == 0x00000148, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2   ) == 0x0000014A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R    ) == 0x00000160, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R    ) == 0x00000164, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R    ) == 0x00000168, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR    ) == 0x0000016A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSCFG     ) == 0x00000000, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BUSWAIT    ) == 0x00000002, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSSTS0    ) == 0x00000004, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PLLSTA     ) == 0x00000006, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DVSTCTR0   ) == 0x00000008, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, TESTMODE   ) == 0x0000000C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFO      ) == 0x00000014, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFO     ) == 0x00000018, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFO     ) == 0x0000001C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOSEL   ) == 0x00000020, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOCTR   ) == 0x00000022, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOSEL  ) == 0x00000028, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOCTR  ) == 0x0000002A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOSEL  ) == 0x0000002C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOCTR  ) == 0x0000002E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB0    ) == 0x00000030, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB1    ) == 0x00000032, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYENB    ) == 0x00000036, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYENB    ) == 0x00000038, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPENB    ) == 0x0000003A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SOFCFG     ) == 0x0000003C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSET     ) == 0x0000003E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS0    ) == 0x00000040, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS1    ) == 0x00000042, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYSTS    ) == 0x00000046, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYSTS    ) == 0x00000048, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPSTS    ) == 0x0000004A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, FRMNUM     ) == 0x0000004C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UFRMNUM    ) == 0x0000004E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBADDR    ) == 0x00000050, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBREQ     ) == 0x00000054, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBVAL     ) == 0x00000056, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBINDX    ) == 0x00000058, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBLENG    ) == 0x0000005A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCFG     ) == 0x0000005C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPMAXP    ) == 0x0000005E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCTR     ) == 0x00000060, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPESEL    ) == 0x00000064, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPECFG    ) == 0x00000068, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEMAXP   ) == 0x0000006C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEPERI   ) == 0x0000006E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_CTR   ) == 0x00000070, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_TR    ) == 0x00000090, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UCKSEL     ) == 0x000000C4, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBMC      ) == 0x000000CC, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DEVADD     ) == 0x000000D0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSLEW    ) == 0x000000F0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPCTRL     ) == 0x00000100, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPSTS      ) == 0x00000102, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BCCTRL     ) == 0x00000140, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL1   ) == 0x00000144, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL2   ) == 0x00000146, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL1   ) == 0x00000148, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL2   ) == 0x0000014A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R    ) == 0x00000160, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R    ) == 0x00000164, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR2R    ) == 0x00000168, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSRCR    ) == 0x0000016A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset");
 
 #ifdef __cplusplus
 }

From 2a10d5c20bf3dd504f51b010321fc6b72bf1bb35 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 16 Mar 2023 11:39:53 +0700
Subject: [PATCH 1546/2085] rename ra  board name

---
 hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/board.mk                | 2 +-
 hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/fsp_cfg/bsp_cfg.h       | 0
 hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/fsp_cfg/bsp_clock_cfg.h | 0
 .../boards/{ek_ra4m3 => ra4m3_ek}/fsp_cfg/bsp_mcu_family_cfg.h  | 0
 hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/fsp_cfg/r_ioport_cfg.h  | 0
 hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/fsp_cfg/vector_data.h   | 0
 hw/bsp/ra/boards/{ek_ra4m3/ek_ra4m3.c => ra4m3_ek/ra4m3_ek.c}   | 0
 hw/bsp/ra/boards/{ek_ra4m3/ek_ra4m3.ld => ra4m3_ek/ra4m3_ek.ld} | 0
 8 files changed, 1 insertion(+), 1 deletion(-)
 rename hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/board.mk (90%)
 rename hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/fsp_cfg/bsp_cfg.h (100%)
 rename hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/fsp_cfg/bsp_clock_cfg.h (100%)
 rename hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/fsp_cfg/bsp_mcu_family_cfg.h (100%)
 rename hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/fsp_cfg/r_ioport_cfg.h (100%)
 rename hw/bsp/ra/boards/{ek_ra4m3 => ra4m3_ek}/fsp_cfg/vector_data.h (100%)
 rename hw/bsp/ra/boards/{ek_ra4m3/ek_ra4m3.c => ra4m3_ek/ra4m3_ek.c} (100%)
 rename hw/bsp/ra/boards/{ek_ra4m3/ek_ra4m3.ld => ra4m3_ek/ra4m3_ek.ld} (100%)
 mode change 100755 => 100644

diff --git a/hw/bsp/ra/boards/ek_ra4m3/board.mk b/hw/bsp/ra/boards/ra4m3_ek/board.mk
similarity index 90%
rename from hw/bsp/ra/boards/ek_ra4m3/board.mk
rename to hw/bsp/ra/boards/ra4m3_ek/board.mk
index 19f293e54..61a7c5c4a 100644
--- a/hw/bsp/ra/boards/ek_ra4m3/board.mk
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.mk
@@ -8,7 +8,7 @@ FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m3
 FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m3_ek
 
 # All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/ek_ra4m3.ld
+LD_FILE = $(BOARD_PATH)/ra4m3_ek.ld
 
 # For flash-jlink target
 JLINK_DEVICE = R7FA4M3AF
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_mcu_family_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/bsp_mcu_family_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_mcu_family_cfg.h
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/r_ioport_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/r_ioport_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/r_ioport_cfg.h
diff --git a/hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h
similarity index 100%
rename from hw/bsp/ra/boards/ek_ra4m3/fsp_cfg/vector_data.h
rename to hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h
diff --git a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
similarity index 100%
rename from hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.c
rename to hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
diff --git a/hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.ld b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld
old mode 100755
new mode 100644
similarity index 100%
rename from hw/bsp/ra/boards/ek_ra4m3/ek_ra4m3.ld
rename to hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld

From e0b1de923c5411417d7818fe0611b3041b2ff2d4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 16 Mar 2023 22:39:00 +0700
Subject: [PATCH 1547/2085] add ra4m1_ek board

---
 docs/reference/supported.rst                  |  13 +-
 hw/bsp/ra/boards/ra4m1_ek/board.mk            |  17 +
 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h   |  35 +
 .../boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h   |  21 +
 .../ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h     |   5 +
 .../ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h  |  11 +
 .../ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h     |  78 ++
 .../ra/boards/ra4m1_ek/fsp_cfg/r_ioport_cfg.h |   7 +
 .../ra/boards/ra4m1_ek/fsp_cfg/vector_data.h  |   5 +
 hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c          | 232 ++++++
 hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld         | 738 ++++++++++++++++++
 hw/bsp/ra/boards/ra4m3_ek/board.mk            |   2 +
 hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c          |  18 +-
 13 files changed, 1172 insertions(+), 10 deletions(-)
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/board.mk
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/r_ioport_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index ae16d361d..b3f3f41d3 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -297,8 +297,17 @@ LPC55
 -  `LPCXpresso 55s69 EVK <https://www.nxp.com/design/development-boards/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK>`__
 -  `MCU-Link <https://www.nxp.com/design/development-boards/lpcxpresso-boards/mcu-link-debug-probe:MCU-LINK>`__
 
-Renesas RX
-----------
+Renesas
+-------
+
+RA
+^^
+
+-  `Evaluation Kit for RA4M1 <https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m1-evaluation-kit-ra4m1-mcu-group>`__
+-  `Evaluation Kit for RA4M3 <https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m3-evaluation-kit-ra4m3-mcu-group>`__
+
+RX
+^^
 
 -  `GR-CITRUS <https://www.renesas.com/us/en/products/gadget-renesas/boards/gr-citrus>`__
 -  `Renesas RX65N Target Board <https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk5rx65n0c00000br-target-board-rx65n>`__
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.mk b/hw/bsp/ra/boards/ra4m1_ek/board.mk
new file mode 100644
index 000000000..6a661c0b8
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.mk
@@ -0,0 +1,17 @@
+CFLAGS += \
+	-mcpu=cortex-m4 \
+	-mfloat-abi=hard \
+	-mfpu=fpv4-sp-d16 \
+	-DCFG_TUSB_MCU=OPT_MCU_RAXXX
+
+FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m1
+FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m1_ek
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/ra4m1_ek.ld
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA4M1AB
+JLINK_IF     = SWD
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h
new file mode 100644
index 000000000..b38a79b40
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h
@@ -0,0 +1,35 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+
+#include "board.h"
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+
+#undef RA_NOT_DEFINED
+#define BSP_CFG_RTOS (0)
+#if defined(_RA_BOOT_IMAGE)
+#define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x400)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT     ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE	(0)
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE		(0)
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(1)
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..930fa3547
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,21 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
+#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_8_0) /* PLL Mul x8 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..444d32e56
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..d810dabb2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M1AB3CFP
+#define BSP_MCU_FEATURE_SET ('A')
+#define BSP_ROM_SIZE_BYTES (262144)
+#define BSP_RAM_SIZE_BYTES (32768)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (100)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..3bde2db0d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h
@@ -0,0 +1,78 @@
+/* generated configuration header file through renesas e2 studio */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA4M1 (1)
+#define BSP_LOCO_HZ                 (32768)
+#define BSP_MOCO_HZ                 (8000000)
+#define BSP_SUB_CLOCK_HZ            (32768)
+#if   BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ             (24000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ             (32000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 4
+                #define BSP_HOCO_HZ             (48000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 5
+                #define BSP_HOCO_HZ             (64000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+/*
+ ID Code
+ Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+ WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+ */
+#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+            #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+            #else
+/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+#endif
+
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..cb7c07932
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,7 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h
new file mode 100644
index 000000000..37739c12a
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h
@@ -0,0 +1,5 @@
+/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
+#define TU_IRQn 0
+#define USBFS_RESUME_IRQn 1
+#define USBFS_FIFO_0_IRQn 2
+#define USBFS_FIFO_1_IRQn 3
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c
new file mode 100644
index 000000000..ea2204837
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c
@@ -0,0 +1,232 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Rafael Silva
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include <stdio.h>
+
+#include "bsp/board.h"
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "r_ioport_api.h"
+#include "renesas.h"
+
+/* Key code for writing PRCR register. */
+#define BSP_PRV_PRCR_KEY	 (0xA500U)
+#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
+#define BSP_PRV_PRCR_LOCK	 ((BSP_PRV_PRCR_KEY) | 0x0U)
+
+#define SW1  (BSP_IO_PORT_01_PIN_05)
+#define LED1 (BSP_IO_PORT_01_PIN_06)
+
+#define LED_STATE_ON          1
+#define BUTTON_STATE_ACTIVE   0
+
+/* ISR prototypes */
+void usbfs_interrupt_handler(void);
+void usbfs_resume_handler(void);
+void usbfs_d0fifo_handler(void);
+void usbfs_d1fifo_handler(void);
+
+BSP_DONT_REMOVE const
+  fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
+    [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
+    [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
+    [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
+    [3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
+};
+const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
+  [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
+  [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
+  [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
+  [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
+};
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+  { .pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) },
+  { .pin = SW1 , .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) },
+
+  { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
+  { .pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
+  { .pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
+
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+  .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
+  .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void usbfs_interrupt_handler(void)
+{
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+
+#if CFG_TUH_ENABLED
+  tuh_int_handler(0);
+#endif
+
+#if CFG_TUD_ENABLED
+  tud_int_handler(0);
+#endif
+}
+
+void usbfs_resume_handler(void)
+{
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+
+#if CFG_TUH_ENABLED
+  tuh_int_handler(0);
+#endif
+
+#if CFG_TUD_ENABLED
+  tud_int_handler(0);
+#endif
+}
+
+void usbfs_d0fifo_handler(void)
+{
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+
+#if CFG_TUH_ENABLED
+  tuh_int_handler(0);
+#endif
+
+#if CFG_TUD_ENABLED
+  tud_int_handler(0);
+#endif
+}
+
+void usbfs_d1fifo_handler(void)
+{
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+
+#if CFG_TUH_ENABLED
+  tuh_int_handler(0);
+#endif
+
+#if CFG_TUD_ENABLED
+  tud_int_handler(0);
+#endif
+}
+
+void board_init(void)
+{
+  /* Configure pins. */
+  R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+
+  /* Enable USB_BASE */
+  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
+  R_MSTP->MSTPCRB &= ~(1U << 11U);
+  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  /* Init systick */
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
+}
+
+uint32_t board_button_read(void)
+{
+  bsp_io_level_t lvl;
+  R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
+  return lvl == BUTTON_STATE_ACTIVE;
+}
+
+int board_uart_read(uint8_t *buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#else
+#endif
+
+int close(int fd)
+{
+  (void) fd;
+  return -1;
+}
+int fstat(int fd, void *pstat)
+{
+  (void) fd;
+  (void) pstat;
+  return 0;
+}
+off_t lseek(int fd, off_t pos, int whence)
+{
+  (void) fd;
+  (void) pos;
+  (void) whence;
+  return 0;
+}
+int isatty(int fd)
+{
+  (void) fd;
+  return 1;
+}
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld
new file mode 100644
index 000000000..8ddaa0a97
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld
@@ -0,0 +1,738 @@
+/* generated memory regions file - do not edit */
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x8000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x40000;
+DATA_FLASH_START = 0x40100000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x00000000;
+OPTION_SETTING_LENGTH = 0x0;
+OPTION_SETTING_S_START = 0x80000000;
+OPTION_SETTING_S_LENGTH = 0x0;
+ID_CODE_START = 0x01010018;
+ID_CODE_LENGTH = 0x20;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x0;
+OSPI_DEVICE_0_START = 0x80020000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x80030000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+/*
+                  Linker File for Renesas FSP
+*/
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+NS_OFFSET_START = DEFINED(NS_OFFSET_START) ? NS_OFFSET_START : 0;
+NS_IMAGE_OFFSET = DEFINED(PROJECT_NONSECURE) ? NS_OFFSET_START : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+                         FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                          FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END    = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                         FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                        FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                        __bl_FLASH_NS_START - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START    = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START   = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                       FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+                       __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                            FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                            __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START;
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+                           FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+                           FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+                XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+                FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+                       DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+                       FLASH_LENGTH;
+
+/* Define memory regions. */
+MEMORY
+{
+  ITCM (rx)               : ORIGIN = ITCM_START + NS_IMAGE_OFFSET, LENGTH = ITCM_LENGTH
+  DTCM (rwx)              : ORIGIN = DTCM_START + NS_IMAGE_OFFSET, LENGTH = DTCM_LENGTH
+  FLASH (rx)              : ORIGIN = FLASH_ORIGIN + NS_IMAGE_OFFSET, LENGTH = LIMITED_FLASH_LENGTH
+  RAM (rwx)               : ORIGIN = RAM_START + NS_IMAGE_OFFSET, LENGTH = RAM_LENGTH
+  DATA_FLASH (rx)         : ORIGIN = DATA_FLASH_START + NS_IMAGE_OFFSET, LENGTH = DATA_FLASH_LENGTH
+  QSPI_FLASH (rx)         : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+  OSPI_DEVICE_0 (rx)      : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1 (rx)      : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+  OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+  SDRAM (rwx)             : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+  OPTION_SETTING (r)      : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_LENGTH
+  OPTION_SETTING_OFS (r)  : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = 0x18
+  OPTION_SETTING_SAS (r)  : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET + 0x34, LENGTH = OPTION_SETTING_LENGTH - 0x34
+  OPTION_SETTING_S (r)    : ORIGIN = OPTION_SETTING_S_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_S_LENGTH
+  ID_CODE (rx)            : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ *   __qspi_flash_start__
+ *   __qspi_flash_end__
+ *   __qspi_flash_code_size__
+ *   __qspi_region_max_size__
+ *   __qspi_region_start_address__
+ *   __qspi_region_end_address__
+ *   __ospi_device_0_start__
+ *   __ospi_device_0_end__
+ *   __ospi_device_0_code_size__
+ *   __ospi_device_0_region_max_size__
+ *   __ospi_device_0_region_start_address__
+ *   __ospi_device_0_region_end_address__
+ *   __ospi_device_1_start__
+ *   __ospi_device_1_end__
+ *   __ospi_device_1_code_size__
+ *   __ospi_device_1_region_max_size__
+ *   __ospi_device_1_region_start_address__
+ *   __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    /* Initialized ITCM data. */
+    .itcm_data :
+    {
+        /* Start of ITCM Secure Trustzone region. */
+        __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+        /* All ITCM data start */
+        __itcm_data_start__ = .;
+
+        KEEP(*(.itcm_data*))
+
+        /* All ITCM data end */
+        __itcm_data_end__ = .;
+
+        /*
+         * Start of the ITCM Non-Secure Trustzone region.
+         * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+         */
+        __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end__, 8192);
+    } > ITCM
+
+    .text :
+    {
+        __tz_FLASH_S = ABSOLUTE(FLASH_START);
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+
+        /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+        /* Allocate flash write-boundary-aligned
+         * space for sce9 wrapped public keys for mcuboot if the module is used.
+         */
+		. = ALIGN(128);
+        KEEP(*(.mcuboot_sce9_key*))
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    __tz_RAM_S = ORIGIN(RAM);
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        __data_start__ = .;
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        *(vtable)
+        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+        *(.data.*)
+        *(.data)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+
+        . = ALIGN(4);
+
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM AT > FLASH
+
+    /* Start address of the initial values for .dtcm_data. */
+    __dtcm_data_init_start = __etext + __data_end__ - __data_start__;
+
+    /* Initialized DTCM data. */
+    .dtcm_data :
+    {
+        /* Start of DTCM Secure Trustzone region. */
+        __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+        /* Initialized DTCM data start */
+        __dtcm_data_start__ = .;
+
+        KEEP(*(.dtcm_data*))
+
+        /* Initialized DTCM data end */
+        __dtcm_data_end__ = .;
+    } > DTCM AT > FLASH
+
+    /* Uninitialized DTCM data. */
+    .dtcm_noinit (NOLOAD):
+    {
+        /* Uninitialized DTCM data start */
+        __dtcm_noinit_start = .;
+
+        KEEP(*(.dtcm_noinit*))
+
+        /* Uninitialized DTCM data end */
+        __dtcm_noinit_end = .;
+
+        /*
+         * Start of the DTCM Non-Secure Trustzone region.
+         * DTCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+         */
+        __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_noinit_end, 8192);
+    } > DTCM
+
+    /* TrustZone Secure Gateway Stubs Section. */
+
+    /* Some arithmetic is needed to eliminate unnecessary FILL for secure projects. */
+    /* 1. Get the address to the next block after the .data section in FLASH. */
+    DATA_END = LOADADDR(.data) + SIZEOF(.data);
+    /* 2. Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block after .data */
+    SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(DATA_END, 1024);
+    /* 3. Manually specify the start location for .gnu.sgstubs */
+    .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+    {
+        __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+        _start_sg = .;
+        *(.gnu.sgstubs*)
+        . = ALIGN(32);
+        _end_sg = .;
+    } > FLASH
+
+    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+    FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+    /* QSPI_FLASH section to be downloaded via debugger */
+    .qspi_flash :
+    {
+        __qspi_flash_start__ = .;
+        KEEP(*(.qspi_flash*))
+        KEEP(*(.code_in_qspi*))
+        __qspi_flash_end__ = .;
+    } > QSPI_FLASH
+    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+    __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
+    .qspi_non_retentive : AT (__qspi_flash_code_addr__)
+    {
+        __qspi_non_retentive_start__ = .;
+        KEEP(*(.qspi_non_retentive*))
+        __qspi_non_retentive_end__ = .;
+    } > QSPI_FLASH
+    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
+    __qspi_region_start_address__ = __qspi_flash_start__;
+    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+    /* Support for OctaRAM */
+    .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_0_start__ = .;
+        *(.ospi_device_0_no_load*)
+        . = ALIGN(4);
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0_RAM
+
+    .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+    {
+        . = ALIGN(4);
+        __ospi_device_1_start__ = .;
+        *(.ospi_device_1_no_load*)
+        . = ALIGN(4);
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1_RAM
+
+    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+    /* OSPI_DEVICE_0 section to be downloaded via debugger */
+    .OSPI_DEVICE_0 :
+    {
+        __ospi_device_0_start__ = .;
+        KEEP(*(.ospi_device_0*))
+        KEEP(*(.code_in_ospi_device_0*))
+        __ospi_device_0_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__);
+    .ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__)
+    {
+        __ospi_device_0_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_0_non_retentive*))
+        __ospi_device_0_non_retentive_end__ = .;
+    } > OSPI_DEVICE_0
+    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+    /* OSPI_DEVICE_1 section to be downloaded via debugger */
+    .OSPI_DEVICE_1 :
+    {
+        __ospi_device_1_start__ = .;
+        KEEP(*(.ospi_device_1*))
+        KEEP(*(.code_in_ospi_device_1*))
+        __ospi_device_1_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+    __ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__);
+    .ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__)
+    {
+        __ospi_device_1_non_retentive_start__ = .;
+        KEEP(*(.ospi_device_1_non_retentive*))
+        __ospi_device_1_non_retentive_end__ = .;
+    } > OSPI_DEVICE_1
+    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
+    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
+    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        . = ALIGN(8);
+        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+        KEEP(*(.heap.*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        /* Place the STD heap here. */
+        KEEP(*(.heap))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+    __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+    .ns_buffer (NOLOAD):
+    {
+        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+        KEEP(*(.ns_buffer*))
+    } > RAM
+
+    /* Data flash. */
+    .data_flash :
+    {
+        . = ORIGIN(DATA_FLASH);
+        __tz_DATA_FLASH_S = .;
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+
+        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+    } > DATA_FLASH
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_S = ORIGIN(SDRAM);
+
+    /* SDRAM */
+    .sdram (NOLOAD):
+    {
+        __SDRAM_Start = .;
+        KEEP(*(.sdram*))
+        KEEP(*(.frame*))
+        __SDRAM_End = .;
+    } > SDRAM
+
+    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
+    __tz_SDRAM_N = __SDRAM_End;
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
+    __tz_ID_CODE_N = __ID_Code_End;
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+    .option_setting_ofs :
+    {
+        __OPTION_SETTING_OFS_Start = .;
+        KEEP(*(.option_setting_ofs0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_ofs2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+        KEEP(*(.option_setting_dualsel))
+        __OPTION_SETTING_OFS_End = .;
+    } > OPTION_SETTING_OFS = 0xFF
+
+    .option_setting_sas :
+    {
+        __OPTION_SETTING_SAS_Start = .;
+        KEEP(*(.option_setting_sas))
+        __OPTION_SETTING_SAS_End = .;
+    } > OPTION_SETTING_SAS = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+    .option_setting_ns :
+    {
+        __OPTION_SETTING_NS_Start = .;
+        KEEP(*(.option_setting_ofs1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_ofs3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_banksel))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_bps3))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps0))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps1))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps2))
+        . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+        KEEP(*(.option_setting_pbps3))
+        __OPTION_SETTING_NS_End = .;
+    } > OPTION_SETTING = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+    .option_setting_s :
+    {
+        __OPTION_SETTING_S_Start = .;
+        KEEP(*(.option_setting_ofs1_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sec))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_pbps_sec3))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs1_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_ofs3_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_banksel_sel))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel0))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel1))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel2))
+        . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+        KEEP(*(.option_setting_bps_sel3))
+        __OPTION_SETTING_S_End = .;
+    } > OPTION_SETTING_S = 0xFF
+
+    /* Symbol required for RA Configuration tool. */
+    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.mk b/hw/bsp/ra/boards/ra4m3_ek/board.mk
index 61a7c5c4a..d668db0ea 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.mk
@@ -13,3 +13,5 @@ LD_FILE = $(BOARD_PATH)/ra4m3_ek.ld
 # For flash-jlink target
 JLINK_DEVICE = R7FA4M3AF
 JLINK_IF     = SWD
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
index eab102de9..327ef71d5 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
@@ -91,11 +91,11 @@ void usbfs_interrupt_handler(void)
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+#if CFG_TUH_ENABLED
   tuh_int_handler(0);
 #endif
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+#if CFG_TUD_ENABLED
   tud_int_handler(0);
 #endif
 }
@@ -104,37 +104,39 @@ void usbfs_resume_handler(void)
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+#if CFG_TUH_ENABLED
   tuh_int_handler(0);
 #endif
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+#if CFG_TUD_ENABLED
   tud_int_handler(0);
 #endif
 }
+
 void usbfs_d0fifo_handler(void)
 {
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+#if CFG_TUH_ENABLED
   tuh_int_handler(0);
 #endif
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+#if CFG_TUD_ENABLED
   tud_int_handler(0);
 #endif
 }
+
 void usbfs_d1fifo_handler(void)
 {
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST
+#if CFG_TUH_ENABLED
   tuh_int_handler(0);
 #endif
 
-#if CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE
+#if CFG_TUD_ENABLED
   tud_int_handler(0);
 #endif
 }

From ffdffc7e06080cfaf94b5c318053576d48cb604e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 16 Mar 2023 23:11:11 +0700
Subject: [PATCH 1548/2085] rename FREERTOS_PORT to FREERTOS_PORTABLE_SRC

also fix trailing spaces
---
 examples/device/cdc_msc_freertos/Makefile       |  8 ++++----
 examples/device/hid_composite_freertos/Makefile | 10 +++++-----
 hw/bsp/ch32v307/family.mk                       | 10 +++++-----
 hw/bsp/d5035_01/board.mk                        |  2 +-
 hw/bsp/da14695_dk_usb/board.mk                  |  3 +--
 hw/bsp/da1469x_dk_pro/board.mk                  |  3 +--
 hw/bsp/ea4088qs/board.mk                        |  2 +-
 hw/bsp/ea4357/board.mk                          |  2 +-
 hw/bsp/fomu/family.mk                           |  4 ++--
 hw/bsp/frdm_k32l2b/board.mk                     |  2 +-
 hw/bsp/frdm_kl25z/board.mk                      |  2 +-
 hw/bsp/gd32vf103/family.mk                      |  4 ++--
 hw/bsp/imxrt/family.mk                          |  4 ++--
 hw/bsp/kuiic/board.mk                           |  4 ++--
 hw/bsp/lpc15/family.mk                          |  4 ++--
 hw/bsp/lpc18/family.mk                          |  2 +-
 hw/bsp/lpc54/family.mk                          |  4 ++--
 hw/bsp/lpc55/family.mk                          |  2 +-
 hw/bsp/lpcxpresso11u37/board.mk                 |  6 +++---
 hw/bsp/lpcxpresso11u68/board.mk                 |  6 +++---
 hw/bsp/lpcxpresso1347/board.mk                  |  4 ++--
 hw/bsp/lpcxpresso1769/board.mk                  |  2 +-
 hw/bsp/lpcxpresso51u68/board.mk                 |  6 +++---
 hw/bsp/mbed1768/board.mk                        |  5 ++---
 hw/bsp/mm32/family.mk                           |  6 +++---
 hw/bsp/msp432e4/family.mk                       |  2 +-
 hw/bsp/ngx4330/board.mk                         |  4 ++--
 hw/bsp/nrf/family.mk                            |  2 +-
 hw/bsp/nutiny_nuc121s/board.mk                  |  2 +-
 hw/bsp/nutiny_nuc125s/board.mk                  |  2 +-
 hw/bsp/nutiny_nuc126v/board.mk                  |  2 +-
 hw/bsp/nutiny_sdk_nuc120/board.mk               |  2 +-
 hw/bsp/nutiny_sdk_nuc505/board.mk               |  6 +++---
 hw/bsp/ra/family.mk                             |  2 +-
 hw/bsp/rx/boards/gr_citrus/board.mk             |  2 +-
 hw/bsp/rx/boards/rx65n_target/board.mk          |  2 +-
 hw/bsp/samd11/family.mk                         |  2 +-
 hw/bsp/samd21/family.mk                         |  2 +-
 hw/bsp/samd51/family.mk                         |  2 +-
 hw/bsp/same54xplainedpro/board.mk               |  2 +-
 hw/bsp/same70_qmtech/board.mk                   |  2 +-
 hw/bsp/same70_xplained/board.mk                 |  4 ++--
 hw/bsp/samg55xplained/board.mk                  |  4 ++--
 hw/bsp/saml2x/family.mk                         |  2 +-
 hw/bsp/sltb009a/board.mk                        |  2 +-
 hw/bsp/stm32f0/family.mk                        |  2 +-
 hw/bsp/stm32f1/family.mk                        |  2 +-
 hw/bsp/stm32f207nucleo/board.mk                 |  2 +-
 hw/bsp/stm32f303disco/board.mk                  |  2 +-
 hw/bsp/stm32f4/family.mk                        |  2 +-
 hw/bsp/stm32f7/family.mk                        |  2 +-
 hw/bsp/stm32g4/family.mk                        |  4 ++--
 hw/bsp/stm32h7/family.mk                        |  3 +--
 hw/bsp/stm32l0/family.mk                        |  2 +-
 hw/bsp/stm32l0538disco/board.mk                 |  4 ++--
 hw/bsp/stm32l4/family.mk                        |  2 +-
 hw/bsp/stm32u5/family.mk                        |  4 ++--
 hw/bsp/stm32wb/family.mk                        |  2 +-
 hw/bsp/tm4c123/family.mk                        |  4 ++--
 hw/bsp/xmc4000/family.mk                        |  2 +-
 60 files changed, 96 insertions(+), 100 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index ed3b3f0ce..73b4ce608 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -3,14 +3,14 @@ DEPS_SUBMODULES += lib/FreeRTOS-Kernel
 include ../../make.mk
 
 FREERTOS_SRC = lib/FreeRTOS-Kernel
-FREERTOS_PORT_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
+FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
 
 INC += \
 	src \
 	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
-	$(TOP)/$(FREERTOS_PORT)
+	$(TOP)/$(FREERTOS_PORTABLE_SRC)
 
 # Example source
 EXAMPLE_SOURCE = \
@@ -27,10 +27,10 @@ SRC_C += \
 	$(FREERTOS_SRC)/queue.c \
 	$(FREERTOS_SRC)/tasks.c \
 	$(FREERTOS_SRC)/timers.c \
-	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c))
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c))
 
 SRC_S += \
-	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.s))
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
 
 # include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
 # SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index f4410b202..9d30fddf7 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -3,21 +3,21 @@ DEPS_SUBMODULES += lib/FreeRTOS-Kernel
 include ../../make.mk
 
 FREERTOS_SRC = lib/FreeRTOS-Kernel
-FREERTOS_PORT_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
+FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
 
 INC += \
 	src \
 	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
-	$(TOP)/$(FREERTOS_PORT)
+	$(TOP)/$(FREERTOS_PORTABLE_SRC)
 
 # Example source
 EXAMPLE_SOURCE = \
 	src/freertos_hook.c \
 	src/main.c \
 	src/usb_descriptors.c
-	
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 # FreeRTOS source, all files in port folder
@@ -26,10 +26,10 @@ SRC_C += \
 	$(FREERTOS_SRC)/queue.c \
 	$(FREERTOS_SRC)/tasks.c \
 	$(FREERTOS_SRC)/timers.c \
-	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c))
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c))
 
 SRC_S += \
-	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.s))
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
 
 # include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
 # SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
diff --git a/hw/bsp/ch32v307/family.mk b/hw/bsp/ch32v307/family.mk
index 15f6724a8..4b06cf429 100644
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@@ -34,23 +34,23 @@ SRC_C += \
 	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_gpio.c \
 	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_misc.c \
 	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_rcc.c \
-	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_usart.c 
-	
+	$(CH32V307_SDK_SRC)/Peripheral/src/ch32v30x_usart.c
+
 SRC_S += \
-	$(CH32V307_SDK_SRC)/Startup/startup_ch32v30x_D8C.S 
+	$(CH32V307_SDK_SRC)/Startup/startup_ch32v30x_D8C.S
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(CH32V307_SDK_SRC)/Peripheral/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = RISC-V
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
 
 # wch-link is not supported yet in official openOCD yet. We need to either use
 # 1. download openocd as part of mounriver studio http://www.mounriver.com/download or
 # 2. compiled from modified source https://github.com/kprasadvnsi/riscv-openocd-wch
 #
-# Note: For Linux, somehow openocd in mounriver studio does not seem to have wch-link enable, 
+# Note: For Linux, somehow openocd in mounriver studio does not seem to have wch-link enable,
 # therefore we need to compile it from source as follows:
 # 	git clone https://github.com/kprasadvnsi/riscv-openocd-wch
 # 	cd riscv-openocd-wch
diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk
index cefd8c935..fc196b339 100644
--- a/hw/bsp/d5035_01/board.mk
+++ b/hw/bsp/d5035_01/board.mk
@@ -52,7 +52,7 @@ INC += \
 	$(TOP)/hw/mcu/microchip/same51/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = ATSAME51J19
diff --git a/hw/bsp/da14695_dk_usb/board.mk b/hw/bsp/da14695_dk_usb/board.mk
index 2ca7f8529..1f7bc1588 100644
--- a/hw/bsp/da14695_dk_usb/board.mk
+++ b/hw/bsp/da14695_dk_usb/board.mk
@@ -31,7 +31,7 @@ INC += \
 	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM33_NTZ/non_secure
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
 
 # For flash-jlink target
 JLINK_DEVICE = DA14695
@@ -52,4 +52,3 @@ flash-dialog: $(BUILD)/$(PROJECT).bin
 	@echo go >> $(BUILD)/$(BOARD).jlink
 	@echo exit >> $(BUILD)/$(BOARD).jlink
 	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
-
diff --git a/hw/bsp/da1469x_dk_pro/board.mk b/hw/bsp/da1469x_dk_pro/board.mk
index d9dd5cd65..f9bf480de 100644
--- a/hw/bsp/da1469x_dk_pro/board.mk
+++ b/hw/bsp/da1469x_dk_pro/board.mk
@@ -31,7 +31,7 @@ INC += \
 	$(TOP)/$(MCU_FAMILY_DIR)/SDK_10.0.8.105/sdk/bsp/include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM33_NTZ/non_secure
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
 
 # For flash-jlink target
 JLINK_DEVICE = DA14699
@@ -52,4 +52,3 @@ flash-dialog: $(BUILD)/$(PROJECT).bin
 	@echo go >> $(BUILD)/$(BOARD).jlink
 	@echo exit >> $(BUILD)/$(BOARD).jlink
 	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
-
diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/ea4088qs/board.mk
index 54195b20c..376840fb1 100644
--- a/hw/bsp/ea4088qs/board.mk
+++ b/hw/bsp/ea4088qs/board.mk
@@ -37,7 +37,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = LPC4088
diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
index 4556e98f6..6fd229166 100644
--- a/hw/bsp/ea4357/board.mk
+++ b/hw/bsp/ea4357/board.mk
@@ -39,7 +39,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc/config_43xx
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = LPC4357_M4
diff --git a/hw/bsp/fomu/family.mk b/hw/bsp/fomu/family.mk
index 8f8f3d011..d0b819120 100644
--- a/hw/bsp/fomu/family.mk
+++ b/hw/bsp/fomu/family.mk
@@ -19,12 +19,12 @@ INC += \
 	$(TOP)/$(FAMILY_PATH)/include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RISC-V
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
 
 # flash using dfu-util
 $(BUILD)/$(PROJECT).dfu: $(BUILD)/$(PROJECT).bin
 	@echo "Create $@"
 	python $(TOP)/hw/bsp/$(BOARD)/dfu.py -b $^ -D 0x1209:0x5bf0 $@
-	
+
 flash: $(BUILD)/$(PROJECT).dfu
 	dfu-util -D $^
diff --git a/hw/bsp/frdm_k32l2b/board.mk b/hw/bsp/frdm_k32l2b/board.mk
index f922fc433..feb0a25f4 100644
--- a/hw/bsp/frdm_k32l2b/board.mk
+++ b/hw/bsp/frdm_k32l2b/board.mk
@@ -39,7 +39,7 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = MKL25Z128xxx4
diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/frdm_kl25z/board.mk
index 2ac089404..fd616f7ed 100644
--- a/hw/bsp/frdm_kl25z/board.mk
+++ b/hw/bsp/frdm_kl25z/board.mk
@@ -40,7 +40,7 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_MKL25Z4.S
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = MKL25Z128xxx4
diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk
index c0c144f5c..1725559c4 100644
--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@@ -44,7 +44,7 @@ SRC_C += \
 	$(LIBC_STUBS)/isatty.c \
 	$(LIBC_STUBS)/fstat.c \
 	$(LIBC_STUBS)/lseek.c \
-	$(LIBC_STUBS)/read.c 
+	$(LIBC_STUBS)/read.c
 
 SRC_S += \
 	$(STARTUP_ASM)/startup_gd32vf103.S \
@@ -57,7 +57,7 @@ INC += \
 	$(TOP)/$(GD32VF103_SDK_SOC)/Common/Include/Usb
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RISC-V
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
 
 # For flash-jlink target
 JLINK_IF = jtag
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index f2273cb56..6788de8df 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -30,7 +30,7 @@ MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
 # All source paths should be relative to the top level.
 LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx_flexspi_nor.ld
 
-# TODO for net_lwip_webserver example, but may not needed !! 
+# TODO for net_lwip_webserver example, but may not needed !!
 LDFLAGS += \
 	-Wl,--defsym,__stack_size__=0x800 \
 
@@ -59,7 +59,7 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7/r0p1
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
 
 # UF2 generation, iMXRT need to strip to text only before conversion
 APPLICATION_ADDR = 0x6000C000
diff --git a/hw/bsp/kuiic/board.mk b/hw/bsp/kuiic/board.mk
index 94646dbde..cb3459586 100644
--- a/hw/bsp/kuiic/board.mk
+++ b/hw/bsp/kuiic/board.mk
@@ -35,12 +35,12 @@ INC += \
 	$(TOP)/$(SDK_DIR)/drivers/port \
 	$(TOP)/$(SDK_DIR)/drivers/lpuart \
 	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers 
+	$(TOP)/$(MCU_DIR)/drivers
 
 SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = MKL25Z128xxx4
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
index fee0e0106..0ad1220d6 100644
--- a/hw/bsp/lpc15/family.mk
+++ b/hw/bsp/lpc15/family.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -D__USE_LPCOPEN \
   -DCFG_EXAMPLE_MSC_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_LPC15XX \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual
@@ -36,4 +36,4 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index 8ba05c9c9..fbe6ad834 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -34,4 +34,4 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc/config_18xx
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index 3af679bda..0ec59f9bf 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -11,7 +11,7 @@ CFLAGS += \
   -mfloat-abi=hard \
   -mfpu=fpv4-sp-d16 \
   -DCFG_TUSB_MCU=OPT_MCU_LPC54XXX \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
 ifeq ($(PORT), 1)
   $(info "PORT1 High Speed")
@@ -51,4 +51,4 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index 58fc18a5c..789f7727d 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -65,4 +65,4 @@ SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM33_NTZ/non_secure
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk
index a9e63ad67..61e5eda7e 100644
--- a/hw/bsp/lpcxpresso11u37/board.mk
+++ b/hw/bsp/lpcxpresso11u37/board.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=redundant-decls
@@ -36,11 +36,11 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = LPC11U37/401
 
-# flash using pyocd 
+# flash using pyocd
 flash: $(BUILD)/$(PROJECT).hex
 	pyocd flash -t lpc11u37 $<
diff --git a/hw/bsp/lpcxpresso11u68/board.mk b/hw/bsp/lpcxpresso11u68/board.mk
index 9647b8b8f..cd6ad3617 100644
--- a/hw/bsp/lpcxpresso11u68/board.mk
+++ b/hw/bsp/lpcxpresso11u68/board.mk
@@ -11,7 +11,7 @@ CFLAGS += \
   -D__USE_LPCOPEN \
   -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc11u6x/lpc_chip_11u6x
 
@@ -32,11 +32,11 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = LPC11U68
 
-# flash using pyocd 
+# flash using pyocd
 flash: $(BUILD)/$(PROJECT).hex
 	pyocd flash -t lpc11u68 $<
diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk
index 79405c896..25d6fa7a3 100644
--- a/hw/bsp/lpcxpresso1347/board.mk
+++ b/hw/bsp/lpcxpresso1347/board.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
 # startup.c and lpc_types.h cause following errors
 CFLAGS += -Wno-error=strict-prototypes -Wno-error=redundant-decls
@@ -36,7 +36,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = LPC1347
diff --git a/hw/bsp/lpcxpresso1769/board.mk b/hw/bsp/lpcxpresso1769/board.mk
index ecafccc49..d459c8b7b 100644
--- a/hw/bsp/lpcxpresso1769/board.mk
+++ b/hw/bsp/lpcxpresso1769/board.mk
@@ -34,7 +34,7 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = LPC1769
diff --git a/hw/bsp/lpcxpresso51u68/board.mk b/hw/bsp/lpcxpresso51u68/board.mk
index 6e39bbcad..b1a126c51 100644
--- a/hw/bsp/lpcxpresso51u68/board.mk
+++ b/hw/bsp/lpcxpresso51u68/board.mk
@@ -9,7 +9,7 @@ CFLAGS += \
   -DCPU_LPC51U68JBD64 \
   -DCFG_TUSB_MCU=OPT_MCU_LPC51UXX \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' 
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
@@ -36,14 +36,14 @@ INC += \
 	$(TOP)/$(SDK_DIR)/drivers/common \
 	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio	
+	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
 
 SRC_S += $(MCU_DIR)/gcc/startup_LPC51U68.S
 
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 JLINK_DEVICE = LPC51U68
 PYOCD_TARGET = LPC51U68
diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk
index a65d6eacb..6940bbb55 100644
--- a/hw/bsp/mbed1768/board.mk
+++ b/hw/bsp/mbed1768/board.mk
@@ -34,12 +34,11 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = LPC1768
 
-# flash using pyocd 
+# flash using pyocd
 flash: $(BUILD)/$(PROJECT).hex
 	pyocd flash -t lpc1768 $<
-
diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk
index c1147b4e9..81af0d166 100644
--- a/hw/bsp/mm32/family.mk
+++ b/hw/bsp/mm32/family.mk
@@ -11,7 +11,7 @@ CFLAGS += \
   -mcpu=cortex-m3 \
   -mfloat-abi=soft \
   -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_MM32F327X 
+  -DCFG_TUSB_MCU=OPT_MCU_MM32F327X
 
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=cast-qual
@@ -22,7 +22,7 @@ SRC_C += \
 	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_gpio.c \
 	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_rcc.c \
 	$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Src/hal_uart.c \
-	
+
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
@@ -30,7 +30,7 @@ INC += \
 	$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
 
 # flash target using on-board
 flash: flash-jlink
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
index 7f823b1aa..2383bc604 100644
--- a/hw/bsp/msp432e4/family.mk
+++ b/hw/bsp/msp432e4/family.mk
@@ -34,7 +34,7 @@ INC += \
 SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = MSP432E401Y
diff --git a/hw/bsp/ngx4330/board.mk b/hw/bsp/ngx4330/board.mk
index 26f8ae760..99c1f194c 100644
--- a/hw/bsp/ngx4330/board.mk
+++ b/hw/bsp/ngx4330/board.mk
@@ -37,11 +37,11 @@ INC += \
 	$(TOP)/$(MCU_DIR)/inc/config_43xx
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = LPC4330
-JLINK_IF = swd 
+JLINK_IF = swd
 
 # flash using jlink
 flash: flash-jlink
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index c79d7e654..4102c8187 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -42,7 +42,7 @@ SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_$(MCU_VARIANT).S
 ASFLAGS += -D__HEAP_SIZE=0
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = $(MCU_VARIANT)_xxaa
diff --git a/hw/bsp/nutiny_nuc121s/board.mk b/hw/bsp/nutiny_nuc121s/board.mk
index 69092dfd5..aa8f00e70 100644
--- a/hw/bsp/nutiny_nuc121s/board.mk
+++ b/hw/bsp/nutiny_nuc121s/board.mk
@@ -35,7 +35,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC121SC2AE
diff --git a/hw/bsp/nutiny_nuc125s/board.mk b/hw/bsp/nutiny_nuc125s/board.mk
index 0272564c4..bf7610a7b 100644
--- a/hw/bsp/nutiny_nuc125s/board.mk
+++ b/hw/bsp/nutiny_nuc125s/board.mk
@@ -31,7 +31,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc121_125/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC125SC2AE
diff --git a/hw/bsp/nutiny_nuc126v/board.mk b/hw/bsp/nutiny_nuc126v/board.mk
index 3d9e239af..46f53420c 100644
--- a/hw/bsp/nutiny_nuc126v/board.mk
+++ b/hw/bsp/nutiny_nuc126v/board.mk
@@ -37,7 +37,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc126/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC126VG4AE
diff --git a/hw/bsp/nutiny_sdk_nuc120/board.mk b/hw/bsp/nutiny_sdk_nuc120/board.mk
index b06d4873e..b1f9245a6 100644
--- a/hw/bsp/nutiny_sdk_nuc120/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc120/board.mk
@@ -30,7 +30,7 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc100_120/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = NUC120LE3
diff --git a/hw/bsp/nutiny_sdk_nuc505/board.mk b/hw/bsp/nutiny_sdk_nuc505/board.mk
index 3118dc7f8..3e48d3998 100644
--- a/hw/bsp/nutiny_sdk_nuc505/board.mk
+++ b/hw/bsp/nutiny_sdk_nuc505/board.mk
@@ -42,14 +42,14 @@ INC += \
   $(TOP)/hw/mcu/nuvoton/nuc505/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = NUC505YO13Y
 
 # Note
-# To be able to program the SPI flash, it need to boot with ICP mode "1011". 
-# However, in ICP mode, opencod cannot establish connection to the mcu. 
+# To be able to program the SPI flash, it need to boot with ICP mode "1011".
+# However, in ICP mode, opencod cannot establish connection to the mcu.
 # Therefore, there is no easy command line flash for NUC505
 # It is probably better to just use Nuvoton NuMicro ICP programming on windows to program the board
 # - 1111 "SPI" (run from internal flash)
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 3c681a7c3..d48272e61 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -52,4 +52,4 @@ INC += \
 
 # For freeRTOS port source
 # hack to use the port provided by renesas
-FREERTOS_PORT = hw/mcu/renesas/fsp/ra/fsp/src/rm_freertos_port
+FREERTOS_PORTABLE_SRC = hw/mcu/renesas/fsp/ra/fsp/src/rm_freertos_port
diff --git a/hw/bsp/rx/boards/gr_citrus/board.mk b/hw/bsp/rx/boards/gr_citrus/board.mk
index 7bef40614..e3af8d9b0 100644
--- a/hw/bsp/rx/boards/gr_citrus/board.mk
+++ b/hw/bsp/rx/boards/gr_citrus/board.mk
@@ -9,7 +9,7 @@ MCU_DIR = hw/mcu/renesas/rx/rx63n
 LD_FILE = $(BOARD_PATH)/r5f5631fd.ld
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RX600
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RX600
 
 # For flash-jlink target
 JLINK_DEVICE = R5F5631F
diff --git a/hw/bsp/rx/boards/rx65n_target/board.mk b/hw/bsp/rx/boards/rx65n_target/board.mk
index 18c7d354d..90bc0efbb 100644
--- a/hw/bsp/rx/boards/rx65n_target/board.mk
+++ b/hw/bsp/rx/boards/rx65n_target/board.mk
@@ -12,7 +12,7 @@ MCU_DIR = hw/mcu/renesas/rx/rx65n
 LD_FILE = $(BOARD_PATH)/r5f565ne.ld
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/RX600
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RX600
 
 # For flash-jlink target
 JLINK_DEVICE = R5F565NE
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index ef1f1424d..dc6678b30 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -37,4 +37,4 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd11/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index 158ea000f..6d02d7fa6 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -37,7 +37,7 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd21/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
index aa3af5318..3ecc5aa66 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd51/family.mk
@@ -38,7 +38,7 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd51/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
index 7d7ede0f0..1c6732231 100644
--- a/hw/bsp/same54xplainedpro/board.mk
+++ b/hw/bsp/same54xplainedpro/board.mk
@@ -38,7 +38,7 @@ INC += \
 	$(TOP)/hw/mcu/microchip/same54/CMSIS/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = ATSAME54P20
diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
index 77dfbe499..1dcb8bfcd 100644
--- a/hw/bsp/same70_qmtech/board.mk
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -44,7 +44,7 @@ INC += \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7
 
 # For flash-jlink target
 JLINK_DEVICE = SAME70N19B
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index 2f94512d0..95c4aaaa2 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -44,7 +44,7 @@ INC += \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7
 
 # For flash-jlink target
 JLINK_DEVICE = SAME70Q21B
@@ -53,4 +53,4 @@ JLINK_DEVICE = SAME70Q21B
 # Note: SAME70's GPNVM1 must be set to 1 to boot from flash with
 # 	edbg -t same70 -F w0,1,1
 flash: $(BUILD)/$(PROJECT).bin
-	edbg --verbose -t same70 -pv -f $< 
+	edbg --verbose -t same70 -pv -f $<
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index 886430231..7cc9487fd 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -42,11 +42,11 @@ INC += \
 	$(TOP)/$(ASF_DIR)/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = ATSAMG55J19
 
 # flash using edbg from https://github.com/ataradov/edbg
 flash: $(BUILD)/$(PROJECT).bin
-	edbg --verbose -t samg55 -pv -f $< 
+	edbg --verbose -t samg55 -pv -f $<
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index 8ea553514..6022158de 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -39,7 +39,7 @@ INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk
index d4318b5e2..f9c1dd4db 100644
--- a/hw/bsp/sltb009a/board.mk
+++ b/hw/bsp/sltb009a/board.mk
@@ -35,7 +35,7 @@ INC += \
   $(TOP)/hw/bsp/$(BOARD)
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = EFM32GG12B810F1024
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index d57b14d53..08e349a81 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -53,4 +53,4 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index 72ca259b7..cd1d587f1 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -44,7 +44,7 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f103c8
diff --git a/hw/bsp/stm32f207nucleo/board.mk b/hw/bsp/stm32f207nucleo/board.mk
index f418c6c04..55581e1ec 100644
--- a/hw/bsp/stm32f207nucleo/board.mk
+++ b/hw/bsp/stm32f207nucleo/board.mk
@@ -39,7 +39,7 @@ INC += \
   $(TOP)/hw/bsp/$(BOARD)
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM3
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f207zg
diff --git a/hw/bsp/stm32f303disco/board.mk b/hw/bsp/stm32f303disco/board.mk
index 371aba0f3..b81de4ee4 100644
--- a/hw/bsp/stm32f303disco/board.mk
+++ b/hw/bsp/stm32f303disco/board.mk
@@ -40,7 +40,7 @@ INC += \
   $(TOP)/hw/bsp/$(BOARD)
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f303vc
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index bc9504038..394c4a72f 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -52,7 +52,7 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index 0dcaa0453..b44381586 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -66,4 +66,4 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7/r0p1
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk
index f8f04384a..5ed84422d 100644
--- a/hw/bsp/stm32g4/family.mk
+++ b/hw/bsp/stm32g4/family.mk
@@ -12,7 +12,7 @@ include $(TOP)/$(BOARD_PATH)/board.mk
 # --------------
 CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32G4
-  
+
 # GCC Flags
 GCC_CFLAGS += \
   -flto \
@@ -53,7 +53,7 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index 2641edba5..8042248a8 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -68,5 +68,4 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM7/r0p1
-
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
diff --git a/hw/bsp/stm32l0/family.mk b/hw/bsp/stm32l0/family.mk
index 622fa61e0..67a5c69b8 100644
--- a/hw/bsp/stm32l0/family.mk
+++ b/hw/bsp/stm32l0/family.mk
@@ -37,4 +37,4 @@ INC += \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/hw/bsp/stm32l0538disco/board.mk b/hw/bsp/stm32l0538disco/board.mk
index b25380c5c..72e887adf 100644
--- a/hw/bsp/stm32l0538disco/board.mk
+++ b/hw/bsp/stm32l0538disco/board.mk
@@ -41,12 +41,12 @@ INC += \
   $(TOP)/hw/bsp/$(BOARD)
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # For flash-jlink target
 JLINK_DEVICE = STM32L053R8
 
-# Path to STM32 Cube Programmer CLI, should be added into system path 
+# Path to STM32 Cube Programmer CLI, should be added into system path
 STM32Prog = STM32_Programmer_CLI
 
 # flash target using on-board stlink
diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index 3ba459dc2..0e84d1af0 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -55,7 +55,7 @@ INC += \
 	$(TOP)/$(BOARD_PATH)
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index 1cfb81e43..23d7f4dda 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -16,7 +16,7 @@ CFLAGS += \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32U5
 
-# suppress warning caused by vendor mcu driver 
+# suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=undef -Wno-error=unused-parameter
 
 #src/portable/st/synopsys/dcd_synopsys.c
@@ -39,7 +39,7 @@ INC += \
 	$(TOP)/$(BOARD_PATH)
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM33_NTZ/non_secure
+FREERTOS_PORTABLE_SRC = ARM_CM33_NTZ/non_secure
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32wb/family.mk b/hw/bsp/stm32wb/family.mk
index 66f8ff4e2..97210889c 100644
--- a/hw/bsp/stm32wb/family.mk
+++ b/hw/bsp/stm32wb/family.mk
@@ -38,7 +38,7 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/tm4c123/family.mk b/hw/bsp/tm4c123/family.mk
index 73b65f00c..021b47fd3 100644
--- a/hw/bsp/tm4c123/family.mk
+++ b/hw/bsp/tm4c123/family.mk
@@ -12,7 +12,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \
   -uvectors \
   -DTM4C123GH6PM
-  
+
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
 
@@ -33,4 +33,4 @@ SRC_C += \
 	$(MCU_DIR)/Source/GCC/tm4c123_startup.c
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk
index 134098dac..1094f3b72 100644
--- a/hw/bsp/xmc4000/family.mk
+++ b/hw/bsp/xmc4000/family.mk
@@ -37,4 +37,4 @@ INC += \
 	$(TOP)/$(MCU_DIR)/XMCLib/inc
 
 # For freeRTOS port source
-FREERTOS_PORT = $(FREERTOS_PORT_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F

From e7d212f33760f13b0102a307569aac0ed8e14bd2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 16 Mar 2023 23:21:15 +0700
Subject: [PATCH 1549/2085] more fix

---
 hw/bsp/stm32u5/family.mk                | 2 +-
 src/portable/renesas/rusb2/rusb2_ra.h   | 6 +++---
 src/portable/renesas/rusb2/rusb2_rx.h   | 6 +++---
 src/portable/renesas/rusb2/rusb2_type.h | 6 +++---
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index 23d7f4dda..e1c496dee 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -39,7 +39,7 @@ INC += \
 	$(TOP)/$(BOARD_PATH)
 
 # For freeRTOS port source
-FREERTOS_PORTABLE_SRC = ARM_CM33_NTZ/non_secure
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 24658e95a..5785850cc 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _LINK_RA_H_
-#define _LINK_RA_H_
+#ifndef _RUSB2_RA_H_
+#define _RUSB2_RA_H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -57,4 +57,4 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void)
 }
 #endif
 
-#endif /* _LINK_RA_H_ */
+#endif /* _RUSB2_RA_H_ */
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
index c28689df1..397c0d56c 100644
--- a/src/portable/renesas/rusb2/rusb2_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -26,8 +26,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _LINK_RX_H_
-#define _LINK_RX_H_
+#ifndef _RUSB2_RX_H_
+#define _RUSB2_RX_H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -71,4 +71,4 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void)
 }
 #endif
 
-#endif /* _LINK_RX_H_ */
+#endif /* _RUSB2_RX_H_ */
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 6a5c7f8ff..7a2898366 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_LINK_TYPE_H_
-#define _TUSB_LINK_TYPE_H_
+#ifndef _TUSB_RUSB2_TYPE_H_
+#define _TUSB_RUSB2_TYPE_H_
 
 #include <stdint.h>
 
@@ -1666,4 +1666,4 @@ TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect of
 }
 #endif
 
-#endif /* _TUSB_LINK_TYPE_H_ */
+#endif /* _TUSB_RUSB2_TYPE_H_ */

From c12795734c3434db999d3198173335050a3b59a4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 10:59:08 +0700
Subject: [PATCH 1550/2085] reduce number  of supported RA to only those that
 is tested

---
 README.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index a8d471a03..566af8584 100644
--- a/README.rst
+++ b/README.rst
@@ -51,7 +51,7 @@ The stack supports the following MCUs:
 - **Renesas:**
 
 	- RX Series: 63N, 65N, 72N
-	- RA Series: RA2A1, RA2E1, RA2E2, RA2l1, RA4E1, RA4M1, RA4M2, RA4M3, RA4W1, RA6E1, RA6M1, RA6M2, RA6M3, RA6M4, RA6M5, RA6T1, RA6T2
+	- RA Series: RA4M1, RA4M3
 
 - **Silabs:** EFM32GG
 - **Sony:** CXD56

From f349ae77029c3a82bd9509c1ad57e3e6cd815596 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 13:58:01 +0700
Subject: [PATCH 1551/2085] fix enumerate one device at a time

---
 src/host/usbh.c | 35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 12b0ed203..45a2a0c66 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -54,8 +54,6 @@
 // USBH-HCD common data structure
 //--------------------------------------------------------------------+
 
-// device0 struct must be strictly a subset of normal device struct
-// TODO refactor later
 typedef struct
 {
   // port
@@ -63,15 +61,13 @@ typedef struct
   uint8_t hub_addr;
   uint8_t hub_port;
   uint8_t speed;
+  volatile uint8_t enumerating;
 
-  struct TU_ATTR_PACKED
-  {
-    volatile uint8_t connected  : 1;
-    volatile uint8_t addressed  : 1;
-    volatile uint8_t configured : 1;
-    volatile uint8_t suspended  : 1;
-  };
-
+//  struct TU_ATTR_PACKED {
+//    uint8_t          speed       : 4; // packed speed to save footprint
+//    volatile uint8_t enumerating : 1;
+//    uint8_t TU_RESERVED : 3;
+//  };
 } usbh_dev0_t;
 
 typedef struct {
@@ -402,10 +398,18 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
     switch (event.event_id)
     {
       case HCD_EVENT_DEVICE_ATTACH:
-        // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
+        // due to the shared _usbh_ctrl_buf, we must complete enumerating
         // one device before enumerating another one.
-        TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
-        enum_new_device(&event);
+        if ( _dev0.enumerating )
+        {
+          TU_LOG1("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
+          osal_queue_send(_usbh_q, &event, in_isr);
+        }else
+        {
+          TU_LOG1("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
+          _dev0.enumerating = 1;
+          enum_new_device(&event);
+        }
       break;
 
       case HCD_EVENT_DEVICE_REMOVE:
@@ -1623,6 +1627,9 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
 
 static void enum_full_complete(void)
 {
+  // mark enumeration as complete
+  _dev0.enumerating = 0;
+
 #if CFG_TUH_HUB
   // get next hub status
   if (_dev0.hub_addr) hub_edpt_status_xfer(_dev0.hub_addr);

From 317177c83d3c28d66bfe60be971ff37a44bd84df Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 14:06:25 +0700
Subject: [PATCH 1552/2085] update host example, add pio-pico-usb for rp2040

---
 examples/host/bare_api/CMakeLists.txt             | 5 +++++
 examples/host/bare_api/src/tusb_config.h          | 4 ++--
 examples/host/cdc_msc_hid/CMakeLists.txt          | 5 +++++
 examples/host/cdc_msc_hid/src/tusb_config.h       | 6 +++---
 examples/host/hid_controller/CMakeLists.txt       | 5 +++++
 examples/host/hid_controller/src/tusb_config.h    | 7 +++----
 examples/host/msc_file_explorer/CMakeLists.txt    | 4 ++++
 examples/host/msc_file_explorer/src/tusb_config.h | 6 +++---
 hw/bsp/rp2040/family.mk                           | 3 ---
 src/class/cdc/cdc_host.c                          | 8 ++++----
 src/common/tusb_common.h                          | 6 ++++++
 src/common/tusb_types.h                           | 5 -----
 12 files changed, 40 insertions(+), 24 deletions(-)

diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 4879613b4..616edd4ac 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -25,3 +25,8 @@ target_include_directories(${PROJECT} PUBLIC
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
+
+# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
+if(FAMILY STREQUAL "rp2040")
+  family_add_pico_pio_usb(${PROJECT})
+endif()
diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index 701aa6d90..64be41a4e 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -100,7 +100,7 @@
 
 // max device support (excluding hub device)
 // 1 hub typically has 4 ports
-#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1)
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
 
 // Max endpoint per device
 #define CFG_TUH_ENDPOINT_MAX        8
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index dbba6bf44..d7d1a54d7 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -28,3 +28,8 @@ target_include_directories(${PROJECT} PUBLIC
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
+
+# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
+if(FAMILY STREQUAL "rp2040")
+  family_add_pico_pio_usb(${PROJECT})
+endif()
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 139a921d1..4b50f2096 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -101,8 +101,8 @@
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
 
-// max device support (excluding hub device)
-#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
 
 //------------- HID -------------//
 #define CFG_TUH_HID_EPIN_BUFSIZE    64
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index aa50b5a52..ac3070b82 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -26,3 +26,8 @@ target_include_directories(${PROJECT} PUBLIC
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
+
+# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
+if(FAMILY STREQUAL "rp2040")
+  family_add_pico_pio_usb(${PROJECT})
+endif()
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index e6d6f873d..2e0dd0dbe 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -101,9 +101,8 @@
 #define CFG_TUH_MSC                 0
 #define CFG_TUH_VENDOR              0
 
-// max device support (excluding hub device)
-// 1 hub typically has 4 ports
-#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1)
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
 
 //------------- HID -------------//
 
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 2c06eafee..7955b3078 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -32,3 +32,7 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT})
 
+# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
+if(FAMILY STREQUAL "rp2040")
+  family_add_pico_pio_usb(${PROJECT})
+endif()
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index ddf8368f4..eaf3ea6d4 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -101,8 +101,8 @@
 #define CFG_TUH_HID                 0 // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_VENDOR              0
 
-// max device support (excluding hub device)
-#define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
 
 //------------- MSC -------------//
 #define CFG_TUH_MSC_MAXLUN    4 // typical for most card reader
diff --git a/hw/bsp/rp2040/family.mk b/hw/bsp/rp2040/family.mk
index cf6b53793..25d1ad9c5 100644
--- a/hw/bsp/rp2040/family.mk
+++ b/hw/bsp/rp2040/family.mk
@@ -13,9 +13,6 @@ $(BUILD):
 all: $(BUILD)
 	$(MAKE) -C $(BUILD)
 
-clean:
-	$(RM) -rf $(BUILD)
-
 flash: flash-pyocd
 flash-uf2:
 	@$(CP) $(BUILD)/$(PROJECT).uf2 /media/$(USER)/RPI-RP2
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index e9c3d34cb..011ee49dc 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -97,7 +97,7 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
     }
   }
 
-  return TUSB_INDEX_INVALID;
+  return TU_INDEX_INVALID_8;
 }
 
 
@@ -124,7 +124,7 @@ uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num)
     if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i;
   }
 
-  return TUSB_INDEX_INVALID;
+  return TU_INDEX_INVALID_8;
 }
 
 bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info)
@@ -533,7 +533,7 @@ static void process_cdc_config(tuh_xfer_t* xfer)
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  TU_ASSERT(idx != TUSB_INDEX_INVALID, );
+  TU_ASSERT(idx != TU_INDEX_INVALID_8, );
 
   switch(state)
   {
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 957491aa9..faccf8726 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -75,6 +75,12 @@
 
 #include "tusb_timeout.h" // TODO remove
 
+enum
+{
+  TU_INDEX_INVALID_8 = 0xFFu
+};
+
+
 //--------------------------------------------------------------------+
 // Optional API implemented by application if needed
 // TODO move to a more ovious place/file
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 7266a525e..d567bd482 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -273,11 +273,6 @@ enum
   CONTROL_STAGE_ACK
 };
 
-enum
-{
-  TUSB_INDEX_INVALID = 0xff
-};
-
 //--------------------------------------------------------------------+
 // USB Descriptors
 //--------------------------------------------------------------------+

From e1fda007f6ad7f05452cd2bb02f8578197b9339e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 14:46:02 +0700
Subject: [PATCH 1553/2085] minor refactor to invalid index

---
 src/host/usbh.c | 26 +++++++++++---------------
 1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 45a2a0c66..aeab681e9 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -118,10 +118,6 @@ typedef struct {
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-// Invalid driver ID in itf2drv[] ep2drv[][] mapping
-enum { DRVID_INVALID = 0xFFu };
-enum { CONTROLLER_INVALID = 0xFFu };
-
 #if CFG_TUSB_DEBUG >= 2
   #define DRIVER_NAME(_name)    .name = _name,
 #else
@@ -199,7 +195,7 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1
 // sum of end device + hub
 #define TOTAL_DEVICES   (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB)
 
-static uint8_t _usbh_controller = CONTROLLER_INVALID;
+static uint8_t _usbh_controller = TU_INDEX_INVALID_8;
 
 // Device with address = 0 for enumeration
 static usbh_dev0_t _dev0;
@@ -307,13 +303,13 @@ tusb_speed_t tuh_speed_get (uint8_t dev_addr)
 static void clear_device(usbh_device_t* dev)
 {
   tu_memclr(dev, sizeof(usbh_device_t));
-  memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
-  memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
+  memset(dev->itf2drv, TU_INDEX_INVALID_8, sizeof(dev->itf2drv)); // invalid mapping
+  memset(dev->ep2drv , TU_INDEX_INVALID_8, sizeof(dev->ep2drv )); // invalid mapping
 }
 
 bool tuh_inited(void)
 {
-  return _usbh_controller != CONTROLLER_INVALID;
+  return _usbh_controller != TU_INDEX_INVALID_8;
 }
 
 bool tuh_init(uint8_t controller_id)
@@ -402,11 +398,11 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
         // one device before enumerating another one.
         if ( _dev0.enumerating )
         {
-          TU_LOG1("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
+          TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
           osal_queue_send(_usbh_q, &event, in_isr);
         }else
         {
-          TU_LOG1("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
+          TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
           _dev0.enumerating = 1;
           enum_new_device(&event);
         }
@@ -1362,11 +1358,11 @@ static void process_enumeration(tuh_xfer_t* xfer)
 
       dev->configured = 1;
 
-      // Start the Set Configuration process for interfaces (itf = DRVID_INVALID)
+      // Start the Set Configuration process for interfaces (itf = TU_INDEX_INVALID_8)
       // Since driver can perform control transfer within its set_config, this is done asynchronously.
       // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete()
-      // TODO use separated API instead of using DRVID_INVALID
-      usbh_driver_set_config_complete(daddr, DRVID_INVALID);
+      // TODO use separated API instead of using TU_INDEX_INVALID_8
+      usbh_driver_set_config_complete(daddr, TU_INDEX_INVALID_8);
     }
     break;
 
@@ -1566,7 +1562,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
           uint8_t const itf_num = desc_itf->bInterfaceNumber+i;
 
           // Interface number must not be used already
-          TU_ASSERT( DRVID_INVALID == dev->itf2drv[itf_num] );
+          TU_ASSERT( TU_INDEX_INVALID_8 == dev->itf2drv[itf_num] );
           dev->itf2drv[itf_num] = drv_id;
         }
 
@@ -1600,7 +1596,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
     // IAD binding interface such as CDCs should return itf_num + 1 when complete
     // with usbh_driver_set_config_complete()
     uint8_t const drv_id = dev->itf2drv[itf_num];
-    if (drv_id != DRVID_INVALID)
+    if (drv_id != TU_INDEX_INVALID_8)
     {
       usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
       TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num);

From 511f5be8b34f0a28b20773f2d39bda575f07065f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 14:46:34 +0700
Subject: [PATCH 1554/2085] bump up pico-pio-usb dependency

---
 tools/get_deps.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index 3aa95ece5..2d4fcf5de 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -17,8 +17,8 @@ deps_list = {
     'hw/mcu/nxp/lpcopen'                       : ['43c45c85405a5dd114fff0ea95cca62837740c13', 'https://github.com/hathach/nxp_lpcopen.git'                    ],
     'hw/mcu/nxp/mcux-sdk'                      : ['ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294', 'https://github.com/NXPmicro/mcux-sdk.git'                      ],
     'hw/mcu/nxp/nxp_sdk'                       : ['845c8fc49b6fb660f06a5c45225494eacb06f00c', 'https://github.com/hathach/nxp_sdk.git'                        ],
-    'hw/mcu/raspberry_pi/Pico-PIO-USB'         : ['9ff3f52fd3c1f81532bce8dd311aa8fc8d9b2665', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git'            ],
-    'hw/mcu/renesas/fsp'                       : ['8dc14709f2a6518b43f71efad70d900b7718d9f1', 'https://github.com/renesas/fsp.git'                            ],    
+    'hw/mcu/raspberry_pi/Pico-PIO-USB'         : ['c3715ce94b6f6391856de56081d4d9b3e98fa93d', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git'            ],
+    'hw/mcu/renesas/fsp'                       : ['8dc14709f2a6518b43f71efad70d900b7718d9f1', 'https://github.com/renesas/fsp.git'                            ],
     'hw/mcu/renesas/rx'                        : ['706b4e0cf485605c32351e2f90f5698267996023', 'https://github.com/kkitayam/rx_device.git'                     ],
     'hw/mcu/silabs/cmsis-dfp-efm32gg12b'       : ['f1c31b7887669cb230b3ea63f9b56769078960bc', 'https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git'       ],
     'hw/mcu/sony/cxd56/spresense-exported-sdk' : ['2ec2a1538362696118dc3fdf56f33dacaf8f4067', 'https://github.com/sonydevworld/spresense-exported-sdk.git'    ],

From 6763521ec7f3979dcd7bc0b37a756f8d13399cbb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 15:31:21 +0700
Subject: [PATCH 1555/2085] remove all submodules

---
 .gitmodules         |  9 ---------
 lib/FreeRTOS-Kernel |  1 -
 lib/lwip            |  1 -
 tools/get_deps.py   | 30 +++++++++++++++++++++---------
 tools/uf2           |  1 -
 5 files changed, 21 insertions(+), 21 deletions(-)
 delete mode 160000 lib/FreeRTOS-Kernel
 delete mode 160000 lib/lwip
 delete mode 160000 tools/uf2

diff --git a/.gitmodules b/.gitmodules
index 469192026..e69de29bb 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,9 +0,0 @@
-[submodule "tools/uf2"]
-	path = tools/uf2
-	url = https://github.com/microsoft/uf2.git
-[submodule "lib/lwip"]
-	path = lib/lwip
-	url = https://github.com/lwip-tcpip/lwip.git
-[submodule "lib/FreeRTOS-Kernel"]
-	path = lib/FreeRTOS-Kernel
-	url = https://github.com/FreeRTOS/FreeRTOS-Kernel.git
diff --git a/lib/FreeRTOS-Kernel b/lib/FreeRTOS-Kernel
deleted file mode 160000
index 2a604f4a2..000000000
--- a/lib/FreeRTOS-Kernel
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 2a604f4a2818b8354b5e1a39e388eb5e16cfbc1f
diff --git a/lib/lwip b/lib/lwip
deleted file mode 160000
index 159e31b68..000000000
--- a/lib/lwip
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 159e31b689577dbf69cf0683bbaffbd71fa5ee10
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 2d4fcf5de..358f1cb9d 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -3,8 +3,17 @@ import subprocess
 from pathlib import Path
 from multiprocessing import Pool
 
+# Mandatory Dependencies that is always fetched
 # path, url, commit (Alphabet sorted by path)
-deps_list = {
+deps_mandatory = {
+    'lib/FreeRTOS-Kernel'                      : ['2a604f4a2818b8354b5e1a39e388eb5e16cfbc1f', 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git'               ],
+    'lib/lwip'                                 : ['159e31b689577dbf69cf0683bbaffbd71fa5ee10', 'https://github.com/lwip-tcpip/lwip.git'                        ],
+    'tools/uf2'                                : ['19615407727073e36d81bf239c52108ba92e7660', 'https://github.com/microsoft/uf2.git'                          ],
+}
+
+# Optional Dependencies per MCU
+# path, url, commit (Alphabet sorted by path)
+deps_optional = {
     'hw/mcu/allwinner'                         : ['8e5e89e8e132c0fd90e72d5422e5d3d68232b756', 'https://github.com/hathach/allwinner_driver.git'               ],
     'hw/mcu/bridgetek/ft9xx/ft90x-sdk'         : ['91060164afe239fcb394122e8bf9eb24d3194eb1', 'https://github.com/BRTSG-FOSS/ft90x-sdk.git'                   ],
     'hw/mcu/broadcom'                          : ['08370086080759ed54ac1136d62d2ad24c6fa267', 'https://github.com/adafruit/broadcom-peripherals.git'          ],
@@ -55,22 +64,22 @@ deps_list = {
     'hw/mcu/ti'                                : ['143ed6cc20a7615d042b03b21e070197d473e6e5', 'https://github.com/hathach/ti_driver.git'                      ],
     'hw/mcu/wch/ch32v307'                      : ['17761f5cf9dbbf2dcf665b7c04934188add20082', 'https://github.com/openwch/ch32v307.git'                       ],
     'lib/CMSIS_5'                              : ['20285262657d1b482d132d20d755c8c330d55c1f', 'https://github.com/ARM-software/CMSIS_5.git'                   ],
-    'lib/FreeRTOS-Kernel'                      : ['2a604f4a2818b8354b5e1a39e388eb5e16cfbc1f', 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git'               ],
-    'lib/lwip'                                 : ['159e31b689577dbf69cf0683bbaffbd71fa5ee10', 'https://github.com/lwip-tcpip/lwip.git'                        ],
     'lib/sct_neopixel'                         : ['e73e04ca63495672d955f9268e003cffe168fcd8', 'https://github.com/gsteiert/sct_neopixel.git'                  ],
-    'tools/uf2'                                : ['19615407727073e36d81bf239c52108ba92e7660', 'https://github.com/microsoft/uf2.git'                          ],
 }
 
+# combined 2 deps
+deps_all = {**deps_mandatory, **deps_optional}
+
 # TOP is tinyusb root dir
 TOP = Path(__file__).parent.parent.resolve()
 
 
 def get_a_dep(d):
-    if d not in deps_list.keys():
+    if d not in deps_all.keys():
         print('{} is not found in dependency list')
         return 1
-    commit = deps_list[d][0]
-    url = deps_list[d][1]
+    commit = deps_all[d][0]
+    url = deps_all[d][1]
     print('cloning {} with {}'.format(d, url))
 
     p = Path(TOP / d)
@@ -94,8 +103,11 @@ def get_a_dep(d):
 
 
 if __name__ == "__main__":
+    if len(sys.argv) <= 1:
+        sys.exit(1)
+
     status = 0
-    all_deps = sys.argv[1:]
+    deps = list(deps_mandatory.keys()) + sys.argv[1:]
     with Pool() as pool:
-        status = sum(pool.map(get_a_dep, all_deps))
+        status = sum(pool.map(get_a_dep, deps))
     sys.exit(status)
diff --git a/tools/uf2 b/tools/uf2
deleted file mode 160000
index 196154077..000000000
--- a/tools/uf2
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 19615407727073e36d81bf239c52108ba92e7660

From 323a56e309654601d1eaeaa4114e03f750c58a36 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 15:39:59 +0700
Subject: [PATCH 1556/2085] bump up freeRTOS deps to version 10.5.1

---
 tools/get_deps.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index 358f1cb9d..24e5f383a 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -6,7 +6,7 @@ from multiprocessing import Pool
 # Mandatory Dependencies that is always fetched
 # path, url, commit (Alphabet sorted by path)
 deps_mandatory = {
-    'lib/FreeRTOS-Kernel'                      : ['2a604f4a2818b8354b5e1a39e388eb5e16cfbc1f', 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git'               ],
+    'lib/FreeRTOS-Kernel'                      : ['def7d2df2b0506d3d249334974f51e427c17a41c', 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git'               ],
     'lib/lwip'                                 : ['159e31b689577dbf69cf0683bbaffbd71fa5ee10', 'https://github.com/lwip-tcpip/lwip.git'                        ],
     'tools/uf2'                                : ['19615407727073e36d81bf239c52108ba92e7660', 'https://github.com/microsoft/uf2.git'                          ],
 }
@@ -96,6 +96,7 @@ def get_a_dep(d):
     head = result.stdout.decode("utf-8").splitlines()[0]
 
     if commit != head:
+        subprocess.run("{} reset --hard".format(git_cmd, commit), shell=True)
         subprocess.run("{} fetch --depth 1 origin {}".format(git_cmd, commit), shell=True)
         subprocess.run("{} checkout FETCH_HEAD".format(git_cmd), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
 

From 2faad42cb1d258155f714e5140bb27bc1ed30caf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 15:54:25 +0700
Subject: [PATCH 1557/2085] update ci

- remove submodules init
- pre-commit: forbid new submodule, run in ci
---
 .github/workflows/build_aarch64.yml | 3 ---
 .github/workflows/build_arm.yml     | 8 +-------
 .github/workflows/build_iar.yml     | 8 +++-----
 .github/workflows/build_msp430.yml  | 5 +----
 .github/workflows/build_renesas.yml | 3 ---
 .github/workflows/build_riscv.yml   | 3 ---
 .github/workflows/build_win_mac.yml | 3 ---
 .github/workflows/pre-commit.yml    | 3 +++
 .pre-commit-config.yaml             | 3 ++-
 9 files changed, 10 insertions(+), 29 deletions(-)

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 30df2bdf0..cc8ddb070 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -42,9 +42,6 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
     - name: Checkout hathach/linkermap
       uses: actions/checkout@v3
       with:
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index b5a92d6e3..7aecb8386 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -65,9 +65,6 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
     - name: Checkout hathach/linkermap
       uses: actions/checkout@v3
       with:
@@ -145,9 +142,6 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
     - name: Build
       run: python3 tools/build_board.py ${{ matrix.example }}
 
@@ -275,4 +269,4 @@ jobs:
     - name: Test dfu_runtime
       run: |
         ./flash.sh dfu_runtime.elf
-        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done  
+        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index afb6efb6b..a5d24892f 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -30,7 +30,7 @@ jobs:
         family:
         # Alphabetical order
         # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
-        # run IAR build. Too many matrix can hurt due to setup/teardown overhead. 
+        # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
         - 'stm32f0 stm32f1 stm32f4 stm32f7 stm32g4 stm32h7 stm32l4'
     steps:
     - name: Clean workspace
@@ -42,10 +42,8 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Checkout submodules and dependencies
-      run: |
-        git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-        python3 tools/get_family_deps.py ${{ matrix.family }}
+    - name: Get Dependencies
+      run: python3 tools/get_family_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }} CC=iccarm
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 6832c54b3..7cb60dceb 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -21,7 +21,7 @@ concurrency:
   group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
   cancel-in-progress: true
 
-jobs:  
+jobs:
   build-msp430:
     runs-on: ubuntu-latest
     strategy:
@@ -40,9 +40,6 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
     - name: Checkout hathach/linkermap
       uses: actions/checkout@v3
       with:
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 7ce674485..ffdeedb71 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -39,9 +39,6 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
     - name: Checkout hathach/linkermap
       uses: actions/checkout@v3
       with:
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 876ebbdef..87c7b522e 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -41,9 +41,6 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
     - name: Checkout hathach/linkermap
       uses: actions/checkout@v3
       with:
diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index 7c884abd9..4b743a686 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -46,9 +46,6 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Checkout common submodules in lib
-      run: git submodule update --init lib/FreeRTOS-Kernel lib/lwip
-
     - name: Get Dependencies
       run: python3 tools/get_family_deps.py stm32f4
 
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index d2150d13f..6deee872f 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -26,6 +26,9 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
+    - name: Run pre-commit
+      uses: pre-commit/action@v3.0.0
+
     - name: Run codespell
       uses: codespell-project/actions-codespell@master
 
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index 865307896..ea2372f07 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -4,11 +4,12 @@
 
 repos:
 -   repo: https://github.com/pre-commit/pre-commit-hooks
-    rev: v4.0.1
+    rev: v4.4.0
     hooks:
     - id: check-yaml
     - id: trailing-whitespace
     - id: end-of-file-fixer
+    - id: forbid-submodules
 
 -   repo: local
     hooks:

From 3623ba1884ddff23e9b64766cb6dd032f1425846 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 16:12:49 +0700
Subject: [PATCH 1558/2085] fix trailing space and new line

temporarily disable codespell
---
 .gitattributes                                |   6 +-
 .github/ISSUE_TEMPLATE/bug_report.yml         |   6 +-
 .github/workflows/trigger.yml                 |   4 +-
 .pre-commit-config.yaml                       |  10 +-
 .readthedocs.yaml                             |   1 -
 docs/assets/stack.svg                         |   2 +-
 docs/contributing/code_of_conduct.rst         |   2 +-
 docs/info/changelog.rst                       |  54 +-
 docs/info/contributors.rst                    |   2 +-
 docs/reference/getting_started.rst            |  14 +-
 examples/device/audio_4_channel_mic/skip.txt  |   2 +-
 .../device/audio_4_channel_mic/src/main.c     |   2 +-
 .../src/plot_audio_samples.py                 |   1 -
 .../audio_4_channel_mic/src/usb_descriptors.c |   2 +-
 examples/device/audio_test/CMakeLists.txt     |   2 +-
 examples/device/audio_test/skip.txt           |   2 +-
 examples/device/audio_test/src/main.c         |   2 +-
 .../audio_test/src/plot_audio_samples.py      |   3 +-
 .../device/audio_test/src/usb_descriptors.c   |   2 +-
 .../audio_test_multi_rate/CMakeLists.txt      |   2 +-
 .../device/audio_test_multi_rate/skip.txt     |   2 +-
 .../device/audio_test_multi_rate/src/main.c   |  10 +-
 .../src/plot_audio_samples.py                 |   3 +-
 .../audio_test_multi_rate/src/tusb_config.h   |   2 +-
 .../src/usb_descriptors.c                     |   2 +-
 .../src/usb_descriptors.h                     |   4 +-
 examples/device/board_test/src/CMakeLists.txt |   2 +-
 examples/device/board_test/src/main.c         |   2 +-
 examples/device/cdc_dual_ports/CMakeLists.txt |   2 +-
 examples/device/cdc_dual_ports/src/main.c     |   2 +-
 .../cdc_dual_ports/src/usb_descriptors.c      |   2 +-
 examples/device/cdc_msc/CMakeLists.txt        |   2 +-
 examples/device/cdc_msc/skip.txt              |   2 +-
 examples/device/cdc_msc/src/main.c            |   2 +-
 examples/device/cdc_msc/src/msc_disk.c        |   2 +-
 examples/device/cdc_msc/src/usb_descriptors.c |   2 +-
 examples/device/cdc_msc_freertos/src/main.c   |   2 +-
 .../device/cdc_msc_freertos/src/msc_disk.c    |   2 +-
 .../cdc_msc_freertos/src/usb_descriptors.c    |   2 +-
 examples/device/dfu_runtime/CMakeLists.txt    |   2 +-
 examples/device/dfu_runtime/src/main.c        |   2 +-
 .../dynamic_configuration/CMakeLists.txt      |   2 +-
 .../device/dynamic_configuration/skip.txt     |   2 +-
 .../device/dynamic_configuration/src/main.c   |   2 +-
 .../dynamic_configuration/src/msc_disk.c      |   2 +-
 .../src/usb_descriptors.c                     |   2 +-
 .../device/hid_boot_interface/CMakeLists.txt  |   2 +-
 examples/device/hid_boot_interface/Makefile   |   2 +-
 examples/device/hid_boot_interface/src/main.c |   2 +-
 .../hid_boot_interface/src/usb_descriptors.c  |   2 +-
 .../hid_boot_interface/src/usb_descriptors.h  |   2 +-
 examples/device/hid_composite/CMakeLists.txt  |   2 +-
 examples/device/hid_composite/src/main.c      |   2 +-
 .../hid_composite/src/usb_descriptors.c       |   2 +-
 .../hid_composite/src/usb_descriptors.h       |   2 +-
 .../device/hid_composite_freertos/src/main.c  |   2 +-
 .../src/usb_descriptors.c                     |   2 +-
 .../src/usb_descriptors.h                     |   2 +-
 .../device/hid_generic_inout/CMakeLists.txt   |   2 +-
 examples/device/hid_generic_inout/hid_test.js |   3 +-
 examples/device/hid_generic_inout/src/main.c  |   2 +-
 .../hid_generic_inout/src/usb_descriptors.c   |   2 +-
 .../hid_multiple_interface/CMakeLists.txt     |   2 +-
 examples/device/midi_test/CMakeLists.txt      |   2 +-
 examples/device/midi_test/src/main.c          |   2 +-
 .../device/midi_test/src/usb_descriptors.c    |   2 +-
 examples/device/msc_dual_lun/CMakeLists.txt   |   2 +-
 examples/device/msc_dual_lun/skip.txt         |   2 +-
 examples/device/msc_dual_lun/src/main.c       |   2 +-
 .../device/msc_dual_lun/src/msc_disk_dual.c   |   2 +-
 .../device/msc_dual_lun/src/usb_descriptors.c |   2 +-
 .../device/net_lwip_webserver/CMakeLists.txt  |   2 +-
 examples/device/net_lwip_webserver/skip.txt   |   2 +-
 .../device/net_lwip_webserver/src/arch/cc.h   |  32 +-
 .../device/net_lwip_webserver/src/lwipopts.h  |  28 +-
 examples/device/net_lwip_webserver/src/main.c |   6 +-
 .../net_lwip_webserver/src/usb_descriptors.c  |   4 +-
 examples/device/uac2_headset/CMakeLists.txt   |   2 +-
 examples/device/uac2_headset/src/main.c       |   4 +-
 .../device/uac2_headset/src/usb_descriptors.c |   2 +-
 .../device/uac2_headset/src/usb_descriptors.h |   2 +-
 examples/device/usbtmc/CMakeLists.txt         |   2 +-
 examples/device/usbtmc/src/main.c             |   2 +-
 examples/device/usbtmc/visaQuery.py           |  26 +-
 examples/device/video_capture/CMakeLists.txt  |   2 +-
 examples/device/video_capture/src/main.c      |   2 +-
 .../video_capture/src/usb_descriptors.c       |   2 +-
 .../video_capture/src/usb_descriptors.h       |   2 +-
 examples/device/webusb_serial/CMakeLists.txt  |   2 +-
 examples/device/webusb_serial/src/main.c      |   2 +-
 .../webusb_serial/src/usb_descriptors.c       |   2 +-
 .../webusb_serial/src/usb_descriptors.h       |   2 +-
 .../dual/host_hid_to_device_cdc/src/main.c    |   2 +-
 .../src/usb_descriptors.c                     |   2 +-
 examples/host/bare_api/src/main.c             |   2 +-
 examples/host/cdc_msc_hid/src/main.c          |   2 +-
 examples/host/cdc_msc_hid/src/msc_app.c       |   3 +-
 examples/host/hid_controller/src/main.c       |   2 +-
 examples/host/msc_file_explorer/src/main.c    |   2 +-
 examples/host/msc_file_explorer/src/msc_app.c |   2 +-
 examples/rules.mk                             |   2 +-
 hw/bsp/ansi_escape.h                          |   2 +-
 hw/bsp/board.c                                |   2 +-
 hw/bsp/board.h                                |   2 +-
 .../boards/raspberrypi_zero_w/board.h         |   2 +-
 .../boards/raspberrypi_zero_w/board.mk        |   2 +-
 hw/bsp/broadcom_32bit/family.c                |   2 +-
 .../boards/raspberrypi_cm4/board.h            |   2 +-
 .../boards/raspberrypi_zero2w/board.h         |   2 +-
 hw/bsp/broadcom_64bit/family.c                |   2 +-
 hw/bsp/brtmm90x/family.c                      |   7 +-
 hw/bsp/brtmm90x/family.mk                     |   8 +-
 .../ch32v307/boards/ch32v307v-r1-1v0/board.h  |   2 +-
 .../boards/ch32v307v-r1-1v0/debug_uart.c      |   4 +-
 hw/bsp/ch32v307/ch32v307.ld                   |  35 +-
 hw/bsp/ch32v307/ch32v30x_conf.h               |   7 +-
 hw/bsp/ch32v307/ch32v30x_it.c                 |   2 -
 hw/bsp/ch32v307/ch32v30x_it.h                 |   2 -
 hw/bsp/ch32v307/core_riscv.h                  |   7 +-
 hw/bsp/ch32v307/system_ch32v30x.c             | 140 ++--
 hw/bsp/ch32v307/system_ch32v30x.h             |   9 +-
 hw/bsp/da14695_dk_usb/da14695_dk_usb.c        |   2 +-
 hw/bsp/da14695_dk_usb/da1469x.ld              |   1 -
 hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c        |   2 +-
 hw/bsp/da1469x_dk_pro/da1469x.ld              |   1 -
 hw/bsp/ea4088qs/ea4088qs.c                    |   2 +-
 hw/bsp/ea4088qs/lpc4088.ld                    |  54 +-
 hw/bsp/ea4357/ea4357.c                        |   2 +-
 hw/bsp/ea4357/lpc4357.ld                      | 106 +--
 hw/bsp/ea4357/pca9532.c                       |   6 +-
 hw/bsp/ea4357/pca9532.h                       |   2 +-
 hw/bsp/esp32s2/boards/CMakeLists.txt          |   2 +-
 .../adafruit_feather_esp32s2/board.cmake      |   2 +-
 .../boards/adafruit_feather_esp32s2/board.h   |   2 +-
 .../boards/adafruit_magtag_29gray/board.cmake |   2 +-
 .../boards/adafruit_magtag_29gray/board.h     |   2 +-
 .../boards/adafruit_metro_esp32s2/board.cmake |   2 +-
 .../boards/adafruit_metro_esp32s2/board.h     |   2 +-
 hw/bsp/esp32s2/boards/esp32s2.c               |   3 +-
 .../boards/espressif_kaluga_1/board.cmake     |   2 +-
 .../esp32s2/boards/espressif_kaluga_1/board.h |   2 +-
 .../boards/espressif_saola_1/board.cmake      |   2 +-
 .../esp32s2/boards/espressif_saola_1/board.h  |   2 +-
 .../components/led_strip/CMakeLists.txt       |   1 -
 hw/bsp/esp32s2/family.cmake                   |   2 +-
 hw/bsp/esp32s2/family.mk                      |   1 -
 hw/bsp/esp32s3/boards/CMakeLists.txt          |   2 +-
 hw/bsp/esp32s3/boards/esp32s3.c               |   3 +-
 .../boards/espressif_addax_1/board.cmake      |   2 +-
 .../esp32s3/boards/espressif_addax_1/board.h  |   2 +-
 .../boards/espressif_s3_devkitc/board.cmake   |   2 +-
 .../boards/espressif_s3_devkitc/board.h       |   2 +-
 .../boards/espressif_s3_devkitm/board.cmake   |   2 +-
 .../boards/espressif_s3_devkitm/board.h       |   2 +-
 .../components/led_strip/CMakeLists.txt       |   1 -
 hw/bsp/esp32s3/family.cmake                   |   2 +-
 hw/bsp/esp32s3/family.mk                      |   1 -
 hw/bsp/f1c100s/README.md                      |   2 +-
 hw/bsp/f1c100s/board.h                        |   2 +-
 hw/bsp/f1c100s/board.mk                       |   6 +-
 hw/bsp/f1c100s/f1c100s.c                      |   4 +-
 hw/bsp/family_support.cmake                   |   2 +-
 hw/bsp/fomu/boards/fomu/board.mk              |   2 +-
 hw/bsp/fomu/fomu.c                            |   2 +-
 hw/bsp/fomu/include/hw/common.h               |   2 +-
 hw/bsp/fomu/include/irq.h                     |   2 +-
 hw/bsp/frdm_k32l2b/board.h                    |   2 +-
 hw/bsp/frdm_k32l2b/frdm_k32l2b.c              |  12 +-
 hw/bsp/frdm_kl25z/frdm_kl25z.c                |   4 +-
 hw/bsp/gd32vf103/family.c                     |   2 +-
 hw/bsp/gd32vf103/system_gd32vf103.c           |  10 +-
 hw/bsp/imxrt/boards/metro_m7_1011/board.h     |   2 +-
 .../boards/metro_m7_1011/metro_m7_1011.ld     |   2 +-
 hw/bsp/imxrt/boards/mimxrt1010_evk/board.h    |   2 +-
 hw/bsp/imxrt/boards/mimxrt1015_evk/board.h    |   2 +-
 hw/bsp/imxrt/boards/mimxrt1020_evk/board.h    |   2 +-
 hw/bsp/imxrt/boards/mimxrt1024_evk/board.h    |   2 +-
 hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h   |   2 +-
 hw/bsp/imxrt/boards/mimxrt1060_evk/board.h    |   2 +-
 hw/bsp/imxrt/boards/mimxrt1064_evk/board.h    |   2 +-
 hw/bsp/imxrt/boards/teensy_40/board.h         |   2 +-
 hw/bsp/imxrt/boards/teensy_40/board.mk        |   2 +-
 hw/bsp/imxrt/boards/teensy_41/board.h         |   2 +-
 hw/bsp/imxrt/boards/teensy_41/board.mk        |   2 +-
 hw/bsp/imxrt/family.c                         |   2 +-
 hw/bsp/kuiic/K32L2B31xxxxA_flash.ld           |   1 -
 hw/bsp/kuiic/board.h                          |   2 +-
 hw/bsp/kuiic/kuiic.c                          |  16 +-
 hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld |  60 +-
 hw/bsp/lpc15/family.c                         |   2 +-
 .../lpc18/boards/lpcxpresso18s37/lpc1837.ld   |  86 +--
 hw/bsp/lpc18/boards/mcb1800/lpc1857.ld        | 106 +--
 hw/bsp/lpc18/family.c                         |   2 +-
 hw/bsp/lpc54/boards/lpcxpresso54628/board.mk  |   2 +-
 hw/bsp/lpc54/family.c                         |   2 +-
 .../LPC55S69_cm33_core0_uf2.ld                |   1 -
 hw/bsp/lpc55/family.c                         |   2 +-
 hw/bsp/lpcxpresso11u37/lpc11u37.ld            |  50 +-
 hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c      |   2 +-
 hw/bsp/lpcxpresso11u68/lpc11u68.ld            |  68 +-
 hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c      |   2 +-
 hw/bsp/lpcxpresso1347/lpc1347.ld              |  68 +-
 hw/bsp/lpcxpresso1347/lpcxpresso1347.c        |   4 +-
 hw/bsp/lpcxpresso1769/lpc1769.ld              |  54 +-
 hw/bsp/lpcxpresso1769/lpcxpresso1769.c        |   2 +-
 hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c      |   2 +-
 hw/bsp/mbed1768/lpc1768.ld                    |  54 +-
 hw/bsp/mbed1768/mbed1768.c                    |   2 +-
 hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld    |   8 +-
 .../boards/mm32f327x_mb39/mm32f327x_mb39.c    |   4 +-
 hw/bsp/ngx4330/ngx4330.c                      |   2 +-
 hw/bsp/ngx4330/ngx4330.ld                     |  80 +--
 hw/bsp/nrf/boards/adafruit_clue/board.h       |   2 +-
 .../boards/adafruit_clue/nrf52840_s140_v6.ld  |   4 +-
 .../arduino_nano33_ble/arduino_nano33_ble.ld  |   2 +-
 hw/bsp/nrf/boards/arduino_nano33_ble/board.h  |   2 +-
 .../circuitplayground_bluefruit/board.h       |   2 +-
 .../nrf52840_s140_v6.ld                       |   4 +-
 .../boards/feather_nrf52840_express/board.h   |   2 +-
 .../nrf52840_s140_v6.ld                       |   4 +-
 .../nrf/boards/feather_nrf52840_sense/board.h |   2 +-
 .../nrf52840_s140_v6.ld                       |   4 +-
 hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h  |   2 +-
 .../itsybitsy_nrf52840/nrf52840_s140_v6.ld    |   4 +-
 hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h |   2 +-
 .../nrf/boards/nrf52840_mdk_dongle/board.mk   |   2 +-
 hw/bsp/nrf/boards/pca10056/board.h            |   2 +-
 hw/bsp/nrf/boards/pca10059/board.h            |   2 +-
 hw/bsp/nrf/boards/pca10100/board.h            |   2 +-
 hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h   |   2 +-
 hw/bsp/nrf/family.c                           |   2 +-
 hw/bsp/nutiny_nuc121s/nuc121_flash.ld         |   2 +-
 hw/bsp/nutiny_nuc121s/nutiny_nuc121.c         |   2 +-
 hw/bsp/nutiny_nuc125s/nuc125_flash.ld         |   2 +-
 hw/bsp/nutiny_nuc125s/nutiny_nuc125.c         |   2 +-
 hw/bsp/nutiny_nuc126v/nutiny_nuc126.c         |   2 +-
 hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c  |   2 +-
 hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c  |   2 +-
 .../boards/olimex_emz64/olimex_emz64.c        |   2 +-
 hw/bsp/pic32mz/family.c                       |   2 +-
 hw/bsp/rp2040/board.h                         |   2 +-
 .../boards/raspberry_pi_pico/board.cmake      |   2 +-
 hw/bsp/rp2040/family.cmake                    |   2 +-
 hw/bsp/rx/boards/gr_citrus/gr_citrus.c        |   6 +-
 hw/bsp/rx/boards/rx65n_target/rx65n_target.c  |   2 +-
 .../samd11_xplained/samd11d14am_flash.ld      |   4 +-
 hw/bsp/samd21/boards/atsamd21_xpro/board.h    |   2 +-
 .../boards/circuitplayground_express/board.h  |   2 +-
 hw/bsp/samd21/boards/curiosity_nano/board.h   |   2 +-
 .../samd21/boards/feather_m0_express/board.h  |   2 +-
 hw/bsp/samd21/boards/itsybitsy_m0/board.h     |   2 +-
 hw/bsp/samd21/boards/luna_d21/board.h         |   2 +-
 hw/bsp/samd21/boards/luna_d21/board.mk        |   1 -
 hw/bsp/samd21/boards/metro_m0_express/board.h |   2 +-
 hw/bsp/samd21/boards/qtpy/board.h             |   2 +-
 hw/bsp/samd21/boards/seeeduino_xiao/board.h   |   2 +-
 hw/bsp/samd21/boards/trinket_m0/board.h       |   1 -
 hw/bsp/samd21/boards/trinket_m0/board.mk      |   1 -
 hw/bsp/samd21/family.c                        |   2 +-
 .../samd51/boards/feather_m4_express/board.h  |   2 +-
 hw/bsp/samd51/boards/itsybitsy_m4/board.h     |   2 +-
 hw/bsp/samd51/boards/metro_m4_express/board.h |   2 +-
 .../samd51/boards/metro_m4_express/board.mk   |   1 -
 hw/bsp/samd51/boards/pybadge/board.h          |   2 +-
 hw/bsp/samd51/boards/pyportal/board.h         |   2 +-
 hw/bsp/samd51/family.c                        |   2 +-
 hw/bsp/same54xplainedpro/same54p20a_flash.ld  |   4 +-
 hw/bsp/same54xplainedpro/same54p20a_sram.ld   |   4 +-
 hw/bsp/samg55xplained/samg55xplained.c        |   2 +-
 hw/bsp/saml2x/boards/atsaml21_xpro/board.h    |   2 +-
 hw/bsp/saml2x/boards/saml22_feather/board.h   |   2 +-
 .../boards/saml22_feather/saml22_feather.ld   |   4 +-
 hw/bsp/saml2x/boards/sensorwatch_m0/board.h   |   2 +-
 .../boards/sensorwatch_m0/sensorwatch_m0.ld   |   4 +-
 hw/bsp/saml2x/family.c                        |   2 +-
 hw/bsp/sltb009a/sltb009a.c                    |   4 +-
 hw/bsp/spresense/board_spresense.c            |   6 +-
 .../stm32f0/boards/stm32f070rbnucleo/board.h  |   2 +-
 .../stm32f0/boards/stm32f070rbnucleo/board.mk |   2 +-
 .../stm32f070rbnucleo/stm32F070rbtx_flash.ld  |  14 +-
 .../stm32f072disco/STM32F072RBTx_FLASH.ld     |   8 +-
 hw/bsp/stm32f0/boards/stm32f072disco/board.h  |   2 +-
 hw/bsp/stm32f0/boards/stm32f072eval/board.h   |   2 +-
 hw/bsp/stm32f0/family.c                       |   2 +-
 hw/bsp/stm32f0/stm32f0xx_hal_conf.h           |  51 +-
 .../stm32f103_bluepill/STM32F103X8_FLASH.ld   |   6 +-
 .../stm32f1/boards/stm32f103_bluepill/board.h |   2 +-
 .../stm32f103_mini_2/STM32F103XC_FLASH.ld     |   6 +-
 .../stm32f1/boards/stm32f103_mini_2/board.h   |   2 +-
 hw/bsp/stm32f1/family.c                       |   8 +-
 hw/bsp/stm32f1/stm32f1xx_hal_conf.h           |  44 +-
 hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld |   8 +-
 hw/bsp/stm32f207nucleo/stm32f207nucleo.c      |   4 +-
 hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h   |  56 +-
 hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld  |  18 +-
 hw/bsp/stm32f303disco/stm32f303disco.c        |   2 +-
 hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h    |  38 +-
 .../feather_stm32f405/STM32F405RGTx_FLASH.ld  |  18 +-
 .../stm32f4/boards/feather_stm32f405/board.h  |   2 +-
 .../boards/pyboardv11/STM32F405RGTx_FLASH.ld  |  18 +-
 hw/bsp/stm32f4/boards/pyboardv11/board.h      |   2 +-
 .../stm32f401blackpill/STM32F401VCTx_FLASH.ld |   8 +-
 .../stm32f4/boards/stm32f401blackpill/board.h |   2 +-
 .../stm32f401blackpill/stm32f4xx_hal_conf.h   |  82 +--
 .../stm32f407disco/STM32F407VGTx_FLASH.ld     |  18 +-
 hw/bsp/stm32f4/boards/stm32f407disco/board.h  |   2 +-
 .../stm32f407disco/stm32f4xx_hal_conf.h       |  82 +--
 .../stm32f411blackpill/STM32F411CEUx_FLASH.ld |   8 +-
 .../stm32f4/boards/stm32f411blackpill/board.h |   2 +-
 .../stm32f411blackpill/stm32f4xx_hal_conf.h   |  82 +--
 .../stm32f411disco/STM32F411VETx_FLASH.ld     |   8 +-
 hw/bsp/stm32f4/boards/stm32f411disco/board.h  |   2 +-
 .../stm32f411disco/stm32f4xx_hal_conf.h       |  82 +--
 .../stm32f412disco/STM32F412ZGTx_FLASH.ld     |   8 +-
 hw/bsp/stm32f4/boards/stm32f412disco/board.h  |   2 +-
 .../stm32f412disco/stm32f4xx_hal_conf.h       |  82 +--
 .../stm32f412nucleo/STM32F412ZGTx_FLASH.ld    |   8 +-
 .../stm32f412nucleo/stm32f4xx_hal_conf.h      |  82 +--
 .../stm32f439nucleo/stm32f4xx_hal_conf.h      |  70 +-
 hw/bsp/stm32f4/family.c                       |   2 +-
 hw/bsp/stm32f7/boards/stlinkv3mini/board.h    |   2 +-
 hw/bsp/stm32f7/boards/stm32f723disco/board.h  |   2 +-
 hw/bsp/stm32f7/boards/stm32f746disco/board.h  |   2 +-
 .../stm32f746nucleo/STM32F746ZGTx_FLASH.ld    |   6 +-
 hw/bsp/stm32f7/boards/stm32f746nucleo/board.h |   2 +-
 .../stm32f746nucleo/stm32f7xx_hal_conf.h      |  52 +-
 .../stm32f767nucleo/STM32F767ZITx_FLASH.ld    |   8 +-
 hw/bsp/stm32f7/boards/stm32f767nucleo/board.h |   2 +-
 .../stm32f7/boards/stm32f767nucleo/board.mk   |   2 +-
 .../stm32f767nucleo/stm32f7xx_hal_conf.h      |  52 +-
 hw/bsp/stm32f7/boards/stm32f769disco/board.h  |   2 +-
 .../stm32g474nucleo/STM32G474RETx_FLASH.ld    |   8 +-
 hw/bsp/stm32g4/family.c                       |   2 +-
 hw/bsp/stm32g4/stm32g4xx_hal_conf.h           |  26 +-
 hw/bsp/stm32h7/boards/daisyseed/board.mk      |   1 -
 .../boards/daisyseed/stm32h750ibkx_flash.ld   |   2 -
 .../boards/stm32h743eval/stm32h743xx_flash.ld |   8 +-
 .../stm32h743nucleo/stm32h743xx_flash.ld      |   8 +-
 hw/bsp/stm32h7/boards/stm32h745disco/board.mk |   1 -
 .../STM32H743IITX_FLASH.ld                    |   2 -
 .../boards/waveshare_openh743i/board.mk       |   2 +-
 hw/bsp/stm32h7/family.c                       |   2 +-
 hw/bsp/stm32h7/stm32h7xx_hal_conf.h           |   6 +-
 .../stm32l052dap52/STM32L052K8Ux_FLASH.ld     |   8 +-
 hw/bsp/stm32l0/boards/stm32l052dap52/board.h  |  34 +-
 hw/bsp/stm32l0/family.c                       |   2 +-
 hw/bsp/stm32l0/stm32l0xx_hal_conf.h           |  49 +-
 hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld |   8 +-
 hw/bsp/stm32l0538disco/stm32l0538disco.c      |   2 +-
 hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h   | 102 +--
 .../stm32l412nucleo/STM32L412KBUx_FLASH.ld    |  14 +-
 hw/bsp/stm32l4/boards/stm32l412nucleo/board.h |   6 +-
 .../stm32l476disco/STM32L476VGTx_FLASH.ld     |  14 +-
 hw/bsp/stm32l4/boards/stm32l476disco/board.h  |   2 +-
 .../stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld    |  12 +-
 hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h |   2 +-
 .../stm32l4r5nucleo/STM32L4RXxI_FLASH.ld      |   6 +-
 hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h |   2 +-
 hw/bsp/stm32l4/stm32l4xx_hal_conf.h           |  10 +-
 hw/bsp/stm32u5/stm32u5xx_hal_conf.h           |   1 -
 .../stm32wb55nucleo/stm32wb55xx_flash_cm4.ld  |   8 +-
 hw/bsp/stm32wb/family.c                       |   2 +-
 hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk  |   2 +-
 .../tm4c123/boards/ek-tm4c123gxl/tm4c123.ld   |  24 +-
 hw/bsp/tm4c123/family.c                       |   1 -
 hw/bsp/xmc4000/boards/xmc4500_relax/board.h   |   2 +-
 hw/mcu/bridgetek/ft9xx/Readme.md              |   4 +-
 hw/mcu/bridgetek/ft9xx/scripts/crt0.S         |   8 +-
 hw/mcu/dialog/README.md                       |   4 +-
 .../SDK_10.0.8.105/sdk/bsp/arm_license.txt    |   1 -
 .../sdk/bsp/include/cmsis_compiler.h          |   1 -
 .../sdk/bsp/include/cmsis_gcc.h               |  10 +-
 .../SDK_10.0.8.105/sdk/bsp/include/core_cm0.h |   2 +-
 .../sdk/bsp/include/core_cm33.h               |   4 +-
 .../sdk/bsp/include/mpu_armv8.h               |  33 +-
 hw/mcu/dialog/da1469x/da1469x.ld              |   1 -
 hw/mcu/dialog/da1469x/include/mcu/mcu.h       |   1 -
 .../nrf5x/s140_nrf52_6.1.1_API/include/ble.h  |   2 +-
 .../s140_nrf52_6.1.1_API/include/ble_gap.h    |   2 +-
 lib/SEGGER_RTT/RTT/SEGGER_RTT.c               |  16 +-
 lib/SEGGER_RTT/RTT/SEGGER_RTT.h               |   2 +-
 lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S    |   6 +-
 lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h          |  12 +-
 .../Syscalls/SEGGER_RTT_Syscalls_GCC.c        |   4 +-
 .../Syscalls/SEGGER_RTT_Syscalls_KEIL.c       |  42 +-
 lib/fatfs/source/00history.txt                |   1 -
 lib/fatfs/source/00readme.txt                 |   1 -
 lib/fatfs/source/diskio.c                     |   1 -
 lib/fatfs/source/ff.c                         |   1 -
 lib/fatfs/source/ffsystem.c                   |   1 -
 lib/networking/dhserver.c                     |  10 +-
 lib/networking/dhserver.h                     |   6 +-
 lib/networking/dnserver.c                     |   8 +-
 lib/networking/dnserver.h                     |   6 +-
 lib/networking/ndis.h                         |  10 +-
 lib/networking/rndis_protocol.h               |  28 +-
 lib/networking/rndis_reports.c                |  14 +-
 src/class/audio/audio.h                       |   6 +-
 src/class/audio/audio_device.c                |   6 +-
 src/class/audio/audio_device.h                |   4 +-
 src/class/bth/bth_device.h                    |   2 +-
 src/class/cdc/cdc_device.c                    |  12 +-
 src/class/cdc/cdc_device.h                    |   2 +-
 src/class/cdc/cdc_host.h                      |   2 +-
 src/class/cdc/cdc_rndis.h                     |   2 +-
 src/class/cdc/cdc_rndis_host.c                |   2 +-
 src/class/cdc/cdc_rndis_host.h                |   2 +-
 src/class/hid/hid.h                           |   2 +-
 src/class/midi/midi.h                         |   2 +-
 src/class/midi/midi_device.c                  |   2 +-
 src/class/midi/midi_device.h                  |   2 +-
 src/class/msc/msc.h                           |   2 +-
 src/class/msc/msc_device.h                    |   2 +-
 src/class/msc/msc_host.c                      |  12 +-
 src/class/msc/msc_host.h                      |   2 +-
 src/class/net/ecm_rndis_device.c              |   2 +-
 src/class/net/ncm_device.c                    |   2 +-
 src/class/net/net_device.h                    |   2 +-
 src/class/usbtmc/usbtmc.h                     |   1 -
 src/class/usbtmc/usbtmc_device.c              |   4 +-
 src/class/vendor/vendor_device.h              |   2 +-
 src/class/vendor/vendor_host.c                |   2 +-
 src/class/vendor/vendor_host.h                |   2 +-
 src/class/video/video_device.c                |   2 +-
 src/common/tusb_compiler.h                    |   4 +-
 src/common/tusb_timeout.h                     |   2 +-
 src/common/tusb_verify.h                      |   2 +-
 src/device/dcd.h                              |   2 +-
 src/device/usbd.c                             |   4 +-
 src/device/usbd_pvt.h                         |   2 +-
 src/host/hcd.h                                |   2 +-
 src/host/hub.c                                |   4 +-
 src/host/usbh.h                               |   2 +-
 src/osal/osal.h                               |   2 +-
 src/osal/osal_freertos.h                      |   2 +-
 src/osal/osal_none.h                          |   2 +-
 src/osal/osal_pico.h                          |   2 +-
 src/osal/osal_rtx4.h                          |   4 +-
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c      |  78 +-
 src/portable/chipidea/ci_hs/ci_hs_type.h      |   2 +-
 src/portable/chipidea/ci_hs/dcd_ci_hs.c       |   2 +-
 src/portable/chipidea/ci_hs/hcd_ci_hs.c       |   2 +-
 src/portable/ehci/ehci.c                      |   6 +-
 src/portable/espressif/esp32sx/dcd_esp32sx.c  |   1 -
 src/portable/mentor/musb/dcd_musb.c           |   8 +-
 src/portable/mentor/musb/hcd_musb.c           |   4 +-
 src/portable/microchip/pic/dcd_pic.c          |   4 +-
 .../microchip/pic32mz/usbhs_registers.h       |  40 +-
 src/portable/microchip/samg/dcd_samg.c        |   2 +-
 .../microchip/samx7x/common_usb_regs.h        |   6 +-
 src/portable/microchip/samx7x/dcd_samx7x.c    |  36 +-
 src/portable/nordic/nrf5x/dcd_nrf5x.c         |   2 +-
 src/portable/nuvoton/nuc120/dcd_nuc120.c      |   6 +-
 src/portable/nuvoton/nuc121/dcd_nuc121.c      |   6 +-
 src/portable/nuvoton/nuc505/dcd_nuc505.c      |   6 +-
 src/portable/nxp/khci/dcd_khci.c              |   6 +-
 src/portable/nxp/khci/hcd_khci.c              |   4 +-
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c      |   2 +-
 src/portable/nxp/lpc17_40/dcd_lpc17_40.h      |   2 +-
 src/portable/nxp/lpc17_40/hcd_lpc17_40.c      |   3 +-
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c  |   7 +-
 .../transdimension/common_transdimension.h    |   2 +-
 .../nxp/transdimension/dcd_transdimension.c   |   2 +-
 .../nxp/transdimension/hcd_transdimension.c   |   2 +-
 src/portable/ohci/ohci.c                      |   3 +-
 .../raspberrypi/pio_usb/dcd_pio_usb.c         |   2 +-
 src/portable/raspberrypi/rp2040/rp2040_usb.h  |   2 +-
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |  45 +-
 src/portable/st/synopsys/synopsys_common.h    | 672 +++++++++---------
 src/portable/sunxi/dcd_sunxi_musb.c           |   6 +-
 src/portable/template/dcd_template.c          |   2 +-
 src/portable/valentyusb/eptri/dcd_eptri.c     |   2 +-
 src/portable/valentyusb/eptri/dcd_eptri.h     |   2 +-
 src/portable/wch/ch32v307/dcd_usbhs.c         |   8 +-
 test/fuzz/dcd_fuzz.cc                         |   4 +-
 test/fuzz/device/cdc/CMakeLists.txt           |   2 +-
 test/fuzz/device/cdc/src/fuzz.cc              |   4 +-
 test/fuzz/device/msc/CMakeLists.txt           |   2 +-
 test/fuzz/device/msc/src/fuzz.cc              |   1 -
 test/fuzz/device/net/CMakeLists.txt           |   2 +-
 test/fuzz/device/net/src/arch/cc.h            |  32 +-
 test/fuzz/device/net/src/fuzz.cc              |   2 +-
 test/fuzz/device/net/src/lwipopts.h           |  28 +-
 test/fuzz/dicts/cdc.dict                      |   1 -
 test/fuzz/make.mk                             |   3 +-
 test/fuzz/msc_fuzz.cc                         |   2 +-
 test/fuzz/net_fuzz.cc                         |   2 +-
 test/fuzz/rules.mk                            |   6 +-
 .../test/device/msc/test_msc_device.c         |   2 +-
 test/unit-test/test/device/usbd/test_usbd.c   |   2 +-
 test/unit-test/test/test_fifo.c               |   2 +-
 .../unit-test/vendor/ceedling/lib/ceedling.rb |   1 -
 .../lib/ceedling/build_invoker_utils.rb       |  14 +-
 .../ceedling/lib/ceedling/cacheinator.rb      |  10 +-
 .../lib/ceedling/cacheinator_helper.rb        |   2 +-
 .../ceedling/lib/ceedling/cmock_builder.rb    |   8 +-
 .../ceedling/lib/ceedling/configurator.rb     |   1 -
 .../lib/ceedling/configurator_plugins.rb      |   2 +-
 .../lib/ceedling/configurator_setup.rb        |   2 +-
 .../lib/ceedling/configurator_validator.rb    |  78 +-
 .../ceedling/lib/ceedling/erb_wrapper.rb      |   2 +-
 .../ceedling/lib/ceedling/file_finder.rb      |   1 -
 .../lib/ceedling/file_finder_helper.rb        |  22 +-
 .../lib/ceedling/file_system_utils.rb         |  14 +-
 .../lib/ceedling/file_system_wrapper.rb       |   2 +-
 .../ceedling/lib/ceedling/flaginator.rb       |  14 +-
 .../ceedling/lib/ceedling/generator_helper.rb |   8 +-
 .../lib/ceedling/generator_test_results.rb    |   2 +-
 .../generator_test_results_sanity_checker.rb  |  22 +-
 .../vendor/ceedling/lib/ceedling/loginator.rb |   6 +-
 .../vendor/ceedling/lib/ceedling/makefile.rb  |   4 +-
 .../vendor/ceedling/lib/ceedling/objects.yml  |   2 +-
 .../vendor/ceedling/lib/ceedling/par_map.rb   |   1 -
 .../vendor/ceedling/lib/ceedling/plugin.rb    |   8 +-
 .../ceedling/lib/ceedling/plugin_builder.rb   |   4 +-
 .../lib/ceedling/plugin_reportinator.rb       |  40 +-
 .../ceedling/plugin_reportinator_helper.rb    |  10 +-
 .../preprocessinator_includes_handler.rb      |   2 +-
 .../lib/ceedling/project_config_manager.rb    |   2 +-
 .../ceedling/lib/ceedling/rake_utils.rb       |   2 +-
 .../ceedling/lib/ceedling/reportinator.rb     |   4 +-
 .../ceedling/lib/ceedling/rules_cmock.rake    |   2 +-
 .../lib/ceedling/rules_preprocess.rake        |   5 +-
 .../ceedling/lib/ceedling/rules_release.rake  |   1 -
 .../rules_release_deep_dependencies.rake      |   3 +-
 .../ceedling/lib/ceedling/rules_tests.rake    |   1 -
 .../rules_tests_deep_dependencies.rake        |   1 -
 .../ceedling/lib/ceedling/setupinator.rb      |   8 +-
 .../ceedling/lib/ceedling/stream_wrapper.rb   |   2 +-
 .../ceedling/lib/ceedling/streaminator.rb     |   2 +-
 .../lib/ceedling/streaminator_helper.rb       |   2 +-
 .../ceedling/lib/ceedling/system_utils.rb     |   6 +-
 .../ceedling/lib/ceedling/task_invoker.rb     |  20 +-
 .../ceedling/lib/ceedling/tasks_base.rake     |   1 -
 .../lib/ceedling/tasks_filesystem.rake        |   2 -
 .../ceedling/lib/ceedling/tasks_release.rake  |  11 +-
 .../ceedling/lib/ceedling/tasks_tests.rake    |   1 -
 .../lib/ceedling/test_invoker_helper.rb       |   8 +-
 .../vendor/ceedling/plugins/beep/lib/beep.rb  |   1 -
 .../ceedling/plugins/bullseye/README.md       |   2 +-
 .../plugins/bullseye/assets/template.erb      |   1 -
 .../ceedling/plugins/bullseye/lib/bullseye.rb |  26 +-
 .../ceedling/plugins/colour_report/README.md  |   2 +-
 .../command_hooks/lib/command_hooks.rb        |   1 -
 .../plugins/compile_commands_json/README.md   |   2 +-
 .../plugins/fake_function_framework/Rakefile  |   2 +-
 .../examples/fff_example/project.yml          |   2 +-
 .../examples/fff_example/src/display.c        |   2 +-
 .../lib/fff_mock_generator.rb                 |   2 +-
 .../spec/fff_mock_header_generator_spec.rb    |   2 +-
 .../spec/fff_mock_source_generator_spec.rb    |   2 +-
 .../spec/header_generator.rb                  |   2 +-
 .../src/fff_unity_helper.h                    |   2 +-
 .../ceedling/plugins/gcov/assets/template.erb |   1 -
 .../plugins/gcov/lib/reportinator_helper.rb   |   2 +-
 .../plugins/json_tests_report/README.md       |   4 +-
 .../lib/json_tests_report.rb                  |   4 +-
 .../plugins/module_generator/README.md        |   4 +-
 .../config/module_generator.yml               |   2 +-
 .../stdout_gtestlike_tests_report/README.md   |   4 +-
 .../plugins/stdout_ide_tests_report/README.md |   2 +-
 .../stdout_pretty_tests_report/README.md      |   2 +-
 .../assets/template.erb                       |   1 -
 .../lib/stdout_pretty_tests_report.rb         |   8 +-
 .../ceedling/plugins/subprojects/README.md    |  14 +-
 .../plugins/subprojects/subprojects.rake      |   3 +-
 .../plugins/teamcity_tests_report/README.md   |   2 +-
 .../vendor/c_exception/lib/CException.c       |   1 -
 .../vendor/c_exception/lib/meson.build        |   2 +-
 .../vendor/ceedling/vendor/cmock/src/cmock.c  |   1 -
 .../ceedling/vendor/cmock/src/meson.build     |   2 +-
 .../vendor/ceedling/vendor/diy/lib/diy.rb     |  60 +-
 .../ceedling/vendor/diy/lib/diy/factory.rb    |   5 +-
 .../vendor/unity/auto/generate_config.yml     |   2 +-
 .../ceedling/vendor/unity/src/meson.build     |   2 +-
 tools/build_board.py                          |   2 +-
 tools/build_utils.py                          |   2 +-
 tools/iar_template.ipcf                       |   2 +-
 tools/mksunxi.py                              |   2 +-
 tools/pcapng_to_corpus.py                     |  10 +-
 tools/usb_drivers/tinyusb_win_usbser.inf      |   2 +-
 581 files changed, 2553 insertions(+), 2694 deletions(-)

diff --git a/.gitattributes b/.gitattributes
index 2342decc3..140ae8929 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -1,10 +1,10 @@
 # Set the default behavior, in case people don't have core.autocrlf set.
 * text=auto
 
-*.c text 
-*.cpp text 
+*.c text
+*.cpp text
 *.h text
-*.icf text 
+*.icf text
 *.js text
 *.json text
 *.ld text
diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index 8c39b95e1..dc5f0ee16 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -54,7 +54,7 @@ body:
         Exact steps in chronological order, details should be specific e.g if you use a command/script to test with, please post it as well.
         1. Go to '...'
         2. Click on '....'
-        3. See error      
+        3. See error
     validations:
       required: true
 
@@ -63,9 +63,9 @@ body:
       label: Debug Log as txt file
       placeholder: |
         Attach your debug log txt file here, where the issue occurred, best with comments to explain the actual events.
-        
+
         Note1: Please DO NOT paste your lengthy log contents here since it hurts the readability.
-        Note2: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h. 
+        Note2: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h.
         More information can be found at [example's readme](https://github.com/hathach/tinyusb/blob/master/docs/getting_started.md)
     validations:
       required: false
diff --git a/.github/workflows/trigger.yml b/.github/workflows/trigger.yml
index 11e58d86c..86c699dac 100644
--- a/.github/workflows/trigger.yml
+++ b/.github/workflows/trigger.yml
@@ -43,7 +43,7 @@ jobs:
         if [ -n "$(git status --porcelain)" ]; then
           git add .
           git commit --message "Update from https://github.com/$GITHUB_REPOSITORY/commit/$GITHUB_SHA"
-          git push 
+          git push
         fi
 
     - name: Create tinyusb_src Release
@@ -53,7 +53,7 @@ jobs:
         cd tinyusb_src
         git tag ${{ github.event.release.tag_name }}
         git push origin ${{ github.event.release.tag_name }}
-        
+
         # Send POST reqwuest to release https://docs.github.com/en/rest/reference/repos#create-a-release
         bb="For release note, please checkout https://github.com/hathach/tinyusb/releases/tag/${{ github.event.release.tag_name }}"
         curl -X POST -H "Authorization: token ${{ secrets.API_TOKEN_GITHUB }}" -H "Accept: application/vnd.github.v3+json" --data '{"tag_name": "${{ github.event.release.tag_name }}", "name": "${{ github.event.release.name }}", "body": "$bb", "draft": ${{ github.event.release.draft }}, "prerelease": ${{ github.event.release.prerelease }}}' https://api.github.com/repos/hathach/tinyusb_src/releases
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index ea2372f07..976f04e63 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -13,11 +13,11 @@ repos:
 
 -   repo: local
     hooks:
-    -   id: codespell
-        name: codespell
-        entry: codespell
-        types_or: [c, header]
-        language: system
+    #-   id: codespell
+    #    name: codespell
+    #    entry: codespell
+    #    types_or: [c, header]
+    #    language: system
 
     -   id: unit-test
         name: unit-test
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index e83cd90fd..1421b397a 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -15,4 +15,3 @@ python:
 submodules:
   include: []
   recursive: false
-    
\ No newline at end of file
diff --git a/docs/assets/stack.svg b/docs/assets/stack.svg
index 85fe35e96..ed46c8649 100644
--- a/docs/assets/stack.svg
+++ b/docs/assets/stack.svg
@@ -1 +1 @@
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diff --git a/docs/contributing/code_of_conduct.rst b/docs/contributing/code_of_conduct.rst
index b52bf14c5..82627099f 120000
--- a/docs/contributing/code_of_conduct.rst
+++ b/docs/contributing/code_of_conduct.rst
@@ -1 +1 @@
-../../CODE_OF_CONDUCT.rst
\ No newline at end of file
+../../CODE_OF_CONDUCT.rst
diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index 451e3dace..ca715cb58 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -15,7 +15,7 @@ Changelog
 - Fix tu_fifo memory overflown when repeatedly write to overwritable fifo (accumulated more than 2 depths)
 - Better support for IAR (ARM) with ci build check for stm32 mcus.
 - Fix Windows build for some mingw gnu make situations
-  
+
 Controller Driver (DCD & HCD)
 -----------------------------
 
@@ -27,7 +27,7 @@ Controller Driver (DCD & HCD)
   - Fix endpoint internal state when closed
   - Fix reception of large ISO packets
 
-- [rp2040] 
+- [rp2040]
 
   - [dcd] Implement workaround for Errata 15. This enable SOF when bulk-in endpoint is in use and reduce its bandwidth to only 80%
   - [hcd] Fix shared irq slots filling up when hcd_init() is called multiple times
@@ -51,7 +51,7 @@ Device Stack
 
   - Support port name strings
   - fix MS Header wTotalLength computation
- 
+
 - [HID]
 
   - Add FIDO descriptor template
@@ -60,7 +60,7 @@ Device Stack
 - [CDC]
 
   - Fix autoflush for FIFO < MPS
-  - Fix tx fifo memory overflown when DTR is not set and tud_cdc_write() is called repeatedly with large enough data  
+  - Fix tx fifo memory overflown when DTR is not set and tud_cdc_write() is called repeatedly with large enough data
 
 - [USBTMC] Fix packet size with highspeed
 
@@ -100,14 +100,14 @@ Controller Driver (DCD & HCD)
   - Fix overwrite with grstctl when disable endpoint
 - [EHCI] Fix an issue with EHCI driver
 - [msp430] Fix for possible bug in msp430-elf-gcc 9.3.0
-- [nrf5x] Fix DMA access race condition using atomic function 
+- [nrf5x] Fix DMA access race condition using atomic function
 - [pic32] Fix PIC32 santiy
 - [rp2040]
 
   - Add PICO-PIO-USB as controller (device/host) support for rp2040
   - Use shared IRQ handlers, so user can also hook the USB IRQ
   - Fix resumed signal not reported to device stack
-- [stm32fsdev] Add support for stm32wb55 
+- [stm32fsdev] Add support for stm32wb55
 
 Device Stack
 ------------
@@ -159,7 +159,7 @@ Controller Driver (DCD & HCD)
 - [F1C100s] Add new DCD for Allwinner F1C100s family
 - [PIC32MZ] Add new DCD for PIC32MZ
 - [nRF] Fix/Enhance various race condition with: EASY DMA, request HFXO, EPOUT
-- [ChipIdea] rename Transdimension to more popular ChipIdea Highspeed, 
+- [ChipIdea] rename Transdimension to more popular ChipIdea Highspeed,
 - [RP2040] various update/fix for hcd/dcd
 - [FT9XX] new DCD port for Bridgetek FT90x and FT93x devices
 - [DA1469X] Fix resume
@@ -246,7 +246,7 @@ RP2040
 ^^^^^^
 
 - Add RP2040 suspend & resume support
-- Implement double buffer for both host and device (#891). However device EPOUT is still single buffered due to techinical issue with short packet 
+- Implement double buffer for both host and device (#891). However device EPOUT is still single buffered due to techinical issue with short packet
 
 Device Stack
 ------------
@@ -267,7 +267,7 @@ DFU
 ^^^
 
 - Enhance DFU implementation to support multiple alternate interface and better support bwPollTimeout
-- Rename CFG_TUD_DFU_MODE to simply CFG_TUD_DFU 
+- Rename CFG_TUD_DFU_MODE to simply CFG_TUD_DFU
 
 HID
 ^^^
@@ -287,7 +287,7 @@ UAC2
 ^^^^
 
 - Fix bug and enhance of UAC2
- 
+
 Vendor
 ^^^^^^
 
@@ -479,7 +479,7 @@ Host Controller Driver (HCD)
   - Move echi/ohci files to portable/
   - Rename hcd_lpc18_43 to hcd_transdimension
   - Sub hcd API with hcd_ehci_init(), hcd_ehci_register_addr()
-  
+
 - Update NXP transdimention hcd_init() to reset controller to host mode
 
   - Ported hcd to rt10xx
@@ -529,13 +529,13 @@ Device Controller Driver
 
 - ESP32-S2:
   - Add bus suspend and wakeup support
-  
+
 - SAMD21:
   - Fix (walkaround) samd21 setup_packet overflow by USB DMA
-  
+
 - STM32 Synopsys:
   - Rework USB FIFO allocation scheme and allow RX FIFO size reduction
-  
+
 - Sony CXD56
   - Update Update Spresense SDK to 2.0.2
   - Fix dcd issues with setup packets
@@ -554,17 +554,17 @@ USB Device
 
 - CDC
   - Allow to transmit data, even if the host does not support control line states i.e set DTR
-  
+
 - HID
   - change default CFG_TUD_HID_EP_BUFSIZE from 16 to 64
-  
+
 - MIDI
   - Fix midi sysex sending bug
-  
+
 - MSC
   - Invoke only scsi complete callback after status transaction is complete.
   - Fix scsi_mode_sense6_t padding, which cause IAR compiler internal error.
-  
+
 - USBTMC
   - Change interrupt endpoint example size to 8 instead of 2 for better compatibility with mcu
 
@@ -614,20 +614,20 @@ Device Controller Driver
   - Fix FIFO flush during stall
   - Implement dcd_edpt_close() API
   - Support F105, F107
-  
+
 - Enhance STM32 fsdev
   - Improve dcd fifo allocation
   - Fix ISTR race condition
   - Support remap USB IRQ on supported MCUs
   - Implement dcd_edpt_close() API
-  
+
 - Enhance NUC 505: enhance set configure behavior
 
 - Enhance SAMD
   - Fix race condition with setup packet
   - Add SAMD11 option `OPT_MCU_SAMD11`
   - Add SAME5x option `OPT_MCU_SAME5X`
-  
+
 - Fix SAMG control data toggle and stall race condition
 
 - Enhance nRF
@@ -659,7 +659,7 @@ USB Device
   - `usbd_driver_open()` add max length argument, and return length of interface (0 for not supported). Return value is used for finding appropriate driver
   - Add application implemented class driver via `usbd_app_driver_get_cb()`
   - IAD is handled to assign driver id
-  
+
 - Added `tud_descriptor_device_qualifier_cb()` callback
 - Optimize `tu_fifo` bulk write/read transfer
 - Forward non-std control request to class driver
@@ -675,12 +675,12 @@ USB Device
   - Send zero length packet for end of data when needed
   - Add `tud_cdc_tx_complete_cb()` callback
   - Change tud_cdc_n_write_flush() return number of bytes forced to transfer, and flush when writing enough data to fifo
-  
+
 - MIDI:
   - Add packet interface
   - Add multiple jack descriptors
   - Fix MIDI driver for sysex
-  
+
 - DFU Runtime: fix response to SET_INTERFACE and DFU_GETSTATUS request
 
 - Rename some configure macro to make it clear that those are used directly for endpoint transfer
@@ -688,7 +688,7 @@ USB Device
   - CFG_TUD_CDC_EPSIZE to CFG_TUD_CDC_EP_BUFSIZE
   - CFG_TUD_MSC_BUFSIZE to CFG_TUD_MSC_EP_BUFSIZE
   - CFG_TUD_MIDI_EPSIZE to CFG_TUD_MIDI_EP_BUFSIZE
-  
+
 - HID:
   - Fix gamepad template descriptor
   - Add multiple HID interface API
@@ -700,7 +700,7 @@ USB Host
 - Rework USB host stack (still work in progress)
    - Fix compile error with pipehandle
    - Rework usbh control and enumeration as non-blocking
-   
+
 - Improve Hub, MSC, HID host driver
 
 Examples
@@ -713,7 +713,7 @@ Examples
 - Enhance `net_lwip_webserver` example
   - Add multiple configuration: RNDIS for Windows, CDC-ECM for macOS (Linux will work with both)
   - Update lwip to STABLE-2_1_2_RELEASE for net_lwip_webserver
-  
+
 - Added new Audio example: audio_test uac2_headsest
 
 New Boards
diff --git a/docs/info/contributors.rst b/docs/info/contributors.rst
index b3748ccb5..02608919f 120000
--- a/docs/info/contributors.rst
+++ b/docs/info/contributors.rst
@@ -1 +1 @@
-../../CONTRIBUTORS.rst
\ No newline at end of file
+../../CONTRIBUTORS.rst
diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index e328757ba..ef4a6ba61 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -44,18 +44,18 @@ For your convenience, TinyUSB contains a handful of examples for both host and d
    $ git clone https://github.com/hathach/tinyusb tinyusb
    $ cd tinyusb
 
-Some TinyUSB examples also requires external submodule libraries in ``/lib`` such as FreeRTOS, Lightweight IP to build. Run following command to fetch them 
+Some TinyUSB examples also requires external submodule libraries in ``/lib`` such as FreeRTOS, Lightweight IP to build. Run following command to fetch them
 
 .. code-block::
 
    $ git submodule update --init lib
 
-Some ports will also require a port-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples. They are out of scope for tinyusb, you should download/install it first according to its manufacturer guide. 
+Some ports will also require a port-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples. They are out of scope for tinyusb, you should download/install it first according to its manufacturer guide.
 
 Build
 ^^^^^
 
-To build example, first change directory to an example folder. 
+To build example, first change directory to an example folder.
 
 .. code-block::
 
@@ -118,7 +118,7 @@ To compile for debugging add ``DEBUG=1``\ , for example
 Log
 ~~~
 
-Should you have an issue running example and/or submitting an bug report. You could enable TinyUSB built-in debug logging with optional ``LOG=``. LOG=1 will only print out error message, LOG=2 print more information with on-going events. LOG=3 or higher is not used yet. 
+Should you have an issue running example and/or submitting an bug report. You could enable TinyUSB built-in debug logging with optional ``LOG=``. LOG=1 will only print out error message, LOG=2 print more information with on-going events. LOG=3 or higher is not used yet.
 
 .. code-block::
 
@@ -127,7 +127,7 @@ Should you have an issue running example and/or submitting an bug report. You co
 Logger
 ~~~~~~
 
-By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols: 
+By default log message is printed via on-board UART which is slow and take lots of CPU time comparing to USB speed. If your board support on-board/external debugger, it would be more efficient to use it for logging. There are 2 protocols:
 
 
 * `LOGGER=rtt`: use `Segger RTT protocol <https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/>`_
@@ -178,12 +178,12 @@ IAR Project Connection files are provided to import TinyUSB stack into your proj
 
 
   * Take example of STM32F0:
-  
+
     -  You need `stm32l0xx.h`, `startup_stm32f0xx.s`, `system_stm32f0xx.c`.
 
     - `STM32L0xx_HAL_Driver` is only needed to run examples, TinyUSB stack itself doesn't rely on MCU's SDKs.
 
-* Open `Tools -> Configure Custom Argument Variables` (Switch to `Global` tab if you want to do it for all your projects) 
+* Open `Tools -> Configure Custom Argument Variables` (Switch to `Global` tab if you want to do it for all your projects)
    Click `New Group ...`, name it to `TUSB`, Click `Add Variable ...`, name it to `TUSB_DIR`, change it's value to the path of your TinyUSB stack,
    for example `C:\\tinyusb`
 
diff --git a/examples/device/audio_4_channel_mic/skip.txt b/examples/device/audio_4_channel_mic/skip.txt
index ae9b57f1f..1ee86a485 100644
--- a/examples/device/audio_4_channel_mic/skip.txt
+++ b/examples/device/audio_4_channel_mic/skip.txt
@@ -1,3 +1,3 @@
 mcu:SAMD11
 mcu:SAME5X
-mcu:SAMG
\ No newline at end of file
+mcu:SAMG
diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index a6af5fd19..26d8c48c5 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Reinhard Panhuber
diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
index 9ab15135d..8312b4e28 100644
--- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
+++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
@@ -31,4 +31,3 @@ if __name__ == '__main__':
     plt.ylabel('Amplitude')
     plt.title('MicNode 4 Channel')
     plt.show()
-    
\ No newline at end of file
diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index 8929f3057..8bf9eebc4 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt
index cb321f9a8..f6e10e2ea 100644
--- a/examples/device/audio_test/CMakeLists.txt
+++ b/examples/device/audio_test/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/audio_test/skip.txt b/examples/device/audio_test/skip.txt
index ae9b57f1f..1ee86a485 100644
--- a/examples/device/audio_test/skip.txt
+++ b/examples/device/audio_test/skip.txt
@@ -1,3 +1,3 @@
 mcu:SAMD11
 mcu:SAME5X
-mcu:SAMG
\ No newline at end of file
+mcu:SAMG
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index 56961e427..f9cc63cdd 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Reinhard Panhuber
diff --git a/examples/device/audio_test/src/plot_audio_samples.py b/examples/device/audio_test/src/plot_audio_samples.py
index 2303df3d0..1504684a6 100644
--- a/examples/device/audio_test/src/plot_audio_samples.py
+++ b/examples/device/audio_test/src/plot_audio_samples.py
@@ -32,7 +32,6 @@ if __name__ == '__main__':
     plt.ylabel('Amplitude')
     plt.title('MicNode')
     plt.show()
-    
+
     samples = np.array(myrecording)
     np.savetxt('Output.csv', samples, delimiter=",", fmt='%s')
-    
\ No newline at end of file
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index da3e203d7..891e90802 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/audio_test_multi_rate/CMakeLists.txt b/examples/device/audio_test_multi_rate/CMakeLists.txt
index cb321f9a8..f6e10e2ea 100644
--- a/examples/device/audio_test_multi_rate/CMakeLists.txt
+++ b/examples/device/audio_test_multi_rate/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/audio_test_multi_rate/skip.txt b/examples/device/audio_test_multi_rate/skip.txt
index ae9b57f1f..1ee86a485 100644
--- a/examples/device/audio_test_multi_rate/skip.txt
+++ b/examples/device/audio_test_multi_rate/skip.txt
@@ -1,3 +1,3 @@
 mcu:SAMD11
 mcu:SAME5X
-mcu:SAMG
\ No newline at end of file
+mcu:SAMG
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
index 0e11a509b..4dd53dd34 100644
--- a/examples/device/audio_test_multi_rate/src/main.c
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Reinhard Panhuber
@@ -165,7 +165,7 @@ bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_reque
   (void)rhport;
   //uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
   uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
-  
+
   // Clear buffer when streaming format is changed
   if(alt != 0)
   {
@@ -257,7 +257,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
       return false;
     }
   }
-  
+
   // Clock Source unit
   if ( entityID == UAC2_ENTITY_CLOCK )
   {
@@ -279,7 +279,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
         return false;
     }
   }
-  
+
   return false;    // Yet not implemented
 }
 
@@ -491,7 +491,7 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin
       pData_32[cnt] = (uint32_t)startVal++ << 16U;
     }
   }
-  
+
   return true;
 }
 
diff --git a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
index 4a5f15a9c..c92e49957 100644
--- a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
+++ b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py
@@ -32,7 +32,6 @@ if __name__ == '__main__':
     plt.ylabel('Amplitude')
     plt.title('MicNode')
     plt.show()
-    
+
     samples = np.array(myrecording)
     np.savetxt('Output.csv', samples, delimiter=",", fmt='%s')
-    
\ No newline at end of file
diff --git a/examples/device/audio_test_multi_rate/src/tusb_config.h b/examples/device/audio_test_multi_rate/src/tusb_config.h
index d8b6511d6..1c8288bce 100644
--- a/examples/device/audio_test_multi_rate/src/tusb_config.h
+++ b/examples/device/audio_test_multi_rate/src/tusb_config.h
@@ -111,7 +111,7 @@ extern "C" {
 
 // How many formats are used, need to adjust USB descriptor if changed
 #define CFG_TUD_AUDIO_FUNC_1_N_FORMATS                               2
-  
+
 // 16bit in 16bit slots
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX          2
 #define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX                  16
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.c b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
index 92e791a72..276bf8aa0 100644
--- a/examples/device/audio_test_multi_rate/src/usb_descriptors.c
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.h b/examples/device/audio_test_multi_rate/src/usb_descriptors.h
index 77e2fe6c1..8d8a03e49 100644
--- a/examples/device/audio_test_multi_rate/src/usb_descriptors.h
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2022 HiFiPhile
@@ -99,4 +99,4 @@
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
 
-#endif
\ No newline at end of file
+#endif
diff --git a/examples/device/board_test/src/CMakeLists.txt b/examples/device/board_test/src/CMakeLists.txt
index e4e1f4e9a..37625f441 100644
--- a/examples/device/board_test/src/CMakeLists.txt
+++ b/examples/device/board_test/src/CMakeLists.txt
@@ -2,7 +2,7 @@
 idf_component_register(SRCS "main.c"
                     INCLUDE_DIRS "."
                     REQUIRES freertos soc)
-                    
+
 file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake)
 
 if(EXISTS ${board_cmake})
diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index 0289ca15f..e8e393717 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt
index abc4d91da..acaa54198 100644
--- a/examples/device/cdc_dual_ports/CMakeLists.txt
+++ b/examples/device/cdc_dual_ports/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 0264f0566..c0296191b 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index 4eb8c7c27..8be404cc9 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index fa6e83b7e..8e4db9d29 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/cdc_msc/skip.txt b/examples/device/cdc_msc/skip.txt
index d844feae8..eadb6e74a 100644
--- a/examples/device/cdc_msc/skip.txt
+++ b/examples/device/cdc_msc/skip.txt
@@ -1 +1 @@
-mcu:SAMD11
\ No newline at end of file
+mcu:SAMD11
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index c83299e59..207dd728c 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index e67e381ce..f8f37a577 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 6b59ed50f..44c849277 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index cfb14aa2b..0e8a24d02 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c
index a895f4738..707c8d578 100644
--- a/examples/device/cdc_msc_freertos/src/msc_disk.c
+++ b/examples/device/cdc_msc_freertos/src/msc_disk.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
index 30a712275..822442724 100644
--- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c
+++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt
index abc4d91da..acaa54198 100644
--- a/examples/device/dfu_runtime/CMakeLists.txt
+++ b/examples/device/dfu_runtime/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index bd9a91c27..4ec2fa31d 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt
index fa6e83b7e..8e4db9d29 100644
--- a/examples/device/dynamic_configuration/CMakeLists.txt
+++ b/examples/device/dynamic_configuration/CMakeLists.txt
@@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/dynamic_configuration/skip.txt b/examples/device/dynamic_configuration/skip.txt
index d844feae8..eadb6e74a 100644
--- a/examples/device/dynamic_configuration/skip.txt
+++ b/examples/device/dynamic_configuration/skip.txt
@@ -1 +1 @@
-mcu:SAMD11
\ No newline at end of file
+mcu:SAMD11
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index 33a603343..90794e979 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c
index e8cb03fdd..27856a1a4 100644
--- a/examples/device/dynamic_configuration/src/msc_disk.c
+++ b/examples/device/dynamic_configuration/src/msc_disk.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index 092229b99..0590bd679 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_boot_interface/CMakeLists.txt b/examples/device/hid_boot_interface/CMakeLists.txt
index abc4d91da..acaa54198 100644
--- a/examples/device/hid_boot_interface/CMakeLists.txt
+++ b/examples/device/hid_boot_interface/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/hid_boot_interface/Makefile b/examples/device/hid_boot_interface/Makefile
index d58a539e8..b3f2cc588 100644
--- a/examples/device/hid_boot_interface/Makefile
+++ b/examples/device/hid_boot_interface/Makefile
@@ -8,7 +8,7 @@ INC += \
 EXAMPLE_SOURCE = \
 	src/main.c \
 	src/usb_descriptors.c
-	
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 include ../../rules.mk
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index b13428041..1a155996a 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.c b/examples/device/hid_boot_interface/src/usb_descriptors.c
index a0d7e9f15..10345ab41 100644
--- a/examples/device/hid_boot_interface/src/usb_descriptors.c
+++ b/examples/device/hid_boot_interface/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.h b/examples/device/hid_boot_interface/src/usb_descriptors.h
index 57cf0e2c0..6fee9e223 100644
--- a/examples/device/hid_boot_interface/src/usb_descriptors.h
+++ b/examples/device/hid_boot_interface/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt
index abc4d91da..acaa54198 100644
--- a/examples/device/hid_composite/CMakeLists.txt
+++ b/examples/device/hid_composite/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 05315f266..4edb045c2 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_composite/src/usb_descriptors.c b/examples/device/hid_composite/src/usb_descriptors.c
index 2988baee2..347bbf29a 100644
--- a/examples/device/hid_composite/src/usb_descriptors.c
+++ b/examples/device/hid_composite/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_composite/src/usb_descriptors.h b/examples/device/hid_composite/src/usb_descriptors.h
index ca8925ad9..e733d31dd 100644
--- a/examples/device/hid_composite/src/usb_descriptors.h
+++ b/examples/device/hid_composite/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 7c9619c4b..ca02af100 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.c b/examples/device/hid_composite_freertos/src/usb_descriptors.c
index 4df12d3db..30f327d5e 100644
--- a/examples/device/hid_composite_freertos/src/usb_descriptors.c
+++ b/examples/device/hid_composite_freertos/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.h b/examples/device/hid_composite_freertos/src/usb_descriptors.h
index ca8925ad9..e733d31dd 100644
--- a/examples/device/hid_composite_freertos/src/usb_descriptors.h
+++ b/examples/device/hid_composite_freertos/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt
index abc4d91da..acaa54198 100644
--- a/examples/device/hid_generic_inout/CMakeLists.txt
+++ b/examples/device/hid_generic_inout/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/hid_generic_inout/hid_test.js b/examples/device/hid_generic_inout/hid_test.js
index daa958fd5..16bc723e2 100644
--- a/examples/device/hid_generic_inout/hid_test.js
+++ b/examples/device/hid_generic_inout/hid_test.js
@@ -48,7 +48,7 @@ if( deviceInfo ) {
 
 
 function anySupportedBoard(d) {
-	
+
 	for (var key in boards) {
 	    if (boards.hasOwnProperty(key)) {
 	        if (isDevice(boards[key],d)) {
@@ -65,4 +65,3 @@ function isDevice(board,d){
 	// product id 0xff is matches all
 	return d.vendorId==board[0] && (d.productId==board[1] || board[1] == 0xFFFF);
 }
-
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 5b7daf118..6649b49b5 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_generic_inout/src/usb_descriptors.c b/examples/device/hid_generic_inout/src/usb_descriptors.c
index cd4838407..8377a0f47 100644
--- a/examples/device/hid_generic_inout/src/usb_descriptors.c
+++ b/examples/device/hid_generic_inout/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt
index abc4d91da..acaa54198 100644
--- a/examples/device/hid_multiple_interface/CMakeLists.txt
+++ b/examples/device/hid_multiple_interface/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt
index abc4d91da..acaa54198 100644
--- a/examples/device/midi_test/CMakeLists.txt
+++ b/examples/device/midi_test/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 3310348bd..66fa72063 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c
index c84a873b1..4845dcf57 100644
--- a/examples/device/midi_test/src/usb_descriptors.c
+++ b/examples/device/midi_test/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt
index 9e834ae21..9188ab06c 100644
--- a/examples/device/msc_dual_lun/CMakeLists.txt
+++ b/examples/device/msc_dual_lun/CMakeLists.txt
@@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/msc_dual_lun/skip.txt b/examples/device/msc_dual_lun/skip.txt
index 3549c702a..47e561cf0 100644
--- a/examples/device/msc_dual_lun/skip.txt
+++ b/examples/device/msc_dual_lun/skip.txt
@@ -1,2 +1,2 @@
 mcu:SAMD11
-mcu:MKL25ZXX
\ No newline at end of file
+mcu:MKL25ZXX
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index 96790d20c..0a7284939 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c
index 2b773b43b..b1047acdb 100644
--- a/examples/device/msc_dual_lun/src/msc_disk_dual.c
+++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c
index d8dbb5ce3..2de81111c 100644
--- a/examples/device/msc_dual_lun/src/usb_descriptors.c
+++ b/examples/device/msc_dual_lun/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 9fe1a325e..5f1e37931 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -80,4 +80,4 @@ if (EXISTS ${TOP}/lib/lwip/src)
     # Configure compilation flags and libraries for the example... see the corresponding function
     # in hw/bsp/FAMILY/family.cmake for details.
     family_configure_device_example(${PROJECT})
-endif()
\ No newline at end of file
+endif()
diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt
index 68761b058..b0e5235ac 100644
--- a/examples/device/net_lwip_webserver/skip.txt
+++ b/examples/device/net_lwip_webserver/skip.txt
@@ -7,4 +7,4 @@ mcu:STM32L0
 mcu:MKL25ZXX
 family:broadcom_64bit
 family:broadcom_32bit
-board:curiosity_nano
\ No newline at end of file
+board:curiosity_nano
diff --git a/examples/device/net_lwip_webserver/src/arch/cc.h b/examples/device/net_lwip_webserver/src/arch/cc.h
index 56a0cacf7..9f30b91cb 100644
--- a/examples/device/net_lwip_webserver/src/arch/cc.h
+++ b/examples/device/net_lwip_webserver/src/arch/cc.h
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
@@ -11,21 +11,21 @@
  *    this list of conditions and the following disclaimer in the documentation
  *    and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
+ *    derived from this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  * OF SUCH DAMAGE.
  *
  * This file is part of the lwIP TCP/IP stack.
- * 
+ *
  * Author: Adam Dunkels <adam@sics.se>
  *
  */
@@ -42,7 +42,7 @@ typedef int sys_prot_t;
 #if defined (__ICCARM__)
 
 #define PACK_STRUCT_BEGIN
-#define PACK_STRUCT_STRUCT 
+#define PACK_STRUCT_STRUCT
 #define PACK_STRUCT_END
 #define PACK_STRUCT_FIELD(x) x
 #define PACK_STRUCT_USE_INCLUDES
@@ -50,7 +50,7 @@ typedef int sys_prot_t;
 #elif defined (__CC_ARM)
 
 #define PACK_STRUCT_BEGIN __packed
-#define PACK_STRUCT_STRUCT 
+#define PACK_STRUCT_STRUCT
 #define PACK_STRUCT_END
 #define PACK_STRUCT_FIELD(x) x
 
diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h
index a215017c7..336c9243d 100644
--- a/examples/device/net_lwip_webserver/src/lwipopts.h
+++ b/examples/device/net_lwip_webserver/src/lwipopts.h
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
@@ -11,21 +11,21 @@
  *    this list of conditions and the following disclaimer in the documentation
  *    and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
+ *    derived from this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  * OF SUCH DAMAGE.
  *
  * This file is part of the lwIP TCP/IP stack.
- * 
+ *
  * Author: Simon Goldschmidt
  *
  */
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 33b4d38b6..88081ffe2 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Peter Lawrence
@@ -39,7 +39,7 @@ and likely their manufacturer has not tested such functionality.  Some code work
 The smartphone may only have an ECM driver, but refuse to automatically pick ECM (unlike the OSes above);
 try modifying ./examples/devices/net_lwip_webserver/usb_descriptors.c so that CONFIG_ID_ECM is default.
 
-The smartphone may be artificially picky about which Ethernet MAC address to recognize; if this happens, 
+The smartphone may be artificially picky about which Ethernet MAC address to recognize; if this happens,
 try changing the first byte of tud_network_mac_address[] below from 0x02 to 0x00 (clearing bit 1).
 */
 
@@ -170,7 +170,7 @@ bool dns_query_proc(const char *name, ip4_addr_t *addr)
 
 bool tud_network_recv_cb(const uint8_t *src, uint16_t size)
 {
-  /* this shouldn't happen, but if we get another packet before 
+  /* this shouldn't happen, but if we get another packet before
   parsing the previous, we must signal our inability to accept it */
   if (received_frame) return false;
 
diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c
index bee51790a..3c0ed3db7 100644
--- a/examples/device/net_lwip_webserver/src/usb_descriptors.c
+++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -77,7 +77,7 @@ tusb_desc_device_t const desc_device =
     .bDeviceClass       = TUSB_CLASS_MISC,
     .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
     .bDeviceProtocol    = MISC_PROTOCOL_IAD,
-    
+
     .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
     .idVendor           = 0xCafe,
diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt
index abc4d91da..acaa54198 100644
--- a/examples/device/uac2_headset/CMakeLists.txt
+++ b/examples/device/uac2_headset/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 01707d51b..bafd40d34 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenberg
@@ -176,7 +176,7 @@ static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t
         rangef.subrange[i].bRes = 0;
         TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
       }
-      
+
       return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef));
     }
   }
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 07c86b903..0a0b4c602 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Ha Thach (tinyusb.org)
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 342b4fac1..5525c916a 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenbreg
diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt
index c49603c26..b4678dc5e 100644
--- a/examples/device/usbtmc/CMakeLists.txt
+++ b/examples/device/usbtmc/CMakeLists.txt
@@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 6945d8743..da7f0418a 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/usbtmc/visaQuery.py b/examples/device/usbtmc/visaQuery.py
index c4e5ad2b9..ca65daf97 100644
--- a/examples/device/usbtmc/visaQuery.py
+++ b/examples/device/usbtmc/visaQuery.py
@@ -36,8 +36,8 @@ def test_trig():
 	time.sleep(0.3) # SRQ may have some delay
 	assert (inst.read_stb() & 0x40), "SRQ not set after 0.3 seconds"
 	assert (inst.read_stb() == 0)
-	
-	
+
+
 def test_mav():
 	inst.write("delay 50")
 	inst.read_stb() # clear STB
@@ -45,15 +45,15 @@ def test_mav():
 	inst.write("123")
 	time.sleep(0.3)
 	assert (inst.read_stb() & 0x10), "MAV not set after 0.5 seconds"
-	
+
 	rsp = inst.read()
 	assert(rsp == "123\r\n")
-	
-	
+
+
 def test_srq():
 	assert (inst.read_stb() == 0)
 	inst.write("123")
-	
+
 	#inst.enable_event(pyvisa.constants.VI_EVENT_SERVICE_REQ, pyvisa.constants.VI_QUEUE)
 	#waitrsp = inst.wait_on_event(pyvisa.constants.VI_EVENT_SERVICE_REQ, 5000)
 	#inst.discard_events(pyvisa.constants.VI_EVENT_SERVICE_REQ, pyvisa.constants.VI_QUEUE)
@@ -64,7 +64,7 @@ def test_srq():
 	assert (stb == 0x50),msg
 
 	assert (inst.read_stb() == 0x10), "SRQ set at second read!"
-	
+
 	rsp = inst.read()
 	assert(rsp == "123\r\n")
 
@@ -110,7 +110,7 @@ def test_abort_in():
 	inst.timeout = 800
 	y = inst.read()
 	assert(y == "xxx\r\n")
-	
+
 def test_indicate():
 	# perform indicator pulse
 	usb_iface = inst.get_visa_attribute(pyvisa.constants.VI_ATTR_USB_INTFC_NUM)
@@ -120,8 +120,8 @@ def test_indicate():
 		assert(retv == b'\x01')
 	else:
 		assert((retv[1] == pyvisa.constants.StatusCode(0)) and (retv[0] == b'\x01')), f"indicator pulse failed: retv={retv}"
-	
-	
+
+
 def test_multi_read():
 	old_chunk_size = inst.chunk_size
 	longstr = "0123456789abcdefghijklmnopqrstuvwxyz" * 10
@@ -133,7 +133,7 @@ def test_multi_read():
 	y = inst.read()
 	assert (x + "\r\n" == y)
 	#inst.chunk_size = old_chunk_size
-	
+
 def test_stall_ep0():
 	usb_iface = inst.get_visa_attribute(pyvisa.constants.VI_ATTR_USB_INTFC_NUM)
 	inst.read_stb()
@@ -143,7 +143,7 @@ def test_stall_ep0():
 		assert(False)
 	except pyvisa.VisaIOError:
 		pass
-	
+
 	assert (inst.read_stb() == 0)
 
 
@@ -153,7 +153,7 @@ print(reslist)
 
 if (len(reslist) == 0):
     sys.exit()
-	
+
 inst = rm.open_resource(reslist[0]);
 inst.timeout = 3000
 
diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt
index b92a2b804..f1ef247e1 100644
--- a/examples/device/video_capture/CMakeLists.txt
+++ b/examples/device/video_capture/CMakeLists.txt
@@ -31,4 +31,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 3ceebe821..08db1b00f 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 0cf772010..af18d15d1 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index f1ed3c8e9..93f148a82 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenbreg
diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt
index abc4d91da..acaa54198 100644
--- a/examples/device/webusb_serial/CMakeLists.txt
+++ b/examples/device/webusb_serial/CMakeLists.txt
@@ -25,4 +25,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index 604d30a83..24456f9f3 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c
index 99f5caaf9..b2593001c 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.c
+++ b/examples/device/webusb_serial/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/device/webusb_serial/src/usb_descriptors.h b/examples/device/webusb_serial/src/usb_descriptors.h
index 19f1ff3f3..a1c4a2cf1 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.h
+++ b/examples/device/webusb_serial/src/usb_descriptors.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index bd7870274..817c63c70 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
index 6b0a89127..63b6bc603 100644
--- a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
+++ b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index 51cab2de0..bb7fa850e 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index b34810252..23312296f 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c
index 797d55f8a..e9c9676b8 100644
--- a/examples/host/cdc_msc_hid/src/msc_app.c
+++ b/examples/host/cdc_msc_hid/src/msc_app.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -68,4 +68,3 @@ void tuh_msc_umount_cb(uint8_t dev_addr)
   (void) dev_addr;
   printf("A MassStorage device is unmounted\r\n");
 }
-
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index 299a3ff10..3380e9246 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index ab2cfd498..40c88a7d3 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index eef28fe12..003e2865b 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/examples/rules.mk b/examples/rules.mk
index f8e4001ec..56ad89fd0 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -283,4 +283,4 @@ copy-artifact: $(BIN)
 # Print out the value of a make variable.
 # https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile
 print-%:
-	@echo $* = $($*)
\ No newline at end of file
+	@echo $* = $($*)
diff --git a/hw/bsp/ansi_escape.h b/hw/bsp/ansi_escape.h
index 6e62ee20a..15af2f3ab 100644
--- a/hw/bsp/ansi_escape.h
+++ b/hw/bsp/ansi_escape.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 14858c2b6..e715bdf2e 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index 0a10294d0..036556731 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
index 1d3565d5c..84a106346 100644
--- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
index 52e9e45c4..77811d18d 100644
--- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
@@ -2,4 +2,4 @@ CFLAGS += -mcpu=arm1176jzf-s \
           -DBCM_VERSION=2835 \
           -DCFG_TUSB_MCU=OPT_MCU_BCM2835
 
-SUFFIX = 
+SUFFIX =
diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c
index f7a11fb49..42ad4b666 100644
--- a/hw/bsp/broadcom_32bit/family.c
+++ b/hw/bsp/broadcom_32bit/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
index 1d3565d5c..84a106346 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
index 1d3565d5c..84a106346 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c
index f7a11fb49..42ad4b666 100644
--- a/hw/bsp/broadcom_64bit/family.c
+++ b/hw/bsp/broadcom_64bit/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index 3b6b03904..f812c922f 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright 2021 Bridgetek Pte Ltd
@@ -70,7 +70,7 @@ void board_init(void)
     board_uart_write(WELCOME_MSG, sizeof(WELCOME_MSG));
 
 #ifdef BOARD_GPIO_LED
-    gpio_function(BOARD_GPIO_LED, pad_func_0); 
+    gpio_function(BOARD_GPIO_LED, pad_func_0);
     gpio_idrive(BOARD_GPIO_LED, pad_drive_12mA);
     gpio_dir(BOARD_GPIO_LED, pad_dir_output);
 #endif
@@ -233,7 +233,7 @@ int board_uart_write(void const *buf, int len)
 uint32_t board_millis(void)
 {
     uint32_t safe_ms;
-    
+
     CRITICAL_SECTION_BEGIN
     safe_ms = timer_ms;
     CRITICAL_SECTION_END
@@ -254,4 +254,3 @@ void chip_reboot(void)
  	dbg_memory_copy(0xfe, 0, 0, 255);
 #endif
 }
-
diff --git a/hw/bsp/brtmm90x/family.mk b/hw/bsp/brtmm90x/family.mk
index 0ddf47a3a..6df0bfdfe 100644
--- a/hw/bsp/brtmm90x/family.mk
+++ b/hw/bsp/brtmm90x/family.mk
@@ -5,7 +5,7 @@ SKIP_NANOLIB = 1
 # Set to use FT90X prebuilt libraries.
 FT9XX_PREBUILT_LIBS = 0
 ifeq ($(FT9XX_PREBUILT_LIBS),1)
-# If the FT90X toolchain is installed on Windows systems then the SDK 
+# If the FT90X toolchain is installed on Windows systems then the SDK
 # include files and prebuilt libraries are at: %FT90X_TOOLCHAIN%/hardware
 FT9XX_SDK = $(FT90X_TOOLCHAIN)/hardware
 INC += "$(FT9XX_SDK)/include"
@@ -21,7 +21,7 @@ endif
 
 # Add include files which are within the TinyUSB directory structure.
 INC += \
-	$(TOP)/$(BOARD_PATH) 
+	$(TOP)/$(BOARD_PATH)
 
 # Add required C Compiler flags for FT90X.
 CFLAGS += \
@@ -30,7 +30,7 @@ CFLAGS += \
 	-fvar-tracking-assignments \
 	-fmessage-length=0 \
 	-ffunction-sections \
-	-DCFG_TUSB_MCU=OPT_MCU_FT90X 
+	-DCFG_TUSB_MCU=OPT_MCU_FT90X
 
 # Maximum USB device speed supported by the board
 CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
@@ -45,7 +45,7 @@ LDFLAGS += $(addprefix -L,$(LDINC)) \
 	-Wl,-lc
 
 # Additional Source files for FT90X.
-SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c 
+SRC_C += src/portable/bridgetek/ft9xx/dcd_ft9xx.c
 
 # Linker library.
 ifneq ($(FT9XX_PREBUILT_LIBS),1)
diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h
index 0eab34916..7b488096e 100644
--- a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h
+++ b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2023 Ha Thach (tinyusb.org) for Adafruit Industries
diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
index 45fc9e3aa..db3551ca7 100644
--- a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
+++ b/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
@@ -36,7 +36,7 @@ static unsigned int tx_produce;
 static volatile unsigned int tx_consume;
 
 void USART1_IRQHandler(void) __attribute__((naked));
-void USART1_IRQHandler(void) { 
+void USART1_IRQHandler(void) {
       __asm volatile ("call USART1_IRQHandler_impl; mret");
 }
 
@@ -57,7 +57,7 @@ __attribute__((used)) void USART1_IRQHandler_impl(void)
 void uart_write(char c)
 {
 	unsigned int tx_produce_next = (tx_produce + 1) & UART_RINGBUFFER_MASK_TX;
-	
+
     NVIC_DisableIRQ(USART1_IRQn);
     if((tx_consume != tx_produce) || (USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)) {
 		tx_buf[tx_produce] = c;
diff --git a/hw/bsp/ch32v307/ch32v307.ld b/hw/bsp/ch32v307/ch32v307.ld
index af7c06615..55bd10cd0 100644
--- a/hw/bsp/ch32v307/ch32v307.ld
+++ b/hw/bsp/ch32v307/ch32v307.ld
@@ -41,7 +41,7 @@ SECTIONS
 		*(.glue_7t)
 		*(.gnu.linkonce.t.*)
 		. = ALIGN(4);
-	} >FLASH AT>FLASH 
+	} >FLASH AT>FLASH
 
 	.fini :
 	{
@@ -50,31 +50,31 @@ SECTIONS
 	} >FLASH AT>FLASH
 
 	PROVIDE( _etext = . );
-	PROVIDE( _eitcm = . );	
+	PROVIDE( _eitcm = . );
 
 	.preinit_array  :
 	{
 	  PROVIDE_HIDDEN (__preinit_array_start = .);
 	  KEEP (*(.preinit_array))
 	  PROVIDE_HIDDEN (__preinit_array_end = .);
-	} >FLASH AT>FLASH 
-	
+	} >FLASH AT>FLASH
+
 	.init_array     :
 	{
 	  PROVIDE_HIDDEN (__init_array_start = .);
 	  KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
 	  KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
 	  PROVIDE_HIDDEN (__init_array_end = .);
-	} >FLASH AT>FLASH 
-	
+	} >FLASH AT>FLASH
+
 	.fini_array     :
 	{
 	  PROVIDE_HIDDEN (__fini_array_start = .);
 	  KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
 	  KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
 	  PROVIDE_HIDDEN (__fini_array_end = .);
-	} >FLASH AT>FLASH 
-	
+	} >FLASH AT>FLASH
+
 	.ctors          :
 	{
 	  /* gcc uses crtbegin.o to find the start of
@@ -95,8 +95,8 @@ SECTIONS
 	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
 	  KEEP (*(SORT(.ctors.*)))
 	  KEEP (*(.ctors))
-	} >FLASH AT>FLASH 
-	
+	} >FLASH AT>FLASH
+
 	.dtors          :
 	{
 	  KEEP (*crtbegin.o(.dtors))
@@ -104,17 +104,17 @@ SECTIONS
 	  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
 	  KEEP (*(SORT(.dtors.*)))
 	  KEEP (*(.dtors))
-	} >FLASH AT>FLASH 
+	} >FLASH AT>FLASH
 
 	.dalign :
 	{
 		. = ALIGN(4);
 		PROVIDE(_data_vma = .);
-	} >RAM AT>FLASH	
+	} >RAM AT>FLASH
 
 	.dlalign :
 	{
-		. = ALIGN(4); 
+		. = ALIGN(4);
 		PROVIDE(_data_lma = .);
 	} >FLASH AT>FLASH
 
@@ -145,7 +145,7 @@ SECTIONS
   	    *(.sbss*)
         *(.gnu.linkonce.sb.*)
 		*(.bss*)
-     	*(.gnu.linkonce.b.*)		
+     	*(.gnu.linkonce.b.*)
 		*(COMMON*)
 		. = ALIGN(4);
 		PROVIDE( _ebss = .);
@@ -156,15 +156,12 @@ SECTIONS
 
     .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
     {
-        PROVIDE( _heap_end = . );    
+        PROVIDE( _heap_end = . );
         . = ALIGN(4);
         PROVIDE(_susrstack = . );
         . = . + __stack_size;
         PROVIDE( _eusrstack = .);
         __freertos_irq_stack_top = .;
-    } >RAM 
+    } >RAM
 
 }
-
-
-
diff --git a/hw/bsp/ch32v307/ch32v30x_conf.h b/hw/bsp/ch32v307/ch32v30x_conf.h
index 399feaf68..0b86ad390 100644
--- a/hw/bsp/ch32v307/ch32v30x_conf.h
+++ b/hw/bsp/ch32v307/ch32v30x_conf.h
@@ -6,7 +6,7 @@
 * Description        : Library configuration file.
 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
 * SPDX-License-Identifier: Apache-2.0
-*******************************************************************************/ 
+*******************************************************************************/
 #ifndef __CH32V30x_CONF_H
 #define __CH32V30x_CONF_H
 
@@ -36,8 +36,3 @@
 
 
 #endif /* __CH32V30x_CONF_H */
-
-
-	
-	
-	
diff --git a/hw/bsp/ch32v307/ch32v30x_it.c b/hw/bsp/ch32v307/ch32v30x_it.c
index d348dd989..c329c5613 100644
--- a/hw/bsp/ch32v307/ch32v30x_it.c
+++ b/hw/bsp/ch32v307/ch32v30x_it.c
@@ -45,5 +45,3 @@ __attribute__((used)) void HardFault_Handler_impl(void)
   {
   }
 }
-
-
diff --git a/hw/bsp/ch32v307/ch32v30x_it.h b/hw/bsp/ch32v307/ch32v30x_it.h
index 42f285edf..f3977a8be 100644
--- a/hw/bsp/ch32v307/ch32v30x_it.h
+++ b/hw/bsp/ch32v307/ch32v30x_it.h
@@ -14,5 +14,3 @@
 
 
 #endif /* __CH32V30x_IT_H */
-
-
diff --git a/hw/bsp/ch32v307/core_riscv.h b/hw/bsp/ch32v307/core_riscv.h
index 2e94ec683..a7ce10a00 100644
--- a/hw/bsp/ch32v307/core_riscv.h
+++ b/hw/bsp/ch32v307/core_riscv.h
@@ -336,7 +336,7 @@ RV_STATIC_INLINE void NVIC_SystemReset(void)
 }
 
 
-/* Core_Exported_Functions */  
+/* Core_Exported_Functions */
 extern uint32_t __get_FFLAGS(void);
 extern void __set_FFLAGS(uint32_t value);
 extern uint32_t __get_FRM(void);
@@ -377,8 +377,3 @@ extern uint32_t __get_SP(void);
 
 
 #endif
-
-
-
-
-
diff --git a/hw/bsp/ch32v307/system_ch32v30x.c b/hw/bsp/ch32v307/system_ch32v30x.c
index 12b18d7b8..23f783df4 100644
--- a/hw/bsp/ch32v307/system_ch32v30x.c
+++ b/hw/bsp/ch32v307/system_ch32v30x.c
@@ -8,17 +8,17 @@
 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
 * SPDX-License-Identifier: Apache-2.0
 *********************************************************************************/
-#include "ch32v30x.h" 
+#include "ch32v30x.h"
 
-/* 
-* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+/*
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
 * reset the HSI is used as SYSCLK source).
-* If none of the define below is enabled, the HSI is used as System clock source. 
+* If none of the define below is enabled, the HSI is used as System clock source.
 */
 // #define SYSCLK_FREQ_HSE    HSE_VALUE
-/* #define SYSCLK_FREQ_24MHz  24000000  */ 
+/* #define SYSCLK_FREQ_24MHz  24000000  */
 //#define SYSCLK_FREQ_48MHz  48000000
-/* #define SYSCLK_FREQ_56MHz  56000000  */  
+/* #define SYSCLK_FREQ_56MHz  56000000  */
 //#define SYSCLK_FREQ_72MHz  72000000
 //#define SYSCLK_FREQ_96MHz  96000000
 //#define SYSCLK_FREQ_120MHz  120000000
@@ -60,7 +60,7 @@ static void SetSysClock(void);
 #elif defined SYSCLK_FREQ_48MHz
   static void SetSysClockTo48(void);
 #elif defined SYSCLK_FREQ_56MHz
-  static void SetSysClockTo56(void);  
+  static void SetSysClockTo56(void);
 #elif defined SYSCLK_FREQ_72MHz
   static void SetSysClockTo72(void);
 
@@ -90,7 +90,7 @@ void SystemInit (void)
   RCC->CFGR0 &= (uint32_t)0xF8FF0000;
 #else
   RCC->CFGR0 &= (uint32_t)0xF0FF0000;
-#endif 
+#endif
 
   RCC->CTLR &= (uint32_t)0xFEF6FFFF;
   RCC->CTLR &= (uint32_t)0xFFFBFFFF;
@@ -101,8 +101,8 @@ void SystemInit (void)
   RCC->INTR = 0x00FF0000;
   RCC->CFGR2 = 0x00000000;
 #else
-  RCC->INTR = 0x009F0000;   
-#endif   
+  RCC->INTR = 0x009F0000;
+#endif
   SetSysClock();
 }
 
@@ -118,18 +118,18 @@ void SystemCoreClockUpdate (void)
   uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
 
   tmp = RCC->CFGR0 & RCC_SWS;
-  
+
   switch (tmp)
   {
     case 0x00:
       SystemCoreClock = HSI_VALUE;
       break;
-    case 0x04:  
+    case 0x04:
       SystemCoreClock = HSE_VALUE;
       break;
-    case 0x08: 
+    case 0x08:
       pllmull = RCC->CFGR0 & RCC_PLLMULL;
-      pllsource = RCC->CFGR0 & RCC_PLLSRC; 
+      pllsource = RCC->CFGR0 & RCC_PLLSRC;
       pllmull = ( pllmull >> 18) + 2;
 
 #ifdef CH32V30x_D8
@@ -149,7 +149,7 @@ void SystemCoreClockUpdate (void)
         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
       }
       else
-      {    
+      {
         if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
         {
           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
@@ -167,9 +167,9 @@ void SystemCoreClockUpdate (void)
       SystemCoreClock = HSI_VALUE;
       break;
   }
- 
+
   tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
-  SystemCoreClock >>= tmp;  
+  SystemCoreClock >>= tmp;
 }
 
 /*********************************************************************
@@ -188,7 +188,7 @@ static void SetSysClock(void)
 #elif defined SYSCLK_FREQ_48MHz
   SetSysClockTo48();
 #elif defined SYSCLK_FREQ_56MHz
-  SetSysClockTo56();  
+  SetSysClockTo56();
 #elif defined SYSCLK_FREQ_72MHz
   SetSysClockTo72();
 #elif defined SYSCLK_FREQ_96MHz
@@ -199,9 +199,9 @@ static void SetSysClock(void)
   SetSysClockTo144();
 
 #endif
- 
+
  /* If none of the define above is enabled, the HSI is used as System clock
-  * source (default after reset) 
+  * source (default after reset)
     */
 }
 
@@ -218,14 +218,14 @@ static void SetSysClock(void)
 static void SetSysClockToHSE(void)
 {
   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-   
+
   RCC->CTLR |= ((uint32_t)RCC_HSEON);
- 
+
   /* Wait till HSE is ready and if Time out is reached exit */
   do
   {
     HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;  
+    StartUpCounter++;
   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 
   if ((RCC->CTLR & RCC_HSERDY) != RESET)
@@ -235,20 +235,20 @@ static void SetSysClockToHSE(void)
   else
   {
     HSEStatus = (uint32_t)0x00;
-  }  
+  }
 
   if (HSEStatus == (uint32_t)0x01)
   {
     /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
     /* PCLK2 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
-    
+
     /* Select HSE as system clock source */
     RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
 
     /* Wait till HSE is used as system clock source */
     while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
@@ -256,11 +256,11 @@ static void SetSysClockToHSE(void)
     }
   }
   else
-  { 
+  {
         /* If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error 
+     * configuration. User can add here some code to deal with this error
          */
-  }  
+  }
 }
 
 #elif defined SYSCLK_FREQ_24MHz
@@ -275,14 +275,14 @@ static void SetSysClockToHSE(void)
 static void SetSysClockTo24(void)
 {
   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-     
+
   RCC->CTLR |= ((uint32_t)RCC_HSEON);
- 
+
   /* Wait till HSE is ready and if Time out is reached exit */
   do
   {
     HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;  
+    StartUpCounter++;
   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 
   if ((RCC->CTLR & RCC_HSERDY) != RESET)
@@ -292,13 +292,13 @@ static void SetSysClockTo24(void)
   else
   {
     HSEStatus = (uint32_t)0x00;
-  }  
+  }
   if (HSEStatus == (uint32_t)0x01)
   {
     /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
     /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
 
@@ -318,18 +318,18 @@ static void SetSysClockTo24(void)
     }
     /* Select PLL as system clock source */
     RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
     /* Wait till PLL is used as system clock source */
     while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
     {
     }
   }
   else
-  { 
+  {
         /* If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error 
+     * configuration. User can add here some code to deal with this error
          */
-  } 
+  }
 }
 
 #elif defined SYSCLK_FREQ_48MHz
@@ -344,14 +344,14 @@ static void SetSysClockTo24(void)
 static void SetSysClockTo48(void)
 {
   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-     
-   
+
+
   RCC->CTLR |= ((uint32_t)RCC_HSEON);
   /* Wait till HSE is ready and if Time out is reached exit */
   do
   {
     HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;  
+    StartUpCounter++;
   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 
   if ((RCC->CTLR & RCC_HSERDY) != RESET)
@@ -361,14 +361,14 @@ static void SetSysClockTo48(void)
   else
   {
     HSEStatus = (uint32_t)0x00;
-  }  
+  }
 
   if (HSEStatus == (uint32_t)0x01)
   {
     /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
     /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
 
@@ -389,19 +389,19 @@ static void SetSysClockTo48(void)
     }
     /* Select PLL as system clock source */
     RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
     /* Wait till PLL is used as system clock source */
     while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
     {
     }
   }
   else
-  { 
+  {
         /*
          * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error 
+     * configuration. User can add here some code to deal with this error
          */
-  } 
+  }
 }
 
 #elif defined SYSCLK_FREQ_56MHz
@@ -416,14 +416,14 @@ static void SetSysClockTo48(void)
 static void SetSysClockTo56(void)
 {
   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-     
+
   RCC->CTLR |= ((uint32_t)RCC_HSEON);
 
   /* Wait till HSE is ready and if Time out is reached exit */
   do
   {
     HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;  
+    StartUpCounter++;
   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 
   if ((RCC->CTLR & RCC_HSERDY) != RESET)
@@ -433,17 +433,17 @@ static void SetSysClockTo56(void)
   else
   {
     HSEStatus = (uint32_t)0x00;
-  }  
+  }
 
   if (HSEStatus == (uint32_t)0x01)
   {
     /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
     /* PCLK2 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
-  
+
     /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
     RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
 
@@ -462,19 +462,19 @@ static void SetSysClockTo56(void)
 
     /* Select PLL as system clock source */
     RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
     /* Wait till PLL is used as system clock source */
     while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
     {
     }
   }
   else
-  { 
+  {
         /*
          * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error 
+     * configuration. User can add here some code to deal with this error
          */
-  } 
+  }
 }
 
 #elif defined SYSCLK_FREQ_72MHz
@@ -489,14 +489,14 @@ static void SetSysClockTo56(void)
 static void SetSysClockTo72(void)
 {
   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-     
+
   RCC->CTLR |= ((uint32_t)RCC_HSEON);
- 
+
   /* Wait till HSE is ready and if Time out is reached exit */
   do
   {
     HSEStatus = RCC->CTLR & RCC_HSERDY;
-    StartUpCounter++;  
+    StartUpCounter++;
   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 
   if ((RCC->CTLR & RCC_HSERDY) != RESET)
@@ -506,17 +506,17 @@ static void SetSysClockTo72(void)
   else
   {
     HSEStatus = (uint32_t)0x00;
-  }  
+  }
 
   if (HSEStatus == (uint32_t)0x01)
   {
     /* HCLK = SYSCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
     /* PCLK2 = HCLK */
-    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
     /* PCLK1 = HCLK */
     RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
- 
+
     /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
     RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
                                         RCC_PLLMULL));
@@ -532,20 +532,20 @@ static void SetSysClockTo72(void)
     /* Wait till PLL is ready */
     while((RCC->CTLR & RCC_PLLRDY) == 0)
     {
-    }    
+    }
     /* Select PLL as system clock source */
     RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
-    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
     /* Wait till PLL is used as system clock source */
     while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
     {
     }
   }
   else
-  { 
+  {
         /*
          * If HSE fails to start-up, the application will have wrong clock
-     * configuration. User can add here some code to deal with this error 
+     * configuration. User can add here some code to deal with this error
          */
   }
 }
diff --git a/hw/bsp/ch32v307/system_ch32v30x.h b/hw/bsp/ch32v307/system_ch32v30x.h
index 0e0ef4e51..ad81058c7 100644
--- a/hw/bsp/ch32v307/system_ch32v30x.h
+++ b/hw/bsp/ch32v307/system_ch32v30x.h
@@ -7,16 +7,16 @@
 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
 * SPDX-License-Identifier: Apache-2.0
 *******************************************************************************/
-#ifndef __SYSTEM_CH32V30x_H 
+#ifndef __SYSTEM_CH32V30x_H
 #define __SYSTEM_CH32V30x_H
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
 
-/* System_Exported_Functions */  
+/* System_Exported_Functions */
 extern void SystemInit(void);
 extern void SystemCoreClockUpdate(void);
 
@@ -25,6 +25,3 @@ extern void SystemCoreClockUpdate(void);
 #endif
 
 #endif /*__CH32V30x_SYSTEM_H */
-
-
-
diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
index a4d996810..3abb488f2 100644
--- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenberg
diff --git a/hw/bsp/da14695_dk_usb/da1469x.ld b/hw/bsp/da14695_dk_usb/da1469x.ld
index 96507d6e7..8cc1d9d99 100644
--- a/hw/bsp/da14695_dk_usb/da1469x.ld
+++ b/hw/bsp/da14695_dk_usb/da1469x.ld
@@ -242,4 +242,3 @@ SECTIONS
     /* Check that intvect is at the beginning of RAM */
     ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
 }
-
diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
index 13113fb95..abe7f54cb 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
+++ b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenberg
diff --git a/hw/bsp/da1469x_dk_pro/da1469x.ld b/hw/bsp/da1469x_dk_pro/da1469x.ld
index 96507d6e7..8cc1d9d99 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x.ld
+++ b/hw/bsp/da1469x_dk_pro/da1469x.ld
@@ -242,4 +242,3 @@ SECTIONS
     /* Check that intvect is at the beginning of RAM */
     ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
 }
-
diff --git a/hw/bsp/ea4088qs/ea4088qs.c b/hw/bsp/ea4088qs/ea4088qs.c
index 7150ed393..ace72fef0 100644
--- a/hw/bsp/ea4088qs/ea4088qs.c
+++ b/hw/bsp/ea4088qs/ea4088qs.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/ea4088qs/lpc4088.ld b/hw/bsp/ea4088qs/lpc4088.ld
index 4b1cddd6e..5897707f6 100644
--- a/hw/bsp/ea4088qs/lpc4088.ld
+++ b/hw/bsp/ea4088qs/lpc4088.ld
@@ -11,24 +11,24 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  RamLoc64 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */  
-  RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */  
+  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  RamLoc64 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */
+  RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash512 = 0x0  ; /* MFlash512 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc64 = 0x10000000  ; /* RamLoc64 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc64 = 0x10000000 + 0x10000 ; /* 64K bytes */  
-  __top_RAM = 0x10000000 + 0x10000 ; /* 64K bytes */  
-  __base_RamPeriph32 = 0x20000000  ; /* RamPeriph32 */  
-  __base_RAM2 = 0x20000000 ; /* RAM2 */  
-  __top_RamPeriph32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM2 = 0x20000000 + 0x8000 ; /* 32K bytes */  
+  __base_MFlash512 = 0x0  ; /* MFlash512 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc64 = 0x10000000  ; /* RamLoc64 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc64 = 0x10000000 + 0x10000 ; /* 64K bytes */
+  __top_RAM = 0x10000000 + 0x10000 ; /* 64K bytes */
+  __base_RamPeriph32 = 0x20000000  ; /* RamPeriph32 */
+  __base_RAM2 = 0x20000000 ; /* RAM2 */
+  __top_RamPeriph32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM2 = 0x20000000 + 0x8000 ; /* 32K bytes */
 
 ENTRY(ResetISR)
 
@@ -72,9 +72,9 @@ SECTIONS
     } > MFlash512
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash512
@@ -88,7 +88,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamPeriph32 */
 
     .data_RAM2 : ALIGN(4)
@@ -130,7 +130,7 @@ SECTIONS
        *(.bss.$RamPeriph32*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamPeriph32 
+    } > RamPeriph32
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -149,13 +149,13 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamPeriph32*)
        . = ALIGN(4) ;
-    } > RamPeriph32 
+    } > RamPeriph32
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc64
@@ -163,11 +163,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc64 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -181,4 +181,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/ea4357/ea4357.c b/hw/bsp/ea4357/ea4357.c
index f88d3b89e..68bcaa123 100644
--- a/hw/bsp/ea4357/ea4357.c
+++ b/hw/bsp/ea4357/ea4357.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/ea4357/lpc4357.ld b/hw/bsp/ea4357/lpc4357.ld
index 14a0df328..e3dfbfda1 100644
--- a/hw/bsp/ea4357/lpc4357.ld
+++ b/hw/bsp/ea4357/lpc4357.ld
@@ -11,44 +11,44 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
+  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */  
-  __base_Flash = 0x1a000000 ; /* Flash */  
-  __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-  __base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */  
-  __base_Flash2 = 0x1b000000 ; /* Flash2 */  
-  __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-  __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamLoc40 = 0x10080000  ; /* RamLoc40 */  
-  __base_RAM2 = 0x10080000 ; /* RAM2 */  
-  __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-  __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-  __base_RAM3 = 0x20000000 ; /* RAM3 */  
-  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-  __base_RAM4 = 0x20008000 ; /* RAM4 */  
-  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-  __base_RAM5 = 0x2000c000 ; /* RAM5 */  
-  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
+  __base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */
+  __base_Flash = 0x1a000000 ; /* Flash */
+  __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+  __base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */
+  __base_Flash2 = 0x1b000000 ; /* Flash2 */
+  __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+  __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_RamLoc40 = 0x10080000  ; /* RamLoc40 */
+  __base_RAM2 = 0x10080000 ; /* RAM2 */
+  __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+  __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
+  __base_RAM3 = 0x20000000 ; /* RAM3 */
+  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
+  __base_RAM4 = 0x20008000 ; /* RAM4 */
+  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
+  __base_RAM5 = 0x2000c000 ; /* RAM5 */
+  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
 
 
 ENTRY(ResetISR)
@@ -119,9 +119,9 @@ SECTIONS
     } > MFlashA512
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlashA512
@@ -135,7 +135,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamLoc40 */
 
     .data_RAM2 : ALIGN(4)
@@ -216,7 +216,7 @@ SECTIONS
        *(.bss.$RamLoc40*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamLoc40 
+    } > RamLoc40
 
     /* BSS section for RamAHB32 */
     .bss_RAM3 : ALIGN(4)
@@ -226,7 +226,7 @@ SECTIONS
        *(.bss.$RamAHB32*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* BSS section for RamAHB16 */
     .bss_RAM4 : ALIGN(4)
@@ -236,7 +236,7 @@ SECTIONS
        *(.bss.$RamAHB16*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM4 = .) ;
-    } > RamAHB16 
+    } > RamAHB16
 
     /* BSS section for RamAHB_ETB16 */
     .bss_RAM5 : ALIGN(4)
@@ -246,7 +246,7 @@ SECTIONS
        *(.bss.$RamAHB_ETB16*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM5 = .) ;
-    } > RamAHB_ETB16 
+    } > RamAHB_ETB16
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -265,7 +265,7 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamLoc40*)
        . = ALIGN(4) ;
-    } > RamLoc40 
+    } > RamLoc40
 
     /* NOINIT section for RamAHB32 */
     .noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -273,7 +273,7 @@ SECTIONS
        *(.noinit.$RAM3*)
        *(.noinit.$RamAHB32*)
        . = ALIGN(4) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* NOINIT section for RamAHB16 */
     .noinit_RAM4 (NOLOAD) : ALIGN(4)
@@ -281,7 +281,7 @@ SECTIONS
        *(.noinit.$RAM4*)
        *(.noinit.$RamAHB16*)
        . = ALIGN(4) ;
-    } > RamAHB16 
+    } > RamAHB16
 
     /* NOINIT section for RamAHB_ETB16 */
     .noinit_RAM5 (NOLOAD) : ALIGN(4)
@@ -289,13 +289,13 @@ SECTIONS
        *(.noinit.$RAM5*)
        *(.noinit.$RamAHB_ETB16*)
        . = ALIGN(4) ;
-    } > RamAHB_ETB16 
+    } > RamAHB_ETB16
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc32
@@ -303,11 +303,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -321,4 +321,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/ea4357/pca9532.c b/hw/bsp/ea4357/pca9532.c
index eae3805c2..150167cde 100644
--- a/hw/bsp/ea4357/pca9532.c
+++ b/hw/bsp/ea4357/pca9532.c
@@ -57,7 +57,7 @@ static uint16_t ledStateShadow = 0;
  * Local Functions
  *****************************************************************************/
 
-static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len) 
+static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
 {
 	I2CM_XFER_T i2cData;
 
@@ -75,7 +75,7 @@ static Status I2CWrite(uint32_t addr, uint8_t* buf, uint32_t len)
 	return SUCCESS;
 }
 
-static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len) 
+static Status I2CRead(uint32_t addr, uint8_t* buf, uint32_t len)
 {
 	I2CM_XFER_T i2cData;
 
@@ -181,7 +181,7 @@ uint16_t pca9532_getLedState (uint32_t shadow)
          * A blinking LED may be reported as on or off depending on
          * its state when reading the Input register.
          */
-        
+
         buf[0] = PCA9532_INPUT0;
         I2CWrite(PCA9532_I2C_ADDR, buf, 1);
 
diff --git a/hw/bsp/ea4357/pca9532.h b/hw/bsp/ea4357/pca9532.h
index 7a7c6e145..f21c1ff09 100644
--- a/hw/bsp/ea4357/pca9532.h
+++ b/hw/bsp/ea4357/pca9532.h
@@ -48,7 +48,7 @@
 #define KEY_MASK 0x000F
 
 /*
- * MMC Card Detect and MMC Write Protect are mapped to LED4 
+ * MMC Card Detect and MMC Write Protect are mapped to LED4
  * and LED5 on the PCA9532. Please note that WP is active low.
  */
 
diff --git a/hw/bsp/esp32s2/boards/CMakeLists.txt b/hw/bsp/esp32s2/boards/CMakeLists.txt
index c3c687a70..ff90acbde 100644
--- a/hw/bsp/esp32s2/boards/CMakeLists.txt
+++ b/hw/bsp/esp32s2/boards/CMakeLists.txt
@@ -8,5 +8,5 @@ include("${BOARD}/board.cmake")
 
 target_include_directories(${COMPONENT_TARGET} PUBLIC
   "${TOP}/hw"
-  "${TOP}/src"  
+  "${TOP}/src"
 )
diff --git a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
index d33962676..e39ceb887 100644
--- a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
+++ b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
@@ -14,4 +14,4 @@ set(IDF_TARGET "esp32s2" FORCE)
 target_compile_options(${COMPONENT_TARGET} PUBLIC
   "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
   "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
+)
diff --git a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h
index 43e00901d..1f8dc2cea 100644
--- a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h
+++ b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
index d33962676..e39ceb887 100644
--- a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
+++ b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
@@ -14,4 +14,4 @@ set(IDF_TARGET "esp32s2" FORCE)
 target_compile_options(${COMPONENT_TARGET} PUBLIC
   "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
   "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
+)
diff --git a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h
index 16e30b685..084a7aaf2 100644
--- a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h
+++ b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
index d5c17b9be..16b0e9cdd 100644
--- a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
+++ b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
@@ -14,4 +14,4 @@ set(IDF_TARGET "esp32s2" FORCE)
 target_compile_options(${COMPONENT_TARGET} PUBLIC
   "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
   "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
+)
diff --git a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h
index 49a2474bc..2ec80ef47 100644
--- a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h
+++ b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/esp32s2/boards/esp32s2.c b/hw/bsp/esp32s2/boards/esp32s2.c
index a7ca82deb..015d8305b 100644
--- a/hw/bsp/esp32s2/boards/esp32s2.c
+++ b/hw/bsp/esp32s2/boards/esp32s2.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -150,4 +150,3 @@ int board_uart_write(void const * buf, int len)
   (void) buf; (void) len;
   return 0;
 }
-
diff --git a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
index d5c17b9be..16b0e9cdd 100644
--- a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
+++ b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
@@ -14,4 +14,4 @@ set(IDF_TARGET "esp32s2" FORCE)
 target_compile_options(${COMPONENT_TARGET} PUBLIC
   "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
   "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
+)
diff --git a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h
index 6bb44f76d..0acb9c439 100644
--- a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h
+++ b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake b/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
index d5c17b9be..16b0e9cdd 100644
--- a/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
+++ b/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
@@ -14,4 +14,4 @@ set(IDF_TARGET "esp32s2" FORCE)
 target_compile_options(${COMPONENT_TARGET} PUBLIC
   "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
   "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
+)
diff --git a/hw/bsp/esp32s2/boards/espressif_saola_1/board.h b/hw/bsp/esp32s2/boards/espressif_saola_1/board.h
index f450b9a8b..e068efef9 100644
--- a/hw/bsp/esp32s2/boards/espressif_saola_1/board.h
+++ b/hw/bsp/esp32s2/boards/espressif_saola_1/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt b/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt
index 6d0fcbc86..8266c5a1c 100644
--- a/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt
+++ b/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt
@@ -5,4 +5,3 @@ idf_component_register(SRCS "${component_srcs}"
                        PRIV_INCLUDE_DIRS ""
                        PRIV_REQUIRES "driver"
                        REQUIRES "")
-
diff --git a/hw/bsp/esp32s2/family.cmake b/hw/bsp/esp32s2/family.cmake
index f3d41d041..0973adcac 100644
--- a/hw/bsp/esp32s2/family.cmake
+++ b/hw/bsp/esp32s2/family.cmake
@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 3.5)
 
 # Add example src and bsp directories
-set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2/boards" "${TOP}/hw/bsp/esp32s2/components")  
+set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2/boards" "${TOP}/hw/bsp/esp32s2/components")
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 set(SUPPORTED_TARGETS esp32s2)
 set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/esp32s2/family.mk
index b95098e15..fba0f038b 100644
--- a/hw/bsp/esp32s2/family.mk
+++ b/hw/bsp/esp32s2/family.mk
@@ -21,4 +21,3 @@ UF2_FAMILY_ID = 0xbfdd4eee
 $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
 	@echo CREATE $@
 	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
-
diff --git a/hw/bsp/esp32s3/boards/CMakeLists.txt b/hw/bsp/esp32s3/boards/CMakeLists.txt
index e1b921ae9..311c6e900 100644
--- a/hw/bsp/esp32s3/boards/CMakeLists.txt
+++ b/hw/bsp/esp32s3/boards/CMakeLists.txt
@@ -10,5 +10,5 @@ idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PAT
 target_include_directories(${COMPONENT_TARGET} PUBLIC
   "${FREERTOS_ORIG_INCLUDE_PATH}"
   "${TOP}/hw"
-  "${TOP}/src"  
+  "${TOP}/src"
 )
diff --git a/hw/bsp/esp32s3/boards/esp32s3.c b/hw/bsp/esp32s3/boards/esp32s3.c
index a7ca82deb..015d8305b 100644
--- a/hw/bsp/esp32s3/boards/esp32s3.c
+++ b/hw/bsp/esp32s3/boards/esp32s3.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -150,4 +150,3 @@ int board_uart_write(void const * buf, int len)
   (void) buf; (void) len;
   return 0;
 }
-
diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake b/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
index 8996ff9dc..2bff4f836 100644
--- a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
+++ b/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
@@ -4,4 +4,4 @@ target_include_directories(${COMPONENT_LIB} PRIVATE .)
 target_compile_options(${COMPONENT_TARGET} PUBLIC
   "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
   "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
+)
diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.h b/hw/bsp/esp32s3/boards/espressif_addax_1/board.h
index fff24ba44..d4690f732 100644
--- a/hw/bsp/esp32s3/boards/espressif_addax_1/board.h
+++ b/hw/bsp/esp32s3/boards/espressif_addax_1/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
index 8996ff9dc..2bff4f836 100644
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
+++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
@@ -4,4 +4,4 @@ target_include_directories(${COMPONENT_LIB} PRIVATE .)
 target_compile_options(${COMPONENT_TARGET} PUBLIC
   "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
   "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
+)
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h
index c7940c56e..fe33b5c43 100644
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h
+++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
index 8996ff9dc..2bff4f836 100644
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
+++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
@@ -4,4 +4,4 @@ target_include_directories(${COMPONENT_LIB} PRIVATE .)
 target_compile_options(${COMPONENT_TARGET} PUBLIC
   "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
   "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
\ No newline at end of file
+)
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h
index c7940c56e..fe33b5c43 100644
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h
+++ b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt b/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
index 6d0fcbc86..8266c5a1c 100644
--- a/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
+++ b/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
@@ -5,4 +5,3 @@ idf_component_register(SRCS "${component_srcs}"
                        PRIV_INCLUDE_DIRS ""
                        PRIV_REQUIRES "driver"
                        REQUIRES "")
-
diff --git a/hw/bsp/esp32s3/family.cmake b/hw/bsp/esp32s3/family.cmake
index 511dd58bb..0bcad035e 100644
--- a/hw/bsp/esp32s3/family.cmake
+++ b/hw/bsp/esp32s3/family.cmake
@@ -1,7 +1,7 @@
 cmake_minimum_required(VERSION 3.5)
 
 # Add example src and bsp directories
-set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s3/boards" "${TOP}/hw/bsp/esp32s3/components")  
+set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s3/boards" "${TOP}/hw/bsp/esp32s3/components")
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 set(SUPPORTED_TARGETS esp32s3)
 set(FAMILY_MCUS ESP32S3)
diff --git a/hw/bsp/esp32s3/family.mk b/hw/bsp/esp32s3/family.mk
index cf153ffc2..d82a1c969 100644
--- a/hw/bsp/esp32s3/family.mk
+++ b/hw/bsp/esp32s3/family.mk
@@ -23,4 +23,3 @@ UF2_FAMILY_ID = 0xc47e5767
 $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
 	@echo CREATE $@
 	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
-
diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md
index 4aa1e153b..f7a863c34 100644
--- a/hw/bsp/f1c100s/README.md
+++ b/hw/bsp/f1c100s/README.md
@@ -17,4 +17,4 @@ Flash: `make BOARD=f1c100s flash` will write the image to SPI flash, and then re
 
 ## TODO
 
-* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT` high speed MCU check in examples (maybe we should extract the logic?)
\ No newline at end of file
+* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT` high speed MCU check in examples (maybe we should extract the logic?)
diff --git a/hw/bsp/f1c100s/board.h b/hw/bsp/f1c100s/board.h
index 238ac796d..0ef9a1700 100644
--- a/hw/bsp/f1c100s/board.h
+++ b/hw/bsp/f1c100s/board.h
@@ -1 +1 @@
-// Nothing valuable here
\ No newline at end of file
+// Nothing valuable here
diff --git a/hw/bsp/f1c100s/board.mk b/hw/bsp/f1c100s/board.mk
index 5fe26a9ea..9062483b0 100644
--- a/hw/bsp/f1c100s/board.mk
+++ b/hw/bsp/f1c100s/board.mk
@@ -32,7 +32,7 @@ SRC_C += \
 	$(MCU_DIR)/machine/sys-spi-flash.c \
 	$(MCU_DIR)/machine/f1c100s-intc.c \
 	$(MCU_DIR)/lib/malloc.c \
-	$(MCU_DIR)/lib/printf.c 
+	$(MCU_DIR)/lib/printf.c
 
 SRC_S += \
   $(MCU_DIR)/machine/start.S \
@@ -47,6 +47,6 @@ INC += \
 flash: flash-xfel
 
 exec: $(BUILD)/$(PROJECT).bin
-	xfel ddr 
+	xfel ddr
 	xfel write 0x80000000 $<
-	xfel exec 0x80000000
\ No newline at end of file
+	xfel exec 0x80000000
diff --git a/hw/bsp/f1c100s/f1c100s.c b/hw/bsp/f1c100s/f1c100s.c
index d45072ecb..5dcae33f7 100644
--- a/hw/bsp/f1c100s/f1c100s.c
+++ b/hw/bsp/f1c100s/f1c100s.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -125,6 +125,6 @@ static void timer_init(void) {
   f1c100s_intc_set_isr(F1C100S_IRQ_TIMER0, timer_handler);
   f1c100s_intc_enable_irq(F1C100S_IRQ_TIMER0);
 }
-#else 
+#else
 static void timer_init(void) { }
 #endif
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 601cd54f5..08bb20bc3 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -139,4 +139,4 @@ if (NOT TARGET _family_support_marker)
 
     # save it in case of re-inclusion
     set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
-endif()
\ No newline at end of file
+endif()
diff --git a/hw/bsp/fomu/boards/fomu/board.mk b/hw/bsp/fomu/boards/fomu/board.mk
index 8ced11412..b5545c89a 100644
--- a/hw/bsp/fomu/boards/fomu/board.mk
+++ b/hw/bsp/fomu/boards/fomu/board.mk
@@ -1 +1 @@
-# place holder
\ No newline at end of file
+# place holder
diff --git a/hw/bsp/fomu/fomu.c b/hw/bsp/fomu/fomu.c
index 33c630303..e079e7c5b 100644
--- a/hw/bsp/fomu/fomu.c
+++ b/hw/bsp/fomu/fomu.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/fomu/include/hw/common.h b/hw/bsp/fomu/include/hw/common.h
index 6a97ca2e9..b902bc4f2 100644
--- a/hw/bsp/fomu/include/hw/common.h
+++ b/hw/bsp/fomu/include/hw/common.h
@@ -30,4 +30,4 @@ static inline uint32_t csr_readl(uint32_t addr)
 {
 	return *(volatile uint32_t *)addr;
 }
-#endif /* _HW_COMMON_H_ */
\ No newline at end of file
+#endif /* _HW_COMMON_H_ */
diff --git a/hw/bsp/fomu/include/irq.h b/hw/bsp/fomu/include/irq.h
index a82218907..dc96c228d 100644
--- a/hw/bsp/fomu/include/irq.h
+++ b/hw/bsp/fomu/include/irq.h
@@ -68,4 +68,4 @@ static inline unsigned int irq_pending(void)
 }
 #endif
 
-#endif /* __IRQ_H */
\ No newline at end of file
+#endif /* __IRQ_H */
diff --git a/hw/bsp/frdm_k32l2b/board.h b/hw/bsp/frdm_k32l2b/board.h
index 825367915..8d21fdcd4 100644
--- a/hw/bsp/frdm_k32l2b/board.h
+++ b/hw/bsp/frdm_k32l2b/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
index 924bb18e9..8d2b39500 100644
--- a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
+++ b/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -56,10 +56,10 @@ void board_init(void)
   gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
   GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
   const port_pin_config_t BUTTON_CFG = {
-    kPORT_PullUp, 
-    kPORT_FastSlewRate, 
-    kPORT_PassiveFilterDisable, 
-    kPORT_LowDriveStrength, 
+    kPORT_PullUp,
+    kPORT_FastSlewRate,
+    kPORT_PassiveFilterDisable,
+    kPORT_LowDriveStrength,
     kPORT_MuxAsGpio
   };
   PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
@@ -68,7 +68,7 @@ void board_init(void)
   PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2);
   /* PORTA2 (pin 24) is configured as LPUART0_TX */
   PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2);
-  
+
   SIM->SOPT5 = ((SIM->SOPT5 &
                /* Mask bits to zero which are setting */
                (~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/frdm_kl25z/frdm_kl25z.c
index 8d93fdbaa..46f85f6a5 100644
--- a/hw/bsp/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/frdm_kl25z/frdm_kl25z.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -103,7 +103,7 @@ void board_init(void)
   // Button
   CLOCK_EnableClock(BUTTON_PIN_CLOCK);
   port_pin_config_t button_port = {
-    .pullSelect = kPORT_PullUp, 
+    .pullSelect = kPORT_PullUp,
     .mux = BUTTON_PIN_FUNCTION,
   };
   PORT_SetPinConfig(BUTTON_PIN_PORT, BUTTON_PIN, &button_port);
diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c
index 60a326d27..113c4c304 100644
--- a/hw/bsp/gd32vf103/family.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -44,7 +44,7 @@ void USBFS_IRQHandler(void) { tud_int_handler(0); }
 
 // According to GD32VF103 user manual clock tree:
 // Systick clock = AHB clock / 4.
-#define TIMER_TICKS         ((SystemCoreClock / 4) / 1000) 
+#define TIMER_TICKS         ((SystemCoreClock / 4) / 1000)
 
 #define BUTTON_PORT         GPIOA
 #define BUTTON_PIN          GPIO_PIN_0
diff --git a/hw/bsp/gd32vf103/system_gd32vf103.c b/hw/bsp/gd32vf103/system_gd32vf103.c
index c2001a980..200852abf 100644
--- a/hw/bsp/gd32vf103/system_gd32vf103.c
+++ b/hw/bsp/gd32vf103/system_gd32vf103.c
@@ -95,7 +95,7 @@ void SystemInit(void)
     /* reset the RCC clock configuration to the default reset state */
     /* enable IRC8M */
     RCU_CTL |= RCU_CTL_IRC8MEN;
-    
+
     /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */
     RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |
                   RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL);
@@ -107,7 +107,7 @@ void SystemInit(void)
     RCU_CTL &= ~(RCU_CTL_HXTALBPS);
 
     /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */
-    
+
     RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF |
                   RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4);
     RCU_CFG1 = 0x00000000U;
@@ -141,12 +141,12 @@ void SystemCoreClockUpdate(void)
         case SEL_IRC8M:
             SystemCoreClock = IRC8M_VALUE;
             break;
-            
+
         /* HXTAL is selected as CK_SYS */
         case SEL_HXTAL:
             SystemCoreClock = HXTAL_VALUE;
             break;
-            
+
         /* PLL is selected as CK_SYS */
         case SEL_PLL:
             /* PLL clock source selection, HXTAL or IRC8M/2 */
@@ -313,7 +313,7 @@ static void system_clock_72m_hxtal(void)
     /* APB1 = AHB/2 */
     RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
 
-    /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ 
+    /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */
     RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
     RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18);
 
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.h b/hw/bsp/imxrt/boards/metro_m7_1011/board.h
index 7fa2f8541..3c172ebb9 100644
--- a/hw/bsp/imxrt/boards/metro_m7_1011/board.h
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld
index 30dd84373..960fc6891 100644
--- a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld
@@ -35,7 +35,7 @@ MEMORY
 {
   m_flash_config        (RX)  : ORIGIN = 0x60000400, LENGTH = 0x00000C00
   m_ivt                 (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
-  
+
   m_interrupts          (RX)  : ORIGIN = 0x6000C000, LENGTH = 0x00000400
   m_text                (RX)  : ORIGIN = 0x6000C400, LENGTH = (8*1024*1024 - 0xC400)
   m_qacode              (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00008000
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
index 4f21b52fa..926f45618 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
index 932ce7fd7..10d9fad07 100644
--- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
index 56ed5855b..284bb08e7 100644
--- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
index 152c9ab18..9100072e2 100644
--- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
index 0472f608c..beb69bf2b 100644
--- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
index 7fa37e33f..0f45f72e1 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
index 5f51e91a2..37ad94eef 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/teensy_40/board.h b/hw/bsp/imxrt/boards/teensy_40/board.h
index b3cc0a8c5..cac773442 100644
--- a/hw/bsp/imxrt/boards/teensy_40/board.h
+++ b/hw/bsp/imxrt/boards/teensy_40/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/teensy_40/board.mk b/hw/bsp/imxrt/boards/teensy_40/board.mk
index 0ad5ea5c0..45ca0fb6e 100644
--- a/hw/bsp/imxrt/boards/teensy_40/board.mk
+++ b/hw/bsp/imxrt/boards/teensy_40/board.mk
@@ -5,6 +5,6 @@ MCU_VARIANT = MIMXRT1062
 JLINK_DEVICE = MIMXRT1062xxx6A
 
 # flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
-# Make sure it is in your PATH 
+# Make sure it is in your PATH
 flash: $(BUILD)/$(PROJECT).hex
 	teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_41/board.h b/hw/bsp/imxrt/boards/teensy_41/board.h
index b0b4931c7..72c18f540 100644
--- a/hw/bsp/imxrt/boards/teensy_41/board.h
+++ b/hw/bsp/imxrt/boards/teensy_41/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/imxrt/boards/teensy_41/board.mk b/hw/bsp/imxrt/boards/teensy_41/board.mk
index 0ad5ea5c0..45ca0fb6e 100644
--- a/hw/bsp/imxrt/boards/teensy_41/board.mk
+++ b/hw/bsp/imxrt/boards/teensy_41/board.mk
@@ -5,6 +5,6 @@ MCU_VARIANT = MIMXRT1062
 JLINK_DEVICE = MIMXRT1062xxx6A
 
 # flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
-# Make sure it is in your PATH 
+# Make sure it is in your PATH
 flash: $(BUILD)/$(PROJECT).hex
 	teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index e28a6174a..5eb672c24 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
diff --git a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
index 5420ffc00..f478a99c7 100644
--- a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
+++ b/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
@@ -214,4 +214,3 @@ SECTIONS
 
   ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
 }
-
diff --git a/hw/bsp/kuiic/board.h b/hw/bsp/kuiic/board.h
index 78ad83a2e..1e2d4f18b 100644
--- a/hw/bsp/kuiic/board.h
+++ b/hw/bsp/kuiic/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/kuiic/kuiic.c b/hw/bsp/kuiic/kuiic.c
index 7aaa9e03c..97677d47a 100644
--- a/hw/bsp/kuiic/kuiic.c
+++ b/hw/bsp/kuiic/kuiic.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
@@ -96,10 +96,10 @@ void board_init(void)
   CLOCK_EnableClock(kCLOCK_PortD);
   CLOCK_EnableClock(kCLOCK_PortE);
 
-  
+
   gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 1 };
   GPIO_PinInit(GPIOA, 1U, &led_config);
-  PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio);  
+  PORT_SetPinMux(PORTA, 1U, kPORT_MuxAsGpio);
   led_config.outputLogic = 0;
   GPIO_PinInit(GPIOA, 2U, &led_config);
   PORT_SetPinMux(PORTA, 2U, kPORT_MuxAsGpio);
@@ -108,10 +108,10 @@ void board_init(void)
   gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
   GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
   const port_pin_config_t BUTTON_CFG = {
-    kPORT_PullUp, 
-    kPORT_FastSlewRate, 
-    kPORT_PassiveFilterDisable, 
-    kPORT_LowDriveStrength, 
+    kPORT_PullUp,
+    kPORT_FastSlewRate,
+    kPORT_PassiveFilterDisable,
+    kPORT_LowDriveStrength,
     kPORT_MuxAsGpio
   };
   PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
@@ -121,7 +121,7 @@ void board_init(void)
   PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3);
   /* PORTA2 (pin 24) is configured as LPUART0_TX */
   PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
-  
+
   SIM->SOPT5 = ((SIM->SOPT5 &
                /* Mask bits to zero which are setting */
                (~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK)))
diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld b/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
index 6dd12ade1..d8079717e 100644
--- a/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
+++ b/hw/bsp/lpc15/boards/lpcxpresso1549/lpc1549.ld
@@ -13,29 +13,29 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */  
-  Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */  
-  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */  
-  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */  
+  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */
+  Ram0_16 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x4000 /* 16K bytes (alias RAM) */
+  Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes (alias RAM2) */
+  Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes (alias RAM3) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash256 = 0x0  ; /* MFlash256 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */  
-  __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */  
-  __base_Ram0_16 = 0x2000000  ; /* Ram0_16 */  
-  __base_RAM = 0x2000000 ; /* RAM */  
-  __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */  
-  __base_Ram1_16 = 0x2004000  ; /* Ram1_16 */  
-  __base_RAM2 = 0x2004000 ; /* RAM2 */  
-  __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */  
-  __base_Ram2_4 = 0x2008000  ; /* Ram2_4 */  
-  __base_RAM3 = 0x2008000 ; /* RAM3 */  
-  __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */  
-  __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */  
+  __base_MFlash256 = 0x0  ; /* MFlash256 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */
+  __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */
+  __base_Ram0_16 = 0x2000000  ; /* Ram0_16 */
+  __base_RAM = 0x2000000 ; /* RAM */
+  __top_Ram0_16 = 0x2000000 + 0x4000 ; /* 16K bytes */
+  __top_RAM = 0x2000000 + 0x4000 ; /* 16K bytes */
+  __base_Ram1_16 = 0x2004000  ; /* Ram1_16 */
+  __base_RAM2 = 0x2004000 ; /* RAM2 */
+  __top_Ram1_16 = 0x2004000 + 0x4000 ; /* 16K bytes */
+  __top_RAM2 = 0x2004000 + 0x4000 ; /* 16K bytes */
+  __base_Ram2_4 = 0x2008000  ; /* Ram2_4 */
+  __base_RAM3 = 0x2008000 ; /* RAM3 */
+  __top_Ram2_4 = 0x2008000 + 0x1000 ; /* 4K bytes */
+  __top_RAM3 = 0x2008000 + 0x1000 ; /* 4K bytes */
 
 ENTRY(ResetISR)
 
@@ -84,9 +84,9 @@ SECTIONS
     } > MFlash256
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash256
@@ -98,9 +98,9 @@ SECTIONS
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
     } > MFlash256
     __exidx_end = .;
- 
+
     _etext = .;
-        
+
     /* DATA section for Ram1_16 */
 
     .data_RAM2 : ALIGN(4)
@@ -225,11 +225,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_16 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -243,4 +243,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c
index 7f5984a3e..30a3e51e1 100644
--- a/hw/bsp/lpc15/family.c
+++ b/hw/bsp/lpc15/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld b/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
index 51fd1539d..f12c1760c 100644
--- a/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/lpc1837.ld
@@ -12,43 +12,43 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
+  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
 }
 
 /* Define a symbol for the top of each memory region */
-__base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */  
-__base_Flash = 0x1a000000 ; /* Flash */  
-__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */  
-__base_Flash2 = 0x1b000000 ; /* Flash2 */  
-__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-__base_RAM = 0x10000000 ; /* RAM */  
-__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__base_RamLoc40 = 0x10080000  ; /* RamLoc40 */  
-__base_RAM2 = 0x10080000 ; /* RAM2 */  
-__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-__base_RAM3 = 0x20000000 ; /* RAM3 */  
-__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-__base_RAM4 = 0x20008000 ; /* RAM4 */  
-__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-__base_RAM5 = 0x2000c000 ; /* RAM5 */  
-__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
+__base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */
+__base_Flash = 0x1a000000 ; /* Flash */
+__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */
+__base_Flash2 = 0x1b000000 ; /* Flash2 */
+__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+__base_RAM = 0x10000000 ; /* RAM */
+__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+__base_RamLoc40 = 0x10080000  ; /* RamLoc40 */
+__base_RAM2 = 0x10080000 ; /* RAM2 */
+__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
+__base_RAM3 = 0x20000000 ; /* RAM3 */
+__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
+__base_RAM4 = 0x20008000 ; /* RAM4 */
+__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
+__base_RAM5 = 0x2000c000 ; /* RAM5 */
+__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
 __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
 
 ENTRY(ResetISR)
@@ -137,9 +137,9 @@ SECTIONS
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
         __exidx_end = .;
     } > MFlashA512
- 
+
     _etext = .;
-        
+
     /* DATA section for RamLoc40 */
 
     .data_RAM2 : ALIGN(4)
@@ -377,17 +377,17 @@ SECTIONS
          . = ALIGN(4) ;
         _end_noinit = .;
        PROVIDE(__end_noinit_RAM = .) ;
-       PROVIDE(__end_noinit_RamLoc32 = .) ;        
+       PROVIDE(__end_noinit_RamLoc32 = .) ;
     } > RamLoc32 AT> RamLoc32
     PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -401,4 +401,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
index 9a308e342..9a67e8946 100644
--- a/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
+++ b/hw/bsp/lpc18/boards/mcb1800/lpc1857.ld
@@ -11,44 +11,44 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
+  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
 }
 
 /* Define a symbol for the top of each memory region */
-__base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */  
-__base_Flash = 0x1a000000 ; /* Flash */  
-__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */  
-__base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */  
-__base_Flash2 = 0x1b000000 ; /* Flash2 */  
-__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */  
-__base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-__base_RAM = 0x10000000 ; /* RAM */  
-__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-__base_RamLoc40 = 0x10080000  ; /* RamLoc40 */  
-__base_RAM2 = 0x10080000 ; /* RAM2 */  
-__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */  
-__base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-__base_RAM3 = 0x20000000 ; /* RAM3 */  
-__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-__base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-__base_RAM4 = 0x20008000 ; /* RAM4 */  
-__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-__base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-__base_RAM5 = 0x2000c000 ; /* RAM5 */  
-__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
+__base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */
+__base_Flash = 0x1a000000 ; /* Flash */
+__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+__base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */
+__base_Flash2 = 0x1b000000 ; /* Flash2 */
+__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+__base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+__base_RAM = 0x10000000 ; /* RAM */
+__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+__base_RamLoc40 = 0x10080000  ; /* RamLoc40 */
+__base_RAM2 = 0x10080000 ; /* RAM2 */
+__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+__base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
+__base_RAM3 = 0x20000000 ; /* RAM3 */
+__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+__base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
+__base_RAM4 = 0x20008000 ; /* RAM4 */
+__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+__base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
+__base_RAM5 = 0x2000c000 ; /* RAM5 */
+__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
 
 ENTRY(ResetISR)
 
@@ -118,9 +118,9 @@ SECTIONS
     } > MFlashA512
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlashA512
@@ -134,7 +134,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamLoc40 */
 
     .data_RAM2 : ALIGN(4)
@@ -215,7 +215,7 @@ SECTIONS
        *(.bss.$RamLoc40*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamLoc40 
+    } > RamLoc40
 
     /* BSS section for RamAHB32 */
     .bss_RAM3 : ALIGN(4)
@@ -225,7 +225,7 @@ SECTIONS
        *(.bss.$RamAHB32*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* BSS section for RamAHB16 */
     .bss_RAM4 : ALIGN(4)
@@ -235,7 +235,7 @@ SECTIONS
        *(.bss.$RamAHB16*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM4 = .) ;
-    } > RamAHB16 
+    } > RamAHB16
 
     /* BSS section for RamAHB_ETB16 */
     .bss_RAM5 : ALIGN(4)
@@ -245,7 +245,7 @@ SECTIONS
        *(.bss.$RamAHB_ETB16*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM5 = .) ;
-    } > RamAHB_ETB16 
+    } > RamAHB_ETB16
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -264,7 +264,7 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamLoc40*)
        . = ALIGN(4) ;
-    } > RamLoc40 
+    } > RamLoc40
 
     /* NOINIT section for RamAHB32 */
     .noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -272,7 +272,7 @@ SECTIONS
        *(.noinit.$RAM3*)
        *(.noinit.$RamAHB32*)
        . = ALIGN(4) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* NOINIT section for RamAHB16 */
     .noinit_RAM4 (NOLOAD) : ALIGN(4)
@@ -280,7 +280,7 @@ SECTIONS
        *(.noinit.$RAM4*)
        *(.noinit.$RamAHB16*)
        . = ALIGN(4) ;
-    } > RamAHB16 
+    } > RamAHB16
 
     /* NOINIT section for RamAHB_ETB16 */
     .noinit_RAM5 (NOLOAD) : ALIGN(4)
@@ -288,13 +288,13 @@ SECTIONS
        *(.noinit.$RAM5*)
        *(.noinit.$RamAHB_ETB16*)
        . = ALIGN(4) ;
-    } > RamAHB_ETB16 
+    } > RamAHB_ETB16
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc32
@@ -302,11 +302,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -320,4 +320,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index 72c20e034..57f9d55da 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk b/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
index 925374cc8..5f15e2bbe 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
+++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
@@ -15,4 +15,4 @@ PYOCD_TARGET = LPC54628
 
 #flash: flash-pyocd
 
-flash: flash-jlink
\ No newline at end of file
+flash: flash-jlink
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index 621788948..fe9cfcc47 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
diff --git a/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld b/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld
index 6b5d852aa..e2197b972 100644
--- a/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld
+++ b/hw/bsp/lpc55/boards/double_m33_express/LPC55S69_cm33_core0_uf2.ld
@@ -231,4 +231,3 @@ SECTIONS
 
   ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
 }
-
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index 5b6c56dd3..3ed00e7da 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
diff --git a/hw/bsp/lpcxpresso11u37/lpc11u37.ld b/hw/bsp/lpcxpresso11u37/lpc11u37.ld
index 6a2dfb7f5..8e0a4e4c6 100644
--- a/hw/bsp/lpcxpresso11u37/lpc11u37.ld
+++ b/hw/bsp/lpcxpresso11u37/lpc11u37.ld
@@ -12,24 +12,24 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */  
-  RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */  
-  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */  
+  MFlash128 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias Flash) */
+  RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
+  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash128 = 0x0  ; /* MFlash128 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */  
-  __top_Flash = 0x0 + 0x20000 ; /* 128K bytes */  
-  __base_RamLoc8 = 0x10000000  ; /* RamLoc8 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __base_RamUsb2 = 0x20004000  ; /* RamUsb2 */  
-  __base_RAM2 = 0x20004000 ; /* RAM2 */  
-  __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */  
+  __base_MFlash128 = 0x0  ; /* MFlash128 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash128 = 0x0 + 0x20000 ; /* 128K bytes */
+  __top_Flash = 0x0 + 0x20000 ; /* 128K bytes */
+  __base_RamLoc8 = 0x10000000  ; /* RamLoc8 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
+  __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
+  __base_RamUsb2 = 0x20004000  ; /* RamUsb2 */
+  __base_RAM2 = 0x20004000 ; /* RAM2 */
+  __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
+  __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
 
 
 ENTRY(ResetISR)
@@ -74,9 +74,9 @@ SECTIONS
     } > MFlash128
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash128
@@ -88,9 +88,9 @@ SECTIONS
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
     } > MFlash128
     __exidx_end = .;
- 
+
     _etext = .;
-        
+
     /* DATA section for RamUsb2 */
 
     .data_RAM2 : ALIGN(4)
@@ -176,11 +176,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) 
-                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
+                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
                                          )
            );
 
@@ -192,4 +192,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c b/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
index 11f1797a2..79cd685c3 100644
--- a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
+++ b/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/lpcxpresso11u68/lpc11u68.ld b/hw/bsp/lpcxpresso11u68/lpc11u68.ld
index 56d9e4b89..4a35b192e 100644
--- a/hw/bsp/lpcxpresso11u68/lpc11u68.ld
+++ b/hw/bsp/lpcxpresso11u68/lpc11u68.ld
@@ -11,29 +11,29 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */  
-  Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */  
-  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */  
+  MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes (alias Flash) */
+  Ram0_32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
+  Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash256 = 0x0  ; /* MFlash256 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */  
-  __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */  
-  __base_Ram0_32 = 0x10000000  ; /* Ram0_32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_Ram0_32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_Ram1_2 = 0x20000000  ; /* Ram1_2 */  
-  __base_RAM2 = 0x20000000 ; /* RAM2 */  
-  __top_Ram1_2 = 0x20000000 + 0x800 ; /* 2K bytes */  
-  __top_RAM2 = 0x20000000 + 0x800 ; /* 2K bytes */  
-  __base_Ram2USB_2 = 0x20004000  ; /* Ram2USB_2 */  
-  __base_RAM3 = 0x20004000 ; /* RAM3 */  
-  __top_Ram2USB_2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __top_RAM3 = 0x20004000 + 0x800 ; /* 2K bytes */  
+  __base_MFlash256 = 0x0  ; /* MFlash256 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash256 = 0x0 + 0x40000 ; /* 256K bytes */
+  __top_Flash = 0x0 + 0x40000 ; /* 256K bytes */
+  __base_Ram0_32 = 0x10000000  ; /* Ram0_32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_Ram0_32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_Ram1_2 = 0x20000000  ; /* Ram1_2 */
+  __base_RAM2 = 0x20000000 ; /* RAM2 */
+  __top_Ram1_2 = 0x20000000 + 0x800 ; /* 2K bytes */
+  __top_RAM2 = 0x20000000 + 0x800 ; /* 2K bytes */
+  __base_Ram2USB_2 = 0x20004000  ; /* Ram2USB_2 */
+  __base_RAM3 = 0x20004000 ; /* RAM3 */
+  __top_Ram2USB_2 = 0x20004000 + 0x800 ; /* 2K bytes */
+  __top_RAM3 = 0x20004000 + 0x800 ; /* 2K bytes */
 
 ENTRY(ResetISR)
 
@@ -82,9 +82,9 @@ SECTIONS
     } > MFlash256
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash256
@@ -98,7 +98,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* possible MTB section for Ram1_2 */
     .mtb_buffer_RAM2 (NOLOAD) :
     {
@@ -172,7 +172,7 @@ SECTIONS
        *(.bss.$Ram1_2*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > Ram1_2 
+    } > Ram1_2
 
     /* BSS section for Ram2USB_2 */
     .bss_RAM3 : ALIGN(4)
@@ -182,7 +182,7 @@ SECTIONS
        *(.bss.$Ram2USB_2*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM3 = .) ;
-    } > Ram2USB_2 
+    } > Ram2USB_2
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -201,7 +201,7 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$Ram1_2*)
        . = ALIGN(4) ;
-    } > Ram1_2 
+    } > Ram1_2
 
     /* NOINIT section for Ram2USB_2 */
     .noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -209,13 +209,13 @@ SECTIONS
        *(.noinit.$RAM3*)
        *(.noinit.$Ram2USB_2*)
        . = ALIGN(4) ;
-    } > Ram2USB_2 
+    } > Ram2USB_2
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > Ram0_32
@@ -223,11 +223,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_Ram0_32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1) 
-                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
+                                         + (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
                                          )
            );
 
@@ -239,4 +239,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c b/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
index e33a5c6e5..a04e43867 100644
--- a/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
+++ b/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/lpcxpresso1347/lpc1347.ld b/hw/bsp/lpcxpresso1347/lpc1347.ld
index 42a4bb25c..a2111cd1c 100644
--- a/hw/bsp/lpcxpresso1347/lpc1347.ld
+++ b/hw/bsp/lpcxpresso1347/lpc1347.ld
@@ -11,29 +11,29 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes (alias Flash) */  
-  RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */  
-  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */  
-  RamPeriph2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */  
+  MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes (alias Flash) */
+  RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
+  RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
+  RamPeriph2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash64 = 0x0  ; /* MFlash64 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash64 = 0x0 + 0x10000 ; /* 64K bytes */  
-  __top_Flash = 0x0 + 0x10000 ; /* 64K bytes */  
-  __base_RamLoc8 = 0x10000000  ; /* RamLoc8 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */  
-  __base_RamUsb2 = 0x20004000  ; /* RamUsb2 */  
-  __base_RAM2 = 0x20004000 ; /* RAM2 */  
-  __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */  
-  __base_RamPeriph2 = 0x20000000  ; /* RamPeriph2 */  
-  __base_RAM3 = 0x20000000 ; /* RAM3 */  
-  __top_RamPeriph2 = 0x20000000 + 0x800 ; /* 2K bytes */  
-  __top_RAM3 = 0x20000000 + 0x800 ; /* 2K bytes */  
+  __base_MFlash64 = 0x0  ; /* MFlash64 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash64 = 0x0 + 0x10000 ; /* 64K bytes */
+  __top_Flash = 0x0 + 0x10000 ; /* 64K bytes */
+  __base_RamLoc8 = 0x10000000  ; /* RamLoc8 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
+  __top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
+  __base_RamUsb2 = 0x20004000  ; /* RamUsb2 */
+  __base_RAM2 = 0x20004000 ; /* RAM2 */
+  __top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
+  __top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
+  __base_RamPeriph2 = 0x20000000  ; /* RamPeriph2 */
+  __base_RAM3 = 0x20000000 ; /* RAM3 */
+  __top_RamPeriph2 = 0x20000000 + 0x800 ; /* 2K bytes */
+  __top_RAM3 = 0x20000000 + 0x800 ; /* 2K bytes */
 
 ENTRY(ResetISR)
 
@@ -82,9 +82,9 @@ SECTIONS
     } > MFlash64
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash64
@@ -98,7 +98,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamUsb2 */
 
     .data_RAM2 : ALIGN(4)
@@ -153,7 +153,7 @@ SECTIONS
        *(.bss.$RamUsb2*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamUsb2 
+    } > RamUsb2
 
     /* BSS section for RamPeriph2 */
     .bss_RAM3 : ALIGN(4)
@@ -163,7 +163,7 @@ SECTIONS
        *(.bss.$RamPeriph2*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM3 = .) ;
-    } > RamPeriph2 
+    } > RamPeriph2
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -182,7 +182,7 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamUsb2*)
        . = ALIGN(4) ;
-    } > RamUsb2 
+    } > RamUsb2
 
     /* NOINIT section for RamPeriph2 */
     .noinit_RAM3 (NOLOAD) : ALIGN(4)
@@ -190,13 +190,13 @@ SECTIONS
        *(.noinit.$RAM3*)
        *(.noinit.$RamPeriph2*)
        . = ALIGN(4) ;
-    } > RamPeriph2 
+    } > RamPeriph2
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc8
@@ -204,11 +204,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -222,4 +222,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpcxpresso1347/lpcxpresso1347.c b/hw/bsp/lpcxpresso1347/lpcxpresso1347.c
index a9a67ae3a..8ee611037 100644
--- a/hw/bsp/lpcxpresso1347/lpcxpresso1347.c
+++ b/hw/bsp/lpcxpresso1347/lpcxpresso1347.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -64,7 +64,7 @@ const uint32_t ExtRateIn = 0;
 
 /* Pin muxing table, only items that need changing from their default pin
    state are in this table. */
-static const PINMUX_GRP_T pinmuxing[] = 
+static const PINMUX_GRP_T pinmuxing[] =
 {
   {0,  1,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)},	/* PIO0_1 used for CLKOUT */
   {0,  2,  (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_PULLUP)},	/* PIO0_2 used for SSEL */
diff --git a/hw/bsp/lpcxpresso1769/lpc1769.ld b/hw/bsp/lpcxpresso1769/lpc1769.ld
index d1c83d8e2..095bd3d92 100644
--- a/hw/bsp/lpcxpresso1769/lpc1769.ld
+++ b/hw/bsp/lpcxpresso1769/lpc1769.ld
@@ -11,24 +11,24 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */  
+  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash512 = 0x0  ; /* MFlash512 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB32 = 0x2007c000  ; /* RamAHB32 */  
-  __base_RAM2 = 0x2007c000 ; /* RAM2 */  
-  __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
+  __base_MFlash512 = 0x0  ; /* MFlash512 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_RamAHB32 = 0x2007c000  ; /* RamAHB32 */
+  __base_RAM2 = 0x2007c000 ; /* RAM2 */
+  __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+  __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
 
 ENTRY(ResetISR)
 
@@ -72,9 +72,9 @@ SECTIONS
     } > MFlash512
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash512
@@ -88,7 +88,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamAHB32 */
 
     .data_RAM2 : ALIGN(4)
@@ -130,7 +130,7 @@ SECTIONS
        *(.bss.$RamAHB32*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -149,13 +149,13 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamAHB32*)
        . = ALIGN(4) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc32
@@ -163,11 +163,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -181,4 +181,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
index b7bce93d2..24333ad1a 100644
--- a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
+++ b/hw/bsp/lpcxpresso1769/lpcxpresso1769.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c b/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c
index 6bade7743..c94b0d6d8 100644
--- a/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c
+++ b/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
diff --git a/hw/bsp/mbed1768/lpc1768.ld b/hw/bsp/mbed1768/lpc1768.ld
index d1c83d8e2..095bd3d92 100644
--- a/hw/bsp/mbed1768/lpc1768.ld
+++ b/hw/bsp/mbed1768/lpc1768.ld
@@ -11,24 +11,24 @@
 MEMORY
 {
   /* Define each memory region */
-  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */  
-  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */  
-  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */  
+  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_MFlash512 = 0x0  ; /* MFlash512 */  
-  __base_Flash = 0x0 ; /* Flash */  
-  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */  
-  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */  
-  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB32 = 0x2007c000  ; /* RamAHB32 */  
-  __base_RAM2 = 0x2007c000 ; /* RAM2 */  
-  __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */  
+  __base_MFlash512 = 0x0  ; /* MFlash512 */
+  __base_Flash = 0x0 ; /* Flash */
+  __top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_RamAHB32 = 0x2007c000  ; /* RamAHB32 */
+  __base_RAM2 = 0x2007c000 ; /* RAM2 */
+  __top_RamAHB32 = 0x2007c000 + 0x8000 ; /* 32K bytes */
+  __top_RAM2 = 0x2007c000 + 0x8000 ; /* 32K bytes */
 
 ENTRY(ResetISR)
 
@@ -72,9 +72,9 @@ SECTIONS
     } > MFlash512
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > MFlash512
@@ -88,7 +88,7 @@ SECTIONS
     __exidx_end = .;
 
     _etext = .;
-        
+
     /* DATA section for RamAHB32 */
 
     .data_RAM2 : ALIGN(4)
@@ -130,7 +130,7 @@ SECTIONS
        *(.bss.$RamAHB32*)
        . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
        PROVIDE(__end_bss_RAM2 = .) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* MAIN BSS SECTION */
     .bss : ALIGN(4)
@@ -149,13 +149,13 @@ SECTIONS
        *(.noinit.$RAM2*)
        *(.noinit.$RamAHB32*)
        . = ALIGN(4) ;
-    } > RamAHB32 
+    } > RamAHB32
 
     /* DEFAULT NOINIT SECTION */
     .noinit (NOLOAD): ALIGN(4)
     {
         _noinit = .;
-        *(.noinit*) 
+        *(.noinit*)
          . = ALIGN(4) ;
         _end_noinit = .;
     } > RamLoc32
@@ -163,11 +163,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -181,4 +181,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/mbed1768/mbed1768.c b/hw/bsp/mbed1768/mbed1768.c
index 08cf3adbd..9f3d294d3 100644
--- a/hw/bsp/mbed1768/mbed1768.c
+++ b/hw/bsp/mbed1768/mbed1768.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
index 0b45ee7bd..796ed04f6 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/flash.ld
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 MM32 SE TEAM
@@ -110,7 +110,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -121,7 +121,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -149,7 +149,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
index 9793ba241..c3f5bc16d 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 MM32 SE TEAM
@@ -57,7 +57,7 @@ const int baudrate = 115200;
 
 void board_init (void)
 {
-//   usb clock	
+//   usb clock
   USB_DeviceClockInit();
 
   if ( SysTick_Config(SystemCoreClock / 1000) )
diff --git a/hw/bsp/ngx4330/ngx4330.c b/hw/bsp/ngx4330/ngx4330.c
index 4fc314165..d61f775c7 100644
--- a/hw/bsp/ngx4330/ngx4330.c
+++ b/hw/bsp/ngx4330/ngx4330.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/ngx4330/ngx4330.ld b/hw/bsp/ngx4330/ngx4330.ld
index 7bd363f08..300869c20 100644
--- a/hw/bsp/ngx4330/ngx4330.ld
+++ b/hw/bsp/ngx4330/ngx4330.ld
@@ -12,39 +12,39 @@
 MEMORY
 {
   /* Define each memory region */
-  RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */  
-  RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes (alias RAM2) */  
-  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */  
-  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */  
-  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */  
-  SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes (alias Flash) */  
+  RamLoc128 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */
+  RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes (alias RAM2) */
+  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
+  SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes (alias Flash) */
 }
 
   /* Define a symbol for the top of each memory region */
-  __base_RamLoc128 = 0x10000000  ; /* RamLoc128 */  
-  __base_RAM = 0x10000000 ; /* RAM */  
-  __top_RamLoc128 = 0x10000000 + 0x20000 ; /* 128K bytes */  
-  __top_RAM = 0x10000000 + 0x20000 ; /* 128K bytes */  
-  __base_RamLoc72 = 0x10080000  ; /* RamLoc72 */  
-  __base_RAM2 = 0x10080000 ; /* RAM2 */  
-  __top_RamLoc72 = 0x10080000 + 0x12000 ; /* 72K bytes */  
-  __top_RAM2 = 0x10080000 + 0x12000 ; /* 72K bytes */  
-  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */  
-  __base_RAM3 = 0x20000000 ; /* RAM3 */  
-  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */  
-  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */  
-  __base_RAM4 = 0x20008000 ; /* RAM4 */  
-  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */  
-  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */  
-  __base_RAM5 = 0x2000c000 ; /* RAM5 */  
-  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */  
-  __base_SPIFI = 0x14000000  ; /* SPIFI */  
-  __base_Flash = 0x14000000 ; /* Flash */  
-  __top_SPIFI = 0x14000000 + 0x400000 ; /* 4M bytes */  
-  __top_Flash = 0x14000000 + 0x400000 ; /* 4M bytes */  
+  __base_RamLoc128 = 0x10000000  ; /* RamLoc128 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc128 = 0x10000000 + 0x20000 ; /* 128K bytes */
+  __top_RAM = 0x10000000 + 0x20000 ; /* 128K bytes */
+  __base_RamLoc72 = 0x10080000  ; /* RamLoc72 */
+  __base_RAM2 = 0x10080000 ; /* RAM2 */
+  __top_RamLoc72 = 0x10080000 + 0x12000 ; /* 72K bytes */
+  __top_RAM2 = 0x10080000 + 0x12000 ; /* 72K bytes */
+  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
+  __base_RAM3 = 0x20000000 ; /* RAM3 */
+  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
+  __base_RAM4 = 0x20008000 ; /* RAM4 */
+  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
+  __base_RAM5 = 0x2000c000 ; /* RAM5 */
+  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+  __base_SPIFI = 0x14000000  ; /* SPIFI */
+  __base_Flash = 0x14000000 ; /* Flash */
+  __top_SPIFI = 0x14000000 + 0x400000 ; /* 4M bytes */
+  __top_Flash = 0x14000000 + 0x400000 ; /* 4M bytes */
 
 ENTRY(ResetISR)
 
@@ -103,9 +103,9 @@ SECTIONS
     } > SPIFI
     /*
      * for exception handling/unwind - some Newlib functions (in common
-     * with C++ and STDC++) use this. 
+     * with C++ and STDC++) use this.
      */
-    .ARM.extab : ALIGN(4) 
+    .ARM.extab : ALIGN(4)
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
     } > SPIFI
@@ -117,9 +117,9 @@ SECTIONS
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
     } > SPIFI
     __exidx_end = .;
- 
+
     _etext = .;
-        
+
     /* DATA section for RamLoc72 */
 
     .data_RAM2 : ALIGN(4)
@@ -322,11 +322,11 @@ SECTIONS
     PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc128 - 0);
 
     /* ## Create checksum value (used in startup) ## */
-    PROVIDE(__valid_user_code_checksum = 0 - 
-                                         (_vStackTop 
-                                         + (ResetISR + 1) 
-                                         + (NMI_Handler + 1) 
-                                         + (HardFault_Handler + 1) 
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
                                          + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
                                          + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
                                          + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
@@ -340,4 +340,4 @@ SECTIONS
     _image_start = LOADADDR(.text);
     _image_end = LOADADDR(.data) + SIZEOF(.data);
     _image_size = _image_end - _image_start;
-}
\ No newline at end of file
+}
diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.h b/hw/bsp/nrf/boards/adafruit_clue/board.h
index 2c58e8fe8..8d6df786e 100644
--- a/hw/bsp/nrf/boards/adafruit_clue/board.h
+++ b/hw/bsp/nrf/boards/adafruit_clue/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld
index 5314a4e93..71c55bb81 100755
--- a/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld
+++ b/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld
@@ -13,7 +13,7 @@ MEMORY
    * - Max ATT MTU
    * - Concurrent connection peripheral + central + secure links
    * - Event Len, HVN queue, Write CMD queue
-   */ 
+   */
   RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
 }
 
@@ -26,7 +26,7 @@ SECTIONS
     KEEP(*(.svc_data))
     PROVIDE(__stop_svc_data = .);
   } > RAM
-  
+
   .fs_data :
   {
     PROVIDE(__start_fs_data = .);
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld b/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
index f570740b6..f609f743f 100755
--- a/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
@@ -20,7 +20,7 @@ SECTIONS
     KEEP(*(.svc_data))
     PROVIDE(__stop_svc_data = .);
   } > RAM
-  
+
   .fs_data :
   {
     PROVIDE(__start_fs_data = .);
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
index d548e01c3..00fa8d8ea 100644
--- a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
index a86c9dc7f..3dd354efa 100644
--- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
index 5314a4e93..71c55bb81 100755
--- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
@@ -13,7 +13,7 @@ MEMORY
    * - Max ATT MTU
    * - Concurrent connection peripheral + central + secure links
    * - Event Len, HVN queue, Write CMD queue
-   */ 
+   */
   RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
 }
 
@@ -26,7 +26,7 @@ SECTIONS
     KEEP(*(.svc_data))
     PROVIDE(__stop_svc_data = .);
   } > RAM
-  
+
   .fs_data :
   {
     PROVIDE(__start_fs_data = .);
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index 3208a948a..8e6ce3230 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
index 5314a4e93..71c55bb81 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
@@ -13,7 +13,7 @@ MEMORY
    * - Max ATT MTU
    * - Concurrent connection peripheral + central + secure links
    * - Event Len, HVN queue, Write CMD queue
-   */ 
+   */
   RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
 }
 
@@ -26,7 +26,7 @@ SECTIONS
     KEEP(*(.svc_data))
     PROVIDE(__stop_svc_data = .);
   } > RAM
-  
+
   .fs_data :
   {
     PROVIDE(__start_fs_data = .);
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
index ece6e34cb..605deea24 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
index 5314a4e93..71c55bb81 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
@@ -13,7 +13,7 @@ MEMORY
    * - Max ATT MTU
    * - Concurrent connection peripheral + central + secure links
    * - Event Len, HVN queue, Write CMD queue
-   */ 
+   */
   RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
 }
 
@@ -26,7 +26,7 @@ SECTIONS
     KEEP(*(.svc_data))
     PROVIDE(__stop_svc_data = .);
   } > RAM
-  
+
   .fs_data :
   {
     PROVIDE(__start_fs_data = .);
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
index 132173a80..33c370f53 100644
--- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
index 5314a4e93..71c55bb81 100644
--- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
@@ -13,7 +13,7 @@ MEMORY
    * - Max ATT MTU
    * - Concurrent connection peripheral + central + secure links
    * - Event Len, HVN queue, Write CMD queue
-   */ 
+   */
   RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
 }
 
@@ -26,7 +26,7 @@ SECTIONS
     KEEP(*(.svc_data))
     PROVIDE(__stop_svc_data = .);
   } > RAM
-  
+
   .fs_data :
   {
     PROVIDE(__start_fs_data = .);
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
index 01dd1f24f..072cb2714 100644
--- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
+++ b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk
index 3afa234aa..f25ec8f34 100644
--- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk
+++ b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk
@@ -12,4 +12,4 @@ $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 
 flash: $(BUILD)/$(PROJECT).zip
 	@:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0)
-	$(NRFUTIL) dfu usb-serial --package $^ -p $(SERIAL) -b 115200
\ No newline at end of file
+	$(NRFUTIL) dfu usb-serial --package $^ -p $(SERIAL) -b 115200
diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h
index ab12d21aa..50d3067b3 100644
--- a/hw/bsp/nrf/boards/pca10056/board.h
+++ b/hw/bsp/nrf/boards/pca10056/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/pca10059/board.h b/hw/bsp/nrf/boards/pca10059/board.h
index 0810be648..ea3f4030d 100644
--- a/hw/bsp/nrf/boards/pca10059/board.h
+++ b/hw/bsp/nrf/boards/pca10059/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/pca10100/board.h b/hw/bsp/nrf/boards/pca10100/board.h
index 881133035..2b2579732 100644
--- a/hw/bsp/nrf/boards/pca10100/board.h
+++ b/hw/bsp/nrf/boards/pca10100/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
index dcf829d9c..bc203f073 100644
--- a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
+++ b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index a07332d4c..02cec31ef 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nutiny_nuc121s/nuc121_flash.ld b/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
index 3966b276e..0c599a561 100644
--- a/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
+++ b/hw/bsp/nutiny_nuc121s/nuc121_flash.ld
@@ -69,7 +69,7 @@ SECTIONS
  		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
  		*(SORT(.dtors.*))
  		*(.dtors)
-        
+
 		*(.rodata*)
 
 		KEEP(*(.eh_frame*))
diff --git a/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c b/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
index 7117a3422..ec66f8deb 100644
--- a/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
+++ b/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nutiny_nuc125s/nuc125_flash.ld b/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
index 3966b276e..0c599a561 100644
--- a/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
+++ b/hw/bsp/nutiny_nuc125s/nuc125_flash.ld
@@ -69,7 +69,7 @@ SECTIONS
  		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
  		*(SORT(.dtors.*))
  		*(.dtors)
-        
+
 		*(.rodata*)
 
 		KEEP(*(.eh_frame*))
diff --git a/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c b/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
index 7117a3422..ec66f8deb 100644
--- a/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
+++ b/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c b/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
index da62e7bd2..90fa2ffd8 100644
--- a/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
+++ b/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c b/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
index 0d78116b8..9e7eacb23 100644
--- a/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
+++ b/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c b/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
index 49e66d2d0..1fc97e3dc 100644
--- a/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
+++ b/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
index e47ec5f31..0bb6cb728 100644
--- a/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
+++ b/hw/bsp/pic32mz/boards/olimex_emz64/olimex_emz64.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2022 Jerzy Kasenberg
diff --git a/hw/bsp/pic32mz/family.c b/hw/bsp/pic32mz/family.c
index 786f04978..895e23899 100644
--- a/hw/bsp/pic32mz/family.c
+++ b/hw/bsp/pic32mz/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2022 Jerzy Kasenberg
diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index e7eab088e..1eeeaf9af 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
index 8280c835d..f9887c09c 100644
--- a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
+++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake
@@ -1 +1 @@
-set(PICO_BOARD pico)
\ No newline at end of file
+set(PICO_BOARD pico)
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 678bce274..5d80ab66e 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -55,7 +55,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		message("Compiling TinyUSB with CFG_TUSB_DEBUG=1")
 		set(TINYUSB_DEBUG_LEVEL 1)
 	endif()
-	
+
 	target_compile_definitions(tinyusb_common_base INTERFACE
 			CFG_TUSB_MCU=OPT_MCU_RP2040
 			CFG_TUSB_OS=${TINYUSB_OPT_OS}
diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
index 9bd9399f6..4f87153ac 100644
--- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
+++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
@@ -33,9 +33,9 @@
  * - Short EMLE pad and 3.3V(GR-CITRUS pin name) with a wire.
  *
  * The pads are [the back side of GR-CITRUS](https://www.slideshare.net/MinaoYamamoto/grcitrusrx631/2).
- * 
+ *
  * Connect the pins between GR-CITRUS and JLink as follows.
- * 
+ *
  * | Function  | GR-CITRUS pin | JLink pin No.| note     |
  * |:---------:|:-------------:|:------------:|:--------:|
  * | VTref     |   3.3V        |   1          |          |
@@ -91,7 +91,7 @@ void INT_Excep_SCI0_TXI0(void)
 {
   uint8_t *buf = sci0_buf[0].buf;
   uint32_t cnt = sci0_buf[0].cnt;
-  
+
   if (!buf || !cnt) {
     SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
     return;
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index 3c729ad50..691038fc8 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -126,7 +126,7 @@ void INT_Excep_SCI5_TXI5(void)
 {
   uint8_t *buf = sci_buf[0].buf;
   uint32_t cnt = sci_buf[0].cnt;
-  
+
   if (!buf || !cnt) {
     SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
     return;
diff --git a/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld b/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld
index 8b3124c0e..9e12acec8 100644
--- a/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld
+++ b/hw/bsp/samd11/boards/samd11_xplained/samd11d14am_flash.ld
@@ -14,9 +14,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the Licence at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.h b/hw/bsp/samd21/boards/atsamd21_xpro/board.h
index a3e03997c..315e40c78 100644
--- a/hw/bsp/samd21/boards/atsamd21_xpro/board.h
+++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.h b/hw/bsp/samd21/boards/circuitplayground_express/board.h
index 2d7da1c0b..0037db00d 100644
--- a/hw/bsp/samd21/boards/circuitplayground_express/board.h
+++ b/hw/bsp/samd21/boards/circuitplayground_express/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.h b/hw/bsp/samd21/boards/curiosity_nano/board.h
index 67924d809..1a4a833a3 100644
--- a/hw/bsp/samd21/boards/curiosity_nano/board.h
+++ b/hw/bsp/samd21/boards/curiosity_nano/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.h b/hw/bsp/samd21/boards/feather_m0_express/board.h
index b9292b9af..8e0caa6bd 100644
--- a/hw/bsp/samd21/boards/feather_m0_express/board.h
+++ b/hw/bsp/samd21/boards/feather_m0_express/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.h b/hw/bsp/samd21/boards/itsybitsy_m0/board.h
index 177fb695e..6ee814da5 100644
--- a/hw/bsp/samd21/boards/itsybitsy_m0/board.h
+++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd21/boards/luna_d21/board.h b/hw/bsp/samd21/boards/luna_d21/board.h
index 2e0a2a60f..776063636 100644
--- a/hw/bsp/samd21/boards/luna_d21/board.h
+++ b/hw/bsp/samd21/boards/luna_d21/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd21/boards/luna_d21/board.mk b/hw/bsp/samd21/boards/luna_d21/board.mk
index 27a634e3a..508a72b1f 100644
--- a/hw/bsp/samd21/boards/luna_d21/board.mk
+++ b/hw/bsp/samd21/boards/luna_d21/board.mk
@@ -8,4 +8,3 @@ JLINK_DEVICE = ATSAMD21G18
 # flash using dfu-util
 flash: $(BUILD)/$(PROJECT).bin
 	dfu-util -a 0 -d 1d50:615c -D $< || dfu-util -a 0 -d 16d0:05a5 -D $<
-
diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.h b/hw/bsp/samd21/boards/metro_m0_express/board.h
index 13b7556b0..d26aae53c 100644
--- a/hw/bsp/samd21/boards/metro_m0_express/board.h
+++ b/hw/bsp/samd21/boards/metro_m0_express/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd21/boards/qtpy/board.h b/hw/bsp/samd21/boards/qtpy/board.h
index 6f8325e49..9ba39e966 100644
--- a/hw/bsp/samd21/boards/qtpy/board.h
+++ b/hw/bsp/samd21/boards/qtpy/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.h b/hw/bsp/samd21/boards/seeeduino_xiao/board.h
index 0d1e9cef1..1bd63d6d9 100644
--- a/hw/bsp/samd21/boards/seeeduino_xiao/board.h
+++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd21/boards/trinket_m0/board.h b/hw/bsp/samd21/boards/trinket_m0/board.h
index c8692e6bd..741f2a7f3 100644
--- a/hw/bsp/samd21/boards/trinket_m0/board.h
+++ b/hw/bsp/samd21/boards/trinket_m0/board.h
@@ -31,4 +31,3 @@
 
 // UART
 #define UART_SERCOM           0
-
diff --git a/hw/bsp/samd21/boards/trinket_m0/board.mk b/hw/bsp/samd21/boards/trinket_m0/board.mk
index 803ffe892..6addf13b7 100644
--- a/hw/bsp/samd21/boards/trinket_m0/board.mk
+++ b/hw/bsp/samd21/boards/trinket_m0/board.mk
@@ -2,4 +2,3 @@ CFLAGS += -D__SAMD21E18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/trinket_m0.ld
-
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index 494dc393a..308fb51b5 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.h b/hw/bsp/samd51/boards/feather_m4_express/board.h
index 1d5ed8040..4629643fd 100644
--- a/hw/bsp/samd51/boards/feather_m4_express/board.h
+++ b/hw/bsp/samd51/boards/feather_m4_express/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd51/boards/itsybitsy_m4/board.h b/hw/bsp/samd51/boards/itsybitsy_m4/board.h
index 0760d4288..272315771 100644
--- a/hw/bsp/samd51/boards/itsybitsy_m4/board.h
+++ b/hw/bsp/samd51/boards/itsybitsy_m4/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h
index ab10ae4f8..5d7734576 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.h
+++ b/hw/bsp/samd51/boards/metro_m4_express/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.mk b/hw/bsp/samd51/boards/metro_m4_express/board.mk
index d7953cc24..57a680e91 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.mk
+++ b/hw/bsp/samd51/boards/metro_m4_express/board.mk
@@ -7,4 +7,3 @@ LD_FILE = $(BOARD_PATH)/$(BOARD).ld
 JLINK_DEVICE = ATSAMD51J19
 
 flash: flash-bossac
-
diff --git a/hw/bsp/samd51/boards/pybadge/board.h b/hw/bsp/samd51/boards/pybadge/board.h
index 1d5ed8040..4629643fd 100644
--- a/hw/bsp/samd51/boards/pybadge/board.h
+++ b/hw/bsp/samd51/boards/pybadge/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd51/boards/pyportal/board.h b/hw/bsp/samd51/boards/pyportal/board.h
index 9e51ded32..ff04c900b 100644
--- a/hw/bsp/samd51/boards/pyportal/board.h
+++ b/hw/bsp/samd51/boards/pyportal/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 020e638c4..3da89ee14 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/same54xplainedpro/same54p20a_flash.ld b/hw/bsp/same54xplainedpro/same54p20a_flash.ld
index 97072bfe6..1f427a066 100644
--- a/hw/bsp/same54xplainedpro/same54p20a_flash.ld
+++ b/hw/bsp/same54xplainedpro/same54p20a_flash.ld
@@ -14,9 +14,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the Licence at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/hw/bsp/same54xplainedpro/same54p20a_sram.ld b/hw/bsp/same54xplainedpro/same54p20a_sram.ld
index 6219f4afe..e6e33ec48 100644
--- a/hw/bsp/same54xplainedpro/same54p20a_sram.ld
+++ b/hw/bsp/same54xplainedpro/same54p20a_sram.ld
@@ -14,9 +14,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the Licence at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/hw/bsp/samg55xplained/samg55xplained.c b/hw/bsp/samg55xplained/samg55xplained.c
index 027c88e2f..6e1ed56a9 100644
--- a/hw/bsp/samg55xplained/samg55xplained.c
+++ b/hw/bsp/samg55xplained/samg55xplained.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, hathach (tinyusb.org)
diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
index a3e03997c..315e40c78 100644
--- a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
+++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.h b/hw/bsp/saml2x/boards/saml22_feather/board.h
index 13a326000..72e9897b6 100644
--- a/hw/bsp/saml2x/boards/saml22_feather/board.h
+++ b/hw/bsp/saml2x/boards/saml22_feather/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld b/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
index d1aaa44fc..156c3e7e4 100644
--- a/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
+++ b/hw/bsp/saml2x/boards/saml22_feather/saml22_feather.ld
@@ -14,9 +14,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the Licence at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
index 7fc690ab2..735f6afc8 100644
--- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld b/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
index d1aaa44fc..156c3e7e4 100644
--- a/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
+++ b/hw/bsp/saml2x/boards/sensorwatch_m0/sensorwatch_m0.ld
@@ -14,9 +14,9 @@
  * Licensed under the Apache License, Version 2.0 (the "License"); you may
  * not use this file except in compliance with the License.
  * You may obtain a copy of the Licence at
- * 
+ *
  * http://www.apache.org/licenses/LICENSE-2.0
- * 
+ *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
diff --git a/hw/bsp/saml2x/family.c b/hw/bsp/saml2x/family.c
index 470fde750..f119d23a1 100644
--- a/hw/bsp/saml2x/family.c
+++ b/hw/bsp/saml2x/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/sltb009a/sltb009a.c b/hw/bsp/sltb009a/sltb009a.c
index b5eb5ed5d..2a5d112a8 100644
--- a/hw/bsp/sltb009a/sltb009a.c
+++ b/hw/bsp/sltb009a/sltb009a.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Rafael Silva (@perigoso)
@@ -712,7 +712,7 @@ uint32_t board_millis(void)
   * @retval None
   */
 void assert_failed(char *file, uint32_t line)
-{ 
+{
   /* USER CODE BEGIN 6 */
   /* User can add his own implementation to report the file name and line number,
      tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
diff --git a/hw/bsp/spresense/board_spresense.c b/hw/bsp/spresense/board_spresense.c
index 256bccd15..5f778ad70 100644
--- a/hw/bsp/spresense/board_spresense.c
+++ b/hw/bsp/spresense/board_spresense.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright 2019 Sony Semiconductor Solutions Corporation
@@ -64,7 +64,7 @@ void board_led_write(bool state)
 // a '1' means active (pressed), a '0' means inactive.
 uint32_t board_button_read(void)
 {
-  if (board_gpio_read(BUTTON_PIN)) 
+  if (board_gpio_read(BUTTON_PIN))
   {
     return 0;
   }
@@ -96,7 +96,7 @@ uint32_t board_millis(void)
     /* Wait until RTC is available */
     while (g_rtc_enabled == false);
 
-    if (clock_gettime(CLOCK_MONOTONIC, &tp)) 
+    if (clock_gettime(CLOCK_MONOTONIC, &tp))
     {
         return 0;
     }
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h
index 7c527e2c2..9af81e63c 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
index cf787a103..1cc443352 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
@@ -12,4 +12,4 @@ IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f070xb_flash.icf
 JLINK_DEVICE = stm32f070rb
 
 # flash target using on-board stlink
-flash: flash-stlink
\ No newline at end of file
+flash: flash-stlink
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
index 4a6491510..6bb9d33cb 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/stm32F070rbtx_flash.ld
@@ -102,12 +102,12 @@ SECTIONS
     . = ALIGN(4);
   } >FLASH
 
-  .ARM.extab   : { 
+  .ARM.extab   : {
   	. = ALIGN(4);
   	*(.ARM.extab* .gnu.linkonce.armextab.*)
   	. = ALIGN(4);
   } >FLASH
-  
+
   .ARM : {
     . = ALIGN(4);
     __exidx_start = .;
@@ -124,7 +124,7 @@ SECTIONS
     PROVIDE_HIDDEN (__preinit_array_end = .);
     . = ALIGN(4);
   } >FLASH
-  
+
   .init_array :
   {
     . = ALIGN(4);
@@ -134,7 +134,7 @@ SECTIONS
     PROVIDE_HIDDEN (__init_array_end = .);
     . = ALIGN(4);
   } >FLASH
-  
+
   .fini_array :
   {
     . = ALIGN(4);
@@ -149,7 +149,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections into "RAM" Ram type memory */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -158,9 +158,9 @@ SECTIONS
 
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
-    
+
   } >RAM AT> FLASH
-  
+
   /* Uninitialized data section into "RAM" Ram type memory */
   . = ALIGN(4);
   .bss :
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
index f0879e929..8715e0723 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/STM32F072RBTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.h b/hw/bsp/stm32f0/boards/stm32f072disco/board.h
index 0b1824b8e..1febd01e8 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.h
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.h b/hw/bsp/stm32f0/boards/stm32f072eval/board.h
index 8869d5dc9..7dcfa3e85 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.h
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index 884208fb1..bfa843494 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f0/stm32f0xx_hal_conf.h b/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
index 0bf053e13..b205464f3 100644
--- a/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
+++ b/hw/bsp/stm32f0/stm32f0xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F0xx_HAL_CONF_H
@@ -30,9 +30,9 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
+#define HAL_MODULE_ENABLED
 /*#define HAL_ADC_MODULE_ENABLED   */
 /*#define HAL_CAN_MODULE_ENABLED   */
 /*#define HAL_CEC_MODULE_ENABLED   */
@@ -65,15 +65,15 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE            8000000U  /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 /**
-  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-  *        Timeout value 
+  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+  *        Timeout value
   */
 #if !defined  (HSE_STARTUP_TIMEOUT)
   #define HSE_STARTUP_TIMEOUT  100U      /*!< Time out for HSE start up, in ms */
@@ -82,24 +82,24 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE            8000000U  /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
-  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-  *        Timeout value 
+  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+  *        Timeout value
   */
-#if !defined  (HSI_STARTUP_TIMEOUT) 
+#if !defined  (HSI_STARTUP_TIMEOUT)
   #define HSI_STARTUP_TIMEOUT  5000U     /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */  
+#endif /* HSI_STARTUP_TIMEOUT */
 
 /**
   * @brief Internal High Speed oscillator for ADC (HSI14) value.
   */
-#if !defined  (HSI14_VALUE) 
+#if !defined  (HSI14_VALUE)
   #define HSI14_VALUE          14000000U /*!< Value of the Internal High Speed oscillator for ADC in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -108,7 +108,7 @@
 /**
   * @brief Internal High Speed oscillator for USB (HSI48) value.
   */
-#if !defined  (HSI48_VALUE) 
+#if !defined  (HSI48_VALUE)
   #define HSI48_VALUE          48000000U /*!< Value of the Internal High Speed oscillator for USB in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -117,8 +117,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
-  #define LSI_VALUE            32000U    
+#if !defined  (LSI_VALUE)
+  #define LSI_VALUE            32000U
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -127,7 +127,7 @@
   */
 #if !defined  (LSE_VALUE)
   #define LSE_VALUE            32768U    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */     
+#endif /* LSE_VALUE */
 
 /**
   * @brief Time out for LSE start up value in ms.
@@ -143,8 +143,8 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    3300U  /*!< Value of VDD in mv */           
+  */
+#define  VDD_VALUE                    3300U  /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default)             */
                                                                               /*  Warning: Must be set to higher priority for HAL_Delay()  */
                                                                               /*  and HAL_GetTick() usage under interrupt context          */
@@ -175,14 +175,14 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
- #define USE_FULL_ASSERT   1 
+ #define USE_FULL_ASSERT   1
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -299,7 +299,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
@@ -308,8 +308,8 @@
   void assert_failed(const char* file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */    
-    
+#endif /* USE_FULL_ASSERT */
+
 #ifdef __cplusplus
 }
 #endif
@@ -318,4 +318,3 @@
 
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
index c434ca038..95836522e 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/STM32F103X8_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
index 57a607ed5..8fa8f4ffa 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
index da637d1b0..524ac7c03 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/STM32F103XC_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
index bedce7f14..c8dba4268 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index 6f0471096..5e112de70 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -53,7 +53,7 @@ void USBWakeUp_IRQHandler(void)
 void board_init(void)
 {
   board_stm32f1_clock_init();
-  
+
   // Enable All GPIOs clocks
   __HAL_RCC_GPIOA_CLK_ENABLE();
   __HAL_RCC_GPIOB_CLK_ENABLE();
@@ -70,7 +70,7 @@ void board_init(void)
   NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
-  
+
   // LED
   GPIO_InitTypeDef  GPIO_InitStruct;
   GPIO_InitStruct.Pin = LED_PIN;
@@ -153,7 +153,7 @@ void HardFault_Handler (void)
   * @retval None
   */
 void assert_failed(const char *file, uint32_t line)
-{ 
+{
   /* USER CODE BEGIN 6 */
   /* User can add his own implementation to report the file name and line number,
      tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
diff --git a/hw/bsp/stm32f1/stm32f1xx_hal_conf.h b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
index 5243e5bca..45ef993da 100644
--- a/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
+++ b/hw/bsp/stm32f1/stm32f1xx_hal_conf.h
@@ -32,7 +32,7 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
 #define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED */
@@ -69,9 +69,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
 #if defined(USE_STM3210C_EVAL)
   #define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
 #else
@@ -86,7 +86,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE              8000000U  /*!< Value of the Internal oscillator in Hz */
@@ -95,7 +95,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE               40000U    /*!< LSI Typical Value in Hz */
 #endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
                                                 The real value may vary depending on the variations
@@ -119,7 +119,7 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY            0x00U /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
@@ -151,7 +151,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -168,7 +168,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    8U                  /* 8 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -176,9 +176,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -190,7 +190,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -205,13 +205,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -233,7 +233,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -243,7 +243,7 @@
 #ifdef HAL_GPIO_MODULE_ENABLED
  #include "stm32f1xx_hal_gpio.h"
 #endif /* HAL_GPIO_MODULE_ENABLED */
-   
+
 #ifdef HAL_EXTI_MODULE_ENABLED
   #include "stm32f1xx_hal_exti.h"
 #endif /* HAL_EXTI_MODULE_ENABLED */
@@ -251,7 +251,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f1xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CAN_MODULE_ENABLED
  #include "stm32f1xx_hal_can.h"
 #endif /* HAL_CAN_MODULE_ENABLED */
@@ -310,15 +310,15 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
  #include "stm32f1xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+#endif /* HAL_PCCARD_MODULE_ENABLED */
 
 #ifdef HAL_SD_MODULE_ENABLED
  #include "stm32f1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */  
+#endif /* HAL_SD_MODULE_ENABLED */
 
 #ifdef HAL_SDRAM_MODULE_ENABLED
  #include "stm32f1xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */     
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_SPI_MODULE_ENABLED
  #include "stm32f1xx_hal_spi.h"
@@ -358,7 +358,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr: If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
@@ -367,8 +367,8 @@
   void assert_failed(const char* file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */    
-    
+#endif /* USE_FULL_ASSERT */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld b/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
index 5010435ae..3fce1b578 100644
--- a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c b/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
index d77643661..80f762c93 100644
--- a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
+++ b/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -105,7 +105,7 @@ void SystemClock_Config(void)
 void board_init(void)
 {
   SystemClock_Config();
-  
+
   #if CFG_TUSB_OS  == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
diff --git a/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h b/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h
index 2ab46b260..b38a9d951 100644
--- a/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h
+++ b/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F2xx_HAL_CONF_H
@@ -30,9 +30,9 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED   */
 /* #define HAL_CAN_MODULE_ENABLED   */
 /* #define HAL_CRC_MODULE_ENABLED   */
@@ -42,7 +42,7 @@
 /* #define HAL_DMA_MODULE_ENABLED */
 /* #define HAL_ETH_MODULE_ENABLED */
 #define HAL_EXTI_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED */
 /* #define HAL_NOR_MODULE_ENABLED */
 /* #define HAL_PCCARD_MODULE_ENABLED */
@@ -52,8 +52,8 @@
 /* #define HAL_I2C_MODULE_ENABLED */
 /* #define HAL_I2S_MODULE_ENABLED    */
 /* #define HAL_IWDG_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED   
-#define HAL_RCC_MODULE_ENABLED 
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED    */
 /* #define HAL_RTC_MODULE_ENABLED */
 /* #define HAL_SD_MODULE_ENABLED   */
@@ -65,7 +65,7 @@
 /* #define HAL_SMARTCARD_MODULE_ENABLED  */
 /* #define HAL_WWDG_MODULE_ENABLED   */
 #define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED 
+#define HAL_PCD_MODULE_ENABLED
 /* #define HAL_HCD_MODULE_ENABLED */
 
 
@@ -73,9 +73,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE                     8000000U       /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -86,7 +86,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE                    16000000U       /*!< Value of the Internal oscillator in Hz*/
@@ -95,7 +95,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE                        32000U       /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                                 /*!< Value of the Internal Low Speed oscillator in Hz
                                                             The real value may vary depending on the variations
@@ -113,8 +113,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE       12288000U        /*!< Value of the Internal oscillator in Hz*/
@@ -126,7 +126,7 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                      3300U /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY              0x0FU /*!< tick interrupt priority */
 #define  USE_RTOS                          0U
@@ -163,7 +163,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -180,7 +180,7 @@
 #define MAC_ADDR4                         0U
 #define MAC_ADDR5                         0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                   ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                       5U       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -190,7 +190,7 @@
 
 /* LAN8742A PHY Address*/
 #define LAN8742A_PHY_ADDRESS            0x00U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -202,7 +202,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -217,7 +217,7 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
@@ -228,7 +228,7 @@
 
 #define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
 #define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
- 
+
 /* ################## SPI peripheral configuration ########################## */
 
 /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
@@ -240,7 +240,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -258,7 +258,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f2xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f2xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -276,7 +276,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f2xx_hal_cryp.h" 
+  #include "stm32f2xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DAC_MODULE_ENABLED
@@ -294,7 +294,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f2xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f2xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -309,7 +309,7 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f2xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+#endif /* HAL_PCCARD_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f2xx_hal_hash.h"
@@ -378,14 +378,14 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f2xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr: If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
@@ -402,6 +402,6 @@
 #endif
 
 #endif /* __STM32F2xx_HAL_CONF_H */
- 
+
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld b/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
index 7f46c71b2..981107af1 100644
--- a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
+++ b/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
@@ -115,7 +115,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -128,11 +128,11 @@ SECTIONS
 
   _siccmram = LOADADDR(.ccmram);
 
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
   * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
+  * the startup code needs to be modified to copy the init-values.
   */
   .ccmram :
   {
@@ -140,12 +140,12 @@ SECTIONS
     _sccmram = .;       /* create a global symbol at ccmram start */
     *(.ccmram)
     *(.ccmram*)
-    
+
     . = ALIGN(4);
     _eccmram = .;       /* create a global symbol at ccmram end */
   } >CCMRAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -173,7 +173,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -185,5 +185,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f303disco/stm32f303disco.c b/hw/bsp/stm32f303disco/stm32f303disco.c
index 940c49d26..ac9bda983 100644
--- a/hw/bsp/stm32f303disco/stm32f303disco.c
+++ b/hw/bsp/stm32f303disco/stm32f303disco.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h b/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h
index 0abcbb019..82d3765af 100644
--- a/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h
+++ b/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F3xx_HAL_CONF_H
@@ -30,9 +30,9 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED */
 /* #define HAL_CAN_MODULE_ENABLED */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED */
@@ -57,7 +57,7 @@
 /* #define HAL_OPAMP_MODULE_ENABLED */
 /* #define HAL_PCD_MODULE_ENABLED */
 /* #define HAL_PWR_MODULE_ENABLED */
-#define HAL_RCC_MODULE_ENABLED 
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RTC_MODULE_ENABLED */
 /* #define HAL_SDADC_MODULE_ENABLED */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
@@ -73,15 +73,15 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 /**
-  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-  *        Timeout value 
+  * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+  *        Timeout value
   */
 #if !defined  (HSE_STARTUP_TIMEOUT)
   #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
@@ -90,25 +90,25 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (8000000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
-  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-  *        Timeout value 
+  * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+  *        Timeout value
   */
-#if !defined  (HSI_STARTUP_TIMEOUT) 
+#if !defined  (HSI_STARTUP_TIMEOUT)
  #define HSI_STARTUP_TIMEOUT   (5000U) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */  
+#endif /* HSI_STARTUP_TIMEOUT */
 
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (40000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (40000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -124,11 +124,11 @@
   */
 #if !defined  (LSE_STARTUP_TIMEOUT)
   #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */     
+#endif /* LSE_STARTUP_TIMEOUT */
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
   *        frequency, this source is inserted directly through I2S_CKIN pad.
   *        - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
   *        - External clock not generated on EVAL 373
@@ -256,8 +256,8 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f3xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_HRTIM_MODULE_ENABLED
  #include "stm32f3xx_hal_hrtim.h"
 #endif /* HAL_HRTIM_MODULE_ENABLED */
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld b/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
index 9eb53bcc0..0dc2879a4 100644
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/STM32F405RGTx_FLASH.ld
@@ -115,7 +115,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -128,11 +128,11 @@ SECTIONS
 
   _siccmram = LOADADDR(.ccmram);
 
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
   * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
+  * the startup code needs to be modified to copy the init-values.
   */
   .ccmram :
   {
@@ -140,12 +140,12 @@ SECTIONS
     _sccmram = .;       /* create a global symbol at ccmram start */
     *(.ccmram)
     *(.ccmram*)
-    
+
     . = ALIGN(4);
     _eccmram = .;       /* create a global symbol at ccmram end */
   } >CCMRAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -173,7 +173,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -185,5 +185,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
index 19d0a1ea4..d1ad2a6ce 100644
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld b/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
index 9eb53bcc0..0dc2879a4 100644
--- a/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/pyboardv11/STM32F405RGTx_FLASH.ld
@@ -115,7 +115,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -128,11 +128,11 @@ SECTIONS
 
   _siccmram = LOADADDR(.ccmram);
 
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
   * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
+  * the startup code needs to be modified to copy the init-values.
   */
   .ccmram :
   {
@@ -140,12 +140,12 @@ SECTIONS
     _sccmram = .;       /* create a global symbol at ccmram start */
     *(.ccmram)
     *(.ccmram*)
-    
+
     . = ALIGN(4);
     _eccmram = .;       /* create a global symbol at ccmram end */
   } >CCMRAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -173,7 +173,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -185,5 +185,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.h b/hw/bsp/stm32f4/boards/pyboardv11/board.h
index 685919c57..c126f0666 100644
--- a/hw/bsp/stm32f4/boards/pyboardv11/board.h
+++ b/hw/bsp/stm32f4/boards/pyboardv11/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
index 2bc5f6c14..b91f456ca 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/STM32F401VCTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
index e1fef7277..e6c99a462 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h
index 2ab9a1d57..16f081cfb 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (25000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
index aac6577ea..549787945 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/STM32F407VGTx_FLASH.ld
@@ -115,7 +115,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -128,11 +128,11 @@ SECTIONS
 
   _siccmram = LOADADDR(.ccmram);
 
-  /* CCM-RAM section 
-  * 
-  * IMPORTANT NOTE! 
+  /* CCM-RAM section
+  *
+  * IMPORTANT NOTE!
   * If initialized variables will be placed in this section,
-  * the startup code needs to be modified to copy the init-values.  
+  * the startup code needs to be modified to copy the init-values.
   */
   .ccmram :
   {
@@ -140,12 +140,12 @@ SECTIONS
     _sccmram = .;       /* create a global symbol at ccmram start */
     *(.ccmram)
     *(.ccmram*)
-    
+
     . = ALIGN(4);
     _eccmram = .;       /* create a global symbol at ccmram end */
   } >CCMRAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -173,7 +173,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -185,5 +185,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.h b/hw/bsp/stm32f4/boards/stm32f407disco/board.h
index 693e0393f..c38f354ce 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h
index 7864f8d5f..e24e782ea 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
index 56dcea605..45912ac32 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/STM32F411CEUx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(4);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
index e1fef7277..e6c99a462 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h
index 2ab9a1d57..16f081cfb 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (25000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
index 4477229ea..85bf5c4c4 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/STM32F411VETx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.h b/hw/bsp/stm32f4/boards/stm32f411disco/board.h
index 008a94a5d..57d1e061e 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h
index 7864f8d5f..e24e782ea 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
index 2372cc1d9..38dd3d321 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/STM32F412ZGTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.h b/hw/bsp/stm32f4/boards/stm32f412disco/board.h
index 7f4a4fa15..d61b70eb9 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/board.h
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h
index 7864f8d5f..e24e782ea 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
index 2372cc1d9..38dd3d321 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/STM32F412ZGTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
index 7864f8d5f..e24e782ea 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -205,7 +205,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -213,9 +213,9 @@
 
 /* Section 2: PHY configuration section */
 
-/* DP83848 PHY Address*/ 
+/* DP83848 PHY Address*/
 #define DP83848_PHY_ADDRESS             0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 0x000000FFU
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                0x00000FFFU
@@ -227,7 +227,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -242,13 +242,13 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
 #define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
 #define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
- 
+
 #define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
 #define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
 #define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
@@ -270,7 +270,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -288,7 +288,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -310,7 +310,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -332,7 +332,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -347,11 +347,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -432,7 +432,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -471,7 +471,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h
index a2c11d717..7bbd6b54f 100644
--- a/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/stm32f4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F4xx_HAL_CONF_H
@@ -30,38 +30,38 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED         
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED      */
 /* #define HAL_CAN_MODULE_ENABLED      */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
-/* #define HAL_CRC_MODULE_ENABLED      */ 
-/* #define HAL_CEC_MODULE_ENABLED      */ 
-/* #define HAL_CRYP_MODULE_ENABLED     */ 
-/* #define HAL_DAC_MODULE_ENABLED      */ 
-/* #define HAL_DCMI_MODULE_ENABLED     */ 
-#define HAL_DMA_MODULE_ENABLED 
-/* #define HAL_DMA2D_MODULE_ENABLED    */ 
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
 /* #define HAL_ETH_MODULE_ENABLED      */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED     */
 /* #define HAL_NOR_MODULE_ENABLED      */
 /* #define HAL_PCCARD_MODULE_ENABLED   */
 /* #define HAL_SRAM_MODULE_ENABLED     */
 /* #define HAL_SDRAM_MODULE_ENABLED    */
-/* #define HAL_HASH_MODULE_ENABLED     */  
+/* #define HAL_HASH_MODULE_ENABLED     */
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_EXTI_MODULE_ENABLED     */
 /* #define HAL_I2C_MODULE_ENABLED      */
 /* #define HAL_SMBUS_MODULE_ENABLED    */
 /* #define HAL_I2S_MODULE_ENABLED      */
-/* #define HAL_IWDG_MODULE_ENABLED     */ 
+/* #define HAL_IWDG_MODULE_ENABLED     */
 /* #define HAL_LTDC_MODULE_ENABLED     */
 /* #define HAL_DSI_MODULE_ENABLED      */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED     */
-#define HAL_RCC_MODULE_ENABLED      
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED      */
 /* #define HAL_RTC_MODULE_ENABLED      */
 /* #define HAL_SAI_MODULE_ENABLED      */
@@ -69,11 +69,11 @@
 // #define HAL_SPI_MODULE_ENABLED
 /* #define HAL_TIM_MODULE_ENABLED      */
 #define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED    */ 
+/* #define HAL_USART_MODULE_ENABLED    */
 /* #define HAL_IRDA_MODULE_ENABLED     */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
 /* #define HAL_WWDG_MODULE_ENABLED     */
-#define HAL_CORTEX_MODULE_ENABLED   
+#define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED      */
 /* #define HAL_HCD_MODULE_ENABLED      */
 /* #define HAL_FMPI2C_MODULE_ENABLED   */
@@ -86,9 +86,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -108,8 +108,8 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE  (32000U)    
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -126,8 +126,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
@@ -139,9 +139,9 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */           
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              1U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -263,7 +263,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -281,7 +281,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f4xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f4xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -303,7 +303,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h" 
+  #include "stm32f4xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -325,7 +325,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f4xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -340,11 +340,11 @@
 
 #ifdef HAL_PCCARD_MODULE_ENABLED
   #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-  
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f4xx_hal_hash.h"
@@ -425,7 +425,7 @@
 #ifdef HAL_HCD_MODULE_ENABLED
  #include "stm32f4xx_hal_hcd.h"
 #endif /* HAL_HCD_MODULE_ENABLED */
-   
+
 #ifdef HAL_DSI_MODULE_ENABLED
  #include "stm32f4xx_hal_dsi.h"
 #endif /* HAL_DSI_MODULE_ENABLED */
@@ -464,7 +464,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index 93ab5bb35..a308bae05 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h
index d0ef6625f..ed02df061 100644
--- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/hw/bsp/stm32f7/boards/stm32f723disco/board.h
index 93d83efc6..258786b7f 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.h b/hw/bsp/stm32f7/boards/stm32f746disco/board.h
index ee342b9f5..1c7e6dd2b 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
index e1e60bc78..eeb0e29f3 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/STM32F746ZGTx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
index 92c109a72..cf895af87 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h
index 234191b00..03dec8f0d 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h
@@ -2,7 +2,7 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_conf.h
   * @author  MCD Application Team
-  * @brief   HAL configuration file. 
+  * @brief   HAL configuration file.
   ******************************************************************************
   * @attention
   *
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F7xx_HAL_CONF_H
@@ -30,9 +30,9 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED   */
 /* #define HAL_CAN_MODULE_ENABLED */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED */
@@ -44,7 +44,7 @@
 #define HAL_DMA_MODULE_ENABLED
 /* #define HAL_DMA2D_MODULE_ENABLED  */
 /* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED */
 /* #define HAL_NOR_MODULE_ENABLED */
 /* #define HAL_SRAM_MODULE_ENABLED */
@@ -58,7 +58,7 @@
 /* #define HAL_LTDC_MODULE_ENABLED  */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED 
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED    */
 /* #define HAL_RTC_MODULE_ENABLED */
 /* #define HAL_SAI_MODULE_ENABLED    */
@@ -84,9 +84,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -97,7 +97,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -106,7 +106,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
@@ -124,8 +124,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
@@ -137,7 +137,7 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
@@ -185,7 +185,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1 */
@@ -202,7 +202,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -211,7 +211,7 @@
 /* Section 2: PHY configuration section */
 /* LAN8742A PHY Address*/
 #define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
@@ -223,7 +223,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -238,7 +238,7 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
@@ -261,7 +261,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -275,7 +275,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f7xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f7xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -301,7 +301,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h" 
+  #include "stm32f7xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -323,7 +323,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f7xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f7xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -338,7 +338,7 @@
 
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f7xx_hal_hash.h"
@@ -443,14 +443,14 @@
 #ifdef HAL_MDIOS_MODULE_ENABLED
  #include "stm32f7xx_hal_mdios.h"
 #endif /* HAL_MDIOS_MODULE_ENABLED */
-   
+
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr: If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
@@ -467,6 +467,6 @@
 #endif
 
 #endif /* __STM32F7xx_HAL_CONF_H */
- 
+
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld b/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
index 3785f9cbf..520a75539 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/STM32F767ZITx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h
index 1283f2313..e053572a7 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
index a460245b2..be5862612 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
@@ -1,5 +1,5 @@
 PORT ?= 0
-SPEED ?= full 
+SPEED ?= full
 
 CFLAGS += \
   -DSTM32F767xx \
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h
index 234191b00..03dec8f0d 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h
@@ -2,7 +2,7 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_conf.h
   * @author  MCD Application Team
-  * @brief   HAL configuration file. 
+  * @brief   HAL configuration file.
   ******************************************************************************
   * @attention
   *
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F7xx_HAL_CONF_H
@@ -30,9 +30,9 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
+#define HAL_MODULE_ENABLED
 /* #define HAL_ADC_MODULE_ENABLED   */
 /* #define HAL_CAN_MODULE_ENABLED */
 /* #define HAL_CAN_LEGACY_MODULE_ENABLED */
@@ -44,7 +44,7 @@
 #define HAL_DMA_MODULE_ENABLED
 /* #define HAL_DMA2D_MODULE_ENABLED  */
 /* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 /* #define HAL_NAND_MODULE_ENABLED */
 /* #define HAL_NOR_MODULE_ENABLED */
 /* #define HAL_SRAM_MODULE_ENABLED */
@@ -58,7 +58,7 @@
 /* #define HAL_LTDC_MODULE_ENABLED  */
 #define HAL_PWR_MODULE_ENABLED
 /* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED 
+#define HAL_RCC_MODULE_ENABLED
 /* #define HAL_RNG_MODULE_ENABLED    */
 /* #define HAL_RTC_MODULE_ENABLED */
 /* #define HAL_SAI_MODULE_ENABLED    */
@@ -84,9 +84,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -97,7 +97,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -106,7 +106,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
@@ -124,8 +124,8 @@
 
 /**
   * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source 
-  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
   */
 #if !defined  (EXTERNAL_CLOCK_VALUE)
   #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
@@ -137,7 +137,7 @@
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
 #define  USE_RTOS                     0U
@@ -185,7 +185,7 @@
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1 */
@@ -202,7 +202,7 @@
 #define MAC_ADDR4   0U
 #define MAC_ADDR5   0U
 
-/* Definition of the Ethernet driver buffers size and count */   
+/* Definition of the Ethernet driver buffers size and count */
 #define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
 #define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
 #define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
@@ -211,7 +211,7 @@
 /* Section 2: PHY configuration section */
 /* LAN8742A PHY Address*/
 #define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
 #define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
 /* PHY Configuration delay */
 #define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
@@ -223,7 +223,7 @@
 
 #define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
 #define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
+
 #define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
 #define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
 #define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
@@ -238,7 +238,7 @@
 #define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
 #define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
 #define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
+
 /* Section 4: Extended PHY Registers */
 
 #define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
@@ -261,7 +261,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -275,7 +275,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32f7xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32f7xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -301,7 +301,7 @@
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h" 
+  #include "stm32f7xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DMA2D_MODULE_ENABLED
@@ -323,7 +323,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32f7xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_SRAM_MODULE_ENABLED
   #include "stm32f7xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
@@ -338,7 +338,7 @@
 
 #ifdef HAL_SDRAM_MODULE_ENABLED
   #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */      
+#endif /* HAL_SDRAM_MODULE_ENABLED */
 
 #ifdef HAL_HASH_MODULE_ENABLED
  #include "stm32f7xx_hal_hash.h"
@@ -443,14 +443,14 @@
 #ifdef HAL_MDIOS_MODULE_ENABLED
  #include "stm32f7xx_hal_mdios.h"
 #endif /* HAL_MDIOS_MODULE_ENABLED */
-   
+
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
 /**
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr: If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
@@ -467,6 +467,6 @@
 #endif
 
 #endif /* __STM32F7xx_HAL_CONF_H */
- 
+
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.h b/hw/bsp/stm32f7/boards/stm32f769disco/board.h
index 5ec217f5f..472af0b98 100644
--- a/hw/bsp/stm32f7/boards/stm32f769disco/board.h
+++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
index 9c327483b..c43829994 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
@@ -135,7 +135,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -146,7 +146,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -174,7 +174,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -186,5 +186,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index f3ba54576..f5177fd10 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32g4/stm32g4xx_hal_conf.h b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h
index ad5f7dbd4..632c4f0ac 100644
--- a/hw/bsp/stm32g4/stm32g4xx_hal_conf.h
+++ b/hw/bsp/stm32g4/stm32g4xx_hal_conf.h
@@ -15,7 +15,7 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef STM32G4xx_HAL_CONF_H
@@ -30,10 +30,10 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-  
-#define HAL_MODULE_ENABLED  
+
+#define HAL_MODULE_ENABLED
 
   /*#define HAL_ADC_MODULE_ENABLED   */
 /*#define HAL_COMP_MODULE_ENABLED   */
@@ -111,9 +111,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    (24000000UL) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -124,7 +124,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
@@ -145,10 +145,10 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
 /*!< Value of the Internal Low Speed oscillator in Hz
 The real value may vary depending on the variations in voltage and temperature.*/
-#define LSI_VALUE  (32000UL)     /*!< LSI Typical Value in Hz*/    
+#define LSI_VALUE  (32000UL)     /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */
 /**
   * @brief External Low Speed oscillator (LSE) value.
@@ -156,7 +156,7 @@ The real value may vary depending on the variations in voltage and temperature.*
   */
 #if !defined  (LSE_VALUE)
 #define LSE_VALUE  (32768UL)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */     
+#endif /* LSE_VALUE */
 
 #if !defined  (LSE_STARTUP_TIMEOUT)
 #define LSE_STARTUP_TIMEOUT    (5000UL)   /*!< Time out for LSE start up, in ms */
@@ -177,10 +177,10 @@ The real value may vary depending on the variations in voltage and temperature.*
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 
 #define  VDD_VALUE                   (3300UL) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY           (0UL)    /*!< tick interrupt priority (lowest by default)  */            
+#define  TICK_INT_PRIORITY           (0UL)    /*!< tick interrupt priority (lowest by default)  */
 #define  USE_RTOS                     0U
 #define  PREFETCH_ENABLE              0U
 #define  INSTRUCTION_CACHE_ENABLE     1U
@@ -188,7 +188,7 @@ The real value may vary depending on the variations in voltage and temperature.*
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.mk b/hw/bsp/stm32h7/boards/daisyseed/board.mk
index 4d718f04e..d53782496 100644
--- a/hw/bsp/stm32h7/boards/daisyseed/board.mk
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.mk
@@ -16,4 +16,3 @@ JLINK_DEVICE = stm32h750ibk6_m7
 
 # flash target using on-board stlink
 flash: flash-stlink
-
diff --git a/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld
index 83904067a..3588ada5b 100644
--- a/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld
+++ b/hw/bsp/stm32h7/boards/daisyseed/stm32h750ibkx_flash.ld
@@ -172,5 +172,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
index 7ee40671c..336afc01f 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
@@ -118,7 +118,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -129,7 +129,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >DTCMRAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -157,7 +157,7 @@ SECTIONS
     . = ALIGN(8);
   } >DTCMRAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -169,5 +169,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
index 7ee40671c..336afc01f 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
@@ -118,7 +118,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -129,7 +129,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >DTCMRAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -157,7 +157,7 @@ SECTIONS
     . = ALIGN(8);
   } >DTCMRAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -169,5 +169,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
index b51b109f6..86347ade7 100644
--- a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
@@ -19,4 +19,3 @@ JLINK_DEVICE = stm32h745xi_m7
 
 # flash target using on-board stlink
 flash: flash-stlink
-
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld b/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
index e99bb977b..697a1a1df 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
@@ -171,5 +171,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
index fbf4b55c6..e8202d9fc 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
@@ -21,4 +21,4 @@ IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf
 JLINK_DEVICE = stm32h743ii
 
 # flash target using jlink
-flash: flash-jlink
\ No newline at end of file
+flash: flash-jlink
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 65ffc8ef4..35b2cd55b 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -91,7 +91,7 @@ void board_init(void)
 #endif
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
-  
+
   GPIO_InitTypeDef  GPIO_InitStruct;
 
   // LED
diff --git a/hw/bsp/stm32h7/stm32h7xx_hal_conf.h b/hw/bsp/stm32h7/stm32h7xx_hal_conf.h
index a7cc6d826..216fc82f2 100644
--- a/hw/bsp/stm32h7/stm32h7xx_hal_conf.h
+++ b/hw/bsp/stm32h7/stm32h7xx_hal_conf.h
@@ -1,7 +1,7 @@
 /**
   ******************************************************************************
   * @file    stm32h7xx_hal_conf_template.h
-  * @brief   HAL configuration template file. 
+  * @brief   HAL configuration template file.
   *          This file should be copied to the application folder and renamed
   *          to stm32h7xx_hal_conf.h.
   ******************************************************************************
@@ -32,7 +32,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32H7xx_HAL_CONF_H
@@ -478,6 +478,6 @@
 #endif
 
 #endif /* __STM32H7xx_HAL_CONF_H */
- 
+
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
index dfefe59f1..d4d5b6ca5 100644
--- a/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/STM32L052K8Ux_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
index 8ad3e43c8..c8963199b 100644
--- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -58,43 +58,43 @@ static inline void board_stm32l0_clock_init(void)
   RCC_OscInitTypeDef RCC_OscInitStruct;
   RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
   static RCC_CRSInitTypeDef RCC_CRSInitStruct;
-  
+
   /* Enable HSI Oscillator to be used as System clock source
      Enable HSI48 Oscillator to be used as USB clock source */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
   RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct); 
- 
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
   /* Select HSI48 as USB clock source */
   PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
   PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
   HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-  
-  /* Select HSI as system clock source and configure the HCLK, PCLK1 and PCLK2 
+
+  /* Select HSI as system clock source and configure the HCLK, PCLK1 and PCLK2
      clock dividers */
   RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;  
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;  
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-    
+
   /*Configure the clock recovery system (CRS)**********************************/
-  
+
   /*Enable CRS Clock*/
-  __HAL_RCC_CRS_CLK_ENABLE(); 
-  
+  __HAL_RCC_CRS_CLK_ENABLE();
+
   /* Default Synchro Signal division factor (not divided) */
-  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;  
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
   /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
-  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;  
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
   /* HSI48 is synchronized with USB SOF at 1KHz rate */
   RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
-  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;  
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
   /* Set the TRIM[5:0] to the default value*/
-  RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;   
-  /* Start automatic synchronization */ 
+  RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;
+  /* Start automatic synchronization */
   HAL_RCCEx_CRSConfig (&RCC_CRSInitStruct);
 }
 
diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c
index dcd71a513..6bce88b39 100644
--- a/hw/bsp/stm32l0/family.c
+++ b/hw/bsp/stm32l0/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32l0/stm32l0xx_hal_conf.h b/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
index cc20ea8e0..e3a131043 100644
--- a/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
+++ b/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
@@ -2,22 +2,22 @@
   ******************************************************************************
   * @file    stm32l0xx_hal_conf.h
   * @author  MCD Application Team
-  * @brief   HAL configuration template file. 
+  * @brief   HAL configuration template file.
   *          This file should be copied to the application folder and renamed
   *          to stm32l0xx_hal_conf.h.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
+  * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L0xx_HAL_CONF_H
@@ -32,9 +32,9 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
+#define HAL_MODULE_ENABLED
 /*#define HAL_ADC_MODULE_ENABLED */
 /*#define HAL_COMP_MODULE_ENABLED */
 /*#define HAL_CRC_MODULE_ENABLED */
@@ -69,9 +69,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -90,7 +90,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -99,7 +99,7 @@
 /**
   * @brief Internal High Speed oscillator for USB (HSI48) value.
   */
-#if !defined  (HSI48_VALUE) 
+#if !defined  (HSI48_VALUE)
 #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -108,7 +108,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE  ((uint32_t)37000U)       /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
@@ -128,24 +128,24 @@
   #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
-   
+
 /* Tip: To avoid modifying this file each time you need to use different HSE,
    ===  you can define the HSE value in your toolchain compiler preprocessor. */
 
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
+  */
 #define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U)    /*!< tick interrupt priority */            
-#define  USE_RTOS                     0U     
-#define  PREFETCH_ENABLE              1U              
+#define  TICK_INT_PRIORITY            (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U)    /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
 #define  PREREAD_ENABLE               0U
 #define  BUFFER_CACHE_DISABLE         0U
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1U */
@@ -191,13 +191,13 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
   #include "stm32l0xx_hal_rcc.h"
 #endif /* HAL_RCC_MODULE_ENABLED */
-  
+
 #ifdef HAL_GPIO_MODULE_ENABLED
   #include "stm32l0xx_hal_gpio.h"
 #endif /* HAL_GPIO_MODULE_ENABLED */
@@ -233,11 +233,11 @@
 #ifdef HAL_FIREWALL_MODULE_ENABLED
   #include "stm32l0xx_hal_firewall.h"
 #endif /* HAL_FIREWALL_MODULE_ENABLED */
- 
+
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32l0xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_I2C_MODULE_ENABLED
  #include "stm32l0xx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
@@ -257,7 +257,7 @@
 #ifdef HAL_LPTIM_MODULE_ENABLED
 #include "stm32l0xx_hal_lptim.h"
 #endif /* HAL_LPTIM_MODULE_ENABLED */
-   
+
 #ifdef HAL_PWR_MODULE_ENABLED
  #include "stm32l0xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */
@@ -316,7 +316,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
@@ -332,7 +332,6 @@
 #endif
 
 #endif /* __STM32L0xx_HAL_CONF_H */
- 
+
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld b/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
index 79427d80b..033dcc0ad 100644
--- a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
+++ b/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -165,5 +165,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32l0538disco/stm32l0538disco.c b/hw/bsp/stm32l0538disco/stm32l0538disco.c
index f4c38d150..46f6f0ff6 100644
--- a/hw/bsp/stm32l0538disco/stm32l0538disco.c
+++ b/hw/bsp/stm32l0538disco/stm32l0538disco.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h b/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h
index 773b74e29..a917214c3 100644
--- a/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h
+++ b/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h
@@ -7,39 +7,39 @@
   *
   * Copyright (c) 2016 STMicroelectronics International N.V. All rights reserved.
   *
-  * Redistribution and use in source and binary forms, with or without 
+  * Redistribution and use in source and binary forms, with or without
   * modification, are permitted, provided that the following conditions are met:
   *
-  * 1. Redistribution of source code must retain the above copyright notice, 
+  * 1. Redistribution of source code must retain the above copyright notice,
   *    this list of conditions and the following disclaimer.
   * 2. Redistributions in binary form must reproduce the above copyright notice,
   *    this list of conditions and the following disclaimer in the documentation
   *    and/or other materials provided with the distribution.
-  * 3. Neither the name of STMicroelectronics nor the names of other 
-  *    contributors to this software may be used to endorse or promote products 
+  * 3. Neither the name of STMicroelectronics nor the names of other
+  *    contributors to this software may be used to endorse or promote products
   *    derived from this software without specific written permission.
-  * 4. This software, including modifications and/or derivative works of this 
+  * 4. This software, including modifications and/or derivative works of this
   *    software, must execute solely and exclusively on microcontroller or
   *    microprocessor devices manufactured by or for STMicroelectronics.
-  * 5. Redistribution and use of this software other than as permitted under 
-  *    this license is void and will automatically terminate your rights under 
-  *    this license. 
+  * 5. Redistribution and use of this software other than as permitted under
+  *    this license is void and will automatically terminate your rights under
+  *    this license.
   *
-  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" 
-  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT 
-  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A 
+  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
+  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
   * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
-  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT 
+  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
   * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
   * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
-  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
-  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
+  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
   * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
   * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L0xx_HAL_CONF_H
@@ -54,36 +54,36 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver 
+  * @brief This is the list of modules to be used in the HAL driver
   */
-#define HAL_MODULE_ENABLED  
+#define HAL_MODULE_ENABLED
 // #define HAL_ADC_MODULE_ENABLED
-/* #define HAL_COMP_MODULE_ENABLED */ 
-/* #define HAL_CRC_MODULE_ENABLED */  
-/* #define HAL_CRYP_MODULE_ENABLED */ 
-/* #define HAL_DAC_MODULE_ENABLED */   
+/* #define HAL_COMP_MODULE_ENABLED */
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
 #define HAL_DMA_MODULE_ENABLED
 /* #define HAL_FIREWALL_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED 
+#define HAL_FLASH_MODULE_ENABLED
 #define HAL_GPIO_MODULE_ENABLED
 /* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */   
+/* #define HAL_I2S_MODULE_ENABLED */
 /* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LCD_MODULE_ENABLED */ 
+/* #define HAL_LCD_MODULE_ENABLED */
 /* #define HAL_LPTIM_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED  
-#define HAL_RCC_MODULE_ENABLED 
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
 //#define HAL_RNG_MODULE_ENABLED
 /* #define HAL_RTC_MODULE_ENABLED */
 //#define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED */   
+/* #define HAL_TIM_MODULE_ENABLED */
 /* #define HAL_TSC_MODULE_ENABLED */
-/* #define HAL_UART_MODULE_ENABLED */ 
-/* #define HAL_USART_MODULE_ENABLED */ 
+/* #define HAL_UART_MODULE_ENABLED */
+/* #define HAL_USART_MODULE_ENABLED */
 /* #define HAL_IRDA_MODULE_ENABLED */
 /* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */   
-/* #define HAL_WWDG_MODULE_ENABLED */ 
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
 //#define HAL_PCD_MODULE_ENABLED
 #define HAL_CORTEX_MODULE_ENABLED
 /* #define HAL_PCD_MODULE_ENABLED */
@@ -93,9 +93,9 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
+  *        (when HSE is used as system clock source, directly or through the PLL).
   */
-#if !defined  (HSE_VALUE) 
+#if !defined  (HSE_VALUE)
   #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
@@ -114,7 +114,7 @@
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
+  *        (when HSI is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSI_VALUE)
   #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
@@ -123,7 +123,7 @@
 /**
   * @brief Internal High Speed oscillator for USB (HSI48) value.
   */
-#if !defined  (HSI48_VALUE) 
+#if !defined  (HSI48_VALUE)
 #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
                                              The real value may vary depending on the variations
                                              in voltage and temperature.  */
@@ -132,7 +132,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE  ((uint32_t)37000U)       /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
@@ -152,24 +152,24 @@
   #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
 #endif /* LSE_STARTUP_TIMEOUT */
 
-   
+
 /* Tip: To avoid modifying this file each time you need to use different HSE,
    ===  you can define the HSE value in your toolchain compiler preprocessor. */
 
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */ 
-#define  TICK_INT_PRIORITY            ((uint32_t)0U)    /*!< tick interrupt priority */           
-#define  USE_RTOS                     0U     
-#define  PREFETCH_ENABLE              1U              
+  */
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U)    /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
 #define  PREREAD_ENABLE               1U
 #define  BUFFER_CACHE_DISABLE         0U
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
   *        HAL drivers code
   */
 /* #define USE_FULL_ASSERT    1 */
@@ -185,7 +185,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file 
+  * @brief Include module's header file
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
@@ -199,7 +199,7 @@
 #ifdef HAL_DMA_MODULE_ENABLED
   #include "stm32l0xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
-   
+
 #ifdef HAL_CORTEX_MODULE_ENABLED
   #include "stm32l0xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -211,7 +211,7 @@
 #ifdef HAL_COMP_MODULE_ENABLED
   #include "stm32l0xx_hal_comp.h"
 #endif /* HAL_COMP_MODULE_ENABLED */
-   
+
 #ifdef HAL_CRC_MODULE_ENABLED
   #include "stm32l0xx_hal_crc.h"
 #endif /* HAL_CRC_MODULE_ENABLED */
@@ -231,7 +231,7 @@
 #ifdef HAL_FLASH_MODULE_ENABLED
   #include "stm32l0xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
- 
+
 #ifdef HAL_I2C_MODULE_ENABLED
  #include "stm32l0xx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
@@ -251,7 +251,7 @@
 #ifdef HAL_LPTIM_MODULE_ENABLED
 #include "stm32l0xx_hal_lptim.h"
 #endif /* HAL_LPTIM_MODULE_ENABLED */
-   
+
 #ifdef HAL_PWR_MODULE_ENABLED
  #include "stm32l0xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */
@@ -310,7 +310,7 @@
   * @brief  The assert_param macro is used for function's parameters check.
   * @param  expr If expr is false, it calls assert_failed function
   *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
+  *         line number of the call that failed.
   *         If expr is true, it returns no value.
   * @retval None
   */
@@ -326,6 +326,6 @@
 #endif
 
 #endif /* __STM32L0xx_HAL_CONF_H */
- 
+
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
index d4b86b3e3..4ae4a4cf4 100644
--- a/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
@@ -83,8 +83,8 @@ SECTIONS
     . = ALIGN(8);
   } >FLASH
 
-  .ARM.extab   : 
-  { 
+  .ARM.extab   :
+  {
   . = ALIGN(8);
   *(.ARM.extab* .gnu.linkonce.armextab.*)
   . = ALIGN(8);
@@ -105,7 +105,7 @@ SECTIONS
     PROVIDE_HIDDEN (__preinit_array_end = .);
 	. = ALIGN(8);
   } >FLASH
-  
+
   .init_array :
   {
 	. = ALIGN(8);
@@ -129,7 +129,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(8);
     _sdata = .;        /* create a global symbol at data start */
@@ -140,7 +140,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -168,7 +168,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -180,5 +180,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
index 704d742cc..72d17b760 100644
--- a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
@@ -94,7 +94,7 @@ static inline void board_clock_init(void)
   RCC_OscInitStruct.PLL.PLLN = 10;
   RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
-  
+
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
   /** Initializes the CPU, AHB and APB buses clocks
@@ -122,7 +122,7 @@ static inline void board_clock_init(void)
   RCC_CRSInitStruct.HSI48CalibrationValue = 32;
 
   HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
-  
+
   /* Select HSI48 output as USB clock source */
   PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
   PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
index d6865f49d..3bb13ed85 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/STM32L476VGTx_FLASH.ld
@@ -82,8 +82,8 @@ SECTIONS
     . = ALIGN(8);
   } >FLASH
 
-  .ARM.extab   : 
-  { 
+  .ARM.extab   :
+  {
   . = ALIGN(8);
   *(.ARM.extab* .gnu.linkonce.armextab.*)
   . = ALIGN(8);
@@ -104,7 +104,7 @@ SECTIONS
     PROVIDE_HIDDEN (__preinit_array_end = .);
 	. = ALIGN(8);
   } >FLASH
-  
+
   .init_array :
   {
 	. = ALIGN(8);
@@ -128,7 +128,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(8);
     _sdata = .;        /* create a global symbol at data start */
@@ -139,7 +139,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -167,7 +167,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -179,5 +179,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.h b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
index 42c657d5e..9d4351b39 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld
index c1a490a70..02c07dd74 100644
--- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/STM32L4P5ZGTX_FLASH.ld
@@ -102,12 +102,12 @@ SECTIONS
     . = ALIGN(4);
   } >ROM
 
-  .ARM.extab   : { 
+  .ARM.extab   : {
     . = ALIGN(4);
     *(.ARM.extab* .gnu.linkonce.armextab.*)
     . = ALIGN(4);
   } >ROM
-  
+
   .ARM : {
     . = ALIGN(4);
     __exidx_start = .;
@@ -124,7 +124,7 @@ SECTIONS
     PROVIDE_HIDDEN (__preinit_array_end = .);
     . = ALIGN(4);
   } >ROM
-  
+
   .init_array :
   {
     . = ALIGN(4);
@@ -134,7 +134,7 @@ SECTIONS
     PROVIDE_HIDDEN (__init_array_end = .);
     . = ALIGN(4);
   } >ROM
-  
+
   .fini_array :
   {
     . = ALIGN(4);
@@ -149,7 +149,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections into "RAM" Ram type memory */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -158,7 +158,7 @@ SECTIONS
 
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
-    
+
   } >RAM AT> ROM
 
   /* Uninitialized data section into "RAM" Ram type memory */
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
index 1df389aed..47ada6bb9 100644
--- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
index f77c72d1b..267a87a8b 100644
--- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/STM32L4RXxI_FLASH.ld
@@ -114,7 +114,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -125,7 +125,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -153,7 +153,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
index 1df389aed..47ada6bb9 100644
--- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32l4/stm32l4xx_hal_conf.h b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h
index 312f86da1..25dbc0523 100644
--- a/hw/bsp/stm32l4/stm32l4xx_hal_conf.h
+++ b/hw/bsp/stm32l4/stm32l4xx_hal_conf.h
@@ -50,7 +50,7 @@
 /* #define HAL_NAND_MODULE_ENABLED */
 // #define HAL_NOR_MODULE_ENABLED
 // #define HAL_SRAM_MODULE_ENABLED
-/* #define HAL_HCD_MODULE_ENABLED */ 
+/* #define HAL_HCD_MODULE_ENABLED */
 #define HAL_GPIO_MODULE_ENABLED
 //#define HAL_I2C_MODULE_ENABLED
 /* #define HAL_IRDA_MODULE_ENABLED */
@@ -115,7 +115,7 @@
   *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
   *        which is subject to manufacturing process variations.
   */
-#if !defined  (HSI48_VALUE) 
+#if !defined  (HSI48_VALUE)
  #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
                                               The real value my vary depending on manufacturing process variations.*/
 #endif /* HSI48_VALUE */
@@ -123,7 +123,7 @@
 /**
   * @brief Internal Low Speed oscillator (LSI) value.
   */
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
  #define LSI_VALUE  32000U                 /*!< LSI Typical Value in Hz*/
 #endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
                                              The real value may vary depending on the variations
@@ -142,7 +142,7 @@
 
 /**
   * @brief External clock source for SAI1 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
   *        frequency.
   */
 #if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)
@@ -151,7 +151,7 @@
 
 /**
   * @brief External clock source for SAI2 peripheral
-  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source 
+  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
   *        frequency.
   */
 #if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)
diff --git a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
index 15dffa813..87c3683de 100644
--- a/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
+++ b/hw/bsp/stm32u5/stm32u5xx_hal_conf.h
@@ -503,4 +503,3 @@
 #endif
 
 #endif /* STM32U5xx_HAL_CONF_H */
-
diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
index 660f30161..916f11866 100644
--- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
+++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/stm32wb55xx_flash_cm4.ld
@@ -113,7 +113,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -124,7 +124,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM1 AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -152,7 +152,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM1
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -167,5 +167,3 @@ SECTIONS
    MB_MEM1 (NOLOAD)       : { *(MB_MEM1) } >RAM_SHARED
    MB_MEM2 (NOLOAD)       : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
 }
-
-
diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c
index 525d637ea..e9ca59866 100644
--- a/hw/bsp/stm32wb/family.c
+++ b/hw/bsp/stm32wb/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2022 Jerzy Kasenberg
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
index d60365d1d..0ff24ab60 100644
--- a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
+++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
@@ -1,5 +1,5 @@
 CFLAGS += -DTM4C123GH6PM
- 
+
 LD_FILE = $(BOARD_PATH)/tm4c123.ld
 
 # For flash-jlink target
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld
index e2720a9ac..351857bd6 100644
--- a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld
+++ b/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld
@@ -6,37 +6,37 @@ _Min_Heap_Size = 0;      /* required amount of heap  */
 _Min_Stack_Size = 0x1000; /* required amount of stack */
 
 
-MEMORY 
+MEMORY
 {
     FLASH(rx) : ORIGIN = 0x00000000, LENGTH = 256K
     SRAM(rwx) : ORIGIN = 0x20000000, LENGTH = 32K
 }
 
-SECTIONS 
+SECTIONS
 {
-    .text : 
+    .text :
     {
         . = ALIGN(4) ;
-        *(.vectors) 
-        *(.text) 
+        *(.vectors)
+        *(.text)
         *(.text.*)
         *(.init)
         *(.fini)
         *(.rodata)
         *(.rodata.*)
-        . = ALIGN(4) ; 
-        __end_text = . ; 
+        . = ALIGN(4) ;
+        __end_text = . ;
     } >FLASH
-    
+
     .data : AT(ADDR(.text) + SIZEOF(.text))
     {
         . = ALIGN(4);
-        __start_data = . ; 
+        __start_data = . ;
         __la_data = LOADADDR(.data);
-        *(.data) 
+        *(.data)
         *(.data.*)
         . = ALIGN(4);
-        __end_data = . ; 
+        __end_data = . ;
 
     } >SRAM
 
@@ -47,7 +47,7 @@ SECTIONS
         __bss_start__ = __start_bss;
         *(.bss)
         *(.bss.*)
-        *(.COMMON) 
+        *(.COMMON)
         __end_bss = . ;
         . = ALIGN(4);
     }>SRAM
diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c
index 87b94289b..3f4f43220 100644
--- a/hw/bsp/tm4c123/family.c
+++ b/hw/bsp/tm4c123/family.c
@@ -175,4 +175,3 @@ uint32_t board_millis (void)
   return system_ticks;
 }
 #endif
-
diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h
index 3e2cb9583..2d4764f40 100644
--- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h
+++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/hw/mcu/bridgetek/ft9xx/Readme.md b/hw/mcu/bridgetek/ft9xx/Readme.md
index 1db91058c..adf8fc765 100644
--- a/hw/mcu/bridgetek/ft9xx/Readme.md
+++ b/hw/mcu/bridgetek/ft9xx/Readme.md
@@ -2,6 +2,6 @@
 
 **BridgeTek** provides a hardware abstraction library with software source code for the SDKs for FT9xx software family.
 
-Whole SDK repository is installed as part of the FT9xx Toolchain and can be downloaded from BridgeTek web page `https://www.brtchip.com`. 
+Whole SDK repository is installed as part of the FT9xx Toolchain and can be downloaded from BridgeTek web page `https://www.brtchip.com`.
 
-Registers definition files, and included peripheral register definition files have licenses that allow for redistribution.  
+Registers definition files, and included peripheral register definition files have licenses that allow for redistribution.
diff --git a/hw/mcu/bridgetek/ft9xx/scripts/crt0.S b/hw/mcu/bridgetek/ft9xx/scripts/crt0.S
index 62fa266ee..380b31c37 100644
--- a/hw/mcu/bridgetek/ft9xx/scripts/crt0.S
+++ b/hw/mcu/bridgetek/ft9xx/scripts/crt0.S
@@ -50,11 +50,11 @@ _start:
 
 codestart:
         jmp    init
-        
+
 .global _exithook
 _exithook:               # Debugger uses '_exithook' at 0x90 to catch program exit
         return
-        
+
 init:
         # Disable all interrupts
         ldk     $r0,0x80
@@ -63,12 +63,12 @@ init:
 .else
         sta.b   0x100e3,$r0
 .endif
-        
+
         # Reset all peripherals
         # lda.l   $r0, 0x10018
         # bins.l  $r0, $r0, 0x23F  # Set bit 31
         # sta.l   0x10018, $r0
-        
+
         # Initialize DATA by copying from program memory
         ldk.l   $r0,__data_load_start
         ldk.l   $r1,__data_load_end
diff --git a/hw/mcu/dialog/README.md b/hw/mcu/dialog/README.md
index 69676f081..33d270aac 100644
--- a/hw/mcu/dialog/README.md
+++ b/hw/mcu/dialog/README.md
@@ -3,7 +3,5 @@
 **Dialog Semiconductors** provides SDKs for DA146x MCU family.
 Most of the files there can't be redistributed.
 Registers definition file `DA1469xAB.h` and some **ARM** originated headers are have licenses that allow
-for redistribution.  
+for redistribution.
 Whole SDK repository can be downloaded from Dialog Semiconductor web page `https://www.dialog.com`
-
-
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt
index b324eb286..7e8067a6f 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/arm_license.txt
@@ -24,4 +24,3 @@
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
    ---------------------------------------------------------------------------*/
-
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h
index fdb1a971c..8f871ea31 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_compiler.h
@@ -268,4 +268,3 @@
 
 
 #endif /* __CMSIS_COMPILER_H */
-
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h
index 47a4b59d8..812c3789a 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/cmsis_gcc.h
@@ -47,9 +47,9 @@
 #ifndef   __STATIC_INLINE
   #define __STATIC_INLINE                        static inline
 #endif
-#ifndef   __STATIC_FORCEINLINE                 
+#ifndef   __STATIC_FORCEINLINE
   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
-#endif                                           
+#endif
 #ifndef   __NO_RETURN
   #define __NO_RETURN                            __attribute__((__noreturn__))
 #endif
@@ -586,7 +586,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence zero is returned always in non-secure
   mode.
-  
+
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
  */
@@ -631,7 +631,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
   Stack Pointer Limit register hence the write is silently ignored in non-secure
   mode.
-  
+
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
  */
@@ -768,7 +768,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
 {
 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_get_fpscr) 
+#if __has_builtin(__builtin_arm_get_fpscr)
 // Re-enable using built-in when GCC has been fixed
 // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h
index e2cf6b966..a8cd3ea45 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm0.h
@@ -62,7 +62,7 @@
  */
 
 #include "cmsis_version.h"
- 
+
 /*  CMSIS CM0 definitions */
 #define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
 #define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h
index 7249e1331..05b61383e 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/core_cm33.h
@@ -2065,7 +2065,7 @@ typedef struct
 
 /* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
 
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
 #define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
 
 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
@@ -2080,7 +2080,7 @@ typedef struct
 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
 #define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
-#else 
+#else
 #define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
 #endif
 
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h
index bc3b05109..50bb56333 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/mpu_armv8.h
@@ -103,7 +103,7 @@
   (MPU_RLAR_EN_Msk))
 
 #if defined(MPU_RLAR_PXN_Pos)
-  
+
 /** \brief Region Limit Address Register with PXN value
 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
 * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
@@ -114,7 +114,7 @@
   ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
   ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
   (MPU_RLAR_EN_Msk))
-  
+
 #endif
 
 /**
@@ -124,7 +124,7 @@ typedef struct {
   uint32_t RBAR;                   /*!< Region Base Address Register value */
   uint32_t RLAR;                   /*!< Region Limit Address Register value */
 } ARM_MPU_Region_t;
-    
+
 /** Enable the MPU.
 * \param MPU_Control Default access permissions for unconfigured regions.
 */
@@ -185,11 +185,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at
   const uint8_t reg = idx / 4U;
   const uint32_t pos = ((idx % 4U) * 8U);
   const uint32_t mask = 0xFFU << pos;
-  
+
   if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
     return; // invalid index
   }
-  
+
   mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
 }
 
@@ -236,7 +236,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
 * \param rnr Region number to be cleared.
 */
 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
-{  
+{
   ARM_MPU_ClrRegionEx(MPU_NS, rnr);
 }
 #endif
@@ -246,7 +246,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
   mpu->RNR = rnr;
@@ -258,7 +258,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
   ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
@@ -269,10 +269,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla
 * \param rnr Region number to be configured.
 * \param rbar Value for RBAR register.
 * \param rlar Value for RLAR register.
-*/   
+*/
 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
 {
-  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
 }
 #endif
 
@@ -284,7 +284,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
 __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
   uint32_t i;
-  for (i = 0U; i < len; ++i) 
+  for (i = 0U; i < len; ++i)
   {
     dst[i] = src[i];
   }
@@ -296,7 +296,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
   if (cnt == 1U) {
@@ -305,7 +305,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
   } else {
     uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
     uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
-    
+
     mpu->RNR = rnrBase;
     while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
       uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
@@ -316,7 +316,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
       rnrBase += MPU_TYPE_RALIASES;
       mpu->RNR = rnrBase;
     }
-    
+
     ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
   }
 }
@@ -326,7 +326,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   ARM_MPU_LoadEx(MPU, rnr, table, cnt);
 }
@@ -337,11 +337,10 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u
 * \param table Pointer to the MPU configuration table.
 * \param cnt Amount of regions to be configured.
 */
-__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
 {
   ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
 }
 #endif
 
 #endif
-
diff --git a/hw/mcu/dialog/da1469x/da1469x.ld b/hw/mcu/dialog/da1469x/da1469x.ld
index c91dea841..0133f3759 100644
--- a/hw/mcu/dialog/da1469x/da1469x.ld
+++ b/hw/mcu/dialog/da1469x/da1469x.ld
@@ -225,4 +225,3 @@ SECTIONS
     /* Check that intvect is at the beginning of RAM */
     ASSERT(__intvect_start__ == ORIGIN(RAM), "intvect is not at beginning of RAM")
 }
-
diff --git a/hw/mcu/dialog/da1469x/include/mcu/mcu.h b/hw/mcu/dialog/da1469x/include/mcu/mcu.h
index 1e6736785..38961e828 100644
--- a/hw/mcu/dialog/da1469x/include/mcu/mcu.h
+++ b/hw/mcu/dialog/da1469x/include/mcu/mcu.h
@@ -162,4 +162,3 @@ void mcu_gpio_exit_sleep(void);
 #endif
 
 #endif /* __MCU_MCU_H_ */
-
diff --git a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h
index 76a432bfd..9ba24f458 100644
--- a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h
+++ b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble.h
@@ -539,7 +539,7 @@ SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_v
 
 
 /**@brief Remove a Vendor Specific base UUID.
- * 
+ *
  * @details This call removes a Vendor Specific base UUID that has been added with @ref sd_ble_uuid_vs_add. This function allows
  * the application to reuse memory allocated for Vendor Specific base UUIDs.
  *
diff --git a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h
index c434fefb3..e11149435 100644
--- a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h
+++ b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_gap.h
@@ -1666,7 +1666,7 @@ SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr
  *
  * @retval ::NRF_SUCCESS                  Address successfully retrieved.
  * @retval ::NRF_ERROR_INVALID_ADDR       Invalid or NULL pointer supplied.
- * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found. 
+ * @retval ::BLE_ERROR_INVALID_ADV_HANDLE The provided advertising handle was not found.
  * @retval ::NRF_ERROR_INVALID_STATE      The advertising set is currently not advertising.
  */
 SVCALL(SD_BLE_GAP_ADV_ADDR_GET, uint32_t, sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr));
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
index a7ae013dd..c8de8e0f3 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
@@ -62,7 +62,7 @@ Additional information:
           WrOff == (RdOff - 1): Buffer is full
           WrOff >  RdOff:       Free space includes wrap-around
           WrOff <  RdOff:       Used space includes wrap-around
-          (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0):  
+          (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0):
                                 Buffer full and wrap-around after next byte
 
 
@@ -504,7 +504,7 @@ static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) {
 *    Reads characters from SEGGER real-time-terminal control block
 *    which have been previously stored by the application.
 *    Do not lock against interrupts and multiple access.
-*    Used to do the same operation that J-Link does, to transfer 
+*    Used to do the same operation that J-Link does, to transfer
 *    RTT data via other channels, such as TCP/IP or UART.
 *
 *  Parameters
@@ -693,7 +693,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
 *  Function description
 *    Reads characters from SEGGER real-time-terminal control block
 *    which have been previously stored by the application.
-*    Used to do the same operation that J-Link does, to transfer 
+*    Used to do the same operation that J-Link does, to transfer
 *    RTT data via other channels, such as TCP/IP or UART.
 *
 *  Parameters
@@ -708,7 +708,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
 *    This function must not be called when J-Link might also do RTT.
 *    This function locks against all other RTT operations. I.e. during
 *    the read operation, writing is also locked.
-*    If only one consumer reads from the up buffer, 
+*    If only one consumer reads from the up buffer,
 *    call sEGGER_RTT_ReadUpBufferNoLock() instead.
 */
 unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) {
@@ -766,7 +766,7 @@ unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSiz
 *  Function description
 *    Stores a specified number of characters in SEGGER RTT
 *    control block.
-*    SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application 
+*    SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application
 *    and overwrites data if the data does not fit into the buffer.
 *
 *  Parameters
@@ -779,7 +779,7 @@ unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSiz
 *    (2) For performance reasons this function does not call Init()
 *        and may only be called after RTT has been initialized.
 *        Either by calling SEGGER_RTT_Init() or calling another RTT API function first.
-*    (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link 
+*    (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link
 *        connection reads RTT data.
 */
 void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
@@ -946,7 +946,7 @@ CopyStraight:
 *    Stores a specified number of characters in SEGGER RTT
 *    control block inside a <Down> buffer.
 *    SEGGER_RTT_WriteDownBufferNoLock does not lock the application.
-*    Used to do the same operation that J-Link does, to transfer 
+*    Used to do the same operation that J-Link does, to transfer
 *    RTT data from other channels, such as TCP/IP or UART.
 *
 *  Parameters
@@ -1116,7 +1116,7 @@ unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsig
 *    This function must not be called when J-Link might also do RTT.
 *    This function locks against all other RTT operations. I.e. during
 *    the write operation, writing from the application is also locked.
-*    If only one consumer writes to the down buffer, 
+*    If only one consumer writes to the down buffer,
 *    call SEGGER_RTT_WriteDownBufferNoLock() instead.
 */
 unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.h b/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
index 3c04df55f..07eb4f39e 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
@@ -44,7 +44,7 @@
 ---------------------------END-OF-HEADER------------------------------
 File    : SEGGER_RTT.h
 Purpose : Implementation of SEGGER real-time transfer which allows
-          real-time communication on targets which support debugger 
+          real-time communication on targets which support debugger
           memory accesses while the CPU is running.
 Revision: $Rev: 17697 $
 ----------------------------------------------------------------------
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S b/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S
index 78cde4d75..aec372eec 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S
@@ -36,9 +36,9 @@ Additional information:
   #define _THUMB_CODE          .code 16
   #define _WORD                .word
   #define _SECTION(Sect, Type, AlignExp) .section Sect ##, "ax"
-  #define _ALIGN(Exp)          .align Exp 
+  #define _ALIGN(Exp)          .align Exp
   #define _PLACE_LITS          .ltorg
-  #define _DATA_SECT_START 
+  #define _DATA_SECT_START
   #define _C_STARTUP           _start
   #define _STACK_END           __stack_end__
   #define _RAMFUNC
@@ -58,7 +58,7 @@ Additional information:
   #define _THUMB_CODE          THUMB
   #define _WORD                DCD
   #define _SECTION(Sect, Type, AlignExp) SECTION Sect ## : ## Type ## :REORDER:NOROOT ## (AlignExp)
-  #define _ALIGN(Exp)          alignrom Exp 
+  #define _ALIGN(Exp)          alignrom Exp
   #define _PLACE_LITS
   #define _DATA_SECT_START     DATA
   #define _C_STARTUP           __iar_program_start
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h b/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h
index 5e79d7e67..fda5a5f51 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h
@@ -91,12 +91,12 @@ Revision: $Rev: 18601 $
 *
 *       RTT memcpy configuration
 *
-*       memcpy() is good for large amounts of data, 
+*       memcpy() is good for large amounts of data,
 *       but the overhead is big for small amounts, which are usually stored via RTT.
 *       With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead.
 *
 *       SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions.
-*       This is may be required with memory access restrictions, 
+*       This is may be required with memory access restrictions,
 *       such as on Cortex-A devices with MMU.
 */
 #ifndef   SEGGER_RTT_MEMCPY_USE_BYTELOOP
@@ -105,7 +105,7 @@ Revision: $Rev: 18601 $
 //
 // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets
 //
-//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))  
+//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))
 //  #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes)      SEGGER_memcpy((pDest), (pSrc), (NumBytes))
 //#endif
 
@@ -204,7 +204,7 @@ Revision: $Rev: 18601 $
                                                  :                             \
                                                  :                             \
                                                 );
-                               
+
   #define SEGGER_RTT_UNLOCK()    __asm volatile ("csrr  a1, mstatus  \n\t"     \
                                                  "or    %0, %0, a1   \n\t"     \
                                                  "csrs  mstatus, %0  \n\t"     \
@@ -345,8 +345,8 @@ Revision: $Rev: 18601 $
   #define SEGGER_RTT_LOCK()   {                                                                     \
                                 unsigned long LockState;                                            \
                                 LockState = get_psw() & 0x010000;                                   \
-                                clrpsw_i();                           
-                                    
+                                clrpsw_i();
+
   #define SEGGER_RTT_UNLOCK()   set_psw(get_psw() | LockState);                                     \
                               }
 #endif
diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c
index da4a4b5f5..6bf670a02 100644
--- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c
+++ b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c
@@ -44,7 +44,7 @@
 ---------------------------END-OF-HEADER------------------------------
 File    : SEGGER_RTT_Syscalls_GCC.c
 Purpose : Low-level functions for using printf() via RTT in GCC.
-          To use RTT for printf output, include this file in your 
+          To use RTT for printf output, include this file in your
           application.
 Revision: $Rev: 17697 $
 ----------------------------------------------------------------------
@@ -62,7 +62,7 @@ Revision: $Rev: 17697 $
 **********************************************************************
 */
 //
-// If necessary define the _reent struct 
+// If necessary define the _reent struct
 // to match the one passed by the used standard library.
 //
 struct _reent;
diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c
index f7f5aed48..ba9772d3e 100644
--- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c
+++ b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c
@@ -110,7 +110,7 @@ const char __stderr_name[] = "STDERR";
 *
 *  Parameters:
 *    c    - character to output
-*  
+*
 */
 void _ttywrch(int c) {
   fputc(c, stdout); // stdout
@@ -127,9 +127,9 @@ void _ttywrch(int c) {
 *  Parameters:
 *    sName        - sName of the device/file to open
 *    OpenMode    - This parameter is currently ignored
-*  
+*
 *  Return value:
-*    != 0     - Handle to the object to open, otherwise 
+*    != 0     - Handle to the object to open, otherwise
 *    == 0     -"device" is not handled by this module
 *
 */
@@ -153,7 +153,7 @@ FILEHANDLE _sys_open(const char * sName, int OpenMode) {
 *
 *  Parameters:
 *    hFile    - Handle to a file opened via _sys_open
-*  
+*
 *  Return value:
 *    0     - device/file closed
 *
@@ -176,7 +176,7 @@ int _sys_close(FILEHANDLE hFile) {
 *    pBuffer  - Pointer to the data that shall be written
 *    NumBytes      - Number of bytes to write
 *    Mode     - The Mode that shall be used
-*  
+*
 *  Return value:
 *    Number of bytes *not* written to the file/device
 *
@@ -205,7 +205,7 @@ int _sys_write(FILEHANDLE hFile, const unsigned char * pBuffer, unsigned NumByte
 *    pBuffer  - Pointer to buffer to store the read data
 *    NumBytes      - Number of bytes to read
 *    Mode     - The Mode that shall be used
-*  
+*
 *  Return value:
 *    Number of bytes read from the file/device
 *
@@ -223,12 +223,12 @@ int _sys_read(FILEHANDLE hFile, unsigned char * pBuffer, unsigned NumBytes, int
 *       _sys_istty
 *
 *  Function description:
-*    This function shall return whether the opened file 
+*    This function shall return whether the opened file
 *    is a console device or not.
 *
 *  Parameters:
 *    hFile    - Handle to a file opened via _sys_open
-*  
+*
 *  Return value:
 *    1       - Device is     a console
 *    0       - Device is not a console
@@ -250,10 +250,10 @@ int _sys_istty(FILEHANDLE hFile) {
 *
 *  Parameters:
 *    hFile  - Handle to a file opened via _sys_open
-*    Pos    - 
-*  
+*    Pos    -
+*
 *  Return value:
-*    int       - 
+*    int       -
 *
 */
 int _sys_seek(FILEHANDLE hFile, long Pos) {
@@ -267,13 +267,13 @@ int _sys_seek(FILEHANDLE hFile, long Pos) {
 *       _sys_ensure
 *
 *  Function description:
-*    
+*
 *
 *  Parameters:
 *    hFile    - Handle to a file opened via _sys_open
-*  
+*
 *  Return value:
-*    int       - 
+*    int       -
 *
 */
 int _sys_ensure(FILEHANDLE hFile) {
@@ -290,7 +290,7 @@ int _sys_ensure(FILEHANDLE hFile) {
 *
 *  Parameters:
 *    hFile    - Handle to a file opened via _sys_open
-*  
+*
 *  Return value:
 *    Length of the file
 *
@@ -305,17 +305,17 @@ long _sys_flen(FILEHANDLE hFile) {
 *       _sys_tmpnam
 *
 *  Function description:
-*    This function converts the file number fileno for a temporary 
+*    This function converts the file number fileno for a temporary
 *    file to a unique filename, for example, tmp0001.
 *
 *  Parameters:
 *    pBuffer    - Pointer to a buffer to store the name
 *    FileNum    - file number to convert
 *    MaxLen     - Size of the buffer
-*  
+*
 *  Return value:
 *     1 - Error
-*     0 - Success  
+*     0 - Success
 *
 */
 int _sys_tmpnam(char * pBuffer, int FileNum, unsigned MaxLen) {
@@ -335,7 +335,7 @@ int _sys_tmpnam(char * pBuffer, int FileNum, unsigned MaxLen) {
 *  Parameters:
 *    cmd    - Pointer to the command string
 *    len    - Length of the string
-*  
+*
 *  Return value:
 *    == NULL - Command was not successfully executed
 *    == sCmd - Command was passed successfully
@@ -355,7 +355,7 @@ char * _sys_command_string(char * cmd, int len) {
 *
 *  Parameters:
 *    ReturnCode    - Return code from the main function
-*  
+*
 *
 */
 void _sys_exit(int ReturnCode) {
@@ -373,7 +373,7 @@ void _sys_exit(int ReturnCode) {
 *
 *  Parameters:
 *    ch    - Character to output
-*  
+*
 *
 */
 int stdout_putchar(int ch) {
diff --git a/lib/fatfs/source/00history.txt b/lib/fatfs/source/00history.txt
index 7a153a229..f7898cbd9 100644
--- a/lib/fatfs/source/00history.txt
+++ b/lib/fatfs/source/00history.txt
@@ -366,4 +366,3 @@ R0.15 (November 6, 2022)
   Fixed f_mkfs() creates broken exFAT volume when the size of volume is >= 2^32 sectors.
   Fixed string functions cannot write the unicode characters not in BMP when FF_LFN_UNICODE == 2 (UTF-8).
   Fixed a compatibility issue in identification of GPT header.
-
diff --git a/lib/fatfs/source/00readme.txt b/lib/fatfs/source/00readme.txt
index 3de3aeaa2..48c02a42d 100644
--- a/lib/fatfs/source/00readme.txt
+++ b/lib/fatfs/source/00readme.txt
@@ -18,4 +18,3 @@ FILES
   module is only a generic file system layer and it does not depend on any specific
   storage device. You need to provide a low level disk I/O module written to
   control the storage device that attached to the target system.
-
diff --git a/lib/fatfs/source/diskio.c b/lib/fatfs/source/diskio.c
index 179e387a2..3cb423db3 100644
--- a/lib/fatfs/source/diskio.c
+++ b/lib/fatfs/source/diskio.c
@@ -226,4 +226,3 @@ DRESULT disk_ioctl (
 
 	return RES_PARERR;
 }
-
diff --git a/lib/fatfs/source/ff.c b/lib/fatfs/source/ff.c
index 6d412fa0e..05ca02f0a 100644
--- a/lib/fatfs/source/ff.c
+++ b/lib/fatfs/source/ff.c
@@ -7081,4 +7081,3 @@ FRESULT f_setcp (
 	return FR_OK;
 }
 #endif	/* FF_CODE_PAGE == 0 */
-
diff --git a/lib/fatfs/source/ffsystem.c b/lib/fatfs/source/ffsystem.c
index d5c5134bf..bc0047dce 100644
--- a/lib/fatfs/source/ffsystem.c
+++ b/lib/fatfs/source/ffsystem.c
@@ -205,4 +205,3 @@ void ff_mutex_give (
 }
 
 #endif	/* FF_FS_REENTRANT */
-
diff --git a/lib/networking/dhserver.c b/lib/networking/dhserver.c
index 8cd22ddb9..2f14f7a09 100644
--- a/lib/networking/dhserver.c
+++ b/lib/networking/dhserver.c
@@ -2,17 +2,17 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2015 by Sergey Fetisov <fsenok@gmail.com>
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice shall be included in all
  * copies or substantial portions of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@@ -267,7 +267,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const
 				DHCP_OFFER,
 				config->domain,
 				config->dns,
-				entry->lease, 
+				entry->lease,
 				*netif_ip4_addr(netif),
 				config->router,
 				*netif_ip4_netmask(netif));
@@ -309,7 +309,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const
 				DHCP_ACK,
 				config->domain,
 				config->dns,
-				entry->lease, 
+				entry->lease,
 				*netif_ip4_addr(netif),
 				config->router,
 				*netif_ip4_netmask(netif));
diff --git a/lib/networking/dhserver.h b/lib/networking/dhserver.h
index 2a0b15854..b3642459a 100644
--- a/lib/networking/dhserver.h
+++ b/lib/networking/dhserver.h
@@ -2,17 +2,17 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2015 by Sergey Fetisov <fsenok@gmail.com>
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice shall be included in all
  * copies or substantial portions of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
diff --git a/lib/networking/dnserver.c b/lib/networking/dnserver.c
index 539cc2cea..6d15fee02 100644
--- a/lib/networking/dnserver.c
+++ b/lib/networking/dnserver.c
@@ -2,17 +2,17 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2015 by Sergey Fetisov <fsenok@gmail.com>
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice shall be included in all
  * copies or substantial portions of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@@ -165,7 +165,7 @@ static void udp_recv_proc(void *arg, struct udp_pcb *upcb, struct pbuf *p, const
 	answer->ttl = htonl(32);
 	answer->len = htons(4);
 	answer->addr = host_addr.addr;
-	
+
 	udp_sendto(upcb, out, addr, port);
 	pbuf_free(out);
 
diff --git a/lib/networking/dnserver.h b/lib/networking/dnserver.h
index a062e3aa7..50b29be89 100644
--- a/lib/networking/dnserver.h
+++ b/lib/networking/dnserver.h
@@ -2,17 +2,17 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2015 by Sergey Fetisov <fsenok@gmail.com>
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice shall be included in all
  * copies or substantial portions of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
diff --git a/lib/networking/ndis.h b/lib/networking/ndis.h
index 06258e6bb..29b07749c 100644
--- a/lib/networking/ndis.h
+++ b/lib/networking/ndis.h
@@ -16,14 +16,14 @@
  */
 
 /*
- * ndis.h 
- * 
+ * ndis.h
+ *
  * Modified by Colin O'Flynn <coflynn@newae.com>
  * ntddndis.h modified by Benedikt Spranger <b.spranger@pengutronix.de>
- * 
- * Thanks to the cygwin development team, 
+ *
+ * Thanks to the cygwin development team,
  * especially to Casper S. Hornstrup <chorns@users.sourceforge.net>
- * 
+ *
  * THIS SOFTWARE IS NOT COPYRIGHTED
  *
  * This source code is offered for use in the public domain. You may
diff --git a/lib/networking/rndis_protocol.h b/lib/networking/rndis_protocol.h
index b45860eeb..3d07d6fa3 100644
--- a/lib/networking/rndis_protocol.h
+++ b/lib/networking/rndis_protocol.h
@@ -39,7 +39,7 @@
 #ifndef _RNDIS_H
 #define _RNDIS_H
 
-/** 
+/**
   \addtogroup RNDIS
   @{
   */
@@ -112,7 +112,7 @@ typedef struct{
 	rndis_MinorVersion_t	MinorVersion;
 	rndis_MaxTransferSize_t	MaxTransferSize;
 	} rndis_initialize_msg_t;
-	
+
 /* Response: */
 typedef struct{
 	rndis_MessageType_t		MessageType;
@@ -129,7 +129,7 @@ typedef struct{
 	rndis_AfListOffset_t	AfListOffset;
 	rndis_AfListSize_t		AfListSize;
 	} rndis_initialize_cmplt_t;
-	
+
 
 /*** Remote NDIS Halt Message ***/
 typedef struct{
@@ -137,7 +137,7 @@ typedef struct{
 	rndis_MessageLength_t	MessageLength;
 	rndis_RequestId_t		RequestId;
 	} rndis_halt_msg_t;
-	
+
 typedef uint32_t rndis_Oid_t;
 typedef uint32_t rndis_InformationBufferLength_t;
 typedef uint32_t rndis_InformationBufferOffset_t;
@@ -153,7 +153,7 @@ typedef struct{
 	rndis_InformationBufferOffset_t	InformationBufferOffset;
 	rndis_DeviceVcHandle_t			DeviceVcHandle;
 	}  rndis_query_msg_t;
-	
+
 /* Response: */
 
 typedef struct{
@@ -164,7 +164,7 @@ typedef struct{
 	rndis_InformationBufferLength_t	InformationBufferLength;
 	rndis_InformationBufferOffset_t	InformationBufferOffset;
 	} rndis_query_cmplt_t;
-	
+
 /*** Remote NDIS Set Message ***/
 typedef struct{
 	rndis_MessageType_t		MessageType;
@@ -175,7 +175,7 @@ typedef struct{
 	rndis_InformationBufferOffset_t	InformationBufferOffset;
 	rndis_DeviceVcHandle_t			DeviceVcHandle;
 	} rndis_set_msg_t;
-	
+
 /* Response */
 typedef struct{
 	rndis_MessageType_t		MessageType;
@@ -199,9 +199,9 @@ typedef struct{
 	rndis_ParameterNameLength_t		ParameterNameLength;
 	rndis_ParameterType_t			ParameterType;
 	rndis_ParameterValueOffset_t	ParameterValueOffset;
-	rndis_ParameterValueLength_t	ParameterValueLength;	
+	rndis_ParameterValueLength_t	ParameterValueLength;
 	}rndis_config_parameter_t;
-	
+
 typedef uint32_t rndis_Reserved_t;
 
 /*** Remote NDIS Soft Reset Message ***/
@@ -210,7 +210,7 @@ typedef struct{
 	rndis_MessageLength_t	MessageLength;
 	rndis_Reserved_t		Reserved;
 	} rndis_reset_msg_t;
-	
+
 typedef uint32_t rndis_AddressingReset_t;
 
 /* Response: */
@@ -220,7 +220,7 @@ typedef struct{
 	rndis_Status_t			Status;
 	rndis_AddressingReset_t	AddressingReset;
 	}  rndis_reset_cmplt_t;
-	
+
 /*** Remote NDIS Indicate Status Message ***/
 typedef struct{
 	rndis_MessageType_t		MessageType;
@@ -229,7 +229,7 @@ typedef struct{
 	rndis_Status_t			StatusBufferLength;
 	rndis_Status_t			StatusBufferOffset;
 	}  rndis_indicate_status_t;
-	
+
 typedef uint32_t rndis_DiagStatus_t;
 typedef uint32_t rndis_ErrorOffset_t;
 
@@ -237,14 +237,14 @@ typedef struct {
 	rndis_DiagStatus_t		DiagStatus;
 	rndis_ErrorOffset_t		ErrorOffset;
 	}rndis_diagnostic_info_t;
-	
+
 /*** Remote NDIS Keepalive Message */
 typedef struct{
 	rndis_MessageType_t		MessageType;
 	rndis_MessageLength_t	MessageLength;
 	rndis_RequestId_t		RequestId;
 	}rndis_keepalive_msg_t;
-	
+
 /* Response: */
 typedef struct{
 	rndis_MessageType_t		MessageType;
diff --git a/lib/networking/rndis_reports.c b/lib/networking/rndis_reports.c
index d129466c8..cc14f174c 100644
--- a/lib/networking/rndis_reports.c
+++ b/lib/networking/rndis_reports.c
@@ -7,17 +7,17 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2015 by Sergey Fetisov <fsenok@gmail.com>
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights
  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice shall be included in all
  * copies or substantial portions of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@@ -45,7 +45,7 @@ static rndis_state_t rndis_state;
 
 CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t ndis_report[8] = { 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
 
-static const uint32_t OIDSupportedList[] = 
+static const uint32_t OIDSupportedList[] =
 {
   OID_GEN_SUPPORTED_LIST,
   OID_GEN_HARDWARE_STATUS,
@@ -203,8 +203,8 @@ static void rndis_handle_set_msg(void)
       {
         rndis_packetFilter(oid_packet_filter);
         rndis_state = rndis_data_initialized;
-      } 
-      else 
+      }
+      else
       {
         rndis_state = rndis_initialized;
       }
@@ -266,7 +266,7 @@ void rndis_class_set_handler(uint8_t *data, int size)
     case REMOTE_NDIS_QUERY_MSG:
       rndis_query();
       break;
-      
+
     case REMOTE_NDIS_SET_MSG:
       rndis_handle_set_msg();
       break;
diff --git a/src/class/audio/audio.h b/src/class/audio/audio.h
index ba497906b..70d431282 100644
--- a/src/class/audio/audio.h
+++ b/src/class/audio/audio.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -824,10 +824,10 @@ typedef struct TU_ATTR_PACKED
             uint8_t type      :  2; ///< Request type tusb_request_type_t.
             uint8_t direction :  1; ///< Direction type. tusb_dir_t
         } bmRequestType_bit;
-        
+
         uint8_t bmRequestType;
     };
-    
+
     uint8_t bRequest;  ///< Request type audio_cs_req_t
     uint8_t bChannelNumber;
     uint8_t bControlSelector;
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index f21dfee64..32ba5761e 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Reinhard Panhuber, Jerzy Kasenberg
@@ -1525,7 +1525,7 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   #endif
               }
             }
-            
+
           }
         }
         p_desc = tu_desc_next(p_desc);
@@ -2124,7 +2124,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3
     {
       if (tud_audio_fb_done_cb) tud_audio_fb_done_cb(func_id);
 
-      // Schedule a transmit with the new value if EP is not busy 
+      // Schedule a transmit with the new value if EP is not busy
       if (!usbd_edpt_busy(rhport, audio->ep_fb))
       {
         // Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 0ef100fa4..7c88b99fc 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Ha Thach (tinyusb.org)
@@ -473,7 +473,7 @@ TU_ATTR_WEAK void tud_audio_fb_done_cb(uint8_t func_id);
 // the choice of format is left to the caller and feedback argument is sent as-is. If CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION is set, then tinyusb
 // expects 16.16 format and handles the conversion to 10.14 on FS.
 //
-// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the 
+// Note that due to a bug in its USB Audio 2.0 driver, Windows currently requires 16.16 format for _all_ USB 2.0 devices. On Linux and macOS it seems the
 // driver can work with either format. So a good compromise is to keep format correction disabled and stick to 16.16 format.
 
 // Feedback value can be determined from within the SOF ISR of the audio driver. This should reduce jitter. If the feature is used, the user can not set the feedback value.
diff --git a/src/class/bth/bth_device.h b/src/class/bth/bth_device.h
index 1b90d0915..921bd7a1a 100755
--- a/src/class/bth/bth_device.h
+++ b/src/class/bth/bth_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Jerzy Kasenberg
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index f372fe462..a82ef1d62 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -386,7 +386,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         bool const rts = tu_bit_test(request->wValue, 1);
 
         p_cdc->line_state = (uint8_t) request->wValue;
-        
+
         // Disable fifo overwriting if DTR bit is set
         tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
 
@@ -433,7 +433,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
   if ( ep_addr == p_cdc->ep_out )
   {
     tu_fifo_write_n(&p_cdc->rx_ff, p_cdc->epout_buf, (uint16_t) xferred_bytes);
-    
+
     // Check for wanted char and invoke callback if needed
     if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) )
     {
@@ -445,14 +445,14 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_
         }
       }
     }
-    
+
     // invoke receive callback (if there is still data)
     if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff) ) tud_cdc_rx_cb(itf);
-    
+
     // prepare for OUT transaction
     _prep_out_transaction(p_cdc);
   }
-  
+
   // Data sent to host, we continue to fetch from tx fifo to send.
   // Note: This will cause incorrect baudrate set in line coding.
   //       Though maybe the baudrate is not really important !!!
diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h
index f8a004df4..a6e07aa5c 100644
--- a/src/class/cdc/cdc_device.h
+++ b/src/class/cdc/cdc_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index c759527e6..4090d0e9f 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/cdc/cdc_rndis.h b/src/class/cdc/cdc_rndis.h
index e0f129fe3..ad153e0ac 100644
--- a/src/class/cdc/cdc_rndis.h
+++ b/src/class/cdc/cdc_rndis.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c
index 44de85b45..41d21bbad 100644
--- a/src/class/cdc/cdc_rndis_host.c
+++ b/src/class/cdc/cdc_rndis_host.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/cdc/cdc_rndis_host.h b/src/class/cdc/cdc_rndis_host.h
index 447cc4e97..bb431ec1f 100644
--- a/src/class/cdc/cdc_rndis_host.h
+++ b/src/class/cdc/cdc_rndis_host.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h
index d9b0ead10..fbd3eef38 100644
--- a/src/class/hid/hid.h
+++ b/src/class/hid/hid.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/midi/midi.h b/src/class/midi/midi.h
index 74dc41749..8b78c6555 100644
--- a/src/class/midi/midi.h
+++ b/src/class/midi/midi.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index 5dea43431..e3e7826da 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/midi/midi_device.h b/src/class/midi/midi_device.h
index 211edc8d1..1c6f996be 100644
--- a/src/class/midi/midi_device.h
+++ b/src/class/midi/midi_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/msc/msc.h b/src/class/msc/msc.h
index 84b6e4d79..7f25a29ba 100644
--- a/src/class/msc/msc.h
+++ b/src/class/msc/msc.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h
index 5839b168d..72f95be06 100644
--- a/src/class/msc/msc_device.h
+++ b/src/class/msc/msc_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 6724e486c..2fddeb818 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -232,23 +232,23 @@ bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba,
 
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
- 
+
   cbw.total_bytes = block_count*p_msc->capacity[lun].block_size;
   cbw.dir         = TUSB_DIR_IN_MASK;
   cbw.cmd_len     = sizeof(scsi_read10_t);
- 
+
   scsi_read10_t const cmd_read10 =
   {
     .cmd_code    = SCSI_CMD_READ_10,
     .lba         = tu_htonl(lba),
     .block_count = tu_htons(block_count)
   };
- 
+
   memcpy(cbw.command, &cmd_read10, cbw.cmd_len);
- 
+
   return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb, arg);
 }
- 
+
 bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index 5134b63c2..6c0e5c9dd 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index a072bfd79..8ac7cbd01 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Peter Lawrence
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index aa13c9535..9e9580249 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -430,7 +430,7 @@ static void handle_incoming_datagram(uint32_t len)
   {
     ncm_interface.num_datagrams++;
   }
-  
+
   tud_network_recv_renew();
 }
 
diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index 6e294465b..133689deb 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Peter Lawrence
diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h
index fd52d766e..3c5e86d4c 100644
--- a/src/class/usbtmc/usbtmc.h
+++ b/src/class/usbtmc/usbtmc.h
@@ -316,4 +316,3 @@ typedef struct TU_ATTR_PACKED
 TU_VERIFY_STATIC(sizeof(usbtmc_read_stb_interrupt_488_t) == 2u, "struct wrong length");
 
 #endif
-
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index a4e6eaeb3..8dbda14c5 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -83,7 +83,7 @@ tu_static char logMsg[150];
 
 // Buffer size must be an exact multiple of the max packet size for both
 // bulk  (up to 64 bytes for FS, 512 bytes for HS). In addation, this driver
-// imposes a minimum buffer size of 32 bytes. 
+// imposes a minimum buffer size of 32 bytes.
 #define USBTMCD_BUFFER_SIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
 
 /*
@@ -598,7 +598,7 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
     uint32_t ep_addr = (request->wIndex);
 
     // At this point, a transfer MAY be in progress. Based on USB spec, when clearing bulk EP HALT,
-    // the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if 
+    // the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if
     // the EP is not halted. The only USBD API interface to do this is to stall and then un-stall the EP.
     if(ep_addr == usbtmc_state.ep_bulk_out)
     {
diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index 2bb6afa67..9abafda50 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/vendor/vendor_host.c b/src/class/vendor/vendor_host.c
index dbea1228d..e66c5007f 100644
--- a/src/class/vendor/vendor_host.c
+++ b/src/class/vendor/vendor_host.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/vendor/vendor_host.h b/src/class/vendor/vendor_host.h
index 65223fbca..acfebe7a4 100644
--- a/src/class/vendor/vendor_host.h
+++ b/src/class/vendor/vendor_host.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 02a490aee..d6e98602b 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji KITAYAMA
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 30478ba6d..1057d7ca3 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -239,7 +239,7 @@
   #define TU_BSWAP16(u16) ((unsigned short)_builtin_revw((unsigned long)u16))
   #define TU_BSWAP32(u32) (_builtin_revl(u32))
 
-#else 
+#else
   #error "Compiler attribute porting is required"
 #endif
 
diff --git a/src/common/tusb_timeout.h b/src/common/tusb_timeout.h
index ce53955f0..533e67ab8 100644
--- a/src/common/tusb_timeout.h
+++ b/src/common/tusb_timeout.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index a52a6d269..12355e8be 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 93170732f..00419ff05 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 7733cc2e2..0fb236a88 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -1398,11 +1398,11 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep
 
   uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(desc_ep->bEndpointAddress);
-  
+
   TU_ASSERT(dcd_edpt_iso_activate);
   TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX);
   TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
-  
+
   _usbd_dev.ep_status[epnum][dir].stalled = false;
   _usbd_dev.ep_status[epnum][dir].busy = false;
   _usbd_dev.ep_status[epnum][dir].claimed = false;
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index f860ab0a1..8393d3469 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/host/hcd.h b/src/host/hcd.h
index a400626e4..623c12a12 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/host/hub.c b/src/host/hub.c
index 3da5358b2..b84042fb6 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -202,7 +202,7 @@ bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf
 
   TU_ASSERT(TUSB_DESC_ENDPOINT  == desc_ep->bDescriptorType &&
             TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0);
-  
+
   TU_ASSERT(tuh_edpt_open(dev_addr, desc_ep));
 
   hub_interface_t* p_hub = get_itf(dev_addr);
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 37de7093c..7942de5c2 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/osal/osal.h b/src/osal/osal.h
index afa3826fc..f092e8ffb 100644
--- a/src/osal/osal.h
+++ b/src/osal/osal.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 9393d1f26..477f64892 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 2e2b3c7ce..5f407378e 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h
index 8b428d642..e6efa0968 100644
--- a/src/osal/osal_pico.h
+++ b/src/osal/osal_pico.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h
index dea1c12c8..e443135e0 100644
--- a/src/osal/osal_rtx4.h
+++ b/src/osal/osal_rtx4.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Tian Yunhao (t123yh)
@@ -115,7 +115,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
   os_mbx_declare(_name##__mbox, _depth);              \
   _declare_box(_name##__pool, sizeof(_type), _depth); \
   osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .pool = _name##__pool, .mbox = _name##__mbox };
-  
+
 
 typedef struct
 {
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index efca5bdcb..95dfda49c 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright 2021 Bridgetek Pte Ltd
@@ -24,15 +24,15 @@
  * This file is part of the TinyUSB stack.
  */
 
-/* 
- * Contains code adapted from Bridgetek Pte Ltd via license terms stated 
+/*
+ * Contains code adapted from Bridgetek Pte Ltd via license terms stated
  * in https://brtchip.com/BRTSourceCodeLicenseAgreement
  */
 
 #include "tusb_option.h"
 
 #if CFG_TUD_ENABLED && \
-  (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X) 
+  (CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X)
 
 #include <stdint.h>
 #include <ft900.h>
@@ -58,7 +58,7 @@ struct ft9xx_xfer_state
 {
   volatile uint8_t ready; // OUT Transfer has been received and waiting for transfer.
   volatile uint8_t valid; // Transfer is pending and total_size, remain_size, and buff_ptr are valid.
-  
+
   int16_t total_size; // Total transfer size in bytes for this transfer.
   int16_t remain_size; // Total remaining in transfer.
   uint8_t *buff_ptr; // Pointer to buffer to transmit from or receive to.
@@ -92,7 +92,7 @@ static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len
 
 // Manage an OUT transfer from the host.
 // This can be up-to the maximum packet size of the endpoint.
-// Continuation of a transfer beyond the maximum packet size is performed 
+// Continuation of a transfer beyond the maximum packet size is performed
 // by the interrupt handler.
 static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
 {
@@ -125,7 +125,7 @@ static uint16_t _ft9xx_edpt_xfer_out(uint8_t ep_number, uint8_t *buffer, uint16_
 
 // Manage an IN transfer to the host.
 // This can be up-to the maximum packet size of the endpoint.
-// Continuation of a transfer beyond the maximum packet size is performed 
+// Continuation of a transfer beyond the maximum packet size is performed
 // by the interrupt handler.
 static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t xfer_bytes)
 {
@@ -196,7 +196,7 @@ static uint16_t _ft9xx_edpt_xfer_in(uint8_t ep_number, uint8_t *buffer, uint16_t
   return xfer_bytes;
 }
 
-// Reset all non-control endpoints to a default state. 
+// Reset all non-control endpoints to a default state.
 // Control endpoint is always enabled and ready. All others disabled.
 static void _ft9xx_reset_edpts(void)
 {
@@ -208,7 +208,7 @@ static void _ft9xx_reset_edpts(void)
     // Disable hardware.
     USBD_EP_CR_REG(i) = 0;
   }
-  
+
   // Enable interrupts from USB device control.
   USBD_REG(cmie) = MASK_USBD_CMIE_ALL;
 }
@@ -319,7 +319,7 @@ static void _dcd_ft9xx_detach(void)
 }
 
 // Determine the speed of the USB to which we are connected.
-// Set the speed of the PHY accordingly. 
+// Set the speed of the PHY accordingly.
 // High speed can be disabled through CFG_TUSB_RHPORT0_MODE or CFG_TUD_MAX_SPEED settings.
 static void _ft9xx_usb_speed(void)
 {
@@ -379,16 +379,16 @@ static void _ft9xx_usb_speed(void)
 }
 
 // Send a buffer to the USB IN FIFO.
-// When the macro USBD_USE_STREAMS is defined this will stream a buffer of data 
+// When the macro USBD_USE_STREAMS is defined this will stream a buffer of data
 // to the FIFO using the most efficient MCU streamout combination.
-// If streaming is disabled then it will send each byte of the buffer in turn 
+// If streaming is disabled then it will send each byte of the buffer in turn
 // to the FIFO. The is no reason to not stream.
 // The total number of bytes sent to the FIFO is returned.
 static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_t length)
 {
   uint16_t bytes_read = 0;
   uint16_t buff_size = length;
-  
+
 #ifdef USBD_USE_STREAMS
   volatile uint8_t *data_reg;
 
@@ -423,7 +423,7 @@ static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_
     bytes_read = buff_size;
   }
 #else // USBD_USE_STREAMS
-  
+
   bytes_read = buff_size;
   while (buff_size--)
   {
@@ -438,7 +438,7 @@ static uint16_t _ft9xx_dusb_in(uint8_t ep_number, const uint8_t *buffer, uint16_
 // Receive a buffer from the USB OUT FIFO.
 // When the macro USBD_USE_STREAMS is defined this will stream from the FIFO
 // to a buffer of data using the most efficient MCU streamin combination.
-// If streaming is disabled then it will receive each byte from the FIFO in turn 
+// If streaming is disabled then it will receive each byte from the FIFO in turn
 // to the buffer. The is no reason to not stream.
 // The total number of bytes received from the FIFO is returned.
 static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t length)
@@ -448,7 +448,7 @@ static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len
 #endif // USBD_USE_STREAMS
   uint16_t bytes_read = 0;
   uint16_t buff_size = length;
-  
+
   if (length > 0)
   {
     if (ep_number == USBD_EP_0)
@@ -596,7 +596,7 @@ void dcd_remote_wakeup(uint8_t rhport)
   SYS->MSC0CFG = SYS->MSC0CFG | MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
 
   // At least 2 ms of delay needed for RESUME Data K state.
-  delayms(2); 
+  delayms(2);
 
   SYS->MSC0CFG &= ~MASK_SYS_MSC0CFG_DEV_RMWAKEUP;
 
@@ -621,7 +621,7 @@ void dcd_connect(uint8_t rhport)
     // Determine bus speed and signal speed to tusb.
     _ft9xx_usb_speed();
   }
-  
+
   // Setup the control endpoint only.
 #if CFG_TUD_ENDPOINT0_SIZE == 64
   USBD_EP_CR_REG(USBD_EP_0) = (USBD_EP0_MAX_SIZE_64 << BIT_USBD_EP0_MAX_SIZE);
@@ -702,7 +702,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     TU_LOG1("FT9xx endpoint size not valid: requested %d max 1024\r\n", ep_size);
     return false;
   }
-  // Calculate actual amount of buffer RAM used by this endpoint. This may be more than the 
+  // Calculate actual amount of buffer RAM used by this endpoint. This may be more than the
   // requested size.
   ep_buff_size = 8 << ep_reg_size;
 
@@ -714,7 +714,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     if (ep_xfer[ep_number].type != USBD_EP_TYPE_DISABLED)
     {
       // This could be because an endpoint has been assigned with the same number.
-      // On FT9xx, IN and OUT endpoints may not have the same number. e.g. There 
+      // On FT9xx, IN and OUT endpoints may not have the same number. e.g. There
       // cannot been an 0x81 and 0x01 endpoint.
       TU_LOG1("FT9xx endpoint %d already assigned\r\n", ep_number);
       return false;
@@ -723,7 +723,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     // Check that there is enough buffer RAM to allocate to this new endpoint.
     // Available buffer RAM depends on the device revision.
     // The IN and OUT buffer RAM should be the same size.
-    if (ep_dir == USBD_DIR_IN) 
+    if (ep_dir == USBD_DIR_IN)
       total_ram = USBD_RAMTOTAL_IN;
     else
       total_ram = USBD_RAMTOTAL_OUT;
@@ -753,7 +753,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc)
     if (total_ram < ep_buff_size)
     {
       TU_LOG1("FT9xx insufficient buffer RAM for endpoint %d\r\n", ep_number);
-      return false;    
+      return false;
     }
 
     // Set the type of this endpoint in the control register.
@@ -827,7 +827,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
     ep_xfer[ep_number].total_size = total_bytes;
     ep_xfer[ep_number].remain_size = total_bytes;
     ep_xfer[ep_number].buff_ptr = buffer;
-    
+
     if (ep_number == USBD_EP_0)
     {
       ep_xfer[USBD_EP_0].dir = ep_dir;
@@ -876,7 +876,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
         // then report the transfer complete with dcd_event_xfer_complete.
         ep_xfer[ep_number].valid = 1;
       }
-    } 
+    }
     status = true;
   }
   else
@@ -922,7 +922,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   CRITICAL_SECTION_END
 }
 
-// Clear stall (non-control endpoint), data toggle is also reset to DATA0 
+// Clear stall (non-control endpoint), data toggle is also reset to DATA0
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
   uint8_t ep_number = tu_edpt_number(ep_addr);
@@ -1025,7 +1025,7 @@ void dcd_int_handler(uint8_t rhport)
 
         // Host has sent a SETUP packet. Receive this into the SETUP packet store.
         _ft9xx_dusb_out(USBD_EP_0, (uint8_t *)_ft9xx_setup_packet, sizeof(USB_device_request));
-        
+
         // Send the packet to tinyusb.
         dcd_event_setup_received(BOARD_TUD_RHPORT, _ft9xx_setup_packet, true);
 
@@ -1046,13 +1046,13 @@ void dcd_int_handler(uint8_t rhport)
         {
           xfer_bytes = (uint16_t)ep_xfer[USBD_EP_0].total_size;
 
-          // Transfer incoming data from an OUT packet to the buffer supplied.        
+          // Transfer incoming data from an OUT packet to the buffer supplied.
           if (ep_xfer[USBD_EP_0].dir == TUSB_DIR_OUT)
           {
             xfer_bytes = _ft9xx_edpt_xfer_out(USBD_EP_0, ep_xfer[USBD_EP_0].buff_ptr, xfer_bytes);
           }
           // Now signal completion of data packet.
-          dcd_event_xfer_complete(BOARD_TUD_RHPORT, USBD_EP_0 | (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0), 
+          dcd_event_xfer_complete(BOARD_TUD_RHPORT, USBD_EP_0 | (ep_xfer[USBD_EP_0].dir ? TUSB_DIR_IN_MASK : 0),
             xfer_bytes, XFER_RESULT_SUCCESS, true);
 
           // Incoming FIFO has been cleared.
@@ -1097,13 +1097,13 @@ void dcd_int_handler(uint8_t rhport)
           // Start or continue an OUT transfer.
           if (ep_xfer[ep_number].dir == TUSB_DIR_OUT)
           {
-            xfer_bytes = _ft9xx_edpt_xfer_out(ep_number, 
-                            ep_xfer[ep_number].buff_ptr, 
+            xfer_bytes = _ft9xx_edpt_xfer_out(ep_number,
+                            ep_xfer[ep_number].buff_ptr,
                             (uint16_t)ep_xfer[ep_number].remain_size);
 
             // Report each OUT packet received to the stack.
-            dcd_event_xfer_complete(BOARD_TUD_RHPORT, 
-                                      ep_number /* | TUSB_DIR_OUT_MASK */, 
+            dcd_event_xfer_complete(BOARD_TUD_RHPORT,
+                                      ep_number /* | TUSB_DIR_OUT_MASK */,
                                       xfer_bytes, XFER_RESULT_SUCCESS, true);
 
             ep_xfer[ep_number].buff_ptr += xfer_bytes;
@@ -1114,8 +1114,8 @@ void dcd_int_handler(uint8_t rhport)
           {
             if (ep_xfer[ep_number].remain_size > 0)
             {
-              xfer_bytes = _ft9xx_edpt_xfer_in(ep_number, 
-                            ep_xfer[ep_number].buff_ptr, 
+              xfer_bytes = _ft9xx_edpt_xfer_in(ep_number,
+                            ep_xfer[ep_number].buff_ptr,
                             (uint16_t)ep_xfer[ep_number].remain_size);
 
               ep_xfer[ep_number].buff_ptr += xfer_bytes;
@@ -1124,8 +1124,8 @@ void dcd_int_handler(uint8_t rhport)
 
             if (ep_xfer[ep_number].remain_size == 0)
             {
-              dcd_event_xfer_complete(BOARD_TUD_RHPORT, 
-                                      ep_number | TUSB_DIR_IN_MASK, 
+              dcd_event_xfer_complete(BOARD_TUD_RHPORT,
+                                      ep_number | TUSB_DIR_IN_MASK,
                                       ep_xfer[ep_number].total_size, XFER_RESULT_SUCCESS, true);
             }
           }
@@ -1151,7 +1151,7 @@ void dcd_int_handler(uint8_t rhport)
             // once the transfer is initiated.
             // Strictly this should not happen for a non-control endpoint. Interrupts
             // are disabled when there are no transfers setup for an endpoint.
-            ep_xfer[ep_number].ready = 1;          
+            ep_xfer[ep_number].ready = 1;
           }
         }
       }
@@ -1159,13 +1159,13 @@ void dcd_int_handler(uint8_t rhport)
   }
 }
 
-// Power management interrupt handler. 
+// Power management interrupt handler.
 // This handles USB device related power management interrupts only.
 void ft9xx_usbd_pm_ISR(void)
 {
     uint16_t pmcfg = SYS->PMCFG_H;
 
-  // Main interrupt handler is responible for 
+  // Main interrupt handler is responible for
   if (pmcfg & MASK_SYS_PMCFG_DEV_CONN_DEV)
   {
       // Signal connection interrupt
diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h
index 728a86b86..31b5a012d 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_type.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_type.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 5bccf81a7..bc6736cf2 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -545,7 +545,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
       tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
     }
   }
-  
+
   // only number of bytes in the IOC qtd
   dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
 }
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index d0396daea..d607627b4 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 7140897a1..ee9dfb11f 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -566,7 +566,7 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms)
       case EHCI_QTYPE_ITD: // TODO support hs/fs ISO
       case EHCI_QTYPE_SITD:
       case EHCI_QTYPE_FSTN:
-				
+
       default: break;
     }
 
@@ -683,7 +683,7 @@ void hcd_int_handler(uint8_t rhport)
 
   uint32_t int_status = regs->status;
   int_status &= regs->inten;
-  
+
   regs->status = int_status; // Acknowledge handled interrupt
 
   if (int_status == 0) return;
diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c
index 41240f737..1fcfb6241 100644
--- a/src/portable/espressif/esp32sx/dcd_esp32sx.c
+++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c
@@ -874,4 +874,3 @@ void dcd_int_disable (uint8_t rhport)
 }
 
 #endif // #if OPT_MCU_ESP32S2 || OPT_MCU_ESP32S3
-
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 0ba53d4d0..487761847 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji KITAYAMA
@@ -572,7 +572,7 @@ static void process_bus_reset(uint8_t rhport)
   _dcd.pipe0.buf = NULL;
 
   USB0->TXIE = 1; /* Enable only EP0 */
-  USB0->RXIE = 0; 
+  USB0->RXIE = 0;
 
   /* Clear FIFO settings */
   for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
@@ -722,7 +722,7 @@ void dcd_edpt_close_all(uint8_t rhport)
   unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
   USB0->TXIE = 1; /* Enable only EP0 */
-  USB0->RXIE = 0; 
+  USB0->RXIE = 0;
   for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) {
     regs->TXMAXP = 0;
     regs->TXCSRH = 0;
@@ -854,7 +854,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   if (tu_edpt_dir(ep_addr)) { /* IN */
     regs->TXCSRL = USB_TXCSRL1_CLRDT;
   } else { /* OUT */
-    regs->RXCSRL = USB_RXCSRL1_CLRDT; 
+    regs->RXCSRL = USB_RXCSRL1_CLRDT;
   }
   if (ie) NVIC_EnableIRQ(USB0_IRQn);
 }
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 85e18e3aa..9eb2e005e 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji KITAYAMA
@@ -588,7 +588,7 @@ void hcd_int_disable(uint8_t rhport)
 uint32_t hcd_frame_number(uint8_t rhport)
 {
   (void)rhport;
-  /* The device must be reset at least once after connection 
+  /* The device must be reset at least once after connection
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
   return USB0->FRAME;
diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c
index 6cf0e6285..6986c8317 100644
--- a/src/portable/microchip/pic/dcd_pic.c
+++ b/src/portable/microchip/pic/dcd_pic.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Koji Kitayama
@@ -486,7 +486,7 @@ void dcd_init(uint8_t rhport)
 #else
   U1PWRCbits.USBPWR = 1;
 #endif
-  
+
 #if TU_PIC_INT_SIZE == 4
   uint32_t bdt_phys = KVA_TO_PA((uintptr_t)_dcd.bdt);
 
diff --git a/src/portable/microchip/pic32mz/usbhs_registers.h b/src/portable/microchip/pic32mz/usbhs_registers.h
index 93b552322..03fe78bbd 100644
--- a/src/portable/microchip/pic32mz/usbhs_registers.h
+++ b/src/portable/microchip/pic32mz/usbhs_registers.h
@@ -21,7 +21,7 @@
 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
 *******************************************************************************/
 /*******************************************************************************
-  USBHS Peripheral Library Register Definitions 
+  USBHS Peripheral Library Register Definitions
 
   File Name:
     usbhs_registers.h
@@ -50,16 +50,16 @@
 #define USBHS_REG_INTRRX        0x004
 #define USBHS_REG_INTRTXE       0x006
 #define USBHS_REG_INTRRXE       0x008
-#define USBHS_REG_INTRUSB       0x00A 
-#define USBHS_REG_INTRUSBE      0x00B 
+#define USBHS_REG_INTRUSB       0x00A
+#define USBHS_REG_INTRUSBE      0x00B
 #define USBHS_REG_FRAME         0x00C
 #define USBHS_REG_INDEX         0x00E
 #define USBHS_REG_TESTMODE      0x00F
 
 /*******************************************************
- * Endpoint Control Status Registers (CSR). These values 
+ * Endpoint Control Status Registers (CSR). These values
  * should be added to either the 0x10 to access the
- * register through Indexed CSR. To access the actual 
+ * register through Indexed CSR. To access the actual
  * CSR, see ahead in this header file.
  ******************************************************/
 
@@ -99,20 +99,20 @@
 #define USBHS_EP_DEVICE_RX_SEND_STALL 0x20
 
 /* FADDR - Device Function Address */
-typedef union 
+typedef union
 {
-    struct __attribute__((packed)) 
+    struct __attribute__((packed))
     {
         unsigned FUNC:7;
         unsigned :1;
     };
 
-    uint8_t w;  
+    uint8_t w;
 
 } __USBHS_FADDR_t;
 
 /* POWER - Control Resume and Suspend signalling */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -126,14 +126,14 @@ typedef union
         unsigned ISOUPD:1;
     };
     struct
-    {   
+    {
         uint8_t w;
     };
 
 } __USBHS_POWER_t;
 
 /* INTRTXE - Transmit endpoint interrupt enable */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -155,7 +155,7 @@ typedef union
 } __USBHS_INTRTXE_t;
 
 /* INTRRXE - Receive endpoint interrupt enable */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -198,7 +198,7 @@ typedef union
 } __USBHS_INTRUSBE_t;
 
 /* FRAME - Frame number */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -213,7 +213,7 @@ typedef union
 } __USBHS_FRAME_t;
 
 /* INDEX - Endpoint index */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -228,7 +228,7 @@ typedef union
 } __USBHS_INDEX_t;
 
 /* TESTMODE - Test mode register */
-typedef union 
+typedef union
 {
     struct __attribute__((packed))
     {
@@ -248,7 +248,7 @@ typedef union
 
 } __USBHS_TESTMODE_t;
 
-/* COUNT0 - Indicates the amount of data received in endpoint 0 */ 
+/* COUNT0 - Indicates the amount of data received in endpoint 0 */
 typedef union
 {
     struct __attribute__((packed))
@@ -627,7 +627,7 @@ typedef union
     };
     uint16_t w;
 
-} __USBHS_TXMAXP_t;  
+} __USBHS_TXMAXP_t;
 
 /* TXFIFOSZ - Size of the transmit endpoint FIFO */
 typedef struct __attribute__((packed))
@@ -781,7 +781,7 @@ typedef union
 
 } __USBHS_DMACNTL_t;
 
-/* Endpoint Control and Status Register Set */    
+/* Endpoint Control and Status Register Set */
 typedef struct __attribute__((packed))
 {
     volatile __USBHS_TXMAXP_t TXMAXPbits;
@@ -906,7 +906,7 @@ typedef struct __attribute__((aligned(4),packed))
 
     volatile __USBHS_TXFIFOADD_t   TXFIFOADDbits;
     volatile __USBHS_RXFIFOADD_t   RXFIFOADDbits;
-    
+
     volatile uint32_t   VCONTROL;
     volatile uint16_t   HWVERS;
     volatile uint8_t    padding1[10];
@@ -923,7 +923,7 @@ typedef struct __attribute__((aligned(4),packed))
     volatile __USBHS_TARGET_ADDR_t  TADDR[16];
     volatile __USBHS_EPCSR_t        EPCSR[16];
     volatile uint32_t               DMA_INTR;
-    volatile __USBHS_DMA_CHANNEL_t  DMA_CHANNEL[8]; 
+    volatile __USBHS_DMA_CHANNEL_t  DMA_CHANNEL[8];
     volatile uint32_t               RQPKTXOUNT[16];
 
 } usbhs_registers_t;
diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c
index 814e680fb..e3fa51e31 100644
--- a/src/portable/microchip/samg/dcd_samg.c
+++ b/src/portable/microchip/samg/dcd_samg.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
diff --git a/src/portable/microchip/samx7x/common_usb_regs.h b/src/portable/microchip/samx7x/common_usb_regs.h
index d232f0bcb..db4a81e0e 100644
--- a/src/portable/microchip/samx7x/common_usb_regs.h
+++ b/src/portable/microchip/samx7x/common_usb_regs.h
@@ -2007,7 +2007,7 @@
 
 /** \brief DEVDMA hardware registers */
 typedef struct
-{  
+{
   __IO uint32_t DEVDMANXTDSC; /**< (DEVDMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */
   __IO uint32_t DEVDMAADDRESS; /**< (DEVDMA Offset: 0x04) Device DMA Channel Address Register */
   __IO uint32_t DEVDMACONTROL; /**< (DEVDMA Offset: 0x08) Device DMA Channel Control Register */
@@ -2016,7 +2016,7 @@ typedef struct
 
 /** \brief HSTDMA hardware registers */
 typedef struct
-{  
+{
   __IO uint32_t HSTDMANXTDSC; /**< (HSTDMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */
   __IO uint32_t HSTDMAADDRESS; /**< (HSTDMA Offset: 0x04) Host DMA Channel Address Register */
   __IO uint32_t HSTDMACONTROL; /**< (HSTDMA Offset: 0x08) Host DMA Channel Control Register */
@@ -2025,7 +2025,7 @@ typedef struct
 
 /** \brief USBHS hardware registers */
 typedef struct
-{  
+{
   __IO uint32_t DEVCTRL;  /**< (USBHS Offset: 0x00) Device General Control Register */
   __I  uint32_t DEVISR;   /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */
   __O  uint32_t DEVICR;   /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 24657872b..2bbb345d6 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -241,7 +241,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
     if (int_status & DEVEPTISR_RXOUTI)
     {
       uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
-      
+
       if (count && xfer->total_len)
       {
         uint16_t remain = xfer->total_len - xfer->queued_len;
@@ -252,7 +252,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         if (xfer->buffer)
         {
           memcpy(xfer->buffer + xfer->queued_len, ptr, count);
-        } else 
+        } else
         {
           tu_fifo_write_n(xfer->fifo, ptr, count);
         }
@@ -281,7 +281,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX not complete
         dcd_transmit_packet(xfer, 0);
-      } else 
+      } else
       {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
@@ -292,7 +292,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
         }
       }
     }
-  } else 
+  } else
   {
     if (int_status & DEVEPTISR_RXOUTI)
     {
@@ -333,7 +333,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
       {
         // TX not complete
         dcd_transmit_packet(xfer, ep_ix);
-      } else 
+      } else
       {
         // TX complete
         dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true);
@@ -359,7 +359,7 @@ static void dcd_dma_handler(uint8_t ep_ix)
   if(USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR)
   {
     dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true);
-  } else 
+  } else
   {
     dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true);
   }
@@ -507,12 +507,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
       // Enable Endpoint 0 Interrupts
       USB_REG->DEVIER = DEVIER_PEP_0;
       return true;
-    } else 
+    } else
     {
       // Endpoint configuration is not successful
       return false;
     }
-  } else 
+  } else
   {
     // Enable the endpoint
     USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos);
@@ -544,7 +544,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
     {
       USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos);
       return true;
-    } else 
+    } else
     {
       // Endpoint configuration is not successful
       return false;
@@ -583,7 +583,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
     {
       memcpy(ptr, xfer->buffer + xfer->queued_len, len);
     }
-    else 
+    else
     {
       tu_fifo_read_n(xfer->fifo, ptr, len);
     }
@@ -595,7 +595,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
   {
     // Control endpoint: clear the interrupt flag to send the data
     USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC;
-  } else 
+  } else
   {
     // Other endpoint types: clear the FIFO control flag to send the data
     USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC;
@@ -616,7 +616,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   xfer->total_len = total_bytes;
   xfer->queued_len = 0;
   xfer->fifo = NULL;
-  
+
   if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
   {
     // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the
@@ -648,12 +648,12 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     // and the DMA transfer must be not started.
     // It is the end of transfer
     return false;
-  } else 
+  } else
   {
     if (dir == TUSB_DIR_OUT)
     {
       USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
-    } else 
+    } else
     {
       dcd_transmit_packet(xfer,epnum);
     }
@@ -701,20 +701,20 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 
     // Clean invalidate cache of linear part
     CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_lin, 4), info.len_lin + 31);
-    
+
     USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.ptr_lin;
     if (info.len_wrap)
     {
       // Clean invalidate cache of wrapped part
       CleanInValidateCache((uint32_t*) tu_align((uint32_t) info.ptr_wrap, 4), info.len_wrap + 31);
-      
+
       dma_desc[epnum - 1].next_desc = 0;
       dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
       dma_desc[epnum - 1].chnl_ctrl =
         udd_dma_ctrl_wrap | (info.len_wrap << DEVDMACONTROL_BUFF_LENGTH_Pos);
       // Clean cache of wrapped DMA descriptor
       CleanInValidateCache((uint32_t*)&dma_desc[epnum - 1], sizeof(dma_desc_t));
-      
+
       udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST;
       USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1];
     } else {
@@ -743,7 +743,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
     if (dir == TUSB_DIR_OUT)
     {
       USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES;
-    } else 
+    } else
     {
       dcd_transmit_packet(xfer,epnum);
     }
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index 4aeb85fc0..eee5686f4 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c
index 2fdc05f36..fb12122e0 100644
--- a/src/portable/nuvoton/nuc120/dcd_nuc120.c
+++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c
@@ -27,9 +27,9 @@
 /*
   Theory of operation:
 
-  The NUC100/NUC120 USBD peripheral has six "EP"s, but each is simplex, 
-  so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to 
-  implement USB EP0.  PERIPH_EP0 and PERIPH_EP1 are used by this driver for 
+  The NUC100/NUC120 USBD peripheral has six "EP"s, but each is simplex,
+  so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to
+  implement USB EP0.  PERIPH_EP0 and PERIPH_EP1 are used by this driver for
   EP0_IN and EP0_OUT respectively.  This leaves up to four for user usage.
 */
 
diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c
index a56b5f8e8..873b1b7ef 100644
--- a/src/portable/nuvoton/nuc121/dcd_nuc121.c
+++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c
@@ -27,9 +27,9 @@
 /*
   Theory of operation:
 
-  The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex, 
-  so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to 
-  implement USB EP0.  PERIPH_EP0 and PERIPH_EP1 are used by this driver for 
+  The NUC121/NUC125/NUC126 USBD peripheral has eight "EP"s, but each is simplex,
+  so two collectively (peripheral nomenclature of "EP0" and "EP1") are needed to
+  implement USB EP0.  PERIPH_EP0 and PERIPH_EP1 are used by this driver for
   EP0_IN and EP0_OUT respectively.  This leaves up to six for user usage.
 */
 
diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c
index 3fa7c1ec1..3a92c9794 100644
--- a/src/portable/nuvoton/nuc505/dcd_nuc505.c
+++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c
@@ -27,9 +27,9 @@
 /*
   Theory of operation:
 
-  The NUC505 USBD peripheral has twelve "EP"s, where each is simplex, in addition 
+  The NUC505 USBD peripheral has twelve "EP"s, where each is simplex, in addition
   to dedicated support for the control endpoint (EP0).  The non-user endpoints
-  are referred to as "user" EPs in this code, and follow the datasheet 
+  are referred to as "user" EPs in this code, and follow the datasheet
   nomenclature of EPA through EPL.
 */
 
@@ -389,7 +389,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
       while (total_bytes < USBD->CEPRXCNT);
       for (int count = 0; count < total_bytes; count++)
         *buffer++ = USBD->CEPDAT_BYTE;
-      
+
       dcd_event_xfer_complete(0, ep_addr, total_bytes, XFER_RESULT_SUCCESS, true);
     }
   }
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 13eb105cd..b6daec3de 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 Koji Kitayama
@@ -296,7 +296,7 @@ void dcd_int_disable(uint8_t rhport)
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
-  _dcd.addr = dev_addr & 0x7F; 
+  _dcd.addr = dev_addr & 0x7F;
   /* Response with status first before changing device address */
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
@@ -528,7 +528,7 @@ void dcd_int_handler(uint8_t rhport)
   if (is & USB_ISTAT_SLEEP_MASK) {
     // TU_LOG2("Suspend: "); TU_LOG2_HEX(is);
 
-    // Note Host usually has extra delay after bus reset (without SOF), which could falsely 
+    // Note Host usually has extra delay after bus reset (without SOF), which could falsely
     // detected as Sleep event. Though usbd has debouncing logic so we are good
     KHCI->ISTAT = USB_ISTAT_SLEEP_MASK;
     process_bus_sleep(rhport);
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 0f5fa6275..35763f121 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Koji Kitayama
@@ -414,7 +414,7 @@ void hcd_int_disable(uint8_t rhport)
 uint32_t hcd_frame_number(uint8_t rhport)
 {
   (void)rhport;
-  /* The device must be reset at least once after connection 
+  /* The device must be reset at least once after connection
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
   uint32_t frmnum = KHCI->FRMNUML;
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 0894a5eeb..86149afd8 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.h b/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
index 07daa32e4..654b80866 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
index ad9ed59b4..372dcf51f 100644
--- a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
@@ -44,4 +44,3 @@ void hcd_int_disable(uint8_t rhport)
 }
 
 #endif
-
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 124656307..5368ef868 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -373,7 +373,7 @@ void dcd_edpt_close_all (uint8_t rhport)
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
   (void) rhport;
-  
+
   uint8_t ep_id = ep_addr2id(ep_addr);
   _dcd.ep[ep_id][0].cmd_sts.active = _dcd.ep[ep_id][0].cmd_sts.active = 0; // TODO proper way is to EPSKIP then wait ep[][].active then write ep[][].disable (see table 778 in LPC55S69 Use Manual)
   _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
@@ -426,7 +426,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
 static void bus_reset(uint8_t rhport)
 {
   tu_memclr(&_dcd, sizeof(dcd_data_t));
-  edpt_reset_all(rhport); 
+  edpt_reset_all(rhport);
 
   // disable all endpoints as specified by LPC55S69 UM Table 778
   for(uint8_t ep_id = 0; ep_id < 2*MAX_EP_PAIRS; ep_id++)
@@ -575,4 +575,3 @@ void dcd_int_handler(uint8_t rhport)
 }
 
 #endif
-
diff --git a/src/portable/nxp/transdimension/common_transdimension.h b/src/portable/nxp/transdimension/common_transdimension.h
index 69074de41..95ae1903e 100644
--- a/src/portable/nxp/transdimension/common_transdimension.h
+++ b/src/portable/nxp/transdimension/common_transdimension.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2021, Ha Thach (tinyusb.org)
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
index 1f27a6872..983d7cfcf 100644
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ b/src/portable/nxp/transdimension/dcd_transdimension.c
@@ -569,7 +569,7 @@ static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir
       tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
     }
   }
-  
+
   // only number of bytes in the IOC qtd
   dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
 }
diff --git a/src/portable/nxp/transdimension/hcd_transdimension.c b/src/portable/nxp/transdimension/hcd_transdimension.c
index 392764ff6..0b3e9e4ef 100644
--- a/src/portable/nxp/transdimension/hcd_transdimension.c
+++ b/src/portable/nxp/transdimension/hcd_transdimension.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index b615743b8..260804d3d 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -715,4 +715,3 @@ void hcd_int_handler(uint8_t hostid)
 
 
 #endif
-
diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
index 1bc5594d8..e6daf6827 100644
--- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index a06407f23..9f8e58d42 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -47,7 +47,7 @@ typedef struct hw_endpoint
 {
     // Is this a valid struct
     bool configured;
-    
+
     // Transfer direction (i.e. IN is rx for host but tx for device)
     // allows us to common up transfer functions
     bool rx;
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index e49c0b52e..1677cfa12 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Nathan Conrad
@@ -181,7 +181,7 @@ static void dcd_handle_bus_reset(void);
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix);
 static void dcd_ep_ctr_handler(void);
 
-// PMA allocation/access 
+// PMA allocation/access
 static uint8_t open_ep_count;
 static uint16_t ep_buf_ptr; ///< Points to first free memory location
 static void dcd_pma_alloc_reset(void);
@@ -249,7 +249,7 @@ void dcd_init (uint8_t rhport)
     asm("NOP");
   }
   USB->CNTR = 0; // Enable USB
-  
+
   USB->BTABLE = DCD_STM32_BTABLE_BASE;
 
   USB->ISTR = 0; // Clear pending interrupts
@@ -263,7 +263,7 @@ void dcd_init (uint8_t rhport)
 
   USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
   dcd_handle_bus_reset();
-  
+
   // Enable pull-up if supported
   if ( dcd_connect ) dcd_connect(rhport);
 }
@@ -464,12 +464,12 @@ static void dcd_handle_bus_reset(void)
   //__IO uint16_t * const epreg = &(EPREG(0));
   USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
 
-  
+
   for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
   {
     // Clear all EPREG (or maybe this is automatic? I'm not sure)
     pcd_set_endpoint(USB,i,0u);
-    
+
     // Clear EP allocation status
     ep_alloc_status[i].ep_num = 0xFF;
     ep_alloc_status[i].ep_type = 0xFF;
@@ -531,7 +531,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr)
   {
     return;
   }
-  
+
   if((ep_addr == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */
   {
     // The setup_received function uses memcpy, so this must first copy the setup data into
@@ -743,11 +743,11 @@ static void dcd_pma_alloc_reset(void)
 
 /***
  * Allocate a section of PMA
- * 
+ *
  * If the EP number has already been allocated, and the new allocation
  * is larger than the old allocation, then this will fail with a TU_ASSERT.
  * (This is done to simplify the code. More complicated algorithms could be used)
- * 
+ *
  * During failure, TU_ASSERT is used. If this happens, rework/reallocate memory manually.
  */
 static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
@@ -838,7 +838,7 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type)
           ep_alloc_status[i].ep_num = epnum;
           ep_alloc_status[i].ep_type = ep_type;
           ep_alloc_status[i].allocated[dir] = true;
-          
+
           return i;
         }
       }
@@ -860,7 +860,7 @@ static void dcd_ep_free(uint8_t ep_addr)
   for(uint8_t i = 0; i < STFSDEV_EP_COUNT; i++)
   {
     // Check if EP number & dir are the same
-    if(ep_alloc_status[i].ep_num == epnum && 
+    if(ep_alloc_status[i].ep_num == epnum &&
        ep_alloc_status[i].allocated[dir] == dir)
     {
       ep_alloc_status[i].allocated[dir] = false;
@@ -968,9 +968,9 @@ void dcd_edpt_close_all (uint8_t rhport)
 
 /**
  * Close an endpoint.
- * 
+ *
  * This function may be called with interrupts enabled or disabled.
- * 
+ *
  * This also clears transfers in progress, should there be any.
  */
 void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
@@ -998,9 +998,9 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size)
 {
   (void)rhport;
-  
+
   TU_ASSERT(largest_packet_size <= 1024);
-  
+
   uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS);
   const uint16_t buffer_size = pcd_aligned_buffer_size(largest_packet_size);
 
@@ -1011,10 +1011,10 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
   xfer_ctl_ptr(ep_addr)->ep_idx = ep_idx;
 
   pcd_set_eptype(USB, ep_idx, USB_EP_ISOCHRONOUS);
-  
+
   *pcd_ep_tx_address_ptr(USB, ep_idx) = pma_addr;
   *pcd_ep_rx_address_ptr(USB, ep_idx) = pma_addr;
-  
+
   return true;
 }
 
@@ -1035,7 +1035,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpo
   {
     pcd_set_ep_rx_status(USB, ep_idx, USB_EP_RX_DIS);
   }
-  
+
   pcd_set_ep_address(USB, ep_idx, tu_edpt_number(p_endpoint_desc->bEndpointAddress));
   // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
   // or being double-buffered (bulk endpoints)
@@ -1250,11 +1250,11 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
 {
   // Since we copy from a ring buffer FIFO, a wrap might occur making it necessary to conduct two copies
   tu_fifo_buffer_info_t info;
-  tu_fifo_get_read_info(ff, &info); 
-  
+  tu_fifo_get_read_info(ff, &info);
+
   uint16_t cnt_lin =  TU_MIN(wNBytes, info.len_lin);
   uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap);
-  
+
   // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
   // last lin byte will be combined with wrapped part
   // To ensure PMA is always access 16bit aligned (dst aligned to 16 bit)
@@ -1352,7 +1352,7 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
     // Copy last linear byte & first wrapped byte
     uint16_t tmp;
     dcd_read_packet_memory(&tmp, src, 2);
-    
+
     ((uint8_t*)info.ptr_lin)[cnt_lin - 1] = (uint8_t)tmp;
     ((uint8_t*)info.ptr_wrap)[0] = (uint8_t)(tmp >> 8U);
     src += 2;
@@ -1379,4 +1379,3 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
 }
 
 #endif
-
diff --git a/src/portable/st/synopsys/synopsys_common.h b/src/portable/st/synopsys/synopsys_common.h
index 6f0602fe9..ce3195b23 100644
--- a/src/portable/st/synopsys/synopsys_common.h
+++ b/src/portable/st/synopsys/synopsys_common.h
@@ -2,15 +2,15 @@
   ******************************************************************************
   * @file    synopsys_common.h
   * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M3 Device USB OTG peripheral Header File. 
-  *          This file contains the USB OTG peripheral register's definitions, bits 
+  * @brief   CMSIS Cortex-M3 Device USB OTG peripheral Header File.
+  *          This file contains the USB OTG peripheral register's definitions, bits
   *          definitions and memory mapping for STM32F1xx devices.
-  *            
+  *
   *          This file contains:
   *           - Data structures and the address mapping for the USB OTG peripheral
   *           - The Peripheral's registers declarations and bits definition
   *           - Macros to access the peripheral's registers hardware
-  *  
+  *
   ******************************************************************************
   * @attention
   *
@@ -40,7 +40,7 @@
 #define     __OM  volatile
 #define     __IOM volatile
 
-/** 
+/**
   * @brief __USB_OTG_Core_register
   */
 
@@ -66,11 +66,11 @@ typedef struct
   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                 Address offset: 0x104 */
 } USB_OTG_GlobalTypeDef;
 
-/** 
+/**
   * @brief __device_Registers
   */
 
-typedef struct 
+typedef struct
 {
   __IO uint32_t DCFG;                 /*!< dev Configuration Register                 Address offset: 800h*/
   __IO uint32_t DCTL;                 /*!< dev Control Register                       Address offset: 804h*/
@@ -87,18 +87,18 @@ typedef struct
   __IO uint32_t DTHRCTL;              /*!< dev thr                                    Address offset: 830h*/
   __IO uint32_t DIEPEMPMSK;           /*!< dev empty msk                              Address offset: 834h*/
   __IO uint32_t DEACHINT;             /*!< dedicated EP interrupt                     Address offset: 838h*/
-  __IO uint32_t DEACHMSK;             /*!< dedicated EP msk                           Address offset: 83Ch*/  
+  __IO uint32_t DEACHMSK;             /*!< dedicated EP msk                           Address offset: 83Ch*/
   uint32_t Reserved40;                /*!< dedicated EP mask                          Address offset: 840h*/
   __IO uint32_t DINEP1MSK;            /*!< dedicated EP mask                          Address offset: 844h*/
   uint32_t  Reserved44[15];           /*!< Reserved 844-87Ch*/
   __IO uint32_t DOUTEP1MSK;           /*!< dedicated EP msk                           Address offset: 884h*/
 } USB_OTG_DeviceTypeDef;
 
-/** 
+/**
   * @brief __IN_Endpoint-Specific_Register
   */
 
-typedef struct 
+typedef struct
 {
   __IO uint32_t DIEPCTL;              /*!< dev IN Endpoint Control Reg                900h + (ep_num * 20h) + 00h*/
   uint32_t Reserved04;                /*!< Reserved                                   900h + (ep_num * 20h) + 04h*/
@@ -110,11 +110,11 @@ typedef struct
   uint32_t Reserved18;                /*!< Reserved                                   900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
 } USB_OTG_INEndpointTypeDef;
 
-/** 
+/**
   * @brief __OUT_Endpoint-Specific_Registers
   */
 
-typedef struct 
+typedef struct
 {
   __IO uint32_t DOEPCTL;              /*!< dev OUT Endpoint Control Reg               B00h + (ep_num * 20h) + 00h*/
   uint32_t Reserved04;                /*!< Reserved                                   B00h + (ep_num * 20h) + 04h*/
@@ -125,11 +125,11 @@ typedef struct
   uint32_t Reserved18[2];             /*!< Reserved                                   B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
 } USB_OTG_OUTEndpointTypeDef;
 
-/** 
+/**
   * @brief __Host_Mode_Register_Structures
   */
 
-typedef struct 
+typedef struct
 {
   __IO uint32_t HCFG;                 /*!< Host Configuration Register    400h*/
   __IO uint32_t HFIR;                 /*!< Host Frame Interval Register   404h*/
@@ -140,7 +140,7 @@ typedef struct
   __IO uint32_t HAINTMSK;             /*!< Host All Channels Interrupt Mask 418h*/
 } USB_OTG_HostTypeDef;
 
-/** 
+/**
   * @brief __Host_Channel_Specific_Registers
   */
 
@@ -177,60 +177,60 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
-#define USB_OTG_GOTGCTL_SRQSCS_Pos              (0U)                           
+#define USB_OTG_GOTGCTL_SRQSCS_Pos              (0U)
 #define USB_OTG_GOTGCTL_SRQSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
 #define USB_OTG_GOTGCTL_SRQSCS                  USB_OTG_GOTGCTL_SRQSCS_Msk     /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ_Pos                 (1U)                           
+#define USB_OTG_GOTGCTL_SRQ_Pos                 (1U)
 #define USB_OTG_GOTGCTL_SRQ_Msk                 (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
 #define USB_OTG_GOTGCTL_SRQ                     USB_OTG_GOTGCTL_SRQ_Msk        /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS_Pos              (8U)                           
+#define USB_OTG_GOTGCTL_HNGSCS_Pos              (8U)
 #define USB_OTG_GOTGCTL_HNGSCS_Msk              (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
 #define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ_Pos               (9U)                           
+#define USB_OTG_GOTGCTL_HNPRQ_Pos               (9U)
 #define USB_OTG_GOTGCTL_HNPRQ_Msk               (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
 #define USB_OTG_GOTGCTL_HNPRQ                   USB_OTG_GOTGCTL_HNPRQ_Msk      /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN_Pos             (10U)                          
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos             (10U)
 #define USB_OTG_GOTGCTL_HSHNPEN_Msk             (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
 #define USB_OTG_GOTGCTL_HSHNPEN                 USB_OTG_GOTGCTL_HSHNPEN_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN_Pos              (11U)                          
+#define USB_OTG_GOTGCTL_DHNPEN_Pos              (11U)
 #define USB_OTG_GOTGCTL_DHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
 #define USB_OTG_GOTGCTL_DHNPEN                  USB_OTG_GOTGCTL_DHNPEN_Msk     /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS_Pos              (16U)                          
+#define USB_OTG_GOTGCTL_CIDSTS_Pos              (16U)
 #define USB_OTG_GOTGCTL_CIDSTS_Msk              (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
 #define USB_OTG_GOTGCTL_CIDSTS                  USB_OTG_GOTGCTL_CIDSTS_Msk     /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT_Pos                (17U)                          
+#define USB_OTG_GOTGCTL_DBCT_Pos                (17U)
 #define USB_OTG_GOTGCTL_DBCT_Msk                (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
 #define USB_OTG_GOTGCTL_DBCT                    USB_OTG_GOTGCTL_DBCT_Msk       /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD_Pos               (18U)                          
+#define USB_OTG_GOTGCTL_ASVLD_Pos               (18U)
 #define USB_OTG_GOTGCTL_ASVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
 #define USB_OTG_GOTGCTL_ASVLD                   USB_OTG_GOTGCTL_ASVLD_Msk      /*!< A-session valid */
-#define USB_OTG_GOTGCTL_BSVLD_Pos               (19U)                          
+#define USB_OTG_GOTGCTL_BSVLD_Pos               (19U)
 #define USB_OTG_GOTGCTL_BSVLD_Msk               (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
 #define USB_OTG_GOTGCTL_BSVLD                   USB_OTG_GOTGCTL_BSVLD_Msk      /*!< B-session valid */
 
 /********************  Bit definition for USB_OTG_HCFG register  ********************/
 
-#define USB_OTG_HCFG_FSLSPCS_Pos                (0U)                           
+#define USB_OTG_HCFG_FSLSPCS_Pos                (0U)
 #define USB_OTG_HCFG_FSLSPCS_Msk                (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
 #define USB_OTG_HCFG_FSLSPCS                    USB_OTG_HCFG_FSLSPCS_Msk       /*!< FS/LS PHY clock select */
 #define USB_OTG_HCFG_FSLSPCS_0                  (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
 #define USB_OTG_HCFG_FSLSPCS_1                  (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCFG_FSLSS_Pos                  (2U)                           
+#define USB_OTG_HCFG_FSLSS_Pos                  (2U)
 #define USB_OTG_HCFG_FSLSS_Msk                  (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
 #define USB_OTG_HCFG_FSLSS                      USB_OTG_HCFG_FSLSS_Msk         /*!< FS- and LS-only support */
 
 /********************  Bit definition for USB_OTG_DCFG register  ********************/
 
-#define USB_OTG_DCFG_DSPD_Pos                   (0U)                           
+#define USB_OTG_DCFG_DSPD_Pos                   (0U)
 #define USB_OTG_DCFG_DSPD_Msk                   (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
 #define USB_OTG_DCFG_DSPD                       USB_OTG_DCFG_DSPD_Msk          /*!< Device speed */
 #define USB_OTG_DCFG_DSPD_0                     (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
 #define USB_OTG_DCFG_DSPD_1                     (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCFG_NZLSOHSK_Pos               (2U)                           
+#define USB_OTG_DCFG_NZLSOHSK_Pos               (2U)
 #define USB_OTG_DCFG_NZLSOHSK_Msk               (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
 #define USB_OTG_DCFG_NZLSOHSK                   USB_OTG_DCFG_NZLSOHSK_Msk      /*!< Nonzero-length status OUT handshake */
 
-#define USB_OTG_DCFG_DAD_Pos                    (4U)                           
+#define USB_OTG_DCFG_DAD_Pos                    (4U)
 #define USB_OTG_DCFG_DAD_Msk                    (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
 #define USB_OTG_DCFG_DAD                        USB_OTG_DCFG_DAD_Msk           /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                      (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
@@ -241,120 +241,120 @@ typedef struct
 #define USB_OTG_DCFG_DAD_5                      (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
 #define USB_OTG_DCFG_DAD_6                      (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
 
-#define USB_OTG_DCFG_PFIVL_Pos                  (11U)                          
+#define USB_OTG_DCFG_PFIVL_Pos                  (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                  (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
 #define USB_OTG_DCFG_PFIVL                      USB_OTG_DCFG_PFIVL_Msk         /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                    (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                    (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
-#define USB_OTG_DCFG_PERSCHIVL_Pos              (24U)                          
+#define USB_OTG_DCFG_PERSCHIVL_Pos              (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk              (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
 #define USB_OTG_DCFG_PERSCHIVL                  USB_OTG_DCFG_PERSCHIVL_Msk     /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK_Pos               (0U)                           
+#define USB_OTG_PCGCR_STPPCLK_Pos               (0U)
 #define USB_OTG_PCGCR_STPPCLK_Msk               (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
 #define USB_OTG_PCGCR_STPPCLK                   USB_OTG_PCGCR_STPPCLK_Msk      /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK_Pos              (1U)                           
+#define USB_OTG_PCGCR_GATEHCLK_Pos              (1U)
 #define USB_OTG_PCGCR_GATEHCLK_Msk              (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
 #define USB_OTG_PCGCR_GATEHCLK                  USB_OTG_PCGCR_GATEHCLK_Msk     /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP_Pos               (4U)                           
+#define USB_OTG_PCGCR_PHYSUSP_Pos               (4U)
 #define USB_OTG_PCGCR_PHYSUSP_Msk               (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
 #define USB_OTG_PCGCR_PHYSUSP                   USB_OTG_PCGCR_PHYSUSP_Msk      /*!< PHY suspended */
 
 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET_Pos               (2U)                           
+#define USB_OTG_GOTGINT_SEDET_Pos               (2U)
 #define USB_OTG_GOTGINT_SEDET_Msk               (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
 #define USB_OTG_GOTGINT_SEDET                   USB_OTG_GOTGINT_SEDET_Msk      /*!< Session end detected */
-#define USB_OTG_GOTGINT_SRSSCHG_Pos             (8U)                           
+#define USB_OTG_GOTGINT_SRSSCHG_Pos             (8U)
 #define USB_OTG_GOTGINT_SRSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
 #define USB_OTG_GOTGINT_SRSSCHG                 USB_OTG_GOTGINT_SRSSCHG_Msk    /*!< Session request success status change */
-#define USB_OTG_GOTGINT_HNSSCHG_Pos             (9U)                           
+#define USB_OTG_GOTGINT_HNSSCHG_Pos             (9U)
 #define USB_OTG_GOTGINT_HNSSCHG_Msk             (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
 #define USB_OTG_GOTGINT_HNSSCHG                 USB_OTG_GOTGINT_HNSSCHG_Msk    /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET_Pos              (17U)                          
+#define USB_OTG_GOTGINT_HNGDET_Pos              (17U)
 #define USB_OTG_GOTGINT_HNGDET_Msk              (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
 #define USB_OTG_GOTGINT_HNGDET                  USB_OTG_GOTGINT_HNGDET_Msk     /*!< Host negotiation detected */
-#define USB_OTG_GOTGINT_ADTOCHG_Pos             (18U)                          
+#define USB_OTG_GOTGINT_ADTOCHG_Pos             (18U)
 #define USB_OTG_GOTGINT_ADTOCHG_Msk             (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
 #define USB_OTG_GOTGINT_ADTOCHG                 USB_OTG_GOTGINT_ADTOCHG_Msk    /*!< A-device timeout change */
-#define USB_OTG_GOTGINT_DBCDNE_Pos              (19U)                          
+#define USB_OTG_GOTGINT_DBCDNE_Pos              (19U)
 #define USB_OTG_GOTGINT_DBCDNE_Msk              (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
 #define USB_OTG_GOTGINT_DBCDNE                  USB_OTG_GOTGINT_DBCDNE_Msk     /*!< Debounce done */
 
 /********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG_Pos                 (0U)                           
+#define USB_OTG_DCTL_RWUSIG_Pos                 (0U)
 #define USB_OTG_DCTL_RWUSIG_Msk                 (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
 #define USB_OTG_DCTL_RWUSIG                     USB_OTG_DCTL_RWUSIG_Msk        /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS_Pos                   (1U)                           
+#define USB_OTG_DCTL_SDIS_Pos                   (1U)
 #define USB_OTG_DCTL_SDIS_Msk                   (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
 #define USB_OTG_DCTL_SDIS                       USB_OTG_DCTL_SDIS_Msk          /*!< Soft disconnect */
-#define USB_OTG_DCTL_GINSTS_Pos                 (2U)                           
+#define USB_OTG_DCTL_GINSTS_Pos                 (2U)
 #define USB_OTG_DCTL_GINSTS_Msk                 (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
 #define USB_OTG_DCTL_GINSTS                     USB_OTG_DCTL_GINSTS_Msk        /*!< Global IN NAK status */
-#define USB_OTG_DCTL_GONSTS_Pos                 (3U)                           
+#define USB_OTG_DCTL_GONSTS_Pos                 (3U)
 #define USB_OTG_DCTL_GONSTS_Msk                 (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
 #define USB_OTG_DCTL_GONSTS                     USB_OTG_DCTL_GONSTS_Msk        /*!< Global OUT NAK status */
 
-#define USB_OTG_DCTL_TCTL_Pos                   (4U)                           
+#define USB_OTG_DCTL_TCTL_Pos                   (4U)
 #define USB_OTG_DCTL_TCTL_Msk                   (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
 #define USB_OTG_DCTL_TCTL                       USB_OTG_DCTL_TCTL_Msk          /*!< Test control */
 #define USB_OTG_DCTL_TCTL_0                     (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCTL_TCTL_1                     (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCTL_TCTL_2                     (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCTL_SGINAK_Pos                 (7U)                           
+#define USB_OTG_DCTL_SGINAK_Pos                 (7U)
 #define USB_OTG_DCTL_SGINAK_Msk                 (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
 #define USB_OTG_DCTL_SGINAK                     USB_OTG_DCTL_SGINAK_Msk        /*!< Set global IN NAK */
-#define USB_OTG_DCTL_CGINAK_Pos                 (8U)                           
+#define USB_OTG_DCTL_CGINAK_Pos                 (8U)
 #define USB_OTG_DCTL_CGINAK_Msk                 (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
 #define USB_OTG_DCTL_CGINAK                     USB_OTG_DCTL_CGINAK_Msk        /*!< Clear global IN NAK */
-#define USB_OTG_DCTL_SGONAK_Pos                 (9U)                           
+#define USB_OTG_DCTL_SGONAK_Pos                 (9U)
 #define USB_OTG_DCTL_SGONAK_Msk                 (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
 #define USB_OTG_DCTL_SGONAK                     USB_OTG_DCTL_SGONAK_Msk        /*!< Set global OUT NAK */
-#define USB_OTG_DCTL_CGONAK_Pos                 (10U)                          
+#define USB_OTG_DCTL_CGONAK_Pos                 (10U)
 #define USB_OTG_DCTL_CGONAK_Msk                 (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
 #define USB_OTG_DCTL_CGONAK                     USB_OTG_DCTL_CGONAK_Msk        /*!< Clear global OUT NAK */
-#define USB_OTG_DCTL_POPRGDNE_Pos               (11U)                          
+#define USB_OTG_DCTL_POPRGDNE_Pos               (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk               (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                   USB_OTG_DCTL_POPRGDNE_Msk      /*!< Power-on programming done */
 
 /********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL_Pos                  (0U)                           
+#define USB_OTG_HFIR_FRIVL_Pos                  (0U)
 #define USB_OTG_HFIR_FRIVL_Msk                  (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_HFIR_FRIVL                      USB_OTG_HFIR_FRIVL_Msk         /*!< Frame interval */
 
 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM_Pos                 (0U)                           
+#define USB_OTG_HFNUM_FRNUM_Pos                 (0U)
 #define USB_OTG_HFNUM_FRNUM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_HFNUM_FRNUM                     USB_OTG_HFNUM_FRNUM_Msk        /*!< Frame number */
-#define USB_OTG_HFNUM_FTREM_Pos                 (16U)                          
+#define USB_OTG_HFNUM_FTREM_Pos                 (16U)
 #define USB_OTG_HFNUM_FTREM_Msk                 (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
 #define USB_OTG_HFNUM_FTREM                     USB_OTG_HFNUM_FTREM_Msk        /*!< Frame time remaining */
 
 /********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS_Pos                (0U)                           
+#define USB_OTG_DSTS_SUSPSTS_Pos                (0U)
 #define USB_OTG_DSTS_SUSPSTS_Msk                (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
 #define USB_OTG_DSTS_SUSPSTS                    USB_OTG_DSTS_SUSPSTS_Msk       /*!< Suspend status */
 
-#define USB_OTG_DSTS_ENUMSPD_Pos                (1U)                           
+#define USB_OTG_DSTS_ENUMSPD_Pos                (1U)
 #define USB_OTG_DSTS_ENUMSPD_Msk                (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
 #define USB_OTG_DSTS_ENUMSPD                    USB_OTG_DSTS_ENUMSPD_Msk       /*!< Enumerated speed */
 #define USB_OTG_DSTS_ENUMSPD_0                  (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
 #define USB_OTG_DSTS_ENUMSPD_1                  (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
-#define USB_OTG_DSTS_EERR_Pos                   (3U)                           
+#define USB_OTG_DSTS_EERR_Pos                   (3U)
 #define USB_OTG_DSTS_EERR_Msk                   (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
 #define USB_OTG_DSTS_EERR                       USB_OTG_DSTS_EERR_Msk          /*!< Erratic error */
-#define USB_OTG_DSTS_FNSOF_Pos                  (8U)                           
+#define USB_OTG_DSTS_FNSOF_Pos                  (8U)
 #define USB_OTG_DSTS_FNSOF_Msk                  (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
 #define USB_OTG_DSTS_FNSOF                      USB_OTG_DSTS_FNSOF_Msk         /*!< Frame number of the received SOF */
 
 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT_Pos                (0U)                           
+#define USB_OTG_GAHBCFG_GINT_Pos                (0U)
 #define USB_OTG_GAHBCFG_GINT_Msk                (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
 #define USB_OTG_GAHBCFG_GINT                    USB_OTG_GAHBCFG_GINT_Msk       /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)                           
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos             (1U)
 #define USB_OTG_GAHBCFG_HBSTLEN_Msk             (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
 #define USB_OTG_GAHBCFG_HBSTLEN                 USB_OTG_GAHBCFG_HBSTLEN_Msk    /*!< Burst length/type */
 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
@@ -362,99 +362,99 @@ typedef struct
 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
 #define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
-#define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)                           
+#define USB_OTG_GAHBCFG_DMAEN_Pos               (5U)
 #define USB_OTG_GAHBCFG_DMAEN_Msk               (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
 #define USB_OTG_GAHBCFG_DMAEN                   USB_OTG_GAHBCFG_DMAEN_Msk      /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL_Pos             (7U)                           
+#define USB_OTG_GAHBCFG_TXFELVL_Pos             (7U)
 #define USB_OTG_GAHBCFG_TXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
 #define USB_OTG_GAHBCFG_TXFELVL                 USB_OTG_GAHBCFG_TXFELVL_Msk    /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL_Pos            (8U)                           
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos            (8U)
 #define USB_OTG_GAHBCFG_PTXFELVL_Msk            (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
 #define USB_OTG_GAHBCFG_PTXFELVL                USB_OTG_GAHBCFG_PTXFELVL_Msk   /*!< Periodic TxFIFO empty level */
 
 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
 
-#define USB_OTG_GUSBCFG_TOCAL_Pos               (0U)                           
+#define USB_OTG_GUSBCFG_TOCAL_Pos               (0U)
 #define USB_OTG_GUSBCFG_TOCAL_Msk               (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
 #define USB_OTG_GUSBCFG_TOCAL                   USB_OTG_GUSBCFG_TOCAL_Msk      /*!< FS timeout calibration */
 #define USB_OTG_GUSBCFG_TOCAL_0                 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
 #define USB_OTG_GUSBCFG_TOCAL_1                 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
 #define USB_OTG_GUSBCFG_TOCAL_2                 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
-#define USB_OTG_GUSBCFG_PHYSEL_Pos              (6U)                           
+#define USB_OTG_GUSBCFG_PHYSEL_Pos              (6U)
 #define USB_OTG_GUSBCFG_PHYSEL_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
 #define USB_OTG_GUSBCFG_PHYSEL                  USB_OTG_GUSBCFG_PHYSEL_Msk     /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP_Pos              (8U)                           
+#define USB_OTG_GUSBCFG_SRPCAP_Pos              (8U)
 #define USB_OTG_GUSBCFG_SRPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
 #define USB_OTG_GUSBCFG_SRPCAP                  USB_OTG_GUSBCFG_SRPCAP_Msk     /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP_Pos              (9U)                           
+#define USB_OTG_GUSBCFG_HNPCAP_Pos              (9U)
 #define USB_OTG_GUSBCFG_HNPCAP_Msk              (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
 #define USB_OTG_GUSBCFG_HNPCAP                  USB_OTG_GUSBCFG_HNPCAP_Msk     /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT_Pos                (10U)                          
+#define USB_OTG_GUSBCFG_TRDT_Pos                (10U)
 #define USB_OTG_GUSBCFG_TRDT_Msk                (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
 #define USB_OTG_GUSBCFG_TRDT                    USB_OTG_GUSBCFG_TRDT_Msk       /*!< USB turnaround time */
 #define USB_OTG_GUSBCFG_TRDT_0                  (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
 #define USB_OTG_GUSBCFG_TRDT_1                  (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
 #define USB_OTG_GUSBCFG_TRDT_2                  (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
 #define USB_OTG_GUSBCFG_TRDT_3                  (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
-#define USB_OTG_GUSBCFG_PHYLPCS_Pos             (15U)                          
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos             (15U)
 #define USB_OTG_GUSBCFG_PHYLPCS_Msk             (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
 #define USB_OTG_GUSBCFG_PHYLPCS                 USB_OTG_GUSBCFG_PHYLPCS_Msk    /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS_Pos            (17U)                          
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos            (17U)
 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk            (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
 #define USB_OTG_GUSBCFG_ULPIFSLS                USB_OTG_GUSBCFG_ULPIFSLS_Msk   /*!< ULPI FS/LS select */
-#define USB_OTG_GUSBCFG_ULPIAR_Pos              (18U)                          
+#define USB_OTG_GUSBCFG_ULPIAR_Pos              (18U)
 #define USB_OTG_GUSBCFG_ULPIAR_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
 #define USB_OTG_GUSBCFG_ULPIAR                  USB_OTG_GUSBCFG_ULPIAR_Msk     /*!< ULPI Auto-resume */
-#define USB_OTG_GUSBCFG_ULPICSM_Pos             (19U)                          
+#define USB_OTG_GUSBCFG_ULPICSM_Pos             (19U)
 #define USB_OTG_GUSBCFG_ULPICSM_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
 #define USB_OTG_GUSBCFG_ULPICSM                 USB_OTG_GUSBCFG_ULPICSM_Msk    /*!< ULPI Clock SuspendM */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos          (20U)                          
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos          (20U)
 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
 #define USB_OTG_GUSBCFG_ULPIEVBUSD              USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos          (21U)                          
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos          (21U)
 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk          (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
 #define USB_OTG_GUSBCFG_ULPIEVBUSI              USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
-#define USB_OTG_GUSBCFG_TSDPS_Pos               (22U)                          
+#define USB_OTG_GUSBCFG_TSDPS_Pos               (22U)
 #define USB_OTG_GUSBCFG_TSDPS_Msk               (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
 #define USB_OTG_GUSBCFG_TSDPS                   USB_OTG_GUSBCFG_TSDPS_Msk      /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI_Pos                (23U)                          
+#define USB_OTG_GUSBCFG_PCCI_Pos                (23U)
 #define USB_OTG_GUSBCFG_PCCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
 #define USB_OTG_GUSBCFG_PCCI                    USB_OTG_GUSBCFG_PCCI_Msk       /*!< Indicator complement */
-#define USB_OTG_GUSBCFG_PTCI_Pos                (24U)                          
+#define USB_OTG_GUSBCFG_PTCI_Pos                (24U)
 #define USB_OTG_GUSBCFG_PTCI_Msk                (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
 #define USB_OTG_GUSBCFG_PTCI                    USB_OTG_GUSBCFG_PTCI_Msk       /*!< Indicator pass through */
-#define USB_OTG_GUSBCFG_ULPIIPD_Pos             (25U)                          
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos             (25U)
 #define USB_OTG_GUSBCFG_ULPIIPD_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
 #define USB_OTG_GUSBCFG_ULPIIPD                 USB_OTG_GUSBCFG_ULPIIPD_Msk    /*!< ULPI interface protect disable */
-#define USB_OTG_GUSBCFG_FHMOD_Pos               (29U)                          
+#define USB_OTG_GUSBCFG_FHMOD_Pos               (29U)
 #define USB_OTG_GUSBCFG_FHMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
 #define USB_OTG_GUSBCFG_FHMOD                   USB_OTG_GUSBCFG_FHMOD_Msk      /*!< Forced host mode */
-#define USB_OTG_GUSBCFG_FDMOD_Pos               (30U)                          
+#define USB_OTG_GUSBCFG_FDMOD_Pos               (30U)
 #define USB_OTG_GUSBCFG_FDMOD_Msk               (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
 #define USB_OTG_GUSBCFG_FDMOD                   USB_OTG_GUSBCFG_FDMOD_Msk      /*!< Forced peripheral mode */
-#define USB_OTG_GUSBCFG_CTXPKT_Pos              (31U)                          
+#define USB_OTG_GUSBCFG_CTXPKT_Pos              (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk              (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
 #define USB_OTG_GUSBCFG_CTXPKT                  USB_OTG_GUSBCFG_CTXPKT_Msk     /*!< Corrupt Tx packet */
 
 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST_Pos               (0U)                           
+#define USB_OTG_GRSTCTL_CSRST_Pos               (0U)
 #define USB_OTG_GRSTCTL_CSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
 #define USB_OTG_GRSTCTL_CSRST                   USB_OTG_GRSTCTL_CSRST_Msk      /*!< Core soft reset */
-#define USB_OTG_GRSTCTL_HSRST_Pos               (1U)                           
+#define USB_OTG_GRSTCTL_HSRST_Pos               (1U)
 #define USB_OTG_GRSTCTL_HSRST_Msk               (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
 #define USB_OTG_GRSTCTL_HSRST                   USB_OTG_GRSTCTL_HSRST_Msk      /*!< HCLK soft reset */
-#define USB_OTG_GRSTCTL_FCRST_Pos               (2U)                           
+#define USB_OTG_GRSTCTL_FCRST_Pos               (2U)
 #define USB_OTG_GRSTCTL_FCRST_Msk               (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
 #define USB_OTG_GRSTCTL_FCRST                   USB_OTG_GRSTCTL_FCRST_Msk      /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH_Pos             (4U)                           
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos             (4U)
 #define USB_OTG_GRSTCTL_RXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
 #define USB_OTG_GRSTCTL_RXFFLSH                 USB_OTG_GRSTCTL_RXFFLSH_Msk    /*!< RxFIFO flush */
-#define USB_OTG_GRSTCTL_TXFFLSH_Pos             (5U)                           
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos             (5U)
 #define USB_OTG_GRSTCTL_TXFFLSH_Msk             (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
 #define USB_OTG_GRSTCTL_TXFFLSH                 USB_OTG_GRSTCTL_TXFFLSH_Msk    /*!< TxFIFO flush */
 
 
-#define USB_OTG_GRSTCTL_TXFNUM_Pos              (6U)                           
+#define USB_OTG_GRSTCTL_TXFNUM_Pos              (6U)
 #define USB_OTG_GRSTCTL_TXFNUM_Msk              (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
 #define USB_OTG_GRSTCTL_TXFNUM                  USB_OTG_GRSTCTL_TXFNUM_Msk     /*!< TxFIFO number */
 #define USB_OTG_GRSTCTL_TXFNUM_0                (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
@@ -462,44 +462,44 @@ typedef struct
 #define USB_OTG_GRSTCTL_TXFNUM_2                (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
 #define USB_OTG_GRSTCTL_TXFNUM_3                (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
 #define USB_OTG_GRSTCTL_TXFNUM_4                (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GRSTCTL_DMAREQ_Pos              (30U)                          
+#define USB_OTG_GRSTCTL_DMAREQ_Pos              (30U)
 #define USB_OTG_GRSTCTL_DMAREQ_Msk              (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
 #define USB_OTG_GRSTCTL_DMAREQ                  USB_OTG_GRSTCTL_DMAREQ_Msk     /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL_Pos              (31U)                          
+#define USB_OTG_GRSTCTL_AHBIDL_Pos              (31U)
 #define USB_OTG_GRSTCTL_AHBIDL_Msk              (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
 #define USB_OTG_GRSTCTL_AHBIDL                  USB_OTG_GRSTCTL_AHBIDL_Msk     /*!< AHB master idle */
 
 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM_Pos               (0U)                           
+#define USB_OTG_DIEPMSK_XFRCM_Pos               (0U)
 #define USB_OTG_DIEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
 #define USB_OTG_DIEPMSK_XFRCM                   USB_OTG_DIEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPMSK_EPDM_Pos                (1U)                           
+#define USB_OTG_DIEPMSK_EPDM_Pos                (1U)
 #define USB_OTG_DIEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
 #define USB_OTG_DIEPMSK_EPDM                    USB_OTG_DIEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPMSK_TOM_Pos                 (3U)                           
+#define USB_OTG_DIEPMSK_TOM_Pos                 (3U)
 #define USB_OTG_DIEPMSK_TOM_Msk                 (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
 #define USB_OTG_DIEPMSK_TOM                     USB_OTG_DIEPMSK_TOM_Msk        /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos           (4U)                           
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos           (4U)
 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk           (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
 #define USB_OTG_DIEPMSK_ITTXFEMSK               USB_OTG_DIEPMSK_ITTXFEMSK_Msk  /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPMSK_INEPNMM_Pos             (5U)                           
+#define USB_OTG_DIEPMSK_INEPNMM_Pos             (5U)
 #define USB_OTG_DIEPMSK_INEPNMM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
 #define USB_OTG_DIEPMSK_INEPNMM                 USB_OTG_DIEPMSK_INEPNMM_Msk    /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPMSK_INEPNEM_Pos             (6U)                           
+#define USB_OTG_DIEPMSK_INEPNEM_Pos             (6U)
 #define USB_OTG_DIEPMSK_INEPNEM_Msk             (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
 #define USB_OTG_DIEPMSK_INEPNEM                 USB_OTG_DIEPMSK_INEPNEM_Msk    /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPMSK_TXFURM_Pos              (8U)                           
+#define USB_OTG_DIEPMSK_TXFURM_Pos              (8U)
 #define USB_OTG_DIEPMSK_TXFURM_Msk              (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
 #define USB_OTG_DIEPMSK_TXFURM                  USB_OTG_DIEPMSK_TXFURM_Msk     /*!< FIFO underrun mask */
-#define USB_OTG_DIEPMSK_BIM_Pos                 (9U)                           
+#define USB_OTG_DIEPMSK_BIM_Pos                 (9U)
 #define USB_OTG_DIEPMSK_BIM_Msk                 (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
 #define USB_OTG_DIEPMSK_BIM                     USB_OTG_DIEPMSK_BIM_Msk        /*!< BNA interrupt mask */
 
 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL_Pos            (0U)                           
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos            (0U)
 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk            (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_HPTXSTS_PTXFSAVL                USB_OTG_HPTXSTS_PTXFSAVL_Msk   /*!< Periodic transmit data FIFO space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_Pos             (16U)                          
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos             (16U)
 #define USB_OTG_HPTXSTS_PTXQSAV_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
 #define USB_OTG_HPTXSTS_PTXQSAV                 USB_OTG_HPTXSTS_PTXQSAV_Msk    /*!< Periodic transmit request queue space available */
 #define USB_OTG_HPTXSTS_PTXQSAV_0               (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
@@ -511,7 +511,7 @@ typedef struct
 #define USB_OTG_HPTXSTS_PTXQSAV_6               (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
 #define USB_OTG_HPTXSTS_PTXQSAV_7               (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
 
-#define USB_OTG_HPTXSTS_PTXQTOP_Pos             (24U)                          
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos             (24U)
 #define USB_OTG_HPTXSTS_PTXQTOP_Msk             (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
 #define USB_OTG_HPTXSTS_PTXQTOP                 USB_OTG_HPTXSTS_PTXQTOP_Msk    /*!< Top of the periodic transmit request queue */
 #define USB_OTG_HPTXSTS_PTXQTOP_0               (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
@@ -524,36 +524,36 @@ typedef struct
 #define USB_OTG_HPTXSTS_PTXQTOP_7               (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
 
 /********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT_Pos                 (0U)                           
+#define USB_OTG_HAINT_HAINT_Pos                 (0U)
 #define USB_OTG_HAINT_HAINT_Msk                 (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_HAINT_HAINT                     USB_OTG_HAINT_HAINT_Msk        /*!< Channel interrupts */
 
 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM_Pos               (0U)                           
+#define USB_OTG_DOEPMSK_XFRCM_Pos               (0U)
 #define USB_OTG_DOEPMSK_XFRCM_Msk               (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
 #define USB_OTG_DOEPMSK_XFRCM                   USB_OTG_DOEPMSK_XFRCM_Msk      /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPMSK_EPDM_Pos                (1U)                           
+#define USB_OTG_DOEPMSK_EPDM_Pos                (1U)
 #define USB_OTG_DOEPMSK_EPDM_Msk                (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
 #define USB_OTG_DOEPMSK_EPDM                    USB_OTG_DOEPMSK_EPDM_Msk       /*!< Endpoint disabled interrupt mask */
 #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
 #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
 #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
-#define USB_OTG_DOEPMSK_STUPM_Pos               (3U)                           
+#define USB_OTG_DOEPMSK_STUPM_Pos               (3U)
 #define USB_OTG_DOEPMSK_STUPM_Msk               (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
 #define USB_OTG_DOEPMSK_STUPM                   USB_OTG_DOEPMSK_STUPM_Msk      /*!< SETUP phase done mask */
-#define USB_OTG_DOEPMSK_OTEPDM_Pos              (4U)                           
+#define USB_OTG_DOEPMSK_OTEPDM_Pos              (4U)
 #define USB_OTG_DOEPMSK_OTEPDM_Msk              (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
 #define USB_OTG_DOEPMSK_OTEPDM                  USB_OTG_DOEPMSK_OTEPDM_Msk     /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
 #define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP_Pos             (6U)                           
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos             (6U)
 #define USB_OTG_DOEPMSK_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
 #define USB_OTG_DOEPMSK_B2BSTUP                 USB_OTG_DOEPMSK_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received mask */
-#define USB_OTG_DOEPMSK_OPEM_Pos                (8U)                           
+#define USB_OTG_DOEPMSK_OPEM_Pos                (8U)
 #define USB_OTG_DOEPMSK_OPEM_Msk                (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
 #define USB_OTG_DOEPMSK_OPEM                    USB_OTG_DOEPMSK_OPEM_Msk       /*!< OUT packet error mask */
-#define USB_OTG_DOEPMSK_BOIM_Pos                (9U)                           
+#define USB_OTG_DOEPMSK_BOIM_Pos                (9U)
 #define USB_OTG_DOEPMSK_BOIM_Msk                (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
 #define USB_OTG_DOEPMSK_BOIM                    USB_OTG_DOEPMSK_BOIM_Msk       /*!< BNA interrupt mask */
 #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
@@ -566,235 +566,235 @@ typedef struct
 #define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
 #define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD_Pos                (0U)                           
+#define USB_OTG_GINTSTS_CMOD_Pos                (0U)
 #define USB_OTG_GINTSTS_CMOD_Msk                (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
 #define USB_OTG_GINTSTS_CMOD                    USB_OTG_GINTSTS_CMOD_Msk       /*!< Current mode of operation */
-#define USB_OTG_GINTSTS_MMIS_Pos                (1U)                           
+#define USB_OTG_GINTSTS_MMIS_Pos                (1U)
 #define USB_OTG_GINTSTS_MMIS_Msk                (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
 #define USB_OTG_GINTSTS_MMIS                    USB_OTG_GINTSTS_MMIS_Msk       /*!< Mode mismatch interrupt */
-#define USB_OTG_GINTSTS_OTGINT_Pos              (2U)                           
+#define USB_OTG_GINTSTS_OTGINT_Pos              (2U)
 #define USB_OTG_GINTSTS_OTGINT_Msk              (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
 #define USB_OTG_GINTSTS_OTGINT                  USB_OTG_GINTSTS_OTGINT_Msk     /*!< OTG interrupt */
-#define USB_OTG_GINTSTS_SOF_Pos                 (3U)                           
+#define USB_OTG_GINTSTS_SOF_Pos                 (3U)
 #define USB_OTG_GINTSTS_SOF_Msk                 (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
 #define USB_OTG_GINTSTS_SOF                     USB_OTG_GINTSTS_SOF_Msk        /*!< Start of frame */
-#define USB_OTG_GINTSTS_RXFLVL_Pos              (4U)                           
+#define USB_OTG_GINTSTS_RXFLVL_Pos              (4U)
 #define USB_OTG_GINTSTS_RXFLVL_Msk              (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
 #define USB_OTG_GINTSTS_RXFLVL                  USB_OTG_GINTSTS_RXFLVL_Msk     /*!< RxFIFO nonempty */
-#define USB_OTG_GINTSTS_NPTXFE_Pos              (5U)                           
+#define USB_OTG_GINTSTS_NPTXFE_Pos              (5U)
 #define USB_OTG_GINTSTS_NPTXFE_Msk              (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
 #define USB_OTG_GINTSTS_NPTXFE                  USB_OTG_GINTSTS_NPTXFE_Msk     /*!< Nonperiodic TxFIFO empty */
-#define USB_OTG_GINTSTS_GINAKEFF_Pos            (6U)                           
+#define USB_OTG_GINTSTS_GINAKEFF_Pos            (6U)
 #define USB_OTG_GINTSTS_GINAKEFF_Msk            (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
 #define USB_OTG_GINTSTS_GINAKEFF                USB_OTG_GINTSTS_GINAKEFF_Msk   /*!< Global IN nonperiodic NAK effective */
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos          (7U)                           
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos          (7U)
 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk          (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
 #define USB_OTG_GINTSTS_BOUTNAKEFF              USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
-#define USB_OTG_GINTSTS_ESUSP_Pos               (10U)                          
+#define USB_OTG_GINTSTS_ESUSP_Pos               (10U)
 #define USB_OTG_GINTSTS_ESUSP_Msk               (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
 #define USB_OTG_GINTSTS_ESUSP                   USB_OTG_GINTSTS_ESUSP_Msk      /*!< Early suspend */
-#define USB_OTG_GINTSTS_USBSUSP_Pos             (11U)                          
+#define USB_OTG_GINTSTS_USBSUSP_Pos             (11U)
 #define USB_OTG_GINTSTS_USBSUSP_Msk             (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
 #define USB_OTG_GINTSTS_USBSUSP                 USB_OTG_GINTSTS_USBSUSP_Msk    /*!< USB suspend */
-#define USB_OTG_GINTSTS_USBRST_Pos              (12U)                          
+#define USB_OTG_GINTSTS_USBRST_Pos              (12U)
 #define USB_OTG_GINTSTS_USBRST_Msk              (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
 #define USB_OTG_GINTSTS_USBRST                  USB_OTG_GINTSTS_USBRST_Msk     /*!< USB reset */
-#define USB_OTG_GINTSTS_ENUMDNE_Pos             (13U)                          
+#define USB_OTG_GINTSTS_ENUMDNE_Pos             (13U)
 #define USB_OTG_GINTSTS_ENUMDNE_Msk             (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
 #define USB_OTG_GINTSTS_ENUMDNE                 USB_OTG_GINTSTS_ENUMDNE_Msk    /*!< Enumeration done */
-#define USB_OTG_GINTSTS_ISOODRP_Pos             (14U)                          
+#define USB_OTG_GINTSTS_ISOODRP_Pos             (14U)
 #define USB_OTG_GINTSTS_ISOODRP_Msk             (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
 #define USB_OTG_GINTSTS_ISOODRP                 USB_OTG_GINTSTS_ISOODRP_Msk    /*!< Isochronous OUT packet dropped interrupt */
-#define USB_OTG_GINTSTS_EOPF_Pos                (15U)                          
+#define USB_OTG_GINTSTS_EOPF_Pos                (15U)
 #define USB_OTG_GINTSTS_EOPF_Msk                (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
 #define USB_OTG_GINTSTS_EOPF                    USB_OTG_GINTSTS_EOPF_Msk       /*!< End of periodic frame interrupt */
-#define USB_OTG_GINTSTS_IEPINT_Pos              (18U)                          
+#define USB_OTG_GINTSTS_IEPINT_Pos              (18U)
 #define USB_OTG_GINTSTS_IEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
 #define USB_OTG_GINTSTS_IEPINT                  USB_OTG_GINTSTS_IEPINT_Msk     /*!< IN endpoint interrupt */
-#define USB_OTG_GINTSTS_OEPINT_Pos              (19U)                          
+#define USB_OTG_GINTSTS_OEPINT_Pos              (19U)
 #define USB_OTG_GINTSTS_OEPINT_Msk              (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
 #define USB_OTG_GINTSTS_OEPINT                  USB_OTG_GINTSTS_OEPINT_Msk     /*!< OUT endpoint interrupt */
-#define USB_OTG_GINTSTS_IISOIXFR_Pos            (20U)                          
+#define USB_OTG_GINTSTS_IISOIXFR_Pos            (20U)
 #define USB_OTG_GINTSTS_IISOIXFR_Msk            (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
 #define USB_OTG_GINTSTS_IISOIXFR                USB_OTG_GINTSTS_IISOIXFR_Msk   /*!< Incomplete isochronous IN transfer */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)                          
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)
 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT       USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
-#define USB_OTG_GINTSTS_DATAFSUSP_Pos           (22U)                          
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos           (22U)
 #define USB_OTG_GINTSTS_DATAFSUSP_Msk           (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
 #define USB_OTG_GINTSTS_DATAFSUSP               USB_OTG_GINTSTS_DATAFSUSP_Msk  /*!< Data fetch suspended */
-#define USB_OTG_GINTSTS_HPRTINT_Pos             (24U)                          
+#define USB_OTG_GINTSTS_HPRTINT_Pos             (24U)
 #define USB_OTG_GINTSTS_HPRTINT_Msk             (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
 #define USB_OTG_GINTSTS_HPRTINT                 USB_OTG_GINTSTS_HPRTINT_Msk    /*!< Host port interrupt */
-#define USB_OTG_GINTSTS_HCINT_Pos               (25U)                          
+#define USB_OTG_GINTSTS_HCINT_Pos               (25U)
 #define USB_OTG_GINTSTS_HCINT_Msk               (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
 #define USB_OTG_GINTSTS_HCINT                   USB_OTG_GINTSTS_HCINT_Msk      /*!< Host channels interrupt */
-#define USB_OTG_GINTSTS_PTXFE_Pos               (26U)                          
+#define USB_OTG_GINTSTS_PTXFE_Pos               (26U)
 #define USB_OTG_GINTSTS_PTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
 #define USB_OTG_GINTSTS_PTXFE                   USB_OTG_GINTSTS_PTXFE_Msk      /*!< Periodic TxFIFO empty */
-#define USB_OTG_GINTSTS_CIDSCHG_Pos             (28U)                          
+#define USB_OTG_GINTSTS_CIDSCHG_Pos             (28U)
 #define USB_OTG_GINTSTS_CIDSCHG_Msk             (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
 #define USB_OTG_GINTSTS_CIDSCHG                 USB_OTG_GINTSTS_CIDSCHG_Msk    /*!< Connector ID status change */
-#define USB_OTG_GINTSTS_DISCINT_Pos             (29U)                          
+#define USB_OTG_GINTSTS_DISCINT_Pos             (29U)
 #define USB_OTG_GINTSTS_DISCINT_Msk             (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
 #define USB_OTG_GINTSTS_DISCINT                 USB_OTG_GINTSTS_DISCINT_Msk    /*!< Disconnect detected interrupt */
-#define USB_OTG_GINTSTS_SRQINT_Pos              (30U)                          
+#define USB_OTG_GINTSTS_SRQINT_Pos              (30U)
 #define USB_OTG_GINTSTS_SRQINT_Msk              (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
 #define USB_OTG_GINTSTS_SRQINT                  USB_OTG_GINTSTS_SRQINT_Msk     /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT_Pos              (31U)                          
+#define USB_OTG_GINTSTS_WKUINT_Pos              (31U)
 #define USB_OTG_GINTSTS_WKUINT_Msk              (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
 #define USB_OTG_GINTSTS_WKUINT                  USB_OTG_GINTSTS_WKUINT_Msk     /*!< Resume/remote wakeup detected interrupt */
 
 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM_Pos               (1U)                           
+#define USB_OTG_GINTMSK_MMISM_Pos               (1U)
 #define USB_OTG_GINTMSK_MMISM_Msk               (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
 #define USB_OTG_GINTMSK_MMISM                   USB_OTG_GINTMSK_MMISM_Msk      /*!< Mode mismatch interrupt mask */
-#define USB_OTG_GINTMSK_OTGINT_Pos              (2U)                           
+#define USB_OTG_GINTMSK_OTGINT_Pos              (2U)
 #define USB_OTG_GINTMSK_OTGINT_Msk              (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
 #define USB_OTG_GINTMSK_OTGINT                  USB_OTG_GINTMSK_OTGINT_Msk     /*!< OTG interrupt mask */
-#define USB_OTG_GINTMSK_SOFM_Pos                (3U)                           
+#define USB_OTG_GINTMSK_SOFM_Pos                (3U)
 #define USB_OTG_GINTMSK_SOFM_Msk                (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
 #define USB_OTG_GINTMSK_SOFM                    USB_OTG_GINTMSK_SOFM_Msk       /*!< Start of frame mask */
-#define USB_OTG_GINTMSK_RXFLVLM_Pos             (4U)                           
+#define USB_OTG_GINTMSK_RXFLVLM_Pos             (4U)
 #define USB_OTG_GINTMSK_RXFLVLM_Msk             (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
 #define USB_OTG_GINTMSK_RXFLVLM                 USB_OTG_GINTMSK_RXFLVLM_Msk    /*!< Receive FIFO nonempty mask */
-#define USB_OTG_GINTMSK_NPTXFEM_Pos             (5U)                           
+#define USB_OTG_GINTMSK_NPTXFEM_Pos             (5U)
 #define USB_OTG_GINTMSK_NPTXFEM_Msk             (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
 #define USB_OTG_GINTMSK_NPTXFEM                 USB_OTG_GINTMSK_NPTXFEM_Msk    /*!< Nonperiodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_GINAKEFFM_Pos           (6U)                           
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos           (6U)
 #define USB_OTG_GINTMSK_GINAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
 #define USB_OTG_GINTMSK_GINAKEFFM               USB_OTG_GINTMSK_GINAKEFFM_Msk  /*!< Global nonperiodic IN NAK effective mask */
-#define USB_OTG_GINTMSK_GONAKEFFM_Pos           (7U)                           
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos           (7U)
 #define USB_OTG_GINTMSK_GONAKEFFM_Msk           (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
 #define USB_OTG_GINTMSK_GONAKEFFM               USB_OTG_GINTMSK_GONAKEFFM_Msk  /*!< Global OUT NAK effective mask */
-#define USB_OTG_GINTMSK_ESUSPM_Pos              (10U)                          
+#define USB_OTG_GINTMSK_ESUSPM_Pos              (10U)
 #define USB_OTG_GINTMSK_ESUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
 #define USB_OTG_GINTMSK_ESUSPM                  USB_OTG_GINTMSK_ESUSPM_Msk     /*!< Early suspend mask */
-#define USB_OTG_GINTMSK_USBSUSPM_Pos            (11U)                          
+#define USB_OTG_GINTMSK_USBSUSPM_Pos            (11U)
 #define USB_OTG_GINTMSK_USBSUSPM_Msk            (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
 #define USB_OTG_GINTMSK_USBSUSPM                USB_OTG_GINTMSK_USBSUSPM_Msk   /*!< USB suspend mask */
-#define USB_OTG_GINTMSK_USBRST_Pos              (12U)                          
+#define USB_OTG_GINTMSK_USBRST_Pos              (12U)
 #define USB_OTG_GINTMSK_USBRST_Msk              (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
 #define USB_OTG_GINTMSK_USBRST                  USB_OTG_GINTMSK_USBRST_Msk     /*!< USB reset mask */
-#define USB_OTG_GINTMSK_ENUMDNEM_Pos            (13U)                          
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos            (13U)
 #define USB_OTG_GINTMSK_ENUMDNEM_Msk            (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
 #define USB_OTG_GINTMSK_ENUMDNEM                USB_OTG_GINTMSK_ENUMDNEM_Msk   /*!< Enumeration done mask */
-#define USB_OTG_GINTMSK_ISOODRPM_Pos            (14U)                          
+#define USB_OTG_GINTMSK_ISOODRPM_Pos            (14U)
 #define USB_OTG_GINTMSK_ISOODRPM_Msk            (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
 #define USB_OTG_GINTMSK_ISOODRPM                USB_OTG_GINTMSK_ISOODRPM_Msk   /*!< Isochronous OUT packet dropped interrupt mask */
-#define USB_OTG_GINTMSK_EOPFM_Pos               (15U)                          
+#define USB_OTG_GINTMSK_EOPFM_Pos               (15U)
 #define USB_OTG_GINTMSK_EOPFM_Msk               (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
 #define USB_OTG_GINTMSK_EOPFM                   USB_OTG_GINTMSK_EOPFM_Msk      /*!< End of periodic frame interrupt mask */
-#define USB_OTG_GINTMSK_EPMISM_Pos              (17U)                          
+#define USB_OTG_GINTMSK_EPMISM_Pos              (17U)
 #define USB_OTG_GINTMSK_EPMISM_Msk              (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
 #define USB_OTG_GINTMSK_EPMISM                  USB_OTG_GINTMSK_EPMISM_Msk     /*!< Endpoint mismatch interrupt mask */
-#define USB_OTG_GINTMSK_IEPINT_Pos              (18U)                          
+#define USB_OTG_GINTMSK_IEPINT_Pos              (18U)
 #define USB_OTG_GINTMSK_IEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
 #define USB_OTG_GINTMSK_IEPINT                  USB_OTG_GINTMSK_IEPINT_Msk     /*!< IN endpoints interrupt mask */
-#define USB_OTG_GINTMSK_OEPINT_Pos              (19U)                          
+#define USB_OTG_GINTMSK_OEPINT_Pos              (19U)
 #define USB_OTG_GINTMSK_OEPINT_Msk              (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
 #define USB_OTG_GINTMSK_OEPINT                  USB_OTG_GINTMSK_OEPINT_Msk     /*!< OUT endpoints interrupt mask */
-#define USB_OTG_GINTMSK_IISOIXFRM_Pos           (20U)                          
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos           (20U)
 #define USB_OTG_GINTMSK_IISOIXFRM_Msk           (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
 #define USB_OTG_GINTMSK_IISOIXFRM               USB_OTG_GINTMSK_IISOIXFRM_Msk  /*!< Incomplete isochronous IN transfer mask */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos     (21U)                          
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos     (21U)
 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk     (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM         USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
-#define USB_OTG_GINTMSK_FSUSPM_Pos              (22U)                          
+#define USB_OTG_GINTMSK_FSUSPM_Pos              (22U)
 #define USB_OTG_GINTMSK_FSUSPM_Msk              (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
 #define USB_OTG_GINTMSK_FSUSPM                  USB_OTG_GINTMSK_FSUSPM_Msk     /*!< Data fetch suspended mask */
-#define USB_OTG_GINTMSK_PRTIM_Pos               (24U)                          
+#define USB_OTG_GINTMSK_PRTIM_Pos               (24U)
 #define USB_OTG_GINTMSK_PRTIM_Msk               (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
 #define USB_OTG_GINTMSK_PRTIM                   USB_OTG_GINTMSK_PRTIM_Msk      /*!< Host port interrupt mask */
-#define USB_OTG_GINTMSK_HCIM_Pos                (25U)                          
+#define USB_OTG_GINTMSK_HCIM_Pos                (25U)
 #define USB_OTG_GINTMSK_HCIM_Msk                (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
 #define USB_OTG_GINTMSK_HCIM                    USB_OTG_GINTMSK_HCIM_Msk       /*!< Host channels interrupt mask */
-#define USB_OTG_GINTMSK_PTXFEM_Pos              (26U)                          
+#define USB_OTG_GINTMSK_PTXFEM_Pos              (26U)
 #define USB_OTG_GINTMSK_PTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
 #define USB_OTG_GINTMSK_PTXFEM                  USB_OTG_GINTMSK_PTXFEM_Msk     /*!< Periodic TxFIFO empty mask */
-#define USB_OTG_GINTMSK_CIDSCHGM_Pos            (28U)                          
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos            (28U)
 #define USB_OTG_GINTMSK_CIDSCHGM_Msk            (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
 #define USB_OTG_GINTMSK_CIDSCHGM                USB_OTG_GINTMSK_CIDSCHGM_Msk   /*!< Connector ID status change mask */
-#define USB_OTG_GINTMSK_DISCINT_Pos             (29U)                          
+#define USB_OTG_GINTMSK_DISCINT_Pos             (29U)
 #define USB_OTG_GINTMSK_DISCINT_Msk             (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
 #define USB_OTG_GINTMSK_DISCINT                 USB_OTG_GINTMSK_DISCINT_Msk    /*!< Disconnect detected interrupt mask */
-#define USB_OTG_GINTMSK_SRQIM_Pos               (30U)                          
+#define USB_OTG_GINTMSK_SRQIM_Pos               (30U)
 #define USB_OTG_GINTMSK_SRQIM_Msk               (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
 #define USB_OTG_GINTMSK_SRQIM                   USB_OTG_GINTMSK_SRQIM_Msk      /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM_Pos                (31U)                          
+#define USB_OTG_GINTMSK_WUIM_Pos                (31U)
 #define USB_OTG_GINTMSK_WUIM_Msk                (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
 #define USB_OTG_GINTMSK_WUIM                    USB_OTG_GINTMSK_WUIM_Msk       /*!< Resume/remote wakeup detected interrupt mask */
 
 /********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT_Pos                (0U)                           
+#define USB_OTG_DAINT_IEPINT_Pos                (0U)
 #define USB_OTG_DAINT_IEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_DAINT_IEPINT                    USB_OTG_DAINT_IEPINT_Msk       /*!< IN endpoint interrupt bits */
-#define USB_OTG_DAINT_OEPINT_Pos                (16U)                          
+#define USB_OTG_DAINT_OEPINT_Pos                (16U)
 #define USB_OTG_DAINT_OEPINT_Msk                (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
 #define USB_OTG_DAINT_OEPINT                    USB_OTG_DAINT_OEPINT_Msk       /*!< OUT endpoint interrupt bits */
 
 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM_Pos             (0U)                           
+#define USB_OTG_HAINTMSK_HAINTM_Pos             (0U)
 #define USB_OTG_HAINTMSK_HAINTM_Msk             (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_HAINTMSK_HAINTM                 USB_OTG_HAINTMSK_HAINTM_Msk    /*!< Channel interrupt mask */
 
 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM_Pos               (0U)                           
+#define USB_OTG_GRXSTSP_EPNUM_Pos               (0U)
 #define USB_OTG_GRXSTSP_EPNUM_Msk               (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
 #define USB_OTG_GRXSTSP_EPNUM                   USB_OTG_GRXSTSP_EPNUM_Msk      /*!< IN EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_BCNT_Pos                (4U)                           
+#define USB_OTG_GRXSTSP_BCNT_Pos                (4U)
 #define USB_OTG_GRXSTSP_BCNT_Msk                (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
 #define USB_OTG_GRXSTSP_BCNT                    USB_OTG_GRXSTSP_BCNT_Msk       /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID_Pos                (15U)                          
+#define USB_OTG_GRXSTSP_DPID_Pos                (15U)
 #define USB_OTG_GRXSTSP_DPID_Msk                (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
 #define USB_OTG_GRXSTSP_DPID                    USB_OTG_GRXSTSP_DPID_Msk       /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS_Pos              (17U)                          
+#define USB_OTG_GRXSTSP_PKTSTS_Pos              (17U)
 #define USB_OTG_GRXSTSP_PKTSTS_Msk              (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
 #define USB_OTG_GRXSTSP_PKTSTS                  USB_OTG_GRXSTSP_PKTSTS_Msk     /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM_Pos               (0U)                           
+#define USB_OTG_DAINTMSK_IEPM_Pos               (0U)
 #define USB_OTG_DAINTMSK_IEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_DAINTMSK_IEPM                   USB_OTG_DAINTMSK_IEPM_Msk      /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM_Pos               (16U)                          
+#define USB_OTG_DAINTMSK_OEPM_Pos               (16U)
 #define USB_OTG_DAINTMSK_OEPM_Msk               (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
 #define USB_OTG_DAINTMSK_OEPM                   USB_OTG_DAINTMSK_OEPM_Msk      /*!< OUT EP interrupt mask bits */
 
 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD_Pos                (0U)                           
+#define USB_OTG_GRXFSIZ_RXFD_Pos                (0U)
 #define USB_OTG_GRXFSIZ_RXFD_Msk                (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_GRXFSIZ_RXFD                    USB_OTG_GRXFSIZ_RXFD_Msk       /*!< RxFIFO depth */
 
 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT_Pos             (0U)                           
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos             (0U)
 #define USB_OTG_DVBUSDIS_VBUSDT_Msk             (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_DVBUSDIS_VBUSDT                 USB_OTG_DVBUSDIS_VBUSDT_Msk    /*!< Device VBUS discharge time */
 
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA_Pos                     (0U)                           
+#define USB_OTG_NPTXFSA_Pos                     (0U)
 #define USB_OTG_NPTXFSA_Msk                     (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_NPTXFSA                         USB_OTG_NPTXFSA_Msk            /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD_Pos                      (16U)                          
+#define USB_OTG_NPTXFD_Pos                      (16U)
 #define USB_OTG_NPTXFD_Msk                      (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
 #define USB_OTG_NPTXFD                          USB_OTG_NPTXFD_Msk             /*!< Nonperiodic TxFIFO depth */
-#define USB_OTG_TX0FSA_Pos                      (0U)                           
+#define USB_OTG_TX0FSA_Pos                      (0U)
 #define USB_OTG_TX0FSA_Msk                      (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_TX0FSA                          USB_OTG_TX0FSA_Msk             /*!< Endpoint 0 transmit RAM start address */
-#define USB_OTG_TX0FD_Pos                       (16U)                          
+#define USB_OTG_TX0FD_Pos                       (16U)
 #define USB_OTG_TX0FD_Msk                       (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
 #define USB_OTG_TX0FD                           USB_OTG_TX0FD_Msk              /*!< Endpoint 0 TxFIFO depth */
 
 /********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP_Pos           (0U)                           
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos           (0U)
 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk           (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
 #define USB_OTG_DVBUSPULSE_DVBUSP               USB_OTG_DVBUSPULSE_DVBUSP_Msk  /*!< Device VBUS pulsing time */
 
 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos           (0U)                           
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos           (0U)
 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk           (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_GNPTXSTS_NPTXFSAV               USB_OTG_GNPTXSTS_NPTXFSAV_Msk  /*!< Nonperiodic TxFIFO space available */
 
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos           (16U)                          
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos           (16U)
 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk           (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
 #define USB_OTG_GNPTXSTS_NPTQXSAV               USB_OTG_GNPTXSTS_NPTQXSAV_Msk  /*!< Nonperiodic transmit request queue space available */
 #define USB_OTG_GNPTXSTS_NPTQXSAV_0             (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
@@ -806,7 +806,7 @@ typedef struct
 #define USB_OTG_GNPTXSTS_NPTQXSAV_6             (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
 #define USB_OTG_GNPTXSTS_NPTQXSAV_7             (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
 
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos           (24U)                          
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos           (24U)
 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk           (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
 #define USB_OTG_GNPTXSTS_NPTXQTOP               USB_OTG_GNPTXSTS_NPTXQTOP_Msk  /*!< Top of the nonperiodic transmit request queue */
 #define USB_OTG_GNPTXSTS_NPTXQTOP_0             (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
@@ -818,14 +818,14 @@ typedef struct
 #define USB_OTG_GNPTXSTS_NPTXQTOP_6             (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
 
 /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN_Pos         (0U)                           
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos         (0U)
 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk         (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
 #define USB_OTG_DTHRCTL_NONISOTHREN             USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN_Pos            (1U)                           
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos            (1U)
 #define USB_OTG_DTHRCTL_ISOTHREN_Msk            (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
 #define USB_OTG_DTHRCTL_ISOTHREN                USB_OTG_DTHRCTL_ISOTHREN_Msk   /*!< ISO IN endpoint threshold enable */
 
-#define USB_OTG_DTHRCTL_TXTHRLEN_Pos            (2U)                           
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos            (2U)
 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
 #define USB_OTG_DTHRCTL_TXTHRLEN                USB_OTG_DTHRCTL_TXTHRLEN_Msk   /*!< Transmit threshold length */
 #define USB_OTG_DTHRCTL_TXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
@@ -837,11 +837,11 @@ typedef struct
 #define USB_OTG_DTHRCTL_TXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
 #define USB_OTG_DTHRCTL_TXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
 #define USB_OTG_DTHRCTL_TXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_DTHRCTL_RXTHREN_Pos             (16U)                          
+#define USB_OTG_DTHRCTL_RXTHREN_Pos             (16U)
 #define USB_OTG_DTHRCTL_RXTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
 #define USB_OTG_DTHRCTL_RXTHREN                 USB_OTG_DTHRCTL_RXTHREN_Msk    /*!< Receive threshold enable */
 
-#define USB_OTG_DTHRCTL_RXTHRLEN_Pos            (17U)                          
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos            (17U)
 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk            (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
 #define USB_OTG_DTHRCTL_RXTHRLEN                USB_OTG_DTHRCTL_RXTHRLEN_Msk   /*!< Receive threshold length */
 #define USB_OTG_DTHRCTL_RXTHRLEN_0              (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
@@ -853,118 +853,118 @@ typedef struct
 #define USB_OTG_DTHRCTL_RXTHRLEN_6              (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
 #define USB_OTG_DTHRCTL_RXTHRLEN_7              (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
 #define USB_OTG_DTHRCTL_RXTHRLEN_8              (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
-#define USB_OTG_DTHRCTL_ARPEN_Pos               (27U)                          
+#define USB_OTG_DTHRCTL_ARPEN_Pos               (27U)
 #define USB_OTG_DTHRCTL_ARPEN_Msk               (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
 #define USB_OTG_DTHRCTL_ARPEN                   USB_OTG_DTHRCTL_ARPEN_Msk      /*!< Arbiter parking enable */
 
 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos        (0U)                           
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos        (0U)
 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk        (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_DIEPEMPMSK_INEPTXFEM            USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
 
 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT_Pos            (1U)                           
+#define USB_OTG_DEACHINT_IEP1INT_Pos            (1U)
 #define USB_OTG_DEACHINT_IEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
 #define USB_OTG_DEACHINT_IEP1INT                USB_OTG_DEACHINT_IEP1INT_Msk   /*!< IN endpoint 1interrupt bit */
-#define USB_OTG_DEACHINT_OEP1INT_Pos            (17U)                          
+#define USB_OTG_DEACHINT_OEP1INT_Pos            (17U)
 #define USB_OTG_DEACHINT_OEP1INT_Msk            (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
 #define USB_OTG_DEACHINT_OEP1INT                USB_OTG_DEACHINT_OEP1INT_Msk   /*!< OUT endpoint 1 interrupt bit */
 
 /********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN_Pos                (16U)                          
+#define USB_OTG_GCCFG_PWRDWN_Pos                (16U)
 #define USB_OTG_GCCFG_PWRDWN_Msk                (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
 #define USB_OTG_GCCFG_PWRDWN                    USB_OTG_GCCFG_PWRDWN_Msk       /*!< Power down */
-#define USB_OTG_GCCFG_VBUSASEN_Pos              (18U)                          
+#define USB_OTG_GCCFG_VBUSASEN_Pos              (18U)
 #define USB_OTG_GCCFG_VBUSASEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
 #define USB_OTG_GCCFG_VBUSASEN                  USB_OTG_GCCFG_VBUSASEN_Msk     /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN_Pos              (19U)                          
+#define USB_OTG_GCCFG_VBUSBSEN_Pos              (19U)
 #define USB_OTG_GCCFG_VBUSBSEN_Msk              (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
 #define USB_OTG_GCCFG_VBUSBSEN                  USB_OTG_GCCFG_VBUSBSEN_Msk     /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN_Pos              (20U)                          
+#define USB_OTG_GCCFG_SOFOUTEN_Pos              (20U)
 #define USB_OTG_GCCFG_SOFOUTEN_Msk              (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
 #define USB_OTG_GCCFG_SOFOUTEN                  USB_OTG_GCCFG_SOFOUTEN_Msk     /*!< SOF output enable */
 
 /********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos        (1U)                           
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos        (1U)
 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
 #define USB_OTG_DEACHINTMSK_IEP1INTM            USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos        (17U)                          
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos        (17U)
 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk        (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
 #define USB_OTG_DEACHINTMSK_OEP1INTM            USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
 
 /********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID_Pos              (0U)                           
+#define USB_OTG_CID_PRODUCT_ID_Pos              (0U)
 #define USB_OTG_CID_PRODUCT_ID_Msk              (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
 #define USB_OTG_CID_PRODUCT_ID                  USB_OTG_CID_PRODUCT_ID_Msk     /*!< Product ID field */
 
 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos          (0U)                           
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos          (0U)
 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
 #define USB_OTG_DIEPEACHMSK1_XFRCM              USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_EPDM_Pos           (1U)                           
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos           (1U)
 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
 #define USB_OTG_DIEPEACHMSK1_EPDM               USB_OTG_DIEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_TOM_Pos            (3U)                           
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos            (3U)
 #define USB_OTG_DIEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
 #define USB_OTG_DIEPEACHMSK1_TOM                USB_OTG_DIEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos      (4U)
 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK          USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos        (5U)                           
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos        (5U)
 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
 #define USB_OTG_DIEPEACHMSK1_INEPNMM            USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos        (6U)                           
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos        (6U)
 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
 #define USB_OTG_DIEPEACHMSK1_INEPNEM            USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos         (8U)                           
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos         (8U)
 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
 #define USB_OTG_DIEPEACHMSK1_TXFURM             USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
-#define USB_OTG_DIEPEACHMSK1_BIM_Pos            (9U)                           
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos            (9U)
 #define USB_OTG_DIEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
 #define USB_OTG_DIEPEACHMSK1_BIM                USB_OTG_DIEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
-#define USB_OTG_DIEPEACHMSK1_NAKM_Pos           (13U)                          
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos           (13U)
 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
 #define USB_OTG_DIEPEACHMSK1_NAKM               USB_OTG_DIEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
 
 /********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS_Pos                  (0U)                           
+#define USB_OTG_HPRT_PCSTS_Pos                  (0U)
 #define USB_OTG_HPRT_PCSTS_Msk                  (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
 #define USB_OTG_HPRT_PCSTS                      USB_OTG_HPRT_PCSTS_Msk         /*!< Port connect status */
-#define USB_OTG_HPRT_PCDET_Pos                  (1U)                           
+#define USB_OTG_HPRT_PCDET_Pos                  (1U)
 #define USB_OTG_HPRT_PCDET_Msk                  (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
 #define USB_OTG_HPRT_PCDET                      USB_OTG_HPRT_PCDET_Msk         /*!< Port connect detected */
-#define USB_OTG_HPRT_PENA_Pos                   (2U)                           
+#define USB_OTG_HPRT_PENA_Pos                   (2U)
 #define USB_OTG_HPRT_PENA_Msk                   (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
 #define USB_OTG_HPRT_PENA                       USB_OTG_HPRT_PENA_Msk          /*!< Port enable */
-#define USB_OTG_HPRT_PENCHNG_Pos                (3U)                           
+#define USB_OTG_HPRT_PENCHNG_Pos                (3U)
 #define USB_OTG_HPRT_PENCHNG_Msk                (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
 #define USB_OTG_HPRT_PENCHNG                    USB_OTG_HPRT_PENCHNG_Msk       /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA_Pos                   (4U)                           
+#define USB_OTG_HPRT_POCA_Pos                   (4U)
 #define USB_OTG_HPRT_POCA_Msk                   (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
 #define USB_OTG_HPRT_POCA                       USB_OTG_HPRT_POCA_Msk          /*!< Port overcurrent active */
-#define USB_OTG_HPRT_POCCHNG_Pos                (5U)                           
+#define USB_OTG_HPRT_POCCHNG_Pos                (5U)
 #define USB_OTG_HPRT_POCCHNG_Msk                (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
 #define USB_OTG_HPRT_POCCHNG                    USB_OTG_HPRT_POCCHNG_Msk       /*!< Port overcurrent change */
-#define USB_OTG_HPRT_PRES_Pos                   (6U)                           
+#define USB_OTG_HPRT_PRES_Pos                   (6U)
 #define USB_OTG_HPRT_PRES_Msk                   (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
 #define USB_OTG_HPRT_PRES                       USB_OTG_HPRT_PRES_Msk          /*!< Port resume */
-#define USB_OTG_HPRT_PSUSP_Pos                  (7U)                           
+#define USB_OTG_HPRT_PSUSP_Pos                  (7U)
 #define USB_OTG_HPRT_PSUSP_Msk                  (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
 #define USB_OTG_HPRT_PSUSP                      USB_OTG_HPRT_PSUSP_Msk         /*!< Port suspend */
-#define USB_OTG_HPRT_PRST_Pos                   (8U)                           
+#define USB_OTG_HPRT_PRST_Pos                   (8U)
 #define USB_OTG_HPRT_PRST_Msk                   (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
 #define USB_OTG_HPRT_PRST                       USB_OTG_HPRT_PRST_Msk          /*!< Port reset */
 
-#define USB_OTG_HPRT_PLSTS_Pos                  (10U)                          
+#define USB_OTG_HPRT_PLSTS_Pos                  (10U)
 #define USB_OTG_HPRT_PLSTS_Msk                  (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
 #define USB_OTG_HPRT_PLSTS                      USB_OTG_HPRT_PLSTS_Msk         /*!< Port line status */
 #define USB_OTG_HPRT_PLSTS_0                    (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
 #define USB_OTG_HPRT_PLSTS_1                    (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_HPRT_PPWR_Pos                   (12U)                          
+#define USB_OTG_HPRT_PPWR_Pos                   (12U)
 #define USB_OTG_HPRT_PPWR_Msk                   (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
 #define USB_OTG_HPRT_PPWR                       USB_OTG_HPRT_PPWR_Msk          /*!< Port power */
 
-#define USB_OTG_HPRT_PTCTL_Pos                  (13U)                          
+#define USB_OTG_HPRT_PTCTL_Pos                  (13U)
 #define USB_OTG_HPRT_PTCTL_Msk                  (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
 #define USB_OTG_HPRT_PTCTL                      USB_OTG_HPRT_PTCTL_Msk         /*!< Port test control */
 #define USB_OTG_HPRT_PTCTL_0                    (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
@@ -972,136 +972,136 @@ typedef struct
 #define USB_OTG_HPRT_PTCTL_2                    (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
 #define USB_OTG_HPRT_PTCTL_3                    (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
 
-#define USB_OTG_HPRT_PSPD_Pos                   (17U)                          
+#define USB_OTG_HPRT_PSPD_Pos                   (17U)
 #define USB_OTG_HPRT_PSPD_Msk                   (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
 #define USB_OTG_HPRT_PSPD                       USB_OTG_HPRT_PSPD_Msk          /*!< Port speed */
 #define USB_OTG_HPRT_PSPD_0                     (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
 #define USB_OTG_HPRT_PSPD_1                     (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
 
 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos          (0U)                           
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos          (0U)
 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
 #define USB_OTG_DOEPEACHMSK1_XFRCM              USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_EPDM_Pos           (1U)                           
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos           (1U)
 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
 #define USB_OTG_DOEPEACHMSK1_EPDM               USB_OTG_DOEPEACHMSK1_EPDM_Msk  /*!< Endpoint disabled interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_TOM_Pos            (3U)                           
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos            (3U)
 #define USB_OTG_DOEPEACHMSK1_TOM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
 #define USB_OTG_DOEPEACHMSK1_TOM                USB_OTG_DOEPEACHMSK1_TOM_Msk   /*!< Timeout condition mask */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos      (4U)                           
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos      (4U)
 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk      (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK          USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos        (5U)                           
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos        (5U)
 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
 #define USB_OTG_DOEPEACHMSK1_INEPNMM            USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos        (6U)                           
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos        (6U)
 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk        (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
 #define USB_OTG_DOEPEACHMSK1_INEPNEM            USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos         (8U)                           
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos         (8U)
 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
 #define USB_OTG_DOEPEACHMSK1_TXFURM             USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
-#define USB_OTG_DOEPEACHMSK1_BIM_Pos            (9U)                           
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos            (9U)
 #define USB_OTG_DOEPEACHMSK1_BIM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
 #define USB_OTG_DOEPEACHMSK1_BIM                USB_OTG_DOEPEACHMSK1_BIM_Msk   /*!< BNA interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_BERRM_Pos          (12U)                          
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos          (12U)
 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
 #define USB_OTG_DOEPEACHMSK1_BERRM              USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NAKM_Pos           (13U)                          
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos           (13U)
 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
 #define USB_OTG_DOEPEACHMSK1_NAKM               USB_OTG_DOEPEACHMSK1_NAKM_Msk  /*!< NAK interrupt mask */
-#define USB_OTG_DOEPEACHMSK1_NYETM_Pos          (14U)                          
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos          (14U)
 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
 #define USB_OTG_DOEPEACHMSK1_NYETM              USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
 
 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA_Pos              (0U)                           
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos              (0U)
 #define USB_OTG_HPTXFSIZ_PTXSA_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_HPTXFSIZ_PTXSA                  USB_OTG_HPTXFSIZ_PTXSA_Msk     /*!< Host periodic TxFIFO start address */
-#define USB_OTG_HPTXFSIZ_PTXFD_Pos              (16U)                          
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos              (16U)
 #define USB_OTG_HPTXFSIZ_PTXFD_Msk              (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
 #define USB_OTG_HPTXFSIZ_PTXFD                  USB_OTG_HPTXFSIZ_PTXFD_Msk     /*!< Host periodic TxFIFO depth */
 
 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ_Pos               (0U)                           
+#define USB_OTG_DIEPCTL_MPSIZ_Pos               (0U)
 #define USB_OTG_DIEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
 #define USB_OTG_DIEPCTL_MPSIZ                   USB_OTG_DIEPCTL_MPSIZ_Msk      /*!< Maximum packet size */
-#define USB_OTG_DIEPCTL_USBAEP_Pos              (15U)                          
+#define USB_OTG_DIEPCTL_USBAEP_Pos              (15U)
 #define USB_OTG_DIEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
 #define USB_OTG_DIEPCTL_USBAEP                  USB_OTG_DIEPCTL_USBAEP_Msk     /*!< USB active endpoint */
-#define USB_OTG_DIEPCTL_EONUM_DPID_Pos          (16U)                          
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos          (16U)
 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk          (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
 #define USB_OTG_DIEPCTL_EONUM_DPID              USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
-#define USB_OTG_DIEPCTL_NAKSTS_Pos              (17U)                          
+#define USB_OTG_DIEPCTL_NAKSTS_Pos              (17U)
 #define USB_OTG_DIEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
 #define USB_OTG_DIEPCTL_NAKSTS                  USB_OTG_DIEPCTL_NAKSTS_Msk     /*!< NAK status */
 
-#define USB_OTG_DIEPCTL_EPTYP_Pos               (18U)                          
+#define USB_OTG_DIEPCTL_EPTYP_Pos               (18U)
 #define USB_OTG_DIEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
 #define USB_OTG_DIEPCTL_EPTYP                   USB_OTG_DIEPCTL_EPTYP_Msk      /*!< Endpoint type */
 #define USB_OTG_DIEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
 #define USB_OTG_DIEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DIEPCTL_STALL_Pos               (21U)                          
+#define USB_OTG_DIEPCTL_STALL_Pos               (21U)
 #define USB_OTG_DIEPCTL_STALL_Msk               (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
 #define USB_OTG_DIEPCTL_STALL                   USB_OTG_DIEPCTL_STALL_Msk      /*!< STALL handshake */
 
-#define USB_OTG_DIEPCTL_TXFNUM_Pos              (22U)                          
+#define USB_OTG_DIEPCTL_TXFNUM_Pos              (22U)
 #define USB_OTG_DIEPCTL_TXFNUM_Msk              (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
 #define USB_OTG_DIEPCTL_TXFNUM                  USB_OTG_DIEPCTL_TXFNUM_Msk     /*!< TxFIFO number */
 #define USB_OTG_DIEPCTL_TXFNUM_0                (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
 #define USB_OTG_DIEPCTL_TXFNUM_1                (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
 #define USB_OTG_DIEPCTL_TXFNUM_2                (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
 #define USB_OTG_DIEPCTL_TXFNUM_3                (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
-#define USB_OTG_DIEPCTL_CNAK_Pos                (26U)                          
+#define USB_OTG_DIEPCTL_CNAK_Pos                (26U)
 #define USB_OTG_DIEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
 #define USB_OTG_DIEPCTL_CNAK                    USB_OTG_DIEPCTL_CNAK_Msk       /*!< Clear NAK */
-#define USB_OTG_DIEPCTL_SNAK_Pos                (27U)                          
+#define USB_OTG_DIEPCTL_SNAK_Pos                (27U)
 #define USB_OTG_DIEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
 #define USB_OTG_DIEPCTL_SNAK                    USB_OTG_DIEPCTL_SNAK_Msk       /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos      (28U)
 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM          USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DIEPCTL_SODDFRM_Pos             (29U)                          
+#define USB_OTG_DIEPCTL_SODDFRM_Pos             (29U)
 #define USB_OTG_DIEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
 #define USB_OTG_DIEPCTL_SODDFRM                 USB_OTG_DIEPCTL_SODDFRM_Msk    /*!< Set odd frame */
-#define USB_OTG_DIEPCTL_EPDIS_Pos               (30U)                          
+#define USB_OTG_DIEPCTL_EPDIS_Pos               (30U)
 #define USB_OTG_DIEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
 #define USB_OTG_DIEPCTL_EPDIS                   USB_OTG_DIEPCTL_EPDIS_Msk      /*!< Endpoint disable */
-#define USB_OTG_DIEPCTL_EPENA_Pos               (31U)                          
+#define USB_OTG_DIEPCTL_EPENA_Pos               (31U)
 #define USB_OTG_DIEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
 #define USB_OTG_DIEPCTL_EPENA                   USB_OTG_DIEPCTL_EPENA_Msk      /*!< Endpoint enable */
 
 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ_Pos                (0U)                           
+#define USB_OTG_HCCHAR_MPSIZ_Pos                (0U)
 #define USB_OTG_HCCHAR_MPSIZ_Msk                (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
 #define USB_OTG_HCCHAR_MPSIZ                    USB_OTG_HCCHAR_MPSIZ_Msk       /*!< Maximum packet size */
 
-#define USB_OTG_HCCHAR_EPNUM_Pos                (11U)                          
+#define USB_OTG_HCCHAR_EPNUM_Pos                (11U)
 #define USB_OTG_HCCHAR_EPNUM_Msk                (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
 #define USB_OTG_HCCHAR_EPNUM                    USB_OTG_HCCHAR_EPNUM_Msk       /*!< Endpoint number */
 #define USB_OTG_HCCHAR_EPNUM_0                  (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
 #define USB_OTG_HCCHAR_EPNUM_1                  (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
 #define USB_OTG_HCCHAR_EPNUM_2                  (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
 #define USB_OTG_HCCHAR_EPNUM_3                  (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCCHAR_EPDIR_Pos                (15U)                          
+#define USB_OTG_HCCHAR_EPDIR_Pos                (15U)
 #define USB_OTG_HCCHAR_EPDIR_Msk                (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
 #define USB_OTG_HCCHAR_EPDIR                    USB_OTG_HCCHAR_EPDIR_Msk       /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV_Pos                (17U)                          
+#define USB_OTG_HCCHAR_LSDEV_Pos                (17U)
 #define USB_OTG_HCCHAR_LSDEV_Msk                (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
 #define USB_OTG_HCCHAR_LSDEV                    USB_OTG_HCCHAR_LSDEV_Msk       /*!< Low-speed device */
 
-#define USB_OTG_HCCHAR_EPTYP_Pos                (18U)                          
+#define USB_OTG_HCCHAR_EPTYP_Pos                (18U)
 #define USB_OTG_HCCHAR_EPTYP_Msk                (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
 #define USB_OTG_HCCHAR_EPTYP                    USB_OTG_HCCHAR_EPTYP_Msk       /*!< Endpoint type */
 #define USB_OTG_HCCHAR_EPTYP_0                  (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
 #define USB_OTG_HCCHAR_EPTYP_1                  (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
-                                      
-#define USB_OTG_HCCHAR_MC_Pos                   (20U)                          
+
+#define USB_OTG_HCCHAR_MC_Pos                   (20U)
 #define USB_OTG_HCCHAR_MC_Msk                   (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
 #define USB_OTG_HCCHAR_MC                       USB_OTG_HCCHAR_MC_Msk          /*!< Multi Count (MC) / Error Count (EC) */
 #define USB_OTG_HCCHAR_MC_0                     (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
 #define USB_OTG_HCCHAR_MC_1                     (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
 
-#define USB_OTG_HCCHAR_DAD_Pos                  (22U)                          
+#define USB_OTG_HCCHAR_DAD_Pos                  (22U)
 #define USB_OTG_HCCHAR_DAD_Msk                  (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
 #define USB_OTG_HCCHAR_DAD                      USB_OTG_HCCHAR_DAD_Msk         /*!< Device address */
 #define USB_OTG_HCCHAR_DAD_0                    (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
@@ -1111,19 +1111,19 @@ typedef struct
 #define USB_OTG_HCCHAR_DAD_4                    (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
 #define USB_OTG_HCCHAR_DAD_5                    (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
 #define USB_OTG_HCCHAR_DAD_6                    (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
-#define USB_OTG_HCCHAR_ODDFRM_Pos               (29U)                          
+#define USB_OTG_HCCHAR_ODDFRM_Pos               (29U)
 #define USB_OTG_HCCHAR_ODDFRM_Msk               (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
 #define USB_OTG_HCCHAR_ODDFRM                   USB_OTG_HCCHAR_ODDFRM_Msk      /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS_Pos                (30U)                          
+#define USB_OTG_HCCHAR_CHDIS_Pos                (30U)
 #define USB_OTG_HCCHAR_CHDIS_Msk                (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
 #define USB_OTG_HCCHAR_CHDIS                    USB_OTG_HCCHAR_CHDIS_Msk       /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA_Pos                (31U)                          
+#define USB_OTG_HCCHAR_CHENA_Pos                (31U)
 #define USB_OTG_HCCHAR_CHENA_Msk                (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
 #define USB_OTG_HCCHAR_CHENA                    USB_OTG_HCCHAR_CHENA_Msk       /*!< Channel enable */
 
 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
 
-#define USB_OTG_HCSPLT_PRTADDR_Pos              (0U)                           
+#define USB_OTG_HCSPLT_PRTADDR_Pos              (0U)
 #define USB_OTG_HCSPLT_PRTADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
 #define USB_OTG_HCSPLT_PRTADDR                  USB_OTG_HCSPLT_PRTADDR_Msk     /*!< Port address */
 #define USB_OTG_HCSPLT_PRTADDR_0                (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
@@ -1134,7 +1134,7 @@ typedef struct
 #define USB_OTG_HCSPLT_PRTADDR_5                (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
 #define USB_OTG_HCSPLT_PRTADDR_6                (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
 
-#define USB_OTG_HCSPLT_HUBADDR_Pos              (7U)                           
+#define USB_OTG_HCSPLT_HUBADDR_Pos              (7U)
 #define USB_OTG_HCSPLT_HUBADDR_Msk              (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
 #define USB_OTG_HCSPLT_HUBADDR                  USB_OTG_HCSPLT_HUBADDR_Msk     /*!< Hub address */
 #define USB_OTG_HCSPLT_HUBADDR_0                (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
@@ -1145,240 +1145,240 @@ typedef struct
 #define USB_OTG_HCSPLT_HUBADDR_5                (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
 #define USB_OTG_HCSPLT_HUBADDR_6                (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
 
-#define USB_OTG_HCSPLT_XACTPOS_Pos              (14U)                          
+#define USB_OTG_HCSPLT_XACTPOS_Pos              (14U)
 #define USB_OTG_HCSPLT_XACTPOS_Msk              (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
 #define USB_OTG_HCSPLT_XACTPOS                  USB_OTG_HCSPLT_XACTPOS_Msk     /*!< XACTPOS */
 #define USB_OTG_HCSPLT_XACTPOS_0                (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
 #define USB_OTG_HCSPLT_XACTPOS_1                (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCSPLT_COMPLSPLT_Pos            (16U)                          
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos            (16U)
 #define USB_OTG_HCSPLT_COMPLSPLT_Msk            (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
 #define USB_OTG_HCSPLT_COMPLSPLT                USB_OTG_HCSPLT_COMPLSPLT_Msk   /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN_Pos              (31U)                          
+#define USB_OTG_HCSPLT_SPLITEN_Pos              (31U)
 #define USB_OTG_HCSPLT_SPLITEN_Msk              (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
 #define USB_OTG_HCSPLT_SPLITEN                  USB_OTG_HCSPLT_SPLITEN_Msk     /*!< Split enable */
 
 /********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC_Pos                  (0U)                           
+#define USB_OTG_HCINT_XFRC_Pos                  (0U)
 #define USB_OTG_HCINT_XFRC_Msk                  (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
 #define USB_OTG_HCINT_XFRC                      USB_OTG_HCINT_XFRC_Msk         /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH_Pos                   (1U)                           
+#define USB_OTG_HCINT_CHH_Pos                   (1U)
 #define USB_OTG_HCINT_CHH_Msk                   (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
 #define USB_OTG_HCINT_CHH                       USB_OTG_HCINT_CHH_Msk          /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR_Pos                (2U)                           
+#define USB_OTG_HCINT_AHBERR_Pos                (2U)
 #define USB_OTG_HCINT_AHBERR_Msk                (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
 #define USB_OTG_HCINT_AHBERR                    USB_OTG_HCINT_AHBERR_Msk       /*!< AHB error */
-#define USB_OTG_HCINT_STALL_Pos                 (3U)                           
+#define USB_OTG_HCINT_STALL_Pos                 (3U)
 #define USB_OTG_HCINT_STALL_Msk                 (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
 #define USB_OTG_HCINT_STALL                     USB_OTG_HCINT_STALL_Msk        /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK_Pos                   (4U)                           
+#define USB_OTG_HCINT_NAK_Pos                   (4U)
 #define USB_OTG_HCINT_NAK_Msk                   (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
 #define USB_OTG_HCINT_NAK                       USB_OTG_HCINT_NAK_Msk          /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK_Pos                   (5U)                           
+#define USB_OTG_HCINT_ACK_Pos                   (5U)
 #define USB_OTG_HCINT_ACK_Msk                   (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
 #define USB_OTG_HCINT_ACK                       USB_OTG_HCINT_ACK_Msk          /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET_Pos                  (6U)                           
+#define USB_OTG_HCINT_NYET_Pos                  (6U)
 #define USB_OTG_HCINT_NYET_Msk                  (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
 #define USB_OTG_HCINT_NYET                      USB_OTG_HCINT_NYET_Msk         /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR_Pos                 (7U)                           
+#define USB_OTG_HCINT_TXERR_Pos                 (7U)
 #define USB_OTG_HCINT_TXERR_Msk                 (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
 #define USB_OTG_HCINT_TXERR                     USB_OTG_HCINT_TXERR_Msk        /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR_Pos                 (8U)                           
+#define USB_OTG_HCINT_BBERR_Pos                 (8U)
 #define USB_OTG_HCINT_BBERR_Msk                 (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
 #define USB_OTG_HCINT_BBERR                     USB_OTG_HCINT_BBERR_Msk        /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR_Pos                 (9U)                           
+#define USB_OTG_HCINT_FRMOR_Pos                 (9U)
 #define USB_OTG_HCINT_FRMOR_Msk                 (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
 #define USB_OTG_HCINT_FRMOR                     USB_OTG_HCINT_FRMOR_Msk        /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR_Pos                 (10U)                          
+#define USB_OTG_HCINT_DTERR_Pos                 (10U)
 #define USB_OTG_HCINT_DTERR_Msk                 (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
 #define USB_OTG_HCINT_DTERR                     USB_OTG_HCINT_DTERR_Msk        /*!< Data toggle error */
 
 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC_Pos                (0U)                           
+#define USB_OTG_DIEPINT_XFRC_Pos                (0U)
 #define USB_OTG_DIEPINT_XFRC_Msk                (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
 #define USB_OTG_DIEPINT_XFRC                    USB_OTG_DIEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD_Pos              (1U)                           
+#define USB_OTG_DIEPINT_EPDISD_Pos              (1U)
 #define USB_OTG_DIEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
 #define USB_OTG_DIEPINT_EPDISD                  USB_OTG_DIEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
 #define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
 #define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
 #define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
-#define USB_OTG_DIEPINT_TOC_Pos                 (3U)                           
+#define USB_OTG_DIEPINT_TOC_Pos                 (3U)
 #define USB_OTG_DIEPINT_TOC_Msk                 (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
 #define USB_OTG_DIEPINT_TOC                     USB_OTG_DIEPINT_TOC_Msk        /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE_Pos              (4U)                           
+#define USB_OTG_DIEPINT_ITTXFE_Pos              (4U)
 #define USB_OTG_DIEPINT_ITTXFE_Msk              (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
 #define USB_OTG_DIEPINT_ITTXFE                  USB_OTG_DIEPINT_ITTXFE_Msk     /*!< IN token received when TxFIFO is empty */
 #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
 #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
 #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
-#define USB_OTG_DIEPINT_INEPNE_Pos              (6U)                           
+#define USB_OTG_DIEPINT_INEPNE_Pos              (6U)
 #define USB_OTG_DIEPINT_INEPNE_Msk              (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
 #define USB_OTG_DIEPINT_INEPNE                  USB_OTG_DIEPINT_INEPNE_Msk     /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE_Pos                (7U)                           
+#define USB_OTG_DIEPINT_TXFE_Pos                (7U)
 #define USB_OTG_DIEPINT_TXFE_Msk                (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
 #define USB_OTG_DIEPINT_TXFE                    USB_OTG_DIEPINT_TXFE_Msk       /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos          (8U)                           
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos          (8U)
 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk          (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
 #define USB_OTG_DIEPINT_TXFIFOUDRN              USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA_Pos                 (9U)                           
+#define USB_OTG_DIEPINT_BNA_Pos                 (9U)
 #define USB_OTG_DIEPINT_BNA_Msk                 (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
 #define USB_OTG_DIEPINT_BNA                     USB_OTG_DIEPINT_BNA_Msk        /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS_Pos           (11U)                          
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos           (11U)
 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk           (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
 #define USB_OTG_DIEPINT_PKTDRPSTS               USB_OTG_DIEPINT_PKTDRPSTS_Msk  /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR_Pos                (12U)                          
+#define USB_OTG_DIEPINT_BERR_Pos                (12U)
 #define USB_OTG_DIEPINT_BERR_Msk                (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
 #define USB_OTG_DIEPINT_BERR                    USB_OTG_DIEPINT_BERR_Msk       /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK_Pos                 (13U)                          
+#define USB_OTG_DIEPINT_NAK_Pos                 (13U)
 #define USB_OTG_DIEPINT_NAK_Msk                 (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
 #define USB_OTG_DIEPINT_NAK                     USB_OTG_DIEPINT_NAK_Msk        /*!< NAK interrupt */
 
 /********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM_Pos              (0U)                           
+#define USB_OTG_HCINTMSK_XFRCM_Pos              (0U)
 #define USB_OTG_HCINTMSK_XFRCM_Msk              (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
 #define USB_OTG_HCINTMSK_XFRCM                  USB_OTG_HCINTMSK_XFRCM_Msk     /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM_Pos               (1U)                           
+#define USB_OTG_HCINTMSK_CHHM_Pos               (1U)
 #define USB_OTG_HCINTMSK_CHHM_Msk               (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
 #define USB_OTG_HCINTMSK_CHHM                   USB_OTG_HCINTMSK_CHHM_Msk      /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR_Pos             (2U)                           
+#define USB_OTG_HCINTMSK_AHBERR_Pos             (2U)
 #define USB_OTG_HCINTMSK_AHBERR_Msk             (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
 #define USB_OTG_HCINTMSK_AHBERR                 USB_OTG_HCINTMSK_AHBERR_Msk    /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM_Pos             (3U)                           
+#define USB_OTG_HCINTMSK_STALLM_Pos             (3U)
 #define USB_OTG_HCINTMSK_STALLM_Msk             (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
 #define USB_OTG_HCINTMSK_STALLM                 USB_OTG_HCINTMSK_STALLM_Msk    /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM_Pos               (4U)                           
+#define USB_OTG_HCINTMSK_NAKM_Pos               (4U)
 #define USB_OTG_HCINTMSK_NAKM_Msk               (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
 #define USB_OTG_HCINTMSK_NAKM                   USB_OTG_HCINTMSK_NAKM_Msk      /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM_Pos               (5U)                           
+#define USB_OTG_HCINTMSK_ACKM_Pos               (5U)
 #define USB_OTG_HCINTMSK_ACKM_Msk               (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
 #define USB_OTG_HCINTMSK_ACKM                   USB_OTG_HCINTMSK_ACKM_Msk      /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET_Pos               (6U)                           
+#define USB_OTG_HCINTMSK_NYET_Pos               (6U)
 #define USB_OTG_HCINTMSK_NYET_Msk               (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
 #define USB_OTG_HCINTMSK_NYET                   USB_OTG_HCINTMSK_NYET_Msk      /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM_Pos             (7U)                           
+#define USB_OTG_HCINTMSK_TXERRM_Pos             (7U)
 #define USB_OTG_HCINTMSK_TXERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
 #define USB_OTG_HCINTMSK_TXERRM                 USB_OTG_HCINTMSK_TXERRM_Msk    /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM_Pos             (8U)                           
+#define USB_OTG_HCINTMSK_BBERRM_Pos             (8U)
 #define USB_OTG_HCINTMSK_BBERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
 #define USB_OTG_HCINTMSK_BBERRM                 USB_OTG_HCINTMSK_BBERRM_Msk    /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM_Pos             (9U)                           
+#define USB_OTG_HCINTMSK_FRMORM_Pos             (9U)
 #define USB_OTG_HCINTMSK_FRMORM_Msk             (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
 #define USB_OTG_HCINTMSK_FRMORM                 USB_OTG_HCINTMSK_FRMORM_Msk    /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM_Pos             (10U)                          
+#define USB_OTG_HCINTMSK_DTERRM_Pos             (10U)
 #define USB_OTG_HCINTMSK_DTERRM_Msk             (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
 #define USB_OTG_HCINTMSK_DTERRM                 USB_OTG_HCINTMSK_DTERRM_Msk    /*!< Data toggle error mask */
 
 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
 
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos             (0U)                           
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos             (0U)
 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
 #define USB_OTG_DIEPTSIZ_XFRSIZ                 USB_OTG_DIEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT_Pos             (19U)                          
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos             (19U)
 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
 #define USB_OTG_DIEPTSIZ_PKTCNT                 USB_OTG_DIEPTSIZ_PKTCNT_Msk    /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT_Pos             (29U)                          
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos             (29U)
 #define USB_OTG_DIEPTSIZ_MULCNT_Msk             (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
 #define USB_OTG_DIEPTSIZ_MULCNT                 USB_OTG_DIEPTSIZ_MULCNT_Msk    /*!< Packet count */
 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ_Pos               (0U)                           
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos               (0U)
 #define USB_OTG_HCTSIZ_XFRSIZ_Msk               (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
 #define USB_OTG_HCTSIZ_XFRSIZ                   USB_OTG_HCTSIZ_XFRSIZ_Msk      /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT_Pos               (19U)                          
+#define USB_OTG_HCTSIZ_PKTCNT_Pos               (19U)
 #define USB_OTG_HCTSIZ_PKTCNT_Msk               (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
 #define USB_OTG_HCTSIZ_PKTCNT                   USB_OTG_HCTSIZ_PKTCNT_Msk      /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING_Pos               (31U)                          
+#define USB_OTG_HCTSIZ_DOPING_Pos               (31U)
 #define USB_OTG_HCTSIZ_DOPING_Msk               (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
 #define USB_OTG_HCTSIZ_DOPING                   USB_OTG_HCTSIZ_DOPING_Msk      /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID_Pos                 (29U)                          
+#define USB_OTG_HCTSIZ_DPID_Pos                 (29U)
 #define USB_OTG_HCTSIZ_DPID_Msk                 (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
 #define USB_OTG_HCTSIZ_DPID                     USB_OTG_HCTSIZ_DPID_Msk        /*!< Data PID */
 #define USB_OTG_HCTSIZ_DPID_0                   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
 #define USB_OTG_HCTSIZ_DPID_1                   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
 
 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR_Pos             (0U)                           
+#define USB_OTG_DIEPDMA_DMAADDR_Pos             (0U)
 #define USB_OTG_DIEPDMA_DMAADDR_Msk             (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
 #define USB_OTG_DIEPDMA_DMAADDR                 USB_OTG_DIEPDMA_DMAADDR_Msk    /*!< DMA address */
 
 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR_Pos               (0U)                           
+#define USB_OTG_HCDMA_DMAADDR_Pos               (0U)
 #define USB_OTG_HCDMA_DMAADDR_Msk               (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
 #define USB_OTG_HCDMA_DMAADDR                   USB_OTG_HCDMA_DMAADDR_Msk      /*!< DMA address */
 
 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV_Pos           (0U)                           
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos           (0U)
 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk           (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
 
 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA_Pos            (0U)                           
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos            (0U)
 #define USB_OTG_DIEPTXF_INEPTXSA_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
 #define USB_OTG_DIEPTXF_INEPTXSA                USB_OTG_DIEPTXF_INEPTXSA_Msk   /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD_Pos            (16U)                          
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos            (16U)
 #define USB_OTG_DIEPTXF_INEPTXFD_Msk            (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
 #define USB_OTG_DIEPTXF_INEPTXFD                USB_OTG_DIEPTXF_INEPTXFD_Msk   /*!< IN endpoint TxFIFO depth */
 
 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
 
-#define USB_OTG_DOEPCTL_MPSIZ_Pos               (0U)                           
+#define USB_OTG_DOEPCTL_MPSIZ_Pos               (0U)
 #define USB_OTG_DOEPCTL_MPSIZ_Msk               (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP_Pos              (15U)                          
+#define USB_OTG_DOEPCTL_USBAEP_Pos              (15U)
 #define USB_OTG_DOEPCTL_USBAEP_Msk              (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
 #define USB_OTG_DOEPCTL_USBAEP                  USB_OTG_DOEPCTL_USBAEP_Msk     /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS_Pos              (17U)                          
+#define USB_OTG_DOEPCTL_NAKSTS_Pos              (17U)
 #define USB_OTG_DOEPCTL_NAKSTS_Msk              (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
 #define USB_OTG_DOEPCTL_NAKSTS                  USB_OTG_DOEPCTL_NAKSTS_Msk     /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos      (28U)                          
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos      (28U)
 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk      (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM          USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM_Pos             (29U)                          
+#define USB_OTG_DOEPCTL_SODDFRM_Pos             (29U)
 #define USB_OTG_DOEPCTL_SODDFRM_Msk             (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
 #define USB_OTG_DOEPCTL_SODDFRM                 USB_OTG_DOEPCTL_SODDFRM_Msk    /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP_Pos               (18U)                          
+#define USB_OTG_DOEPCTL_EPTYP_Pos               (18U)
 #define USB_OTG_DOEPCTL_EPTYP_Msk               (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
 #define USB_OTG_DOEPCTL_EPTYP                   USB_OTG_DOEPCTL_EPTYP_Msk      /*!< Endpoint type */
 #define USB_OTG_DOEPCTL_EPTYP_0                 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
 #define USB_OTG_DOEPCTL_EPTYP_1                 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DOEPCTL_SNPM_Pos                (20U)                          
+#define USB_OTG_DOEPCTL_SNPM_Pos                (20U)
 #define USB_OTG_DOEPCTL_SNPM_Msk                (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
 #define USB_OTG_DOEPCTL_SNPM                    USB_OTG_DOEPCTL_SNPM_Msk       /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL_Pos               (21U)                          
+#define USB_OTG_DOEPCTL_STALL_Pos               (21U)
 #define USB_OTG_DOEPCTL_STALL_Msk               (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
 #define USB_OTG_DOEPCTL_STALL                   USB_OTG_DOEPCTL_STALL_Msk      /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK_Pos                (26U)                          
+#define USB_OTG_DOEPCTL_CNAK_Pos                (26U)
 #define USB_OTG_DOEPCTL_CNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
 #define USB_OTG_DOEPCTL_CNAK                    USB_OTG_DOEPCTL_CNAK_Msk       /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK_Pos                (27U)                          
+#define USB_OTG_DOEPCTL_SNAK_Pos                (27U)
 #define USB_OTG_DOEPCTL_SNAK_Msk                (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
 #define USB_OTG_DOEPCTL_SNAK                    USB_OTG_DOEPCTL_SNAK_Msk       /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS_Pos               (30U)                          
+#define USB_OTG_DOEPCTL_EPDIS_Pos               (30U)
 #define USB_OTG_DOEPCTL_EPDIS_Msk               (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
 #define USB_OTG_DOEPCTL_EPDIS                   USB_OTG_DOEPCTL_EPDIS_Msk      /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA_Pos               (31U)                          
+#define USB_OTG_DOEPCTL_EPENA_Pos               (31U)
 #define USB_OTG_DOEPCTL_EPENA_Msk               (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
 #define USB_OTG_DOEPCTL_EPENA                   USB_OTG_DOEPCTL_EPENA_Msk      /*!< Endpoint enable */
 
 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC_Pos                (0U)                           
+#define USB_OTG_DOEPINT_XFRC_Pos                (0U)
 #define USB_OTG_DOEPINT_XFRC_Msk                (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
 #define USB_OTG_DOEPINT_XFRC                    USB_OTG_DOEPINT_XFRC_Msk       /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD_Pos              (1U)                           
+#define USB_OTG_DOEPINT_EPDISD_Pos              (1U)
 #define USB_OTG_DOEPINT_EPDISD_Msk              (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
 #define USB_OTG_DOEPINT_EPDISD                  USB_OTG_DOEPINT_EPDISD_Msk     /*!< Endpoint disabled interrupt */
 #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
 #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
 #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
-#define USB_OTG_DOEPINT_STUP_Pos                (3U)                           
+#define USB_OTG_DOEPINT_STUP_Pos                (3U)
 #define USB_OTG_DOEPINT_STUP_Msk                (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
 #define USB_OTG_DOEPINT_STUP                    USB_OTG_DOEPINT_STUP_Msk       /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS_Pos             (4U)                           
+#define USB_OTG_DOEPINT_OTEPDIS_Pos             (4U)
 #define USB_OTG_DOEPINT_OTEPDIS_Msk             (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
 #define USB_OTG_DOEPINT_OTEPDIS                 USB_OTG_DOEPINT_OTEPDIS_Msk    /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
 #define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
 #define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP_Pos             (6U)                           
+#define USB_OTG_DOEPINT_B2BSTUP_Pos             (6U)
 #define USB_OTG_DOEPINT_B2BSTUP_Msk             (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
 #define USB_OTG_DOEPINT_B2BSTUP                 USB_OTG_DOEPINT_B2BSTUP_Msk    /*!< Back-to-back SETUP packets received */
 #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
@@ -1387,7 +1387,7 @@ typedef struct
 #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
 #define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
 #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
-#define USB_OTG_DOEPINT_NYET_Pos                (14U)                          
+#define USB_OTG_DOEPINT_NYET_Pos                (14U)
 #define USB_OTG_DOEPINT_NYET_Msk                (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
 #define USB_OTG_DOEPINT_NYET                    USB_OTG_DOEPINT_NYET_Msk       /*!< NYET interrupt */
 #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
@@ -1395,50 +1395,50 @@ typedef struct
 #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
 
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos             (0U)                           
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos             (0U)
 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk             (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
 #define USB_OTG_DOEPTSIZ_XFRSIZ                 USB_OTG_DOEPTSIZ_XFRSIZ_Msk    /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT_Pos             (19U)                          
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos             (19U)
 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk             (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
 #define USB_OTG_DOEPTSIZ_PKTCNT                 USB_OTG_DOEPTSIZ_PKTCNT_Msk    /*!< Packet count */
 
-#define USB_OTG_DOEPTSIZ_STUPCNT_Pos            (29U)                          
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos            (29U)
 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk            (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
 #define USB_OTG_DOEPTSIZ_STUPCNT                USB_OTG_DOEPTSIZ_STUPCNT_Msk   /*!< SETUP packet count */
 #define USB_OTG_DOEPTSIZ_STUPCNT_0              (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
 #define USB_OTG_DOEPTSIZ_STUPCNT_1              (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
 
 /********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK_Pos             (0U)                           
+#define USB_OTG_PCGCCTL_STOPCLK_Pos             (0U)
 #define USB_OTG_PCGCCTL_STOPCLK_Msk             (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
 #define USB_OTG_PCGCCTL_STOPCLK                 USB_OTG_PCGCCTL_STOPCLK_Msk    /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK_Pos             (1U)                           
+#define USB_OTG_PCGCCTL_GATECLK_Pos             (1U)
 #define USB_OTG_PCGCCTL_GATECLK_Msk             (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
 #define USB_OTG_PCGCCTL_GATECLK                 USB_OTG_PCGCCTL_GATECLK_Msk    /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP_Pos             (4U)                           
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos             (4U)
 #define USB_OTG_PCGCCTL_PHYSUSP_Msk             (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
 #define USB_OTG_PCGCCTL_PHYSUSP                 USB_OTG_PCGCCTL_PHYSUSP_Msk    /*!<Bit 1 */
 
 /* Legacy define */
 /********************  Bit definition for OTG register  ********************/
-#define USB_OTG_CHNUM_Pos                       (0U)                           
+#define USB_OTG_CHNUM_Pos                       (0U)
 #define USB_OTG_CHNUM_Msk                       (0xFUL << USB_OTG_CHNUM_Pos)    /*!< 0x0000000F */
 #define USB_OTG_CHNUM                           USB_OTG_CHNUM_Msk              /*!< Channel number */
 #define USB_OTG_CHNUM_0                         (0x1UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000001 */
 #define USB_OTG_CHNUM_1                         (0x2UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000002 */
 #define USB_OTG_CHNUM_2                         (0x4UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000004 */
 #define USB_OTG_CHNUM_3                         (0x8UL << USB_OTG_CHNUM_Pos)    /*!< 0x00000008 */
-#define USB_OTG_BCNT_Pos                        (4U)                           
+#define USB_OTG_BCNT_Pos                        (4U)
 #define USB_OTG_BCNT_Msk                        (0x7FFUL << USB_OTG_BCNT_Pos)   /*!< 0x00007FF0 */
 #define USB_OTG_BCNT                            USB_OTG_BCNT_Msk               /*!< Byte count */
 
-#define USB_OTG_DPID_Pos                        (15U)                          
+#define USB_OTG_DPID_Pos                        (15U)
 #define USB_OTG_DPID_Msk                        (0x3UL << USB_OTG_DPID_Pos)     /*!< 0x00018000 */
 #define USB_OTG_DPID                            USB_OTG_DPID_Msk               /*!< Data PID */
 #define USB_OTG_DPID_0                          (0x1UL << USB_OTG_DPID_Pos)     /*!< 0x00008000 */
 #define USB_OTG_DPID_1                          (0x2UL << USB_OTG_DPID_Pos)     /*!< 0x00010000 */
 
-#define USB_OTG_PKTSTS_Pos                      (17U)                          
+#define USB_OTG_PKTSTS_Pos                      (17U)
 #define USB_OTG_PKTSTS_Msk                      (0xFUL << USB_OTG_PKTSTS_Pos)   /*!< 0x001E0000 */
 #define USB_OTG_PKTSTS                          USB_OTG_PKTSTS_Msk             /*!< Packet status */
 #define USB_OTG_PKTSTS_0                        (0x1UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00020000 */
@@ -1446,7 +1446,7 @@ typedef struct
 #define USB_OTG_PKTSTS_2                        (0x4UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00080000 */
 #define USB_OTG_PKTSTS_3                        (0x8UL << USB_OTG_PKTSTS_Pos)   /*!< 0x00100000 */
 
-#define USB_OTG_EPNUM_Pos                       (0U)                           
+#define USB_OTG_EPNUM_Pos                       (0U)
 #define USB_OTG_EPNUM_Msk                       (0xFUL << USB_OTG_EPNUM_Pos)    /*!< 0x0000000F */
 #define USB_OTG_EPNUM                           USB_OTG_EPNUM_Msk              /*!< Endpoint number */
 #define USB_OTG_EPNUM_0                         (0x1UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000001 */
@@ -1454,7 +1454,7 @@ typedef struct
 #define USB_OTG_EPNUM_2                         (0x4UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000004 */
 #define USB_OTG_EPNUM_3                         (0x8UL << USB_OTG_EPNUM_Pos)    /*!< 0x00000008 */
 
-#define USB_OTG_FRMNUM_Pos                      (21U)                          
+#define USB_OTG_FRMNUM_Pos                      (21U)
 #define USB_OTG_FRMNUM_Msk                      (0xFUL << USB_OTG_FRMNUM_Pos)   /*!< 0x01E00000 */
 #define USB_OTG_FRMNUM                          USB_OTG_FRMNUM_Msk             /*!< Frame number */
 #define USB_OTG_FRMNUM_0                        (0x1UL << USB_OTG_FRMNUM_Pos)   /*!< 0x00200000 */
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index 2d0e379ad..e26be775d 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -996,7 +996,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   if (dir_in) {
     USBC_Writew(mps, USBC_REG_TXMAXP(USBC0_BASE));
 
-    reg_val = (1 << USBC_BP_TXCSR_D_MODE) 
+    reg_val = (1 << USBC_BP_TXCSR_D_MODE)
       | (1 << USBC_BP_TXCSR_D_FLUSH_FIFO)
       | (1 << USBC_BP_TXCSR_D_CLEAR_DATA_TOGGLE);
     if  (xfer == TUSB_XFER_ISOCHRONOUS)
@@ -1048,7 +1048,7 @@ void dcd_edpt_close_all(uint8_t rhport)
       USBC_REG_TXCSR(USBC0_BASE));
 
     USBC_Writew(0, USBC_REG_RXMAXP(USBC0_BASE));
-	  USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO), 
+	  USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
       USBC_REG_RXCSR(USBC0_BASE));
 
     USBC_Writew(0, USBC_REG_TXFIFOAD(USBC0_BASE));
@@ -1078,7 +1078,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   } else {
     USBC_INT_DisableRxEp(epn);
     USBC_Writew(0, USBC_REG_RXMAXP(USBC0_BASE));
-	  USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO), 
+	  USBC_Writew((1 << USBC_BP_RXCSR_D_CLEAR_DATA_TOGGLE) | (1 << USBC_BP_RXCSR_D_FLUSH_FIFO),
       USBC_REG_RXCSR(USBC0_BASE));
 
     USBC_Writew(0, USBC_REG_RXFIFOAD(USBC0_BASE));
diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c
index 26b5dce9d..590dd9fcf 100644
--- a/src/portable/template/dcd_template.c
+++ b/src/portable/template/dcd_template.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2018, hathach (tinyusb.org)
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c
index a3f228dd9..58628a8bb 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.c
+++ b/src/portable/valentyusb/eptri/dcd_eptri.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/portable/valentyusb/eptri/dcd_eptri.h b/src/portable/valentyusb/eptri/dcd_eptri.h
index 0fa6ecc64..d67635d7c 100644
--- a/src/portable/valentyusb/eptri/dcd_eptri.h
+++ b/src/portable/valentyusb/eptri/dcd_eptri.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/src/portable/wch/ch32v307/dcd_usbhs.c b/src/portable/wch/ch32v307/dcd_usbhs.c
index b7a79e166..3ad011cff 100644
--- a/src/portable/wch/ch32v307/dcd_usbhs.c
+++ b/src/portable/wch/ch32v307/dcd_usbhs.c
@@ -1,7 +1,7 @@
-/* 
+/*
  * The MIT License (MIT)
  *
- * Copyright (c) 2022 Greg Davill 
+ * Copyright (c) 2022 Greg Davill
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -261,7 +261,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
                 USBHS_Dev_Endp0_Tog ^= 1;
             } else {
                 xfer->queued_len += short_packet_size;
-                
+
                 EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer;
                 USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum);
                 EP_TX_LEN(epnum) = short_packet_size;
@@ -366,7 +366,7 @@ void dcd_int_handler(uint8_t rhport) {
     } else if (intflag & USBHS_SETUP_FLAG) {
         USBHS_Dev_Endp0_Tog = 1;
         dcd_event_setup_received(0, EP0_DatabufHD, true);
-        
+
         USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
     } else if (intflag & USBHS_DETECT_FLAG) {
         USBHS_Dev_Endp0_Tog = 1;
diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc
index 6403015dd..06ddddc4a 100644
--- a/test/fuzz/dcd_fuzz.cc
+++ b/test/fuzz/dcd_fuzz.cc
@@ -185,7 +185,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer,
 
 /* TODO: implement a fuzzed version of this.
 bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff,
-                        uint16_t total_bytes) {} 
+                        uint16_t total_bytes) {}
 */
 
 // Stall endpoint, any queuing transfer should be removed from endpoint
@@ -205,4 +205,4 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
   UNUSED(ep_addr);
   return;
 }
-}
\ No newline at end of file
+}
diff --git a/test/fuzz/device/cdc/CMakeLists.txt b/test/fuzz/device/cdc/CMakeLists.txt
index fa6e83b7e..8e4db9d29 100644
--- a/test/fuzz/device/cdc/CMakeLists.txt
+++ b/test/fuzz/device/cdc/CMakeLists.txt
@@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/test/fuzz/device/cdc/src/fuzz.cc b/test/fuzz/device/cdc/src/fuzz.cc
index d40483ca6..0560e8621 100644
--- a/test/fuzz/device/cdc/src/fuzz.cc
+++ b/test/fuzz/device/cdc/src/fuzz.cc
@@ -143,7 +143,7 @@ void cdc_task(FuzzedDataProvider *provider) {
     // TODO: Fuzz interface number
     (void)tud_cdc_n_write(0, buffer.data(), buffer.size());
   } break;
-  
+
 case kCdcNWriteChar:
   // TODO: Fuzz interface number
   (void)tud_cdc_n_write_char(0, provider->ConsumeIntegral<char>());
@@ -171,4 +171,4 @@ case kMaxValue:
   break;
 }
 }
-}
\ No newline at end of file
+}
diff --git a/test/fuzz/device/msc/CMakeLists.txt b/test/fuzz/device/msc/CMakeLists.txt
index fa6e83b7e..8e4db9d29 100644
--- a/test/fuzz/device/msc/CMakeLists.txt
+++ b/test/fuzz/device/msc/CMakeLists.txt
@@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/test/fuzz/device/msc/src/fuzz.cc b/test/fuzz/device/msc/src/fuzz.cc
index 568900452..371d49882 100644
--- a/test/fuzz/device/msc/src/fuzz.cc
+++ b/test/fuzz/device/msc/src/fuzz.cc
@@ -59,4 +59,3 @@ extern "C" int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) {
 
   return 0;
 }
-
diff --git a/test/fuzz/device/net/CMakeLists.txt b/test/fuzz/device/net/CMakeLists.txt
index fa6e83b7e..8e4db9d29 100644
--- a/test/fuzz/device/net/CMakeLists.txt
+++ b/test/fuzz/device/net/CMakeLists.txt
@@ -26,4 +26,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
\ No newline at end of file
+family_configure_device_example(${PROJECT})
diff --git a/test/fuzz/device/net/src/arch/cc.h b/test/fuzz/device/net/src/arch/cc.h
index 56a0cacf7..9f30b91cb 100644
--- a/test/fuzz/device/net/src/arch/cc.h
+++ b/test/fuzz/device/net/src/arch/cc.h
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
@@ -11,21 +11,21 @@
  *    this list of conditions and the following disclaimer in the documentation
  *    and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
+ *    derived from this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  * OF SUCH DAMAGE.
  *
  * This file is part of the lwIP TCP/IP stack.
- * 
+ *
  * Author: Adam Dunkels <adam@sics.se>
  *
  */
@@ -42,7 +42,7 @@ typedef int sys_prot_t;
 #if defined (__ICCARM__)
 
 #define PACK_STRUCT_BEGIN
-#define PACK_STRUCT_STRUCT 
+#define PACK_STRUCT_STRUCT
 #define PACK_STRUCT_END
 #define PACK_STRUCT_FIELD(x) x
 #define PACK_STRUCT_USE_INCLUDES
@@ -50,7 +50,7 @@ typedef int sys_prot_t;
 #elif defined (__CC_ARM)
 
 #define PACK_STRUCT_BEGIN __packed
-#define PACK_STRUCT_STRUCT 
+#define PACK_STRUCT_STRUCT
 #define PACK_STRUCT_END
 #define PACK_STRUCT_FIELD(x) x
 
diff --git a/test/fuzz/device/net/src/fuzz.cc b/test/fuzz/device/net/src/fuzz.cc
index ea4943665..a6935928a 100644
--- a/test/fuzz/device/net/src/fuzz.cc
+++ b/test/fuzz/device/net/src/fuzz.cc
@@ -81,7 +81,7 @@ void net_task(FuzzedDataProvider *provider) {
 
   assert(provider != NULL);
   switch (provider->ConsumeEnum<NetApiFuncs>()) {
-  
+
   case kNetworkRecvRenew:
     tud_network_recv_renew();
     break;
diff --git a/test/fuzz/device/net/src/lwipopts.h b/test/fuzz/device/net/src/lwipopts.h
index a215017c7..336c9243d 100644
--- a/test/fuzz/device/net/src/lwipopts.h
+++ b/test/fuzz/device/net/src/lwipopts.h
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
- * All rights reserved. 
- * 
- * Redistribution and use in source and binary forms, with or without modification, 
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
  *
  * 1. Redistributions of source code must retain the above copyright notice,
@@ -11,21 +11,21 @@
  *    this list of conditions and the following disclaimer in the documentation
  *    and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission. 
+ *    derived from this software without specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  * OF SUCH DAMAGE.
  *
  * This file is part of the lwIP TCP/IP stack.
- * 
+ *
  * Author: Simon Goldschmidt
  *
  */
diff --git a/test/fuzz/dicts/cdc.dict b/test/fuzz/dicts/cdc.dict
index 138775cdc..421eb8ed9 100644
--- a/test/fuzz/dicts/cdc.dict
+++ b/test/fuzz/dicts/cdc.dict
@@ -71,4 +71,3 @@ RNDIS_PACKET_TYPE_FUNCTIONAL="\x00\x00\x40\x00"
 # NIC driver frames that a Token Ring NIC receives.
 RNDIS_PACKET_TYPE_MAC_FRAME="\x00\x00\x80\x00"
 RNDIS_PACKET_TYPE_NO_LOCAL="\x00\x01\x00\x00"
-
diff --git a/test/fuzz/make.mk b/test/fuzz/make.mk
index 934819665..b7b6d6a75 100644
--- a/test/fuzz/make.mk
+++ b/test/fuzz/make.mk
@@ -114,7 +114,7 @@ CXXFLAGS += \
 
 # conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion
 #  -Wconversion
-  
+
 # Debugging/Optimization
 ifeq ($(DEBUG), 1)
   CFLAGS += -Og
@@ -132,4 +132,3 @@ endif
 ifneq ($(LOGGER),)
 	CMAKE_DEFSYM +=	-DLOGGER=$(LOGGER)
 endif
-
diff --git a/test/fuzz/msc_fuzz.cc b/test/fuzz/msc_fuzz.cc
index e906ca971..6e838a682 100644
--- a/test/fuzz/msc_fuzz.cc
+++ b/test/fuzz/msc_fuzz.cc
@@ -159,4 +159,4 @@ int32_t tud_msc_scsi_cb(uint8_t lun, uint8_t const scsi_cmd[16], void *buffer,
 }
 }
 
-#endif
\ No newline at end of file
+#endif
diff --git a/test/fuzz/net_fuzz.cc b/test/fuzz/net_fuzz.cc
index 8467d6d8e..3158e74ef 100644
--- a/test/fuzz/net_fuzz.cc
+++ b/test/fuzz/net_fuzz.cc
@@ -79,4 +79,4 @@ void tud_network_link_state_cb(bool state) {
 }
 }
 
-#endif
\ No newline at end of file
+#endif
diff --git a/test/fuzz/rules.mk b/test/fuzz/rules.mk
index d9c2a1a77..825abddc5 100644
--- a/test/fuzz/rules.mk
+++ b/test/fuzz/rules.mk
@@ -89,7 +89,7 @@ endif
 # Rules
 # ---------------------------------------
 
-all: $(BUILD)/$(PROJECT) 
+all: $(BUILD)/$(PROJECT)
 
 OBJ_DIRS = $(sort $(dir $(OBJ)))
 $(OBJ): | $(OBJ_DIRS)
@@ -111,7 +111,7 @@ vpath %.c . $(TOP)
 $(BUILD)/obj/%.o: %.c
 	@echo CC $(notdir $@)
 	@$(CC) $(CFLAGS) -c -MD -o $@ $<
-	
+
 # All cpp srcs
 vpath %.cc . $(TOP)
 $(BUILD)/obj/%_cxx.o: %.cc
@@ -158,4 +158,4 @@ linkermap: $(BUILD)/$(PROJECT)
 # Print out the value of a make variable.
 # https://stackoverflow.com/questions/16467718/how-to-print-out-a-variable-in-makefile
 print-%:
-	@echo $* = $($*)
\ No newline at end of file
+	@echo $* = $($*)
diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c
index 63684e76a..c757cdcfa 100644
--- a/test/unit-test/test/device/msc/test_msc_device.c
+++ b/test/unit-test/test/device/msc/test_msc_device.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, hathach (tinyusb.org)
diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c
index ad95eb47a..dcded605a 100644
--- a/test/unit-test/test/device/usbd/test_usbd.c
+++ b/test/unit-test/test/device/usbd/test_usbd.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/test/unit-test/test/test_fifo.c b/test/unit-test/test/test_fifo.c
index 28be6d8fc..3b4deb33e 100644
--- a/test/unit-test/test/test_fifo.c
+++ b/test/unit-test/test/test_fifo.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling.rb b/test/unit-test/vendor/ceedling/lib/ceedling.rb
index 7f3400236..6c57fb48d 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling.rb
@@ -96,4 +96,3 @@ module Ceedling
     DEFAULT_CEEDLING_CONFIG[:plugins][:load_paths] << gem_dir
   end
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
index 5727bcabc..31abe6d99 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/build_invoker_utils.rb
@@ -5,7 +5,7 @@ require 'ceedling/constants'
 class BuildInvokerUtils
 
   constructor :configurator, :streaminator
- 
+
   ##
   # Processes exceptions and tries to display a useful message for the user.
   #
@@ -13,27 +13,27 @@ class BuildInvokerUtils
   #
   # * _exception_:  The exception given by a rescue statement.
   # * _context_:    A symbol representing where in the build the exception
-  # occurs. 
+  # occurs.
   # * _test_build_: A bool to signify if the exception occurred while building
   # from test or source.
   #
   def process_exception(exception, context, test_build=true)
     if (exception.message =~ /Don't know how to build task '(.+)'/i)
       error_header  = "ERROR: Rake could not find file referenced in source"
-      error_header += " or test" if (test_build) 
+      error_header += " or test" if (test_build)
       error_header += ": '#{$1}'. Possible stale dependency."
-      
+
       @streaminator.stderr_puts( error_header )
 
       if (@configurator.project_use_deep_dependencies)
-        help_message = "Try fixing #include statements or adding missing file. Then run '#{REFRESH_TASK_ROOT}#{context.to_s}' task and try again."      
+        help_message = "Try fixing #include statements or adding missing file. Then run '#{REFRESH_TASK_ROOT}#{context.to_s}' task and try again."
         @streaminator.stderr_puts( help_message )
       end
-      
+
       raise ''
     else
       raise exception
     end
   end
-  
+
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator.rb
index 519a4aab4..fd7451fa7 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator.rb
@@ -2,7 +2,7 @@
 class Cacheinator
 
   constructor :cacheinator_helper, :file_path_utils, :file_wrapper, :yaml_wrapper
-  
+
   def cache_test_config(hash)
     @yaml_wrapper.dump( @file_path_utils.form_test_build_cache_path( INPUT_CONFIGURATION_CACHE_FILE), hash )
   end
@@ -11,15 +11,15 @@ class Cacheinator
     @yaml_wrapper.dump( @file_path_utils.form_release_build_cache_path( INPUT_CONFIGURATION_CACHE_FILE ), hash )
   end
 
-  
+
   def diff_cached_test_file( filepath )
     cached_filepath = @file_path_utils.form_test_build_cache_path( filepath )
-  
+
     if (@file_wrapper.exist?( cached_filepath ) and (!@file_wrapper.compare( filepath, cached_filepath )))
       @file_wrapper.cp(filepath, cached_filepath, {:preserve => false})
       return filepath
     elsif (!@file_wrapper.exist?( cached_filepath ))
-      @file_wrapper.cp(filepath, cached_filepath, {:preserve => false}) 
+      @file_wrapper.cp(filepath, cached_filepath, {:preserve => false})
       return filepath
     end
 
@@ -43,5 +43,5 @@ class Cacheinator
 
     return @cacheinator_helper.diff_cached_config?( cached_filepath, hash )
   end
-  
+
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
index 14e8a6ef0..b7fa5863f 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/cacheinator_helper.rb
@@ -2,7 +2,7 @@
 class CacheinatorHelper
 
   constructor :file_wrapper, :yaml_wrapper
-  
+
   def diff_cached_config?(cached_filepath, hash)
     return false if ( not @file_wrapper.exist?(cached_filepath) )
     return true if (@yaml_wrapper.load(cached_filepath) != hash)
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/cmock_builder.rb b/test/unit-test/vendor/ceedling/lib/ceedling/cmock_builder.rb
index 4a74aa842..82ef96135 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/cmock_builder.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/cmock_builder.rb
@@ -1,13 +1,13 @@
 require 'cmock'
 
 class CmockBuilder
-  
+
   attr_accessor :cmock
-  
-  def setup 
+
+  def setup
     @cmock = nil
   end
-  
+
   def manufacture(cmock_config)
     @cmock = CMock.new(cmock_config)
   end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/configurator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator.rb
index 0ae4d04a8..8dc11aa5a 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/configurator.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/configurator.rb
@@ -379,4 +379,3 @@ class Configurator
 
 
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_plugins.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
index 75bcd982d..c2e198597 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_plugins.rb
@@ -109,7 +109,7 @@ class ConfiguratorPlugins
     return defaults_with_path
   end
 
-  # gather up and return 
+  # gather up and return
   def find_plugin_hash_defaults(config, plugin_paths)
     defaults_hash= []
 
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_setup.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_setup.rb
index c43bb5c12..cba88df3c 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_setup.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_setup.rb
@@ -79,7 +79,7 @@ class ConfiguratorSetup
 
     if config[:cmock][:unity_helper]
       config[:cmock][:unity_helper].each do |path|
-        validation << @configurator_validator.validate_filepath_simple( path, :cmock, :unity_helper ) 
+        validation << @configurator_validator.validate_filepath_simple( path, :cmock, :unity_helper )
       end
     end
 
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_validator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_validator.rb
index fc0210124..fc2950e0b 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/configurator_validator.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/configurator_validator.rb
@@ -6,7 +6,7 @@ require 'ceedling/file_path_utils'  # for glob handling class methods
 
 
 class ConfiguratorValidator
-  
+
   constructor :file_wrapper, :stream_wrapper, :system_wrapper
 
   # walk into config hash verify existence of data at key depth
@@ -16,9 +16,9 @@ class ConfiguratorValidator
 
     if (not exist)
       # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-      @stream_wrapper.stderr_puts("ERROR: Required config file entry #{format_key_sequence(keys, hash[:depth])} does not exist.")    
+      @stream_wrapper.stderr_puts("ERROR: Required config file entry #{format_key_sequence(keys, hash[:depth])} does not exist.")
     end
-    
+
     return exist
   end
 
@@ -33,39 +33,39 @@ class ConfiguratorValidator
 
     path_list = []
     exist = true
-    
+
     case list
       when String then path_list << list
       when Array  then path_list =  list
     end
-    
+
     path_list.each do |path|
       base_path = FilePathUtils::extract_path(path) # lop off add/subtract notation & glob specifiers
-      
+
       if (not @file_wrapper.exist?(base_path))
         # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-        @stream_wrapper.stderr_puts("ERROR: Config path #{format_key_sequence(keys, hash[:depth])}['#{base_path}'] does not exist on disk.") 
+        @stream_wrapper.stderr_puts("ERROR: Config path #{format_key_sequence(keys, hash[:depth])}['#{base_path}'] does not exist on disk.")
         exist = false
-      end 
+      end
     end
-    
+
     return exist
   end
 
-  
+
   # simple path verification
   def validate_filepath_simple(path, *keys)
     validate_path = path
-    
+
     if (not @file_wrapper.exist?(validate_path))
       # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-      @stream_wrapper.stderr_puts("ERROR: Config path '#{validate_path}' associated with #{format_key_sequence(keys, keys.size)} does not exist on disk.") 
+      @stream_wrapper.stderr_puts("ERROR: Config path '#{validate_path}' associated with #{format_key_sequence(keys, keys.size)} does not exist on disk.")
       return false
-    end 
-    
+    end
+
     return true
   end
- 
+
   # walk into config hash. verify specified file exists.
   def validate_filepath(config, *keys)
     hash          = retrieve_value(config, keys)
@@ -76,21 +76,21 @@ class ConfiguratorValidator
 
     # skip everything if we've got an argument replacement pattern
     return true if (filepath =~ TOOL_EXECUTOR_ARGUMENT_REPLACEMENT_PATTERN)
-    
+
     if (not @file_wrapper.exist?(filepath))
 
       # See if we can deal with it internally.
-      if GENERATED_DIR_PATH.include?(filepath)      
+      if GENERATED_DIR_PATH.include?(filepath)
         # we already made this directory before let's make it again.
         FileUtils.mkdir_p File.join(File.dirname(__FILE__), filepath)
-        @stream_wrapper.stderr_puts("WARNING: Generated filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk. Recreating") 
- 
+        @stream_wrapper.stderr_puts("WARNING: Generated filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk. Recreating")
+
       else
         # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
         @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk.")
         return false
       end
-    end      
+    end
 
     return true
   end
@@ -106,17 +106,17 @@ class ConfiguratorValidator
 
     # skip everything if we've got an argument replacement pattern
     return true if (filepath =~ TOOL_EXECUTOR_ARGUMENT_REPLACEMENT_PATTERN)
-    
+
     # if there's no path included, verify file exists somewhere in system search paths
     if (not filepath.include?('/'))
       exists = false
-      
+
       @system_wrapper.search_paths.each do |path|
         if (@file_wrapper.exist?( File.join(path, filepath)) )
           exists = true
           break
         end
-        
+
         if (@file_wrapper.exist?( (File.join(path, filepath)).ext( exe_extension ) ))
           exists = true
           break
@@ -125,25 +125,25 @@ class ConfiguratorValidator
           break
         end
       end
-      
+
       if (not exists)
         # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-        @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist in system search paths.") 
-        return false        
+        @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist in system search paths.")
+        return false
       end
-      
+
     # if there is a path included, check that explicit filepath exists
     else
       if (not @file_wrapper.exist?(filepath))
         # no verbosity checking since this is lowest level anyhow & verbosity checking depends on configurator
-        @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk.") 
+        @stream_wrapper.stderr_puts("ERROR: Config filepath #{format_key_sequence(keys, hash[:depth])}['#{filepath}'] does not exist on disk.")
         return false
-      end      
+      end
     end
 
     return true
   end
-  
+
   def validate_tool_stderr_redirect(config, tools, tool)
     redirect = config[tools][tool][:stderr_redirect]
     if (redirect.class == Symbol)
@@ -151,17 +151,17 @@ class ConfiguratorValidator
       if (not StdErrRedirect.constants.map{|constant| constant.to_s}.include?(redirect.to_s.upcase))
         error = "ERROR: [:#{tools}][:#{tool}][:stderr_redirect][:#{redirect}] is not a recognized option " +
                 "{#{StdErrRedirect.constants.map{|constant| ':' + constant.to_s.downcase}.join(', ')}}."
-        @stream_wrapper.stderr_puts(error) 
-        return false        
+        @stream_wrapper.stderr_puts(error)
+        return false
       end
     end
-    
+
     return true
   end
-  
+
   private #########################################
-  
-  
+
+
   def retrieve_value(config, keys)
     value = nil
     hash  = config
@@ -178,7 +178,7 @@ class ConfiguratorValidator
         break
       end
     end
-    
+
     return {:value => value, :depth => depth}
   end
 
@@ -186,8 +186,8 @@ class ConfiguratorValidator
   def format_key_sequence(keys, depth)
     walked_keys    = keys.slice(0, depth)
     formatted_keys = walked_keys.map{|key| "[:#{key.to_s}]"}
-    
+
     return formatted_keys.join
   end
-  
+
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/erb_wrapper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/erb_wrapper.rb
index 8d70b6d28..dab8d736b 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/erb_wrapper.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/erb_wrapper.rb
@@ -6,4 +6,4 @@ class ErbWrapper
       f << ERB.new(template, 0, "<>").result(binding)
     end
   end
-end
\ No newline at end of file
+end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/file_finder.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_finder.rb
index 53775b7bb..4a1064c52 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/file_finder.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/file_finder.rb
@@ -146,4 +146,3 @@ class FileFinder
     return @file_finder_helper.find_file_in_collection(file_path, file_list, complain)
   end
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/file_finder_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
index a168e5cb5..f2d6a5e91 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/file_finder_helper.rb
@@ -4,11 +4,11 @@ require 'ceedling/constants' # for Verbosity enumeration
 class FileFinderHelper
 
   constructor :streaminator
-  
-  
+
+
   def find_file_in_collection(file_name, file_list, complain, extra_message="")
     file_to_find = nil
-    
+
     file_list.each do |item|
       base_file = File.basename(item)
 
@@ -22,29 +22,29 @@ class FileFinderHelper
           blow_up(file_name, "However, a filename having different capitalization was found: '#{item}'.")
         end
       end
-      
+
     end
-    
+
     if file_to_find.nil?
       case (complain)
-        when :error then blow_up(file_name, extra_message) 
+        when :error then blow_up(file_name, extra_message)
         when :warn  then gripe(file_name, extra_message)
-        #when :ignore then      
+        #when :ignore then
       end
     end
-    
+
     return file_to_find
   end
 
   private
-  
+
   def blow_up(file_name, extra_message="")
     error = "ERROR: Found no file '#{file_name}' in search paths."
     error += ' ' if (extra_message.length > 0)
     @streaminator.stderr_puts(error + extra_message, Verbosity::ERRORS)
     raise
   end
-  
+
   def gripe(file_name, extra_message="")
     warning = "WARNING: Found no file '#{file_name}' in search paths."
     warning += ' ' if (extra_message.length > 0)
@@ -52,5 +52,3 @@ class FileFinderHelper
   end
 
 end
-
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/file_system_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_system_utils.rb
index 97e5856fb..245d8f826 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/file_system_utils.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/file_system_utils.rb
@@ -6,7 +6,7 @@ require 'ceedling/file_path_utils'
 
 
 class FileSystemUtils
-  
+
   constructor :file_wrapper
 
   # build up path list from input of one or more strings or arrays of (+/-) paths & globs
@@ -14,7 +14,7 @@ class FileSystemUtils
     raw   = []  # all paths and globs
     plus  = Set.new # all paths to expand and add
     minus = Set.new # all paths to remove from plus set
-    
+
     # assemble all globs and simple paths, reforming our glob notation to ruby globs
     paths.each do |paths_container|
       case (paths_container)
@@ -26,29 +26,29 @@ class FileSystemUtils
 
     # iterate through each path and glob
     raw.each do |path|
-    
+
       dirs = []  # container for only (expanded) paths
-    
+
       # if a glob, expand it and slurp up all non-file paths
       if path.include?('*')
         # grab base directory only if globs are snug up to final path separator
         if (path =~ /\/\*+$/)
           dirs << FilePathUtils.extract_path(path)
         end
-        
+
         # grab expanded sub-directory globs
         expanded = @file_wrapper.directory_listing( FilePathUtils.extract_path_no_aggregation_operators(path) )
         expanded.each do |entry|
           dirs << entry if @file_wrapper.directory?(entry)
         end
-        
+
       # else just grab simple path
       # note: we could just run this through glob expansion but such an
       #       approach doesn't handle a path not yet on disk)
       else
         dirs << FilePathUtils.extract_path_no_aggregation_operators(path)
       end
-      
+
       # add dirs to the appropriate set based on path aggregation modifier if present
       FilePathUtils.add_path?(path) ? plus.merge(dirs) : minus.merge(dirs)
     end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb
index 807cbd23f..1bb2883ee 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/file_system_wrapper.rb
@@ -7,4 +7,4 @@ class FileSystemWrapper
     end
   end
 
-end
\ No newline at end of file
+end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/flaginator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/flaginator.rb
index 31d62c46a..175b3c5ac 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/flaginator.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/flaginator.rb
@@ -29,25 +29,25 @@ class Flaginator
 
   def get_flag(hash, file_name)
     file_key = file_name.to_sym
-   
+
     # 1. try literals
-    literals, magic = partition(hash) { |k, v| k.to_s =~ /^\w+$/ }  
+    literals, magic = partition(hash) { |k, v| k.to_s =~ /^\w+$/ }
     return literals[file_key] if literals.include?(file_key)
-    
+
     any, regex = partition(magic) { |k, v| (k == :'*') || (k == :'.*')  } # glob or regex wild card
-    
+
     # 2. try regexes
     find_res = regex.find { |k, v| file_name =~ /^#{k.to_s}$/ }
     return find_res[1] if find_res
-    
+
     # 3. try anything
     find_res = any.find { |k, v| file_name =~ /.*/ }
     return find_res[1] if find_res
-      
+
     # 4. well, we've tried
     return []
   end
-  
+
   def flag_down( operation, context, file )
     # create configurator accessor method
     accessor = ('flags_' + context.to_s).to_sym
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/generator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator_helper.rb
index 343156092..a6682c275 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/generator_helper.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/generator_helper.rb
@@ -9,7 +9,7 @@ class GeneratorHelper
   def test_results_error_handler(executable, shell_result)
     notice = ''
     error  = false
-    
+
     if (shell_result[:output].nil? or shell_result[:output].strip.empty?)
       error = true
       # mirror style of generic tool_executor failure output
@@ -24,7 +24,7 @@ class GeneratorHelper
                 "> Produced no final test result counts in $stdout:\n" +
                 "#{shell_result[:output].strip}\n"
     end
-    
+
     if (error)
       # since we told the tool executor to ignore the exit code, handle it explicitly here
       notice += "> And exited with status: [#{shell_result[:exit_code]}] (count of failed tests).\n" if (shell_result[:exit_code] != nil)
@@ -33,8 +33,8 @@ class GeneratorHelper
       notice += "> This is often a symptom of a bad memory access in source or test code.\n\n"
 
       @streaminator.stderr_puts(notice, Verbosity::COMPLAIN)
-      raise      
+      raise
     end
   end
-  
+
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results.rb
index 3af2d720a..2cd96478c 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results.rb
@@ -77,7 +77,7 @@ class GeneratorTestResults
     # handle anything preceding filename in line as extra output to be collected
     stdout = nil
     stdout_regex = /(.+)#{Regexp.escape(filename)}.+/i
-    unity_test_time = 0 
+    unity_test_time = 0
 
     if (line =~ stdout_regex)
       stdout = $1.clone
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb
index 0b518325b..1d193c844 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/generator_test_results_sanity_checker.rb
@@ -6,34 +6,34 @@ require 'ceedling/constants'
 class GeneratorTestResultsSanityChecker
 
   constructor :configurator, :streaminator
-  
+
   def verify(results, unity_exit_code)
-  
+
     # do no sanity checking if it's disabled
     return if (@configurator.sanity_checks == TestResultsSanityChecks::NONE)
     raise "results nil or empty" if results.nil? || results.empty?
 
-    ceedling_ignores_count   = results[:ignores].size 
+    ceedling_ignores_count   = results[:ignores].size
     ceedling_failures_count  = results[:failures].size
     ceedling_tests_summation = (ceedling_ignores_count + ceedling_failures_count + results[:successes].size)
 
-    # Exit code handling is not a sanity check that can always be performed because 
+    # Exit code handling is not a sanity check that can always be performed because
     # command line simulators may or may not pass through Unity's exit code
     if (@configurator.sanity_checks >= TestResultsSanityChecks::THOROUGH)
       # many platforms limit exit codes to a maximum of 255
       if ((ceedling_failures_count != unity_exit_code) and (unity_exit_code < 255))
         sanity_check_warning(results[:source][:file], "Unity's exit code (#{unity_exit_code}) does not match Ceedling's summation of failed test cases (#{ceedling_failures_count}).")
       end
-      
+
       if ((ceedling_failures_count < 255) and (unity_exit_code == 255))
         sanity_check_warning(results[:source][:file], "Ceedling's summation of failed test cases (#{ceedling_failures_count}) is less than Unity's exit code (255 or more).")
       end
     end
-    
+
     if (ceedling_ignores_count != results[:counts][:ignored])
       sanity_check_warning(results[:source][:file], "Unity's final ignore count (#{results[:counts][:ignored]}) does not match Ceedling's summation of ignored test cases (#{ceedling_ignores_count}).")
     end
-    
+
     if (ceedling_failures_count != results[:counts][:failed])
       sanity_check_warning(results[:source][:file], "Unity's final fail count (#{results[:counts][:failed]}) does not match Ceedling's summation of failed test cases (#{ceedling_failures_count}).")
     end
@@ -41,14 +41,14 @@ class GeneratorTestResultsSanityChecker
     if (ceedling_tests_summation != results[:counts][:total])
       sanity_check_warning(results[:source][:file], "Unity's final test count (#{results[:counts][:total]}) does not match Ceedling's summation of all test cases (#{ceedling_tests_summation}).")
     end
-    
+
   end
 
   private
-  
+
   def sanity_check_warning(file, message)
     unless defined?(CEEDLING_IGNORE_SANITY_CHECK)
-      notice = "\n" + 
+      notice = "\n" +
                "ERROR: Internal sanity check for test fixture '#{file.ext(@configurator.extension_executable)}' finds that #{message}\n" +
                "  Possible causes:\n" +
                "    1. Your test + source dereferenced a null pointer.\n" +
@@ -56,7 +56,7 @@ class GeneratorTestResultsSanityChecker
                "    3. Your test + source committed a memory access violation.\n" +
                "    4. Your test fixture produced an exit code of 0 despite execution ending prematurely.\n" +
                "  Sanity check failures of test results are usually a symptom of interrupted test execution.\n\n"
-      
+
       @streaminator.stderr_puts( notice )
       raise
     end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/loginator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/loginator.rb
index 92276e1df..38147b322 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/loginator.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/loginator.rb
@@ -11,7 +11,7 @@ class Loginator
     config_files.concat( @project_config_manager.options_files )
     config_files.compact!
     config_files.map! { |file| file.ext('') }
-    
+
     log_name = config_files.join( '_' )
 
     @project_log_filepath = File.join( @configurator.project_log_path, log_name.ext('.log') )
@@ -20,12 +20,12 @@ class Loginator
 
   def log(string, heading=nil)
     return if (not @configurator.project_logging)
-  
+
     output  = "\n[#{@system_wrapper.time_now}]"
     output += " :: #{heading}" if (not heading.nil?)
     output += "\n#{string.strip}\n"
 
     @file_wrapper.write(@project_log_filepath, output, 'a')
   end
-  
+
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/makefile.rb b/test/unit-test/vendor/ceedling/lib/ceedling/makefile.rb
index c3d7496d2..9ad894ea0 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/makefile.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/makefile.rb
@@ -1,6 +1,6 @@
 
 # modified version of Rake's provided make-style dependency loader
-# customizations: 
+# customizations:
 #  (1) handles windows drives in paths -- colons don't confuse task demarcation
 #  (2) handles spaces in directory paths
 
@@ -29,7 +29,7 @@ module Rake
       file_tasks, args = line.split(/:\s/)
 
       return if args.nil?
-      
+
       # split at non-escaped space boundary between files (i.e. escaped spaces in paths are left alone)
       dependents = args.split(/\b\s+/)
       # replace escaped spaces and clean up any extra whitespace
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/objects.yml b/test/unit-test/vendor/ceedling/lib/ceedling/objects.yml
index 43bbc066c..d73987f7c 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/objects.yml
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/objects.yml
@@ -223,7 +223,7 @@ dependinator:
     - configurator
     - project_config_manager
     - test_includes_extractor
-    - file_path_utils 
+    - file_path_utils
     - rake_wrapper
     - file_wrapper
 
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/par_map.rb b/test/unit-test/vendor/ceedling/lib/ceedling/par_map.rb
index 98198a2ce..250b5ad30 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/par_map.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/par_map.rb
@@ -16,4 +16,3 @@ def par_map(n, things, &block)
   end
   threads.each { |t| t.join }
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/plugin.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin.rb
index f20b3a3b2..835c08c52 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/plugin.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/plugin.rb
@@ -5,7 +5,7 @@ class String
   def left_margin(margin=0)
     non_whitespace_column = 0
     new_lines = []
-    
+
     # find first line with non-whitespace and count left columns of whitespace
     self.each_line do |line|
       if (line =~ /^\s*\S/)
@@ -13,7 +13,7 @@ class String
         break
       end
     end
-    
+
     # iterate through each line, chopping off leftmost whitespace columns and add back the desired whitespace margin
     self.each_line do |line|
       columns = []
@@ -25,7 +25,7 @@ class String
         new_lines << "\n"
       end
     end
-    
+
     return new_lines.join
   end
 end
@@ -74,7 +74,7 @@ class Plugin
   # whole shebang (any use of Ceedling)
   def pre_build; end
   def post_build; end
-  
+
   def summary; end
 
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_builder.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_builder.rb
index 1269141f1..a010e1d0f 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_builder.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_builder.rb
@@ -23,7 +23,7 @@ class PluginBuilder
   end
 
   private
-  
+
   def camelize(underscored_name)
     return underscored_name.gsub(/(_|^)([a-z0-9])/) {$2.upcase}
   end
@@ -50,4 +50,4 @@ class PluginBuilder
     end
   end
 
-end
\ No newline at end of file
+end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb
index 8d83727ba..afc54494b 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator.rb
@@ -2,46 +2,46 @@ require 'ceedling/constants'
 require 'ceedling/defaults'
 
 class PluginReportinator
-  
+
   constructor :plugin_reportinator_helper, :plugin_manager, :reportinator
 
   def setup
     @test_results_template = nil
   end
-  
-  
+
+
   def set_system_objects(system_objects)
     @plugin_reportinator_helper.ceedling = system_objects
   end
-  
-  
+
+
   def fetch_results(results_path, test, options={:boom => false})
     return @plugin_reportinator_helper.fetch_results( File.join(results_path, test), options )
   end
 
-  
+
   def generate_banner(message)
     return @reportinator.generate_banner(message)
   end
 
-  
+
   def assemble_test_results(results_list, options={:boom => false})
     aggregated_results = get_results_structure
-    
-    results_list.each do |result_path| 
+
+    results_list.each do |result_path|
       results = @plugin_reportinator_helper.fetch_results( result_path, options )
       @plugin_reportinator_helper.process_results(aggregated_results, results)
     end
 
     return aggregated_results
   end
-  
-  
+
+
   def register_test_results_template(template)
     @test_results_template = template if (@test_results_template.nil?)
   end
-  
-  
+
+
   def run_test_results_report(hash, verbosity=Verbosity::NORMAL, &block)
     run_report( $stdout,
                 ((@test_results_template.nil?) ? DEFAULT_TESTS_RESULTS_REPORT_TEMPLATE : @test_results_template),
@@ -49,19 +49,19 @@ class PluginReportinator
                 verbosity,
                 &block )
   end
-  
-  
+
+
   def run_report(stream, template, hash=nil, verbosity=Verbosity::NORMAL)
     failure = nil
     failure = yield() if block_given?
-  
+
     @plugin_manager.register_build_failure( failure )
-    
+
     @plugin_reportinator_helper.run_report( stream, template, hash, verbosity )
   end
-  
+
   private ###############################
-  
+
   def get_results_structure
     return {
       :successes => [],
@@ -72,5 +72,5 @@ class PluginReportinator
       :time      => 0.0
       }
   end
- 
+
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb
index 322a530b5..783158797 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/plugin_reportinator_helper.rb
@@ -4,11 +4,11 @@ require 'rake' # for ext()
 require 'ceedling/constants'
 
 class PluginReportinatorHelper
-  
+
   attr_writer :ceedling
-  
+
   constructor :configurator, :streaminator, :yaml_wrapper, :file_wrapper
-  
+
   def fetch_results(results_path, options)
     pass_path = File.join(results_path.ext( @configurator.extension_testpass ))
     fail_path = File.join(results_path.ext( @configurator.extension_testfail ))
@@ -23,7 +23,7 @@ class PluginReportinatorHelper
         raise
       end
     end
-    
+
     return {}
   end
 
@@ -47,5 +47,5 @@ class PluginReportinatorHelper
     output = ERB.new(template, 0, "%<>")
     @streaminator.stream_puts(stream, output.result(binding()), verbosity)
   end
-  
+
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
index 8b89c0b3a..916d31332 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
@@ -94,7 +94,7 @@ class PreprocessinatorIncludesHandler
     target_file = make_rule.split[0].gsub(':', '').gsub('\\','/')
     base = File.basename(target_file, File.extname(target_file))
     make_rule_dependencies = make_rule.gsub(/.*\b#{Regexp.escape(base)}\S*/, '').gsub(/\\$/, '')
-    
+
     # Extract the headers dependencies from the make rule
     hdr_ext = @configurator.extension_header
     headers_dependencies = make_rule_dependencies.split.find_all {|path| path.end_with?(hdr_ext) }.uniq
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/project_config_manager.rb b/test/unit-test/vendor/ceedling/lib/ceedling/project_config_manager.rb
index ed7a73b8c..b1d455127 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/project_config_manager.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/project_config_manager.rb
@@ -20,7 +20,7 @@ class ProjectConfigManager
   def merge_options(config_hash, option_filepath)
     @options_files << File.basename( option_filepath )
     config_hash.deep_merge!( @yaml_wrapper.load( option_filepath ) )
-  end 
+  end
 
 
   def filter_internal_sources(sources)
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rake_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/rake_utils.rb
index 3f667c852..b13749738 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/rake_utils.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/rake_utils.rb
@@ -1,6 +1,6 @@
 
 class RakeUtils
-  
+
   constructor :rake_wrapper
 
   def task_invoked?(task_regex)
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/reportinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/reportinator.rb
index 0f583d06d..fcb5286b9 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/reportinator.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/reportinator.rb
@@ -14,8 +14,8 @@ class Reportinator
   # ==== Examples
   #
   #    rp = Reportinator.new
-  #    rp.generate_banner("Hello world!") => "------------\nHello world!\n------------\n" 
-  #    rp.generate_banner("Hello world!", 3) => "---\nHello world!\n---\n" 
+  #    rp.generate_banner("Hello world!") => "------------\nHello world!\n------------\n"
+  #    rp.generate_banner("Hello world!", 3) => "---\nHello world!\n---\n"
   #
   #
   def generate_banner(message, width=nil)
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_cmock.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_cmock.rake
index 70ddcbc2e..51485d3a8 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_cmock.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_cmock.rake
@@ -3,7 +3,7 @@
 rule(/#{CMOCK_MOCK_PREFIX}[^\/\\]+#{'\\'+EXTENSION_SOURCE}$/ => [
     proc do |task_name|
       @ceedling[:file_finder].find_header_input_for_mock_file(task_name)
-    end  
+    end
   ]) do |mock|
   @ceedling[:generator].generate_mock(TEST_SYM, mock.source)
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
index c29111272..936961ce8 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
@@ -6,7 +6,7 @@
 rule(/#{PROJECT_TEST_PREPROCESS_FILES_PATH}\/.+/ => [
     proc do |task_name|
       @ceedling[:file_finder].find_test_or_source_or_header_file(task_name)
-    end  
+    end
   ]) do |file|
   if (not @ceedling[:configurator].project_use_deep_dependencies)
     raise 'ERROR: Ceedling preprocessing rule invoked though neccessary auxiliary dependency support not enabled.'
@@ -19,8 +19,7 @@ end
 rule(/#{PROJECT_TEST_PREPROCESS_INCLUDES_PATH}\/.+/ => [
     proc do |task_name|
       @ceedling[:file_finder].find_test_or_source_or_header_file(task_name)
-    end  
+    end
   ]) do |file|
   @ceedling[:generator].generate_shallow_includes_list(TEST_SYM, file.source)
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_release.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_release.rake
index 4a583bd6c..47eec858f 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_release.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_release.rake
@@ -96,4 +96,3 @@ namespace RELEASE_SYM do
   end
 
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake
index 9550783cc..bf944de25 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_release_deep_dependencies.rake
@@ -3,7 +3,7 @@
 rule(/#{PROJECT_RELEASE_DEPENDENCIES_PATH}\/#{'.+\\'+EXTENSION_DEPENDENCIES}$/ => [
     proc do |task_name|
       @ceedling[:file_finder].find_compilation_input_file(task_name, :error, true)
-    end  
+    end
   ]) do |dep|
   @ceedling[:generator].generate_dependencies_file(
   	TOOLS_RELEASE_DEPENDENCIES_GENERATOR,
@@ -12,4 +12,3 @@ rule(/#{PROJECT_RELEASE_DEPENDENCIES_PATH}\/#{'.+\\'+EXTENSION_DEPENDENCIES}$/ =
   	@ceedling[:file_path_utils].form_release_build_c_object_filepath(dep.source),
   	dep.name)
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests.rake
index 61e15e2cc..3ab80f3a9 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests.rake
@@ -70,4 +70,3 @@ namespace TEST_SYM do
     @ceedling[:test_invoker].setup_and_invoke([test.source])
   end
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake
index 7175ee3f2..a8dfd296e 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_tests_deep_dependencies.rake
@@ -12,4 +12,3 @@ rule(/#{PROJECT_TEST_DEPENDENCIES_PATH}\/#{'.+\\'+EXTENSION_DEPENDENCIES}$/ => [
   	@ceedling[:file_path_utils].form_test_build_c_object_filepath(dep.source),
   	dep.name)
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/setupinator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/setupinator.rb
index ea78fd97e..cf9922f07 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/setupinator.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/setupinator.rb
@@ -18,7 +18,7 @@ class Setupinator
     @config_hash = config_hash
 
     # load up all the constants and accessors our rake files, objects, & external scripts will need;
-    # note: configurator modifies the cmock section of the hash with a couple defaults to tie 
+    # note: configurator modifies the cmock section of the hash with a couple defaults to tie
     #       project together - the modified hash is used to build cmock object
     @ceedling[:configurator].populate_defaults( config_hash )
     @ceedling[:configurator].populate_unity_defaults( config_hash )
@@ -31,16 +31,16 @@ class Setupinator
     @ceedling[:configurator].standardize_paths( config_hash )
     @ceedling[:configurator].validate( config_hash )
     @ceedling[:configurator].build( config_hash, :environment )
-    
+
     @ceedling[:configurator].insert_rake_plugins( @ceedling[:configurator].rake_plugins )
     @ceedling[:configurator].tools_supplement_arguments( config_hash )
-    
+
     # merge in any environment variables plugins specify, after the main build
     @ceedling[:plugin_manager].load_plugin_scripts( @ceedling[:configurator].script_plugins, @ceedling ) do |env|
       @ceedling[:configurator].eval_environment_variables( env )
       @ceedling[:configurator].build_supplement( config_hash, env )
     end
-    
+
     @ceedling[:plugin_reportinator].set_system_objects( @ceedling )
     @ceedling[:file_finder].prepare_search_sources
     @ceedling[:loginator].setup_log_filepath
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/stream_wrapper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/stream_wrapper.rb
index 7e160527f..2cee58d3e 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/stream_wrapper.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/stream_wrapper.rb
@@ -16,7 +16,7 @@ class StreamWrapper
   def stdout_flush
     $stdout.flush
   end
-  
+
   def stderr_puts(string)
     $stderr.puts(string)
   end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/streaminator.rb b/test/unit-test/vendor/ceedling/lib/ceedling/streaminator.rb
index b8dcd070f..e30440c7d 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/streaminator.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/streaminator.rb
@@ -12,7 +12,7 @@ class Streaminator
       @stream_wrapper.stdout_puts(string)
       @stream_wrapper.stdout_flush
     end
-    
+
     # write to log as though Verbosity::OBNOXIOUS
     @loginator.log( string, @streaminator_helper.extract_name($stdout) )
   end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/streaminator_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/streaminator_helper.rb
index 9fb5cc0b7..cbaef7c92 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/streaminator_helper.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/streaminator_helper.rb
@@ -8,7 +8,7 @@ class StreaminatorHelper
       when 2 then '#<IO:$stderr>'
       else stream.inspect
     end
-    
+
     return name
   end
 
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb
index 477aba4f1..81bb7bc54 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb
@@ -13,7 +13,7 @@ class SystemUtils
   constructor :system_wrapper
 
   ##
-  # Sets up the class. 
+  # Sets up the class.
   def setup
     @tcsh_shell = nil
   end
@@ -23,7 +23,7 @@ class SystemUtils
   def tcsh_shell?
     # once run a single time, return state determined at that execution
     return @tcsh_shell if not @tcsh_shell.nil?
-  
+
     result = @system_wrapper.shell_backticks('echo $version')
 
     if ((result[:exit_code] == 0) and (result[:output].strip =~ /^tcsh/))
@@ -31,7 +31,7 @@ class SystemUtils
     else
       @tcsh_shell = false
     end
-  
+
     return @tcsh_shell
   end
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/task_invoker.rb b/test/unit-test/vendor/ceedling/lib/ceedling/task_invoker.rb
index 7bfabbb12..35f92ae03 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/task_invoker.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/task_invoker.rb
@@ -11,7 +11,7 @@ class TaskInvoker
     @release_regexs = [/^#{RELEASE_ROOT_NAME}(:|$)/]
     @first_run = true
   end
-  
+
   def add_test_task_regex(regex)
     @test_regexs << regex
   end
@@ -19,26 +19,26 @@ class TaskInvoker
   def add_release_task_regex(regex)
     @release_regexs << regex
   end
-  
+
   def test_invoked?
     invoked = false
-    
+
     @test_regexs.each do |regex|
       invoked = true if (@rake_utils.task_invoked?(regex))
       break if invoked
     end
-    
+
     return invoked
   end
-  
+
   def release_invoked?
     invoked = false
-    
+
     @release_regexs.each do |regex|
       invoked = true if (@rake_utils.task_invoked?(regex))
       break if invoked
     end
-    
+
     return invoked
   end
 
@@ -60,7 +60,7 @@ class TaskInvoker
       @rake_wrapper[mock].invoke
     }
   end
-  
+
   def invoke_test_runner(runner)
     @dependinator.enhance_runner_dependencies( runner )
     reset_rake_task_for_changed_defines( runner )
@@ -112,11 +112,11 @@ class TaskInvoker
       @rake_wrapper[file].invoke
     end
   end
-  
+
   def invoke_release_objects(objects)
     par_map(PROJECT_COMPILE_THREADS, objects) do |object|
       @rake_wrapper[object].invoke
     end
   end
-  
+
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_base.rake b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_base.rake
index a35cde75e..67a3b503a 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_base.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_base.rake
@@ -113,4 +113,3 @@ task :summary do
   puts "\nNOTE: Summaries may be out of date with project sources.\n\n"
 end
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake
index 7b950ca0b..8263955fa 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_filesystem.rake
@@ -109,5 +109,3 @@ namespace :files do
   end
 
 end
-
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_release.rake b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_release.rake
index b313b2f53..9d3a59c53 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_release.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_release.rake
@@ -5,8 +5,8 @@ require 'ceedling/file_path_utils'
 desc "Build release target."
 task RELEASE_SYM => [:directories] do
   header = "Release build '#{File.basename(PROJECT_RELEASE_BUILD_TARGET)}'"
-  @ceedling[:streaminator].stdout_puts("\n\n#{header}\n#{'-' * header.length}")  
-  
+  @ceedling[:streaminator].stdout_puts("\n\n#{header}\n#{'-' * header.length}")
+
   begin
     @ceedling[:plugin_manager].pre_release
 
@@ -15,16 +15,15 @@ task RELEASE_SYM => [:directories] do
 
     @ceedling[:project_config_manager].process_release_config_change
     core_objects.concat( @ceedling[:release_invoker].setup_and_invoke_c_objects( COLLECTION_ALL_SOURCE ) )
-  
+
     # if assembler use isn't enabled, COLLECTION_ALL_ASSEMBLY is empty array & nothing happens
     core_objects.concat( @ceedling[:release_invoker].setup_and_invoke_asm_objects( COLLECTION_ALL_ASSEMBLY ) )
-  
+
     # if we're using libraries, we need to add those to our collection as well
     library_objects = (defined? LIBRARIES_RELEASE && !LIBRARIES_RELEASE.empty?) ? LIBRARIES_RELEASE.flatten.compact : []
     file( PROJECT_RELEASE_BUILD_TARGET => (core_objects + extra_objects + library_objects) )
     Rake::Task[PROJECT_RELEASE_BUILD_TARGET].invoke
   ensure
-    @ceedling[:plugin_manager].post_release  
+    @ceedling[:plugin_manager].post_release
   end
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_tests.rake b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_tests.rake
index 6c51ebcc9..5c1006b36 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/tasks_tests.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/tasks_tests.rake
@@ -59,4 +59,3 @@ namespace TEST_SYM do
   end
 
 end
-
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb b/test/unit-test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb
index 403d93e3e..a48edf9f9 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/test_invoker_helper.rb
@@ -19,14 +19,14 @@ class TestInvokerHelper
 
     yield( dependencies_list ) if block_given?
   end
-  
+
   def extract_sources(test)
     sources  = []
     includes = @test_includes_extractor.lookup_includes_list(test)
-    
+
     includes.each { |include| sources << @file_finder.find_compilation_input_file(include, :ignore) }
-    
+
     return sources.compact
   end
-  
+
 end
diff --git a/test/unit-test/vendor/ceedling/plugins/beep/lib/beep.rb b/test/unit-test/vendor/ceedling/plugins/beep/lib/beep.rb
index 6a6d01ab2..cbc5e3e38 100644
--- a/test/unit-test/vendor/ceedling/plugins/beep/lib/beep.rb
+++ b/test/unit-test/vendor/ceedling/plugins/beep/lib/beep.rb
@@ -37,4 +37,3 @@ class Beep < Plugin
     end
   end
 end
-
diff --git a/test/unit-test/vendor/ceedling/plugins/bullseye/README.md b/test/unit-test/vendor/ceedling/plugins/bullseye/README.md
index ab0b53b45..aad449204 100644
--- a/test/unit-test/vendor/ceedling/plugins/bullseye/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/bullseye/README.md
@@ -5,7 +5,7 @@ ceedling-bullseye
 
 Plugin for integrating Bullseye code coverage tool into Ceedling projects.
 This plugin requires a working license to Bullseye code coverage tools. The tools
-must be within the path or the path should be added to the environment in the 
+must be within the path or the path should be added to the environment in the
 `project.yml file`.
 
 ## Configuration
diff --git a/test/unit-test/vendor/ceedling/plugins/bullseye/assets/template.erb b/test/unit-test/vendor/ceedling/plugins/bullseye/assets/template.erb
index 504f85583..e1ef9874b 100644
--- a/test/unit-test/vendor/ceedling/plugins/bullseye/assets/template.erb
+++ b/test/unit-test/vendor/ceedling/plugins/bullseye/assets/template.erb
@@ -12,4 +12,3 @@ BRANCHES:  <%=sprintf(format_string, hash[:coverage][:branches])%>%
 % else
 BRANCHES:  none
 % end
-
diff --git a/test/unit-test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb b/test/unit-test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb
index ffa444ac7..3e7622006 100644
--- a/test/unit-test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb
+++ b/test/unit-test/vendor/ceedling/plugins/bullseye/lib/bullseye.rb
@@ -38,7 +38,7 @@ class Bullseye < Plugin
     @ceedling[:plugin_manager].pre_compile_execute(arg_hash)
 
     @ceedling[:streaminator].stdout_puts("Compiling #{File.basename(source)} with coverage...")
-    compile_command  = 
+    compile_command  =
       @ceedling[:tool_executor].build_command_line(
         TOOLS_BULLSEYE_COMPILER,
         @ceedling[:flaginator].flag_down( OPERATION_COMPILE_SYM, BULLSEYE_SYM, source ),
@@ -48,14 +48,14 @@ class Bullseye < Plugin
     coverage_command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_INSTRUMENTATION, [], compile_command[:line] )
 
     shell_result     = @ceedling[:tool_executor].exec( coverage_command[:line], coverage_command[:options] )
-    
+
     arg_hash[:shell_result] = shell_result
     @ceedling[:plugin_manager].post_compile_execute(arg_hash)
   end
 
   def post_test_fixture_execute(arg_hash)
     result_file = arg_hash[:result_file]
-  
+
     if ((result_file =~ /#{BULLSEYE_RESULTS_PATH}/) and (not @result_list.include?(result_file)))
       @result_list << arg_hash[:result_file]
     end
@@ -70,13 +70,13 @@ class Bullseye < Plugin
       :header => BULLSEYE_ROOT_NAME.upcase,
       :results => results
     }
-    
+
     @ceedling[:plugin_reportinator].run_test_results_report(hash) do
       message = ''
       message = 'Unit test failures.' if (results[:counts][:failed] > 0)
       message
     end
-    
+
     # coverage results
     return if (verify_coverage_file() == false)
     if (@ceedling[:task_invoker].invoked?(/^#{BULLSEYE_TASK_ROOT}(all|delta)/))
@@ -100,13 +100,13 @@ class Bullseye < Plugin
     }
 
     @ceedling[:plugin_reportinator].run_test_results_report(hash)
-    
+
     # coverage results
     command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_REPORT_COVSRC)
     shell_result = @ceedling[:tool_executor].exec(command[:line], command[:options])
     report_coverage_results_all(shell_result[:output])
   end
-  
+
   def enableBullseye(enable)
     if BULLSEYE_AUTO_LICENSE
       if (enable)
@@ -117,14 +117,14 @@ class Bullseye < Plugin
         @ceedling[:streaminator].stdout_puts("Reverting Bullseye to previous state")
       end
 
-      args.each do |arg| 
+      args.each do |arg|
         command = @ceedling[:tool_executor].build_command_line(TOOLS_BULLSEYE_BUILD_ENABLE_DISABLE, [], arg)
         shell_result = @ceedling[:tool_executor].exec(command[:line], command[:options])
       end
 
     end
   end
-  
+
   private ###################################
 
   def report_coverage_results_all(coverage)
@@ -139,7 +139,7 @@ class Bullseye < Plugin
     if (coverage =~ /^Total.*?=\s+([0-9]+)\%/)
       results[:coverage][:functions] = $1.to_i
     end
-    
+
     if (coverage =~ /^Total.*=\s+([0-9]+)\%\s*$/)
       results[:coverage][:branches] = $1.to_i
     end
@@ -177,10 +177,10 @@ class Bullseye < Plugin
       banner = @ceedling[:plugin_reportinator].generate_banner( "#{BULLSEYE_ROOT_NAME.upcase}: CODE COVERAGE SUMMARY" )
       @ceedling[:streaminator].stdout_puts "\n" + banner + "\nNo coverage file.\n\n"
     end
-    
+
     return exist
   end
-  
+
 end
 
 
@@ -188,7 +188,7 @@ end
 END {
   # cache our input configurations to use in comparison upon next execution
   if (@ceedling[:task_invoker].invoked?(/^#{BULLSEYE_TASK_ROOT}/))
-    @ceedling[:cacheinator].cache_test_config( @ceedling[:setupinator].config_hash ) 
+    @ceedling[:cacheinator].cache_test_config( @ceedling[:setupinator].config_hash )
     @ceedling[BULLSEYE_SYM].enableBullseye(false)
   end
 }
diff --git a/test/unit-test/vendor/ceedling/plugins/colour_report/README.md b/test/unit-test/vendor/ceedling/plugins/colour_report/README.md
index 4e0fcd45e..5f4ff77b1 100644
--- a/test/unit-test/vendor/ceedling/plugins/colour_report/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/colour_report/README.md
@@ -3,7 +3,7 @@ ceedling-colour-report
 
 ## Overview
 
-The colour_report replaces the normal ceedling "pretty" output with 
+The colour_report replaces the normal ceedling "pretty" output with
 a colorized variant, in order to make the results easier to read from
 a standard command line. This is very useful on developer machines, but
 can occasionally cause problems with parsing on CI servers.
diff --git a/test/unit-test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb b/test/unit-test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb
index 4bf8b5312..67e94f935 100644
--- a/test/unit-test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb
+++ b/test/unit-test/vendor/ceedling/plugins/command_hooks/lib/command_hooks.rb
@@ -89,4 +89,3 @@ class CommandHooks < Plugin
     end
   end
 end
-
diff --git a/test/unit-test/vendor/ceedling/plugins/compile_commands_json/README.md b/test/unit-test/vendor/ceedling/plugins/compile_commands_json/README.md
index ea80b7397..7e3846e56 100644
--- a/test/unit-test/vendor/ceedling/plugins/compile_commands_json/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/compile_commands_json/README.md
@@ -9,7 +9,7 @@ In June of 2016, Microsoft with Red Hat and Codenvy got together to create a sta
 
 For C and C++ projects, many people use the `clangd` backend. So that it can do things like "go to definition", `clangd` needs to know how to build the project so that it can figure out all the pieces to the puzzle. There are manual tools such as `bear` which can be run with `gcc` or `clang` to extract this information it has a big limitation in that if run with `ceedling release` you won't get any auto completion for Unity and you'll also get error messages reported by your IDE because of what it perceives as missing headers. If you do the same with `ceedling test` now you get Unity but you might miss things that are only seen in the release build.
 
-This plugin resolves that issue. As it is run by Ceedling, it has access to all the build information it needs to create the perfect `compile_commands.json`. Once enabled, this plugin will generate that file and place it in `./build/artifacts/compile_commands.json`. `clangd` will search your project for this file, but it is easier to symlink it into the root directory (for example `ln -s ./build/artifacts/compile_commands.json`. 
+This plugin resolves that issue. As it is run by Ceedling, it has access to all the build information it needs to create the perfect `compile_commands.json`. Once enabled, this plugin will generate that file and place it in `./build/artifacts/compile_commands.json`. `clangd` will search your project for this file, but it is easier to symlink it into the root directory (for example `ln -s ./build/artifacts/compile_commands.json`.
 
 For more information on LSP and to find out if your editor supports it, check out https://langserver.org/
 
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/Rakefile b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/Rakefile
index bc5594110..2fd9f859f 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/Rakefile
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/Rakefile
@@ -16,4 +16,4 @@ task :integration_test do
     end
 end
 
-task :default => [:spec, :integration_test]
\ No newline at end of file
+task :default => [:spec, :integration_test]
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml
index 6bda22291..00e395d0c 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml
@@ -28,7 +28,7 @@
   :source:
     - src/**
   :support:
-      
+
 :defines:
   # in order to add common defines:
   #  1) remove the trailing [] from the :common: section
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c
index 2f03449b0..797d46878 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/src/display.c
@@ -4,4 +4,4 @@
 void display_turnOffStatusLed(void)
 {
     printf("Display: Status LED off");
-}
\ No newline at end of file
+}
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb
index 9dc03a653..d439a8d7f 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fff_mock_generator.rb
@@ -90,7 +90,7 @@ class FffMockGenerator
     # In the init function, reset the FFF globals. These are used for things
     # like the call history.
     output.puts "    FFF_RESET_HISTORY();"
-    
+
     # Also, reset all of the fakes.
     if parsed_header[:functions]
       parsed_header[:functions].each do |function|
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb
index e6ac11dd0..09d317551 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_header_generator_spec.rb
@@ -254,7 +254,7 @@ describe "FffMockGenerator.create_mock_header" do
       )
     end
   end
-  
+
   context "when there is a function that returns a const int" do
     let(:mock_header){
       parsed_header = {}
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb
index 364f8521e..7b7f04f58 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/fff_mock_source_generator_spec.rb
@@ -146,4 +146,4 @@ describe "FffMockGenerator.create_mock_source" do
       )
     end
   end
-end
\ No newline at end of file
+end
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb
index cda278440..3b6fa7120 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/spec/header_generator.rb
@@ -48,4 +48,4 @@ def create_cmock_style_parsed_header(functions, typedefs = nil)
     end
   end
   parsed_header
-end
\ No newline at end of file
+end
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h
index de3db44aa..970ecbb35 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/src/fff_unity_helper.h
@@ -30,4 +30,4 @@
         fff.call_history[order_],                                           \
         "Function " #function_ " not called in order " #order_ )
 
-#endif
\ No newline at end of file
+#endif
diff --git a/test/unit-test/vendor/ceedling/plugins/gcov/assets/template.erb b/test/unit-test/vendor/ceedling/plugins/gcov/assets/template.erb
index 5e5a1742b..266750497 100644
--- a/test/unit-test/vendor/ceedling/plugins/gcov/assets/template.erb
+++ b/test/unit-test/vendor/ceedling/plugins/gcov/assets/template.erb
@@ -12,4 +12,3 @@ BRANCHES:  <%=sprintf(format_string, hash[:coverage][:branches])%>%
 % else
 BRANCHES:  none
 % end
-
diff --git a/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb b/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb
index 92617fba5..10a0a6c5c 100644
--- a/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb
+++ b/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportinator_helper.rb
@@ -5,7 +5,7 @@ class ReportinatorHelper
     def print_shell_result(shell_result)
       if !(shell_result.nil?)
         puts "Done in %.3f seconds." % shell_result[:time]
-  
+
         if !(shell_result[:output].nil?) && (shell_result[:output].length > 0)
           puts shell_result[:output]
         end
diff --git a/test/unit-test/vendor/ceedling/plugins/json_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/json_tests_report/README.md
index 8e5a1e571..b383492e2 100644
--- a/test/unit-test/vendor/ceedling/plugins/json_tests_report/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/json_tests_report/README.md
@@ -3,8 +3,8 @@ json_tests_report
 
 ## Overview
 
-The json_tests_report plugin creates a JSON file of test results, which is 
-handy for Continuous Integration build servers or as input into other 
+The json_tests_report plugin creates a JSON file of test results, which is
+handy for Continuous Integration build servers or as input into other
 reporting tools. The JSON file is output to the appropriate
 `<build_root>/artifacts/` directory (e.g. `artifacts/test/` for test tasks,
 `artifacts/gcov/` for gcov, or `artifacts/bullseye/` for bullseye runs).
diff --git a/test/unit-test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb b/test/unit-test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb
index e7023db7b..f09339ee2 100644
--- a/test/unit-test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb
+++ b/test/unit-test/vendor/ceedling/plugins/json_tests_report/lib/json_tests_report.rb
@@ -33,7 +33,7 @@ class JsonTestsReport < Plugin
           "IgnoredTests" => write_tests(results[:ignores]),
           "Summary" => write_statistics(results[:counts])
         }
-        
+
         f << JSON.pretty_generate(json)
       end
     end
@@ -62,7 +62,7 @@ class JsonTestsReport < Plugin
     results.each do |result|
       result[:collection].each do |item|
         @test_counter += 1
-        retval << { 
+        retval << {
           "file" => File.join(result[:source][:path], result[:source][:file]),
           "test" => item[:test]
         }
diff --git a/test/unit-test/vendor/ceedling/plugins/module_generator/README.md b/test/unit-test/vendor/ceedling/plugins/module_generator/README.md
index a3c2c7ad9..61cf45bd6 100644
--- a/test/unit-test/vendor/ceedling/plugins/module_generator/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/module_generator/README.md
@@ -96,7 +96,7 @@ put that corporate copyright notice (or maybe a copyleft notice, if that's your
 ### Test Defines
 
 You can specify the "#ifdef TEST" at the top of the test files with a custom define.
-This example will put a "#ifdef CEEDLING_TEST" at the top of the test files.  
+This example will put a "#ifdef CEEDLING_TEST" at the top of the test files.
 
 ```
 :module_generator:
@@ -115,5 +115,3 @@ Your options are as follows:
   - `:camel` - camelFilesAreSimilarButStartLow
   - `:snake` - snake_case_is_all_lower_and_uses_underscores
   - `:caps`  - CAPS_FEELS_LIKE_YOU_ARE_SCREAMING
-
-
diff --git a/test/unit-test/vendor/ceedling/plugins/module_generator/config/module_generator.yml b/test/unit-test/vendor/ceedling/plugins/module_generator/config/module_generator.yml
index cdb2da2eb..b90afd0ff 100644
--- a/test/unit-test/vendor/ceedling/plugins/module_generator/config/module_generator.yml
+++ b/test/unit-test/vendor/ceedling/plugins/module_generator/config/module_generator.yml
@@ -1,4 +1,4 @@
 :module_generator:
   :project_root: ./
   :source_root: src/
-  :test_root: test/
\ No newline at end of file
+  :test_root: test/
diff --git a/test/unit-test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md
index 9ab60847e..e95106ed1 100644
--- a/test/unit-test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/stdout_gtestlike_tests_report/README.md
@@ -3,8 +3,8 @@ ceedling-stdout-gtestlike-tests-report
 
 ## Overview
 
-The stdout_gtestlike_tests_report replaces the normal ceedling "pretty" output with 
-a variant that resembles the output of gtest. This is most helpful when trying to 
+The stdout_gtestlike_tests_report replaces the normal ceedling "pretty" output with
+a variant that resembles the output of gtest. This is most helpful when trying to
 integrate into an IDE or CI that is meant to work with google test.
 
 ## Setup
diff --git a/test/unit-test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md
index ed6c65582..da04d1c14 100644
--- a/test/unit-test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/stdout_ide_tests_report/README.md
@@ -3,7 +3,7 @@ ceedling-stdout-ide-tests-report
 
 ## Overview
 
-The stdout_ide_tests_report replaces the normal ceedling "pretty" output with 
+The stdout_ide_tests_report replaces the normal ceedling "pretty" output with
 a simplified variant intended to be easily parseable.
 
 ## Setup
diff --git a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md
index 7e1be2382..358aa93ab 100644
--- a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/README.md
@@ -5,7 +5,7 @@ ceedling-pretty-tests-report
 
 The stdout_pretty_tests_report is the default output of ceedling. Instead of
 showing most of the raw output of CMock, Ceedling, etc., it shows a simplified
-view. It also creates a nice summary at the end of execution which groups the 
+view. It also creates a nice summary at the end of execution which groups the
 results into ignored and failed tests.
 
 ## Setup
diff --git a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb
index 52b29f7f0..1c025bf1b 100644
--- a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb
+++ b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/assets/template.erb
@@ -56,4 +56,3 @@ IGNORED: <%=sprintf(format_string, ignored)%>
 
 No tests executed.
 % end
-
diff --git a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb
index 018388fc1..fd9589183 100644
--- a/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb
+++ b/test/unit-test/vendor/ceedling/plugins/stdout_pretty_tests_report/lib/stdout_pretty_tests_report.rb
@@ -2,20 +2,20 @@ require 'ceedling/plugin'
 require 'ceedling/defaults'
 
 class StdoutPrettyTestsReport < Plugin
-  
+
   def setup
     @result_list = []
     @plugin_root = File.expand_path(File.join(File.dirname(__FILE__), '..'))
     template = @ceedling[:file_wrapper].read(File.join(@plugin_root, 'assets/template.erb'))
     @ceedling[:plugin_reportinator].register_test_results_template( template )
   end
-  
+
   def post_test_fixture_execute(arg_hash)
     return if not (arg_hash[:context] == TEST_SYM)
-  
+
     @result_list << arg_hash[:result_file]
   end
-  
+
   def post_build
     return if not (@ceedling[:task_invoker].test_invoked?)
 
diff --git a/test/unit-test/vendor/ceedling/plugins/subprojects/README.md b/test/unit-test/vendor/ceedling/plugins/subprojects/README.md
index e51a4e60e..ef4caa57b 100644
--- a/test/unit-test/vendor/ceedling/plugins/subprojects/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/subprojects/README.md
@@ -1,9 +1,9 @@
 ceedling-subprojects
 ====================
 
-Plugin for supporting subprojects that are built as static libraries. It continues to support  
-dependency tracking, without getting confused between your main project files and your   
-subproject files. It accepts different compiler flags and linker flags, allowing you to   
+Plugin for supporting subprojects that are built as static libraries. It continues to support
+dependency tracking, without getting confused between your main project files and your
+subproject files. It accepts different compiler flags and linker flags, allowing you to
 optimize for your situation.
 
 First, you're going to want to add the extension to your list of known extensions:
@@ -13,12 +13,12 @@ First, you're going to want to add the extension to your list of known extension
   :subprojects: '.a'
 ```
 
-Define a new section called :subprojects. There, you can list as many subprojects  
-as you may need under the :paths key. For each, you specify a unique place to build  
+Define a new section called :subprojects. There, you can list as many subprojects
+as you may need under the :paths key. For each, you specify a unique place to build
 and a unique name.
 
 ```
-:subprojects:  
+:subprojects:
   :paths:
    - :name: libprojectA
      :source:
@@ -27,7 +27,7 @@ and a unique name.
      :include:
        - ./subprojectA/include/dir
      :build_root: ./subprojectA/build/dir
-     :defines: 
+     :defines:
        - DEFINE_JUST_FOR_THIS_FILE
        - AND_ANOTHER
    - :name: libprojectB
diff --git a/test/unit-test/vendor/ceedling/plugins/subprojects/subprojects.rake b/test/unit-test/vendor/ceedling/plugins/subprojects/subprojects.rake
index 0025c3ecd..f80c812f3 100644
--- a/test/unit-test/vendor/ceedling/plugins/subprojects/subprojects.rake
+++ b/test/unit-test/vendor/ceedling/plugins/subprojects/subprojects.rake
@@ -73,6 +73,5 @@ SUBPROJECTS_PATHS.each do |subproj|
   task :directories => subproj_directories.clone
 
   # Finally, add the static library to our RELEASE build dependency list
-  task RELEASE_SYM => ["#{subproj_build_root}/#{subproj_name}#{EXTENSION_SUBPROJECTS}"] 
+  task RELEASE_SYM => ["#{subproj_build_root}/#{subproj_name}#{EXTENSION_SUBPROJECTS}"]
 end
-
diff --git a/test/unit-test/vendor/ceedling/plugins/teamcity_tests_report/README.md b/test/unit-test/vendor/ceedling/plugins/teamcity_tests_report/README.md
index 9fcda7d5b..2467ebe99 100644
--- a/test/unit-test/vendor/ceedling/plugins/teamcity_tests_report/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/teamcity_tests_report/README.md
@@ -3,7 +3,7 @@ ceedling-teamcity-tests-report
 
 ## Overview
 
-The teamcity_tests_report replaces the normal ceedling "pretty" output with 
+The teamcity_tests_report replaces the normal ceedling "pretty" output with
 a version that has results tagged to be consumed with the teamcity CI server.
 
 ## Setup
diff --git a/test/unit-test/vendor/ceedling/vendor/c_exception/lib/CException.c b/test/unit-test/vendor/ceedling/vendor/c_exception/lib/CException.c
index fdff8f475..24b3b09e8 100644
--- a/test/unit-test/vendor/ceedling/vendor/c_exception/lib/CException.c
+++ b/test/unit-test/vendor/ceedling/vendor/c_exception/lib/CException.c
@@ -43,4 +43,3 @@ void Throw(CEXCEPTION_T ExceptionID)
     }                                                                   <- finish off that local scope we created to have our own variables
     if (CExceptionFrames[CEXCEPTION_GET_ID].Exception != CEXCEPTION_NONE)  <- start the actual 'catch' processing if we have an exception id saved away
  */
-
diff --git a/test/unit-test/vendor/ceedling/vendor/c_exception/lib/meson.build b/test/unit-test/vendor/ceedling/vendor/c_exception/lib/meson.build
index 2770122af..9694e51c7 100644
--- a/test/unit-test/vendor/ceedling/vendor/c_exception/lib/meson.build
+++ b/test/unit-test/vendor/ceedling/vendor/c_exception/lib/meson.build
@@ -6,6 +6,6 @@
 #
 cexception_dir = include_directories('.')
 
-cexception_lib = static_library(meson.project_name(), 
+cexception_lib = static_library(meson.project_name(),
     files('CException.c'),
     include_directories : cexception_dir)
diff --git a/test/unit-test/vendor/ceedling/vendor/cmock/src/cmock.c b/test/unit-test/vendor/ceedling/vendor/cmock/src/cmock.c
index 88f2c2b25..d8bdb1369 100644
--- a/test/unit-test/vendor/ceedling/vendor/cmock/src/cmock.c
+++ b/test/unit-test/vendor/ceedling/vendor/cmock/src/cmock.c
@@ -213,4 +213,3 @@ void CMock_Guts_MemFreeFinal(void)
   }
 #endif
 }
-
diff --git a/test/unit-test/vendor/ceedling/vendor/cmock/src/meson.build b/test/unit-test/vendor/ceedling/vendor/cmock/src/meson.build
index c03c4e5bb..b3145c02e 100644
--- a/test/unit-test/vendor/ceedling/vendor/cmock/src/meson.build
+++ b/test/unit-test/vendor/ceedling/vendor/cmock/src/meson.build
@@ -6,7 +6,7 @@
 #
 cmock_dir = include_directories('.')
 
-cmock_lib = static_library(meson.project_name(), 
+cmock_lib = static_library(meson.project_name(),
     files('cmock.c'),
     dependencies: [unity_dep],
     include_directories: cmock_dir)
diff --git a/test/unit-test/vendor/ceedling/vendor/diy/lib/diy.rb b/test/unit-test/vendor/ceedling/vendor/diy/lib/diy.rb
index 581afc7e6..cbeb8267a 100644
--- a/test/unit-test/vendor/ceedling/vendor/diy/lib/diy.rb
+++ b/test/unit-test/vendor/ceedling/vendor/diy/lib/diy.rb
@@ -18,8 +18,8 @@ module DIY #:nodoc:#
       raise "Nil context hash" unless context_hash
       raise "Need a hash" unless context_hash.kind_of?(Hash)
       [ "[]", "keys" ].each do |mname|
-        unless extra_inputs.respond_to?(mname) 
-          raise "Extra inputs must respond to hash-like [] operator and methods #keys and #each" 
+        unless extra_inputs.respond_to?(mname)
+          raise "Extra inputs must respond to hash-like [] operator and methods #keys and #each"
         end
       end
 
@@ -37,7 +37,7 @@ module DIY #:nodoc:#
       @cache = {}
       @cache['this_context'] = self
     end
-   
+
 
     # Convenience: create a new DIY::Context by loading from a String (or open file handle.)
     def self.from_yaml(io_or_string, extra_inputs={})
@@ -51,7 +51,7 @@ module DIY #:nodoc:#
       self.from_yaml(File.read(fname), extra_inputs)
     end
 
-    # Return a reference to the object named.  If necessary, the object will 
+    # Return a reference to the object named.  If necessary, the object will
     # be instantiated on first use.  If the object is non-singleton, a new
     # object will be produced each time.
     def get_object(obj_name)
@@ -77,7 +77,7 @@ module DIY #:nodoc:#
     end
     alias :[] :get_object
 
-    # Inject a named object into the Context.  This must be done before the Context has instantiated the 
+    # Inject a named object into the Context.  This must be done before the Context has instantiated the
     # object in question.
     def set_object(obj_name,obj)
       key = obj_name.to_s
@@ -108,9 +108,9 @@ module DIY #:nodoc:#
       @defs.keys.member?(key) or extra_inputs_has(key)
     end
 
-    # Every top level object in the Context is instantiated.  This is especially useful for 
+    # Every top level object in the Context is instantiated.  This is especially useful for
     # systems that have "floating observers"... objects that are never directly accessed, who
-    # would thus never be instantiated by coincedence.  This does not build any subcontexts 
+    # would thus never be instantiated by coincedence.  This does not build any subcontexts
     # that may exist.
     def build_everything
       @defs.keys.each { |k| self[k] }
@@ -131,7 +131,7 @@ module DIY #:nodoc:#
         # we modify the info hash below so it's important to have a new
         # instance to play with
         info = info.dup if info
-        
+
         # see if we are building a factory
         if info and info.has_key?('builds')
           unless info.has_key?('auto_require')
@@ -150,21 +150,21 @@ module DIY #:nodoc:#
 
         name = name.to_s
         case name
-        when /^\+/ 
+        when /^\+/
           # subcontext
           @sub_context_defs[name.gsub(/^\+/,'')] = info
-          
+
         when /^using_namespace/
           # namespace: use a module(s) prefix for the classname of contained object defs
           # NOTE: namespacing is NOT scope... it's just a convenient way to setup class names for a group of objects.
           get_defs_from info, parse_namespace(name)
         when /^method\s/
           key_name = name.gsub(/^method\s/, "")
-          @defs[key_name] = MethodDef.new(:name => key_name, 
-                                      :object => info['object'], 
+          @defs[key_name] = MethodDef.new(:name => key_name,
+                                      :object => info['object'],
                                       :method => info['method'],
                                       :attach => info['attach'])
-        else 
+        else
           # Normal object def
           info ||= {}
           if extra_inputs_has(name)
@@ -173,14 +173,14 @@ module DIY #:nodoc:#
           unless info.has_key?('auto_require')
             info['auto_require'] = self.class.auto_require
           end
-          if namespace 
+          if namespace
             if info['class']
               info['class'] = namespace.build_classname(info['class'])
             else
               info['class'] = namespace.build_classname(name)
             end
           end
-            
+
           @defs[name] = ObjectDef.new(:name => name, :info => info)
 
         end
@@ -191,10 +191,10 @@ module DIY #:nodoc:#
       method_definition = @defs[key]
       object = get_object(method_definition.object)
       method = object.method(method_definition.method)
-      
+
       unless method_definition.attach.nil?
         instance_var_name = "@__diy_#{method_definition.object}"
-        
+
         method_definition.attach.each do |object_key|
           get_object(object_key).instance_eval do
             instance_variable_set(instance_var_name, object)
@@ -202,14 +202,14 @@ module DIY #:nodoc:#
               #{instance_var_name}.#{method_definition.method}(*args)
             end|
           end
-        end      
+        end
       end
-      
+
       return method
     rescue Exception => oops
       build_and_raise_construction_error(key, oops)
     end
-    
+
     def construct_object(key)
       # Find the object definition
       obj_def = @defs[key]
@@ -242,13 +242,13 @@ module DIY #:nodoc:#
     rescue Exception => oops
       build_and_raise_construction_error(key, oops)
     end
-    
+
     def build_and_raise_construction_error(key, oops)
       cerr = ConstructionError.new(key,oops)
       cerr.set_backtrace(oops.backtrace)
       raise cerr
     end
-      
+
     def get_class_for_name_with_module_delimeters(class_name)
       class_name.split(/::/).inject(Object) do |mod,const_name| mod.const_get(const_name) end
     end
@@ -264,7 +264,7 @@ module DIY #:nodoc:#
       Namespace.new(str)
     end
   end
-  
+
   class Namespace #:nodoc:#
     def initialize(str)
       # 'using_namespace Animal Reptile'
@@ -292,15 +292,15 @@ module DIY #:nodoc:#
       @name = obj_name
     end
   end
-  
+
   class MethodDef #:nodoc:
     attr_accessor :name, :object, :method, :attach
-    
+
     def initialize(opts)
       @name, @object, @method, @attach = opts[:name], opts[:object], opts[:method], opts[:attach]
     end
   end
-  
+
   class ObjectDef #:nodoc:
     attr_accessor :name, :class_name, :library, :components
     def initialize(opts)
@@ -330,7 +330,7 @@ module DIY #:nodoc:#
 
       # Use Class Directly
       @use_class_directly = info.delete 'use_class_directly'
-      
+
       # Auto-compose
       compose = info.delete 'compose'
       if compose
@@ -380,7 +380,7 @@ module DIY #:nodoc:#
       object_name = object_name
       cause = cause
       m = "Failed to construct '#{object_name}'"
-      if cause 
+      if cause
         m << "\n  ...caused by:\n  >>> #{cause}"
       end
       super m
@@ -388,11 +388,11 @@ module DIY #:nodoc:#
   end
 
   class NamespaceError < RuntimeError #:nodoc:#
-  end 
+  end
 
   module Infl #:nodoc:#
     # Ganked this from Inflector:
-    def self.camelize(lower_case_and_underscored_word) 
+    def self.camelize(lower_case_and_underscored_word)
       lower_case_and_underscored_word.to_s.gsub(/\/(.?)/) { "::" + $1.upcase }.gsub(/(^|_)(.)/) { $2.upcase }
     end
     # Ganked this from Inflector:
diff --git a/test/unit-test/vendor/ceedling/vendor/diy/lib/diy/factory.rb b/test/unit-test/vendor/ceedling/vendor/diy/lib/diy/factory.rb
index d2566c5d1..8f00e5e45 100644
--- a/test/unit-test/vendor/ceedling/vendor/diy/lib/diy/factory.rb
+++ b/test/unit-test/vendor/ceedling/vendor/diy/lib/diy/factory.rb
@@ -1,7 +1,7 @@
 module DIY #:nodoc:#
   class FactoryDef #:nodoc:
     attr_accessor :name, :target, :class_name, :library
-    
+
     def initialize(opts)
       @name, @target, @library, @auto_require =
         opts[:name], opts[:target], opts[:library], opts[:auto_require]
@@ -10,7 +10,7 @@ module DIY #:nodoc:#
 			@library ||= Infl.underscore(@class_name) if @auto_require
     end
   end
-  
+
 	class Context
     def construct_factory(key)
       factory_def = @defs[key]
@@ -33,4 +33,3 @@ module DIY #:nodoc:#
     end
   end
 end
-
diff --git a/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_config.yml b/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_config.yml
index 4a5e47424..c7679aefc 100644
--- a/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_config.yml
+++ b/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_config.yml
@@ -18,7 +18,7 @@
       - Defs.h
       - Board.h
       - Exception.h
-  :boilerplates: 
+  :boilerplates:
     #these are inserted at the top of generated files.
     #just comment out or remove if not desired.
     #use %1$s where you would like the file name to appear (path/extension not included)
diff --git a/test/unit-test/vendor/ceedling/vendor/unity/src/meson.build b/test/unit-test/vendor/ceedling/vendor/unity/src/meson.build
index 1c7b426ff..5acd51a9b 100644
--- a/test/unit-test/vendor/ceedling/vendor/unity/src/meson.build
+++ b/test/unit-test/vendor/ceedling/vendor/unity/src/meson.build
@@ -6,6 +6,6 @@
 #
 unity_dir = include_directories('.')
 
-unity_lib = static_library(meson.project_name(), 
+unity_lib = static_library(meson.project_name(),
     files('unity.c'),
     include_directories: unity_dir)
diff --git a/tools/build_board.py b/tools/build_board.py
index 4593dafa5..13376d126 100644
--- a/tools/build_board.py
+++ b/tools/build_board.py
@@ -56,7 +56,7 @@ if __name__ == '__main__':
             result = pool.starmap(build_utils.build_example, pool_args)
             # sum all element of same index (column sum)
             result = list(map(sum, list(zip(*result))))
-            
+
             # add to total result
             total_result = list(map(lambda x, y: x + y, total_result, result))
 
diff --git a/tools/build_utils.py b/tools/build_utils.py
index de9052d2d..d0ef52717 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -124,4 +124,4 @@ def build_size(make_cmd):
             sram_size = int(size_list[1]) + int(size_list[2])
             return (flash_size, sram_size)
 
-    return (0, 0)
\ No newline at end of file
+    return (0, 0)
diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index ba54fe057..d243aab0a 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -141,5 +141,5 @@
             <path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
 		</group>
     </files>
-    
+
 </iarProjectConnection>
diff --git a/tools/mksunxi.py b/tools/mksunxi.py
index 04786f429..fd8557cfc 100644
--- a/tools/mksunxi.py
+++ b/tools/mksunxi.py
@@ -45,4 +45,4 @@ if __name__ == "__main__":
     if len(sys.argv) != 3:
         print("Usage: mksunxi.py input.bin output.bin")
         exit(1)
-    exit(process_file(sys.argv[1], sys.argv[2]))
\ No newline at end of file
+    exit(process_file(sys.argv[1], sys.argv[2]))
diff --git a/tools/pcapng_to_corpus.py b/tools/pcapng_to_corpus.py
index 78b1f77a2..9c31365eb 100755
--- a/tools/pcapng_to_corpus.py
+++ b/tools/pcapng_to_corpus.py
@@ -16,7 +16,7 @@ def extract_packets(pcap_file):
 
 def build_corpus_zip(zip_file_output, packets):
     """Builds a zip file with a file per packet
-    
+
     The structure of this zip corpus is a simple content addressable storage
     i.e. seed_file_name == sha256_digest(packet).
     """
@@ -25,7 +25,7 @@ def build_corpus_zip(zip_file_output, packets):
             hash = hashlib.sha256(packet).hexdigest()
             if hash not in out.namelist():
                 out.writestr(hash, packet)
-    
+
 
 def main(pcap_file, output_zip_file):
     packets = extract_packets(pcap_file)
@@ -35,12 +35,10 @@ if __name__ == "__main__":
     parser = argparse.ArgumentParser(
         prog = "pcapng_to_corpus.py",
         description="""Converts a wireshark capture to a zip of binary packet
-                    files suitable for an oss-fuzz corpus. In the case the 
-                    zip corpus already exists, this script will modify 
+                    files suitable for an oss-fuzz corpus. In the case the
+                    zip corpus already exists, this script will modify
                     the zip file in place adding seed entries.""")
     parser.add_argument('pcapng_capture_file')
     parser.add_argument('oss_fuzz_corpus_zip')
     args = parser.parse_args()
     main(args.pcapng_capture_file, args.oss_fuzz_corpus_zip)
-    
-    
diff --git a/tools/usb_drivers/tinyusb_win_usbser.inf b/tools/usb_drivers/tinyusb_win_usbser.inf
index e7f7a9b22..659f048ae 100644
--- a/tools/usb_drivers/tinyusb_win_usbser.inf
+++ b/tools/usb_drivers/tinyusb_win_usbser.inf
@@ -105,4 +105,4 @@ DRIVERFILENAME ="usbser"
 MFGNAME="tinyusb.org"
 INSTDISK="tinyusb CDC Driver"
 DESCRIPTION="tinyusb Serial"
-SERVICE="USB RS-232 Emulation Driver"
\ No newline at end of file
+SERVICE="USB RS-232 Emulation Driver"

From 2e5f649fd3ba3e0a17bb6007f773461bdc0e82fb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 16:57:30 +0700
Subject: [PATCH 1559/2085] fix run unit test with pre-commit

---
 .github/workflows/pre-commit.yml | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index 6deee872f..86c106151 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -26,19 +26,18 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
+    - name: Get Dependencies
+      run: |
+        gem install ceedling
+        #cd test/unit-test
+        #ceedling test:all
+
     - name: Run pre-commit
       uses: pre-commit/action@v3.0.0
 
     - name: Run codespell
       uses: codespell-project/actions-codespell@master
 
-    - name: Run Unit Tests
-      run: |
-        # Install Ceedling
-        gem install ceedling
-        cd test/unit-test
-        ceedling test:all
-
     - name: Build Fuzzer
       run: |
         export CC=clang

From a4b17483b9e7cb5f73ec1b64cdd41987743ef4da Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 17:01:56 +0700
Subject: [PATCH 1560/2085] fix ci build with fomu

---
 examples/rules.mk | 2 --
 tools/get_deps.py | 3 ---
 2 files changed, 5 deletions(-)

diff --git a/examples/rules.mk b/examples/rules.mk
index 56ad89fd0..59cf4fd1f 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -192,9 +192,7 @@ endif
 # get depenecies
 .PHONY: get-deps
 get-deps:
-  ifdef DEPS_SUBMODULES
 	$(PYTHON) $(TOP)/tools/get_deps.py $(DEPS_SUBMODULES)
-  endif
 
 .PHONY: size
 size: $(BUILD)/$(PROJECT).elf
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 24e5f383a..574e5d089 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -104,9 +104,6 @@ def get_a_dep(d):
 
 
 if __name__ == "__main__":
-    if len(sys.argv) <= 1:
-        sys.exit(1)
-
     status = 0
     deps = list(deps_mandatory.keys()) + sys.argv[1:]
     with Pool() as pool:

From 0c174c17ad98249f5862440b9f4ff25e10fc0824 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 17:04:11 +0700
Subject: [PATCH 1561/2085] fix ci with building fuzz

---
 test/fuzz/rules.mk | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/test/fuzz/rules.mk b/test/fuzz/rules.mk
index 825abddc5..ee91c706d 100644
--- a/test/fuzz/rules.mk
+++ b/test/fuzz/rules.mk
@@ -142,9 +142,7 @@ endif
 # get depenecies
 .PHONY: get-deps
 get-deps:
-  ifdef DEPS_SUBMODULES
-	git -C $(TOP) submodule update --init $(DEPS_SUBMODULES)
-  endif
+	$(PYTHON) $(TOP)/tools/get_deps.py $(DEPS_SUBMODULES)
 
 size: $(BUILD)/$(PROJECT)
 	-@echo ''

From f14b4ba30a1800a1ed3ffa4977d182b5c1e1f5a5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 17:20:01 +0700
Subject: [PATCH 1562/2085] use codespell as pre-commit

---
 .pre-commit-config.yaml | 41 ++++++++++++++++++++---------------------
 1 file changed, 20 insertions(+), 21 deletions(-)

diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index 976f04e63..7d7c1a3ce 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -3,26 +3,25 @@
 # SPDX-License-Identifier: Unlicense
 
 repos:
--   repo: https://github.com/pre-commit/pre-commit-hooks
-    rev: v4.4.0
-    hooks:
-    - id: check-yaml
-    - id: trailing-whitespace
-    - id: end-of-file-fixer
-    - id: forbid-submodules
+- repo: https://github.com/pre-commit/pre-commit-hooks
+  rev: v4.4.0
+  hooks:
+  - id: check-yaml
+  - id: trailing-whitespace
+  - id: end-of-file-fixer
+  - id: forbid-submodules
 
--   repo: local
-    hooks:
-    #-   id: codespell
-    #    name: codespell
-    #    entry: codespell
-    #    types_or: [c, header]
-    #    language: system
+- repo: https://github.com/codespell-project/codespell
+  rev: v2.2.4
+  hooks:
+  - id: codespell
 
-    -   id: unit-test
-        name: unit-test
-        files: ^(src/|test/unit-test/)
-        entry: sh -c "cd test/unit-test && ceedling test:all"
-        pass_filenames: false
-        types_or: [c, header]
-        language: system
+- repo: local
+  hooks:
+  - id: unit-test
+    name: unit-test
+    files: ^(src/|test/unit-test/)
+    entry: sh -c "cd test/unit-test && ceedling test:all"
+    pass_filenames: false
+    types_or: [c, header]
+    language: system

From 25d802532c27f11a6445f71ef44af98a2a780864 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 17:27:34 +0700
Subject: [PATCH 1563/2085] fix spelling

---
 .codespell/ignore-words.txt                            |  2 ++
 .codespellrc                                           |  2 +-
 .pre-commit-config.yaml                                |  2 ++
 .../da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h | 10 +++++-----
 hw/mcu/dialog/da1469x/src/system_da1469x.c             |  2 +-
 .../nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h     |  2 +-
 hw/mcu/sony/cxd56/tools/flash_writer.py                |  6 +++---
 hw/mcu/sony/cxd56/tools/xmodem.py                      |  4 ++--
 test/unit-test/vendor/ceedling/bin/ceedling            |  2 +-
 test/unit-test/vendor/ceedling/lib/ceedling.rb         |  2 +-
 .../lib/ceedling/preprocessinator_includes_handler.rb  |  2 +-
 .../vendor/ceedling/lib/ceedling/rules_preprocess.rake |  2 +-
 .../vendor/ceedling/lib/ceedling/system_utils.rb       |  2 +-
 .../ceedling/plugins/dependencies/dependencies.rake    |  2 +-
 .../ceedling/plugins/fake_function_framework/README.md |  2 +-
 .../examples/fff_example/project.yml                   |  2 +-
 .../examples/fff_example/test/test_event_processor.c   |  2 +-
 .../lib/fake_function_framework.rb                     |  2 +-
 .../plugins/gcov/lib/reportgenerator_reportinator.rb   |  2 +-
 .../vendor/ceedling/plugins/module_generator/README.md |  2 +-
 .../ceedling/vendor/cmock/lib/cmock_header_parser.rb   |  4 ++--
 .../ceedling/vendor/unity/auto/generate_test_runner.rb |  2 +-
 .../unit-test/vendor/ceedling/vendor/unity/src/unity.c |  2 +-
 23 files changed, 33 insertions(+), 29 deletions(-)

diff --git a/.codespell/ignore-words.txt b/.codespell/ignore-words.txt
index e1ad88a07..fc14fe417 100644
--- a/.codespell/ignore-words.txt
+++ b/.codespell/ignore-words.txt
@@ -7,3 +7,5 @@ dout
 mot
 te
 attch
+endianess
+pris
diff --git a/.codespellrc b/.codespellrc
index 8c32ed706..dc089903c 100644
--- a/.codespellrc
+++ b/.codespellrc
@@ -7,4 +7,4 @@ exclude-file = .codespell/exclude-file.txt
 check-filenames =
 check-hidden =
 count =
-skip = .cproject,./.git,./hw/mcu,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./test/unit-test/vendor,./tests_obsolete,./tools/uf2
+skip = *.rb,.cproject,.git,./lib,./examples/*/*/_build,./examples/*/*/ses,./examples/*/*/ozone,./hw/mcu,./tests_obsolete
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index 7d7c1a3ce..d37c27d40 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -15,6 +15,8 @@ repos:
   rev: v2.2.4
   hooks:
   - id: codespell
+    args: [-w]
+    exclude: ^lib/
 
 - repo: local
   hooks:
diff --git a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h
index fa2ca5d94..faf8b852a 100644
--- a/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h
+++ b/hw/mcu/dialog/da1469x/SDK_10.0.8.105/sdk/bsp/include/DA1469xAB.h
@@ -954,11 +954,11 @@ typedef struct {                                /*!< (@ 0x50030A00) LRA Structur
   __IOM uint32_t  LRA_FLT_COEF3_REG;            /*!< (@ 0x00000034) LRA Filter Coefficient Register                            */
   __IOM uint32_t  LRA_BRD_LS_REG;               /*!< (@ 0x00000038) LRA Bridge Register                                        */
   __IOM uint32_t  LRA_BRD_HS_REG;               /*!< (@ 0x0000003C) LRA Bridge Register                                        */
-  __IOM uint32_t  LRA_BRD_STAT_REG;             /*!< (@ 0x00000040) LRA Bridge Staus Register                                  */
+  __IOM uint32_t  LRA_BRD_STAT_REG;             /*!< (@ 0x00000040) LRA Bridge Status Register                                  */
   __IOM uint32_t  LRA_ADC_CTRL1_REG;            /*!< (@ 0x00000044) General Purpose ADC Control Register                       */
   __IM  uint32_t  RESERVED[2];
   __IOM uint32_t  LRA_ADC_RESULT_REG;           /*!< (@ 0x00000050) General Purpose ADC Result Register                        */
-  __IOM uint32_t  LRA_LDO_REG;                  /*!< (@ 0x00000054) LRA LDO Regsiter                                           */
+  __IOM uint32_t  LRA_LDO_REG;                  /*!< (@ 0x00000054) LRA LDO Register                                           */
   __IOM uint32_t  LRA_DFT_REG;                  /*!< (@ 0x00000058) LRA test Register                                          */
 } LRA_Type;                                     /*!< Size = 92 (0x5c)                                                          */
 
@@ -1043,7 +1043,7 @@ typedef struct {                                /*!< (@ 0x50000200) PDC Structur
   __IOM uint32_t  PDC_CTRL15_REG;               /*!< (@ 0x0000003C) PDC control register                                       */
   __IM  uint32_t  RESERVED[16];
   __IOM uint32_t  PDC_ACKNOWLEDGE_REG;          /*!< (@ 0x00000080) Clear a pending PDC bit                                    */
-  __IOM uint32_t  PDC_PENDING_REG;              /*!< (@ 0x00000084) Shows any pending wakup event                              */
+  __IOM uint32_t  PDC_PENDING_REG;              /*!< (@ 0x00000084) Shows any pending wakeup event                              */
   __IOM uint32_t  PDC_PENDING_SNC_REG;          /*!< (@ 0x00000088) Shows any pending IRQ to SNC                               */
   __IOM uint32_t  PDC_PENDING_CM33_REG;         /*!< (@ 0x0000008C) Shows any pending IRQ to CM33                              */
   __IOM uint32_t  PDC_PENDING_CMAC_REG;         /*!< (@ 0x00000090) Shows any pending IRQ to CM33                              */
@@ -1752,8 +1752,8 @@ typedef struct {                                /*!< (@ 0x50000100) WAKEUP Struc
   __IOM uint32_t  WKUP_SELECT_P1_REG;           /*!< (@ 0x00000018) select which inputs from P1 port can trigger
                                                                     wkup counter                                               */
   __IM  uint32_t  RESERVED2[3];
-  __IOM uint32_t  WKUP_POL_P0_REG;              /*!< (@ 0x00000028) select the sesitivity polarity for each P0 input           */
-  __IOM uint32_t  WKUP_POL_P1_REG;              /*!< (@ 0x0000002C) select the sesitivity polarity for each P1 input           */
+  __IOM uint32_t  WKUP_POL_P0_REG;              /*!< (@ 0x00000028) select the sensitivity polarity for each P0 input           */
+  __IOM uint32_t  WKUP_POL_P1_REG;              /*!< (@ 0x0000002C) select the sensitivity polarity for each P1 input           */
   __IM  uint32_t  RESERVED3[3];
   __IOM uint32_t  WKUP_STATUS_P0_REG;           /*!< (@ 0x0000003C) Event status register for P0                               */
   __IOM uint32_t  WKUP_STATUS_P1_REG;           /*!< (@ 0x00000040) Event status register for P1                               */
diff --git a/hw/mcu/dialog/da1469x/src/system_da1469x.c b/hw/mcu/dialog/da1469x/src/system_da1469x.c
index 538bac79f..91477b553 100644
--- a/hw/mcu/dialog/da1469x/src/system_da1469x.c
+++ b/hw/mcu/dialog/da1469x/src/system_da1469x.c
@@ -34,7 +34,7 @@ SystemInit(void)
   __ISB();
 #endif
 
-  /* Freez watchdog */
+  /* Freeze watchdog */
   GPREG->SET_FREEZE_REG |= GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
   /* Initialize power domains (disable radio only) */
   CRG_TOP->PMU_CTRL_REG = CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk;
diff --git a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h
index edaf6641f..8cbed0fac 100644
--- a/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h
+++ b/hw/mcu/nordic/nrf5x/s140_nrf52_6.1.1_API/include/ble_l2cap.h
@@ -286,7 +286,7 @@ typedef struct
 /**@brief L2CAP event structure. */
 typedef struct
 {
-  uint16_t conn_handle;                                     /**< Connection Handle on which the event occured. */
+  uint16_t conn_handle;                                     /**< Connection Handle on which the event occurred. */
   uint16_t local_cid;                                       /**< Local Channel ID of the L2CAP channel, or
                                                                  @ref BLE_L2CAP_CID_INVALID if not present. */
   union
diff --git a/hw/mcu/sony/cxd56/tools/flash_writer.py b/hw/mcu/sony/cxd56/tools/flash_writer.py
index 840f10c32..bf630547a 100755
--- a/hw/mcu/sony/cxd56/tools/flash_writer.py
+++ b/hw/mcu/sony/cxd56/tools/flash_writer.py
@@ -46,7 +46,7 @@ import xmodem
 
 import_serial_module = True
 
-# When SDK release, plase set SDK_RELEASE as True.
+# When SDK release, please set SDK_RELEASE as True.
 SDK_RELEASE = False
 
 if SDK_RELEASE :
@@ -508,7 +508,7 @@ def main():
 	do_wait_reset = True
 	if ConfigArgs.AUTO_RESET:
 		if subprocess.call("cd " + sys.path[0] + "; ./reset_board.sh", shell=True) == 0:
-			print("auto reset board sucess!!")
+			print("auto reset board success!!")
 			do_wait_reset = False
 			bootrom_msg = writer.cancel_autoboot()
 
@@ -536,7 +536,7 @@ def main():
 
 	# Remove files
 	if ConfigArgs.ERASE_NAME :
-		print(">>> Remove exisiting files ...")
+		print(">>> Remove existing files ...")
 		writer.delete_files(ConfigArgs.ERASE_NAME)
 
 	# Install files
diff --git a/hw/mcu/sony/cxd56/tools/xmodem.py b/hw/mcu/sony/cxd56/tools/xmodem.py
index c93430056..60fcc952c 100644
--- a/hw/mcu/sony/cxd56/tools/xmodem.py
+++ b/hw/mcu/sony/cxd56/tools/xmodem.py
@@ -147,7 +147,7 @@ class XMODEM(object):
     >>> modem = XMODEM(getc, putc)
 
 
-    :param getc: Function to retreive bytes from a stream
+    :param getc: Function to retrieve bytes from a stream
     :type getc: callable
     :param putc: Function to transmit bytes to a stream
     :type putc: callable
@@ -215,7 +215,7 @@ class XMODEM(object):
             >>> print modem.send(stream)
             True
 
-        Returns ``True`` upon succesful transmission or ``False`` in case of
+        Returns ``True`` upon successful transmission or ``False`` in case of
         failure.
 
         :param stream: The stream object to send data from.
diff --git a/test/unit-test/vendor/ceedling/bin/ceedling b/test/unit-test/vendor/ceedling/bin/ceedling
index d110f3d4c..b317db2f1 100644
--- a/test/unit-test/vendor/ceedling/bin/ceedling
+++ b/test/unit-test/vendor/ceedling/bin/ceedling
@@ -86,7 +86,7 @@ unless (project_found)
           end
         end
 
-        # Genarate gitkeep in test support path
+        # Generate gitkeep in test support path
         FileUtils.touch(File.join(test_support_path, '.gitkeep'))
 
         # If documentation requested, create a place to dump them and do so
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling.rb b/test/unit-test/vendor/ceedling/lib/ceedling.rb
index 6c57fb48d..063cfddd5 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling.rb
@@ -77,7 +77,7 @@ module Ceedling
   # * The gem name must be prefixed with 'ceedling-' followed by the plugin
   #   name (ex. 'ceedling-bullseye')
   #
-  # * The contents of the plugin must be isntalled into a subdirectory of
+  # * The contents of the plugin must be installed into a subdirectory of
   #   the gem with the same name as the plugin (ex. 'bullseye/')
   #
   # === Arguments
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
index 916d31332..9e5ae1fbf 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/preprocessinator_includes_handler.rb
@@ -181,7 +181,7 @@ class PreprocessinatorIncludesHandler
       end
       # If we found a real file, delete it from the array and return it,
       # otherwise return nil. Since nil is falsy this has the effect of making
-      # find_all return only the annotated filess for which a real file was
+      # find_all return only the annotated files for which a real file was
       # found/deleted
       idx ? real_files.delete_at(idx) : nil
     end.compact
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake b/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
index 936961ce8..d599421c0 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/rules_preprocess.rake
@@ -9,7 +9,7 @@ rule(/#{PROJECT_TEST_PREPROCESS_FILES_PATH}\/.+/ => [
     end
   ]) do |file|
   if (not @ceedling[:configurator].project_use_deep_dependencies)
-    raise 'ERROR: Ceedling preprocessing rule invoked though neccessary auxiliary dependency support not enabled.'
+    raise 'ERROR: Ceedling preprocessing rule invoked though necessary auxiliary dependency support not enabled.'
   end
   @ceedling[:generator].generate_preprocessed_file(TEST_SYM, file.source)
 end
diff --git a/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb b/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb
index 81bb7bc54..7d232a7fb 100644
--- a/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb
+++ b/test/unit-test/vendor/ceedling/lib/ceedling/system_utils.rb
@@ -7,7 +7,7 @@ end
 
 
 ##
-# Class containing system utility funcions.
+# Class containing system utility functions.
 class SystemUtils
 
   constructor :system_wrapper
diff --git a/test/unit-test/vendor/ceedling/plugins/dependencies/dependencies.rake b/test/unit-test/vendor/ceedling/plugins/dependencies/dependencies.rake
index 08a1a48eb..4b9409bed 100644
--- a/test/unit-test/vendor/ceedling/plugins/dependencies/dependencies.rake
+++ b/test/unit-test/vendor/ceedling/plugins/dependencies/dependencies.rake
@@ -113,7 +113,7 @@ end
 # Add any artifact:include or :source folders to our release & test includes paths so linking and mocking work.
 @ceedling[DEPENDENCIES_SYM].add_headers_and_sources()
 
-# Add tasks for building or cleaning ALL depencies
+# Add tasks for building or cleaning ALL dependencies
 namespace DEPENDENCIES_SYM do
   desc "Deploy missing dependencies."
   task :deploy => DEPENDENCIES_LIBRARIES.map{|deplib| "#{DEPENDENCIES_SYM}:deploy:#{@ceedling[DEPENDENCIES_SYM].get_name(deplib)}"}
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/README.md b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/README.md
index 8042775e5..c99a95196 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/README.md
@@ -34,7 +34,7 @@ In the `:plugins` configuration, add `fake_function_framework` to the list of en
     - module_generator
     - fake_function_framework
 ```
-*Note that you could put the plugin source in some other loaction.
+*Note that you could put the plugin source in some other location.
 In that case you'd need to add a new path the `:load_paths`.*
 
 ## How to use it
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml
index 00e395d0c..3253acf69 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/project.yml
@@ -33,7 +33,7 @@
   # in order to add common defines:
   #  1) remove the trailing [] from the :common: section
   #  2) add entries to the :common: section (e.g. :test: has TEST defined)
-  :commmon: &common_defines []
+  :common: &common_defines []
   :test:
     - *common_defines
     - TEST
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_event_processor.c b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_event_processor.c
index 9f999443d..ea59cd3e6 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_event_processor.c
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/examples/fff_example/test/test_event_processor.c
@@ -41,7 +41,7 @@ test_whenThePowerReadingIsLessThan5_thenTheStatusLedIsNotTurnedOn(void)
 }
 
 /*
-    Test that a single function was called with the correct arugment.
+    Test that a single function was called with the correct argument.
 */
 void
 test_whenTheVolumeKnobIsMaxed_thenVolumeDisplayIsSetTo11(void)
diff --git a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fake_function_framework.rb b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fake_function_framework.rb
index 51a90b3a5..8fbb1e9b5 100644
--- a/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fake_function_framework.rb
+++ b/test/unit-test/vendor/ceedling/plugins/fake_function_framework/lib/fake_function_framework.rb
@@ -23,7 +23,7 @@ class FakeFunctionFramework < Plugin
     # all mocks linked into the test.
     File.open(arg_hash[:runner_file], 'a') do |f|
       f.puts
-      f.puts "//=======Defintions of FFF variables====="
+      f.puts "//=======Definitions of FFF variables====="
       f.puts %{#include "fff.h"}
       f.puts "DEFINE_FFF_GLOBALS;"
     end
diff --git a/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportgenerator_reportinator.rb b/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportgenerator_reportinator.rb
index d4a885c97..96cf89163 100644
--- a/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportgenerator_reportinator.rb
+++ b/test/unit-test/vendor/ceedling/plugins/gcov/lib/reportgenerator_reportinator.rb
@@ -138,7 +138,7 @@ class ReportGeneratorReportinator
       # Removing trailing ';' after the last report type.
       args = args.chomp(";")
 
-      # Append a space seperator after the report type.
+      # Append a space separator after the report type.
       args += "\" "
     end
 
diff --git a/test/unit-test/vendor/ceedling/plugins/module_generator/README.md b/test/unit-test/vendor/ceedling/plugins/module_generator/README.md
index 61cf45bd6..c7e982352 100644
--- a/test/unit-test/vendor/ceedling/plugins/module_generator/README.md
+++ b/test/unit-test/vendor/ceedling/plugins/module_generator/README.md
@@ -82,7 +82,7 @@ by adding to the `:includes` array. For example:
 ### Boilerplates
 
 You can specify the actual boilerplate used for each of your files. This is the handy place to
-put that corporate copyright notice (or maybe a copyleft notice, if that's your perference?)
+put that corporate copyright notice (or maybe a copyleft notice, if that's your preference?)
 
 ```
 :module_generator:
diff --git a/test/unit-test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb b/test/unit-test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb
index 9730bf40b..b008dc149 100644
--- a/test/unit-test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb
+++ b/test/unit-test/vendor/ceedling/vendor/cmock/lib/cmock_header_parser.rb
@@ -119,7 +119,7 @@ class CMockHeaderParser
     square_bracket_pair_regex_format = /\{[^\{\}]*\}/ # Regex to match one whole block enclosed by two square brackets
 
     # Convert user provided string patterns to regex
-    # Use word bounderies before and after the user regex to limit matching to actual word iso part of a word
+    # Use word boundaries before and after the user regex to limit matching to actual word iso part of a word
     @inline_function_patterns.each do |user_format_string|
       user_regex = Regexp.new(user_format_string)
       word_boundary_before_user_regex = /\b/
@@ -258,7 +258,7 @@ class CMockHeaderParser
 
     source.gsub!(/\s*=\s*['"a-zA-Z0-9_\.]+\s*/, '')                                        # remove default value statements from argument lists
     source.gsub!(/^(?:[\w\s]*\W)?typedef\W[^;]*/m, '')                                     # remove typedef statements
-    source.gsub!(/\)(\w)/, ') \1')                                                         # add space between parenthese and alphanumeric
+    source.gsub!(/\)(\w)/, ') \1')                                                         # add space between parentheses and alphanumeric
     source.gsub!(/(^|\W+)(?:#{@c_strippables.join('|')})(?=$|\W+)/, '\1') unless @c_strippables.empty? # remove known attributes slated to be stripped
 
     # scan standalone function pointers and remove them, because they can just be ignored
diff --git a/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb b/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
index d1d8f91af..6821bdc60 100644
--- a/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
+++ b/test/unit-test/vendor/ceedling/vendor/unity/auto/generate_test_runner.rb
@@ -114,7 +114,7 @@ class UnityTestRunnerGenerator
     # @ is not a valid C character, so there should be no clashes with files genuinely containing these markers
     substring_subs = { '{' => '@co@', '}' => '@cc@', ';' => '@ss@', '/' => '@fs@' }
     substring_re = Regexp.union(substring_subs.keys)
-    substring_unsubs = substring_subs.invert                   # the inverse map will be used to fix the strings afterwords
+    substring_unsubs = substring_subs.invert                   # the inverse map will be used to fix the strings afterwards
     substring_unsubs['@quote@'] = '\\"'
     substring_unsubs['@apos@'] = '\\\''
     substring_unre = Regexp.union(substring_unsubs.keys)
diff --git a/test/unit-test/vendor/ceedling/vendor/unity/src/unity.c b/test/unit-test/vendor/ceedling/vendor/unity/src/unity.c
index 764a42b18..ae5afa856 100644
--- a/test/unit-test/vendor/ceedling/vendor/unity/src/unity.c
+++ b/test/unit-test/vendor/ceedling/vendor/unity/src/unity.c
@@ -13,7 +13,7 @@
 #define PROGMEM
 #endif
 
-/* If omitted from header, declare overrideable prototypes here so they're ready for use */
+/* If omitted from header, declare overridable prototypes here so they're ready for use */
 #ifdef UNITY_OMIT_OUTPUT_CHAR_HEADER_DECLARATION
 void UNITY_OUTPUT_CHAR(int);
 #endif

From 57d23c7a68b37555cfe1c8a8dc4c0983fb07f0e9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 18:34:56 +0700
Subject: [PATCH 1564/2085] update example description

---
 examples/host/msc_file_explorer/src/main.c | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index 40c88a7d3..7b1c2ef27 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -23,6 +23,38 @@
  *
  */
 
+/* Example to show how to navigate mass storage device with built-in command line.
+ * Type help for list of supported commands and syntax (mostly linux commands)
+
+ > help
+ * help
+        Print list of commands
+ * cat
+        Usage: cat [FILE]...
+        Concatenate FILE(s) to standard output..
+ * cd
+        Usage: cd [DIR]...
+        Change the current directory to DIR.
+ * cp
+        Usage: cp SOURCE DEST
+        Copy SOURCE to DEST.
+ * ls
+        Usage: ls [DIR]...
+        List information about the FILEs (the current directory by default).
+ * pwd
+        Usage: pwd
+        Print the name of the current working directory.
+ * mkdir
+        Usage: mkdir DIR...
+        Create the DIRECTORY(ies), if they do not already exist..
+ * mv
+        Usage: mv SOURCE DEST...
+        Rename SOURCE to DEST.
+ * rm
+        Usage: rm [FILE]...
+        Remove (unlink) the FILE(s).
+ */
+
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>

From 6683053f4827b682f51c56ed664e440c0286de80 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 18:44:30 +0700
Subject: [PATCH 1565/2085] finalize

---
 .github/workflows/pre-commit.yml | 3 ---
 .pre-commit-config.yaml          | 2 +-
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index 86c106151..ab416bc52 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -35,9 +35,6 @@ jobs:
     - name: Run pre-commit
       uses: pre-commit/action@v3.0.0
 
-    - name: Run codespell
-      uses: codespell-project/actions-codespell@master
-
     - name: Build Fuzzer
       run: |
         export CC=clang
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index d37c27d40..7fa6f52ee 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -15,7 +15,7 @@ repos:
   rev: v2.2.4
   hooks:
   - id: codespell
-    args: [-w]
+    #args: [-w]
     exclude: ^lib/
 
 - repo: local

From bc57358eb0b9a72325a10b0324ae4a8a024cc692 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 19:29:25 +0700
Subject: [PATCH 1566/2085] Update README.rst

---
 README.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.rst b/README.rst
index 566af8584..adca22433 100644
--- a/README.rst
+++ b/README.rst
@@ -50,8 +50,8 @@ The stack supports the following MCUs:
 - **Raspberry Pi:** RP2040
 - **Renesas:**
 
-	- RX Series: 63N, 65N, 72N
-	- RA Series: RA4M1, RA4M3
+  - RX Series: 63N, 65N, 72N
+  - RA Series: RA4M1, RA4M3
 
 - **Silabs:** EFM32GG
 - **Sony:** CXD56

From 899e7cc4f908b721c619818b6c0c5f9d71974edb Mon Sep 17 00:00:00 2001
From: Koen De Vleeschauwer <kdv@kdvelectronics.eu>
Date: Thu, 2 Feb 2023 10:16:57 +0100
Subject: [PATCH 1567/2085] add board: DshanMCU Pitaya Lite

---
 .../boards/mm32f327x_bluepillplus/board.mk    |   8 +
 .../boards/mm32f327x_bluepillplus/flash.ld    | 163 ++++++++++++++++
 .../mm32f327x_bluepillplus.c                  | 182 ++++++++++++++++++
 .../boards/mm32f327x_pitaya_lite/board.mk     |   8 +
 .../boards/mm32f327x_pitaya_lite/flash.ld     | 163 ++++++++++++++++
 .../mm32f327x_pitaya_lite.c                   | 182 ++++++++++++++++++
 6 files changed, 706 insertions(+)
 create mode 100644 hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk
 create mode 100644 hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld
 create mode 100644 hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
 create mode 100644 hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
 create mode 100644 hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
 create mode 100644 hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c

diff --git a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk
new file mode 100644
index 000000000..b7663926f
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk
@@ -0,0 +1,8 @@
+LD_FILE = $(BOARD_PATH)/flash.ld
+SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
+
+# For flash-jlink target
+#JLINK_DEVICE = stm32f411ve
+
+# flash target using on-board stlink
+#flash: flash-jlink
diff --git a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld
new file mode 100644
index 000000000..0b45ee7bd
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld
@@ -0,0 +1,163 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2001FFFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
new file mode 100644
index 000000000..08abc83c6
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
@@ -0,0 +1,182 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* WeAct BluePillPlus with MM32F3273G6P */
+
+#include "mm32_device.h"
+#include "hal_conf.h"
+#include "tusb.h"
+#include "../board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler (void)
+{
+  tud_int_handler(0);
+
+}
+void USB_DeviceClockInit (void)
+{
+  /* Select USBCLK source */
+  //  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
+  RCC->CFGR &= ~(0x3 << 22);
+  RCC->CFGR |= (0x1 << 22);
+
+  /* Enable USB clock */
+  RCC->AHB2ENR |= 0x1 << 7;
+}
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+
+extern u32 SystemCoreClock;
+const int baudrate = 115200;
+
+void board_init (void)
+{
+//   usb clock	
+  USB_DeviceClockInit();
+
+  if ( SysTick_Config(SystemCoreClock / 1000) )
+  {
+    while ( 1 )
+      ;
+  }
+  NVIC_SetPriority(SysTick_IRQn, 0x0);
+
+  // LED on PB2
+  GPIO_InitTypeDef GPIO_InitStruct;
+  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOB, ENABLE);
+  GPIO_StructInit(&GPIO_InitStruct);
+
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  board_led_write(true);
+
+  // KEY on PA0
+  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
+  GPIO_StructInit(&GPIO_InitStruct);
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_0;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPD;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  // UART
+  UART_InitTypeDef UART_InitStruct;
+
+  RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE);    //enableUART1,GPIOAclock
+  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);      //
+  //UART initialset
+
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
+
+  UART_StructInit(&UART_InitStruct);
+  UART_InitStruct.UART_BaudRate = baudrate;
+  UART_InitStruct.UART_WordLength = UART_WordLength_8b;
+  UART_InitStruct.UART_StopBits = UART_StopBits_1;    //one stopbit
+  UART_InitStruct.UART_Parity = UART_Parity_No;    //none odd-even  verify bit
+  UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;    //No hardware flow control
+  UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx;    // receive and sent  mode
+
+  UART_Init(UART1, &UART_InitStruct);    //initial uart 1
+  UART_Cmd(UART1, ENABLE);                    //enable uart 1
+
+  //UART1_TX   GPIOA.9
+  GPIO_StructInit(&GPIO_InitStruct);
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  //UART1_RX    GPIOA.10
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+}
+
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write (bool state)
+{
+  state ? (GPIO_ResetBits(GPIOB, GPIO_Pin_2)) : (GPIO_SetBits(GPIOB, GPIO_Pin_2));
+}
+
+uint32_t board_button_read (void)
+{
+  uint32_t key = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0) == Bit_SET;
+  return key;
+}
+
+int board_uart_read (uint8_t *buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write (void const *buf, int len)
+{
+  const char *buff = buf;
+  while ( len )
+  {
+    while ( (UART1->CSR & UART_IT_TXIEN) == 0 )
+      ;    //The loop is sent until it is finished
+    UART1->TDR = (*buff & 0xFF);
+    buff++;
+    len--;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis (void)
+{
+  return system_ticks;
+}
+#endif
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
new file mode 100644
index 000000000..fbf0322c1
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
@@ -0,0 +1,8 @@
+LD_FILE = $(BOARD_PATH)/flash.ld
+SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
+
+# For flash-jlink target
+#JLINK_DEVICE = MM32F3273G8P
+
+# flash target using on-board stlink
+#flash: flash-jlink
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
new file mode 100644
index 000000000..0b45ee7bd
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
@@ -0,0 +1,163 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2001FFFF;    /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
new file mode 100644
index 000000000..819b440e5
--- /dev/null
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
@@ -0,0 +1,182 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 MM32 SE TEAM
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/* DshanMCU Pitaya Lite with MM32F3273 */
+
+#include "mm32_device.h"
+#include "hal_conf.h"
+#include "tusb.h"
+#include "../board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void OTG_FS_IRQHandler (void)
+{
+  tud_int_handler(0);
+
+}
+void USB_DeviceClockInit (void)
+{
+  /* Select USBCLK source */
+  //  RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
+  RCC->CFGR &= ~(0x3 << 22);
+  RCC->CFGR |= (0x1 << 22);
+
+  /* Enable USB clock */
+  RCC->AHB2ENR |= 0x1 << 7;
+}
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+
+extern u32 SystemCoreClock;
+const int baudrate = 115200;
+
+void board_init (void)
+{
+//   usb clock
+// requires SYSCLK_FREQ_XXMHz  (HSE_VALUE*8) in system_mm32f327x.c
+  USB_DeviceClockInit();
+
+  if ( SysTick_Config(SystemCoreClock / 1000) )
+  {
+    while ( 1 )
+      ;
+  }
+  NVIC_SetPriority(SysTick_IRQn, 0x0);
+
+  // LED on PA1
+  GPIO_InitTypeDef GPIO_InitStruct;
+  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);
+  GPIO_StructInit(&GPIO_InitStruct);
+
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_1;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  board_led_write(true);
+
+  // KEY on PA0
+  GPIO_StructInit(&GPIO_InitStruct);
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_0;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_10MHz;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_FLOATING;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  // UART
+  UART_InitTypeDef UART_InitStruct;
+
+  RCC_APB2PeriphClockCmd(RCC_APB2ENR_UART1, ENABLE);    //enableUART1,GPIOAclock
+  RCC_AHBPeriphClockCmd(RCC_AHBENR_GPIOA, ENABLE);      //
+  //UART initialset
+
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7);
+  GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7);
+
+  UART_StructInit(&UART_InitStruct);
+  UART_InitStruct.UART_BaudRate = baudrate;
+  UART_InitStruct.UART_WordLength = UART_WordLength_8b;
+  UART_InitStruct.UART_StopBits = UART_StopBits_1;    //one stopbit
+  UART_InitStruct.UART_Parity = UART_Parity_No;    //none odd-even  verify bit
+  UART_InitStruct.UART_HardwareFlowControl = UART_HardwareFlowControl_None;    //No hardware flow control
+  UART_InitStruct.UART_Mode = UART_Mode_Rx | UART_Mode_Tx;    // receive and sent  mode
+
+  UART_Init(UART1, &UART_InitStruct);    //initial uart 1
+  UART_Cmd(UART1, ENABLE);                    //enable uart 1
+
+  //UART1_TX   GPIOA.9
+  GPIO_StructInit(&GPIO_InitStruct);
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  //UART1_RX    GPIOA.10
+  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_5;
+  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
+  GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+}
+
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write (bool state)
+{
+  state ? (GPIO_ResetBits(GPIOA, GPIO_Pin_1)) : (GPIO_SetBits(GPIOA, GPIO_Pin_1));
+}
+
+uint32_t board_button_read (void)
+{
+  uint32_t key = GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_0) == Bit_RESET;
+  return key;
+}
+
+int board_uart_read (uint8_t *buf, int len)
+{
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write (void const *buf, int len)
+{
+  const char *buff = buf;
+  while ( len )
+  {
+    while ( (UART1->CSR & UART_IT_TXIEN) == 0 )
+      ;    //The loop is sent until it is finished
+    UART1->TDR = (*buff & 0xFF);
+    buff++;
+    len--;
+  }
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis (void)
+{
+  return system_ticks;
+}
+#endif
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}

From b3ecf82196f09ca26161d63dc15c4c3aec6ae57d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 19:31:45 +0700
Subject: [PATCH 1568/2085] whitespace

---
 hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld        | 8 ++++----
 .../mm32f327x_bluepillplus/mm32f327x_bluepillplus.c       | 4 ++--
 hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld         | 8 ++++----
 .../boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c  | 2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld
index 0b45ee7bd..796ed04f6 100644
--- a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld
+++ b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/flash.ld
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 MM32 SE TEAM
@@ -110,7 +110,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -121,7 +121,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -149,7 +149,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
index 08abc83c6..0a07dc749 100644
--- a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
+++ b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 MM32 SE TEAM
@@ -59,7 +59,7 @@ const int baudrate = 115200;
 
 void board_init (void)
 {
-//   usb clock	
+//   usb clock
   USB_DeviceClockInit();
 
   if ( SysTick_Config(SystemCoreClock / 1000) )
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
index 0b45ee7bd..796ed04f6 100644
--- a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/flash.ld
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 MM32 SE TEAM
@@ -110,7 +110,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -121,7 +121,7 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
@@ -149,7 +149,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
index 819b440e5..381e93e11 100644
--- a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2020 MM32 SE TEAM

From 1ed04ad05d1c44ea2821173cadd7c3ea871f4610 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 19:46:22 +0700
Subject: [PATCH 1569/2085] update mm32sdk with idndef for SYSCLK_FREQ_XXMHz
 and SYSCLK_HSI_XXMHz

add HSE_VALUE define for each board with 8mhz, 12mhz accordingly
---
 hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk | 3 +++
 hw/bsp/mm32/boards/mm32f327x_mb39/board.mk         | 4 ++++
 hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk  | 3 +++
 tools/get_deps.py                                  | 2 +-
 4 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk
index b7663926f..bda3daf91 100644
--- a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk
+++ b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/board.mk
@@ -1,3 +1,6 @@
+CFLAGS += \
+	-DHSE_VALUE=8000000
+
 LD_FILE = $(BOARD_PATH)/flash.ld
 SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
 
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
index b7663926f..a0d92d1c7 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.mk
@@ -1,6 +1,10 @@
+CFLAGS += \
+	-DHSE_VALUE=8000000
+
 LD_FILE = $(BOARD_PATH)/flash.ld
 SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
 
+
 # For flash-jlink target
 #JLINK_DEVICE = stm32f411ve
 
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
index fbf0322c1..a778e749f 100644
--- a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.mk
@@ -1,3 +1,6 @@
+CFLAGS += \
+	-DHSE_VALUE=12000000
+
 LD_FILE = $(BOARD_PATH)/flash.ld
 SRC_S += $(SDK_DIR)/mm32f327x/MM32F327x/Source/GCC_StartAsm/startup_mm32m3ux_u_gcc.S
 
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 574e5d089..92bad1408 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -20,7 +20,7 @@ deps_optional = {
     'hw/mcu/gd/nuclei-sdk'                     : ['7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7', 'https://github.com/Nuclei-Software/nuclei-sdk.git'             ],
     'hw/mcu/infineon/mtb-xmclib-cat3'          : ['daf5500d03cba23e68c2f241c30af79cd9d63880', 'https://github.com/Infineon/mtb-xmclib-cat3.git'               ],
     'hw/mcu/microchip'                         : ['9e8b37e307d8404033bb881623a113931e1edf27', 'https://github.com/hathach/microchip_driver.git'               ],
-    'hw/mcu/mindmotion/mm32sdk'                : ['708a7152952ac595d24837069dcc0f7f59a4c30b', 'https://github.com/hathach/mm32sdk.git'                        ],
+    'hw/mcu/mindmotion/mm32sdk'                : ['f6e458fea77074990ce011e3716c08cfeddbd6d5', 'https://github.com/hathach/mm32sdk.git'                        ],
     'hw/mcu/nordic/nrfx'                       : ['281cc2e178fd9a470d844b3afdea9eb322a0b0e8', 'https://github.com/NordicSemiconductor/nrfx.git'               ],
     'hw/mcu/nuvoton'                           : ['2204191ec76283371419fbcec207da02e1bc22fa', 'https://github.com/majbthrd/nuc_driver.git'                    ],
     'hw/mcu/nxp/lpcopen'                       : ['43c45c85405a5dd114fff0ea95cca62837740c13', 'https://github.com/hathach/nxp_lpcopen.git'                    ],

From b2568eb02b5a9ff3af266a2bb1326969830e038a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 17 Mar 2023 20:22:08 +0700
Subject: [PATCH 1570/2085] bump up mm32sdk to fix HSE_VALUE not 8Mhz warnings

---
 tools/get_deps.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index 92bad1408..8bf56cd8d 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -20,7 +20,7 @@ deps_optional = {
     'hw/mcu/gd/nuclei-sdk'                     : ['7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7', 'https://github.com/Nuclei-Software/nuclei-sdk.git'             ],
     'hw/mcu/infineon/mtb-xmclib-cat3'          : ['daf5500d03cba23e68c2f241c30af79cd9d63880', 'https://github.com/Infineon/mtb-xmclib-cat3.git'               ],
     'hw/mcu/microchip'                         : ['9e8b37e307d8404033bb881623a113931e1edf27', 'https://github.com/hathach/microchip_driver.git'               ],
-    'hw/mcu/mindmotion/mm32sdk'                : ['f6e458fea77074990ce011e3716c08cfeddbd6d5', 'https://github.com/hathach/mm32sdk.git'                        ],
+    'hw/mcu/mindmotion/mm32sdk'                : ['0b79559eb411149d36e073c1635c620e576308d4', 'https://github.com/hathach/mm32sdk.git'                        ],
     'hw/mcu/nordic/nrfx'                       : ['281cc2e178fd9a470d844b3afdea9eb322a0b0e8', 'https://github.com/NordicSemiconductor/nrfx.git'               ],
     'hw/mcu/nuvoton'                           : ['2204191ec76283371419fbcec207da02e1bc22fa', 'https://github.com/majbthrd/nuc_driver.git'                    ],
     'hw/mcu/nxp/lpcopen'                       : ['43c45c85405a5dd114fff0ea95cca62837740c13', 'https://github.com/hathach/nxp_lpcopen.git'                    ],

From d919f107c71021b2dfa20cd9bfe252c4f544422f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 18 Mar 2023 11:22:44 +0700
Subject: [PATCH 1571/2085] minor clean up

---
 examples/device/uac2_headset/src/usb_descriptors.h | 8 ++++----
 examples/device/usbtmc/src/usbtmc_app.c            | 1 -
 src/class/video/video.h                            | 2 +-
 src/common/tusb_compiler.h                         | 2 +-
 src/device/usbd.h                                  | 8 ++++----
 5 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 2069cc975..457e69882 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -114,7 +114,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Interface 1, Alternate 2 - alternate interface for data streaming */\
@@ -124,7 +124,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
     /* Standard AS Interface Descriptor(4.9.1) */\
@@ -138,7 +138,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
     /* Interface 2, Alternate 2 - alternate interface for data streaming */\
@@ -148,7 +148,7 @@ enum
     /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
     TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\
     /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
     /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
     TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index f1596f6d0..72989b4fe 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -242,7 +242,6 @@ void usbtmc_app_task_iter(void) {
     break;
   default:
     TU_ASSERT(false,);
-    return;
   }
 }
 
diff --git a/src/class/video/video.h b/src/class/video/video.h
index 40dae4c1a..c0088c4f6 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -549,7 +549,7 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 
 /* 3.10.1.1 */
 #define TUD_VIDEO_DESC_EP_ISO(_ep, _epsize, _ep_interval) \
-  7, TUSB_DESC_ENDPOINT, _ep, (uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS,\
+  7, TUSB_DESC_ENDPOINT, _ep, (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS),\
   U16_TO_U8S_LE(_epsize), _ep_interval
 
 /* 3.10.1.2 */
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index cea876413..713bbb8d4 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -196,7 +196,7 @@
   #define TU_ATTR_DEPRECATED(mess)      __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))             // Function/Variable is meant to be used
-  #define TU_ATTR_FALLTHROUGH
+  #define TU_ATTR_FALLTHROUGH           do {} while (0)  /* fallthrough */
 
   #define TU_ATTR_PACKED_BEGIN
   #define TU_ATTR_PACKED_END
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 7bb9f916b..255e5a844 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -420,7 +420,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */
 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN 7
 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _interval) \
-  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval
+  TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval
 
 // AUDIO simple descriptor (UAC2) for 1 microphone input
 // - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source
@@ -467,7 +467,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -516,7 +516,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
 
@@ -564,7 +564,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
   /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
   TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
   /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
-  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ ((uint8_t) TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
+  TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ TUD_OPT_HIGH_SPEED ? 0x04 : 0x01),\
   /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
   TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
   /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\

From 9f54cc1eb725e7d77a5b275b209d8257b180d7ed Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 18 Mar 2023 11:43:47 +0700
Subject: [PATCH 1572/2085] more clean up

---
 src/class/usbtmc/usbtmc_device.c             | 7 +++++++
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 4 ++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 8dbda14c5..4e320a778 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -154,7 +154,10 @@ TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small");
 static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len);
 static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen);
 
+#ifndef NDEBUG
 tu_static uint8_t termChar;
+#endif
+
 tu_static uint8_t termCharRequested = false;
 
 #if OSAL_MUTEX_REQUIRED
@@ -442,7 +445,10 @@ static bool handle_devMsgIn(void *data, size_t len)
   usbtmc_state.transfer_size_sent = 0u;
 
   termCharRequested = msg->bmTransferAttributes.TermCharEnabled;
+
+#ifndef NDEBUG
   termChar = msg->TermChar;
+#endif
 
   if(termCharRequested)
     TU_VERIFY(usbtmc_state.capabilities->bmDevCapabilities.canEndBulkInOnTermChar);
@@ -511,6 +517,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
       return true;
 
     case STATE_ABORTING_BULK_OUT:
+      // Should be stalled by now, shouldn't have received a packet.
       return false;
 
     case STATE_TX_REQUESTED:
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 79af0204b..5d3d792cb 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -36,8 +36,8 @@
 #define __tusb_irq_path_func(x) x
 #endif
 
-#define usb_hw_set hw_set_alias(usb_hw)
-#define usb_hw_clear hw_clear_alias(usb_hw)
+#define usb_hw_set    ((usb_hw_t *) hw_set_alias(usb_hw))
+#define usb_hw_clear  ((usb_hw_t *) hw_clear_alias(usb_hw))
 
 #define pico_info(...)  TU_LOG(2, __VA_ARGS__)
 #define pico_trace(...) TU_LOG(3, __VA_ARGS__)

From f9b8a0667a2cc42a6c6521c51bba695ca8e9e28f Mon Sep 17 00:00:00 2001
From: Bob Paddock <bob.pddock@pm.me>
Date: Mon, 16 Jan 2023 15:05:31 -0500
Subject: [PATCH 1573/2085] Add support for NXP FRDM_K32L2A4S eval board.

---
 hw/bsp/board_mcu.h                   |   2 +-
 hw/bsp/frdm_k32l2a4s/README.rst      |  51 ++++++++
 hw/bsp/frdm_k32l2a4s/board.h         |  58 +++++++++
 hw/bsp/frdm_k32l2a4s/board.mk        |  80 +++++++++++++
 hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c | 171 +++++++++++++++++++++++++++
 src/common/tusb_mcu.h                |   2 +-
 src/portable/nxp/khci/dcd_khci.c     |   9 +-
 src/portable/nxp/khci/hcd_khci.c     |   9 +-
 src/tusb_option.h                    |   1 +
 9 files changed, 375 insertions(+), 8 deletions(-)
 create mode 100644 hw/bsp/frdm_k32l2a4s/README.rst
 create mode 100644 hw/bsp/frdm_k32l2a4s/board.h
 create mode 100644 hw/bsp/frdm_k32l2a4s/board.mk
 create mode 100644 hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index b34197e6c..920e7d0d9 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -47,7 +47,7 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
       CFG_TUSB_MCU == OPT_MCU_LPC55XX  || CFG_TUSB_MCU == OPT_MCU_MKL25ZXX || \
-      CFG_TUSB_MCU == OPT_MCU_K32L2BXX
+      CFG_TUSB_MCU == OPT_MCU_K32L2AXX || OPT_MCU_K32L2BXX
   #include "fsl_device_registers.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
diff --git a/hw/bsp/frdm_k32l2a4s/README.rst b/hw/bsp/frdm_k32l2a4s/README.rst
new file mode 100644
index 000000000..68ab409c3
--- /dev/null
+++ b/hw/bsp/frdm_k32l2a4s/README.rst
@@ -0,0 +1,51 @@
+Jan/13/2023 13:04
+
+The FRDM-K32L2B3 Freedom development board provides a platform for
+evaluation and development of the K32 L2B MCU Family. -
+https://www.nxp.com/part/FRDM-K32L2B3#/
+
+TinyUSB does not include the board specific drivers. Those drivers
+need to be extracted from the MCUXpresso IDE and SDK.
+
+Install MCUXPresso version 11.6 or later and SDK 2.12 or later.  Then
+build the example project "frdmk32l2b_hellow_worldvirual_com".
+
+From the frdmk32l2b_hellow_worldvirual_com project copy these files to
+this directory structure, in this directory:
+
+hw/mcu/nxp/mcux-sdk/devices/K32L2B31A
+
+CMSIS/
+config/
+drivers/
+gcc/
+fsl_device_registers.h
+K32L2B31A_features.h
+K32L2B31A.h
+
+./CMSIS:
+cmsis_armcc.h     cmsis_armclang_ltm.h  cmsis_gcc.h     cmsis_version.h  mpu_armv7.h
+cmsis_armclang.h  cmsis_compiler.h      cmsis_iccarm.h  core_cm0plus.h
+
+./config:
+clock_config.c  clock_config.h  system_K32L2B31A.c  system_K32L2B31A.h
+
+./drivers:
+fsl_clock.c       fsl_common_arm.h  fsl_gpio.c    fsl_lpuart.h  fsl_smc.h
+fsl_clock.h       fsl_common.c      fsl_gpio.h    fsl_port.h    fsl_uart.c
+fsl_common_arm.c  fsl_common.h      fsl_lpuart.c  fsl_smc.c     fsl_uart.h
+
+./gcc:
+frdmk32l2b.ld          startup_k32l2b31a.c
+frdmk32l2b_library.ld  frdmk32l2b_memory.ld
+
+The linker files have been renamed and the #include directive edited
+to match.
+
+Then to build a test project change to the directory
+examples/devices/cdc_msc and do:
+
+make BOARD=frdm_k32l2b
+
+The resulting .hex file will be found in the _build directory, copy
+that will to the FRDM board to run the demo.
diff --git a/hw/bsp/frdm_k32l2a4s/board.h b/hw/bsp/frdm_k32l2a4s/board.h
new file mode 100644
index 000000000..14eefda17
--- /dev/null
+++ b/hw/bsp/frdm_k32l2a4s/board.h
@@ -0,0 +1,58 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#include "fsl_device_registers.h"
+
+// LED
+// The Red   LED is on PTE29.
+// The Green LED is on PTC4.
+// The Blue  LED is on PTE31.
+#define LED_PIN_CLOCK         kCLOCK_PortC
+#define LED_GPIO              GPIOC
+#define LED_PORT              PORTC
+#define LED_PIN               4
+#define LED_STATE_ON          0
+
+// SW3 button1
+#define BUTTON_PIN_CLOCK      kCLOCK_PortE
+#define BUTTON_GPIO           GPIOE
+#define BUTTON_PORT           PORTE
+#define BUTTON_PIN            4
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_PORT             LPUART0
+#define UART_PIN_CLOCK        kCLOCK_PortB
+#define UART_PIN_GPIO         GPIOB
+#define UART_PIN_PORT         PORTB
+#define UART_PIN_RX           16u
+#define UART_PIN_TX           17u
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/frdm_k32l2a4s/board.mk b/hw/bsp/frdm_k32l2a4s/board.mk
new file mode 100644
index 000000000..e9e606fe6
--- /dev/null
+++ b/hw/bsp/frdm_k32l2a4s/board.mk
@@ -0,0 +1,80 @@
+
+# Default to a less-verbose build.  If you want all the gory compiler output,
+# "VERBOSE=1" to the make command line.
+ifndef VERBOSE
+.SILENT:
+$(info Non-Verbose Output)
+else
+$(info Verbose Output)
+endif
+
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+MCU_DIR = $(SDK_DIR)/devices/K32L2A4S
+
+ifdef VERBOSE
+$(info TOP='$(TOP)')
+$(info )
+
+$(info BSP='$(TOP)/hw/bsp/$(BOARD)')
+$(info )
+
+$(info TOP/SDK_DIR='$(TOP)/$(SDK_DIR)')
+$(info )
+
+$(info MCU_DIR='$(MCU_DIR)')
+$(info )
+endif
+
+DEPS_SUBMODULES += $(SDK_DIR)
+
+CFLAGS += \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0plus \
+  -DCPU_K32L2A41VLH1A \
+  -DCFG_TUSB_MCU=OPT_MCU_K32L2AXX
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual
+
+# All source paths should be relative to the top level.
+
+LD_FILE  = $(MCU_DIR)/gcc/frdmk32l2a4s.ld
+LDFLAGS += -L$(TOP)/$(MCU_DIR)/gcc
+
+# Define Recursive Depth wildcard:
+rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d))
+
+SRC_C += \
+	src/portable/nxp/khci/dcd_khci.c \
+	$(MCU_DIR)/gcc/startup_k32l2a41a.c
+
+SRC_C += $(call rwildcard,$(TOP)/$(MCU_DIR)/config,*.c)
+SRC_C += $(call rwildcard,$(TOP)/$(MCU_DIR)/drivers,*.c)
+
+INC += \
+	$(TOP)/hw/bsp/$(BOARD) \
+	$(TOP)/$(MCU_DIR)/CMSIS/ \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/config \
+	$(TOP)/$(MCU_DIR)/drivers
+
+ifdef VERBOSE
+$(info INC = '$(strip $(INC))')
+$(info )
+
+$(info SRC_C = '$(sort $(strip $(SRC_C)))')
+$(info )
+endif
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM0
+
+# For flash-jlink target
+#JLINK_DEVICE = ?
+
+# For flash-pyocd target
+PYOCD_TARGET = K32L2A
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c
new file mode 100644
index 000000000..47dd0c8ec
--- /dev/null
+++ b/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c
@@ -0,0 +1,171 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ * Copyright (c) 2020, Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../board.h"
+#include "board.h"
+#include "fsl_gpio.h"
+#include "fsl_port.h"
+#include "fsl_clock.h"
+#include "fsl_lpuart.h"
+
+#include "clock_config.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void board_init(void)
+{
+  /* Enable port clocks for UART/LED/Button pins */
+  CLOCK_EnableClock(UART_PIN_CLOCK);
+  CLOCK_EnableClock(LED_PIN_CLOCK);
+  CLOCK_EnableClock(BUTTON_PIN_CLOCK);
+
+  gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0 };
+  GPIO_PinInit(LED_GPIO, LED_PIN, &led_config);
+  PORT_SetPinMux(LED_PORT, LED_PIN, kPORT_MuxAsGpio);
+
+  gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0 };
+  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
+  const port_pin_config_t BUTTON_CFG = {
+    kPORT_PullUp,
+    kPORT_FastSlewRate,
+    kPORT_PassiveFilterDisable,
+    kPORT_OpenDrainDisable,
+    kPORT_LowDriveStrength,
+    kPORT_MuxAsGpio,
+    kPORT_UnlockRegister
+  };
+  PORT_SetPinConfig(BUTTON_PORT, BUTTON_PIN, &BUTTON_CFG);
+
+  /*
+    Enable LPUART0 clock and configure port pins.
+    FIR clock is being used so the USB examples work.
+  */
+  PCC_LPUART0  = 0U;                          /* Clock must be off to set PCS */
+  PCC_LPUART0  = PCC_CLKCFG_PCS( 3U );        /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */
+  PCC_LPUART0 |= PCC_CLKCFG_CGC( 1U );        /* Enable LPUART */
+
+  /* PORTB16 (pin 62) is configured as LPUART0_RX */
+  gpio_pin_config_t const lpuart_config_rx = { kGPIO_DigitalInput, 0 };
+  GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx);
+  const port_pin_config_t UART_CFG = {
+    kPORT_PullUp,
+    kPORT_FastSlewRate,
+    kPORT_PassiveFilterDisable,
+    kPORT_OpenDrainDisable,
+    kPORT_LowDriveStrength,
+    kPORT_MuxAsGpio,
+    kPORT_UnlockRegister
+  };
+  PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG);
+  PORT_SetPinMux(   UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3);
+
+  /* PORTB17 (pin 63) is configured as LPUART0_TX */
+  gpio_pin_config_t const lpuart_config_tx = { kGPIO_DigitalOutput, 0 };
+  GPIO_PinInit(   UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx);
+  PORT_SetPinMux( UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3);
+
+  BOARD_BootClockRUN();
+  SystemCoreClockUpdate();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  lpuart_config_t uart_config;
+  LPUART_GetDefaultConfig(&uart_config);
+  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
+  uart_config.enableTx = true;
+  uart_config.enableRx = true;
+  LPUART_Init(UART_PORT, &uart_config, CLOCK_GetFreq(kCLOCK_ScgFircClk));
+
+  // USB
+  CLOCK_EnableUsbfs0Clock(kCLOCK_IpSrcFircAsync, 48000000U);
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+#if 0 /*
+	Use this version if want the LED to blink during BOARD=board_test,
+	without having to hit a key.
+      */
+  if( 0U != (kLPUART_RxDataRegFullFlag & LPUART_GetStatusFlags( UART_PORT )) )
+    {
+      LPUART_ReadBlocking(UART_PORT, buf, len);
+      return len;
+    }
+
+  return( 0 );
+#else /* Wait for 'len' characters to come in */
+
+  LPUART_ReadBlocking(UART_PORT, buf, len);
+  return len;
+
+#endif
+}
+
+int board_uart_write(void const * buf, int len)
+{
+  LPUART_WriteBlocking(UART_PORT, (uint8_t const*) buf, len);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 1d27f47af..18e40e1b1 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -85,7 +85,7 @@
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1 // Port0 HS, Port1 HS
 
-#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2BXX)
+#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2AXX, OPT_MCU_K32L2BXX)
   #define TUP_DCD_ENDPOINT_MAX    16
 
 #elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index b6daec3de..2678cdca1 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -26,9 +26,12 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED && ( \
-      ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \
-    )
+#if CFG_TUD_ENABLED &&                     \
+  (					   \
+   ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || \
+   ( CFG_TUSB_MCU == OPT_MCU_K32L2AXX ) || \
+   ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX )	   \
+  )
 
 #include "fsl_device_registers.h"
 #define KHCI        USB0
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 35763f121..8ff1feff7 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -26,9 +26,12 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && ( \
-      ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX ) \
-    )
+#if CFG_TUD_ENABLED &&                     \
+  (					   \
+   ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || \
+   ( CFG_TUSB_MCU == OPT_MCU_K32L2AXX ) || \
+   ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX )	   \
+  )
 
 #include "fsl_device_registers.h"
 #define KHCI        USB0
diff --git a/src/tusb_option.h b/src/tusb_option.h
index c019b0ba4..5a234e357 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -119,6 +119,7 @@
 // NXP Kinetis
 #define OPT_MCU_MKL25ZXX         1200 ///< NXP MKL25Zxx
 #define OPT_MCU_K32L2BXX         1201 ///< NXP K32L2Bxx
+#define OPT_MCU_K32L2AXX         1202 ///< NXP K32L2Axx
 
 // Silabs
 #define OPT_MCU_EFM32GG          1300 ///< Silabs EFM32GG

From b13b95a6705348947aa2117423788b5dc2289047 Mon Sep 17 00:00:00 2001
From: Bob Paddock <bob.pddock@pm.me>
Date: Mon, 16 Jan 2023 15:17:11 -0500
Subject: [PATCH 1574/2085] Document that support for the FRDM-K32L2A4S has
 been added.

---
 docs/reference/supported.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index b3f3f41d3..b1e0c0a68 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -253,6 +253,7 @@ Kinetis
 ^^^^^^^
 
 -  `Freedom FRDM-KL25Z <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z>`__
+-  `Freedom FRDM-K32L2A  <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/nxp-freedom-platform-for-k32-l2a-mcus:FRDM-K32L2A4S>`__
 -  `Freedom FRDM-K32L2B3 <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3>`__
 -  `KUIIC <https://github.com/nxf58843/kuiic>`__
 

From 2d187777c0eb625ad7c63c21dd881ca7362363fc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 18 Mar 2023 18:30:51 +0700
Subject: [PATCH 1575/2085] merge kinetis into its own family in bsp

---
 hw/bsp/frdm_k32l2a4s/README.rst               | 51 ------------
 hw/bsp/frdm_k32l2a4s/board.mk                 | 80 -------------------
 hw/bsp/frdm_k32l2b/board.mk                   | 51 ------------
 .../boards}/frdm_k32l2a4s/board.h             |  2 +-
 hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk  | 26 ++++++
 .../boards}/frdm_k32l2a4s/frdm_k32l2a4s.c     |  2 +-
 .../{ => kinetis/boards}/frdm_k32l2b/board.h  |  0
 hw/bsp/kinetis/boards/frdm_k32l2b/board.mk    | 26 ++++++
 .../boards}/frdm_k32l2b/frdm_k32l2b.c         |  2 +-
 .../{ => kinetis/boards}/frdm_kl25z/board.mk  | 27 +------
 .../boards}/frdm_kl25z/frdm_kl25z.c           |  0
 hw/bsp/kinetis/family.mk                      | 46 +++++++++++
 src/common/tusb_mcu.h                         |  2 +
 src/portable/nxp/khci/dcd_khci.c              | 15 ++--
 src/portable/nxp/khci/hcd_khci.c              |  2 +-
 15 files changed, 114 insertions(+), 218 deletions(-)
 delete mode 100644 hw/bsp/frdm_k32l2a4s/README.rst
 delete mode 100644 hw/bsp/frdm_k32l2a4s/board.mk
 delete mode 100644 hw/bsp/frdm_k32l2b/board.mk
 rename hw/bsp/{ => kinetis/boards}/frdm_k32l2a4s/board.h (99%)
 create mode 100644 hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk
 rename hw/bsp/{ => kinetis/boards}/frdm_k32l2a4s/frdm_k32l2a4s.c (99%)
 rename hw/bsp/{ => kinetis/boards}/frdm_k32l2b/board.h (100%)
 create mode 100644 hw/bsp/kinetis/boards/frdm_k32l2b/board.mk
 rename hw/bsp/{ => kinetis/boards}/frdm_k32l2b/frdm_k32l2b.c (99%)
 rename hw/bsp/{ => kinetis/boards}/frdm_kl25z/board.mk (54%)
 rename hw/bsp/{ => kinetis/boards}/frdm_kl25z/frdm_kl25z.c (100%)
 create mode 100644 hw/bsp/kinetis/family.mk

diff --git a/hw/bsp/frdm_k32l2a4s/README.rst b/hw/bsp/frdm_k32l2a4s/README.rst
deleted file mode 100644
index 68ab409c3..000000000
--- a/hw/bsp/frdm_k32l2a4s/README.rst
+++ /dev/null
@@ -1,51 +0,0 @@
-Jan/13/2023 13:04
-
-The FRDM-K32L2B3 Freedom development board provides a platform for
-evaluation and development of the K32 L2B MCU Family. -
-https://www.nxp.com/part/FRDM-K32L2B3#/
-
-TinyUSB does not include the board specific drivers. Those drivers
-need to be extracted from the MCUXpresso IDE and SDK.
-
-Install MCUXPresso version 11.6 or later and SDK 2.12 or later.  Then
-build the example project "frdmk32l2b_hellow_worldvirual_com".
-
-From the frdmk32l2b_hellow_worldvirual_com project copy these files to
-this directory structure, in this directory:
-
-hw/mcu/nxp/mcux-sdk/devices/K32L2B31A
-
-CMSIS/
-config/
-drivers/
-gcc/
-fsl_device_registers.h
-K32L2B31A_features.h
-K32L2B31A.h
-
-./CMSIS:
-cmsis_armcc.h     cmsis_armclang_ltm.h  cmsis_gcc.h     cmsis_version.h  mpu_armv7.h
-cmsis_armclang.h  cmsis_compiler.h      cmsis_iccarm.h  core_cm0plus.h
-
-./config:
-clock_config.c  clock_config.h  system_K32L2B31A.c  system_K32L2B31A.h
-
-./drivers:
-fsl_clock.c       fsl_common_arm.h  fsl_gpio.c    fsl_lpuart.h  fsl_smc.h
-fsl_clock.h       fsl_common.c      fsl_gpio.h    fsl_port.h    fsl_uart.c
-fsl_common_arm.c  fsl_common.h      fsl_lpuart.c  fsl_smc.c     fsl_uart.h
-
-./gcc:
-frdmk32l2b.ld          startup_k32l2b31a.c
-frdmk32l2b_library.ld  frdmk32l2b_memory.ld
-
-The linker files have been renamed and the #include directive edited
-to match.
-
-Then to build a test project change to the directory
-examples/devices/cdc_msc and do:
-
-make BOARD=frdm_k32l2b
-
-The resulting .hex file will be found in the _build directory, copy
-that will to the FRDM board to run the demo.
diff --git a/hw/bsp/frdm_k32l2a4s/board.mk b/hw/bsp/frdm_k32l2a4s/board.mk
deleted file mode 100644
index e9e606fe6..000000000
--- a/hw/bsp/frdm_k32l2a4s/board.mk
+++ /dev/null
@@ -1,80 +0,0 @@
-
-# Default to a less-verbose build.  If you want all the gory compiler output,
-# "VERBOSE=1" to the make command line.
-ifndef VERBOSE
-.SILENT:
-$(info Non-Verbose Output)
-else
-$(info Verbose Output)
-endif
-
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-MCU_DIR = $(SDK_DIR)/devices/K32L2A4S
-
-ifdef VERBOSE
-$(info TOP='$(TOP)')
-$(info )
-
-$(info BSP='$(TOP)/hw/bsp/$(BOARD)')
-$(info )
-
-$(info TOP/SDK_DIR='$(TOP)/$(SDK_DIR)')
-$(info )
-
-$(info MCU_DIR='$(MCU_DIR)')
-$(info )
-endif
-
-DEPS_SUBMODULES += $(SDK_DIR)
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -DCPU_K32L2A41VLH1A \
-  -DCFG_TUSB_MCU=OPT_MCU_K32L2AXX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual
-
-# All source paths should be relative to the top level.
-
-LD_FILE  = $(MCU_DIR)/gcc/frdmk32l2a4s.ld
-LDFLAGS += -L$(TOP)/$(MCU_DIR)/gcc
-
-# Define Recursive Depth wildcard:
-rwildcard=$(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2) $(filter $(subst *,%,$2),$d))
-
-SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	$(MCU_DIR)/gcc/startup_k32l2a41a.c
-
-SRC_C += $(call rwildcard,$(TOP)/$(MCU_DIR)/config,*.c)
-SRC_C += $(call rwildcard,$(TOP)/$(MCU_DIR)/drivers,*.c)
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(MCU_DIR)/CMSIS/ \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/config \
-	$(TOP)/$(MCU_DIR)/drivers
-
-ifdef VERBOSE
-$(info INC = '$(strip $(INC))')
-$(info )
-
-$(info SRC_C = '$(sort $(strip $(SRC_C)))')
-$(info )
-endif
-
-# For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
-
-# For flash-jlink target
-#JLINK_DEVICE = ?
-
-# For flash-pyocd target
-PYOCD_TARGET = K32L2A
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/hw/bsp/frdm_k32l2b/board.mk b/hw/bsp/frdm_k32l2b/board.mk
deleted file mode 100644
index feb0a25f4..000000000
--- a/hw/bsp/frdm_k32l2b/board.mk
+++ /dev/null
@@ -1,51 +0,0 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -DCPU_K32L2B31VLH0A \
-  -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
-
-MCU_DIR = $(SDK_DIR)/devices/K32L2B31A
-
-# All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
-
-SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	$(MCU_DIR)/system_K32L2B31A.c \
-	$(MCU_DIR)/project_template/clock_config.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(SDK_DIR)/CMSIS/Include \
-	$(TOP)/$(SDK_DIR)/drivers/smc \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/gpio \
-	$(TOP)/$(SDK_DIR)/drivers/port \
-	$(TOP)/$(SDK_DIR)/drivers/lpuart \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(MCU_DIR)/project_template \
-
-SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = MKL25Z128xxx4
-
-# For flash-pyocd target
-PYOCD_TARGET = K32L2B
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/hw/bsp/frdm_k32l2a4s/board.h b/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h
similarity index 99%
rename from hw/bsp/frdm_k32l2a4s/board.h
rename to hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h
index 14eefda17..b1f38c997 100644
--- a/hw/bsp/frdm_k32l2a4s/board.h
+++ b/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019, Ha Thach (tinyusb.org)
diff --git a/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk
new file mode 100644
index 000000000..723fb3893
--- /dev/null
+++ b/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk
@@ -0,0 +1,26 @@
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+MCU = K32L2A41A
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
+
+CFLAGS += \
+  -mcpu=cortex-m0plus \
+  -DCPU_K32L2A41VLH1A \
+  -DCFG_TUSB_MCU=OPT_MCU_K32L2AXX
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual
+
+# All source paths should be relative to the top level.
+LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
+
+# For flash-jlink target
+JLINK_DEVICE = K32L2A41xxxxA
+
+# For flash-pyocd target
+PYOCD_TARGET = K32L2A
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
similarity index 99%
rename from hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c
rename to hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
index 47dd0c8ec..80830163b 100644
--- a/hw/bsp/frdm_k32l2a4s/frdm_k32l2a4s.c
+++ b/hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
@@ -25,7 +25,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#include "bsp/board.h"
 #include "board.h"
 #include "fsl_gpio.h"
 #include "fsl_port.h"
diff --git a/hw/bsp/frdm_k32l2b/board.h b/hw/bsp/kinetis/boards/frdm_k32l2b/board.h
similarity index 100%
rename from hw/bsp/frdm_k32l2b/board.h
rename to hw/bsp/kinetis/boards/frdm_k32l2b/board.h
diff --git a/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk
new file mode 100644
index 000000000..66d408c67
--- /dev/null
+++ b/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk
@@ -0,0 +1,26 @@
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+MCU = K32L2B31A
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
+
+CFLAGS += \
+  -mcpu=cortex-m0plus \
+  -DCPU_K32L2B31VLH0A \
+  -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
+
+# All source paths should be relative to the top level.
+LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
+
+# For flash-jlink target
+JLINK_DEVICE = K32L2B31xxxxA
+
+# For flash-pyocd target
+PYOCD_TARGET = K32L2B
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c
similarity index 99%
rename from hw/bsp/frdm_k32l2b/frdm_k32l2b.c
rename to hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c
index 8d2b39500..1566b4e2e 100644
--- a/hw/bsp/frdm_k32l2b/frdm_k32l2b.c
+++ b/hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c
@@ -25,7 +25,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#include "bsp/board.h"
 #include "board.h"
 #include "fsl_gpio.h"
 #include "fsl_port.h"
diff --git a/hw/bsp/frdm_kl25z/board.mk b/hw/bsp/kinetis/boards/frdm_kl25z/board.mk
similarity index 54%
rename from hw/bsp/frdm_kl25z/board.mk
rename to hw/bsp/kinetis/boards/frdm_kl25z/board.mk
index fd616f7ed..5ce6cd51e 100644
--- a/hw/bsp/frdm_kl25z/board.mk
+++ b/hw/bsp/kinetis/boards/frdm_kl25z/board.mk
@@ -1,9 +1,8 @@
 SDK_DIR = hw/mcu/nxp/nxp_sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+MCU = MKL25Z4
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 
 CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
   -mcpu=cortex-m0plus \
   -DCPU_MKL25Z128VLK4 \
   -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX \
@@ -16,29 +15,9 @@ LDFLAGS += \
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls
 
-MCU_DIR = $(SDK_DIR)/devices/MKL25Z4
-
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld
 
-SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	src/portable/nxp/khci/hcd_khci.c \
-	$(MCU_DIR)/system_MKL25Z4.c \
-	$(MCU_DIR)/project_template/clock_config.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(MCU_DIR)/drivers/fsl_gpio.c \
-	$(MCU_DIR)/drivers/fsl_lpsci.c
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(SDK_DIR)/CMSIS/Include \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(MCU_DIR)/project_template \
-
-SRC_S += $(MCU_DIR)/gcc/startup_MKL25Z4.S
-
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
@@ -49,4 +28,4 @@ JLINK_DEVICE = MKL25Z128xxx4
 PYOCD_TARGET = mkl25zl128
 
 # flash using pyocd
-flash: flash-pyocd
+flash: flash-jlink
diff --git a/hw/bsp/frdm_kl25z/frdm_kl25z.c b/hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c
similarity index 100%
rename from hw/bsp/frdm_kl25z/frdm_kl25z.c
rename to hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c
diff --git a/hw/bsp/kinetis/family.mk b/hw/bsp/kinetis/family.mk
new file mode 100644
index 000000000..65767988a
--- /dev/null
+++ b/hw/bsp/kinetis/family.mk
@@ -0,0 +1,46 @@
+DEPS_SUBMODULES += hw/mcu/nxp/nxp_sdk hw/mcu/nxp/mcux-sdk
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -mthumb \
+  -mabi=aapcs \
+
+SRC_C += \
+	src/portable/nxp/khci/dcd_khci.c \
+	src/portable/nxp/khci/hcd_khci.c \
+	$(MCU_DIR)/system_$(MCU).c \
+	$(MCU_DIR)/project_template/clock_config.c \
+	$(MCU_DIR)/drivers/fsl_clock.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(SDK_DIR)/CMSIS/Include \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/project_template \
+	$(TOP)/$(MCU_DIR)/drivers
+
+# mcu-sdk has different driver layout than previous old sdk
+ifeq ($(SDK_DIR),hw/mcu/nxp/mcux-sdk)
+
+SRC_C += \
+	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
+
+INC += \
+	$(TOP)/$(SDK_DIR)/drivers/smc \
+	$(TOP)/$(SDK_DIR)/drivers/common \
+	$(TOP)/$(SDK_DIR)/drivers/gpio \
+	$(TOP)/$(SDK_DIR)/drivers/port \
+	$(TOP)/$(SDK_DIR)/drivers/lpuart \
+
+else
+
+SRC_C += \
+	$(MCU_DIR)/drivers/fsl_gpio.c \
+	$(MCU_DIR)/drivers/fsl_lpsci.c \
+	$(MCU_DIR)/drivers/fsl_uart.c
+
+endif
+
+SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 18e40e1b1..a94e1877f 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -86,6 +86,8 @@
   #define TUP_RHPORT_HIGHSPEED    1 // Port0 HS, Port1 HS
 
 #elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2AXX, OPT_MCU_K32L2BXX)
+  #define TUP_USBIP_CHIPIDEA_FS
+  #define TUP_USBIP_CHIPIDEA_FS_KINETIS
   #define TUP_DCD_ENDPOINT_MAX    16
 
 #elif TU_CHECK_MCU(OPT_MCU_MM32F327X)
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 2678cdca1..52f4145f2 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -26,15 +26,14 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED &&                     \
-  (					   \
-   ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || \
-   ( CFG_TUSB_MCU == OPT_MCU_K32L2AXX ) || \
-   ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX )	   \
-  )
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_FS)
 
-#include "fsl_device_registers.h"
-#define KHCI        USB0
+#ifdef TUP_USBIP_CHIPIDEA_FS_KINETIS
+  #include "fsl_device_registers.h"
+  #define KHCI        USB0
+#else
+  #error "MCU is not supported"
+#endif
 
 #include "device/dcd.h"
 
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 8ff1feff7..27073dce7 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUD_ENABLED &&                     \
+#if CFG_TUH_ENABLED &&                     \
   (					   \
    ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || \
    ( CFG_TUSB_MCU == OPT_MCU_K32L2AXX ) || \

From 1fc203b085ba6ce2edef90e9dcc75ec72eaeb314 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 18 Mar 2023 19:50:24 +0700
Subject: [PATCH 1576/2085] more update to kinetis bsp

---
 docs/reference/supported.rst                  |  2 +-
 hw/bsp/board_mcu.h                            | 14 ++---
 .../boards/frdm_k32l2a4s/board.h              |  0
 .../boards/frdm_k32l2a4s/board.mk             |  6 +--
 .../boards/frdm_k32l2a4s/frdm_k32l2a4s.c      |  0
 .../boards/frdm_k32l2b/board.h                |  0
 .../boards/frdm_k32l2b/board.mk               |  6 +--
 .../boards/frdm_k32l2b/frdm_k32l2b.c          |  0
 .../boards}/kuiic/K32L2B31xxxxA_flash.ld      |  0
 hw/bsp/{ => kinetis_k32/boards}/kuiic/board.h |  0
 hw/bsp/kinetis_k32/boards/kuiic/board.mk      | 26 ++++++++++
 hw/bsp/{ => kinetis_k32/boards}/kuiic/kuiic.c |  2 +-
 hw/bsp/{kinetis => kinetis_k32}/family.mk     | 28 +++-------
 .../boards/frdm_kl25z/board.mk                | 11 ----
 .../boards/frdm_kl25z/frdm_kl25z.c            |  0
 hw/bsp/kinetis_kl/family.mk                   | 37 +++++++++++++
 hw/bsp/kuiic/board.mk                         | 52 -------------------
 src/common/tusb_mcu.h                         |  2 +-
 src/portable/nxp/khci/hcd_khci.c              | 15 +++---
 src/tusb_option.h                             |  8 +--
 20 files changed, 98 insertions(+), 111 deletions(-)
 rename hw/bsp/{kinetis => kinetis_k32}/boards/frdm_k32l2a4s/board.h (100%)
 rename hw/bsp/{kinetis => kinetis_k32}/boards/frdm_k32l2a4s/board.mk (84%)
 rename hw/bsp/{kinetis => kinetis_k32}/boards/frdm_k32l2a4s/frdm_k32l2a4s.c (100%)
 rename hw/bsp/{kinetis => kinetis_k32}/boards/frdm_k32l2b/board.h (100%)
 rename hw/bsp/{kinetis => kinetis_k32}/boards/frdm_k32l2b/board.mk (83%)
 rename hw/bsp/{kinetis => kinetis_k32}/boards/frdm_k32l2b/frdm_k32l2b.c (100%)
 rename hw/bsp/{ => kinetis_k32/boards}/kuiic/K32L2B31xxxxA_flash.ld (100%)
 rename hw/bsp/{ => kinetis_k32/boards}/kuiic/board.h (100%)
 create mode 100644 hw/bsp/kinetis_k32/boards/kuiic/board.mk
 rename hw/bsp/{ => kinetis_k32/boards}/kuiic/kuiic.c (99%)
 rename hw/bsp/{kinetis => kinetis_k32}/family.mk (63%)
 rename hw/bsp/{kinetis => kinetis_kl}/boards/frdm_kl25z/board.mk (60%)
 rename hw/bsp/{kinetis => kinetis_kl}/boards/frdm_kl25z/frdm_kl25z.c (100%)
 create mode 100644 hw/bsp/kinetis_kl/family.mk
 delete mode 100644 hw/bsp/kuiic/board.mk

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index b1e0c0a68..a5d055893 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -253,7 +253,7 @@ Kinetis
 ^^^^^^^
 
 -  `Freedom FRDM-KL25Z <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z>`__
--  `Freedom FRDM-K32L2A  <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/nxp-freedom-platform-for-k32-l2a-mcus:FRDM-K32L2A4S>`__
+-  `Freedom FRDM-K32L2A4S  <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/nxp-freedom-platform-for-k32-l2a-mcus:FRDM-K32L2A4S>`__
 -  `Freedom FRDM-K32L2B3 <https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3>`__
 -  `KUIIC <https://github.com/nxf58843/kuiic>`__
 
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index 920e7d0d9..cd195a19b 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -39,15 +39,15 @@
 //--------------------------------------------------------------------+
 
 // Include order follows OPT_MCU_ number
-#if   CFG_TUSB_MCU == OPT_MCU_LPC11UXX   || CFG_TUSB_MCU == OPT_MCU_LPC13XX    || \
-      CFG_TUSB_MCU == OPT_MCU_LPC15XX    || CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || \
-      CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC18XX    || \
-      CFG_TUSB_MCU == OPT_MCU_LPC40XX    || CFG_TUSB_MCU == OPT_MCU_LPC43XX
+#if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) || \
+      TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX)  || \
+      TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX)
   #include "chip.h"
 
-#elif CFG_TUSB_MCU == OPT_MCU_LPC51UXX || CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
-      CFG_TUSB_MCU == OPT_MCU_LPC55XX  || CFG_TUSB_MCU == OPT_MCU_MKL25ZXX || \
-      CFG_TUSB_MCU == OPT_MCU_K32L2AXX || OPT_MCU_K32L2BXX
+#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX)
+  #include "fsl_device_registers.h"
+
+#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32)
   #include "fsl_device_registers.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
diff --git a/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.h
similarity index 100%
rename from hw/bsp/kinetis/boards/frdm_k32l2a4s/board.h
rename to hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.h
diff --git a/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.mk
similarity index 84%
rename from hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk
rename to hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.mk
index 723fb3893..d96ab58b8 100644
--- a/hw/bsp/kinetis/boards/frdm_k32l2a4s/board.mk
+++ b/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.mk
@@ -1,11 +1,8 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
 MCU = K32L2A41A
-MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 
 CFLAGS += \
   -mcpu=cortex-m0plus \
   -DCPU_K32L2A41VLH1A \
-  -DCFG_TUSB_MCU=OPT_MCU_K32L2AXX
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual
@@ -13,6 +10,9 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
 
+SRC_C += \
+	$(MCU_DIR)/project_template/clock_config.c \
+
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
diff --git a/hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
similarity index 100%
rename from hw/bsp/kinetis/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
rename to hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
diff --git a/hw/bsp/kinetis/boards/frdm_k32l2b/board.h b/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.h
similarity index 100%
rename from hw/bsp/kinetis/boards/frdm_k32l2b/board.h
rename to hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.h
diff --git a/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.mk
similarity index 83%
rename from hw/bsp/kinetis/boards/frdm_k32l2b/board.mk
rename to hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.mk
index 66d408c67..5f8ecbfe4 100644
--- a/hw/bsp/kinetis/boards/frdm_k32l2b/board.mk
+++ b/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.mk
@@ -1,11 +1,8 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
 MCU = K32L2B31A
-MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 
 CFLAGS += \
   -mcpu=cortex-m0plus \
   -DCPU_K32L2B31VLH0A \
-  -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
@@ -13,6 +10,9 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
 
+SRC_C += \
+	$(MCU_DIR)/project_template/clock_config.c \
+
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
diff --git a/hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis_k32/boards/frdm_k32l2b/frdm_k32l2b.c
similarity index 100%
rename from hw/bsp/kinetis/boards/frdm_k32l2b/frdm_k32l2b.c
rename to hw/bsp/kinetis_k32/boards/frdm_k32l2b/frdm_k32l2b.c
diff --git a/hw/bsp/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kinetis_k32/boards/kuiic/K32L2B31xxxxA_flash.ld
similarity index 100%
rename from hw/bsp/kuiic/K32L2B31xxxxA_flash.ld
rename to hw/bsp/kinetis_k32/boards/kuiic/K32L2B31xxxxA_flash.ld
diff --git a/hw/bsp/kuiic/board.h b/hw/bsp/kinetis_k32/boards/kuiic/board.h
similarity index 100%
rename from hw/bsp/kuiic/board.h
rename to hw/bsp/kinetis_k32/boards/kuiic/board.h
diff --git a/hw/bsp/kinetis_k32/boards/kuiic/board.mk b/hw/bsp/kinetis_k32/boards/kuiic/board.mk
new file mode 100644
index 000000000..29a12e982
--- /dev/null
+++ b/hw/bsp/kinetis_k32/boards/kuiic/board.mk
@@ -0,0 +1,26 @@
+MCU = K32L2B31A
+
+# This board uses TinyUF2 for updates
+UF2_FAMILY_ID = 0x7f83e793
+
+CFLAGS += \
+  -mcpu=cortex-m0plus \
+  -DCPU_K32L2B31VLH0A \
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/K32L2B31xxxxA_flash.ld
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
+
+# For flash-jlink target
+JLINK_DEVICE = K32L2B31xxxxA
+
+# For flash-pyocd target
+PYOCD_TARGET = K32L2B
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/kuiic/kuiic.c b/hw/bsp/kinetis_k32/boards/kuiic/kuiic.c
similarity index 99%
rename from hw/bsp/kuiic/kuiic.c
rename to hw/bsp/kinetis_k32/boards/kuiic/kuiic.c
index 97677d47a..f9002a6d3 100644
--- a/hw/bsp/kuiic/kuiic.c
+++ b/hw/bsp/kinetis_k32/boards/kuiic/kuiic.c
@@ -25,7 +25,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#include "bsp/board.h"
 #include "board.h"
 #include "fsl_smc.h"
 #include "fsl_gpio.h"
diff --git a/hw/bsp/kinetis/family.mk b/hw/bsp/kinetis_k32/family.mk
similarity index 63%
rename from hw/bsp/kinetis/family.mk
rename to hw/bsp/kinetis_k32/family.mk
index 65767988a..f89138b72 100644
--- a/hw/bsp/kinetis/family.mk
+++ b/hw/bsp/kinetis_k32/family.mk
@@ -1,46 +1,32 @@
-DEPS_SUBMODULES += hw/mcu/nxp/nxp_sdk hw/mcu/nxp/mcux-sdk
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+DEPS_SUBMODULES += $(SDK_DIR)
 
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
 
 CFLAGS += \
   -mthumb \
   -mabi=aapcs \
+	-DCFG_TUSB_MCU=OPT_MCU_KINETIS_K32
 
 SRC_C += \
 	src/portable/nxp/khci/dcd_khci.c \
 	src/portable/nxp/khci/hcd_khci.c \
 	$(MCU_DIR)/system_$(MCU).c \
-	$(MCU_DIR)/project_template/clock_config.c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
+	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(SDK_DIR)/CMSIS/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/project_template \
-	$(TOP)/$(MCU_DIR)/drivers
-
-# mcu-sdk has different driver layout than previous old sdk
-ifeq ($(SDK_DIR),hw/mcu/nxp/mcux-sdk)
-
-SRC_C += \
-	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
-
-INC += \
+	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/smc \
 	$(TOP)/$(SDK_DIR)/drivers/common \
 	$(TOP)/$(SDK_DIR)/drivers/gpio \
 	$(TOP)/$(SDK_DIR)/drivers/port \
 	$(TOP)/$(SDK_DIR)/drivers/lpuart \
 
-else
-
-SRC_C += \
-	$(MCU_DIR)/drivers/fsl_gpio.c \
-	$(MCU_DIR)/drivers/fsl_lpsci.c \
-	$(MCU_DIR)/drivers/fsl_uart.c
-
-endif
-
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
diff --git a/hw/bsp/kinetis/boards/frdm_kl25z/board.mk b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
similarity index 60%
rename from hw/bsp/kinetis/boards/frdm_kl25z/board.mk
rename to hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
index 5ce6cd51e..affe864fb 100644
--- a/hw/bsp/kinetis/boards/frdm_kl25z/board.mk
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
@@ -1,26 +1,15 @@
-SDK_DIR = hw/mcu/nxp/nxp_sdk
 MCU = MKL25Z4
-MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 
 CFLAGS += \
-  -mcpu=cortex-m0plus \
   -DCPU_MKL25Z128VLK4 \
-  -DCFG_TUSB_MCU=OPT_MCU_MKL25ZXX \
   -DCFG_EXAMPLE_VIDEO_READONLY
 
-LDFLAGS += \
-  -Wl,--defsym,__stack_size__=0x400 \
-  -Wl,--defsym,__heap_size__=0
-
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls
 
 # All source paths should be relative to the top level.
 LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
 # For flash-jlink target
 JLINK_DEVICE = MKL25Z128xxx4
 
diff --git a/hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c b/hw/bsp/kinetis_kl/boards/frdm_kl25z/frdm_kl25z.c
similarity index 100%
rename from hw/bsp/kinetis/boards/frdm_kl25z/frdm_kl25z.c
rename to hw/bsp/kinetis_kl/boards/frdm_kl25z/frdm_kl25z.c
diff --git a/hw/bsp/kinetis_kl/family.mk b/hw/bsp/kinetis_kl/family.mk
new file mode 100644
index 000000000..e805d6dae
--- /dev/null
+++ b/hw/bsp/kinetis_kl/family.mk
@@ -0,0 +1,37 @@
+SDK_DIR = hw/mcu/nxp/nxp_sdk
+DEPS_SUBMODULES += $(SDK_DIR)
+
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0plus \
+  -DCFG_TUSB_MCU=OPT_MCU_KINETIS_KL \
+
+LDFLAGS += \
+  -Wl,--defsym,__stack_size__=0x400 \
+  -Wl,--defsym,__heap_size__=0
+
+SRC_C += \
+	src/portable/nxp/khci/dcd_khci.c \
+	src/portable/nxp/khci/hcd_khci.c \
+	$(MCU_DIR)/system_$(MCU).c \
+	$(MCU_DIR)/project_template/clock_config.c \
+	$(MCU_DIR)/drivers/fsl_clock.c \
+	$(MCU_DIR)/drivers/fsl_gpio.c \
+	$(MCU_DIR)/drivers/fsl_lpsci.c \
+	$(MCU_DIR)/drivers/fsl_uart.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/$(SDK_DIR)/CMSIS/Include \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/project_template \
+	$(TOP)/$(MCU_DIR)/drivers
+
+SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/hw/bsp/kuiic/board.mk b/hw/bsp/kuiic/board.mk
deleted file mode 100644
index cb3459586..000000000
--- a/hw/bsp/kuiic/board.mk
+++ /dev/null
@@ -1,52 +0,0 @@
-SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR) tools/uf2
-
-# This board uses TinyUF2 for updates
-UF2_FAMILY_ID = 0x7f83e793
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -DCPU_K32L2B31VLH0A \
-  -DCFG_TUSB_MCU=OPT_MCU_K32L2BXX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
-
-MCU_DIR = $(SDK_DIR)/devices/K32L2B31A
-
-# All source paths should be relative to the top level.
-LD_FILE = /hw/bsp/$(BOARD)/K32L2B31xxxxA_flash.ld
-
-SRC_C += \
-	src/portable/nxp/khci/dcd_khci.c \
-	$(MCU_DIR)/system_K32L2B31A.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
-
-INC += \
-	$(TOP)/hw/bsp/$(BOARD) \
-	$(TOP)/$(SDK_DIR)/CMSIS/Include \
-	$(TOP)/$(SDK_DIR)/drivers/smc \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/gpio \
-	$(TOP)/$(SDK_DIR)/drivers/port \
-	$(TOP)/$(SDK_DIR)/drivers/lpuart \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers
-
-SRC_S += $(MCU_DIR)/gcc/startup_K32L2B31A.S
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = MKL25Z128xxx4
-
-# For flash-pyocd target
-PYOCD_TARGET = K32L2B
-
-# flash using pyocd
-flash: flash-pyocd
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index a94e1877f..b903abeca 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -85,7 +85,7 @@
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1 // Port0 HS, Port1 HS
 
-#elif TU_CHECK_MCU(OPT_MCU_MKL25ZXX, OPT_MCU_K32L2AXX, OPT_MCU_K32L2BXX)
+#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32)
   #define TUP_USBIP_CHIPIDEA_FS
   #define TUP_USBIP_CHIPIDEA_FS_KINETIS
   #define TUP_DCD_ENDPOINT_MAX    16
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 27073dce7..6d25cd862 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -26,15 +26,14 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED &&                     \
-  (					   \
-   ( CFG_TUSB_MCU == OPT_MCU_MKL25ZXX ) || \
-   ( CFG_TUSB_MCU == OPT_MCU_K32L2AXX ) || \
-   ( CFG_TUSB_MCU == OPT_MCU_K32L2BXX )	   \
-  )
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_CHIPIDEA_FS)
 
-#include "fsl_device_registers.h"
-#define KHCI        USB0
+#ifdef TUP_USBIP_CHIPIDEA_FS_KINETIS
+  #include "fsl_device_registers.h"
+  #define KHCI        USB0
+#else
+  #error "MCU is not supported"
+#endif
 
 #include "host/hcd.h"
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 5a234e357..c679f2f12 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -117,9 +117,11 @@
 #define OPT_MCU_RP2040           1100 ///< Raspberry Pi RP2040
 
 // NXP Kinetis
-#define OPT_MCU_MKL25ZXX         1200 ///< NXP MKL25Zxx
-#define OPT_MCU_K32L2BXX         1201 ///< NXP K32L2Bxx
-#define OPT_MCU_K32L2AXX         1202 ///< NXP K32L2Axx
+#define OPT_MCU_KINETIS_KL       1200 ///< NXP KL series
+#define OPT_MCU_KINETIS_K32      1201 ///< NXP K32 series
+
+#define OPT_MCU_MKL25ZXX         1200 ///< Alias to KL (obsolete)
+#define OPT_MCU_K32L2BXX         1201 ///< Alias to K32 (obsolete)
 
 // Silabs
 #define OPT_MCU_EFM32GG          1300 ///< Silabs EFM32GG

From bbe550efa0d99c18721c230b3a0a45e8ac6cd28e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 18 Mar 2023 20:19:37 +0700
Subject: [PATCH 1577/2085] add kinetis family to ci

---
 .github/workflows/build_arm.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 7aecb8386..f63f637b1 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -34,6 +34,7 @@ jobs:
         # Alphabetical order
         - 'broadcom_32bit'
         - 'imxrt'
+        - 'kinetis_k32 kinetis_kl'
         - 'lpc15 lpc18'
         - 'lpc54 lpc55'
         - 'mm32 msp432e4'

From ec0f25d095a670d24578e39145729b2eb3028c28 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 18 Mar 2023 20:30:49 +0700
Subject: [PATCH 1578/2085] fix ci with kl25z

---
 examples/device/net_lwip_webserver/skip.txt  | 1 +
 hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt
index b0e5235ac..77c7ec63a 100644
--- a/examples/device/net_lwip_webserver/skip.txt
+++ b/examples/device/net_lwip_webserver/skip.txt
@@ -8,3 +8,4 @@ mcu:MKL25ZXX
 family:broadcom_64bit
 family:broadcom_32bit
 board:curiosity_nano
+board:frdm_kl25z
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
index affe864fb..0d0bceaa4 100644
--- a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
@@ -2,7 +2,8 @@ MCU = MKL25Z4
 
 CFLAGS += \
   -DCPU_MKL25Z128VLK4 \
-  -DCFG_EXAMPLE_VIDEO_READONLY
+  -DCFG_EXAMPLE_VIDEO_READONLY \
+  -DCFG_EXAMPLE_MSC_READONLY
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls

From 3944f1c4dab07569cb6fa781facd6afc20bbf35d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 11:28:06 +0700
Subject: [PATCH 1579/2085] group same5x

---
 .codespell/ignore-words.txt                   |  1 +
 .github/workflows/build_arm.yml               |  2 +-
 hw/bsp/d5035_01/board.mk                      | 61 -------------------
 hw/bsp/same54xplainedpro/board.mk             | 48 ---------------
 hw/bsp/same5x/boards/d5035_01/board.mk        | 21 +++++++
 .../{ => same5x/boards}/d5035_01/d5035_01.c   |  0
 .../boards}/d5035_01/same51j19a_flash.ld      |  0
 hw/bsp/same5x/boards/same54_xplained/board.mk | 12 ++++
 .../boards/same54_xplained/same54_xplained.c} |  0
 .../same54_xplained}/same54p20a_flash.ld      |  0
 .../same54_xplained}/same54p20a_sram.ld       |  0
 hw/bsp/same5x/family.mk                       | 42 +++++++++++++
 12 files changed, 77 insertions(+), 110 deletions(-)
 delete mode 100644 hw/bsp/d5035_01/board.mk
 delete mode 100644 hw/bsp/same54xplainedpro/board.mk
 create mode 100644 hw/bsp/same5x/boards/d5035_01/board.mk
 rename hw/bsp/{ => same5x/boards}/d5035_01/d5035_01.c (100%)
 rename hw/bsp/{ => same5x/boards}/d5035_01/same51j19a_flash.ld (100%)
 create mode 100644 hw/bsp/same5x/boards/same54_xplained/board.mk
 rename hw/bsp/{same54xplainedpro/same54xplainedpro.c => same5x/boards/same54_xplained/same54_xplained.c} (100%)
 rename hw/bsp/{same54xplainedpro => same5x/boards/same54_xplained}/same54p20a_flash.ld (100%)
 rename hw/bsp/{same54xplainedpro => same5x/boards/same54_xplained}/same54p20a_sram.ld (100%)
 create mode 100644 hw/bsp/same5x/family.mk

diff --git a/.codespell/ignore-words.txt b/.codespell/ignore-words.txt
index fc14fe417..5c89bae1c 100644
--- a/.codespell/ignore-words.txt
+++ b/.codespell/ignore-words.txt
@@ -9,3 +9,4 @@ te
 attch
 endianess
 pris
+busses
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index f63f637b1..905cc4f9a 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -41,7 +41,7 @@ jobs:
         - 'nrf'
         - 'ra'
         - 'rp2040'
-        - 'samd11'
+        - 'samd11 same5x'
         - 'samd21'
         - 'samd51'
         - 'saml2x'
diff --git a/hw/bsp/d5035_01/board.mk b/hw/bsp/d5035_01/board.mk
deleted file mode 100644
index fc196b339..000000000
--- a/hw/bsp/d5035_01/board.mk
+++ /dev/null
@@ -1,61 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-HWREV ?= 1
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mlong-calls \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -D__SAME51J19A__ \
-  -DCONF_CPU_FREQUENCY=80000000 \
-  -DCONF_GCLK_USB_FREQUENCY=48000000 \
-  -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
-  -DD5035_01=1 \
-  -DBOARD_NAME="\"D5035-01\"" \
-  -DSVC_Handler=SVCall_Handler \
-  -DHWREV=$(HWREV)
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/same51j19a_flash.ld
-
-SRC_C += \
-  src/portable/microchip/samd/dcd_samd.c \
-  hw/mcu/microchip/same51/gcc/gcc/startup_same51.c \
-  hw/mcu/microchip/same51/gcc/system_same51.c
-
-ifdef SYSCALLS
-ifneq ($(SYSCALLS),0)
-  SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c
-endif
-endif
-
-ifdef LOG
-ifneq ($(LOG),0)
-  SRC_C += hw/mcu/microchip/same51/hal/utils/src/utils_syscalls.c
-endif
-endif
-
-INC += \
-	$(TOP)/hw/mcu/microchip/same51/ \
-	$(TOP)/hw/mcu/microchip/same51/config \
-	$(TOP)/hw/mcu/microchip/same51/include \
-	$(TOP)/hw/mcu/microchip/same51/hal/include \
-	$(TOP)/hw/mcu/microchip/same51/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/same51/hpl/port \
-	$(TOP)/hw/mcu/microchip/same51/hri \
-	$(TOP)/hw/mcu/microchip/same51/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAME51J19
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/same54xplainedpro/board.mk b/hw/bsp/same54xplainedpro/board.mk
deleted file mode 100644
index 1c6732231..000000000
--- a/hw/bsp/same54xplainedpro/board.mk
+++ /dev/null
@@ -1,48 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/microchip
-
-CONF_CPU_FREQUENCY ?= 48000000
-
-CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mlong-calls \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -D__SAME54P20A__ \
-  -DCONF_CPU_FREQUENCY=$(CONF_CPU_FREQUENCY) \
-  -DCFG_TUSB_MCU=OPT_MCU_SAME5X \
-  -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
-
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/same54p20a_flash.ld
-
-SRC_C += \
-  src/portable/microchip/samd/dcd_samd.c \
-  hw/mcu/microchip/same54/gcc/gcc/startup_same54.c \
-  hw/mcu/microchip/same54/gcc/system_same54.c \
-  hw/mcu/microchip/same54/hal/utils/src/utils_syscalls.c
-
-INC += \
-	$(TOP)/hw/mcu/microchip/same54/ \
-	$(TOP)/hw/mcu/microchip/same54/config \
-	$(TOP)/hw/mcu/microchip/same54/include \
-	$(TOP)/hw/mcu/microchip/same54/hal/include \
-	$(TOP)/hw/mcu/microchip/same54/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/same54/hpl/port \
-	$(TOP)/hw/mcu/microchip/same54/hri \
-	$(TOP)/hw/mcu/microchip/same54/CMSIS/Include
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAME54P20
-
-# flash using edbg from https://github.com/ataradov/edbg
-flash: $(BUILD)/$(PROJECT).bin
-	edbg --verbose -t same54 -pv -f $<
diff --git a/hw/bsp/same5x/boards/d5035_01/board.mk b/hw/bsp/same5x/boards/d5035_01/board.mk
new file mode 100644
index 000000000..c53411bb8
--- /dev/null
+++ b/hw/bsp/same5x/boards/d5035_01/board.mk
@@ -0,0 +1,21 @@
+MCU = same51
+
+HWREV ?= 1
+
+CFLAGS += \
+  -D__SAME51J19A__ \
+  -DCONF_CPU_FREQUENCY=80000000 \
+  -DCONF_GCLK_USB_FREQUENCY=48000000 \
+  -DD5035_01=1 \
+  -DBOARD_NAME="\"D5035-01\"" \
+  -DSVC_Handler=SVCall_Handler \
+  -DHWREV=$(HWREV)
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/same51j19a_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAME51J19
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/d5035_01/d5035_01.c b/hw/bsp/same5x/boards/d5035_01/d5035_01.c
similarity index 100%
rename from hw/bsp/d5035_01/d5035_01.c
rename to hw/bsp/same5x/boards/d5035_01/d5035_01.c
diff --git a/hw/bsp/d5035_01/same51j19a_flash.ld b/hw/bsp/same5x/boards/d5035_01/same51j19a_flash.ld
similarity index 100%
rename from hw/bsp/d5035_01/same51j19a_flash.ld
rename to hw/bsp/same5x/boards/d5035_01/same51j19a_flash.ld
diff --git a/hw/bsp/same5x/boards/same54_xplained/board.mk b/hw/bsp/same5x/boards/same54_xplained/board.mk
new file mode 100644
index 000000000..41cf95bfc
--- /dev/null
+++ b/hw/bsp/same5x/boards/same54_xplained/board.mk
@@ -0,0 +1,12 @@
+MCU = same54
+
+CFLAGS += \
+  -DCONF_CPU_FREQUENCY=48000000 \
+  -D__SAME54P20A__ \
+  -DBOARD_NAME="\"Microchip SAM E54 Xplained Pro\""
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/same54p20a_flash.ld
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAME54P20
diff --git a/hw/bsp/same54xplainedpro/same54xplainedpro.c b/hw/bsp/same5x/boards/same54_xplained/same54_xplained.c
similarity index 100%
rename from hw/bsp/same54xplainedpro/same54xplainedpro.c
rename to hw/bsp/same5x/boards/same54_xplained/same54_xplained.c
diff --git a/hw/bsp/same54xplainedpro/same54p20a_flash.ld b/hw/bsp/same5x/boards/same54_xplained/same54p20a_flash.ld
similarity index 100%
rename from hw/bsp/same54xplainedpro/same54p20a_flash.ld
rename to hw/bsp/same5x/boards/same54_xplained/same54p20a_flash.ld
diff --git a/hw/bsp/same54xplainedpro/same54p20a_sram.ld b/hw/bsp/same5x/boards/same54_xplained/same54p20a_sram.ld
similarity index 100%
rename from hw/bsp/same54xplainedpro/same54p20a_sram.ld
rename to hw/bsp/same5x/boards/same54_xplained/same54p20a_sram.ld
diff --git a/hw/bsp/same5x/family.mk b/hw/bsp/same5x/family.mk
new file mode 100644
index 000000000..7f8692c97
--- /dev/null
+++ b/hw/bsp/same5x/family.mk
@@ -0,0 +1,42 @@
+DEPS_SUBMODULES += hw/mcu/microchip
+
+SDK_DIR = hw/mcu/microchip/$(MCU)
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -mthumb \
+  -mabi=aapcs \
+  -mlong-calls \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_SAME5X
+
+# suppress warning caused by vendor mcu driver
+#CFLAGS += -Wno-error=cast-qual
+
+SRC_C += \
+  src/portable/microchip/samd/dcd_samd.c \
+  $(SDK_DIR)/gcc/gcc/startup_$(MCU).c \
+  $(SDK_DIR)/gcc/system_$(MCU).c \
+  $(SDK_DIR)/hal/utils/src/utils_syscalls.c
+
+INC += \
+	$(TOP)/$(SDK_DIR) \
+	$(TOP)/$(SDK_DIR)/config \
+	$(TOP)/$(SDK_DIR)/include \
+	$(TOP)/$(SDK_DIR)/hal/include \
+	$(TOP)/$(SDK_DIR)/hal/utils/include \
+	$(TOP)/$(SDK_DIR)/hpl/port \
+	$(TOP)/$(SDK_DIR)/hri \
+	$(TOP)/$(SDK_DIR)/CMSIS/Include
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
+
+# flash using edbg from https://github.com/ataradov/edbg
+flash-edbg: $(BUILD)/$(PROJECT).bin
+	edbg --verbose -t $(MCU) -pv -f $<
+
+flash: flash-edbg

From ab0da3c30baab6eb63e55217f2b4d5a719fb86e4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 12:01:33 +0700
Subject: [PATCH 1580/2085] group stm32l0

---
 .github/workflows/build_arm.yml               |   2 +-
 hw/bsp/stm32l0/boards/stm32l052dap52/board.mk |   3 +-
 .../stm32l0538disco/STM32L053C8Tx_FLASH.ld    |   0
 .../boards/stm32l0538disco/board.h}           | 147 ++------
 .../stm32l0/boards/stm32l0538disco/board.mk   |  14 +
 hw/bsp/stm32l0/family.c                       |  32 +-
 hw/bsp/stm32l0/family.mk                      |  13 +-
 hw/bsp/stm32l0/stm32l0xx_hal_conf.h           |  90 +++--
 hw/bsp/stm32l0538disco/board.mk               |  54 ---
 hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h   | 331 ------------------
 10 files changed, 130 insertions(+), 556 deletions(-)
 rename hw/bsp/{ => stm32l0/boards}/stm32l0538disco/STM32L053C8Tx_FLASH.ld (100%)
 rename hw/bsp/{stm32l0538disco/stm32l0538disco.c => stm32l0/boards/stm32l0538disco/board.h} (51%)
 create mode 100644 hw/bsp/stm32l0/boards/stm32l0538disco/board.mk
 delete mode 100644 hw/bsp/stm32l0538disco/board.mk
 delete mode 100644 hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 905cc4f9a..3abfd50a8 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -50,7 +50,7 @@ jobs:
         - 'stm32f7'
         - 'stm32g4 stm32wb'
         - 'stm32h7'
-        - 'stm32l4'
+        - 'stm32l0 stm32l4'
         - 'tm4c123 xmc4000'
     steps:
     - name: Setup Python
diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk b/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
index 84662344d..0b1348474 100644
--- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
+++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.mk
@@ -1,4 +1,5 @@
-CFLAGS += -DSTM32L052xx -DCFG_EXAMPLE_VIDEO_READONLY
+CFLAGS += \
+	-DSTM32L052xx
 
 LD_FILE = $(BOARD_PATH)/STM32L052K8Ux_FLASH.ld
 
diff --git a/hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld b/hw/bsp/stm32l0/boards/stm32l0538disco/STM32L053C8Tx_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32l0538disco/STM32L053C8Tx_FLASH.ld
rename to hw/bsp/stm32l0/boards/stm32l0538disco/STM32L053C8Tx_FLASH.ld
diff --git a/hw/bsp/stm32l0538disco/stm32l0538disco.c b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h
similarity index 51%
rename from hw/bsp/stm32l0538disco/stm32l0538disco.c
rename to hw/bsp/stm32l0/boards/stm32l0538disco/board.h
index 46f6f0ff6..0722e3102 100644
--- a/hw/bsp/stm32l0538disco/stm32l0538disco.c
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h
@@ -1,7 +1,7 @@
 /*
  * The MIT License (MIT)
  *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -24,45 +24,35 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
-#include "stm32l0xx_hal.h"
+#ifndef BOARD_H_
+#define BOARD_H_
 
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
-  tud_int_handler(0);
-}
+#ifdef __cplusplus
+ extern "C" {
+#endif
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM
-//--------------------------------------------------------------------+
+// LED
 #define LED_PORT              GPIOA
 #define LED_PIN               GPIO_PIN_5
 #define LED_STATE_ON          1
 
+// Button
 #define BUTTON_PORT           GPIOA
 #define BUTTON_PIN            GPIO_PIN_0
 #define BUTTON_STATE_ACTIVE   1
 
-/**
-  * @brief  System Clock Configuration
-  *         The system Clock is configured as follow:
-  *         HSI48 used as USB clock source
-  *              - System Clock source            = HSI
-  *              - HSI Frequency(Hz)              = 16000000
-  *              - SYSCLK(Hz)                     = 16000000
-  *              - HCLK(Hz)                       = 16000000
-  *              - AHB Prescaler                  = 1
-  *              - APB1 Prescaler                 = 1
-  *              - APB2 Prescaler                 = 1
-  *              - Flash Latency(WS)              = 0
-  *              - Main regulator output voltage  = Scale1 mode
-  * @param  None
-  * @retval None
-  */
-static void SystemClock_Config(void)
+// UART
+//#define UART_DEV              USART2
+//#define UART_CLK_EN           __HAL_RCC_USART2_CLK_ENABLE
+//#define UART_GPIO_PORT        GPIOA
+//#define UART_GPIO_AF          GPIO_AF4_USART2
+//#define UART_TX_PIN           GPIO_PIN_2
+//#define UART_RX_PIN           GPIO_PIN_3
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_stm32l0_clock_init(void)
 {
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_OscInitTypeDef RCC_OscInitStruct;
@@ -108,99 +98,12 @@ static void SystemClock_Config(void)
   HAL_RCCEx_CRSConfig (&RCC_CRSInitStruct);
 }
 
-void board_init(void)
+static inline void board_vbus_sense_init(void)
 {
-  SystemClock_Config();
+}
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
-  // 1ms tick timer
-  SysTick_Config(SystemCoreClock / 1000);
-#elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  //NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#ifdef __cplusplus
+ }
 #endif
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
-
-  // LED
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
-
-  board_led_write(false);
-
-  // Button
-  //__HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
-
-  // USB
-  /* Configure DM DP Pins */
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* Enable USB FS Clock */
-  __HAL_RCC_USB_CLK_ENABLE();
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
-}
-
-uint32_t board_button_read(void)
-{
-  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
-}
-
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS  == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
-  HAL_IncTick();
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-void HardFault_Handler (void)
-{
-  asm("bkpt");
-}
-
-// Required by __libc_init_array in startup code if we are compiling using
-// -nostdlib/-nostartfiles.
-void _init(void)
-{
-
-}
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk b/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk
new file mode 100644
index 000000000..deed519ba
--- /dev/null
+++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += \
+  -DSTM32L053xx
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32L053C8Tx_FLASH.ld
+
+SRC_S += \
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l053xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = STM32L053R8
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c
index 6bce88b39..89749fb50 100644
--- a/hw/bsp/stm32l0/family.c
+++ b/hw/bsp/stm32l0/family.c
@@ -39,21 +39,14 @@ void USB_IRQHandler(void)
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
+#ifdef UART_DEV
 UART_HandleTypeDef UartHandle;
+#endif
 
 void board_init(void)
 {
   board_stm32l0_clock_init();
 
-  // Enable All GPIOs clocks
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-
-  // Enable UART Clock
-  UART_CLK_EN();
-
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
@@ -66,6 +59,12 @@ void board_init(void)
   NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+
   // LED
   GPIO_InitTypeDef  GPIO_InitStruct;
   GPIO_InitStruct.Pin = LED_PIN;
@@ -74,6 +73,8 @@ void board_init(void)
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
 
+  board_led_write(false);
+
   // Button
   GPIO_InitStruct.Pin = BUTTON_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
@@ -81,7 +82,10 @@ void board_init(void)
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 
-  // Uart
+#ifdef UART_DEV
+  // Enable UART Clock
+  UART_CLK_EN();
+
   GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
   GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
   GPIO_InitStruct.Pull      = GPIO_PULLUP;
@@ -98,13 +102,14 @@ void board_init(void)
   UartHandle.Init.Mode       = UART_MODE_TX_RX;
   UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
   HAL_UART_Init(&UartHandle);
+#endif
 
   // USB Pins
   // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
   GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
   // USB Clock enable
@@ -133,8 +138,13 @@ int board_uart_read(uint8_t* buf, int len)
 
 int board_uart_write(void const * buf, int len)
 {
+#ifdef UART_DEV
   HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
+#else
+  (void) buf; (void) len;
+  return 0;
+#endif
 }
 
 #if CFG_TUSB_OS  == OPT_OS_NONE
diff --git a/hw/bsp/stm32l0/family.mk b/hw/bsp/stm32l0/family.mk
index 67a5c69b8..f069ae8f0 100644
--- a/hw/bsp/stm32l0/family.mk
+++ b/hw/bsp/stm32l0/family.mk
@@ -1,5 +1,8 @@
 ST_FAMILY = l0
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+DEPS_SUBMODULES += \
+	lib/CMSIS_5 \
+	hw/mcu/st/cmsis_device_$(ST_FAMILY) \
+	hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
@@ -17,8 +20,12 @@ CFLAGS += \
   -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L0
 
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-align -Wno-error=maybe-uninitialized
+# mcu driver cause following warnings
+CFLAGS += \
+	-Wno-error=unused-parameter \
+	-Wno-error=redundant-decls \
+	-Wno-error=cast-align \
+	-Wno-error=maybe-uninitialized
 
 SRC_C += \
   src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
diff --git a/hw/bsp/stm32l0/stm32l0xx_hal_conf.h b/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
index e3a131043..fd109bc8c 100644
--- a/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
+++ b/hw/bsp/stm32l0/stm32l0xx_hal_conf.h
@@ -2,19 +2,41 @@
   ******************************************************************************
   * @file    stm32l0xx_hal_conf.h
   * @author  MCD Application Team
-  * @brief   HAL configuration template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l0xx_hal_conf.h.
+  * @brief   HAL configuration file.
   ******************************************************************************
-  * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2016 STMicroelectronics International N.V. All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted, provided that the following conditions are met:
+  *
+  * 1. Redistribution of source code must retain the above copyright notice,
+  *    this list of conditions and the following disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright notice,
+  *    this list of conditions and the following disclaimer in the documentation
+  *    and/or other materials provided with the distribution.
+  * 3. Neither the name of STMicroelectronics nor the names of other
+  *    contributors to this software may be used to endorse or promote products
+  *    derived from this software without specific written permission.
+  * 4. This software, including modifications and/or derivative works of this
+  *    software, must execute solely and exclusively on microcontroller or
+  *    microprocessor devices manufactured by or for STMicroelectronics.
+  * 5. Redistribution and use of this software other than as permitted under
+  *    this license is void and will automatically terminate your rights under
+  *    this license.
+  *
+  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
+  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
+  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
+  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
   */
@@ -35,35 +57,37 @@
   * @brief This is the list of modules to be used in the HAL driver
   */
 #define HAL_MODULE_ENABLED
-/*#define HAL_ADC_MODULE_ENABLED */
-/*#define HAL_COMP_MODULE_ENABLED */
-/*#define HAL_CRC_MODULE_ENABLED */
-/*#define HAL_CRYP_MODULE_ENABLED */
-/*#define HAL_DAC_MODULE_ENABLED */
+// #define HAL_ADC_MODULE_ENABLED
+/* #define HAL_COMP_MODULE_ENABLED */
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
 #define HAL_DMA_MODULE_ENABLED
-/*#define HAL_FIREWALL_MODULE_ENABLED */
+/* #define HAL_FIREWALL_MODULE_ENABLED */
 #define HAL_FLASH_MODULE_ENABLED
 #define HAL_GPIO_MODULE_ENABLED
-/*#define HAL_I2C_MODULE_ENABLED */
-/*#define HAL_I2S_MODULE_ENABLED */
-/*#define HAL_IWDG_MODULE_ENABLED */
-/*#define HAL_LCD_MODULE_ENABLED */
-/*#define HAL_LPTIM_MODULE_ENABLED */
+/* #define HAL_I2C_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LCD_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
 #define HAL_PWR_MODULE_ENABLED
 #define HAL_RCC_MODULE_ENABLED
-/*#define HAL_RNG_MODULE_ENABLED */
-/*#define HAL_RTC_MODULE_ENABLED */
-/*#define HAL_SPI_MODULE_ENABLED */
-/*#define HAL_TIM_MODULE_ENABLED */
-/*#define HAL_TSC_MODULE_ENABLED */
+//#define HAL_RNG_MODULE_ENABLED
+/* #define HAL_RTC_MODULE_ENABLED */
+//#define HAL_SPI_MODULE_ENABLED
+/* #define HAL_TIM_MODULE_ENABLED */
+/* #define HAL_TSC_MODULE_ENABLED */
 #define HAL_UART_MODULE_ENABLED
-/*#define HAL_USART_MODULE_ENABLED */
-/*#define HAL_IRDA_MODULE_ENABLED */
-/*#define HAL_SMARTCARD_MODULE_ENABLED */
-/*#define HAL_SMBUS_MODULE_ENABLED */
-/*#define HAL_WWDG_MODULE_ENABLED */
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+//#define HAL_PCD_MODULE_ENABLED
 #define HAL_CORTEX_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_PCD_MODULE_ENABLED */
+
 
 /* ########################## Oscillator Values adaptation ####################*/
 /**
@@ -322,7 +346,7 @@
   */
   #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
 /* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
+  void assert_failed(uint8_t *file, uint32_t line);
 #else
   #define assert_param(expr) ((void)0U)
 #endif /* USE_FULL_ASSERT */
diff --git a/hw/bsp/stm32l0538disco/board.mk b/hw/bsp/stm32l0538disco/board.mk
deleted file mode 100644
index 72e887adf..000000000
--- a/hw/bsp/stm32l0538disco/board.mk
+++ /dev/null
@@ -1,54 +0,0 @@
-ST_FAMILY = l0
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -mfloat-abi=soft \
-  -nostdlib -nostartfiles \
-  -DSTM32L053xx \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_EXAMPLE_VIDEO_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32L0
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=maybe-uninitialized -Wno-error=redundant-decls
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32L053C8Tx_FLASH.ld
-
-SRC_C += \
-  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
-  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
-
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l053xx.s
-
-INC += \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc \
-  $(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = STM32L053R8
-
-# Path to STM32 Cube Programmer CLI, should be added into system path
-STM32Prog = STM32_Programmer_CLI
-
-# flash target using on-board stlink
-flash: $(BUILD)/$(PROJECT).elf
-	$(STM32Prog) --connect port=swd --write $< --go
diff --git a/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h b/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h
deleted file mode 100644
index a917214c3..000000000
--- a/hw/bsp/stm32l0538disco/stm32l0xx_hal_conf.h
+++ /dev/null
@@ -1,331 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  *
-  * Copyright (c) 2016 STMicroelectronics International N.V. All rights reserved.
-  *
-  * Redistribution and use in source and binary forms, with or without
-  * modification, are permitted, provided that the following conditions are met:
-  *
-  * 1. Redistribution of source code must retain the above copyright notice,
-  *    this list of conditions and the following disclaimer.
-  * 2. Redistributions in binary form must reproduce the above copyright notice,
-  *    this list of conditions and the following disclaimer in the documentation
-  *    and/or other materials provided with the distribution.
-  * 3. Neither the name of STMicroelectronics nor the names of other
-  *    contributors to this software may be used to endorse or promote products
-  *    derived from this software without specific written permission.
-  * 4. This software, including modifications and/or derivative works of this
-  *    software, must execute solely and exclusively on microcontroller or
-  *    microprocessor devices manufactured by or for STMicroelectronics.
-  * 5. Redistribution and use of this software other than as permitted under
-  *    this license is void and will automatically terminate your rights under
-  *    this license.
-  *
-  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT
-  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY
-  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT
-  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L0xx_HAL_CONF_H
-#define __STM32L0xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-// #define HAL_ADC_MODULE_ENABLED
-/* #define HAL_COMP_MODULE_ENABLED */
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CRYP_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_FIREWALL_MODULE_ENABLED */
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LCD_MODULE_ENABLED */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-//#define HAL_RNG_MODULE_ENABLED
-/* #define HAL_RTC_MODULE_ENABLED */
-//#define HAL_SPI_MODULE_ENABLED
-/* #define HAL_TIM_MODULE_ENABLED */
-/* #define HAL_TSC_MODULE_ENABLED */
-/* #define HAL_UART_MODULE_ENABLED */
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-//#define HAL_PCD_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator for USB (HSI48) value.
-  */
-#if !defined  (HSI48_VALUE)
-#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* HSI48_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)37000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-/**
-  * @brief Time out for LSE start up value in ms.
-  */
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0U)    /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  PREREAD_ENABLE               1U
-#define  BUFFER_CACHE_DISABLE         0U
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC                   1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32l0xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32l0xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l0xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32l0xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32l0xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l0xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32l0xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32l0xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32l0xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FIREWALL_MODULE_ENABLED
-  #include "stm32l0xx_hal_firewall.h"
-#endif /* HAL_FIREWALL_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32l0xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l0xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32l0xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l0xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l0xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-#include "stm32l0xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l0xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32l0xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-  #include "stm32l0xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l0xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l0xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_TSC_MODULE_ENABLED
-  #include "stm32l0xx_hal_tsc.h"
-#endif /* HAL_TSC_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l0xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l0xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l0xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l0xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32l0xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l0xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l0xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t *file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L0xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

From 322f58ea8530e2b43d00a087b6d501776be25a00 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 12:47:05 +0700
Subject: [PATCH 1581/2085] add CFLAGS_SKIP to improve sam compile time

---
 .github/workflows/build_arm.yml | 5 ++---
 examples/rules.mk               | 4 ++++
 hw/bsp/samd11/family.mk         | 7 ++++++-
 hw/bsp/samd21/family.mk         | 5 ++++-
 hw/bsp/samd51/family.mk         | 4 ++--
 hw/bsp/same5x/family.mk         | 4 ++--
 hw/bsp/same70_qmtech/board.mk   | 5 ++++-
 hw/bsp/same70_xplained/board.mk | 5 ++++-
 hw/bsp/samg55xplained/board.mk  | 5 ++++-
 hw/bsp/saml2x/family.mk         | 5 ++++-
 10 files changed, 36 insertions(+), 13 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 3abfd50a8..8a3181440 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -48,9 +48,8 @@ jobs:
         - 'stm32f0 stm32f1'
         - 'stm32f4'
         - 'stm32f7'
-        - 'stm32g4 stm32wb'
-        - 'stm32h7'
-        - 'stm32l0 stm32l4'
+        - 'stm32g4 stm32h7'
+        - 'stm32l0 stm32l4 stm32u5 stm32wb'
         - 'tm4c123 xmc4000'
     steps:
     - name: Setup Python
diff --git a/examples/rules.mk b/examples/rules.mk
index 59cf4fd1f..b85837c16 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -66,6 +66,10 @@ ifeq ($(NO_LTO),1)
 CFLAGS := $(filter-out -flto,$(CFLAGS))
 endif
 
+ifneq ($(CFLAGS_SKIP),)
+CFLAGS := $(filter-out $(CFLAGS_SKIP),$(CFLAGS))
+endif
+
 LDFLAGS += $(CFLAGS) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections
 
 ifdef LD_FILE
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index dc6678b30..a2a5268aa 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -9,10 +9,15 @@ CFLAGS += \
   -nostdlib -nostartfiles \
   -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
   -DOSC32K_OVERWRITE_CALIBRATION=0 \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD11
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index 6d02d7fa6..30eccacb2 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -13,7 +13,10 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD21
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
index 3ecc5aa66..657e33438 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd51/family.mk
@@ -13,8 +13,8 @@ CFLAGS += \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD51
 
-# suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
diff --git a/hw/bsp/same5x/family.mk b/hw/bsp/same5x/family.mk
index 7f8692c97..df1af4a9d 100644
--- a/hw/bsp/same5x/family.mk
+++ b/hw/bsp/same5x/family.mk
@@ -13,8 +13,8 @@ CFLAGS += \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_SAME5X
 
-# suppress warning caused by vendor mcu driver
-#CFLAGS += -Wno-error=cast-qual
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
 
 SRC_C += \
   src/portable/microchip/samd/dcd_samd.c \
diff --git a/hw/bsp/same70_qmtech/board.mk b/hw/bsp/same70_qmtech/board.mk
index 1dcb8bfcd..ad5af2020 100644
--- a/hw/bsp/same70_qmtech/board.mk
+++ b/hw/bsp/same70_qmtech/board.mk
@@ -11,7 +11,10 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
 
 ASF_DIR = hw/mcu/microchip/same70
 
diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk
index 95c4aaaa2..769d03e21 100644
--- a/hw/bsp/same70_xplained/board.mk
+++ b/hw/bsp/same70_xplained/board.mk
@@ -11,7 +11,10 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMX7X
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
 
 ASF_DIR = hw/mcu/microchip/same70
 
diff --git a/hw/bsp/samg55xplained/board.mk b/hw/bsp/samg55xplained/board.mk
index 7cc9487fd..ed0d59772 100644
--- a/hw/bsp/samg55xplained/board.mk
+++ b/hw/bsp/samg55xplained/board.mk
@@ -12,7 +12,10 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAMG
 
 # suppress following warnings from mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=cast-qual -Wno-error=null-dereference -Wno-error=redundant-decls
+CFLAGS += -Wno-error=undef -Wno-error=null-dereference -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
 
 ASF_DIR = hw/mcu/microchip/samg55
 
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index 6022158de..91c2cfa61 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -14,7 +14,10 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_SAML22
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls
+CFLAGS += -Wno-error=redundant-decls
+
+# SAM driver is flooded with -Wcast-qual which slow down complication significantly
+CFLAGS_SKIP += -Wcast-qual
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \

From b46632ba07d5e3827029413f69618f41f987f452 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 13:11:41 +0700
Subject: [PATCH 1582/2085] bsp for f2 f3

---
 .github/workflows/build_arm.yml               |  7 ++-
 .../stm32f207nucleo/STM32F207ZGTx_FLASH.ld    |  0
 .../stm32f2/boards/stm32f207nucleo/board.mk   | 14 ++++++
 .../boards}/stm32f207nucleo/stm32f207nucleo.c |  2 +-
 .../board.mk => stm32f2/family.mk}            | 23 +++------
 .../stm32f2xx_hal_conf.h                      |  0
 .../stm32f303disco/STM32F303VCTx_FLASH.ld     |  0
 hw/bsp/stm32f3/boards/stm32f303disco/board.mk | 14 ++++++
 .../boards}/stm32f303disco/stm32f303disco.c   |  0
 .../stm32f303disco/stm32f3xx_hal_conf.h       |  0
 hw/bsp/stm32f303disco/board.mk                | 49 -------------------
 11 files changed, 40 insertions(+), 69 deletions(-)
 rename hw/bsp/{ => stm32f2/boards}/stm32f207nucleo/STM32F207ZGTx_FLASH.ld (100%)
 create mode 100644 hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk
 rename hw/bsp/{ => stm32f2/boards}/stm32f207nucleo/stm32f207nucleo.c (99%)
 rename hw/bsp/{stm32f207nucleo/board.mk => stm32f2/family.mk} (68%)
 rename hw/bsp/{stm32f207nucleo => stm32f2}/stm32f2xx_hal_conf.h (100%)
 rename hw/bsp/{ => stm32f3/boards}/stm32f303disco/STM32F303VCTx_FLASH.ld (100%)
 create mode 100644 hw/bsp/stm32f3/boards/stm32f303disco/board.mk
 rename hw/bsp/{ => stm32f3/boards}/stm32f303disco/stm32f303disco.c (100%)
 rename hw/bsp/{ => stm32f3/boards}/stm32f303disco/stm32f3xx_hal_conf.h (100%)
 delete mode 100644 hw/bsp/stm32f303disco/board.mk

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 8a3181440..2f72e758a 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -41,11 +41,10 @@ jobs:
         - 'nrf'
         - 'ra'
         - 'rp2040'
-        - 'samd11 same5x'
-        - 'samd21'
-        - 'samd51'
+        - 'samd11 samd21'
+        - 'samd51 same5x'
         - 'saml2x'
-        - 'stm32f0 stm32f1'
+        - 'stm32f0 stm32f1 stm32f2 stm32f3'
         - 'stm32f4'
         - 'stm32f7'
         - 'stm32g4 stm32h7'
diff --git a/hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld b/hw/bsp/stm32f2/boards/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
rename to hw/bsp/stm32f2/boards/stm32f207nucleo/STM32F207ZGTx_FLASH.ld
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk
new file mode 100644
index 000000000..ba185d199
--- /dev/null
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += \
+  -DSTM32F207xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32F207ZGTx_FLASH.ld
+
+SRC_S += \
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f207zg
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c b/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
similarity index 99%
rename from hw/bsp/stm32f207nucleo/stm32f207nucleo.c
rename to hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
index 80f762c93..48203b787 100644
--- a/hw/bsp/stm32f207nucleo/stm32f207nucleo.c
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#include "bsp/board.h"
 
 #include "stm32f2xx_hal.h"
 
diff --git a/hw/bsp/stm32f207nucleo/board.mk b/hw/bsp/stm32f2/family.mk
similarity index 68%
rename from hw/bsp/stm32f207nucleo/board.mk
rename to hw/bsp/stm32f2/family.mk
index 55581e1ec..7ca378548 100644
--- a/hw/bsp/stm32f207nucleo/board.mk
+++ b/hw/bsp/stm32f2/family.mk
@@ -1,9 +1,15 @@
 ST_FAMILY = f2
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
+DEPS_SUBMODULES += \
+	lib/CMSIS_5 \
+	$(ST_CMSIS) \
+	$(ST_HAL_DRIVER)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
 CFLAGS += \
   -flto \
   -mthumb \
@@ -11,15 +17,11 @@ CFLAGS += \
   -mcpu=cortex-m3 \
   -mfloat-abi=soft \
   -nostdlib -nostartfiles \
-  -DSTM32F207xx \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F2
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=sign-compare
 
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32F207ZGTx_FLASH.ld
-
 SRC_C += \
   src/portable/synopsys/dwc2/dcd_dwc2.c \
   $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
@@ -29,20 +31,11 @@ SRC_C += \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
 
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f207xx.s
-
 INC += \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
-  $(TOP)/hw/bsp/$(BOARD)
+  $(TOP)/$(BOARD_PATH)
 
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f207zg
-
-# flash target using on-board stlink
-flash: flash-stlink
diff --git a/hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h b/hw/bsp/stm32f2/stm32f2xx_hal_conf.h
similarity index 100%
rename from hw/bsp/stm32f207nucleo/stm32f2xx_hal_conf.h
rename to hw/bsp/stm32f2/stm32f2xx_hal_conf.h
diff --git a/hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld b/hw/bsp/stm32f3/boards/stm32f303disco/STM32F303VCTx_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32f303disco/STM32F303VCTx_FLASH.ld
rename to hw/bsp/stm32f3/boards/stm32f303disco/STM32F303VCTx_FLASH.ld
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.mk b/hw/bsp/stm32f3/boards/stm32f303disco/board.mk
new file mode 100644
index 000000000..e387f2d54
--- /dev/null
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.mk
@@ -0,0 +1,14 @@
+CFLAGS += \
+  -DSTM32F303xC \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32F303VCTx_FLASH.ld
+
+SRC_S += \
+  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f303vc
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f303disco/stm32f303disco.c b/hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
similarity index 100%
rename from hw/bsp/stm32f303disco/stm32f303disco.c
rename to hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
diff --git a/hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h b/hw/bsp/stm32f3/boards/stm32f303disco/stm32f3xx_hal_conf.h
similarity index 100%
rename from hw/bsp/stm32f303disco/stm32f3xx_hal_conf.h
rename to hw/bsp/stm32f3/boards/stm32f303disco/stm32f3xx_hal_conf.h
diff --git a/hw/bsp/stm32f303disco/board.mk b/hw/bsp/stm32f303disco/board.mk
deleted file mode 100644
index b81de4ee4..000000000
--- a/hw/bsp/stm32f303disco/board.mk
+++ /dev/null
@@ -1,49 +0,0 @@
-ST_FAMILY = f3
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
-ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib -nostartfiles \
-  -DSTM32F303xC \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F3
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/STM32F303VCTx_FLASH.ld
-
-SRC_C += \
-  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
-  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
-
-SRC_S += \
-  $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f303xc.s
-
-INC += \
-  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/$(ST_CMSIS)/Include \
-  $(TOP)/$(ST_HAL_DRIVER)/Inc \
-  $(TOP)/hw/bsp/$(BOARD)
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f303vc
-
-# flash target using on-board stlink
-flash: flash-stlink

From aa11e213584526e69e4e7e16553b24fc08481bc5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 13:15:05 +0700
Subject: [PATCH 1583/2085] add mising file

---
 hw/bsp/stm32f3/family.mk | 42 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 hw/bsp/stm32f3/family.mk

diff --git a/hw/bsp/stm32f3/family.mk b/hw/bsp/stm32f3/family.mk
new file mode 100644
index 000000000..f3b21d530
--- /dev/null
+++ b/hw/bsp/stm32f3/family.mk
@@ -0,0 +1,42 @@
+ST_FAMILY = f3
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+DEPS_SUBMODULES += \
+	lib/CMSIS_5 \
+	$(ST_CMSIS) \
+	$(ST_HAL_DRIVER)
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m4 \
+  -mfloat-abi=hard \
+  -mfpu=fpv4-sp-d16 \
+  -nostdlib -nostartfiles \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32F3
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter
+
+SRC_C += \
+  src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+  $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+  $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
+
+INC += \
+  $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+  $(TOP)/$(ST_CMSIS)/Include \
+  $(TOP)/$(ST_HAL_DRIVER)/Inc \
+  $(TOP)/$(BOARD_PATH)
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F

From 1867ba0bc10c89977a8370a8a55e5d68f6231e13 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 16:43:59 +0700
Subject: [PATCH 1584/2085] fix l4 hw testing ci

---
 .github/workflows/build_arm.yml | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 2f72e758a..ee3d9f533 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -94,21 +94,30 @@ jobs:
     # Upload binaries for rp2040/stm32l412nucleo hardware test with self-hosted
 
     - name: Prepare rp2040 Artifacts
-      if: matrix.family == 'rp2040' && github.repository_owner == 'hathach'
+      if: contains(matrix.family, 'rp2040') && github.repository_owner == 'hathach'
       run: find examples/ -name "*.elf" -exec mv {} . \;
 
     - name: Prepare stm32l412nucleo Artifacts
-      if: matrix.family == 'stm32l4'
+      if: contains(matrix.family, 'stm32l4')
       run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
 
-    - name: Upload Artifacts for hardware testing
-      if: matrix.family == 'stm32l4' || (matrix.family == 'rp2040' && github.repository_owner == 'hathach')
+    - name: Upload Artifacts for rp2040
+      if: contains(matrix.family,'rp2040') && github.repository_owner == 'hathach')
       uses: actions/upload-artifact@v3
       with:
-        name: ${{ matrix.family }}
+        name: rp2040
         path: |
           *.elf
 
+    - name: Upload Artifacts for stm32l412nucleo
+      if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach')
+      uses: actions/upload-artifact@v3
+      with:
+        name: stm32l4
+        path: |
+          *.elf
+
+
   # ---------------------------------------
   # Build all no-family (orphaned) boards
   # disable this workflow since it is often failed randomly

From 80be1aa13dcdd0b86c01212b6266a099669c98b2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 17:19:33 +0700
Subject: [PATCH 1585/2085] bsp lpc11

---
 .github/workflows/build_arm.yml               |  2 +-
 hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk  | 24 ++++++++++
 .../boards}/lpcxpresso11u37/lpc11u37.ld       |  0
 .../boards}/lpcxpresso11u37/lpcxpresso11u37.c |  2 +-
 hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk  | 18 ++++++++
 .../boards}/lpcxpresso11u68/lpc11u68.ld       |  0
 .../boards}/lpcxpresso11u68/lpcxpresso11u68.c |  2 +-
 hw/bsp/lpc11/family.mk                        | 43 +++++++++++++++++
 hw/bsp/lpcxpresso11u37/board.mk               | 46 -------------------
 hw/bsp/lpcxpresso11u68/board.mk               | 42 -----------------
 10 files changed, 88 insertions(+), 91 deletions(-)
 create mode 100644 hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk
 rename hw/bsp/{ => lpc11/boards}/lpcxpresso11u37/lpc11u37.ld (100%)
 rename hw/bsp/{ => lpc11/boards}/lpcxpresso11u37/lpcxpresso11u37.c (99%)
 create mode 100644 hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk
 rename hw/bsp/{ => lpc11/boards}/lpcxpresso11u68/lpc11u68.ld (100%)
 rename hw/bsp/{ => lpc11/boards}/lpcxpresso11u68/lpcxpresso11u68.c (99%)
 create mode 100644 hw/bsp/lpc11/family.mk
 delete mode 100644 hw/bsp/lpcxpresso11u37/board.mk
 delete mode 100644 hw/bsp/lpcxpresso11u68/board.mk

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index ee3d9f533..1a0e556e9 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -35,7 +35,7 @@ jobs:
         - 'broadcom_32bit'
         - 'imxrt'
         - 'kinetis_k32 kinetis_kl'
-        - 'lpc15 lpc18'
+        - 'lpc11 lpc15 lpc18'
         - 'lpc54 lpc55'
         - 'mm32 msp432e4'
         - 'nrf'
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk
new file mode 100644
index 000000000..fdc17374b
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.mk
@@ -0,0 +1,24 @@
+MCU = 11uxx
+MCU_DRV = 11xx
+
+CFLAGS += \
+  -DCORE_M0 \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'
+
+# mcu driver cause following warnings
+CFLAGS += \
+	-Wno-error=strict-prototypes \
+	-Wno-error=unused-parameter \
+	-Wno-error=redundant-decls
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc11u37.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC11U37/401
+PYOCD_TARGET = lpc11u37
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/lpcxpresso11u37/lpc11u37.ld b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
similarity index 100%
rename from hw/bsp/lpcxpresso11u37/lpc11u37.ld
rename to hw/bsp/lpc11/boards/lpcxpresso11u37/lpc11u37.ld
diff --git a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
similarity index 99%
rename from hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
rename to hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
index 79cd685c3..02dc2cbf9 100644
--- a/hw/bsp/lpcxpresso11u37/lpcxpresso11u37.c
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "../board.h"
+#include "bsp/board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk
new file mode 100644
index 000000000..fbe97b853
--- /dev/null
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.mk
@@ -0,0 +1,18 @@
+MCU = 11u6x
+MCU_DRV = 11u6x
+
+CFLAGS += \
+  -DCORE_M0PLUS \
+  -D__VTOR_PRESENT=0 \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc11u68.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC11U68
+PYOCD_TARGET = lpc11u68
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/lpcxpresso11u68/lpc11u68.ld b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpc11u68.ld
similarity index 100%
rename from hw/bsp/lpcxpresso11u68/lpc11u68.ld
rename to hw/bsp/lpc11/boards/lpcxpresso11u68/lpc11u68.ld
diff --git a/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
similarity index 99%
rename from hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
rename to hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
index a04e43867..44d091511 100644
--- a/hw/bsp/lpcxpresso11u68/lpcxpresso11u68.c
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "../board.h"
+#include "bsp/board.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/lpc11/family.mk b/hw/bsp/lpc11/family.mk
new file mode 100644
index 000000000..eb427c09d
--- /dev/null
+++ b/hw/bsp/lpc11/family.mk
@@ -0,0 +1,43 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc$(MCU)/lpc_chip_$(MCU)
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0plus \
+  -nostdlib \
+  -D__USE_LPCOPEN \
+  -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+
+SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
+	$(MCU_DIR)/../gcc/cr_startup_lpc$(MCU_DRV).c \
+	$(MCU_DIR)/src/chip_$(MCU_DRV).c \
+	$(MCU_DIR)/src/clock_$(MCU_DRV).c \
+	$(MCU_DIR)/src/iocon_$(MCU_DRV).c \
+	$(MCU_DIR)/src/sysinit_$(MCU_DRV).c
+
+ifeq ($(MCU),11u6x)
+SRC_C += \
+	$(MCU_DIR)/src/gpio_$(MCU_DRV).c \
+	$(MCU_DIR)/src/syscon_$(MCU_DRV).c \
+
+else
+
+SRC_C += \
+	$(MCU_DIR)/src/gpio_$(MCU_DRV)_1.c \
+	$(MCU_DIR)/src/sysctl_$(MCU_DRV).c
+endif
+
+INC += \
+	$(TOP)/$(MCU_DIR)/inc
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
+
+# For flash-jlink target
+JLINK_DEVICE = LPC11U68
diff --git a/hw/bsp/lpcxpresso11u37/board.mk b/hw/bsp/lpcxpresso11u37/board.mk
deleted file mode 100644
index 61e5eda7e..000000000
--- a/hw/bsp/lpcxpresso11u37/board.mk
+++ /dev/null
@@ -1,46 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0 \
-  -nostdlib \
-  -DCORE_M0 \
-  -D__USE_LPCOPEN \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_EXAMPLE_VIDEO_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=redundant-decls
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc11uxx/lpc_chip_11uxx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc11u37.ld
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc11xx.c \
-	$(MCU_DIR)/src/chip_11xx.c \
-	$(MCU_DIR)/src/clock_11xx.c \
-	$(MCU_DIR)/src/gpio_11xx_1.c \
-	$(MCU_DIR)/src/iocon_11xx.c \
-	$(MCU_DIR)/src/sysctl_11xx.c \
-	$(MCU_DIR)/src/sysinit_11xx.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = LPC11U37/401
-
-# flash using pyocd
-flash: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t lpc11u37 $<
diff --git a/hw/bsp/lpcxpresso11u68/board.mk b/hw/bsp/lpcxpresso11u68/board.mk
deleted file mode 100644
index cd6ad3617..000000000
--- a/hw/bsp/lpcxpresso11u68/board.mk
+++ /dev/null
@@ -1,42 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -nostdlib \
-  -DCORE_M0PLUS \
-  -D__VTOR_PRESENT=0 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM3")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc11u6x/lpc_chip_11u6x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc11u68.ld
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc11u6x.c \
-	$(MCU_DIR)/src/chip_11u6x.c \
-	$(MCU_DIR)/src/clock_11u6x.c \
-	$(MCU_DIR)/src/gpio_11u6x.c \
-	$(MCU_DIR)/src/iocon_11u6x.c \
-	$(MCU_DIR)/src/syscon_11u6x.c \
-	$(MCU_DIR)/src/sysinit_11u6x.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
-# For flash-jlink target
-JLINK_DEVICE = LPC11U68
-
-# flash using pyocd
-flash: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t lpc11u68 $<

From 64c6b715cecb80788b23a5f8f07e256e1c96ed38 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 17:26:49 +0700
Subject: [PATCH 1586/2085] bsp lpc13

---
 .github/workflows/build_arm.yml               |  6 +--
 hw/bsp/lpc13/boards/lpcxpresso1347/board.mk   | 13 ++++++
 .../boards}/lpcxpresso1347/lpc1347.ld         |  0
 .../boards}/lpcxpresso1347/lpcxpresso1347.c   |  0
 hw/bsp/lpcxpresso1347/board.mk                | 45 -------------------
 5 files changed, 16 insertions(+), 48 deletions(-)
 create mode 100644 hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
 rename hw/bsp/{ => lpc13/boards}/lpcxpresso1347/lpc1347.ld (100%)
 rename hw/bsp/{ => lpc13/boards}/lpcxpresso1347/lpcxpresso1347.c (100%)
 delete mode 100644 hw/bsp/lpcxpresso1347/board.mk

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 1a0e556e9..01b390ac8 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -35,7 +35,7 @@ jobs:
         - 'broadcom_32bit'
         - 'imxrt'
         - 'kinetis_k32 kinetis_kl'
-        - 'lpc11 lpc15 lpc18'
+        - 'lpc11 lpc13 lpc15 lpc18'
         - 'lpc54 lpc55'
         - 'mm32 msp432e4'
         - 'nrf'
@@ -102,7 +102,7 @@ jobs:
       run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
 
     - name: Upload Artifacts for rp2040
-      if: contains(matrix.family,'rp2040') && github.repository_owner == 'hathach')
+      if: contains(matrix.family,'rp2040') && github.repository_owner == 'hathach'
       uses: actions/upload-artifact@v3
       with:
         name: rp2040
@@ -110,7 +110,7 @@ jobs:
           *.elf
 
     - name: Upload Artifacts for stm32l412nucleo
-      if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach')
+      if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach'
       uses: actions/upload-artifact@v3
       with:
         name: stm32l4
diff --git a/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk b/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
new file mode 100644
index 000000000..31eb2f28f
--- /dev/null
+++ b/hw/bsp/lpc13/boards/lpcxpresso1347/board.mk
@@ -0,0 +1,13 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+
+CFLAGS += \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc1347.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1347
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/lpcxpresso1347/lpc1347.ld b/hw/bsp/lpc13/boards/lpcxpresso1347/lpc1347.ld
similarity index 100%
rename from hw/bsp/lpcxpresso1347/lpc1347.ld
rename to hw/bsp/lpc13/boards/lpcxpresso1347/lpc1347.ld
diff --git a/hw/bsp/lpcxpresso1347/lpcxpresso1347.c b/hw/bsp/lpc13/boards/lpcxpresso1347/lpcxpresso1347.c
similarity index 100%
rename from hw/bsp/lpcxpresso1347/lpcxpresso1347.c
rename to hw/bsp/lpc13/boards/lpcxpresso1347/lpcxpresso1347.c
diff --git a/hw/bsp/lpcxpresso1347/board.mk b/hw/bsp/lpcxpresso1347/board.mk
deleted file mode 100644
index 25d6fa7a3..000000000
--- a/hw/bsp/lpcxpresso1347/board.mk
+++ /dev/null
@@ -1,45 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -nostdlib \
-  -DCORE_M3 \
-  -D__USE_LPCOPEN \
-  -DCFG_EXAMPLE_MSC_READONLY \
-  -DCFG_EXAMPLE_VIDEO_READONLY \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
-
-# startup.c and lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=redundant-decls
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1347.ld
-
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc13xx.c \
-	$(MCU_DIR)/src/chip_13xx.c \
-	$(MCU_DIR)/src/clock_13xx.c \
-	$(MCU_DIR)/src/gpio_13xx_1.c \
-	$(MCU_DIR)/src/iocon_13xx.c \
-	$(MCU_DIR)/src/sysctl_13xx.c \
-	$(MCU_DIR)/src/sysinit_13xx.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1347
-
-# flash using jlink
-flash: flash-jlink

From 1154b7a9e733fd6571c2a47e52d6d49da0b3b096 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 17:40:44 +0700
Subject: [PATCH 1587/2085] add mising lpc13 file

---
 hw/bsp/lpc13/family.mk | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 hw/bsp/lpc13/family.mk

diff --git a/hw/bsp/lpc13/family.mk b/hw/bsp/lpc13/family.mk
new file mode 100644
index 000000000..28f98e4ca
--- /dev/null
+++ b/hw/bsp/lpc13/family.mk
@@ -0,0 +1,39 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m3 \
+  -nostdlib \
+  -DCORE_M3 \
+  -D__USE_LPCOPEN \
+  -DCFG_EXAMPLE_MSC_READONLY \
+  -DCFG_EXAMPLE_VIDEO_READONLY \
+  -DCFG_TUSB_MCU=OPT_MCU_LPC13XX \
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+
+# startup.c and lpc_types.h cause following errors
+CFLAGS += -Wno-error=strict-prototypes -Wno-error=redundant-decls
+
+# caused by freeRTOS port !!
+CFLAGS += -Wno-error=maybe-uninitialized
+
+SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
+	$(MCU_DIR)/../gcc/cr_startup_lpc13xx.c \
+	$(MCU_DIR)/src/chip_13xx.c \
+	$(MCU_DIR)/src/clock_13xx.c \
+	$(MCU_DIR)/src/gpio_13xx_1.c \
+	$(MCU_DIR)/src/iocon_13xx.c \
+	$(MCU_DIR)/src/sysctl_13xx.c \
+	$(MCU_DIR)/src/sysinit_13xx.c
+
+INC += \
+	$(TOP)/$(MCU_DIR)/inc
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3

From 934baae9b8dd58dd17881ef8ad8bd3428b208b1f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 17:58:20 +0700
Subject: [PATCH 1588/2085] bsp lpc51

---
 .github/workflows/build_arm.yml               |  2 +-
 hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk  | 37 +++++++++++++++++++
 .../boards}/lpcxpresso51u68/lpcxpresso51u68.c |  0
 .../board.mk => lpc51/family.mk}              | 19 +++-------
 4 files changed, 44 insertions(+), 14 deletions(-)
 create mode 100644 hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
 rename hw/bsp/{ => lpc51/boards}/lpcxpresso51u68/lpcxpresso51u68.c (100%)
 rename hw/bsp/{lpcxpresso51u68/board.mk => lpc51/family.mk} (74%)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 01b390ac8..2b64e5410 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -36,7 +36,7 @@ jobs:
         - 'imxrt'
         - 'kinetis_k32 kinetis_kl'
         - 'lpc11 lpc13 lpc15 lpc18'
-        - 'lpc54 lpc55'
+        - 'lpc51 lpc54 lpc55'
         - 'mm32 msp432e4'
         - 'nrf'
         - 'ra'
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
new file mode 100644
index 000000000..27b9b371f
--- /dev/null
+++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
@@ -0,0 +1,37 @@
+MCU = LPC51U68
+
+CFLAGS += \
+  -DCPU_LPC51U68JBD64 \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))'
+
+SRC_C += \
+	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
+	$(MCU_DIR)/system_LPC51U68.c \
+	$(MCU_DIR)/drivers/fsl_clock.c \
+	$(MCU_DIR)/drivers/fsl_power.c \
+	$(MCU_DIR)/drivers/fsl_reset.c \
+	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
+	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
+
+INC += \
+	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/drivers \
+	$(TOP)/$(SDK_DIR)/drivers/common \
+	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
+	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
+	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
+
+SRC_S += $(MCU_DIR)/gcc/startup_LPC51U68.S
+
+LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
+
+JLINK_DEVICE = LPC51U68
+PYOCD_TARGET = LPC51U68
+
+# flash using pyocd (51u68 is not supported yet)
+flash: flash-pyocd
diff --git a/hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c b/hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c
similarity index 100%
rename from hw/bsp/lpcxpresso51u68/lpcxpresso51u68.c
rename to hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c
diff --git a/hw/bsp/lpcxpresso51u68/board.mk b/hw/bsp/lpc51/family.mk
similarity index 74%
rename from hw/bsp/lpcxpresso51u68/board.mk
rename to hw/bsp/lpc51/family.mk
index b1a126c51..8a64f0945 100644
--- a/hw/bsp/lpcxpresso51u68/board.mk
+++ b/hw/bsp/lpc51/family.mk
@@ -1,27 +1,26 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
 DEPS_SUBMODULES += $(SDK_DIR)
 
+MCU_DIR = $(SDK_DIR)/devices/$(MCU)
+include $(TOP)/$(BOARD_PATH)/board.mk
+
 CFLAGS += \
   -flto \
   -mthumb \
   -mabi=aapcs \
   -mcpu=cortex-m0plus \
-  -DCPU_LPC51U68JBD64 \
   -DCFG_TUSB_MCU=OPT_MCU_LPC51UXX \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))' \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter
 
-MCU_DIR = $(SDK_DIR)/devices/LPC51U68
-
 # All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/LPC51U68_flash.ld
+LD_FILE = $(MCU_DIR)/gcc/$(MCU)_flash.ld
 
 SRC_C += \
 	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/system_LPC51U68.c \
+	$(MCU_DIR)/system_$(MCU).c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(MCU_DIR)/drivers/fsl_power.c \
 	$(MCU_DIR)/drivers/fsl_reset.c \
@@ -38,15 +37,9 @@ INC += \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
 
-SRC_S += $(MCU_DIR)/gcc/startup_LPC51U68.S
+SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
 
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
 
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
-JLINK_DEVICE = LPC51U68
-PYOCD_TARGET = LPC51U68
-
-# flash using pyocd (51u68 is not supported yet)
-flash: flash-pyocd

From f75a019732c266a5c1eede1c763389210e8bc79d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 18:03:18 +0700
Subject: [PATCH 1589/2085] bsp lpc17

---
 .github/workflows/build_arm.yml               |  2 +-
 hw/bsp/lpc17/boards/lpcxpresso1769/board.mk   |  8 ++++
 .../boards}/lpcxpresso1769/lpc1769.ld         |  0
 .../boards}/lpcxpresso1769/lpcxpresso1769.c   |  0
 hw/bsp/lpc17/boards/mbed1768/board.mk         |  9 ++++
 hw/bsp/{ => lpc17/boards}/mbed1768/lpc1768.ld |  0
 hw/bsp/{ => lpc17/boards}/mbed1768/mbed1768.c |  0
 .../board.mk => lpc17/family.mk}              | 15 +++----
 hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk  | 26 -----------
 hw/bsp/mbed1768/board.mk                      | 44 -------------------
 10 files changed, 24 insertions(+), 80 deletions(-)
 create mode 100644 hw/bsp/lpc17/boards/lpcxpresso1769/board.mk
 rename hw/bsp/{ => lpc17/boards}/lpcxpresso1769/lpc1769.ld (100%)
 rename hw/bsp/{ => lpc17/boards}/lpcxpresso1769/lpcxpresso1769.c (100%)
 create mode 100644 hw/bsp/lpc17/boards/mbed1768/board.mk
 rename hw/bsp/{ => lpc17/boards}/mbed1768/lpc1768.ld (100%)
 rename hw/bsp/{ => lpc17/boards}/mbed1768/mbed1768.c (100%)
 rename hw/bsp/{lpcxpresso1769/board.mk => lpc17/family.mk} (82%)
 delete mode 100644 hw/bsp/mbed1768/board.mk

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 2b64e5410..a62d587ce 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -35,7 +35,7 @@ jobs:
         - 'broadcom_32bit'
         - 'imxrt'
         - 'kinetis_k32 kinetis_kl'
-        - 'lpc11 lpc13 lpc15 lpc18'
+        - 'lpc11 lpc13 lpc15 lpc17 lpc18'
         - 'lpc51 lpc54 lpc55'
         - 'mm32 msp432e4'
         - 'nrf'
diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/board.mk b/hw/bsp/lpc17/boards/lpcxpresso1769/board.mk
new file mode 100644
index 000000000..e22c4f64b
--- /dev/null
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/board.mk
@@ -0,0 +1,8 @@
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc1769.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1769
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/lpcxpresso1769/lpc1769.ld b/hw/bsp/lpc17/boards/lpcxpresso1769/lpc1769.ld
similarity index 100%
rename from hw/bsp/lpcxpresso1769/lpc1769.ld
rename to hw/bsp/lpc17/boards/lpcxpresso1769/lpc1769.ld
diff --git a/hw/bsp/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
similarity index 100%
rename from hw/bsp/lpcxpresso1769/lpcxpresso1769.c
rename to hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
diff --git a/hw/bsp/lpc17/boards/mbed1768/board.mk b/hw/bsp/lpc17/boards/mbed1768/board.mk
new file mode 100644
index 000000000..a982a970b
--- /dev/null
+++ b/hw/bsp/lpc17/boards/mbed1768/board.mk
@@ -0,0 +1,9 @@
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/lpc1768.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC1768
+PYOCD_TARGET = lpc1768
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/mbed1768/lpc1768.ld b/hw/bsp/lpc17/boards/mbed1768/lpc1768.ld
similarity index 100%
rename from hw/bsp/mbed1768/lpc1768.ld
rename to hw/bsp/lpc17/boards/mbed1768/lpc1768.ld
diff --git a/hw/bsp/mbed1768/mbed1768.c b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
similarity index 100%
rename from hw/bsp/mbed1768/mbed1768.c
rename to hw/bsp/lpc17/boards/mbed1768/mbed1768.c
diff --git a/hw/bsp/lpcxpresso1769/board.mk b/hw/bsp/lpc17/family.mk
similarity index 82%
rename from hw/bsp/lpcxpresso1769/board.mk
rename to hw/bsp/lpc17/family.mk
index d459c8b7b..af01b55a8 100644
--- a/hw/bsp/lpcxpresso1769/board.mk
+++ b/hw/bsp/lpc17/family.mk
@@ -1,5 +1,8 @@
 DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
+include $(TOP)/$(BOARD_PATH)/board.mk
+
 CFLAGS += \
   -flto \
   -mthumb \
@@ -14,10 +17,10 @@ CFLAGS += \
 # lpc_types.h cause following errors
 CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
 
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
+# caused by freeRTOS port !!
+CFLAGS += -Wno-error=maybe-uninitialized
 
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1769.ld
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 
 SRC_C += \
 	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
@@ -35,9 +38,3 @@ INC += \
 
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1769
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
index 27b9b371f..5627cb024 100644
--- a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
+++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.mk
@@ -4,32 +4,6 @@ CFLAGS += \
   -DCPU_LPC51U68JBD64 \
   -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data")))'
 
-SRC_C += \
-	src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \
-	$(MCU_DIR)/system_LPC51U68.c \
-	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(MCU_DIR)/drivers/fsl_power.c \
-	$(MCU_DIR)/drivers/fsl_reset.c \
-	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
-	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/drivers \
-	$(TOP)/$(SDK_DIR)/drivers/common \
-	$(TOP)/$(SDK_DIR)/drivers/flexcomm \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_iocon \
-	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
-
-SRC_S += $(MCU_DIR)/gcc/startup_LPC51U68.S
-
-LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
 JLINK_DEVICE = LPC51U68
 PYOCD_TARGET = LPC51U68
 
diff --git a/hw/bsp/mbed1768/board.mk b/hw/bsp/mbed1768/board.mk
deleted file mode 100644
index 6940bbb55..000000000
--- a/hw/bsp/mbed1768/board.mk
+++ /dev/null
@@ -1,44 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -nostdlib \
-  -DCORE_M3 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC175X_6X \
-  -DRTC_EV_SUPPORT=0
-
-# startup.c and lpc_types.h cause following errors
-CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc1768.ld
-
-SRC_C += \
-	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
-	$(MCU_DIR)/src/chip_17xx_40xx.c \
-	$(MCU_DIR)/src/clock_17xx_40xx.c \
-	$(MCU_DIR)/src/gpio_17xx_40xx.c \
-	$(MCU_DIR)/src/iocon_17xx_40xx.c \
-	$(MCU_DIR)/src/sysctl_17xx_40xx.c \
-	$(MCU_DIR)/src/sysinit_17xx_40xx.c \
-	$(MCU_DIR)/src/uart_17xx_40xx.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = LPC1768
-
-# flash using pyocd
-flash: $(BUILD)/$(PROJECT).hex
-	pyocd flash -t lpc1768 $<

From f58da311453b13808db775f27337345bcbdf9aba Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 19 Mar 2023 18:12:03 +0700
Subject: [PATCH 1590/2085] clean up

---
 .github/workflows/build_arm.yml | 36 ---------------------------------
 1 file changed, 36 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index a62d587ce..b60d12a98 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -117,42 +117,6 @@ jobs:
         path: |
           *.elf
 
-
-  # ---------------------------------------
-  # Build all no-family (orphaned) boards
-  # disable this workflow since it is often failed randomly
-  # ---------------------------------------
-  build-board:
-    runs-on: ubuntu-latest
-    if: false
-    strategy:
-      fail-fast: false
-      matrix:
-        example:
-        # Alphabetical order, a group of 4
-        - 'device/audio_test device/board_test device/cdc_dual_ports device/cdc_msc'
-        - 'device/cdc_msc_freertos device/dfu_runtime device/hid_composite device/hid_composite_freertos'
-        - 'device/hid_generic_inout device/hid_multiple_interface device/midi_test device/msc_dual_lun'
-        - 'device/net_lwip_webserver'
-        - 'device/uac2_headset device/usbtmc device/webusb_serial host/cdc_msc_hid'
-
-    steps:
-    - name: Setup Python
-      uses: actions/setup-python@v4
-      with:
-        python-version: '3.x'
-
-    - name: Install ARM GCC
-      uses: carlosperate/arm-none-eabi-gcc-action@v1
-      with:
-        release: '11.2-2022.02'
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Build
-      run: python3 tools/build_board.py ${{ matrix.example }}
-
   # ---------------------------------------
   # Hardware in the loop (HIL)
   # Current self-hosted instance is running on an RPI4 with

From 45202187864d6dce8c4bc1a3d698e90ae98b7855 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 20 Mar 2023 11:33:39 +0700
Subject: [PATCH 1591/2085] more compatible with IAR

---
 src/portable/raspberrypi/rp2040/rp2040_usb.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.h b/src/portable/raspberrypi/rp2040/rp2040_usb.h
index 5d3d792cb..d4d29a816 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.h
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.h
@@ -36,8 +36,8 @@
 #define __tusb_irq_path_func(x) x
 #endif
 
-#define usb_hw_set    ((usb_hw_t *) hw_set_alias(usb_hw))
-#define usb_hw_clear  ((usb_hw_t *) hw_clear_alias(usb_hw))
+#define usb_hw_set    ((usb_hw_t *) hw_set_alias_untyped(usb_hw))
+#define usb_hw_clear  ((usb_hw_t *) hw_clear_alias_untyped(usb_hw))
 
 #define pico_info(...)  TU_LOG(2, __VA_ARGS__)
 #define pico_trace(...) TU_LOG(3, __VA_ARGS__)

From e44e461ce3295f5680ea211048ade473963ba016 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 21 Mar 2023 12:54:43 +0700
Subject: [PATCH 1592/2085] add tuh_set_interface

---
 src/class/cdc/cdc_host.c |  6 ++---
 src/class/cdc/cdc_host.h |  2 +-
 src/common/tusb_common.h |  6 -----
 src/common/tusb_types.h  |  5 ++++
 src/host/usbh.c          | 50 ++++++++++++++++++++++++++++++++--------
 src/host/usbh.h          |  5 ++++
 6 files changed, 55 insertions(+), 19 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 011ee49dc..d34662cb7 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -97,7 +97,7 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
     }
   }
 
-  return TU_INDEX_INVALID_8;
+  return TUSB_INDEX_INVALID_8;
 }
 
 
@@ -124,7 +124,7 @@ uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num)
     if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i;
   }
 
-  return TU_INDEX_INVALID_8;
+  return TUSB_INDEX_INVALID_8;
 }
 
 bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info)
@@ -533,7 +533,7 @@ static void process_cdc_config(tuh_xfer_t* xfer)
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  TU_ASSERT(idx != TU_INDEX_INVALID_8, );
+  TU_ASSERT(idx != TUSB_INDEX_INVALID_8, );
 
   switch(state)
   {
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 4090d0e9f..03f32e542 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -80,7 +80,7 @@ typedef struct
 } tuh_cdc_itf_info_t;
 
 // Get Interface index from device address + interface number
-// return TUSB_INDEX_INVALID (0xFF) if not found
+// return TUSB_INDEX_INVALID_8 (0xFF) if not found
 uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num);
 
 // Get Interface information
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index faccf8726..957491aa9 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -75,12 +75,6 @@
 
 #include "tusb_timeout.h" // TODO remove
 
-enum
-{
-  TU_INDEX_INVALID_8 = 0xFFu
-};
-
-
 //--------------------------------------------------------------------+
 // Optional API implemented by application if needed
 // TODO move to a more ovious place/file
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index d567bd482..39a2d4564 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -273,6 +273,11 @@ enum
   CONTROL_STAGE_ACK
 };
 
+enum
+{
+  TUSB_INDEX_INVALID_8 = 0xFFu
+};
+
 //--------------------------------------------------------------------+
 // USB Descriptors
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 9ccbe7557..5a14aea5f 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -195,7 +195,7 @@ enum { CONFIG_NUM = 1 }; // default to use configuration 1
 // sum of end device + hub
 #define TOTAL_DEVICES   (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB)
 
-static uint8_t _usbh_controller = TU_INDEX_INVALID_8;
+static uint8_t _usbh_controller = TUSB_INDEX_INVALID_8;
 
 // Device with address = 0 for enumeration
 static usbh_dev0_t _dev0;
@@ -303,13 +303,13 @@ tusb_speed_t tuh_speed_get (uint8_t dev_addr)
 static void clear_device(usbh_device_t* dev)
 {
   tu_memclr(dev, sizeof(usbh_device_t));
-  memset(dev->itf2drv, TU_INDEX_INVALID_8, sizeof(dev->itf2drv)); // invalid mapping
-  memset(dev->ep2drv , TU_INDEX_INVALID_8, sizeof(dev->ep2drv )); // invalid mapping
+  memset(dev->itf2drv, TUSB_INDEX_INVALID_8, sizeof(dev->itf2drv)); // invalid mapping
+  memset(dev->ep2drv , TUSB_INDEX_INVALID_8, sizeof(dev->ep2drv )); // invalid mapping
 }
 
 bool tuh_inited(void)
 {
-  return _usbh_controller != TU_INDEX_INVALID_8;
+  return _usbh_controller != TUSB_INDEX_INVALID_8;
 }
 
 bool tuh_init(uint8_t controller_id)
@@ -1033,6 +1033,38 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
   return tuh_control_xfer(&xfer);
 }
 
+bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
+                       tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  TU_LOG_USBH("Set Interface %u Alternate %u\r\n", itf_num, itf_alt);
+
+  tusb_control_request_t const request =
+  {
+    .bmRequestType_bit =
+    {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_STANDARD,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = TUSB_REQ_SET_INTERFACE,
+    .wValue   = tu_htole16(itf_alt),
+    .wIndex   = tu_htole16(itf_num),
+    .wLength  = 0
+  };
+
+  tuh_xfer_t xfer =
+  {
+    .daddr       = daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = NULL,
+    .complete_cb = complete_cb,
+    .user_data   = user_data
+  };
+
+  return tuh_control_xfer(&xfer);
+}
+
 //--------------------------------------------------------------------+
 // Descriptor Sync
 //--------------------------------------------------------------------+
@@ -1358,11 +1390,11 @@ static void process_enumeration(tuh_xfer_t* xfer)
 
       dev->configured = 1;
 
-      // Start the Set Configuration process for interfaces (itf = TU_INDEX_INVALID_8)
+      // Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8)
       // Since driver can perform control transfer within its set_config, this is done asynchronously.
       // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete()
-      // TODO use separated API instead of using TU_INDEX_INVALID_8
-      usbh_driver_set_config_complete(daddr, TU_INDEX_INVALID_8);
+      // TODO use separated API instead of using TUSB_INDEX_INVALID_8
+      usbh_driver_set_config_complete(daddr, TUSB_INDEX_INVALID_8);
     }
     break;
 
@@ -1562,7 +1594,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
           uint8_t const itf_num = desc_itf->bInterfaceNumber+i;
 
           // Interface number must not be used already
-          TU_ASSERT( TU_INDEX_INVALID_8 == dev->itf2drv[itf_num] );
+          TU_ASSERT( TUSB_INDEX_INVALID_8 == dev->itf2drv[itf_num] );
           dev->itf2drv[itf_num] = drv_id;
         }
 
@@ -1596,7 +1628,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
     // IAD binding interface such as CDCs should return itf_num + 1 when complete
     // with usbh_driver_set_config_complete()
     uint8_t const drv_id = dev->itf2drv[itf_num];
-    if (drv_id != TU_INDEX_INVALID_8)
+    if (drv_id != TUSB_INDEX_INVALID_8)
     {
       usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
       TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num);
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 7942de5c2..45e6356bc 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -171,6 +171,11 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
                            tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
+// Set Interface (control transfer)
+// true on success, false if there is on-going control transfer or incorrect parameters
+bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
+                       tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
 //--------------------------------------------------------------------+
 // Descriptors Asynchronous (non-blocking)
 //--------------------------------------------------------------------+

From ccf17e3cde4c3ca42731829107ca18217aab541e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 21 Mar 2023 13:21:59 +0700
Subject: [PATCH 1593/2085] add  -Wreturn-type

---
 examples/make.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/examples/make.mk b/examples/make.mk
index 0a07da21c..2ce6fb398 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -150,6 +150,7 @@ GCC_CFLAGS += \
   -Wnull-dereference \
   -Wuninitialized \
   -Wunused \
+  -Wreturn-type \
   -Wredundant-decls
 
 # conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion

From 42decd94e5de3a25fd7e7702da2f756b53a6c9f9 Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Tue, 21 Mar 2023 07:58:39 +0100
Subject: [PATCH 1594/2085] UAC2: fix feedback EP buffer alignment.

---
 src/class/audio/audio_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 32ba5761e..f487fe60e 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -312,7 +312,7 @@ typedef struct
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
   struct {
-    uint32_t value;       // Feedback value for asynchronous mode (in 16.16 format).
+    CFG_TUSB_MEM_ALIGN uint32_t value;  // Feedback value for asynchronous mode (in 16.16 format).
     uint32_t min_value;   // min value according to UAC2 FMT-2.0 section 2.3.1.1.
     uint32_t max_value;   // max value according to UAC2 FMT-2.0 section 2.3.1.1.
 

From 878f2b54fe208f717677cabda57180ef8a4bc3cd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 21 Mar 2023 18:12:55 +0700
Subject: [PATCH 1595/2085] relax hid host enumeration, allow set protocol to
 be stalled

---
 src/class/hid/hid_host.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index e5fc86267..df220d7c3 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -465,8 +465,10 @@ bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
 
 static void process_set_config(tuh_xfer_t* xfer)
 {
-  // Stall is a valid response for SET_IDLE, therefore we could ignore its result
-  if ( xfer->setup->bRequest != HID_REQ_CONTROL_SET_IDLE )
+  // Stall is a valid response for SET_IDLE, sometime SET_PROTOCOL as well
+  // therefore we could ignore its result
+  if ( !(xfer->setup->bRequest == HID_REQ_CONTROL_SET_IDLE ||
+         xfer->setup->bRequest == HID_REQ_CONTROL_SET_PROTOCOL) )
   {
     TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS, );
   }

From d34508a316a2b97db749651452b8e1650e854f37 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 21 Mar 2023 18:13:25 +0700
Subject: [PATCH 1596/2085] add note for blocking tuh_configuration_set(),
 tuh_interface_set()

---
 src/host/usbh.c | 20 ++++++++++++++++++--
 src/host/usbh.h |  2 ++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 5a14aea5f..a3335102f 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1030,7 +1030,15 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
     .user_data   = user_data
   };
 
-  return tuh_control_xfer(&xfer);
+  bool ret = tuh_control_xfer(&xfer);
+
+  // if blocking, user_data could be pointed to xfer_result
+  if ( !complete_cb && user_data )
+  {
+    *((xfer_result_t*) user_data) = xfer.result;
+  }
+
+  return ret;
 }
 
 bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
@@ -1062,7 +1070,15 @@ bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
     .user_data   = user_data
   };
 
-  return tuh_control_xfer(&xfer);
+  bool ret = tuh_control_xfer(&xfer);
+
+  // if blocking, user_data could be pointed to xfer_result
+  if ( !complete_cb && user_data )
+  {
+    *((xfer_result_t*) user_data) = xfer.result;
+  }
+
+  return ret;
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 45e6356bc..125d8f4c9 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -168,11 +168,13 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
 // Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
 // true on success, false if there is on-going control transfer or incorrect parameters
+// if complete_cb == NULL i.e blocking, user_data should be pointed to xfer_reuslt_t*
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
                            tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Set Interface (control transfer)
 // true on success, false if there is on-going control transfer or incorrect parameters
+// if complete_cb == NULL i.e blocking, user_data should be pointed to xfer_reuslt_t*
 bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
                        tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 

From 8a0b17598c14497805addbb7c670e41c9eb5c0b7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 21 Mar 2023 18:15:45 +0700
Subject: [PATCH 1597/2085] add osal_task_delay() for control blocking

---
 src/host/usbh.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index a3335102f..dc347c458 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -568,6 +568,8 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
       // only need to call task if not preempted RTOS
       #if CFG_TUSB_OS == OPT_OS_NONE || CFG_TUSB_OS == OPT_OS_PICO
       tuh_task();
+      #else
+      osal_task_delay(1); // TODO maybe yield()
       #endif
 
       // TODO probably some timeout to prevent hanged

From d22fc550c76f0d2c5d980a253161e95f1a853309 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 21 Mar 2023 21:04:06 +0700
Subject: [PATCH 1598/2085] change meaning of CFG_TUH_HID to total number of
 HID interfaces supported.

- previously CFG_TUH_HID is max number of interfaces per device which is
rather limited and consume more resources than needed.
- change hid host instance in API to index
---
 .../host_hid_to_device_cdc/src/tusb_config.h  |   2 +-
 examples/host/cdc_msc_hid/src/tusb_config.h   |   4 +-
 .../host/hid_controller/src/tusb_config.h     |   2 +-
 src/class/hid/hid_host.c                      | 355 +++++++++---------
 src/class/hid/hid_host.h                      |  44 ++-
 5 files changed, 218 insertions(+), 189 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
index f749bd712..72ec8d654 100644
--- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
+++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
@@ -132,7 +132,7 @@
 // max device support (excluding hub device)
 #define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
 
-#define CFG_TUH_HID                  4
+#define CFG_TUH_HID                 (4*CFG_TUH_DEVICE_MAX)
 #define CFG_TUH_HID_EPIN_BUFSIZE    64
 #define CFG_TUH_HID_EPOUT_BUFSIZE   64
 
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 4b50f2096..a0a740c6e 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -36,7 +36,7 @@
 
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
 // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB   0
+#define CFG_TUH_RPI_PIO_USB   1
 #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
 #endif
 
@@ -97,7 +97,7 @@
 
 #define CFG_TUH_HUB                 1 // number of supported hubs
 #define CFG_TUH_CDC                 1
-#define CFG_TUH_HID                 4 // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_HID                 (4*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
 
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index 2e0dd0dbe..f4ddc1b81 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -97,7 +97,7 @@
 
 #define CFG_TUH_HUB                 0
 #define CFG_TUH_CDC                 0
-#define CFG_TUH_HID                 4 // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_HID                 (4*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 0
 #define CFG_TUH_VENDOR              0
 
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index df220d7c3..f65b2dc20 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -39,6 +39,8 @@
 
 typedef struct
 {
+  uint8_t daddr;
+
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t ep_out;
@@ -56,74 +58,131 @@ typedef struct
   uint8_t epout_buf[CFG_TUH_HID_EPOUT_BUFSIZE];
 } hidh_interface_t;
 
-typedef struct
-{
-  uint8_t inst_count;
-  hidh_interface_t instances[CFG_TUH_HID];
-} hidh_device_t;
-
 CFG_TUSB_MEM_SECTION
-static hidh_device_t _hidh_dev[CFG_TUH_DEVICE_MAX];
+tu_static hidh_interface_t _hidh_itf[CFG_TUH_HID];
 
-//------------- Internal prototypes -------------//
+//--------------------------------------------------------------------+
+// Helper
+//--------------------------------------------------------------------+
 
-// Get HID device & interface
-TU_ATTR_ALWAYS_INLINE static inline hidh_device_t* get_dev(uint8_t dev_addr);
-TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_instance(uint8_t dev_addr, uint8_t instance);
-static uint8_t get_instance_id_by_itfnum(uint8_t dev_addr, uint8_t itf);
-static uint8_t get_instance_id_by_epaddr(uint8_t dev_addr, uint8_t ep_addr);
+TU_ATTR_ALWAYS_INLINE static inline
+hidh_interface_t* get_hid_itf(uint8_t daddr, uint8_t idx)
+{
+  TU_ASSERT(daddr && idx < CFG_TUH_HID, NULL);
+  hidh_interface_t* p_hid = &_hidh_itf[idx];
+  return (p_hid->daddr == daddr) ? p_hid : NULL;
+}
+
+// Get instance ID by endpoint address
+static uint8_t get_idx_by_epaddr(uint8_t daddr, uint8_t ep_addr)
+{
+  for ( uint8_t idx = 0; idx < CFG_TUH_HID; idx++ )
+  {
+    hidh_interface_t const * p_hid = &_hidh_itf[idx];
+
+    if ( p_hid->daddr == daddr &&
+         (p_hid->ep_in == ep_addr || p_hid->ep_out == ep_addr) )
+    {
+      return idx;
+    }
+  }
+
+  return TUSB_INDEX_INVALID_8;
+}
+
+static hidh_interface_t* find_new_itf(void)
+{
+  for(uint8_t i=0; i<CFG_TUH_HID; i++)
+  {
+    if (_hidh_itf[i].daddr == 0) return &_hidh_itf[i];
+  }
+
+  return NULL;
+}
 
 //--------------------------------------------------------------------+
 // Interface API
 //--------------------------------------------------------------------+
 
-uint8_t tuh_hid_instance_count(uint8_t dev_addr)
+uint8_t tuh_hid_itf_get_count(uint8_t daddr)
 {
-  return get_dev(dev_addr)->inst_count;
+  uint8_t count = 0;
+
+  for(uint8_t i=0; i<CFG_TUH_HID; i++)
+  {
+    if (_hidh_itf[i].daddr == daddr) count++;
+  }
+
+  return count;
 }
 
-bool tuh_hid_mounted(uint8_t dev_addr, uint8_t instance)
+uint8_t tuh_hid_itf_get_total_count(void)
 {
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-  return (hid_itf->ep_in != 0) || (hid_itf->ep_out != 0);
+  uint8_t count = 0;
+
+  for(uint8_t i=0; i<CFG_TUH_HID; i++)
+  {
+    if (_hidh_itf[i].daddr != 0) count++;
+  }
+
+  return count;
 }
 
-uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance)
+bool tuh_hid_mounted(uint8_t daddr, uint8_t idx)
 {
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-  return hid_itf->itf_protocol;
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  return p_hid != NULL;
+}
+
+uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num)
+{
+  for ( uint8_t idx = 0; idx < CFG_TUH_HID; idx++ )
+  {
+    hidh_interface_t const * p_hid = &_hidh_itf[idx];
+
+    if ( p_hid->daddr == daddr && p_hid->itf_num == itf_num) return idx;
+  }
+
+  return TUSB_INDEX_INVALID_8;
+}
+
+uint8_t tuh_hid_interface_protocol(uint8_t daddr, uint8_t idx)
+{
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  return p_hid ? p_hid->itf_protocol : 0;
 }
 
 //--------------------------------------------------------------------+
 // Control Endpoint API
 //--------------------------------------------------------------------+
 
-uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance)
+uint8_t tuh_hid_get_protocol(uint8_t daddr, uint8_t idx)
 {
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-  return hid_itf->protocol_mode;
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  return p_hid ? p_hid->protocol_mode : 0;
 }
 
 static void set_protocol_complete(tuh_xfer_t* xfer)
 {
-  uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t const daddr       = xfer->daddr;
-  uint8_t const instance    = get_instance_id_by_itfnum(daddr, itf_num);
-  hidh_interface_t* hid_itf = get_instance(daddr, instance);
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t const daddr   = xfer->daddr;
+  uint8_t const idx     = tuh_hid_itf_get_index(daddr, itf_num);
+
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid, );
 
   if (XFER_RESULT_SUCCESS == xfer->result)
   {
-    hid_itf->protocol_mode = (uint8_t) tu_le16toh(xfer->setup->wValue);
+    p_hid->protocol_mode = (uint8_t) tu_le16toh(xfer->setup->wValue);
   }
 
   if (tuh_hid_set_protocol_complete_cb)
   {
-    tuh_hid_set_protocol_complete_cb(daddr, instance, hid_itf->protocol_mode);
+    tuh_hid_set_protocol_complete_cb(daddr, idx, p_hid->protocol_mode);
   }
 }
 
-
-static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   TU_LOG2("HID Set Protocol = %d\r\n", protocol);
 
@@ -143,7 +202,7 @@ static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protoc
 
   tuh_xfer_t xfer =
   {
-    .daddr       = dev_addr,
+    .daddr       = daddr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
@@ -151,16 +210,15 @@ static bool _hidh_set_protocol(uint8_t dev_addr, uint8_t itf_num, uint8_t protoc
     .user_data   = user_data
   };
 
-  TU_ASSERT( tuh_control_xfer(&xfer) );
-  return true;
+  return tuh_control_xfer(&xfer);
 }
 
-bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol)
+bool tuh_hid_set_protocol(uint8_t daddr, uint8_t idx, uint8_t protocol)
 {
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-  TU_VERIFY(hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE);
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid && p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE);
 
-  return _hidh_set_protocol(dev_addr, hid_itf->itf_num, protocol, set_protocol_complete, 0);
+  return _hidh_set_protocol(daddr, p_hid->itf_num, protocol, set_protocol_complete, 0);
 }
 
 static void set_report_complete(tuh_xfer_t* xfer)
@@ -169,20 +227,22 @@ static void set_report_complete(tuh_xfer_t* xfer)
 
   if (tuh_hid_set_report_complete_cb)
   {
-    uint8_t const itf_num     = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-    uint8_t const instance    = get_instance_id_by_itfnum(xfer->daddr, itf_num);
+    uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+    uint8_t const idx     = tuh_hid_itf_get_index(xfer->daddr, itf_num);
 
     uint8_t const report_type = tu_u16_high(xfer->setup->wValue);
     uint8_t const report_id   = tu_u16_low(xfer->setup->wValue);
 
-    tuh_hid_set_report_complete_cb(xfer->daddr, instance, report_id, report_type,
+    tuh_hid_set_report_complete_cb(xfer->daddr, idx, report_id, report_type,
                                    (xfer->result == XFER_RESULT_SUCCESS) ? xfer->setup->wLength : 0);
   }
 }
 
-bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, void* report, uint16_t len)
+bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len)
 {
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
+
   TU_LOG2("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len);
 
   tusb_control_request_t const request =
@@ -194,14 +254,14 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
       .direction = TUSB_DIR_OUT
     },
     .bRequest = HID_REQ_CONTROL_SET_REPORT,
-    .wValue   = tu_u16(report_type, report_id),
-    .wIndex   = hid_itf->itf_num,
+    .wValue   = tu_htole16(tu_u16(report_type, report_id)),
+    .wIndex   = tu_htole16((uint16_t)p_hid->itf_num),
     .wLength  = len
   };
 
   tuh_xfer_t xfer =
   {
-    .daddr       = dev_addr,
+    .daddr       = daddr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = report,
@@ -209,14 +269,14 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, u
     .user_data   = 0
   };
 
-  TU_ASSERT( tuh_control_xfer(&xfer) );
-  return true;
+  return tuh_control_xfer(&xfer);
 }
 
-static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   // SET IDLE request, device can stall if not support this request
   TU_LOG2("HID Set Idle \r\n");
+
   tusb_control_request_t const request =
   {
     .bmRequestType_bit =
@@ -226,14 +286,14 @@ static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate
       .direction = TUSB_DIR_OUT
     },
     .bRequest = HID_REQ_CONTROL_SET_IDLE,
-    .wValue   = idle_rate,
-    .wIndex   = itf_num,
+    .wValue   = tu_htole16(idle_rate),
+    .wIndex   = tu_htole16((uint16_t)itf_num),
     .wLength  = 0
   };
 
   tuh_xfer_t xfer =
   {
-    .daddr       = dev_addr,
+    .daddr       = daddr,
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
@@ -241,25 +301,24 @@ static bool _hidh_set_idle(uint8_t dev_addr, uint8_t itf_num, uint16_t idle_rate
     .user_data   = user_data
   };
 
-  TU_ASSERT( tuh_control_xfer(&xfer) );
-
-  return true;
+  return tuh_control_xfer(&xfer);
 }
 
 //--------------------------------------------------------------------+
 // Interrupt Endpoint API
 //--------------------------------------------------------------------+
 
-bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance)
+bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx)
 {
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
 
   // claim endpoint
-  TU_VERIFY( usbh_edpt_claim(dev_addr, hid_itf->ep_in) );
+  TU_VERIFY( usbh_edpt_claim(daddr, p_hid->ep_in) );
 
-  if ( !usbh_edpt_xfer(dev_addr, hid_itf->ep_in, hid_itf->epin_buf, hid_itf->epin_size) )
+  if ( !usbh_edpt_xfer(daddr, p_hid->ep_in, p_hid->epin_buf, p_hid->epin_size) )
   {
-    usbh_edpt_release(dev_addr, hid_itf->ep_in);
+    usbh_edpt_release(daddr, p_hid->ep_in);
     return false;
   }
 
@@ -274,44 +333,45 @@ bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance)
 //  return !usbh_edpt_busy(dev_addr, hid_itf->ep_in);
 //}
 
-bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, const void* report, uint16_t len)
+bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len)
 {
   TU_LOG2("HID Send Report %d\r\n", report_id);
 
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
 
-  if (hid_itf->ep_out == 0)
+  if (p_hid->ep_out == 0)
   {
     // This HID does not have an out endpoint (other than control)
     return false;
   }
-  else if (len > CFG_TUH_HID_EPOUT_BUFSIZE
-           || (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1)))
+  else if (len > CFG_TUH_HID_EPOUT_BUFSIZE ||
+           (report_id != 0 && len > (CFG_TUH_HID_EPOUT_BUFSIZE - 1)))
   {
     // ep_out buffer is not large enough to hold contents
     return false;
   }
 
   // claim endpoint
-  TU_VERIFY( usbh_edpt_claim(dev_addr, hid_itf->ep_out) );
+  TU_VERIFY( usbh_edpt_claim(daddr, p_hid->ep_out) );
 
   if (report_id == 0)
   {
     // No report ID in transmission
-    memcpy(&hid_itf->epout_buf[0], report, len);
+    memcpy(&p_hid->epout_buf[0], report, len);
   }
   else
   {
-    hid_itf->epout_buf[0] = report_id;
-    memcpy(&hid_itf->epout_buf[1], report, len);
+    p_hid->epout_buf[0] = report_id;
+    memcpy(&p_hid->epout_buf[1], report, len);
     ++len; // 1 more byte for report_id
   }
 
-  TU_LOG3_MEM(hid_itf->epout_buf, len, 2);
+  TU_LOG3_MEM(p_hid->epout_buf, len, 2);
 
-  if ( !usbh_edpt_xfer(dev_addr, hid_itf->ep_out, hid_itf->epout_buf, len) )
+  if ( !usbh_edpt_xfer(daddr, p_hid->ep_out, p_hid->epout_buf, len) )
   {
-    usbh_edpt_release(dev_addr, hid_itf->ep_out);
+    usbh_edpt_release(daddr, p_hid->ep_out);
     return false;
   }
 
@@ -323,56 +383,57 @@ bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id,
 //--------------------------------------------------------------------+
 void hidh_init(void)
 {
-  tu_memclr(_hidh_dev, sizeof(_hidh_dev));
+  tu_memclr(_hidh_itf, sizeof(_hidh_itf));
 }
 
-bool hidh_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
 {
   (void) result;
 
   uint8_t const dir = tu_edpt_dir(ep_addr);
-  uint8_t const instance = get_instance_id_by_epaddr(dev_addr, ep_addr);
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  uint8_t const idx = get_idx_by_epaddr(daddr, ep_addr);
+
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid);
 
   if ( dir == TUSB_DIR_IN )
   {
-    TU_LOG2("  Get Report callback (%u, %u)\r\n", dev_addr, instance);
-    TU_LOG3_MEM(hid_itf->epin_buf, xferred_bytes, 2);
-    tuh_hid_report_received_cb(dev_addr, instance, hid_itf->epin_buf, (uint16_t) xferred_bytes);
+    TU_LOG2("  Get Report callback (%u, %u)\r\n", daddr, idx);
+    TU_LOG3_MEM(p_hid->epin_buf, xferred_bytes, 2);
+    tuh_hid_report_received_cb(daddr, idx, p_hid->epin_buf, (uint16_t) xferred_bytes);
   }else
   {
-    if (tuh_hid_report_sent_cb) tuh_hid_report_sent_cb(dev_addr, instance, hid_itf->epout_buf, (uint16_t) xferred_bytes);
+    if (tuh_hid_report_sent_cb) tuh_hid_report_sent_cb(daddr, idx, p_hid->epout_buf, (uint16_t) xferred_bytes);
   }
 
   return true;
 }
 
-void hidh_close(uint8_t dev_addr)
+void hidh_close(uint8_t daddr)
 {
-  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
-
-  hidh_device_t* hid_dev = get_dev(dev_addr);
-
-  if (tuh_hid_umount_cb)
+  for(uint8_t i=0; i<CFG_TUH_HID; i++)
   {
-    for (uint8_t inst = 0; inst < hid_dev->inst_count; inst++ ) tuh_hid_umount_cb(dev_addr, inst);
+    hidh_interface_t* p_hid = &_hidh_itf[i];
+    if (p_hid->daddr == daddr)
+    {
+       if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i);
+       p_hid->daddr = 0;
+    }
   }
-
-  tu_memclr(hid_dev, sizeof(hidh_device_t));
 }
 
 //--------------------------------------------------------------------+
 // Enumeration
 //--------------------------------------------------------------------+
 
-bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
+bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
 {
   (void) rhport;
   (void) max_len;
 
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass);
 
-  TU_LOG2("[%u] HID opening Interface %u\r\n", dev_addr, desc_itf->bInterfaceNumber);
+  TU_LOG2("[%u] HID opening Interface %u\r\n", daddr, desc_itf->bInterfaceNumber);
 
   // len = interface + hid + n*endpoints
   uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
@@ -386,12 +447,9 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc;
   TU_ASSERT(HID_DESC_TYPE_HID == desc_hid->bDescriptorType);
 
-  // not enough interface, try to increase CFG_TUH_HID
-  // TODO multiple devices
-  hidh_device_t* hid_dev = get_dev(dev_addr);
-  TU_ASSERT(hid_dev->inst_count < CFG_TUH_HID, 0);
-
-  hidh_interface_t* hid_itf = get_instance(dev_addr, hid_dev->inst_count);
+  hidh_interface_t* p_hid = find_new_itf();
+  TU_ASSERT(p_hid); // not enough interface, try to increase CFG_TUH_HID
+  p_hid->daddr = daddr;
 
   //------------- Endpoint Descriptors -------------//
   p_desc = tu_desc_next(p_desc);
@@ -400,34 +458,35 @@ bool hidh_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   for(int i = 0; i < desc_itf->bNumEndpoints; i++)
   {
     TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType);
-    TU_ASSERT( tuh_edpt_open(dev_addr, desc_ep) );
+    TU_ASSERT( tuh_edpt_open(daddr, desc_ep) );
 
     if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
     {
-      hid_itf->ep_in     = desc_ep->bEndpointAddress;
-      hid_itf->epin_size = tu_edpt_packet_size(desc_ep);
+      p_hid->ep_in     = desc_ep->bEndpointAddress;
+      p_hid->epin_size = tu_edpt_packet_size(desc_ep);
     }
     else
     {
-      hid_itf->ep_out     = desc_ep->bEndpointAddress;
-      hid_itf->epout_size = tu_edpt_packet_size(desc_ep);
+      p_hid->ep_out     = desc_ep->bEndpointAddress;
+      p_hid->epout_size = tu_edpt_packet_size(desc_ep);
     }
 
     p_desc = tu_desc_next(p_desc);
     desc_ep = (tusb_desc_endpoint_t const *) p_desc;
   }
 
-  hid_dev->inst_count++;
-
-  hid_itf->itf_num   = desc_itf->bInterfaceNumber;
+  p_hid->itf_num   = desc_itf->bInterfaceNumber;
 
   // Assume bNumDescriptors = 1
-  hid_itf->report_desc_type = desc_hid->bReportType;
-  hid_itf->report_desc_len  = tu_unaligned_read16(&desc_hid->wReportLength);
+  p_hid->report_desc_type = desc_hid->bReportType;
+  p_hid->report_desc_len  = tu_unaligned_read16(&desc_hid->wReportLength);
 
   // Per HID Specs: default is Report protocol, though we will force Boot protocol when set_config
-  hid_itf->protocol_mode = HID_PROTOCOL_BOOT;
-  if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass ) hid_itf->itf_protocol = desc_itf->bInterfaceProtocol;
+  p_hid->protocol_mode = HID_PROTOCOL_BOOT;
+  if ( HID_SUBCLASS_BOOT == desc_itf->bInterfaceSubClass )
+  {
+    p_hid->itf_protocol = desc_itf->bInterfaceProtocol;
+  }
 
   return true;
 }
@@ -443,16 +502,16 @@ enum {
   CONFIG_COMPLETE
 };
 
-static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len);
+static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len);
 static void process_set_config(tuh_xfer_t* xfer);
 
-bool hidh_set_config(uint8_t dev_addr, uint8_t itf_num)
+bool hidh_set_config(uint8_t daddr, uint8_t itf_num)
 {
   tusb_control_request_t request;
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
   tuh_xfer_t xfer;
-  xfer.daddr     = dev_addr;
+  xfer.daddr     = daddr;
   xfer.result    = XFER_RESULT_SUCCESS;
   xfer.setup     = &request;
   xfer.user_data = CONFG_SET_IDLE;
@@ -477,8 +536,9 @@ static void process_set_config(tuh_xfer_t* xfer)
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const daddr   = xfer->daddr;
 
-  uint8_t const instance    = get_instance_id_by_itfnum(daddr, itf_num);
-  hidh_interface_t* hid_itf = get_instance(daddr, instance);
+  uint8_t const idx       = tuh_hid_itf_get_index(daddr, itf_num);
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid, );
 
   switch(state)
   {
@@ -486,27 +546,27 @@ static void process_set_config(tuh_xfer_t* xfer)
     {
       // Idle rate = 0 mean only report when there is changes
       const uint16_t idle_rate = 0;
-      const uintptr_t next_state = (hid_itf->itf_protocol != HID_ITF_PROTOCOL_NONE) ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC;
+      const uintptr_t next_state = (p_hid->itf_protocol != HID_ITF_PROTOCOL_NONE) ? CONFIG_SET_PROTOCOL : CONFIG_GET_REPORT_DESC;
       _hidh_set_idle(daddr, itf_num, idle_rate, process_set_config, next_state);
     }
     break;
 
     case CONFIG_SET_PROTOCOL:
-      _hidh_set_protocol(daddr, hid_itf->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC);
+      _hidh_set_protocol(daddr, p_hid->itf_num, HID_PROTOCOL_BOOT, process_set_config, CONFIG_GET_REPORT_DESC);
     break;
 
     case CONFIG_GET_REPORT_DESC:
       // Get Report Descriptor if possible
       // using usbh enumeration buffer since report descriptor can be very long
-      if( hid_itf->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE )
+      if( p_hid->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE )
       {
-        TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", hid_itf->report_desc_len);
+        TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", p_hid->report_desc_len);
 
         // Driver is mounted without report descriptor
-        config_driver_mount_complete(daddr, instance, NULL, 0);
+        config_driver_mount_complete(daddr, idx, NULL, 0);
       }else
       {
-        tuh_descriptor_get_hid_report(daddr, itf_num, hid_itf->report_desc_type, 0, usbh_get_enum_buf(), hid_itf->report_desc_len, process_set_config, CONFIG_COMPLETE);
+        tuh_descriptor_get_hid_report(daddr, itf_num, p_hid->report_desc_type, 0, usbh_get_enum_buf(), p_hid->report_desc_len, process_set_config, CONFIG_COMPLETE);
       }
       break;
 
@@ -515,7 +575,7 @@ static void process_set_config(tuh_xfer_t* xfer)
       uint8_t const* desc_report = usbh_get_enum_buf();
       uint16_t const desc_len    = tu_le16toh(xfer->setup->wLength);
 
-      config_driver_mount_complete(daddr, instance, desc_report, desc_len);
+      config_driver_mount_complete(daddr, idx, desc_report, desc_len);
     }
     break;
 
@@ -523,15 +583,16 @@ static void process_set_config(tuh_xfer_t* xfer)
   }
 }
 
-static void config_driver_mount_complete(uint8_t dev_addr, uint8_t instance, uint8_t const* desc_report, uint16_t desc_len)
+static void config_driver_mount_complete(uint8_t daddr, uint8_t idx, uint8_t const* desc_report, uint16_t desc_len)
 {
-  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid, );
 
   // enumeration is complete
-  tuh_hid_mount_cb(dev_addr, instance, desc_report, desc_len);
+  if (tuh_hid_mount_cb) tuh_hid_mount_cb(daddr, idx, desc_report, desc_len);
 
   // notify usbh that driver enumeration is complete
-  usbh_driver_set_config_complete(dev_addr, hid_itf->itf_num);
+  usbh_driver_set_config_complete(daddr, p_hid->itf_num);
 }
 
 //--------------------------------------------------------------------+
@@ -676,46 +737,4 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr,
   return report_num;
 }
 
-//--------------------------------------------------------------------+
-// Helper
-//--------------------------------------------------------------------+
-
-// Get Device by address
-TU_ATTR_ALWAYS_INLINE static inline hidh_device_t* get_dev(uint8_t dev_addr)
-{
-  return &_hidh_dev[dev_addr-1];
-}
-
-// Get Interface by instance number
-TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_instance(uint8_t dev_addr, uint8_t instance)
-{
-  return &_hidh_dev[dev_addr-1].instances[instance];
-}
-
-// Get instance ID by interface number
-static uint8_t get_instance_id_by_itfnum(uint8_t dev_addr, uint8_t itf)
-{
-  for ( uint8_t inst = 0; inst < CFG_TUH_HID; inst++ )
-  {
-    hidh_interface_t *hid = get_instance(dev_addr, inst);
-
-    if ( (hid->itf_num == itf) && (hid->ep_in || hid->ep_out) ) return inst;
-  }
-
-  return 0xff;
-}
-
-// Get instance ID by endpoint address
-static uint8_t get_instance_id_by_epaddr(uint8_t dev_addr, uint8_t ep_addr)
-{
-  for ( uint8_t inst = 0; inst < CFG_TUH_HID; inst++ )
-  {
-    hidh_interface_t *hid = get_instance(dev_addr, inst);
-
-    if ( (ep_addr == hid->ep_in) || ( ep_addr == hid->ep_out) ) return inst;
-  }
-
-  return 0xff;
-}
-
 #endif
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index c152e527a..f808f36d4 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -62,14 +62,24 @@ typedef struct
 // Interface API
 //--------------------------------------------------------------------+
 
-// Get the number of HID instances
-uint8_t tuh_hid_instance_count(uint8_t dev_addr);
+// Get the number of mounted HID interfaces of a device
+uint8_t tuh_hid_itf_get_count(uint8_t dev_addr);
 
-// Check if HID instance is mounted
-bool tuh_hid_mounted(uint8_t dev_addr, uint8_t instance);
+// Get all mounted interfaces across devices
+uint8_t tuh_hid_itf_get_total_count(void);
+
+// backward compatible rename
+#define tuh_hid_instance_count    tuh_hid_itf_get_count
+
+// Check if HID interface is mounted
+bool tuh_hid_mounted(uint8_t dev_addr, uint8_t idx);
+
+// Get Interface index from device address + interface number
+// return TUSB_INDEX_INVALID_8 (0xFF) if not found
+uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num);
 
 // Get interface supported protocol (bInterfaceProtocol) check out hid_interface_protocol_enum_t for possible values
-uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t instance);
+uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t idx);
 
 // Parse report descriptor into array of report_info struct and return number of reports.
 // For complicated report, application should write its own parser.
@@ -82,31 +92,31 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr,
 // Get current protocol: HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
 // Note: Device will be initialized in Boot protocol for simplicity.
 //       Application can use set_protocol() to switch back to Report protocol.
-uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t instance);
+uint8_t tuh_hid_get_protocol(uint8_t dev_addr, uint8_t idx);
 
 // Set protocol to HID_PROTOCOL_BOOT (0) or HID_PROTOCOL_REPORT (1)
 // This function is only supported by Boot interface (tuh_n_hid_interface_protocol() != NONE)
-bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t instance, uint8_t protocol);
+bool tuh_hid_set_protocol(uint8_t dev_addr, uint8_t idx, uint8_t protocol);
 
 // Set Report using control endpoint
 // report_type is either Input, Output or Feature, (value from hid_report_type_t)
-bool tuh_hid_set_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, void* report, uint16_t len);
+bool tuh_hid_set_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, void* report, uint16_t len);
 
 //--------------------------------------------------------------------+
 // Interrupt Endpoint API
 //--------------------------------------------------------------------+
 
 // Check if the interface is ready to use
-//bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t instance);
+//bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t idx);
 
 // Try to receive next report on Interrupt Endpoint. Immediately return
 // - true If succeeded, tuh_hid_report_received_cb() callback will be invoked when report is available
 // - false if failed to queue the transfer e.g endpoint is busy
-bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t instance);
+bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t idx);
 
 // Send report using interrupt endpoint
 // If report_id > 0 (composite), it will be sent as 1st byte, then report contents. Otherwise only report content is sent.
-bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id, const void* report, uint16_t len);
+bool tuh_hid_send_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len);
 
 //--------------------------------------------------------------------+
 // Callbacks (Weak is optional)
@@ -117,24 +127,24 @@ bool tuh_hid_send_report(uint8_t dev_addr, uint8_t instance, uint8_t report_id,
 // can be used to parse common/simple enough descriptor.
 // Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
 // therefore report_desc = NULL, desc_len = 0
-void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report_desc, uint16_t desc_len);
+TU_ATTR_WEAK void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* report_desc, uint16_t desc_len);
 
 // Invoked when device with hid interface is un-mounted
-TU_ATTR_WEAK void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance);
+TU_ATTR_WEAK void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t idx);
 
 // Invoked when received report from device via interrupt endpoint
 // Note: if there is report ID (composite), it is 1st byte of report
-void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len);
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* report, uint16_t len);
 
 // Invoked when sent report to device successfully via interrupt endpoint
-TU_ATTR_WEAK void tuh_hid_report_sent_cb(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len);
+TU_ATTR_WEAK void tuh_hid_report_sent_cb(uint8_t dev_addr, uint8_t idx, uint8_t const* report, uint16_t len);
 
 // Invoked when Sent Report to device via either control endpoint
 // len = 0 indicate there is error in the transfer e.g stalled response
-TU_ATTR_WEAK void tuh_hid_set_report_complete_cb(uint8_t dev_addr, uint8_t instance, uint8_t report_id, uint8_t report_type, uint16_t len);
+TU_ATTR_WEAK void tuh_hid_set_report_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_t report_type, uint16_t len);
 
 // Invoked when Set Protocol request is complete
-TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t instance, uint8_t protocol);
+TU_ATTR_WEAK void tuh_hid_set_protocol_complete_cb(uint8_t dev_addr, uint8_t idx, uint8_t protocol);
 
 //--------------------------------------------------------------------+
 // Internal Class Driver API

From a97f39151ebdf5569ff4831902648c518821a25c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Mar 2023 08:33:30 +0700
Subject: [PATCH 1599/2085] fine tune CFG_TUH_HID value

---
 examples/dual/host_hid_to_device_cdc/src/tusb_config.h | 2 +-
 examples/host/cdc_msc_hid/src/tusb_config.h            | 2 +-
 examples/host/hid_controller/src/tusb_config.h         | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
index 72ec8d654..604cc6681 100644
--- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
+++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
@@ -132,7 +132,7 @@
 // max device support (excluding hub device)
 #define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
 
-#define CFG_TUH_HID                 (4*CFG_TUH_DEVICE_MAX)
+#define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX)
 #define CFG_TUH_HID_EPIN_BUFSIZE    64
 #define CFG_TUH_HID_EPOUT_BUFSIZE   64
 
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index a0a740c6e..6d5933bca 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -97,7 +97,7 @@
 
 #define CFG_TUH_HUB                 1 // number of supported hubs
 #define CFG_TUH_CDC                 1
-#define CFG_TUH_HID                 (4*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
 
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index f4ddc1b81..f5ae2fd6f 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -97,7 +97,7 @@
 
 #define CFG_TUH_HUB                 0
 #define CFG_TUH_CDC                 0
-#define CFG_TUH_HID                 (4*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 0
 #define CFG_TUH_VENDOR              0
 

From 0921edaf5924d498e8115815dc23acfb1decb7a0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Mar 2023 09:23:11 +0700
Subject: [PATCH 1600/2085] use tud_inited() instead of tusb_inited()

---
 src/device/usbd.c                                | 4 ++--
 test/unit-test/test/device/msc/test_msc_device.c | 2 +-
 test/unit-test/test/device/usbd/test_usbd.c      | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 0fb236a88..cee56af60 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -450,7 +450,7 @@ static void usbd_reset(uint8_t rhport)
 bool tud_task_event_ready(void)
 {
   // Skip if stack is not initialized
-  if ( !tusb_inited() ) return false;
+  if ( !tud_inited() ) return false;
 
   return !osal_queue_empty(_usbd_q);
 }
@@ -478,7 +478,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
   (void) in_isr; // not implemented yet
 
   // Skip if stack is not initialized
-  if ( !tusb_inited() ) return;
+  if ( !tud_inited() ) return;
 
   // Loop until there is no more events in the queue
   while (1)
diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c
index c757cdcfa..a62418524 100644
--- a/test/unit-test/test/device/msc/test_msc_device.c
+++ b/test/unit-test/test/device/msc/test_msc_device.c
@@ -197,7 +197,7 @@ void setUp(void)
   dcd_int_disable_Ignore();
   dcd_int_enable_Ignore();
 
-  if ( !tusb_inited() )
+  if ( !tud_inited() )
   {
     dcd_init_Expect(rhport);
     tusb_init();
diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c
index dcded605a..00950c5a9 100644
--- a/test/unit-test/test/device/usbd/test_usbd.c
+++ b/test/unit-test/test/device/usbd/test_usbd.c
@@ -124,7 +124,7 @@ void setUp(void)
   dcd_int_disable_Ignore();
   dcd_int_enable_Ignore();
 
-  if ( !tusb_inited() )
+  if ( !tud_inited() )
   {
     mscd_init_Expect();
     dcd_init_Expect(rhport);

From f8a5cde3c7fde62c3d6bd379fea6eaa9a629ded6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Mar 2023 09:23:44 +0700
Subject: [PATCH 1601/2085] add tuh_task_event_ready(), better implement
 blocking control transfer for rtos

---
 src/host/usbh.c | 22 +++++++++++++++-------
 src/host/usbh.h | 10 ++++++++++
 2 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index dc347c458..3eff0830a 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -360,6 +360,14 @@ bool tuh_init(uint8_t controller_id)
   return true;
 }
 
+bool tuh_task_event_ready(void)
+{
+  // Skip if stack is not initialized
+  if ( !tuh_inited() ) return false;
+
+  return !osal_queue_empty(_usbh_q);
+}
+
 /* USB Host Driver task
  * This top level thread manages all host controller event and delegates events to class-specific drivers.
  * This should be called periodically within the mainloop or rtos thread.
@@ -383,7 +391,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
   (void) in_isr; // not implemented yet
 
   // Skip if stack is not initialized
-  if ( !tusb_inited() ) return;
+  if ( !tuh_inited() ) return;
 
   // Loop until there is no more events in the queue
   while (1)
@@ -565,12 +573,12 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
 
     while (result == XFER_RESULT_INVALID)
     {
-      // only need to call task if not preempted RTOS
-      #if CFG_TUSB_OS == OPT_OS_NONE || CFG_TUSB_OS == OPT_OS_PICO
-      tuh_task();
-      #else
-      osal_task_delay(1); // TODO maybe yield()
-      #endif
+      // Note: this can be called within an callback ie. part of tuh_task()
+      // therefore event with RTOS tuh_task() still need to be invoked
+      if (tuh_task_event_ready())
+      {
+        tuh_task();
+      }
 
       // TODO probably some timeout to prevent hanged
     }
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 125d8f4c9..0f969a46a 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -69,6 +69,13 @@ struct tuh_xfer_s
   // uint32_t timeout_ms;    // place holder, not supported yet
 };
 
+// Subject to change
+typedef struct
+{
+  uint8_t daddr;
+  tusb_desc_interface_t desc;
+} tuh_itf_info_t;
+
 // ConfigID for tuh_config()
 enum
 {
@@ -118,6 +125,9 @@ void tuh_task(void)
   tuh_task_ext(UINT32_MAX, false);
 }
 
+// Check if there is pending events need processing by tuh_task()
+bool tuh_task_event_ready(void);
+
 #ifndef _TUSB_HCD_H_
 extern void hcd_int_handler(uint8_t rhport);
 #endif

From f27486e19abcc020c93c0c938c71e3692c21b9f5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Mar 2023 10:00:42 +0700
Subject: [PATCH 1602/2085] add tuh_hid_itf_get_info() and change
 tuh_cdc_itf_get_info() to use new tuh_itf_info_t

---
 .pre-commit-config.yaml                 |  2 +-
 examples/host/cdc_msc_hid/src/cdc_app.c |  8 ++++----
 src/class/cdc/cdc_host.c                | 20 +++++++++++++++-----
 src/class/cdc/cdc_host.h                | 10 +---------
 src/class/hid/hid_host.c                | 23 +++++++++++++++++++++++
 src/class/hid/hid_host.h                |  7 +++++--
 tools/build_family.py                   |  4 ++--
 tools/get_deps.py                       |  8 +++++++-
 8 files changed, 58 insertions(+), 24 deletions(-)

diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index 7fa6f52ee..d37c27d40 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -15,7 +15,7 @@ repos:
   rev: v2.2.4
   hooks:
   - id: codespell
-    #args: [-w]
+    args: [-w]
     exclude: ^lib/
 
 - repo: local
diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index b1b137e0e..7769d109e 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -87,10 +87,10 @@ void tuh_cdc_rx_cb(uint8_t idx)
 
 void tuh_cdc_mount_cb(uint8_t idx)
 {
-  tuh_cdc_itf_info_t itf_info = { 0 };
+  tuh_itf_info_t itf_info = { 0 };
   tuh_cdc_itf_get_info(idx, &itf_info);
 
-  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
+  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
 
 #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
   // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
@@ -106,8 +106,8 @@ void tuh_cdc_mount_cb(uint8_t idx)
 
 void tuh_cdc_umount_cb(uint8_t idx)
 {
-  tuh_cdc_itf_info_t itf_info = { 0 };
+  tuh_itf_info_t itf_info = { 0 };
   tuh_cdc_itf_get_info(idx, &itf_info);
 
-  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.bInterfaceNumber);
+  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
 }
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index d34662cb7..fee314823 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -127,15 +127,25 @@ uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num)
   return TUSB_INDEX_INVALID_8;
 }
 
-bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info)
+bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && info);
 
-  info->daddr              = p_cdc->daddr;
-  info->bInterfaceNumber   = p_cdc->bInterfaceNumber;
-  info->bInterfaceSubClass = p_cdc->bInterfaceSubClass;
-  info->bInterfaceProtocol = p_cdc->bInterfaceProtocol;
+  info->daddr = p_cdc->daddr;
+
+  // re-construct descriptor
+  tusb_desc_interface_t* desc = &info->desc;
+  desc->bLength            = sizeof(tusb_desc_interface_t);
+  desc->bDescriptorType    = TUSB_DESC_INTERFACE;
+
+  desc->bInterfaceNumber   = p_cdc->bInterfaceNumber;
+  desc->bAlternateSetting  = 0;
+  desc->bNumEndpoints      = 2u + (p_cdc->ep_notif ? 1u : 0u);
+  desc->bInterfaceClass    = TUSB_CLASS_CDC;
+  desc->bInterfaceSubClass = p_cdc->bInterfaceSubClass;
+  desc->bInterfaceProtocol = p_cdc->bInterfaceProtocol;
+  desc->iInterface         = 0; // not used yet
 
   return true;
 }
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 03f32e542..a1e78f158 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -71,21 +71,13 @@
 // Application API
 //--------------------------------------------------------------------+
 
-typedef struct
-{
-  uint8_t daddr;
-  uint8_t bInterfaceNumber;
-  uint8_t bInterfaceSubClass;
-  uint8_t bInterfaceProtocol;
-} tuh_cdc_itf_info_t;
-
 // Get Interface index from device address + interface number
 // return TUSB_INDEX_INVALID_8 (0xFF) if not found
 uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num);
 
 // Get Interface information
 // return true if index is correct and interface is currently mounted
-bool tuh_cdc_itf_get_info(uint8_t idx, tuh_cdc_itf_info_t* info);
+bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info);
 
 // Check if a interface is mounted
 bool tuh_cdc_mounted(uint8_t idx);
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index f65b2dc20..20373f541 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -134,6 +134,29 @@ bool tuh_hid_mounted(uint8_t daddr, uint8_t idx)
   return p_hid != NULL;
 }
 
+bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* info)
+{
+  hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
+  TU_VERIFY(p_hid && info);
+
+  info->daddr = daddr;
+
+  // re-construct descriptor
+  tusb_desc_interface_t* desc = &info->desc;
+  desc->bLength            = sizeof(tusb_desc_interface_t);
+  desc->bDescriptorType    = TUSB_DESC_INTERFACE;
+
+  desc->bInterfaceNumber   = p_hid->itf_num;
+  desc->bAlternateSetting  = 0;
+  desc->bNumEndpoints      = (uint8_t) ((p_hid->ep_in ? 1u : 0u) + (p_hid->ep_out ? 1u : 0u));
+  desc->bInterfaceClass    = TUSB_CLASS_HID;
+  desc->bInterfaceSubClass = (p_hid->itf_protocol ? HID_SUBCLASS_BOOT : HID_SUBCLASS_NONE);
+  desc->bInterfaceProtocol = p_hid->itf_protocol;
+  desc->iInterface         = 0; // not used yet
+
+  return true;
+}
+
 uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num)
 {
   for ( uint8_t idx = 0; idx < CFG_TUH_HID; idx++ )
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index f808f36d4..c0c727e6a 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -71,8 +71,8 @@ uint8_t tuh_hid_itf_get_total_count(void);
 // backward compatible rename
 #define tuh_hid_instance_count    tuh_hid_itf_get_count
 
-// Check if HID interface is mounted
-bool tuh_hid_mounted(uint8_t dev_addr, uint8_t idx);
+// Get Interface information
+bool tuh_hid_itf_get_info(uint8_t daddr, uint8_t idx, tuh_itf_info_t* itf_info);
 
 // Get Interface index from device address + interface number
 // return TUSB_INDEX_INVALID_8 (0xFF) if not found
@@ -81,6 +81,9 @@ uint8_t tuh_hid_itf_get_index(uint8_t daddr, uint8_t itf_num);
 // Get interface supported protocol (bInterfaceProtocol) check out hid_interface_protocol_enum_t for possible values
 uint8_t tuh_hid_interface_protocol(uint8_t dev_addr, uint8_t idx);
 
+// Check if HID interface is mounted
+bool tuh_hid_mounted(uint8_t dev_addr, uint8_t idx);
+
 // Parse report descriptor into array of report_info struct and return number of reports.
 // For complicated report, application should write its own parser.
 uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* reports_info_arr, uint8_t arr_count, uint8_t const* desc_report, uint16_t desc_len) TU_ATTR_UNUSED;
diff --git a/tools/build_family.py b/tools/build_family.py
index cdc099691..532938d42 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -34,7 +34,6 @@ def build_family(example, family, make_option):
         # sum all element of same index (column sum)
         return list(map(sum, list(zip(*result))))
 
-
 if __name__ == '__main__':
     # IAR CC
     if make_iar_option not in sys.argv:
@@ -68,7 +67,8 @@ if __name__ == '__main__':
         print(build_separator)
         for family in all_families:
             fret = build_family(example, family, make_iar_option)
-            total_result = list(map(lambda x, y: x + y, total_result, fret))
+            if len(fret) == len(total_result):
+                total_result = [total_result[i] + fret[i] for i in range(len(fret))]
 
     total_time = time.monotonic() - total_time
     print(build_separator)
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 8bf56cd8d..4b81d1468 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -105,7 +105,13 @@ def get_a_dep(d):
 
 if __name__ == "__main__":
     status = 0
-    deps = list(deps_mandatory.keys()) + sys.argv[1:]
+    deps = list(deps_mandatory.keys())
+    # get all if executed with all as argument
+    if len(sys.argv) == 2 and sys.argv[1] == 'all':
+        deps += deps_optional
+    else:
+        deps += sys.argv[1:]
+
     with Pool() as pool:
         status = sum(pool.map(get_a_dep, deps))
     sys.exit(status)

From c85f46c4ab8c680eb02e6a964cf3afadf2301328 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Mar 2023 16:59:57 +0700
Subject: [PATCH 1603/2085] fix bitorder in usbtmc_response_capabilities_488_t

---
 src/class/usbtmc/usbtmc.h | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h
index 3c5e86d4c..1b3c3ab6d 100644
--- a/src/class/usbtmc/usbtmc.h
+++ b/src/class/usbtmc/usbtmc.h
@@ -277,17 +277,17 @@ typedef struct TU_ATTR_PACKED
 
   struct TU_ATTR_PACKED
   {
-    unsigned int is488_2 :1;
-    unsigned int supportsREN_GTL_LLO :1;
-    unsigned int supportsTrigger :1;
+    uint8_t supportsTrigger :1;
+    uint8_t supportsREN_GTL_LLO :1;
+    uint8_t is488_2 :1;
   } bmIntfcCapabilities488;
 
   struct TU_ATTR_PACKED
   {
-    unsigned int SCPI :1;
-    unsigned int SR1 :1;
-    unsigned int RL1 :1;
-    unsigned int DT1 :1;
+    uint8_t DT1 :1;
+    uint8_t RL1 :1;
+    uint8_t SR1 :1;
+    uint8_t SCPI :1;
   } bmDevCapabilities488;
   uint8_t _reserved3[8];
 } usbtmc_response_capabilities_488_t;

From 096da11e88cd9d4714db9590955fb7db62edb75e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 22 Mar 2023 17:01:04 +0700
Subject: [PATCH 1604/2085] more update

---
 src/class/usbtmc/usbtmc.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/class/usbtmc/usbtmc.h b/src/class/usbtmc/usbtmc.h
index 1b3c3ab6d..090ab3c4a 100644
--- a/src/class/usbtmc/usbtmc.h
+++ b/src/class/usbtmc/usbtmc.h
@@ -262,14 +262,14 @@ typedef struct TU_ATTR_PACKED
 
   struct TU_ATTR_PACKED
   {
-    unsigned int listenOnly :1;
-    unsigned int talkOnly :1;
-    unsigned int supportsIndicatorPulse :1;
+    uint8_t listenOnly :1;
+    uint8_t talkOnly :1;
+    uint8_t supportsIndicatorPulse :1;
   } bmIntfcCapabilities;
 
   struct TU_ATTR_PACKED
   {
-    unsigned int canEndBulkInOnTermChar :1;
+    uint8_t canEndBulkInOnTermChar :1;
   } bmDevCapabilities;
 
   uint8_t _reserved2[6];

From 4274cab3950cfa30b387bab7d388b6a4b8480edb Mon Sep 17 00:00:00 2001
From: Matt Mills <mmills@2bn.net>
Date: Wed, 22 Mar 2023 07:18:27 -0600
Subject: [PATCH 1605/2085] Update net_device.h

---
 src/class/net/net_device.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h
index 133689deb..399916355 100644
--- a/src/class/net/net_device.h
+++ b/src/class/net/net_device.h
@@ -94,7 +94,7 @@ void tud_network_init_cb(void);
 
 // client must provide this: 48-bit MAC address
 // TODO removed later since it is not part of tinyusb stack
-extern const uint8_t tud_network_mac_address[6];
+extern uint8_t tud_network_mac_address[6];
 
 //------------- NCM -------------//
 

From 033627ee4118b5015f1d31b88b8c4fcbad14292d Mon Sep 17 00:00:00 2001
From: Matt Mills <mmills@2bn.net>
Date: Wed, 22 Mar 2023 07:30:46 -0600
Subject: [PATCH 1606/2085] Remove const from tud_network_mac_address in
 example and test files

---
 examples/device/net_lwip_webserver/src/main.c | 2 +-
 test/fuzz/net_fuzz.cc                         | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 88081ffe2..19a0eae9d 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -64,7 +64,7 @@ static struct pbuf *received_frame;
 /* this is used by this code, ./class/net/net_driver.c, and usb_descriptors.c */
 /* ideally speaking, this should be generated from the hardware's unique ID (if available) */
 /* it is suggested that the first byte is 0x02 to indicate a link-local address */
-const uint8_t tud_network_mac_address[6] = {0x02,0x02,0x84,0x6A,0x96,0x00};
+uint8_t tud_network_mac_address[6] = {0x02,0x02,0x84,0x6A,0x96,0x00};
 
 /* network parameters of this MCU */
 static const ip4_addr_t ipaddr  = INIT_IP4(192, 168, 7, 1);
diff --git a/test/fuzz/net_fuzz.cc b/test/fuzz/net_fuzz.cc
index 3158e74ef..63cd1ac98 100644
--- a/test/fuzz/net_fuzz.cc
+++ b/test/fuzz/net_fuzz.cc
@@ -67,7 +67,7 @@ void tud_network_init_cb(void) {
 
 // client must provide this: 48-bit MAC address
 // TODO removed later since it is not part of tinyusb stack
-const uint8_t tud_network_mac_address[6] = {0};
+uint8_t tud_network_mac_address[6] = {0};
 
 //------------- NCM -------------//
 

From 4cee79af274c999b885b05c79ab1082c01dcc25a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 23 Mar 2023 13:08:09 +0700
Subject: [PATCH 1607/2085] rename and change default pio usb pin to adafruit
 feather usb host

---
 examples/host/cdc_msc_hid/src/tusb_config.h |  2 +-
 hw/bsp/rp2040/board.h                       | 25 ++++++++++++++++-----
 hw/bsp/rp2040/family.c                      |  8 +++----
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 6d5933bca..6c5e68a87 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -36,7 +36,7 @@
 
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
 // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB   1
+#define CFG_TUH_RPI_PIO_USB   0
 #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
 #endif
 
diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index 1eeeaf9af..ccad00c4a 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -31,6 +31,7 @@
  extern "C" {
 #endif
 
+// LED
 #ifdef PICO_DEFAULT_LED_PIN
 #define LED_PIN               PICO_DEFAULT_LED_PIN
 #define LED_STATE_ON          (!(PICO_DEFAULT_LED_PIN_INVERTED))
@@ -40,6 +41,7 @@
 #define BUTTON_BOOTSEL
 #define BUTTON_STATE_ACTIVE   0
 
+// UART
 #if defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) && \
     defined(PICO_DEFAULT_UART) && defined(LIB_PICO_STDIO_UART)
 #define UART_DEV              PICO_DEFAULT_UART
@@ -47,16 +49,27 @@
 #define UART_RX_PIN           PICO_DEFAULT_UART_RX_PIN
 #endif
 
-// PIO_USB_DP_PIN_DEFAULT is 0, which conflict with UART, change to other pin
-#ifndef PIO_USB_DP_PIN
-#define PIO_USB_DP_PIN        20
+// PIO_USB
+
+// #define USE_ADAFRUIT_RP2040_TESTER
+#ifdef USE_ADAFRUIT_RP2040_TESTER
+#define PICO_DEFAULT_PIO_USB_DP_PIN       20
+#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN   22
+#endif
+
+// following default to pin on Adafruit Feather rp2040 USB Host
+#ifndef PICO_DEFAULT_PIO_USB_DP_PIN
+#define PICO_DEFAULT_PIO_USB_DP_PIN       16
 #endif
 
 // VBUS enable pin and its active state
-#define PIO_USB_VBUSEN_PIN    22
+#ifndef PICO_DEFAULT_PIO_USB_VBUSEN_PIN
+#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN   18
+#endif
 
-#ifndef PIO_USB_VBUSEN_STATE
-#define PIO_USB_VBUSEN_STATE  1
+// VBUS enable state
+#ifndef PICO_DEFAULT_PIO_USB_VBUSEN_STATE
+#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1
 #endif
 
 #ifdef __cplusplus
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index f9fa88ac4..920869585 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -126,15 +126,15 @@ void board_init(void)
   set_sys_clock_khz(120000, true);
 
 #ifdef PIO_USB_VBUSEN_PIN
-  gpio_init(PIO_USB_VBUSEN_PIN);
-  gpio_set_dir(PIO_USB_VBUSEN_PIN, GPIO_OUT);
-  gpio_put(PIO_USB_VBUSEN_PIN, PIO_USB_VBUSEN_STATE);
+  gpio_init(PICO_DEFAULT_PIO_USB_VBUSEN_PIN);
+  gpio_set_dir(PICO_DEFAULT_PIO_USB_VBUSEN_PIN, GPIO_OUT);
+  gpio_put(PICO_DEFAULT_PIO_USB_VBUSEN_PIN, PIO_USB_VBUSEN_STATE);
 #endif
 
   // rp2040 use pico-pio-usb for host tuh_configure() can be used to passed pio configuration to the host stack
   // Note: tuh_configure() must be called before tuh_init()
   pio_usb_configuration_t pio_cfg = PIO_USB_DEFAULT_CONFIG;
-  pio_cfg.pin_dp = PIO_USB_DP_PIN;
+  pio_cfg.pin_dp = PICO_DEFAULT_PIO_USB_DP_PIN;
   tuh_configure(BOARD_TUH_RHPORT, TUH_CFGID_RPI_PIO_USB_CONFIGURATION, &pio_cfg);
 #endif
 

From f80d11301ea03746d86dd64c651b31bd600772f7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 23 Mar 2023 16:33:35 +0700
Subject: [PATCH 1608/2085] update doc and generate deps list

---
 README.rst                         |  2 +
 docs/reference/dependencies.rst    | 64 ++++++++++++++++++++++++++++++
 docs/reference/getting_started.rst | 22 +++++-----
 docs/reference/index.rst           |  1 +
 tools/gen_doc.py                   | 33 +++++++++++++++
 5 files changed, 109 insertions(+), 13 deletions(-)
 create mode 100644 docs/reference/dependencies.rst
 create mode 100644 tools/gen_doc.py

diff --git a/README.rst b/README.rst
index adca22433..ef441a596 100644
--- a/README.rst
+++ b/README.rst
@@ -112,6 +112,7 @@ Docs
 
   - `Supported Devices`_
   - `Getting Started`_
+  - `Dependencies`_
   - `Concurrency`_
 
 - `Contributing`_
@@ -146,6 +147,7 @@ in your project.
 .. _Reference: docs/reference/index.rst
 .. _Supported Devices: docs/reference/supported.rst
 .. _Getting Started: docs/reference/getting_started.rst
+.. _Dependencies: docs/reference/dependencies.rst
 .. _Concurrency: docs/reference/concurrency.rst
 .. _Contributing: docs/contributing/index.rst
 .. _Code of Conduct: CODE_OF_CONDUCT.rst
diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst
new file mode 100644
index 000000000..130527e2c
--- /dev/null
+++ b/docs/reference/dependencies.rst
@@ -0,0 +1,64 @@
+************
+Dependencies
+************
+
+MCU low-level peripheral driver and external libraries for building TinyUSB examples
+
+========================================  ==============================================================  ========================================
+Path                                      Project                                                         Commit
+========================================  ==============================================================  ========================================
+hw/mcu/allwinner                          https://github.com/hathach/allwinner_driver.git                 8e5e89e8e132c0fd90e72d5422e5d3d68232b756
+hw/mcu/bridgetek/ft9xx/ft90x-sdk          https://github.com/BRTSG-FOSS/ft90x-sdk.git                     91060164afe239fcb394122e8bf9eb24d3194eb1
+hw/mcu/broadcom                           https://github.com/adafruit/broadcom-peripherals.git            08370086080759ed54ac1136d62d2ad24c6fa267
+hw/mcu/gd/nuclei-sdk                      https://github.com/Nuclei-Software/nuclei-sdk.git               7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7
+hw/mcu/infineon/mtb-xmclib-cat3           https://github.com/Infineon/mtb-xmclib-cat3.git                 daf5500d03cba23e68c2f241c30af79cd9d63880
+hw/mcu/microchip                          https://github.com/hathach/microchip_driver.git                 9e8b37e307d8404033bb881623a113931e1edf27
+hw/mcu/mindmotion/mm32sdk                 https://github.com/hathach/mm32sdk.git                          0b79559eb411149d36e073c1635c620e576308d4
+hw/mcu/nordic/nrfx                        https://github.com/NordicSemiconductor/nrfx.git                 281cc2e178fd9a470d844b3afdea9eb322a0b0e8
+hw/mcu/nuvoton                            https://github.com/majbthrd/nuc_driver.git                      2204191ec76283371419fbcec207da02e1bc22fa
+hw/mcu/nxp/lpcopen                        https://github.com/hathach/nxp_lpcopen.git                      43c45c85405a5dd114fff0ea95cca62837740c13
+hw/mcu/nxp/mcux-sdk                       https://github.com/NXPmicro/mcux-sdk.git                        ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294
+hw/mcu/nxp/nxp_sdk                        https://github.com/hathach/nxp_sdk.git                          845c8fc49b6fb660f06a5c45225494eacb06f00c
+hw/mcu/raspberry_pi/Pico-PIO-USB          https://github.com/sekigon-gonnoc/Pico-PIO-USB.git              c3715ce94b6f6391856de56081d4d9b3e98fa93d
+hw/mcu/renesas/fsp                        https://github.com/renesas/fsp.git                              8dc14709f2a6518b43f71efad70d900b7718d9f1
+hw/mcu/renesas/rx                         https://github.com/kkitayam/rx_device.git                       706b4e0cf485605c32351e2f90f5698267996023
+hw/mcu/silabs/cmsis-dfp-efm32gg12b        https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git         f1c31b7887669cb230b3ea63f9b56769078960bc
+hw/mcu/sony/cxd56/spresense-exported-sdk  https://github.com/sonydevworld/spresense-exported-sdk.git      2ec2a1538362696118dc3fdf56f33dacaf8f4067
+hw/mcu/st/cmsis_device_f0                 https://github.com/STMicroelectronics/cmsis_device_f0.git       2fc25ee22264bc27034358be0bd400b893ef837e
+hw/mcu/st/cmsis_device_f1                 https://github.com/STMicroelectronics/cmsis_device_f1.git       6601104a6397299b7304fd5bcd9a491f56cb23a6
+hw/mcu/st/cmsis_device_f2                 https://github.com/STMicroelectronics/cmsis_device_f2.git       182fcb3681ce116816feb41b7764f1b019ce796f
+hw/mcu/st/cmsis_device_f3                 https://github.com/STMicroelectronics/cmsis_device_f3.git       5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b
+hw/mcu/st/cmsis_device_f4                 https://github.com/STMicroelectronics/cmsis_device_f4.git       2615e866fa48fe1ff1af9e31c348813f2b19e7ec
+hw/mcu/st/cmsis_device_f7                 https://github.com/STMicroelectronics/cmsis_device_f7.git       fc676ef1ad177eb874eaa06444d3d75395fc51f4
+hw/mcu/st/cmsis_device_g0                 https://github.com/STMicroelectronics/cmsis_device_g0.git       08258b28ee95f50cb9624d152a1cbf084be1f9a5
+hw/mcu/st/cmsis_device_g4                 https://github.com/STMicroelectronics/cmsis_device_g4.git       ce822adb1dc552b3aedd13621edbc7fdae124878
+hw/mcu/st/cmsis_device_h7                 https://github.com/STMicroelectronics/cmsis_device_h7.git       60dc2c913203dc8629dc233d4384dcc41c91e77f
+hw/mcu/st/cmsis_device_l0                 https://github.com/STMicroelectronics/cmsis_device_l0.git       06748ca1f93827befdb8b794402320d94d02004f
+hw/mcu/st/cmsis_device_l1                 https://github.com/STMicroelectronics/cmsis_device_l1.git       7f16ec0a1c4c063f84160b4cc6bf88ad554a823e
+hw/mcu/st/cmsis_device_l4                 https://github.com/STMicroelectronics/cmsis_device_l4.git       6ca7312fa6a5a460b5a5a63d66da527fdd8359a6
+hw/mcu/st/cmsis_device_l5                 https://github.com/STMicroelectronics/cmsis_device_l5.git       d922865fc0326a102c26211c44b8e42f52c1e53d
+hw/mcu/st/cmsis_device_u5                 https://github.com/STMicroelectronics/cmsis_device_u5.git       bc00f3c9d8a4e25220f84c26d414902cc6bdf566
+hw/mcu/st/cmsis_device_wb                 https://github.com/STMicroelectronics/cmsis_device_wb.git       9c5d1920dd9fabbe2548e10561d63db829bb744f
+hw/mcu/st/stm32f0xx_hal_driver            https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git  0e95cd88657030f640a11e690a8a5186c7712ea5
+hw/mcu/st/stm32f1xx_hal_driver            https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git  1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29
+hw/mcu/st/stm32f2xx_hal_driver            https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git  c75ace9b908a9aca631193ebf2466963b8ea33d0
+hw/mcu/st/stm32f3xx_hal_driver            https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git  1761b6207318ede021706e75aae78f452d72b6fa
+hw/mcu/st/stm32f4xx_hal_driver            https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git  04e99fbdabd00ab8f370f377c66b0a4570365b58
+hw/mcu/st/stm32f7xx_hal_driver            https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git  f7ffdf6bf72110e58b42c632b0a051df5997e4ee
+hw/mcu/st/stm32g0xx_hal_driver            https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git  5b53e6cee664a82b16c86491aa0060e2110c00cb
+hw/mcu/st/stm32g4xx_hal_driver            https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git  8b4518417706d42eef5c14e56a650005abf478a8
+hw/mcu/st/stm32h7xx_hal_driver            https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git  d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04
+hw/mcu/st/stm32l0xx_hal_driver            https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git  fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b
+hw/mcu/st/stm32l1xx_hal_driver            https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git  44efc446fa69ed8344e7fd966e68ed11043b35d9
+hw/mcu/st/stm32l4xx_hal_driver            https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git  aee3d5bf283ae5df87532b781bdd01b7caf256fc
+hw/mcu/st/stm32l5xx_hal_driver            https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git  675c32a75df37f39d50d61f51cb0dcf53f07e1cb
+hw/mcu/st/stm32u5xx_hal_driver            https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git  2e1d4cdb386e33391cb261dfff4fefa92e4aa35a
+hw/mcu/st/stm32wbxx_hal_driver            https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git  2c5f06638be516c1b772f768456ba637f077bac8
+hw/mcu/ti                                 https://github.com/hathach/ti_driver.git                        143ed6cc20a7615d042b03b21e070197d473e6e5
+hw/mcu/wch/ch32v307                       https://github.com/openwch/ch32v307.git                         17761f5cf9dbbf2dcf665b7c04934188add20082
+lib/CMSIS_5                               https://github.com/ARM-software/CMSIS_5.git                     20285262657d1b482d132d20d755c8c330d55c1f
+lib/FreeRTOS-Kernel                       https://github.com/FreeRTOS/FreeRTOS-Kernel.git                 def7d2df2b0506d3d249334974f51e427c17a41c
+lib/lwip                                  https://github.com/lwip-tcpip/lwip.git                          159e31b689577dbf69cf0683bbaffbd71fa5ee10
+lib/sct_neopixel                          https://github.com/gsteiert/sct_neopixel.git                    e73e04ca63495672d955f9268e003cffe168fcd8
+tools/uf2                                 https://github.com/microsoft/uf2.git                            19615407727073e36d81bf239c52108ba92e7660
+========================================  ==============================================================  ========================================
diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst
index ef4a6ba61..1f41cb888 100644
--- a/docs/reference/getting_started.rst
+++ b/docs/reference/getting_started.rst
@@ -44,12 +44,6 @@ For your convenience, TinyUSB contains a handful of examples for both host and d
    $ git clone https://github.com/hathach/tinyusb tinyusb
    $ cd tinyusb
 
-Some TinyUSB examples also requires external submodule libraries in ``/lib`` such as FreeRTOS, Lightweight IP to build. Run following command to fetch them
-
-.. code-block::
-
-   $ git submodule update --init lib
-
 Some ports will also require a port-specific SDK (e.g. RP2040) or binary (e.g. Sony Spresense) to build examples. They are out of scope for tinyusb, you should download/install it first according to its manufacturer guide.
 
 Build
@@ -61,23 +55,25 @@ To build example, first change directory to an example folder.
 
    $ cd examples/device/cdc_msc
 
-Before building, we need to download MCU driver submodule to provide low-level MCU peripheral's driver first. Run the ``get-deps`` target in one of the example folder as follow. You only need to do this once per mcu
+Before building, we firstly need to download dependencies such as: MCU low-level peripheral driver and external libraries e.g FreeRTOS (required by some examples). Run the ``get-deps`` target in one of the example folder as follow. You only need to do this once per mcu. Check out `complete list of dependencies and their designated path here <dependencies.rst>`_
 
 .. code-block::
 
-   $ make BOARD=feather_nrf52840_express get-deps
-
-
-Some modules (e.g. RP2040 and ESP32s2) require the project makefiles to be customized using CMake. If necessary apply any setup steps for the platform's SDK.
+   $ make BOARD=raspberry_pi_pico get-deps
 
 Then compile with ``make BOARD=[board_name] all``\ , for example
 
 .. code-block::
 
-   $ make BOARD=feather_nrf52840_express all
+   $ make BOARD=raspberry_pi_pico all
 
 Note: ``BOARD`` can be found as directory name in ``hw/bsp``\ , either in its family/boards or directly under bsp (no family).
-Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``/examples/device/99-tinyusb.rules`` file to /etc/udev/rules.d/ then run ``sudo udevadm control --reload-rules && sudo udevadm trigger`` is good enough.
+Note: some examples especially those that uses Vendor class (e.g webUSB) may requires udev permission on Linux (and/or macOS) to access usb device. It depends on your OS distro, typically copy ``99-tinyusb.rules`` and reload your udev is good to go
+
+.. code-block::
+
+   $ cp examples/device/99-tinyusb.rules /etc/udev/rules.d/
+   $ sudo udevadm control --reload-rules && sudo udevadm trigger
 
 Port Selection
 ~~~~~~~~~~~~~~
diff --git a/docs/reference/index.rst b/docs/reference/index.rst
index 292fb1a93..a9663ee7d 100644
--- a/docs/reference/index.rst
+++ b/docs/reference/index.rst
@@ -56,4 +56,5 @@ Index
 
    supported
    getting_started
+   dependencies
    concurrency
diff --git a/tools/gen_doc.py b/tools/gen_doc.py
new file mode 100644
index 000000000..db11e2cfb
--- /dev/null
+++ b/tools/gen_doc.py
@@ -0,0 +1,33 @@
+import pandas as pd
+from tabulate import tabulate
+from pathlib import Path
+from get_deps import deps_all
+
+# TOP is tinyusb root dir
+TOP = Path(__file__).parent.parent.resolve()
+
+###########################################
+# Dependencies
+###########################################
+def gen_deps_doc():
+    deps_rst = Path(TOP) / "docs/reference/dependencies.rst"
+    df = pd.DataFrame.from_dict(deps_all, orient='index', columns=['Commit', 'Project'])
+    df = df[['Project', 'Commit']].sort_index()
+    df = df.rename_axis("Path")
+
+    outstr = f"""\
+************
+Dependencies
+************
+
+MCU low-level peripheral driver and external libraries for building TinyUSB examples
+
+{tabulate(df, headers="keys", tablefmt='rst')}
+"""
+
+    with deps_rst.open('w') as f:
+        f.write(outstr)
+
+
+if __name__ == "__main__":
+    gen_deps_doc()

From 71fb6469d4997347f2014daa41839391cc070a74 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Mar 2023 14:02:09 +0700
Subject: [PATCH 1609/2085] separate CFG_TUSB_MEM_SECTION and
 CFG_TUSB_MEM_ALIGN to

- CFG_TUD_MEM_SECTION and CFG_TUD_MEM_ALIGN
- CFG_TUH_MEM_SECTION and CFG_TUH_MEM_ALIGN
- fix missing mem section and align for host
---
 hw/bsp/ea4088qs/board.mk         |  3 ++-
 src/class/cdc/cdc_host.c         |  6 ++---
 src/class/cdc/cdc_rndis_host.c   |  4 ++--
 src/class/hid/hid_host.c         |  6 ++---
 src/class/msc/msc_host.c         |  8 +++----
 src/host/hub.c                   |  8 +++----
 src/host/usbh.c                  |  8 +++----
 src/portable/ehci/ehci.c         |  2 +-
 src/portable/nxp/khci/hcd_khci.c |  4 ++--
 src/portable/ohci/ohci.c         |  2 +-
 src/tusb_option.h                | 40 +++++++++++++++++++++++++++++++-
 tools/build_utils.py             |  2 +-
 tools/gen_doc.py                 |  2 ++
 13 files changed, 68 insertions(+), 27 deletions(-)

diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/ea4088qs/board.mk
index 376840fb1..e1e14b717 100644
--- a/hw/bsp/ea4088qs/board.mk
+++ b/hw/bsp/ea4088qs/board.mk
@@ -10,7 +10,8 @@ CFLAGS += \
   -nostdlib \
   -DCORE_M4 \
   -D__USE_LPCOPEN \
-  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
+  -DCFG_TUD_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
+  -DCFG_TUH_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
   -DCFG_TUSB_MCU=OPT_MCU_LPC40XX
 
 # mcu driver cause following warnings
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index fee314823..734ddd1b8 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -62,10 +62,10 @@ typedef struct {
     tu_edpt_stream_t rx;
 
     uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
-    CFG_TUSB_MEM_ALIGN uint8_t tx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
+    CFG_TUH_MEM_ALIGN uint8_t tx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
 
     uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
-    CFG_TUSB_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
+    CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
   } stream;
 
 } cdch_interface_t;
@@ -74,7 +74,7 @@ typedef struct {
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-CFG_TUSB_MEM_SECTION
+CFG_TUH_MEM_SECTION
 static cdch_interface_t cdch_data[CFG_TUH_CDC];
 
 static inline cdch_interface_t* get_itf(uint8_t idx)
diff --git a/src/class/cdc/cdc_rndis_host.c b/src/class/cdc/cdc_rndis_host.c
index 41d21bbad..11a5355aa 100644
--- a/src/class/cdc/cdc_rndis_host.c
+++ b/src/class/cdc/cdc_rndis_host.c
@@ -50,8 +50,8 @@
 //--------------------------------------------------------------------+
 #define RNDIS_MSG_PAYLOAD_MAX   (1024*4)
 
-CFG_TUSB_MEM_SECTION static uint8_t msg_notification[CFG_TUH_DEVICE_MAX][8];
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t msg_payload[RNDIS_MSG_PAYLOAD_MAX];
+CFG_TUH_MEM_SECTION static uint8_t msg_notification[CFG_TUH_DEVICE_MAX][8];
+CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static uint8_t msg_payload[RNDIS_MSG_PAYLOAD_MAX];
 
 static rndish_data_t rndish_data[CFG_TUH_DEVICE_MAX];
 
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 20373f541..a0032aeba 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -54,11 +54,11 @@ typedef struct
   uint16_t epin_size;
   uint16_t epout_size;
 
-  uint8_t epin_buf[CFG_TUH_HID_EPIN_BUFSIZE];
-  uint8_t epout_buf[CFG_TUH_HID_EPOUT_BUFSIZE];
+  CFG_TUH_MEM_ALIGN uint8_t epin_buf[CFG_TUH_HID_EPIN_BUFSIZE];
+  CFG_TUH_MEM_ALIGN uint8_t epout_buf[CFG_TUH_HID_EPOUT_BUFSIZE];
 } hidh_interface_t;
 
-CFG_TUSB_MEM_SECTION
+CFG_TUH_MEM_SECTION
 tu_static hidh_interface_t _hidh_itf[CFG_TUH_HID];
 
 //--------------------------------------------------------------------+
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 2fddeb818..1b48813ec 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -71,15 +71,15 @@ typedef struct
   tuh_msc_complete_cb_t complete_cb;
   uintptr_t complete_arg;
 
-  msc_cbw_t cbw;
-  msc_csw_t csw;
+  CFG_TUH_MEM_ALIGN msc_cbw_t cbw;
+  CFG_TUH_MEM_ALIGN msc_csw_t csw;
 }msch_interface_t;
 
-CFG_TUSB_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
+CFG_TUH_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
 
 // buffer used to read scsi information when mounted
 // largest response data currently is inquiry TODO Inquiry is not part of enum anymore
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4)
+CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN
 static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)];
 
 TU_ATTR_ALWAYS_INLINE
diff --git a/src/host/hub.c b/src/host/hub.c
index b84042fb6..386ad6aae 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -43,12 +43,12 @@ typedef struct
   uint8_t port_count;
   uint8_t status_change; // data from status change interrupt endpoint
 
-  hub_port_status_response_t port_status;
-  hub_status_response_t hub_status;
+  CFG_TUH_MEM_ALIGN hub_port_status_response_t port_status;
+  CFG_TUH_MEM_ALIGN hub_status_response_t hub_status;
 } hub_interface_t;
 
-CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB];
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
+CFG_TUH_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB];
+CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
 
 TU_ATTR_ALWAYS_INLINE
 static inline hub_interface_t* get_itf(uint8_t dev_addr)
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 3eff0830a..3be662c63 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -203,7 +203,7 @@ static usbh_dev0_t _dev0;
 // all devices excluding zero-address
 // hub address start from CFG_TUH_DEVICE_MAX+1
 // TODO: hub can has its own simpler struct to save memory
-CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[TOTAL_DEVICES];
+static usbh_device_t _usbh_devices[TOTAL_DEVICES];
 
 // Mutex for claiming endpoint
 #if OSAL_MUTEX_REQUIRED
@@ -218,15 +218,15 @@ CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[TOTAL_DEVICES];
 OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
+CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN
 static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
 
 // Control transfers: since most controllers do not support multiple control transfers
 // on multiple devices concurrently and control transfers are not used much except for
 // enumeration, we will only execute control transfers one at a time.
-CFG_TUSB_MEM_SECTION struct
+CFG_TUH_MEM_SECTION struct
 {
-  tusb_control_request_t request TU_ATTR_ALIGNED(4);
+  CFG_TUH_MEM_ALIGN tusb_control_request_t request;
   uint8_t* buffer;
   tuh_xfer_cb_t complete_cb;
   uintptr_t user_data;
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index ee9dfb11f..9951aa5da 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -85,7 +85,7 @@ typedef struct
 }ehci_data_t;
 
 // Periodic frame list must be 4K alignment
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
+CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
 
 //--------------------------------------------------------------------+
 // PROTOTYPE
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 6d25cd862..f6029ee0d 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -137,8 +137,8 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd;
-//CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _rx_buf[1024];
+CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd;
+//CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _rx_buf[1024];
 
 int find_pipe(uint8_t dev_addr, uint8_t ep_addr)
 {
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 260804d3d..3f702d22c 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -145,7 +145,7 @@ enum {
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static ohci_data_t ohci_data;
+CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(256) static ohci_data_t ohci_data;
 
 static ohci_ed_t * const p_ed_head[] =
 {
diff --git a/src/tusb_option.h b/src/tusb_option.h
index c679f2f12..f8ac722f4 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -289,12 +289,15 @@
   #define CFG_TUSB_DEBUG 0
 #endif
 
-// place data in accessible RAM for usb controller
+// TODO MEM_SECTION can be different for host and device controller
+// should use CFG_TUD_MEM_SECTION, CFG_TUH_MEM_SECTION
 #ifndef CFG_TUSB_MEM_SECTION
   #define CFG_TUSB_MEM_SECTION
 #endif
 
 // alignment requirement of buffer used for endpoint transferring
+// TODO MEM_ALIGN can be different for host and device controller
+// should use CFG_TUD_MEM_ALIGN, CFG_TUH_MEM_ALIGN
 #ifndef CFG_TUSB_MEM_ALIGN
   #define CFG_TUSB_MEM_ALIGN      TU_ATTR_ALIGNED(4)
 #endif
@@ -312,6 +315,26 @@
 // Device Options (Default)
 //--------------------------------------------------------------------
 
+// Attribute to place data in accessible RAM for device controller
+// default to CFG_TUSB_MEM_SECTION for backward-compatible
+#ifndef CFG_TUD_MEM_SECTION
+  #ifdef CFG_TUSB_MEM_SECTION
+    #define CFG_TUD_MEM_SECTION   CFG_TUSB_MEM_SECTION
+  #else
+    #define CFG_TUD_MEM_SECTION
+  #endif
+#endif
+
+// Attribute to align memory for device controller
+// default to CFG_TUSB_MEM_ALIGN for backward-compatible
+#ifndef CFG_TUD_MEM_ALIGN
+  #ifdef CFG_TUSB_MEM_ALIGN
+    #define CFG_TUD_MEM_ALIGN   CFG_TUSB_MEM_ALIGN
+  #else
+    #define CFG_TUD_MEM_ALIGN   TU_ATTR_ALIGNED(4)
+  #endif
+#endif
+
 #ifndef CFG_TUD_ENDPOINT0_SIZE
   #define CFG_TUD_ENDPOINT0_SIZE  64
 #endif
@@ -390,6 +413,21 @@
   #endif
 #endif // CFG_TUH_ENABLED
 
+// Attribute to place data in accessible RAM for host controller
+// default to CFG_TUSB_MEM_SECTION for backward-compatible
+#ifndef CFG_TUH_MEM_SECTION
+  #ifdef CFG_TUSB_MEM_SECTION
+    #define CFG_TUH_MEM_SECTION   CFG_TUSB_MEM_SECTION
+  #else
+    #define CFG_TUH_MEM_SECTION
+  #endif
+#endif
+
+// Attribute to align memory for host controller
+#ifndef CFG_TUH_MEM_ALIGN
+  #define CFG_TUH_MEM_ALIGN   TU_ATTR_ALIGNED(4)
+#endif
+
 //------------- CLASS -------------//
 
 #ifndef CFG_TUH_HUB
diff --git a/tools/build_utils.py b/tools/build_utils.py
index d0ef52717..905d06a86 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -93,7 +93,7 @@ def build_example(example, board, make_option):
         ret[2] = 1
         print(build_format.format(example, board, status, '-', flash_size, sram_size))
     else:
-        subprocess.run(make_cmd + " clean", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        #subprocess.run(make_cmd + " clean", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
         build_result = subprocess.run(make_cmd + " all", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
 
         if build_result.returncode == 0:
diff --git a/tools/gen_doc.py b/tools/gen_doc.py
index db11e2cfb..9078299cc 100644
--- a/tools/gen_doc.py
+++ b/tools/gen_doc.py
@@ -6,9 +6,11 @@ from get_deps import deps_all
 # TOP is tinyusb root dir
 TOP = Path(__file__).parent.parent.resolve()
 
+
 ###########################################
 # Dependencies
 ###########################################
+
 def gen_deps_doc():
     deps_rst = Path(TOP) / "docs/reference/dependencies.rst"
     df = pd.DataFrame.from_dict(deps_all, orient='index', columns=['Commit', 'Project'])

From 76dae8d8c1764e94c99effe5d3f4f9b0ec0d4c99 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Mar 2023 14:08:57 +0700
Subject: [PATCH 1610/2085] update host example to use new tuh mem macros

---
 .../host_hid_to_device_cdc/src/tusb_config.h     | 16 ++++++++++++----
 examples/host/bare_api/src/tusb_config.h         |  8 ++++----
 examples/host/cdc_msc_hid/src/tusb_config.h      |  8 ++++----
 examples/host/hid_controller/src/tusb_config.h   |  8 ++++----
 .../host/msc_file_explorer/src/tusb_config.h     |  8 ++++----
 5 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
index 604cc6681..2185cd1f1 100644
--- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
+++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
@@ -95,12 +95,12 @@
  * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUD_MEM_SECTION
+#define CFG_TUD_MEM_SECTION
 #endif
 
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
+#ifndef CFG_TUD_MEM_ALIGN
+#define CFG_TUD_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
@@ -128,6 +128,14 @@
 // Size of buffer to hold descriptors and other data used for enumeration
 #define CFG_TUH_ENUMERATION_BUFSIZE 256
 
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
+#endif
+
 #define CFG_TUH_HUB                 1
 // max device support (excluding hub device)
 #define CFG_TUH_DEVICE_MAX          (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports
diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h
index 64be41a4e..ede9618d3 100644
--- a/examples/host/bare_api/src/tusb_config.h
+++ b/examples/host/bare_api/src/tusb_config.h
@@ -80,12 +80,12 @@
  * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
 #endif
 
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 6c5e68a87..1152e4910 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -80,12 +80,12 @@
  * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
 #endif
 
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h
index f5ae2fd6f..d37fc02d2 100644
--- a/examples/host/hid_controller/src/tusb_config.h
+++ b/examples/host/hid_controller/src/tusb_config.h
@@ -80,12 +80,12 @@
  * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
 #endif
 
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index eaf3ea6d4..1e0d067bf 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -80,12 +80,12 @@
  * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
  * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
  */
-#ifndef CFG_TUSB_MEM_SECTION
-#define CFG_TUSB_MEM_SECTION
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
 #endif
 
-#ifndef CFG_TUSB_MEM_ALIGN
-#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
 #endif
 
 //--------------------------------------------------------------------

From b05422978004f076de665f5101e5cc1bac34175c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Mar 2023 17:26:30 +0700
Subject: [PATCH 1611/2085] fix cdc host enumeration issue when device does not
 support line request

---
 src/class/cdc/cdc_host.c | 39 +++++++++++++++++++++++----------------
 1 file changed, 23 insertions(+), 16 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 734ddd1b8..08b82416d 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -323,7 +323,8 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
     .user_data   = user_data
   };
 
-  return tuh_control_xfer(&xfer);
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
 }
 
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
@@ -363,7 +364,8 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
     .user_data   = user_data
   };
 
-  return tuh_control_xfer(&xfer);
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
 }
 
 //--------------------------------------------------------------------+
@@ -543,26 +545,31 @@ static void process_cdc_config(tuh_xfer_t* xfer)
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  TU_ASSERT(idx != TUSB_INDEX_INVALID_8, );
+  cdch_interface_t * p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc, );
 
   switch(state)
   {
     case CONFIG_SET_CONTROL_LINE_STATE:
-    #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), );
-      break;
-    #endif
-    TU_ATTR_FALLTHROUGH;
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+      if (p_cdc->acm_capability.support_line_request)
+      {
+        TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), );
+        break;
+      }
+      #endif
+      TU_ATTR_FALLTHROUGH;
 
     case CONFIG_SET_LINE_CODING:
-    #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-    {
-      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-      TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), );
-      break;
-    }
-    #endif
-    TU_ATTR_FALLTHROUGH;
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      if (p_cdc->acm_capability.support_line_request)
+      {
+        cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+        TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), );
+        break;
+      }
+      #endif
+      TU_ATTR_FALLTHROUGH;
 
     case CONFIG_COMPLETE:
       if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);

From df5f60b6d67400891c5887afe29fcac5644cc668 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 24 Mar 2023 17:36:29 +0700
Subject: [PATCH 1612/2085] fix shadow warning

---
 src/class/cdc/cdc_host.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 08b82416d..c0cc41adf 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -575,7 +575,6 @@ static void process_cdc_config(tuh_xfer_t* xfer)
       if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
 
       // Prepare for incoming data
-      cdch_interface_t* p_cdc = get_itf(idx);
       tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
 
       // notify usbh that driver enumeration is complete

From 97f9321e1d94ddb4904dba0a472790a1189e53f2 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Fri, 3 Mar 2023 22:06:57 +0900
Subject: [PATCH 1613/2085] Add handling for bulk EPs

---
 src/class/video/video_device.c | 39 +++++++++++++++++++++-------------
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index d6e98602b..e03ca6b1f 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -680,24 +680,30 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
       (video_probe_and_commit_control_t *)&stm->ep_buf;
     tu_memclr(param, sizeof(*param));
     TU_LOG2("    done 0\n");
-    return _update_streaming_parameters(stm, param);
+    if (!_update_streaming_parameters(stm, param))
+      return false;
+    /* Open bulk endpoint if present. */
+    for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) {
+      cur = _find_desc_ep(cur, end);
+      TU_ASSERT(cur < end);
+      tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur;
+      TU_VERIFY(TUSB_XFER_BULK == ep->bmAttributes.xfer);
+      TU_ASSERT(usbd_edpt_open(rhport, ep));
+      stm->desc.ep[i] = (uint16_t)(cur - desc);
+      TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
+    }
+    return true;
   }
-  /* Open endpoints of the new settings. */
+  /* Open isochronous endpoints of the new settings. */
   for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) {
     cur = _find_desc_ep(cur, end);
     TU_ASSERT(cur < end);
     tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur;
-    if (!stm->max_payload_transfer_size) {
-      video_probe_and_commit_control_t const *param = (video_probe_and_commit_control_t const*)&stm->ep_buf;
-      uint_fast32_t max_size = param->dwMaxPayloadTransferSize;
-      if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) &&
-          (tu_edpt_packet_size(ep) < max_size))
-      {
-        /* FS must be less than or equal to max packet size */
-        return false;
-      }
-      /* Set the negotiated value */
-      stm->max_payload_transfer_size = max_size;
+    uint_fast32_t max_size = stm->max_payload_transfer_size;
+    if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) &&
+        (tu_edpt_packet_size(ep) < max_size)) {
+      /* FS must be less than or equal to max packet size */
+      return false;
     }
     TU_ASSERT(usbd_edpt_open(rhport, ep));
     stm->desc.ep[i] = (uint16_t) (cur - desc);
@@ -982,9 +988,12 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
             TU_VERIFY(sizeof(video_probe_and_commit_control_t) >= request->wLength, VIDEO_ERROR_UNKNOWN);
             TU_VERIFY(tud_control_xfer(rhport, request, self->ep_buf, sizeof(video_probe_and_commit_control_t)), VIDEO_ERROR_UNKNOWN);
           } else if (stage == CONTROL_STAGE_DATA) {
-            TU_VERIFY(_update_streaming_parameters(self, (video_probe_and_commit_control_t*)self->ep_buf), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            video_probe_and_commit_control_t *param = (video_probe_and_commit_control_t*)self->ep_buf;
+            TU_VERIFY(_update_streaming_parameters(self, param), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
+            /* Set the negotiated value */
+            self->max_payload_transfer_size = param->dwMaxPayloadTransferSize;
             if (tud_video_commit_cb) {
-              return tud_video_commit_cb(self->index_vc, self->index_vs, (video_probe_and_commit_control_t*)self->ep_buf);
+              return tud_video_commit_cb(self->index_vc, self->index_vs, param);
             }
           }
           return VIDEO_ERROR_NONE;

From 78732d6733fa75e6f8b25dc9e694d4d38e7b72ce Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Fri, 10 Mar 2023 22:51:49 +0900
Subject: [PATCH 1614/2085] Fix streaming interface handling

---
 src/class/video/video_device.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index e03ca6b1f..d53de2bac 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -709,11 +709,6 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     stm->desc.ep[i] = (uint16_t) (cur - desc);
     TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
   }
-  /* initialize payload header */
-  tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)stm->ep_buf;
-  hdr->bHeaderLength = sizeof(*hdr);
-  hdr->bmHeaderInfo  = 0;
-
   TU_LOG2("    done\n");
   return true;
 }
@@ -992,8 +987,15 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
             TU_VERIFY(_update_streaming_parameters(self, param), VIDEO_ERROR_INVALID_VALUE_WITHIN_RANGE);
             /* Set the negotiated value */
             self->max_payload_transfer_size = param->dwMaxPayloadTransferSize;
+            int ret = VIDEO_ERROR_NONE;
             if (tud_video_commit_cb) {
-              return tud_video_commit_cb(self->index_vc, self->index_vs, param);
+              ret = tud_video_commit_cb(self->index_vc, self->index_vs, param);
+            }
+            if (VIDEO_ERROR_NONE == ret) {
+              /* initialize payload header */
+              tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)self->ep_buf;
+              hdr->bHeaderLength = sizeof(*hdr);
+              hdr->bmHeaderInfo  = 0;
             }
           }
           return VIDEO_ERROR_NONE;
@@ -1166,6 +1168,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
   uint_fast8_t bInCollection   = vc->ctl.bInCollection;
 
+  videod_streaming_interface_t *default_stm = NULL;
   /* Find the end of the video interface descriptor */
   void const *cur = _next_desc_itf(itf_desc, end);
   for (uint8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) {
@@ -1183,7 +1186,9 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
     stm->desc.beg = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
     cur = _next_desc_itf(cur, end);
     stm->desc.end = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
+    if (!default_stm) default_stm = stm;
   }
+  TU_VERIFY(_open_vs_itf(rhport, default_stm, 0), 0);
   self->len = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
   return (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
 }

From e508831561da46cfd03e59876e4218aadd57855c Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 13 Mar 2023 22:50:31 +0900
Subject: [PATCH 1615/2085] Update handle streaming interface

---
 src/class/video/video_device.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index d53de2bac..8dd39242f 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -1168,7 +1168,6 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   tusb_desc_vc_itf_t const *vc = _get_desc_vc(self);
   uint_fast8_t bInCollection   = vc->ctl.bInCollection;
 
-  videod_streaming_interface_t *default_stm = NULL;
   /* Find the end of the video interface descriptor */
   void const *cur = _next_desc_itf(itf_desc, end);
   for (uint8_t stm_idx = 0; stm_idx < bInCollection; ++stm_idx) {
@@ -1186,9 +1185,16 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
     stm->desc.beg = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
     cur = _next_desc_itf(cur, end);
     stm->desc.end = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
-    if (!default_stm) default_stm = stm;
+    if (0 == stm_idx && 1 == bInCollection) {
+      /* If there is only one streaming interface and no alternate settings,
+       * host may not issue set_interface so open the streaming interface here. */
+      uint8_t const *sbeg = (uint8_t const*)itf_desc + stm->desc.beg;
+      uint8_t const *send = (uint8_t const*)itf_desc + stm->desc.end;
+      if (end == _find_desc_itf(sbeg, send, _desc_itfnum(sbeg), 1)) {
+        TU_VERIFY(_open_vs_itf(rhport, stm, 0), 0);
+      }
+    }
   }
-  TU_VERIFY(_open_vs_itf(rhport, default_stm, 0), 0);
   self->len = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
   return (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
 }
@@ -1201,7 +1207,6 @@ bool videod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_
   int err;
   TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
   uint_fast8_t itfnum = tu_u16_low(request->wIndex);
-
   /* Identify which control interface to use */
   uint_fast8_t itf;
   for (itf = 0; itf < CFG_TUD_VIDEO; ++itf) {

From 389babf20bcf77159a268bbdebd534bc7e1d1bb9 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Mon, 13 Mar 2023 22:51:21 +0900
Subject: [PATCH 1616/2085] Add descriptor for a bulk endpoint as a streaming
 endpoint

---
 .../device/video_capture/src/tusb_config.h    |  3 ++
 .../video_capture/src/usb_descriptors.c       | 10 ++++
 .../video_capture/src/usb_descriptors.h       | 51 +++++++++++++++++++
 3 files changed, 64 insertions(+)

diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h
index e567ba669..274bf2b9c 100644
--- a/examples/device/video_capture/src/tusb_config.h
+++ b/examples/device/video_capture/src/tusb_config.h
@@ -100,6 +100,9 @@
 // video streaming endpoint size
 #define CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE  256
 
+// use bulk endpoint for streaming interface
+#define CFG_TUD_VIDEO_STREAMING_BULK 0
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index af18d15d1..f85e3cd8a 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -77,6 +77,8 @@ uint8_t const * tud_descriptor_device_cb(void)
 
 #if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_LEN)
+#elif 1 == CFG_TUD_VIDEO_STREAMING_BULK
+#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_BULK_LEN)
 #else
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN)
 #endif
@@ -84,7 +86,11 @@ uint8_t const * tud_descriptor_device_cb(void)
 #if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
   // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
   // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In, 5 Bulk etc ...
+#if 1 == CFG_TUD_VIDEO_STREAMING_BULK
+  #define EPNUM_VIDEO_IN    0x82
+#else
   #define EPNUM_VIDEO_IN    0x83
+#endif
 
 #elif TU_CHECK_MCU(OPT_MCU_NRF5X)
   // nRF5x ISO can only be endpoint 8
@@ -105,6 +111,10 @@ uint8_t const desc_fs_configuration[] =
   TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(4, EPNUM_VIDEO_IN,
                                      FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
                                      CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
+#elif 1 == CFG_TUD_VIDEO_STREAMING_BULK
+  TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR_BULK(4, EPNUM_VIDEO_IN,
+                                       FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
+                                       64)
 #else
   TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(4, EPNUM_VIDEO_IN,
                                        FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 93f148a82..7b7857246 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -79,6 +79,22 @@ enum {
     + 7/* Endpoint */\
   )
 
+#define TUD_VIDEO_CAPTURE_DESC_UNCOMPR_BULK_LEN (\
+    TUD_VIDEO_DESC_IAD_LEN\
+    /* control */\
+    + TUD_VIDEO_DESC_STD_VC_LEN\
+    + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+    + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+    + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+    + TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+    + 7/* Endpoint */\
+  )
+
 /* Windows support YUY2 and NV12
  * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
 
@@ -165,4 +181,39 @@ enum {
     /* EP */ \
     TUD_VIDEO_DESC_EP_ISO(_epin, _epsize, 1)
 
+
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+  /* Video control 0 */ \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
+    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
+         /* wTotalLength - bLength */ \
+         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
+         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
+                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
+                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+  /* Video stream alt. 0 */ \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
+    /* Video stream header for without still image capture */ \
+    TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+        /*wTotalLength - bLength */\
+        TUD_VIDEO_DESC_CS_VS_FMT_UNCOMPR_LEN\
+        + TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT_LEN\
+        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+        /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+        /*bmaControls(1)*/0), \
+      /* Video stream format */ \
+      TUD_VIDEO_DESC_CS_VS_FMT_YUY2(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /* Video stream frame format */ \
+        TUD_VIDEO_DESC_CS_VS_FRM_UNCOMPR_CONT(/*bFrameIndex */1, 0, _width, _height, \
+            _width * _height * 16, _width * _height * 16 * _fps, \
+            _width * _height * 16, \
+            (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+        TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
+
 #endif

From 993b8d66861253408c1029bf98923ccba7317482 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sat, 25 Mar 2023 22:13:20 +0900
Subject: [PATCH 1617/2085] Add state variable

---
 src/class/video/video_device.c | 68 +++++++++++++++++++++-------------
 1 file changed, 42 insertions(+), 26 deletions(-)

diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 8dd39242f..91f452afc 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -37,6 +37,10 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
+#define VS_STATE_PROBING      0     /* Configuration in progress */
+#define VS_STATE_COMMITTED    1     /* Ready for streaming or Streaming via bulk endpoint */
+#define VS_STATE_STREAMING    2     /* Streaming via isochronous endpoint */
+
 typedef struct {
   tusb_desc_interface_t            std;
   tusb_desc_cs_video_ctl_itf_hdr_t ctl;
@@ -102,6 +106,7 @@ typedef struct TU_ATTR_PACKED {
   uint32_t offset;   /* offset for the next payload transfer */
   uint32_t max_payload_transfer_size;
   uint8_t  error_code;/* error code */
+  uint8_t  state;    /* 0:probing 1:committed 2:streaming */
   /*------------- From this point, data is not cleared by bus reset -------------*/
   CFG_TUSB_MEM_ALIGN uint8_t ep_buf[CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE]; /* EP transfer buffer for streaming */
 } videod_streaming_interface_t;
@@ -639,6 +644,17 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
   return true;
 }
 
+static bool _init_vs_configuration(videod_streaming_interface_t *stm)
+{
+  /* initialize streaming settings */
+  stm->state = VS_STATE_PROBING;
+  stm->max_payload_transfer_size = 0;
+  video_probe_and_commit_control_t *param =
+    (video_probe_and_commit_control_t *)&stm->ep_buf;
+  tu_memclr(param, sizeof(*param));
+  return _update_streaming_parameters(stm, param);
+}
+
 /** Set the alternate setting to own video streaming interface.
  *
  * @param[in,out] stm      Streaming interface context.
@@ -672,43 +688,32 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
 
   uint_fast8_t numeps = ((tusb_desc_interface_t const *)cur)->bNumEndpoints;
   TU_ASSERT(numeps <= TU_ARRAY_SIZE(stm->desc.ep));
-  stm->desc.cur = (uint16_t) (cur - desc); /* Save the offset of the new settings */
-  if (!altnum) {
-    /* initialize streaming settings */
-    stm->max_payload_transfer_size = 0;
-    video_probe_and_commit_control_t *param =
-      (video_probe_and_commit_control_t *)&stm->ep_buf;
-    tu_memclr(param, sizeof(*param));
-    TU_LOG2("    done 0\n");
-    if (!_update_streaming_parameters(stm, param))
-      return false;
-    /* Open bulk endpoint if present. */
-    for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) {
-      cur = _find_desc_ep(cur, end);
-      TU_ASSERT(cur < end);
-      tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur;
-      TU_VERIFY(TUSB_XFER_BULK == ep->bmAttributes.xfer);
-      TU_ASSERT(usbd_edpt_open(rhport, ep));
-      stm->desc.ep[i] = (uint16_t)(cur - desc);
-      TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
-    }
-    return true;
+  stm->desc.cur = (uint16_t)(cur - desc); /* Save the offset of the new settings */
+  if (!altnum && (VS_STATE_COMMITTED != stm->state)) {
+    TU_VERIFY(_init_vs_configuration(stm));
   }
-  /* Open isochronous endpoints of the new settings. */
+  /* Open bulk or isochronous endpoints of the new settings. */
   for (i = 0, cur = tu_desc_next(cur); i < numeps; ++i, cur = tu_desc_next(cur)) {
     cur = _find_desc_ep(cur, end);
     TU_ASSERT(cur < end);
     tusb_desc_endpoint_t const *ep = (tusb_desc_endpoint_t const*)cur;
     uint_fast32_t max_size = stm->max_payload_transfer_size;
-    if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) &&
-        (tu_edpt_packet_size(ep) < max_size)) {
-      /* FS must be less than or equal to max packet size */
-      return false;
+    if (altnum) {
+      if ((TUSB_XFER_ISOCHRONOUS == ep->bmAttributes.xfer) &&
+          (tu_edpt_packet_size(ep) < max_size)) {
+        /* FS must be less than or equal to max packet size */
+        return false;
+      }
+    } else {
+      TU_VERIFY(TUSB_XFER_BULK == ep->bmAttributes.xfer);
     }
     TU_ASSERT(usbd_edpt_open(rhport, ep));
     stm->desc.ep[i] = (uint16_t) (cur - desc);
     TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
   }
+  if (altnum) {
+    stm->state = VS_STATE_STREAMING;
+  }
   TU_LOG2("    done\n");
   return true;
 }
@@ -921,6 +926,10 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
       break;
 
     case VIDEO_VS_CTL_PROBE:
+      if (self->state != VS_STATE_PROBING) {
+        self->state = VS_STATE_PROBING;
+        _init_vs_configuration(self);
+      }
       switch (request->bRequest) {
         case VIDEO_REQUEST_SET_CUR:
           if (stage == CONTROL_STAGE_SETUP) {
@@ -992,6 +1001,10 @@ static int handle_video_stm_cs_req(uint8_t rhport, uint8_t stage,
               ret = tud_video_commit_cb(self->index_vc, self->index_vs, param);
             }
             if (VIDEO_ERROR_NONE == ret) {
+              self->state   = VS_STATE_COMMITTED;
+              self->buffer  = NULL;
+              self->bufsize = 0;
+              self->offset  = 0;
               /* initialize payload header */
               tusb_video_payload_header_t *hdr = (tusb_video_payload_header_t*)self->ep_buf;
               hdr->bHeaderLength = sizeof(*hdr);
@@ -1080,6 +1093,7 @@ bool tud_video_n_streaming(uint_fast8_t ctl_idx, uint_fast8_t stm_idx)
   TU_ASSERT(stm_idx < CFG_TUD_VIDEO_STREAMING);
   videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx);
   if (!stm || !stm->desc.ep[0]) return false;
+  if (stm->state == VS_STATE_PROBING) return false;
   return true;
 }
 
@@ -1090,6 +1104,7 @@ bool tud_video_n_frame_xfer(uint_fast8_t ctl_idx, uint_fast8_t stm_idx, void *bu
   if (!buffer || !bufsize) return false;
   videod_streaming_interface_t *stm = _get_instance_streaming(ctl_idx, stm_idx);
   if (!stm || !stm->desc.ep[0] || stm->buffer) return false;
+  if (stm->state == VS_STATE_PROBING) return false;
 
   /* Find EP address */
   uint8_t const *desc = _videod_itf[stm->index_vc].beg;
@@ -1185,6 +1200,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
     stm->desc.beg = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
     cur = _next_desc_itf(cur, end);
     stm->desc.end = (uint16_t) ((uintptr_t)cur - (uintptr_t)itf_desc);
+    stm->state = VS_STATE_PROBING;
     if (0 == stm_idx && 1 == bInCollection) {
       /* If there is only one streaming interface and no alternate settings,
        * host may not issue set_interface so open the streaming interface here. */

From 5ce60c5d207b9e7de419be6956164aebde14c3f2 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 26 Mar 2023 21:22:52 +0900
Subject: [PATCH 1618/2085] Add MJPEG descriptor for bulk transfer

---
 .../video_capture/src/usb_descriptors.c       | 30 ++++++++---
 .../video_capture/src/usb_descriptors.h       | 52 +++++++++++++++++++
 2 files changed, 74 insertions(+), 8 deletions(-)

diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index f85e3cd8a..9847cf7c5 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -76,11 +76,17 @@ uint8_t const * tud_descriptor_device_cb(void)
 //--------------------------------------------------------------------+
 
 #if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_LEN)
-#elif 1 == CFG_TUD_VIDEO_STREAMING_BULK
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_BULK_LEN)
+# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
+#  define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_BULK_LEN)
+# else
+#  define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_MJPEG_LEN)
+# endif
 #else
-#define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN)
+# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
+#  define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_BULK_LEN)
+# else
+#  define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_VIDEO_CAPTURE_DESC_UNCOMPR_LEN)
+# endif
 #endif
 
 #if TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
@@ -108,17 +114,25 @@ uint8_t const desc_fs_configuration[] =
 
   // IAD for Video Control
 #if defined(CFG_EXAMPLE_VIDEO_READONLY) && !defined(CFG_EXAMPLE_VIDEO_DISABLE_MJPEG)
+# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
+  TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(4, EPNUM_VIDEO_IN,
+                                          FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
+                                          64)
+# else
   TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG(4, EPNUM_VIDEO_IN,
                                      FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
                                      CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
-#elif 1 == CFG_TUD_VIDEO_STREAMING_BULK
-  TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR_BULK(4, EPNUM_VIDEO_IN,
-                                       FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
-                                       64)
+# endif
 #else
+# if 1 == CFG_TUD_VIDEO_STREAMING_BULK
+  TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR_BULK(4, EPNUM_VIDEO_IN,
+                                            FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
+                                            64)
+# else
   TUD_VIDEO_CAPTURE_DESCRIPTOR_UNCOMPR(4, EPNUM_VIDEO_IN,
                                        FRAME_WIDTH, FRAME_HEIGHT, FRAME_RATE,
                                        CFG_TUD_VIDEO_STREAMING_EP_BUFSIZE)
+# endif
 #endif
 };
 
diff --git a/examples/device/video_capture/src/usb_descriptors.h b/examples/device/video_capture/src/usb_descriptors.h
index 7b7857246..b924c8dbe 100644
--- a/examples/device/video_capture/src/usb_descriptors.h
+++ b/examples/device/video_capture/src/usb_descriptors.h
@@ -95,6 +95,22 @@ enum {
     + 7/* Endpoint */\
   )
 
+#define TUD_VIDEO_CAPTURE_DESC_MJPEG_BULK_LEN (\
+    TUD_VIDEO_DESC_IAD_LEN\
+    /* control */\
+    + TUD_VIDEO_DESC_STD_VC_LEN\
+    + (TUD_VIDEO_DESC_CS_VC_LEN + 1/*bInCollection*/)\
+    + TUD_VIDEO_DESC_CAMERA_TERM_LEN\
+    + TUD_VIDEO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_VIDEO_DESC_STD_VS_LEN\
+    + (TUD_VIDEO_DESC_CS_VS_IN_LEN + 1/*bNumFormats x bControlSize*/)\
+    + TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
+    + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
+    + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN\
+    + 7/* Endpoint */\
+  )
+
 /* Windows support YUY2 and NV12
  * https://docs.microsoft.com/en-us/windows-hardware/drivers/stream/usb-video-class-driver-overview */
 
@@ -216,4 +232,40 @@ enum {
         TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
         TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
 
+#define TUD_VIDEO_CAPTURE_DESCRIPTOR_MJPEG_BULK(_stridx, _epin, _width, _height, _fps, _epsize) \
+  TUD_VIDEO_DESC_IAD(ITF_NUM_VIDEO_CONTROL, /* 2 Interfaces */ 0x02, _stridx), \
+  /* Video control 0 */ \
+  TUD_VIDEO_DESC_STD_VC(ITF_NUM_VIDEO_CONTROL, 0, _stridx), \
+    TUD_VIDEO_DESC_CS_VC( /* UVC 1.5*/ 0x0150, \
+         /* wTotalLength - bLength */ \
+         TUD_VIDEO_DESC_CAMERA_TERM_LEN + TUD_VIDEO_DESC_OUTPUT_TERM_LEN, \
+         UVC_CLOCK_FREQUENCY, ITF_NUM_VIDEO_STREAMING), \
+      TUD_VIDEO_DESC_CAMERA_TERM(UVC_ENTITY_CAP_INPUT_TERMINAL, 0, 0,\
+                                 /*wObjectiveFocalLengthMin*/0, /*wObjectiveFocalLengthMax*/0,\
+                                 /*wObjectiveFocalLength*/0, /*bmControls*/0), \
+      TUD_VIDEO_DESC_OUTPUT_TERM(UVC_ENTITY_CAP_OUTPUT_TERMINAL, VIDEO_TT_STREAMING, 0, 1, 0), \
+  /* Video stream alt. 0 */ \
+  TUD_VIDEO_DESC_STD_VS(ITF_NUM_VIDEO_STREAMING, 0, 1, _stridx), \
+    /* Video stream header for without still image capture */ \
+    TUD_VIDEO_DESC_CS_VS_INPUT( /*bNumFormats*/1, \
+        /*wTotalLength - bLength */\
+        TUD_VIDEO_DESC_CS_VS_FMT_MJPEG_LEN\
+        + TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT_LEN\
+        + TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING_LEN,\
+        _epin, /*bmInfo*/0, /*bTerminalLink*/UVC_ENTITY_CAP_OUTPUT_TERMINAL, \
+        /*bStillCaptureMethod*/0, /*bTriggerSupport*/0, /*bTriggerUsage*/0, \
+        /*bmaControls(1)*/0), \
+      /* Video stream format */ \
+      TUD_VIDEO_DESC_CS_VS_FMT_MJPEG(/*bFormatIndex*/1, /*bNumFrameDescriptors*/1, \
+        /*bmFlags*/0, /*bDefaultFrameIndex*/1, 0, 0, 0, /*bCopyProtect*/0), \
+        /* Video stream frame format */ \
+        TUD_VIDEO_DESC_CS_VS_FRM_MJPEG_CONT(/*bFrameIndex */1, 0, _width, _height, \
+            _width * _height * 16, _width * _height * 16 * _fps, \
+            _width * _height * 16 / 8, \
+            (10000000/_fps), (10000000/_fps), (10000000/_fps)*_fps, (10000000/_fps)), \
+        TUD_VIDEO_DESC_CS_VS_COLOR_MATCHING(VIDEO_COLOR_PRIMARIES_BT709, VIDEO_COLOR_XFER_CH_BT709, VIDEO_COLOR_COEF_SMPTE170M), \
+        /* EP */ \
+        TUD_VIDEO_DESC_EP_BULK(_epin, _epsize, 1)
+
+
 #endif

From faaed198b48b3af7482503bacf3188040c245a1e Mon Sep 17 00:00:00 2001
From: epatstarkey <58745560+epatstarkey@users.noreply.github.com>
Date: Tue, 28 Mar 2023 13:59:59 -0500
Subject: [PATCH 1619/2085] Update vendor_device.h

---
 src/class/vendor/vendor_device.h | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index 9abafda50..ca4837d7b 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -1,4 +1,4 @@
-/*
+/* 
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
@@ -48,6 +48,7 @@ bool     tud_vendor_n_peek            (uint8_t itf, uint8_t* ui8);
 void     tud_vendor_n_read_flush      (uint8_t itf);
 
 uint32_t tud_vendor_n_write           (uint8_t itf, void const* buffer, uint32_t bufsize);
+uint32_t tud_vendor_n_write_flush     (uint8_t itf);
 uint32_t tud_vendor_n_write_available (uint8_t itf);
 
 static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str);
@@ -64,7 +65,7 @@ static inline void     tud_vendor_read_flush      (void);
 static inline uint32_t tud_vendor_write           (void const* buffer, uint32_t bufsize);
 static inline uint32_t tud_vendor_write_str       (char const* str);
 static inline uint32_t tud_vendor_write_available (void);
-static inline uint32_t tud_vendor_flush           (void);
+static inline uint32_t tud_vendor_write_flush     (void);
 
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
@@ -114,6 +115,11 @@ static inline uint32_t tud_vendor_write (void const* buffer, uint32_t bufsize)
   return tud_vendor_n_write(0, buffer, bufsize);
 }
 
+static inline uint32_t tud_vendor_write_flush (void)
+{
+  return tud_vendor_n_write_flush(0);
+}
+
 static inline uint32_t tud_vendor_write_str (char const* str)
 {
   return tud_vendor_n_write_str(0, str);
@@ -124,11 +130,6 @@ static inline uint32_t tud_vendor_write_available (void)
   return tud_vendor_n_write_available(0);
 }
 
-static inline uint32_t tud_vendor_flush (void)
-{
-  return tud_vendor_n_flush(0);
-}
-
 //--------------------------------------------------------------------+
 // Internal Class Driver API
 //--------------------------------------------------------------------+

From 876f49f6ad10ef2bca000602fe862889c3e0268f Mon Sep 17 00:00:00 2001
From: epatstarkey <58745560+epatstarkey@users.noreply.github.com>
Date: Tue, 28 Mar 2023 14:00:23 -0500
Subject: [PATCH 1620/2085] Update vendor_device.c

---
 src/class/vendor/vendor_device.c | 65 ++++++++++++++++++++------------
 1 file changed, 40 insertions(+), 25 deletions(-)

diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index d07bd75ec..260da0125 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -59,7 +59,7 @@ typedef struct
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE];
 } vendord_interface_t;
 
-CFG_TUSB_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
+CFG_TUSB_MEM_SECTION static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
 
 #define ITF_MEM_RESET_SIZE   offsetof(vendord_interface_t, rx_ff)
 
@@ -86,8 +86,8 @@ static void _prep_out_transaction (vendord_interface_t* p_itf)
 {
   uint8_t const rhport = 0;
 
-  // skip if previous transfer not complete
-  if ( usbd_edpt_busy(rhport, p_itf->ep_out) ) return;
+    // claim endpoint
+  TU_VERIFY(usbd_edpt_claim(rhport, p_itf->ep_out), );
 
   // Prepare for incoming data but only allow what we can store in the ring buffer.
   uint16_t max_read = tu_fifo_remaining(&p_itf->rx_ff);
@@ -95,6 +95,11 @@ static void _prep_out_transaction (vendord_interface_t* p_itf)
   {
     usbd_edpt_xfer(rhport, p_itf->ep_out, p_itf->epout_buf, CFG_TUD_VENDOR_EPSIZE);
   }
+  else
+  {
+    // Release endpoint since we don't make any transfer
+    usbd_edpt_release(rhport, p_itf->ep_out);
+  }
 }
 
 uint32_t tud_vendor_n_read (uint8_t itf, void* buffer, uint32_t bufsize)
@@ -115,37 +120,47 @@ void tud_vendor_n_read_flush (uint8_t itf)
 //--------------------------------------------------------------------+
 // Write API
 //--------------------------------------------------------------------+
-static uint16_t maybe_transmit(vendord_interface_t* p_itf)
-{
-  uint8_t const rhport = 0;
-
-  // skip if previous transfer not complete
-  TU_VERIFY( !usbd_edpt_busy(rhport, p_itf->ep_in) );
-
-  uint16_t count = tu_fifo_read_n(&p_itf->tx_ff, p_itf->epin_buf, CFG_TUD_VENDOR_EPSIZE);
-  if (count > 0)
-  {
-    TU_ASSERT( usbd_edpt_xfer(rhport, p_itf->ep_in, p_itf->epin_buf, count) );
-  }
-  return count;
-}
-
 uint32_t tud_vendor_n_write (uint8_t itf, void const* buffer, uint32_t bufsize)
 {
   vendord_interface_t* p_itf = &_vendord_itf[itf];
   uint16_t ret = tu_fifo_write_n(&p_itf->tx_ff, buffer, (uint16_t) bufsize);
+
+  // flush if queue more than packet size
   if (tu_fifo_count(&p_itf->tx_ff) >= CFG_TUD_VENDOR_EPSIZE) {
-    maybe_transmit(p_itf);
+    tud_vendor_n_write_flush(itf);
   }
   return ret;
 }
 
-uint32_t tud_vendor_n_flush (uint8_t itf)
+uint32_t tud_vendor_n_write_flush (uint8_t itf)
 {
   vendord_interface_t* p_itf = &_vendord_itf[itf];
-  uint32_t ret = maybe_transmit(p_itf);
 
-  return ret;
+  // Skip if usb is not ready yet
+  TU_VERIFY( tud_ready(), 0 );
+
+  // No data to send
+  if ( !tu_fifo_count(&p_itf->tx_ff) ) return 0;
+
+  uint8_t const rhport = 0;
+
+  // Claim the endpoint
+  TU_VERIFY( usbd_edpt_claim(rhport, p_itf->ep_in), 0 );
+
+  // Pull data from FIFO
+  uint16_t const count = tu_fifo_read_n(&p_itf->tx_ff, p_itf->epin_buf, sizeof(p_itf->epin_buf));
+
+  if ( count )
+  {
+    TU_ASSERT( usbd_edpt_xfer(rhport, p_itf->ep_in, p_itf->epin_buf, count), 0 );
+    return count;
+  }else
+  {
+    // Release endpoint since we don't make any transfer
+    // Note: data is dropped if terminal is not connected
+    usbd_edpt_release(rhport, p_itf->ep_in);
+    return 0;
+  }
 }
 
 uint32_t tud_vendor_n_write_available (uint8_t itf)
@@ -225,10 +240,10 @@ uint16_t vendord_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, ui
     // Prepare for incoming data
     if ( p_vendor->ep_out )
     {
-      TU_ASSERT(usbd_edpt_xfer(rhport, p_vendor->ep_out, p_vendor->epout_buf, sizeof(p_vendor->epout_buf)), 0);
+      _prep_out_transaction(p_vendor);
     }
 
-    if ( p_vendor->ep_in ) maybe_transmit(p_vendor);
+    if ( p_vendor->ep_in ) tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf));
   }
 
   return (uint16_t) ((uintptr_t) p_desc - (uintptr_t) desc_itf);
@@ -263,7 +278,7 @@ bool vendord_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint
   {
     if (tud_vendor_tx_cb) tud_vendor_tx_cb(itf, (uint16_t) xferred_bytes);
     // Send complete, try to send more if possible
-    maybe_transmit(p_itf);
+    tud_vendor_n_write_flush(itf);
   }
 
   return true;

From 1fb2a2f1bd61f06dc9384df1b9df3b39aeec42cf Mon Sep 17 00:00:00 2001
From: epatstarkey <58745560+epatstarkey@users.noreply.github.com>
Date: Tue, 28 Mar 2023 14:01:33 -0500
Subject: [PATCH 1621/2085] Update vendor_device.c

---
 src/class/vendor/vendor_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 260da0125..93596ee33 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -59,7 +59,7 @@ typedef struct
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE];
 } vendord_interface_t;
 
-CFG_TUSB_MEM_SECTION static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
+CFG_TUSB_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
 
 #define ITF_MEM_RESET_SIZE   offsetof(vendord_interface_t, rx_ff)
 

From 99315bcca35e1ffb9d14705a0cd533f962bc79eb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 29 Mar 2023 14:23:11 +0700
Subject: [PATCH 1622/2085] adding more cmake support

---
 .gitignore                       | 2 ++
 examples/CMakeLists.txt          | 9 +++++++++
 hw/bsp/rp2040/rp2040-openocd.cfg | 3 +++
 3 files changed, 14 insertions(+)
 create mode 100644 examples/CMakeLists.txt
 create mode 100644 hw/bsp/rp2040/rp2040-openocd.cfg

diff --git a/.gitignore b/.gitignore
index bd4271925..268decfc6 100644
--- a/.gitignore
+++ b/.gitignore
@@ -28,6 +28,8 @@ cov-int
 *-build-dir
 /_bin/
 __pycache__
+cmake-build-*
+sdkconfig
 
 # submodules
 hw/mcu/allwinner
diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt
new file mode 100644
index 000000000..8f5626fa9
--- /dev/null
+++ b/examples/CMakeLists.txt
@@ -0,0 +1,9 @@
+cmake_minimum_required(VERSION 3.5)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../hw/bsp/family_support.cmake)
+
+project(tinyusb_examples)
+
+add_subdirectory(device)
+add_subdirectory(dual)
+add_subdirectory(host)
diff --git a/hw/bsp/rp2040/rp2040-openocd.cfg b/hw/bsp/rp2040/rp2040-openocd.cfg
new file mode 100644
index 000000000..3364c595e
--- /dev/null
+++ b/hw/bsp/rp2040/rp2040-openocd.cfg
@@ -0,0 +1,3 @@
+source [find interface/cmsis-dap.cfg]
+adapter speed 5000
+source [find target/rp2040.cfg]

From 96718b7ca08d1d74cf1ecfb3816b57df50bf1616 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 30 Mar 2023 00:31:26 +0700
Subject: [PATCH 1623/2085] merge s2 and s3, update cmake for espressif, add
 tinyusb_src as component

---
 .../device/cdc_msc_freertos/CMakeLists.txt    |   3 +-
 .../cdc_msc_freertos/src/CMakeLists.txt       |  26 +--
 examples/rules.mk                             |   2 +-
 hw/bsp/esp32s2/boards/CMakeLists.txt          |  12 --
 .../adafruit_feather_esp32s2/board.cmake      |  17 --
 .../boards/adafruit_magtag_29gray/board.cmake |  17 --
 .../boards/adafruit_metro_esp32s2/board.cmake |  17 --
 .../boards/espressif_kaluga_1/board.cmake     |  17 --
 .../boards/espressif_saola_1/board.cmake      |  17 --
 hw/bsp/esp32s2/family.cmake                   |   7 -
 hw/bsp/esp32s3/boards/esp32s3.c               | 152 ----------------
 .../boards/espressif_addax_1/board.cmake      |   7 -
 .../boards/espressif_s3_devkitc/board.cmake   |   7 -
 .../boards/espressif_s3_devkitm/board.cmake   |   7 -
 .../components/led_strip/CMakeLists.txt       |   7 -
 .../components/led_strip/include/led_strip.h  | 126 -------------
 .../led_strip/src/led_strip_rmt_ws2812.c      | 171 ------------------
 hw/bsp/esp32s3/family.cmake                   |   7 -
 hw/bsp/esp32s3/family.mk                      |  25 ---
 .../boards/CMakeLists.txt                     |   4 +-
 .../adafruit_feather_esp32s2/board.cmake      |   3 +
 .../boards/adafruit_feather_esp32s2/board.h   |   0
 .../boards/adafruit_magtag_29gray/board.cmake |   3 +
 .../boards/adafruit_magtag_29gray/board.h     |   0
 .../boards/adafruit_metro_esp32s2/board.cmake |   3 +
 .../boards/adafruit_metro_esp32s2/board.h     |   0
 .../boards/espressif_addax_1/board.cmake      |   3 +
 .../boards/espressif_addax_1/board.h          |   0
 .../boards/espressif_kaluga_1/board.cmake     |   3 +
 .../boards/espressif_kaluga_1/board.h         |   0
 .../boards/espressif_s3_devkitc/board.cmake   |   3 +
 .../boards/espressif_s3_devkitc/board.h       |   0
 .../boards/espressif_s3_devkitm/board.cmake   |   3 +
 .../boards/espressif_s3_devkitm/board.h       |   0
 .../boards/espressif_saola_1/board.cmake      |   3 +
 .../boards/espressif_saola_1/board.h          |   0
 .../esp32s2.c => espressif/boards/family.c}   |   0
 .../components/led_strip/CMakeLists.txt       |   0
 .../components/led_strip/include/led_strip.h  |   0
 .../led_strip/src/led_strip_rmt_ws2812.c      |   0
 .../components/tinyusb_src/CMakeLists.txt     |  60 ++++++
 hw/bsp/espressif/family.cmake                 |   9 +
 hw/bsp/{esp32s2 => espressif}/family.mk       |  17 +-
 tools/build_esp32sx.py                        |   5 +-
 tools/build_family.py                         |   2 +-
 45 files changed, 114 insertions(+), 651 deletions(-)
 delete mode 100644 hw/bsp/esp32s2/boards/CMakeLists.txt
 delete mode 100644 hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
 delete mode 100644 hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
 delete mode 100644 hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
 delete mode 100644 hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
 delete mode 100644 hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
 delete mode 100644 hw/bsp/esp32s2/family.cmake
 delete mode 100644 hw/bsp/esp32s3/boards/esp32s3.c
 delete mode 100644 hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
 delete mode 100644 hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
 delete mode 100644 hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
 delete mode 100644 hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
 delete mode 100644 hw/bsp/esp32s3/components/led_strip/include/led_strip.h
 delete mode 100644 hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
 delete mode 100644 hw/bsp/esp32s3/family.cmake
 delete mode 100644 hw/bsp/esp32s3/family.mk
 rename hw/bsp/{esp32s3 => espressif}/boards/CMakeLists.txt (73%)
 create mode 100644 hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
 rename hw/bsp/{esp32s2 => espressif}/boards/adafruit_feather_esp32s2/board.h (100%)
 create mode 100644 hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake
 rename hw/bsp/{esp32s2 => espressif}/boards/adafruit_magtag_29gray/board.h (100%)
 create mode 100644 hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
 rename hw/bsp/{esp32s2 => espressif}/boards/adafruit_metro_esp32s2/board.h (100%)
 create mode 100644 hw/bsp/espressif/boards/espressif_addax_1/board.cmake
 rename hw/bsp/{esp32s3 => espressif}/boards/espressif_addax_1/board.h (100%)
 create mode 100644 hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake
 rename hw/bsp/{esp32s2 => espressif}/boards/espressif_kaluga_1/board.h (100%)
 create mode 100644 hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake
 rename hw/bsp/{esp32s3 => espressif}/boards/espressif_s3_devkitc/board.h (100%)
 create mode 100644 hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake
 rename hw/bsp/{esp32s3 => espressif}/boards/espressif_s3_devkitm/board.h (100%)
 create mode 100644 hw/bsp/espressif/boards/espressif_saola_1/board.cmake
 rename hw/bsp/{esp32s2 => espressif}/boards/espressif_saola_1/board.h (100%)
 rename hw/bsp/{esp32s2/boards/esp32s2.c => espressif/boards/family.c} (100%)
 rename hw/bsp/{esp32s2 => espressif}/components/led_strip/CMakeLists.txt (100%)
 rename hw/bsp/{esp32s2 => espressif}/components/led_strip/include/led_strip.h (100%)
 rename hw/bsp/{esp32s2 => espressif}/components/led_strip/src/led_strip_rmt_ws2812.c (100%)
 create mode 100644 hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
 create mode 100644 hw/bsp/espressif/family.cmake
 rename hw/bsp/{esp32s2 => espressif}/family.mk (62%)

diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index cbd75efd6..82bf79f19 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -16,7 +16,6 @@ project(${PROJECT})
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
 # Check for -DFAMILY=
-if(FAMILY MATCHES "^esp32s[2-3]")
-else()
+if(NOT FAMILY  STREQUAL "espressif")
   message(FATAL_ERROR "Invalid FAMILY specified: ${FAMILY}")
 endif()
diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index 9216e2b49..e433e5074 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -1,35 +1,11 @@
 idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c"
                     INCLUDE_DIRS "."
-                    REQUIRES freertos soc)
-
-file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake)
-
-if(EXISTS ${board_cmake})
-    include(${board_cmake})
-endif()
+                    REQUIRES freertos soc tinyusb_src)
 
 target_include_directories(${COMPONENT_TARGET} PUBLIC
   "${TOP}/hw"
-  "${TOP}/src"
 )
 
 target_compile_definitions(${COMPONENT_TARGET} PUBLIC
   ESP_PLATFORM
 )
-
-target_sources(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/src/tusb.c"
-  "${TOP}/src/common/tusb_fifo.c"
-  "${TOP}/src/device/usbd.c"
-  "${TOP}/src/device/usbd_control.c"
-  "${TOP}/src/class/cdc/cdc_device.c"
-  "${TOP}/src/class/dfu/dfu_rt_device.c"
-  "${TOP}/src/class/hid/hid_device.c"
-  "${TOP}/src/class/midi/midi_device.c"
-  "${TOP}/src/class/msc/msc_device.c"
-  "${TOP}/src/class/net/ecm_rndis_device.c"
-  "${TOP}/src/class/net/ncm_device.c"
-  "${TOP}/src/class/usbtmc/usbtmc_device.c"
-  "${TOP}/src/class/vendor/vendor_device.c"
-  "${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c"
-)
diff --git a/examples/rules.mk b/examples/rules.mk
index b85837c16..c125408df 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -7,7 +7,7 @@
 
 # ---------------- GNU Make Start -----------------------
 # ESP32-Sx and RP2040 has its own CMake build system
-ifeq (,$(findstring $(FAMILY),esp32s2 esp32s3 rp2040))
+ifeq (,$(findstring $(FAMILY),espressif rp2040))
 
 # ---------------------------------------
 # Compiler Flags
diff --git a/hw/bsp/esp32s2/boards/CMakeLists.txt b/hw/bsp/esp32s2/boards/CMakeLists.txt
deleted file mode 100644
index ff90acbde..000000000
--- a/hw/bsp/esp32s2/boards/CMakeLists.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-idf_component_register(SRCS esp32s2.c
-                    INCLUDE_DIRS "." "${BOARD}"
-                    PRIV_REQUIRES "driver"
-                    REQUIRES freertos src led_strip)
-
-# Apply board specific content
-include("${BOARD}/board.cmake")
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/hw"
-  "${TOP}/src"
-)
diff --git a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
deleted file mode 100644
index e39ceb887..000000000
--- a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: $ENV{IDF_TARGET}(${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
diff --git a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake b/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
deleted file mode 100644
index e39ceb887..000000000
--- a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: $ENV{IDF_TARGET}(${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
diff --git a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
deleted file mode 100644
index 16b0e9cdd..000000000
--- a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
diff --git a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake b/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
deleted file mode 100644
index 16b0e9cdd..000000000
--- a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
diff --git a/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake b/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
deleted file mode 100644
index 16b0e9cdd..000000000
--- a/hw/bsp/esp32s2/boards/espressif_saola_1/board.cmake
+++ /dev/null
@@ -1,17 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-idf_build_get_property(idf_target IDF_TARGET)
-
-message(STATUS "Apply ${BOARD}(${idf_target}) specific options for component: ${COMPONENT_TARGET}")
-
-if(NOT ${idf_target} STREQUAL "esp32s2")
-    message(FATAL_ERROR "Incorrect target for board ${BOARD}: (${idf_target}), try to clean the build first." )
-endif()
-
-set(IDF_TARGET "esp32s2" FORCE)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S2"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
diff --git a/hw/bsp/esp32s2/family.cmake b/hw/bsp/esp32s2/family.cmake
deleted file mode 100644
index 0973adcac..000000000
--- a/hw/bsp/esp32s2/family.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-cmake_minimum_required(VERSION 3.5)
-
-# Add example src and bsp directories
-set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s2/boards" "${TOP}/hw/bsp/esp32s2/components")
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-set(SUPPORTED_TARGETS esp32s2)
-set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/esp32s3/boards/esp32s3.c b/hw/bsp/esp32s3/boards/esp32s3.c
deleted file mode 100644
index 015d8305b..000000000
--- a/hw/bsp/esp32s3/boards/esp32s3.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2020, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "../../board.h"
-#include "board.h"
-
-#include "esp_rom_gpio.h"
-#include "hal/gpio_ll.h"
-#include "hal/usb_hal.h"
-#include "soc/usb_periph.h"
-
-#include "driver/rmt.h"
-
-#if ESP_IDF_VERSION_MAJOR > 4
-  #include "esp_private/periph_ctrl.h"
-#else
-  #include "driver/periph_ctrl.h"
-#endif
-
-#ifdef NEOPIXEL_PIN
-#include "led_strip.h"
-static led_strip_t *strip;
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-
-static void configure_pins(usb_hal_context_t *usb);
-
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void)
-{
-
-#ifdef NEOPIXEL_PIN
-  #ifdef NEOPIXEL_POWER_PIN
-  gpio_reset_pin(NEOPIXEL_POWER_PIN);
-  gpio_set_direction(NEOPIXEL_POWER_PIN, GPIO_MODE_OUTPUT);
-  gpio_set_level(NEOPIXEL_POWER_PIN, NEOPIXEL_POWER_STATE);
-  #endif
-
-  // WS2812 Neopixel driver with RMT peripheral
-  rmt_config_t config = RMT_DEFAULT_CONFIG_TX(NEOPIXEL_PIN, RMT_CHANNEL_0);
-  config.clk_div = 2; // set counter clock to 40MHz
-
-  rmt_config(&config);
-  rmt_driver_install(config.channel, 0, 0);
-
-  led_strip_config_t strip_config = LED_STRIP_DEFAULT_CONFIG(1, (led_strip_dev_t) config.channel);
-  strip = led_strip_new_rmt_ws2812(&strip_config);
-  strip->clear(strip, 100); // off led
-#endif
-
-  // Button
-  esp_rom_gpio_pad_select_gpio(BUTTON_PIN);
-  gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
-  gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
-
-  // USB Controller Hal init
-  periph_module_reset(PERIPH_USB_MODULE);
-  periph_module_enable(PERIPH_USB_MODULE);
-
-  usb_hal_context_t hal = {
-    .use_external_phy = false // use built-in PHY
-  };
-  usb_hal_init(&hal);
-  configure_pins(&hal);
-}
-
-static void configure_pins(usb_hal_context_t *usb)
-{
-  /* usb_periph_iopins currently configures USB_OTG as USB Device.
-   * Introduce additional parameters in usb_hal_context_t when adding support
-   * for USB Host.
-   */
-  for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
-    if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
-      esp_rom_gpio_pad_select_gpio(iopin->pin);
-      if (iopin->is_output) {
-        esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false);
-      } else {
-        esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false);
-#if ESP_IDF_VERSION_MAJOR > 4
-        if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT))
-#else
-        if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH))
-#endif
-        {
-          gpio_ll_input_enable(&GPIO, iopin->pin);
-        }
-      }
-      esp_rom_gpio_pad_unhold(iopin->pin);
-    }
-  }
-  if (!usb->use_external_phy) {
-    gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
-    gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
-  }
-}
-
-// Turn LED on or off
-void board_led_write(bool state)
-{
-#ifdef NEOPIXEL_PIN
-  strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00);
-  strip->refresh(strip, 100);
-#endif
-}
-
-// Get the current state of button
-// a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void)
-{
-  return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
-}
-
-// Get characters from UART
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
-
-// Send characters to UART
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake b/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
deleted file mode 100644
index 2bff4f836..000000000
--- a/hw/bsp/esp32s3/boards/espressif_addax_1/board.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
deleted file mode 100644
index 2bff4f836..000000000
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake b/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
deleted file mode 100644
index 2bff4f836..000000000
--- a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-# Apply board specific content here
-target_include_directories(${COMPONENT_LIB} PRIVATE .)
-
-target_compile_options(${COMPONENT_TARGET} PUBLIC
-  "-DCFG_TUSB_MCU=OPT_MCU_ESP32S3"
-  "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-)
diff --git a/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt b/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
deleted file mode 100644
index 8266c5a1c..000000000
--- a/hw/bsp/esp32s3/components/led_strip/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-set(component_srcs "src/led_strip_rmt_ws2812.c")
-
-idf_component_register(SRCS "${component_srcs}"
-                       INCLUDE_DIRS "include"
-                       PRIV_INCLUDE_DIRS ""
-                       PRIV_REQUIRES "driver"
-                       REQUIRES "")
diff --git a/hw/bsp/esp32s3/components/led_strip/include/led_strip.h b/hw/bsp/esp32s3/components/led_strip/include/led_strip.h
deleted file mode 100644
index a9dffc325..000000000
--- a/hw/bsp/esp32s3/components/led_strip/include/led_strip.h
+++ /dev/null
@@ -1,126 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "esp_err.h"
-
-/**
-* @brief LED Strip Type
-*
-*/
-typedef struct led_strip_s led_strip_t;
-
-/**
-* @brief LED Strip Device Type
-*
-*/
-typedef void *led_strip_dev_t;
-
-/**
-* @brief Declare of LED Strip Type
-*
-*/
-struct led_strip_s {
-    /**
-    * @brief Set RGB for a specific pixel
-    *
-    * @param strip: LED strip
-    * @param index: index of pixel to set
-    * @param red: red part of color
-    * @param green: green part of color
-    * @param blue: blue part of color
-    *
-    * @return
-    *      - ESP_OK: Set RGB for a specific pixel successfully
-    *      - ESP_ERR_INVALID_ARG: Set RGB for a specific pixel failed because of invalid parameters
-    *      - ESP_FAIL: Set RGB for a specific pixel failed because other error occurred
-    */
-    esp_err_t (*set_pixel)(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue);
-
-    /**
-    * @brief Refresh memory colors to LEDs
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for refreshing task
-    *
-    * @return
-    *      - ESP_OK: Refresh successfully
-    *      - ESP_ERR_TIMEOUT: Refresh failed because of timeout
-    *      - ESP_FAIL: Refresh failed because some other error occurred
-    *
-    * @note:
-    *      After updating the LED colors in the memory, a following invocation of this API is needed to flush colors to strip.
-    */
-    esp_err_t (*refresh)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Clear LED strip (turn off all LEDs)
-    *
-    * @param strip: LED strip
-    * @param timeout_ms: timeout value for clearing task
-    *
-    * @return
-    *      - ESP_OK: Clear LEDs successfully
-    *      - ESP_ERR_TIMEOUT: Clear LEDs failed because of timeout
-    *      - ESP_FAIL: Clear LEDs failed because some other error occurred
-    */
-    esp_err_t (*clear)(led_strip_t *strip, uint32_t timeout_ms);
-
-    /**
-    * @brief Free LED strip resources
-    *
-    * @param strip: LED strip
-    *
-    * @return
-    *      - ESP_OK: Free resources successfully
-    *      - ESP_FAIL: Free resources failed because error occurred
-    */
-    esp_err_t (*del)(led_strip_t *strip);
-};
-
-/**
-* @brief LED Strip Configuration Type
-*
-*/
-typedef struct {
-    uint32_t max_leds;   /*!< Maximum LEDs in a single strip */
-    led_strip_dev_t dev; /*!< LED strip device (e.g. RMT channel, PWM channel, etc) */
-} led_strip_config_t;
-
-/**
- * @brief Default configuration for LED strip
- *
- */
-#define LED_STRIP_DEFAULT_CONFIG(number, dev_hdl) \
-    {                                             \
-        .max_leds = number,                       \
-        .dev = dev_hdl,                           \
-    }
-
-/**
-* @brief Install a new ws2812 driver (based on RMT peripheral)
-*
-* @param config: LED strip configuration
-* @return
-*      LED strip instance or NULL
-*/
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c b/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
deleted file mode 100644
index fd1746cad..000000000
--- a/hw/bsp/esp32s3/components/led_strip/src/led_strip_rmt_ws2812.c
+++ /dev/null
@@ -1,171 +0,0 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#include <stdlib.h>
-#include <string.h>
-#include <sys/cdefs.h>
-#include "esp_log.h"
-#include "esp_attr.h"
-#include "led_strip.h"
-#include "driver/rmt.h"
-
-static const char *TAG = "ws2812";
-#define STRIP_CHECK(a, str, goto_tag, ret_value, ...)                             \
-    do                                                                            \
-    {                                                                             \
-        if (!(a))                                                                 \
-        {                                                                         \
-            ESP_LOGE(TAG, "%s(%d): " str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
-            ret = ret_value;                                                      \
-            goto goto_tag;                                                        \
-        }                                                                         \
-    } while (0)
-
-#define WS2812_T0H_NS (350)
-#define WS2812_T0L_NS (1000)
-#define WS2812_T1H_NS (1000)
-#define WS2812_T1L_NS (350)
-#define WS2812_RESET_US (280)
-
-static uint32_t ws2812_t0h_ticks = 0;
-static uint32_t ws2812_t1h_ticks = 0;
-static uint32_t ws2812_t0l_ticks = 0;
-static uint32_t ws2812_t1l_ticks = 0;
-
-typedef struct {
-    led_strip_t parent;
-    rmt_channel_t rmt_channel;
-    uint32_t strip_len;
-    uint8_t buffer[0];
-} ws2812_t;
-
-/**
- * @brief Convert RGB data to RMT format.
- *
- * @note For WS2812, R,G,B each contains 256 different choices (i.e. uint8_t)
- *
- * @param[in] src: source data, to converted to RMT format
- * @param[in] dest: place where to store the convert result
- * @param[in] src_size: size of source data
- * @param[in] wanted_num: number of RMT items that want to get
- * @param[out] translated_size: number of source data that got converted
- * @param[out] item_num: number of RMT items which are converted from source data
- */
-static void IRAM_ATTR ws2812_rmt_adapter(const void *src, rmt_item32_t *dest, size_t src_size,
-        size_t wanted_num, size_t *translated_size, size_t *item_num)
-{
-    if (src == NULL || dest == NULL) {
-        *translated_size = 0;
-        *item_num = 0;
-        return;
-    }
-    const rmt_item32_t bit0 = {{{ ws2812_t0h_ticks, 1, ws2812_t0l_ticks, 0 }}}; //Logical 0
-    const rmt_item32_t bit1 = {{{ ws2812_t1h_ticks, 1, ws2812_t1l_ticks, 0 }}}; //Logical 1
-    size_t size = 0;
-    size_t num = 0;
-    uint8_t *psrc = (uint8_t *)src;
-    rmt_item32_t *pdest = dest;
-    while (size < src_size && num < wanted_num) {
-        for (int i = 0; i < 8; i++) {
-            // MSB first
-            if (*psrc & (1 << (7 - i))) {
-                pdest->val =  bit1.val;
-            } else {
-                pdest->val =  bit0.val;
-            }
-            num++;
-            pdest++;
-        }
-        size++;
-        psrc++;
-    }
-    *translated_size = size;
-    *item_num = num;
-}
-
-static esp_err_t ws2812_set_pixel(led_strip_t *strip, uint32_t index, uint32_t red, uint32_t green, uint32_t blue)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(index < ws2812->strip_len, "index out of the maximum number of leds", err, ESP_ERR_INVALID_ARG);
-    uint32_t start = index * 3;
-    // In thr order of GRB
-    ws2812->buffer[start + 0] = green & 0xFF;
-    ws2812->buffer[start + 1] = red & 0xFF;
-    ws2812->buffer[start + 2] = blue & 0xFF;
-    return ESP_OK;
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_refresh(led_strip_t *strip, uint32_t timeout_ms)
-{
-    esp_err_t ret = ESP_OK;
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    STRIP_CHECK(rmt_write_sample(ws2812->rmt_channel, ws2812->buffer, ws2812->strip_len * 3, true) == ESP_OK,
-                "transmit RMT samples failed", err, ESP_FAIL);
-    return rmt_wait_tx_done(ws2812->rmt_channel, pdMS_TO_TICKS(timeout_ms));
-err:
-    return ret;
-}
-
-static esp_err_t ws2812_clear(led_strip_t *strip, uint32_t timeout_ms)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    // Write zero to turn off all leds
-    memset(ws2812->buffer, 0, ws2812->strip_len * 3);
-    return ws2812_refresh(strip, timeout_ms);
-}
-
-static esp_err_t ws2812_del(led_strip_t *strip)
-{
-    ws2812_t *ws2812 = __containerof(strip, ws2812_t, parent);
-    free(ws2812);
-    return ESP_OK;
-}
-
-led_strip_t *led_strip_new_rmt_ws2812(const led_strip_config_t *config)
-{
-    led_strip_t *ret = NULL;
-    STRIP_CHECK(config, "configuration can't be null", err, NULL);
-
-    // 24 bits per led
-    uint32_t ws2812_size = sizeof(ws2812_t) + config->max_leds * 3;
-    ws2812_t *ws2812 = calloc(1, ws2812_size);
-    STRIP_CHECK(ws2812, "request memory for ws2812 failed", err, NULL);
-
-    uint32_t counter_clk_hz = 0;
-    STRIP_CHECK(rmt_get_counter_clock((rmt_channel_t)config->dev, &counter_clk_hz) == ESP_OK,
-                "get rmt counter clock failed", err, NULL);
-    // ns -> ticks
-    float ratio = (float)counter_clk_hz / 1e9;
-    ws2812_t0h_ticks = (uint32_t)(ratio * WS2812_T0H_NS);
-    ws2812_t0l_ticks = (uint32_t)(ratio * WS2812_T0L_NS);
-    ws2812_t1h_ticks = (uint32_t)(ratio * WS2812_T1H_NS);
-    ws2812_t1l_ticks = (uint32_t)(ratio * WS2812_T1L_NS);
-
-    // set ws2812 to rmt adapter
-    rmt_translator_init((rmt_channel_t)config->dev, ws2812_rmt_adapter);
-
-    ws2812->rmt_channel = (rmt_channel_t)config->dev;
-    ws2812->strip_len = config->max_leds;
-
-    ws2812->parent.set_pixel = ws2812_set_pixel;
-    ws2812->parent.refresh = ws2812_refresh;
-    ws2812->parent.clear = ws2812_clear;
-    ws2812->parent.del = ws2812_del;
-
-    return &ws2812->parent;
-err:
-    return ret;
-}
diff --git a/hw/bsp/esp32s3/family.cmake b/hw/bsp/esp32s3/family.cmake
deleted file mode 100644
index 0bcad035e..000000000
--- a/hw/bsp/esp32s3/family.cmake
+++ /dev/null
@@ -1,7 +0,0 @@
-cmake_minimum_required(VERSION 3.5)
-
-# Add example src and bsp directories
-set(EXTRA_COMPONENT_DIRS "src" "${TOP}/hw/bsp/esp32s3/boards" "${TOP}/hw/bsp/esp32s3/components")
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-set(SUPPORTED_TARGETS esp32s3)
-set(FAMILY_MCUS ESP32S3)
diff --git a/hw/bsp/esp32s3/family.mk b/hw/bsp/esp32s3/family.mk
deleted file mode 100644
index d82a1c969..000000000
--- a/hw/bsp/esp32s3/family.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#DEPS_SUBMODULES +=
-
-.PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
-
-all:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) -DIDF_TARGET=esp32s3 build
-
-build: all
-
-clean:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) clean
-
-fullclean:
-	if test -f sdkconfig; then $(RM) -f sdkconfig ; fi
-	if test -d $(BUILD); then $(RM) -rf $(BUILD) ; fi
-
-flash bootloader-flash app-flash erase monitor dfu-flash dfu:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) $@
-
-uf2: $(BUILD)/$(PROJECT).uf2
-
-UF2_FAMILY_ID = 0xc47e5767
-$(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
-	@echo CREATE $@
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
diff --git a/hw/bsp/esp32s3/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt
similarity index 73%
rename from hw/bsp/esp32s3/boards/CMakeLists.txt
rename to hw/bsp/espressif/boards/CMakeLists.txt
index 311c6e900..3832037a9 100644
--- a/hw/bsp/esp32s3/boards/CMakeLists.txt
+++ b/hw/bsp/espressif/boards/CMakeLists.txt
@@ -1,4 +1,4 @@
-idf_component_register(SRCS esp32s3.c
+idf_component_register(SRCS family.c
                     INCLUDE_DIRS "." "${BOARD}"
                     PRIV_REQUIRES "driver"
                     REQUIRES freertos src led_strip)
@@ -6,7 +6,7 @@ idf_component_register(SRCS esp32s3.c
 # Apply board specific content
 include("${BOARD}/board.cmake")
 
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
+idf_component_get_property(FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
 target_include_directories(${COMPONENT_TARGET} PUBLIC
   "${FREERTOS_ORIG_INCLUDE_PATH}"
   "${TOP}/hw"
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
new file mode 100644
index 000000000..fcd2f6e9f
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
+set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h
similarity index 100%
rename from hw/bsp/esp32s2/boards/adafruit_feather_esp32s2/board.h
rename to hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h
diff --git a/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake
new file mode 100644
index 000000000..fcd2f6e9f
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
+set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h
similarity index 100%
rename from hw/bsp/esp32s2/boards/adafruit_magtag_29gray/board.h
rename to hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h
diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
new file mode 100644
index 000000000..fcd2f6e9f
--- /dev/null
+++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
+set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
similarity index 100%
rename from hw/bsp/esp32s2/boards/adafruit_metro_esp32s2/board.h
rename to hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
diff --git a/hw/bsp/espressif/boards/espressif_addax_1/board.cmake b/hw/bsp/espressif/boards/espressif_addax_1/board.cmake
new file mode 100644
index 000000000..bc528e9fa
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_addax_1/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
+set(FAMILY_MCUS ESP32S3)
diff --git a/hw/bsp/esp32s3/boards/espressif_addax_1/board.h b/hw/bsp/espressif/boards/espressif_addax_1/board.h
similarity index 100%
rename from hw/bsp/esp32s3/boards/espressif_addax_1/board.h
rename to hw/bsp/espressif/boards/espressif_addax_1/board.h
diff --git a/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake b/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake
new file mode 100644
index 000000000..fcd2f6e9f
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
+set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
similarity index 100%
rename from hw/bsp/esp32s2/boards/espressif_kaluga_1/board.h
rename to hw/bsp/espressif/boards/espressif_kaluga_1/board.h
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake
new file mode 100644
index 000000000..bc528e9fa
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
+set(FAMILY_MCUS ESP32S3)
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h
similarity index 100%
rename from hw/bsp/esp32s3/boards/espressif_s3_devkitc/board.h
rename to hw/bsp/espressif/boards/espressif_s3_devkitc/board.h
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake
new file mode 100644
index 000000000..bc528e9fa
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s3")
+set(FAMILY_MCUS ESP32S3)
diff --git a/hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
similarity index 100%
rename from hw/bsp/esp32s3/boards/espressif_s3_devkitm/board.h
rename to hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
diff --git a/hw/bsp/espressif/boards/espressif_saola_1/board.cmake b/hw/bsp/espressif/boards/espressif_saola_1/board.cmake
new file mode 100644
index 000000000..fcd2f6e9f
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_saola_1/board.cmake
@@ -0,0 +1,3 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
+set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/esp32s2/boards/espressif_saola_1/board.h b/hw/bsp/espressif/boards/espressif_saola_1/board.h
similarity index 100%
rename from hw/bsp/esp32s2/boards/espressif_saola_1/board.h
rename to hw/bsp/espressif/boards/espressif_saola_1/board.h
diff --git a/hw/bsp/esp32s2/boards/esp32s2.c b/hw/bsp/espressif/boards/family.c
similarity index 100%
rename from hw/bsp/esp32s2/boards/esp32s2.c
rename to hw/bsp/espressif/boards/family.c
diff --git a/hw/bsp/esp32s2/components/led_strip/CMakeLists.txt b/hw/bsp/espressif/components/led_strip/CMakeLists.txt
similarity index 100%
rename from hw/bsp/esp32s2/components/led_strip/CMakeLists.txt
rename to hw/bsp/espressif/components/led_strip/CMakeLists.txt
diff --git a/hw/bsp/esp32s2/components/led_strip/include/led_strip.h b/hw/bsp/espressif/components/led_strip/include/led_strip.h
similarity index 100%
rename from hw/bsp/esp32s2/components/led_strip/include/led_strip.h
rename to hw/bsp/espressif/components/led_strip/include/led_strip.h
diff --git a/hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c b/hw/bsp/espressif/components/led_strip/src/led_strip_rmt_ws2812.c
similarity index 100%
rename from hw/bsp/esp32s2/components/led_strip/src/led_strip_rmt_ws2812.c
rename to hw/bsp/espressif/components/led_strip/src/led_strip_rmt_ws2812.c
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
new file mode 100644
index 000000000..0bd404cee
--- /dev/null
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -0,0 +1,60 @@
+idf_build_get_property(target IDF_TARGET)
+
+set(srcs)
+set(includes_public)
+set(includes_private)
+set(compile_options)
+set(tusb_src "${TOP}/src")
+
+if(target STREQUAL "esp32s3")
+  set(tusb_mcu "OPT_MCU_ESP32S3")
+elseif(target STREQUAL "esp32s2")
+  set(tusb_mcu "OPT_MCU_ESP32S2")
+else()
+  # CONFIG_TINYUSB dependency has been guaranteed by Kconfig logic,
+  # So it's not possible that cmake goes here
+  message(FATAL_ERROR "TinyUSB is not support on ${target}.")
+  return()
+endif()
+
+list(APPEND compile_options
+    "-DCFG_TUSB_MCU=${tusb_mcu}"
+    #"-DCFG_TUSB_DEBUG=1"
+    )
+
+idf_component_get_property(freertos_component_dir freertos COMPONENT_DIR)
+
+list(APPEND includes_private
+    "${tusb_src}"
+    )
+
+list(APPEND includes_public
+    "${tusb_src}"
+    # The FreeRTOS API include convention in tinyusb is different from esp-idf
+    "${freertos_component_dir}/include/freertos"
+    )
+
+list(APPEND srcs
+    "${tusb_src}/tusb.c"
+    "${tusb_src}/common/tusb_fifo.c"
+    "${tusb_src}/device/usbd.c"
+    "${tusb_src}/device/usbd_control.c"
+    "${tusb_src}/class/cdc/cdc_device.c"
+    "${tusb_src}/class/dfu/dfu_rt_device.c"
+    "${tusb_src}/class/hid/hid_device.c"
+    "${tusb_src}/class/midi/midi_device.c"
+    "${tusb_src}/class/msc/msc_device.c"
+    "${tusb_src}/class/net/ecm_rndis_device.c"
+    "${tusb_src}/class/net/ncm_device.c"
+    "${tusb_src}/class/usbtmc/usbtmc_device.c"
+    "${tusb_src}/class/vendor/vendor_device.c"
+    "${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c"
+    )
+
+idf_component_register(SRCS ${srcs}
+    INCLUDE_DIRS ${includes_public}
+    PRIV_INCLUDE_DIRS ${includes_private}
+    PRIV_REQUIRES src
+    )
+
+target_compile_options(${COMPONENT_LIB} PUBLIC ${compile_options})
diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake
new file mode 100644
index 000000000..19b9139c3
--- /dev/null
+++ b/hw/bsp/espressif/family.cmake
@@ -0,0 +1,9 @@
+cmake_minimum_required(VERSION 3.5)
+
+# Apply board specific content
+include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
+
+# Add example src and bsp directories
+set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components")
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
diff --git a/hw/bsp/esp32s2/family.mk b/hw/bsp/espressif/family.mk
similarity index 62%
rename from hw/bsp/esp32s2/family.mk
rename to hw/bsp/espressif/family.mk
index fba0f038b..0dc21b8eb 100644
--- a/hw/bsp/esp32s2/family.mk
+++ b/hw/bsp/espressif/family.mk
@@ -1,9 +1,21 @@
 #DEPS_SUBMODULES +=
 
+UF2_FAMILY_ID_esp32s2 = 0xbfdd4eee
+UF2_FAMILY_ID_esp32s3 = 0xc47e5767
+
+BOARD_CMAKE := $(file < $(TOP)/$(BOARD_PATH)/board.cmake)
+ifneq ($(findstring esp32s2,$(BOARD_CMAKE)),)
+	IDF_TARGET = esp32s2
+else
+ifneq ($(findstring esp32s3,$(BOARD_CMAKE)),)
+	IDF_TARGET = esp32s3
+endif
+endif
+
 .PHONY: all clean flash bootloader-flash app-flash erase monitor dfu-flash dfu
 
 all:
-	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) -DIDF_TARGET=esp32s2 build
+	idf.py -B$(BUILD) -DFAMILY=$(FAMILY) -DBOARD=$(BOARD) $(CMAKE_DEFSYM) build
 
 build: all
 
@@ -17,7 +29,6 @@ clean flash bootloader-flash app-flash erase monitor dfu-flash dfu size size-com
 
 uf2: $(BUILD)/$(PROJECT).uf2
 
-UF2_FAMILY_ID = 0xbfdd4eee
 $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).bin
 	@echo CREATE $@
-	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID) -b 0x0 -c -o $@ $^
+	$(PYTHON) $(TOP)/tools/uf2/utils/uf2conv.py -f $(UF2_FAMILY_ID_$(IDF_TARGET)) -b 0x0 -c -o $@ $^
diff --git a/tools/build_esp32sx.py b/tools/build_esp32sx.py
index 2947a0a6b..00783bf58 100644
--- a/tools/build_esp32sx.py
+++ b/tools/build_esp32sx.py
@@ -37,10 +37,7 @@ all_examples.sort()
 
 # Build all boards if not specified
 all_boards = []
-for entry in os.scandir("hw/bsp/esp32s2/boards"):
-    if entry.is_dir():
-        all_boards.append(entry.name)
-for entry in os.scandir("hw/bsp/esp32s3/boards"):
+for entry in os.scandir("hw/bsp/espressif/boards"):
     if entry.is_dir():
         all_boards.append(entry.name)
 filter_with_input(all_boards)
diff --git a/tools/build_family.py b/tools/build_family.py
index 532938d42..ae0bb282d 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -52,7 +52,7 @@ if __name__ == '__main__':
     # If family are not specified in arguments, build all
     all_families = []
     for entry in os.scandir("hw/bsp"):
-        if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name not in ("esp32s2", "esp32s3"):
+        if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name != 'espressif'
             all_families.append(entry.name)
     filter_with_input(all_families)
     all_families.sort()

From 641613c428e10a029b172c318d4db077e35fee7d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 30 Mar 2023 10:41:11 +0700
Subject: [PATCH 1624/2085] update all cmake for esp32 build

---
 examples/device/board_test/CMakeLists.txt     | 27 ++++++---------
 examples/device/board_test/src/CMakeLists.txt | 16 ++-------
 examples/device/board_test/src/main.c         |  2 +-
 .../device/cdc_msc_freertos/CMakeLists.txt    |  2 +-
 .../cdc_msc_freertos/src/CMakeLists.txt       |  4 ---
 .../device/cdc_msc_freertos/src/tusb_config.h |  2 ++
 .../hid_composite_freertos/CMakeLists.txt     | 20 ++++++-----
 .../hid_composite_freertos/src/CMakeLists.txt | 34 ++-----------------
 .../hid_composite_freertos/src/tusb_config.h  |  2 ++
 hw/bsp/espressif/boards/CMakeLists.txt        |  8 +----
 hw/bsp/espressif/boards/family.c              |  2 +-
 .../components/tinyusb_src/CMakeLists.txt     |  1 +
 tools/build_family.py                         |  4 +--
 13 files changed, 40 insertions(+), 84 deletions(-)

diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index 37113578e..b21d56f9e 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -1,29 +1,24 @@
 cmake_minimum_required(VERSION 3.5)
 
-include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
-
-# Check for -DFAMILY=
-if(FAMILY MATCHES "^esp32s[2-3]")
-  # use BOARD-Directory name for project id
-  get_filename_component(PROJECT ${CMAKE_CURRENT_SOURCE_DIR} NAME)
-  set(PROJECT ${BOARD}-${PROJECT})
-
+# -DFAMILY=espressif
+if(FAMILY STREQUAL "espressif")
   # TOP is absolute path to root directory of TinyUSB git repo
   set(TOP "../../..")
   get_filename_component(TOP "${TOP}" REALPATH)
+endif()
 
-  project(${PROJECT})
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
-else()
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-  # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
-  family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+project(${PROJECT})
 
-  project(${PROJECT})
-
-  # Checks this example is valid for the family and initializes the project
-  family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Other family such as rp2040
+if(NOT FAMILY STREQUAL "espressif")
   add_executable(${PROJECT})
 
   # Example source
diff --git a/examples/device/board_test/src/CMakeLists.txt b/examples/device/board_test/src/CMakeLists.txt
index 37625f441..03f4c7505 100644
--- a/examples/device/board_test/src/CMakeLists.txt
+++ b/examples/device/board_test/src/CMakeLists.txt
@@ -1,17 +1,7 @@
-# FAMILY = esp32sx
 idf_component_register(SRCS "main.c"
                     INCLUDE_DIRS "."
-                    REQUIRES freertos soc)
+                    REQUIRES freertos soc tinyusb_src)
 
-file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake)
-
-if(EXISTS ${board_cmake})
-    include(${board_cmake})
-endif()
-
-idf_component_get_property( FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
 target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${FREERTOS_ORIG_INCLUDE_PATH}"
-  "${TOP}/hw"
-  "${TOP}/src"
-)
+    "${TOP}/hw"
+    )
diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index 3f8d55c52..b11f6f2bb 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -30,7 +30,7 @@
 #include "bsp/board.h"
 
 //--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF PROTYPES
+// MACRO CONSTANT TYPEDEF PROTOTYPES
 //--------------------------------------------------------------------+
 
 /* Blink pattern
diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 82bf79f19..573924b18 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -16,6 +16,6 @@ project(${PROJECT})
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
 # Check for -DFAMILY=
-if(NOT FAMILY  STREQUAL "espressif")
+if(NOT FAMILY STREQUAL "espressif")
   message(FATAL_ERROR "Invalid FAMILY specified: ${FAMILY}")
 endif()
diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index e433e5074..9c597b302 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -5,7 +5,3 @@ idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c"
 target_include_directories(${COMPONENT_TARGET} PUBLIC
   "${TOP}/hw"
 )
-
-target_compile_definitions(${COMPONENT_TARGET} PUBLIC
-  ESP_PLATFORM
-)
diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h
index 0ec8896b9..91efe7d40 100644
--- a/examples/device/cdc_msc_freertos/src/tusb_config.h
+++ b/examples/device/cdc_msc_freertos/src/tusb_config.h
@@ -54,7 +54,9 @@
 #endif
 
 // This examples use FreeRTOS
+#ifndef CFG_TUSB_OS
 #define CFG_TUSB_OS           OPT_OS_FREERTOS
+#endif
 
 // Espressif IDF requires "freertos/" prefix in include path
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt
index ed734b954..573924b18 100644
--- a/examples/device/hid_composite_freertos/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/CMakeLists.txt
@@ -1,17 +1,21 @@
 cmake_minimum_required(VERSION 3.5)
 
-# use BOARD-Directory name for project id
-get_filename_component(PROJECT ${CMAKE_CURRENT_SOURCE_DIR} NAME)
-set(PROJECT ${BOARD}-${PROJECT})
-
 # TOP is absolute path to root directory of TinyUSB git repo
+# needed for esp32sx build. TODO could be removed later on
 set(TOP "../../..")
 get_filename_component(TOP "${TOP}" REALPATH)
 
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT})
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
 # Check for -DFAMILY=
-if(FAMILY MATCHES "^esp32s[2-3]")
-  include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
-  project(${PROJECT})
-else()
+if(NOT FAMILY STREQUAL "espressif")
   message(FATAL_ERROR "Invalid FAMILY specified: ${FAMILY}")
 endif()
diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt
index 25da8fcd7..1e1e465e0 100644
--- a/examples/device/hid_composite_freertos/src/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt
@@ -1,35 +1,7 @@
 idf_component_register(SRCS "main.c" "usb_descriptors.c"
                     INCLUDE_DIRS "."
-                    REQUIRES freertos soc)
-
-file(TO_NATIVE_PATH "${TOP}/hw/bsp/${FAMILY}/boards/${BOARD}/board.cmake" board_cmake)
-
-if(EXISTS ${board_cmake})
-    include(${board_cmake})
-endif()
+                    REQUIRES freertos soc tinyusb_src)
 
 target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/hw"
-  "${TOP}/src"
-)
-
-target_compile_definitions(${COMPONENT_TARGET} PUBLIC
-  ESP_PLATFORM
-)
-
-target_sources(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/src/tusb.c"
-  "${TOP}/src/common/tusb_fifo.c"
-  "${TOP}/src/device/usbd.c"
-  "${TOP}/src/device/usbd_control.c"
-  "${TOP}/src/class/cdc/cdc_device.c"
-  "${TOP}/src/class/dfu/dfu_rt_device.c"
-  "${TOP}/src/class/hid/hid_device.c"
-  "${TOP}/src/class/midi/midi_device.c"
-  "${TOP}/src/class/msc/msc_device.c"
-  "${TOP}/src/class/net/ecm_rndis_device.c"
-  "${TOP}/src/class/net/ncm_device.c"
-  "${TOP}/src/class/usbtmc/usbtmc_device.c"
-  "${TOP}/src/class/vendor/vendor_device.c"
-  "${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c"
-)
+    "${TOP}/hw"
+    )
diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h
index 935ae9453..3ba9bf311 100644
--- a/examples/device/hid_composite_freertos/src/tusb_config.h
+++ b/examples/device/hid_composite_freertos/src/tusb_config.h
@@ -54,7 +54,9 @@
 #endif
 
 // This examples use FreeRTOS
+#ifndef CFG_TUSB_OS
 #define CFG_TUSB_OS           OPT_OS_FREERTOS
+#endif
 
 // Espressif IDF requires "freertos/" prefix in include path
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt
index 3832037a9..a5332d715 100644
--- a/hw/bsp/espressif/boards/CMakeLists.txt
+++ b/hw/bsp/espressif/boards/CMakeLists.txt
@@ -1,14 +1,8 @@
 idf_component_register(SRCS family.c
                     INCLUDE_DIRS "." "${BOARD}"
                     PRIV_REQUIRES "driver"
-                    REQUIRES freertos src led_strip)
+                    REQUIRES led_strip src tinyusb_src)
 
-# Apply board specific content
-include("${BOARD}/board.cmake")
-
-idf_component_get_property(FREERTOS_ORIG_INCLUDE_PATH freertos ORIG_INCLUDE_PATH)
 target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${FREERTOS_ORIG_INCLUDE_PATH}"
   "${TOP}/hw"
-  "${TOP}/src"
 )
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 015d8305b..8fc4a1cc8 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../../board.h"
+#include "bsp/board.h"
 #include "board.h"
 
 #include "esp_rom_gpio.h"
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
index 0bd404cee..9aadda43d 100644
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -19,6 +19,7 @@ endif()
 
 list(APPEND compile_options
     "-DCFG_TUSB_MCU=${tusb_mcu}"
+    "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
     #"-DCFG_TUSB_DEBUG=1"
     )
 
diff --git a/tools/build_family.py b/tools/build_family.py
index ae0bb282d..f9f7261fe 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -42,7 +42,7 @@ if __name__ == '__main__':
     # If examples are not specified in arguments, build all
     all_examples = []
     for dir1 in os.scandir("examples"):
-        if dir1.is_dir():
+        if dir1.is_dir() and 'cmake-build' not in dir1.name:
             for entry in os.scandir(dir1.path):
                 if entry.is_dir():
                     all_examples.append(dir1.name + '/' + entry.name)
@@ -52,7 +52,7 @@ if __name__ == '__main__':
     # If family are not specified in arguments, build all
     all_families = []
     for entry in os.scandir("hw/bsp"):
-        if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name != 'espressif'
+        if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name != 'espressif':
             all_families.append(entry.name)
     filter_with_input(all_families)
     all_families.sort()

From cf7aad790c23dd1adebd0d86ae2338a1cd64aa97 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 30 Mar 2023 11:37:36 +0700
Subject: [PATCH 1625/2085] more esp32 cmake clean up

---
 examples/device/board_test/CMakeLists.txt              |  7 -------
 examples/device/board_test/src/CMakeLists.txt          |  6 +-----
 examples/device/cdc_msc_freertos/CMakeLists.txt        |  5 -----
 examples/device/cdc_msc_freertos/src/CMakeLists.txt    |  6 +-----
 examples/device/hid_composite_freertos/CMakeLists.txt  |  5 -----
 .../device/hid_composite_freertos/src/CMakeLists.txt   |  6 +-----
 hw/bsp/espressif/boards/CMakeLists.txt                 |  8 +++-----
 hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt | 10 ++--------
 hw/bsp/espressif/family.cmake                          |  2 +-
 9 files changed, 9 insertions(+), 46 deletions(-)

diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index b21d56f9e..4435bd523 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -1,12 +1,5 @@
 cmake_minimum_required(VERSION 3.5)
 
-# -DFAMILY=espressif
-if(FAMILY STREQUAL "espressif")
-  # TOP is absolute path to root directory of TinyUSB git repo
-  set(TOP "../../..")
-  get_filename_component(TOP "${TOP}" REALPATH)
-endif()
-
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
diff --git a/examples/device/board_test/src/CMakeLists.txt b/examples/device/board_test/src/CMakeLists.txt
index 03f4c7505..8d85dcafd 100644
--- a/examples/device/board_test/src/CMakeLists.txt
+++ b/examples/device/board_test/src/CMakeLists.txt
@@ -1,7 +1,3 @@
 idf_component_register(SRCS "main.c"
                     INCLUDE_DIRS "."
-                    REQUIRES freertos soc tinyusb_src)
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-    "${TOP}/hw"
-    )
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 573924b18..714e5333b 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -1,10 +1,5 @@
 cmake_minimum_required(VERSION 3.5)
 
-# TOP is absolute path to root directory of TinyUSB git repo
-# needed for esp32sx build. TODO could be removed later on
-set(TOP "../../..")
-get_filename_component(TOP "${TOP}" REALPATH)
-
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index 9c597b302..b77a68c8d 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -1,7 +1,3 @@
 idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c"
                     INCLUDE_DIRS "."
-                    REQUIRES freertos soc tinyusb_src)
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/hw"
-)
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt
index 573924b18..714e5333b 100644
--- a/examples/device/hid_composite_freertos/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/CMakeLists.txt
@@ -1,10 +1,5 @@
 cmake_minimum_required(VERSION 3.5)
 
-# TOP is absolute path to root directory of TinyUSB git repo
-# needed for esp32sx build. TODO could be removed later on
-set(TOP "../../..")
-get_filename_component(TOP "${TOP}" REALPATH)
-
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
diff --git a/examples/device/hid_composite_freertos/src/CMakeLists.txt b/examples/device/hid_composite_freertos/src/CMakeLists.txt
index 1e1e465e0..6d912854f 100644
--- a/examples/device/hid_composite_freertos/src/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/src/CMakeLists.txt
@@ -1,7 +1,3 @@
 idf_component_register(SRCS "main.c" "usb_descriptors.c"
                     INCLUDE_DIRS "."
-                    REQUIRES freertos soc tinyusb_src)
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-    "${TOP}/hw"
-    )
+                    REQUIRES boards tinyusb_src)
diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt
index a5332d715..325263c1d 100644
--- a/hw/bsp/espressif/boards/CMakeLists.txt
+++ b/hw/bsp/espressif/boards/CMakeLists.txt
@@ -1,8 +1,6 @@
+set(hw_dir "${CMAKE_CURRENT_LIST_DIR}/../../../")
+
 idf_component_register(SRCS family.c
-                    INCLUDE_DIRS "." "${BOARD}"
+                    INCLUDE_DIRS "." ${BOARD} ${hw_dir}
                     PRIV_REQUIRES "driver"
                     REQUIRES led_strip src tinyusb_src)
-
-target_include_directories(${COMPONENT_TARGET} PUBLIC
-  "${TOP}/hw"
-)
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
index 9aadda43d..5e0ed9ac7 100644
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -2,9 +2,8 @@ idf_build_get_property(target IDF_TARGET)
 
 set(srcs)
 set(includes_public)
-set(includes_private)
 set(compile_options)
-set(tusb_src "${TOP}/src")
+set(tusb_src "${CMAKE_CURRENT_SOURCE_DIR}/../../../../../src")
 
 if(target STREQUAL "esp32s3")
   set(tusb_mcu "OPT_MCU_ESP32S3")
@@ -25,10 +24,6 @@ list(APPEND compile_options
 
 idf_component_get_property(freertos_component_dir freertos COMPONENT_DIR)
 
-list(APPEND includes_private
-    "${tusb_src}"
-    )
-
 list(APPEND includes_public
     "${tusb_src}"
     # The FreeRTOS API include convention in tinyusb is different from esp-idf
@@ -54,8 +49,7 @@ list(APPEND srcs
 
 idf_component_register(SRCS ${srcs}
     INCLUDE_DIRS ${includes_public}
-    PRIV_INCLUDE_DIRS ${includes_private}
-    PRIV_REQUIRES src
+    REQUIRES src
     )
 
 target_compile_options(${COMPONENT_LIB} PUBLIC ${compile_options})
diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake
index 19b9139c3..954dc635b 100644
--- a/hw/bsp/espressif/family.cmake
+++ b/hw/bsp/espressif/family.cmake
@@ -1,6 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
-# Apply board specific content
+# Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
 include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
 
 # Add example src and bsp directories

From d7d4e7b527357d0d4eac63e1c7c26548de5177e3 Mon Sep 17 00:00:00 2001
From: epatstarkey <ep.atstarkey@gmail.com>
Date: Thu, 30 Mar 2023 11:34:39 -0500
Subject: [PATCH 1626/2085] Update samples

---
 examples/device/webusb_serial/src/main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index 838d86381..eaca78c73 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -112,7 +112,7 @@ void echo_all(uint8_t buf[], uint32_t count)
   if ( web_serial_connected )
   {
     tud_vendor_write(buf, count);
-    tud_vendor_flush();
+    tud_vendor_write_flush();
   }
 
   // echo to cdc
@@ -211,7 +211,7 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ
           blink_interval_ms = BLINK_ALWAYS_ON;
 
           tud_vendor_write_str("\r\nWebUSB interface connected\r\n");
-          tud_vendor_flush();
+          tud_vendor_write_flush();
         }else
         {
           blink_interval_ms = BLINK_MOUNTED;

From 1372d4e4d55ee0ff63e07e75aa873c3df3f9e108 Mon Sep 17 00:00:00 2001
From: epatstarkey <ep.atstarkey@gmail.com>
Date: Fri, 31 Mar 2023 12:58:51 -0500
Subject: [PATCH 1627/2085] Remove trailing whitespace

---
 src/class/vendor/vendor_device.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index ca4837d7b..7afd49cc1 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)

From 160e2a8aeb2b2ed67f2abb6231b4efd2e0792077 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Apr 2023 11:07:48 +0700
Subject: [PATCH 1628/2085] skip .idea

---
 .gitignore | 1 -
 1 file changed, 1 deletion(-)

diff --git a/.gitignore b/.gitignore
index 268decfc6..8f5bb6efd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -12,7 +12,6 @@ latex
 *.ind
 .env
 .settings/
-.idea/
 .vscode/
 .gdb_history
 /examples/*/*/build*

From 1911c613c7f66d13bf22a1252144cadae1264533 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Apr 2023 11:33:53 +0700
Subject: [PATCH 1629/2085] add some .idea configuration

---
 .idea/.gitignore                             |  8 +++
 .idea/cmake.xml                              | 28 +++++++++
 .idea/runConfigurations/cdc_msc.xml          | 10 +++
 .idea/runConfigurations/hid_composite.xml    | 10 +++
 .idea/runConfigurations/msc_dual_lun.xml     | 10 +++
 .idea/runConfigurations/tinyusb_examples.xml |  5 ++
 .idea/vcs.xml                                | 65 ++++++++++++++++++++
 .pre-commit-config.yaml                      |  1 +
 8 files changed, 137 insertions(+)
 create mode 100644 .idea/.gitignore
 create mode 100644 .idea/cmake.xml
 create mode 100644 .idea/runConfigurations/cdc_msc.xml
 create mode 100644 .idea/runConfigurations/hid_composite.xml
 create mode 100644 .idea/runConfigurations/msc_dual_lun.xml
 create mode 100644 .idea/runConfigurations/tinyusb_examples.xml
 create mode 100644 .idea/vcs.xml

diff --git a/.idea/.gitignore b/.idea/.gitignore
new file mode 100644
index 000000000..73f69e095
--- /dev/null
+++ b/.idea/.gitignore
@@ -0,0 +1,8 @@
+# Default ignored files
+/shelf/
+/workspace.xml
+# Datasource local storage ignored files
+/dataSources/
+/dataSources.local.xml
+# Editor-based HTTP Client requests
+/httpRequests/
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
new file mode 100644
index 000000000..291da5371
--- /dev/null
+++ b/.idea/cmake.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="CMakeSharedSettings">
+    <configurations>
+      <configuration PROFILE_NAME="esp32s3" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_s3_devkitm -DIDF_TARGET=esp32s3">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+            <env name="ESPPORT" value="/dev/ttyUSB0" />
+            <env name="IDF_PATH" value="$PROJECT_DIR$/../esp-idf" />
+            <env name="PATH" value="$PROJECT_DIR$/../esp-idf/components/esptool_py/esptool:/home/hathach/code/esp-idf/components/espcoredump:/home/hathach/code/esp-idf/components/partition_table:/home/hathach/code/esp-idf/components/app_update:/home/hathach/.espressif/tools/xtensa-esp-elf-gdb/11.2_20220823/xtensa-esp-elf-gdb/bin:/home/hathach/.espressif/tools/riscv32-esp-elf-gdb/11.2_20220823/riscv32-esp-elf-gdb/bin:/home/hathach/.espressif/tools/xtensa-esp32-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s2-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s2-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s3-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s3-elf/bin:/home/hathach/.espressif/tools/riscv32-esp-elf/esp-2021r2-patch5-8.4.0/riscv32-esp-elf/bin:/home/hathach/.espressif/tools/esp32ulp-elf/2.35_20220830/esp32ulp-elf/bin:/home/hathach/.espressif/tools/openocd-esp32/v0.11.0-esp32-20221026/openocd-esp32/bin:/home/hathach/.espressif/python_env/idf4.4_py3.10_env/bin:/home/hathach/code/esp-idf/tools:/home/hathach/app/riscv-openocd-wch/src:/home/hathach/app/arm-gnu-toolchain-12.2.rel1-x86_64-arm-none-eabi/bin:/home/hathach/.local/bin:/home/hathach/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/opt/SEGGER/JLink:/home/hathach/app/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/10.2.0-1.2.1/.content/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/openocd/*/.content/bin:/home/hathach/ti/msp430-gcc/bin:/home/hathach/ti/MSPFlasher_1.3.20:/home/hathach/ti/uniflash_7.0.0:/home/hathach/app/gcc_8.3.0.202102_gnurx-elf/bin:/home/hathach/app/RFP_CLI_Linux_V31101_x64/linux-x64:/home/hathach/app/fomu-toolchain-linux_x86_64-v1.5.5/bin:/home/hathach/app/nuclei_riscv_newlibc_prebuilt_linux64_2020.08/gcc/bin:/home/hathach/app/riscv32-embecosm-ubuntu2004-gcc11.1.0/bin:/home/hathach/app/cov-analysis-linux64-2019.03/bin:/opt/iarsystems/bxarm/arm/bin:/home/hathach/.local/bin" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+            <env name="ESPPORT" value="/dev/ttyUSB0" />
+            <env name="IDF_PATH" value="$PROJECT_DIR$/../esp-idf" />
+            <env name="PATH" value="$PROJECT_DIR$/../esp-idf/components/esptool_py/esptool:/home/hathach/code/esp-idf/components/espcoredump:/home/hathach/code/esp-idf/components/partition_table:/home/hathach/code/esp-idf/components/app_update:/home/hathach/.espressif/tools/xtensa-esp-elf-gdb/11.2_20220823/xtensa-esp-elf-gdb/bin:/home/hathach/.espressif/tools/riscv32-esp-elf-gdb/11.2_20220823/riscv32-esp-elf-gdb/bin:/home/hathach/.espressif/tools/xtensa-esp32-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s2-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s2-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s3-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s3-elf/bin:/home/hathach/.espressif/tools/riscv32-esp-elf/esp-2021r2-patch5-8.4.0/riscv32-esp-elf/bin:/home/hathach/.espressif/tools/esp32ulp-elf/2.35_20220830/esp32ulp-elf/bin:/home/hathach/.espressif/tools/openocd-esp32/v0.11.0-esp32-20221026/openocd-esp32/bin:/home/hathach/.espressif/python_env/idf4.4_py3.10_env/bin:/home/hathach/code/esp-idf/tools:/home/hathach/app/riscv-openocd-wch/src:/home/hathach/app/arm-gnu-toolchain-12.2.rel1-x86_64-arm-none-eabi/bin:/home/hathach/.local/bin:/home/hathach/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/opt/SEGGER/JLink:/home/hathach/app/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/10.2.0-1.2.1/.content/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/openocd/*/.content/bin:/home/hathach/ti/msp430-gcc/bin:/home/hathach/ti/MSPFlasher_1.3.20:/home/hathach/ti/uniflash_7.0.0:/home/hathach/app/gcc_8.3.0.202102_gnurx-elf/bin:/home/hathach/app/RFP_CLI_Linux_V31101_x64/linux-x64:/home/hathach/app/fomu-toolchain-linux_x86_64-v1.5.5/bin:/home/hathach/app/nuclei_riscv_newlibc_prebuilt_linux64_2020.08/gcc/bin:/home/hathach/app/riscv32-embecosm-ubuntu2004-gcc11.1.0/bin:/home/hathach/app/cov-analysis-linux64-2019.03/bin:/opt/iarsystems/bxarm/arm/bin:/home/hathach/.local/bin" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="rp2040" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=rp2040 -DBOARD=raspberry_pi_pico" />
+    </configurations>
+  </component>
+</project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/cdc_msc.xml b/.idea/runConfigurations/cdc_msc.xml
new file mode 100644
index 000000000..fbeb4ae05
--- /dev/null
+++ b/.idea/runConfigurations/cdc_msc.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="cdc_msc" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
+      <debugger kind="GDB" isBundled="true" />
+    </openocd>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/hid_composite.xml b/.idea/runConfigurations/hid_composite.xml
new file mode 100644
index 000000000..b9f1d1a72
--- /dev/null
+++ b/.idea/runConfigurations/hid_composite.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="hid_composite" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="hid_composite" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="hid_composite">
+    <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
+      <debugger kind="GDB" isBundled="true" />
+    </openocd>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/msc_dual_lun.xml b/.idea/runConfigurations/msc_dual_lun.xml
new file mode 100644
index 000000000..6e0d74f5b
--- /dev/null
+++ b/.idea/runConfigurations/msc_dual_lun.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="msc_dual_lun" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="msc_dual_lun" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="msc_dual_lun">
+    <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
+      <debugger kind="GDB" isBundled="true" />
+    </openocd>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/tinyusb_examples.xml b/.idea/runConfigurations/tinyusb_examples.xml
new file mode 100644
index 000000000..60e586bbc
--- /dev/null
+++ b/.idea/runConfigurations/tinyusb_examples.xml
@@ -0,0 +1,5 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="tinyusb_examples" type="CMakeListConfigurationType" factoryName="CMakeListConfigurationFactory">
+    <method v="2" />
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/vcs.xml b/.idea/vcs.xml
new file mode 100644
index 000000000..f05d025e7
--- /dev/null
+++ b/.idea/vcs.xml
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="VcsDirectoryMappings">
+    <mapping directory="$PROJECT_DIR$/../pico/pico-sdk" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/allwinner" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/bridgetek/ft9xx/ft90x-sdk" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/broadcom" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/gd/nuclei-sdk" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/infineon/mtb-xmclib-cat3" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/microchip" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/mindmotion/mm32sdk" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/nordic/nrfx" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/nuvoton" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/nxp/lpcopen" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/nxp/mcux-sdk" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/nxp/nxp_sdk" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/Pico-PIO-USB" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/cyw43-driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/lwip" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/tinyusb" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/renesas/fsp" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/renesas/rx" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/silabs/cmsis-dfp-efm32gg12b" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/sony/cxd56/spresense-exported-sdk" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f0" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f1" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f2" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f3" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f4" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f7" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_g0" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_g4" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_h7" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_l0" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_l1" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_l4" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_l5" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_u5" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_wb" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f0xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f1xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f2xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f3xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f4xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f7xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32g0xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32g4xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32h7xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32l0xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32l1xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32l4xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32l5xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32u5xx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32wbxx_hal_driver" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/ti" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/wch/ch32v307" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/lib/CMSIS_5" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/lib/FreeRTOS-Kernel" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/lib/lwip" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/lib/sct_neopixel" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/tools/uf2" vcs="Git" />
+  </component>
+</project>
\ No newline at end of file
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index d37c27d40..6fb98afb8 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -9,6 +9,7 @@ repos:
   - id: check-yaml
   - id: trailing-whitespace
   - id: end-of-file-fixer
+    exclude: ^.idea/
   - id: forbid-submodules
 
 - repo: https://github.com/codespell-project/codespell

From f2faf72f7fe6bf04870c65437088ae76a9db8baf Mon Sep 17 00:00:00 2001
From: raiden00pl <raiden00@railab.me>
Date: Sat, 1 Apr 2023 21:22:33 +0200
Subject: [PATCH 1630/2085] openh743i: initialize USB3300 reset pin

---
 hw/bsp/stm32h7/boards/waveshare_openh743i/board.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
index cf6ad762e..a3d0d07f9 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h
@@ -192,6 +192,14 @@ static inline void board_stm32h7_post_init(void)
   // Init timer
   TIM_HandleTypeDef tim2Handle;
   TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  GPIO_InitTypeDef  GPIO_InitStruct;
+
+  // ULPI_RST
+  GPIO_InitStruct.Pin   = ULPI_RST_PIN;
+  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull  = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = 0;
+  HAL_GPIO_Init(ULPI_RST_PORT, &GPIO_InitStruct);
 
   __HAL_RCC_TIM2_CLK_ENABLE();
 

From 5ef260d5fceeef49c8d1eb08fe39a12712b1ae53 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Apr 2023 17:44:05 +0700
Subject: [PATCH 1631/2085] fix build for esp32

---
 .github/workflows/build_esp.yml                            | 2 +-
 examples/CMakeLists.txt                                    | 1 +
 .../espressif/boards/adafruit_feather_esp32s2/board.cmake  | 1 -
 hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake | 1 -
 hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake | 1 -
 hw/bsp/espressif/boards/espressif_addax_1/board.cmake      | 1 -
 hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake     | 1 -
 hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake   | 1 -
 hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake   | 1 -
 hw/bsp/espressif/boards/espressif_saola_1/board.cmake      | 1 -
 hw/bsp/espressif/family.cmake                              | 6 ++++++
 tools/{build_esp32sx.py => build_esp32.py}                 | 0
 tools/build_utils.py                                       | 7 +++++++
 13 files changed, 15 insertions(+), 9 deletions(-)
 rename tools/{build_esp32sx.py => build_esp32.py} (100%)

diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index dbc51a60f..0a6815ea2 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -54,7 +54,7 @@ jobs:
          path: linkermap
 
     - name: Build
-      run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32sx.py ${{ matrix.board }}
+      run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32.py ${{ matrix.board }}
 
     - name: Linker Map
       run: |
diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt
index 8f5626fa9..d91d8ca62 100644
--- a/examples/CMakeLists.txt
+++ b/examples/CMakeLists.txt
@@ -1,5 +1,6 @@
 cmake_minimum_required(VERSION 3.5)
 
+#set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 include(${CMAKE_CURRENT_SOURCE_DIR}/../hw/bsp/family_support.cmake)
 
 project(tinyusb_examples)
diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
index fcd2f6e9f..abbdf7abc 100644
--- a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
+++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake
@@ -1,3 +1,2 @@
 # Apply board specific content here
 set(IDF_TARGET "esp32s2")
-set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake
index fcd2f6e9f..abbdf7abc 100644
--- a/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake
+++ b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.cmake
@@ -1,3 +1,2 @@
 # Apply board specific content here
 set(IDF_TARGET "esp32s2")
-set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
index fcd2f6e9f..abbdf7abc 100644
--- a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
+++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake
@@ -1,3 +1,2 @@
 # Apply board specific content here
 set(IDF_TARGET "esp32s2")
-set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/espressif/boards/espressif_addax_1/board.cmake b/hw/bsp/espressif/boards/espressif_addax_1/board.cmake
index bc528e9fa..9bac46d64 100644
--- a/hw/bsp/espressif/boards/espressif_addax_1/board.cmake
+++ b/hw/bsp/espressif/boards/espressif_addax_1/board.cmake
@@ -1,3 +1,2 @@
 # Apply board specific content here
 set(IDF_TARGET "esp32s3")
-set(FAMILY_MCUS ESP32S3)
diff --git a/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake b/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake
index fcd2f6e9f..abbdf7abc 100644
--- a/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake
+++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.cmake
@@ -1,3 +1,2 @@
 # Apply board specific content here
 set(IDF_TARGET "esp32s2")
-set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake
index bc528e9fa..9bac46d64 100644
--- a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.cmake
@@ -1,3 +1,2 @@
 # Apply board specific content here
 set(IDF_TARGET "esp32s3")
-set(FAMILY_MCUS ESP32S3)
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake
index bc528e9fa..9bac46d64 100644
--- a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.cmake
@@ -1,3 +1,2 @@
 # Apply board specific content here
 set(IDF_TARGET "esp32s3")
-set(FAMILY_MCUS ESP32S3)
diff --git a/hw/bsp/espressif/boards/espressif_saola_1/board.cmake b/hw/bsp/espressif/boards/espressif_saola_1/board.cmake
index fcd2f6e9f..abbdf7abc 100644
--- a/hw/bsp/espressif/boards/espressif_saola_1/board.cmake
+++ b/hw/bsp/espressif/boards/espressif_saola_1/board.cmake
@@ -1,3 +1,2 @@
 # Apply board specific content here
 set(IDF_TARGET "esp32s2")
-set(FAMILY_MCUS ESP32S2)
diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake
index 954dc635b..92a9bcb04 100644
--- a/hw/bsp/espressif/family.cmake
+++ b/hw/bsp/espressif/family.cmake
@@ -3,6 +3,12 @@ cmake_minimum_required(VERSION 3.5)
 # Apply board specific content i.e IDF_TARGET must be set before project.cmake is included
 include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake")
 
+if(IDF_TARGET STREQUAL "esp32s2")
+  set(FAMILY_MCUS ESP32S2)
+elseif(IDF_TARGET STREQUAL "esp32s3")
+  set(FAMILY_MCUS ESP32S3)
+endif()
+
 # Add example src and bsp directories
 set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components")
 
diff --git a/tools/build_esp32sx.py b/tools/build_esp32.py
similarity index 100%
rename from tools/build_esp32sx.py
rename to tools/build_esp32.py
diff --git a/tools/build_utils.py b/tools/build_utils.py
index 905d06a86..ec850e732 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -53,6 +53,13 @@ def skip_example(example, board):
             token = token.strip("\"")
             _, opt_mcu = token.split("=")
             mcu = opt_mcu[len("OPT_MCU_"):]
+            break
+        if "esp32s2" in token:
+            mcu = "ESP32S2"
+            break
+        if "esp32s3" in token:
+            mcu = "ESP32S3"
+            break
 
     # Skip all OPT_MCU_NONE these are WIP port
     if mcu == "NONE":

From 4f96a1f3b2f4dd265214594450277e4851680258 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Apr 2023 18:05:22 +0700
Subject: [PATCH 1632/2085] more fix

---
 hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
index 5e0ed9ac7..bf8e45be2 100644
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -27,7 +27,7 @@ idf_component_get_property(freertos_component_dir freertos COMPONENT_DIR)
 list(APPEND includes_public
     "${tusb_src}"
     # The FreeRTOS API include convention in tinyusb is different from esp-idf
-    "${freertos_component_dir}/include/freertos"
+    #"${freertos_component_dir}/include/freertos"
     )
 
 list(APPEND srcs

From 718bcdb8bc3b9b522e9bad12ace2c7b62589cb4c Mon Sep 17 00:00:00 2001
From: John Cronin <jncronin@tysos.org>
Date: Mon, 3 Apr 2023 13:56:16 +0100
Subject: [PATCH 1633/2085] Add STM32L5 support - no OTG similar to some L4s

---
 src/common/tusb_mcu.h                                | 6 ++++++
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c        | 6 ++++++
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 8 ++++++++
 src/tusb_option.h                                    | 1 +
 4 files changed, 21 insertions(+)

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index b903abeca..ba8976a8c 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -229,6 +229,12 @@
   #define TUP_USBIP_DWC2_STM32
   #define TUP_DCD_ENDPOINT_MAX    6
 
+#elif TU_CHECK_MCU(OPT_MCU_STM32L5)
+  #define TUP_USBIP_FSDEV
+  #define TUP_USBIP_FSDEV_STM32
+  #define TUP_DCD_ENDPOINT_MAX    8
+
+
 //--------------------------------------------------------------------+
 // Sony
 //--------------------------------------------------------------------+
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 1677cfa12..98d3d0829 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -362,6 +362,9 @@ void dcd_int_enable (uint8_t rhport)
   NVIC_EnableIRQ(USB_HP_IRQn);
   NVIC_EnableIRQ(USB_LP_IRQn);
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
+  NVIC_EnableIRQ(USB_FS_IRQn);
+
 #else
   #error Unknown arch in USB driver
 #endif
@@ -409,6 +412,9 @@ void dcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USB_HP_IRQn);
   NVIC_DisableIRQ(USB_LP_IRQn);
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
+  NVIC_DisableIRQ(USB_FS_IRQn);
+
 #else
   #error Unknown arch in USB driver
 #endif
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 015b177cf..e3fc8aeb5 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -93,6 +93,14 @@
   #include "stm32l4xx.h"
   #define PMA_LENGTH (1024u)
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32L5
+  #include "stm32l5xx.h"
+  #define PMA_LENGTH (1024u)
+
+  #ifndef USB_PMAADDR
+    #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS))
+  #endif
+
 #else
   #error You are using an untested or unimplemented STM32 variant. Please update the driver.
   // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
diff --git a/src/tusb_option.h b/src/tusb_option.h
index f8ac722f4..44d036ea4 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -82,6 +82,7 @@
 #define OPT_MCU_STM32G4           311 ///< ST G4
 #define OPT_MCU_STM32WB           312 ///< ST WB
 #define OPT_MCU_STM32U5           313 ///< ST U5
+#define OPT_MCU_STM32L5           314 ///< ST L5
 
 // Sony
 #define OPT_MCU_CXD56             400 ///< SONY CXD56

From 44fab77c3df784fd6ac94ff75aaa19f70e7760f4 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Tue, 4 Apr 2023 11:02:20 +0700
Subject: [PATCH 1634/2085] Update bug_report.yml

---
 .github/ISSUE_TEMPLATE/bug_report.yml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml
index dc5f0ee16..d00ee78bd 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.yml
+++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -60,15 +60,15 @@ body:
 
   - type: textarea
     attributes:
-      label: Debug Log as txt file
+      label: Debug Log as txt file (LOG/CFG_TUSB_DEBUG=2)
       placeholder: |
         Attach your debug log txt file here, where the issue occurred, best with comments to explain the actual events.
 
         Note1: Please DO NOT paste your lengthy log contents here since it hurts the readability.
-        Note2: To enable logging, add `LOG=3` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=3` in your tusb_config.h.
+        Note2: To enable logging, add `LOG=2` to to the make command if building with stock examples or set `CFG_TUSB_DEBUG=2` in your tusb_config.h.
         More information can be found at [example's readme](https://github.com/hathach/tinyusb/blob/master/docs/getting_started.md)
     validations:
-      required: false
+      required: true
 
   - type: textarea
     attributes:

From 106084289dec0146c117fad69925696b388509be Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 6 Apr 2023 11:15:57 +0700
Subject: [PATCH 1635/2085] add define for vendor_flush() to write_flush() for
 backward compatible

---
 src/class/vendor/vendor_device.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/class/vendor/vendor_device.h b/src/class/vendor/vendor_device.h
index 7afd49cc1..d239406b4 100644
--- a/src/class/vendor/vendor_device.h
+++ b/src/class/vendor/vendor_device.h
@@ -52,7 +52,9 @@ uint32_t tud_vendor_n_write_flush     (uint8_t itf);
 uint32_t tud_vendor_n_write_available (uint8_t itf);
 
 static inline uint32_t tud_vendor_n_write_str (uint8_t itf, char const* str);
-uint32_t tud_vendor_n_flush           (uint8_t itf);
+
+// backward compatible
+#define tud_vendor_n_flush(itf) tud_vendor_n_write_flush(itf)
 
 //--------------------------------------------------------------------+
 // Application API (Single Port)
@@ -67,6 +69,9 @@ static inline uint32_t tud_vendor_write_str       (char const* str);
 static inline uint32_t tud_vendor_write_available (void);
 static inline uint32_t tud_vendor_write_flush     (void);
 
+// backward compatible
+#define tud_vendor_flush() tud_vendor_write_flush()
+
 //--------------------------------------------------------------------+
 // Application Callback API (weak is optional)
 //--------------------------------------------------------------------+

From 6db24e0dbae248c865ec3ed0e5febcf341b489d4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 6 Apr 2023 11:16:28 +0700
Subject: [PATCH 1636/2085] implement tuh_hid_receive_ready() and
 tuh_hid_send_ready()

---
 src/class/hid/hid_host.c | 23 ++++++++++++++++-------
 src/class/hid/hid_host.h |  9 ++++++---
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index a0032aeba..d95d3ef35 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -331,6 +331,15 @@ static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, t
 // Interrupt Endpoint API
 //--------------------------------------------------------------------+
 
+// Check if HID interface is ready to receive report
+bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx)
+{
+  hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx);
+  TU_VERIFY(p_hid);
+
+  return !usbh_edpt_busy(dev_addr, p_hid->ep_in);
+}
+
 bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx)
 {
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
@@ -348,13 +357,13 @@ bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx)
   return true;
 }
 
-//bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t instance)
-//{
-//  TU_VERIFY(tuh_n_hid_n_mounted(dev_addr, instance));
-//
-//  hidh_interface_t* hid_itf = get_instance(dev_addr, instance);
-//  return !usbh_edpt_busy(dev_addr, hid_itf->ep_in);
-//}
+bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx)
+{
+  hidh_interface_t* p_hid = get_hid_itf(dev_addr, idx);
+  TU_VERIFY(p_hid);
+
+  return !usbh_edpt_busy(dev_addr, p_hid->ep_out);
+}
 
 bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len)
 {
diff --git a/src/class/hid/hid_host.h b/src/class/hid/hid_host.h
index c0c727e6a..08ad421d2 100644
--- a/src/class/hid/hid_host.h
+++ b/src/class/hid/hid_host.h
@@ -62,7 +62,7 @@ typedef struct
 // Interface API
 //--------------------------------------------------------------------+
 
-// Get the number of mounted HID interfaces of a device
+// Get the total number of mounted HID interfaces of a device
 uint8_t tuh_hid_itf_get_count(uint8_t dev_addr);
 
 // Get all mounted interfaces across devices
@@ -109,14 +109,17 @@ bool tuh_hid_set_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, uint8_
 // Interrupt Endpoint API
 //--------------------------------------------------------------------+
 
-// Check if the interface is ready to use
-//bool tuh_n_hid_n_ready(uint8_t dev_addr, uint8_t idx);
+// Check if HID interface is ready to receive report
+bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx);
 
 // Try to receive next report on Interrupt Endpoint. Immediately return
 // - true If succeeded, tuh_hid_report_received_cb() callback will be invoked when report is available
 // - false if failed to queue the transfer e.g endpoint is busy
 bool tuh_hid_receive_report(uint8_t dev_addr, uint8_t idx);
 
+// Check if HID interface is ready to send report
+bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx);
+
 // Send report using interrupt endpoint
 // If report_id > 0 (composite), it will be sent as 1st byte, then report contents. Otherwise only report content is sent.
 bool tuh_hid_send_report(uint8_t dev_addr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len);

From 2cda9b60c99894db9a4610f80fc6f974f0499622 Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Thu, 6 Apr 2023 15:45:23 -0700
Subject: [PATCH 1637/2085] Handle iMX RT 1042 usb naming

---
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index 2de0d9cb4..607926a65 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -37,6 +37,11 @@
 #define USB2_BASE USB_OTG2_BASE
 #endif
 
+// RT1040 calls its only USB USB_OTG (no 1)
+#if defined(MIMXRT1042_SERIES)
+#define USB_OTG1_IRQn USB_OTG_IRQn
+#endif
+
 static const ci_hs_controller_t _ci_controller[] =
 {
   // RT1010 and RT1020 only has 1 USB controller

From d4c7c9871ed4e304385aab125116720cb553298d Mon Sep 17 00:00:00 2001
From: tyustli <1225613647@qq.com>
Date: Sat, 8 Apr 2023 18:14:10 +0800
Subject: [PATCH 1638/2085] fix audio comment error

---
 examples/device/audio_4_channel_mic/src/usb_descriptors.c   | 4 ++--
 examples/device/audio_test/src/usb_descriptors.c            | 4 ++--
 examples/device/audio_test_multi_rate/src/usb_descriptors.c | 4 ++--
 examples/device/uac2_headset/src/usb_descriptors.c          | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index 8bf9eebc4..160e4f12f 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -44,7 +44,7 @@ tusb_desc_device_t const desc_device =
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = 0x0200,
 
-    // Use Interface Association Descriptor (IAD) for CDC
+    // Use Interface Association Descriptor (IAD) for Audio
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
     .bDeviceClass       = TUSB_CLASS_MISC,
     .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
@@ -96,7 +96,7 @@ enum
 
 uint8_t const desc_configuration[] =
 {
-  // Interface count, string index, total length, attribute, power in mA
+  // Config number, Interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP Out & EP In address, EP size
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index 891e90802..e9c3aee7a 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -44,7 +44,7 @@ tusb_desc_device_t const desc_device =
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = 0x0200,
 
-    // Use Interface Association Descriptor (IAD) for CDC
+    // Use Interface Association Descriptor (IAD) for Audio
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
     .bDeviceClass       = TUSB_CLASS_MISC,
     .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
@@ -96,7 +96,7 @@ enum
 
 uint8_t const desc_configuration[] =
 {
-    // Interface count, string index, total length, attribute, power in mA
+    // Config number, Interface count, string index, total length, attribute, power in mA
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.c b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
index 276bf8aa0..78c72a6c2 100644
--- a/examples/device/audio_test_multi_rate/src/usb_descriptors.c
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
@@ -46,7 +46,7 @@ tusb_desc_device_t const desc_device =
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = 0x0200,
 
-    // Use Interface Association Descriptor (IAD) for CDC
+    // Use Interface Association Descriptor (IAD) for Audio
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
     .bDeviceClass       = TUSB_CLASS_MISC,
     .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
@@ -98,7 +98,7 @@ enum
 
 uint8_t const desc_configuration[] =
 {
-    // Interface count, string index, total length, attribute, power in mA
+    // Config number, Interface count, string index, total length, attribute, power in mA
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 0a0b4c602..6d6931682 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -46,7 +46,7 @@ tusb_desc_device_t const desc_device =
     .bDescriptorType    = TUSB_DESC_DEVICE,
     .bcdUSB             = 0x0200,
 
-    // Use Interface Association Descriptor (IAD) for CDC
+    // Use Interface Association Descriptor (IAD) for Audio
     // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
     .bDeviceClass       = TUSB_CLASS_MISC,
     .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
@@ -106,7 +106,7 @@ uint8_t const * tud_descriptor_device_cb(void)
 
 uint8_t const desc_configuration[] =
 {
-    // Interface count, string index, total length, attribute, power in mA
+    // Config number, Interface count, string index, total length, attribute, power in mA
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size

From 95dec2ac26fd1b552f2b892f62ec0ed96033e4ba Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sat, 8 Apr 2023 15:39:33 +0200
Subject: [PATCH 1639/2085] Fix case.

---
 examples/device/audio_4_channel_mic/src/usb_descriptors.c   | 2 +-
 examples/device/audio_test/src/usb_descriptors.c            | 2 +-
 examples/device/audio_test_multi_rate/src/usb_descriptors.c | 2 +-
 examples/device/uac2_headset/src/usb_descriptors.c          | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index 160e4f12f..b77da9fac 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -96,7 +96,7 @@ enum
 
 uint8_t const desc_configuration[] =
 {
-  // Config number, Interface count, string index, total length, attribute, power in mA
+  // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
   // Interface number, string index, EP Out & EP In address, EP size
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index e9c3aee7a..cc364ee88 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -96,7 +96,7 @@ enum
 
 uint8_t const desc_configuration[] =
 {
-    // Config number, Interface count, string index, total length, attribute, power in mA
+    // Config number, interface count, string index, total length, attribute, power in mA
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.c b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
index 78c72a6c2..2c72edb17 100644
--- a/examples/device/audio_test_multi_rate/src/usb_descriptors.c
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
@@ -98,7 +98,7 @@ enum
 
 uint8_t const desc_configuration[] =
 {
-    // Config number, Interface count, string index, total length, attribute, power in mA
+    // Config number, interface count, string index, total length, attribute, power in mA
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 6d6931682..682774b72 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -106,7 +106,7 @@ uint8_t const * tud_descriptor_device_cb(void)
 
 uint8_t const desc_configuration[] =
 {
-    // Config number, Interface count, string index, total length, attribute, power in mA
+    // Config number, interface count, string index, total length, attribute, power in mA
     TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
     // Interface number, string index, EP Out & EP In address, EP size

From 16ed10a6e4b42b5bcfa0de9868f5bbe83401a099 Mon Sep 17 00:00:00 2001
From: Devin Auclair <devinauclair@gmail.com>
Date: Fri, 14 Apr 2023 12:48:59 +0000
Subject: [PATCH 1640/2085] Fix spelling configuraiton->configuration

---
 examples/device/dynamic_configuration/src/usb_descriptors.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index 0590bd679..71348abef 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -183,7 +183,7 @@ uint8_t const desc_configuration_0[] =
 };
 
 
-uint8_t const desc_configuraiton_1[] =
+uint8_t const desc_configuration_1[] =
 {
   // Config number, interface count, string index, total length, attribute, power in mA
   TUD_CONFIG_DESCRIPTOR(1, ITF_1_NUM_TOTAL, 0, CONFIG_1_TOTAL_LEN, 0x00, 100),
@@ -199,7 +199,7 @@ uint8_t const desc_configuraiton_1[] =
 uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 {
   (void) index; // for multiple configurations
-  return mode ? desc_configuraiton_1 : desc_configuration_0;
+  return mode ? desc_configuration_1 : desc_configuration_0;
 }
 
 //--------------------------------------------------------------------+

From 152a22f3eef3e3c6977a99df1aae26eb3095c9f1 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 14 Apr 2023 16:05:56 +0200
Subject: [PATCH 1641/2085] Update lib & template.

---
 tools/get_deps.py       | 4 ++--
 tools/iar_template.ipcf | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index 4b81d1468..dfe00b32a 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -37,7 +37,7 @@ deps_optional = {
     'hw/mcu/st/cmsis_device_f3'                : ['5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b', 'https://github.com/STMicroelectronics/cmsis_device_f3.git'     ],
     'hw/mcu/st/cmsis_device_f4'                : ['2615e866fa48fe1ff1af9e31c348813f2b19e7ec', 'https://github.com/STMicroelectronics/cmsis_device_f4.git'     ],
     'hw/mcu/st/cmsis_device_f7'                : ['fc676ef1ad177eb874eaa06444d3d75395fc51f4', 'https://github.com/STMicroelectronics/cmsis_device_f7.git'     ],
-    'hw/mcu/st/cmsis_device_g0'                : ['08258b28ee95f50cb9624d152a1cbf084be1f9a5', 'https://github.com/STMicroelectronics/cmsis_device_g0.git'     ],
+    'hw/mcu/st/cmsis_device_g0'                : ['3a23e1224417f3f2d00300ecd620495e363f2094', 'https://github.com/STMicroelectronics/cmsis_device_g0.git'     ],
     'hw/mcu/st/cmsis_device_g4'                : ['ce822adb1dc552b3aedd13621edbc7fdae124878', 'https://github.com/STMicroelectronics/cmsis_device_g4.git'     ],
     'hw/mcu/st/cmsis_device_h7'                : ['60dc2c913203dc8629dc233d4384dcc41c91e77f', 'https://github.com/STMicroelectronics/cmsis_device_h7.git'     ],
     'hw/mcu/st/cmsis_device_l0'                : ['06748ca1f93827befdb8b794402320d94d02004f', 'https://github.com/STMicroelectronics/cmsis_device_l0.git'     ],
@@ -52,7 +52,7 @@ deps_optional = {
     'hw/mcu/st/stm32f3xx_hal_driver'           : ['1761b6207318ede021706e75aae78f452d72b6fa', 'https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git'],
     'hw/mcu/st/stm32f4xx_hal_driver'           : ['04e99fbdabd00ab8f370f377c66b0a4570365b58', 'https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git'],
     'hw/mcu/st/stm32f7xx_hal_driver'           : ['f7ffdf6bf72110e58b42c632b0a051df5997e4ee', 'https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git'],
-    'hw/mcu/st/stm32g0xx_hal_driver'           : ['5b53e6cee664a82b16c86491aa0060e2110c00cb', 'https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git'],
+    'hw/mcu/st/stm32g0xx_hal_driver'           : ['e911b12c7f67084d7f6b76157a4c0d4e2ec3779c', 'https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git'],
     'hw/mcu/st/stm32g4xx_hal_driver'           : ['8b4518417706d42eef5c14e56a650005abf478a8', 'https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git'],
     'hw/mcu/st/stm32h7xx_hal_driver'           : ['d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04', 'https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git'],
     'hw/mcu/st/stm32l0xx_hal_driver'           : ['fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b', 'https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git'],
diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index d243aab0a..2d262c414 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -57,7 +57,6 @@
 		<group name="src/host">
 			<path>$TUSB_DIR$/src/host/hub.c</path>
 			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
 		</group>
 		<group name="src/portable/synopsys/dwc2">
 			<path>$TUSB_DIR$/src/portable/synopsys/dwc2/dcd_dwc2.c</path>
@@ -120,8 +119,9 @@
 			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
 			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
 		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		<group name="src/portable/renesas/rusb2">
+			<path>$TUSB_DIR$/src/portable/renesas/rusb2/dcd_rusb2.c</path>
+            <path>$TUSB_DIR$/src/portable/renesas/rusb2/hcd_rusb2.c</path>
 		</group>
 		<group name="src/portable/sony/cxd56">
 			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>

From 0ea23904c4deb8641b90f32b668e2f9cdb96c34e Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 14 Apr 2023 16:07:04 +0200
Subject: [PATCH 1642/2085] Add stm32g0b1nucleo BSP.

---
 .../stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld    | 189 ++++++++++
 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h | 116 ++++++
 .../stm32g0/boards/stm32g0b1nucleo/board.mk   |  13 +
 hw/bsp/stm32g0/family.c                       | 189 ++++++++++
 hw/bsp/stm32g0/family.mk                      |  57 +++
 hw/bsp/stm32g0/stm32g0xx_hal_conf.h           | 351 ++++++++++++++++++
 6 files changed, 915 insertions(+)
 create mode 100644 hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld
 create mode 100644 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
 create mode 100644 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk
 create mode 100644 hw/bsp/stm32g0/family.c
 create mode 100644 hw/bsp/stm32g0/family.mk
 create mode 100644 hw/bsp/stm32g0/stm32g0xx_hal_conf.h

diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld
new file mode 100644
index 000000000..842cf1372
--- /dev/null
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+
+**  File        : LinkerScript.ld
+**
+**  Author		: STM32CubeMX
+**
+**  Abstract    : Linker script for STM32G0B1RETx series
+**                512Kbytes FLASH and 144Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed “as is,� without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;      /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 144K
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 512K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
new file mode 100644
index 000000000..3f5bc60b7
--- /dev/null
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
@@ -0,0 +1,116 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ * Copyright (c) 2034, HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// G0B1RE Nucleo does not has usb connection. We need to manually connect
+// - PA12 for D+, CN10.12
+// - PA11 for D-, CN10.14
+
+// LED
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   1
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART2
+#define UART_CLK_EN           __HAL_RCC_USART2_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF1_USART2
+#define UART_TX_PIN           GPIO_PIN_2
+#define UART_RX_PIN           GPIO_PIN_3
+
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_CRSInitTypeDef pInit = {0};
+
+  /** Tick priority is used in HAL_RCC_OscConfig, so we need to enable it now
+  */
+  HAL_InitTick(0);
+  
+  /** Configure the main internal regulator output voltage
+  */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+  /** Enable the SYSCFG APB clock
+  */
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /** Configures CRS
+  */
+  pInit.Prescaler = RCC_CRS_SYNC_DIV1;
+  pInit.Source = RCC_CRS_SYNC_SOURCE_USB;
+  pInit.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+  pInit.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
+  pInit.ErrorLimitValue = 34;
+  pInit.HSI48CalibrationValue = 32;
+
+  HAL_RCCEx_CRSConfig(&pInit);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk
new file mode 100644
index 000000000..50f282b09
--- /dev/null
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk
@@ -0,0 +1,13 @@
+CFLAGS += \
+	-DSTM32G0B1xx
+
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g0b1xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32G0B1RETx_FLASH.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32g0b1xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32g0b1xx_flash.icf
+
+# For flash-jlink target
+JLINK_DEVICE = stm32g0b1re
diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c
new file mode 100644
index 000000000..585398974
--- /dev/null
+++ b/hw/bsp/stm32g0/family.c
@@ -0,0 +1,189 @@
+/* 
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2023 HiFiPhile
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "stm32g0xx_hal.h"
+#include "bsp/board.h"
+#include "board.h"
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_UCPD1_2_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+UART_HandleTypeDef UartHandle;
+
+void board_init(void)
+{
+  board_clock_init();
+
+  // Enable All GPIOs clocks
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+
+  UART_CLK_EN();
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+  // Explicitly disable systick to prevent its ISR runs before scheduler start
+  SysTick->CTRL &= ~1U;
+
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB_UCPD1_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+  GPIO_InitTypeDef  GPIO_InitStruct;
+
+  // LED
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+
+  board_led_write(false);
+
+  // Button
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+
+#ifdef UART_DEV
+  // UART
+  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull      = GPIO_PULLUP;
+  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+
+  UartHandle = (UART_HandleTypeDef){
+    .Instance        = UART_DEV,
+    .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+    .Init.WordLength = UART_WORDLENGTH_8B,
+    .Init.StopBits   = UART_STOPBITS_1,
+    .Init.Parity     = UART_PARITY_NONE,
+    .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+    .Init.Mode       = UART_MODE_TX_RX,
+    .Init.OverSampling = UART_OVERSAMPLING_16,
+    .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT
+  };
+  HAL_UART_Init(&UartHandle);
+#endif
+
+  // USB Pins TODO double check USB clock and pin setup
+  // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* Peripheral clock enable */
+  __HAL_RCC_USB_CLK_ENABLE();
+
+  /* Enable VDDUSB */
+  if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+  {
+    __HAL_RCC_PWR_CLK_ENABLE();
+    HAL_PWREx_EnableVddUSB();
+    __HAL_RCC_PWR_CLK_DISABLE();
+  }
+  else
+  {
+    HAL_PWREx_EnableVddUSB();
+  }
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+  HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
+}
+
+uint32_t board_button_read(void)
+{
+  return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  return len;
+#else
+  (void) buf; (void) len; (void) UartHandle;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS  == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler (void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
+
+void HardFault_Handler (void)
+{
+  __asm("BKPT #0\n");
+}
+
+// Required by __libc_init_array in startup code if we are compiling using
+// -nostdlib/-nostartfiles.
+void _init(void)
+{
+
+}
diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk
new file mode 100644
index 000000000..ac0eee156
--- /dev/null
+++ b/hw/bsp/stm32g0/family.mk
@@ -0,0 +1,57 @@
+ST_FAMILY = g0
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
+ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+# --------------
+# Compiler Flags
+# --------------
+CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_STM32G0
+  
+# GCC Flags
+GCC_CFLAGS += \
+  -flto \
+  -mthumb \
+  -mabi=aapcs \
+  -mcpu=cortex-m0plus \
+  -mfloat-abi=soft \
+  -nostdlib -nostartfiles
+
+# suppress warning caused by vendor mcu driver
+GCC_CFLAGS += -Wno-error=cast-align
+
+# IAR Flags
+IAR_CFLAGS += --cpu cortex-m0
+IAR_ASFLAGS += --cpu cortex-m0
+
+# -----------------
+# Sources & Include
+# -----------------
+
+SRC_C += \
+	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(ST_CMSIS)/Include \
+	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# For freeRTOS port source
+FREERTOS_PORT = ARM_CM0
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32g0/stm32g0xx_hal_conf.h b/hw/bsp/stm32g0/stm32g0xx_hal_conf.h
new file mode 100644
index 000000000..b2e335676
--- /dev/null
+++ b/hw/bsp/stm32g0/stm32g0xx_hal_conf.h
@@ -0,0 +1,351 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018-2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_CONF_H
+#define STM32G0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_EXTI_MODULE_ENABLED   */
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_I2C_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+  * @brief This is the list of modules where register callback can be used
+  */
+#define USE_HAL_ADC_REGISTER_CALLBACKS    0u
+#define USE_HAL_CEC_REGISTER_CALLBACKS    0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS   0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS   0u
+#define USE_HAL_DAC_REGISTER_CALLBACKS    0u
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS  0u
+#define USE_HAL_HCD_REGISTER_CALLBACKS    0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS    0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS    0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS   0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS  0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS    0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS    0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS    0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS  0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS    0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS    0u
+#define USE_HAL_UART_REGISTER_CALLBACKS   0u
+#define USE_HAL_USART_REGISTER_CALLBACKS  0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS   0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    (8000000UL)         /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    (100UL)         /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    (16000000UL)            /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+/**
+  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+  *        This internal oscillator is mainly dedicated to provide a high precision clock to
+  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+  *        which is subject to manufacturing process variations.
+  */
+#if !defined  (HSI48_VALUE)
+  #define HSI48_VALUE   48000000U             /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+                                               The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+#endif
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  (32000UL)                /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations
+in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    (32768UL)               /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    (5000UL)      /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S1 peripheral
+  *        This value is used by the RCC HAL module to compute the I2S1 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_I2S1_CLOCK_VALUE)
+#define EXTERNAL_I2S1_CLOCK_VALUE    (48000UL) /*!< Value of the I2S1 External clock source in Hz*/
+#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
+
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+/**
+  * @brief External clock source for I2S2 peripheral
+  *        This value is used by the RCC HAL module to compute the I2S2 clock source
+  *        frequency.
+  */
+#if !defined  (EXTERNAL_I2S2_CLOCK_VALUE)
+  #define EXTERNAL_I2S2_CLOCK_VALUE    48000U /*!< Value of the I2S2 External clock source in Hz*/
+#endif /* EXTERNAL_I2S2_CLOCK_VALUE */
+#endif
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    (3300UL)                                        /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            0U /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME     1U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include modules header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32g0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32g0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32g0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32g0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32g0xx_hal_adc.h"
+#include "stm32g0xx_hal_adc_ex.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+#include "stm32g0xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32g0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32g0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32g0xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32g0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32g0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32g0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32g0xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32g0xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32g0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32g0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32g0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32g0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32g0xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32g0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32g0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32g0xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32g0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32g0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32g0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32g0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32g0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32g0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32g0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32g0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for functions parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_CONF_H */

From 413b0a7da5b9ef1e519e4087a577bfc6d6681d97 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 14 Apr 2023 17:12:47 +0200
Subject: [PATCH 1643/2085] Use PLL clock.

---
 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h | 38 ++++++++-----------
 hw/bsp/stm32g0/family.c                       | 14 ++-----
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c |  1 +
 3 files changed, 21 insertions(+), 32 deletions(-)

diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
index 3f5bc60b7..60357d1e8 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
@@ -62,7 +62,7 @@ static inline void board_clock_init(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_CRSInitTypeDef pInit = {0};
+  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = { 0 };
 
   /** Tick priority is used in HAL_RCC_OscConfig, so we need to enable it now
   */
@@ -75,38 +75,32 @@ static inline void board_clock_init(void)
   /** Initializes the RCC Oscillators according to the specified parameters
   * in the RCC_OscInitTypeDef structure.
   */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
-  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 12;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
+  /* Select HSI48 as USB clock source */
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
   /** Initializes the CPU, AHB and APB buses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
 
-  /** Enable the SYSCFG APB clock
-  */
-  __HAL_RCC_CRS_CLK_ENABLE();
-
-  /** Configures CRS
-  */
-  pInit.Prescaler = RCC_CRS_SYNC_DIV1;
-  pInit.Source = RCC_CRS_SYNC_SOURCE_USB;
-  pInit.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
-  pInit.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
-  pInit.ErrorLimitValue = 34;
-  pInit.HSI48CalibrationValue = 32;
-
-  HAL_RCCEx_CRSConfig(&pInit);
 }
 
 #ifdef __cplusplus
diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c
index 585398974..be356efe9 100644
--- a/hw/bsp/stm32g0/family.c
+++ b/hw/bsp/stm32g0/family.c
@@ -53,6 +53,9 @@ void board_init(void)
   __HAL_RCC_GPIOD_CLK_ENABLE();
   __HAL_RCC_GPIOE_CLK_ENABLE();
 
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
   UART_CLK_EN();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -119,16 +122,7 @@ void board_init(void)
   __HAL_RCC_USB_CLK_ENABLE();
 
   /* Enable VDDUSB */
-  if(__HAL_RCC_PWR_IS_CLK_DISABLED())
-  {
-    __HAL_RCC_PWR_CLK_ENABLE();
-    HAL_PWREx_EnableVddUSB();
-    __HAL_RCC_PWR_CLK_DISABLE();
-  }
-  else
-  {
-    HAL_PWREx_EnableVddUSB();
-  }
+  HAL_PWREx_EnableVddUSB();
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 36b9133be..23b328b49 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -44,6 +44,7 @@
  * L0x2, L0x3                     1024 byte buffer
  * L1                              512 byte buffer
  * L4x2, L4x3                     1024 byte buffer
+ * G0                             2048 byte buffer
  *
  * To use this driver, you must:
  * - If you are using a device with crystal-less USB, set up the clock recovery system (CRS)

From 71d2ccd78f643886237944729f4bd03876dd108f Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 14 Apr 2023 17:22:25 +0200
Subject: [PATCH 1644/2085] Fix CI

---
 .../boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld      | 10 ++++------
 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h          |  2 +-
 hw/bsp/stm32g0/family.c                                |  2 +-
 hw/bsp/stm32g0/family.mk                               |  2 +-
 4 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld
index 842cf1372..0f3fed096 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/STM32G0B1RETx_FLASH.ld
@@ -134,7 +134,7 @@ SECTIONS
   _sidata = LOADADDR(.data);
 
   /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data : 
+  .data :
   {
     . = ALIGN(4);
     _sdata = .;        /* create a global symbol at data start */
@@ -145,12 +145,12 @@ SECTIONS
     _edata = .;        /* define a global symbol at data end */
   } >RAM AT> FLASH
 
-  
+
   /* Uninitialized data section */
   . = ALIGN(4);
   .bss :
   {
-    /* This is used by the startup in order to initialize the .bss secion */
+    /* This is used by the startup in order to initialize the .bss section */
     _sbss = .;         /* define a global symbol at bss start */
     __bss_start__ = _sbss;
     *(.bss)
@@ -173,7 +173,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-  
+
 
   /* Remove information from the standard libraries */
   /DISCARD/ :
@@ -185,5 +185,3 @@ SECTIONS
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
 }
-
-
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
index 60357d1e8..0d651ea4e 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
@@ -67,7 +67,7 @@ static inline void board_clock_init(void)
   /** Tick priority is used in HAL_RCC_OscConfig, so we need to enable it now
   */
   HAL_InitTick(0);
-  
+
   /** Configure the main internal regulator output voltage
   */
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c
index be356efe9..10023b7e2 100644
--- a/hw/bsp/stm32g0/family.c
+++ b/hw/bsp/stm32g0/family.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * The MIT License (MIT)
  *
  * Copyright (c) 2019 Ha Thach (tinyusb.org)
diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk
index ac0eee156..faf92dca9 100644
--- a/hw/bsp/stm32g0/family.mk
+++ b/hw/bsp/stm32g0/family.mk
@@ -11,7 +11,7 @@ include $(TOP)/$(BOARD_PATH)/board.mk
 # --------------
 CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32G0
-  
+
 # GCC Flags
 GCC_CFLAGS += \
   -flto \

From 2f2c8ce9ec4a567603cbd5e0420fc3dcaffbdfb6 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 14 Apr 2023 17:54:25 +0200
Subject: [PATCH 1645/2085] Fix GCC build.

---
 hw/bsp/board_mcu.h                                   |  3 +++
 hw/bsp/stm32g0/family.mk                             |  2 +-
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c        | 12 ++++++++++--
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 11 +++++++++++
 4 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index cd195a19b..6d40aa0d1 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -101,6 +101,9 @@
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
   #include "stm32u5xx.h"
 
+#elif CFG_TUSB_MCU == OPT_MCU_STM32G0
+  #include "stm32g0xx.h"
+
 #elif CFG_TUSB_MCU == OPT_MCU_CXD56
   // no header needed
 
diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk
index faf92dca9..76f59fc34 100644
--- a/hw/bsp/stm32g0/family.mk
+++ b/hw/bsp/stm32g0/family.mk
@@ -51,7 +51,7 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
 # For freeRTOS port source
-FREERTOS_PORT = ARM_CM0
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 23b328b49..32bab2bed 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -367,7 +367,11 @@ void dcd_int_enable (uint8_t rhport)
   NVIC_EnableIRQ(USBWakeUp_IRQn);
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
-  NVIC_EnableIRQ(USB_UCPD1_2_IRQn);
+  #ifdef STM32G0B0xx
+    NVIC_EnableIRQ(USB_IRQn);
+  #else
+    NVIC_EnableIRQ(USB_UCPD1_2_IRQn);
+  #endif
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   NVIC_EnableIRQ(USB_HP_IRQn);
@@ -420,7 +424,11 @@ void dcd_int_disable(uint8_t rhport)
   NVIC_DisableIRQ(USBWakeUp_IRQn);
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
-  NVIC_DisableIRQ(USB_UCPD1_2_IRQn);
+  #ifdef STM32G0B0xx
+    NVIC_DisableIRQ(USB_IRQn);
+  #else
+    NVIC_DisableIRQ(USB_UCPD1_2_IRQn);
+  #endif
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32WB
   NVIC_DisableIRQ(USB_HP_IRQn);
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index c0f923c8f..32f715e6e 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -184,6 +184,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t pcd_aligned_buffer_size(uint16_t si
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wRegValue)
 {
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   __O uint32_t *reg = (__O uint32_t *)(USB_DRD_BASE + bEpIdx*4);
   *reg = wRegValue;
 #else
@@ -195,6 +196,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, ui
 /* GetENDPOINT */
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpIdx) {
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   __I uint32_t *reg = (__I uint32_t *)(USB_DRD_BASE + bEpIdx*4);
 #else
   __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpIdx*2u);
@@ -249,6 +251,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx,
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   return (pma32[2*bEpIdx] & 0x03FF0000) >> 16;
 #else
   __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
@@ -259,6 +262,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USB
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   return (pma32[2*bEpIdx + 1] & 0x03FF0000) >> 16;
 #else
   __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
@@ -285,6 +289,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_address(USB_TypeDef * USBx,
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   return pma32[2*bEpIdx] & 0x0000FFFFu ;
 #else
   return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u);
@@ -294,6 +299,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_tx_address(USB_TypeDef *
 TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx)
 {
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   return pma32[2*bEpIdx + 1] & 0x0000FFFFu;
 #else
   return *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u);
@@ -303,6 +309,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_ep_rx_address(USB_TypeDef *
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr)
 {
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   pma32[2*bEpIdx] = (pma32[2*bEpIdx] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
 #else
   *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 0u) = addr;
@@ -312,6 +319,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_address(USB_TypeDef * USB
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t addr)
 {
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & 0xFFFF0000u) | (addr & 0x0000FFFCu);
 #else
   *pcd_btable_word_ptr(USBx,(bEpIdx)*4u + 2u) = addr;
@@ -321,6 +329,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_address(USB_TypeDef * USB
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
 {
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   pma32[2*bEpIdx] = (pma32[2*bEpIdx] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
 #else
   __IO uint16_t * reg = pcd_ep_tx_cnt_ptr(USBx, bEpIdx);
@@ -331,6 +340,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, u
 TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpIdx, uint32_t wCount)
 {
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   pma32[2*bEpIdx + 1] = (pma32[2*bEpIdx + 1] & ~0x03FF0000u) | ((wCount & 0x3FFu) << 16);
 #else
   __IO uint16_t * reg = pcd_ep_rx_cnt_ptr(USBx, bEpIdx);
@@ -342,6 +352,7 @@ TU_ATTR_ALWAYS_INLINE static inline void pcd_set_ep_blsize_num_blocks(USB_TypeDe
 {
   /* Encode into register. When BLSIZE==1, we need to subtract 1 block count */
 #ifdef PMA_32BIT_ACCESS
+  (void) USBx;
   pma32[rxtx_idx] = (pma32[rxtx_idx] & 0x0000FFFFu) | (blocksize << 31) | ((numblocks - blocksize) << 26);
 #else
   __IO uint16_t *pdwReg = pcd_btable_word_ptr(USBx, rxtx_idx*2u + 1u);

From 818bda18c23e17c08c689b543d77ecc944681dea Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 14 Apr 2023 23:34:20 +0200
Subject: [PATCH 1646/2085] Fix FIFO transfer and buffer alignment.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 166 +++++++++++++++---
 .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h   |   2 +-
 2 files changed, 142 insertions(+), 26 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index 32bab2bed..b8d04331a 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -186,12 +186,12 @@ static void dcd_ep_ctr_handler(void);
 static uint8_t open_ep_count;
 static uint16_t ep_buf_ptr; ///< Points to first free memory location
 static void dcd_pma_alloc_reset(void);
-static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length);
+static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length);
 static void dcd_pma_free(uint8_t ep_addr);
 static void dcd_ep_free(uint8_t ep_addr);
 static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type);
-static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes);
-static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes);
+static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes);
+static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes);
 
 static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wNBytes);
 static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNBytes);
@@ -792,7 +792,7 @@ static void dcd_pma_alloc_reset(void)
  *
  * During failure, TU_ASSERT is used. If this happens, rework/reallocate memory manually.
  */
-static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
+static uint16_t dcd_pma_alloc(uint8_t ep_addr, uint16_t length)
 {
   xfer_ctl_t* epXferCtl = xfer_ctl_ptr(ep_addr);
 
@@ -804,6 +804,13 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
     return epXferCtl->pma_ptr;
   }
 
+  // Ensure allocated buffer is aligned
+#ifdef PMA_32BIT_ACCESS
+  length = (length + 3) & ~0x03;
+#else
+  length = (length + 1) & ~0x01;
+#endif
+
   open_ep_count++;
 
   uint16_t addr = ep_buf_ptr;
@@ -814,7 +821,7 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length)
 
   epXferCtl->pma_ptr = addr;
   epXferCtl->pma_alloc_size = length;
-  //TU_LOG2("dcd_pma_alloc(%x,%x)=%x\r\n",ep_addr,length,addr);
+  //TU_LOG1("dcd_pma_alloc(%x,%x)=%x\r\n",ep_addr,length,addr);
 
   return addr;
 }
@@ -1240,15 +1247,36 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
 }
 
 #ifdef PMA_32BIT_ACCESS
-static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
+static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes)
 {
-  // FIXME original function uses byte-access to source memory (to support non-aligned buffers)
-  const uint32_t* src32 = (const uint32_t*)(src);
+  const uint8_t* srcVal = src;
   volatile uint32_t* dst32 = (volatile uint32_t*)(USB_PMAADDR + dst);
-  for (unsigned n=wNBytes/4; n>0; --n) {
-    *dst32++ = *src32++;
+
+  for (uint32_t n = wNBytes / 4; n > 0; --n) {
+    *dst32++ = tu_unaligned_read32(srcVal);
+    srcVal += 4;
   }
-  *dst32 = (*src32) & ((1<<8*(wNBytes % 4)) - 1);
+
+  wNBytes = wNBytes & 0x03;
+  if (wNBytes)
+  {
+    uint32_t wrVal = *srcVal;
+    wNBytes--;
+
+    if (wNBytes)
+    {
+      wrVal |= *++srcVal << 8;
+      wNBytes--;
+
+      if (wNBytes)
+      {
+        wrVal |= *++srcVal << 16;
+      }
+    }
+
+    *dst32 = wrVal;
+  }
+
   return true;
 }
 #else
@@ -1263,7 +1291,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
   * @param   wNBytes no. of bytes to be copied.
   * @retval None
   */
-static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
+static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, uint16_t wNBytes)
 {
   uint32_t n = (uint32_t)wNBytes >> 1U;
   uint16_t temp1, temp2;
@@ -1286,7 +1314,7 @@ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
     srcVal++;
   }
 
-  if (wNBytes & 0x01)
+  if (wNBytes)
   {
     temp1 = *srcVal;
     *pdwVal = temp1;
@@ -1313,7 +1341,37 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
 
   // We want to read from the FIFO and write it into the PMA, if LIN part is ODD and has WRAPPED part,
   // last lin byte will be combined with wrapped part
-  // To ensure PMA is always access 16bit aligned (dst aligned to 16 bit)
+  // To ensure PMA is always access aligned (dst aligned to 16 or 32 bit)
+#ifdef PMA_32BIT_ACCESS
+  if((cnt_lin & 0x03) && cnt_wrap)
+  {
+    // Copy first linear part
+    dcd_write_packet_memory(dst, info.ptr_lin, cnt_lin &~0x03);
+    dst += cnt_lin &~0x03;
+
+    // Copy last linear bytes & first wrapped bytes to buffer
+    uint32_t i;
+    uint8_t tmp[4];
+    for (i = 0; i < (cnt_lin & 0x03); i++)
+    {
+      tmp[i] = ((uint8_t*)info.ptr_lin)[(cnt_lin &~0x03) + i];
+    }
+    uint32_t wCnt = cnt_wrap;
+    for (; i < 4 && wCnt > 0; i++, wCnt--)
+    {
+      tmp[i] = *(uint8_t*)info.ptr_wrap;
+      info.ptr_wrap = (uint8_t*)info.ptr_wrap + 1;
+    }
+
+    // Write unaligned buffer
+    dcd_write_packet_memory(dst, &tmp, 4);
+    dst += 4;
+
+    // Copy rest of wrapped byte
+    if (wCnt)
+        dcd_write_packet_memory(dst, info.ptr_wrap, wCnt);
+  }
+#else
   if((cnt_lin & 0x01) && cnt_wrap)
   {
     // Copy first linear part
@@ -1328,6 +1386,7 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
     // Copy rest of wrapped byte
     dcd_write_packet_memory(dst, ((uint8_t*)info.ptr_wrap) + 1, cnt_wrap - 1);
   }
+#endif
   else
   {
     // Copy linear part
@@ -1347,11 +1406,37 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN
 }
 
 #ifdef PMA_32BIT_ACCESS
-static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes)
+static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes)
 {
-    // FIXME this should probably be modified for possible unaligned access?
-    memcpy(dst, (void*)(USB_PMAADDR+src), wNBytes);
-    return true;
+  uint8_t* dstVal = dst;
+  volatile uint32_t* src32 = (volatile uint32_t*)(USB_PMAADDR + src);
+
+  for (uint32_t n = wNBytes / 4; n > 0; --n) {
+    tu_unaligned_write32(dstVal, *src32++);
+    dstVal += 4;
+  }
+
+  wNBytes = wNBytes & 0x03;
+  if (wNBytes)
+  {
+    uint32_t rdVal = *src32;
+
+    *dstVal = tu_u32_byte0(rdVal);
+    wNBytes--;
+
+    if (wNBytes)
+    {
+      *++dstVal = tu_u32_byte1(rdVal);
+      wNBytes--;
+
+      if (wNBytes)
+      {
+        *++dstVal = tu_u32_byte2(rdVal);
+      }
+    }
+  }
+
+  return true;
 }
 #else
 /**
@@ -1360,7 +1445,7 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
   * @param   wNBytes no. of bytes to be copied.
   * @retval None
   */
-static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes)
+static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, uint16_t wNBytes)
 {
   uint32_t n = (uint32_t)wNBytes >> 1U;
   // The GCC optimizer will combine access to 32-bit sizes if we let it. Force
@@ -1405,9 +1490,39 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
   uint16_t cnt_lin =  TU_MIN(wNBytes, info.len_lin);
   uint16_t cnt_wrap = TU_MIN(wNBytes - cnt_lin, info.len_wrap);
 
+
   // We want to read from PMA and write it into the FIFO, if LIN part is ODD and has WRAPPED part,
   // last lin byte will be combined with wrapped part
-  // To ensure PMA is always access 16bit aligned (src aligned to 16 bit)
+  // To ensure PMA is always access aligned (src aligned to 16 or 32 bit)
+#ifdef PMA_32BIT_ACCESS
+  if((cnt_lin & 0x03) && cnt_wrap)
+  {
+    // Copy first linear part
+    dcd_read_packet_memory(info.ptr_lin, src, cnt_lin &~0x03);
+    src += cnt_lin &~0x03;
+
+    // Copy last linear bytes & first wrapped bytes
+    uint8_t tmp[4];
+    dcd_read_packet_memory(tmp, src, 4);
+    src += 4;
+
+    uint32_t i;
+    for (i = 0; i < (cnt_lin & 0x03); i++)
+    {
+      ((uint8_t*)info.ptr_lin)[(cnt_lin &~0x03) + i] = tmp[i];
+    }
+    uint32_t wCnt = cnt_wrap;
+    for (; i < 4 && wCnt > 0; i++, wCnt--)
+    {
+      *(uint8_t*)info.ptr_wrap = tmp[i];
+      info.ptr_wrap = (uint8_t*)info.ptr_wrap + 1;
+    }
+
+    // Copy rest of wrapped byte
+    if (wCnt)
+      dcd_read_packet_memory(info.ptr_wrap, src, wCnt);
+  }
+#else
   if((cnt_lin & 0x01) && cnt_wrap)
   {
     // Copy first linear part
@@ -1415,16 +1530,17 @@ static bool dcd_read_packet_memory_ff(tu_fifo_t * ff, uint16_t src, uint16_t wNB
     src += cnt_lin &~0x01;
 
     // Copy last linear byte & first wrapped byte
-    uint16_t tmp;
-    dcd_read_packet_memory(&tmp, src, 2);
-
-    ((uint8_t*)info.ptr_lin)[cnt_lin - 1] = (uint8_t)tmp;
-    ((uint8_t*)info.ptr_wrap)[0] = (uint8_t)(tmp >> 8U);
+    uint8_t tmp[2];
+    dcd_read_packet_memory(tmp, src, 2);
     src += 2;
 
+    ((uint8_t*)info.ptr_lin)[cnt_lin - 1] = tmp[0];
+    ((uint8_t*)info.ptr_wrap)[0] = tmp[1];
+
     // Copy rest of wrapped byte
     dcd_read_packet_memory(((uint8_t*)info.ptr_wrap) + 1, src, cnt_wrap - 1);
   }
+#endif
   else
   {
     // Copy linear part
diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
index 32f715e6e..e6649de5a 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h
@@ -85,7 +85,7 @@
 #elif CFG_TUSB_MCU == OPT_MCU_STM32G0
   #include "stm32g0xx.h"
   #define PMA_32BIT_ACCESS
-  #define PMA_LENGTH (1024u) // FIXME it is 2048, really
+  #define PMA_LENGTH (2048u)
   #undef USB_PMAADDR
   #define USB_PMAADDR USB_DRD_PMAADDR
   #define USB_TypeDef USB_DRD_TypeDef

From 8c780a9564a05ea0f0e3bf0d929fd5dbe6c4806a Mon Sep 17 00:00:00 2001
From: slc-tl <91279938+slc-tl@users.noreply.github.com>
Date: Fri, 14 Apr 2023 17:07:33 -0600
Subject: [PATCH 1647/2085] Update porting.rst

Adds more in depth documentation of how tud_task does not need to be polled in implementations that use an RTOS / scheduler.
---
 docs/contributing/porting.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/contributing/porting.rst b/docs/contributing/porting.rst
index 710af51c3..9ec392661 100644
--- a/docs/contributing/porting.rst
+++ b/docs/contributing/porting.rst
@@ -69,7 +69,7 @@ The code is almost entirely agnostic of MCU and lives in ``src/osal``.
 Device API
 ^^^^^^^^^^
 
-After the USB device is setup, the USB device code works by processing events on the main thread (by calling ``tud_task``\ ). These events are queued by the USB interrupt handler. So, there are three parts to the device low-level API: device setup, endpoint setup and interrupt processing.
+After the USB device is setup, the USB device code works by processing events on the main thread (by calling ``tud_task``\ ). In RTOS configurations, tud_task blocks behind a synchronization structure when the event queue is empty, so that the scheduler may give the CPU to a different task. To take advantage of the library's capability to yield the CPU when there are no actionable USB device events, ensure that the `CFG_TUSB_OS` symbol is defined in your modified ``tusb_config.h``. For example `#define CFG_TUSB_OS  OPT_OS_FREERTOS` enables the FreeRTOS scheduler to schedule other threads than that which calls `tud_task`. These events are queued by the USB interrupt handler. So, there are three parts to the device low-level API: device setup, endpoint setup and interrupt processing. 
 
 All of the code for the low-level device API is in ``src/portable/<vendor>/<chip family>/dcd_<chip family>.c``.
 

From d97b6d57de0b2586624dec51b37ccd699a0314a6 Mon Sep 17 00:00:00 2001
From: Reimu NotMoe <reimu@sudomaker.com>
Date: Mon, 17 Apr 2023 20:20:22 +0800
Subject: [PATCH 1648/2085] Fix compatibility with the latest Microchip XC16
 compiler

---
 src/common/tusb_compiler.h | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 713bbb8d4..a1794584d 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -138,10 +138,14 @@
   #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
   #define TU_ATTR_BIT_FIELD_ORDER_END
 
-  #if __has_attribute(__fallthrough__)
-    #define TU_ATTR_FALLTHROUGH         __attribute__((fallthrough))
-  #else
+  #if defined(__XC16)
     #define TU_ATTR_FALLTHROUGH         do {} while (0)  /* fallthrough */
+  #else
+    #if __has_attribute(__fallthrough__)
+      #define TU_ATTR_FALLTHROUGH         __attribute__((fallthrough))
+    #else
+      #define TU_ATTR_FALLTHROUGH         do {} while (0)  /* fallthrough */
+    #endif
   #endif
 
   // Endian conversion use well-known host to network (big endian) naming

From fa8f3731c1b2e069dd07d30e86ea4a3af18c34dc Mon Sep 17 00:00:00 2001
From: Reimu NotMoe <reimu@sudomaker.com>
Date: Mon, 17 Apr 2023 21:02:12 +0800
Subject: [PATCH 1649/2085] Implement TU_BSWAP{16,32} correctly for Microchip
 XC16

---
 src/common/tusb_compiler.h | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index a1794584d..dce32e92b 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -155,8 +155,17 @@
     #define TU_BYTE_ORDER TU_BIG_ENDIAN
   #endif
 
-  #define TU_BSWAP16(u16) (__builtin_bswap16(u16))
-  #define TU_BSWAP32(u32) (__builtin_bswap32(u32))
+  // Unfortunately XC16 doesn't provide builtins for 32bit endian conversion
+  #if defined(__XC16)
+    #define TU_BSWAP16(u16) (__builtin_swap(u16))
+    #define TU_BSWAP32(u32) ((((u32) & 0xff000000) >> 24) |  \
+                            (((u32) & 0x00ff0000) >> 8)  |  \
+                            (((u32) & 0x0000ff00) << 8)  |  \
+                            (((u32) & 0x000000ff) << 24))
+  #else
+    #define TU_BSWAP16(u16) (__builtin_bswap16(u16))
+    #define TU_BSWAP32(u32) (__builtin_bswap32(u32))
+  #endif
 
 	#ifndef __ARMCC_VERSION
   // List of obsolete callback function that is renamed and should not be defined.

From 412b557a080526fbfe7b42dd8aa07468c16413cc Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Mon, 17 Apr 2023 15:34:20 +0200
Subject: [PATCH 1650/2085] Cleanup unnecessary code for 16bit access.

---
 src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 39 ++++---------------
 1 file changed, 7 insertions(+), 32 deletions(-)

diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
index b8d04331a..14cabaf8d 100644
--- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -210,17 +210,6 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t ep_addr)
   return &xfer_status[epnum][dir];
 }
 
-// Using a function due to better type checks
-// This seems better than having to do type casts everywhere else
-TU_ATTR_ALWAYS_INLINE static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) {
-  *reg = (uint16_t)(*reg & ~mask);
-}
-
-// Bits in ISTR are cleared upon writing 0
-TU_ATTR_ALWAYS_INLINE static inline void clear_istr_bits(uint32_t mask) {
-  USB->ISTR = ~mask;
-}
-
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
@@ -244,11 +233,7 @@ void dcd_init (uint8_t rhport)
     asm("NOP");
   }
 
-#ifdef PMA_32BIT_ACCESS // CNTR register is 32bits on STM32G0, 16bit on older versions
   USB->CNTR &= ~USB_CNTR_PDWN;
-#else
-  reg16_clear_bits(&USB->CNTR, USB_CNTR_PDWN);// Remove powerdown
-#endif
 
   // Wait startup time, for F042 and F070, this is <= 1 us.
   for(uint32_t i = 0; i<200; i++) // should be a few us
@@ -492,7 +477,6 @@ static void dcd_handle_bus_reset(void)
   //__IO uint16_t * const epreg = &(EPREG(0));
   USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
 
-
   for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
   {
     // Clear all EPREG (or maybe this is automatic? I'm not sure)
@@ -683,13 +667,13 @@ void dcd_int_handler(uint8_t rhport) {
 
   /* Put SOF flag at the beginning of ISR in case to get least amount of jitter if it is used for timing purposes */
   if(int_status & USB_ISTR_SOF) {
-    clear_istr_bits(USB_ISTR_SOF);
+    USB->ISTR &=~USB_ISTR_SOF;
     dcd_event_sof(0, USB->FNR & USB_FNR_FN, true);
   }
 
   if(int_status & USB_ISTR_RESET) {
     // USBRST is start of reset.
-    clear_istr_bits(USB_ISTR_RESET);
+    USB->ISTR &=~USB_ISTR_RESET;
     dcd_handle_bus_reset();
     dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
     return; // Don't do the rest of the things here; perhaps they've been cleared?
@@ -704,14 +688,10 @@ void dcd_int_handler(uint8_t rhport) {
 
   if (int_status & USB_ISTR_WKUP)
   {
-#ifdef PMA_32BIT_ACCESS // CNTR register is 32bits on STM32G0, 16bit on older versions
     USB->CNTR &= ~USB_CNTR_LPMODE;
     USB->CNTR &= ~USB_CNTR_FSUSP;
-#else
-    reg16_clear_bits(&USB->CNTR, USB_CNTR_LPMODE);
-    reg16_clear_bits(&USB->CNTR, USB_CNTR_FSUSP);
-#endif
-    clear_istr_bits(USB_ISTR_WKUP);
+
+    USB->ISTR &=~USB_ISTR_WKUP;
     dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
   }
 
@@ -725,7 +705,7 @@ void dcd_int_handler(uint8_t rhport) {
     USB->CNTR |= USB_CNTR_LPMODE;
 
     /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
-    clear_istr_bits(USB_ISTR_SUSP);
+    USB->ISTR &=~USB_ISTR_SUSP;
     dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
   }
 
@@ -738,7 +718,7 @@ void dcd_int_handler(uint8_t rhport) {
     {
       remoteWakeCountdown--;
     }
-    clear_istr_bits(USB_ISTR_ESOF);
+    USB->ISTR &=~USB_ISTR_ESOF;
   }
 }
 
@@ -759,13 +739,8 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
     uint8_t const dev_addr = (uint8_t) request->wValue;
 
     // Setting new address after the whole request is complete
-#ifdef PMA_32BIT_ACCESS
     USB->DADDR &= ~USB_DADDR_ADD;
-    USB->DADDR = (USB->DADDR & ~USB_DADDR_ADD_Msk) | dev_addr; // leave the enable bit set
-#else
-    reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD);
-    USB->DADDR = (uint16_t)(USB->DADDR | dev_addr); // leave the enable bit set
-#endif
+    USB->DADDR |= dev_addr; // leave the enable bit set
   }
 }
 

From 9002dc706711741b6db2c53de4e5b94b02322f37 Mon Sep 17 00:00:00 2001
From: Reimu NotMoe <reimu@sudomaker.com>
Date: Tue, 18 Apr 2023 17:27:42 +0800
Subject: [PATCH 1651/2085] Use __GNUC__ macro to determine if __has_attribute
 is supported

---
 src/common/tusb_compiler.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index dce32e92b..5ab56e145 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -138,7 +138,7 @@
   #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
   #define TU_ATTR_BIT_FIELD_ORDER_END
 
-  #if defined(__XC16)
+  #if __GNUC__ < 5
     #define TU_ATTR_FALLTHROUGH         do {} while (0)  /* fallthrough */
   #else
     #if __has_attribute(__fallthrough__)

From fab48e5bcc0708077a0efb6f2412b92a6529bc3e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 20 Apr 2023 14:09:38 +0700
Subject: [PATCH 1652/2085] adding cmake build for imxrt1010

---
 .idea/cmake.xml                               |  1 +
 .idea/runConfigurations/msc_dual_lun.xml      |  2 +-
 cmake/cpu/cortex-m7.cmake                     |  6 ++
 cmake/toolchain/arm_gcc.cmake                 | 19 +++++
 cmake/toolchain/set_flags.cmake               | 22 ++++++
 examples/device/board_test/CMakeLists.txt     | 47 +++++++++++--
 examples/device/cdc_msc/CMakeLists.txt        |  2 +-
 .../imxrt/boards/mimxrt1010_evk/board.cmake   | 10 +++
 hw/bsp/imxrt/family.cmake                     | 69 +++++++++++++++++++
 9 files changed, 172 insertions(+), 6 deletions(-)
 create mode 100644 cmake/cpu/cortex-m7.cmake
 create mode 100644 cmake/toolchain/arm_gcc.cmake
 create mode 100644 cmake/toolchain/set_flags.cmake
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
 create mode 100644 hw/bsp/imxrt/family.cmake

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 291da5371..4d9fc9aa5 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -23,6 +23,7 @@
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
       <configuration PROFILE_NAME="rp2040" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=rp2040 -DBOARD=raspberry_pi_pico" />
+      <configuration PROFILE_NAME="rt1010 evk" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1010_evk" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/msc_dual_lun.xml b/.idea/runConfigurations/msc_dual_lun.xml
index 6e0d74f5b..5c1ea270b 100644
--- a/.idea/runConfigurations/msc_dual_lun.xml
+++ b/.idea/runConfigurations/msc_dual_lun.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="msc_dual_lun" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="msc_dual_lun" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="msc_dual_lun">
+  <configuration default="false" name="msc_dual_lun" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="msc_dual_lun" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="msc_dual_lun">
     <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
       <debugger kind="GDB" isBundled="true" />
     </openocd>
diff --git a/cmake/cpu/cortex-m7.cmake b/cmake/cpu/cortex-m7.cmake
new file mode 100644
index 000000000..2b258726f
--- /dev/null
+++ b/cmake/cpu/cortex-m7.cmake
@@ -0,0 +1,6 @@
+set(TOOLCHAIN_COMMON_FLAGS
+  -mthumb
+  -mcpu=cortex-m7
+  -mfloat-abi=hard
+  -mfpu=fpv5-d16
+  )
diff --git a/cmake/toolchain/arm_gcc.cmake b/cmake/toolchain/arm_gcc.cmake
new file mode 100644
index 000000000..44683118e
--- /dev/null
+++ b/cmake/toolchain/arm_gcc.cmake
@@ -0,0 +1,19 @@
+set(CMAKE_SYSTEM_NAME Generic)
+
+set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc")
+set(CMAKE_C_COMPILER "arm-none-eabi-gcc")
+set(CMAKE_CXX_COMPILER "arm-none-eabi-g++")
+set(GCC_ELF2BIN "arm-none-eabi-objcopy")
+set_property(GLOBAL PROPERTY ELF2BIN ${GCC_ELF2BIN})
+
+# Look for includes and libraries only in the target system prefix.
+set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
+
+# pass TOOLCHAIN_CPU to
+set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_SYSTEM_PROCESSOR)
+
+include(${CMAKE_CURRENT_LIST_DIR}/../cpu/${CMAKE_SYSTEM_PROCESSOR}.cmake)
+include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake)
diff --git a/cmake/toolchain/set_flags.cmake b/cmake/toolchain/set_flags.cmake
new file mode 100644
index 000000000..e6c7b6feb
--- /dev/null
+++ b/cmake/toolchain/set_flags.cmake
@@ -0,0 +1,22 @@
+get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
+
+# join the toolchain flags into a single string
+list(JOIN TOOLCHAIN_COMMON_FLAGS " " TOOLCHAIN_COMMON_FLAGS)
+
+foreach(LANG IN ITEMS C CXX ASM)
+    set(CMAKE_${LANG}_FLAGS_INIT "${TOOLCHAIN_COMMON_FLAGS}")
+    if (PICO_DEOPTIMIZED_DEBUG)
+        set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-O0")
+    else()
+        set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-Og")
+    endif()
+    set(CMAKE_${LANG}_LINK_FLAGS "-Wl,--build-id=none")
+
+    # try_compile is where the feature testing is done, and at that point,
+    # pico_standard_link is not ready to be linked in to provide essential
+    # functions like _exit. So pass -nostdlib so it doesn't link in an exit()
+    # function at all.
+    if(IS_IN_TRY_COMPILE)
+        set(CMAKE_${LANG}_LINK_FLAGS "${CMAKE_${LANG}_LINK_FLAGS} -nostdlib")
+    endif()
+endforeach()
diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index 4435bd523..ac47bf0b4 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -1,4 +1,10 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.13)
+include(CMakePrintHelpers)
+
+# default toolchain is gcc
+if (NOT TOOLCHAIN)
+  set(TOOLCHAIN "gcc")
+endif ()
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
@@ -24,7 +30,40 @@ if(NOT FAMILY STREQUAL "espressif")
           ${CMAKE_CURRENT_SOURCE_DIR}/src
           )
 
-  # Configure compilation flags and libraries for the example... see the corresponding function
-  # in hw/bsp/FAMILY/family.cmake for details.
-  family_configure_device_example(${PROJECT})
+  if(FAMILY STREQUAL "rp2040")
+    # Configure compilation flags and libraries for the example... see the corresponding function
+    # in hw/bsp/FAMILY/family.cmake for details.
+    family_configure_device_example(${PROJECT})
+  else ()
+    # TOP is absolute path to root directory of TinyUSB git repo
+    set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
+    get_filename_component(TOP "${TOP}" REALPATH)
+
+    # re-include family.cmake
+    include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
+
+    target_sources(${PROJECT} PUBLIC
+      ${TOP}/src/device/usbd.c
+      ${TOP}/src/device/usbd_control.c
+      ${TOP}/src/class/audio/audio_device.c
+      ${TOP}/src/class/cdc/cdc_device.c
+      ${TOP}/src/class/dfu/dfu_device.c
+      ${TOP}/src/class/dfu/dfu_rt_device.c
+      ${TOP}/src/class/hid/hid_device.c
+      ${TOP}/src/class/midi/midi_device.c
+      ${TOP}/src/class/msc/msc_device.c
+      ${TOP}/src/class/net/ecm_rndis_device.c
+      ${TOP}/src/class/net/ncm_device.c
+      ${TOP}/src/class/usbtmc/usbtmc_device.c
+      ${TOP}/src/class/vendor/vendor_device.c
+      ${TOP}/src/class/video/video_device.c
+      )
+
+    target_include_directories(${PROJECT} PUBLIC
+      ${TOP}/hw
+      ${TOP}/src
+      )
+
+
+  endif ()
 endif()
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index 8e4db9d29..caac260d1 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.13)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
new file mode 100644
index 000000000..52d1846ea
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT MIMXRT1011)
+
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
+  )
+
+target_compile_definitions(${PROJECT} PUBLIC
+  CPU_MIMXRT1011DAE5A
+  CFG_EXAMPLE_VIDEO_READONLY
+  )
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
new file mode 100644
index 000000000..1e095ebfb
--- /dev/null
+++ b/hw/bsp/imxrt/family.cmake
@@ -0,0 +1,69 @@
+# toolchain set up, include before project()
+if (NOT TARGET ${PROJECT})
+  set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
+  set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+else ()
+  if (NOT BOARD)
+    message(FATAL_ERROR "BOARD not specified")
+  endif ()
+
+  set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+  set(DEPS_SUBMODULES ${SDK_DIR})
+
+  # include basic family CMake functionality
+  #set(FAMILY_MCUS RP2040)
+
+  include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+  target_compile_definitions(${PROJECT} PUBLIC
+    CFG_TUSB_MCU=OPT_MCU_MIMXRT
+    __ARMVFP__=0
+    __ARMFPV5__=0
+    XIP_EXTERNAL_FLASH=1
+    XIP_BOOT_HEADER_ENABLE=1
+    )
+
+  target_link_options(${PROJECT} PUBLIC
+    --specs=nosys.specs
+    --specs=nano.specs
+    #-lgcc -lm -lnosys
+    )
+
+#  target_link_libraries(${PROJECT} PUBLIC
+#    -lgcc -lm -lnosys
+#    )
+
+  target_sources(${PROJECT} PUBLIC
+    # TinyUSB
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+    ${TOP}/src/portable/ehci/ehci.c
+    # BSP
+    ${CMAKE_CURRENT_LIST_DIR}/family.c
+    ${SDK_DIR}/drivers/common/fsl_common.c
+    ${SDK_DIR}/drivers/igpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/project_template/clock_config.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    )
+
+  if (TOOLCHAIN STREQUAL "gcc")
+    target_sources(${PROJECT} PUBLIC
+      ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
+      )
+  endif ()
+
+  target_include_directories(${PROJECT} PUBLIC
+    ${CMAKE_CURRENT_LIST_DIR}
+    ${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}
+    ${SDK_DIR}/CMSIS/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/project_template
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/igpio
+    ${SDK_DIR}/drivers/lpuart
+    )
+endif ()

From b42d3e431c15ac082b17a1725d639c4ee4980264 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 20 Apr 2023 16:42:13 +0700
Subject: [PATCH 1653/2085] board test running with cmake

---
 .idea/runConfigurations/rt1010.xml        | 10 ++++++++++
 examples/device/board_test/CMakeLists.txt |  2 +-
 hw/bsp/imxrt/family.cmake                 |  9 ++++-----
 3 files changed, 15 insertions(+), 6 deletions(-)
 create mode 100644 .idea/runConfigurations/rt1010.xml

diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml
new file mode 100644
index 000000000..50659c95c
--- /dev/null
+++ b/.idea/runConfigurations/rt1010.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="imxrt" PROGRAM_PARAMS="gdbserver -p 55503 -t mimxrt1010" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="board_test" TARGET_NAME="board_test" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="board_test" RUN_TARGET_NAME="board_test">
+    <custom-gdb-server version="1" gdb-connect="tcp::55503" executable="$USER_HOME$/.local/bin/pyocd" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index ac47bf0b4..847246453 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -11,7 +11,7 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 1e095ebfb..399e2be92 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -26,13 +26,8 @@ else ()
   target_link_options(${PROJECT} PUBLIC
     --specs=nosys.specs
     --specs=nano.specs
-    #-lgcc -lm -lnosys
     )
 
-#  target_link_libraries(${PROJECT} PUBLIC
-#    -lgcc -lm -lnosys
-#    )
-
   target_sources(${PROJECT} PUBLIC
     # TinyUSB
     ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -53,6 +48,10 @@ else ()
     target_sources(${PROJECT} PUBLIC
       ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
       )
+
+    target_link_options(${PROJECT} PUBLIC
+      "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld"
+      )
   endif ()
 
   target_include_directories(${PROJECT} PUBLIC

From 2ac289685aa5a93ac56d0e5705d8067a1f751bc6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 20 Apr 2023 16:55:48 +0700
Subject: [PATCH 1654/2085] clean up

---
 examples/device/board_test/CMakeLists.txt | 106 ++++++++++------------
 examples/device/cdc_msc/CMakeLists.txt    |   7 +-
 hw/bsp/family_support.cmake               |   7 ++
 hw/bsp/imxrt/family.cmake                 |   4 +-
 4 files changed, 66 insertions(+), 58 deletions(-)

diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index 847246453..835d15488 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -1,10 +1,4 @@
 cmake_minimum_required(VERSION 3.13)
-include(CMakePrintHelpers)
-
-# default toolchain is gcc
-if (NOT TOOLCHAIN)
-  set(TOOLCHAIN "gcc")
-endif ()
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
@@ -16,54 +10,54 @@ project(${PROJECT} C CXX ASM)
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
-# Other family such as rp2040
-if(NOT FAMILY STREQUAL "espressif")
-  add_executable(${PROJECT})
-
-  # Example source
-  target_sources(${PROJECT} PUBLIC
-          ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-          )
-
-  # Example include
-  target_include_directories(${PROJECT} PUBLIC
-          ${CMAKE_CURRENT_SOURCE_DIR}/src
-          )
-
-  if(FAMILY STREQUAL "rp2040")
-    # Configure compilation flags and libraries for the example... see the corresponding function
-    # in hw/bsp/FAMILY/family.cmake for details.
-    family_configure_device_example(${PROJECT})
-  else ()
-    # TOP is absolute path to root directory of TinyUSB git repo
-    set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
-    get_filename_component(TOP "${TOP}" REALPATH)
-
-    # re-include family.cmake
-    include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
-
-    target_sources(${PROJECT} PUBLIC
-      ${TOP}/src/device/usbd.c
-      ${TOP}/src/device/usbd_control.c
-      ${TOP}/src/class/audio/audio_device.c
-      ${TOP}/src/class/cdc/cdc_device.c
-      ${TOP}/src/class/dfu/dfu_device.c
-      ${TOP}/src/class/dfu/dfu_rt_device.c
-      ${TOP}/src/class/hid/hid_device.c
-      ${TOP}/src/class/midi/midi_device.c
-      ${TOP}/src/class/msc/msc_device.c
-      ${TOP}/src/class/net/ecm_rndis_device.c
-      ${TOP}/src/class/net/ncm_device.c
-      ${TOP}/src/class/usbtmc/usbtmc_device.c
-      ${TOP}/src/class/vendor/vendor_device.c
-      ${TOP}/src/class/video/video_device.c
-      )
-
-    target_include_directories(${PROJECT} PUBLIC
-      ${TOP}/hw
-      ${TOP}/src
-      )
-
-
-  endif ()
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
 endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+if(FAMILY STREQUAL "rp2040")
+  # Configure compilation flags and libraries for the example... see the corresponding function
+  # in hw/bsp/FAMILY/family.cmake for details.
+  family_configure_device_example(${PROJECT})
+else ()
+  # TOP is absolute path to root directory of TinyUSB git repo
+  set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
+  get_filename_component(TOP "${TOP}" REALPATH)
+
+  # re-include family.cmake
+  include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
+
+  target_sources(${PROJECT} PUBLIC
+    ${TOP}/src/device/usbd.c
+    ${TOP}/src/device/usbd_control.c
+    ${TOP}/src/class/audio/audio_device.c
+    ${TOP}/src/class/cdc/cdc_device.c
+    ${TOP}/src/class/dfu/dfu_device.c
+    ${TOP}/src/class/dfu/dfu_rt_device.c
+    ${TOP}/src/class/hid/hid_device.c
+    ${TOP}/src/class/midi/midi_device.c
+    ${TOP}/src/class/msc/msc_device.c
+    ${TOP}/src/class/net/ecm_rndis_device.c
+    ${TOP}/src/class/net/ncm_device.c
+    ${TOP}/src/class/usbtmc/usbtmc_device.c
+    ${TOP}/src/class/vendor/vendor_device.c
+    ${TOP}/src/class/video/video_device.c
+    )
+
+  target_include_directories(${PROJECT} PUBLIC
+    ${TOP}/hw
+    ${TOP}/src
+    )
+endif ()
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index caac260d1..43b81ce23 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -5,11 +5,16 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 08bb20bc3..cc95dde9e 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -1,4 +1,11 @@
 if (NOT TARGET _family_support_marker)
+    include(CMakePrintHelpers)
+
+    # Default to gcc
+    if(NOT DEFINED TOOLCHAIN)
+        set(TOOLCHAIN gcc)
+    endif()
+
     add_library(_family_support_marker INTERFACE)
 
     if (NOT FAMILY)
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 399e2be92..7da81dfb6 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -1,5 +1,7 @@
-# toolchain set up, include before project()
+
+
 if (NOT TARGET ${PROJECT})
+  # toolchain set up, include before project()
   set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
   set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 else ()

From 9bf97e3e52c09e2f7279ee37a86ec0b38275c494 Mon Sep 17 00:00:00 2001
From: Jacek Fedorynski <jfedor@jfedor.org>
Date: Thu, 13 Apr 2023 20:04:04 +0200
Subject: [PATCH 1655/2085] [rp2040] Make writes to SIE_CTRL aware of
 concurrent access

This commit makes it so that when setting the START_TRANS bit in the
SIE_CTRL register, along with some other bits, we first set all the
other bits, then wait some cycles, and then set the START_TRANS bit.

Doing so protects against a situation where the USB controller is
reading the register at the same time and gets an incorrect value.

This mirrors the procedure already applied to buffer control
registers.
---
 src/portable/raspberrypi/rp2040/hcd_rp2040.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 661255cf6..02f9968a7 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -562,6 +562,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
                      (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS) |
                      (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
+    // START_TRANS bit on SIE_CTRL seems to exhibit the same behavior as the AVAILABLE bit
+    // described in RP2040 Datasheet, release 2.1, section "4.1.2.5.1. Concurrent access".
+    // We write everything except the START_TRANS bit first, then wait some cycles.
+    usb_hw->sie_ctrl = flags & ~USB_SIE_CTRL_START_TRANS_BITS;
+    busy_wait_at_least_cycles(12);
     usb_hw->sie_ctrl = flags;
   }else
   {
@@ -602,6 +607,11 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
                          (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
 
+  // START_TRANS bit on SIE_CTRL seems to exhibit the same behavior as the AVAILABLE bit
+  // described in RP2040 Datasheet, release 2.1, section "4.1.2.5.1. Concurrent access".
+  // We write everything except the START_TRANS bit first, then wait some cycles.
+  usb_hw->sie_ctrl = flags & ~USB_SIE_CTRL_START_TRANS_BITS;
+  busy_wait_at_least_cycles(12);
   usb_hw->sie_ctrl = flags;
 
   return true;

From 0afe1b36842c1542293e2133212aa0cfca9608c8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 21 Apr 2023 18:10:28 +0700
Subject: [PATCH 1656/2085] example run well with cmake for imxrt

---
 examples/device/board_test/CMakeLists.txt   | 39 ++--------------
 examples/device/cdc_msc/CMakeLists.txt      |  2 +-
 examples/device/msc_dual_lun/CMakeLists.txt | 21 +++++----
 hw/bsp/imxrt/family.cmake                   | 50 +++++++++++++--------
 src/CMakeLists.txt                          | 25 +++++++++++
 5 files changed, 74 insertions(+), 63 deletions(-)
 create mode 100644 src/CMakeLists.txt

diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index 835d15488..c48efdaa5 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.13)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
@@ -27,37 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-if(FAMILY STREQUAL "rp2040")
-  # Configure compilation flags and libraries for the example... see the corresponding function
-  # in hw/bsp/FAMILY/family.cmake for details.
-  family_configure_device_example(${PROJECT})
-else ()
-  # TOP is absolute path to root directory of TinyUSB git repo
-  set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
-  get_filename_component(TOP "${TOP}" REALPATH)
-
-  # re-include family.cmake
-  include(${TOP}/hw/bsp/${FAMILY}/family.cmake)
-
-  target_sources(${PROJECT} PUBLIC
-    ${TOP}/src/device/usbd.c
-    ${TOP}/src/device/usbd_control.c
-    ${TOP}/src/class/audio/audio_device.c
-    ${TOP}/src/class/cdc/cdc_device.c
-    ${TOP}/src/class/dfu/dfu_device.c
-    ${TOP}/src/class/dfu/dfu_rt_device.c
-    ${TOP}/src/class/hid/hid_device.c
-    ${TOP}/src/class/midi/midi_device.c
-    ${TOP}/src/class/msc/msc_device.c
-    ${TOP}/src/class/net/ecm_rndis_device.c
-    ${TOP}/src/class/net/ncm_device.c
-    ${TOP}/src/class/usbtmc/usbtmc_device.c
-    ${TOP}/src/class/vendor/vendor_device.c
-    ${TOP}/src/class/video/video_device.c
-    )
-
-  target_include_directories(${PROJECT} PUBLIC
-    ${TOP}/hw
-    ${TOP}/src
-    )
-endif ()
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index 43b81ce23..7eddc2422 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.13)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt
index 9188ab06c..dc8d5512c 100644
--- a/examples/device/msc_dual_lun/CMakeLists.txt
+++ b/examples/device/msc_dual_lun/CMakeLists.txt
@@ -1,28 +1,33 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk_dual.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk_dual.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 7da81dfb6..d1d28d4eb 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -1,23 +1,27 @@
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-
-if (NOT TARGET ${PROJECT})
-  # toolchain set up, include before project()
-  set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
-  set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-else ()
+function(family_configure_target TARGET)
   if (NOT BOARD)
     message(FATAL_ERROR "BOARD not specified")
   endif ()
 
+  # set output name to .elf
+  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+
+  # TOP is absolute path to root directory of TinyUSB git repo
+  set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
+  get_filename_component(TOP "${TOP}" REALPATH)
+
   set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
   set(DEPS_SUBMODULES ${SDK_DIR})
 
-  # include basic family CMake functionality
-  #set(FAMILY_MCUS RP2040)
+  include(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board.cmake)
 
-  include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+  cmake_print_variables(TOP CMAKE_CURRENT_FUNCTION_LIST_DIR)
 
-  target_compile_definitions(${PROJECT} PUBLIC
+  target_compile_definitions(${TARGET} PUBLIC
     CFG_TUSB_MCU=OPT_MCU_MIMXRT
     __ARMVFP__=0
     __ARMFPV5__=0
@@ -25,18 +29,18 @@ else ()
     XIP_BOOT_HEADER_ENABLE=1
     )
 
-  target_link_options(${PROJECT} PUBLIC
+  target_link_options(${TARGET} PUBLIC
     --specs=nosys.specs
     --specs=nano.specs
     )
 
-  target_sources(${PROJECT} PUBLIC
+  target_sources(${TARGET} PUBLIC
     # TinyUSB
     ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
     ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
     ${TOP}/src/portable/ehci/ehci.c
     # BSP
-    ${CMAKE_CURRENT_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${SDK_DIR}/drivers/common/fsl_common.c
     ${SDK_DIR}/drivers/igpio/fsl_gpio.c
     ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
@@ -47,18 +51,19 @@ else ()
     )
 
   if (TOOLCHAIN STREQUAL "gcc")
-    target_sources(${PROJECT} PUBLIC
+    target_sources(${TARGET} PUBLIC
       ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
       )
 
-    target_link_options(${PROJECT} PUBLIC
+    target_link_options(${TARGET} PUBLIC
       "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld"
       )
   endif ()
 
-  target_include_directories(${PROJECT} PUBLIC
-    ${CMAKE_CURRENT_LIST_DIR}
-    ${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}
+  target_include_directories(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     ${SDK_DIR}/CMSIS/Include
     ${SDK_DIR}/devices/${MCU_VARIANT}
     ${SDK_DIR}/devices/${MCU_VARIANT}/project_template
@@ -67,4 +72,11 @@ else ()
     ${SDK_DIR}/drivers/igpio
     ${SDK_DIR}/drivers/lpuart
     )
-endif ()
+
+  # include tinyusb cmake
+  include(${TOP}/src/CMakeLists.txt)
+endfunction()
+
+function(family_configure_device_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
new file mode 100644
index 000000000..ade4c2c85
--- /dev/null
+++ b/src/CMakeLists.txt
@@ -0,0 +1,25 @@
+# cmake_minimum_required(VERSION 3.17)
+# TODO make tinyusb as library that depends on 'tusb_config' interface that exposes the tusb_config.h file
+
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_LIST_DIR}/tusb.c
+  ${CMAKE_CURRENT_LIST_DIR}/common/tusb_fifo.c
+  ${CMAKE_CURRENT_LIST_DIR}/device/usbd.c
+  ${CMAKE_CURRENT_LIST_DIR}/device/usbd_control.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/audio/audio_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/cdc/cdc_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_rt_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/hid/hid_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/midi/midi_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/msc/msc_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/net/ecm_rndis_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/net/ncm_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/usbtmc/usbtmc_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/vendor/vendor_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/video/video_device.c
+  )
+
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_LIST_DIR}
+  )

From 6daa135201b16c287f0b0d7ad7463877d471ceef Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 21 Apr 2023 18:23:40 +0700
Subject: [PATCH 1657/2085] update most examples cmake to build with imxrt

---
 examples/device/audio_4_channel_mic/CMakeLists.txt  | 13 +++++++++----
 examples/device/audio_test/CMakeLists.txt           |  9 +++++++--
 .../device/audio_test_multi_rate/CMakeLists.txt     |  9 +++++++--
 examples/device/cdc_dual_ports/CMakeLists.txt       |  9 +++++++--
 examples/device/cdc_msc_freertos/CMakeLists.txt     |  2 +-
 examples/device/dfu/CMakeLists.txt                  |  8 ++++++--
 examples/device/dfu_runtime/CMakeLists.txt          |  8 ++++++--
 .../device/dynamic_configuration/CMakeLists.txt     |  8 ++++++--
 examples/device/hid_boot_interface/CMakeLists.txt   |  8 ++++++--
 examples/device/hid_composite/CMakeLists.txt        |  8 ++++++--
 examples/device/hid_generic_inout/CMakeLists.txt    |  8 ++++++--
 .../device/hid_multiple_interface/CMakeLists.txt    |  8 ++++++--
 examples/device/midi_test/CMakeLists.txt            |  9 ++++++---
 examples/device/uac2_headset/CMakeLists.txt         |  9 +++++++--
 examples/device/usbtmc/CMakeLists.txt               |  9 +++++++--
 examples/device/video_capture/CMakeLists.txt        |  9 +++++++--
 examples/device/webusb_serial/CMakeLists.txt        |  9 +++++++--
 17 files changed, 107 insertions(+), 36 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/CMakeLists.txt b/examples/device/audio_4_channel_mic/CMakeLists.txt
index f6e10e2ea..87b7d07d4 100644
--- a/examples/device/audio_4_channel_mic/CMakeLists.txt
+++ b/examples/device/audio_4_channel_mic/CMakeLists.txt
@@ -1,27 +1,32 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
   ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-)
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
-)
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt
index f6e10e2ea..b0889285c 100644
--- a/examples/device/audio_test/CMakeLists.txt
+++ b/examples/device/audio_test/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/device/audio_test_multi_rate/CMakeLists.txt b/examples/device/audio_test_multi_rate/CMakeLists.txt
index f6e10e2ea..b0889285c 100644
--- a/examples/device/audio_test_multi_rate/CMakeLists.txt
+++ b/examples/device/audio_test_multi_rate/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt
index acaa54198..d142e9c04 100644
--- a/examples/device/cdc_dual_ports/CMakeLists.txt
+++ b/examples/device/cdc_dual_ports/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 714e5333b..c6cce711a 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
diff --git a/examples/device/dfu/CMakeLists.txt b/examples/device/dfu/CMakeLists.txt
index acaa54198..eb4c198d6 100644
--- a/examples/device/dfu/CMakeLists.txt
+++ b/examples/device/dfu/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt
index acaa54198..eb4c198d6 100644
--- a/examples/device/dfu_runtime/CMakeLists.txt
+++ b/examples/device/dfu_runtime/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt
index 8e4db9d29..046a32257 100644
--- a/examples/device/dynamic_configuration/CMakeLists.txt
+++ b/examples/device/dynamic_configuration/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
diff --git a/examples/device/hid_boot_interface/CMakeLists.txt b/examples/device/hid_boot_interface/CMakeLists.txt
index acaa54198..eb4c198d6 100644
--- a/examples/device/hid_boot_interface/CMakeLists.txt
+++ b/examples/device/hid_boot_interface/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt
index acaa54198..eb4c198d6 100644
--- a/examples/device/hid_composite/CMakeLists.txt
+++ b/examples/device/hid_composite/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt
index acaa54198..eb4c198d6 100644
--- a/examples/device/hid_generic_inout/CMakeLists.txt
+++ b/examples/device/hid_generic_inout/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt
index acaa54198..eb4c198d6 100644
--- a/examples/device/hid_multiple_interface/CMakeLists.txt
+++ b/examples/device/hid_multiple_interface/CMakeLists.txt
@@ -1,14 +1,18 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
 
diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt
index acaa54198..5b1a5547d 100644
--- a/examples/device/midi_test/CMakeLists.txt
+++ b/examples/device/midi_test/CMakeLists.txt
@@ -1,17 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
 
 add_executable(${PROJECT})
-
 # Example source
 target_sources(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt
index acaa54198..d142e9c04 100644
--- a/examples/device/uac2_headset/CMakeLists.txt
+++ b/examples/device/uac2_headset/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt
index b4678dc5e..a6b22ab36 100644
--- a/examples/device/usbtmc/CMakeLists.txt
+++ b/examples/device/usbtmc/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt
index f1ef247e1..e0bd975c4 100644
--- a/examples/device/video_capture/CMakeLists.txt
+++ b/examples/device/video_capture/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 if (FORCE_READONLY)
diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt
index acaa54198..d142e9c04 100644
--- a/examples/device/webusb_serial/CMakeLists.txt
+++ b/examples/device/webusb_serial/CMakeLists.txt
@@ -1,15 +1,20 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source

From 11e1aff3891c7e88f66391b5b5ee850c26f10594 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 21 Apr 2023 20:55:44 +0700
Subject: [PATCH 1658/2085] update freeRTOS kernel to latest for library cmake

add per family freeRTOSConfig.h also make changes to build with
freertos_kernel cmake
- hard coded configPRIO_BITS based on family
- change configSUPPORT_STATIC_ALLOCATION to 0,
configSUPPORT_DYNAMIC_ALLOCATION to 1
- enable configRECORD_STACK_HIGH_ADDRESS for tracing
- enable INCLUDE_xTaskGetCurrentTaskHandle which is required to compile
stream_buffer (although we don't use it).
---
 .../device/cdc_msc_freertos/CMakeLists.txt    |  37 +++-
 .../cdc_msc_freertos/src/CMakeLists.txt       |   1 +
 hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h  | 166 ++++++++++++++++++
 hw/bsp/imxrt/family.cmake                     |  18 ++
 tools/get_deps.py                             |   2 +-
 5 files changed, 219 insertions(+), 5 deletions(-)
 create mode 100644 hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h

diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index c6cce711a..89ff87e13 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -5,12 +5,41 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
-# Check for -DFAMILY=
-if(NOT FAMILY STREQUAL "espressif")
-  message(FATAL_ERROR "Invalid FAMILY specified: ${FAMILY}")
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
 endif()
+
+add_executable(${PROJECT})
+
+set(freertos_path ${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel)
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  ${freertos_path}/include
+  )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
+
+family_add_freertos_config(${PROJECT})
+add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel)
+
+target_link_libraries(${PROJECT} PUBLIC
+  freertos_kernel
+  )
diff --git a/examples/device/cdc_msc_freertos/src/CMakeLists.txt b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
index b77a68c8d..fee264363 100644
--- a/examples/device/cdc_msc_freertos/src/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/src/CMakeLists.txt
@@ -1,3 +1,4 @@
+# This file is for ESP-IDF only
 idf_component_register(SRCS "main.c" "usb_descriptors.c" "msc_disk.c"
                     INCLUDE_DIRS "."
                     REQUIRES boards tinyusb_src)
diff --git a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..c8d94f9ed
--- /dev/null
+++ b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+// FIXME cause redundant-decls warnings
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU								        0
+#define configENABLE_FPU								        1
+#define configENABLE_TRUSTZONE					        0
+#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index d1d28d4eb..40b8ab974 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -58,6 +58,8 @@ function(family_configure_target TARGET)
     target_link_options(${TARGET} PUBLIC
       "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld"
       )
+  else ()
+    # TODO support IAR
   endif ()
 
   target_include_directories(${TARGET} PUBLIC
@@ -77,6 +79,22 @@ function(family_configure_target TARGET)
   include(${TOP}/src/CMakeLists.txt)
 endfunction()
 
+function(family_add_freertos_config TARGET)
+  add_library(freertos_config INTERFACE)
+
+  # add path to FreeRTOSConfig.h
+  target_include_directories(freertos_config SYSTEM INTERFACE
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig
+    )
+
+  # select freertos port
+  if (TOOLCHAIN STREQUAL "gcc")
+    set(FREERTOS_PORT "GCC_ARM_CM7" CACHE INTERNAL "")
+  else ()
+    # TODO support IAR
+  endif ()
+endfunction()
+
 function(family_configure_device_example TARGET)
   family_configure_target(${TARGET})
 endfunction()
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 4b81d1468..f1723fde2 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -6,7 +6,7 @@ from multiprocessing import Pool
 # Mandatory Dependencies that is always fetched
 # path, url, commit (Alphabet sorted by path)
 deps_mandatory = {
-    'lib/FreeRTOS-Kernel'                      : ['def7d2df2b0506d3d249334974f51e427c17a41c', 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git'               ],
+    'lib/FreeRTOS-Kernel'                      : ['5f19e34f878af97810a7662a75eac59bd74d628b', 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git'               ],
     'lib/lwip'                                 : ['159e31b689577dbf69cf0683bbaffbd71fa5ee10', 'https://github.com/lwip-tcpip/lwip.git'                        ],
     'tools/uf2'                                : ['19615407727073e36d81bf239c52108ba92e7660', 'https://github.com/microsoft/uf2.git'                          ],
 }

From 9858d45815ca5dec16b267d3c795e42b5084e394 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 21 Apr 2023 22:07:58 +0700
Subject: [PATCH 1659/2085] build all freertos, not able to build net lwip due
 to lack of sio_open()

---
 .../device/cdc_msc_freertos/CMakeLists.txt    |  5 +--
 .../hid_composite_freertos/CMakeLists.txt     | 37 ++++++++++++++++---
 .../device/net_lwip_webserver/CMakeLists.txt  |  4 +-
 3 files changed, 36 insertions(+), 10 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 89ff87e13..699860223 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -17,8 +17,6 @@ endif()
 
 add_executable(${PROJECT})
 
-set(freertos_path ${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel)
-
 # Example source
 target_sources(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c
@@ -30,15 +28,16 @@ target_sources(${PROJECT} PUBLIC
 # Example include
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
-  ${freertos_path}/include
   )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
 
+if (NOT TARGET freertos_kernel)
 family_add_freertos_config(${PROJECT})
 add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel)
+endif()
 
 target_link_libraries(${PROJECT} PUBLIC
   freertos_kernel
diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt
index 714e5333b..9b0ffa4b6 100644
--- a/examples/device/hid_composite_freertos/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/CMakeLists.txt
@@ -1,16 +1,43 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
-# Check for -DFAMILY=
-if(NOT FAMILY STREQUAL "espressif")
-  message(FATAL_ERROR "Invalid FAMILY specified: ${FAMILY}")
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
 endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
+
+if (NOT TARGET freertos_kernel)
+family_add_freertos_config(${PROJECT})
+add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel)
+endif()
+
+target_link_libraries(${PROJECT} PUBLIC
+  freertos_kernel
+  )
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 5f1e37931..e7338c809 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 set(TOP "../../..")
 get_filename_component(TOP "${TOP}" REALPATH)
@@ -9,7 +9,7 @@ if (EXISTS ${TOP}/lib/lwip/src)
     # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
     family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-    project(${PROJECT})
+    project(${PROJECT} C CXX ASM)
 
     # Checks this example is valid for the family and initializes the project
     family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})

From 5254202b203ee58e2fdb319c85e2ae1a87518140 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Apr 2023 11:54:58 +0700
Subject: [PATCH 1660/2085] minor update

---
 cmake/toolchain/arm_gcc.cmake   | 35 +++++++++++++++++++++++
 cmake/toolchain/set_flags.cmake | 36 +++++++++++-------------
 hw/bsp/imxrt/family.cmake       |  4 +--
 src/CMakeLists.txt              | 50 +++++++++++++++++++--------------
 4 files changed, 83 insertions(+), 42 deletions(-)

diff --git a/cmake/toolchain/arm_gcc.cmake b/cmake/toolchain/arm_gcc.cmake
index 44683118e..c5937192e 100644
--- a/cmake/toolchain/arm_gcc.cmake
+++ b/cmake/toolchain/arm_gcc.cmake
@@ -16,4 +16,39 @@ set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
 set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_SYSTEM_PROCESSOR)
 
 include(${CMAKE_CURRENT_LIST_DIR}/../cpu/${CMAKE_SYSTEM_PROCESSOR}.cmake)
+
+# enable all possible warnings for building examples
+list(APPEND TOOLCHAIN_COMMON_FLAGS
+  -fdata-sections
+  -ffunction-sections
+  -fsingle-precision-constant
+  -fno-strict-aliasing
+  )
+
+set(TOOLCHAIN_WARNING_FLAGS
+  -Wall
+  -Wextra
+  -Werror
+  -Wfatal-errors
+  -Wdouble-promotion
+  -Wstrict-prototypes
+  -Wstrict-overflow
+  -Werror-implicit-function-declaration
+  -Wfloat-equal
+  -Wundef
+  -Wshadow
+  -Wwrite-strings
+  -Wsign-compare
+  -Wmissing-format-attribute
+  -Wunreachable-code
+  -Wcast-align
+  -Wcast-function-type
+  -Wcast-qual
+  -Wnull-dereference
+  -Wuninitialized
+  -Wunused
+  -Wreturn-type
+  -Wredundant-decls
+  )
+
 include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake)
diff --git a/cmake/toolchain/set_flags.cmake b/cmake/toolchain/set_flags.cmake
index e6c7b6feb..da381c254 100644
--- a/cmake/toolchain/set_flags.cmake
+++ b/cmake/toolchain/set_flags.cmake
@@ -1,22 +1,20 @@
-get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
-
-# join the toolchain flags into a single string
-list(JOIN TOOLCHAIN_COMMON_FLAGS " " TOOLCHAIN_COMMON_FLAGS)
-
+include(CMakePrintHelpers)
 foreach(LANG IN ITEMS C CXX ASM)
-    set(CMAKE_${LANG}_FLAGS_INIT "${TOOLCHAIN_COMMON_FLAGS}")
-    if (PICO_DEOPTIMIZED_DEBUG)
-        set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-O0")
-    else()
-        set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-Og")
-    endif()
-    set(CMAKE_${LANG}_LINK_FLAGS "-Wl,--build-id=none")
+    # join the toolchain flags into a single string
+    list(APPEND TOOLCHAIN_${LANG}_FLAGS ${TOOLCHAIN_COMMON_FLAGS})
+    list(JOIN TOOLCHAIN_${LANG}_FLAGS " " TOOLCHAIN_${LANG}_FLAGS)
+    set(CMAKE_${LANG}_FLAGS_INIT "${TOOLCHAIN_${LANG}_FLAGS}")
 
-    # try_compile is where the feature testing is done, and at that point,
-    # pico_standard_link is not ready to be linked in to provide essential
-    # functions like _exit. So pass -nostdlib so it doesn't link in an exit()
-    # function at all.
-    if(IS_IN_TRY_COMPILE)
-        set(CMAKE_${LANG}_LINK_FLAGS "${CMAKE_${LANG}_LINK_FLAGS} -nostdlib")
-    endif()
+    #cmake_print_variables(CMAKE_${LANG}_FLAGS_INIT)
+
+    # optimization flags
+    set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-Og")
 endforeach()
+
+# try_compile is cmake test compiling its own example,
+# pass -nostdlib to skip stdlib linking
+get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
+if(IS_IN_TRY_COMPILE)
+    set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
+    set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
+endif()
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 40b8ab974..e36adaf5a 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -19,8 +19,6 @@ function(family_configure_target TARGET)
 
   include(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board.cmake)
 
-  cmake_print_variables(TOP CMAKE_CURRENT_FUNCTION_LIST_DIR)
-
   target_compile_definitions(${TARGET} PUBLIC
     CFG_TUSB_MCU=OPT_MCU_MIMXRT
     __ARMVFP__=0
@@ -77,6 +75,8 @@ function(family_configure_target TARGET)
 
   # include tinyusb cmake
   include(${TOP}/src/CMakeLists.txt)
+  add_tinyusb(${TARGET})
+
 endfunction()
 
 function(family_add_freertos_config TARGET)
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index ade4c2c85..00755df95 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -1,25 +1,33 @@
 # cmake_minimum_required(VERSION 3.17)
 # TODO make tinyusb as library that depends on 'tusb_config' interface that exposes the tusb_config.h file
 
-target_sources(${PROJECT} PUBLIC
-  ${CMAKE_CURRENT_LIST_DIR}/tusb.c
-  ${CMAKE_CURRENT_LIST_DIR}/common/tusb_fifo.c
-  ${CMAKE_CURRENT_LIST_DIR}/device/usbd.c
-  ${CMAKE_CURRENT_LIST_DIR}/device/usbd_control.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/audio/audio_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/cdc/cdc_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_rt_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/hid/hid_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/midi/midi_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/msc/msc_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/net/ecm_rndis_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/net/ncm_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/usbtmc/usbtmc_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/vendor/vendor_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/video/video_device.c
-  )
+function(add_tinyusb TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c
+    )
 
-target_include_directories(${PROJECT} PUBLIC
-  ${CMAKE_CURRENT_LIST_DIR}
-  )
+  target_include_directories(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    )
+
+  # enable all possible warnings
+  target_compile_options(${TARGET} PUBLIC
+
+    )
+
+endfunction()

From a4d5d515493187437731eae830cb4b173fd11c02 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Apr 2023 16:24:06 +0700
Subject: [PATCH 1661/2085] add wip note

---
 .idea/runConfigurations/cdc_msc.xml       | 10 ----------
 .idea/runConfigurations/hid_composite.xml | 10 ----------
 .idea/runConfigurations/msc_dual_lun.xml  | 10 ----------
 .idea/runConfigurations/rt1010.xml        | 10 ----------
 src/CMakeLists.txt                        |  4 +++-
 5 files changed, 3 insertions(+), 41 deletions(-)
 delete mode 100644 .idea/runConfigurations/cdc_msc.xml
 delete mode 100644 .idea/runConfigurations/hid_composite.xml
 delete mode 100644 .idea/runConfigurations/msc_dual_lun.xml
 delete mode 100644 .idea/runConfigurations/rt1010.xml

diff --git a/.idea/runConfigurations/cdc_msc.xml b/.idea/runConfigurations/cdc_msc.xml
deleted file mode 100644
index fbeb4ae05..000000000
--- a/.idea/runConfigurations/cdc_msc.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="cdc_msc" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
-    <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
-      <debugger kind="GDB" isBundled="true" />
-    </openocd>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/hid_composite.xml b/.idea/runConfigurations/hid_composite.xml
deleted file mode 100644
index b9f1d1a72..000000000
--- a/.idea/runConfigurations/hid_composite.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="hid_composite" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="hid_composite" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="hid_composite">
-    <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
-      <debugger kind="GDB" isBundled="true" />
-    </openocd>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/msc_dual_lun.xml b/.idea/runConfigurations/msc_dual_lun.xml
deleted file mode 100644
index 5c1ea270b..000000000
--- a/.idea/runConfigurations/msc_dual_lun.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="msc_dual_lun" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="msc_dual_lun" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="msc_dual_lun">
-    <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
-      <debugger kind="GDB" isBundled="true" />
-    </openocd>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml
deleted file mode 100644
index 50659c95c..000000000
--- a/.idea/runConfigurations/rt1010.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" folderName="imxrt" PROGRAM_PARAMS="gdbserver -p 55503 -t mimxrt1010" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="board_test" TARGET_NAME="board_test" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="board_test" RUN_TARGET_NAME="board_test">
-    <custom-gdb-server version="1" gdb-connect="tcp::55503" executable="$USER_HOME$/.local/bin/pyocd" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
-      <debugger kind="GDB" isBundled="true" />
-    </custom-gdb-server>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 00755df95..a270ea8b7 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -1,5 +1,7 @@
-# cmake_minimum_required(VERSION 3.17)
 # TODO make tinyusb as library that depends on 'tusb_config' interface that exposes the tusb_config.h file
+# This file is WIP and should not used yet
+
+cmake_minimum_required(VERSION 3.17)
 
 function(add_tinyusb TARGET)
   target_sources(${TARGET} PUBLIC

From 841a62170e79944d0b03a2ca7e18c949eea70fe3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Apr 2023 16:54:26 +0700
Subject: [PATCH 1662/2085] bump up imxrt mcux-sdk to 2.13.1 commit
 f357a1150f6cf6c6b844f53f2d426bfb3e649850

---
 tools/get_deps.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index f1723fde2..d8b044343 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -24,7 +24,7 @@ deps_optional = {
     'hw/mcu/nordic/nrfx'                       : ['281cc2e178fd9a470d844b3afdea9eb322a0b0e8', 'https://github.com/NordicSemiconductor/nrfx.git'               ],
     'hw/mcu/nuvoton'                           : ['2204191ec76283371419fbcec207da02e1bc22fa', 'https://github.com/majbthrd/nuc_driver.git'                    ],
     'hw/mcu/nxp/lpcopen'                       : ['43c45c85405a5dd114fff0ea95cca62837740c13', 'https://github.com/hathach/nxp_lpcopen.git'                    ],
-    'hw/mcu/nxp/mcux-sdk'                      : ['ae2ab01d9d70ad00cd0e935c2552bd5f0e5c0294', 'https://github.com/NXPmicro/mcux-sdk.git'                      ],
+    'hw/mcu/nxp/mcux-sdk'                      : ['f357a1150f6cf6c6b844f53f2d426bfb3e649850', 'https://github.com/NXPmicro/mcux-sdk.git'                      ],
     'hw/mcu/nxp/nxp_sdk'                       : ['845c8fc49b6fb660f06a5c45225494eacb06f00c', 'https://github.com/hathach/nxp_sdk.git'                        ],
     'hw/mcu/raspberry_pi/Pico-PIO-USB'         : ['c3715ce94b6f6391856de56081d4d9b3e98fa93d', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git'            ],
     'hw/mcu/renesas/fsp'                       : ['8dc14709f2a6518b43f71efad70d900b7718d9f1', 'https://github.com/renesas/fsp.git'                            ],

From ad39833ea4c76f3b85317858fb52767fa07fea11 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Apr 2023 22:10:13 +0700
Subject: [PATCH 1663/2085] fix build with nxp since mcux-sdk from 2.13.0
 remove CMSIS folder

---
 hw/bsp/imxrt/family.mk       | 4 ++--
 hw/bsp/kinetis_k32/family.mk | 4 ++--
 hw/bsp/lpc51/family.mk       | 4 ++--
 hw/bsp/lpc54/family.mk       | 4 ++--
 hw/bsp/lpc55/family.mk       | 4 ++--
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 6788de8df..0c297f060 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -1,6 +1,6 @@
 UF2_FAMILY_ID = 0x4fb2d5bd
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
@@ -48,7 +48,7 @@ SRC_C += \
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/project_template \
 	$(TOP)/$(MCU_DIR)/drivers \
diff --git a/hw/bsp/kinetis_k32/family.mk b/hw/bsp/kinetis_k32/family.mk
index f89138b72..41f22e250 100644
--- a/hw/bsp/kinetis_k32/family.mk
+++ b/hw/bsp/kinetis_k32/family.mk
@@ -1,5 +1,5 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
@@ -19,7 +19,7 @@ SRC_C += \
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(SDK_DIR)/CMSIS/Include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/project_template \
 	$(TOP)/$(MCU_DIR)/drivers \
diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk
index 8a64f0945..bfca2f6b1 100644
--- a/hw/bsp/lpc51/family.mk
+++ b/hw/bsp/lpc51/family.mk
@@ -1,5 +1,5 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
@@ -29,7 +29,7 @@ SRC_C += \
 	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
 
 INC += \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index 0ec59f9bf..f52b9b5eb 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -1,5 +1,5 @@
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
@@ -40,7 +40,7 @@ SRC_C += \
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index 789f7727d..f9dabcfa3 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -1,6 +1,6 @@
 UF2_FAMILY_ID = 0x2abc77ec
 SDK_DIR = hw/mcu/nxp/mcux-sdk
-DEPS_SUBMODULES += lib/sct_neopixel $(SDK_DIR)
+DEPS_SUBMODULES += lib/CMSIS_5 lib/sct_neopixel $(SDK_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
@@ -51,7 +51,7 @@ SRC_C += \
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/lib/sct_neopixel \
-	$(TOP)/$(MCU_DIR)/../../CMSIS/Include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
 	$(TOP)/$(MCU_DIR)/drivers \
 	$(TOP)/$(SDK_DIR)/drivers/common \

From 1a229f3ce2623f8e0cf072e66e3770ee7f95e095 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Apr 2023 21:42:31 +0700
Subject: [PATCH 1664/2085] fix pio vbus typo

---
 hw/bsp/rp2040/family.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 920869585..3aa989c0e 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -125,10 +125,10 @@ void board_init(void)
   // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb
   set_sys_clock_khz(120000, true);
 
-#ifdef PIO_USB_VBUSEN_PIN
+#ifdef PICO_DEFAULT_PIO_USB_VBUSEN_PIN
   gpio_init(PICO_DEFAULT_PIO_USB_VBUSEN_PIN);
   gpio_set_dir(PICO_DEFAULT_PIO_USB_VBUSEN_PIN, GPIO_OUT);
-  gpio_put(PICO_DEFAULT_PIO_USB_VBUSEN_PIN, PIO_USB_VBUSEN_STATE);
+  gpio_put(PICO_DEFAULT_PIO_USB_VBUSEN_PIN, PICO_DEFAULT_PIO_USB_VBUSEN_STATE);
 #endif
 
   // rp2040 use pico-pio-usb for host tuh_configure() can be used to passed pio configuration to the host stack

From 45169d833d05ec8b64d0ce11a5ff1efbea0b7917 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Apr 2023 12:43:46 +0700
Subject: [PATCH 1665/2085] hacky, but ftdi work with hard code baudrate = 9600

---
 .codespell/ignore-words.txt      |   1 +
 src/class/cdc/cdc_host.c         | 366 ++++++++++++++++++++++++-------
 src/class/cdc/serial/ftdi_host.h | 258 ++++++++++++++++++++++
 src/host/usbh.c                  |   2 +-
 src/tusb_option.h                |   5 +
 5 files changed, 549 insertions(+), 83 deletions(-)
 create mode 100644 src/class/cdc/serial/ftdi_host.h

diff --git a/.codespell/ignore-words.txt b/.codespell/ignore-words.txt
index 5c89bae1c..2513691cb 100644
--- a/.codespell/ignore-words.txt
+++ b/.codespell/ignore-words.txt
@@ -1,6 +1,7 @@
 synopsys
 sie
 tre
+thre
 hsi
 fro
 dout
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index c0cc41adf..7949ff8d3 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -33,6 +33,10 @@
 
 #include "cdc_host.h"
 
+#if CFG_TUH_CDC_FTDI
+  #include "serial/ftdi_host.h"
+#endif
+
 
 // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
 #define CDCH_DEBUG   2
@@ -43,12 +47,18 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+enum {
+  SERIAL_PROTOCOL_ACM  = 0,
+  SERIAL_PROTOCOL_FTDI = 1,
+};
+
 typedef struct {
   uint8_t daddr;
   uint8_t bInterfaceNumber;
   uint8_t bInterfaceSubClass;
   uint8_t bInterfaceProtocol;
 
+  uint8_t serial_protocol;
   cdc_acm_capability_t acm_capability;
   uint8_t ep_notif;
 
@@ -111,6 +121,11 @@ static cdch_interface_t* find_new_itf(void)
   return NULL;
 }
 
+static inline bool support_line_request(cdch_interface_t const* p_cdc) {
+  return (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM && p_cdc->acm_capability.support_line_request) ||
+          (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI);
+}
+
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
@@ -270,21 +285,32 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
 
   if (xfer->result == XFER_RESULT_SUCCESS)
   {
-    switch(xfer->setup->bRequest)
-    {
-      case CDC_REQUEST_SET_CONTROL_LINE_STATE:
-        p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
-      break;
+    if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) {
+      switch (xfer->setup->bRequest) {
+        case CDC_REQUEST_SET_CONTROL_LINE_STATE:
+          p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
+          break;
 
-      case CDC_REQUEST_SET_LINE_CODING:
-      {
-        uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
-        memcpy(&p_cdc->line_coding, xfer->buffer, len);
+        case CDC_REQUEST_SET_LINE_CODING: {
+          uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
+          memcpy(&p_cdc->line_coding, xfer->buffer, len);
+        }
+          break;
+
+        default: break;
       }
-      break;
-
-      default: break;
     }
+    #if CFG_TUH_CDC_FTDI
+    else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
+      switch (xfer->setup->bRequest) {
+        case FTDI_SIO_MODEM_CTRL:
+          p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff);
+          break;
+
+        default: break;
+      }
+    }
+    #endif
   }
 
   xfer->complete_cb = p_cdc->user_control_cb;
@@ -294,27 +320,51 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
-  TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request);
+  TU_VERIFY(p_cdc && support_line_request(p_cdc));
 
   TU_LOG_CDCH("CDC Set Control Line State\r\n");
 
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
-    .wValue   = tu_htole16(line_state),
-    .wIndex   = tu_htole16((uint16_t) p_cdc->bInterfaceNumber),
-    .wLength  = 0
-  };
+  tusb_control_request_t request;
+
+  if(p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM ) {
+    tusb_control_request_t const acm_request = {
+      .bmRequestType_bit = {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
+      .wValue   = tu_htole16(line_state),
+      .wIndex   = tu_htole16((uint16_t) p_cdc->bInterfaceNumber),
+      .wLength  = 0
+    };
+
+    request = acm_request;
+  }
+  #if CFG_TUH_CDC_FTDI
+  else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
+    // FTDI use vendor specific request to set control line state
+    tusb_control_request_t const ftdi_request = {
+      .bmRequestType_bit = {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_VENDOR,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = FTDI_SIO_MODEM_CTRL,
+      .wValue   = tu_htole16(0x0300 | line_state), // 0x0300 is DTR and RTS enable
+      .wIndex   = 0, // port
+      .wLength  = 0
+    };
+
+    request = ftdi_request;
+  }
+  #endif
+  else {
+    return false;
+  }
 
   p_cdc->user_control_cb = complete_cb;
-  tuh_xfer_t xfer =
-  {
+  tuh_xfer_t xfer = {
     .daddr       = p_cdc->daddr,
     .ep_addr     = 0,
     .setup       = &request,
@@ -324,34 +374,60 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
   };
 
   TU_ASSERT(tuh_control_xfer(&xfer));
+
   return true;
 }
 
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
-  TU_VERIFY(p_cdc && p_cdc->acm_capability.support_line_request);
+  TU_VERIFY(p_cdc && support_line_request(p_cdc));
 
   TU_LOG_CDCH("CDC Set Line Conding\r\n");
 
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = CDC_REQUEST_SET_LINE_CODING,
-    .wValue   = 0,
-    .wIndex   = tu_htole16(p_cdc->bInterfaceNumber),
-    .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
-  };
+  tusb_control_request_t request;
+  uint8_t* enum_buf = NULL;
 
-  // use usbh enum buf to hold line coding since user line_coding variable may not live long enough
-  // for the transfer to complete
-  uint8_t* enum_buf = usbh_get_enum_buf();
-  memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t));
+  if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) {
+    tusb_control_request_t const acm_request = {
+      .bmRequestType_bit = {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_CLASS,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = CDC_REQUEST_SET_LINE_CODING,
+      .wValue   = 0,
+      .wIndex   = tu_htole16(p_cdc->bInterfaceNumber),
+      .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
+    };
+
+    request = acm_request;
+
+    // use usbh enum buf to hold line coding since user line_coding variable does not live long enough
+    enum_buf = usbh_get_enum_buf();
+    memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t));
+  }
+  #if CFG_TUH_CDC_FTDI
+  else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
+    // FTDI need to set baud rate and data bits, parity, stop bits separately
+    tusb_control_request_t const ftdi_request = {
+      .bmRequestType_bit = {
+        .recipient = TUSB_REQ_RCPT_INTERFACE,
+        .type      = TUSB_REQ_TYPE_VENDOR,
+        .direction = TUSB_DIR_OUT
+      },
+      .bRequest = FTDI_SIO_SET_BAUD_RATE,
+      .wValue   = 0x4138, // FIXME hardcoded to 9600 baud
+      .wIndex   = 0, // port
+      .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
+    };
+
+    request = ftdi_request;
+  }
+  #endif
+  else {
+    return false;
+  }
 
   p_cdc->user_control_cb = complete_cb;
   tuh_xfer_t xfer =
@@ -434,8 +510,17 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
   {
     tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
 
+    #if CFG_TUH_CDC_FTDI
+    // FTDI reserve 2 bytes for status
+    if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
+      uint8_t status[2];
+      tu_edpt_stream_read(&p_cdc->stream.rx, status, 2);
+      (void) status; // TODO handle status
+    }
+    #endif
+
     // invoke receive callback
-    if (tuh_cdc_rx_cb)  tuh_cdc_rx_cb(idx);
+    if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx);
 
     // prepare for next transfer if needed
     tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
@@ -453,17 +538,99 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 //--------------------------------------------------------------------+
 // Enumeration
 //--------------------------------------------------------------------+
-
-bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
+enum
 {
-  (void) rhport;
+  // ACM
+  CONFIG_SET_CONTROL_LINE_STATE,
+  CONFIG_SET_LINE_CODING,
+  CONFIG_COMPLETE,
 
-  // Only support ACM subclass
-  // Protocol 0xFF can be RNDIS device for windows XP
-  TU_VERIFY( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
-             CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass &&
-             0xFF                                     != itf_desc->bInterfaceProtocol);
+  // FTDI
+  CONFIG_FTDI_RESET
+};
 
+static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep)
+{
+  for(size_t i=0; i<2; i++)
+  {
+    TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType &&
+              TUSB_XFER_BULK     == desc_ep->bmAttributes.xfer);
+
+    TU_ASSERT(tuh_edpt_open(p_cdc->daddr, desc_ep));
+
+    if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
+    {
+      tu_edpt_stream_open(&p_cdc->stream.rx, p_cdc->daddr, desc_ep);
+    }else
+    {
+      tu_edpt_stream_open(&p_cdc->stream.tx, p_cdc->daddr, desc_ep);
+    }
+
+    desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(desc_ep);
+  }
+
+  return true;
+}
+
+#if CFG_TUH_CDC_FTDI
+bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+  // FTDI configuration includes 1 vendor interface + 2 bulk endpoints
+  TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2);
+  TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t * p_cdc = find_new_itf();
+  TU_VERIFY(p_cdc);
+
+  p_cdc->daddr              = daddr;
+  p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
+  p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
+  p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol;
+  p_cdc->line_state         = 0;
+  p_cdc->serial_protocol    = SERIAL_PROTOCOL_FTDI;
+
+  // endpoint pair
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep));
+
+  return true;
+}
+
+static bool ftdih_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_VENDOR,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = FTDI_SIO_RESET,
+    .wValue   = tu_htole16(FTDI_SIO_RESET_SIO),
+    .wIndex   = 0,
+    .wLength  = 0
+  };
+
+  p_cdc->user_control_cb = complete_cb;
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = NULL,
+    .complete_cb = complete_cb,
+    .user_data   = user_data
+  };
+
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
+}
+
+#endif
+
+
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
+{
   uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len;
 
   cdch_interface_t * p_cdc = find_new_itf();
@@ -474,6 +641,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
   p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
   p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol;
   p_cdc->line_state         = 0;
+  p_cdc->serial_protocol    = SERIAL_PROTOCOL_ACM;
 
   //------------- Control Interface -------------//
   uint8_t const * p_desc = tu_desc_next(itf_desc);
@@ -510,35 +678,45 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
     p_desc = tu_desc_next(p_desc);
 
     // data endpoints expected to be in pairs
-    for(uint32_t i=0; i<2; i++)
-    {
-      tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-      TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType &&
-                TUSB_XFER_BULK     == desc_ep->bmAttributes.xfer);
-
-      TU_ASSERT(tuh_edpt_open(daddr, desc_ep));
-
-      if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
-      {
-        tu_edpt_stream_open(&p_cdc->stream.rx, daddr, desc_ep);
-      }else
-      {
-        tu_edpt_stream_open(&p_cdc->stream.tx, daddr, desc_ep);
-      }
-
-      p_desc = tu_desc_next(p_desc);
-    }
+    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc));
   }
 
   return true;
 }
 
-enum
+
+bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
-  CONFIG_SET_CONTROL_LINE_STATE,
-  CONFIG_SET_LINE_CODING,
-  CONFIG_COMPLETE
-};
+  (void) rhport;
+
+  // Only support ACM subclass
+  // Note: Protocol 0xFF can be RNDIS device
+  if ( TUSB_CLASS_CDC                           == itf_desc->bInterfaceClass &&
+       CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass)
+  {
+    return acm_open(daddr, itf_desc, max_len);
+  }
+  else if ( 0xff == itf_desc->bInterfaceClass )
+  {
+    uint16_t vid, pid;
+    TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
+
+#if CFG_TUH_CDC_FTDI
+    if (TU_FTDI_VID == vid) {
+      uint16_t const ftdi_pids[] = {TU_FTDI_PID_LIST};
+      enum { FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) };
+
+      for (size_t i = 0; i < FTDI_PID_COUNT; i++) {
+        if (ftdi_pids[i] == pid) {
+          return ftdih_open(daddr, itf_desc, max_len);
+        }
+      }
+    }
+#endif
+  }
+
+  return false;
+}
 
 static void process_cdc_config(tuh_xfer_t* xfer)
 {
@@ -550,9 +728,16 @@ static void process_cdc_config(tuh_xfer_t* xfer)
 
   switch(state)
   {
+    #if CFG_TUH_CDC_FTDI
+    // Note may need to read FTDI eeprom
+    case CONFIG_FTDI_RESET:
+      TU_ASSERT(ftdih_sio_reset(p_cdc, process_cdc_config, CONFIG_SET_CONTROL_LINE_STATE), );
+      break;
+    #endif
+
     case CONFIG_SET_CONTROL_LINE_STATE:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      if (p_cdc->acm_capability.support_line_request)
+      if (support_line_request(p_cdc))
       {
         TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), );
         break;
@@ -562,7 +747,7 @@ static void process_cdc_config(tuh_xfer_t* xfer)
 
     case CONFIG_SET_LINE_CODING:
       #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      if (p_cdc->acm_capability.support_line_request)
+      if (support_line_request(p_cdc))
       {
         cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
         TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), );
@@ -588,7 +773,6 @@ static void process_cdc_config(tuh_xfer_t* xfer)
 
 bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
 {
-  // fake transfer to kick-off process
   tusb_control_request_t request;
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
@@ -596,7 +780,25 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
   xfer.daddr     = daddr;
   xfer.result    = XFER_RESULT_SUCCESS;
   xfer.setup     = &request;
-  xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE;
+
+  // fake transfer to kick-off process
+  uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num);
+  cdch_interface_t * p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc);
+
+  switch (p_cdc->serial_protocol) {
+    case SERIAL_PROTOCOL_ACM:
+      xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE;
+      break;
+
+  #if CFG_TUH_CDC_FTDI
+    case SERIAL_PROTOCOL_FTDI:
+      xfer.user_data = CONFIG_FTDI_RESET;
+      break;
+  #endif
+
+      default: return false;
+  }
 
   process_cdc_config(&xfer);
 
diff --git a/src/class/cdc/serial/ftdi_host.h b/src/class/cdc/serial/ftdi_host.h
new file mode 100644
index 000000000..4276d374e
--- /dev/null
+++ b/src/class/cdc/serial/ftdi_host.h
@@ -0,0 +1,258 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TUSB_FTDI_HOST_H
+#define TUSB_FTDI_HOST_H
+
+// VID/PID for matching FTDI devices
+#define TU_FTDI_VID 0x0403
+#define TU_FTDI_PID_LIST \
+  0x6001, 0x6006, 0x6010, 0x6011, 0x6014, 0x6015, 0x8372, 0xFBFA, \
+  0xcd18
+
+// Commands
+#define FTDI_SIO_RESET             	0    /* Reset the port */
+#define FTDI_SIO_MODEM_CTRL        	1    /* Set the modem control register */
+#define FTDI_SIO_SET_FLOW_CTRL     	2    /* Set flow control register */
+#define FTDI_SIO_SET_BAUD_RATE     	3    /* Set baud rate */
+#define FTDI_SIO_SET_DATA          	4    /* Set the data characteristics of the port */
+#define FTDI_SIO_GET_MODEM_STATUS  	5    /* Retrieve current value of modem status register */
+#define FTDI_SIO_SET_EVENT_CHAR    	6    /* Set the event character */
+#define FTDI_SIO_SET_ERROR_CHAR    	7    /* Set the error character */
+#define FTDI_SIO_SET_LATENCY_TIMER 	9    /* Set the latency timer */
+#define FTDI_SIO_GET_LATENCY_TIMER 	0x0a /* Get the latency timer */
+#define FTDI_SIO_SET_BITMODE       	0x0b /* Set bitbang mode */
+#define FTDI_SIO_READ_PINS         	0x0c /* Read immediate value of pins */
+#define FTDI_SIO_READ_EEPROM       	0x90 /* Read EEPROM */
+
+/* FTDI_SIO_RESET */
+#define FTDI_SIO_RESET_SIO 0
+#define FTDI_SIO_RESET_PURGE_RX 1
+#define FTDI_SIO_RESET_PURGE_TX 2
+
+/*
+ * BmRequestType:  0100 0000B
+ * bRequest:       FTDI_SIO_RESET
+ * wValue:         Control Value
+ *                   0 = Reset SIO
+ *                   1 = Purge RX buffer
+ *                   2 = Purge TX buffer
+ * wIndex:         Port
+ * wLength:        0
+ * Data:           None
+ *
+ * The Reset SIO command has this effect:
+ *
+ *    Sets flow control set to 'none'
+ *    Event char = $0D
+ *    Event trigger = disabled
+ *    Purge RX buffer
+ *    Purge TX buffer
+ *    Clear DTR
+ *    Clear RTS
+ *    baud and data format not reset
+ *
+ * The Purge RX and TX buffer commands affect nothing except the buffers
+ *
+   */
+
+/* FTDI_SIO_MODEM_CTRL */
+/*
+ * BmRequestType:   0100 0000B
+ * bRequest:        FTDI_SIO_MODEM_CTRL
+ * wValue:          ControlValue (see below)
+ * wIndex:          Port
+ * wLength:         0
+ * Data:            None
+ *
+ * NOTE: If the device is in RTS/CTS flow control, the RTS set by this
+ * command will be IGNORED without an error being returned
+ * Also - you can not set DTR and RTS with one control message
+ */
+
+#define FTDI_SIO_SET_DTR_MASK 0x1
+#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1)
+#define FTDI_SIO_SET_DTR_LOW  ((FTDI_SIO_SET_DTR_MASK << 8) | 0)
+#define FTDI_SIO_SET_RTS_MASK 0x2
+#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2)
+#define FTDI_SIO_SET_RTS_LOW  ((FTDI_SIO_SET_RTS_MASK << 8) | 0)
+
+/*
+ * ControlValue
+ * B0    DTR state
+ *          0 = reset
+ *          1 = set
+ * B1    RTS state
+ *          0 = reset
+ *          1 = set
+ * B2..7 Reserved
+ * B8    DTR state enable
+ *          0 = ignore
+ *          1 = use DTR state
+ * B9    RTS state enable
+ *          0 = ignore
+ *          1 = use RTS state
+ * B10..15 Reserved
+ */
+
+/* FTDI_SIO_SET_FLOW_CTRL */
+#define FTDI_SIO_DISABLE_FLOW_CTRL 0x0
+#define FTDI_SIO_RTS_CTS_HS (0x1 << 8)
+#define FTDI_SIO_DTR_DSR_HS (0x2 << 8)
+#define FTDI_SIO_XON_XOFF_HS (0x4 << 8)
+
+/*
+ *   BmRequestType:  0100 0000b
+ *   bRequest:       FTDI_SIO_SET_FLOW_CTRL
+ *   wValue:         Xoff/Xon
+ *   wIndex:         Protocol/Port - hIndex is protocol / lIndex is port
+ *   wLength:        0
+ *   Data:           None
+ *
+ * hIndex protocol is:
+ *   B0 Output handshaking using RTS/CTS
+ *       0 = disabled
+ *       1 = enabled
+ *   B1 Output handshaking using DTR/DSR
+ *       0 = disabled
+ *       1 = enabled
+ *   B2 Xon/Xoff handshaking
+ *       0 = disabled
+ *       1 = enabled
+ *
+ * A value of zero in the hIndex field disables handshaking
+ *
+ * If Xon/Xoff handshaking is specified, the hValue field should contain the
+ * XOFF character and the lValue field contains the XON character.
+ */
+
+/* FTDI_SIO_SET_BAUD_RATE */
+/*
+ * BmRequestType:  0100 0000B
+ * bRequest:       FTDI_SIO_SET_BAUDRATE
+ * wValue:         BaudDivisor value - see below
+ * wIndex:         Port
+ * wLength:        0
+ * Data:           None
+ * The BaudDivisor values are calculated as follows (too complicated):
+ */
+
+/* FTDI_SIO_SET_DATA */
+#define FTDI_SIO_SET_DATA_PARITY_NONE	(0x0 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_ODD	(0x1 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_EVEN	(0x2 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_MARK	(0x3 << 8)
+#define FTDI_SIO_SET_DATA_PARITY_SPACE	(0x4 << 8)
+#define FTDI_SIO_SET_DATA_STOP_BITS_1	(0x0 << 11)
+#define FTDI_SIO_SET_DATA_STOP_BITS_15	(0x1 << 11)
+#define FTDI_SIO_SET_DATA_STOP_BITS_2	(0x2 << 11)
+#define FTDI_SIO_SET_BREAK		(0x1 << 14)
+
+/*
+ * BmRequestType:  0100 0000B
+ * bRequest:       FTDI_SIO_SET_DATA
+ * wValue:         Data characteristics (see below)
+ * wIndex:         Port
+ * wLength:        0
+ * Data:           No
+ *
+ * Data characteristics
+ *
+ *   B0..7   Number of data bits
+ *   B8..10  Parity
+ *           0 = None
+ *           1 = Odd
+ *           2 = Even
+ *           3 = Mark
+ *           4 = Space
+ *   B11..13 Stop Bits
+ *           0 = 1
+ *           1 = 1.5
+ *           2 = 2
+ *   B14
+ *           1 = TX ON (break)
+ *           0 = TX OFF (normal state)
+ *   B15 Reserved
+ *
+ */
+
+/*
+* DATA FORMAT
+*
+* IN Endpoint
+*
+* The device reserves the first two bytes of data on this endpoint to contain
+* the current values of the modem and line status registers. In the absence of
+* data, the device generates a message consisting of these two status bytes
+  * every 40 ms
+  *
+  * Byte 0: Modem Status
+*
+* Offset	Description
+* B0	Reserved - must be 1
+* B1	Reserved - must be 0
+* B2	Reserved - must be 0
+* B3	Reserved - must be 0
+* B4	Clear to Send (CTS)
+* B5	Data Set Ready (DSR)
+* B6	Ring Indicator (RI)
+* B7	Receive Line Signal Detect (RLSD)
+*
+* Byte 1: Line Status
+*
+* Offset	Description
+* B0	Data Ready (DR)
+* B1	Overrun Error (OE)
+* B2	Parity Error (PE)
+* B3	Framing Error (FE)
+* B4	Break Interrupt (BI)
+* B5	Transmitter Holding Register (THRE)
+* B6	Transmitter Empty (TEMT)
+* B7	Error in RCVR FIFO
+*
+*/
+#define FTDI_RS0_CTS	(1 << 4)
+#define FTDI_RS0_DSR	(1 << 5)
+#define FTDI_RS0_RI	(1 << 6)
+#define FTDI_RS0_RLSD	(1 << 7)
+
+#define FTDI_RS_DR	1
+#define FTDI_RS_OE	(1<<1)
+#define FTDI_RS_PE	(1<<2)
+#define FTDI_RS_FE	(1<<3)
+#define FTDI_RS_BI	(1<<4)
+#define FTDI_RS_THRE	(1<<5)
+#define FTDI_RS_TEMT	(1<<6)
+#define FTDI_RS_FIFO	(1<<7)
+
+//--------------------------------------------------------------------+
+// Internal Class Driver API
+//--------------------------------------------------------------------+
+void ftdih_init       (void);
+bool ftdih_open       (uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+bool ftdih_set_config (uint8_t daddr, uint8_t itf_num);
+bool ftdih_xfer_cb    (uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void ftdih_close      (uint8_t daddr);
+
+#endif //TUSB_FTDI_HOST_H
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 3be662c63..3953d5b21 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -286,7 +286,7 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
   *vid = *pid = 0;
 
   usbh_device_t const* dev = get_device(dev_addr);
-  TU_VERIFY(dev && dev->configured);
+  TU_VERIFY(dev && dev->addressed && dev->vid != 0);
 
   *vid = dev->vid;
   *pid = dev->pid;
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 44d036ea4..a372e9950 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -439,6 +439,11 @@
 #define CFG_TUH_CDC    0
 #endif
 
+#ifndef CFG_TUH_CDC_FTDI
+  // FTDI is not part of CDC class, CDC is used for Serial-over-USB here
+  #define CFG_TUH_CDC_FTDI 0
+#endif
+
 #ifndef CFG_TUH_HID
 #define CFG_TUH_HID    0
 #endif

From cf95b4400167f6e523d8e5d1762a78744f63e2a9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Apr 2023 22:35:28 +0700
Subject: [PATCH 1666/2085] enable CDC FTDI

---
 examples/host/cdc_msc_hid/src/tusb_config.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 1152e4910..2baf2b1ac 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -96,7 +96,8 @@
 #define CFG_TUH_ENUMERATION_BUFSIZE 256
 
 #define CFG_TUH_HUB                 1 // number of supported hubs
-#define CFG_TUH_CDC                 1
+#define CFG_TUH_CDC                 1 // CDC ACM
+#define CFG_TUH_CDC_FTDI            1 // FTDI UART
 #define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0

From 293a6222f81ac1085f8b34730f1907f899ce17cf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Apr 2023 11:08:42 +0700
Subject: [PATCH 1667/2085] rename ftdi_host to ftdi_sio

---
 examples/host/cdc_msc_hid/CMakeLists.txt         |  2 +-
 src/class/cdc/cdc_host.c                         |  2 +-
 src/class/cdc/serial/{ftdi_host.h => ftdi_sio.h} | 15 +++------------
 3 files changed, 5 insertions(+), 14 deletions(-)
 rename src/class/cdc/serial/{ftdi_host.h => ftdi_sio.h} (92%)

diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index d7d1a54d7..b66ff2382 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 7949ff8d3..d33f31f1a 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -34,7 +34,7 @@
 #include "cdc_host.h"
 
 #if CFG_TUH_CDC_FTDI
-  #include "serial/ftdi_host.h"
+  #include "serial/ftdi_sio.h"
 #endif
 
 
diff --git a/src/class/cdc/serial/ftdi_host.h b/src/class/cdc/serial/ftdi_sio.h
similarity index 92%
rename from src/class/cdc/serial/ftdi_host.h
rename to src/class/cdc/serial/ftdi_sio.h
index 4276d374e..6916e4031 100644
--- a/src/class/cdc/serial/ftdi_host.h
+++ b/src/class/cdc/serial/ftdi_sio.h
@@ -22,8 +22,8 @@
  * THE SOFTWARE.
  */
 
-#ifndef TUSB_FTDI_HOST_H
-#define TUSB_FTDI_HOST_H
+#ifndef TUSB_FTDI_SIO_H
+#define TUSB_FTDI_SIO_H
 
 // VID/PID for matching FTDI devices
 #define TU_FTDI_VID 0x0403
@@ -246,13 +246,4 @@
 #define FTDI_RS_TEMT	(1<<6)
 #define FTDI_RS_FIFO	(1<<7)
 
-//--------------------------------------------------------------------+
-// Internal Class Driver API
-//--------------------------------------------------------------------+
-void ftdih_init       (void);
-bool ftdih_open       (uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
-bool ftdih_set_config (uint8_t daddr, uint8_t itf_num);
-bool ftdih_xfer_cb    (uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
-void ftdih_close      (uint8_t daddr);
-
-#endif //TUSB_FTDI_HOST_H
+#endif //TUSB_FTDI_SIO_H

From 85d9925d24feb41bd355a9248207acaf853b70ff Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Apr 2023 15:20:04 +0700
Subject: [PATCH 1668/2085] refactor ftdi driver

---
 src/class/cdc/cdc_host.c | 463 +++++++++++++++++++++++++--------------
 src/tusb_option.h        |   7 +-
 2 files changed, 307 insertions(+), 163 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index d33f31f1a..fc7a7a038 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -37,6 +37,9 @@
   #include "serial/ftdi_sio.h"
 #endif
 
+#if CFG_TUH_CDC_CP210X
+  #include "serial/cp210x.h"
+#endif
 
 // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
 #define CDCH_DEBUG   2
@@ -48,8 +51,9 @@
 //--------------------------------------------------------------------+
 
 enum {
-  SERIAL_PROTOCOL_ACM  = 0,
-  SERIAL_PROTOCOL_FTDI = 1,
+  SERIAL_PROTOCOL_ACM = 0,
+  SERIAL_PROTOCOL_FTDI,
+  SERIAL_PROTOCOL_CP210X,
 };
 
 typedef struct {
@@ -111,11 +115,20 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr)
 }
 
 
-static cdch_interface_t* find_new_itf(void)
+static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc)
 {
   for(uint8_t i=0; i<CFG_TUH_CDC; i++)
   {
-    if (cdch_data[i].daddr == 0) return &cdch_data[i];
+    if (cdch_data[i].daddr == 0) {
+      cdch_interface_t* p_cdc = &cdch_data[i];
+
+      p_cdc->daddr              = daddr;
+      p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
+      p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
+      p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol;
+      p_cdc->line_state         = 0;
+      return p_cdc;
+    }
   }
 
   return NULL;
@@ -126,6 +139,221 @@ static inline bool support_line_request(cdch_interface_t const* p_cdc) {
           (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI);
 }
 
+static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep);
+static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num);
+static void cdch_internal_control_complete(tuh_xfer_t* xfer);
+
+//--------------------------------------------------------------------+
+// FTDI
+//--------------------------------------------------------------------+
+#if CFG_TUH_CDC_FTDI
+
+static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST };
+enum {
+  FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
+};
+
+enum {
+  CONFIG_FTDI_RESET,
+  CONFIG_FTDI_MODEM_CTRL,
+  CONFIG_FTDI_SET_BAUDRATE,
+  CONFIG_FTDI_SET_DATA,
+  CONFIG_FTDI_COMPLETE
+};
+
+static bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+  // FTDI Interface includes 1 vendor interface + 2 bulk endpoints
+  TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2);
+  TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY(p_cdc);
+
+  p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI;
+
+  // endpoint pair
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  return open_ep_stream_pair(p_cdc, desc_ep);
+}
+
+static bool ftdih_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_VENDOR,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = FTDI_SIO_RESET,
+    .wValue   = tu_htole16(FTDI_SIO_RESET_SIO),
+    .wIndex   = 0,
+    .wLength  = 0
+  };
+
+  p_cdc->user_control_cb = complete_cb;
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = NULL,
+    .complete_cb = complete_cb,
+    .user_data   = user_data
+  };
+
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
+}
+
+static bool ftdi_sio_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_VENDOR,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = FTDI_SIO_MODEM_CTRL,
+    .wValue   = tu_htole16(0x0300 | line_state), // 0x0300 is DTR and RTS enable
+    .wIndex   = 0, // port
+    .wLength  = 0
+  };
+
+  p_cdc->user_control_cb = complete_cb;
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = NULL,
+    .complete_cb = cdch_internal_control_complete,
+    .user_data   = user_data
+  };
+
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
+}
+
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  // TODO baudrate to baud divisor
+  (void) baudrate;
+
+  uint16_t divisor = 0x4138; // FIXME hardcoded to 9600 baud
+
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_VENDOR,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = FTDI_SIO_SET_BAUD_RATE,
+    .wValue   = tu_htole16(divisor),
+    .wIndex   = 0, // port
+    .wLength  = 0
+  };
+
+  p_cdc->user_control_cb = complete_cb;
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = NULL,
+    .complete_cb = cdch_internal_control_complete,
+    .user_data   = user_data
+  };
+
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
+}
+
+static void process_ftdi_config(tuh_xfer_t* xfer) {
+  uintptr_t const state = xfer->user_data;
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t * p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc, );
+
+  switch(state) {
+    // Note may need to read FTDI eeprom
+    case CONFIG_FTDI_RESET:
+      TU_ASSERT(ftdih_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),);
+      break;
+
+    case CONFIG_FTDI_MODEM_CTRL:
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+      TU_ASSERT(ftdi_sio_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+
+    case CONFIG_FTDI_SET_BAUDRATE: {
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, process_ftdi_config, CONFIG_FTDI_SET_DATA),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+    }
+
+    case CONFIG_FTDI_SET_DATA: {
+  #if 0 // TODO set data format
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      TU_ASSERT(ftdi_sio_set_data(p_cdc, process_ftdi_config, CONFIG_FTDI_COMPLETE),);
+      break;
+      #endif
+  #endif
+
+      TU_ATTR_FALLTHROUGH;
+    }
+
+    case CONFIG_FTDI_COMPLETE:
+      set_config_complete(p_cdc, idx, itf_num);
+      break;
+
+    default:
+      break;
+  }
+}
+
+#endif
+
+//--------------------------------------------------------------------+
+// CP210x
+//--------------------------------------------------------------------+
+
+#if CFG_TUH_CDC_CP210X
+
+static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST };
+enum {
+  CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])
+};
+
+static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+  // CP210x Interface includes 1 vendor interface + 2 bulk endpoints
+  TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2);
+  TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY(p_cdc);
+
+  p_cdc->serial_protocol = SERIAL_PROTOCOL_CP210X;
+
+  // endpoint pair
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  return open_ep_stream_pair(p_cdc, desc_ep);
+}
+
+#endif
+
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
@@ -324,10 +552,8 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
 
   TU_LOG_CDCH("CDC Set Control Line State\r\n");
 
-  tusb_control_request_t request;
-
   if(p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM ) {
-    tusb_control_request_t const acm_request = {
+    tusb_control_request_t const request = {
       .bmRequestType_bit = {
         .recipient = TUSB_REQ_RCPT_INTERFACE,
         .type      = TUSB_REQ_TYPE_CLASS,
@@ -339,43 +565,27 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
       .wLength  = 0
     };
 
-    request = acm_request;
+    p_cdc->user_control_cb = complete_cb;
+    tuh_xfer_t xfer = {
+      .daddr       = p_cdc->daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = NULL,
+      .complete_cb = cdch_internal_control_complete,
+      .user_data   = user_data
+    };
+
+    TU_ASSERT(tuh_control_xfer(&xfer));
+    return true;
   }
   #if CFG_TUH_CDC_FTDI
   else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
-    // FTDI use vendor specific request to set control line state
-    tusb_control_request_t const ftdi_request = {
-      .bmRequestType_bit = {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_VENDOR,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = FTDI_SIO_MODEM_CTRL,
-      .wValue   = tu_htole16(0x0300 | line_state), // 0x0300 is DTR and RTS enable
-      .wIndex   = 0, // port
-      .wLength  = 0
-    };
-
-    request = ftdi_request;
+    return ftdi_sio_modem_ctrl(p_cdc, line_state, complete_cb, user_data);
   }
   #endif
   else {
     return false;
   }
-
-  p_cdc->user_control_cb = complete_cb;
-  tuh_xfer_t xfer = {
-    .daddr       = p_cdc->daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = cdch_internal_control_complete,
-    .user_data   = user_data
-  };
-
-  TU_ASSERT(tuh_control_xfer(&xfer));
-
-  return true;
 }
 
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
@@ -385,11 +595,8 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
 
   TU_LOG_CDCH("CDC Set Line Conding\r\n");
 
-  tusb_control_request_t request;
-  uint8_t* enum_buf = NULL;
-
   if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) {
-    tusb_control_request_t const acm_request = {
+    tusb_control_request_t const request = {
       .bmRequestType_bit = {
         .recipient = TUSB_REQ_RCPT_INTERFACE,
         .type      = TUSB_REQ_TYPE_CLASS,
@@ -401,47 +608,32 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
       .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
     };
 
-    request = acm_request;
-
     // use usbh enum buf to hold line coding since user line_coding variable does not live long enough
-    enum_buf = usbh_get_enum_buf();
+    uint8_t* enum_buf = usbh_get_enum_buf();
     memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t));
+
+    p_cdc->user_control_cb = complete_cb;
+    tuh_xfer_t xfer = {
+      .daddr       = p_cdc->daddr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = enum_buf,
+      .complete_cb = cdch_internal_control_complete,
+      .user_data   = user_data
+    };
+
+    TU_ASSERT(tuh_control_xfer(&xfer));
+    return true;
   }
   #if CFG_TUH_CDC_FTDI
   else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
     // FTDI need to set baud rate and data bits, parity, stop bits separately
-    tusb_control_request_t const ftdi_request = {
-      .bmRequestType_bit = {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_VENDOR,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = FTDI_SIO_SET_BAUD_RATE,
-      .wValue   = 0x4138, // FIXME hardcoded to 9600 baud
-      .wIndex   = 0, // port
-      .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
-    };
-
-    request = ftdi_request;
+    return ftdi_sio_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data);
   }
   #endif
   else {
     return false;
   }
-
-  p_cdc->user_control_cb = complete_cb;
-  tuh_xfer_t xfer =
-  {
-    .daddr       = p_cdc->daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = enum_buf,
-    .complete_cb = cdch_internal_control_complete,
-    .user_data   = user_data
-  };
-
-  TU_ASSERT(tuh_control_xfer(&xfer));
-  return true;
 }
 
 //--------------------------------------------------------------------+
@@ -544,9 +736,6 @@ enum
   CONFIG_SET_CONTROL_LINE_STATE,
   CONFIG_SET_LINE_CODING,
   CONFIG_COMPLETE,
-
-  // FTDI
-  CONFIG_FTDI_RESET
 };
 
 static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep)
@@ -572,76 +761,14 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t c
   return true;
 }
 
-#if CFG_TUH_CDC_FTDI
-bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
-  // FTDI configuration includes 1 vendor interface + 2 bulk endpoints
-  TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2);
-  TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
-
-  cdch_interface_t * p_cdc = find_new_itf();
-  TU_VERIFY(p_cdc);
-
-  p_cdc->daddr              = daddr;
-  p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
-  p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
-  p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol;
-  p_cdc->line_state         = 0;
-  p_cdc->serial_protocol    = SERIAL_PROTOCOL_FTDI;
-
-  // endpoint pair
-  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
-
-  // data endpoints expected to be in pairs
-  TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep));
-
-  return true;
-}
-
-static bool ftdih_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  tusb_control_request_t const request = {
-    .bmRequestType_bit = {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_VENDOR,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = FTDI_SIO_RESET,
-    .wValue   = tu_htole16(FTDI_SIO_RESET_SIO),
-    .wIndex   = 0,
-    .wLength  = 0
-  };
-
-  p_cdc->user_control_cb = complete_cb;
-
-  tuh_xfer_t xfer = {
-    .daddr       = p_cdc->daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
-  };
-
-  TU_ASSERT(tuh_control_xfer(&xfer));
-  return true;
-}
-
-#endif
-
-
 static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
   uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len;
 
-  cdch_interface_t * p_cdc = find_new_itf();
+  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
 
-  p_cdc->daddr              = daddr;
-  p_cdc->bInterfaceNumber   = itf_desc->bInterfaceNumber;
-  p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass;
-  p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol;
-  p_cdc->line_state         = 0;
-  p_cdc->serial_protocol    = SERIAL_PROTOCOL_ACM;
+  p_cdc->serial_protocol = SERIAL_PROTOCOL_ACM;
 
   //------------- Control Interface -------------//
   uint8_t const * p_desc = tu_desc_next(itf_desc);
@@ -696,28 +823,47 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
   {
     return acm_open(daddr, itf_desc, max_len);
   }
+  #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X
   else if ( 0xff == itf_desc->bInterfaceClass )
   {
     uint16_t vid, pid;
     TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
 
-#if CFG_TUH_CDC_FTDI
+    #if CFG_TUH_CDC_FTDI
     if (TU_FTDI_VID == vid) {
-      uint16_t const ftdi_pids[] = {TU_FTDI_PID_LIST};
-      enum { FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0]) };
-
       for (size_t i = 0; i < FTDI_PID_COUNT; i++) {
         if (ftdi_pids[i] == pid) {
           return ftdih_open(daddr, itf_desc, max_len);
         }
       }
     }
-#endif
+    #endif
+
+    #if CFG_TUH_CDC_CP210X
+    if (TU_CP210X_VID == vid) {
+      for (size_t i = 0; i < CP210X_PID_COUNT; i++) {
+        if (cp210x_pids[i] == pid) {
+          return cp210x_open(daddr, itf_desc, max_len);
+        }
+      }
+    }
+    #endif
   }
+  #endif
 
   return false;
 }
 
+static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) {
+  if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
+
+  // Prepare for incoming data
+  tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
+
+  // notify usbh that driver enumeration is complete
+  usbh_driver_set_config_complete(p_cdc->daddr, itf_num);
+}
+
 static void process_cdc_config(tuh_xfer_t* xfer)
 {
   uintptr_t const state = xfer->user_data;
@@ -728,16 +874,9 @@ static void process_cdc_config(tuh_xfer_t* xfer)
 
   switch(state)
   {
-    #if CFG_TUH_CDC_FTDI
-    // Note may need to read FTDI eeprom
-    case CONFIG_FTDI_RESET:
-      TU_ASSERT(ftdih_sio_reset(p_cdc, process_cdc_config, CONFIG_SET_CONTROL_LINE_STATE), );
-      break;
-    #endif
-
     case CONFIG_SET_CONTROL_LINE_STATE:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      if (support_line_request(p_cdc))
+      if (p_cdc->acm_capability.support_line_request)
       {
         TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), );
         break;
@@ -747,7 +886,7 @@ static void process_cdc_config(tuh_xfer_t* xfer)
 
     case CONFIG_SET_LINE_CODING:
       #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      if (support_line_request(p_cdc))
+      if (p_cdc->acm_capability.support_line_request)
       {
         cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
         TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), );
@@ -757,14 +896,8 @@ static void process_cdc_config(tuh_xfer_t* xfer)
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_COMPLETE:
-      if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
-
-      // Prepare for incoming data
-      tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
-
-      // notify usbh that driver enumeration is complete
       // itf_num+1 to account for data interface as well
-      usbh_driver_set_config_complete(xfer->daddr, itf_num+1);
+      set_config_complete(p_cdc, idx, itf_num+1);
     break;
 
     default: break;
@@ -789,19 +922,25 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
   switch (p_cdc->serial_protocol) {
     case SERIAL_PROTOCOL_ACM:
       xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE;
+      process_cdc_config(&xfer);
       break;
 
-  #if CFG_TUH_CDC_FTDI
+    #if CFG_TUH_CDC_FTDI
     case SERIAL_PROTOCOL_FTDI:
       xfer.user_data = CONFIG_FTDI_RESET;
+      process_ftdi_config(&xfer);
       break;
-  #endif
+    #endif
+
+    #if CFG_TUH_CDC_CP210X
+    case SERIAL_PROTOCOL_CP210X:
+      //xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE;
+      break;
+    #endif
 
       default: return false;
   }
 
-  process_cdc_config(&xfer);
-
   return true;
 }
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index a372e9950..4f3f3a985 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -440,10 +440,15 @@
 #endif
 
 #ifndef CFG_TUH_CDC_FTDI
-  // FTDI is not part of CDC class, CDC is used for Serial-over-USB here
+  // FTDI is not part of CDC class, only to re-use CDC driver API
   #define CFG_TUH_CDC_FTDI 0
 #endif
 
+#ifndef CFG_TUH_CDC_CP210X
+  // CP210X is not part of CDC class, only to re-use CDC driver API
+  #define CFG_TUH_CDC_CP210X 0
+#endif
+
 #ifndef CFG_TUH_HID
 #define CFG_TUH_HID    0
 #endif

From 9698a088db7616eb628b47457f717574221c9153 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Apr 2023 15:29:44 +0700
Subject: [PATCH 1669/2085] refactor acm function

---
 src/class/cdc/cdc_host.c | 138 +++++++++++++++++++++------------------
 1 file changed, 73 insertions(+), 65 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index fc7a7a038..00a86888c 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -545,38 +545,42 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
   xfer->complete_cb(xfer);
 }
 
+static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
+    .wValue   = tu_htole16(line_state),
+    .wIndex   = tu_htole16((uint16_t) p_cdc->bInterfaceNumber),
+    .wLength  = 0
+  };
+
+  p_cdc->user_control_cb = complete_cb;
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = NULL,
+    .complete_cb = cdch_internal_control_complete,
+    .user_data   = user_data
+  };
+
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
+}
+
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && support_line_request(p_cdc));
-
   TU_LOG_CDCH("CDC Set Control Line State\r\n");
 
   if(p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM ) {
-    tusb_control_request_t const request = {
-      .bmRequestType_bit = {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
-      .wValue   = tu_htole16(line_state),
-      .wIndex   = tu_htole16((uint16_t) p_cdc->bInterfaceNumber),
-      .wLength  = 0
-    };
-
-    p_cdc->user_control_cb = complete_cb;
-    tuh_xfer_t xfer = {
-      .daddr       = p_cdc->daddr,
-      .ep_addr     = 0,
-      .setup       = &request,
-      .buffer      = NULL,
-      .complete_cb = cdch_internal_control_complete,
-      .user_data   = user_data
-    };
-
-    TU_ASSERT(tuh_control_xfer(&xfer));
-    return true;
+    return acm_set_control_line_state(p_cdc, line_state, complete_cb, user_data);
   }
   #if CFG_TUH_CDC_FTDI
   else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
@@ -588,42 +592,45 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
   }
 }
 
+bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = CDC_REQUEST_SET_LINE_CODING,
+    .wValue   = 0,
+    .wIndex   = tu_htole16(p_cdc->bInterfaceNumber),
+    .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
+  };
+
+  // use usbh enum buf to hold line coding since user line_coding variable does not live long enough
+  uint8_t* enum_buf = usbh_get_enum_buf();
+  memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t));
+
+  p_cdc->user_control_cb = complete_cb;
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = enum_buf,
+    .complete_cb = cdch_internal_control_complete,
+    .user_data   = user_data
+  };
+
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
+}
+
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && support_line_request(p_cdc));
-
   TU_LOG_CDCH("CDC Set Line Conding\r\n");
 
   if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) {
-    tusb_control_request_t const request = {
-      .bmRequestType_bit = {
-        .recipient = TUSB_REQ_RCPT_INTERFACE,
-        .type      = TUSB_REQ_TYPE_CLASS,
-        .direction = TUSB_DIR_OUT
-      },
-      .bRequest = CDC_REQUEST_SET_LINE_CODING,
-      .wValue   = 0,
-      .wIndex   = tu_htole16(p_cdc->bInterfaceNumber),
-      .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
-    };
-
-    // use usbh enum buf to hold line coding since user line_coding variable does not live long enough
-    uint8_t* enum_buf = usbh_get_enum_buf();
-    memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t));
-
-    p_cdc->user_control_cb = complete_cb;
-    tuh_xfer_t xfer = {
-      .daddr       = p_cdc->daddr,
-      .ep_addr     = 0,
-      .setup       = &request,
-      .buffer      = enum_buf,
-      .complete_cb = cdch_internal_control_complete,
-      .user_data   = user_data
-    };
-
-    TU_ASSERT(tuh_control_xfer(&xfer));
-    return true;
+    return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
   }
   #if CFG_TUH_CDC_FTDI
   else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
@@ -733,9 +740,9 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 enum
 {
   // ACM
-  CONFIG_SET_CONTROL_LINE_STATE,
-  CONFIG_SET_LINE_CODING,
-  CONFIG_COMPLETE,
+  CONFIG_ACM_SET_CONTROL_LINE_STATE,
+  CONFIG_ACM_SET_LINE_CODING,
+  CONFIG_ACM_COMPLETE,
 };
 
 static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep)
@@ -864,7 +871,7 @@ static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t i
   usbh_driver_set_config_complete(p_cdc->daddr, itf_num);
 }
 
-static void process_cdc_config(tuh_xfer_t* xfer)
+static void process_acm_config(tuh_xfer_t* xfer)
 {
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
@@ -874,28 +881,29 @@ static void process_cdc_config(tuh_xfer_t* xfer)
 
   switch(state)
   {
-    case CONFIG_SET_CONTROL_LINE_STATE:
+    case CONFIG_ACM_SET_CONTROL_LINE_STATE:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
       if (p_cdc->acm_capability.support_line_request)
       {
-        TU_ASSERT( tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cdc_config, CONFIG_SET_LINE_CODING), );
+        TU_ASSERT(tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_acm_config,
+                                                 CONFIG_ACM_SET_LINE_CODING), );
         break;
       }
       #endif
       TU_ATTR_FALLTHROUGH;
 
-    case CONFIG_SET_LINE_CODING:
+    case CONFIG_ACM_SET_LINE_CODING:
       #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
       if (p_cdc->acm_capability.support_line_request)
       {
         cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-        TU_ASSERT( tuh_cdc_set_line_coding(idx, &line_coding, process_cdc_config, CONFIG_COMPLETE), );
+        TU_ASSERT(tuh_cdc_set_line_coding(idx, &line_coding, process_acm_config, CONFIG_ACM_COMPLETE), );
         break;
       }
       #endif
       TU_ATTR_FALLTHROUGH;
 
-    case CONFIG_COMPLETE:
+    case CONFIG_ACM_COMPLETE:
       // itf_num+1 to account for data interface as well
       set_config_complete(p_cdc, idx, itf_num+1);
     break;
@@ -921,8 +929,8 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
 
   switch (p_cdc->serial_protocol) {
     case SERIAL_PROTOCOL_ACM:
-      xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE;
-      process_cdc_config(&xfer);
+      xfer.user_data = CONFIG_ACM_SET_CONTROL_LINE_STATE;
+      process_acm_config(&xfer);
       break;
 
     #if CFG_TUH_CDC_FTDI

From a32ef1cde124251d86696ed980a87eb25739c6a8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Apr 2023 16:32:42 +0700
Subject: [PATCH 1670/2085] more host serial refactor

---
 src/class/cdc/cdc_host.c | 112 ++++++++++++++++-----------------------
 1 file changed, 47 insertions(+), 65 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 00a86888c..c25ed48b0 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -154,14 +154,14 @@ enum {
 };
 
 enum {
-  CONFIG_FTDI_RESET,
+  CONFIG_FTDI_RESET = 0,
   CONFIG_FTDI_MODEM_CTRL,
   CONFIG_FTDI_SET_BAUDRATE,
   CONFIG_FTDI_SET_DATA,
   CONFIG_FTDI_COMPLETE
 };
 
-static bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) {
   // FTDI Interface includes 1 vendor interface + 2 bulk endpoints
   TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2);
   TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
@@ -169,6 +169,8 @@ static bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uin
   cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
 
+  TU_LOG_CDCH("FTDI opened\r\n");
+
   p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI;
 
   // endpoint pair
@@ -178,22 +180,19 @@ static bool ftdih_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uin
   return open_ep_stream_pair(p_cdc, desc_ep);
 }
 
-static bool ftdih_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
+static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   tusb_control_request_t const request = {
     .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_DEVICE,
       .type      = TUSB_REQ_TYPE_VENDOR,
       .direction = TUSB_DIR_OUT
     },
-    .bRequest = FTDI_SIO_RESET,
-    .wValue   = tu_htole16(FTDI_SIO_RESET_SIO),
+    .bRequest = command,
+    .wValue   = tu_htole16(value),
     .wIndex   = 0,
     .wLength  = 0
   };
 
-  p_cdc->user_control_cb = complete_cb;
-
   tuh_xfer_t xfer = {
     .daddr       = p_cdc->daddr,
     .ep_addr     = 0,
@@ -203,36 +202,19 @@ static bool ftdih_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb,
     .user_data   = user_data
   };
 
-  TU_ASSERT(tuh_control_xfer(&xfer));
+  return tuh_control_xfer(&xfer);
+}
+
+static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data));
   return true;
 }
 
 static bool ftdi_sio_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  tusb_control_request_t const request = {
-    .bmRequestType_bit = {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_VENDOR,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = FTDI_SIO_MODEM_CTRL,
-    .wValue   = tu_htole16(0x0300 | line_state), // 0x0300 is DTR and RTS enable
-    .wIndex   = 0, // port
-    .wLength  = 0
-  };
-
   p_cdc->user_control_cb = complete_cb;
-
-  tuh_xfer_t xfer = {
-    .daddr       = p_cdc->daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = cdch_internal_control_complete,
-    .user_data   = user_data
-  };
-
-  TU_ASSERT(tuh_control_xfer(&xfer));
+  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, cdch_internal_control_complete, user_data));
   return true;
 }
 
@@ -240,33 +222,10 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
 {
   // TODO baudrate to baud divisor
   (void) baudrate;
-
   uint16_t divisor = 0x4138; // FIXME hardcoded to 9600 baud
 
-  tusb_control_request_t const request = {
-    .bmRequestType_bit = {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_VENDOR,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = FTDI_SIO_SET_BAUD_RATE,
-    .wValue   = tu_htole16(divisor),
-    .wIndex   = 0, // port
-    .wLength  = 0
-  };
-
   p_cdc->user_control_cb = complete_cb;
-
-  tuh_xfer_t xfer = {
-    .daddr       = p_cdc->daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = cdch_internal_control_complete,
-    .user_data   = user_data
-  };
-
-  TU_ASSERT(tuh_control_xfer(&xfer));
+  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data));
   return true;
 }
 
@@ -280,7 +239,7 @@ static void process_ftdi_config(tuh_xfer_t* xfer) {
   switch(state) {
     // Note may need to read FTDI eeprom
     case CONFIG_FTDI_RESET:
-      TU_ASSERT(ftdih_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),);
+      TU_ASSERT(ftdi_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),);
       break;
 
     case CONFIG_FTDI_MODEM_CTRL:
@@ -335,6 +294,13 @@ enum {
   CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])
 };
 
+enum {
+  CONFIG_CP210X_IFC_ENABLE = 0,
+  CONFIG_CP210X_SET_BAUDRATE,
+  CONFIG_CP210X_SET_LINE_CTL,
+  CONFIG_CP210X_SET_MHS
+};
+
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
   // CP210x Interface includes 1 vendor interface + 2 bulk endpoints
   TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2);
@@ -343,6 +309,7 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui
   cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
 
+  TU_LOG_CDCH("CP210x opened\r\n");
   p_cdc->serial_protocol = SERIAL_PROTOCOL_CP210X;
 
   // endpoint pair
@@ -352,6 +319,22 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui
   return open_ep_stream_pair(p_cdc, desc_ep);
 }
 
+static void process_cp210x_config(tuh_xfer_t* xfer) {
+  uintptr_t const state   = xfer->user_data;
+  uint8_t const   itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t const   idx     = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t *p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc,);
+
+  switch (state) {
+    case CONFIG_CP210X_IFC_ENABLE:
+
+      break;
+
+    default: break;
+  }
+}
+
 #endif
 
 //--------------------------------------------------------------------+
@@ -740,7 +723,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 enum
 {
   // ACM
-  CONFIG_ACM_SET_CONTROL_LINE_STATE,
+  CONFIG_ACM_SET_CONTROL_LINE_STATE = 0,
   CONFIG_ACM_SET_LINE_CODING,
   CONFIG_ACM_COMPLETE,
 };
@@ -840,7 +823,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
     if (TU_FTDI_VID == vid) {
       for (size_t i = 0; i < FTDI_PID_COUNT; i++) {
         if (ftdi_pids[i] == pid) {
-          return ftdih_open(daddr, itf_desc, max_len);
+          return ftdi_open(daddr, itf_desc, max_len);
         }
       }
     }
@@ -918,9 +901,10 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
   request.wIndex = tu_htole16((uint16_t) itf_num);
 
   tuh_xfer_t xfer;
-  xfer.daddr     = daddr;
-  xfer.result    = XFER_RESULT_SUCCESS;
-  xfer.setup     = &request;
+  xfer.daddr  = daddr;
+  xfer.result = XFER_RESULT_SUCCESS;
+  xfer.setup  = &request;
+  xfer.user_data = 0;
 
   // fake transfer to kick-off process
   uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num);
@@ -929,20 +913,18 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
 
   switch (p_cdc->serial_protocol) {
     case SERIAL_PROTOCOL_ACM:
-      xfer.user_data = CONFIG_ACM_SET_CONTROL_LINE_STATE;
       process_acm_config(&xfer);
       break;
 
     #if CFG_TUH_CDC_FTDI
     case SERIAL_PROTOCOL_FTDI:
-      xfer.user_data = CONFIG_FTDI_RESET;
       process_ftdi_config(&xfer);
       break;
     #endif
 
     #if CFG_TUH_CDC_CP210X
     case SERIAL_PROTOCOL_CP210X:
-      //xfer.user_data = CONFIG_SET_CONTROL_LINE_STATE;
+      process_cp210x_config(&xfer);
       break;
     #endif
 

From 86f6fd17edec73c6c7f19ece19fe1dba8575985a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Apr 2023 17:09:21 +0700
Subject: [PATCH 1671/2085] cp210x seems to work well

---
 examples/host/cdc_msc_hid/src/tusb_config.h |  3 +-
 src/class/cdc/cdc_host.c                    | 93 +++++++++++++++++++--
 2 files changed, 89 insertions(+), 7 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 2baf2b1ac..cc3775a76 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -97,7 +97,8 @@
 
 #define CFG_TUH_HUB                 1 // number of supported hubs
 #define CFG_TUH_CDC                 1 // CDC ACM
-#define CFG_TUH_CDC_FTDI            1 // FTDI UART
+#define CFG_TUH_CDC_FTDI            1 // FTDI Serial
+#define CFG_TUH_CDC_CP210X          1 // CP210x Serial
 #define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index c25ed48b0..a19f66181 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -180,6 +180,7 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint
   return open_ep_stream_pair(p_cdc, desc_ep);
 }
 
+// set request without data
 static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   tusb_control_request_t const request = {
     .bmRequestType_bit = {
@@ -207,11 +208,10 @@ static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint1
 
 static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data));
-  return true;
+  return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
 }
 
-static bool ftdi_sio_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, cdch_internal_control_complete, user_data));
@@ -244,7 +244,8 @@ static void process_ftdi_config(tuh_xfer_t* xfer) {
 
     case CONFIG_FTDI_MODEM_CTRL:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(ftdi_sio_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),);
+      TU_ASSERT(
+        ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -298,7 +299,8 @@ enum {
   CONFIG_CP210X_IFC_ENABLE = 0,
   CONFIG_CP210X_SET_BAUDRATE,
   CONFIG_CP210X_SET_LINE_CTL,
-  CONFIG_CP210X_SET_MHS
+  CONFIG_CP210X_SET_DTR_RTS,
+  CONFIG_CP210X_COMPLETE
 };
 
 static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
@@ -319,6 +321,54 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui
   return open_ep_stream_pair(p_cdc, desc_ep);
 }
 
+static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_VENDOR,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = command,
+    .wValue   = tu_htole16(value),
+    .wIndex   = p_cdc->bInterfaceNumber,
+    .wLength  = tu_htole16(length)
+  };
+
+  // use usbh enum buf since application variable does not live long enough
+  uint8_t* enum_buf = NULL;
+
+  if (buffer && length > 0) {
+    enum_buf = usbh_get_enum_buf();
+    tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
+  }
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = enum_buf,
+    .complete_cb = complete_cb,
+    .user_data   = user_data
+  };
+
+  return tuh_control_xfer(&xfer);
+}
+
+static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data);
+}
+
+static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  baudrate = tu_htole32(baudrate);
+  return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baudrate, 4, complete_cb, user_data);
+}
+
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  p_cdc->user_control_cb = complete_cb;
+  return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, cdch_internal_control_complete, user_data);
+}
+
 static void process_cp210x_config(tuh_xfer_t* xfer) {
   uintptr_t const state   = xfer->user_data;
   uint8_t const   itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
@@ -328,7 +378,38 @@ static void process_cp210x_config(tuh_xfer_t* xfer) {
 
   switch (state) {
     case CONFIG_CP210X_IFC_ENABLE:
+      TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, process_cp210x_config, CONFIG_CP210X_SET_BAUDRATE),);
+      break;
 
+    case CONFIG_CP210X_SET_BAUDRATE: {
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, process_cp210x_config, CONFIG_CP210X_SET_LINE_CTL),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+    }
+
+    case CONFIG_CP210X_SET_LINE_CTL: {
+      #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+    }
+
+    case CONFIG_CP210X_SET_DTR_RTS:
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+      TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cp210x_config, CONFIG_CP210X_COMPLETE),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+
+    case CONFIG_CP210X_COMPLETE:
+      set_config_complete(p_cdc, idx, itf_num);
       break;
 
     default: break;
@@ -567,7 +648,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
   }
   #if CFG_TUH_CDC_FTDI
   else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
-    return ftdi_sio_modem_ctrl(p_cdc, line_state, complete_cb, user_data);
+    return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data);
   }
   #endif
   else {

From 438387be8c308c3bfed1ca952f5908a51a97b5c2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Apr 2023 17:32:56 +0700
Subject: [PATCH 1672/2085] more refactor

---
 examples/host/cdc_msc_hid/src/tusb_config.h |   4 +-
 src/class/cdc/cdc_host.c                    | 595 +++++++++++---------
 2 files changed, 317 insertions(+), 282 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index cc3775a76..abb75f068 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -97,8 +97,8 @@
 
 #define CFG_TUH_HUB                 1 // number of supported hubs
 #define CFG_TUH_CDC                 1 // CDC ACM
-#define CFG_TUH_CDC_FTDI            1 // FTDI Serial
-#define CFG_TUH_CDC_CP210X          1 // CP210x Serial
+#define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
 #define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
 #define CFG_TUH_MSC                 1
 #define CFG_TUH_VENDOR              0
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index a19f66181..f47ac4f10 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -143,281 +143,35 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t c
 static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num);
 static void cdch_internal_control_complete(tuh_xfer_t* xfer);
 
-//--------------------------------------------------------------------+
-// FTDI
-//--------------------------------------------------------------------+
+//------------- FTDI prototypes -------------//
 #if CFG_TUH_CDC_FTDI
-
 static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST };
 enum {
   FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
 };
 
-enum {
-  CONFIG_FTDI_RESET = 0,
-  CONFIG_FTDI_MODEM_CTRL,
-  CONFIG_FTDI_SET_BAUDRATE,
-  CONFIG_FTDI_SET_DATA,
-  CONFIG_FTDI_COMPLETE
-};
-
-static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) {
-  // FTDI Interface includes 1 vendor interface + 2 bulk endpoints
-  TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2);
-  TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
-
-  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
-  TU_VERIFY(p_cdc);
-
-  TU_LOG_CDCH("FTDI opened\r\n");
-
-  p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI;
-
-  // endpoint pair
-  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
-
-  // data endpoints expected to be in pairs
-  return open_ep_stream_pair(p_cdc, desc_ep);
-}
-
-// set request without data
-static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  tusb_control_request_t const request = {
-    .bmRequestType_bit = {
-      .recipient = TUSB_REQ_RCPT_DEVICE,
-      .type      = TUSB_REQ_TYPE_VENDOR,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = command,
-    .wValue   = tu_htole16(value),
-    .wIndex   = 0,
-    .wLength  = 0
-  };
-
-  tuh_xfer_t xfer = {
-    .daddr       = p_cdc->daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
-  };
-
-  return tuh_control_xfer(&xfer);
-}
-
-static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
-}
-
-static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  p_cdc->user_control_cb = complete_cb;
-  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, cdch_internal_control_complete, user_data));
-  return true;
-}
-
-static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  // TODO baudrate to baud divisor
-  (void) baudrate;
-  uint16_t divisor = 0x4138; // FIXME hardcoded to 9600 baud
-
-  p_cdc->user_control_cb = complete_cb;
-  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data));
-  return true;
-}
-
-static void process_ftdi_config(tuh_xfer_t* xfer) {
-  uintptr_t const state = xfer->user_data;
-  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t * p_cdc = get_itf(idx);
-  TU_ASSERT(p_cdc, );
-
-  switch(state) {
-    // Note may need to read FTDI eeprom
-    case CONFIG_FTDI_RESET:
-      TU_ASSERT(ftdi_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),);
-      break;
-
-    case CONFIG_FTDI_MODEM_CTRL:
-      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(
-        ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),);
-      break;
-      #else
-      TU_ATTR_FALLTHROUGH;
-      #endif
-
-    case CONFIG_FTDI_SET_BAUDRATE: {
-      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-      TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, process_ftdi_config, CONFIG_FTDI_SET_DATA),);
-      break;
-      #else
-      TU_ATTR_FALLTHROUGH;
-      #endif
-    }
-
-    case CONFIG_FTDI_SET_DATA: {
-  #if 0 // TODO set data format
-      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-      TU_ASSERT(ftdi_sio_set_data(p_cdc, process_ftdi_config, CONFIG_FTDI_COMPLETE),);
-      break;
-      #endif
-  #endif
-
-      TU_ATTR_FALLTHROUGH;
-    }
-
-    case CONFIG_FTDI_COMPLETE:
-      set_config_complete(p_cdc, idx, itf_num);
-      break;
-
-    default:
-      break;
-  }
-}
+static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
+static void process_ftdi_config(tuh_xfer_t* xfer);
 
+static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
-//--------------------------------------------------------------------+
-// CP210x
-//--------------------------------------------------------------------+
-
+//------------- CP210X prototypes -------------//
 #if CFG_TUH_CDC_CP210X
-
 static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST };
 enum {
   CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])
 };
 
-enum {
-  CONFIG_CP210X_IFC_ENABLE = 0,
-  CONFIG_CP210X_SET_BAUDRATE,
-  CONFIG_CP210X_SET_LINE_CTL,
-  CONFIG_CP210X_SET_DTR_RTS,
-  CONFIG_CP210X_COMPLETE
-};
-
-static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
-  // CP210x Interface includes 1 vendor interface + 2 bulk endpoints
-  TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2);
-  TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
-
-  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
-  TU_VERIFY(p_cdc);
-
-  TU_LOG_CDCH("CP210x opened\r\n");
-  p_cdc->serial_protocol = SERIAL_PROTOCOL_CP210X;
-
-  // endpoint pair
-  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
-
-  // data endpoints expected to be in pairs
-  return open_ep_stream_pair(p_cdc, desc_ep);
-}
-
-static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  tusb_control_request_t const request = {
-    .bmRequestType_bit = {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_VENDOR,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = command,
-    .wValue   = tu_htole16(value),
-    .wIndex   = p_cdc->bInterfaceNumber,
-    .wLength  = tu_htole16(length)
-  };
-
-  // use usbh enum buf since application variable does not live long enough
-  uint8_t* enum_buf = NULL;
-
-  if (buffer && length > 0) {
-    enum_buf = usbh_get_enum_buf();
-    tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
-  }
-
-  tuh_xfer_t xfer = {
-    .daddr       = p_cdc->daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = enum_buf,
-    .complete_cb = complete_cb,
-    .user_data   = user_data
-  };
-
-  return tuh_control_xfer(&xfer);
-}
-
-static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data);
-}
-
-static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  baudrate = tu_htole32(baudrate);
-  return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baudrate, 4, complete_cb, user_data);
-}
-
-static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  p_cdc->user_control_cb = complete_cb;
-  return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, cdch_internal_control_complete, user_data);
-}
-
-static void process_cp210x_config(tuh_xfer_t* xfer) {
-  uintptr_t const state   = xfer->user_data;
-  uint8_t const   itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
-  uint8_t const   idx     = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
-  cdch_interface_t *p_cdc = get_itf(idx);
-  TU_ASSERT(p_cdc,);
-
-  switch (state) {
-    case CONFIG_CP210X_IFC_ENABLE:
-      TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, process_cp210x_config, CONFIG_CP210X_SET_BAUDRATE),);
-      break;
-
-    case CONFIG_CP210X_SET_BAUDRATE: {
-      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
-      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-      TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, process_cp210x_config, CONFIG_CP210X_SET_LINE_CTL),);
-      break;
-      #else
-      TU_ATTR_FALLTHROUGH;
-      #endif
-    }
-
-    case CONFIG_CP210X_SET_LINE_CTL: {
-      #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now
-      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-      break;
-      #else
-      TU_ATTR_FALLTHROUGH;
-      #endif
-    }
-
-    case CONFIG_CP210X_SET_DTR_RTS:
-      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cp210x_config, CONFIG_CP210X_COMPLETE),);
-      break;
-      #else
-      TU_ATTR_FALLTHROUGH;
-      #endif
-
-    case CONFIG_CP210X_COMPLETE:
-      set_config_complete(p_cdc, idx, itf_num);
-      break;
-
-    default: break;
-  }
-}
+static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+static void process_cp210x_config(tuh_xfer_t* xfer);
 
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 #endif
 
+
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
@@ -610,6 +364,7 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
 }
 
 static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_CDCH("CDC ACM Set Control Line State\r\n");
   tusb_control_request_t const request = {
     .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_INTERFACE,
@@ -641,18 +396,23 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
 {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && support_line_request(p_cdc));
-  TU_LOG_CDCH("CDC Set Control Line State\r\n");
 
-  if(p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM ) {
-    return acm_set_control_line_state(p_cdc, line_state, complete_cb, user_data);
-  }
-  #if CFG_TUH_CDC_FTDI
-  else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
-    return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data);
-  }
-  #endif
-  else {
-    return false;
+  switch(p_cdc->serial_protocol) {
+    case SERIAL_PROTOCOL_ACM:
+      return acm_set_control_line_state(p_cdc, line_state, complete_cb, user_data);
+
+    #if CFG_TUH_CDC_FTDI
+    case SERIAL_PROTOCOL_FTDI:
+      return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data);
+    #endif
+
+    #if CFG_TUH_CDC_CP210X
+    case SERIAL_PROTOCOL_CP210X:
+      return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data);
+    #endif
+
+    default:
+      return false;
   }
 }
 
@@ -693,17 +453,22 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
   TU_VERIFY(p_cdc && support_line_request(p_cdc));
   TU_LOG_CDCH("CDC Set Line Conding\r\n");
 
-  if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) {
-    return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
-  }
-  #if CFG_TUH_CDC_FTDI
-  else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
-    // FTDI need to set baud rate and data bits, parity, stop bits separately
-    return ftdi_sio_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data);
-  }
-  #endif
-  else {
-    return false;
+  switch(p_cdc->serial_protocol) {
+    case SERIAL_PROTOCOL_ACM:
+      return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
+
+    #if CFG_TUH_CDC_FTDI
+    case SERIAL_PROTOCOL_FTDI:
+      // FTDI need to set baud rate and data bits, parity, stop bits separately
+      return ftdi_sio_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data);
+    #endif
+
+    #if CFG_TUH_CDC_CP210X
+    case SERIAL_PROTOCOL_CP210X:
+      return cp210x_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data);
+    #endif
+
+    default: return false;
   }
 }
 
@@ -949,7 +714,7 @@ static void process_acm_config(tuh_xfer_t* xfer)
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
       if (p_cdc->acm_capability.support_line_request)
       {
-        TU_ASSERT(tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_acm_config,
+        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_acm_config,
                                                  CONFIG_ACM_SET_LINE_CODING), );
         break;
       }
@@ -1015,4 +780,274 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
   return true;
 }
 
+//--------------------------------------------------------------------+
+// FTDI
+//--------------------------------------------------------------------+
+#if CFG_TUH_CDC_FTDI
+
+enum {
+  CONFIG_FTDI_RESET = 0,
+  CONFIG_FTDI_MODEM_CTRL,
+  CONFIG_FTDI_SET_BAUDRATE,
+  CONFIG_FTDI_SET_DATA,
+  CONFIG_FTDI_COMPLETE
+};
+
+static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) {
+  // FTDI Interface includes 1 vendor interface + 2 bulk endpoints
+  TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2);
+  TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY(p_cdc);
+
+  TU_LOG_CDCH("FTDI opened\r\n");
+
+  p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI;
+
+  // endpoint pair
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  return open_ep_stream_pair(p_cdc, desc_ep);
+}
+
+// set request without data
+static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_DEVICE,
+      .type      = TUSB_REQ_TYPE_VENDOR,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = command,
+    .wValue   = tu_htole16(value),
+    .wIndex   = 0,
+    .wLength  = 0
+  };
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = NULL,
+    .complete_cb = complete_cb,
+    .user_data   = user_data
+  };
+
+  return tuh_control_xfer(&xfer);
+}
+
+static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data);
+}
+
+static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  TU_LOG_CDCH("CDC FTDI Set Control Line State\r\n");
+  p_cdc->user_control_cb = complete_cb;
+  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, cdch_internal_control_complete, user_data));
+  return true;
+}
+
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  // TODO baudrate to baud divisor
+  (void) baudrate;
+  uint16_t divisor = 0x4138; // FIXME hardcoded to 9600 baud
+
+  TU_LOG_CDCH("CDC FTDI Set BaudRate = %u, divisor = %u\n", baudrate, divisor);
+
+  p_cdc->user_control_cb = complete_cb;
+  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data));
+  return true;
+}
+
+static void process_ftdi_config(tuh_xfer_t* xfer) {
+  uintptr_t const state = xfer->user_data;
+  uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t * p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc, );
+
+  switch(state) {
+    // Note may need to read FTDI eeprom
+    case CONFIG_FTDI_RESET:
+      TU_ASSERT(ftdi_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),);
+      break;
+
+    case CONFIG_FTDI_MODEM_CTRL:
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+      TU_ASSERT(
+        ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+
+    case CONFIG_FTDI_SET_BAUDRATE: {
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, process_ftdi_config, CONFIG_FTDI_SET_DATA),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+    }
+
+    case CONFIG_FTDI_SET_DATA: {
+      #if 0 // TODO set data format
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      TU_ASSERT(ftdi_sio_set_data(p_cdc, process_ftdi_config, CONFIG_FTDI_COMPLETE),);
+      break;
+      #endif
+      #endif
+
+      TU_ATTR_FALLTHROUGH;
+    }
+
+    case CONFIG_FTDI_COMPLETE:
+      set_config_complete(p_cdc, idx, itf_num);
+      break;
+
+    default:
+      break;
+  }
+}
+
+#endif
+
+//--------------------------------------------------------------------+
+// CP210x
+//--------------------------------------------------------------------+
+
+#if CFG_TUH_CDC_CP210X
+
+enum {
+  CONFIG_CP210X_IFC_ENABLE = 0,
+  CONFIG_CP210X_SET_BAUDRATE,
+  CONFIG_CP210X_SET_LINE_CTL,
+  CONFIG_CP210X_SET_DTR_RTS,
+  CONFIG_CP210X_COMPLETE
+};
+
+static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+  // CP210x Interface includes 1 vendor interface + 2 bulk endpoints
+  TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2);
+  TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len);
+
+  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY(p_cdc);
+
+  TU_LOG_CDCH("CP210x opened\r\n");
+  p_cdc->serial_protocol = SERIAL_PROTOCOL_CP210X;
+
+  // endpoint pair
+  tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+
+  // data endpoints expected to be in pairs
+  return open_ep_stream_pair(p_cdc, desc_ep);
+}
+
+static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_VENDOR,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = command,
+    .wValue   = tu_htole16(value),
+    .wIndex   = p_cdc->bInterfaceNumber,
+    .wLength  = tu_htole16(length)
+  };
+
+  // use usbh enum buf since application variable does not live long enough
+  uint8_t* enum_buf = NULL;
+
+  if (buffer && length > 0) {
+    enum_buf = usbh_get_enum_buf();
+    tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length);
+  }
+
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = enum_buf,
+    .complete_cb = complete_cb,
+    .user_data   = user_data
+  };
+
+  return tuh_control_xfer(&xfer);
+}
+
+static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data);
+}
+
+static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_CDCH("CDC CP210x Set BaudRate = %u\n", baudrate);
+  baudrate = tu_htole32(baudrate);
+  return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baudrate, 4, complete_cb, user_data);
+}
+
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+{
+  TU_LOG_CDCH("CDC CP210x Set Control Line State\r\n");
+  p_cdc->user_control_cb = complete_cb;
+  return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, cdch_internal_control_complete, user_data);
+}
+
+static void process_cp210x_config(tuh_xfer_t* xfer) {
+  uintptr_t const state   = xfer->user_data;
+  uint8_t const   itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
+  uint8_t const   idx     = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
+  cdch_interface_t *p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc,);
+
+  switch (state) {
+    case CONFIG_CP210X_IFC_ENABLE:
+      TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, process_cp210x_config, CONFIG_CP210X_SET_BAUDRATE),);
+      break;
+
+    case CONFIG_CP210X_SET_BAUDRATE: {
+      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, process_cp210x_config, CONFIG_CP210X_SET_LINE_CTL),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+    }
+
+    case CONFIG_CP210X_SET_LINE_CTL: {
+      #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now
+      cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+    }
+
+    case CONFIG_CP210X_SET_DTR_RTS:
+      #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
+      TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cp210x_config, CONFIG_CP210X_COMPLETE),);
+      break;
+      #else
+      TU_ATTR_FALLTHROUGH;
+      #endif
+
+    case CONFIG_CP210X_COMPLETE:
+      set_config_complete(p_cdc, idx, itf_num);
+      break;
+
+    default: break;
+  }
+}
+
+#endif
+
 #endif

From c10f52b2375de8cca153beffb7852877d4cd7e58 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Apr 2023 17:39:02 +0700
Subject: [PATCH 1673/2085] forgot to add cp210x header

---
 src/class/cdc/serial/cp210x.h | 64 +++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 src/class/cdc/serial/cp210x.h

diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h
new file mode 100644
index 000000000..b01417092
--- /dev/null
+++ b/src/class/cdc/serial/cp210x.h
@@ -0,0 +1,64 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TUSB_CP210X_H
+#define TUSB_CP210X_H
+
+// Protocol details can be found at AN571: CP210x Virtual COM Port Interface
+// https://www.silabs.com/documents/public/application-notes/AN571.pdf
+
+#define TU_CP210X_VID 0x10C4
+#define TU_CP210X_PID_LIST \
+  0xEA60, 0xEA70
+
+/* Config request codes */
+#define CP210X_IFC_ENABLE      0x00
+#define CP210X_SET_BAUDDIV     0x01
+#define CP210X_GET_BAUDDIV     0x02
+#define CP210X_SET_LINE_CTL    0x03 // Set parity, data bits, stop bits
+#define CP210X_GET_LINE_CTL    0x04
+#define CP210X_SET_BREAK       0x05
+#define CP210X_IMM_CHAR        0x06
+#define CP210X_SET_MHS         0x07 // Set DTR, RTS
+#define CP210X_GET_MDMSTS      0x08 // Get modem status (DTR, RTS, CTS, DSR, RI, DCD)
+#define CP210X_SET_XON         0x09
+#define CP210X_SET_XOFF        0x0A
+#define CP210X_SET_EVENTMASK   0x0B
+#define CP210X_GET_EVENTMASK   0x0C
+#define CP210X_SET_CHAR        0x0D
+#define CP210X_GET_CHARS       0x0E
+#define CP210X_GET_PROPS       0x0F
+#define CP210X_GET_COMM_STATUS 0x10
+#define CP210X_RESET           0x11
+#define CP210X_PURGE           0x12
+#define CP210X_SET_FLOW        0x13
+#define CP210X_GET_FLOW        0x14
+#define CP210X_EMBED_EVENTS    0x15
+#define CP210X_GET_EVENTSTATE  0x16
+#define CP210X_SET_CHARS       0x19
+#define CP210X_GET_BAUDRATE    0x1D
+#define CP210X_SET_BAUDRATE    0x1E
+#define CP210X_VENDOR_SPECIFIC 0xFF // GPIO, Recipient must be Device
+
+#endif //TUSB_CP210X_H

From 8214f0f497271116d07e874f2e5f764f1e8ebd47 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Apr 2023 17:40:08 +0700
Subject: [PATCH 1674/2085] clean up

---
 src/class/cdc/cdc_host.c | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index f47ac4f10..ab1a10427 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -33,14 +33,6 @@
 
 #include "cdc_host.h"
 
-#if CFG_TUH_CDC_FTDI
-  #include "serial/ftdi_sio.h"
-#endif
-
-#if CFG_TUH_CDC_CP210X
-  #include "serial/cp210x.h"
-#endif
-
 // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
 #define CDCH_DEBUG   2
 
@@ -145,6 +137,8 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer);
 
 //------------- FTDI prototypes -------------//
 #if CFG_TUH_CDC_FTDI
+#include "serial/ftdi_sio.h"
+
 static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST };
 enum {
   FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
@@ -159,6 +153,8 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
 
 //------------- CP210X prototypes -------------//
 #if CFG_TUH_CDC_CP210X
+#include "serial/cp210x.h"
+
 static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST };
 enum {
   CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])

From ee58278ed2502a6e9b6d2625f2fe1bf453038716 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Apr 2023 23:08:25 +0700
Subject: [PATCH 1675/2085] add code to calculate divisor from baudrate for
 ftdi

---
 src/class/cdc/cdc_host.c | 35 +++++++++++++++++++++++++++++------
 1 file changed, 29 insertions(+), 6 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index ab1a10427..132b1ef09 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -847,13 +847,36 @@ static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state
   return true;
 }
 
+static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base)
+{
+  const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 };
+  uint32_t divisor;
+
+  /* divisor shifted 3 bits to the left */
+  uint32_t divisor3 = base / (2 * baud);
+  divisor = (divisor3 >> 3);
+  divisor |= (uint32_t) divfrac[divisor3 & 0x7] << 14;
+
+  /* Deal with special cases for highest baud rates. */
+  if (divisor == 1) { /* 1.0 */
+    divisor = 0;
+  }
+  else if (divisor == 0x4001) { /* 1.5 */
+    divisor = 1;
+  }
+
+  return divisor;
+}
+
+static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud)
+{
+  return ftdi_232bm_baud_base_to_divisor(baud, 48000000u);
+}
+
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  // TODO baudrate to baud divisor
-  (void) baudrate;
-  uint16_t divisor = 0x4138; // FIXME hardcoded to 9600 baud
-
-  TU_LOG_CDCH("CDC FTDI Set BaudRate = %u, divisor = %u\n", baudrate, divisor);
+  uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
+  TU_LOG_CDCH("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data));
@@ -985,7 +1008,7 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe
 }
 
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  TU_LOG_CDCH("CDC CP210x Set BaudRate = %u\n", baudrate);
+  TU_LOG_CDCH("CDC CP210x Set BaudRate = %lu\n", baudrate);
   baudrate = tu_htole32(baudrate);
   return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baudrate, 4, complete_cb, user_data);
 }

From 732686cc109aea9527d3133c3b8e61dc045dc233 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Apr 2023 23:22:10 +0700
Subject: [PATCH 1676/2085] add tuh_cdc_set_baudrate()

---
 src/class/cdc/cdc_host.c | 43 +++++++++++++++++++++++++++++++---------
 src/class/cdc/cdc_host.h | 13 ++++++++----
 2 files changed, 43 insertions(+), 13 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 132b1ef09..4c87ff1ad 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -126,11 +126,6 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const
   return NULL;
 }
 
-static inline bool support_line_request(cdch_interface_t const* p_cdc) {
-  return (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM && p_cdc->acm_capability.support_line_request) ||
-          (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI);
-}
-
 static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep);
 static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num);
 static void cdch_internal_control_complete(tuh_xfer_t* xfer);
@@ -391,10 +386,11 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
-  TU_VERIFY(p_cdc && support_line_request(p_cdc));
+  TU_VERIFY(p_cdc);
 
   switch(p_cdc->serial_protocol) {
     case SERIAL_PROTOCOL_ACM:
+      TU_VERIFY(p_cdc->acm_capability.support_line_request);
       return acm_set_control_line_state(p_cdc, line_state, complete_cb, user_data);
 
     #if CFG_TUH_CDC_FTDI
@@ -413,6 +409,8 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
 }
 
 bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_CDCH("CDC ACM Set Line Conding\r\n");
+
   tusb_control_request_t const request = {
     .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_INTERFACE,
@@ -446,11 +444,11 @@ bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
-  TU_VERIFY(p_cdc && support_line_request(p_cdc));
-  TU_LOG_CDCH("CDC Set Line Conding\r\n");
+  TU_VERIFY(p_cdc);
 
   switch(p_cdc->serial_protocol) {
     case SERIAL_PROTOCOL_ACM:
+      TU_VERIFY(p_cdc->acm_capability.support_line_request);
       return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
 
     #if CFG_TUH_CDC_FTDI
@@ -468,6 +466,33 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
   }
 }
 
+bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc);
+
+  switch(p_cdc->serial_protocol) {
+    case SERIAL_PROTOCOL_ACM: {
+      TU_VERIFY(p_cdc->acm_capability.support_line_request);
+      cdc_line_coding_t line_coding = p_cdc->line_coding;
+      line_coding.bit_rate = baudrate;
+      return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data);
+    }
+
+    #if CFG_TUH_CDC_FTDI
+    case SERIAL_PROTOCOL_FTDI:
+      // FTDI need to set baud rate and data bits, parity, stop bits separately
+      return ftdi_sio_set_baudrate(p_cdc, baudrate, complete_cb, user_data);
+    #endif
+
+    #if CFG_TUH_CDC_CP210X
+    case SERIAL_PROTOCOL_CP210X:
+      return cp210x_set_baudrate(p_cdc, baudrate, complete_cb, user_data);
+    #endif
+
+    default: return false;
+  }
+}
+
 //--------------------------------------------------------------------+
 // CLASS-USBH API
 //--------------------------------------------------------------------+
@@ -722,7 +747,7 @@ static void process_acm_config(tuh_xfer_t* xfer)
       if (p_cdc->acm_capability.support_line_request)
       {
         cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-        TU_ASSERT(tuh_cdc_set_line_coding(idx, &line_coding, process_acm_config, CONFIG_ACM_COMPLETE), );
+        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, process_acm_config, CONFIG_ACM_COMPLETE), );
         break;
       }
       #endif
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index a1e78f158..971ebe2ae 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -140,22 +140,27 @@ bool tuh_cdc_read_clear (uint8_t idx);
 // Request to Set Control Line State: DTR (bit 0), RTS (bit 1)
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
-// Request to Set Line Coding
+// Request to set baudrate
+bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+// Request to Set Line Coding (ACM only)
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
-// Request to Get Line Coding
+// Request to Get Line Coding (ACM only)
 // Should only use if tuh_cdc_set_line_coding() / tuh_cdc_get_line_coding() never got invoked and
 // CFG_TUH_CDC_LINE_CODING_ON_ENUM is not defined
 // bool tuh_cdc_get_line_coding(uint8_t idx, cdc_line_coding_t* coding);
 
 // Connect by set both DTR, RTS
-static inline bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+TU_ATTR_ALWAYS_INLINE static inline
+bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   return tuh_cdc_set_control_line_state(idx, CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS, complete_cb, user_data);
 }
 
 // Disconnect by clear both DTR, RTS
-static inline bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
+TU_ATTR_ALWAYS_INLINE static inline
+bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data);
 }

From 8f4797663902cd445994ed48f2cd093161af68f2 Mon Sep 17 00:00:00 2001
From: Jean-Baptiste Theou <jb@thing.com>
Date: Thu, 27 Apr 2023 15:48:15 -1000
Subject: [PATCH 1677/2085] cdc: fix line_coding aligment

While calling tud_cdc_n_get_line_coding, the structure is copied into
the destination.

Dump of assembler code for function tud_cdc_n_get_line_coding:
   0x000193f4 <+0>:	mov.w	r2, #2112	@ 0x840
0x000193f8 <+4>:	ldr	r3, [pc, #20]	@ (0x19410
<tud_cdc_n_get_line_coding+28>)
   0x000193fa <+6>:	mla	r0, r2, r0, r3
=> 0x000193fe <+10>:	ldr.w	r3, [r0, #6]
   0x00019402 <+14>:	str	r3, [r1, #0]

On some platform (tested on LPC55S28), the address needs to be 4-bytes
aligned. Without this, the address is

(gdb) p &_cdcd_itf.line_coding
$3 = (cdc_line_coding_t *) 0x40100006 <_cdcd_itf+6>

which leads to a HardFault. With this fix

(gdb) p &_cdcd_itf.line_coding
$5 = (cdc_line_coding_t *) 0x40100008 <_cdcd_itf+8>

and the function can be called properly

Signed-off-by: Jean-Baptiste Theou <jb@thing.com>
---
 src/class/cdc/cdc_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index a82ef1d62..bf15d0d97 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -53,7 +53,7 @@ typedef struct
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
   char    wanted_char;
-  cdc_line_coding_t line_coding;
+  CFG_TUSB_MEM_ALIGN cdc_line_coding_t line_coding;
 
   // FIFO
   tu_fifo_t rx_ff;

From 190acc1fb0579d3e097ba2b0b96033740ecee26e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Apr 2023 11:12:03 +0700
Subject: [PATCH 1678/2085] add aligned(4) for cdc_line_coding_t

---
 src/class/cdc/cdc_device.c | 2 +-
 src/class/cdc/cdc_host.c   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index bf15d0d97..5adce521d 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -53,7 +53,7 @@ typedef struct
 
   /*------------- From this point, data is not cleared by bus reset -------------*/
   char    wanted_char;
-  CFG_TUSB_MEM_ALIGN cdc_line_coding_t line_coding;
+  TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding;
 
   // FIFO
   tu_fifo_t rx_ff;
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 4c87ff1ad..e2447d033 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -58,8 +58,8 @@ typedef struct {
   cdc_acm_capability_t acm_capability;
   uint8_t ep_notif;
 
-  cdc_line_coding_t line_coding;  // Baudrate, stop bits, parity, data width
-  uint8_t line_state;             // DTR (bit0), RTS (bit1)
+  uint8_t line_state;                               // DTR (bit0), RTS (bit1)
+  TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width
 
   tuh_xfer_cb_t user_control_cb;
 

From 090078542fd8b9a11d72163b11b99e7d25f63072 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Apr 2023 11:34:12 +0700
Subject: [PATCH 1679/2085] update osal note

---
 docs/contributing/porting.rst | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/contributing/porting.rst b/docs/contributing/porting.rst
index 9ec392661..f81d98782 100644
--- a/docs/contributing/porting.rst
+++ b/docs/contributing/porting.rst
@@ -62,14 +62,14 @@ Feel free to skip this until you want to verify your demo code is running. To im
 OS Abstraction Layer (OSAL)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-The OS Abstraction Layer is responsible for providing basic data structures for TinyUSB that may allow for concurrency when used with an RTOS. Without an RTOS it simply handles concurrency issues between the main code and interrupts.
+The OS Abstraction Layer is responsible for providing basic data structures for TinyUSB that may allow for concurrency when used with an RTOS. Without an RTOS it simply handles concurrency issues between the main code and interrupts. The code is almost entirely agnostic of MCU and lives in ``src/osal``.
 
-The code is almost entirely agnostic of MCU and lives in ``src/osal``.
+In RTOS configurations, tud_task()/tuh_task() blocks behind a synchronization structure when the event queue is empty, so that the scheduler may give the CPU to a different task. To take advantage of the library's capability to yield the CPU when there are no actionable USB device events, ensure that the `CFG_TUSB_OS` symbol is defined, e.g `OPT_OS_FREERTOS` enables the FreeRTOS scheduler to schedule other threads than that which calls `tud_task()/tuh_task()`.
 
 Device API
 ^^^^^^^^^^
 
-After the USB device is setup, the USB device code works by processing events on the main thread (by calling ``tud_task``\ ). In RTOS configurations, tud_task blocks behind a synchronization structure when the event queue is empty, so that the scheduler may give the CPU to a different task. To take advantage of the library's capability to yield the CPU when there are no actionable USB device events, ensure that the `CFG_TUSB_OS` symbol is defined in your modified ``tusb_config.h``. For example `#define CFG_TUSB_OS  OPT_OS_FREERTOS` enables the FreeRTOS scheduler to schedule other threads than that which calls `tud_task`. These events are queued by the USB interrupt handler. So, there are three parts to the device low-level API: device setup, endpoint setup and interrupt processing. 
+After the USB device is setup, the USB device code works by processing events on the main thread (by calling ``tud_task``\ ). These events are queued by the USB interrupt handler. So, there are three parts to the device low-level API: device setup, endpoint setup and interrupt processing.
 
 All of the code for the low-level device API is in ``src/portable/<vendor>/<chip family>/dcd_<chip family>.c``.
 

From 0a43a7b418dc9ba510505eef6abbc2da6f9151e5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Apr 2023 19:06:08 +0700
Subject: [PATCH 1680/2085] improve host serial drivers

- tuh_control_xfer() update xfer result to user_data if complete
callback = NULL (sync/blocking)
- refactor host serial driver for acm/ftdi/cp210x
---
 src/class/cdc/cdc_host.c | 638 ++++++++++++++++++++-------------------
 src/class/cdc/cdc_host.h |   6 +-
 src/host/usbh.c          |  56 +---
 3 files changed, 347 insertions(+), 353 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index e2447d033..b25bc5512 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -39,22 +39,16 @@
 #define TU_LOG_CDCH(...)   TU_LOG(CDCH_DEBUG, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
+// Host CDC Interface
 //--------------------------------------------------------------------+
 
-enum {
-  SERIAL_PROTOCOL_ACM = 0,
-  SERIAL_PROTOCOL_FTDI,
-  SERIAL_PROTOCOL_CP210X,
-};
-
 typedef struct {
   uint8_t daddr;
   uint8_t bInterfaceNumber;
   uint8_t bInterfaceSubClass;
   uint8_t bInterfaceProtocol;
 
-  uint8_t serial_protocol;
+  uint8_t serial_drid; // Serial Driver ID
   cdc_acm_capability_t acm_capability;
   uint8_t ep_notif;
 
@@ -76,13 +70,103 @@ typedef struct {
 
 } cdch_interface_t;
 
+CFG_TUH_MEM_SECTION
+static cdch_interface_t cdch_data[CFG_TUH_CDC];
+
+//--------------------------------------------------------------------+
+// Serial Driver
+//--------------------------------------------------------------------+
+
+//------------- ACM prototypes -------------//
+static void acm_process_config(tuh_xfer_t* xfer);
+
+static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+
+//------------- FTDI prototypes -------------//
+#if CFG_TUH_CDC_FTDI
+#include "serial/ftdi_sio.h"
+
+static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST };
+enum {
+  FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
+};
+
+// Store last request baudrate since divisor to baudrate is not easy
+static uint32_t _ftdi_requested_baud;
+
+static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
+static void ftdi_process_config(tuh_xfer_t* xfer);
+
+static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+#endif
+
+//------------- CP210X prototypes -------------//
+#if CFG_TUH_CDC_CP210X
+#include "serial/cp210x.h"
+
+static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST };
+enum {
+  CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])
+};
+
+static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+static void cp210x_process_config(tuh_xfer_t* xfer);
+
+static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+#endif
+
+enum {
+  SERIAL_DRIVER_ACM = 0,
+
+#if CFG_TUH_CDC_FTDI
+  SERIAL_DRIVER_FTDI,
+#endif
+
+#if CFG_TUH_CDC_CP210X
+  SERIAL_DRIVER_CP210X,
+#endif
+};
+
+typedef struct {
+  void (*const process_set_config)(tuh_xfer_t* xfer);
+  bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+  bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
+} cdch_serial_driver_t;
+
+// Note driver list must be in the same order as SERIAL_DRIVER enum
+static const cdch_serial_driver_t serial_drivers[] = {
+  { .process_set_config     = acm_process_config,
+    .set_control_line_state = acm_set_control_line_state,
+    .set_baudrate           = acm_set_baudrate
+  },
+
+  #if CFG_TUH_CDC_FTDI
+  { .process_set_config     = ftdi_process_config,
+    .set_control_line_state = ftdi_sio_set_modem_ctrl,
+    .set_baudrate           = ftdi_sio_set_baudrate
+  },
+  #endif
+
+  #if CFG_TUH_CDC_CP210X
+  { .process_set_config     = cp210x_process_config,
+    .set_control_line_state = cp210x_set_modem_ctrl,
+    .set_baudrate           = cp210x_set_baudrate
+  },
+  #endif
+};
+
+enum {
+  SERIAL_DRIVER_COUNT = sizeof(serial_drivers) / sizeof(serial_drivers[0])
+};
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-CFG_TUH_MEM_SECTION
-static cdch_interface_t cdch_data[CFG_TUH_CDC];
-
 static inline cdch_interface_t* get_itf(uint8_t idx)
 {
   TU_ASSERT(idx < CFG_TUH_CDC, NULL);
@@ -130,39 +214,6 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t c
 static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num);
 static void cdch_internal_control_complete(tuh_xfer_t* xfer);
 
-//------------- FTDI prototypes -------------//
-#if CFG_TUH_CDC_FTDI
-#include "serial/ftdi_sio.h"
-
-static uint16_t const ftdi_pids[] = { TU_FTDI_PID_LIST };
-enum {
-  FTDI_PID_COUNT = sizeof(ftdi_pids) / sizeof(ftdi_pids[0])
-};
-
-static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len);
-static void process_ftdi_config(tuh_xfer_t* xfer);
-
-static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-#endif
-
-//------------- CP210X prototypes -------------//
-#if CFG_TUH_CDC_CP210X
-#include "serial/cp210x.h"
-
-static uint16_t const cp210x_pids[] = { TU_CP210X_PID_LIST };
-enum {
-  CP210X_PID_COUNT = sizeof(cp210x_pids) / sizeof(cp210x_pids[0])
-};
-
-static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
-static void process_cp210x_config(tuh_xfer_t* xfer);
-
-static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
-#endif
-
-
 //--------------------------------------------------------------------+
 // APPLICATION API
 //--------------------------------------------------------------------+
@@ -322,175 +373,86 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
 
   if (xfer->result == XFER_RESULT_SUCCESS)
   {
-    if (p_cdc->serial_protocol == SERIAL_PROTOCOL_ACM) {
-      switch (xfer->setup->bRequest) {
-        case CDC_REQUEST_SET_CONTROL_LINE_STATE:
-          p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
-          break;
+    switch (p_cdc->serial_drid) {
+      case SERIAL_DRIVER_ACM:
+        switch (xfer->setup->bRequest) {
+          case CDC_REQUEST_SET_CONTROL_LINE_STATE:
+            p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue);
+            break;
 
-        case CDC_REQUEST_SET_LINE_CODING: {
-          uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
-          memcpy(&p_cdc->line_coding, xfer->buffer, len);
+          case CDC_REQUEST_SET_LINE_CODING: {
+            uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength));
+            memcpy(&p_cdc->line_coding, xfer->buffer, len);
+          }
+            break;
+
+          default: break;
         }
-          break;
+        break;
 
-        default: break;
-      }
-    }
-    #if CFG_TUH_CDC_FTDI
-    else if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
-      switch (xfer->setup->bRequest) {
-        case FTDI_SIO_MODEM_CTRL:
-          p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff);
-          break;
+      #if CFG_TUH_CDC_FTDI
+      case SERIAL_DRIVER_FTDI:
+        switch (xfer->setup->bRequest) {
+          case FTDI_SIO_MODEM_CTRL:
+            p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff);
+            break;
 
-        default: break;
-      }
+          case FTDI_SIO_SET_BAUD_RATE:
+            // convert from divisor to baudrate is not supported
+            p_cdc->line_coding.bit_rate = _ftdi_requested_baud;
+            break;
+
+          default: break;
+        }
+        break;
+      #endif
+
+      #if CFG_TUH_CDC_CP210X
+      case SERIAL_DRIVER_CP210X:
+        switch(xfer->setup->bRequest) {
+          case CP210X_SET_MHS:
+            p_cdc->line_state = (uint8_t) (tu_le16toh(xfer->setup->wValue) & 0x00ff);
+            break;
+
+          case CP210X_SET_BAUDRATE: {
+            uint32_t baudrate;
+            memcpy(&baudrate, xfer->buffer, sizeof(uint32_t));
+            p_cdc->line_coding.bit_rate = tu_le32toh(baudrate);
+          }
+            break;
+        }
+        break;
+      #endif
+
+      default: break;
     }
-    #endif
   }
 
   xfer->complete_cb = p_cdc->user_control_cb;
-  xfer->complete_cb(xfer);
-}
-
-static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  TU_LOG_CDCH("CDC ACM Set Control Line State\r\n");
-  tusb_control_request_t const request = {
-    .bmRequestType_bit = {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
-    .wValue   = tu_htole16(line_state),
-    .wIndex   = tu_htole16((uint16_t) p_cdc->bInterfaceNumber),
-    .wLength  = 0
-  };
-
-  p_cdc->user_control_cb = complete_cb;
-
-  tuh_xfer_t xfer = {
-    .daddr       = p_cdc->daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = NULL,
-    .complete_cb = cdch_internal_control_complete,
-    .user_data   = user_data
-  };
-
-  TU_ASSERT(tuh_control_xfer(&xfer));
-  return true;
-}
-
-bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
-{
-  cdch_interface_t* p_cdc = get_itf(idx);
-  TU_VERIFY(p_cdc);
-
-  switch(p_cdc->serial_protocol) {
-    case SERIAL_PROTOCOL_ACM:
-      TU_VERIFY(p_cdc->acm_capability.support_line_request);
-      return acm_set_control_line_state(p_cdc, line_state, complete_cb, user_data);
-
-    #if CFG_TUH_CDC_FTDI
-    case SERIAL_PROTOCOL_FTDI:
-      return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data);
-    #endif
-
-    #if CFG_TUH_CDC_CP210X
-    case SERIAL_PROTOCOL_CP210X:
-      return ftdi_sio_set_modem_ctrl(p_cdc, line_state, complete_cb, user_data);
-    #endif
-
-    default:
-      return false;
+  if (xfer->complete_cb) {
+    xfer->complete_cb(xfer);
   }
 }
 
-bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  TU_LOG_CDCH("CDC ACM Set Line Conding\r\n");
+bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  return serial_drivers[p_cdc->serial_drid].set_control_line_state(p_cdc, line_state, complete_cb, user_data);
+}
 
-  tusb_control_request_t const request = {
-    .bmRequestType_bit = {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_OUT
-    },
-    .bRequest = CDC_REQUEST_SET_LINE_CODING,
-    .wValue   = 0,
-    .wIndex   = tu_htole16(p_cdc->bInterfaceNumber),
-    .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
-  };
-
-  // use usbh enum buf to hold line coding since user line_coding variable does not live long enough
-  uint8_t* enum_buf = usbh_get_enum_buf();
-  memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t));
-
-  p_cdc->user_control_cb = complete_cb;
-  tuh_xfer_t xfer = {
-    .daddr       = p_cdc->daddr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = enum_buf,
-    .complete_cb = cdch_internal_control_complete,
-    .user_data   = user_data
-  };
-
-  TU_ASSERT(tuh_control_xfer(&xfer));
-  return true;
+bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  cdch_interface_t* p_cdc = get_itf(idx);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+  return serial_drivers[p_cdc->serial_drid].set_baudrate(p_cdc, baudrate, complete_cb, user_data);
 }
 
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc);
-
-  switch(p_cdc->serial_protocol) {
-    case SERIAL_PROTOCOL_ACM:
-      TU_VERIFY(p_cdc->acm_capability.support_line_request);
-      return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
-
-    #if CFG_TUH_CDC_FTDI
-    case SERIAL_PROTOCOL_FTDI:
-      // FTDI need to set baud rate and data bits, parity, stop bits separately
-      return ftdi_sio_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data);
-    #endif
-
-    #if CFG_TUH_CDC_CP210X
-    case SERIAL_PROTOCOL_CP210X:
-      return cp210x_set_baudrate(p_cdc, line_coding->bit_rate, complete_cb, user_data);
-    #endif
-
-    default: return false;
-  }
-}
-
-bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  cdch_interface_t* p_cdc = get_itf(idx);
-  TU_VERIFY(p_cdc);
-
-  switch(p_cdc->serial_protocol) {
-    case SERIAL_PROTOCOL_ACM: {
-      TU_VERIFY(p_cdc->acm_capability.support_line_request);
-      cdc_line_coding_t line_coding = p_cdc->line_coding;
-      line_coding.bit_rate = baudrate;
-      return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data);
-    }
-
-    #if CFG_TUH_CDC_FTDI
-    case SERIAL_PROTOCOL_FTDI:
-      // FTDI need to set baud rate and data bits, parity, stop bits separately
-      return ftdi_sio_set_baudrate(p_cdc, baudrate, complete_cb, user_data);
-    #endif
-
-    #if CFG_TUH_CDC_CP210X
-    case SERIAL_PROTOCOL_CP210X:
-      return cp210x_set_baudrate(p_cdc, baudrate, complete_cb, user_data);
-    #endif
-
-    default: return false;
-  }
+  // only ACM support this set line coding request
+  TU_VERIFY(p_cdc->serial_drid == SERIAL_DRIVER_ACM && p_cdc->acm_capability.support_line_request);
+  return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
 }
 
 //--------------------------------------------------------------------+
@@ -561,7 +523,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 
     #if CFG_TUH_CDC_FTDI
     // FTDI reserve 2 bytes for status
-    if (p_cdc->serial_protocol == SERIAL_PROTOCOL_FTDI) {
+    if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) {
       uint8_t status[2];
       tu_edpt_stream_read(&p_cdc->stream.rx, status, 2);
       (void) status; // TODO handle status
@@ -587,15 +549,10 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
 //--------------------------------------------------------------------+
 // Enumeration
 //--------------------------------------------------------------------+
-enum
-{
-  // ACM
-  CONFIG_ACM_SET_CONTROL_LINE_STATE = 0,
-  CONFIG_ACM_SET_LINE_CODING,
-  CONFIG_ACM_COMPLETE,
-};
 
-static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep)
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+
+static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const *desc_ep)
 {
   for(size_t i=0; i<2; i++)
   {
@@ -618,57 +575,6 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t c
   return true;
 }
 
-static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
-{
-  uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len;
-
-  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
-  TU_VERIFY(p_cdc);
-
-  p_cdc->serial_protocol = SERIAL_PROTOCOL_ACM;
-
-  //------------- Control Interface -------------//
-  uint8_t const * p_desc = tu_desc_next(itf_desc);
-
-  // Communication Functional Descriptors
-  while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) )
-  {
-    if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
-    {
-      // save ACM bmCapabilities
-      p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
-    }
-
-    p_desc = tu_desc_next(p_desc);
-  }
-
-  // Open notification endpoint of control interface if any
-  if (itf_desc->bNumEndpoints == 1)
-  {
-    TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc));
-    tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-
-    TU_ASSERT( tuh_edpt_open(daddr, desc_ep) );
-    p_cdc->ep_notif = desc_ep->bEndpointAddress;
-
-    p_desc = tu_desc_next(p_desc);
-  }
-
-  //------------- Data Interface (if any) -------------//
-  if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
-       (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
-  {
-    // next to endpoint descriptor
-    p_desc = tu_desc_next(p_desc);
-
-    // data endpoints expected to be in pairs
-    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc));
-  }
-
-  return true;
-}
-
-
 bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
 {
   (void) rhport;
@@ -721,7 +627,88 @@ static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t i
   usbh_driver_set_config_complete(p_cdc->daddr, itf_num);
 }
 
-static void process_acm_config(tuh_xfer_t* xfer)
+
+bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
+{
+  tusb_control_request_t request;
+  request.wIndex = tu_htole16((uint16_t) itf_num);
+
+  // fake transfer to kick-off process
+  tuh_xfer_t xfer;
+  xfer.daddr  = daddr;
+  xfer.result = XFER_RESULT_SUCCESS;
+  xfer.setup  = &request;
+  xfer.user_data = 0; // initial state
+
+  uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num);
+  cdch_interface_t * p_cdc = get_itf(idx);
+  TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
+
+  serial_drivers[p_cdc->serial_drid].process_set_config(&xfer);
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// ACM
+//--------------------------------------------------------------------+
+
+enum {
+  CONFIG_ACM_SET_CONTROL_LINE_STATE = 0,
+  CONFIG_ACM_SET_LINE_CODING,
+  CONFIG_ACM_COMPLETE,
+};
+
+static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
+{
+  uint8_t const * p_desc_end = ((uint8_t const*) itf_desc) + max_len;
+
+  cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
+  TU_VERIFY(p_cdc);
+
+  p_cdc->serial_drid = SERIAL_DRIVER_ACM;
+
+  //------------- Control Interface -------------//
+  uint8_t const * p_desc = tu_desc_next(itf_desc);
+
+  // Communication Functional Descriptors
+  while( (p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc)) )
+  {
+    if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
+    {
+      // save ACM bmCapabilities
+      p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
+    }
+
+    p_desc = tu_desc_next(p_desc);
+  }
+
+  // Open notification endpoint of control interface if any
+  if (itf_desc->bNumEndpoints == 1)
+  {
+    TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc));
+    tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+
+    TU_ASSERT( tuh_edpt_open(daddr, desc_ep) );
+    p_cdc->ep_notif = desc_ep->bEndpointAddress;
+
+    p_desc = tu_desc_next(p_desc);
+  }
+
+  //------------- Data Interface (if any) -------------//
+  if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
+       (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
+  {
+    // next to endpoint descriptor
+    p_desc = tu_desc_next(p_desc);
+
+    // data endpoints expected to be in pairs
+    TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc));
+  }
+
+  return true;
+}
+
+static void acm_process_config(tuh_xfer_t* xfer)
 {
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
@@ -735,72 +722,103 @@ static void process_acm_config(tuh_xfer_t* xfer)
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
       if (p_cdc->acm_capability.support_line_request)
       {
-        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_acm_config,
-                                                 CONFIG_ACM_SET_LINE_CODING), );
+        TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config,
+                                             CONFIG_ACM_SET_LINE_CODING), );
         break;
       }
-      #endif
+          #endif
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_SET_LINE_CODING:
-      #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+        #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
       if (p_cdc->acm_capability.support_line_request)
       {
         cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, process_acm_config, CONFIG_ACM_COMPLETE), );
+        TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE), );
         break;
       }
-      #endif
+        #endif
       TU_ATTR_FALLTHROUGH;
 
     case CONFIG_ACM_COMPLETE:
       // itf_num+1 to account for data interface as well
       set_config_complete(p_cdc, idx, itf_num+1);
-    break;
+      break;
 
     default: break;
   }
 }
 
-bool cdch_set_config(uint8_t daddr, uint8_t itf_num)
-{
-  tusb_control_request_t request;
-  request.wIndex = tu_htole16((uint16_t) itf_num);
+static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_VERIFY(p_cdc->acm_capability.support_line_request);
+  TU_LOG_CDCH("CDC ACM Set Control Line State\r\n");
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
+    .wValue   = tu_htole16(line_state),
+    .wIndex   = tu_htole16((uint16_t) p_cdc->bInterfaceNumber),
+    .wLength  = 0
+  };
 
-  tuh_xfer_t xfer;
-  xfer.daddr  = daddr;
-  xfer.result = XFER_RESULT_SUCCESS;
-  xfer.setup  = &request;
-  xfer.user_data = 0;
+  p_cdc->user_control_cb = complete_cb;
 
-  // fake transfer to kick-off process
-  uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num);
-  cdch_interface_t * p_cdc = get_itf(idx);
-  TU_ASSERT(p_cdc);
-
-  switch (p_cdc->serial_protocol) {
-    case SERIAL_PROTOCOL_ACM:
-      process_acm_config(&xfer);
-      break;
-
-    #if CFG_TUH_CDC_FTDI
-    case SERIAL_PROTOCOL_FTDI:
-      process_ftdi_config(&xfer);
-      break;
-    #endif
-
-    #if CFG_TUH_CDC_CP210X
-    case SERIAL_PROTOCOL_CP210X:
-      process_cp210x_config(&xfer);
-      break;
-    #endif
-
-      default: return false;
-  }
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = NULL,
+    .complete_cb = cdch_internal_control_complete,
+    .user_data   = user_data
+  };
 
+  TU_ASSERT(tuh_control_xfer(&xfer));
   return true;
 }
 
+static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_LOG_CDCH("CDC ACM Set Line Conding\r\n");
+
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
+      .recipient = TUSB_REQ_RCPT_INTERFACE,
+      .type      = TUSB_REQ_TYPE_CLASS,
+      .direction = TUSB_DIR_OUT
+    },
+    .bRequest = CDC_REQUEST_SET_LINE_CODING,
+    .wValue   = 0,
+    .wIndex   = tu_htole16(p_cdc->bInterfaceNumber),
+    .wLength  = tu_htole16(sizeof(cdc_line_coding_t))
+  };
+
+  // use usbh enum buf to hold line coding since user line_coding variable does not live long enough
+  uint8_t* enum_buf = usbh_get_enum_buf();
+  memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t));
+
+  p_cdc->user_control_cb = complete_cb;
+  tuh_xfer_t xfer = {
+    .daddr       = p_cdc->daddr,
+    .ep_addr     = 0,
+    .setup       = &request,
+    .buffer      = enum_buf,
+    .complete_cb = cdch_internal_control_complete,
+    .user_data   = user_data
+  };
+
+  TU_ASSERT(tuh_control_xfer(&xfer));
+  return true;
+}
+
+static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
+  TU_VERIFY(p_cdc->acm_capability.support_line_request);
+  cdc_line_coding_t line_coding = p_cdc->line_coding;
+  line_coding.bit_rate = baudrate;
+  return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data);
+}
+
 //--------------------------------------------------------------------+
 // FTDI
 //--------------------------------------------------------------------+
@@ -824,7 +842,7 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint
 
   TU_LOG_CDCH("FTDI opened\r\n");
 
-  p_cdc->serial_protocol = SERIAL_PROTOCOL_FTDI;
+  p_cdc->serial_drid = SERIAL_DRIVER_FTDI;
 
   // endpoint pair
   tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
@@ -904,11 +922,13 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
   TU_LOG_CDCH("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
+  _ftdi_requested_baud = baudrate;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data));
+
   return true;
 }
 
-static void process_ftdi_config(tuh_xfer_t* xfer) {
+static void ftdi_process_config(tuh_xfer_t* xfer) {
   uintptr_t const state = xfer->user_data;
   uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
@@ -918,13 +938,13 @@ static void process_ftdi_config(tuh_xfer_t* xfer) {
   switch(state) {
     // Note may need to read FTDI eeprom
     case CONFIG_FTDI_RESET:
-      TU_ASSERT(ftdi_sio_reset(p_cdc, process_ftdi_config, CONFIG_FTDI_MODEM_CTRL),);
+      TU_ASSERT(ftdi_sio_reset(p_cdc, ftdi_process_config, CONFIG_FTDI_MODEM_CTRL),);
       break;
 
     case CONFIG_FTDI_MODEM_CTRL:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
       TU_ASSERT(
-        ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_ftdi_config, CONFIG_FTDI_SET_BAUDRATE),);
+        ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -933,7 +953,7 @@ static void process_ftdi_config(tuh_xfer_t* xfer) {
     case CONFIG_FTDI_SET_BAUDRATE: {
       #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
       cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-      TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, process_ftdi_config, CONFIG_FTDI_SET_DATA),);
+      TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, ftdi_process_config, CONFIG_FTDI_SET_DATA),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -986,7 +1006,7 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui
   TU_VERIFY(p_cdc);
 
   TU_LOG_CDCH("CP210x opened\r\n");
-  p_cdc->serial_protocol = SERIAL_PROTOCOL_CP210X;
+  p_cdc->serial_drid = SERIAL_DRIVER_CP210X;
 
   // endpoint pair
   tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
@@ -1034,8 +1054,9 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe
 
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_LOG_CDCH("CDC CP210x Set BaudRate = %lu\n", baudrate);
-  baudrate = tu_htole32(baudrate);
-  return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baudrate, 4, complete_cb, user_data);
+  uint32_t baud_le = tu_htole32(baudrate);
+  p_cdc->user_control_cb = complete_cb;
+  return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, cdch_internal_control_complete, user_data);
 }
 
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
@@ -1045,7 +1066,7 @@ static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
   return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, cdch_internal_control_complete, user_data);
 }
 
-static void process_cp210x_config(tuh_xfer_t* xfer) {
+static void cp210x_process_config(tuh_xfer_t* xfer) {
   uintptr_t const state   = xfer->user_data;
   uint8_t const   itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex);
   uint8_t const   idx     = tuh_cdc_itf_get_index(xfer->daddr, itf_num);
@@ -1054,13 +1075,13 @@ static void process_cp210x_config(tuh_xfer_t* xfer) {
 
   switch (state) {
     case CONFIG_CP210X_IFC_ENABLE:
-      TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, process_cp210x_config, CONFIG_CP210X_SET_BAUDRATE),);
+      TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, cp210x_process_config, CONFIG_CP210X_SET_BAUDRATE),);
       break;
 
     case CONFIG_CP210X_SET_BAUDRATE: {
       #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
       cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
-      TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, process_cp210x_config, CONFIG_CP210X_SET_LINE_CTL),);
+      TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, cp210x_process_config, CONFIG_CP210X_SET_LINE_CTL),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
@@ -1078,7 +1099,8 @@ static void process_cp210x_config(tuh_xfer_t* xfer) {
 
     case CONFIG_CP210X_SET_DTR_RTS:
       #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM
-      TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, process_cp210x_config, CONFIG_CP210X_COMPLETE),);
+      TU_ASSERT(
+        cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),);
       break;
       #else
       TU_ATTR_FALLTHROUGH;
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 971ebe2ae..f6cc3812f 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -134,7 +134,11 @@ bool tuh_cdc_read_clear (uint8_t idx);
 
 //--------------------------------------------------------------------+
 // Control Endpoint (Request) API
-// Each Function will make a USB transfer request to/from device
+// Each Function will make a USB control transfer request to/from device
+// - If complete_cb is provided, the function will return immediately and invoke
+// the callback when request is complete.
+// - If complete_cb is NULL, the function will block until request is complete.
+// In this case, user_data should be pointed to xfer_result_t to hold the transfer result.
 //--------------------------------------------------------------------+
 
 // Request to Set Control Line State: DTR (bit 0), RTS (bit 1)
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 3953d5b21..24ce47a7f 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -571,19 +571,19 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
 
     TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
 
-    while (result == XFER_RESULT_INVALID)
-    {
+    while (result == XFER_RESULT_INVALID) {
       // Note: this can be called within an callback ie. part of tuh_task()
       // therefore event with RTOS tuh_task() still need to be invoked
-      if (tuh_task_event_ready())
-      {
+      if (tuh_task_event_ready()) {
         tuh_task();
       }
-
       // TODO probably some timeout to prevent hanged
     }
 
-    // update transfer result
+    // update transfer result, user_data is expected to point to xfer_result_t
+    if (xfer->user_data != 0) {
+      *((xfer_result_t*) xfer->user_data) = result;
+    }
     xfer->result     = result;
     xfer->actual_len = _ctrl_xfer.actual_len;
   }
@@ -877,7 +877,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
 //--------------------------------------------------------------------+
 
 // generic helper to get a descriptor
-// if blocking, user_data could be pointed to xfer_result
+// if blocking, user_data is pointed to xfer_result
 static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
                             tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
@@ -905,15 +905,7 @@ static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t
     .user_data   = user_data
   };
 
-  bool const ret = tuh_control_xfer(&xfer);
-
-  // if blocking, user_data could be pointed to xfer_result
-  if ( !complete_cb && user_data )
-  {
-    *((xfer_result_t*) user_data) = xfer.result;
-  }
-
-  return ret;
+  return tuh_control_xfer(&xfer);
 }
 
 bool tuh_descriptor_get(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len,
@@ -971,7 +963,7 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void*
 }
 
 // Get HID report descriptor
-// if blocking, user_data could be pointed to xfer_result
+// if blocking, user_data is pointed to xfer_result
 bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len,
                                    tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
@@ -1000,15 +992,7 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_
     .user_data   = user_data
   };
 
-  bool const ret = tuh_control_xfer(&xfer);
-
-  // if blocking, user_data could be pointed to xfer_result
-  if ( !complete_cb && user_data )
-  {
-    *((xfer_result_t*) user_data) = xfer.result;
-  }
-
-  return ret;
+  return tuh_control_xfer(&xfer);
 }
 
 bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
@@ -1040,15 +1024,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
     .user_data   = user_data
   };
 
-  bool ret = tuh_control_xfer(&xfer);
-
-  // if blocking, user_data could be pointed to xfer_result
-  if ( !complete_cb && user_data )
-  {
-    *((xfer_result_t*) user_data) = xfer.result;
-  }
-
-  return ret;
+  return tuh_control_xfer(&xfer);
 }
 
 bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
@@ -1080,15 +1056,7 @@ bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt,
     .user_data   = user_data
   };
 
-  bool ret = tuh_control_xfer(&xfer);
-
-  // if blocking, user_data could be pointed to xfer_result
-  if ( !complete_cb && user_data )
-  {
-    *((xfer_result_t*) user_data) = xfer.result;
-  }
-
-  return ret;
+  return tuh_control_xfer(&xfer);
 }
 
 //--------------------------------------------------------------------+

From fb5fe3360fb29a5d937cb6d6f1baa7695c04c361 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Apr 2023 21:50:54 +0700
Subject: [PATCH 1681/2085] allow call tuh cdc with blocking (callback = NULL)

- tuh_cdc_set_control_line_state()
- tuh_cdc_set_baudrate()
- tuh_cdc_set_line_coding()
---
 src/class/cdc/cdc_host.c | 83 ++++++++++++++++++++++++++++++++++------
 src/class/cdc/cdc_host.h |  1 +
 2 files changed, 73 insertions(+), 11 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index b25bc5512..858fdd9a7 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -437,22 +437,78 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
 bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
-  return serial_drivers[p_cdc->serial_drid].set_control_line_state(p_cdc, line_state, complete_cb, user_data);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
+
+  if ( complete_cb ) {
+    return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data);
+  }else {
+    // blocking
+    xfer_result_t result;
+    bool ret = driver->set_control_line_state(p_cdc, line_state, complete_cb, (uintptr_t) &result);
+
+    if (user_data) {
+      // user_data is not NULL, return result via user_data
+      *((xfer_result_t*) user_data) = result;
+    }
+
+    if (result == XFER_RESULT_SUCCESS) {
+      p_cdc->line_state = (uint8_t) line_state;
+    }
+
+    return ret;
+  }
 }
 
 bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   cdch_interface_t* p_cdc = get_itf(idx);
   TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT);
-  return serial_drivers[p_cdc->serial_drid].set_baudrate(p_cdc, baudrate, complete_cb, user_data);
+  cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid];
+
+  if ( complete_cb ) {
+    return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data);
+  }else {
+    // blocking
+    xfer_result_t result;
+    bool ret = driver->set_baudrate(p_cdc, baudrate, complete_cb, (uintptr_t) &result);
+
+    if (user_data) {
+      // user_data is not NULL, return result via user_data
+      *((xfer_result_t*) user_data) = result;
+    }
+
+    if (result == XFER_RESULT_SUCCESS) {
+      p_cdc->line_coding.bit_rate = baudrate;
+    }
+
+    return ret;
+  }
 }
 
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   cdch_interface_t* p_cdc = get_itf(idx);
-  TU_VERIFY(p_cdc);
   // only ACM support this set line coding request
-  TU_VERIFY(p_cdc->serial_drid == SERIAL_DRIVER_ACM && p_cdc->acm_capability.support_line_request);
-  return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
+  TU_VERIFY(p_cdc && p_cdc->serial_drid == SERIAL_DRIVER_ACM);
+  TU_VERIFY(p_cdc->acm_capability.support_line_request);
+
+  if ( complete_cb ) {
+    return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
+  }else {
+    // blocking
+    xfer_result_t result;
+    bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
+
+    if (user_data) {
+      // user_data is not NULL, return result via user_data
+      *((xfer_result_t*) user_data) = result;
+    }
+
+    if (result == XFER_RESULT_SUCCESS) {
+      p_cdc->line_coding = *line_coding;
+    }
+
+    return ret;
+  }
 }
 
 //--------------------------------------------------------------------+
@@ -752,6 +808,7 @@ static void acm_process_config(tuh_xfer_t* xfer)
 static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_VERIFY(p_cdc->acm_capability.support_line_request);
   TU_LOG_CDCH("CDC ACM Set Control Line State\r\n");
+
   tusb_control_request_t const request = {
     .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_INTERFACE,
@@ -771,7 +828,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = NULL,
-    .complete_cb = cdch_internal_control_complete,
+    .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, // complete_cb is NULL for sync call
     .user_data   = user_data
   };
 
@@ -804,7 +861,7 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const
     .ep_addr     = 0,
     .setup       = &request,
     .buffer      = enum_buf,
-    .complete_cb = cdch_internal_control_complete,
+    .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, // complete_cb is NULL for sync call
     .user_data   = user_data
   };
 
@@ -886,7 +943,8 @@ static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state
 {
   TU_LOG_CDCH("CDC FTDI Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
-  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, cdch_internal_control_complete, user_data));
+  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
+                                 complete_cb ? cdch_internal_control_complete : NULL, user_data));
   return true;
 }
 
@@ -923,7 +981,8 @@ static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tu
 
   p_cdc->user_control_cb = complete_cb;
   _ftdi_requested_baud = baudrate;
-  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, cdch_internal_control_complete, user_data));
+  TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor,
+                                 complete_cb ? cdch_internal_control_complete : NULL, user_data));
 
   return true;
 }
@@ -1056,14 +1115,16 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
   TU_LOG_CDCH("CDC CP210x Set BaudRate = %lu\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
   p_cdc->user_control_cb = complete_cb;
-  return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, cdch_internal_control_complete, user_data);
+  return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4,
+                            complete_cb ? cdch_internal_control_complete : NULL, user_data);
 }
 
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   TU_LOG_CDCH("CDC CP210x Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
-  return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, cdch_internal_control_complete, user_data);
+  return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0,
+                            complete_cb ? cdch_internal_control_complete : NULL, user_data);
 }
 
 static void cp210x_process_config(tuh_xfer_t* xfer) {
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index f6cc3812f..8544ff740 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -148,6 +148,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
 bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Request to Set Line Coding (ACM only)
+// Should only use if you don't work with serial devices such as FTDI/CP210x
 bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 // Request to Get Line Coding (ACM only)

From 1763eede4839d0131cda077e2dd9631f315ce115 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Apr 2023 22:14:14 +0700
Subject: [PATCH 1682/2085] more update to host serial API

---
 src/class/cdc/cdc_host.c | 27 ++++++++++++---------------
 src/class/cdc/cdc_host.h |  3 ++-
 2 files changed, 14 insertions(+), 16 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 858fdd9a7..fe3691bf4 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -443,7 +443,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
     return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data);
   }else {
     // blocking
-    xfer_result_t result;
+    xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = driver->set_control_line_state(p_cdc, line_state, complete_cb, (uintptr_t) &result);
 
     if (user_data) {
@@ -451,11 +451,10 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c
       *((xfer_result_t*) user_data) = result;
     }
 
-    if (result == XFER_RESULT_SUCCESS) {
-      p_cdc->line_state = (uint8_t) line_state;
-    }
+    TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
 
-    return ret;
+    p_cdc->line_state = (uint8_t) line_state;
+    return true;
   }
 }
 
@@ -468,7 +467,7 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
     return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data);
   }else {
     // blocking
-    xfer_result_t result;
+    xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = driver->set_baudrate(p_cdc, baudrate, complete_cb, (uintptr_t) &result);
 
     if (user_data) {
@@ -476,11 +475,10 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete
       *((xfer_result_t*) user_data) = result;
     }
 
-    if (result == XFER_RESULT_SUCCESS) {
-      p_cdc->line_coding.bit_rate = baudrate;
-    }
+    TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
 
-    return ret;
+    p_cdc->line_coding.bit_rate = baudrate;
+    return true;
   }
 }
 
@@ -495,7 +493,7 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
     return acm_set_line_coding(p_cdc, line_coding, complete_cb, user_data);
   }else {
     // blocking
-    xfer_result_t result;
+    xfer_result_t result = XFER_RESULT_INVALID;
     bool ret = acm_set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result);
 
     if (user_data) {
@@ -503,11 +501,10 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding,
       *((xfer_result_t*) user_data) = result;
     }
 
-    if (result == XFER_RESULT_SUCCESS) {
-      p_cdc->line_coding = *line_coding;
-    }
+    TU_VERIFY(ret && result == XFER_RESULT_SUCCESS);
 
-    return ret;
+    p_cdc->line_coding = *line_coding;
+    return true;
   }
 }
 
diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h
index 8544ff740..19552f1ee 100644
--- a/src/class/cdc/cdc_host.h
+++ b/src/class/cdc/cdc_host.h
@@ -138,7 +138,8 @@ bool tuh_cdc_read_clear (uint8_t idx);
 // - If complete_cb is provided, the function will return immediately and invoke
 // the callback when request is complete.
 // - If complete_cb is NULL, the function will block until request is complete.
-// In this case, user_data should be pointed to xfer_result_t to hold the transfer result.
+//   - In this case, user_data should be pointed to xfer_result_t to hold the transfer result.
+//   - The function will return true if transfer is successful, false otherwise.
 //--------------------------------------------------------------------+
 
 // Request to Set Control Line State: DTR (bit 0), RTS (bit 1)

From be54870c3b2f7f1c14b0f5527f4928c8a4a4a7ae Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 3 May 2023 10:02:24 +0200
Subject: [PATCH 1683/2085] renesas_ra: add support for HS port

---
 hw/bsp/ra/family.mk                    |  2 +
 src/portable/renesas/rusb2/dcd_rusb2.c | 76 ++++++++++++++++++++++----
 src/portable/renesas/rusb2/hcd_rusb2.c | 46 +++++++++++-----
 src/portable/renesas/rusb2/rusb2_ra.c  | 16 ++++++
 src/portable/renesas/rusb2/rusb2_ra.h  | 37 +++++++++++--
 5 files changed, 147 insertions(+), 30 deletions(-)
 create mode 100644 src/portable/renesas/rusb2/rusb2_ra.c

diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index d48272e61..3ed17f79f 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -22,6 +22,7 @@ CFLAGS += \
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
+	src/portable/renesas/rusb2/rusb2_ra.c \
 	hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
 	hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \
 	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \
@@ -47,6 +48,7 @@ INC += \
 	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc \
 	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/api \
 	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/instances \
+	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all \
 	$(TOP)/$(FSP_MCU_DIR) \
 	$(TOP)/$(FSP_BOARD_DIR)
 
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 78584125f..9ae36e253 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -52,8 +52,10 @@
 /* LINK core registers */
 #if defined(__CCRX__)
   #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
+#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE)
 #else
-  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
+  #define RUSB2 ((R_USB_FS0_Type*)R_USB_FS0_BASE)
 #endif
 
 /* Start of definition of packed structs (used by the CCRX toolchain) */
@@ -81,6 +83,18 @@ typedef union TU_ATTR_PACKED {
   volatile uint16_t u16;
 } hw_fifo_t;
 
+typedef union TU_ATTR_PACKED {
+  struct {
+    volatile uint32_t  : 24;
+    volatile uint32_t u8: 8;
+  };
+  struct {
+    volatile uint32_t    : 16;
+    volatile uint32_t u16: 16;
+  };
+  volatile uint32_t u32;
+} hw_fifo32_t;
+
 typedef struct TU_ATTR_PACKED
 {
   void      *buf;      /* the start address of a transfer data buffer */
@@ -185,14 +199,18 @@ static inline void pipe_wait_for_ready(unsigned num)
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 {
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo;
+#else
   volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo;
+#endif
   uintptr_t addr = (uintptr_t)buf;
   while (len >= 2) {
     reg->u16 = *(const uint16_t *)addr;
     addr += 2;
     len  -= 2;
   }
-  if (len) {
+  if (len > 0) {
     reg->u8 = *(const uint8_t *)addr;
     ++addr;
   }
@@ -519,12 +537,17 @@ static void process_bus_reset(uint8_t rhport)
     ++ctr;
   }
   tu_varclr(&_dcd);
+
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, true);
+#else
   dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+#endif
 }
 
 static void process_set_address(uint8_t rhport)
 {
-  const uint32_t addr = RUSB2->USBADDR_b.USBADDR;
+  const uint32_t addr = RUSB2->USBADDR & 0xFF;
   if (!addr) return;
   const tusb_control_request_t setup_packet = {
 #if defined(__CCRX__)
@@ -572,34 +595,53 @@ void dcd_init(uint8_t rhport)
 {
   (void)rhport;
 
-#if 0 // previously present in the rx driver before generalization
-  uint32_t pswi = disable_interrupt();
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(USB0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  enable_interrupt(pswi);
-#endif
-
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  RUSB2->SYSCFG_b.HSE = 1;
+  RUSB2->PHYSET_b.DIRPD = 0;
+  R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
+  RUSB2->PHYSET_b.PLLRESET = 0;
+  //RUSB2->PHYSET_b.REPSTART = 1;
+  RUSB2->SYSCFG_b.DRPD = 0;
+  RUSB2->SYSCFG_b.USBE = 1;
+  RUSB2->LPSTS_b.SUSPENDM = 1;
+  while (!RUSB2->PLLSTA_b.PLLLOCK);
+  //RUSB2->BUSWAIT |= 0x0F00U;
+  //RUSB2->PHYSET_b.REPSEL = 1;
+  RUSB2->CFIFOSEL_b.MBW = 1;
+  RUSB2->D0FIFOSEL_b.MBW = 1;
+  RUSB2->D1FIFOSEL_b.MBW = 1;
+  RUSB2->INTSTS0 = 0;
+#else
   RUSB2->SYSCFG_b.SCKE = 1;
   while (!RUSB2->SYSCFG_b.SCKE) ;
   RUSB2->SYSCFG_b.DRPD = 0;
   RUSB2->SYSCFG_b.DCFM = 0;
   RUSB2->SYSCFG_b.USBE = 1;
+#endif
 
   // MCU specific PHY init
   rusb2_phy_init();
 
+#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
   RUSB2->PHYSLEW = 0x5;
   RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
 
+  #define USB_VDCEN                 (0x0080U) /* b7: Regulator ON/OFF control */
+  RUSB2->USBMC = (uint16_t) (RUSB2->USBMC | (USB_VDCEN));
+#endif
+
   /* Setup default control pipe */
   RUSB2->DCPMAXP_b.MXPS = 64;
   RUSB2->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
           RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
-          RUSB2_INTSTS0_RESM_Msk;
+          RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk;
   RUSB2->BEMPENB = 1;
   RUSB2->BRDYENB = 1;
 
+#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
+  RUSB2->SYSCFG_b.DPRPU = 1;  /* necessary in this position */
+#endif
+
   if (RUSB2->INTSTS0_b.VBSTS) {
     dcd_connect(rhport);
   }
@@ -630,6 +672,10 @@ void dcd_remote_wakeup(uint8_t rhport)
 void dcd_connect(uint8_t rhport)
 {
   (void)rhport;
+  #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  RUSB2->SYSCFG_b.CNEN = 1;
+  R_BSP_SoftwareDelay((uint32_t) 10, BSP_DELAY_UNITS_MILLISECONDS);
+  #endif
   RUSB2->SYSCFG_b.DPRPU = 1;
 }
 
@@ -672,6 +718,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   /* setup pipe */
   dcd_int_disable(rhport);
+  #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
+  RUSB2->PIPEBUF = 0x7C08;
+  #endif
   RUSB2->PIPESEL = num;
   RUSB2->PIPEMAXP = mps;
   volatile uint16_t *ctr = get_pipectr(num);
@@ -826,6 +875,9 @@ void dcd_int_handler(uint8_t rhport)
       break;
     }
   }
+  if (is0 & RUSB2_INTSTS0_NRDY_Msk) {
+    RUSB2->NRDYSTS = 0;
+  }
   if (is0 & RUSB2_INTSTS0_CTRT_Msk) {
     if (is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA) {
       /* A setup packet has been received. */
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index e4743223e..03811d63f 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -48,8 +48,10 @@
 /* LINK core registers */
 #if defined(__CCRX__)
   #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
+#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
+  #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE)
 #else
-  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
+  #define RUSB2 ((R_USB_FS0_Type*) R_USB_FS0_BASE)
 #endif
 
 TU_ATTR_PACKED_BEGIN
@@ -477,31 +479,49 @@ bool hcd_init(uint8_t rhport)
 {
   (void)rhport;
 
-#if 0 // previously present in the rx driver before generalization
-  uint32_t pswi = disable_interrupt();
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
-  MSTP(USB0) = 0;
-  SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
-  enable_interrupt(pswi);
-#endif
-
-  RUSB2->SYSCFG_b.SCKE = 1;
-  while (!RUSB2->SYSCFG_b.SCKE) ;
-  RUSB2->SYSCFG_b.DPRPU = 0;
-  RUSB2->SYSCFG_b.DRPD = 0;
+#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
+  RUSB2->SYSCFG_b.HSE = 1;
+  RUSB2->PHYSET_b.HSEB = 0;
+  RUSB2->PHYSET_b.DIRPD = 0;
+  R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
+  RUSB2->PHYSET_b.PLLRESET = 0;
+  RUSB2->LPSTS_b.SUSPENDM = 1;
+  while (!RUSB2->PLLSTA_b.PLLLOCK);
+  RUSB2->SYSCFG_b.DRPD = 1;
   RUSB2->SYSCFG_b.DCFM = 1;
+  RUSB2->SYSCFG_b.DPRPU = 0;
+  RUSB2->SYSCFG_b.CNEN = 1;
+  RUSB2->BUSWAIT |= 0x0F00U;
+  RUSB2->SOFCFG_b.INTL = 1;
+  RUSB2->DVSTCTR0_b.VBUSEN = 1;
+  RUSB2->CFIFOSEL_b.MBW = 1;
+  RUSB2->D0FIFOSEL_b.MBW = 1;
+  RUSB2->D1FIFOSEL_b.MBW = 1;
+  RUSB2->INTSTS0 = 0;
+  for (volatile int i = 0; i < 30000; ++i) ;
+  RUSB2->SYSCFG_b.USBE = 1;
+#else
+  /* HOST DEVICE Full SPEED */
+  RUSB2->SYSCFG_b.SCKE = 1;         /* USB Clock enable */
+  while (!RUSB2->SYSCFG_b.SCKE) ;
+  RUSB2->SYSCFG_b.DPRPU = 0;        /* D+ pull up enable - 0/disable in host mode */
+  RUSB2->SYSCFG_b.DRPD = 1;         /* D+/D- pull down - 1/in Host mode (pag.834)*/
+  RUSB2->SYSCFG_b.DCFM = 1;         /* HOST or Device - 1/HOST */
 
   RUSB2->DVSTCTR0_b.VBUSEN = 1;
 
   RUSB2->SYSCFG_b.DRPD = 1;
   for (volatile int i = 0; i < 30000; ++i) ;
   RUSB2->SYSCFG_b.USBE = 1;
+#endif
 
   // MCU specific PHY init
   rusb2_phy_init();
 
+#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST)
   RUSB2->PHYSLEW = 0x5;
   RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
+#endif
 
   /* Setup default control pipe */
   RUSB2->DCPCFG  = RUSB2_PIPECFG_SHTNAK_Msk;
diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c
new file mode 100644
index 000000000..2b6ce7b2f
--- /dev/null
+++ b/src/portable/renesas/rusb2/rusb2_ra.c
@@ -0,0 +1,16 @@
+#include "tusb_option.h"
+#include "rusb2_ra.h"
+
+#ifdef CFG_TUSB_RHPORT0_MODE
+IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn;
+void tud_set_irq_usbfs(IRQn_Type q) {
+  _usb_fs_irqn = q;
+}
+#endif
+
+#ifdef CFG_TUSB_RHPORT1_MODE
+IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn;
+void tud_set_irq_usbhs(IRQn_Type q) {
+  _usb_hs_irqn = q;
+}
+#endif
\ No newline at end of file
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 5785850cc..b18b506e5 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -34,18 +34,45 @@ extern "C" {
 /* renesas fsp api */
 #include "bsp_api.h"
 
-#define RUSB2_REG_BASE (0x40090000)
+extern IRQn_Type _usb_fs_irqn;
+extern IRQn_Type _usb_hs_irqn;
 
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_EnableIRQ(TU_IRQn);
+#ifdef CFG_TUSB_RHPORT1_MODE
+#if (CFG_TUSB_RHPORT1_MODE != 0)
+  if (rhport == 1) {
+    NVIC_EnableIRQ(_usb_hs_irqn);
+  }
+#endif
+#endif
+
+#ifdef CFG_TUSB_RHPORT0_MODE
+#if  (CFG_TUSB_RHPORT0_MODE != 0)
+  if (rhport == 0) {
+    NVIC_EnableIRQ(_usb_fs_irqn);
+  }
+#endif
+#endif
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport)
 {
-  (void) rhport;
-  NVIC_DisableIRQ(TU_IRQn);
+#ifdef CFG_TUSB_RHPORT1_MODE
+#if (CFG_TUSB_RHPORT1_MODE != 0)
+  if (rhport == 1) {
+    NVIC_DisableIRQ(_usb_hs_irqn);
+  }
+#endif
+#endif
+
+#ifdef CFG_TUSB_RHPORT0_MODE
+#if (CFG_TUSB_RHPORT0_MODE != 0)
+  if (rhport == 0) {
+    NVIC_DisableIRQ(_usb_fs_irqn);
+  }
+#endif
+#endif
 }
 
 // MCU specific PHY init

From 4afed62646d18dd96eef619d7d21b47a2422672f Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 3 May 2023 10:05:29 +0200
Subject: [PATCH 1684/2085] renesas_ra: host: handle retry on attach()

---
 src/portable/renesas/rusb2/hcd_rusb2.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 03811d63f..9dd4f0a48 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -759,9 +759,10 @@ void hcd_int_handler(uint8_t rhport)
     7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
     20, 8, 19, 18};
 #endif
-
+  static unsigned char attach_attempt = 0;
   unsigned is1 = RUSB2->INTSTS1;
   unsigned is0 = RUSB2->INTSTS0;
+
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
   RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
   RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
@@ -772,12 +773,21 @@ void hcd_int_handler(uint8_t rhport)
   if (is1 & RUSB2_INTSTS1_SACK_Msk) {
     /* Set DATA1 in advance for the next transfer. */
     RUSB2->DCPCTR_b.SQSET = 1;
+    attach_attempt = 0;
     hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
   }
   if (is1 & RUSB2_INTSTS1_SIGN_Msk) {
     hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
+    if(attach_attempt > 0) {
+      RUSB2->DVSTCTR0_b.UACT = 1;
+      _hcd.need_reset = true;
+      RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
+      hcd_event_device_attach(rhport, true);
+    }
+    attach_attempt--;
   }
   if (is1 & RUSB2_INTSTS1_ATTCH_Msk) {
+    attach_attempt = 10;
     RUSB2->DVSTCTR0_b.UACT = 1;
     _hcd.need_reset = true;
     RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;

From 5f7e7b4b0a9f65a401c679d5045b96b4b56755df Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 3 May 2023 10:06:13 +0200
Subject: [PATCH 1685/2085] renesas_ra: support RA2A1 (FS only)

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 9ae36e253..f3bda5205 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -41,6 +41,15 @@
   #include "rusb2_rx.h"
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
   #include "rusb2_ra.h"
+  #if defined(RENESAS_CORTEX_M23)
+    #define D0FIFO CFIFO
+    #define D0FIFOSEL CFIFOSEL
+    #define D0FIFOSEL_b CFIFOSEL_b
+    #define D1FIFOSEL CFIFOSEL
+    #define D1FIFOSEL_b CFIFOSEL_b
+    #define D0FIFOCTR CFIFOCTR
+    #define D0FIFOCTR_b CFIFOCTR_b
+  #endif
 #else
   #error "Unsupported MCU"
 #endif
@@ -121,6 +130,10 @@ typedef struct
 //--------------------------------------------------------------------+
 static dcd_data_t _dcd;
 
+#ifndef FIRST_BULK_PIPE
+#define FIRST_BULK_PIPE 3
+#endif
+
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
@@ -130,7 +143,7 @@ static unsigned find_pipe(unsigned xfer)
     }
     break;
   case TUSB_XFER_BULK:
-    for (int i = 3; i <= 5; ++i) {
+    for (int i = FIRST_BULK_PIPE; i <= 5; ++i) {
       if (0 == _dcd.pipe[i].ep) return  i;
     }
     for (int i = 1; i <= 1; ++i) {

From a349869906a41f959103b7aead2a1fd839773581 Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 3 May 2023 10:06:58 +0200
Subject: [PATCH 1686/2085] renesas_ra: fix existing boards support

---
 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h | 2 +-
 hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c            | 2 +-
 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h | 2 +-
 hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c            | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h
index 37739c12a..4719e22e6 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h
@@ -1,5 +1,5 @@
 /* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
-#define TU_IRQn 0
+#define USBFS_INT_IRQn 0
 #define USBFS_RESUME_IRQn 1
 #define USBFS_FIFO_0_IRQn 2
 #define USBFS_FIFO_1_IRQn 3
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c
index ea2204837..300cf6178 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c
@@ -151,7 +151,7 @@ void board_init(void)
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_INT_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h
index 37739c12a..4719e22e6 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h
@@ -1,5 +1,5 @@
 /* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
-#define TU_IRQn 0
+#define USBFS_INT_IRQn 0
 #define USBFS_RESUME_IRQn 1
 #define USBFS_FIFO_0_IRQn 2
 #define USBFS_FIFO_1_IRQn 3
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
index 327ef71d5..b68228008 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
@@ -153,7 +153,7 @@ void board_init(void)
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_INT_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);

From 6ff62c0fe85e825d077d7d803c657181769e542f Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 3 May 2023 11:47:41 +0200
Subject: [PATCH 1687/2085] renesas: add fallback for targets not defining
 CFG_TUSB_RHPORT*_MODE

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 5 +++++
 src/portable/renesas/rusb2/hcd_rusb2.c | 5 +++++
 src/portable/renesas/rusb2/rusb2_ra.h  | 5 +++++
 3 files changed, 15 insertions(+)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index f3bda5205..f509dcc56 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -37,6 +37,11 @@
 #include "device/dcd.h"
 #include "rusb2_type.h"
 
+#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
+// fallback
+#define CFG_TUSB_RHPORT0_MODE   OPT_MODE_DEVICE
+#endif
+
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 9dd4f0a48..1ec25f1e2 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -33,6 +33,11 @@
 #include "host/hcd.h"
 #include "rusb2_type.h"
 
+#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
+// fallback
+#define CFG_TUSB_RHPORT0_MODE   OPT_MODE_HOST
+#endif
+
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index b18b506e5..874492304 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -37,6 +37,11 @@ extern "C" {
 extern IRQn_Type _usb_fs_irqn;
 extern IRQn_Type _usb_hs_irqn;
 
+#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
+// fallback
+#define CFG_TUSB_RHPORT0_MODE   ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST )
+#endif
+
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
 #ifdef CFG_TUSB_RHPORT1_MODE

From 629717cd13730fa5f7543ce414ff11b5c175add0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 4 May 2023 16:38:06 +0700
Subject: [PATCH 1688/2085] fix cmake build

---
 {cmake => examples/cmake}/cpu/cortex-m7.cmake       | 0
 {cmake => examples/cmake}/toolchain/arm_gcc.cmake   | 0
 {cmake => examples/cmake}/toolchain/set_flags.cmake | 0
 hw/bsp/imxrt/family.cmake                           | 2 +-
 tools/build_family.py                               | 8 ++++----
 5 files changed, 5 insertions(+), 5 deletions(-)
 rename {cmake => examples/cmake}/cpu/cortex-m7.cmake (100%)
 rename {cmake => examples/cmake}/toolchain/arm_gcc.cmake (100%)
 rename {cmake => examples/cmake}/toolchain/set_flags.cmake (100%)

diff --git a/cmake/cpu/cortex-m7.cmake b/examples/cmake/cpu/cortex-m7.cmake
similarity index 100%
rename from cmake/cpu/cortex-m7.cmake
rename to examples/cmake/cpu/cortex-m7.cmake
diff --git a/cmake/toolchain/arm_gcc.cmake b/examples/cmake/toolchain/arm_gcc.cmake
similarity index 100%
rename from cmake/toolchain/arm_gcc.cmake
rename to examples/cmake/toolchain/arm_gcc.cmake
diff --git a/cmake/toolchain/set_flags.cmake b/examples/cmake/toolchain/set_flags.cmake
similarity index 100%
rename from cmake/toolchain/set_flags.cmake
rename to examples/cmake/toolchain/set_flags.cmake
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index e36adaf5a..95c4c0415 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -1,6 +1,6 @@
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 function(family_configure_target TARGET)
   if (NOT BOARD)
diff --git a/tools/build_family.py b/tools/build_family.py
index f9f7261fe..1fc25907b 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -41,11 +41,11 @@ if __name__ == '__main__':
 
     # If examples are not specified in arguments, build all
     all_examples = []
-    for dir1 in os.scandir("examples"):
-        if dir1.is_dir() and 'cmake-build' not in dir1.name:
-            for entry in os.scandir(dir1.path):
+    for d in os.scandir("examples"):
+        if d.is_dir() and 'cmake-build' not in d.name and 'cmake' not in d.name:
+            for entry in os.scandir(d.path):
                 if entry.is_dir():
-                    all_examples.append(dir1.name + '/' + entry.name)
+                    all_examples.append(d.name + '/' + entry.name)
     filter_with_input(all_examples)
     all_examples.sort()
 

From 161c95f1b7d63394b184a351f7bbaa54841c02f6 Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Thu, 4 May 2023 14:42:32 +0200
Subject: [PATCH 1689/2085] renesas: update fsp to 4.0.0

---
 tools/get_deps.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index d8b044343..4f2f7b089 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -27,7 +27,7 @@ deps_optional = {
     'hw/mcu/nxp/mcux-sdk'                      : ['f357a1150f6cf6c6b844f53f2d426bfb3e649850', 'https://github.com/NXPmicro/mcux-sdk.git'                      ],
     'hw/mcu/nxp/nxp_sdk'                       : ['845c8fc49b6fb660f06a5c45225494eacb06f00c', 'https://github.com/hathach/nxp_sdk.git'                        ],
     'hw/mcu/raspberry_pi/Pico-PIO-USB'         : ['c3715ce94b6f6391856de56081d4d9b3e98fa93d', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git'            ],
-    'hw/mcu/renesas/fsp'                       : ['8dc14709f2a6518b43f71efad70d900b7718d9f1', 'https://github.com/renesas/fsp.git'                            ],
+    'hw/mcu/renesas/fsp'                       : ['9860fae1f180340a0e3c097dc6e91323cf83b926', 'https://github.com/renesas/fsp.git'                            ],
     'hw/mcu/renesas/rx'                        : ['706b4e0cf485605c32351e2f90f5698267996023', 'https://github.com/kkitayam/rx_device.git'                     ],
     'hw/mcu/silabs/cmsis-dfp-efm32gg12b'       : ['f1c31b7887669cb230b3ea63f9b56769078960bc', 'https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git'       ],
     'hw/mcu/sony/cxd56/spresense-exported-sdk' : ['2ec2a1538362696118dc3fdf56f33dacaf8f4067', 'https://github.com/sonydevworld/spresense-exported-sdk.git'    ],

From 8a9d2b4b759990f9609a33c313b154cc7314bec7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 4 May 2023 23:29:37 +0700
Subject: [PATCH 1690/2085] wip

---
 examples/device/cdc_msc/CMakeLists.txt |  7 ++++++
 hw/bsp/imxrt/family.cmake              | 17 ++++++++++++--
 src/CMakeLists.txt                     | 31 ++++++++++++++++++++++++++
 3 files changed, 53 insertions(+), 2 deletions(-)

diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index 7eddc2422..1115f51d1 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -29,6 +29,13 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
+# define tinyusb_config target
+add_library(tinyusb_config INTERFACE)
+
+target_include_directories(tinyusb_config INTERFACE
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 95c4c0415..c18fb01ab 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -73,9 +73,22 @@ function(family_configure_target TARGET)
     ${SDK_DIR}/drivers/lpuart
     )
 
+  # define tinyusb_config target
+
+  #target_include_directories(tinyusb_config INTERFACE
+  #  )
+
+  target_compile_definitions(tinyusb_config PUBLIC
+    )
+
   # include tinyusb cmake
-  include(${TOP}/src/CMakeLists.txt)
-  add_tinyusb(${TARGET})
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+  target_link_libraries(${TARGET} PUBLIC
+    tinyusb
+    )
+
+  #include(${TOP}/src/CMakeLists.txt)
+  #add_tinyusb(${TARGET})
 
 endfunction()
 
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index a270ea8b7..ec7fe32c4 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -3,6 +3,37 @@
 
 cmake_minimum_required(VERSION 3.17)
 
+if (NOT TARGET tinyusb_config)
+  message(FATAL_ERROR "tinyusb_config target is not defined")
+endif()
+
+add_library(tinyusb STATIC
+  ${CMAKE_CURRENT_LIST_DIR}/tusb.c
+  ${CMAKE_CURRENT_LIST_DIR}/common/tusb_fifo.c
+  ${CMAKE_CURRENT_LIST_DIR}/device/usbd.c
+  ${CMAKE_CURRENT_LIST_DIR}/device/usbd_control.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/audio/audio_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/cdc/cdc_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_rt_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/hid/hid_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/midi/midi_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/msc/msc_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/net/ecm_rndis_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/net/ncm_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/usbtmc/usbtmc_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/vendor/vendor_device.c
+  ${CMAKE_CURRENT_LIST_DIR}/class/video/video_device.c
+  )
+
+target_include_directories(tinyusb PUBLIC
+  ${CMAKE_CURRENT_LIST_DIR}
+  )
+
+target_link_libraries(tinyusb PUBLIC
+  tinyusb_config
+  )
+
 function(add_tinyusb TARGET)
   target_sources(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c

From 97ee40fd7bf8b094417810a7f1816e60fdf9497b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 5 May 2023 16:51:50 +0700
Subject: [PATCH 1691/2085] add clion files

---
 .idea/runConfigurations/rp2040.xml       | 10 ++++++++++
 .idea/runConfigurations/rt10xx.xml       | 10 ++++++++++
 .idea/runConfigurations/rt10xx_pyocd.xml |  7 +++++++
 .idea/vcs.xml                            |  2 ++
 4 files changed, 29 insertions(+)
 create mode 100644 .idea/runConfigurations/rp2040.xml
 create mode 100644 .idea/runConfigurations/rt10xx.xml
 create mode 100644 .idea/runConfigurations/rt10xx_pyocd.xml

diff --git a/.idea/runConfigurations/rp2040.xml b/.idea/runConfigurations/rp2040.xml
new file mode 100644
index 000000000..227a5e2bc
--- /dev/null
+++ b/.idea/runConfigurations/rp2040.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rp2040" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc_hid" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc_hid" RUN_TARGET_NAME="cdc_msc_hid">
+    <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
+      <debugger kind="GDB" isBundled="true" />
+    </openocd>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt10xx.xml b/.idea/runConfigurations/rt10xx.xml
new file mode 100644
index 000000000..332b4d477
--- /dev/null
+++ b/.idea/runConfigurations/rt10xx.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt10xx" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver -p 55503 -t mimxrt1010" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_device_examples" TARGET_NAME="cdc_msc_freertos" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_device_examples" RUN_TARGET_NAME="cdc_msc_freertos">
+    <custom-gdb-server version="1" gdb-connect="tcp::55503" executable="$USER_HOME$/.local/bin/pyocd" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt10xx_pyocd.xml b/.idea/runConfigurations/rt10xx_pyocd.xml
new file mode 100644
index 000000000..f5c142690
--- /dev/null
+++ b/.idea/runConfigurations/rt10xx_pyocd.xml
@@ -0,0 +1,7 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt10xx pyocd" type="CMakeRunConfiguration" factoryName="Application" PROGRAM_PARAMS="flash -t mimxrt1010 $CMakeCurrentProductFile$" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc_hid" TARGET_NAME="msc_dual_lun" RUN_PATH="$USER_HOME$/.local/bin/pyocd">
+    <method v="2">
+      <option name="com.jetbrains.cidr.execution.CidrBuildBeforeRunTaskProvider$BuildBeforeRunTask" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/vcs.xml b/.idea/vcs.xml
index f05d025e7..63371256f 100644
--- a/.idea/vcs.xml
+++ b/.idea/vcs.xml
@@ -17,8 +17,10 @@
     <mapping directory="$PROJECT_DIR$/hw/mcu/nxp/nxp_sdk" vcs="Git" />
     <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/Pico-PIO-USB" vcs="Git" />
     <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/btstack" vcs="Git" />
     <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/cyw43-driver" vcs="Git" />
     <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/lwip" vcs="Git" />
+    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/mbedtls" vcs="Git" />
     <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/tinyusb" vcs="Git" />
     <mapping directory="$PROJECT_DIR$/hw/mcu/renesas/fsp" vcs="Git" />
     <mapping directory="$PROJECT_DIR$/hw/mcu/renesas/rx" vcs="Git" />

From cda5ab8b259522be962840a49a448648d3f5d308 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 5 May 2023 19:15:19 +0700
Subject: [PATCH 1692/2085] more temp work

---
 .../imxrt/boards/mimxrt1010_evk/board.cmake   |  4 +-
 hw/bsp/imxrt/family.cmake                     | 48 +++++++++------
 src/CMakeLists.txt                            | 58 +++++++++----------
 3 files changed, 60 insertions(+), 50 deletions(-)

diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
index 52d1846ea..c43de5ba4 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
@@ -1,10 +1,10 @@
 set(MCU_VARIANT MIMXRT1011)
 
-target_sources(${PROJECT} PUBLIC
+target_sources(bsp PUBLIC
   ${CMAKE_CURRENT_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
   )
 
-target_compile_definitions(${PROJECT} PUBLIC
+target_compile_definitions(bsp PUBLIC
   CPU_MIMXRT1011DAE5A
   CFG_EXAMPLE_VIDEO_READONLY
   )
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index c18fb01ab..53df88c47 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -2,6 +2,7 @@
 set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
+
 function(family_configure_target TARGET)
   if (NOT BOARD)
     message(FATAL_ERROR "BOARD not specified")
@@ -17,9 +18,14 @@ function(family_configure_target TARGET)
   set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
   set(DEPS_SUBMODULES ${SDK_DIR})
 
+  # define BSP target
+  add_library(bsp STATIC
+    )
+
+  # include board specific cmake
   include(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board.cmake)
 
-  target_compile_definitions(${TARGET} PUBLIC
+  target_compile_definitions(bsp PUBLIC
     CFG_TUSB_MCU=OPT_MCU_MIMXRT
     __ARMVFP__=0
     __ARMFPV5__=0
@@ -32,11 +38,11 @@ function(family_configure_target TARGET)
     --specs=nano.specs
     )
 
-  target_sources(${TARGET} PUBLIC
+  target_sources(bsp PUBLIC
     # TinyUSB
-    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
-    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
-    ${TOP}/src/portable/ehci/ehci.c
+#    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+#    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+#    ${TOP}/src/portable/ehci/ehci.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${SDK_DIR}/drivers/common/fsl_common.c
@@ -49,18 +55,18 @@ function(family_configure_target TARGET)
     )
 
   if (TOOLCHAIN STREQUAL "gcc")
-    target_sources(${TARGET} PUBLIC
+    target_sources(bsp PUBLIC
       ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
       )
 
-    target_link_options(${TARGET} PUBLIC
+    target_link_options(bsp PUBLIC
       "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld"
       )
   else ()
     # TODO support IAR
   endif ()
 
-  target_include_directories(${TARGET} PUBLIC
+  target_include_directories(bsp PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
@@ -73,25 +79,31 @@ function(family_configure_target TARGET)
     ${SDK_DIR}/drivers/lpuart
     )
 
-  # define tinyusb_config target
+  if(NOT TARGET tinyusb_config)
+    message(FATAL_ERROR "tinyusb_config target not found")
+  endif()
 
-  #target_include_directories(tinyusb_config INTERFACE
-  #  )
-
-  target_compile_definitions(tinyusb_config PUBLIC
+  target_compile_definitions(tinyusb_config INTERFACE
+    CFG_TUSB_MCU=OPT_MCU_MIMXRT
     )
 
-  # include tinyusb cmake
+  # include tinyusb CMakeList.txt for tinyusb target
   add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+  add_library(tinyusb_port STATIC
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+    ${TOP}/src/portable/ehci/ehci.c
+    )
+
+
   target_link_libraries(${TARGET} PUBLIC
     tinyusb
+    bsp
     )
-
-  #include(${TOP}/src/CMakeLists.txt)
-  #add_tinyusb(${TARGET})
-
 endfunction()
 
+
 function(family_add_freertos_config TARGET)
   add_library(freertos_config INTERFACE)
 
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index ec7fe32c4..e7e3125a2 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -34,33 +34,31 @@ target_link_libraries(tinyusb PUBLIC
   tinyusb_config
   )
 
-function(add_tinyusb TARGET)
-  target_sources(${TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c
-    )
-
-  target_include_directories(${TARGET} PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    )
-
-  # enable all possible warnings
-  target_compile_options(${TARGET} PUBLIC
-
-    )
-
-endfunction()
+#function(add_tinyusb TARGET)
+#  target_sources(${TARGET} PUBLIC
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c
+#    )
+#
+#  target_include_directories(${TARGET} PUBLIC
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+#    )
+#
+#  # enable all possible warnings
+#  target_compile_options(${TARGET} PUBLIC
+#    )
+#endfunction()

From f15f79df5d242fdeff06dff14a9550905f29d514 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 6 May 2023 15:14:54 +0700
Subject: [PATCH 1693/2085] cmake work well with imxrt

---
 examples/CMakeLists.txt                       |   6 +-
 examples/device/CMakeLists.txt                |   2 +-
 examples/device/audio_test/CMakeLists.txt     |   4 +-
 .../audio_test_multi_rate/CMakeLists.txt      |   4 +-
 examples/device/board_test/CMakeLists.txt     |   8 +-
 examples/device/cdc_dual_ports/CMakeLists.txt |  10 +-
 examples/device/cdc_msc/CMakeLists.txt        |  15 +-
 .../device/cdc_msc_freertos/CMakeLists.txt    |   2 +-
 .../hid_composite_freertos/CMakeLists.txt     |   2 +-
 examples/host/cdc_msc_hid/CMakeLists.txt      |   2 +-
 hw/bsp/family_support.cmake                   |   4 +-
 .../imxrt/boards/mimxrt1010_evk/board.cmake   |  17 +-
 hw/bsp/imxrt/family.cmake                     | 151 ++++++++++--------
 src/CMakeLists.txt                            | 106 ++++++------
 14 files changed, 167 insertions(+), 166 deletions(-)

diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt
index d91d8ca62..a23b4ed62 100644
--- a/examples/CMakeLists.txt
+++ b/examples/CMakeLists.txt
@@ -3,8 +3,8 @@ cmake_minimum_required(VERSION 3.5)
 #set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 include(${CMAKE_CURRENT_SOURCE_DIR}/../hw/bsp/family_support.cmake)
 
-project(tinyusb_examples)
+project(tinyusb_examples C CXX ASM)
 
 add_subdirectory(device)
-add_subdirectory(dual)
-add_subdirectory(host)
+#add_subdirectory(dual)
+#add_subdirectory(host)
diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index 5520209e0..ac1bbf161 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 3.5)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
 
-project(tinyusb_device_examples)
+project(tinyusb_device_examples C CXX ASM)
 family_initialize_project(tinyusb_device_examples ${CMAKE_CURRENT_LIST_DIR})
 
 # family_add_subdirectory will filter what to actually add based on selected FAMILY
diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt
index b0889285c..87b7d07d4 100644
--- a/examples/device/audio_test/CMakeLists.txt
+++ b/examples/device/audio_test/CMakeLists.txt
@@ -21,12 +21,12 @@ add_executable(${PROJECT})
 target_sources(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
   ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-)
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
-)
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
diff --git a/examples/device/audio_test_multi_rate/CMakeLists.txt b/examples/device/audio_test_multi_rate/CMakeLists.txt
index b0889285c..87b7d07d4 100644
--- a/examples/device/audio_test_multi_rate/CMakeLists.txt
+++ b/examples/device/audio_test_multi_rate/CMakeLists.txt
@@ -21,12 +21,12 @@ add_executable(${PROJECT})
 target_sources(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
   ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-)
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
-)
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index c48efdaa5..4ab8d5a65 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -19,13 +19,13 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt
index d142e9c04..87b7d07d4 100644
--- a/examples/device/cdc_dual_ports/CMakeLists.txt
+++ b/examples/device/cdc_dual_ports/CMakeLists.txt
@@ -19,14 +19,14 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index 1115f51d1..63030e733 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -19,20 +19,13 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
-
-# define tinyusb_config target
-add_library(tinyusb_config INTERFACE)
-
-target_include_directories(tinyusb_config INTERFACE
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 699860223..75ec33145 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -35,7 +35,7 @@ target_include_directories(${PROJECT} PUBLIC
 family_configure_device_example(${PROJECT})
 
 if (NOT TARGET freertos_kernel)
-family_add_freertos_config(${PROJECT})
+family_configure_freertos_example(${PROJECT})
 add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel)
 endif()
 
diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt
index 9b0ffa4b6..30729f438 100644
--- a/examples/device/hid_composite_freertos/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/CMakeLists.txt
@@ -34,7 +34,7 @@ target_include_directories(${PROJECT} PUBLIC
 family_configure_device_example(${PROJECT})
 
 if (NOT TARGET freertos_kernel)
-family_add_freertos_config(${PROJECT})
+family_configure_freertos_example(${PROJECT})
 add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel)
 endif()
 
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index b66ff2382..42dac5be7 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -5,7 +5,7 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index cc95dde9e..26baa6365 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -1,4 +1,6 @@
 if (NOT TARGET _family_support_marker)
+    add_library(_family_support_marker INTERFACE)
+
     include(CMakePrintHelpers)
 
     # Default to gcc
@@ -6,8 +8,6 @@ if (NOT TARGET _family_support_marker)
         set(TOOLCHAIN gcc)
     endif()
 
-    add_library(_family_support_marker INTERFACE)
-
     if (NOT FAMILY)
         message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line")
     endif()
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
index c43de5ba4..d4015e488 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
@@ -1,10 +1,11 @@
 set(MCU_VARIANT MIMXRT1011)
 
-target_sources(bsp PUBLIC
-  ${CMAKE_CURRENT_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
-  )
-
-target_compile_definitions(bsp PUBLIC
-  CPU_MIMXRT1011DAE5A
-  CFG_EXAMPLE_VIDEO_READONLY
-  )
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1011DAE5A
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 53df88c47..1731d9e60 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -1,50 +1,34 @@
+if (TARGET _imxrt_family_inclusion_marker)
+  return()
+endif ()
+
+add_library(_imxrt_family_inclusion_marker INTERFACE)
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
-function(family_configure_target TARGET)
-  if (NOT BOARD)
-    message(FATAL_ERROR "BOARD not specified")
-  endif ()
 
-  # set output name to .elf
-  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
-
-  # TOP is absolute path to root directory of TinyUSB git repo
-  set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
-  get_filename_component(TOP "${TOP}" REALPATH)
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+set(BOARD_TARGET board_${BOARD})
+if (NOT TARGET ${BOARD_TARGET})
+  # TOP is path to root directory
+  set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
 
   set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
-  set(DEPS_SUBMODULES ${SDK_DIR})
+  set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
-  # define BSP target
-  add_library(bsp STATIC
-    )
-
-  # include board specific cmake
-  include(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-  target_compile_definitions(bsp PUBLIC
-    CFG_TUSB_MCU=OPT_MCU_MIMXRT
-    __ARMVFP__=0
-    __ARMFPV5__=0
-    XIP_EXTERNAL_FLASH=1
-    XIP_BOOT_HEADER_ENABLE=1
-    )
-
-  target_link_options(${TARGET} PUBLIC
-    --specs=nosys.specs
-    --specs=nano.specs
-    )
-
-  target_sources(bsp PUBLIC
-    # TinyUSB
-#    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
-#    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
-#    ${TOP}/src/portable/ehci/ehci.c
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+  add_library(${BOARD_TARGET} STATIC
     ${SDK_DIR}/drivers/common/fsl_common.c
     ${SDK_DIR}/drivers/igpio/fsl_gpio.c
     ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
@@ -53,24 +37,15 @@ function(family_configure_target TARGET)
     ${SDK_DIR}/devices/${MCU_VARIANT}/project_template/clock_config.c
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
     )
-
-  if (TOOLCHAIN STREQUAL "gcc")
-    target_sources(bsp PUBLIC
-      ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
-      )
-
-    target_link_options(bsp PUBLIC
-      "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld"
-      )
-  else ()
-    # TODO support IAR
-  endif ()
-
-  target_include_directories(bsp PUBLIC
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    ${SDK_DIR}/CMSIS/Include
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_TUSB_MCU=OPT_MCU_MIMXRT
+    __ARMVFP__=0
+    __ARMFPV5__=0
+    XIP_EXTERNAL_FLASH=1
+    XIP_BOOT_HEADER_ENABLE=1
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMSIS_DIR}/CMSIS/Core/Include
     ${SDK_DIR}/devices/${MCU_VARIANT}
     ${SDK_DIR}/devices/${MCU_VARIANT}/project_template
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
@@ -78,33 +53,71 @@ function(family_configure_target TARGET)
     ${SDK_DIR}/drivers/igpio
     ${SDK_DIR}/drivers/lpuart
     )
+  update_board(${BOARD_TARGET})
 
-  if(NOT TARGET tinyusb_config)
-    message(FATAL_ERROR "tinyusb_config target not found")
-  endif()
+  if (TOOLCHAIN STREQUAL "gcc")
+    target_sources(${BOARD_TARGET} PUBLIC
+      ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld"
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  else ()
+    # TODO support IAR
+  endif ()
+endif () # BOARD_TARGET
 
-  target_compile_definitions(tinyusb_config INTERFACE
-    CFG_TUSB_MCU=OPT_MCU_MIMXRT
-    )
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_target TARGET)
+  # set output name to .elf
+  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
 
-  # include tinyusb CMakeList.txt for tinyusb target
-  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+  # TOP is path to root directory
+  set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
 
-  add_library(tinyusb_port STATIC
+  #---------- BSP_TARGET ----------
+  # BSP_TARGET is built for each example since it depends on example's tusb_config.h
+  set(BSP_TARGET "${TARGET}_bsp_${BOARD}")
+  add_library(${BSP_TARGET} STATIC
+    # TinyUSB
     ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
     ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
     ${TOP}/src/portable/ehci/ehci.c
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    )
+  target_include_directories(${BSP_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
+  #---------- TinyUSB ----------
+  # tinyusb target is built for each example since it depends on example's tusb_config.h
+  set(TINYUSB_TARGET_PREFIX ${TARGET})
+  add_library(${TARGET}_tinyusb_config INTERFACE)
 
-  target_link_libraries(${TARGET} PUBLIC
-    tinyusb
-    bsp
+  target_include_directories(${TARGET}_tinyusb_config INTERFACE
+    ${CMAKE_CURRENT_SOURCE_DIR}/src
     )
+  target_compile_definitions(${TARGET}_tinyusb_config INTERFACE
+    CFG_TUSB_MCU=OPT_MCU_MIMXRT
+    )
+
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+  # Link dependencies
+  target_link_libraries(${BSP_TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}_tinyusb)
+  target_link_libraries(${TARGET} PUBLIC ${BSP_TARGET} ${TARGET}_tinyusb)
 endfunction()
 
 
-function(family_add_freertos_config TARGET)
+function(family_configure_freertos_example TARGET)
   add_library(freertos_config INTERFACE)
 
   # add path to FreeRTOSConfig.h
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index e7e3125a2..21aa23d54 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -3,62 +3,56 @@
 
 cmake_minimum_required(VERSION 3.17)
 
-if (NOT TARGET tinyusb_config)
-  message(FATAL_ERROR "tinyusb_config target is not defined")
+# Add tinyusb to a target
+function(add_tinyusb TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    )
+  # enable all possible warnings
+  target_compile_options(${TARGET} PUBLIC
+    )
+endfunction()
+
+set(TINYUSB_TARGET "tinyusb")
+set(TINYUSB_CONFIG_TARGET "tinyusb_config")
+
+if (DEFINED TINYUSB_TARGET_PREFIX)
+  set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}_${TINYUSB_TARGET}")
+  set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET_PREFIX}_${TINYUSB_CONFIG_TARGET}")
+endif ()
+
+if (DEFINED TINYUSB_TARGET_SUFFIX)
+  set(TINYUSB_TARGET "${TINYUSB_TARGET}_${TINYUSB_TARGET_SUFFIX}")
+  set(TINYUSB_CONFIG_TARGET "${TINYUSB_CONFIG_TARGET}_${TINYUSB_TARGET_SUFFIX}")
+endif ()
+
+add_library(${TINYUSB_TARGET} STATIC)
+add_tinyusb(${TINYUSB_TARGET})
+
+# Link with tinyusb_config target
+
+if (NOT TARGET ${TINYUSB_CONFIG_TARGET})
+  message(FATAL_ERROR "${TINYUSB_CONFIG_TARGET} target is not defined")
 endif()
 
-add_library(tinyusb STATIC
-  ${CMAKE_CURRENT_LIST_DIR}/tusb.c
-  ${CMAKE_CURRENT_LIST_DIR}/common/tusb_fifo.c
-  ${CMAKE_CURRENT_LIST_DIR}/device/usbd.c
-  ${CMAKE_CURRENT_LIST_DIR}/device/usbd_control.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/audio/audio_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/cdc/cdc_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/dfu/dfu_rt_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/hid/hid_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/midi/midi_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/msc/msc_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/net/ecm_rndis_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/net/ncm_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/usbtmc/usbtmc_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/vendor/vendor_device.c
-  ${CMAKE_CURRENT_LIST_DIR}/class/video/video_device.c
+target_link_libraries(${TINYUSB_TARGET} PUBLIC
+  ${TINYUSB_CONFIG_TARGET}
   )
-
-target_include_directories(tinyusb PUBLIC
-  ${CMAKE_CURRENT_LIST_DIR}
-  )
-
-target_link_libraries(tinyusb PUBLIC
-  tinyusb_config
-  )
-
-#function(add_tinyusb TARGET)
-#  target_sources(${TARGET} PUBLIC
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/dfu/dfu_rt_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/midi/midi_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ecm_rndis_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/net/ncm_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c
-#    )
-#
-#  target_include_directories(${TARGET} PUBLIC
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-#    )
-#
-#  # enable all possible warnings
-#  target_compile_options(${TARGET} PUBLIC
-#    )
-#endfunction()

From 6945c594d53ca6a35f1f0bb120b5a652c6ce9e84 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 7 May 2023 22:09:08 +0700
Subject: [PATCH 1694/2085] update all device cmake example for imx

---
 .idea/runConfigurations/rt10xx_pyocd.xml      |  7 ---
 examples/CMakeLists.txt                       |  6 +--
 examples/cmake/cpu/cortex-m7.cmake            | 18 ++++---
 examples/device/CMakeLists.txt                |  2 +-
 .../device/cdc_msc_freertos/CMakeLists.txt    | 10 +---
 .../hid_composite_freertos/CMakeLists.txt     | 10 +---
 examples/dual/CMakeLists.txt                  |  4 +-
 .../host_hid_to_device_cdc/CMakeLists.txt     |  4 +-
 examples/host/CMakeLists.txt                  |  4 +-
 examples/host/bare_api/CMakeLists.txt         |  4 +-
 examples/host/hid_controller/CMakeLists.txt   |  4 +-
 .../host/msc_file_explorer/CMakeLists.txt     |  4 +-
 hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt    |  8 +++
 .../imxrt/boards/mimxrt1010_evk/board.cmake   |  3 ++
 hw/bsp/imxrt/family.cmake                     | 52 ++++++++++++-------
 src/CMakeLists.txt                            |  8 +--
 16 files changed, 81 insertions(+), 67 deletions(-)
 delete mode 100644 .idea/runConfigurations/rt10xx_pyocd.xml
 create mode 100644 hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt

diff --git a/.idea/runConfigurations/rt10xx_pyocd.xml b/.idea/runConfigurations/rt10xx_pyocd.xml
deleted file mode 100644
index f5c142690..000000000
--- a/.idea/runConfigurations/rt10xx_pyocd.xml
+++ /dev/null
@@ -1,7 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt10xx pyocd" type="CMakeRunConfiguration" factoryName="Application" PROGRAM_PARAMS="flash -t mimxrt1010 $CMakeCurrentProductFile$" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc_hid" TARGET_NAME="msc_dual_lun" RUN_PATH="$USER_HOME$/.local/bin/pyocd">
-    <method v="2">
-      <option name="com.jetbrains.cidr.execution.CidrBuildBeforeRunTaskProvider$BuildBeforeRunTask" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt
index a23b4ed62..91c9fb098 100644
--- a/examples/CMakeLists.txt
+++ b/examples/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 #set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 include(${CMAKE_CURRENT_SOURCE_DIR}/../hw/bsp/family_support.cmake)
@@ -6,5 +6,5 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../hw/bsp/family_support.cmake)
 project(tinyusb_examples C CXX ASM)
 
 add_subdirectory(device)
-#add_subdirectory(dual)
-#add_subdirectory(host)
+add_subdirectory(dual)
+add_subdirectory(host)
diff --git a/examples/cmake/cpu/cortex-m7.cmake b/examples/cmake/cpu/cortex-m7.cmake
index 2b258726f..458d8b438 100644
--- a/examples/cmake/cpu/cortex-m7.cmake
+++ b/examples/cmake/cpu/cortex-m7.cmake
@@ -1,6 +1,12 @@
-set(TOOLCHAIN_COMMON_FLAGS
-  -mthumb
-  -mcpu=cortex-m7
-  -mfloat-abi=hard
-  -mfpu=fpv5-d16
-  )
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m7
+    -mfloat-abi=hard
+    -mfpu=fpv5-d16
+    )
+
+  set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
+else ()
+  # TODO support IAR
+endif ()
diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index ac1bbf161..5b077a5e1 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
 
diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 75ec33145..319ad0356 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -34,11 +34,5 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
 
-if (NOT TARGET freertos_kernel)
-family_configure_freertos_example(${PROJECT})
-add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel)
-endif()
-
-target_link_libraries(${PROJECT} PUBLIC
-  freertos_kernel
-  )
+# Add FreeRTOS for this example
+family_add_freertos(${PROJECT})
diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt
index 30729f438..211904cf9 100644
--- a/examples/device/hid_composite_freertos/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/CMakeLists.txt
@@ -33,11 +33,5 @@ target_include_directories(${PROJECT} PUBLIC
 # in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT})
 
-if (NOT TARGET freertos_kernel)
-family_configure_freertos_example(${PROJECT})
-add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/../../../lib/FreeRTOS-Kernel lib/FreeRTOS-Kernel)
-endif()
-
-target_link_libraries(${PROJECT} PUBLIC
-  freertos_kernel
-  )
+# Add FreeRTOS for this example
+family_add_freertos(${PROJECT})
diff --git a/examples/dual/CMakeLists.txt b/examples/dual/CMakeLists.txt
index d2f9a42f0..d211c8b83 100644
--- a/examples/dual/CMakeLists.txt
+++ b/examples/dual/CMakeLists.txt
@@ -1,8 +1,8 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
 
-project(tinyusb_dual_examples)
+project(tinyusb_dual_examples C CXX ASM)
 family_initialize_project(tinyusb_dual_examples ${CMAKE_CURRENT_LIST_DIR})
 if (FAMILY STREQUAL "rp2040" AND NOT TARGET tinyusb_pico_pio_usb)
     message("Skipping dual host/device mode examples as Pico-PIO-USB is not available")
diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index 724d1e119..3505d39eb 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -1,11 +1,11 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/host/CMakeLists.txt b/examples/host/CMakeLists.txt
index 758973ab2..bedd2220b 100644
--- a/examples/host/CMakeLists.txt
+++ b/examples/host/CMakeLists.txt
@@ -1,8 +1,8 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
 
-project(tinyusb_host_examples)
+project(tinyusb_host_examples C CXX ASM)
 family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
 
 # family_add_subdirectory will filter what to actually add based on selected FAMILY
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 616edd4ac..b6d8c9c89 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -1,11 +1,11 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index ac3070b82..e1d2f1642 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -1,11 +1,11 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 7955b3078..2ab0aa881 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -1,11 +1,11 @@
-cmake_minimum_required(VERSION 3.5)
+cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
-project(${PROJECT})
+project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
diff --git a/hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt b/hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt
new file mode 100644
index 000000000..0bacaf824
--- /dev/null
+++ b/hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt
@@ -0,0 +1,8 @@
+if (NOT TARGET freertos_config)
+  add_library(freertos_config INTERFACE)
+
+  # add path to FreeRTOSConfig.h
+  target_include_directories(freertos_config SYSTEM INTERFACE
+    ${CMAKE_CURRENT_LIST_DIR}
+    )
+endif()
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
index d4015e488..02955e356 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
@@ -1,5 +1,8 @@
 set(MCU_VARIANT MIMXRT1011)
 
+set(JLINK_DEVICE MIMXRT1011DAE5A)
+set(PYOCD_TARGET mimxrt1010)
+
 function(update_board TARGET)
   target_sources(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 1731d9e60..653885bb2 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -81,7 +81,7 @@ function(family_configure_target TARGET)
 
   #---------- BSP_TARGET ----------
   # BSP_TARGET is built for each example since it depends on example's tusb_config.h
-  set(BSP_TARGET "${TARGET}_bsp_${BOARD}")
+  set(BSP_TARGET "${TARGET}-bsp")
   add_library(${BSP_TARGET} STATIC
     # TinyUSB
     ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -98,13 +98,13 @@ function(family_configure_target TARGET)
 
   #---------- TinyUSB ----------
   # tinyusb target is built for each example since it depends on example's tusb_config.h
-  set(TINYUSB_TARGET_PREFIX ${TARGET})
-  add_library(${TARGET}_tinyusb_config INTERFACE)
+  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+  add_library(${TARGET}-tinyusb_config INTERFACE)
 
-  target_include_directories(${TARGET}_tinyusb_config INTERFACE
+  target_include_directories(${TARGET}-tinyusb_config INTERFACE
     ${CMAKE_CURRENT_SOURCE_DIR}/src
     )
-  target_compile_definitions(${TARGET}_tinyusb_config INTERFACE
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
     CFG_TUSB_MCU=OPT_MCU_MIMXRT
     )
 
@@ -112,25 +112,41 @@ function(family_configure_target TARGET)
   add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
 
   # Link dependencies
-  target_link_libraries(${BSP_TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}_tinyusb)
-  target_link_libraries(${TARGET} PUBLIC ${BSP_TARGET} ${TARGET}_tinyusb)
+  target_link_libraries(${BSP_TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+  target_link_libraries(${TARGET} PUBLIC ${BSP_TARGET} ${TARGET}-tinyusb)
+
+  # Flash Target
+  add_custom_target(${TARGET}-pyocd
+    COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
+    )
 endfunction()
 
 
-function(family_configure_freertos_example TARGET)
-  add_library(freertos_config INTERFACE)
+function(family_add_freertos TARGET)
+  # freertos_config
+  add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config)
 
-  # add path to FreeRTOSConfig.h
-  target_include_directories(freertos_config SYSTEM INTERFACE
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig
+  ## freertos
+  if (NOT TARGET freertos_kernel)
+    add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
+  endif ()
+
+  # Add FreeRTOS option to tinyusb_config
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_OS=OPT_OS_FREERTOS
+    )
+  # tinyusb need to be linked with freeRTOS kernel
+  target_link_libraries(${TARGET}-tinyusb PUBLIC
+    freertos_kernel
     )
 
-  # select freertos port
-  if (TOOLCHAIN STREQUAL "gcc")
-    set(FREERTOS_PORT "GCC_ARM_CM7" CACHE INTERNAL "")
-  else ()
-    # TODO support IAR
-  endif ()
+  target_link_libraries(${TARGET}-tinyusb PUBLIC
+    freertos_kernel
+    )
+
+  target_link_libraries(${TARGET} PUBLIC
+    freertos_kernel
+    )
 endfunction()
 
 function(family_configure_device_example TARGET)
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 21aa23d54..02f962f44 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -35,13 +35,13 @@ set(TINYUSB_TARGET "tinyusb")
 set(TINYUSB_CONFIG_TARGET "tinyusb_config")
 
 if (DEFINED TINYUSB_TARGET_PREFIX)
-  set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}_${TINYUSB_TARGET}")
-  set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET_PREFIX}_${TINYUSB_CONFIG_TARGET}")
+  set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_TARGET}")
+  set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_CONFIG_TARGET}")
 endif ()
 
 if (DEFINED TINYUSB_TARGET_SUFFIX)
-  set(TINYUSB_TARGET "${TINYUSB_TARGET}_${TINYUSB_TARGET_SUFFIX}")
-  set(TINYUSB_CONFIG_TARGET "${TINYUSB_CONFIG_TARGET}_${TINYUSB_TARGET_SUFFIX}")
+  set(TINYUSB_TARGET "${TINYUSB_TARGET}${TINYUSB_TARGET_SUFFIX}")
+  set(TINYUSB_CONFIG_TARGET "${TINYUSB_CONFIG_TARGET}${TINYUSB_TARGET_SUFFIX}")
 endif ()
 
 add_library(${TINYUSB_TARGET} STATIC)

From 654f1821769f50c44f786032bedfe417a9ad4d0f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 May 2023 00:24:48 +0700
Subject: [PATCH 1695/2085] build host examples with imx

---
 examples/host/cdc_msc_hid/CMakeLists.txt      | 14 +++---
 examples/host/hid_controller/CMakeLists.txt   | 10 ++--
 .../host/msc_file_explorer/CMakeLists.txt     | 20 ++++----
 hw/bsp/board.c                                | 49 -------------------
 hw/bsp/imxrt/family.cmake                     |  7 +++
 src/CMakeLists.txt                            |  9 ++++
 6 files changed, 38 insertions(+), 71 deletions(-)

diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 42dac5be7..68b52e274 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -14,16 +14,16 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index e1d2f1642..e27f83c53 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -14,14 +14,14 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 2ab0aa881..2d5600059 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -14,19 +14,19 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
-        ${TOP}/lib/fatfs/source/ff.c
-        ${TOP}/lib/fatfs/source/ffsystem.c
-        ${TOP}/lib/fatfs/source/ffunicode.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+  ${TOP}/lib/fatfs/source/ff.c
+  ${TOP}/lib/fatfs/source/ffsystem.c
+  ${TOP}/lib/fatfs/source/ffunicode.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        ${TOP}/lib/fatfs/source
-        ${TOP}/lib/embedded-cli
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  ${TOP}/lib/fatfs/source
+  ${TOP}/lib/embedded-cli
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index e715bdf2e..66ffcb199 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -25,55 +25,6 @@
 
 #include "board.h"
 
-#if 0
-#define LED_PHASE_MAX   8
-
-static struct
-{
-  uint32_t phase[LED_PHASE_MAX];
-  uint8_t phase_count;
-
-  bool led_state;
-  uint8_t current_phase;
-  uint32_t current_ms;
-}led_pattern;
-
-void board_led_pattern(uint32_t const phase_ms[], uint8_t count)
-{
-  memcpy(led_pattern.phase, phase_ms, 4*count);
-  led_pattern.phase_count = count;
-
-  // reset with 1st phase is on
-  led_pattern.current_ms = board_millis();
-  led_pattern.current_phase = 0;
-  led_pattern.led_state = true;
-  board_led_on();
-}
-
-void board_led_task(void)
-{
-  if ( led_pattern.phase_count == 0 ) return;
-
-  uint32_t const duration = led_pattern.phase[led_pattern.current_phase];
-
-  // return if not enough time
-  if (board_millis() - led_pattern.current_ms < duration) return;
-
-  led_pattern.led_state = !led_pattern.led_state;
-  board_led_write(led_pattern.led_state);
-
-  led_pattern.current_ms += duration;
-  led_pattern.current_phase++;
-
-  if (led_pattern.current_phase == led_pattern.phase_count)
-  {
-    led_pattern.current_phase = 0;
-    led_pattern.led_state = true;
-    board_led_on();
-  }
-}
-#endif
-
 //--------------------------------------------------------------------+
 // newlib read()/write() retarget
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 653885bb2..b180f725e 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -12,6 +12,8 @@ endif ()
 set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
+set(FAMILY_MCUS MIMXRT CACHE INTERNAL "")
+
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
@@ -89,6 +91,7 @@ function(family_configure_target TARGET)
     ${TOP}/src/portable/ehci/ehci.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
     )
   target_include_directories(${BSP_TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
@@ -152,3 +155,7 @@ endfunction()
 function(family_configure_device_example TARGET)
   family_configure_target(${TARGET})
 endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 02f962f44..0b99d8919 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -6,8 +6,10 @@ cmake_minimum_required(VERSION 3.17)
 # Add tinyusb to a target
 function(add_tinyusb TARGET)
   target_sources(${TARGET} PUBLIC
+    # common
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c
+    # device
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/device/usbd_control.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/audio/audio_device.c
@@ -22,6 +24,13 @@ function(add_tinyusb TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/usbtmc/usbtmc_device.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_device.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/video/video_device.c
+    # host
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/host/usbh.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/host/hub.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/cdc/cdc_host.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_host.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_host.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_host.c
     )
   target_include_directories(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}

From 4fc4f35a8af6465eb2137f765e994de1029e9c5a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 May 2023 17:25:47 +0700
Subject: [PATCH 1696/2085] fix linking missing ivt symbol for imxrt with cmake

changed device port = 0, host port =1 for imxrt 1060 and 1064
---
 .../runConfigurations/{rt10xx.xml => rt1010.xml}  |  2 +-
 .idea/runConfigurations/tinyusb_examples.xml      |  5 -----
 examples/cmake/cpu/cortex-m7.cmake                |  2 +-
 examples/cmake/toolchain/arm_gcc.cmake            |  8 +++++++-
 examples/cmake/toolchain/set_flags.cmake          |  3 +++
 examples/device/cdc_msc/CMakeLists.txt            |  1 +
 examples/rules.mk                                 |  2 +-
 hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake    | 15 +++++++++++++++
 hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk       |  4 ++--
 hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake    | 15 +++++++++++++++
 hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk       |  4 ++--
 hw/bsp/imxrt/family.c                             |  1 +
 hw/bsp/imxrt/family.cmake                         | 12 +++++++++++-
 13 files changed, 60 insertions(+), 14 deletions(-)
 rename .idea/runConfigurations/{rt10xx.xml => rt1010.xml} (74%)
 delete mode 100644 .idea/runConfigurations/tinyusb_examples.xml
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake

diff --git a/.idea/runConfigurations/rt10xx.xml b/.idea/runConfigurations/rt1010.xml
similarity index 74%
rename from .idea/runConfigurations/rt10xx.xml
rename to .idea/runConfigurations/rt1010.xml
index 332b4d477..700cb5732 100644
--- a/.idea/runConfigurations/rt10xx.xml
+++ b/.idea/runConfigurations/rt1010.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt10xx" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver -p 55503 -t mimxrt1010" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_device_examples" TARGET_NAME="cdc_msc_freertos" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_device_examples" RUN_TARGET_NAME="cdc_msc_freertos">
+  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver -p 55503 -t mimxrt1010" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::55503" executable="$USER_HOME$/.local/bin/pyocd" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/tinyusb_examples.xml b/.idea/runConfigurations/tinyusb_examples.xml
deleted file mode 100644
index 60e586bbc..000000000
--- a/.idea/runConfigurations/tinyusb_examples.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="tinyusb_examples" type="CMakeListConfigurationType" factoryName="CMakeListConfigurationFactory">
-    <method v="2" />
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/examples/cmake/cpu/cortex-m7.cmake b/examples/cmake/cpu/cortex-m7.cmake
index 458d8b438..481c86bc5 100644
--- a/examples/cmake/cpu/cortex-m7.cmake
+++ b/examples/cmake/cpu/cortex-m7.cmake
@@ -1,5 +1,5 @@
 if (TOOLCHAIN STREQUAL "gcc")
-  set(TOOLCHAIN_COMMON_FLAGS
+  list(APPEND TOOLCHAIN_COMMON_FLAGS
     -mthumb
     -mcpu=cortex-m7
     -mfloat-abi=hard
diff --git a/examples/cmake/toolchain/arm_gcc.cmake b/examples/cmake/toolchain/arm_gcc.cmake
index c5937192e..c7b6cff98 100644
--- a/examples/cmake/toolchain/arm_gcc.cmake
+++ b/examples/cmake/toolchain/arm_gcc.cmake
@@ -25,7 +25,13 @@ list(APPEND TOOLCHAIN_COMMON_FLAGS
   -fno-strict-aliasing
   )
 
-set(TOOLCHAIN_WARNING_FLAGS
+list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS
+  -Wl,--print-memory-usage
+  -Wl,--gc-sections
+  -Wl,--cref
+  )
+
+list(APPEND TOOLCHAIN_WARNING_FLAGS
   -Wall
   -Wextra
   -Werror
diff --git a/examples/cmake/toolchain/set_flags.cmake b/examples/cmake/toolchain/set_flags.cmake
index da381c254..27631abcd 100644
--- a/examples/cmake/toolchain/set_flags.cmake
+++ b/examples/cmake/toolchain/set_flags.cmake
@@ -11,6 +11,9 @@ foreach(LANG IN ITEMS C CXX ASM)
     set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-Og")
 endforeach()
 
+# Linker
+list(JOIN TOOLCHAIN_EXE_LINKER_FLAGS " " CMAKE_EXE_LINKER_FLAGS_INIT)
+
 # try_compile is cmake test compiling its own example,
 # pass -nostdlib to skip stdlib linking
 get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index 63030e733..4ec172f17 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -1,4 +1,5 @@
 cmake_minimum_required(VERSION 3.17)
+set_property(GLOBAL PROPERTY USE_FOLDERS ON)
 
 include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
 
diff --git a/examples/rules.mk b/examples/rules.mk
index c125408df..3ec3c880b 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -169,7 +169,7 @@ $(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
 
 $(BUILD)/$(PROJECT).elf: $(OBJ)
 	@echo LINK $@
-	@$(LD) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group
+	@$(LD) -o $@ $(LDFLAGS) $^ -Wl,--print-memory-usage -Wl,--start-group $(LIBS) -Wl,--end-group
 
 endif
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
new file mode 100644
index 000000000..033f9fcf9
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT MIMXRT1062)
+
+set(JLINK_DEVICE MIMXRT1062xxx6A)
+set(PYOCD_TARGET mimxrt1060)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1060_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1062DVL6A
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
index d21063c99..0317ee452 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk
@@ -7,8 +7,8 @@ JLINK_DEVICE = MIMXRT1062xxx6A
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1060
 
-BOARD_TUD_RHPORT = 1
-BOARD_TUH_RHPORT = 0
+BOARD_TUD_RHPORT = 0
+BOARD_TUH_RHPORT = 1
 
 # flash using pyocd
 flash: flash-pyocd
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake
new file mode 100644
index 000000000..925664b41
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT MIMXRT1064)
+
+set(JLINK_DEVICE MIMXRT1064xxx6A)
+set(PYOCD_TARGET mimxrt1064)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1064_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1064DVL6A
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
index 00b574c52..ddde419ae 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk
@@ -7,8 +7,8 @@ JLINK_DEVICE = MIMXRT1064xxx6A
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1064
 
-BOARD_TUD_RHPORT = 1
-BOARD_TUH_RHPORT = 0
+BOARD_TUD_RHPORT = 0
+BOARD_TUH_RHPORT = 1
 
 # flash using pyocd
 flash: flash-pyocd
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 5eb672c24..b009b27e1 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -47,6 +47,7 @@
 #endif
 
 // needed by fsl_flexspi_nor_boot
+TU_ATTR_USED
 const uint8_t dcd_data[] = { 0x00 };
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index b180f725e..9e084b4fd 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -63,8 +63,13 @@ if (NOT TARGET ${BOARD_TARGET})
       )
     target_link_options(${BOARD_TARGET} PUBLIC
       "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld"
+      "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
+      # nanolib
       --specs=nosys.specs
       --specs=nano.specs
+      # force linker to look for these symbols
+      -Wl,-uimage_vector_table
+      -Wl,-ug_boot_data
       )
   else ()
     # TODO support IAR
@@ -116,12 +121,17 @@ function(family_configure_target TARGET)
 
   # Link dependencies
   target_link_libraries(${BSP_TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
-  target_link_libraries(${TARGET} PUBLIC ${BSP_TARGET} ${TARGET}-tinyusb)
+  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${BSP_TARGET} ${TARGET}-tinyusb)
 
   # Flash Target
   add_custom_target(${TARGET}-pyocd
     COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
     )
+
+  # group target
+  set_target_properties(${BSP_TARGET} ${TARGET}-tinyusb ${TARGET}-tinyusb_config ${TARGET}-pyocd
+    PROPERTIES FOLDER ${TARGET}
+    )
 endfunction()
 
 

From fd50be2e626fc606b6c367e42a6f0f6867f76322 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 8 May 2023 19:43:48 +0700
Subject: [PATCH 1697/2085] change imxrt board_uart_read() to non-blocking

simple host seems to work
---
 hw/bsp/imxrt/family.c | 77 +++++++++++++++++++++++--------------------
 1 file changed, 42 insertions(+), 35 deletions(-)

diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index b009b27e1..6c4b0706b 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -54,6 +54,21 @@ const uint8_t dcd_data[] = { 0x00 };
 //
 //--------------------------------------------------------------------+
 
+static void init_usb_phy(USBPHY_Type* usb_phy) {
+  // Enable PHY support for Low speed device + LS via FS Hub
+  usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+  // Enable all power for normal operation
+  // TODO may not be needed since it is called within CLOCK_EnableUsbhs0PhyPllClock()
+  usb_phy->PWD = 0;
+
+  // TX Timing
+  uint32_t phytx = usb_phy->TX;
+  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+  usb_phy->TX = phytx;
+}
+
 void board_init(void)
 {
   // make sure the dcache is on.
@@ -117,52 +132,24 @@ void board_init(void)
 
   LPUART_Init(UART_PORT, &uart_config, freq);
 
-  //------------- USB0 -------------//
+  //------------- USB -------------//
+  // Note: RT105x RT106x and later have dual USB controllers.
 
   // Clock
   CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
   CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
 
-  USBPHY_Type* usb_phy;
-
-  // RT105x RT106x have dual USB controller.
 #ifdef USBPHY1
-  usb_phy = USBPHY1;
+  init_usb_phy(USBPHY1);
 #else
-  usb_phy = USBPHY;
+  init_usb_phy(USBPHY);
 #endif
 
-  // Enable PHY support for Low speed device + LS via FS Hub
-  usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
-
-  // Enable all power for normal operation
-  usb_phy->PWD = 0;
-
-  // TX Timing
-  uint32_t phytx = usb_phy->TX;
-  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
-  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
-  usb_phy->TX = phytx;
-
-  // RT105x RT106x have dual USB controller.
 #ifdef USBPHY2
   // USB1
   CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
   CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
-
-  usb_phy = USBPHY2;
-
-  // Enable PHY support for Low speed device + LS via FS Hub
-  usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
-
-  // Enable all power for normal operation
-  usb_phy->PWD = 0;
-
-  // TX Timing
-  phytx = usb_phy->TX;
-  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
-  phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
-  usb_phy->TX = phytx;
+  init_usb_phy(USBPHY2);
 #endif
 }
 
@@ -208,8 +195,28 @@ uint32_t board_button_read(void)
 
 int board_uart_read(uint8_t* buf, int len)
 {
-  LPUART_ReadBlocking(UART_PORT, buf, len);
-  return len;
+  int count = 0;
+
+  while( count < len )
+  {
+    uint8_t const rx_count = LPUART_GetRxFifoCount(UART_PORT);
+    if (!rx_count)
+    {
+      // clear all error flag if any
+      uint32_t status_flags = LPUART_GetStatusFlags(UART_PORT);
+      status_flags  &= (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | kLPUART_NoiseErrorFlag);
+      LPUART_ClearStatusFlags(UART_PORT, status_flags);
+      break;
+    }
+
+    for(int i=0; i<rx_count; i++)
+    {
+      buf[count] = LPUART_ReadByte(UART_PORT);
+      count++;
+    }
+  }
+
+  return count;
 }
 
 int board_uart_write(void const * buf, int len)

From 4be7546372eb18f4e33293f5ba9ab78b1303f6b6 Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Mon, 8 May 2023 15:57:34 +0200
Subject: [PATCH 1698/2085] fix(iar_template.ipcf): add missing portable links,
 and delete the usbh_control.c from the list

---
 tools/iar_template.ipcf | 35 +++++++++++++++++++++++++++++++----
 1 file changed, 31 insertions(+), 4 deletions(-)

diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index d243aab0a..32bfce08c 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -57,7 +57,13 @@
 		<group name="src/host">
 			<path>$TUSB_DIR$/src/host/hub.c</path>
 			<path>$TUSB_DIR$/src/host/usbh.c</path>
-			<path>$TUSB_DIR$/src/host/usbh_control.c</path>
+		</group>
+		<group name="src/portable/bridgetek/ft9xx">
+			<path>$TUSB_DIR$/src/portable/bridgetek/ft9xx/dcd_ft9xx.c</path>
+		</group>
+		<group name="src/portable/chipidea/ci_hs">
+			<path>$TUSB_DIR$/src/portable/chipidea/ci_hs/dcd_ci_hs.c</path>
+			<path>$TUSB_DIR$/src/portable/chipidea/ci_hs/hcd_ci_hs.c</path>
 		</group>
 		<group name="src/portable/synopsys/dwc2">
 			<path>$TUSB_DIR$/src/portable/synopsys/dwc2/dcd_dwc2.c</path>
@@ -73,6 +79,7 @@
 		</group>
 		<group name="src/portable/mentor/musb">
 			<path>$TUSB_DIR$/src/portable/mentor/musb/dcd_musb.c</path>
+			<path>$TUSB_DIR$/src/portable/mentor/musb/hcd_musb.c</path>
 		</group>
 		<group name="src/portable/microchip/samd">
 			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
@@ -83,6 +90,12 @@
 		<group name="src/portable/microchip/samx7x">
 			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
 		</group>
+		<group name="src/portable/microchip/pic">
+			<path>$TUSB_DIR$/src/portable/microchip/pic/dcd_pic.c</path>
+		</group>
+		<group name="src/portable/microchip/pic32mz">
+			<path>$TUSB_DIR$/src/portable/microchip/pic32mz/dcd_pic32mz.c</path>
+		</group>
 		<group name="src/portable/mindmotion/mm32">
 			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
 		</group>
@@ -100,6 +113,7 @@
 		</group>
 		<group name="src/portable/nxp/khci">
 			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+			<path>$TUSB_DIR$/src/portable/nxp/khci/hcd_khci.c</path>
 		</group>
 		<group name="src/portable/nxp/lpc17_40">
 			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
@@ -115,13 +129,17 @@
 		<group name="src/portable/ohci">
 			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
 		</group>
+		<group name="src/portable/raspberrypi/pio_usb">
+			<path>$TUSB_DIR$/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c</path>
+			<path>$TUSB_DIR$/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c</path>
+		</group>
 		<group name="src/portable/raspberrypi/rp2040">
 			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
 			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
 		</group>
-		<group name="src/portable/renesas/usba">
-			<path>$TUSB_DIR$/src/portable/renesas/usba/dcd_usba.c</path>
+		<group name="src/portable/renesas/rusb2">
+			<path>$TUSB_DIR$/src/portable/renesas/rusb2/dcd_rusb2.c</path>
+			<path>$TUSB_DIR$/src/portable/renesas/rusb2/hcd_rusb2.c</path>
 		</group>
 		<group name="src/portable/sony/cxd56">
 			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
@@ -129,12 +147,21 @@
 		<group name="src/portable/st/stm32_fsdev">
 			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
 		</group>
+		<group name="src/portable/st/synopsys">
+			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
+		</group>
+		<group name="src/portable/sunxi">
+			<path>$TUSB_DIR$/src/portable/sunxi/dcd_sunxi_musb.c</path>
+		</group>
 		<group name="src/portable/ti/msp430x5xx">
 			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
 		</group>
 		<group name="src/portable/valentyusb/eptri">
 			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
 		</group>
+		<group name="src/portable/wch/ch32v307">
+			<path>$TUSB_DIR$/src/portable/wch/ch32v307/dcd_usbhs.c</path>
+		</group>
         <group name="lib/SEGGER_RTT">
 			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
             <path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>

From 04c759028af73af095c773d84374004c86c70c1e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 9 May 2023 10:02:44 +0700
Subject: [PATCH 1699/2085] simplify cmake target, remove -bsp

---
 hw/bsp/imxrt/family.c     |  1 +
 hw/bsp/imxrt/family.cmake | 25 +++++++++----------------
 2 files changed, 10 insertions(+), 16 deletions(-)

diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 6c4b0706b..52d3bb91b 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -86,6 +86,7 @@ void board_init(void)
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
+
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 9e084b4fd..e9615a1f4 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -86,11 +86,10 @@ function(family_configure_target TARGET)
   # TOP is path to root directory
   set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
 
-  #---------- BSP_TARGET ----------
-  # BSP_TARGET is built for each example since it depends on example's tusb_config.h
-  set(BSP_TARGET "${TARGET}-bsp")
-  add_library(${BSP_TARGET} STATIC
-    # TinyUSB
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # TinyUSB Port
     ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
     ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
     ${TOP}/src/portable/ehci/ehci.c
@@ -98,7 +97,7 @@ function(family_configure_target TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
     )
-  target_include_directories(${BSP_TARGET} PUBLIC
+  target_include_directories(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
@@ -120,8 +119,7 @@ function(family_configure_target TARGET)
   add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
 
   # Link dependencies
-  target_link_libraries(${BSP_TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
-  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${BSP_TARGET} ${TARGET}-tinyusb)
+  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
 
   # Flash Target
   add_custom_target(${TARGET}-pyocd
@@ -129,8 +127,8 @@ function(family_configure_target TARGET)
     )
 
   # group target
-  set_target_properties(${BSP_TARGET} ${TARGET}-tinyusb ${TARGET}-tinyusb_config ${TARGET}-pyocd
-    PROPERTIES FOLDER ${TARGET}
+  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
+    PROPERTIES FOLDER ${TARGET}_sub
     )
 endfunction()
 
@@ -148,15 +146,10 @@ function(family_add_freertos TARGET)
   target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
     CFG_TUSB_OS=OPT_OS_FREERTOS
     )
-  # tinyusb need to be linked with freeRTOS kernel
+  # link tinyusb with freeRTOS kernel
   target_link_libraries(${TARGET}-tinyusb PUBLIC
     freertos_kernel
     )
-
-  target_link_libraries(${TARGET}-tinyusb PUBLIC
-    freertos_kernel
-    )
-
   target_link_libraries(${TARGET} PUBLIC
     freertos_kernel
     )

From 77f0726361c66bf2783c1ce68e0f00bdd5f58229 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 9 May 2023 17:32:14 +0700
Subject: [PATCH 1700/2085] fix ehci issue with portsc when enable port power
 and port reset

fix attached device not regconized if attached before power on
---
 .idea/runConfigurations/rt1060_redlink.xml    |  10 ++
 .../imxrt/boards/mimxrt1060_evk/board.cmake   |   1 +
 hw/bsp/imxrt/family.cmake                     |  19 ++-
 src/portable/ehci/ehci.c                      |  94 ++++++++-----
 src/portable/ehci/ehci.h                      | 132 ++++++++++++------
 5 files changed, 173 insertions(+), 83 deletions(-)
 create mode 100644 .idea/runConfigurations/rt1060_redlink.xml

diff --git a/.idea/runConfigurations/rt1060_redlink.xml b/.idea/runConfigurations/rt1060_redlink.xml
new file mode 100644
index 000000000..a6f345fac
--- /dev/null
+++ b/.idea/runConfigurations/rt1060_redlink.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt1060 redlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver --gdb-port 55503 --semihost-port -1 MIMXRT1062xxxxA:EVK-MIMXRT1060" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc_hid" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc_hid" RUN_TARGET_NAME="cdc_msc_hid">
+    <custom-gdb-server version="1" gdb-connect="tcp::55503" executable="/usr/local/LinkServer/LinkServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
index 033f9fcf9..171d427de 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
@@ -2,6 +2,7 @@ set(MCU_VARIANT MIMXRT1062)
 
 set(JLINK_DEVICE MIMXRT1062xxx6A)
 set(PYOCD_TARGET mimxrt1060)
+set(NXPLS_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
 
 function(update_board TARGET)
   target_sources(${TARGET} PUBLIC
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index e9615a1f4..e38bcf4b1 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -121,15 +121,26 @@ function(family_configure_target TARGET)
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
 
-  # Flash Target
+  # group target (not yet supported by clion)
+  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
+    PROPERTIES FOLDER ${TARGET}_sub
+    )
+
+  #---------- Flash ----------
+  # Flash using pyocd
   add_custom_target(${TARGET}-pyocd
     COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
     )
 
-  # group target
-  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
-    PROPERTIES FOLDER ${TARGET}_sub
+  # Flash using NXP LinkServer (redlink)
+  # https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
+  # LinkServer has a bug that can only execute with full path otherwise it throws:
+  # realpath error: No such file or directory
+  execute_process(COMMAND which LinkServer OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
+  add_custom_target(${TARGET}-redlink
+    COMMAND ${LINKSERVER_PATH} flash ${NXPLS_DEVICE} load $<TARGET_FILE:${TARGET}>
     )
+
 endfunction()
 
 
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 9951aa5da..494e2e50f 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -79,7 +79,8 @@ typedef struct
   ehci_qhd_t qhd_pool[QHD_MAX];
   ehci_qtd_t qtd_pool[QTD_MAX] TU_ATTR_ALIGNED(32);
 
-  ehci_registers_t* regs;
+  ehci_registers_t* regs;         // operational register
+  ehci_cap_registers_t* cap_regs; // capability register
 
   volatile uint32_t uframe_number;
 }ehci_data_t;
@@ -87,6 +88,26 @@ typedef struct
 // Periodic frame list must be 4K alignment
 CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
 
+//--------------------------------------------------------------------+
+// Debug
+//--------------------------------------------------------------------+
+#if CFG_TUSB_DEBUG >= EHCI_DBG
+static inline void print_portsc(ehci_registers_t* regs)
+{
+  TU_LOG_HEX(EHCI_DBG, regs->portsc);
+  TU_LOG(EHCI_DBG, "  Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status);
+  TU_LOG(EHCI_DBG, "  Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change);
+  TU_LOG(EHCI_DBG, "  Port Enabled          : %u\r\n", regs->portsc_bm.port_enabled);
+  TU_LOG(EHCI_DBG, "  Port Enabled Change   : %u\r\n", regs->portsc_bm.port_enable_change);
+
+  TU_LOG(EHCI_DBG, "  Port Reset            : %u\r\n", regs->portsc_bm.port_reset);
+  TU_LOG(EHCI_DBG, "  Port Power            : %u\r\n", regs->portsc_bm.port_power);
+}
+
+#else
+#define print_portsc(_reg)
+#endif
+
 //--------------------------------------------------------------------+
 // PROTOTYPE
 //--------------------------------------------------------------------+
@@ -152,11 +173,11 @@ void hcd_port_reset(uint8_t rhport)
 
   ehci_registers_t* regs = ehci_data.regs;
 
-//  regs->portsc_bm.port_enabled = 0; // disable port before reset
-//  regs->portsc_bm.port_reset = 1;
-
-  uint32_t portsc = regs->portsc;
+  // mask out all change bits since they are Write 1 to clear
+  uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL;
 
+  // EHCI Table 2-16 PortSC
+  // when software writes Port Reset bit to a one, it must also write a zero to the Port Enable bit.
   portsc &= ~(EHCI_PORTSC_MASK_PORT_EANBLED);
   portsc |= EHCI_PORTSC_MASK_PORT_RESET;
 
@@ -167,9 +188,14 @@ void hcd_port_reset_end(uint8_t rhport)
 {
   (void) rhport;
 
-#if 0
+#if 0 // TODO check if this is necessary
   ehci_registers_t* regs = ehci_data.regs;
-  regs->portsc_bm.port_reset = 0;
+
+  // mask out all change bits since they are Write 1 to clear
+  uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL;
+  portsc &= ~(EHCI_PORTSC_MASK_PORT_RESET);
+
+  regs->portsc = portsc;
 #endif
 }
 
@@ -240,19 +266,26 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 
 bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
 {
-  (void) capability_reg; // not used yet
-
   tu_memclr(&ehci_data, sizeof(ehci_data_t));
 
-  ehci_data.regs = (ehci_registers_t* ) operatial_reg;
+  ehci_data.regs = (ehci_registers_t*) operatial_reg;
+  ehci_data.cap_regs = (ehci_cap_registers_t*) capability_reg;
 
   ehci_registers_t* regs = ehci_data.regs;
 
-  //------------- CTRLDSSEGMENT Register (skip) -------------//
-  //------------- USB INT Register -------------//
-  regs->inten  = 0;                 // 1. disable all the interrupt
-  regs->status = EHCI_INT_MASK_ALL; // 2. clear all status
+  // EHCI 4.1 Host Controller Initialization
 
+  //------------- CTRLDSSEGMENT Register (skip) -------------//
+
+  //------------- USB INT Register -------------//
+
+  // disable all the interrupt
+  regs->inten  = 0;
+
+  // clear all status except port change since device maybe connected before this driver is initialized
+  regs->status = (EHCI_INT_MASK_ALL & ~EHCI_INT_MASK_PORT_CHANGE);
+
+  // Enable interrupts
   regs->inten  = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_ASYNC_ADVANCE |
                  EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_FRAMELIST_ROLLOVER;
 
@@ -316,7 +349,16 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
                    FRAMELIST_SIZE_USBCMD_VALUE;
 
   //------------- ConfigFlag Register (skip) -------------//
-  regs->portsc_bm.port_power = 1; // enable port power
+
+  // enable port power bit in portsc. The function of this bit depends on the value of the Port
+  // Power Control (PPC) field in the HCSPARAMS register.
+  if (ehci_data.cap_regs->hcsparams_bm.port_power_control) {
+    // mask out all change bits since they are Write 1 to clear
+    uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL);
+    portsc |= ECHI_PORTSC_MASK_PORT_POWER;
+
+    regs->portsc = portsc;
+  }
 
   return true;
 }
@@ -656,26 +698,6 @@ static void xfer_error_isr(uint8_t hostid)
   }
 }
 
-#if CFG_TUSB_DEBUG >= EHCI_DBG
-
-static inline void print_portsc(ehci_registers_t* regs)
-{
-  TU_LOG_HEX(EHCI_DBG, regs->portsc);
-  TU_LOG(EHCI_DBG, "  Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status);
-  TU_LOG(EHCI_DBG, "  Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change);
-  TU_LOG(EHCI_DBG, "  Port Enabled          : %u\r\n", regs->portsc_bm.port_enabled);
-  TU_LOG(EHCI_DBG, "  Port Enabled Change   : %u\r\n", regs->portsc_bm.port_enable_change);
-
-  TU_LOG(EHCI_DBG, "  Port Reset            : %u\r\n", regs->portsc_bm.port_reset);
-  TU_LOG(EHCI_DBG, "  Port Power            : %u\r\n", regs->portsc_bm.port_power);
-}
-
-#else
-
-#define print_portsc(_reg)
-
-#endif
-
 //------------- Host Controller Driver's Interrupt Handler -------------//
 void hcd_int_handler(uint8_t rhport)
 {
@@ -695,7 +717,7 @@ void hcd_int_handler(uint8_t rhport)
 
   if (int_status & EHCI_INT_MASK_PORT_CHANGE)
   {
-    uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_ALL;
+    uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_CHANGE_ALL;
     print_portsc(regs);
 
     if (regs->portsc_bm.connect_status_change)
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index 36f8649be..dd090cb36 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -267,16 +267,15 @@ TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" );
 //--------------------------------------------------------------------+
 // EHCI Operational Register
 //--------------------------------------------------------------------+
-enum ehci_interrupt_mask_{
+enum {
   EHCI_INT_MASK_USB                   = TU_BIT(0),
   EHCI_INT_MASK_ERROR                 = TU_BIT(1),
   EHCI_INT_MASK_PORT_CHANGE           = TU_BIT(2),
-
   EHCI_INT_MASK_FRAMELIST_ROLLOVER    = TU_BIT(3),
   EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR = TU_BIT(4),
   EHCI_INT_MASK_ASYNC_ADVANCE         = TU_BIT(5),
-  EHCI_INT_MASK_NXP_SOF               = TU_BIT(7),
 
+  EHCI_INT_MASK_NXP_SOF               = TU_BIT(7),
   EHCI_INT_MASK_NXP_ASYNC             = TU_BIT(18),
   EHCI_INT_MASK_NXP_PERIODIC          = TU_BIT(19),
 
@@ -287,7 +286,7 @@ enum ehci_interrupt_mask_{
       EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC
 };
 
-enum ehci_usbcmd_pos_ {
+enum {
   EHCI_USBCMD_POS_RUN_STOP               = 0,
   EHCI_USBCMD_POS_FRAMELIST_SIZE         = 2,
   EHCI_USBCMD_POS_PERIOD_ENABLE          = 4,
@@ -296,24 +295,27 @@ enum ehci_usbcmd_pos_ {
   EHCI_USBCMD_POS_INTERRUPT_THRESHOLD    = 16
 };
 
-enum ehci_portsc_change_mask_{
+enum {
   EHCI_PORTSC_MASK_CURRENT_CONNECT_STATUS = TU_BIT(0),
   EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE  = TU_BIT(1),
   EHCI_PORTSC_MASK_PORT_EANBLED           = TU_BIT(2),
-  EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE     = TU_BIT(3),
+  EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE     = TU_BIT(3),
   EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE    = TU_BIT(5),
+  EHCI_PORTSC_MASK_FORCE_RESUME           = TU_BIT(6),
+  EHCI_PORTSC_MASK_PORT_SUSPEND           = TU_BIT(7),
   EHCI_PORTSC_MASK_PORT_RESET             = TU_BIT(8),
+  ECHI_PORTSC_MASK_PORT_POWER             = TU_BIT(12),
 
-  EHCI_PORTSC_MASK_ALL =
-      EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
-      EHCI_PORTSC_MASK_PORT_ENABLE_CHAGNE |
-      EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
+  EHCI_PORTSC_MASK_CHANGE_ALL =
+    EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
+    EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE |
+    EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE
 };
 
 typedef volatile struct
 {
   union {
-    uint32_t command;
+    uint32_t command; // 0x00
 
     struct {
       uint32_t run_stop               : 1 ; ///< 1=Run. 0=Stop
@@ -333,7 +335,7 @@ typedef volatile struct
   };
 
   union {
-    uint32_t status;
+    uint32_t status; // 0x04
 
     struct {
       uint32_t usb                   : 1  ; ///< qTD with IOC is retired
@@ -357,7 +359,7 @@ typedef volatile struct
   };
 
   union{
-    uint32_t inten;
+    uint32_t inten; // 0x08
 
     struct {
       uint32_t usb                   : 1  ;
@@ -375,43 +377,87 @@ typedef volatile struct
     }inten_bm;
   };
 
-  uint32_t frame_index        ; ///< Micro frame counter
-  uint32_t ctrl_ds_seg        ; ///< Control Data Structure Segment
-  uint32_t periodic_list_base ; ///< Beginning address of perodic frame list
-  uint32_t async_list_addr    ; ///< Address of next async QHD to be executed
+  uint32_t frame_index        ; ///< 0x0C Micro frame counter
+  uint32_t ctrl_ds_seg        ; ///< 0x10 Control Data Structure Segment
+  uint32_t periodic_list_base ; ///< 0x14 Beginning address of perodic frame list
+  uint32_t async_list_addr    ; ///< 0x18 Address of next async QHD to be executed
   uint32_t nxp_tt_control     ; ///< nxp embedded transaction translator (reserved by EHCI specs)
   uint32_t reserved[8]        ;
-  uint32_t config_flag        ; ///< not used by NXP
+  uint32_t config_flag        ; ///< 0x40 not used by NXP
 
   union {
-    uint32_t portsc             ; ///< port status and control
-    struct {
-      uint32_t current_connect_status      : 1; ///< 0: No device, 1: Device is present on port
-      uint32_t connect_status_change       : 1; ///< Change in Current Connect Status
-      uint32_t port_enabled                : 1; ///< Ports can only be enabled by HC as a part of the reset and enable. SW can write 0 to disable
-      uint32_t port_enable_change          : 1; ///< Port Enabled has changed
-      uint32_t over_current_active         : 1; ///< Port has an over-current condition
-      uint32_t over_current_change         : 1; ///< Change to Over-current Active
-      uint32_t force_port_resume           : 1; ///< Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit.
-      uint32_t suspend                     : 1; ///< Port in suspend state
-      uint32_t port_reset                  : 1; ///< 1=Port is in Reset. 0=Port is not in Reset
-      uint32_t nxp_highspeed_status        : 1; ///< NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode
-      uint32_t line_status                 : 2; ///< D+/D- state: 00: SE0, 10: J-state, 01: K-state
-      uint32_t port_power                  : 1; ///< 0= power off, 1= power on
-      uint32_t port_owner                  : 1; ///< not used by NXP
-      uint32_t port_indicator_control      : 2; ///< 00b: off, 01b: Amber, 10b: green, 11b: undefined
-      uint32_t port_test_control           : 4; ///< Port test mode, not used by tinyusb
-      uint32_t wake_on_connect_enable      : 1; ///< Enables device connects as wake-up events
-      uint32_t wake_on_disconnect_enable   : 1; ///< Enables device disconnects as wake-up events
-      uint32_t wake_on_over_current_enable : 1; ///< Enables over-current conditions as wake-up events
-      uint32_t nxp_phy_clock_disable       : 1; ///< NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock
-      uint32_t nxp_port_force_fullspeed    : 1; ///< NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
-      uint32_t TU_RESERVED                 : 1;
-      uint32_t nxp_port_speed              : 2; ///< NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed
+    // mixed with RW and R/WC bits, care should be taken when writing to this register
+    uint32_t portsc           ; ///< 0x44 port status and control
+    const struct {
+      uint32_t current_connect_status      : 1; ///< 00: 0: No device, 1: Device is present on port
+      uint32_t connect_status_change       : 1; ///< 01: [R/WC] Change in Current Connect Status
+      uint32_t port_enabled                : 1; ///< 02: Ports can only be enabled by HC as a part of the reset and enable. SW can write 0 to disable
+      uint32_t port_enable_change          : 1; ///< 03: [R/WC] Port Enabled has changed
+      uint32_t over_current_active         : 1; ///< 04: Port has an over-current condition
+      uint32_t over_current_change         : 1; ///< 05: [R/WC] Change to Over-current Active
+      uint32_t force_port_resume           : 1; ///< 06: Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit.
+      uint32_t suspend                     : 1; ///< 07: Port in suspend state
+      uint32_t port_reset                  : 1; ///< 08: 1=Port is in Reset. 0=Port is not in Reset
+      uint32_t nxp_highspeed_status        : 1; ///< 09: NXP customized: 0=connected to the port is not in High-speed mode, 1=connected to the port is in High-speed mode
+      uint32_t line_status                 : 2; ///< 10-11: D+/D- state: 00: SE0, 10: J-state, 01: K-state
+      uint32_t port_power                  : 1; ///< 12: 0= power off, 1= power on
+      uint32_t port_owner                  : 1; ///< 13: not used by NXP
+      uint32_t port_indicator_control      : 2; ///< 14-15: 00b: off, 01b: Amber, 10b: green, 11b: undefined
+      uint32_t port_test_control           : 4; ///< 16-19: Port test mode, not used by tinyusb
+      uint32_t wake_on_connect_enable      : 1; ///< 20: Enables device connects as wake-up events
+      uint32_t wake_on_disconnect_enable   : 1; ///< 21: Enables device disconnects as wake-up events
+      uint32_t wake_on_over_current_enable : 1; ///< 22: Enables over-current conditions as wake-up events
+      uint32_t nxp_phy_clock_disable       : 1; ///< 23: NXP customized: the PHY can be put into Low Power Suspend – Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0: enable PHY clock, 1: disable PHY clock
+      uint32_t nxp_port_force_fullspeed    : 1; ///< 24: NXP customized: Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allowsthe port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.
+      uint32_t TU_RESERVED                 : 1; ///< 25
+      uint32_t nxp_port_speed              : 2; ///< 26-27: NXP customized: This register field indicates the speed atwhich the port is operating. For HS mode operation in the host controllerand HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator. 0x0: Fullspeed, 0x1: Lowspeed, 0x2: Highspeed
       uint32_t TU_RESERVED                 : 4;
     }portsc_bm;
   };
-}ehci_registers_t;
+} ehci_registers_t;
+
+//--------------------------------------------------------------------+
+// Capability Registers
+//--------------------------------------------------------------------+
+typedef volatile struct {
+  uint8_t caplength;   // 0x00
+  uint8_t TU_RESERVED; // 0x01
+  uint16_t hciversion; // 0x02
+
+  union {
+    uint32_t hcsparams; // 0x04
+    struct {
+      uint32_t num_ports          : 4; // [00:03]
+      uint32_t port_power_control : 1; // [04]
+      uint32_t TU_RESERVED        : 2; // [05:06]
+      uint32_t port_route_rule    : 1; // [07]
+      uint32_t n_pcc              : 4; // [08:11] Number of Ports per Companion Controller
+      uint32_t n_cc               : 4; // [12:15] Number of Companion Controllers
+      uint32_t port_ind           : 1; // [16] Port Indicators
+      uint32_t TU_RESERVED        : 3; // [17:19]
+      uint32_t n_ptt              : 4; // [20:23] ChipIdea: Number of Ports per Transaction Translator
+      uint32_t n_tt               : 4; // [24:27] ChipIdea: Number of Transaction Translators
+      uint32_t TU_RESERVED        : 4; // [28:31]
+    } hcsparams_bm;
+  };
+
+  union {
+    uint32_t hccparams; // 0x08
+    struct {
+      uint32_t addr_64bit                   : 1; // [00] 64-bit Addressing Capability
+      uint32_t programmable_frame_list_flag : 1; // [01] Programmable Frame List Flag
+      uint32_t async_park_cap               : 1; // [02] Asynchronous Schedule Park Capability
+      uint32_t TU_RESERVED                  : 1; // [03]
+      uint32_t iso_schedule_threshold       : 4; // [4:7] Isochronous Scheduling Threshold
+      uint32_t eecp                         : 8; // [8:15] EHCI Extended Capabilities Pointer
+      uint32_t TU_RESERVED                  : 16;// [16:31]
+    } hccparams_bm;
+  };
+
+  uint32_t hcsp_portroute; // 0x0C HCSP Port Route Register
+} ehci_cap_registers_t;
+
+TU_VERIFY_STATIC(sizeof(ehci_cap_registers_t) == 16, "size is not correct");
 
 #ifdef __cplusplus
  }

From bc579c045e5d62050f0b58f20fd28fb71e4070a8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 9 May 2023 21:39:10 +0700
Subject: [PATCH 1701/2085] skip link option --print-memory-usage for renesas
 rx since it does not support this option

---
 .../{rt1060_redlink.xml => rt1060_nxplink.xml}             | 2 +-
 examples/rules.mk                                          | 7 ++++++-
 hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake             | 1 +
 hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake             | 2 +-
 hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake             | 1 +
 hw/bsp/imxrt/family.cmake                                  | 4 ++--
 6 files changed, 12 insertions(+), 5 deletions(-)
 rename .idea/runConfigurations/{rt1060_redlink.xml => rt1060_nxplink.xml} (92%)

diff --git a/.idea/runConfigurations/rt1060_redlink.xml b/.idea/runConfigurations/rt1060_nxplink.xml
similarity index 92%
rename from .idea/runConfigurations/rt1060_redlink.xml
rename to .idea/runConfigurations/rt1060_nxplink.xml
index a6f345fac..d3303bdb6 100644
--- a/.idea/runConfigurations/rt1060_redlink.xml
+++ b/.idea/runConfigurations/rt1060_nxplink.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1060 redlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver --gdb-port 55503 --semihost-port -1 MIMXRT1062xxxxA:EVK-MIMXRT1060" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc_hid" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc_hid" RUN_TARGET_NAME="cdc_msc_hid">
+  <configuration default="false" name="rt1060 nxplink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver --gdb-port 55503 --semihost-port -1 MIMXRT1062xxxxA:EVK-MIMXRT1060" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc_hid" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc_hid" RUN_TARGET_NAME="cdc_msc_hid">
     <custom-gdb-server version="1" gdb-connect="tcp::55503" executable="/usr/local/LinkServer/LinkServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/examples/rules.mk b/examples/rules.mk
index 3ec3c880b..516beca78 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -72,6 +72,11 @@ endif
 
 LDFLAGS += $(CFLAGS) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections
 
+# Some toolchain such as renesas rx does not support --print-memory-usage flags
+ifneq ($(FAMILY),rx)
+LDFLAGS += -Wl,--print-memory-usage
+endif
+
 ifdef LD_FILE
 LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE)
 endif
@@ -169,7 +174,7 @@ $(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
 
 $(BUILD)/$(PROJECT).elf: $(OBJ)
 	@echo LINK $@
-	@$(LD) -o $@ $(LDFLAGS) $^ -Wl,--print-memory-usage -Wl,--start-group $(LIBS) -Wl,--end-group
+	@$(LD) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group
 
 endif
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
index 02955e356..3ba95bf2c 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
@@ -2,6 +2,7 @@ set(MCU_VARIANT MIMXRT1011)
 
 set(JLINK_DEVICE MIMXRT1011DAE5A)
 set(PYOCD_TARGET mimxrt1010)
+set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
 
 function(update_board TARGET)
   target_sources(${TARGET} PUBLIC
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
index 171d427de..fd335cdf5 100644
--- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake
@@ -2,7 +2,7 @@ set(MCU_VARIANT MIMXRT1062)
 
 set(JLINK_DEVICE MIMXRT1062xxx6A)
 set(PYOCD_TARGET mimxrt1060)
-set(NXPLS_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
+set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
 
 function(update_board TARGET)
   target_sources(${TARGET} PUBLIC
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake
index 925664b41..cd75c5227 100644
--- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake
@@ -2,6 +2,7 @@ set(MCU_VARIANT MIMXRT1064)
 
 set(JLINK_DEVICE MIMXRT1064xxx6A)
 set(PYOCD_TARGET mimxrt1064)
+set(NXPLINK_DEVICE MIMXRT1064xxxxA:EVK-MIMXRT1064)
 
 function(update_board TARGET)
   target_sources(${TARGET} PUBLIC
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index e38bcf4b1..85ad104a0 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -137,8 +137,8 @@ function(family_configure_target TARGET)
   # LinkServer has a bug that can only execute with full path otherwise it throws:
   # realpath error: No such file or directory
   execute_process(COMMAND which LinkServer OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
-  add_custom_target(${TARGET}-redlink
-    COMMAND ${LINKSERVER_PATH} flash ${NXPLS_DEVICE} load $<TARGET_FILE:${TARGET}>
+  add_custom_target(${TARGET}-nxplink
+    COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
     )
 
 endfunction()

From c0e4c02b9d70240b97aa4924e6002ccb3d8057dd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 May 2023 11:15:11 +0700
Subject: [PATCH 1702/2085] allow imxrt build with dual exmaples

---
 examples/cmake/toolchain/set_flags.cmake      |  3 +-
 examples/dual/CMakeLists.txt                  | 11 ++++----
 .../host_hid_to_device_cdc/CMakeLists.txt     | 28 +++++++++----------
 hw/bsp/family_support.cmake                   |  4 +--
 hw/bsp/imxrt/family.cmake                     |  4 +++
 src/portable/chipidea/ci_hs/hcd_ci_hs.c       |  2 ++
 6 files changed, 30 insertions(+), 22 deletions(-)

diff --git a/examples/cmake/toolchain/set_flags.cmake b/examples/cmake/toolchain/set_flags.cmake
index 27631abcd..3f109b59e 100644
--- a/examples/cmake/toolchain/set_flags.cmake
+++ b/examples/cmake/toolchain/set_flags.cmake
@@ -8,7 +8,8 @@ foreach(LANG IN ITEMS C CXX ASM)
     #cmake_print_variables(CMAKE_${LANG}_FLAGS_INIT)
 
     # optimization flags
-    set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-Og")
+    set(CMAKE_${LANG}_FLAGS_RELEASE_INIT "-Os")
+    set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-O0")
 endforeach()
 
 # Linker
diff --git a/examples/dual/CMakeLists.txt b/examples/dual/CMakeLists.txt
index d211c8b83..15081cf26 100644
--- a/examples/dual/CMakeLists.txt
+++ b/examples/dual/CMakeLists.txt
@@ -4,9 +4,10 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
 
 project(tinyusb_dual_examples C CXX ASM)
 family_initialize_project(tinyusb_dual_examples ${CMAKE_CURRENT_LIST_DIR})
+
 if (FAMILY STREQUAL "rp2040" AND NOT TARGET tinyusb_pico_pio_usb)
-    message("Skipping dual host/device mode examples as Pico-PIO-USB is not available")
-else()
-    # family_add_subdirectory will filter what to actually add based on selected FAMILY
-    family_add_subdirectory(host_hid_to_device_cdc)
-endif()
+  message("Skipping dual host/device mode examples as Pico-PIO-USB is not available")
+else ()
+  # family_add_subdirectory will filter what to actually add based on selected FAMILY
+  family_add_subdirectory(host_hid_to_device_cdc)
+endif ()
diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index 3505d39eb..c6d19a720 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -14,14 +14,14 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
@@ -29,12 +29,12 @@ family_configure_dual_usb_example(${PROJECT})
 
 # due to warnings from Pico-PIO-USB
 target_compile_options(${PROJECT} PUBLIC
-        -Wno-error=shadow
-        -Wno-error=cast-align
-        -Wno-error=cast-qual
-        -Wno-error=redundant-decls
-        -Wno-error=sign-conversion
-        -Wno-error=conversion
-        -Wno-error=sign-compare
-        -Wno-error=unused-function
-        )
+  -Wno-error=shadow
+  -Wno-error=cast-align
+  -Wno-error=cast-qual
+  -Wno-error=redundant-decls
+  -Wno-error=sign-conversion
+  -Wno-error=conversion
+  -Wno-error=sign-compare
+  -Wno-error=unused-function
+  )
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 26baa6365..01e7bb018 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -27,8 +27,8 @@ if (NOT TARGET _family_support_marker)
             foreach(MCU IN LISTS FAMILY_MCUS)
                 # For each line in only.txt
                 foreach(_line ${ONLYS_LINES})
-                    # If mcu:xxx exists for this mcu then include
-                    if (${_line} STREQUAL "mcu:${MCU}")
+                    # If mcu:xxx exists for this mcu or board:xxx then include
+                    if (${_line} STREQUAL "mcu:${MCU}" OR ${_line} STREQUAL "board:${BOARD}")
                         set(${RESULT} 1 PARENT_SCOPE)
                         return()
                     endif()
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 85ad104a0..b510c064e 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -173,3 +173,7 @@ endfunction()
 function(family_configure_host_example TARGET)
   family_configure_target(${TARGET})
 endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index d607627b4..b06633f30 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -76,6 +76,8 @@ bool hcd_init(uint8_t rhport)
 #endif
 
   // FIXME force full speed, still have issue with Highspeed enumeration
+  // 1. Have issue when plug/unplug devices, maybe the port is not reset properly
+  // 2. Also does not seems to detect disconnection
   hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
 
   return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD);

From 4c796b89d80606e40fb098f1b4b5496dbb5bb7dc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 May 2023 11:20:26 +0700
Subject: [PATCH 1703/2085] try to build with cmake on ci

---
 .github/workflows/cmake_arm.yml | 58 +++++++++++++++++++++++++++++++++
 examples/device/CMakeLists.txt  |  7 +++-
 2 files changed, 64 insertions(+), 1 deletion(-)
 create mode 100644 .github/workflows/cmake_arm.yml

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
new file mode 100644
index 000000000..98aae7df2
--- /dev/null
+++ b/.github/workflows/cmake_arm.yml
@@ -0,0 +1,58 @@
+name: CMake Build ARM
+
+on:
+  push:
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+      - '.github/workflows/cmake_arm.yml'
+  pull_request:
+    branches: [ master ]
+    paths:
+      - 'src/**'
+      - 'examples/**'
+      - 'lib/**'
+      - 'hw/**'
+      - '.github/workflows/cmake_arm.yml'
+
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
+jobs:
+  # ---------------------------------------
+  # Build ARM family
+  # ---------------------------------------
+  build-arm:
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        family:
+        # Alphabetical order
+        - 'imxrt'
+    steps:
+    - name: Setup Python
+      uses: actions/setup-python@v4
+      with:
+        python-version: '3.x'
+
+    - name: Install ARM GCC
+      uses: carlosperate/arm-none-eabi-gcc-action@v1
+      with:
+        release: '11.2-2022.02'
+
+    - name: Checkout TinyUSB
+      uses: actions/checkout@v3
+
+    - name: Get Dependencies
+      run: python3 tools/get_family_deps.py ${{ matrix.family }}
+
+    - name: Build
+      run: |
+        mkdir -p examples/build
+        cd examples/build
+        cmake -DFAMILY=${{ matrix.family }} -DBOARD=mimxrt1060_evk ..
+        cmake --build .
diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index 5b077a5e1..10a1f4c26 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -22,7 +22,12 @@ family_add_subdirectory(hid_generic_inout)
 family_add_subdirectory(hid_multiple_interface)
 family_add_subdirectory(midi_test)
 family_add_subdirectory(msc_dual_lun)
-family_add_subdirectory(net_lwip_webserver)
+
+# FIXME temp skip net_lwip_webserver for imxrt for now
+if (NOT ${FAMILY} STREQUAL "imxrt")
+  family_add_subdirectory(net_lwip_webserver)
+endif()
+
 family_add_subdirectory(uac2_headset)
 family_add_subdirectory(usbtmc)
 family_add_subdirectory(video_capture)

From 8e3bdd23913468acace297f09286c942a1a025c3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 May 2023 13:09:15 +0700
Subject: [PATCH 1704/2085] add python script to help building cmake, build all
 imxrt boards with ci

---
 .github/workflows/cmake_arm.yml               |  8 +-
 hw/bsp/imxrt/boards/metro_m7_1011/board.cmake | 15 +++
 .../imxrt/boards/mimxrt1015_evk/board.cmake   | 15 +++
 .../imxrt/boards/mimxrt1020_evk/board.cmake   | 14 +++
 .../imxrt/boards/mimxrt1024_evk/board.cmake   | 16 +++
 .../imxrt/boards/mimxrt1050_evkb/board.cmake  | 16 +++
 hw/bsp/imxrt/boards/teensy_40/board.cmake     | 21 ++++
 .../teensy_40/teensy40_flexspi_nor_config.c   |  2 +-
 hw/bsp/imxrt/boards/teensy_41/board.cmake     | 21 ++++
 .../teensy_41/teensy41_flexspi_nor_config.c   |  2 +-
 tools/build_cmake.py                          | 99 +++++++++++++++++++
 11 files changed, 221 insertions(+), 8 deletions(-)
 create mode 100644 hw/bsp/imxrt/boards/metro_m7_1011/board.cmake
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake
 create mode 100644 hw/bsp/imxrt/boards/teensy_40/board.cmake
 create mode 100644 hw/bsp/imxrt/boards/teensy_41/board.cmake
 create mode 100644 tools/build_cmake.py

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 98aae7df2..3a1ef4f4f 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -1,4 +1,4 @@
-name: CMake Build ARM
+name: CMake ARM
 
 on:
   push:
@@ -51,8 +51,4 @@ jobs:
       run: python3 tools/get_family_deps.py ${{ matrix.family }}
 
     - name: Build
-      run: |
-        mkdir -p examples/build
-        cd examples/build
-        cmake -DFAMILY=${{ matrix.family }} -DBOARD=mimxrt1060_evk ..
-        cmake --build .
+      run: python tools/build_cmake.py ${{ matrix.family }}
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake
new file mode 100644
index 000000000..3ba95bf2c
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT MIMXRT1011)
+
+set(JLINK_DEVICE MIMXRT1011DAE5A)
+set(PYOCD_TARGET mimxrt1010)
+set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1011DAE5A
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake
new file mode 100644
index 000000000..becad46d4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT MIMXRT1015)
+
+set(JLINK_DEVICE MIMXRT1015DAF5A)
+set(PYOCD_TARGET mimxrt1015)
+set(NXPLINK_DEVICE MIMXRT1015xxxxx:EVK-MIMXRT1015)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1015_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1015DAF5A
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake
new file mode 100644
index 000000000..1696dc987
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT MIMXRT1021)
+
+set(JLINK_DEVICE MIMXRT1021DAG5A)
+set(PYOCD_TARGET mimxrt1020)
+set(NXPLINK_DEVICE MIMXRT1021xxxxx:EVK-MIMXRT1020)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1020_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1021DAG5A
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
new file mode 100644
index 000000000..7011fec9b
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MIMXRT1024)
+
+set(JLINK_DEVICE MIMXRT1024DAG5A)
+set(PYOCD_TARGET mimxrt1024)
+set(NXPLINK_DEVICE MIMXRT1024xxxxx:MIMXRT1024-EVK)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1024_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1024DAG5A
+    CFG_EXAMPLE_VIDEO_READONLY
+    #-Wno-error=array-bounds
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake
new file mode 100644
index 000000000..1aee75b0d
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT MIMXRT1052)
+
+set(JLINK_DEVICE MIMXRT1052xxxxB)
+set(PYOCD_TARGET mimxrt1050)
+set(NXPLINK_DEVICE MIMXRT1052xxxxB:EVK-MIMXRT1050)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkbimxrt1050_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1052DVL6B
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
diff --git a/hw/bsp/imxrt/boards/teensy_40/board.cmake b/hw/bsp/imxrt/boards/teensy_40/board.cmake
new file mode 100644
index 000000000..41fdc78f5
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MIMXRT1062)
+
+set(JLINK_DEVICE MIMXRT1062xxx6A)
+set(PYOCD_TARGET mimxrt1060)
+set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/teensy40_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1062DVL6A
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
+
+# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
+# Make sure it is in your PATH
+# flash: $(BUILD)/$(PROJECT).hex
+# teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c b/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
index 7929906eb..dbedc90a0 100644
--- a/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
+++ b/hw/bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h>
+#include "teensy40_flexspi_nor_config.h"
 
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
diff --git a/hw/bsp/imxrt/boards/teensy_41/board.cmake b/hw/bsp/imxrt/boards/teensy_41/board.cmake
new file mode 100644
index 000000000..0fd8d528e
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT MIMXRT1062)
+
+set(JLINK_DEVICE MIMXRT1062xxx6A)
+set(PYOCD_TARGET mimxrt1060)
+set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/teensy41_flexspi_nor_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MIMXRT1062DVL6A
+    BOARD_TUD_RHPORT=0
+    BOARD_TUH_RHPORT=1
+    )
+endfunction()
+
+# flash by using teensy_loader_cli https://github.com/PaulStoffregen/teensy_loader_cli
+# Make sure it is in your PATH
+# flash: $(BUILD)/$(PROJECT).hex
+# teensy_loader_cli --mcu=imxrt1062 -v -w $<
diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
index 2d2bf8f09..f40c72cf7 100644
--- a/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
+++ b/hw/bsp/imxrt/boards/teensy_41/teensy41_flexspi_nor_config.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <bsp/imxrt/boards/teensy_40/teensy40_flexspi_nor_config.h>
+#include "teensy41_flexspi_nor_config.h"
 
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
diff --git a/tools/build_cmake.py b/tools/build_cmake.py
new file mode 100644
index 000000000..88d27dfb8
--- /dev/null
+++ b/tools/build_cmake.py
@@ -0,0 +1,99 @@
+import os
+import sys
+import time
+import subprocess
+import pathlib
+from multiprocessing import Pool
+
+import build_utils
+
+SUCCEEDED = "\033[32msucceeded\033[0m"
+FAILED = "\033[31mfailed\033[0m"
+SKIPPED = "\033[33mskipped\033[0m"
+
+build_separator = '-' * 106
+
+make_iar_option = 'CC=iccarm'
+
+def filter_with_input(mylist):
+    if len(sys.argv) > 1:
+        input_args = list(set(mylist).intersection(sys.argv))
+        if len(input_args) > 0:
+            mylist[:] = input_args
+
+
+def build_family(family, make_option):
+    all_boards = []
+    for entry in os.scandir("hw/bsp/{}/boards".format(family)):
+        if entry.is_dir() and entry.name != 'pico_sdk':
+            all_boards.append(entry.name)
+    all_boards.sort()
+
+    # success, failed, skipped
+    ret = [0, 0, 0]
+    for board in all_boards:
+        start_time = time.monotonic()
+
+        # Generate build
+        r = subprocess.run(f"cmake examples -B cmake-build-ci-{board} -G \"Ninja\" -DFAMILY={family} -DBOARD"
+                           f"={board}", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+
+        # Build
+        if r.returncode == 0:
+            r = subprocess.run(f"cmake --build cmake-build-ci-{board}", shell=True, stdout=subprocess.PIPE,
+                               stderr=subprocess.STDOUT)
+
+        duration = time.monotonic() - start_time
+
+        if r.returncode == 0:
+            status = SUCCEEDED
+            ret[0] += 1
+        else:
+            status = FAILED
+            ret[1] += 1
+
+        flash_size = "-"
+        sram_size = "-"
+        example = 'all'
+        print(build_utils.build_format.format(example, board, status, "{:.2f}s".format(duration), flash_size, sram_size))
+
+        if r.returncode != 0:
+            # group output in CI
+            print(f"::group::{board} build error")
+            print(r.stdout.decode("utf-8"))
+            print(f"::endgroup::")
+
+    return ret
+
+
+if __name__ == '__main__':
+    # IAR CC
+    if make_iar_option not in sys.argv:
+        make_iar_option = ''
+
+    # If family are not specified in arguments, build all
+    all_families = []
+    for entry in os.scandir("hw/bsp"):
+        if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name != 'espressif':
+            all_families.append(entry.name)
+    filter_with_input(all_families)
+    all_families.sort()
+
+    print(build_separator)
+    print(build_utils.build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
+    total_time = time.monotonic()
+
+    # succeeded, failed, skipped
+    total_result = [0, 0, 0]
+    for family in all_families:
+        fret = build_family(family, make_iar_option)
+        if len(fret) == len(total_result):
+            total_result = [total_result[i] + fret[i] for i in range(len(fret))]
+
+    total_time = time.monotonic() - total_time
+    print(build_separator)
+    print("Build Summary: {} {}, {} {}, {} {} and took {:.2f}s".format(total_result[0], SUCCEEDED, total_result[1],
+                                                                       FAILED, total_result[2], SKIPPED, total_time))
+    print(build_separator)
+
+    sys.exit(total_result[1])

From c3770019cb3d49d8b17a1135e10cfc2d77905a4e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 May 2023 13:50:24 +0700
Subject: [PATCH 1705/2085] install ninja

---
 .github/workflows/cmake_arm.yml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 3a1ef4f4f..412244836 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -44,6 +44,9 @@ jobs:
       with:
         release: '11.2-2022.02'
 
+    - name: Install Ninja
+      run: apt install -y ninja-build
+
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 

From c4b2fed8bd8e54d60925c90b2876f87c3662d56c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 May 2023 13:51:45 +0700
Subject: [PATCH 1706/2085] forgot sudo

---
 .github/workflows/cmake_arm.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 412244836..844a03443 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -45,7 +45,7 @@ jobs:
         release: '11.2-2022.02'
 
     - name: Install Ninja
-      run: apt install -y ninja-build
+      run: sudo apt install -y ninja-build
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3

From 1e91fc97e2f99c26e672a2c4ad76bcb6af529c28 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 May 2023 14:59:23 +0700
Subject: [PATCH 1707/2085] remove imxrt from makebuild

---
 .github/workflows/build_arm.yml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index b60d12a98..f0b01b43d 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -33,7 +33,6 @@ jobs:
         family:
         # Alphabetical order
         - 'broadcom_32bit'
-        - 'imxrt'
         - 'kinetis_k32 kinetis_kl'
         - 'lpc11 lpc13 lpc15 lpc17 lpc18'
         - 'lpc51 lpc54 lpc55'

From 137d51688225915e8251a55a5dad6d9f41963036 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 May 2023 15:32:39 +0700
Subject: [PATCH 1708/2085] try to fix build doc

---
 .readthedocs.yaml | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index 1421b397a..e26b1f475 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -4,11 +4,18 @@
 
 version: 2
 
+# Set the version of Python and other tools you might need
+build:
+  os: ubuntu-22.04
+  tools:
+    python: "3.11"
+
+# Build documentation in the docs/ directory with Sphinx
 sphinx:
    configuration: docs/conf.py
 
+# Optionally declare the Python requirements required to build your docs
 python:
-  version: 3.8
   install:
     - requirements: docs/requirements.txt
 

From eaa159c0a6a0a56a56507e44e83fe1883b3995c2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 May 2023 15:52:33 +0700
Subject: [PATCH 1709/2085] more doc build fix

---
 docs/info/changelog.rst | 2 +-
 docs/requirements.txt   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst
index ca715cb58..c6c02d181 100644
--- a/docs/info/changelog.rst
+++ b/docs/info/changelog.rst
@@ -93,7 +93,7 @@ Controller Driver (DCD & HCD)
 
   - CFG_TUD_ENABLED/CFG_TUH_ENABLED, CFG_TUD_MAX_SPEED/CFG_TUH_MAX_SPEED can be used to replace CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE
   - tud_init(rphort), tuh_init(rhport) can be used to init stack on specified roothub port (controller) instead of tusb_init(void)
-- Add dcd/hcd port specific defines TUP_ (stand for tinyusb port-specific)
+- Add dcd/hcd port specific defines `TUP_` (stand for tinyusb port-specific)
 - [dwc2]
 
   - Update to support stm32 h72x, h73x with only 1 otg controller
diff --git a/docs/requirements.txt b/docs/requirements.txt
index 15022e147..ad5c89922 100644
--- a/docs/requirements.txt
+++ b/docs/requirements.txt
@@ -1,4 +1,4 @@
-sphinx~=3.0
+sphinx>=5.0
 furo>=2020.12.30.b24
 sphinx-autodoc-typehints>=1.10
-jinja2==3.0.3
+jinja2>=3.0.3

From 9c1918fe465b9cbb77540bf3c37b64103a537d47 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 12 May 2023 13:13:42 +0200
Subject: [PATCH 1710/2085] Remove deprecated dcd_synopsys

---
 tools/iar_template.ipcf | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index 32bfce08c..6ea1d576d 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -147,9 +147,6 @@
 		<group name="src/portable/st/stm32_fsdev">
 			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
 		</group>
-		<group name="src/portable/st/synopsys">
-			<path>$TUSB_DIR$/src/portable/st/synopsys/dcd_synopsys.c</path>
-		</group>
 		<group name="src/portable/sunxi">
 			<path>$TUSB_DIR$/src/portable/sunxi/dcd_sunxi_musb.c</path>
 		</group>

From 2c745d1b1eb6c57235372e2f8fe4a8a806a8f4f7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 May 2023 18:15:48 +0700
Subject: [PATCH 1711/2085] able to build lpc55

---
 examples/cmake/cpu/cortex-m33.cmake           |  12 ++
 hw/bsp/imxrt/family.cmake                     |   1 +
 .../lpc55/boards/lpcxpresso55s69/board.cmake  |  12 ++
 hw/bsp/lpc55/family.c                         |   3 +
 hw/bsp/lpc55/family.cmake                     | 181 ++++++++++++++++++
 hw/bsp/lpc55/family.mk                        |   1 +
 6 files changed, 210 insertions(+)
 create mode 100644 examples/cmake/cpu/cortex-m33.cmake
 create mode 100644 hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
 create mode 100644 hw/bsp/lpc55/family.cmake

diff --git a/examples/cmake/cpu/cortex-m33.cmake b/examples/cmake/cpu/cortex-m33.cmake
new file mode 100644
index 000000000..fbd5027b1
--- /dev/null
+++ b/examples/cmake/cpu/cortex-m33.cmake
@@ -0,0 +1,12 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  list(APPEND TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m33
+    -mfloat-abi=hard
+    -mfpu=fpv5-d16
+    )
+
+  set(FREERTOS_PORT GCC_ARM_CM33_NONSECURE CACHE INTERNAL "")
+else ()
+  # TODO support IAR
+endif ()
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index b510c064e..4881f9c0f 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -98,6 +98,7 @@ function(family_configure_target TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
     )
   target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
new file mode 100644
index 000000000..9cc5ed3c5
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT LPC55S69)
+set(MCU_CORE LPC55S69_cm33_core0)
+
+set(JLINK_DEVICE LPC55S69)
+set(PYOCD_TARGET LPC55S69)
+set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC55S69JBD100_cm33_core0
+    )
+endfunction()
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index 3ed00e7da..1d2c87b4f 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -31,8 +31,11 @@
 #include "fsl_power.h"
 #include "fsl_iocon.h"
 #include "fsl_usart.h"
+
+#ifdef NEOPIXEL_PIN
 #include "fsl_sctimer.h"
 #include "sct_neopixel.h"
+#endif
 
 #ifdef BOARD_TUD_RHPORT
   #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
new file mode 100644
index 000000000..729454b5e
--- /dev/null
+++ b/hw/bsp/lpc55/family.cmake
@@ -0,0 +1,181 @@
+if (TARGET _${FAMILY}_family_inclusion_marker)
+  return()
+endif ()
+
+add_library(_${FAMILY}_family_inclusion_marker INTERFACE)
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+set(BOARD_TARGET board_${BOARD})
+if (NOT TARGET ${BOARD_TARGET})
+  # TOP is path to root directory
+  set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
+
+  set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+  set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+  add_library(${BOARD_TARGET} STATIC
+    # external driver
+    #lib/sct_neopixel/sct_neopixel.c
+    # driver
+    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_TUSB_MCU=OPT_MCU_LPC55XX
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    # driver
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/lpc_iocon
+    ${SDK_DIR}/drivers/lpc_gpio
+    ${SDK_DIR}/drivers/lpuart
+    # mcu
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    )
+  update_board(${BOARD_TARGET})
+
+  if (TOOLCHAIN STREQUAL "gcc")
+    target_sources(${BOARD_TARGET} PUBLIC
+      ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      # linker file
+      "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
+      # link map
+      "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  else ()
+    # TODO support IAR
+  endif ()
+endif () # BOARD_TARGET
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_target TARGET)
+  # set output name to .elf
+  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+
+  # TOP is path to root directory
+  set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # TinyUSB Port
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  #---------- TinyUSB ----------
+  # tinyusb target is built for each example since it depends on example's tusb_config.h
+  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+  add_library(${TARGET}-tinyusb_config INTERFACE)
+
+  target_include_directories(${TARGET}-tinyusb_config INTERFACE
+    ${CMAKE_CURRENT_SOURCE_DIR}/src
+    )
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_MCU=OPT_MCU_LPC55XX
+    )
+
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+
+  # group target (not yet supported by clion)
+  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
+    PROPERTIES FOLDER ${TARGET}_sub
+    )
+
+  #---------- Flash ----------
+  # Flash using pyocd
+  add_custom_target(${TARGET}-pyocd
+    COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
+    )
+
+  # Flash using NXP LinkServer (redlink)
+  # https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
+  # LinkServer has a bug that can only execute with full path otherwise it throws:
+  # realpath error: No such file or directory
+  execute_process(COMMAND which LinkServer OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
+  add_custom_target(${TARGET}-nxplink
+    COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
+    )
+
+endfunction()
+
+
+function(family_add_freertos TARGET)
+  # freertos_config
+  add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config)
+
+  ## freertos
+  if (NOT TARGET freertos_kernel)
+    add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
+  endif ()
+
+  # Add FreeRTOS option to tinyusb_config
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_OS=OPT_OS_FREERTOS
+    )
+  # link tinyusb with freeRTOS kernel
+  target_link_libraries(${TARGET}-tinyusb PUBLIC
+    freertos_kernel
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    freertos_kernel
+    )
+endfunction()
+
+function(family_configure_device_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index f9dabcfa3..ee0b1ca7f 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -42,6 +42,7 @@ SRC_C += \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(MCU_DIR)/drivers/fsl_power.c \
 	$(MCU_DIR)/drivers/fsl_reset.c \
+
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
 	$(SDK_DIR)/drivers/common/fsl_common_arm.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \

From dbcef41f95a1c52079c005586d196a5b22060b13 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 10 May 2023 18:22:51 +0700
Subject: [PATCH 1712/2085] add support for other lpc55 boards

---
 hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake | 12 ++++++++++++
 hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake |  2 ++
 hw/bsp/lpc55/boards/mcu_link/board.cmake        | 14 ++++++++++++++
 3 files changed, 28 insertions(+)
 create mode 100644 hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
 create mode 100644 hw/bsp/lpc55/boards/mcu_link/board.cmake

diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
new file mode 100644
index 000000000..d935b70e6
--- /dev/null
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT LPC55S28)
+set(MCU_CORE LPC55S28)
+
+set(JLINK_DEVICE LPC55S28)
+set(PYOCD_TARGET LPC55S28)
+set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC55S28JBD100
+    )
+endfunction()
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
index 9cc5ed3c5..fd7cb6de6 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
@@ -8,5 +8,7 @@ set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S69JBD100_cm33_core0
+    # port 1 is highspeed
+    # BOARD_TUD_RHPORT=1
     )
 endfunction()
diff --git a/hw/bsp/lpc55/boards/mcu_link/board.cmake b/hw/bsp/lpc55/boards/mcu_link/board.cmake
new file mode 100644
index 000000000..fd7cb6de6
--- /dev/null
+++ b/hw/bsp/lpc55/boards/mcu_link/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT LPC55S69)
+set(MCU_CORE LPC55S69_cm33_core0)
+
+set(JLINK_DEVICE LPC55S69)
+set(PYOCD_TARGET LPC55S69)
+set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC55S69JBD100_cm33_core0
+    # port 1 is highspeed
+    # BOARD_TUD_RHPORT=1
+    )
+endfunction()

From a57ba87859c90ae7e5d8419685fffef87db67b21 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Thu, 11 May 2023 15:16:32 +0700
Subject: [PATCH 1713/2085] revert family.mk

---
 hw/bsp/lpc55/family.mk | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index ee0b1ca7f..f9dabcfa3 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -42,7 +42,6 @@ SRC_C += \
 	$(MCU_DIR)/drivers/fsl_clock.c \
 	$(MCU_DIR)/drivers/fsl_power.c \
 	$(MCU_DIR)/drivers/fsl_reset.c \
-
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
 	$(SDK_DIR)/drivers/common/fsl_common_arm.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \

From 9fd0fee458759c49acbeab6b9382df287620e532 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 May 2023 14:25:42 +0700
Subject: [PATCH 1714/2085] adding nrf

---
 .idea/cmake.xml                        |   6 +-
 examples/cmake/cpu/cortex-m4.cmake     |  12 ++
 examples/rules.mk                      |   2 +-
 hw/bsp/lpc55/family.cmake              |   4 +-
 hw/bsp/nrf/boards/pca10056/board.cmake |   8 ++
 hw/bsp/nrf/family.cmake                | 176 +++++++++++++++++++++++++
 6 files changed, 203 insertions(+), 5 deletions(-)
 create mode 100644 examples/cmake/cpu/cortex-m4.cmake
 create mode 100644 hw/bsp/nrf/boards/pca10056/board.cmake
 create mode 100644 hw/bsp/nrf/family.cmake

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 4d9fc9aa5..52b698227 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,6 +2,8 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
+      <configuration PROFILE_NAME="pca10056" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" />
+      <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc55 -DBOARD=lpcxpresso55s69" />
       <configuration PROFILE_NAME="esp32s3" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_s3_devkitm -DIDF_TARGET=esp32s3">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
@@ -22,8 +24,8 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="rp2040" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=rp2040 -DBOARD=raspberry_pi_pico" />
-      <configuration PROFILE_NAME="rt1010 evk" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1010_evk" />
+      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=rp2040 -DBOARD=raspberry_pi_pico" />
+      <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1010_evk" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/examples/cmake/cpu/cortex-m4.cmake b/examples/cmake/cpu/cortex-m4.cmake
new file mode 100644
index 000000000..5a2d16c05
--- /dev/null
+++ b/examples/cmake/cpu/cortex-m4.cmake
@@ -0,0 +1,12 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  list(APPEND TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m4
+    -mfloat-abi=hard
+    -mfpu=fpv4-sp-d16
+    )
+
+  set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
+else ()
+  # TODO support IAR
+endif ()
diff --git a/examples/rules.mk b/examples/rules.mk
index 516beca78..2eaa48e2e 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -86,7 +86,7 @@ LDFLAGS += -Wl,-T,$(TOP)/$(GCC_LD_FILE)
 endif
 
 ifneq ($(SKIP_NANOLIB), 1)
-LDFLAGS += -specs=nosys.specs -specs=nano.specs
+LDFLAGS += --specs=nosys.specs --specs=nano.specs
 endif
 
 ASFLAGS += $(CFLAGS)
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 729454b5e..0ac2b6ce3 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -1,8 +1,8 @@
-if (TARGET _${FAMILY}_family_inclusion_marker)
+if (TARGET _lpc55_family_inclusion_marker)
   return()
 endif ()
 
-add_library(_${FAMILY}_family_inclusion_marker INTERFACE)
+add_library(_lpc55_family_inclusion_marker INTERFACE)
 
 if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake
new file mode 100644
index 000000000..cc8ef2fcb
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10056/board.cmake
@@ -0,0 +1,8 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_gcc ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    NRF52840_XXAA
+    )
+endfunction()
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
new file mode 100644
index 000000000..7adee5a03
--- /dev/null
+++ b/hw/bsp/nrf/family.cmake
@@ -0,0 +1,176 @@
+if (TARGET _nrf_family_inclusion_marker)
+  return()
+endif ()
+
+add_library(_nrf_family_inclusion_marker INTERFACE)
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
+
+# TOP is path to root directory
+set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
+set(NRFX_DIR ${TOP}/hw/mcu/nordic/nrfx)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+set(JLINK_DEVICE $(MCU_VARIANT)_xxaa)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+set(BOARD_TARGET board_${BOARD})
+if (NOT TARGET ${BOARD_TARGET})
+  add_library(${BOARD_TARGET} STATIC
+    # driver
+    ${NRFX_DIR}/drivers/src/nrfx_power.c
+    ${NRFX_DIR}/drivers/src/nrfx_uarte.c
+    # mcu
+    ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CONFIG_GPIO_AS_PINRESET
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${NRFX_DIR}/../ # hw/mcu/nordic: remove later
+    # driver
+    ${NRFX_DIR}
+    ${NRFX_DIR}/mdk
+    ${NRFX_DIR}/hal
+    ${NRFX_DIR}/drivers/include
+    ${NRFX_DIR}/drivers/src
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    )
+  update_board(${BOARD_TARGET})
+
+  if (NOT DEFINED LD_FILE_${TOOLCHAIN})
+    set(LD_FILE_gcc ${NRFX_DIR}/mdk/${MCU_VARIANT}_xxaa.ld)
+  endif ()
+
+  if (TOOLCHAIN STREQUAL "gcc")
+    target_sources(${BOARD_TARGET} PUBLIC
+      ${NRFX_DIR}/mdk/gcc_startup_${MCU_VARIANT}.S
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      # linker file
+      "LINKER:--script=${LD_FILE_gcc}"
+      -L${NRFX_DIR}/mdk
+      # link map
+      "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  else ()
+    # TODO support IAR
+  endif ()
+endif () # BOARD_TARGET
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_target TARGET)
+  # set output name to .elf
+  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+
+  # TOP is path to root directory
+  set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # TinyUSB Port
+    ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  #---------- TinyUSB ----------
+  # tinyusb target is built for each example since it depends on example's tusb_config.h
+  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+  add_library(${TARGET}-tinyusb_config INTERFACE)
+
+  target_include_directories(${TARGET}-tinyusb_config INTERFACE
+    ${CMAKE_CURRENT_SOURCE_DIR}/src
+    )
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_MCU=OPT_MCU_NRF5X
+    )
+
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+
+  # group target (not yet supported by clion)
+  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
+    PROPERTIES FOLDER ${TARGET}_sub
+    )
+
+  #---------- Flash ----------
+  # Flash using pyocd
+  add_custom_target(${TARGET}-pyocd
+    COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
+    )
+
+  # Flash using NXP LinkServer (redlink)
+  # https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
+  # LinkServer has a bug that can only execute with full path otherwise it throws:
+  # realpath error: No such file or directory
+  execute_process(COMMAND which LinkServer OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
+  add_custom_target(${TARGET}-nxplink
+    COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
+    )
+
+endfunction()
+
+
+function(family_add_freertos TARGET)
+  # freertos_config
+  add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config)
+
+  ## freertos
+  if (NOT TARGET freertos_kernel)
+    add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
+  endif ()
+
+  # Add FreeRTOS option to tinyusb_config
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_OS=OPT_OS_FREERTOS
+    )
+  # link tinyusb with freeRTOS kernel
+  target_link_libraries(${TARGET}-tinyusb PUBLIC
+    freertos_kernel
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    freertos_kernel
+    )
+endfunction()
+
+function(family_configure_device_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()

From 9f5b08dc93176485c5a4d9ce58271e22f765d976 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Mon, 15 May 2023 14:39:49 +0700
Subject: [PATCH 1715/2085] Update build_arm.yml

try bump up gcc to 12
---
 .github/workflows/build_arm.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index f0b01b43d..565fc3f27 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -58,7 +58,7 @@ jobs:
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
       with:
-        release: '11.2-2022.02'
+        release: '12.2.Rel1'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3

From d7175ad834ff80978a560db9c3a5e21b0716029e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 May 2023 16:51:06 +0700
Subject: [PATCH 1716/2085] update nrf cmake and make to support nrf5340
 (pca10095)

---
 .idea/cmake.xml                        |  3 +-
 examples/rules.mk                      |  2 +-
 hw/bsp/imxrt/family.cmake              |  2 ++
 hw/bsp/nrf/boards/pca10095/board.cmake | 12 +++++++
 hw/bsp/nrf/boards/pca10095/board.h     | 50 ++++++++++++++++++++++++++
 hw/bsp/nrf/boards/pca10095/board.mk    | 13 +++++++
 hw/bsp/nrf/family.c                    | 40 ++++++++++++++++-----
 hw/bsp/nrf/family.cmake                | 46 +++++++++++++++---------
 hw/bsp/nrf/family.mk                   |  5 ++-
 hw/bsp/nrf/nrfx_config.h               | 46 ++++++++++++++++++++++++
 hw/{mcu/nordic => bsp/nrf}/nrfx_glue.h |  0
 hw/{mcu/nordic => bsp/nrf}/nrfx_log.h  |  0
 hw/mcu/nordic/nrfx_config.h            | 18 ----------
 13 files changed, 189 insertions(+), 48 deletions(-)
 create mode 100644 hw/bsp/nrf/boards/pca10095/board.cmake
 create mode 100644 hw/bsp/nrf/boards/pca10095/board.h
 create mode 100644 hw/bsp/nrf/boards/pca10095/board.mk
 create mode 100644 hw/bsp/nrf/nrfx_config.h
 rename hw/{mcu/nordic => bsp/nrf}/nrfx_glue.h (100%)
 rename hw/{mcu/nordic => bsp/nrf}/nrfx_log.h (100%)
 delete mode 100644 hw/mcu/nordic/nrfx_config.h

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 52b698227..bbef86164 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,7 +2,8 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="pca10056" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" />
+      <configuration PROFILE_NAME="pca10095" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095" BUILD_OPTIONS="-v" />
+      <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" BUILD_OPTIONS="-v" />
       <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc55 -DBOARD=lpcxpresso55s69" />
       <configuration PROFILE_NAME="esp32s3" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_s3_devkitm -DIDF_TARGET=esp32s3">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
diff --git a/examples/rules.mk b/examples/rules.mk
index 2eaa48e2e..426000128 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -230,7 +230,7 @@ JLINK_IF ?= swd
 # Flash using jlink
 flash-jlink: $(BUILD)/$(PROJECT).hex
 	@echo halt > $(BUILD)/$(BOARD).jlink
-	@echo r > $(BUILD)/$(BOARD).jlink
+	@echo r >> $(BUILD)/$(BOARD).jlink
 	@echo loadfile $^ >> $(BUILD)/$(BOARD).jlink
 	@echo r >> $(BUILD)/$(BOARD).jlink
 	@echo go >> $(BUILD)/$(BOARD).jlink
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 4881f9c0f..77ac05c87 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -130,6 +130,7 @@ function(family_configure_target TARGET)
   #---------- Flash ----------
   # Flash using pyocd
   add_custom_target(${TARGET}-pyocd
+    DEPENDS ${TARGET}
     COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
     )
 
@@ -139,6 +140,7 @@ function(family_configure_target TARGET)
   # realpath error: No such file or directory
   execute_process(COMMAND which LinkServer OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
   add_custom_target(${TARGET}-nxplink
+    DEPENDS ${TARGET}
     COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
     )
 
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
new file mode 100644
index 000000000..e90d76e91
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT nrf5340_application)
+set(LD_FILE_gcc ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    NRF5340_XXAA
+    NRF5340_XXAA_APPLICATION
+    )
+  target_sources(${TARGET} PUBLIC
+    ${NRFX_DIR}/drivers/src/nrfx_usbreg.c
+    )
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h
new file mode 100644
index 000000000..fd3c63d6a
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/board.h
@@ -0,0 +1,50 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PIN               28
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PIN            23
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_RX_PIN           32
+#define UART_TX_PIN           33
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/nrf/boards/pca10095/board.mk b/hw/bsp/nrf/boards/pca10095/board.mk
new file mode 100644
index 000000000..5ad103d62
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/board.mk
@@ -0,0 +1,13 @@
+MCU_VARIANT = nrf5340_application
+CFLAGS += -DNRF5340_XXAA -DNRF5340_XXAA_APPLICATION
+
+LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf5340_xxaa_application.ld
+
+SRC_C += hw/mcu/nordic/nrfx/drivers/src/nrfx_usbreg.c
+
+# caused by void SystemStoreFICRNS() (without void) in system_nrf5340_application.c
+CFLAGS += -Wno-error=strict-prototypes
+
+# flash using jlink
+JLINK_DEVICE = nrf5340_xxaa_app
+flash: flash-jlink
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 02cec31ef..157b2bf21 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -28,9 +28,9 @@
 #include "board.h"
 
 #include "nrfx.h"
-#include "nrfx/hal/nrf_gpio.h"
-#include "nrfx/drivers/include/nrfx_power.h"
-#include "nrfx/drivers/include/nrfx_uarte.h"
+#include "hal/nrf_gpio.h"
+#include "drivers/include/nrfx_power.h"
+#include "drivers/include/nrfx_uarte.h"
 
 #ifdef SOFTDEVICE_PRESENT
 #include "nrf_sdm.h"
@@ -49,6 +49,23 @@ void USBD_IRQHandler(void)
 /* MACRO TYPEDEF CONSTANT ENUM
  *------------------------------------------------------------------*/
 
+// Value is chosen to be as same as NRFX_POWER_USB_EVT_* in nrfx_power.h
+enum {
+  USB_EVT_DETECTED = 0,
+  USB_EVT_REMOVED = 1,
+  USB_EVT_READY = 2
+};
+
+#ifdef NRF5340_XXAA
+  #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC
+  #define VBUSDETECT_Msk USBREG_USBREGSTATUS_VBUSDETECT_Msk
+  #define OUTPUTRDY_Msk USBREG_USBREGSTATUS_OUTPUTRDY_Msk
+#else
+  #define LFCLK_SRC_RC CLOCK_LFCLKSRC_SRC_RC
+  #define VBUSDETECT_Msk POWER_USBREGSTATUS_VBUSDETECT_Msk
+  #define OUTPUTRDY_Msk POWER_USBREGSTATUS_OUTPUTRDY_Msk
+#endif
+
 static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0);
 
 // tinyusb function that handles power event (detected, ready, removed)
@@ -68,7 +85,7 @@ void board_init(void)
   NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
 
   // Use Internal OSC to compatible with all boards
-  NRF_CLOCK->LFCLKSRC = CLOCK_LFCLKSRC_SRC_RC;
+  NRF_CLOCK->LFCLKSRC = LFCLK_SRC_RC;
   NRF_CLOCK->TASKS_LFCLKSTART = 1UL;
 
   // LED
@@ -123,21 +140,26 @@ void board_init(void)
 #endif
   {
     // Power module init
-    const nrfx_power_config_t pwr_cfg = { 0 };
+    const nrfx_power_config_t pwr_cfg = {0};
     nrfx_power_init(&pwr_cfg);
 
     // Register tusb function as USB power handler
     // cause cast-function-type warning
-    const nrfx_power_usbevt_config_t config = { .handler = power_event_handler };
+    const nrfx_power_usbevt_config_t config = {.handler = power_event_handler};
     nrfx_power_usbevt_init(&config);
-
     nrfx_power_usbevt_enable();
 
+    // USB power may already be ready at this time -> no event generated
+    // We need to invoke the handler based on the status initially
+    #ifdef NRF5340_XXAA
+    usb_reg = NRF_USBREGULATOR->USBREGSTATUS;
+    #else
     usb_reg = NRF_POWER->USBREGSTATUS;
+    #endif
   }
 
-  if ( usb_reg & POWER_USBREGSTATUS_VBUSDETECT_Msk ) tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_DETECTED);
-  if ( usb_reg & POWER_USBREGSTATUS_OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(NRFX_POWER_USB_EVT_READY);
+  if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED);
+  if ( usb_reg & OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(USB_EVT_READY);
 #endif
 }
 
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 7adee5a03..c8faa23cc 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -8,12 +8,6 @@ if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
 endif ()
 
-# toolchain set up
-set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-
-set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
-
 # TOP is path to root directory
 set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
 set(NRFX_DIR ${TOP}/hw/mcu/nordic/nrfx)
@@ -21,7 +15,19 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-set(JLINK_DEVICE $(MCU_VARIANT)_xxaa)
+
+# toolchain set up
+if (MCU_VARIANT STREQUAL "nrf5340_application")
+  set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+  set(JLINK_DEVICE nrf5340_xxaa_app)
+else ()
+  set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+  set(JLINK_DEVICE ${MCU_VARIANT}_xxaa)
+endif ()
+
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
 
 #------------------------------------
 # BOARD_TARGET
@@ -40,8 +46,7 @@ if (NOT TARGET ${BOARD_TARGET})
     CONFIG_GPIO_AS_PINRESET
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
-    ${NRFX_DIR}/../ # hw/mcu/nordic: remove later
-    # driver
+    ${CMAKE_CURRENT_LIST_DIR}
     ${NRFX_DIR}
     ${NRFX_DIR}/mdk
     ${NRFX_DIR}/hal
@@ -78,6 +83,8 @@ endif () # BOARD_TARGET
 # Functions
 #------------------------------------
 function(family_configure_target TARGET)
+  #family_add_default_example_warnings(${TARGET})
+
   # set output name to .elf
   set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
 
@@ -126,16 +133,23 @@ function(family_configure_target TARGET)
   #---------- Flash ----------
   # Flash using pyocd
   add_custom_target(${TARGET}-pyocd
+    DEPENDS ${TARGET}
     COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
     )
 
-  # Flash using NXP LinkServer (redlink)
-  # https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
-  # LinkServer has a bug that can only execute with full path otherwise it throws:
-  # realpath error: No such file or directory
-  execute_process(COMMAND which LinkServer OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
-  add_custom_target(${TARGET}-nxplink
-    COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
+  # Flash using jlink
+  set(JLINKEXE JLinkExe)
+  file(GENERATE
+    OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
+    CONTENT "halt
+loadfile $<TARGET_FILE:${TARGET}>
+r
+go
+exit"
+    )
+  add_custom_target(${TARGET}-jlink
+    DEPENDS ${TARGET}
+    COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
     )
 
 endfunction()
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index 4102c8187..310578d02 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -14,7 +14,7 @@ CFLAGS += \
   -DCONFIG_GPIO_AS_PINRESET
 
 # suppress warning caused by vendor mcu driver
-CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual
+CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
 
 # All source paths should be relative to the top level.
 LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
@@ -30,7 +30,6 @@ SRC_C += \
 INC += \
   $(TOP)/$(BOARD_PATH) \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/hw/mcu/nordic \
   $(TOP)/hw/mcu/nordic/nrfx \
   $(TOP)/hw/mcu/nordic/nrfx/mdk \
   $(TOP)/hw/mcu/nordic/nrfx/hal \
@@ -45,4 +44,4 @@ ASFLAGS += -D__HEAP_SIZE=0
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 
 # For flash-jlink target
-JLINK_DEVICE = $(MCU_VARIANT)_xxaa
+JLINK_DEVICE ?= $(MCU_VARIANT)_xxaa
diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h
new file mode 100644
index 000000000..696a3fb04
--- /dev/null
+++ b/hw/bsp/nrf/nrfx_config.h
@@ -0,0 +1,46 @@
+#ifndef NRFX_CONFIG_H__
+#define NRFX_CONFIG_H__
+
+#define NRFX_POWER_ENABLED   1
+#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY  7
+
+#define NRFX_CLOCK_ENABLED   0
+
+#define NRFX_UARTE_ENABLED   1
+#define NRFX_UARTE0_ENABLED  1
+
+#define NRFX_UARTE1_ENABLED  0
+#define NRFX_UARTE2_ENABLED  0
+#define NRFX_UARTE3_ENABLED  0
+
+#define NRFX_PRS_ENABLED     0
+#define NRFX_USBREG_ENABLED  1
+
+#if defined(NRF51)
+#include <templates/nrfx_config_nrf51.h>
+#elif defined(NRF52805_XXAA)
+#include <templates/nrfx_config_nrf52805.h>
+#elif defined(NRF52810_XXAA)
+#include <templates/nrfx_config_nrf52810.h>
+#elif defined(NRF52811_XXAA)
+#include <templates/nrfx_config_nrf52811.h>
+#elif defined(NRF52820_XXAA)
+#include <templates/nrfx_config_nrf52820.h>
+#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB)
+#include <templates/nrfx_config_nrf52832.h>
+#elif defined(NRF52833_XXAA)
+#include <templates/nrfx_config_nrf52833.h>
+#elif defined(NRF52840_XXAA)
+#include <templates/nrfx_config_nrf52840.h>
+#elif defined(NRF5340_XXAA_APPLICATION)
+#include <templates/nrfx_config_nrf5340_application.h>
+#elif defined(NRF5340_XXAA_NETWORK)
+    #include <templates/nrfx_config_nrf5340_network.h>
+#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA)
+    #include <templates/nrfx_config_nrf91.h>
+#else
+    #error "Unknown device."
+#endif
+
+
+#endif // NRFX_CONFIG_H__
diff --git a/hw/mcu/nordic/nrfx_glue.h b/hw/bsp/nrf/nrfx_glue.h
similarity index 100%
rename from hw/mcu/nordic/nrfx_glue.h
rename to hw/bsp/nrf/nrfx_glue.h
diff --git a/hw/mcu/nordic/nrfx_log.h b/hw/bsp/nrf/nrfx_log.h
similarity index 100%
rename from hw/mcu/nordic/nrfx_log.h
rename to hw/bsp/nrf/nrfx_log.h
diff --git a/hw/mcu/nordic/nrfx_config.h b/hw/mcu/nordic/nrfx_config.h
deleted file mode 100644
index 6a974ba70..000000000
--- a/hw/mcu/nordic/nrfx_config.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef NRFX_CONFIG_H__
-#define NRFX_CONFIG_H__
-
-#define NRFX_POWER_ENABLED   1
-#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY  7
-
-#define NRFX_CLOCK_ENABLED   0
-
-#define NRFX_UARTE_ENABLED   1
-#define NRFX_UARTE0_ENABLED  1
-
-#define NRFX_UARTE1_ENABLED  0
-#define NRFX_UARTE2_ENABLED  0
-#define NRFX_UARTE3_ENABLED  0
-
-#define NRFX_PRS_ENABLED     0
-
-#endif // NRFX_CONFIG_H__

From 792cf95f2d20be2908f87f4960edadcf10c207dd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 15 May 2023 23:35:29 +0700
Subject: [PATCH 1717/2085] revert ci gcc to 11.2, update nrfx to version 2.11

---
 .github/workflows/build_arm.yml | 2 +-
 tools/get_deps.py               | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 565fc3f27..f0b01b43d 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -58,7 +58,7 @@ jobs:
     - name: Install ARM GCC
       uses: carlosperate/arm-none-eabi-gcc-action@v1
       with:
-        release: '12.2.Rel1'
+        release: '11.2-2022.02'
 
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
diff --git a/tools/get_deps.py b/tools/get_deps.py
index d8b044343..be5738dc1 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -21,7 +21,7 @@ deps_optional = {
     'hw/mcu/infineon/mtb-xmclib-cat3'          : ['daf5500d03cba23e68c2f241c30af79cd9d63880', 'https://github.com/Infineon/mtb-xmclib-cat3.git'               ],
     'hw/mcu/microchip'                         : ['9e8b37e307d8404033bb881623a113931e1edf27', 'https://github.com/hathach/microchip_driver.git'               ],
     'hw/mcu/mindmotion/mm32sdk'                : ['0b79559eb411149d36e073c1635c620e576308d4', 'https://github.com/hathach/mm32sdk.git'                        ],
-    'hw/mcu/nordic/nrfx'                       : ['281cc2e178fd9a470d844b3afdea9eb322a0b0e8', 'https://github.com/NordicSemiconductor/nrfx.git'               ],
+    'hw/mcu/nordic/nrfx'                       : ['2527e3c8449cfd38aee41598e8af8492f410ed15', 'https://github.com/NordicSemiconductor/nrfx.git'               ],
     'hw/mcu/nuvoton'                           : ['2204191ec76283371419fbcec207da02e1bc22fa', 'https://github.com/majbthrd/nuc_driver.git'                    ],
     'hw/mcu/nxp/lpcopen'                       : ['43c45c85405a5dd114fff0ea95cca62837740c13', 'https://github.com/hathach/nxp_lpcopen.git'                    ],
     'hw/mcu/nxp/mcux-sdk'                      : ['f357a1150f6cf6c6b844f53f2d426bfb3e649850', 'https://github.com/NXPmicro/mcux-sdk.git'                      ],

From 116a258858ef3c58639d00346e197bd07ad86952 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 16 May 2023 10:14:00 +0700
Subject: [PATCH 1718/2085] fix nrf build

---
 hw/bsp/nrf/boards/adafruit_clue/board.mk      |  3 ++
 .../arduino_nano33_ble/arduino_nano33_ble.ld  |  2 +-
 .../circuitplayground_bluefruit/board.mk      |  3 ++
 .../nrf52840_s140_v6.ld                       | 38 -------------------
 .../boards/feather_nrf52840_express/board.mk  |  3 ++
 .../nrf52840_s140_v6.ld                       | 38 -------------------
 .../boards/feather_nrf52840_sense/board.mk    |  3 ++
 .../nrf52840_s140_v6.ld                       | 38 -------------------
 hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk |  3 ++
 .../itsybitsy_nrf52840/nrf52840_s140_v6.ld    | 38 -------------------
 hw/bsp/nrf/family.mk                          |  3 --
 .../nrf52840_s140_v6.ld                       |  2 +-
 tools/build_family.py                         |  4 +-
 13 files changed, 19 insertions(+), 159 deletions(-)
 delete mode 100755 hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
 delete mode 100644 hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
 delete mode 100644 hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
 delete mode 100644 hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
 rename hw/bsp/nrf/{boards/adafruit_clue => linker}/nrf52840_s140_v6.ld (96%)
 mode change 100755 => 100644

diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.mk b/hw/bsp/nrf/boards/adafruit_clue/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/adafruit_clue/board.mk
+++ b/hw/bsp/nrf/boards/adafruit_clue/board.mk
@@ -1,6 +1,9 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
 $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
 
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld b/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
index f609f743f..b7cac1019 100755
--- a/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/arduino_nano33_ble.ld
@@ -29,4 +29,4 @@ SECTIONS
   } > RAM
 } INSERT AFTER .data;
 
-INCLUDE "nrf52_common.ld"
+INCLUDE "nrf_common.ld"
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.mk
@@ -1,6 +1,9 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
 $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
 
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
deleted file mode 100755
index 71c55bb81..000000000
--- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk b/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
@@ -1,6 +1,9 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
 $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
 
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
deleted file mode 100644
index 71c55bb81..000000000
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.mk
@@ -1,6 +1,9 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
 $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
 
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
deleted file mode 100644
index 71c55bb81..000000000
--- a/hw/bsp/nrf/boards/feather_nrf52840_sense/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
index f31899eb7..b80807963 100644
--- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.mk
@@ -1,6 +1,9 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# All source paths should be relative to the top level.
+LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
+
 $(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex
 	adafruit-nrfutil dfu genpkg --dev-type 0x0052 --sd-req 0xFFFE --application $^ $@
 
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld b/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
deleted file mode 100644
index 71c55bb81..000000000
--- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/nrf52840_s140_v6.ld
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Linker script to configure memory regions. */
-
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
-
-  /* SRAM required by S132 depend on
-   * - Attribute Table Size
-   * - Vendor UUID count
-   * - Max ATT MTU
-   * - Concurrent connection peripheral + central + secure links
-   * - Event Len, HVN queue, Write CMD queue
-   */
-  RAM (rwx) :  ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
-}
-
-SECTIONS
-{
-  . = ALIGN(4);
-  .svc_data :
-  {
-    PROVIDE(__start_svc_data = .);
-    KEEP(*(.svc_data))
-    PROVIDE(__stop_svc_data = .);
-  } > RAM
-
-  .fs_data :
-  {
-    PROVIDE(__start_fs_data = .);
-    KEEP(*(.fs_data))
-    PROVIDE(__stop_fs_data = .);
-  } > RAM
-} INSERT AFTER .data;
-
-INCLUDE "nrf52_common.ld"
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index 310578d02..d5042a160 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -16,9 +16,6 @@ CFLAGS += \
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
 
-# All source paths should be relative to the top level.
-LD_FILE ?= hw/bsp/nrf/boards/$(BOARD)/nrf52840_s140_v6.ld
-
 LDFLAGS += -L$(TOP)/hw/mcu/nordic/nrfx/mdk
 
 SRC_C += \
diff --git a/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld b/hw/bsp/nrf/linker/nrf52840_s140_v6.ld
old mode 100755
new mode 100644
similarity index 96%
rename from hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld
rename to hw/bsp/nrf/linker/nrf52840_s140_v6.ld
index 71c55bb81..e27fa1c91
--- a/hw/bsp/nrf/boards/adafruit_clue/nrf52840_s140_v6.ld
+++ b/hw/bsp/nrf/linker/nrf52840_s140_v6.ld
@@ -35,4 +35,4 @@ SECTIONS
   } > RAM
 } INSERT AFTER .data;
 
-INCLUDE "nrf52_common.ld"
+INCLUDE "nrf_common.ld"
diff --git a/tools/build_family.py b/tools/build_family.py
index 1fc25907b..9b612b4cb 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -42,9 +42,9 @@ if __name__ == '__main__':
     # If examples are not specified in arguments, build all
     all_examples = []
     for d in os.scandir("examples"):
-        if d.is_dir() and 'cmake-build' not in d.name and 'cmake' not in d.name:
+        if d.is_dir() and 'cmake' not in d.name:
             for entry in os.scandir(d.path):
-                if entry.is_dir():
+                if entry.is_dir() and 'cmake' not in entry.name:
                     all_examples.append(d.name + '/' + entry.name)
     filter_with_input(all_examples)
     all_examples.sort()

From 206d63e038744b228cfa6051d701cab50b520fe6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 11 May 2023 14:26:12 +0700
Subject: [PATCH 1719/2085] correct EHCI reporting failed xfer (instead of
 stalled) when device is unplugged

---
 src/class/cdc/cdc_host.c  | 21 +++++++++++----------
 src/class/hid/hid_host.c  | 27 ++++++++++++++++-----------
 src/class/msc/msc_host.c  | 10 +++++++---
 src/common/tusb_debug.h   |  1 +
 src/device/usbd_control.c |  9 ++++++---
 src/host/hub.c            |  9 ++++++++-
 src/host/usbh.c           | 20 +++++++++++++-------
 src/portable/ehci/ehci.c  | 11 ++++++++---
 src/tusb.c                |  4 ++++
 9 files changed, 74 insertions(+), 38 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index fe3691bf4..9ff666ed4 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -35,8 +35,7 @@
 
 // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
 #define CDCH_DEBUG   2
-
-#define TU_LOG_CDCH(...)   TU_LOG(CDCH_DEBUG, __VA_ARGS__)
+#define TU_LOG_DRV(...)   TU_LOG(CDCH_DEBUG, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
 // Host CDC Interface
@@ -537,6 +536,8 @@ void cdch_close(uint8_t daddr)
     cdch_interface_t* p_cdc = &cdch_data[idx];
     if (p_cdc->daddr == daddr)
     {
+      TU_LOG_DRV("  CDCh close addr = %u index = %u\r\n", daddr, idx);
+
       // Invoke application callback
       if (tuh_cdc_umount_cb) tuh_cdc_umount_cb(idx);
 
@@ -804,7 +805,7 @@ static void acm_process_config(tuh_xfer_t* xfer)
 
 static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
   TU_VERIFY(p_cdc->acm_capability.support_line_request);
-  TU_LOG_CDCH("CDC ACM Set Control Line State\r\n");
+  TU_LOG_DRV("CDC ACM Set Control Line State\r\n");
 
   tusb_control_request_t const request = {
     .bmRequestType_bit = {
@@ -834,7 +835,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st
 }
 
 static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  TU_LOG_CDCH("CDC ACM Set Line Conding\r\n");
+  TU_LOG_DRV("CDC ACM Set Line Conding\r\n");
 
   tusb_control_request_t const request = {
     .bmRequestType_bit = {
@@ -894,7 +895,7 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint
   cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
 
-  TU_LOG_CDCH("FTDI opened\r\n");
+  TU_LOG_DRV("FTDI opened\r\n");
 
   p_cdc->serial_drid = SERIAL_DRIVER_FTDI;
 
@@ -938,7 +939,7 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u
 
 static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  TU_LOG_CDCH("CDC FTDI Set Control Line State\r\n");
+  TU_LOG_DRV("CDC FTDI Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state,
                                  complete_cb ? cdch_internal_control_complete : NULL, user_data));
@@ -974,7 +975,7 @@ static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud)
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
-  TU_LOG_CDCH("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor);
+  TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
   _ftdi_requested_baud = baudrate;
@@ -1061,7 +1062,7 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui
   cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc);
   TU_VERIFY(p_cdc);
 
-  TU_LOG_CDCH("CP210x opened\r\n");
+  TU_LOG_DRV("CP210x opened\r\n");
   p_cdc->serial_drid = SERIAL_DRIVER_CP210X;
 
   // endpoint pair
@@ -1109,7 +1110,7 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe
 }
 
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  TU_LOG_CDCH("CDC CP210x Set BaudRate = %lu\n", baudrate);
+  TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
   p_cdc->user_control_cb = complete_cb;
   return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4,
@@ -1118,7 +1119,7 @@ static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_
 
 static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  TU_LOG_CDCH("CDC CP210x Set Control Line State\r\n");
+  TU_LOG_DRV("CDC CP210x Set Control Line State\r\n");
   p_cdc->user_control_cb = complete_cb;
   return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0,
                             complete_cb ? cdch_internal_control_complete : NULL, user_data);
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index d95d3ef35..3a491937a 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -33,6 +33,10 @@
 
 #include "hid_host.h"
 
+// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
+#define HIDH_DEBUG   2
+#define TU_LOG_DRV(...)   TU_LOG(HIDH_DEBUG, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -207,7 +211,7 @@ static void set_protocol_complete(tuh_xfer_t* xfer)
 
 static bool _hidh_set_protocol(uint8_t daddr, uint8_t itf_num, uint8_t protocol, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
-  TU_LOG2("HID Set Protocol = %d\r\n", protocol);
+  TU_LOG_DRV("HID Set Protocol = %d\r\n", protocol);
 
   tusb_control_request_t const request =
   {
@@ -246,7 +250,7 @@ bool tuh_hid_set_protocol(uint8_t daddr, uint8_t idx, uint8_t protocol)
 
 static void set_report_complete(tuh_xfer_t* xfer)
 {
-  TU_LOG2("HID Set Report complete\r\n");
+  TU_LOG_DRV("HID Set Report complete\r\n");
 
   if (tuh_hid_set_report_complete_cb)
   {
@@ -266,7 +270,7 @@ bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t r
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid);
 
-  TU_LOG2("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len);
+  TU_LOG_DRV("HID Set Report: id = %u, type = %u, len = %u\r\n", report_id, report_type, len);
 
   tusb_control_request_t const request =
   {
@@ -298,7 +302,7 @@ bool tuh_hid_set_report(uint8_t daddr, uint8_t idx, uint8_t report_id, uint8_t r
 static bool _hidh_set_idle(uint8_t daddr, uint8_t itf_num, uint16_t idle_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   // SET IDLE request, device can stall if not support this request
-  TU_LOG2("HID Set Idle \r\n");
+  TU_LOG_DRV("HID Set Idle \r\n");
 
   tusb_control_request_t const request =
   {
@@ -367,7 +371,7 @@ bool tuh_hid_send_ready(uint8_t dev_addr, uint8_t idx)
 
 bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const void* report, uint16_t len)
 {
-  TU_LOG2("HID Send Report %d\r\n", report_id);
+  TU_LOG_DRV("HID Send Report %d\r\n", report_id);
 
   hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
   TU_VERIFY(p_hid);
@@ -430,7 +434,7 @@ bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t
 
   if ( dir == TUSB_DIR_IN )
   {
-    TU_LOG2("  Get Report callback (%u, %u)\r\n", daddr, idx);
+    TU_LOG_DRV("  Get Report callback (%u, %u)\r\n", daddr, idx);
     TU_LOG3_MEM(p_hid->epin_buf, xferred_bytes, 2);
     tuh_hid_report_received_cb(daddr, idx, p_hid->epin_buf, (uint16_t) xferred_bytes);
   }else
@@ -448,8 +452,9 @@ void hidh_close(uint8_t daddr)
     hidh_interface_t* p_hid = &_hidh_itf[i];
     if (p_hid->daddr == daddr)
     {
-       if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i);
-       p_hid->daddr = 0;
+      TU_LOG_DRV("  HIDh close addr = %u index = %u\r\n", daddr, i);
+      if(tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i);
+      p_hid->daddr = 0;
     }
   }
 }
@@ -465,7 +470,7 @@ bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *desc_
 
   TU_VERIFY(TUSB_CLASS_HID == desc_itf->bInterfaceClass);
 
-  TU_LOG2("[%u] HID opening Interface %u\r\n", daddr, desc_itf->bInterfaceNumber);
+  TU_LOG_DRV("[%u] HID opening Interface %u\r\n", daddr, desc_itf->bInterfaceNumber);
 
   // len = interface + hid + n*endpoints
   uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) +
@@ -592,7 +597,7 @@ static void process_set_config(tuh_xfer_t* xfer)
       // using usbh enumeration buffer since report descriptor can be very long
       if( p_hid->report_desc_len > CFG_TUH_ENUMERATION_BUFSIZE )
       {
-        TU_LOG2("HID Skip Report Descriptor since it is too large %u bytes\r\n", p_hid->report_desc_len);
+        TU_LOG_DRV("HID Skip Report Descriptor since it is too large %u bytes\r\n", p_hid->report_desc_len);
 
         // Driver is mounted without report descriptor
         config_driver_mount_complete(daddr, idx, NULL, 0);
@@ -763,7 +768,7 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr,
   for ( uint8_t i = 0; i < report_num; i++ )
   {
     info = report_info_arr+i;
-    TU_LOG2("%u: id = %u, usage_page = %u, usage = %u\r\n", i, info->report_id, info->usage_page, info->usage);
+    TU_LOG_DRV("%u: id = %u, usage_page = %u, usage = %u\r\n", i, info->report_id, info->usage_page, info->usage);
   }
 
   return report_num;
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 1b48813ec..138443de4 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -35,7 +35,6 @@
 
 // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
 #define MSCH_DEBUG   2
-
 #define TU_LOG_MSCH(...)   TU_LOG(MSCH_DEBUG, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
@@ -82,6 +81,7 @@ CFG_TUH_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
 CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN
 static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)];
 
+// FIXME potential nul reference
 TU_ATTR_ALWAYS_INLINE
 static inline msch_interface_t* get_itf(uint8_t dev_addr)
 {
@@ -305,11 +305,15 @@ void msch_init(void)
 void msch_close(uint8_t dev_addr)
 {
   TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
-
   msch_interface_t* p_msc = get_itf(dev_addr);
+  TU_VERIFY(p_msc->configured, );
+
+  TU_LOG_MSCH("  MSCh close addr = %d\r\n", dev_addr);
 
   // invoke Application Callback
-  if (p_msc->mounted && tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr);
+  if (p_msc->mounted) {
+    if(tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr);
+  }
 
   tu_memclr(p_msc, sizeof(msch_interface_t));
 }
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 82f682043..36507041f 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -46,6 +46,7 @@
 #if CFG_TUSB_DEBUG >= 2
 extern char const* const tu_str_speed[];
 extern char const* const tu_str_std_request[];
+extern char const* const tu_str_xfer_result[];
 #endif
 
 void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index ea8eef285..2afe967b5 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -32,7 +32,10 @@
 #include "tusb.h"
 #include "device/usbd_pvt.h"
 
-#if CFG_TUSB_DEBUG >= 2
+// Debug level of USBD Control
+#define USBD_CONTROL_DEBUG   2
+
+#if CFG_TUSB_DEBUG >= USBD_CONTROL_DEBUG
 extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
 #endif
 
@@ -188,7 +191,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
   {
     TU_VERIFY(_ctrl_xfer.buffer);
     memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes);
-    TU_LOG_MEM(2, _usbd_ctrl_buf, xferred_bytes, 2);
+    TU_LOG_MEM(USBD_CONTROL_DEBUG, _usbd_ctrl_buf, xferred_bytes, 2);
   }
 
   _ctrl_xfer.total_xferred += (uint16_t) xferred_bytes;
@@ -205,7 +208,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
     // callback can still stall control in status phase e.g out data does not make sense
     if ( _ctrl_xfer.complete_cb )
     {
-      #if CFG_TUSB_DEBUG >= 2
+      #if CFG_TUSB_DEBUG >= USBD_CONTROL_DEBUG
       usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb);
       #endif
 
diff --git a/src/host/hub.c b/src/host/hub.c
index 386ad6aae..85bf22b3e 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -33,6 +33,10 @@
 #include "usbh_classdriver.h"
 #include "hub.h"
 
+// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
+#define HUB_DEBUG   2
+#define TU_LOG_DRV(...)   TU_LOG(HUB_DEBUG, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -218,7 +222,10 @@ void hub_close(uint8_t dev_addr)
   TU_VERIFY(dev_addr > CFG_TUH_DEVICE_MAX, );
   hub_interface_t* p_hub = get_itf(dev_addr);
 
-  if (p_hub->ep_in) tu_memclr(p_hub, sizeof( hub_interface_t));
+  if (p_hub->ep_in) {
+    TU_LOG_DRV("  HUB close addr = %d\r\n", dev_addr);
+    tu_memclr(p_hub, sizeof( hub_interface_t));
+  }
 }
 
 bool hub_edpt_status_xfer(uint8_t dev_addr)
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 24ce47a7f..4cfc7c5c2 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -61,6 +61,8 @@ typedef struct
   uint8_t hub_addr;
   uint8_t hub_port;
   uint8_t speed;
+
+  // enumeration is in progress, done when all interfaces are configured
   volatile uint8_t enumerating;
 
 //  struct TU_ATTR_PACKED {
@@ -436,7 +438,8 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
         uint8_t const epnum   = tu_edpt_number(ep_addr);
         uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
-        TU_LOG_USBH("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
+        TU_LOG_USBH("on EP %02X with %u bytes %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len,
+                    tu_str_xfer_result[event.xfer_complete.result]);
 
         if (event.dev_addr == 0)
         {
@@ -866,6 +869,10 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
 {
   switch (event->event_id)
   {
+//    case HCD_EVENT_DEVICE_REMOVE:
+//
+//      break;
+
     default:
       osal_queue_send(_usbh_q, event, in_isr);
     break;
@@ -1128,30 +1135,28 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
     usbh_device_t* dev = &_usbh_devices[dev_id];
     uint8_t const dev_addr = dev_id+1;
 
-    // TODO Hub multiple level
     if (dev->rhport == rhport   &&
         (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr = 0 means roothub
         (hub_port == 0 || dev->hub_port == hub_port) && // hub_port = 0 means all devices of downstream hub
         dev->connected)
     {
-      TU_LOG_USBH("  Address = %u\r\n", dev_addr);
+      TU_LOG_USBH("Device unplugged address = %u\r\n", dev_addr);
 
       if (is_hub_addr(dev_addr))
       {
-        TU_LOG(USBH_DEBUG, "HUB address = %u is unmounted\r\n", dev_addr);
+        TU_LOG(USBH_DEBUG, "  is a HUB device\r\n", dev_addr);
         // If the device itself is a usb hub, unplug downstream devices.
         // FIXME un-roll recursive calls to prevent potential stack overflow
         process_device_unplugged(rhport, dev_addr, 0);
       }else
       {
-        // Invoke callback before closing driver
+        // Invoke callback before closing driver (maybe call it later ?)
         if (tuh_umount_cb) tuh_umount_cb(dev_addr);
       }
 
       // Close class driver
       for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
       {
-        TU_LOG_USBH("%s close\r\n", usbh_class_drivers[drv_id].name);
         usbh_class_drivers[drv_id].close(dev_addr);
       }
 
@@ -1449,6 +1454,7 @@ static uint8_t get_new_address(bool is_hub)
 {
   uint8_t start;
   uint8_t end;
+
   if ( is_hub )
   {
     start = CFG_TUH_DEVICE_MAX;
@@ -1459,7 +1465,7 @@ static uint8_t get_new_address(bool is_hub)
     end   = start + CFG_TUH_DEVICE_MAX;
   }
 
-  for ( uint8_t idx = start; idx < end; idx++)
+  for (uint8_t idx = start; idx < end; idx++)
   {
     if (!_usbh_devices[idx].connected) return (idx+1);
   }
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 494e2e50f..69e59ce65 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -142,8 +142,11 @@ static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
 // determine if a queue head has bus-related error
 static inline bool qhd_has_xact_error (ehci_qhd_t * p_qhd)
 {
-  return (p_qhd->qtd_overlay.buffer_err || p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err);
-  //p_qhd->qtd_overlay.non_hs_period_missed_uframe || p_qhd->qtd_overlay.pingstate_err TODO split transaction error
+  volatile ehci_qtd_t *qtd_overlay = &p_qhd->qtd_overlay;
+
+  // Error count = 0 often occurs when device disconnected
+  return (qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err || qtd_overlay->xact_err);
+  //qtd_overlay->non_hs_period_missed_uframe || qtd_overlay->pingstate_err TODO split transaction error
 }
 
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
@@ -630,7 +633,9 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
 
     p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
 
-//    if ( XFER_RESULT_FAILED == error_event )    TU_BREAKPOINT(); // TODO skip unplugged device
+//    if ( XFER_RESULT_FAILED == error_event ) {
+//      TU_BREAKPOINT(); // TODO skip unplugged device
+//    }
 
     p_qhd->p_qtd_list_head->used = 0; // free QTD
     qtd_remove_1st_from_qhd(p_qhd);
diff --git a/src/tusb.c b/src/tusb.c
index 85fe5a3cc..7327db685 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -439,6 +439,10 @@ char const* const tu_str_std_request[] =
   "Synch Frame"
 };
 
+char const* const tu_str_xfer_result[] = {
+    "OK", "Failed", "Stalled", "Timeout"
+};
+
 #endif
 
 static void dump_str_line(uint8_t const* buf, uint16_t count)

From 1c4f22a54cf60e6221995f9b64e2e765fd0a5bfe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 11 May 2023 22:18:40 +0700
Subject: [PATCH 1720/2085] EHCI: fix xfer failed with disconnected device as
 stalled

- change CFG_TUH_ENDPOINT_MAX to 16 (max endpoint pair per device) if
not defined
- change QHD_MAX for EHCI, should be user configurable and more
optimized in the future
---
 examples/host/cdc_msc_hid/src/hid_app.c |  2 +-
 hw/bsp/imxrt/family.c                   |  5 ++-
 src/class/hid/hid_host.c                |  2 +-
 src/host/hcd.h                          |  4 ++-
 src/portable/ehci/ehci.c                | 48 ++++++++++---------------
 5 files changed, 27 insertions(+), 34 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index ed53c502d..87e110ab2 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -263,7 +263,7 @@ static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t c
 
   if (!rpt_info)
   {
-    printf("Couldn't find the report info for this report !\r\n");
+    printf("Couldn't find report info !\r\n");
     return;
   }
 
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 52d3bb91b..46adabf0a 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -131,7 +131,10 @@ void board_init(void)
     freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
   }
 
-  LPUART_Init(UART_PORT, &uart_config, freq);
+  if ( kStatus_Success != LPUART_Init(UART_PORT, &uart_config, freq) ) {
+    // failed to init uart, probably baudrate is not supported
+    // TU_BREAKPOINT();
+  }
 
   //------------- USB -------------//
   // Note: RT105x RT106x and later have dual USB controllers.
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 3a491937a..6abe298e5 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -72,7 +72,7 @@ tu_static hidh_interface_t _hidh_itf[CFG_TUH_HID];
 TU_ATTR_ALWAYS_INLINE static inline
 hidh_interface_t* get_hid_itf(uint8_t daddr, uint8_t idx)
 {
-  TU_ASSERT(daddr && idx < CFG_TUH_HID, NULL);
+  TU_ASSERT(daddr > 0 && idx < CFG_TUH_HID, NULL);
   hidh_interface_t* p_hid = &_hidh_itf[idx];
   return (p_hid->daddr == daddr) ? p_hid : NULL;
 }
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 623c12a12..f4e76f9ef 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -39,8 +39,10 @@
 // Configuration
 //--------------------------------------------------------------------+
 
+// Max number of endpoints per device
+// TODO optimize memory usage
 #ifndef CFG_TUH_ENDPOINT_MAX
-  #define CFG_TUH_ENDPOINT_MAX   (CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3)
+  #define CFG_TUH_ENDPOINT_MAX   16
 //  #ifdef TUP_HCD_ENDPOINT_MAX
 //    #define CFG_TUH_ENDPPOINT_MAX   TUP_HCD_ENDPOINT_MAX
 //  #else
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 69e59ce65..080ee9bbc 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -58,7 +58,8 @@
 
 #define FRAMELIST_SIZE                  (1024 >> FRAMELIST_SIZE_BIT_VALUE)
 
-#define QHD_MAX      (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX)
+// Total queue head pool. TODO should be user configurable and more optimize memory usage in the future
+#define QHD_MAX      (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB)
 #define QTD_MAX      QHD_MAX
 
 typedef struct
@@ -138,17 +139,6 @@ static inline ehci_qtd_t* qtd_control(uint8_t dev_addr)
 static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd);
 static inline ehci_qhd_t* qhd_find_free (void);
 static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
-
-// determine if a queue head has bus-related error
-static inline bool qhd_has_xact_error (ehci_qhd_t * p_qhd)
-{
-  volatile ehci_qtd_t *qtd_overlay = &p_qhd->qtd_overlay;
-
-  // Error count = 0 often occurs when device disconnected
-  return (qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err || qtd_overlay->xact_err);
-  //qtd_overlay->non_hs_period_missed_uframe || qtd_overlay->pingstate_err TODO split transaction error
-}
-
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
 
 static inline ehci_qtd_t* qtd_find_free (void);
@@ -392,15 +382,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
 
   //------------- Prepare Queue Head -------------//
-  ehci_qhd_t * p_qhd;
-
-  if ( ep_desc->bEndpointAddress == 0 )
-  {
-    p_qhd = qhd_control(dev_addr);
-  }else
-  {
-    p_qhd = qhd_find_free();
-  }
+  ehci_qhd_t *p_qhd = (ep_desc->bEndpointAddress == 0) ? qhd_control(dev_addr) : qhd_find_free();
   TU_ASSERT(p_qhd);
 
   qhd_init(p_qhd, dev_addr, ep_desc);
@@ -622,18 +604,23 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms)
 
 static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
 {
-  if ( (p_qhd->dev_addr != 0 && p_qhd->qtd_overlay.halted) || // addr0 cannot be protocol STALL
-        qhd_has_xact_error(p_qhd) )
-  {
-    // current qhd has error in transaction
-    xfer_result_t error_event;
+  volatile ehci_qtd_t *qtd_overlay = &p_qhd->qtd_overlay;
 
-    // no error bits are set, endpoint is halted due to STALL
-    error_event = qhd_has_xact_error(p_qhd) ? XFER_RESULT_FAILED : XFER_RESULT_STALLED;
+  // TD has error
+  if (qtd_overlay->halted) {
+    xfer_result_t xfer_result;
+
+    if (qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err || qtd_overlay->xact_err) {
+      // Error count = 0 often occurs when device disconnected, or other bus-related error
+      xfer_result = XFER_RESULT_FAILED;
+    }else {
+      // no error bits are set, endpoint is halted due to STALL
+      xfer_result = XFER_RESULT_STALLED;
+    }
 
     p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
 
-//    if ( XFER_RESULT_FAILED == error_event ) {
+//    if (XFER_RESULT_FAILED == xfer_result ) {
 //      TU_BREAKPOINT(); // TODO skip unplugged device
 //    }
 
@@ -655,7 +642,8 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
     }
 
     // call USBH callback
-    hcd_event_xfer_complete(p_qhd->dev_addr, tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0), p_qhd->total_xferred_bytes, error_event, true);
+    uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0);
+    hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, p_qhd->total_xferred_bytes, xfer_result, true);
 
     p_qhd->total_xferred_bytes = 0;
   }

From 2c48050993777c586210af503504e612f31228d8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 11 May 2023 22:21:18 +0700
Subject: [PATCH 1721/2085] add various check for disconncted device, also fix
 #1511 un-roll recursive hub removal with usbh queue

---
 src/host/usbh.c | 124 ++++++++++++++++++++++++++++++++----------------
 1 file changed, 82 insertions(+), 42 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 4cfc7c5c2..c56ff9459 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -81,10 +81,12 @@ typedef struct {
 
   // Device State
   struct TU_ATTR_PACKED {
-    volatile uint8_t connected  : 1;
-    volatile uint8_t addressed  : 1;
-    volatile uint8_t configured : 1;
-    volatile uint8_t suspended  : 1;
+    volatile uint8_t connected  : 1; // After 1st transfer
+    volatile uint8_t addressed  : 1; // After SET_ADDR
+    volatile uint8_t configured : 1; // After SET_CONFIG and all drivers are configured
+    volatile uint8_t suspended  : 1; // Bus suspended
+
+    // volatile uint8_t removing : 1; // Physically disconnected, waiting to be processed by usbh
   };
 
   // Device Descriptor
@@ -248,7 +250,7 @@ static inline usbh_device_t* get_device(uint8_t dev_addr)
 }
 
 static bool enum_new_device(hcd_event_t* event);
-static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port);
+static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port);
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
 static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
@@ -420,7 +422,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
 
       case HCD_EVENT_DEVICE_REMOVE:
         TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port);
-        process_device_unplugged(event.rhport, event.connection.hub_addr, event.connection.hub_port);
+        process_removing_device(event.rhport, event.connection.hub_addr, event.connection.hub_port);
 
         #if CFG_TUH_HUB
         // TODO remove
@@ -450,7 +452,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
         else
         {
           usbh_device_t* dev = get_device(event.dev_addr);
-          TU_ASSERT(dev, );
+          TU_VERIFY(dev && dev->connected, );
 
           dev->ep_status[epnum][ep_dir].busy    = 0;
           dev->ep_status[epnum][ep_dir].claimed = 0;
@@ -739,29 +741,33 @@ void usbh_int_set(bool enabled)
 // TODO has some duplication code with device, refactor later
 bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
 {
+  // Note: addr0 only use tuh_control_xfer
   usbh_device_t* dev = get_device(dev_addr);
-
-  // addr0 only use tuh_control_xfer
-  TU_ASSERT(dev);
+  TU_ASSERT(dev && dev->connected);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  return tu_edpt_claim(&dev->ep_status[epnum][dir], _usbh_mutex);
+  TU_VERIFY(tu_edpt_claim(&dev->ep_status[epnum][dir], _usbh_mutex));
+  TU_LOG_USBH("[%u] Claimed EP 0x%02x\r\n", dev_addr, ep_addr);
+
+  return true;
 }
 
 // TODO has some duplication code with device, refactor later
 bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
 {
+  // Note: addr0 only use tuh_control_xfer
   usbh_device_t* dev = get_device(dev_addr);
-
-  // addr0 only use tuh_control_xfer
-  TU_ASSERT(dev);
+  TU_VERIFY(dev && dev->connected);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  return tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex);
+  TU_VERIFY(tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex));
+  TU_LOG_USBH("[%u] Released EP 0x%02x\r\n", dev_addr, ep_addr);
+
+  return true;
 }
 
 // TODO has some duplication code with device, refactor later
@@ -870,7 +876,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
   switch (event->event_id)
   {
 //    case HCD_EVENT_DEVICE_REMOVE:
-//
+//      // mark device as removing to prevent further xfer before the event is processed in usbh task
 //      break;
 
     default:
@@ -1116,7 +1122,7 @@ uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_i
 }
 
 //--------------------------------------------------------------------+
-//
+// Detaching
 //--------------------------------------------------------------------+
 
 TU_ATTR_ALWAYS_INLINE
@@ -1125,45 +1131,79 @@ static inline bool is_hub_addr(uint8_t daddr)
   return (CFG_TUH_HUB > 0) && (daddr > CFG_TUH_DEVICE_MAX);
 }
 
+//static void mark_removing_device_isr(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) {
+//  for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) {
+//    usbh_device_t *dev = &_usbh_devices[dev_id];
+//    uint8_t const daddr = dev_id + 1;
+//
+//    // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub
+//    if (dev->rhport == rhport && dev->connected &&
+//        (hub_addr == 0 || dev->hub_addr == hub_addr) &&
+//        (hub_port == 0 || dev->hub_port == hub_port)) {
+//      if (is_hub_addr(daddr)) {
+//        // If the device itself is a usb hub, mark all downstream devices.
+//        // FIXME recursive calls
+//        mark_removing_device_isr(rhport, daddr, 0);
+//      }
+//
+//      dev->removing = 1;
+//    }
+//  }
+//}
+
 // a device unplugged from rhport:hub_addr:hub_port
-static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
+static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
 {
   //------------- find the all devices (star-network) under port that is unplugged -------------//
   // TODO mark as disconnected in ISR, also handle dev0
-  for ( uint8_t dev_id = 0; dev_id < TU_ARRAY_SIZE(_usbh_devices); dev_id++ )
-  {
-    usbh_device_t* dev = &_usbh_devices[dev_id];
-    uint8_t const dev_addr = dev_id+1;
 
-    if (dev->rhport == rhport   &&
-        (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr = 0 means roothub
-        (hub_port == 0 || dev->hub_port == hub_port) && // hub_port = 0 means all devices of downstream hub
-        dev->connected)
-    {
-      TU_LOG_USBH("Device unplugged address = %u\r\n", dev_addr);
+#if 0
+  // index as hub addr, value is hub port (0xFF for invalid)
+  uint8_t removing_hubs[CFG_TUH_HUB];
+  memset(removing_hubs, TUSB_INDEX_INVALID_8, sizeof(removing_hubs));
 
-      if (is_hub_addr(dev_addr))
-      {
-        TU_LOG(USBH_DEBUG, "  is a HUB device\r\n", dev_addr);
-        // If the device itself is a usb hub, unplug downstream devices.
-        // FIXME un-roll recursive calls to prevent potential stack overflow
-        process_device_unplugged(rhport, dev_addr, 0);
-      }else
-      {
+  removing_hubs[hub_addr-CFG_TUH_DEVICE_MAX] = hub_port;
+
+  // consecutive non-removing hub
+  uint8_t nop_count = 0;
+#endif
+
+  for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) {
+    usbh_device_t *dev = &_usbh_devices[dev_id];
+    uint8_t const daddr = dev_id + 1;
+
+    // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub
+    if (dev->rhport == rhport && dev->connected &&
+        (hub_addr == 0 || dev->hub_addr == hub_addr) &&
+        (hub_port == 0 || dev->hub_port == hub_port)) {
+      TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
+
+      if (is_hub_addr(daddr)) {
+        TU_LOG(USBH_DEBUG, "  is a HUB device\r\n", daddr);
+
+        // Submit removed event If the device itself is a hub (un-rolled recursive)
+        // TODO a better to unroll recursrive is using array of removing_hubs and mark it here
+        hcd_event_t event;
+        event.rhport = rhport;
+        event.event_id = HCD_EVENT_DEVICE_REMOVE;
+        event.connection.hub_addr = daddr;
+        event.connection.hub_port = 0;
+
+        hcd_event_handler(&event, false);
+      } else {
         // Invoke callback before closing driver (maybe call it later ?)
-        if (tuh_umount_cb) tuh_umount_cb(dev_addr);
+        if (tuh_umount_cb) tuh_umount_cb(daddr);
       }
 
       // Close class driver
-      for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
-      {
-        usbh_class_drivers[drv_id].close(dev_addr);
+      for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) {
+        usbh_class_drivers[drv_id].close(daddr);
       }
 
-      hcd_device_close(rhport, dev_addr);
+      hcd_device_close(rhport, daddr);
       clear_device(dev);
       // abort on-going control xfer if any
-      if (_ctrl_xfer.daddr == dev_addr) _set_control_xfer_stage(CONTROL_STAGE_IDLE);
+      if (_ctrl_xfer.daddr == daddr) _set_control_xfer_stage(CONTROL_STAGE_IDLE);
     }
   }
 }

From 1e998ce3bd1ecdf535a8a9feb6823627f3cf7c14 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 12 May 2023 10:58:42 +0700
Subject: [PATCH 1722/2085] usbd: fix control transfer issue for chipidea hs
 when previous status and new setup complete in the same isr frame

change usbd edpt busy/stalled/claimed value to 0/1 instead of
(true/false) since they are 1-bit field.
---
 .idea/runConfigurations/rt1010.xml         | 10 ------
 .idea/runConfigurations/rt1010_nxplink.xml | 10 ++++++
 src/device/usbd.c                          | 39 +++++++++++-----------
 src/portable/chipidea/ci_hs/dcd_ci_hs.c    | 18 +++++-----
 4 files changed, 39 insertions(+), 38 deletions(-)
 delete mode 100644 .idea/runConfigurations/rt1010.xml
 create mode 100644 .idea/runConfigurations/rt1010_nxplink.xml

diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml
deleted file mode 100644
index 700cb5732..000000000
--- a/.idea/runConfigurations/rt1010.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver -p 55503 -t mimxrt1010" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
-    <custom-gdb-server version="1" gdb-connect="tcp::55503" executable="$USER_HOME$/.local/bin/pyocd" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
-      <debugger kind="GDB" isBundled="true" />
-    </custom-gdb-server>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010_nxplink.xml b/.idea/runConfigurations/rt1010_nxplink.xml
new file mode 100644
index 000000000..cf3bf842f
--- /dev/null
+++ b/.idea/runConfigurations/rt1010_nxplink.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt1010 nxplink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver --gdb-port 55503 --semihost-port -1 MIMXRT1011xxxxx:EVK-MIMXRT1010" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="host_hid_to_device_cdc" TARGET_NAME="host_hid_to_device_cdc" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="host_hid_to_device_cdc" RUN_TARGET_NAME="host_hid_to_device_cdc">
+    <custom-gdb-server version="1" gdb-connect="tcp::55503" executable="/usr/local/LinkServer/LinkServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/src/device/usbd.c b/src/device/usbd.c
index cee56af60..409a5ec10 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -516,9 +516,9 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         _usbd_dev.connected = 1;
 
         // mark both in & out control as free
-        _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = false;
+        _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = 0;
         _usbd_dev.ep_status[0][TUSB_DIR_OUT].claimed = 0;
-        _usbd_dev.ep_status[0][TUSB_DIR_IN ].busy = false;
+        _usbd_dev.ep_status[0][TUSB_DIR_IN ].busy = 0;
         _usbd_dev.ep_status[0][TUSB_DIR_IN ].claimed = 0;
 
         // Process control request
@@ -540,12 +540,13 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
 
         TU_LOG(USBD_DBG, "on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
 
-        _usbd_dev.ep_status[epnum][ep_dir].busy = false;
+        _usbd_dev.ep_status[epnum][ep_dir].busy = 0;
         _usbd_dev.ep_status[epnum][ep_dir].claimed = 0;
 
         if ( 0 == epnum )
         {
-          usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len);
+          usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete
+          .len);
         }
         else
         {
@@ -553,7 +554,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
           TU_ASSERT(driver, );
 
           TU_LOG(USBD_DBG, "  %s xfer callback\r\n", driver->name);
-          driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len);
+          driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
         }
       }
       break;
@@ -1244,7 +1245,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
 
   // Set busy first since the actual transfer can be complete before dcd_edpt_xfer()
   // could return and USBD task can preempt and clear the busy
-  _usbd_dev.ep_status[epnum][dir].busy = true;
+  _usbd_dev.ep_status[epnum][dir].busy = 1;
 
   if ( dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes) )
   {
@@ -1252,7 +1253,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   }else
   {
     // DCD error, mark endpoint as ready to allow next transfer
-    _usbd_dev.ep_status[epnum][dir].busy = false;
+    _usbd_dev.ep_status[epnum][dir].busy = 0;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
     TU_LOG(USBD_DBG, "FAILED\r\n");
     TU_BREAKPOINT();
@@ -1278,7 +1279,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 
   // Set busy first since the actual transfer can be complete before dcd_edpt_xfer() could return
   // and usbd task can preempt and clear the busy
-  _usbd_dev.ep_status[epnum][dir].busy = true;
+  _usbd_dev.ep_status[epnum][dir].busy = 1;
 
   if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes))
   {
@@ -1287,7 +1288,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   }else
   {
     // DCD error, mark endpoint as ready to allow next transfer
-    _usbd_dev.ep_status[epnum][dir].busy = false;
+    _usbd_dev.ep_status[epnum][dir].busy = 0;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
     TU_LOG(USBD_DBG, "failed\r\n");
     TU_BREAKPOINT();
@@ -1317,8 +1318,8 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   {
     TU_LOG(USBD_DBG, "    Stall EP %02X\r\n", ep_addr);
     dcd_edpt_stall(rhport, ep_addr);
-    _usbd_dev.ep_status[epnum][dir].stalled = true;
-    _usbd_dev.ep_status[epnum][dir].busy = true;
+    _usbd_dev.ep_status[epnum][dir].stalled = 1;
+    _usbd_dev.ep_status[epnum][dir].busy = 1;
   }
 }
 
@@ -1334,8 +1335,8 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   {
     TU_LOG(USBD_DBG, "    Clear Stall EP %02X\r\n", ep_addr);
     dcd_edpt_clear_stall(rhport, ep_addr);
-    _usbd_dev.ep_status[epnum][dir].stalled = false;
-    _usbd_dev.ep_status[epnum][dir].busy = false;
+    _usbd_dev.ep_status[epnum][dir].stalled = 0;
+    _usbd_dev.ep_status[epnum][dir].busy = 0;
   }
 }
 
@@ -1366,9 +1367,9 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   dcd_edpt_close(rhport, ep_addr);
-  _usbd_dev.ep_status[epnum][dir].stalled = false;
-  _usbd_dev.ep_status[epnum][dir].busy = false;
-  _usbd_dev.ep_status[epnum][dir].claimed = false;
+  _usbd_dev.ep_status[epnum][dir].stalled = 0;
+  _usbd_dev.ep_status[epnum][dir].busy = 0;
+  _usbd_dev.ep_status[epnum][dir].claimed = 0;
 
   return;
 }
@@ -1403,9 +1404,9 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep
   TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX);
   TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
 
-  _usbd_dev.ep_status[epnum][dir].stalled = false;
-  _usbd_dev.ep_status[epnum][dir].busy = false;
-  _usbd_dev.ep_status[epnum][dir].claimed = false;
+  _usbd_dev.ep_status[epnum][dir].stalled = 0;
+  _usbd_dev.ep_status[epnum][dir].busy = 0;
+  _usbd_dev.ep_status[epnum][dir].claimed = 0;
   return dcd_edpt_iso_activate(rhport, desc_ep);
 }
 
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index bc6736cf2..9be79a2f1 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -616,15 +616,6 @@ void dcd_int_handler(uint8_t rhport)
     uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
     dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
 
-    if (dcd_reg->ENDPTSETUPSTAT)
-    {
-      //------------- Set up Received -------------//
-      // 23.10.10.2 Operational model for setup transfers
-      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
-
-      dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
-    }
-
     // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
     // nothing to do, we will submit xfer as error to usbd
     // if (int_status & INTR_ERROR) { }
@@ -637,6 +628,15 @@ void dcd_int_handler(uint8_t rhport)
         if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN);
       }
     }
+
+    // Set up Received
+    // 23.10.10.2 Operational model for setup transfers
+    // Must be after normal transfer complete since it is possible to have both previous control status + new setup
+    // in the same frame and we should handle previous status first.
+    if (dcd_reg->ENDPTSETUPSTAT) {
+      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
+      dcd_event_setup_received(rhport, (uint8_t *) (uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
+    }
   }
 
   if (int_status & INTR_SOF)

From a9aa0e3a1a9323df16c91d7705aad480033f962a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 13 May 2023 13:20:09 +0700
Subject: [PATCH 1723/2085] fix error on EHCI causes xfer error in non-queued
 qhd which cause memory fault

---
 .idea/cmake.xml                               |  2 +
 .../host_hid_to_device_cdc/src/tusb_config.h  |  6 +--
 src/portable/ehci/ehci.c                      | 44 ++++++++++++++-----
 src/portable/ehci/ehci.h                      |  2 +-
 4 files changed, 36 insertions(+), 18 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index bbef86164..7dacd0003 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,6 +2,7 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
+      <configuration PROFILE_NAME="rt1060 evk" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1060_evk" />
       <configuration PROFILE_NAME="pca10095" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095" BUILD_OPTIONS="-v" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" BUILD_OPTIONS="-v" />
       <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc55 -DBOARD=lpcxpresso55s69" />
@@ -27,6 +28,7 @@
       </configuration>
       <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=rp2040 -DBOARD=raspberry_pi_pico" />
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1010_evk" />
+      <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1064_evk" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
index 2185cd1f1..8133ed418 100644
--- a/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
+++ b/examples/dual/host_hid_to_device_cdc/src/tusb_config.h
@@ -84,10 +84,6 @@
 #define CFG_TUH_RPI_PIO_USB   1
 #endif
 
-
-// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
-// #define CFG_TUSB_DEBUG           0
-
 /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
  * Tinyusb use follows macros to declare transferring memory so that they can be put
  * into those specific section.
@@ -133,7 +129,7 @@
 #endif
 
 #ifndef CFG_TUH_MEM_ALIGN
-#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
+#define CFG_TUH_MEM_ALIGN           __attribute__ ((aligned(4)))
 #endif
 
 #define CFG_TUH_HUB                 1
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 080ee9bbc..8203b0f06 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -93,16 +93,30 @@ CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
 // Debug
 //--------------------------------------------------------------------+
 #if CFG_TUSB_DEBUG >= EHCI_DBG
-static inline void print_portsc(ehci_registers_t* regs)
-{
+static inline void print_portsc(ehci_registers_t* regs) {
   TU_LOG_HEX(EHCI_DBG, regs->portsc);
-  TU_LOG(EHCI_DBG, "  Current Connect Status: %u\r\n", regs->portsc_bm.current_connect_status);
-  TU_LOG(EHCI_DBG, "  Connect Status Change : %u\r\n", regs->portsc_bm.connect_status_change);
-  TU_LOG(EHCI_DBG, "  Port Enabled          : %u\r\n", regs->portsc_bm.port_enabled);
-  TU_LOG(EHCI_DBG, "  Port Enabled Change   : %u\r\n", regs->portsc_bm.port_enable_change);
+  TU_LOG(EHCI_DBG, "  Connect Status : %u\r\n", regs->portsc_bm.current_connect_status);
+  TU_LOG(EHCI_DBG, "  Connect Change : %u\r\n", regs->portsc_bm.connect_status_change);
+  TU_LOG(EHCI_DBG, "  Enabled        : %u\r\n", regs->portsc_bm.port_enabled);
+  TU_LOG(EHCI_DBG, "  Enabled Change : %u\r\n", regs->portsc_bm.port_enable_change);
 
-  TU_LOG(EHCI_DBG, "  Port Reset            : %u\r\n", regs->portsc_bm.port_reset);
-  TU_LOG(EHCI_DBG, "  Port Power            : %u\r\n", regs->portsc_bm.port_power);
+  TU_LOG(EHCI_DBG, "  OverCurr Change: %u\r\n", regs->portsc_bm.over_current_change);
+  TU_LOG(EHCI_DBG, "  Force Resume   : %u\r\n", regs->portsc_bm.force_port_resume);
+  TU_LOG(EHCI_DBG, "  Suspend        : %u\r\n", regs->portsc_bm.suspend);
+  TU_LOG(EHCI_DBG, "  Reset          : %u\r\n", regs->portsc_bm.port_reset);
+  TU_LOG(EHCI_DBG, "  Power          : %u\r\n", regs->portsc_bm.port_power);
+}
+
+static inline void print_intr(uint32_t intr) {
+  TU_LOG_HEX(EHCI_DBG, intr);
+  TU_LOG(EHCI_DBG, "  USB Interrupt      : %u\r\n", (intr & EHCI_INT_MASK_USB) ? 1 : 0);
+  TU_LOG(EHCI_DBG, "  USB Error          : %u\r\n", (intr & EHCI_INT_MASK_ERROR) ? 1 : 0);
+  TU_LOG(EHCI_DBG, "  Port Change Detect : %u\r\n", (intr & EHCI_INT_MASK_PORT_CHANGE) ? 1 : 0);
+  TU_LOG(EHCI_DBG, "  Frame List Rollover: %u\r\n", (intr & EHCI_INT_MASK_FRAMELIST_ROLLOVER) ? 1 : 0);
+  TU_LOG(EHCI_DBG, "  Host System Error  : %u\r\n", (intr & EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR) ? 1 : 0);
+  TU_LOG(EHCI_DBG, "  Async Advance      : %u\r\n", (intr & EHCI_INT_MASK_ASYNC_ADVANCE) ? 1 : 0);
+//  TU_LOG(EHCI_DBG, "  Interrupt on Async: %u\r\n", (intr & EHCI_INT_MASK_NXP_ASYNC));
+//  TU_LOG(EHCI_DBG, "  Periodic Schedule : %u\r\n", (intr & EHCI_INT_MASK_NXP_PERIODIC));
 }
 
 #else
@@ -166,8 +180,8 @@ void hcd_port_reset(uint8_t rhport)
 
   ehci_registers_t* regs = ehci_data.regs;
 
-  // mask out all change bits since they are Write 1 to clear
-  uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL;
+  // mask out Write-1-to-Clear bits
+  uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C;
 
   // EHCI Table 2-16 PortSC
   // when software writes Port Reset bit to a one, it must also write a zero to the Port Enable bit.
@@ -347,7 +361,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   // Power Control (PPC) field in the HCSPARAMS register.
   if (ehci_data.cap_regs->hcsparams_bm.port_power_control) {
     // mask out all change bits since they are Write 1 to clear
-    uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL);
+    uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_W1C);
     portsc |= ECHI_PORTSC_MASK_PORT_POWER;
 
     regs->portsc = portsc;
@@ -621,9 +635,14 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
     p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
 
 //    if (XFER_RESULT_FAILED == xfer_result ) {
+//      TU_LOG1("  QHD xfer err count: %d\n", qtd_overlay->err_count);
 //      TU_BREAKPOINT(); // TODO skip unplugged device
+//      while(1){}
 //    }
 
+    // No TD, probably an signal noise ?
+    TU_VERIFY(p_qhd->p_qtd_list_head, );
+
     p_qhd->p_qtd_list_head->used = 0; // free QTD
     qtd_remove_1st_from_qhd(p_qhd);
 
@@ -710,7 +729,8 @@ void hcd_int_handler(uint8_t rhport)
 
   if (int_status & EHCI_INT_MASK_PORT_CHANGE)
   {
-    uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_CHANGE_ALL;
+    // Including: Force port resume, over-current change, enable/disable change and connect status change.
+    uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_W1C;
     print_portsc(regs);
 
     if (regs->portsc_bm.connect_status_change)
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index dd090cb36..a73e43707 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -306,7 +306,7 @@ enum {
   EHCI_PORTSC_MASK_PORT_RESET             = TU_BIT(8),
   ECHI_PORTSC_MASK_PORT_POWER             = TU_BIT(12),
 
-  EHCI_PORTSC_MASK_CHANGE_ALL =
+  EHCI_PORTSC_MASK_W1C =
     EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |
     EHCI_PORTSC_MASK_PORT_ENABLE_CHANGE |
     EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE

From eb89df411540cb8cf5323991516a45590fa0b81d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 17 May 2023 16:14:35 +0700
Subject: [PATCH 1724/2085] adding hcd_dcache_clean/hcd_dcache_invalidate

---
 hw/bsp/imxrt/family.cmake               | 15 +++++++++++++++
 src/host/hcd.h                          | 10 ++++++++++
 src/portable/chipidea/ci_hs/hcd_ci_hs.c |  9 +++++++++
 src/portable/ehci/ehci.h                |  7 +++++++
 4 files changed, 41 insertions(+)

diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 77ac05c87..4628abc34 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -144,6 +144,21 @@ function(family_configure_target TARGET)
     COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
     )
 
+  # Flash using jlink
+  set(JLINKEXE JLinkExe)
+  file(GENERATE
+    OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
+    CONTENT "halt
+loadfile $<TARGET_FILE:${TARGET}>
+r
+go
+exit"
+    )
+  add_custom_target(${TARGET}-jlink
+    DEPENDS ${TARGET}
+    COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
+    )
+
 endfunction()
 
 
diff --git a/src/host/hcd.h b/src/host/hcd.h
index f4e76f9ef..38c89a1d2 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -104,6 +104,16 @@ typedef struct
   uint8_t speed;
 } hcd_devtree_info_t;
 
+//--------------------------------------------------------------------+
+// Memory API
+//--------------------------------------------------------------------+
+
+// clean/flush data cache: write cache -> memory
+void hcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+
+// invalidate data cache: mark cache as invalid, next read will read from memory
+void hcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index b06633f30..56ca01f85 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -41,6 +41,15 @@
 
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   #include "ci_hs_imxrt.h"
+
+  void hcd_dcache_clean(void* addr, uint32_t data_size) {
+    SCB_CleanDCache_by_Addr((uint32_t*) addr, (int32_t) data_size);
+  }
+
+  void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
+    SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
+  }
+
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"
 #else
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index a73e43707..56befd306 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -268,6 +268,7 @@ TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" );
 // EHCI Operational Register
 //--------------------------------------------------------------------+
 enum {
+  // Bit 0-5 has maskable in interrupt enabled register
   EHCI_INT_MASK_USB                   = TU_BIT(0),
   EHCI_INT_MASK_ERROR                 = TU_BIT(1),
   EHCI_INT_MASK_PORT_CHANGE           = TU_BIT(2),
@@ -276,6 +277,12 @@ enum {
   EHCI_INT_MASK_ASYNC_ADVANCE         = TU_BIT(5),
 
   EHCI_INT_MASK_NXP_SOF               = TU_BIT(7),
+
+  EHCI_INT_MASK_HC_HALTED             = TU_BIT(12),
+  EHCI_INT_MASK_RECLAIMATION          = TU_BIT(13),
+  EHCI_INT_MASK_PERIODIC_SCHED_STATUS = TU_BIT(14),
+  EHCI_INT_MASK_ASYNC_SCHED_STATUS    = TU_BIT(15),
+
   EHCI_INT_MASK_NXP_ASYNC             = TU_BIT(18),
   EHCI_INT_MASK_NXP_PERIODIC          = TU_BIT(19),
 

From 32f9f452afc4d431d51cb16a02f99d76c88f7fb9 Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Wed, 17 May 2023 12:13:25 +0200
Subject: [PATCH 1725/2085] renesas: provide default for CFG_TUSB_RHPORT1_MODE

Should fix CI failure for Renesas RX family
---
 src/portable/renesas/rusb2/dcd_rusb2.c | 1 +
 src/portable/renesas/rusb2/hcd_rusb2.c | 1 +
 src/portable/renesas/rusb2/rusb2_ra.h  | 1 +
 3 files changed, 3 insertions(+)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index f509dcc56..2653d0da6 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -40,6 +40,7 @@
 #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
 // fallback
 #define CFG_TUSB_RHPORT0_MODE   OPT_MODE_DEVICE
+#define CFG_TUSB_RHPORT1_MODE   0
 #endif
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 1ec25f1e2..1e26c931d 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -36,6 +36,7 @@
 #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
 // fallback
 #define CFG_TUSB_RHPORT0_MODE   OPT_MODE_HOST
+#define CFG_TUSB_RHPORT1_MODE   0
 #endif
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 874492304..a1c58abe5 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -40,6 +40,7 @@ extern IRQn_Type _usb_hs_irqn;
 #if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
 // fallback
 #define CFG_TUSB_RHPORT0_MODE   ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST )
+#define CFG_TUSB_RHPORT1_MODE   0
 #endif
 
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)

From a3e017bfd2923dcb1ce86d395606a24e2285e54a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 May 2023 10:04:48 +0700
Subject: [PATCH 1726/2085] EHCI adding dcahe support, passing enumertaion

---
 src/host/hcd.h                          |  10 +-
 src/portable/chipidea/ci_hs/hcd_ci_hs.c |   4 +
 src/portable/ehci/ehci.c                | 167 +++++++++++++++---------
 src/portable/ehci/ehci.h                |   1 +
 4 files changed, 117 insertions(+), 65 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 38c89a1d2..c6fde2adc 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -108,12 +108,18 @@ typedef struct
 // Memory API
 //--------------------------------------------------------------------+
 
-// clean/flush data cache: write cache -> memory
+// clean/flush data cache: write cache -> memory.
+// Required before an DMA TX transfer to make sure data is in memory
 void hcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK;
 
 // invalidate data cache: mark cache as invalid, next read will read from memory
+// Required BOTH before and after an DMA RX transfer
 void hcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
 
+// clean and invalidate data cache
+// Required before an DMA transfer where memory is both read/write by DMA
+void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
@@ -194,6 +200,7 @@ void hcd_event_device_attach(uint8_t rhport, bool in_isr)
   event.event_id            = HCD_EVENT_DEVICE_ATTACH;
   event.connection.hub_addr = 0;
   event.connection.hub_port = 0;
+
   hcd_event_handler(&event, in_isr);
 }
 
@@ -224,7 +231,6 @@ void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred
   event.xfer_complete.result = result;
   event.xfer_complete.len = xferred_bytes;
 
-
   hcd_event_handler(&event, in_isr);
 }
 
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 56ca01f85..ecb1a621c 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -50,6 +50,10 @@
     SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
   }
 
+void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+    SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
+  }
+
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"
 #else
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 8203b0f06..9023e4b35 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -92,7 +92,7 @@ CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4096) static ehci_data_t ehci_data;
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= EHCI_DBG
+#if CFG_TUSB_DEBUG >= (EHCI_DBG + 1)
 static inline void print_portsc(ehci_registers_t* regs) {
   TU_LOG_HEX(EHCI_DBG, regs->portsc);
   TU_LOG(EHCI_DBG, "  Connect Status : %u\r\n", regs->portsc_bm.current_connect_status);
@@ -159,7 +159,7 @@ static inline ehci_qtd_t* qtd_find_free (void);
 static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd);
 static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new);
 static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd);
-static void qtd_init (ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes);
+static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes);
 
 static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
 static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer);
@@ -325,28 +325,27 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   // 3 --> period_head_arr[3] (8ms)
 
   // TODO EHCI_FRAMELIST_SIZE with other size than 8
-  for(uint32_t i=0; i<FRAMELIST_SIZE; i++)
-  {
+  for (uint32_t i = 0; i < FRAMELIST_SIZE; i++) {
     framelist[i].address = (uint32_t) period_1ms;
-    framelist[i].type    = EHCI_QTYPE_QHD;
+    framelist[i].type = EHCI_QTYPE_QHD;
   }
 
-  for(uint32_t i=0; i<FRAMELIST_SIZE; i+=2)
-  {
+  for (uint32_t i = 0; i < FRAMELIST_SIZE; i += 2) {
     list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD);
   }
 
-  for(uint32_t i=1; i<FRAMELIST_SIZE; i+=4)
-  {
+  for (uint32_t i = 1; i < FRAMELIST_SIZE; i += 4) {
     list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD);
   }
-
-  list_insert(framelist+3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD);
-
+  list_insert(framelist + 3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD);
   period_1ms->terminate    = 1;
 
   regs->periodic_list_base = (uint32_t) framelist;
 
+  if(hcd_dcache_clean) {
+    hcd_dcache_clean(&ehci_data, sizeof(ehci_data_t));
+  }
+
   //------------- TT Control (NXP only) -------------//
   regs->nxp_tt_control = 0;
 
@@ -430,6 +429,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   // TODO might need to disable async/period list
   list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD);
 
+  if(hcd_dcache_clean) {
+    hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t));
+    hcd_dcache_clean(list_head, sizeof(ehci_link_t));
+  }
+
   return true;
 }
 
@@ -441,9 +445,12 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   ehci_qtd_t* td  = &ehci_data.control[dev_addr].qtd;
 
   qtd_init(td, setup_packet, 8);
-  td->pid          = EHCI_PID_SETUP;
-  td->int_on_complete = 1;
-  td->next.terminate  = 1;
+  td->pid = EHCI_PID_SETUP;
+
+  if (hcd_dcache_clean && hcd_dcache_clean_invalidate) {
+    hcd_dcache_clean((void *) setup_packet, 8);
+    hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t));
+  }
 
   // sw region
   qhd->p_qtd_list_head = td;
@@ -452,6 +459,10 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   // attach TD
   qhd->qtd_overlay.next.address = (uint32_t) td;
 
+  if (hcd_dcache_clean_invalidate) {
+    hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
+  }
+
   return true;
 }
 
@@ -462,41 +473,48 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
+  ehci_qhd_t* qhd;
+  ehci_qtd_t* qtd;
+
   if ( epnum == 0 )
   {
-    ehci_qhd_t* qhd = qhd_control(dev_addr);
-    ehci_qtd_t* qtd = qtd_control(dev_addr);
+    qhd = qhd_control(dev_addr);
+    qtd = qtd_control(dev_addr);
 
     qtd_init(qtd, buffer, buflen);
 
     // first first data toggle is always 1 (data & setup stage)
     qtd->data_toggle = 1;
     qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT;
-    qtd->int_on_complete = 1;
-    qtd->next.terminate  = 1;
-
-    // sw region
-    qhd->p_qtd_list_head = qtd;
-    qhd->p_qtd_list_tail = qtd;
-
-    // attach TD
-    qhd->qtd_overlay.next.address = (uint32_t) qtd;
   }else
   {
-    ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
-    ehci_qtd_t *p_qtd = qtd_find_free();
-    TU_ASSERT(p_qtd);
+    qhd = qhd_get_from_addr(dev_addr, ep_addr);
+    qtd = qtd_find_free();
+    TU_ASSERT(qtd);
 
-    qtd_init(p_qtd, buffer, buflen);
-    p_qtd->pid = p_qhd->pid;
+    qtd_init(qtd, buffer, buflen);
+    qtd->pid = qhd->pid;
+  }
 
-    // Insert TD to QH
-    qtd_insert_to_qhd(p_qhd, p_qtd);
+  if (hcd_dcache_clean && hcd_dcache_clean_invalidate) {
+    // IN transfer: invalidate buffer, OUT transfer: clean buffer
+    if (dir) {
+      hcd_dcache_invalidate(buffer, buflen);
+    }else {
+      hcd_dcache_clean(buffer, buflen);
+    }
+    hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t));
+  }
 
-    p_qhd->p_qtd_list_tail->int_on_complete = 1;
+  // Software: assign TD to QHD
+  qhd->p_qtd_list_head = qtd;
+  qhd->p_qtd_list_tail = qtd;
 
-    // attach head QTD to QHD start transferring
-    p_qhd->qtd_overlay.next.address = (uint32_t) p_qhd->p_qtd_list_head;
+  // attach TD to QHD start transferring
+  qhd->qtd_overlay.next.address = (uint32_t) qtd;
+
+  if (hcd_dcache_clean_invalidate) {
+    hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
   }
 
   return true;
@@ -551,6 +569,11 @@ static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
   while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active)
   {
     ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head;
+
+    if (hcd_dcache_invalidate) {
+      hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
+    }
+
     bool const is_ioc = (qtd->int_on_complete != 0);
     uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0);
 
@@ -573,8 +596,12 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
   ehci_qhd_t *p_qhd = async_head;
   do
   {
-    if ( !p_qhd->qtd_overlay.halted ) // halted or error is processed in error isr
-    {
+    if (hcd_dcache_invalidate) {
+      hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t));
+    }
+
+    // halted or error is processed in error isr
+    if ( !p_qhd->qtd_overlay.halted ) {
       qhd_xfer_complete_isr(p_qhd);
     }
     p_qhd = qhd_next(p_qhd);
@@ -640,8 +667,8 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
 //      while(1){}
 //    }
 
-    // No TD, probably an signal noise ?
-    TU_VERIFY(p_qhd->p_qtd_list_head, );
+    // No TD yet, it is probably the probably an signal noise ?
+    TU_ASSERT(p_qhd->p_qtd_list_head, );
 
     p_qhd->p_qtd_list_head->used = 0; // free QTD
     qtd_remove_1st_from_qhd(p_qhd);
@@ -714,17 +741,19 @@ static void xfer_error_isr(uint8_t hostid)
 void hcd_int_handler(uint8_t rhport)
 {
   ehci_registers_t* regs = ehci_data.regs;
+  uint32_t const int_status = regs->status;
 
-  uint32_t int_status = regs->status;
-  int_status &= regs->inten;
-
-  regs->status = int_status; // Acknowledge handled interrupt
-
-  if (int_status == 0) return;
+  if (int_status & EHCI_INT_MASK_HC_HALTED) {
+    // something seriously wrong, maybe forget to flush/invalidate cache
+    TU_BREAKPOINT();
+    TU_LOG1("  HC halted\n");
+    return;
+  }
 
   if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER)
   {
     ehci_data.uframe_number += (FRAMELIST_SIZE << 3);
+    regs->status = EHCI_INT_MASK_FRAMELIST_ROLLOVER; // Acknowledge
   }
 
   if (int_status & EHCI_INT_MASK_PORT_CHANGE)
@@ -739,31 +768,41 @@ void hcd_int_handler(uint8_t rhport)
     }
 
     regs->portsc |= port_status; // Acknowledge change bits in portsc
+    regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge
   }
 
   if (int_status & EHCI_INT_MASK_ERROR)
   {
     xfer_error_isr(rhport);
+    regs->status = EHCI_INT_MASK_ERROR; // Acknowledge
   }
 
   //------------- some QTD/SITD/ITD with IOC set is completed -------------//
   if (int_status & EHCI_INT_MASK_NXP_ASYNC)
   {
-    async_list_xfer_complete_isr( qhd_async_head(rhport) );
+    async_list_xfer_complete_isr(qhd_async_head(rhport));
+    regs->status = EHCI_INT_MASK_NXP_ASYNC; // Acknowledge
   }
 
   if (int_status & EHCI_INT_MASK_NXP_PERIODIC)
   {
     for (uint32_t i=1; i <= FRAMELIST_SIZE; i *= 2)
     {
-      period_list_xfer_complete_isr( rhport, i );
+      period_list_xfer_complete_isr(rhport, i);
     }
+    regs->status = EHCI_INT_MASK_NXP_PERIODIC; // Acknowledge
+  }
+
+  if (int_status & EHCI_INT_MASK_USB) {
+    // TODO standard EHCI xfer complete
+    regs->status = EHCI_INT_MASK_USB; // Acknowledge
   }
 
   //------------- There is some removed async previously -------------//
-  if (int_status & EHCI_INT_MASK_ASYNC_ADVANCE) // need to place after EHCI_INT_MASK_NXP_ASYNC
-  {
+  // need to place after EHCI_INT_MASK_NXP_ASYNC
+  if (int_status & EHCI_INT_MASK_ASYNC_ADVANCE) {
     async_advance_isr(rhport);
+    regs->status = EHCI_INT_MASK_ASYNC_ADVANCE; // Acknowledge
   }
 }
 
@@ -918,28 +957,30 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
   }
 }
 
-static void qtd_init(ehci_qtd_t* p_qtd, void const* buffer, uint16_t total_bytes)
+static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
 {
-  tu_memclr(p_qtd, sizeof(ehci_qtd_t));
+  tu_memclr(qtd, sizeof(ehci_qtd_t));
+  qtd->used                = 1;
 
-  p_qtd->used                = 1;
+  qtd->next.terminate      = 1; // init to null
+  qtd->alternate.terminate = 1; // not used, always set to terminated
+  qtd->active              = 1;
+  qtd->err_count           = 3; // TODO 3 consecutive errors tolerance
+  qtd->data_toggle         = 0;
+  qtd->int_on_complete     = 1;
+  qtd->total_bytes         = total_bytes;
+  qtd->expected_bytes      = total_bytes;
 
-  p_qtd->next.terminate      = 1; // init to null
-  p_qtd->alternate.terminate = 1; // not used, always set to terminated
-  p_qtd->active              = 1;
-  p_qtd->err_count           = 3; // TODO 3 consecutive errors tolerance
-  p_qtd->data_toggle         = 0;
-  p_qtd->total_bytes         = total_bytes;
-  p_qtd->expected_bytes      = total_bytes;
-
-  p_qtd->buffer[0] = (uint32_t) buffer;
+  qtd->buffer[0] = (uint32_t) buffer;
   for(uint8_t i=1; i<5; i++)
   {
-    p_qtd->buffer[i] |= tu_align4k( p_qtd->buffer[i-1] ) + 4096;
+    qtd->buffer[i] |= tu_align4k(qtd->buffer[i - 1] ) + 4096;
   }
 }
 
 //------------- List Managing Helper -------------//
+
+// insert at head
 static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type)
 {
   new->address = current->address;
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index 56befd306..e76a59401 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -165,6 +165,7 @@ typedef struct TU_ATTR_ALIGNED(32)
 	uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set
 	uint8_t reserved2[2];
 
+  // TODO USBH will only queue 1 TD per QHD, thus we can remove the list
 	ehci_qtd_t * volatile p_qtd_list_head;	// head of the scheduled TD list
 	ehci_qtd_t * volatile p_qtd_list_tail;	// tail of the scheduled TD list
 } ehci_qhd_t;

From e4f4ad5bc3a24f619b9cf6c542aaa3ff8cb37ec4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 May 2023 10:21:11 +0700
Subject: [PATCH 1727/2085] use weak local for dcache function to skip if()

---
 src/portable/ehci/ehci.c | 65 +++++++++++++++++++++-------------------
 1 file changed, 34 insertions(+), 31 deletions(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 9023e4b35..ac715aa60 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -164,6 +164,25 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
 static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
 static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer);
 
+TU_ATTR_WEAK void hcd_dcache_clean(void* addr, uint32_t data_size) {
+  (void) addr;
+  (void) data_size;
+}
+
+// invalidate data cache: mark cache as invalid, next read will read from memory
+// Required BOTH before and after an DMA RX transfer
+TU_ATTR_WEAK void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
+  (void) addr;
+  (void) data_size;
+}
+
+// clean and invalidate data cache
+// Required before an DMA transfer where memory is both read/write by DMA
+TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+  (void) addr;
+  (void) data_size;
+}
+
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
@@ -342,9 +361,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
 
   regs->periodic_list_base = (uint32_t) framelist;
 
-  if(hcd_dcache_clean) {
-    hcd_dcache_clean(&ehci_data, sizeof(ehci_data_t));
-  }
+  hcd_dcache_clean(&ehci_data, sizeof(ehci_data_t));
 
   //------------- TT Control (NXP only) -------------//
   regs->nxp_tt_control = 0;
@@ -429,10 +446,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   // TODO might need to disable async/period list
   list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD);
 
-  if(hcd_dcache_clean) {
-    hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t));
-    hcd_dcache_clean(list_head, sizeof(ehci_link_t));
-  }
+  hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t));
+  hcd_dcache_clean(list_head, sizeof(ehci_link_t));
 
   return true;
 }
@@ -447,10 +462,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   qtd_init(td, setup_packet, 8);
   td->pid = EHCI_PID_SETUP;
 
-  if (hcd_dcache_clean && hcd_dcache_clean_invalidate) {
-    hcd_dcache_clean((void *) setup_packet, 8);
-    hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t));
-  }
+  hcd_dcache_clean((void *) setup_packet, 8);
+  hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t));
 
   // sw region
   qhd->p_qtd_list_head = td;
@@ -459,9 +472,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   // attach TD
   qhd->qtd_overlay.next.address = (uint32_t) td;
 
-  if (hcd_dcache_clean_invalidate) {
-    hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
-  }
+  hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
 
   return true;
 }
@@ -496,15 +507,13 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     qtd->pid = qhd->pid;
   }
 
-  if (hcd_dcache_clean && hcd_dcache_clean_invalidate) {
-    // IN transfer: invalidate buffer, OUT transfer: clean buffer
-    if (dir) {
-      hcd_dcache_invalidate(buffer, buflen);
-    }else {
-      hcd_dcache_clean(buffer, buflen);
-    }
-    hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t));
+  // IN transfer: invalidate buffer, OUT transfer: clean buffer
+  if (dir) {
+    hcd_dcache_invalidate(buffer, buflen);
+  }else {
+    hcd_dcache_clean(buffer, buflen);
   }
+  hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t));
 
   // Software: assign TD to QHD
   qhd->p_qtd_list_head = qtd;
@@ -513,9 +522,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   // attach TD to QHD start transferring
   qhd->qtd_overlay.next.address = (uint32_t) qtd;
 
-  if (hcd_dcache_clean_invalidate) {
-    hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
-  }
+  hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
 
   return true;
 }
@@ -570,9 +577,7 @@ static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
   {
     ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head;
 
-    if (hcd_dcache_invalidate) {
-      hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
-    }
+    hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
 
     bool const is_ioc = (qtd->int_on_complete != 0);
     uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0);
@@ -596,9 +601,7 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
   ehci_qhd_t *p_qhd = async_head;
   do
   {
-    if (hcd_dcache_invalidate) {
-      hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t));
-    }
+    hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t));
 
     // halted or error is processed in error isr
     if ( !p_qhd->qtd_overlay.halted ) {

From a0aea52a117246f246529459f9203ce36d2fcd81 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 May 2023 12:39:53 +0700
Subject: [PATCH 1728/2085] more cache, fix an similar issue with OHCI when
 removing an queue head

---
 src/portable/ehci/ehci.c | 50 ++++++++++++++++++++++------------------
 src/portable/ehci/ehci.h |  2 ++
 2 files changed, 29 insertions(+), 23 deletions(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index ac715aa60..0b4202788 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -162,7 +162,7 @@ static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd);
 static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes);
 
 static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
-static inline ehci_link_t* list_next (ehci_link_t *p_link_pointer);
+static inline ehci_link_t* list_next (ehci_link_t const *p_link);
 
 TU_ATTR_WEAK void hcd_dcache_clean(void* addr, uint32_t data_size) {
   (void) addr;
@@ -237,24 +237,22 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
   return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed
 }
 
-static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
-{
-  for(ehci_link_t* prev = list_head;
-      !prev->terminate && (tu_align32(prev->address) != (uint32_t) list_head) && prev != NULL;
-      prev = list_next(prev) )
-  {
-    // TODO check type for ISO iTD and siTD
-    // TODO Suppress cast-align warning
-    #pragma GCC diagnostic push
-    #pragma GCC diagnostic ignored "-Wcast-align"
-    ehci_qhd_t* qhd = (ehci_qhd_t*) list_next(prev);
-    #pragma GCC diagnostic pop
-    if ( qhd->dev_addr == dev_addr )
-    {
+static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) {
+  ehci_link_t* prev = list_head;
+
+  while (prev && !prev->terminate) {
+    ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev);
+
+    // done if loop back to head
+    if ( (uintptr_t) qhd == (uintptr_t) list_head) {
+      break;
+    }
+
+    if ( qhd->dev_addr == dev_addr ) {
       // TODO deactivate all TD, wait for QHD to inactive before removal
       prev->address = qhd->next.address;
 
-      // EHCI 4.8.2 link the removed qhd to async head (which always reachable by Host Controller)
+      // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller)
       qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1);
 
       if ( qhd->int_smask )
@@ -267,6 +265,11 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
         // mark as removing, will completely re-usable when async advance isr occurs
         qhd->removing = 1;
       }
+
+      hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
+      hcd_dcache_clean(prev, sizeof(ehci_qhd_t));
+    }else {
+      prev = list_next(prev);
     }
   }
 }
@@ -275,15 +278,16 @@ static void list_remove_qhd_by_addr(ehci_link_t* list_head, uint8_t dev_addr)
 void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 {
   // skip dev0
-  if (dev_addr == 0) return;
+  if (dev_addr == 0) {
+    return;
+  }
 
   // Remove from async list
-  list_remove_qhd_by_addr( (ehci_link_t*) qhd_async_head(rhport), dev_addr );
+  list_remove_qhd_by_daddr((ehci_link_t *) qhd_async_head(rhport), dev_addr);
 
   // Remove from all interval period list
-  for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++)
-  {
-    list_remove_qhd_by_addr( (ehci_link_t*) &ehci_data.period_head_arr[i], dev_addr);
+  for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) {
+    list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], dev_addr);
   }
 
   // Async doorbell (EHCI 4.8.2 for operational details)
@@ -990,9 +994,9 @@ static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t n
   current->address = ((uint32_t) new) | (new_type << 1);
 }
 
-static inline ehci_link_t* list_next(ehci_link_t *p_link_pointer)
+static inline ehci_link_t* list_next(ehci_link_t const *p_link)
 {
-  return (ehci_link_t*) tu_align32(p_link_pointer->address);
+  return (ehci_link_t*) tu_align32(p_link->address);
 }
 
 #endif
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index e76a59401..d7d37d627 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -81,6 +81,8 @@ typedef union {
 	};
 }ehci_link_t;
 
+TU_VERIFY_STATIC( sizeof(ehci_link_t) == 4, "size is not correct" );
+
 /// Queue Element Transfer Descriptor
 /// Qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with TU_ATTR_ALIGNED(32)
 typedef struct

From 49e2aabc819f761284dd490fd4f1c5d4ad5c3695 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 May 2023 13:45:38 +0700
Subject: [PATCH 1729/2085] EHCI more improvement

- more dcache clean/invalidate
- extract init_periodic_list()
- improve isr list handling
---
 src/host/hcd.h           |   2 +-
 src/portable/ehci/ehci.c | 204 +++++++++++++++++++++------------------
 2 files changed, 109 insertions(+), 97 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index c6fde2adc..5a3b0a087 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -175,7 +175,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
 
 // clear stall, data toggle is also reset to DATA0
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
+bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
 // USBH implemented API
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 0b4202788..0b45d7b93 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -294,6 +294,40 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
   ehci_data.regs->command_bm.async_adv_doorbell = 1;
 }
 
+static void init_periodic_list(uint8_t rhport) {
+  // Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only
+  for ( uint32_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++ ) {
+    ehci_data.period_head_arr[i].int_smask          = 1; // queue head in period list must have smask non-zero
+    ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive
+  }
+
+  ehci_link_t * const framelist  = ehci_data.period_framelist;
+  ehci_link_t * const period_1ms = get_period_head(rhport, 1u);
+
+  // all links --> period_head_arr[0] (1ms)
+  // 0, 2, 4, 6 etc --> period_head_arr[1] (2ms)
+  // 1, 5 --> period_head_arr[2] (4ms)
+  // 3 --> period_head_arr[3] (8ms)
+
+  // TODO EHCI_FRAMELIST_SIZE with other size than 8
+  for (uint32_t i = 0; i < FRAMELIST_SIZE; i++) {
+    framelist[i].address = (uint32_t) period_1ms;
+    framelist[i].type = EHCI_QTYPE_QHD;
+  }
+
+  for (uint32_t i = 0; i < FRAMELIST_SIZE; i += 2) {
+    list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD);
+  }
+
+  for (uint32_t i = 1; i < FRAMELIST_SIZE; i += 4) {
+    list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD);
+  }
+
+  list_insert(framelist + 3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD);
+
+  period_1ms->terminate    = 1;
+}
+
 bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
 {
   tu_memclr(&ehci_data, sizeof(ehci_data_t));
@@ -332,38 +366,8 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   regs->async_list_addr = (uint32_t) async_head;
 
   //------------- Periodic List -------------//
-  // Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only
-  for ( uint32_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++ )
-  {
-    ehci_data.period_head_arr[i].int_smask          = 1; // queue head in period list must have smask non-zero
-    ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive
-  }
-
-  ehci_link_t * const framelist  = ehci_data.period_framelist;
-  ehci_link_t * const period_1ms = get_period_head(rhport, 1u);
-
-  // all links --> period_head_arr[0] (1ms)
-  // 0, 2, 4, 6 etc --> period_head_arr[1] (2ms)
-  // 1, 5 --> period_head_arr[2] (4ms)
-  // 3 --> period_head_arr[3] (8ms)
-
-  // TODO EHCI_FRAMELIST_SIZE with other size than 8
-  for (uint32_t i = 0; i < FRAMELIST_SIZE; i++) {
-    framelist[i].address = (uint32_t) period_1ms;
-    framelist[i].type = EHCI_QTYPE_QHD;
-  }
-
-  for (uint32_t i = 0; i < FRAMELIST_SIZE; i += 2) {
-    list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD);
-  }
-
-  for (uint32_t i = 1; i < FRAMELIST_SIZE; i += 4) {
-    list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD);
-  }
-  list_insert(framelist + 3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD);
-  period_1ms->terminate    = 1;
-
-  regs->periodic_list_base = (uint32_t) framelist;
+  init_periodic_list(rhport);
+  regs->periodic_list_base = (uint32_t) ehci_data.period_framelist;
 
   hcd_dcache_clean(&ehci_data, sizeof(ehci_data_t));
 
@@ -491,8 +495,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   ehci_qhd_t* qhd;
   ehci_qtd_t* qtd;
 
-  if ( epnum == 0 )
-  {
+  if (epnum == 0) {
     qhd = qhd_control(dev_addr);
     qtd = qtd_control(dev_addr);
 
@@ -501,8 +504,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     // first first data toggle is always 1 (data & setup stage)
     qtd->data_toggle = 1;
     qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT;
-  }else
-  {
+  } else {
     qhd = qhd_get_from_addr(dev_addr, ep_addr);
     qtd = qtd_find_free();
     TU_ASSERT(qtd);
@@ -531,10 +533,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   return true;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
+bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr)
 {
-  ehci_qhd_t *p_qhd = qhd_get_from_addr(dev_addr, ep_addr);
-  p_qhd->qtd_overlay.halted = 0;
+  ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr);
+  qhd->qtd_overlay.halted = 0;
+  hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
   // TODO reset data toggle ?
   return true;
 }
@@ -546,22 +549,22 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 // async_advance is handshake between usb stack & ehci controller.
 // This isr mean it is safe to modify previously removed queue head from async list.
 // In tinyusb, queue head is only removed when device is unplugged.
-static void async_advance_isr(uint8_t rhport)
+TU_ATTR_ALWAYS_INLINE static inline
+void async_advance_isr(uint8_t rhport)
 {
   (void) rhport;
 
-  ehci_qhd_t* qhd_pool = ehci_data.qhd_pool;
-  for(uint32_t i = 0; i < QHD_MAX; i++)
-  {
-    if ( qhd_pool[i].removing )
-    {
+  ehci_qhd_t *qhd_pool = ehci_data.qhd_pool;
+  for (uint32_t i = 0; i < QHD_MAX; i++) {
+    if (qhd_pool[i].removing) {
       qhd_pool[i].removing = 0;
-      qhd_pool[i].used     = 0;
+      qhd_pool[i].used = 0;
     }
   }
 }
 
-static void port_connect_status_change_isr(uint8_t rhport)
+TU_ATTR_ALWAYS_INLINE static inline
+void port_connect_status_change_isr(uint8_t rhport)
 {
   // NOTE There is an sequence plug->unplug->…..-> plug if device is powering with pre-plugged device
   if (ehci_data.regs->portsc_bm.current_connect_status)
@@ -574,13 +577,13 @@ static void port_connect_status_change_isr(uint8_t rhport)
   }
 }
 
-static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
+TU_ATTR_ALWAYS_INLINE static inline
+void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
 {
   // free all TDs from the head td to the first active TD
   while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active)
   {
     ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head;
-
     hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
 
     bool const is_ioc = (qtd->int_on_complete != 0);
@@ -600,7 +603,8 @@ static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
   }
 }
 
-static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
+TU_ATTR_ALWAYS_INLINE static inline
+void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
 {
   ehci_qhd_t *p_qhd = async_head;
   do
@@ -611,46 +615,55 @@ static void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
     if ( !p_qhd->qtd_overlay.halted ) {
       qhd_xfer_complete_isr(p_qhd);
     }
+
     p_qhd = qhd_next(p_qhd);
   }while(p_qhd != async_head); // async list traversal, stop if loop around
 }
 
-static void period_list_xfer_complete_isr(uint8_t hostid, uint32_t interval_ms)
+TU_ATTR_ALWAYS_INLINE static inline
+void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms)
 {
-  uint16_t max_loop = 0;
-  uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1u);
-  ehci_link_t next_item = * get_period_head(hostid, interval_ms);
+  uint32_t const period_1ms_addr = (uint32_t) get_period_head(rhport, 1u);
+  ehci_link_t next_link = * get_period_head(rhport, interval_ms);
 
-  // TODO abstract max loop guard for period
-  while( !next_item.terminate &&
-      !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) &&
-      max_loop < (QHD_MAX + EHCI_MAX_ITD + EHCI_MAX_SITD)*CFG_TUH_DEVICE_MAX)
-  {
-    switch ( next_item.type )
-    {
-      case EHCI_QTYPE_QHD:
-      {
-        ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address);
-        if ( !p_qhd_int->qtd_overlay.halted )
-        {
-          qhd_xfer_complete_isr(p_qhd_int);
-        }
-      }
+  while (!next_link.terminate) {
+    if (interval_ms > 1 && period_1ms_addr == tu_align32(next_link.address)) {
+      // 1ms period list is end of list for all larger interval
       break;
-
-      case EHCI_QTYPE_ITD: // TODO support hs/fs ISO
-      case EHCI_QTYPE_SITD:
-      case EHCI_QTYPE_FSTN:
-
-      default: break;
     }
 
-    next_item = *list_next(&next_item);
-    max_loop++;
+    uintptr_t const entry_addr = tu_align32(next_link.address);
+
+    switch (next_link.type) {
+      case EHCI_QTYPE_QHD: {
+        ehci_qhd_t *qhd = (ehci_qhd_t *) entry_addr;
+        hcd_dcache_invalidate(qhd, sizeof(ehci_qhd_t));
+
+        if (!qhd->qtd_overlay.halted) {
+          qhd_xfer_complete_isr(qhd);
+        }
+      }
+        break;
+
+      case EHCI_QTYPE_ITD:
+        // TODO support hs ISO
+        break;
+
+      case EHCI_QTYPE_SITD:
+        // TODO support split ISO
+        break;
+
+      case EHCI_QTYPE_FSTN:
+      default:
+        break;
+    }
+
+    next_link = *list_next(&next_link);
   }
 }
 
-static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
+TU_ATTR_ALWAYS_INLINE static inline
+void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
 {
   volatile ehci_qtd_t *qtd_overlay = &p_qhd->qtd_overlay;
 
@@ -666,22 +679,22 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
       xfer_result = XFER_RESULT_STALLED;
     }
 
-    p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
-
 //    if (XFER_RESULT_FAILED == xfer_result ) {
 //      TU_LOG1("  QHD xfer err count: %d\n", qtd_overlay->err_count);
 //      TU_BREAKPOINT(); // TODO skip unplugged device
 //      while(1){}
 //    }
 
-    // No TD yet, it is probably the probably an signal noise ?
-    TU_ASSERT(p_qhd->p_qtd_list_head, );
+    ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head;
+    TU_ASSERT(qtd, ); // No TD yet, probably a race condition or cache issue !?
 
-    p_qhd->p_qtd_list_head->used = 0; // free QTD
+    hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
+    p_qhd->total_xferred_bytes += qtd->expected_bytes - qtd->total_bytes;
+
+    qtd->used = 0; // free QTD
     qtd_remove_1st_from_qhd(p_qhd);
 
-    if ( 0 == p_qhd->ep_number )
-    {
+    if ( 0 == p_qhd->ep_number ) {
       // control cannot be halted --> clear all qtd list
       p_qhd->p_qtd_list_head = NULL;
       p_qhd->p_qtd_list_tail = NULL;
@@ -702,13 +715,15 @@ static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
   }
 }
 
-static void xfer_error_isr(uint8_t hostid)
+TU_ATTR_ALWAYS_INLINE static inline
+void xfer_error_isr(uint8_t hostid)
 {
   //------------- async list -------------//
   ehci_qhd_t * const async_head = qhd_async_head(hostid);
   ehci_qhd_t *p_qhd = async_head;
   do
   {
+    hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t));
     qhd_xfer_error_isr( p_qhd );
     p_qhd = qhd_next(p_qhd);
   }while(p_qhd != async_head); // async list traversal, stop if loop around
@@ -728,6 +743,8 @@ static void xfer_error_isr(uint8_t hostid)
         case EHCI_QTYPE_QHD:
         {
           ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address);
+          hcd_dcache_invalidate(p_qhd_int, sizeof(ehci_qhd_t));
+
           qhd_xfer_error_isr(p_qhd_int);
         }
         break;
@@ -757,20 +774,17 @@ void hcd_int_handler(uint8_t rhport)
     return;
   }
 
-  if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER)
-  {
+  if (int_status & EHCI_INT_MASK_FRAMELIST_ROLLOVER) {
     ehci_data.uframe_number += (FRAMELIST_SIZE << 3);
     regs->status = EHCI_INT_MASK_FRAMELIST_ROLLOVER; // Acknowledge
   }
 
-  if (int_status & EHCI_INT_MASK_PORT_CHANGE)
-  {
+  if (int_status & EHCI_INT_MASK_PORT_CHANGE) {
     // Including: Force port resume, over-current change, enable/disable change and connect status change.
     uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_W1C;
     print_portsc(regs);
 
-    if (regs->portsc_bm.connect_status_change)
-    {
+    if (regs->portsc_bm.connect_status_change) {
       port_connect_status_change_isr(rhport);
     }
 
@@ -778,15 +792,13 @@ void hcd_int_handler(uint8_t rhport)
     regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge
   }
 
-  if (int_status & EHCI_INT_MASK_ERROR)
-  {
+  if (int_status & EHCI_INT_MASK_ERROR) {
     xfer_error_isr(rhport);
     regs->status = EHCI_INT_MASK_ERROR; // Acknowledge
   }
 
   //------------- some QTD/SITD/ITD with IOC set is completed -------------//
-  if (int_status & EHCI_INT_MASK_NXP_ASYNC)
-  {
+  if (int_status & EHCI_INT_MASK_NXP_ASYNC) {
     async_list_xfer_complete_isr(qhd_async_head(rhport));
     regs->status = EHCI_INT_MASK_NXP_ASYNC; // Acknowledge
   }

From 27acaa013bd8af8ac29e966d7dc145b33dd6bc73 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 May 2023 15:44:08 +0700
Subject: [PATCH 1730/2085] refactor ehci, since usbh only queue 1 TD per queue
 head

---
 src/portable/ehci/ehci.c | 117 ++++++++++++---------------------------
 src/portable/ehci/ehci.h |  16 +-----
 2 files changed, 39 insertions(+), 94 deletions(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 0b45d7b93..a08731667 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -156,9 +156,6 @@ static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
 
 static inline ehci_qtd_t* qtd_find_free (void);
-static inline ehci_qtd_t* qtd_next (ehci_qtd_t const * p_qtd);
-static inline void qtd_insert_to_qhd (ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new);
-static inline void qtd_remove_1st_from_qhd (ehci_qhd_t *p_qhd);
 static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes);
 
 static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
@@ -473,11 +470,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   hcd_dcache_clean((void *) setup_packet, 8);
   hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t));
 
-  // sw region
-  qhd->p_qtd_list_head = td;
-  qhd->p_qtd_list_tail = td;
-
   // attach TD
+  qhd->p_attached_qtd = td; // software management
   qhd->qtd_overlay.next.address = (uint32_t) td;
 
   hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
@@ -501,7 +495,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
     qtd_init(qtd, buffer, buflen);
 
-    // first first data toggle is always 1 (data & setup stage)
+    // first data toggle is always 1 (data & setup stage)
     qtd->data_toggle = 1;
     qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT;
   } else {
@@ -521,11 +515,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   }
   hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t));
 
-  // Software: assign TD to QHD
-  qhd->p_qtd_list_head = qtd;
-  qhd->p_qtd_list_tail = qtd;
-
   // attach TD to QHD start transferring
+  qhd->p_attached_qtd = qtd; // software management
   qhd->qtd_overlay.next.address = (uint32_t) qtd;
 
   hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
@@ -580,27 +571,25 @@ void port_connect_status_change_isr(uint8_t rhport)
 TU_ATTR_ALWAYS_INLINE static inline
 void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
 {
-  // free all TDs from the head td to the first active TD
-  while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active)
-  {
-    ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head;
-    hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
+  // examine TD attached to queue head
+  ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_attached_qtd;
+  if (qtd == NULL) return; // no TD attached
+  hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
 
-    bool const is_ioc = (qtd->int_on_complete != 0);
-    uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0);
-
-    p_qhd->total_xferred_bytes += qtd->expected_bytes - qtd->total_bytes;
-
-    // TD need to be freed and removed from qhd, before invoking callback
-    qtd->used = 0; // free QTD
-    qtd_remove_1st_from_qhd(p_qhd);
-
-    if (is_ioc)
-    {
-      hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, p_qhd->total_xferred_bytes, XFER_RESULT_SUCCESS, true);
-      p_qhd->total_xferred_bytes = 0;
-    }
+  // TD is still active, no need to process
+  if (qtd->active) {
+    return;
   }
+
+  uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
+  uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0);
+
+  // remove and free TD before invoking callback
+  p_qhd->p_attached_qtd = NULL;
+  qtd->used = 0; // free QTD
+
+  // IOC is always set
+  hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, xferred_bytes, XFER_RESULT_SUCCESS, true);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
@@ -685,20 +674,17 @@ void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
 //      while(1){}
 //    }
 
-    ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_qtd_list_head;
+    ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_attached_qtd;
     TU_ASSERT(qtd, ); // No TD yet, probably a race condition or cache issue !?
 
     hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
-    p_qhd->total_xferred_bytes += qtd->expected_bytes - qtd->total_bytes;
+    uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
 
+    p_qhd->p_attached_qtd = NULL;
     qtd->used = 0; // free QTD
-    qtd_remove_1st_from_qhd(p_qhd);
 
     if ( 0 == p_qhd->ep_number ) {
-      // control cannot be halted --> clear all qtd list
-      p_qhd->p_qtd_list_head = NULL;
-      p_qhd->p_qtd_list_tail = NULL;
-
+      // control cannot be halted
       p_qhd->qtd_overlay.next.terminate      = 1;
       p_qhd->qtd_overlay.alternate.terminate = 1;
       p_qhd->qtd_overlay.halted              = 0;
@@ -707,19 +693,17 @@ void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
       p_setup->used = 0;
     }
 
-    // call USBH callback
+    // notify usbh
     uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0);
-    hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, p_qhd->total_xferred_bytes, xfer_result, true);
-
-    p_qhd->total_xferred_bytes = 0;
+    hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true);
   }
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-void xfer_error_isr(uint8_t hostid)
+void xfer_error_isr(uint8_t rhport)
 {
   //------------- async list -------------//
-  ehci_qhd_t * const async_head = qhd_async_head(hostid);
+  ehci_qhd_t * const async_head = qhd_async_head(rhport);
   ehci_qhd_t *p_qhd = async_head;
   do
   {
@@ -729,10 +713,10 @@ void xfer_error_isr(uint8_t hostid)
   }while(p_qhd != async_head); // async list traversal, stop if loop around
 
   //------------- TODO refractor period list -------------//
-  uint32_t const period_1ms_addr = (uint32_t) get_period_head(hostid, 1u);
+  uint32_t const period_1ms_addr = (uint32_t) get_period_head(rhport, 1u);
   for (uint32_t interval_ms=1; interval_ms <= FRAMELIST_SIZE; interval_ms *= 2)
   {
-    ehci_link_t next_item = * get_period_head(hostid, interval_ms);
+    ehci_link_t next_item = * get_period_head(rhport, interval_ms);
 
     // TODO abstract max loop guard for period
     while( !next_item.terminate &&
@@ -873,34 +857,6 @@ static inline ehci_qtd_t* qtd_find_free(void)
   return NULL;
 }
 
-static inline ehci_qtd_t* qtd_next(ehci_qtd_t const * p_qtd )
-{
-  return (ehci_qtd_t*) tu_align32(p_qtd->next.address);
-}
-
-static inline void qtd_remove_1st_from_qhd(ehci_qhd_t *p_qhd)
-{
-  if (p_qhd->p_qtd_list_head == p_qhd->p_qtd_list_tail) // last TD --> make it NULL
-  {
-    p_qhd->p_qtd_list_head = p_qhd->p_qtd_list_tail = NULL;
-  }else
-  {
-    p_qhd->p_qtd_list_head = qtd_next( p_qhd->p_qtd_list_head );
-  }
-}
-
-static inline void qtd_insert_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new)
-{
-  if (p_qhd->p_qtd_list_head == NULL) // empty list
-  {
-    p_qhd->p_qtd_list_head               = p_qhd->p_qtd_list_tail = p_qtd_new;
-  }else
-  {
-    p_qhd->p_qtd_list_tail->next.address = (uint32_t) p_qtd_new;
-    p_qhd->p_qtd_list_tail               = p_qtd_new;
-  }
-}
-
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
   // address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise)
@@ -955,15 +911,14 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
     p_qhd->int_smask = p_qhd->fl_int_cmask = 0;
   }
 
-  p_qhd->fl_hub_addr     = devtree_info.hub_addr;
-  p_qhd->fl_hub_port     = devtree_info.hub_port;
-  p_qhd->mult            = 1; // TODO not use high bandwidth/park mode yet
+  p_qhd->fl_hub_addr    = devtree_info.hub_addr;
+  p_qhd->fl_hub_port    = devtree_info.hub_port;
+  p_qhd->mult           = 1; // TODO not use high bandwidth/park mode yet
 
   //------------- HCD Management Data -------------//
-  p_qhd->used            = 1;
-  p_qhd->removing        = 0;
-  p_qhd->p_qtd_list_head = NULL;
-  p_qhd->p_qtd_list_tail = NULL;
+  p_qhd->used           = 1;
+  p_qhd->removing       = 0;
+  p_qhd->p_attached_qtd = NULL;
   p_qhd->pid = tu_edpt_dir(ep_desc->bEndpointAddress) ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint
 
   //------------- active, but no TD list -------------//
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index d7d37d627..b525131c6 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -164,12 +164,10 @@ typedef struct TU_ATTR_ALIGNED(32)
 	uint8_t pid;
 	uint8_t interval_ms; // polling interval in frames (or millisecond)
 
-	uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set
-	uint8_t reserved2[2];
+	uint8_t TU_RESERVED[8];
 
-  // TODO USBH will only queue 1 TD per QHD, thus we can remove the list
-	ehci_qtd_t * volatile p_qtd_list_head;	// head of the scheduled TD list
-	ehci_qtd_t * volatile p_qtd_list_tail;	// tail of the scheduled TD list
+  // usbh will only queue 1 TD per QHD
+	ehci_qtd_t * volatile p_attached_qtd;
 } ehci_qhd_t;
 
 TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" );
@@ -248,14 +246,6 @@ typedef struct TU_ATTR_ALIGNED(32)
 	/// Word 4-5: Buffer Pointer List
 	uint32_t buffer[2];		// buffer[1] TP: Transaction Position - T-Count: Transaction Count
 
-// 	union{
-// 		uint32_t BufferPointer1;
-// 		struct  {
-// 			volatile uint32_t TCount : 3;
-// 			volatile uint32_t TPosition : 2;
-// 		};
-// 	};
-
 	/*---------- Word 6 ----------*/
 	ehci_link_t back;
 

From ec4bd39a9209f37b02edac2f6a1ea2ef27f6b785 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 May 2023 16:41:06 +0700
Subject: [PATCH 1731/2085] refactor ehci: add attached_buffer for dcache
 invalidate for IN transfer

---
 src/portable/ehci/ehci.c | 116 ++++++++++++++++++++++-----------------
 src/portable/ehci/ehci.h |   8 ++-
 2 files changed, 72 insertions(+), 52 deletions(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index a08731667..cc825d549 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -154,6 +154,7 @@ static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd);
 static inline ehci_qhd_t* qhd_find_free (void);
 static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
+static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd);
 
 static inline ehci_qtd_t* qtd_find_free (void);
 static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes);
@@ -468,13 +469,9 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   td->pid = EHCI_PID_SETUP;
 
   hcd_dcache_clean((void *) setup_packet, 8);
-  hcd_dcache_clean_invalidate(td, sizeof(ehci_qtd_t));
 
-  // attach TD
-  qhd->p_attached_qtd = td; // software management
-  qhd->qtd_overlay.next.address = (uint32_t) td;
-
-  hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
+  // attach TD to QHD -> start transferring
+  qhd_attach_qtd(qhd, td);
 
   return true;
 }
@@ -513,13 +510,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   }else {
     hcd_dcache_clean(buffer, buflen);
   }
-  hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t));
 
-  // attach TD to QHD start transferring
-  qhd->p_attached_qtd = qtd; // software management
-  qhd->qtd_overlay.next.address = (uint32_t) qtd;
-
-  hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
+  // attach TD to QHD -> start transferring
+  qhd_attach_qtd(qhd, qtd);
 
   return true;
 }
@@ -569,10 +562,9 @@ void port_connect_status_change_isr(uint8_t rhport)
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
-{
+void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
   // examine TD attached to queue head
-  ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_attached_qtd;
+  ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd;
   if (qtd == NULL) return; // no TD attached
   hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
 
@@ -581,15 +573,22 @@ void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
     return;
   }
 
+  uint8_t dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0;
   uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
-  uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, qtd->pid == EHCI_PID_IN ? 1 : 0);
+
+  // invalidate dcache if IN transfer
+  if (dir == 1 && qhd->attached_buffer != 0) {
+    hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
+  }
 
   // remove and free TD before invoking callback
-  p_qhd->p_attached_qtd = NULL;
+  qhd->attached_qtd = NULL;
+  qhd->attached_buffer = 0;
   qtd->used = 0; // free QTD
 
-  // IOC is always set
-  hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, xferred_bytes, XFER_RESULT_SUCCESS, true);
+  // notify usbh
+  uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir);
+  hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, XFER_RESULT_SUCCESS, true);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
@@ -651,10 +650,11 @@ void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms)
   }
 }
 
+// TODO merge with qhd_xfer_complete_isr()
 TU_ATTR_ALWAYS_INLINE static inline
-void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
+void qhd_xfer_error_isr(ehci_qhd_t * qhd)
 {
-  volatile ehci_qtd_t *qtd_overlay = &p_qhd->qtd_overlay;
+  volatile ehci_qtd_t *qtd_overlay = &qhd->qtd_overlay;
 
   // TD has error
   if (qtd_overlay->halted) {
@@ -674,28 +674,37 @@ void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
 //      while(1){}
 //    }
 
-    ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) p_qhd->p_attached_qtd;
+    ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd;
     TU_ASSERT(qtd, ); // No TD yet, probably a race condition or cache issue !?
 
     hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
+
+    uint8_t dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0;
     uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
 
-    p_qhd->p_attached_qtd = NULL;
+    // invalidate dcache if IN transfer
+    if (dir == 1 && qhd->attached_buffer != 0) {
+      hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
+    }
+
+    // remove and free TD before invoking callback
+    qhd->attached_qtd = NULL;
+    qhd->attached_buffer = 0;
     qtd->used = 0; // free QTD
 
-    if ( 0 == p_qhd->ep_number ) {
+    if (0 == qhd->ep_number ) {
       // control cannot be halted
-      p_qhd->qtd_overlay.next.terminate      = 1;
-      p_qhd->qtd_overlay.alternate.terminate = 1;
-      p_qhd->qtd_overlay.halted              = 0;
+      qhd->qtd_overlay.next.terminate      = 1;
+      qhd->qtd_overlay.alternate.terminate = 1;
+      qhd->qtd_overlay.halted              = 0;
 
-      ehci_qtd_t *p_setup = qtd_control(p_qhd->dev_addr);
+      ehci_qtd_t *p_setup = qtd_control(qhd->dev_addr);
       p_setup->used = 0;
     }
 
     // notify usbh
-    uint8_t const ep_addr = tu_edpt_addr(p_qhd->ep_number, p_qhd->pid == EHCI_PID_IN ? 1 : 0);
-    hcd_event_xfer_complete(p_qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true);
+    uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir);
+    hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true);
   }
 }
 
@@ -846,22 +855,10 @@ static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr)
   return NULL;
 }
 
-//------------- TD helper -------------//
-static inline ehci_qtd_t* qtd_find_free(void)
-{
-  for (uint32_t i=0; i<QTD_MAX; i++)
-  {
-    if ( !ehci_data.qtd_pool[i].used ) return &ehci_data.qtd_pool[i];
-  }
-
-  return NULL;
-}
-
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
   // address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise)
-  if (dev_addr != 0)
-  {
+  if (dev_addr != 0) {
     tu_memclr(p_qhd, sizeof(ehci_qhd_t));
   }
 
@@ -911,26 +908,47 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
     p_qhd->int_smask = p_qhd->fl_int_cmask = 0;
   }
 
-  p_qhd->fl_hub_addr    = devtree_info.hub_addr;
-  p_qhd->fl_hub_port    = devtree_info.hub_port;
-  p_qhd->mult           = 1; // TODO not use high bandwidth/park mode yet
+  p_qhd->fl_hub_addr  = devtree_info.hub_addr;
+  p_qhd->fl_hub_port  = devtree_info.hub_port;
+  p_qhd->mult         = 1; // TODO not use high bandwidth/park mode yet
 
   //------------- HCD Management Data -------------//
-  p_qhd->used           = 1;
-  p_qhd->removing       = 0;
-  p_qhd->p_attached_qtd = NULL;
+  p_qhd->used         = 1;
+  p_qhd->removing     = 0;
+  p_qhd->attached_qtd = NULL;
   p_qhd->pid = tu_edpt_dir(ep_desc->bEndpointAddress) ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint
 
   //------------- active, but no TD list -------------//
   p_qhd->qtd_overlay.halted              = 0;
   p_qhd->qtd_overlay.next.terminate      = 1;
   p_qhd->qtd_overlay.alternate.terminate = 1;
+
   if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT)
   {
     p_qhd->qtd_overlay.ping_err = 1; // do PING for Highspeed Bulk OUT, EHCI section 4.11
   }
 }
 
+static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd) {
+  qhd->attached_qtd = qtd;
+  qhd->attached_buffer = qtd->buffer[0];
+
+  // clean and invalidate cache before physically write
+  hcd_dcache_clean_invalidate(qtd, sizeof(ehci_qtd_t));
+
+  qhd->qtd_overlay.next.address = (uint32_t) qtd;
+  hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
+}
+
+
+//------------- TD helper -------------//
+static inline ehci_qtd_t *qtd_find_free(void) {
+  for (uint32_t i = 0; i < QTD_MAX; i++) {
+    if (!ehci_data.qtd_pool[i].used) return &ehci_data.qtd_pool[i];
+  }
+  return NULL;
+}
+
 static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
 {
   tu_memclr(qtd, sizeof(ehci_qtd_t));
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index b525131c6..8338fb419 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -164,10 +164,12 @@ typedef struct TU_ATTR_ALIGNED(32)
 	uint8_t pid;
 	uint8_t interval_ms; // polling interval in frames (or millisecond)
 
-	uint8_t TU_RESERVED[8];
+	uint8_t TU_RESERVED[4];
 
-  // usbh will only queue 1 TD per QHD
-	ehci_qtd_t * volatile p_attached_qtd;
+  // Attached TD management, note usbh will only queue 1 TD per QHD.
+  // buffer for dcache invalidate since td's buffer is modified by HC and finding initial buffer address is not trivial
+  uint32_t attached_buffer;
+	ehci_qtd_t * volatile attached_qtd;
 } ehci_qhd_t;
 
 TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" );

From f22d8ee3b93000769ac8d177cd29467c81143f5e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 18 May 2023 16:46:02 +0700
Subject: [PATCH 1732/2085] add rt1060 jlink config

---
 .idea/runConfigurations/rt1060_jlink.xml | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 .idea/runConfigurations/rt1060_jlink.xml

diff --git a/.idea/runConfigurations/rt1060_jlink.xml b/.idea/runConfigurations/rt1060_jlink.xml
new file mode 100644
index 000000000..eabadaf59
--- /dev/null
+++ b/.idea/runConfigurations/rt1060_jlink.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt1060 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="host_hid_to_device_cdc" TARGET_NAME="host_hid_to_device_cdc" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="host_hid_to_device_cdc" RUN_TARGET_NAME="host_hid_to_device_cdc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file

From f26a93908ef9dcde6818c9b271727ed6c77e87d8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 May 2023 10:56:52 +0700
Subject: [PATCH 1733/2085] only clean/invalidate dcache on imxrt if memory is
 not in DTCM

---
 src/portable/chipidea/ci_hs/hcd_ci_hs.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index ecb1a621c..ab6a42e11 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -42,17 +42,28 @@
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   #include "ci_hs_imxrt.h"
 
+  // check if memory is cacheable i.e not in DTCM
+  TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uint32_t addr) {
+    return !(0x20000000 <= addr && addr < 0x20100000);
+  }
+
   void hcd_dcache_clean(void* addr, uint32_t data_size) {
-    SCB_CleanDCache_by_Addr((uint32_t*) addr, (int32_t) data_size);
+    if (is_cache_mem((uint32_t) addr)) {
+      SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size);
+    }
   }
 
   void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
-    SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
+    if (is_cache_mem((uint32_t) addr)) {
+      SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
+    }
   }
 
 void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+  if (is_cache_mem((uint32_t) addr)) {
     SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
   }
+}
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"

From 5dae5e12928ba789cd7e248edd9fa91376902925 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 May 2023 13:32:49 +0700
Subject: [PATCH 1734/2085] ehci fix dcache clean when control endpoint failed

---
 hw/bsp/imxrt/family.cmake |  6 +++++-
 src/host/usbh.c           |  3 ++-
 src/portable/ehci/ehci.c  | 10 ++++------
 src/tusb.c                |  2 +-
 4 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 4628abc34..a475b4721 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -57,12 +57,16 @@ if (NOT TARGET ${BOARD_TARGET})
     )
   update_board(${BOARD_TARGET})
 
+  if (NOT DEFINED LD_FILE_${TOOLCHAIN})
+    set(LD_FILE_gcc ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
+  endif ()
+
   if (TOOLCHAIN STREQUAL "gcc")
     target_sources(${BOARD_TARGET} PUBLIC
       ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
       )
     target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld"
+      "LINKER:--script=${LD_FILE_gcc}"
       "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
       # nanolib
       --specs=nosys.specs
diff --git a/src/host/usbh.c b/src/host/usbh.c
index c56ff9459..7b265c742 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -440,7 +440,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
         uint8_t const epnum   = tu_edpt_number(ep_addr);
         uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
-        TU_LOG_USBH("on EP %02X with %u bytes %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len,
+        TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len,
                     tu_str_xfer_result[event.xfer_complete.result]);
 
         if (event.dev_addr == 0)
@@ -1255,6 +1255,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
     {
       failed_count++;
       osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit
+      TU_LOG1("Enumeration attempt %u\r\n", failed_count);
       TU_ASSERT(tuh_control_xfer(xfer), );
     }else
     {
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index cc825d549..10e2db7b5 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -577,7 +577,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
   uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
 
   // invalidate dcache if IN transfer
-  if (dir == 1 && qhd->attached_buffer != 0) {
+  if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) {
     hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
   }
 
@@ -660,7 +660,7 @@ void qhd_xfer_error_isr(ehci_qhd_t * qhd)
   if (qtd_overlay->halted) {
     xfer_result_t xfer_result;
 
-    if (qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err || qtd_overlay->xact_err) {
+    if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) {
       // Error count = 0 often occurs when device disconnected, or other bus-related error
       xfer_result = XFER_RESULT_FAILED;
     }else {
@@ -671,7 +671,6 @@ void qhd_xfer_error_isr(ehci_qhd_t * qhd)
 //    if (XFER_RESULT_FAILED == xfer_result ) {
 //      TU_LOG1("  QHD xfer err count: %d\n", qtd_overlay->err_count);
 //      TU_BREAKPOINT(); // TODO skip unplugged device
-//      while(1){}
 //    }
 
     ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd;
@@ -683,7 +682,7 @@ void qhd_xfer_error_isr(ehci_qhd_t * qhd)
     uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
 
     // invalidate dcache if IN transfer
-    if (dir == 1 && qhd->attached_buffer != 0) {
+    if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) {
       hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
     }
 
@@ -698,8 +697,7 @@ void qhd_xfer_error_isr(ehci_qhd_t * qhd)
       qhd->qtd_overlay.alternate.terminate = 1;
       qhd->qtd_overlay.halted              = 0;
 
-      ehci_qtd_t *p_setup = qtd_control(qhd->dev_addr);
-      p_setup->used = 0;
+      hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
     }
 
     // notify usbh
diff --git a/src/tusb.c b/src/tusb.c
index 7327db685..465b608b0 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -440,7 +440,7 @@ char const* const tu_str_std_request[] =
 };
 
 char const* const tu_str_xfer_result[] = {
-    "OK", "Failed", "Stalled", "Timeout"
+    "OK", "FAILED", "STALLED", "TIMEOUT"
 };
 
 #endif

From 7211dd18b46affdf027522e34ff3aa3b5d8d5df5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 May 2023 13:42:26 +0700
Subject: [PATCH 1735/2085] more dcache fix

---
 src/portable/ehci/ehci.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 10e2db7b5..852e7f4fe 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -273,19 +273,19 @@ static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) {
 }
 
 // Close all opened endpoint belong to this device
-void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
+void hcd_device_close(uint8_t rhport, uint8_t daddr)
 {
   // skip dev0
-  if (dev_addr == 0) {
+  if (daddr == 0) {
     return;
   }
 
   // Remove from async list
-  list_remove_qhd_by_daddr((ehci_link_t *) qhd_async_head(rhport), dev_addr);
+  list_remove_qhd_by_daddr((ehci_link_t *) qhd_async_head(rhport), daddr);
 
   // Remove from all interval period list
   for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) {
-    list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], dev_addr);
+    list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr);
   }
 
   // Async doorbell (EHCI 4.8.2 for operational details)
@@ -453,7 +453,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD);
 
   hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t));
-  hcd_dcache_clean(list_head, sizeof(ehci_link_t));
+  hcd_dcache_clean(list_head, sizeof(ehci_qhd_t));
 
   return true;
 }

From e8dd200fed6adeebd98ebc7abf09d45285da7abf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 May 2023 14:46:39 +0700
Subject: [PATCH 1736/2085] move cmake folder to tools/

---
 .idea/vcs.xml                                 | 61 -------------------
 hw/bsp/imxrt/family.cmake                     |  8 +--
 hw/bsp/lpc55/family.cmake                     | 13 ++--
 hw/bsp/nrf/family.cmake                       |  3 +-
 .../cmake/cpu/cortex-m33.cmake                |  0
 {examples => tools}/cmake/cpu/cortex-m4.cmake |  0
 {examples => tools}/cmake/cpu/cortex-m7.cmake |  0
 .../cmake/toolchain/arm_gcc.cmake             |  0
 .../cmake/toolchain/set_flags.cmake           |  0
 9 files changed, 12 insertions(+), 73 deletions(-)
 rename {examples => tools}/cmake/cpu/cortex-m33.cmake (100%)
 rename {examples => tools}/cmake/cpu/cortex-m4.cmake (100%)
 rename {examples => tools}/cmake/cpu/cortex-m7.cmake (100%)
 rename {examples => tools}/cmake/toolchain/arm_gcc.cmake (100%)
 rename {examples => tools}/cmake/toolchain/set_flags.cmake (100%)

diff --git a/.idea/vcs.xml b/.idea/vcs.xml
index 63371256f..94a25f7f4 100644
--- a/.idea/vcs.xml
+++ b/.idea/vcs.xml
@@ -1,67 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <project version="4">
   <component name="VcsDirectoryMappings">
-    <mapping directory="$PROJECT_DIR$/../pico/pico-sdk" vcs="Git" />
     <mapping directory="$PROJECT_DIR$" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/allwinner" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/bridgetek/ft9xx/ft90x-sdk" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/broadcom" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/gd/nuclei-sdk" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/infineon/mtb-xmclib-cat3" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/microchip" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/mindmotion/mm32sdk" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/nordic/nrfx" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/nuvoton" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/nxp/lpcopen" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/nxp/mcux-sdk" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/nxp/nxp_sdk" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/Pico-PIO-USB" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/btstack" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/cyw43-driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/lwip" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/mbedtls" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/raspberry_pi/pico-sdk/lib/tinyusb" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/renesas/fsp" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/renesas/rx" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/silabs/cmsis-dfp-efm32gg12b" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/sony/cxd56/spresense-exported-sdk" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f0" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f1" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f2" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f3" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f4" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_f7" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_g0" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_g4" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_h7" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_l0" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_l1" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_l4" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_l5" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_u5" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/cmsis_device_wb" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f0xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f1xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f2xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f3xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f4xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32f7xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32g0xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32g4xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32h7xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32l0xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32l1xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32l4xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32l5xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32u5xx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/st/stm32wbxx_hal_driver" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/ti" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/hw/mcu/wch/ch32v307" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/lib/CMSIS_5" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/lib/FreeRTOS-Kernel" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/lib/lwip" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/lib/sct_neopixel" vcs="Git" />
-    <mapping directory="$PROJECT_DIR$/tools/uf2" vcs="Git" />
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index a475b4721..e9be7acc8 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -8,9 +8,12 @@ if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
 endif ()
 
+# TOP is path to root directory
+set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
+
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS MIMXRT CACHE INTERNAL "")
 
@@ -24,9 +27,6 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 # only need to be built ONCE for all examples
 set(BOARD_TARGET board_${BOARD})
 if (NOT TARGET ${BOARD_TARGET})
-  # TOP is path to root directory
-  set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
-
   set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
   set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 0ac2b6ce3..439f54170 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -8,9 +8,14 @@ if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
 endif ()
 
+# TOP is path to root directory
+set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${CMAKE_CURRENT_LIST_DIR}/../../../examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
 
@@ -24,12 +29,6 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 # only need to be built ONCE for all examples
 set(BOARD_TARGET board_${BOARD})
 if (NOT TARGET ${BOARD_TARGET})
-  # TOP is path to root directory
-  set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
-
-  set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
-  set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
-
   add_library(${BOARD_TARGET} STATIC
     # external driver
     #lib/sct_neopixel/sct_neopixel.c
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index c8faa23cc..ca28c4f5d 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -25,10 +25,11 @@ else ()
   set(JLINK_DEVICE ${MCU_VARIANT}_xxaa)
 endif ()
 
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
 
+
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
diff --git a/examples/cmake/cpu/cortex-m33.cmake b/tools/cmake/cpu/cortex-m33.cmake
similarity index 100%
rename from examples/cmake/cpu/cortex-m33.cmake
rename to tools/cmake/cpu/cortex-m33.cmake
diff --git a/examples/cmake/cpu/cortex-m4.cmake b/tools/cmake/cpu/cortex-m4.cmake
similarity index 100%
rename from examples/cmake/cpu/cortex-m4.cmake
rename to tools/cmake/cpu/cortex-m4.cmake
diff --git a/examples/cmake/cpu/cortex-m7.cmake b/tools/cmake/cpu/cortex-m7.cmake
similarity index 100%
rename from examples/cmake/cpu/cortex-m7.cmake
rename to tools/cmake/cpu/cortex-m7.cmake
diff --git a/examples/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake
similarity index 100%
rename from examples/cmake/toolchain/arm_gcc.cmake
rename to tools/cmake/toolchain/arm_gcc.cmake
diff --git a/examples/cmake/toolchain/set_flags.cmake b/tools/cmake/toolchain/set_flags.cmake
similarity index 100%
rename from examples/cmake/toolchain/set_flags.cmake
rename to tools/cmake/toolchain/set_flags.cmake

From 270136e84af4f01c394be17fc0688461cf3d1f1c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 May 2023 16:02:26 +0700
Subject: [PATCH 1737/2085] adding cpu core .mk for makefile

fix cortex m33 for nrf5340 dk
---
 examples/make.mk                    |  3 +++
 hw/bsp/nrf/boards/pca10095/board.mk |  1 +
 hw/bsp/nrf/family.mk                |  9 ++++-----
 tools/make/cpu/cortex-m33.mk        | 11 +++++++++++
 tools/make/cpu/cortex-m4.mk         | 11 +++++++++++
 tools/make/cpu/cortex-m7.mk         | 11 +++++++++++
 6 files changed, 41 insertions(+), 5 deletions(-)
 create mode 100644 tools/make/cpu/cortex-m33.mk
 create mode 100644 tools/make/cpu/cortex-m4.mk
 create mode 100644 tools/make/cpu/cortex-m7.mk

diff --git a/examples/make.mk b/examples/make.mk
index 2ce6fb398..28ebc62da 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -2,6 +2,8 @@
 # Common make definition for all examples
 # ---------------------------------------
 
+TOOLCHAIN ?= gcc
+
 #-------------- TOP and CURRENT_PATH ------------
 
 # Set TOP to be the path to get from the current directory (where make was
@@ -75,6 +77,7 @@ else
 endif
 
 #-------------- Cross Compiler  ------------
+
 # Can be set by board, default to ARM GCC
 CROSS_COMPILE ?= arm-none-eabi-
 
diff --git a/hw/bsp/nrf/boards/pca10095/board.mk b/hw/bsp/nrf/boards/pca10095/board.mk
index 5ad103d62..9c4edbafc 100644
--- a/hw/bsp/nrf/boards/pca10095/board.mk
+++ b/hw/bsp/nrf/boards/pca10095/board.mk
@@ -1,3 +1,4 @@
+CPU_CORE = cortex-m33
 MCU_VARIANT = nrf5340_application
 CFLAGS += -DNRF5340_XXAA -DNRF5340_XXAA_APPLICATION
 
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index d5042a160..13258c9e0 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -3,13 +3,12 @@ DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/nordic/nrfx
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+CPU_CORE ?= cortex-m4
+
+include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
+
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -DCFG_TUSB_MCU=OPT_MCU_NRF5X \
   -DCONFIG_GPIO_AS_PINRESET
 
diff --git a/tools/make/cpu/cortex-m33.mk b/tools/make/cpu/cortex-m33.mk
new file mode 100644
index 000000000..cae8c6e3a
--- /dev/null
+++ b/tools/make/cpu/cortex-m33.mk
@@ -0,0 +1,11 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m33 \
+    -mfloat-abi=hard \
+    -mfpu=fpv5-d16 \
+
+  #set(FREERTOS_PORT GCC_ARM_CM33_NONSECURE CACHE INTERNAL "")
+else ifeq ($(TOOLCHAIN),iar)
+  # TODO support IAR
+endif
diff --git a/tools/make/cpu/cortex-m4.mk b/tools/make/cpu/cortex-m4.mk
new file mode 100644
index 000000000..7a3e204e2
--- /dev/null
+++ b/tools/make/cpu/cortex-m4.mk
@@ -0,0 +1,11 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m4 \
+    -mfloat-abi=hard \
+    -mfpu=fpv4-sp-d16 \
+
+  #set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
+else ifeq ($(TOOLCHAIN),iar)
+  # TODO support IAR
+endif
diff --git a/tools/make/cpu/cortex-m7.mk b/tools/make/cpu/cortex-m7.mk
new file mode 100644
index 000000000..47de4e07d
--- /dev/null
+++ b/tools/make/cpu/cortex-m7.mk
@@ -0,0 +1,11 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m7 \
+    -mfloat-abi=hard \
+    -mfpu=fpv5-d16 \
+
+  #set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
+else ifeq ($(TOOLCHAIN),iar)
+  # TODO support IAR
+endif

From 49d8d27770133ba4fe2f5d5798560e75df7824ce Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 May 2023 16:27:07 +0700
Subject: [PATCH 1738/2085] improve flash target

---
 examples/rules.mk           |  17 +-
 hw/bsp/family_support.cmake | 346 +++++++++++++++++++++---------------
 hw/bsp/imxrt/family.cmake   |  34 +---
 hw/bsp/lpc55/family.cmake   |  17 +-
 hw/bsp/nrf/family.cmake     |  21 +--
 5 files changed, 219 insertions(+), 216 deletions(-)

diff --git a/examples/rules.mk b/examples/rules.mk
index 426000128..f6422092a 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -227,14 +227,19 @@ endif
 # Jlink Interface
 JLINK_IF ?= swd
 
+# Jlink script
+define jlink_script
+halt
+loadfile $^
+r
+go
+exit
+endef
+export jlink_script
+
 # Flash using jlink
 flash-jlink: $(BUILD)/$(PROJECT).hex
-	@echo halt > $(BUILD)/$(BOARD).jlink
-	@echo r >> $(BUILD)/$(BOARD).jlink
-	@echo loadfile $^ >> $(BUILD)/$(BOARD).jlink
-	@echo r >> $(BUILD)/$(BOARD).jlink
-	@echo go >> $(BUILD)/$(BOARD).jlink
-	@echo exit >> $(BUILD)/$(BOARD).jlink
+	@echo "$$jlink_script" > $(BUILD)/$(BOARD).jlink
 	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
 
 # Flash STM32 MCU using stlink with STM32 Cube Programmer CLI
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 01e7bb018..442aba955 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -1,149 +1,205 @@
-if (NOT TARGET _family_support_marker)
-    add_library(_family_support_marker INTERFACE)
+if (TARGET _family_support_marker)
+    return()
+endif ()
 
-    include(CMakePrintHelpers)
+add_library(_family_support_marker INTERFACE)
 
-    # Default to gcc
-    if(NOT DEFINED TOOLCHAIN)
-        set(TOOLCHAIN gcc)
-    endif()
+include(CMakePrintHelpers)
 
-    if (NOT FAMILY)
-        message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line")
-    endif()
-
-    if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
-        message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
-    endif()
-
-    function(family_filter RESULT DIR)
-        get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
-
-        if (EXISTS "${DIR}/only.txt")
-            file(READ "${DIR}/only.txt" ONLYS)
-            # Replace newlines with semicolon so that it is treated as a list by CMake
-            string(REPLACE "\n" ";" ONLYS_LINES ${ONLYS})
-            # For each mcu
-            foreach(MCU IN LISTS FAMILY_MCUS)
-                # For each line in only.txt
-                foreach(_line ${ONLYS_LINES})
-                    # If mcu:xxx exists for this mcu or board:xxx then include
-                    if (${_line} STREQUAL "mcu:${MCU}" OR ${_line} STREQUAL "board:${BOARD}")
-                        set(${RESULT} 1 PARENT_SCOPE)
-                        return()
-                    endif()
-                endforeach()
-            endforeach()
-
-            # Didn't find it in only file so don't build
-            set(${RESULT} 0 PARENT_SCOPE)
-
-        elseif (EXISTS "${DIR}/skip.txt")
-            file(READ "${DIR}/skip.txt" SKIPS)
-            # Replace newlines with semicolon so that it is treated as a list by CMake
-            string(REPLACE "\n" ";" SKIPS_LINES ${SKIPS})
-            # For each mcu
-            foreach(MCU IN LISTS FAMILY_MCUS)
-                # For each line in only.txt
-                foreach(_line ${SKIPS_LINES})
-                    # If mcu:xxx exists for this mcu then skip
-                    if (${_line} STREQUAL "mcu:${MCU}")
-                        set(${RESULT} 0 PARENT_SCOPE)
-                        return()
-                    endif()
-                endforeach()
-            endforeach()
-
-            # Didn't find in skip file so build
-            set(${RESULT} 1 PARENT_SCOPE)
-
-        else()
-
-            # Didn't find skip or only file so build
-            set(${RESULT} 1 PARENT_SCOPE)
-
-        endif()
-
-    endfunction()
-
-    function(family_add_subdirectory DIR)
-        family_filter(SHOULD_ADD "${DIR}")
-        if (SHOULD_ADD)
-            add_subdirectory(${DIR})
-        endif()
-    endfunction()
-
-    function(family_get_project_name OUTPUT_NAME DIR)
-        get_filename_component(SHORT_NAME ${DIR} NAME)
-        set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
-    endfunction()
-
-    function(family_initialize_project PROJECT DIR)
-        family_filter(ALLOWED "${DIR}")
-        if (NOT ALLOWED)
-            get_filename_component(SHORT_NAME ${DIR} NAME)
-            message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
-        endif()
-    endfunction()
-
-    function(family_add_default_example_warnings TARGET)
-        target_compile_options(${TARGET} PUBLIC
-                -Wall
-                -Wextra
-                -Werror
-                -Wfatal-errors
-                -Wdouble-promotion
-                -Wfloat-equal
-                -Wshadow
-                -Wwrite-strings
-                -Wsign-compare
-                -Wmissing-format-attribute
-                -Wunreachable-code
-                -Wcast-align
-                -Wcast-qual
-                -Wnull-dereference
-                -Wuninitialized
-                -Wunused
-                -Wredundant-decls
-                #-Wstrict-prototypes
-                #-Werror-implicit-function-declaration
-                #-Wundef
-                )
-
-        if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-            # GCC 10
-            if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
-                target_compile_options(${TARGET} PUBLIC -Wconversion)
-            endif()
-
-            # GCC 8
-            if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
-                target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow)
-            endif()
-
-            # GCC 6
-            if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0)
-                target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing)
-            endif()
-        endif()
-    endfunction()
-
-    # configure an executable target to link to tinyusb in device mode, and add the board implementation
-    function(family_configure_device_example TARGET)
-        # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
-    endfunction()
-
-    # configure an executable target to link to tinyusb in host mode, and add the board implementation
-    function(family_configure_host_example TARGET)
-        # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
-    endfunction()
-
-    include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
-
-    if (NOT FAMILY_MCUS)
-        set(FAMILY_MCUS ${FAMILY})
-    endif()
-
-    # save it in case of re-inclusion
-    set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
+# Default to gcc
+if(NOT DEFINED TOOLCHAIN)
+    set(TOOLCHAIN gcc)
 endif()
+
+if (NOT FAMILY)
+    message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line")
+endif()
+
+if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
+    message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
+endif()
+
+function(family_filter RESULT DIR)
+    get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
+
+    if (EXISTS "${DIR}/only.txt")
+        file(READ "${DIR}/only.txt" ONLYS)
+        # Replace newlines with semicolon so that it is treated as a list by CMake
+        string(REPLACE "\n" ";" ONLYS_LINES ${ONLYS})
+        # For each mcu
+        foreach(MCU IN LISTS FAMILY_MCUS)
+            # For each line in only.txt
+            foreach(_line ${ONLYS_LINES})
+                # If mcu:xxx exists for this mcu or board:xxx then include
+                if (${_line} STREQUAL "mcu:${MCU}" OR ${_line} STREQUAL "board:${BOARD}")
+                    set(${RESULT} 1 PARENT_SCOPE)
+                    return()
+                endif()
+            endforeach()
+        endforeach()
+
+        # Didn't find it in only file so don't build
+        set(${RESULT} 0 PARENT_SCOPE)
+
+    elseif (EXISTS "${DIR}/skip.txt")
+        file(READ "${DIR}/skip.txt" SKIPS)
+        # Replace newlines with semicolon so that it is treated as a list by CMake
+        string(REPLACE "\n" ";" SKIPS_LINES ${SKIPS})
+        # For each mcu
+        foreach(MCU IN LISTS FAMILY_MCUS)
+            # For each line in only.txt
+            foreach(_line ${SKIPS_LINES})
+                # If mcu:xxx exists for this mcu then skip
+                if (${_line} STREQUAL "mcu:${MCU}")
+                    set(${RESULT} 0 PARENT_SCOPE)
+                    return()
+                endif()
+            endforeach()
+        endforeach()
+
+        # Didn't find in skip file so build
+        set(${RESULT} 1 PARENT_SCOPE)
+
+    else()
+
+        # Didn't find skip or only file so build
+        set(${RESULT} 1 PARENT_SCOPE)
+
+    endif()
+
+endfunction()
+
+function(family_add_subdirectory DIR)
+    family_filter(SHOULD_ADD "${DIR}")
+    if (SHOULD_ADD)
+        add_subdirectory(${DIR})
+    endif()
+endfunction()
+
+function(family_get_project_name OUTPUT_NAME DIR)
+    get_filename_component(SHORT_NAME ${DIR} NAME)
+    set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
+endfunction()
+
+function(family_initialize_project PROJECT DIR)
+    family_filter(ALLOWED "${DIR}")
+    if (NOT ALLOWED)
+        get_filename_component(SHORT_NAME ${DIR} NAME)
+        message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
+    endif()
+endfunction()
+
+function(family_add_default_example_warnings TARGET)
+    target_compile_options(${TARGET} PUBLIC
+            -Wall
+            -Wextra
+            -Werror
+            -Wfatal-errors
+            -Wdouble-promotion
+            -Wfloat-equal
+            -Wshadow
+            -Wwrite-strings
+            -Wsign-compare
+            -Wmissing-format-attribute
+            -Wunreachable-code
+            -Wcast-align
+            -Wcast-qual
+            -Wnull-dereference
+            -Wuninitialized
+            -Wunused
+            -Wredundant-decls
+            #-Wstrict-prototypes
+            #-Werror-implicit-function-declaration
+            #-Wundef
+            )
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+        if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0)
+            target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
+        endif()
+
+        # GCC 10
+        if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
+            target_compile_options(${TARGET} PUBLIC -Wconversion)
+        endif()
+
+        # GCC 8
+        if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
+            target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow)
+        endif()
+
+        # GCC 6
+        if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0)
+            target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing)
+        endif()
+    endif()
+endfunction()
+
+# Add flash jlink target
+function(family_flash_jlink TARGET)
+    if (NOT DEFINED JLINKEXE)
+        set(JLINKEXE JLinkExe)
+    endif ()
+
+    file(GENERATE
+      OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
+      CONTENT "halt
+loadfile $<TARGET_FILE:${TARGET}>
+r
+go
+exit"
+      )
+
+    add_custom_target(${TARGET}-jlink
+      DEPENDS ${TARGET}
+      COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
+      )
+endfunction()
+
+# Add flash pycod target
+function(family_flash_pyocd TARGET)
+    if (NOT DEFINED PYOC)
+        set(PYOCD pyocd)
+    endif ()
+
+    add_custom_target(${TARGET}-pyocd
+      DEPENDS ${TARGET}
+      COMMAND ${PYOCD} flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
+      )
+endfunction()
+
+# Add flash using NXP's LinkServer (redserver)
+# https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
+function(family_flash_nxplink TARGET)
+    if (NOT DEFINED LINKSERVER)
+        set(LINKSERVER LinkServer)
+    endif ()
+
+    # LinkServer has a bug that can only execute with full path otherwise it throws:
+    # realpath error: No such file or directory
+    execute_process(COMMAND which ${LINKSERVER} OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
+
+    add_custom_target(${TARGET}-nxplink
+      DEPENDS ${TARGET}
+      COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
+      )
+endfunction()
+
+# configure an executable target to link to tinyusb in device mode, and add the board implementation
+function(family_configure_device_example TARGET)
+    # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
+endfunction()
+
+# configure an executable target to link to tinyusb in host mode, and add the board implementation
+function(family_configure_host_example TARGET)
+    # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
+endfunction()
+
+include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
+
+if (NOT FAMILY_MCUS)
+    set(FAMILY_MCUS ${FAMILY})
+endif()
+
+# save it in case of re-inclusion
+set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index e9be7acc8..5261e5810 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -132,37 +132,9 @@ function(family_configure_target TARGET)
     )
 
   #---------- Flash ----------
-  # Flash using pyocd
-  add_custom_target(${TARGET}-pyocd
-    DEPENDS ${TARGET}
-    COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
-    )
-
-  # Flash using NXP LinkServer (redlink)
-  # https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
-  # LinkServer has a bug that can only execute with full path otherwise it throws:
-  # realpath error: No such file or directory
-  execute_process(COMMAND which LinkServer OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
-  add_custom_target(${TARGET}-nxplink
-    DEPENDS ${TARGET}
-    COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
-    )
-
-  # Flash using jlink
-  set(JLINKEXE JLinkExe)
-  file(GENERATE
-    OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
-    CONTENT "halt
-loadfile $<TARGET_FILE:${TARGET}>
-r
-go
-exit"
-    )
-  add_custom_target(${TARGET}-jlink
-    DEPENDS ${TARGET}
-    COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
-    )
-
+  family_flash_jlink(${TARGET})
+  family_flash_nxplink(${TARGET})
+  family_flash_pyocd(${TARGET})
 endfunction()
 
 
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 439f54170..611c88eb5 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -128,20 +128,9 @@ function(family_configure_target TARGET)
     )
 
   #---------- Flash ----------
-  # Flash using pyocd
-  add_custom_target(${TARGET}-pyocd
-    COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
-    )
-
-  # Flash using NXP LinkServer (redlink)
-  # https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
-  # LinkServer has a bug that can only execute with full path otherwise it throws:
-  # realpath error: No such file or directory
-  execute_process(COMMAND which LinkServer OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
-  add_custom_target(${TARGET}-nxplink
-    COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
-    )
-
+  family_flash_jlink(${TARGET})
+  family_flash_nxplink(${TARGET})
+  family_flash_pyocd(${TARGET})
 endfunction()
 
 
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index ca28c4f5d..9c43478e8 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -132,26 +132,7 @@ function(family_configure_target TARGET)
     )
 
   #---------- Flash ----------
-  # Flash using pyocd
-  add_custom_target(${TARGET}-pyocd
-    DEPENDS ${TARGET}
-    COMMAND pyocd flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
-    )
-
-  # Flash using jlink
-  set(JLINKEXE JLinkExe)
-  file(GENERATE
-    OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
-    CONTENT "halt
-loadfile $<TARGET_FILE:${TARGET}>
-r
-go
-exit"
-    )
-  add_custom_target(${TARGET}-jlink
-    DEPENDS ${TARGET}
-    COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
-    )
+  family_flash_jlink(${TARGET})
 
 endfunction()
 

From 9f0bae4c3fb687b8a3c1e6df84512ec48690369f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 19 May 2023 18:04:08 +0700
Subject: [PATCH 1739/2085] fix freertos build with nrf

---
 hw/bsp/nrf/family.mk         | 5 +----
 tools/make/cpu/cortex-m33.mk | 1 +
 tools/make/cpu/cortex-m4.mk  | 1 +
 tools/make/cpu/cortex-m7.mk  | 1 +
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index 13258c9e0..6d067e1c2 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -3,8 +3,8 @@ DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/nordic/nrfx
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# nRF52 is cortex-m4, nRF53 is cortex-m33
 CPU_CORE ?= cortex-m4
-
 include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
 
 CFLAGS += \
@@ -36,8 +36,5 @@ SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_$(MCU_VARIANT).S
 
 ASFLAGS += -D__HEAP_SIZE=0
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
 # For flash-jlink target
 JLINK_DEVICE ?= $(MCU_VARIANT)_xxaa
diff --git a/tools/make/cpu/cortex-m33.mk b/tools/make/cpu/cortex-m33.mk
index cae8c6e3a..2ea3a0753 100644
--- a/tools/make/cpu/cortex-m33.mk
+++ b/tools/make/cpu/cortex-m33.mk
@@ -6,6 +6,7 @@ ifeq ($(TOOLCHAIN),gcc)
     -mfpu=fpv5-d16 \
 
   #set(FREERTOS_PORT GCC_ARM_CM33_NONSECURE CACHE INTERNAL "")
+  FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
 else ifeq ($(TOOLCHAIN),iar)
   # TODO support IAR
 endif
diff --git a/tools/make/cpu/cortex-m4.mk b/tools/make/cpu/cortex-m4.mk
index 7a3e204e2..890feefe3 100644
--- a/tools/make/cpu/cortex-m4.mk
+++ b/tools/make/cpu/cortex-m4.mk
@@ -6,6 +6,7 @@ ifeq ($(TOOLCHAIN),gcc)
     -mfpu=fpv4-sp-d16 \
 
   #set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
+  FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 else ifeq ($(TOOLCHAIN),iar)
   # TODO support IAR
 endif
diff --git a/tools/make/cpu/cortex-m7.mk b/tools/make/cpu/cortex-m7.mk
index 47de4e07d..504ffd486 100644
--- a/tools/make/cpu/cortex-m7.mk
+++ b/tools/make/cpu/cortex-m7.mk
@@ -6,6 +6,7 @@ ifeq ($(TOOLCHAIN),gcc)
     -mfpu=fpv5-d16 \
 
   #set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
+  FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
 else ifeq ($(TOOLCHAIN),iar)
   # TODO support IAR
 endif

From 1ef820ecfe569e181b8f20cb936f632e51d8257e Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Tue, 23 May 2023 21:45:00 +0700
Subject: [PATCH 1740/2085] Enhance chipidea (#2075)

* update chipidea dcd, remove manual ep_count and use DCCPARAMS to get number of endpoint instead
* add dcd dcache for chipidea
* add cmake for lpc18
* add makefile build for mcx
* use fork of mcu sdk
* fix ci build with nrf
* flash rp2040 with openocd
---
 .github/workflows/build_arm.yml               |   3 +-
 .github/workflows/cmake_arm.yml               |   1 +
 .idea/cmake.xml                               |   7 +-
 .idea/runConfigurations/rt1010_jlink.xml      |  10 +
 .idea/runConfigurations/rt1010_nxplink.xml    |  10 -
 .idea/runConfigurations/rt1060_nxplink.xml    |  10 -
 .pre-commit-config.yaml                       |  16 +-
 examples/device/CMakeLists.txt                |   2 +-
 hw/bsp/board_mcu.h                            |   2 +-
 hw/bsp/family_support.cmake                   |   7 +
 hw/bsp/imxrt/family.cmake                     |  11 +-
 .../lpc18/boards/lpcxpresso18s37/board.cmake  |  11 +
 hw/bsp/lpc18/boards/mcb1800/board.cmake       |  11 +
 hw/bsp/lpc18/family.cmake                     | 155 ++++++++
 hw/bsp/lpc55/family.cmake                     |   6 +-
 hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h    | 166 +++++++++
 hw/bsp/mcx/boards/mcxn947brk/board.cmake      |  18 +
 hw/bsp/mcx/boards/mcxn947brk/board.h          |  66 ++++
 hw/bsp/mcx/boards/mcxn947brk/board.mk         |  11 +
 hw/bsp/mcx/boards/mcxn947brk/clock_config.c   | 338 ++++++++++++++++++
 hw/bsp/mcx/boards/mcxn947brk/clock_config.h   | 177 +++++++++
 hw/bsp/mcx/boards/mcxn947brk/pin_mux.c        | 141 ++++++++
 hw/bsp/mcx/boards/mcxn947brk/pin_mux.h        |  51 +++
 hw/bsp/mcx/family.c                           | 262 ++++++++++++++
 hw/bsp/mcx/family.cmake                       | 179 ++++++++++
 hw/bsp/mcx/family.mk                          |  48 +++
 hw/bsp/nrf/family.cmake                       |  11 +-
 src/common/tusb_mcu.h                         |  26 +-
 src/device/dcd.h                              |  16 +
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h     |  32 +-
 src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h  |   6 +-
 src/portable/chipidea/ci_hs/ci_hs_mcx.h       |  52 +++
 src/portable/chipidea/ci_hs/ci_hs_type.h      |  14 +-
 src/portable/chipidea/ci_hs/dcd_ci_hs.c       |  98 +++--
 src/portable/chipidea/ci_hs/hcd_ci_hs.c       |  21 +-
 src/portable/ehci/ehci.c                      |  13 +-
 src/tusb_option.h                             |   6 +-
 tools/cmake/cpu/cortex-m3.cmake               |  10 +
 tools/cmake/cpu/cortex-m33.cmake              |   5 +-
 tools/cmake/toolchain/arm_gcc.cmake           |   2 +
 tools/get_deps.py                             |   2 +-
 tools/make/cpu/cortex-m33.mk                  |   4 +-
 42 files changed, 1915 insertions(+), 122 deletions(-)
 create mode 100644 .idea/runConfigurations/rt1010_jlink.xml
 delete mode 100644 .idea/runConfigurations/rt1010_nxplink.xml
 delete mode 100644 .idea/runConfigurations/rt1060_nxplink.xml
 create mode 100644 hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
 create mode 100644 hw/bsp/lpc18/boards/mcb1800/board.cmake
 create mode 100644 hw/bsp/lpc18/family.cmake
 create mode 100644 hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/board.cmake
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/board.h
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/board.mk
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/clock_config.c
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/clock_config.h
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
 create mode 100644 hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
 create mode 100644 hw/bsp/mcx/family.c
 create mode 100644 hw/bsp/mcx/family.cmake
 create mode 100644 hw/bsp/mcx/family.mk
 create mode 100644 src/portable/chipidea/ci_hs/ci_hs_mcx.h
 create mode 100644 tools/cmake/cpu/cortex-m3.cmake

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index f0b01b43d..917c83d74 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -142,8 +142,7 @@ jobs:
 
     - name: Create flash.sh
       run: |
-        #echo > flash.sh 'cmdout=$(openocd -f "interface/picoprobe.cfg" -f "target/rp2040.cfg" -c "program $1 reset exit")'
-        echo > flash.sh 'pyocd flash -t rp2040 $1'
+        echo > flash.sh 'cmdout=$(openocd -f "interface/cmsis-dap.cfg" -f "target/rp2040.cfg" -c "adapter speed 5000" -c "program $1 reset exit")'
         echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
         chmod +x flash.sh
 
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 844a03443..12173fb63 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -32,6 +32,7 @@ jobs:
       matrix:
         family:
         # Alphabetical order
+        - 'mcx'
         - 'imxrt'
     steps:
     - name: Setup Python
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 7dacd0003..a80ebed3c 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,8 +2,9 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="rt1060 evk" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1060_evk" />
-      <configuration PROFILE_NAME="pca10095" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095" BUILD_OPTIONS="-v" />
+      <configuration PROFILE_NAME="mcxn947" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=mcx -DBOARD=mcxn947brk" />
+      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1060_evk" />
+      <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" BUILD_OPTIONS="-v" />
       <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc55 -DBOARD=lpcxpresso55s69" />
       <configuration PROFILE_NAME="esp32s3" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_s3_devkitm -DIDF_TARGET=esp32s3">
@@ -29,6 +30,8 @@
       <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=rp2040 -DBOARD=raspberry_pi_pico" />
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1010_evk" />
       <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1064_evk" />
+      <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=mcb1800" />
+      <configuration PROFILE_NAME="lpcxpresso18s37" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=lpcxpresso18s37" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010_jlink.xml b/.idea/runConfigurations/rt1010_jlink.xml
new file mode 100644
index 000000000..70cfeea53
--- /dev/null
+++ b/.idea/runConfigurations/rt1010_jlink.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt1010 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcxn947" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010_nxplink.xml b/.idea/runConfigurations/rt1010_nxplink.xml
deleted file mode 100644
index cf3bf842f..000000000
--- a/.idea/runConfigurations/rt1010_nxplink.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1010 nxplink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver --gdb-port 55503 --semihost-port -1 MIMXRT1011xxxxx:EVK-MIMXRT1010" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="host_hid_to_device_cdc" TARGET_NAME="host_hid_to_device_cdc" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="host_hid_to_device_cdc" RUN_TARGET_NAME="host_hid_to_device_cdc">
-    <custom-gdb-server version="1" gdb-connect="tcp::55503" executable="/usr/local/LinkServer/LinkServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
-      <debugger kind="GDB" isBundled="true" />
-    </custom-gdb-server>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1060_nxplink.xml b/.idea/runConfigurations/rt1060_nxplink.xml
deleted file mode 100644
index d3303bdb6..000000000
--- a/.idea/runConfigurations/rt1060_nxplink.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1060 nxplink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="gdbserver --gdb-port 55503 --semihost-port -1 MIMXRT1062xxxxA:EVK-MIMXRT1060" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc_hid" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc_hid" RUN_TARGET_NAME="cdc_msc_hid">
-    <custom-gdb-server version="1" gdb-connect="tcp::55503" executable="/usr/local/LinkServer/LinkServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
-      <debugger kind="GDB" isBundled="true" />
-    </custom-gdb-server>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml
index 6fb98afb8..4071ec326 100644
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@@ -8,8 +8,16 @@ repos:
   hooks:
   - id: check-yaml
   - id: trailing-whitespace
+    exclude: |
+      (?x)^(
+        hw/bsp/mcx/sdk/
+      )
   - id: end-of-file-fixer
-    exclude: ^.idea/
+    exclude: |
+      (?x)^(
+        .idea/|
+        hw/bsp/mcx/sdk/
+      )
   - id: forbid-submodules
 
 - repo: https://github.com/codespell-project/codespell
@@ -17,7 +25,11 @@ repos:
   hooks:
   - id: codespell
     args: [-w]
-    exclude: ^lib/
+    exclude: |
+      (?x)^(
+        lib/|
+        hw/bsp/mcx/sdk/
+      )
 
 - repo: local
   hooks:
diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index 10a1f4c26..89cfceeeb 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -24,7 +24,7 @@ family_add_subdirectory(midi_test)
 family_add_subdirectory(msc_dual_lun)
 
 # FIXME temp skip net_lwip_webserver for imxrt for now
-if (NOT ${FAMILY} STREQUAL "imxrt")
+if (NOT ${FAMILY} STREQUAL "imxrt" AND NOT ${FAMILY} STREQUAL "mcx")
   family_add_subdirectory(net_lwip_webserver)
 endif()
 
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index cd195a19b..35210dbae 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -44,7 +44,7 @@
       TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX)
   #include "chip.h"
 
-#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9)
   #include "fsl_device_registers.h"
 
 #elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32)
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 442aba955..d2d675332 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -135,6 +135,13 @@ function(family_add_default_example_warnings TARGET)
     endif()
 endfunction()
 
+
+#  add_custom_command(TARGET ${TARGET} POST_BUILD
+#    COMMAND ${CMAKE_OBJCOPY} -O ihex $<TARGET_FILE:${TARGET}> ${TARGET}.hex
+#    COMMAND ${CMAKE_OBJCOPY} -O binary $<TARGET_FILE:${TARGET}> ${TARGET}.bin
+#    COMMENT "Creating ${TARGET}.hex and ${TARGET}.bin"
+#    )
+
 # Add flash jlink target
 function(family_flash_jlink TARGET)
     if (NOT DEFINED JLINKEXE)
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 5261e5810..ade744aa5 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -1,8 +1,4 @@
-if (TARGET _imxrt_family_inclusion_marker)
-  return()
-endif ()
-
-add_library(_imxrt_family_inclusion_marker INTERFACE)
+include_guard()
 
 if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
@@ -87,6 +83,11 @@ function(family_configure_target TARGET)
   # set output name to .elf
   set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
 
+  # run size after build
+  add_custom_command(TARGET ${TARGET} POST_BUILD
+    COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
+    )
+
   # TOP is path to root directory
   set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
 
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
new file mode 100644
index 000000000..b540012a4
--- /dev/null
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC18S37)
+
+set(JLINK_DEVICE LPC18S37)
+set(PYOCD_TARGET LPC18S37)
+set(NXPLINK_DEVICE LPC18S37:LPCXPRESSO18S37)
+
+set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld)
+
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.cmake b/hw/bsp/lpc18/boards/mcb1800/board.cmake
new file mode 100644
index 000000000..1efeafd12
--- /dev/null
+++ b/hw/bsp/lpc18/boards/mcb1800/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC1857)
+
+set(JLINK_DEVICE LPC1857)
+set(PYOCD_TARGET LPC1857)
+set(NXPLINK_DEVICE LPC1857:MCB1857)
+
+set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld)
+
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
new file mode 100644
index 000000000..059408fe9
--- /dev/null
+++ b/hw/bsp/lpc18/family.cmake
@@ -0,0 +1,155 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+# TOP is path to root directory
+set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+set(BOARD_TARGET board_${BOARD})
+if (NOT TARGET ${BOARD_TARGET})
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/../gcc/cr_startup_lpc18xx.c
+    ${SDK_DIR}/src/chip_18xx_43xx.c
+    ${SDK_DIR}/src/clock_18xx_43xx.c
+    ${SDK_DIR}/src/gpio_18xx_43xx.c
+    ${SDK_DIR}/src/sysinit_18xx_43xx.c
+    ${SDK_DIR}/src/uart_18xx_43xx.c
+    )
+  target_compile_options(${BOARD_TARGET} PUBLIC
+    -nostdlib
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    CORE_M3
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${SDK_DIR}/inc/config_18xx
+    )
+  update_board(${BOARD_TARGET})
+
+  if (NOT DEFINED LD_FILE_${TOOLCHAIN})
+    MESSAGE(FATAL_ERROR "LD_FILE_${TOOLCHAIN} not defined")
+  endif ()
+
+  if (TOOLCHAIN STREQUAL "gcc")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_gcc}"
+      "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  else ()
+    # TODO support IAR
+  endif ()
+endif () # BOARD_TARGET
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_target TARGET)
+  # set output name to .elf
+  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+
+  # run size after build
+  add_custom_command(TARGET ${TARGET} POST_BUILD
+    COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
+    )
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # TinyUSB Port
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+    ${TOP}/src/portable/ehci/ehci.c
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  #---------- TinyUSB ----------
+  # tinyusb target is built for each example since it depends on example's tusb_config.h
+  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+  add_library(${TARGET}-tinyusb_config INTERFACE)
+
+  target_include_directories(${TARGET}-tinyusb_config INTERFACE
+    ${CMAKE_CURRENT_SOURCE_DIR}/src
+    )
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_MCU=OPT_MCU_LPC18XX
+    )
+
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+
+  # group target (not yet supported by clion)
+  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
+    PROPERTIES FOLDER ${TARGET}_sub
+    )
+
+  #---------- Flash ----------
+  family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(family_add_freertos TARGET)
+  # freertos_config
+  add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config)
+
+  ## freertos
+  if (NOT TARGET freertos_kernel)
+    add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
+  endif ()
+
+  # Add FreeRTOS option to tinyusb_config
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_OS=OPT_OS_FREERTOS
+    )
+  # link tinyusb with freeRTOS kernel
+  target_link_libraries(${TARGET}-tinyusb PUBLIC
+    freertos_kernel
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    freertos_kernel
+    )
+endfunction()
+
+function(family_configure_device_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 611c88eb5..3aeda5b2d 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -1,8 +1,4 @@
-if (TARGET _lpc55_family_inclusion_marker)
-  return()
-endif ()
-
-add_library(_lpc55_family_inclusion_marker INTERFACE)
+include_guard()
 
 if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..4c6058d27
--- /dev/null
+++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// IAR assembler have limited preprocessor support and it only need following macros:
+#ifndef __IASMARM__
+// FIXME cause redundant-decls warnings
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU								        0
+#define configENABLE_FPU								        1
+#define configENABLE_TRUSTZONE					        0
+#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
new file mode 100644
index 000000000..b9acf04d9
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
@@ -0,0 +1,18 @@
+set(MCU_VARIANT MCXN947)
+set(MCU_CORE MCXN947_cm33_core0)
+
+set(JLINK_DEVICE MCXN947)
+set(PYOCD_TARGET MCXN947)
+set(NXPLINK_DEVICE MCXN947:MCXN947)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MCXN947VDF_cm33_core0
+    # port 1 is highspeed
+    BOARD_TUD_RHPORT=1
+    )
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
+    )
+endfunction()
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.h b/hw/bsp/mcx/boards/mcxn947brk/board.h
new file mode 100644
index 000000000..eae98bfa7
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.h
@@ -0,0 +1,66 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_GPIO              GPIO3
+#define LED_CLK               kCLOCK_Gpio3
+#define LED_PIN               4 // red
+#define LED_STATE_ON          0
+
+// WAKE button (Dummy, use unused pin
+#define BUTTON_GPIO           GPIO0
+#define BUTTON_CLK            kCLOCK_Gpio0
+#define BUTTON_PIN            6
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              LPUART4
+
+static inline void board_uart_init_clock(void) {
+  /* attach FRO 12M to FLEXCOMM4 */
+  CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
+  CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+  RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
+}
+
+//#define UART_RX_PINMUX        0, 24, IOCON_PIO_DIG_FUNC1_EN
+//#define UART_TX_PINMUX        0, 25, IOCON_PIO_DIG_FUNC1_EN
+
+// XTAL
+#define XTAL0_CLK_HZ          (24 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk
new file mode 100644
index 000000000..69f47b8a8
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk
@@ -0,0 +1,11 @@
+MCU_VARIANT = MCXN947
+MCU_CORE = MCXN947_cm33_core0
+PORT ?= 1
+
+CFLAGS += -DCPU_MCXN947VDF_cm33_core0
+
+JLINK_DEVICE = LPC55S69
+PYOCD_TARGET = LPC55S69
+
+# flash using pyocd
+flash: flash-pyocd
diff --git a/hw/bsp/mcx/boards/mcxn947brk/clock_config.c b/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
new file mode 100644
index 000000000..37d2b4dfc
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/clock_config.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v10.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+board: MCX-N9XX-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "clock_config.h"
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+// extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL150M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: Slow_clock.outFreq, value: 3 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF144M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 144 MHz}
+- {id: MAIN_clock.outFreq, value: 144 MHz}
+- {id: Slow_clock.outFreq, value: 18 MHz}
+- {id: System_clock.outFreq, value: 72 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.FIRC.outFreq, value: 144 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF144M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(144000000U);               /*!< Enable FRO HF(144MHz) output */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U);           /*!< Set AHBCLKDIV divider to value 2 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL150M
+called_from_default_init: true
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 150 MHz}
+- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
+- {id: Slow_clock.outFreq, value: 37.5 MHz}
+- {id: System_clock.outFreq, value: 150 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL0_Mode, value: Normal}
+- {id: RunPowerMode, value: OD}
+- {id: SCGMode, value: PLL0}
+- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
+- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
+- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
+- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL150M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupFROHFClocking(48000000U);                /*!< Enable FRO HF(48MHz) output */
+
+    /*!< Set up PLL0 */
+    const pll_setup_t pll0Setup = {
+        .pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
+        .pllndiv = SCG_APLLNDIV_NDIV(8U),
+        .pllpdiv = SCG_APLLPDIV_PDIV(1U),
+        .pllmdiv = SCG_APLLMDIV_MDIV(50U),
+        .pllRate = 150000000U
+    };
+    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */
+    CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);    /* Pll0 Monitor is disabled */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL100M
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: CLK_IN_clock.outFreq, value: 24 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: MAIN_clock.outFreq, value: 100 MHz}
+- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
+- {id: Slow_clock.outFreq, value: 25 MHz}
+- {id: System_clock.outFreq, value: 100 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+settings:
+- {id: PLL1_Mode, value: Normal}
+- {id: SCGMode, value: PLL1}
+- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
+- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
+- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
+- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
+- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
+- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
+- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
+sources:
+- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL100M(void)
+{
+    /*!< Enable SCG clock */
+    CLOCK_EnableClock(kCLOCK_Scg);
+
+    CLOCK_SetupExtClocking(24000000U);
+    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);    /* System OSC Clock Monitor is disabled */
+
+    /*!< Set up PLL1 */
+    const pll_setup_t pll1Setup = {
+        .pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
+        .pllndiv = SCG_SPLLNDIV_NDIV(6U),
+        .pllpdiv = SCG_SPLLPDIV_PDIV(2U),
+        .pllmdiv = SCG_SPLLMDIV_MDIV(100U),
+        .pllRate = 100000000U
+    };
+    CLOCK_SetPLL1Freq(&pll1Setup);                       /*!< Configure PLL1 to the desired values */
+    CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);    /* Pll1 Monitor is disabled */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);           /*!< Set AHBCLKDIV divider to value 1 */
+
+    /* Set SystemCoreClock variable */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
+}
diff --git a/hw/bsp/mcx/boards/mcxn947brk/clock_config.h b/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
new file mode 100644
index 000000000..c238a0423
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/clock_config.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK           12000000U  /*!< Core clock frequency: 12000000Hz */
+#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK                  0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK         48000000U  /*!< Core clock frequency: 48000000Hz */
+#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK                0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF144M ********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK       144000000U  /*!< Core clock frequency: 144000000Hz */
+#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK               0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF144M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF144M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL150M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK         150000000U  /*!< Core clock frequency: 150000000Hz */
+#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL150M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL150M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL100M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK         100000000U  /*!< Core clock frequency: 100000000Hz */
+#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK                 0U  /*!< ROSC clock frequency: 0Hz */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL100M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL100M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
new file mode 100644
index 000000000..acc2f3e45
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v12.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 0.12.3
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+    BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
+    invert_input: normal}
+  - {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
+    slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
+  - {pin_num: F14, peripheral: GPIO3, signal: 'GPIO, 4', pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, slew_rate: fast, open_drain: disable, drive_strength: low,
+    pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+    /* Enables the clock for PORT1: Enables clock */
+    CLOCK_EnableClock(kCLOCK_Port1);
+    /* Enables the clock for PORT3: Enables clock */
+    CLOCK_EnableClock(kCLOCK_Port3);
+
+    const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
+                                                    kPORT_PullDisable,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Pin is configured as FC4_P0 */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT1_8 (pin A1) is configured as FC4_P0 */
+    PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
+
+    const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
+                                                    kPORT_PullDisable,
+                                                    /* Low internal pull resistor value is selected. */
+                                                    kPORT_LowPullResistor,
+                                                    /* Fast slew rate is configured */
+                                                    kPORT_FastSlewRate,
+                                                    /* Passive input filter is disabled */
+                                                    kPORT_PassiveFilterDisable,
+                                                    /* Open drain output is disabled */
+                                                    kPORT_OpenDrainDisable,
+                                                    /* Low drive strength is configured */
+                                                    kPORT_LowDriveStrength,
+                                                    /* Pin is configured as FC4_P1 */
+                                                    kPORT_MuxAlt2,
+                                                    /* Digital input enabled */
+                                                    kPORT_InputBufferEnable,
+                                                    /* Digital input is not inverted */
+                                                    kPORT_InputNormal,
+                                                    /* Pin Control Register fields [15:0] are not locked */
+                                                    kPORT_UnlockRegister};
+    /* PORT1_9 (pin B1) is configured as FC4_P1 */
+    PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
+
+    const port_pin_config_t port3_4_pinF14_config = {/* Internal pull-up/down resistor is disabled */
+                                                     kPORT_PullDisable,
+                                                     /* Low internal pull resistor value is selected. */
+                                                     kPORT_LowPullResistor,
+                                                     /* Fast slew rate is configured */
+                                                     kPORT_FastSlewRate,
+                                                     /* Passive input filter is disabled */
+                                                     kPORT_PassiveFilterDisable,
+                                                     /* Open drain output is disabled */
+                                                     kPORT_OpenDrainDisable,
+                                                     /* Low drive strength is configured */
+                                                     kPORT_LowDriveStrength,
+                                                     /* Pin is configured as PIO3_4 */
+                                                     kPORT_MuxAlt0,
+                                                     /* Digital input enabled */
+                                                     kPORT_InputBufferEnable,
+                                                     /* Digital input is not inverted */
+                                                     kPORT_InputNormal,
+                                                     /* Pin Control Register fields [15:0] are not locked */
+                                                     kPORT_UnlockRegister};
+    /* PORT3_4 (pin F14) is configured as PIO3_4 */
+    PORT_SetPinConfig(PORT3, 4U, &port3_4_pinF14_config);
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
new file mode 100644
index 000000000..40968c275
--- /dev/null
+++ b/hw/bsp/mcx/boards/mcxn947brk/pin_mux.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
new file mode 100644
index 000000000..36d2f2d0a
--- /dev/null
+++ b/hw/bsp/mcx/family.c
@@ -0,0 +1,262 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018, hathach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "bsp/board.h"
+#include "fsl_device_registers.h"
+#include "fsl_gpio.h"
+#include "fsl_lpuart.h"
+#include "board.h"
+
+#include "pin_mux.h"
+#include "clock_config.h"
+
+#ifdef BOARD_TUD_RHPORT
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#ifdef BOARD_TUH_RHPORT
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB0_FS_IRQHandler(void)
+{
+  tud_int_handler(0);
+}
+
+void USB1_HS_IRQHandler(void)
+{
+  tud_int_handler(1);
+}
+
+void board_init(void)
+{
+  BOARD_InitPins();
+  BOARD_InitBootClocks();
+
+  // 1ms tick timer
+  SysTick_Config(SystemCoreClock / 1000);
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(USB1_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
+#endif
+
+  // LED
+  CLOCK_EnableClock(LED_CLK);
+  gpio_pin_config_t led_config = {
+      kGPIO_DigitalOutput,
+      0,
+  };
+  GPIO_PinInit(LED_GPIO,LED_PIN, &led_config);
+  board_led_write(0);
+
+#ifdef NEOPIXEL_PIN
+  // Neopixel
+  static uint32_t pixelData[NEOPIXEL_NUMBER];
+  IOCON_PinMuxSet(IOCON, NEOPIXEL_PORT, NEOPIXEL_PIN, IOCON_PIO_DIG_FUNC4_EN);
+
+  sctpix_init(NEOPIXEL_TYPE);
+  sctpix_addCh(NEOPIXEL_CH, pixelData, NEOPIXEL_NUMBER);
+  sctpix_setPixel(NEOPIXEL_CH, 0, 0x100010);
+  sctpix_setPixel(NEOPIXEL_CH, 1, 0x100010);
+  sctpix_show();
+#endif
+
+  // Button
+#ifdef BUTTON_GPIO
+  CLOCK_EnableClock(BUTTON_CLK);
+  gpio_pin_config_t const button_config = { kGPIO_DigitalInput, 0};
+  GPIO_PinInit(BUTTON_GPIO, BUTTON_PIN, &button_config);
+#endif
+
+#ifdef UART_DEV
+  // UART
+//  IOCON_PinMuxSet(IOCON, UART_RX_PINMUX);
+//  IOCON_PinMuxSet(IOCON, UART_TX_PINMUX);
+
+  // Enable UART when debug log is on
+  board_uart_init_clock();
+
+  lpuart_config_t uart_config;
+  LPUART_GetDefaultConfig(&uart_config);
+  uart_config.baudRate_Bps = CFG_BOARD_UART_BAUDRATE;
+  uart_config.enableTx     = true;
+  uart_config.enableRx     = true;
+  LPUART_Init(UART_DEV, &uart_config, 12000000u);
+#endif
+
+  // USB VBUS
+  /* PORT0 PIN22 configured as USB0_VBUS */
+
+  CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
+
+#if PORT_SUPPORT_DEVICE(0)
+  // Port0 is Full Speed
+
+  /* Turn on USB0 Phy */
+  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
+
+  /* reset the IP to make sure it's in reset state. */
+  RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn);
+  RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn);
+
+  // Enable USB Clock Adjustments to trim the FRO for the full speed controller
+  ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
+  CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
+  CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
+
+  /*According to reference manual, device mode setting has to be set by access usb host register */
+  CLOCK_EnableClock(kCLOCK_Usbhsl0);  // enable usb0 host clock
+  USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
+  CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
+
+  /* enable USB Device clock */
+  CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
+#endif
+
+#if PORT_SUPPORT_DEVICE(1)
+  // Port1 is High Speed
+
+  // Power
+  SPC0->ACTIVE_VDELAY = 0x0500;
+  /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, CORELDO is 1.0V) */
+  SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
+  SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
+                      SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
+  /* Wait until it is done */
+  while (SPC0->SC & SPC_SC_BUSY_MASK) {}
+  if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
+    SCG0->TRIM_LOCK = 0x5a5a0001U;
+    SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+    /* wait LDO ready */
+    while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK));
+  }
+  SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
+  SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
+  /* xtal = 20 ~ 30MHz */
+  SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
+  SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
+  while (1) {
+    if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
+      break;
+    }
+  }
+
+  // Clock
+  SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
+  CLOCK_EnableClock(kCLOCK_UsbHs);
+  CLOCK_EnableClock(kCLOCK_UsbHsPhy);
+  CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U);
+  CLOCK_EnableUsbhsClock();
+
+  // USB PHY
+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
+  USBPHY->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
+#endif
+
+  // Enable PHY support for Low speed device + LS via FS Hub
+  USBPHY->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK;
+
+  // Enable all power for normal operation
+  USBPHY->PWD = 0;
+
+  // TX Timing
+  uint32_t phytx = USBPHY->TX;
+  phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK);
+  phytx |= USBPHY_TX_D_CAL(0x04) | USBPHY_TX_TXCAL45DP(0x07) | USBPHY_TX_TXCAL45DM(0x07);
+  //phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
+  USBPHY->TX = phytx;
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_led_write(bool state)
+{
+  GPIO_PinWrite(LED_GPIO, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+
+#ifdef NEOPIXEL_PIN
+  if (state) {
+    sctpix_setPixel(NEOPIXEL_CH, 0, 0x100000);
+    sctpix_setPixel(NEOPIXEL_CH, 1, 0x101010);
+  } else {
+    sctpix_setPixel(NEOPIXEL_CH, 0, 0x001000);
+    sctpix_setPixel(NEOPIXEL_CH, 1, 0x000010);
+  }
+  sctpix_show();
+#endif
+}
+
+uint32_t board_button_read(void)
+{
+#ifdef BUTTON_GPIO
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_GPIO, BUTTON_PIN);
+#endif
+}
+
+int board_uart_read(uint8_t* buf, int len)
+{
+  (void) buf; (void) len;
+  return 0;
+}
+
+int board_uart_write(void const * buf, int len)
+{
+#ifdef UART_DEV
+  LPUART_WriteBlocking(UART_DEV, (uint8_t const *) buf, len);
+  return len;
+#else
+  (void) buf; (void) len;
+  return 0;
+#endif
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+void SysTick_Handler(void)
+{
+  system_ticks++;
+}
+
+uint32_t board_millis(void)
+{
+  return system_ticks;
+}
+#endif
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
new file mode 100644
index 000000000..e4bc11be5
--- /dev/null
+++ b/hw/bsp/mcx/family.cmake
@@ -0,0 +1,179 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+# TOP is path to root directory
+set(TOP ${CMAKE_CURRENT_LIST_DIR}/../../..)
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+set(BOARD_TARGET board_${BOARD})
+if (NOT TARGET ${BOARD_TARGET})
+  add_library(${BOARD_TARGET} STATIC
+    # external driver
+    #lib/sct_neopixel/sct_neopixel.c
+
+    # driver
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+    )
+#  target_compile_definitions(${BOARD_TARGET} PUBLIC
+#    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    # driver
+    # mcu
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    )
+  update_board(${BOARD_TARGET})
+
+  if (TOOLCHAIN STREQUAL "gcc")
+    target_sources(${BOARD_TARGET} PUBLIC
+      ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      # linker file
+      "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
+      # link map
+      "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  else ()
+    # TODO support IAR
+  endif ()
+endif () # BOARD_TARGET
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_target TARGET)
+  # set output name to .elf
+  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+
+  # run size after build
+  add_custom_command(TARGET ${TARGET} POST_BUILD
+    COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
+    )
+
+  # TOP is path to root directory
+  set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # TinyUSB Port
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  #---------- TinyUSB ----------
+  # tinyusb target is built for each example since it depends on example's tusb_config.h
+  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+  add_library(${TARGET}-tinyusb_config INTERFACE)
+
+  target_include_directories(${TARGET}-tinyusb_config INTERFACE
+    ${CMAKE_CURRENT_SOURCE_DIR}/src
+    )
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_MCU=OPT_MCU_MCXN9
+    )
+
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+
+  # group target (not yet supported by clion)
+  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
+    PROPERTIES FOLDER ${TARGET}_sub
+    )
+
+  #---------- Flash ----------
+  # use MCUXpresso GUI Flash Tool to flash the elf
+
+#  set(REDLINK_EXE /usr/local/LinkServer/binaries/crt_emu_cm_redlink)
+#  add_custom_target(${TARGET}-redlink
+#    DEPENDS ${TARGET}
+#    COMMAND ${REDLINK_EXE} --flash-load-exec $<TARGET_FILE:${TARGET}> --vendor NXP -p MCXN947 --bootromstall
+#    0x50000040 -CoreIndex=0 --flash-driver= -x ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash --flash-dir
+#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash --flash-hashing
+#    )
+
+  #family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
+
+
+function(family_add_freertos TARGET)
+  # freertos_config
+  if (NOT TARGET freertos_config)
+    add_library(freertos_config INTERFACE)
+    target_include_directories(freertos_config SYSTEM INTERFACE
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig
+      )
+  endif()
+
+  ## freertos
+  if (NOT TARGET freertos_kernel)
+    add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
+  endif ()
+
+  # Add FreeRTOS option to tinyusb_config
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_OS=OPT_OS_FREERTOS
+    )
+  # link tinyusb with freeRTOS kernel
+  target_link_libraries(${TARGET}-tinyusb PUBLIC
+    freertos_kernel
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    freertos_kernel
+    )
+endfunction()
+
+function(family_configure_device_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_target(${TARGET})
+endfunction()
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
new file mode 100644
index 000000000..2cd4c2448
--- /dev/null
+++ b/hw/bsp/mcx/family.mk
@@ -0,0 +1,48 @@
+UF2_FAMILY_ID = 0x2abc77ec
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
+
+include $(TOP)/$(BOARD_PATH)/board.mk
+
+CPU_CORE ?= cortex-m33
+include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
+
+# Default to Highspeed PORT1
+PORT ?= 1
+
+CFLAGS += \
+  -flto \
+  -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
+  -DBOARD_TUD_RHPORT=$(PORT) \
+
+ifeq ($(PORT), 1)
+  $(info "PORT1 High Speed")
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+else
+  $(info "PORT0 Full Speed")
+endif
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
+
+# All source paths should be relative to the top level.
+LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
+
+SRC_C += \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_gpio.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_common_arm.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpflexcomm.c \
+	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_lpuart.c \
+
+INC += \
+	$(TOP)/$(BOARD_PATH) \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
+	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
+	$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
+
+SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 9c43478e8..1156a171b 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -1,8 +1,4 @@
-if (TARGET _nrf_family_inclusion_marker)
-  return()
-endif ()
-
-add_library(_nrf_family_inclusion_marker INTERFACE)
+include_guard()
 
 if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
@@ -89,6 +85,11 @@ function(family_configure_target TARGET)
   # set output name to .elf
   set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
 
+  # run size after build
+  add_custom_command(TARGET ${TARGET} POST_BUILD
+    COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
+    )
+
   # TOP is path to root directory
   set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
 
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index ba8976a8c..9c2933983 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -59,14 +59,6 @@
   #define TUP_USBIP_OHCI
   #define TUP_OHCI_RHPORTS        2
 
-#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
-  // TODO USB0 has 6, USB1 has 4
-  #define TUP_USBIP_CHIPIDEA_HS
-  #define TUP_USBIP_EHCI
-
-  #define TUP_DCD_ENDPOINT_MAX    6
-  #define TUP_RHPORT_HIGHSPEED    1 // Port0 HS, Port1 FS
-
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
    #define TUP_DCD_ENDPOINT_MAX   5
 
@@ -78,12 +70,28 @@
   // TODO USB0 has 5, USB1 has 6
   #define TUP_DCD_ENDPOINT_MAX    6
 
+#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
+  // USB0 has 6 with HS PHY, USB1 has 4 only FS
+  #define TUP_USBIP_CHIPIDEA_HS
+  #define TUP_USBIP_EHCI
+
+  #define TUP_DCD_ENDPOINT_MAX    6
+  #define TUP_RHPORT_HIGHSPEED    1
+
+#elif TU_CHECK_MCU(OPT_MCU_MCXN9)
+  // NOTE: MCXN943 port 1 use chipidea HS, port 0 use chipidea FS
+  #define TUP_USBIP_CHIPIDEA_HS
+  #define TUP_USBIP_EHCI
+
+  #define TUP_DCD_ENDPOINT_MAX    8
+  #define TUP_RHPORT_HIGHSPEED    1
+
 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT)
   #define TUP_USBIP_CHIPIDEA_HS
   #define TUP_USBIP_EHCI
 
   #define TUP_DCD_ENDPOINT_MAX    8
-  #define TUP_RHPORT_HIGHSPEED    1 // Port0 HS, Port1 HS
+  #define TUP_RHPORT_HIGHSPEED    1
 
 #elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32)
   #define TUP_USBIP_CHIPIDEA_FS
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 00419ff05..f82b8633d 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -102,6 +102,22 @@ typedef struct TU_ATTR_ALIGNED(4)
 
 //TU_VERIFY_STATIC(sizeof(dcd_event_t) <= 12, "size is not correct");
 
+//--------------------------------------------------------------------+
+// Memory API
+//--------------------------------------------------------------------+
+
+// clean/flush data cache: write cache -> memory.
+// Required before an DMA TX transfer to make sure data is in memory
+void dcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+
+// invalidate data cache: mark cache as invalid, next read will read from memory
+// Required BOTH before and after an DMA RX transfer
+void dcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+
+// clean and invalidate data cache
+// Required before an DMA transfer where memory is both read/write by DMA
+void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index 607926a65..ceff893bd 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -46,18 +46,44 @@ static const ci_hs_controller_t _ci_controller[] =
 {
   // RT1010 and RT1020 only has 1 USB controller
   #if FSL_FEATURE_SOC_USBHS_COUNT == 1
-    { .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
+    { .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn }
   #else
-    { .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
-    { .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
+    { .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn},
+    { .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn}
   #endif
 };
 
+#define CI_HS_REG(_port)        ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
+
+//------------- DCD -------------//
 #define CI_DCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
 #define CI_DCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
 
+//------------- HCD -------------//
 #define CI_HCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
 #define CI_HCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
 
+//------------- DCache -------------//
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uint32_t addr) {
+  return !(0x20000000 <= addr && addr < 0x20100000);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void* addr, uint32_t data_size) {
+  if (imxrt_is_cache_mem((uint32_t) addr)) {
+    SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size);
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void* addr, uint32_t data_size) {
+  if (imxrt_is_cache_mem((uint32_t) addr)) {
+    SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+  if (imxrt_is_cache_mem((uint32_t) addr)) {
+    SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
+  }
+}
 
 #endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
index 8c2e7dfa6..2e84c93e7 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
@@ -32,10 +32,12 @@
 
 static const ci_hs_controller_t _ci_controller[] =
 {
-  { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
-  { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
+  { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn },
+  { .reg_base = LPC_USB1_BASE, .irqnum = USB1_IRQn }
 };
 
+#define CI_HS_REG(_port)        ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
+
 #define CI_DCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
 #define CI_DCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
 
diff --git a/src/portable/chipidea/ci_hs/ci_hs_mcx.h b/src/portable/chipidea/ci_hs/ci_hs_mcx.h
new file mode 100644
index 000000000..f940f4a9d
--- /dev/null
+++ b/src/portable/chipidea/ci_hs/ci_hs_mcx.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_HS_MCX_H_
+#define _CI_HS_MCX_H_
+
+#include "fsl_device_registers.h"
+
+// NOTE: MCX N9 has 2 different USB Controller
+// - USB0 is KHCI FullSpeed
+// - USB1 is ChipIdea HighSpeed, therefore rhport = 1 is actually index 0
+
+static const ci_hs_controller_t _ci_controller[] = {
+    {.reg_base = USBHS1__USBC_BASE, .irqnum = USB1_HS_IRQn}
+};
+
+TU_ATTR_ALWAYS_INLINE static inline ci_hs_regs_t* CI_HS_REG(uint8_t port) {
+  (void) port;
+  return ((ci_hs_regs_t*) _ci_controller[0].reg_base);
+}
+
+#define CI_DCD_INT_ENABLE(_p)   do { (void) _p; NVIC_EnableIRQ (_ci_controller[0].irqnum); } while (0)
+#define CI_DCD_INT_DISABLE(_p)  do { (void) _p; NVIC_DisableIRQ(_ci_controller[0].irqnum); } while (0)
+
+#define CI_HCD_INT_ENABLE(_p)   NVIC_EnableIRQ (_ci_controller[_p].irqnum)
+#define CI_HCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
+
+
+#endif
diff --git a/src/portable/chipidea/ci_hs/ci_hs_type.h b/src/portable/chipidea/ci_hs/ci_hs_type.h
index 31b5a012d..2f3aa3694 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_type.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_type.h
@@ -31,13 +31,21 @@
  extern "C" {
 #endif
 
+// DCCPARAMS
+enum {
+  DCCPARAMS_DEN_MASK = 0x1Fu, ///< DEN bit 4:0
+};
+
 // USBCMD
 enum {
   USBCMD_RUN_STOP         = TU_BIT(0),
   USBCMD_RESET            = TU_BIT(1),
   USBCMD_SETUP_TRIPWIRE   = TU_BIT(13),
-  USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
-// Interrupt Threshold bit 23:16
+  USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14), // This bit is used as a semaphore to ensure the to proper addition of a
+                                        // new dTD to an active (primed) endpoint’s linked list. This bit is set and
+                                        // cleared by software during the process of adding a new dTD
+
+  USBCMD_INTR_THRESHOLD_MASK = 0x00FF0000u, // Interrupt Threshold bit 23:16
 };
 
 // PORTSC1
@@ -72,6 +80,7 @@ enum {
 
 // USBMode
 enum {
+  USBMOD_CM_MASK    = TU_BIT(0) | TU_BIT(1),
   USBMODE_CM_DEVICE = 2,
   USBMODE_CM_HOST   = 3,
 
@@ -134,7 +143,6 @@ typedef struct
 {
   uint32_t reg_base;
   uint32_t irqnum;
-  uint8_t  ep_count; // Max bi-directional Endpoints
 }ci_hs_controller_t;
 
 #ifdef __cplusplus
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 9be79a2f1..850c82e43 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -28,35 +28,53 @@
 
 #if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_HS)
 
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
 #include "device/dcd.h"
 #include "ci_hs_type.h"
 
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   #include "ci_hs_imxrt.h"
-#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
+
+  void dcd_dcache_clean(void* addr, uint32_t data_size) {
+    imxrt_dcache_clean(addr, data_size);
+  }
+
+  void dcd_dcache_invalidate(void* addr, uint32_t data_size) {
+    imxrt_dcache_invalidate(addr, data_size);
+  }
+
+  void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+    imxrt_dcache_clean_invalidate(addr, data_size);
+  }
+
+#else
+
+#if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"
+
+#elif TU_CHECK_MCU(OPT_MCU_MCXN9)
+  // MCX N9 only port 1 use this controller
+  #include "ci_hs_mcx.h"
 #else
   #error "Unsupported MCUs"
 #endif
 
+  TU_ATTR_WEAK void dcd_dcache_clean(void* addr, uint32_t data_size) {
+    (void) addr; (void) data_size;
+  }
+
+  TU_ATTR_WEAK void dcd_dcache_invalidate(void* addr, uint32_t data_size) {
+    (void) addr; (void) data_size;
+  }
+
+  TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+    (void) addr; (void) data_size;
+  }
+#endif
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-#define CI_HS_REG(_port)      ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
-
-// Clean means to push any cached changes to RAM and invalidate "removes" the
-// entry from the cache.
-#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
-  #define CleanInvalidateDCache_by_Addr   SCB_CleanInvalidateDCache_by_Addr
-#else
-  #define CleanInvalidateDCache_by_Addr(_addr, _dsize)
-#endif
-
-
 // ENDPTCTRL
 enum {
   ENDPTCTRL_STALL          = TU_BIT(0),
@@ -160,6 +178,16 @@ typedef struct {
 CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
 static dcd_data_t _dcd_data;
 
+//--------------------------------------------------------------------+
+// Prototypes and Helper Functions
+//--------------------------------------------------------------------+
+
+TU_ATTR_ALWAYS_INLINE
+static inline uint8_t ci_ep_count(ci_hs_regs_t const* dcd_reg)
+{
+  return dcd_reg->DCCPARAMS & DCCPARAMS_DEN_MASK;
+}
+
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
@@ -174,7 +202,8 @@ static void bus_reset(uint8_t rhport)
   // endpoint type of the unused direction must be changed from the control type to any other
   // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
   // for the data PID tracking on the active endpoint.
-  for( uint8_t i=1; i < _ci_controller[rhport].ep_count; i++)
+  uint8_t const ep_count = ci_ep_count(dcd_reg);
+  for( uint8_t i=1; i < ep_count; i++)
   {
     dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
   }
@@ -202,7 +231,7 @@ static void bus_reset(uint8_t rhport)
 
   _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
 
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
 }
 
 void dcd_init(uint8_t rhport)
@@ -211,26 +240,34 @@ void dcd_init(uint8_t rhport)
 
   ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
 
+  TU_ASSERT(ci_ep_count(dcd_reg) <= TUP_DCD_ENDPOINT_MAX, );
+
   // Reset controller
   dcd_reg->USBCMD |= USBCMD_RESET;
   while( dcd_reg->USBCMD & USBCMD_RESET ) {}
 
   // Set mode to device, must be set immediately after reset
-  dcd_reg->USBMODE = USBMODE_CM_DEVICE;
+  uint32_t usbmode = dcd_reg->USBMODE & ~USBMOD_CM_MASK;
+  usbmode |= USBMODE_CM_DEVICE;
+  dcd_reg->USBMODE = usbmode;
+
   dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
 
 #if !TUD_OPT_HIGH_SPEED
   dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
 #endif
 
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
 
   dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
   dcd_reg->USBSTS  = dcd_reg->USBSTS;
   dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND;
 
-  dcd_reg->USBCMD &= ~0x00FF0000;     // Interrupt Threshold Interval = 0
-  dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
+  uint32_t usbcmd = dcd_reg->USBCMD;
+  usbcmd &= ~USBCMD_INTR_THRESHOLD_MASK; // Interrupt Threshold Interval = 0
+  usbcmd |= USBCMD_RUN_STOP; // run
+
+  dcd_reg->USBCMD = usbcmd;
 }
 
 void dcd_int_enable(uint8_t rhport)
@@ -286,7 +323,7 @@ static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
 {
   // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the
   // address to 32-byte boundaries. Buffer must be word aligned
-  CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
+  dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
 
   tu_memclr(p_qtd, sizeof(dcd_qtd_t));
 
@@ -343,8 +380,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
   uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
   uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
 
+  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
+
   // Must not exceed max endpoint number
-  TU_ASSERT( epnum < _ci_controller[rhport].ep_count );
+  TU_ASSERT(epnum < ci_ep_count(dcd_reg));
 
   //------------- Prepare Queue Head -------------//
   dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
@@ -359,11 +398,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 
   p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
 
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
 
   // Enable EP Control
-  ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
-
   uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
 
   if ( dir == TUSB_DIR_OUT )
@@ -382,7 +419,8 @@ void dcd_edpt_close_all (uint8_t rhport)
   ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport);
 
   // Disable all non-control endpoints
-  for( uint8_t epnum=1; epnum < _ci_controller[rhport].ep_count; epnum++)
+  uint8_t const ep_count = ci_ep_count(dcd_reg);
+  for (uint8_t epnum = 1; epnum < ep_count; epnum++)
   {
     _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1;
     _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1;
@@ -420,7 +458,7 @@ static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
   p_qhd->qtd_overlay.next   = (uint32_t) p_qtd; // link qtd to qhd
 
   // flush cache
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+  dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
 
   if ( epnum == 0 )
   {
@@ -498,7 +536,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
         }
       }
 
-      CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
+      dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
     }
     else
     {
@@ -611,7 +649,7 @@ void dcd_int_handler(uint8_t rhport)
   if (int_status & INTR_USB)
   {
     // Make sure we read the latest version of _dcd_data.
-    CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
+    dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t));
 
     uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
     dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index ab6a42e11..8c27abbf6 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -42,28 +42,17 @@
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   #include "ci_hs_imxrt.h"
 
-  // check if memory is cacheable i.e not in DTCM
-  TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uint32_t addr) {
-    return !(0x20000000 <= addr && addr < 0x20100000);
-  }
-
   void hcd_dcache_clean(void* addr, uint32_t data_size) {
-    if (is_cache_mem((uint32_t) addr)) {
-      SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size);
-    }
+    imxrt_dcache_clean(addr, data_size);
   }
 
   void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
-    if (is_cache_mem((uint32_t) addr)) {
-      SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
-    }
+    imxrt_dcache_invalidate(addr, data_size);
   }
 
-void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
-  if (is_cache_mem((uint32_t) addr)) {
-    SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
+  void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+    imxrt_dcache_clean_invalidate(addr, data_size);
   }
-}
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"
@@ -75,8 +64,6 @@ void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
-#define CI_HS_REG(_port)      ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
-
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 852e7f4fe..2b25eee9d 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -163,22 +163,15 @@ static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t
 static inline ehci_link_t* list_next (ehci_link_t const *p_link);
 
 TU_ATTR_WEAK void hcd_dcache_clean(void* addr, uint32_t data_size) {
-  (void) addr;
-  (void) data_size;
+  (void) addr; (void) data_size;
 }
 
-// invalidate data cache: mark cache as invalid, next read will read from memory
-// Required BOTH before and after an DMA RX transfer
 TU_ATTR_WEAK void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
-  (void) addr;
-  (void) data_size;
+  (void) addr; (void) data_size;
 }
 
-// clean and invalidate data cache
-// Required before an DMA transfer where memory is both read/write by DMA
 TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
-  (void) addr;
-  (void) data_size;
+  (void) addr; (void) data_size;
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 4f3f3a985..948c9edf3 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -166,6 +166,10 @@
 // WCH
 #define OPT_MCU_CH32V307         2200 ///< WCH CH32V307
 
+
+// NXP LPC MCX
+#define OPT_MCU_MCXN9            2300  ///< NXP MCX N9 Series
+
 // Helper to check if configured MCU is one of listed
 // Apply _TU_CHECK_MCU with || as separator to list of input
 #define _TU_CHECK_MCU(_m)   (CFG_TUSB_MCU == _m)
@@ -274,7 +278,7 @@
 // In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler
 // to generate unaligned access code.
 // LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM
-#if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX)
+#if TUD_OPT_HIGH_SPEED && TU_CHECK_MCU(OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX)
   #define TUP_MCU_STRICT_ALIGN   1
 #else
   #define TUP_MCU_STRICT_ALIGN   0
diff --git a/tools/cmake/cpu/cortex-m3.cmake b/tools/cmake/cpu/cortex-m3.cmake
new file mode 100644
index 000000000..b740ee44c
--- /dev/null
+++ b/tools/cmake/cpu/cortex-m3.cmake
@@ -0,0 +1,10 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  list(APPEND TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m3
+    )
+
+  set(FREERTOS_PORT GCC_ARM_CM3 CACHE INTERNAL "")
+else ()
+  # TODO support IAR
+endif ()
diff --git a/tools/cmake/cpu/cortex-m33.cmake b/tools/cmake/cpu/cortex-m33.cmake
index fbd5027b1..26c91a64f 100644
--- a/tools/cmake/cpu/cortex-m33.cmake
+++ b/tools/cmake/cpu/cortex-m33.cmake
@@ -3,10 +3,11 @@ if (TOOLCHAIN STREQUAL "gcc")
     -mthumb
     -mcpu=cortex-m33
     -mfloat-abi=hard
-    -mfpu=fpv5-d16
+    #-mfpu=fpv5-d16
+    -mfpu=fpv5-sp-d16
     )
 
-  set(FREERTOS_PORT GCC_ARM_CM33_NONSECURE CACHE INTERNAL "")
+  set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
 else ()
   # TODO support IAR
 endif ()
diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake
index c7b6cff98..5f25d637b 100644
--- a/tools/cmake/toolchain/arm_gcc.cmake
+++ b/tools/cmake/toolchain/arm_gcc.cmake
@@ -3,6 +3,8 @@ set(CMAKE_SYSTEM_NAME Generic)
 set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc")
 set(CMAKE_C_COMPILER "arm-none-eabi-gcc")
 set(CMAKE_CXX_COMPILER "arm-none-eabi-g++")
+
+set(TOOLCHAIN_SIZE "arm-none-eabi-size" CACHE INTERNAL "")
 set(GCC_ELF2BIN "arm-none-eabi-objcopy")
 set_property(GLOBAL PROPERTY ELF2BIN ${GCC_ELF2BIN})
 
diff --git a/tools/get_deps.py b/tools/get_deps.py
index be5738dc1..f499562cb 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -24,7 +24,7 @@ deps_optional = {
     'hw/mcu/nordic/nrfx'                       : ['2527e3c8449cfd38aee41598e8af8492f410ed15', 'https://github.com/NordicSemiconductor/nrfx.git'               ],
     'hw/mcu/nuvoton'                           : ['2204191ec76283371419fbcec207da02e1bc22fa', 'https://github.com/majbthrd/nuc_driver.git'                    ],
     'hw/mcu/nxp/lpcopen'                       : ['43c45c85405a5dd114fff0ea95cca62837740c13', 'https://github.com/hathach/nxp_lpcopen.git'                    ],
-    'hw/mcu/nxp/mcux-sdk'                      : ['f357a1150f6cf6c6b844f53f2d426bfb3e649850', 'https://github.com/NXPmicro/mcux-sdk.git'                      ],
+    'hw/mcu/nxp/mcux-sdk'                      : ['950819b7de9b32f92c3edf396bc5ffb8d66e7009', 'https://github.com/hathach/mcux-sdk.git'                       ],
     'hw/mcu/nxp/nxp_sdk'                       : ['845c8fc49b6fb660f06a5c45225494eacb06f00c', 'https://github.com/hathach/nxp_sdk.git'                        ],
     'hw/mcu/raspberry_pi/Pico-PIO-USB'         : ['c3715ce94b6f6391856de56081d4d9b3e98fa93d', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git'            ],
     'hw/mcu/renesas/fsp'                       : ['8dc14709f2a6518b43f71efad70d900b7718d9f1', 'https://github.com/renesas/fsp.git'                            ],
diff --git a/tools/make/cpu/cortex-m33.mk b/tools/make/cpu/cortex-m33.mk
index 2ea3a0753..3d12b01fd 100644
--- a/tools/make/cpu/cortex-m33.mk
+++ b/tools/make/cpu/cortex-m33.mk
@@ -3,7 +3,9 @@ ifeq ($(TOOLCHAIN),gcc)
     -mthumb \
     -mcpu=cortex-m33 \
     -mfloat-abi=hard \
-    -mfpu=fpv5-d16 \
+    -mfpu=fpv5-sp-d16 \
+
+    #-mfpu=fpv5-d16 \
 
   #set(FREERTOS_PORT GCC_ARM_CM33_NONSECURE CACHE INTERNAL "")
   FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure

From 57d2eb603b412a6bfbfdad7fb0bac854302b4351 Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Mon, 15 May 2023 18:27:45 +0200
Subject: [PATCH 1741/2085] fix(RA Host Portable): implement missing function
 __builtin_ctz(x) for IAR

---
 src/portable/renesas/rusb2/hcd_rusb2.c | 2 +-
 src/portable/renesas/rusb2/rusb2_ra.h  | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index e4743223e..0e6fa1618 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -407,7 +407,7 @@ static void process_pipe0_bemp(uint8_t rhport)
 static void process_pipe_nrdy(uint8_t rhport, unsigned num)
 {
   (void)rhport;
-  unsigned result;
+  xfer_result_t result;
   uint16_t volatile *ctr = get_pipectr(num);
   // TU_LOG1("NRDY %d %x\n", num, *ctr);
   switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) {
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 5785850cc..5be9f11ce 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -36,6 +36,10 @@ extern "C" {
 
 #define RUSB2_REG_BASE (0x40090000)
 
+#if defined(__ICCARM__)
+  #define __builtin_ctz(x)             __iar_builtin_CLZ(__iar_builtin_RBIT(x))
+#endif
+
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
   (void) rhport;

From 5a0c2bd63892f8457a707c0046e2d01ddba4f1e1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 25 May 2023 16:11:57 +0700
Subject: [PATCH 1742/2085] update get_deps.py to support geting family as
 argument

---
 .github/workflows/cmake_arm.yml |   2 +-
 tools/get_deps.py               | 245 ++++++++++++++++++++++++--------
 2 files changed, 185 insertions(+), 62 deletions(-)

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 12173fb63..d7eea512c 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -52,7 +52,7 @@ jobs:
       uses: actions/checkout@v3
 
     - name: Get Dependencies
-      run: python3 tools/get_family_deps.py ${{ matrix.family }}
+      run: python3 tools/get_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python tools/build_cmake.py ${{ matrix.family }}
diff --git a/tools/get_deps.py b/tools/get_deps.py
index f499562cb..842fb9275 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -4,67 +4,176 @@ from pathlib import Path
 from multiprocessing import Pool
 
 # Mandatory Dependencies that is always fetched
-# path, url, commit (Alphabet sorted by path)
+# path, url, commit, family (Alphabet sorted by path)
 deps_mandatory = {
-    'lib/FreeRTOS-Kernel'                      : ['5f19e34f878af97810a7662a75eac59bd74d628b', 'https://github.com/FreeRTOS/FreeRTOS-Kernel.git'               ],
-    'lib/lwip'                                 : ['159e31b689577dbf69cf0683bbaffbd71fa5ee10', 'https://github.com/lwip-tcpip/lwip.git'                        ],
-    'tools/uf2'                                : ['19615407727073e36d81bf239c52108ba92e7660', 'https://github.com/microsoft/uf2.git'                          ],
+    'lib/FreeRTOS-Kernel': ['https://github.com/FreeRTOS/FreeRTOS-Kernel.git',
+                            '5f19e34f878af97810a7662a75eac59bd74d628b',
+                            'all'],
+    'lib/lwip': ['https://github.com/lwip-tcpip/lwip.git',
+                 '159e31b689577dbf69cf0683bbaffbd71fa5ee10',
+                 'all'],
+    'tools/uf2': ['https://github.com/microsoft/uf2.git',
+                  '19615407727073e36d81bf239c52108ba92e7660',
+                  'all'],
 }
 
 # Optional Dependencies per MCU
-# path, url, commit (Alphabet sorted by path)
+# path, url, commit, family (Alphabet sorted by path)
 deps_optional = {
-    'hw/mcu/allwinner'                         : ['8e5e89e8e132c0fd90e72d5422e5d3d68232b756', 'https://github.com/hathach/allwinner_driver.git'               ],
-    'hw/mcu/bridgetek/ft9xx/ft90x-sdk'         : ['91060164afe239fcb394122e8bf9eb24d3194eb1', 'https://github.com/BRTSG-FOSS/ft90x-sdk.git'                   ],
-    'hw/mcu/broadcom'                          : ['08370086080759ed54ac1136d62d2ad24c6fa267', 'https://github.com/adafruit/broadcom-peripherals.git'          ],
-    'hw/mcu/gd/nuclei-sdk'                     : ['7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7', 'https://github.com/Nuclei-Software/nuclei-sdk.git'             ],
-    'hw/mcu/infineon/mtb-xmclib-cat3'          : ['daf5500d03cba23e68c2f241c30af79cd9d63880', 'https://github.com/Infineon/mtb-xmclib-cat3.git'               ],
-    'hw/mcu/microchip'                         : ['9e8b37e307d8404033bb881623a113931e1edf27', 'https://github.com/hathach/microchip_driver.git'               ],
-    'hw/mcu/mindmotion/mm32sdk'                : ['0b79559eb411149d36e073c1635c620e576308d4', 'https://github.com/hathach/mm32sdk.git'                        ],
-    'hw/mcu/nordic/nrfx'                       : ['2527e3c8449cfd38aee41598e8af8492f410ed15', 'https://github.com/NordicSemiconductor/nrfx.git'               ],
-    'hw/mcu/nuvoton'                           : ['2204191ec76283371419fbcec207da02e1bc22fa', 'https://github.com/majbthrd/nuc_driver.git'                    ],
-    'hw/mcu/nxp/lpcopen'                       : ['43c45c85405a5dd114fff0ea95cca62837740c13', 'https://github.com/hathach/nxp_lpcopen.git'                    ],
-    'hw/mcu/nxp/mcux-sdk'                      : ['950819b7de9b32f92c3edf396bc5ffb8d66e7009', 'https://github.com/hathach/mcux-sdk.git'                       ],
-    'hw/mcu/nxp/nxp_sdk'                       : ['845c8fc49b6fb660f06a5c45225494eacb06f00c', 'https://github.com/hathach/nxp_sdk.git'                        ],
-    'hw/mcu/raspberry_pi/Pico-PIO-USB'         : ['c3715ce94b6f6391856de56081d4d9b3e98fa93d', 'https://github.com/sekigon-gonnoc/Pico-PIO-USB.git'            ],
-    'hw/mcu/renesas/fsp'                       : ['8dc14709f2a6518b43f71efad70d900b7718d9f1', 'https://github.com/renesas/fsp.git'                            ],
-    'hw/mcu/renesas/rx'                        : ['706b4e0cf485605c32351e2f90f5698267996023', 'https://github.com/kkitayam/rx_device.git'                     ],
-    'hw/mcu/silabs/cmsis-dfp-efm32gg12b'       : ['f1c31b7887669cb230b3ea63f9b56769078960bc', 'https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git'       ],
-    'hw/mcu/sony/cxd56/spresense-exported-sdk' : ['2ec2a1538362696118dc3fdf56f33dacaf8f4067', 'https://github.com/sonydevworld/spresense-exported-sdk.git'    ],
-    'hw/mcu/st/cmsis_device_f0'                : ['2fc25ee22264bc27034358be0bd400b893ef837e', 'https://github.com/STMicroelectronics/cmsis_device_f0.git'     ],
-    'hw/mcu/st/cmsis_device_f1'                : ['6601104a6397299b7304fd5bcd9a491f56cb23a6', 'https://github.com/STMicroelectronics/cmsis_device_f1.git'     ],
-    'hw/mcu/st/cmsis_device_f2'                : ['182fcb3681ce116816feb41b7764f1b019ce796f', 'https://github.com/STMicroelectronics/cmsis_device_f2.git'     ],
-    'hw/mcu/st/cmsis_device_f3'                : ['5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b', 'https://github.com/STMicroelectronics/cmsis_device_f3.git'     ],
-    'hw/mcu/st/cmsis_device_f4'                : ['2615e866fa48fe1ff1af9e31c348813f2b19e7ec', 'https://github.com/STMicroelectronics/cmsis_device_f4.git'     ],
-    'hw/mcu/st/cmsis_device_f7'                : ['fc676ef1ad177eb874eaa06444d3d75395fc51f4', 'https://github.com/STMicroelectronics/cmsis_device_f7.git'     ],
-    'hw/mcu/st/cmsis_device_g0'                : ['08258b28ee95f50cb9624d152a1cbf084be1f9a5', 'https://github.com/STMicroelectronics/cmsis_device_g0.git'     ],
-    'hw/mcu/st/cmsis_device_g4'                : ['ce822adb1dc552b3aedd13621edbc7fdae124878', 'https://github.com/STMicroelectronics/cmsis_device_g4.git'     ],
-    'hw/mcu/st/cmsis_device_h7'                : ['60dc2c913203dc8629dc233d4384dcc41c91e77f', 'https://github.com/STMicroelectronics/cmsis_device_h7.git'     ],
-    'hw/mcu/st/cmsis_device_l0'                : ['06748ca1f93827befdb8b794402320d94d02004f', 'https://github.com/STMicroelectronics/cmsis_device_l0.git'     ],
-    'hw/mcu/st/cmsis_device_l1'                : ['7f16ec0a1c4c063f84160b4cc6bf88ad554a823e', 'https://github.com/STMicroelectronics/cmsis_device_l1.git'     ],
-    'hw/mcu/st/cmsis_device_l4'                : ['6ca7312fa6a5a460b5a5a63d66da527fdd8359a6', 'https://github.com/STMicroelectronics/cmsis_device_l4.git'     ],
-    'hw/mcu/st/cmsis_device_l5'                : ['d922865fc0326a102c26211c44b8e42f52c1e53d', 'https://github.com/STMicroelectronics/cmsis_device_l5.git'     ],
-    'hw/mcu/st/cmsis_device_u5'                : ['bc00f3c9d8a4e25220f84c26d414902cc6bdf566', 'https://github.com/STMicroelectronics/cmsis_device_u5.git'     ],
-    'hw/mcu/st/cmsis_device_wb'                : ['9c5d1920dd9fabbe2548e10561d63db829bb744f', 'https://github.com/STMicroelectronics/cmsis_device_wb.git'     ],
-    'hw/mcu/st/stm32f0xx_hal_driver'           : ['0e95cd88657030f640a11e690a8a5186c7712ea5', 'https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git'],
-    'hw/mcu/st/stm32f1xx_hal_driver'           : ['1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29', 'https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git'],
-    'hw/mcu/st/stm32f2xx_hal_driver'           : ['c75ace9b908a9aca631193ebf2466963b8ea33d0', 'https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git'],
-    'hw/mcu/st/stm32f3xx_hal_driver'           : ['1761b6207318ede021706e75aae78f452d72b6fa', 'https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git'],
-    'hw/mcu/st/stm32f4xx_hal_driver'           : ['04e99fbdabd00ab8f370f377c66b0a4570365b58', 'https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git'],
-    'hw/mcu/st/stm32f7xx_hal_driver'           : ['f7ffdf6bf72110e58b42c632b0a051df5997e4ee', 'https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git'],
-    'hw/mcu/st/stm32g0xx_hal_driver'           : ['5b53e6cee664a82b16c86491aa0060e2110c00cb', 'https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git'],
-    'hw/mcu/st/stm32g4xx_hal_driver'           : ['8b4518417706d42eef5c14e56a650005abf478a8', 'https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git'],
-    'hw/mcu/st/stm32h7xx_hal_driver'           : ['d8461b980b59b1625207d8c4f2ce0a9c2a7a3b04', 'https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git'],
-    'hw/mcu/st/stm32l0xx_hal_driver'           : ['fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b', 'https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git'],
-    'hw/mcu/st/stm32l1xx_hal_driver'           : ['44efc446fa69ed8344e7fd966e68ed11043b35d9', 'https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git'],
-    'hw/mcu/st/stm32l4xx_hal_driver'           : ['aee3d5bf283ae5df87532b781bdd01b7caf256fc', 'https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git'],
-    'hw/mcu/st/stm32l5xx_hal_driver'           : ['675c32a75df37f39d50d61f51cb0dcf53f07e1cb', 'https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git'],
-    'hw/mcu/st/stm32u5xx_hal_driver'           : ['2e1d4cdb386e33391cb261dfff4fefa92e4aa35a', 'https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git'],
-    'hw/mcu/st/stm32wbxx_hal_driver'           : ['2c5f06638be516c1b772f768456ba637f077bac8', 'https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git'],
-    'hw/mcu/ti'                                : ['143ed6cc20a7615d042b03b21e070197d473e6e5', 'https://github.com/hathach/ti_driver.git'                      ],
-    'hw/mcu/wch/ch32v307'                      : ['17761f5cf9dbbf2dcf665b7c04934188add20082', 'https://github.com/openwch/ch32v307.git'                       ],
-    'lib/CMSIS_5'                              : ['20285262657d1b482d132d20d755c8c330d55c1f', 'https://github.com/ARM-software/CMSIS_5.git'                   ],
-    'lib/sct_neopixel'                         : ['e73e04ca63495672d955f9268e003cffe168fcd8', 'https://github.com/gsteiert/sct_neopixel.git'                  ],
+    'hw/mcu/allwinner': ['https://github.com/hathach/allwinner_driver.git',
+                         '8e5e89e8e132c0fd90e72d5422e5d3d68232b756',
+                         'fc100s'],
+    'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git',
+                                         '91060164afe239fcb394122e8bf9eb24d3194eb1',
+                                         'brtmm90x'],
+    'hw/mcu/broadcom': ['https://github.com/adafruit/broadcom-peripherals.git',
+                        '08370086080759ed54ac1136d62d2ad24c6fa267',
+                        'broadcom_32bit broadcom_64bit'],
+    'hw/mcu/gd/nuclei-sdk': ['https://github.com/Nuclei-Software/nuclei-sdk.git',
+                             '7eb7bfa9ea4fbeacfafe1d5f77d5a0e6ed3922e7',
+                             'gd32vf103'],
+    'hw/mcu/infineon/mtb-xmclib-cat3': ['https://github.com/Infineon/mtb-xmclib-cat3.git',
+                                        'daf5500d03cba23e68c2f241c30af79cd9d63880',
+                                        'xmc4000'],
+    'hw/mcu/microchip': ['https://github.com/hathach/microchip_driver.git',
+                         '9e8b37e307d8404033bb881623a113931e1edf27',
+                         'sam3x samd11 samd21 samd51 same5x same7x saml2x samg'],
+    'hw/mcu/mindmotion/mm32sdk': ['https://github.com/hathach/mm32sdk.git',
+                                  '0b79559eb411149d36e073c1635c620e576308d4',
+                                  'mm32'],
+    'hw/mcu/nordic/nrfx': ['https://github.com/NordicSemiconductor/nrfx.git',
+                           '2527e3c8449cfd38aee41598e8af8492f410ed15',
+                           'nrf'],
+    'hw/mcu/nuvoton': ['https://github.com/majbthrd/nuc_driver.git',
+                       '2204191ec76283371419fbcec207da02e1bc22fa',
+                       'nuc'],
+    'hw/mcu/nxp/lpcopen': ['https://github.com/hathach/nxp_lpcopen.git',
+                           '43c45c85405a5dd114fff0ea95cca62837740c13',
+                           'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
+    'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
+                            '950819b7de9b32f92c3edf396bc5ffb8d66e7009',
+                            'kinetis_k32 lpc51 lpc54 lpc55 mcx imxrt'],
+    'hw/mcu/nxp/nxp_sdk': ['https://github.com/hathach/nxp_sdk.git',
+                           '845c8fc49b6fb660f06a5c45225494eacb06f00c',
+                           'kinetis_kl'],
+    'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
+                                         'c3715ce94b6f6391856de56081d4d9b3e98fa93d',
+                                         'rp2040'],
+    'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git',
+                           '8dc14709f2a6518b43f71efad70d900b7718d9f1',
+                           'ra'],
+    'hw/mcu/renesas/rx': ['https://github.com/kkitayam/rx_device.git',
+                          '706b4e0cf485605c32351e2f90f5698267996023',
+                          'rx'],
+    'hw/mcu/silabs/cmsis-dfp-efm32gg12b': ['https://github.com/cmsis-packs/cmsis-dfp-efm32gg12b.git',
+                                           'f1c31b7887669cb230b3ea63f9b56769078960bc',
+                                           'efm32'],
+    'hw/mcu/sony/cxd56/spresense-exported-sdk': ['https://github.com/sonydevworld/spresense-exported-sdk.git',
+                                                 '2ec2a1538362696118dc3fdf56f33dacaf8f4067',
+                                                 'spresense'],
+    'hw/mcu/st/cmsis_device_f0': ['https://github.com/STMicroelectronics/cmsis_device_f0.git',
+                                  '2fc25ee22264bc27034358be0bd400b893ef837e',
+                                  'stm32f0'],
+    'hw/mcu/st/cmsis_device_f1': ['https://github.com/STMicroelectronics/cmsis_device_f1.git',
+                                  '6601104a6397299b7304fd5bcd9a491f56cb23a6',
+                                  'stm32f1'],
+    'hw/mcu/st/cmsis_device_f2': ['https://github.com/STMicroelectronics/cmsis_device_f2.git',
+                                  '182fcb3681ce116816feb41b7764f1b019ce796f',
+                                  'stm32f2'],
+    'hw/mcu/st/cmsis_device_f3': ['https://github.com/STMicroelectronics/cmsis_device_f3.git',
+                                  '5e4ee5ed7a7b6c85176bb70a9fd3c72d6eb99f1b',
+                                  'stm32f3'],
+    'hw/mcu/st/cmsis_device_f4': ['https://github.com/STMicroelectronics/cmsis_device_f4.git',
+                                  '2615e866fa48fe1ff1af9e31c348813f2b19e7ec',
+                                  'stm32f4'],
+    'hw/mcu/st/cmsis_device_f7': ['https://github.com/STMicroelectronics/cmsis_device_f7.git',
+                                  'fc676ef1ad177eb874eaa06444d3d75395fc51f4',
+                                  'stm32f7'],
+    'hw/mcu/st/cmsis_device_g0': ['https://github.com/STMicroelectronics/cmsis_device_g0.git',
+                                  '08258b28ee95f50cb9624d152a1cbf084be1f9a5',
+                                  'stm32g0'],
+    'hw/mcu/st/cmsis_device_g4': ['https://github.com/STMicroelectronics/cmsis_device_g4.git',
+                                  'ce822adb1dc552b3aedd13621edbc7fdae124878',
+                                  'stm32g4'],
+    'hw/mcu/st/cmsis_device_h7': ['https://github.com/STMicroelectronics/cmsis_device_h7.git',
+                                  '60dc2c913203dc8629dc233d4384dcc41c91e77f',
+                                  'stm32h7'],
+    'hw/mcu/st/cmsis_device_l0': ['https://github.com/STMicroelectronics/cmsis_device_l0.git',
+                                  '06748ca1f93827befdb8b794402320d94d02004f',
+                                  'stm32l0'],
+    'hw/mcu/st/cmsis_device_l1': ['https://github.com/STMicroelectronics/cmsis_device_l1.git',
+                                  '7f16ec0a1c4c063f84160b4cc6bf88ad554a823e',
+                                  'stm32l1'],
+    'hw/mcu/st/cmsis_device_l4': ['https://github.com/STMicroelectronics/cmsis_device_l4.git',
+                                  '6ca7312fa6a5a460b5a5a63d66da527fdd8359a6',
+                                  'stm32l4'],
+    'hw/mcu/st/cmsis_device_l5': ['https://github.com/STMicroelectronics/cmsis_device_l5.git',
+                                  'd922865fc0326a102c26211c44b8e42f52c1e53d',
+                                  'stm32l5'],
+    'hw/mcu/st/cmsis_device_u5': ['https://github.com/STMicroelectronics/cmsis_device_u5.git',
+                                  'bc00f3c9d8a4e25220f84c26d414902cc6bdf566',
+                                  'stm32u5'],
+    'hw/mcu/st/cmsis_device_wb': ['https://github.com/STMicroelectronics/cmsis_device_wb.git',
+                                  '9c5d1920dd9fabbe2548e10561d63db829bb744f',
+                                  'stm32wb'],
+    'hw/mcu/st/stm32f0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git',
+                                       '0e95cd88657030f640a11e690a8a5186c7712ea5',
+                                       'stm32f0'],
+    'hw/mcu/st/stm32f1xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f1xx_hal_driver.git',
+                                       '1dd9d3662fb7eb2a7f7d3bc0a4c1dc7537915a29',
+                                       'stm32f1'],
+    'hw/mcu/st/stm32f2xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f2xx_hal_driver.git',
+                                       'c75ace9b908a9aca631193ebf2466963b8ea33d0',
+                                       'stm32f2'],
+    'hw/mcu/st/stm32f3xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f3xx_hal_driver.git',
+                                       '1761b6207318ede021706e75aae78f452d72b6fa',
+                                       'stm32f3'],
+    'hw/mcu/st/stm32f4xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f4xx_hal_driver.git',
+                                       '04e99fbdabd00ab8f370f377c66b0a4570365b58',
+                                       'stm32f4'],
+    'hw/mcu/st/stm32f7xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f7xx_hal_driver.git',
+                                       'f7ffdf6bf72110e58b42c632b0a051df5997e4ee',
+                                       'stm32f7'],
+    'hw/mcu/st/stm32g0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32g0xx_hal_driver.git',
+                                       '5b53e6cee664a82b16c86491aa0060e2110c00cb',
+                                       'stm32g0'],
+    'hw/mcu/st/stm32g4xx_hal_driver': ['https://github.com/STMicroelectronics/stm32g4xx_hal_driver.git',
+                                       '8b4518417706d42eef5c14e56a650005abf478a8',
+                                       'stm32g4'],
+    'hw/mcu/st/stm32h7xx_hal_driver': ['https://github.com/STMicroelectronics/stm32h7xx_hal_driver.git',
+                                       'd8461b980b59b1625207d8c4f2ce0a9c2a7a3b04',
+                                       'stm32h7'],
+    'hw/mcu/st/stm32l0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l0xx_hal_driver.git',
+                                       'fbdacaf6f8c82a4e1eb9bd74ba650b491e97e17b',
+                                       'stm32l0'],
+    'hw/mcu/st/stm32l1xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git',
+                                       '44efc446fa69ed8344e7fd966e68ed11043b35d9',
+                                       'stm32l1'],
+    'hw/mcu/st/stm32l4xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git',
+                                       'aee3d5bf283ae5df87532b781bdd01b7caf256fc',
+                                       'stm32l4'],
+    'hw/mcu/st/stm32l5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git',
+                                       '675c32a75df37f39d50d61f51cb0dcf53f07e1cb',
+                                       'stm32l5'],
+    'hw/mcu/st/stm32u5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git',
+                                       '2e1d4cdb386e33391cb261dfff4fefa92e4aa35a',
+                                       'stm32u5'],
+    'hw/mcu/st/stm32wbxx_hal_driver': ['https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git',
+                                       '2c5f06638be516c1b772f768456ba637f077bac8',
+                                       'stm32wb'],
+    'hw/mcu/ti': ['https://github.com/hathach/ti_driver.git',
+                  '143ed6cc20a7615d042b03b21e070197d473e6e5',
+                  'msp430 msp432e4 tm4c123'],
+    'hw/mcu/wch/ch32v307': ['https://github.com/openwch/ch32v307.git',
+                            '17761f5cf9dbbf2dcf665b7c04934188add20082',
+                            'ch32v307'],
+    'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
+                    '20285262657d1b482d132d20d755c8c330d55c1f',
+                    'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l0 stm32l1 stm32l4 '
+                    'stm32l5 stm32u5 stm32wb'],
+    'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
+                         'e73e04ca63495672d955f9268e003cffe168fcd8',
+                         'lpc55'],
 }
 
 # combined 2 deps
@@ -78,8 +187,10 @@ def get_a_dep(d):
     if d not in deps_all.keys():
         print('{} is not found in dependency list')
         return 1
-    commit = deps_all[d][0]
-    url = deps_all[d][1]
+    url = deps_all[d][0]
+    commit = deps_all[d][1]
+    families = deps_all[d][2]
+
     print('cloning {} with {}'.format(d, url))
 
     p = Path(TOP / d)
@@ -103,14 +214,26 @@ def get_a_dep(d):
     return 0
 
 
+# Arguments can be
+# - family name
+# - specific deps path
+# - all
 if __name__ == "__main__":
     status = 0
     deps = list(deps_mandatory.keys())
-    # get all if executed with all as argument
+    # get all if  'all' is argument
     if len(sys.argv) == 2 and sys.argv[1] == 'all':
-        deps += deps_optional
+        deps += deps_optional.keys()
     else:
-        deps += sys.argv[1:]
+        for arg in sys.argv[1:]:
+            if arg in deps_all.keys():
+                # if arg is a dep, add it
+                deps.append(arg)
+            else:
+                # arg is a family name, add all deps of that family
+                for d in deps_optional:
+                    if arg in deps_optional[d][2]:
+                        deps.append(d)
 
     with Pool() as pool:
         status = sum(pool.map(get_a_dep, deps))

From 7a3d7a7c23da7a7e8122c879b047f80a1a131fcc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 25 May 2023 16:17:41 +0700
Subject: [PATCH 1743/2085] cmsis_5 missing mcx and imxrt

---
 tools/get_deps.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index 842fb9275..6db5224a4 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -169,8 +169,8 @@ deps_optional = {
                             'ch32v307'],
     'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
                     '20285262657d1b482d132d20d755c8c330d55c1f',
-                    'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l0 stm32l1 stm32l4 '
-                    'stm32l5 stm32u5 stm32wb'],
+                    'imxrt mcx stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l0 stm32l1 '
+                    'stm32l4 stm32l5 stm32u5 stm32wb'],
     'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
                          'e73e04ca63495672d955f9268e003cffe168fcd8',
                          'lpc55'],

From 625c27ca58dc2782da77c210c5d5878ce4b1fc12 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 25 May 2023 16:20:58 +0700
Subject: [PATCH 1744/2085] add workflow_dispatch for manual trigger

---
 .github/workflows/cmake_arm.yml  | 1 +
 .github/workflows/pre-commit.yml | 1 +
 .github/workflows/trigger.yml    | 1 +
 3 files changed, 3 insertions(+)

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index d7eea512c..e7991252d 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -1,6 +1,7 @@
 name: CMake ARM
 
 on:
+  workflow_dispatch:
   push:
     paths:
       - 'src/**'
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index ab416bc52..f984954d9 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -1,6 +1,7 @@
 name: pre-commit
 
 on:
+  workflow_dispatch:
   push:
   pull_request:
     branches: [ master ]
diff --git a/.github/workflows/trigger.yml b/.github/workflows/trigger.yml
index 86c699dac..33e3db859 100644
--- a/.github/workflows/trigger.yml
+++ b/.github/workflows/trigger.yml
@@ -1,6 +1,7 @@
 name: Trigger Repos
 
 on:
+  workflow_dispatch:
   push:
     branches: master
   release:

From 26d05d7fc922f3715799f6049556232d5ed5c8e3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 25 May 2023 16:53:32 +0700
Subject: [PATCH 1745/2085] fix issue with ftdi host driver with status bytes

add workflow_dispatch to all ci workflow
---
 .github/workflows/build_aarch64.yml |  1 +
 .github/workflows/build_arm.yml     |  1 +
 .github/workflows/build_esp.yml     |  1 +
 .github/workflows/build_iar.yml     |  1 +
 .github/workflows/build_msp430.yml  |  1 +
 .github/workflows/build_renesas.yml |  1 +
 .github/workflows/build_riscv.yml   |  1 +
 .github/workflows/build_win_mac.yml |  1 +
 .github/workflows/cifuzz.yml        |  1 +
 src/class/cdc/cdc_host.c            | 36 ++++++++++++++---------------
 src/common/tusb_private.h           | 17 +++++++++-----
 11 files changed, 37 insertions(+), 25 deletions(-)

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index cc8ddb070..77d3778d7 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -1,6 +1,7 @@
 name: Build AArch64
 
 on:
+  workflow_dispatch:
   push:
     paths:
       - 'src/**'
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 917c83d74..1db9586af 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -1,6 +1,7 @@
 name: Build ARM
 
 on:
+  workflow_dispatch:
   push:
     paths:
       - 'src/**'
diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 0a6815ea2..29585cb36 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -1,6 +1,7 @@
 name: Build ESP
 
 on:
+  workflow_dispatch:
   push:
     paths:
       - 'src/**'
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index a5d24892f..8c3b57e10 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -1,6 +1,7 @@
 name: Build IAR
 
 on:
+  workflow_dispatch:
   push:
     paths:
       - 'src/**'
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 7cb60dceb..5424a88d6 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -1,6 +1,7 @@
 name: Build MSP430
 
 on:
+  workflow_dispatch:
   push:
     paths:
       - 'src/**'
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index ffdeedb71..3f0a4b694 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -1,6 +1,7 @@
 name: Build Renesas
 
 on:
+  workflow_dispatch:
   push:
     paths:
       - 'src/**'
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 87c7b522e..8682d655a 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -1,6 +1,7 @@
 name: Build RISC-V
 
 on:
+  workflow_dispatch:
   push:
     paths:
       - 'src/**'
diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index 4b743a686..45fc62f78 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -1,6 +1,7 @@
 name: Build Windows/MacOS
 
 on:
+  workflow_dispatch:
   push:
     paths:
       - 'src/**'
diff --git a/.github/workflows/cifuzz.yml b/.github/workflows/cifuzz.yml
index 7314fd9e6..4c4b12a6b 100644
--- a/.github/workflows/cifuzz.yml
+++ b/.github/workflows/cifuzz.yml
@@ -1,5 +1,6 @@
 name: CIFuzz
 on:
+  workflow_dispatch:
   pull_request:
     branches:
       - master
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 9ff666ed4..ce9f27c33 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -550,8 +550,7 @@ void cdch_close(uint8_t daddr)
   }
 }
 
-bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
-{
+bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) {
   // TODO handle stall response, retry failed transfer ...
   TU_ASSERT(event == XFER_RESULT_SUCCESS);
 
@@ -559,41 +558,40 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
   cdch_interface_t * p_cdc = get_itf(idx);
   TU_ASSERT(p_cdc);
 
-  if ( ep_addr == p_cdc->stream.tx.ep_addr )
-  {
+  if ( ep_addr == p_cdc->stream.tx.ep_addr ) {
     // invoke tx complete callback to possibly refill tx fifo
     if (tuh_cdc_tx_complete_cb) tuh_cdc_tx_complete_cb(idx);
 
-    if ( 0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx) )
-    {
+    if ( 0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx) ) {
       // If there is no data left, a ZLP should be sent if:
       // - xferred_bytes is multiple of EP Packet size and not zero
       tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes);
     }
   }
-  else if ( ep_addr == p_cdc->stream.rx.ep_addr )
-  {
-    tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
-
+  else if ( ep_addr == p_cdc->stream.rx.ep_addr ) {
     #if CFG_TUH_CDC_FTDI
-    // FTDI reserve 2 bytes for status
     if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) {
-      uint8_t status[2];
-      tu_edpt_stream_read(&p_cdc->stream.rx, status, 2);
-      (void) status; // TODO handle status
-    }
+      // FTDI reserve 2 bytes for status
+      // FTDI status
+//      uint8_t status[2] = {
+//        p_cdc->stream.rx.ep_buf[0],
+//        p_cdc->stream.rx.ep_buf[1]
+//      };
+      tu_edpt_stream_read_xfer_complete_offset(&p_cdc->stream.rx, xferred_bytes, 2);
+    }else
     #endif
+    {
+      tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes);
+    }
 
     // invoke receive callback
     if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx);
 
     // prepare for next transfer if needed
     tu_edpt_stream_read_xfer(&p_cdc->stream.rx);
-  }else if ( ep_addr == p_cdc->ep_notif )
-  {
+  }else if ( ep_addr == p_cdc->ep_notif ) {
     // TODO handle notification endpoint
-  }else
-  {
+  }else {
     TU_ASSERT(false);
   }
 
diff --git a/src/common/tusb_private.h b/src/common/tusb_private.h
index d5541856c..db1ba974d 100644
--- a/src/common/tusb_private.h
+++ b/src/common/tusb_private.h
@@ -148,21 +148,26 @@ uint32_t tu_edpt_stream_read_xfer(tu_edpt_stream_t* s);
 
 // Must be called in the transfer complete callback
 TU_ATTR_ALWAYS_INLINE static inline
-void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes)
-{
+void tu_edpt_stream_read_xfer_complete(tu_edpt_stream_t* s, uint32_t xferred_bytes) {
   tu_fifo_write_n(&s->ff, s->ep_buf, (uint16_t) xferred_bytes);
 }
 
+// Same as tu_edpt_stream_read_xfer_complete but skip the first n bytes
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_edpt_stream_read_xfer_complete_offset(tu_edpt_stream_t* s, uint32_t xferred_bytes, uint32_t skip_offset) {
+  if (skip_offset < xferred_bytes) {
+    tu_fifo_write_n(&s->ff, s->ep_buf + skip_offset, (uint16_t) (xferred_bytes - skip_offset));
+  }
+}
+
 // Get the number of bytes available for reading
 TU_ATTR_ALWAYS_INLINE static inline
-uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s)
-{
+uint32_t tu_edpt_stream_read_available(tu_edpt_stream_t* s) {
   return (uint32_t) tu_fifo_count(&s->ff);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-bool tu_edpt_stream_peek(tu_edpt_stream_t* s, uint8_t* ch)
-{
+bool tu_edpt_stream_peek(tu_edpt_stream_t* s, uint8_t* ch) {
   return tu_fifo_peek(&s->ff, ch);
 }
 

From 5fea010406747a94f3a65a89e65e7956ff811b3c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 25 May 2023 17:27:05 +0700
Subject: [PATCH 1746/2085] add family_support_configure_common()

---
 hw/bsp/family_support.cmake | 16 ++++++++++++++++
 hw/bsp/imxrt/family.cmake   | 20 +++++---------------
 hw/bsp/lpc18/family.cmake   | 16 +++++-----------
 hw/bsp/lpc55/family.cmake   | 16 +++++-----------
 hw/bsp/mcx/family.cmake     | 22 ++++++----------------
 hw/bsp/nrf/family.cmake     | 23 +++++------------------
 6 files changed, 42 insertions(+), 71 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index d2d675332..760f2fbbc 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -136,6 +136,22 @@ function(family_add_default_example_warnings TARGET)
 endfunction()
 
 
+function(family_support_configure_common TARGET)
+    # set output name to .elf
+    set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+
+    # run size after build
+    add_custom_command(TARGET ${TARGET} POST_BUILD
+      COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
+      )
+
+    # Generate map file
+    target_link_options(${TARGET} PUBLIC
+      # link map
+      "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map"
+      )
+endfunction()
+
 #  add_custom_command(TARGET ${TARGET} POST_BUILD
 #    COMMAND ${CMAKE_OBJCOPY} -O ihex $<TARGET_FILE:${TARGET}> ${TARGET}.hex
 #    COMMAND ${CMAKE_OBJCOPY} -O binary $<TARGET_FILE:${TARGET}> ${TARGET}.bin
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index ade744aa5..0e55b825d 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -63,7 +63,6 @@ if (NOT TARGET ${BOARD_TARGET})
       )
     target_link_options(${BOARD_TARGET} PUBLIC
       "LINKER:--script=${LD_FILE_gcc}"
-      "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
       # nanolib
       --specs=nosys.specs
       --specs=nano.specs
@@ -79,17 +78,8 @@ endif () # BOARD_TARGET
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_target TARGET)
-  # set output name to .elf
-  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
-
-  # run size after build
-  add_custom_command(TARGET ${TARGET} POST_BUILD
-    COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
-    )
-
-  # TOP is path to root directory
-  set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
+function(family_configure_example TARGET)
+  family_support_configure_common(${TARGET})
 
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
@@ -162,13 +152,13 @@ function(family_add_freertos TARGET)
 endfunction()
 
 function(family_configure_device_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
 
 function(family_configure_host_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
 
 function(family_configure_dual_usb_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index 059408fe9..29fa73d34 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -65,14 +65,8 @@ endif () # BOARD_TARGET
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_target TARGET)
-  # set output name to .elf
-  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
-
-  # run size after build
-  add_custom_command(TARGET ${TARGET} POST_BUILD
-    COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
-    )
+function(family_configure_example TARGET)
+  family_support_configure_common(${TARGET})
 
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
@@ -143,13 +137,13 @@ function(family_add_freertos TARGET)
 endfunction()
 
 function(family_configure_device_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
 
 function(family_configure_host_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
 
 function(family_configure_dual_usb_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 3aeda5b2d..363b7a9cd 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -63,8 +63,6 @@ if (NOT TARGET ${BOARD_TARGET})
     target_link_options(${BOARD_TARGET} PUBLIC
       # linker file
       "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
-      # link map
-      "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
       # nanolib
       --specs=nosys.specs
       --specs=nano.specs
@@ -77,12 +75,8 @@ endif () # BOARD_TARGET
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_target TARGET)
-  # set output name to .elf
-  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
-
-  # TOP is path to root directory
-  set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
+function(family_configure_example TARGET)
+  family_support_configure_common(${TARGET})
 
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
@@ -153,13 +147,13 @@ function(family_add_freertos TARGET)
 endfunction()
 
 function(family_configure_device_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
 
 function(family_configure_host_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
 
 function(family_configure_dual_usb_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index e4bc11be5..bc0dfe875 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -54,11 +54,10 @@ if (NOT TARGET ${BOARD_TARGET})
     target_sources(${BOARD_TARGET} PUBLIC
       ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
       )
+    cmake_print_variables(CMAKE_CURRENT_BINARY_DIR)
     target_link_options(${BOARD_TARGET} PUBLIC
       # linker file
       "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
-      # link map
-      "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
       # nanolib
       --specs=nosys.specs
       --specs=nano.specs
@@ -71,17 +70,8 @@ endif () # BOARD_TARGET
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_target TARGET)
-  # set output name to .elf
-  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
-
-  # run size after build
-  add_custom_command(TARGET ${TARGET} POST_BUILD
-    COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
-    )
-
-  # TOP is path to root directory
-  set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
+function(family_configure_example TARGET)
+  family_support_configure_common(${TARGET})
 
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
@@ -167,13 +157,13 @@ function(family_add_freertos TARGET)
 endfunction()
 
 function(family_configure_device_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
 
 function(family_configure_host_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
 
 function(family_configure_dual_usb_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 1156a171b..9d958fee2 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -65,8 +65,6 @@ if (NOT TARGET ${BOARD_TARGET})
       # linker file
       "LINKER:--script=${LD_FILE_gcc}"
       -L${NRFX_DIR}/mdk
-      # link map
-      "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
       # nanolib
       --specs=nosys.specs
       --specs=nano.specs
@@ -79,19 +77,8 @@ endif () # BOARD_TARGET
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_target TARGET)
-  #family_add_default_example_warnings(${TARGET})
-
-  # set output name to .elf
-  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
-
-  # run size after build
-  add_custom_command(TARGET ${TARGET} POST_BUILD
-    COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
-    )
-
-  # TOP is path to root directory
-  set(TOP "${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../..")
+function(family_configure_example TARGET)
+  family_support_configure_common(${TARGET})
 
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
@@ -161,13 +148,13 @@ function(family_add_freertos TARGET)
 endfunction()
 
 function(family_configure_device_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
 
 function(family_configure_host_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()
 
 function(family_configure_dual_usb_example TARGET)
-  family_configure_target(${TARGET})
+  family_configure_example(${TARGET})
 endfunction()

From 4c9605910f1f53b2517fff5f0cc02973260f0739 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 25 May 2023 21:27:26 +0700
Subject: [PATCH 1747/2085] update cmake with freertos

---
 hw/bsp/family_support.cmake                  |  85 ++++++----
 hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt   |   8 -
 hw/bsp/imxrt/family.cmake                    |  23 +--
 hw/bsp/lpc18/family.cmake                    |  23 +--
 hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h | 166 +++++++++++++++++++
 hw/bsp/lpc55/family.cmake                    |  33 ++--
 hw/bsp/mcx/family.cmake                      |  28 +---
 hw/bsp/nrf/family.cmake                      |  24 +--
 hw/bsp/rp2040/family.cmake                   |   4 +
 9 files changed, 240 insertions(+), 154 deletions(-)
 delete mode 100644 hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt
 create mode 100644 hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 760f2fbbc..5bd9a6d75 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -1,19 +1,15 @@
-if (TARGET _family_support_marker)
-    return()
-endif ()
-
-add_library(_family_support_marker INTERFACE)
+include_guard()
 
 include(CMakePrintHelpers)
 
 # Default to gcc
-if(NOT DEFINED TOOLCHAIN)
+if (NOT DEFINED TOOLCHAIN)
     set(TOOLCHAIN gcc)
-endif()
+endif ()
 
 if (NOT FAMILY)
     message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line")
-endif()
+endif ()
 
 if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
     message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
@@ -137,19 +133,19 @@ endfunction()
 
 
 function(family_support_configure_common TARGET)
-    # set output name to .elf
-    set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
+  # set output name to .elf
+  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
 
-    # run size after build
-    add_custom_command(TARGET ${TARGET} POST_BUILD
-      COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
-      )
+  # run size after build
+  add_custom_command(TARGET ${TARGET} POST_BUILD
+    COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
+    )
 
-    # Generate map file
-    target_link_options(${TARGET} PUBLIC
-      # link map
-      "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map"
-      )
+  # Generate map file
+  target_link_options(${TARGET} PUBLIC
+    # link map
+    "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map"
+    )
 endfunction()
 
 #  add_custom_command(TARGET ${TARGET} POST_BUILD
@@ -160,23 +156,23 @@ endfunction()
 
 # Add flash jlink target
 function(family_flash_jlink TARGET)
-    if (NOT DEFINED JLINKEXE)
-        set(JLINKEXE JLinkExe)
-    endif ()
+  if (NOT DEFINED JLINKEXE)
+    set(JLINKEXE JLinkExe)
+  endif ()
 
-    file(GENERATE
-      OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
-      CONTENT "halt
+  file(GENERATE
+    OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
+    CONTENT "halt
 loadfile $<TARGET_FILE:${TARGET}>
 r
 go
 exit"
-      )
+    )
 
-    add_custom_target(${TARGET}-jlink
-      DEPENDS ${TARGET}
-      COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
-      )
+  add_custom_target(${TARGET}-jlink
+    DEPENDS ${TARGET}
+    COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} -if swd -JTAGConf -1,-1 -speed auto -CommandFile ${CMAKE_CURRENT_BINARY_DIR}/${TARGET}.jlink
+    )
 endfunction()
 
 # Add flash pycod target
@@ -218,6 +214,35 @@ function(family_configure_host_example TARGET)
     # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
 endfunction()
 
+# Add freeRTOS support to example, can be overridden by FAMILY/family.cmake
+function(family_add_freertos TARGET)
+    # freeros config
+    if (NOT TARGET freertos_config)
+        add_library(freertos_config INTERFACE)
+        target_include_directories(freertos_config SYSTEM INTERFACE
+          ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig
+          )
+    endif()
+
+    # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable
+    # such as CMAKE_C_COMPILE_OBJECT
+    if (NOT TARGET freertos_kernel)
+        add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
+    endif ()
+
+    # Add FreeRTOS option to tinyusb_config
+    target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+      CFG_TUSB_OS=OPT_OS_FREERTOS
+      )
+    # link tinyusb with freeRTOS kernel
+    target_link_libraries(${TARGET}-tinyusb PUBLIC
+      freertos_kernel
+      )
+    target_link_libraries(${TARGET} PUBLIC
+      freertos_kernel
+      )
+endfunction()
+
 include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
 
 if (NOT FAMILY_MCUS)
diff --git a/hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt b/hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt
deleted file mode 100644
index 0bacaf824..000000000
--- a/hw/bsp/imxrt/FreeRTOSConfig/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-if (NOT TARGET freertos_config)
-  add_library(freertos_config INTERFACE)
-
-  # add path to FreeRTOSConfig.h
-  target_include_directories(freertos_config SYSTEM INTERFACE
-    ${CMAKE_CURRENT_LIST_DIR}
-    )
-endif()
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 0e55b825d..f9818cde6 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -75,6 +75,7 @@ if (NOT TARGET ${BOARD_TARGET})
   endif ()
 endif () # BOARD_TARGET
 
+
 #------------------------------------
 # Functions
 #------------------------------------
@@ -129,28 +130,6 @@ function(family_configure_example TARGET)
 endfunction()
 
 
-function(family_add_freertos TARGET)
-  # freertos_config
-  add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config)
-
-  ## freertos
-  if (NOT TARGET freertos_kernel)
-    add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
-  endif ()
-
-  # Add FreeRTOS option to tinyusb_config
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_OS=OPT_OS_FREERTOS
-    )
-  # link tinyusb with freeRTOS kernel
-  target_link_libraries(${TARGET}-tinyusb PUBLIC
-    freertos_kernel
-    )
-  target_link_libraries(${TARGET} PUBLIC
-    freertos_kernel
-    )
-endfunction()
-
 function(family_configure_device_example TARGET)
   family_configure_example(${TARGET})
 endfunction()
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index 29fa73d34..c47839a5c 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -62,6 +62,7 @@ if (NOT TARGET ${BOARD_TARGET})
   endif ()
 endif () # BOARD_TARGET
 
+
 #------------------------------------
 # Functions
 #------------------------------------
@@ -114,28 +115,6 @@ function(family_configure_example TARGET)
 endfunction()
 
 
-function(family_add_freertos TARGET)
-  # freertos_config
-  add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config)
-
-  ## freertos
-  if (NOT TARGET freertos_kernel)
-    add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
-  endif ()
-
-  # Add FreeRTOS option to tinyusb_config
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_OS=OPT_OS_FREERTOS
-    )
-  # link tinyusb with freeRTOS kernel
-  target_link_libraries(${TARGET}-tinyusb PUBLIC
-    freertos_kernel
-    )
-  target_link_libraries(${TARGET} PUBLIC
-    freertos_kernel
-    )
-endfunction()
-
 function(family_configure_device_example TARGET)
   family_configure_example(${TARGET})
 endfunction()
diff --git a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..4c6058d27
--- /dev/null
+++ b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// IAR assembler have limited preprocessor support and it only need following macros:
+#ifndef __IASMARM__
+// FIXME cause redundant-decls warnings
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU								        0
+#define configENABLE_FPU								        1
+#define configENABLE_TRUSTZONE					        0
+#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 363b7a9cd..d6ce0b781 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -18,6 +18,16 @@ set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
+#------------------------------------
+# freertos
+#------------------------------------
+if (NOT TARGET freertos_config)
+  add_library(freertos_config INTERFACE)
+  target_include_directories(freertos_config SYSTEM INTERFACE
+    ${CMAKE_CURRENT_LIST_DIR}/FreeRTOSConfig
+    )
+endif()
+
 
 #------------------------------------
 # BOARD_TARGET
@@ -72,6 +82,7 @@ if (NOT TARGET ${BOARD_TARGET})
   endif ()
 endif () # BOARD_TARGET
 
+
 #------------------------------------
 # Functions
 #------------------------------------
@@ -124,28 +135,6 @@ function(family_configure_example TARGET)
 endfunction()
 
 
-function(family_add_freertos TARGET)
-  # freertos_config
-  add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config)
-
-  ## freertos
-  if (NOT TARGET freertos_kernel)
-    add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
-  endif ()
-
-  # Add FreeRTOS option to tinyusb_config
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_OS=OPT_OS_FREERTOS
-    )
-  # link tinyusb with freeRTOS kernel
-  target_link_libraries(${TARGET}-tinyusb PUBLIC
-    freertos_kernel
-    )
-  target_link_libraries(${TARGET} PUBLIC
-    freertos_kernel
-    )
-endfunction()
-
 function(family_configure_device_example TARGET)
   family_configure_example(${TARGET})
 endfunction()
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index bc0dfe875..abca7c90e 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -67,6 +67,7 @@ if (NOT TARGET ${BOARD_TARGET})
   endif ()
 endif () # BOARD_TARGET
 
+
 #------------------------------------
 # Functions
 #------------------------------------
@@ -129,33 +130,6 @@ function(family_configure_example TARGET)
 endfunction()
 
 
-function(family_add_freertos TARGET)
-  # freertos_config
-  if (NOT TARGET freertos_config)
-    add_library(freertos_config INTERFACE)
-    target_include_directories(freertos_config SYSTEM INTERFACE
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig
-      )
-  endif()
-
-  ## freertos
-  if (NOT TARGET freertos_kernel)
-    add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
-  endif ()
-
-  # Add FreeRTOS option to tinyusb_config
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_OS=OPT_OS_FREERTOS
-    )
-  # link tinyusb with freeRTOS kernel
-  target_link_libraries(${TARGET}-tinyusb PUBLIC
-    freertos_kernel
-    )
-  target_link_libraries(${TARGET} PUBLIC
-    freertos_kernel
-    )
-endfunction()
-
 function(family_configure_device_example TARGET)
   family_configure_example(${TARGET})
 endfunction()
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 9d958fee2..59d4a7947 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -74,6 +74,7 @@ if (NOT TARGET ${BOARD_TARGET})
   endif ()
 endif () # BOARD_TARGET
 
+
 #------------------------------------
 # Functions
 #------------------------------------
@@ -121,32 +122,9 @@ function(family_configure_example TARGET)
 
   #---------- Flash ----------
   family_flash_jlink(${TARGET})
-
 endfunction()
 
 
-function(family_add_freertos TARGET)
-  # freertos_config
-  add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/FreeRTOSConfig ${CMAKE_CURRENT_BINARY_DIR}/freertos_config)
-
-  ## freertos
-  if (NOT TARGET freertos_kernel)
-    add_subdirectory(${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../../lib/FreeRTOS-Kernel ${CMAKE_CURRENT_BINARY_DIR}/freertos_kernel)
-  endif ()
-
-  # Add FreeRTOS option to tinyusb_config
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_OS=OPT_OS_FREERTOS
-    )
-  # link tinyusb with freeRTOS kernel
-  target_link_libraries(${TARGET}-tinyusb PUBLIC
-    freertos_kernel
-    )
-  target_link_libraries(${TARGET} PUBLIC
-    freertos_kernel
-    )
-endfunction()
-
 function(family_configure_device_example TARGET)
   family_configure_example(${TARGET})
 endfunction()
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 5d80ab66e..17f206c77 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -330,4 +330,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 					COMPILE_FLAGS "-Wno-cast-qual")
 		endif()
 	endfunction()
+
+	# rp2040 does not support freeRTOS example yet
+	function(family_add_freertos TARGET)
+	endfunction()
 endif()

From c0ecf8b50fe68a56b28bed98ecbfc6b236a848ef Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 May 2023 14:56:22 +0700
Subject: [PATCH 1748/2085] move set TOP to family_support.cmake

---
 hw/bsp/family_support.cmake | 3 +++
 hw/bsp/imxrt/family.cmake   | 3 ---
 hw/bsp/lpc18/family.cmake   | 2 --
 hw/bsp/lpc55/family.cmake   | 2 --
 hw/bsp/mcx/family.cmake     | 2 --
 hw/bsp/nrf/family.cmake     | 2 --
 hw/bsp/rp2040/family.cmake  | 4 ++--
 7 files changed, 5 insertions(+), 13 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 5bd9a6d75..68a21bc7d 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -2,6 +2,9 @@ include_guard()
 
 include(CMakePrintHelpers)
 
+# TOP is path to root directory
+set(TOP "${CMAKE_CURRENT_LIST_DIR}/../..")
+
 # Default to gcc
 if (NOT DEFINED TOOLCHAIN)
     set(TOOLCHAIN gcc)
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index f9818cde6..a681b0419 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -4,9 +4,6 @@ if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
 endif ()
 
-# TOP is path to root directory
-set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
-
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index c47839a5c..698120077 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -4,8 +4,6 @@ if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
 endif ()
 
-# TOP is path to root directory
-set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
 set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx)
 
 # toolchain set up
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index d6ce0b781..1b9c1a655 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -4,8 +4,6 @@ if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
 endif ()
 
-# TOP is path to root directory
-set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
 set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
 set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index abca7c90e..1719320e6 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -4,8 +4,6 @@ if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
 endif ()
 
-# TOP is path to root directory
-set(TOP ${CMAKE_CURRENT_LIST_DIR}/../../..)
 set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
 set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 59d4a7947..68b19b33b 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -4,8 +4,6 @@ if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
 endif ()
 
-# TOP is path to root directory
-set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
 set(NRFX_DIR ${TOP}/hw/mcu/nordic/nrfx)
 set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 17f206c77..28637e3ee 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -16,8 +16,8 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 	include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 	# TOP is absolute path to root directory of TinyUSB git repo
-	set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
-	get_filename_component(TOP "${TOP}" REALPATH)
+	#set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
+	#get_filename_component(TOP "${TOP}" REALPATH)
 
 	if (NOT PICO_TINYUSB_PATH)
 		set(PICO_TINYUSB_PATH ${TOP})

From b262164a35e9e305b67cb8d0c2188353db405200 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 May 2023 15:16:18 +0700
Subject: [PATCH 1749/2085] fix build with net_lwip_webserver example

---
 examples/device/CMakeLists.txt                |   7 +-
 .../device/net_lwip_webserver/CMakeLists.txt  | 164 +++++++++---------
 src/CMakeLists.txt                            |   2 +
 3 files changed, 88 insertions(+), 85 deletions(-)

diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index 89cfceeeb..5b077a5e1 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -22,12 +22,7 @@ family_add_subdirectory(hid_generic_inout)
 family_add_subdirectory(hid_multiple_interface)
 family_add_subdirectory(midi_test)
 family_add_subdirectory(msc_dual_lun)
-
-# FIXME temp skip net_lwip_webserver for imxrt for now
-if (NOT ${FAMILY} STREQUAL "imxrt" AND NOT ${FAMILY} STREQUAL "mcx")
-  family_add_subdirectory(net_lwip_webserver)
-endif()
-
+family_add_subdirectory(net_lwip_webserver)
 family_add_subdirectory(uac2_headset)
 family_add_subdirectory(usbtmc)
 family_add_subdirectory(video_capture)
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index e7338c809..5225f7c42 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -1,83 +1,89 @@
 cmake_minimum_required(VERSION 3.17)
 
-set(TOP "../../..")
-get_filename_component(TOP "${TOP}" REALPATH)
+include(${CMAKE_CURRENT_LIST_DIR}/../../../hw/bsp/family_support.cmake)
 
-if (EXISTS ${TOP}/lib/lwip/src)
-    include(${TOP}/hw/bsp/family_support.cmake)
-
-    # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
-    family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
-
-    project(${PROJECT} C CXX ASM)
-
-    # Checks this example is valid for the family and initializes the project
-    family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
-
-    add_executable(${PROJECT})
-
-    # Example source
-    target_sources(${PROJECT} PUBLIC
-            ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-            ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-            )
-
-    # Example include
-    target_include_directories(${PROJECT} PUBLIC
-            ${CMAKE_CURRENT_SOURCE_DIR}/src
-            ${TOP}/lib/lwip/src/include
-            ${TOP}/lib/lwip/src/include/ipv4
-            ${TOP}/lib/lwip/src/include/lwip/apps
-            ${TOP}/lib/networking
-            )
-
-    target_sources(${PROJECT} PUBLIC
-            ${TOP}/lib/lwip/src/core/altcp.c
-            ${TOP}/lib/lwip/src/core/altcp_alloc.c
-            ${TOP}/lib/lwip/src/core/altcp_tcp.c
-            ${TOP}/lib/lwip/src/core/def.c
-            ${TOP}/lib/lwip/src/core/dns.c
-            ${TOP}/lib/lwip/src/core/inet_chksum.c
-            ${TOP}/lib/lwip/src/core/init.c
-            ${TOP}/lib/lwip/src/core/ip.c
-            ${TOP}/lib/lwip/src/core/mem.c
-            ${TOP}/lib/lwip/src/core/memp.c
-            ${TOP}/lib/lwip/src/core/netif.c
-            ${TOP}/lib/lwip/src/core/pbuf.c
-            ${TOP}/lib/lwip/src/core/raw.c
-            ${TOP}/lib/lwip/src/core/stats.c
-            ${TOP}/lib/lwip/src/core/sys.c
-            ${TOP}/lib/lwip/src/core/tcp.c
-            ${TOP}/lib/lwip/src/core/tcp_in.c
-            ${TOP}/lib/lwip/src/core/tcp_out.c
-            ${TOP}/lib/lwip/src/core/timeouts.c
-            ${TOP}/lib/lwip/src/core/udp.c
-            ${TOP}/lib/lwip/src/core/ipv4/autoip.c
-            ${TOP}/lib/lwip/src/core/ipv4/dhcp.c
-            ${TOP}/lib/lwip/src/core/ipv4/etharp.c
-            ${TOP}/lib/lwip/src/core/ipv4/icmp.c
-            ${TOP}/lib/lwip/src/core/ipv4/igmp.c
-            ${TOP}/lib/lwip/src/core/ipv4/ip4.c
-            ${TOP}/lib/lwip/src/core/ipv4/ip4_addr.c
-            ${TOP}/lib/lwip/src/core/ipv4/ip4_frag.c
-            ${TOP}/lib/lwip/src/netif/ethernet.c
-            ${TOP}/lib/lwip/src/netif/slipif.c
-            ${TOP}/lib/lwip/src/apps/http/httpd.c
-            ${TOP}/lib/lwip/src/apps/http/fs.c
-            ${TOP}/lib/networking/dhserver.c
-            ${TOP}/lib/networking/dnserver.c
-            ${TOP}/lib/networking/rndis_reports.c
-            )
-
-    # due to warnings from other net source, we need to prevent error from some of the warnings options
-    target_compile_options(${PROJECT} PUBLIC
-        -Wno-error=null-dereference
-        -Wno-error=conversion
-        -Wno-error=sign-conversion
-        -Wno-error=sign-compare
-        )
-
-    # Configure compilation flags and libraries for the example... see the corresponding function
-    # in hw/bsp/FAMILY/family.cmake for details.
-    family_configure_device_example(${PROJECT})
+set(LWIP ${TOP}/lib/lwip)
+if (NOT EXISTS ${LWIP}/src)
+  MESSAGE(WARNING "lib/lwip submodule not found, please run 'python tools/get_deps.py lib/lwip' to fetch it")
+  return()
 endif()
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_LIST_DIR}/src/main.c
+  ${CMAKE_CURRENT_LIST_DIR}/src/usb_descriptors.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_LIST_DIR}/src
+  ${LWIP}/src/include
+  ${LWIP}/src/include/ipv4
+  ${LWIP}/src/include/lwip/apps
+  ${TOP}/lib/networking
+  )
+
+# lib/networking sources
+target_sources(${PROJECT} PUBLIC
+  ${TOP}/lib/networking/dhserver.c
+  ${TOP}/lib/networking/dnserver.c
+  ${TOP}/lib/networking/rndis_reports.c
+  )
+
+# lwip sources
+target_sources(${PROJECT} PUBLIC
+  ${LWIP}/src/core/altcp.c
+  ${LWIP}/src/core/altcp_alloc.c
+  ${LWIP}/src/core/altcp_tcp.c
+  ${LWIP}/src/core/def.c
+  ${LWIP}/src/core/dns.c
+  ${LWIP}/src/core/inet_chksum.c
+  ${LWIP}/src/core/init.c
+  ${LWIP}/src/core/ip.c
+  ${LWIP}/src/core/mem.c
+  ${LWIP}/src/core/memp.c
+  ${LWIP}/src/core/netif.c
+  ${LWIP}/src/core/pbuf.c
+  ${LWIP}/src/core/raw.c
+  ${LWIP}/src/core/stats.c
+  ${LWIP}/src/core/sys.c
+  ${LWIP}/src/core/tcp.c
+  ${LWIP}/src/core/tcp_in.c
+  ${LWIP}/src/core/tcp_out.c
+  ${LWIP}/src/core/timeouts.c
+  ${LWIP}/src/core/udp.c
+  ${LWIP}/src/core/ipv4/autoip.c
+  ${LWIP}/src/core/ipv4/dhcp.c
+  ${LWIP}/src/core/ipv4/etharp.c
+  ${LWIP}/src/core/ipv4/icmp.c
+  ${LWIP}/src/core/ipv4/igmp.c
+  ${LWIP}/src/core/ipv4/ip4.c
+  ${LWIP}/src/core/ipv4/ip4_addr.c
+  ${LWIP}/src/core/ipv4/ip4_frag.c
+  ${LWIP}/src/netif/ethernet.c
+  ${LWIP}/src/netif/slipif.c
+  ${LWIP}/src/apps/http/httpd.c
+  ${LWIP}/src/apps/http/fs.c
+  )
+
+# due to warnings from other net source, we need to prevent error from some of the warnings options
+target_compile_options(${PROJECT} PUBLIC
+  -Wno-error=null-dereference
+  -Wno-error=conversion
+  -Wno-error=sign-conversion
+  -Wno-error=sign-compare
+  )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 0b99d8919..0d2f0975b 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -34,6 +34,8 @@ function(add_tinyusb TARGET)
     )
   target_include_directories(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    # TODO for net driver, should be removed/changed
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../lib/networking
     )
   # enable all possible warnings
   target_compile_options(${TARGET} PUBLIC

From 1d857605b79156a10d14aeb837a9e82bbb81e87c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 May 2023 15:25:55 +0700
Subject: [PATCH 1750/2085] use get_deps.py

---
 .github/workflows/build_aarch64.yml | 2 +-
 .github/workflows/build_arm.yml     | 2 +-
 .github/workflows/build_iar.yml     | 2 +-
 .github/workflows/build_msp430.yml  | 2 +-
 .github/workflows/build_renesas.yml | 2 +-
 .github/workflows/build_riscv.yml   | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/build_aarch64.yml b/.github/workflows/build_aarch64.yml
index 77d3778d7..6ac7ad015 100644
--- a/.github/workflows/build_aarch64.yml
+++ b/.github/workflows/build_aarch64.yml
@@ -70,7 +70,7 @@ jobs:
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
     - name: Get Dependencies
-      run: python3 tools/get_family_deps.py ${{ matrix.family }}
+      run: python3 tools/get_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 1db9586af..e3b9a9686 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -77,7 +77,7 @@ jobs:
         echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
 
     - name: Get Dependencies
-      run: python3 tools/get_family_deps.py ${{ matrix.family }}
+      run: python3 tools/get_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 8c3b57e10..3da5ed40f 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -44,7 +44,7 @@ jobs:
       uses: actions/checkout@v3
 
     - name: Get Dependencies
-      run: python3 tools/get_family_deps.py ${{ matrix.family }}
+      run: python3 tools/get_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }} CC=iccarm
diff --git a/.github/workflows/build_msp430.yml b/.github/workflows/build_msp430.yml
index 5424a88d6..c62056940 100644
--- a/.github/workflows/build_msp430.yml
+++ b/.github/workflows/build_msp430.yml
@@ -68,7 +68,7 @@ jobs:
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
     - name: Get Dependencies
-      run: python3 tools/get_family_deps.py ${{ matrix.family }}
+      run: python3 tools/get_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_renesas.yml b/.github/workflows/build_renesas.yml
index 3f0a4b694..66b98a71b 100644
--- a/.github/workflows/build_renesas.yml
+++ b/.github/workflows/build_renesas.yml
@@ -68,7 +68,7 @@ jobs:
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
     - name: Get Dependencies
-      run: python3 tools/get_family_deps.py ${{ matrix.family }}
+      run: python3 tools/get_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}
diff --git a/.github/workflows/build_riscv.yml b/.github/workflows/build_riscv.yml
index 8682d655a..8ec549072 100644
--- a/.github/workflows/build_riscv.yml
+++ b/.github/workflows/build_riscv.yml
@@ -69,7 +69,7 @@ jobs:
       run: echo >> $GITHUB_PATH `echo ~/cache/toolchain/*/bin`
 
     - name: Get Dependencies
-      run: python3 tools/get_family_deps.py ${{ matrix.family }}
+      run: python3 tools/get_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }}

From 05cc342dfa258a2c5e381788009b84445b6e9856 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 May 2023 15:45:55 +0700
Subject: [PATCH 1751/2085] update deps, rename kinetis_k32 to k32l

---
 .github/workflows/build_arm.yml                             | 2 +-
 .../boards/frdm_k32l2a4s/board.h                            | 0
 .../boards/frdm_k32l2a4s/board.mk                           | 0
 .../boards/frdm_k32l2a4s/frdm_k32l2a4s.c                    | 0
 .../boards/frdm_k32l2b/board.h                              | 0
 .../boards/frdm_k32l2b/board.mk                             | 0
 .../boards/frdm_k32l2b/frdm_k32l2b.c                        | 0
 .../boards/kuiic/K32L2B31xxxxA_flash.ld                     | 0
 hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/kuiic/board.h   | 0
 hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/kuiic/board.mk  | 0
 hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/kuiic/kuiic.c   | 0
 hw/bsp/{kinetis_k32 => kinetis_k32l}/family.mk              | 0
 hw/bsp/saml2x/family.mk                                     | 6 +++---
 tools/get_deps.py                                           | 5 +++--
 14 files changed, 7 insertions(+), 6 deletions(-)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/frdm_k32l2a4s/board.h (100%)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/frdm_k32l2a4s/board.mk (100%)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/frdm_k32l2a4s/frdm_k32l2a4s.c (100%)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/frdm_k32l2b/board.h (100%)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/frdm_k32l2b/board.mk (100%)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/frdm_k32l2b/frdm_k32l2b.c (100%)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/kuiic/K32L2B31xxxxA_flash.ld (100%)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/kuiic/board.h (100%)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/kuiic/board.mk (100%)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/boards/kuiic/kuiic.c (100%)
 rename hw/bsp/{kinetis_k32 => kinetis_k32l}/family.mk (100%)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index e3b9a9686..8fbaba4c6 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -34,7 +34,7 @@ jobs:
         family:
         # Alphabetical order
         - 'broadcom_32bit'
-        - 'kinetis_k32 kinetis_kl'
+        - 'kinetis_k32l kinetis_kl'
         - 'lpc11 lpc13 lpc15 lpc17 lpc18'
         - 'lpc51 lpc54 lpc55'
         - 'mm32 msp432e4'
diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.h
similarity index 100%
rename from hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.h
rename to hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.h
diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.mk
similarity index 100%
rename from hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/board.mk
rename to hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.mk
diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
similarity index 100%
rename from hw/bsp/kinetis_k32/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
rename to hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.h b/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.h
similarity index 100%
rename from hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.h
rename to hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.h
diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.mk
similarity index 100%
rename from hw/bsp/kinetis_k32/boards/frdm_k32l2b/board.mk
rename to hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.mk
diff --git a/hw/bsp/kinetis_k32/boards/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/frdm_k32l2b.c
similarity index 100%
rename from hw/bsp/kinetis_k32/boards/frdm_k32l2b/frdm_k32l2b.c
rename to hw/bsp/kinetis_k32l/boards/frdm_k32l2b/frdm_k32l2b.c
diff --git a/hw/bsp/kinetis_k32/boards/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kinetis_k32l/boards/kuiic/K32L2B31xxxxA_flash.ld
similarity index 100%
rename from hw/bsp/kinetis_k32/boards/kuiic/K32L2B31xxxxA_flash.ld
rename to hw/bsp/kinetis_k32l/boards/kuiic/K32L2B31xxxxA_flash.ld
diff --git a/hw/bsp/kinetis_k32/boards/kuiic/board.h b/hw/bsp/kinetis_k32l/boards/kuiic/board.h
similarity index 100%
rename from hw/bsp/kinetis_k32/boards/kuiic/board.h
rename to hw/bsp/kinetis_k32l/boards/kuiic/board.h
diff --git a/hw/bsp/kinetis_k32/boards/kuiic/board.mk b/hw/bsp/kinetis_k32l/boards/kuiic/board.mk
similarity index 100%
rename from hw/bsp/kinetis_k32/boards/kuiic/board.mk
rename to hw/bsp/kinetis_k32l/boards/kuiic/board.mk
diff --git a/hw/bsp/kinetis_k32/boards/kuiic/kuiic.c b/hw/bsp/kinetis_k32l/boards/kuiic/kuiic.c
similarity index 100%
rename from hw/bsp/kinetis_k32/boards/kuiic/kuiic.c
rename to hw/bsp/kinetis_k32l/boards/kuiic/kuiic.c
diff --git a/hw/bsp/kinetis_k32/family.mk b/hw/bsp/kinetis_k32l/family.mk
similarity index 100%
rename from hw/bsp/kinetis_k32/family.mk
rename to hw/bsp/kinetis_k32l/family.mk
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index 91c2cfa61..98071737a 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -1,5 +1,5 @@
 UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/microchip
+DEPS_SUBMODULES += hw/mcu/microchip
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
@@ -32,14 +32,14 @@ SRC_C += \
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(MCU_DIR)/ \
+	$(TOP)/$(MCU_DIR) \
+	$(TOP)/$(MCU_DIR)/CMSIS/Include \
 	$(TOP)/$(MCU_DIR)/config \
 	$(TOP)/$(MCU_DIR)/include \
 	$(TOP)/$(MCU_DIR)/hal/include \
 	$(TOP)/$(MCU_DIR)/hal/utils/include \
 	$(TOP)/$(MCU_DIR)/hpl/port \
 	$(TOP)/$(MCU_DIR)/hri \
-	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
 
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 6db5224a4..4f8c0355c 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -169,8 +169,9 @@ deps_optional = {
                             'ch32v307'],
     'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
                     '20285262657d1b482d132d20d755c8c330d55c1f',
-                    'imxrt mcx stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l0 stm32l1 '
-                    'stm32l4 stm32l5 stm32u5 stm32wb'],
+                    'imxrt kinetis_k32l lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra '
+                    'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 '
+                    'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'],
     'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
                          'e73e04ca63495672d955f9268e003cffe168fcd8',
                          'lpc55'],

From 7ac85d08c7aa59f35cbbf2657dd9be68d46e1fdc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 May 2023 16:37:47 +0700
Subject: [PATCH 1752/2085] move lpc18 and rp2040 to cmake workflow since
 rp2040 often failed randomly with make

---
 .github/workflows/build_arm.yml               |   3 +-
 .github/workflows/cmake_arm.yml               |  19 +-
 hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h  |   8 +-
 hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h  | 166 ++++++++++++++++++
 hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h  |   8 +-
 .../boards/double_m33_express/board.cmake     |  16 ++
 hw/bsp/lpc55/family.cmake                     |  14 +-
 hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h    |   8 +-
 hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h    | 166 ++++++++++++++++++
 hw/bsp/saml2x/family.mk                       |   4 +-
 src/CMakeLists.txt                            |  47 ++++-
 tools/get_deps.py                             |   4 +-
 12 files changed, 429 insertions(+), 34 deletions(-)
 create mode 100644 hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/lpc55/boards/double_m33_express/board.cmake
 create mode 100644 hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 8fbaba4c6..42c8eb7ce 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -35,12 +35,11 @@ jobs:
         # Alphabetical order
         - 'broadcom_32bit'
         - 'kinetis_k32l kinetis_kl'
-        - 'lpc11 lpc13 lpc15 lpc17 lpc18'
+        - 'lpc11 lpc13 lpc15 lpc17'
         - 'lpc51 lpc54 lpc55'
         - 'mm32 msp432e4'
         - 'nrf'
         - 'ra'
-        - 'rp2040'
         - 'samd11 samd21'
         - 'samd51 same5x'
         - 'saml2x'
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index e7991252d..f3989f239 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -32,9 +32,11 @@ jobs:
       fail-fast: false
       matrix:
         family:
-        # Alphabetical order
-        - 'mcx'
-        - 'imxrt'
+          # Alphabetical order
+          - 'lpc18'
+          - 'mcx'
+          - 'imxrt'
+          - 'rp2040'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
@@ -52,8 +54,19 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
+    - name: Checkout pico-sdk for rp2040
+      if: matrix.family == 'rp2040'
+      uses: actions/checkout@v3
+      with:
+        repository: raspberrypi/pico-sdk
+        ref: develop
+        path: pico-sdk
+
     - name: Get Dependencies
       run: python3 tools/get_deps.py ${{ matrix.family }}
 
     - name: Build
       run: python tools/build_cmake.py ${{ matrix.family }}
+      env:
+        # for rp2040, there is no harm if defined for other families
+        PICO_SDK_PATH: ${{ github.workspace }}/pico-sdk
diff --git a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
index c8d94f9ed..c1928fbcd 100644
--- a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
@@ -49,10 +49,10 @@ extern uint32_t SystemCoreClock;
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU								        0
-#define configENABLE_FPU								        1
-#define configENABLE_TRUSTZONE					        0
-#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+#define configENABLE_MPU						0
+#define configENABLE_FPU						1
+#define configENABLE_TRUSTZONE					0
+#define configMINIMAL_SECURE_STACK_SIZE			(1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..323c1a0a4
--- /dev/null
+++ b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// IAR assembler have limited preprocessor support and it only need following macros:
+#ifndef __IASMARM__
+// FIXME cause redundant-decls warnings
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU						0
+#define configENABLE_FPU						0
+#define configENABLE_TRUSTZONE					0
+#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
index 4c6058d27..421106f08 100644
--- a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
@@ -49,10 +49,10 @@ extern uint32_t SystemCoreClock;
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU								        0
-#define configENABLE_FPU								        1
-#define configENABLE_TRUSTZONE					        0
-#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+#define configENABLE_MPU						0
+#define configENABLE_FPU						1
+#define configENABLE_TRUSTZONE					0
+#define configMINIMAL_SECURE_STACK_SIZE			(1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.cmake b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
new file mode 100644
index 000000000..7c46c075e
--- /dev/null
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT LPC55S69)
+set(MCU_CORE LPC55S69_cm33_core0)
+
+set(JLINK_DEVICE LPC55S69)
+set(PYOCD_TARGET LPC55S69)
+set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
+
+set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC55S69JBD100_cm33_core0
+    # port 1 is highspeed
+    BOARD_TUD_RHPORT=1
+    )
+endfunction()
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 1b9c1a655..77a2b821e 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -34,8 +34,6 @@ endif()
 set(BOARD_TARGET board_${BOARD})
 if (NOT TARGET ${BOARD_TARGET})
   add_library(${BOARD_TARGET} STATIC
-    # external driver
-    #lib/sct_neopixel/sct_neopixel.c
     # driver
     ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
     ${SDK_DIR}/drivers/common/fsl_common_arm.c
@@ -48,15 +46,17 @@ if (NOT TARGET ${BOARD_TARGET})
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
     )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
-    CFG_TUSB_MCU=OPT_MCU_LPC55XX
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
+    ${TOP}/lib/sct_neopixel
     # driver
     ${SDK_DIR}/drivers/common
     ${SDK_DIR}/drivers/flexcomm
     ${SDK_DIR}/drivers/lpc_iocon
     ${SDK_DIR}/drivers/lpc_gpio
     ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/sctimer
     # mcu
     ${CMSIS_DIR}/CMSIS/Core/Include
     ${SDK_DIR}/devices/${MCU_VARIANT}
@@ -64,13 +64,17 @@ if (NOT TARGET ${BOARD_TARGET})
     )
   update_board(${BOARD_TARGET})
 
+  if (NOT DEFINED LD_FILE_${TOOLCHAIN})
+    set(LD_FILE_gcc ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+  endif ()
+
   if (TOOLCHAIN STREQUAL "gcc")
     target_sources(${BOARD_TARGET} PUBLIC
       ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
       )
     target_link_options(${BOARD_TARGET} PUBLIC
       # linker file
-      "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
+      "LINKER:--script=${LD_FILE_gcc}"
       # nanolib
       --specs=nosys.specs
       --specs=nano.specs
@@ -95,6 +99,8 @@ function(family_configure_example TARGET)
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    # external driver
+    ${TOP}/lib/sct_neopixel/sct_neopixel.c
     )
   target_include_directories(${TARGET} PUBLIC
     # family, hw, board
diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
index 4c6058d27..421106f08 100644
--- a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
@@ -49,10 +49,10 @@ extern uint32_t SystemCoreClock;
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU								        0
-#define configENABLE_FPU								        1
-#define configENABLE_TRUSTZONE					        0
-#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+#define configENABLE_MPU						0
+#define configENABLE_FPU						1
+#define configENABLE_TRUSTZONE					0
+#define configMINIMAL_SECURE_STACK_SIZE			(1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..421106f08
--- /dev/null
+++ b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// IAR assembler have limited preprocessor support and it only need following macros:
+#ifndef __IASMARM__
+// FIXME cause redundant-decls warnings
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU						0
+#define configENABLE_FPU						1
+#define configENABLE_TRUSTZONE					0
+#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index 98071737a..62e5f8f4a 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -1,5 +1,5 @@
 UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES += hw/mcu/microchip
+DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/microchip
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
@@ -33,13 +33,13 @@ SRC_C += \
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/CMSIS/Include \
 	$(TOP)/$(MCU_DIR)/config \
 	$(TOP)/$(MCU_DIR)/include \
 	$(TOP)/$(MCU_DIR)/hal/include \
 	$(TOP)/$(MCU_DIR)/hal/utils/include \
 	$(TOP)/$(MCU_DIR)/hpl/port \
 	$(TOP)/$(MCU_DIR)/hri \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
 
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 0d2f0975b..396737ed5 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -1,11 +1,12 @@
-# TODO make tinyusb as library that depends on 'tusb_config' interface that exposes the tusb_config.h file
-# This file is WIP and should not used yet
+# TODO more docs and example on how to use this file
+# Usage: requires target tinyusb_config which expose tusb_config.h file
+# TINYUSB_TARGET_PREFIX and TINYUSB_TARGET_SUFFIX can be used to change the name of the target
 
 cmake_minimum_required(VERSION 3.17)
 
-# Add tinyusb to a target
+# Add tinyusb to a target, if user don't want to compile tinyusb as a library
 function(add_tinyusb TARGET)
-  target_sources(${TARGET} PUBLIC
+  target_sources(${TARGET} PRIVATE
     # common
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/common/tusb_fifo.c
@@ -37,11 +38,39 @@ function(add_tinyusb TARGET)
     # TODO for net driver, should be removed/changed
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../lib/networking
     )
-  # enable all possible warnings
-  target_compile_options(${TARGET} PUBLIC
-    )
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${TARGET} PRIVATE
+      -Wall
+      -Wextra
+      -Werror
+      -Wfatal-errors
+      -Wdouble-promotion
+      -Wstrict-prototypes
+      -Wstrict-overflow
+      -Werror-implicit-function-declaration
+      -Wfloat-equal
+      -Wundef
+      -Wshadow
+      -Wwrite-strings
+      -Wsign-compare
+      -Wmissing-format-attribute
+      -Wunreachable-code
+      -Wcast-align
+      -Wcast-function-type
+      -Wcast-qual
+      -Wnull-dereference
+      -Wuninitialized
+      -Wunused
+      -Wreturn-type
+      -Wredundant-decls
+      )
+  endif ()
 endfunction()
 
+#------------------------------------
+# TinyUSB as library target
+#------------------------------------
 set(TINYUSB_TARGET "tinyusb")
 set(TINYUSB_CONFIG_TARGET "tinyusb_config")
 
@@ -58,12 +87,12 @@ endif ()
 add_library(${TINYUSB_TARGET} STATIC)
 add_tinyusb(${TINYUSB_TARGET})
 
-# Link with tinyusb_config target
-
+# Check if tinyusb_config target is defined
 if (NOT TARGET ${TINYUSB_CONFIG_TARGET})
   message(FATAL_ERROR "${TINYUSB_CONFIG_TARGET} target is not defined")
 endif()
 
+# Link with tinyusb_config target
 target_link_libraries(${TINYUSB_TARGET} PUBLIC
   ${TINYUSB_CONFIG_TARGET}
   )
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 4f8c0355c..b16bf7005 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -52,7 +52,7 @@ deps_optional = {
                            'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
     'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
                             '950819b7de9b32f92c3edf396bc5ffb8d66e7009',
-                            'kinetis_k32 lpc51 lpc54 lpc55 mcx imxrt'],
+                            'kinetis_k32l lpc51 lpc54 lpc55 mcx imxrt'],
     'hw/mcu/nxp/nxp_sdk': ['https://github.com/hathach/nxp_sdk.git',
                            '845c8fc49b6fb660f06a5c45225494eacb06f00c',
                            'kinetis_kl'],
@@ -169,7 +169,7 @@ deps_optional = {
                             'ch32v307'],
     'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
                     '20285262657d1b482d132d20d755c8c330d55c1f',
-                    'imxrt kinetis_k32l lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra '
+                    'imxrt kinetis_k32l lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
                     'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 '
                     'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'],
     'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',

From 7fb74a33a113a0acd44b89863435dd6df1ee3393 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 May 2023 16:44:29 +0700
Subject: [PATCH 1753/2085] forgot to move hw test

---
 .github/workflows/build_arm.yml | 75 +--------------------------------
 .github/workflows/cmake_arm.yml | 73 ++++++++++++++++++++++++++++++++
 2 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 42c8eb7ce..3a2daab08 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -90,24 +90,11 @@ jobs:
           find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
         done
 
-    # Upload binaries for rp2040/stm32l412nucleo hardware test with self-hosted
-
-    - name: Prepare rp2040 Artifacts
-      if: contains(matrix.family, 'rp2040') && github.repository_owner == 'hathach'
-      run: find examples/ -name "*.elf" -exec mv {} . \;
-
+    # Upload binaries for hardware test with self-hosted
     - name: Prepare stm32l412nucleo Artifacts
       if: contains(matrix.family, 'stm32l4')
       run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
 
-    - name: Upload Artifacts for rp2040
-      if: contains(matrix.family,'rp2040') && github.repository_owner == 'hathach'
-      uses: actions/upload-artifact@v3
-      with:
-        name: rp2040
-        path: |
-          *.elf
-
     - name: Upload Artifacts for stm32l412nucleo
       if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach'
       uses: actions/upload-artifact@v3
@@ -116,66 +103,6 @@ jobs:
         path: |
           *.elf
 
-  # ---------------------------------------
-  # Hardware in the loop (HIL)
-  # Current self-hosted instance is running on an RPI4 with
-  # - pico + pico-probe connected via USB
-  # - pico-probe is /dev/ttyACM0
-  # ---------------------------------------
-  hw-rp2040-test:
-    # run only with hathach's commit due to limited resource on RPI4
-    if: github.repository_owner == 'hathach'
-    needs: build-arm
-    runs-on: [self-hosted, Linux, ARM64, rp2040]
-
-    steps:
-    - name: Clean workspace
-      run: |
-        echo "Cleaning up previous run"
-        rm -rf "${{ github.workspace }}"
-        mkdir -p "${{ github.workspace }}"
-
-    - name: Download rp2040 Artifacts
-      uses: actions/download-artifact@v3
-      with:
-        name: rp2040
-
-    - name: Create flash.sh
-      run: |
-        echo > flash.sh 'cmdout=$(openocd -f "interface/cmsis-dap.cfg" -f "target/rp2040.cfg" -c "adapter speed 5000" -c "program $1 reset exit")'
-        echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
-        chmod +x flash.sh
-
-    - name: Test cdc_dual_ports
-      run: |
-        ./flash.sh cdc_dual_ports.elf
-        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-
-    - name: Test cdc_msc
-      run: |
-        ./flash.sh cdc_msc.elf
-        readme='/media/pi/TinyUSB MSC/README.TXT'
-        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -f "$readme" && echo "$readme exists"
-        cat "$readme"
-
-    - name: Test dfu
-      run: |
-        ./flash.sh dfu.elf
-        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
-        dfu-util -d cafe -a 0 -U dfu0
-        dfu-util -d cafe -a 1 -U dfu1
-        grep "TinyUSB DFU! - Partition 0" dfu0
-        grep "TinyUSB DFU! - Partition 1" dfu1
-
-    - name: Test dfu_runtime
-      run: |
-        ./flash.sh dfu_runtime.elf
-        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
-
   # ---------------------------------------
   # Hardware in the loop (HIL)
   # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index f3989f239..b3f1bd410 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -70,3 +70,76 @@ jobs:
       env:
         # for rp2040, there is no harm if defined for other families
         PICO_SDK_PATH: ${{ github.workspace }}/pico-sdk
+
+    # Upload binaries for hardware test with self-hosted
+    - name: Prepare rp2040 Artifacts
+      if: contains(matrix.family, 'rp2040') && github.repository_owner == 'hathach'
+      run: find examples/ -name "*.elf" -exec mv {} . \;
+
+    - name: Upload Artifacts for rp2040
+      if: contains(matrix.family,'rp2040') && github.repository_owner == 'hathach'
+      uses: actions/upload-artifact@v3
+      with:
+        name: rp2040
+        path: |
+          *.elf
+
+  # ---------------------------------------
+  # Hardware in the loop (HIL)
+  # Current self-hosted instance is running on an RPI4 with
+  # - pico + pico-probe connected via USB
+  # - pico-probe is /dev/ttyACM0
+  # ---------------------------------------
+  hw-rp2040-test:
+    # run only with hathach's commit due to limited resource on RPI4
+    if: github.repository_owner == 'hathach'
+    needs: build-arm
+    runs-on: [self-hosted, Linux, ARM64, rp2040]
+
+    steps:
+      - name: Clean workspace
+        run: |
+          echo "Cleaning up previous run"
+          rm -rf "${{ github.workspace }}"
+          mkdir -p "${{ github.workspace }}"
+
+      - name: Download rp2040 Artifacts
+        uses: actions/download-artifact@v3
+        with:
+          name: rp2040
+
+      - name: Create flash.sh
+        run: |
+          echo > flash.sh 'cmdout=$(openocd -f "interface/cmsis-dap.cfg" -f "target/rp2040.cfg" -c "adapter speed 5000" -c "program $1 reset exit")'
+          echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
+          chmod +x flash.sh
+
+      - name: Test cdc_dual_ports
+        run: |
+          ./flash.sh cdc_dual_ports.elf
+          while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
+          test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+          test -e /dev/ttyACM2 && echo "ttyACM2 exists"
+
+      - name: Test cdc_msc
+        run: |
+          ./flash.sh cdc_msc.elf
+          readme='/media/pi/TinyUSB MSC/README.TXT'
+          while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
+          test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+          test -f "$readme" && echo "$readme exists"
+          cat "$readme"
+
+      - name: Test dfu
+        run: |
+          ./flash.sh dfu.elf
+          while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
+          dfu-util -d cafe -a 0 -U dfu0
+          dfu-util -d cafe -a 1 -U dfu1
+          grep "TinyUSB DFU! - Partition 0" dfu0
+          grep "TinyUSB DFU! - Partition 1" dfu1
+
+      - name: Test dfu_runtime
+        run: |
+          ./flash.sh dfu_runtime.elf
+          while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done

From c88e7481be0a6a55bf8af0a48950892aba05eaee Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 May 2023 17:15:54 +0700
Subject: [PATCH 1754/2085] retry hw test

---
 .github/workflows/cmake_arm.yml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index b3f1bd410..2070c5061 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -74,7 +74,11 @@ jobs:
     # Upload binaries for hardware test with self-hosted
     - name: Prepare rp2040 Artifacts
       if: contains(matrix.family, 'rp2040') && github.repository_owner == 'hathach'
-      run: find examples/ -name "*.elf" -exec mv {} . \;
+      working-directory: ${{github.workspace}}/cmake-build-ci-raspberry_pi_pico
+      run: |
+        find device/ -name "*.elf" -exec mv {} . \;
+        # find host/ -name "*.elf" -exec mv {} . \;
+        # find dual/ -name "*.elf" -exec mv {} . \;
 
     - name: Upload Artifacts for rp2040
       if: contains(matrix.family,'rp2040') && github.repository_owner == 'hathach'

From 4bd02fb04d52dbd1c2e0f1fe8b18afbd299e46cd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 May 2023 18:54:14 +0700
Subject: [PATCH 1755/2085] more test

---
 .github/workflows/cmake_arm.yml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 2070c5061..ed00ee4dc 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -76,6 +76,8 @@ jobs:
       if: contains(matrix.family, 'rp2040') && github.repository_owner == 'hathach'
       working-directory: ${{github.workspace}}/cmake-build-ci-raspberry_pi_pico
       run: |
+        tree -L 3
+        find device/ -name "*.elf"
         find device/ -name "*.elf" -exec mv {} . \;
         # find host/ -name "*.elf" -exec mv {} . \;
         # find dual/ -name "*.elf" -exec mv {} . \;

From 59ad5c59dfe1d9dbef033a772d2d5c474c22c53e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 26 May 2023 18:58:21 +0700
Subject: [PATCH 1756/2085] fix artifacts location

---
 .github/workflows/cmake_arm.yml | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index ed00ee4dc..ccca0c9be 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -76,11 +76,9 @@ jobs:
       if: contains(matrix.family, 'rp2040') && github.repository_owner == 'hathach'
       working-directory: ${{github.workspace}}/cmake-build-ci-raspberry_pi_pico
       run: |
-        tree -L 3
-        find device/ -name "*.elf"
-        find device/ -name "*.elf" -exec mv {} . \;
-        # find host/ -name "*.elf" -exec mv {} . \;
-        # find dual/ -name "*.elf" -exec mv {} . \;
+        find device/ -name "*.elf" -exec mv {} ../ \;
+        # find host/ -name "*.elf" -exec mv {} ../ \;
+        # find dual/ -name "*.elf" -exec mv {} ../ \;
 
     - name: Upload Artifacts for rp2040
       if: contains(matrix.family,'rp2040') && github.repository_owner == 'hathach'

From acfaa4494faccd615475e4ae9d3df940ed13d7af Mon Sep 17 00:00:00 2001
From: gitlab <georgebochileanu@gmail.com>
Date: Sun, 28 May 2023 15:40:01 +0100
Subject: [PATCH 1757/2085] Fixes bug in tuh_msc_ready

---
 src/class/msc/msc_host.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 138443de4..d32c0adb0 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -118,7 +118,7 @@ bool tuh_msc_mounted(uint8_t dev_addr)
 bool tuh_msc_ready(uint8_t dev_addr)
 {
   msch_interface_t* p_msc = get_itf(dev_addr);
-  return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in);
+  return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in) && !usbh_edpt_busy(dev_addr, p_msc->ep_out);
 }
 
 //--------------------------------------------------------------------+

From 8ad024e51bbc663678d8a357f91021bd39222246 Mon Sep 17 00:00:00 2001
From: Ivo Popov <popov.ivo@gmail.com>
Date: Sun, 9 Apr 2023 19:10:01 -0400
Subject: [PATCH 1758/2085] Even when we get an empty "status change" interrupt
 from the hub, schedule another interrupt poll.

During enumeration, when there are multiple devices attached to the
hub as it's plugged into the Pi Pico, enumeration hangs, because we
get a "status change" callback with value zero. With this patch, we
retry several times on "zero" status change callbacks, until
eventually we succeed.

This is the cheapo hub that exhibits this behavior, but I assume it's
not the only one: https://www.amazon.com/gp/product/B083RQMC7S.

While debugging this, I consulted the implementation in the Linux
kernel. There, hub setup explicitly checks each port individually,
before starting to depend on "status change" interrupts:
https://elixir.bootlin.com/linux/latest/source/drivers/usb/core/hub.c#L1133.
We probably should do something like that here, but it's a much bigger
change.
---
 src/host/hub.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/host/hub.c b/src/host/hub.c
index 85bf22b3e..5b2db547d 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -361,6 +361,13 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
         break;
       }
     }
+
+    // The status change event was neither for the hub, nor for any of
+    // its ports. (For example `p_hub->status_change == 0`.) This
+    // shouldn't happen, but it does with some devices. Initiate the
+    // next interrupt poll here, because we've scheduled no other work
+    // whose completion can initiate it.
+    hub_edpt_status_xfer(dev_addr);
   }
 
   // NOTE: next status transfer is queued by usbh.c after handling this request

From 5c428d35a61f7d877cba19d9e094bd519ae91997 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 29 May 2023 13:27:20 +0700
Subject: [PATCH 1759/2085] check status_change is not zero first

---
 src/host/hub.c | 42 ++++++++++++++++++------------------------
 1 file changed, 18 insertions(+), 24 deletions(-)

diff --git a/src/host/hub.c b/src/host/hub.c
index 5b2db547d..0807c2023 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -327,51 +327,45 @@ static void connection_clear_conn_change_complete (tuh_xfer_t* xfer);
 static void connection_port_reset_complete (tuh_xfer_t* xfer);
 
 // callback as response of interrupt endpoint polling
-bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports
   (void) ep_addr;
   TU_ASSERT(result == XFER_RESULT_SUCCESS);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
 
-  TU_LOG2("  Hub Status Change = 0x%02X\r\n", p_hub->status_change);
+  uint8_t const status_change = p_hub->status_change;
+  TU_LOG2("  Hub Status Change = 0x%02X\r\n", status_change);
 
-  // Hub bit 0 is for the hub device events
-  if (tu_bit_test(p_hub->status_change, 0))
-  {
-    if (hub_port_get_status(dev_addr, 0, &p_hub->hub_status, hub_get_status_complete, 0) == false)
-    {
+  if ( status_change == 0 ) {
+    // The status change event was neither for the hub, nor for any of its ports.
+    // This shouldn't happen, but it does with some devices.
+    // Initiate the next interrupt poll here.
+    hub_edpt_status_xfer(dev_addr);
+    return true;
+  }
+
+  if (tu_bit_test(status_change, 0)) {
+    // Hub bit 0 is for the hub device events
+    if (hub_port_get_status(dev_addr, 0, &p_hub->hub_status, hub_get_status_complete, 0) == false) {
       //Hub status control transfer failed, retry
       hub_edpt_status_xfer(dev_addr);
     }
   }
-  else
-  {
+  else {
     // Hub bits 1 to n are hub port events
-    for (uint8_t port=1; port <= p_hub->port_count; port++)
-    {
-      if ( tu_bit_test(p_hub->status_change, port) )
-      {
-        if (hub_port_get_status(dev_addr, port, &p_hub->port_status, hub_port_get_status_complete, 0) == false)
-        {
+    for (uint8_t port=1; port <= p_hub->port_count; port++) {
+      if ( tu_bit_test(status_change, port) ) {
+        if (hub_port_get_status(dev_addr, port, &p_hub->port_status, hub_port_get_status_complete, 0) == false) {
           //Hub status control transfer failed, retry
           hub_edpt_status_xfer(dev_addr);
         }
         break;
       }
     }
-
-    // The status change event was neither for the hub, nor for any of
-    // its ports. (For example `p_hub->status_change == 0`.) This
-    // shouldn't happen, but it does with some devices. Initiate the
-    // next interrupt poll here, because we've scheduled no other work
-    // whose completion can initiate it.
-    hub_edpt_status_xfer(dev_addr);
   }
 
   // NOTE: next status transfer is queued by usbh.c after handling this request
-
   return true;
 }
 

From 20ef6c4ef7f7fa7130352ae0c0984692a9719b35 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 29 May 2023 13:29:11 +0700
Subject: [PATCH 1760/2085] slightly clean up

---
 src/host/hub.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/host/hub.c b/src/host/hub.c
index 0807c2023..182bd6ce8 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -341,8 +341,7 @@ bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32
     // The status change event was neither for the hub, nor for any of its ports.
     // This shouldn't happen, but it does with some devices.
     // Initiate the next interrupt poll here.
-    hub_edpt_status_xfer(dev_addr);
-    return true;
+    return hub_edpt_status_xfer(dev_addr);
   }
 
   if (tu_bit_test(status_change, 0)) {

From 19a597bcae11077c3011d78f1a85dc2f1bfcd00f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jun 2023 12:36:08 +0700
Subject: [PATCH 1761/2085] add lto for cmake

---
 hw/bsp/family_support.cmake              | 310 ++++++++++++-----------
 hw/bsp/imxrt/family.cmake                |   5 +-
 hw/bsp/lpc18/family.cmake                |   5 +-
 hw/bsp/lpc55/family.cmake                |   2 +-
 hw/bsp/mcx/boards/mcxn947brk/board.cmake |   2 +-
 hw/bsp/mcx/family.cmake                  |  17 +-
 hw/bsp/nrf/family.cmake                  |   5 +-
 tools/cmake/cpu/cortex-m33.cmake         |   1 -
 tools/cmake/toolchain/arm_gcc.cmake      |   8 +-
 tools/cmake/toolchain/set_flags.cmake    |  28 +-
 10 files changed, 200 insertions(+), 183 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 68a21bc7d..e3f2f45ff 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -7,141 +7,145 @@ set(TOP "${CMAKE_CURRENT_LIST_DIR}/../..")
 
 # Default to gcc
 if (NOT DEFINED TOOLCHAIN)
-    set(TOOLCHAIN gcc)
+  set(TOOLCHAIN gcc)
 endif ()
 
 if (NOT FAMILY)
-    message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line")
+  message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line")
 endif ()
 
 if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
-    message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
+  message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
 endif()
 
+
 function(family_filter RESULT DIR)
-    get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
+  get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
 
-    if (EXISTS "${DIR}/only.txt")
-        file(READ "${DIR}/only.txt" ONLYS)
-        # Replace newlines with semicolon so that it is treated as a list by CMake
-        string(REPLACE "\n" ";" ONLYS_LINES ${ONLYS})
-        # For each mcu
-        foreach(MCU IN LISTS FAMILY_MCUS)
-            # For each line in only.txt
-            foreach(_line ${ONLYS_LINES})
-                # If mcu:xxx exists for this mcu or board:xxx then include
-                if (${_line} STREQUAL "mcu:${MCU}" OR ${_line} STREQUAL "board:${BOARD}")
-                    set(${RESULT} 1 PARENT_SCOPE)
-                    return()
-                endif()
-            endforeach()
-        endforeach()
+  if (EXISTS "${DIR}/only.txt")
+    file(READ "${DIR}/only.txt" ONLYS)
+    # Replace newlines with semicolon so that it is treated as a list by CMake
+    string(REPLACE "\n" ";" ONLYS_LINES ${ONLYS})
 
-        # Didn't find it in only file so don't build
-        set(${RESULT} 0 PARENT_SCOPE)
+    # For each mcu
+    foreach(MCU IN LISTS FAMILY_MCUS)
+      # For each line in only.txt
+      foreach(_line ${ONLYS_LINES})
+        # If mcu:xxx exists for this mcu or board:xxx then include
+        if (${_line} STREQUAL "mcu:${MCU}" OR ${_line} STREQUAL "board:${BOARD}")
+          set(${RESULT} 1 PARENT_SCOPE)
+          return()
+        endif()
+      endforeach()
+    endforeach()
 
-    elseif (EXISTS "${DIR}/skip.txt")
-        file(READ "${DIR}/skip.txt" SKIPS)
-        # Replace newlines with semicolon so that it is treated as a list by CMake
-        string(REPLACE "\n" ";" SKIPS_LINES ${SKIPS})
-        # For each mcu
-        foreach(MCU IN LISTS FAMILY_MCUS)
-            # For each line in only.txt
-            foreach(_line ${SKIPS_LINES})
-                # If mcu:xxx exists for this mcu then skip
-                if (${_line} STREQUAL "mcu:${MCU}")
-                    set(${RESULT} 0 PARENT_SCOPE)
-                    return()
-                endif()
-            endforeach()
-        endforeach()
+    # Didn't find it in only file so don't build
+    set(${RESULT} 0 PARENT_SCOPE)
 
-        # Didn't find in skip file so build
-        set(${RESULT} 1 PARENT_SCOPE)
+  elseif (EXISTS "${DIR}/skip.txt")
+    file(READ "${DIR}/skip.txt" SKIPS)
+    # Replace newlines with semicolon so that it is treated as a list by CMake
+    string(REPLACE "\n" ";" SKIPS_LINES ${SKIPS})
 
-    else()
+    # For each mcu
+    foreach(MCU IN LISTS FAMILY_MCUS)
+      # For each line in only.txt
+      foreach(_line ${SKIPS_LINES})
+        # If mcu:xxx exists for this mcu then skip
+        if (${_line} STREQUAL "mcu:${MCU}")
+          set(${RESULT} 0 PARENT_SCOPE)
+          return()
+        endif()
+      endforeach()
+    endforeach()
 
-        # Didn't find skip or only file so build
-        set(${RESULT} 1 PARENT_SCOPE)
-
-    endif()
+    # Didn't find in skip file so build
+    set(${RESULT} 1 PARENT_SCOPE)
+  else()
 
+    # Didn't find skip or only file so build
+    set(${RESULT} 1 PARENT_SCOPE)
+  endif()
 endfunction()
 
+
 function(family_add_subdirectory DIR)
-    family_filter(SHOULD_ADD "${DIR}")
-    if (SHOULD_ADD)
-        add_subdirectory(${DIR})
-    endif()
+  family_filter(SHOULD_ADD "${DIR}")
+  if (SHOULD_ADD)
+    add_subdirectory(${DIR})
+  endif()
 endfunction()
 
+
 function(family_get_project_name OUTPUT_NAME DIR)
-    get_filename_component(SHORT_NAME ${DIR} NAME)
-    set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
+  get_filename_component(SHORT_NAME ${DIR} NAME)
+  set(${OUTPUT_NAME} ${TINYUSB_FAMILY_PROJECT_NAME_PREFIX}${SHORT_NAME} PARENT_SCOPE)
 endfunction()
 
+
 function(family_initialize_project PROJECT DIR)
-    family_filter(ALLOWED "${DIR}")
-    if (NOT ALLOWED)
-        get_filename_component(SHORT_NAME ${DIR} NAME)
-        message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
-    endif()
+  # set output suffix to .elf
+  set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE)
+
+  family_filter(ALLOWED "${DIR}")
+  if (NOT ALLOWED)
+    get_filename_component(SHORT_NAME ${DIR} NAME)
+    message(FATAL_ERROR "${SHORT_NAME} is not supported on FAMILY=${FAMILY}")
+  endif()
 endfunction()
 
+
 function(family_add_default_example_warnings TARGET)
-    target_compile_options(${TARGET} PUBLIC
-            -Wall
-            -Wextra
-            -Werror
-            -Wfatal-errors
-            -Wdouble-promotion
-            -Wfloat-equal
-            -Wshadow
-            -Wwrite-strings
-            -Wsign-compare
-            -Wmissing-format-attribute
-            -Wunreachable-code
-            -Wcast-align
-            -Wcast-qual
-            -Wnull-dereference
-            -Wuninitialized
-            -Wunused
-            -Wredundant-decls
-            #-Wstrict-prototypes
-            #-Werror-implicit-function-declaration
-            #-Wundef
-            )
+  target_compile_options(${TARGET} PUBLIC
+    -Wall
+    -Wextra
+    -Werror
+    -Wfatal-errors
+    -Wdouble-promotion
+    -Wfloat-equal
+    -Wshadow
+    -Wwrite-strings
+    -Wsign-compare
+    -Wmissing-format-attribute
+    -Wunreachable-code
+    -Wcast-align
+    -Wcast-qual
+    -Wnull-dereference
+    -Wuninitialized
+    -Wunused
+    -Wredundant-decls
+    #-Wstrict-prototypes
+    #-Werror-implicit-function-declaration
+    #-Wundef
+    )
 
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-        if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0)
-            target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
-        endif()
-
-        # GCC 10
-        if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
-            target_compile_options(${TARGET} PUBLIC -Wconversion)
-        endif()
-
-        # GCC 8
-        if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
-            target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow)
-        endif()
-
-        # GCC 6
-        if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0)
-            target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing)
-        endif()
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0)
+      target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments")
     endif()
+
+    # GCC 10
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 10.0)
+      target_compile_options(${TARGET} PUBLIC -Wconversion)
+    endif()
+
+    # GCC 8
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 8.0)
+      target_compile_options(${TARGET} PUBLIC -Wcast-function-type -Wstrict-overflow)
+    endif()
+
+    # GCC 6
+    if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 6.0)
+      target_compile_options(${TARGET} PUBLIC -Wno-strict-aliasing)
+    endif()
+  endif()
 endfunction()
 
 
-function(family_support_configure_common TARGET)
-  # set output name to .elf
-  set_target_properties(${TARGET} PROPERTIES OUTPUT_NAME ${TARGET}.elf)
-
+function(family_configure_common TARGET)
   # run size after build
   add_custom_command(TARGET ${TARGET} POST_BUILD
-    COMMAND ${TOOLCHAIN_SIZE} $<TARGET_FILE:${TARGET}>
+    COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${TARGET}>
     )
 
   # Generate map file
@@ -151,11 +155,15 @@ function(family_support_configure_common TARGET)
     )
 endfunction()
 
-#  add_custom_command(TARGET ${TARGET} POST_BUILD
-#    COMMAND ${CMAKE_OBJCOPY} -O ihex $<TARGET_FILE:${TARGET}> ${TARGET}.hex
-#    COMMAND ${CMAKE_OBJCOPY} -O binary $<TARGET_FILE:${TARGET}> ${TARGET}.bin
-#    COMMENT "Creating ${TARGET}.hex and ${TARGET}.bin"
-#    )
+
+# Add bin/hex output
+function(family_add_bin_hex TARGET)
+  add_custom_command(TARGET ${TARGET} POST_BUILD
+    COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
+    COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
+    VERBATIM)
+endfunction()
+
 
 # Add flash jlink target
 function(family_flash_jlink TARGET)
@@ -178,78 +186,84 @@ exit"
     )
 endfunction()
 
+
 # Add flash pycod target
 function(family_flash_pyocd TARGET)
-    if (NOT DEFINED PYOC)
-        set(PYOCD pyocd)
-    endif ()
+  if (NOT DEFINED PYOC)
+    set(PYOCD pyocd)
+  endif ()
 
-    add_custom_target(${TARGET}-pyocd
-      DEPENDS ${TARGET}
-      COMMAND ${PYOCD} flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
-      )
+  add_custom_target(${TARGET}-pyocd
+    DEPENDS ${TARGET}
+    COMMAND ${PYOCD} flash -t ${PYOCD_TARGET} $<TARGET_FILE:${TARGET}>
+    )
 endfunction()
 
+
 # Add flash using NXP's LinkServer (redserver)
 # https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/linkserver-for-microcontrollers:LINKERSERVER
 function(family_flash_nxplink TARGET)
-    if (NOT DEFINED LINKSERVER)
-        set(LINKSERVER LinkServer)
-    endif ()
+  if (NOT DEFINED LINKSERVER)
+    set(LINKSERVER LinkServer)
+  endif ()
 
-    # LinkServer has a bug that can only execute with full path otherwise it throws:
-    # realpath error: No such file or directory
-    execute_process(COMMAND which ${LINKSERVER} OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
+  # LinkServer has a bug that can only execute with full path otherwise it throws:
+  # realpath error: No such file or directory
+  execute_process(COMMAND which ${LINKSERVER} OUTPUT_VARIABLE LINKSERVER_PATH OUTPUT_STRIP_TRAILING_WHITESPACE)
 
-    add_custom_target(${TARGET}-nxplink
-      DEPENDS ${TARGET}
-      COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
-      )
+  add_custom_target(${TARGET}-nxplink
+    DEPENDS ${TARGET}
+    COMMAND ${LINKSERVER_PATH} flash ${NXPLINK_DEVICE} load $<TARGET_FILE:${TARGET}>
+    )
 endfunction()
 
+
 # configure an executable target to link to tinyusb in device mode, and add the board implementation
 function(family_configure_device_example TARGET)
-    # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
+  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
 endfunction()
 
+
 # configure an executable target to link to tinyusb in host mode, and add the board implementation
 function(family_configure_host_example TARGET)
-    # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
+  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
 endfunction()
 
+
 # Add freeRTOS support to example, can be overridden by FAMILY/family.cmake
 function(family_add_freertos TARGET)
-    # freeros config
-    if (NOT TARGET freertos_config)
-        add_library(freertos_config INTERFACE)
-        target_include_directories(freertos_config SYSTEM INTERFACE
-          ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig
-          )
-    endif()
+  # freeros config
+  if (NOT TARGET freertos_config)
+    add_library(freertos_config INTERFACE)
+    target_include_directories(freertos_config SYSTEM INTERFACE
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig
+      )
+  endif()
 
-    # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable
-    # such as CMAKE_C_COMPILE_OBJECT
-    if (NOT TARGET freertos_kernel)
-        add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
-    endif ()
+  # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable
+  # such as CMAKE_C_COMPILE_OBJECT
+  if (NOT TARGET freertos_kernel)
+    add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
+  endif ()
 
-    # Add FreeRTOS option to tinyusb_config
-    target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-      CFG_TUSB_OS=OPT_OS_FREERTOS
-      )
-    # link tinyusb with freeRTOS kernel
-    target_link_libraries(${TARGET}-tinyusb PUBLIC
-      freertos_kernel
-      )
-    target_link_libraries(${TARGET} PUBLIC
-      freertos_kernel
-      )
+  # Add FreeRTOS option to tinyusb_config
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_OS=OPT_OS_FREERTOS
+    )
+  # link tinyusb with freeRTOS kernel
+  target_link_libraries(${TARGET}-tinyusb PUBLIC
+    freertos_kernel
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    freertos_kernel
+    )
 endfunction()
 
+
 include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
 
 if (NOT FAMILY_MCUS)
-    set(FAMILY_MCUS ${FAMILY})
+  set(FAMILY_MCUS ${FAMILY})
 endif()
 
 # save it in case of re-inclusion
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index a681b0419..49a4a9281 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -4,6 +4,9 @@ if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
 endif ()
 
+# enable LTO
+set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
@@ -77,7 +80,7 @@ endif () # BOARD_TARGET
 # Functions
 #------------------------------------
 function(family_configure_example TARGET)
-  family_support_configure_common(${TARGET})
+  family_configure_common(${TARGET})
 
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index 698120077..1bfc63d21 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -6,6 +6,9 @@ endif ()
 
 set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx)
 
+# enable LTO
+set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
@@ -65,7 +68,7 @@ endif () # BOARD_TARGET
 # Functions
 #------------------------------------
 function(family_configure_example TARGET)
-  family_support_configure_common(${TARGET})
+  family_configure_common(${TARGET})
 
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 77a2b821e..eb163bde7 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -89,7 +89,7 @@ endif () # BOARD_TARGET
 # Functions
 #------------------------------------
 function(family_configure_example TARGET)
-  family_support_configure_common(${TARGET})
+  family_configure_common(${TARGET})
 
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
index b9acf04d9..7a210628f 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
@@ -1,7 +1,7 @@
 set(MCU_VARIANT MCXN947)
 set(MCU_CORE MCXN947_cm33_core0)
 
-set(JLINK_DEVICE MCXN947)
+set(JLINK_DEVICE MCXN947_M33_0)
 set(PYOCD_TARGET MCXN947)
 set(NXPLINK_DEVICE MCXN947:MCXN947)
 
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 1719320e6..d5a17f584 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -7,6 +7,9 @@ endif ()
 set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
 set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
+# enable LTO
+set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
@@ -70,7 +73,7 @@ endif () # BOARD_TARGET
 # Functions
 #------------------------------------
 function(family_configure_example TARGET)
-  family_support_configure_common(${TARGET})
+  family_configure_common(${TARGET})
 
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
@@ -112,17 +115,7 @@ function(family_configure_example TARGET)
     )
 
   #---------- Flash ----------
-  # use MCUXpresso GUI Flash Tool to flash the elf
-
-#  set(REDLINK_EXE /usr/local/LinkServer/binaries/crt_emu_cm_redlink)
-#  add_custom_target(${TARGET}-redlink
-#    DEPENDS ${TARGET}
-#    COMMAND ${REDLINK_EXE} --flash-load-exec $<TARGET_FILE:${TARGET}> --vendor NXP -p MCXN947 --bootromstall
-#    0x50000040 -CoreIndex=0 --flash-driver= -x ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash --flash-dir
-#    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/flash --flash-hashing
-#    )
-
-  #family_flash_jlink(${TARGET})
+  family_flash_jlink(${TARGET})
   #family_flash_nxplink(${TARGET})
   #family_flash_pyocd(${TARGET})
 endfunction()
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 68b19b33b..71067c8ae 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -10,6 +10,9 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
+# enable LTO
+set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+
 # toolchain set up
 if (MCU_VARIANT STREQUAL "nrf5340_application")
   set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
@@ -77,7 +80,7 @@ endif () # BOARD_TARGET
 # Functions
 #------------------------------------
 function(family_configure_example TARGET)
-  family_support_configure_common(${TARGET})
+  family_configure_common(${TARGET})
 
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
diff --git a/tools/cmake/cpu/cortex-m33.cmake b/tools/cmake/cpu/cortex-m33.cmake
index 26c91a64f..fda277010 100644
--- a/tools/cmake/cpu/cortex-m33.cmake
+++ b/tools/cmake/cpu/cortex-m33.cmake
@@ -3,7 +3,6 @@ if (TOOLCHAIN STREQUAL "gcc")
     -mthumb
     -mcpu=cortex-m33
     -mfloat-abi=hard
-    #-mfpu=fpv5-d16
     -mfpu=fpv5-sp-d16
     )
 
diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake
index 5f25d637b..c7f12f43a 100644
--- a/tools/cmake/toolchain/arm_gcc.cmake
+++ b/tools/cmake/toolchain/arm_gcc.cmake
@@ -4,9 +4,11 @@ set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc")
 set(CMAKE_C_COMPILER "arm-none-eabi-gcc")
 set(CMAKE_CXX_COMPILER "arm-none-eabi-g++")
 
-set(TOOLCHAIN_SIZE "arm-none-eabi-size" CACHE INTERNAL "")
-set(GCC_ELF2BIN "arm-none-eabi-objcopy")
-set_property(GLOBAL PROPERTY ELF2BIN ${GCC_ELF2BIN})
+set(CMAKE_SIZE "arm-none-eabi-size" CACHE FILEPATH "")
+set(CMAKE_OBJCOPY "arm-none-eabi-objcopy" CACHE FILEPATH "")
+set(CMAKE_OBJDUMP "arm-none-eabi-objdump" CACHE FILEPATH "")
+
+set_property(GLOBAL PROPERTY TARGET_SUPPORTS_SHARED_LIBS FALSE)
 
 # Look for includes and libraries only in the target system prefix.
 set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
diff --git a/tools/cmake/toolchain/set_flags.cmake b/tools/cmake/toolchain/set_flags.cmake
index 3f109b59e..6f74fe673 100644
--- a/tools/cmake/toolchain/set_flags.cmake
+++ b/tools/cmake/toolchain/set_flags.cmake
@@ -1,16 +1,16 @@
 include(CMakePrintHelpers)
-foreach(LANG IN ITEMS C CXX ASM)
-    # join the toolchain flags into a single string
-    list(APPEND TOOLCHAIN_${LANG}_FLAGS ${TOOLCHAIN_COMMON_FLAGS})
-    list(JOIN TOOLCHAIN_${LANG}_FLAGS " " TOOLCHAIN_${LANG}_FLAGS)
-    set(CMAKE_${LANG}_FLAGS_INIT "${TOOLCHAIN_${LANG}_FLAGS}")
+foreach (LANG IN ITEMS C CXX ASM)
+  # join the toolchain flags into a single string
+  list(APPEND TOOLCHAIN_${LANG}_FLAGS ${TOOLCHAIN_COMMON_FLAGS})
+  list(JOIN TOOLCHAIN_${LANG}_FLAGS " " TOOLCHAIN_${LANG}_FLAGS)
+  set(CMAKE_${LANG}_FLAGS_INIT "${TOOLCHAIN_${LANG}_FLAGS}")
 
-    #cmake_print_variables(CMAKE_${LANG}_FLAGS_INIT)
+  #cmake_print_variables(CMAKE_${LANG}_FLAGS_INIT)
 
-    # optimization flags
-    set(CMAKE_${LANG}_FLAGS_RELEASE_INIT "-Os")
-    set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-O0")
-endforeach()
+  # optimization flags for LOG, LOGGER ?
+  #set(CMAKE_${LANG}_FLAGS_RELEASE_INIT "-Os")
+  #set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-O0")
+endforeach ()
 
 # Linker
 list(JOIN TOOLCHAIN_EXE_LINKER_FLAGS " " CMAKE_EXE_LINKER_FLAGS_INIT)
@@ -18,7 +18,7 @@ list(JOIN TOOLCHAIN_EXE_LINKER_FLAGS " " CMAKE_EXE_LINKER_FLAGS_INIT)
 # try_compile is cmake test compiling its own example,
 # pass -nostdlib to skip stdlib linking
 get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
-if(IS_IN_TRY_COMPILE)
-    set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
-    set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
-endif()
+if (IS_IN_TRY_COMPILE)
+  set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
+  set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
+endif ()

From 62b2d05d34b3ecca08e531709b4a7f809c108047 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jun 2023 12:50:32 +0700
Subject: [PATCH 1762/2085] skip set CMAKE_EXECUTABLE_SUFFIX for espressif port

---
 hw/bsp/family_support.cmake | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index e3f2f45ff..69290ceec 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -84,8 +84,10 @@ endfunction()
 
 
 function(family_initialize_project PROJECT DIR)
-  # set output suffix to .elf
-  set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE)
+  # set output suffix to .elf (skip espressif)
+  if(NOT FAMILY STREQUAL "espressif")
+    set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE)
+  endif()
 
   family_filter(ALLOWED "${DIR}")
   if (NOT ALLOWED)

From 6b44d8fb55345e19fd82a6169258fbf357a15f81 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jun 2023 15:58:02 +0700
Subject: [PATCH 1763/2085] add cmake support for g0, exlicitly call HAL_Init()
 and also HAL_IncTick() in systick irq, fix button active state.

---
 hw/bsp/lpc18/family.cmake                     |   5 -
 .../boards/stm32g0b1nucleo/board.cmake        |  15 ++
 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h |  15 +-
 hw/bsp/stm32g0/family.c                       |   2 +
 hw/bsp/stm32g0/family.cmake                   | 137 ++++++++++++++++++
 tools/cmake/cpu/cortex-m0plus.cmake           |  11 ++
 6 files changed, 169 insertions(+), 16 deletions(-)
 create mode 100644 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
 create mode 100644 hw/bsp/stm32g0/family.cmake
 create mode 100644 tools/cmake/cpu/cortex-m0plus.cmake

diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index 1bfc63d21..515348e10 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -46,14 +46,9 @@ if (NOT TARGET ${BOARD_TARGET})
     )
   update_board(${BOARD_TARGET})
 
-  if (NOT DEFINED LD_FILE_${TOOLCHAIN})
-    MESSAGE(FATAL_ERROR "LD_FILE_${TOOLCHAIN} not defined")
-  endif ()
-
   if (TOOLCHAIN STREQUAL "gcc")
     target_link_options(${BOARD_TARGET} PUBLIC
       "LINKER:--script=${LD_FILE_gcc}"
-      "LINKER:-Map=$<IF:$<BOOL:$<TARGET_PROPERTY:OUTPUT_NAME>>,$<TARGET_PROPERTY:OUTPUT_NAME>,$<TARGET_PROPERTY:NAME>>${CMAKE_EXECUTABLE_SUFFIX}.map"
       # nanolib
       --specs=nosys.specs
       --specs=nano.specs
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
new file mode 100644
index 000000000..c9f2a9c8e
--- /dev/null
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
@@ -0,0 +1,15 @@
+#set(MCU_VARIANT MIMXRT1011)
+set(JLINK_DEVICE STM32G0B1RE)
+
+set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/STM32G0B1RETx_FLASH.ld)
+set(LD_FILE_iar ${ST_CMSIS}/Source/Templates/iar/linker/stm32g0b1xx_flash.icf)
+
+set(STARTUP_FILE_gcc ${ST_CMSIS}/Source/Templates/gcc/startup_stm32g0b1xx.s)
+set(STARTUP_FILE_iar ${ST_CMSIS}/Source/Templates/iar/startup_stm32g0b1xx.s)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32G0B1xx
+    #HSE_VALUE=8000000U
+    )
+endfunction()
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
index 0d651ea4e..e622c71c2 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
@@ -44,7 +44,7 @@
 // Button
 #define BUTTON_PORT           GPIOC
 #define BUTTON_PIN            GPIO_PIN_13
-#define BUTTON_STATE_ACTIVE   1
+#define BUTTON_STATE_ACTIVE   0
 
 // UART Enable for STLink VCOM
 #define UART_DEV              USART2
@@ -64,17 +64,11 @@ static inline void board_clock_init(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct = { 0 };
 
-  /** Tick priority is used in HAL_RCC_OscConfig, so we need to enable it now
-  */
-  HAL_InitTick(0);
-
-  /** Configure the main internal regulator output voltage
-  */
+  /** Configure the main internal regulator output voltage */
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
 
   /** Initializes the RCC Oscillators according to the specified parameters
-  * in the RCC_OscInitTypeDef structure.
-  */
+  * in the RCC_OscInitTypeDef structure. */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
@@ -91,8 +85,7 @@ static inline void board_clock_init(void)
   PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
   HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
-  /** Initializes the CPU, AHB and APB buses clocks
-  */
+  /** Initializes the CPU, AHB and APB buses clocks */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1;
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c
index 10023b7e2..1a975915f 100644
--- a/hw/bsp/stm32g0/family.c
+++ b/hw/bsp/stm32g0/family.c
@@ -44,6 +44,7 @@ UART_HandleTypeDef UartHandle;
 
 void board_init(void)
 {
+  HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS
   board_clock_init();
 
   // Enable All GPIOs clocks
@@ -162,6 +163,7 @@ volatile uint32_t system_ticks = 0;
 void SysTick_Handler (void)
 {
   system_ticks++;
+  HAL_IncTick();
 }
 
 uint32_t board_millis(void)
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
new file mode 100644
index 000000000..5fc9387e5
--- /dev/null
+++ b/hw/bsp/stm32g0/family.cmake
@@ -0,0 +1,137 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY g0)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# enable LTO
+#set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32G0 CACHE INTERNAL "")
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+set(BOARD_TARGET board_${BOARD})
+if (NOT TARGET ${BOARD_TARGET})
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  target_compile_options(${BOARD_TARGET} PUBLIC
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    )
+  update_board(${BOARD_TARGET})
+
+  target_sources(${BOARD_TARGET} PUBLIC
+    ${STARTUP_FILE_${TOOLCHAIN}}
+    )
+
+  if (TOOLCHAIN STREQUAL "gcc")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_gcc}"
+      -nostartfiles
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  else ()
+    # TODO support IAR
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_iar}"
+      )
+  endif ()
+endif () # BOARD_TARGET
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET)
+  family_configure_common(${TARGET})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # TinyUSB Port
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  #---------- TinyUSB ----------
+  # tinyusb target is built for each example since it depends on example's tusb_config.h
+  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+  add_library(${TARGET}-tinyusb_config INTERFACE)
+
+  target_include_directories(${TARGET}-tinyusb_config INTERFACE
+    ${CMAKE_CURRENT_SOURCE_DIR}/src
+    )
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_MCU=OPT_MCU_STM32G0
+    )
+
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+
+  # group target (not yet supported by clion)
+  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
+    PROPERTIES FOLDER ${TARGET}_sub
+    )
+
+  #---------- Flash ----------
+  family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(family_configure_device_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
diff --git a/tools/cmake/cpu/cortex-m0plus.cmake b/tools/cmake/cpu/cortex-m0plus.cmake
new file mode 100644
index 000000000..1e316ccfc
--- /dev/null
+++ b/tools/cmake/cpu/cortex-m0plus.cmake
@@ -0,0 +1,11 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  list(APPEND TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m0plus
+    -mfloat-abi=soft
+    )
+
+  set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+else ()
+  # TODO support IAR
+endif ()

From 6280cba6e8fb62492d8d07288c914b822b934cd5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jun 2023 16:52:58 +0700
Subject: [PATCH 1764/2085] tested with g0b1 nucleo

---
 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h | 58 ++++++++++++++++++-
 1 file changed, 57 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
index e622c71c2..44c69934d 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
@@ -58,6 +58,62 @@
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
+#if 1
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure. */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
+  RCC_OscInitStruct.PLL.PLLN = 8;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /** Initializes the CPU, AHB and APB buses clocks */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  // Configure CRS clock source
+  __HAL_RCC_CRS_CLK_ENABLE();
+  RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+  RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+  RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
+  RCC_CRSInitStruct.ErrorLimitValue = 34;
+  RCC_CRSInitStruct.HSI48CalibrationValue = 32;
+
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
+  /* Select HSI48 as USB clock source */
+  RCC_PeriphCLKInitTypeDef usb_clk = {0 };
+  usb_clk.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  usb_clk.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&usb_clk);
+
+  // Enable HSI48
+  RCC_OscInitTypeDef osc_hsi48 = {0};
+  osc_hsi48.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  osc_hsi48.HSI48State = RCC_HSI48_ON;
+  HAL_RCC_OscConfig(&osc_hsi48);
+}
+#else
 static inline void board_clock_init(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
@@ -93,8 +149,8 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
-
 }
+#endif
 
 #ifdef __cplusplus
  }

From c750030f7a9b3076b3722172014604ff5190df91 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jun 2023 17:03:04 +0700
Subject: [PATCH 1765/2085] add freertosconfig for g0, add cmake stlink, add g0
 to cmake ci

---
 .github/workflows/cmake_arm.yml               |   1 +
 hw/bsp/family_support.cmake                   |  13 ++
 .../stm32g0/FreeRTOSConfig/FreeRTOSConfig.h   | 166 ++++++++++++++++++
 hw/bsp/stm32g0/family.cmake                   |   1 +
 4 files changed, 181 insertions(+)
 create mode 100644 hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index ccca0c9be..2e74c304c 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -37,6 +37,7 @@ jobs:
           - 'mcx'
           - 'imxrt'
           - 'rp2040'
+          - 'stm32g0'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 69290ceec..d9b8bbbe9 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -189,6 +189,19 @@ exit"
 endfunction()
 
 
+# Add flash stlink target
+function(family_flash_stlink TARGET)
+  if (NOT DEFINED STM32_PROGRAMMER_CLI)
+    set(STM32_PROGRAMMER_CLI STM32_Programmer_CLI)
+  endif ()
+
+  add_custom_target(${TARGET}-stlink
+    DEPENDS ${TARGET}
+    COMMAND ${STM32_PROGRAMMER_CLI} --connect port=swd --write $<TARGET_FILE:${TARGET}> --go
+    )
+endfunction()
+
+
 # Add flash pycod target
 function(family_flash_pyocd TARGET)
   if (NOT DEFINED PYOC)
diff --git a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..1758efcf2
--- /dev/null
+++ b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// IAR assembler have limited preprocessor support and it only need following macros:
+#ifndef __IASMARM__
+// FIXME cause redundant-decls warnings
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU						0
+#define configENABLE_FPU						0
+#define configENABLE_TRUSTZONE					0
+#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index 5fc9387e5..ddd39bc3b 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -120,6 +120,7 @@ function(family_configure_example TARGET)
     )
 
   #---------- Flash ----------
+  family_flash_stlink(${TARGET})
   family_flash_jlink(${TARGET})
 endfunction()
 

From dc3afdbf3b0520caa4a8147c08219486672a6832 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jun 2023 20:52:48 +0700
Subject: [PATCH 1766/2085] add note for B0 clock variant

---
 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h | 4 ++++
 hw/bsp/stm32g0/family.cmake                   | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
index 44c69934d..ae0820529 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h
@@ -59,6 +59,7 @@
 // RCC Clock
 //--------------------------------------------------------------------+
 #if 1
+// Clock configure for STM32G0B1RE Nucleo
 static inline void board_clock_init(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
@@ -114,6 +115,9 @@ static inline void board_clock_init(void)
   HAL_RCC_OscConfig(&osc_hsi48);
 }
 #else
+
+// Clock configure for STM32G0 nucleo with B0 mcu variant for someone that is skilled enough
+// to rework and solder the B0 chip. Note: SB17 may need to be soldered as well (check user manual)
 static inline void board_clock_init(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index ddd39bc3b..9674bc759 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -121,7 +121,7 @@ function(family_configure_example TARGET)
 
   #---------- Flash ----------
   family_flash_stlink(${TARGET})
-  family_flash_jlink(${TARGET})
+  #family_flash_jlink(${TARGET})
 endfunction()
 
 

From 70a92291fe84eb57844a331749ceecb6d2f1f544 Mon Sep 17 00:00:00 2001
From: Dave Nadler <drn@nadler.com>
Date: Thu, 1 Jun 2023 10:58:03 -0400
Subject: [PATCH 1767/2085] Fix diagnostic format string (missing %u)

---
 src/host/usbh.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 7b265c742..6159044ab 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -1179,7 +1179,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
       TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
 
       if (is_hub_addr(daddr)) {
-        TU_LOG(USBH_DEBUG, "  is a HUB device\r\n", daddr);
+        TU_LOG(USBH_DEBUG, "  is a HUB device %u\r\n", daddr);
 
         // Submit removed event If the device itself is a hub (un-rolled recursive)
         // TODO a better to unroll recursrive is using array of removing_hubs and mark it here

From c3bde520cc0b93098fbf3a5d85b9343a2cfa6c3d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 1 Jun 2023 22:03:54 +0700
Subject: [PATCH 1768/2085] add new b_g474e_dpow1 board

---
 .idea/cmake.xml                               |   5 +-
 .idea/runConfigurations/rp2040.xml            |   2 +-
 .../b_g474e_dpow1/STM32G474RETx_FLASH.ld      | 200 ++++++++++++++++++
 .../stm32g4/boards/b_g474e_dpow1/board.cmake  |  14 ++
 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h   | 134 ++++++++++++
 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk  |  13 ++
 .../stm32g474nucleo/STM32G474RETx_FLASH.ld    |  68 +++---
 .../boards/stm32g474nucleo/board.cmake        |  15 ++
 hw/bsp/stm32g4/family.c                       |   1 +
 hw/bsp/stm32g4/family.cmake                   | 138 ++++++++++++
 10 files changed, 560 insertions(+), 30 deletions(-)
 create mode 100644 hw/bsp/stm32g4/boards/b_g474e_dpow1/STM32G474RETx_FLASH.ld
 create mode 100644 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
 create mode 100644 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
 create mode 100644 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk
 create mode 100644 hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
 create mode 100644 hw/bsp/stm32g4/family.cmake

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index a80ebed3c..871968dfb 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,7 +2,7 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="mcxn947" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=mcx -DBOARD=mcxn947brk" />
+      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=mcx -DBOARD=mcxn947brk" />
       <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1060_evk" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" BUILD_OPTIONS="-v" />
@@ -32,6 +32,9 @@
       <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1064_evk" />
       <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=mcb1800" />
       <configuration PROFILE_NAME="lpcxpresso18s37" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=lpcxpresso18s37" />
+      <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g0 -DBOARD=stm32g0b1nucleo" />
+      <configuration PROFILE_NAME="stm32g474nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=stm32g474nucleo" />
+      <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=b_g474e_dpow1" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rp2040.xml b/.idea/runConfigurations/rp2040.xml
index 227a5e2bc..0d1484b25 100644
--- a/.idea/runConfigurations/rp2040.xml
+++ b/.idea/runConfigurations/rp2040.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rp2040" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc_hid" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc_hid" RUN_TARGET_NAME="cdc_msc_hid">
+  <configuration default="false" name="rp2040" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_device_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="b_g474e_dpow1" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_device_examples" RUN_TARGET_NAME="cdc_msc">
     <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
       <debugger kind="GDB" isBundled="true" />
     </openocd>
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/b_g474e_dpow1/STM32G474RETx_FLASH.ld
new file mode 100644
index 000000000..8ba23a5b8
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/STM32G474RETx_FLASH.ld
@@ -0,0 +1,200 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author		: Auto-generated by STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32G474RETx Device from stm32g4 series
+**                      512Kbytes FLASH
+**                      128Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**   1. Redistributions of source code must retain the above copyright notice,
+**      this list of conditions and the following disclaimer.
+**   2. Redistributions in binary form must reproduce the above copyright notice,
+**      this list of conditions and the following disclaimer in the documentation
+**      and/or other materials provided with the distribution.
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
+**      may be used to endorse or promote products derived from this software
+**      without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x1000 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x1000 ;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 128K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
new file mode 100644
index 000000000..4e8f3f059
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT stm32g474xx)
+set(JLINK_DEVICE stm32g474re)
+
+set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
+set(LD_FILE_iar ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+set(STARTUP_FILE_gcc ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_iar ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32G474xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
new file mode 100644
index 000000000..dcbc0163e
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
@@ -0,0 +1,134 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// G474RE Nucleo does not has usb connection. We need to manually connect
+// - PA12 for D+, CN10.12
+// - PA11 for D-, CN10.14
+
+// LED
+#define LED_PORT              GPIOB
+#define LED_PIN               GPIO_PIN_5
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN            GPIO_PIN_13
+#define BUTTON_STATE_ACTIVE   0
+
+// UART Enable for STLink VCOM
+#define UART_DEV              USART3
+#define UART_CLK_EN           __HAL_RCC_USART3_CLK_ENABLE
+#define UART_GPIO_PORT        GPIOC
+#define UART_GPIO_AF          GPIO_AF7_USART3
+#define UART_TX_PIN           GPIO_PIN_10
+#define UART_RX_PIN           GPIO_PIN_11
+
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  // Configure the main internal regulator output voltage
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
+
+  // Initializes the CPU, AHB and APB buses clocks
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState       = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM       = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN       = 50;
+  RCC_OscInitStruct.PLL.PLLP       = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ       = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR       = RCC_PLLR_DIV2;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  // Initializes the CPU, AHB and APB buses clocks
+  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInit.UsbClockSelection    = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) ;
+
+#if 0 // TODO need to check if USB clock is enabled
+  /* Enable HSI48 */
+  memset(&RCC_OscInitStruct, 0, sizeof(RCC_OscInitStruct));
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /*Enable CRS Clock*/
+  RCC_CRSInitTypeDef RCC_CRSInitStruct= {0};
+  __HAL_RCC_CRS_CLK_ENABLE();
+
+  /* Default Synchro Signal division factor (not divided) */
+  RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+
+  /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
+  RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
+
+  /* HSI48 is synchronized with USB SOF at 1KHz rate */
+  RCC_CRSInitStruct.ReloadValue =  __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
+  RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
+
+  /* Set the TRIM[5:0] to the default value */
+  RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
+
+  /* Start automatic synchronization */
+  HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+#endif
+}
+
+static inline void board_vbus_sense_init(void)
+{
+  // Enable VBUS sense (B device) via pin PA9
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk
new file mode 100644
index 000000000..75cd9d8f5
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk
@@ -0,0 +1,13 @@
+CFLAGS += \
+	-DSTM32G474xx \
+
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g474xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32g474xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32g474xx_flash.icf
+
+# For flash-jlink target
+JLINK_DEVICE = stm32g474re
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
index c43829994..8ba23a5b8 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
@@ -1,13 +1,13 @@
 /*
 ******************************************************************************
 **
-
 **  File        : LinkerScript.ld
 **
-**  Author		: Auto-generated by Ac6 System Workbench
+**  Author		: Auto-generated by STM32CubeIDE
 **
-**  Abstract    : Linker script for STM32G474RETx series
-**                512Kbytes FLASH and 160Kbytes RAM
+**  Abstract    : Linker script for STM32G474RETx Device from stm32g4 series
+**                      512Kbytes FLASH
+**                      128Kbytes RAM
 **
 **                Set heap size, stack size and stack location according
 **                to application requirements.
@@ -16,13 +16,13 @@
 **
 **  Target      : STMicroelectronics STM32
 **
-**  Distribution: The file is distributed �as is,� without any warranty
+**  Distribution: The file is distributed as is without any warranty
 **                of any kind.
 **
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6</center></h2>
+** <h2><center>&copy; COPYRIGHT(c) 2020 STMicroelectronics</center></h2>
 **
 ** Redistribution and use in source and binary forms, with or without modification,
 ** are permitted provided that the following conditions are met:
@@ -31,7 +31,7 @@
 **   2. Redistributions in binary form must reproduce the above copyright notice,
 **      this list of conditions and the following disclaimer in the documentation
 **      and/or other materials provided with the distribution.
-**   3. Neither the name of Ac6 nor the names of its contributors
+**   3. Neither the name of STMicroelectronics nor the names of its contributors
 **      may be used to endorse or promote products derived from this software
 **      without specific prior written permission.
 **
@@ -53,23 +53,22 @@
 ENTRY(Reset_Handler)
 
 /* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
 
-/* Specify the memory areas */
+_Min_Heap_Size = 0x1000 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x1000 ;	/* required amount of stack */
+
+/* Memories definition */
 MEMORY
 {
-FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 512K
-RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-CCMSRAM (xrw)      : ORIGIN = 0x10000000, LENGTH = 32K
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 128K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
 }
 
-/* Define output sections */
+/* Sections */
 SECTIONS
 {
-  /* The startup code goes first into FLASH */
+  /* The startup code into "FLASH" Rom type memory */
   .isr_vector :
   {
     . = ALIGN(4);
@@ -77,7 +76,7 @@ SECTIONS
     . = ALIGN(4);
   } >FLASH
 
-  /* The program code and other data goes into FLASH */
+  /* The program code and other data into "FLASH" Rom type memory */
   .text :
   {
     . = ALIGN(4);
@@ -94,7 +93,7 @@ SECTIONS
     _etext = .;        /* define a global symbols at end of code */
   } >FLASH
 
-  /* Constant data goes into FLASH */
+  /* Constant data into "FLASH" Rom type memory */
   .rodata :
   {
     . = ALIGN(4);
@@ -103,38 +102,53 @@ SECTIONS
     . = ALIGN(4);
   } >FLASH
 
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
   .ARM : {
+    . = ALIGN(4);
     __exidx_start = .;
     *(.ARM.exidx*)
     __exidx_end = .;
+    . = ALIGN(4);
   } >FLASH
 
   .preinit_array     :
   {
+    . = ALIGN(4);
     PROVIDE_HIDDEN (__preinit_array_start = .);
     KEEP (*(.preinit_array*))
     PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
   } >FLASH
+
   .init_array :
   {
+    . = ALIGN(4);
     PROVIDE_HIDDEN (__init_array_start = .);
     KEEP (*(SORT(.init_array.*)))
     KEEP (*(.init_array*))
     PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
   } >FLASH
+
   .fini_array :
   {
+    . = ALIGN(4);
     PROVIDE_HIDDEN (__fini_array_start = .);
     KEEP (*(SORT(.fini_array.*)))
     KEEP (*(.fini_array*))
     PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
   } >FLASH
 
-  /* used by the startup to initialize data */
+  /* Used by the startup to initialize data */
   _sidata = LOADADDR(.data);
 
-  /* Initialized data sections goes into RAM, load LMA copy after code */
+  /* Initialized data sections into "RAM" Ram type memory */
   .data :
   {
     . = ALIGN(4);
@@ -144,10 +158,10 @@ SECTIONS
 
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
+
   } >RAM AT> FLASH
 
-
-  /* Uninitialized data section */
+  /* Uninitialized data section into "RAM" Ram type memory */
   . = ALIGN(4);
   .bss :
   {
@@ -163,7 +177,7 @@ SECTIONS
     __bss_end__ = _ebss;
   } >RAM
 
-  /* User_heap_stack section, used to check that there is enough RAM left */
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
   ._user_heap_stack :
   {
     . = ALIGN(8);
@@ -174,9 +188,7 @@ SECTIONS
     . = ALIGN(8);
   } >RAM
 
-
-
-  /* Remove information from the standard libraries */
+  /* Remove information from the compiler libraries */
   /DISCARD/ :
   {
     libc.a ( * )
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
new file mode 100644
index 000000000..8cc633449
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
@@ -0,0 +1,15 @@
+set(MCU_VARIANT stm32g474xx)
+set(JLINK_DEVICE stm32g474re)
+
+set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
+set(LD_FILE_iar ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+set(STARTUP_FILE_gcc ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_iar ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32G474xx
+    HSE_VALUE=24000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index f5177fd10..3b490e9b3 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -53,6 +53,7 @@ UART_HandleTypeDef UartHandle;
 
 void board_init(void)
 {
+  HAL_Init();
   board_clock_init();
 
   // Enable All GPIOs clocks
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
new file mode 100644
index 000000000..1de6fd674
--- /dev/null
+++ b/hw/bsp/stm32g4/family.cmake
@@ -0,0 +1,138 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY g4)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# enable LTO
+#set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32G4 CACHE INTERNAL "")
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+set(BOARD_TARGET board_${BOARD})
+if (NOT TARGET ${BOARD_TARGET})
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  target_compile_options(${BOARD_TARGET} PUBLIC
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    )
+  update_board(${BOARD_TARGET})
+
+  target_sources(${BOARD_TARGET} PUBLIC
+    ${STARTUP_FILE_${TOOLCHAIN}}
+    )
+
+  if (TOOLCHAIN STREQUAL "gcc")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_gcc}"
+      -nostartfiles
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  else ()
+    # TODO support IAR
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_iar}"
+      )
+  endif ()
+endif () # BOARD_TARGET
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET)
+  family_configure_common(${TARGET})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # TinyUSB Port
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  #---------- TinyUSB ----------
+  # tinyusb target is built for each example since it depends on example's tusb_config.h
+  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+  add_library(${TARGET}-tinyusb_config INTERFACE)
+
+  target_include_directories(${TARGET}-tinyusb_config INTERFACE
+    ${CMAKE_CURRENT_SOURCE_DIR}/src
+    )
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_MCU=OPT_MCU_STM32G4
+    )
+
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+
+  # group target (not yet supported by clion)
+  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
+    PROPERTIES FOLDER ${TARGET}_sub
+    )
+
+  #---------- Flash ----------
+  family_flash_stlink(${TARGET})
+  #family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(family_configure_device_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()

From e8b7f21af6e5e994ece7c989202767732f23809e Mon Sep 17 00:00:00 2001
From: Dave Nadler <drn@nadler.com>
Date: Thu, 1 Jun 2023 12:57:44 -0400
Subject: [PATCH 1769/2085] For FreeRTOS kernel-aware debugging, when queue
 registry is enabled, label tinyUSB queue

---
 src/osal/osal_freertos.h | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 477f64892..0b1b11589 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -169,11 +169,16 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 
 TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
 {
-#if configSUPPORT_STATIC_ALLOCATION
-	return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
-#else
-  return xQueueCreate(qdef->depth, qdef->item_sz);
-#endif
+  osal_queue_t q;
+  #if configSUPPORT_STATIC_ALLOCATION
+    q = xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
+  #else
+    q = xQueueCreate(qdef->depth, qdef->item_sz);
+  #endif
+  #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+    vQueueAddToRegistry(q, "tinyUSB");
+  #endif
+  return q;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)

From ba3d71b615df1ba8dd5f8e4858a182620ef1472b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Jun 2023 10:19:46 +0700
Subject: [PATCH 1770/2085] fix usb clock for dpow1

---
 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h | 50 ++++++++++-----------
 1 file changed, 24 insertions(+), 26 deletions(-)

diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
index dcbc0163e..5d936d009 100644
--- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
@@ -61,44 +61,38 @@ static inline void board_clock_init(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
   // Configure the main internal regulator output voltage
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
 
-  // Initializes the CPU, AHB and APB buses clocks
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState       = RCC_HSE_ON;
-  RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLM       = RCC_PLLM_DIV4;
-  RCC_OscInitStruct.PLL.PLLN       = 50;
-  RCC_OscInitStruct.PLL.PLLP       = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ       = RCC_PLLQ_DIV2;
-  RCC_OscInitStruct.PLL.PLLR       = RCC_PLLR_DIV2;
+  /* Activate PLL with HSI as source */
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM            = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN            = 85;
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV10;
+  RCC_OscInitStruct.PLL.PLLQ            = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR            = RCC_PLLR_DIV2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
   // Initializes the CPU, AHB and APB buses clocks
-  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.ClockType      = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
+                                     RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
   HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
 
-  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInit.UsbClockSelection    = RCC_USBCLKSOURCE_HSI48;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) ;
-
-#if 0 // TODO need to check if USB clock is enabled
-  /* Enable HSI48 */
-  memset(&RCC_OscInitStruct, 0, sizeof(RCC_OscInitStruct));
-
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
-  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+  //------------- HSI48 and CRS for USB -------------//
+  RCC_OscInitTypeDef osc_hsi48 = {0};
+  osc_hsi48.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
+  osc_hsi48.HSI48State = RCC_HSI48_ON;
+  osc_hsi48.PLL.PLLState = RCC_PLL_NONE;
+  HAL_RCC_OscConfig(&osc_hsi48);
 
   /*Enable CRS Clock*/
   RCC_CRSInitTypeDef RCC_CRSInitStruct= {0};
@@ -119,7 +113,11 @@ static inline void board_clock_init(void)
 
   /* Start automatic synchronization */
   HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
-#endif
+
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInit.UsbClockSelection    = RCC_USBCLKSOURCE_HSI48;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
 }
 
 static inline void board_vbus_sense_init(void)

From e7090c75148820ff3a4ad60c718684c46c954c18 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Jun 2023 11:42:17 +0700
Subject: [PATCH 1771/2085] cmake refactor

---
 .github/workflows/build_arm.yml |   2 +-
 .github/workflows/cmake_arm.yml |   9 +--
 hw/bsp/family_support.cmake     | 116 ++++++++++++++++++++------------
 hw/bsp/imxrt/family.cmake       |  26 ++-----
 hw/bsp/lpc18/family.cmake       |  23 +------
 hw/bsp/lpc55/family.cmake       |  25 ++-----
 hw/bsp/mcx/family.cmake         |  23 +------
 hw/bsp/nrf/family.cmake         |  23 +------
 hw/bsp/stm32g0/family.cmake     |  23 +------
 hw/bsp/stm32g4/family.cmake     |  25 ++-----
 src/CMakeLists.txt              |   4 ++
 tools/build_cmake.py            |  10 +--
 12 files changed, 112 insertions(+), 197 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 3a2daab08..a7c7fd1e1 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -46,7 +46,7 @@ jobs:
         - 'stm32f0 stm32f1 stm32f2 stm32f3'
         - 'stm32f4'
         - 'stm32f7'
-        - 'stm32g4 stm32h7'
+        - 'stm32h7'
         - 'stm32l0 stm32l4 stm32u5 stm32wb'
         - 'tm4c123 xmc4000'
     steps:
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 2e74c304c..2ca8e32f5 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -38,6 +38,7 @@ jobs:
           - 'imxrt'
           - 'rp2040'
           - 'stm32g0'
+          - 'stm32g4'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
@@ -75,11 +76,11 @@ jobs:
     # Upload binaries for hardware test with self-hosted
     - name: Prepare rp2040 Artifacts
       if: contains(matrix.family, 'rp2040') && github.repository_owner == 'hathach'
-      working-directory: ${{github.workspace}}/cmake-build-ci-raspberry_pi_pico
+      working-directory: ${{github.workspace}}/cmake-build/cmake-build-raspberry_pi_pico
       run: |
-        find device/ -name "*.elf" -exec mv {} ../ \;
-        # find host/ -name "*.elf" -exec mv {} ../ \;
-        # find dual/ -name "*.elf" -exec mv {} ../ \;
+        find device/ -name "*.elf" -exec mv {} ../../ \;
+        # find host/ -name "*.elf" -exec mv {} ../../ \;
+        # find dual/ -name "*.elf" -exec mv {} ../../ \;
 
     - name: Upload Artifacts for rp2040
       if: contains(matrix.family,'rp2040') && github.repository_owner == 'hathach'
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index d9b8bbbe9..fdc9580ae 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -84,8 +84,8 @@ endfunction()
 
 
 function(family_initialize_project PROJECT DIR)
-  # set output suffix to .elf (skip espressif)
-  if(NOT FAMILY STREQUAL "espressif")
+  # set output suffix to .elf (skip espressif and rp2040)
+  if(NOT FAMILY STREQUAL "espressif" AND NOT FAMILY STREQUAL "rp2040")
     set(CMAKE_EXECUTABLE_SUFFIX .elf PARENT_SCOPE)
   endif()
 
@@ -144,6 +144,11 @@ function(family_add_default_example_warnings TARGET)
 endfunction()
 
 
+#------------------------------------
+# Main target configure
+#------------------------------------
+
+# Add common configuration to example
 function(family_configure_common TARGET)
   # run size after build
   add_custom_command(TARGET ${TARGET} POST_BUILD
@@ -158,6 +163,66 @@ function(family_configure_common TARGET)
 endfunction()
 
 
+# configure an executable target to link to tinyusb in device mode, and add the board implementation
+function(family_configure_device_example TARGET)
+  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
+endfunction()
+
+
+# configure an executable target to link to tinyusb in host mode, and add the board implementation
+function(family_configure_host_example TARGET)
+  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
+endfunction()
+
+
+# Add tinyusb to example
+function(family_add_tinyusb TARGET OPT_MCU)
+  # tinyusb target is built for each example since it depends on example's tusb_config.h
+  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+  add_library(${TARGET}-tinyusb_config INTERFACE)
+
+  target_include_directories(${TARGET}-tinyusb_config INTERFACE
+    ${CMAKE_CURRENT_SOURCE_DIR}/src
+    )
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_MCU=${OPT_MCU}
+    )
+
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+endfunction()
+
+
+# Add freeRTOS support to example
+function(family_add_freertos TARGET)
+  # freeros config
+  if (NOT TARGET freertos_config)
+    add_library(freertos_config INTERFACE)
+    target_include_directories(freertos_config SYSTEM INTERFACE
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig
+      )
+  endif()
+
+  # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable
+  # such as CMAKE_C_COMPILE_OBJECT
+  if (NOT TARGET freertos_kernel)
+    add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
+  endif ()
+
+  # Add FreeRTOS option to tinyusb_config
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_OS=OPT_OS_FREERTOS
+    )
+  # link tinyusb with freeRTOS kernel
+  target_link_libraries(${TARGET}-tinyusb PUBLIC
+    freertos_kernel
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    freertos_kernel
+    )
+endfunction()
+
+
 # Add bin/hex output
 function(family_add_bin_hex TARGET)
   add_custom_command(TARGET ${TARGET} POST_BUILD
@@ -167,6 +232,10 @@ function(family_add_bin_hex TARGET)
 endfunction()
 
 
+#----------------------------------
+# Flashing target
+#----------------------------------
+
 # Add flash jlink target
 function(family_flash_jlink TARGET)
   if (NOT DEFINED JLINKEXE)
@@ -233,48 +302,7 @@ function(family_flash_nxplink TARGET)
 endfunction()
 
 
-# configure an executable target to link to tinyusb in device mode, and add the board implementation
-function(family_configure_device_example TARGET)
-  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
-endfunction()
-
-
-# configure an executable target to link to tinyusb in host mode, and add the board implementation
-function(family_configure_host_example TARGET)
-  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
-endfunction()
-
-
-# Add freeRTOS support to example, can be overridden by FAMILY/family.cmake
-function(family_add_freertos TARGET)
-  # freeros config
-  if (NOT TARGET freertos_config)
-    add_library(freertos_config INTERFACE)
-    target_include_directories(freertos_config SYSTEM INTERFACE
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig
-      )
-  endif()
-
-  # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable
-  # such as CMAKE_C_COMPILE_OBJECT
-  if (NOT TARGET freertos_kernel)
-    add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
-  endif ()
-
-  # Add FreeRTOS option to tinyusb_config
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_OS=OPT_OS_FREERTOS
-    )
-  # link tinyusb with freeRTOS kernel
-  target_link_libraries(${TARGET}-tinyusb PUBLIC
-    freertos_kernel
-    )
-  target_link_libraries(${TARGET} PUBLIC
-    freertos_kernel
-    )
-endfunction()
-
-
+# family specific: can override above functions
 include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
 
 if (NOT FAMILY_MCUS)
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 49a4a9281..3c156285c 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -36,7 +36,6 @@ if (NOT TARGET ${BOARD_TARGET})
     ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
     )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
-    CFG_TUSB_MCU=OPT_MCU_MIMXRT
     __ARMVFP__=0
     __ARMFPV5__=0
     XIP_EXTERNAL_FLASH=1
@@ -100,33 +99,16 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  #---------- TinyUSB ----------
-  # tinyusb target is built for each example since it depends on example's tusb_config.h
-  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
-  add_library(${TARGET}-tinyusb_config INTERFACE)
-
-  target_include_directories(${TARGET}-tinyusb_config INTERFACE
-    ${CMAKE_CURRENT_SOURCE_DIR}/src
-    )
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_MCU=OPT_MCU_MIMXRT
-    )
-
-  # tinyusb's CMakeList.txt
-  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+  # Add TinyUSB
+  family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT)
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
 
-  # group target (not yet supported by clion)
-  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
-    PROPERTIES FOLDER ${TARGET}_sub
-    )
-
-  #---------- Flash ----------
+  # Flashing
   family_flash_jlink(${TARGET})
   family_flash_nxplink(${TARGET})
-  family_flash_pyocd(${TARGET})
+  #family_flash_pyocd(${TARGET})
 endfunction()
 
 
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index 515348e10..a133e7217 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -83,30 +83,13 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  #---------- TinyUSB ----------
-  # tinyusb target is built for each example since it depends on example's tusb_config.h
-  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
-  add_library(${TARGET}-tinyusb_config INTERFACE)
-
-  target_include_directories(${TARGET}-tinyusb_config INTERFACE
-    ${CMAKE_CURRENT_SOURCE_DIR}/src
-    )
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_MCU=OPT_MCU_LPC18XX
-    )
-
-  # tinyusb's CMakeList.txt
-  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+  # Add TinyUSB
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX)
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
 
-  # group target (not yet supported by clion)
-  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
-    PROPERTIES FOLDER ${TARGET}_sub
-    )
-
-  #---------- Flash ----------
+  # Flashing
   family_flash_jlink(${TARGET})
 endfunction()
 
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index eb163bde7..25eed48de 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -109,33 +109,16 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  #---------- TinyUSB ----------
-  # tinyusb target is built for each example since it depends on example's tusb_config.h
-  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
-  add_library(${TARGET}-tinyusb_config INTERFACE)
-
-  target_include_directories(${TARGET}-tinyusb_config INTERFACE
-    ${CMAKE_CURRENT_SOURCE_DIR}/src
-    )
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_MCU=OPT_MCU_LPC55XX
-    )
-
-  # tinyusb's CMakeList.txt
-  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+  # Add TinyUSB
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX)
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
 
-  # group target (not yet supported by clion)
-  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
-    PROPERTIES FOLDER ${TARGET}_sub
-    )
-
-  #---------- Flash ----------
+  # Flashing
   family_flash_jlink(${TARGET})
   family_flash_nxplink(${TARGET})
-  family_flash_pyocd(${TARGET})
+  #family_flash_pyocd(${TARGET})
 endfunction()
 
 
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index d5a17f584..17f54a53b 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -91,30 +91,13 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  #---------- TinyUSB ----------
-  # tinyusb target is built for each example since it depends on example's tusb_config.h
-  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
-  add_library(${TARGET}-tinyusb_config INTERFACE)
-
-  target_include_directories(${TARGET}-tinyusb_config INTERFACE
-    ${CMAKE_CURRENT_SOURCE_DIR}/src
-    )
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_MCU=OPT_MCU_MCXN9
-    )
-
-  # tinyusb's CMakeList.txt
-  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+  # Add TinyUSB
+  family_add_tinyusb(${TARGET} OPT_MCU_MCXN9)
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
 
-  # group target (not yet supported by clion)
-  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
-    PROPERTIES FOLDER ${TARGET}_sub
-    )
-
-  #---------- Flash ----------
+  # Flashing
   family_flash_jlink(${TARGET})
   #family_flash_nxplink(${TARGET})
   #family_flash_pyocd(${TARGET})
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 71067c8ae..2c5d7a431 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -98,30 +98,13 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  #---------- TinyUSB ----------
-  # tinyusb target is built for each example since it depends on example's tusb_config.h
-  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
-  add_library(${TARGET}-tinyusb_config INTERFACE)
-
-  target_include_directories(${TARGET}-tinyusb_config INTERFACE
-    ${CMAKE_CURRENT_SOURCE_DIR}/src
-    )
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_MCU=OPT_MCU_NRF5X
-    )
-
-  # tinyusb's CMakeList.txt
-  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+  # Add TinyUSB
+  family_add_tinyusb(${TARGET} OPT_MCU_NRF5X)
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
 
-  # group target (not yet supported by clion)
-  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
-    PROPERTIES FOLDER ${TARGET}_sub
-    )
-
-  #---------- Flash ----------
+  # Flashing
   family_flash_jlink(${TARGET})
 endfunction()
 
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index 9674bc759..184dc6062 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -96,30 +96,13 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  #---------- TinyUSB ----------
-  # tinyusb target is built for each example since it depends on example's tusb_config.h
-  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
-  add_library(${TARGET}-tinyusb_config INTERFACE)
-
-  target_include_directories(${TARGET}-tinyusb_config INTERFACE
-    ${CMAKE_CURRENT_SOURCE_DIR}/src
-    )
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_MCU=OPT_MCU_STM32G0
-    )
-
-  # tinyusb's CMakeList.txt
-  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+  # Add TinyUSB
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32G0)
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
 
-  # group target (not yet supported by clion)
-  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
-    PROPERTIES FOLDER ${TARGET}_sub
-    )
-
-  #---------- Flash ----------
+  # Flashing
   family_flash_stlink(${TARGET})
   #family_flash_jlink(${TARGET})
 endfunction()
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index 1de6fd674..5578a9b6c 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -12,7 +12,7 @@ set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
 set(CMSIS_5 ${TOP}/lib/CMSIS_5)
 
 # enable LTO
-#set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
 
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
@@ -96,30 +96,13 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  #---------- TinyUSB ----------
-  # tinyusb target is built for each example since it depends on example's tusb_config.h
-  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
-  add_library(${TARGET}-tinyusb_config INTERFACE)
-
-  target_include_directories(${TARGET}-tinyusb_config INTERFACE
-    ${CMAKE_CURRENT_SOURCE_DIR}/src
-    )
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_MCU=OPT_MCU_STM32G4
-    )
-
-  # tinyusb's CMakeList.txt
-  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+  # Add TinyUSB
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32G4)
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
 
-  # group target (not yet supported by clion)
-  set_target_properties(${TARGET}-tinyusb ${TARGET}-tinyusb_config
-    PROPERTIES FOLDER ${TARGET}_sub
-    )
-
-  #---------- Flash ----------
+  # Flashing
   family_flash_stlink(${TARGET})
   #family_flash_jlink(${TARGET})
 endfunction()
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 396737ed5..ad9fbc7c0 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -96,3 +96,7 @@ endif()
 target_link_libraries(${TINYUSB_TARGET} PUBLIC
   ${TINYUSB_CONFIG_TARGET}
   )
+
+# export target name
+# set(TINYUSB_TARGET ${TINYUSB_TARGET} PARENT_SCOPE)
+# set(TINYUSB_CONFIG_TARGET ${TINYUSB_CONFIG_TARGET} PARENT_SCOPE)
diff --git a/tools/build_cmake.py b/tools/build_cmake.py
index 88d27dfb8..d85726213 100644
--- a/tools/build_cmake.py
+++ b/tools/build_cmake.py
@@ -34,13 +34,15 @@ def build_family(family, make_option):
     for board in all_boards:
         start_time = time.monotonic()
 
+        build_dir = f"cmake-build/cmake-build-{board}"
+
         # Generate build
-        r = subprocess.run(f"cmake examples -B cmake-build-ci-{board} -G \"Ninja\" -DFAMILY={family} -DBOARD"
+        r = subprocess.run(f"cmake examples -B {build_dir} -G \"Ninja\" -DFAMILY={family} -DBOARD"
                            f"={board}", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
 
         # Build
         if r.returncode == 0:
-            r = subprocess.run(f"cmake --build cmake-build-ci-{board}", shell=True, stdout=subprocess.PIPE,
+            r = subprocess.run(f"cmake --build {build_dir}", shell=True, stdout=subprocess.PIPE,
                                stderr=subprocess.STDOUT)
 
         duration = time.monotonic() - start_time
@@ -71,10 +73,10 @@ if __name__ == '__main__':
     if make_iar_option not in sys.argv:
         make_iar_option = ''
 
-    # If family are not specified in arguments, build all
+    # If family are not specified in arguments, build all supported
     all_families = []
     for entry in os.scandir("hw/bsp"):
-        if entry.is_dir() and os.path.isdir(entry.path + "/boards") and entry.name != 'espressif':
+        if entry.is_dir() and entry.name != 'espressif' and os.path.isfile(entry.path + "/family.cmake"):
             all_families.append(entry.name)
     filter_with_input(all_families)
     all_families.sort()

From fcf77914546496d88d5915223095d93bb63c67fe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Jun 2023 13:27:18 +0700
Subject: [PATCH 1772/2085] add IAR support for G0 with cmake

---
 .../device/net_lwip_webserver/CMakeLists.txt  |  16 +-
 hw/bsp/family_support.cmake                   | 160 +++++++++---------
 hw/bsp/imxrt/family.cmake                     |   4 +-
 .../lpc18/boards/lpcxpresso18s37/board.cmake  |   2 +-
 hw/bsp/lpc18/boards/mcb1800/board.cmake       |   2 +-
 hw/bsp/lpc18/family.cmake                     |   2 +-
 .../boards/double_m33_express/board.cmake     |   2 +-
 hw/bsp/lpc55/family.cmake                     |   4 +-
 hw/bsp/nrf/boards/pca10056/board.cmake        |   2 +-
 hw/bsp/nrf/boards/pca10095/board.cmake        |   2 +-
 hw/bsp/nrf/family.cmake                       |   4 +-
 .../boards/stm32g0b1nucleo/board.cmake        |   8 +-
 hw/bsp/stm32g0/family.cmake                   |  86 +++++-----
 .../stm32g4/boards/b_g474e_dpow1/board.cmake  |   8 +-
 .../boards/stm32g474nucleo/board.cmake        |   8 +-
 hw/bsp/stm32g4/family.cmake                   |   4 +-
 src/CMakeLists.txt                            |   2 +
 tools/cmake/cpu/cortex-m0plus.cmake           |  12 +-
 tools/cmake/toolchain/arm_gcc.cmake           |  14 +-
 tools/cmake/toolchain/arm_iar.cmake           |  34 ++++
 tools/cmake/toolchain/set_flags.cmake         |  17 +-
 21 files changed, 222 insertions(+), 171 deletions(-)
 create mode 100644 tools/cmake/toolchain/arm_iar.cmake

diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 5225f7c42..2c21aa52b 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -77,12 +77,16 @@ target_sources(${PROJECT} PUBLIC
   )
 
 # due to warnings from other net source, we need to prevent error from some of the warnings options
-target_compile_options(${PROJECT} PUBLIC
-  -Wno-error=null-dereference
-  -Wno-error=conversion
-  -Wno-error=sign-conversion
-  -Wno-error=sign-compare
-  )
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+  target_compile_options(${PROJECT} PUBLIC
+    -Wno-error=null-dereference
+    -Wno-error=conversion
+    -Wno-error=sign-conversion
+    -Wno-error=sign-compare
+    )
+elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+
+endif ()
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index fdc9580ae..e801f0116 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -97,6 +97,87 @@ function(family_initialize_project PROJECT DIR)
 endfunction()
 
 
+#------------------------------------
+# Main target configure
+#------------------------------------
+
+# Add common configuration to example
+function(family_configure_common TARGET)
+  # run size after build
+  add_custom_command(TARGET ${TARGET} POST_BUILD
+    COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${TARGET}>
+    )
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GCC")
+    # Generate map file
+    target_link_options(${TARGET} PUBLIC
+      # link map
+      "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map"
+      )
+  endif()
+endfunction()
+
+
+# configure an executable target to link to tinyusb in device mode, and add the board implementation
+function(family_configure_device_example TARGET)
+  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
+endfunction()
+
+
+# configure an executable target to link to tinyusb in host mode, and add the board implementation
+function(family_configure_host_example TARGET)
+  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
+endfunction()
+
+
+# Add tinyusb to example
+function(family_add_tinyusb TARGET OPT_MCU)
+  # tinyusb target is built for each example since it depends on example's tusb_config.h
+  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
+  add_library(${TARGET}-tinyusb_config INTERFACE)
+
+  target_include_directories(${TARGET}-tinyusb_config INTERFACE
+    ${CMAKE_CURRENT_SOURCE_DIR}/src
+    )
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_MCU=${OPT_MCU}
+    )
+
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+endfunction()
+
+
+# Add freeRTOS support to example
+function(family_add_freertos TARGET)
+  # freeros config
+  if (NOT TARGET freertos_config)
+    add_library(freertos_config INTERFACE)
+    target_include_directories(freertos_config INTERFACE
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig
+      )
+  endif()
+
+  # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable
+  # such as CMAKE_C_COMPILE_OBJECT
+  if (NOT TARGET freertos_kernel)
+    add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
+  endif ()
+
+  # Add FreeRTOS option to tinyusb_config
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
+    CFG_TUSB_OS=OPT_OS_FREERTOS
+    )
+  # link tinyusb with freeRTOS kernel
+  target_link_libraries(${TARGET}-tinyusb PUBLIC
+    freertos_kernel
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    freertos_kernel
+    )
+endfunction()
+
+
 function(family_add_default_example_warnings TARGET)
   target_compile_options(${TARGET} PUBLIC
     -Wall
@@ -144,85 +225,6 @@ function(family_add_default_example_warnings TARGET)
 endfunction()
 
 
-#------------------------------------
-# Main target configure
-#------------------------------------
-
-# Add common configuration to example
-function(family_configure_common TARGET)
-  # run size after build
-  add_custom_command(TARGET ${TARGET} POST_BUILD
-    COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${TARGET}>
-    )
-
-  # Generate map file
-  target_link_options(${TARGET} PUBLIC
-    # link map
-    "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map"
-    )
-endfunction()
-
-
-# configure an executable target to link to tinyusb in device mode, and add the board implementation
-function(family_configure_device_example TARGET)
-  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
-endfunction()
-
-
-# configure an executable target to link to tinyusb in host mode, and add the board implementation
-function(family_configure_host_example TARGET)
-  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
-endfunction()
-
-
-# Add tinyusb to example
-function(family_add_tinyusb TARGET OPT_MCU)
-  # tinyusb target is built for each example since it depends on example's tusb_config.h
-  set(TINYUSB_TARGET_PREFIX ${TARGET}-)
-  add_library(${TARGET}-tinyusb_config INTERFACE)
-
-  target_include_directories(${TARGET}-tinyusb_config INTERFACE
-    ${CMAKE_CURRENT_SOURCE_DIR}/src
-    )
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_MCU=${OPT_MCU}
-    )
-
-  # tinyusb's CMakeList.txt
-  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
-endfunction()
-
-
-# Add freeRTOS support to example
-function(family_add_freertos TARGET)
-  # freeros config
-  if (NOT TARGET freertos_config)
-    add_library(freertos_config INTERFACE)
-    target_include_directories(freertos_config SYSTEM INTERFACE
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig
-      )
-  endif()
-
-  # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable
-  # such as CMAKE_C_COMPILE_OBJECT
-  if (NOT TARGET freertos_kernel)
-    add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
-  endif ()
-
-  # Add FreeRTOS option to tinyusb_config
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_OS=OPT_OS_FREERTOS
-    )
-  # link tinyusb with freeRTOS kernel
-  target_link_libraries(${TARGET}-tinyusb PUBLIC
-    freertos_kernel
-    )
-  target_link_libraries(${TARGET} PUBLIC
-    freertos_kernel
-    )
-endfunction()
-
-
 # Add bin/hex output
 function(family_add_bin_hex TARGET)
   add_custom_command(TARGET ${TARGET} POST_BUILD
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 3c156285c..b5d47614e 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -53,7 +53,7 @@ if (NOT TARGET ${BOARD_TARGET})
   update_board(${BOARD_TARGET})
 
   if (NOT DEFINED LD_FILE_${TOOLCHAIN})
-    set(LD_FILE_gcc ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
+    set(LD_FILE_GCC ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
   endif ()
 
   if (TOOLCHAIN STREQUAL "gcc")
@@ -61,7 +61,7 @@ if (NOT TARGET ${BOARD_TARGET})
       ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
       )
     target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_gcc}"
+      "LINKER:--script=${LD_FILE_GCC}"
       # nanolib
       --specs=nosys.specs
       --specs=nano.specs
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
index b540012a4..00686ca01 100644
--- a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
@@ -4,7 +4,7 @@ set(JLINK_DEVICE LPC18S37)
 set(PYOCD_TARGET LPC18S37)
 set(NXPLINK_DEVICE LPC18S37:LPCXPRESSO18S37)
 
-set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld)
+set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld)
 
 function(update_board TARGET)
   # nothing to do
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.cmake b/hw/bsp/lpc18/boards/mcb1800/board.cmake
index 1efeafd12..cfc2739e3 100644
--- a/hw/bsp/lpc18/boards/mcb1800/board.cmake
+++ b/hw/bsp/lpc18/boards/mcb1800/board.cmake
@@ -4,7 +4,7 @@ set(JLINK_DEVICE LPC1857)
 set(PYOCD_TARGET LPC1857)
 set(NXPLINK_DEVICE LPC1857:MCB1857)
 
-set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld)
+set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld)
 
 function(update_board TARGET)
   # nothing to do
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index a133e7217..38b0f61fc 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -48,7 +48,7 @@ if (NOT TARGET ${BOARD_TARGET})
 
   if (TOOLCHAIN STREQUAL "gcc")
     target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_gcc}"
+      "LINKER:--script=${LD_FILE_GCC}"
       # nanolib
       --specs=nosys.specs
       --specs=nano.specs
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.cmake b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
index 7c46c075e..62b0993dc 100644
--- a/hw/bsp/lpc55/boards/double_m33_express/board.cmake
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
@@ -5,7 +5,7 @@ set(JLINK_DEVICE LPC55S69)
 set(PYOCD_TARGET LPC55S69)
 set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
-set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
+set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 25eed48de..967ed3fa6 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -65,7 +65,7 @@ if (NOT TARGET ${BOARD_TARGET})
   update_board(${BOARD_TARGET})
 
   if (NOT DEFINED LD_FILE_${TOOLCHAIN})
-    set(LD_FILE_gcc ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+    set(LD_FILE_GCC ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
   endif ()
 
   if (TOOLCHAIN STREQUAL "gcc")
@@ -74,7 +74,7 @@ if (NOT TARGET ${BOARD_TARGET})
       )
     target_link_options(${BOARD_TARGET} PUBLIC
       # linker file
-      "LINKER:--script=${LD_FILE_gcc}"
+      "LINKER:--script=${LD_FILE_GCC}"
       # nanolib
       --specs=nosys.specs
       --specs=nano.specs
diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake
index cc8ef2fcb..3137c4fcd 100644
--- a/hw/bsp/nrf/boards/pca10056/board.cmake
+++ b/hw/bsp/nrf/boards/pca10056/board.cmake
@@ -1,5 +1,5 @@
 set(MCU_VARIANT nrf52840)
-set(LD_FILE_gcc ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+set(LD_FILE_GCC ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
index e90d76e91..a0562c738 100644
--- a/hw/bsp/nrf/boards/pca10095/board.cmake
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -1,5 +1,5 @@
 set(MCU_VARIANT nrf5340_application)
-set(LD_FILE_gcc ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
+set(LD_FILE_GCC ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 2c5d7a431..e94aeb9bd 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -55,7 +55,7 @@ if (NOT TARGET ${BOARD_TARGET})
   update_board(${BOARD_TARGET})
 
   if (NOT DEFINED LD_FILE_${TOOLCHAIN})
-    set(LD_FILE_gcc ${NRFX_DIR}/mdk/${MCU_VARIANT}_xxaa.ld)
+    set(LD_FILE_GCC ${NRFX_DIR}/mdk/${MCU_VARIANT}_xxaa.ld)
   endif ()
 
   if (TOOLCHAIN STREQUAL "gcc")
@@ -64,7 +64,7 @@ if (NOT TARGET ${BOARD_TARGET})
       )
     target_link_options(${BOARD_TARGET} PUBLIC
       # linker file
-      "LINKER:--script=${LD_FILE_gcc}"
+      "LINKER:--script=${LD_FILE_GCC}"
       -L${NRFX_DIR}/mdk
       # nanolib
       --specs=nosys.specs
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
index c9f2a9c8e..145490921 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
@@ -1,11 +1,11 @@
 #set(MCU_VARIANT MIMXRT1011)
 set(JLINK_DEVICE STM32G0B1RE)
 
-set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/STM32G0B1RETx_FLASH.ld)
-set(LD_FILE_iar ${ST_CMSIS}/Source/Templates/iar/linker/stm32g0b1xx_flash.icf)
+set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/STM32G0B1RETx_FLASH.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/stm32g0b1xx_flash.icf)
 
-set(STARTUP_FILE_gcc ${ST_CMSIS}/Source/Templates/gcc/startup_stm32g0b1xx.s)
-set(STARTUP_FILE_iar ${ST_CMSIS}/Source/Templates/iar/startup_stm32g0b1xx.s)
+set(STARTUP_FILE_GCC ${ST_CMSIS}/Source/Templates/gcc/startup_stm32g0b1xx.s)
+set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_stm32g0b1xx.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index 184dc6062..d77b3c102 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -28,50 +28,49 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
-set(BOARD_TARGET board_${BOARD})
-if (NOT TARGET ${BOARD_TARGET})
-  add_library(${BOARD_TARGET} STATIC
-    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_LIST_DIR}
-    ${CMSIS_5}/CMSIS/Core/Include
-    ${ST_CMSIS}/Include
-    ${ST_HAL_DRIVER}/Inc
-    )
-  target_compile_options(${BOARD_TARGET} PUBLIC
-    )
-  target_compile_definitions(${BOARD_TARGET} PUBLIC
-    )
-  update_board(${BOARD_TARGET})
-
-  target_sources(${BOARD_TARGET} PUBLIC
-    ${STARTUP_FILE_${TOOLCHAIN}}
-    )
-
-  if (TOOLCHAIN STREQUAL "gcc")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_gcc}"
-      -nostartfiles
-      # nanolib
-      --specs=nosys.specs
-      --specs=nano.specs
+function(add_board_target TARGET)
+  if (NOT TARGET ${TARGET})
+    add_library(${TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
       )
-  else ()
-    # TODO support IAR
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--config=${LD_FILE_iar}"
+    target_include_directories(${TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
       )
+    target_compile_options(${TARGET} PUBLIC
+      )
+    target_compile_definitions(${TARGET} PUBLIC
+      )
+
+    update_board(${TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GCC")
+      target_link_options(${TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GCC}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      # TODO support IAR
+      target_link_options(${TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
   endif ()
-endif () # BOARD_TARGET
+endfunction()
 
 
 #------------------------------------
@@ -80,6 +79,9 @@ endif () # BOARD_TARGET
 function(family_configure_example TARGET)
   family_configure_common(${TARGET})
 
+  # Board target
+  add_board_target(board_${BOARD})
+
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
@@ -100,7 +102,7 @@ function(family_configure_example TARGET)
   family_add_tinyusb(${TARGET} OPT_MCU_STM32G0)
 
   # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
   # Flashing
   family_flash_stlink(${TARGET})
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
index 4e8f3f059..3a4849ef6 100644
--- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
@@ -1,11 +1,11 @@
 set(MCU_VARIANT stm32g474xx)
 set(JLINK_DEVICE stm32g474re)
 
-set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
-set(LD_FILE_iar ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
 
-set(STARTUP_FILE_gcc ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_iar ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_GCC ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
index 8cc633449..f13f1fc28 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
@@ -1,11 +1,11 @@
 set(MCU_VARIANT stm32g474xx)
 set(JLINK_DEVICE stm32g474re)
 
-set(LD_FILE_gcc ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
-set(LD_FILE_iar ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
 
-set(STARTUP_FILE_gcc ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_iar ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_GCC ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index 5578a9b6c..c87486677 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -59,7 +59,7 @@ if (NOT TARGET ${BOARD_TARGET})
 
   if (TOOLCHAIN STREQUAL "gcc")
     target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_gcc}"
+      "LINKER:--script=${LD_FILE_GCC}"
       -nostartfiles
       # nanolib
       --specs=nosys.specs
@@ -68,7 +68,7 @@ if (NOT TARGET ${BOARD_TARGET})
   else ()
     # TODO support IAR
     target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--config=${LD_FILE_iar}"
+      "LINKER:--config=${LD_FILE_IAR}"
       )
   endif ()
 endif () # BOARD_TARGET
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index ad9fbc7c0..09f41c9ab 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -65,6 +65,8 @@ function(add_tinyusb TARGET)
       -Wreturn-type
       -Wredundant-decls
       )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+
   endif ()
 endfunction()
 
diff --git a/tools/cmake/cpu/cortex-m0plus.cmake b/tools/cmake/cpu/cortex-m0plus.cmake
index 1e316ccfc..bc2257048 100644
--- a/tools/cmake/cpu/cortex-m0plus.cmake
+++ b/tools/cmake/cpu/cortex-m0plus.cmake
@@ -1,11 +1,17 @@
 if (TOOLCHAIN STREQUAL "gcc")
-  list(APPEND TOOLCHAIN_COMMON_FLAGS
+  set(TOOLCHAIN_COMMON_FLAGS
     -mthumb
     -mcpu=cortex-m0plus
     -mfloat-abi=soft
     )
 
   set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
-else ()
-  # TODO support IAR
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m0
+    )
+
+  set(FREERTOS_PORT IAR_ARM_CM0 CACHE INTERNAL "")
+
 endif ()
diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake
index c7f12f43a..6dd1e7002 100644
--- a/tools/cmake/toolchain/arm_gcc.cmake
+++ b/tools/cmake/toolchain/arm_gcc.cmake
@@ -1,8 +1,8 @@
 set(CMAKE_SYSTEM_NAME Generic)
 
-set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc")
 set(CMAKE_C_COMPILER "arm-none-eabi-gcc")
 set(CMAKE_CXX_COMPILER "arm-none-eabi-g++")
+set(CMAKE_ASM_COMPILER "arm-none-eabi-gcc")
 
 set(CMAKE_SIZE "arm-none-eabi-size" CACHE FILEPATH "")
 set(CMAKE_OBJCOPY "arm-none-eabi-objcopy" CACHE FILEPATH "")
@@ -29,13 +29,13 @@ list(APPEND TOOLCHAIN_COMMON_FLAGS
   -fno-strict-aliasing
   )
 
-list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS
+set(TOOLCHAIN_EXE_LINKER_FLAGS
   -Wl,--print-memory-usage
   -Wl,--gc-sections
   -Wl,--cref
   )
 
-list(APPEND TOOLCHAIN_WARNING_FLAGS
+set(TOOLCHAIN_WARNING_FLAGS
   -Wall
   -Wextra
   -Werror
@@ -62,3 +62,11 @@ list(APPEND TOOLCHAIN_WARNING_FLAGS
   )
 
 include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake)
+
+# try_compile is cmake test compiling its own example,
+# pass -nostdlib to skip stdlib linking
+get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
+if (IS_IN_TRY_COMPILE)
+  set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
+  set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
+endif ()
diff --git a/tools/cmake/toolchain/arm_iar.cmake b/tools/cmake/toolchain/arm_iar.cmake
new file mode 100644
index 000000000..dfbe55e0d
--- /dev/null
+++ b/tools/cmake/toolchain/arm_iar.cmake
@@ -0,0 +1,34 @@
+set(CMAKE_SYSTEM_NAME Generic)
+
+set(CMAKE_C_COMPILER "iccarm")
+set(CMAKE_CXX_COMPILER "iccarm")
+set(CMAKE_ASM_COMPILER "iasmarm")
+
+set(CMAKE_SIZE "size" CACHE FILEPATH "")
+set(CMAKE_OBJCOPY "ielftool" CACHE FILEPATH "")
+set(CMAKE_OBJDUMP "iefdumparm" CACHE FILEPATH "")
+
+set_property(GLOBAL PROPERTY TARGET_SUPPORTS_SHARED_LIBS FALSE)
+
+# Look for includes and libraries only in the target system prefix.
+set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
+set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
+
+# pass TOOLCHAIN_CPU to
+set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_SYSTEM_PROCESSOR)
+
+include(${CMAKE_CURRENT_LIST_DIR}/../cpu/${CMAKE_SYSTEM_PROCESSOR}.cmake)
+
+# enable all possible warnings for building examples
+list(APPEND TOOLCHAIN_COMMON_FLAGS
+  )
+
+list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS
+  )
+
+list(APPEND TOOLCHAIN_WARNING_FLAGS
+  )
+
+include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake)
diff --git a/tools/cmake/toolchain/set_flags.cmake b/tools/cmake/toolchain/set_flags.cmake
index 6f74fe673..44930ef4d 100644
--- a/tools/cmake/toolchain/set_flags.cmake
+++ b/tools/cmake/toolchain/set_flags.cmake
@@ -1,9 +1,10 @@
 include(CMakePrintHelpers)
+
+# join the toolchain flags into a single string
+list(JOIN TOOLCHAIN_COMMON_FLAGS " " TOOLCHAIN_COMMON_FLAGS)
+
 foreach (LANG IN ITEMS C CXX ASM)
-  # join the toolchain flags into a single string
-  list(APPEND TOOLCHAIN_${LANG}_FLAGS ${TOOLCHAIN_COMMON_FLAGS})
-  list(JOIN TOOLCHAIN_${LANG}_FLAGS " " TOOLCHAIN_${LANG}_FLAGS)
-  set(CMAKE_${LANG}_FLAGS_INIT "${TOOLCHAIN_${LANG}_FLAGS}")
+  set(CMAKE_${LANG}_FLAGS_INIT ${TOOLCHAIN_COMMON_FLAGS})
 
   #cmake_print_variables(CMAKE_${LANG}_FLAGS_INIT)
 
@@ -14,11 +15,3 @@ endforeach ()
 
 # Linker
 list(JOIN TOOLCHAIN_EXE_LINKER_FLAGS " " CMAKE_EXE_LINKER_FLAGS_INIT)
-
-# try_compile is cmake test compiling its own example,
-# pass -nostdlib to skip stdlib linking
-get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE)
-if (IS_IN_TRY_COMPILE)
-  set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib")
-  set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib")
-endif ()

From bb795e6a5eededff57f18336c11b84f5470d4e4e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Jun 2023 15:26:16 +0700
Subject: [PATCH 1773/2085] update cmake to build with IAR for g0 and g4

---
 hw/bsp/family_support.cmake                   |   2 +-
 hw/bsp/imxrt/family.cmake                     | 124 ++++++++++--------
 .../lpc18/boards/lpcxpresso18s37/board.cmake  |   2 +-
 hw/bsp/lpc18/boards/mcb1800/board.cmake       |   2 +-
 hw/bsp/lpc18/family.cmake                     |  86 ++++++------
 .../boards/double_m33_express/board.cmake     |   2 +-
 hw/bsp/lpc55/family.cmake                     | 108 ++++++++-------
 hw/bsp/mcx/family.cmake                       | 100 +++++++-------
 hw/bsp/nrf/boards/pca10056/board.cmake        |   2 +-
 hw/bsp/nrf/boards/pca10095/board.cmake        |   2 +-
 hw/bsp/nrf/family.cmake                       |  99 ++++++++------
 .../boards/stm32g0b1nucleo/board.cmake        |   4 +-
 hw/bsp/stm32g0/family.cmake                   |  37 +++---
 .../stm32g4/boards/b_g474e_dpow1/board.cmake  |   4 +-
 .../boards/stm32g474nucleo/board.cmake        |   4 +-
 hw/bsp/stm32g4/family.cmake                   |  97 +++++++-------
 tools/cmake/cpu/cortex-m3.cmake               |  12 +-
 tools/cmake/cpu/cortex-m33.cmake              |  13 +-
 tools/cmake/cpu/cortex-m4.cmake               |  13 +-
 tools/cmake/cpu/cortex-m7.cmake               |  13 +-
 20 files changed, 415 insertions(+), 311 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index e801f0116..fdcd9a983 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -108,7 +108,7 @@ function(family_configure_common TARGET)
     COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${TARGET}>
     )
 
-  if (CMAKE_C_COMPILER_ID STREQUAL "GCC")
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
     # Generate map file
     target_link_options(${TARGET} PUBLIC
       # link map
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index b5d47614e..f687fe833 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -4,8 +4,11 @@ if (NOT BOARD)
   message(FATAL_ERROR "BOARD not specified")
 endif ()
 
-# enable LTO
-set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
@@ -13,66 +16,79 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS MIMXRT CACHE INTERNAL "")
 
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
 
 
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
-set(BOARD_TARGET board_${BOARD})
-if (NOT TARGET ${BOARD_TARGET})
-  set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
-  set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${SDK_DIR}/drivers/common/fsl_common.c
+      ${SDK_DIR}/drivers/igpio/fsl_gpio.c
+      ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/project_template/clock_config.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      __ARMVFP__=0
+      __ARMFPV5__=0
+      XIP_EXTERNAL_FLASH=1
+      XIP_BOOT_HEADER_ENABLE=1
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      ${SDK_DIR}/devices/${MCU_VARIANT}
+      ${SDK_DIR}/devices/${MCU_VARIANT}/project_template
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+      ${SDK_DIR}/drivers/common
+      ${SDK_DIR}/drivers/igpio
+      ${SDK_DIR}/drivers/lpuart
+      )
 
-  add_library(${BOARD_TARGET} STATIC
-    ${SDK_DIR}/drivers/common/fsl_common.c
-    ${SDK_DIR}/drivers/igpio/fsl_gpio.c
-    ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/project_template/clock_config.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-    )
-  target_compile_definitions(${BOARD_TARGET} PUBLIC
-    __ARMVFP__=0
-    __ARMFPV5__=0
-    XIP_EXTERNAL_FLASH=1
-    XIP_BOOT_HEADER_ENABLE=1
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMSIS_DIR}/CMSIS/Core/Include
-    ${SDK_DIR}/devices/${MCU_VARIANT}
-    ${SDK_DIR}/devices/${MCU_VARIANT}/project_template
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-    ${SDK_DIR}/drivers/common
-    ${SDK_DIR}/drivers/igpio
-    ${SDK_DIR}/drivers/lpuart
-    )
-  update_board(${BOARD_TARGET})
+    update_board(${BOARD_TARGET})
 
-  if (NOT DEFINED LD_FILE_${TOOLCHAIN})
-    set(LD_FILE_GCC ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
-  endif ()
+    # LD_FILE and STARTUP_FILE can be defined in board.cmake
+    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+      set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
+      #set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
+    endif ()
+
+    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+      set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+      #set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+    endif ()
 
-  if (TOOLCHAIN STREQUAL "gcc")
     target_sources(${BOARD_TARGET} PUBLIC
-      ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
       )
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GCC}"
-      # nanolib
-      --specs=nosys.specs
-      --specs=nano.specs
-      # force linker to look for these symbols
-      -Wl,-uimage_vector_table
-      -Wl,-ug_boot_data
-      )
-  else ()
-    # TODO support IAR
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        # force linker to look for these symbols
+        -Wl,-uimage_vector_table
+        -Wl,-ug_boot_data
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
   endif ()
-endif () # BOARD_TARGET
+endfunction()
 
 
 #------------------------------------
@@ -81,6 +97,9 @@ endif () # BOARD_TARGET
 function(family_configure_example TARGET)
   family_configure_common(${TARGET})
 
+  # Board target
+  add_board_target(board_${BOARD})
+
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
@@ -103,12 +122,11 @@ function(family_configure_example TARGET)
   family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT)
 
   # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
   # Flashing
   family_flash_jlink(${TARGET})
-  family_flash_nxplink(${TARGET})
-  #family_flash_pyocd(${TARGET})
+  #family_flash_nxplink(${TARGET})
 endfunction()
 
 
diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
index 00686ca01..3abe6f3bb 100644
--- a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.cmake
@@ -4,7 +4,7 @@ set(JLINK_DEVICE LPC18S37)
 set(PYOCD_TARGET LPC18S37)
 set(NXPLINK_DEVICE LPC18S37:LPCXPRESSO18S37)
 
-set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld)
 
 function(update_board TARGET)
   # nothing to do
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.cmake b/hw/bsp/lpc18/boards/mcb1800/board.cmake
index cfc2739e3..f6fae89d7 100644
--- a/hw/bsp/lpc18/boards/mcb1800/board.cmake
+++ b/hw/bsp/lpc18/boards/mcb1800/board.cmake
@@ -4,7 +4,7 @@ set(JLINK_DEVICE LPC1857)
 set(PYOCD_TARGET LPC1857)
 set(NXPLINK_DEVICE LPC1857:MCB1857)
 
-set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld)
 
 function(update_board TARGET)
   # nothing to do
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index 38b0f61fc..bcdec9c01 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -6,8 +6,8 @@ endif ()
 
 set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc18xx/lpc_chip_18xx)
 
-# enable LTO
-set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
@@ -15,48 +15,56 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
 
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
 
 
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
-set(BOARD_TARGET board_${BOARD})
-if (NOT TARGET ${BOARD_TARGET})
-  add_library(${BOARD_TARGET} STATIC
-    ${SDK_DIR}/../gcc/cr_startup_lpc18xx.c
-    ${SDK_DIR}/src/chip_18xx_43xx.c
-    ${SDK_DIR}/src/clock_18xx_43xx.c
-    ${SDK_DIR}/src/gpio_18xx_43xx.c
-    ${SDK_DIR}/src/sysinit_18xx_43xx.c
-    ${SDK_DIR}/src/uart_18xx_43xx.c
-    )
-  target_compile_options(${BOARD_TARGET} PUBLIC
-    -nostdlib
-    )
-  target_compile_definitions(${BOARD_TARGET} PUBLIC
-    __USE_LPCOPEN
-    CORE_M3
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${SDK_DIR}/inc
-    ${SDK_DIR}/inc/config_18xx
-    )
-  update_board(${BOARD_TARGET})
-
-  if (TOOLCHAIN STREQUAL "gcc")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GCC}"
-      # nanolib
-      --specs=nosys.specs
-      --specs=nano.specs
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${SDK_DIR}/../gcc/cr_startup_lpc18xx.c
+      ${SDK_DIR}/src/chip_18xx_43xx.c
+      ${SDK_DIR}/src/clock_18xx_43xx.c
+      ${SDK_DIR}/src/gpio_18xx_43xx.c
+      ${SDK_DIR}/src/sysinit_18xx_43xx.c
+      ${SDK_DIR}/src/uart_18xx_43xx.c
       )
-  else ()
-    # TODO support IAR
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -nostdlib
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      __USE_LPCOPEN
+      CORE_M3
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${SDK_DIR}/inc
+      ${SDK_DIR}/inc/config_18xx
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
   endif ()
-endif () # BOARD_TARGET
+endfunction()
 
 
 #------------------------------------
@@ -65,6 +73,9 @@ endif () # BOARD_TARGET
 function(family_configure_example TARGET)
   family_configure_common(${TARGET})
 
+  # Board target
+  add_board_target(board_${BOARD})
+
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
@@ -87,10 +98,11 @@ function(family_configure_example TARGET)
   family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX)
 
   # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
   # Flashing
   family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
 endfunction()
 
 
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.cmake b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
index 62b0993dc..f84e629c7 100644
--- a/hw/bsp/lpc55/boards/double_m33_express/board.cmake
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
@@ -5,7 +5,7 @@ set(JLINK_DEVICE LPC55S69)
 set(PYOCD_TARGET LPC55S69)
 set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
-set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 967ed3fa6..22a09ce10 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -31,58 +31,67 @@ endif()
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
-set(BOARD_TARGET board_${BOARD})
-if (NOT TARGET ${BOARD_TARGET})
-  add_library(${BOARD_TARGET} STATIC
-    # driver
-    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
-    ${SDK_DIR}/drivers/common/fsl_common_arm.c
-    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
-    # mcu
-    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
-    )
-  target_compile_definitions(${BOARD_TARGET} PUBLIC
-    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${TOP}/lib/sct_neopixel
-    # driver
-    ${SDK_DIR}/drivers/common
-    ${SDK_DIR}/drivers/flexcomm
-    ${SDK_DIR}/drivers/lpc_iocon
-    ${SDK_DIR}/drivers/lpc_gpio
-    ${SDK_DIR}/drivers/lpuart
-    ${SDK_DIR}/drivers/sctimer
-    # mcu
-    ${CMSIS_DIR}/CMSIS/Core/Include
-    ${SDK_DIR}/devices/${MCU_VARIANT}
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-    )
-  update_board(${BOARD_TARGET})
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      # driver
+      ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+      ${SDK_DIR}/drivers/common/fsl_common_arm.c
+      ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+      ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+      # mcu
+      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${TOP}/lib/sct_neopixel
+      # driver
+      ${SDK_DIR}/drivers/common
+      ${SDK_DIR}/drivers/flexcomm
+      ${SDK_DIR}/drivers/lpc_iocon
+      ${SDK_DIR}/drivers/lpc_gpio
+      ${SDK_DIR}/drivers/lpuart
+      ${SDK_DIR}/drivers/sctimer
+      # mcu
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      ${SDK_DIR}/devices/${MCU_VARIANT}
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+      )
 
-  if (NOT DEFINED LD_FILE_${TOOLCHAIN})
-    set(LD_FILE_GCC ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
-  endif ()
+    update_board(${BOARD_TARGET})
+
+    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+      set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+    endif ()
+
+    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+      set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+    endif ()
 
-  if (TOOLCHAIN STREQUAL "gcc")
     target_sources(${BOARD_TARGET} PUBLIC
-      ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
       )
-    target_link_options(${BOARD_TARGET} PUBLIC
-      # linker file
-      "LINKER:--script=${LD_FILE_GCC}"
-      # nanolib
-      --specs=nosys.specs
-      --specs=nano.specs
-      )
-  else ()
-    # TODO support IAR
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        # linker file
+        "LINKER:--script=${LD_FILE_GNU}"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
   endif ()
-endif () # BOARD_TARGET
+endfunction()
 
 
 #------------------------------------
@@ -91,6 +100,9 @@ endif () # BOARD_TARGET
 function(family_configure_example TARGET)
   family_configure_common(${TARGET})
 
+  # Board target
+  add_board_target(board_${BOARD})
+
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
@@ -113,7 +125,7 @@ function(family_configure_example TARGET)
   family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX)
 
   # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
   # Flashing
   family_flash_jlink(${TARGET})
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 17f54a53b..1dbf6f8f7 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -7,8 +7,8 @@ endif ()
 set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
 set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
-# enable LTO
-set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
@@ -16,57 +16,64 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
 
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
 
 
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
-set(BOARD_TARGET board_${BOARD})
-if (NOT TARGET ${BOARD_TARGET})
-  add_library(${BOARD_TARGET} STATIC
-    # external driver
-    #lib/sct_neopixel/sct_neopixel.c
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      # external driver
+      #lib/sct_neopixel/sct_neopixel.c
 
-    # driver
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
-    # mcu
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
-    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
-    )
-#  target_compile_definitions(${BOARD_TARGET} PUBLIC
-#    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    # driver
-    # mcu
-    ${CMSIS_DIR}/CMSIS/Core/Include
-    ${SDK_DIR}/devices/${MCU_VARIANT}
-    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-    )
-  update_board(${BOARD_TARGET})
+      # driver
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_gpio.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_common_arm.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpuart.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_lpflexcomm.c
+      # mcu
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+      )
+    #  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    #    )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      # driver
+      # mcu
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      ${SDK_DIR}/devices/${MCU_VARIANT}
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+      )
 
-  if (TOOLCHAIN STREQUAL "gcc")
-    target_sources(${BOARD_TARGET} PUBLIC
-      ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
-      )
-    cmake_print_variables(CMAKE_CURRENT_BINARY_DIR)
-    target_link_options(${BOARD_TARGET} PUBLIC
-      # linker file
-      "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
-      # nanolib
-      --specs=nosys.specs
-      --specs=nano.specs
-      )
-  else ()
-    # TODO support IAR
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_sources(${BOARD_TARGET} PUBLIC
+        ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S
+        )
+      target_link_options(${BOARD_TARGET} PUBLIC
+        # linker file
+        "LINKER:--script=${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
   endif ()
-endif () # BOARD_TARGET
+endfunction()
 
 
 #------------------------------------
@@ -75,6 +82,9 @@ endif () # BOARD_TARGET
 function(family_configure_example TARGET)
   family_configure_common(${TARGET})
 
+  # Board target
+  add_board_target(board_${BOARD})
+
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
@@ -95,7 +105,7 @@ function(family_configure_example TARGET)
   family_add_tinyusb(${TARGET} OPT_MCU_MCXN9)
 
   # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
   # Flashing
   family_flash_jlink(${TARGET})
diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake
index 3137c4fcd..b4fe39fc0 100644
--- a/hw/bsp/nrf/boards/pca10056/board.cmake
+++ b/hw/bsp/nrf/boards/pca10056/board.cmake
@@ -1,5 +1,5 @@
 set(MCU_VARIANT nrf52840)
-set(LD_FILE_GCC ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
index a0562c738..1eb8ad4f1 100644
--- a/hw/bsp/nrf/boards/pca10095/board.cmake
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -1,5 +1,5 @@
 set(MCU_VARIANT nrf5340_application)
-set(LD_FILE_GCC ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index e94aeb9bd..7faeaf6cb 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -10,9 +10,6 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
-# enable LTO
-set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-
 # toolchain set up
 if (MCU_VARIANT STREQUAL "nrf5340_application")
   set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
@@ -26,54 +23,69 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
 
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
 
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
-set(BOARD_TARGET board_${BOARD})
-if (NOT TARGET ${BOARD_TARGET})
-  add_library(${BOARD_TARGET} STATIC
-    # driver
-    ${NRFX_DIR}/drivers/src/nrfx_power.c
-    ${NRFX_DIR}/drivers/src/nrfx_uarte.c
-    # mcu
-    ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c
-    )
-  target_compile_definitions(${BOARD_TARGET} PUBLIC
-    CONFIG_GPIO_AS_PINRESET
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_LIST_DIR}
-    ${NRFX_DIR}
-    ${NRFX_DIR}/mdk
-    ${NRFX_DIR}/hal
-    ${NRFX_DIR}/drivers/include
-    ${NRFX_DIR}/drivers/src
-    ${CMSIS_DIR}/CMSIS/Core/Include
-    )
-  update_board(${BOARD_TARGET})
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      # driver
+      ${NRFX_DIR}/drivers/src/nrfx_power.c
+      ${NRFX_DIR}/drivers/src/nrfx_uarte.c
+      # mcu
+      ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CONFIG_GPIO_AS_PINRESET
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${NRFX_DIR}
+      ${NRFX_DIR}/mdk
+      ${NRFX_DIR}/hal
+      ${NRFX_DIR}/drivers/include
+      ${NRFX_DIR}/drivers/src
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      )
 
-  if (NOT DEFINED LD_FILE_${TOOLCHAIN})
-    set(LD_FILE_GCC ${NRFX_DIR}/mdk/${MCU_VARIANT}_xxaa.ld)
-  endif ()
+    update_board(${BOARD_TARGET})
+
+    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+      set(LD_FILE_GNU ${NRFX_DIR}/mdk/${MCU_VARIANT}_xxaa.ld)
+    endif ()
+
+    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+      set(STARTUP_FILE_GNU ${NRFX_DIR}/mdk/gcc_startup_${MCU_VARIANT}.S)
+    endif ()
 
-  if (TOOLCHAIN STREQUAL "gcc")
     target_sources(${BOARD_TARGET} PUBLIC
-      ${NRFX_DIR}/mdk/gcc_startup_${MCU_VARIANT}.S
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
       )
-    target_link_options(${BOARD_TARGET} PUBLIC
-      # linker file
-      "LINKER:--script=${LD_FILE_GCC}"
-      -L${NRFX_DIR}/mdk
-      # nanolib
-      --specs=nosys.specs
-      --specs=nano.specs
-      )
-  else ()
-    # TODO support IAR
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        # linker file
+        "LINKER:--script=${LD_FILE_GNU}"
+        -L${NRFX_DIR}/mdk
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
   endif ()
-endif () # BOARD_TARGET
+endfunction()
 
 
 #------------------------------------
@@ -82,6 +94,9 @@ endif () # BOARD_TARGET
 function(family_configure_example TARGET)
   family_configure_common(${TARGET})
 
+  # Board target
+  add_board_target(board_${BOARD})
+
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
@@ -102,7 +117,7 @@ function(family_configure_example TARGET)
   family_add_tinyusb(${TARGET} OPT_MCU_NRF5X)
 
   # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
   # Flashing
   family_flash_jlink(${TARGET})
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
index 145490921..1ebf8a700 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
@@ -1,10 +1,10 @@
 #set(MCU_VARIANT MIMXRT1011)
 set(JLINK_DEVICE STM32G0B1RE)
 
-set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/STM32G0B1RETx_FLASH.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G0B1RETx_FLASH.ld)
 set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/stm32g0b1xx_flash.icf)
 
-set(STARTUP_FILE_GCC ${ST_CMSIS}/Source/Templates/gcc/startup_stm32g0b1xx.s)
+set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_stm32g0b1xx.s)
 set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_stm32g0b1xx.s)
 
 function(update_board TARGET)
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index d77b3c102..988033070 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -11,8 +11,8 @@ set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
 set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
 set(CMSIS_5 ${TOP}/lib/CMSIS_5)
 
-# enable LTO
-#set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
@@ -20,17 +20,21 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32G0 CACHE INTERNAL "")
 
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
 
 
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
-function(add_board_target TARGET)
-  if (NOT TARGET ${TARGET})
-    add_library(${TARGET} STATIC
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
       ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
@@ -42,30 +46,31 @@ function(add_board_target TARGET)
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
       ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
       )
-    target_include_directories(${TARGET} PUBLIC
+    target_include_directories(${BOARD_TARGET} PUBLIC
       ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
       ${CMSIS_5}/CMSIS/Core/Include
       ${ST_CMSIS}/Include
       ${ST_HAL_DRIVER}/Inc
       )
-    target_compile_options(${TARGET} PUBLIC
+    target_compile_options(${BOARD_TARGET} PUBLIC
       )
-    target_compile_definitions(${TARGET} PUBLIC
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
       )
 
-    update_board(${TARGET})
+    update_board(${BOARD_TARGET})
 
-    if (CMAKE_C_COMPILER_ID STREQUAL "GCC")
-      target_link_options(${TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_GCC}"
+    cmake_print_variables(CMAKE_C_COMPILER_ID)
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
         -nostartfiles
         # nanolib
         --specs=nosys.specs
         --specs=nano.specs
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      # TODO support IAR
-      target_link_options(${TARGET} PUBLIC
+      target_link_options(${BOARD_TARGET} PUBLIC
         "LINKER:--config=${LD_FILE_IAR}"
         )
     endif ()
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
index 3a4849ef6..9b72672ea 100644
--- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
@@ -1,10 +1,10 @@
 set(MCU_VARIANT stm32g474xx)
 set(JLINK_DEVICE stm32g474re)
 
-set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
 set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
 
-set(STARTUP_FILE_GCC ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
 set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
index f13f1fc28..88cd616b3 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
@@ -1,10 +1,10 @@
 set(MCU_VARIANT stm32g474xx)
 set(JLINK_DEVICE stm32g474re)
 
-set(LD_FILE_GCC ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
 set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
 
-set(STARTUP_FILE_GCC ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
 set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index c87486677..ab17c0980 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -11,8 +11,8 @@ set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
 set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
 set(CMSIS_5 ${TOP}/lib/CMSIS_5)
 
-# enable LTO
-set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
@@ -20,58 +20,60 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32G4 CACHE INTERNAL "")
 
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
 
 
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
-set(BOARD_TARGET board_${BOARD})
-if (NOT TARGET ${BOARD_TARGET})
-  add_library(${BOARD_TARGET} STATIC
-    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
-    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    ${CMAKE_CURRENT_LIST_DIR}
-    ${CMSIS_5}/CMSIS/Core/Include
-    ${ST_CMSIS}/Include
-    ${ST_HAL_DRIVER}/Inc
-    )
-  target_compile_options(${BOARD_TARGET} PUBLIC
-    )
-  target_compile_definitions(${BOARD_TARGET} PUBLIC
-    )
-  update_board(${BOARD_TARGET})
-
-  target_sources(${BOARD_TARGET} PUBLIC
-    ${STARTUP_FILE_${TOOLCHAIN}}
-    )
-
-  if (TOOLCHAIN STREQUAL "gcc")
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--script=${LD_FILE_GCC}"
-      -nostartfiles
-      # nanolib
-      --specs=nosys.specs
-      --specs=nano.specs
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
       )
-  else ()
-    # TODO support IAR
-    target_link_options(${BOARD_TARGET} PUBLIC
-      "LINKER:--config=${LD_FILE_IAR}"
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
       )
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
   endif ()
-endif () # BOARD_TARGET
+endfunction()
 
 
 #------------------------------------
@@ -80,6 +82,9 @@ endif () # BOARD_TARGET
 function(family_configure_example TARGET)
   family_configure_common(${TARGET})
 
+  # Board target
+  add_board_target(board_${BOARD})
+
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
@@ -100,7 +105,7 @@ function(family_configure_example TARGET)
   family_add_tinyusb(${TARGET} OPT_MCU_STM32G4)
 
   # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC ${BOARD_TARGET} ${TARGET}-tinyusb)
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
   # Flashing
   family_flash_stlink(${TARGET})
diff --git a/tools/cmake/cpu/cortex-m3.cmake b/tools/cmake/cpu/cortex-m3.cmake
index b740ee44c..f6f5a62f8 100644
--- a/tools/cmake/cpu/cortex-m3.cmake
+++ b/tools/cmake/cpu/cortex-m3.cmake
@@ -1,10 +1,16 @@
 if (TOOLCHAIN STREQUAL "gcc")
-  list(APPEND TOOLCHAIN_COMMON_FLAGS
+  set(TOOLCHAIN_COMMON_FLAGS
     -mthumb
     -mcpu=cortex-m3
     )
 
   set(FREERTOS_PORT GCC_ARM_CM3 CACHE INTERNAL "")
-else ()
-  # TODO support IAR
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m3
+    )
+
+  set(FREERTOS_PORT IAR_ARM_CM3 CACHE INTERNAL "")
+
 endif ()
diff --git a/tools/cmake/cpu/cortex-m33.cmake b/tools/cmake/cpu/cortex-m33.cmake
index fda277010..7ebaf1748 100644
--- a/tools/cmake/cpu/cortex-m33.cmake
+++ b/tools/cmake/cpu/cortex-m33.cmake
@@ -1,5 +1,5 @@
 if (TOOLCHAIN STREQUAL "gcc")
-  list(APPEND TOOLCHAIN_COMMON_FLAGS
+  set(TOOLCHAIN_COMMON_FLAGS
     -mthumb
     -mcpu=cortex-m33
     -mfloat-abi=hard
@@ -7,6 +7,13 @@ if (TOOLCHAIN STREQUAL "gcc")
     )
 
   set(FREERTOS_PORT GCC_ARM_CM33_NTZ_NONSECURE CACHE INTERNAL "")
-else ()
-  # TODO support IAR
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m33
+    --fpu VFPv5-SP
+    )
+
+  set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
+
 endif ()
diff --git a/tools/cmake/cpu/cortex-m4.cmake b/tools/cmake/cpu/cortex-m4.cmake
index 5a2d16c05..a0cf3498f 100644
--- a/tools/cmake/cpu/cortex-m4.cmake
+++ b/tools/cmake/cpu/cortex-m4.cmake
@@ -1,5 +1,5 @@
 if (TOOLCHAIN STREQUAL "gcc")
-  list(APPEND TOOLCHAIN_COMMON_FLAGS
+  set(TOOLCHAIN_COMMON_FLAGS
     -mthumb
     -mcpu=cortex-m4
     -mfloat-abi=hard
@@ -7,6 +7,13 @@ if (TOOLCHAIN STREQUAL "gcc")
     )
 
   set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
-else ()
-  # TODO support IAR
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m4
+    --fpu VFPv4
+    )
+
+  set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
+
 endif ()
diff --git a/tools/cmake/cpu/cortex-m7.cmake b/tools/cmake/cpu/cortex-m7.cmake
index 481c86bc5..3e5f7f44b 100644
--- a/tools/cmake/cpu/cortex-m7.cmake
+++ b/tools/cmake/cpu/cortex-m7.cmake
@@ -1,5 +1,5 @@
 if (TOOLCHAIN STREQUAL "gcc")
-  list(APPEND TOOLCHAIN_COMMON_FLAGS
+  set(TOOLCHAIN_COMMON_FLAGS
     -mthumb
     -mcpu=cortex-m7
     -mfloat-abi=hard
@@ -7,6 +7,13 @@ if (TOOLCHAIN STREQUAL "gcc")
     )
 
   set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
-else ()
-  # TODO support IAR
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m7
+    --fpu VFPv5_D16
+    )
+
+  set(FREERTOS_PORT IAR_ARM_CM7 CACHE INTERNAL "")
+
 endif ()

From c2bc363f06b81e1758122167d58c40817c4d2e27 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Jun 2023 16:11:00 +0700
Subject: [PATCH 1774/2085] build g0 g4 iar cmake

---
 .github/workflows/build_iar.yml               |  28 ++-
 .../stm32g4/FreeRTOSConfig/FreeRTOSConfig.h   | 166 ++++++++++++++++++
 tools/build_cmake.py                          |  25 +--
 3 files changed, 208 insertions(+), 11 deletions(-)
 create mode 100644 hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 3da5ed40f..da741bbcf 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -23,7 +23,7 @@ concurrency:
   cancel-in-progress: true
 
 jobs:
-  build-arm:
+  makefile:
     runs-on: [self-hosted, Linux, X64, hifiphile]
     strategy:
       fail-fast: false
@@ -48,3 +48,29 @@ jobs:
 
     - name: Build
       run: python3 tools/build_family.py ${{ matrix.family }} CC=iccarm
+
+  cmake:
+    runs-on: [self-hosted, Linux, X64, hifiphile]
+    strategy:
+      fail-fast: false
+      matrix:
+        family:
+          # Alphabetical order
+          # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
+          # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
+          - 'stm32g0 stm32g4'
+    steps:
+      - name: Clean workspace
+        run: |
+          echo "Cleaning up previous run"
+          rm -rf "${{ github.workspace }}"
+          mkdir -p "${{ github.workspace }}"
+
+      - name: Checkout TinyUSB
+        uses: actions/checkout@v3
+
+      - name: Get Dependencies
+        run: python3 tools/get_deps.py ${{ matrix.family }}
+
+      - name: Build
+        run: python3 tools/build_family.py ${{ matrix.family }} -DTOOLCHAIN=iccarm
diff --git a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..7974434d3
--- /dev/null
+++ b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// IAR assembler have limited preprocessor support and it only need following macros:
+#ifndef __IASMARM__
+// FIXME cause redundant-decls warnings
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU						0
+#define configENABLE_FPU						0
+#define configENABLE_TRUSTZONE					0
+#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/tools/build_cmake.py b/tools/build_cmake.py
index d85726213..140105620 100644
--- a/tools/build_cmake.py
+++ b/tools/build_cmake.py
@@ -13,7 +13,7 @@ SKIPPED = "\033[33mskipped\033[0m"
 
 build_separator = '-' * 106
 
-make_iar_option = 'CC=iccarm'
+toolchain_iar = '-DTOOLCHAIN=iar'
 
 def filter_with_input(mylist):
     if len(sys.argv) > 1:
@@ -22,7 +22,7 @@ def filter_with_input(mylist):
             mylist[:] = input_args
 
 
-def build_family(family, make_option):
+def build_family(family, toolchain_option):
     all_boards = []
     for entry in os.scandir("hw/bsp/{}/boards".format(family)):
         if entry.is_dir() and entry.name != 'pico_sdk':
@@ -38,7 +38,7 @@ def build_family(family, make_option):
 
         # Generate build
         r = subprocess.run(f"cmake examples -B {build_dir} -G \"Ninja\" -DFAMILY={family} -DBOARD"
-                           f"={board}", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+                           f"={board} {toolchain_option}", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
 
         # Build
         if r.returncode == 0:
@@ -57,21 +57,26 @@ def build_family(family, make_option):
         flash_size = "-"
         sram_size = "-"
         example = 'all'
-        print(build_utils.build_format.format(example, board, status, "{:.2f}s".format(duration), flash_size, sram_size))
+        title = build_utils.build_format.format(example, board, status, "{:.2f}s".format(duration), flash_size, sram_size)
 
-        if r.returncode != 0:
-            # group output in CI
-            print(f"::group::{board} build error")
+        if os.getenv('CI'):
+            # always print build output if in CI
+            print(f"::group::{title} build error")
             print(r.stdout.decode("utf-8"))
             print(f"::endgroup::")
+        else:
+            # print build output if failed
+            print(title)
+            if r.returncode != 0:
+                print(r.stdout.decode("utf-8"))
 
     return ret
 
 
 if __name__ == '__main__':
     # IAR CC
-    if make_iar_option not in sys.argv:
-        make_iar_option = ''
+    if toolchain_iar not in sys.argv:
+        toolchain_iar = ''
 
     # If family are not specified in arguments, build all supported
     all_families = []
@@ -88,7 +93,7 @@ if __name__ == '__main__':
     # succeeded, failed, skipped
     total_result = [0, 0, 0]
     for family in all_families:
-        fret = build_family(family, make_iar_option)
+        fret = build_family(family, toolchain_iar)
         if len(fret) == len(total_result):
             total_result = [total_result[i] + fret[i] for i in range(len(fret))]
 

From 11fb837b51417ec41b8244ebbbab828b9f3fce37 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Jun 2023 16:15:26 +0700
Subject: [PATCH 1775/2085] fix ci

---
 .github/workflows/build_iar.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index da741bbcf..83e81164a 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -73,4 +73,4 @@ jobs:
         run: python3 tools/get_deps.py ${{ matrix.family }}
 
       - name: Build
-        run: python3 tools/build_family.py ${{ matrix.family }} -DTOOLCHAIN=iccarm
+        run: python3 tools/build_cmake.py ${{ matrix.family }} -DTOOLCHAIN=iccarm

From 2016ad72f3dad74ee752943ab29c687a82687255 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 2 Jun 2023 16:21:49 +0700
Subject: [PATCH 1776/2085] fix iar ci

---
 tools/build_cmake.py | 2 +-
 tools/build_utils.py | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/build_cmake.py b/tools/build_cmake.py
index 140105620..eb7375ae2 100644
--- a/tools/build_cmake.py
+++ b/tools/build_cmake.py
@@ -61,7 +61,7 @@ def build_family(family, toolchain_option):
 
         if os.getenv('CI'):
             # always print build output if in CI
-            print(f"::group::{title} build error")
+            print(f"::group::{title}")
             print(r.stdout.decode("utf-8"))
             print(f"::endgroup::")
         else:
diff --git a/tools/build_utils.py b/tools/build_utils.py
index ec850e732..6f907729b 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -47,6 +47,7 @@ def skip_example(example, board):
 
         mk_contents = board_mk.read_text()
 
+    mcu = "NONE"
     for token in mk_contents.split():
         if "CFG_TUSB_MCU=OPT_MCU_" in token:
             # Strip " because cmake files has them.

From 268ab5863a3437c804d6db0ea5dc9f90560e9ffc Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Wed, 24 May 2023 14:08:42 +0200
Subject: [PATCH 1777/2085] fix(RA Host Portable): git rid of the IAR warnings
 for packed

---
 src/portable/renesas/rusb2/rusb2_type.h | 146 ++++++++++++------------
 1 file changed, 73 insertions(+), 73 deletions(-)

diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 7a2898366..d80ecc62e 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -41,11 +41,11 @@ extern "C" {
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
-typedef struct TU_ATTR_PACKED {
+typedef struct {
   union {
     volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       uint16_t : 8;
       volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
       volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
@@ -56,18 +56,18 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t N; /* (@ 0x00000002) Pipe Transaction Counter Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t TRNCNT : 16; /* [15..0] Transaction Counter */
     } N_b;
   };
 } RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */
 
 /* LINK_REG Structure */
-typedef struct TU_ATTR_PACKED {
+typedef struct {
   union {
     volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t USBE  : 1; /* [0..0] USB Operation Enable */
       uint16_t                : 2;
       volatile uint16_t DMRPU : 1; /* [3..3] D- Line Resistor Control */
@@ -85,7 +85,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
       uint16_t : 12;
     } BUSWAIT_b;
@@ -94,7 +94,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile const uint16_t SYSSTS0; /* (@ 0x00000004) System Configuration Status Register 0 */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t LNST   : 2; /* [1..0] USB Data Line Status Monitor */
       volatile const uint16_t IDMON  : 1; /* [2..2] External ID0 Input Pin Monitor */
       uint16_t                       : 2;
@@ -109,7 +109,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile const uint16_t PLLSTA; /* (@ 0x00000006) PLL Status Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
       uint16_t : 15;
     } PLLSTA_b;
@@ -118,7 +118,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t DVSTCTR0; /* (@ 0x00000008) Device State Control Register 0 */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t RHST : 3; /* [2..0] USB Bus Reset Status */
       uint16_t                     : 1;
       volatile uint16_t UACT       : 1; /* [4..4] USB Bus Enable */
@@ -137,7 +137,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t TESTMODE; /* (@ 0x0000000C) USB Test Mode Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t UTST : 4; /* [3..0] Test Mode */
       uint16_t : 12;
     } TESTMODE_b;
@@ -148,7 +148,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint32_t CFIFO; /* (@ 0x00000014) CFIFO Port Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       union {
         volatile uint16_t CFIFOL; /* (@ 0x00000014) CFIFO Port Register L */
         volatile uint8_t CFIFOLL; /* (@ 0x00000014) CFIFO Port Register LL */
@@ -157,7 +157,7 @@ typedef struct TU_ATTR_PACKED {
       union {
         volatile uint16_t CFIFOH; /* (@ 0x00000016) CFIFO Port Register H */
 
-        struct {
+        struct TU_ATTR_PACKED {
           volatile const uint8_t RESERVED3;
           volatile uint8_t CFIFOHH; /* (@ 0x00000017) CFIFO Port Register HH */
         };
@@ -168,7 +168,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint32_t D0FIFO; /* (@ 0x00000018) D0FIFO Port Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       union {
         volatile uint16_t D0FIFOL; /* (@ 0x00000018) D0FIFO Port Register L */
         volatile uint8_t D0FIFOLL; /* (@ 0x00000018) D0FIFO Port Register LL */
@@ -177,7 +177,7 @@ typedef struct TU_ATTR_PACKED {
       union {
         volatile uint16_t D0FIFOH; /* (@ 0x0000001A) D0FIFO Port Register H */
 
-        struct {
+        struct TU_ATTR_PACKED {
           volatile const uint8_t RESERVED4;
           volatile uint8_t D0FIFOHH; /* (@ 0x0000001B) D0FIFO Port Register HH */
         };
@@ -188,7 +188,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint32_t D1FIFO; /* (@ 0x0000001C) D1FIFO Port Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       union {
         volatile uint16_t D1FIFOL; /* (@ 0x0000001C) D1FIFO Port Register L */
         volatile uint8_t D1FIFOLL; /* (@ 0x0000001C) D1FIFO Port Register LL */
@@ -197,7 +197,7 @@ typedef struct TU_ATTR_PACKED {
       union {
         volatile uint16_t D1FIFOH; /* (@ 0x0000001E) D1FIFO Port Register H */
 
-        struct {
+        struct TU_ATTR_PACKED {
           volatile const uint8_t RESERVED5;
           volatile uint8_t D1FIFOHH; /* (@ 0x0000001F) D1FIFO Port Register HH */
         };
@@ -208,7 +208,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t CFIFOSEL; /* (@ 0x00000020) CFIFO Port Select Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t CURPIPE : 4; /* [3..0] CFIFO Port Access Pipe Specification */
       uint16_t                  : 1;
       volatile uint16_t ISEL    : 1; /* [5..5] CFIFO Port Access Direction When DCP is Selected */
@@ -225,12 +225,12 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
       uint16_t                     : 1;
       volatile const uint16_t FRDY : 1;  /* [13..13] FIFO Port Ready */
-      volatile uint16_t BCLR       : 1;	 /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-      volatile uint16_t BVAL       : 1;	 /* [15..15] Buffer Memory Valid Flag */
+      volatile uint16_t BCLR       : 1;  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL       : 1;  /* [15..15] Buffer Memory Valid Flag */
     } CFIFOCTR_b;
   };
   volatile const uint32_t RESERVED6;
@@ -238,7 +238,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t D0FIFOSEL; /* (@ 0x00000028) D0FIFO Port Select Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
       uint16_t                  : 4;
       volatile uint16_t BIGEND  : 1; /* [8..8] FIFO Port Endian Control */
@@ -254,19 +254,19 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
       uint16_t                     : 1;
       volatile const uint16_t FRDY : 1;  /* [13..13] FIFO Port Ready */
-      volatile uint16_t BCLR       : 1;	 /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
-      volatile uint16_t BVAL       : 1;	 /* [15..15] Buffer Memory Valid Flag */
+      volatile uint16_t BCLR       : 1;  /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
+      volatile uint16_t BVAL       : 1;  /* [15..15] Buffer Memory Valid Flag */
     } D0FIFOCTR_b;
   };
 
   union {
     volatile uint16_t D1FIFOSEL; /* (@ 0x0000002C) D1FIFO Port Select Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t CURPIPE : 4; /* [3..0] FIFO Port Access Pipe Specification */
       uint16_t                  : 4;
       volatile uint16_t BIGEND  : 1; /* [8..8] FIFO Port Endian Control */
@@ -282,7 +282,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
       uint16_t                     : 1;
       volatile const uint16_t FRDY : 1;  /* [13..13] FIFO Port Ready */
@@ -294,7 +294,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
 
-    struct {
+    struct TU_ATTR_PACKED {
       uint16_t : 8;
       volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
       volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
@@ -310,7 +310,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t INTENB1; /* (@ 0x00000032) Interrupt Enable Register 1 */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PDDETINTE0 : 1; /* [0..0] PDDETINT0 Detection Interrupt Enable */
       uint16_t                     : 3;
       volatile uint16_t SACKE      : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */
@@ -329,7 +329,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t BRDYENB; /* (@ 0x00000036) BRDY Interrupt Enable Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PIPE0BRDYE : 1; /* [0..0] BRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE1BRDYE : 1; /* [1..1] BRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE2BRDYE : 1; /* [2..2] BRDY Interrupt Enable for PIPE */
@@ -347,7 +347,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t NRDYENB; /* (@ 0x00000038) NRDY Interrupt Enable Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PIPE0NRDYE : 1; /* [0..0] NRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE1NRDYE : 1; /* [1..1] NRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE2NRDYE : 1; /* [2..2] NRDY Interrupt Enable for PIPE */
@@ -365,7 +365,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t BEMPENB; /* (@ 0x0000003A) BEMP Interrupt Enable Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PIPE0BEMPE : 1; /* [0..0] BEMP Interrupt Enable for PIPE */
       volatile uint16_t PIPE1BEMPE : 1; /* [1..1] BEMP Interrupt Enable for PIPE */
       volatile uint16_t PIPE2BEMPE : 1; /* [2..2] BEMP Interrupt Enable for PIPE */
@@ -383,7 +383,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t SOFCFG; /* (@ 0x0000003C) SOF Output Configuration Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       uint16_t                        : 4;
       volatile const uint16_t EDGESTS : 1; /* [4..4] Edge Interrupt Output Status Monitor */
       volatile uint16_t INTL          : 1; /* [5..5] Interrupt Output Sense Select */
@@ -397,7 +397,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t PHYSET; /* (@ 0x0000003E) PHY Setting Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t DIRPD    : 1; /* [0..0] Power-Down Control */
       volatile uint16_t PLLRESET : 1; /* [1..1] PLL Reset Control */
       uint16_t                   : 1;
@@ -415,7 +415,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t INTSTS0; /* (@ 0x00000040) Interrupt Status Register 0 */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t CTSQ  : 3; /* [2..0] Control Transfer Stage */
       volatile uint16_t VALID       : 1; /* [3..3] USB Request Reception */
       volatile const uint16_t DVSQ  : 3; /* [6..4] Device State */
@@ -434,7 +434,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t INTSTS1; /* (@ 0x00000042) Interrupt Status Register 1 */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PDDETINT0 : 1; /* [0..0] PDDET0 Detection Interrupt Status */
       uint16_t                    : 3;
       volatile uint16_t SACK      : 1; /* [4..4] Setup Transaction Normal Response Interrupt Status */
@@ -456,7 +456,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t BRDYSTS; /* (@ 0x00000046) BRDY Interrupt Status Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PIPE0BRDY : 1; /* [0..0] BRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE1BRDY : 1; /* [1..1] BRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE2BRDY : 1; /* [2..2] BRDY Interrupt Status for PIPE */
@@ -474,7 +474,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t NRDYSTS; /* (@ 0x00000048) NRDY Interrupt Status Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PIPE0NRDY : 1; /* [0..0] NRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE1NRDY : 1; /* [1..1] NRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE2NRDY : 1; /* [2..2] NRDY Interrupt Status for PIPE */
@@ -492,7 +492,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t BEMPSTS; /* (@ 0x0000004A) BEMP Interrupt Status Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PIPE0BEMP : 1; /* [0..0] BEMP Interrupt Status for PIPE */
       volatile uint16_t PIPE1BEMP : 1; /* [1..1] BEMP Interrupt Status for PIPE */
       volatile uint16_t PIPE2BEMP : 1; /* [2..2] BEMP Interrupt Status for PIPE */
@@ -510,7 +510,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t FRMNUM; /* (@ 0x0000004C) Frame Number Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t FRNM : 11; /* [10..0] Frame NumberLatest frame number */
       uint16_t                     : 3;
       volatile uint16_t CRCE       : 1; /* [14..14] Receive Data Error */
@@ -521,7 +521,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t UFRMNUM; /* (@ 0x0000004E) uFrame Number Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t UFRNM : 3; /* [2..0] MicroframeIndicate the microframe number. */
       uint16_t                      : 12;
       volatile uint16_t DVCHG       : 1; /* [15..15] Device State Change */
@@ -531,7 +531,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t USBADDR; /* (@ 0x00000050) USB Address Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t USBADDR : 7; /* [6..0] USB Address In device controller mode */
       uint16_t                        : 1;
       volatile uint16_t STSRECOV0     : 3; /* [10..8] Status Recovery */
@@ -543,7 +543,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
       volatile uint16_t BREQUEST      : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
     } USBREQ_b;
@@ -552,7 +552,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t USBVAL; /* (@ 0x00000056) USB Request Value Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t WVALUE : 16; /* [15..0] ValueThese bits store the USB request Value value. */
     } USBVAL_b;
   };
@@ -560,7 +560,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t USBINDX; /* (@ 0x00000058) USB Request Index Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t WINDEX : 16; /* [15..0] IndexThese bits store the USB request wIndex value. */
     } USBINDX_b;
   };
@@ -568,7 +568,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t USBLENG; /* (@ 0x0000005A) USB Request Length Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t WLENGTH : 16; /* [15..0] LengthThese bits store the USB request wLength value. */
     } USBLENG_b;
   };
@@ -576,7 +576,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t DCPCFG; /* (@ 0x0000005C) DCP Configuration Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       uint16_t                 : 4;
       volatile uint16_t DIR    : 1; /* [4..4] Transfer Direction */
       uint16_t                 : 2;
@@ -589,7 +589,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t DCPMAXP; /* (@ 0x0000005E) DCP Maximum Packet Size Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t MXPS   : 7; /* [6..0] Maximum Packet Size */
       uint16_t                 : 5;
       volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
@@ -599,7 +599,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t DCPCTR; /* (@ 0x00000060) DCP Control Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PID         : 2; /* [1..0] Response PID */
       volatile uint16_t CCPL        : 1; /* [2..2] Control Transfer End Enable */
       uint16_t                      : 2;
@@ -619,7 +619,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t PIPESEL; /* (@ 0x00000064) Pipe Window Select Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
       uint16_t : 12;
     } PIPESEL_b;
@@ -629,7 +629,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t PIPECFG;      /* (@ 0x00000068) Pipe Configuration Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t EPNUM  : 4; /* [3..0] Endpoint Number */
       volatile uint16_t DIR    : 1; /* [4..4] Transfer Direction */
       uint16_t                 : 2;
@@ -646,7 +646,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t MXPS   : 9; /* [8..0] Maximum Packet Size */
       uint16_t                 : 3;
       volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
@@ -656,7 +656,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t PIPEPERI; /* (@ 0x0000006E) Pipe Cycle Control Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t IITV : 3; /* [2..0] Interval Error Detection Interval */
       uint16_t               : 9;
       volatile uint16_t IFIS : 1; /* [12..12] Isochronous IN Buffer Flush */
@@ -667,7 +667,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t PIPE_CTR[9];        /* (@ 0x00000070) Pipe [0..8] Control Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t PID          : 2; /* [1..0] Response PID */
       uint16_t                       : 3;
       volatile const uint16_t PBUSY  : 1; /* [5..5] Pipe Busy */
@@ -691,7 +691,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t USBBCCTRL0;             /* (@ 0x000000B0) BC Control Register 0 */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t RPDME0           : 1; /* [0..0] D- Pin Pull-Down Control */
       volatile uint16_t IDPSRCE0         : 1; /* [1..1] D+ Pin IDPSRC Output Control */
       volatile uint16_t
@@ -713,7 +713,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t UCKSEL; /* (@ 0x000000C4) USB Clock Selection Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
       uint16_t : 15;
     } UCKSEL_b;
@@ -724,7 +724,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t USBMC; /* (@ 0x000000CC) USB Module Control Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t VDDUSBE : 1; /* [0..0] USB Reference Power Supply Circuit On/Off Control */
       uint16_t                  : 6;
       volatile uint16_t VDCEN   : 1; /* [7..7] USB Regulator On/Off Control */
@@ -736,7 +736,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       uint16_t : 6;
       volatile uint16_t USBSPD  : 2; /* [7..6] Transfer Speed of Communication Target Device */
       volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
@@ -749,7 +749,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint32_t PHYSLEW; /* (@ 0x000000F0) PHY Cross Point Adjustment Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint32_t SLEWR00 : 1; /* [0..0] Receiver Cross Point Adjustment 00 */
       volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
       volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
@@ -762,7 +762,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       uint16_t : 7;
       volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
       uint16_t : 8;
@@ -772,7 +772,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       uint16_t : 14;
       volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
       uint16_t : 1;
@@ -783,7 +783,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t BCCTRL; /* (@ 0x00000140) Battery Charging Control Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t IDPSRCE         : 1; /* [0..0] IDPSRC Control */
       volatile uint16_t IDMSINKE        : 1; /* [1..1] IDMSINK Control */
       volatile uint16_t VDPSRCE         : 1; /* [2..2] VDPSRC Control */
@@ -801,7 +801,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t PL1CTRL1; /* (@ 0x00000144) Function L1 Control Register 1 */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t L1RESPEN   : 1; /* [0..0] L1 Response Enable */
       volatile uint16_t L1RESPMD   : 2; /* [2..1] L1 Response Mode */
       volatile uint16_t L1NEGOMD   : 1; /* [3..3] L1 Response Negotiation Control. */
@@ -816,7 +816,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
 
-    struct {
+    struct TU_ATTR_PACKED {
       uint16_t : 8;
       volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
       volatile uint16_t RWEMON  : 1;  /* [12..12] RWE Value Monitor */
@@ -827,8 +827,8 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t HL1CTRL1; /* (@ 0x00000148) Host L1 Control Register 1 */
 
-    struct {
-      volatile uint16_t L1REQ          : 1;	      /* [0..0] L1 Transition Request */
+    struct TU_ATTR_PACKED {
+      volatile uint16_t L1REQ          : 1;       /* [0..0] L1 Transition Request */
       volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
       uint16_t : 13;
     } HL1CTRL1_b;
@@ -837,7 +837,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t HL1CTRL2; /* (@ 0x0000014A) Host L1 Control Register 2 */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint16_t L1ADDR : 4; /* [3..0] LPM Token DeviceAddress */
       uint16_t                 : 4;
       volatile uint16_t HIRD   : 4; /* [11..8] LPM Token HIRD */
@@ -851,7 +851,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       uint32_t : 20;
       volatile const uint32_t DOVCAHM  : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
       volatile const uint32_t DOVCBHM  : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
@@ -864,7 +864,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       uint32_t : 4;
       volatile uint32_t DOVCAHE       : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
       volatile uint32_t DOVCBHE       : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
@@ -882,7 +882,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t DPUSR2R; /* (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */
       volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */
       uint16_t                      : 2;
@@ -898,8 +898,8 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint16_t DPUSRCR; /* (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register */
 
-    struct {
-      volatile uint16_t FIXPHY   : 1;	/* [0..0] USB Transceiver Control Fix */
+    struct TU_ATTR_PACKED {
+      volatile uint16_t FIXPHY   : 1; /* [0..0] USB Transceiver Control Fix */
       volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
       uint16_t : 14;
     } DPUSRCR_b;
@@ -910,7 +910,7 @@ typedef struct TU_ATTR_PACKED {
     volatile uint32_t
       DPUSR0R_FS; /* (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin Monitor Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint32_t SRPC0         : 1; /* [0..0] USB Single End Receiver Control */
       volatile uint32_t RPUE0         : 1; /* [1..1] DP Pull-Up Resistor Control */
       uint32_t                        : 1;
@@ -931,7 +931,7 @@ typedef struct TU_ATTR_PACKED {
   union {
     volatile uint32_t DPUSR1R_FS; /* (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt Register */
 
-    struct {
+    struct TU_ATTR_PACKED {
       volatile uint32_t DPINTE0        : 1; /* [0..0] USB DP Interrupt Enable/Clear */
       volatile uint32_t DMINTE0        : 1; /* [1..1] USB DM Interrupt Enable/Clear */
       uint32_t                         : 2;

From cdae66c8371e1c73d28279462fa8598a9daae5a7 Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Mon, 5 Jun 2023 09:04:52 +0200
Subject: [PATCH 1778/2085] renesas_rx: fix compilation on latest GCC

__CCRX__ only applyes to version 4 of RX family compiler http://tool-support.renesas.com/autoupdate/support/onlinehelp/csp/V4.01.00/CS+.chm/Compiler-CCRX.chm/Output/ccrx04c0201y.html

__RX__ is one of the macros exported by latest gcc (gcc_8.3.0.202305_rx_elf)
---
 src/portable/renesas/rusb2/dcd_rusb2.c | 2 ++
 src/portable/renesas/rusb2/hcd_rusb2.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 2653d0da6..e9ac46517 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -67,6 +67,8 @@
 /* LINK core registers */
 #if defined(__CCRX__)
   #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
+#elif defined(__RX__)
+  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
 #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
   #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE)
 #else
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 1e26c931d..b97ffd7e9 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -54,6 +54,8 @@
 /* LINK core registers */
 #if defined(__CCRX__)
   #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
+#elif defined(__RX__)
+  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
 #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
   #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE)
 #else

From 2b735ee8f5476168d6b5ed1dc32edc52f4d3648a Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Mon, 5 Jun 2023 09:31:58 +0200
Subject: [PATCH 1779/2085] renesas_ra: fix wrong ifdef

Since CFG_TUSB_RHPORT1_MODE is always defined now for backwards compatibility
---
 src/portable/renesas/rusb2/rusb2_ra.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c
index 2b6ce7b2f..ff2191b1f 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.c
+++ b/src/portable/renesas/rusb2/rusb2_ra.c
@@ -1,16 +1,16 @@
 #include "tusb_option.h"
 #include "rusb2_ra.h"
 
-#ifdef CFG_TUSB_RHPORT0_MODE
+#if (CFG_TUSB_RHPORT0_MODE != 0)
 IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn;
 void tud_set_irq_usbfs(IRQn_Type q) {
   _usb_fs_irqn = q;
 }
 #endif
 
-#ifdef CFG_TUSB_RHPORT1_MODE
+#if (CFG_TUSB_RHPORT1_MODE != 0)
 IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn;
 void tud_set_irq_usbhs(IRQn_Type q) {
   _usb_hs_irqn = q;
 }
-#endif
\ No newline at end of file
+#endif

From f6a45a7aab42264fc9c270150549cd4c4a54292e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 5 Jun 2023 15:41:35 +0700
Subject: [PATCH 1780/2085] clean up

---
 .idea/runConfigurations/stm32g474_jlink.xml | 10 +++++
 hw/bsp/board.c                              | 11 ++---
 hw/bsp/family_support.cmake                 | 17 ++++---
 hw/bsp/stm32g4/family.c                     | 50 ++++++++++++---------
 src/CMakeLists.txt                          |  4 --
 5 files changed, 55 insertions(+), 37 deletions(-)
 create mode 100644 .idea/runConfigurations/stm32g474_jlink.xml

diff --git a/.idea/runConfigurations/stm32g474_jlink.xml b/.idea/runConfigurations/stm32g474_jlink.xml
new file mode 100644
index 000000000..45a755da4
--- /dev/null
+++ b/.idea/runConfigurations/stm32g474_jlink.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="stm32g474 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 100000 -port 25321 -swoport 25322 -TelnetPort 25323 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="b_g474e_dpow1" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 66ffcb199..3f62547a0 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -39,7 +39,7 @@
   #define sys_read    _read
 #endif
 
-#if defined(LOGGER_RTT)
+#if defined(LOGGER_RTT) || defined(LOGGER_rtt)
 // Logging with RTT
 
 // If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead
@@ -62,7 +62,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 
 #endif
 
-#elif defined(LOGGER_SWO)
+#elif defined(LOGGER_SWO) || defined(LOGGER_swo)
 // Logging with SWO for ARM Cortex
 
 #include "board_mcu.h"
@@ -71,11 +71,12 @@ TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
 {
   (void) fhdl;
   uint8_t const* buf8 = (uint8_t const*) buf;
-  for(size_t i=0; i<count; i++)
-  {
+
+  for(size_t i=0; i<count; i++) {
     ITM_SendChar(buf8[i]);
   }
-  return count;
+
+  return (int) count;
 }
 
 TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index fdcd9a983..2c0ee95d6 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -115,6 +115,12 @@ function(family_configure_common TARGET)
       "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map"
       )
   endif()
+
+  # LOGGER
+  if (DEFINED LOGGER)
+    target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER})
+  endif ()
+
 endfunction()
 
 
@@ -136,12 +142,11 @@ function(family_add_tinyusb TARGET OPT_MCU)
   set(TINYUSB_TARGET_PREFIX ${TARGET}-)
   add_library(${TARGET}-tinyusb_config INTERFACE)
 
-  target_include_directories(${TARGET}-tinyusb_config INTERFACE
-    ${CMAKE_CURRENT_SOURCE_DIR}/src
-    )
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_MCU=${OPT_MCU}
-    )
+  target_include_directories(${TARGET}-tinyusb_config INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/src)
+  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_MCU=${OPT_MCU})
+  if (DEFINED LOG)
+    target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG})
+  endif()
 
   # tinyusb's CMakeList.txt
   add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index 3b490e9b3..19ba415bc 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -79,32 +79,35 @@ void board_init(void)
   NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef gpio_init;
 
   // LED
-  GPIO_InitStruct.Pin = LED_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
+  memset(&gpio_init, 0, sizeof(gpio_init));
+  gpio_init.Pin = LED_PIN;
+  gpio_init.Mode = GPIO_MODE_OUTPUT_PP;
+  gpio_init.Pull = GPIO_PULLUP;
+  gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &gpio_init);
 
   board_led_write(false);
 
   // Button
-  GPIO_InitStruct.Pin = BUTTON_PIN;
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
+  memset(&gpio_init, 0, sizeof(gpio_init));
+  gpio_init.Pin = BUTTON_PIN;
+  gpio_init.Mode = GPIO_MODE_INPUT;
+  gpio_init.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
+  gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &gpio_init);
 
 #ifdef UART_DEV
   // UART
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
-  GPIO_InitStruct.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
+  memset(&gpio_init, 0, sizeof(gpio_init));
+  gpio_init.Pin       = UART_TX_PIN | UART_RX_PIN;
+  gpio_init.Mode      = GPIO_MODE_AF_PP;
+  gpio_init.Pull      = GPIO_PULLUP;
+  gpio_init.Speed     = GPIO_SPEED_FREQ_HIGH;
+  gpio_init.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &gpio_init);
 
   UartHandle = (UART_HandleTypeDef){
     .Instance        = UART_DEV,
@@ -121,15 +124,18 @@ void board_init(void)
 
   // USB Pins TODO double check USB clock and pin setup
   // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
-  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+  memset(&gpio_init, 0, sizeof(gpio_init));
+  gpio_init.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  gpio_init.Mode = GPIO_MODE_INPUT;
+  gpio_init.Pull = GPIO_NOPULL;
+  gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &gpio_init);
 
   __HAL_RCC_USB_CLK_ENABLE();
 
   board_vbus_sense_init();
+
+  // USB PD
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 09f41c9ab..3dbd72d61 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -98,7 +98,3 @@ endif()
 target_link_libraries(${TINYUSB_TARGET} PUBLIC
   ${TINYUSB_CONFIG_TARGET}
   )
-
-# export target name
-# set(TINYUSB_TARGET ${TINYUSB_TARGET} PARENT_SCOPE)
-# set(TINYUSB_CONFIG_TARGET ${TINYUSB_CONFIG_TARGET} PARENT_SCOPE)

From a70978e05790cf744e777fd3e50f271fc3fffd1f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 5 Jun 2023 19:53:40 +0700
Subject: [PATCH 1781/2085] clean up

---
 hw/bsp/board.c                              | 4 ++--
 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h | 2 ++
 hw/bsp/stm32g4/family.c                     | 1 +
 hw/bsp/stm32g4/family.cmake                 | 2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 3f62547a0..7804a18e0 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -39,7 +39,7 @@
   #define sys_read    _read
 #endif
 
-#if defined(LOGGER_RTT) || defined(LOGGER_rtt)
+#if defined(LOGGER_RTT)
 // Logging with RTT
 
 // If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead
@@ -62,7 +62,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 
 #endif
 
-#elif defined(LOGGER_SWO) || defined(LOGGER_swo)
+#elif defined(LOGGER_SWO)
 // Logging with SWO for ARM Cortex
 
 #include "board_mcu.h"
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
index 5d936d009..21d4e459b 100644
--- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
@@ -57,6 +57,8 @@
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
+
+// CPU Frequency (Core Clock) is 170MHz
 static inline void board_clock_init(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index 19ba415bc..030abe0d0 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -136,6 +136,7 @@ void board_init(void)
   board_vbus_sense_init();
 
   // USB PD
+
 }
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index ab17c0980..2c10a9769 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -109,7 +109,7 @@ function(family_configure_example TARGET)
 
   # Flashing
   family_flash_stlink(${TARGET})
-  #family_flash_jlink(${TARGET})
+  family_flash_jlink(${TARGET})
 endfunction()
 
 

From b3fda4a35433a4102743ea9719e2323e4076ff34 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 6 Jun 2023 23:55:33 +0700
Subject: [PATCH 1782/2085] able to get usbpd irq handler

- handle cc1, cc2 voltage changes
- get order set, rx message end interrupt
- add  segger rtt support for cmake
---
 hw/bsp/family_support.cmake                 |  15 ++
 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h |  22 +--
 hw/bsp/stm32g4/family.c                     | 183 +++++++++++++++++---
 src/common/tusb_types.h                     |  13 ++
 4 files changed, 196 insertions(+), 37 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 2c0ee95d6..e9b4f2fdb 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -97,6 +97,18 @@ function(family_initialize_project PROJECT DIR)
 endfunction()
 
 
+# Add segger rtt to example
+function(family_add_segger_rtt TARGET)
+  if (NOT TARGET segger_rtt)
+    add_library(segger_rtt STATIC
+      ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+      )
+    target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
+  endif()
+
+  target_link_libraries(${TARGET} PUBLIC segger_rtt)
+endfunction()
+
 #------------------------------------
 # Main target configure
 #------------------------------------
@@ -119,6 +131,9 @@ function(family_configure_common TARGET)
   # LOGGER
   if (DEFINED LOGGER)
     target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER})
+    if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
+      family_add_segger_rtt(${TARGET})
+    endif ()
   endif ()
 
 endfunction()
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
index 21d4e459b..b1a98ba97 100644
--- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
@@ -58,7 +58,7 @@
 // RCC Clock
 //--------------------------------------------------------------------+
 
-// CPU Frequency (Core Clock) is 170MHz
+// CPU Frequency (Core Clock) is 150MHz
 static inline void board_clock_init(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
@@ -68,16 +68,16 @@ static inline void board_clock_init(void)
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
 
   /* Activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLM            = RCC_PLLM_DIV4;
-  RCC_OscInitStruct.PLL.PLLN            = 85;
-  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV10;
-  RCC_OscInitStruct.PLL.PLLQ            = RCC_PLLQ_DIV2;
-  RCC_OscInitStruct.PLL.PLLR            = RCC_PLLR_DIV2;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 75;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
   // Initializes the CPU, AHB and APB buses clocks
@@ -87,7 +87,7 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
 
   //------------- HSI48 and CRS for USB -------------//
   RCC_OscInitTypeDef osc_hsi48 = {0};
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index 030abe0d0..8b17c0643 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -25,9 +25,127 @@
  */
 
 #include "stm32g4xx_hal.h"
+#include "stm32g4xx_ll_bus.h"
+
 #include "bsp/board.h"
 #include "board.h"
 
+
+//--------------------------------------------------------------------+
+// USB PD
+//--------------------------------------------------------------------+
+
+void usbpd_init(uint8_t port_num, tusb_typec_port_type_t port_type) {
+  (void) port_num;
+
+  // Initialization phase: CFG1
+  UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
+      (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) |
+      ( 0 << UCPD_CFG1_TXDMAEN_Pos) | (0 << UCPD_CFG1_RXDMAEN_Pos);
+  UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
+
+  // General programming sequence (with UCPD configured then enabled)
+  if (port_type == TUSB_TYPEC_PORT_SNK) {
+    // Enable both CC Phy
+    UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos);
+
+    // Read Voltage State on CC1 & CC2 fore initial state
+    uint32_t vstate_cc[2];
+    vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
+    vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
+
+    TU_LOG1_INT(vstate_cc[0]);
+    TU_LOG1_INT(vstate_cc[1]);
+
+    // Enable CC1 & CC2 Interrupt
+    UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE;
+  }
+
+  // Enable interrupt
+  //NVIC_SetPriority(UCPD1_IRQn, 0);
+//  NVIC_EnableIRQ(UCPD1_IRQn);
+}
+
+uint8_t pd_rx_buf[262];
+uint32_t pd_rx_count = 0;
+
+void UCPD1_IRQHandler(void) {
+  uint32_t sr = UCPD1->SR;
+  sr &= UCPD1->IMR;
+
+  TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr);
+
+  if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) {
+    uint32_t vstate_cc[2];
+    vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
+    vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
+
+    TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
+
+    uint32_t cr = UCPD1->CR;
+
+    if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) {
+      TU_LOG1("Attach CC1\n");
+      cr &= ~UCPD_CR_PHYCCSEL;
+      cr |= UCPD_CR_PHYRXEN;
+    } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) {
+      TU_LOG1("Attach CC2\n");
+      cr |= UCPD_CR_PHYCCSEL;
+      cr |= UCPD_CR_PHYRXEN;
+    } else {
+      TU_LOG1("Detach\n");
+      cr &= ~UCPD_CR_PHYRXEN;
+    }
+
+    // Enable Interrupt
+    UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
+        /*UCPD_IMR_RXNEIE |*/ UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE |
+        UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
+
+    // Enable PD RX
+    UCPD1->CR = cr;
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
+  }
+
+  if (sr & UCPD_SR_RXORDDET) {
+    // SOP: Start of Packet
+    // TODO DMA later
+    uint8_t order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
+    TU_LOG1_HEX(order_set);
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_RXORDDETCF;
+  }
+
+  if ( sr & UCPD_SR_RXMSGEND) {
+    // End of message
+//    uint32_t payload_size = UCPD1->RX_PAYSZ;
+//    TU_LOG1_HEX(payload_size);
+//
+//    for(uint32_t i=0; i<payload_size; i++) {
+//      pd_rx_buf[i] = UCPD1->RXDR;
+//
+//      TU_LOG1("0x%02X ", pd_rx_buf[i]);
+//    }
+//    TU_LOG1("\n");
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
+  }
+
+//  if (sr & UCPD_SR_RXNE) {
+//    uint8_t data = UCPD1->RXDR;
+//    pd_rx_buf[pd_rx_count++] = data;
+//    TU_LOG1_HEX(data);
+//  }
+
+//  else {
+//    TU_LOG_LOCATION();
+//  }
+}
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -79,35 +197,35 @@ void board_init(void)
   NVIC_SetPriority(USBWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
-  GPIO_InitTypeDef gpio_init;
+  GPIO_InitTypeDef GPIO_InitStruct;
 
   // LED
-  memset(&gpio_init, 0, sizeof(gpio_init));
-  gpio_init.Pin = LED_PIN;
-  gpio_init.Mode = GPIO_MODE_OUTPUT_PP;
-  gpio_init.Pull = GPIO_PULLUP;
-  gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(LED_PORT, &gpio_init);
+  memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct));
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
 
   board_led_write(false);
 
   // Button
-  memset(&gpio_init, 0, sizeof(gpio_init));
-  gpio_init.Pin = BUTTON_PIN;
-  gpio_init.Mode = GPIO_MODE_INPUT;
-  gpio_init.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
-  gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(BUTTON_PORT, &gpio_init);
+  memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct));
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 
 #ifdef UART_DEV
   // UART
-  memset(&gpio_init, 0, sizeof(gpio_init));
-  gpio_init.Pin       = UART_TX_PIN | UART_RX_PIN;
-  gpio_init.Mode      = GPIO_MODE_AF_PP;
-  gpio_init.Pull      = GPIO_PULLUP;
-  gpio_init.Speed     = GPIO_SPEED_FREQ_HIGH;
-  gpio_init.Alternate = UART_GPIO_AF;
-  HAL_GPIO_Init(UART_GPIO_PORT, &gpio_init);
+  memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct));
+  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull      = GPIO_PULLUP;
+  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Alternate = UART_GPIO_AF;
+  HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
 
   UartHandle = (UART_HandleTypeDef){
     .Instance        = UART_DEV,
@@ -124,18 +242,31 @@ void board_init(void)
 
   // USB Pins TODO double check USB clock and pin setup
   // Configure USB DM and DP pins. This is optional, and maintained only for user guidance.
-  memset(&gpio_init, 0, sizeof(gpio_init));
-  gpio_init.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
-  gpio_init.Mode = GPIO_MODE_INPUT;
-  gpio_init.Pull = GPIO_NOPULL;
-  gpio_init.Speed = GPIO_SPEED_FREQ_HIGH;
-  HAL_GPIO_Init(GPIOA, &gpio_init);
+  memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct));
+  GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12);
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
   __HAL_RCC_USB_CLK_ENABLE();
 
   board_vbus_sense_init();
 
+#if 0
   // USB PD
+  /* PWR register access (for disabling dead battery feature) */
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC);
+
+  __HAL_RCC_UCPD1_CLK_ENABLE();
+
+  // Default CC1/CC2 is PB4/PB6
+  // PB4   ------> UCPD1_CC2
+  // PB6   ------> UCPD1_CC1
+
+  usbpd_init(0, TUSB_TYPEC_PORT_SNK);
+#endif
 
 }
 
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 39a2d4564..7b82c51d9 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -232,6 +232,19 @@ enum {
 
 #define TUSB_DESC_CONFIG_POWER_MA(x)  ((x)/2)
 
+//--------------------------------------------------------------------+
+// TYPE-C
+//--------------------------------------------------------------------+
+
+typedef enum {
+  TUSB_TYPEC_PORT_SRC,
+  TUSB_TYPEC_PORT_SNK,
+  TUSB_TYPEC_PORT_DRP
+} tusb_typec_port_type_t;
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
 typedef enum
 {
   XFER_RESULT_SUCCESS = 0,

From 23f7130ae47b6cbb11e1fffcb3d5e75a5417ef78 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 7 Jun 2023 00:07:58 +0700
Subject: [PATCH 1783/2085] update rtt to rev 25842

---
 .../{RTT => Config}/SEGGER_RTT_Conf.h         | 140 +++--
 lib/SEGGER_RTT/LICENSE.md                     |  36 ++
 lib/SEGGER_RTT/License.txt                    |  34 --
 lib/SEGGER_RTT/README.md                      |  24 +
 lib/SEGGER_RTT/README.txt                     |  20 -
 lib/SEGGER_RTT/RTT/SEGGER_RTT.c               | 427 +++++++++------
 lib/SEGGER_RTT/RTT/SEGGER_RTT.h               | 231 ++++++--
 lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S    |   7 +
 lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c        | 500 ------------------
 .../Syscalls/SEGGER_RTT_Syscalls_GCC.c        | 120 -----
 .../Syscalls/SEGGER_RTT_Syscalls_IAR.c        | 115 ----
 .../Syscalls/SEGGER_RTT_Syscalls_KEIL.c       | 386 --------------
 .../Syscalls/SEGGER_RTT_Syscalls_SES.c        | 247 ---------
 13 files changed, 617 insertions(+), 1670 deletions(-)
 rename lib/SEGGER_RTT/{RTT => Config}/SEGGER_RTT_Conf.h (69%)
 create mode 100644 lib/SEGGER_RTT/LICENSE.md
 delete mode 100644 lib/SEGGER_RTT/License.txt
 create mode 100644 lib/SEGGER_RTT/README.md
 delete mode 100644 lib/SEGGER_RTT/README.txt
 delete mode 100644 lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c
 delete mode 100644 lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c
 delete mode 100644 lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c
 delete mode 100644 lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c
 delete mode 100644 lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c

diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h b/lib/SEGGER_RTT/Config/SEGGER_RTT_Conf.h
similarity index 69%
rename from lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h
rename to lib/SEGGER_RTT/Config/SEGGER_RTT_Conf.h
index fda5a5f51..3ac38dcf1 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT_Conf.h
+++ b/lib/SEGGER_RTT/Config/SEGGER_RTT_Conf.h
@@ -3,7 +3,7 @@
 *                        The Embedded Experts                        *
 **********************************************************************
 *                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
+*            (c) 1995 - 2020 SEGGER Microcontroller GmbH             *
 *                                                                    *
 *       www.segger.com     Support: support@segger.com               *
 *                                                                    *
@@ -46,7 +46,7 @@ File    : SEGGER_RTT_Conf.h
 Purpose : Implementation of SEGGER real-time transfer (RTT) which
           allows real-time communication on targets which support
           debugger memory accesses while the CPU is running.
-Revision: $Rev: 18601 $
+Revision: $Rev: 24316 $
 
 */
 
@@ -63,10 +63,25 @@ Revision: $Rev: 18601 $
 *
 **********************************************************************
 */
+
+//
+// Take in and set to correct values for Cortex-A systems with CPU cache
+//
+//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE            (32)          // Largest cache line size (in bytes) in the current system
+//#define SEGGER_RTT_UNCACHED_OFF                   (0xFB000000)  // Address alias where RTT CB and buffers can be accessed uncached
+//
+// Most common case:
+// Up-channel 0: RTT
+// Up-channel 1: SystemView
+//
 #ifndef   SEGGER_RTT_MAX_NUM_UP_BUFFERS
   #define SEGGER_RTT_MAX_NUM_UP_BUFFERS             (3)     // Max. number of up-buffers (T->H) available on this target    (Default: 3)
 #endif
-
+//
+// Most common case:
+// Down-channel 0: RTT
+// Down-channel 1: SystemView
+//
 #ifndef   SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
   #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS           (3)     // Max. number of down-buffers (H->T) available on this target  (Default: 3)
 #endif
@@ -135,18 +150,18 @@ Revision: $Rev: 18601 $
 #if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32))
   #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                    unsigned int LockState;                                         \
+                                    unsigned int _SEGGER_RTT__LockState;                                         \
                                   __asm volatile ("mrs   %0, primask  \n\t"                         \
-                                                  "movs  r1, $1       \n\t"                         \
+                                                  "movs  r1, #1       \n\t"                         \
                                                   "msr   primask, r1  \n\t"                         \
-                                                  : "=r" (LockState)                                \
+                                                  : "=r" (_SEGGER_RTT__LockState)                                \
                                                   :                                                 \
-                                                  : "r1"                                            \
+                                                  : "r1", "cc"                                      \
                                                   );
 
     #define SEGGER_RTT_UNLOCK()   __asm volatile ("msr   primask, %0  \n\t"                         \
                                                   :                                                 \
-                                                  : "r" (LockState)                                 \
+                                                  : "r" (_SEGGER_RTT__LockState)                                 \
                                                   :                                                 \
                                                   );                                                \
                                 }
@@ -155,32 +170,32 @@ Revision: $Rev: 18601 $
       #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
     #endif
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                    unsigned int LockState;                                         \
+                                    unsigned int _SEGGER_RTT__LockState;                                         \
                                   __asm volatile ("mrs   %0, basepri  \n\t"                         \
                                                   "mov   r1, %1       \n\t"                         \
                                                   "msr   basepri, r1  \n\t"                         \
-                                                  : "=r" (LockState)                                \
+                                                  : "=r" (_SEGGER_RTT__LockState)                                \
                                                   : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY)          \
-                                                  : "r1"                                            \
+                                                  : "r1", "cc"                                      \
                                                   );
 
     #define SEGGER_RTT_UNLOCK()   __asm volatile ("msr   basepri, %0  \n\t"                         \
                                                   :                                                 \
-                                                  : "r" (LockState)                                 \
+                                                  : "r" (_SEGGER_RTT__LockState)                                 \
                                                   :                                                 \
                                                   );                                                \
                                 }
 
-  #elif defined(__ARM_ARCH_7A__)
+  #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__))
     #define SEGGER_RTT_LOCK() {                                                \
-                                 unsigned int LockState;                       \
+                                 unsigned int _SEGGER_RTT__LockState;                       \
                                  __asm volatile ("mrs r1, CPSR \n\t"           \
                                                  "mov %0, r1 \n\t"             \
                                                  "orr r1, r1, #0xC0 \n\t"      \
                                                  "msr CPSR_c, r1 \n\t"         \
-                                                 : "=r" (LockState)            \
+                                                 : "=r" (_SEGGER_RTT__LockState)            \
                                                  :                             \
-                                                 : "r1"                        \
+                                                 : "r1", "cc"                  \
                                                  );
 
     #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t"              \
@@ -190,17 +205,17 @@ Revision: $Rev: 18601 $
                                                 "orr r1, r1, r0 \n\t"          \
                                                 "msr CPSR_c, r1 \n\t"          \
                                                 :                              \
-                                                : "r" (LockState)              \
-                                                : "r0", "r1"                   \
+                                                : "r" (_SEGGER_RTT__LockState)              \
+                                                : "r0", "r1", "cc"             \
                                                 );                             \
                             }
   #elif defined(__riscv) || defined(__riscv_xlen)
     #define SEGGER_RTT_LOCK()  {                                               \
-                                 unsigned int LockState;                       \
+                                 unsigned int _SEGGER_RTT__LockState;                       \
                                  __asm volatile ("csrr  %0, mstatus  \n\t"     \
                                                  "csrci mstatus, 8   \n\t"     \
                                                  "andi  %0, %0,  8   \n\t"     \
-                                                 : "=r" (LockState)            \
+                                                 : "=r" (_SEGGER_RTT__LockState)            \
                                                  :                             \
                                                  :                             \
                                                 );
@@ -209,7 +224,7 @@ Revision: $Rev: 18601 $
                                                  "or    %0, %0, a1   \n\t"     \
                                                  "csrs  mstatus, %0  \n\t"     \
                                                  :                             \
-                                                 : "r"  (LockState)            \
+                                                 : "r"  (_SEGGER_RTT__LockState)            \
                                                  : "a1"                        \
                                                 );                             \
                                }
@@ -227,11 +242,11 @@ Revision: $Rev: 18601 $
   #if (defined (__ARM6M__)          && (__CORE__ == __ARM6M__))             ||                      \
       (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__))
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  LockState = __get_PRIMASK();                                      \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_PRIMASK();                                      \
                                   __set_PRIMASK(1);
 
-    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(LockState);                                         \
+    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(_SEGGER_RTT__LockState);                                         \
                                 }
   #elif (defined (__ARM7EM__)         && (__CORE__ == __ARM7EM__))          ||                      \
         (defined (__ARM7M__)          && (__CORE__ == __ARM7M__))           ||                      \
@@ -241,12 +256,36 @@ Revision: $Rev: 18601 $
       #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
     #endif
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  LockState = __get_BASEPRI();                                      \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_BASEPRI();                                      \
                                   __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
 
-    #define SEGGER_RTT_UNLOCK()   __set_BASEPRI(LockState);                                         \
+    #define SEGGER_RTT_UNLOCK()   __set_BASEPRI(_SEGGER_RTT__LockState);                                         \
                                 }
+  #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__))                    ||                      \
+        (defined (__ARM7R__) && (__CORE__ == __ARM7R__))
+    #define SEGGER_RTT_LOCK() {                                                                     \
+                                 unsigned int _SEGGER_RTT__LockState;                                            \
+                                 __asm volatile ("mrs r1, CPSR \n\t"                                \
+                                                 "mov %0, r1 \n\t"                                  \
+                                                 "orr r1, r1, #0xC0 \n\t"                           \
+                                                 "msr CPSR_c, r1 \n\t"                              \
+                                                 : "=r" (_SEGGER_RTT__LockState)                                 \
+                                                 :                                                  \
+                                                 : "r1", "cc"                                       \
+                                                 );
+
+    #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t"                                   \
+                                                "mrs r1, CPSR \n\t"                                 \
+                                                "bic r1, r1, #0xC0 \n\t"                            \
+                                                "and r0, r0, #0xC0 \n\t"                            \
+                                                "orr r1, r1, r0 \n\t"                               \
+                                                "msr CPSR_c, r1 \n\t"                               \
+                                                :                                                   \
+                                                : "r" (_SEGGER_RTT__LockState)                                   \
+                                                : "r0", "r1", "cc"                                  \
+                                                );                                                  \
+                            }
   #endif
 #endif
 
@@ -256,11 +295,11 @@ Revision: $Rev: 18601 $
 */
 #ifdef __ICCRX__
   #define SEGGER_RTT_LOCK()   {                                                                     \
-                                unsigned long LockState;                                            \
-                                LockState = __get_interrupt_state();                                \
+                                unsigned long _SEGGER_RTT__LockState;                                            \
+                                _SEGGER_RTT__LockState = __get_interrupt_state();                                \
                                 __disable_interrupt();
 
-  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(LockState);                                   \
+  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(_SEGGER_RTT__LockState);                                   \
                               }
 #endif
 
@@ -270,11 +309,11 @@ Revision: $Rev: 18601 $
 */
 #ifdef __ICCRL78__
   #define SEGGER_RTT_LOCK()   {                                                                     \
-                                __istate_t LockState;                                               \
-                                LockState = __get_interrupt_state();                                \
+                                __istate_t _SEGGER_RTT__LockState;                                               \
+                                _SEGGER_RTT__LockState = __get_interrupt_state();                                \
                                 __disable_interrupt();
 
-  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(LockState);                                   \
+  #define SEGGER_RTT_UNLOCK()   __set_interrupt_state(_SEGGER_RTT__LockState);                                   \
                               }
 #endif
 
@@ -285,13 +324,13 @@ Revision: $Rev: 18601 $
 #ifdef __CC_ARM
   #if (defined __TARGET_ARCH_6S_M)
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  register unsigned char PRIMASK __asm( "primask");                 \
-                                  LockState = PRIMASK;                                              \
-                                  PRIMASK = 1u;                                                     \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask");                 \
+                                  _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK;                                              \
+                                  _SEGGER_RTT__PRIMASK = 1u;                                                     \
                                   __schedule_barrier();
 
-    #define SEGGER_RTT_UNLOCK()   PRIMASK = LockState;                                              \
+    #define SEGGER_RTT_UNLOCK()   _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState;                                              \
                                   __schedule_barrier();                                             \
                                 }
   #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
@@ -299,13 +338,13 @@ Revision: $Rev: 18601 $
       #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
     #endif
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
                                   register unsigned char BASEPRI __asm( "basepri");                 \
-                                  LockState = BASEPRI;                                              \
+                                  _SEGGER_RTT__LockState = BASEPRI;                                              \
                                   BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY;                      \
                                   __schedule_barrier();
 
-    #define SEGGER_RTT_UNLOCK()   BASEPRI = LockState;                                              \
+    #define SEGGER_RTT_UNLOCK()   BASEPRI = _SEGGER_RTT__LockState;                                              \
                                   __schedule_barrier();                                             \
                                 }
   #endif
@@ -318,21 +357,21 @@ Revision: $Rev: 18601 $
 #ifdef __TI_ARM__
   #if defined (__TI_ARM_V6M0__)
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  LockState = __get_PRIMASK();                                      \
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = __get_PRIMASK();                                      \
                                   __set_PRIMASK(1);
 
-    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(LockState);                                         \
+    #define SEGGER_RTT_UNLOCK()   __set_PRIMASK(_SEGGER_RTT__LockState);                                         \
                                 }
   #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__))
     #ifndef   SEGGER_RTT_MAX_INTERRUPT_PRIORITY
       #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY   (0x20)
     #endif
     #define SEGGER_RTT_LOCK()   {                                                                   \
-                                  unsigned int LockState;                                           \
-                                  LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
+                                  unsigned int _SEGGER_RTT__LockState;                                           \
+                                  _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
 
-    #define SEGGER_RTT_UNLOCK()   _set_interrupt_priority(LockState);                               \
+    #define SEGGER_RTT_UNLOCK()   _set_interrupt_priority(_SEGGER_RTT__LockState);                               \
                                 }
   #endif
 #endif
@@ -342,12 +381,13 @@ Revision: $Rev: 18601 $
 *       RTT lock configuration for CCRX
 */
 #ifdef __RX
+  #include <machine.h>
   #define SEGGER_RTT_LOCK()   {                                                                     \
-                                unsigned long LockState;                                            \
-                                LockState = get_psw() & 0x010000;                                   \
+                                unsigned long _SEGGER_RTT__LockState;                                            \
+                                _SEGGER_RTT__LockState = get_psw() & 0x010000;                                   \
                                 clrpsw_i();
 
-  #define SEGGER_RTT_UNLOCK()   set_psw(get_psw() | LockState);                                     \
+  #define SEGGER_RTT_UNLOCK()   set_psw(get_psw() | _SEGGER_RTT__LockState);                                     \
                               }
 #endif
 
diff --git a/lib/SEGGER_RTT/LICENSE.md b/lib/SEGGER_RTT/LICENSE.md
new file mode 100644
index 000000000..14881c29b
--- /dev/null
+++ b/lib/SEGGER_RTT/LICENSE.md
@@ -0,0 +1,36 @@
+
+                    SEGGER Microcontroller GmbH
+                       The Embedded Experts
+
+           (c) 1995 - 2021 SEGGER Microcontroller GmbH
+          www.segger.com     Support: support@segger.com
+
+        SEGGER RTT  Real Time Transfer for embedded targets
+
+
+    All rights reserved.
+
+    SEGGER strongly recommends to not make any changes
+    to or modify the source code of this software in order to stay
+    compatible with the RTT protocol and J-Link.
+
+    Redistribution and use in source and binary forms, with or
+    without modification, are permitted provided that the following
+    condition is met:
+
+    - Redistributions of source code must retain the above copyright
+     notice, this condition and the following disclaimer.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+    CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+    INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR
+    ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+    OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+    OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+    LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+    USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+    DAMAGE.
diff --git a/lib/SEGGER_RTT/License.txt b/lib/SEGGER_RTT/License.txt
deleted file mode 100644
index e1f5f89ff..000000000
--- a/lib/SEGGER_RTT/License.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Important - Read carefully:
-
-SEGGER RTT - Real Time Transfer for embedded targets
-
-All rights reserved.
-
-SEGGER strongly recommends to not make any changes
-to or modify the source code of this software in order to stay
-compatible with the RTT protocol and J-Link.
-
-Redistribution and use in source and binary forms, with or
-without modification, are permitted provided that the following
-condition is met:
-
-o Redistributions of source code must retain the above copyright
-  notice, this condition and the following disclaimer.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
-CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
-DAMAGE.
-
-
-(c) 2014 - 2016  SEGGER Microcontroller GmbH
-www.segger.com
diff --git a/lib/SEGGER_RTT/README.md b/lib/SEGGER_RTT/README.md
new file mode 100644
index 000000000..06349d248
--- /dev/null
+++ b/lib/SEGGER_RTT/README.md
@@ -0,0 +1,24 @@
+RTT
+===
+
+SEGGER RTT Sources
+
+https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer
+https://wiki.segger.com/RTT
+
+## Included files
+
+  * `RTT/`
+    * `SEGGER_RTT.c`               - Main module for RTT.
+    * `SEGGER_RTT.h`               - Main header for RTT.
+    * `SEGGER_RTT_ASM_ARMv7M.S`    - Assembly-optimized implementation of RTT functions for ARMv7M processors.
+    * `SEGGER_RTT_Printf.c`        - Simple implementation of printf (`SEGGER_RTT_Printf()`) to write formatted strings via RTT.
+  * `Syscalls/`
+    * `SEGGER_RTT_Syscalls_*.c`    - Low-level syscalls to retarget `printf()` to RTT with different toolchains.
+  * `Config/`
+    * `SEGGER_RTT_Conf.h`          - RTT configuration file.
+  * `Examples/`
+    * `Main_RTT_InputEchoApp.c`    - Example application which echoes input on Channel 0.
+    * `Main_RTT_MenuApp.c`         - Example application to demonstrate RTT bi-directional functionality.
+    * `Main_RTT_PrintfTest.c`      - Example application to test RTT's simple printf implementation.
+    * `Main_RTT_SpeedTestApp.c`    - Example application to measure RTT performance. (Requires embOS)
diff --git a/lib/SEGGER_RTT/README.txt b/lib/SEGGER_RTT/README.txt
deleted file mode 100644
index 49ec655c4..000000000
--- a/lib/SEGGER_RTT/README.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-README.txt for the SEGGER RTT Implementation Pack.
-
-Included files:
-===============
-Root Directory
-  - Examples
-    - Main_RTT_InputEchoApp.c    - Sample application which echoes input on Channel 0.
-    - Main_RTT_MenuApp.c         - Sample application to demonstrate RTT bi-directional functionality.
-    - Main_RTT_PrintfTest.c      - Sample application to test RTT small printf implementation.
-    - Main_RTT_SpeedTestApp.c    - Sample application for measuring RTT performance. embOS needed.
-  - RTT
-    - SEGGER_RTT.c                - The RTT implementation.
-    - SEGGER_RTT.h                - Header for RTT implementation.
-    - SEGGER_RTT_Conf.h           - Pre-processor configuration for the RTT implementation.
-    - SEGGER_RTT_Printf.c         - Simple implementation of printf to write formatted strings via RTT.
-  - Syscalls
-    - RTT_Syscalls_GCC.c          - Low-level syscalls to retarget printf() to RTT with GCC / Newlib.
-    - RTT_Syscalls_IAR.c          - Low-level syscalls to retarget printf() to RTT with IAR compiler.
-    - RTT_Syscalls_KEIL.c         - Low-level syscalls to retarget printf() to RTT with KEIL/uVision compiler.
-    - RTT_Syscalls_SES.c          - Low-level syscalls to retarget printf() to RTT with SEGGER Embedded Studio.
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
index c8de8e0f3..895085ba2 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
@@ -46,7 +46,7 @@ File    : SEGGER_RTT.c
 Purpose : Implementation of SEGGER real-time transfer (RTT) which
           allows real-time communication on targets which support
           debugger memory accesses while the CPU is running.
-Revision: $Rev: 17697 $
+Revision: $Rev: 29668 $
 
 Additional information:
           Type "int" is assumed to be 32-bits in size
@@ -80,6 +80,27 @@ Additional information:
 **********************************************************************
 */
 
+#if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+  #ifdef SEGGER_RTT_CB_ALIGN
+    #error "Custom SEGGER_RTT_CB_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_BUFFER_ALIGN
+    #error "Custom SEGGER_RTT_BUFFER_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_PUT_CB_SECTION
+    #error "Custom SEGGER_RTT_PUT_CB_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_PUT_BUFFER_SECTION
+    #error "Custom SEGGER_RTT_PUT_BUFFER_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_BUFFER_ALIGNMENT
+    #error "Custom SEGGER_RTT_BUFFER_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+  #ifdef SEGGER_RTT_ALIGNMENT
+    #error "Custom SEGGER_RTT_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+#endif
+
 #ifndef   BUFFER_SIZE_UP
   #define BUFFER_SIZE_UP                                  1024  // Size of the buffer for terminal output of target, up to host
 #endif
@@ -103,11 +124,11 @@ Additional information:
 #endif
 
 #ifndef   SEGGER_RTT_ALIGNMENT
-  #define SEGGER_RTT_ALIGNMENT                            0
+  #define SEGGER_RTT_ALIGNMENT                            SEGGER_RTT_CPU_CACHE_LINE_SIZE
 #endif
 
 #ifndef   SEGGER_RTT_BUFFER_ALIGNMENT
-  #define SEGGER_RTT_BUFFER_ALIGNMENT                     0
+  #define SEGGER_RTT_BUFFER_ALIGNMENT                     SEGGER_RTT_CPU_CACHE_LINE_SIZE
 #endif
 
 #ifndef   SEGGER_RTT_MODE_DEFAULT
@@ -127,7 +148,7 @@ Additional information:
 #endif
 
 #ifndef   STRCPY
-  #define STRCPY(pDest, pSrc, NumBytes)                   strcpy((pDest), (pSrc))
+  #define STRCPY(pDest, pSrc)                             strcpy((pDest), (pSrc))
 #endif
 
 #ifndef   SEGGER_RTT_MEMCPY_USE_BYTELOOP
@@ -143,17 +164,17 @@ Additional information:
 #endif
 
 #ifndef   MIN
-  #define MIN(a, b)         (((a) < (b)) ? (a) : (b))
+  #define MIN(a, b)                                       (((a) < (b)) ? (a) : (b))
 #endif
 
 #ifndef   MAX
-  #define MAX(a, b)         (((a) > (b)) ? (a) : (b))
+  #define MAX(a, b)                                       (((a) > (b)) ? (a) : (b))
 #endif
 //
 // For some environments, NULL may not be defined until certain headers are included
 //
 #ifndef NULL
-  #define NULL 0
+  #define NULL                                            0
 #endif
 
 /*********************************************************************
@@ -167,7 +188,7 @@ Additional information:
 #endif
 
 #if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT
-  #if (defined __GNUC__)
+  #if ((defined __GNUC__) || (defined __clang__))
     #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment)))
   #elif (defined __ICCARM__) || (defined __ICCRX__)
     #define PRAGMA(A) _Pragma(#A)
@@ -183,7 +204,7 @@ Additional information:
 #endif
 
 #if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION)
-  #if (defined __GNUC__)
+  #if ((defined __GNUC__) || (defined __clang__))
     #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var
   #elif (defined __ICCARM__) || (defined __ICCRX__)
 #define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \
@@ -197,7 +218,6 @@ Additional information:
   #define SEGGER_RTT_PUT_SECTION(Var, Section) Var
 #endif
 
-
 #if SEGGER_RTT_ALIGNMENT
   #define SEGGER_RTT_CB_ALIGN(Var)  SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT)
 #else
@@ -230,7 +250,7 @@ Additional information:
 **********************************************************************
 */
 
-static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
+static const unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
 
 /*********************************************************************
 *
@@ -238,13 +258,30 @@ static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7'
 *
 **********************************************************************
 */
+
 //
 // RTT Control Block and allocate buffers for channel 0
 //
-SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT));
-
-SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer  [BUFFER_SIZE_UP]));
-SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN]));
+#if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+  #if ((defined __GNUC__) || (defined __clang__))
+    SEGGER_RTT_CB _SEGGER_RTT                                                             __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE)));
+    static char   _acUpBuffer  [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)]   __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE)));
+    static char   _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)] __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE)));
+  #elif (defined __ICCARM__)
+    #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    SEGGER_RTT_CB _SEGGER_RTT;
+    #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    static char   _acUpBuffer  [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)];
+    #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    static char   _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)];
+  #else
+    #error "Don't know how to place _SEGGER_RTT, _acUpBuffer, _acDownBuffer cache-line aligned"
+  #endif
+#else
+  SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT));
+  SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer  [BUFFER_SIZE_UP]));
+  SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN]));
+#endif
 
 static unsigned char _ActiveTerminal;
 
@@ -261,18 +298,29 @@ static unsigned char _ActiveTerminal;
 *
 *  Function description
 *    Initializes the control block an buffers.
-*    May only be called via INIT() to avoid overriding settings.
 *
+*  Notes
+*    (1) May only be called via INIT() to avoid overriding settings.
+*        The only exception is SEGGER_RTT_Init(), to make an intentional override possible.
 */
-#define INIT()  do {                                            \
-                  if (_SEGGER_RTT.acID[0] == '\0') { _DoInit(); }  \
-                } while (0)
+  #define INIT()                                                                             \
+    do {                                                                                     \
+      volatile SEGGER_RTT_CB* pRTTCBInit;                                                    \
+      pRTTCBInit = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \
+      if (pRTTCBInit->acID[0] != 'S') {                                                      \
+        _DoInit();                                                                           \
+      }                                                                                      \
+    } while (0)
+
 static void _DoInit(void) {
-  SEGGER_RTT_CB* p;
+  volatile SEGGER_RTT_CB* p;   // Volatile to make sure that compiler cannot change the order of accesses to the control block
+  static const char _aInitStr[] = "\0\0\0\0\0\0TTR REGGES";  // Init complete ID string to make sure that things also work if RTT is linked to a no-init memory area
+  unsigned i;
   //
   // Initialize control block
   //
-  p = &_SEGGER_RTT;
+  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
+  memset((SEGGER_RTT_CB*)p, 0, sizeof(_SEGGER_RTT));         // Make sure that the RTT CB is always zero initialized.
   p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
   p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
   //
@@ -280,7 +328,7 @@ static void _DoInit(void) {
   //
   p->aUp[0].sName         = "Terminal";
   p->aUp[0].pBuffer       = _acUpBuffer;
-  p->aUp[0].SizeOfBuffer  = sizeof(_acUpBuffer);
+  p->aUp[0].SizeOfBuffer  = BUFFER_SIZE_UP;
   p->aUp[0].RdOff         = 0u;
   p->aUp[0].WrOff         = 0u;
   p->aUp[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
@@ -289,18 +337,20 @@ static void _DoInit(void) {
   //
   p->aDown[0].sName         = "Terminal";
   p->aDown[0].pBuffer       = _acDownBuffer;
-  p->aDown[0].SizeOfBuffer  = sizeof(_acDownBuffer);
+  p->aDown[0].SizeOfBuffer  = BUFFER_SIZE_DOWN;
   p->aDown[0].RdOff         = 0u;
   p->aDown[0].WrOff         = 0u;
   p->aDown[0].Flags         = SEGGER_RTT_MODE_DEFAULT;
   //
   // Finish initialization of the control block.
-  // Copy Id string in three steps to make sure "SEGGER RTT" is not found
-  // in initializer memory (usually flash) by J-Link
+  // Copy Id string backwards to make sure that "SEGGER RTT" is not found in initializer memory (usually flash),
+  // as this would cause J-Link to "find" the control block at a wrong address.
   //
-  STRCPY(&p->acID[7], "RTT", 9);
-  STRCPY(&p->acID[0], "SEGGER", 7);
-  p->acID[6] = ' ';
+  RTT__DMB();                       // Force order of memory accesses for cores that may perform out-of-order memory accesses
+  for (i = 0; i < sizeof(_aInitStr) - 1; ++i) {
+    p->acID[i] = _aInitStr[sizeof(_aInitStr) - 2 - i];  // Skip terminating \0 at the end of the array
+  }
+  RTT__DMB();                       // Force order of memory accesses for cores that may perform out-of-order memory accesses
 }
 
 /*********************************************************************
@@ -327,9 +377,7 @@ static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer,
   unsigned NumBytesWritten;
   unsigned RdOff;
   unsigned WrOff;
-#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-  char*    pDst;
-#endif
+  volatile char* pDst;
   //
   // Write data to buffer and handle wrap-around if necessary
   //
@@ -344,8 +392,8 @@ static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer,
     }
     NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff));      // Number of bytes that can be written until buffer wrap-around
     NumBytesToWrite = MIN(NumBytesToWrite, NumBytes);
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pDst = pRing->pBuffer + WrOff;
     NumBytesWritten += NumBytesToWrite;
     NumBytes        -= NumBytesToWrite;
     WrOff           += NumBytesToWrite;
@@ -353,7 +401,7 @@ static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer,
       *pDst++ = *pBuffer++;
     };
 #else
-    SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pBuffer, NumBytesToWrite);
+    SEGGER_RTT_MEMCPY((void*)pDst, pBuffer, NumBytesToWrite);
     NumBytesWritten += NumBytesToWrite;
     pBuffer         += NumBytesToWrite;
     NumBytes        -= NumBytesToWrite;
@@ -362,9 +410,9 @@ static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer,
     if (WrOff == pRing->SizeOfBuffer) {
       WrOff = 0u;
     }
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff;
   } while (NumBytes);
-  //
   return NumBytesWritten;
 }
 
@@ -390,9 +438,7 @@ static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsign
   unsigned NumBytesAtOnce;
   unsigned WrOff;
   unsigned Rem;
-#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-  char*    pDst;
-#endif
+  volatile char* pDst;
 
   WrOff = pRing->WrOff;
   Rem = pRing->SizeOfBuffer - WrOff;
@@ -400,15 +446,17 @@ static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsign
     //
     // All data fits before wrap around
     //
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pDst = pRing->pBuffer + WrOff;
     WrOff += NumBytes;
     while (NumBytes--) {
       *pDst++ = *pData++;
     };
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff;
 #else
-    SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytes);
+    SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes);
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff + NumBytes;
 #endif
   } else {
@@ -416,22 +464,26 @@ static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsign
     // We reach the end of the buffer, so need to wrap around
     //
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pDst = pRing->pBuffer + WrOff;
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
     NumBytesAtOnce = Rem;
     while (NumBytesAtOnce--) {
       *pDst++ = *pData++;
     };
-    pDst = pRing->pBuffer;
+    pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
     NumBytesAtOnce = NumBytes - Rem;
     while (NumBytesAtOnce--) {
       *pDst++ = *pData++;
     };
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = NumBytes - Rem;
 #else
     NumBytesAtOnce = Rem;
-    SEGGER_RTT_MEMCPY(pRing->pBuffer + WrOff, pData, NumBytesAtOnce);
+    pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce);
     NumBytesAtOnce = NumBytes - Rem;
-    SEGGER_RTT_MEMCPY(pRing->pBuffer, pData + Rem, NumBytesAtOnce);
+    pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
+    SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce);
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = NumBytesAtOnce;
 #endif
   }
@@ -496,6 +548,7 @@ static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) {
 *
 **********************************************************************
 */
+
 /*********************************************************************
 *
 *       SEGGER_RTT_ReadUpBufferNoLock()
@@ -525,12 +578,10 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
   unsigned                WrOff;
   unsigned char*          pBuffer;
   SEGGER_RTT_BUFFER_UP*   pRing;
-#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-  const char*             pSrc;
-#endif
-  //
+  volatile char*          pSrc;
+
   INIT();
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   pBuffer = (unsigned char*)pData;
   RdOff = pRing->RdOff;
   WrOff = pRing->WrOff;
@@ -541,8 +592,8 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
   if (RdOff > WrOff) {
     NumBytesRem = pRing->SizeOfBuffer - RdOff;
     NumBytesRem = MIN(NumBytesRem, BufferSize);
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pSrc = pRing->pBuffer + RdOff;
     NumBytesRead += NumBytesRem;
     BufferSize   -= NumBytesRem;
     RdOff        += NumBytesRem;
@@ -550,7 +601,7 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
       *pBuffer++ = *pSrc++;
     };
 #else
-    SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem);
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
     NumBytesRead += NumBytesRem;
     pBuffer      += NumBytesRem;
     BufferSize   -= NumBytesRem;
@@ -569,8 +620,8 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
   NumBytesRem = WrOff - RdOff;
   NumBytesRem = MIN(NumBytesRem, BufferSize);
   if (NumBytesRem > 0u) {
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pSrc = pRing->pBuffer + RdOff;
     NumBytesRead += NumBytesRem;
     BufferSize   -= NumBytesRem;
     RdOff        += NumBytesRem;
@@ -578,7 +629,7 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
       *pBuffer++ = *pSrc++;
     };
 #else
-    SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem);
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
     NumBytesRead += NumBytesRem;
     pBuffer      += NumBytesRem;
     BufferSize   -= NumBytesRem;
@@ -619,12 +670,10 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
   unsigned                WrOff;
   unsigned char*          pBuffer;
   SEGGER_RTT_BUFFER_DOWN* pRing;
-#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-  const char*             pSrc;
-#endif
+  volatile char*          pSrc;
   //
   INIT();
-  pRing = &_SEGGER_RTT.aDown[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   pBuffer = (unsigned char*)pData;
   RdOff = pRing->RdOff;
   WrOff = pRing->WrOff;
@@ -635,8 +684,8 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
   if (RdOff > WrOff) {
     NumBytesRem = pRing->SizeOfBuffer - RdOff;
     NumBytesRem = MIN(NumBytesRem, BufferSize);
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pSrc = pRing->pBuffer + RdOff;
     NumBytesRead += NumBytesRem;
     BufferSize   -= NumBytesRem;
     RdOff        += NumBytesRem;
@@ -644,7 +693,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
       *pBuffer++ = *pSrc++;
     };
 #else
-    SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem);
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
     NumBytesRead += NumBytesRem;
     pBuffer      += NumBytesRem;
     BufferSize   -= NumBytesRem;
@@ -663,8 +712,8 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
   NumBytesRem = WrOff - RdOff;
   NumBytesRem = MIN(NumBytesRem, BufferSize);
   if (NumBytesRem > 0u) {
+    pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-    pSrc = pRing->pBuffer + RdOff;
     NumBytesRead += NumBytesRem;
     BufferSize   -= NumBytesRem;
     RdOff        += NumBytesRem;
@@ -672,7 +721,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
       *pBuffer++ = *pSrc++;
     };
 #else
-    SEGGER_RTT_MEMCPY(pBuffer, pRing->pBuffer + RdOff, NumBytesRem);
+    SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem);
     NumBytesRead += NumBytesRem;
     pBuffer      += NumBytesRem;
     BufferSize   -= NumBytesRem;
@@ -713,7 +762,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
 */
 unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) {
   unsigned NumBytesRead;
-  //
+
   SEGGER_RTT_LOCK();
   //
   // Call the non-locking read function
@@ -745,7 +794,7 @@ unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned B
 */
 unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) {
   unsigned NumBytesRead;
-  //
+
   SEGGER_RTT_LOCK();
   //
   // Call the non-locking read function
@@ -786,15 +835,12 @@ void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuff
   const char*           pData;
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned              Avail;
-#if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-  char*                 pDst;
-#endif
-
-  pData = (const char *)pBuffer;
+  volatile char*        pDst;
   //
   // Get "to-host" ring buffer and copy some elements into local variables.
   //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pData = (const char *)pBuffer;
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Check if we will overwrite data and need to adjust the RdOff.
   //
@@ -820,15 +866,17 @@ void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuff
       //
       // Last round
       //
+      pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-      pDst = pRing->pBuffer + pRing->WrOff;
       Avail = NumBytes;
       while (NumBytes--) {
         *pDst++ = *pData++;
       };
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff += Avail;
 #else
-      SEGGER_RTT_MEMCPY(pRing->pBuffer + pRing->WrOff, pData, NumBytes);
+      SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes);
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff += NumBytes;
 #endif
       break;
@@ -836,16 +884,18 @@ void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuff
       //
       //  Wrap-around necessary, write until wrap-around and reset WrOff
       //
+      pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
 #if SEGGER_RTT_MEMCPY_USE_BYTELOOP
-      pDst = pRing->pBuffer + pRing->WrOff;
       NumBytes -= Avail;
       while (Avail--) {
         *pDst++ = *pData++;
       };
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff = 0;
 #else
-      SEGGER_RTT_MEMCPY(pRing->pBuffer + pRing->WrOff, pData, Avail);
+      SEGGER_RTT_MEMCPY((void*)pDst, pData, Avail);
       pData += Avail;
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff = 0;
       NumBytes -= Avail;
 #endif
@@ -889,6 +939,7 @@ unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, u
   unsigned              RdOff;
   unsigned              WrOff;
   unsigned              Rem;
+  volatile char*        pDst;
   //
   // Cases:
   //   1) RdOff <= WrOff => Space until wrap-around is sufficient
@@ -900,21 +951,22 @@ unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, u
   // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough
   //
   pData = (const char *)pBuffer;
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   RdOff = pRing->RdOff;
   WrOff = pRing->WrOff;
+  pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF;
   if (RdOff <= WrOff) {                                 // Case 1), 2) or 3)
     Avail = pRing->SizeOfBuffer - WrOff - 1u;           // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0)
     if (Avail >= NumBytes) {                            // Case 1)?
-CopyStraight:
-      memcpy(pRing->pBuffer + WrOff, pData, NumBytes);
+      memcpy((void*)pDst, pData, NumBytes);
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff = WrOff + NumBytes;
       return 1;
     }
     Avail += RdOff;                                     // Space incl. wrap-around
     if (Avail >= NumBytes) {                            // Case 2? => If not, we have case 3) (does not fit)
       Rem = pRing->SizeOfBuffer - WrOff;                // Space until end of buffer
-      memcpy(pRing->pBuffer + WrOff, pData, Rem);       // Copy 1st chunk
+      memcpy((void*)pDst, pData, Rem);                  // Copy 1st chunk
       NumBytes -= Rem;
       //
       // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used
@@ -923,15 +975,20 @@ CopyStraight:
       // Therefore, check if 2nd memcpy is necessary at all
       //
       if (NumBytes) {
-        memcpy(pRing->pBuffer, pData + Rem, NumBytes);
+        pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF;
+        memcpy((void*)pDst, pData + Rem, NumBytes);
       }
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
       pRing->WrOff = NumBytes;
       return 1;
     }
   } else {                                             // Potential case 4)
     Avail = RdOff - WrOff - 1u;
     if (Avail >= NumBytes) {                           // Case 4)? => If not, we have case 5) (does not fit)
-      goto CopyStraight;
+      memcpy((void*)pDst, pData, NumBytes);
+      RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
+      pRing->WrOff = WrOff + NumBytes;
+      return 1;
     }
   }
   return 0;     // No space in buffer
@@ -971,13 +1028,12 @@ unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuf
   unsigned                Avail;
   const char*             pData;
   SEGGER_RTT_BUFFER_UP*   pRing;
-
-  pData = (const char *)pBuffer;
   //
   // Get "to-target" ring buffer.
   // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be modified by J-Link.
   //
-  pRing = (SEGGER_RTT_BUFFER_UP*)&_SEGGER_RTT.aDown[BufferIndex];
+  pData = (const char *)pBuffer;
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // How we output depends upon the mode...
   //
@@ -1047,12 +1103,11 @@ unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsig
   unsigned              Avail;
   const char*           pData;
   SEGGER_RTT_BUFFER_UP* pRing;
-
-  pData = (const char *)pBuffer;
   //
   // Get "to-host" ring buffer.
   //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pData = (const char *)pBuffer;
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // How we output depends upon the mode...
   //
@@ -1121,18 +1176,11 @@ unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsig
 */
 unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
   unsigned Status;
-  //
+
   INIT();
   SEGGER_RTT_LOCK();
-  //
-  // Call the non-locking write function
-  //
-  Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes);
-  //
-  // Finish up.
-  //
+  Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes);  // Call the non-locking write function
   SEGGER_RTT_UNLOCK();
-  //
   return Status;
 }
 
@@ -1157,18 +1205,11 @@ unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, u
 */
 unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) {
   unsigned Status;
-  //
+
   INIT();
   SEGGER_RTT_LOCK();
-  //
-  // Call the non-locking write function
-  //
-  Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes);
-  //
-  // Finish up.
-  //
+  Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes);  // Call the non-locking write function
   SEGGER_RTT_UNLOCK();
-  //
   return Status;
 }
 
@@ -1226,10 +1267,11 @@ unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) {
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned              WrOff;
   unsigned              Status;
+  volatile char*        pDst;
   //
   // Get "to-host" ring buffer.
   //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Get write position and handle wrap-around if necessary
   //
@@ -1241,7 +1283,9 @@ unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) {
   // Output byte if free space is available
   //
   if (WrOff != pRing->RdOff) {
-    pRing->pBuffer[pRing->WrOff] = c;
+    pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    *pDst = c;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff;
     Status = 1;
   } else {
@@ -1273,6 +1317,7 @@ unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) {
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned              WrOff;
   unsigned              Status;
+  volatile char*        pDst;
   //
   // Prepare
   //
@@ -1281,7 +1326,7 @@ unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) {
   //
   // Get "to-host" ring buffer.
   //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Get write position and handle wrap-around if necessary
   //
@@ -1293,7 +1338,9 @@ unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) {
   // Output byte if free space is available
   //
   if (WrOff != pRing->RdOff) {
-    pRing->pBuffer[pRing->WrOff] = c;
+    pDst  = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    *pDst = c;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff;
     Status = 1;
   } else {
@@ -1329,6 +1376,7 @@ unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) {
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned              WrOff;
   unsigned              Status;
+  volatile char*        pDst;
   //
   // Prepare
   //
@@ -1337,7 +1385,7 @@ unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) {
   //
   // Get "to-host" ring buffer.
   //
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Get write position and handle wrap-around if necessary
   //
@@ -1357,7 +1405,9 @@ unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) {
   // Output byte if free space is available
   //
   if (WrOff != pRing->RdOff) {
-    pRing->pBuffer[pRing->WrOff] = c;
+    pDst  = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF;
+    *pDst = c;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     pRing->WrOff = WrOff;
     Status = 1;
   } else {
@@ -1367,7 +1417,6 @@ unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) {
   // Finish up.
   //
   SEGGER_RTT_UNLOCK();
-  //
   return Status;
 }
 
@@ -1404,7 +1453,7 @@ int SEGGER_RTT_GetKey(void) {
 *       SEGGER_RTT_WaitKey
 *
 *  Function description
-*    Waits until at least one character is available in the SEGGER RTT buffer.
+*    Waits until at least one character is avaible in the SEGGER RTT buffer.
 *    Once a character is available, it is read and this function returns.
 *
 *  Return value
@@ -1438,12 +1487,14 @@ int SEGGER_RTT_WaitKey(void) {
 *    (1) This function is only specified for accesses to RTT buffer 0
 */
 int SEGGER_RTT_HasKey(void) {
+  SEGGER_RTT_BUFFER_DOWN* pRing;
   unsigned RdOff;
   int r;
 
   INIT();
-  RdOff = _SEGGER_RTT.aDown[0].RdOff;
-  if (RdOff != _SEGGER_RTT.aDown[0].WrOff) {
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  RdOff = pRing->RdOff;
+  if (RdOff != pRing->WrOff) {
     r = 1;
   } else {
     r = 0;
@@ -1467,7 +1518,7 @@ unsigned SEGGER_RTT_HasData(unsigned BufferIndex) {
   SEGGER_RTT_BUFFER_DOWN* pRing;
   unsigned                v;
 
-  pRing = &_SEGGER_RTT.aDown[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   v = pRing->WrOff;
   return v - pRing->RdOff;
 }
@@ -1488,7 +1539,7 @@ unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) {
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned                v;
 
-  pRing = &_SEGGER_RTT.aUp[BufferIndex];
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   v = pRing->RdOff;
   return pRing->WrOff - v;
 }
@@ -1507,6 +1558,7 @@ unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) {
 *    pBuffer      Pointer to a buffer to be used.
 *    BufferSize   Size of the buffer.
 *    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0 - O.K. Buffer Index
@@ -1514,23 +1566,26 @@ unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) {
 */
 int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
   int BufferIndex;
+  volatile SEGGER_RTT_CB* pRTTCB;
 
   INIT();
   SEGGER_RTT_LOCK();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   BufferIndex = 0;
   do {
-    if (_SEGGER_RTT.aDown[BufferIndex].pBuffer == NULL) {
+    if (pRTTCB->aDown[BufferIndex].pBuffer == NULL) {
       break;
     }
     BufferIndex++;
-  } while (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers);
-  if (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers) {
-    _SEGGER_RTT.aDown[BufferIndex].sName        = sName;
-    _SEGGER_RTT.aDown[BufferIndex].pBuffer      = (char*)pBuffer;
-    _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize;
-    _SEGGER_RTT.aDown[BufferIndex].RdOff        = 0u;
-    _SEGGER_RTT.aDown[BufferIndex].WrOff        = 0u;
-    _SEGGER_RTT.aDown[BufferIndex].Flags        = Flags;
+  } while (BufferIndex < pRTTCB->MaxNumDownBuffers);
+  if (BufferIndex < pRTTCB->MaxNumDownBuffers) {
+    pRTTCB->aDown[BufferIndex].sName        = sName;
+    pRTTCB->aDown[BufferIndex].pBuffer      = (char*)pBuffer;
+    pRTTCB->aDown[BufferIndex].SizeOfBuffer = BufferSize;
+    pRTTCB->aDown[BufferIndex].RdOff        = 0u;
+    pRTTCB->aDown[BufferIndex].WrOff        = 0u;
+    pRTTCB->aDown[BufferIndex].Flags        = Flags;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
   } else {
     BufferIndex = -1;
   }
@@ -1552,6 +1607,7 @@ int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned Buffer
 *    pBuffer      Pointer to a buffer to be used.
 *    BufferSize   Size of the buffer.
 *    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0 - O.K. Buffer Index
@@ -1559,23 +1615,26 @@ int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned Buffer
 */
 int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
   int BufferIndex;
+  volatile SEGGER_RTT_CB* pRTTCB;
 
   INIT();
   SEGGER_RTT_LOCK();
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   BufferIndex = 0;
   do {
-    if (_SEGGER_RTT.aUp[BufferIndex].pBuffer == NULL) {
+    if (pRTTCB->aUp[BufferIndex].pBuffer == NULL) {
       break;
     }
     BufferIndex++;
-  } while (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers);
-  if (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers) {
-    _SEGGER_RTT.aUp[BufferIndex].sName        = sName;
-    _SEGGER_RTT.aUp[BufferIndex].pBuffer      = (char*)pBuffer;
-    _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize;
-    _SEGGER_RTT.aUp[BufferIndex].RdOff        = 0u;
-    _SEGGER_RTT.aUp[BufferIndex].WrOff        = 0u;
-    _SEGGER_RTT.aUp[BufferIndex].Flags        = Flags;
+  } while (BufferIndex < pRTTCB->MaxNumUpBuffers);
+  if (BufferIndex < pRTTCB->MaxNumUpBuffers) {
+    pRTTCB->aUp[BufferIndex].sName        = sName;
+    pRTTCB->aUp[BufferIndex].pBuffer      = (char*)pBuffer;
+    pRTTCB->aUp[BufferIndex].SizeOfBuffer = BufferSize;
+    pRTTCB->aUp[BufferIndex].RdOff        = 0u;
+    pRTTCB->aUp[BufferIndex].WrOff        = 0u;
+    pRTTCB->aUp[BufferIndex].Flags        = Flags;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
   } else {
     BufferIndex = -1;
   }
@@ -1598,6 +1657,7 @@ int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSi
 *    pBuffer      Pointer to a buffer to be used.
 *    BufferSize   Size of the buffer.
 *    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0 - O.K.
@@ -1610,18 +1670,22 @@ int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSi
 */
 int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_UP* pUp;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
     SEGGER_RTT_LOCK();
-    if (BufferIndex > 0u) {
-      _SEGGER_RTT.aUp[BufferIndex].sName        = sName;
-      _SEGGER_RTT.aUp[BufferIndex].pBuffer      = (char*)pBuffer;
-      _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize;
-      _SEGGER_RTT.aUp[BufferIndex].RdOff        = 0u;
-      _SEGGER_RTT.aUp[BufferIndex].WrOff        = 0u;
+    pUp = &pRTTCB->aUp[BufferIndex];
+    if (BufferIndex) {
+      pUp->sName        = sName;
+      pUp->pBuffer      = (char*)pBuffer;
+      pUp->SizeOfBuffer = BufferSize;
+      pUp->RdOff        = 0u;
+      pUp->WrOff        = 0u;
     }
-    _SEGGER_RTT.aUp[BufferIndex].Flags          = Flags;
+    pUp->Flags          = Flags;
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1645,6 +1709,7 @@ int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBu
 *    pBuffer      Pointer to a buffer to be used.
 *    BufferSize   Size of the buffer.
 *    Flags        Operating modes. Define behavior if buffer is full (not enough space for entire message).
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0  O.K.
@@ -1657,18 +1722,23 @@ int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBu
 */
 int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_DOWN* pDown;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
     SEGGER_RTT_LOCK();
-    if (BufferIndex > 0u) {
-      _SEGGER_RTT.aDown[BufferIndex].sName        = sName;
-      _SEGGER_RTT.aDown[BufferIndex].pBuffer      = (char*)pBuffer;
-      _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize;
-      _SEGGER_RTT.aDown[BufferIndex].RdOff        = 0u;
-      _SEGGER_RTT.aDown[BufferIndex].WrOff        = 0u;
+    pDown = &pRTTCB->aDown[BufferIndex];
+    if (BufferIndex) {
+      pDown->sName        = sName;
+      pDown->pBuffer      = (char*)pBuffer;
+      pDown->SizeOfBuffer = BufferSize;
+      pDown->RdOff        = 0u;
+      pDown->WrOff        = 0u;
     }
-    _SEGGER_RTT.aDown[BufferIndex].Flags          = Flags;
+    pDown->Flags          = Flags;
+    RTT__DMB();                     // Force data write to be complete before writing the <WrOff>, in case CPU is allowed to change the order of memory accesses
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1695,11 +1765,15 @@ int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* p
 */
 int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_UP* pUp;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
     SEGGER_RTT_LOCK();
-    _SEGGER_RTT.aUp[BufferIndex].sName = sName;
+    pUp = &pRTTCB->aUp[BufferIndex];
+    pUp->sName = sName;
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1726,11 +1800,15 @@ int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) {
 */
 int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_DOWN* pDown;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
     SEGGER_RTT_LOCK();
-    _SEGGER_RTT.aDown[BufferIndex].sName = sName;
+    pDown = &pRTTCB->aDown[BufferIndex];
+    pDown->sName = sName;
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1750,6 +1828,7 @@ int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) {
 *  Parameters
 *    BufferIndex  Index of the buffer.
 *    Flags        Flags to set for the buffer.
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0  O.K.
@@ -1757,11 +1836,15 @@ int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) {
 */
 int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_UP* pUp;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
     SEGGER_RTT_LOCK();
-    _SEGGER_RTT.aUp[BufferIndex].Flags = Flags;
+    pUp = &pRTTCB->aUp[BufferIndex];
+    pUp->Flags = Flags;
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1781,6 +1864,7 @@ int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) {
 *  Parameters
 *    BufferIndex  Index of the buffer to renamed.
 *    Flags        Flags to set for the buffer.
+*                 Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 *
 *  Return value
 *    >= 0  O.K.
@@ -1788,11 +1872,15 @@ int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) {
 */
 int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) {
   int r;
+  volatile SEGGER_RTT_CB* pRTTCB;
+  volatile SEGGER_RTT_BUFFER_DOWN* pDown;
 
   INIT();
-  if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) {
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
     SEGGER_RTT_LOCK();
-    _SEGGER_RTT.aDown[BufferIndex].Flags = Flags;
+    pDown = &pRTTCB->aDown[BufferIndex];
+    pDown->Flags = Flags;
     SEGGER_RTT_UNLOCK();
     r =  0;
   } else {
@@ -1827,21 +1915,23 @@ void SEGGER_RTT_Init (void) {
 *  Return value
 *    >= 0  O.K.
 *     < 0  Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id)
+*
+*  Notes
+*    (1) Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed
 */
 int SEGGER_RTT_SetTerminal (unsigned char TerminalId) {
   unsigned char         ac[2];
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned Avail;
   int r;
-  //
+
   INIT();
-  //
   r = 0;
   ac[0] = 0xFFu;
   if (TerminalId < sizeof(_aTerminalId)) { // We only support a certain number of channels
     ac[1] = _aTerminalId[TerminalId];
-    pRing = &_SEGGER_RTT.aUp[0];    // Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed
-    SEGGER_RTT_LOCK();    // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing
+    pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+    SEGGER_RTT_LOCK();                     // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing
     if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) {
       _ActiveTerminal = TerminalId;
       _WriteBlocking(pRing, (const char*)ac, 2u);
@@ -1892,7 +1982,7 @@ int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) {
     //
     // Get "to-host" ring buffer.
     //
-    pRing = &_SEGGER_RTT.aUp[0];
+    pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
     //
     // Need to be able to change terminal, write data, change back.
     // Compute the fixed and variable sizes.
@@ -1966,8 +2056,11 @@ int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) {
 *  Return value
 *    Number of bytes that are free in the selected up buffer.
 */
-unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex){
-  return _GetAvailWriteSpace(&_SEGGER_RTT.aUp[BufferIndex]);
+unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex) {
+  SEGGER_RTT_BUFFER_UP* pRing;
+
+  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  return _GetAvailWriteSpace(pRing);
 }
 
 
@@ -1988,16 +2081,18 @@ unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) {
   unsigned RdOff;
   unsigned WrOff;
   unsigned r;
+  volatile SEGGER_RTT_CB* pRTTCB;
   //
   // Avoid warnings regarding volatile access order.  It's not a problem
   // in this case, but dampen compiler enthusiasm.
   //
-  RdOff = _SEGGER_RTT.aUp[BufferIndex].RdOff;
-  WrOff = _SEGGER_RTT.aUp[BufferIndex].WrOff;
+  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  RdOff = pRTTCB->aUp[BufferIndex].RdOff;
+  WrOff = pRTTCB->aUp[BufferIndex].WrOff;
   if (RdOff <= WrOff) {
     r = WrOff - RdOff;
   } else {
-    r = _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff);
+    r = pRTTCB->aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff);
   }
   return r;
 }
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.h b/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
index 07eb4f39e..a3161f694 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
@@ -46,16 +46,14 @@ File    : SEGGER_RTT.h
 Purpose : Implementation of SEGGER real-time transfer which allows
           real-time communication on targets which support debugger
           memory accesses while the CPU is running.
-Revision: $Rev: 17697 $
+Revision: $Rev: 25842 $
 ----------------------------------------------------------------------
 */
 
 #ifndef SEGGER_RTT_H
 #define SEGGER_RTT_H
 
-#include "SEGGER_RTT_Conf.h"
-
-
+#include "../Config/SEGGER_RTT_Conf.h"
 
 /*********************************************************************
 *
@@ -63,46 +61,168 @@ Revision: $Rev: 17697 $
 *
 **********************************************************************
 */
+
 #ifndef RTT_USE_ASM
-  #if (defined __SES_ARM)                       // SEGGER Embedded Studio
+  //
+  // Some cores support out-of-order memory accesses (reordering of memory accesses in the core)
+  // For such cores, we need to define a memory barrier to guarantee the order of certain accesses to the RTT ring buffers.
+  // Needed for:
+  //   Cortex-M7 (ARMv7-M)
+  //   Cortex-M23 (ARM-v8M)
+  //   Cortex-M33 (ARM-v8M)
+  //   Cortex-A/R (ARM-v7A/R)
+  //
+  // We do not explicitly check for "Embedded Studio" as the compiler in use determines what we support.
+  // You can use an external toolchain like IAR inside ES. So there is no point in checking for "Embedded Studio"
+  //
+  #if (defined __CROSSWORKS_ARM)                  // Rowley Crossworks
     #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __CROSSWORKS_ARM)              // Rowley Crossworks
-    #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __GNUC__)                      // GCC
-    #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __clang__)                     // Clang compiler
-    #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __IASMARM__)                   // IAR assembler
-    #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __ICCARM__)                    // IAR compiler
-    #define _CC_HAS_RTT_ASM_SUPPORT 1
-  #else
-    #define _CC_HAS_RTT_ASM_SUPPORT 0
-  #endif
-  #if (defined __ARM_ARCH_7M__)                 // Cortex-M3/4
-    #define _CORE_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __ARM_ARCH_7EM__)              // Cortex-M7
-    #define _CORE_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __ARM_ARCH_8M_MAIN__)          // Cortex-M33
-    #define _CORE_HAS_RTT_ASM_SUPPORT 1
-  #elif (defined __ARM7M__)                     // IAR Cortex-M3/4
-    #if (__CORE__ == __ARM7M__)
+    #if (defined __ARM_ARCH_7M__)                 // Cortex-M3
       #define _CORE_HAS_RTT_ASM_SUPPORT 1
+    #elif (defined __ARM_ARCH_7EM__)              // Cortex-M4/M7
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_BASE__)          // Cortex-M23
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_MAIN__)          // Cortex-M33
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
     #else
       #define _CORE_HAS_RTT_ASM_SUPPORT 0
     #endif
-  #elif (defined __ARM7EM__)                    // IAR Cortex-M7
-    #if (__CORE__ == __ARM7EM__)
+  #elif (defined __ARMCC_VERSION)
+    //
+    // ARM compiler
+    // ARM compiler V6.0 and later is clang based.
+    // Our ASM part is compatible to clang.
+    //
+    #if (__ARMCC_VERSION >= 6000000)
+      #define _CC_HAS_RTT_ASM_SUPPORT 1
+    #else
+      #define _CC_HAS_RTT_ASM_SUPPORT 0
+    #endif
+    #if (defined __ARM_ARCH_6M__)                 // Cortex-M0 / M1
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0         // No ASM support for this architecture
+    #elif (defined __ARM_ARCH_7M__)               // Cortex-M3
       #define _CORE_HAS_RTT_ASM_SUPPORT 1
+    #elif (defined __ARM_ARCH_7EM__)              // Cortex-M4/M7
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_BASE__)          // Cortex-M23
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_MAIN__)          // Cortex-M33
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__))  // Cortex-A/R 32-bit ARMv7-A/R
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
     #else
       #define _CORE_HAS_RTT_ASM_SUPPORT 0
     #endif
+  #elif ((defined __GNUC__) || (defined __clang__))
+    //
+    // GCC / Clang
+    //
+    #define _CC_HAS_RTT_ASM_SUPPORT 1
+    // ARM 7/9: __ARM_ARCH_5__ / __ARM_ARCH_5E__ / __ARM_ARCH_5T__ / __ARM_ARCH_5T__ / __ARM_ARCH_5TE__
+    #if (defined __ARM_ARCH_7M__)                 // Cortex-M3
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+    #elif (defined __ARM_ARCH_7EM__)              // Cortex-M4/M7
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1         // Only Cortex-M7 needs a DMB but we cannot distinguish M4 and M7 here...
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_BASE__)          // Cortex-M23
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8M_MAIN__)          // Cortex-M33
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__))  // Cortex-A/R 32-bit ARMv7-A/R
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #else
+      #define _CORE_HAS_RTT_ASM_SUPPORT 0
+    #endif
+  #elif ((defined __IASMARM__) || (defined __ICCARM__))
+    //
+    // IAR assembler/compiler
+    //
+    #define _CC_HAS_RTT_ASM_SUPPORT 1
+    #if (__VER__ < 6300000)
+      #define VOLATILE
+    #else
+      #define VOLATILE volatile
+    #endif
+    #if (defined __ARM7M__)                            // Needed for old versions that do not know the define yet
+      #if (__CORE__ == __ARM7M__)                      // Cortex-M3
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #endif
+    #endif
+    #if (defined __ARM7EM__)
+      #if (__CORE__ == __ARM7EM__)                     // Cortex-M4/M7
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM8M_BASELINE__)
+      #if (__CORE__ == __ARM8M_BASELINE__)             // Cortex-M23
+        #define _CORE_HAS_RTT_ASM_SUPPORT 0
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM8M_MAINLINE__)
+      #if (__CORE__ == __ARM8M_MAINLINE__)             // Cortex-M33
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM8EM_MAINLINE__)
+      #if (__CORE__ == __ARM8EM_MAINLINE__)            // Cortex-???
+        #define _CORE_HAS_RTT_ASM_SUPPORT 1
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM7A__)
+      #if (__CORE__ == __ARM7A__)                      // Cortex-A 32-bit ARMv7-A
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+    #if (defined __ARM7R__)
+      #if (__CORE__ == __ARM7R__)                      // Cortex-R 32-bit ARMv7-R
+        #define _CORE_NEEDS_DMB 1
+        #define RTT__DMB() asm VOLATILE ("DMB");
+      #endif
+    #endif
+// TBD: __ARM8A__ => Cortex-A 64-bit ARMv8-A
+// TBD: __ARM8R__ => Cortex-R 64-bit ARMv8-R
   #else
+    //
+    // Other compilers
+    //
+    #define _CC_HAS_RTT_ASM_SUPPORT   0
     #define _CORE_HAS_RTT_ASM_SUPPORT 0
   #endif
   //
   // If IDE and core support the ASM version, enable ASM version by default
   //
+  #ifndef _CORE_HAS_RTT_ASM_SUPPORT
+    #define _CORE_HAS_RTT_ASM_SUPPORT 0              // Default for unknown cores
+  #endif
   #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT)
     #define RTT_USE_ASM                           (1)
   #else
@@ -110,6 +230,35 @@ Revision: $Rev: 17697 $
   #endif
 #endif
 
+#ifndef _CORE_NEEDS_DMB
+  #define _CORE_NEEDS_DMB 0
+#endif
+
+#ifndef RTT__DMB
+  #if _CORE_NEEDS_DMB
+    #error "Don't know how to place inline assembly for DMB"
+  #else
+    #define RTT__DMB()
+  #endif
+#endif
+
+#ifndef SEGGER_RTT_CPU_CACHE_LINE_SIZE
+  #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (0)   // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here
+#endif
+
+#ifndef SEGGER_RTT_UNCACHED_OFF
+  #if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    #error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #else
+    #define SEGGER_RTT_UNCACHED_OFF (0)
+  #endif
+#endif
+#if RTT_USE_ASM
+  #if SEGGER_RTT_CPU_CACHE_LINE_SIZE
+    #error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0"
+  #endif
+#endif
+
 #ifndef SEGGER_RTT_ASM  // defined when SEGGER_RTT.h is included from assembly file
 #include <stdlib.h>
 #include <stdarg.h>
@@ -121,6 +270,21 @@ Revision: $Rev: 17697 $
 **********************************************************************
 */
 
+//
+// Determine how much we must pad the control block to make it a multiple of a cache line in size
+// Assuming: U8 = 1B
+//           U16 = 2B
+//           U32 = 4B
+//           U8/U16/U32* = 4B
+//
+#if SEGGER_RTT_CPU_CACHE_LINE_SIZE    // Avoid division by zero in case we do not have any cache
+  #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * SEGGER_RTT_CPU_CACHE_LINE_SIZE)
+#else
+  #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes)
+#endif
+#define SEGGER_RTT__CB_SIZE                              (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24))
+#define SEGGER_RTT__CB_PADDING                           (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE)
+
 /*********************************************************************
 *
 *       Types
@@ -138,7 +302,7 @@ typedef struct {
             unsigned SizeOfBuffer;  // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
             unsigned WrOff;         // Position of next item to be written by either target.
   volatile  unsigned RdOff;         // Position of next item to be read by host. Must be volatile since it may be modified by host.
-            unsigned Flags;         // Contains configuration flags
+            unsigned Flags;         // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 } SEGGER_RTT_BUFFER_UP;
 
 //
@@ -151,7 +315,7 @@ typedef struct {
             unsigned SizeOfBuffer;  // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
   volatile  unsigned WrOff;         // Position of next item to be written by host. Must be volatile since it may be modified by host.
             unsigned RdOff;         // Position of next item to be read by target (down-buffer).
-            unsigned Flags;         // Contains configuration flags
+            unsigned Flags;         // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode.
 } SEGGER_RTT_BUFFER_DOWN;
 
 //
@@ -165,6 +329,9 @@ typedef struct {
   int                     MaxNumDownBuffers;                        // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2)
   SEGGER_RTT_BUFFER_UP    aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS];       // Up buffers, transferring information up from target via debug probe to host
   SEGGER_RTT_BUFFER_DOWN  aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS];   // Down buffers, transferring information down from host via debug probe to target
+#if SEGGER_RTT__CB_PADDING
+  unsigned char           aDummy[SEGGER_RTT__CB_PADDING];
+#endif
 } SEGGER_RTT_CB;
 
 /*********************************************************************
@@ -214,7 +381,7 @@ unsigned     SEGGER_RTT_GetBytesInBuffer        (unsigned BufferIndex);
 //
 // Function macro for performance optimization
 //
-#define      SEGGER_RTT_HASDATA(n)       (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff)
+#define      SEGGER_RTT_HASDATA(n)       (((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)
 
 #if RTT_USE_ASM
   #define SEGGER_RTT_WriteSkipNoLock  SEGGER_RTT_ASM_WriteSkipNoLock
@@ -231,7 +398,7 @@ unsigned     SEGGER_RTT_ReadUpBufferNoLock      (unsigned BufferIndex, void* pDa
 unsigned     SEGGER_RTT_WriteDownBuffer         (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
 unsigned     SEGGER_RTT_WriteDownBufferNoLock   (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
 
-#define      SEGGER_RTT_HASDATA_UP(n)    (_SEGGER_RTT.aUp[n].WrOff - _SEGGER_RTT.aUp[n].RdOff)
+#define      SEGGER_RTT_HASDATA_UP(n)    (((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)   // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
 
 /*********************************************************************
 *
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S b/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S
index aec372eec..85c79899e 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT_ASM_ARMv7M.S
@@ -23,6 +23,7 @@ Additional information:
 *
 **********************************************************************
 */
+
 #define _CCIAR   0
 #define _CCCLANG 1
 
@@ -182,6 +183,9 @@ _LoopCopyStraight:                               // memcpy(pRing->pBuffer + WrOf
         SUBS     R2,R2,#+1
         BNE      _LoopCopyStraight
 _CSDone:
+#if _CORE_NEEDS_DMB                              // Do not slow down cores that do not need a DMB instruction here
+        DMB                                      // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the <WrOff> in the struct
+#endif
         STR      R0,[R6, #+12]                   // pRing->WrOff = WrOff + NumBytes;
         MOVS     R0,#+1
         POP      {R4-R7}
@@ -214,6 +218,9 @@ _LoopCopyAfterWrapAround:                        // memcpy(pRing->pBuffer, pData
         SUBS     R2,R2,#+1
         BNE      _LoopCopyAfterWrapAround
 _No2ChunkNeeded:
+#if _CORE_NEEDS_DMB                              // Do not slow down cores that do not need a DMB instruction here
+        DMB                                      // Cortex-M7 may delay memory writes and also change the order in which the writes happen. Therefore, make sure that all buffer writes are finished, before updating the <WrOff> in the struct
+#endif
         STR      R4,[R6, #+12]                   // pRing->WrOff = NumBytes; => Must be written after copying data because J-Link may read control block asynchronously while writing into buffer
         MOVS     R0,#+1
         POP      {R4-R7}
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c b/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c
deleted file mode 100644
index 4c996b408..000000000
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c
+++ /dev/null
@@ -1,500 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* SEGGER strongly recommends to not make any changes                 *
-* to or modify the source code of this software in order to stay     *
-* compatible with the RTT protocol and J-Link.                       *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* condition is met:                                                  *
-*                                                                    *
-* o Redistributions of source code must retain the above copyright   *
-*   notice, this condition and the following disclaimer.             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : SEGGER_RTT_printf.c
-Purpose : Replacement for printf to write formatted data via RTT
-Revision: $Rev: 17697 $
-----------------------------------------------------------------------
-*/
-#include "SEGGER_RTT.h"
-#include "SEGGER_RTT_Conf.h"
-
-/*********************************************************************
-*
-*       Defines, configurable
-*
-**********************************************************************
-*/
-
-#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE
-  #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64)
-#endif
-
-#include <stdlib.h>
-#include <stdarg.h>
-
-
-#define FORMAT_FLAG_LEFT_JUSTIFY   (1u << 0)
-#define FORMAT_FLAG_PAD_ZERO       (1u << 1)
-#define FORMAT_FLAG_PRINT_SIGN     (1u << 2)
-#define FORMAT_FLAG_ALTERNATE      (1u << 3)
-
-/*********************************************************************
-*
-*       Types
-*
-**********************************************************************
-*/
-
-typedef struct {
-  char*     pBuffer;
-  unsigned  BufferSize;
-  unsigned  Cnt;
-
-  int   ReturnValue;
-
-  unsigned RTTBufferIndex;
-} SEGGER_RTT_PRINTF_DESC;
-
-/*********************************************************************
-*
-*       Function prototypes
-*
-**********************************************************************
-*/
-
-/*********************************************************************
-*
-*       Static code
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       _StoreChar
-*/
-static void _StoreChar(SEGGER_RTT_PRINTF_DESC * p, char c) {
-  unsigned Cnt;
-
-  Cnt = p->Cnt;
-  if ((Cnt + 1u) <= p->BufferSize) {
-    *(p->pBuffer + Cnt) = c;
-    p->Cnt = Cnt + 1u;
-    p->ReturnValue++;
-  }
-  //
-  // Write part of string, when the buffer is full
-  //
-  if (p->Cnt == p->BufferSize) {
-    if (SEGGER_RTT_Write(p->RTTBufferIndex, p->pBuffer, p->Cnt) != p->Cnt) {
-      p->ReturnValue = -1;
-    } else {
-      p->Cnt = 0u;
-    }
-  }
-}
-
-/*********************************************************************
-*
-*       _PrintUnsigned
-*/
-static void _PrintUnsigned(SEGGER_RTT_PRINTF_DESC * pBufferDesc, unsigned v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) {
-  static const char _aV2C[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
-  unsigned Div;
-  unsigned Digit;
-  unsigned Number;
-  unsigned Width;
-  char c;
-
-  Number = v;
-  Digit = 1u;
-  //
-  // Get actual field width
-  //
-  Width = 1u;
-  while (Number >= Base) {
-    Number = (Number / Base);
-    Width++;
-  }
-  if (NumDigits > Width) {
-    Width = NumDigits;
-  }
-  //
-  // Print leading chars if necessary
-  //
-  if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) {
-    if (FieldWidth != 0u) {
-      if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && (NumDigits == 0u)) {
-        c = '0';
-      } else {
-        c = ' ';
-      }
-      while ((FieldWidth != 0u) && (Width < FieldWidth)) {
-        FieldWidth--;
-        _StoreChar(pBufferDesc, c);
-        if (pBufferDesc->ReturnValue < 0) {
-          break;
-        }
-      }
-    }
-  }
-  if (pBufferDesc->ReturnValue >= 0) {
-    //
-    // Compute Digit.
-    // Loop until Digit has the value of the highest digit required.
-    // Example: If the output is 345 (Base 10), loop 2 times until Digit is 100.
-    //
-    while (1) {
-      if (NumDigits > 1u) {       // User specified a min number of digits to print? => Make sure we loop at least that often, before checking anything else (> 1 check avoids problems with NumDigits being signed / unsigned)
-        NumDigits--;
-      } else {
-        Div = v / Digit;
-        if (Div < Base) {        // Is our divider big enough to extract the highest digit from value? => Done
-          break;
-        }
-      }
-      Digit *= Base;
-    }
-    //
-    // Output digits
-    //
-    do {
-      Div = v / Digit;
-      v -= Div * Digit;
-      _StoreChar(pBufferDesc, _aV2C[Div]);
-      if (pBufferDesc->ReturnValue < 0) {
-        break;
-      }
-      Digit /= Base;
-    } while (Digit);
-    //
-    // Print trailing spaces if necessary
-    //
-    if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == FORMAT_FLAG_LEFT_JUSTIFY) {
-      if (FieldWidth != 0u) {
-        while ((FieldWidth != 0u) && (Width < FieldWidth)) {
-          FieldWidth--;
-          _StoreChar(pBufferDesc, ' ');
-          if (pBufferDesc->ReturnValue < 0) {
-            break;
-          }
-        }
-      }
-    }
-  }
-}
-
-/*********************************************************************
-*
-*       _PrintInt
-*/
-static void _PrintInt(SEGGER_RTT_PRINTF_DESC * pBufferDesc, int v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) {
-  unsigned Width;
-  int Number;
-
-  Number = (v < 0) ? -v : v;
-
-  //
-  // Get actual field width
-  //
-  Width = 1u;
-  while (Number >= (int)Base) {
-    Number = (Number / (int)Base);
-    Width++;
-  }
-  if (NumDigits > Width) {
-    Width = NumDigits;
-  }
-  if ((FieldWidth > 0u) && ((v < 0) || ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN))) {
-    FieldWidth--;
-  }
-
-  //
-  // Print leading spaces if necessary
-  //
-  if ((((FormatFlags & FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) {
-    if (FieldWidth != 0u) {
-      while ((FieldWidth != 0u) && (Width < FieldWidth)) {
-        FieldWidth--;
-        _StoreChar(pBufferDesc, ' ');
-        if (pBufferDesc->ReturnValue < 0) {
-          break;
-        }
-      }
-    }
-  }
-  //
-  // Print sign if necessary
-  //
-  if (pBufferDesc->ReturnValue >= 0) {
-    if (v < 0) {
-      v = -v;
-      _StoreChar(pBufferDesc, '-');
-    } else if ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN) {
-      _StoreChar(pBufferDesc, '+');
-    } else {
-
-    }
-    if (pBufferDesc->ReturnValue >= 0) {
-      //
-      // Print leading zeros if necessary
-      //
-      if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) && (NumDigits == 0u)) {
-        if (FieldWidth != 0u) {
-          while ((FieldWidth != 0u) && (Width < FieldWidth)) {
-            FieldWidth--;
-            _StoreChar(pBufferDesc, '0');
-            if (pBufferDesc->ReturnValue < 0) {
-              break;
-            }
-          }
-        }
-      }
-      if (pBufferDesc->ReturnValue >= 0) {
-        //
-        // Print number without sign
-        //
-        _PrintUnsigned(pBufferDesc, (unsigned)v, Base, NumDigits, FieldWidth, FormatFlags);
-      }
-    }
-  }
-}
-
-/*********************************************************************
-*
-*       Public code
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       SEGGER_RTT_vprintf
-*
-*  Function description
-*    Stores a formatted string in SEGGER RTT control block.
-*    This data is read by the host.
-*
-*  Parameters
-*    BufferIndex  Index of "Up"-buffer to be used. (e.g. 0 for "Terminal")
-*    sFormat      Pointer to format string
-*    pParamList   Pointer to the list of arguments for the format string
-*
-*  Return values
-*    >= 0:  Number of bytes which have been stored in the "Up"-buffer.
-*     < 0:  Error
-*/
-int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList) {
-  char c;
-  SEGGER_RTT_PRINTF_DESC BufferDesc;
-  int v;
-  unsigned NumDigits;
-  unsigned FormatFlags;
-  unsigned FieldWidth;
-  char acBuffer[SEGGER_RTT_PRINTF_BUFFER_SIZE];
-
-  BufferDesc.pBuffer        = acBuffer;
-  BufferDesc.BufferSize     = SEGGER_RTT_PRINTF_BUFFER_SIZE;
-  BufferDesc.Cnt            = 0u;
-  BufferDesc.RTTBufferIndex = BufferIndex;
-  BufferDesc.ReturnValue    = 0;
-
-  do {
-    c = *sFormat;
-    sFormat++;
-    if (c == 0u) {
-      break;
-    }
-    if (c == '%') {
-      //
-      // Filter out flags
-      //
-      FormatFlags = 0u;
-      v = 1;
-      do {
-        c = *sFormat;
-        switch (c) {
-        case '-': FormatFlags |= FORMAT_FLAG_LEFT_JUSTIFY; sFormat++; break;
-        case '0': FormatFlags |= FORMAT_FLAG_PAD_ZERO;     sFormat++; break;
-        case '+': FormatFlags |= FORMAT_FLAG_PRINT_SIGN;   sFormat++; break;
-        case '#': FormatFlags |= FORMAT_FLAG_ALTERNATE;    sFormat++; break;
-        default:  v = 0; break;
-        }
-      } while (v);
-      //
-      // filter out field with
-      //
-      FieldWidth = 0u;
-      do {
-        c = *sFormat;
-        if ((c < '0') || (c > '9')) {
-          break;
-        }
-        sFormat++;
-        FieldWidth = (FieldWidth * 10u) + ((unsigned)c - '0');
-      } while (1);
-
-      //
-      // Filter out precision (number of digits to display)
-      //
-      NumDigits = 0u;
-      c = *sFormat;
-      if (c == '.') {
-        sFormat++;
-        do {
-          c = *sFormat;
-          if ((c < '0') || (c > '9')) {
-            break;
-          }
-          sFormat++;
-          NumDigits = NumDigits * 10u + ((unsigned)c - '0');
-        } while (1);
-      }
-      //
-      // Filter out length modifier
-      //
-      c = *sFormat;
-      do {
-        if ((c == 'l') || (c == 'h')) {
-          sFormat++;
-          c = *sFormat;
-        } else {
-          break;
-        }
-      } while (1);
-      //
-      // Handle specifiers
-      //
-      switch (c) {
-      case 'c': {
-        char c0;
-        v = va_arg(*pParamList, int);
-        c0 = (char)v;
-        _StoreChar(&BufferDesc, c0);
-        break;
-      }
-      case 'd':
-        v = va_arg(*pParamList, int);
-        _PrintInt(&BufferDesc, v, 10u, NumDigits, FieldWidth, FormatFlags);
-        break;
-      case 'u':
-        v = va_arg(*pParamList, int);
-        _PrintUnsigned(&BufferDesc, (unsigned)v, 10u, NumDigits, FieldWidth, FormatFlags);
-        break;
-      case 'x':
-      case 'X':
-        v = va_arg(*pParamList, int);
-        _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, NumDigits, FieldWidth, FormatFlags);
-        break;
-      case 's':
-        {
-          const char * s = va_arg(*pParamList, const char *);
-          do {
-            c = *s;
-            s++;
-            if (c == '\0') {
-              break;
-            }
-           _StoreChar(&BufferDesc, c);
-          } while (BufferDesc.ReturnValue >= 0);
-        }
-        break;
-      case 'p':
-        v = va_arg(*pParamList, int);
-        _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, 8u, 8u, 0u);
-        break;
-      case '%':
-        _StoreChar(&BufferDesc, '%');
-        break;
-      default:
-        break;
-      }
-      sFormat++;
-    } else {
-      _StoreChar(&BufferDesc, c);
-    }
-  } while (BufferDesc.ReturnValue >= 0);
-
-  if (BufferDesc.ReturnValue > 0) {
-    //
-    // Write remaining data, if any
-    //
-    if (BufferDesc.Cnt != 0u) {
-      SEGGER_RTT_Write(BufferIndex, acBuffer, BufferDesc.Cnt);
-    }
-    BufferDesc.ReturnValue += (int)BufferDesc.Cnt;
-  }
-  return BufferDesc.ReturnValue;
-}
-
-/*********************************************************************
-*
-*       SEGGER_RTT_printf
-*
-*  Function description
-*    Stores a formatted string in SEGGER RTT control block.
-*    This data is read by the host.
-*
-*  Parameters
-*    BufferIndex  Index of "Up"-buffer to be used. (e.g. 0 for "Terminal")
-*    sFormat      Pointer to format string, followed by the arguments for conversion
-*
-*  Return values
-*    >= 0:  Number of bytes which have been stored in the "Up"-buffer.
-*     < 0:  Error
-*
-*  Notes
-*    (1) Conversion specifications have following syntax:
-*          %[flags][FieldWidth][.Precision]ConversionSpecifier
-*    (2) Supported flags:
-*          -: Left justify within the field width
-*          +: Always print sign extension for signed conversions
-*          0: Pad with 0 instead of spaces. Ignored when using '-'-flag or precision
-*        Supported conversion specifiers:
-*          c: Print the argument as one char
-*          d: Print the argument as a signed integer
-*          u: Print the argument as an unsigned integer
-*          x: Print the argument as an hexadecimal integer
-*          s: Print the string pointed to by the argument
-*          p: Print the argument as an 8-digit hexadecimal integer. (Argument shall be a pointer to void.)
-*/
-int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...) {
-  int r;
-  va_list ParamList;
-
-  va_start(ParamList, sFormat);
-  r = SEGGER_RTT_vprintf(BufferIndex, sFormat, &ParamList);
-  va_end(ParamList);
-  return r;
-}
-/*************************** End of file ****************************/
diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c
deleted file mode 100644
index 6bf670a02..000000000
--- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* SEGGER strongly recommends to not make any changes                 *
-* to or modify the source code of this software in order to stay     *
-* compatible with the RTT protocol and J-Link.                       *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* condition is met:                                                  *
-*                                                                    *
-* o Redistributions of source code must retain the above copyright   *
-*   notice, this condition and the following disclaimer.             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : SEGGER_RTT_Syscalls_GCC.c
-Purpose : Low-level functions for using printf() via RTT in GCC.
-          To use RTT for printf output, include this file in your
-          application.
-Revision: $Rev: 17697 $
-----------------------------------------------------------------------
-*/
-#if (defined __GNUC__) && !(defined __SES_ARM) && !(defined __CROSSWORKS_ARM)
-
-#include <reent.h>  // required for _write_r
-#include "SEGGER_RTT.h"
-
-
-/*********************************************************************
-*
-*       Types
-*
-**********************************************************************
-*/
-//
-// If necessary define the _reent struct
-// to match the one passed by the used standard library.
-//
-struct _reent;
-
-/*********************************************************************
-*
-*       Function prototypes
-*
-**********************************************************************
-*/
-int _write(int file, char *ptr, int len);
-int _write_r(struct _reent *r, int file, const void *ptr, int len);
-
-/*********************************************************************
-*
-*       Global functions
-*
-**********************************************************************
-*/
-
-/*********************************************************************
-*
-*       _write()
-*
-* Function description
-*   Low-level write function.
-*   libc subroutines will use this system routine for output to all files,
-*   including stdout.
-*   Write data via RTT.
-*/
-int _write(int file, char *ptr, int len) {
-  (void) file;  /* Not used, avoid warning */
-  SEGGER_RTT_Write(0, ptr, len);
-  return len;
-}
-
-/*********************************************************************
-*
-*       _write_r()
-*
-* Function description
-*   Low-level reentrant write function.
-*   libc subroutines will use this system routine for output to all files,
-*   including stdout.
-*   Write data via RTT.
-*/
-int _write_r(struct _reent *r, int file, const void *ptr, int len) {
-  (void) file;  /* Not used, avoid warning */
-  (void) r;     /* Not used, avoid warning */
-  SEGGER_RTT_Write(0, ptr, len);
-  return len;
-}
-
-#endif
-/****** End Of File *************************************************/
diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c
deleted file mode 100644
index 4c76752b3..000000000
--- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* SEGGER strongly recommends to not make any changes                 *
-* to or modify the source code of this software in order to stay     *
-* compatible with the RTT protocol and J-Link.                       *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* condition is met:                                                  *
-*                                                                    *
-* o Redistributions of source code must retain the above copyright   *
-*   notice, this condition and the following disclaimer.             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : SEGGER_RTT_Syscalls_IAR.c
-Purpose : Low-level functions for using printf() via RTT in IAR.
-          To use RTT for printf output, include this file in your
-          application and set the Library Configuration to Normal.
-Revision: $Rev: 17697 $
-----------------------------------------------------------------------
-*/
-#ifdef __IAR_SYSTEMS_ICC__
-
-//
-// Since IAR EWARM V8 and EWRX V4, yfuns.h is considered as deprecated and LowLevelIOInterface.h
-// shall be used instead. To not break any compatibility with older compiler versions, we have a
-// version check in here.
-//
-#if ((defined __ICCARM__) && (__VER__ >= 8000000)) || ((defined __ICCRX__)  && (__VER__ >= 400))
-  #include <LowLevelIOInterface.h>
-#else
-  #include <yfuns.h>
-#endif
-
-#include "SEGGER_RTT.h"
-#pragma module_name = "?__write"
-
-/*********************************************************************
-*
-*       Function prototypes
-*
-**********************************************************************
-*/
-size_t __write(int handle, const unsigned char * buffer, size_t size);
-
-/*********************************************************************
-*
-*       Global functions
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       __write()
-*
-* Function description
-*   Low-level write function.
-*   Standard library subroutines will use this system routine
-*   for output to all files, including stdout.
-*   Write data via RTT.
-*/
-size_t __write(int handle, const unsigned char * buffer, size_t size) {
-  (void) handle;  /* Not used, avoid warning */
-  SEGGER_RTT_Write(0, (const char*)buffer, size);
-  return size;
-}
-
-/*********************************************************************
-*
-*       __write_buffered()
-*
-* Function description
-*   Low-level write function.
-*   Standard library subroutines will use this system routine
-*   for output to all files, including stdout.
-*   Write data via RTT.
-*/
-size_t __write_buffered(int handle, const unsigned char * buffer, size_t size) {
-  (void) handle;  /* Not used, avoid warning */
-  SEGGER_RTT_Write(0, (const char*)buffer, size);
-  return size;
-}
-
-#endif
-/****** End Of File *************************************************/
diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c
deleted file mode 100644
index ba9772d3e..000000000
--- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_KEIL.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* SEGGER strongly recommends to not make any changes                 *
-* to or modify the source code of this software in order to stay     *
-* compatible with the RTT protocol and J-Link.                       *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* condition is met:                                                  *
-*                                                                    *
-* o Redistributions of source code must retain the above copyright   *
-*   notice, this condition and the following disclaimer.             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : RTT_Syscalls_KEIL.c
-Purpose : Retargeting module for KEIL MDK-CM3.
-          Low-level functions for using printf() via RTT
-Revision: $Rev: 17697 $
-----------------------------------------------------------------------
-*/
-#ifdef __CC_ARM
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <rt_sys.h>
-#include <rt_misc.h>
-
-#include "SEGGER_RTT.h"
-/*********************************************************************
-*
-*       #pragmas
-*
-**********************************************************************
-*/
-#pragma import(__use_no_semihosting)
-
-#ifdef _MICROLIB
-  #pragma import(__use_full_stdio)
-#endif
-
-/*********************************************************************
-*
-*       Defines non-configurable
-*
-**********************************************************************
-*/
-
-/* Standard IO device handles - arbitrary, but any real file system handles must be
-   less than 0x8000. */
-#define STDIN             0x8001    // Standard Input Stream
-#define STDOUT            0x8002    // Standard Output Stream
-#define STDERR            0x8003    // Standard Error Stream
-
-/*********************************************************************
-*
-*       Public const
-*
-**********************************************************************
-*/
-#if __ARMCC_VERSION < 5000000
-//const char __stdin_name[]  = "STDIN";
-const char __stdout_name[] = "STDOUT";
-const char __stderr_name[] = "STDERR";
-#endif
-
-/*********************************************************************
-*
-*       Public code
-*
-**********************************************************************
-*/
-
-/*********************************************************************
-*
-*       _ttywrch
-*
-*  Function description:
-*    Outputs a character to the console
-*
-*  Parameters:
-*    c    - character to output
-*
-*/
-void _ttywrch(int c) {
-  fputc(c, stdout); // stdout
-  fflush(stdout);
-}
-
-/*********************************************************************
-*
-*       _sys_open
-*
-*  Function description:
-*    Opens the device/file in order to do read/write operations
-*
-*  Parameters:
-*    sName        - sName of the device/file to open
-*    OpenMode    - This parameter is currently ignored
-*
-*  Return value:
-*    != 0     - Handle to the object to open, otherwise
-*    == 0     -"device" is not handled by this module
-*
-*/
-FILEHANDLE _sys_open(const char * sName, int OpenMode) {
-  (void)OpenMode;
-  // Register standard Input Output devices.
-  if (strcmp(sName, __stdout_name) == 0) {
-    return (STDOUT);
-  } else if (strcmp(sName, __stderr_name) == 0) {
-    return (STDERR);
-  } else
-  return (0);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_close
-*
-*  Function description:
-*    Closes the handle to the open device/file
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*
-*  Return value:
-*    0     - device/file closed
-*
-*/
-int _sys_close(FILEHANDLE hFile) {
-  (void)hFile;
-  return 0;  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_write
-*
-*  Function description:
-*    Writes the data to an open handle.
-*    Currently this function only outputs data to the console
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*    pBuffer  - Pointer to the data that shall be written
-*    NumBytes      - Number of bytes to write
-*    Mode     - The Mode that shall be used
-*
-*  Return value:
-*    Number of bytes *not* written to the file/device
-*
-*/
-int _sys_write(FILEHANDLE hFile, const unsigned char * pBuffer, unsigned NumBytes, int Mode) {
-  int r = 0;
-
-  (void)Mode;
-  if (hFile == STDOUT) {
-    SEGGER_RTT_Write(0, (const char*)pBuffer, NumBytes);
-		return 0;
-  }
-  return r;
-}
-
-/*********************************************************************
-*
-*       _sys_read
-*
-*  Function description:
-*    Reads data from an open handle.
-*    Currently this modules does nothing.
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*    pBuffer  - Pointer to buffer to store the read data
-*    NumBytes      - Number of bytes to read
-*    Mode     - The Mode that shall be used
-*
-*  Return value:
-*    Number of bytes read from the file/device
-*
-*/
-int _sys_read(FILEHANDLE hFile, unsigned char * pBuffer, unsigned NumBytes, int Mode) {
-  (void)hFile;
-  (void)pBuffer;
-  (void)NumBytes;
-  (void)Mode;
-  return (0);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_istty
-*
-*  Function description:
-*    This function shall return whether the opened file
-*    is a console device or not.
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*
-*  Return value:
-*    1       - Device is     a console
-*    0       - Device is not a console
-*
-*/
-int _sys_istty(FILEHANDLE hFile) {
-  if (hFile > 0x8000) {
-    return (1);
-  }
-  return (0);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_seek
-*
-*  Function description:
-*    Seeks via the file to a specific position
-*
-*  Parameters:
-*    hFile  - Handle to a file opened via _sys_open
-*    Pos    -
-*
-*  Return value:
-*    int       -
-*
-*/
-int _sys_seek(FILEHANDLE hFile, long Pos) {
-  (void)hFile;
-  (void)Pos;
-  return (0);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_ensure
-*
-*  Function description:
-*
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*
-*  Return value:
-*    int       -
-*
-*/
-int _sys_ensure(FILEHANDLE hFile) {
-  (void)hFile;
-  return (-1);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_flen
-*
-*  Function description:
-*    Returns the length of the opened file handle
-*
-*  Parameters:
-*    hFile    - Handle to a file opened via _sys_open
-*
-*  Return value:
-*    Length of the file
-*
-*/
-long _sys_flen(FILEHANDLE hFile) {
-  (void)hFile;
-  return (0);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_tmpnam
-*
-*  Function description:
-*    This function converts the file number fileno for a temporary
-*    file to a unique filename, for example, tmp0001.
-*
-*  Parameters:
-*    pBuffer    - Pointer to a buffer to store the name
-*    FileNum    - file number to convert
-*    MaxLen     - Size of the buffer
-*
-*  Return value:
-*     1 - Error
-*     0 - Success
-*
-*/
-int _sys_tmpnam(char * pBuffer, int FileNum, unsigned MaxLen) {
-  (void)pBuffer;
-  (void)FileNum;
-  (void)MaxLen;
-  return (1);  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_command_string
-*
-*  Function description:
-*    This function shall execute a system command.
-*
-*  Parameters:
-*    cmd    - Pointer to the command string
-*    len    - Length of the string
-*
-*  Return value:
-*    == NULL - Command was not successfully executed
-*    == sCmd - Command was passed successfully
-*
-*/
-char * _sys_command_string(char * cmd, int len) {
-  (void)len;
-  return cmd;  // Not implemented
-}
-
-/*********************************************************************
-*
-*       _sys_exit
-*
-*  Function description:
-*    This function is called when the application returns from main
-*
-*  Parameters:
-*    ReturnCode    - Return code from the main function
-*
-*
-*/
-void _sys_exit(int ReturnCode) {
-  (void)ReturnCode;
-  while (1);  // Not implemented
-}
-
-#if __ARMCC_VERSION >= 5000000
-/*********************************************************************
-*
-*       stdout_putchar
-*
-*  Function description:
-*    Put a character to the stdout
-*
-*  Parameters:
-*    ch    - Character to output
-*
-*
-*/
-int stdout_putchar(int ch) {
-  (void)ch;
-  return ch;  // Not implemented
-}
-#endif
-
-#endif
-/*************************** End of file ****************************/
diff --git a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c b/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c
deleted file mode 100644
index 5ce8457e1..000000000
--- a/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_SES.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*                        The Embedded Experts                        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
-*                                                                    *
-*       www.segger.com     Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-*       SEGGER RTT * Real Time Transfer for embedded targets         *
-*                                                                    *
-**********************************************************************
-*                                                                    *
-* All rights reserved.                                               *
-*                                                                    *
-* SEGGER strongly recommends to not make any changes                 *
-* to or modify the source code of this software in order to stay     *
-* compatible with the RTT protocol and J-Link.                       *
-*                                                                    *
-* Redistribution and use in source and binary forms, with or         *
-* without modification, are permitted provided that the following    *
-* condition is met:                                                  *
-*                                                                    *
-* o Redistributions of source code must retain the above copyright   *
-*   notice, this condition and the following disclaimer.             *
-*                                                                    *
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
-* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
-* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
-* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
-* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
-* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
-* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
-* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
-* DAMAGE.                                                            *
-*                                                                    *
-**********************************************************************
----------------------------END-OF-HEADER------------------------------
-File    : SEGGER_RTT_Syscalls_SES.c
-Purpose : Reimplementation of printf, puts and __getchar using RTT
-          in SEGGER Embedded Studio.
-          To use RTT for printf output, include this file in your
-          application.
-Revision: $Rev: 18539 $
-----------------------------------------------------------------------
-*/
-#if (defined __SES_ARM) || (defined __SES_RISCV) || (defined __CROSSWORKS_ARM)
-
-#include "SEGGER_RTT.h"
-#include <stdarg.h>
-#include <stdio.h>
-#include "limits.h"
-#include "__libc.h"
-#include "__vfprintf.h"
-
-/*********************************************************************
-*
-*       Defines, configurable
-*
-**********************************************************************
-*/
-//
-// Select string formatting implementation.
-//
-// RTT printf formatting
-//  - Configurable stack usage. (SEGGER_RTT_PRINTF_BUFFER_SIZE in SEGGER_RTT_Conf.h)
-//  - No maximum string length.
-//  - Limited conversion specifiers and flags. (See SEGGER_RTT_printf.c)
-// Standard library printf formatting
-//  - Configurable formatting capabilities.
-//  - Full conversion specifier and flag support.
-//  - Maximum string length has to be known or (slightly) slower character-wise output.
-//
-// #define PRINTF_USE_SEGGER_RTT_FORMATTING    0 // Use standard library formatting
-// #define PRINTF_USE_SEGGER_RTT_FORMATTING    1 // Use RTT formatting
-//
-#ifndef   PRINTF_USE_SEGGER_RTT_FORMATTING
-  #define PRINTF_USE_SEGGER_RTT_FORMATTING    0
-#endif
-//
-// If using standard library formatting,
-// select maximum output string buffer size or character-wise output.
-//
-// #define PRINTF_BUFFER_SIZE                  0 // Use character-wise output
-// #define PRINTF_BUFFER_SIZE                128 // Default maximum string length
-//
-#ifndef   PRINTF_BUFFER_SIZE
-  #define PRINTF_BUFFER_SIZE                128
-#endif
-
-#if PRINTF_USE_SEGGER_RTT_FORMATTING  // Use SEGGER RTT formatting implementation
-/*********************************************************************
-*
-*       Function prototypes
-*
-**********************************************************************
-*/
-int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList);
-
-/*********************************************************************
-*
-*       Global functions, printf
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       printf()
-*
-*  Function description
-*    print a formatted string using RTT and SEGGER RTT formatting.
-*/
-int printf(const char *fmt,...) {
-  int     n;
-  va_list args;
-
-  va_start (args, fmt);
-  n = SEGGER_RTT_vprintf(0, fmt, &args);
-  va_end(args);
-  return n;
-}
-
-#elif PRINTF_BUFFER_SIZE == 0 // Use standard library formatting with character-wise output
-
-/*********************************************************************
-*
-*       Static functions
-*
-**********************************************************************
-*/
-static int _putchar(int x, __printf_tag_ptr ctx) {
-  (void)ctx;
-  SEGGER_RTT_Write(0, (char *)&x, 1);
-  return x;
-}
-
-/*********************************************************************
-*
-*       Global functions, printf
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       printf()
-*
-*  Function description
-*    print a formatted string character-wise, using RTT and standard
-*    library formatting.
-*/
-int printf(const char *fmt, ...) {
-  int         n;
-  va_list     args;
-  __printf_t  iod;
-
-  va_start(args, fmt);
-  iod.string    = 0;
-  iod.maxchars  = INT_MAX;
-  iod.output_fn = _putchar;
-  SEGGER_RTT_LOCK();
-  n = __vfprintf(&iod, fmt, args);
-  SEGGER_RTT_UNLOCK();
-  va_end(args);
-  return n;
-}
-
-#else // Use standard library formatting with static buffer
-
-/*********************************************************************
-*
-*       Global functions, printf
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       printf()
-*
-*  Function description
-*    print a formatted string using RTT and standard library formatting.
-*/
-int printf(const char *fmt,...) {
-  int     n;
-  char    aBuffer[PRINTF_BUFFER_SIZE];
-  va_list args;
-
-  va_start (args, fmt);
-  n = vsnprintf(aBuffer, sizeof(aBuffer), fmt, args);
-  if (n > (int)sizeof(aBuffer)) {
-    SEGGER_RTT_Write(0, aBuffer, sizeof(aBuffer));
-  } else if (n > 0) {
-    SEGGER_RTT_Write(0, aBuffer, n);
-  }
-  va_end(args);
-  return n;
-}
-#endif
-
-/*********************************************************************
-*
-*       Global functions
-*
-**********************************************************************
-*/
-/*********************************************************************
-*
-*       puts()
-*
-*  Function description
-*    print a string using RTT.
-*/
-int puts(const char *s) {
-  return SEGGER_RTT_WriteString(0, s);
-}
-
-/*********************************************************************
-*
-*       __putchar()
-*
-*  Function description
-*    Write one character via RTT.
-*/
-int __putchar(int x, __printf_tag_ptr ctx) {
-  (void)ctx;
-  SEGGER_RTT_Write(0, (char *)&x, 1);
-  return x;
-}
-
-/*********************************************************************
-*
-*       __getchar()
-*
-*  Function description
-*    Wait for and get a character via RTT.
-*/
-int __getchar() {
-  return SEGGER_RTT_WaitKey();
-}
-
-#endif
-/****** End Of File *************************************************/

From e02eee74777446a5eb5445bef6e047284932e164 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 7 Jun 2023 00:14:22 +0700
Subject: [PATCH 1784/2085] revert board flash latency to 8

---
 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h | 2 +-
 hw/bsp/stm32g4/family.c                     | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
index b1a98ba97..6b00efc8f 100644
--- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
@@ -87,7 +87,7 @@ static inline void board_clock_init(void)
   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
 
   //------------- HSI48 and CRS for USB -------------//
   RCC_OscInitTypeDef osc_hsi48 = {0};
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index 8b17c0643..5883b74b8 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -62,8 +62,7 @@ void usbpd_init(uint8_t port_num, tusb_typec_port_type_t port_type) {
   }
 
   // Enable interrupt
-  //NVIC_SetPriority(UCPD1_IRQn, 0);
-//  NVIC_EnableIRQ(UCPD1_IRQn);
+  NVIC_EnableIRQ(UCPD1_IRQn);
 }
 
 uint8_t pd_rx_buf[262];
@@ -253,7 +252,7 @@ void board_init(void)
 
   board_vbus_sense_init();
 
-#if 0
+#if 1
   // USB PD
   /* PWR register access (for disabling dead battery feature) */
   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);

From 914e82b25dea1a7ec63ea4160a2e6ebb5e59a5db Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 7 Jun 2023 09:36:37 +0700
Subject: [PATCH 1785/2085] able to receive first PD message

---
 hw/bsp/stm32g4/family.c | 49 +++++++++++++++++++++++++----------------
 1 file changed, 30 insertions(+), 19 deletions(-)

diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index 5883b74b8..6c870ac7a 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -72,7 +72,7 @@ void UCPD1_IRQHandler(void) {
   uint32_t sr = UCPD1->SR;
   sr &= UCPD1->IMR;
 
-  TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr);
+//  TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr);
 
   if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) {
     uint32_t vstate_cc[2];
@@ -83,6 +83,7 @@ void UCPD1_IRQHandler(void) {
 
     uint32_t cr = UCPD1->CR;
 
+    // TODO only support SNK for now, required highest voltage for now
     if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) {
       TU_LOG1("Attach CC1\n");
       cr &= ~UCPD_CR_PHYCCSEL;
@@ -96,10 +97,12 @@ void UCPD1_IRQHandler(void) {
       cr &= ~UCPD_CR_PHYRXEN;
     }
 
-    // Enable Interrupt
-    UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
-        /*UCPD_IMR_RXNEIE |*/ UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE |
-        UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
+    if (cr & UCPD_CR_PHYRXEN) {
+      // Enable Interrupt
+      UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
+                    UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE |
+                    UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
+    }
 
     // Enable PD RX
     UCPD1->CR = cr;
@@ -108,32 +111,40 @@ void UCPD1_IRQHandler(void) {
     UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
   }
 
+  //------------- Receive -------------//
   if (sr & UCPD_SR_RXORDDET) {
-    // SOP: Start of Packet
-    // TODO DMA later
-    uint8_t order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
-    TU_LOG1_HEX(order_set);
+    // SOP: Start of Packet.
+    // uint8_t order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
+
+    // reset count when received SOP
+    pd_rx_count = 0;
 
     // ack
     UCPD1->ICR = UCPD_ICR_RXORDDETCF;
   }
 
-  if ( sr & UCPD_SR_RXMSGEND) {
+  if (sr & UCPD_SR_RXNE) {
+    // TODO DMA later
+    do {
+      pd_rx_buf[pd_rx_count++] = UCPD1->RXDR;
+    } while (UCPD1->SR & UCPD_SR_RXNE);
+  }
+
+  if (sr & UCPD_SR_RXMSGEND) {
     // End of message
-//    uint32_t payload_size = UCPD1->RX_PAYSZ;
-//    TU_LOG1_HEX(payload_size);
-//
-//    for(uint32_t i=0; i<payload_size; i++) {
-//      pd_rx_buf[i] = UCPD1->RXDR;
-//
-//      TU_LOG1("0x%02X ", pd_rx_buf[i]);
-//    }
-//    TU_LOG1("\n");
+    uint32_t payload_size = UCPD1->RX_PAYSZ;
 
     // ack
     UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
   }
 
+  if (sr & UCPD_SR_RXOVR) {
+    TU_LOG1("RXOVR\n");
+    TU_LOG1_HEX(pd_rx_count);
+    // ack
+    UCPD1->ICR = UCPD_ICR_RXOVRCF;
+  }
+
 //  if (sr & UCPD_SR_RXNE) {
 //    uint8_t data = UCPD1->RXDR;
 //    pd_rx_buf[pd_rx_count++] = data;

From b893f1d5417adf8cf874d6b2e7946582ca37982a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 7 Jun 2023 15:10:40 +0700
Subject: [PATCH 1786/2085] inital support for usb typec and pd example

---
 examples/typec/power_delivery/CMakeLists.txt  |  32 ++++
 examples/typec/power_delivery/Makefile        |  11 ++
 examples/typec/power_delivery/only.txt        |   1 +
 examples/typec/power_delivery/src/main.c      |  90 +++++++++
 .../typec/power_delivery/src/tusb_config.h    |  79 ++++++++
 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h   |   8 +-
 hw/bsp/stm32g4/family.c                       | 133 +------------
 hw/bsp/stm32g4/family.cmake                   |   1 +
 src/CMakeLists.txt                            |   2 +
 src/common/tusb_mcu.h                         |   2 +
 src/common/tusb_types.h                       |  91 +++++++--
 src/portable/st/typec/typec_stm32.c           | 181 ++++++++++++++++++
 src/tusb.h                                    |   5 +
 src/typec/tcd.h                               |  58 ++++++
 src/typec/utcd.c                              |  48 +++++
 src/typec/utcd.h                              |  54 ++++++
 16 files changed, 651 insertions(+), 145 deletions(-)
 create mode 100644 examples/typec/power_delivery/CMakeLists.txt
 create mode 100644 examples/typec/power_delivery/Makefile
 create mode 100644 examples/typec/power_delivery/only.txt
 create mode 100644 examples/typec/power_delivery/src/main.c
 create mode 100644 examples/typec/power_delivery/src/tusb_config.h
 create mode 100644 src/portable/st/typec/typec_stm32.c
 create mode 100644 src/typec/tcd.h
 create mode 100644 src/typec/utcd.c
 create mode 100644 src/typec/utcd.h

diff --git a/examples/typec/power_delivery/CMakeLists.txt b/examples/typec/power_delivery/CMakeLists.txt
new file mode 100644
index 000000000..4ab8d5a65
--- /dev/null
+++ b/examples/typec/power_delivery/CMakeLists.txt
@@ -0,0 +1,32 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
diff --git a/examples/typec/power_delivery/Makefile b/examples/typec/power_delivery/Makefile
new file mode 100644
index 000000000..2a3d854fb
--- /dev/null
+++ b/examples/typec/power_delivery/Makefile
@@ -0,0 +1,11 @@
+include ../../make.mk
+
+INC += \
+  src \
+  $(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += $(wildcard src/*.c)
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../rules.mk
diff --git a/examples/typec/power_delivery/only.txt b/examples/typec/power_delivery/only.txt
new file mode 100644
index 000000000..657aeaac5
--- /dev/null
+++ b/examples/typec/power_delivery/only.txt
@@ -0,0 +1 @@
+mcu:STM32G4
diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
new file mode 100644
index 000000000..9d032b6bb
--- /dev/null
+++ b/examples/typec/power_delivery/src/main.c
@@ -0,0 +1,90 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+
+/* Blink pattern
+ * - 250 ms  : button is not pressed
+ * - 1000 ms : button is pressed (and hold)
+ */
+enum  {
+  BLINK_PRESSED = 250,
+  BLINK_UNPRESSED = 1000
+};
+
+static uint32_t blink_interval_ms = BLINK_UNPRESSED;
+
+void led_blinking_task(void);
+
+#define HELLO_STR   "Hello from TinyUSB\r\n"
+
+int main(void)
+{
+  board_init();
+  board_led_write(true);
+
+  tuc_init(0, TYPEC_PORT_SNK);
+
+  uint32_t start_ms = 0;
+  bool led_state = false;
+
+  while (1) {
+    led_blinking_task();
+
+//    tuc_task();
+  }
+}
+
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+void app_main(void)
+{
+  main();
+}
+#endif
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/typec/power_delivery/src/tusb_config.h b/examples/typec/power_delivery/src/tusb_config.h
new file mode 100644
index 000000000..deddcbfa4
--- /dev/null
+++ b/examples/typec/power_delivery/src/tusb_config.h
@@ -0,0 +1,79 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// special example that doesn't enable device or host stack
+// This can cause some TinyUSB API missing, this define hack to allow us to fill those API
+// to pass the compilation process
+#define tud_int_handler(x)
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+  #error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+  #define CFG_TUSB_OS               OPT_OS_NONE
+#endif
+
+#define CFG_TUD_ENABLED   0
+#define CFG_TUH_ENABLED   0
+
+// Enable TYPEC stack
+#define CFG_TUC_ENABLED   1
+
+// CFG_TUSB_DEBUG is defined by compiler in DEBUG build
+// #define CFG_TUSB_DEBUG           0
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN          __attribute__ ((aligned(4)))
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
index 6b00efc8f..e61b13170 100644
--- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
@@ -58,7 +58,7 @@
 // RCC Clock
 //--------------------------------------------------------------------+
 
-// CPU Frequency (Core Clock) is 150MHz
+// CPU Frequency (Core Clock) is 170 MHz
 static inline void board_clock_init(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
@@ -74,9 +74,9 @@ static inline void board_clock_init(void)
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
   RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
-  RCC_OscInitStruct.PLL.PLLN = 75;
-  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 85;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV10;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
   RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index 6c870ac7a..d0601b385 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -30,132 +30,6 @@
 #include "bsp/board.h"
 #include "board.h"
 
-
-//--------------------------------------------------------------------+
-// USB PD
-//--------------------------------------------------------------------+
-
-void usbpd_init(uint8_t port_num, tusb_typec_port_type_t port_type) {
-  (void) port_num;
-
-  // Initialization phase: CFG1
-  UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
-      (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) |
-      ( 0 << UCPD_CFG1_TXDMAEN_Pos) | (0 << UCPD_CFG1_RXDMAEN_Pos);
-  UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
-
-  // General programming sequence (with UCPD configured then enabled)
-  if (port_type == TUSB_TYPEC_PORT_SNK) {
-    // Enable both CC Phy
-    UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos);
-
-    // Read Voltage State on CC1 & CC2 fore initial state
-    uint32_t vstate_cc[2];
-    vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
-    vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
-
-    TU_LOG1_INT(vstate_cc[0]);
-    TU_LOG1_INT(vstate_cc[1]);
-
-    // Enable CC1 & CC2 Interrupt
-    UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE;
-  }
-
-  // Enable interrupt
-  NVIC_EnableIRQ(UCPD1_IRQn);
-}
-
-uint8_t pd_rx_buf[262];
-uint32_t pd_rx_count = 0;
-
-void UCPD1_IRQHandler(void) {
-  uint32_t sr = UCPD1->SR;
-  sr &= UCPD1->IMR;
-
-//  TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr);
-
-  if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) {
-    uint32_t vstate_cc[2];
-    vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
-    vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
-
-    TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
-
-    uint32_t cr = UCPD1->CR;
-
-    // TODO only support SNK for now, required highest voltage for now
-    if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) {
-      TU_LOG1("Attach CC1\n");
-      cr &= ~UCPD_CR_PHYCCSEL;
-      cr |= UCPD_CR_PHYRXEN;
-    } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) {
-      TU_LOG1("Attach CC2\n");
-      cr |= UCPD_CR_PHYCCSEL;
-      cr |= UCPD_CR_PHYRXEN;
-    } else {
-      TU_LOG1("Detach\n");
-      cr &= ~UCPD_CR_PHYRXEN;
-    }
-
-    if (cr & UCPD_CR_PHYRXEN) {
-      // Enable Interrupt
-      UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
-                    UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE |
-                    UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
-    }
-
-    // Enable PD RX
-    UCPD1->CR = cr;
-
-    // ack
-    UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
-  }
-
-  //------------- Receive -------------//
-  if (sr & UCPD_SR_RXORDDET) {
-    // SOP: Start of Packet.
-    // uint8_t order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
-
-    // reset count when received SOP
-    pd_rx_count = 0;
-
-    // ack
-    UCPD1->ICR = UCPD_ICR_RXORDDETCF;
-  }
-
-  if (sr & UCPD_SR_RXNE) {
-    // TODO DMA later
-    do {
-      pd_rx_buf[pd_rx_count++] = UCPD1->RXDR;
-    } while (UCPD1->SR & UCPD_SR_RXNE);
-  }
-
-  if (sr & UCPD_SR_RXMSGEND) {
-    // End of message
-    uint32_t payload_size = UCPD1->RX_PAYSZ;
-
-    // ack
-    UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
-  }
-
-  if (sr & UCPD_SR_RXOVR) {
-    TU_LOG1("RXOVR\n");
-    TU_LOG1_HEX(pd_rx_count);
-    // ack
-    UCPD1->ICR = UCPD_ICR_RXOVRCF;
-  }
-
-//  if (sr & UCPD_SR_RXNE) {
-//    uint8_t data = UCPD1->RXDR;
-//    pd_rx_buf[pd_rx_count++] = data;
-//    TU_LOG1_HEX(data);
-//  }
-
-//  else {
-//    TU_LOG_LOCATION();
-//  }
-}
-
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
@@ -174,6 +48,11 @@ void USBWakeUp_IRQHandler(void)
   tud_int_handler(0);
 }
 
+// USB PD
+void UCPD1_IRQHandler(void) {
+  tuc_int_handler(0);
+}
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -274,8 +153,6 @@ void board_init(void)
   // Default CC1/CC2 is PB4/PB6
   // PB4   ------> UCPD1_CC2
   // PB6   ------> UCPD1_CC1
-
-  usbpd_init(0, TUSB_TYPEC_PORT_SNK);
 #endif
 
 }
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index 2c10a9769..618563f66 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -90,6 +90,7 @@ function(family_configure_example TARGET)
   target_sources(${TARGET} PUBLIC
     # TinyUSB Port
     ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    ${TOP}/src/portable/st/typec/typec_stm32.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 3dbd72d61..ce4486ecd 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -32,6 +32,8 @@ function(add_tinyusb TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/hid/hid_host.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_host.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_host.c
+    # typec
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/typec/utcd.c
     )
   target_include_directories(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 48f765674..bb4483f7d 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -199,6 +199,8 @@
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
+  #define TUP_USBIP_TYPEC_STM32
+
   #define TUP_DCD_ENDPOINT_MAX    8
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32G0)
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 7b82c51d9..e6b350a40 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -232,16 +232,6 @@ enum {
 
 #define TUSB_DESC_CONFIG_POWER_MA(x)  ((x)/2)
 
-//--------------------------------------------------------------------+
-// TYPE-C
-//--------------------------------------------------------------------+
-
-typedef enum {
-  TUSB_TYPEC_PORT_SRC,
-  TUSB_TYPEC_PORT_SNK,
-  TUSB_TYPEC_PORT_DRP
-} tusb_typec_port_type_t;
-
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
@@ -487,9 +477,9 @@ typedef struct TU_ATTR_PACKED
   uint16_t bcdDFUVersion;
 } tusb_desc_dfu_functional_t;
 
-/*------------------------------------------------------------------*/
-/* Types
- *------------------------------------------------------------------*/
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
 typedef struct TU_ATTR_PACKED{
   union {
     struct TU_ATTR_PACKED {
@@ -509,6 +499,81 @@ typedef struct TU_ATTR_PACKED{
 
 TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 
+//--------------------------------------------------------------------+
+// TYPE-C
+//--------------------------------------------------------------------+
+
+typedef enum {
+  TYPEC_PORT_SRC,
+  TYPEC_PORT_SNK,
+  TYPEC_PORT_DRP
+} typec_port_type_t;
+
+typedef enum {
+  TYPEC_MSG_CTRL_RESERVED = 0,            // 0b00000: 0
+  TYPEC_MSG_CTRL_GOOD_CRC,                // 0b00001: 1
+  TYPEC_MSG_CTRL_GO_TO_MIN,               // 0b00010: 2
+  TYPEC_MSG_CTRL_ACCEPT,                  // 0b00011: 3
+  TYPEC_MSG_CTRL_REJECT,                  // 0b00100: 4
+  TYPEC_MSG_CTRL_PING,                    // 0b00101: 5
+  TYPEC_MSG_CTRL_PS_RDY,                  // 0b00110: 6
+  TYPEC_MSG_CTRL_GET_SOURCE_CAP,          // 0b00111: 7
+  TYPEC_MSG_CTRL_GET_SINK_CAP,            // 0b01000: 8
+  TYPEC_MSG_CTRL_DR_SWAP,                 // 0b01001: 9
+  TYPEC_MSG_CTRL_PR_SWAP,                 // 0b01010: 10
+  TYPEC_MSG_CTRL_VCONN_SWAP,              // 0b01011: 11
+  TYPEC_MSG_CTRL_WAIT,                    // 0b01100: 12
+  TYPEC_MSG_CTRL_SOFT_RESET,              // 0b01101: 13
+  TYPEC_MSG_CTRL_DATA_RESET,              // 0b01110: 14
+  TYPEC_MSG_CTRL_DATA_RESET_COMPLETE,     // 0b01111: 15
+  TYPEC_MSG_CTRL_NOT_SUPPORTED,           // 0b10000: 16
+  TYPEC_MSG_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17
+  TYPEC_MSG_CTRL_GET_STATUS,              // 0b10010: 18
+  TYPEC_MSG_CTRL_FR_SWAP,                 // 0b10011: 19
+  TYPEC_MSG_CTRL_GET_PPS_STATUS,          // 0b10100: 20
+  TYPEC_MSG_CTRL_GET_COUNTRY_CODES,       // 0b10101: 21
+  TYPEC_MSG_CTRL_GET_SINK_CAP_EXTENDED,   // 0b10110: 22
+  TYPEC_MSG_CTRL_GET_SOURCE_INFO,         // 0b10111: 23
+  TYPEC_MSG_CTRL_REVISION,                // 0b11000: 24
+} typec_msg_ctrl_type_t;
+
+typedef enum {
+  TYPEC_MSG_DATA_RESERVED = 0,     // 0b00000: 0
+  TYPEC_MSG_DATA_SOURCE_CAP,       // 0b00001: 1
+  TYPEC_MSG_DATA_REQUEST,          // 0b00010: 2
+  TYPEC_MSG_DATA_BIST,             // 0b00011: 3
+  TYPEC_MSG_DATA_SINK_CAP,         // 0b00100: 4
+  TYPEC_MSG_DATA_BATTERY_STATUS,   // 0b00101: 5
+  TYPEC_MSG_DATA_ALERT,            // 0b00110: 6
+  TYPEC_MSG_DATA_GET_COUNTRY_INFO, // 0b00111: 7
+  TYPEC_MSG_DATA_ENTER_USB,        // 0b01000: 8
+  TYPEC_MSG_DATA_EPR_REQUEST,      // 0b01001: 9
+  TYPEC_MSG_DATA_EPR_MODE,         // 0b01010: 10
+  TYPEC_MSG_DATA_SRC_INFO,         // 0b01011: 11
+  TYPEC_MSG_DATA_REVISION,         // 0b01100: 12
+  TYPEC_MSG_DATA_RESERVED_13,      // 0b01101: 13
+  TYPEC_MSG_DATA_RESERVED_14,      // 0b01110: 14
+  TYPEC_MSG_DATA_VENDOR_DEFINED,   // 0b01111: 15
+} typec_msg_data_type_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint16_t msg_type   : 5; // [0:4]
+  uint16_t data_role  : 1; // [5] SOP only
+  uint16_t specs_rev  : 2; // [6:7]
+  uint16_t power_role : 1; // [8] SOP only
+  uint16_t msg_id     : 3; // [9:11]
+  uint16_t n_data_obj : 3; // [12:14]
+  uint16_t extended   : 1; // [15]
+} tusb_typec_message_header_t;
+
+typedef struct TU_ATTR_PACKED {
+  uint16_t data_size     : 9; // [0:8]
+  uint16_t reserved      : 1; // [9]
+  uint16_t request_chunk : 1; // [10]
+  uint16_t chunk_number  : 4; // [11:14]
+  uint16_t chunked       : 1; // [15]
+} tusb_typec_message_header_extended_t;
+
 
 TU_ATTR_PACKED_END  // End of all packed definitions
 TU_ATTR_BIT_FIELD_ORDER_END
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
new file mode 100644
index 000000000..fd029473d
--- /dev/null
+++ b/src/portable/st/typec/typec_stm32.c
@@ -0,0 +1,181 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "tusb_option.h"
+#include "typec/tcd.h"
+
+#if CFG_TUC_ENABLED && defined(TUP_USBIP_TYPEC_STM32)
+
+#include "common/tusb_common.h"
+
+#include "stm32g4xx.h"
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+uint8_t pd_rx_buf[262];
+uint32_t pd_rx_count = 0;
+uint8_t pd_rx_order_set;
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool tcd_init(uint8_t rhport, typec_port_type_t port_type) {
+  (void) rhport;
+
+  // Initialization phase: CFG1
+  UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
+                (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) |
+                (0 << UCPD_CFG1_TXDMAEN_Pos) | (0 << UCPD_CFG1_RXDMAEN_Pos);
+  UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
+
+  // General programming sequence (with UCPD configured then enabled)
+  if (port_type == TYPEC_PORT_SNK) {
+    // Enable both CC Phy
+    UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos);
+
+    // Read Voltage State on CC1 & CC2 fore initial state
+    uint32_t vstate_cc[2];
+    vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
+    vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
+
+    TU_LOG1_INT(vstate_cc[0]);
+    TU_LOG1_INT(vstate_cc[1]);
+
+    // Enable CC1 & CC2 Interrupt
+    UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE;
+  }
+
+  return true;
+}
+
+// Enable interrupt
+void tcd_int_enable (uint8_t rhport) {
+  (void) rhport;
+  NVIC_EnableIRQ(UCPD1_IRQn);
+}
+
+// Disable interrupt
+void tcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+  NVIC_DisableIRQ(UCPD1_IRQn);
+}
+
+void tcd_int_handler(uint8_t rhport) {
+  (void) rhport;
+
+  uint32_t sr = UCPD1->SR;
+  sr &= UCPD1->IMR;
+
+//  TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr);
+
+  if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) {
+    uint32_t vstate_cc[2];
+    vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
+    vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
+
+    TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
+
+    uint32_t cr = UCPD1->CR;
+
+    // TODO only support SNK for now, required highest voltage for now
+    if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) {
+      TU_LOG1("Attach CC1\n");
+      cr &= ~UCPD_CR_PHYCCSEL;
+      cr |= UCPD_CR_PHYRXEN;
+    } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) {
+      TU_LOG1("Attach CC2\n");
+      cr |= UCPD_CR_PHYCCSEL;
+      cr |= UCPD_CR_PHYRXEN;
+    } else {
+      TU_LOG1("Detach\n");
+      cr &= ~UCPD_CR_PHYRXEN;
+    }
+
+    if (cr & UCPD_CR_PHYRXEN) {
+      // Enable Interrupt
+      UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
+                    UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE |
+                    UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
+    }
+
+    // Enable PD RX
+    UCPD1->CR = cr;
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
+  }
+
+  //------------- Receive -------------//
+  if (sr & UCPD_SR_RXORDDET) {
+    // SOP: Start of Packet.
+    pd_rx_order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
+
+    // reset count when received SOP
+    pd_rx_count = 0;
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_RXORDDETCF;
+  }
+
+  if (sr & UCPD_SR_RXNE) {
+    // TODO DMA later
+    do {
+      pd_rx_buf[pd_rx_count++] = UCPD1->RXDR;
+    } while (UCPD1->SR & UCPD_SR_RXNE);
+  }
+
+  if (sr & UCPD_SR_RXMSGEND) {
+    // End of message
+
+    // Skip if CRC failed
+    if (!(sr & UCPD_SR_RXERR)) {
+      uint32_t payload_size = UCPD1->RX_PAYSZ;
+      TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count);
+    }
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
+  }
+
+  if (sr & UCPD_SR_RXOVR) {
+    TU_LOG1("RXOVR\n");
+    TU_LOG1_HEX(pd_rx_count);
+    // ack
+    UCPD1->ICR = UCPD_ICR_RXOVRCF;
+  }
+
+//  if (sr & UCPD_SR_RXNE) {
+//    uint8_t data = UCPD1->RXDR;
+//    pd_rx_buf[pd_rx_count++] = data;
+//    TU_LOG1_HEX(data);
+//  }
+
+//  else {
+//    TU_LOG_LOCATION();
+//  }
+}
+
+#endif
diff --git a/src/tusb.h b/src/tusb.h
index b776d7d01..0b87b1969 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -40,6 +40,11 @@
 
 #include "class/hid/hid.h"
 
+//------------- TypeC -------------//
+#if CFG_TUC_ENABLED
+  #include "typec/utcd.h"
+#endif
+
 //------------- HOST -------------//
 #if CFG_TUH_ENABLED
   #include "host/usbh.h"
diff --git a/src/typec/tcd.h b/src/typec/tcd.h
new file mode 100644
index 000000000..397c0ac83
--- /dev/null
+++ b/src/typec/tcd.h
@@ -0,0 +1,58 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (thach@tinyusb.org) for Adafruit Industries
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_TCD_H_
+#define _TUSB_TCD_H_
+
+#include "common/tusb_common.h"
+#include "osal/osal.h"
+#include "common/tusb_fifo.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// Initialize controller
+bool tcd_init(uint8_t rhport, typec_port_type_t port_type);
+
+// Enable interrupt
+void tcd_int_enable (uint8_t rhport);
+
+// Disable interrupt
+void tcd_int_disable(uint8_t rhport);
+
+// Interrupt Handler
+void tcd_int_handler(uint8_t rhport);
+
+#endif
diff --git a/src/typec/utcd.c b/src/typec/utcd.c
new file mode 100644
index 000000000..baa95fbe5
--- /dev/null
+++ b/src/typec/utcd.c
@@ -0,0 +1,48 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (thach@tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUC_ENABLED
+
+#include "tcd.h"
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool tuc_init(uint8_t rhport, typec_port_type_t port_type) {
+  TU_ASSERT(tcd_init(rhport, port_type));
+  tcd_int_enable(rhport);
+  return true;
+}
+
+#endif
diff --git a/src/typec/utcd.h b/src/typec/utcd.h
new file mode 100644
index 000000000..2f9b84fb7
--- /dev/null
+++ b/src/typec/utcd.h
@@ -0,0 +1,54 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_UTCD_H_
+#define _TUSB_UTCD_H_
+
+#include "common/tusb_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Application API
+//--------------------------------------------------------------------+
+
+// init typec stack
+bool tuc_init(uint8_t rhport, typec_port_type_t port_type);
+
+#ifndef _TUSB_TCD_H_
+extern void tcd_int_handler(uint8_t rhport);
+#endif
+
+// Interrupt handler, name alias to TCD
+#define tuc_int_handler tcd_int_handler
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+#endif

From 8bb012e50b39d9ed05c80509e69f9e26d463367c Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Wed, 7 Jun 2023 12:01:59 +0200
Subject: [PATCH 1787/2085] fix(RA): static assert RUSB2 register

---
 src/portable/renesas/rusb2/rusb2_type.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index d80ecc62e..90ba4f012 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -1599,6 +1599,7 @@ TU_ATTR_BIT_FIELD_ORDER_END
 //--------------------------------------------------------------------+
 
 TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size");
+TU_VERIFY_STATIC(sizeof(RUSB2_REG_t) == 1032, "incorrect size");
 
 TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSCFG     ) == 0x00000000, "incorrect offset");
 TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BUSWAIT    ) == 0x00000002, "incorrect offset");

From 9b7dee563e83a548f0d0fb68dd991a868a6427c9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 7 Jun 2023 18:57:48 +0700
Subject: [PATCH 1788/2085] able to response with good crc

---
 examples/typec/power_delivery/src/main.c |   2 +-
 src/common/tusb_mcu.h                    |   5 +
 src/common/tusb_types.h                  | 112 ++++++++++++----------
 src/device/usbd.c                        |  10 ++
 src/host/usbh.c                          |   2 +-
 src/portable/st/typec/typec_stm32.c      | 113 +++++++++++++++++++----
 src/typec/tcd.h                          |  15 ++-
 src/typec/utcd.c                         |  57 +++++++++++-
 src/typec/utcd.h                         |  16 +++-
 9 files changed, 257 insertions(+), 75 deletions(-)

diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
index 9d032b6bb..648345a55 100644
--- a/examples/typec/power_delivery/src/main.c
+++ b/examples/typec/power_delivery/src/main.c
@@ -54,7 +54,7 @@ int main(void)
   board_init();
   board_led_write(true);
 
-  tuc_init(0, TYPEC_PORT_SNK);
+  tuc_init(0, TUSB_TYPEC_PORT_SNK);
 
   uint32_t start_ms = 0;
   bool led_state = false;
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index bb4483f7d..f89467e75 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -197,12 +197,17 @@
   #define TUP_DCD_ENDPOINT_MAX    9
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32G4)
+  // Device controller
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
+
+  // TypeC controller
   #define TUP_USBIP_TYPEC_STM32
 
   #define TUP_DCD_ENDPOINT_MAX    8
 
+  #define TUP_TYPEC_RHPORTS_NUM 1
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32G0)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index e6b350a40..c92320e5c 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -504,67 +504,75 @@ TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 //--------------------------------------------------------------------+
 
 typedef enum {
-  TYPEC_PORT_SRC,
-  TYPEC_PORT_SNK,
-  TYPEC_PORT_DRP
-} typec_port_type_t;
+  TUSB_TYPEC_PORT_SRC,
+  TUSB_TYPEC_PORT_SNK,
+  TUSB_TYPEC_PORT_DRP
+} tusb_typec_port_type_t;
 
 typedef enum {
-  TYPEC_MSG_CTRL_RESERVED = 0,            // 0b00000: 0
-  TYPEC_MSG_CTRL_GOOD_CRC,                // 0b00001: 1
-  TYPEC_MSG_CTRL_GO_TO_MIN,               // 0b00010: 2
-  TYPEC_MSG_CTRL_ACCEPT,                  // 0b00011: 3
-  TYPEC_MSG_CTRL_REJECT,                  // 0b00100: 4
-  TYPEC_MSG_CTRL_PING,                    // 0b00101: 5
-  TYPEC_MSG_CTRL_PS_RDY,                  // 0b00110: 6
-  TYPEC_MSG_CTRL_GET_SOURCE_CAP,          // 0b00111: 7
-  TYPEC_MSG_CTRL_GET_SINK_CAP,            // 0b01000: 8
-  TYPEC_MSG_CTRL_DR_SWAP,                 // 0b01001: 9
-  TYPEC_MSG_CTRL_PR_SWAP,                 // 0b01010: 10
-  TYPEC_MSG_CTRL_VCONN_SWAP,              // 0b01011: 11
-  TYPEC_MSG_CTRL_WAIT,                    // 0b01100: 12
-  TYPEC_MSG_CTRL_SOFT_RESET,              // 0b01101: 13
-  TYPEC_MSG_CTRL_DATA_RESET,              // 0b01110: 14
-  TYPEC_MSG_CTRL_DATA_RESET_COMPLETE,     // 0b01111: 15
-  TYPEC_MSG_CTRL_NOT_SUPPORTED,           // 0b10000: 16
-  TYPEC_MSG_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17
-  TYPEC_MSG_CTRL_GET_STATUS,              // 0b10010: 18
-  TYPEC_MSG_CTRL_FR_SWAP,                 // 0b10011: 19
-  TYPEC_MSG_CTRL_GET_PPS_STATUS,          // 0b10100: 20
-  TYPEC_MSG_CTRL_GET_COUNTRY_CODES,       // 0b10101: 21
-  TYPEC_MSG_CTRL_GET_SINK_CAP_EXTENDED,   // 0b10110: 22
-  TYPEC_MSG_CTRL_GET_SOURCE_INFO,         // 0b10111: 23
-  TYPEC_MSG_CTRL_REVISION,                // 0b11000: 24
-} typec_msg_ctrl_type_t;
+  TUSB_PD_CTRL_RESERVED = 0,            // 0b00000: 0
+  TUSB_PD_CTRL_GOOD_CRC,                // 0b00001: 1
+  TUSB_PD_CTRL_GO_TO_MIN,               // 0b00010: 2
+  TUSB_PD_CTRL_ACCEPT,                  // 0b00011: 3
+  TUSB_PD_CTRL_REJECT,                  // 0b00100: 4
+  TUSB_PD_CTRL_PING,                    // 0b00101: 5
+  TUSB_PD_CTRL_PS_RDY,                  // 0b00110: 6
+  TUSB_PD_CTRL_GET_SOURCE_CAP,          // 0b00111: 7
+  TUSB_PD_CTRL_GET_SINK_CAP,            // 0b01000: 8
+  TUSB_PD_CTRL_DR_SWAP,                 // 0b01001: 9
+  TUSB_PD_CTRL_PR_SWAP,                 // 0b01010: 10
+  TUSB_PD_CTRL_VCONN_SWAP,              // 0b01011: 11
+  TUSB_PD_CTRL_WAIT,                    // 0b01100: 12
+  TUSB_PD_CTRL_SOFT_RESET,              // 0b01101: 13
+  TUSB_PD_CTRL_DATA_RESET,              // 0b01110: 14
+  TUSB_PD_CTRL_DATA_RESET_COMPLETE,     // 0b01111: 15
+  TUSB_PD_CTRL_NOT_SUPPORTED,           // 0b10000: 16
+  TUSB_PD_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17
+  TUSB_PD_CTRL_GET_STATUS,              // 0b10010: 18
+  TUSB_PD_CTRL_FR_SWAP,                 // 0b10011: 19
+  TUSB_PD_CTRL_GET_PPS_STATUS,          // 0b10100: 20
+  TUSB_PD_CTRL_GET_COUNTRY_CODES,       // 0b10101: 21
+  TUSB_PD_CTRL_GET_SINK_CAP_EXTENDED,   // 0b10110: 22
+  TUSB_PD_CTRL_GET_SOURCE_INFO,         // 0b10111: 23
+  TUSB_PD_CTRL_REVISION,                // 0b11000: 24
+} tusb_pd_ctrl_type_t;
 
 typedef enum {
-  TYPEC_MSG_DATA_RESERVED = 0,     // 0b00000: 0
-  TYPEC_MSG_DATA_SOURCE_CAP,       // 0b00001: 1
-  TYPEC_MSG_DATA_REQUEST,          // 0b00010: 2
-  TYPEC_MSG_DATA_BIST,             // 0b00011: 3
-  TYPEC_MSG_DATA_SINK_CAP,         // 0b00100: 4
-  TYPEC_MSG_DATA_BATTERY_STATUS,   // 0b00101: 5
-  TYPEC_MSG_DATA_ALERT,            // 0b00110: 6
-  TYPEC_MSG_DATA_GET_COUNTRY_INFO, // 0b00111: 7
-  TYPEC_MSG_DATA_ENTER_USB,        // 0b01000: 8
-  TYPEC_MSG_DATA_EPR_REQUEST,      // 0b01001: 9
-  TYPEC_MSG_DATA_EPR_MODE,         // 0b01010: 10
-  TYPEC_MSG_DATA_SRC_INFO,         // 0b01011: 11
-  TYPEC_MSG_DATA_REVISION,         // 0b01100: 12
-  TYPEC_MSG_DATA_RESERVED_13,      // 0b01101: 13
-  TYPEC_MSG_DATA_RESERVED_14,      // 0b01110: 14
-  TYPEC_MSG_DATA_VENDOR_DEFINED,   // 0b01111: 15
-} typec_msg_data_type_t;
+  TUSB_PD_DATA_RESERVED = 0,     // 0b00000: 0
+  TUSB_PD_DATA_SOURCE_CAP,       // 0b00001: 1
+  TUSB_PD_DATA_REQUEST,          // 0b00010: 2
+  TUSB_PD_DATA_BIST,             // 0b00011: 3
+  TUSB_PD_DATA_SINK_CAP,         // 0b00100: 4
+  TUSB_PD_DATA_BATTERY_STATUS,   // 0b00101: 5
+  TUSB_PD_DATA_ALERT,            // 0b00110: 6
+  TUSB_PD_DATA_GET_COUNTRY_INFO, // 0b00111: 7
+  TUSB_PD_DATA_ENTER_USB,        // 0b01000: 8
+  TUSB_PD_DATA_EPR_REQUEST,      // 0b01001: 9
+  TUSB_PD_DATA_EPR_MODE,         // 0b01010: 10
+  TUSB_PD_DATA_SRC_INFO,         // 0b01011: 11
+  TUSB_PD_DATA_REVISION,         // 0b01100: 12
+  TUSB_PD_DATA_RESERVED_13,      // 0b01101: 13
+  TUSB_PD_DATA_RESERVED_14,      // 0b01110: 14
+  TUSB_PD_DATA_VENDOR_DEFINED,   // 0b01111: 15
+} tusb_pd_data_type_t;
+
+enum {
+  TUSB_PD_REV10	= 0x0,
+  TUSB_PD_REV20	= 0x1,
+  TUSB_PD_REV30	= 0x2,
+};
 
 typedef struct TU_ATTR_PACKED {
   uint16_t msg_type   : 5; // [0:4]
-  uint16_t data_role  : 1; // [5] SOP only
+  uint16_t data_role  : 1; // [5] SOP only: 0 UFP, 1 DFP
   uint16_t specs_rev  : 2; // [6:7]
-  uint16_t power_role : 1; // [8] SOP only
+  uint16_t power_role : 1; // [8] SOP only: 0 Sink, 1 Source
   uint16_t msg_id     : 3; // [9:11]
   uint16_t n_data_obj : 3; // [12:14]
   uint16_t extended   : 1; // [15]
-} tusb_typec_message_header_t;
+} tusb_pd_header_t;
+
+TU_VERIFY_STATIC( sizeof(tusb_pd_header_t) == 2, "size is not correct");
 
 typedef struct TU_ATTR_PACKED {
   uint16_t data_size     : 9; // [0:8]
@@ -572,7 +580,9 @@ typedef struct TU_ATTR_PACKED {
   uint16_t request_chunk : 1; // [10]
   uint16_t chunk_number  : 4; // [11:14]
   uint16_t chunked       : 1; // [15]
-} tusb_typec_message_header_extended_t;
+} tusb_pd_header_extended_t;
+
+TU_VERIFY_STATIC( sizeof(tusb_pd_header_extended_t) == 2, "size is not correct");
 
 
 TU_ATTR_PACKED_END  // End of all packed definitions
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 409a5ec10..44c2530ce 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -252,9 +252,19 @@ static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
     drvid -= _app_driver_count;
   }
 
+  // when there is no built-in drivers BUILTIN_DRIVER_COUNT = 0 will cause -Wtype-limits warning
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wtype-limits"
+#endif
+
   // Built-in drivers
   if (drvid < BUILTIN_DRIVER_COUNT) return &_usbd_driver[drvid];
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
   return NULL;
 }
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 6159044ab..98e959a12 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -724,7 +724,7 @@ uint8_t* usbh_get_enum_buf(void)
 
 void usbh_int_set(bool enabled)
 {
-  // TODO all host controller if multiple is used
+  // TODO all host controller if multiple are used since they shared the same event queue
   if (enabled)
   {
     hcd_int_enable(_usbh_controller);
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
index fd029473d..79f37b729 100644
--- a/src/portable/st/typec/typec_stm32.c
+++ b/src/portable/st/typec/typec_stm32.c
@@ -29,20 +29,43 @@
 
 #include "common/tusb_common.h"
 
-#include "stm32g4xx.h"
-
-//--------------------------------------------------------------------+
-//
-//--------------------------------------------------------------------+
-uint8_t pd_rx_buf[262];
-uint32_t pd_rx_count = 0;
-uint8_t pd_rx_order_set;
+#if CFG_TUSB_MCU == OPT_MCU_STM32G4
+  #include "stm32g4xx.h"
+#else
+  #error "Unsupported STM32 family"
+#endif
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
-bool tcd_init(uint8_t rhport, typec_port_type_t port_type) {
+#define PHY_SYNC1 0x18u
+#define PHY_SYNC2 0x11u
+#define PHY_SYNC3 0x06u
+#define PHY_RST1  0x07u
+#define PHY_RST2  0x19u
+#define PHY_EOP   0x0Du
+
+#define PHY_ORDERED_SET_SOP          (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC2<<15u)) // SOP Ordered set coding
+#define PHY_ORDERED_SET_SOP_P        (PHY_SYNC1 | (PHY_SYNC1<<5u) | (PHY_SYNC3<<10u) | (PHY_SYNC3<<15u)) // SOP' Ordered set coding
+#define PHY_ORDERED_SET_SOP_PP       (PHY_SYNC1 | (PHY_SYNC3<<5u) | (PHY_SYNC1<<10u) | (PHY_SYNC3<<15u)) // SOP'' Ordered set coding
+#define PHY_ORDERED_SET_HARD_RESET   (PHY_RST1  | (PHY_RST1<<5u)  | (PHY_RST1<<10u)  | (PHY_RST2<<15u )) // Hard Reset Ordered set coding
+#define PHY_ORDERED_SET_CABLE_RESET  (PHY_RST1  | (PHY_SYNC1<<5u) | (PHY_RST1<<10u)  | (PHY_SYNC3<<15u)) // Cable Reset Ordered set coding
+#define PHY_ORDERED_SET_SOP_P_DEBUG  (PHY_SYNC1 | (PHY_RST2<<5u)  | (PHY_RST2<<10u)  | (PHY_SYNC3<<15u)) // SOP' Debug Ordered set coding
+#define PHY_ORDERED_SET_SOP_PP_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u)  | (PHY_SYNC3<<10u) | (PHY_SYNC2<<15u)) // SOP'' Debug Ordered set coding
+
+
+static uint8_t rx_buf[262] TU_ATTR_ALIGNED(4);
+static uint32_t rx_count = 0;
+
+static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4);
+static uint32_t tx_count;
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
   (void) rhport;
 
   // Initialization phase: CFG1
@@ -52,7 +75,7 @@ bool tcd_init(uint8_t rhport, typec_port_type_t port_type) {
   UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
 
   // General programming sequence (with UCPD configured then enabled)
-  if (port_type == TYPEC_PORT_SNK) {
+  if (port_type == TUSB_TYPEC_PORT_SNK) {
     // Enable both CC Phy
     UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos);
 
@@ -83,6 +106,19 @@ void tcd_int_disable(uint8_t rhport) {
   NVIC_DisableIRQ(UCPD1_IRQn);
 }
 
+bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
+  (void) rhport;
+
+  return true;
+}
+
+bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes) {
+  (void) rhport;
+  (void) buffer;
+  (void) total_bytes;
+  return false;
+}
+
 void tcd_int_handler(uint8_t rhport) {
   (void) rhport;
 
@@ -116,7 +152,7 @@ void tcd_int_handler(uint8_t rhport) {
 
     if (cr & UCPD_CR_PHYRXEN) {
       // Enable Interrupt
-      UCPD1->IMR |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
+      UCPD1->IMR |= UCPD_IMR_TXISIE | UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
                     UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE |
                     UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
     }
@@ -128,13 +164,13 @@ void tcd_int_handler(uint8_t rhport) {
     UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
   }
 
-  //------------- Receive -------------//
+  //------------- RX -------------//
   if (sr & UCPD_SR_RXORDDET) {
     // SOP: Start of Packet.
-    pd_rx_order_set = UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
+    // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
 
     // reset count when received SOP
-    pd_rx_count = 0;
+    rx_count = 0;
 
     // ack
     UCPD1->ICR = UCPD_ICR_RXORDDETCF;
@@ -143,17 +179,38 @@ void tcd_int_handler(uint8_t rhport) {
   if (sr & UCPD_SR_RXNE) {
     // TODO DMA later
     do {
-      pd_rx_buf[pd_rx_count++] = UCPD1->RXDR;
+      rx_buf[rx_count++] = UCPD1->RXDR;
     } while (UCPD1->SR & UCPD_SR_RXNE);
+
+    // no ack needed
   }
 
+  // End of message
   if (sr & UCPD_SR_RXMSGEND) {
-    // End of message
 
     // Skip if CRC failed
     if (!(sr & UCPD_SR_RXERR)) {
       uint32_t payload_size = UCPD1->RX_PAYSZ;
-      TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count);
+      // TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count);
+
+      tusb_pd_header_t const* rx_header = (tusb_pd_header_t const*) rx_buf;
+      (*(tusb_pd_header_t*) tx_buf) = (tusb_pd_header_t) {
+          .msg_type = TUSB_PD_CTRL_GOOD_CRC,
+          .data_role = 0, // UFP
+          .specs_rev = TUSB_PD_REV30,
+          .power_role = 0, // Sink
+          .msg_id = rx_header->msg_id,
+          .n_data_obj = 0,
+          .extended = 0
+      };
+      tx_count = 0;
+
+      // response with good crc
+      UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
+      UCPD1->TX_PAYSZ = 2;
+      UCPD1->CR |= UCPD_CR_TXSEND; // will trigger TXIS interrupt
+
+      // notify stack after good crc ?
     }
 
     // ack
@@ -162,11 +219,31 @@ void tcd_int_handler(uint8_t rhport) {
 
   if (sr & UCPD_SR_RXOVR) {
     TU_LOG1("RXOVR\n");
-    TU_LOG1_HEX(pd_rx_count);
+    TU_LOG1_HEX(rx_count);
     // ack
     UCPD1->ICR = UCPD_ICR_RXOVRCF;
   }
 
+  //------------- TX -------------//
+  if (sr & UCPD_SR_TXIS) {
+    // TU_LOG1("TXIS\n");
+
+    // TODO DMA later
+    do {
+      UCPD1->TXDR = tx_buf[tx_count++];
+    } while (UCPD1->SR & UCPD_SR_TXIS);
+
+    // no ack needed
+  }
+
+  if (sr & UCPD_SR_TXMSGSENT) {
+    // all byte sent
+    TU_LOG1("TXMSGSENT\n");
+
+    // ack
+    UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
+  }
+
 //  if (sr & UCPD_SR_RXNE) {
 //    uint8_t data = UCPD1->RXDR;
 //    pd_rx_buf[pd_rx_count++] = data;
diff --git a/src/typec/tcd.h b/src/typec/tcd.h
index 397c0ac83..e823bf8d7 100644
--- a/src/typec/tcd.h
+++ b/src/typec/tcd.h
@@ -38,13 +38,19 @@ extern "C" {
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
+typedef struct {
+  uint8_t rhport;
+  uint8_t event_id;
+
+
+} tcd_event_t;;
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
 // Initialize controller
-bool tcd_init(uint8_t rhport, typec_port_type_t port_type);
+bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type);
 
 // Enable interrupt
 void tcd_int_enable (uint8_t rhport);
@@ -55,4 +61,11 @@ void tcd_int_disable(uint8_t rhport);
 // Interrupt Handler
 void tcd_int_handler(uint8_t rhport);
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes);
+bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes);
+
 #endif
diff --git a/src/typec/utcd.c b/src/typec/utcd.c
index baa95fbe5..b5f9965fe 100644
--- a/src/typec/utcd.c
+++ b/src/typec/utcd.c
@@ -29,20 +29,75 @@
 #if CFG_TUC_ENABLED
 
 #include "tcd.h"
+#include "utcd.h"
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
+// Debug level of USBD
+#define UTCD_DEBUG   2
+#define TU_LOG_UTCD(...)   TU_LOG(UTCD_DEBUG, __VA_ARGS__)
+
+// Event queue
+// utcd_int_set() is used as mutex in OS NONE config
+void utcd_int_set(bool enabled);
+OSAL_QUEUE_DEF(utcd_int_set, utcd_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t);
+tu_static osal_queue_t utcd_q;
+
+// if stack is initialized
+static bool utcd_inited = false;
+
+// if port is initialized
+static bool port_inited[TUP_TYPEC_RHPORTS_NUM];
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
+bool tuc_inited(uint8_t rhport) {
+  return utcd_inited && port_inited[rhport];
+}
+
+bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
+  // Initialize stack
+  if (!utcd_inited) {
+    tu_memclr(port_inited, sizeof(port_inited));
+
+    utcd_q = osal_queue_create(&utcd_qdef);
+    TU_ASSERT(utcd_q != NULL);
+
+    utcd_inited = true;
+  }
+
+  // skip if port already initialized
+  if ( port_inited[rhport] ) {
+    return true;
+  }
+
+  TU_LOG_UTCD("UTCD init on port %u\r\n", rhport);
 
-bool tuc_init(uint8_t rhport, typec_port_type_t port_type) {
   TU_ASSERT(tcd_init(rhport, port_type));
   tcd_int_enable(rhport);
+
+  port_inited[rhport] = true;
   return true;
 }
 
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+void utcd_int_set(bool enabled) {
+  // Disable all controllers since they shared the same event queue
+  for (uint8_t p = 0; p < TUP_TYPEC_RHPORTS_NUM; p++) {
+    if ( port_inited[p] ) {
+      if (enabled) {
+        tcd_int_enable(p);
+      }else {
+        tcd_int_disable(p);
+      }
+    }
+  }
+}
+
 #endif
diff --git a/src/typec/utcd.h b/src/typec/utcd.h
index 2f9b84fb7..06a62ef23 100644
--- a/src/typec/utcd.h
+++ b/src/typec/utcd.h
@@ -33,12 +33,24 @@
 extern "C" {
 #endif
 
+//--------------------------------------------------------------------+
+// TypeC Configuration
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUC_TASK_QUEUE_SZ
+#define CFG_TUC_TASK_QUEUE_SZ   16
+#endif
+
+
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+
 
-// init typec stack
-bool tuc_init(uint8_t rhport, typec_port_type_t port_type);
+// Init typec stack on a port
+bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type);
+
+// Check if typec port is initialized
+bool tuc_inited(uint8_t rhport);
 
 #ifndef _TUSB_TCD_H_
 extern void tcd_int_handler(uint8_t rhport);

From 0493983a8ff7d068bd1ef94bcea92846cbe4157e Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Wed, 7 Jun 2023 14:46:14 -0500
Subject: [PATCH 1789/2085] movement of TOP in c0ecf8b5 broke RP2040 SDK build

---
 hw/bsp/family_support.cmake | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index fdcd9a983..d80b54ef8 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -4,6 +4,7 @@ include(CMakePrintHelpers)
 
 # TOP is path to root directory
 set(TOP "${CMAKE_CURRENT_LIST_DIR}/../..")
+get_filename_component(TOP ${TOP} ABSOLUTE)
 
 # Default to gcc
 if (NOT DEFINED TOOLCHAIN)

From 7fd0a17bc3eb1e992865c851c3d24484131fa284 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Jun 2023 09:11:29 +0700
Subject: [PATCH 1790/2085] default CFG_TUC_ENABLED to 0

---
 src/tusb_option.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 948c9edf3..427d19719 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -483,6 +483,14 @@
 #endif
 
 
+//--------------------------------------------------------------------+
+// TypeC Options (Default)
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUC_ENABLED
+#define CFG_TUC_ENABLED 0
+#endif
+
 //------------------------------------------------------------------
 // Configuration Validation
 //------------------------------------------------------------------

From fc761953b323b7565c42254fcfbb248520d83e0e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Jun 2023 09:34:15 +0700
Subject: [PATCH 1791/2085] define tuc_int_handler() to empty if TUC not
 enabled

---
 src/tusb_option.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/tusb_option.h b/src/tusb_option.h
index 427d19719..bb669e693 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -489,6 +489,8 @@
 
 #ifndef CFG_TUC_ENABLED
 #define CFG_TUC_ENABLED 0
+
+#define tuc_int_handler(_p)
 #endif
 
 //------------------------------------------------------------------

From 9c2a8490afadd47d5847793a806e2dce51565868 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Jun 2023 13:37:37 +0700
Subject: [PATCH 1792/2085] dma rx works well

---
 .../boards/b_g474e_dpow1/cubemx/board.ioc     | 194 ++++++++++++++++++
 hw/bsp/stm32g4/family.c                       |   7 +-
 src/portable/st/typec/typec_stm32.c           |  80 +++++++-
 3 files changed, 267 insertions(+), 14 deletions(-)
 create mode 100644 hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc

diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc b/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc
new file mode 100644
index 000000000..6ce126f84
--- /dev/null
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc
@@ -0,0 +1,194 @@
+#MicroXplorer Configuration settings - do not modify
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+Dma.Request0=UCPD1_RX
+Dma.Request1=UCPD1_TX
+Dma.RequestsNb=2
+Dma.UCPD1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
+Dma.UCPD1_RX.0.EventEnable=DISABLE
+Dma.UCPD1_RX.0.Instance=DMA1_Channel1
+Dma.UCPD1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.UCPD1_RX.0.MemInc=DMA_MINC_ENABLE
+Dma.UCPD1_RX.0.Mode=DMA_NORMAL
+Dma.UCPD1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.UCPD1_RX.0.PeriphInc=DMA_PINC_DISABLE
+Dma.UCPD1_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.UCPD1_RX.0.Priority=DMA_PRIORITY_HIGH
+Dma.UCPD1_RX.0.RequestNumber=1
+Dma.UCPD1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.UCPD1_RX.0.SignalID=NONE
+Dma.UCPD1_RX.0.SyncEnable=DISABLE
+Dma.UCPD1_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.UCPD1_RX.0.SyncRequestNumber=1
+Dma.UCPD1_RX.0.SyncSignalID=NONE
+Dma.UCPD1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
+Dma.UCPD1_TX.1.EventEnable=DISABLE
+Dma.UCPD1_TX.1.Instance=DMA1_Channel2
+Dma.UCPD1_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.UCPD1_TX.1.MemInc=DMA_MINC_ENABLE
+Dma.UCPD1_TX.1.Mode=DMA_NORMAL
+Dma.UCPD1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.UCPD1_TX.1.PeriphInc=DMA_PINC_DISABLE
+Dma.UCPD1_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.UCPD1_TX.1.Priority=DMA_PRIORITY_HIGH
+Dma.UCPD1_TX.1.RequestNumber=1
+Dma.UCPD1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.UCPD1_TX.1.SignalID=NONE
+Dma.UCPD1_TX.1.SyncEnable=DISABLE
+Dma.UCPD1_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.UCPD1_TX.1.SyncRequestNumber=1
+Dma.UCPD1_TX.1.SyncSignalID=NONE
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=true
+Mcu.CPN=STM32G474RET3
+Mcu.Family=STM32G4
+Mcu.IP0=DMA
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IP4=UCPD1
+Mcu.IP5=USART3
+Mcu.IPNb=6
+Mcu.Name=STM32G474R(B-C-E)Tx
+Mcu.Package=LQFP64
+Mcu.Pin0=PC10
+Mcu.Pin1=PC11
+Mcu.Pin2=PB4
+Mcu.Pin3=PB6
+Mcu.Pin4=VP_SYS_VS_Systick
+Mcu.Pin5=VP_SYS_VS_DBSignals
+Mcu.PinsNb=6
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32G474RETx
+MxCube.Version=6.8.1
+MxDb.Version=DB.6.0.81
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
+NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
+NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:false
+PB4.Mode=Sink_AllSignals
+PB4.Signal=UCPD1_CC2
+PB6.Mode=Sink_AllSignals
+PB6.Signal=UCPD1_CC1
+PC10.GPIOParameters=GPIO_PuPd
+PC10.GPIO_PuPd=GPIO_PULLUP
+PC10.Mode=Asynchronous
+PC10.Signal=USART3_TX
+PC11.GPIOParameters=GPIO_PuPd
+PC11.GPIO_PuPd=GPIO_PULLUP
+PC11.Mode=Asynchronous
+PC11.Signal=USART3_RX
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32G474RETx
+ProjectManager.FirmwarePackage=STM32Cube FW_G4 V1.5.1
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=2
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=board.ioc
+ProjectManager.ProjectName=board
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=Makefile
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_UCPD1_Init-UCPD1-false-LL-true
+RCC.ADC12Freq_Value=150000000
+RCC.ADC345Freq_Value=150000000
+RCC.AHBFreq_Value=150000000
+RCC.APB1Freq_Value=150000000
+RCC.APB1TimFreq_Value=150000000
+RCC.APB2Freq_Value=150000000
+RCC.APB2TimFreq_Value=150000000
+RCC.CRSFreq_Value=48000000
+RCC.CortexFreq_Value=150000000
+RCC.EXTERNAL_CLOCK_VALUE=12288000
+RCC.FCLKCortexFreq_Value=150000000
+RCC.FDCANFreq_Value=150000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=150000000
+RCC.HRTIM1Freq_Value=150000000
+RCC.HSE_VALUE=24000000
+RCC.HSI48_VALUE=48000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=150000000
+RCC.I2C2Freq_Value=150000000
+RCC.I2C3Freq_Value=150000000
+RCC.I2C4Freq_Value=150000000
+RCC.I2SFreq_Value=150000000
+RCC.IPParameters=ADC12Freq_Value,ADC345Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=150000000
+RCC.LPUART1Freq_Value=150000000
+RCC.LSCOPinFreq_Value=32000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.PLLM=RCC_PLLM_DIV4
+RCC.PLLN=75
+RCC.PLLPoutputFreq_Value=150000000
+RCC.PLLQ=RCC_PLLQ_DIV4
+RCC.PLLQoutputFreq_Value=75000000
+RCC.PLLRCLKFreq_Value=150000000
+RCC.PWRFreq_Value=150000000
+RCC.QSPIFreq_Value=150000000
+RCC.RNGFreq_Value=75000000
+RCC.SAI1Freq_Value=150000000
+RCC.SYSCLKFreq_VALUE=150000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.UART4Freq_Value=150000000
+RCC.UART5Freq_Value=150000000
+RCC.USART1Freq_Value=150000000
+RCC.USART2Freq_Value=150000000
+RCC.USART3Freq_Value=150000000
+RCC.USBFreq_Value=75000000
+RCC.VCOInputFreq_Value=4000000
+RCC.VCOOutputFreq_Value=300000000
+USART3.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
+USART3.BaudRate=115200
+USART3.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
+USART3.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
+USART3.IPParameters=BaudRate,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam,VirtualMode-Asynchronous
+USART3.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
+USART3.Mode=MODE_TX_RX
+USART3.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
+USART3.OverSampling=UART_OVERSAMPLING_16
+USART3.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
+USART3.Parity=PARITY_ODD
+USART3.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
+USART3.StopBits=STOPBITS_1
+USART3.SwapParam=ADVFEATURE_SWAP_DISABLE
+USART3.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
+USART3.VirtualMode-Asynchronous=VM_ASYNC
+USART3.WordLength=WORDLENGTH_8B
+VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals
+VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index d0601b385..5fa6e3dbb 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -144,15 +144,16 @@ void board_init(void)
 
 #if 1
   // USB PD
+  // Default CC1/CC2 is PB4/PB6
   /* PWR register access (for disabling dead battery feature) */
   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
   LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC);
 
   __HAL_RCC_UCPD1_CLK_ENABLE();
 
-  // Default CC1/CC2 is PB4/PB6
-  // PB4   ------> UCPD1_CC2
-  // PB6   ------> UCPD1_CC1
+  // Enable DMA clock
+  __HAL_RCC_DMAMUX1_CLK_ENABLE();
+  __HAL_RCC_DMA1_CLK_ENABLE();
 #endif
 
 }
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
index 79f37b729..c96dd0902 100644
--- a/src/portable/st/typec/typec_stm32.c
+++ b/src/portable/st/typec/typec_stm32.c
@@ -31,6 +31,7 @@
 
 #if CFG_TUSB_MCU == OPT_MCU_STM32G4
   #include "stm32g4xx.h"
+  #include "stm32g4xx_hal_dma.h"
 #else
   #error "Unsupported STM32 family"
 #endif
@@ -61,13 +62,46 @@ static uint32_t rx_count = 0;
 static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4);
 static uint32_t tx_count;
 
+#define CFG_TUC_STM32_DMA_RX { DMA1_Channel1 }
+//#define CFG_TUC_STM32_DMA_TX { DMA1_Channel2 }
+
+#ifdef CFG_TUC_STM32_DMA_RX
+static DMA_Channel_TypeDef* dma_rx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_RX;
+
+TU_ATTR_ALWAYS_INLINE static inline
+void dma_rx_start(uint8_t rhport)
+{
+  DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
+
+  dma_rx_ch->CMAR = (uint32_t) rx_buf;
+  dma_rx_ch->CNDTR = sizeof(rx_buf);
+  dma_rx_ch->CCR |= DMA_CCR_EN;
+}
+#endif
+
+#ifdef CFG_TUC_STM32_DMA_TX
+static DMA_Channel_TypeDef* dma_tx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_TX;
+#endif
+
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
+#include "stm32g4xx_ll_dma.h"
 
 bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
   (void) rhport;
 
+#ifdef CFG_TUC_STM32_DMA_RX
+  // Init DMA
+  DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
+
+  // Peripheral -> Memory, Memory inc, 8-bit, High priority
+  dma_rx_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1;
+  dma_rx_ch->CPAR = (uint32_t) &UCPD1->RXDR;
+
+  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_UCPD1_RX);
+#endif
+
   // Initialization phase: CFG1
   UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
                 (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) |
@@ -77,7 +111,7 @@ bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
   // General programming sequence (with UCPD configured then enabled)
   if (port_type == TUSB_TYPEC_PORT_SNK) {
     // Enable both CC Phy
-    UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (0x03 << UCPD_CR_CCENABLE_Pos);
+    UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
 
     // Read Voltage State on CC1 & CC2 fore initial state
     uint32_t vstate_cc[2];
@@ -135,30 +169,48 @@ void tcd_int_handler(uint8_t rhport) {
     TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
 
     uint32_t cr = UCPD1->CR;
+    uint32_t cfg1 = UCPD1->CFG1;
 
     // TODO only support SNK for now, required highest voltage for now
+    // Enable PHY on correct CC and disable Rd on other CC
     if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) {
       TU_LOG1("Attach CC1\n");
-      cr &= ~UCPD_CR_PHYCCSEL;
-      cr |= UCPD_CR_PHYRXEN;
+
+      cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE);
+      cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0;
     } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) {
       TU_LOG1("Attach CC2\n");
-      cr |= UCPD_CR_PHYCCSEL;
-      cr |= UCPD_CR_PHYRXEN;
+      cr &= ~UCPD_CR_CCENABLE;
+      cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1);
     } else {
       TU_LOG1("Detach\n");
       cr &= ~UCPD_CR_PHYRXEN;
+      cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
     }
 
     if (cr & UCPD_CR_PHYRXEN) {
       // Enable Interrupt
-      UCPD1->IMR |= UCPD_IMR_TXISIE | UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
-                    UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE | UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE |
-                    UCPD_IMR_RXMSGENDIE | UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE;
+      uint32_t imr = UCPD1->IMR;
+      imr |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
+          UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE |
+          UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE;
+
+      #ifdef CFG_TUC_STM32_DMA_RX
+      cfg1 |= UCPD_CFG1_RXDMAEN;
+      dma_rx_start(rhport);
+      #else
+      imr |= UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE;
+      #endif
+
+      #ifndef CFG_TUC_STM32_DMA_TX
+      imr |= UCPD_IMR_TXISIE;
+      #endif
+
+      UCPD1->IMR = imr;
     }
 
-    // Enable PD RX
     UCPD1->CR = cr;
+    UCPD1->CFG1 = cfg1;
 
     // ack
     UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
@@ -176,6 +228,7 @@ void tcd_int_handler(uint8_t rhport) {
     UCPD1->ICR = UCPD_ICR_RXORDDETCF;
   }
 
+#ifndef CFG_TUC_STM32_DMA_RX
   if (sr & UCPD_SR_RXNE) {
     // TODO DMA later
     do {
@@ -184,8 +237,9 @@ void tcd_int_handler(uint8_t rhport) {
 
     // no ack needed
   }
+#endif
 
-  // End of message
+  // Received full message
   if (sr & UCPD_SR_RXMSGEND) {
 
     // Skip if CRC failed
@@ -213,13 +267,17 @@ void tcd_int_handler(uint8_t rhport) {
       // notify stack after good crc ?
     }
 
+    #ifdef CFG_TUC_STM32_DMA_RX
+    // prepare next receive
+    dma_rx_start(rhport);
+    #endif
+
     // ack
     UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
   }
 
   if (sr & UCPD_SR_RXOVR) {
     TU_LOG1("RXOVR\n");
-    TU_LOG1_HEX(rx_count);
     // ack
     UCPD1->ICR = UCPD_ICR_RXOVRCF;
   }

From 8181d470e5bbb01f873d8fa11e8e1293cb76703f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 8 Jun 2023 18:55:54 +0700
Subject: [PATCH 1793/2085] enable DMA for both pd rx, tx

---
 src/portable/st/typec/typec_stm32.c | 205 +++++++++++++++-------------
 1 file changed, 107 insertions(+), 98 deletions(-)

diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
index c96dd0902..a898cda47 100644
--- a/src/portable/st/typec/typec_stm32.c
+++ b/src/portable/st/typec/typec_stm32.c
@@ -31,7 +31,7 @@
 
 #if CFG_TUSB_MCU == OPT_MCU_STM32G4
   #include "stm32g4xx.h"
-  #include "stm32g4xx_hal_dma.h"
+  #include "stm32g4xx_ll_dma.h" // for UCLP REQID
 #else
   #error "Unsupported STM32 family"
 #endif
@@ -40,6 +40,12 @@
 //
 //--------------------------------------------------------------------+
 
+enum {
+  IMR_ATTACHED = UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
+                 UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE |
+                 UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE
+};
+
 #define PHY_SYNC1 0x18u
 #define PHY_SYNC2 0x11u
 #define PHY_SYNC3 0x06u
@@ -57,55 +63,101 @@
 
 
 static uint8_t rx_buf[262] TU_ATTR_ALIGNED(4);
-static uint32_t rx_count = 0;
-
 static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4);
-static uint32_t tx_count;
+static uint32_t tx_index;
 
-#define CFG_TUC_STM32_DMA_RX { DMA1_Channel1 }
-//#define CFG_TUC_STM32_DMA_TX { DMA1_Channel2 }
+// address of DMA channel rx, tx for each port
+#define CFG_TUC_STM32_DMA  { { DMA1_Channel1_BASE, DMA1_Channel2_BASE } }
 
-#ifdef CFG_TUC_STM32_DMA_RX
-static DMA_Channel_TypeDef* dma_rx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_RX;
+//--------------------------------------------------------------------+
+// DMA
+//--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline
-void dma_rx_start(uint8_t rhport)
-{
-  DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
+static const uint32_t dma_addr_arr[TUP_TYPEC_RHPORTS_NUM][2] = CFG_TUC_STM32_DMA;
 
-  dma_rx_ch->CMAR = (uint32_t) rx_buf;
-  dma_rx_ch->CNDTR = sizeof(rx_buf);
-  dma_rx_ch->CCR |= DMA_CCR_EN;
+TU_ATTR_ALWAYS_INLINE static inline uint32_t dma_get_addr(uint8_t rhport, bool is_rx) {
+  return dma_addr_arr[rhport][is_rx ? 0 : 1];
 }
-#endif
 
-#ifdef CFG_TUC_STM32_DMA_TX
-static DMA_Channel_TypeDef* dma_tx_arr[TUP_TYPEC_RHPORTS_NUM] = CFG_TUC_STM32_DMA_TX;
-#endif
+static void dma_init(uint8_t rhport, bool is_rx) {
+  uint32_t dma_addr = dma_get_addr(rhport, is_rx);
+  DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_addr;
+  uint32_t req_id;
+
+  if (is_rx) {
+    // Peripheral -> Memory, Memory inc, 8-bit, High priority
+    dma_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1;
+    dma_ch->CPAR = (uint32_t) &UCPD1->RXDR;
+
+    req_id = LL_DMAMUX_REQ_UCPD1_RX;
+  } else {
+    // Memory -> Peripheral, Memory inc, 8-bit, High priority
+    dma_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1 | DMA_CCR_DIR;
+    dma_ch->CPAR = (uint32_t) &UCPD1->TXDR;
+
+    req_id = LL_DMAMUX_REQ_UCPD1_TX;
+  }
+
+  // find and set up mux channel TODO support mcu with multiple DMAMUXs
+  enum {
+    CH_DIFF = DMA1_Channel2_BASE - DMA1_Channel1_BASE
+  };
+  uint32_t mux_ch_num;
+
+  #ifdef DMA2_BASE
+  if (dma_addr > DMA2_BASE) {
+    mux_ch_num = 8 * ((dma_addr - DMA2_Channel1_BASE) / CH_DIFF);
+  } else
+  #endif
+  {
+    mux_ch_num = (dma_addr - DMA1_Channel1_BASE) / CH_DIFF;
+  }
+
+  DMAMUX_Channel_TypeDef* mux_ch = DMAMUX1_Channel0 + mux_ch_num;
+
+  uint32_t mux_ccr = mux_ch->CCR & ~(DMAMUX_CxCR_DMAREQ_ID);
+  mux_ccr |= req_id;
+  mux_ch->CCR = mux_ccr;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dma_start(uint8_t rhport, bool is_rx, void const* buf, uint16_t len) {
+  DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
+
+  dma_ch->CMAR = (uint32_t) buf;
+  dma_ch->CNDTR = len;
+  dma_ch->CCR |= DMA_CCR_EN;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dma_stop(uint8_t rhport, bool is_rx) {
+  DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
+  dma_ch->CCR &= ~DMA_CCR_EN;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dma_rx_start(uint8_t rhport) {
+  dma_start(rhport, true, rx_buf, sizeof(rx_buf));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) {
+  UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
+  UCPD1->TX_PAYSZ = len;
+  dma_start(rhport, false, buf, len);
+}
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
-#include "stm32g4xx_ll_dma.h"
+
 
 bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
   (void) rhport;
 
-#ifdef CFG_TUC_STM32_DMA_RX
-  // Init DMA
-  DMA_Channel_TypeDef* dma_rx_ch = dma_rx_arr[rhport];
-
-  // Peripheral -> Memory, Memory inc, 8-bit, High priority
-  dma_rx_ch->CCR = DMA_CCR_MINC | DMA_CCR_PL_1;
-  dma_rx_ch->CPAR = (uint32_t) &UCPD1->RXDR;
-
-  LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_1, LL_DMAMUX_REQ_UCPD1_RX);
-#endif
+  // Init DMA for RX, TX
+  dma_init(rhport, true);
+  dma_init(rhport, false);
 
   // Initialization phase: CFG1
   UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
-                (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos) |
-                (0 << UCPD_CFG1_TXDMAEN_Pos) | (0 << UCPD_CFG1_RXDMAEN_Pos);
+                (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos);
   UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
 
   // General programming sequence (with UCPD configured then enabled)
@@ -118,8 +170,7 @@ bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
     vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
     vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
 
-    TU_LOG1_INT(vstate_cc[0]);
-    TU_LOG1_INT(vstate_cc[1]);
+    TU_LOG1("Initial VState CC1 = %u, CC2 = %u\r\n", vstate_cc[0], vstate_cc[1]);
 
     // Enable CC1 & CC2 Interrupt
     UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE;
@@ -142,7 +193,8 @@ void tcd_int_disable(uint8_t rhport) {
 
 bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
   (void) rhport;
-
+  (void) buffer;
+  (void) total_bytes;
   return true;
 }
 
@@ -159,8 +211,6 @@ void tcd_int_handler(uint8_t rhport) {
   uint32_t sr = UCPD1->SR;
   sr &= UCPD1->IMR;
 
-//  TU_LOG1("UCPD1_IRQHandler: sr = 0x%08X\n", sr);
-
   if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) {
     uint32_t vstate_cc[2];
     vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
@@ -169,7 +219,6 @@ void tcd_int_handler(uint8_t rhport) {
     TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
 
     uint32_t cr = UCPD1->CR;
-    uint32_t cfg1 = UCPD1->CFG1;
 
     // TODO only support SNK for now, required highest voltage for now
     // Enable PHY on correct CC and disable Rd on other CC
@@ -189,28 +238,18 @@ void tcd_int_handler(uint8_t rhport) {
     }
 
     if (cr & UCPD_CR_PHYRXEN) {
-      // Enable Interrupt
-      uint32_t imr = UCPD1->IMR;
-      imr |= UCPD_IMR_TXMSGDISCIE | UCPD_IMR_TXMSGSENTIE | UCPD_IMR_TXMSGABTIE | UCPD_IMR_TXUNDIE |
-          UCPD_IMR_RXHRSTDETIE | UCPD_IMR_RXOVRIE | UCPD_IMR_RXMSGENDIE | UCPD_IMR_RXORDDETIE |
-          UCPD_IMR_HRSTDISCIE | UCPD_IMR_HRSTSENTIE | UCPD_IMR_FRSEVTIE;
+      // Attached
+      UCPD1->IMR |= IMR_ATTACHED;
+      UCPD1->CFG1 |= UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN;
 
-      #ifdef CFG_TUC_STM32_DMA_RX
-      cfg1 |= UCPD_CFG1_RXDMAEN;
       dma_rx_start(rhport);
-      #else
-      imr |= UCPD_IMR_RXNEIE | UCPD_IMR_RXORDDETIE;
-      #endif
-
-      #ifndef CFG_TUC_STM32_DMA_TX
-      imr |= UCPD_IMR_TXISIE;
-      #endif
-
-      UCPD1->IMR = imr;
+    }else {
+      // Detached
+      UCPD1->CFG1 &= ~(UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN);
+      UCPD1->IMR &= ~IMR_ATTACHED;
     }
 
     UCPD1->CR = cr;
-    UCPD1->CFG1 = cfg1;
 
     // ack
     UCPD1->ICR = UCPD_ICR_TYPECEVT1CF | UCPD_ICR_TYPECEVT2CF;
@@ -221,27 +260,15 @@ void tcd_int_handler(uint8_t rhport) {
     // SOP: Start of Packet.
     // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
 
-    // reset count when received SOP
-    rx_count = 0;
-
     // ack
     UCPD1->ICR = UCPD_ICR_RXORDDETCF;
   }
 
-#ifndef CFG_TUC_STM32_DMA_RX
-  if (sr & UCPD_SR_RXNE) {
-    // TODO DMA later
-    do {
-      rx_buf[rx_count++] = UCPD1->RXDR;
-    } while (UCPD1->SR & UCPD_SR_RXNE);
-
-    // no ack needed
-  }
-#endif
-
   // Received full message
   if (sr & UCPD_SR_RXMSGEND) {
 
+    dma_stop(rhport, true);
+
     // Skip if CRC failed
     if (!(sr & UCPD_SR_RXERR)) {
       uint32_t payload_size = UCPD1->RX_PAYSZ;
@@ -251,26 +278,23 @@ void tcd_int_handler(uint8_t rhport) {
       (*(tusb_pd_header_t*) tx_buf) = (tusb_pd_header_t) {
           .msg_type = TUSB_PD_CTRL_GOOD_CRC,
           .data_role = 0, // UFP
-          .specs_rev = TUSB_PD_REV30,
+          .specs_rev = TUSB_PD_REV20,
           .power_role = 0, // Sink
           .msg_id = rx_header->msg_id,
           .n_data_obj = 0,
           .extended = 0
       };
-      tx_count = 0;
 
       // response with good crc
-      UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
-      UCPD1->TX_PAYSZ = 2;
-      UCPD1->CR |= UCPD_CR_TXSEND; // will trigger TXIS interrupt
+      dma_tx_start(rhport, tx_buf, 2);
 
-      // notify stack after good crc ?
+      UCPD1->CR |= UCPD_CR_TXSEND;
+
+      // notify stack
     }
 
-    #ifdef CFG_TUC_STM32_DMA_RX
     // prepare next receive
     dma_rx_start(rhport);
-    #endif
 
     // ack
     UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
@@ -283,34 +307,19 @@ void tcd_int_handler(uint8_t rhport) {
   }
 
   //------------- TX -------------//
-  if (sr & UCPD_SR_TXIS) {
-    // TU_LOG1("TXIS\n");
-
-    // TODO DMA later
-    do {
-      UCPD1->TXDR = tx_buf[tx_count++];
-    } while (UCPD1->SR & UCPD_SR_TXIS);
-
-    // no ack needed
-  }
-
   if (sr & UCPD_SR_TXMSGSENT) {
     // all byte sent
-    TU_LOG1("TXMSGSENT\n");
+    dma_stop(rhport, false);
 
     // ack
     UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
   }
 
-//  if (sr & UCPD_SR_RXNE) {
-//    uint8_t data = UCPD1->RXDR;
-//    pd_rx_buf[pd_rx_count++] = data;
-//    TU_LOG1_HEX(data);
-//  }
-
-//  else {
-//    TU_LOG_LOCATION();
-//  }
+  if (sr & (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND)) {
+    TU_LOG1("TX Error\n");
+    dma_stop(rhport, false);
+    UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND;
+  }
 }
 
 #endif

From 08338069805a4e1b5bdf6d3bac0b694d6b10f20e Mon Sep 17 00:00:00 2001
From: Eugene Kliuchnikov <eustas.ru@gmail.com>
Date: Thu, 8 Jun 2023 15:38:30 +0200
Subject: [PATCH 1794/2085] Fix typos

---
 .../device/audio_test_multi_rate/src/usb_descriptors.h |  2 +-
 examples/device/uac2_headset/src/usb_descriptors.h     |  4 ++--
 src/class/video/video.h                                |  4 ++--
 src/device/usbd.h                                      | 10 +++++-----
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.h b/examples/device/audio_test_multi_rate/src/usb_descriptors.h
index 8d8a03e49..8381e31f5 100644
--- a/examples/device/audio_test_multi_rate/src/usb_descriptors.h
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.h
@@ -60,7 +60,7 @@
 
 #define TUD_AUDIO_MIC_ONE_CH_2_FORMAT_DESCRIPTOR(_itfnum, _stridx, _epin) \
   /* Standard Interface Association Descriptor (IAD) */\
-  TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+  TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
   /* Standard AC Interface Descriptor(4.7.1) */\
   TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
   /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
diff --git a/examples/device/uac2_headset/src/usb_descriptors.h b/examples/device/uac2_headset/src/usb_descriptors.h
index 457e69882..d7e170162 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.h
+++ b/examples/device/uac2_headset/src/usb_descriptors.h
@@ -57,7 +57,7 @@ enum
     + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
     /* Interface 1, Alternate 0 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
-    /* Interface 1, Alternate 0 */\
+    /* Interface 1, Alternate 1 */\
     + TUD_AUDIO_DESC_STD_AS_INT_LEN\
     + TUD_AUDIO_DESC_CS_AS_INT_LEN\
     + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
@@ -86,7 +86,7 @@ enum
 
 #define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin) \
     /* Standard Interface Association Descriptor (IAD) */\
-    TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ 3, /*_stridx*/ 0x00),\
+    TUD_AUDIO_DESC_IAD(/*_firstitf*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ ITF_NUM_TOTAL, /*_stridx*/ 0x00),\
     /* Standard AC Interface Descriptor(4.7.1) */\
     TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
     /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
diff --git a/src/class/video/video.h b/src/class/video/video.h
index c0088c4f6..d9880c291 100644
--- a/src/class/video/video.h
+++ b/src/class/video/video.h
@@ -448,9 +448,9 @@ TU_VERIFY_STATIC( sizeof(video_probe_and_commit_control_t) == 48, "size is not c
 #define TUD_VIDEO_GUID_M420   0x4D,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
 #define TUD_VIDEO_GUID_I420   0x49,0x34,0x32,0x30,0x00,0x00,0x10,0x00,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71
 
-#define TUD_VIDEO_DESC_IAD(_firstitfs, _nitfs, _stridx) \
+#define TUD_VIDEO_DESC_IAD(_firstitf, _nitfs, _stridx) \
   TUD_VIDEO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, \
-  _firstitfs, _nitfs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_INTERFACE_COLLECTION, \
+  _firstitf, _nitfs, TUSB_CLASS_VIDEO, VIDEO_SUBCLASS_INTERFACE_COLLECTION, \
   VIDEO_ITF_PROTOCOL_UNDEFINED, _stridx
 
 #define TUD_VIDEO_DESC_STD_VC(_itfnum, _nEPs, _stridx) \
diff --git a/src/device/usbd.h b/src/device/usbd.h
index 255e5a844..b11c1a09d 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -347,8 +347,8 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 /* Standard Interface Association Descriptor (IAD) */
 #define TUD_AUDIO_DESC_IAD_LEN 8
-#define TUD_AUDIO_DESC_IAD(_firstitfs, _nitfs, _stridx) \
-  TUD_AUDIO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, _firstitfs, _nitfs, TUSB_CLASS_AUDIO, AUDIO_FUNCTION_SUBCLASS_UNDEFINED, AUDIO_FUNC_PROTOCOL_CODE_V2, _stridx
+#define TUD_AUDIO_DESC_IAD(_firstitf, _nitfs, _stridx) \
+  TUD_AUDIO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, _firstitf, _nitfs, TUSB_CLASS_AUDIO, AUDIO_FUNCTION_SUBCLASS_UNDEFINED, AUDIO_FUNC_PROTOCOL_CODE_V2, _stridx
 
 /* Standard AC Interface Descriptor(4.7.1) */
 #define TUD_AUDIO_DESC_STD_AC_LEN 9
@@ -443,7 +443,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 #define TUD_AUDIO_MIC_ONE_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \
   /* Standard Interface Association Descriptor (IAD) */\
-  TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+  TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
   /* Standard AC Interface Descriptor(4.7.1) */\
   TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
   /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
@@ -492,7 +492,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 #define TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \
   /* Standard Interface Association Descriptor (IAD) */\
-  TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+  TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
   /* Standard AC Interface Descriptor(4.7.1) */\
   TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
   /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
@@ -540,7 +540,7 @@ TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb
 
 #define TUD_AUDIO_SPEAKER_MONO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epsize, _epfb) \
   /* Standard Interface Association Descriptor (IAD) */\
-  TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+  TUD_AUDIO_DESC_IAD(/*_firstitf*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
   /* Standard AC Interface Descriptor(4.7.1) */\
   TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
   /* Class-Specific AC Interface Header Descriptor(4.7.2) */\

From 912802456b568e4b666a9205c3799da79f87ef69 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 9 Jun 2023 18:15:28 +0700
Subject: [PATCH 1795/2085] move protocol message to stack, disable battery in
 PWR's CR3

there is still issue with CC1/CC2 pull down resistor and vstate is not
correct.
---
 hw/bsp/stm32g4/family.c             |   8 +-
 src/device/dcd.h                    |   1 +
 src/portable/st/typec/typec_stm32.c | 113 ++++++++++++++--------------
 src/typec/tcd.h                     |  52 +++++++++++++
 src/typec/utcd.c                    |  61 +++++++++++----
 src/typec/utcd.h                    |   2 +-
 6 files changed, 162 insertions(+), 75 deletions(-)

diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index 5fa6e3dbb..d77183357 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -145,13 +145,13 @@ void board_init(void)
 #if 1
   // USB PD
   // Default CC1/CC2 is PB4/PB6
-  /* PWR register access (for disabling dead battery feature) */
-  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC);
 
+  // Enable pwr for disabling dead battery feature in Power's CR3
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_RCC_CRC_CLK_ENABLE();
   __HAL_RCC_UCPD1_CLK_ENABLE();
 
-  // Enable DMA clock
+  // Enable DMA for USB PD
   __HAL_RCC_DMAMUX1_CLK_ENABLE();
   __HAL_RCC_DMA1_CLK_ENABLE();
 #endif
diff --git a/src/device/dcd.h b/src/device/dcd.h
index f82b8633d..4e9cfd5d5 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -189,6 +189,7 @@ TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t l
 
 // Configure and enable an ISO endpoint according to descriptor
 TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endpoint_desc);
+
 //--------------------------------------------------------------------+
 // Event API (implemented by stack)
 //--------------------------------------------------------------------+
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
index a898cda47..1dba54492 100644
--- a/src/portable/st/typec/typec_stm32.c
+++ b/src/portable/st/typec/typec_stm32.c
@@ -31,7 +31,7 @@
 
 #if CFG_TUSB_MCU == OPT_MCU_STM32G4
   #include "stm32g4xx.h"
-  #include "stm32g4xx_ll_dma.h" // for UCLP REQID
+  #include "stm32g4xx_ll_dma.h" // for UCPD REQID
 #else
   #error "Unsupported STM32 family"
 #endif
@@ -62,9 +62,17 @@ enum {
 #define PHY_ORDERED_SET_SOP_PP_DEBUG (PHY_SYNC1 | (PHY_RST2<<5u)  | (PHY_SYNC3<<10u) | (PHY_SYNC2<<15u)) // SOP'' Debug Ordered set coding
 
 
-static uint8_t rx_buf[262] TU_ATTR_ALIGNED(4);
-static uint8_t tx_buf[262] TU_ATTR_ALIGNED(4);
-static uint32_t tx_index;
+static uint8_t const* _rx_buf;
+
+static tusb_pd_header_t _good_crc = {
+    .msg_type   = TUSB_PD_CTRL_GOOD_CRC,
+    .data_role  = 0, // UFP
+    .specs_rev  = TUSB_PD_REV20,
+    .power_role = 0, // Sink
+    .msg_id     = 0,
+    .n_data_obj = 0,
+    .extended   = 0
+};
 
 // address of DMA channel rx, tx for each port
 #define CFG_TUC_STM32_DMA  { { DMA1_Channel1_BASE, DMA1_Channel2_BASE } }
@@ -73,10 +81,10 @@ static uint32_t tx_index;
 // DMA
 //--------------------------------------------------------------------+
 
-static const uint32_t dma_addr_arr[TUP_TYPEC_RHPORTS_NUM][2] = CFG_TUC_STM32_DMA;
+static const uint32_t _dma_addr_arr[TUP_TYPEC_RHPORTS_NUM][2] = CFG_TUC_STM32_DMA;
 
 TU_ATTR_ALWAYS_INLINE static inline uint32_t dma_get_addr(uint8_t rhport, bool is_rx) {
-  return dma_addr_arr[rhport][is_rx ? 0 : 1];
+  return _dma_addr_arr[rhport][is_rx ? 0 : 1];
 }
 
 static void dma_init(uint8_t rhport, bool is_rx) {
@@ -133,10 +141,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dma_stop(uint8_t rhport, bool is_rx) {
   dma_ch->CCR &= ~DMA_CCR_EN;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void dma_rx_start(uint8_t rhport) {
-  dma_start(rhport, true, rx_buf, sizeof(rx_buf));
-}
-
 TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) {
   UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
   UCPD1->TX_PAYSZ = len;
@@ -147,7 +151,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const
 //
 //--------------------------------------------------------------------+
 
-
 bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
   (void) rhport;
 
@@ -155,27 +158,30 @@ bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
   dma_init(rhport, true);
   dma_init(rhport, false);
 
-  // Initialization phase: CFG1
+  // Initialization phase: CFG1, detect all SOPs
   UCPD1->CFG1 = (0x0d << UCPD_CFG1_HBITCLKDIV_Pos) | (0x10 << UCPD_CFG1_IFRGAP_Pos) | (0x07 << UCPD_CFG1_TRANSWIN_Pos) |
                 (0x01 << UCPD_CFG1_PSC_UCPDCLK_Pos) | (0x1f << UCPD_CFG1_RXORDSETEN_Pos);
   UCPD1->CFG1 |= UCPD_CFG1_UCPDEN;
 
   // General programming sequence (with UCPD configured then enabled)
   if (port_type == TUSB_TYPEC_PORT_SNK) {
-    // Enable both CC Phy
-    UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
+    // Set analog mode enable both CC Phy
+    UCPD1->CR = (0x01 << UCPD_CR_ANAMODE_Pos) | (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1);
 
     // Read Voltage State on CC1 & CC2 fore initial state
-    uint32_t vstate_cc[2];
-    vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
-    vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
+    uint32_t v_cc[2];
+    v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
+    v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
 
-    TU_LOG1("Initial VState CC1 = %u, CC2 = %u\r\n", vstate_cc[0], vstate_cc[1]);
+    TU_LOG1("Initial VState CC1 = %u, CC2 = %u\r\n", v_cc[0], v_cc[1]);
 
     // Enable CC1 & CC2 Interrupt
     UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE;
   }
 
+  // Disable dead battery in PWR's CR3
+  PWR->CR3 |= PWR_CR3_UCPD_DBDIS;
+
   return true;
 }
 
@@ -192,9 +198,8 @@ void tcd_int_disable(uint8_t rhport) {
 }
 
 bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
-  (void) rhport;
-  (void) buffer;
-  (void) total_bytes;
+  _rx_buf = buffer;
+  dma_start(rhport, true, buffer, total_bytes);
   return true;
 }
 
@@ -212,27 +217,28 @@ void tcd_int_handler(uint8_t rhport) {
   sr &= UCPD1->IMR;
 
   if (sr & (UCPD_SR_TYPECEVT1 | UCPD_SR_TYPECEVT2)) {
-    uint32_t vstate_cc[2];
-    vstate_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
-    vstate_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
+    uint32_t v_cc[2];
+    v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
+    v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
 
-    TU_LOG1("VState CC1 = %u, CC2 = %u\n", vstate_cc[0], vstate_cc[1]);
+    TU_LOG3("VState CC1 = %u, CC2 = %u\n", v_cc[0], v_cc[1]);
 
     uint32_t cr = UCPD1->CR;
 
     // TODO only support SNK for now, required highest voltage for now
-    // Enable PHY on correct CC and disable Rd on other CC
-    if ((sr & UCPD_SR_TYPECEVT1) && (vstate_cc[0] == 3)) {
-      TU_LOG1("Attach CC1\n");
-
+    // Enable PHY on active CC and disable Rd on other CC
+    // FIXME somehow CC2 is vstate is not correct, always 1 even not attached.
+    // on DPOW1 board, it is connected to PA10 (USBPD_DBCC2), we probably miss something.
+    if ((sr & UCPD_SR_TYPECEVT1) && (v_cc[0] == 3)) {
+      TU_LOG3("Attach CC1\n");
       cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE);
       cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0;
-    } else if ((sr & UCPD_SR_TYPECEVT2) && (vstate_cc[1] == 3)) {
-      TU_LOG1("Attach CC2\n");
+    } else if ((sr & UCPD_SR_TYPECEVT2) && (v_cc[1] == 3)) {
+      TU_LOG3("Attach CC2\n");
       cr &= ~UCPD_CR_CCENABLE;
       cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1);
     } else {
-      TU_LOG1("Detach\n");
+      TU_LOG3("Detach\n");
       cr &= ~UCPD_CR_PHYRXEN;
       cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
     }
@@ -241,14 +247,15 @@ void tcd_int_handler(uint8_t rhport) {
       // Attached
       UCPD1->IMR |= IMR_ATTACHED;
       UCPD1->CFG1 |= UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN;
-
-      dma_rx_start(rhport);
     }else {
       // Detached
       UCPD1->CFG1 &= ~(UCPD_CFG1_RXDMAEN | UCPD_CFG1_TXDMAEN);
       UCPD1->IMR &= ~IMR_ATTACHED;
     }
 
+    // notify stack
+    tcd_event_cc_changed(rhport, v_cc[0], v_cc[1], true);
+
     UCPD1->CR = cr;
 
     // ack
@@ -258,6 +265,7 @@ void tcd_int_handler(uint8_t rhport) {
   //------------- RX -------------//
   if (sr & UCPD_SR_RXORDDET) {
     // SOP: Start of Packet.
+    TU_LOG3("SOP\n");
     // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
 
     // ack
@@ -266,48 +274,39 @@ void tcd_int_handler(uint8_t rhport) {
 
   // Received full message
   if (sr & UCPD_SR_RXMSGEND) {
-
+    TU_LOG3("RX MSG END\n");
     dma_stop(rhport, true);
 
-    // Skip if CRC failed
+    uint8_t result;
+
     if (!(sr & UCPD_SR_RXERR)) {
-      uint32_t payload_size = UCPD1->RX_PAYSZ;
-      // TU_LOG1("RXMSGEND: payload_size = %u, rx count = %u\n", payload_size, pd_rx_count);
-
-      tusb_pd_header_t const* rx_header = (tusb_pd_header_t const*) rx_buf;
-      (*(tusb_pd_header_t*) tx_buf) = (tusb_pd_header_t) {
-          .msg_type = TUSB_PD_CTRL_GOOD_CRC,
-          .data_role = 0, // UFP
-          .specs_rev = TUSB_PD_REV20,
-          .power_role = 0, // Sink
-          .msg_id = rx_header->msg_id,
-          .n_data_obj = 0,
-          .extended = 0
-      };
-
       // response with good crc
-      dma_tx_start(rhport, tx_buf, 2);
-
+      _good_crc.msg_id = ((tusb_pd_header_t const*) _rx_buf)->msg_id;
+      dma_tx_start(rhport, &_good_crc, 2);
       UCPD1->CR |= UCPD_CR_TXSEND;
 
-      // notify stack
+      result = XFER_RESULT_SUCCESS;
+    }else {
+      // CRC failed
+      result = XFER_RESULT_FAILED;
     }
 
-    // prepare next receive
-    dma_rx_start(rhport);
+    // notify stack
+    tcd_event_rx_complete(rhport, UCPD1->RX_PAYSZ, result, true);
 
     // ack
     UCPD1->ICR = UCPD_ICR_RXMSGENDCF;
   }
 
   if (sr & UCPD_SR_RXOVR) {
-    TU_LOG1("RXOVR\n");
+    TU_LOG3("RXOVR\n");
     // ack
     UCPD1->ICR = UCPD_ICR_RXOVRCF;
   }
 
   //------------- TX -------------//
   if (sr & UCPD_SR_TXMSGSENT) {
+    TU_LOG3("TX MSG SENT\n");
     // all byte sent
     dma_stop(rhport, false);
 
@@ -316,7 +315,7 @@ void tcd_int_handler(uint8_t rhport) {
   }
 
   if (sr & (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND)) {
-    TU_LOG1("TX Error\n");
+    TU_LOG3("TX Error\n");
     dma_stop(rhport, false);
     UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND;
   }
diff --git a/src/typec/tcd.h b/src/typec/tcd.h
index e823bf8d7..41dceaa74 100644
--- a/src/typec/tcd.h
+++ b/src/typec/tcd.h
@@ -38,10 +38,28 @@ extern "C" {
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
+
+enum {
+  TCD_EVENT_INVALID = 0,
+  TCD_EVENT_CC_CHANGED,
+  TCD_EVENT_RX_COMPLETE,
+};
+
+
 typedef struct {
   uint8_t rhport;
   uint8_t event_id;
 
+  union {
+    struct {
+      uint8_t cc_state[2];
+    } cc_changed;
+
+    struct {
+      uint16_t xferred_bytes;
+      uint8_t result;
+    } rx_complete;
+  };
 
 } tcd_event_t;;
 
@@ -68,4 +86,38 @@ void tcd_int_handler(uint8_t rhport);
 bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes);
 bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes);
 
+//--------------------------------------------------------------------+
+// Event API (implemented by stack)
+// Called by TCD to notify stack
+//--------------------------------------------------------------------+
+
+extern void tcd_event_handler(tcd_event_t const * event, bool in_isr);
+
+TU_ATTR_ALWAYS_INLINE static inline
+void tcd_event_cc_changed(uint8_t rhport, uint8_t cc1, uint8_t cc2, bool in_isr) {
+  tcd_event_t event = {
+    .rhport   = rhport,
+    .event_id = TCD_EVENT_CC_CHANGED,
+    .cc_changed = {
+        .cc_state = {cc1, cc2 }
+    }
+  };
+
+  tcd_event_handler(&event, in_isr);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline
+void tcd_event_rx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t result, bool in_isr) {
+  tcd_event_t event = {
+    .rhport   = rhport,
+    .event_id = TCD_EVENT_RX_COMPLETE,
+    .rx_complete = {
+        .xferred_bytes = xferred_bytes,
+        .result        = result
+    }
+  };
+
+  tcd_event_handler(&event, in_isr);
+}
+
 #endif
diff --git a/src/typec/utcd.c b/src/typec/utcd.c
index b5f9965fe..fb69b01e8 100644
--- a/src/typec/utcd.c
+++ b/src/typec/utcd.c
@@ -42,35 +42,38 @@
 // Event queue
 // utcd_int_set() is used as mutex in OS NONE config
 void utcd_int_set(bool enabled);
-OSAL_QUEUE_DEF(utcd_int_set, utcd_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t);
-tu_static osal_queue_t utcd_q;
+OSAL_QUEUE_DEF(utcd_int_set, _utcd_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t);
+tu_static osal_queue_t _utcd_q;
 
 // if stack is initialized
-static bool utcd_inited = false;
+static bool _utcd_inited = false;
 
 // if port is initialized
-static bool port_inited[TUP_TYPEC_RHPORTS_NUM];
+static bool _port_inited[TUP_TYPEC_RHPORTS_NUM];
+
+// Max possible PD size is 262 bytes
+static uint8_t _rx_buf[262] TU_ATTR_ALIGNED(4);
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 bool tuc_inited(uint8_t rhport) {
-  return utcd_inited && port_inited[rhport];
+  return _utcd_inited && _port_inited[rhport];
 }
 
 bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
   // Initialize stack
-  if (!utcd_inited) {
-    tu_memclr(port_inited, sizeof(port_inited));
+  if (!_utcd_inited) {
+    tu_memclr(_port_inited, sizeof(_port_inited));
 
-    utcd_q = osal_queue_create(&utcd_qdef);
-    TU_ASSERT(utcd_q != NULL);
+    _utcd_q = osal_queue_create(&_utcd_qdef);
+    TU_ASSERT(_utcd_q != NULL);
 
-    utcd_inited = true;
+    _utcd_inited = true;
   }
 
   // skip if port already initialized
-  if ( port_inited[rhport] ) {
+  if ( _port_inited[rhport] ) {
     return true;
   }
 
@@ -79,10 +82,42 @@ bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
   TU_ASSERT(tcd_init(rhport, port_type));
   tcd_int_enable(rhport);
 
-  port_inited[rhport] = true;
+  _port_inited[rhport] = true;
   return true;
 }
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+//bool parse_message(uint8_t const * data, uint16_t len, pd_msg_t * msg) {
+//  // TODO
+//  (void) data;
+//  (void) len;
+//  (void) msg;
+//  return false;
+//}
+
+void tcd_event_handler(tcd_event_t const * event, bool in_isr) {
+  (void) in_isr;
+  switch(event->event_id) {
+    case TCD_EVENT_CC_CHANGED:
+      if (event->cc_changed.cc_state[0] || event->cc_changed.cc_state[1]) {
+        // Attach
+        tcd_rx_start(event->rhport, _rx_buf, sizeof(_rx_buf));
+      }else {
+        // Detach
+      }
+      break;
+
+    case TCD_EVENT_RX_COMPLETE:
+      // TODO process message here in ISR, move to thread later
+
+      // start new rx
+      tcd_rx_start(event->rhport, _rx_buf, sizeof(_rx_buf));
+      break;
+  }
+}
 
 //--------------------------------------------------------------------+
 //
@@ -90,7 +125,7 @@ bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
 void utcd_int_set(bool enabled) {
   // Disable all controllers since they shared the same event queue
   for (uint8_t p = 0; p < TUP_TYPEC_RHPORTS_NUM; p++) {
-    if ( port_inited[p] ) {
+    if ( _port_inited[p] ) {
       if (enabled) {
         tcd_int_enable(p);
       }else {
diff --git a/src/typec/utcd.h b/src/typec/utcd.h
index 06a62ef23..75ff6f1db 100644
--- a/src/typec/utcd.h
+++ b/src/typec/utcd.h
@@ -38,7 +38,7 @@ extern "C" {
 //--------------------------------------------------------------------+
 
 #ifndef CFG_TUC_TASK_QUEUE_SZ
-#define CFG_TUC_TASK_QUEUE_SZ   16
+#define CFG_TUC_TASK_QUEUE_SZ   8
 #endif
 
 

From bb4fb0543bab21e68748b359ec7d59e74cac1445 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 9 Jun 2023 19:38:50 +0700
Subject: [PATCH 1796/2085] able to parse SOURCE_CAP message from dfp

---
 src/typec/utcd.c | 56 ++++++++++++++++++++++++++++++++++++++------
 src/typec/utcd.h | 60 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 109 insertions(+), 7 deletions(-)

diff --git a/src/typec/utcd.c b/src/typec/utcd.c
index fb69b01e8..abbe8b43e 100644
--- a/src/typec/utcd.c
+++ b/src/typec/utcd.c
@@ -90,13 +90,50 @@ bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
 //
 //--------------------------------------------------------------------+
 
-//bool parse_message(uint8_t const * data, uint16_t len, pd_msg_t * msg) {
-//  // TODO
-//  (void) data;
-//  (void) len;
-//  (void) msg;
-//  return false;
-//}
+bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) {
+  (void) rhport;
+  uint8_t const* p_end = buf + len;
+  tusb_pd_header_t const* header = (tusb_pd_header_t const*) buf;
+  uint8_t const * ptr = buf + sizeof(tusb_pd_header_t);
+
+  if (header->n_data_obj == 0) {
+    // control message
+  } else {
+    // data message
+    switch (header->msg_type) {
+      case TUSB_PD_DATA_SOURCE_CAP: {
+        for(size_t i=0; i<header->n_data_obj; i++) {
+          TU_VERIFY(ptr < p_end);
+          uint32_t const pdo = tu_le32toh(tu_unaligned_read32(ptr));
+
+          switch ((pdo >> 30) & 0x03ul) {
+            case PD_PDO_TYPE_FIXED: {
+              pd_pdo_fixed_t const* fixed = (pd_pdo_fixed_t const*) &pdo;
+              TU_LOG3("[Fixed] %u mV %u mA\r\n", fixed->voltage_50mv*50, fixed->current_max_10ma*10);
+              break;
+            }
+
+            case PD_PDO_TYPE_BATTERY:
+              break;
+
+            case PD_PDO_TYPE_VARIABLE:
+              break;
+
+            case PD_PDO_TYPE_APDO:
+              break;
+          }
+
+          ptr += 4;
+        }
+        break;
+      }
+
+      default: break;
+    }
+  }
+
+  return true;
+}
 
 void tcd_event_handler(tcd_event_t const * event, bool in_isr) {
   (void) in_isr;
@@ -112,10 +149,15 @@ void tcd_event_handler(tcd_event_t const * event, bool in_isr) {
 
     case TCD_EVENT_RX_COMPLETE:
       // TODO process message here in ISR, move to thread later
+      if (event->rx_complete.result == XFER_RESULT_SUCCESS) {
+        parse_message(event->rhport, _rx_buf, event->rx_complete.xferred_bytes);
+      }
 
       // start new rx
       tcd_rx_start(event->rhport, _rx_buf, sizeof(_rx_buf));
       break;
+
+    default: break;
   }
 }
 
diff --git a/src/typec/utcd.h b/src/typec/utcd.h
index 75ff6f1db..dbc909592 100644
--- a/src/typec/utcd.h
+++ b/src/typec/utcd.h
@@ -41,6 +41,66 @@ extern "C" {
 #define CFG_TUC_TASK_QUEUE_SZ   8
 #endif
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// All table references are from USBPD Specification rev3.1 version 1.8
+enum {
+  PD_PDO_TYPE_FIXED = 0, // Vmin = Vmax
+  PD_PDO_TYPE_BATTERY,
+  PD_PDO_TYPE_VARIABLE, // non-battery
+  PD_PDO_TYPE_APDO, // Augmented Power Data Object
+};
+
+// Fixed Power Data Object (PDO) table 6-9
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_max_10ma          : 10; // [9..0] Max current in 10mA unit
+  uint32_t voltage_50mv              : 10; // [19..10] Voltage in 50mV unit
+  uint32_t current_peak              :  2; // [21..20] Peak current
+  uint32_t reserved                  :  1; // [22] Reserved
+  uint32_t epr_mode_capable          :  1; // [23] epr_mode_capable
+  uint32_t unchunked_ext_msg_support :  1; // [24] UnChunked Extended Message Supported
+  uint32_t dual_role_data            :  1; // [25] Dual Role Data
+  uint32_t usb_comm_capable          :  1; // [26] USB Communications Capable
+  uint32_t unconstrained_power       :  1; // [27] Unconstrained Power
+  uint32_t usb_suspend_supported     :  1; // [28] USB Suspend Supported
+  uint32_t dual_role_power           :  1; // [29] Dual Role Power
+  uint32_t type                      :  2; // [30] Fixed Supply type = PD_PDO_TYPE_FIXED
+} pd_pdo_fixed_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_fixed_t) == 4, "Invalid size");
+
+// Battery Power Data Object (PDO) table 6-12
+typedef struct TU_ATTR_PACKED {
+  uint32_t power_max_250mw   : 10; // [9..0] Max allowable power in 250mW unit
+  uint32_t voltage_min_50mv  : 10; // [19..10] Minimum voltage in 50mV unit
+  uint32_t voltage_max_50mv  : 10; // [29..20] Maximum voltage in 50mV unit
+  uint32_t type              :  2; // [31..30] Battery type = PD_PDO_TYPE_BATTERY
+} pd_pdo_battery_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_battery_t) == 4, "Invalid size");
+
+// Variable Power Data Object (PDO) table 6-11
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_max_10ma  : 10; // [9..0] Max current in 10mA unit
+  uint32_t voltage_min_50mv  : 10; // [19..10] Minimum voltage in 50mV unit
+  uint32_t voltage_max_50mv  : 10; // [29..20] Maximum voltage in 50mV unit
+  uint32_t type              :  2; // [31..30] Variable Supply type = PD_PDO_TYPE_VARIABLE
+} pd_pdo_variable_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_variable_t) == 4, "Invalid size");
+
+// Augmented Power Data Object (PDO) table 6-13
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_max_50ma  :  7; // [6..0] Max current in 50mA unit
+  uint32_t reserved1         :  1; // [7] Reserved
+  uint32_t voltage_min_100mv :  8; // [15..8] Minimum Voltage in 100mV unit
+  uint32_t reserved2         :  1; // [16] Reserved
+  uint32_t voltage_max_100mv :  8; // [24..17] Maximum Voltage in 100mV unit
+  uint32_t reserved3         :  2; // [26..25] Reserved
+  uint32_t pps_power_limited :  1; // [27] PPS Power Limited
+  uint32_t spr_programmable  :  2; // [29..28] SPR Programmable Power Supply
+  uint32_t type              :  2; // [31..30] Augmented Power Data Object = PD_PDO_TYPE_APDO
+} pd_pdo_apdo_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_apdo_t) == 4, "Invalid size");
 
 //--------------------------------------------------------------------+
 // Application API

From debde4cc97cb7c6c13d62d0e3bbe195c80bfec9f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jun 2023 12:14:55 +0700
Subject: [PATCH 1797/2085] response with request safe5v, get passed PS_READY

---
 src/common/tusb_types.h             | 10 ++++
 src/portable/st/typec/typec_stm32.c | 78 +++++++++++++++++++++++------
 src/typec/tcd.h                     | 17 ++++++-
 src/typec/utcd.c                    | 59 ++++++++++++++++++++++
 src/typec/utcd.h                    | 34 ++++++++++++-
 5 files changed, 180 insertions(+), 18 deletions(-)

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index c92320e5c..cad633ee4 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -562,6 +562,16 @@ enum {
   TUSB_PD_REV30	= 0x2,
 };
 
+enum {
+  TUSB_PD_DATA_ROLE_UFP	= 0x0,
+  TUSB_PD_DATA_ROLE_DFP	= 0x1,
+};
+
+enum {
+  TUSB_PD_POWER_ROLE_SINK	= 0x0,
+  TUSB_PD_POWER_ROLE_SOURCE	= 0x1,
+};
+
 typedef struct TU_ATTR_PACKED {
   uint16_t msg_type   : 5; // [0:4]
   uint16_t data_role  : 1; // [5] SOP only: 0 UFP, 1 DFP
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
index 1dba54492..9b3b21707 100644
--- a/src/portable/st/typec/typec_stm32.c
+++ b/src/portable/st/typec/typec_stm32.c
@@ -63,6 +63,9 @@ enum {
 
 
 static uint8_t const* _rx_buf;
+static uint8_t const* _tx_pending_buf;
+static uint16_t _tx_pending_bytes;
+static uint16_t _tx_xferring_bytes;
 
 static tusb_pd_header_t _good_crc = {
     .msg_type   = TUSB_PD_CTRL_GOOD_CRC,
@@ -141,10 +144,21 @@ TU_ATTR_ALWAYS_INLINE static inline void dma_stop(uint8_t rhport, bool is_rx) {
   dma_ch->CCR &= ~DMA_CCR_EN;
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(uint8_t rhport, bool is_rx) {
+  DMA_Channel_TypeDef* dma_ch = (DMA_Channel_TypeDef*) dma_get_addr(rhport, is_rx);
+  return dma_ch->CCR & DMA_CCR_EN;
+}
+
+
 TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) {
   UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
   UCPD1->TX_PAYSZ = len;
   dma_start(rhport, false, buf, len);
+  UCPD1->CR |= UCPD_CR_TXSEND;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void dma_tx_stop(uint8_t rhport) {
+  dma_stop(rhport, false);
 }
 
 //--------------------------------------------------------------------+
@@ -203,11 +217,23 @@ bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
   return true;
 }
 
-bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes) {
+bool tcd_msg_send(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes) {
   (void) rhport;
-  (void) buffer;
-  (void) total_bytes;
-  return false;
+
+  if (dma_enabled(rhport, false)) {
+    // DMA is busy, probably sending GoodCRC, save as pending TX
+    _tx_pending_buf = buffer;
+    _tx_pending_bytes = total_bytes;
+  }else {
+    // DMA is free, start sending
+    _tx_pending_buf = NULL;
+    _tx_pending_bytes = 0;
+
+    _tx_xferring_bytes = total_bytes;
+    dma_tx_start(rhport, buffer, total_bytes);
+  }
+
+  return true;
 }
 
 void tcd_int_handler(uint8_t rhport) {
@@ -275,6 +301,8 @@ void tcd_int_handler(uint8_t rhport) {
   // Received full message
   if (sr & UCPD_SR_RXMSGEND) {
     TU_LOG3("RX MSG END\n");
+
+    // stop TX
     dma_stop(rhport, true);
 
     uint8_t result;
@@ -283,7 +311,6 @@ void tcd_int_handler(uint8_t rhport) {
       // response with good crc
       _good_crc.msg_id = ((tusb_pd_header_t const*) _rx_buf)->msg_id;
       dma_tx_start(rhport, &_good_crc, 2);
-      UCPD1->CR |= UCPD_CR_TXSEND;
 
       result = XFER_RESULT_SUCCESS;
     }else {
@@ -305,19 +332,38 @@ void tcd_int_handler(uint8_t rhport) {
   }
 
   //------------- TX -------------//
-  if (sr & UCPD_SR_TXMSGSENT) {
-    TU_LOG3("TX MSG SENT\n");
-    // all byte sent
-    dma_stop(rhport, false);
+  // All tx events: complete and error
+  if (sr & (UCPD_SR_TXMSGSENT | (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND))) {
+    // force TX stop
+    dma_tx_stop(rhport);
 
-    // ack
-    UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
-  }
+    uint16_t const xferred_bytes = _tx_xferring_bytes - UCPD1->TX_PAYSZ;
+    uint8_t result;
 
-  if (sr & (UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND)) {
-    TU_LOG3("TX Error\n");
-    dma_stop(rhport, false);
-    UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND;
+    if ( sr & UCPD_SR_TXMSGSENT ) {
+      TU_LOG3("TX MSG SENT\n");
+      result = XFER_RESULT_SUCCESS;
+      // ack
+      UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
+    }else {
+      TU_LOG3("TX Error\n");
+      result = XFER_RESULT_FAILED;
+      // ack
+      UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND;
+    }
+
+    // start pending TX if any
+    if (_tx_pending_buf && _tx_pending_bytes ) {
+      // Start the pending TX
+      dma_tx_start(rhport, _tx_pending_buf, _tx_pending_bytes);
+
+      // clear pending
+      _tx_pending_buf = NULL;
+      _tx_pending_bytes = 0;
+    }
+
+    // notify stack
+    tcd_event_tx_complete(rhport, xferred_bytes, result, true);
   }
 }
 
diff --git a/src/typec/tcd.h b/src/typec/tcd.h
index 41dceaa74..b131d6ba9 100644
--- a/src/typec/tcd.h
+++ b/src/typec/tcd.h
@@ -43,6 +43,7 @@ enum {
   TCD_EVENT_INVALID = 0,
   TCD_EVENT_CC_CHANGED,
   TCD_EVENT_RX_COMPLETE,
+  TCD_EVENT_TX_COMPLETE,
 };
 
 
@@ -84,7 +85,7 @@ void tcd_int_handler(uint8_t rhport);
 //--------------------------------------------------------------------+
 
 bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes);
-bool tcd_tx_start(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes);
+bool tcd_msg_send(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes);
 
 //--------------------------------------------------------------------+
 // Event API (implemented by stack)
@@ -120,4 +121,18 @@ void tcd_event_rx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t resul
   tcd_event_handler(&event, in_isr);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline
+void tcd_event_tx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t result, bool in_isr) {
+  tcd_event_t event = {
+      .rhport   = rhport,
+      .event_id = TCD_EVENT_TX_COMPLETE,
+      .rx_complete = {
+          .xferred_bytes = xferred_bytes,
+          .result        = result
+      }
+  };
+
+  tcd_event_handler(&event, in_isr);
+}
+
 #endif
diff --git a/src/typec/utcd.c b/src/typec/utcd.c
index abbe8b43e..09031e5c9 100644
--- a/src/typec/utcd.c
+++ b/src/typec/utcd.c
@@ -53,6 +53,7 @@ static bool _port_inited[TUP_TYPEC_RHPORTS_NUM];
 
 // Max possible PD size is 262 bytes
 static uint8_t _rx_buf[262] TU_ATTR_ALIGNED(4);
+static uint8_t _tx_buf[100] TU_ATTR_ALIGNED(4);
 
 //--------------------------------------------------------------------+
 //
@@ -90,6 +91,19 @@ bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
 //
 //--------------------------------------------------------------------+
 
+bool utcd_msg_send(uint8_t rhport, tusb_pd_header_t const* header, void const* data) {
+  // copy header
+  memcpy(_tx_buf, header, sizeof(tusb_pd_header_t));
+
+  // copy data objcet if available
+  uint16_t const n_data_obj = header->n_data_obj;
+  if (n_data_obj > 0) {
+    memcpy(_tx_buf + sizeof(tusb_pd_header_t), data, n_data_obj * 4);
+  }
+
+  return tcd_msg_send(rhport, _tx_buf, sizeof(tusb_pd_header_t) + n_data_obj * 4);
+}
+
 bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) {
   (void) rhport;
   uint8_t const* p_end = buf + len;
@@ -98,10 +112,28 @@ bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) {
 
   if (header->n_data_obj == 0) {
     // control message
+    switch (header->msg_type) {
+      case TUSB_PD_CTRL_GOOD_CRC:
+        break;
+
+      case TUSB_PD_CTRL_ACCEPT:
+        break;
+
+      case TUSB_PD_CTRL_REJECT:
+        break;
+
+      case TUSB_PD_CTRL_PS_RDY:
+        break;
+
+      default: break;
+    }
   } else {
     // data message
     switch (header->msg_type) {
       case TUSB_PD_DATA_SOURCE_CAP: {
+        // Examine source capability and select a suitable PDO (starting from 1 with safe5v)
+        uint8_t obj_pos = 1;
+
         for(size_t i=0; i<header->n_data_obj; i++) {
           TU_VERIFY(ptr < p_end);
           uint32_t const pdo = tu_le32toh(tu_unaligned_read32(ptr));
@@ -125,6 +157,33 @@ bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) {
 
           ptr += 4;
         }
+
+        // Send request with selected PDO position as response to Source Cap
+        pd_rdo_fixed_variable_t rdo = {
+            .current_extremum_10ma = 50, // max 500mA
+            .current_operate_10ma = 30, // 300mA
+            .reserved = 0,
+            .epr_mode_capable = 0,
+            .unchunked_ext_msg_support = 0,
+            .no_usb_suspend = 0,
+            .usb_comm_capable = 1,
+            .capability_mismatch = 0,
+            .give_back_flag = 0, // exteremum is max
+            .object_position = obj_pos,
+        };
+
+        tusb_pd_header_t const req_header = {
+            .msg_type = TUSB_PD_DATA_REQUEST,
+            .data_role = TUSB_PD_DATA_ROLE_UFP,
+            .specs_rev = TUSB_PD_REV20,
+            .power_role = TUSB_PD_POWER_ROLE_SINK,
+            .msg_id = 0,
+            .n_data_obj = 1,
+            .extended = 0,
+        };
+
+        utcd_msg_send(rhport, &req_header, &rdo);
+
         break;
       }
 
diff --git a/src/typec/utcd.h b/src/typec/utcd.h
index dbc909592..bb1523253 100644
--- a/src/typec/utcd.h
+++ b/src/typec/utcd.h
@@ -42,7 +42,7 @@ extern "C" {
 #endif
 
 //--------------------------------------------------------------------+
-//
+// Source Capability
 //--------------------------------------------------------------------+
 
 // All table references are from USBPD Specification rev3.1 version 1.8
@@ -102,6 +102,38 @@ typedef struct TU_ATTR_PACKED {
 } pd_pdo_apdo_t;
 TU_VERIFY_STATIC(sizeof(pd_pdo_apdo_t) == 4, "Invalid size");
 
+//--------------------------------------------------------------------+
+// Request
+//--------------------------------------------------------------------+
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_extremum_10ma     : 10; // [9..0] Max (give back = 0) or Min (give back = 1) current in 10mA unit
+  uint32_t current_operate_10ma      : 10; // [19..10] Operating current in 10mA unit
+  uint32_t reserved                  :  2; // [21..20] Reserved
+  uint32_t epr_mode_capable          :  1; // [22] EPR mode capable
+  uint32_t unchunked_ext_msg_support :  1; // [23] UnChunked Extended Message Supported
+  uint32_t no_usb_suspend            :  1; // [24] No USB Suspend
+  uint32_t usb_comm_capable          :  1; // [25] USB Communications Capable
+  uint32_t capability_mismatch       :  1; // [26] Capability Mismatch
+  uint32_t give_back_flag            :  1; // [27] GiveBack Flag: 0 = Max, 1 = Min
+  uint32_t object_position           :  4; // [31..28] Object Position
+} pd_rdo_fixed_variable_t;
+TU_VERIFY_STATIC(sizeof(pd_rdo_fixed_variable_t) == 4, "Invalid size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t power_extremum_250mw      : 10; // [9..0] Max (give back = 0) or Min (give back = 1) operating power in 250mW unit
+  uint32_t power_operate_250mw       : 10; // [19..10] Operating power in 250mW unit
+  uint32_t reserved                  :  2; // [21..20] Reserved
+  uint32_t epr_mode_capable          :  1; // [22] EPR mode capable
+  uint32_t unchunked_ext_msg_support :  1; // [23] UnChunked Extended Message Supported
+  uint32_t no_usb_suspend            :  1; // [24] No USB Suspend
+  uint32_t usb_comm_capable          :  1; // [25] USB Communications Capable
+  uint32_t capability_mismatch       :  1; // [26] Capability Mismatch
+  uint32_t give_back_flag            :  1; // [27] GiveBack Flag: 0 = Max, 1 = Min
+  uint32_t object_position           :  4; // [31..28] Object Position
+} pd_rdo_battery_t;
+TU_VERIFY_STATIC(sizeof(pd_rdo_battery_t) == 4, "Invalid size");
+
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+

From c28503060c0c3cb09d8e2ce63d1b0009affbdf72 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jun 2023 14:57:50 +0700
Subject: [PATCH 1798/2085] ad pd_types.h

---
 src/common/tusb_types.h             |  96 +----------
 src/portable/st/typec/typec_stm32.c |  13 +-
 src/typec/pd_types.h                | 237 ++++++++++++++++++++++++++++
 src/typec/tcd.h                     |  10 +-
 src/typec/utcd.c                    |  38 ++---
 src/typec/utcd.h                    | 101 +-----------
 6 files changed, 278 insertions(+), 217 deletions(-)
 create mode 100644 src/typec/pd_types.h

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index cad633ee4..fab680989 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -480,6 +480,7 @@ typedef struct TU_ATTR_PACKED
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
+
 typedef struct TU_ATTR_PACKED{
   union {
     struct TU_ATTR_PACKED {
@@ -499,101 +500,6 @@ typedef struct TU_ATTR_PACKED{
 
 TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
 
-//--------------------------------------------------------------------+
-// TYPE-C
-//--------------------------------------------------------------------+
-
-typedef enum {
-  TUSB_TYPEC_PORT_SRC,
-  TUSB_TYPEC_PORT_SNK,
-  TUSB_TYPEC_PORT_DRP
-} tusb_typec_port_type_t;
-
-typedef enum {
-  TUSB_PD_CTRL_RESERVED = 0,            // 0b00000: 0
-  TUSB_PD_CTRL_GOOD_CRC,                // 0b00001: 1
-  TUSB_PD_CTRL_GO_TO_MIN,               // 0b00010: 2
-  TUSB_PD_CTRL_ACCEPT,                  // 0b00011: 3
-  TUSB_PD_CTRL_REJECT,                  // 0b00100: 4
-  TUSB_PD_CTRL_PING,                    // 0b00101: 5
-  TUSB_PD_CTRL_PS_RDY,                  // 0b00110: 6
-  TUSB_PD_CTRL_GET_SOURCE_CAP,          // 0b00111: 7
-  TUSB_PD_CTRL_GET_SINK_CAP,            // 0b01000: 8
-  TUSB_PD_CTRL_DR_SWAP,                 // 0b01001: 9
-  TUSB_PD_CTRL_PR_SWAP,                 // 0b01010: 10
-  TUSB_PD_CTRL_VCONN_SWAP,              // 0b01011: 11
-  TUSB_PD_CTRL_WAIT,                    // 0b01100: 12
-  TUSB_PD_CTRL_SOFT_RESET,              // 0b01101: 13
-  TUSB_PD_CTRL_DATA_RESET,              // 0b01110: 14
-  TUSB_PD_CTRL_DATA_RESET_COMPLETE,     // 0b01111: 15
-  TUSB_PD_CTRL_NOT_SUPPORTED,           // 0b10000: 16
-  TUSB_PD_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17
-  TUSB_PD_CTRL_GET_STATUS,              // 0b10010: 18
-  TUSB_PD_CTRL_FR_SWAP,                 // 0b10011: 19
-  TUSB_PD_CTRL_GET_PPS_STATUS,          // 0b10100: 20
-  TUSB_PD_CTRL_GET_COUNTRY_CODES,       // 0b10101: 21
-  TUSB_PD_CTRL_GET_SINK_CAP_EXTENDED,   // 0b10110: 22
-  TUSB_PD_CTRL_GET_SOURCE_INFO,         // 0b10111: 23
-  TUSB_PD_CTRL_REVISION,                // 0b11000: 24
-} tusb_pd_ctrl_type_t;
-
-typedef enum {
-  TUSB_PD_DATA_RESERVED = 0,     // 0b00000: 0
-  TUSB_PD_DATA_SOURCE_CAP,       // 0b00001: 1
-  TUSB_PD_DATA_REQUEST,          // 0b00010: 2
-  TUSB_PD_DATA_BIST,             // 0b00011: 3
-  TUSB_PD_DATA_SINK_CAP,         // 0b00100: 4
-  TUSB_PD_DATA_BATTERY_STATUS,   // 0b00101: 5
-  TUSB_PD_DATA_ALERT,            // 0b00110: 6
-  TUSB_PD_DATA_GET_COUNTRY_INFO, // 0b00111: 7
-  TUSB_PD_DATA_ENTER_USB,        // 0b01000: 8
-  TUSB_PD_DATA_EPR_REQUEST,      // 0b01001: 9
-  TUSB_PD_DATA_EPR_MODE,         // 0b01010: 10
-  TUSB_PD_DATA_SRC_INFO,         // 0b01011: 11
-  TUSB_PD_DATA_REVISION,         // 0b01100: 12
-  TUSB_PD_DATA_RESERVED_13,      // 0b01101: 13
-  TUSB_PD_DATA_RESERVED_14,      // 0b01110: 14
-  TUSB_PD_DATA_VENDOR_DEFINED,   // 0b01111: 15
-} tusb_pd_data_type_t;
-
-enum {
-  TUSB_PD_REV10	= 0x0,
-  TUSB_PD_REV20	= 0x1,
-  TUSB_PD_REV30	= 0x2,
-};
-
-enum {
-  TUSB_PD_DATA_ROLE_UFP	= 0x0,
-  TUSB_PD_DATA_ROLE_DFP	= 0x1,
-};
-
-enum {
-  TUSB_PD_POWER_ROLE_SINK	= 0x0,
-  TUSB_PD_POWER_ROLE_SOURCE	= 0x1,
-};
-
-typedef struct TU_ATTR_PACKED {
-  uint16_t msg_type   : 5; // [0:4]
-  uint16_t data_role  : 1; // [5] SOP only: 0 UFP, 1 DFP
-  uint16_t specs_rev  : 2; // [6:7]
-  uint16_t power_role : 1; // [8] SOP only: 0 Sink, 1 Source
-  uint16_t msg_id     : 3; // [9:11]
-  uint16_t n_data_obj : 3; // [12:14]
-  uint16_t extended   : 1; // [15]
-} tusb_pd_header_t;
-
-TU_VERIFY_STATIC( sizeof(tusb_pd_header_t) == 2, "size is not correct");
-
-typedef struct TU_ATTR_PACKED {
-  uint16_t data_size     : 9; // [0:8]
-  uint16_t reserved      : 1; // [9]
-  uint16_t request_chunk : 1; // [10]
-  uint16_t chunk_number  : 4; // [11:14]
-  uint16_t chunked       : 1; // [15]
-} tusb_pd_header_extended_t;
-
-TU_VERIFY_STATIC( sizeof(tusb_pd_header_extended_t) == 2, "size is not correct");
-
 
 TU_ATTR_PACKED_END  // End of all packed definitions
 TU_ATTR_BIT_FIELD_ORDER_END
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
index 9b3b21707..b09dc5bae 100644
--- a/src/portable/st/typec/typec_stm32.c
+++ b/src/portable/st/typec/typec_stm32.c
@@ -67,10 +67,10 @@ static uint8_t const* _tx_pending_buf;
 static uint16_t _tx_pending_bytes;
 static uint16_t _tx_xferring_bytes;
 
-static tusb_pd_header_t _good_crc = {
-    .msg_type   = TUSB_PD_CTRL_GOOD_CRC,
+static pd_header_t _good_crc = {
+    .msg_type   = PD_CTRL_GOOD_CRC,
     .data_role  = 0, // UFP
-    .specs_rev  = TUSB_PD_REV20,
+    .specs_rev  = PD_REV_20,
     .power_role = 0, // Sink
     .msg_id     = 0,
     .n_data_obj = 0,
@@ -149,7 +149,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(uint8_t rhport, bool is_rx)
   return dma_ch->CCR & DMA_CCR_EN;
 }
 
-
 TU_ATTR_ALWAYS_INLINE static inline void dma_tx_start(uint8_t rhport, void const* buf, uint16_t len) {
   UCPD1->TX_ORDSET = PHY_ORDERED_SET_SOP;
   UCPD1->TX_PAYSZ = len;
@@ -165,7 +164,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dma_tx_stop(uint8_t rhport) {
 //
 //--------------------------------------------------------------------+
 
-bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
+bool tcd_init(uint8_t rhport, uint32_t port_type) {
   (void) rhport;
 
   // Init DMA for RX, TX
@@ -211,7 +210,7 @@ void tcd_int_disable(uint8_t rhport) {
   NVIC_DisableIRQ(UCPD1_IRQn);
 }
 
-bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
+bool tcd_msg_receive(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes) {
   _rx_buf = buffer;
   dma_start(rhport, true, buffer, total_bytes);
   return true;
@@ -309,7 +308,7 @@ void tcd_int_handler(uint8_t rhport) {
 
     if (!(sr & UCPD_SR_RXERR)) {
       // response with good crc
-      _good_crc.msg_id = ((tusb_pd_header_t const*) _rx_buf)->msg_id;
+      _good_crc.msg_id = ((pd_header_t const*) _rx_buf)->msg_id;
       dma_tx_start(rhport, &_good_crc, 2);
 
       result = XFER_RESULT_SUCCESS;
diff --git a/src/typec/pd_types.h b/src/typec/pd_types.h
new file mode 100644
index 000000000..1b2968f65
--- /dev/null
+++ b/src/typec/pd_types.h
@@ -0,0 +1,237 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_PD_TYPES_H_
+#define _TUSB_PD_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "common/tusb_compiler.h"
+
+// Start of all packed definitions for compiler without per-type packed
+TU_ATTR_PACKED_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
+
+//--------------------------------------------------------------------+
+// TYPE-C
+//--------------------------------------------------------------------+
+
+typedef enum {
+  TUSB_TYPEC_PORT_SRC,
+  TUSB_TYPEC_PORT_SNK,
+  TUSB_TYPEC_PORT_DRP
+} tusb_typec_port_type_t;
+
+enum {
+  PD_CTRL_RESERVED = 0,            // 0b00000: 0
+  PD_CTRL_GOOD_CRC,                // 0b00001: 1
+  PD_CTRL_GO_TO_MIN,               // 0b00010: 2
+  PD_CTRL_ACCEPT,                  // 0b00011: 3
+  PD_CTRL_REJECT,                  // 0b00100: 4
+  PD_CTRL_PING,                    // 0b00101: 5
+  PD_CTRL_PS_READY,                // 0b00110: 6
+  PD_CTRL_GET_SOURCE_CAP,          // 0b00111: 7
+  PD_CTRL_GET_SINK_CAP,            // 0b01000: 8
+  PD_CTRL_DR_SWAP,                 // 0b01001: 9
+  PD_CTRL_PR_SWAP,                 // 0b01010: 10
+  PD_CTRL_VCONN_SWAP,              // 0b01011: 11
+  PD_CTRL_WAIT,                    // 0b01100: 12
+  PD_CTRL_SOFT_RESET,              // 0b01101: 13
+  PD_CTRL_DATA_RESET,              // 0b01110: 14
+  PD_CTRL_DATA_RESET_COMPLETE,     // 0b01111: 15
+  PD_CTRL_NOT_SUPPORTED,           // 0b10000: 16
+  PD_CTRL_GET_SOURCE_CAP_EXTENDED, // 0b10001: 17
+  PD_CTRL_GET_STATUS,              // 0b10010: 18
+  PD_CTRL_FR_SWAP,                 // 0b10011: 19
+  PD_CTRL_GET_PPS_STATUS,          // 0b10100: 20
+  PD_CTRL_GET_COUNTRY_CODES,       // 0b10101: 21
+  PD_CTRL_GET_SINK_CAP_EXTENDED,   // 0b10110: 22
+  PD_CTRL_GET_SOURCE_INFO,         // 0b10111: 23
+  PD_CTRL_REVISION,                // 0b11000: 24
+};
+
+enum {
+  PD_DATA_RESERVED = 0,     // 0b00000: 0
+  PD_DATA_SOURCE_CAP,       // 0b00001: 1
+  PD_DATA_REQUEST,          // 0b00010: 2
+  PD_DATA_BIST,             // 0b00011: 3
+  PD_DATA_SINK_CAP,         // 0b00100: 4
+  PD_DATA_BATTERY_STATUS,   // 0b00101: 5
+  PD_DATA_ALERT,            // 0b00110: 6
+  PD_DATA_GET_COUNTRY_INFO, // 0b00111: 7
+  PD_DATA_ENTER_USB,        // 0b01000: 8
+  PD_DATA_EPR_REQUEST,      // 0b01001: 9
+  PD_DATA_EPR_MODE,         // 0b01010: 10
+  PD_DATA_SRC_INFO,         // 0b01011: 11
+  PD_DATA_REVISION,         // 0b01100: 12
+  PD_DATA_RESERVED_13,      // 0b01101: 13
+  PD_DATA_RESERVED_14,      // 0b01110: 14
+  PD_DATA_VENDOR_DEFINED,   // 0b01111: 15
+};
+
+enum {
+  PD_REV_10	= 0x0,
+  PD_REV_20	= 0x1,
+  PD_REV_30	= 0x2,
+};
+
+enum {
+  PD_DATA_ROLE_UFP	= 0x0,
+  PD_DATA_ROLE_DFP	= 0x1,
+};
+
+enum {
+  PD_POWER_ROLE_SINK	= 0x0,
+  PD_POWER_ROLE_SOURCE	= 0x1,
+};
+
+typedef struct TU_ATTR_PACKED {
+  uint16_t msg_type   : 5; // [0:4]
+  uint16_t data_role  : 1; // [5] SOP only: 0 UFP, 1 DFP
+  uint16_t specs_rev  : 2; // [6:7]
+  uint16_t power_role : 1; // [8] SOP only: 0 Sink, 1 Source
+  uint16_t msg_id     : 3; // [9:11]
+  uint16_t n_data_obj : 3; // [12:14]
+  uint16_t extended   : 1; // [15]
+} pd_header_t;
+TU_VERIFY_STATIC(sizeof(pd_header_t) == 2, "size is not correct");
+
+typedef struct TU_ATTR_PACKED {
+  uint16_t data_size     : 9; // [0:8]
+  uint16_t reserved      : 1; // [9]
+  uint16_t request_chunk : 1; // [10]
+  uint16_t chunk_number  : 4; // [11:14]
+  uint16_t chunked       : 1; // [15]
+} pd_header_extended_t;
+TU_VERIFY_STATIC(sizeof(pd_header_extended_t) == 2, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Source Capability
+//--------------------------------------------------------------------+
+
+// All table references are from USBPD Specification rev3.1 version 1.8
+enum {
+  PD_PDO_TYPE_FIXED = 0, // Vmin = Vmax
+  PD_PDO_TYPE_BATTERY,
+  PD_PDO_TYPE_VARIABLE, // non-battery
+  PD_PDO_TYPE_APDO, // Augmented Power Data Object
+};
+
+// Fixed Power Data Object (PDO) table 6-9
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_max_10ma          : 10; // [9..0] Max current in 10mA unit
+  uint32_t voltage_50mv              : 10; // [19..10] Voltage in 50mV unit
+  uint32_t current_peak              :  2; // [21..20] Peak current
+  uint32_t reserved                  :  1; // [22] Reserved
+  uint32_t epr_mode_capable          :  1; // [23] epr_mode_capable
+  uint32_t unchunked_ext_msg_support :  1; // [24] UnChunked Extended Message Supported
+  uint32_t dual_role_data            :  1; // [25] Dual Role Data
+  uint32_t usb_comm_capable          :  1; // [26] USB Communications Capable
+  uint32_t unconstrained_power       :  1; // [27] Unconstrained Power
+  uint32_t usb_suspend_supported     :  1; // [28] USB Suspend Supported
+  uint32_t dual_role_power           :  1; // [29] Dual Role Power
+  uint32_t type                      :  2; // [30] Fixed Supply type = PD_PDO_TYPE_FIXED
+} pd_pdo_fixed_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_fixed_t) == 4, "Invalid size");
+
+// Battery Power Data Object (PDO) table 6-12
+typedef struct TU_ATTR_PACKED {
+  uint32_t power_max_250mw   : 10; // [9..0] Max allowable power in 250mW unit
+  uint32_t voltage_min_50mv  : 10; // [19..10] Minimum voltage in 50mV unit
+  uint32_t voltage_max_50mv  : 10; // [29..20] Maximum voltage in 50mV unit
+  uint32_t type              :  2; // [31..30] Battery type = PD_PDO_TYPE_BATTERY
+} pd_pdo_battery_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_battery_t) == 4, "Invalid size");
+
+// Variable Power Data Object (PDO) table 6-11
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_max_10ma  : 10; // [9..0] Max current in 10mA unit
+  uint32_t voltage_min_50mv  : 10; // [19..10] Minimum voltage in 50mV unit
+  uint32_t voltage_max_50mv  : 10; // [29..20] Maximum voltage in 50mV unit
+  uint32_t type              :  2; // [31..30] Variable Supply type = PD_PDO_TYPE_VARIABLE
+} pd_pdo_variable_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_variable_t) == 4, "Invalid size");
+
+// Augmented Power Data Object (PDO) table 6-13
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_max_50ma  :  7; // [6..0] Max current in 50mA unit
+  uint32_t reserved1         :  1; // [7] Reserved
+  uint32_t voltage_min_100mv :  8; // [15..8] Minimum Voltage in 100mV unit
+  uint32_t reserved2         :  1; // [16] Reserved
+  uint32_t voltage_max_100mv :  8; // [24..17] Maximum Voltage in 100mV unit
+  uint32_t reserved3         :  2; // [26..25] Reserved
+  uint32_t pps_power_limited :  1; // [27] PPS Power Limited
+  uint32_t spr_programmable  :  2; // [29..28] SPR Programmable Power Supply
+  uint32_t type              :  2; // [31..30] Augmented Power Data Object = PD_PDO_TYPE_APDO
+} pd_pdo_apdo_t;
+TU_VERIFY_STATIC(sizeof(pd_pdo_apdo_t) == 4, "Invalid size");
+
+//--------------------------------------------------------------------+
+// Request
+//--------------------------------------------------------------------+
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t current_extremum_10ma     : 10; // [9..0] Max (give back = 0) or Min (give back = 1) current in 10mA unit
+  uint32_t current_operate_10ma      : 10; // [19..10] Operating current in 10mA unit
+  uint32_t reserved                  :  2; // [21..20] Reserved
+  uint32_t epr_mode_capable          :  1; // [22] EPR mode capable
+  uint32_t unchunked_ext_msg_support :  1; // [23] UnChunked Extended Message Supported
+  uint32_t no_usb_suspend            :  1; // [24] No USB Suspend
+  uint32_t usb_comm_capable          :  1; // [25] USB Communications Capable
+  uint32_t capability_mismatch       :  1; // [26] Capability Mismatch
+  uint32_t give_back_flag            :  1; // [27] GiveBack Flag: 0 = Max, 1 = Min
+  uint32_t object_position           :  4; // [31..28] Object Position
+} pd_rdo_fixed_variable_t;
+TU_VERIFY_STATIC(sizeof(pd_rdo_fixed_variable_t) == 4, "Invalid size");
+
+typedef struct TU_ATTR_PACKED {
+  uint32_t power_extremum_250mw      : 10; // [9..0] Max (give back = 0) or Min (give back = 1) operating power in 250mW unit
+  uint32_t power_operate_250mw       : 10; // [19..10] Operating power in 250mW unit
+  uint32_t reserved                  :  2; // [21..20] Reserved
+  uint32_t epr_mode_capable          :  1; // [22] EPR mode capable
+  uint32_t unchunked_ext_msg_support :  1; // [23] UnChunked Extended Message Supported
+  uint32_t no_usb_suspend            :  1; // [24] No USB Suspend
+  uint32_t usb_comm_capable          :  1; // [25] USB Communications Capable
+  uint32_t capability_mismatch       :  1; // [26] Capability Mismatch
+  uint32_t give_back_flag            :  1; // [27] GiveBack Flag: 0 = Max, 1 = Min
+  uint32_t object_position           :  4; // [31..28] Object Position
+} pd_rdo_battery_t;
+TU_VERIFY_STATIC(sizeof(pd_rdo_battery_t) == 4, "Invalid size");
+
+
+TU_ATTR_PACKED_END  // End of all packed definitions
+TU_ATTR_BIT_FIELD_ORDER_END
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/src/typec/tcd.h b/src/typec/tcd.h
index b131d6ba9..ee73943bd 100644
--- a/src/typec/tcd.h
+++ b/src/typec/tcd.h
@@ -28,6 +28,8 @@
 #define _TUSB_TCD_H_
 
 #include "common/tusb_common.h"
+#include "pd_types.h"
+
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
 
@@ -69,7 +71,7 @@ typedef struct {
 //--------------------------------------------------------------------+
 
 // Initialize controller
-bool tcd_init(uint8_t rhport, tusb_typec_port_type_t port_type);
+bool tcd_init(uint8_t rhport, uint32_t port_type);
 
 // Enable interrupt
 void tcd_int_enable (uint8_t rhport);
@@ -84,7 +86,7 @@ void tcd_int_handler(uint8_t rhport);
 //
 //--------------------------------------------------------------------+
 
-bool tcd_rx_start(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes);
+bool tcd_msg_receive(uint8_t rhport, uint8_t* buffer, uint16_t total_bytes);
 bool tcd_msg_send(uint8_t rhport, uint8_t const* buffer, uint16_t total_bytes);
 
 //--------------------------------------------------------------------+
@@ -135,4 +137,8 @@ void tcd_event_tx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t resul
   tcd_event_handler(&event, in_isr);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif
diff --git a/src/typec/utcd.c b/src/typec/utcd.c
index 09031e5c9..439fe89b9 100644
--- a/src/typec/utcd.c
+++ b/src/typec/utcd.c
@@ -62,7 +62,7 @@ bool tuc_inited(uint8_t rhport) {
   return _utcd_inited && _port_inited[rhport];
 }
 
-bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
+bool tuc_init(uint8_t rhport, uint32_t port_type) {
   // Initialize stack
   if (!_utcd_inited) {
     tu_memclr(_port_inited, sizeof(_port_inited));
@@ -91,38 +91,38 @@ bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type) {
 //
 //--------------------------------------------------------------------+
 
-bool utcd_msg_send(uint8_t rhport, tusb_pd_header_t const* header, void const* data) {
+bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data) {
   // copy header
-  memcpy(_tx_buf, header, sizeof(tusb_pd_header_t));
+  memcpy(_tx_buf, header, sizeof(pd_header_t));
 
   // copy data objcet if available
   uint16_t const n_data_obj = header->n_data_obj;
   if (n_data_obj > 0) {
-    memcpy(_tx_buf + sizeof(tusb_pd_header_t), data, n_data_obj * 4);
+    memcpy(_tx_buf + sizeof(pd_header_t), data, n_data_obj * 4);
   }
 
-  return tcd_msg_send(rhport, _tx_buf, sizeof(tusb_pd_header_t) + n_data_obj * 4);
+  return tcd_msg_send(rhport, _tx_buf, sizeof(pd_header_t) + n_data_obj * 4);
 }
 
 bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) {
   (void) rhport;
   uint8_t const* p_end = buf + len;
-  tusb_pd_header_t const* header = (tusb_pd_header_t const*) buf;
-  uint8_t const * ptr = buf + sizeof(tusb_pd_header_t);
+  pd_header_t const* header = (pd_header_t const*) buf;
+  uint8_t const * ptr = buf + sizeof(pd_header_t);
 
   if (header->n_data_obj == 0) {
     // control message
     switch (header->msg_type) {
-      case TUSB_PD_CTRL_GOOD_CRC:
+      case PD_CTRL_GOOD_CRC:
         break;
 
-      case TUSB_PD_CTRL_ACCEPT:
+      case PD_CTRL_ACCEPT:
         break;
 
-      case TUSB_PD_CTRL_REJECT:
+      case PD_CTRL_REJECT:
         break;
 
-      case TUSB_PD_CTRL_PS_RDY:
+      case PD_CTRL_PS_READY:
         break;
 
       default: break;
@@ -130,7 +130,7 @@ bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) {
   } else {
     // data message
     switch (header->msg_type) {
-      case TUSB_PD_DATA_SOURCE_CAP: {
+      case PD_DATA_SOURCE_CAP: {
         // Examine source capability and select a suitable PDO (starting from 1 with safe5v)
         uint8_t obj_pos = 1;
 
@@ -172,11 +172,11 @@ bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) {
             .object_position = obj_pos,
         };
 
-        tusb_pd_header_t const req_header = {
-            .msg_type = TUSB_PD_DATA_REQUEST,
-            .data_role = TUSB_PD_DATA_ROLE_UFP,
-            .specs_rev = TUSB_PD_REV20,
-            .power_role = TUSB_PD_POWER_ROLE_SINK,
+        pd_header_t const req_header = {
+            .msg_type = PD_DATA_REQUEST,
+            .data_role = PD_DATA_ROLE_UFP,
+            .specs_rev = PD_REV_20,
+            .power_role = PD_POWER_ROLE_SINK,
             .msg_id = 0,
             .n_data_obj = 1,
             .extended = 0,
@@ -200,7 +200,7 @@ void tcd_event_handler(tcd_event_t const * event, bool in_isr) {
     case TCD_EVENT_CC_CHANGED:
       if (event->cc_changed.cc_state[0] || event->cc_changed.cc_state[1]) {
         // Attach
-        tcd_rx_start(event->rhport, _rx_buf, sizeof(_rx_buf));
+        tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf));
       }else {
         // Detach
       }
@@ -213,7 +213,7 @@ void tcd_event_handler(tcd_event_t const * event, bool in_isr) {
       }
 
       // start new rx
-      tcd_rx_start(event->rhport, _rx_buf, sizeof(_rx_buf));
+      tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf));
       break;
 
     default: break;
diff --git a/src/typec/utcd.h b/src/typec/utcd.h
index bb1523253..740e477ac 100644
--- a/src/typec/utcd.h
+++ b/src/typec/utcd.h
@@ -28,6 +28,7 @@
 #define _TUSB_UTCD_H_
 
 #include "common/tusb_common.h"
+#include "pd_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -41,105 +42,12 @@ extern "C" {
 #define CFG_TUC_TASK_QUEUE_SZ   8
 #endif
 
-//--------------------------------------------------------------------+
-// Source Capability
-//--------------------------------------------------------------------+
-
-// All table references are from USBPD Specification rev3.1 version 1.8
-enum {
-  PD_PDO_TYPE_FIXED = 0, // Vmin = Vmax
-  PD_PDO_TYPE_BATTERY,
-  PD_PDO_TYPE_VARIABLE, // non-battery
-  PD_PDO_TYPE_APDO, // Augmented Power Data Object
-};
-
-// Fixed Power Data Object (PDO) table 6-9
-typedef struct TU_ATTR_PACKED {
-  uint32_t current_max_10ma          : 10; // [9..0] Max current in 10mA unit
-  uint32_t voltage_50mv              : 10; // [19..10] Voltage in 50mV unit
-  uint32_t current_peak              :  2; // [21..20] Peak current
-  uint32_t reserved                  :  1; // [22] Reserved
-  uint32_t epr_mode_capable          :  1; // [23] epr_mode_capable
-  uint32_t unchunked_ext_msg_support :  1; // [24] UnChunked Extended Message Supported
-  uint32_t dual_role_data            :  1; // [25] Dual Role Data
-  uint32_t usb_comm_capable          :  1; // [26] USB Communications Capable
-  uint32_t unconstrained_power       :  1; // [27] Unconstrained Power
-  uint32_t usb_suspend_supported     :  1; // [28] USB Suspend Supported
-  uint32_t dual_role_power           :  1; // [29] Dual Role Power
-  uint32_t type                      :  2; // [30] Fixed Supply type = PD_PDO_TYPE_FIXED
-} pd_pdo_fixed_t;
-TU_VERIFY_STATIC(sizeof(pd_pdo_fixed_t) == 4, "Invalid size");
-
-// Battery Power Data Object (PDO) table 6-12
-typedef struct TU_ATTR_PACKED {
-  uint32_t power_max_250mw   : 10; // [9..0] Max allowable power in 250mW unit
-  uint32_t voltage_min_50mv  : 10; // [19..10] Minimum voltage in 50mV unit
-  uint32_t voltage_max_50mv  : 10; // [29..20] Maximum voltage in 50mV unit
-  uint32_t type              :  2; // [31..30] Battery type = PD_PDO_TYPE_BATTERY
-} pd_pdo_battery_t;
-TU_VERIFY_STATIC(sizeof(pd_pdo_battery_t) == 4, "Invalid size");
-
-// Variable Power Data Object (PDO) table 6-11
-typedef struct TU_ATTR_PACKED {
-  uint32_t current_max_10ma  : 10; // [9..0] Max current in 10mA unit
-  uint32_t voltage_min_50mv  : 10; // [19..10] Minimum voltage in 50mV unit
-  uint32_t voltage_max_50mv  : 10; // [29..20] Maximum voltage in 50mV unit
-  uint32_t type              :  2; // [31..30] Variable Supply type = PD_PDO_TYPE_VARIABLE
-} pd_pdo_variable_t;
-TU_VERIFY_STATIC(sizeof(pd_pdo_variable_t) == 4, "Invalid size");
-
-// Augmented Power Data Object (PDO) table 6-13
-typedef struct TU_ATTR_PACKED {
-  uint32_t current_max_50ma  :  7; // [6..0] Max current in 50mA unit
-  uint32_t reserved1         :  1; // [7] Reserved
-  uint32_t voltage_min_100mv :  8; // [15..8] Minimum Voltage in 100mV unit
-  uint32_t reserved2         :  1; // [16] Reserved
-  uint32_t voltage_max_100mv :  8; // [24..17] Maximum Voltage in 100mV unit
-  uint32_t reserved3         :  2; // [26..25] Reserved
-  uint32_t pps_power_limited :  1; // [27] PPS Power Limited
-  uint32_t spr_programmable  :  2; // [29..28] SPR Programmable Power Supply
-  uint32_t type              :  2; // [31..30] Augmented Power Data Object = PD_PDO_TYPE_APDO
-} pd_pdo_apdo_t;
-TU_VERIFY_STATIC(sizeof(pd_pdo_apdo_t) == 4, "Invalid size");
-
-//--------------------------------------------------------------------+
-// Request
-//--------------------------------------------------------------------+
-
-typedef struct TU_ATTR_PACKED {
-  uint32_t current_extremum_10ma     : 10; // [9..0] Max (give back = 0) or Min (give back = 1) current in 10mA unit
-  uint32_t current_operate_10ma      : 10; // [19..10] Operating current in 10mA unit
-  uint32_t reserved                  :  2; // [21..20] Reserved
-  uint32_t epr_mode_capable          :  1; // [22] EPR mode capable
-  uint32_t unchunked_ext_msg_support :  1; // [23] UnChunked Extended Message Supported
-  uint32_t no_usb_suspend            :  1; // [24] No USB Suspend
-  uint32_t usb_comm_capable          :  1; // [25] USB Communications Capable
-  uint32_t capability_mismatch       :  1; // [26] Capability Mismatch
-  uint32_t give_back_flag            :  1; // [27] GiveBack Flag: 0 = Max, 1 = Min
-  uint32_t object_position           :  4; // [31..28] Object Position
-} pd_rdo_fixed_variable_t;
-TU_VERIFY_STATIC(sizeof(pd_rdo_fixed_variable_t) == 4, "Invalid size");
-
-typedef struct TU_ATTR_PACKED {
-  uint32_t power_extremum_250mw      : 10; // [9..0] Max (give back = 0) or Min (give back = 1) operating power in 250mW unit
-  uint32_t power_operate_250mw       : 10; // [19..10] Operating power in 250mW unit
-  uint32_t reserved                  :  2; // [21..20] Reserved
-  uint32_t epr_mode_capable          :  1; // [22] EPR mode capable
-  uint32_t unchunked_ext_msg_support :  1; // [23] UnChunked Extended Message Supported
-  uint32_t no_usb_suspend            :  1; // [24] No USB Suspend
-  uint32_t usb_comm_capable          :  1; // [25] USB Communications Capable
-  uint32_t capability_mismatch       :  1; // [26] Capability Mismatch
-  uint32_t give_back_flag            :  1; // [27] GiveBack Flag: 0 = Max, 1 = Min
-  uint32_t object_position           :  4; // [31..28] Object Position
-} pd_rdo_battery_t;
-TU_VERIFY_STATIC(sizeof(pd_rdo_battery_t) == 4, "Invalid size");
-
 //--------------------------------------------------------------------+
 // Application API
 //--------------------------------------------------------------------+
 
 // Init typec stack on a port
-bool tuc_init(uint8_t rhport, tusb_typec_port_type_t port_type);
+bool tuc_init(uint8_t rhport, uint32_t port_type);
 
 // Check if typec port is initialized
 bool tuc_inited(uint8_t rhport);
@@ -155,4 +63,9 @@ extern void tcd_int_handler(uint8_t rhport);
 //
 //--------------------------------------------------------------------+
 
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif

From 6941a5af81b53cd0df52632d403cccdb7d22cf30 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jun 2023 16:42:27 +0700
Subject: [PATCH 1799/2085] wrap up initial PD support for G4

---
 examples/typec/power_delivery/src/main.c |  90 +++++++++++-
 src/typec/tcd.h                          |  15 +-
 src/typec/utcd.c                         | 180 ++++++++++-------------
 src/typec/utcd.h                         |  20 +++
 4 files changed, 196 insertions(+), 109 deletions(-)

diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
index 648345a55..42665ed1b 100644
--- a/examples/typec/power_delivery/src/main.c
+++ b/examples/typec/power_delivery/src/main.c
@@ -62,7 +62,8 @@ int main(void)
   while (1) {
     led_blinking_task();
 
-//    tuc_task();
+    // tinyusb typec task
+    tuc_task();
   }
 }
 
@@ -73,6 +74,93 @@ void app_main(void)
 }
 #endif
 
+//--------------------------------------------------------------------+
+// TypeC PD callbacks
+//--------------------------------------------------------------------+
+
+bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end) {
+  switch (header->msg_type) {
+    case PD_DATA_SOURCE_CAP: {
+      printf("PD Source Capabilities\r\n");
+      // Examine source capability and select a suitable PDO (starting from 1 with safe5v)
+      uint8_t obj_pos = 1;
+
+      for(size_t i=0; i<header->n_data_obj; i++) {
+        TU_VERIFY(dobj < p_end);
+        uint32_t const pdo = tu_le32toh(tu_unaligned_read32(dobj));
+
+        switch ((pdo >> 30) & 0x03ul) {
+          case PD_PDO_TYPE_FIXED: {
+            pd_pdo_fixed_t const* fixed = (pd_pdo_fixed_t const*) &pdo;
+            printf("[Fixed] %u mV %u mA\r\n", fixed->voltage_50mv*50, fixed->current_max_10ma*10);
+            break;
+          }
+
+          case PD_PDO_TYPE_BATTERY:
+            break;
+
+          case PD_PDO_TYPE_VARIABLE:
+            break;
+
+          case PD_PDO_TYPE_APDO:
+            break;
+        }
+
+        dobj += 4;
+      }
+
+      //------------- Response with selected PDO -------------//
+      // Be careful and make sure your board can withstand the selected PDO voltage other than safe5v e.g 12v or 20v
+
+      // Send request with selected PDO position as response to Source Cap
+      pd_rdo_fixed_variable_t rdo = {
+          .current_extremum_10ma = 50, // max 500mA
+          .current_operate_10ma = 30, // 300mA
+          .reserved = 0,
+          .epr_mode_capable = 0,
+          .unchunked_ext_msg_support = 0,
+          .no_usb_suspend = 0,
+          .usb_comm_capable = 1,
+          .capability_mismatch = 0,
+          .give_back_flag = 0, // exteremum is max
+          .object_position = obj_pos,
+      };
+
+      tuc_msg_request(rhport, &rdo);
+
+      break;
+    }
+
+    default: break;
+  }
+
+  return true;
+}
+
+bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header) {
+  switch (header->msg_type) {
+    case PD_CTRL_ACCEPT:
+      printf("PD Request Accepted\r\n");
+      // preparing for power transition
+      break;
+
+    case PD_CTRL_REJECT:
+      printf("PD Request Rejected\r\n");
+      // try to negotiate further power
+      break;
+
+    case PD_CTRL_PS_READY:
+      printf("PD Power Ready\r\n");
+      // Source is ready to supply power
+      break;
+
+    default:
+      break;
+  }
+
+  return true;
+}
+
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
diff --git a/src/typec/tcd.h b/src/typec/tcd.h
index ee73943bd..86499c951 100644
--- a/src/typec/tcd.h
+++ b/src/typec/tcd.h
@@ -48,8 +48,7 @@ enum {
   TCD_EVENT_TX_COMPLETE,
 };
 
-
-typedef struct {
+typedef struct TU_ATTR_PACKED {
   uint8_t rhport;
   uint8_t event_id;
 
@@ -58,10 +57,10 @@ typedef struct {
       uint8_t cc_state[2];
     } cc_changed;
 
-    struct {
-      uint16_t xferred_bytes;
-      uint8_t result;
-    } rx_complete;
+    struct TU_ATTR_PACKED {
+      uint16_t result : 2;
+      uint16_t xferred_bytes : 14;
+    } xfer_complete;
   };
 
 } tcd_event_t;;
@@ -114,7 +113,7 @@ void tcd_event_rx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t resul
   tcd_event_t event = {
     .rhport   = rhport,
     .event_id = TCD_EVENT_RX_COMPLETE,
-    .rx_complete = {
+    .xfer_complete = {
         .xferred_bytes = xferred_bytes,
         .result        = result
     }
@@ -128,7 +127,7 @@ void tcd_event_tx_complete(uint8_t rhport, uint16_t xferred_bytes, uint8_t resul
   tcd_event_t event = {
       .rhport   = rhport,
       .event_id = TCD_EVENT_TX_COMPLETE,
-      .rx_complete = {
+      .xfer_complete = {
           .xferred_bytes = xferred_bytes,
           .result        = result
       }
diff --git a/src/typec/utcd.c b/src/typec/utcd.c
index 439fe89b9..831df1fe8 100644
--- a/src/typec/utcd.c
+++ b/src/typec/utcd.c
@@ -52,8 +52,12 @@ static bool _utcd_inited = false;
 static bool _port_inited[TUP_TYPEC_RHPORTS_NUM];
 
 // Max possible PD size is 262 bytes
-static uint8_t _rx_buf[262] TU_ATTR_ALIGNED(4);
-static uint8_t _tx_buf[100] TU_ATTR_ALIGNED(4);
+static uint8_t _rx_buf[64] TU_ATTR_ALIGNED(4);
+static uint8_t _tx_buf[64] TU_ATTR_ALIGNED(4);
+
+bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data);
+bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end);
+bool parse_msg_control(uint8_t rhport, pd_header_t const* header);
 
 //--------------------------------------------------------------------+
 //
@@ -79,6 +83,7 @@ bool tuc_init(uint8_t rhport, uint32_t port_type) {
   }
 
   TU_LOG_UTCD("UTCD init on port %u\r\n", rhport);
+  TU_LOG_INT(UTCD_DEBUG, sizeof(tcd_event_t));
 
   TU_ASSERT(tcd_init(rhport, port_type));
   tcd_int_enable(rhport);
@@ -87,6 +92,65 @@ bool tuc_init(uint8_t rhport, uint32_t port_type) {
   return true;
 }
 
+void tuc_task_ext(uint32_t timeout_ms, bool in_isr) {
+  (void) in_isr; // not implemented yet
+
+  // Skip if stack is not initialized
+  if (!_utcd_inited) return;
+
+  // Loop until there is no more events in the queue
+  while (1) {
+    tcd_event_t event;
+    if (!osal_queue_receive(_utcd_q, &event, timeout_ms)) return;
+
+    switch (event.event_id) {
+      case TCD_EVENT_CC_CHANGED:
+        break;
+
+      case TCD_EVENT_RX_COMPLETE:
+        // TODO process message here in ISR, move to thread later
+        if (event.xfer_complete.result == XFER_RESULT_SUCCESS) {
+          pd_header_t const* header = (pd_header_t const*) _rx_buf;
+
+          if (header->n_data_obj == 0) {
+            parse_msg_control(event.rhport, header);
+
+          }else {
+            uint8_t const* p_end = _rx_buf + event.xfer_complete.xferred_bytes;
+            uint8_t const * dobj = _rx_buf + sizeof(pd_header_t);
+
+            parse_msg_data(event.rhport, header, dobj, p_end);
+          }
+        }
+
+        // prepare for next message
+        tcd_msg_receive(event.rhport, _rx_buf, sizeof(_rx_buf));
+        break;
+
+      case TCD_EVENT_TX_COMPLETE:
+        break;
+
+      default: break;
+    }
+  }
+}
+
+bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end) {
+  if (tuc_pd_data_received_cb) {
+    tuc_pd_data_received_cb(rhport, header, dobj, p_end);
+  }
+
+  return true;
+}
+
+bool parse_msg_control(uint8_t rhport, pd_header_t const* header) {
+  if (tuc_pd_control_received_cb) {
+    tuc_pd_control_received_cb(rhport, header);
+  }
+
+  return true;
+}
+
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
@@ -104,94 +168,18 @@ bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data)
   return tcd_msg_send(rhport, _tx_buf, sizeof(pd_header_t) + n_data_obj * 4);
 }
 
-bool parse_message(uint8_t rhport, uint8_t const* buf, uint16_t len) {
-  (void) rhport;
-  uint8_t const* p_end = buf + len;
-  pd_header_t const* header = (pd_header_t const*) buf;
-  uint8_t const * ptr = buf + sizeof(pd_header_t);
+bool tuc_msg_request(uint8_t rhport, void const* rdo) {
+  pd_header_t const header = {
+      .msg_type = PD_DATA_REQUEST,
+      .data_role = PD_DATA_ROLE_UFP,
+      .specs_rev = PD_REV_30,
+      .power_role = PD_POWER_ROLE_SINK,
+      .msg_id = 0,
+      .n_data_obj = 1,
+      .extended = 0,
+  };
 
-  if (header->n_data_obj == 0) {
-    // control message
-    switch (header->msg_type) {
-      case PD_CTRL_GOOD_CRC:
-        break;
-
-      case PD_CTRL_ACCEPT:
-        break;
-
-      case PD_CTRL_REJECT:
-        break;
-
-      case PD_CTRL_PS_READY:
-        break;
-
-      default: break;
-    }
-  } else {
-    // data message
-    switch (header->msg_type) {
-      case PD_DATA_SOURCE_CAP: {
-        // Examine source capability and select a suitable PDO (starting from 1 with safe5v)
-        uint8_t obj_pos = 1;
-
-        for(size_t i=0; i<header->n_data_obj; i++) {
-          TU_VERIFY(ptr < p_end);
-          uint32_t const pdo = tu_le32toh(tu_unaligned_read32(ptr));
-
-          switch ((pdo >> 30) & 0x03ul) {
-            case PD_PDO_TYPE_FIXED: {
-              pd_pdo_fixed_t const* fixed = (pd_pdo_fixed_t const*) &pdo;
-              TU_LOG3("[Fixed] %u mV %u mA\r\n", fixed->voltage_50mv*50, fixed->current_max_10ma*10);
-              break;
-            }
-
-            case PD_PDO_TYPE_BATTERY:
-              break;
-
-            case PD_PDO_TYPE_VARIABLE:
-              break;
-
-            case PD_PDO_TYPE_APDO:
-              break;
-          }
-
-          ptr += 4;
-        }
-
-        // Send request with selected PDO position as response to Source Cap
-        pd_rdo_fixed_variable_t rdo = {
-            .current_extremum_10ma = 50, // max 500mA
-            .current_operate_10ma = 30, // 300mA
-            .reserved = 0,
-            .epr_mode_capable = 0,
-            .unchunked_ext_msg_support = 0,
-            .no_usb_suspend = 0,
-            .usb_comm_capable = 1,
-            .capability_mismatch = 0,
-            .give_back_flag = 0, // exteremum is max
-            .object_position = obj_pos,
-        };
-
-        pd_header_t const req_header = {
-            .msg_type = PD_DATA_REQUEST,
-            .data_role = PD_DATA_ROLE_UFP,
-            .specs_rev = PD_REV_20,
-            .power_role = PD_POWER_ROLE_SINK,
-            .msg_id = 0,
-            .n_data_obj = 1,
-            .extended = 0,
-        };
-
-        utcd_msg_send(rhport, &req_header, &rdo);
-
-        break;
-      }
-
-      default: break;
-    }
-  }
-
-  return true;
+  return utcd_msg_send(rhport, &header, rdo);
 }
 
 void tcd_event_handler(tcd_event_t const * event, bool in_isr) {
@@ -199,25 +187,17 @@ void tcd_event_handler(tcd_event_t const * event, bool in_isr) {
   switch(event->event_id) {
     case TCD_EVENT_CC_CHANGED:
       if (event->cc_changed.cc_state[0] || event->cc_changed.cc_state[1]) {
-        // Attach
+        // Attach, start receiving
         tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf));
       }else {
         // Detach
       }
       break;
 
-    case TCD_EVENT_RX_COMPLETE:
-      // TODO process message here in ISR, move to thread later
-      if (event->rx_complete.result == XFER_RESULT_SUCCESS) {
-        parse_message(event->rhport, _rx_buf, event->rx_complete.xferred_bytes);
-      }
-
-      // start new rx
-      tcd_msg_receive(event->rhport, _rx_buf, sizeof(_rx_buf));
-      break;
-
     default: break;
   }
+
+  osal_queue_send(_utcd_q, event, in_isr);
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/typec/utcd.h b/src/typec/utcd.h
index 740e477ac..9fbff9bc6 100644
--- a/src/typec/utcd.h
+++ b/src/typec/utcd.h
@@ -52,6 +52,17 @@ bool tuc_init(uint8_t rhport, uint32_t port_type);
 // Check if typec port is initialized
 bool tuc_inited(uint8_t rhport);
 
+// Task function should be called in main/rtos loop, extended version of tud_task()
+// - timeout_ms: millisecond to wait, zero = no wait, 0xFFFFFFFF = wait forever
+// - in_isr: if function is called in ISR
+void tuc_task_ext(uint32_t timeout_ms, bool in_isr);
+
+// Task function should be called in main/rtos loop
+TU_ATTR_ALWAYS_INLINE static inline
+void tuc_task (void) {
+  tuc_task_ext(UINT32_MAX, false);
+}
+
 #ifndef _TUSB_TCD_H_
 extern void tcd_int_handler(uint8_t rhport);
 #endif
@@ -59,10 +70,19 @@ extern void tcd_int_handler(uint8_t rhport);
 // Interrupt handler, name alias to TCD
 #define tuc_int_handler tcd_int_handler
 
+//--------------------------------------------------------------------+
+// Callbacks
+//--------------------------------------------------------------------+
+
+TU_ATTR_WEAK bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end);
+TU_ATTR_WEAK bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header);
+
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
+bool tuc_msg_request(uint8_t rhport, void const* rdo);
+
 
 #ifdef __cplusplus
 }

From 7a1179a4e1dbf238e8cce203aa92c38c0cb055b7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jun 2023 17:01:54 +0700
Subject: [PATCH 1800/2085] tested with 9V request

---
 examples/typec/power_delivery/src/main.c | 27 +++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
index 42665ed1b..342a2235f 100644
--- a/examples/typec/power_delivery/src/main.c
+++ b/examples/typec/power_delivery/src/main.c
@@ -34,6 +34,13 @@
 // MACRO CONSTANT TYPEDEF PROTOTYPES
 //--------------------------------------------------------------------+
 
+// Voltage and current for selecting PDO
+// DANGEROUS: Please make sure your board can withstand the voltage and current
+// defined here. Otherwise, you may damage your board, smoke can come out
+#define VOLTAGE_MAX_MV       5000 // maximum voltage in mV
+#define CURRENT_MAX_MA       500  // maximum current in mA
+#define CURRENT_OPERATING_MA 100  // operating current in mA
+
 /* Blink pattern
  * - 250 ms  : button is not pressed
  * - 1000 ms : button is pressed (and hold)
@@ -83,7 +90,7 @@ bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t
     case PD_DATA_SOURCE_CAP: {
       printf("PD Source Capabilities\r\n");
       // Examine source capability and select a suitable PDO (starting from 1 with safe5v)
-      uint8_t obj_pos = 1;
+      uint8_t selected_pos = 1;
 
       for(size_t i=0; i<header->n_data_obj; i++) {
         TU_VERIFY(dobj < p_end);
@@ -92,7 +99,15 @@ bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t
         switch ((pdo >> 30) & 0x03ul) {
           case PD_PDO_TYPE_FIXED: {
             pd_pdo_fixed_t const* fixed = (pd_pdo_fixed_t const*) &pdo;
-            printf("[Fixed] %u mV %u mA\r\n", fixed->voltage_50mv*50, fixed->current_max_10ma*10);
+            uint32_t const voltage_mv = fixed->voltage_50mv*50;
+            uint32_t const current_ma = fixed->current_max_10ma*10;
+            printf("[Fixed] %lu mV %lu mA\r\n", voltage_mv, current_ma);
+
+            if (voltage_mv <= VOLTAGE_MAX_MV && current_ma >= CURRENT_MAX_MA) {
+              // Found a suitable PDO
+              selected_pos = i+1;
+            }
+
             break;
           }
 
@@ -110,7 +125,10 @@ bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t
       }
 
       //------------- Response with selected PDO -------------//
-      // Be careful and make sure your board can withstand the selected PDO voltage other than safe5v e.g 12v or 20v
+      // Be careful and make sure your board can withstand the selected PDO
+      // voltage other than safe5v e.g 12v or 20v
+
+      printf("Selected PDO %u\r\n", selected_pos);
 
       // Send request with selected PDO position as response to Source Cap
       pd_rdo_fixed_variable_t rdo = {
@@ -123,9 +141,8 @@ bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t
           .usb_comm_capable = 1,
           .capability_mismatch = 0,
           .give_back_flag = 0, // exteremum is max
-          .object_position = obj_pos,
+          .object_position = selected_pos,
       };
-
       tuc_msg_request(rhport, &rdo);
 
       break;

From d2d486dced7f92e8cab65f87be79b7e60d211ad2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jun 2023 17:06:04 +0700
Subject: [PATCH 1801/2085] update docs

---
 README.rst | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/README.rst b/README.rst
index 425cfa0e3..2c9119fef 100644
--- a/README.rst
+++ b/README.rst
@@ -20,8 +20,8 @@ Please take a look at the online `documentation <https://docs.tinyusb.org/>`__.
 	├── docs            # Documentation
 	├── examples        # Sample with Makefile build support
 	├── hw
-	│   ├── bsp         # Supported boards source files
-	│   └── mcu         # Low level mcu core & peripheral drivers
+	│   ├── bsp         # Supported boards source files
+	│   └── mcu         # Low level mcu core & peripheral drivers
 	├── lib             # Sources from 3rd party such as freeRTOS, fatfs ...
 	├── src             # All sources files for TinyUSB stack itself.
 	├── test            # Unit tests for the stack
@@ -89,6 +89,13 @@ Host Stack
 - Mass Storage Class (MSC)
 - Hub with multiple-level support
 
+TypeC PD Stack
+==============
+
+- Power Delivery 3.0 (PD3.0) with USB Type-C support (WIP)
+- Super early stage, only for testing purpose
+- Only support STM32 G4
+
 OS Abstraction layer
 ====================
 

From 41801c2a6bd146033f5ff00e54983de46ab414b9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 12 Jun 2023 17:12:25 +0700
Subject: [PATCH 1802/2085] add typec example to cmake

---
 examples/CMakeLists.txt       | 1 +
 examples/typec/CMakeLists.txt | 9 +++++++++
 2 files changed, 10 insertions(+)
 create mode 100644 examples/typec/CMakeLists.txt

diff --git a/examples/CMakeLists.txt b/examples/CMakeLists.txt
index 91c9fb098..c603d0c22 100644
--- a/examples/CMakeLists.txt
+++ b/examples/CMakeLists.txt
@@ -8,3 +8,4 @@ project(tinyusb_examples C CXX ASM)
 add_subdirectory(device)
 add_subdirectory(dual)
 add_subdirectory(host)
+add_subdirectory(typec)
diff --git a/examples/typec/CMakeLists.txt b/examples/typec/CMakeLists.txt
new file mode 100644
index 000000000..c7641494e
--- /dev/null
+++ b/examples/typec/CMakeLists.txt
@@ -0,0 +1,9 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../hw/bsp/family_support.cmake)
+
+project(tinyusb_host_examples C CXX ASM)
+family_initialize_project(tinyusb_host_examples ${CMAKE_CURRENT_LIST_DIR})
+
+# family_add_subdirectory will filter what to actually add based on selected FAMILY
+family_add_subdirectory(power_delivery)

From 9593ab7acc528814faf86c652b2a22209938128d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 13 Jun 2023 16:40:29 +0700
Subject: [PATCH 1803/2085] fix usbh issue when device genreate multiple
 attach/detach/attach when plugging in

---
 src/host/usbh.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 98e959a12..f3e9d3858 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -411,7 +411,14 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
         if ( _dev0.enumerating )
         {
           TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
+
+          bool is_empty = osal_queue_empty(_usbh_q);
           osal_queue_send(_usbh_q, &event, in_isr);
+
+          if (is_empty) {
+            // Exit if this is the only event in the queue, otherwise we may loop forever
+            return;
+          }
         }else
         {
           TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
@@ -1461,7 +1468,10 @@ static bool enum_new_device(hcd_event_t* event)
     hcd_port_reset_end( _dev0.rhport);
 
     // device unplugged while delaying
-    if ( !hcd_port_connect_status(_dev0.rhport) ) return true;
+    if ( !hcd_port_connect_status(_dev0.rhport) ) {
+      enum_full_complete();
+      return true;
+    }
 
     _dev0.speed = hcd_port_speed_get(_dev0.rhport );
     TU_LOG_USBH("%s Speed\r\n", tu_str_speed[_dev0.speed]);

From a88d7c7c7472b07f641772bff45e7804584f9ccd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 13 Jun 2023 17:47:28 +0700
Subject: [PATCH 1804/2085] ide setting

---
 .idea/cmake.xml                             | 14 ++++++++------
 .idea/runConfigurations/rp2040.xml          |  2 +-
 .idea/runConfigurations/rt1010_jlink.xml    |  2 +-
 .idea/runConfigurations/rt1060_jlink.xml    |  2 +-
 .idea/runConfigurations/stm32g474_jlink.xml |  2 +-
 5 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 871968dfb..3c016ccff 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -3,11 +3,9 @@
   <component name="CMakeSharedSettings">
     <configurations>
       <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=mcx -DBOARD=mcxn947brk" />
-      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1060_evk" />
+      <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095" />
-      <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" BUILD_OPTIONS="-v" />
-      <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc55 -DBOARD=lpcxpresso55s69" />
-      <configuration PROFILE_NAME="esp32s3" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_s3_devkitm -DIDF_TARGET=esp32s3">
+      <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
@@ -17,7 +15,7 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
+      <configuration PROFILE_NAME="esp32s3" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_s3_devkitm -DIDF_TARGET=esp32s3">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
@@ -29,12 +27,16 @@
       </configuration>
       <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=rp2040 -DBOARD=raspberry_pi_pico" />
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1010_evk" />
+      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1060_evk" />
       <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1064_evk" />
       <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=mcb1800" />
       <configuration PROFILE_NAME="lpcxpresso18s37" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=lpcxpresso18s37" />
+      <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc55 -DBOARD=lpcxpresso55s69" />
       <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g0 -DBOARD=stm32g0b1nucleo" />
+      <configuration PROFILE_NAME="stm32g0b1nucleo iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g0 -DBOARD=stm32g0b1nucleo -DTOOLCHAIN=iar" />
       <configuration PROFILE_NAME="stm32g474nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=stm32g474nucleo" />
-      <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=b_g474e_dpow1" />
+      <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=b_g474e_dpow1 -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="b_g474e_dpow1 iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=b_g474e_dpow1 -DTOOLCHAIN=iar" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rp2040.xml b/.idea/runConfigurations/rp2040.xml
index 0d1484b25..9b6111900 100644
--- a/.idea/runConfigurations/rp2040.xml
+++ b/.idea/runConfigurations/rp2040.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rp2040" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_device_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="b_g474e_dpow1" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_device_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rp2040" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_device_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_device_examples" RUN_TARGET_NAME="cdc_msc">
     <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
       <debugger kind="GDB" isBundled="true" />
     </openocd>
diff --git a/.idea/runConfigurations/rt1010_jlink.xml b/.idea/runConfigurations/rt1010_jlink.xml
index 70cfeea53..e660a46ae 100644
--- a/.idea/runConfigurations/rt1010_jlink.xml
+++ b/.idea/runConfigurations/rt1010_jlink.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1010 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcxn947" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rt1010 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="b_g474e_dpow1" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/rt1060_jlink.xml b/.idea/runConfigurations/rt1060_jlink.xml
index eabadaf59..b9a47a2ce 100644
--- a/.idea/runConfigurations/rt1060_jlink.xml
+++ b/.idea/runConfigurations/rt1060_jlink.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1060 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="host_hid_to_device_cdc" TARGET_NAME="host_hid_to_device_cdc" CONFIG_NAME="rt1060 evk" version="1" RUN_TARGET_PROJECT_NAME="host_hid_to_device_cdc" RUN_TARGET_NAME="host_hid_to_device_cdc">
+  <configuration default="false" name="rt1060 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="b_g474e_dpow1" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/stm32g474_jlink.xml b/.idea/runConfigurations/stm32g474_jlink.xml
index 45a755da4..c33829833 100644
--- a/.idea/runConfigurations/stm32g474_jlink.xml
+++ b/.idea/runConfigurations/stm32g474_jlink.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stm32g474 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 100000 -port 25321 -swoport 25322 -TelnetPort 25323 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="b_g474e_dpow1" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="stm32g474 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="b_g474e_dpow1" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>

From 05969d2a58d426e5948df5dc0479e2ad8dfd02a9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jun 2023 11:07:58 +0700
Subject: [PATCH 1805/2085] rename typec driver

---
 src/CMakeLists.txt           |  2 +-
 src/tusb.h                   |  2 +-
 src/typec/{utcd.c => usbc.c} | 44 ++++++++++++++++++------------------
 src/typec/{utcd.h => usbc.h} |  0
 4 files changed, 24 insertions(+), 24 deletions(-)
 rename src/typec/{utcd.c => usbc.c} (85%)
 rename src/typec/{utcd.h => usbc.h} (100%)

diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index ce4486ecd..b99c7be6e 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -33,7 +33,7 @@ function(add_tinyusb TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/msc/msc_host.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/class/vendor/vendor_host.c
     # typec
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/typec/utcd.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/typec/usbc.c
     )
   target_include_directories(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
diff --git a/src/tusb.h b/src/tusb.h
index 0b87b1969..37a521fa8 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -42,7 +42,7 @@
 
 //------------- TypeC -------------//
 #if CFG_TUC_ENABLED
-  #include "typec/utcd.h"
+  #include "typec/usbc.h"
 #endif
 
 //------------- HOST -------------//
diff --git a/src/typec/utcd.c b/src/typec/usbc.c
similarity index 85%
rename from src/typec/utcd.c
rename to src/typec/usbc.c
index 831df1fe8..fdf2a0cd6 100644
--- a/src/typec/utcd.c
+++ b/src/typec/usbc.c
@@ -29,24 +29,24 @@
 #if CFG_TUC_ENABLED
 
 #include "tcd.h"
-#include "utcd.h"
+#include "usbc.h"
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
 // Debug level of USBD
-#define UTCD_DEBUG   2
-#define TU_LOG_UTCD(...)   TU_LOG(UTCD_DEBUG, __VA_ARGS__)
+#define USBC_DEBUG   2
+#define TU_LOG_USBC(...)   TU_LOG(USBC_DEBUG, __VA_ARGS__)
 
 // Event queue
-// utcd_int_set() is used as mutex in OS NONE config
-void utcd_int_set(bool enabled);
-OSAL_QUEUE_DEF(utcd_int_set, _utcd_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t);
-tu_static osal_queue_t _utcd_q;
+// usbc_int_set() is used as mutex in OS NONE config
+void usbc_int_set(bool enabled);
+OSAL_QUEUE_DEF(usbc_int_set, _usbc_qdef, CFG_TUC_TASK_QUEUE_SZ, tcd_event_t);
+tu_static osal_queue_t _usbc_q;
 
 // if stack is initialized
-static bool _utcd_inited = false;
+static bool _usbc_inited = false;
 
 // if port is initialized
 static bool _port_inited[TUP_TYPEC_RHPORTS_NUM];
@@ -55,7 +55,7 @@ static bool _port_inited[TUP_TYPEC_RHPORTS_NUM];
 static uint8_t _rx_buf[64] TU_ATTR_ALIGNED(4);
 static uint8_t _tx_buf[64] TU_ATTR_ALIGNED(4);
 
-bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data);
+bool usbc_msg_send(uint8_t rhport, pd_header_t const* header, void const* data);
 bool parse_msg_data(uint8_t rhport, pd_header_t const* header, uint8_t const* dobj, uint8_t const* p_end);
 bool parse_msg_control(uint8_t rhport, pd_header_t const* header);
 
@@ -63,18 +63,18 @@ bool parse_msg_control(uint8_t rhport, pd_header_t const* header);
 //
 //--------------------------------------------------------------------+
 bool tuc_inited(uint8_t rhport) {
-  return _utcd_inited && _port_inited[rhport];
+  return _usbc_inited && _port_inited[rhport];
 }
 
 bool tuc_init(uint8_t rhport, uint32_t port_type) {
   // Initialize stack
-  if (!_utcd_inited) {
+  if (!_usbc_inited) {
     tu_memclr(_port_inited, sizeof(_port_inited));
 
-    _utcd_q = osal_queue_create(&_utcd_qdef);
-    TU_ASSERT(_utcd_q != NULL);
+    _usbc_q = osal_queue_create(&_usbc_qdef);
+    TU_ASSERT(_usbc_q != NULL);
 
-    _utcd_inited = true;
+    _usbc_inited = true;
   }
 
   // skip if port already initialized
@@ -82,8 +82,8 @@ bool tuc_init(uint8_t rhport, uint32_t port_type) {
     return true;
   }
 
-  TU_LOG_UTCD("UTCD init on port %u\r\n", rhport);
-  TU_LOG_INT(UTCD_DEBUG, sizeof(tcd_event_t));
+  TU_LOG_USBC("USBC init on port %u\r\n", rhport);
+  TU_LOG_INT(USBC_DEBUG, sizeof(tcd_event_t));
 
   TU_ASSERT(tcd_init(rhport, port_type));
   tcd_int_enable(rhport);
@@ -96,12 +96,12 @@ void tuc_task_ext(uint32_t timeout_ms, bool in_isr) {
   (void) in_isr; // not implemented yet
 
   // Skip if stack is not initialized
-  if (!_utcd_inited) return;
+  if (!_usbc_inited) return;
 
   // Loop until there is no more events in the queue
   while (1) {
     tcd_event_t event;
-    if (!osal_queue_receive(_utcd_q, &event, timeout_ms)) return;
+    if (!osal_queue_receive(_usbc_q, &event, timeout_ms)) return;
 
     switch (event.event_id) {
       case TCD_EVENT_CC_CHANGED:
@@ -155,7 +155,7 @@ bool parse_msg_control(uint8_t rhport, pd_header_t const* header) {
 //
 //--------------------------------------------------------------------+
 
-bool utcd_msg_send(uint8_t rhport, pd_header_t const* header, void const* data) {
+bool usbc_msg_send(uint8_t rhport, pd_header_t const* header, void const* data) {
   // copy header
   memcpy(_tx_buf, header, sizeof(pd_header_t));
 
@@ -179,7 +179,7 @@ bool tuc_msg_request(uint8_t rhport, void const* rdo) {
       .extended = 0,
   };
 
-  return utcd_msg_send(rhport, &header, rdo);
+  return usbc_msg_send(rhport, &header, rdo);
 }
 
 void tcd_event_handler(tcd_event_t const * event, bool in_isr) {
@@ -197,13 +197,13 @@ void tcd_event_handler(tcd_event_t const * event, bool in_isr) {
     default: break;
   }
 
-  osal_queue_send(_utcd_q, event, in_isr);
+  osal_queue_send(_usbc_q, event, in_isr);
 }
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
-void utcd_int_set(bool enabled) {
+void usbc_int_set(bool enabled) {
   // Disable all controllers since they shared the same event queue
   for (uint8_t p = 0; p < TUP_TYPEC_RHPORTS_NUM; p++) {
     if ( _port_inited[p] ) {
diff --git a/src/typec/utcd.h b/src/typec/usbc.h
similarity index 100%
rename from src/typec/utcd.h
rename to src/typec/usbc.h

From 8b8b9690ad8c546a8310c942ea926f654562f97c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jun 2023 12:01:21 +0700
Subject: [PATCH 1806/2085] update segger rtt to fix cast align

---
 hw/bsp/mcx/boards/mcxn947brk/board.cmake |   1 +
 hw/bsp/mcx/boards/mcxn947brk/board.mk    |   6 +-
 hw/bsp/mcx/family.cmake                  |   2 +-
 lib/SEGGER_RTT/RTT/SEGGER_RTT.c          |  50 +--
 lib/SEGGER_RTT/RTT/SEGGER_RTT.h          |  17 +-
 lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c   | 500 +++++++++++++++++++++++
 6 files changed, 545 insertions(+), 31 deletions(-)
 create mode 100644 lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c

diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
index 7a210628f..650f10967 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
@@ -10,6 +10,7 @@ function(update_board TARGET)
     CPU_MCXN947VDF_cm33_core0
     # port 1 is highspeed
     BOARD_TUD_RHPORT=1
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
     )
   target_sources(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.mk b/hw/bsp/mcx/boards/mcxn947brk/board.mk
index 69f47b8a8..aaad5e73e 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.mk
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.mk
@@ -4,8 +4,8 @@ PORT ?= 1
 
 CFLAGS += -DCPU_MCXN947VDF_cm33_core0
 
-JLINK_DEVICE = LPC55S69
-PYOCD_TARGET = LPC55S69
+JLINK_DEVICE = MCXN947_M33_0
+PYOCD_TARGET = MCXN947
 
 # flash using pyocd
-flash: flash-pyocd
+flash: flash-jlink
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 1dbf6f8f7..1c85b51f8 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -14,7 +14,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
+set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
 
 # enable LTO if supported
 include(CheckIPOSupported)
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
index 895085ba2..730a5cfb3 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
@@ -306,7 +306,7 @@ static unsigned char _ActiveTerminal;
   #define INIT()                                                                             \
     do {                                                                                     \
       volatile SEGGER_RTT_CB* pRTTCBInit;                                                    \
-      pRTTCBInit = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \
+      pRTTCBInit = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \
       if (pRTTCBInit->acID[0] != 'S') {                                                      \
         _DoInit();                                                                           \
       }                                                                                      \
@@ -319,7 +319,7 @@ static void _DoInit(void) {
   //
   // Initialize control block
   //
-  p                     = (volatile SEGGER_RTT_CB*)((char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
+  p                     = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly
   memset((SEGGER_RTT_CB*)p, 0, sizeof(_SEGGER_RTT));         // Make sure that the RTT CB is always zero initialized.
   p->MaxNumUpBuffers    = SEGGER_RTT_MAX_NUM_UP_BUFFERS;
   p->MaxNumDownBuffers  = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS;
@@ -581,7 +581,7 @@ unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsign
   volatile char*          pSrc;
 
   INIT();
-  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   pBuffer = (unsigned char*)pData;
   RdOff = pRing->RdOff;
   WrOff = pRing->WrOff;
@@ -673,7 +673,7 @@ unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned Buffe
   volatile char*          pSrc;
   //
   INIT();
-  pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   pBuffer = (unsigned char*)pData;
   RdOff = pRing->RdOff;
   WrOff = pRing->WrOff;
@@ -840,7 +840,7 @@ void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuff
   // Get "to-host" ring buffer and copy some elements into local variables.
   //
   pData = (const char *)pBuffer;
-  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Check if we will overwrite data and need to adjust the RdOff.
   //
@@ -1033,7 +1033,7 @@ unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuf
   // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be modified by J-Link.
   //
   pData = (const char *)pBuffer;
-  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // How we output depends upon the mode...
   //
@@ -1107,7 +1107,7 @@ unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsig
   // Get "to-host" ring buffer.
   //
   pData = (const char *)pBuffer;
-  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // How we output depends upon the mode...
   //
@@ -1271,7 +1271,7 @@ unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) {
   //
   // Get "to-host" ring buffer.
   //
-  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Get write position and handle wrap-around if necessary
   //
@@ -1326,7 +1326,7 @@ unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) {
   //
   // Get "to-host" ring buffer.
   //
-  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Get write position and handle wrap-around if necessary
   //
@@ -1385,7 +1385,7 @@ unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) {
   //
   // Get "to-host" ring buffer.
   //
-  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   //
   // Get write position and handle wrap-around if necessary
   //
@@ -1492,7 +1492,7 @@ int SEGGER_RTT_HasKey(void) {
   int r;
 
   INIT();
-  pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   RdOff = pRing->RdOff;
   if (RdOff != pRing->WrOff) {
     r = 1;
@@ -1518,7 +1518,7 @@ unsigned SEGGER_RTT_HasData(unsigned BufferIndex) {
   SEGGER_RTT_BUFFER_DOWN* pRing;
   unsigned                v;
 
-  pRing = (SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   v = pRing->WrOff;
   return v - pRing->RdOff;
 }
@@ -1539,7 +1539,7 @@ unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) {
   SEGGER_RTT_BUFFER_UP* pRing;
   unsigned                v;
 
-  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   v = pRing->RdOff;
   return pRing->WrOff - v;
 }
@@ -1570,7 +1570,7 @@ int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned Buffer
 
   INIT();
   SEGGER_RTT_LOCK();
-  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   BufferIndex = 0;
   do {
     if (pRTTCB->aDown[BufferIndex].pBuffer == NULL) {
@@ -1619,7 +1619,7 @@ int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSi
 
   INIT();
   SEGGER_RTT_LOCK();
-  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   BufferIndex = 0;
   do {
     if (pRTTCB->aUp[BufferIndex].pBuffer == NULL) {
@@ -1674,7 +1674,7 @@ int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBu
   volatile SEGGER_RTT_BUFFER_UP* pUp;
 
   INIT();
-  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
     SEGGER_RTT_LOCK();
     pUp = &pRTTCB->aUp[BufferIndex];
@@ -1726,7 +1726,7 @@ int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* p
   volatile SEGGER_RTT_BUFFER_DOWN* pDown;
 
   INIT();
-  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
     SEGGER_RTT_LOCK();
     pDown = &pRTTCB->aDown[BufferIndex];
@@ -1769,7 +1769,7 @@ int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) {
   volatile SEGGER_RTT_BUFFER_UP* pUp;
 
   INIT();
-  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
     SEGGER_RTT_LOCK();
     pUp = &pRTTCB->aUp[BufferIndex];
@@ -1804,7 +1804,7 @@ int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) {
   volatile SEGGER_RTT_BUFFER_DOWN* pDown;
 
   INIT();
-  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
     SEGGER_RTT_LOCK();
     pDown = &pRTTCB->aDown[BufferIndex];
@@ -1840,7 +1840,7 @@ int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) {
   volatile SEGGER_RTT_BUFFER_UP* pUp;
 
   INIT();
-  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) {
     SEGGER_RTT_LOCK();
     pUp = &pRTTCB->aUp[BufferIndex];
@@ -1876,7 +1876,7 @@ int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) {
   volatile SEGGER_RTT_BUFFER_DOWN* pDown;
 
   INIT();
-  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) {
     SEGGER_RTT_LOCK();
     pDown = &pRTTCB->aDown[BufferIndex];
@@ -1930,7 +1930,7 @@ int SEGGER_RTT_SetTerminal (unsigned char TerminalId) {
   ac[0] = 0xFFu;
   if (TerminalId < sizeof(_aTerminalId)) { // We only support a certain number of channels
     ac[1] = _aTerminalId[TerminalId];
-    pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+    pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
     SEGGER_RTT_LOCK();                     // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing
     if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) {
       _ActiveTerminal = TerminalId;
@@ -1982,7 +1982,7 @@ int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) {
     //
     // Get "to-host" ring buffer.
     //
-    pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+    pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
     //
     // Need to be able to change terminal, write data, change back.
     // Compute the fixed and variable sizes.
@@ -2059,7 +2059,7 @@ int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) {
 unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex) {
   SEGGER_RTT_BUFFER_UP* pRing;
 
-  pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF);  // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   return _GetAvailWriteSpace(pRing);
 }
 
@@ -2086,7 +2086,7 @@ unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) {
   // Avoid warnings regarding volatile access order.  It's not a problem
   // in this case, but dampen compiler enthusiasm.
   //
-  pRTTCB = (volatile SEGGER_RTT_CB*)((unsigned char*)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+  pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF);  // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
   RdOff = pRTTCB->aUp[BufferIndex].RdOff;
   WrOff = pRTTCB->aUp[BufferIndex].WrOff;
   if (RdOff <= WrOff) {
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.h b/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
index a3161f694..87f2841a5 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.h
@@ -91,6 +91,10 @@ Revision: $Rev: 25842 $
       #define _CORE_HAS_RTT_ASM_SUPPORT 1
       #define _CORE_NEEDS_DMB           1
       #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined(__ARM_ARCH_8_1M_MAIN__))       // Cortex-M85
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
     #else
       #define _CORE_HAS_RTT_ASM_SUPPORT 0
     #endif
@@ -121,6 +125,10 @@ Revision: $Rev: 25842 $
       #define _CORE_HAS_RTT_ASM_SUPPORT 1
       #define _CORE_NEEDS_DMB           1
       #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8_1M_MAIN__)        // Cortex-M85
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
     #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__))  // Cortex-A/R 32-bit ARMv7-A/R
       #define _CORE_NEEDS_DMB           1
       #define RTT__DMB() __asm volatile ("dmb\n" : : :);
@@ -147,6 +155,10 @@ Revision: $Rev: 25842 $
       #define _CORE_HAS_RTT_ASM_SUPPORT 1
       #define _CORE_NEEDS_DMB           1
       #define RTT__DMB() __asm volatile ("dmb\n" : : :);
+    #elif (defined __ARM_ARCH_8_1M_MAIN__)        // Cortex-M85
+      #define _CORE_HAS_RTT_ASM_SUPPORT 1
+      #define _CORE_NEEDS_DMB           1
+      #define RTT__DMB() __asm volatile ("dmb\n" : : :);
     #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__))  // Cortex-A/R 32-bit ARMv7-A/R
       #define _CORE_NEEDS_DMB           1
       #define RTT__DMB() __asm volatile ("dmb\n" : : :);
@@ -262,6 +274,7 @@ Revision: $Rev: 25842 $
 #ifndef SEGGER_RTT_ASM  // defined when SEGGER_RTT.h is included from assembly file
 #include <stdlib.h>
 #include <stdarg.h>
+#include <stdint.h>
 
 /*********************************************************************
 *
@@ -381,7 +394,7 @@ unsigned     SEGGER_RTT_GetBytesInBuffer        (unsigned BufferIndex);
 //
 // Function macro for performance optimization
 //
-#define      SEGGER_RTT_HASDATA(n)       (((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)
+#define      SEGGER_RTT_HASDATA(n)       (((SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)
 
 #if RTT_USE_ASM
   #define SEGGER_RTT_WriteSkipNoLock  SEGGER_RTT_ASM_WriteSkipNoLock
@@ -398,7 +411,7 @@ unsigned     SEGGER_RTT_ReadUpBufferNoLock      (unsigned BufferIndex, void* pDa
 unsigned     SEGGER_RTT_WriteDownBuffer         (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
 unsigned     SEGGER_RTT_WriteDownBufferNoLock   (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
 
-#define      SEGGER_RTT_HASDATA_UP(n)    (((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)   // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
+#define      SEGGER_RTT_HASDATA_UP(n)    (((SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff)   // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly
 
 /*********************************************************************
 *
diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c b/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c
new file mode 100644
index 000000000..4c996b408
--- /dev/null
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c
@@ -0,0 +1,500 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2019 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+*       SEGGER RTT * Real Time Transfer for embedded targets         *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* SEGGER strongly recommends to not make any changes                 *
+* to or modify the source code of this software in order to stay     *
+* compatible with the RTT protocol and J-Link.                       *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* o Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+---------------------------END-OF-HEADER------------------------------
+File    : SEGGER_RTT_printf.c
+Purpose : Replacement for printf to write formatted data via RTT
+Revision: $Rev: 17697 $
+----------------------------------------------------------------------
+*/
+#include "SEGGER_RTT.h"
+#include "SEGGER_RTT_Conf.h"
+
+/*********************************************************************
+*
+*       Defines, configurable
+*
+**********************************************************************
+*/
+
+#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE
+  #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64)
+#endif
+
+#include <stdlib.h>
+#include <stdarg.h>
+
+
+#define FORMAT_FLAG_LEFT_JUSTIFY   (1u << 0)
+#define FORMAT_FLAG_PAD_ZERO       (1u << 1)
+#define FORMAT_FLAG_PRINT_SIGN     (1u << 2)
+#define FORMAT_FLAG_ALTERNATE      (1u << 3)
+
+/*********************************************************************
+*
+*       Types
+*
+**********************************************************************
+*/
+
+typedef struct {
+  char*     pBuffer;
+  unsigned  BufferSize;
+  unsigned  Cnt;
+
+  int   ReturnValue;
+
+  unsigned RTTBufferIndex;
+} SEGGER_RTT_PRINTF_DESC;
+
+/*********************************************************************
+*
+*       Function prototypes
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       Static code
+*
+**********************************************************************
+*/
+/*********************************************************************
+*
+*       _StoreChar
+*/
+static void _StoreChar(SEGGER_RTT_PRINTF_DESC * p, char c) {
+  unsigned Cnt;
+
+  Cnt = p->Cnt;
+  if ((Cnt + 1u) <= p->BufferSize) {
+    *(p->pBuffer + Cnt) = c;
+    p->Cnt = Cnt + 1u;
+    p->ReturnValue++;
+  }
+  //
+  // Write part of string, when the buffer is full
+  //
+  if (p->Cnt == p->BufferSize) {
+    if (SEGGER_RTT_Write(p->RTTBufferIndex, p->pBuffer, p->Cnt) != p->Cnt) {
+      p->ReturnValue = -1;
+    } else {
+      p->Cnt = 0u;
+    }
+  }
+}
+
+/*********************************************************************
+*
+*       _PrintUnsigned
+*/
+static void _PrintUnsigned(SEGGER_RTT_PRINTF_DESC * pBufferDesc, unsigned v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) {
+  static const char _aV2C[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
+  unsigned Div;
+  unsigned Digit;
+  unsigned Number;
+  unsigned Width;
+  char c;
+
+  Number = v;
+  Digit = 1u;
+  //
+  // Get actual field width
+  //
+  Width = 1u;
+  while (Number >= Base) {
+    Number = (Number / Base);
+    Width++;
+  }
+  if (NumDigits > Width) {
+    Width = NumDigits;
+  }
+  //
+  // Print leading chars if necessary
+  //
+  if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) {
+    if (FieldWidth != 0u) {
+      if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && (NumDigits == 0u)) {
+        c = '0';
+      } else {
+        c = ' ';
+      }
+      while ((FieldWidth != 0u) && (Width < FieldWidth)) {
+        FieldWidth--;
+        _StoreChar(pBufferDesc, c);
+        if (pBufferDesc->ReturnValue < 0) {
+          break;
+        }
+      }
+    }
+  }
+  if (pBufferDesc->ReturnValue >= 0) {
+    //
+    // Compute Digit.
+    // Loop until Digit has the value of the highest digit required.
+    // Example: If the output is 345 (Base 10), loop 2 times until Digit is 100.
+    //
+    while (1) {
+      if (NumDigits > 1u) {       // User specified a min number of digits to print? => Make sure we loop at least that often, before checking anything else (> 1 check avoids problems with NumDigits being signed / unsigned)
+        NumDigits--;
+      } else {
+        Div = v / Digit;
+        if (Div < Base) {        // Is our divider big enough to extract the highest digit from value? => Done
+          break;
+        }
+      }
+      Digit *= Base;
+    }
+    //
+    // Output digits
+    //
+    do {
+      Div = v / Digit;
+      v -= Div * Digit;
+      _StoreChar(pBufferDesc, _aV2C[Div]);
+      if (pBufferDesc->ReturnValue < 0) {
+        break;
+      }
+      Digit /= Base;
+    } while (Digit);
+    //
+    // Print trailing spaces if necessary
+    //
+    if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == FORMAT_FLAG_LEFT_JUSTIFY) {
+      if (FieldWidth != 0u) {
+        while ((FieldWidth != 0u) && (Width < FieldWidth)) {
+          FieldWidth--;
+          _StoreChar(pBufferDesc, ' ');
+          if (pBufferDesc->ReturnValue < 0) {
+            break;
+          }
+        }
+      }
+    }
+  }
+}
+
+/*********************************************************************
+*
+*       _PrintInt
+*/
+static void _PrintInt(SEGGER_RTT_PRINTF_DESC * pBufferDesc, int v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) {
+  unsigned Width;
+  int Number;
+
+  Number = (v < 0) ? -v : v;
+
+  //
+  // Get actual field width
+  //
+  Width = 1u;
+  while (Number >= (int)Base) {
+    Number = (Number / (int)Base);
+    Width++;
+  }
+  if (NumDigits > Width) {
+    Width = NumDigits;
+  }
+  if ((FieldWidth > 0u) && ((v < 0) || ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN))) {
+    FieldWidth--;
+  }
+
+  //
+  // Print leading spaces if necessary
+  //
+  if ((((FormatFlags & FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) {
+    if (FieldWidth != 0u) {
+      while ((FieldWidth != 0u) && (Width < FieldWidth)) {
+        FieldWidth--;
+        _StoreChar(pBufferDesc, ' ');
+        if (pBufferDesc->ReturnValue < 0) {
+          break;
+        }
+      }
+    }
+  }
+  //
+  // Print sign if necessary
+  //
+  if (pBufferDesc->ReturnValue >= 0) {
+    if (v < 0) {
+      v = -v;
+      _StoreChar(pBufferDesc, '-');
+    } else if ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN) {
+      _StoreChar(pBufferDesc, '+');
+    } else {
+
+    }
+    if (pBufferDesc->ReturnValue >= 0) {
+      //
+      // Print leading zeros if necessary
+      //
+      if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) && (NumDigits == 0u)) {
+        if (FieldWidth != 0u) {
+          while ((FieldWidth != 0u) && (Width < FieldWidth)) {
+            FieldWidth--;
+            _StoreChar(pBufferDesc, '0');
+            if (pBufferDesc->ReturnValue < 0) {
+              break;
+            }
+          }
+        }
+      }
+      if (pBufferDesc->ReturnValue >= 0) {
+        //
+        // Print number without sign
+        //
+        _PrintUnsigned(pBufferDesc, (unsigned)v, Base, NumDigits, FieldWidth, FormatFlags);
+      }
+    }
+  }
+}
+
+/*********************************************************************
+*
+*       Public code
+*
+**********************************************************************
+*/
+/*********************************************************************
+*
+*       SEGGER_RTT_vprintf
+*
+*  Function description
+*    Stores a formatted string in SEGGER RTT control block.
+*    This data is read by the host.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used. (e.g. 0 for "Terminal")
+*    sFormat      Pointer to format string
+*    pParamList   Pointer to the list of arguments for the format string
+*
+*  Return values
+*    >= 0:  Number of bytes which have been stored in the "Up"-buffer.
+*     < 0:  Error
+*/
+int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList) {
+  char c;
+  SEGGER_RTT_PRINTF_DESC BufferDesc;
+  int v;
+  unsigned NumDigits;
+  unsigned FormatFlags;
+  unsigned FieldWidth;
+  char acBuffer[SEGGER_RTT_PRINTF_BUFFER_SIZE];
+
+  BufferDesc.pBuffer        = acBuffer;
+  BufferDesc.BufferSize     = SEGGER_RTT_PRINTF_BUFFER_SIZE;
+  BufferDesc.Cnt            = 0u;
+  BufferDesc.RTTBufferIndex = BufferIndex;
+  BufferDesc.ReturnValue    = 0;
+
+  do {
+    c = *sFormat;
+    sFormat++;
+    if (c == 0u) {
+      break;
+    }
+    if (c == '%') {
+      //
+      // Filter out flags
+      //
+      FormatFlags = 0u;
+      v = 1;
+      do {
+        c = *sFormat;
+        switch (c) {
+        case '-': FormatFlags |= FORMAT_FLAG_LEFT_JUSTIFY; sFormat++; break;
+        case '0': FormatFlags |= FORMAT_FLAG_PAD_ZERO;     sFormat++; break;
+        case '+': FormatFlags |= FORMAT_FLAG_PRINT_SIGN;   sFormat++; break;
+        case '#': FormatFlags |= FORMAT_FLAG_ALTERNATE;    sFormat++; break;
+        default:  v = 0; break;
+        }
+      } while (v);
+      //
+      // filter out field with
+      //
+      FieldWidth = 0u;
+      do {
+        c = *sFormat;
+        if ((c < '0') || (c > '9')) {
+          break;
+        }
+        sFormat++;
+        FieldWidth = (FieldWidth * 10u) + ((unsigned)c - '0');
+      } while (1);
+
+      //
+      // Filter out precision (number of digits to display)
+      //
+      NumDigits = 0u;
+      c = *sFormat;
+      if (c == '.') {
+        sFormat++;
+        do {
+          c = *sFormat;
+          if ((c < '0') || (c > '9')) {
+            break;
+          }
+          sFormat++;
+          NumDigits = NumDigits * 10u + ((unsigned)c - '0');
+        } while (1);
+      }
+      //
+      // Filter out length modifier
+      //
+      c = *sFormat;
+      do {
+        if ((c == 'l') || (c == 'h')) {
+          sFormat++;
+          c = *sFormat;
+        } else {
+          break;
+        }
+      } while (1);
+      //
+      // Handle specifiers
+      //
+      switch (c) {
+      case 'c': {
+        char c0;
+        v = va_arg(*pParamList, int);
+        c0 = (char)v;
+        _StoreChar(&BufferDesc, c0);
+        break;
+      }
+      case 'd':
+        v = va_arg(*pParamList, int);
+        _PrintInt(&BufferDesc, v, 10u, NumDigits, FieldWidth, FormatFlags);
+        break;
+      case 'u':
+        v = va_arg(*pParamList, int);
+        _PrintUnsigned(&BufferDesc, (unsigned)v, 10u, NumDigits, FieldWidth, FormatFlags);
+        break;
+      case 'x':
+      case 'X':
+        v = va_arg(*pParamList, int);
+        _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, NumDigits, FieldWidth, FormatFlags);
+        break;
+      case 's':
+        {
+          const char * s = va_arg(*pParamList, const char *);
+          do {
+            c = *s;
+            s++;
+            if (c == '\0') {
+              break;
+            }
+           _StoreChar(&BufferDesc, c);
+          } while (BufferDesc.ReturnValue >= 0);
+        }
+        break;
+      case 'p':
+        v = va_arg(*pParamList, int);
+        _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, 8u, 8u, 0u);
+        break;
+      case '%':
+        _StoreChar(&BufferDesc, '%');
+        break;
+      default:
+        break;
+      }
+      sFormat++;
+    } else {
+      _StoreChar(&BufferDesc, c);
+    }
+  } while (BufferDesc.ReturnValue >= 0);
+
+  if (BufferDesc.ReturnValue > 0) {
+    //
+    // Write remaining data, if any
+    //
+    if (BufferDesc.Cnt != 0u) {
+      SEGGER_RTT_Write(BufferIndex, acBuffer, BufferDesc.Cnt);
+    }
+    BufferDesc.ReturnValue += (int)BufferDesc.Cnt;
+  }
+  return BufferDesc.ReturnValue;
+}
+
+/*********************************************************************
+*
+*       SEGGER_RTT_printf
+*
+*  Function description
+*    Stores a formatted string in SEGGER RTT control block.
+*    This data is read by the host.
+*
+*  Parameters
+*    BufferIndex  Index of "Up"-buffer to be used. (e.g. 0 for "Terminal")
+*    sFormat      Pointer to format string, followed by the arguments for conversion
+*
+*  Return values
+*    >= 0:  Number of bytes which have been stored in the "Up"-buffer.
+*     < 0:  Error
+*
+*  Notes
+*    (1) Conversion specifications have following syntax:
+*          %[flags][FieldWidth][.Precision]ConversionSpecifier
+*    (2) Supported flags:
+*          -: Left justify within the field width
+*          +: Always print sign extension for signed conversions
+*          0: Pad with 0 instead of spaces. Ignored when using '-'-flag or precision
+*        Supported conversion specifiers:
+*          c: Print the argument as one char
+*          d: Print the argument as a signed integer
+*          u: Print the argument as an unsigned integer
+*          x: Print the argument as an hexadecimal integer
+*          s: Print the string pointed to by the argument
+*          p: Print the argument as an 8-digit hexadecimal integer. (Argument shall be a pointer to void.)
+*/
+int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...) {
+  int r;
+  va_list ParamList;
+
+  va_start(ParamList, sFormat);
+  r = SEGGER_RTT_vprintf(BufferIndex, sFormat, &ParamList);
+  va_end(ParamList);
+  return r;
+}
+/*************************** End of file ****************************/

From 31a66eb5bcd09ee62d3a28069ae6a5e7d6e2ec08 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jun 2023 15:33:57 +0700
Subject: [PATCH 1807/2085] mcx neeed helps to locate rtt control block

---
 .idea/runConfigurations/mcx947_jlink.xml | 10 ++++++++++
 hw/bsp/mcx/mcx.jlinkscript               |  5 +++++
 2 files changed, 15 insertions(+)
 create mode 100644 .idea/runConfigurations/mcx947_jlink.xml
 create mode 100644 hw/bsp/mcx/mcx.jlinkscript

diff --git a/.idea/runConfigurations/mcx947_jlink.xml b/.idea/runConfigurations/mcx947_jlink.xml
new file mode 100644
index 000000000..71616ab70
--- /dev/null
+++ b/.idea/runConfigurations/mcx947_jlink.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="mcx947 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/mcx.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcxn947" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/hw/bsp/mcx/mcx.jlinkscript b/hw/bsp/mcx/mcx.jlinkscript
new file mode 100644
index 000000000..fd8bcffef
--- /dev/null
+++ b/hw/bsp/mcx/mcx.jlinkscript
@@ -0,0 +1,5 @@
+int SetupTarget(void) {
+  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
+
+  return 0;
+}

From bce282186e811a7eefcee52c4a4fb3ca107001e4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 14 Jun 2023 22:36:44 +0700
Subject: [PATCH 1808/2085] update kinetis kl to use mcx-sdk, also add cmake
 support

note: cdc_msc_freertos built but does not seems to work with kl
---
 .../FreeRTOSConfig/FreeRTOSConfig.h           | 166 ++++++++
 .../kinetis_kl/boards/frdm_kl25z/board.cmake  |  18 +
 hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h   |  58 +++
 hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk  |   7 +-
 .../boards/frdm_kl25z/clock_config.c          | 307 ++++++++++++++
 .../boards/frdm_kl25z/clock_config.h          | 130 ++++++
 .../frdm_kl25z/frdm_kl25z.c => family.c}      |  41 +-
 hw/bsp/kinetis_kl/family.cmake                | 126 ++++++
 hw/bsp/kinetis_kl/family.mk                   |  24 +-
 hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld  | 253 ++++++++++++
 hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S       | 383 ++++++++++++++++++
 tools/get_deps.py                             |   3 -
 tools/get_family_deps.py                      |  21 -
 13 files changed, 1464 insertions(+), 73 deletions(-)
 create mode 100644 hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/kinetis_kl/boards/frdm_kl25z/board.cmake
 create mode 100644 hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h
 create mode 100644 hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c
 create mode 100644 hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.h
 rename hw/bsp/kinetis_kl/{boards/frdm_kl25z/frdm_kl25z.c => family.c} (74%)
 create mode 100644 hw/bsp/kinetis_kl/family.cmake
 create mode 100644 hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld
 create mode 100644 hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S
 delete mode 100644 tools/get_family_deps.py

diff --git a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..960bb23e1
--- /dev/null
+++ b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,166 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+// FIXME cause redundant-decls warnings
+extern uint32_t SystemCoreClock;
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU						0
+#define configENABLE_FPU						1
+#define configENABLE_TRUSTZONE					0
+#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.cmake b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.cmake
new file mode 100644
index 000000000..d34a56840
--- /dev/null
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.cmake
@@ -0,0 +1,18 @@
+set(MCU_VARIANT MKL25Z4)
+
+set(JLINK_DEVICE MKL25Z128xxx4)
+set(PYOCD_TARGET mkl25zl128)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../gcc/MKL25Z128xxx4_flash.ld)
+set(STARTUP_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../gcc/startup_MKL25Z4.S)
+
+function(update_board TARGET)
+  target_sources(${TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
+    )
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_MKL25Z128VLK4
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h
new file mode 100644
index 000000000..23f144666
--- /dev/null
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h
@@ -0,0 +1,58 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+// LED
+#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
+#define LED_PORT              GPIOB
+#define LED_PIN_CLOCK         kCLOCK_PortB
+#define LED_PIN_PORT          PORTB
+#define LED_PIN               19U
+#define LED_PIN_FUNCTION      kPORT_MuxAsGpio
+#define LED_STATE_ON          0
+
+// Button
+#define BUTTON_PORT           GPIOC
+#define BUTTON_PIN_CLOCK      kCLOCK_PortC
+#define BUTTON_PIN_PORT       PORTC
+#define BUTTON_PIN            9U
+#define BUTTON_PIN_FUNCTION   kPORT_MuxAsGpio
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_PORT             UART0
+#define UART_PIN_CLOCK        kCLOCK_PortA
+#define UART_PIN_PORT         PORTA
+#define UART_PIN_RX           1u
+#define UART_PIN_TX           2u
+#define UART_PIN_FUNCTION     kPORT_MuxAlt2
+#define SOPT5_UART0RXSRC_UART_RX      0x00u   /*!< UART0 receive data source select: UART0_RX pin */
+#define SOPT5_UART0TXSRC_UART_TX      0x00u   /*!< UART0 transmit data source select: UART0_TX pin */
+
+#endif
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
index 0d0bceaa4..efd922c5e 100644
--- a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.mk
@@ -8,8 +8,13 @@ CFLAGS += \
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=format -Wno-error=redundant-decls
 
+SRC_C += \
+	$(BOARD_PATH)/clock_config.c \
+
 # All source paths should be relative to the top level.
-LD_FILE = $(MCU_DIR)/gcc/MKL25Z128xxx4_flash.ld
+LD_FILE = $(FAMILY_PATH)/gcc/MKL25Z128xxx4_flash.ld
+
+SRC_S += $(FAMILY_PATH)/gcc/startup_$(MCU).S
 
 # For flash-jlink target
 JLINK_DEVICE = MKL25Z128xxx4
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c
new file mode 100644
index 000000000..1ba35e0dc
--- /dev/null
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ *    and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ *    internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ *        explicitly to setup MCGIRCLK.
+ *
+ *    3). Don't need to configure FLL explicitly, because if target mode is FLL
+ *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ *        if the target mode is not FLL mode, the FLL is disabled.
+ *
+ *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!ClocksProfile
+product: Clocks v1.0
+processor: MKL25Z128xxx4
+package_id: MKL25Z128VLK4
+mcu_data: ksdk2_0
+processor_version: 1.1.0
+board: FRDM-KL25Z
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+#include "fsl_smc.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_PLL_DISABLE                                   0U  /*!< MCGPLLCLK disabled */
+#define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_LPO_CLK                             3U  /*!< OSC32KSEL select: LPO clock */
+#define SIM_PLLFLLSEL_MCGFLLCLK_CLK                       0U  /*!< PLLFLL select: MCGFLLCLK clock */
+#define SIM_PLLFLLSEL_MCGPLLCLK_CLK                       1U  /*!< PLLFLL select: MCGPLLCLK clock */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Code
+******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
+ * Description   : Configure FLL external reference divider (FRDIV).
+ * Param frdiv   : The value to set FRDIV.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
+{
+    MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 24 MHz}
+- {id: Core_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
+- {id: ERCLK32K.outFreq, value: 1 kHz}
+- {id: Flash_clock.outFreq, value: 24 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
+- {id: OSCERCLK.outFreq, value: 8 MHz}
+- {id: PLLFLLCLK.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: MCGMode, value: PEE}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IREFS.sel, value: MCG.FRDIV}
+- {id: MCG.PLLS.sel, value: MCG.PLL}
+- {id: MCG.PRDIV.scale, value: '2', locked: true}
+- {id: MCG.VDIV.scale, value: '24', locked: true}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: High}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
+- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
+- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
+- {id: SIM.CLKOUTSEL.sel, value: SIM.OUTDIV4}
+- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.OUTDIV1.scale, value: '2'}
+- {id: SIM.PLLFLLSEL.sel, value: SIM.MCGPLLCLK_DIV2}
+- {id: SIM.TPMSRCSEL.sel, value: SIM.PLLFLLSEL}
+- {id: SIM.UART0SRCSEL.sel, value: SIM.PLLFLLSEL}
+- {id: SIM.USBSRCSEL.sel, value: SIM.PLLFLLSEL}
+sources:
+- {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN =
+    {
+        .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcSlow,                     /* Slow internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x1U,                    /* PLL Reference divider: divided by 2 */
+                .vdiv = 0x0U,                     /* VCO divider: multiplied by 24 */
+            },
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+        .er32kSrc = SIM_OSC32KSEL_LPO_CLK,        /* OSC32KSEL select: LPO clock */
+        .clkdiv1 = 0x10010000U,                   /* SIM_CLKDIV1 - OUTDIV1: /2, OUTDIV4: /2 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 8000000U,                         /* Oscillator frequency: 8000000Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = kOSC_ErClkEnable,   /* Enable external reference clock, disable external reference clock in STOP mode */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
+    /* Configure FLL external reference divider (FRDIV). */
+    CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
+    /* Set MCG to PEE mode. */
+    CLOCK_BootToPeeMode(kMCG_OscselOsc,
+                        kMCG_PllClkSelPll0,
+                        &mcgConfig_BOARD_BootClockRUN.pll0Config);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
+                                  mcgConfig_BOARD_BootClockRUN.ircs,
+                                  mcgConfig_BOARD_BootClockRUN.fcrdiv);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 800 kHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: ERCLK32K.outFreq, value: 1 kHz}
+- {id: Flash_clock.outFreq, value: 800 kHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGIRCLK.outFreq, value: 4 MHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: MCGMode, value: BLPI}
+- {id: powerMode, value: VLPR}
+- {id: MCG.CLKS.sel, value: MCG.IRCS}
+- {id: MCG.FCRDIV.scale, value: '1', locked: true}
+- {id: MCG.FRDIV.scale, value: '32'}
+- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
+- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
+- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
+- {id: MCG_C2_RANGE0_CFG, value: High}
+- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
+- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
+- {id: SIM.OUTDIV4.scale, value: '5'}
+sources:
+- {id: OSC.OSC.outFreq, value: 8 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
+    {
+        .mcgMode = kMCG_ModeBLPI,                 /* BLPI - Bypassed Low Power Internal */
+        .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
+        .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
+        .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
+        .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 32 */
+        .drs = kMCG_DrsLow,                       /* Low frequency range */
+        .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
+        .pll0Config =
+            {
+                .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
+                .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
+                .vdiv = 0x0U,                     /* VCO divider: multiplied by 24 */
+            },
+    };
+const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
+    {
+        .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+        .er32kSrc = SIM_OSC32KSEL_LPO_CLK,        /* OSC32KSEL select: LPO clock */
+        .clkdiv1 = 0x40000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /5 */
+    };
+const osc_config_t oscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 0U,                               /* Oscillator frequency: 0Hz */
+        .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
+        .workMode = kOSC_ModeOscLowPower,         /* Oscillator low power */
+        .oscerConfig =
+            {
+                .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+            }
+    };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetSimSafeDivs();
+    /* Set MCG to BLPI mode. */
+    CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
+                         mcgConfig_BOARD_BootClockVLPR.ircs,
+                         mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
+    SMC_SetPowerModeVlpr(SMC, false);
+#else
+    SMC_SetPowerModeVlpr(SMC);
+#endif
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
+    {
+    }
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+}
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.h b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.h
new file mode 100644
index 000000000..1033d4e55
--- /dev/null
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#define BOARD_XTAL0_CLK_HZ                          8000000U  /*!< Board xtal0 frequency in Hz */
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockRUN configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
+/*! @brief SIM module set for BOARD_BootClockRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
+/*! @brief OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              4000000U  /*!< Core clock frequency: 4000000Hz */
+
+/*! @brief MCG set for BOARD_BootClockVLPR configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
+/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
+/*! @brief OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
+
+/*******************************************************************************
+ * API for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/frdm_kl25z.c b/hw/bsp/kinetis_kl/family.c
similarity index 74%
rename from hw/bsp/kinetis_kl/boards/frdm_kl25z/frdm_kl25z.c
rename to hw/bsp/kinetis_kl/family.c
index 46f85f6a5..8914078d5 100644
--- a/hw/bsp/kinetis_kl/boards/frdm_kl25z/frdm_kl25z.c
+++ b/hw/bsp/kinetis_kl/family.c
@@ -21,11 +21,10 @@
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#include "bsp/board.h"
+#include "board.h"
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
 #include "fsl_port.h"
@@ -47,38 +46,6 @@ void USB0_IRQHandler(void)
 #endif
 }
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
-// LED
-#define LED_PINMUX            IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
-#define LED_PORT              GPIOB
-#define LED_PIN_CLOCK         kCLOCK_PortB
-#define LED_PIN_PORT          PORTB
-#define LED_PIN               19U
-#define LED_PIN_FUNCTION      kPORT_MuxAsGpio
-#define LED_STATE_ON          0
-
-// Button
-#define BUTTON_PORT           GPIOC
-#define BUTTON_PIN_CLOCK      kCLOCK_PortC
-#define BUTTON_PIN_PORT       PORTC
-#define BUTTON_PIN            9U
-#define BUTTON_PIN_FUNCTION   kPORT_MuxAsGpio
-#define BUTTON_STATE_ACTIVE   0
-
-// UART
-#define UART_PORT             UART0
-#define UART_PIN_CLOCK        kCLOCK_PortA
-#define UART_PIN_PORT         PORTA
-#define UART_PIN_RX           1u
-#define UART_PIN_TX           2u
-#define UART_PIN_FUNCTION     kPORT_MuxAlt2
-#define SOPT5_UART0RXSRC_UART_RX      0x00u   /*!< UART0 receive data source select: UART0_RX pin */
-#define SOPT5_UART0TXSRC_UART_TX      0x00u   /*!< UART0 transmit data source select: UART0_TX pin */
-
-const uint8_t dcd_data[] = { 0x00 };
-
 void board_init(void)
 {
   BOARD_BootClockRUN();
@@ -139,13 +106,13 @@ void board_init(void)
 
 void board_led_write(bool state)
 {
-  GPIO_WritePinOutput(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
 }
 
 uint32_t board_button_read(void)
 {
 #if defined(BUTTON_PORT) && defined(BUTTON_PIN)
-  return BUTTON_STATE_ACTIVE == GPIO_ReadPinInput(BUTTON_PORT, BUTTON_PIN);
+  return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
 #endif
   return 0;
 }
diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake
new file mode 100644
index 000000000..77b932b8e
--- /dev/null
+++ b/hw/bsp/kinetis_kl/family.cmake
@@ -0,0 +1,126 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "")
+
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${SDK_DIR}/drivers/gpio/fsl_gpio.c
+      ${SDK_DIR}/drivers/lpsci/fsl_lpsci.c
+      ${SDK_DIR}/drivers/uart/fsl_uart.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      ${SDK_DIR}/devices/${MCU_VARIANT}
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+      ${SDK_DIR}/drivers/common
+      ${SDK_DIR}/drivers/gpio
+      ${SDK_DIR}/drivers/lpsci
+      ${SDK_DIR}/drivers/port
+      ${SDK_DIR}/drivers/smc
+      ${SDK_DIR}/drivers/uart
+      )
+
+    update_board(${BOARD_TARGET})
+
+    # LD_FILE and STARTUP_FILE can be defined in board.cmake
+
+    target_sources(${BOARD_TARGET} PUBLIC
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET)
+  family_configure_common(${TARGET})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # TinyUSB Port
+    ${TOP}/src/portable/nxp/khci/dcd_khci.c
+    ${TOP}/src/portable/nxp/khci/hcd_khci.c
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB
+  family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL)
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+endfunction()
+
+
+function(family_configure_device_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
diff --git a/hw/bsp/kinetis_kl/family.mk b/hw/bsp/kinetis_kl/family.mk
index e805d6dae..2bed6b486 100644
--- a/hw/bsp/kinetis_kl/family.mk
+++ b/hw/bsp/kinetis_kl/family.mk
@@ -1,5 +1,5 @@
-SDK_DIR = hw/mcu/nxp/nxp_sdk
-DEPS_SUBMODULES += $(SDK_DIR)
+SDK_DIR = hw/mcu/nxp/mcux-sdk
+DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
@@ -18,20 +18,22 @@ SRC_C += \
 	src/portable/nxp/khci/dcd_khci.c \
 	src/portable/nxp/khci/hcd_khci.c \
 	$(MCU_DIR)/system_$(MCU).c \
-	$(MCU_DIR)/project_template/clock_config.c \
 	$(MCU_DIR)/drivers/fsl_clock.c \
-	$(MCU_DIR)/drivers/fsl_gpio.c \
-	$(MCU_DIR)/drivers/fsl_lpsci.c \
-	$(MCU_DIR)/drivers/fsl_uart.c
+	$(SDK_DIR)/drivers/gpio/fsl_gpio.c \
+	$(SDK_DIR)/drivers/lpsci/fsl_lpsci.c \
+	$(SDK_DIR)/drivers/uart/fsl_uart.c \
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/$(SDK_DIR)/CMSIS/Include \
+	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR) \
-	$(TOP)/$(MCU_DIR)/project_template \
-	$(TOP)/$(MCU_DIR)/drivers
-
-SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
+	$(TOP)/$(MCU_DIR)/drivers \
+	$(TOP)/$(SDK_DIR)/drivers/common \
+	$(TOP)/$(SDK_DIR)/drivers/gpio \
+	$(TOP)/$(SDK_DIR)/drivers/lpsci \
+	$(TOP)/$(SDK_DIR)/drivers/port \
+	$(TOP)/$(SDK_DIR)/drivers/smc \
+	$(TOP)/$(SDK_DIR)/drivers/uart \
 
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld b/hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld
new file mode 100644
index 000000000..b38aa827c
--- /dev/null
+++ b/hw/bsp/kinetis_kl/gcc/MKL25Z128xxx4_flash.ld
@@ -0,0 +1,253 @@
+/*
+** ###################################################################
+**     Processors:          MKL25Z128VFM4
+**                          MKL25Z128VFT4
+**                          MKL25Z128VLH4
+**                          MKL25Z128VLK4
+**
+**     Compiler:            GNU C Compiler
+**     Reference manual:    KL25P80M48SF0RM, Rev.3, Sep 2012
+**     Version:             rev. 2.5, 2015-02-19
+**     Build:               b170214
+**
+**     Abstract:
+**         Linker file for the GNU C Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0200 : 0x0;
+
+/* Specify the memory areas */
+MEMORY
+{
+  m_interrupts          (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00000200
+  m_flash_config        (RX)  : ORIGIN = 0x00000400, LENGTH = 0x00000010
+  m_text                (RX)  : ORIGIN = 0x00000410, LENGTH = 0x0001FBF0
+  m_data                (RW)  : ORIGIN = 0x1FFFF000, LENGTH = 0x00004000
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into internal flash */
+  .interrupts :
+  {
+    __VECTOR_TABLE = .;
+    . = ALIGN(4);
+    KEEP(*(.isr_vector))     /* Startup code */
+    . = ALIGN(4);
+  } > m_interrupts
+
+  .flash_config :
+  {
+    . = ALIGN(4);
+    KEEP(*(.FlashConfig))    /* Flash Configuration Field (FCF) */
+    . = ALIGN(4);
+  } > m_flash_config
+
+  /* The program code and other data goes into internal flash */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)                 /* .text sections (code) */
+    *(.text*)                /* .text* sections (code) */
+    *(.rodata)               /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)              /* .rodata* sections (constants, strings, etc.) */
+    *(.glue_7)               /* glue arm to thumb code */
+    *(.glue_7t)              /* glue thumb to arm code */
+    *(.eh_frame)
+    KEEP (*(.init))
+    KEEP (*(.fini))
+    . = ALIGN(4);
+  } > m_text
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } > m_text
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } > m_text
+
+ .ctors :
+  {
+    __CTOR_LIST__ = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __CTOR_END__ = .;
+  } > m_text
+
+  .dtors :
+  {
+    __DTOR_LIST__ = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    __DTOR_END__ = .;
+  } > m_text
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } > m_text
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } > m_text
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } > m_text
+
+  __etext = .;    /* define a global symbol at end of code */
+  __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+  /* reserve MTB memory at the beginning of m_data */
+  .mtb : /* MTB buffer address as defined by the hardware */
+  {
+    . = ALIGN(8);
+    _mtb_start = .;
+    KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+    . = ALIGN(8);
+    _mtb_end = .;
+  } > m_data
+
+  .interrupts_ram :
+  {
+    . = ALIGN(4);
+    __VECTOR_RAM__ = .;
+    __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+    *(.m_interrupts_ram)     /* This is a user defined section */
+    . += M_VECTOR_RAM_SIZE;
+    . = ALIGN(4);
+    __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+  } > m_data
+
+  __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+  __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+  .data : AT(__DATA_ROM)
+  {
+    . = ALIGN(4);
+    __DATA_RAM = .;
+    __data_start__ = .;      /* create a global symbol at data start */
+    *(.data)                 /* .data sections */
+    *(.data*)                /* .data* sections */
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+    __data_end__ = .;        /* define a global symbol at data end */
+  } > m_data
+
+  __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+  text_end = ORIGIN(m_text) + LENGTH(m_text);
+  ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+  /* Uninitialized data section */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    . = ALIGN(4);
+    __START_BSS = .;
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+    __END_BSS = .;
+  } > m_data
+
+  .heap :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    __HeapBase = .;
+    . += HEAP_SIZE;
+    __HeapLimit = .;
+    __heap_limit = .; /* Add for _sbrk */
+  } > m_data
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += STACK_SIZE;
+  } > m_data
+
+  /* Initializes stack on the end of block */
+  __StackTop   = ORIGIN(m_data) + LENGTH(m_data);
+  __StackLimit = __StackTop - STACK_SIZE;
+  PROVIDE(__stack = __StackTop);
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
diff --git a/hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S b/hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S
new file mode 100644
index 000000000..dc1438f3a
--- /dev/null
+++ b/hw/bsp/kinetis_kl/gcc/startup_MKL25Z4.S
@@ -0,0 +1,383 @@
+/* ---------------------------------------------------------------------------------------*/
+/*  @file:    startup_MKL25Z4.s                                                           */
+/*  @purpose: CMSIS Cortex-M0P Core Device Startup File                                   */
+/*            MKL25Z4                                                                     */
+/*  @version: 2.5                                                                         */
+/*  @date:    2015-2-19                                                                   */
+/*  @build:   b170112                                                                     */
+/* ---------------------------------------------------------------------------------------*/
+/*                                                                                        */
+/* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc.                               */
+/* Copyright 2016 - 2017 NXP                                                              */
+/* Redistribution and use in source and binary forms, with or without modification,       */
+/* are permitted provided that the following conditions are met:                          */
+/*                                                                                        */
+/* o Redistributions of source code must retain the above copyright notice, this list     */
+/*   of conditions and the following disclaimer.                                          */
+/*                                                                                        */
+/* o Redistributions in binary form must reproduce the above copyright notice, this       */
+/*   list of conditions and the following disclaimer in the documentation and/or          */
+/*   other materials provided with the distribution.                                      */
+/*                                                                                        */
+/* o Neither the name of the copyright holder nor the names of its                        */
+/*   contributors may be used to endorse or promote products derived from this            */
+/*   software without specific prior written permission.                                  */
+/*                                                                                        */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND        */
+/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED          */
+/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE                 */
+/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR       */
+/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES         */
+/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;           */
+/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON         */
+/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT                */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS          */
+/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors                                  */
+/*****************************************************************************/
+    .syntax unified
+    .arch armv6-m
+
+    .section .isr_vector, "a"
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long   __StackTop                                      /* Top of Stack */
+    .long   Reset_Handler                                   /* Reset Handler */
+    .long   NMI_Handler                                     /* NMI Handler*/
+    .long   HardFault_Handler                               /* Hard Fault Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   SVC_Handler                                     /* SVCall Handler*/
+    .long   0                                               /* Reserved*/
+    .long   0                                               /* Reserved*/
+    .long   PendSV_Handler                                  /* PendSV Handler*/
+    .long   SysTick_Handler                                 /* SysTick Handler*/
+
+                                                            /* External Interrupts*/
+    .long   DMA0_IRQHandler                                 /* DMA channel 0 transfer complete*/
+    .long   DMA1_IRQHandler                                 /* DMA channel 1 transfer complete*/
+    .long   DMA2_IRQHandler                                 /* DMA channel 2 transfer complete*/
+    .long   DMA3_IRQHandler                                 /* DMA channel 3 transfer complete*/
+    .long   Reserved20_IRQHandler                           /* Reserved interrupt*/
+    .long   FTFA_IRQHandler                                 /* Command complete and read collision*/
+    .long   LVD_LVW_IRQHandler                              /* Low-voltage detect, low-voltage warning*/
+    .long   LLWU_IRQHandler                                 /* Low leakage wakeup Unit*/
+    .long   I2C0_IRQHandler                                 /* I2C0 interrupt*/
+    .long   I2C1_IRQHandler                                 /* I2C1 interrupt*/
+    .long   SPI0_IRQHandler                                 /* SPI0 single interrupt vector for all sources*/
+    .long   SPI1_IRQHandler                                 /* SPI1 single interrupt vector for all sources*/
+    .long   UART0_IRQHandler                                /* UART0 status and error*/
+    .long   UART1_IRQHandler                                /* UART1 status and error*/
+    .long   UART2_IRQHandler                                /* UART2 status and error*/
+    .long   ADC0_IRQHandler                                 /* ADC0 interrupt*/
+    .long   CMP0_IRQHandler                                 /* CMP0 interrupt*/
+    .long   TPM0_IRQHandler                                 /* TPM0 single interrupt vector for all sources*/
+    .long   TPM1_IRQHandler                                 /* TPM1 single interrupt vector for all sources*/
+    .long   TPM2_IRQHandler                                 /* TPM2 single interrupt vector for all sources*/
+    .long   RTC_IRQHandler                                  /* RTC alarm*/
+    .long   RTC_Seconds_IRQHandler                          /* RTC seconds*/
+    .long   PIT_IRQHandler                                  /* PIT interrupt*/
+    .long   Reserved39_IRQHandler                           /* Reserved interrupt*/
+    .long   USB0_IRQHandler                                 /* USB0 interrupt*/
+    .long   DAC0_IRQHandler                                 /* DAC0 interrupt*/
+    .long   TSI0_IRQHandler                                 /* TSI0 interrupt*/
+    .long   MCG_IRQHandler                                  /* MCG interrupt*/
+    .long   LPTMR0_IRQHandler                               /* LPTMR0 interrupt*/
+    .long   Reserved45_IRQHandler                           /* Reserved interrupt*/
+    .long   PORTA_IRQHandler                                /* PORTA Pin detect*/
+    .long   PORTD_IRQHandler                                /* PORTD Pin detect*/
+
+    .size    __isr_vector, . - __isr_vector
+
+/* Flash Configuration */
+    .section .FlashConfig, "a"
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFF
+    .long 0xFFFFFFFE
+
+    .text
+    .thumb
+
+/* Reset Handler */
+
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    cpsid   i               /* Mask interrupts */
+    .equ    VTOR, 0xE000ED08
+    ldr     r0, =VTOR
+    ldr     r1, =__isr_vector
+    str     r1, [r0]
+    ldr     r2, [r1]
+    msr     msp, r2
+#ifndef __NO_SYSTEM_INIT
+    ldr   r0,=SystemInit
+    blx   r0
+#endif
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble     .LC0
+
+.LC1:
+    subs    r3, 4
+    ldr    r0, [r1,r3]
+    str    r0, [r2,r3]
+    bgt    .LC1
+.LC0:
+
+#ifdef __STARTUP_CLEAR_BSS
+/*     This part of work usually is done in C library startup code. Otherwise,
+ *     define this macro to enable it in this startup.
+ *
+ *     Loop to zero out BSS section, which uses following symbols
+ *     in linker script:
+ *      __bss_start__: start of BSS section. Must align to 4
+ *      __bss_end__: end of BSS section. Must align to 4
+ */
+    ldr r1, =__bss_start__
+    ldr r2, =__bss_end__
+
+    subs    r2, r1
+    ble .LC3
+
+    movs    r0, 0
+.LC2:
+    str r0, [r1, r2]
+    subs    r2, 4
+    bge .LC2
+.LC3:
+#endif
+    cpsie   i               /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+    ldr   r0,=__START
+    blx   r0
+#else
+    ldr   r0,=__libc_init_array
+    blx   r0
+    ldr   r0,=main
+    bx    r0
+#endif
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+
+    .align  1
+    .thumb_func
+    .weak DefaultISR
+    .type DefaultISR, %function
+DefaultISR:
+    ldr r0, =DefaultISR
+    bx r0
+    .size DefaultISR, . - DefaultISR
+
+    .align 1
+    .thumb_func
+    .weak NMI_Handler
+    .type NMI_Handler, %function
+NMI_Handler:
+    ldr   r0,=NMI_Handler
+    bx    r0
+    .size NMI_Handler, . - NMI_Handler
+
+    .align 1
+    .thumb_func
+    .weak HardFault_Handler
+    .type HardFault_Handler, %function
+HardFault_Handler:
+    ldr   r0,=HardFault_Handler
+    bx    r0
+    .size HardFault_Handler, . - HardFault_Handler
+
+    .align 1
+    .thumb_func
+    .weak SVC_Handler
+    .type SVC_Handler, %function
+SVC_Handler:
+    ldr   r0,=SVC_Handler
+    bx    r0
+    .size SVC_Handler, . - SVC_Handler
+
+    .align 1
+    .thumb_func
+    .weak PendSV_Handler
+    .type PendSV_Handler, %function
+PendSV_Handler:
+    ldr   r0,=PendSV_Handler
+    bx    r0
+    .size PendSV_Handler, . - PendSV_Handler
+
+    .align 1
+    .thumb_func
+    .weak SysTick_Handler
+    .type SysTick_Handler, %function
+SysTick_Handler:
+    ldr   r0,=SysTick_Handler
+    bx    r0
+    .size SysTick_Handler, . - SysTick_Handler
+
+    .align 1
+    .thumb_func
+    .weak DMA0_IRQHandler
+    .type DMA0_IRQHandler, %function
+DMA0_IRQHandler:
+    ldr   r0,=DMA0_DriverIRQHandler
+    bx    r0
+    .size DMA0_IRQHandler, . - DMA0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA1_IRQHandler
+    .type DMA1_IRQHandler, %function
+DMA1_IRQHandler:
+    ldr   r0,=DMA1_DriverIRQHandler
+    bx    r0
+    .size DMA1_IRQHandler, . - DMA1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA2_IRQHandler
+    .type DMA2_IRQHandler, %function
+DMA2_IRQHandler:
+    ldr   r0,=DMA2_DriverIRQHandler
+    bx    r0
+    .size DMA2_IRQHandler, . - DMA2_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak DMA3_IRQHandler
+    .type DMA3_IRQHandler, %function
+DMA3_IRQHandler:
+    ldr   r0,=DMA3_DriverIRQHandler
+    bx    r0
+    .size DMA3_IRQHandler, . - DMA3_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2C0_IRQHandler
+    .type I2C0_IRQHandler, %function
+I2C0_IRQHandler:
+    ldr   r0,=I2C0_DriverIRQHandler
+    bx    r0
+    .size I2C0_IRQHandler, . - I2C0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak I2C1_IRQHandler
+    .type I2C1_IRQHandler, %function
+I2C1_IRQHandler:
+    ldr   r0,=I2C1_DriverIRQHandler
+    bx    r0
+    .size I2C1_IRQHandler, . - I2C1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPI0_IRQHandler
+    .type SPI0_IRQHandler, %function
+SPI0_IRQHandler:
+    ldr   r0,=SPI0_DriverIRQHandler
+    bx    r0
+    .size SPI0_IRQHandler, . - SPI0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak SPI1_IRQHandler
+    .type SPI1_IRQHandler, %function
+SPI1_IRQHandler:
+    ldr   r0,=SPI1_DriverIRQHandler
+    bx    r0
+    .size SPI1_IRQHandler, . - SPI1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UART0_IRQHandler
+    .type UART0_IRQHandler, %function
+UART0_IRQHandler:
+    ldr   r0,=UART0_DriverIRQHandler
+    bx    r0
+    .size UART0_IRQHandler, . - UART0_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UART1_IRQHandler
+    .type UART1_IRQHandler, %function
+UART1_IRQHandler:
+    ldr   r0,=UART1_DriverIRQHandler
+    bx    r0
+    .size UART1_IRQHandler, . - UART1_IRQHandler
+
+    .align 1
+    .thumb_func
+    .weak UART2_IRQHandler
+    .type UART2_IRQHandler, %function
+UART2_IRQHandler:
+    ldr   r0,=UART2_DriverIRQHandler
+    bx    r0
+    .size UART2_IRQHandler, . - UART2_IRQHandler
+
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro def_irq_handler  handler_name
+    .weak \handler_name
+    .set  \handler_name, DefaultISR
+    .endm
+
+/* Exception Handlers */
+    def_irq_handler    DMA0_DriverIRQHandler
+    def_irq_handler    DMA1_DriverIRQHandler
+    def_irq_handler    DMA2_DriverIRQHandler
+    def_irq_handler    DMA3_DriverIRQHandler
+    def_irq_handler    Reserved20_IRQHandler
+    def_irq_handler    FTFA_IRQHandler
+    def_irq_handler    LVD_LVW_IRQHandler
+    def_irq_handler    LLWU_IRQHandler
+    def_irq_handler    I2C0_DriverIRQHandler
+    def_irq_handler    I2C1_DriverIRQHandler
+    def_irq_handler    SPI0_DriverIRQHandler
+    def_irq_handler    SPI1_DriverIRQHandler
+    def_irq_handler    UART0_DriverIRQHandler
+    def_irq_handler    UART1_DriverIRQHandler
+    def_irq_handler    UART2_DriverIRQHandler
+    def_irq_handler    ADC0_IRQHandler
+    def_irq_handler    CMP0_IRQHandler
+    def_irq_handler    TPM0_IRQHandler
+    def_irq_handler    TPM1_IRQHandler
+    def_irq_handler    TPM2_IRQHandler
+    def_irq_handler    RTC_IRQHandler
+    def_irq_handler    RTC_Seconds_IRQHandler
+    def_irq_handler    PIT_IRQHandler
+    def_irq_handler    Reserved39_IRQHandler
+    def_irq_handler    USB0_IRQHandler
+    def_irq_handler    DAC0_IRQHandler
+    def_irq_handler    TSI0_IRQHandler
+    def_irq_handler    MCG_IRQHandler
+    def_irq_handler    LPTMR0_IRQHandler
+    def_irq_handler    Reserved45_IRQHandler
+    def_irq_handler    PORTA_IRQHandler
+    def_irq_handler    PORTD_IRQHandler
+
+    .end
diff --git a/tools/get_deps.py b/tools/get_deps.py
index b4739e940..7e798cf9e 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -53,9 +53,6 @@ deps_optional = {
     'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
                             '950819b7de9b32f92c3edf396bc5ffb8d66e7009',
                             'kinetis_k32l lpc51 lpc54 lpc55 mcx imxrt'],
-    'hw/mcu/nxp/nxp_sdk': ['https://github.com/hathach/nxp_sdk.git',
-                           '845c8fc49b6fb660f06a5c45225494eacb06f00c',
-                           'kinetis_kl'],
     'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
                                          'c3715ce94b6f6391856de56081d4d9b3e98fa93d',
                                          'rp2040'],
diff --git a/tools/get_family_deps.py b/tools/get_family_deps.py
deleted file mode 100644
index 071d7b756..000000000
--- a/tools/get_family_deps.py
+++ /dev/null
@@ -1,21 +0,0 @@
-import sys
-import subprocess
-import os
-
-# TOP is tinyusb root dir
-TOP = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
-
-def get_family_dep(family):
-    for entry in os.scandir("{}/hw/bsp/{}/boards".format(TOP, family)):
-        if entry.is_dir():
-            result = subprocess.run("make -C {}/examples/device/board_test BOARD={} get-deps".format(TOP, entry.name),
-                                    shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-            print(result.stdout.decode("utf-8"))
-            return result.returncode
-
-
-status = 0
-for d in sys.argv[1:]:
-    status += get_family_dep(d)
-
-sys.exit(status)

From d70403f1f496f5853251f83392ffe80130255489 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Jun 2023 13:06:27 +0700
Subject: [PATCH 1809/2085] refactor khci to chipidea fs driver for device
 (host is not yet)

---
 .idea/cmake.xml                             |   3 +-
 .idea/runConfigurations/mcx947_jlink.xml    |   2 +-
 .idea/runConfigurations/rt1010_jlink.xml    |   2 +-
 .idea/runConfigurations/rt1060_jlink.xml    |   2 +-
 hw/bsp/kinetis_kl/family.cmake              |   2 +-
 hw/bsp/mcx/boards/mcxn947brk/board.cmake    |   8 +-
 hw/bsp/mcx/family.c                         |  27 +-
 hw/bsp/mcx/family.cmake                     |   4 +-
 hw/bsp/mcx/family.mk                        |  19 +-
 src/common/tusb_mcu.h                       |   6 +-
 src/portable/chipidea/ci_fs/ci_fs_kinetis.h |  51 ++
 src/portable/chipidea/ci_fs/ci_fs_mcx.h     |  47 ++
 src/portable/chipidea/ci_fs/ci_fs_type.h    | 118 +++++
 src/portable/chipidea/ci_fs/dcd_ci_fs.c     | 555 ++++++++++++++++++++
 14 files changed, 805 insertions(+), 41 deletions(-)
 create mode 100644 src/portable/chipidea/ci_fs/ci_fs_kinetis.h
 create mode 100644 src/portable/chipidea/ci_fs/ci_fs_mcx.h
 create mode 100644 src/portable/chipidea/ci_fs/ci_fs_type.h
 create mode 100644 src/portable/chipidea/ci_fs/dcd_ci_fs.c

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 3c016ccff..c9024715c 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,7 +2,7 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=mcx -DBOARD=mcxn947brk" />
+      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=mcx -DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095" />
       <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
@@ -37,6 +37,7 @@
       <configuration PROFILE_NAME="stm32g474nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=stm32g474nucleo" />
       <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=b_g474e_dpow1 -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="b_g474e_dpow1 iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=b_g474e_dpow1 -DTOOLCHAIN=iar" />
+      <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=kinetis_kl -DBOARD=frdm_kl25z -DLOG=3 -DLOGGER=RTT" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/mcx947_jlink.xml b/.idea/runConfigurations/mcx947_jlink.xml
index 71616ab70..27661bec5 100644
--- a/.idea/runConfigurations/mcx947_jlink.xml
+++ b/.idea/runConfigurations/mcx947_jlink.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="mcx947 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/mcx.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcxn947" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="mcx947 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/mcx.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/rt1010_jlink.xml b/.idea/runConfigurations/rt1010_jlink.xml
index e660a46ae..68ebb8885 100644
--- a/.idea/runConfigurations/rt1010_jlink.xml
+++ b/.idea/runConfigurations/rt1010_jlink.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1010 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="b_g474e_dpow1" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rt1010 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="frdm_kl25z" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/rt1060_jlink.xml b/.idea/runConfigurations/rt1060_jlink.xml
index b9a47a2ce..014a4d1b1 100644
--- a/.idea/runConfigurations/rt1060_jlink.xml
+++ b/.idea/runConfigurations/rt1060_jlink.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1060 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="b_g474e_dpow1" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rt1060 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake
index 77b932b8e..f491b3dee 100644
--- a/hw/bsp/kinetis_kl/family.cmake
+++ b/hw/bsp/kinetis_kl/family.cmake
@@ -88,7 +88,7 @@ function(family_configure_example TARGET)
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
     # TinyUSB Port
-    ${TOP}/src/portable/nxp/khci/dcd_khci.c
+    ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
     ${TOP}/src/portable/nxp/khci/hcd_khci.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.cmake b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
index 650f10967..8c3280743 100644
--- a/hw/bsp/mcx/boards/mcxn947brk/board.cmake
+++ b/hw/bsp/mcx/boards/mcxn947brk/board.cmake
@@ -5,12 +5,14 @@ set(JLINK_DEVICE MCXN947_M33_0)
 set(PYOCD_TARGET MCXN947)
 set(NXPLINK_DEVICE MCXN947:MCXN947)
 
+set(PORT 1)
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_MCXN947VDF_cm33_core0
-    # port 1 is highspeed
-    BOARD_TUD_RHPORT=1
-    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    BOARD_TUD_RHPORT=${PORT}
+    # port 0 is fullspeed, port 1 is highspeed
+    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
     )
   target_sources(${TARGET} PUBLIC
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
index 36d2f2d0a..4344ffc4e 100644
--- a/hw/bsp/mcx/family.c
+++ b/hw/bsp/mcx/family.c
@@ -66,6 +66,7 @@ void board_init(void)
 {
   BOARD_InitPins();
   BOARD_InitBootClocks();
+  CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
 
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
@@ -122,31 +123,13 @@ void board_init(void)
   // USB VBUS
   /* PORT0 PIN22 configured as USB0_VBUS */
 
-  CLOCK_SetupExtClocking(XTAL0_CLK_HZ);
-
 #if PORT_SUPPORT_DEVICE(0)
   // Port0 is Full Speed
 
-  /* Turn on USB0 Phy */
-  POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
-
-  /* reset the IP to make sure it's in reset state. */
-  RESET_PeripheralReset(kUSB0D_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn);
-  RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn);
-
-  // Enable USB Clock Adjustments to trim the FRO for the full speed controller
-  ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
-  CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
-  CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
-
-  /*According to reference manual, device mode setting has to be set by access usb host register */
-  CLOCK_EnableClock(kCLOCK_Usbhsl0);  // enable usb0 host clock
-  USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
-  CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
-
-  /* enable USB Device clock */
-  CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
+  CLOCK_AttachClk(kCLK_48M_to_USB0);
+  CLOCK_EnableClock(kCLOCK_Usb0Ram);
+  CLOCK_EnableClock(kCLOCK_Usb0Fs);
+  CLOCK_EnableUsbfsClock();
 #endif
 
 #if PORT_SUPPORT_DEVICE(1)
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 1c85b51f8..7c5feaecf 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -88,8 +88,8 @@ function(family_configure_example TARGET)
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
-    # TinyUSB Port
-    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+    ${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
index 2cd4c2448..2722c2038 100644
--- a/hw/bsp/mcx/family.mk
+++ b/hw/bsp/mcx/family.mk
@@ -16,21 +16,24 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_MCXN9 \
   -DBOARD_TUD_RHPORT=$(PORT) \
 
-ifeq ($(PORT), 1)
-  $(info "PORT1 High Speed")
-  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-else
-  $(info "PORT0 Full Speed")
-endif
-
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
 
 # All source paths should be relative to the top level.
 LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
 
+# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+ifeq ($(PORT), 1)
+  $(info "PORT1 High Speed")
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+	SRC_C += src/portable/chipidea/ci_hs/dcd_ci_hs.c
+else
+  $(info "PORT0 Full Speed")
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+  SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c
+endif
+
 SRC_C += \
-	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
 	$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index f89467e75..485d6168d 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -79,7 +79,11 @@
   #define TUP_RHPORT_HIGHSPEED    1
 
 #elif TU_CHECK_MCU(OPT_MCU_MCXN9)
-  // NOTE: MCXN943 port 1 use chipidea HS, port 0 use chipidea FS
+  // USB0 is chipidea FS
+  #define TUP_USBIP_CHIPIDEA_FS
+  #define TUP_USBIP_CHIPIDEA_FS_MCX
+
+  // USB1 is chipidea HS
   #define TUP_USBIP_CHIPIDEA_HS
   #define TUP_USBIP_EHCI
 
diff --git a/src/portable/chipidea/ci_fs/ci_fs_kinetis.h b/src/portable/chipidea/ci_fs/ci_fs_kinetis.h
new file mode 100644
index 000000000..cd21af1c7
--- /dev/null
+++ b/src/portable/chipidea/ci_fs/ci_fs_kinetis.h
@@ -0,0 +1,51 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_FS_KINETIS_H
+#define _CI_FS_KINETIS_H
+
+#include "fsl_device_registers.h"
+
+//static const ci_fs_controller_t _ci_controller[] = {
+//    {.reg_base = USB0_BASE, .irqnum = USB0_IRQn}
+//};
+
+#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USB0_BASE)
+#define CI_REG                  CI_FS_REG(0)
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USB0_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB0_IRQn);
+}
+
+#endif
diff --git a/src/portable/chipidea/ci_fs/ci_fs_mcx.h b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
new file mode 100644
index 000000000..3bfcd398e
--- /dev/null
+++ b/src/portable/chipidea/ci_fs/ci_fs_mcx.h
@@ -0,0 +1,47 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_FS_MCX_H
+#define _CI_FS_MCX_H
+
+#include "fsl_device_registers.h"
+
+#define CI_FS_REG(_port)        ((ci_fs_regs_t*) USBFS0_BASE)
+#define CI_REG                  CI_FS_REG(0)
+
+void dcd_int_enable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_EnableIRQ(USB0_FS_IRQn);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+  (void) rhport;
+  NVIC_DisableIRQ(USB0_FS_IRQn);
+}
+
+#endif
diff --git a/src/portable/chipidea/ci_fs/ci_fs_type.h b/src/portable/chipidea/ci_fs/ci_fs_type.h
new file mode 100644
index 000000000..5a5e53fb0
--- /dev/null
+++ b/src/portable/chipidea/ci_fs/ci_fs_type.h
@@ -0,0 +1,118 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _CI_FS_TYPE_H
+#define _CI_FS_TYPE_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// Note: some MCUs can only access these registers in 8-bit mode
+// align 4 is used to get rid of reserved fields
+#define _va32     volatile TU_ATTR_ALIGNED(4)
+
+typedef struct {
+  _va32 uint8_t PER_ID;                 // [00] Peripheral ID register
+  _va32 uint8_t ID_COMP;                // [04] Peripheral ID complement register
+  _va32 uint8_t REV;                    // [08] Peripheral revision register
+  _va32 uint8_t ADD_INFO;               // [0C] Peripheral additional info register
+  _va32 uint8_t OTG_ISTAT;              // [10] OTG Interrupt Status Register
+  _va32 uint8_t OTG_ICTRL;              // [14] OTG Interrupt Control Register
+  _va32 uint8_t OTG_STAT;               // [18] OTG Status Register
+  _va32 uint8_t OTG_CTRL;               // [1C] OTG Control register
+  uint32_t reserved_20[24];             // [20]
+  _va32 uint8_t INT_STAT;               // [80] Interrupt status register
+  _va32 uint8_t INT_EN;                 // [84] Interrupt enable register
+  _va32 uint8_t ERR_STAT;               // [88] Error interrupt status register
+  _va32 uint8_t ERR_ENB;                // [8C] Error interrupt enable register
+  _va32 uint8_t STAT;                   // [90] Status register
+  _va32 uint8_t CTL;                    // [94] Control register
+  _va32 uint8_t ADDR;                   // [98] Address register
+  _va32 uint8_t BDT_PAGE1;              // [9C] BDT page register 1
+  _va32 uint8_t FRM_NUML;               // [A0] Frame number register
+  _va32 uint8_t FRM_NUMH;               // [A4] Frame number register
+  _va32 uint8_t TOKEN;                  // [A8] Token register
+  _va32 uint8_t SOF_THLD;               // [AC] SOF threshold register
+  _va32 uint8_t BDT_PAGE2;              // [B0] BDT page register 2
+  _va32 uint8_t BDT_PAGE3;              // [B4] BDT page register 3
+
+  uint32_t reserved_b8;                 // [B8]
+  uint32_t reserved_bc;                 // [BC]
+
+  struct {
+    _va32 uint8_t CTL;
+  }EP[16];                              // [C0] Endpoint control register
+
+  //----- Following is only found available in NXP Kinetis
+  _va32 uint8_t USBCTRL;                // [100] USB Control register,
+  _va32 uint8_t OBSERVE;                // [104] USB OTG Observe register,
+  _va32 uint8_t CONTROL;                // [108] USB OTG Control register,
+  _va32 uint8_t USBTRC0;                // [10C] USB Transceiver Control Register 0,
+  uint32_t reserved_110;                // [110]
+  _va32 uint8_t USBFRMADJUST;           // [114] Frame Adjust Register,
+
+  //----- Following is only found available in NXP MCX
+  uint32_t reserved_118[3];             // [118]
+  _va32 uint8_t KEEP_ALIVE_CTRL;        // [124] Keep Alive Mode Control,
+  _va32 uint8_t KEEP_ALIVE_WKCTRL;      // [128] Keep Alive Mode Wakeup Control,
+  _va32 uint8_t MISCCTRL;               // [12C] Miscellaneous Control,
+  _va32 uint8_t STALL_IL_DIS;           // [130] Peripheral Mode Stall Disable for Endpoints[ 7..0] IN
+  _va32 uint8_t STALL_IH_DIS;           // [134] Peripheral Mode Stall Disable for Endpoints[15..8] IN
+  _va32 uint8_t STALL_OL_DIS;           // [138] Peripheral Mode Stall Disable for Endpoints[ 7..0] OUT
+  _va32 uint8_t STALL_OH_DIS;           // [13C] Peripheral Mode Stall Disable for Endpoints[15..8] OUT
+  _va32 uint8_t CLK_RECOVER_CTRL;       // [140] USB Clock Recovery Control,
+  _va32 uint8_t CLK_RECOVER_IRC_EN;     // [144] FIRC Oscillator Enable,
+  uint32_t reserved_148[3];             // [148]
+  _va32 uint8_t CLK_RECOVER_INT_EN;     // [154] Clock Recovery Combined Interrupt Enable,
+  uint32_t reserved_158;                // [158]
+  _va32 uint8_t CLK_RECOVER_INT_STATUS; // [15C] Clock Recovery Separated Interrupt Status,
+} ci_fs_regs_t;
+
+TU_VERIFY_STATIC(sizeof(ci_fs_regs_t) == 0x160, "Size is not correct");
+
+typedef struct
+{
+  uint32_t reg_base;
+  uint32_t irqnum;
+} ci_fs_controller_t;
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
new file mode 100644
index 000000000..37265df8b
--- /dev/null
+++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
@@ -0,0 +1,555 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Koji Kitayama
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_CHIPIDEA_FS)
+
+#include "device/dcd.h"
+#include "ci_fs_type.h"
+
+#if defined(TUP_USBIP_CHIPIDEA_FS_KINETIS)
+  #include "ci_fs_kinetis.h"
+#elif defined(TUP_USBIP_CHIPIDEA_FS_MCX)
+  #include "ci_fs_mcx.h"
+#else
+  #error "MCU is not supported"
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+enum {
+  TOK_PID_OUT   = 0x1u,
+  TOK_PID_IN    = 0x9u,
+  TOK_PID_SETUP = 0xDu,
+};
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t head;
+    struct {
+      union {
+        struct {
+               uint16_t           :  2;
+          __IO uint16_t tok_pid   :  4;
+               uint16_t data      :  1;
+          __IO uint16_t own       :  1;
+               uint16_t           :  8;
+        };
+        struct {
+               uint16_t           :  2;
+               uint16_t bdt_stall :  1;
+               uint16_t dts       :  1;
+               uint16_t ninc      :  1;
+               uint16_t keep      :  1;
+               uint16_t           : 10;
+        };
+      };
+      __IO uint16_t bc : 10;
+           uint16_t    :  6;
+    };
+  };
+  uint8_t *addr;
+}buffer_descriptor_t;
+
+TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
+
+typedef struct TU_ATTR_PACKED
+{
+  union {
+    uint32_t state;
+    struct {
+      uint32_t max_packet_size :11;
+      uint32_t                 : 5;
+      uint32_t odd             : 1;
+      uint32_t                 :15;
+    };
+  };
+  uint16_t length;
+  uint16_t remaining;
+}endpoint_state_t;
+
+TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
+
+typedef struct
+{
+  union {
+    /* [#EP][OUT,IN][EVEN,ODD] */
+    buffer_descriptor_t bdt[16][2][2];
+    uint16_t            bda[512];
+  };
+  TU_ATTR_ALIGNED(4) union {
+    endpoint_state_t endpoint[16][2];
+    endpoint_state_t endpoint_unified[16 * 2];
+  };
+  uint8_t setup_packet[8];
+  uint8_t addr;
+}dcd_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+// BDT(Buffer Descriptor Table) must be 256-byte aligned
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
+
+TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
+
+static void prepare_next_setup_packet(uint8_t rhport)
+{
+  const unsigned out_odd = _dcd.endpoint[0][0].odd;
+  const unsigned in_odd  = _dcd.endpoint[0][1].odd;
+  TU_ASSERT(0 == _dcd.bdt[0][0][out_odd].own, );
+
+  _dcd.bdt[0][0][out_odd].data     = 0;
+  _dcd.bdt[0][0][out_odd ^ 1].data = 1;
+  _dcd.bdt[0][1][in_odd].data      = 1;
+  _dcd.bdt[0][1][in_odd ^ 1].data  = 0;
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
+                _dcd.setup_packet, sizeof(_dcd.setup_packet));
+}
+
+static void process_stall(uint8_t rhport)
+{
+  for (int i = 0; i < 16; ++i) {
+    uint32_t const ep_ctl = CI_REG->EP[i].CTL;
+
+    if (ep_ctl & USB_ENDPT_EPSTALL_MASK) {
+      // prepare next setup if endpoint0
+      if ( i == 0 ) prepare_next_setup_packet(rhport);
+
+      // clear stall bit
+      CI_REG->EP[i].CTL = ep_ctl & ~USB_ENDPT_EPSTALL_MASK;
+    }
+  }
+}
+
+static void process_tokdne(uint8_t rhport)
+{
+  const unsigned s = CI_REG->STAT;
+  CI_REG->INT_STAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
+
+  uint8_t const epnum = (s >> USB_STAT_ENDP_SHIFT);
+  uint8_t const dir   = (s & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT;
+  unsigned const odd  = (s & USB_STAT_ODD_MASK) ? 1 : 0;
+
+  buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
+  endpoint_state_t    *ep = &_dcd.endpoint_unified[s >> 3];
+
+  /* fetch pid before discarded by the next steps */
+  const unsigned pid = bd->tok_pid;
+
+  /* reset values for a next transfer */
+  bd->bdt_stall = 0;
+  bd->dts       = 1;
+  bd->ninc      = 0;
+  bd->keep      = 0;
+  /* update the odd variable to prepare for the next transfer */
+  ep->odd       = odd ^ 1;
+  if (pid == TOK_PID_SETUP) {
+    dcd_event_setup_received(rhport, bd->addr, true);
+    CI_REG->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+    return;
+  }
+
+  const unsigned bc = bd->bc;
+  const unsigned remaining = ep->remaining - bc;
+  if (remaining && bc == ep->max_packet_size) {
+    /* continue the transferring consecutive data */
+    ep->remaining = remaining;
+    const int next_remaining = remaining - ep->max_packet_size;
+    if (next_remaining > 0) {
+      /* prepare to the after next transfer */
+      bd->addr += ep->max_packet_size * 2;
+      bd->bc    = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
+      __DSB();
+      bd->own   = 1; /* the own bit must set after addr */
+    }
+    return;
+  }
+  const unsigned length = ep->length;
+  dcd_event_xfer_complete(rhport,
+                          tu_edpt_addr(epnum, dir),
+                          length - remaining, XFER_RESULT_SUCCESS, true);
+  if (0 == epnum && 0 == length) {
+    /* After completion a ZLP of control transfer,
+     * it prepares for the next steup transfer. */
+    if (_dcd.addr) {
+      /* When the transfer was the SetAddress,
+       * the device address should be updated here. */
+      CI_REG->ADDR = _dcd.addr;
+      _dcd.addr  = 0;
+    }
+    prepare_next_setup_packet(rhport);
+  }
+}
+
+static void process_bus_reset(uint8_t rhport)
+{
+  CI_REG->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
+  CI_REG->CTL     |= USB_CTL_ODDRST_MASK;
+  CI_REG->ADDR     = 0;
+  CI_REG->INT_EN   = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | USB_INTEN_SLEEPEN_MASK |
+                     USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
+
+  CI_REG->EP[0].CTL = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
+  for (unsigned i = 1; i < 16; ++i) {
+    CI_REG->EP[i].CTL = 0;
+  }
+  buffer_descriptor_t *bd = _dcd.bdt[0][0];
+  for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
+    bd->head = 0;
+  }
+  const endpoint_state_t ep0 = {
+    .max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
+    .odd             = 0,
+    .length          = 0,
+    .remaining       = 0,
+  };
+  _dcd.endpoint[0][0] = ep0;
+  _dcd.endpoint[0][1] = ep0;
+  tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
+  _dcd.addr = 0;
+  prepare_next_setup_packet(rhport);
+  CI_REG->CTL &= ~USB_CTL_ODDRST_MASK;
+  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
+}
+
+static void process_bus_sleep(uint8_t rhport)
+{
+  // Enable resume & disable suspend interrupt
+  const unsigned inten = CI_REG->INT_EN;
+
+  CI_REG->INT_EN   = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
+  CI_REG->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK;
+  CI_REG->USBCTRL |= USB_USBCTRL_SUSP_MASK;
+
+  dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+}
+
+static void process_bus_resume(uint8_t rhport)
+{
+  // Enable suspend & disable resume interrupt
+  const unsigned inten = CI_REG->INT_EN;
+
+  CI_REG->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; // will also clear USB_USBTRC0_USB_RESUME_INT_MASK
+  CI_REG->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK;
+  CI_REG->INT_EN   = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
+
+  dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
+}
+
+/*------------------------------------------------------------------*/
+/* Device API
+ *------------------------------------------------------------------*/
+void dcd_init(uint8_t rhport)
+{
+  (void) rhport;
+
+  CI_REG->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
+  while (CI_REG->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
+
+  tu_memclr(&_dcd, sizeof(_dcd));
+  CI_REG->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
+  CI_REG->BDT_PAGE1 = (uint8_t)((uintptr_t)_dcd.bdt >> 8);
+  CI_REG->BDT_PAGE2 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
+  CI_REG->BDT_PAGE3 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
+
+  CI_REG->INT_EN = USB_INTEN_USBRSTEN_MASK;
+
+  dcd_connect(rhport);
+  // NVIC_ClearPendingIRQ(USB0_IRQn);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+  _dcd.addr = dev_addr & 0x7F;
+  /* Response with status first before changing device address */
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+  (void) rhport;
+
+  CI_REG->CTL |= USB_CTL_RESUME_MASK;
+
+  unsigned cnt = SystemCoreClock / 1000;
+  while (cnt--) __NOP();
+
+  CI_REG->CTL &= ~USB_CTL_RESUME_MASK;
+}
+
+void dcd_connect(uint8_t rhport)
+{
+  (void) rhport;
+  CI_REG->USBCTRL  = 0;
+  CI_REG->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
+  CI_REG->CTL     |= USB_CTL_USBENSOFEN_MASK;
+}
+
+void dcd_disconnect(uint8_t rhport)
+{
+  (void) rhport;
+  CI_REG->CTL      = 0;
+  CI_REG->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
+}
+
+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
+{
+  (void) rhport;
+
+  const unsigned ep_addr  = ep_desc->bEndpointAddress;
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  const unsigned xfer     = ep_desc->bmAttributes.xfer;
+  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
+  const unsigned odd      = ep->odd;
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+
+  /* No support for control transfer */
+  TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
+
+  ep->max_packet_size = tu_edpt_packet_size(ep_desc);
+  unsigned val = USB_ENDPT_EPCTLDIS_MASK;
+  val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
+  val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+  CI_REG->EP[epn].CTL |= val;
+
+  if (xfer != TUSB_XFER_ISOCHRONOUS) {
+    bd[odd].dts      = 1;
+    bd[odd].data     = 0;
+    bd[odd ^ 1].dts  = 1;
+    bd[odd ^ 1].data = 1;
+  }
+
+  return true;
+}
+
+void dcd_edpt_close_all(uint8_t rhport)
+{
+  dcd_int_disable(rhport);
+
+  for (unsigned i = 1; i < 16; ++i) {
+    CI_REG->EP[i].CTL = 0;
+  }
+
+  dcd_int_enable(rhport);
+
+  buffer_descriptor_t *bd = _dcd.bdt[1][0];
+  for (unsigned i = 2; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
+    bd->head = 0;
+  }
+
+  endpoint_state_t *ep = &_dcd.endpoint[1][0];
+  for (unsigned i = 2; i < sizeof(_dcd.endpoint)/sizeof(*ep); ++i, ++ep) {
+    /* Clear except the odd */
+    ep->max_packet_size = 0;
+    ep->length          = 0;
+    ep->remaining       = 0;
+  }
+}
+
+void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  endpoint_state_t *ep    = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+  const unsigned msk      = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
+
+  dcd_int_disable(rhport);
+
+  CI_REG->EP[epn].CTL &= ~msk;
+  ep->max_packet_size = 0;
+  ep->length          = 0;
+  ep->remaining       = 0;
+  bd[0].head          = 0;
+  bd[1].head          = 0;
+
+  dcd_int_enable(rhport);
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
+{
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  endpoint_state_t    *ep = &_dcd.endpoint[epn][dir];
+  buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
+  TU_ASSERT(0 == bd->own);
+
+  dcd_int_disable(rhport);
+
+  ep->length    = total_bytes;
+  ep->remaining = total_bytes;
+
+  const unsigned mps = ep->max_packet_size;
+  if (total_bytes > mps) {
+    buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
+    /* When total_bytes is greater than the max packet size,
+     * it prepares to the next transfer to avoid NAK in advance. */
+    next->bc   = total_bytes >= 2 * mps ? mps: total_bytes - mps;
+    next->addr = buffer + mps;
+    next->own  = 1;
+  }
+  bd->bc   = total_bytes >= mps ? mps: total_bytes;
+  bd->addr = buffer;
+  __DSB();
+  bd->own  = 1; /* This bit must be set last */
+
+  dcd_int_enable(rhport);
+
+  return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  (void) rhport;
+  const unsigned epn = tu_edpt_number(ep_addr);
+
+  if (0 == epn) {
+    CI_REG->EP[epn].CTL |=  USB_ENDPT_EPSTALL_MASK;
+  } else {
+    const unsigned dir      = tu_edpt_dir(ep_addr);
+    const unsigned odd      = _dcd.endpoint[epn][dir].odd;
+    buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][odd];
+    TU_ASSERT(0 == bd->own,);
+
+    dcd_int_disable(rhport);
+
+    bd->bdt_stall = 1;
+    __DSB();
+    bd->own       = 1; /* This bit must be set last */
+
+    dcd_int_enable(rhport);
+  }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+  const unsigned epn      = tu_edpt_number(ep_addr);
+  TU_VERIFY(epn,);
+  const unsigned dir      = tu_edpt_dir(ep_addr);
+  const unsigned odd      = _dcd.endpoint[epn][dir].odd;
+  buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
+  TU_VERIFY(bd[odd].own,);
+
+  dcd_int_disable(rhport);
+
+  bd[odd].own = 0;
+  __DSB();
+
+  // clear stall
+  bd[odd].bdt_stall  = 0;
+
+  // Reset data toggle
+  bd[odd    ].data = 0;
+  bd[odd ^ 1].data = 1;
+
+  // We already cleared this in ISR, but just clear it here to be safe
+  const uint32_t ep_ctl = CI_REG->EP[epn].CTL;
+  if (ep_ctl & USB_ENDPT_EPSTALL_MASK) {
+    CI_REG->EP[epn].CTL = ep_ctl & ~USB_ENDPT_EPSTALL_MASK;
+  }
+
+  dcd_int_enable(rhport);
+}
+
+//--------------------------------------------------------------------+
+// ISR
+//--------------------------------------------------------------------+
+void dcd_int_handler(uint8_t rhport)
+{
+  uint32_t is  = CI_REG->INT_STAT;
+  uint32_t msk = CI_REG->INT_EN;
+
+  // clear non-enabled interrupts
+  CI_REG->INT_STAT = is & ~msk;
+  is &= msk;
+
+  if (is & USB_ISTAT_ERROR_MASK) {
+    /* TODO: */
+    uint32_t es = CI_REG->ERR_STAT;
+    CI_REG->ERR_STAT = es;
+    CI_REG->INT_STAT = is; /* discard any pending events */
+  }
+
+  if (is & USB_ISTAT_USBRST_MASK) {
+    CI_REG->INT_STAT = is; /* discard any pending events */
+    process_bus_reset(rhport);
+  }
+
+  if (is & USB_ISTAT_SLEEP_MASK) {
+    // TU_LOG2("Suspend: "); TU_LOG2_HEX(is);
+
+    // Note Host usually has extra delay after bus reset (without SOF), which could falsely
+    // detected as Sleep event. Though usbd has debouncing logic so we are good
+    CI_REG->INT_STAT = USB_ISTAT_SLEEP_MASK;
+    process_bus_sleep(rhport);
+  }
+
+#if 0 // ISTAT_RESUME never trigger, probably for host mode ?
+  if (is & USB_ISTAT_RESUME_MASK) {
+    // TU_LOG2("ISTAT Resume: "); TU_LOG2_HEX(is);
+    KHCI->ISTAT = USB_ISTAT_RESUME_MASK;
+    process_bus_resume(rhport);
+  }
+#endif
+
+  if (CI_REG->USBTRC0 & USB_USBTRC0_USB_RESUME_INT_MASK) {
+     // TU_LOG2("USBTRC0 Resume: "); TU_LOG2_HEX(is); TU_LOG2_HEX(KHCI->USBTRC0);
+    process_bus_resume(rhport);
+  }
+
+  if (is & USB_ISTAT_SOFTOK_MASK) {
+    CI_REG->INT_STAT = USB_ISTAT_SOFTOK_MASK;
+    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
+  }
+
+  if (is & USB_ISTAT_STALL_MASK) {
+    CI_REG->INT_STAT = USB_ISTAT_STALL_MASK;
+    process_stall(rhport);
+  }
+
+  if (is & USB_ISTAT_TOKDNE_MASK) {
+    process_tokdne(rhport);
+  }
+}
+
+#endif

From 1a37777f59936cba0523bb4790ef657bbf17b870 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 15 Jun 2023 13:11:21 +0700
Subject: [PATCH 1810/2085] fix ci with win/mac

---
 .github/workflows/build_win_mac.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build_win_mac.yml b/.github/workflows/build_win_mac.yml
index 45fc62f78..cb879a705 100644
--- a/.github/workflows/build_win_mac.yml
+++ b/.github/workflows/build_win_mac.yml
@@ -48,7 +48,7 @@ jobs:
       uses: actions/checkout@v3
 
     - name: Get Dependencies
-      run: python3 tools/get_family_deps.py stm32f4
+      run: python3 tools/get_deps.py stm32f4
 
     - name: Build
       run: python3 tools/build_family.py stm32f4 stm32f411disco

From 96f7cd09dc2c8cd62afc5bb4b325ade45332e0ba Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Jun 2023 10:45:59 +0700
Subject: [PATCH 1811/2085] remove legacy transdimension driver

---
 .../transdimension/common_transdimension.h    | 136 ----
 .../nxp/transdimension/dcd_transdimension.c   | 672 ------------------
 .../nxp/transdimension/hcd_transdimension.c   | 119 ----
 3 files changed, 927 deletions(-)
 delete mode 100644 src/portable/nxp/transdimension/common_transdimension.h
 delete mode 100644 src/portable/nxp/transdimension/dcd_transdimension.c
 delete mode 100644 src/portable/nxp/transdimension/hcd_transdimension.c

diff --git a/src/portable/nxp/transdimension/common_transdimension.h b/src/portable/nxp/transdimension/common_transdimension.h
deleted file mode 100644
index 95ae1903e..000000000
--- a/src/portable/nxp/transdimension/common_transdimension.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2021, Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#ifndef COMMON_TRANSDIMENSION_H_
-#define COMMON_TRANSDIMENSION_H_
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// USBCMD
-enum {
-  USBCMD_RUN_STOP         = TU_BIT(0),
-  USBCMD_RESET            = TU_BIT(1),
-  USBCMD_SETUP_TRIPWIRE   = TU_BIT(13),
-  USBCMD_ADD_QTD_TRIPWIRE = TU_BIT(14)  ///< This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD
-// Interrupt Threshold bit 23:16
-};
-
-// PORTSC1
-#define PORTSC1_PORT_SPEED_POS    26
-
-enum {
-  PORTSC1_CURRENT_CONNECT_STATUS = TU_BIT(0),
-  PORTSC1_FORCE_PORT_RESUME      = TU_BIT(6),
-  PORTSC1_SUSPEND                = TU_BIT(7),
-  PORTSC1_FORCE_FULL_SPEED       = TU_BIT(24),
-  PORTSC1_PORT_SPEED             = TU_BIT(26) | TU_BIT(27)
-};
-
-// OTGSC
-enum {
-  OTGSC_VBUS_DISCHARGE          = TU_BIT(0),
-  OTGSC_VBUS_CHARGE             = TU_BIT(1),
-//  OTGSC_HWASSIST_AUTORESET    = TU_BIT(2),
-  OTGSC_OTG_TERMINATION         = TU_BIT(3), ///< Must set to 1 when OTG go to device mode
-  OTGSC_DATA_PULSING            = TU_BIT(4),
-  OTGSC_ID_PULLUP               = TU_BIT(5),
-//  OTGSC_HWASSIT_DATA_PULSE    = TU_BIT(6),
-//  OTGSC_HWASSIT_BDIS_ACONN    = TU_BIT(7),
-  OTGSC_ID                      = TU_BIT(8), ///< 0 = A device, 1 = B Device
-  OTGSC_A_VBUS_VALID            = TU_BIT(9),
-  OTGSC_A_SESSION_VALID         = TU_BIT(10),
-  OTGSC_B_SESSION_VALID         = TU_BIT(11),
-  OTGSC_B_SESSION_END           = TU_BIT(12),
-  OTGSC_1MS_TOGGLE              = TU_BIT(13),
-  OTGSC_DATA_BUS_PULSING_STATUS = TU_BIT(14),
-};
-
-// USBMode
-enum {
-  USBMODE_CM_DEVICE = 2,
-  USBMODE_CM_HOST   = 3,
-
-  USBMODE_SLOM = TU_BIT(3),
-  USBMODE_SDIS = TU_BIT(4),
-
-  USBMODE_VBUS_POWER_SELECT = TU_BIT(5), // Need to be enabled for LPC18XX/43XX in host mode
-};
-
-// Device Registers
-typedef struct
-{
-  //------------- ID + HW Parameter Registers-------------//
-  __I  uint32_t TU_RESERVED[64]; ///< For iMX RT10xx, but not used by LPC18XX/LPC43XX
-
-  //------------- Capability Registers-------------//
-  __I  uint8_t  CAPLENGTH;       ///< Capability Registers Length
-  __I  uint8_t  TU_RESERVED[1];
-  __I  uint16_t HCIVERSION;      ///< Host Controller Interface Version
-
-  __I  uint32_t HCSPARAMS;       ///< Host Controller Structural Parameters
-  __I  uint32_t HCCPARAMS;       ///< Host Controller Capability Parameters
-  __I  uint32_t TU_RESERVED[5];
-
-  __I  uint16_t DCIVERSION;      ///< Device Controller Interface Version
-  __I  uint8_t  TU_RESERVED[2];
-
-  __I  uint32_t DCCPARAMS;       ///< Device Controller Capability Parameters
-  __I  uint32_t TU_RESERVED[6];
-
-  //------------- Operational Registers -------------//
-  __IO uint32_t USBCMD;          ///< USB Command Register
-  __IO uint32_t USBSTS;          ///< USB Status Register
-  __IO uint32_t USBINTR;         ///< Interrupt Enable Register
-  __IO uint32_t FRINDEX;         ///< USB Frame Index
-  __I  uint32_t TU_RESERVED;
-  __IO uint32_t DEVICEADDR;      ///< Device Address
-  __IO uint32_t ENDPTLISTADDR;   ///< Endpoint List Address
-  __I  uint32_t TU_RESERVED;
-  __IO uint32_t BURSTSIZE;       ///< Programmable Burst Size
-  __IO uint32_t TXFILLTUNING;    ///< TX FIFO Fill Tuning
-       uint32_t TU_RESERVED[4];
-  __IO uint32_t ENDPTNAK;        ///< Endpoint NAK
-  __IO uint32_t ENDPTNAKEN;      ///< Endpoint NAK Enable
-  __I  uint32_t TU_RESERVED;
-  __IO uint32_t PORTSC1;         ///< Port Status & Control
-  __I  uint32_t TU_RESERVED[7];
-  __IO uint32_t OTGSC;           ///< On-The-Go Status & control
-  __IO uint32_t USBMODE;         ///< USB Device Mode
-  __IO uint32_t ENDPTSETUPSTAT;  ///< Endpoint Setup Status
-  __IO uint32_t ENDPTPRIME;      ///< Endpoint Prime
-  __IO uint32_t ENDPTFLUSH;      ///< Endpoint Flush
-  __I  uint32_t ENDPTSTAT;       ///< Endpoint Status
-  __IO uint32_t ENDPTCOMPLETE;   ///< Endpoint Complete
-  __IO uint32_t ENDPTCTRL[8];    ///< Endpoint Control 0 - 7
-} dcd_registers_t, hcd_registers_t;
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* COMMON_TRANSDIMENSION_H_ */
diff --git a/src/portable/nxp/transdimension/dcd_transdimension.c b/src/portable/nxp/transdimension/dcd_transdimension.c
deleted file mode 100644
index 983d7cfcf..000000000
--- a/src/portable/nxp/transdimension/dcd_transdimension.c
+++ /dev/null
@@ -1,672 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-#if CFG_TUD_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT)
-
-#warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly"
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
-  #include "fsl_device_registers.h"
-  #define INCLUDE_FSL_DEVICE_REGISTERS
-#else
-  // LPCOpen for 18xx & 43xx
-  #include "chip.h"
-#endif
-
-#include "common/tusb_common.h"
-#include "device/dcd.h"
-#include "common_transdimension.h"
-
-#if defined(__CORTEX_M) && __CORTEX_M == 7 && __DCACHE_PRESENT == 1
-  #define CleanInvalidateDCache_by_Addr   SCB_CleanInvalidateDCache_by_Addr
-#else
-  #define CleanInvalidateDCache_by_Addr(_addr, _dsize)
-#endif
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-// ENDPTCTRL
-enum {
-  ENDPTCTRL_STALL          = TU_BIT(0),
-  ENDPTCTRL_TOGGLE_INHIBIT = TU_BIT(5), // used for test only
-  ENDPTCTRL_TOGGLE_RESET   = TU_BIT(6),
-  ENDPTCTRL_ENABLE         = TU_BIT(7)
-};
-
-enum {
-  ENDPTCTRL_TYPE_POS  = 2, // Endpoint type is 2-bit field
-};
-
-// USBSTS, USBINTR
-enum {
-  INTR_USB         = TU_BIT(0),
-  INTR_ERROR       = TU_BIT(1),
-  INTR_PORT_CHANGE = TU_BIT(2),
-  INTR_RESET       = TU_BIT(6),
-  INTR_SOF         = TU_BIT(7),
-  INTR_SUSPEND     = TU_BIT(8),
-  INTR_NAK         = TU_BIT(16)
-};
-
-// Queue Transfer Descriptor
-typedef struct
-{
-  // Word 0: Next QTD Pointer
-  uint32_t next; ///< Next link pointer This field contains the physical memory address of the next dTD to be processed
-
-  // Word 1: qTQ Token
-  uint32_t                      : 3  ;
-  volatile uint32_t xact_err    : 1  ;
-  uint32_t                      : 1  ;
-  volatile uint32_t buffer_err  : 1  ;
-  volatile uint32_t halted      : 1  ;
-  volatile uint32_t active      : 1  ;
-  uint32_t                      : 2  ;
-  uint32_t iso_mult_override    : 2  ; ///< This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO.
-  uint32_t                      : 3  ;
-  uint32_t int_on_complete      : 1  ;
-  volatile uint32_t total_bytes : 15 ;
-  uint32_t                      : 1  ;
-
-  // Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page
-  uint32_t buffer[5]; ///< buffer1 has frame_n for TODO Isochronous
-
-  //--------------------------------------------------------------------+
-  // TD is 32 bytes aligned but occupies only 28 bytes
-  // Therefore there are 4 bytes padding that we can use.
-  //--------------------------------------------------------------------+
-  uint16_t expected_bytes;
-  uint8_t reserved[2];
-} dcd_qtd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
-
-// Queue Head
-typedef struct
-{
-  // Word 0: Capabilities and Characteristics
-  uint32_t                         : 15 ; ///< Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed.
-  uint32_t int_on_setup            : 1  ; ///< Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received.
-  uint32_t max_packet_size         : 11 ; ///< Endpoint's wMaxPacketSize
-  uint32_t                         : 2  ;
-  uint32_t zero_length_termination : 1  ; ///< This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple�. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length.
-  uint32_t iso_mult                : 2  ; ///<
-
-  // Word 1: Current qTD Pointer
-  volatile uint32_t qtd_addr;
-
-  // Word 2-9: Transfer Overlay
-  volatile dcd_qtd_t qtd_overlay;
-
-  // Word 10-11: Setup request (control OUT only)
-  volatile tusb_control_request_t setup_request;
-
-  //--------------------------------------------------------------------+
-  // QHD is 64 bytes aligned but occupies only 48 bytes
-  // Therefore there are 16 bytes padding that we can use.
-  //--------------------------------------------------------------------+
-  tu_fifo_t * ff;
-  uint8_t reserved[12];
-} dcd_qhd_t;
-
-TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
-
-//--------------------------------------------------------------------+
-// Variables
-//--------------------------------------------------------------------+
-
-typedef struct
-{
-  dcd_registers_t* regs;  // registers
-  const IRQn_Type irqnum; // IRQ number
-  const uint8_t ep_count; // Max bi-directional Endpoints
-}dcd_controller_t;
-
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
-  static const dcd_controller_t _dcd_controller[] =
-  {
-    // RT1010 and RT1020 only has 1 USB controller
-    #if FSL_FEATURE_SOC_USBHS_COUNT == 1
-      { .regs = (dcd_registers_t*) USB_BASE , .irqnum = USB_OTG1_IRQn, .ep_count = 8 }
-    #else
-      { .regs = (dcd_registers_t*) USB1_BASE, .irqnum = USB_OTG1_IRQn, .ep_count = 8 },
-      { .regs = (dcd_registers_t*) USB2_BASE, .irqnum = USB_OTG2_IRQn, .ep_count = 8 }
-    #endif
-  };
-
-#else
-  static const dcd_controller_t _dcd_controller[] =
-  {
-    { .regs = (dcd_registers_t*) LPC_USB0_BASE, .irqnum = USB0_IRQn, .ep_count = 6 },
-    { .regs = (dcd_registers_t*) LPC_USB1_BASE, .irqnum = USB1_IRQn, .ep_count = 4 }
-  };
-#endif
-
-#define QTD_NEXT_INVALID 0x01
-
-typedef struct {
-  // Must be at 2K alignment
-  // Each endpoint with direction (IN/OUT) occupies a queue head
-  // for portability, TinyUSB only queue 1 TD for each Qhd
-  dcd_qhd_t qhd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(64);
-  dcd_qtd_t qtd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
-}dcd_data_t;
-
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
-static dcd_data_t _dcd_data;
-
-//--------------------------------------------------------------------+
-// Controller API
-//--------------------------------------------------------------------+
-
-/// follows LPC43xx User Manual 23.10.3
-static void bus_reset(uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  // The reset value for all endpoint types is the control endpoint. If one endpoint
-  // direction is enabled and the paired endpoint of opposite direction is disabled, then the
-  // endpoint type of the unused direction must be changed from the control type to any other
-  // type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior
-  // for the data PID tracking on the active endpoint.
-  for( uint8_t i=1; i < _dcd_controller[rhport].ep_count; i++)
-  {
-    dcd_reg->ENDPTCTRL[i] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
-  }
-
-  //------------- Clear All Registers -------------//
-  dcd_reg->ENDPTNAK       = dcd_reg->ENDPTNAK;
-  dcd_reg->ENDPTNAKEN     = 0;
-  dcd_reg->USBSTS         = dcd_reg->USBSTS;
-  dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
-  dcd_reg->ENDPTCOMPLETE  = dcd_reg->ENDPTCOMPLETE;
-
-  while (dcd_reg->ENDPTPRIME) {}
-  dcd_reg->ENDPTFLUSH = 0xFFFFFFFF;
-  while (dcd_reg->ENDPTFLUSH) {}
-
-  // read reset bit in portsc
-
-  //------------- Queue Head & Queue TD -------------//
-  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
-
-  //------------- Set up Control Endpoints (0 OUT, 1 IN) -------------//
-  _dcd_data.qhd[0][0].zero_length_termination = _dcd_data.qhd[0][1].zero_length_termination = 1;
-  _dcd_data.qhd[0][0].max_packet_size  = _dcd_data.qhd[0][1].max_packet_size  = CFG_TUD_ENDPOINT0_SIZE;
-  _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID;
-
-  _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only
-}
-
-void dcd_init(uint8_t rhport)
-{
-  tu_memclr(&_dcd_data, sizeof(dcd_data_t));
-
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  // Reset controller
-  dcd_reg->USBCMD |= USBCMD_RESET;
-  while( dcd_reg->USBCMD & USBCMD_RESET ) {}
-
-  // Set mode to device, must be set immediately after reset
-  dcd_reg->USBMODE = USBMODE_CM_DEVICE;
-  dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION;
-
-#if !TUD_OPT_HIGH_SPEED
-  dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED;
-#endif
-
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
-  dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment
-  dcd_reg->USBSTS  = dcd_reg->USBSTS;
-  dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND;
-
-  dcd_reg->USBCMD &= ~0x00FF0000;     // Interrupt Threshold Interval = 0
-  dcd_reg->USBCMD |= USBCMD_RUN_STOP; // Connect
-}
-
-void dcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(_dcd_controller[rhport].irqnum);
-}
-
-void dcd_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(_dcd_controller[rhport].irqnum);
-}
-
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  // Response with status first before changing device address
-  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
-
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->DEVICEADDR = (dev_addr << 25) | TU_BIT(24);
-}
-
-void dcd_remote_wakeup(uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->PORTSC1 |= PORTSC1_FORCE_PORT_RESUME;
-}
-
-void dcd_connect(uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->USBCMD |= USBCMD_RUN_STOP;
-}
-
-void dcd_disconnect(uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->USBCMD &= ~USBCMD_RUN_STOP;
-}
-
-void dcd_sof_enable(uint8_t rhport, bool en)
-{
-  (void) rhport;
-  (void) en;
-
-  // TODO implement later
-}
-
-//--------------------------------------------------------------------+
-// HELPER
-//--------------------------------------------------------------------+
-
-static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
-{
-  // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the
-  // address to 32-byte boundaries. Buffer must be word aligned
-  CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31);
-
-  tu_memclr(p_qtd, sizeof(dcd_qtd_t));
-
-  p_qtd->next            = QTD_NEXT_INVALID;
-  p_qtd->active          = 1;
-  p_qtd->total_bytes     = p_qtd->expected_bytes = total_bytes;
-  p_qtd->int_on_complete = true;
-
-  if (data_ptr != NULL)
-  {
-    p_qtd->buffer[0] = (uint32_t) data_ptr;
-
-    uint32_t const bufend = p_qtd->buffer[0] + total_bytes;
-    for(uint8_t i=1; i<5; i++)
-    {
-      uint32_t const next_page = tu_align4k( p_qtd->buffer[i-1] ) + 4096;
-      if ( bufend <= next_page ) break;
-
-      p_qtd->buffer[i] = next_page;
-
-      // TODO page[1] FRAME_N for ISO transfer
-    }
-  }
-}
-
-//--------------------------------------------------------------------+
-// DCD Endpoint Port
-//--------------------------------------------------------------------+
-void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
-
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0);
-
-  // flush to abort any primed buffer
-  dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
-}
-
-void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  // data toggle also need to be reset
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << ( dir ? 16 : 0 );
-  dcd_reg->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << ( dir  ? 16 : 0));
-}
-
-bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
-{
-  uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
-  uint8_t const dir   = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
-
-  // Must not exceed max endpoint number
-  TU_ASSERT( epnum < _dcd_controller[rhport].ep_count );
-
-  //------------- Prepare Queue Head -------------//
-  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
-  tu_memclr(p_qhd, sizeof(dcd_qhd_t));
-
-  p_qhd->zero_length_termination = 1;
-  p_qhd->max_packet_size         = tu_edpt_packet_size(p_endpoint_desc);
-  if (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
-  {
-    p_qhd->iso_mult = 1;
-  }
-
-  p_qhd->qtd_overlay.next        = QTD_NEXT_INVALID;
-
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
-  // Enable EP Control
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET;
-
-  if ( dir == TUSB_DIR_OUT )
-  {
-    dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0xFFFF0000u) | epctrl;
-  }else
-  {
-    dcd_reg->ENDPTCTRL[epnum] = (dcd_reg->ENDPTCTRL[epnum] & 0x0000FFFFu) | (epctrl << 16);
-  }
-
-  return true;
-}
-
-void dcd_edpt_close_all (uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  // Disable all non-control endpoints
-  for( uint8_t epnum=1; epnum < _dcd_controller[rhport].ep_count; epnum++)
-  {
-    _dcd_data.qhd[epnum][TUSB_DIR_OUT].qtd_overlay.halted = 1;
-    _dcd_data.qhd[epnum][TUSB_DIR_IN ].qtd_overlay.halted = 1;
-
-    dcd_reg->ENDPTFLUSH = TU_BIT(epnum) |  TU_BIT(epnum+16);
-    dcd_reg->ENDPTCTRL[epnum] = (TUSB_XFER_BULK << ENDPTCTRL_TYPE_POS) | (TUSB_XFER_BULK << (16+ENDPTCTRL_TYPE_POS));
-  }
-}
-
-void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
-{
-  uint8_t const epnum  = tu_edpt_number(ep_addr);
-  uint8_t const dir    = tu_edpt_dir(ep_addr);
-
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  _dcd_data.qhd[epnum][dir].qtd_overlay.halted = 1;
-
-  // Flush EP
-  uint32_t const flush_mask = TU_BIT(epnum + (dir ? 16 : 0));
-  dcd_reg->ENDPTFLUSH = flush_mask;
-  while(dcd_reg->ENDPTFLUSH & flush_mask);
-
-  // Clear EP enable
-  dcd_reg->ENDPTCTRL[epnum] &=~(ENDPTCTRL_ENABLE << (dir ? 16 : 0));
-}
-
-static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
-  dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
-
-  p_qhd->qtd_overlay.halted = false;            // clear any previous error
-  p_qhd->qtd_overlay.next   = (uint32_t) p_qtd; // link qtd to qhd
-
-  // flush cache
-  CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
-  if ( epnum == 0 )
-  {
-    // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
-    // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
-    while(dcd_reg->ENDPTSETUPSTAT & TU_BIT(0)) {}
-  }
-
-  // start transfer
-  dcd_reg->ENDPTPRIME = TU_BIT(epnum + (dir ? 16 : 0));
-}
-
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  dcd_qhd_t* p_qhd = &_dcd_data.qhd[epnum][dir];
-  dcd_qtd_t* p_qtd = &_dcd_data.qtd[epnum][dir];
-
-  // Prepare qtd
-  qtd_init(p_qtd, buffer, total_bytes);
-
-  // Start qhd transfer
-  p_qhd->ff = NULL;
-  qhd_start_xfer(rhport, epnum, dir);
-
-  return true;
-}
-
-// fifo has to be aligned to 4k boundary
-bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
-  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
-  dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
-
-  tu_fifo_buffer_info_t fifo_info;
-
-  if (dir)
-  {
-    tu_fifo_get_read_info(ff, &fifo_info);
-  } else
-  {
-    tu_fifo_get_write_info(ff, &fifo_info);
-  }
-
-  if ( fifo_info.len_lin >= total_bytes )
-  {
-    // Linear length is enough for this transfer
-    qtd_init(p_qtd, fifo_info.ptr_lin, total_bytes);
-  }
-  else
-  {
-    // linear part is not enough
-
-    // prepare TD up to linear length
-    qtd_init(p_qtd, fifo_info.ptr_lin, fifo_info.len_lin);
-
-    if ( !tu_offset4k((uint32_t) fifo_info.ptr_wrap) && !tu_offset4k(tu_fifo_depth(ff)) )
-    {
-      // If buffer is aligned to 4K & buffer size is multiple of 4K
-      // We can make use of buffer page array to also combine the linear + wrapped length
-      p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes;
-
-      for(uint8_t i = 1, page = 0; i < 5; i++)
-      {
-        // pick up buffer array where linear ends
-        if (p_qtd->buffer[i] == 0)
-        {
-          p_qtd->buffer[i] = (uint32_t) fifo_info.ptr_wrap + 4096 * page;
-          page++;
-        }
-      }
-
-      CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31);
-    }
-    else
-    {
-      // TODO we may need to carry the wrapped length after the linear part complete
-      // for now only transfer up to linear part
-    }
-  }
-
-  // Start qhd transfer
-  p_qhd->ff = ff;
-  qhd_start_xfer(rhport, epnum, dir);
-
-  return true;
-}
-
-//--------------------------------------------------------------------+
-// ISR
-//--------------------------------------------------------------------+
-
-static void process_edpt_complete_isr(uint8_t rhport, uint8_t epnum, uint8_t dir)
-{
-  dcd_qhd_t * p_qhd = &_dcd_data.qhd[epnum][dir];
-  dcd_qtd_t * p_qtd = &_dcd_data.qtd[epnum][dir];
-
-  uint8_t result = p_qtd->halted ? XFER_RESULT_STALLED :
-      ( p_qtd->xact_err || p_qtd->buffer_err ) ? XFER_RESULT_FAILED : XFER_RESULT_SUCCESS;
-
-  if ( result != XFER_RESULT_SUCCESS )
-  {
-    dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-    // flush to abort error buffer
-    dcd_reg->ENDPTFLUSH = TU_BIT(epnum + (dir ? 16 : 0));
-  }
-
-  uint16_t const xferred_bytes = p_qtd->expected_bytes - p_qtd->total_bytes;
-
-  if (p_qhd->ff)
-  {
-    if (dir == TUSB_DIR_IN)
-    {
-      tu_fifo_advance_read_pointer(p_qhd->ff, xferred_bytes);
-    } else
-    {
-      tu_fifo_advance_write_pointer(p_qhd->ff, xferred_bytes);
-    }
-  }
-
-  // only number of bytes in the IOC qtd
-  dcd_event_xfer_complete(rhport, tu_edpt_addr(epnum, dir), xferred_bytes, result, true);
-}
-
-void dcd_int_handler(uint8_t rhport)
-{
-  dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-
-  uint32_t const int_enable = dcd_reg->USBINTR;
-  uint32_t const int_status = dcd_reg->USBSTS & int_enable;
-  dcd_reg->USBSTS = int_status; // Acknowledge handled interrupt
-
-  // disabled interrupt sources
-  if (int_status == 0) return;
-
-  // Set if the port controller enters the full or high-speed operational state.
-  // either from Bus Reset or Suspended state
-	if (int_status & INTR_PORT_CHANGE)
-	{
-	  // TU_LOG2("PortChange %08lx\r\n", dcd_reg->PORTSC1);
-
-	  // Reset interrupt is not enabled, we manually check if Port Change is due
-	  // to connection / disconnection
-	  if ( dcd_reg->USBSTS & INTR_RESET )
-	  {
-	    dcd_reg->USBSTS = INTR_RESET;
-
-	    if (dcd_reg->PORTSC1 & PORTSC1_CURRENT_CONNECT_STATUS)
-	    {
-	      uint32_t const speed = (dcd_reg->PORTSC1 & PORTSC1_PORT_SPEED) >> PORTSC1_PORT_SPEED_POS;
-	      bus_reset(rhport);
-	      dcd_event_bus_reset(rhport, (tusb_speed_t) speed, true);
-	    }else
-	    {
-	      dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
-	    }
-	  }
-	  else
-	  {
-	    // Triggered by resuming from suspended state
-	    if ( !(dcd_reg->PORTSC1 & PORTSC1_SUSPEND) )
-	    {
-	      dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-	    }
-	  }
-	}
-
-  if (int_status & INTR_SUSPEND)
-  {
-    // TU_LOG2("Suspend %08lx\r\n", dcd_reg->PORTSC1);
-
-    if (dcd_reg->PORTSC1 & PORTSC1_SUSPEND)
-    {
-      // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-      // Skip suspend event if we are not addressed
-      if ((dcd_reg->DEVICEADDR >> 25) & 0x0f)
-      {
-        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-      }
-    }
-  }
-
-  if (int_status & INTR_USB)
-  {
-    // Make sure we read the latest version of _dcd_data.
-    CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd_data, sizeof(dcd_data_t));
-
-    uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE;
-    dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge
-
-    if (dcd_reg->ENDPTSETUPSTAT)
-    {
-      //------------- Set up Received -------------//
-      // 23.10.10.2 Operational model for setup transfers
-      dcd_reg->ENDPTSETUPSTAT = dcd_reg->ENDPTSETUPSTAT;
-
-      dcd_event_setup_received(rhport, (uint8_t*)(uintptr_t) &_dcd_data.qhd[0][0].setup_request, true);
-    }
-
-    // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
-    // nothing to do, we will submit xfer as error to usbd
-    // if (int_status & INTR_ERROR) { }
-
-    if ( edpt_complete )
-    {
-      for(uint8_t epnum = 0; epnum < TUP_DCD_ENDPOINT_MAX; epnum++)
-      {
-        if ( tu_bit_test(edpt_complete, epnum)    ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_OUT);
-        if ( tu_bit_test(edpt_complete, epnum+16) ) process_edpt_complete_isr(rhport, epnum, TUSB_DIR_IN);
-      }
-    }
-  }
-
-  if (int_status & INTR_SOF)
-  {
-    dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
-  }
-}
-
-#endif
diff --git a/src/portable/nxp/transdimension/hcd_transdimension.c b/src/portable/nxp/transdimension/hcd_transdimension.c
deleted file mode 100644
index 0b3e9e4ef..000000000
--- a/src/portable/nxp/transdimension/hcd_transdimension.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include "tusb_option.h"
-
-// NXP Trans-Dimension USB IP implement EHCI for host functionality
-
-#if CFG_TUH_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT)
-
-#warning "transdimenion is renamed to chipidea (portable/chipidea/ci_hs) to match other opensource naming convention such as linux. This file will be removed in the future, please update your makefile accordingly"
-
-//--------------------------------------------------------------------+
-// INCLUDE
-//--------------------------------------------------------------------+
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
-  #include "fsl_device_registers.h"
-#else
-  // LPCOpen for 18xx & 43xx
-  #include "chip.h"
-#endif
-
-#include "common/tusb_common.h"
-#include "common_transdimension.h"
-#include "portable/ehci/ehci_api.h"
-
-//--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF
-//--------------------------------------------------------------------+
-
-// TODO can be merged with dcd_controller_t
-typedef struct
-{
-  uint32_t regs_base;     // registers base
-  const IRQn_Type irqnum; // IRQ number
-}hcd_controller_t;
-
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
-  static const hcd_controller_t _hcd_controller[] =
-  {
-    // RT1010 and RT1020 only has 1 USB controller
-    #if FSL_FEATURE_SOC_USBHS_COUNT == 1
-      { .regs_base = USB_BASE , .irqnum = USB_OTG1_IRQn }
-    #else
-      { .regs_base = USB1_BASE, .irqnum = USB_OTG1_IRQn },
-      { .regs_base = USB2_BASE, .irqnum = USB_OTG2_IRQn }
-    #endif
-  };
-
-#else
-  static const hcd_controller_t _hcd_controller[] =
-  {
-    { .regs_base = LPC_USB0_BASE, .irqnum = USB0_IRQn },
-    { .regs_base = LPC_USB1_BASE, .irqnum = USB1_IRQn }
-  };
-#endif
-
-//--------------------------------------------------------------------+
-// Controller API
-//--------------------------------------------------------------------+
-
-bool hcd_init(uint8_t rhport)
-{
-  hcd_registers_t* hcd_reg = (hcd_registers_t*) _hcd_controller[rhport].regs_base;
-
-  // Reset controller
-  hcd_reg->USBCMD |= USBCMD_RESET;
-  while( hcd_reg->USBCMD & USBCMD_RESET ) {}
-
-  // Set mode to device, must be set immediately after reset
-#if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
-  // LPC18XX/43XX need to set VBUS Power Select to HIGH
-  // RHPORT1 is fullspeed only (need external PHY for Highspeed)
-  hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
-  if (rhport == 1) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
-#else
-  hcd_reg->USBMODE = USBMODE_CM_HOST;
-#endif
-
-  // FIXME force full speed, still have issue with Highspeed enumeration
-  hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
-
-  return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD);
-}
-
-void hcd_int_enable(uint8_t rhport)
-{
-  NVIC_EnableIRQ(_hcd_controller[rhport].irqnum);
-}
-
-void hcd_int_disable(uint8_t rhport)
-{
-  NVIC_DisableIRQ(_hcd_controller[rhport].irqnum);
-}
-
-#endif

From 8af8869d3bcb1504835ead4ba472cd922d997e8d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Jun 2023 11:26:38 +0700
Subject: [PATCH 1812/2085] renam OPT_MCU_MIMXRT to OPT_MCU_MIMXRT1XXX

fix build util with makefile
---
 examples/host/bare_api/only.txt          | 2 +-
 examples/host/cdc_msc_hid/only.txt       | 2 +-
 examples/host/hid_controller/only.txt    | 2 +-
 examples/host/msc_file_explorer/only.txt | 2 +-
 hw/bsp/board_mcu.h                       | 2 +-
 hw/bsp/f1c100s/README.md                 | 2 +-
 hw/bsp/imxrt/family.cmake                | 4 ++--
 hw/bsp/imxrt/family.mk                   | 2 +-
 src/class/audio/audio_device.c           | 4 ++--
 src/common/tusb_mcu.h                    | 2 +-
 src/portable/chipidea/ci_hs/dcd_ci_hs.c  | 2 +-
 src/portable/chipidea/ci_hs/hcd_ci_hs.c  | 5 ++---
 src/tusb_option.h                        | 6 +++---
 tools/build_utils.py                     | 7 +------
 14 files changed, 19 insertions(+), 25 deletions(-)

diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index fa9c14857..45da6c3f2 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -3,7 +3,7 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index fa9c14857..45da6c3f2 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -3,7 +3,7 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index fa9c14857..45da6c3f2 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -3,7 +3,7 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt
index fa9c14857..45da6c3f2 100644
--- a/examples/host/msc_file_explorer/only.txt
+++ b/examples/host/msc_file_explorer/only.txt
@@ -3,7 +3,7 @@ mcu:LPC177X_8X
 mcu:LPC18XX
 mcu:LPC40XX
 mcu:LPC43XX
-mcu:MIMXRT
+mcu:MIMXRT1XXX
 mcu:MIMXRT10XX
 mcu:MIMXRT11XX
 mcu:RP2040
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index edae4c645..ce2f919bf 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -116,7 +116,7 @@
 #elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI
   // no header needed
 
-#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT
+#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
   #include "fsl_device_registers.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_NUC120
diff --git a/hw/bsp/f1c100s/README.md b/hw/bsp/f1c100s/README.md
index f7a863c34..86d454f8e 100644
--- a/hw/bsp/f1c100s/README.md
+++ b/hw/bsp/f1c100s/README.md
@@ -17,4 +17,4 @@ Flash: `make BOARD=f1c100s flash` will write the image to SPI flash, and then re
 
 ## TODO
 
-* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT` high speed MCU check in examples (maybe we should extract the logic?)
+* Add F1C100s to `#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX` high speed MCU check in examples (maybe we should extract the logic?)
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index f687fe833..c2c067141 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -14,7 +14,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-set(FAMILY_MCUS MIMXRT CACHE INTERNAL "")
+set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "")
 
 # enable LTO if supported
 include(CheckIPOSupported)
@@ -119,7 +119,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB
-  family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT)
+  family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX)
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index 0c297f060..c3a69e7c5 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -13,7 +13,7 @@ CFLAGS += \
   -D__ARMVFP__=0 -D__ARMFPV5__=0\
   -DXIP_EXTERNAL_FLASH=1 \
   -DXIP_BOOT_HEADER_ENABLE=1 \
-  -DCFG_TUSB_MCU=OPT_MCU_MIMXRT
+  -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX
 
 ifdef BOARD_TUD_RHPORT
 CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT)
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index f487fe60e..e5dbe988a 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -66,7 +66,7 @@
 
 // Use ring buffer if it's available, some MCUs need extra RAM requirements
 #ifndef TUD_AUDIO_PREFER_RING_BUFFER
-  #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT
+  #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
     #define TUD_AUDIO_PREFER_RING_BUFFER 0
   #else
     #define TUD_AUDIO_PREFER_RING_BUFFER 1
@@ -85,7 +85,7 @@
     CFG_TUSB_MCU == OPT_MCU_RX72N     || \
     CFG_TUSB_MCU == OPT_MCU_LPC18XX   || \
     CFG_TUSB_MCU == OPT_MCU_LPC43XX   || \
-    CFG_TUSB_MCU == OPT_MCU_MIMXRT    || \
+    CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX    || \
     CFG_TUSB_MCU == OPT_MCU_MSP432E4
   #if TUD_AUDIO_PREFER_RING_BUFFER
     #define  USE_LINEAR_BUFFER     0
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 485d6168d..56525725e 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -90,7 +90,7 @@
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1
 
-#elif TU_CHECK_MCU(OPT_MCU_MIMXRT)
+#elif TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX)
   #define TUP_USBIP_CHIPIDEA_HS
   #define TUP_USBIP_EHCI
 
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 850c82e43..588e761a9 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -31,7 +31,7 @@
 #include "device/dcd.h"
 #include "ci_hs_type.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
   #include "ci_hs_imxrt.h"
 
   void dcd_dcache_clean(void* addr, uint32_t data_size) {
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 8c27abbf6..0f095147d 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -28,8 +28,7 @@
 
 // Chipidea Highspeed USB IP implement EHCI for host functionality
 
-#if CFG_TUH_ENABLED && \
-    (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT)
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_EHCI)
 
 //--------------------------------------------------------------------+
 // INCLUDE
@@ -39,7 +38,7 @@
 #include "portable/ehci/ehci_api.h"
 #include "ci_hs_type.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_MIMXRT
+#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
   #include "ci_hs_imxrt.h"
 
   void hcd_dcache_clean(void* addr, uint32_t data_size) {
diff --git a/src/tusb_option.h b/src/tusb_option.h
index bb669e693..43e67cf64 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -97,9 +97,9 @@
 #define OPT_MCU_VALENTYUSB_EPTRI  600 ///< Fomu eptri config
 
 // NXP iMX RT
-#define OPT_MCU_MIMXRT            700             ///< NXP iMX RT Series
-#define OPT_MCU_MIMXRT10XX        OPT_MCU_MIMXRT  ///< RT10xx
-#define OPT_MCU_MIMXRT11XX        OPT_MCU_MIMXRT  ///< RT11xx
+#define OPT_MCU_MIMXRT1XXX        700                 ///< NXP iMX RT1xxx Series
+#define OPT_MCU_MIMXRT10XX        OPT_MCU_MIMXRT1XXX  ///< RT10xx
+#define OPT_MCU_MIMXRT11XX        OPT_MCU_MIMXRT1XXX  ///< RT11xx
 
 // Nuvoton
 #define OPT_MCU_NUC121            800
diff --git a/tools/build_utils.py b/tools/build_utils.py
index 6f907729b..5d735bc17 100644
--- a/tools/build_utils.py
+++ b/tools/build_utils.py
@@ -30,13 +30,8 @@ def skip_example(example, board):
         family_dir = board_dir.parent.parent
         family = family_dir.name
 
-        # family CMake
-        family_mk = family_dir / "family.cmake"
-
         # family.mk
-        if not family_mk.exists():
-            family_mk = family_dir / "family.mk"
-
+        family_mk = family_dir / "family.mk"
         mk_contents = family_mk.read_text()
 
     # Find the mcu, first in family mk then board mk

From 65d6acdbfaea84c3274e359acd5e5474f04e8851 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Jun 2023 12:02:42 +0700
Subject: [PATCH 1813/2085] fix build warnings

---
 hw/bsp/family_support.cmake                  |  2 ++
 hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h | 11 +++++-----
 hw/bsp/imxrt/family.cmake                    | 12 ++++++----
 src/device/dcd.h                             |  6 ++---
 src/host/hcd.h                               |  6 ++---
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h    | 23 +++++++++++---------
 src/portable/chipidea/ci_hs/dcd_ci_hs.c      | 12 +++++-----
 src/portable/chipidea/ci_hs/hcd_ci_hs.c      |  6 ++---
 src/portable/ehci/ehci.c                     |  8 +++----
 9 files changed, 47 insertions(+), 39 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index dfc2095e5..02040c4ed 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -177,6 +177,8 @@ function(family_add_freertos TARGET)
     target_include_directories(freertos_config INTERFACE
       ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig
       )
+    # add board definition to freertos_config mostly for SystemCoreClock
+    target_link_libraries(freertos_config INTERFACE board_${BOARD})
   endif()
 
   # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable
diff --git a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
index c1928fbcd..f95927069 100644
--- a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
@@ -44,15 +44,14 @@
 
 // skip if included from IAR assembler
 #ifndef __IASMARM__
-// FIXME cause redundant-decls warnings
-extern uint32_t SystemCoreClock;
+  #include "fsl_device_registers.h"
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU						0
-#define configENABLE_FPU						1
-#define configENABLE_TRUSTZONE					0
-#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index c2c067141..fc90b7e80 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -103,10 +103,6 @@ function(family_configure_example TARGET)
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
-    # TinyUSB Port
-    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
-    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
-    ${TOP}/src/portable/ehci/ehci.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
@@ -121,6 +117,14 @@ function(family_configure_example TARGET)
   # Add TinyUSB
   family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX)
 
+  # Add TinyUSB Port source
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+    ${TOP}/src/portable/ehci/ehci.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
diff --git a/src/device/dcd.h b/src/device/dcd.h
index 4e9cfd5d5..18a708347 100644
--- a/src/device/dcd.h
+++ b/src/device/dcd.h
@@ -108,15 +108,15 @@ typedef struct TU_ATTR_ALIGNED(4)
 
 // clean/flush data cache: write cache -> memory.
 // Required before an DMA TX transfer to make sure data is in memory
-void dcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
 
 // invalidate data cache: mark cache as invalid, next read will read from memory
 // Required BOTH before and after an DMA RX transfer
-void dcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
 
 // clean and invalidate data cache
 // Required before an DMA transfer where memory is both read/write by DMA
-void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
 
 //--------------------------------------------------------------------+
 // Controller API
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 5a3b0a087..3355c18b2 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -110,15 +110,15 @@ typedef struct
 
 // clean/flush data cache: write cache -> memory.
 // Required before an DMA TX transfer to make sure data is in memory
-void hcd_dcache_clean(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+void hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
 
 // invalidate data cache: mark cache as invalid, next read will read from memory
 // Required BOTH before and after an DMA RX transfer
-void hcd_dcache_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+void hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
 
 // clean and invalidate data cache
 // Required before an DMA transfer where memory is both read/write by DMA
-void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) TU_ATTR_WEAK;
+void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
 
 //--------------------------------------------------------------------+
 // Controller API
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index ceff893bd..c14f00431 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -64,25 +64,28 @@ static const ci_hs_controller_t _ci_controller[] =
 #define CI_HCD_INT_DISABLE(_p)  NVIC_DisableIRQ(_ci_controller[_p].irqnum)
 
 //------------- DCache -------------//
-TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uint32_t addr) {
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) {
   return !(0x20000000 <= addr && addr < 0x20100000);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void* addr, uint32_t data_size) {
-  if (imxrt_is_cache_mem((uint32_t) addr)) {
-    SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size);
+TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (imxrt_is_cache_mem(addr32)) {
+    SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void* addr, uint32_t data_size) {
-  if (imxrt_is_cache_mem((uint32_t) addr)) {
-    SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
+TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (imxrt_is_cache_mem(addr32)) {
+    SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void* addr, uint32_t data_size) {
-  if (imxrt_is_cache_mem((uint32_t) addr)) {
-    SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
+TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (imxrt_is_cache_mem(addr32)) {
+    SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
   }
 }
 
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index 588e761a9..f50550d33 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -34,15 +34,15 @@
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
   #include "ci_hs_imxrt.h"
 
-  void dcd_dcache_clean(void* addr, uint32_t data_size) {
+  void dcd_dcache_clean(void const* addr, uint32_t data_size) {
     imxrt_dcache_clean(addr, data_size);
   }
 
-  void dcd_dcache_invalidate(void* addr, uint32_t data_size) {
+  void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
     imxrt_dcache_invalidate(addr, data_size);
   }
 
-  void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+  void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
     imxrt_dcache_clean_invalidate(addr, data_size);
   }
 
@@ -58,15 +58,15 @@
   #error "Unsupported MCUs"
 #endif
 
-  TU_ATTR_WEAK void dcd_dcache_clean(void* addr, uint32_t data_size) {
+  TU_ATTR_WEAK void dcd_dcache_clean(void const* addr, uint32_t data_size) {
     (void) addr; (void) data_size;
   }
 
-  TU_ATTR_WEAK void dcd_dcache_invalidate(void* addr, uint32_t data_size) {
+  TU_ATTR_WEAK void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
     (void) addr; (void) data_size;
   }
 
-  TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+  TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
     (void) addr; (void) data_size;
   }
 #endif
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 0f095147d..56167b8f6 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -41,15 +41,15 @@
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
   #include "ci_hs_imxrt.h"
 
-  void hcd_dcache_clean(void* addr, uint32_t data_size) {
+  void hcd_dcache_clean(void const* addr, uint32_t data_size) {
     imxrt_dcache_clean(addr, data_size);
   }
 
-  void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
+  void hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
     imxrt_dcache_invalidate(addr, data_size);
   }
 
-  void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+  void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
     imxrt_dcache_clean_invalidate(addr, data_size);
   }
 
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 2b25eee9d..38711e382 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -162,15 +162,15 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
 static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
 static inline ehci_link_t* list_next (ehci_link_t const *p_link);
 
-TU_ATTR_WEAK void hcd_dcache_clean(void* addr, uint32_t data_size) {
+TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) {
   (void) addr; (void) data_size;
 }
 
-TU_ATTR_WEAK void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
+TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
   (void) addr; (void) data_size;
 }
 
-TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
   (void) addr; (void) data_size;
 }
 
@@ -461,7 +461,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   qtd_init(td, setup_packet, 8);
   td->pid = EHCI_PID_SETUP;
 
-  hcd_dcache_clean((void *) setup_packet, 8);
+  hcd_dcache_clean(setup_packet, 8);
 
   // attach TD to QHD -> start transferring
   qhd_attach_qtd(qhd, td);

From a7f330fa94b7a39858f6d770737451b51f061c25 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Jun 2023 14:17:25 +0700
Subject: [PATCH 1814/2085] fix build, update freertos config for cmake

---
 examples/device/net_lwip_webserver/skip.txt   |  2 +-
 hw/bsp/family_support.cmake                   |  8 ++------
 hw/bsp/imxrt/family.cmake                     |  4 +---
 .../FreeRTOSConfig/FreeRTOSConfig.h           | 11 +++++-----
 .../boards/frdm_kl25z/clock_config.c          |  2 +-
 hw/bsp/kinetis_kl/family.cmake                | 10 ++++++----
 hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h  | 13 ++++++------
 hw/bsp/lpc18/family.cmake                     | 12 ++++++-----
 hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h  | 13 ++++++------
 hw/bsp/lpc55/family.cmake                     | 20 ++++++-------------
 hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h    | 13 ++++++------
 hw/bsp/mcx/family.cmake                       |  9 ++++++---
 hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h    | 13 ++++++------
 hw/bsp/nrf/boards/pca10095/board.cmake        |  2 +-
 hw/bsp/nrf/family.cmake                       | 10 +++++++---
 .../stm32g0/FreeRTOSConfig/FreeRTOSConfig.h   | 13 ++++++------
 hw/bsp/stm32g0/family.cmake                   | 11 +++++-----
 .../stm32g4/FreeRTOSConfig/FreeRTOSConfig.h   | 13 ++++++------
 hw/bsp/stm32g4/family.cmake                   | 10 ++++++----
 src/portable/nordic/nrf5x/dcd_nrf5x.c         | 14 +++++++++++++
 src/portable/st/typec/typec_stm32.c           |  4 ++--
 21 files changed, 107 insertions(+), 100 deletions(-)

diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt
index 77c7ec63a..e3a726a2b 100644
--- a/examples/device/net_lwip_webserver/skip.txt
+++ b/examples/device/net_lwip_webserver/skip.txt
@@ -4,7 +4,7 @@ mcu:MSP430x5xx
 mcu:NUC121
 mcu:SAMD11
 mcu:STM32L0
-mcu:MKL25ZXX
+mcu:KINETIS_KL
 family:broadcom_64bit
 family:broadcom_32bit
 board:curiosity_nano
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 02040c4ed..0132ef629 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -192,12 +192,8 @@ function(family_add_freertos TARGET)
     CFG_TUSB_OS=OPT_OS_FREERTOS
     )
   # link tinyusb with freeRTOS kernel
-  target_link_libraries(${TARGET}-tinyusb PUBLIC
-    freertos_kernel
-    )
-  target_link_libraries(${TARGET} PUBLIC
-    freertos_kernel
-    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel)
+  target_link_libraries(${TARGET} PUBLIC freertos_kernel)
 endfunction()
 
 
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index fc90b7e80..4a9842cf9 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -114,10 +114,8 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  # Add TinyUSB
+  # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX)
-
-  # Add TinyUSB Port source
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
     ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
diff --git a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
index 960bb23e1..a46af1759 100644
--- a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
@@ -44,15 +44,14 @@
 
 // skip if included from IAR assembler
 #ifndef __IASMARM__
-// FIXME cause redundant-decls warnings
-extern uint32_t SystemCoreClock;
+  #include "fsl_device_registers.h"
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU						0
-#define configENABLE_FPU						1
-#define configENABLE_TRUSTZONE					0
-#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c
index 1ba35e0dc..deabe25aa 100644
--- a/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c
+++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/clock_config.c
@@ -83,7 +83,7 @@ board: FRDM-KL25Z
  * Variables
  ******************************************************************************/
 /* System clock frequency. */
-extern uint32_t SystemCoreClock;
+//extern uint32_t SystemCoreClock;
 
 /*******************************************************************************
  * Code
diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake
index f491b3dee..5d4165185 100644
--- a/hw/bsp/kinetis_kl/family.cmake
+++ b/hw/bsp/kinetis_kl/family.cmake
@@ -87,9 +87,6 @@ function(family_configure_example TARGET)
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
-    # TinyUSB Port
-    ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
-    ${TOP}/src/portable/nxp/khci/hcd_khci.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
@@ -101,8 +98,13 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  # Add TinyUSB
+  # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+    ${TOP}/src/portable/nxp/khci/hcd_khci.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
diff --git a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
index 323c1a0a4..1b3c64e0b 100644
--- a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,17 +42,16 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
-// IAR assembler have limited preprocessor support and it only need following macros:
+// skip if included from IAR assembler
 #ifndef __IASMARM__
-// FIXME cause redundant-decls warnings
-extern uint32_t SystemCoreClock;
+  #include "chip.h"
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU						0
-#define configENABLE_FPU						0
-#define configENABLE_TRUSTZONE					0
-#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index bcdec9c01..4e6e2b56d 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -79,10 +79,6 @@ function(family_configure_example TARGET)
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
-    # TinyUSB Port
-    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
-    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
-    ${TOP}/src/portable/ehci/ehci.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
@@ -94,8 +90,14 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  # Add TinyUSB
+  # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+    ${TOP}/src/portable/ehci/ehci.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
diff --git a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
index 421106f08..b1cef793e 100644
--- a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,17 +42,16 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
-// IAR assembler have limited preprocessor support and it only need following macros:
+// skip if included from IAR assembler
 #ifndef __IASMARM__
-// FIXME cause redundant-decls warnings
-extern uint32_t SystemCoreClock;
+  #include "fsl_device_registers.h"
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU						0
-#define configENABLE_FPU						1
-#define configENABLE_TRUSTZONE					0
-#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 22a09ce10..43fbe8638 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -16,16 +16,6 @@ set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
-#------------------------------------
-# freertos
-#------------------------------------
-if (NOT TARGET freertos_config)
-  add_library(freertos_config INTERFACE)
-  target_include_directories(freertos_config SYSTEM INTERFACE
-    ${CMAKE_CURRENT_LIST_DIR}/FreeRTOSConfig
-    )
-endif()
-
 
 #------------------------------------
 # BOARD_TARGET
@@ -106,8 +96,6 @@ function(family_configure_example TARGET)
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
-    # TinyUSB Port
-    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
@@ -121,15 +109,19 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  # Add TinyUSB
+  # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
   # Flashing
   family_flash_jlink(${TARGET})
-  family_flash_nxplink(${TARGET})
+  #family_flash_nxplink(${TARGET})
   #family_flash_pyocd(${TARGET})
 endfunction()
 
diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
index 421106f08..b1cef793e 100644
--- a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,17 +42,16 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
-// IAR assembler have limited preprocessor support and it only need following macros:
+// skip if included from IAR assembler
 #ifndef __IASMARM__
-// FIXME cause redundant-decls warnings
-extern uint32_t SystemCoreClock;
+  #include "fsl_device_registers.h"
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU						0
-#define configENABLE_FPU						1
-#define configENABLE_TRUSTZONE					0
-#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 7c5feaecf..83f44222b 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -88,8 +88,6 @@ function(family_configure_example TARGET)
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
-    # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
-    ${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
@@ -101,8 +99,13 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  # Add TinyUSB
+  # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_MCXN9)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
+    ${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
diff --git a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
index 421106f08..a56f243ea 100644
--- a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,17 +42,16 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
-// IAR assembler have limited preprocessor support and it only need following macros:
+// skip if included from IAR assembler
 #ifndef __IASMARM__
-// FIXME cause redundant-decls warnings
-extern uint32_t SystemCoreClock;
+  #include "nrf.h"
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU						0
-#define configENABLE_FPU						1
-#define configENABLE_TRUSTZONE					0
-#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
index 1eb8ad4f1..1e72243c9 100644
--- a/hw/bsp/nrf/boards/pca10095/board.cmake
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -6,7 +6,7 @@ function(update_board TARGET)
     NRF5340_XXAA
     NRF5340_XXAA_APPLICATION
     )
-  target_sources(${TARGET} PUBLIC
+  target_sources(${TARGET} PRIVATE
     ${NRFX_DIR}/drivers/src/nrfx_usbreg.c
     )
 endfunction()
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 7faeaf6cb..88670b50b 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -100,8 +100,6 @@ function(family_configure_example TARGET)
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
-    # TinyUSB Port
-    ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
@@ -113,8 +111,14 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  # Add TinyUSB
+  # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_NRF5X)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
diff --git a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
index 1758efcf2..c8736f6d1 100644
--- a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,17 +42,16 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
-// IAR assembler have limited preprocessor support and it only need following macros:
+// skip if included from IAR assembler
 #ifndef __IASMARM__
-// FIXME cause redundant-decls warnings
-extern uint32_t SystemCoreClock;
+  #include "stm32g0xx.h"
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU						0
-#define configENABLE_FPU						0
-#define configENABLE_TRUSTZONE					0
-#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index 988033070..1381eaa5f 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -59,8 +59,6 @@ function(add_board_target BOARD_TARGET)
 
     update_board(${BOARD_TARGET})
 
-    cmake_print_variables(CMAKE_C_COMPILER_ID)
-
     if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
       target_link_options(${BOARD_TARGET} PUBLIC
         "LINKER:--script=${LD_FILE_GNU}"
@@ -90,8 +88,6 @@ function(family_configure_example TARGET)
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
-    # TinyUSB Port
-    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
@@ -103,8 +99,13 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  # Add TinyUSB
+  # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_STM32G0)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    ${TOP}/src/portable/st/typec/typec_stm32.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
diff --git a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
index 7974434d3..95fcbb08a 100644
--- a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -42,17 +42,16 @@
  * See http://www.freertos.org/a00110.html.
  *----------------------------------------------------------*/
 
-// IAR assembler have limited preprocessor support and it only need following macros:
+// skip if included from IAR assembler
 #ifndef __IASMARM__
-// FIXME cause redundant-decls warnings
-extern uint32_t SystemCoreClock;
+  #include "stm32g4xx.h"
 #endif
 
 /* Cortex M23/M33 port configuration. */
-#define configENABLE_MPU						0
-#define configENABLE_FPU						0
-#define configENABLE_TRUSTZONE					0
-#define configMINIMAL_SECURE_STACK_SIZE			(1024)
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
 
 #define configUSE_PREEMPTION                    1
 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index 618563f66..45525c744 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -88,9 +88,6 @@ function(family_configure_example TARGET)
   #---------- Port Specific ----------
   # These files are built for each example since it depends on example's tusb_config.h
   target_sources(${TARGET} PUBLIC
-    # TinyUSB Port
-    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
-    ${TOP}/src/portable/st/typec/typec_stm32.c
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
@@ -102,8 +99,13 @@ function(family_configure_example TARGET)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
     )
 
-  # Add TinyUSB
+  # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_STM32G4)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    ${TOP}/src/portable/st/typec/typec_stm32.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c
index eee5686f4..acc967bb3 100644
--- a/src/portable/nordic/nrf5x/dcd_nrf5x.c
+++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c
@@ -29,10 +29,24 @@
 #if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_NRF5X
 
 #include <stdatomic.h>
+
+// Suppress warning caused by nrfx driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wcast-align"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 #include "nrf.h"
 #include "nrf_clock.h"
 #include "nrf_power.h"
 #include "nrfx_usbd_errata.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 #include "device/dcd.h"
 
 // TODO remove later
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
index b09dc5bae..231da5450 100644
--- a/src/portable/st/typec/typec_stm32.c
+++ b/src/portable/st/typec/typec_stm32.c
@@ -186,7 +186,7 @@ bool tcd_init(uint8_t rhport, uint32_t port_type) {
     v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
     v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
 
-    TU_LOG1("Initial VState CC1 = %u, CC2 = %u\r\n", v_cc[0], v_cc[1]);
+    TU_LOG1("Initial VState CC1 = %lu, CC2 = %lu\r\n", v_cc[0], v_cc[1]);
 
     // Enable CC1 & CC2 Interrupt
     UCPD1->IMR = UCPD_IMR_TYPECEVT1IE | UCPD_IMR_TYPECEVT2IE;
@@ -246,7 +246,7 @@ void tcd_int_handler(uint8_t rhport) {
     v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
     v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
 
-    TU_LOG3("VState CC1 = %u, CC2 = %u\n", v_cc[0], v_cc[1]);
+    TU_LOG3("VState CC1 = %lu, CC2 = %lu\n", v_cc[0], v_cc[1]);
 
     uint32_t cr = UCPD1->CR;
 

From e754795d3adec4bc3a66a4131d0662d87acb4893 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Jun 2023 15:29:34 +0700
Subject: [PATCH 1815/2085] fix build warnings

---
 .github/workflows/build_iar.yml               |  2 +-
 .../device/audio_test_multi_rate/src/main.c   |  2 +-
 .../host/msc_file_explorer/CMakeLists.txt     |  7 +++++
 examples/rules.mk                             |  1 +
 examples/typec/power_delivery/src/main.c      |  4 +--
 hw/bsp/family_support.cmake                   | 29 +++++++++++++++++++
 hw/bsp/imxrt/family.c                         | 11 +++++++
 hw/bsp/lpc55/family.cmake                     |  1 +
 hw/bsp/nrf/family.c                           | 14 +++++++++
 hw/bsp/stm32g4/family.mk                      |  1 +
 src/portable/st/typec/typec_stm32.c           |  9 ++++--
 tools/cmake/toolchain/arm_gcc.cmake           | 26 -----------------
 tools/cmake/toolchain/arm_iar.cmake           |  3 --
 13 files changed, 73 insertions(+), 37 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 83e81164a..7e42a66f8 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -32,7 +32,7 @@ jobs:
         # Alphabetical order
         # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
         # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
-        - 'stm32f0 stm32f1 stm32f4 stm32f7 stm32g4 stm32h7 stm32l4'
+        - 'stm32f0 stm32f1 stm32f7 stm32h7 stm32l4'
     steps:
     - name: Clean workspace
       run: |
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
index 4dd53dd34..078e783eb 100644
--- a/examples/device/audio_test_multi_rate/src/main.c
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -268,7 +268,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
 
         sampFreq = (uint32_t)((audio_control_cur_4_t *)pBuff)->bCur;
 
-        TU_LOG2("Clock set current freq: %d\r\n", sampFreq);
+        TU_LOG2("Clock set current freq: %lu\r\n", sampFreq);
 
         return true;
       break;
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 2d5600059..327d1218a 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -21,6 +21,13 @@ target_sources(${PROJECT} PUBLIC
   ${TOP}/lib/fatfs/source/ffunicode.c
   )
 
+# Suppress warnings on fatfs
+set_source_files_properties(
+  ${TOP}/lib/fatfs/source/ff.c
+  PROPERTIES
+  COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual"
+)
+
 # Example include
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
diff --git a/examples/rules.mk b/examples/rules.mk
index f6422092a..5727ab7e3 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -28,6 +28,7 @@ SRC_C += \
 	src/common/tusb_fifo.c \
 	src/device/usbd.c \
 	src/device/usbd_control.c \
+	src/typec/usbc.c \
 	src/class/audio/audio_device.c \
 	src/class/cdc/cdc_device.c \
 	src/class/dfu/dfu_device.c \
diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
index 342a2235f..08590aa74 100644
--- a/examples/typec/power_delivery/src/main.c
+++ b/examples/typec/power_delivery/src/main.c
@@ -63,9 +63,6 @@ int main(void)
 
   tuc_init(0, TUSB_TYPEC_PORT_SNK);
 
-  uint32_t start_ms = 0;
-  bool led_state = false;
-
   while (1) {
     led_blinking_task();
 
@@ -155,6 +152,7 @@ bool tuc_pd_data_received_cb(uint8_t rhport, pd_header_t const* header, uint8_t
 }
 
 bool tuc_pd_control_received_cb(uint8_t rhport, pd_header_t const* header) {
+  (void) rhport;
   switch (header->msg_type) {
     case PD_CTRL_ACCEPT:
       printf("PD Request Accepted\r\n");
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 0132ef629..ec36df5c8 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -19,6 +19,33 @@ if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
   message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
 endif()
 
+set(WARNING_FLAGS_GNU
+  -Wall
+  -Wextra
+  -Werror
+  -Wfatal-errors
+  -Wdouble-promotion
+  -Wstrict-prototypes
+  -Wstrict-overflow
+  -Werror-implicit-function-declaration
+  -Wfloat-equal
+  -Wundef
+  -Wshadow
+  -Wwrite-strings
+  -Wsign-compare
+  -Wmissing-format-attribute
+  -Wunreachable-code
+  -Wcast-align
+  -Wcast-function-type
+  -Wcast-qual
+  -Wnull-dereference
+  -Wuninitialized
+  -Wunused
+  -Wreturn-type
+  -Wredundant-decls
+  )
+
+set(WARNINGS_FLAGS_IAR "")
 
 function(family_filter RESULT DIR)
   get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
@@ -121,6 +148,8 @@ function(family_configure_common TARGET)
     COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${TARGET}>
     )
 
+  target_compile_options(${TARGET} PUBLIC ${WARNING_FLAGS_${CMAKE_C_COMPILER_ID}})
+
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
     # Generate map file
     target_link_options(${TARGET} PUBLIC
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 46adabf0a..735fbdb9b 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -26,12 +26,23 @@
 
 #include "bsp/board.h"
 #include "board.h"
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
 #include "fsl_iomuxc.h"
 #include "fsl_clock.h"
 #include "fsl_lpuart.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 #include "clock_config.h"
 
 #if defined(BOARD_TUD_RHPORT) && CFG_TUD_ENABLED
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 43fbe8638..9f6b1f63d 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -102,6 +102,7 @@ function(family_configure_example TARGET)
     # external driver
     ${TOP}/lib/sct_neopixel/sct_neopixel.c
     )
+
   target_include_directories(${TARGET} PUBLIC
     # family, hw, board
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 157b2bf21..6a559ada6 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -27,6 +27,15 @@
 #include "bsp/board.h"
 #include "board.h"
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wcast-align"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#pragma GCC diagnostic ignored "-Wundef"
+#endif
+
 #include "nrfx.h"
 #include "hal/nrf_gpio.h"
 #include "drivers/include/nrfx_power.h"
@@ -37,6 +46,11 @@
 #include "nrf_soc.h"
 #endif
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk
index 5ed84422d..a4b644245 100644
--- a/hw/bsp/stm32g4/family.mk
+++ b/hw/bsp/stm32g4/family.mk
@@ -36,6 +36,7 @@ IAR_ASFLAGS += --cpu cortex-m4 --fpu VFPv4
 
 SRC_C += \
 	src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \
+	src/portable/st/typec/typec_stm32.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
index 231da5450..bf8b660f0 100644
--- a/src/portable/st/typec/typec_stm32.c
+++ b/src/portable/st/typec/typec_stm32.c
@@ -183,9 +183,9 @@ bool tcd_init(uint8_t rhport, uint32_t port_type) {
 
     // Read Voltage State on CC1 & CC2 fore initial state
     uint32_t v_cc[2];
+    (void) v_cc;
     v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
     v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
-
     TU_LOG1("Initial VState CC1 = %lu, CC2 = %lu\r\n", v_cc[0], v_cc[1]);
 
     // Enable CC1 & CC2 Interrupt
@@ -308,8 +308,11 @@ void tcd_int_handler(uint8_t rhport) {
 
     if (!(sr & UCPD_SR_RXERR)) {
       // response with good crc
-      _good_crc.msg_id = ((pd_header_t const*) _rx_buf)->msg_id;
-      dma_tx_start(rhport, &_good_crc, 2);
+      // TODO move this to usbc stack
+      if (_rx_buf) {
+        _good_crc.msg_id = ((pd_header_t const *) _rx_buf)->msg_id;
+        dma_tx_start(rhport, &_good_crc, 2);
+      }
 
       result = XFER_RESULT_SUCCESS;
     }else {
diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake
index 6dd1e7002..cefa9d2ce 100644
--- a/tools/cmake/toolchain/arm_gcc.cmake
+++ b/tools/cmake/toolchain/arm_gcc.cmake
@@ -35,32 +35,6 @@ set(TOOLCHAIN_EXE_LINKER_FLAGS
   -Wl,--cref
   )
 
-set(TOOLCHAIN_WARNING_FLAGS
-  -Wall
-  -Wextra
-  -Werror
-  -Wfatal-errors
-  -Wdouble-promotion
-  -Wstrict-prototypes
-  -Wstrict-overflow
-  -Werror-implicit-function-declaration
-  -Wfloat-equal
-  -Wundef
-  -Wshadow
-  -Wwrite-strings
-  -Wsign-compare
-  -Wmissing-format-attribute
-  -Wunreachable-code
-  -Wcast-align
-  -Wcast-function-type
-  -Wcast-qual
-  -Wnull-dereference
-  -Wuninitialized
-  -Wunused
-  -Wreturn-type
-  -Wredundant-decls
-  )
-
 include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake)
 
 # try_compile is cmake test compiling its own example,
diff --git a/tools/cmake/toolchain/arm_iar.cmake b/tools/cmake/toolchain/arm_iar.cmake
index dfbe55e0d..a487e5b9f 100644
--- a/tools/cmake/toolchain/arm_iar.cmake
+++ b/tools/cmake/toolchain/arm_iar.cmake
@@ -28,7 +28,4 @@ list(APPEND TOOLCHAIN_COMMON_FLAGS
 list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS
   )
 
-list(APPEND TOOLCHAIN_WARNING_FLAGS
-  )
-
 include(${CMAKE_CURRENT_LIST_DIR}/set_flags.cmake)

From 1419091923e7b524b920afb2dabdf323c3b6a44d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Jun 2023 16:47:32 +0700
Subject: [PATCH 1816/2085] update h7 to cmake, and move iar build to cmake

---
 .github/workflows/build_iar.yml               |   4 +-
 hw/bsp/imxrt/family.mk                        |  14 +-
 .../stm32h7/FreeRTOSConfig/FreeRTOSConfig.h   | 165 +++++++++++++++++
 hw/bsp/stm32h7/boards/daisyseed/board.cmake   |  19 ++
 .../boards/stm32h723nucleo/board.cmake        |  18 ++
 .../stm32h7/boards/stm32h723nucleo/board.mk   |   2 +-
 .../stm32h7/boards/stm32h743eval/board.cmake  |  18 ++
 hw/bsp/stm32h7/boards/stm32h743eval/board.mk  |   2 +-
 .../boards/stm32h743nucleo/board.cmake        |  18 ++
 .../stm32h7/boards/stm32h743nucleo/board.mk   |   2 +-
 .../stm32h743nucleo/stm32h743xx_flash.ld      | 171 -----------------
 .../stm32h7/boards/stm32h745disco/board.cmake |  19 ++
 .../STM32H743IITX_FLASH.ld                    | 173 ------------------
 .../boards/waveshare_openh743i/board.cmake    |  23 +++
 .../boards/waveshare_openh743i/board.mk       |   2 +-
 hw/bsp/stm32h7/family.cmake                   | 130 +++++++++++++
 hw/bsp/stm32h7/family.mk                      |   6 +-
 .../stm32h723xx_flash.ld                      |   0
 .../stm32h743xx_flash.ld                      |   0
 19 files changed, 424 insertions(+), 362 deletions(-)
 create mode 100644 hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/stm32h7/boards/daisyseed/board.cmake
 create mode 100644 hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake
 create mode 100644 hw/bsp/stm32h7/boards/stm32h743eval/board.cmake
 create mode 100644 hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake
 delete mode 100644 hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
 create mode 100644 hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
 delete mode 100644 hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
 create mode 100644 hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake
 create mode 100644 hw/bsp/stm32h7/family.cmake
 rename hw/bsp/stm32h7/{boards/stm32h723nucleo => linker}/stm32h723xx_flash.ld (100%)
 rename hw/bsp/stm32h7/{boards/stm32h743eval => linker}/stm32h743xx_flash.ld (100%)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 7e42a66f8..08149e201 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -32,7 +32,7 @@ jobs:
         # Alphabetical order
         # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
         # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
-        - 'stm32f0 stm32f1 stm32f7 stm32h7 stm32l4'
+        - 'stm32f0 stm32f1 stm32f7 stm32l4'
     steps:
     - name: Clean workspace
       run: |
@@ -58,7 +58,7 @@ jobs:
           # Alphabetical order
           # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
           # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
-          - 'stm32g0 stm32g4'
+          - 'stm32g0 stm32g4 stm32h7'
     steps:
       - name: Clean workspace
         run: |
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index c3a69e7c5..d0bb5be17 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -4,13 +4,12 @@ DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+CPU_CORE ?= cortex-m7
+include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
+
 CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
-  -D__ARMVFP__=0 -D__ARMFPV5__=0\
+  -D__ARMVFP__=0 \
+  -D__ARMFPV5__=0 \
   -DXIP_EXTERNAL_FLASH=1 \
   -DXIP_BOOT_HEADER_ENABLE=1 \
   -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX
@@ -58,9 +57,6 @@ INC += \
 
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
-
 # UF2 generation, iMXRT need to strip to text only before conversion
 APPLICATION_ADDR = 0x6000C000
 $(BUILD)/$(PROJECT).uf2: $(BUILD)/$(PROJECT).elf
diff --git a/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6881385a8
--- /dev/null
+++ b/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32h7xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.cmake b/hw/bsp/stm32h7/boards/daisyseed/board.cmake
new file mode 100644
index 000000000..9fac51128
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.cmake
@@ -0,0 +1,19 @@
+set(MCU_VARIANT stm32h750xx)
+set(JLINK_DEVICE stm32h750ibk6_m7)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32h750ibkx_flash.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H750xx
+    HSE_VALUE=16000000
+    CORE_CM7
+    # default to PORT 0
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake
new file mode 100644
index 000000000..ac1acd346
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake
@@ -0,0 +1,18 @@
+set(MCU_VARIANT stm32h723xx)
+set(JLINK_DEVICE stm32h723zg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H723xx
+    HSE_VALUE=8000000
+    # default to PORT 0
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
index 57dfb7e64..9cf241df8 100644
--- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
@@ -5,7 +5,7 @@ PORT ?= 0
 
 # GCC
 GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h723xx.s
-GCC_LD_FILE = $(BOARD_PATH)/stm32h723xx_flash.ld
+GCC_LD_FILE =  $(FAMILY_PATH)/linker/stm32h723xx_flash.ld
 
 # IAR
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h723xx.s
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake
new file mode 100644
index 000000000..2cd2a4bac
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake
@@ -0,0 +1,18 @@
+set(MCU_VARIANT stm32h743xx)
+set(JLINK_DEVICE stm32h743xi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H743xx
+    HSE_VALUE=25000000
+    # default to PORT 1 High Speed
+    BOARD_TUD_RHPORT=1
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
index 78ff47c09..558e943b4 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
@@ -6,7 +6,7 @@ SPEED ?= high
 
 # GCC
 GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-GCC_LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
+GCC_LD_FILE = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld
 
 # IAR
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake
new file mode 100644
index 000000000..9d5f09be4
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake
@@ -0,0 +1,18 @@
+set(MCU_VARIANT stm32h743xx)
+set(JLINK_DEVICE stm32h743xi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H743xx
+    HSE_VALUE=8000000
+    # default to PORT 0
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
index 4bdd5b6a8..0bff0940e 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
@@ -5,7 +5,7 @@ PORT ?= 0
 
 # GCC
 GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-GCC_LD_FILE = $(BOARD_PATH)/stm32h743xx_flash.ld
+GCC_LD_FILE = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld
 
 # IAR
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld b/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
deleted file mode 100644
index 336afc01f..000000000
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/stm32h743xx_flash.ld
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
-*****************************************************************************
-**
-
-**  File        : LinkerScript.ld
-**
-**  Abstract    : Linker script for STM32H743XIHx Device with
-**                2048KByte FLASH, 128KByte RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-**  (c)Copyright Ac6.
-**  You may use this file as-is or modify it according to the needs of your
-**  project. Distribution of this file (unmodified or modified) is not
-**  permitted. Ac6 permit registered System Workbench for MCU users the
-**  rights to distribute the assembled, compiled & linked contents of this
-**  file as part of an application binary file, provided that it is built
-**  using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200;      /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-DTCMRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-RAM_D1 (xrw)      : ORIGIN = 0x24000000, LENGTH = 512K
-RAM_D2 (xrw)      : ORIGIN = 0x30000000, LENGTH = 288K
-RAM_D3 (xrw)      : ORIGIN = 0x38000000, LENGTH = 64K
-ITCMRAM (xrw)      : ORIGIN = 0x00000000, LENGTH = 64K
-FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 2048K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data :
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >DTCMRAM AT> FLASH
-
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >DTCMRAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >DTCMRAM
-
-
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake b/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
new file mode 100644
index 000000000..46744df49
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
@@ -0,0 +1,19 @@
+set(MCU_VARIANT stm32h745xx)
+set(JLINK_DEVICE stm32h745xi_m7)
+
+set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_CM7.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash_CM7.icf)
+
+set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H745xx
+    HSE_VALUE=25000000
+    CORE_CM7
+    # default to PORT 0
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld b/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
deleted file mode 100644
index 697a1a1df..000000000
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/STM32H743IITX_FLASH.ld
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
-******************************************************************************
-**
-**  File        : LinkerScript.ld
-**
-**  Author      : STM32CubeIDE
-**
-**  Abstract    : Linker script for STM32H7 series
-**                2048Kbytes FLASH and 192Kbytes RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Distribution: The file is distributed as is, without any warranty
-**                of any kind.
-**
-*****************************************************************************
-** @attention
-**
-** Copyright (c) 2019 STMicroelectronics.
-** All rights reserved.
-**
-** This software component is licensed by ST under BSD 3-Clause license,
-** the "License"; You may not use this file except in compliance with the
-** License. You may obtain a copy of the License at:
-**                        opensource.org/licenses/BSD-3-Clause
-**
-****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20020000;    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x2000 ;  /* required amount of heap  */
-_Min_Stack_Size = 0x2000 ; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-  FLASH (rx)     : ORIGIN = 0x08000000, LENGTH = 2048K
-  RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
-  RAM_D1 (xrw)   : ORIGIN = 0x24000000, LENGTH = 512K
-  RAM_D2 (xrw)   : ORIGIN = 0x30000000, LENGTH = 288K
-  RAM_D3 (xrw)   : ORIGIN = 0x38000000, LENGTH = 64K
-  ITCMRAM (xrw)  : ORIGIN = 0x00000000, LENGTH = 64K
-}
-
-/* Define output sections */
-SECTIONS
-{
-  /* The startup code goes first into FLASH */
-  .isr_vector :
-  {
-    . = ALIGN(4);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(4);
-  } >FLASH
-
-  /* The program code and other data goes into FLASH */
-  .text :
-  {
-    . = ALIGN(4);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(4);
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data goes into FLASH */
-  .rodata :
-  {
-    . = ALIGN(4);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(4);
-  } >FLASH
-
-  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
-  .ARM : {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array     :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections goes into RAM, load LMA copy after code */
-  .data :
-  {
-    . = ALIGN(4);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-    *(.RamFunc)        /* .RamFunc sections */
-    *(.RamFunc*)       /* .RamFunc* sections */
-
-    . = ALIGN(4);
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section */
-  . = ALIGN(4);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(4);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough RAM left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  /* Remove information from the standard libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake
new file mode 100644
index 000000000..033d3a9f2
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake
@@ -0,0 +1,23 @@
+set(MCU_VARIANT stm32h743xx)
+set(JLINK_DEVICE stm32h743xi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32H743xx
+    HSE_VALUE=8000000
+    HAL_TIM_MODULE_ENABLED
+    # default to PORT 1 High Speed
+    BOARD_TUD_RHPORT=1
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+  target_sources(${TARGET} PUBLIC
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_tim.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_tim_ex.c
+    )
+endfunction()
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
index e8202d9fc..9997faff9 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
@@ -11,7 +11,7 @@ SRC_C += \
 
 # GCC
 GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32H743IITX_FLASH.ld
+GCC_LD_FILE = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld
 
 # IAR
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake
new file mode 100644
index 000000000..f04a768a5
--- /dev/null
+++ b/hw/bsp/stm32h7/family.cmake
@@ -0,0 +1,130 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY h7)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32H7 CACHE INTERNAL "")
+
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET)
+  family_configure_common(${TARGET})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32H7)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(family_configure_device_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index 8042248a8..c11240207 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -53,13 +53,13 @@ SRC_C += \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/stm32h723xx_flash.ld b/hw/bsp/stm32h7/linker/stm32h723xx_flash.ld
similarity index 100%
rename from hw/bsp/stm32h7/boards/stm32h723nucleo/stm32h723xx_flash.ld
rename to hw/bsp/stm32h7/linker/stm32h723xx_flash.ld
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld b/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld
similarity index 100%
rename from hw/bsp/stm32h7/boards/stm32h743eval/stm32h743xx_flash.ld
rename to hw/bsp/stm32h7/linker/stm32h743xx_flash.ld

From 268ce0287f25eb73c2f0dbe5180981e09d84ec47 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 16 Jun 2023 19:39:03 +0700
Subject: [PATCH 1817/2085] correct cmake iar build

---
 .github/workflows/build_iar.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 08149e201..48d66240e 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -73,4 +73,4 @@ jobs:
         run: python3 tools/get_deps.py ${{ matrix.family }}
 
       - name: Build
-        run: python3 tools/build_cmake.py ${{ matrix.family }} -DTOOLCHAIN=iccarm
+        run: python3 tools/build_cmake.py ${{ matrix.family }} -DTOOLCHAIN=iar

From 5e78f08a24a1f53d66be9bc2df82051fc70cdf90 Mon Sep 17 00:00:00 2001
From: dsugisawa-mixi <daisuke.sugisawa.ts@mixi.co.jp>
Date: Sat, 17 Jun 2023 19:04:17 +0900
Subject: [PATCH 1818/2085] fix example of bare_api, check empty string

---
 examples/host/bare_api/src/main.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index bb7fa850e..d1ee5e9ac 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -410,6 +410,7 @@ static int _count_utf8_bytes(const uint16_t *buf, size_t len) {
 }
 
 static void print_utf16(uint16_t *temp_buf, size_t buf_len) {
+    if ((temp_buf[0] & 0xff) == 0) return;  // empty
     size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t);
     size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len);
     _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len);

From 7dc6829519afd3aa30523950efaa2438b6b6dbe9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 19 Jun 2023 16:33:47 +0700
Subject: [PATCH 1819/2085] enable etm trace support for h743 eval

---
 hw/bsp/family_support.cmake                   |    5 +
 hw/bsp/stm32h7/boards/stm32h743eval/board.h   |   57 +-
 .../stm32h743eval/cubemx/stm32h743eval.ioc    | 1125 +++++++++++++++++
 .../stm32h743eval/ozone/h743eval.jdebug       |  249 ++++
 hw/bsp/stm32h7/family.c                       |   26 +
 5 files changed, 1443 insertions(+), 19 deletions(-)
 create mode 100644 hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
 create mode 100644 hw/bsp/stm32h7/boards/stm32h743eval/ozone/h743eval.jdebug

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index ec36df5c8..73e674c18 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -166,6 +166,11 @@ function(family_configure_common TARGET)
     endif ()
   endif ()
 
+  # ETM Trace
+  if (TRACE_ETM STREQUAL "1")
+    target_compile_definitions(${TARGET} PUBLIC TRACE_ETM)
+  endif ()
+
 endfunction()
 
 
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
index 666bec9a1..7e3c015c8 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
@@ -85,41 +85,60 @@ static inline void board_stm32h7_clock_init(void)
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 
-  /* PLL1 for System Clock */
+  // PLL1 for System Clock
+#ifdef TRACE_ETM
+  // From H743 eval board manual
+  // - ETM can only work at 50 MHz clock by default because ETM signals are shared with other peripherals. If better
+  //   performance of ETM is required (84 MHz/98 MHz), R217, R230, R231, R234, R236, SB2, SB5, SB8, SB11,
+  //   SB42, SB57 must be removed to reduce the stub on ETM signals. In this configuration SAI and PDM are not
+  //   functional and NOR Flash and the address of SRAM are limited on A18.
+  // - ETM trace function would be abnormal as SAI_SDB share the same pins with TRACE_D0, and TRACE_D0
+  //   would be forced high by SAI_SDB. When using ETM trace it is necessary to set ADCDAT1 pin (SAI_SDB signal
+  //   of the STM32) of audio codec WM8994ECS/R (U22) by software to be tri-state.
+
+  // Since Trace CLK = PLL1 / 3 --> max PLL1 clock is 150Mhz
+  RCC_OscInitStruct.PLL.PLLM = 2;
+  RCC_OscInitStruct.PLL.PLLN = 24;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+#else
+  // Set PLL1 to 400Mhz
   RCC_OscInitStruct.PLL.PLLM = 5;
   RCC_OscInitStruct.PLL.PLLN = 160;
-  RCC_OscInitStruct.PLL.PLLFRACN = 0;
   RCC_OscInitStruct.PLL.PLLP = 2;
   RCC_OscInitStruct.PLL.PLLR = 2;
   RCC_OscInitStruct.PLL.PLLQ = 4;
-
+#endif
   RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
   RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
-  /* PLL3 for USB Clock */
-  PeriphClkInitStruct.PLL3.PLL3M = 25;
-  PeriphClkInitStruct.PLL3.PLL3N = 336;
-  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
-  PeriphClkInitStruct.PLL3.PLL3P = 2;
-  PeriphClkInitStruct.PLL3.PLL3R = 2;
-  PeriphClkInitStruct.PLL3.PLL3Q = 7;
 
-  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
-  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-
-  /* Select PLL as system clock source and configure  bus clocks dividers */
-  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \
-  RCC_CLOCKTYPE_PCLK2  | RCC_CLOCKTYPE_D3PCLK1);
+  /* Select PLL as system clock source and configure bus clocks dividers */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 |
+      RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1;
 
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
-  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
-  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  /* PLL3 for USB Clock */
+  PeriphClkInitStruct.PLL3.PLL3M = 25;
+  PeriphClkInitStruct.PLL3.PLL3N = 336;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.PLL3.PLL3P = 2;
+  PeriphClkInitStruct.PLL3.PLL3Q = 7;
+  PeriphClkInitStruct.PLL3.PLL3R = 2;
+
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
   /*activate CSI clock mondatory for I/O Compensation Cell*/
   __HAL_RCC_CSI_ENABLE() ;
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
new file mode 100644
index 000000000..1cc2cc8fa
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
@@ -0,0 +1,1125 @@
+#MicroXplorer Configuration settings - do not modify
+CAD.formats=[]
+CAD.pinconfig=Project naming
+CAD.provider=
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+Mcu.CPN=STM32H743XIH6
+Mcu.Family=STM32H7
+Mcu.IP0=CORTEX_M7
+Mcu.IP1=DEBUG
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IP5=USB_OTG_FS
+Mcu.IP6=USB_OTG_HS
+Mcu.IPNb=7
+Mcu.Name=STM32H743XIHx
+Mcu.Package=TFBGA240
+Mcu.Pin0=PI6
+Mcu.Pin1=PI5
+Mcu.Pin10=PA15 (JTDI)
+Mcu.Pin100=PC1
+Mcu.Pin101=PC2
+Mcu.Pin102=PC3
+Mcu.Pin103=PJ9
+Mcu.Pin104=PH2
+Mcu.Pin105=PA2
+Mcu.Pin106=PA1
+Mcu.Pin107=PJ0
+Mcu.Pin108=PE10
+Mcu.Pin109=PJ8
+Mcu.Pin11=PI1
+Mcu.Pin110=PJ7
+Mcu.Pin111=PJ6
+Mcu.Pin112=PH3
+Mcu.Pin113=PH4
+Mcu.Pin114=PH5
+Mcu.Pin115=PI15
+Mcu.Pin116=PJ1
+Mcu.Pin117=PF13
+Mcu.Pin118=PF14
+Mcu.Pin119=PE9
+Mcu.Pin12=PI0
+Mcu.Pin120=PE11
+Mcu.Pin121=PB10
+Mcu.Pin122=PB11
+Mcu.Pin123=PH10
+Mcu.Pin124=PH11
+Mcu.Pin125=PD15
+Mcu.Pin126=PD14
+Mcu.Pin127=PA6
+Mcu.Pin128=PA7
+Mcu.Pin129=PB2
+Mcu.Pin13=PI7
+Mcu.Pin130=PF12
+Mcu.Pin131=PF15
+Mcu.Pin132=PE12
+Mcu.Pin133=PE15
+Mcu.Pin134=PJ5
+Mcu.Pin135=PH9
+Mcu.Pin136=PH12
+Mcu.Pin137=PD11
+Mcu.Pin138=PD12
+Mcu.Pin139=PD13
+Mcu.Pin14=PE1
+Mcu.Pin140=PA0_C
+Mcu.Pin141=PA5
+Mcu.Pin142=PC4
+Mcu.Pin143=PB1
+Mcu.Pin144=PJ2
+Mcu.Pin145=PF11
+Mcu.Pin146=PG0
+Mcu.Pin147=PE8
+Mcu.Pin148=PE13
+Mcu.Pin149=PH6
+Mcu.Pin15=PB6
+Mcu.Pin150=PH8
+Mcu.Pin151=PB12
+Mcu.Pin152=PB15
+Mcu.Pin153=PD10
+Mcu.Pin154=PD9
+Mcu.Pin155=PA3
+Mcu.Pin156=PA4
+Mcu.Pin157=PC5
+Mcu.Pin158=PB0
+Mcu.Pin159=PJ3
+Mcu.Pin16=PB4 (NJTRST)
+Mcu.Pin160=PJ4
+Mcu.Pin161=PG1
+Mcu.Pin162=PE7
+Mcu.Pin163=PE14
+Mcu.Pin164=PH7
+Mcu.Pin165=PB13
+Mcu.Pin166=PB14
+Mcu.Pin167=PD8
+Mcu.Pin168=VP_SYS_VS_Systick
+Mcu.Pin17=PK4
+Mcu.Pin18=PG11
+Mcu.Pin19=PJ15
+Mcu.Pin2=PI4
+Mcu.Pin20=PD6
+Mcu.Pin21=PD3
+Mcu.Pin22=PC11
+Mcu.Pin23=PA14 (JTCK/SWCLK)
+Mcu.Pin24=PI2
+Mcu.Pin25=PH15
+Mcu.Pin26=PH14
+Mcu.Pin27=PC15-OSC32_OUT (OSC32_OUT)
+Mcu.Pin28=PC14-OSC32_IN (OSC32_IN)
+Mcu.Pin29=PE2
+Mcu.Pin3=PB5
+Mcu.Pin30=PE0
+Mcu.Pin31=PB7
+Mcu.Pin32=PB3 (JTDO/TRACESWO)
+Mcu.Pin33=PK6
+Mcu.Pin34=PK3
+Mcu.Pin35=PG12
+Mcu.Pin36=PD7
+Mcu.Pin37=PC12
+Mcu.Pin38=PI3
+Mcu.Pin39=PA13 (JTMS/SWDIO)
+Mcu.Pin4=PK5
+Mcu.Pin40=PE5
+Mcu.Pin41=PE4
+Mcu.Pin42=PE3
+Mcu.Pin43=PB9
+Mcu.Pin44=PB8
+Mcu.Pin45=PG15
+Mcu.Pin46=PK7
+Mcu.Pin47=PG14
+Mcu.Pin48=PG13
+Mcu.Pin49=PJ14
+Mcu.Pin5=PG10
+Mcu.Pin50=PJ12
+Mcu.Pin51=PD2
+Mcu.Pin52=PD0
+Mcu.Pin53=PA10
+Mcu.Pin54=PA9
+Mcu.Pin55=PH13
+Mcu.Pin56=PI9
+Mcu.Pin57=PC13
+Mcu.Pin58=PI8
+Mcu.Pin59=PE6
+Mcu.Pin6=PG9
+Mcu.Pin60=PJ13
+Mcu.Pin61=PD1
+Mcu.Pin62=PC8
+Mcu.Pin63=PC9
+Mcu.Pin64=PA8
+Mcu.Pin65=PA12
+Mcu.Pin66=PA11
+Mcu.Pin67=PI10
+Mcu.Pin68=PI11
+Mcu.Pin69=PC7
+Mcu.Pin7=PD5
+Mcu.Pin70=PC6
+Mcu.Pin71=PG8
+Mcu.Pin72=PG7
+Mcu.Pin73=PF2
+Mcu.Pin74=PF1
+Mcu.Pin75=PF0
+Mcu.Pin76=PG5
+Mcu.Pin77=PG6
+Mcu.Pin78=PI12
+Mcu.Pin79=PI13
+Mcu.Pin8=PD4
+Mcu.Pin80=PI14
+Mcu.Pin81=PF3
+Mcu.Pin82=PG4
+Mcu.Pin83=PG3
+Mcu.Pin84=PG2
+Mcu.Pin85=PK2
+Mcu.Pin86=PH1-OSC_OUT (PH1)
+Mcu.Pin87=PH0-OSC_IN (PH0)
+Mcu.Pin88=PF5
+Mcu.Pin89=PF4
+Mcu.Pin9=PC10
+Mcu.Pin90=PK0
+Mcu.Pin91=PK1
+Mcu.Pin92=PF6
+Mcu.Pin93=PF7
+Mcu.Pin94=PF8
+Mcu.Pin95=PJ11
+Mcu.Pin96=PC0
+Mcu.Pin97=PF10
+Mcu.Pin98=PF9
+Mcu.Pin99=PJ10
+Mcu.PinsNb=169
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32H743XIHx
+MxCube.Version=6.8.1
+MxDb.Version=DB.6.0.81
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false
+PA0_C.GPIOParameters=GPIO_Label
+PA0_C.GPIO_Label=Potentiometer
+PA0_C.Locked=true
+PA0_C.Signal=ADCx_INN1
+PA1.GPIOParameters=GPIO_Label
+PA1.GPIO_Label=RMII_REF_CLK [LAN8742A_REFCLK0]
+PA1.Locked=true
+PA1.Signal=ETH_REF_CLK
+PA10.GPIOParameters=GPIO_Label
+PA10.GPIO_Label=USB_FS1_ID
+PA10.Locked=true
+PA10.Signal=USB_OTG_FS_ID
+PA11.GPIOParameters=GPIO_Label
+PA11.GPIO_Label=USB_FS1_DM
+PA11.Locked=true
+PA11.Mode=Device_Only
+PA11.Signal=USB_OTG_FS_DM
+PA12.GPIOParameters=GPIO_Label
+PA12.GPIO_Label=USB_FS1_DP
+PA12.Locked=true
+PA12.Mode=Device_Only
+PA12.Signal=USB_OTG_FS_DP
+PA13\ (JTMS/SWDIO).Locked=true
+PA13\ (JTMS/SWDIO).Mode=Trace_Synchro_4bits_SW
+PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
+PA14\ (JTCK/SWCLK).Locked=true
+PA14\ (JTCK/SWCLK).Mode=Trace_Synchro_4bits_SW
+PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
+PA15\ (JTDI).GPIOParameters=GPIO_Label
+PA15\ (JTDI).GPIO_Label=TDI
+PA15\ (JTDI).Locked=true
+PA15\ (JTDI).Signal=DEBUG_JTDI
+PA2.GPIOParameters=GPIO_Label
+PA2.GPIO_Label=ETH_MDIO [LAN8742A_MDIO]
+PA2.Locked=true
+PA2.Signal=ETH_MDIO
+PA3.GPIOParameters=GPIO_Label
+PA3.GPIO_Label=ULPI_D0 [USB3320C_D0]
+PA3.Locked=true
+PA3.Mode=Device_HS
+PA3.Signal=USB_OTG_HS_ULPI_D0
+PA4.GPIOParameters=GPIO_Label
+PA4.GPIO_Label=LED3_RGB [LD3_Red]
+PA4.Locked=true
+PA4.Signal=GPIO_Output
+PA5.GPIOParameters=GPIO_Label
+PA5.GPIO_Label=ULPI_CK  [USB3320C_CLKOUT]
+PA5.Locked=true
+PA5.Mode=Device_HS
+PA5.Signal=USB_OTG_HS_ULPI_CK
+PA6.GPIOParameters=GPIO_Label
+PA6.GPIO_Label=LCD_BL_CTRL
+PA6.Locked=true
+PA6.Signal=GPIO_Output
+PA7.GPIOParameters=GPIO_Label
+PA7.GPIO_Label=RMII_CRS_DV [LAN8742A_CRS_DV]
+PA7.Locked=true
+PA7.Signal=ETH_CRS_DV
+PA8.GPIOParameters=GPIO_Label
+PA8.GPIO_Label=MCO
+PA8.Locked=true
+PA8.Signal=RCC_MCO_1
+PA9.GPIOParameters=GPIO_Label
+PA9.GPIO_Label=VBUS_FS1
+PA9.Locked=true
+PA9.Signal=USB_OTG_FS_VBUS
+PB0.GPIOParameters=GPIO_Label
+PB0.GPIO_Label=ULPI_D1 [USB3320C_D1]
+PB0.Locked=true
+PB0.Mode=Device_HS
+PB0.Signal=USB_OTG_HS_ULPI_D1
+PB1.GPIOParameters=GPIO_Label
+PB1.GPIO_Label=ULPI_D2 [USB3320C_D2]
+PB1.Locked=true
+PB1.Mode=Device_HS
+PB1.Signal=USB_OTG_HS_ULPI_D2
+PB10.GPIOParameters=GPIO_Label
+PB10.GPIO_Label=ULPI_D3 [USB3320C_D3]
+PB10.Locked=true
+PB10.Mode=Device_HS
+PB10.Signal=USB_OTG_HS_ULPI_D3
+PB11.GPIOParameters=GPIO_Label
+PB11.GPIO_Label=ULPI_D4 [USB3320C_D4]
+PB11.Locked=true
+PB11.Mode=Device_HS
+PB11.Signal=USB_OTG_HS_ULPI_D4
+PB12.GPIOParameters=GPIO_Label
+PB12.GPIO_Label=ULPI_D5 [USB3320C_D5]
+PB12.Locked=true
+PB12.Mode=Device_HS
+PB12.Signal=USB_OTG_HS_ULPI_D5
+PB13.GPIOParameters=GPIO_Label
+PB13.GPIO_Label=ULPI_D6 [USB3320C_D6]
+PB13.Locked=true
+PB13.Mode=Device_HS
+PB13.Signal=USB_OTG_HS_ULPI_D6
+PB14.GPIOParameters=GPIO_Label
+PB14.GPIO_Label=RS232_TX [ST3241EBPR_T2IN]
+PB14.Locked=true
+PB14.Signal=USART1_TX
+PB15.GPIOParameters=GPIO_Label
+PB15.GPIO_Label=RS_232RX [ST3241EBPR_R3OUT]
+PB15.Locked=true
+PB15.Signal=USART1_RX
+PB2.GPIOParameters=GPIO_Label
+PB2.GPIO_Label=QSPI_CLK [MT25TL01GHBA8ESF_CLK_1]
+PB2.Locked=true
+PB2.Signal=QUADSPI_CLK
+PB3\ (JTDO/TRACESWO).Locked=true
+PB3\ (JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO
+PB4\ (NJTRST).GPIOParameters=GPIO_Label
+PB4\ (NJTRST).GPIO_Label=TRST
+PB4\ (NJTRST).Locked=true
+PB4\ (NJTRST).Signal=DEBUG_JTRST
+PB5.GPIOParameters=GPIO_Label
+PB5.GPIO_Label=ULPI_D7 [USB3320C_D7]
+PB5.Locked=true
+PB5.Mode=Device_HS
+PB5.Signal=USB_OTG_HS_ULPI_D7
+PB6.GPIOParameters=GPIO_Label
+PB6.GPIO_Label=I2C1_SCL [STM32L152CCT6_I2C_SCL]
+PB6.Locked=true
+PB6.Signal=I2C1_SCL
+PB7.GPIOParameters=GPIO_Label
+PB7.GPIO_Label=I2C1_SDA [STM32L152CCT6_I2C_SDA]
+PB7.Locked=true
+PB7.Signal=I2C1_SDA
+PB8.GPIOParameters=GPIO_Label
+PB8.GPIO_Label=SDIO1_CKIN
+PB8.Locked=true
+PB8.Signal=SDMMC1_CKIN
+PB9.GPIOParameters=GPIO_Label
+PB9.GPIO_Label=SDIO1_CDIR
+PB9.Locked=true
+PB9.Signal=SDMMC1_CDIR
+PC0.GPIOParameters=GPIO_Label
+PC0.GPIO_Label=ULPI_STP [USB3320C_STP]
+PC0.Locked=true
+PC0.Mode=Device_HS
+PC0.Signal=USB_OTG_HS_ULPI_STP
+PC1.GPIOParameters=GPIO_Label
+PC1.GPIO_Label=RMII_MDC [LAN8742A_MDC]
+PC1.Locked=true
+PC1.Signal=ETH_MDC
+PC10.GPIOParameters=GPIO_Label
+PC10.GPIO_Label=SDIO1_D2
+PC10.Locked=true
+PC10.Signal=SDMMC1_D2
+PC11.GPIOParameters=GPIO_Label
+PC11.GPIO_Label=SDIO1_D3
+PC11.Locked=true
+PC11.Signal=SDMMC1_D3
+PC12.GPIOParameters=GPIO_Label
+PC12.GPIO_Label=SDIO1_CLK
+PC12.Locked=true
+PC12.Signal=SDMMC1_CK
+PC13.GPIOParameters=GPIO_Label
+PC13.GPIO_Label=TAMPER_KEY [B1]
+PC13.Locked=true
+PC13.Signal=RTC_TAMP1
+PC14-OSC32_IN\ (OSC32_IN).Locked=true
+PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN
+PC15-OSC32_OUT\ (OSC32_OUT).Locked=true
+PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT
+PC2.GPIOParameters=GPIO_Label
+PC2.GPIO_Label=DFSDM_CLK
+PC2.Locked=true
+PC2.Signal=S_CKOUTDFSDM1
+PC3.GPIOParameters=GPIO_Label
+PC3.GPIO_Label=DFSM_DAT1
+PC3.Locked=true
+PC3.Signal=S_DATAIN1DFSDM1
+PC4.GPIOParameters=GPIO_Label
+PC4.GPIO_Label=RMII_RXD0 [LAN8742A_RXD0]
+PC4.Locked=true
+PC4.Signal=ETH_RXD0
+PC5.GPIOParameters=GPIO_Label
+PC5.GPIO_Label=RMII_RXD1 [LAN8742A_RXD1]
+PC5.Locked=true
+PC5.Signal=ETH_RXD1
+PC6.GPIOParameters=GPIO_Label
+PC6.GPIO_Label=SDIO1_D0DIR
+PC6.Locked=true
+PC6.Signal=SDMMC1_D0DIR
+PC7.Locked=true
+PC7.Signal=DEBUG_TRGIO
+PC8.GPIOParameters=GPIO_Label
+PC8.GPIO_Label=SDIO1_D0
+PC8.Locked=true
+PC8.Signal=SDMMC1_D0
+PC9.GPIOParameters=GPIO_Label
+PC9.GPIO_Label=SDIO1_D1
+PC9.Locked=true
+PC9.Signal=SDMMC1_D1
+PD0.GPIOParameters=GPIO_Label
+PD0.GPIO_Label=D2 [IS42S32800G_DQ2]
+PD0.Locked=true
+PD0.Signal=FMC_D2_DA2
+PD1.GPIOParameters=GPIO_Label
+PD1.GPIO_Label=D3 [IS42S32800G_DQ3]
+PD1.Locked=true
+PD1.Signal=FMC_D3_DA3
+PD10.GPIOParameters=GPIO_Label
+PD10.GPIO_Label=D15 [IS42S32800G_DQ15]
+PD10.Locked=true
+PD10.Signal=FMC_D15_DA15
+PD11.GPIOParameters=GPIO_Label
+PD11.GPIO_Label=A16 [PC28F128M29EWLA_A16]
+PD11.Locked=true
+PD11.Signal=FMC_A16_CLE
+PD12.GPIOParameters=GPIO_Label
+PD12.GPIO_Label=A17 [PC28F128M29EWLA_A17]
+PD12.Locked=true
+PD12.Signal=FMC_A17_ALE
+PD13.GPIOParameters=GPIO_Label
+PD13.GPIO_Label=A18 [PC28F128M29EWLA_A18]
+PD13.Locked=true
+PD13.Signal=FMC_A18
+PD14.GPIOParameters=GPIO_Label
+PD14.GPIO_Label=D0 [IS42S32800G_DQ0]
+PD14.Locked=true
+PD14.Signal=FMC_D0_DA0
+PD15.GPIOParameters=GPIO_Label
+PD15.GPIO_Label=D1 [IS42S32800G_DQ1]
+PD15.Locked=true
+PD15.Signal=FMC_D1_DA1
+PD2.GPIOParameters=GPIO_Label
+PD2.GPIO_Label=SDIO1_CMD
+PD2.Locked=true
+PD2.Signal=SDMMC1_CMD
+PD3.GPIOParameters=GPIO_Label
+PD3.GPIO_Label=FDCAN1_STBY [MCP2562FD_STBY]
+PD3.Locked=true
+PD3.Signal=GPIO_Output
+PD4.GPIOParameters=GPIO_Label
+PD4.GPIO_Label=FMC_NOE [IS61WV102416BLL_OE]
+PD4.Locked=true
+PD4.Signal=FMC_NOE
+PD5.GPIOParameters=GPIO_Label
+PD5.GPIO_Label=FMC_NWE [IS61WV102416BLL_WE]
+PD5.Locked=true
+PD5.Signal=FMC_NWE
+PD6.GPIOParameters=GPIO_Label
+PD6.GPIO_Label=FMC_NWAIT [PC28F128M29EWLA_RB]
+PD6.Locked=true
+PD6.Signal=FMC_NWAIT
+PD7.GPIOParameters=GPIO_Label
+PD7.GPIO_Label=FMC_NE1 [PC28F128M29EWLA_E]
+PD7.Locked=true
+PD7.Signal=FMC_NE1
+PD8.GPIOParameters=GPIO_Label
+PD8.GPIO_Label=D13 [IS42S32800G_DQ13]
+PD8.Locked=true
+PD8.Signal=FMC_D13_DA13
+PD9.GPIOParameters=GPIO_Label
+PD9.GPIO_Label=D14 [IS42S32800G_DQ14]
+PD9.Locked=true
+PD9.Signal=FMC_D14_DA14
+PE0.GPIOParameters=GPIO_Label
+PE0.GPIO_Label=FMC_NBL0 [IS42S32800G_DQM0]
+PE0.Locked=true
+PE0.Signal=FMC_NBL0
+PE1.GPIOParameters=GPIO_Label
+PE1.GPIO_Label=FMC_NBL1 [IS42S32800G_DQM1]
+PE1.Locked=true
+PE1.Signal=FMC_NBL1
+PE10.GPIOParameters=GPIO_Label
+PE10.GPIO_Label=D7 [IS42S32800G_DQ7]
+PE10.Locked=true
+PE10.Signal=FMC_D7_DA7
+PE11.GPIOParameters=GPIO_Label
+PE11.GPIO_Label=D8 [IS42S32800G_DQ8]
+PE11.Locked=true
+PE11.Signal=FMC_D8_DA8
+PE12.GPIOParameters=GPIO_Label
+PE12.GPIO_Label=D9 [IS42S32800G_DQ9]
+PE12.Locked=true
+PE12.Signal=FMC_D9_DA9
+PE13.GPIOParameters=GPIO_Label
+PE13.GPIO_Label=D10 [IS42S32800G_DQ10]
+PE13.Locked=true
+PE13.Signal=FMC_D10_DA10
+PE14.GPIOParameters=GPIO_Label
+PE14.GPIO_Label=D11 [IS42S32800G_DQ11]
+PE14.Locked=true
+PE14.Signal=FMC_D11_DA11
+PE15.GPIOParameters=GPIO_Label
+PE15.GPIO_Label=D12 [IS42S32800G_DQ12]
+PE15.Locked=true
+PE15.Signal=FMC_D12_DA12
+PE2.Locked=true
+PE2.Mode=Trace_Synchro_4bits_SW
+PE2.Signal=DEBUG_TRACECLK
+PE3.Locked=true
+PE3.Mode=Trace_Synchro_4bits_SW
+PE3.Signal=DEBUG_TRACED0
+PE4.Locked=true
+PE4.Mode=Trace_Synchro_4bits_SW
+PE4.Signal=DEBUG_TRACED1
+PE5.Locked=true
+PE5.Mode=Trace_Synchro_4bits_SW
+PE5.Signal=DEBUG_TRACED2
+PE6.Locked=true
+PE6.Mode=Trace_Synchro_4bits_SW
+PE6.Signal=DEBUG_TRACED3
+PE7.GPIOParameters=GPIO_Label
+PE7.GPIO_Label=D4 [IS42S32800G_DQ4]
+PE7.Locked=true
+PE7.Signal=FMC_D4_DA4
+PE8.GPIOParameters=GPIO_Label
+PE8.GPIO_Label=D5 [IS42S32800G_DQ5]
+PE8.Locked=true
+PE8.Signal=FMC_D5_DA5
+PE9.GPIOParameters=GPIO_Label
+PE9.GPIO_Label=D6 [IS42S32800G_DQ6]
+PE9.Locked=true
+PE9.Signal=FMC_D6_DA6
+PF0.GPIOParameters=GPIO_Label
+PF0.GPIO_Label=A0 [PC28F128M29EWLA_A0]
+PF0.Locked=true
+PF0.Signal=FMC_A0
+PF1.GPIOParameters=GPIO_Label
+PF1.GPIO_Label=A1 [PC28F128M29EWLA_A1]
+PF1.Locked=true
+PF1.Signal=FMC_A1
+PF10.GPIOParameters=GPIO_Label
+PF10.GPIO_Label=LED1_RGB [LD1_Green]
+PF10.Locked=true
+PF10.Signal=GPIO_Output
+PF11.GPIOParameters=GPIO_Label
+PF11.GPIO_Label=SNDRAS [IS42S32800G_RAS]
+PF11.Locked=true
+PF11.Signal=FMC_SDNRAS
+PF12.GPIOParameters=GPIO_Label
+PF12.GPIO_Label=A6 [PC28F128M29EWLA_A6]
+PF12.Locked=true
+PF12.Signal=FMC_A6
+PF13.GPIOParameters=GPIO_Label
+PF13.GPIO_Label=A7 [PC28F128M29EWLA_A7]
+PF13.Locked=true
+PF13.Signal=FMC_A7
+PF14.GPIOParameters=GPIO_Label
+PF14.GPIO_Label=A8 [PC28F128M29EWLA_A8]
+PF14.Locked=true
+PF14.Signal=FMC_A8
+PF15.GPIOParameters=GPIO_Label
+PF15.GPIO_Label=A9 [PC28F128M29EWLA_A9]
+PF15.Locked=true
+PF15.Signal=FMC_A9
+PF2.GPIOParameters=GPIO_Label
+PF2.GPIO_Label=A2 [PC28F128M29EWLA_A2]
+PF2.Locked=true
+PF2.Signal=FMC_A2
+PF3.GPIOParameters=GPIO_Label
+PF3.GPIO_Label=A3 [PC28F128M29EWLA_A3]
+PF3.Locked=true
+PF3.Signal=FMC_A3
+PF4.GPIOParameters=GPIO_Label
+PF4.GPIO_Label=A4 [PC28F128M29EWLA_A4]
+PF4.Locked=true
+PF4.Signal=FMC_A4
+PF5.GPIOParameters=GPIO_Label
+PF5.GPIO_Label=A5 [PC28F128M29EWLA_A5]
+PF5.Locked=true
+PF5.Signal=FMC_A5
+PF6.GPIOParameters=GPIO_Label
+PF6.GPIO_Label=QSPI_BK1_IO3 [MT25TL01GHBA8ESF_DQ3]
+PF6.Locked=true
+PF6.Signal=QUADSPI_BK1_IO3
+PF7.GPIOParameters=GPIO_Label
+PF7.GPIO_Label=QSPI_BK1_IO2 [MT25TL01GHBA8ESF_DQ2]
+PF7.Locked=true
+PF7.Signal=QUADSPI_BK1_IO2
+PF8.GPIOParameters=GPIO_Label
+PF8.GPIO_Label=QSPI_BK1_IO0 [MT25TL01GHBA8ESF_DQ0]
+PF8.Locked=true
+PF8.Signal=QUADSPI_BK1_IO0
+PF9.GPIOParameters=GPIO_Label
+PF9.GPIO_Label=QSPI_BK1_IO1 [MT25TL01GHBA8ESF_DQ1]
+PF9.Locked=true
+PF9.Signal=QUADSPI_BK1_IO1
+PG0.GPIOParameters=GPIO_Label
+PG0.GPIO_Label=A10 [PC28F128M29EWLA_A10]
+PG0.Locked=true
+PG0.Signal=FMC_A10
+PG1.GPIOParameters=GPIO_Label
+PG1.GPIO_Label=A11 [PC28F128M29EWLA_A11]
+PG1.Locked=true
+PG1.Signal=FMC_A11
+PG10.GPIOParameters=GPIO_Label
+PG10.GPIO_Label=FMC_NE3 [IS61WV102416BLL_CE]
+PG10.Locked=true
+PG10.Signal=FMC_NE3
+PG11.GPIOParameters=GPIO_Label
+PG11.GPIO_Label=RMII_TX_EN [LAN8742A_TXEN]
+PG11.Locked=true
+PG11.Signal=ETH_TX_EN
+PG12.GPIOParameters=GPIO_Label
+PG12.GPIO_Label=RMII_TXD1 [LAN8742A_TXD1]
+PG12.Locked=true
+PG12.Signal=ETH_TXD1
+PG13.GPIOParameters=GPIO_Label
+PG13.GPIO_Label=RMII_TXD0 [LAN8742A_TXD0]
+PG13.Locked=true
+PG13.Signal=ETH_TXD0
+PG14.GPIOParameters=GPIO_Label
+PG14.GPIO_Label=QSPI_BK2_IO3 [MT25TL01GHBA8ESF_DQ7]
+PG14.Locked=true
+PG14.Signal=QUADSPI_BK2_IO3
+PG15.GPIOParameters=GPIO_Label
+PG15.GPIO_Label=SDNCAS [IS42S32800G_CAS]
+PG15.Locked=true
+PG15.Signal=FMC_SDNCAS
+PG2.GPIOParameters=GPIO_Label
+PG2.GPIO_Label=A12 [PC28F128M29EWLA_A12]
+PG2.Locked=true
+PG2.Signal=FMC_A12
+PG3.GPIOParameters=GPIO_Label
+PG3.GPIO_Label=A13 [PC28F128M29EWLA_A13]
+PG3.Locked=true
+PG3.Signal=FMC_A13
+PG4.Locked=true
+PG4.Signal=FMC_A14_BA0
+PG5.Locked=true
+PG5.Signal=FMC_A15_BA1
+PG6.GPIOParameters=GPIO_Label
+PG6.GPIO_Label=QSPI_BK1_NCS [MT25TL01GHBA8ESF_CS]
+PG6.Locked=true
+PG6.Signal=QUADSPI_BK1_NCS
+PG7.GPIOParameters=GPIO_Label
+PG7.GPIO_Label=SAI1_MCLKA [WM8994ECS_MCLK1]
+PG7.Locked=true
+PG7.Signal=SAI1_MCLK_A
+PG8.GPIOParameters=GPIO_Label
+PG8.GPIO_Label=SDCLK [IS42S32800G_CLK]
+PG8.Locked=true
+PG8.Signal=FMC_SDCLK
+PG9.GPIOParameters=GPIO_Label
+PG9.GPIO_Label=QSPI_BK2_IO2 [MT25TL01GHBA8ESF_DQ6]
+PG9.Locked=true
+PG9.Signal=QUADSPI_BK2_IO2
+PH0-OSC_IN\ (PH0).Locked=true
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
+PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
+PH1-OSC_OUT\ (PH1).Locked=true
+PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
+PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
+PH10.GPIOParameters=GPIO_Label
+PH10.GPIO_Label=D18 [IS42S32800G_DQ18]
+PH10.Locked=true
+PH10.Signal=FMC_D18
+PH11.GPIOParameters=GPIO_Label
+PH11.GPIO_Label=D19 [IS42S32800G_DQ19]
+PH11.Locked=true
+PH11.Signal=FMC_D19
+PH12.GPIOParameters=GPIO_Label
+PH12.GPIO_Label=D20 [IS42S32800G_DQ20]
+PH12.Locked=true
+PH12.Signal=FMC_D20
+PH13.GPIOParameters=GPIO_Label
+PH13.GPIO_Label=D21 [IS42S32800G_DQ21]
+PH13.Locked=true
+PH13.Signal=FMC_D21
+PH14.GPIOParameters=GPIO_Label
+PH14.GPIO_Label=D22 [IS42S32800G_DQ22]
+PH14.Locked=true
+PH14.Signal=FMC_D22
+PH15.GPIOParameters=GPIO_Label
+PH15.GPIO_Label=D23 [IS42S32800G_DQ23]
+PH15.Locked=true
+PH15.Signal=FMC_D23
+PH2.GPIOParameters=GPIO_Label
+PH2.GPIO_Label=QSPI_BK2_IO0 [MT25TL01GHBA8ESF_DQ4]
+PH2.Locked=true
+PH2.Signal=QUADSPI_BK2_IO0
+PH3.GPIOParameters=GPIO_Label
+PH3.GPIO_Label=QSPI_BK2_IO1 [MT25TL01GHBA8ESF_DQ5]
+PH3.Locked=true
+PH3.Signal=QUADSPI_BK2_IO1
+PH4.GPIOParameters=GPIO_Label
+PH4.GPIO_Label=ULPI_NXT [USB3320C_NXT]
+PH4.Locked=true
+PH4.Mode=Device_HS
+PH4.Signal=USB_OTG_HS_ULPI_NXT
+PH5.GPIOParameters=GPIO_Label
+PH5.GPIO_Label=SDNWE [IS42S32800G_WE]
+PH5.Locked=true
+PH5.Signal=FMC_SDNWE
+PH6.GPIOParameters=GPIO_Label
+PH6.GPIO_Label=SDNE1 [IS42S32800G_CS]
+PH6.Locked=true
+PH6.Signal=FMC_SDNE1
+PH7.GPIOParameters=GPIO_Label
+PH7.GPIO_Label=SDCKE1 [IS42S32800G_CKE]
+PH7.Locked=true
+PH7.Signal=FMC_SDCKE1
+PH8.GPIOParameters=GPIO_Label
+PH8.GPIO_Label=D16 [IS42S32800G_DQ16]
+PH8.Locked=true
+PH8.Signal=FMC_D16
+PH9.GPIOParameters=GPIO_Label
+PH9.GPIO_Label=D17 [IS42S32800G_DQ17]
+PH9.Locked=true
+PH9.Signal=FMC_D17
+PI0.GPIOParameters=GPIO_Label
+PI0.GPIO_Label=D24 [IS42S32800G_DQ24]
+PI0.Locked=true
+PI0.Signal=FMC_D24
+PI1.GPIOParameters=GPIO_Label
+PI1.GPIO_Label=D25 [IS42S32800G_DQ25]
+PI1.Locked=true
+PI1.Signal=FMC_D25
+PI10.GPIOParameters=GPIO_Label
+PI10.GPIO_Label=D31 [IS42S32800G_DQ31]
+PI10.Locked=true
+PI10.Signal=FMC_D31
+PI11.GPIOParameters=GPIO_Label
+PI11.GPIO_Label=ULPI_DIR [USB3320C_DIR]
+PI11.Locked=true
+PI11.Mode=Device_HS
+PI11.Signal=USB_OTG_HS_ULPI_DIR
+PI12.GPIOParameters=GPIO_Label
+PI12.GPIO_Label=LCD_HSYNC
+PI12.Locked=true
+PI12.Signal=LTDC_HSYNC
+PI13.GPIOParameters=GPIO_Label
+PI13.GPIO_Label=LCD_VSYNC
+PI13.Locked=true
+PI13.Signal=LTDC_VSYNC
+PI14.GPIOParameters=GPIO_Label
+PI14.GPIO_Label=LCD_CLK
+PI14.Locked=true
+PI14.Signal=LTDC_CLK
+PI15.GPIOParameters=GPIO_Label
+PI15.GPIO_Label=LCD_R0
+PI15.Locked=true
+PI15.Signal=LTDC_R0
+PI2.GPIOParameters=GPIO_Label
+PI2.GPIO_Label=D26 [IS42S32800G_DQ26]
+PI2.Locked=true
+PI2.Signal=FMC_D26
+PI3.GPIOParameters=GPIO_Label
+PI3.GPIO_Label=D27 [IS42S32800G_DQ27
+PI3.Locked=true
+PI3.Signal=FMC_D27
+PI4.GPIOParameters=GPIO_Label
+PI4.GPIO_Label=FMC_NBL2 [IS42S32800G_DQM2]
+PI4.Locked=true
+PI4.Signal=FMC_NBL2
+PI5.GPIOParameters=GPIO_Label
+PI5.GPIO_Label=FMC_NBL3 [IS42S32800G_DQM3]
+PI5.Locked=true
+PI5.Signal=FMC_NBL3
+PI6.GPIOParameters=GPIO_Label
+PI6.GPIO_Label=D28 [IS42S32800G_DQ28]
+PI6.Locked=true
+PI6.Signal=FMC_D28
+PI7.GPIOParameters=GPIO_Label
+PI7.GPIO_Label=D29 [IS42S32800G_DQ29]
+PI7.Locked=true
+PI7.Signal=FMC_D29
+PI8.GPIOParameters=GPIO_Label
+PI8.GPIO_Label=MFX_IRQOUT [MFX_V3_IRQOUT]
+PI8.Locked=true
+PI8.Signal=GPXTI8
+PI9.GPIOParameters=GPIO_Label
+PI9.GPIO_Label=D30 [IS42S32800G_DQ30]
+PI9.Locked=true
+PI9.Signal=FMC_D30
+PJ0.GPIOParameters=GPIO_Label
+PJ0.GPIO_Label=LCD_R1
+PJ0.Locked=true
+PJ0.Signal=LTDC_R1
+PJ1.GPIOParameters=GPIO_Label
+PJ1.GPIO_Label=LCD_R2
+PJ1.Locked=true
+PJ1.Signal=LTDC_R2
+PJ10.GPIOParameters=GPIO_Label
+PJ10.GPIO_Label=LCd_G3
+PJ10.Locked=true
+PJ10.Signal=LTDC_G3
+PJ11.GPIOParameters=GPIO_Label
+PJ11.GPIO_Label=LCD_G4
+PJ11.Locked=true
+PJ11.Signal=LTDC_G4
+PJ12.Locked=true
+PJ12.Signal=DEBUG_TRGOUT
+PJ13.GPIOParameters=GPIO_Label
+PJ13.GPIO_Label=LCD_B1
+PJ13.Locked=true
+PJ13.Signal=LTDC_B1
+PJ14.GPIOParameters=GPIO_Label
+PJ14.GPIO_Label=LCD_B2
+PJ14.Locked=true
+PJ14.Signal=LTDC_B2
+PJ15.GPIOParameters=GPIO_Label
+PJ15.GPIO_Label=LCD_B3
+PJ15.Locked=true
+PJ15.Signal=LTDC_B3
+PJ2.GPIOParameters=GPIO_Label
+PJ2.GPIO_Label=LCD_R3
+PJ2.Locked=true
+PJ2.Signal=LTDC_R3
+PJ3.GPIOParameters=GPIO_Label
+PJ3.GPIO_Label=LCD_R4
+PJ3.Locked=true
+PJ3.Signal=LTDC_R4
+PJ4.GPIOParameters=GPIO_Label
+PJ4.GPIO_Label=LCD_R5
+PJ4.Locked=true
+PJ4.Signal=LTDC_R5
+PJ5.GPIOParameters=GPIO_Label
+PJ5.GPIO_Label=LCD_R6
+PJ5.Locked=true
+PJ5.Signal=LTDC_R6
+PJ6.GPIOParameters=GPIO_Label
+PJ6.GPIO_Label=LCD_R7
+PJ6.Locked=true
+PJ6.Signal=LTDC_R7
+PJ7.Locked=true
+PJ7.Signal=DEBUG_TRGIN
+PJ8.GPIOParameters=GPIO_Label
+PJ8.GPIO_Label=LCD_G1
+PJ8.Locked=true
+PJ8.Signal=LTDC_G1
+PJ9.GPIOParameters=GPIO_Label
+PJ9.GPIO_Label=LCD_G2
+PJ9.Locked=true
+PJ9.Signal=LTDC_G2
+PK0.GPIOParameters=GPIO_Label
+PK0.GPIO_Label=LCD_G5
+PK0.Locked=true
+PK0.Signal=LTDC_G5
+PK1.GPIOParameters=GPIO_Label
+PK1.GPIO_Label=LCD_G6
+PK1.Locked=true
+PK1.Signal=LTDC_G6
+PK2.GPIOParameters=GPIO_Label
+PK2.GPIO_Label=LCD_G7
+PK2.Locked=true
+PK2.Signal=LTDC_G7
+PK3.GPIOParameters=GPIO_Label
+PK3.GPIO_Label=LCD_B4
+PK3.Locked=true
+PK3.Signal=LTDC_B4
+PK4.GPIOParameters=GPIO_Label
+PK4.GPIO_Label=LCD_B5
+PK4.Locked=true
+PK4.Signal=LTDC_B5
+PK5.GPIOParameters=GPIO_Label
+PK5.GPIO_Label=LCD_B6
+PK5.Locked=true
+PK5.Signal=LTDC_B6
+PK6.GPIOParameters=GPIO_Label
+PK6.GPIO_Label=LCD_B7
+PK6.Locked=true
+PK6.Signal=LTDC_B7
+PK7.GPIOParameters=GPIO_Label
+PK7.GPIO_Label=LCD_DE
+PK7.Locked=true
+PK7.Signal=LTDC_DE
+PinOutPanel.CurrentBGAView=Top
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32H743XIHx
+ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=stm32h743eval.ioc
+ProjectManager.ProjectName=stm32h743eval
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=Makefile
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,4-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+RCC.ADCFreq_Value=50390625
+RCC.AHB12Freq_Value=150000000
+RCC.AHB4Freq_Value=150000000
+RCC.APB1Freq_Value=75000000
+RCC.APB2Freq_Value=75000000
+RCC.APB3Freq_Value=75000000
+RCC.APB4Freq_Value=75000000
+RCC.AXIClockFreq_Value=150000000
+RCC.CECFreq_Value=32000
+RCC.CKPERFreq_Value=64000000
+RCC.CortexFreq_Value=150000000
+RCC.CpuClockFreq_Value=150000000
+RCC.D1CPREFreq_Value=150000000
+RCC.D1PPRE=RCC_APB3_DIV2
+RCC.D2PPRE1=RCC_APB1_DIV2
+RCC.D2PPRE2=RCC_APB2_DIV2
+RCC.D3PPRE=RCC_APB4_DIV2
+RCC.DFSDMACLkFreq_Value=75000000
+RCC.DFSDMFreq_Value=75000000
+RCC.DIVM1=2
+RCC.DIVM3=25
+RCC.DIVN1=24
+RCC.DIVN3=336
+RCC.DIVP1Freq_Value=150000000
+RCC.DIVP2Freq_Value=50390625
+RCC.DIVP3Freq_Value=168000000
+RCC.DIVQ1=4
+RCC.DIVQ1Freq_Value=75000000
+RCC.DIVQ2Freq_Value=50390625
+RCC.DIVQ3=7
+RCC.DIVQ3Freq_Value=48000000
+RCC.DIVR1Freq_Value=150000000
+RCC.DIVR2Freq_Value=50390625
+RCC.DIVR3Freq_Value=168000000
+RCC.EnbaleCSS=true
+RCC.FDCANFreq_Value=75000000
+RCC.FMCFreq_Value=150000000
+RCC.FamilyName=M
+RCC.HCLK3ClockFreq_Value=150000000
+RCC.HCLKFreq_Value=150000000
+RCC.HPREFreq_Value=64000000
+RCC.HRTIMFreq_Value=150000000
+RCC.HSICalibrationValue=32
+RCC.I2C123Freq_Value=75000000
+RCC.I2C4Freq_Value=75000000
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPREFreq_Value,HRTIMFreq_Value,HSICalibrationValue,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.LPTIM1Freq_Value=75000000
+RCC.LPTIM2Freq_Value=75000000
+RCC.LPTIM345Freq_Value=75000000
+RCC.LPUART1Freq_Value=75000000
+RCC.LTDCFreq_Value=168000000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=150000000
+RCC.PLL2FRACN=0
+RCC.PLL3FRACN=0
+RCC.PLLFRACN=0
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1
+RCC.QSPIFreq_Value=150000000
+RCC.RNGFreq_Value=48000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=75000000
+RCC.SAI23Freq_Value=75000000
+RCC.SAI4AFreq_Value=75000000
+RCC.SAI4BFreq_Value=75000000
+RCC.SDMMCFreq_Value=75000000
+RCC.SPDIFRXFreq_Value=75000000
+RCC.SPI123Freq_Value=75000000
+RCC.SPI45Freq_Value=75000000
+RCC.SPI6Freq_Value=75000000
+RCC.SWPMI1Freq_Value=75000000
+RCC.SYSCLKFreq_VALUE=150000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.Tim1OutputFreq_Value=150000000
+RCC.Tim2OutputFreq_Value=150000000
+RCC.TraceFreq_Value=150000000
+RCC.USART16Freq_Value=75000000
+RCC.USART234578Freq_Value=75000000
+RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3
+RCC.USBFreq_Value=48000000
+RCC.VCO1OutputFreq_Value=300000000
+RCC.VCO2OutputFreq_Value=100781250
+RCC.VCO3OutputFreq_Value=336000000
+RCC.VCOInput1Freq_Value=12500000
+RCC.VCOInput2Freq_Value=781250
+RCC.VCOInput3Freq_Value=1000000
+SH.ADCx_INN1.0=ADC1_INN1
+SH.ADCx_INN1.ConfNb=1
+SH.FMC_A0.0=FMC_A0
+SH.FMC_A0.ConfNb=1
+SH.FMC_A1.0=FMC_A1
+SH.FMC_A1.ConfNb=1
+SH.FMC_A10.0=FMC_A10
+SH.FMC_A10.ConfNb=1
+SH.FMC_A11.0=FMC_A11
+SH.FMC_A11.ConfNb=1
+SH.FMC_A12.0=FMC_A12
+SH.FMC_A12.ConfNb=1
+SH.FMC_A13.0=FMC_A13
+SH.FMC_A13.ConfNb=1
+SH.FMC_A14_BA0.0=FMC_BA0
+SH.FMC_A14_BA0.1=FMC_A14
+SH.FMC_A14_BA0.ConfNb=2
+SH.FMC_A15_BA1.0=FMC_BA1
+SH.FMC_A15_BA1.1=FMC_A15
+SH.FMC_A15_BA1.ConfNb=2
+SH.FMC_A16_CLE.0=FMC_A16
+SH.FMC_A16_CLE.ConfNb=1
+SH.FMC_A17_ALE.0=FMC_A17
+SH.FMC_A17_ALE.ConfNb=1
+SH.FMC_A18.0=FMC_A18
+SH.FMC_A18.ConfNb=1
+SH.FMC_A2.0=FMC_A2
+SH.FMC_A2.ConfNb=1
+SH.FMC_A3.0=FMC_A3
+SH.FMC_A3.ConfNb=1
+SH.FMC_A4.0=FMC_A4
+SH.FMC_A4.ConfNb=1
+SH.FMC_A5.0=FMC_A5
+SH.FMC_A5.ConfNb=1
+SH.FMC_A6.0=FMC_A6
+SH.FMC_A6.ConfNb=1
+SH.FMC_A7.0=FMC_A7
+SH.FMC_A7.ConfNb=1
+SH.FMC_A8.0=FMC_A8
+SH.FMC_A8.ConfNb=1
+SH.FMC_A9.0=FMC_A9
+SH.FMC_A9.ConfNb=1
+SH.FMC_D0_DA0.0=FMC_D0
+SH.FMC_D0_DA0.ConfNb=1
+SH.FMC_D10_DA10.0=FMC_D10
+SH.FMC_D10_DA10.ConfNb=1
+SH.FMC_D11_DA11.0=FMC_D11
+SH.FMC_D11_DA11.ConfNb=1
+SH.FMC_D12_DA12.0=FMC_D12
+SH.FMC_D12_DA12.ConfNb=1
+SH.FMC_D13_DA13.0=FMC_D13
+SH.FMC_D13_DA13.ConfNb=1
+SH.FMC_D14_DA14.0=FMC_D14
+SH.FMC_D14_DA14.ConfNb=1
+SH.FMC_D15_DA15.0=FMC_D15
+SH.FMC_D15_DA15.ConfNb=1
+SH.FMC_D16.0=FMC_D16
+SH.FMC_D16.ConfNb=1
+SH.FMC_D17.0=FMC_D17
+SH.FMC_D17.ConfNb=1
+SH.FMC_D18.0=FMC_D18
+SH.FMC_D18.ConfNb=1
+SH.FMC_D19.0=FMC_D19
+SH.FMC_D19.ConfNb=1
+SH.FMC_D1_DA1.0=FMC_D1
+SH.FMC_D1_DA1.ConfNb=1
+SH.FMC_D20.0=FMC_D20
+SH.FMC_D20.ConfNb=1
+SH.FMC_D21.0=FMC_D21
+SH.FMC_D21.ConfNb=1
+SH.FMC_D22.0=FMC_D22
+SH.FMC_D22.ConfNb=1
+SH.FMC_D23.0=FMC_D23
+SH.FMC_D23.ConfNb=1
+SH.FMC_D24.0=FMC_D24
+SH.FMC_D24.ConfNb=1
+SH.FMC_D25.0=FMC_D25
+SH.FMC_D25.ConfNb=1
+SH.FMC_D26.0=FMC_D26
+SH.FMC_D26.ConfNb=1
+SH.FMC_D27.0=FMC_D27
+SH.FMC_D27.ConfNb=1
+SH.FMC_D28.0=FMC_D28
+SH.FMC_D28.ConfNb=1
+SH.FMC_D29.0=FMC_D29
+SH.FMC_D29.ConfNb=1
+SH.FMC_D2_DA2.0=FMC_D2
+SH.FMC_D2_DA2.ConfNb=1
+SH.FMC_D30.0=FMC_D30
+SH.FMC_D30.ConfNb=1
+SH.FMC_D31.0=FMC_D31
+SH.FMC_D31.ConfNb=1
+SH.FMC_D3_DA3.0=FMC_D3
+SH.FMC_D3_DA3.ConfNb=1
+SH.FMC_D4_DA4.0=FMC_D4
+SH.FMC_D4_DA4.ConfNb=1
+SH.FMC_D5_DA5.0=FMC_D5
+SH.FMC_D5_DA5.ConfNb=1
+SH.FMC_D6_DA6.0=FMC_D6
+SH.FMC_D6_DA6.ConfNb=1
+SH.FMC_D7_DA7.0=FMC_D7
+SH.FMC_D7_DA7.ConfNb=1
+SH.FMC_D8_DA8.0=FMC_D8
+SH.FMC_D8_DA8.ConfNb=1
+SH.FMC_D9_DA9.0=FMC_D9
+SH.FMC_D9_DA9.ConfNb=1
+SH.FMC_NBL0.0=FMC_NBL0
+SH.FMC_NBL0.ConfNb=1
+SH.FMC_NBL1.0=FMC_NBL1
+SH.FMC_NBL1.ConfNb=1
+SH.FMC_NBL2.0=FMC_NBL2
+SH.FMC_NBL2.ConfNb=1
+SH.FMC_NBL3.0=FMC_NBL3
+SH.FMC_NBL3.ConfNb=1
+SH.FMC_NOE.0=FMC_NOE
+SH.FMC_NOE.ConfNb=1
+SH.FMC_NWAIT.0=FMC_NWAIT
+SH.FMC_NWAIT.ConfNb=1
+SH.FMC_NWE.0=FMC_NWE
+SH.FMC_NWE.ConfNb=1
+SH.FMC_SDCLK.0=FMC_SDCLK
+SH.FMC_SDCLK.ConfNb=1
+SH.FMC_SDNCAS.0=FMC_SDNCAS
+SH.FMC_SDNCAS.ConfNb=1
+SH.FMC_SDNRAS.0=FMC_SDNRAS
+SH.FMC_SDNRAS.ConfNb=1
+SH.FMC_SDNWE.0=FMC_SDNWE
+SH.FMC_SDNWE.ConfNb=1
+SH.GPXTI8.0=GPIO_EXTI8
+SH.GPXTI8.ConfNb=1
+SH.S_CKOUTDFSDM1.0=DFSDM1_CKOUT
+SH.S_CKOUTDFSDM1.ConfNb=1
+SH.S_DATAIN1DFSDM1.0=DFSDM1_DATIN1
+SH.S_DATAIN1DFSDM1.ConfNb=1
+USB_OTG_FS.IPParameters=VirtualMode
+USB_OTG_FS.VirtualMode=Device_Only
+USB_OTG_HS.IPParameters=VirtualMode-Device_HS
+USB_OTG_HS.VirtualMode-Device_HS=Device_HS
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=STM32H743I-EVAL2
+boardIOC=true
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/h743eval.jdebug b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/h743eval.jdebug
new file mode 100644
index 000000000..093951765
--- /dev/null
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/h743eval.jdebug
@@ -0,0 +1,249 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  //
+  // Dialog-generated settings
+  //
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd");
+  Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd");
+  Project.AddSvdFile ("./STM32H743.svd");
+
+  Project.SetDevice ("STM32H743XI");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+
+  //
+  // User settings
+  //
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTraceTiming (100, 100, 100, 100);
+  Edit.SysVar (VAR_TRACE_CORE_CLOCK, 150000000);
+  File.Open ("/home/hathach/code/tinyusb/examples/device/cdc_msc/cmake-build-h743eval/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging a RAM program on a Cortex-M target device
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  Exec.Reset();
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//
+//    Util.Log("Resetting Program.");
+//
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+
+void BeforeTargetConnect (void) {
+  //
+  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+  //
+  //Project.SetJLinkScript("./ST_STM32H743_Traceconfig.pex");
+}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+  Util.Log("___");
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 35b2cd55b..7e0469bd8 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -56,6 +56,30 @@ void OTG_HS_IRQHandler(void)
 
 UART_HandleTypeDef UartHandle;
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+#ifdef TRACE_ETM
+void trace_etm_init(void) {
+  // H7 trace pin is PE2 to PE6
+  // __HAL_RCC_GPIOE_CLK_ENABLE();
+
+  GPIO_InitTypeDef  gpio_init;
+  gpio_init.Pin       = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6;
+  gpio_init.Mode      = GPIO_MODE_AF_PP;
+  gpio_init.Pull      = GPIO_PULLUP;
+  gpio_init.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
+  gpio_init.Alternate = GPIO_AF0_TRACE;
+  HAL_GPIO_Init(GPIOE, &gpio_init);
+
+  // Enable trace clk, also in D1 and D3 domain
+  DBGMCU->CR |= DBGMCU_CR_DBG_TRACECKEN | DBGMCU_CR_DBG_CKD1EN | DBGMCU_CR_DBG_CKD3EN;
+}
+#else
+  #define etm_trace_init()
+#endif
+
 void board_init(void)
 {
   board_stm32h7_clock_init();
@@ -74,6 +98,8 @@ void board_init(void)
 #endif
   __HAL_RCC_GPIOJ_CLK_ENABLE();
 
+  trace_etm_init();
+
   // Enable UART Clock
   UART_CLK_EN();
 

From 3d685fe7f2f383b10a2ed86d33d4b97781843f0d Mon Sep 17 00:00:00 2001
From: Angel Molina <angelmolinu@gmail.com>
Date: Fri, 21 Oct 2022 19:35:15 +0200
Subject: [PATCH 1820/2085] Add CDC+UAC2 composite device example for Pico

Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
---
 examples/device/cdc_uac2/CMakeLists.txt       |  38 +++
 examples/device/cdc_uac2/README.md            |  52 +++
 examples/device/cdc_uac2/skip.txt             |  52 +++
 examples/device/cdc_uac2/src/common.h         |  34 ++
 examples/device/cdc_uac2/src/main.c           |  99 ++++++
 examples/device/cdc_uac2/src/tusb_cdc.c       |  72 ++++
 examples/device/cdc_uac2/src/tusb_config.h    | 174 ++++++++++
 examples/device/cdc_uac2/src/tusb_uac2.c      | 316 ++++++++++++++++++
 .../device/cdc_uac2/src/usb_descriptors.c     | 190 +++++++++++
 .../device/cdc_uac2/src/usb_descriptors.h     | 158 +++++++++
 10 files changed, 1185 insertions(+)
 create mode 100644 examples/device/cdc_uac2/CMakeLists.txt
 create mode 100644 examples/device/cdc_uac2/README.md
 create mode 100644 examples/device/cdc_uac2/skip.txt
 create mode 100644 examples/device/cdc_uac2/src/common.h
 create mode 100644 examples/device/cdc_uac2/src/main.c
 create mode 100644 examples/device/cdc_uac2/src/tusb_cdc.c
 create mode 100644 examples/device/cdc_uac2/src/tusb_config.h
 create mode 100644 examples/device/cdc_uac2/src/tusb_uac2.c
 create mode 100644 examples/device/cdc_uac2/src/usb_descriptors.c
 create mode 100644 examples/device/cdc_uac2/src/usb_descriptors.h

diff --git a/examples/device/cdc_uac2/CMakeLists.txt b/examples/device/cdc_uac2/CMakeLists.txt
new file mode 100644
index 000000000..efe8c74ba
--- /dev/null
+++ b/examples/device/cdc_uac2/CMakeLists.txt
@@ -0,0 +1,38 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/tusb_cdc.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/tusb_uac2.c
+        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+        )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+        ${CMAKE_CURRENT_SOURCE_DIR}/src
+        )
+
+# Configure compilation flags and libraries for the example... see the corresponding function
+# in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT})
+
+# Uncomment me to enable UART based debugging
+# pico_enable_stdio_uart(${PROJECT} 1)
diff --git a/examples/device/cdc_uac2/README.md b/examples/device/cdc_uac2/README.md
new file mode 100644
index 000000000..5d120be7d
--- /dev/null
+++ b/examples/device/cdc_uac2/README.md
@@ -0,0 +1,52 @@
+#### Composite CDC + UAC2 on Pico
+
+This example provides a composite CDC + UAC2 device on top of a Raspberry Pi
+Pico board.
+
+
+#### Use Cases
+
+- The CDC + UAC2 composite device happens to be important, especially in the
+  amateur radio community.
+
+  Modern radios (`rigs`) like Icom IC-7300 + IC-705 expose a sound card and a
+  serial device (`composite device`) to the computer over a single USB cable.
+  This allows for Audio I/O and CAT control over a single USB cable which is
+  very convenient.
+
+  By including and maintaining this example in TinyUSB repository, we enable
+  the amateur radio community to build (`homebrew`) radios with similar
+  functionality as the (expensive) commercial rigs.
+
+  This PR is important in bridging this specific gap between the commercial
+  rigs and homebrew equipment.
+
+- https://digirig.net/digirig-mobile-rev-1-9/ is a digital interface for
+  interfacing radios (that lack an inbuilt digital interface) with computers.
+  Digirig Mobile works brilliantly (is OSS!) and is a big improvement over
+  traditional digital interfaces (like the SignaLink USB Interface). By using a
+  Raspberry Pi Pico powered CDC + UAC2 composite device, we can simplify the
+  Digirig Mobile schematic, drastically reduce the manufacturing cost, and
+  (again) enable the homebrewers community to homebrew a modern digital interface
+  with ease themselves.
+
+
+#### Build Steps
+
+```
+cd examples/device/cdc_uac2
+
+export PICO_SDK_PATH=$HOME/pico-sdk
+
+cmake -DFAMILY=rp2040 pico .
+
+cmake -DFAMILY=rp2040 -DCMAKE_BUILD_TYPE=Debug # use this for debugging
+
+make BOARD=raspberry_pi_pico all
+```
+
+
+#### Development Notes
+
+Please try to keep this code synchronized with the `uac2_headset` example
+included in this repository.
diff --git a/examples/device/cdc_uac2/skip.txt b/examples/device/cdc_uac2/skip.txt
new file mode 100644
index 000000000..8e70a5278
--- /dev/null
+++ b/examples/device/cdc_uac2/skip.txt
@@ -0,0 +1,52 @@
+board:curiosity_nano
+board:frdm_kl25z
+board:stm32l052dap52
+family:broadcom_32bit
+family:broadcom_64bit
+family:ch32v307
+family:fomu
+family:gd32vf103
+family:kinetis_k32l
+family:kinetis_kl
+family:lpc11
+family:lpc13
+family:lpc15
+family:lpc17
+family:lpc51
+family:lpc54
+family:lpc55
+family:mm32
+family:msp430
+family:msp432e
+family:msp432e4
+family:nrf
+family:ra
+family:rx
+family:samd11
+family:samd21
+family:samd51
+family:same5x
+family:saml2x
+family:stm32f0
+family:stm32f1
+family:stm32f2
+family:stm32f3
+family:stm32f4
+family:stm32f7
+family:stm32g4
+family:stm32h7
+family:stm32l0
+family:stm32l4
+family:stm32u5
+family:stm32wb
+family:tm4c123
+family:xmc4000
+mcu:LPC11UXX
+mcu:LPC13XX
+mcu:MKL25ZXX
+mcu:MSP430x5xx
+mcu:NUC121
+mcu:SAMD11
+mcu:SAME5X
+mcu:SAMG
+mcu:STM32L0
diff --git a/examples/device/cdc_uac2/src/common.h b/examples/device/cdc_uac2/src/common.h
new file mode 100644
index 000000000..f281024c7
--- /dev/null
+++ b/examples/device/cdc_uac2/src/common.h
@@ -0,0 +1,34 @@
+#ifndef __COMMON_H__
+#define __COMMON_H__
+
+/* Blink pattern
+ * - 25 ms   : streaming data
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum
+{
+  BLINK_STREAMING = 25,
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+enum
+{
+  VOLUME_CTRL_0_DB = 0,
+  VOLUME_CTRL_10_DB = 2560,
+  VOLUME_CTRL_20_DB = 5120,
+  VOLUME_CTRL_30_DB = 7680,
+  VOLUME_CTRL_40_DB = 10240,
+  VOLUME_CTRL_50_DB = 12800,
+  VOLUME_CTRL_60_DB = 15360,
+  VOLUME_CTRL_70_DB = 17920,
+  VOLUME_CTRL_80_DB = 20480,
+  VOLUME_CTRL_90_DB = 23040,
+  VOLUME_CTRL_100_DB = 25600,
+  VOLUME_CTRL_SILENCE = 0x8000,
+};
+
+#endif
diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c
new file mode 100644
index 000000000..68352338e
--- /dev/null
+++ b/examples/device/cdc_uac2/src/main.c
@@ -0,0 +1,99 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenberg
+ * Copyright (c) 2022 Angel Molina <angelmolinu@gmail.com>
+ * Copyright (c) 2023 Dhiru Kholia <dhiru.kholia@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+#include "common.h"
+
+extern uint32_t blink_interval_ms;
+
+#if (CFG_TUSB_MCU == OPT_MCU_RP2040)
+#include "pico/stdlib.h"
+#endif
+
+void led_blinking_task(void);
+
+/*------------- MAIN -------------*/
+int main(void)
+{
+  board_init();
+
+  // init device stack on configured roothub port
+  tud_init(BOARD_TUD_RHPORT);
+
+#if (CFG_TUSB_MCU == OPT_MCU_RP2040)
+  stdio_init_all();
+#endif
+
+  TU_LOG1("CDC UAC2 example running\r\n");
+
+  while (1)
+  {
+    tud_task(); // TinyUSB device task
+    led_blinking_task();
+
+#if (CFG_TUSB_MCU == OPT_MCU_RP2040)
+    // printf("Hello, world!\n");
+#endif
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Device callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device is mounted
+void tud_mount_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
+
+// Invoked when device is unmounted
+void tud_umount_cb(void)
+{
+  blink_interval_ms = BLINK_NOT_MOUNTED;
+}
+
+// Invoked when usb bus is suspended
+// remote_wakeup_en : if host allow us  to perform remote wakeup
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+void tud_suspend_cb(bool remote_wakeup_en)
+{
+  (void)remote_wakeup_en;
+  blink_interval_ms = BLINK_SUSPENDED;
+}
+
+// Invoked when usb bus is resumed
+void tud_resume_cb(void)
+{
+  blink_interval_ms = BLINK_MOUNTED;
+}
diff --git a/examples/device/cdc_uac2/src/tusb_cdc.c b/examples/device/cdc_uac2/src/tusb_cdc.c
new file mode 100644
index 000000000..a95f638d9
--- /dev/null
+++ b/examples/device/cdc_uac2/src/tusb_cdc.c
@@ -0,0 +1,72 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board.h"
+#include "tusb.h"
+#include "common.h"
+
+// Invoked when cdc when line state changed e.g connected/disconnected
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
+{
+  (void) itf;
+  (void) rts;
+
+  if (dtr)
+  {
+    // Terminal connected
+  }
+  else
+  {
+    // Terminal disconnected
+  }
+}
+
+// Invoked when CDC interface received data from host
+void tud_cdc_rx_cb(uint8_t itf)
+{
+  uint8_t buf[64];
+  uint32_t count;
+
+  // connected() check for DTR bit
+  // Most but not all terminal client set this when making connection
+  if (tud_cdc_connected())
+  {
+    if (tud_cdc_available()) // data is available
+    {
+      count = tud_cdc_n_read(itf, buf, sizeof(buf));
+      (void) count;
+
+      tud_cdc_n_write(itf, buf, count);
+      tud_cdc_n_write_flush(itf);
+      // dummy code to check that cdc serial is responding
+      board_led_write(0);
+      board_delay(50);
+      board_led_write(1);
+      board_delay(50);
+      board_led_write(0);
+    }
+  }
+}
diff --git a/examples/device/cdc_uac2/src/tusb_config.h b/examples/device/cdc_uac2/src/tusb_config.h
new file mode 100644
index 000000000..373f0b01f
--- /dev/null
+++ b/examples/device/cdc_uac2/src/tusb_config.h
@@ -0,0 +1,174 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jerzy Kasenberg
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "usb_descriptors.h"
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+// RHPort number used for device can be defined by board.mk, default to port 0
+#ifndef BOARD_TUD_RHPORT
+#define BOARD_TUD_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUD_MAX_SPEED
+#define BOARD_TUD_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// Common Configuration
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Device stack
+#define CFG_TUD_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUD_MAX_SPEED     BOARD_TUD_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUSB_MEM_SECTION
+#define CFG_TUSB_MEM_SECTION
+#endif
+
+#ifndef CFG_TUSB_MEM_ALIGN
+#define CFG_TUSB_MEM_ALIGN        __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE CONFIGURATION
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+#define CFG_TUD_ENDPOINT0_SIZE    64
+#endif
+
+//------------- CLASS -------------//
+#define CFG_TUD_CDC               1
+#define CFG_TUD_MSC               0
+#define CFG_TUD_HID               0
+#define CFG_TUD_MIDI              0
+#define CFG_TUD_AUDIO             1
+#define CFG_TUD_VENDOR            0
+
+//--------------------------------------------------------------------
+// AUDIO CLASS DRIVER CONFIGURATION
+//--------------------------------------------------------------------
+
+#define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                                TUD_AUDIO_HEADSET_STEREO_DESC_LEN
+
+// How many formats are used, need to adjust USB descriptor if changed
+#define CFG_TUD_AUDIO_FUNC_1_N_FORMATS                               2
+
+// Audio format type I specifications
+#if defined(__RX__)
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         48000     // 16bit/48kHz is the best quality for Renesas RX
+#else
+#define CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE                         96000     // 24bit/96kHz is the best quality for full-speed, high-speed is needed beyond this
+#endif
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX                           1
+#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX                           1         // Changed
+
+// 16bit in 16bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX          2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX                  16
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX          2
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX                  16
+
+#if defined(__RX__)
+// 8bit in 8bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX          1
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX                  8
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX          1
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX                  8
+#else
+// 24bit in 32bit slots
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX          4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX                  24
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX          4
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX                  24
+#endif
+
+// EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
+#define CFG_TUD_AUDIO_ENABLE_EP_IN                1
+
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+#define CFG_TUD_AUDIO_FUNC_1_FORMAT_2_EP_SZ_IN    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ      TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN)
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX         TU_MAX(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_EP_SZ_IN) // Maximum EP IN size for all AS alternate settings used
+
+// EP and buffer size - for isochronous EP´s, the buffer and EP size are equal (different sizes would not make sense)
+#define CFG_TUD_AUDIO_ENABLE_EP_OUT               1
+
+#define CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+#define CFG_TUD_AUDIO_UNC_1_FORMAT_2_EP_SZ_OUT    TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX)
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ     TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT)
+#define CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX        TU_MAX(CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT, CFG_TUD_AUDIO_UNC_1_FORMAT_1_EP_SZ_OUT) // Maximum EP IN size for all AS alternate settings used
+
+// Number of Standard AS Interface Descriptors (4.9.1) defined per audio function - this is required to be able to remember the current alternate settings of these interfaces - We restrict us here to have a constant number for all audio functions (which means this has to be the maximum number of AS interfaces an audio function has and a second audio function with less AS interfaces just wastes a few bytes)
+#define CFG_TUD_AUDIO_FUNC_1_N_AS_INT 	          2
+
+// Size of control request buffer
+#define CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ          64
+
+// CDC FIFO size of TX and RX
+#define CFG_TUD_CDC_RX_BUFSIZE                    64
+#define CFG_TUD_CDC_TX_BUFSIZE                    64
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/device/cdc_uac2/src/tusb_uac2.c b/examples/device/cdc_uac2/src/tusb_uac2.c
new file mode 100644
index 000000000..33dc33122
--- /dev/null
+++ b/examples/device/cdc_uac2/src/tusb_uac2.c
@@ -0,0 +1,316 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenberg
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board.h"
+#include "tusb.h"
+#include "usb_descriptors.h"
+#include "common.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+
+// List of supported sample rates
+const uint32_t sample_rates[] = {44100, 48000};
+uint32_t current_sample_rate  = 44100;
+
+#define N_SAMPLE_RATES  TU_ARRAY_SIZE(sample_rates)
+
+uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
+
+// Audio controls
+// Current states
+int8_t mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];       // +1 for master channel 0
+int16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX + 1];    // +1 for master channel 0
+
+// Buffer for microphone data
+int32_t mic_buf[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ / 4];
+// Buffer for speaker data
+int32_t spk_buf[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ / 4];
+// Speaker data size received in the last frame
+int spk_data_size;
+// Resolution per format
+const uint8_t resolutions_per_format[CFG_TUD_AUDIO_FUNC_1_N_FORMATS] = {CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX};
+// Current resolution, update on format change
+uint8_t current_resolution;
+
+// Helper for clock get requests
+static bool tud_audio_clock_get_request(uint8_t rhport, audio_control_request_t const *request)
+{
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
+
+  if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+  {
+    if (request->bRequest == AUDIO_CS_REQ_CUR)
+    {
+      TU_LOG1("Clock get current freq %lu\r\n", current_sample_rate);
+
+      audio_control_cur_4_t curf = { (int32_t) tu_htole32(current_sample_rate) };
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &curf, sizeof(curf));
+    }
+    else if (request->bRequest == AUDIO_CS_REQ_RANGE)
+    {
+      audio_control_range_4_n_t(N_SAMPLE_RATES) rangef =
+      {
+        .wNumSubRanges = tu_htole16(N_SAMPLE_RATES)
+      };
+      TU_LOG1("Clock get %d freq ranges\r\n", N_SAMPLE_RATES);
+      for(uint8_t i = 0; i < N_SAMPLE_RATES; i++)
+      {
+        rangef.subrange[i].bMin = (int32_t) sample_rates[i];
+        rangef.subrange[i].bMax = (int32_t) sample_rates[i];
+        rangef.subrange[i].bRes = 0;
+        TU_LOG1("Range %d (%d, %d, %d)\r\n", i, (int)rangef.subrange[i].bMin, (int)rangef.subrange[i].bMax, (int)rangef.subrange[i].bRes);
+      }
+
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &rangef, sizeof(rangef));
+    }
+  }
+  else if (request->bControlSelector == AUDIO_CS_CTRL_CLK_VALID &&
+           request->bRequest == AUDIO_CS_REQ_CUR)
+  {
+    audio_control_cur_1_t cur_valid = { .bCur = 1 };
+    TU_LOG1("Clock get is valid %u\r\n", cur_valid.bCur);
+    return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_valid, sizeof(cur_valid));
+  }
+  TU_LOG1("Clock get request not supported, entity = %u, selector = %u, request = %u\r\n",
+          request->bEntityID, request->bControlSelector, request->bRequest);
+  return false;
+}
+
+// Helper for clock set requests
+static bool tud_audio_clock_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+  (void)rhport;
+
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_CLOCK);
+  TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+  if (request->bControlSelector == AUDIO_CS_CTRL_SAM_FREQ)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_4_t));
+
+    current_sample_rate = (uint32_t) ((audio_control_cur_4_t const *)buf)->bCur;
+
+    TU_LOG1("Clock set current freq: %ld\r\n", current_sample_rate);
+
+    return true;
+  }
+  else
+  {
+    TU_LOG1("Clock set request not supported, entity = %u, selector = %u, request = %u\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+    return false;
+  }
+}
+
+// Helper for feature unit get requests
+static bool tud_audio_feature_unit_get_request(uint8_t rhport, audio_control_request_t const *request)
+{
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT);
+
+  if (request->bControlSelector == AUDIO_FU_CTRL_MUTE && request->bRequest == AUDIO_CS_REQ_CUR)
+  {
+    audio_control_cur_1_t mute1 = { .bCur = mute[request->bChannelNumber] };
+    TU_LOG1("Get channel %u mute %d\r\n", request->bChannelNumber, mute1.bCur);
+    return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &mute1, sizeof(mute1));
+  }
+  else if (UAC2_ENTITY_SPK_FEATURE_UNIT && request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+  {
+    if (request->bRequest == AUDIO_CS_REQ_RANGE)
+    {
+      audio_control_range_2_n_t(1) range_vol = {
+        .wNumSubRanges = tu_htole16(1),
+        .subrange[0] = { .bMin = tu_htole16(-VOLUME_CTRL_50_DB), tu_htole16(VOLUME_CTRL_0_DB), tu_htole16(256) }
+      };
+      TU_LOG1("Get channel %u volume range (%d, %d, %u) dB\r\n", request->bChannelNumber,
+              range_vol.subrange[0].bMin / 256, range_vol.subrange[0].bMax / 256, range_vol.subrange[0].bRes / 256);
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &range_vol, sizeof(range_vol));
+    }
+    else if (request->bRequest == AUDIO_CS_REQ_CUR)
+    {
+      audio_control_cur_2_t cur_vol = { .bCur = tu_htole16(volume[request->bChannelNumber]) };
+      TU_LOG1("Get channel %u volume %d dB\r\n", request->bChannelNumber, cur_vol.bCur / 256);
+      return tud_audio_buffer_and_schedule_control_xfer(rhport, (tusb_control_request_t const *)request, &cur_vol, sizeof(cur_vol));
+    }
+  }
+  TU_LOG1("Feature unit get request not supported, entity = %u, selector = %u, request = %u\r\n",
+          request->bEntityID, request->bControlSelector, request->bRequest);
+
+  return false;
+}
+
+// Helper for feature unit set requests
+static bool tud_audio_feature_unit_set_request(uint8_t rhport, audio_control_request_t const *request, uint8_t const *buf)
+{
+  (void)rhport;
+
+  TU_ASSERT(request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT);
+  TU_VERIFY(request->bRequest == AUDIO_CS_REQ_CUR);
+
+  if (request->bControlSelector == AUDIO_FU_CTRL_MUTE)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_1_t));
+
+    mute[request->bChannelNumber] = ((audio_control_cur_1_t const *)buf)->bCur;
+
+    TU_LOG1("Set channel %d Mute: %d\r\n", request->bChannelNumber, mute[request->bChannelNumber]);
+
+    return true;
+  }
+  else if (request->bControlSelector == AUDIO_FU_CTRL_VOLUME)
+  {
+    TU_VERIFY(request->wLength == sizeof(audio_control_cur_2_t));
+
+    volume[request->bChannelNumber] = ((audio_control_cur_2_t const *)buf)->bCur;
+
+    TU_LOG1("Set channel %d volume: %d dB\r\n", request->bChannelNumber, volume[request->bChannelNumber] / 256);
+
+    return true;
+  }
+  else
+  {
+    TU_LOG1("Feature unit set request not supported, entity = %u, selector = %u, request = %u\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+    return false;
+  }
+}
+
+//--------------------------------------------------------------------+
+// Application Callback API Implementations
+//--------------------------------------------------------------------+
+
+// Invoked when audio class specific get request received for an entity
+bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request)
+{
+  audio_control_request_t const *request = (audio_control_request_t const *)p_request;
+
+  if (request->bEntityID == UAC2_ENTITY_CLOCK)
+    return tud_audio_clock_get_request(rhport, request);
+  if (request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT)
+    return tud_audio_feature_unit_get_request(rhport, request);
+  else
+  {
+    TU_LOG1("Get request not handled, entity = %d, selector = %d, request = %d\r\n",
+            request->bEntityID, request->bControlSelector, request->bRequest);
+  }
+  return false;
+}
+
+// Invoked when audio class specific set request received for an entity
+bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p_request, uint8_t *buf)
+{
+  audio_control_request_t const *request = (audio_control_request_t const *)p_request;
+
+  if (request->bEntityID == UAC2_ENTITY_SPK_FEATURE_UNIT)
+    return tud_audio_feature_unit_set_request(rhport, request, buf);
+  if (request->bEntityID == UAC2_ENTITY_CLOCK)
+    return tud_audio_clock_set_request(rhport, request, buf);
+  TU_LOG1("Set request not handled, entity = %d, selector = %d, request = %d\r\n",
+          request->bEntityID, request->bControlSelector, request->bRequest);
+
+  return false;
+}
+
+bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void)rhport;
+
+  uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+  uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+  if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt == 0) {
+    // Audio streaming stop
+    blink_interval_ms = BLINK_MOUNTED;
+  }
+
+  return true;
+}
+
+bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+  (void)rhport;
+  uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex));
+  uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue));
+
+  TU_LOG2("Set interface %d alt %d\r\n", itf, alt);
+  if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt != 0) {
+    // Audio streaming start
+    blink_interval_ms = BLINK_STREAMING;
+  }
+
+  // Clear buffer when streaming format is changed
+  spk_data_size = 0;
+  if(alt != 0)
+  {
+    current_resolution = resolutions_per_format[alt-1];
+  }
+
+  return true;
+}
+
+bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting)
+{
+  (void)rhport;
+  (void)func_id;
+  (void)ep_out;
+  (void)cur_alt_setting;
+
+  spk_data_size = tud_audio_read(spk_buf, n_bytes_received);
+  tud_audio_write(spk_buf, n_bytes_received);
+
+  return true;
+}
+
+bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting)
+{
+  (void)rhport;
+  (void)itf;
+  (void)ep_in;
+  (void)cur_alt_setting;
+
+  // This callback could be used to fill microphone data separately
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+void led_blinking_task(void)
+{
+  static uint32_t start_ms = 0;
+  static bool led_state = false;
+
+  // Blink every interval ms
+  if (board_millis() - start_ms < blink_interval_ms) return;
+  start_ms += blink_interval_ms;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state;
+}
diff --git a/examples/device/cdc_uac2/src/usb_descriptors.c b/examples/device/cdc_uac2/src/usb_descriptors.c
new file mode 100644
index 000000000..1b2766829
--- /dev/null
+++ b/examples/device/cdc_uac2/src/usb_descriptors.c
@@ -0,0 +1,190 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Jerzy Kasenberg
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+#include "usb_descriptors.h"
+
+/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
+ * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
+ *
+ * Auto ProductID layout's Bitmap:
+ *   [MSB]     AUDIO | MIDI | HID | MSC | CDC          [LSB]
+ */
+#define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
+#define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
+    _PID_MAP(MIDI, 3) | _PID_MAP(AUDIO, 4) | _PID_MAP(VENDOR, 5) )
+
+//--------------------------------------------------------------------+
+// Device Descriptors
+//--------------------------------------------------------------------+
+tusb_desc_device_t const desc_device =
+{
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = 0x0200,
+
+    // Use Interface Association Descriptor (IAD)
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+
+    .idVendor           = 0xCafe,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
+
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
+
+    .bNumConfigurations = 0x01
+};
+
+// Invoked when received GET DEVICE DESCRIPTOR
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void)
+{
+  return (uint8_t const *)&desc_device;
+}
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor
+//--------------------------------------------------------------------+
+#define CONFIG_TOTAL_LEN    	(TUD_CONFIG_DESC_LEN + CFG_TUD_AUDIO * TUD_AUDIO_HEADSET_STEREO_DESC_LEN + CFG_TUD_CDC * TUD_CDC_DESC_LEN)
+
+#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX
+  // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number
+  // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ...
+  #define EPNUM_AUDIO_IN    0x03
+  #define EPNUM_AUDIO_OUT   0x03
+
+  #define EPNUM_CDC_NOTIF   0x84
+  #define EPNUM_CDC_OUT     0x05
+  #define EPNUM_CDC_IN      0x85
+
+#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+  // ISO endpoints for NRF5x are fixed to 0x08 (0x88)
+  #define EPNUM_AUDIO_IN    0x08
+  #define EPNUM_AUDIO_OUT   0x08
+
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
+  // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_AUDIO_IN    0x01
+  #define EPNUM_AUDIO_OUT   0x02
+
+#elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
+  // FT9XX doesn't support a same endpoint number with different direction IN and OUT
+  //    e.g EP1 OUT & EP1 IN cannot exist together
+  #define EPNUM_AUDIO_IN    0x01
+  #define EPNUM_AUDIO_OUT   0x02
+
+#else
+  #define EPNUM_AUDIO_IN    0x01
+  #define EPNUM_AUDIO_OUT   0x01
+
+  #define EPNUM_CDC_NOTIF   0x83
+  #define EPNUM_CDC_OUT     0x04
+  #define EPNUM_CDC_IN      0x84
+#endif
+
+uint8_t const desc_configuration[] =
+{
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(2, EPNUM_AUDIO_OUT, EPNUM_AUDIO_IN | 0x80),
+
+    // CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 6, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64)
+};
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR
+// Application return pointer to descriptor
+// Descriptor contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
+{
+  (void)index; // for multiple configurations
+  return desc_configuration;
+}
+
+//--------------------------------------------------------------------+
+// String Descriptors
+//--------------------------------------------------------------------+
+
+// array of pointer to string descriptors
+char const* string_desc_arr [] =
+{
+  (const char[]) { 0x09, 0x04 },  // 0: is supported language is English (0x0409)
+  "TinyUSB",                      // 1: Manufacturer
+  "TinyUSB headset",              // 2: Product
+  "000001",                       // 3: Serials, should use chip ID
+  "TinyUSB Speakers",             // 4: Audio Interface
+  "TinyUSB Microphone",           // 5: Audio Interface
+  "TinyUSB CDC",                  // 6: Audio Interface
+};
+
+static uint16_t _desc_str[32];
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
+{
+  (void)langid;
+
+  uint8_t chr_count;
+
+  if (index == 0)
+  {
+    memcpy(&_desc_str[1], string_desc_arr[0], 2);
+    chr_count = 1;
+  }
+  else
+  {
+    // Convert ASCII string into UTF-16
+
+    if (!(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0]))) return NULL;
+
+    const char* str = string_desc_arr[index];
+
+    // Cap at max char
+    chr_count = (uint8_t) strlen(str);
+    if (chr_count > 31) chr_count = 31;
+
+    for (uint8_t i = 0; i < chr_count; i++)
+    {
+      _desc_str[1 + i] = str[i];
+    }
+  }
+
+  // first byte is length (including header), second byte is string type
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+
+  return _desc_str;
+}
diff --git a/examples/device/cdc_uac2/src/usb_descriptors.h b/examples/device/cdc_uac2/src/usb_descriptors.h
new file mode 100644
index 000000000..736feeefe
--- /dev/null
+++ b/examples/device/cdc_uac2/src/usb_descriptors.h
@@ -0,0 +1,158 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Jerzy Kasenbreg
+ * Copyright (c) 2022 Angel Molina (angelmolinu@gmail.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _USB_DESCRIPTORS_H_
+#define _USB_DESCRIPTORS_H_
+
+// #include "tusb.h"
+
+// Unit numbers are arbitrary selected
+#define UAC2_ENTITY_CLOCK               0x04
+// Speaker path
+#define UAC2_ENTITY_SPK_INPUT_TERMINAL  0x01
+#define UAC2_ENTITY_SPK_FEATURE_UNIT    0x02
+#define UAC2_ENTITY_SPK_OUTPUT_TERMINAL 0x03
+// Microphone path
+#define UAC2_ENTITY_MIC_INPUT_TERMINAL  0x11
+#define UAC2_ENTITY_MIC_OUTPUT_TERMINAL 0x13
+
+enum
+{
+  ITF_NUM_AUDIO_CONTROL = 0,
+  ITF_NUM_AUDIO_STREAMING_SPK,
+  ITF_NUM_AUDIO_STREAMING_MIC,
+  ITF_NUM_CDC,
+  ITF_NUM_CDC_DATA,
+  ITF_NUM_TOTAL
+};
+
+#define TUD_AUDIO_HEADSET_STEREO_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+    + TUD_AUDIO_DESC_STD_AC_LEN\
+    + TUD_AUDIO_DESC_CS_AC_LEN\
+    + TUD_AUDIO_DESC_CLK_SRC_LEN\
+    + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN\
+    + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+    + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    /* Interface 1, Alternate 0 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 1, Alternate 2 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 2, Alternate 0 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    /* Interface 2, Alternate 1 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+    /* Interface 2, Alternate 2 */\
+    + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+    + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+    + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+    + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+    + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
+
+#define TUD_AUDIO_HEADSET_STEREO_DESCRIPTOR(_stridx, _epout, _epin) \
+    /* Standard Interface Association Descriptor (IAD) */\
+    TUD_AUDIO_DESC_IAD(/*_firstitfs*/ ITF_NUM_AUDIO_CONTROL, /*_nitfs*/ 3, /*_stridx*/ 0x00),\
+    /* Standard AC Interface Descriptor(4.7.1) */\
+    TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ ITF_NUM_AUDIO_CONTROL, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+    /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+    TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_HEADSET, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+    /* Clock Source Descriptor(4.7.2.1) */\
+    TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ UAC2_ENTITY_CLOCK, /*_attr*/ 3, /*_ctrl*/ 7, /*_assocTerm*/ 0x00,  /*_stridx*/ 0x00),    \
+    /* Input Terminal Descriptor(4.7.2.4) */\
+    TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x02, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
+    /* Feature Unit Descriptor(4.7.2.8) */\
+    TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL(/*_unitid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_srcid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrlch0master*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch1*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch2*/ (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_stridx*/ 0x00),\
+    /* Output Terminal Descriptor(4.7.2.5) */\
+    TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_SPK_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_OUT_HEADPHONES, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_SPK_FEATURE_UNIT, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+    /* Input Terminal Descriptor(4.7.2.4) */\
+    TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ UAC2_ENTITY_MIC_INPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x00, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
+    /* Output Terminal Descriptor(4.7.2.5) */\
+    TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_srcid*/ UAC2_ENTITY_MIC_INPUT_TERMINAL, /*_clkid*/ UAC2_ENTITY_CLOCK, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+    /* Standard AS Interface Descriptor(4.9.1) */\
+    /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x05),\
+    /* Standard AS Interface Descriptor(4.9.1) */\
+    /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x05),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_RX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
+    /* Interface 1, Alternate 2 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_SPK), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x05),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_SPK_INPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_RX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ADAPTIVE | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_RX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_RX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_MILLISEC, /*_lockdelay*/ 0x0001),\
+    /* Standard AS Interface Descriptor(4.9.1) */\
+    /* Interface 2, Alternate 0 - default alternate setting with 0 bandwidth */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x04),\
+    /* Standard AS Interface Descriptor(4.9.1) */\
+    /* Interface 2, Alternate 1 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_RESOLUTION_TX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
+    /* Interface 2, Alternate 2 - alternate interface for data streaming */\
+    TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)(ITF_NUM_AUDIO_STREAMING_MIC), /*_altset*/ 0x02, /*_nEPs*/ 0x01, /*_stridx*/ 0x04),\
+    /* Class-Specific AS Interface Descriptor(4.9.2) */\
+    TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ UAC2_ENTITY_MIC_OUTPUT_TERMINAL, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+    /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+    TUD_AUDIO_DESC_TYPE_I_FORMAT(CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_RESOLUTION_TX),\
+    /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+    TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (uint8_t) (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_MAX_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_FORMAT_2_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX), /*_interval*/ 0x01),\
+    /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+    TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
+
+#endif

From 1b658ae109a9d2aa1ac2fc14393cb9d8a64ccd8a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 20 Jun 2023 12:11:01 +0700
Subject: [PATCH 1821/2085] add etm trace for mcb1800

clean up other ide setting
---
 .gitignore                                    |  2 ++
 .idea/runConfigurations/kl25.xml              | 10 ++++++
 .idea/runConfigurations/lpc1857.xml           | 10 ++++++
 .idea/runConfigurations/mcx947.xml            | 10 ++++++
 .idea/runConfigurations/mcx947_jlink.xml      | 10 ------
 .idea/runConfigurations/rt1010.xml            | 10 ++++++
 .idea/runConfigurations/rt1010_jlink.xml      | 10 ------
 .idea/runConfigurations/rt1060.xml            | 10 ++++++
 .idea/runConfigurations/rt1060_jlink.xml      | 10 ------
 .idea/runConfigurations/stlink.xml            | 10 ++++++
 .idea/runConfigurations/stm32g474.xml         | 10 ++++++
 .idea/runConfigurations/stm32g474_jlink.xml   | 10 ------
 .idea/runConfigurations/stm32h743.xml         | 10 ++++++
 hw/bsp/lpc18/boards/mcb1800/board.h           | 21 ++++++-----
 .../lpc18/boards/mcb1800/ozone/lpc1857.jdebug | 36 +++++++++++++++++++
 hw/bsp/lpc18/family.c                         | 11 ++++--
 .../cubemx/{board.ioc => b_g474e_dpow1.ioc}   |  6 ++--
 .../stm32h743eval/cubemx/stm32h743eval.ioc    |  4 +--
 .../{h743eval.jdebug => stm32h743.jdebug}     | 14 +++-----
 19 files changed, 150 insertions(+), 64 deletions(-)
 create mode 100644 .idea/runConfigurations/kl25.xml
 create mode 100644 .idea/runConfigurations/lpc1857.xml
 create mode 100644 .idea/runConfigurations/mcx947.xml
 delete mode 100644 .idea/runConfigurations/mcx947_jlink.xml
 create mode 100644 .idea/runConfigurations/rt1010.xml
 delete mode 100644 .idea/runConfigurations/rt1010_jlink.xml
 create mode 100644 .idea/runConfigurations/rt1060.xml
 delete mode 100644 .idea/runConfigurations/rt1060_jlink.xml
 create mode 100644 .idea/runConfigurations/stlink.xml
 create mode 100644 .idea/runConfigurations/stm32g474.xml
 delete mode 100644 .idea/runConfigurations/stm32g474_jlink.xml
 create mode 100644 .idea/runConfigurations/stm32h743.xml
 create mode 100644 hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
 rename hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/{board.ioc => b_g474e_dpow1.ioc} (98%)
 rename hw/bsp/stm32h7/boards/stm32h743eval/ozone/{h743eval.jdebug => stm32h743.jdebug} (96%)

diff --git a/.gitignore b/.gitignore
index 8f5bb6efd..c665d6c73 100644
--- a/.gitignore
+++ b/.gitignore
@@ -21,6 +21,8 @@ _build
 /examples/*/*/ses
 /examples/*/*/ozone
 /examples/obsolete
+hw/bsp/**/cubemx/*/
+.mxproject
 # coverity intermediate files
 cov-int
 # cppcheck build directories
diff --git a/.idea/runConfigurations/kl25.xml b/.idea/runConfigurations/kl25.xml
new file mode 100644
index 000000000..8b0cd9e75
--- /dev/null
+++ b/.idea/runConfigurations/kl25.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MKL25Z128xxx4&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc1857.xml b/.idea/runConfigurations/lpc1857.xml
new file mode 100644
index 000000000..ed7d17ca6
--- /dev/null
+++ b/.idea/runConfigurations/lpc1857.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="lpc1857" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc1857&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/mcx947.xml b/.idea/runConfigurations/mcx947.xml
new file mode 100644
index 000000000..ddd568bcb
--- /dev/null
+++ b/.idea/runConfigurations/mcx947.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/mcx.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/mcx947_jlink.xml b/.idea/runConfigurations/mcx947_jlink.xml
deleted file mode 100644
index 27661bec5..000000000
--- a/.idea/runConfigurations/mcx947_jlink.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="mcx947 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/mcx.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
-    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
-      <debugger kind="GDB" isBundled="true" />
-    </custom-gdb-server>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml
new file mode 100644
index 000000000..98dea28a4
--- /dev/null
+++ b/.idea/runConfigurations/rt1010.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010_jlink.xml b/.idea/runConfigurations/rt1010_jlink.xml
deleted file mode 100644
index 68ebb8885..000000000
--- a/.idea/runConfigurations/rt1010_jlink.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1010 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="frdm_kl25z" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
-    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
-      <debugger kind="GDB" isBundled="true" />
-    </custom-gdb-server>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1060.xml b/.idea/runConfigurations/rt1060.xml
new file mode 100644
index 000000000..ff6ee8d84
--- /dev/null
+++ b/.idea/runConfigurations/rt1060.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="rt1060" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1060_jlink.xml b/.idea/runConfigurations/rt1060_jlink.xml
deleted file mode 100644
index 014a4d1b1..000000000
--- a/.idea/runConfigurations/rt1060_jlink.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1060 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
-    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
-      <debugger kind="GDB" isBundled="true" />
-    </custom-gdb-server>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml
new file mode 100644
index 000000000..b3f6d15f0
--- /dev/null
+++ b/.idea/runConfigurations/stlink.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="stlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-p 62847 -cp &quot;/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.0.600.202301161003/tools/bin&quot; --frequency 24000 --swd" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::62847" executable="/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.linux64_2.0.500.202301161003/tools/bin/ST-LINK_gdbserver" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/stm32g474.xml b/.idea/runConfigurations/stm32g474.xml
new file mode 100644
index 000000000..d461cd60e
--- /dev/null
+++ b/.idea/runConfigurations/stm32g474.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/stm32g474_jlink.xml b/.idea/runConfigurations/stm32g474_jlink.xml
deleted file mode 100644
index c33829833..000000000
--- a/.idea/runConfigurations/stm32g474_jlink.xml
+++ /dev/null
@@ -1,10 +0,0 @@
-<component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stm32g474 jlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="b_g474e_dpow1" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
-    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
-      <debugger kind="GDB" isBundled="true" />
-    </custom-gdb-server>
-    <method v="2">
-      <option name="CLION.COMPOUND.BUILD" enabled="true" />
-    </method>
-  </configuration>
-</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/stm32h743.xml b/.idea/runConfigurations/stm32h743.xml
new file mode 100644
index 000000000..c438422ce
--- /dev/null
+++ b/.idea/runConfigurations/stm32h743.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="stm32h743" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32h743xi&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.h b/hw/bsp/lpc18/boards/mcb1800/board.h
index 6111da975..f10500d79 100644
--- a/hw/bsp/lpc18/boards/mcb1800/board.h
+++ b/hw/bsp/lpc18/boards/mcb1800/board.h
@@ -41,10 +41,8 @@
 
 #define UART_DEV      LPC_USART3
 
-static inline void board_lpc18_pinmux(void)
-{
-  const PINMUX_GRP_T pinmuxing[] =
-  {
+static inline void board_lpc18_pinmux(void) {
+  const PINMUX_GRP_T pinmuxing[] = {
     // LEDs
     { 0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4) },
     { 0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
@@ -67,13 +65,21 @@ static inline void board_lpc18_pinmux(void)
 
     { 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 },			              // P9_5 USB1_VBUS_EN, USB1 VBus function
     { 0x2, 5, SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
+
+    // ETM Trace
+    #ifdef TRACE_ETM
+    { 0xF, 4, SCU_MODE_FUNC2 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 5, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 6, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 7, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 8, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    #endif
   };
 
   Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
 
   /* Pin clock mux values, re-used structure, value in first index is meaningless */
-  const PINMUX_GRP_T pinclockmuxing[] =
-  {
+  const PINMUX_GRP_T pinclockmuxing[] = {
     { 0, 0,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
     { 0, 1,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
     { 0, 2,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
@@ -81,8 +87,7 @@ static inline void board_lpc18_pinmux(void)
   };
 
   /* Clock pins only, group field not used */
-  for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
-  {
+  for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) {
     Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
   }
 }
diff --git a/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
new file mode 100644
index 000000000..6e298c62d
--- /dev/null
+++ b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
@@ -0,0 +1,36 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Project.AddSvdFile ("Cortex-M3.svd");
+  Project.AddSvdFile ("./LPC18xx.svd");
+
+  Project.SetDevice ("LPC1857");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-mcb1800/cdc_msc.elf");
+}
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+  //
+  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+  //
+  // Project.SetJLinkScript("./NXP_LPC1857JET256_TraceExample.pex");
+}
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index 57f9d55da..2fd69c84b 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -69,7 +69,6 @@ void USB1_IRQHandler(void)
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
-
 /* System configuration variables used by chip driver */
 const uint32_t OscRateIn = 12000000;
 const uint32_t ExtRateIn = 0;
@@ -84,7 +83,15 @@ void SystemInit(void)
 #endif
 
   board_lpc18_pinmux();
-  Chip_SetupXtalClocking();
+
+  #ifdef TRACE_ETM
+  // Trace clock is limited to 60MHz, limit CPU clock to 120MHz
+  Chip_SetupCoreClock(CLKIN_CRYSTAL, 120000000UL, true);
+  #else
+  // CPU clock max to 180 Mhz
+  Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
+  #endif
+
 }
 
 void board_init(void)
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc b/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/b_g474e_dpow1.ioc
similarity index 98%
rename from hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc
rename to hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/b_g474e_dpow1.ioc
index 6ce126f84..c15011896 100644
--- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/board.ioc
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/cubemx/b_g474e_dpow1.ioc
@@ -111,13 +111,13 @@ ProjectManager.MainLocation=Src
 ProjectManager.NoMain=false
 ProjectManager.PreviousToolchain=
 ProjectManager.ProjectBuild=false
-ProjectManager.ProjectFileName=board.ioc
-ProjectManager.ProjectName=board
+ProjectManager.ProjectFileName=b_g474e_dpow1.ioc
+ProjectManager.ProjectName=b_g474e_dpow1
 ProjectManager.ProjectStructure=
 ProjectManager.RegisterCallBack=
 ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=Makefile
-ProjectManager.ToolChainLocation=
+ProjectManager.ToolChainLocation=Src
 ProjectManager.UnderRoot=false
 ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_UCPD1_Init-UCPD1-false-LL-true
 RCC.ADC12Freq_Value=150000000
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
index 1cc2cc8fa..331080c17 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
@@ -881,7 +881,7 @@ ProjectManager.HalAssertFull=false
 ProjectManager.HeapSize=0x200
 ProjectManager.KeepUserCode=true
 ProjectManager.LastFirmware=true
-ProjectManager.LibraryCopy=0
+ProjectManager.LibraryCopy=2
 ProjectManager.MainLocation=Src
 ProjectManager.NoMain=false
 ProjectManager.PreviousToolchain=
@@ -892,7 +892,7 @@ ProjectManager.ProjectStructure=
 ProjectManager.RegisterCallBack=
 ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=Makefile
-ProjectManager.ToolChainLocation=
+ProjectManager.ToolChainLocation=Src
 ProjectManager.UnderRoot=false
 ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,4-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
 RCC.ADCFreq_Value=50390625
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/h743eval.jdebug b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug
similarity index 96%
rename from hw/bsp/stm32h7/boards/stm32h743eval/ozone/h743eval.jdebug
rename to hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug
index 093951765..0ab078319 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/ozone/h743eval.jdebug
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/ozone/stm32h743.jdebug
@@ -9,9 +9,6 @@
 **********************************************************************
 */
 void OnProjectLoad (void) {
-  //
-  // Dialog-generated settings
-  //
   Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd");
   Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd");
   Project.AddSvdFile ("./STM32H743.svd");
@@ -21,17 +18,16 @@ void OnProjectLoad (void) {
   Project.SetTargetIF ("SWD");
   Project.SetTIFSpeed ("50 MHz");
 
-  //
-  // User settings
-  //
   Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+  // timing delay for trace pins in pico seconds, default is 2 nano seconds
   Project.SetTraceTiming (100, 100, 100, 100);
-  Edit.SysVar (VAR_TRACE_CORE_CLOCK, 150000000);
-  File.Open ("/home/hathach/code/tinyusb/examples/device/cdc_msc/cmake-build-h743eval/cdc_msc.elf");
+
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-stm32h743eval/cdc_msc.elf");
 }
 
 /*********************************************************************
-*
+*0
 *      TargetReset
 *
 * Function description

From 19c99d3b42276f25a84b184816a9980ee93beb8f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 20 Jun 2023 13:19:08 +0700
Subject: [PATCH 1822/2085] etm trace for nrf52840

---
 hw/bsp/lpc18/boards/mcb1800/board.h           |  18 +-
 hw/bsp/nrf/boards/pca10056/board.h            |   2 +-
 .../nrf/boards/pca10056/ozone/nrf52840.jdebug | 242 ++++++++++++++++++
 hw/bsp/nrf/family.c                           |  25 ++
 hw/bsp/stm32h7/family.c                       |   2 +-
 5 files changed, 278 insertions(+), 11 deletions(-)
 create mode 100644 hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug

diff --git a/hw/bsp/lpc18/boards/mcb1800/board.h b/hw/bsp/lpc18/boards/mcb1800/board.h
index f10500d79..5bfaa37cd 100644
--- a/hw/bsp/lpc18/boards/mcb1800/board.h
+++ b/hw/bsp/lpc18/boards/mcb1800/board.h
@@ -43,6 +43,15 @@
 
 static inline void board_lpc18_pinmux(void) {
   const PINMUX_GRP_T pinmuxing[] = {
+    // ETM Trace
+    #ifdef TRACE_ETM
+    { 0xF, 4, SCU_MODE_FUNC2 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 5, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 6, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 7, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    { 0xF, 8, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
+    #endif
+
     // LEDs
     { 0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4) },
     { 0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
@@ -65,15 +74,6 @@ static inline void board_lpc18_pinmux(void) {
 
     { 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 },			              // P9_5 USB1_VBUS_EN, USB1 VBus function
     { 0x2, 5, SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
-
-    // ETM Trace
-    #ifdef TRACE_ETM
-    { 0xF, 4, SCU_MODE_FUNC2 | SCU_MODE_HIGHSPEEDSLEW_EN },
-    { 0xF, 5, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
-    { 0xF, 6, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
-    { 0xF, 7, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
-    { 0xF, 8, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
-    #endif
   };
 
   Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h
index 50d3067b3..f4368f830 100644
--- a/hw/bsp/nrf/boards/pca10056/board.h
+++ b/hw/bsp/nrf/boards/pca10056/board.h
@@ -36,7 +36,7 @@
 #define LED_STATE_ON          0
 
 // Button
-#define BUTTON_PIN            11
+#define BUTTON_PIN            25 // button 4
 #define BUTTON_STATE_ACTIVE   0
 
 // UART
diff --git a/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug b/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug
new file mode 100644
index 000000000..5b918f429
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug
@@ -0,0 +1,242 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  // Dialog-generated settings
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M4F.svd");
+  Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd");
+
+  Project.SetDevice ("nRF52840_xxAA");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("8 MHz");
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  // User settings
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-pca10056/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging a RAM program on a Cortex-M target device
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  Exec.Reset();
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//
+//    Util.Log("Resetting Program.");
+//
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+  //
+  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+  //
+  Project.SetJLinkScript("./Nordic_nRF52840_TraceExample.pex");
+}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 6a559ada6..5a4730f09 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -93,8 +93,33 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event)
   tusb_hal_nrf_power_event((uint32_t) event);
 }
 
+#ifdef TRACE_ETM
+void trace_etm_init(void) {
+  #ifdef NRF52840_XXAA
+  // Trace clk: P0.7, Trace D0..D3: P1.0, P0.11, P0.12, P1.09
+  // Setting drive strength to H0H1
+  uint32_t const pin_cnf = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
+                           (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
+  NRF_P0->PIN_CNF[ 7] = pin_cnf; // CLK
+  NRF_P1->PIN_CNF[ 0] = pin_cnf; // D0
+  NRF_P0->PIN_CNF[11] = pin_cnf; // D1
+  NRF_P0->PIN_CNF[12] = pin_cnf; // D2
+  NRF_P1->PIN_CNF[ 9] = pin_cnf; // D3
+
+  // trace clock = 16 Mhz, Trace mux = parallel
+  NRF_CLOCK->TRACECONFIG = (CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) |
+                           (CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos);
+  #endif
+}
+#else
+
+#define trace_etm_init()
+#endif
+
 void board_init(void)
 {
+  trace_etm_init();
+
   // stop LF clock just in case we jump from application without reset
   NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
 
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 7e0469bd8..eb4ac841e 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -77,7 +77,7 @@ void trace_etm_init(void) {
   DBGMCU->CR |= DBGMCU_CR_DBG_TRACECKEN | DBGMCU_CR_DBG_CKD1EN | DBGMCU_CR_DBG_CKD3EN;
 }
 #else
-  #define etm_trace_init()
+  #define trace_etm_init()
 #endif
 
 void board_init(void)

From c789cfe518168c7e6e02cd6d4111de9a52b0a8e4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 20 Jun 2023 16:13:10 +0700
Subject: [PATCH 1823/2085] use system_nrf5x.c built-in support for ETM with
 ENABLE_ETM

---
 .../nrf/boards/pca10056/ozone/nrf52840.jdebug |   4 -
 .../nrf/boards/pca10095/ozone/nrf5340.jdebug  | 335 ++++++++++++++++++
 hw/bsp/nrf/family.c                           |  25 --
 hw/bsp/nrf/family.cmake                       |   6 +
 4 files changed, 341 insertions(+), 29 deletions(-)
 create mode 100644 hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug

diff --git a/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug b/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug
index 5b918f429..fa7ab9e23 100644
--- a/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug
+++ b/hw/bsp/nrf/boards/pca10056/ozone/nrf52840.jdebug
@@ -134,10 +134,6 @@ void AfterTargetReset (void) {
 **********************************************************************
 */
 void BeforeTargetConnect (void) {
-  //
-  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
-  //
-  Project.SetJLinkScript("./Nordic_nRF52840_TraceExample.pex");
 }
 
 /*********************************************************************
diff --git a/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug b/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug
new file mode 100644
index 000000000..4ad0376a4
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10095/ozone/nrf5340.jdebug
@@ -0,0 +1,335 @@
+/*********************************************************************
+*                 (c) SEGGER Microcontroller GmbH                    *
+*                      The Embedded Experts                          *
+*                         www.segger.com                             *
+**********************************************************************
+
+File          :
+Created       : 30 Jun 2021 13:37
+Ozone Version : V3.24a
+*/
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  // Dialog-generated settings
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M33F.svd");
+  Project.AddSvdFile ("./nrf5340_application.svd");
+  Project.SetDevice ("nRF5340_xxAA_APP");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("16 MHz");
+
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  // User settings
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-pca10095/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*       OnStartupComplete
+*
+* Function description
+*   Called when program execution has reached/passed
+*   the startup completion point. Optional.
+*
+**********************************************************************
+*/
+//void OnStartupComplete (void) {
+//}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging an application in RAM on a Cortex-M target device.
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//  //
+//  // Set up initial stack pointer
+//  //
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//  }
+//  //
+//  // Set up entry point PC
+//  //
+//  PC = Elf.GetEntryPointPC();
+//
+//  if (PC != 0xFFFFFFFF) {
+//    Target.SetReg("PC", PC);
+//  } else if (VectorTableAddr != 0xFFFFFFFF) {
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  } else {
+//    Util.Error("Project file error: failed to set entry point PC", 1);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+**
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  _SetupTarget();
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*   The default implementation initializes SP and PC to reset values.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  _SetupTarget();
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetResume
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetResume (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotLoad
+*
+* Function description
+*   Called upon loading a snapshot. Optional.
+*
+* Additional information
+*   This function is used to restore the target state in cases
+*   where values cannot simply be written to the target.
+*   Typical use: GPIO clock needs to be enabled, before
+*   GPIO is configured.
+*
+**********************************************************************
+*/
+//void OnSnapshotLoad (void) {
+//}
+
+/*********************************************************************
+*
+*       OnSnapshotSave
+*
+* Function description
+*   Called upon saving a snapshot. Optional.
+*
+* Additional information
+*   This function is usually used to save values of the target
+*   state which can either not be trivially read,
+*   or need to be restored in a specific way or order.
+*   Typically use: Memory Mapped Registers,
+*   such as PLL and GPIO configuration.
+*
+**********************************************************************
+*/
+//void OnSnapshotSave (void) {
+//}
+
+/*********************************************************************
+*
+*       OnError
+*
+* Function description
+*   Called when an error occurred. Optional.
+*
+**********************************************************************
+*/
+//void OnError (void) {
+//}
+
+/*********************************************************************
+*
+*       _SetupTarget
+*
+* Function description
+*   Setup the target.
+*   Called by AfterTargetReset() and AfterTargetDownload().
+*
+*   Auto-generated function. May be overridden by Ozone.
+*
+**********************************************************************
+*/
+void _SetupTarget(void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+  //
+  // Set up initial stack pointer
+  //
+  SP = Target.ReadU32(VectorTableAddr);
+  if (SP != 0xFFFFFFFF) {
+    Target.SetReg("SP", SP);
+  }
+  //
+  // Set up entry point PC
+  //
+  PC = Elf.GetEntryPointPC();
+  if (PC != 0xFFFFFFFF) {
+    Target.SetReg("PC", PC);
+  } else {
+    Util.Error("Project script error: failed to set up entry point PC", 1);
+  }
+}
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 5a4730f09..6a559ada6 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -93,33 +93,8 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event)
   tusb_hal_nrf_power_event((uint32_t) event);
 }
 
-#ifdef TRACE_ETM
-void trace_etm_init(void) {
-  #ifdef NRF52840_XXAA
-  // Trace clk: P0.7, Trace D0..D3: P1.0, P0.11, P0.12, P1.09
-  // Setting drive strength to H0H1
-  uint32_t const pin_cnf = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
-                           (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
-  NRF_P0->PIN_CNF[ 7] = pin_cnf; // CLK
-  NRF_P1->PIN_CNF[ 0] = pin_cnf; // D0
-  NRF_P0->PIN_CNF[11] = pin_cnf; // D1
-  NRF_P0->PIN_CNF[12] = pin_cnf; // D2
-  NRF_P1->PIN_CNF[ 9] = pin_cnf; // D3
-
-  // trace clock = 16 Mhz, Trace mux = parallel
-  NRF_CLOCK->TRACECONFIG = (CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) |
-                           (CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos);
-  #endif
-}
-#else
-
-#define trace_etm_init()
-#endif
-
 void board_init(void)
 {
-  trace_etm_init();
-
   // stop LF clock just in case we jump from application without reset
   NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
 
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 88670b50b..825380d0b 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -46,6 +46,12 @@ function(add_board_target BOARD_TARGET)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
       CONFIG_GPIO_AS_PINRESET
       )
+
+    if (TRACE_ETM STREQUAL "1")
+      # ENABLE_TRACE will cause system_nrf5x.c to set up ETM trace
+      target_compile_definitions(${BOARD_TARGET} PUBLIC ENABLE_TRACE)
+    endif ()
+
     target_include_directories(${BOARD_TARGET} PUBLIC
       ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
       ${NRFX_DIR}

From 77e01448e2047ede1f2b2c8a52609a0ee48a6b13 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 20 Jun 2023 16:41:51 +0700
Subject: [PATCH 1824/2085] ide settings

---
 .idea/cmake.xml                       |  9 +++++----
 .idea/runConfigurations/kl25.xml      |  2 +-
 .idea/runConfigurations/lpc1857.xml   |  2 +-
 .idea/runConfigurations/mcx947.xml    |  2 +-
 .idea/runConfigurations/nrf52840.xml  | 10 ++++++++++
 .idea/runConfigurations/nrf5340.xml   | 10 ++++++++++
 .idea/runConfigurations/rt1010.xml    |  2 +-
 .idea/runConfigurations/rt1060.xml    |  2 +-
 .idea/runConfigurations/stlink.xml    |  2 +-
 .idea/runConfigurations/stm32g474.xml |  2 +-
 .idea/runConfigurations/stm32h743.xml |  4 ++--
 11 files changed, 34 insertions(+), 13 deletions(-)
 create mode 100644 .idea/runConfigurations/nrf52840.xml
 create mode 100644 .idea/runConfigurations/nrf5340.xml

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index c9024715c..0f7649efc 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,9 +2,9 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=mcx -DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056" />
-      <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095" />
+      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="MinSizeRel" GENERATION_OPTIONS="-DFAMILY=mcx -DBOARD=mcxn947brk -DLOG=0 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
@@ -29,7 +29,7 @@
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1010_evk" />
       <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1060_evk" />
       <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1064_evk" />
-      <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=mcb1800" />
+      <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="lpcxpresso18s37" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=lpcxpresso18s37" />
       <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc55 -DBOARD=lpcxpresso55s69" />
       <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g0 -DBOARD=stm32g0b1nucleo" />
@@ -38,6 +38,7 @@
       <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=b_g474e_dpow1 -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="b_g474e_dpow1 iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=b_g474e_dpow1 -DTOOLCHAIN=iar" />
       <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=kinetis_kl -DBOARD=frdm_kl25z -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32h743eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32h7 -DBOARD=stm32h743eval -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/kl25.xml b/.idea/runConfigurations/kl25.xml
index 8b0cd9e75..add9a0d6b 100644
--- a/.idea/runConfigurations/kl25.xml
+++ b/.idea/runConfigurations/kl25.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MKL25Z128xxx4&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MKL25Z128xxx4&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/lpc1857.xml b/.idea/runConfigurations/lpc1857.xml
index ed7d17ca6..f377d86f2 100644
--- a/.idea/runConfigurations/lpc1857.xml
+++ b/.idea/runConfigurations/lpc1857.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="lpc1857" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc1857&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="lpc1857" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc1857&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/mcx947.xml b/.idea/runConfigurations/mcx947.xml
index ddd568bcb..038c87421 100644
--- a/.idea/runConfigurations/mcx947.xml
+++ b/.idea/runConfigurations/mcx947.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/mcx.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/mcx.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/nrf52840.xml b/.idea/runConfigurations/nrf52840.xml
new file mode 100644
index 000000000..66473cc0e
--- /dev/null
+++ b/.idea/runConfigurations/nrf52840.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="nrf52840" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;nrf52840_xxaa&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/nrf5340.xml b/.idea/runConfigurations/nrf5340.xml
new file mode 100644
index 000000000..403095d70
--- /dev/null
+++ b/.idea/runConfigurations/nrf5340.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="nrf5340" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;nrf5340_xxaa_app&quot; -if swd -speed 16000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml
index 98dea28a4..6fabd8561 100644
--- a/.idea/runConfigurations/rt1010.xml
+++ b/.idea/runConfigurations/rt1010.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/rt1060.xml b/.idea/runConfigurations/rt1060.xml
index ff6ee8d84..218c2dfbc 100644
--- a/.idea/runConfigurations/rt1060.xml
+++ b/.idea/runConfigurations/rt1060.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1060" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rt1060" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml
index b3f6d15f0..c27392ca5 100644
--- a/.idea/runConfigurations/stlink.xml
+++ b/.idea/runConfigurations/stlink.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-p 62847 -cp &quot;/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.0.600.202301161003/tools/bin&quot; --frequency 24000 --swd" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="stlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-p 62847 -cp &quot;/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.0.600.202301161003/tools/bin&quot; --frequency 24000 --swd" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::62847" executable="/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.linux64_2.0.500.202301161003/tools/bin/ST-LINK_gdbserver" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/stm32g474.xml b/.idea/runConfigurations/stm32g474.xml
index d461cd60e..bbab2a5c5 100644
--- a/.idea/runConfigurations/stm32g474.xml
+++ b/.idea/runConfigurations/stm32g474.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/stm32h743.xml b/.idea/runConfigurations/stm32h743.xml
index c438422ce..7581ddf9b 100644
--- a/.idea/runConfigurations/stm32h743.xml
+++ b/.idea/runConfigurations/stm32h743.xml
@@ -1,6 +1,6 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stm32h743" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32h743xi&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="mcb1800" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
-    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+  <configuration default="false" name="stm32h743" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32h743xi&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
     <method v="2">

From 3a5f43528e6f678cd44b0e4691152a4f6bbb1e38 Mon Sep 17 00:00:00 2001
From: Andrew Hooper <ahooper@kos.net>
Date: Fri, 23 Jun 2023 11:51:58 -0400
Subject: [PATCH 1825/2085] Board support for STM32F407VETx

---
 .../stm32f407blackvet/STM32F407VETX_FLASH.ld  | 177 +++++++
 .../boards/stm32f407blackvet/board.cmake      |  18 +
 .../stm32f4/boards/stm32f407blackvet/board.h  | 107 ++++
 .../stm32f4/boards/stm32f407blackvet/board.mk |  16 +
 .../stm32f407blackvet/stm32f4xx_hal_conf.h    | 493 ++++++++++++++++++
 hw/bsp/stm32f4/family.cmake                   | 134 +++++
 hw/bsp/stm32f4/stm32f4xx_hal_conf.h           | 493 ++++++++++++++++++
 7 files changed, 1438 insertions(+)
 create mode 100644 hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETX_FLASH.ld
 create mode 100644 hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake
 create mode 100644 hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
 create mode 100644 hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk
 create mode 100644 hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h
 create mode 100644 hw/bsp/stm32f4/family.cmake
 create mode 100644 hw/bsp/stm32f4/stm32f4xx_hal_conf.h

diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETX_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETX_FLASH.ld
new file mode 100644
index 000000000..6dec5543a
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETX_FLASH.ld
@@ -0,0 +1,177 @@
+/**
+ ******************************************************************************
+ * @file      LinkerScript.ld
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     Linker script for STM32F407VETx Device from STM32F4 series
+ *                      512Kbytes FLASH
+ *                      64Kbytes CCMRAM
+ *                      128Kbytes RAM
+ *
+ *            Set heap size, stack size and stack location according
+ *            to application requirements.
+ *
+ *            Set memory bank area and size if external memory is used
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  CCMRAM    (xrw)    : ORIGIN = 0x10000000,   LENGTH = 64K
+  RAM    (xrw)    : ORIGIN = 0x20000000,   LENGTH = 128K
+  FLASH    (rx)    : ORIGIN = 0x8000000,   LENGTH = 512K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : {
+    . = ALIGN(4);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM : {
+    . = ALIGN(4);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(4);
+  } >FLASH
+
+  .preinit_array     :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .init_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  .fini_array :
+  {
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(4);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake
new file mode 100644
index 000000000..52cf95700
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake
@@ -0,0 +1,18 @@
+set(MCU_VARIANT stm32f407xx)
+set(JLINK_DEVICE stm32f407ve)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F407VETx_FLASH.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F407xx
+    HSE_VALUE=8000000
+    CORE_CM4
+          BOARD_TUD_RHPORT=0
+          BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
new file mode 100644
index 000000000..b7a6d96c2
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h
@@ -0,0 +1,107 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              GPIOA
+#define LED_PIN               GPIO_PIN_6
+#define LED_STATE_ON          1
+
+// Button
+#define BUTTON_PORT           GPIOE
+#define BUTTON_PIN            GPIO_PIN_4
+#define BUTTON_STATE_ACTIVE   0
+
+// Enable PA2 as the debug log UART
+// It is not routed to the ST/Link on the Discovery board.
+#define UART_DEV              USART2
+#define UART_GPIO_PORT        GPIOA
+#define UART_GPIO_AF          GPIO_AF7_USART2
+#define UART_TX_PIN           GPIO_PIN_2
+#define UART_RX_PIN           GPIO_PIN_3
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+static inline void board_clock_init(void)
+{
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+
+  /* Enable Power Control clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* The voltage scaling allows optimizing the power consumption when the device is
+     clocked below the maximum system frequency, to update the voltage scaling value
+     regarding system frequency refer to product datasheet.  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /* Enable HSE Oscillator and activate PLL with HSE as source */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/2000000;
+  RCC_OscInitStruct.PLL.PLLN = 168;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
+     clocks dividers */
+  RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+
+  // Enable clocks for LED, Button, Uart
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_USART2_CLK_ENABLE();
+}
+
+static inline void board_vbus_sense_init(void)
+{
+    // Black F407VET6 doesn't use VBUS sense (B device) explicitly disable it
+    USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
+    USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk
new file mode 100644
index 000000000..a184804d3
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk
@@ -0,0 +1,16 @@
+CFLAGS += -DSTM32F407xx
+
+# GCC
+GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s
+GCC_LD_FILE = $(BOARD_PATH)/STM32F407VGTx_FLASH.ld
+
+# IAR
+IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s
+IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f407xx_flash.icf
+
+
+# For flash-jlink target
+JLINK_DEVICE = stm32f407vg
+
+# flash target using on-board stlink
+flash: flash-stlink
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h
new file mode 100644
index 000000000..e24e782ea
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/stm32f4xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED      */
+/* #define HAL_CAN_MODULE_ENABLED      */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
+/* #define HAL_ETH_MODULE_ENABLED      */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED     */
+/* #define HAL_NOR_MODULE_ENABLED      */
+/* #define HAL_PCCARD_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED     */
+/* #define HAL_SDRAM_MODULE_ENABLED    */
+/* #define HAL_HASH_MODULE_ENABLED     */
+#define HAL_GPIO_MODULE_ENABLED
+/* #define HAL_EXTI_MODULE_ENABLED     */
+/* #define HAL_I2C_MODULE_ENABLED      */
+/* #define HAL_SMBUS_MODULE_ENABLED    */
+/* #define HAL_I2S_MODULE_ENABLED      */
+/* #define HAL_IWDG_MODULE_ENABLED     */
+/* #define HAL_LTDC_MODULE_ENABLED     */
+/* #define HAL_DSI_MODULE_ENABLED      */
+#define HAL_PWR_MODULE_ENABLED
+/* #define HAL_QSPI_MODULE_ENABLED     */
+#define HAL_RCC_MODULE_ENABLED
+/* #define HAL_RNG_MODULE_ENABLED      */
+/* #define HAL_RTC_MODULE_ENABLED      */
+/* #define HAL_SAI_MODULE_ENABLED      */
+/* #define HAL_SD_MODULE_ENABLED       */
+// #define HAL_SPI_MODULE_ENABLED
+/* #define HAL_TIM_MODULE_ENABLED      */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED    */
+/* #define HAL_IRDA_MODULE_ENABLED     */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED     */
+#define HAL_CORTEX_MODULE_ENABLED
+/* #define HAL_PCD_MODULE_ENABLED      */
+/* #define HAL_HCD_MODULE_ENABLED      */
+/* #define HAL_FMPI2C_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED  */
+/* #define HAL_DFSDM_MODULE_ENABLED    */
+/* #define HAL_LPTIM_MODULE_ENABLED    */
+/* #define HAL_MMC_MODULE_ENABLED      */
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake
new file mode 100644
index 000000000..7d9bbf331
--- /dev/null
+++ b/hw/bsp/stm32f4/family.cmake
@@ -0,0 +1,134 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY f4)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F4 CACHE INTERNAL "")
+
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET)
+  family_configure_common(${TARGET})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F4)
+  if (MCU_VARIANT STREQUAL "stm32f407xx")
+    target_sources(${TARGET}-tinyusb PUBLIC
+            ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+            )
+  else()
+    target_sources(${TARGET}-tinyusb PUBLIC
+            ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+            )
+  endif()
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(family_configure_device_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f4/stm32f4xx_hal_conf.h b/hw/bsp/stm32f4/stm32f4xx_hal_conf.h
new file mode 100644
index 000000000..e24e782ea
--- /dev/null
+++ b/hw/bsp/stm32f4/stm32f4xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+/* #define HAL_ADC_MODULE_ENABLED      */
+/* #define HAL_CAN_MODULE_ENABLED      */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED      */
+/* #define HAL_CRC_MODULE_ENABLED      */
+/* #define HAL_CEC_MODULE_ENABLED      */
+/* #define HAL_CRYP_MODULE_ENABLED     */
+/* #define HAL_DAC_MODULE_ENABLED      */
+/* #define HAL_DCMI_MODULE_ENABLED     */
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED    */
+/* #define HAL_ETH_MODULE_ENABLED      */
+#define HAL_FLASH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED     */
+/* #define HAL_NOR_MODULE_ENABLED      */
+/* #define HAL_PCCARD_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED     */
+/* #define HAL_SDRAM_MODULE_ENABLED    */
+/* #define HAL_HASH_MODULE_ENABLED     */
+#define HAL_GPIO_MODULE_ENABLED
+/* #define HAL_EXTI_MODULE_ENABLED     */
+/* #define HAL_I2C_MODULE_ENABLED      */
+/* #define HAL_SMBUS_MODULE_ENABLED    */
+/* #define HAL_I2S_MODULE_ENABLED      */
+/* #define HAL_IWDG_MODULE_ENABLED     */
+/* #define HAL_LTDC_MODULE_ENABLED     */
+/* #define HAL_DSI_MODULE_ENABLED      */
+#define HAL_PWR_MODULE_ENABLED
+/* #define HAL_QSPI_MODULE_ENABLED     */
+#define HAL_RCC_MODULE_ENABLED
+/* #define HAL_RNG_MODULE_ENABLED      */
+/* #define HAL_RTC_MODULE_ENABLED      */
+/* #define HAL_SAI_MODULE_ENABLED      */
+/* #define HAL_SD_MODULE_ENABLED       */
+// #define HAL_SPI_MODULE_ENABLED
+/* #define HAL_TIM_MODULE_ENABLED      */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED    */
+/* #define HAL_IRDA_MODULE_ENABLED     */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED     */
+#define HAL_CORTEX_MODULE_ENABLED
+/* #define HAL_PCD_MODULE_ENABLED      */
+/* #define HAL_HCD_MODULE_ENABLED      */
+/* #define HAL_FMPI2C_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED  */
+/* #define HAL_DFSDM_MODULE_ENABLED    */
+/* #define HAL_LPTIM_MODULE_ENABLED    */
+/* #define HAL_MMC_MODULE_ENABLED      */
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  (32000U)
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  (32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    (12288000U) /*!< Value of the External oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (0x0FU) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS             0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */
+#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */
+#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */
+
+#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */
+#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */
+
+#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */
+#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

From edbf06aaab9ac7cf098f1170a7a9861f5cf3572e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 17:35:37 +0700
Subject: [PATCH 1826/2085] separate iar and gcc build for clean make, also add
 cpu specific make

---
 examples/device/cdc_msc/Makefile      |   6 +-
 examples/make.mk                      |  89 ++++------------
 examples/rules.mk                     | 144 ++------------------------
 hw/bsp/stm32h7/family.mk              |  13 +--
 src/tinyusb.mk                        |  19 ++++
 tools/make/cpu/cortex-m7.mk           |  13 ++-
 tools/make/toolchain/arm_gcc.mk       |  77 ++++++++++++++
 tools/make/toolchain/arm_gcc_rules.mk |  78 ++++++++++++++
 tools/make/toolchain/arm_iar.mk       |  13 +++
 tools/make/toolchain/arm_iar_rules.mk |  44 ++++++++
 10 files changed, 275 insertions(+), 221 deletions(-)
 create mode 100644 src/tinyusb.mk
 create mode 100644 tools/make/toolchain/arm_gcc.mk
 create mode 100644 tools/make/toolchain/arm_gcc_rules.mk
 create mode 100644 tools/make/toolchain/arm_iar.mk
 create mode 100644 tools/make/toolchain/arm_iar_rules.mk

diff --git a/examples/device/cdc_msc/Makefile b/examples/device/cdc_msc/Makefile
index da088ea6b..429959e70 100644
--- a/examples/device/cdc_msc/Makefile
+++ b/examples/device/cdc_msc/Makefile
@@ -5,7 +5,11 @@ INC += \
 	$(TOP)/hw \
 
 # Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
+EXAMPLE_SOURCE += \
+  src/main.c \
+  src/msc_disk.c \
+  src/usb_descriptors.c \
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 include ../../rules.mk
diff --git a/examples/make.mk b/examples/make.mk
index 28ebc62da..4fcde83c8 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -2,6 +2,7 @@
 # Common make definition for all examples
 # ---------------------------------------
 
+# Supported toolchain: gcc, iar
 TOOLCHAIN ?= gcc
 
 #-------------- TOP and CURRENT_PATH ------------
@@ -32,13 +33,6 @@ CMDEXE := 1
 SHELL := cmd.exe
 endif
 
-
-# Build directory
-BUILD := _build/$(BOARD)
-
-PROJECT := $(notdir $(CURDIR))
-BIN := $(TOP)/_bin/$(BOARD)/$(notdir $(CURDIR))
-
 # Handy check parameter function
 check_defined = \
     $(strip $(foreach 1,$1, \
@@ -47,6 +41,13 @@ __check_defined = \
     $(if $(value $1),, \
     $(error Undefined make flag: $1$(if $2, ($2))))
 
+
+# Build directory
+BUILD := _build/$(BOARD)
+
+PROJECT := $(notdir $(CURDIR))
+BIN := $(TOP)/_bin/$(BOARD)/$(notdir $(CURDIR))
+
 #-------------- Select the board to build for. ------------
 
 # Board without family
@@ -81,25 +82,12 @@ endif
 # Can be set by board, default to ARM GCC
 CROSS_COMPILE ?= arm-none-eabi-
 
-ifeq ($(CC),iccarm)
-USE_IAR = 1
+ifeq ($(TOOLCHAIN),iar)
+CC := iccarm
 endif
 
-ifdef USE_IAR
-  AS = iasmarm
-  LD = ilinkarm
-  OBJCOPY = ielftool
-  SIZE = size
-
-else
-  CC = $(CROSS_COMPILE)gcc
-  CXX = $(CROSS_COMPILE)g++
-  AS = $(CC) -x assembler-with-cpp
-  LD = $(CC)
-
-  GDB = $(CROSS_COMPILE)gdb
-  OBJCOPY = $(CROSS_COMPILE)objcopy
-  SIZE = $(CROSS_COMPILE)size
+ifeq ($(CC),iccarm)
+USE_IAR = 1
 endif
 
 ifeq ($(CMDEXE),1)
@@ -115,57 +103,19 @@ else
 endif
 
 #-------------- Source files and compiler flags --------------
+# tinyusb makefile
+include $(TOP)/src/tinyusb.mk
 
 # Include all source C in family & board folder
 SRC_C += hw/bsp/board.c
 SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(BOARD_PATH)/*.c))
 
-INC   += $(TOP)/$(FAMILY_PATH)
+SRC_C += $(TINYUSB_SRC_C)
 
-# Allow for -Os to be changed by board makefiles in case -Os is not allowed
-CFLAGS_OPTIMIZED ?= -Os
+INC += \
+  $(TOP)/$(FAMILY_PATH) \
+  $(TOP)/src \
 
-# GCC Compiler Flags
-GCC_CFLAGS += \
-  -ggdb \
-  -fdata-sections \
-  -ffunction-sections \
-  -fsingle-precision-constant \
-  -fno-strict-aliasing \
-  -Wall \
-  -Wextra \
-  -Werror \
-  -Wfatal-errors \
-  -Wdouble-promotion \
-  -Wstrict-prototypes \
-  -Wstrict-overflow \
-  -Werror-implicit-function-declaration \
-  -Wfloat-equal \
-  -Wundef \
-  -Wshadow \
-  -Wwrite-strings \
-  -Wsign-compare \
-  -Wmissing-format-attribute \
-  -Wunreachable-code \
-  -Wcast-align \
-  -Wcast-function-type \
-  -Wcast-qual \
-  -Wnull-dereference \
-  -Wuninitialized \
-  -Wunused \
-  -Wreturn-type \
-  -Wredundant-decls
-
-# conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion
-#  -Wconversion
-
-# Debugging/Optimization
-ifeq ($(DEBUG), 1)
-  GCC_CFLAGS += -O0
-  NO_LTO = 1
-else
-  GCC_CFLAGS += $(CFLAGS_OPTIMIZED)
-endif
 
 # Log level is mapped to TUSB DEBUG option
 ifneq ($(LOG),)
@@ -186,3 +136,6 @@ ifeq ($(LOGGER),rtt)
 else ifeq ($(LOGGER),swo)
   CFLAGS += -DLOGGER_SWO
 endif
+
+# toolchain specific
+include $(TOP)/tools/make/toolchain/arm_$(TOOLCHAIN).mk
diff --git a/examples/rules.mk b/examples/rules.mk
index 5727ab7e3..e50c0ec7d 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -13,87 +13,8 @@ ifeq (,$(findstring $(FAMILY),espressif rp2040))
 # Compiler Flags
 # ---------------------------------------
 
-LIBS_GCC ?= -lgcc -lm -lnosys
-
-# libc
-LIBS += $(LIBS_GCC)
-
-ifneq ($(BOARD), spresense)
-LIBS += -lc
-endif
-
-# TinyUSB Stack source
-SRC_C += \
-	src/tusb.c \
-	src/common/tusb_fifo.c \
-	src/device/usbd.c \
-	src/device/usbd_control.c \
-	src/typec/usbc.c \
-	src/class/audio/audio_device.c \
-	src/class/cdc/cdc_device.c \
-	src/class/dfu/dfu_device.c \
-	src/class/dfu/dfu_rt_device.c \
-	src/class/hid/hid_device.c \
-	src/class/midi/midi_device.c \
-	src/class/msc/msc_device.c \
-	src/class/net/ecm_rndis_device.c \
-	src/class/net/ncm_device.c \
-	src/class/usbtmc/usbtmc_device.c \
-	src/class/video/video_device.c \
-	src/class/vendor/vendor_device.c
-
-# TinyUSB stack include
-INC += $(TOP)/src
-
 CFLAGS += $(addprefix -I,$(INC))
 
-ifdef USE_IAR
-
-SRC_S += $(IAR_SRC_S)
-
-ASFLAGS := $(CFLAGS) $(IAR_ASFLAGS) $(ASFLAGS) -S
-IAR_LDFLAGS += --config $(TOP)/$(IAR_LD_FILE)
-CFLAGS += $(IAR_CFLAGS) -e --debug --silent
-
-else
-
-SRC_S += $(GCC_SRC_S)
-
-CFLAGS += $(GCC_CFLAGS) -MD
-
-# LTO makes it difficult to analyze map file for optimizing size purpose
-# We will run this option in ci
-ifeq ($(NO_LTO),1)
-CFLAGS := $(filter-out -flto,$(CFLAGS))
-endif
-
-ifneq ($(CFLAGS_SKIP),)
-CFLAGS := $(filter-out $(CFLAGS_SKIP),$(CFLAGS))
-endif
-
-LDFLAGS += $(CFLAGS) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections
-
-# Some toolchain such as renesas rx does not support --print-memory-usage flags
-ifneq ($(FAMILY),rx)
-LDFLAGS += -Wl,--print-memory-usage
-endif
-
-ifdef LD_FILE
-LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE)
-endif
-
-ifdef GCC_LD_FILE
-LDFLAGS += -Wl,-T,$(TOP)/$(GCC_LD_FILE)
-endif
-
-ifneq ($(SKIP_NANOLIB), 1)
-LDFLAGS += --specs=nosys.specs --specs=nano.specs
-endif
-
-ASFLAGS += $(CFLAGS)
-
-endif # USE_IAR
-
 # Verbose mode
 ifeq ("$(V)","1")
 $(info CFLAGS  $(CFLAGS) ) $(info )
@@ -101,15 +22,6 @@ $(info LDFLAGS $(LDFLAGS)) $(info )
 $(info ASFLAGS $(ASFLAGS)) $(info )
 endif
 
-# Assembly files can be name with upper case .S, convert it to .s
-SRC_S := $(SRC_S:.S=.s)
-
-# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
-# assembly file should be placed first in linking order
-# '_asm' suffix is added to object of assembly file
-OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
-OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
-
 # ---------------------------------------
 # Rules
 # ---------------------------------------
@@ -118,15 +30,6 @@ all: $(BUILD)/$(PROJECT).bin $(BUILD)/$(PROJECT).hex size
 
 uf2: $(BUILD)/$(PROJECT).uf2
 
-OBJ_DIRS = $(sort $(dir $(OBJ)))
-$(OBJ): | $(OBJ_DIRS)
-$(OBJ_DIRS):
-ifeq ($(CMDEXE),1)
-	-@$(MKDIR) $(subst /,\,$@)
-else
-	@$(MKDIR) -p $@
-endif
-
 # We set vpath to point to the top of the tree so that the source files
 # can be located. By following this scheme, it allows a single build rule
 # to be used to compile all .c files.
@@ -134,49 +37,16 @@ vpath %.c . $(TOP)
 vpath %.s . $(TOP)
 vpath %.S . $(TOP)
 
-# Compile .c file
-$(BUILD)/obj/%.o: %.c
-	@echo CC $(notdir $@)
-	@$(CC) $(CFLAGS) -c -o $@ $<
+include $(TOP)/tools/make/toolchain/arm_$(TOOLCHAIN)_rules.mk
 
-# ASM sources lower case .s
-$(BUILD)/obj/%_asm.o: %.s
-	@echo AS $(notdir $@)
-	@$(AS) $(ASFLAGS) -c -o $@ $<
-
-# ASM sources upper case .S
-$(BUILD)/obj/%_asm.o: %.S
-	@echo AS $(notdir $@)
-	@$(AS) $(ASFLAGS) -c -o $@ $<
-
-ifdef USE_IAR
-# IAR Compiler
-$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	@$(OBJCOPY) --silent --bin $^ $@
-
-$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	@$(OBJCOPY) --silent --ihex $^ $@
-
-$(BUILD)/$(PROJECT).elf: $(OBJ)
-	@echo LINK $@
-	@$(LD) -o $@ $(IAR_LDFLAGS) $^
 
+OBJ_DIRS = $(sort $(dir $(OBJ)))
+$(OBJ): | $(OBJ_DIRS)
+$(OBJ_DIRS):
+ifeq ($(CMDEXE),1)
+	-@$(MKDIR) $(subst /,\,$@)
 else
-# GCC based compiler
-$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	@$(OBJCOPY) -O binary $^ $@
-
-$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
-	@echo CREATE $@
-	@$(OBJCOPY) -O ihex $^ $@
-
-$(BUILD)/$(PROJECT).elf: $(OBJ)
-	@echo LINK $@
-	@$(LD) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group
-
+	@$(MKDIR) -p $@
 endif
 
 # UF2 generation, iMXRT need to strip to text only before conversion
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index c11240207..48730bbb4 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -6,6 +6,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m7
 
 # --------------
 # Compiler Flags
@@ -29,20 +30,11 @@ endif
 # GCC Flags
 GCC_CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
   -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
 GCC_CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=unused-parameter
 
-# IAR Flags
-IAR_CFLAGS += --cpu cortex-m7 --fpu VFPv5_D16
-IAR_ASFLAGS += --cpu cortex-m7 --fpu VFPv5_D16
-
 # -----------------
 # Sources & Include
 # -----------------
@@ -66,6 +58,3 @@ INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
diff --git a/src/tinyusb.mk b/src/tinyusb.mk
new file mode 100644
index 000000000..85052f90f
--- /dev/null
+++ b/src/tinyusb.mk
@@ -0,0 +1,19 @@
+# C source files
+TINYUSB_SRC_C += \
+	src/tusb.c \
+	src/common/tusb_fifo.c \
+	src/device/usbd.c \
+	src/device/usbd_control.c \
+	src/typec/usbc.c \
+	src/class/audio/audio_device.c \
+	src/class/cdc/cdc_device.c \
+	src/class/dfu/dfu_device.c \
+	src/class/dfu/dfu_rt_device.c \
+	src/class/hid/hid_device.c \
+	src/class/midi/midi_device.c \
+	src/class/msc/msc_device.c \
+	src/class/net/ecm_rndis_device.c \
+	src/class/net/ncm_device.c \
+	src/class/usbtmc/usbtmc_device.c \
+	src/class/video/video_device.c \
+	src/class/vendor/vendor_device.c \
diff --git a/tools/make/cpu/cortex-m7.mk b/tools/make/cpu/cortex-m7.mk
index 504ffd486..0e53cbe9c 100644
--- a/tools/make/cpu/cortex-m7.mk
+++ b/tools/make/cpu/cortex-m7.mk
@@ -5,8 +5,15 @@ ifeq ($(TOOLCHAIN),gcc)
     -mfloat-abi=hard \
     -mfpu=fpv5-d16 \
 
-  #set(FREERTOS_PORT GCC_ARM_CM7 CACHE INTERNAL "")
-  FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
 else ifeq ($(TOOLCHAIN),iar)
-  # TODO support IAR
+  CFLAGS += \
+  	--cpu cortex-m7 \
+  	--fpu VFPv5_D16 \
+
+  ASFLAGS += \
+		--cpu cortex-m7 \
+		--fpu VFPv5_D16 \
+
 endif
+
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
diff --git a/tools/make/toolchain/arm_gcc.mk b/tools/make/toolchain/arm_gcc.mk
new file mode 100644
index 000000000..d5ee98def
--- /dev/null
+++ b/tools/make/toolchain/arm_gcc.mk
@@ -0,0 +1,77 @@
+# makefile for arm gcc toolchain
+
+CC = $(CROSS_COMPILE)gcc
+CXX = $(CROSS_COMPILE)g++
+AS = $(CC) -x assembler-with-cpp
+LD = $(CC)
+
+GDB = $(CROSS_COMPILE)gdb
+OBJCOPY = $(CROSS_COMPILE)objcopy
+SIZE = $(CROSS_COMPILE)size
+
+# CPU specific flags
+include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
+
+# ---------------------------------------
+# Compiler Flags
+# ---------------------------------------
+CFLAGS += \
+  -MD \
+  -ggdb \
+  -fdata-sections \
+  -ffunction-sections \
+  -fsingle-precision-constant \
+  -fno-strict-aliasing \
+  -Wall \
+  -Wextra \
+  -Werror \
+  -Wfatal-errors \
+  -Wdouble-promotion \
+  -Wstrict-prototypes \
+  -Wstrict-overflow \
+  -Werror-implicit-function-declaration \
+  -Wfloat-equal \
+  -Wundef \
+  -Wshadow \
+  -Wwrite-strings \
+  -Wsign-compare \
+  -Wmissing-format-attribute \
+  -Wunreachable-code \
+  -Wcast-align \
+  -Wcast-function-type \
+  -Wcast-qual \
+  -Wnull-dereference \
+  -Wuninitialized \
+  -Wunused \
+  -Wreturn-type \
+  -Wredundant-decls \
+
+# conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion
+#  -Wconversion
+
+# Size Optimization as default
+CFLAGS_OPTIMIZED ?= -Os
+
+# Debugging/Optimization
+ifeq ($(DEBUG), 1)
+  CFLAGS += -O0
+  NO_LTO = 1
+else
+  CFLAGS += $(CFLAGS_OPTIMIZED)
+endif
+
+# ---------------------------------------
+# Linker Flags
+# ---------------------------------------
+LDFLAGS += \
+  -Wl,-Map=$@.map \
+  -Wl,-cref \
+  -Wl,-gc-sections \
+
+# Some toolchain such as renesas rx does not support --print-memory-usage flags
+ifneq ($(FAMILY),rx)
+LDFLAGS += -Wl,--print-memory-usage
+endif
+
+LDFLAGS += \
+  -Wl,--print-memory-usage \
diff --git a/tools/make/toolchain/arm_gcc_rules.mk b/tools/make/toolchain/arm_gcc_rules.mk
new file mode 100644
index 000000000..a39caf351
--- /dev/null
+++ b/tools/make/toolchain/arm_gcc_rules.mk
@@ -0,0 +1,78 @@
+SRC_S += $(GCC_SRC_S)
+
+# Assembly files can be name with upper case .S, convert it to .s
+SRC_S := $(SRC_S:.S=.s)
+
+# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
+# assembly file should be placed first in linking order
+# '_asm' suffix is added to object of assembly file
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
+
+CFLAGS += $(GCC_CFLAGS) -MD
+
+# LTO makes it difficult to analyze map file for optimizing size purpose
+# We will run this option in ci
+ifeq ($(NO_LTO),1)
+CFLAGS := $(filter-out -flto,$(CFLAGS))
+endif
+
+ifneq ($(CFLAGS_SKIP),)
+CFLAGS := $(filter-out $(CFLAGS_SKIP),$(CFLAGS))
+endif
+
+LDFLAGS += $(CFLAGS)
+
+ifdef LD_FILE
+LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE)
+endif
+
+ifdef GCC_LD_FILE
+LDFLAGS += -Wl,-T,$(TOP)/$(GCC_LD_FILE)
+endif
+
+ifneq ($(SKIP_NANOLIB), 1)
+LDFLAGS += --specs=nosys.specs --specs=nano.specs
+endif
+
+ASFLAGS += $(CFLAGS)
+
+LIBS_GCC ?= -lgcc -lm -lnosys
+
+# libc
+LIBS += $(LIBS_GCC)
+
+ifneq ($(BOARD), spresense)
+LIBS += -lc
+endif
+
+# ---------------------------------------
+# Rules
+# ---------------------------------------
+
+# Compile .c file
+$(BUILD)/obj/%.o: %.c
+	@echo CC $(notdir $@)
+	@$(CC) $(CFLAGS) -c -o $@ $<
+
+# ASM sources lower case .s
+$(BUILD)/obj/%_asm.o: %.s
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+# ASM sources upper case .S
+$(BUILD)/obj/%_asm.o: %.S
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) -O binary $^ $@
+
+$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) -O ihex $^ $@
+
+$(BUILD)/$(PROJECT).elf: $(OBJ)
+	@echo LINK $@
+	@$(LD) -o $@ $(LDFLAGS) $^ -Wl,--start-group $(LIBS) -Wl,--end-group
diff --git a/tools/make/toolchain/arm_iar.mk b/tools/make/toolchain/arm_iar.mk
new file mode 100644
index 000000000..42b31cfd3
--- /dev/null
+++ b/tools/make/toolchain/arm_iar.mk
@@ -0,0 +1,13 @@
+# makefile for arm iar toolchain
+AS = iasmarm
+LD = ilinkarm
+OBJCOPY = ielftool --silent
+SIZE = size
+
+include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
+
+# Enable extension mode (gcc compatible)
+CFLAGS += -e --debug --silent
+
+# silent mode
+ASFLAGS += -S
diff --git a/tools/make/toolchain/arm_iar_rules.mk b/tools/make/toolchain/arm_iar_rules.mk
new file mode 100644
index 000000000..4b5cc90e3
--- /dev/null
+++ b/tools/make/toolchain/arm_iar_rules.mk
@@ -0,0 +1,44 @@
+SRC_S += $(IAR_SRC_S)
+
+# Assembly files can be name with upper case .S, convert it to .s
+SRC_S := $(SRC_S:.S=.s)
+
+# Due to GCC LTO bug https://bugs.launchpad.net/gcc-arm-embedded/+bug/1747966
+# assembly file should be placed first in linking order
+# '_asm' suffix is added to object of assembly file
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
+OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
+
+# Linker script
+LDFLAGS += --config $(TOP)/$(IAR_LD_FILE)
+
+# ---------------------------------------
+# Rules
+# ---------------------------------------
+
+# Compile .c file
+$(BUILD)/obj/%.o: %.c
+	@echo CC $(notdir $@)
+	@$(CC) $(CFLAGS) -c -o $@ $<
+
+# ASM sources lower case .s
+$(BUILD)/obj/%_asm.o: %.s
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+# ASM sources upper case .S
+$(BUILD)/obj/%_asm.o: %.S
+	@echo AS $(notdir $@)
+	@$(AS) $(ASFLAGS) -c -o $@ $<
+
+$(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) --bin $^ $@
+
+$(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
+	@echo CREATE $@
+	@$(OBJCOPY) --ihex $^ $@
+
+$(BUILD)/$(PROJECT).elf: $(OBJ)
+	@echo LINK $@
+	@$(LD) -o $@ $(LDFLAGS) $^

From dbf7534cd4bcc3a11c1159a42f252d4166bf3afb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 18:09:05 +0700
Subject: [PATCH 1827/2085] update all stm32 to use new enhance make

---
 hw/bsp/stm32f0/family.mk                        | 12 +-----------
 hw/bsp/stm32f1/family.mk                        | 15 +--------------
 .../boards/stm32f207nucleo/stm32f207nucleo.c    |  2 +-
 hw/bsp/stm32f2/family.mk                        | 14 +++++---------
 hw/bsp/stm32f3/family.mk                        |  9 +--------
 hw/bsp/stm32f4/family.mk                        | 13 +------------
 hw/bsp/stm32f7/family.mk                        | 13 +------------
 hw/bsp/stm32g0/family.mk                        | 12 +-----------
 hw/bsp/stm32g4/family.mk                        | 13 +------------
 hw/bsp/stm32l0/family.mk                        |  8 +-------
 hw/bsp/stm32l4/family.mk                        | 13 +------------
 hw/bsp/stm32u5/family.mk                        | 10 +---------
 hw/bsp/stm32wb/family.mk                        |  9 +--------
 tools/make/cpu/cortex-m0.mk                     | 14 ++++++++++++++
 tools/make/cpu/cortex-m0plus.mk                 | 14 ++++++++++++++
 tools/make/cpu/cortex-m3.mk                     | 17 +++++++++++++++++
 tools/make/cpu/cortex-m33.mk                    | 14 +++++++++-----
 tools/make/cpu/cortex-m4.mk                     |  7 ++++---
 18 files changed, 75 insertions(+), 134 deletions(-)
 create mode 100644 tools/make/cpu/cortex-m0.mk
 create mode 100644 tools/make/cpu/cortex-m0plus.mk
 create mode 100644 tools/make/cpu/cortex-m3.mk

diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 08e349a81..200c4f757 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -6,6 +6,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0
 
 # --------------
 # Compiler Flags
@@ -17,19 +18,11 @@ CFLAGS += \
 # GCC Flags
 GCC_CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0 \
-  -mfloat-abi=soft \
   -nostdlib -nostartfiles \
 
 # suppress warning caused by vendor mcu driver
 GCC_CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
 
-# IAR Flags
-IAR_CFLAGS += --cpu cortex-m0
-IAR_ASFLAGS += --cpu cortex-m0
-
 # ------------------------
 # All source paths should be relative to the top level.
 # ------------------------
@@ -51,6 +44,3 @@ INC += \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index cd1d587f1..4813fba2b 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -5,6 +5,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
 
 # --------------
 # Compiler Flags
@@ -15,16 +16,8 @@ CFLAGS += \
 # GCC Flags
 GCC_CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -mfloat-abi=soft \
   -nostdlib -nostartfiles \
 
-# IAR Flags
-IAR_CFLAGS += --cpu cortex-m3
-IAR_ASFLAGS += --cpu cortex-m3
-
 # ------------------------
 # All source paths should be relative to the top level.
 # ------------------------
@@ -43,12 +36,6 @@ INC += \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
-
-# For flash-jlink target
-JLINK_DEVICE = stm32f103c8
-
 # flash target ROM bootloader
 flash-dfu-util: $(BUILD)/$(PROJECT).bin
 	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c b/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
index 48203b787..020f21cb1 100644
--- a/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
@@ -203,7 +203,7 @@ uint32_t board_millis(void)
 
 void HardFault_Handler (void)
 {
-  asm("bkpt");
+  __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
diff --git a/hw/bsp/stm32f2/family.mk b/hw/bsp/stm32f2/family.mk
index 7ca378548..fd27c0e68 100644
--- a/hw/bsp/stm32f2/family.mk
+++ b/hw/bsp/stm32f2/family.mk
@@ -9,18 +9,17 @@ DEPS_SUBMODULES += \
 	$(ST_HAL_DRIVER)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
 
 CFLAGS += \
+	-DCFG_TUSB_MCU=OPT_MCU_STM32F2
+
+GCC_CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -mfloat-abi=soft \
   -nostdlib -nostartfiles \
-  -DCFG_TUSB_MCU=OPT_MCU_STM32F2
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=sign-compare
+GCC_CFLAGS += -Wno-error=sign-compare
 
 SRC_C += \
   src/portable/synopsys/dwc2/dcd_dwc2.c \
@@ -36,6 +35,3 @@ INC += \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
   $(TOP)/$(BOARD_PATH)
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
diff --git a/hw/bsp/stm32f3/family.mk b/hw/bsp/stm32f3/family.mk
index f3b21d530..a740e9012 100644
--- a/hw/bsp/stm32f3/family.mk
+++ b/hw/bsp/stm32f3/family.mk
@@ -9,14 +9,10 @@ DEPS_SUBMODULES += \
 	$(ST_HAL_DRIVER)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F3
 
@@ -37,6 +33,3 @@ INC += \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc \
   $(TOP)/$(BOARD_PATH)
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 394c4a72f..9c132fd21 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -6,6 +6,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 # --------------
 # Compiler Flags
@@ -16,20 +17,11 @@ CFLAGS += \
 # GCC Flags
 GCC_CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
 GCC_CFLAGS += -Wno-error=cast-align
 
-# IAR Flags
-IAR_CFLAGS += --cpu cortex-m4 --fpu VFPv4
-IAR_ASFLAGS += --cpu cortex-m4 --fpu VFPv4
-
 # -----------------
 # Sources & Include
 # -----------------
@@ -51,8 +43,5 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index b44381586..0b3b641d8 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -6,6 +6,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m7
 
 # --------------
 # Compiler Flags
@@ -29,20 +30,11 @@ endif
 # GCC Flags
 GCC_CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m7 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-d16 \
   -nostdlib -nostartfiles
 
 # mcu driver cause following warnings
 GCC_CFLAGS += -Wno-error=shadow -Wno-error=cast-align
 
-# IAR Flags
-IAR_CFLAGS += --cpu cortex-m7 --fpu VFPv5_D16
-IAR_ASFLAGS += --cpu cortex-m7 --fpu VFPv5_D16
-
 # -----------------
 # Sources & Include
 # -----------------
@@ -64,6 +56,3 @@ INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk
index 76f59fc34..76f1524e5 100644
--- a/hw/bsp/stm32g0/family.mk
+++ b/hw/bsp/stm32g0/family.mk
@@ -5,6 +5,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 # --------------
 # Compiler Flags
@@ -15,19 +16,11 @@ CFLAGS += \
 # GCC Flags
 GCC_CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -mfloat-abi=soft \
   -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
 GCC_CFLAGS += -Wno-error=cast-align
 
-# IAR Flags
-IAR_CFLAGS += --cpu cortex-m0
-IAR_ASFLAGS += --cpu cortex-m0
-
 # -----------------
 # Sources & Include
 # -----------------
@@ -50,8 +43,5 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk
index a4b644245..8ee453aed 100644
--- a/hw/bsp/stm32g4/family.mk
+++ b/hw/bsp/stm32g4/family.mk
@@ -6,6 +6,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 # --------------
 # Compiler Flags
@@ -16,20 +17,11 @@ CFLAGS += \
 # GCC Flags
 GCC_CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
 
 # suppress warning caused by vendor mcu driver
 GCC_CFLAGS += -Wno-error=cast-align
 
-# IAR Flags
-IAR_CFLAGS += --cpu cortex-m4 --fpu VFPv4
-IAR_ASFLAGS += --cpu cortex-m4 --fpu VFPv4
-
 # -----------------
 # Sources & Include
 # -----------------
@@ -53,8 +45,5 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32l0/family.mk b/hw/bsp/stm32l0/family.mk
index f069ae8f0..43f567b50 100644
--- a/hw/bsp/stm32l0/family.mk
+++ b/hw/bsp/stm32l0/family.mk
@@ -8,13 +8,10 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
-  -mfloat-abi=soft \
   -nostdlib -nostartfiles \
   -DCFG_EXAMPLE_MSC_READONLY \
   -DCFG_EXAMPLE_VIDEO_READONLY \
@@ -42,6 +39,3 @@ INC += \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index 0e84d1af0..4392c6766 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -5,6 +5,7 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 # --------------
 # Compiler Flags
@@ -15,20 +16,11 @@ CFLAGS += \
 # GCC Flags
 GCC_CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
 GCC_CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 
-# IAR Flags
-IAR_CFLAGS += --cpu cortex-m4 --fpu VFPv4
-IAR_ASFLAGS += --cpu cortex-m4 --fpu VFPv4
-
 # -----------------
 # Sources & Include
 # -----------------
@@ -54,8 +46,5 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc \
 	$(TOP)/$(BOARD_PATH)
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index e1c496dee..9174fe96a 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -5,21 +5,16 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m33 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-sp-d16 \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32U5
 
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=undef -Wno-error=unused-parameter
 
-#src/portable/st/synopsys/dcd_synopsys.c
 SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
@@ -38,8 +33,5 @@ INC += \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc \
 	$(TOP)/$(BOARD_PATH)
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32wb/family.mk b/hw/bsp/stm32wb/family.mk
index 97210889c..bc3afcaff 100644
--- a/hw/bsp/stm32wb/family.mk
+++ b/hw/bsp/stm32wb/family.mk
@@ -6,14 +6,10 @@ ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
 ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_STM32WB
 
@@ -37,8 +33,5 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/tools/make/cpu/cortex-m0.mk b/tools/make/cpu/cortex-m0.mk
new file mode 100644
index 000000000..c264802c8
--- /dev/null
+++ b/tools/make/cpu/cortex-m0.mk
@@ -0,0 +1,14 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m0 \
+    -mfloat-abi=soft \
+
+else ifeq ($(TOOLCHAIN),iar)
+  # IAR Flags
+  CFLAGS += --cpu cortex-m0
+  ASFLAGS += --cpu cortex-m0
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/tools/make/cpu/cortex-m0plus.mk b/tools/make/cpu/cortex-m0plus.mk
new file mode 100644
index 000000000..626f7156e
--- /dev/null
+++ b/tools/make/cpu/cortex-m0plus.mk
@@ -0,0 +1,14 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m0plus \
+    -mfloat-abi=soft \
+
+else ifeq ($(TOOLCHAIN),iar)
+  # IAR Flags
+  CFLAGS += --cpu cortex-m0+
+  ASFLAGS += --cpu cortex-m0+
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/tools/make/cpu/cortex-m3.mk b/tools/make/cpu/cortex-m3.mk
new file mode 100644
index 000000000..c81cbace6
--- /dev/null
+++ b/tools/make/cpu/cortex-m3.mk
@@ -0,0 +1,17 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mthumb \
+    -mcpu=cortex-m3 \
+    -mfloat-abi=soft \
+
+else ifeq ($(TOOLCHAIN),iar)
+  # IAR Flags
+  CFLAGS += \
+    --cpu cortex-m3 \
+
+  ASFLAGS += \
+     --cpu cortex-m3
+endif
+
+# For freeRTOS port source
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
diff --git a/tools/make/cpu/cortex-m33.mk b/tools/make/cpu/cortex-m33.mk
index 3d12b01fd..240ed0d49 100644
--- a/tools/make/cpu/cortex-m33.mk
+++ b/tools/make/cpu/cortex-m33.mk
@@ -5,10 +5,14 @@ ifeq ($(TOOLCHAIN),gcc)
     -mfloat-abi=hard \
     -mfpu=fpv5-sp-d16 \
 
-    #-mfpu=fpv5-d16 \
-
-  #set(FREERTOS_PORT GCC_ARM_CM33_NONSECURE CACHE INTERNAL "")
-  FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
 else ifeq ($(TOOLCHAIN),iar)
-  # TODO support IAR
+	CFLAGS += \
+		--cpu cortex-m33 \
+		--fpu VFPv5-SP \
+
+	ASFLAGS += \
+		--cpu cortex-m33 \
+		--fpu VFPv5-SP \
 endif
+
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
diff --git a/tools/make/cpu/cortex-m4.mk b/tools/make/cpu/cortex-m4.mk
index 890feefe3..fabe05632 100644
--- a/tools/make/cpu/cortex-m4.mk
+++ b/tools/make/cpu/cortex-m4.mk
@@ -5,8 +5,9 @@ ifeq ($(TOOLCHAIN),gcc)
     -mfloat-abi=hard \
     -mfpu=fpv4-sp-d16 \
 
-  #set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
-  FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
 else ifeq ($(TOOLCHAIN),iar)
-  # TODO support IAR
+  CFLAGS += --cpu cortex-m4 --fpu VFPv4
+  ASFLAGS += --cpu cortex-m4 --fpu VFPv4
 endif
+
+FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F

From b59b65d2ed0f6fa14b18b7bc233309d9b9710898 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 18:26:51 +0700
Subject: [PATCH 1828/2085] rename to kinetis_k32l2, rename OPT_MCU_KINETIS_K32
 to OPT_MCU_KINETIS_K32L

---
 .github/workflows/build_arm.yml                        |  2 +-
 hw/bsp/board_mcu.h                                     |  2 +-
 hw/bsp/imxrt/family.mk                                 |  2 +-
 .../boards/frdm_k32l2a4s/board.h                       |  0
 .../boards/frdm_k32l2a4s/board.mk                      |  7 +------
 .../boards/frdm_k32l2a4s/frdm_k32l2a4s.c               |  0
 .../boards/frdm_k32l2b/board.h                         |  0
 .../boards/frdm_k32l2b/board.mk                        |  7 +------
 .../boards/frdm_k32l2b/frdm_k32l2b.c                   |  0
 .../boards/kuiic/K32L2B31xxxxA_flash.ld                |  0
 .../boards/kuiic/board.h                               |  0
 .../boards/kuiic/board.mk                              | 10 +---------
 .../boards/kuiic/kuiic.c                               |  0
 hw/bsp/{kinetis_k32l => kinetis_k32l2}/family.mk       |  8 ++++----
 src/common/tusb_mcu.h                                  |  2 +-
 src/tusb_option.h                                      |  3 ++-
 tools/get_deps.py                                      |  4 ++--
 17 files changed, 15 insertions(+), 32 deletions(-)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/boards/frdm_k32l2a4s/board.h (100%)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/boards/frdm_k32l2a4s/board.mk (75%)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/boards/frdm_k32l2a4s/frdm_k32l2a4s.c (100%)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/boards/frdm_k32l2b/board.h (100%)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/boards/frdm_k32l2b/board.mk (74%)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/boards/frdm_k32l2b/frdm_k32l2b.c (100%)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/boards/kuiic/K32L2B31xxxxA_flash.ld (100%)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/boards/kuiic/board.h (100%)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/boards/kuiic/board.mk (63%)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/boards/kuiic/kuiic.c (100%)
 rename hw/bsp/{kinetis_k32l => kinetis_k32l2}/family.mk (89%)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index a7c7fd1e1..620aec193 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -34,7 +34,7 @@ jobs:
         family:
         # Alphabetical order
         - 'broadcom_32bit'
-        - 'kinetis_k32l kinetis_kl'
+        - 'kinetis_k32l2 kinetis_kl'
         - 'lpc11 lpc13 lpc15 lpc17'
         - 'lpc51 lpc54 lpc55'
         - 'mm32 msp432e4'
diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h
index ce2f919bf..e5d2bb608 100644
--- a/hw/bsp/board_mcu.h
+++ b/hw/bsp/board_mcu.h
@@ -47,7 +47,7 @@
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9)
   #include "fsl_device_registers.h"
 
-#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32)
+#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L)
   #include "fsl_device_registers.h"
 
 #elif CFG_TUSB_MCU == OPT_MCU_NRF5X
diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk
index d0bb5be17..9eb541473 100644
--- a/hw/bsp/imxrt/family.mk
+++ b/hw/bsp/imxrt/family.mk
@@ -5,7 +5,6 @@ DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 include $(TOP)/$(BOARD_PATH)/board.mk
 
 CPU_CORE ?= cortex-m7
-include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
 
 CFLAGS += \
   -D__ARMVFP__=0 \
@@ -17,6 +16,7 @@ CFLAGS += \
 ifdef BOARD_TUD_RHPORT
 CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT)
 endif
+
 ifdef BOARD_TUH_RHPORT
 CFLAGS += -DBOARD_TUH_RHPORT=$(BOARD_TUH_RHPORT)
 endif
diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h
similarity index 100%
rename from hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.h
rename to hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h
diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
similarity index 75%
rename from hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.mk
rename to hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
index d96ab58b8..f69700139 100644
--- a/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk
@@ -1,8 +1,6 @@
 MCU = K32L2A41A
 
-CFLAGS += \
-  -mcpu=cortex-m0plus \
-  -DCPU_K32L2A41VLH1A \
+CFLAGS += -DCPU_K32L2A41VLH1A
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual
@@ -13,9 +11,6 @@ LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
 SRC_C += \
 	$(MCU_DIR)/project_template/clock_config.c \
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
 # For flash-jlink target
 JLINK_DEVICE = K32L2A41xxxxA
 
diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
similarity index 100%
rename from hw/bsp/kinetis_k32l/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
rename to hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h
similarity index 100%
rename from hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.h
rename to hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h
diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
similarity index 74%
rename from hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.mk
rename to hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
index 5f8ecbfe4..82456b721 100644
--- a/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.mk
@@ -1,8 +1,6 @@
 MCU = K32L2B31A
 
-CFLAGS += \
-  -mcpu=cortex-m0plus \
-  -DCPU_K32L2B31VLH0A \
+CFLAGS += -DCPU_K32L2B31VLH0A
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
@@ -13,9 +11,6 @@ LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
 SRC_C += \
 	$(MCU_DIR)/project_template/clock_config.c \
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
 # For flash-jlink target
 JLINK_DEVICE = K32L2B31xxxxA
 
diff --git a/hw/bsp/kinetis_k32l/boards/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c
similarity index 100%
rename from hw/bsp/kinetis_k32l/boards/frdm_k32l2b/frdm_k32l2b.c
rename to hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c
diff --git a/hw/bsp/kinetis_k32l/boards/kuiic/K32L2B31xxxxA_flash.ld b/hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld
similarity index 100%
rename from hw/bsp/kinetis_k32l/boards/kuiic/K32L2B31xxxxA_flash.ld
rename to hw/bsp/kinetis_k32l2/boards/kuiic/K32L2B31xxxxA_flash.ld
diff --git a/hw/bsp/kinetis_k32l/boards/kuiic/board.h b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h
similarity index 100%
rename from hw/bsp/kinetis_k32l/boards/kuiic/board.h
rename to hw/bsp/kinetis_k32l2/boards/kuiic/board.h
diff --git a/hw/bsp/kinetis_k32l/boards/kuiic/board.mk b/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk
similarity index 63%
rename from hw/bsp/kinetis_k32l/boards/kuiic/board.mk
rename to hw/bsp/kinetis_k32l2/boards/kuiic/board.mk
index 29a12e982..fc5bdeec8 100644
--- a/hw/bsp/kinetis_k32l/boards/kuiic/board.mk
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.mk
@@ -1,11 +1,6 @@
 MCU = K32L2B31A
 
-# This board uses TinyUF2 for updates
-UF2_FAMILY_ID = 0x7f83e793
-
-CFLAGS += \
-  -mcpu=cortex-m0plus \
-  -DCPU_K32L2B31VLH0A \
+CFLAGS += -DCPU_K32L2B31VLH0A
 
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
@@ -13,9 +8,6 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/K32L2B31xxxxA_flash.ld
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
 # For flash-jlink target
 JLINK_DEVICE = K32L2B31xxxxA
 
diff --git a/hw/bsp/kinetis_k32l/boards/kuiic/kuiic.c b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c
similarity index 100%
rename from hw/bsp/kinetis_k32l/boards/kuiic/kuiic.c
rename to hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c
diff --git a/hw/bsp/kinetis_k32l/family.mk b/hw/bsp/kinetis_k32l2/family.mk
similarity index 89%
rename from hw/bsp/kinetis_k32l/family.mk
rename to hw/bsp/kinetis_k32l2/family.mk
index 41f22e250..357485762 100644
--- a/hw/bsp/kinetis_k32l/family.mk
+++ b/hw/bsp/kinetis_k32l2/family.mk
@@ -1,13 +1,13 @@
+UF2_FAMILY_ID = 0x7f83e793
 SDK_DIR = hw/mcu/nxp/mcux-sdk
 DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
-
 MCU_DIR = $(SDK_DIR)/devices/$(MCU)
+
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-	-DCFG_TUSB_MCU=OPT_MCU_KINETIS_K32
+	-DCFG_TUSB_MCU=OPT_MCU_KINETIS_K32L
 
 SRC_C += \
 	src/portable/nxp/khci/dcd_khci.c \
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 56525725e..9f3be78fd 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -97,7 +97,7 @@
   #define TUP_DCD_ENDPOINT_MAX    8
   #define TUP_RHPORT_HIGHSPEED    1
 
-#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32)
+#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L)
   #define TUP_USBIP_CHIPIDEA_FS
   #define TUP_USBIP_CHIPIDEA_FS_KINETIS
   #define TUP_DCD_ENDPOINT_MAX    16
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 43e67cf64..f16d8a5d0 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -119,7 +119,8 @@
 
 // NXP Kinetis
 #define OPT_MCU_KINETIS_KL       1200 ///< NXP KL series
-#define OPT_MCU_KINETIS_K32      1201 ///< NXP K32 series
+#define OPT_MCU_KINETIS_K32L     1201 ///< NXP K32L series
+#define OPT_MCU_KINETIS_K32      1201 ///< Alias to K32L
 
 #define OPT_MCU_MKL25ZXX         1200 ///< Alias to KL (obsolete)
 #define OPT_MCU_K32L2BXX         1201 ///< Alias to K32 (obsolete)
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 7e798cf9e..b81dabae0 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -52,7 +52,7 @@ deps_optional = {
                            'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
     'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
                             '950819b7de9b32f92c3edf396bc5ffb8d66e7009',
-                            'kinetis_k32l lpc51 lpc54 lpc55 mcx imxrt'],
+                            'kinetis_k32l2 lpc51 lpc54 lpc55 mcx imxrt'],
     'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
                                          'c3715ce94b6f6391856de56081d4d9b3e98fa93d',
                                          'rp2040'],
@@ -166,7 +166,7 @@ deps_optional = {
                             'ch32v307'],
     'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
                     '20285262657d1b482d132d20d755c8c330d55c1f',
-                    'imxrt kinetis_k32l lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
+                    'imxrt kinetis_k32l2 lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
                     'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 '
                     'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'],
     'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',

From eb7fcf1b7474fd75f43b2501586c8b6b03354d41 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 18:38:41 +0700
Subject: [PATCH 1829/2085] add CPU_CORE for all family

---
 hw/bsp/lpc11/family.mk             |  7 +------
 hw/bsp/lpc13/family.mk             |  7 +------
 hw/bsp/lpc15/family.mk             |  7 +------
 hw/bsp/lpc17/family.mk             |  7 +------
 hw/bsp/lpc18/family.mk             |  7 +------
 hw/bsp/lpc51/family.mk             |  7 +------
 hw/bsp/lpc54/family.mk             |  9 +--------
 hw/bsp/lpc55/family.mk             |  9 +--------
 hw/bsp/mcx/family.mk               |  2 --
 hw/bsp/mm32/family.mk              |  8 +-------
 hw/bsp/msp432e4/family.mk          | 11 +++--------
 hw/bsp/nrf/family.mk               |  1 -
 hw/bsp/ra/boards/ra4m1_ek/board.mk |  6 +-----
 hw/bsp/ra/boards/ra4m3_ek/board.mk |  6 +-----
 hw/bsp/ra/family.mk                |  4 +---
 hw/bsp/samd11/family.mk            |  6 +-----
 hw/bsp/samd21/family.mk            |  7 +------
 hw/bsp/samd51/family.mk            |  9 +--------
 hw/bsp/same5x/family.mk            |  8 +-------
 hw/bsp/saml2x/family.mk            | 12 +++---------
 hw/bsp/tm4c123/family.mk           |  9 +--------
 hw/bsp/xmc4000/family.mk           | 10 +---------
 22 files changed, 24 insertions(+), 135 deletions(-)

diff --git a/hw/bsp/lpc11/family.mk b/hw/bsp/lpc11/family.mk
index eb427c09d..dee85da90 100644
--- a/hw/bsp/lpc11/family.mk
+++ b/hw/bsp/lpc11/family.mk
@@ -2,12 +2,10 @@ DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc$(MCU)/lpc_chip_$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
   -nostdlib \
   -D__USE_LPCOPEN \
   -DCFG_TUSB_MCU=OPT_MCU_LPC11UXX \
@@ -36,8 +34,5 @@ endif
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
 # For flash-jlink target
 JLINK_DEVICE = LPC11U68
diff --git a/hw/bsp/lpc13/family.mk b/hw/bsp/lpc13/family.mk
index 28f98e4ca..10cf4969d 100644
--- a/hw/bsp/lpc13/family.mk
+++ b/hw/bsp/lpc13/family.mk
@@ -2,12 +2,10 @@ DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
   -nostdlib \
   -DCORE_M3 \
   -D__USE_LPCOPEN \
@@ -34,6 +32,3 @@ SRC_C += \
 
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk
index 0ad1220d6..9f489832f 100644
--- a/hw/bsp/lpc15/family.mk
+++ b/hw/bsp/lpc15/family.mk
@@ -1,12 +1,10 @@
 DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
   -nostdlib \
   -DCORE_M3 \
   -D__USE_LPCOPEN \
@@ -34,6 +32,3 @@ SRC_C += \
 INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
diff --git a/hw/bsp/lpc17/family.mk b/hw/bsp/lpc17/family.mk
index af01b55a8..abf6abe13 100644
--- a/hw/bsp/lpc17/family.mk
+++ b/hw/bsp/lpc17/family.mk
@@ -2,12 +2,10 @@ DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
 MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
   -nostdlib \
   -DCORE_M3 \
   -D__USE_LPCOPEN \
@@ -35,6 +33,3 @@ SRC_C += \
 
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk
index fbe6ad834..9d0f85c20 100644
--- a/hw/bsp/lpc18/family.mk
+++ b/hw/bsp/lpc18/family.mk
@@ -1,12 +1,10 @@
 DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
   -nostdlib \
   -DCORE_M3 \
   -D__USE_LPCOPEN \
@@ -32,6 +30,3 @@ INC += \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(MCU_DIR)/inc \
 	$(TOP)/$(MCU_DIR)/inc/config_18xx
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
diff --git a/hw/bsp/lpc51/family.mk b/hw/bsp/lpc51/family.mk
index bfca2f6b1..df5a9958e 100644
--- a/hw/bsp/lpc51/family.mk
+++ b/hw/bsp/lpc51/family.mk
@@ -3,12 +3,10 @@ DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
   -DCFG_TUSB_MCU=OPT_MCU_LPC51UXX \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
@@ -40,6 +38,3 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU).S
 
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower.a
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index f52b9b5eb..7d8bb86cd 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -2,14 +2,10 @@ SDK_DIR = hw/mcu/nxp/mcux-sdk
 DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -DCFG_TUSB_MCU=OPT_MCU_LPC54XXX \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
 
@@ -49,6 +45,3 @@ INC += \
 	$(TOP)/$(SDK_DIR)/drivers/lpc_gpio
 
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
diff --git a/hw/bsp/lpc55/family.mk b/hw/bsp/lpc55/family.mk
index f9dabcfa3..a87fa5acf 100644
--- a/hw/bsp/lpc55/family.mk
+++ b/hw/bsp/lpc55/family.mk
@@ -3,17 +3,13 @@ SDK_DIR = hw/mcu/nxp/mcux-sdk
 DEPS_SUBMODULES += lib/CMSIS_5 lib/sct_neopixel $(SDK_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m33
 
 # Default to Highspeed PORT1
 PORT ?= 1
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m33 \
-  -mfloat-abi=hard \
-  -mfpu=fpv5-sp-d16 \
   -DCFG_TUSB_MCU=OPT_MCU_LPC55XX \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
   -DBOARD_TUD_RHPORT=$(PORT)
@@ -63,6 +59,3 @@ INC += \
 SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_CORE).S
 
 LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
diff --git a/hw/bsp/mcx/family.mk b/hw/bsp/mcx/family.mk
index 2722c2038..e384aa8eb 100644
--- a/hw/bsp/mcx/family.mk
+++ b/hw/bsp/mcx/family.mk
@@ -4,9 +4,7 @@ SDK_DIR = hw/mcu/nxp/mcux-sdk
 DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 include $(TOP)/$(BOARD_PATH)/board.mk
-
 CPU_CORE ?= cortex-m33
-include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
 
 # Default to Highspeed PORT1
 PORT ?= 1
diff --git a/hw/bsp/mm32/family.mk b/hw/bsp/mm32/family.mk
index 81af0d166..d5b6e315a 100644
--- a/hw/bsp/mm32/family.mk
+++ b/hw/bsp/mm32/family.mk
@@ -3,13 +3,10 @@ SDK_DIR = hw/mcu/mindmotion/mm32sdk
 DEPS_SUBMODULES += lib/CMSIS_5 $(SDK_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m3
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m3 \
-  -mfloat-abi=soft \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_MM32F327X
 
@@ -29,8 +26,5 @@ INC += \
 	$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/Include \
 	$(TOP)/$(SDK_DIR)/mm32f327x/MM32F327x/HAL_Lib/Inc
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
-
 # flash target using on-board
 flash: flash-jlink
diff --git a/hw/bsp/msp432e4/family.mk b/hw/bsp/msp432e4/family.mk
index 2383bc604..b5ade6a52 100644
--- a/hw/bsp/msp432e4/family.mk
+++ b/hw/bsp/msp432e4/family.mk
@@ -1,13 +1,11 @@
 DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/ti
 
+#include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
 CFLAGS += \
 	-flto \
-	-mthumb \
 	-mslow-flash-data \
-	-mabi=aapcs \
-	-mcpu=cortex-m4 \
-	-mfloat-abi=hard \
-	-mfpu=fpv4-sp-d16 \
 	-D__MSP432E401Y__ \
 	-DCFG_TUSB_MCU=OPT_MCU_MSP432E4
 
@@ -33,9 +31,6 @@ INC += \
 
 SRC_S += $(MCU_DIR)/Source/startup_msp432e411y_gcc.S
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
 # For flash-jlink target
 JLINK_DEVICE = MSP432E401Y
 JLINK_IF     = SWD
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index 6d067e1c2..cdcfe39bd 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -5,7 +5,6 @@ include $(TOP)/$(BOARD_PATH)/board.mk
 
 # nRF52 is cortex-m4, nRF53 is cortex-m33
 CPU_CORE ?= cortex-m4
-include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
 
 CFLAGS += \
   -flto \
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.mk b/hw/bsp/ra/boards/ra4m1_ek/board.mk
index 6a661c0b8..5c193513d 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.mk
@@ -1,8 +1,4 @@
-CFLAGS += \
-	-mcpu=cortex-m4 \
-	-mfloat-abi=hard \
-	-mfpu=fpv4-sp-d16 \
-	-DCFG_TUSB_MCU=OPT_MCU_RAXXX
+CPU_CORE = cortex-m4
 
 FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m1
 FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m1_ek
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.mk b/hw/bsp/ra/boards/ra4m3_ek/board.mk
index d668db0ea..264f29c1a 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.mk
@@ -1,8 +1,4 @@
-CFLAGS += \
-	-mcpu=cortex-m33 \
-	-mfloat-abi=hard \
-	-mfpu=fpv5-sp-d16 \
-	-DCFG_TUSB_MCU=OPT_MCU_RAXXX
+CPU_CORE = cortex-m33
 
 FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m3
 FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m3_ek
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index d48272e61..b65c95191 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -1,11 +1,9 @@
 DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
 
-# Cross Compiler for RA
-CROSS_COMPILE = arm-none-eabi-
-
 include $(TOP)/$(BOARD_PATH)/board.mk
 
 CFLAGS += \
+  -DCFG_TUSB_MCU=OPT_MCU_RAXXX \
 	-Wno-error=undef \
 	-Wno-error=strict-prototypes \
 	-Wno-error=cast-align \
diff --git a/hw/bsp/samd11/family.mk b/hw/bsp/samd11/family.mk
index a2a5268aa..43a60a122 100644
--- a/hw/bsp/samd11/family.mk
+++ b/hw/bsp/samd11/family.mk
@@ -1,11 +1,10 @@
 DEPS_SUBMODULES += hw/mcu/microchip
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
   -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
   -nostdlib -nostartfiles \
   -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
   -DOSC32K_OVERWRITE_CALIBRATION=0 \
@@ -40,6 +39,3 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd11/hri \
 	$(TOP)/hw/mcu/microchip/samd11/CMSIS/Include \
 	$(TOP)/hw/mcu/microchip/samd11/CMSIS/Core/Include
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index 30eccacb2..49a1a781a 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -2,12 +2,10 @@ UF2_FAMILY_ID = 0x68ed2b88
 DEPS_SUBMODULES += hw/mcu/microchip
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
   -nostdlib -nostartfiles \
   -DCONF_DFLL_OVERWRITE_CALIBRATION=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD21
@@ -39,9 +37,6 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd21/hri \
 	$(TOP)/hw/mcu/microchip/samd21/CMSIS/Include
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
 # Add it to your PATH or change BOSSAC variable to match your installation
diff --git a/hw/bsp/samd51/family.mk b/hw/bsp/samd51/family.mk
index 657e33438..9a6c67e1a 100644
--- a/hw/bsp/samd51/family.mk
+++ b/hw/bsp/samd51/family.mk
@@ -2,14 +2,10 @@ UF2_FAMILY_ID = 0x55114460
 DEPS_SUBMODULES += hw/mcu/microchip
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_SAMD51
 
@@ -37,9 +33,6 @@ INC += \
 	$(TOP)/hw/mcu/microchip/samd51/hri \
 	$(TOP)/hw/mcu/microchip/samd51/CMSIS/Include
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
 # Add it to your PATH or change BOSSAC variable to match your installation
diff --git a/hw/bsp/same5x/family.mk b/hw/bsp/same5x/family.mk
index df1af4a9d..691863f11 100644
--- a/hw/bsp/same5x/family.mk
+++ b/hw/bsp/same5x/family.mk
@@ -2,14 +2,11 @@ DEPS_SUBMODULES += hw/mcu/microchip
 
 SDK_DIR = hw/mcu/microchip/$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 CFLAGS += \
   -mthumb \
-  -mabi=aapcs \
   -mlong-calls \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_SAME5X
 
@@ -32,9 +29,6 @@ INC += \
 	$(TOP)/$(SDK_DIR)/hri \
 	$(TOP)/$(SDK_DIR)/CMSIS/Include
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
 # flash using edbg from https://github.com/ataradov/edbg
 flash-edbg: $(BUILD)/$(PROJECT).bin
 	edbg --verbose -t $(MCU) -pv -f $<
diff --git a/hw/bsp/saml2x/family.mk b/hw/bsp/saml2x/family.mk
index 62e5f8f4a..0acb0ed14 100644
--- a/hw/bsp/saml2x/family.mk
+++ b/hw/bsp/saml2x/family.mk
@@ -1,14 +1,11 @@
 UF2_FAMILY_ID = 0x68ed2b88
 DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/microchip
-
-include $(TOP)/$(BOARD_PATH)/board.mk
-
 MCU_DIR = hw/mcu/microchip/$(SAML_VARIANT)
 
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
+
 CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
   -nostdlib -nostartfiles \
   -DCONF_OSC32K_CALIB_ENABLE=0 \
   -DCFG_TUSB_MCU=OPT_MCU_SAML22
@@ -41,9 +38,6 @@ INC += \
 	$(TOP)/$(MCU_DIR)/hri \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include
 
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
-
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
 # Add it to your PATH or change BOSSAC variable to match your installation
diff --git a/hw/bsp/tm4c123/family.mk b/hw/bsp/tm4c123/family.mk
index 021b47fd3..608c530bb 100644
--- a/hw/bsp/tm4c123/family.mk
+++ b/hw/bsp/tm4c123/family.mk
@@ -1,14 +1,10 @@
 DEPS_SUBMODULES += hw/mcu/ti
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -DCFG_TUSB_MCU=OPT_MCU_TM4C123 \
   -uvectors \
   -DTM4C123GH6PM
@@ -31,6 +27,3 @@ SRC_C += \
 	src/portable/mentor/musb/hcd_musb.c \
 	$(MCU_DIR)/Source/system_TM4C123.c \
 	$(MCU_DIR)/Source/GCC/tm4c123_startup.c
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk
index 1094f3b72..35c3a58b7 100644
--- a/hw/bsp/xmc4000/family.mk
+++ b/hw/bsp/xmc4000/family.mk
@@ -4,14 +4,10 @@ MCU_DIR = hw/mcu/infineon/mtb-xmclib-cat3
 DEPS_SUBMODULES += $(MCU_DIR)
 
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
 
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib -nostartfiles \
   -DCFG_TUSB_MCU=OPT_MCU_XMC4000
 
@@ -27,7 +23,6 @@ SRC_C += \
 	$(MCU_DIR)/XMCLib/src/xmc4_gpio.c \
 	$(MCU_DIR)/XMCLib/src/xmc4_scu.c
 
-
 SRC_S += $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/startup_$(MCU_VARIANT).S
 
 INC += \
@@ -35,6 +30,3 @@ INC += \
 	$(TOP)/$(MCU_DIR)/CMSIS/Core/Include \
 	$(TOP)/$(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Include \
 	$(TOP)/$(MCU_DIR)/XMCLib/inc
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F

From 086c1d4090bc3bfdcde56aed5036e3efc6d5ea9f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 18:54:14 +0700
Subject: [PATCH 1830/2085] more CPU_CORE

---
 .../boards/raspberrypi_zero_w/board.mk               |  4 ++--
 .../broadcom_64bit/boards/raspberrypi_cm4/board.mk   |  4 ++--
 .../boards/raspberrypi_zero2w/board.mk               |  4 ++--
 hw/bsp/kinetis_kl/family.mk                          |  7 +------
 tools/make/cpu/arm1176.mk                            |  9 +++++++++
 tools/make/cpu/cortex-a53.mk                         | 12 ++++++++++++
 tools/make/cpu/cortex-a72.mk                         | 12 ++++++++++++
 tools/make/cpu/cortex-m33.mk                         |  1 +
 8 files changed, 41 insertions(+), 12 deletions(-)
 create mode 100644 tools/make/cpu/arm1176.mk
 create mode 100644 tools/make/cpu/cortex-a53.mk
 create mode 100644 tools/make/cpu/cortex-a72.mk

diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
index 77811d18d..052033230 100644
--- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
+++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero_w/board.mk
@@ -1,5 +1,5 @@
-CFLAGS += -mcpu=arm1176jzf-s \
-          -DBCM_VERSION=2835 \
+CPU_CORE = arm1176
+CFLAGS += -DBCM_VERSION=2835 \
           -DCFG_TUSB_MCU=OPT_MCU_BCM2835
 
 SUFFIX =
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
index 5706b8318..702f10137 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.mk
@@ -1,3 +1,3 @@
-CFLAGS += -mcpu=cortex-a72 \
-          -DBCM_VERSION=2711 \
+CPU_CORE = cortex-a72
+CFLAGS += -DBCM_VERSION=2711 \
           -DCFG_TUSB_MCU=OPT_MCU_BCM2711
diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
index 3060b0571..da3fe17bc 100644
--- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
+++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2w/board.mk
@@ -1,3 +1,3 @@
-CFLAGS += -mcpu=cortex-a53 \
-          -DBCM_VERSION=2837 \
+CPU_CORE = cortex-a53
+CFLAGS += -DBCM_VERSION=2837 \
           -DCFG_TUSB_MCU=OPT_MCU_BCM2837
diff --git a/hw/bsp/kinetis_kl/family.mk b/hw/bsp/kinetis_kl/family.mk
index 2bed6b486..edb2f3366 100644
--- a/hw/bsp/kinetis_kl/family.mk
+++ b/hw/bsp/kinetis_kl/family.mk
@@ -3,11 +3,9 @@ DEPS_SUBMODULES += $(SDK_DIR) lib/CMSIS_5
 
 MCU_DIR = $(SDK_DIR)/devices/$(MCU)
 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m0plus
 
 CFLAGS += \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m0plus \
   -DCFG_TUSB_MCU=OPT_MCU_KINETIS_KL \
 
 LDFLAGS += \
@@ -34,6 +32,3 @@ INC += \
 	$(TOP)/$(SDK_DIR)/drivers/port \
 	$(TOP)/$(SDK_DIR)/drivers/smc \
 	$(TOP)/$(SDK_DIR)/drivers/uart \
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/tools/make/cpu/arm1176.mk b/tools/make/cpu/arm1176.mk
new file mode 100644
index 000000000..022ccf7ad
--- /dev/null
+++ b/tools/make/cpu/arm1176.mk
@@ -0,0 +1,9 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mcpu=arm1176jzf-s \
+
+else ifeq ($(TOOLCHAIN),iar)
+	#CFLAGS += --cpu cortex-a53
+	#ASFLAGS += --cpu cortex-a53
+
+endif
diff --git a/tools/make/cpu/cortex-a53.mk b/tools/make/cpu/cortex-a53.mk
new file mode 100644
index 000000000..42e522ecf
--- /dev/null
+++ b/tools/make/cpu/cortex-a53.mk
@@ -0,0 +1,12 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mcpu=cortex-a53 \
+
+else ifeq ($(TOOLCHAIN),iar)
+	CFLAGS += \
+		--cpu cortex-a53 \
+
+	ASFLAGS += \
+		--cpu cortex-a53 \
+
+endif
diff --git a/tools/make/cpu/cortex-a72.mk b/tools/make/cpu/cortex-a72.mk
new file mode 100644
index 000000000..1b3d8da4a
--- /dev/null
+++ b/tools/make/cpu/cortex-a72.mk
@@ -0,0 +1,12 @@
+ifeq ($(TOOLCHAIN),gcc)
+  CFLAGS += \
+    -mcpu=cortex-a72 \
+
+else ifeq ($(TOOLCHAIN),iar)
+	CFLAGS += \
+		--cpu cortex-a72 \
+
+	ASFLAGS += \
+		--cpu cortex-a72 \
+
+endif
diff --git a/tools/make/cpu/cortex-m33.mk b/tools/make/cpu/cortex-m33.mk
index 240ed0d49..e53f5c2b1 100644
--- a/tools/make/cpu/cortex-m33.mk
+++ b/tools/make/cpu/cortex-m33.mk
@@ -13,6 +13,7 @@ else ifeq ($(TOOLCHAIN),iar)
 	ASFLAGS += \
 		--cpu cortex-m33 \
 		--fpu VFPv5-SP \
+
 endif
 
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure

From 7d0ce5605ace2acba928f444f3dd7eb6de0b29ec Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 19:08:37 +0700
Subject: [PATCH 1831/2085] allow to skip CPU_CORE

---
 .github/workflows/build_iar.yml | 2 +-
 examples/make.mk                | 5 +++++
 tools/build_family.py           | 2 +-
 tools/make/toolchain/arm_gcc.mk | 3 ---
 tools/make/toolchain/arm_iar.mk | 2 --
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 48d66240e..8c9a500d7 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -47,7 +47,7 @@ jobs:
       run: python3 tools/get_deps.py ${{ matrix.family }}
 
     - name: Build
-      run: python3 tools/build_family.py ${{ matrix.family }} CC=iccarm
+      run: python3 tools/build_family.py ${{ matrix.family }} TOOLCHAIN=iar
 
   cmake:
     runs-on: [self-hosted, Linux, X64, hifiphile]
diff --git a/examples/make.mk b/examples/make.mk
index 4fcde83c8..3c3a920cc 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -137,5 +137,10 @@ else ifeq ($(LOGGER),swo)
   CFLAGS += -DLOGGER_SWO
 endif
 
+# CPU specific flags
+ifdef CPU_CORE
+include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
+endif
+
 # toolchain specific
 include $(TOP)/tools/make/toolchain/arm_$(TOOLCHAIN).mk
diff --git a/tools/build_family.py b/tools/build_family.py
index 9b612b4cb..fb90e0edb 100644
--- a/tools/build_family.py
+++ b/tools/build_family.py
@@ -11,7 +11,7 @@ SKIPPED = "\033[33mskipped\033[0m"
 
 build_separator = '-' * 106
 
-make_iar_option = 'CC=iccarm'
+make_iar_option = 'TOOLCHAIN=iar'
 
 def filter_with_input(mylist):
     if len(sys.argv) > 1:
diff --git a/tools/make/toolchain/arm_gcc.mk b/tools/make/toolchain/arm_gcc.mk
index d5ee98def..693fda0b3 100644
--- a/tools/make/toolchain/arm_gcc.mk
+++ b/tools/make/toolchain/arm_gcc.mk
@@ -9,9 +9,6 @@ GDB = $(CROSS_COMPILE)gdb
 OBJCOPY = $(CROSS_COMPILE)objcopy
 SIZE = $(CROSS_COMPILE)size
 
-# CPU specific flags
-include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
-
 # ---------------------------------------
 # Compiler Flags
 # ---------------------------------------
diff --git a/tools/make/toolchain/arm_iar.mk b/tools/make/toolchain/arm_iar.mk
index 42b31cfd3..f1850add7 100644
--- a/tools/make/toolchain/arm_iar.mk
+++ b/tools/make/toolchain/arm_iar.mk
@@ -4,8 +4,6 @@ LD = ilinkarm
 OBJCOPY = ielftool --silent
 SIZE = size
 
-include $(TOP)/tools/make/cpu/$(CPU_CORE).mk
-
 # Enable extension mode (gcc compatible)
 CFLAGS += -e --debug --silent
 

From 2216704db8801b359659bf191ae955e4c626f031 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 19:31:33 +0700
Subject: [PATCH 1832/2085] rename GCC_CFLAGS to CFLAGS_GCC, GCC_SRC_S to
 SRC_S_GCC etc ..

---
 hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk   |  9 ++-------
 hw/bsp/stm32f0/boards/stm32f072disco/board.mk      |  9 ++++-----
 hw/bsp/stm32f0/boards/stm32f072eval/board.mk       |  8 ++++----
 hw/bsp/stm32f0/family.mk                           | 11 +++++++++--
 hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk  | 12 +++++-------
 hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk    | 12 +++++-------
 hw/bsp/stm32f1/family.mk                           |  6 +++++-
 hw/bsp/stm32f2/family.mk                           |  4 ++--
 hw/bsp/stm32f4/boards/feather_stm32f405/board.mk   |  8 ++++----
 hw/bsp/stm32f4/boards/pyboardv11/board.mk          |  8 ++++----
 hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk  |  8 ++++----
 hw/bsp/stm32f4/boards/stm32f407disco/board.mk      |  8 ++++----
 hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk  |  8 ++++----
 hw/bsp/stm32f4/boards/stm32f411disco/board.mk      |  8 ++++----
 hw/bsp/stm32f4/boards/stm32f412disco/board.mk      |  8 ++++----
 hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk     |  8 ++++----
 hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk     |  8 ++++----
 hw/bsp/stm32f4/family.mk                           |  4 ++--
 hw/bsp/stm32f7/boards/stlinkv3mini/board.mk        |  8 ++++----
 hw/bsp/stm32f7/boards/stm32f723disco/board.mk      |  8 ++++----
 hw/bsp/stm32f7/boards/stm32f746disco/board.mk      |  8 ++++----
 hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk     |  8 ++++----
 hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk     |  8 ++++----
 hw/bsp/stm32f7/boards/stm32f769disco/board.mk      |  8 ++++----
 hw/bsp/stm32f7/family.mk                           |  4 ++--
 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk     |  8 ++++----
 hw/bsp/stm32g0/family.mk                           |  4 ++--
 hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk       | 11 ++++-------
 hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk     | 11 ++++-------
 hw/bsp/stm32g4/family.mk                           | 11 +++++++++--
 hw/bsp/stm32h7/boards/daisyseed/board.mk           |  8 ++++----
 hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk     |  8 ++++----
 hw/bsp/stm32h7/boards/stm32h743eval/board.mk       |  8 ++++----
 hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk     |  8 ++++----
 hw/bsp/stm32h7/boards/stm32h745disco/board.mk      |  8 ++++----
 hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk |  8 ++++----
 hw/bsp/stm32h7/family.mk                           |  4 ++--
 hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk     |  8 ++++----
 hw/bsp/stm32l4/boards/stm32l476disco/board.mk      |  8 ++++----
 hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk     |  8 ++++----
 hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk     |  8 ++++----
 hw/bsp/stm32l4/family.mk                           |  4 ++--
 tools/make/toolchain/arm_gcc.mk                    |  3 ---
 tools/make/toolchain/arm_gcc_rules.mk              |  8 ++++----
 tools/make/toolchain/arm_iar_rules.mk              |  4 ++--
 45 files changed, 173 insertions(+), 174 deletions(-)

diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
index 1cc443352..f8f0952e8 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
@@ -1,12 +1,7 @@
 CFLAGS += -DSTM32F070xB -DCFG_EXAMPLE_VIDEO_READONLY
 
-# GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
-GCC_LD_FILE = $(BOARD_PATH)/stm32F070rbtx_flash.ld
-
-# IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f070xb.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f070xb_flash.icf
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/stm32F070rbtx_flash.ld
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f070rb
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
index 4216ba186..57c658629 100644
--- a/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.mk
@@ -1,10 +1,9 @@
+MCU_VARIANT = stm32f072xb
+
 CFLAGS += -DSTM32F072xB -DCFG_EXAMPLE_VIDEO_READONLY
 
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
-
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F072RBTx_FLASH.ld
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f072rb
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
index bb9cba22a..c368bd8af 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
@@ -1,10 +1,10 @@
 CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY
 
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
 
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f072vb
diff --git a/hw/bsp/stm32f0/family.mk b/hw/bsp/stm32f0/family.mk
index 200c4f757..129a3b73a 100644
--- a/hw/bsp/stm32f0/family.mk
+++ b/hw/bsp/stm32f0/family.mk
@@ -16,12 +16,12 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F0
 
 # GCC Flags
-GCC_CFLAGS += \
+CFLAGS_GCC += \
   -flto \
   -nostdlib -nostartfiles \
 
 # suppress warning caused by vendor mcu driver
-GCC_CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align
+CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=cast-align
 
 # ------------------------
 # All source paths should be relative to the top level.
@@ -44,3 +44,10 @@ INC += \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
index 159b3ecb6..6c5f34501 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.mk
@@ -1,12 +1,10 @@
+MCU_VARIANT = stm32f103xb
+
 CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U -DCFG_EXAMPLE_VIDEO_READONLY
 
-# GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F103X8_FLASH.ld
-
-# IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f103xb.s
-IAR_LD_FILE = $(BOARD_PATH)/stm32f103x8_flash.icf
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F103X8_FLASH.ld
+LD_FILE_IAR = $(BOARD_PATH)/stm32f103x8_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f103c8
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
index efea75be7..7e95c1fe1 100644
--- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.mk
@@ -1,12 +1,10 @@
+MCU_VARIANT = stm32f103xb
+
 CFLAGS += -DSTM32F103xB -DHSE_VALUE=8000000U
 
-# GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f103xb.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F103XC_FLASH.ld
-
-# IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f103xb.s
-IAR_LD_FILE = $(BOARD_PATH)/stm32f103xc_flash.icf
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32F103XC_FLASH.ld
+LD_FILE_IAR = $(BOARD_PATH)/stm32f103xc_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f103rc
diff --git a/hw/bsp/stm32f1/family.mk b/hw/bsp/stm32f1/family.mk
index 4813fba2b..c9321c3cb 100644
--- a/hw/bsp/stm32f1/family.mk
+++ b/hw/bsp/stm32f1/family.mk
@@ -14,7 +14,7 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F1
 
 # GCC Flags
-GCC_CFLAGS += \
+CFLAGS_GCC += \
   -flto \
   -nostdlib -nostartfiles \
 
@@ -36,6 +36,10 @@ INC += \
   $(TOP)/$(ST_CMSIS)/Include \
   $(TOP)/$(ST_HAL_DRIVER)/Inc
 
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
 # flash target ROM bootloader
 flash-dfu-util: $(BUILD)/$(PROJECT).bin
 	dfu-util -R -a 0 --dfuse-address 0x08000000 -D $<
diff --git a/hw/bsp/stm32f2/family.mk b/hw/bsp/stm32f2/family.mk
index fd27c0e68..ce50b16ad 100644
--- a/hw/bsp/stm32f2/family.mk
+++ b/hw/bsp/stm32f2/family.mk
@@ -14,12 +14,12 @@ CPU_CORE ?= cortex-m3
 CFLAGS += \
 	-DCFG_TUSB_MCU=OPT_MCU_STM32F2
 
-GCC_CFLAGS += \
+CFLAGS_GCC += \
   -flto \
   -nostdlib -nostartfiles \
 
 # mcu driver cause following warnings
-GCC_CFLAGS += -Wno-error=sign-compare
+CFLAGS_GCC += -Wno-error=sign-compare
 
 SRC_C += \
   src/portable/synopsys/dwc2/dcd_dwc2.c \
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk b/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
index 1962dd9d8..cfd1d8b3b 100644
--- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.mk
@@ -1,12 +1,12 @@
 CFLAGS += -DSTM32F405xx
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f405xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f405xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f405xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f405xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f405rg
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.mk b/hw/bsp/stm32f4/boards/pyboardv11/board.mk
index 0a9100e1e..4c52e004a 100644
--- a/hw/bsp/stm32f4/boards/pyboardv11/board.mk
+++ b/hw/bsp/stm32f4/boards/pyboardv11/board.mk
@@ -1,12 +1,12 @@
 CFLAGS += -DSTM32F405xx
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f405xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F405RGTx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f405xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f405xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f405xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f405xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f405rg
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
index 11f9b81aa..3285bd232 100644
--- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.mk
@@ -1,12 +1,12 @@
 CFLAGS += -DSTM32F401xC
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f401xc.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F401VCTx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f401xc.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F401VCTx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f401xc.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f401xc_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f401xc.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f401xc_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f401cc
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.mk b/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
index a184804d3..4de656b0c 100644
--- a/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.mk
@@ -1,12 +1,12 @@
 CFLAGS += -DSTM32F407xx
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F407VGTx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F407VGTx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f407xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f407xx_flash.icf
 
 
 # For flash-jlink target
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
index ac15eaa5d..7af7ca47c 100644
--- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.mk
@@ -1,12 +1,12 @@
 CFLAGS += -DSTM32F411xE
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F411CEUx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F411CEUx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f411xe.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f411xe_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f411xe.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f411xe_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f411ce
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.mk b/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
index c5736050c..09fa50bd3 100644
--- a/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.mk
@@ -1,12 +1,12 @@
 CFLAGS += -DSTM32F411xE
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F411VETx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f411xe.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F411VETx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f411xe.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f411xe_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f411xe.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f411xe_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f411ve
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.mk b/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
index 7dc3699e0..f767ac6c4 100644
--- a/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.mk
@@ -1,12 +1,12 @@
 CFLAGS += -DSTM32F412Zx
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f412zx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f412zx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f412zx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f412zx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f412zg
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
index 7dc3699e0..f767ac6c4 100644
--- a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.mk
@@ -1,12 +1,12 @@
 CFLAGS += -DSTM32F412Zx
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f412zx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F412ZGTx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f412zx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f412zx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f412zx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f412zx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f412zg
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
index e1f337a7e..2ab32b7f3 100644
--- a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.mk
@@ -1,12 +1,12 @@
 CFLAGS += -DSTM32F439xx
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f439xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F439ZITX_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f439xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F439ZITX_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f439xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f439xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f439xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f439xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f439zi
diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk
index 9c132fd21..38592ecb0 100644
--- a/hw/bsp/stm32f4/family.mk
+++ b/hw/bsp/stm32f4/family.mk
@@ -15,12 +15,12 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32F4
 
 # GCC Flags
-GCC_CFLAGS += \
+CFLAGS_GCC += \
   -flto \
   -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
-GCC_CFLAGS += -Wno-error=cast-align
+CFLAGS_GCC += -Wno-error=cast-align
 
 # -----------------
 # Sources & Include
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
index e1d352cc9..b59125edc 100644
--- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
@@ -7,12 +7,12 @@ CFLAGS += \
   -DHSE_VALUE=25000000 \
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F723xE_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f723xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f723xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f723xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f723xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
index 6ddb727c7..168ca5dad 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
@@ -6,12 +6,12 @@ CFLAGS += \
   -DHSE_VALUE=25000000 \
 
 # GCC
-GCC_LD_FILE = $(BOARD_PATH)/STM32F723xE_FLASH.ld
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F723xE_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f723xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f723xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f723xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f723xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.mk b/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
index ba31baa16..acda5e2e8 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
@@ -6,12 +6,12 @@ CFLAGS += \
   -DHSE_VALUE=25000000
 
 # GCC
-GCC_LD_FILE = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f746xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f746xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f746xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f746xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
index e4d31040e..511433885 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
@@ -6,12 +6,12 @@ CFLAGS += \
   -DHSE_VALUE=8000000
 
 # GCC
-GCC_LD_FILE = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f746xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f746xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f746xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f746xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
index be5862612..329771986 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
@@ -6,12 +6,12 @@ CFLAGS += \
 	-DHSE_VALUE=8000000 \
 
 # GCC
-GCC_LD_FILE = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f767xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f767xx.s
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f767xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f767xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f767xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f767xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f767zi
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.mk b/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
index 18f59e8b2..20042db98 100644
--- a/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
@@ -7,12 +7,12 @@ CFLAGS += \
   -DHSE_VALUE=25000000 \
 
 # GCC
-GCC_LD_FILE = $(BOARD_PATH)/STM32F769ZITx_FLASH.ld
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f769xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32F769ZITx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f769xx.s
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f769xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f769xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f769xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f769xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index 0b3b641d8..1a15a743c 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -28,12 +28,12 @@ else
 endif
 
 # GCC Flags
-GCC_CFLAGS += \
+CFLAGS_GCC += \
   -flto \
   -nostdlib -nostartfiles
 
 # mcu driver cause following warnings
-GCC_CFLAGS += -Wno-error=shadow -Wno-error=cast-align
+CFLAGS_GCC += -Wno-error=shadow -Wno-error=cast-align
 
 # -----------------
 # Sources & Include
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk
index 50f282b09..6a6078d5f 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.mk
@@ -2,12 +2,12 @@ CFLAGS += \
 	-DSTM32G0B1xx
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g0b1xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32G0B1RETx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g0b1xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32G0B1RETx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32g0b1xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32g0b1xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32g0b1xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32g0b1xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32g0b1re
diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk
index 76f1524e5..412c73291 100644
--- a/hw/bsp/stm32g0/family.mk
+++ b/hw/bsp/stm32g0/family.mk
@@ -14,12 +14,12 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32G0
 
 # GCC Flags
-GCC_CFLAGS += \
+CFLAGS_GCC += \
   -flto \
   -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
-GCC_CFLAGS += -Wno-error=cast-align
+CFLAGS_GCC += -Wno-error=cast-align
 
 # -----------------
 # Sources & Include
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk
index 75cd9d8f5..6266b3ccc 100644
--- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.mk
@@ -1,13 +1,10 @@
+MCU_VARIANT = stm32g474xx
+
 CFLAGS += \
 	-DSTM32G474xx \
 
-# GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g474xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
-
-# IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32g474xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32g474xx_flash.icf
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
 
 # For flash-jlink target
 JLINK_DEVICE = stm32g474re
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
index 2f6ec0ed6..dc46af1d1 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.mk
@@ -1,14 +1,11 @@
+MCU_VARIANT = stm32g474xx
+
 CFLAGS += \
 	-DSTM32G474xx \
 	-DHSE_VALUE=24000000
 
-# GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32g474xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
-
-# IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32g474xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32g474xx_flash.icf
+# Linker
+LD_FILE_GCC = $(BOARD_PATH)/STM32G474RETx_FLASH.ld
 
 # For flash-jlink target
 JLINK_DEVICE = stm32g474re
diff --git a/hw/bsp/stm32g4/family.mk b/hw/bsp/stm32g4/family.mk
index 8ee453aed..2efe91449 100644
--- a/hw/bsp/stm32g4/family.mk
+++ b/hw/bsp/stm32g4/family.mk
@@ -15,12 +15,12 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32G4
 
 # GCC Flags
-GCC_CFLAGS += \
+CFLAGS_GCC += \
   -flto \
   -nostdlib -nostartfiles \
 
 # suppress warning caused by vendor mcu driver
-GCC_CFLAGS += -Wno-error=cast-align
+CFLAGS_GCC += -Wno-error=cast-align
 
 # -----------------
 # Sources & Include
@@ -45,5 +45,12 @@ INC += \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
 
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
+
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.mk b/hw/bsp/stm32h7/boards/daisyseed/board.mk
index d53782496..da2eb4433 100644
--- a/hw/bsp/stm32h7/boards/daisyseed/board.mk
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.mk
@@ -4,12 +4,12 @@ CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=16000000
 PORT ?= 0
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h750xx.s
-GCC_LD_FILE = $(BOARD_PATH)/stm32h750ibkx_flash.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h750xx.s
+LD_FILE_GCC = $(BOARD_PATH)/stm32h750ibkx_flash.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h750ibk6_m7
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
index 9cf241df8..57a316f41 100644
--- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk
@@ -4,12 +4,12 @@ CFLAGS += -DSTM32H723xx -DHSE_VALUE=8000000
 PORT ?= 0
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h723xx.s
-GCC_LD_FILE =  $(FAMILY_PATH)/linker/stm32h723xx_flash.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h723xx.s
+LD_FILE_GCC =  $(FAMILY_PATH)/linker/stm32h723xx_flash.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h723xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h723xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h723xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h723xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h723zg
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
index 558e943b4..36882a0e5 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk
@@ -5,12 +5,12 @@ PORT ?= 1
 SPEED ?= high
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-GCC_LD_FILE = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
+LD_FILE_GCC = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h743xi
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
index 0bff0940e..f641b77aa 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk
@@ -4,12 +4,12 @@ CFLAGS += -DSTM32H743xx -DHSE_VALUE=8000000
 PORT ?= 0
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-GCC_LD_FILE = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
+LD_FILE_GCC = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h743zi
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
index 86347ade7..9c3615f05 100644
--- a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk
@@ -7,12 +7,12 @@ CFLAGS += -DSTM32H745xx -DCORE_CM7 -DHSE_VALUE=25000000
 PORT ?= 0
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h745xx.s
-GCC_LD_FILE = $(ST_CMSIS)/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h745xx.s
+LD_FILE_GCC = $(ST_CMSIS)/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h745xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h745xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h745xi_m7
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
index 9997faff9..cea4bfacb 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk
@@ -10,12 +10,12 @@ SRC_C += \
   $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim_ex.c
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
-GCC_LD_FILE = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s
+LD_FILE_GCC = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32h743ii
diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk
index 48730bbb4..a1ff26d0b 100644
--- a/hw/bsp/stm32h7/family.mk
+++ b/hw/bsp/stm32h7/family.mk
@@ -28,12 +28,12 @@ else
 endif
 
 # GCC Flags
-GCC_CFLAGS += \
+CFLAGS_GCC += \
   -flto \
   -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
-GCC_CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=unused-parameter
+CFLAGS_GCC += -Wno-error=maybe-uninitialized -Wno-error=cast-align -Wno-error=unused-parameter
 
 # -----------------
 # Sources & Include
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
index 854397fc8..87b333500 100644
--- a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.mk
@@ -2,12 +2,12 @@ CFLAGS += \
   -DSTM32L412xx \
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l412xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32L412KBUx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l412xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32L412KBUx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l412xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l412xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l412xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l412xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l412kb
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.mk b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
index 125f1f106..3ba9ab444 100644
--- a/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.mk
@@ -2,12 +2,12 @@ CFLAGS += \
   -DSTM32L476xx \
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l476xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32L476VGTx_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l476xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l476xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l476xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l476xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l476vg
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
index 11edcd9a8..84f831878 100644
--- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.mk
@@ -2,12 +2,12 @@ CFLAGS += \
   -DSTM32L4P5xx \
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4p5xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32L4P5ZGTX_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l4p5xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l4p5xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l4p5xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l4p5xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l4p5zg
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
index 6dca88a8b..ad5bfba38 100644
--- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.mk
@@ -3,12 +3,12 @@ CFLAGS += \
   -DSTM32L4R5xx \
 
 # GCC
-GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l4r5xx.s
+LD_FILE_GCC = $(BOARD_PATH)/STM32L4RXxI_FLASH.ld
 
 # IAR
-IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l4r5xx.s
-IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l4r5xx_flash.icf
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l4r5xx.s
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l4r5xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32l4r5zi
diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index 4392c6766..d492b9645 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -14,12 +14,12 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_STM32L4
 
 # GCC Flags
-GCC_CFLAGS += \
+CFLAGS_GCC += \
   -flto \
   -nostdlib -nostartfiles
 
 # suppress warning caused by vendor mcu driver
-GCC_CFLAGS += -Wno-error=maybe-uninitialized -Wno-error=cast-align
+CFLAGS_GCC += -Wno-error=maybe-uninitialized -Wno-error=cast-align
 
 # -----------------
 # Sources & Include
diff --git a/tools/make/toolchain/arm_gcc.mk b/tools/make/toolchain/arm_gcc.mk
index 693fda0b3..bba0607df 100644
--- a/tools/make/toolchain/arm_gcc.mk
+++ b/tools/make/toolchain/arm_gcc.mk
@@ -69,6 +69,3 @@ LDFLAGS += \
 ifneq ($(FAMILY),rx)
 LDFLAGS += -Wl,--print-memory-usage
 endif
-
-LDFLAGS += \
-  -Wl,--print-memory-usage \
diff --git a/tools/make/toolchain/arm_gcc_rules.mk b/tools/make/toolchain/arm_gcc_rules.mk
index a39caf351..2e8b9f911 100644
--- a/tools/make/toolchain/arm_gcc_rules.mk
+++ b/tools/make/toolchain/arm_gcc_rules.mk
@@ -1,4 +1,4 @@
-SRC_S += $(GCC_SRC_S)
+SRC_S += $(SRC_S_GCC)
 
 # Assembly files can be name with upper case .S, convert it to .s
 SRC_S := $(SRC_S:.S=.s)
@@ -9,7 +9,7 @@ SRC_S := $(SRC_S:.S=.s)
 OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
 OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
 
-CFLAGS += $(GCC_CFLAGS) -MD
+CFLAGS += $(CFLAGS_GCC) -MD
 
 # LTO makes it difficult to analyze map file for optimizing size purpose
 # We will run this option in ci
@@ -27,8 +27,8 @@ ifdef LD_FILE
 LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE)
 endif
 
-ifdef GCC_LD_FILE
-LDFLAGS += -Wl,-T,$(TOP)/$(GCC_LD_FILE)
+ifdef LD_FILE_GCC
+LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE_GCC)
 endif
 
 ifneq ($(SKIP_NANOLIB), 1)
diff --git a/tools/make/toolchain/arm_iar_rules.mk b/tools/make/toolchain/arm_iar_rules.mk
index 4b5cc90e3..2c066f6da 100644
--- a/tools/make/toolchain/arm_iar_rules.mk
+++ b/tools/make/toolchain/arm_iar_rules.mk
@@ -1,4 +1,4 @@
-SRC_S += $(IAR_SRC_S)
+SRC_S += $(SRC_S_IAR)
 
 # Assembly files can be name with upper case .S, convert it to .s
 SRC_S := $(SRC_S:.S=.s)
@@ -10,7 +10,7 @@ OBJ += $(addprefix $(BUILD)/obj/, $(SRC_S:.s=_asm.o))
 OBJ += $(addprefix $(BUILD)/obj/, $(SRC_C:.c=.o))
 
 # Linker script
-LDFLAGS += --config $(TOP)/$(IAR_LD_FILE)
+LDFLAGS += --config $(TOP)/$(LD_FILE_IAR)
 
 # ---------------------------------------
 # Rules

From eb4380fa14a4cdbd8dde92da74c223b458662dc9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 20:17:48 +0700
Subject: [PATCH 1833/2085] more make update

---
 hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk | 2 ++
 hw/bsp/stm32f0/boards/stm32f072eval/board.mk     | 7 +++----
 hw/bsp/stm32f7/boards/stlinkv3mini/board.mk      | 9 +++------
 hw/bsp/stm32f7/boards/stm32f723disco/board.mk    | 9 +++------
 hw/bsp/stm32f7/boards/stm32f746disco/board.mk    | 9 +++------
 hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk   | 9 +++------
 hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk   | 9 +++------
 hw/bsp/stm32f7/boards/stm32f769disco/board.mk    | 9 +++------
 hw/bsp/stm32f7/family.mk                         | 7 +++++++
 9 files changed, 30 insertions(+), 40 deletions(-)

diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
index f8f0952e8..63f6a31c2 100644
--- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.mk
@@ -1,3 +1,5 @@
+MCU_VARIANT = stm32f070xb
+
 CFLAGS += -DSTM32F070xB -DCFG_EXAMPLE_VIDEO_READONLY
 
 # Linker
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
index c368bd8af..bab889524 100644
--- a/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.mk
@@ -1,11 +1,10 @@
+MCU_VARIANT = stm32f072xb
+
 CFLAGS += -DSTM32F072xB -DLSI_VALUE=40000 -DCFG_EXAMPLE_VIDEO_READONLY
 
-SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f072xb.s
+# Linker
 LD_FILE_GCC = $(BOARD_PATH)/STM32F072VBTx_FLASH.ld
 
-SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f072xb.s
-LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f072xb_flash.icf
-
 # For flash-jlink target
 JLINK_DEVICE = stm32f072vb
 
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
index b59125edc..94dce5e84 100644
--- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk
@@ -1,3 +1,5 @@
+MCU_VARIANT = stm32f723xx
+
 # Only OTG-HS has a connector on this board
 PORT ?= 1
 SPEED ?= high
@@ -6,13 +8,8 @@ CFLAGS += \
   -DSTM32F723xx \
   -DHSE_VALUE=25000000 \
 
-# GCC
-SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
+# Linker
 LD_FILE_GCC = $(BOARD_PATH)/STM32F723xE_FLASH.ld
 
-# IAR
-SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f723xx.s
-LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f723xx_flash.icf
-
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
index 168ca5dad..43e8eafe1 100644
--- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk
@@ -1,3 +1,5 @@
+MCU_VARIANT = stm32f723xx
+
 PORT ?= 1
 SPEED ?= high
 
@@ -5,13 +7,8 @@ CFLAGS += \
   -DSTM32F723xx \
   -DHSE_VALUE=25000000 \
 
-# GCC
+# Linker
 LD_FILE_GCC = $(BOARD_PATH)/STM32F723xE_FLASH.ld
-SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f723xx.s
-
-# IAR
-SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f723xx.s
-LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f723xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.mk b/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
index acda5e2e8..61c0aaa7d 100644
--- a/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.mk
@@ -1,3 +1,5 @@
+MCU_VARIANT = stm32f746xx
+
 PORT ?= 1
 SPEED ?= high
 
@@ -5,13 +7,8 @@ CFLAGS += \
   -DSTM32F746xx \
   -DHSE_VALUE=25000000
 
-# GCC
+# Linker
 LD_FILE_GCC = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
-SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
-
-# IAR
-SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f746xx.s
-LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f746xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
index 511433885..3683c79a5 100644
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk
@@ -1,3 +1,5 @@
+MCU_VARIANT = stm32f746xx
+
 PORT ?= 0
 SPEED ?= full
 
@@ -5,13 +7,8 @@ CFLAGS += \
   -DSTM32F746xx \
   -DHSE_VALUE=8000000
 
-# GCC
+# Linker
 LD_FILE_GCC = $(BOARD_PATH)/STM32F746ZGTx_FLASH.ld
-SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f746xx.s
-
-# IAR
-SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f746xx.s
-LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f746xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
index 329771986..059ad166a 100644
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk
@@ -1,3 +1,5 @@
+MCU_VARIANT = stm32f767xx
+
 PORT ?= 0
 SPEED ?= full
 
@@ -5,13 +7,8 @@ CFLAGS += \
   -DSTM32F767xx \
 	-DHSE_VALUE=8000000 \
 
-# GCC
+# Linker
 LD_FILE_GCC = $(BOARD_PATH)/STM32F767ZITx_FLASH.ld
-SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f767xx.s
-
-# IAR
-SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f767xx.s
-LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f767xx_flash.icf
 
 # For flash-jlink target
 JLINK_DEVICE = stm32f767zi
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.mk b/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
index 20042db98..a45af8cc0 100644
--- a/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
+++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.mk
@@ -1,3 +1,5 @@
+MCU_VARIANT = stm32f769xx
+
 # Only OTG-HS has a connector on this board
 PORT ?= 1
 SPEED ?= high
@@ -6,13 +8,8 @@ CFLAGS += \
   -DSTM32F769xx \
   -DHSE_VALUE=25000000 \
 
-# GCC
+# Linker
 LD_FILE_GCC = $(BOARD_PATH)/STM32F769ZITx_FLASH.ld
-SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f769xx.s
-
-# IAR
-SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f769xx.s
-LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f769xx_flash.icf
 
 # flash target using on-board stlink
 flash: flash-stlink
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index 1a15a743c..4a699ea31 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -56,3 +56,10 @@ INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(ST_CMSIS)/Include \
 	$(TOP)/$(ST_HAL_DRIVER)/Inc
+
+# Startup
+SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s
+SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
+
+# Linker
+LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf

From 38a582634ecb31745600768583651df2468ed913 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 20:32:18 +0700
Subject: [PATCH 1834/2085] fix missing replace

---
 examples/device/cdc_msc_freertos/Makefile       | 4 ++--
 examples/device/hid_composite_freertos/Makefile | 4 ++--
 examples/device/net_lwip_webserver/Makefile     | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 73b4ce608..5b5e513ad 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -37,10 +37,10 @@ SRC_S += \
 # CFLAGS += -Wno-error=sign-compare
 
 # Suppress FreeRTOSConfig.h warnings
-GCC_CFLAGS += -Wno-error=redundant-decls
+CFLAGS_GCC += -Wno-error=redundant-decls
 
 # Suppress FreeRTOS source warnings
-GCC_CFLAGS += -Wno-error=cast-qual
+CFLAGS_GCC += -Wno-error=cast-qual
 
 # FreeRTOS (lto + Os) linker issue
 LDFLAGS += -Wl,--undefined=vTaskSwitchContext
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index 9d30fddf7..cc1526cfe 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -36,10 +36,10 @@ SRC_S += \
 # CFLAGS += -Wno-error=sign-compare
 
 # Suppress FreeRTOSConfig.h warnings
-GCC_CFLAGS += -Wno-error=redundant-decls
+CFLAGS_GCC += -Wno-error=redundant-decls
 
 # Suppress FreeRTOS source warnings
-GCC_CFLAGS += -Wno-error=cast-qual
+CFLAGS_GCC += -Wno-error=cast-qual
 
 # FreeRTOS (lto + Os) linker issue
 LDFLAGS += -Wl,--undefined=vTaskSwitchContext
diff --git a/examples/device/net_lwip_webserver/Makefile b/examples/device/net_lwip_webserver/Makefile
index bc2914b36..90b429d00 100644
--- a/examples/device/net_lwip_webserver/Makefile
+++ b/examples/device/net_lwip_webserver/Makefile
@@ -3,7 +3,7 @@ DEPS_SUBMODULES += lib/lwip
 include ../../make.mk
 
 # suppress warning caused by lwip
-GCC_CFLAGS += \
+CFLAGS_GCC += \
   -Wno-error=null-dereference \
   -Wno-error=unused-parameter \
   -Wno-error=unused-variable

From 946d3fdd4f0b5dc1e5a3cadde25691d6f34e30dc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 21:17:40 +0700
Subject: [PATCH 1835/2085] fix iar with make

---
 examples/device/cdc_msc_freertos/Makefile       | 2 +-
 examples/device/hid_composite_freertos/Makefile | 2 +-
 tools/make/toolchain/arm_gcc_rules.mk           | 2 +-
 tools/make/toolchain/arm_iar.mk                 | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 5b5e513ad..0bee668b7 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -43,6 +43,6 @@ CFLAGS_GCC += -Wno-error=redundant-decls
 CFLAGS_GCC += -Wno-error=cast-qual
 
 # FreeRTOS (lto + Os) linker issue
-LDFLAGS += -Wl,--undefined=vTaskSwitchContext
+LDFLAGS_GCC += -Wl,--undefined=vTaskSwitchContext
 
 include ../../rules.mk
diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile
index cc1526cfe..a892e7d1d 100644
--- a/examples/device/hid_composite_freertos/Makefile
+++ b/examples/device/hid_composite_freertos/Makefile
@@ -42,6 +42,6 @@ CFLAGS_GCC += -Wno-error=redundant-decls
 CFLAGS_GCC += -Wno-error=cast-qual
 
 # FreeRTOS (lto + Os) linker issue
-LDFLAGS += -Wl,--undefined=vTaskSwitchContext
+LDFLAGS_GCC += -Wl,--undefined=vTaskSwitchContext
 
 include ../../rules.mk
diff --git a/tools/make/toolchain/arm_gcc_rules.mk b/tools/make/toolchain/arm_gcc_rules.mk
index 2e8b9f911..f3482b9a8 100644
--- a/tools/make/toolchain/arm_gcc_rules.mk
+++ b/tools/make/toolchain/arm_gcc_rules.mk
@@ -21,7 +21,7 @@ ifneq ($(CFLAGS_SKIP),)
 CFLAGS := $(filter-out $(CFLAGS_SKIP),$(CFLAGS))
 endif
 
-LDFLAGS += $(CFLAGS)
+LDFLAGS += $(CFLAGS) $(LDFLAGS_GCC)
 
 ifdef LD_FILE
 LDFLAGS += -Wl,-T,$(TOP)/$(LD_FILE)
diff --git a/tools/make/toolchain/arm_iar.mk b/tools/make/toolchain/arm_iar.mk
index f1850add7..04c9f22b3 100644
--- a/tools/make/toolchain/arm_iar.mk
+++ b/tools/make/toolchain/arm_iar.mk
@@ -8,4 +8,4 @@ SIZE = size
 CFLAGS += -e --debug --silent
 
 # silent mode
-ASFLAGS += -S
+ASFLAGS += -S $(addprefix -I,$(INC))

From 2a96ef2519d566c654907df0e1198088510774fe Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 21:33:46 +0700
Subject: [PATCH 1836/2085] add cmake for f0, f1

---
 .github/workflows/build_iar.yml               |   4 +-
 .../boards/stm32f070rbnucleo/board.cmake      |  11 ++
 .../stm32f0/boards/stm32f072disco/board.cmake |  11 ++
 .../stm32f0/boards/stm32f072eval/board.cmake  |  12 ++
 hw/bsp/stm32f0/family.cmake                   | 134 ++++++++++++++++++
 .../boards/stm32f103_bluepill/board.cmake     |  13 ++
 .../boards/stm32f103_mini_2/board.cmake       |  12 ++
 hw/bsp/stm32f1/family.cmake                   | 130 +++++++++++++++++
 tools/cmake/cpu/cortex-m0.cmake               |  17 +++
 9 files changed, 342 insertions(+), 2 deletions(-)
 create mode 100644 hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.cmake
 create mode 100644 hw/bsp/stm32f0/boards/stm32f072disco/board.cmake
 create mode 100644 hw/bsp/stm32f0/boards/stm32f072eval/board.cmake
 create mode 100644 hw/bsp/stm32f0/family.cmake
 create mode 100644 hw/bsp/stm32f1/boards/stm32f103_bluepill/board.cmake
 create mode 100644 hw/bsp/stm32f1/boards/stm32f103_mini_2/board.cmake
 create mode 100644 hw/bsp/stm32f1/family.cmake
 create mode 100644 tools/cmake/cpu/cortex-m0.cmake

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 8c9a500d7..39d9b9232 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -32,7 +32,7 @@ jobs:
         # Alphabetical order
         # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
         # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
-        - 'stm32f0 stm32f1 stm32f7 stm32l4'
+        - 'stm32f7 stm32l4'
     steps:
     - name: Clean workspace
       run: |
@@ -58,7 +58,7 @@ jobs:
           # Alphabetical order
           # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
           # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
-          - 'stm32g0 stm32g4 stm32h7'
+          - 'stm32f0 stm32f1 stm32g0 stm32g4 stm32h7'
     steps:
       - name: Clean workspace
         run: |
diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.cmake b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.cmake
new file mode 100644
index 000000000..61fec0d30
--- /dev/null
+++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32f070xb)
+set(JLINK_DEVICE stm32f070rb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32F070rbtx_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F070xB
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.cmake b/hw/bsp/stm32f0/boards/stm32f072disco/board.cmake
new file mode 100644
index 000000000..287593f43
--- /dev/null
+++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32f072xb)
+set(JLINK_DEVICE stm32f072rb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F072RBTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F072xB
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.cmake b/hw/bsp/stm32f0/boards/stm32f072eval/board.cmake
new file mode 100644
index 000000000..42d778cb5
--- /dev/null
+++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT stm32f072xb)
+set(JLINK_DEVICE stm32f072vb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F072VBTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F072xB
+    LSI_VALUE=40000
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake
new file mode 100644
index 000000000..68a69586e
--- /dev/null
+++ b/hw/bsp/stm32f0/family.cmake
@@ -0,0 +1,134 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY f0)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F0 CACHE INTERNAL "")
+
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      )
+
+    update_board(${BOARD_TARGET})
+
+    # Startup
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+    # Linker
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET)
+  family_configure_common(${TARGET})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F0)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  #family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(family_configure_device_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.cmake b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.cmake
new file mode 100644
index 000000000..87b8458a2
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT stm32f103xb)
+set(JLINK_DEVICE stm32f103c8)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F103X8_FLASH.ld)
+set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32f103x8_flash.icf)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F103xB
+    HSE_VALUE=8000000U
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.cmake b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.cmake
new file mode 100644
index 000000000..67a96c4d1
--- /dev/null
+++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.cmake
@@ -0,0 +1,12 @@
+set(MCU_VARIANT stm32f103xb)
+set(JLINK_DEVICE stm32f103rc)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F103XC_FLASH.ld)
+set(LD_FILE_IAR ${CMAKE_CURRENT_LIST_DIR}/stm32f103xc_flash.icf)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F103xB
+    HSE_VALUE=8000000U
+    )
+endfunction()
diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake
new file mode 100644
index 000000000..d42da090d
--- /dev/null
+++ b/hw/bsp/stm32f1/family.cmake
@@ -0,0 +1,130 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY f1)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F1 CACHE INTERNAL "")
+
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      )
+
+    update_board(${BOARD_TARGET})
+
+    # Startup
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET)
+  family_configure_common(${TARGET})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F1)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  #family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(family_configure_device_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
diff --git a/tools/cmake/cpu/cortex-m0.cmake b/tools/cmake/cpu/cortex-m0.cmake
new file mode 100644
index 000000000..bc2257048
--- /dev/null
+++ b/tools/cmake/cpu/cortex-m0.cmake
@@ -0,0 +1,17 @@
+if (TOOLCHAIN STREQUAL "gcc")
+  set(TOOLCHAIN_COMMON_FLAGS
+    -mthumb
+    -mcpu=cortex-m0plus
+    -mfloat-abi=soft
+    )
+
+  set(FREERTOS_PORT GCC_ARM_CM0 CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+  set(TOOLCHAIN_COMMON_FLAGS
+    --cpu cortex-m0
+    )
+
+  set(FREERTOS_PORT IAR_ARM_CM0 CACHE INTERNAL "")
+
+endif ()

From 430f16bf76738ca192cfca872c9fd271bfbb78eb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 22:36:53 +0700
Subject: [PATCH 1837/2085] move all IAR to cmake

---
 .github/workflows/build_iar.yml               |  28 +-
 .../stm32f0/FreeRTOSConfig/FreeRTOSConfig.h   | 165 ++++++
 hw/bsp/stm32f0/family.cmake                   |  12 +-
 .../stm32f1/FreeRTOSConfig/FreeRTOSConfig.h   | 165 ++++++
 hw/bsp/stm32f1/family.cmake                   |   8 +-
 .../stm32f7/FreeRTOSConfig/FreeRTOSConfig.h   | 165 ++++++
 .../stm32f7/boards/stlinkv3mini/board.cmake   |  14 +
 .../stm32f7/boards/stm32f723disco/board.cmake |  14 +
 .../stm32f723disco/stm32f7xx_hal_conf.h       | 472 ------------------
 .../stm32f7/boards/stm32f746disco/board.cmake |  14 +
 .../stm32f746disco/stm32f7xx_hal_conf.h       | 472 ------------------
 .../boards/stm32f746nucleo/board.cmake        |  13 +
 .../stm32f746nucleo/stm32f7xx_hal_conf.h      | 472 ------------------
 .../boards/stm32f767nucleo/board.cmake        |  13 +
 .../stm32f767nucleo/stm32f7xx_hal_conf.h      | 472 ------------------
 .../stm32f7/boards/stm32f769disco/board.cmake |  14 +
 .../stm32f769disco/stm32f7xx_hal_conf.h       | 472 ------------------
 hw/bsp/stm32f7/family.cmake                   | 135 +++++
 .../stlinkv3mini => }/stm32f7xx_hal_conf.h    |   0
 .../boards/stm32g0b1nucleo/board.cmake        |   4 -
 hw/bsp/stm32g0/family.cmake                   |   5 +
 .../stm32g4/boards/b_g474e_dpow1/board.cmake  |   4 -
 .../boards/stm32g474nucleo/board.cmake        |   4 -
 hw/bsp/stm32g4/family.cmake                   |   5 +
 hw/bsp/stm32h7/boards/daisyseed/board.cmake   |   4 -
 .../boards/stm32h723nucleo/board.cmake        |   4 -
 .../stm32h7/boards/stm32h743eval/board.cmake  |   4 -
 .../boards/stm32h743nucleo/board.cmake        |   4 -
 .../stm32h7/boards/stm32h745disco/board.cmake |   4 -
 .../boards/waveshare_openh743i/board.cmake    |   4 -
 hw/bsp/stm32h7/family.cmake                   |   5 +
 .../boards/stm32l412nucleo/board.cmake        |  10 +
 .../stm32l4/boards/stm32l476disco/board.cmake |  10 +
 .../boards/stm32l4p5nucleo/board.cmake        |  10 +
 .../boards/stm32l4r5nucleo/board.cmake        |  11 +
 hw/bsp/stm32l4/family.cmake                   | 136 +++++
 hw/bsp/stm32l4/family.mk                      |   6 +-
 37 files changed, 917 insertions(+), 2437 deletions(-)
 create mode 100644 hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake
 create mode 100644 hw/bsp/stm32f7/boards/stm32f723disco/board.cmake
 delete mode 100644 hw/bsp/stm32f7/boards/stm32f723disco/stm32f7xx_hal_conf.h
 create mode 100644 hw/bsp/stm32f7/boards/stm32f746disco/board.cmake
 delete mode 100644 hw/bsp/stm32f7/boards/stm32f746disco/stm32f7xx_hal_conf.h
 create mode 100644 hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake
 delete mode 100644 hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h
 create mode 100644 hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake
 delete mode 100644 hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h
 create mode 100644 hw/bsp/stm32f7/boards/stm32f769disco/board.cmake
 delete mode 100644 hw/bsp/stm32f7/boards/stm32f769disco/stm32f7xx_hal_conf.h
 create mode 100644 hw/bsp/stm32f7/family.cmake
 rename hw/bsp/stm32f7/{boards/stlinkv3mini => }/stm32f7xx_hal_conf.h (100%)
 create mode 100644 hw/bsp/stm32l4/boards/stm32l412nucleo/board.cmake
 create mode 100644 hw/bsp/stm32l4/boards/stm32l476disco/board.cmake
 create mode 100644 hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.cmake
 create mode 100644 hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.cmake
 create mode 100644 hw/bsp/stm32l4/family.cmake

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 39d9b9232..6273385e7 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -23,32 +23,6 @@ concurrency:
   cancel-in-progress: true
 
 jobs:
-  makefile:
-    runs-on: [self-hosted, Linux, X64, hifiphile]
-    strategy:
-      fail-fast: false
-      matrix:
-        family:
-        # Alphabetical order
-        # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
-        # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
-        - 'stm32f7 stm32l4'
-    steps:
-    - name: Clean workspace
-      run: |
-        echo "Cleaning up previous run"
-        rm -rf "${{ github.workspace }}"
-        mkdir -p "${{ github.workspace }}"
-
-    - name: Checkout TinyUSB
-      uses: actions/checkout@v3
-
-    - name: Get Dependencies
-      run: python3 tools/get_deps.py ${{ matrix.family }}
-
-    - name: Build
-      run: python3 tools/build_family.py ${{ matrix.family }} TOOLCHAIN=iar
-
   cmake:
     runs-on: [self-hosted, Linux, X64, hifiphile]
     strategy:
@@ -58,7 +32,7 @@ jobs:
           # Alphabetical order
           # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
           # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
-          - 'stm32f0 stm32f1 stm32g0 stm32g4 stm32h7'
+          - 'stm32f0 stm32f1 stm32f7 stm32g0 stm32g4 stm32h7 stm32l4'
     steps:
       - name: Clean workspace
         run: |
diff --git a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..fc2f9fc67
--- /dev/null
+++ b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32f0xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake
index 68a69586e..9f6a7f098 100644
--- a/hw/bsp/stm32f0/family.cmake
+++ b/hw/bsp/stm32f0/family.cmake
@@ -34,6 +34,11 @@ endif ()
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
     add_library(${BOARD_TARGET} STATIC
       ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
@@ -58,13 +63,6 @@ function(add_board_target BOARD_TARGET)
 
     update_board(${BOARD_TARGET})
 
-    # Startup
-    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
-
-    # Linker
-    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
     if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
       target_link_options(${BOARD_TARGET} PUBLIC
         "LINKER:--script=${LD_FILE_GNU}"
diff --git a/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..5a6b2300b
--- /dev/null
+++ b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32f1xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake
index d42da090d..ab46c9872 100644
--- a/hw/bsp/stm32f1/family.cmake
+++ b/hw/bsp/stm32f1/family.cmake
@@ -34,6 +34,10 @@ endif ()
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+
     add_library(${BOARD_TARGET} STATIC
       ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
@@ -57,10 +61,6 @@ function(add_board_target BOARD_TARGET)
 
     update_board(${BOARD_TARGET})
 
-    # Startup
-    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
-
     if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
       target_link_options(${BOARD_TARGET} PUBLIC
         "LINKER:--script=${LD_FILE_GNU}"
diff --git a/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..815e567dd
--- /dev/null
+++ b/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32f7xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake b/hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake
new file mode 100644
index 000000000..378e736d4
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT stm32f723xx)
+set(JLINK_DEVICE stm32f723xx)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F723xE_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F723xx
+    HSE_VALUE=25000000
+    # default to PORT 1 High Speed
+    BOARD_TUD_RHPORT=1
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake
new file mode 100644
index 000000000..dd3c35b00
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT stm32f723xx)
+set(JLINK_DEVICE stm32f723ie)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F723xE_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F723xx
+    HSE_VALUE=25000000
+    # default to PORT 1 High Speed
+    BOARD_TUD_RHPORT=1
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f723disco/stm32f7xx_hal_conf.h
deleted file mode 100644
index 581f0e46a..000000000
--- a/hw/bsp/stm32f7/boards/stm32f723disco/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f746disco/board.cmake
new file mode 100644
index 000000000..e44c164b8
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT stm32f746xx)
+set(JLINK_DEVICE stm32f746xx)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F746ZGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F746xx
+    HSE_VALUE=25000000
+    # default to PORT 1 High Speed
+    BOARD_TUD_RHPORT=1
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f746disco/stm32f7xx_hal_conf.h
deleted file mode 100644
index 03dec8f0d..000000000
--- a/hw/bsp/stm32f7/boards/stm32f746disco/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake
new file mode 100644
index 000000000..dd4d4a753
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT stm32f746xx)
+set(JLINK_DEVICE stm32f746xx)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F746ZGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F746xx
+    HSE_VALUE=8000000
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h
deleted file mode 100644
index 03dec8f0d..000000000
--- a/hw/bsp/stm32f7/boards/stm32f746nucleo/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake
new file mode 100644
index 000000000..679a6ce87
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake
@@ -0,0 +1,13 @@
+set(MCU_VARIANT stm32f767xx)
+set(JLINK_DEVICE stm32f767zi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F767ZITx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F767xx
+    HSE_VALUE=8000000
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h
deleted file mode 100644
index 03dec8f0d..000000000
--- a/hw/bsp/stm32f7/boards/stm32f767nucleo/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f769disco/board.cmake
new file mode 100644
index 000000000..62a157c58
--- /dev/null
+++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.cmake
@@ -0,0 +1,14 @@
+set(MCU_VARIANT stm32f769xx)
+set(JLINK_DEVICE stm32f769xx)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F769ZITx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F769xx
+    HSE_VALUE=25000000
+    # default to PORT 1 High Speed
+    BOARD_TUD_RHPORT=1
+    BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+    )
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/boards/stm32f769disco/stm32f7xx_hal_conf.h
deleted file mode 100644
index 581f0e46a..000000000
--- a/hw/bsp/stm32f7/boards/stm32f769disco/stm32f7xx_hal_conf.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f7xx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CONF_H
-#define __STM32F7xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
-/* #define HAL_CAN_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED   */
-/* #define HAL_CRC_MODULE_ENABLED   */
-/* #define HAL_CRYP_MODULE_ENABLED   */
-/* #define HAL_DAC_MODULE_ENABLED   */
-/* #define HAL_DCMI_MODULE_ENABLED  */
-#define HAL_DMA_MODULE_ENABLED
-/* #define HAL_DMA2D_MODULE_ENABLED  */
-/* #define HAL_ETH_MODULE_ENABLED  */
-#define HAL_FLASH_MODULE_ENABLED
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED    */
-/* #define HAL_IWDG_MODULE_ENABLED  */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED  */
-#define HAL_PWR_MODULE_ENABLED
-/* #define HAL_QSPI_MODULE_ENABLED    */
-#define HAL_RCC_MODULE_ENABLED
-/* #define HAL_RNG_MODULE_ENABLED    */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED    */
-/* #define HAL_SD_MODULE_ENABLED   */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED    */
-/* #define HAL_TIM_MODULE_ENABLED    */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED  */
-/* #define HAL_IRDA_MODULE_ENABLED  */
-/* #define HAL_SMARTCARD_MODULE_ENABLED  */
-/* #define HAL_WWDG_MODULE_ENABLED   */
-#define HAL_CORTEX_MODULE_ENABLED
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_JPEG_MODULE_ENABLED */
-/* #define HAL_MDIOS_MODULE_ENABLED */
-
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  ART_ACCLERATOR_ENABLE        1U /* To enable instruction cache and prefetch */
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_JPEG_REGISTER_CALLBACKS        0U /* JPEG register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MDIOS_REGISTER_CALLBACKS       0U /* MDIOS register callback disabled     */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## Ethernet peripheral configuration for NUCLEO 144 board ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)5)       /* 5 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)5)       /* 5 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-/* LAN8742A PHY Address*/
-#define LAN8742A_PHY_ADDRESS            0x00
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 ((uint32_t)0x00000FFF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR                          ((uint16_t)0x1F)    /*!< PHY special control/ status register Offset     */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0004)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0010)  /*!< PHY Duplex mask                                 */
-
-
-#define PHY_ISFR                        ((uint16_t)0x1D)    /*!< PHY Interrupt Source Flag register Offset       */
-#define PHY_ISFR_INT4                   ((uint16_t)0x0010)  /*!< PHY Link down inturrupt                         */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f7xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f7xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f7xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f7xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f7xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f7xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-  #include "stm32f7xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f7xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f7xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f7xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f7xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f7xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f7xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f7xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f7xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f7xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f7xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f7xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f7xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f7xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f7xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f7xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f7xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f7xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f7xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f7xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f7xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f7xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f7xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f7xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f7xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f7xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f7xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f7xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f7xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f7xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f7xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f7xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f7xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f7xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_JPEG_MODULE_ENABLED
- #include "stm32f7xx_hal_jpeg.h"
-#endif /* HAL_JPEG_MODULE_ENABLED */
-
-#ifdef HAL_MDIOS_MODULE_ENABLED
- #include "stm32f7xx_hal_mdios.h"
-#endif /* HAL_MDIOS_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F7xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake
new file mode 100644
index 000000000..3b6ba1a15
--- /dev/null
+++ b/hw/bsp/stm32f7/family.cmake
@@ -0,0 +1,135 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY f7)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32F7 CACHE INTERNAL "")
+
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET)
+  family_configure_common(${TARGET})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F7)
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(family_configure_device_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/stm32f7xx_hal_conf.h b/hw/bsp/stm32f7/stm32f7xx_hal_conf.h
similarity index 100%
rename from hw/bsp/stm32f7/boards/stlinkv3mini/stm32f7xx_hal_conf.h
rename to hw/bsp/stm32f7/stm32f7xx_hal_conf.h
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
index 1ebf8a700..defeb0114 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
@@ -2,10 +2,6 @@
 set(JLINK_DEVICE STM32G0B1RE)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G0B1RETx_FLASH.ld)
-set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/stm32g0b1xx_flash.icf)
-
-set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_stm32g0b1xx.s)
-set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_stm32g0b1xx.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index 1381eaa5f..fa93566bf 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -34,6 +34,11 @@ endif ()
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
     add_library(${BOARD_TARGET} STATIC
       ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
index 9b72672ea..7a276b20d 100644
--- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
+++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.cmake
@@ -2,10 +2,6 @@ set(MCU_VARIANT stm32g474xx)
 set(JLINK_DEVICE stm32g474re)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
-set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
-set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
index 88cd616b3..11c76863f 100644
--- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
+++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.cmake
@@ -2,10 +2,6 @@ set(MCU_VARIANT stm32g474xx)
 set(JLINK_DEVICE stm32g474re)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G474RETx_FLASH.ld)
-set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
-set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index 45525c744..c89993f6d 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -34,6 +34,11 @@ endif ()
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
     add_library(${BOARD_TARGET} STATIC
       ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.cmake b/hw/bsp/stm32h7/boards/daisyseed/board.cmake
index 9fac51128..4811c97e8 100644
--- a/hw/bsp/stm32h7/boards/daisyseed/board.cmake
+++ b/hw/bsp/stm32h7/boards/daisyseed/board.cmake
@@ -2,10 +2,6 @@ set(MCU_VARIANT stm32h750xx)
 set(JLINK_DEVICE stm32h750ibk6_m7)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/stm32h750ibkx_flash.ld)
-set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
-set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake
index ac1acd346..b7d133dfa 100644
--- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake
+++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake
@@ -2,10 +2,6 @@ set(MCU_VARIANT stm32h723xx)
 set(JLINK_DEVICE stm32h723zg)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
-set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
-set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake
index 2cd2a4bac..a28aa87bd 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake
@@ -2,10 +2,6 @@ set(MCU_VARIANT stm32h743xx)
 set(JLINK_DEVICE stm32h743xi)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
-set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
-set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake
index 9d5f09be4..f1532a95f 100644
--- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake
+++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake
@@ -2,10 +2,6 @@ set(MCU_VARIANT stm32h743xx)
 set(JLINK_DEVICE stm32h743xi)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
-set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
-set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake b/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
index 46744df49..f0e8bd70a 100644
--- a/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
@@ -2,10 +2,6 @@ set(MCU_VARIANT stm32h745xx)
 set(JLINK_DEVICE stm32h745xi_m7)
 
 set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_CM7.ld)
-set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash_CM7.icf)
-
-set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake
index 033d3a9f2..83c8d4833 100644
--- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake
+++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake
@@ -2,10 +2,6 @@ set(MCU_VARIANT stm32h743xx)
 set(JLINK_DEVICE stm32h743xi)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld)
-set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
-set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake
index f04a768a5..8f161470e 100644
--- a/hw/bsp/stm32h7/family.cmake
+++ b/hw/bsp/stm32h7/family.cmake
@@ -34,6 +34,11 @@ endif ()
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
     add_library(${BOARD_TARGET} STATIC
       ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.cmake b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.cmake
new file mode 100644
index 000000000..e979a7378
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32l412xx)
+set(JLINK_DEVICE stm32l412kb)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L412KBUx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32L412xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake b/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake
new file mode 100644
index 000000000..4ade0a5c9
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32l476xx)
+set(JLINK_DEVICE stm32l476vg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L476VGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32L476xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.cmake b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.cmake
new file mode 100644
index 000000000..ead241e32
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32l4p5xx)
+set(JLINK_DEVICE stm32l4p5zg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L4P5ZGTX_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32L4P5xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.cmake b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.cmake
new file mode 100644
index 000000000..d4bbe6a94
--- /dev/null
+++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT stm32l4r5xx)
+set(JLINK_DEVICE stm32l4r5zi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L4RXxI_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32L4R5xx
+    HSE_VALUE=8000000
+    )
+endfunction()
diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake
new file mode 100644
index 000000000..d299b2568
--- /dev/null
+++ b/hw/bsp/stm32l4/family.cmake
@@ -0,0 +1,136 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY l4)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32L4 CACHE INTERNAL "")
+
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET)
+  family_configure_common(${TARGET})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_$(FAMILY_MCUS))
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    ${TOP}/src/st/stm32_fsdev/dcd_stm32_fsdev.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
+
+
+function(family_configure_device_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_host_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+  family_configure_example(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk
index d492b9645..c16040887 100644
--- a/hw/bsp/stm32l4/family.mk
+++ b/hw/bsp/stm32l4/family.mk
@@ -32,11 +32,11 @@ SRC_C += \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c
 

From c81d8b43a1f0d366cf273b489ce51a3f21653c87 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 22:58:15 +0700
Subject: [PATCH 1838/2085] fix ci build

---
 hw/bsp/stm32f0/family.cmake                       | 1 +
 hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake | 5 ++---
 hw/bsp/stm32h7/boards/stm32h745disco/board.cmake  | 1 +
 hw/bsp/stm32h7/family.cmake                       | 5 ++++-
 hw/bsp/stm32l4/family.cmake                       | 2 +-
 5 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake
index 9f6a7f098..ecf6a8424 100644
--- a/hw/bsp/stm32f0/family.cmake
+++ b/hw/bsp/stm32f0/family.cmake
@@ -59,6 +59,7 @@ function(add_board_target BOARD_TARGET)
     target_compile_options(${BOARD_TARGET} PUBLIC
       )
     target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CFG_EXAMPLE_MSC_READONLY
       )
 
     update_board(${BOARD_TARGET})
diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
index defeb0114..8874b0526 100644
--- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
+++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.cmake
@@ -1,11 +1,10 @@
-#set(MCU_VARIANT MIMXRT1011)
-set(JLINK_DEVICE STM32G0B1RE)
+set(MCU_VARIANT stm32g0b1xx)
+set(JLINK_DEVICE stm32g0b1re)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32G0B1RETx_FLASH.ld)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     STM32G0B1xx
-    #HSE_VALUE=8000000U
     )
 endfunction()
diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake b/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
index f0e8bd70a..f1313d54e 100644
--- a/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
+++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake
@@ -2,6 +2,7 @@ set(MCU_VARIANT stm32h745xx)
 set(JLINK_DEVICE stm32h745xi_m7)
 
 set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_CM7.ld)
+set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash_CM7.icf)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake
index 8f161470e..f3705edb4 100644
--- a/hw/bsp/stm32h7/family.cmake
+++ b/hw/bsp/stm32h7/family.cmake
@@ -37,7 +37,10 @@ function(add_board_target BOARD_TARGET)
     # Startup & Linker script
     set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
     set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
-    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+    if(NOT DEFINED LD_FILE_IAR)
+      set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+    endif()
 
     add_library(${BOARD_TARGET} STATIC
       ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake
index d299b2568..c8397f418 100644
--- a/hw/bsp/stm32l4/family.cmake
+++ b/hw/bsp/stm32l4/family.cmake
@@ -110,7 +110,7 @@ function(family_configure_example TARGET)
   family_add_tinyusb(${TARGET} OPT_MCU_$(FAMILY_MCUS))
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
-    ${TOP}/src/st/stm32_fsdev/dcd_stm32_fsdev.c
+    ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 

From b9cefb144004691ec201f3bb60619ebac633da4b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 23:10:01 +0700
Subject: [PATCH 1839/2085] fix build with L4

---
 hw/bsp/stm32l4/family.cmake | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake
index c8397f418..83c51c9bf 100644
--- a/hw/bsp/stm32l4/family.cmake
+++ b/hw/bsp/stm32l4/family.cmake
@@ -107,7 +107,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_$(FAMILY_MCUS))
+  family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
     ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c

From a64d5607a745cc655ded19bc91494a9b55dc0dd6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 23:17:28 +0700
Subject: [PATCH 1840/2085] fix l4 freertos build

---
 .../stm32l4/FreeRTOSConfig/FreeRTOSConfig.h   | 165 ++++++++++++++++++
 1 file changed, 165 insertions(+)
 create mode 100644 hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h

diff --git a/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..e6a735ddd
--- /dev/null
+++ b/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32l4xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif

From 9b2b4ce647812150ba03cc29a196ce10564a2c73 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 23:32:24 +0700
Subject: [PATCH 1841/2085] move some family ci make to cmake

---
 .github/workflows/build_arm.yml | 6 ++----
 .github/workflows/cmake_arm.yml | 5 +++++
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 620aec193..94721004c 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -43,11 +43,9 @@ jobs:
         - 'samd11 samd21'
         - 'samd51 same5x'
         - 'saml2x'
-        - 'stm32f0 stm32f1 stm32f2 stm32f3'
+        - 'stm32f2 stm32f3'
         - 'stm32f4'
-        - 'stm32f7'
-        - 'stm32h7'
-        - 'stm32l0 stm32l4 stm32u5 stm32wb'
+        - 'stm32l0 stm32u5 stm32wb'
         - 'tm4c123 xmc4000'
     steps:
     - name: Setup Python
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 2ca8e32f5..ec2f977b6 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -37,8 +37,13 @@ jobs:
           - 'mcx'
           - 'imxrt'
           - 'rp2040'
+          - 'stm32f0'
+          - 'stm32f1'
+          - 'stm32f7'
           - 'stm32g0'
           - 'stm32g4'
+          - 'stm32h7'
+          - 'stm32l4'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4

From 30ccfe083216f5219bfa8e85e0a0a26547a2655c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 24 Jun 2023 23:36:52 +0700
Subject: [PATCH 1842/2085] more cmake less make

---
 .github/workflows/build_arm.yml | 4 ++--
 .github/workflows/cmake_arm.yml | 6 ++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 94721004c..b7e6890f9 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -34,9 +34,9 @@ jobs:
         family:
         # Alphabetical order
         - 'broadcom_32bit'
-        - 'kinetis_k32l2 kinetis_kl'
+        - 'kinetis_k32l2'
         - 'lpc11 lpc13 lpc15 lpc17'
-        - 'lpc51 lpc54 lpc55'
+        - 'lpc51 lpc54'
         - 'mm32 msp432e4'
         - 'nrf'
         - 'ra'
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index ec2f977b6..6d7977de8 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -33,9 +33,11 @@ jobs:
       matrix:
         family:
           # Alphabetical order
-          - 'lpc18'
-          - 'mcx'
           - 'imxrt'
+          - 'kinetis_kl'
+          - 'lpc18'
+          - 'lpc55'
+          - 'mcx'
           - 'rp2040'
           - 'stm32f0'
           - 'stm32f1'

From 15376397b10e6fb35ef7ec4b693271adbafecabf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 25 Jun 2023 00:05:23 +0700
Subject: [PATCH 1843/2085] run ci with -DCMAKE_BUILD_TYPE=MinSizeRel

---
 .github/workflows/build_iar.yml |  2 +-
 .github/workflows/cmake_arm.yml |  2 +-
 hw/bsp/stm32f7/family.c         | 10 ++++++++++
 hw/bsp/stm32f7/family.mk        |  2 +-
 tools/build_cmake.py            | 15 +++++++--------
 5 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 6273385e7..4c5fd770c 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -47,4 +47,4 @@ jobs:
         run: python3 tools/get_deps.py ${{ matrix.family }}
 
       - name: Build
-        run: python3 tools/build_cmake.py ${{ matrix.family }} -DTOOLCHAIN=iar
+        run: python3 tools/build_cmake.py ${{ matrix.family }} -DTOOLCHAIN=iar -DCMAKE_BUILD_TYPE=MinSizeRel
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 6d7977de8..0ce63281e 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -75,7 +75,7 @@ jobs:
       run: python3 tools/get_deps.py ${{ matrix.family }}
 
     - name: Build
-      run: python tools/build_cmake.py ${{ matrix.family }}
+      run: python tools/build_cmake.py ${{ matrix.family }} -DCMAKE_BUILD_TYPE=MinSizeRel
       env:
         # for rp2040, there is no harm if defined for other families
         PICO_SDK_PATH: ${{ github.workspace }}/pico-sdk
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index 88cba2c7d..ce7e9d1bc 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -143,9 +143,19 @@ void board_init(void)
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wshadow"
+#endif
+
   /* Enable USB FS Clocks */
   __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 #if OTG_FS_VBUS_SENSE
   /* Configure VBUS Pin */
   GPIO_InitStruct.Pin = GPIO_PIN_9;
diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk
index 4a699ea31..7f37a7e40 100644
--- a/hw/bsp/stm32f7/family.mk
+++ b/hw/bsp/stm32f7/family.mk
@@ -33,7 +33,7 @@ CFLAGS_GCC += \
   -nostdlib -nostartfiles
 
 # mcu driver cause following warnings
-CFLAGS_GCC += -Wno-error=shadow -Wno-error=cast-align
+CFLAGS_GCC += -Wno-error=cast-align
 
 # -----------------
 # Sources & Include
diff --git a/tools/build_cmake.py b/tools/build_cmake.py
index eb7375ae2..e539b9f94 100644
--- a/tools/build_cmake.py
+++ b/tools/build_cmake.py
@@ -13,8 +13,6 @@ SKIPPED = "\033[33mskipped\033[0m"
 
 build_separator = '-' * 106
 
-toolchain_iar = '-DTOOLCHAIN=iar'
-
 def filter_with_input(mylist):
     if len(sys.argv) > 1:
         input_args = list(set(mylist).intersection(sys.argv))
@@ -22,7 +20,7 @@ def filter_with_input(mylist):
             mylist[:] = input_args
 
 
-def build_family(family, toolchain_option):
+def build_family(family, cmake_option):
     all_boards = []
     for entry in os.scandir("hw/bsp/{}/boards".format(family)):
         if entry.is_dir() and entry.name != 'pico_sdk':
@@ -38,7 +36,7 @@ def build_family(family, toolchain_option):
 
         # Generate build
         r = subprocess.run(f"cmake examples -B {build_dir} -G \"Ninja\" -DFAMILY={family} -DBOARD"
-                           f"={board} {toolchain_option}", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+                           f"={board} {cmake_option}", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
 
         # Build
         if r.returncode == 0:
@@ -74,9 +72,10 @@ def build_family(family, toolchain_option):
 
 
 if __name__ == '__main__':
-    # IAR CC
-    if toolchain_iar not in sys.argv:
-        toolchain_iar = ''
+    cmake_options = ''
+    for a in sys.argv[1:]:
+        if a.startswith('-'):
+            cmake_options += ' ' + a
 
     # If family are not specified in arguments, build all supported
     all_families = []
@@ -93,7 +92,7 @@ if __name__ == '__main__':
     # succeeded, failed, skipped
     total_result = [0, 0, 0]
     for family in all_families:
-        fret = build_family(family, toolchain_iar)
+        fret = build_family(family, cmake_options)
         if len(fret) == len(total_result):
             total_result = [total_result[i] + fret[i] for i in range(len(fret))]
 

From 2ecd7c148db9f370dc151dc2f4fe223a71e9df76 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 25 Jun 2023 09:55:05 +0700
Subject: [PATCH 1844/2085] fix ci with lpc55 and kl, move hw test l4 to cmake
 iar

---
 .github/workflows/build_arm.yml | 128 ++++++++++++++++----------------
 .github/workflows/build_iar.yml |  78 +++++++++++++++++++
 hw/bsp/lpc55/family.cmake       |   6 ++
 tools/get_deps.py               |   4 +-
 4 files changed, 150 insertions(+), 66 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index b7e6890f9..0b770f379 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -101,67 +101,67 @@ jobs:
         path: |
           *.elf
 
-  # ---------------------------------------
-  # Hardware in the loop (HIL)
-  # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
-  # - STM32L412 Nucleo with on-board jlink as ttyACM0
-  # ---------------------------------------
-  hw-stm32l412nucleo-test:
-    needs: build-arm
-    runs-on: [self-hosted, Linux, X64, hifiphile]
-
-    steps:
-    - name: Clean workspace
-      run: |
-        echo "Cleaning up previous run"
-        rm -rf "${{ github.workspace }}"
-        mkdir -p "${{ github.workspace }}"
-
-    - name: Download stm32l4 Artifacts
-      uses: actions/download-artifact@v3
-      with:
-        name: stm32l4
-
-    - name: Create flash.sh
-      run: |
-        echo > flash.sh 'echo halt > flash.jlink'
-        echo >> flash.sh 'echo r >> flash.jlink'
-        echo >> flash.sh 'echo loadfile $1 >> flash.jlink'
-        echo >> flash.sh 'echo r >> flash.jlink'
-        echo >> flash.sh 'echo go >> flash.jlink'
-        echo >> flash.sh 'echo exit >> flash.jlink'
-        echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
-        echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
-        chmod +x flash.sh
-
-    - name: Test cdc_dual_ports
-      run: |
-        ./flash.sh cdc_dual_ports.elf
-        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-
-      # Debian does not auto mount usb drive. skip this test for now
-    - name: Test cdc_msc
-      if: false
-      run: |
-        ./flash.sh cdc_msc.elf
-        readme='/media/pi/TinyUSB MSC/README.TXT'
-        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
-        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-        test -f "$readme" && echo "$readme exists"
-        cat "$readme"
-
-    - name: Test dfu
-      run: |
-        ./flash.sh dfu.elf
-        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
-        dfu-util -d cafe -a 0 -U dfu0
-        dfu-util -d cafe -a 1 -U dfu1
-        grep "TinyUSB DFU! - Partition 0" dfu0
-        grep "TinyUSB DFU! - Partition 1" dfu1
-
-    - name: Test dfu_runtime
-      run: |
-        ./flash.sh dfu_runtime.elf
-        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
+#  # ---------------------------------------
+#  # Hardware in the loop (HIL)
+#  # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
+#  # - STM32L412 Nucleo with on-board jlink as ttyACM0
+#  # ---------------------------------------
+#  hw-stm32l412nucleo-test:
+#    needs: build-arm
+#    runs-on: [self-hosted, Linux, X64, hifiphile]
+#
+#    steps:
+#    - name: Clean workspace
+#      run: |
+#        echo "Cleaning up previous run"
+#        rm -rf "${{ github.workspace }}"
+#        mkdir -p "${{ github.workspace }}"
+#
+#    - name: Download stm32l4 Artifacts
+#      uses: actions/download-artifact@v3
+#      with:
+#        name: stm32l4
+#
+#    - name: Create flash.sh
+#      run: |
+#        echo > flash.sh 'echo halt > flash.jlink'
+#        echo >> flash.sh 'echo r >> flash.jlink'
+#        echo >> flash.sh 'echo loadfile $1 >> flash.jlink'
+#        echo >> flash.sh 'echo r >> flash.jlink'
+#        echo >> flash.sh 'echo go >> flash.jlink'
+#        echo >> flash.sh 'echo exit >> flash.jlink'
+#        echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
+#        echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
+#        chmod +x flash.sh
+#
+#    - name: Test cdc_dual_ports
+#      run: |
+#        ./flash.sh cdc_dual_ports.elf
+#        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
+#        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+#        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
+#
+#      # Debian does not auto mount usb drive. skip this test for now
+#    - name: Test cdc_msc
+#      if: false
+#      run: |
+#        ./flash.sh cdc_msc.elf
+#        readme='/media/pi/TinyUSB MSC/README.TXT'
+#        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
+#        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+#        test -f "$readme" && echo "$readme exists"
+#        cat "$readme"
+#
+#    - name: Test dfu
+#      run: |
+#        ./flash.sh dfu.elf
+#        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
+#        dfu-util -d cafe -a 0 -U dfu0
+#        dfu-util -d cafe -a 1 -U dfu1
+#        grep "TinyUSB DFU! - Partition 0" dfu0
+#        grep "TinyUSB DFU! - Partition 1" dfu1
+#
+#    - name: Test dfu_runtime
+#      run: |
+#        ./flash.sh dfu_runtime.elf
+#        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 4c5fd770c..cafb75cd8 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -48,3 +48,81 @@ jobs:
 
       - name: Build
         run: python3 tools/build_cmake.py ${{ matrix.family }} -DTOOLCHAIN=iar -DCMAKE_BUILD_TYPE=MinSizeRel
+
+      # Upload binaries for hardware test with self-hosted
+      - name: Prepare stm32l412nucleo Artifacts
+        if: contains(matrix.family, 'stm32l4')
+        run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
+
+      - name: Upload Artifacts for stm32l412nucleo
+        if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach'
+        uses: actions/upload-artifact@v3
+        with:
+          name: stm32l4
+          path: |
+            *.elf
+
+  # ---------------------------------------
+  # Hardware in the loop (HIL)
+  # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
+  # - STM32L412 Nucleo with on-board jlink as ttyACM0
+  # ---------------------------------------
+  hw-stm32l412nucleo-test:
+    needs: cmake
+    runs-on: [self-hosted, Linux, X64, hifiphile]
+
+    steps:
+      - name: Clean workspace
+        run: |
+          echo "Cleaning up previous run"
+          rm -rf "${{ github.workspace }}"
+          mkdir -p "${{ github.workspace }}"
+
+      - name: Download stm32l4 Artifacts
+        uses: actions/download-artifact@v3
+        with:
+          name: stm32l4
+
+      - name: Create flash.sh
+        run: |
+          echo > flash.sh 'echo halt > flash.jlink'
+          echo >> flash.sh 'echo r >> flash.jlink'
+          echo >> flash.sh 'echo loadfile $1 >> flash.jlink'
+          echo >> flash.sh 'echo r >> flash.jlink'
+          echo >> flash.sh 'echo go >> flash.jlink'
+          echo >> flash.sh 'echo exit >> flash.jlink'
+          echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
+          echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
+          chmod +x flash.sh
+
+      - name: Test cdc_dual_ports
+        run: |
+          ./flash.sh cdc_dual_ports.elf
+          while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
+          test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+          test -e /dev/ttyACM2 && echo "ttyACM2 exists"
+
+        # Debian does not auto mount usb drive. skip this test for now
+      - name: Test cdc_msc
+        if: false
+        run: |
+          ./flash.sh cdc_msc.elf
+          readme='/media/pi/TinyUSB MSC/README.TXT'
+          while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
+          test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+          test -f "$readme" && echo "$readme exists"
+          cat "$readme"
+
+      - name: Test dfu
+        run: |
+          ./flash.sh dfu.elf
+          while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
+          dfu-util -d cafe -a 0 -U dfu0
+          dfu-util -d cafe -a 1 -U dfu1
+          grep "TinyUSB DFU! - Partition 0" dfu0
+          grep "TinyUSB DFU! - Partition 1" dfu1
+
+      - name: Test dfu_runtime
+        run: |
+          ./flash.sh dfu_runtime.elf
+          while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index 9f6b1f63d..e443f47d3 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -103,6 +103,12 @@ function(family_configure_example TARGET)
     ${TOP}/lib/sct_neopixel/sct_neopixel.c
     )
 
+  # https://github.com/gsteiert/sct_neopixel/pull/1
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    set_source_files_properties(${TOP}/lib/sct_neopixel/sct_neopixel.c PROPERTIES
+      COMPILE_FLAGS "-Wno-unused-parameter")
+  endif ()
+
   target_include_directories(${TARGET} PUBLIC
     # family, hw, board
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
diff --git a/tools/get_deps.py b/tools/get_deps.py
index b81dabae0..34e2f30a3 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -52,7 +52,7 @@ deps_optional = {
                            'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
     'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
                             '950819b7de9b32f92c3edf396bc5ffb8d66e7009',
-                            'kinetis_k32l2 lpc51 lpc54 lpc55 mcx imxrt'],
+                            'kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'],
     'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
                                          'c3715ce94b6f6391856de56081d4d9b3e98fa93d',
                                          'rp2040'],
@@ -166,7 +166,7 @@ deps_optional = {
                             'ch32v307'],
     'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
                     '20285262657d1b482d132d20d755c8c330d55c1f',
-                    'imxrt kinetis_k32l2 lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
+                    'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
                     'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 '
                     'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'],
     'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',

From 06d93e95d15b7b6fad4cde608a25c1b50776ec3e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 25 Jun 2023 10:15:05 +0700
Subject: [PATCH 1845/2085] update hw test l4

---
 .github/workflows/build_iar.yml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index cafb75cd8..4b170f2bd 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -52,7 +52,9 @@ jobs:
       # Upload binaries for hardware test with self-hosted
       - name: Prepare stm32l412nucleo Artifacts
         if: contains(matrix.family, 'stm32l4')
-        run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
+        working-directory: ${{github.workspace}}/cmake-build/cmake-build-stm32l412nucleo
+        run: |
+          find device/ -name "*.elf" -exec mv {} ../../ \;
 
       - name: Upload Artifacts for stm32l412nucleo
         if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach'

From 200e58d11ec6aceec31867129508c77f7989d051 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 26 Jun 2023 13:38:24 +0700
Subject: [PATCH 1846/2085] auto detect FAMILY based on BOARD

---
 .idea/cmake.xml             | 42 ++++++++++++++++++++-----------------
 hw/bsp/family_support.cmake | 21 +++++++++++++++++--
 2 files changed, 42 insertions(+), 21 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 0f7649efc..012dc63ef 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,10 +2,10 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="MinSizeRel" GENERATION_OPTIONS="-DFAMILY=mcx -DBOARD=mcxn947brk -DLOG=0 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=nrf -DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
+      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="MinSizeRel" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
@@ -15,7 +15,7 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="esp32s3" ENABLED="false" GENERATION_OPTIONS="-DFAMILY=espressif -DBOARD=espressif_s3_devkitm -DIDF_TARGET=esp32s3">
+      <configuration PROFILE_NAME="esp32s3" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm -DIDF_TARGET=esp32s3">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
@@ -25,20 +25,24 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=rp2040 -DBOARD=raspberry_pi_pico" />
-      <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1010_evk" />
-      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1060_evk" />
-      <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=imxrt -DBOARD=mimxrt1064_evk" />
-      <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="lpcxpresso18s37" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc18 -DBOARD=lpcxpresso18s37" />
-      <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=lpc55 -DBOARD=lpcxpresso55s69" />
-      <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g0 -DBOARD=stm32g0b1nucleo" />
-      <configuration PROFILE_NAME="stm32g0b1nucleo iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g0 -DBOARD=stm32g0b1nucleo -DTOOLCHAIN=iar" />
-      <configuration PROFILE_NAME="stm32g474nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=stm32g474nucleo" />
-      <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=b_g474e_dpow1 -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="b_g474e_dpow1 iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32g4 -DBOARD=b_g474e_dpow1 -DTOOLCHAIN=iar" />
-      <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=kinetis_kl -DBOARD=frdm_kl25z -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="stm32h743eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DFAMILY=stm32h7 -DBOARD=stm32h743eval -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico" />
+      <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk" />
+      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk" />
+      <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1064_evk" />
+      <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="lpcxpresso18s37" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso18s37" />
+      <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69" />
+      <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g0b1nucleo" />
+      <configuration PROFILE_NAME="stm32g474nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g474nucleo" />
+      <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=b_g474e_dpow1 -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="b_g474e_dpow1 iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=b_g474e_dpow1 -DTOOLCHAIN=iar" />
+      <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_kl25z -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32h743eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="metro m7" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="stm32f072disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f072disco" />
+      <configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2" />
+      <configuration PROFILE_NAME="stm32f769disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f769disco -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 73e674c18..93cab8723 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -11,8 +11,25 @@ if (NOT DEFINED TOOLCHAIN)
   set(TOOLCHAIN gcc)
 endif ()
 
-if (NOT FAMILY)
-  message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, eps32s2, esp32s3). You can do this via -DFAMILY=xxx on the cmake command line")
+# FAMILY not defined, try to detect it from BOARD
+if (NOT DEFINED FAMILY)
+  if (NOT DEFINED BOARD)
+    message(FATAL_ERROR "You must set a FAMILY variable for the build (e.g. rp2040, espressif).
+    You can do this via -DFAMILY=xxx on the cmake command line")
+  endif ()
+
+  # Find path contains BOARD
+  file(GLOB BOARD_PATH LIST_DIRECTORIES true
+    RELATIVE ${TOP}/hw/bsp
+    ${TOP}/hw/bsp/*/boards/${BOARD}
+    )
+  if (NOT BOARD_PATH)
+    message(FATAL_ERROR "Could not detect FAMILY from BOARD=${BOARD}")
+  endif ()
+
+  # replace / with ; so that we can get the first element as FAMILY
+  string(REPLACE "/" ";" BOARD_PATH ${BOARD_PATH})
+  list(GET BOARD_PATH 0 FAMILY)
 endif ()
 
 if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)

From 3cfb838ba7f1f1a12203d36c9cbb615178af2cf7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 26 Jun 2023 17:03:45 +0700
Subject: [PATCH 1847/2085] fix warnings when enable rtt with rp2040

---
 hw/bsp/rp2040/family.c                       | 4 ++--
 hw/bsp/rp2040/family.cmake                   | 6 +++++-
 src/portable/raspberrypi/rp2040/dcd_rp2040.c | 2 +-
 src/portable/raspberrypi/rp2040/rp2040_usb.c | 2 +-
 4 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 3aa989c0e..097e6fbd6 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -93,12 +93,12 @@ bool __no_inline_not_in_flash_func(get_bootsel_button)(void) {
 
 static void stdio_rtt_write (const char *buf, int length)
 {
-  SEGGER_RTT_Write(0, buf, length);
+  SEGGER_RTT_Write(0, buf, (unsigned) length);
 }
 
 static int stdio_rtt_read (char *buf, int len)
 {
-  return SEGGER_RTT_Read(0, buf, len);
+  return (int) SEGGER_RTT_Read(0, buf, (unsigned) len);
 }
 
 static stdio_driver_t stdio_rtt =
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 28637e3ee..5cf6b1219 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -127,7 +127,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 		target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG})
 	endif()
 
-	if(LOGGER STREQUAL "rtt")
+	if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
 		target_compile_definitions(tinyusb_additions INTERFACE
 				LOGGER_RTT
 				SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
@@ -137,6 +137,10 @@ if (NOT TARGET _rp2040_family_inclusion_marker)
 				${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
 		)
 
+		set_source_files_properties(${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+			PROPERTIES
+			COMPILE_FLAGS "-Wno-cast-qual -Wno-cast-align -Wno-sign-conversion")
+
 		target_include_directories(tinyusb_additions INTERFACE
 				${TOP}/lib/SEGGER_RTT/RTT
 		)
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 500a5373f..479b17b67 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -189,7 +189,7 @@ static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_by
 static void __tusb_irq_path_func(hw_handle_buff_status)(void)
 {
     uint32_t remaining_buffers = usb_hw->buf_status;
-    pico_trace("buf_status = 0x%08x\n", remaining_buffers);
+    pico_trace("buf_status = 0x%08lx\n", remaining_buffers);
     uint bit = 1u;
     for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++)
     {
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index cf37cba07..1f49665ff 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -419,7 +419,7 @@ static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoi
   if (delta < 800 || delta > 998) {
     return false;
   }
-  TU_LOG(3, "Avoiding sof %u now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof);
+  TU_LOG(3, "Avoiding sof %lu now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof);
   return true;
 }
 

From 8aa28e63fbcb4f38b62a8e111e29ee48b710db6b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 26 Jun 2023 17:54:31 +0700
Subject: [PATCH 1848/2085] minor clean up with include_guard()

---
 .idea/cmake.xml            |   2 +-
 hw/bsp/rp2040/family.cmake | 674 ++++++++++++++++++-------------------
 src/CMakeLists.txt         |   7 +-
 3 files changed, 342 insertions(+), 341 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 012dc63ef..2ac7993c1 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -25,7 +25,7 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico" />
+      <configuration PROFILE_NAME="rp2040" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk" />
       <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk" />
       <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1064_evk" />
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 5cf6b1219..fee376538 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -1,341 +1,339 @@
 cmake_minimum_required(VERSION 3.13)
-if (NOT TARGET _rp2040_family_inclusion_marker)
-	add_library(_rp2040_family_inclusion_marker INTERFACE)
+include_guard()
 
-	if (NOT BOARD)
-		message("BOARD not specified, defaulting to pico_sdk")
-		set(BOARD pico_sdk)
-	endif()
-
-	# add the SDK in case we are standalone tinyusb example (noop if already present)
-	include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake)
-
-	# include basic family CMake functionality
-	set(FAMILY_MCUS RP2040)
-
-	include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-	# TOP is absolute path to root directory of TinyUSB git repo
-	#set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
-	#get_filename_component(TOP "${TOP}" REALPATH)
-
-	if (NOT PICO_TINYUSB_PATH)
-		set(PICO_TINYUSB_PATH ${TOP})
-	endif()
-
-	if (NOT TINYUSB_OPT_OS)
-		set(TINYUSB_OPT_OS OPT_OS_PICO)
-	endif()
-
-	#------------------------------------
-	# Base config for both device and host; wrapped by SDK's tinyusb_common
-	#------------------------------------
-	add_library(tinyusb_common_base INTERFACE)
-
-	target_sources(tinyusb_common_base INTERFACE
-			${TOP}/src/tusb.c
-			${TOP}/src/common/tusb_fifo.c
-			)
-
-	target_include_directories(tinyusb_common_base INTERFACE
-			${TOP}/src
-			${TOP}/src/common
-			${TOP}/hw
-			)
-
-	target_link_libraries(tinyusb_common_base INTERFACE
-			hardware_structs
-			hardware_irq
-			hardware_resets
-			pico_sync
-			)
-
-	set(TINYUSB_DEBUG_LEVEL 0)
-	if (CMAKE_BUILD_TYPE STREQUAL "Debug")
-		message("Compiling TinyUSB with CFG_TUSB_DEBUG=1")
-		set(TINYUSB_DEBUG_LEVEL 1)
-	endif()
-
-	target_compile_definitions(tinyusb_common_base INTERFACE
-			CFG_TUSB_MCU=OPT_MCU_RP2040
-			CFG_TUSB_OS=${TINYUSB_OPT_OS}
-			#CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
-	)
-
-	#------------------------------------
-	# Base config for device mode; wrapped by SDK's tinyusb_device
-	#------------------------------------
-	add_library(tinyusb_device_base INTERFACE)
-	target_sources(tinyusb_device_base INTERFACE
-			${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c
-			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
-			${TOP}/src/device/usbd.c
-			${TOP}/src/device/usbd_control.c
-			${TOP}/src/class/audio/audio_device.c
-			${TOP}/src/class/cdc/cdc_device.c
-			${TOP}/src/class/dfu/dfu_device.c
-			${TOP}/src/class/dfu/dfu_rt_device.c
-			${TOP}/src/class/hid/hid_device.c
-			${TOP}/src/class/midi/midi_device.c
-			${TOP}/src/class/msc/msc_device.c
-			${TOP}/src/class/net/ecm_rndis_device.c
-			${TOP}/src/class/net/ncm_device.c
-			${TOP}/src/class/usbtmc/usbtmc_device.c
-			${TOP}/src/class/vendor/vendor_device.c
-			${TOP}/src/class/video/video_device.c
-			)
-
-	#------------------------------------
-	# Base config for host mode; wrapped by SDK's tinyusb_host
-	#------------------------------------
-	add_library(tinyusb_host_base INTERFACE)
-	target_sources(tinyusb_host_base INTERFACE
-			${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
-			${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
-			${TOP}/src/host/usbh.c
-			${TOP}/src/host/hub.c
-			${TOP}/src/class/cdc/cdc_host.c
-			${TOP}/src/class/hid/hid_host.c
-			${TOP}/src/class/msc/msc_host.c
-			${TOP}/src/class/vendor/vendor_host.c
-			)
-
-	# Sometimes have to do host specific actions in mostly common functions
-	target_compile_definitions(tinyusb_host_base INTERFACE
-			RP2040_USB_HOST_MODE=1
-	)
-
-	#------------------------------------
-	# BSP & Additions
-	#------------------------------------
-	add_library(tinyusb_bsp INTERFACE)
-	target_sources(tinyusb_bsp INTERFACE
-			${TOP}/hw/bsp/rp2040/family.c
-			)
-	#	target_include_directories(tinyusb_bsp INTERFACE
-	#			${TOP}/hw/bsp/rp2040)
-
-	# tinyusb_additions will hold our extra settings for examples
-	add_library(tinyusb_additions INTERFACE)
-
-	target_compile_definitions(tinyusb_additions INTERFACE
-		PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1
-		PICO_RP2040_USB_DEVICE_UFRAME_FIX=1
-	)
-
-	if(DEFINED LOG)
-		target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG})
-	endif()
-
-	if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
-		target_compile_definitions(tinyusb_additions INTERFACE
-				LOGGER_RTT
-				SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
-		)
-
-		target_sources(tinyusb_additions INTERFACE
-				${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
-		)
-
-		set_source_files_properties(${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
-			PROPERTIES
-			COMPILE_FLAGS "-Wno-cast-qual -Wno-cast-align -Wno-sign-conversion")
-
-		target_include_directories(tinyusb_additions INTERFACE
-				${TOP}/lib/SEGGER_RTT/RTT
-		)
-	endif()
-
-	#------------------------------------
-	# Functions
-	#------------------------------------
-
-	function(family_configure_target TARGET)
-		pico_add_extra_outputs(${TARGET})
-		pico_enable_stdio_uart(${TARGET} 1)
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board tinyusb_additions)
-	endfunction()
-
-	function(rp2040_family_configure_example_warnings TARGET)
-		if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS)
-			family_add_default_example_warnings(${TARGET})
-		endif()
-		if(CMAKE_C_COMPILER_ID STREQUAL "Clang")
-			target_compile_options(${TARGET} PRIVATE -Wno-unreachable-code)
-		endif()
-		suppress_tinyusb_warnings()
-	endfunction()
-
-	function(family_configure_device_example TARGET)
-		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device)
-		rp2040_family_configure_example_warnings(${TARGET})
-	endfunction()
-
-	function(family_add_pico_pio_usb TARGET)
-		target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb)
-	endfunction()
-
-	function(family_configure_host_example TARGET)
-		family_configure_target(${TARGET})
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
-		rp2040_family_configure_example_warnings(${TARGET})
-
-		# For rp2040 enable pico-pio-usb
-		if (TARGET tinyusb_pico_pio_usb)
-			# code does not compile with non GCC, or GCC 11.3+
-			if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND NOT CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3)
-				family_add_pico_pio_usb(${PROJECT})
-			endif()
-		endif()
-	endfunction()
-
-	function(family_configure_dual_usb_example TARGET)
-		family_configure_target(${TARGET})
-		# require tinyusb_pico_pio_usb
-		target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb )
-		rp2040_family_configure_example_warnings(${TARGET})
-	endfunction()
-
-	function(check_and_add_pico_pio_usb_support)
-		# check for pico_generate_pio_header (as depending on environment we may be called before SDK is
-		# initialized in which case it isn't available yet), and only do the initialization once
-		if (COMMAND pico_generate_pio_header AND NOT TARGET tinyusb_pico_pio_usb)
-			#------------------------------------
-			# PIO USB for both host and device
-			#------------------------------------
-
-			if (NOT DEFINED PICO_PIO_USB_PATH)
-				set(PICO_PIO_USB_PATH "${TOP}/hw/mcu/raspberry_pi/Pico-PIO-USB")
-			endif()
-
-			if (EXISTS ${PICO_PIO_USB_PATH}/src/pio_usb.c)
-				add_library(tinyusb_pico_pio_usb INTERFACE)
-				target_sources(tinyusb_device_base INTERFACE
-						${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
-						)
-				target_sources(tinyusb_host_base INTERFACE
-						${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
-						)
-
-				target_sources(tinyusb_pico_pio_usb INTERFACE
-						${PICO_PIO_USB_PATH}/src/pio_usb.c
-						${PICO_PIO_USB_PATH}/src/pio_usb_host.c
-						${PICO_PIO_USB_PATH}/src/pio_usb_device.c
-						${PICO_PIO_USB_PATH}/src/usb_crc.c
-						)
-
-				target_include_directories(tinyusb_pico_pio_usb INTERFACE
-						${PICO_PIO_USB_PATH}/src
-						)
-
-				target_link_libraries(tinyusb_pico_pio_usb INTERFACE
-						hardware_dma
-						hardware_pio
-						pico_multicore
-						)
-
-				target_compile_definitions(tinyusb_pico_pio_usb INTERFACE
-						PIO_USB_USE_TINYUSB
-						)
-
-				pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_tx.pio)
-				pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_rx.pio)
-			endif()
-		endif()
-	endfunction()
-
-	# Try to add Pico-PIO_USB support now for the case where this file is included directly
-	# after Pico SDK initialization, but without using the family_ functions (as is the case
-	# when included by the SDK itself)
-	check_and_add_pico_pio_usb_support()
-
-	function(family_initialize_project PROJECT DIR)
-		# call the original version of this function from family_common.cmake
-		_family_initialize_project(${PROJECT} ${DIR})
-		enable_language(C CXX ASM)
-		pico_sdk_init()
-
-		# now re-check for adding Pico-PIO_USB support now SDK is definitely available
-		check_and_add_pico_pio_usb_support()
-	endfunction()
-
-	# This method must be called from the project scope to suppress known warnings in TinyUSB source files
-	function(suppress_tinyusb_warnings)
-		# some of these are pretty silly warnings only occurring in some older GCC versions 9 or prior
-		if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-			if (CMAKE_C_COMPILER_VERSION VERSION_LESS 10.0)
-				set(CONVERSION_WARNING_FILES
-					${PICO_TINYUSB_PATH}/src/tusb.c
-					${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
-					${PICO_TINYUSB_PATH}/src/device/usbd.c
-					${PICO_TINYUSB_PATH}/src/device/usbd_control.c
-					${PICO_TINYUSB_PATH}/src/host/usbh.c
-					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
-					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
-					${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c
-					${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c
-					${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c
-					${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c
-					${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c
-					${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c
-					${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c
-					${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
-					)
-				foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES)
-					set_source_files_properties(
-							${SOURCE_FILE}
-							PROPERTIES
-							COMPILE_FLAGS "-Wno-conversion")
-				endforeach()
-			endif()
-			if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0)
-				set_source_files_properties(
-						${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
-						COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds")
-			endif()
-			set_source_files_properties(
-					${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
-					PROPERTIES
-					COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual")
-
-			set_source_files_properties(
-					${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_in.c
-					${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_out.c
-					PROPERTIES
-					COMPILE_FLAGS "-Wno-conversion")
-
-			set_source_files_properties(
-					${PICO_TINYUSB_PATH}/lib/networking/dnserver.c
-					${PICO_TINYUSB_PATH}/lib/networking/dhserver.c
-					${PICO_TINYUSB_PATH}/lib/networking/rndis_reports.c
-					PROPERTIES
-					COMPILE_FLAGS "-Wno-conversion -Wno-sign-conversion")
-
-			if (TARGET tinyusb_pico_pio_usb)
-				set_source_files_properties(
-						${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_device.c
-						${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb.c
-						${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_host.c
-						${PICO_TINYUSB_PATH}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
-						PROPERTIES
-						COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-attributes")
-			endif()
-		elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang")
-			set_source_files_properties(
-					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
-					COMPILE_FLAGS "-Wno-unreachable-code")
-			set_source_files_properties(
-					${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
-					COMPILE_FLAGS "-Wno-unreachable-code-fallthrough")
-			set_source_files_properties(
-					${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
-					PROPERTIES
-					COMPILE_FLAGS "-Wno-cast-qual")
-		endif()
-	endfunction()
-
-	# rp2040 does not support freeRTOS example yet
-	function(family_add_freertos TARGET)
-	endfunction()
+if (NOT BOARD)
+	message("BOARD not specified, defaulting to pico_sdk")
+	set(BOARD pico_sdk)
 endif()
+
+# add the SDK in case we are standalone tinyusb example (noop if already present)
+include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake)
+
+# include basic family CMake functionality
+set(FAMILY_MCUS RP2040)
+
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# TOP is absolute path to root directory of TinyUSB git repo
+#set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
+#get_filename_component(TOP "${TOP}" REALPATH)
+
+if (NOT PICO_TINYUSB_PATH)
+	set(PICO_TINYUSB_PATH ${TOP})
+endif()
+
+if (NOT TINYUSB_OPT_OS)
+	set(TINYUSB_OPT_OS OPT_OS_PICO)
+endif()
+
+#------------------------------------
+# Base config for both device and host; wrapped by SDK's tinyusb_common
+#------------------------------------
+add_library(tinyusb_common_base INTERFACE)
+
+target_sources(tinyusb_common_base INTERFACE
+		${TOP}/src/tusb.c
+		${TOP}/src/common/tusb_fifo.c
+		)
+
+target_include_directories(tinyusb_common_base INTERFACE
+		${TOP}/src
+		${TOP}/src/common
+		${TOP}/hw
+		)
+
+target_link_libraries(tinyusb_common_base INTERFACE
+		hardware_structs
+		hardware_irq
+		hardware_resets
+		pico_sync
+		)
+
+set(TINYUSB_DEBUG_LEVEL 0)
+if (CMAKE_BUILD_TYPE STREQUAL "Debug")
+	message("Compiling TinyUSB with CFG_TUSB_DEBUG=1")
+	set(TINYUSB_DEBUG_LEVEL 1)
+endif()
+
+target_compile_definitions(tinyusb_common_base INTERFACE
+		CFG_TUSB_MCU=OPT_MCU_RP2040
+		CFG_TUSB_OS=${TINYUSB_OPT_OS}
+		#CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
+)
+
+#------------------------------------
+# Base config for device mode; wrapped by SDK's tinyusb_device
+#------------------------------------
+add_library(tinyusb_device_base INTERFACE)
+target_sources(tinyusb_device_base INTERFACE
+		${TOP}/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+		${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
+		${TOP}/src/device/usbd.c
+		${TOP}/src/device/usbd_control.c
+		${TOP}/src/class/audio/audio_device.c
+		${TOP}/src/class/cdc/cdc_device.c
+		${TOP}/src/class/dfu/dfu_device.c
+		${TOP}/src/class/dfu/dfu_rt_device.c
+		${TOP}/src/class/hid/hid_device.c
+		${TOP}/src/class/midi/midi_device.c
+		${TOP}/src/class/msc/msc_device.c
+		${TOP}/src/class/net/ecm_rndis_device.c
+		${TOP}/src/class/net/ncm_device.c
+		${TOP}/src/class/usbtmc/usbtmc_device.c
+		${TOP}/src/class/vendor/vendor_device.c
+		${TOP}/src/class/video/video_device.c
+		)
+
+#------------------------------------
+# Base config for host mode; wrapped by SDK's tinyusb_host
+#------------------------------------
+add_library(tinyusb_host_base INTERFACE)
+target_sources(tinyusb_host_base INTERFACE
+		${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+		${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c
+		${TOP}/src/host/usbh.c
+		${TOP}/src/host/hub.c
+		${TOP}/src/class/cdc/cdc_host.c
+		${TOP}/src/class/hid/hid_host.c
+		${TOP}/src/class/msc/msc_host.c
+		${TOP}/src/class/vendor/vendor_host.c
+		)
+
+# Sometimes have to do host specific actions in mostly common functions
+target_compile_definitions(tinyusb_host_base INTERFACE
+		RP2040_USB_HOST_MODE=1
+)
+
+#------------------------------------
+# BSP & Additions
+#------------------------------------
+add_library(tinyusb_bsp INTERFACE)
+target_sources(tinyusb_bsp INTERFACE
+		${TOP}/hw/bsp/rp2040/family.c
+		)
+#	target_include_directories(tinyusb_bsp INTERFACE
+#			${TOP}/hw/bsp/rp2040)
+
+# tinyusb_additions will hold our extra settings for examples
+add_library(tinyusb_additions INTERFACE)
+
+target_compile_definitions(tinyusb_additions INTERFACE
+	PICO_RP2040_USB_DEVICE_ENUMERATION_FIX=1
+	PICO_RP2040_USB_DEVICE_UFRAME_FIX=1
+)
+
+if(DEFINED LOG)
+	target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG})
+endif()
+
+if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
+	target_compile_definitions(tinyusb_additions INTERFACE
+			LOGGER_RTT
+			SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL
+	)
+
+	target_sources(tinyusb_additions INTERFACE
+			${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+	)
+
+	set_source_files_properties(${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+		PROPERTIES
+		COMPILE_FLAGS "-Wno-cast-qual -Wno-cast-align -Wno-sign-conversion")
+
+	target_include_directories(tinyusb_additions INTERFACE
+			${TOP}/lib/SEGGER_RTT/RTT
+	)
+endif()
+
+#------------------------------------
+# Functions
+#------------------------------------
+
+function(family_configure_target TARGET)
+	pico_add_extra_outputs(${TARGET})
+	pico_enable_stdio_uart(${TARGET} 1)
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board tinyusb_additions)
+endfunction()
+
+function(rp2040_family_configure_example_warnings TARGET)
+	if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS)
+		family_add_default_example_warnings(${TARGET})
+	endif()
+	if(CMAKE_C_COMPILER_ID STREQUAL "Clang")
+		target_compile_options(${TARGET} PRIVATE -Wno-unreachable-code)
+	endif()
+	suppress_tinyusb_warnings()
+endfunction()
+
+function(family_configure_device_example TARGET)
+	family_configure_target(${TARGET})
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device)
+	rp2040_family_configure_example_warnings(${TARGET})
+endfunction()
+
+function(family_add_pico_pio_usb TARGET)
+	target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb)
+endfunction()
+
+function(family_configure_host_example TARGET)
+	family_configure_target(${TARGET})
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
+	rp2040_family_configure_example_warnings(${TARGET})
+
+	# For rp2040 enable pico-pio-usb
+	if (TARGET tinyusb_pico_pio_usb)
+		# code does not compile with non GCC, or GCC 11.3+
+		if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND NOT CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3)
+			family_add_pico_pio_usb(${PROJECT})
+		endif()
+	endif()
+endfunction()
+
+function(family_configure_dual_usb_example TARGET)
+	family_configure_target(${TARGET})
+	# require tinyusb_pico_pio_usb
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb )
+	rp2040_family_configure_example_warnings(${TARGET})
+endfunction()
+
+function(check_and_add_pico_pio_usb_support)
+	# check for pico_generate_pio_header (as depending on environment we may be called before SDK is
+	# initialized in which case it isn't available yet), and only do the initialization once
+	if (COMMAND pico_generate_pio_header AND NOT TARGET tinyusb_pico_pio_usb)
+		#------------------------------------
+		# PIO USB for both host and device
+		#------------------------------------
+
+		if (NOT DEFINED PICO_PIO_USB_PATH)
+			set(PICO_PIO_USB_PATH "${TOP}/hw/mcu/raspberry_pi/Pico-PIO-USB")
+		endif()
+
+		if (EXISTS ${PICO_PIO_USB_PATH}/src/pio_usb.c)
+			add_library(tinyusb_pico_pio_usb INTERFACE)
+			target_sources(tinyusb_device_base INTERFACE
+					${TOP}/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c
+					)
+			target_sources(tinyusb_host_base INTERFACE
+					${TOP}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+					)
+
+			target_sources(tinyusb_pico_pio_usb INTERFACE
+					${PICO_PIO_USB_PATH}/src/pio_usb.c
+					${PICO_PIO_USB_PATH}/src/pio_usb_host.c
+					${PICO_PIO_USB_PATH}/src/pio_usb_device.c
+					${PICO_PIO_USB_PATH}/src/usb_crc.c
+					)
+
+			target_include_directories(tinyusb_pico_pio_usb INTERFACE
+					${PICO_PIO_USB_PATH}/src
+					)
+
+			target_link_libraries(tinyusb_pico_pio_usb INTERFACE
+					hardware_dma
+					hardware_pio
+					pico_multicore
+					)
+
+			target_compile_definitions(tinyusb_pico_pio_usb INTERFACE
+					PIO_USB_USE_TINYUSB
+					)
+
+			pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_tx.pio)
+			pico_generate_pio_header(tinyusb_pico_pio_usb ${PICO_PIO_USB_PATH}/src/usb_rx.pio)
+		endif()
+	endif()
+endfunction()
+
+# Try to add Pico-PIO_USB support now for the case where this file is included directly
+# after Pico SDK initialization, but without using the family_ functions (as is the case
+# when included by the SDK itself)
+check_and_add_pico_pio_usb_support()
+
+function(family_initialize_project PROJECT DIR)
+	# call the original version of this function from family_common.cmake
+	_family_initialize_project(${PROJECT} ${DIR})
+	enable_language(C CXX ASM)
+	pico_sdk_init()
+
+	# now re-check for adding Pico-PIO_USB support now SDK is definitely available
+	check_and_add_pico_pio_usb_support()
+endfunction()
+
+# This method must be called from the project scope to suppress known warnings in TinyUSB source files
+function(suppress_tinyusb_warnings)
+	# some of these are pretty silly warnings only occurring in some older GCC versions 9 or prior
+	if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+		if (CMAKE_C_COMPILER_VERSION VERSION_LESS 10.0)
+			set(CONVERSION_WARNING_FILES
+				${PICO_TINYUSB_PATH}/src/tusb.c
+				${PICO_TINYUSB_PATH}/src/common/tusb_fifo.c
+				${PICO_TINYUSB_PATH}/src/device/usbd.c
+				${PICO_TINYUSB_PATH}/src/device/usbd_control.c
+				${PICO_TINYUSB_PATH}/src/host/usbh.c
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
+				${PICO_TINYUSB_PATH}/src/class/hid/hid_device.c
+				${PICO_TINYUSB_PATH}/src/class/hid/hid_host.c
+				${PICO_TINYUSB_PATH}/src/class/audio/audio_device.c
+				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_device.c
+				${PICO_TINYUSB_PATH}/src/class/dfu/dfu_rt_device.c
+				${PICO_TINYUSB_PATH}/src/class/midi/midi_device.c
+				${PICO_TINYUSB_PATH}/src/class/usbtmc/usbtmc_device.c
+				${PICO_TINYUSB_PATH}/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+				)
+			foreach(SOURCE_FILE IN LISTS CONVERSION_WARNING_FILES)
+				set_source_files_properties(
+						${SOURCE_FILE}
+						PROPERTIES
+						COMPILE_FLAGS "-Wno-conversion")
+			endforeach()
+		endif()
+		if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.0)
+			set_source_files_properties(
+					${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
+					COMPILE_FLAGS "-Wno-stringop-overflow -Wno-array-bounds")
+		endif()
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual")
+
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_in.c
+				${PICO_TINYUSB_PATH}/lib/lwip/src/core/tcp_out.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion")
+
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/lib/networking/dnserver.c
+				${PICO_TINYUSB_PATH}/lib/networking/dhserver.c
+				${PICO_TINYUSB_PATH}/lib/networking/rndis_reports.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-conversion -Wno-sign-conversion")
+
+		if (TARGET tinyusb_pico_pio_usb)
+			set_source_files_properties(
+					${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_device.c
+					${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb.c
+					${PICO_TINYUSB_PATH}/hw/mcu/raspberry_pi/Pico-PIO-USB/src/pio_usb_host.c
+					${PICO_TINYUSB_PATH}/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+					PROPERTIES
+					COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual -Wno-attributes")
+		endif()
+	elseif(CMAKE_C_COMPILER_ID STREQUAL "Clang")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_device.c
+				COMPILE_FLAGS "-Wno-unreachable-code")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/src/class/cdc/cdc_host.c
+				COMPILE_FLAGS "-Wno-unreachable-code-fallthrough")
+		set_source_files_properties(
+				${PICO_TINYUSB_PATH}/lib/fatfs/source/ff.c
+				PROPERTIES
+				COMPILE_FLAGS "-Wno-cast-qual")
+	endif()
+endfunction()
+
+# rp2040 does not support freeRTOS example yet
+function(family_add_freertos TARGET)
+endfunction()
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index b99c7be6e..8f7f38589 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -75,8 +75,11 @@ endfunction()
 #------------------------------------
 # TinyUSB as library target
 #------------------------------------
-set(TINYUSB_TARGET "tinyusb")
-set(TINYUSB_CONFIG_TARGET "tinyusb_config")
+if (NOT DEFINED TINYUSB_TARGET)
+  set(TINYUSB_TARGET "tinyusb")
+endif ()
+
+set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET}_config")
 
 if (DEFINED TINYUSB_TARGET_PREFIX)
   set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_TARGET}")

From a61d0f074fbca389ff5e8744dfcb610aafd8ae1e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 26 Jun 2023 23:08:59 +0700
Subject: [PATCH 1849/2085] more rp2040 family clean up

---
 hw/bsp/rp2040/family.cmake | 42 ++++++++++++++++----------------------
 1 file changed, 18 insertions(+), 24 deletions(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index fee376538..2d37f8be9 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -14,10 +14,6 @@ set(FAMILY_MCUS RP2040)
 
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
-# TOP is absolute path to root directory of TinyUSB git repo
-#set(TOP "${CMAKE_CURRENT_LIST_DIR}/../../..")
-#get_filename_component(TOP "${TOP}" REALPATH)
-
 if (NOT PICO_TINYUSB_PATH)
 	set(PICO_TINYUSB_PATH ${TOP})
 endif()
@@ -38,29 +34,30 @@ target_sources(tinyusb_common_base INTERFACE
 
 target_include_directories(tinyusb_common_base INTERFACE
 		${TOP}/src
-		${TOP}/src/common
-		${TOP}/hw
 		)
 
-target_link_libraries(tinyusb_common_base INTERFACE
-		hardware_structs
-		hardware_irq
-		hardware_resets
-		pico_sync
-		)
-
-set(TINYUSB_DEBUG_LEVEL 0)
-if (CMAKE_BUILD_TYPE STREQUAL "Debug")
+if(DEFINED LOG)
+	set(TINYUSB_DEBUG_LEVEL ${LOG})
+elseif (CMAKE_BUILD_TYPE STREQUAL "Debug")
 	message("Compiling TinyUSB with CFG_TUSB_DEBUG=1")
 	set(TINYUSB_DEBUG_LEVEL 1)
+else ()
+	set(TINYUSB_DEBUG_LEVEL 0)
 endif()
 
 target_compile_definitions(tinyusb_common_base INTERFACE
 		CFG_TUSB_MCU=OPT_MCU_RP2040
 		CFG_TUSB_OS=${TINYUSB_OPT_OS}
-		#CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
+		CFG_TUSB_DEBUG=${TINYUSB_DEBUG_LEVEL}
 )
 
+target_link_libraries(tinyusb_common_base INTERFACE
+	hardware_structs
+	hardware_irq
+	hardware_resets
+	pico_sync
+	)
+
 #------------------------------------
 # Base config for device mode; wrapped by SDK's tinyusb_device
 #------------------------------------
@@ -109,10 +106,11 @@ target_compile_definitions(tinyusb_host_base INTERFACE
 #------------------------------------
 add_library(tinyusb_bsp INTERFACE)
 target_sources(tinyusb_bsp INTERFACE
-		${TOP}/hw/bsp/rp2040/family.c
-		)
-#	target_include_directories(tinyusb_bsp INTERFACE
-#			${TOP}/hw/bsp/rp2040)
+	${TOP}/hw/bsp/rp2040/family.c
+	)
+target_include_directories(tinyusb_bsp INTERFACE
+	${TOP}/hw
+	)
 
 # tinyusb_additions will hold our extra settings for examples
 add_library(tinyusb_additions INTERFACE)
@@ -122,10 +120,6 @@ target_compile_definitions(tinyusb_additions INTERFACE
 	PICO_RP2040_USB_DEVICE_UFRAME_FIX=1
 )
 
-if(DEFINED LOG)
-	target_compile_definitions(tinyusb_additions INTERFACE CFG_TUSB_DEBUG=${LOG})
-endif()
-
 if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
 	target_compile_definitions(tinyusb_additions INTERFACE
 			LOGGER_RTT

From e43387abaca2044f96017481ccb00b3b68dbdc2a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 27 Jun 2023 15:45:38 +0700
Subject: [PATCH 1850/2085] rework cmake with rtos support add RTOS to
 family_configure_device/host/dual_example()

---
 .../device/audio_4_channel_mic/CMakeLists.txt |   6 +-
 examples/device/audio_test/CMakeLists.txt     |   6 +-
 .../audio_test_multi_rate/CMakeLists.txt      |   6 +-
 examples/device/board_test/CMakeLists.txt     |   6 +-
 examples/device/cdc_dual_ports/CMakeLists.txt |   6 +-
 examples/device/cdc_msc/CMakeLists.txt        |   2 +-
 .../device/cdc_msc_freertos/CMakeLists.txt    |   9 +-
 examples/device/dfu/CMakeLists.txt            |   6 +-
 examples/device/dfu_runtime/CMakeLists.txt    |   6 +-
 .../dynamic_configuration/CMakeLists.txt      |   6 +-
 .../device/hid_boot_interface/CMakeLists.txt  |   6 +-
 examples/device/hid_composite/CMakeLists.txt  |   6 +-
 .../hid_composite_freertos/CMakeLists.txt     |   9 +-
 .../device/hid_generic_inout/CMakeLists.txt   |   6 +-
 .../hid_multiple_interface/CMakeLists.txt     |   6 +-
 examples/device/midi_test/CMakeLists.txt      |   6 +-
 examples/device/msc_dual_lun/CMakeLists.txt   |   6 +-
 .../device/net_lwip_webserver/CMakeLists.txt  |   6 +-
 examples/device/uac2_headset/CMakeLists.txt   |   6 +-
 examples/device/usbtmc/CMakeLists.txt         |   6 +-
 examples/device/video_capture/CMakeLists.txt  |   6 +-
 examples/device/webusb_serial/CMakeLists.txt  |   6 +-
 .../host_hid_to_device_cdc/CMakeLists.txt     |   6 +-
 examples/host/bare_api/CMakeLists.txt         |   6 +-
 examples/host/cdc_msc_hid/CMakeLists.txt      |   6 +-
 examples/host/hid_controller/CMakeLists.txt   |   6 +-
 .../host/msc_file_explorer/CMakeLists.txt     |   6 +-
 examples/typec/power_delivery/CMakeLists.txt  |   6 +-
 .../typec/power_delivery/src/tusb_config.h    |  14 +-
 hw/bsp/family_support.cmake                   | 174 ++++++++++--------
 hw/bsp/imxrt/family.cmake                     |  19 +-
 hw/bsp/kinetis_kl/family.cmake                |  19 +-
 hw/bsp/lpc18/family.cmake                     |  19 +-
 hw/bsp/lpc55/family.cmake                     |  19 +-
 hw/bsp/mcx/family.cmake                       |  19 +-
 hw/bsp/nrf/family.cmake                       |  19 +-
 hw/bsp/rp2040/family.cmake                    |  43 +++--
 hw/bsp/stm32f0/family.cmake                   |  19 +-
 hw/bsp/stm32f1/family.cmake                   |  19 +-
 hw/bsp/stm32f7/family.cmake                   |  19 +-
 hw/bsp/stm32g0/family.cmake                   |  19 +-
 hw/bsp/stm32g4/family.cmake                   |  19 +-
 hw/bsp/stm32h7/family.cmake                   |  19 +-
 hw/bsp/stm32l4/family.cmake                   |  19 +-
 src/common/tusb_compiler.h                    |   8 +-
 test/fuzz/device/cdc/CMakeLists.txt           |  18 +-
 test/fuzz/device/msc/CMakeLists.txt           |   6 +-
 test/fuzz/device/net/CMakeLists.txt           |   6 +-
 48 files changed, 277 insertions(+), 409 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/CMakeLists.txt b/examples/device/audio_4_channel_mic/CMakeLists.txt
index 87b7d07d4..f61e1b640 100644
--- a/examples/device/audio_4_channel_mic/CMakeLists.txt
+++ b/examples/device/audio_4_channel_mic/CMakeLists.txt
@@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/audio_test/CMakeLists.txt b/examples/device/audio_test/CMakeLists.txt
index 87b7d07d4..f61e1b640 100644
--- a/examples/device/audio_test/CMakeLists.txt
+++ b/examples/device/audio_test/CMakeLists.txt
@@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/audio_test_multi_rate/CMakeLists.txt b/examples/device/audio_test_multi_rate/CMakeLists.txt
index 87b7d07d4..f61e1b640 100644
--- a/examples/device/audio_test_multi_rate/CMakeLists.txt
+++ b/examples/device/audio_test_multi_rate/CMakeLists.txt
@@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt
index 4ab8d5a65..012eff095 100644
--- a/examples/device/board_test/CMakeLists.txt
+++ b/examples/device/board_test/CMakeLists.txt
@@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/cdc_dual_ports/CMakeLists.txt b/examples/device/cdc_dual_ports/CMakeLists.txt
index 87b7d07d4..f61e1b640 100644
--- a/examples/device/cdc_dual_ports/CMakeLists.txt
+++ b/examples/device/cdc_dual_ports/CMakeLists.txt
@@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt
index 4ec172f17..9415f8c68 100644
--- a/examples/device/cdc_msc/CMakeLists.txt
+++ b/examples/device/cdc_msc/CMakeLists.txt
@@ -32,4 +32,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt
index 319ad0356..33c7a1ec0 100644
--- a/examples/device/cdc_msc_freertos/CMakeLists.txt
+++ b/examples/device/cdc_msc_freertos/CMakeLists.txt
@@ -30,9 +30,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
-
-# Add FreeRTOS for this example
-family_add_freertos(${PROJECT})
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/dfu/CMakeLists.txt b/examples/device/dfu/CMakeLists.txt
index eb4c198d6..a01eb3456 100644
--- a/examples/device/dfu/CMakeLists.txt
+++ b/examples/device/dfu/CMakeLists.txt
@@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/dfu_runtime/CMakeLists.txt b/examples/device/dfu_runtime/CMakeLists.txt
index eb4c198d6..a01eb3456 100644
--- a/examples/device/dfu_runtime/CMakeLists.txt
+++ b/examples/device/dfu_runtime/CMakeLists.txt
@@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/dynamic_configuration/CMakeLists.txt b/examples/device/dynamic_configuration/CMakeLists.txt
index 046a32257..2b20d2234 100644
--- a/examples/device/dynamic_configuration/CMakeLists.txt
+++ b/examples/device/dynamic_configuration/CMakeLists.txt
@@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_boot_interface/CMakeLists.txt b/examples/device/hid_boot_interface/CMakeLists.txt
index eb4c198d6..a01eb3456 100644
--- a/examples/device/hid_boot_interface/CMakeLists.txt
+++ b/examples/device/hid_boot_interface/CMakeLists.txt
@@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_composite/CMakeLists.txt b/examples/device/hid_composite/CMakeLists.txt
index eb4c198d6..a01eb3456 100644
--- a/examples/device/hid_composite/CMakeLists.txt
+++ b/examples/device/hid_composite/CMakeLists.txt
@@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt
index 211904cf9..eb22014fb 100644
--- a/examples/device/hid_composite_freertos/CMakeLists.txt
+++ b/examples/device/hid_composite_freertos/CMakeLists.txt
@@ -29,9 +29,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
-
-# Add FreeRTOS for this example
-family_add_freertos(${PROJECT})
+# Configure compilation flags and libraries for the example with FreeRTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} freertos)
diff --git a/examples/device/hid_generic_inout/CMakeLists.txt b/examples/device/hid_generic_inout/CMakeLists.txt
index eb4c198d6..a01eb3456 100644
--- a/examples/device/hid_generic_inout/CMakeLists.txt
+++ b/examples/device/hid_generic_inout/CMakeLists.txt
@@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/hid_multiple_interface/CMakeLists.txt b/examples/device/hid_multiple_interface/CMakeLists.txt
index eb4c198d6..a01eb3456 100644
--- a/examples/device/hid_multiple_interface/CMakeLists.txt
+++ b/examples/device/hid_multiple_interface/CMakeLists.txt
@@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt
index 5b1a5547d..e51f14c02 100644
--- a/examples/device/midi_test/CMakeLists.txt
+++ b/examples/device/midi_test/CMakeLists.txt
@@ -26,6 +26,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt
index dc8d5512c..e69fead35 100644
--- a/examples/device/msc_dual_lun/CMakeLists.txt
+++ b/examples/device/msc_dual_lun/CMakeLists.txt
@@ -29,6 +29,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 2c21aa52b..1e34428fe 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -88,6 +88,6 @@ elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
 
 endif ()
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/uac2_headset/CMakeLists.txt b/examples/device/uac2_headset/CMakeLists.txt
index d142e9c04..e92a57148 100644
--- a/examples/device/uac2_headset/CMakeLists.txt
+++ b/examples/device/uac2_headset/CMakeLists.txt
@@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/usbtmc/CMakeLists.txt b/examples/device/usbtmc/CMakeLists.txt
index a6b22ab36..a63ca2d81 100644
--- a/examples/device/usbtmc/CMakeLists.txt
+++ b/examples/device/usbtmc/CMakeLists.txt
@@ -29,6 +29,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/video_capture/CMakeLists.txt b/examples/device/video_capture/CMakeLists.txt
index e0bd975c4..80dc39ca5 100644
--- a/examples/device/video_capture/CMakeLists.txt
+++ b/examples/device/video_capture/CMakeLists.txt
@@ -34,6 +34,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
 )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/webusb_serial/CMakeLists.txt b/examples/device/webusb_serial/CMakeLists.txt
index d142e9c04..e92a57148 100644
--- a/examples/device/webusb_serial/CMakeLists.txt
+++ b/examples/device/webusb_serial/CMakeLists.txt
@@ -28,6 +28,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
index c6d19a720..a6557c2d0 100644
--- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
+++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt
@@ -23,9 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_dual_usb_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_dual_usb_example(${PROJECT} noos)
 
 # due to warnings from Pico-PIO-USB
 target_compile_options(${PROJECT} PUBLIC
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index b6d8c9c89..95af48718 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -22,9 +22,9 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
 
 # Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
 if(FAMILY STREQUAL "rp2040")
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 68b52e274..3fdc832ab 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -25,9 +25,9 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
 
 # Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
 if(FAMILY STREQUAL "rp2040")
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index e27f83c53..d1d901b53 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -23,9 +23,9 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
 
 # Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
 if(FAMILY STREQUAL "rp2040")
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 327d1218a..99c797275 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -35,9 +35,9 @@ target_include_directories(${PROJECT} PUBLIC
   ${TOP}/lib/embedded-cli
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} noos)
 
 # Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
 if(FAMILY STREQUAL "rp2040")
diff --git a/examples/typec/power_delivery/CMakeLists.txt b/examples/typec/power_delivery/CMakeLists.txt
index 4ab8d5a65..012eff095 100644
--- a/examples/typec/power_delivery/CMakeLists.txt
+++ b/examples/typec/power_delivery/CMakeLists.txt
@@ -27,6 +27,6 @@ target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
   )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/examples/typec/power_delivery/src/tusb_config.h b/examples/typec/power_delivery/src/tusb_config.h
index deddcbfa4..f7cb3cc04 100644
--- a/examples/typec/power_delivery/src/tusb_config.h
+++ b/examples/typec/power_delivery/src/tusb_config.h
@@ -30,11 +30,6 @@
  extern "C" {
 #endif
 
-// special example that doesn't enable device or host stack
-// This can cause some TinyUSB API missing, this define hack to allow us to fill those API
-// to pass the compilation process
-#define tud_int_handler(x)
-
 //--------------------------------------------------------------------
 // COMMON CONFIGURATION
 //--------------------------------------------------------------------
@@ -54,6 +49,15 @@
 // Enable TYPEC stack
 #define CFG_TUC_ENABLED   1
 
+
+// special example that doesn't enable device or host stack
+// This can cause some TinyUSB API missing, this define hack to allow us to fill those API
+// to pass the compilation process
+#if CFG_TUD_ENABLED == 0
+#define tud_int_handler(x)
+#endif
+
+
 // CFG_TUSB_DEBUG is defined by compiler in DEBUG build
 // #define CFG_TUSB_DEBUG           0
 
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 93cab8723..781c67bf7 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -64,6 +64,8 @@ set(WARNING_FLAGS_GNU
 
 set(WARNINGS_FLAGS_IAR "")
 
+
+# Filter example based on only.txt and skip.txt
 function(family_filter RESULT DIR)
   get_filename_component(DIR ${DIR} ABSOLUTE BASE_DIR ${CMAKE_CURRENT_SOURCE_DIR})
 
@@ -142,112 +144,136 @@ function(family_initialize_project PROJECT DIR)
 endfunction()
 
 
-# Add segger rtt to example
-function(family_add_segger_rtt TARGET)
-  if (NOT TARGET segger_rtt)
-    add_library(segger_rtt STATIC
-      ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
-      )
-    target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
-  endif()
+#-------------------------------------------------------------
+# Common Target Configure
+# Most families use these settings except rp2040 and espressif
+#-------------------------------------------------------------
 
-  target_link_libraries(${TARGET} PUBLIC segger_rtt)
+# Add RTOS to example
+function(family_add_rtos TARGET RTOS)
+  if (RTOS STREQUAL "freertos")
+    # freertos config
+    if (NOT TARGET freertos_config)
+      add_library(freertos_config INTERFACE)
+      target_include_directories(freertos_config INTERFACE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig)
+      # add board definition to freertos_config mostly for SystemCoreClock
+      target_link_libraries(freertos_config INTERFACE board_${BOARD})
+    endif()
+
+    # freertos kernel
+    if (NOT TARGET freertos_kernel)
+      add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
+    endif ()
+
+    target_link_libraries(${TARGET} PUBLIC freertos_kernel)
+  endif ()
 endfunction()
 
-#------------------------------------
-# Main target configure
-#------------------------------------
 
 # Add common configuration to example
-function(family_configure_common TARGET)
+function(family_configure_common TARGET RTOS)
+  family_add_rtos(${TARGET} ${RTOS})
+
   # run size after build
   add_custom_command(TARGET ${TARGET} POST_BUILD
     COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${TARGET}>
     )
 
+  # Add warnings flags
   target_compile_options(${TARGET} PUBLIC ${WARNING_FLAGS_${CMAKE_C_COMPILER_ID}})
 
+  # Generate linker map file
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-    # Generate map file
-    target_link_options(${TARGET} PUBLIC
-      # link map
-      "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map"
-      )
+    target_link_options(${TARGET} PUBLIC "LINKER:-Map=$<TARGET_FILE:${TARGET}>.map")
   endif()
 
-  # LOGGER
-  if (DEFINED LOGGER)
-    target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER})
-    if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
-      family_add_segger_rtt(${TARGET})
-    endif ()
-  endif ()
-
-  # ETM Trace
+  # ETM Trace option
   if (TRACE_ETM STREQUAL "1")
     target_compile_definitions(${TARGET} PUBLIC TRACE_ETM)
   endif ()
 
-endfunction()
+  # LOGGER option
+  if (DEFINED LOGGER)
+    target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER})
 
-
-# configure an executable target to link to tinyusb in device mode, and add the board implementation
-function(family_configure_device_example TARGET)
-  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
-endfunction()
-
-
-# configure an executable target to link to tinyusb in host mode, and add the board implementation
-function(family_configure_host_example TARGET)
-  # default implementation is empty, the function should be redefined in the FAMILY/family.cmake
+    # Add segger rtt to example
+    if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt")
+      if (NOT TARGET segger_rtt)
+        add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c)
+        target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
+      endif()
+      target_link_libraries(${TARGET} PUBLIC segger_rtt)
+    endif ()
+  endif ()
 endfunction()
 
 
 # Add tinyusb to example
-function(family_add_tinyusb TARGET OPT_MCU)
+function(family_add_tinyusb TARGET OPT_MCU RTOS)
   # tinyusb target is built for each example since it depends on example's tusb_config.h
   set(TINYUSB_TARGET_PREFIX ${TARGET}-)
   add_library(${TARGET}-tinyusb_config INTERFACE)
 
+  # path to tusb_config.h
   target_include_directories(${TARGET}-tinyusb_config INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/src)
   target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_MCU=${OPT_MCU})
+
   if (DEFINED LOG)
     target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG})
   endif()
 
-  # tinyusb's CMakeList.txt
-  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
-endfunction()
-
-
-# Add freeRTOS support to example
-function(family_add_freertos TARGET)
-  # freeros config
-  if (NOT TARGET freertos_config)
-    add_library(freertos_config INTERFACE)
-    target_include_directories(freertos_config INTERFACE
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig
-      )
-    # add board definition to freertos_config mostly for SystemCoreClock
-    target_link_libraries(freertos_config INTERFACE board_${BOARD})
-  endif()
-
-  # freertos kernel should be generic as freertos_config however, CMAKE complains with missing variable
-  # such as CMAKE_C_COMPILE_OBJECT
-  if (NOT TARGET freertos_kernel)
-    add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel)
+  if (RTOS STREQUAL "freertos")
+    target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_OS=OPT_OS_FREERTOS)
   endif ()
 
-  # Add FreeRTOS option to tinyusb_config
-  target_compile_definitions(${TARGET}-tinyusb_config INTERFACE
-    CFG_TUSB_OS=OPT_OS_FREERTOS
-    )
-  # link tinyusb with freeRTOS kernel
-  target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel)
-  target_link_libraries(${TARGET} PUBLIC freertos_kernel)
+  # tinyusb's CMakeList.txt
+  add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb)
+
+  if (RTOS STREQUAL "freertos")
+    # link tinyusb with freeRTOS kernel
+    target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel)
+  endif ()
 endfunction()
 
 
+# Add bin/hex output
+function(family_add_bin_hex TARGET)
+  add_custom_command(TARGET ${TARGET} POST_BUILD
+    COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
+    COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
+    VERBATIM)
+endfunction()
+
+
+#----------------------------------
+# Example Target Configure (Default rule)
+# These function can be redefined in FAMILY/family.cmake
+#----------------------------------
+
+function(family_configure_example TARGET RTOS)
+  # empty function, should be redefined in FAMILY/family.cmake
+endfunction()
+
+# Configure device example with RTOS
+function(family_configure_device_example TARGET RTOS)
+  family_configure_example(${TARGET} ${RTOS})
+endfunction()
+
+
+# Configure host example with RTOS
+function(family_configure_host_example TARGET RTOS)
+  family_configure_example(${TARGET} ${RTOS})
+endfunction()
+
+
+# Configure host + device example with RTOS
+function(family_configure_dual_usb_example TARGET RTOS)
+  family_configure_example(${TARGET} ${RTOS})
+endfunction()
+
+#----------------------------------
+# RPI specific: refactor later
+#----------------------------------
 function(family_add_default_example_warnings TARGET)
   target_compile_options(${TARGET} PUBLIC
     -Wall
@@ -294,16 +320,6 @@ function(family_add_default_example_warnings TARGET)
   endif()
 endfunction()
 
-
-# Add bin/hex output
-function(family_add_bin_hex TARGET)
-  add_custom_command(TARGET ${TARGET} POST_BUILD
-    COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
-    COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${TARGET}> $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.hex
-    VERBATIM)
-endfunction()
-
-
 #----------------------------------
 # Flashing target
 #----------------------------------
@@ -374,6 +390,10 @@ function(family_flash_nxplink TARGET)
 endfunction()
 
 
+#----------------------------------
+# Family specific
+#----------------------------------
+
 # family specific: can override above functions
 include(${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
 
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index 4a9842cf9..aaedfc9d6 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -94,8 +94,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -115,7 +115,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX)
+  family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
     ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -130,16 +130,3 @@ function(family_configure_example TARGET)
   family_flash_jlink(${TARGET})
   #family_flash_nxplink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake
index 5d4165185..4df3d1ed1 100644
--- a/hw/bsp/kinetis_kl/family.cmake
+++ b/hw/bsp/kinetis_kl/family.cmake
@@ -78,8 +78,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -99,7 +99,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL)
+  family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c
     ${TOP}/src/portable/nxp/khci/hcd_khci.c
@@ -113,16 +113,3 @@ function(family_configure_example TARGET)
   family_flash_jlink(${TARGET})
   #family_flash_nxplink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index 4e6e2b56d..da71a0e5d 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -70,8 +70,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -91,7 +91,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX)
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
     ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -106,16 +106,3 @@ function(family_configure_example TARGET)
   family_flash_jlink(${TARGET})
   #family_flash_nxplink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index e443f47d3..dfd08a732 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -87,8 +87,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -117,7 +117,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX)
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
     )
@@ -131,16 +131,3 @@ function(family_configure_example TARGET)
   #family_flash_nxplink(${TARGET})
   #family_flash_pyocd(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index 83f44222b..f548ac4f3 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -79,8 +79,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -100,7 +100,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_MCXN9)
+  family_add_tinyusb(${TARGET} OPT_MCU_MCXN9 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
     ${TOP}/src/portable/chipidea/$<IF:${PORT},ci_hs/dcd_ci_hs.c,ci_fs/dcd_ci_fs.c>
@@ -115,16 +115,3 @@ function(family_configure_example TARGET)
   #family_flash_nxplink(${TARGET})
   #family_flash_pyocd(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 825380d0b..30fd41d7b 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -97,8 +97,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -118,7 +118,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_NRF5X)
+  family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
     )
@@ -132,16 +132,3 @@ function(family_configure_example TARGET)
   # Flashing
   family_flash_jlink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 2d37f8be9..b986b3ebb 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -11,6 +11,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake)
 
 # include basic family CMake functionality
 set(FAMILY_MCUS RP2040)
+set(JLINK_DEVICE rp2040_m0_0)
 
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
@@ -143,12 +144,23 @@ endif()
 # Functions
 #------------------------------------
 
-function(family_configure_target TARGET)
+function(family_configure_target TARGET RTOS)
+	if (RTOS STREQUAL noos OR RTOS STREQUAL "")
+		set(RTOS_SUFFIX "")
+	else()
+		set(RTOS_SUFFIX _${RTOS})
+	endif()
+	# export RTOS_SUFFIX to parent scope
+	set(RTOS_SUFFIX ${RTOS_SUFFIX} PARENT_SCOPE)
+
 	pico_add_extra_outputs(${TARGET})
 	pico_enable_stdio_uart(${TARGET} 1)
-	target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board tinyusb_additions)
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib pico_bootsel_via_double_reset tinyusb_board${RTOS_SUFFIX} tinyusb_additions)
+
+	family_flash_jlink(${TARGET})
 endfunction()
 
+
 function(rp2040_family_configure_example_warnings TARGET)
 	if (NOT PICO_TINYUSB_NO_EXAMPLE_WARNINGS)
 		family_add_default_example_warnings(${TARGET})
@@ -159,19 +171,22 @@ function(rp2040_family_configure_example_warnings TARGET)
 	suppress_tinyusb_warnings()
 endfunction()
 
-function(family_configure_device_example TARGET)
-	family_configure_target(${TARGET})
-	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device)
+
+function(family_configure_device_example TARGET RTOS)
+	family_configure_target(${TARGET} ${RTOS})
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device${RTOS_SUFFIX})
 	rp2040_family_configure_example_warnings(${TARGET})
 endfunction()
 
+
 function(family_add_pico_pio_usb TARGET)
 	target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb)
 endfunction()
 
-function(family_configure_host_example TARGET)
-	family_configure_target(${TARGET})
-	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host)
+
+function(family_configure_host_example TARGET RTOS)
+	family_configure_target(${TARGET} ${RTOS})
+	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_host${RTOS_SUFFIX})
 	rp2040_family_configure_example_warnings(${TARGET})
 
 	# For rp2040 enable pico-pio-usb
@@ -183,13 +198,15 @@ function(family_configure_host_example TARGET)
 	endif()
 endfunction()
 
-function(family_configure_dual_usb_example TARGET)
-	family_configure_target(${TARGET})
+
+function(family_configure_dual_usb_example TARGET RTOS)
+	family_configure_target(${TARGET} ${RTOS})
 	# require tinyusb_pico_pio_usb
 	target_link_libraries(${TARGET} PUBLIC pico_stdlib tinyusb_device tinyusb_host tinyusb_pico_pio_usb )
 	rp2040_family_configure_example_warnings(${TARGET})
 endfunction()
 
+
 function(check_and_add_pico_pio_usb_support)
 	# check for pico_generate_pio_header (as depending on environment we may be called before SDK is
 	# initialized in which case it isn't available yet), and only do the initialization once
@@ -243,6 +260,7 @@ endfunction()
 # when included by the SDK itself)
 check_and_add_pico_pio_usb_support()
 
+
 function(family_initialize_project PROJECT DIR)
 	# call the original version of this function from family_common.cmake
 	_family_initialize_project(${PROJECT} ${DIR})
@@ -253,6 +271,7 @@ function(family_initialize_project PROJECT DIR)
 	check_and_add_pico_pio_usb_support()
 endfunction()
 
+
 # This method must be called from the project scope to suppress known warnings in TinyUSB source files
 function(suppress_tinyusb_warnings)
 	# some of these are pretty silly warnings only occurring in some older GCC versions 9 or prior
@@ -327,7 +346,3 @@ function(suppress_tinyusb_warnings)
 				COMPILE_FLAGS "-Wno-cast-qual")
 	endif()
 endfunction()
-
-# rp2040 does not support freeRTOS example yet
-function(family_add_freertos TARGET)
-endfunction()
diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake
index ecf6a8424..73f43de82 100644
--- a/hw/bsp/stm32f0/family.cmake
+++ b/hw/bsp/stm32f0/family.cmake
@@ -84,8 +84,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -105,7 +105,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_STM32F0)
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F0 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
     )
@@ -118,16 +118,3 @@ function(family_configure_example TARGET)
   family_flash_stlink(${TARGET})
   #family_flash_jlink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake
index ab46c9872..efe41bc1b 100644
--- a/hw/bsp/stm32f1/family.cmake
+++ b/hw/bsp/stm32f1/family.cmake
@@ -81,8 +81,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -102,7 +102,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_STM32F1)
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F1 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
     )
@@ -115,16 +115,3 @@ function(family_configure_example TARGET)
   family_flash_stlink(${TARGET})
   #family_flash_jlink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake
index 3b6ba1a15..30bde9b0d 100644
--- a/hw/bsp/stm32f7/family.cmake
+++ b/hw/bsp/stm32f7/family.cmake
@@ -86,8 +86,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -107,7 +107,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_STM32F7)
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F7 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
     )
@@ -120,16 +120,3 @@ function(family_configure_example TARGET)
   family_flash_stlink(${TARGET})
   family_flash_jlink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index fa93566bf..f7b665090 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -84,8 +84,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -105,7 +105,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_STM32G0)
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32G0 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
     ${TOP}/src/portable/st/typec/typec_stm32.c
@@ -119,16 +119,3 @@ function(family_configure_example TARGET)
   family_flash_stlink(${TARGET})
   #family_flash_jlink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index c89993f6d..3c7633d64 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -84,8 +84,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -105,7 +105,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_STM32G4)
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32G4 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
     ${TOP}/src/portable/st/typec/typec_stm32.c
@@ -119,16 +119,3 @@ function(family_configure_example TARGET)
   family_flash_stlink(${TARGET})
   family_flash_jlink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake
index f3705edb4..1a8c4354c 100644
--- a/hw/bsp/stm32h7/family.cmake
+++ b/hw/bsp/stm32h7/family.cmake
@@ -89,8 +89,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -110,7 +110,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_STM32H7)
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32H7 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
     )
@@ -123,16 +123,3 @@ function(family_configure_example TARGET)
   family_flash_stlink(${TARGET})
   family_flash_jlink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake
index 83c51c9bf..da017cdde 100644
--- a/hw/bsp/stm32l4/family.cmake
+++ b/hw/bsp/stm32l4/family.cmake
@@ -86,8 +86,8 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
 
   # Board target
   add_board_target(board_${BOARD})
@@ -107,7 +107,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS})
+  family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS} ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
     ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
@@ -121,16 +121,3 @@ function(family_configure_example TARGET)
   family_flash_stlink(${TARGET})
   family_flash_jlink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h
index 5ab56e145..6f07bdd53 100644
--- a/src/common/tusb_compiler.h
+++ b/src/common/tusb_compiler.h
@@ -128,7 +128,9 @@
   #define TU_ATTR_SECTION(sec_name)     __attribute__ ((section(#sec_name)))
   #define TU_ATTR_PACKED                __attribute__ ((packed))
   #define TU_ATTR_WEAK                  __attribute__ ((weak))
-  #define TU_ATTR_ALWAYS_INLINE         __attribute__ ((always_inline))
+  #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug
+    #define TU_ATTR_ALWAYS_INLINE       __attribute__ ((always_inline))
+  #endif
   #define TU_ATTR_DEPRECATED(mess)      __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))             // Function/Variable is meant to be used
@@ -205,7 +207,9 @@
   #define TU_ATTR_SECTION(sec_name)     __attribute__ ((section(#sec_name)))
   #define TU_ATTR_PACKED                __attribute__ ((packed))
   #define TU_ATTR_WEAK                  __attribute__ ((weak))
-  #define TU_ATTR_ALWAYS_INLINE         __attribute__ ((always_inline))
+  #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug
+    #define TU_ATTR_ALWAYS_INLINE         __attribute__ ((always_inline))
+  #endif
   #define TU_ATTR_DEPRECATED(mess)      __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
   #define TU_ATTR_UNUSED                __attribute__ ((unused))           // Function/Variable is meant to be possibly unused
   #define TU_ATTR_USED                  __attribute__ ((used))             // Function/Variable is meant to be used
diff --git a/test/fuzz/device/cdc/CMakeLists.txt b/test/fuzz/device/cdc/CMakeLists.txt
index 8e4db9d29..c60f292b9 100644
--- a/test/fuzz/device/cdc/CMakeLists.txt
+++ b/test/fuzz/device/cdc/CMakeLists.txt
@@ -14,16 +14,16 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/test/fuzz/device/msc/CMakeLists.txt b/test/fuzz/device/msc/CMakeLists.txt
index 8e4db9d29..8bff217cb 100644
--- a/test/fuzz/device/msc/CMakeLists.txt
+++ b/test/fuzz/device/msc/CMakeLists.txt
@@ -24,6 +24,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)
diff --git a/test/fuzz/device/net/CMakeLists.txt b/test/fuzz/device/net/CMakeLists.txt
index 8e4db9d29..8bff217cb 100644
--- a/test/fuzz/device/net/CMakeLists.txt
+++ b/test/fuzz/device/net/CMakeLists.txt
@@ -24,6 +24,6 @@ target_include_directories(${PROJECT} PUBLIC
         ${CMAKE_CURRENT_SOURCE_DIR}/src
         )
 
-# Configure compilation flags and libraries for the example... see the corresponding function
-# in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_device_example(${PROJECT} noos)

From 98fb10a724a33b545990a8593f60b5f10f030f5d Mon Sep 17 00:00:00 2001
From: Devin Auclair <devinauclair@gmail.com>
Date: Wed, 28 Jun 2023 14:03:18 -0400
Subject: [PATCH 1851/2085] Fix minor spelling

---
 src/class/msc/msc.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/class/msc/msc.h b/src/class/msc/msc.h
index 7f25a29ba..bbfd35a43 100644
--- a/src/class/msc/msc.h
+++ b/src/class/msc/msc.h
@@ -53,7 +53,7 @@ enum {
 };
 
 /// \brief MassStorage Protocol.
-/// \details CBI only approved to use with full-speed floopy disk & should not used with highspeed or device other than floopy
+/// \details CBI only approved to use with full-speed floppy disk & should not used with highspeed or device other than floppy
 typedef enum
 {
   MSC_PROTOCOL_CBI              = 0 ,  ///< Control/Bulk/Interrupt protocol (with command completion interrupt)
@@ -97,7 +97,7 @@ typedef struct TU_ATTR_PACKED
 {
   uint32_t signature    ; ///< Signature that helps identify this data packet as a CSW. The signature field shall contain the value 53425355h (little endian), indicating CSW.
   uint32_t tag          ; ///< The device shall set this field to the value received in the dCBWTag of the associated CBW.
-  uint32_t data_residue ; ///< For Data-Out the device shall report in the dCSWDataResiduethe difference between the amount of data expected as stated in the dCBWDataTransferLength, and the actual amount of data processed by the device. For Data-In the device shall report in the dCSWDataResiduethe difference between the amount of data expected as stated in the dCBWDataTransferLengthand the actual amount of relevant data sent by the device
+  uint32_t data_residue ; ///< For Data-Out the device shall report in the dCSWDataResidue the difference between the amount of data expected as stated in the dCBWDataTransferLength, and the actual amount of data processed by the device. For Data-In the device shall report in the dCSWDataResiduethe difference between the amount of data expected as stated in the dCBWDataTransferLengthand the actual amount of relevant data sent by the device
   uint8_t  status       ; ///< indicates the success or failure of the command. Values from \ref msc_csw_status_t
 }msc_csw_t;
 
@@ -120,14 +120,14 @@ typedef enum
   SCSI_CMD_REQUEST_SENSE                = 0x03, ///< The SCSI Request Sense command is part of the SCSI computer protocol standard. This command is used to obtain sense data -- status/error information -- from a target device.
   SCSI_CMD_READ_FORMAT_CAPACITY         = 0x23, ///< The command allows the Host to request a list of the possible format capacities for an installed writable media. This command also has the capability to report the writable capacity for a media when it is installed
   SCSI_CMD_READ_10                      = 0x28, ///< The READ (10) command requests that the device server read the specified logical block(s) and transfer them to the data-in buffer.
-  SCSI_CMD_WRITE_10                     = 0x2A, ///< The WRITE (10) command requests thatthe device server transfer the specified logical block(s) from the data-out buffer and write them.
+  SCSI_CMD_WRITE_10                     = 0x2A, ///< The WRITE (10) command requests that the device server transfer the specified logical block(s) from the data-out buffer and write them.
 }scsi_cmd_type_t;
 
 /// SCSI Sense Key
 typedef enum
 {
   SCSI_SENSE_NONE            = 0x00, ///< no specific Sense Key. This would be the case for a successful command
-  SCSI_SENSE_RECOVERED_ERROR = 0x01, ///< ndicates the last command completed successfully with some recovery action performed by the disc drive.
+  SCSI_SENSE_RECOVERED_ERROR = 0x01, ///< Indicates the last command completed successfully with some recovery action performed by the disc drive.
   SCSI_SENSE_NOT_READY       = 0x02, ///< Indicates the logical unit addressed cannot be accessed.
   SCSI_SENSE_MEDIUM_ERROR    = 0x03, ///< Indicates the command terminated with a non-recovered error condition.
   SCSI_SENSE_HARDWARE_ERROR  = 0x04, ///< Indicates the disc drive detected a nonrecoverable hardware failure while performing the command or during a self test.
@@ -138,7 +138,7 @@ typedef enum
   SCSI_SENSE_ABORTED_COMMAND = 0x0b, ///< Indicates the disc drive aborted the command.
   SCSI_SENSE_EQUAL           = 0x0c, ///< Indicates a SEARCH DATA command has satisfied an equal comparison.
   SCSI_SENSE_VOLUME_OVERFLOW = 0x0d, ///< Indicates a buffered peripheral device has reached the end of medium partition and data remains in the buffer that has not been written to the medium.
-  SCSI_SENSE_MISCOMPARE      = 0x0e  ///< ndicates that the source data did not match the data read from the medium.
+  SCSI_SENSE_MISCOMPARE      = 0x0e  ///< Indicates that the source data did not match the data read from the medium.
 }scsi_sense_key_type_t;
 
 //--------------------------------------------------------------------+

From 11fba59319d81fb9502fbf399abb4fe27cf3fa29 Mon Sep 17 00:00:00 2001
From: Dave Nadler <drn@nadler.com>
Date: Wed, 28 Jun 2023 17:25:22 -0400
Subject: [PATCH 1852/2085] Name queues for easier FreeRTOS debugging with
 task- and queue-aware debuggers

---
 src/device/usbd.c        | 4 ++--
 src/host/usbh.c          | 4 ++--
 src/osal/osal_freertos.h | 5 +++--
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 44c2530ce..b6c679b22 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -279,7 +279,7 @@ tu_static uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // usbd_int_set() is used as mutex in OS NONE config
-OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
+OSAL_QUEUE_DEF(usbd_int_set, usbd_events, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
 tu_static osal_queue_t _usbd_q;
 
 // Mutex for claiming endpoint
@@ -410,7 +410,7 @@ bool tud_init (uint8_t rhport)
 #endif
 
   // Init device queue & task
-  _usbd_q = osal_queue_create(&_usbd_qdef);
+  _usbd_q = osal_queue_create(&usbd_events);
   TU_ASSERT(_usbd_q);
 
   // Get application driver if available
diff --git a/src/host/usbh.c b/src/host/usbh.c
index f3e9d3858..987ff7a6e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -219,7 +219,7 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES];
 
 // Event queue
 // usbh_int_set is used as mutex in OS NONE config
-OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
+OSAL_QUEUE_DEF(usbh_int_set, usbh_events, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
 
 CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN
@@ -330,7 +330,7 @@ bool tuh_init(uint8_t controller_id)
   TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t));
 
   // Event queue
-  _usbh_q = osal_queue_create( &_usbh_qdef );
+  _usbh_q = osal_queue_create( &usbh_events );
   TU_ASSERT(_usbh_q != NULL);
 
 #if OSAL_MUTEX_REQUIRED
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 0b1b11589..e83277eb3 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -56,7 +56,7 @@ typedef SemaphoreHandle_t osal_mutex_t;
 // _int_set is not used with an RTOS
 #define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
   static _type _name##_##buf[_depth];\
-  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
+  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .pQueueName = #_name };
 
 typedef struct
 {
@@ -66,6 +66,7 @@ typedef struct
 #if configSUPPORT_STATIC_ALLOCATION
   StaticQueue_t sq;
 #endif
+  const char* pQueueName;
 }osal_queue_def_t;
 
 typedef QueueHandle_t osal_queue_t;
@@ -176,7 +177,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de
     q = xQueueCreate(qdef->depth, qdef->item_sz);
   #endif
   #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
-    vQueueAddToRegistry(q, "tinyUSB");
+    vQueueAddToRegistry(q, qdef->pQueueName);
   #endif
   return q;
 }

From 6284f2d72287396a0df153a0a7bd192c4e3847a7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 29 Jun 2023 18:58:33 +0700
Subject: [PATCH 1853/2085] add hcd_frame_number() for pio-usb host

---
 .gitmodules                                    | 0
 hw/bsp/rp2040/board.h                          | 4 +++-
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 2 +-
 tools/get_deps.py                              | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)
 delete mode 100644 .gitmodules

diff --git a/.gitmodules b/.gitmodules
deleted file mode 100644
index e69de29bb..000000000
diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index ccad00c4a..934e1c7ae 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -49,7 +49,10 @@
 #define UART_RX_PIN           PICO_DEFAULT_UART_RX_PIN
 #endif
 
+//--------------------------------------------------------------------+
 // PIO_USB
+// default to pin on Adafruit Feather rp2040 USB Host or Tester if defined
+//--------------------------------------------------------------------+
 
 // #define USE_ADAFRUIT_RP2040_TESTER
 #ifdef USE_ADAFRUIT_RP2040_TESTER
@@ -57,7 +60,6 @@
 #define PICO_DEFAULT_PIO_USB_VBUSEN_PIN   22
 #endif
 
-// following default to pin on Adafruit Feather rp2040 USB Host
 #ifndef PICO_DEFAULT_PIO_USB_DP_PIN
 #define PICO_DEFAULT_PIO_USB_DP_PIN       16
 #endif
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 58b153ac3..264af2e7a 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -105,7 +105,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 uint32_t hcd_frame_number(uint8_t rhport)
 {
   (void) rhport;
-  return 0;
+  return pio_usb_host_get_frame_number();
 }
 
 void hcd_int_enable(uint8_t rhport)
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 34e2f30a3..9b89c5e4c 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -54,7 +54,7 @@ deps_optional = {
                             '950819b7de9b32f92c3edf396bc5ffb8d66e7009',
                             'kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'],
     'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
-                                         'c3715ce94b6f6391856de56081d4d9b3e98fa93d',
+                                         '58879cfa0eca5725d8db6443ec17f8896a321042',
                                          'rp2040'],
     'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git',
                            '8dc14709f2a6518b43f71efad70d900b7718d9f1',

From f5d0510064bd2a0ffd040697de1fac707fa70069 Mon Sep 17 00:00:00 2001
From: Ha Thach <thach@tinyusb.org>
Date: Thu, 29 Jun 2023 22:57:58 +0700
Subject: [PATCH 1854/2085] Update build badge

---
 README.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.rst b/README.rst
index 2c9119fef..78e8d87b0 100644
--- a/README.rst
+++ b/README.rst
@@ -138,7 +138,7 @@ Please make sure you understand all the license term for files you use
 in your project.
 
 
-.. |Build Status| image:: https://github.com/hathach/tinyusb/workflows/Build/badge.svg
+.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/cmake_arm.yml/badge.svg
    :target: https://github.com/hathach/tinyusb/actions
 .. |Documentation Status| image:: https://readthedocs.org/projects/tinyusb/badge/?version=latest
    :target: https://docs.tinyusb.org/en/latest/?badge=latest

From 3cb4d738996e0856ab42654e421fd766652519bd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 30 Jun 2023 14:52:04 +0700
Subject: [PATCH 1855/2085] clean up ra makefile

---
 hw/bsp/ra/boards/ra4m1_ek/board.mk |  9 +++++-
 hw/bsp/ra/boards/ra4m3_ek/board.mk |  9 +++++-
 hw/bsp/ra/family.mk                | 47 +++++++++++++-----------------
 tools/make/cpu/cortex-m0.mk        |  2 +-
 tools/make/cpu/cortex-m0plus.mk    |  2 +-
 tools/make/cpu/cortex-m3.mk        |  2 +-
 tools/make/cpu/cortex-m33.mk       |  2 +-
 tools/make/cpu/cortex-m4.mk        |  2 +-
 tools/make/cpu/cortex-m7.mk        |  2 +-
 9 files changed, 43 insertions(+), 34 deletions(-)

diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.mk b/hw/bsp/ra/boards/ra4m1_ek/board.mk
index 5c193513d..eae68f87d 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.mk
@@ -1,8 +1,15 @@
 CPU_CORE = cortex-m4
+MCU_VARIANT = ra4m1
 
-FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m1
 FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m1_ek
 
+SRC_C += \
+	$(FSP_BOARD_DIR)/board_init.c \
+	$(FSP_BOARD_DIR)/board_leds.c \
+
+INC += \
+	$(TOP)/$(FSP_BOARD_DIR)
+
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/ra4m1_ek.ld
 
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.mk b/hw/bsp/ra/boards/ra4m3_ek/board.mk
index 264f29c1a..4ca1d365e 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.mk
@@ -1,8 +1,15 @@
 CPU_CORE = cortex-m33
+MCU_VARIANT = ra4m3
 
-FSP_MCU_DIR = hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/ra4m3
 FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m3_ek
 
+SRC_C += \
+	$(FSP_BOARD_DIR)/board_init.c \
+	$(FSP_BOARD_DIR)/board_leds.c \
+
+INC += \
+	$(TOP)/$(FSP_BOARD_DIR)
+
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/ra4m3_ek.ld
 
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index b65c95191..103d3cfa6 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -1,5 +1,6 @@
 DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
 
+FSP_RA = hw/mcu/renesas/fsp/ra/fsp
 include $(TOP)/$(BOARD_PATH)/board.mk
 
 CFLAGS += \
@@ -10,44 +11,38 @@ CFLAGS += \
 	-Wno-error=cast-qual \
 	-Wno-error=unused-but-set-variable \
 	-Wno-error=unused-variable \
-	-mthumb \
 	-nostdlib \
 	-nostartfiles \
-	-ffunction-sections \
-	-fdata-sections \
 	-ffreestanding
 
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_clocks.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_common.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_delay.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_group_irq.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_guard.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_io.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_irq.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_register_protection.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_sbrk.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/bsp/mcu/all/bsp_security.c \
-	hw/mcu/renesas/fsp/ra/fsp/src/r_ioport/r_ioport.c \
-	$(FSP_BOARD_DIR)/board_init.c \
-	$(FSP_BOARD_DIR)/board_leds.c
+	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
+	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_common.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_delay.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_group_irq.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_guard.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_io.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_irq.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_register_protection.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_rom_registers.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_sbrk.c \
+	$(FSP_RA)/src/bsp/mcu/all/bsp_security.c \
+	$(FSP_RA)/src/r_ioport/r_ioport.c \
 
 INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include \
+	$(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(BOARD_PATH)/fsp_cfg \
-	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc \
-	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/api \
-	$(TOP)/hw/mcu/renesas/fsp/ra/fsp/inc/instances \
-	$(TOP)/$(FSP_MCU_DIR) \
-	$(TOP)/$(FSP_BOARD_DIR)
+	$(TOP)/$(FSP_RA)/inc \
+	$(TOP)/$(FSP_RA)/inc/api \
+	$(TOP)/$(FSP_RA)/inc/instances \
+	$(TOP)/$(FSP_RA)/src/bsp/mcu/$(MCU_VARIANT) \
 
 # For freeRTOS port source
 # hack to use the port provided by renesas
-FREERTOS_PORTABLE_SRC = hw/mcu/renesas/fsp/ra/fsp/src/rm_freertos_port
+FREERTOS_PORTABLE_SRC = $(FSP_RA)/src/rm_freertos_port
diff --git a/tools/make/cpu/cortex-m0.mk b/tools/make/cpu/cortex-m0.mk
index c264802c8..feb0f395b 100644
--- a/tools/make/cpu/cortex-m0.mk
+++ b/tools/make/cpu/cortex-m0.mk
@@ -11,4 +11,4 @@ else ifeq ($(TOOLCHAIN),iar)
 endif
 
 # For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/tools/make/cpu/cortex-m0plus.mk b/tools/make/cpu/cortex-m0plus.mk
index 626f7156e..b416b7a4a 100644
--- a/tools/make/cpu/cortex-m0plus.mk
+++ b/tools/make/cpu/cortex-m0plus.mk
@@ -11,4 +11,4 @@ else ifeq ($(TOOLCHAIN),iar)
 endif
 
 # For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM0
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM0
diff --git a/tools/make/cpu/cortex-m3.mk b/tools/make/cpu/cortex-m3.mk
index c81cbace6..7a34b9e04 100644
--- a/tools/make/cpu/cortex-m3.mk
+++ b/tools/make/cpu/cortex-m3.mk
@@ -14,4 +14,4 @@ else ifeq ($(TOOLCHAIN),iar)
 endif
 
 # For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM3
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM3
diff --git a/tools/make/cpu/cortex-m33.mk b/tools/make/cpu/cortex-m33.mk
index e53f5c2b1..fe5b7b380 100644
--- a/tools/make/cpu/cortex-m33.mk
+++ b/tools/make/cpu/cortex-m33.mk
@@ -16,4 +16,4 @@ else ifeq ($(TOOLCHAIN),iar)
 
 endif
 
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM33_NTZ/non_secure
diff --git a/tools/make/cpu/cortex-m4.mk b/tools/make/cpu/cortex-m4.mk
index fabe05632..d8776b5d8 100644
--- a/tools/make/cpu/cortex-m4.mk
+++ b/tools/make/cpu/cortex-m4.mk
@@ -10,4 +10,4 @@ else ifeq ($(TOOLCHAIN),iar)
   ASFLAGS += --cpu cortex-m4 --fpu VFPv4
 endif
 
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
diff --git a/tools/make/cpu/cortex-m7.mk b/tools/make/cpu/cortex-m7.mk
index 0e53cbe9c..0e3461787 100644
--- a/tools/make/cpu/cortex-m7.mk
+++ b/tools/make/cpu/cortex-m7.mk
@@ -16,4 +16,4 @@ else ifeq ($(TOOLCHAIN),iar)
 
 endif
 
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM7/r0p1

From 48738df489ac583ea8a999d15222f1a570f735f7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 30 Jun 2023 16:05:59 +0700
Subject: [PATCH 1856/2085] move LTO checked to family_support.cmake

---
 hw/bsp/family_support.cmake    | 7 +++++++
 hw/bsp/imxrt/family.cmake      | 7 -------
 hw/bsp/kinetis_kl/family.cmake | 7 -------
 hw/bsp/lpc18/family.cmake      | 7 -------
 hw/bsp/mcx/family.cmake        | 7 -------
 hw/bsp/nrf/family.cmake        | 8 --------
 hw/bsp/stm32f0/family.cmake    | 7 -------
 hw/bsp/stm32f1/family.cmake    | 7 -------
 hw/bsp/stm32f7/family.cmake    | 7 -------
 hw/bsp/stm32g0/family.cmake    | 7 -------
 hw/bsp/stm32g4/family.cmake    | 7 -------
 hw/bsp/stm32h7/family.cmake    | 7 -------
 hw/bsp/stm32l4/family.cmake    | 7 -------
 13 files changed, 7 insertions(+), 85 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 781c67bf7..b2e61a824 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -36,6 +36,13 @@ if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
   message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
 endif()
 
+# enable LTO if supported
+include(CheckIPOSupported)
+check_ipo_supported(RESULT IPO_SUPPORTED)
+if (IPO_SUPPORTED)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+endif ()
+
 set(WARNING_FLAGS_GNU
   -Wall
   -Wextra
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index aaedfc9d6..a8841f8ce 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -16,13 +16,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake
index 4df3d1ed1..793ef1783 100644
--- a/hw/bsp/kinetis_kl/family.cmake
+++ b/hw/bsp/kinetis_kl/family.cmake
@@ -16,13 +16,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake
index da71a0e5d..74a794bde 100644
--- a/hw/bsp/lpc18/family.cmake
+++ b/hw/bsp/lpc18/family.cmake
@@ -15,13 +15,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake
index f548ac4f3..b3a4a846e 100644
--- a/hw/bsp/mcx/family.cmake
+++ b/hw/bsp/mcx/family.cmake
@@ -16,13 +16,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS MCXN9 CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 30fd41d7b..2b13249f4 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -23,12 +23,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS NRF5X CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
 
 #------------------------------------
 # BOARD_TARGET
@@ -124,8 +118,6 @@ function(family_configure_example TARGET RTOS)
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
-
-
   # Link dependencies
   target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
 
diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake
index 73f43de82..e0fc705f8 100644
--- a/hw/bsp/stm32f0/family.cmake
+++ b/hw/bsp/stm32f0/family.cmake
@@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32F0 CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake
index efe41bc1b..53af35862 100644
--- a/hw/bsp/stm32f1/family.cmake
+++ b/hw/bsp/stm32f1/family.cmake
@@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32F1 CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake
index 30bde9b0d..48dd9c7ca 100644
--- a/hw/bsp/stm32f7/family.cmake
+++ b/hw/bsp/stm32f7/family.cmake
@@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32F7 CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index f7b665090..b787363ed 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32G0 CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index 3c7633d64..675a96c74 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32G4 CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake
index 1a8c4354c..c08857a50 100644
--- a/hw/bsp/stm32h7/family.cmake
+++ b/hw/bsp/stm32h7/family.cmake
@@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32H7 CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake
index da017cdde..87f87004b 100644
--- a/hw/bsp/stm32l4/family.cmake
+++ b/hw/bsp/stm32l4/family.cmake
@@ -20,13 +20,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32L4 CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET

From 14d69e46be7b875fef534d70e619764df63f023d Mon Sep 17 00:00:00 2001
From: mndza <diego.hdmp@gmail.com>
Date: Tue, 27 Jun 2023 12:05:59 +0200
Subject: [PATCH 1857/2085] Update support for Cynthion boards

- Rename LUNA to Cynthion
- Add support for newer revisions (>=0.6)
- Bootloader (saturn-v) default size is now 2K
---
 docs/reference/supported.rst                  |  2 +-
 .../boards/{luna_d11 => cynthion_d11}/board.h |  6 +++++
 hw/bsp/samd11/boards/cynthion_d11/board.mk    | 22 +++++++++++++++++++
 .../samd11d14am_flash.ld                      |  2 +-
 hw/bsp/samd11/boards/luna_d11/board.mk        | 11 ----------
 hw/bsp/samd11/boards/samd11_xplained/board.h  |  1 +
 hw/bsp/samd11/family.c                        |  2 +-
 .../boards/{luna_d21 => cynthion_d21}/board.h |  0
 .../{luna_d21 => cynthion_d21}/board.mk       |  6 +++++
 .../samd21g18a_flash.ld                       |  2 +-
 10 files changed, 39 insertions(+), 15 deletions(-)
 rename hw/bsp/samd11/boards/{luna_d11 => cynthion_d11}/board.h (87%)
 create mode 100644 hw/bsp/samd11/boards/cynthion_d11/board.mk
 rename hw/bsp/samd11/boards/{luna_d11 => cynthion_d11}/samd11d14am_flash.ld (97%)
 delete mode 100644 hw/bsp/samd11/boards/luna_d11/board.mk
 rename hw/bsp/samd21/boards/{luna_d21 => cynthion_d21}/board.h (100%)
 rename hw/bsp/samd21/boards/{luna_d21 => cynthion_d21}/board.mk (60%)
 rename hw/bsp/samd21/boards/{luna_d21 => cynthion_d21}/samd21g18a_flash.ld (97%)

diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst
index a5d055893..aed64782c 100644
--- a/docs/reference/supported.rst
+++ b/docs/reference/supported.rst
@@ -175,7 +175,7 @@ SAMD11 & SAMD21
 -  `Adafruit Feather M0 Express <https://www.adafruit.com/product/3403>`__
 -  `Adafruit ItsyBitsy M0 Express <https://www.adafruit.com/product/3727>`__
 -  `Adafruit Metro M0 Express <https://www.adafruit.com/product/3505>`__
--  `Great Scott Gadgets LUNA <https://greatscottgadgets.com/luna/>`__
+-  `Great Scott Gadgets Cynthion <https://greatscottgadgets.com/cynthion/>`__
 -  `Microchip SAMD11 Xplained Pro <https://www.microchip.com/developmenttools/ProductDetails/atsamd11-xpro>`__
 -  `Microchip SAMD21 Xplained Pro <https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMD21-XPRO>`__
 -  `Seeeduino Xiao <https://www.seeedstudio.com/Seeeduino-XIAO-Arduino-Microcontroller-SAMD21-Cortex-M0+-p-4426.html>`__
diff --git a/hw/bsp/samd11/boards/luna_d11/board.h b/hw/bsp/samd11/boards/cynthion_d11/board.h
similarity index 87%
rename from hw/bsp/samd11/boards/luna_d11/board.h
rename to hw/bsp/samd11/boards/cynthion_d11/board.h
index 1bda92934..b13c8eeea 100644
--- a/hw/bsp/samd11/boards/luna_d11/board.h
+++ b/hw/bsp/samd11/boards/cynthion_d11/board.h
@@ -36,7 +36,13 @@
 #define LED_STATE_ON          0
 
 // Button
+#if ((_BOARD_REVISION_MAJOR_ == 0) && (_BOARD_REVISION_MINOR_ < 6))
 #define BUTTON_PIN            PIN_PA16 // pin PB22
+#define BUTTON_PULL_MODE      GPIO_PULL_UP
+#else
+#define BUTTON_PIN            PIN_PA02
+#define BUTTON_PULL_MODE      GPIO_PULL_OFF
+#endif
 #define BUTTON_STATE_ACTIVE   0
 
 #ifdef __cplusplus
diff --git a/hw/bsp/samd11/boards/cynthion_d11/board.mk b/hw/bsp/samd11/boards/cynthion_d11/board.mk
new file mode 100644
index 000000000..d36c91970
--- /dev/null
+++ b/hw/bsp/samd11/boards/cynthion_d11/board.mk
@@ -0,0 +1,22 @@
+BOARD_REVISION_MAJOR ?= 1
+BOARD_REVISION_MINOR ?= 0
+
+CFLAGS += -D__SAMD11D14AM__ \
+	-D_BOARD_REVISION_MAJOR_=$(BOARD_REVISION_MAJOR) \
+	-D_BOARD_REVISION_MINOR_=$(BOARD_REVISION_MINOR)
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/samd11d14am_flash.ld
+
+# Default bootloader size is now 2K, allow to specify other
+ifeq ($(BOOTLOADER_SIZE), )
+	BOOTLOADER_SIZE := 0x800
+endif
+LDFLAGS += -Wl,--defsym=BOOTLOADER_SIZE=$(BOOTLOADER_SIZE)
+
+# For flash-jlink target
+JLINK_DEVICE = ATSAMD11D14
+
+# flash using dfu-util
+flash: $(BUILD)/$(PROJECT).bin
+	dfu-util -a 0 -d 1d50:615c -D $< || dfu-util -a 0 -d 16d0:05a5 -D $<
diff --git a/hw/bsp/samd11/boards/luna_d11/samd11d14am_flash.ld b/hw/bsp/samd11/boards/cynthion_d11/samd11d14am_flash.ld
similarity index 97%
rename from hw/bsp/samd11/boards/luna_d11/samd11d14am_flash.ld
rename to hw/bsp/samd11/boards/cynthion_d11/samd11d14am_flash.ld
index cb633c195..f175e6504 100644
--- a/hw/bsp/samd11/boards/luna_d11/samd11d14am_flash.ld
+++ b/hw/bsp/samd11/boards/cynthion_d11/samd11d14am_flash.ld
@@ -35,7 +35,7 @@ SEARCH_DIR(.)
 /* Memory Spaces Definitions */
 MEMORY
 {
-  rom      (rx)  : ORIGIN = 0x00000000 + 4K, LENGTH = 0x00004000 - 4K
+  rom      (rx)  : ORIGIN = 0x00000000 + BOOTLOADER_SIZE, LENGTH = 0x00004000 - BOOTLOADER_SIZE
   ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
 }
 
diff --git a/hw/bsp/samd11/boards/luna_d11/board.mk b/hw/bsp/samd11/boards/luna_d11/board.mk
deleted file mode 100644
index ad9cfb25d..000000000
--- a/hw/bsp/samd11/boards/luna_d11/board.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-CFLAGS += -D__SAMD11D14AM__
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/samd11d14am_flash.ld
-
-# For flash-jlink target
-JLINK_DEVICE = ATSAMD11D14
-
-# flash using dfu-util
-flash: $(BUILD)/$(PROJECT).bin
-	dfu-util -a 0 -d 1d50:615c -D $< || dfu-util -a 0 -d 16d0:05a5 -D $<
diff --git a/hw/bsp/samd11/boards/samd11_xplained/board.h b/hw/bsp/samd11/boards/samd11_xplained/board.h
index cfeac673c..2bbec4958 100644
--- a/hw/bsp/samd11/boards/samd11_xplained/board.h
+++ b/hw/bsp/samd11/boards/samd11_xplained/board.h
@@ -38,6 +38,7 @@
 // Button
 #define BUTTON_PIN            PIN_PA14 // pin PB22
 #define BUTTON_STATE_ACTIVE   0
+#define BUTTON_PULL_MODE      GPIO_PULL_UP
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/samd11/family.c b/hw/bsp/samd11/family.c
index 8d9633971..e232761cc 100644
--- a/hw/bsp/samd11/family.c
+++ b/hw/bsp/samd11/family.c
@@ -78,7 +78,7 @@ void board_init(void)
 
   // Button init
   gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
+  gpio_set_pin_pull_mode(BUTTON_PIN, BUTTON_PULL_MODE);
 
   /* USB Clock init
    * The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
diff --git a/hw/bsp/samd21/boards/luna_d21/board.h b/hw/bsp/samd21/boards/cynthion_d21/board.h
similarity index 100%
rename from hw/bsp/samd21/boards/luna_d21/board.h
rename to hw/bsp/samd21/boards/cynthion_d21/board.h
diff --git a/hw/bsp/samd21/boards/luna_d21/board.mk b/hw/bsp/samd21/boards/cynthion_d21/board.mk
similarity index 60%
rename from hw/bsp/samd21/boards/luna_d21/board.mk
rename to hw/bsp/samd21/boards/cynthion_d21/board.mk
index 508a72b1f..52c9d60cb 100644
--- a/hw/bsp/samd21/boards/luna_d21/board.mk
+++ b/hw/bsp/samd21/boards/cynthion_d21/board.mk
@@ -2,6 +2,12 @@ CFLAGS += -D__SAMD21G18A__ -DCFG_EXAMPLE_VIDEO_READONLY
 
 LD_FILE = $(BOARD_PATH)/samd21g18a_flash.ld
 
+# Default bootloader size is now 2K, allow to specify other
+ifeq ($(BOOTLOADER_SIZE), )
+	BOOTLOADER_SIZE := 0x800
+endif
+LDFLAGS += -Wl,--defsym=BOOTLOADER_SIZE=$(BOOTLOADER_SIZE)
+
 # For flash-jlink target
 JLINK_DEVICE = ATSAMD21G18
 
diff --git a/hw/bsp/samd21/boards/luna_d21/samd21g18a_flash.ld b/hw/bsp/samd21/boards/cynthion_d21/samd21g18a_flash.ld
similarity index 97%
rename from hw/bsp/samd21/boards/luna_d21/samd21g18a_flash.ld
rename to hw/bsp/samd21/boards/cynthion_d21/samd21g18a_flash.ld
index 158593036..ecb6b8523 100644
--- a/hw/bsp/samd21/boards/luna_d21/samd21g18a_flash.ld
+++ b/hw/bsp/samd21/boards/cynthion_d21/samd21g18a_flash.ld
@@ -35,7 +35,7 @@ SEARCH_DIR(.)
 /* Memory Spaces Definitions */
 MEMORY
 {
-  rom      (rx)  : ORIGIN = 0x00000000 + 4K, LENGTH = 0x00040000 - 4K
+  rom      (rx)  : ORIGIN = 0x00000000 + BOOTLOADER_SIZE, LENGTH = 0x00040000 - BOOTLOADER_SIZE
   ram      (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
 }
 

From 99e75e6a8a0de9903e574a51d6ce8057a1e3e73f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 1 Jul 2023 12:40:56 +0700
Subject: [PATCH 1858/2085] rework ra build

---
 .github/workflows/cmake_arm.yml               |   1 +
 hw/bsp/ra/boards/ra4m1_ek/board.cmake         |  15 ++
 hw/bsp/ra/boards/ra4m1_ek/board.h             |  53 ++++
 hw/bsp/ra/boards/ra4m1_ek/board.mk            |   7 -
 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h   |   6 +-
 .../ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h     |   5 +
 hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld         |   1 +
 hw/bsp/ra/boards/ra4m3_ek/board.cmake         |  15 ++
 hw/bsp/ra/boards/ra4m3_ek/board.h             |  52 ++++
 hw/bsp/ra/boards/ra4m3_ek/board.mk            |   7 -
 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h   |   4 +-
 hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c          | 236 ------------------
 hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld         |   1 +
 .../{boards/ra4m1_ek/ra4m1_ek.c => family.c}  |  43 ++--
 hw/bsp/ra/family.cmake                        | 114 +++++++++
 hw/bsp/ra/family.mk                           |   2 +-
 src/portable/renesas/rusb2/rusb2_ra.h         |  12 +
 17 files changed, 299 insertions(+), 275 deletions(-)
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/board.cmake
 create mode 100644 hw/bsp/ra/boards/ra4m1_ek/board.h
 create mode 100644 hw/bsp/ra/boards/ra4m3_ek/board.cmake
 create mode 100644 hw/bsp/ra/boards/ra4m3_ek/board.h
 delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
 rename hw/bsp/ra/{boards/ra4m1_ek/ra4m1_ek.c => family.c} (83%)
 create mode 100644 hw/bsp/ra/family.cmake

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 0ce63281e..4d8cd5591 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -38,6 +38,7 @@ jobs:
           - 'lpc18'
           - 'lpc55'
           - 'mcx'
+          - 'ra'
           - 'rp2040'
           - 'stm32f0'
           - 'stm32f1'
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.cmake b/hw/bsp/ra/boards/ra4m1_ek/board.cmake
new file mode 100644
index 000000000..37c39061d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.cmake
@@ -0,0 +1,15 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra4m1)
+
+set(JLINK_DEVICE R7FA4M1AB)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/ra4m1_ek.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    )
+  target_sources(${TARGET} PRIVATE
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    )
+endfunction()
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h
new file mode 100644
index 000000000..383ab7399
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1 (BSP_IO_PORT_01_PIN_06)
+#define LED_STATE_ON          1
+
+#define SW1  (BSP_IO_PORT_01_PIN_05)
+#define BUTTON_STATE_ACTIVE   0
+
+const ioport_pin_cfg_t board_pin_cfg[] = {
+    { .pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) },
+    { .pin = SW1 , .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) },
+
+    { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
+    { .pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
+    { .pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.mk b/hw/bsp/ra/boards/ra4m1_ek/board.mk
index eae68f87d..9b0fafb28 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.mk
@@ -3,13 +3,6 @@ MCU_VARIANT = ra4m1
 
 FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m1_ek
 
-SRC_C += \
-	$(FSP_BOARD_DIR)/board_init.c \
-	$(FSP_BOARD_DIR)/board_leds.c \
-
-INC += \
-	$(TOP)/$(FSP_BOARD_DIR)
-
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/ra4m1_ek.ld
 
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h
index b38a79b40..b337e49f2 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h
@@ -2,7 +2,6 @@
 #ifndef BSP_CFG_H_
 #define BSP_CFG_H_
 
-#include "board.h"
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
 
@@ -32,4 +31,9 @@
 #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(1)
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 
+#define BSP_FEATURE_TFU_SUPPORTED 0
+
+// for SystemInit()
+void bsp_init(void * p_args);
+
 #endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h
index 3bde2db0d..4e080023e 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h
@@ -25,6 +25,11 @@
 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
 #define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
 
+#define BSP_TZ_SECURE_BUILD    (0)
+#define BSP_TZ_NONSECURE_BUILD (0)
+
+#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
+
 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld
index 8ddaa0a97..63c1d33aa 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld
@@ -553,6 +553,7 @@ SECTIONS
     {
         . = ALIGN(8);
         __HeapBase = .;
+        PROVIDE(end = .);
         /* Place the STD heap here. */
         KEEP(*(.heap))
         __HeapLimit = .;
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.cmake b/hw/bsp/ra/boards/ra4m3_ek/board.cmake
new file mode 100644
index 000000000..241b659a0
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.cmake
@@ -0,0 +1,15 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra4m3)
+
+set(JLINK_DEVICE R7FA4M3AF)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/ra4m3_ek.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    )
+  target_sources(${TARGET} PRIVATE
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    )
+endfunction()
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h
new file mode 100644
index 000000000..e41302f90
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1 (BSP_IO_PORT_04_PIN_15)
+#define LED_STATE_ON          1
+
+#define SW1  (BSP_IO_PORT_00_PIN_05)
+#define BUTTON_STATE_ACTIVE   0
+
+const ioport_pin_cfg_t board_pin_cfg[] = {
+  {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+  {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.mk b/hw/bsp/ra/boards/ra4m3_ek/board.mk
index 4ca1d365e..266de7c0d 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.mk
@@ -3,13 +3,6 @@ MCU_VARIANT = ra4m3
 
 FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m3_ek
 
-SRC_C += \
-	$(FSP_BOARD_DIR)/board_init.c \
-	$(FSP_BOARD_DIR)/board_leds.c \
-
-INC += \
-	$(TOP)/$(FSP_BOARD_DIR)
-
 # All source paths should be relative to the top level.
 LD_FILE = $(BOARD_PATH)/ra4m3_ek.ld
 
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h
index a84d81e8d..a9cb8210b 100755
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h
@@ -2,7 +2,6 @@
 #ifndef BSP_CFG_H_
 #define BSP_CFG_H_
 
-#include "board.h"
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
 
@@ -32,4 +31,7 @@
 #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(1)
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 
+// for SystemInit()
+void bsp_init(void * p_args);
+
 #endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
deleted file mode 100644
index 327ef71d5..000000000
--- a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2022, Rafael Silva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-#include <stdio.h>
-
-#include "bsp/board.h"
-#include "bsp_api.h"
-#include "r_ioport.h"
-#include "r_ioport_api.h"
-#include "renesas.h"
-
-/* Key code for writing PRCR register. */
-#define BSP_PRV_PRCR_KEY	 (0xA500U)
-#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
-#define BSP_PRV_PRCR_LOCK	 ((BSP_PRV_PRCR_KEY) | 0x0U)
-
-#define SW1  (BSP_IO_PORT_00_PIN_05)
-#define SW2  (BSP_IO_PORT_00_PIN_06)
-#define LED1 (BSP_IO_PORT_04_PIN_15)
-#define LED3 (BSP_IO_PORT_04_PIN_00)
-#define LED2 (BSP_IO_PORT_04_PIN_04)
-
-/* ISR prototypes */
-void usbfs_interrupt_handler(void);
-void usbfs_resume_handler(void);
-void usbfs_d0fifo_handler(void);
-void usbfs_d1fifo_handler(void);
-
-BSP_DONT_REMOVE const
-  fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
-    [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
-    [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
-    [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
-    [3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
-};
-const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
-  [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
-  [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
-  [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
-  [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
-};
-
-const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
-  {.pin = BSP_IO_PORT_04_PIN_07,
-   .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = BSP_IO_PORT_05_PIN_00,
-   .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = BSP_IO_PORT_05_PIN_01,
-   .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-  {.pin = LED2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-  {.pin = LED3, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-  {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
-  {.pin = SW2, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)}};
-
-const ioport_cfg_t g_bsp_pin_cfg = {
-  .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
-  .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
-};
-ioport_instance_ctrl_t g_ioport_ctrl;
-const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void usbfs_interrupt_handler(void)
-{
-  IRQn_Type irq = R_FSP_CurrentIrqGet();
-  R_BSP_IrqStatusClear(irq);
-
-#if CFG_TUH_ENABLED
-  tuh_int_handler(0);
-#endif
-
-#if CFG_TUD_ENABLED
-  tud_int_handler(0);
-#endif
-}
-void usbfs_resume_handler(void)
-{
-  IRQn_Type irq = R_FSP_CurrentIrqGet();
-  R_BSP_IrqStatusClear(irq);
-
-#if CFG_TUH_ENABLED
-  tuh_int_handler(0);
-#endif
-
-#if CFG_TUD_ENABLED
-  tud_int_handler(0);
-#endif
-}
-
-void usbfs_d0fifo_handler(void)
-{
-  IRQn_Type irq = R_FSP_CurrentIrqGet();
-  R_BSP_IrqStatusClear(irq);
-
-#if CFG_TUH_ENABLED
-  tuh_int_handler(0);
-#endif
-
-#if CFG_TUD_ENABLED
-  tud_int_handler(0);
-#endif
-}
-
-void usbfs_d1fifo_handler(void)
-{
-  IRQn_Type irq = R_FSP_CurrentIrqGet();
-  R_BSP_IrqStatusClear(irq);
-
-#if CFG_TUH_ENABLED
-  tuh_int_handler(0);
-#endif
-
-#if CFG_TUD_ENABLED
-  tud_int_handler(0);
-#endif
-}
-
-void board_init(void)
-{
-  /* Configure pins. */
-  R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
-
-  /* Enable USB_BASE */
-  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
-  R_MSTP->MSTPCRB &= ~(1U << 11U);
-  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  /* Init systick */
-  SysTick_Config(SystemCoreClock / 1000);
-#endif
-}
-
-//--------------------------------------------------------------------+
-// Board porting API
-//--------------------------------------------------------------------+
-
-void board_led_write(bool state)
-{
-  R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state);
-  R_IOPORT_PinWrite(&g_ioport_ctrl, LED2, state);
-  R_IOPORT_PinWrite(&g_ioport_ctrl, LED3, state);
-}
-
-uint32_t board_button_read(void)
-{
-  bsp_io_level_t lvl;
-  R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
-  return lvl;
-}
-
-int board_uart_read(uint8_t *buf, int len)
-{
-  (void) buf;
-  (void) len;
-  return 0;
-}
-
-int board_uart_write(void const *buf, int len)
-{
-  (void) buf;
-  (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#else
-#endif
-
-int close(int fd)
-{
-  (void) fd;
-  return -1;
-}
-int fstat(int fd, void *pstat)
-{
-  (void) fd;
-  (void) pstat;
-  return 0;
-}
-off_t lseek(int fd, off_t pos, int whence)
-{
-  (void) fd;
-  (void) pos;
-  (void) whence;
-  return 0;
-}
-int isatty(int fd)
-{
-  (void) fd;
-  return 1;
-}
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld
index 5bc335cb4..520b44cc6 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld
@@ -413,6 +413,7 @@ SECTIONS
     {
         . = ALIGN(8);
         __HeapBase = .;
+        PROVIDE(end = .);
         /* Place the STD heap here. */
         KEEP(*(.heap))
         __HeapLimit = .;
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c b/hw/bsp/ra/family.c
similarity index 83%
rename from hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c
rename to hw/bsp/ra/family.c
index ea2204837..42cb2d4a4 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.c
+++ b/hw/bsp/ra/family.c
@@ -26,23 +26,33 @@
 
 #include <stdio.h>
 
-#include "bsp/board.h"
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#pragma GCC diagnostic ignored "-Wundef"
+
+// extra push due to https://github.com/renesas/fsp/pull/278
+#pragma GCC diagnostic push
+#endif
+
 #include "bsp_api.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 #include "r_ioport.h"
 #include "r_ioport_api.h"
 #include "renesas.h"
 
+#include "bsp/board.h"
+#include "board.h"
+
 /* Key code for writing PRCR register. */
 #define BSP_PRV_PRCR_KEY	 (0xA500U)
 #define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
 #define BSP_PRV_PRCR_LOCK	 ((BSP_PRV_PRCR_KEY) | 0x0U)
 
-#define SW1  (BSP_IO_PORT_01_PIN_05)
-#define LED1 (BSP_IO_PORT_01_PIN_06)
-
-#define LED_STATE_ON          1
-#define BUTTON_STATE_ACTIVE   0
-
 /* ISR prototypes */
 void usbfs_interrupt_handler(void);
 void usbfs_resume_handler(void);
@@ -50,7 +60,7 @@ void usbfs_d0fifo_handler(void);
 void usbfs_d1fifo_handler(void);
 
 BSP_DONT_REMOVE const
-  fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
+fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
     [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
     [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
     [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
@@ -63,22 +73,12 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT
   [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
 };
 
-const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
-  { .pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) },
-  { .pin = SW1 , .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) },
-
-  { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
-  { .pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
-  { .pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
-
-};
-
 const ioport_cfg_t g_bsp_pin_cfg = {
-  .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t),
-  .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+  .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
+  .p_pin_cfg_data = board_pin_cfg,
 };
 ioport_instance_ctrl_t g_ioport_ctrl;
-const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
+//const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
@@ -204,7 +204,6 @@ uint32_t board_millis(void)
 {
   return system_ticks;
 }
-#else
 #endif
 
 int close(int fd)
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
new file mode 100644
index 000000000..c4c25bf4f
--- /dev/null
+++ b/hw/bsp/ra/family.cmake
@@ -0,0 +1,114 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+set(FSP_RA ${TOP}/hw/mcu/renesas/fsp/ra/fsp)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS RA CACHE INTERNAL "")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Source/startup.c
+      ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Source/system.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_clocks.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_common.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_delay.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_group_irq.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_guard.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_io.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_irq.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_register_protection.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c
+      ${FSP_RA}/src/bsp/mcu/all/bsp_security.c
+      ${FSP_RA}/src/r_ioport/r_ioport.c
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      _RA_TZ_NONSECURE
+      )
+
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -ffreestanding
+      )
+
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      ${FSP_RA}/inc
+      ${FSP_RA}/inc/api
+      ${FSP_RA}/inc/instances
+      ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Include
+      ${FSP_RA}/src/bsp/mcu/${MCU_VARIANT}
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        # linker file
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nano.specs
+        --specs=nosys.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
+    ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 103d3cfa6..8e4f80eaf 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -35,9 +35,9 @@ SRC_C += \
 
 INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-	$(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(BOARD_PATH)/fsp_cfg \
+	$(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \
 	$(TOP)/$(FSP_RA)/inc \
 	$(TOP)/$(FSP_RA)/inc/api \
 	$(TOP)/$(FSP_RA)/inc/instances \
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 5be9f11ce..be0a9fa66 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -31,9 +31,21 @@
 extern "C" {
 #endif
 
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+
+// extra push due to https://github.com/renesas/fsp/pull/278
+#pragma GCC diagnostic push
+#endif
+
 /* renesas fsp api */
 #include "bsp_api.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 #define RUSB2_REG_BASE (0x40090000)
 
 #if defined(__ICCARM__)

From 22fb66436db38e701b0b1c69ea80c5c3d50d445e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 1 Jul 2023 16:40:47 +0700
Subject: [PATCH 1859/2085] update linker

---
 hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h     | 180 ++++++
 hw/bsp/ra/boards/ra4m1_ek/board.cmake         |  11 +-
 hw/bsp/ra/boards/ra4m1_ek/board.h             |  18 +-
 hw/bsp/ra/boards/ra4m1_ek/board.mk            |   5 -
 hw/bsp/ra/boards/ra4m3_ek/board.cmake         |  11 +-
 hw/bsp/ra/boards/ra4m3_ek/board.mk            |   5 -
 hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld         | 576 ------------------
 hw/bsp/ra/family.c                            | 167 +++--
 hw/bsp/ra/family.cmake                        |  17 +-
 hw/bsp/ra/family.mk                           |   5 +
 .../ra4m1_ek.ld => linker/gcc/fsp.ld}         |  33 +-
 hw/bsp/ra/linker/gcc/ra4m1.ld                 |  22 +
 hw/bsp/ra/linker/gcc/ra4m3.ld                 |  22 +
 hw/bsp/ra/linker/gcc/ra6m1.ld                 |  22 +
 tools/cmake/cpu/cortex-m4.cmake               |   8 +-
 15 files changed, 375 insertions(+), 727 deletions(-)
 create mode 100644 hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
 delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld
 rename hw/bsp/ra/{boards/ra4m1_ek/ra4m1_ek.ld => linker/gcc/fsp.ld} (97%)
 create mode 100644 hw/bsp/ra/linker/gcc/ra4m1.ld
 create mode 100644 hw/bsp/ra/linker/gcc/ra4m3.ld
 create mode 100644 hw/bsp/ra/linker/gcc/ra6m1.ld

diff --git a/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..8c39a2fb8
--- /dev/null
+++ b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,180 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#pragma GCC diagnostic ignored "-Wundef"
+
+// extra push due to https://github.com/renesas/fsp/pull/278
+#pragma GCC diagnostic push
+#endif
+
+#include "bsp_api.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.cmake b/hw/bsp/ra/boards/ra4m1_ek/board.cmake
index 37c39061d..51c1f3d6c 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.cmake
@@ -3,13 +3,8 @@ set(MCU_VARIANT ra4m1)
 
 set(JLINK_DEVICE R7FA4M1AB)
 
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/ra4m1_ek.ld)
-
 function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    )
-  target_sources(${TARGET} PRIVATE
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    )
+  target_compile_definitions(${TARGET} PUBLIC)
+  target_sources(${TARGET} PRIVATE)
+  target_include_directories(${BOARD_TARGET} PUBLIC)
 endfunction()
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h
index 383ab7399..b580bb5e9 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.h
@@ -31,19 +31,19 @@
 extern "C" {
 #endif
 
-#define LED1 (BSP_IO_PORT_01_PIN_06)
-#define LED_STATE_ON          1
+#define LED1          BSP_IO_PORT_01_PIN_06
+#define LED_STATE_ON  1
 
-#define SW1  (BSP_IO_PORT_01_PIN_05)
+#define SW1                   BSP_IO_PORT_01_PIN_05
 #define BUTTON_STATE_ACTIVE   0
 
 const ioport_pin_cfg_t board_pin_cfg[] = {
-    { .pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) },
-    { .pin = SW1 , .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) },
-
-    { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
-    { .pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
-    { .pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) },
+    {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
+    {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
+    // USB D+, D-, VBus
+    {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+    {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+    {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
 };
 
 #ifdef __cplusplus
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.mk b/hw/bsp/ra/boards/ra4m1_ek/board.mk
index 9b0fafb28..a06d75ef3 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.mk
@@ -1,11 +1,6 @@
 CPU_CORE = cortex-m4
 MCU_VARIANT = ra4m1
 
-FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m1_ek
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/ra4m1_ek.ld
-
 # For flash-jlink target
 JLINK_DEVICE = R7FA4M1AB
 JLINK_IF     = SWD
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.cmake b/hw/bsp/ra/boards/ra4m3_ek/board.cmake
index 241b659a0..637e99db6 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.cmake
@@ -3,13 +3,8 @@ set(MCU_VARIANT ra4m3)
 
 set(JLINK_DEVICE R7FA4M3AF)
 
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/ra4m3_ek.ld)
-
 function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    )
-  target_sources(${TARGET} PRIVATE
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    )
+  target_compile_definitions(${TARGET} PUBLIC)
+  target_sources(${TARGET} PRIVATE)
+  target_include_directories(${BOARD_TARGET} PUBLIC)
 endfunction()
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.mk b/hw/bsp/ra/boards/ra4m3_ek/board.mk
index 266de7c0d..f2d0ecfc5 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.mk
@@ -1,11 +1,6 @@
 CPU_CORE = cortex-m33
 MCU_VARIANT = ra4m3
 
-FSP_BOARD_DIR = hw/mcu/renesas/fsp/ra/board/ra4m3_ek
-
-# All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/ra4m3_ek.ld
-
 # For flash-jlink target
 JLINK_DEVICE = R7FA4M3AF
 JLINK_IF     = SWD
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld b/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld
deleted file mode 100644
index 520b44cc6..000000000
--- a/hw/bsp/ra/boards/ra4m3_ek/ra4m3_ek.ld
+++ /dev/null
@@ -1,576 +0,0 @@
-/* generated memory regions file - do not edit */
-RAM_START = 0x20000000;
-RAM_LENGTH = 0x20000;
-FLASH_START = 0x00000000;
-FLASH_LENGTH = 0x100000;
-DATA_FLASH_START = 0x08000000;
-DATA_FLASH_LENGTH = 0x2000;
-OPTION_SETTING_START = 0x0100A100;
-OPTION_SETTING_LENGTH = 0x100;
-OPTION_SETTING_S_START = 0x0100A200;
-OPTION_SETTING_S_LENGTH = 0x100;
-ID_CODE_START = 0x00000000;
-ID_CODE_LENGTH = 0x0;
-SDRAM_START = 0x90000000;
-SDRAM_LENGTH = 0x0;
-QSPI_FLASH_START = 0x60000000;
-QSPI_FLASH_LENGTH = 0x4000000;
-OSPI_DEVICE_0_START = 0x68000000;
-OSPI_DEVICE_0_LENGTH = 0x0;
-OSPI_DEVICE_1_START = 0x70000000;
-OSPI_DEVICE_1_LENGTH = 0x0;
-
-/*
-    Linker File for Renesas FSP
-*/
-
-QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
-OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
-OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
-
-/* This is a non-secure project if the OPTION_SETTING region is non-zero and it does not start at the base address for
- * secure option settings (meaning the secure option settings were already allocated in the secure project). */
-__TZ_NS_PROJECT = LENGTH(OPTION_SETTING) && DEFINED(OPTION_SETTING_S_START) && (ABSOLUTE(OPTION_SETTING_START_S) != ORIGIN(OPTION_SETTING));
-
-/* This is a secure project if the option setting base address matches the option setting base address for secure
- * option settings. This is also set for flat projects because the CPU runs in secure mode for flat projects.
- * This is not defined for projects that do not support TrustZone. */
-__TZ_S_PROJECT = LENGTH(OPTION_SETTING) && DEFINED(OPTION_SETTING_S_START) && (ABSOLUTE(OPTION_SETTING_START_S) == ORIGIN(OPTION_SETTING));
-
-/* If a flat (secure) project has defined RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
-__RESERVE_NS_RAM = __TZ_S_PROJECT && DEFINED(RAM_NS_BUFFER_LENGTH);
-
-RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
-RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
-RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
-RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
-
-/* Define memory regions. */
-MEMORY
-{
-  FLASH (rx)      : ORIGIN = FLASH_START, LENGTH = FLASH_LENGTH
-  RAM (rwx)       : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
-  DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
-  QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
-  OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
-  OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
-  SDRAM (rwx)     : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
-  OPTION_SETTING (r): ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
-  OPTION_SETTING_S (r): ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
-  ID_CODE (rx)    : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
-}
-
-OPTION_SETTING_START_NS = 0x0100A180;
-OPTION_SETTING_START_S = 0x0100A100;
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- *   __qspi_flash_start__
- *   __qspi_flash_end__
- *   __qspi_flash_code_size__
- *   __qspi_region_max_size__
- *   __qspi_region_start_address__
- *   __qspi_region_end_address__
- *   __ospi_device_0_start__
- *   __ospi_device_0_end__
- *   __ospi_device_0_code_size__
- *   __ospi_device_0_region_max_size__
- *   __ospi_device_0_region_start_address__
- *   __ospi_device_0_region_end_address__
- *   __ospi_device_1_start__
- *   __ospi_device_1_end__
- *   __ospi_device_1_code_size__
- *   __ospi_device_1_region_max_size__
- *   __ospi_device_1_region_start_address__
- *   __ospi_device_1_region_end_address__
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        __tz_FLASH_S = ABSOLUTE(FLASH_START);
-        __ROM_Start = .;
-
-        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
-         * space because ROM registers are at address 0x400 and there is very little space
-         * in between. */
-        KEEP(*(.fixed_vectors*))
-        KEEP(*(.application_vectors*))
-        __Vectors_End = .;
-
-        /* ROM Registers start at address 0x00000400 */
-        . = __ROM_Start + 0x400;
-        KEEP(*(.rom_registers*))
-
-        /* Reserving 0x100 bytes of space for ROM registers. */
-        . = __ROM_Start + 0x500;
-
-        *(.text*)
-
-        KEEP(*(.version))
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-        __usb_dev_descriptor_start_fs = .;
-        KEEP(*(.usb_device_desc_fs*))
-        __usb_cfg_descriptor_start_fs = .;
-        KEEP(*(.usb_config_desc_fs*))
-        __usb_interface_descriptor_start_fs = .;
-        KEEP(*(.usb_interface_desc_fs*))
-        __usb_descriptor_end_fs = .;
-        __usb_dev_descriptor_start_hs = .;
-        KEEP(*(.usb_device_desc_hs*))
-        __usb_cfg_descriptor_start_hs = .;
-        KEEP(*(.usb_config_desc_hs*))
-        __usb_interface_descriptor_start_hs = .;
-        KEEP(*(.usb_interface_desc_hs*))
-        __usb_descriptor_end_hs = .;
-
-        KEEP(*(.eh_frame*))
-
-        __ROM_End = .;
-    } > FLASH = 0xFF
-
-    __Vectors_Size = __Vectors_End - __Vectors;
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    /* To copy multiple ROM to RAM sections,
-     * uncomment .copy.table section and,
-     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
-    /*
-    .copy.table :
-    {
-        . = ALIGN(4);
-        __copy_table_start__ = .;
-        LONG (__etext)
-        LONG (__data_start__)
-        LONG (__data_end__ - __data_start__)
-        LONG (__etext2)
-        LONG (__data2_start__)
-        LONG (__data2_end__ - __data2_start__)
-        __copy_table_end__ = .;
-    } > FLASH
-    */
-
-    /* To clear multiple BSS sections,
-     * uncomment .zero.table section and,
-     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
-    /*
-    .zero.table :
-    {
-        . = ALIGN(4);
-        __zero_table_start__ = .;
-        LONG (__bss_start__)
-        LONG (__bss_end__ - __bss_start__)
-        LONG (__bss2_start__)
-        LONG (__bss2_end__ - __bss2_start__)
-        __zero_table_end__ = .;
-    } > FLASH
-    */
-
-    __etext = .;
-
-    __tz_RAM_S = ORIGIN(RAM);
-
-    /* If DTC is used, put the DTC vector table at the start of SRAM.
-       This avoids memory holes due to 1K alignment required by it. */
-    .fsp_dtc_vector_table (NOLOAD) :
-    {
-        . = ORIGIN(RAM);
-        *(.fsp_dtc_vector_table)
-    } > RAM
-
-    /* Initialized data section. */
-    .data :
-    {
-        __data_start__ = .;
-        . = ALIGN(4);
-
-        __Code_In_RAM_Start = .;
-
-        KEEP(*(.code_in_ram*))
-        __Code_In_RAM_End = .;
-
-        *(vtable)
-        /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
-        *(.data.*)
-        *(.data)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-
-        . = ALIGN(4);
-
-        /* All data end */
-        __data_end__ = .;
-
-    } > RAM AT > FLASH
-
-
-    /* TrustZone Secure Gateway Stubs Section. */
-    .gnu.sgstubs : ALIGN (1024)
-    {
-        . = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
-        __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
-        _start_sg = .;
-        *(.gnu.sgstubs*)
-        . = ALIGN(32);
-        _end_sg = .;
-    } > FLASH
-
-    __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(32768);
-
-    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
-    __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
-
-    /* QSPI_FLASH section to be downloaded via debugger */
-    .qspi_flash :
-    {
-        __qspi_flash_start__ = .;
-        KEEP(*(.qspi_flash*))
-        KEEP(*(.code_in_qspi*))
-        __qspi_flash_end__ = .;
-    } > QSPI_FLASH
-    __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
-
-    /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
-    __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
-    .qspi_non_retentive : AT (__qspi_flash_code_addr__)
-    {
-        __qspi_non_retentive_start__ = .;
-        KEEP(*(.qspi_non_retentive*))
-        __qspi_non_retentive_end__ = .;
-    } > QSPI_FLASH
-    __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
-
-    __qspi_region_max_size__ = 0x4000000;   /* Must be the same as defined in MEMORY above */
-    __qspi_region_start_address__ = __qspi_flash_start__;
-    __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
-
-    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
-    __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
-
-    /* Note: There are no secure/non-secure boundaries for QSPI.  These symbols are provided for the RA configuration tool. */
-    __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
-
-    /* OSPI_DEVICE_0 section to be downloaded via debugger */
-    .OSPI_DEVICE_0 :
-    {
-        __ospi_device_0_start__ = .;
-        KEEP(*(.ospi_device_0*))
-        KEEP(*(.code_in_ospi_device_0*))
-        __ospi_device_0_end__ = .;
-    } > OSPI_DEVICE_0
-    __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
-
-    /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
-    __ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__);
-    .ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__)
-    {
-        __ospi_device_0_non_retentive_start__ = .;
-        KEEP(*(.ospi_device_0_non_retentive*))
-        __ospi_device_0_non_retentive_end__ = .;
-    } > OSPI_DEVICE_0
-    __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
-
-    __ospi_device_0_region_max_size__ = 0x8000000;   /* Must be the same as defined in MEMORY above */
-    __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
-    __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
-
-    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
-    __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
-
-    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
-    __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
-
-    /* OSPI_DEVICE_1 section to be downloaded via debugger */
-    .OSPI_DEVICE_1 :
-    {
-        __ospi_device_1_start__ = .;
-        KEEP(*(.ospi_device_1*))
-        KEEP(*(.code_in_ospi_device_1*))
-        __ospi_device_1_end__ = .;
-    } > OSPI_DEVICE_1
-    __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
-
-    /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
-    __ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__);
-    .ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__)
-    {
-        __ospi_device_1_non_retentive_start__ = .;
-        KEEP(*(.ospi_device_1_non_retentive*))
-        __ospi_device_1_non_retentive_end__ = .;
-    } > OSPI_DEVICE_1
-    __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
-
-    __ospi_device_1_region_max_size__ = 0x10000000;   /* Must be the same as defined in MEMORY above */
-    __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
-    __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
-
-    /* Note: There are no secure/non-secure boundaries for OSPI.  These symbols are provided for the RA configuration tool. */
-    __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
-
-    .noinit (NOLOAD):
-    {
-        . = ALIGN(4);
-        __noinit_start = .;
-        KEEP(*(.noinit*))
-        . = ALIGN(8);
-        /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
-        KEEP(*(.heap.*))
-        __noinit_end = .;
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > RAM
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(8);
-        __HeapBase = .;
-        PROVIDE(end = .);
-        /* Place the STD heap here. */
-        KEEP(*(.heap))
-        __HeapLimit = .;
-    } > RAM
-
-    /* Stacks are stored in this section. */
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(8);
-        __StackLimit = .;
-        /* Main stack */
-        KEEP(*(.stack))
-        __StackTop = .;
-        /* Thread stacks */
-        KEEP(*(.stack*))
-        __StackTopAll = .;
-    } > RAM
-
-    PROVIDE(__stack = __StackTopAll);
-
-    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
-       at run time for things such as ThreadX memory pool allocations. */
-    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
-
-    /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
-     * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
-     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
-    __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
-
-    /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
-     * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
-     * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
-     * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
-    __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
-
-    /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
-     * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
-    .ns_buffer (NOLOAD):
-    {
-        /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
-        . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
-
-        KEEP(*(.ns_buffer*))
-    } > RAM
-
-    /* Data flash. */
-    .data_flash :
-    {
-        . = ORIGIN(DATA_FLASH);
-        __tz_DATA_FLASH_S = .;
-        __Data_Flash_Start = .;
-        KEEP(*(.data_flash*))
-        __Data_Flash_End = .;
-
-        __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
-    } > DATA_FLASH
-
-    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
-    __tz_SDRAM_S = ORIGIN(SDRAM);
-
-    /* SDRAM */
-    .sdram (NOLOAD):
-    {
-        __SDRAM_Start = .;
-        KEEP(*(.sdram*))
-        KEEP(*(.frame*))
-        __SDRAM_End = .;
-    } > SDRAM
-
-    /* Note: There are no secure/non-secure boundaries for SDRAM.  These symbols are provided for the RA configuration tool. */
-    __tz_SDRAM_N = __SDRAM_End;
-
-    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
-    __tz_ID_CODE_S = ORIGIN(ID_CODE);
-
-    .id_code :
-    {
-        __ID_Code_Start = .;
-        KEEP(*(.id_code*))
-        __ID_Code_End = .;
-    } > ID_CODE
-
-    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
-    __tz_ID_CODE_N = __ID_Code_End;
-
-    /* Symbol required for RA Configuration tool. */
-    __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING);
-
-    .option_setting :
-    {
-        __OPTION_SETTING_Start = .;
-        KEEP(*(.option_setting_ofs0))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_Start + 0x10 : __OPTION_SETTING_Start;
-        KEEP(*(.option_setting_dualsel))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_Start + 0x34 : __OPTION_SETTING_Start;
-        KEEP(*(.option_setting_sas))
-        __OPTION_SETTING_End = .;
-    } > OPTION_SETTING = 0xFF
-
-    /* Symbol required for RA Configuration tool. */
-    __tz_OPTION_SETTING_N = OPTION_SETTING_START_NS;
-
-    .option_setting_ns :
-    {
-        __OPTION_SETTING_NS_Start = .;
-        KEEP(*(.option_setting_ofs1))
-        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
-        KEEP(*(.option_setting_banksel))
-        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
-        KEEP(*(.option_setting_bps0))
-        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
-        KEEP(*(.option_setting_bps1))
-        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
-        KEEP(*(.option_setting_bps2))
-        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
-        KEEP(*(.option_setting_pbps0))
-        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
-        KEEP(*(.option_setting_pbps1))
-        . = __TZ_NS_PROJECT ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
-        KEEP(*(.option_setting_pbps2))
-        __OPTION_SETTING_NS_End = .;
-    } > OPTION_SETTING = 0xFF
-
-    /* Symbol required for RA Configuration tool. */
-    __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
-
-    .option_setting_s :
-    {
-        __OPTION_SETTING_S_Start = .;
-        KEEP(*(.option_setting_ofs1_sec))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_banksel_sec))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_bps_sec0))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_bps_sec1))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_bps_sec2))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_pbps_sec0))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_pbps_sec1))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_pbps_sec2))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_ofs1_sel))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_banksel_sel))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_bps_sel0))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_bps_sel1))
-        . = __TZ_S_PROJECT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
-        KEEP(*(.option_setting_bps_sel2))
-        __OPTION_SETTING_S_End = .;
-    } > OPTION_SETTING_S = 0xFF
-
-    /* Symbol required for RA Configuration tool. */
-    __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
-}
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 42cb2d4a4..82d7a60c5 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -49,9 +49,9 @@
 #include "board.h"
 
 /* Key code for writing PRCR register. */
-#define BSP_PRV_PRCR_KEY	 (0xA500U)
+#define BSP_PRV_PRCR_KEY	       (0xA500U)
 #define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
-#define BSP_PRV_PRCR_LOCK	 ((BSP_PRV_PRCR_KEY) | 0x0U)
+#define BSP_PRV_PRCR_LOCK	       ((BSP_PRV_PRCR_KEY) | 0x0U)
 
 /* ISR prototypes */
 void usbfs_interrupt_handler(void);
@@ -59,26 +59,87 @@ void usbfs_resume_handler(void);
 void usbfs_d0fifo_handler(void);
 void usbfs_d1fifo_handler(void);
 
-BSP_DONT_REMOVE const
-fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
+const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
     [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
     [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
     [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
     [3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
 };
 const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
-  [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
-  [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
-  [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
-  [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
+    [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
+    [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
+    [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
+    [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
 };
 
-const ioport_cfg_t g_bsp_pin_cfg = {
-  .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
-  .p_pin_cfg_data = board_pin_cfg,
+static const ioport_cfg_t family_pin_cfg = {
+    .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = board_pin_cfg,
 };
-ioport_instance_ctrl_t g_ioport_ctrl;
-//const ioport_instance_t g_ioport = {.p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg};
+static ioport_instance_ctrl_t port_ctrl;
+
+//--------------------------------------------------------------------+
+// Board porting API
+//--------------------------------------------------------------------+
+
+void board_init(void)
+{
+  /* Configure pins. */
+  R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
+
+  board_led_write(false);
+
+  /* Enable USB_BASE */
+  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
+  R_MSTP->MSTPCRB &= ~(1U << 11U);
+  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
+
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+  NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+  SysTick_Config(SystemCoreClock / 1000);
+#endif
+}
+
+void board_led_write(bool state) {
+  R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
+}
+
+uint32_t board_button_read(void) {
+  bsp_io_level_t lvl;
+  R_IOPORT_PinRead(&port_ctrl, SW1, &lvl);
+  return lvl == BUTTON_STATE_ACTIVE;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+volatile uint32_t system_ticks = 0;
+
+void SysTick_Handler(void) {
+  system_ticks++;
+}
+
+uint32_t board_millis(void) {
+  return system_ticks;
+}
+#endif
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
@@ -139,93 +200,29 @@ void usbfs_d1fifo_handler(void)
 #endif
 }
 
-void board_init(void)
-{
-  /* Configure pins. */
-  R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
-
-  /* Enable USB_BASE */
-  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
-  R_MSTP->MSTPCRB &= ~(1U << 11U);
-  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
-
-#if CFG_TUSB_OS == OPT_OS_FREERTOS
-  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
-  NVIC_SetPriority(TU_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USBFS_RESUME_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USBFS_FIFO_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-  NVIC_SetPriority(USBFS_FIFO_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
-#endif
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-  /* Init systick */
-  SysTick_Config(SystemCoreClock / 1000);
-#endif
-}
-
 //--------------------------------------------------------------------+
-// Board porting API
+// stdlib
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  R_IOPORT_PinWrite(&g_ioport_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
-}
-
-uint32_t board_button_read(void)
-{
-  bsp_io_level_t lvl;
-  R_IOPORT_PinRead(&g_ioport_ctrl, SW1, &lvl);
-  return lvl == BUTTON_STATE_ACTIVE;
-}
-
-int board_uart_read(uint8_t *buf, int len)
-{
-  (void) buf;
-  (void) len;
-  return 0;
-}
-
-int board_uart_write(void const *buf, int len)
-{
-  (void) buf;
-  (void) len;
-  return 0;
-}
-
-#if CFG_TUSB_OS == OPT_OS_NONE
-volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
-  system_ticks++;
-}
-
-uint32_t board_millis(void)
-{
-  return system_ticks;
-}
-#endif
-
-int close(int fd)
-{
+int close(int fd) {
   (void) fd;
   return -1;
 }
-int fstat(int fd, void *pstat)
-{
+
+int fstat(int fd, void *pstat) {
   (void) fd;
   (void) pstat;
   return 0;
 }
-off_t lseek(int fd, off_t pos, int whence)
-{
+
+off_t lseek(int fd, off_t pos, int whence) {
   (void) fd;
   (void) pos;
   (void) whence;
   return 0;
 }
-int isatty(int fd)
-{
+
+int isatty(int fd) {
   (void) fd;
   return 1;
 }
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index c4c25bf4f..57e05a4b1 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -9,6 +9,7 @@ set(FSP_RA ${TOP}/hw/mcu/renesas/fsp/ra/fsp)
 
 # include board specific
 include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+#set(FREERTOS_PORT A_CUSTOM_PORT CACHE INTERNAL "")
 
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
@@ -58,10 +59,15 @@ function(add_board_target BOARD_TARGET)
 
     update_board(${BOARD_TARGET})
 
+    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+      set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc/${MCU_VARIANT}.ld)
+    endif ()
+
     if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
       target_link_options(${BOARD_TARGET} PUBLIC
         # linker file
         "LINKER:--script=${LD_FILE_GNU}"
+        -L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc
         -nostartfiles
         # nanolib
         --specs=nano.specs
@@ -98,7 +104,16 @@ function(family_configure_example TARGET RTOS)
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
     )
 
-  # Add TinyUSB target and port source
+#  # RA has custom freertos port
+#  if (NOT TARGET freertos_kernel_port)
+#    add_library(freertos_kernel_port STATIC)
+#    target_sources(freertos_kernel_port PUBLIC ${FSP_RA}/src/rm_freertos_port/port.c)
+#    target_include_directories(freertos_kernel_port PUBLIC ${FSP_RA}/src/rm_freertos_port)
+#
+#    target_link_libraries(freertos_kernel_port PUBLIC freertos_kernel)
+#  endif ()
+
+    # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 8e4f80eaf..6e90583e7 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -43,6 +43,11 @@ INC += \
 	$(TOP)/$(FSP_RA)/inc/instances \
 	$(TOP)/$(FSP_RA)/src/bsp/mcu/$(MCU_VARIANT) \
 
+ifndef LD_FILE
+LD_FILE = $(FAMILY_PATH)/linker/gcc/$(MCU_VARIANT).ld
+LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc
+endif
+
 # For freeRTOS port source
 # hack to use the port provided by renesas
 FREERTOS_PORTABLE_SRC = $(FSP_RA)/src/rm_freertos_port
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld b/hw/bsp/ra/linker/gcc/fsp.ld
similarity index 97%
rename from hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld
rename to hw/bsp/ra/linker/gcc/fsp.ld
index 63c1d33aa..453d46f24 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/ra4m1_ek.ld
+++ b/hw/bsp/ra/linker/gcc/fsp.ld
@@ -1,29 +1,3 @@
-/* generated memory regions file - do not edit */
-RAM_START = 0x20000000;
-RAM_LENGTH = 0x8000;
-FLASH_START = 0x00000000;
-FLASH_LENGTH = 0x40000;
-DATA_FLASH_START = 0x40100000;
-DATA_FLASH_LENGTH = 0x2000;
-OPTION_SETTING_START = 0x00000000;
-OPTION_SETTING_LENGTH = 0x0;
-OPTION_SETTING_S_START = 0x80000000;
-OPTION_SETTING_S_LENGTH = 0x0;
-ID_CODE_START = 0x01010018;
-ID_CODE_LENGTH = 0x20;
-SDRAM_START = 0x80010000;
-SDRAM_LENGTH = 0x0;
-QSPI_FLASH_START = 0x60000000;
-QSPI_FLASH_LENGTH = 0x0;
-OSPI_DEVICE_0_START = 0x80020000;
-OSPI_DEVICE_0_LENGTH = 0x0;
-OSPI_DEVICE_1_START = 0x80030000;
-OSPI_DEVICE_1_LENGTH = 0x0;
-
-/*
-                  Linker File for Renesas FSP
-*/
-
 /* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
 /*
  XIP_SECONDARY_SLOT_IMAGE = 1;
@@ -629,6 +603,11 @@ SECTIONS
     /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
     __tz_ID_CODE_S = ORIGIN(ID_CODE);
 
+    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool.
+     *       Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+     *       memory region between TrustZone projects. */
+    __tz_ID_CODE_N = __tz_ID_CODE_S;
+
     .id_code :
     {
         __ID_Code_Start = .;
@@ -636,8 +615,6 @@ SECTIONS
         __ID_Code_End = .;
     } > ID_CODE
 
-    /* Note: There are no secure/non-secure boundaries for ID_CODE.  These symbols are provided for the RA configuration tool. */
-    __tz_ID_CODE_N = __ID_Code_End;
 
     /* Symbol required for RA Configuration tool. */
     __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
diff --git a/hw/bsp/ra/linker/gcc/ra4m1.ld b/hw/bsp/ra/linker/gcc/ra4m1.ld
new file mode 100644
index 000000000..218acbb2a
--- /dev/null
+++ b/hw/bsp/ra/linker/gcc/ra4m1.ld
@@ -0,0 +1,22 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x8000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x40000;
+DATA_FLASH_START = 0x40100000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x00000000;
+OPTION_SETTING_LENGTH = 0x0;
+OPTION_SETTING_S_START = 0x80000000;
+OPTION_SETTING_S_LENGTH = 0x0;
+ID_CODE_START = 0x01010018;
+ID_CODE_LENGTH = 0x20;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x0;
+OSPI_DEVICE_0_START = 0x80020000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x80030000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/linker/gcc/ra4m3.ld b/hw/bsp/ra/linker/gcc/ra4m3.ld
new file mode 100644
index 000000000..7b3a63fbe
--- /dev/null
+++ b/hw/bsp/ra/linker/gcc/ra4m3.ld
@@ -0,0 +1,22 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x20000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x100000;
+DATA_FLASH_START = 0x08000000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x0100A100;
+OPTION_SETTING_LENGTH = 0x100;
+OPTION_SETTING_S_START = 0x0100A200;
+OPTION_SETTING_S_LENGTH = 0x100;
+ID_CODE_START = 0x00000000;
+ID_CODE_LENGTH = 0x0;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x4000000;
+OSPI_DEVICE_0_START = 0x80020000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x80030000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/linker/gcc/ra6m1.ld b/hw/bsp/ra/linker/gcc/ra6m1.ld
new file mode 100644
index 000000000..91d27f74c
--- /dev/null
+++ b/hw/bsp/ra/linker/gcc/ra6m1.ld
@@ -0,0 +1,22 @@
+RAM_START = 0x1FFE0000;
+RAM_LENGTH = 0x40000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x80000;
+DATA_FLASH_START = 0x40100000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x00000000;
+OPTION_SETTING_LENGTH = 0x0;
+OPTION_SETTING_S_START = 0x80000000;
+OPTION_SETTING_S_LENGTH = 0x0;
+ID_CODE_START = 0x0100A150;
+ID_CODE_LENGTH = 0x10;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x4000000;
+OSPI_DEVICE_0_START = 0x80020000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x80030000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+INCLUDE fsp.ld
diff --git a/tools/cmake/cpu/cortex-m4.cmake b/tools/cmake/cpu/cortex-m4.cmake
index a0cf3498f..4e9bc242d 100644
--- a/tools/cmake/cpu/cortex-m4.cmake
+++ b/tools/cmake/cpu/cortex-m4.cmake
@@ -6,7 +6,9 @@ if (TOOLCHAIN STREQUAL "gcc")
     -mfpu=fpv4-sp-d16
     )
 
-  set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
+  if (NOT DEFINED FREERTOS_PORT)
+    set(FREERTOS_PORT GCC_ARM_CM4F CACHE INTERNAL "")
+  endif ()
 
 elseif (TOOLCHAIN STREQUAL "iar")
   set(TOOLCHAIN_COMMON_FLAGS
@@ -14,6 +16,8 @@ elseif (TOOLCHAIN STREQUAL "iar")
     --fpu VFPv4
     )
 
-  set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
+  if (NOT DEFINED FREERTOS_PORT)
+    set(FREERTOS_PORT IAR_ARM_CM4F CACHE INTERNAL "")
+  endif ()
 
 endif ()

From 50381f7b4caf2d5ee10de16e9cf7bf2fb113364a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 1 Jul 2023 17:08:20 +0700
Subject: [PATCH 1860/2085] refactor to match fsp_cfg

---
 .../ra/boards/ra4m1_ek/fsp_cfg/{ => bsp}/bsp_cfg.h  |  0
 .../ra4m1_ek/fsp_cfg/{ => bsp}/bsp_clock_cfg.h      |  0
 .../ra4m1_ek/fsp_cfg/{ => bsp}/bsp_mcu_device_cfg.h |  0
 .../fsp_cfg/{ => bsp}/bsp_mcu_device_pn_cfg.h       |  0
 .../ra4m1_ek/fsp_cfg/{ => bsp}/bsp_mcu_family_cfg.h |  0
 .../ra/boards/ra4m3_ek/fsp_cfg/{ => bsp}/bsp_cfg.h  |  0
 .../ra4m3_ek/fsp_cfg/{ => bsp}/bsp_clock_cfg.h      |  0
 .../ra4m3_ek/fsp_cfg/{ => bsp}/bsp_mcu_family_cfg.h |  0
 hw/bsp/ra/boards/ra6m1_ek/board.cmake               | 13 +++++++++++++
 hw/bsp/ra/family.cmake                              |  1 +
 hw/bsp/ra/family.mk                                 |  1 +
 11 files changed, 15 insertions(+)
 rename hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/{ => bsp}/bsp_cfg.h (100%)
 rename hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/{ => bsp}/bsp_clock_cfg.h (100%)
 rename hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/{ => bsp}/bsp_mcu_device_cfg.h (100%)
 rename hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/{ => bsp}/bsp_mcu_device_pn_cfg.h (100%)
 rename hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/{ => bsp}/bsp_mcu_family_cfg.h (100%)
 rename hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/{ => bsp}/bsp_cfg.h (100%)
 mode change 100755 => 100644
 rename hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/{ => bsp}/bsp_clock_cfg.h (100%)
 rename hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/{ => bsp}/bsp_mcu_family_cfg.h (100%)
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/board.cmake

diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_cfg.h
rename to hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_cfg.h
rename to hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_device_pn_cfg.h
rename to hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_mcu_family_cfg.h
rename to hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
old mode 100755
new mode 100644
similarity index 100%
rename from hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_clock_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_clock_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_mcu_family_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.cmake b/hw/bsp/ra/boards/ra6m1_ek/board.cmake
new file mode 100644
index 000000000..0d599b2da
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.cmake
@@ -0,0 +1,13 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra6m1)
+
+set(JLINK_DEVICE R7FA6M1AD)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    )
+  target_sources(${TARGET} PRIVATE
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    )
+endfunction()
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index 57e05a4b1..cf7dfad55 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -49,6 +49,7 @@ function(add_board_target BOARD_TARGET)
       ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
       ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
       ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg/bsp
       ${CMSIS_DIR}/CMSIS/Core/Include
       ${FSP_RA}/inc
       ${FSP_RA}/inc/api
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 6e90583e7..03125aac5 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -37,6 +37,7 @@ INC += \
 	$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
 	$(TOP)/$(BOARD_PATH) \
 	$(TOP)/$(BOARD_PATH)/fsp_cfg \
+	$(TOP)/$(BOARD_PATH)/fsp_cfg/bsp \
 	$(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \
 	$(TOP)/$(FSP_RA)/inc \
 	$(TOP)/$(FSP_RA)/inc/api \

From c5d958d104d4ded1554876cf86aec85dc98a1b37 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 1 Jul 2023 17:27:45 +0700
Subject: [PATCH 1861/2085] add ra6m1 board

---
 .../ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h  |  4 +
 .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h |  5 --
 hw/bsp/ra/boards/ra6m1_ek/board.h             | 53 ++++++++++++
 .../ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h  | 77 +++++++++++++++++
 .../ra6m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h      | 23 +++++
 .../ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h |  5 ++
 .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h       | 11 +++
 .../ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 84 +++++++++++++++++++
 .../boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h | 16 ++++
 .../ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h |  7 ++
 .../ra/boards/ra6m1_ek/fsp_cfg/vector_data.h  |  5 ++
 11 files changed, 285 insertions(+), 5 deletions(-)
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/board.h
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/vector_data.h

diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
index b337e49f2..700d9b29f 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -31,7 +31,11 @@
 #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(1)
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 
+#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
+
 #define BSP_FEATURE_TFU_SUPPORTED 0
+#define BSP_TZ_SECURE_BUILD    (0)
+#define BSP_TZ_NONSECURE_BUILD (0)
 
 // for SystemInit()
 void bsp_init(void * p_args);
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
index 4e080023e..3bde2db0d 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -25,11 +25,6 @@
 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
 #define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
 
-#define BSP_TZ_SECURE_BUILD    (0)
-#define BSP_TZ_NONSECURE_BUILD (0)
-
-#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
-
 #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
 #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h
new file mode 100644
index 000000000..982a78e52
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1          BSP_IO_PORT_01_PIN_12
+#define LED_STATE_ON  1
+
+#define SW1                   BSP_IO_PORT_04_PIN_15
+#define BUTTON_STATE_ACTIVE   0
+
+const ioport_pin_cfg_t board_pin_cfg[] = {
+    {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
+    {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
+    // USB D+, D-, VBus
+    {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+    {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+    {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..c2b23b16c
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,77 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+
+#define RA_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (RA_NOT_DEFINED) != (2)
+#define BSP_CFG_RTOS (2)
+#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+  #define BSP_CFG_RTOS (1)
+#else
+  #define BSP_CFG_RTOS (0)
+#endif
+#endif
+
+#ifndef BSP_CFG_RTC_USED
+#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+#endif
+
+#undef RA_NOT_DEFINED
+#if defined(_RA_BOOT_IMAGE)
+  #define BSP_CFG_BOOT_IMAGE (1)
+#endif
+
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x400)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT     ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+#endif
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+#endif
+
+#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
+#define BSP_FEATURE_TFU_SUPPORTED 0
+#define BSP_TZ_SECURE_BUILD    (0)
+#define BSP_TZ_NONSECURE_BUILD (0)
+
+#define BSP_CFG_USE_LOW_VOLTAGE_MODE 0
+
+// for SystemInit()
+void bsp_init(void * p_args);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h
new file mode 100644
index 000000000..1cdfae949
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h
@@ -0,0 +1,23 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..bd6a901c3
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (6)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..40bb3a3bf
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M1AD3CFP
+#define BSP_MCU_FEATURE_SET ('A')
+#define BSP_ROM_SIZE_BYTES (524288)
+#define BSP_RAM_SIZE_BYTES (262144)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (100)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..5fedd754f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,84 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA6M1 (1)
+#define BSP_LOCO_HZ                 (32768)
+#define BSP_MOCO_HZ                 (8000000)
+#define BSP_SUB_CLOCK_HZ            (32768)
+#if   BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ                 (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+  #define BSP_HOCO_HZ                 (18000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+  #define BSP_HOCO_HZ                 (20000000)
+#else
+  #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+
+#define BSP_CFG_FLL_ENABLE                 (0)
+
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) |  (1 << 8))
+#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF)
+#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+/*
+ ID Code
+ Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+ WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+ */
+#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+  #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+  #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+  #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+  #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+#else
+  /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+  #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+  #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+  #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+  #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 000000000..95ceca3e2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,16 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..cb7c07932
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,7 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/vector_data.h
new file mode 100644
index 000000000..37739c12a
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/vector_data.h
@@ -0,0 +1,5 @@
+/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
+#define TU_IRQn 0
+#define USBFS_RESUME_IRQn 1
+#define USBFS_FIFO_0_IRQn 2
+#define USBFS_FIFO_1_IRQn 3

From 54dc699ddd4ff0c9ac4595ff752a97861dd434dc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 1 Jul 2023 17:43:06 +0700
Subject: [PATCH 1862/2085] forgot board.mk for ra6m1

---
 hw/bsp/ra/boards/ra4m1_ek/board.mk | 1 -
 hw/bsp/ra/boards/ra4m3_ek/board.mk | 1 -
 hw/bsp/ra/boards/ra6m1_ek/board.mk | 7 +++++++
 3 files changed, 7 insertions(+), 2 deletions(-)
 create mode 100644 hw/bsp/ra/boards/ra6m1_ek/board.mk

diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.mk b/hw/bsp/ra/boards/ra4m1_ek/board.mk
index a06d75ef3..f257c0000 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.mk
@@ -3,6 +3,5 @@ MCU_VARIANT = ra4m1
 
 # For flash-jlink target
 JLINK_DEVICE = R7FA4M1AB
-JLINK_IF     = SWD
 
 flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.mk b/hw/bsp/ra/boards/ra4m3_ek/board.mk
index f2d0ecfc5..5987269b5 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.mk
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.mk
@@ -3,6 +3,5 @@ MCU_VARIANT = ra4m3
 
 # For flash-jlink target
 JLINK_DEVICE = R7FA4M3AF
-JLINK_IF     = SWD
 
 flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.mk b/hw/bsp/ra/boards/ra6m1_ek/board.mk
new file mode 100644
index 000000000..f06b693d8
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.mk
@@ -0,0 +1,7 @@
+CPU_CORE = cortex-m4
+MCU_VARIANT = ra6m1
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA6M1AD
+
+flash: flash-jlink

From e7431f54f207b8563f2d8dba3384dba243d55bf4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 1 Jul 2023 17:46:21 +0700
Subject: [PATCH 1863/2085] fix undef with fsp

---
 src/portable/renesas/rusb2/rusb2_ra.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index be0a9fa66..df4afdfa0 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -34,6 +34,7 @@ extern "C" {
 #ifdef __GNUC__
 #pragma GCC diagnostic push
 #pragma GCC diagnostic ignored "-Wstrict-prototypes"
+#pragma GCC diagnostic ignored "-Wundef"
 
 // extra push due to https://github.com/renesas/fsp/pull/278
 #pragma GCC diagnostic push

From 14f1123bbdb221a1ff755ca64061ec72b8baca67 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 1 Jul 2023 17:55:36 +0700
Subject: [PATCH 1864/2085] remove left-over build_arm

---
 .github/workflows/build_arm.yml | 84 ---------------------------------
 1 file changed, 84 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 0b770f379..72ddf164b 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -67,12 +67,6 @@ jobs:
          repository: hathach/linkermap
          path: linkermap
 
-    - name: Checkout pico-sdk for rp2040
-      if: matrix.family == 'rp2040'
-      run: |
-        git clone --depth 1 -b develop https://github.com/raspberrypi/pico-sdk ~/pico-sdk
-        echo >> $GITHUB_ENV PICO_SDK_PATH=~/pico-sdk
-
     - name: Get Dependencies
       run: python3 tools/get_deps.py ${{ matrix.family }}
 
@@ -87,81 +81,3 @@ jobs:
         do
           find ${ex} -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
         done
-
-    # Upload binaries for hardware test with self-hosted
-    - name: Prepare stm32l412nucleo Artifacts
-      if: contains(matrix.family, 'stm32l4')
-      run: find examples/ -path "*stm32l412nucleo/*.elf" -exec mv {} . \;
-
-    - name: Upload Artifacts for stm32l412nucleo
-      if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach'
-      uses: actions/upload-artifact@v3
-      with:
-        name: stm32l4
-        path: |
-          *.elf
-
-#  # ---------------------------------------
-#  # Hardware in the loop (HIL)
-#  # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
-#  # - STM32L412 Nucleo with on-board jlink as ttyACM0
-#  # ---------------------------------------
-#  hw-stm32l412nucleo-test:
-#    needs: build-arm
-#    runs-on: [self-hosted, Linux, X64, hifiphile]
-#
-#    steps:
-#    - name: Clean workspace
-#      run: |
-#        echo "Cleaning up previous run"
-#        rm -rf "${{ github.workspace }}"
-#        mkdir -p "${{ github.workspace }}"
-#
-#    - name: Download stm32l4 Artifacts
-#      uses: actions/download-artifact@v3
-#      with:
-#        name: stm32l4
-#
-#    - name: Create flash.sh
-#      run: |
-#        echo > flash.sh 'echo halt > flash.jlink'
-#        echo >> flash.sh 'echo r >> flash.jlink'
-#        echo >> flash.sh 'echo loadfile $1 >> flash.jlink'
-#        echo >> flash.sh 'echo r >> flash.jlink'
-#        echo >> flash.sh 'echo go >> flash.jlink'
-#        echo >> flash.sh 'echo exit >> flash.jlink'
-#        echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
-#        echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
-#        chmod +x flash.sh
-#
-#    - name: Test cdc_dual_ports
-#      run: |
-#        ./flash.sh cdc_dual_ports.elf
-#        while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
-#        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-#        test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-#
-#      # Debian does not auto mount usb drive. skip this test for now
-#    - name: Test cdc_msc
-#      if: false
-#      run: |
-#        ./flash.sh cdc_msc.elf
-#        readme='/media/pi/TinyUSB MSC/README.TXT'
-#        while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
-#        test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-#        test -f "$readme" && echo "$readme exists"
-#        cat "$readme"
-#
-#    - name: Test dfu
-#      run: |
-#        ./flash.sh dfu.elf
-#        while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
-#        dfu-util -d cafe -a 0 -U dfu0
-#        dfu-util -d cafe -a 1 -U dfu1
-#        grep "TinyUSB DFU! - Partition 0" dfu0
-#        grep "TinyUSB DFU! - Partition 1" dfu1
-#
-#    - name: Test dfu_runtime
-#      run: |
-#        ./flash.sh dfu_runtime.elf
-#        while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done

From 7d45a43f57c805f3d7b48638aee2e997bff08b96 Mon Sep 17 00:00:00 2001
From: Andrew Hooper <ahooper@kos.net>
Date: Sat, 1 Jul 2023 07:59:39 -0400
Subject: [PATCH 1865/2085] Correct loader file

---
 hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk
index a184804d3..2593978ec 100644
--- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk
@@ -2,7 +2,7 @@ CFLAGS += -DSTM32F407xx
 
 # GCC
 GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s
-GCC_LD_FILE = $(BOARD_PATH)/STM32F407VGTx_FLASH.ld
+GCC_LD_FILE = $(BOARD_PATH)/STM32F407VETX_FLASH.ld
 
 # IAR
 IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s

From ec02ddf9863ee6e1b7a464d73b6cce205c772f43 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 1 Jul 2023 21:43:52 +0700
Subject: [PATCH 1866/2085] initial ra6m5 ek, board_test led + sw works

---
 hw/bsp/ra/boards/ra4m1_ek/board.cmake         |   6 +-
 hw/bsp/ra/boards/ra4m3_ek/board.cmake         |   6 +-
 hw/bsp/ra/boards/ra6m1_ek/board.cmake         |   9 +-
 .../boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h |  16 -
 hw/bsp/ra/boards/ra6m5_ek/board.cmake         |  10 +
 hw/bsp/ra/boards/ra6m5_ek/board.h             |  52 +++
 hw/bsp/ra/boards/ra6m5_ek/board.mk            |   7 +
 .../ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h  |  65 +++
 .../ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h |   5 +
 .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h       |  11 +
 .../ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 387 ++++++++++++++++++
 .../boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h   |  35 ++
 .../ra/boards/ra6m5_ek/fsp_cfg/r_ioport_cfg.h |   7 +
 .../ra/boards/ra6m5_ek/fsp_cfg/vector_data.h  |   5 +
 hw/bsp/ra/family.cmake                        |   1 +
 hw/bsp/ra/linker/gcc/ra6m5.ld                 |  22 +
 16 files changed, 616 insertions(+), 28 deletions(-)
 delete mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/board.cmake
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/board.h
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/board.mk
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/r_ioport_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/vector_data.h
 create mode 100644 hw/bsp/ra/linker/gcc/ra6m5.ld

diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.cmake b/hw/bsp/ra/boards/ra4m1_ek/board.cmake
index 51c1f3d6c..4188d3188 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.cmake
@@ -4,7 +4,7 @@ set(MCU_VARIANT ra4m1)
 set(JLINK_DEVICE R7FA4M1AB)
 
 function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC)
-  target_sources(${TARGET} PRIVATE)
-  target_include_directories(${BOARD_TARGET} PUBLIC)
+#  target_compile_definitions(${TARGET} PUBLIC)
+#  target_sources(${TARGET} PRIVATE)
+#  target_include_directories(${BOARD_TARGET} PUBLIC)
 endfunction()
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.cmake b/hw/bsp/ra/boards/ra4m3_ek/board.cmake
index 637e99db6..dfd5fc95a 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.cmake
@@ -4,7 +4,7 @@ set(MCU_VARIANT ra4m3)
 set(JLINK_DEVICE R7FA4M3AF)
 
 function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC)
-  target_sources(${TARGET} PRIVATE)
-  target_include_directories(${BOARD_TARGET} PUBLIC)
+#  target_compile_definitions(${TARGET} PUBLIC)
+#  target_sources(${TARGET} PRIVATE)
+#  target_include_directories(${BOARD_TARGET} PUBLIC)
 endfunction()
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.cmake b/hw/bsp/ra/boards/ra6m1_ek/board.cmake
index 0d599b2da..b2f41a354 100644
--- a/hw/bsp/ra/boards/ra6m1_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.cmake
@@ -4,10 +4,7 @@ set(MCU_VARIANT ra6m1)
 set(JLINK_DEVICE R7FA6M1AD)
 
 function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    )
-  target_sources(${TARGET} PRIVATE
-    )
-  target_include_directories(${BOARD_TARGET} PUBLIC
-    )
+#  target_compile_definitions(${TARGET} PUBLIC)
+#  target_sources(${TARGET} PRIVATE)
+#  target_include_directories(${BOARD_TARGET} PUBLIC)
 endfunction()
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h
deleted file mode 100644
index 95ceca3e2..000000000
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_PIN_CFG_H_
-#define BSP_PIN_CFG_H_
-#include "r_ioport.h"
-
-/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
-FSP_HEADER
-
-extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */
-
-void BSP_PinConfigSecurityInit();
-
-/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
-FSP_FOOTER
-
-#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
new file mode 100644
index 000000000..42a4c7417
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
@@ -0,0 +1,10 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra6m5)
+
+set(JLINK_DEVICE R7FA6M5BH)
+
+function(update_board TARGET)
+#  target_compile_definitions(${TARGET} PUBLIC)
+#  target_sources(${TARGET} PRIVATE)
+#  target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h
new file mode 100644
index 000000000..4a1527f93
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.h
@@ -0,0 +1,52 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1                  BSP_IO_PORT_00_PIN_08
+#define LED_STATE_ON          1
+
+#define SW1                   BSP_IO_PORT_00_PIN_05
+#define BUTTON_STATE_ACTIVE   0
+
+const ioport_pin_cfg_t board_pin_cfg[] = {
+  {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
+  {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
+  {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk
new file mode 100644
index 000000000..567908b63
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk
@@ -0,0 +1,7 @@
+CPU_CORE = cortex-m33
+MCU_VARIANT = ra6m5
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA6M5BH
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..e41f603ad
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,65 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+
+#define RA_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (RA_NOT_DEFINED) != (2)
+#define BSP_CFG_RTOS (2)
+#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+  #define BSP_CFG_RTOS (1)
+#else
+  #define BSP_CFG_RTOS (0)
+#endif
+#endif
+#ifndef BSP_CFG_RTC_USED
+#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+#endif
+#undef RA_NOT_DEFINED
+#if defined(_RA_BOOT_IMAGE)
+  #define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x400)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT     ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+#endif
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+#endif
+
+// for SystemInit()
+void bsp_init(void * p_args);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..bd6a901c3
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (6)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..6845183db
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M5BH3CFC
+#define BSP_MCU_FEATURE_SET ('B')
+#define BSP_ROM_SIZE_BYTES (2097152)
+#define BSP_RAM_SIZE_BYTES (524288)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (176)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..d5428540f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,387 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA6M5 (1)
+#define BSP_LOCO_HZ                 (32768)
+#define BSP_MOCO_HZ                 (8000000)
+#define BSP_SUB_CLOCK_HZ            (32768)
+#if   BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ                 (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+  #define BSP_HOCO_HZ                 (18000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+  #define BSP_HOCO_HZ                 (20000000)
+#else
+  #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+
+#define BSP_CFG_FLL_ENABLE                 (0)
+
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
+
+#if defined(_RA_TZ_SECURE)
+            #define BSP_TZ_SECURE_BUILD           (1)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #elif defined(_RA_TZ_NONSECURE)
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (1)
+            #else
+#define BSP_TZ_SECURE_BUILD           (0)
+#define BSP_TZ_NONSECURE_BUILD        (0)
+#endif
+
+/* TrustZone Settings */
+#define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+#define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+#define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
+
+/* CMSIS TrustZone Settings */
+#define SCB_CSR_AIRCR_INIT                (1)
+#define SCB_AIRCR_BFHFNMINS_VAL           (0)
+#define SCB_AIRCR_SYSRESETREQS_VAL        (1)
+#define SCB_AIRCR_PRIS_VAL                (0)
+#define TZ_FPU_NS_USAGE                   (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+#define SCB_NSACR_CP10_11_VAL             (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+#define FPU_FPCCR_TS_VAL                  (1U)
+#endif
+#define FPU_FPCCR_CLRONRETS_VAL           (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+#define FPU_FPCCR_CLRONRET_VAL            (1)
+#endif
+
+/* The C-Cache line size that is configured during startup. */
+#ifndef BSP_CFG_C_CACHE_LINE_SIZE
+#define BSP_CFG_C_CACHE_LINE_SIZE   (1U)
+#endif
+
+/* Type 1 Peripheral Security Attribution */
+
+/* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+            (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
+            0x33f4f9) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
+            0x7fffcef4) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+            0xffae07f0) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+            0x3f3ff8) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+            0xfffffffc) /* Unused */
+#endif
+
+/* Type 2 Peripheral Security Attribution */
+
+/* Security attribution for Cache registers. */
+#ifndef BSP_TZ_CFG_CSAR
+#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+#define BSP_TZ_CFG_LVDSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+            0xFFFFFFFCU)
+#endif
+
+/* Security attribution for LPM registers. */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+#endif
+/* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
+#endif
+#endif
+
+/* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+#endif
+
+/* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
+            0xFFFF0000U)
+#endif
+
+/* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+/* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_ICUSARC
+#define BSP_TZ_CFG_ICUSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
+            0xFFFFFF00U)
+#endif
+
+/* Security attribution registers for SELSR0. */
+#ifndef BSP_TZ_CFG_ICUSARD
+#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+#endif
+
+/* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+#define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+/* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
+#define BSP_TZ_CFG_FSAR (0xFEFEU)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_FSAR (0xFFFFU)
+#endif
+#endif
+
+/* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+#define BSP_TZ_CFG_SRAMSAR (\
+        1 | \
+        ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
+        4 | \
+        0xFFFFFFF8U)
+#endif
+
+/* Security attribution for Standby RAM registers. */
+#ifndef BSP_TZ_CFG_STBRAMSAR
+#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+#endif
+
+/* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+#endif
+
+/* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+#endif
+/* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+#endif
+
+/* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+/* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+#else
+#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+#endif
+#endif
+
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) |  (1 << 8))
+
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+/* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+#endif
+
+/* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+/* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+/* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+#endif
+/* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+#endif
+/* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+/* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+/* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+#endif
+/* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+#endif
+/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+#endif
+/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..77ac41d0a
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,35 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
+#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */
+#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
+#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */
+#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
+#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
+#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 000000000..cb7c07932
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,7 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/vector_data.h
new file mode 100644
index 000000000..37739c12a
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/vector_data.h
@@ -0,0 +1,5 @@
+/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
+#define TU_IRQn 0
+#define USBFS_RESUME_IRQn 1
+#define USBFS_FIFO_0_IRQn 2
+#define USBFS_FIFO_1_IRQn 3
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index cf7dfad55..f93880dff 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -55,6 +55,7 @@ function(add_board_target BOARD_TARGET)
       ${FSP_RA}/inc/api
       ${FSP_RA}/inc/instances
       ${FSP_RA}/src/bsp/cmsis/Device/RENESAS/Include
+      ${FSP_RA}/src/bsp/mcu/all
       ${FSP_RA}/src/bsp/mcu/${MCU_VARIANT}
       )
 
diff --git a/hw/bsp/ra/linker/gcc/ra6m5.ld b/hw/bsp/ra/linker/gcc/ra6m5.ld
new file mode 100644
index 000000000..af747fd9b
--- /dev/null
+++ b/hw/bsp/ra/linker/gcc/ra6m5.ld
@@ -0,0 +1,22 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x80000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x200000;
+DATA_FLASH_START = 0x08000000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x0100A100;
+OPTION_SETTING_LENGTH = 0x100;
+OPTION_SETTING_S_START = 0x0100A200;
+OPTION_SETTING_S_LENGTH = 0x100;
+ID_CODE_START = 0x00000000;
+ID_CODE_LENGTH = 0x0;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x4000000;
+OSPI_DEVICE_0_START = 0x68000000;
+OSPI_DEVICE_0_LENGTH = 0x8000000;
+OSPI_DEVICE_1_START = 0x70000000;
+OSPI_DEVICE_1_LENGTH = 0x10000000;
+
+INCLUDE fsp.ld

From 0693462ebad20338de78aeb93d60d6c3c73a6ca7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Lars=20P=C3=B6tter?= <kontakt@ing-poetter.de>
Date: Sun, 2 Jul 2023 09:02:24 +0200
Subject: [PATCH 1867/2085] made line ends consistent.

---
 src/class/cdc/cdc_host.c                     |  4 +--
 src/class/video/video_device.c               | 16 +++++-----
 src/common/tusb_fifo.c                       |  2 +-
 src/portable/dialog/da146xx/dcd_da146xx.c    |  2 +-
 src/portable/mentor/musb/dcd_musb.c          | 30 +++++++++---------
 src/portable/mentor/musb/hcd_musb.c          |  8 ++---
 src/portable/nxp/khci/hcd_khci.c             | 16 +++++-----
 src/portable/raspberrypi/rp2040/hcd_rp2040.c |  4 +--
 src/portable/raspberrypi/rp2040/rp2040_usb.c |  4 +--
 src/portable/renesas/rusb2/hcd_rusb2.c       |  8 ++---
 src/portable/st/typec/typec_stm32.c          | 18 +++++------
 src/portable/sunxi/dcd_sunxi_musb.c          | 32 ++++++++++----------
 12 files changed, 72 insertions(+), 72 deletions(-)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index ce9f27c33..e1af8d801 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -973,7 +973,7 @@ static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud)
 static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
   uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate);
-  TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\n", baudrate, divisor);
+  TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor);
 
   p_cdc->user_control_cb = complete_cb;
   _ftdi_requested_baud = baudrate;
@@ -1108,7 +1108,7 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe
 }
 
 static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
-  TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\n", baudrate);
+  TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\r\n", baudrate);
   uint32_t baud_le = tu_htole32(baudrate);
   p_cdc->user_control_cb = complete_cb;
   return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4,
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 91f452afc..16eae0ced 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -609,17 +609,17 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
  * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum)
 {
-  TU_LOG2("    open VC %d\n", altnum);
+  TU_LOG2("    open VC %d\r\n", altnum);
   uint8_t const *beg = self->beg;
   uint8_t const *end = beg + self->len;
 
   /* The first descriptor is a video control interface descriptor. */
   uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
-  TU_LOG2("    cur %d\n", cur - beg);
+  TU_LOG2("    cur %d\r\n", cur - beg);
   TU_VERIFY(cur < end);
 
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
-  TU_LOG2("    bInCollection %d\n", vc->ctl.bInCollection);
+  TU_LOG2("    bInCollection %d\r\n", vc->ctl.bInCollection);
   /* Support for up to 2 streaming interfaces only. */
   TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING);
 
@@ -628,7 +628,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
 
   /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
   cur += vc->std.bLength + vc->ctl.bLength;
-  TU_LOG2("    bNumEndpoints %d\n", vc->std.bNumEndpoints);
+  TU_LOG2("    bNumEndpoints %d\r\n", vc->std.bNumEndpoints);
   /* Open the notification endpoint if it exist. */
   if (vc->std.bNumEndpoints) {
     /* Support for 1 endpoint only. */
@@ -662,7 +662,7 @@ static bool _init_vs_configuration(videod_streaming_interface_t *stm)
 static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum)
 {
   uint_fast8_t i;
-  TU_LOG2("    reopen VS %d\n", altnum);
+  TU_LOG2("    reopen VS %d\r\n", altnum);
   uint8_t const *desc = _videod_itf[stm->index_vc].beg;
 
   /* Close endpoints of previous settings. */
@@ -672,7 +672,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     uint8_t  ep_adr = _desc_ep_addr(desc + ofs_ep);
     usbd_edpt_close(rhport, ep_adr);
     stm->desc.ep[i] = 0;
-    TU_LOG2("    close EP%02x\n", ep_adr);
+    TU_LOG2("    close EP%02x\r\n", ep_adr);
   }
 
   /* clear transfer management information */
@@ -709,12 +709,12 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     }
     TU_ASSERT(usbd_edpt_open(rhport, ep));
     stm->desc.ep[i] = (uint16_t) (cur - desc);
-    TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
+    TU_LOG2("    open EP%02x\r\n", _desc_ep_addr(cur));
   }
   if (altnum) {
     stm->state = VS_STATE_STREAMING;
   }
-  TU_LOG2("    done\n");
+  TU_LOG2("    done\r\n");
   return true;
 }
 
diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c
index a52c92267..d6c3db4ce 100644
--- a/src/common/tusb_fifo.c
+++ b/src/common/tusb_fifo.c
@@ -539,7 +539,7 @@ static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu
     // Advance index
     f->wr_idx = advance_index(f->depth, wr_idx, n);
 
-    TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\n", f->wr_idx);
+    TU_LOG(TU_FIFO_DBG, "\tnew_wr = %u\r\n", f->wr_idx);
   }
 
   _ff_unlock(f->mutex_wr);
diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c
index 961da81d6..d1e85c2df 100644
--- a/src/portable/dialog/da146xx/dcd_da146xx.c
+++ b/src/portable/dialog/da146xx/dcd_da146xx.c
@@ -651,7 +651,7 @@ static void handle_epx_tx_ev(xfer_ctl_t *xfer)
   }
   if (txs & USB_USB_TXS1_REG_USB_TX_URUN_Msk)
   {
-    TU_LOG1("EP %d FIFO underrun\n", epnum);
+    TU_LOG1("EP %d FIFO underrun\r\n", epnum);
   }
   // Start next or repeated packet.
   start_tx_packet(xfer);
diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c
index 487761847..3c0114e41 100644
--- a/src/portable/mentor/musb/dcd_musb.c
+++ b/src/portable/mentor/musb/dcd_musb.c
@@ -317,7 +317,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
   const unsigned mps = regs->TXMAXP;
   const unsigned len = TU_MIN(mps, rem);
   void          *buf = pipe->buf;
-  // TU_LOG1("   %p mps %d len %d rem %d\n", buf, mps, len, rem);
+  // TU_LOG1("   %p mps %d len %d rem %d\r\n", buf, mps, len, rem);
   if (len) {
     if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
       pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_IN);
@@ -328,7 +328,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
     pipe->remaining = rem - len;
   }
   regs->TXCSRL = USB_TXCSRL1_TXRDY;
-  // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
+  // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
   return false;
 }
 
@@ -337,7 +337,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
   unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
   pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
   volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1);
-  // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL);
+  // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL);
 
   TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY);
 
@@ -399,14 +399,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
      * may have already finished and received the next setup packet
      * without calling this function, so we have no choice but to
      * invoke the callback function of status packet here. */
-    // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\n", USB0->CSRL0);
+    // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0);
     _dcd.status_out = 0;
     if (req == REQUEST_TYPE_INVALID) {
       dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
     } else {
       /* The next setup packet has already been received, it aborts
        * invoking callback function to avoid confusing TUSB stack. */
-      TU_LOG1("Drop CONTROL_STAGE_ACK\n");
+      TU_LOG1("Drop CONTROL_STAGE_ACK\r\n");
     }
     return true;
   }
@@ -431,16 +431,16 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
       } else {
         USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */
       }
-      // TU_LOG1(" IN USB0->CSRL0 = %x\n", USB0->CSRL0);
+      // TU_LOG1(" IN USB0->CSRL0 = %x\r\n", USB0->CSRL0);
     } else {
-      // TU_LOG1(" OUT USB0->CSRL0 = %x\n", USB0->CSRL0);
+      // TU_LOG1(" OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0);
       _dcd.pipe0.buf       = buffer;
       _dcd.pipe0.length    = len;
       _dcd.pipe0.remaining = len;
       USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */
     }
   } else if (dir_in) {
-    // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\n", USB0->CSRL0);
+    // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\r\n", USB0->CSRL0);
     _dcd.pipe0.buf = NULL;
     _dcd.pipe0.length    = 0;
     _dcd.pipe0.remaining = 0;
@@ -454,7 +454,7 @@ static void process_ep0(uint8_t rhport)
 {
   uint_fast8_t csrl = USB0->CSRL0;
 
-  // TU_LOG1(" EP0 USB0->CSRL0 = %x\n", csrl);
+  // TU_LOG1(" EP0 USB0->CSRL0 = %x\r\n", csrl);
 
   if (csrl & USB_CSRL0_STALLED) {
     /* Returned STALL packet to HOST. */
@@ -464,7 +464,7 @@ static void process_ep0(uint8_t rhport)
 
   unsigned req = _dcd.setup_packet.bmRequestType;
   if (csrl & USB_CSRL0_SETEND) {
-    TU_LOG1("   ABORT by the next packets\n");
+    TU_LOG1("   ABORT by the next packets\r\n");
     USB0->CSRL0 = USB_CSRL0_SETENDC;
     if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
       /* DATA stage was aborted by receiving STATUS or SETUP packet. */
@@ -539,14 +539,14 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
 
   volatile hw_endpoint_t *regs = edpt_regs(epn_minus1);
   if (dir_in) {
-    // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL);
+    // TU_LOG1(" TXCSRL%d = %x\r\n", epn_minus1 + 1, regs->TXCSRL);
     if (regs->TXCSRL & USB_TXCSRL1_STALLED) {
       regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN);
       return;
     }
     completed = handle_xfer_in(ep_addr);
   } else {
-    // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL);
+    // TU_LOG1(" RXCSRL%d = %x\r\n", epn_minus1 + 1, regs->RXCSRL);
     if (regs->RXCSRL & USB_RXCSRL1_STALLED) {
       regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER);
       return;
@@ -789,7 +789,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
   NVIC_DisableIRQ(USB0_IRQn);
@@ -807,7 +807,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   TU_ASSERT(epnum);
   unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn);
@@ -869,7 +869,7 @@ void dcd_int_handler(uint8_t rhport)
   is   = USB0->IS;   /* read and clear interrupt status */
   txis = USB0->TXIS; /* read and clear interrupt status */
   rxis = USB0->RXIS; /* read and clear interrupt status */
-  // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis);
+  // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis);
 
   is &= USB0->IE; /* Clear disabled interrupts */
   if (is & USB_IS_DISCON) {
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 9eb2e005e..7e67b8291 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -418,7 +418,7 @@ static void process_ep0(uint8_t rhport)
   (void)rhport;
 
   uint_fast8_t csrl = USB0->CSRL0;
-  // TU_LOG1(" EP0 CSRL = %x\n", csrl);
+  // TU_LOG1(" EP0 CSRL = %x\r\n", csrl);
 
   unsigned const dev_addr = USB0->TXFUNCADDR0;
   unsigned const req = _hcd.bmRequestType;
@@ -508,7 +508,7 @@ static void process_pipe_tx(uint8_t rhport, uint_fast8_t pipenum)
 
   volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
   unsigned const csrl = regs->TXCSRL;
-  // TU_LOG1(" TXCSRL%d = %x\n", pipenum, csrl);
+  // TU_LOG1(" TXCSRL%d = %x\r\n", pipenum, csrl);
   if (csrl & (USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) {
     if (csrl & USB_TXCSRL1_TXRDY)
       regs->TXCSRL = (csrl & ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_ERROR)) | USB_TXCSRL1_FLUSH;
@@ -537,7 +537,7 @@ static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum)
 
   volatile hw_endpoint_t *regs = edpt_regs(pipenum - 1);
   unsigned const csrl = regs->RXCSRL;
-  // TU_LOG1(" RXCSRL%d = %x\n", pipenum, csrl);
+  // TU_LOG1(" RXCSRL%d = %x\r\n", pipenum, csrl);
   if (csrl & (USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) {
     if (csrl & USB_RXCSRL1_RXRDY)
       regs->RXCSRL = (csrl & ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_ERROR)) | USB_RXCSRL1_FLUSH;
@@ -846,7 +846,7 @@ void hcd_int_handler(uint8_t rhport)
   is   = USB0->IS;   /* read and clear interrupt status */
   txis = USB0->TXIS; /* read and clear interrupt status */
   rxis = USB0->RXIS; /* read and clear interrupt status */
-  // TU_LOG1("D%2x T%2x R%2x\n", is, txis, rxis);
+  // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis);
 
   is &= USB0->IE; /* Clear disabled interrupts */
   if (is & USB_IS_RESUME) {
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index f6029ee0d..fb978cac8 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -161,7 +161,7 @@ static int prepare_packets(int pipenum)
   buffer_descriptor_t *bd = _hcd.bdt[dir_tx];
   TU_ASSERT(0 == bd[odd].own, -1);
 
-  // TU_LOG1("  %p dir %d odd %d data %d\n", &bd[odd], dir_tx, odd, pipe->data);
+  // TU_LOG1("  %p dir %d odd %d data %d\r\n", &bd[odd], dir_tx, odd, pipe->data);
 
   ep->pipenum = pipenum;
 
@@ -251,7 +251,7 @@ static bool resume_transfer(int pipenum)
     flags |= USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPCTLDIS_MASK | USB_ENDPT_RETRYDIS_MASK;
     break;
   }
-  // TU_LOG1("  resume pipenum %d flags %x\n", pipenum, flags);
+  // TU_LOG1("  resume pipenum %d flags %x\r\n", pipenum, flags);
 
   KHCI->ENDPOINT[0].ENDPT = flags;
   KHCI->ADDR  = (KHCI->ADDR & USB_ADDR_LSEN_MASK) | pipe->dev_addr;
@@ -302,7 +302,7 @@ static void process_tokdne(uint8_t rhport)
 
   int pipenum = ep->pipenum;
   int next_pipenum;
-  // TU_LOG1("TOKDNE %x PID %x pipe %d\n", s, pid, pipenum);
+  // TU_LOG1("TOKDNE %x PID %x pipe %d\r\n", s, pid, pipenum);
 
   xfer_result_t result;
   switch (pid) {
@@ -479,7 +479,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void)rhport;
-  // TU_LOG1("SETUP %u\n", dev_addr);
+  // TU_LOG1("SETUP %u\r\n", dev_addr);
   TU_ASSERT(0 == (_hcd.in_progress & TU_BIT(0)));
 
   int pipenum = find_pipe(dev_addr, 0);
@@ -510,7 +510,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 {
   (void)rhport;
   uint8_t const ep_addr = ep_desc->bEndpointAddress;
-  // TU_LOG1("O %u %x\n", dev_addr, ep_addr);
+  // TU_LOG1("O %u %x\r\n", dev_addr, ep_addr);
   /* Find a free pipe */
   pipe_state_t *p = &_hcd.pipe[0];
   pipe_state_t *end = &_hcd.pipe[CFG_TUH_ENDPOINT_MAX * 2];
@@ -543,7 +543,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
 {
   (void)rhport;
-  // TU_LOG1("X %u %x %x %d\n", dev_addr, ep_addr, (uintptr_t)buffer, buflen);
+  // TU_LOG1("X %u %x %x %d\r\n", dev_addr, ep_addr, (uintptr_t)buffer, buflen);
 
   int pipenum = find_pipe(dev_addr, ep_addr);
   TU_ASSERT(0 <= pipenum);
@@ -580,7 +580,7 @@ void hcd_int_handler(uint8_t rhport)
   uint32_t is  = KHCI->ISTAT;
   uint32_t msk = KHCI->INTEN;
 
-  // TU_LOG1("S %lx\n", is);
+  // TU_LOG1("S %lx\r\n", is);
 
   /* clear disabled interrupts */
   KHCI->ISTAT = (is & ~msk & ~USB_ISTAT_TOKDNE_MASK) | USB_ISTAT_SOFTOK_MASK;
@@ -589,7 +589,7 @@ void hcd_int_handler(uint8_t rhport)
   if (is & USB_ISTAT_ERROR_MASK) {
     unsigned err = KHCI->ERRSTAT;
     if (err) {
-      TU_LOG1(" ERR %x\n", err);
+      TU_LOG1(" ERR %x\r\n", err);
       KHCI->ERRSTAT = err;
     } else {
       KHCI->INTEN &= ~USB_ISTAT_ERROR_MASK;
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 02f9968a7..51b8bf72d 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -219,7 +219,7 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
   if ( status & USB_INTS_BUFF_STATUS_BITS )
   {
     handled |= USB_INTS_BUFF_STATUS_BITS;
-    TU_LOG(2, "Buffer complete\n");
+    TU_LOG(2, "Buffer complete\r\n");
     hw_handle_buff_status();
   }
 
@@ -227,7 +227,7 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
   {
     handled |= USB_INTS_TRANS_COMPLETE_BITS;
     usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
-    TU_LOG(2, "Transfer complete\n");
+    TU_LOG(2, "Transfer complete\r\n");
     hw_trans_complete();
   }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 1f49665ff..53486a586 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -219,7 +219,7 @@ void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t to
   if ( ep->active )
   {
     // TODO: Is this acceptable for interrupt packets?
-    TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\n", tu_edpt_number(ep->ep_addr),
+    TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\r\n", tu_edpt_number(ep->ep_addr),
               ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
 
     hw_endpoint_reset_transfer(ep);
@@ -419,7 +419,7 @@ static bool __tusb_irq_path_func(e15_is_critical_frame_period) (struct hw_endpoi
   if (delta < 800 || delta > 998) {
     return false;
   }
-  TU_LOG(3, "Avoiding sof %lu now %lu last %lu\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof);
+  TU_LOG(3, "Avoiding sof %lu now %lu last %lu\r\n", (usb_hw->sof_rd + 1) & USB_SOF_RD_BITS, time_us_32(), e15_last_sof);
   return true;
 }
 
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 0e6fa1618..886a6f6b8 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -409,7 +409,7 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
   (void)rhport;
   xfer_result_t result;
   uint16_t volatile *ctr = get_pipectr(num);
-  // TU_LOG1("NRDY %d %x\n", num, *ctr);
+  // TU_LOG1("NRDY %d %x\r\n", num, *ctr);
   switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) {
     default: return;
     case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
@@ -608,7 +608,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void)rhport;
-  //  TU_LOG1("S %d %x\n", dev_addr, RUSB2->DCPCTR);
+  //  TU_LOG1("S %d %x\r\n", dev_addr, RUSB2->DCPCTR);
 
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
   TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ);
@@ -701,7 +701,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b
 {
   bool r;
   hcd_int_disable(rhport);
-  // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen);
+  // TU_LOG1("X %d %x %u\r\n", dev_addr, ep_addr, buflen);
   r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen);
   hcd_int_enable(rhport);
   return r;
@@ -745,7 +745,7 @@ void hcd_int_handler(uint8_t rhport)
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
   RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
   RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
-  // TU_LOG1("IS %04x %04x\n", is0, is1);
+  // TU_LOG1("IS %04x %04x\r\n", is0, is1);
   is1 &= RUSB2->INTENB1;
   is0 &= RUSB2->INTENB0;
 
diff --git a/src/portable/st/typec/typec_stm32.c b/src/portable/st/typec/typec_stm32.c
index bf8b660f0..8da2e39ba 100644
--- a/src/portable/st/typec/typec_stm32.c
+++ b/src/portable/st/typec/typec_stm32.c
@@ -246,7 +246,7 @@ void tcd_int_handler(uint8_t rhport) {
     v_cc[0] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC1_Pos) & 0x03;
     v_cc[1] = (UCPD1->SR >> UCPD_SR_TYPEC_VSTATE_CC2_Pos) & 0x03;
 
-    TU_LOG3("VState CC1 = %lu, CC2 = %lu\n", v_cc[0], v_cc[1]);
+    TU_LOG3("VState CC1 = %lu, CC2 = %lu\r\n", v_cc[0], v_cc[1]);
 
     uint32_t cr = UCPD1->CR;
 
@@ -255,15 +255,15 @@ void tcd_int_handler(uint8_t rhport) {
     // FIXME somehow CC2 is vstate is not correct, always 1 even not attached.
     // on DPOW1 board, it is connected to PA10 (USBPD_DBCC2), we probably miss something.
     if ((sr & UCPD_SR_TYPECEVT1) && (v_cc[0] == 3)) {
-      TU_LOG3("Attach CC1\n");
+      TU_LOG3("Attach CC1\r\n");
       cr &= ~(UCPD_CR_PHYCCSEL | UCPD_CR_CCENABLE);
       cr |= UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_0;
     } else if ((sr & UCPD_SR_TYPECEVT2) && (v_cc[1] == 3)) {
-      TU_LOG3("Attach CC2\n");
+      TU_LOG3("Attach CC2\r\n");
       cr &= ~UCPD_CR_CCENABLE;
       cr |= (UCPD_CR_PHYCCSEL | UCPD_CR_PHYRXEN | UCPD_CR_CCENABLE_1);
     } else {
-      TU_LOG3("Detach\n");
+      TU_LOG3("Detach\r\n");
       cr &= ~UCPD_CR_PHYRXEN;
       cr |= UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1;
     }
@@ -290,7 +290,7 @@ void tcd_int_handler(uint8_t rhport) {
   //------------- RX -------------//
   if (sr & UCPD_SR_RXORDDET) {
     // SOP: Start of Packet.
-    TU_LOG3("SOP\n");
+    TU_LOG3("SOP\r\n");
     // UCPD1->RX_ORDSET & UCPD_RX_ORDSET_RXORDSET_Msk;
 
     // ack
@@ -299,7 +299,7 @@ void tcd_int_handler(uint8_t rhport) {
 
   // Received full message
   if (sr & UCPD_SR_RXMSGEND) {
-    TU_LOG3("RX MSG END\n");
+    TU_LOG3("RX MSG END\r\n");
 
     // stop TX
     dma_stop(rhport, true);
@@ -328,7 +328,7 @@ void tcd_int_handler(uint8_t rhport) {
   }
 
   if (sr & UCPD_SR_RXOVR) {
-    TU_LOG3("RXOVR\n");
+    TU_LOG3("RXOVR\r\n");
     // ack
     UCPD1->ICR = UCPD_ICR_RXOVRCF;
   }
@@ -343,12 +343,12 @@ void tcd_int_handler(uint8_t rhport) {
     uint8_t result;
 
     if ( sr & UCPD_SR_TXMSGSENT ) {
-      TU_LOG3("TX MSG SENT\n");
+      TU_LOG3("TX MSG SENT\r\n");
       result = XFER_RESULT_SUCCESS;
       // ack
       UCPD1->ICR = UCPD_ICR_TXMSGSENTCF;
     }else {
-      TU_LOG3("TX Error\n");
+      TU_LOG3("TX Error\r\n");
       result = XFER_RESULT_FAILED;
       // ack
       UCPD1->ICR = UCPD_SR_TXMSGDISC | UCPD_SR_TXMSGABT | UCPD_SR_TXUND;
diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c
index e26be775d..6cc1975a8 100644
--- a/src/portable/sunxi/dcd_sunxi_musb.c
+++ b/src/portable/sunxi/dcd_sunxi_musb.c
@@ -408,9 +408,9 @@ static inline unsigned free_block_size(free_block_t const *blk)
 #if 0
 static inline void print_block_list(free_block_t const *blk, unsigned num)
 {
-  TU_LOG1("*************\n");
+  TU_LOG1("*************\r\n");
   for (unsigned i = 0; i < num; ++i) {
-    TU_LOG1(" Blk%u %u %u\n", i, blk->beg, blk->end);
+    TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end);
     ++blk;
   }
 }
@@ -590,7 +590,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
   const unsigned mps = USBC_Readw(USBC_REG_TXMAXP(USBC0_BASE));
   const unsigned len = TU_MIN(mps, rem);
   uint8_t          *buf = pipe->buf;
-  // TU_LOG1("   %p mps %d len %d rem %d\n", buf, mps, len, rem);
+  // TU_LOG1("   %p mps %d len %d rem %d\r\n", buf, mps, len, rem);
   if (len) {
     volatile void* addr = (volatile void*)(USBC_REG_EPFIFO1(USBC0_BASE) + (epnum_minus1 << 2));
     if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) {
@@ -602,7 +602,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr)
     pipe->remaining = rem - len;
   }
   __USBC_Dev_Tx_WriteDataComplete();
-  // TU_LOG1(" TXCSRL%d = %x %d\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
+  // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum_minus1 + 1, regs->TXCSRL, rem - len);
   return false;
 }
 
@@ -610,7 +610,7 @@ static bool handle_xfer_out(uint_fast8_t ep_addr)
 {
   unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1;
   pipe_state_t  *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1];
-  // TU_LOG1(" RXCSRL%d = %x\n", epnum_minus1 + 1, regs->RXCSRL);
+  // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL);
 
   TU_ASSERT(__USBC_Dev_Rx_IsReadDataReady());
 
@@ -677,14 +677,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
      * may have already finished and received the next setup packet
      * without calling this function, so we have no choice but to
      * invoke the callback function of status packet here. */
-    // TU_LOG1(" STATUS OUT CSRL0 = %x\n", CSRL0);
+    // TU_LOG1(" STATUS OUT CSRL0 = %x\r\n", CSRL0);
     _dcd.status_out = 0;
     if (req == REQUEST_TYPE_INVALID) {
       dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false);
     } else {
       /* The next setup packet has already been received, it aborts
        * invoking callback function to avoid confusing TUSB stack. */
-      TU_LOG1("Drop CONTROL_STAGE_ACK\n");
+      TU_LOG1("Drop CONTROL_STAGE_ACK\r\n");
     }
     return true;
   }
@@ -709,16 +709,16 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_
       } else {
         __USBC_Dev_ep0_WriteDataHalf();
       }
-      // TU_LOG1(" IN CSRL0 = %x\n", CSRL0);
+      // TU_LOG1(" IN CSRL0 = %x\r\n", CSRL0);
     } else {
-      // TU_LOG1(" OUT CSRL0 = %x\n", CSRL0);
+      // TU_LOG1(" OUT CSRL0 = %x\r\n", CSRL0);
       _dcd.pipe0.buf       = buffer;
       _dcd.pipe0.length    = len;
       _dcd.pipe0.remaining = len;
       __USBC_Dev_ep0_ReadDataHalf();
     }
   } else if (dir_in) {
-    // TU_LOG1(" STATUS IN CSRL0 = %x\n", CSRL0);
+    // TU_LOG1(" STATUS IN CSRL0 = %x\r\n", CSRL0);
     _dcd.pipe0.buf = NULL;
     _dcd.pipe0.length    = 0;
     _dcd.pipe0.remaining = 0;
@@ -733,7 +733,7 @@ static void process_ep0(uint8_t rhport)
   USBC_SelectActiveEp(0);
   uint_fast8_t csrl = USBC_Readw(USBC_REG_CSR0(USBC0_BASE));
 
-  // TU_LOG1(" EP0 CSRL0 = %x\n", csrl);
+  // TU_LOG1(" EP0 CSRL0 = %x\r\n", csrl);
 
   if (csrl & USB_CSRL0_STALLED) {
     /* Returned STALL packet to HOST. */
@@ -743,7 +743,7 @@ static void process_ep0(uint8_t rhport)
 
   unsigned req = _dcd.setup_packet.bmRequestType;
   if (csrl & USB_CSRL0_SETEND) {
-    // TU_LOG1("   ABORT by the next packets\n");
+    // TU_LOG1("   ABORT by the next packets\r\n");
     USBC_Dev_Ctrl_ClearSetupEnd();
     if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) {
       /* DATA stage was aborted by receiving STATUS or SETUP packet. */
@@ -819,14 +819,14 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr)
   USBC_SelectActiveEp(epn);
 
   if (dir_in) {
-    // TU_LOG1(" TXCSRL%d = %x\n", epn_minus1 + 1, regs->TXCSRL);
+    // TU_LOG1(" TXCSRL%d = %x\r\n", epn_minus1 + 1, regs->TXCSRL);
     if (__USBC_Dev_Tx_IsEpStall()) {
 	  __USBC_Dev_Tx_ClearStall();
       return;
     }
     completed = handle_xfer_in(ep_addr);
   } else {
-    // TU_LOG1(" RXCSRL%d = %x\n", epn_minus1 + 1, regs->RXCSRL);
+    // TU_LOG1(" RXCSRL%d = %x\r\n", epn_minus1 + 1, regs->RXCSRL);
     if (__USBC_Dev_Rx_IsEpStall()) {
 	    __USBC_Dev_Rx_ClearStall();
       return;
@@ -1092,7 +1092,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   musb_int_mask();
 
@@ -1111,7 +1111,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
 {
   (void)rhport;
   bool ret;
-  // TU_LOG1("X %x %d\n", ep_addr, total_bytes);
+  // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes);
   unsigned const epnum = tu_edpt_number(ep_addr);
   TU_ASSERT(epnum);
 

From 2029ca9536e7e889f0f420218136e7bd1ac091fc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Lars=20P=C3=B6tter?= <kontakt@ing-poetter.de>
Date: Sun, 2 Jul 2023 10:53:08 +0200
Subject: [PATCH 1868/2085] also fixed pico_trac() log messages.

---
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 4 ++--
 src/portable/raspberrypi/rp2040/dcd_rp2040.c   | 6 +++---
 src/portable/raspberrypi/rp2040/rp2040_usb.c   | 4 ++--
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 264af2e7a..130716da4 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -150,11 +150,11 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 //    // so if any transfer is active on epx, we are busy. Interrupt endpoints have their own
 //    // EPX so ep->active will only be busy if there is a pending transfer on that interrupt endpoint
 //    // on that device
-//    pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\n", dev_addr, ep_addr);
+//    pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\r\n", dev_addr, ep_addr);
 //    struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
 //    assert(ep);
 //    bool busy = ep->active;
-//    pico_trace("busy == %d\n", busy);
+//    pico_trace("busy == %d\r\n", busy);
 //    return busy;
 //}
 
diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
index 479b17b67..e8cee73fd 100644
--- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c
@@ -189,7 +189,7 @@ static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_by
 static void __tusb_irq_path_func(hw_handle_buff_status)(void)
 {
     uint32_t remaining_buffers = usb_hw->buf_status;
-    pico_trace("buf_status = 0x%08lx\n", remaining_buffers);
+    pico_trace("buf_status = 0x%08lx\r\n", remaining_buffers);
     uint bit = 1u;
     for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++)
     {
@@ -331,7 +331,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void)
   // SE0 for 2.5 us or more (will last at least 10ms)
   if ( status & USB_INTS_BUS_RESET_BITS )
   {
-    pico_trace("BUS RESET\n");
+    pico_trace("BUS RESET\r\n");
 
     handled |= USB_INTS_BUS_RESET_BITS;
 
@@ -565,7 +565,7 @@ void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
 {
     (void) rhport;
 
-    pico_trace("dcd_edpt_close %02x\n", ep_addr);
+    pico_trace("dcd_edpt_close %02x\r\n", ep_addr);
     hw_endpoint_close(ep_addr);
 }
 
diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c
index 53486a586..a512dc34f 100644
--- a/src/portable/raspberrypi/rp2040/rp2040_usb.c
+++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c
@@ -276,7 +276,7 @@ static uint16_t __tusb_irq_path_func(sync_ep_buffer)(struct hw_endpoint *ep, uin
   // Short packet
   if (xferred_bytes < ep->wMaxPacketSize)
   {
-    pico_trace("  Short packet on buffer %d with %u bytes\n", buf_id, xferred_bytes);
+    pico_trace("  Short packet on buffer %d with %u bytes\r\n", buf_id, xferred_bytes);
     // Reduce total length as this is last packet
     ep->remaining_len = 0;
   }
@@ -352,7 +352,7 @@ bool __tusb_irq_path_func(hw_endpoint_xfer_continue)(struct hw_endpoint *ep)
   // If we are done then notify tinyusb
   if (ep->remaining_len == 0)
   {
-    pico_trace("Completed transfer of %d bytes on ep %d %s\n",
+    pico_trace("Completed transfer of %d bytes on ep %d %s\r\n",
                ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
     // Notify caller we are done so it can notify the tinyusb stack
     hw_endpoint_lock_update(ep, -1);

From 787229a35e20e488b642e879e4f068571e9488df Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 2 Jul 2023 23:39:43 +0700
Subject: [PATCH 1869/2085] add etm trace for 6m5

---
 hw/bsp/ra/boards/ra6m5_ek/board.h            | 19 ++++++++---
 hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug | 35 ++++++++++++++++++++
 hw/bsp/ra/family.c                           |  5 +++
 3 files changed, 54 insertions(+), 5 deletions(-)
 create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug

diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h
index 4a1527f93..9c9bb6dcf 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.h
@@ -38,11 +38,20 @@ extern "C" {
 #define BUTTON_STATE_ACTIVE   0
 
 const ioport_pin_cfg_t board_pin_cfg[] = {
-  {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-  {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
+    { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
+    { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
+    { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
+    { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
+    { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
+
+    #ifdef TRACE_ETM
+    // ETM Trace
+    { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    #endif
 };
 
 #ifdef __cplusplus
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
new file mode 100644
index 000000000..fa55d40b2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
@@ -0,0 +1,35 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Project.AddSvdFile ("Cortex-M33.svd");
+  Project.AddSvdFile ("./R7FA6M5BH.svd");
+
+  Project.SetDevice ("R7FA6M5BH");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf");
+}
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+  //
+  // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+  //
+}
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 82d7a60c5..f7c5e36f9 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -87,6 +87,11 @@ void board_init(void)
   /* Configure pins. */
   R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
 
+#ifdef TRACE_ETM
+  // Enable trace clock with div 1 (100 Mhz)
+  R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk;
+#endif
+
   board_led_write(false);
 
   /* Enable USB_BASE */

From ad7764b5b2f4fc3be3e7da53731559c92784d796 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Jul 2023 10:54:37 +0700
Subject: [PATCH 1870/2085] move vector_data.h and ioport_cfg.h to common
 family

---
 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/r_ioport_cfg.h       | 7 -------
 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h        | 5 -----
 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h       | 7 -------
 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/vector_data.h        | 5 -----
 hw/bsp/ra/{boards/ra4m1_ek/fsp_cfg => }/r_ioport_cfg.h | 0
 hw/bsp/ra/{boards/ra4m1_ek/fsp_cfg => }/vector_data.h  | 0
 6 files changed, 24 deletions(-)
 delete mode 100755 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/r_ioport_cfg.h
 delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h
 delete mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h
 delete mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/vector_data.h
 rename hw/bsp/ra/{boards/ra4m1_ek/fsp_cfg => }/r_ioport_cfg.h (100%)
 rename hw/bsp/ra/{boards/ra4m1_ek/fsp_cfg => }/vector_data.h (100%)

diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/r_ioport_cfg.h
deleted file mode 100755
index cb7c07932..000000000
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/r_ioport_cfg.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_IOPORT_CFG_H_
-#define R_IOPORT_CFG_H_
-
-#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-
-#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h
deleted file mode 100644
index 37739c12a..000000000
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/vector_data.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
-#define TU_IRQn 0
-#define USBFS_RESUME_IRQn 1
-#define USBFS_FIFO_0_IRQn 2
-#define USBFS_FIFO_1_IRQn 3
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h
deleted file mode 100644
index cb7c07932..000000000
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_IOPORT_CFG_H_
-#define R_IOPORT_CFG_H_
-
-#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-
-#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/vector_data.h
deleted file mode 100644
index 37739c12a..000000000
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/vector_data.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
-#define TU_IRQn 0
-#define USBFS_RESUME_IRQn 1
-#define USBFS_FIFO_0_IRQn 2
-#define USBFS_FIFO_1_IRQn 3
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/r_ioport_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/r_ioport_cfg.h
rename to hw/bsp/ra/r_ioport_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/vector_data.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/vector_data.h
rename to hw/bsp/ra/vector_data.h

From 960d9fa6f1a2b4e6c17eda354847acbbb6501d77 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Jul 2023 11:03:50 +0700
Subject: [PATCH 1871/2085] move files around

---
 .../ra4m1_ek/fsp_cfg/{bsp => }/bsp_clock_cfg.h  |  0
 .../ra4m3_ek/fsp_cfg/{bsp => }/bsp_clock_cfg.h  |  0
 .../ra6m1_ek/fsp_cfg/{bsp => }/bsp_clock_cfg.h  |  0
 .../ra/boards/ra6m5_ek/fsp_cfg/r_ioport_cfg.h   |  7 -------
 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/vector_data.h |  5 -----
 hw/bsp/ra/family.c                              | 17 ++++++++++-------
 6 files changed, 10 insertions(+), 19 deletions(-)
 rename hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/{bsp => }/bsp_clock_cfg.h (100%)
 rename hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/{bsp => }/bsp_clock_cfg.h (100%)
 rename hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/{bsp => }/bsp_clock_cfg.h (100%)
 delete mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/r_ioport_cfg.h
 delete mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/vector_data.h

diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/r_ioport_cfg.h
deleted file mode 100644
index cb7c07932..000000000
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/r_ioport_cfg.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef R_IOPORT_CFG_H_
-#define R_IOPORT_CFG_H_
-
-#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
-
-#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/vector_data.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/vector_data.h
deleted file mode 100644
index 37739c12a..000000000
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/vector_data.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
-#define TU_IRQn 0
-#define USBFS_RESUME_IRQn 1
-#define USBFS_FIFO_0_IRQn 2
-#define USBFS_FIFO_1_IRQn 3
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index f7c5e36f9..850498fbb 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -53,7 +53,16 @@
 #define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
 #define BSP_PRV_PRCR_LOCK	       ((BSP_PRV_PRCR_KEY) | 0x0U)
 
-/* ISR prototypes */
+static const ioport_cfg_t family_pin_cfg = {
+    .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
+    .p_pin_cfg_data = board_pin_cfg,
+};
+static ioport_instance_ctrl_t port_ctrl;
+
+//--------------------------------------------------------------------+
+// Vector Data
+//--------------------------------------------------------------------+
+
 void usbfs_interrupt_handler(void);
 void usbfs_resume_handler(void);
 void usbfs_d0fifo_handler(void);
@@ -72,12 +81,6 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT
     [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
 };
 
-static const ioport_cfg_t family_pin_cfg = {
-    .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
-    .p_pin_cfg_data = board_pin_cfg,
-};
-static ioport_instance_ctrl_t port_ctrl;
-
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+

From 4080ab3d034557572bcaf17c340026865137bf15 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Jul 2023 11:22:19 +0700
Subject: [PATCH 1872/2085] wrap up ra update

---
 .idea/cmake.xml                       |  7 +++++--
 .idea/runConfigurations/kl25.xml      |  2 +-
 .idea/runConfigurations/stm32g474.xml |  2 +-
 hw/bsp/ra/family.c                    |  7 +------
 hw/bsp/ra/vector_data.h               | 24 ++++++++++++++++++++++++
 5 files changed, 32 insertions(+), 10 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 2ac7993c1..47ca8253e 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,7 +2,7 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="MinSizeRel" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
@@ -25,7 +25,7 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="rp2040" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk" />
       <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk" />
       <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1064_evk" />
@@ -43,6 +43,9 @@
       <configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2" />
       <configuration PROFILE_NAME="stm32f769disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f769disco -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco" />
+      <configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/kl25.xml b/.idea/runConfigurations/kl25.xml
index add9a0d6b..3052b440b 100644
--- a/.idea/runConfigurations/kl25.xml
+++ b/.idea/runConfigurations/kl25.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MKL25Z128xxx4&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MKL25Z128xxx4&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/stm32g474.xml b/.idea/runConfigurations/stm32g474.xml
index bbab2a5c5..6076320b5 100644
--- a/.idea/runConfigurations/stm32g474.xml
+++ b/.idea/runConfigurations/stm32g474.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 850498fbb..00b87f335 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -63,12 +63,7 @@ static ioport_instance_ctrl_t port_ctrl;
 // Vector Data
 //--------------------------------------------------------------------+
 
-void usbfs_interrupt_handler(void);
-void usbfs_resume_handler(void);
-void usbfs_d0fifo_handler(void);
-void usbfs_d1fifo_handler(void);
-
-const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
+BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
     [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
     [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
     [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h
index 37739c12a..400743d17 100644
--- a/hw/bsp/ra/vector_data.h
+++ b/hw/bsp/ra/vector_data.h
@@ -1,5 +1,29 @@
 /* vector numbers are configurable/dynamic, hence this, it will be used inside the port */
+#ifndef VECTOR_DATA_H
+#define VECTOR_DATA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef VECTOR_DATA_IRQ_COUNT
+  #define VECTOR_DATA_IRQ_COUNT 4
+#endif
+
+/* ISR prototypes */
+void usbfs_interrupt_handler(void);
+void usbfs_resume_handler(void);
+void usbfs_d0fifo_handler(void);
+void usbfs_d1fifo_handler(void);
+
+/* Vector table allocations */
 #define TU_IRQn 0
 #define USBFS_RESUME_IRQn 1
 #define USBFS_FIFO_0_IRQn 2
 #define USBFS_FIFO_1_IRQn 3
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

From d5d1b43eb9d1a619b71879892ada7cb85ca3c00f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Jul 2023 12:07:27 +0700
Subject: [PATCH 1873/2085] board pin data clean up

---
 hw/bsp/ra/boards/ra4m1_ek/board.h |  2 +-
 hw/bsp/ra/boards/ra4m3_ek/board.h | 11 ++++++-----
 hw/bsp/ra/boards/ra6m1_ek/board.h |  2 +-
 hw/bsp/ra/boards/ra6m5_ek/board.h | 15 ++++++++++-----
 4 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h
index b580bb5e9..ba3698f3d 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.h
@@ -40,7 +40,7 @@ extern "C" {
 const ioport_pin_cfg_t board_pin_cfg[] = {
     {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
     {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
-    // USB D+, D-, VBus
+    // USB FS D+, D-, VBus
     {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
     {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
     {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h
index e41302f90..c2f150b33 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.h
@@ -38,11 +38,12 @@ extern "C" {
 #define BUTTON_STATE_ACTIVE   0
 
 const ioport_pin_cfg_t board_pin_cfg[] = {
-  {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)},
-  {.pin = LED1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)},
-  {.pin = SW1, .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)},
+  {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
+  {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
+    // USB FS D+, D-, VBus
+  {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+  {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+  {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
 };
 
 #ifdef __cplusplus
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h
index 982a78e52..0b7297fd4 100644
--- a/hw/bsp/ra/boards/ra6m1_ek/board.h
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.h
@@ -40,7 +40,7 @@ extern "C" {
 const ioport_pin_cfg_t board_pin_cfg[] = {
     {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
     {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
-    // USB D+, D-, VBus
+    // USB FS D+, D-, VBus
     {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
     {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
     {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h
index 9c9bb6dcf..87434630f 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.h
@@ -38,20 +38,25 @@ extern "C" {
 #define BUTTON_STATE_ACTIVE   0
 
 const ioport_pin_cfg_t board_pin_cfg[] = {
-    { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
-    { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
-    { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
     { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
     { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
 
-    #ifdef TRACE_ETM
+    // USB FS D+, D-, VBus
+    { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH },
+    { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
+    { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
+
+    // USB HS D+, D-, VBus
+    { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS },
+    { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
+    { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
+
     // ETM Trace
     { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
     { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
     { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
     { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
     { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
-    #endif
 };
 
 #ifdef __cplusplus

From bb0e688b8e950652c70d82b46b7093e14b33c350 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 3 Jul 2023 16:35:22 +0700
Subject: [PATCH 1874/2085] add jlinkscript for detect rtt

---
 hw/bsp/ra/boards/ra4m1_ek/board.h |  2 +-
 hw/bsp/ra/boards/ra4m3_ek/board.h |  2 +-
 hw/bsp/ra/boards/ra6m1_ek/board.h |  2 +-
 hw/bsp/ra/boards/ra6m5_ek/board.h |  2 +-
 hw/bsp/ra/debug.jlinkscript       |  4 ++++
 hw/bsp/ra/family.c                | 12 +++++++-----
 6 files changed, 15 insertions(+), 9 deletions(-)
 create mode 100644 hw/bsp/ra/debug.jlinkscript

diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h
index ba3698f3d..c132387bc 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.h
@@ -37,7 +37,7 @@ extern "C" {
 #define SW1                   BSP_IO_PORT_01_PIN_05
 #define BUTTON_STATE_ACTIVE   0
 
-const ioport_pin_cfg_t board_pin_cfg[] = {
+static const ioport_pin_cfg_t board_pin_cfg[] = {
     {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
     {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
     // USB FS D+, D-, VBus
diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h
index c2f150b33..4b4735c4f 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.h
@@ -37,7 +37,7 @@ extern "C" {
 #define SW1  (BSP_IO_PORT_00_PIN_05)
 #define BUTTON_STATE_ACTIVE   0
 
-const ioport_pin_cfg_t board_pin_cfg[] = {
+static const ioport_pin_cfg_t board_pin_cfg[] = {
   {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
   {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
     // USB FS D+, D-, VBus
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h
index 0b7297fd4..2765a6a5f 100644
--- a/hw/bsp/ra/boards/ra6m1_ek/board.h
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.h
@@ -37,7 +37,7 @@ extern "C" {
 #define SW1                   BSP_IO_PORT_04_PIN_15
 #define BUTTON_STATE_ACTIVE   0
 
-const ioport_pin_cfg_t board_pin_cfg[] = {
+static const ioport_pin_cfg_t board_pin_cfg[] = {
     {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
     {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
     // USB FS D+, D-, VBus
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h
index 87434630f..c88e9a0a2 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.h
@@ -37,7 +37,7 @@ extern "C" {
 #define SW1                   BSP_IO_PORT_00_PIN_05
 #define BUTTON_STATE_ACTIVE   0
 
-const ioport_pin_cfg_t board_pin_cfg[] = {
+static const ioport_pin_cfg_t board_pin_cfg[] = {
     { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
     { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
 
diff --git a/hw/bsp/ra/debug.jlinkscript b/hw/bsp/ra/debug.jlinkscript
new file mode 100644
index 000000000..b34cfaa7f
--- /dev/null
+++ b/hw/bsp/ra/debug.jlinkscript
@@ -0,0 +1,4 @@
+int SetupTarget(void) {
+  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x80000");
+  return 0;
+}
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 8b5e911a1..08823dd52 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -90,12 +90,12 @@ void board_init(void)
   R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk;
 #endif
 
-  board_led_write(false);
+  // Enable USB module
+  R_MSTP->MSTPCRB &= ~(1U << 11U); // FS
 
-  /* Enable USB_BASE */
-  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_PRC1_UNLOCK;
-  R_MSTP->MSTPCRB &= ~(1U << 11U);
-  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_LOCK;
+#ifdef R_USB_HS0_BASE
+  R_MSTP->MSTPCRB &= ~(1U << 12U); // HS
+#endif
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
@@ -108,6 +108,8 @@ void board_init(void)
 #if CFG_TUSB_OS == OPT_OS_NONE
   SysTick_Config(SystemCoreClock / 1000);
 #endif
+
+  board_led_write(false);
 }
 
 void board_led_write(bool state) {

From 34966304dd2b32b141ad107eb75cdf77d22e031f Mon Sep 17 00:00:00 2001
From: Andrew Hooper <ahooper@kos.net>
Date: Mon, 3 Jul 2023 11:21:47 -0400
Subject: [PATCH 1875/2085] Restore RTOS argument for stm32f4

---
 hw/bsp/stm32f4/family.cmake | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake
index 7d9bbf331..a2f36a9e8 100644
--- a/hw/bsp/stm32f4/family.cmake
+++ b/hw/bsp/stm32f4/family.cmake
@@ -79,8 +79,9 @@ endfunction()
 #------------------------------------
 # Functions
 #------------------------------------
-function(family_configure_example TARGET)
-  family_configure_common(${TARGET})
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
 
   # Board target
   add_board_target(board_${BOARD})
@@ -100,7 +101,7 @@ function(family_configure_example TARGET)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_STM32F4)
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32F4 ${RTOS})
   if (MCU_VARIANT STREQUAL "stm32f407xx")
     target_sources(${TARGET}-tinyusb PUBLIC
             ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c

From cfc146e18fe2aa0df4d77d435d4a4b7053361cd7 Mon Sep 17 00:00:00 2001
From: Andrew Hooper <ahooper@kos.net>
Date: Tue, 4 Jul 2023 08:08:05 -0400
Subject: [PATCH 1876/2085] Add FreeRTOSConfig for family stm32f4

---
 .../stm32f4/FreeRTOSConfig/FreeRTOSConfig.h   | 165 ++++++++++++++++++
 1 file changed, 165 insertions(+)
 create mode 100644 hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h

diff --git a/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..b4a9be477
--- /dev/null
+++ b/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32f4xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif

From 071c30f381074c780bfb068cd31ed0801336bea6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 4 Jul 2023 19:27:37 +0700
Subject: [PATCH 1877/2085] update fsp to version 4.5, correct RA BSP. Fix ETM
 Trace with 6m5 by lowering PLL to 128Mhz.

---
 hw/bsp/family_support.cmake                   |  4 ++
 .../ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h  |  6 --
 .../boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h   |  2 +-
 hw/bsp/ra/boards/ra6m1_ek/board.h             | 10 ++-
 .../ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h  |  7 --
 .../boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h   |  2 +-
 hw/bsp/ra/boards/ra6m5_ek/board.h             | 16 +++--
 .../boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h   | 70 +++++++++++--------
 hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug  | 70 +++++++++++++++++++
 hw/bsp/ra/family.c                            | 15 ++--
 hw/bsp/ra/family.cmake                        |  8 +--
 tools/get_deps.py                             |  2 +-
 12 files changed, 142 insertions(+), 70 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index b2e61a824..5b97eb5e4 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -227,6 +227,10 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS)
 
   if (DEFINED LOG)
     target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG})
+    if (LOG STREQUAL "3")
+      # no inline for debug level 3
+      target_compile_definitions(${TARGET}-tinyusb_config INTERFACE TU_ATTR_ALWAYS_INLINE=)
+    endif ()
   endif()
 
   if (RTOS STREQUAL "freertos")
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
index 700d9b29f..19bb473eb 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -31,12 +31,6 @@
 #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(1)
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 
-#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
-
-#define BSP_FEATURE_TFU_SUPPORTED 0
-#define BSP_TZ_SECURE_BUILD    (0)
-#define BSP_TZ_NONSECURE_BUILD (0)
-
 // for SystemInit()
 void bsp_init(void * p_args);
 
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
index 930fa3547..554126523 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
@@ -7,7 +7,7 @@
 #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
 #define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */
 #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
-#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_8_0) /* PLL Mul x8 */
+#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(8u,0u)) /* PLL Mul x8 */
 #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
 #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h
index 2765a6a5f..f73a08fc0 100644
--- a/hw/bsp/ra/boards/ra6m1_ek/board.h
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.h
@@ -38,12 +38,10 @@ extern "C" {
 #define BUTTON_STATE_ACTIVE   0
 
 static const ioport_pin_cfg_t board_pin_cfg[] = {
-    {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
-    {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
-    // USB FS D+, D-, VBus
-    {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
-    {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
-    {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+    { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT },
+    { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
+    // USB FS
+    { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
 };
 
 #ifdef __cplusplus
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
index c2b23b16c..75a331fc2 100644
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -60,13 +60,6 @@ extern "C" {
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 #endif
 
-#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
-#define BSP_FEATURE_TFU_SUPPORTED 0
-#define BSP_TZ_SECURE_BUILD    (0)
-#define BSP_TZ_NONSECURE_BUILD (0)
-
-#define BSP_CFG_USE_LOW_VOLTAGE_MODE 0
-
 // for SystemInit()
 void bsp_init(void * p_args);
 
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h
index 1cdfae949..945a6010b 100644
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h
@@ -7,7 +7,7 @@
 #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
 #define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
 #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */
-#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL Mul x20.0 */
 #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
 #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
 #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h
index c88e9a0a2..779f71810 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.h
@@ -41,22 +41,24 @@ static const ioport_pin_cfg_t board_pin_cfg[] = {
     { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
     { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
 
-    // USB FS D+, D-, VBus
+    // USB FS
     { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH },
     { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
     { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
 
-    // USB HS D+, D-, VBus
+    // USB HS
     { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS },
     { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
     { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
 
     // ETM Trace
-    { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
-    { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
-    { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
-    { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
-    { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE },
+    #ifdef TRACE_ETM
+    { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+    { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+    { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+    { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+    { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+     #endif
 };
 
 #ifdef __cplusplus
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
index 77ac41d0a..9bb496dd6 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
@@ -1,35 +1,45 @@
 /* generated configuration header file - do not edit */
 #ifndef BSP_CLOCK_CFG_H_
 #define BSP_CLOCK_CFG_H_
-#define BSP_CFG_CLOCKS_SECURE (0)
+
+#define BSP_CFG_CLOCKS_SECURE   (0)
 #define BSP_CFG_CLOCKS_OVERRIDE (0)
-#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
-#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
-#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
-#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
-#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_25_0 /* PLL Mul x25.0 */
-#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
-#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
-#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */
-#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
-#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
-#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
-#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */
-#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
-#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
-#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
-#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
-#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
-#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
-#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
-#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
-#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
-#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
-#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
-#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
-#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
-#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */
-#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
-#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
-#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
+#define BSP_CFG_XTAL_HZ         (24000000)                         /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY  (2)                                /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE      (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV         (BSP_CLOCKS_PLL_DIV_3)             /* PLL Div /3 */
+
+#ifdef TRACE_ETM
+// Due to ozone fixed trace clock div = 1, PLL is limited around 100Mhz. This use 128 Mhz
+#define BSP_CFG_PLL_MUL         (BSP_CLOCKS_PLL_MUL(16U,0U))       /* PLL Mul x16.0 */
+#else
+#define BSP_CFG_PLL_MUL         (BSP_CLOCKS_PLL_MUL(25U,0U))       /* PLL Mul x25.0 */
+#endif
+
+#define BSP_CFG_PLL2_SOURCE     (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV        (BSP_CLOCKS_PLL_DIV_2)             /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL        (BSP_CLOCKS_PLL_MUL(20U,0U))       /* PLL2 Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE    (BSP_CLOCKS_SOURCE_CLOCK_PLL)      /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE   (BSP_CLOCKS_CLOCK_DISABLED)        /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE      (BSP_CLOCKS_SOURCE_CLOCK_PLL2)     /* UCLK Src: PLL2 */
+#define BSP_CFG_U60CK_SOURCE    (BSP_CLOCKS_SOURCE_CLOCK_PLL2)     /* U60CK Src: PLL2 */
+#define BSP_CFG_OCTA_SOURCE     (BSP_CLOCKS_CLOCK_DISABLED)        /* OCTASPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED)        /* CANFDCLK Disabled */
+#define BSP_CFG_CECCLK_SOURCE   (BSP_CLOCKS_CLOCK_DISABLED)        /* CECCLK Disabled */
+#define BSP_CFG_ICLK_DIV        (BSP_CLOCKS_SYS_CLOCK_DIV_1)       /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_2)       /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_4)       /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_4)       /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_2)       /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV        (BSP_CLOCKS_SYS_CLOCK_DIV_2)       /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT     (2)                                /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV        (BSP_CLOCKS_SYS_CLOCK_DIV_4)       /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV      (BSP_CLOCKS_SYS_CLOCK_DIV_1)       /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV         (BSP_CLOCKS_USB_CLOCK_DIV_5)       /* UCLK Div /5 */
+#define BSP_CFG_U60CK_DIV       (BSP_CLOCKS_USB60_CLOCK_DIV_4)     /* U60CK Div /4 */
+#define BSP_CFG_OCTA_DIV        (BSP_CLOCKS_OCTA_CLOCK_DIV_1)      /* OCTASPICLK Div /1 */
+#define BSP_CFG_CANFDCLK_DIV    (BSP_CLOCKS_CANFD_CLOCK_DIV_1)     /* CANFDCLK Div /1 */
+#define BSP_CFG_CECCLK_DIV      (BSP_CLOCKS_CEC_CLOCK_DIV_1)       /* CECCLK Div /1 */
+
+
 #endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
index fa55d40b2..8a1262138 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
+++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
@@ -33,3 +33,73 @@ void BeforeTargetConnect (void) {
   // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
   //
 }
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr != 0xFFFFFFFF) {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+  } else {
+    Util.Log("Project file error: failed to get program base");
+  }
+
+  PC = Elf.GetEntryPointPC();
+
+  if (PC != 0xFFFFFFFF) {
+    Target.SetReg("PC", PC);
+  } else if (VectorTableAddr != 0xFFFFFFFF) {
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr != 0xFFFFFFFF) {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+  } else {
+    Util.Log("Project file error: failed to get program base");
+  }
+
+  PC = Elf.GetEntryPointPC();
+
+  if (PC != 0xFFFFFFFF) {
+    Target.SetReg("PC", PC);
+  } else if (VectorTableAddr != 0xFFFFFFFF) {
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 08823dd52..769678954 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -36,15 +36,14 @@
 #endif
 
 #include "bsp_api.h"
+#include "r_ioport.h"
+#include "r_ioport_api.h"
+#include "renesas.h"
 
 #ifdef __GNUC__
 #pragma GCC diagnostic pop
 #endif
 
-#include "r_ioport.h"
-#include "r_ioport_api.h"
-#include "renesas.h"
-
 #include "bsp/board.h"
 #include "board.h"
 
@@ -86,15 +85,17 @@ void board_init(void)
   R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
 
 #ifdef TRACE_ETM
-  // Enable trace clock with div 1 (100 Mhz)
-  R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk;
+  // Enable trace clock (max 100Mhz) = PLL / div
+  // Somehow ozone/jtrace always fixed trace div to 1 therefore for ETM tracing working reliably
+  // PLL is limited around 100Mhz
+  R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01;
 #endif
 
   // Enable USB module
   R_MSTP->MSTPCRB &= ~(1U << 11U); // FS
 
 #ifdef R_USB_HS0_BASE
-  R_MSTP->MSTPCRB &= ~(1U << 12U); // HS
+//  R_MSTP->MSTPCRB &= ~(1U << 12U); // HS
 #endif
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index 828559e5e..f4e978230 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -37,14 +37,14 @@ function(add_board_target BOARD_TARGET)
       ${FSP_RA}/src/bsp/mcu/all/bsp_security.c
       ${FSP_RA}/src/r_ioport/r_ioport.c
       )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      _RA_TZ_NONSECURE
-      )
+    # ETM Trace option
+    if (TRACE_ETM STREQUAL "1")
+      target_compile_definitions(${BOARD_TARGET} PUBLIC TRACE_ETM)
+    endif ()
 
     target_compile_options(${BOARD_TARGET} PUBLIC
       -ffreestanding
       )
-
     target_include_directories(${BOARD_TARGET} PUBLIC
       ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
       ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
diff --git a/tools/get_deps.py b/tools/get_deps.py
index fa47a8067..21ad539c4 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -57,7 +57,7 @@ deps_optional = {
                                          '58879cfa0eca5725d8db6443ec17f8896a321042',
                                          'rp2040'],
     'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git',
-                           '9860fae1f180340a0e3c097dc6e91323cf83b926',
+                           'd52e5a6a59b7c638da860c2bb309b6e78e752ff8',
                            'ra'],
     'hw/mcu/renesas/rx': ['https://github.com/kkitayam/rx_device.git',
                           '706b4e0cf485605c32351e2f90f5698267996023',

From 1d6ca3bc9b68e0f17f2db61d2d8c2c951b8b32eb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 4 Jul 2023 20:04:54 +0700
Subject: [PATCH 1878/2085] fix ra4m3 ek build

---
 hw/bsp/ra/boards/ra4m3_ek/board.h             |   2 +-
 .../ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h  |  46 +-
 .../ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h |   5 +
 .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h       |  11 +
 .../ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 436 +++++++++++-------
 .../boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h   |  42 +-
 6 files changed, 355 insertions(+), 187 deletions(-)
 create mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
 create mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h

diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h
index 4b4735c4f..9dd2545a0 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/board.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/board.h
@@ -40,7 +40,7 @@ extern "C" {
 static const ioport_pin_cfg_t board_pin_cfg[] = {
   {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
   {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
-    // USB FS D+, D-, VBus
+    // USB FS
   {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
   {.pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
   {.pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
index a9cb8210b..6a47bccc6 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -1,21 +1,36 @@
 /* generated configuration header file - do not edit */
 #ifndef BSP_CFG_H_
 #define BSP_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
 
-#undef RA_NOT_DEFINED
+#define RA_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+#define BSP_CFG_RTOS (2)
+#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+#define BSP_CFG_RTOS (1)
+#else
 #define BSP_CFG_RTOS (0)
+#endif
+#endif
+#ifndef BSP_CFG_RTC_USED
+#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+#endif
+#undef RA_NOT_DEFINED
 #if defined(_RA_BOOT_IMAGE)
 #define BSP_CFG_BOOT_IMAGE (1)
 #endif
-#define BSP_CFG_MCU_VCC_MV	      (3300)
-#define BSP_CFG_STACK_MAIN_BYTES      (0x400)
-#define BSP_CFG_HEAP_BYTES	      (0x400)
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x400)
+#define BSP_CFG_HEAP_BYTES (0x400)
 #define BSP_CFG_PARAM_CHECKING_ENABLE (1)
-#define BSP_CFG_ASSERT		      (0)
-#define BSP_CFG_ERROR_LOG	      (0)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
 
 #define BSP_CFG_PFS_PROTECT ((1))
 
@@ -24,14 +39,27 @@
 
 #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
 
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
 #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+#endif
 
-#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE	(0)
-#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE		(0)
-#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(1)
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+#endif
 
 // for SystemInit()
 void bsp_init(void * p_args);
 
+#ifdef __cplusplus
+}
+#endif
 #endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..444d32e56
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..1a0bc02e2
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M3AF3CFB
+#define BSP_MCU_FEATURE_SET ('A')
+#define BSP_ROM_SIZE_BYTES (1048576)
+#define BSP_RAM_SIZE_BYTES (131072)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (144)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
index 4ecda1c66..26e184a94 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -1,129 +1,181 @@
-/* generated configuration header file through renesas e2 studio */
+/* generated configuration header file - do not edit */
 #ifndef BSP_MCU_FAMILY_CFG_H_
 #define BSP_MCU_FAMILY_CFG_H_
-
-#include "bsp_clock_cfg.h"
-#include "bsp_mcu_info.h"
-
-#define BSP_CFG_MCU_PART_SERIES (4)
-#define BSP_MCU_R7FA4M3AF3CFB
-#define BSP_ROM_SIZE_BYTES	  (1048576)
-#define BSP_RAM_SIZE_BYTES	  (131072)
-#define BSP_DATA_FLASH_SIZE_BYTES (8192)
-#define BSP_PACKAGE_LQFP
-#define BSP_PACKAGE_PINS (144)
-
-#define BSP_MCU_GROUP_RA4M3 (1)
-#define BSP_LOCO_HZ	    (32768)
-#define BSP_MOCO_HZ	    (8000000)
-#define BSP_SUB_CLOCK_HZ    (32768)
-#if BSP_CFG_HOCO_FREQUENCY == 0
-#define BSP_HOCO_HZ (16000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 1
-#define BSP_HOCO_HZ (18000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 2
-#define BSP_HOCO_HZ (20000000)
-#else
-#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#ifdef __cplusplus
+extern "C" {
 #endif
 
-#define BSP_CFG_FLL_ENABLE (0)
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+#define BSP_MCU_GROUP_RA4M3 (1)
+#define BSP_LOCO_HZ                 (32768)
+#define BSP_MOCO_HZ                 (8000000)
+#define BSP_SUB_CLOCK_HZ            (32768)
+#if   BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ                 (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+                #define BSP_HOCO_HZ                 (18000000)
+            #elif BSP_CFG_HOCO_FREQUENCY == 2
+                #define BSP_HOCO_HZ                 (20000000)
+            #else
+                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+            #endif
 
-#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
-#define BSP_VECTOR_TABLE_MAX_ENTRIES	(112U)
-#define BSP_MCU_VBATT_SUPPORT		(1)
+#define BSP_CFG_FLL_ENABLE                 (0)
+
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
 
 #if defined(_RA_TZ_SECURE)
-#define BSP_TZ_SECURE_BUILD    (1)
-#define BSP_TZ_NONSECURE_BUILD (0)
-#elif defined(_RA_TZ_NONSECURE)
-#define BSP_TZ_SECURE_BUILD    (0)
-#define BSP_TZ_NONSECURE_BUILD (1)
-#else
-#define BSP_TZ_SECURE_BUILD    (0)
-#define BSP_TZ_NONSECURE_BUILD (0)
+            #define BSP_TZ_SECURE_BUILD           (1)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #elif defined(_RA_TZ_NONSECURE)
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (1)
+            #else
+#define BSP_TZ_SECURE_BUILD           (0)
+#define BSP_TZ_NONSECURE_BUILD        (0)
 #endif
 
 /* TrustZone Settings */
-#define BSP_TZ_CFG_INIT_SECURE_ONLY   (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
-#define BSP_TZ_CFG_SKIP_INIT	      (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
-#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
+#define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+#define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+#define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
 
 /* CMSIS TrustZone Settings */
-#define SCB_CSR_AIRCR_INIT	   (1)
-#define SCB_AIRCR_BFHFNMINS_VAL	   (0)
-#define SCB_AIRCR_SYSRESETREQS_VAL (1)
-#define SCB_AIRCR_PRIS_VAL	   (0)
-#define TZ_FPU_NS_USAGE		   (1)
-#define SCB_NSACR_CP10_11_VAL	   (3U)
+#define SCB_CSR_AIRCR_INIT                (1)
+#define SCB_AIRCR_BFHFNMINS_VAL           (0)
+#define SCB_AIRCR_SYSRESETREQS_VAL        (1)
+#define SCB_AIRCR_PRIS_VAL                (0)
+#define TZ_FPU_NS_USAGE                   (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+#define SCB_NSACR_CP10_11_VAL             (3U)
+#endif
 
-#define FPU_FPCCR_TS_VAL	(1U)
-#define FPU_FPCCR_CLRONRETS_VAL (1)
+#ifndef FPU_FPCCR_TS_VAL
+#define FPU_FPCCR_TS_VAL                  (1U)
+#endif
+#define FPU_FPCCR_CLRONRETS_VAL           (1)
 
-#define FPU_FPCCR_CLRONRET_VAL (1)
+#ifndef FPU_FPCCR_CLRONRET_VAL
+#define FPU_FPCCR_CLRONRET_VAL            (1)
+#endif
 
 /* The C-Cache line size that is configured during startup. */
-#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
+#ifndef BSP_CFG_C_CACHE_LINE_SIZE
+#define BSP_CFG_C_CACHE_LINE_SIZE   (1U)
+#endif
 
 /* Type 1 Peripheral Security Attribution */
 
 /* Peripheral Security Attribution Register (PSAR) Settings */
-#define BSP_TZ_CFG_PSARB                                                                                             \
-  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ |   \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ |   \
-   (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ |             \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | 0x33f4f9) /* Unused */
-#define BSP_TZ_CFG_PSARC                                                                                             \
-  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ |     \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ |  \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | 0x7fffcef4) /* Unused */
-#define BSP_TZ_CFG_PSARD                                                                                               \
-  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ |     \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ |     \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ |                \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ |     \
-   0xffae07f0) /* Unused */
-#define BSP_TZ_CFG_PSARE                                                                                             \
-  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ |    \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ |   \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
-   (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ |              \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ |              \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ |              \
-   (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | 0x3f3ff8) /* Unused */
-#define BSP_TZ_CFG_MSSAR                                                                                              \
-  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
-   0xfffffffc) /* Unused */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+            (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
+            0x33f4f9) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
+            0x7fffcef4) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
+            (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+            0xffae07f0) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+            (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+            (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+            (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+            (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+            0x3f3ff8) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+            0xfffffffc) /* Unused */
+#endif
 
 /* Type 2 Peripheral Security Attribution */
 
 /* Security attribution for Cache registers. */
+#ifndef BSP_TZ_CFG_CSAR
 #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+#endif
 
 /* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
 #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+#endif
 
 /* Security attribution for registers of LVD channels. */
-#define BSP_TZ_CFG_LVDSAR                                              \
-  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
-   0xFFFFFFFCU)
+#ifndef BSP_TZ_CFG_LVDSAR
+#define BSP_TZ_CFG_LVDSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+            0xFFFFFFFCU)
+#endif
 
 /* Security attribution for LPM registers. */
+#ifndef BSP_TZ_CFG_LPMSAR
 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+#endif
 /* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
 #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+#endif
 
 /* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
 #if BSP_CFG_CLOCKS_SECURE
 /* Protect all CGC registers from Non-secure write access. */
 #define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
@@ -131,58 +183,78 @@
 /* Allow Secure and Non-secure write access. */
 #define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
 #endif
+#endif
 
 /* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
 #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+#endif
 
 /* Security attribution for registers for IRQ channels. */
-#define BSP_TZ_CFG_ICUSARA                                                                                                    \
-  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ |                                                       \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ |                                                       \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ |                                                       \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ |                                                       \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ |                                                       \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ |                                                       \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ |                                                       \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ |                                                       \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ |                                                       \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ |   \
-   (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ |                                                     \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ |                                                     \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | 0xFFFF0000U)
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+            (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+            (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
+            0xFFFF0000U)
+#endif
 
 /* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
 #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+#endif
 
 /* Security attribution for registers for DMAC channels */
-#define BSP_TZ_CFG_ICUSARC                                               \
-  ((((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
-   (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | 0xFFFFFF00U)
+#ifndef BSP_TZ_CFG_ICUSARC
+#define BSP_TZ_CFG_ICUSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
+            0xFFFFFF00U)
+#endif
 
 /* Security attribution registers for SELSR0. */
+#ifndef BSP_TZ_CFG_ICUSARD
 #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+#endif
 
 /* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
 #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+#endif
 
 /* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
 #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+#endif
 
 /* Set DTCSTSAR if the Secure program uses the DTC. */
-// #if RA_NOT_DEFINED == RA_NOT_DEFINED
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
 #define BSP_TZ_CFG_DTC_USED (0U)
-// #else
-// #define BSP_TZ_CFG_DTC_USED (1U)
-// #endif
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
 
 /* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
 /* If the CGC registers are only accessible in Secure mode, than there is no
  * reason for nonsecure applications to access FLWT and FCKMHZ. */
 #if BSP_CFG_CLOCKS_SECURE
@@ -192,69 +264,123 @@
 /* Allow Secure and Non-secure write access. */
 #define BSP_TZ_CFG_FSAR (0xFFFFU)
 #endif
+#endif
 
 /* Security attribution for SRAM registers. */
-/* If the CGC registers are only accessible in Secure mode, than there is no
- * reason for Non Secure applications to access
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
  * SRAM0WTEN and therefore there is no reason to access PRCR2. */
-#define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U)
+#define BSP_TZ_CFG_SRAMSAR (\
+        1 | \
+        ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
+        4 | \
+        0xFFFFFFF8U)
+#endif
 
 /* Security attribution for Standby RAM registers. */
+#ifndef BSP_TZ_CFG_STBRAMSAR
 #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+#endif
 
 /* Security attribution for the DMAC Bus Master MPU settings. */
-/* The DMAC Bus Master MPU settings should align with the DMAC channel settings.
- */
+#ifndef BSP_TZ_CFG_MMPUSARA
+/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
 #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+#endif
 
 /* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
 #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+#endif
 /* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
 #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+#endif
 
-#define OFS_SEQ1	     0xA001A001 | (1 << 1) | (3 << 2)
-#define OFS_SEQ2	     (15 << 4) | (3 << 8) | (3 << 10)
-#define OFS_SEQ3	     (1 << 12) | (1 << 14) | (1 << 17)
-#define OFS_SEQ4	     (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
-#define OFS_SEQ5	     (1 << 28) | (1 << 30)
+/* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
 
 /* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
 #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
-#define BSP_CFG_ROM_REG_OFS1_SEL \
-  (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
 #else
 #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
 #endif
+#endif
 
-#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) |  (1 << 8))
+
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
 
-/* Used to create IELS values for the interrupt initialization table
- * g_interrupt_event_link_select. */
-#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector)
 /* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
 #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU)
-/* Block Protection Register 0 */
-#define BSP_CFG_ROM_REG_BPS0 (~(0U))
-/* Block Protection Register 1 */
-#define BSP_CFG_ROM_REG_BPS1 (~(0U))
-/* Block Protection Register 2 */
-#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU)
-/* Permanent Block Protection Register 0 */
-#define BSP_CFG_ROM_REG_PBPS0 (~(0U))
-/* Permanent Block Protection Register 1 */
-#define BSP_CFG_ROM_REG_PBPS1 (~(0U))
-/* Permanent Block Protection Register 2 */
-#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU)
-/* Security Attribution for Block Protection Register 0 (If any blocks are
- * marked as protected in the secure application, then mark them as secure) */
-#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
-/* Security Attribution for Block Protection Register 1 (If any blocks are
- * marked as protected in the secure application, then mark them as secure) */
-#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
-/* Security Attribution for Block Protection Register 2 (If any blocks are
- * marked as protected in the secure application, then mark them as secure) */
-#define BSP_CFG_ROM_REG_BPS_SEL2    (0xFFFFFFFFU)
-#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
 
+/* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+/* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+/* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU)
+#endif
+/* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+#endif
+/* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+/* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+/* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU)
+#endif
+/* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+#endif
+/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU)
+#endif
+/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+#define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
 #endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
index 4f490f340..80641945d 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
@@ -1,27 +1,25 @@
 /* generated configuration header file - do not edit */
 #ifndef BSP_CLOCK_CFG_H_
 #define BSP_CLOCK_CFG_H_
-
-#define BSP_CFG_CLOCKS_SECURE	(0)
+#define BSP_CFG_CLOCKS_SECURE (0)
 #define BSP_CFG_CLOCKS_OVERRIDE (0)
-#define BSP_CFG_XTAL_HZ		(24000000)			   /* XTAL 24000000Hz */
-#define BSP_CFG_HOCO_FREQUENCY	(2)				   /* HOCO 20MHz */
-#define BSP_CFG_PLL_SOURCE	(BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
-#define BSP_CFG_PLL_DIV		(BSP_CLOCKS_PLL_DIV_3)		   /* PLL Div /3 */
-#define BSP_CFG_PLL_MUL		BSP_CLOCKS_PLL_MUL_24_0		   /* PLL Mul x24.0 */
-#define BSP_CFG_PLL2_SOURCE	(BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
-#define BSP_CFG_PLL2_DIV	(BSP_CLOCKS_PLL_DIV_3)		   /* PLL2 Div /3 */
-#define BSP_CFG_PLL2_MUL	BSP_CLOCKS_PLL_MUL_24_0		   /* PLL2 Mul x24.0 */
-#define BSP_CFG_CLOCK_SOURCE	(BSP_CLOCKS_SOURCE_CLOCK_PLL)	   /* Clock Src: PLL */
-#define BSP_CFG_CLKOUT_SOURCE	(BSP_CLOCKS_CLOCK_DISABLED)	   /* CLKOUT Disabled */
-#define BSP_CFG_UCK_SOURCE	(BSP_CLOCKS_SOURCE_CLOCK_PLL2)	   /* UCLK Src: PLL2 */
-#define BSP_CFG_ICLK_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_2)	   /* ICLK Div /2 */
-#define BSP_CFG_PCLKA_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_2)	   /* PCLKA Div /2 */
-#define BSP_CFG_PCLKB_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_4)	   /* PCLKB Div /4 */
-#define BSP_CFG_PCLKC_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_4)	   /* PCLKC Div /4 */
-#define BSP_CFG_PCLKD_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_2)	   /* PCLKD Div /2 */
-#define BSP_CFG_FCLK_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_4)	   /* FCLK Div /4 */
-#define BSP_CFG_CLKOUT_DIV	(BSP_CLOCKS_SYS_CLOCK_DIV_1)	   /* CLKOUT Div /1 */
-#define BSP_CFG_UCK_DIV		(BSP_CLOCKS_USB_CLOCK_DIV_4)	   /* UCLK Div /4 */
-
+#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL Mul x24.0 */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL2 Mul x24.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */
 #endif /* BSP_CLOCK_CFG_H_ */

From f79529c09c6e7c0d6ee5586633ceb8c83e345406 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Jul 2023 17:13:01 +0700
Subject: [PATCH 1879/2085] usb hs work with ra 6m5 ek

---
 .idea/runConfigurations/ra4m1.xml             |  10 ++
 .idea/runConfigurations/ra6m1.xml             |  10 ++
 .idea/runConfigurations/ra6m5.xml             |  10 ++
 hw/bsp/ra/board_cfg.h                         |  45 +++++++
 .../ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h  |   4 +-
 .../ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h  |   4 +-
 .../ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h  |   4 +-
 hw/bsp/ra/boards/ra6m5_ek/board.cmake         |  20 ++-
 .../ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h  |   4 +-
 hw/bsp/ra/family.c                            | 122 ++++++++++++------
 hw/bsp/ra/vector_data.h                       |  15 ++-
 src/common/tusb_mcu.h                         |   1 +
 src/portable/renesas/rusb2/dcd_rusb2.c        |   3 +-
 13 files changed, 190 insertions(+), 62 deletions(-)
 create mode 100644 .idea/runConfigurations/ra4m1.xml
 create mode 100644 .idea/runConfigurations/ra6m1.xml
 create mode 100644 .idea/runConfigurations/ra6m5.xml
 create mode 100644 hw/bsp/ra/board_cfg.h

diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml
new file mode 100644
index 000000000..22bb61949
--- /dev/null
+++ b/.idea/runConfigurations/ra4m1.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml
new file mode 100644
index 000000000..438ac4063
--- /dev/null
+++ b/.idea/runConfigurations/ra6m1.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml
new file mode 100644
index 000000000..02df11610
--- /dev/null
+++ b/.idea/runConfigurations/ra6m5.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/hw/bsp/ra/board_cfg.h b/hw/bsp/ra/board_cfg.h
new file mode 100644
index 000000000..baed46b5f
--- /dev/null
+++ b/hw/bsp/ra/board_cfg.h
@@ -0,0 +1,45 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _BOARD_CFG_H
+#define _BOARD_CFG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
+  #define BOARD_HAS_USB_HIGHSPEED
+#endif
+
+// for SystemInit()
+void bsp_init(void * p_args);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
index 19bb473eb..f0577b702 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -4,6 +4,7 @@
 
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
 
 #undef RA_NOT_DEFINED
 #define BSP_CFG_RTOS (0)
@@ -31,7 +32,4 @@
 #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(1)
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 
-// for SystemInit()
-void bsp_init(void * p_args);
-
 #endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
index 6a47bccc6..47de7747d 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -7,6 +7,7 @@ extern "C" {
 
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
 
 #define RA_NOT_DEFINED 0
 #ifndef BSP_CFG_RTOS
@@ -56,9 +57,6 @@ extern "C" {
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 #endif
 
-// for SystemInit()
-void bsp_init(void * p_args);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
index 75a331fc2..b5ed53a3b 100644
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -8,6 +8,7 @@ extern "C" {
 
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
 
 #define RA_NOT_DEFINED 0
 #ifndef BSP_CFG_RTOS
@@ -60,9 +61,6 @@ extern "C" {
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 #endif
 
-// for SystemInit()
-void bsp_init(void * p_args);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
index 42a4c7417..d934a0c0d 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
@@ -3,8 +3,22 @@ set(MCU_VARIANT ra6m5)
 
 set(JLINK_DEVICE R7FA6M5BH)
 
+# default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+set(PORT 1)
+endif()
+
 function(update_board TARGET)
-#  target_compile_definitions(${TARGET} PUBLIC)
-#  target_sources(${TARGET} PRIVATE)
-#  target_include_directories(${BOARD_TARGET} PUBLIC)
+  target_compile_definitions(${TARGET} PUBLIC
+    BOARD_TUD_RHPORT=${PORT}
+    # port 0 is fullspeed, port 1 is highspeed
+    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
+    )
+
+  if (PORT STREQUAL 1)
+    target_compile_definitions(${TARGET} PUBLIC
+      CFG_TUSB_RHPORT1_MODE=OPT_MODE_DEVICE|OPT_MODE_HIGH_SPEED
+      CFG_TUSB_RHPORT0_MODE=0
+      )
+  endif ()
 endfunction()
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
index e41f603ad..a41536eda 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -7,6 +7,7 @@ extern "C" {
 
 #include "bsp_clock_cfg.h"
 #include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
 
 #define RA_NOT_DEFINED 0
 #ifndef BSP_CFG_RTOS
@@ -56,9 +57,6 @@ extern "C" {
 #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
 #endif
 
-// for SystemInit()
-void bsp_init(void * p_args);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 769678954..36b46beab 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -48,9 +48,9 @@
 #include "board.h"
 
 /* Key code for writing PRCR register. */
-#define BSP_PRV_PRCR_KEY	       (0xA500U)
+#define BSP_PRV_PRCR_KEY         (0xA500U)
 #define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
-#define BSP_PRV_PRCR_LOCK	       ((BSP_PRV_PRCR_KEY) | 0x0U)
+#define BSP_PRV_PRCR_LOCK         ((BSP_PRV_PRCR_KEY) | 0x0U)
 
 static const ioport_cfg_t family_pin_cfg = {
     .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
@@ -62,25 +62,38 @@ static ioport_instance_ctrl_t port_ctrl;
 // Vector Data
 //--------------------------------------------------------------------+
 
-BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = {
+BSP_DONT_REMOVE BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS)
+const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] = {
     [0] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
     [1] = usbfs_resume_handler,    /* USBFS RESUME (USBFS resume interrupt) */
     [2] = usbfs_d0fifo_handler,    /* USBFS FIFO 0 (DMA transfer request 0) */
     [3] = usbfs_d1fifo_handler,    /* USBFS FIFO 1 (DMA transfer request 1) */
+
+#ifdef BOARD_HAS_USB_HIGHSPEED
+    [4] = usbhs_interrupt_handler, /* USBHS INT (USBHS interrupt) */
+    [5] = usbhs_d0fifo_handler,    /* USBHS FIFO 0 (DMA transfer request 0) */
+    [6] = usbhs_d1fifo_handler,    /* USBHS FIFO 1 (DMA transfer request 1) */
+#endif
 };
+
 const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = {
-    [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),    /* USBFS INT (USBFS interrupt) */
-    [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME), /* USBFS RESUME (USBFS resume interrupt) */
-    [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0), /* USBFS FIFO 0 (DMA transfer request 0) */
-    [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1)  /* USBFS FIFO 1 (DMA transfer request 1) */
+    [0] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),            /* USBFS INT (USBFS interrupt) */
+    [1] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME),         /* USBFS RESUME (USBFS resume interrupt) */
+    [2] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0),         /* USBFS FIFO 0 (DMA transfer request 0) */
+    [3] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1),         /* USBFS FIFO 1 (DMA transfer request 1) */
+
+#ifdef BOARD_HAS_USB_HIGHSPEED
+    [4] = BSP_PRV_IELS_ENUM(EVENT_USBHS_USB_INT_RESUME), /* USBHS USB INT RESUME (USBHS interrupt) */
+    [5] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_0),         /* USBHS FIFO 0 (DMA transfer request 0) */
+    [6] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_1),         /* USBHS FIFO 1 (DMA transfer request 1) */
+#endif
 };
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_init(void)
-{
+void board_init(void) {
   /* Configure pins. */
   R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
 
@@ -94,8 +107,8 @@ void board_init(void)
   // Enable USB module
   R_MSTP->MSTPCRB &= ~(1U << 11U); // FS
 
-#ifdef R_USB_HS0_BASE
-//  R_MSTP->MSTPCRB &= ~(1U << 12U); // HS
+#ifdef BOARD_HAS_USB_HIGHSPEED
+  R_MSTP->MSTPCRB &= ~(1U << 12U);
 #endif
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
@@ -145,67 +158,94 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void usbfs_interrupt_handler(void)
-{
+
+#if CFG_TUD_ENABLED && defined(BOARD_TUD_RHPORT)
+  #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_DEVICE(_n)  0
+#endif
+
+#if CFG_TUH_ENABLED && defined(BOARD_TUH_RHPORT)
+  #define PORT_SUPPORT_HOST(_n)    (BOARD_TUH_RHPORT == _n)
+#else
+  #define PORT_SUPPORT_HOST(_n)    0
+#endif
+
+//------------- USB0 FullSpeed -------------//
+void usbfs_interrupt_handler(void) {
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
 
-#if CFG_TUH_ENABLED
+  #if PORT_SUPPORT_HOST(0)
   tuh_int_handler(0);
-#endif
+  #endif
 
-#if CFG_TUD_ENABLED
+  #if PORT_SUPPORT_DEVICE(0)
   tud_int_handler(0);
-#endif
+  #endif
 }
 
-void usbfs_resume_handler(void)
-{
+void usbfs_resume_handler(void) {
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
 
-#if CFG_TUH_ENABLED
+  #if PORT_SUPPORT_HOST(0)
   tuh_int_handler(0);
-#endif
+  #endif
 
-#if CFG_TUD_ENABLED
+  #if PORT_SUPPORT_DEVICE(0)
   tud_int_handler(0);
-#endif
+  #endif
 }
 
-void usbfs_d0fifo_handler(void)
-{
+void usbfs_d0fifo_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
+
+void usbfs_d1fifo_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
+
+//------------- USB1 HighSpeed -------------//
+#ifdef BOARD_HAS_USB_HIGHSPEED
+
+void usbhs_interrupt_handler(void) {
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
 
-#if CFG_TUH_ENABLED
-  tuh_int_handler(0);
-#endif
+  #if PORT_SUPPORT_HOST(1)
+  tuh_int_handler(1);
+  #endif
 
-#if CFG_TUD_ENABLED
-  tud_int_handler(0);
-#endif
+  #if PORT_SUPPORT_DEVICE(1)
+  tud_int_handler(1);
+  #endif
 }
 
-void usbfs_d1fifo_handler(void)
-{
+void usbhs_d0fifo_handler(void) {
   IRQn_Type irq = R_FSP_CurrentIrqGet();
   R_BSP_IrqStatusClear(irq);
-
-#if CFG_TUH_ENABLED
-  tuh_int_handler(0);
-#endif
-
-#if CFG_TUD_ENABLED
-  tud_int_handler(0);
-#endif
+  // TODO not used yet
 }
 
+void usbhs_d1fifo_handler(void) {
+  IRQn_Type irq = R_FSP_CurrentIrqGet();
+  R_BSP_IrqStatusClear(irq);
+  // TODO not used yet
+}
+
+#endif
+
 //--------------------------------------------------------------------+
 // stdlib
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h
index 3d8a24634..ca667faa3 100644
--- a/hw/bsp/ra/vector_data.h
+++ b/hw/bsp/ra/vector_data.h
@@ -6,22 +6,29 @@
 extern "C" {
 #endif
 
-#ifndef VECTOR_DATA_IRQ_COUNT
-  #define VECTOR_DATA_IRQ_COUNT 4
-#endif
-
 /* ISR prototypes */
 void usbfs_interrupt_handler(void);
 void usbfs_resume_handler(void);
 void usbfs_d0fifo_handler(void);
 void usbfs_d1fifo_handler(void);
 
+#ifdef BOARD_HAS_USB_HIGHSPEED
+void usbhs_interrupt_handler(void);
+void usbhs_d0fifo_handler(void);
+void usbhs_d1fifo_handler(void);
+#endif
+
 /* Vector table allocations */
 #define USBFS_INT_IRQn    0
 #define USBFS_RESUME_IRQn 1
 #define USBFS_FIFO_0_IRQn 2
 #define USBFS_FIFO_1_IRQn 3
 
+#define USBHS_USB_INT_RESUME_IRQn  4 /* USBHS USB INT RESUME (USBHS interrupt) */
+#define USBHS_FIFO_0_IRQn          5 /* USBHS FIFO 0 (DMA transfer request 0) */
+#define USBHS_FIFO_1_IRQn          6 /* USBHS FIFO 1 (DMA transfer request 1) */
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 9f3be78fd..496ebfc85 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -327,6 +327,7 @@
 // Renesas
 //--------------------------------------------------------------------+
 #elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N, OPT_MCU_RAXXX)
+  #define TUP_USBIP_RUSB2
   #define TUP_DCD_ENDPOINT_MAX    10
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index e9ac46517..83d2a34c6 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -31,8 +31,7 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if CFG_TUD_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \
-                        TU_CHECK_MCU(OPT_MCU_RAXXX))
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2)
 
 #include "device/dcd.h"
 #include "rusb2_type.h"

From 4f4c93594d8f82c18f9a1052c4da2e7c31fc1b8c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Jul 2023 17:51:36 +0700
Subject: [PATCH 1880/2085] minor pipe clean up

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 74 +++++++++++++++-----------
 1 file changed, 43 insertions(+), 31 deletions(-)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 83d2a34c6..b58e0be01 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -93,20 +93,20 @@ typedef struct TU_ATTR_PACKED {
 
 typedef union TU_ATTR_PACKED {
   struct {
-    volatile uint16_t u8: 8;
-    volatile uint16_t   : 0;
+    volatile uint8_t u8;
+    volatile uint8_t reserved8;
   };
   volatile uint16_t u16;
 } hw_fifo_t;
 
 typedef union TU_ATTR_PACKED {
   struct {
-    volatile uint32_t  : 24;
-    volatile uint32_t u8: 8;
+    volatile uint8_t reserved8[3];
+    volatile uint8_t u8;
   };
   struct {
-    volatile uint32_t    : 16;
-    volatile uint32_t u16: 16;
+    volatile uint16_t reserved16;
+    volatile uint16_t u16;
   };
   volatile uint32_t u32;
 } hw_fifo32_t;
@@ -126,6 +126,19 @@ typedef struct TU_ATTR_PACKED
 TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 TU_ATTR_BIT_FIELD_ORDER_END
 
+// Transfer conditions specifiable for each pipe:
+// - Pipe 0: Control transfer with 64-byte single buffer
+// - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up
+//   to 2 KB and optional double buffer
+// - Pipes 3 to 5: Bulk transfer continuous transfer mode with programmable buffer size up to 2 KB and
+//   optional double buffer
+// - Pipes 6 to 9: Interrupt transfer with 64-byte single buffer
+enum {
+  PIPE_1ST_BULK = 3,
+  PIPE_1ST_INTERRUPT = 6,
+  PIPE_COUNT = 10,
+};
+
 typedef struct
 {
   pipe_state_t pipe[10];
@@ -137,34 +150,33 @@ typedef struct
 //--------------------------------------------------------------------+
 static dcd_data_t _dcd;
 
-#ifndef FIRST_BULK_PIPE
-#define FIRST_BULK_PIPE 3
-#endif
-
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
-  case TUSB_XFER_ISOCHRONOUS:
-    for (int i = 1; i <= 2; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_BULK:
-    for (int i = FIRST_BULK_PIPE; i <= 5; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    for (int i = 1; i <= 1; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_INTERRUPT:
-    for (int i = 6; i <= 9; ++i) {
-      if (0 == _dcd.pipe[i].ep) return  i;
-    }
-    break;
-  default:
-    /* No support for control transfer */
-    break;
+    case TUSB_XFER_ISOCHRONOUS:
+      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
+        if (0 == _dcd.pipe[i].ep) return i;
+      }
+      break;
+
+    case TUSB_XFER_BULK:
+      for (int i = PIPE_1ST_BULK; i < PIPE_1ST_INTERRUPT; ++i) {
+        if (0 == _dcd.pipe[i].ep) return i;
+      }
+      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
+        if (0 == _dcd.pipe[i].ep) return i;
+      }
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      for (int i = PIPE_1ST_INTERRUPT; i < PIPE_COUNT; ++i) {
+        if (0 == _dcd.pipe[i].ep) return i;
+      }
+      break;
+
+    default:
+      /* No support for control transfer */
+      break;
   }
   return 0;
 }

From f308435b649c37f0cffc1d5a566fb71c22b57aa1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 5 Jul 2023 22:09:35 +0700
Subject: [PATCH 1881/2085] update ra type to include usbhs registers

---
 hw/bsp/ra/family.cmake                  |   1 -
 hw/bsp/ra/family.mk                     |   1 -
 src/portable/renesas/rusb2/rusb2_ra.c   |  16 --
 src/portable/renesas/rusb2/rusb2_ra.h   |  85 ++++---
 src/portable/renesas/rusb2/rusb2_type.h | 313 +++++++++++++++---------
 5 files changed, 245 insertions(+), 171 deletions(-)
 delete mode 100644 src/portable/renesas/rusb2/rusb2_ra.c

diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index f4e978230..74329165f 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -120,7 +120,6 @@ function(family_configure_example TARGET RTOS)
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
     ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
-    ${TOP}/src/portable/renesas/rusb2/rusb2_ra.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 9b6b02c02..b6e1bb0ae 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -18,7 +18,6 @@ CFLAGS += \
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
-  src/portable/renesas/rusb2/rusb2_ra.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
 	$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c
deleted file mode 100644
index ff2191b1f..000000000
--- a/src/portable/renesas/rusb2/rusb2_ra.c
+++ /dev/null
@@ -1,16 +0,0 @@
-#include "tusb_option.h"
-#include "rusb2_ra.h"
-
-#if (CFG_TUSB_RHPORT0_MODE != 0)
-IRQn_Type _usb_fs_irqn = USBFS_INT_IRQn;
-void tud_set_irq_usbfs(IRQn_Type q) {
-  _usb_fs_irqn = q;
-}
-#endif
-
-#if (CFG_TUSB_RHPORT1_MODE != 0)
-IRQn_Type _usb_hs_irqn = USBHS_USB_INT_RESUME_IRQn;
-void tud_set_irq_usbhs(IRQn_Type q) {
-  _usb_hs_irqn = q;
-}
-#endif
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 07fcafe6f..ca7c38907 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -47,55 +47,53 @@ extern "C" {
 #pragma GCC diagnostic pop
 #endif
 
-extern IRQn_Type _usb_fs_irqn;
-extern IRQn_Type _usb_hs_irqn;
-
-#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
-// fallback
-#define CFG_TUSB_RHPORT0_MODE   ( CFG_TUD_ENABLED ? OPT_MODE_DEVICE : OPT_MODE_HOST )
-#define CFG_TUSB_RHPORT1_MODE   0
-#endif
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
 
+// IAR does not have __builtin_ctz
 #if defined(__ICCARM__)
-  #define __builtin_ctz(x)             __iar_builtin_CLZ(__iar_builtin_RBIT(x))
+  #define __builtin_ctz(x)   __iar_builtin_CLZ(__iar_builtin_RBIT(x))
 #endif
 
+typedef struct {
+  uint32_t reg_base;
+  int32_t irqnum;
+}rusb2_controller_t;
+
+#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
+  #define RUSB2_HAS_HIGHSPEED
+  #define RUSB2_CONTROLLER_COUNT 2
+#else
+  #define RUSB2_CONTROLLER_COUNT 1
+#endif
+
+// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
+static rusb2_controller_t rusb2_controller[] = {
+    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
+    #ifdef RUSB2_HAS_HIGHSPEED
+    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
+    #endif
+};
+
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
-#ifdef CFG_TUSB_RHPORT1_MODE
-#if (CFG_TUSB_RHPORT1_MODE != 0)
-  if (rhport == 1) {
-    NVIC_EnableIRQ(_usb_hs_irqn);
-  }
-#endif
-#endif
-
-#ifdef CFG_TUSB_RHPORT0_MODE
-#if  (CFG_TUSB_RHPORT0_MODE != 0)
-  if (rhport == 0) {
-    NVIC_EnableIRQ(_usb_fs_irqn);
-  }
-#endif
-#endif
+  #if RUSB2_CONTROLLER_COUNT > 1
+  NVIC_EnableIRQ(rusb2_controller[rhport].irqnum);
+  #else
+  (void) rhport;
+  NVIC_EnableIRQ(rusb2_controller[0].irqnum);
+  #endif
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport)
 {
-#ifdef CFG_TUSB_RHPORT1_MODE
-#if (CFG_TUSB_RHPORT1_MODE != 0)
-  if (rhport == 1) {
-    NVIC_DisableIRQ(_usb_hs_irqn);
-  }
-#endif
-#endif
-
-#ifdef CFG_TUSB_RHPORT0_MODE
-#if (CFG_TUSB_RHPORT0_MODE != 0)
-  if (rhport == 0) {
-    NVIC_DisableIRQ(_usb_fs_irqn);
-  }
-#endif
-#endif
+  #if RUSB2_CONTROLLER_COUNT > 1
+  NVIC_DisableIRQ(rusb2_controller[rhport].irqnum);
+  #else
+  (void) rhport;
+  NVIC_DisableIRQ(rusb2_controller[0].irqnum);
+  #endif
 }
 
 // MCU specific PHY init
@@ -103,6 +101,15 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void)
 {
 }
 
+void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
+  #if RUSB2_CONTROLLER_COUNT > 1
+  rusb2_controller[rhport].irqnum = irqnum;
+  #else
+  (void) rhport;
+  rusb2_controller[0].irqnum = irqnum;
+  #endif
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 90ba4f012..0928f5aeb 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -46,10 +46,10 @@ typedef struct {
     volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 8;
+      uint16_t                : 8;
       volatile uint16_t TRCLR : 1; /* [8..8] Transaction Counter Clear */
       volatile uint16_t TRENB : 1; /* [9..9] Transaction Counter Enable */
-      uint16_t : 6;
+      uint16_t                : 6;
     } E_b;
   };
 
@@ -62,7 +62,8 @@ typedef struct {
   };
 } RUSB2_PIPE_TR_t; /* Size = 4 (0x4) */
 
-/* LINK_REG Structure */
+
+/* RUSB2 Registers Structure */
 typedef struct {
   union {
     volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
@@ -74,7 +75,7 @@ typedef struct {
       volatile uint16_t DPRPU : 1; /* [4..4] D+ Line Resistor Control */
       volatile uint16_t DRPD  : 1; /* [5..5] D+/D- Line Resistor Control */
       volatile uint16_t DCFM  : 1; /* [6..6] Controller Function Select */
-      uint16_t                : 1;
+      volatile uint16_t HSE   : 1; // [7..7] High-Speed Operation Enable
       volatile uint16_t CNEN  : 1; /* [8..8] CNEN Single End Receiver Enable */
       uint16_t                : 1;
       volatile uint16_t SCKE  : 1; /* [10..10] USB Clock Enable */
@@ -87,7 +88,7 @@ typedef struct {
 
     struct TU_ATTR_PACKED {
       volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
-      uint16_t : 12;
+      uint16_t                : 12;
     } BUSWAIT_b;
   };
 
@@ -98,8 +99,7 @@ typedef struct {
       volatile const uint16_t LNST   : 2; /* [1..0] USB Data Line Status Monitor */
       volatile const uint16_t IDMON  : 1; /* [2..2] External ID0 Input Pin Monitor */
       uint16_t                       : 2;
-      volatile const uint16_t
-        SOFEA                        : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
+      volatile const uint16_t SOFEA  : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
       volatile const uint16_t HTACT  : 1; /* [6..6] USB Host Sequencer Status Monitor */
       uint16_t                       : 7;
       volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
@@ -111,7 +111,7 @@ typedef struct {
 
     struct TU_ATTR_PACKED {
       volatile const uint16_t PLLLOCK : 1; /* [0..0] PLL Lock Flag */
-      uint16_t : 15;
+      uint16_t                        : 15;
     } PLLSTA_b;
   };
 
@@ -139,7 +139,7 @@ typedef struct {
 
     struct TU_ATTR_PACKED {
       volatile uint16_t UTST : 4; /* [3..0] Test Mode */
-      uint16_t : 12;
+      uint16_t               : 12;
     } TESTMODE_b;
   };
   volatile const uint16_t RESERVED1;
@@ -295,7 +295,7 @@ typedef struct {
     volatile uint16_t INTENB0; /* (@ 0x00000030) Interrupt Enable Register 0 */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 8;
+      uint16_t                : 8;
       volatile uint16_t BRDYE : 1; /* [8..8] Buffer Ready Interrupt Enable */
       volatile uint16_t NRDYE : 1; /* [9..9] Buffer Not Ready Response Interrupt Enable */
       volatile uint16_t BEMPE : 1; /* [10..10] Buffer Empty Interrupt Enable */
@@ -316,7 +316,10 @@ typedef struct {
       volatile uint16_t SACKE      : 1; /* [4..4] Setup Transaction Normal Response Interrupt Enable */
       volatile uint16_t SIGNE      : 1; /* [5..5] Setup Transaction Error Interrupt Enable */
       volatile uint16_t EOFERRE    : 1; /* [6..6] EOF Error Detection Interrupt Enable */
-      uint16_t                     : 4;
+               uint16_t            : 1;
+      volatile uint16_t LPMENDE    : 1; /*!< [8..8] LPM Transaction End Interrupt Enable                               */
+      volatile uint16_t L1RSMENDE  : 1; /*!< [9..9] L1 Resume End Interrupt Enable                                     */
+               uint16_t            : 1;
       volatile uint16_t ATTCHE     : 1; /* [11..11] Connection Detection Interrupt Enable */
       volatile uint16_t DTCHE      : 1; /* [12..12] Disconnection Detection Interrupt Enable */
       uint16_t                     : 1;
@@ -340,7 +343,7 @@ typedef struct {
       volatile uint16_t PIPE7BRDYE : 1; /* [7..7] BRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE8BRDYE : 1; /* [8..8] BRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE9BRDYE : 1; /* [9..9] BRDY Interrupt Enable for PIPE */
-      uint16_t : 6;
+      uint16_t                     : 6;
     } BRDYENB_b;
   };
 
@@ -358,7 +361,7 @@ typedef struct {
       volatile uint16_t PIPE7NRDYE : 1; /* [7..7] NRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE8NRDYE : 1; /* [8..8] NRDY Interrupt Enable for PIPE */
       volatile uint16_t PIPE9NRDYE : 1; /* [9..9] NRDY Interrupt Enable for PIPE */
-      uint16_t : 6;
+      uint16_t                     : 6;
     } NRDYENB_b;
   };
 
@@ -376,7 +379,7 @@ typedef struct {
       volatile uint16_t PIPE7BEMPE : 1; /* [7..7] BEMP Interrupt Enable for PIPE */
       volatile uint16_t PIPE8BEMPE : 1; /* [8..8] BEMP Interrupt Enable for PIPE */
       volatile uint16_t PIPE9BEMPE : 1; /* [9..9] BEMP Interrupt Enable for PIPE */
-      uint16_t : 6;
+      uint16_t                     : 6;
     } BEMPENB_b;
   };
 
@@ -390,7 +393,7 @@ typedef struct {
       volatile uint16_t BRDYM         : 1; /* [6..6] BRDY Interrupt Status Clear Timing */
       uint16_t                        : 1;
       volatile uint16_t TRNENSEL      : 1; /* [8..8] Transaction-Enabled Time Select */
-      uint16_t : 7;
+      uint16_t                        : 7;
     } SOFCFG_b;
   };
 
@@ -467,7 +470,7 @@ typedef struct {
       volatile uint16_t PIPE7BRDY : 1; /* [7..7] BRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE8BRDY : 1; /* [8..8] BRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE9BRDY : 1; /* [9..9] BRDY Interrupt Status for PIPE */
-      uint16_t : 6;
+      uint16_t                    : 6;
     } BRDYSTS_b;
   };
 
@@ -485,7 +488,7 @@ typedef struct {
       volatile uint16_t PIPE7NRDY : 1; /* [7..7] NRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE8NRDY : 1; /* [8..8] NRDY Interrupt Status for PIPE */
       volatile uint16_t PIPE9NRDY : 1; /* [9..9] NRDY Interrupt Status for PIPE */
-      uint16_t : 6;
+      uint16_t                    : 6;
     } NRDYSTS_b;
   };
 
@@ -503,7 +506,7 @@ typedef struct {
       volatile uint16_t PIPE7BEMP : 1; /* [7..7] BEMP Interrupt Status for PIPE */
       volatile uint16_t PIPE8BEMP : 1; /* [8..8] BEMP Interrupt Status for PIPE */
       volatile uint16_t PIPE9BEMP : 1; /* [9..9] BEMP Interrupt Status for PIPE */
-      uint16_t : 6;
+      uint16_t                    : 6;
     } BEMPSTS_b;
   };
 
@@ -609,7 +612,8 @@ typedef struct {
       volatile uint16_t SQCLR       : 1; /* [8..8] Sequence Toggle Bit Clear */
       uint16_t                      : 2;
       volatile uint16_t SUREQCLR    : 1; /* [11..11] SUREQ Bit Clear */
-      uint16_t                      : 2;
+      volatile uint16_t CSSTS       : 1; /* [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status                  */
+      volatile uint16_t CSCLR       : 1; /* [13..13] Split Transaction CSPLIT Status Clear                            */
       volatile uint16_t SUREQ       : 1; /* [14..14] Setup Token Transmission */
       volatile const uint16_t BSTS  : 1; /* [15..15] Buffer Status */
     } DCPCTR_b;
@@ -621,7 +625,7 @@ typedef struct {
 
     struct TU_ATTR_PACKED {
       volatile uint16_t PIPESEL : 4; /* [3..0] Pipe Window Select */
-      uint16_t : 12;
+      uint16_t                  : 12;
     } PIPESEL_b;
   };
   volatile const uint16_t RESERVED11;
@@ -634,21 +638,31 @@ typedef struct {
       volatile uint16_t DIR    : 1; /* [4..4] Transfer Direction */
       uint16_t                 : 2;
       volatile uint16_t SHTNAK : 1; /* [7..7] Pipe Disabled at End of Transfer */
-      uint16_t                 : 1;
+      volatile uint16_t CNTMD  : 1; /* [8..8] Continuous Transfer Mode                                           */
       volatile uint16_t DBLB   : 1; /* [9..9] Double Buffer Mode */
       volatile uint16_t BFRE   : 1; /* [10..10] BRDY Interrupt Operation Specification */
       uint16_t                 : 3;
       volatile uint16_t TYPE   : 2; /* [15..14] Transfer Type */
     } PIPECFG_b;
   };
-  volatile const uint16_t RESERVED12;
+
+  union {
+    volatile uint16_t PIPEBUF;         /*!< (@ 0x0000006A) Pipe Buffer Register                                       */
+
+    struct {
+      volatile uint16_t BUFNMB  : 8; // [7..0] Buffer NumberThese bits specify the FIFO buffer number of the selected pipe (04h to 87h)
+      uint16_t                  : 2;
+      volatile uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes         */
+      uint16_t                  : 1;
+    } PIPEBUF_b;
+  };
 
   union {
     volatile uint16_t PIPEMAXP; /* (@ 0x0000006C) Pipe Maximum Packet Size Register */
 
     struct TU_ATTR_PACKED {
-      volatile uint16_t MXPS   : 9; /* [8..0] Maximum Packet Size */
-      uint16_t                 : 3;
+      volatile uint16_t MXPS   : 11; /* [10..0] Maximum Packet Size */
+      uint16_t                 : 1;
       volatile uint16_t DEVSEL : 4; /* [15..12] Device Select */
     } PIPEMAXP_b;
   };
@@ -694,11 +708,9 @@ typedef struct {
     struct TU_ATTR_PACKED {
       volatile uint16_t RPDME0           : 1; /* [0..0] D- Pin Pull-Down Control */
       volatile uint16_t IDPSRCE0         : 1; /* [1..1] D+ Pin IDPSRC Output Control */
-      volatile uint16_t
-        IDMSINKE0                        : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t IDMSINKE0        : 1; /* [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control */
       volatile uint16_t VDPSRCE0         : 1; /* [3..3] D+ Pin VDPSRC (0.6 V) Output Control */
-      volatile uint16_t
-        IDPSINKE0                        : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
+      volatile uint16_t IDPSINKE0        : 1; /* [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control */
       volatile uint16_t VDMSRCE0         : 1; /* [5..5] D- Pin VDMSRC (0.6 V) Output Control */
       uint16_t                           : 1;
       volatile uint16_t BATCHGE0         : 1; /* [7..7] BC (Battery Charger) Function Ch0 General Enable Control */
@@ -715,7 +727,7 @@ typedef struct {
 
     struct TU_ATTR_PACKED {
       volatile uint16_t UCKSELC : 1; /* [0..0] USB Clock Selection */
-      uint16_t : 15;
+      uint16_t                  : 15;
     } UCKSEL_b;
   };
   volatile const uint16_t RESERVED18;
@@ -737,11 +749,11 @@ typedef struct {
     volatile uint16_t DEVADD[10]; /* (@ 0x000000D0) Device Address Configuration Register */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 6;
+      uint16_t                  : 6;
       volatile uint16_t USBSPD  : 2; /* [7..6] Transfer Speed of Communication Target Device */
       volatile uint16_t HUBPORT : 3; /* [10..8] Communication Target Connecting Hub Port */
       volatile uint16_t UPPHUB  : 4; /* [14..11] Communication Target Connecting Hub Register */
-      uint16_t : 1;
+      uint16_t                  : 1;
     } DEVADD_b[10];
   };
   volatile const uint32_t RESERVED21[3];
@@ -754,7 +766,7 @@ typedef struct {
       volatile uint32_t SLEWR01 : 1; /* [1..1] Receiver Cross Point Adjustment 01 */
       volatile uint32_t SLEWF00 : 1; /* [2..2] Receiver Cross Point Adjustment 00 */
       volatile uint32_t SLEWF01 : 1; /* [3..3] Receiver Cross Point Adjustment 01 */
-      uint32_t : 28;
+      uint32_t                  : 28;
     } PHYSLEW_b;
   };
   volatile const uint32_t RESERVED22[3];
@@ -763,9 +775,9 @@ typedef struct {
     volatile uint16_t LPCTRL; /* (@ 0x00000100) Low Power Control Register */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 7;
+      uint16_t                : 7;
       volatile uint16_t HWUPM : 1; /* [7..7] Resume Return Mode Setting */
-      uint16_t : 8;
+      uint16_t                : 8;
     } LPCTRL_b;
   };
 
@@ -773,9 +785,9 @@ typedef struct {
     volatile uint16_t LPSTS; /* (@ 0x00000102) Low Power Status Register */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 14;
+      uint16_t                   : 14;
       volatile uint16_t SUSPENDM : 1; /* [14..14] UTMI SuspendM Control */
-      uint16_t : 1;
+      uint16_t                   : 1;
     } LPSTS_b;
   };
   volatile const uint32_t RESERVED23[15];
@@ -793,7 +805,7 @@ typedef struct {
       uint16_t                          : 2;
       volatile const uint16_t CHGDETSTS : 1; /* [8..8] CHGDET Status */
       volatile const uint16_t PDDETSTS  : 1; /* [9..9] PDDET Status */
-      uint16_t : 6;
+      uint16_t                          : 6;
     } BCCTRL_b;
   };
   volatile const uint16_t RESERVED24;
@@ -809,7 +821,7 @@ typedef struct {
       volatile uint16_t HIRDTHR    : 4; /* [11..8] L1 Response Negotiation Threshold Value */
       uint16_t                     : 2;
       volatile uint16_t L1EXTMD    : 1; /* [14..14] PHY Control Mode at L1 Return */
-      uint16_t : 1;
+      uint16_t                     : 1;
     } PL1CTRL1_b;
   };
 
@@ -817,10 +829,10 @@ typedef struct {
     volatile uint16_t PL1CTRL2; /* (@ 0x00000146) Function L1 Control Register 2 */
 
     struct TU_ATTR_PACKED {
-      uint16_t : 8;
+      uint16_t                  : 8;
       volatile uint16_t HIRDMON : 4; /* [11..8] HIRD Value Monitor */
       volatile uint16_t RWEMON  : 1;  /* [12..12] RWE Value Monitor */
-      uint16_t : 3;
+      uint16_t                  : 3;
     } PL1CTRL2_b;
   };
 
@@ -830,7 +842,7 @@ typedef struct {
     struct TU_ATTR_PACKED {
       volatile uint16_t L1REQ          : 1;       /* [0..0] L1 Transition Request */
       volatile const uint16_t L1STATUS : 2; /* [2..1] L1 Request Completion Status */
-      uint16_t : 13;
+      uint16_t                         : 13;
     } HL1CTRL1_b;
   };
 
@@ -846,18 +858,48 @@ typedef struct {
       volatile uint16_t BESL   : 1; /* [15..15] BESL & Alternate HIRD */
     } HL1CTRL2_b;
   };
-  volatile const uint32_t RESERVED25[5];
+
+  volatile uint32_t RESERVED25_1;
+
+  union {
+    volatile uint16_t PHYTRIM1;          /*!< (@ 0x00000150) PHY Timing Register 1                                      */
+
+    struct {
+      volatile uint16_t DRISE      : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function              */
+      volatile uint16_t DFALL      : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function             */
+               uint16_t            : 3;
+      volatile uint16_t PCOMPENB   : 1; /*!< [7..7] PVDD Start-up Detection                                            */
+      volatile uint16_t HSIUP      : 4; /*!< [11..8] HS Output Level Setting                                           */
+      volatile uint16_t IMPOFFSET  : 3; /*!< [14..12] terminating resistance offset value setting.Offset value for adjusting the terminating resistance.                           */
+               uint16_t            : 1;
+    } PHYTRIM1_b;
+  };
+
+  union {
+    volatile uint16_t PHYTRIM2;         /*!< (@ 0x00000152) PHY Timing Register 2                                      */
+
+    struct {
+      volatile  uint16_t SQU      : 4; /*!< [3..0] Squelch Detection Level                                            */
+      uint16_t                    : 3;
+      volatile  uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode                                     */
+      volatile  uint16_t PDR      : 2; /*!< [9..8] HS Output Adjustment Function                                      */
+      uint16_t                    : 2;
+      volatile  uint16_t DIS      : 3; /*!< [14..12] Disconnect Detection Level                                       */
+      uint16_t                    : 1;
+    } PHYTRIM2_b;
+  };
+  volatile uint32_t RESERVED25_2[3];
 
   union {
     volatile const uint32_t DPUSR0R; /* (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor Register */
 
     struct TU_ATTR_PACKED {
-      uint32_t : 20;
+      uint32_t                         : 20;
       volatile const uint32_t DOVCAHM  : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
       volatile const uint32_t DOVCBHM  : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
       uint32_t                         : 1;
       volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
-      uint32_t : 8;
+      uint32_t                         : 8;
     } DPUSR0R_b;
   };
 
@@ -865,7 +907,7 @@ typedef struct {
     volatile uint32_t DPUSR1R; /* (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register */
 
     struct TU_ATTR_PACKED {
-      uint32_t : 4;
+      uint32_t                        : 4;
       volatile uint32_t DOVCAHE       : 1; /* [4..4] OVRCURA Interrupt Enable Clear */
       volatile uint32_t DOVCBHE       : 1; /* [5..5] OVRCURB Interrupt Enable Clear */
       uint32_t                        : 1;
@@ -875,7 +917,7 @@ typedef struct {
       volatile const uint32_t DOVCBH  : 1; /* [21..21] Indication of Return from OVRCURB Interrupt Source */
       uint32_t                        : 1;
       volatile const uint32_t DVBSTSH : 1; /* [23..23] Indication of Return from VBUS Interrupt Source */
-      uint32_t : 8;
+      uint32_t                        : 8;
     } DPUSR1R_b;
   };
 
@@ -891,7 +933,7 @@ typedef struct {
       uint16_t                      : 2;
       volatile uint16_t DPINTE      : 1; /* [8..8] DP Interrupt Enable Clear */
       volatile uint16_t DMINTE      : 1; /* [9..9] DM Interrupt Enable Clear */
-      uint16_t : 6;
+      uint16_t                      : 6;
     } DPUSR2R_b;
   };
 
@@ -901,7 +943,7 @@ typedef struct {
     struct TU_ATTR_PACKED {
       volatile uint16_t FIXPHY   : 1; /* [0..0] USB Transceiver Control Fix */
       volatile uint16_t FIXPHYPD : 1; /* [1..1] USB Transceiver Control Fix for PLL */
-      uint16_t : 14;
+      uint16_t                   : 14;
     } DPUSRCR_b;
   };
   volatile const uint32_t RESERVED26[165];
@@ -924,7 +966,7 @@ typedef struct {
       volatile const uint32_t DOVCB0  : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
       uint32_t                        : 1;
       volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
-      uint32_t : 8;
+      uint32_t                        : 8;
     } DPUSR0R_FS_b;
   };
 
@@ -947,10 +989,10 @@ typedef struct {
       volatile const uint32_t DOVRCRB0 : 1; /* [21..21] USB OVRCURB Interrupt Source Recovery */
       uint32_t                         : 1;
       volatile const uint32_t DVBINT0  : 1; /* [23..23] USB VBUS Interrupt Source Recovery */
-      uint32_t : 8;
+      uint32_t                         : 8;
     } DPUSR1R_FS_b;
   };
-} RUSB2_REG_t; /* Size = 1032 (0x408) */
+} rusb2_reg_t; /* Size = 1032 (0x408) */
 
 TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
 TU_ATTR_BIT_FIELD_ORDER_END
@@ -970,13 +1012,15 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_PIPE_TR_N_TRNCNT_Pos      (0UL)        /* TRNCNT (Bit 0) */
 #define RUSB2_PIPE_TR_N_TRNCNT_Msk      (0xffffUL)   /* TRNCNT (Bitfield-Mask: 0xffff) */
 
-// LINK_REG
+// Core Registers
 
 // SYSCFG
 #define RUSB2_SYSCFG_SCKE_Pos           (10UL)       /* SCKE (Bit 10) */
 #define RUSB2_SYSCFG_SCKE_Msk           (0x400UL)    /* SCKE (Bitfield-Mask: 0x01) */
 #define RUSB2_SYSCFG_CNEN_Pos           (8UL)        /* CNEN (Bit 8) */
 #define RUSB2_SYSCFG_CNEN_Msk           (0x100UL)    /* CNEN (Bitfield-Mask: 0x01) */
+#define RUSB2_SYSCFG_HSE_Pos            (7UL)        /*!< HSE (Bit 7)                                           */
+#define RUSB2_SYSCFG_HSE_Msk            (0x80UL)     /*!< HSE (Bitfield-Mask: 0x01)                             */
 #define RUSB2_SYSCFG_DCFM_Pos           (6UL)        /* DCFM (Bit 6) */
 #define RUSB2_SYSCFG_DCFM_Msk           (0x40UL)     /* DCFM (Bitfield-Mask: 0x01) */
 #define RUSB2_SYSCFG_DRPD_Pos           (5UL)        /* DRPD (Bit 5) */
@@ -1135,6 +1179,10 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_INTENB1_DTCHE_Msk         (0x1000UL)   /* DTCHE (Bitfield-Mask: 0x01) */
 #define RUSB2_INTENB1_ATTCHE_Pos        (11UL)       /* ATTCHE (Bit 11) */
 #define RUSB2_INTENB1_ATTCHE_Msk        (0x800UL)    /* ATTCHE (Bitfield-Mask: 0x01) */
+#define RUSB2_INTENB1_L1RSMENDE_Pos     (9UL)        /*!< L1RSMENDE (Bit 9)                                     */
+#define RUSB2_INTENB1_L1RSMENDE_Msk     (0x200UL)    /*!< L1RSMENDE (Bitfield-Mask: 0x01)                       */
+#define RUSB2_INTENB1_LPMENDE_Pos       (8UL)        /*!< LPMENDE (Bit 8)                                       */
+#define RUSB2_INTENB1_LPMENDE_Msk       (0x100UL)    /*!< LPMENDE (Bitfield-Mask: 0x01)                         */
 #define RUSB2_INTENB1_EOFERRE_Pos       (6UL)        /* EOFERRE (Bit 6) */
 #define RUSB2_INTENB1_EOFERRE_Msk       (0x40UL)     /* EOFERRE (Bitfield-Mask: 0x01) */
 #define RUSB2_INTENB1_SIGNE_Pos         (5UL)        /* SIGNE (Bit 5) */
@@ -1299,6 +1347,10 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_DCPCTR_BSTS_Msk           (0x8000UL)   /* BSTS (Bitfield-Mask: 0x01) */
 #define RUSB2_DCPCTR_SUREQ_Pos          (14UL)       /* SUREQ (Bit 14) */
 #define RUSB2_DCPCTR_SUREQ_Msk          (0x4000UL)   /* SUREQ (Bitfield-Mask: 0x01) */
+#define R_USB_HS0_DCPCTR_CSCLR_Pos      (13UL)       /*!< CSCLR (Bit 13)                                        */
+#define RUSB2_DCPCTR_CSCLR_Msk          (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
+#define RUSB2_DCPCTR_CSSTS_Pos          (12UL)       /*!< CSSTS (Bit 12)                                        */
+#define RUSB2_DCPCTR_CSSTS_Msk          (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
 #define RUSB2_DCPCTR_SUREQCLR_Pos       (11UL)       /* SUREQCLR (Bit 11) */
 #define RUSB2_DCPCTR_SUREQCLR_Msk       (0x800UL)    /* SUREQCLR (Bitfield-Mask: 0x01) */
 #define RUSB2_DCPCTR_SQCLR_Pos          (8UL)        /* SQCLR (Bit 8) */
@@ -1325,6 +1377,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_PIPECFG_BFRE_Msk          (0x400UL)    /* BFRE (Bitfield-Mask: 0x01) */
 #define RUSB2_PIPECFG_DBLB_Pos          (9UL)        /* DBLB (Bit 9) */
 #define RUSB2_PIPECFG_DBLB_Msk          (0x200UL)    /* DBLB (Bitfield-Mask: 0x01) */
+#define RUSB2_PIPECFG_CNTMD_Pos         (8UL)        /*!< CNTMD (Bit 8)                                         */
+#define RUSB2_PIPECFG_CNTMD_Msk         (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
 #define RUSB2_PIPECFG_SHTNAK_Pos        (7UL)        /* SHTNAK (Bit 7) */
 #define RUSB2_PIPECFG_SHTNAK_Msk        (0x80UL)     /* SHTNAK (Bitfield-Mask: 0x01) */
 #define RUSB2_PIPECFG_DIR_Pos           (4UL)        /* DIR (Bit 4) */
@@ -1332,6 +1386,12 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_PIPECFG_EPNUM_Pos         (0UL)        /* EPNUM (Bit 0) */
 #define RUSB2_PIPECFG_EPNUM_Msk         (0xfUL)      /* EPNUM (Bitfield-Mask: 0x0f) */
 
+// PIPEBUF
+#define RUSB2_PIPEBUF_BUFSIZE_Pos       (10UL)       /*!< BUFSIZE (Bit 10)                                      */
+#define RUSB2_PIPEBUF_BUFSIZE_Msk       (0x7c00UL)   /*!< BUFSIZE (Bitfield-Mask: 0x1f)                         */
+#define RUSB2_PIPEBUF_BUFNMB_Pos        (0UL)        /*!< BUFNMB (Bit 0)                                        */
+#define RUSB2_PIPEBUF_BUFNMB_Msk        (0xffUL)     /*!< BUFNMB (Bitfield-Mask: 0xff)                          */
+
 // PIPEMAXP
 #define RUSB2_PIPEMAXP_DEVSEL_Pos       (12UL)       /* DEVSEL (Bit 12) */
 #define RUSB2_PIPEMAXP_DEVSEL_Msk       (0xf000UL)   /* DEVSEL (Bitfield-Mask: 0x0f) */
@@ -1478,6 +1538,28 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_HL1CTRL2_L1ADDR_Pos       (0UL)        /* L1ADDR (Bit 0) */
 #define RUSB2_HL1CTRL2_L1ADDR_Msk       (0xfUL)      /* L1ADDR (Bitfield-Mask: 0x0f) */
 
+// PHYTRIM1
+#define RUSB2_PHYTRIM1_IMPOFFSET_Pos    (12UL)       /*!< IMPOFFSET (Bit 12)                                    */
+#define RUSB2_PHYTRIM1_IMPOFFSET_Msk    (0x7000UL)   /*!< IMPOFFSET (Bitfield-Mask: 0x07)                       */
+#define RUSB2_PHYTRIM1_HSIUP_Pos        (8UL)        /*!< HSIUP (Bit 8)                                         */
+#define RUSB2_PHYTRIM1_HSIUP_Msk        (0xf00UL)    /*!< HSIUP (Bitfield-Mask: 0x0f)                           */
+#define RUSB2_PHYTRIM1_PCOMPENB_Pos     (7UL)        /*!< PCOMPENB (Bit 7)                                      */
+#define RUSB2_PHYTRIM1_PCOMPENB_Msk     (0x80UL)     /*!< PCOMPENB (Bitfield-Mask: 0x01)                        */
+#define RUSB2_PHYTRIM1_DFALL_Pos        (2UL)        /*!< DFALL (Bit 2)                                         */
+#define RUSB2_PHYTRIM1_DFALL_Msk        (0xcUL)      /*!< DFALL (Bitfield-Mask: 0x03)                           */
+#define RUSB2_PHYTRIM1_DRISE_Pos        (0UL)        /*!< DRISE (Bit 0)                                         */
+#define RUSB2_PHYTRIM1_DRISE_Msk        (0x3UL)      /*!< DRISE (Bitfield-Mask: 0x03)                           */
+
+// PHYTRIM2
+#define RUSB2_PHYTRIM2_DIS_Pos          (12UL)       /*!< DIS (Bit 12)                                          */
+#define RUSB2_PHYTRIM2_DIS_Msk          (0x7000UL)   /*!< DIS (Bitfield-Mask: 0x07)                             */
+#define RUSB2_PHYTRIM2_PDR_Pos          (8UL)        /*!< PDR (Bit 8)                                           */
+#define RUSB2_PHYTRIM2_PDR_Msk          (0x300UL)    /*!< PDR (Bitfield-Mask: 0x03)                             */
+#define RUSB2_PHYTRIM2_HSRXENMO_Pos     (7UL)        /*!< HSRXENMO (Bit 7)                                      */
+#define RUSB2_PHYTRIM2_HSRXENMO_Msk     (0x80UL)     /*!< HSRXENMO (Bitfield-Mask: 0x01)                        */
+#define RUSB2_PHYTRIM2_SQU_Pos          (0UL)        /*!< SQU (Bit 0)                                           */
+#define RUSB2_PHYTRIM2_SQU_Msk          (0xfUL)      /*!< SQU (Bitfield-Mask: 0x0f)                             */
+
 // DPUSR0R
 #define RUSB2_DPUSR0R_DVBSTSHM_Pos      (23UL)       /* DVBSTSHM (Bit 23) */
 #define RUSB2_DPUSR0R_DVBSTSHM_Msk      (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
@@ -1599,69 +1681,72 @@ TU_ATTR_BIT_FIELD_ORDER_END
 //--------------------------------------------------------------------+
 
 TU_VERIFY_STATIC(sizeof(RUSB2_PIPE_TR_t) == 4, "incorrect size");
-TU_VERIFY_STATIC(sizeof(RUSB2_REG_t) == 1032, "incorrect size");
+TU_VERIFY_STATIC(sizeof(rusb2_reg_t) == 1032, "incorrect size");
 
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSCFG     ) == 0x00000000, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BUSWAIT    ) == 0x00000002, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SYSSTS0    ) == 0x00000004, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PLLSTA     ) == 0x00000006, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DVSTCTR0   ) == 0x00000008, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, TESTMODE   ) == 0x0000000C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFO      ) == 0x00000014, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFO     ) == 0x00000018, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFO     ) == 0x0000001C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOSEL   ) == 0x00000020, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, CFIFOCTR   ) == 0x00000022, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOSEL  ) == 0x00000028, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D0FIFOCTR  ) == 0x0000002A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOSEL  ) == 0x0000002C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, D1FIFOCTR  ) == 0x0000002E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB0    ) == 0x00000030, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTENB1    ) == 0x00000032, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYENB    ) == 0x00000036, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYENB    ) == 0x00000038, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPENB    ) == 0x0000003A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, SOFCFG     ) == 0x0000003C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSET     ) == 0x0000003E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS0    ) == 0x00000040, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, INTSTS1    ) == 0x00000042, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BRDYSTS    ) == 0x00000046, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, NRDYSTS    ) == 0x00000048, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BEMPSTS    ) == 0x0000004A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, FRMNUM     ) == 0x0000004C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UFRMNUM    ) == 0x0000004E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBADDR    ) == 0x00000050, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBREQ     ) == 0x00000054, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBVAL     ) == 0x00000056, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBINDX    ) == 0x00000058, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBLENG    ) == 0x0000005A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCFG     ) == 0x0000005C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPMAXP    ) == 0x0000005E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DCPCTR     ) == 0x00000060, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPESEL    ) == 0x00000064, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPECFG    ) == 0x00000068, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEMAXP   ) == 0x0000006C, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPEPERI   ) == 0x0000006E, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_CTR   ) == 0x00000070, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PIPE_TR    ) == 0x00000090, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, UCKSEL     ) == 0x000000C4, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, USBMC      ) == 0x000000CC, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DEVADD     ) == 0x000000D0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PHYSLEW    ) == 0x000000F0, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPCTRL     ) == 0x00000100, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, LPSTS      ) == 0x00000102, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, BCCTRL     ) == 0x00000140, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL1   ) == 0x00000144, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, PL1CTRL2   ) == 0x00000146, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL1   ) == 0x00000148, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, HL1CTRL2   ) == 0x0000014A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R    ) == 0x00000160, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R    ) == 0x00000164, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR2R    ) == 0x00000168, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSRCR    ) == 0x0000016A, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset");
-TU_VERIFY_STATIC(offsetof(RUSB2_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSCFG     ) == 0x0000, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BUSWAIT    ) == 0x0002, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SYSSTS0    ) == 0x0004, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PLLSTA     ) == 0x0006, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DVSTCTR0   ) == 0x0008, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, TESTMODE   ) == 0x000C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFO      ) == 0x0014, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFO     ) == 0x0018, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFO     ) == 0x001C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOSEL   ) == 0x0020, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, CFIFOCTR   ) == 0x0022, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOSEL  ) == 0x0028, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D0FIFOCTR  ) == 0x002A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOSEL  ) == 0x002C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, D1FIFOCTR  ) == 0x002E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB0    ) == 0x0030, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTENB1    ) == 0x0032, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYENB    ) == 0x0036, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYENB    ) == 0x0038, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPENB    ) == 0x003A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, SOFCFG     ) == 0x003C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSET     ) == 0x003E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS0    ) == 0x0040, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, INTSTS1    ) == 0x0042, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BRDYSTS    ) == 0x0046, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, NRDYSTS    ) == 0x0048, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BEMPSTS    ) == 0x004A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, FRMNUM     ) == 0x004C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UFRMNUM    ) == 0x004E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBADDR    ) == 0x0050, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBREQ     ) == 0x0054, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBVAL     ) == 0x0056, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBINDX    ) == 0x0058, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBLENG    ) == 0x005A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCFG     ) == 0x005C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPMAXP    ) == 0x005E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DCPCTR     ) == 0x0060, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPESEL    ) == 0x0064, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPECFG    ) == 0x0068, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEBUF    ) == 0x006A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEMAXP   ) == 0x006C, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPEPERI   ) == 0x006E, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_CTR   ) == 0x0070, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PIPE_TR    ) == 0x0090, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBBCCTRL0 ) == 0x00B0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, UCKSEL     ) == 0x00C4, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, USBMC      ) == 0x00CC, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DEVADD     ) == 0x00D0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYSLEW    ) == 0x00F0, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPCTRL     ) == 0x0100, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, LPSTS      ) == 0x0102, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, BCCTRL     ) == 0x0140, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL1   ) == 0x0144, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PL1CTRL2   ) == 0x0146, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL1   ) == 0x0148, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, HL1CTRL2   ) == 0x014A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM1   ) == 0x0150, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, PHYTRIM2   ) == 0x0152, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R    ) == 0x0160, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R    ) == 0x0164, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR2R    ) == 0x0168, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSRCR    ) == 0x016A, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR0R_FS ) == 0x0400, "incorrect offset");
+TU_VERIFY_STATIC(offsetof(rusb2_reg_t, DPUSR1R_FS ) == 0x0404, "incorrect offset");
 
 #ifdef __cplusplus
 }

From 95b77a0e7356b5f6625fbdb66f35415db3aac7a9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 6 Jul 2023 15:54:07 +0700
Subject: [PATCH 1882/2085] add rusb2_module_start(), more update for multiple
 ports for dcd rusb2

---
 hw/bsp/ra/family.c                      |   7 -
 src/portable/renesas/rusb2/dcd_rusb2.c  | 278 ++++++++++++++----------
 src/portable/renesas/rusb2/rusb2_ra.h   |  40 ++--
 src/portable/renesas/rusb2/rusb2_rx.h   |   6 +
 src/portable/renesas/rusb2/rusb2_type.h |   1 +
 5 files changed, 190 insertions(+), 142 deletions(-)

diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 36b46beab..2c21a9967 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -104,13 +104,6 @@ void board_init(void) {
   R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01;
 #endif
 
-  // Enable USB module
-  R_MSTP->MSTPCRB &= ~(1U << 11U); // FS
-
-#ifdef BOARD_HAS_USB_HIGHSPEED
-  R_MSTP->MSTPCRB &= ~(1U << 12U);
-#endif
-
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USBFS_INT_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index b58e0be01..27d525b68 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -65,9 +65,9 @@
 
 /* LINK core registers */
 #if defined(__CCRX__)
-  #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
+  #define RUSB2 ((rusb2_reg_t __evenaccess*) RUSB2_REG_BASE)
 #elif defined(__RX__)
-  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
+  #define RUSB2 ((rusb2_reg_t*) RUSB2_REG_BASE)
 #elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
   #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE)
 #else
@@ -145,10 +145,15 @@ typedef struct
   uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
 } dcd_data_t;
 
+static dcd_data_t _dcd;
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-static dcd_data_t _dcd;
+
+TU_ATTR_ALWAYS_INLINE static inline bool is_highspeed(uint8_t rhport) {
+  return rhport == 1;
+}
 
 static unsigned find_pipe(unsigned xfer)
 {
@@ -543,38 +548,60 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
 
 static void process_bus_reset(uint8_t rhport)
 {
-  RUSB2->BEMPENB = 1;
-  RUSB2->BRDYENB = 1;
-  RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
-  RUSB2->D0FIFOSEL = 0;
-  while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  RUSB2->D1FIFOSEL = 0;
-  while (RUSB2->D1FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
-  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_CTR[0]));
-  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&RUSB2->PIPE_TR[0].E));
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  rusb->BEMPENB = 1;
+  rusb->BRDYENB = 1;
+  rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  rusb->D1FIFOSEL = 0;
+  while (rusb->D1FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  volatile uint16_t *ctr = (volatile uint16_t*)((uintptr_t) (&rusb->PIPE_CTR[0]));
+  volatile uint16_t *tre = (volatile uint16_t*)((uintptr_t) (&rusb->PIPE_TR[0].E));
+
   for (int i = 1; i <= 5; ++i) {
-    RUSB2->PIPESEL = i;
-    RUSB2->PIPECFG = 0;
+    rusb->PIPESEL = i;
+    rusb->PIPECFG = 0;
     *ctr = RUSB2_PIPE_CTR_ACLRM_Msk;
     *ctr = 0;
     ++ctr;
     *tre = TU_BIT(8);
     tre += 2;
   }
+
   for (int i = 6; i <= 9; ++i) {
-    RUSB2->PIPESEL = i;
-    RUSB2->PIPECFG = 0;
+    rusb->PIPESEL = i;
+    rusb->PIPECFG = 0;
     *ctr = RUSB2_PIPE_CTR_ACLRM_Msk;
     *ctr = 0;
     ++ctr;
   }
   tu_varclr(&_dcd);
 
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, true);
-#else
-  dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
-#endif
+  TU_LOG3("Bus reset, RHST = %u\r\n", rusb->DVSTCTR0_b.RHST);
+  tusb_speed_t speed;
+  switch(rusb->DVSTCTR0 & RUSB2_DVSTCTR0_RHST_Msk) {
+    case RUSB2_DVSTCTR0_RHST_LS:
+      speed = TUSB_SPEED_LOW;
+      break;
+
+    case RUSB2_DVSTCTR0_RHST_FS:
+      speed = TUSB_SPEED_FULL;
+      break;
+
+    case RUSB2_DVSTCTR0_RHST_HS:
+      speed = TUSB_SPEED_HIGH;
+      break;
+
+    default:
+      TU_ASSERT(false, );
+  }
+
+  dcd_event_bus_reset(rhport, speed, true);
 }
 
 static void process_set_address(uint8_t rhport)
@@ -625,56 +652,63 @@ static void enable_interrupt(uint32_t pswi)
 
 void dcd_init(uint8_t rhport)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
 
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  RUSB2->SYSCFG_b.HSE = 1;
-  RUSB2->PHYSET_b.DIRPD = 0;
-  R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
-  RUSB2->PHYSET_b.PLLRESET = 0;
-  //RUSB2->PHYSET_b.REPSTART = 1;
-  RUSB2->SYSCFG_b.DRPD = 0;
-  RUSB2->SYSCFG_b.USBE = 1;
-  RUSB2->LPSTS_b.SUSPENDM = 1;
-  while (!RUSB2->PLLSTA_b.PLLLOCK);
-  //RUSB2->BUSWAIT |= 0x0F00U;
-  //RUSB2->PHYSET_b.REPSEL = 1;
-  RUSB2->CFIFOSEL_b.MBW = 1;
-  RUSB2->D0FIFOSEL_b.MBW = 1;
-  RUSB2->D1FIFOSEL_b.MBW = 1;
-  RUSB2->INTSTS0 = 0;
-#else
-  RUSB2->SYSCFG_b.SCKE = 1;
-  while (!RUSB2->SYSCFG_b.SCKE) ;
-  RUSB2->SYSCFG_b.DRPD = 0;
-  RUSB2->SYSCFG_b.DCFM = 0;
-  RUSB2->SYSCFG_b.USBE = 1;
-#endif
+  rusb2_module_start(rhport, true);
 
-  // MCU specific PHY init
-  rusb2_phy_init();
+  if ( is_highspeed(rhport) ) {
+    rusb->SYSCFG_b.HSE = 1;
 
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-  RUSB2->PHYSLEW = 0x5;
-  RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
+    // leave CLKSEL as default (0x11) 24Mhz
 
-  #define USB_VDCEN                 (0x0080U) /* b7: Regulator ON/OFF control */
-  RUSB2->USBMC = (uint16_t) (RUSB2->USBMC | (USB_VDCEN));
-#endif
+    // Power and reset UTMI Phy
+    uint16_t physet = (rusb->PHYSET | RUSB2_PHYSET_PLLRESET_Msk) & ~RUSB2_PHYSET_DIRPD_Msk;
+    rusb->PHYSET = physet;
+    R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
+    rusb->PHYSET_b.PLLRESET = 0;
+
+    // set UTMI to operating mode and wait for PLL lock confirmation
+    rusb->LPSTS_b.SUSPENDM = 1;
+    while (!rusb->PLLSTA_b.PLLLOCK) {}
+
+    rusb->SYSCFG_b.DRPD = 0;
+    rusb->SYSCFG_b.USBE = 1;
+
+    // Set CPU bus wait time (fine tunne later)
+    // rusb2->BUSWAIT |= 0x0F00U;
+
+    rusb->PHYSET_b.REPSEL = 1;
+
+    rusb->CFIFOSEL_b.MBW = 1;
+    rusb->D0FIFOSEL_b.MBW = 1;
+    rusb->D1FIFOSEL_b.MBW = 1;
+  } else {
+    rusb->SYSCFG_b.SCKE = 1;
+    while (!rusb->SYSCFG_b.SCKE) {}
+    rusb->SYSCFG_b.DRPD = 0;
+    rusb->SYSCFG_b.DCFM = 0;
+    rusb->SYSCFG_b.USBE = 1;
+
+    // MCU specific PHY init
+    rusb2_phy_init();
+
+    rusb->PHYSLEW = 0x5;
+    rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
+
+    // rusb2->USBMC = (uint16_t) (rusb2->USBMC | RUSB2_USBMC_VDCEN_Msk);
+  }
 
   /* Setup default control pipe */
-  RUSB2->DCPMAXP_b.MXPS = 64;
-  RUSB2->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
-          RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
-          RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk;
-  RUSB2->BEMPENB = 1;
-  RUSB2->BRDYENB = 1;
+  rusb->DCPMAXP_b.MXPS = 64;
 
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_DEVICE)
-  RUSB2->SYSCFG_b.DPRPU = 1;  /* necessary in this position */
-#endif
+  rusb->INTSTS0 = 0;
+  rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
+                  RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
+                  RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk;
+  rusb->BEMPENB = 1;
+  rusb->BRDYENB = 1;
 
-  if (RUSB2->INTSTS0_b.VBSTS) {
+  if (rusb->INTSTS0_b.VBSTS) {
     dcd_connect(rhport);
   }
 }
@@ -697,24 +731,24 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 
 void dcd_remote_wakeup(uint8_t rhport)
 {
-  (void)rhport;
-  RUSB2->DVSTCTR0_b.WKUP = 1;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb->DVSTCTR0_b.WKUP = 1;
 }
 
 void dcd_connect(uint8_t rhport)
 {
-  (void)rhport;
-  #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  RUSB2->SYSCFG_b.CNEN = 1;
-  R_BSP_SoftwareDelay((uint32_t) 10, BSP_DELAY_UNITS_MILLISECONDS);
-  #endif
-  RUSB2->SYSCFG_b.DPRPU = 1;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  if ( is_highspeed(rhport)) {
+    rusb->SYSCFG_b.CNEN = 1;
+  }
+  rusb->SYSCFG_b.DPRPU = 1;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
-  (void)rhport;
-  RUSB2->SYSCFG_b.DPRPU = 0;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb->SYSCFG_b.DPRPU = 0;
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -861,76 +895,94 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 //--------------------------------------------------------------------+
 void dcd_int_handler(uint8_t rhport)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
+  uint16_t is0 = rusb->INTSTS0;
 
-  unsigned is0 = RUSB2->INTSTS0;
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk |
-                         RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk;
-  if (is0 & RUSB2_INTSTS0_VBINT_Msk) {
-    if (RUSB2->INTSTS0_b.VBSTS) {
+  rusb->INTSTS0 = ~((RUSB2_INTSTS0_CTRT_Msk | RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_SOFR_Msk |
+                     RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_VBINT_Msk) & is0) | RUSB2_INTSTS0_VALID_Msk;
+
+  // VBUS changes
+  if ( is0 & RUSB2_INTSTS0_VBINT_Msk ) {
+    if ( rusb->INTSTS0_b.VBSTS ) {
       dcd_connect(rhport);
     } else {
       dcd_disconnect(rhport);
     }
   }
-  if (is0 & RUSB2_INTSTS0_RESM_Msk) {
+
+  // Resumed
+  if ( is0 & RUSB2_INTSTS0_RESM_Msk ) {
     dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
-#if (0==USE_SOF)
-    RUSB2->INTENB0_b.SOFE = 0;
+#if (0 == USE_SOF)
+    rusb->INTENB0_b.SOFE = 0;
 #endif
   }
-  if ((is0 & RUSB2_INTSTS0_SOFR_Msk) && RUSB2->INTENB0_b.SOFE) {
+
+  // SOF received
+  if ( (is0 & RUSB2_INTSTS0_SOFR_Msk) && rusb->INTENB0_b.SOFE ) {
     // USBD will exit suspended mode when SOF event is received
     dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
 #if (0 == USE_SOF)
-    RUSB2->INTENB0_b.SOFE = 0;
+    rusb->INTENB0_b.SOFE = 0;
 #endif
   }
-  if (is0 & RUSB2_INTSTS0_DVST_Msk) {
+
+  // Device state changes
+  if ( is0 & RUSB2_INTSTS0_DVST_Msk ) {
     switch (is0 & RUSB2_INTSTS0_DVSQ_Msk) {
-    case RUSB2_INTSTS0_DVSQ_STATE_DEF:
-      process_bus_reset(rhport);
-      break;
-    case RUSB2_INTSTS0_DVSQ_STATE_ADDR:
-      process_set_address(rhport);
-      break;
-    case RUSB2_INTSTS0_DVSQ_STATE_SUSP0:
-    case RUSB2_INTSTS0_DVSQ_STATE_SUSP1:
-    case RUSB2_INTSTS0_DVSQ_STATE_SUSP2:
-    case RUSB2_INTSTS0_DVSQ_STATE_SUSP3:
-       dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
-#if (0==USE_SOF)
-      RUSB2->INTENB0_b.SOFE = 1;
+      case RUSB2_INTSTS0_DVSQ_STATE_DEF:
+        process_bus_reset(rhport);
+        break;
+
+      case RUSB2_INTSTS0_DVSQ_STATE_ADDR:
+        process_set_address(rhport);
+        break;
+
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP0:
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP1:
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP2:
+      case RUSB2_INTSTS0_DVSQ_STATE_SUSP3:
+        dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
+#if (0 == USE_SOF)
+        rusb->INTENB0_b.SOFE = 1;
 #endif
-    default:
-      break;
+
+      default: break;
     }
   }
-  if (is0 & RUSB2_INTSTS0_NRDY_Msk) {
-    RUSB2->NRDYSTS = 0;
+
+  if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) {
+    rusb->NRDYSTS = 0;
   }
-  if (is0 & RUSB2_INTSTS0_CTRT_Msk) {
-    if (is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA) {
+
+  // Control transfer stage changes
+  if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) {
+    if ( is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA ) {
       /* A setup packet has been received. */
       process_setup_packet(rhport);
-    } else if (0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk)) {
+    } else if ( 0 == (is0 & RUSB2_INTSTS0_CTSQ_Msk) ) {
       /* A ZLP has been sent/received. */
       process_status_completion(rhport);
     }
   }
-  if (is0 & RUSB2_INTSTS0_BEMP_Msk) {
-    const unsigned s = RUSB2->BEMPSTS;
-    RUSB2->BEMPSTS = 0;
-    if (s & 1) {
+
+  // Buffer empty
+  if ( is0 & RUSB2_INTSTS0_BEMP_Msk ) {
+    const unsigned s = rusb->BEMPSTS;
+    rusb->BEMPSTS = 0;
+    if ( s & 1 ) {
       process_pipe0_bemp(rhport);
     }
   }
-  if (is0 & RUSB2_INTSTS0_BRDY_Msk) {
-    const unsigned m = RUSB2->BRDYENB;
-    unsigned s = RUSB2->BRDYSTS & m;
+
+  // Buffer ready
+  if ( is0 & RUSB2_INTSTS0_BRDY_Msk ) {
+    const unsigned m = rusb->BRDYENB;
+    unsigned s = rusb->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    RUSB2->BRDYSTS = ~s;
+    rusb->BRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       static const int Mod37BitPosition[] = {
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index ca7c38907..0dc59331a 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -76,38 +76,34 @@ static rusb2_controller_t rusb2_controller[] = {
     #endif
 };
 
-TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
-{
-  #if RUSB2_CONTROLLER_COUNT > 1
-  NVIC_EnableIRQ(rusb2_controller[rhport].irqnum);
-  #else
-  (void) rhport;
-  NVIC_EnableIRQ(rusb2_controller[0].irqnum);
-  #endif
+#define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
+
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
+  uint32_t const mask = 1U << (11+rhport);
+  if (start) {
+    R_MSTP->MSTPCRB &= ~mask;
+  }else {
+    R_MSTP->MSTPCRB |= mask;
+  }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport)
-{
-  #if RUSB2_CONTROLLER_COUNT > 1
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport) {
+  NVIC_EnableIRQ(rusb2_controller[rhport].irqnum);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) {
   NVIC_DisableIRQ(rusb2_controller[rhport].irqnum);
-  #else
-  (void) rhport;
-  NVIC_DisableIRQ(rusb2_controller[0].irqnum);
-  #endif
 }
 
 // MCU specific PHY init
-TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void)
-{
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) {
 }
 
+//--------------------------------------------------------------------+
+// Application API for setting IRQ number
+//--------------------------------------------------------------------+
 void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
-  #if RUSB2_CONTROLLER_COUNT > 1
   rusb2_controller[rhport].irqnum = irqnum;
-  #else
-  (void) rhport;
-  rusb2_controller[0].irqnum = irqnum;
-  #endif
 }
 
 #ifdef __cplusplus
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
index 397c0d56c..d7f4e0b42 100644
--- a/src/portable/renesas/rusb2/rusb2_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -37,6 +37,12 @@ extern "C" {
 
 #define RUSB2_REG_BASE (0x000A0000)
 
+// Start/Stop MSTP TODO implement later
+TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
+  (void) rhport;
+  (void) start;
+}
+
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_enable(uint8_t rhport)
 {
   (void) rhport;
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 0928f5aeb..b704626f6 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -1653,6 +1653,7 @@ TU_ATTR_BIT_FIELD_ORDER_END
 
 #define RUSB2_DVSTCTR0_RHST_LS          (1U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Low-speed connection */
 #define RUSB2_DVSTCTR0_RHST_FS          (2U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
+#define RUSB2_DVSTCTR0_RHST_HS          (3U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */
 
 #define RUSB2_DEVADD_USBSPD_LS          (1U << RUSB2_DEVADD_USBSPD_Pos)   /* Target Device Low-speed */
 #define RUSB2_DEVADD_USBSPD_FS          (2U << RUSB2_DEVADD_USBSPD_Pos)   /* Target Device Full-speed */

From 1eefc2b3ef2e268e839002a8b5221eebe26f6cd3 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 6 Jul 2023 19:35:42 +0700
Subject: [PATCH 1883/2085] more multiple ports update

---
 src/portable/renesas/rusb2/dcd_rusb2.c  | 344 ++++++++++++++----------
 src/portable/renesas/rusb2/rusb2_rx.h   |   2 +
 src/portable/renesas/rusb2/rusb2_type.h |   9 +-
 3 files changed, 208 insertions(+), 147 deletions(-)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 27d525b68..833737181 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -63,22 +63,11 @@
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-/* LINK core registers */
-#if defined(__CCRX__)
-  #define RUSB2 ((rusb2_reg_t __evenaccess*) RUSB2_REG_BASE)
-#elif defined(__RX__)
-  #define RUSB2 ((rusb2_reg_t*) RUSB2_REG_BASE)
-#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  #define RUSB2 ((R_USB_HS0_Type*)R_USB_HS0_BASE)
-#else
-  #define RUSB2 ((R_USB_FS0_Type*)R_USB_FS0_BASE)
-#endif
-
 /* Start of definition of packed structs (used by the CCRX toolchain) */
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
-typedef struct TU_ATTR_PACKED {
+typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
   union {
     struct {
       uint16_t      : 8;
@@ -186,52 +175,53 @@ static unsigned find_pipe(unsigned xfer)
   return 0;
 }
 
-static volatile uint16_t* get_pipectr(unsigned num)
+static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num)
 {
   if (num) {
-    return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]);
+    return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]);
   } else {
-    return (volatile uint16_t*)&(RUSB2->DCPCTR);
+    return (volatile uint16_t*)&(rusb->DCPCTR);
   }
 }
 
-static volatile reg_pipetre_t* get_pipetre(unsigned num)
+static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num)
 {
   volatile reg_pipetre_t* tre = NULL;
   if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E);
+    tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E);
   }
   return tre;
 }
 
 static volatile uint16_t* ep_addr_to_pipectr(uint8_t rhport, unsigned ep_addr)
 {
-  (void)rhport;
+  rusb2_reg_t *rusb = RUSB2_REG(rhport);
   const unsigned epn = tu_edpt_number(ep_addr);
+
   if (epn) {
     const unsigned dir = tu_edpt_dir(ep_addr);
     const unsigned num = _dcd.ep[dir][epn];
-    return get_pipectr(num);
+    return get_pipectr(rusb, num);
   } else {
-    return get_pipectr(0);
+    return get_pipectr(rusb, 0);
   }
 }
 
-static unsigned edpt0_max_packet_size(void)
+static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb)
 {
-  return RUSB2->DCPMAXP_b.MXPS;
+  return rusb->DCPMAXP_b.MXPS;
 }
 
-static unsigned edpt_max_packet_size(unsigned num)
+static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num)
 {
-  RUSB2->PIPESEL = num;
-  return RUSB2->PIPEMAXP;
+  rusb->PIPESEL = num;
+  return rusb->PIPEMAXP;
 }
 
-static inline void pipe_wait_for_ready(unsigned num)
+static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num)
 {
-  while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ;
-  while (!RUSB2->D0FIFOCTR_b.FRDY) ;
+  while ( rusb->D0FIFOSEL_b.CURPIPE != num ) {}
+  while ( !rusb->D0FIFOCTR_b.FRDY ) {}
 }
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -284,61 +274,70 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
   ops[dir].tu_fifo_advance(f, total_len - rem);
 }
 
-static bool pipe0_xfer_in(void)
+static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_dcd.pipe[0];
   const unsigned rem = pipe->remaining;
+
   if (!rem) {
     pipe->buf = NULL;
     return true;
   }
-  const unsigned mps = edpt0_max_packet_size();
-  const unsigned len = TU_MIN(mps, rem);
+
+  const uint16_t mps = edpt0_max_packet_size(rusb);
+  const uint16_t len = tu_min16(mps, rem);
   void          *buf = pipe->buf;
+
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
+      pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
+
   if (len < mps) {
-    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
+
   pipe->remaining = rem - len;
   return false;
 }
 
-static bool pipe0_xfer_out(void)
+static bool pipe0_xfer_out(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_dcd.pipe[0];
   const unsigned rem = pipe->remaining;
 
-  const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = RUSB2->CFIFOCTR_b.DTLN;
-  const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
+  const uint16_t mps = edpt0_max_packet_size(rusb);
+  const uint16_t vld = rusb->CFIFOCTR_b.DTLN;
+  const uint16_t len = tu_min16(tu_min16(rem, mps), vld);
   void          *buf = pipe->buf;
+
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->CFIFO, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
+      pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
+
   if (len < mps) {
-    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
+
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return true;
   }
+
   return false;
 }
 
-static bool pipe_xfer_in(unsigned num)
+static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
 {
   pipe_state_t  *pipe = &_dcd.pipe[num];
   const unsigned rem  = pipe->remaining;
@@ -348,119 +347,141 @@ static bool pipe_xfer_in(unsigned num)
     return true;
   }
 
-  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
-  const unsigned len  = TU_MIN(rem, mps);
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+  const uint16_t mps  = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
+  const uint16_t len  = tu_min16(rem, mps);
   void          *buf  = pipe->buf;
+
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_IN);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_IN);
     } else {
-      pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
+      pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
+
   if (len < mps) {
-    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
-  RUSB2->D0FIFOSEL = 0;
-  while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
   pipe->remaining = rem - len;
+
   return false;
 }
 
-static bool pipe_xfer_out(unsigned num)
+static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
 {
   pipe_state_t  *pipe = &_dcd.pipe[num];
-  const unsigned rem  = pipe->remaining;
+  const uint16_t rem  = pipe->remaining;
 
-  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
-  const unsigned vld  = RUSB2->D0FIFOCTR_b.DTLN;
-  const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
+  const uint16_t mps = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
+
+  const uint16_t vld  = rusb->D0FIFOCTR_b.DTLN;
+  const uint16_t len  = tu_min16(tu_min16(rem, mps), vld);
   void          *buf  = pipe->buf;
+
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&RUSB2->D0FIFO, len, TUSB_DIR_OUT);
+      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_OUT);
     } else {
-      pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
+      pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
+
   if (len < mps) {
-    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
-  RUSB2->D0FIFOSEL = 0;
-  while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return NULL != buf;
   }
+
   return false;
 }
 
 static void process_setup_packet(uint8_t rhport)
 {
-  uint16_t setup_packet[4];
-  if (0 == (RUSB2->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return;
-  RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
-  setup_packet[0] = tu_le16toh(RUSB2->USBREQ);
-  setup_packet[1] = RUSB2->USBVAL;
-  setup_packet[2] = RUSB2->USBINDX;
-  setup_packet[3] = RUSB2->USBLENG;
-  RUSB2->INTSTS0 = ~((uint16_t)RUSB2_INTSTS0_VALID_Msk);
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  if (0 == (rusb->INTSTS0 & RUSB2_INTSTS0_VALID_Msk)) return;
+
+  rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+  uint16_t setup_packet[4] = {
+      tu_htole16(rusb->USBREQ),
+      tu_htole16(rusb->USBVAL),
+      tu_htole16(rusb->USBINDX),
+      tu_htole16(rusb->USBLENG)
+  };
+
+  rusb->INTSTS0 = ~((uint16_t) RUSB2_INTSTS0_VALID_Msk);
   dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet[0], true);
 }
 
 static void process_status_completion(uint8_t rhport)
 {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   uint8_t ep_addr;
   /* Check the data stage direction */
-  if (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) {
+  if (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) {
     /* IN transfer. */
     ep_addr = tu_edpt_addr(0, TUSB_DIR_IN);
   } else {
     /* OUT transfer. */
     ep_addr = tu_edpt_addr(0, TUSB_DIR_OUT);
   }
+
   dcd_event_xfer_complete(rhport, ep_addr, 0, XFER_RESULT_SUCCESS, true);
 }
 
-static bool process_pipe0_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
+static bool process_pipe0_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
 {
   /* configure fifo direction and access unit settings */
-  if (ep_addr) { /* IN, 2 bytes */
-    RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
-                         (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
-    while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
-  } else { /* OUT, a byte */
-    RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
-    while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
+  if ( ep_addr ) {
+    /* IN, 2 bytes */
+    rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
+                     (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+    while ( !(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ) {}
+  } else {
+    /* OUT, a byte */
+    rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
+    while ( rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE ) {}
   }
 
   pipe_state_t *pipe = &_dcd.pipe[0];
   pipe->ff        = buffer_type;
   pipe->length    = total_bytes;
   pipe->remaining = total_bytes;
-  if (total_bytes) {
-    pipe->buf     = buffer;
-    if (ep_addr) { /* IN */
-      TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80));
-      pipe0_xfer_in();
+
+  if ( total_bytes ) {
+    pipe->buf = buffer;
+    if ( ep_addr ) {
+      /* IN */
+      TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80));
+      pipe0_xfer_in(rusb);
     }
-    RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
+    rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
   } else {
     /* ZLP */
-    pipe->buf        = NULL;
-    RUSB2->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF;
+    pipe->buf = NULL;
+    rusb->DCPCTR = RUSB2_DCPCTR_CCPL_Msk | RUSB2_PIPE_CTR_PID_BUF;
   }
+
   return true;
 }
 
-static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
+static bool process_pipe_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
 {
   const unsigned epn = tu_edpt_number(ep_addr);
   const unsigned dir = tu_edpt_dir(ep_addr);
@@ -473,49 +494,55 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
   pipe->buf       = buffer;
   pipe->length    = total_bytes;
   pipe->remaining = total_bytes;
-  if (dir) { /* IN */
+
+  if (dir) {
+    /* IN */
     if (total_bytes) {
-      pipe_xfer_in(num);
-    } else { /* ZLP */
-      RUSB2->D0FIFOSEL = num;
-      pipe_wait_for_ready(num);
-      RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
-      RUSB2->D0FIFOSEL = 0;
-      while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+      pipe_xfer_in(rusb, num);
+    } else {
+      /* ZLP */
+      rusb->D0FIFOSEL = num;
+      pipe_wait_for_ready(rusb, num);
+      rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      rusb->D0FIFOSEL = 0;
+      /* if CURPIPE bits changes, check written value */
+      while (rusb->D0FIFOSEL_b.CURPIPE) {}
     }
   } else {
-#if defined(__CCRX__)
-    __evenaccess volatile reg_pipetre_t *pt = get_pipetre(num);
-#else
-    volatile reg_pipetre_t *pt = get_pipetre(num);
-#endif
+    // OUT
+    volatile reg_pipetre_t *pt = get_pipetre(rusb, num);
+
     if (pt) {
-      const unsigned     mps = edpt_max_packet_size(num);
-      volatile uint16_t *ctr = get_pipectr(num);
+      const uint16_t     mps = edpt_max_packet_size(rusb, num);
+      volatile uint16_t *ctr = get_pipectr(rusb, num);
+
       if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK;
+
       pt->TRE   = TU_BIT(8);
       pt->TRN   = (total_bytes + mps - 1) / mps;
       pt->TRENB = 1;
       *ctr = RUSB2_PIPE_CTR_PID_BUF;
     }
   }
-  //  TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
+
+  //  TU_LOG2("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
   return true;
 }
 
-static bool process_edpt_xfer(int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
+static bool process_edpt_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
 {
   const unsigned epn = tu_edpt_number(ep_addr);
   if (0 == epn) {
-    return process_pipe0_xfer(buffer_type, ep_addr, buffer, total_bytes);
+    return process_pipe0_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes);
   } else {
-    return process_pipe_xfer(buffer_type, ep_addr, buffer, total_bytes);
+    return process_pipe_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes);
   }
 }
 
 static void process_pipe0_bemp(uint8_t rhport)
 {
-  bool completed = pipe0_xfer_in();
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  bool completed = pipe0_xfer_in(rusb);
   if (completed) {
     pipe_state_t *pipe = &_dcd.pipe[0];
     dcd_event_xfer_complete(rhport, tu_edpt_addr(0, TUSB_DIR_IN),
@@ -525,17 +552,20 @@ static void process_pipe0_bemp(uint8_t rhport)
 
 static void process_pipe_brdy(uint8_t rhport, unsigned num)
 {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   pipe_state_t  *pipe = &_dcd.pipe[num];
   const unsigned dir  = tu_edpt_dir(pipe->ep);
   bool completed;
 
-  if (dir) { /* IN */
-    completed = pipe_xfer_in(num);
+  if (dir) {
+    /* IN */
+    completed = pipe_xfer_in(rusb, num);
   } else {
+    // OUT
     if (num) {
-      completed = pipe_xfer_out(num);
+      completed = pipe_xfer_out(rusb, num);
     } else {
-      completed = pipe0_xfer_out();
+      completed = pipe0_xfer_out(rusb);
     }
   }
   if (completed) {
@@ -606,8 +636,10 @@ static void process_bus_reset(uint8_t rhport)
 
 static void process_set_address(uint8_t rhport)
 {
-  const uint32_t addr = RUSB2->USBADDR & 0xFF;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  const uint32_t addr = rusb->USBADDR & 0xFF;
   if (!addr) return;
+
   const tusb_control_request_t setup_packet = {
 #if defined(__CCRX__)
       .bmRequestType = { 0 },  /* Note: CCRX needs the braces over this struct member */
@@ -618,8 +650,9 @@ static void process_set_address(uint8_t rhport)
       .wValue        = addr,
       .wIndex        = 0,
       .wLength       = 0,
-    };
-  dcd_event_setup_received(rhport, (const uint8_t*)&setup_packet, true);
+  };
+
+  dcd_event_setup_received(rhport, (const uint8_t *) &setup_packet, true);
 }
 
 /*------------------------------------------------------------------*/
@@ -704,7 +737,7 @@ void dcd_init(uint8_t rhport)
   rusb->INTSTS0 = 0;
   rusb->INTENB0 = RUSB2_INTSTS0_VBINT_Msk | RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_BEMP_Msk |
                   RUSB2_INTSTS0_DVST_Msk | RUSB2_INTSTS0_CTRT_Msk | (USE_SOF ? RUSB2_INTSTS0_SOFR_Msk : 0) |
-                  RUSB2_INTSTS0_RESM_Msk | RUSB2_INTSTS0_NRDY_Msk;
+                  RUSB2_INTSTS0_RESM_Msk;
   rusb->BEMPENB = 1;
   rusb->BRDYENB = 1;
 
@@ -766,33 +799,43 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 {
   (void)rhport;
 
+  rusb2_reg_t * rusb = RUSB2_REG(rhport);
   const unsigned ep_addr = ep_desc->bEndpointAddress;
   const unsigned epn     = tu_edpt_number(ep_addr);
   const unsigned dir     = tu_edpt_dir(ep_addr);
   const unsigned xfer    = ep_desc->bmAttributes.xfer;
 
   const unsigned mps = tu_edpt_packet_size(ep_desc);
-  if (xfer == TUSB_XFER_ISOCHRONOUS && mps > 256) {
-    /* USBa supports up to 256 bytes */
-    return false;
+
+  if (xfer == TUSB_XFER_ISOCHRONOUS) {
+    // Fullspeed ISO is limit to 256 bytes
+    if ( !is_highspeed(rhport) && mps > 256) {
+      return false;
+    }
   }
 
   const unsigned num = find_pipe(xfer);
-  if (!num) return false;
+  TU_ASSERT(num);
+
   _dcd.pipe[num].ep = ep_addr;
   _dcd.ep[dir][epn] = num;
 
   /* setup pipe */
   dcd_int_disable(rhport);
-  #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  RUSB2->PIPEBUF = 0x7C08;
-  #endif
-  RUSB2->PIPESEL = num;
-  RUSB2->PIPEMAXP = mps;
-  volatile uint16_t *ctr = get_pipectr(num);
+
+  if ( is_highspeed(rhport) ) {
+    // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed
+    // depending on the allocation scheme
+    rusb->PIPEBUF = 0x7C08;
+  }
+
+  rusb->PIPESEL = num;
+  rusb->PIPEMAXP = mps;
+  volatile uint16_t *ctr = get_pipectr(rusb, num);
   *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk;
   *ctr = 0;
   unsigned cfg = (dir << 4) | epn;
+
   if (xfer == TUSB_XFER_BULK) {
     cfg |= (RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk);
   } else if (xfer == TUSB_XFER_INTERRUPT) {
@@ -800,13 +843,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   } else {
     cfg |= (RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk);
   }
-  RUSB2->PIPECFG = cfg;
-  RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num);
-  RUSB2->BRDYENB |= TU_BIT(num);
+
+  rusb->PIPECFG = cfg;
+  rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  rusb->BRDYENB |= TU_BIT(num);
+
   if (dir || (xfer != TUSB_XFER_BULK)) {
     *ctr = RUSB2_PIPE_CTR_PID_BUF;
   }
-  // TU_LOG1("O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP);
+
+  // TU_LOG1("O %d %x %x\r\n", rusb->PIPESEL, rusb->PIPECFG, rusb->PIPEMAXP);
   dcd_int_enable(rhport);
 
   return true;
@@ -826,26 +872,28 @@ void dcd_edpt_close_all(uint8_t rhport)
 
 void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
 {
-  (void)rhport;
+  rusb2_reg_t * rusb = RUSB2_REG(rhport);
   const unsigned epn = tu_edpt_number(ep_addr);
   const unsigned dir = tu_edpt_dir(ep_addr);
   const unsigned num = _dcd.ep[dir][epn];
 
-  RUSB2->BRDYENB &= ~TU_BIT(num);
-  volatile uint16_t *ctr = get_pipectr(num);
+  rusb->BRDYENB &= ~TU_BIT(num);
+  volatile uint16_t *ctr = get_pipectr(rusb, num);
   *ctr = 0;
-  RUSB2->PIPESEL = num;
-  RUSB2->PIPECFG = 0;
+  rusb->PIPESEL = num;
+  rusb->PIPECFG = 0;
   _dcd.pipe[num].ep = 0;
   _dcd.ep[dir][epn] = 0;
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
 {
-  bool r;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
   dcd_int_disable(rhport);
-  r = process_edpt_xfer(0, ep_addr, buffer, total_bytes);
+  bool r = process_edpt_xfer(rusb, 0, ep_addr, buffer, total_bytes);
   dcd_int_enable(rhport);
+
   return r;
 }
 
@@ -853,10 +901,12 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_
 {
   // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1
   TU_ASSERT(ff->item_size == 1);
-  bool r;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
   dcd_int_disable(rhport);
-  r = process_edpt_xfer(1, ep_addr, ff, total_bytes);
+  bool r = process_edpt_xfer(rusb, 1, ep_addr, ff, total_bytes);
   dcd_int_enable(rhport);
+
   return r;
 }
 
@@ -873,8 +923,10 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
+  rusb2_reg_t * rusb = RUSB2_REG(rhport);
   volatile uint16_t *ctr = ep_addr_to_pipectr(rhport, ep_addr);
   if (!ctr) return;
+
   dcd_int_disable(rhport);
   *ctr = RUSB2_PIPE_CTR_SQCLR_Msk;
 
@@ -882,8 +934,8 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
     *ctr = RUSB2_PIPE_CTR_PID_BUF;
   } else {
     const unsigned num = _dcd.ep[0][tu_edpt_number(ep_addr)];
-    RUSB2->PIPESEL = num;
-    if (RUSB2->PIPECFG_b.TYPE != 1) {
+    rusb->PIPESEL = num;
+    if (rusb->PIPECFG_b.TYPE != 1) {
       *ctr = RUSB2_PIPE_CTR_PID_BUF;
     }
   }
@@ -953,9 +1005,9 @@ void dcd_int_handler(uint8_t rhport)
     }
   }
 
-  if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) {
-    rusb->NRDYSTS = 0;
-  }
+//  if ( is0 & RUSB2_INTSTS0_NRDY_Msk ) {
+//    rusb->NRDYSTS = 0;
+//  }
 
   // Control transfer stage changes
   if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) {
@@ -970,7 +1022,7 @@ void dcd_int_handler(uint8_t rhport)
 
   // Buffer empty
   if ( is0 & RUSB2_INTSTS0_BEMP_Msk ) {
-    const unsigned s = rusb->BEMPSTS;
+    const uint16_t s = rusb->BEMPSTS;
     rusb->BEMPSTS = 0;
     if ( s & 1 ) {
       process_pipe0_bemp(rhport);
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
index d7f4e0b42..21b2527c3 100644
--- a/src/portable/renesas/rusb2/rusb2_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -37,6 +37,8 @@ extern "C" {
 
 #define RUSB2_REG_BASE (0x000A0000)
 
+#define RUSB2_REG(_p)      ((rusb2_reg_t *) RUSB2_REG_BASE)
+
 // Start/Stop MSTP TODO implement later
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
   (void) rhport;
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index b704626f6..7a5e37089 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -33,6 +33,13 @@
 extern "C" {
 #endif
 
+// CCRX specific attribute to generate a Code that Accesses Variables in the Declared Size
+#ifdef __CCRX__
+  #define _ccrx_evenaccess __evenaccess
+#else
+  #define _ccrx_evenaccess
+#endif
+
 /*--------------------------------------------------------------------*/
 /* Register Definitions                                           */
 /*--------------------------------------------------------------------*/
@@ -64,7 +71,7 @@ typedef struct {
 
 
 /* RUSB2 Registers Structure */
-typedef struct {
+typedef struct _ccrx_evenaccess {
   union {
     volatile uint16_t SYSCFG; /* (@ 0x00000000) System Configuration Control Register */
 

From c53acb145589e2733b7d1abe012e85ae590bffb7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 6 Jul 2023 20:10:58 +0700
Subject: [PATCH 1884/2085] fix build with rx

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 37 +++++++++++++++-----------
 src/portable/renesas/rusb2/rusb2_ra.h  |  4 +--
 src/portable/renesas/rusb2/rusb2_rx.h  |  5 +++-
 3 files changed, 27 insertions(+), 19 deletions(-)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 833737181..81b60b3bc 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -36,12 +36,6 @@
 #include "device/dcd.h"
 #include "rusb2_type.h"
 
-#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
-// fallback
-#define CFG_TUSB_RHPORT0_MODE   OPT_MODE_DEVICE
-#define CFG_TUSB_RHPORT1_MODE   0
-#endif
-
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
@@ -86,7 +80,7 @@ typedef union TU_ATTR_PACKED {
     volatile uint8_t reserved8;
   };
   volatile uint16_t u16;
-} hw_fifo_t;
+} hw_fifo16_t;
 
 typedef union TU_ATTR_PACKED {
   struct {
@@ -140,9 +134,11 @@ static dcd_data_t _dcd;
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline bool is_highspeed(uint8_t rhport) {
-  return rhport == 1;
-}
+#ifdef RUSB2_SUPPORT_HIGHSPEED
+  #define is_highspeed_usbip(_p) (_p == 1)
+#else
+  #define is_highspeed_usbip(_p) (false)
+#endif
 
 static unsigned find_pipe(unsigned xfer)
 {
@@ -229,14 +225,17 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
   volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo;
 #else
-  volatile hw_fifo_t *reg = (volatile hw_fifo_t*) fifo;
+  volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo;
 #endif
+
   uintptr_t addr = (uintptr_t)buf;
+
   while (len >= 2) {
     reg->u16 = *(const uint16_t *)addr;
     addr += 2;
     len  -= 2;
   }
+
   if (len > 0) {
     reg->u8 = *(const uint8_t *)addr;
     ++addr;
@@ -260,11 +259,14 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne
     /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet},
     /* IN  */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet},
   };
+
   tu_fifo_buffer_info_t info;
   ops[dir].tu_fifo_get_info(f, &info);
+
   unsigned total_len = len;
   len = TU_MIN(total_len, info.len_lin);
   ops[dir].pipe_read_write(info.ptr_lin, fifo, len);
+
   unsigned rem = total_len - len;
   if (rem) {
     len = TU_MIN(rem, info.len_wrap);
@@ -689,7 +691,8 @@ void dcd_init(uint8_t rhport)
 
   rusb2_module_start(rhport, true);
 
-  if ( is_highspeed(rhport) ) {
+#ifdef RUSB2_SUPPORT_HIGHSPEED
+  if ( is_highspeed_usbip(rhport) ) {
     rusb->SYSCFG_b.HSE = 1;
 
     // leave CLKSEL as default (0x11) 24Mhz
@@ -715,7 +718,9 @@ void dcd_init(uint8_t rhport)
     rusb->CFIFOSEL_b.MBW = 1;
     rusb->D0FIFOSEL_b.MBW = 1;
     rusb->D1FIFOSEL_b.MBW = 1;
-  } else {
+  } else
+#endif
+  {
     rusb->SYSCFG_b.SCKE = 1;
     while (!rusb->SYSCFG_b.SCKE) {}
     rusb->SYSCFG_b.DRPD = 0;
@@ -772,7 +777,7 @@ void dcd_connect(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
 
-  if ( is_highspeed(rhport)) {
+  if ( is_highspeed_usbip(rhport)) {
     rusb->SYSCFG_b.CNEN = 1;
   }
   rusb->SYSCFG_b.DPRPU = 1;
@@ -809,7 +814,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   if (xfer == TUSB_XFER_ISOCHRONOUS) {
     // Fullspeed ISO is limit to 256 bytes
-    if ( !is_highspeed(rhport) && mps > 256) {
+    if ( !is_highspeed_usbip(rhport) && mps > 256) {
       return false;
     }
   }
@@ -823,7 +828,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   /* setup pipe */
   dcd_int_disable(rhport);
 
-  if ( is_highspeed(rhport) ) {
+  if ( is_highspeed_usbip(rhport) ) {
     // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed
     // depending on the allocation scheme
     rusb->PIPEBUF = 0x7C08;
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 0dc59331a..e04a99685 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -62,7 +62,7 @@ typedef struct {
 }rusb2_controller_t;
 
 #if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
-  #define RUSB2_HAS_HIGHSPEED
+  #define RUSB2_SUPPORT_HIGHSPEED
   #define RUSB2_CONTROLLER_COUNT 2
 #else
   #define RUSB2_CONTROLLER_COUNT 1
@@ -71,7 +71,7 @@ typedef struct {
 // USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
 static rusb2_controller_t rusb2_controller[] = {
     { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
-    #ifdef RUSB2_HAS_HIGHSPEED
+    #ifdef RUSB2_SUPPORT_HIGHSPEED
     { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
     #endif
 };
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
index 21b2527c3..17b9a918c 100644
--- a/src/portable/renesas/rusb2/rusb2_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -37,7 +37,10 @@ extern "C" {
 
 #define RUSB2_REG_BASE (0x000A0000)
 
-#define RUSB2_REG(_p)      ((rusb2_reg_t *) RUSB2_REG_BASE)
+TU_ATTR_ALWAYS_INLINE static inline rusb2_reg_t* RUSB2_REG(uint8_t rhport) {
+  (void) rhport;
+  return (rusb2_reg_t *) RUSB2_REG_BASE;
+}
 
 // Start/Stop MSTP TODO implement later
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {

From 4bbacb10089856fd6cd6e4c54da8ab2dc8575c60 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 7 Jul 2023 11:07:57 +0700
Subject: [PATCH 1885/2085] correct setting trace clock

---
 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h |  8 --------
 hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug      |  3 +--
 hw/bsp/ra/family.c                                | 11 ++++++-----
 hw/bsp/ra/family.cmake                            |  4 ----
 4 files changed, 7 insertions(+), 19 deletions(-)

diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
index 9bb496dd6..0eb5e0516 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
@@ -8,14 +8,7 @@
 #define BSP_CFG_HOCO_FREQUENCY  (2)                                /* HOCO 20MHz */
 #define BSP_CFG_PLL_SOURCE      (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
 #define BSP_CFG_PLL_DIV         (BSP_CLOCKS_PLL_DIV_3)             /* PLL Div /3 */
-
-#ifdef TRACE_ETM
-// Due to ozone fixed trace clock div = 1, PLL is limited around 100Mhz. This use 128 Mhz
-#define BSP_CFG_PLL_MUL         (BSP_CLOCKS_PLL_MUL(16U,0U))       /* PLL Mul x16.0 */
-#else
 #define BSP_CFG_PLL_MUL         (BSP_CLOCKS_PLL_MUL(25U,0U))       /* PLL Mul x25.0 */
-#endif
-
 #define BSP_CFG_PLL2_SOURCE     (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
 #define BSP_CFG_PLL2_DIV        (BSP_CLOCKS_PLL_DIV_2)             /* PLL2 Div /2 */
 #define BSP_CFG_PLL2_MUL        (BSP_CLOCKS_PLL_MUL(20U,0U))       /* PLL2 Mul x20.0 */
@@ -41,5 +34,4 @@
 #define BSP_CFG_CANFDCLK_DIV    (BSP_CLOCKS_CANFD_CLOCK_DIV_1)     /* CANFDCLK Div /1 */
 #define BSP_CFG_CECCLK_DIV      (BSP_CLOCKS_CEC_CLOCK_DIV_1)       /* CECCLK Div /1 */
 
-
 #endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
index 8a1262138..aebb29162 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
+++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
@@ -29,9 +29,8 @@ void OnProjectLoad (void) {
 **********************************************************************
 */
 void BeforeTargetConnect (void) {
-  //
   // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
-  //
+	Project.SetJLinkScript("../../../debug.jlinkscript");
 }
 
 /*********************************************************************
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 2c21a9967..b78fdedc7 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -49,8 +49,6 @@
 
 /* Key code for writing PRCR register. */
 #define BSP_PRV_PRCR_KEY         (0xA500U)
-#define BSP_PRV_PRCR_PRC1_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x2U)
-#define BSP_PRV_PRCR_LOCK         ((BSP_PRV_PRCR_KEY) | 0x0U)
 
 static const ioport_cfg_t family_pin_cfg = {
     .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
@@ -98,10 +96,13 @@ void board_init(void) {
   R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
 
 #ifdef TRACE_ETM
-  // Enable trace clock (max 100Mhz) = PLL / div
-  // Somehow ozone/jtrace always fixed trace div to 1 therefore for ETM tracing working reliably
-  // PLL is limited around 100Mhz
+  // TRCKCR is protected by PRCR bit0 register
+  R_SYSTEM->PRCR = (uint16_t) (BSP_PRV_PRCR_KEY | 0x01);
+
+  // Enable trace clock (max 100Mhz). Since PLL/CPU is 200Mhz, clock div = 2
   R_SYSTEM->TRCKCR = R_SYSTEM_TRCKCR_TRCKEN_Msk | 0x01;
+
+  R_SYSTEM->PRCR = (uint16_t) BSP_PRV_PRCR_KEY;
 #endif
 
 #if CFG_TUSB_OS == OPT_OS_FREERTOS
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index 74329165f..eb2d4958f 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -37,10 +37,6 @@ function(add_board_target BOARD_TARGET)
       ${FSP_RA}/src/bsp/mcu/all/bsp_security.c
       ${FSP_RA}/src/r_ioport/r_ioport.c
       )
-    # ETM Trace option
-    if (TRACE_ETM STREQUAL "1")
-      target_compile_definitions(${BOARD_TARGET} PUBLIC TRACE_ETM)
-    endif ()
 
     target_compile_options(${BOARD_TARGET} PUBLIC
       -ffreestanding

From 4c156100fafa682407f1a9a459d8b8800a029446 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 7 Jul 2023 12:27:18 +0700
Subject: [PATCH 1886/2085] use unaligned access read for hw fifo

---
 src/common/tusb_common.h               | 18 ++++--
 src/common/tusb_mcu.h                  | 12 +++-
 src/portable/renesas/rusb2/dcd_rusb2.c | 79 ++++++++++++++++----------
 3 files changed, 72 insertions(+), 37 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 957491aa9..576cb123f 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -260,11 +260,21 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_
 #else
 
 // MCU that could access unaligned memory natively
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32  (const void* mem) { return *((uint32_t const *) mem); }
-TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16  (const void* mem) { return *((uint16_t const *) mem); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void *mem) {
+  return *((uint32_t const *) mem);
+}
 
-TU_ATTR_ALWAYS_INLINE static inline void     tu_unaligned_write32 (void* mem, uint32_t value ) { *((uint32_t*) mem) = value; }
-TU_ATTR_ALWAYS_INLINE static inline void     tu_unaligned_write16 (void* mem, uint16_t value ) { *((uint16_t*) mem) = value; }
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void *mem) {
+  return *((uint16_t const *) mem);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void *mem, uint32_t value) {
+  *((uint32_t *) mem) = value;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_t value) {
+  *((uint16_t *) mem) = value;
+}
 
 #endif
 
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 496ebfc85..89f89182e 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -34,10 +34,16 @@
 
 //------------- Unaligned Memory Access -------------//
 
-// ARMv7+ (M3-M7, M23-M33) can access unaligned memory
-#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
-  #define TUP_ARCH_STRICT_ALIGN   0
+#ifdef __ARM_ARCH
+  // ARM Architecture set __ARM_FEATURE_UNALIGNED to 1 for mcu supports unaligned access
+  #if defined(__ARM_FEATURE_UNALIGNED) && __ARM_FEATURE_UNALIGNED == 1
+    #define TUP_ARCH_STRICT_ALIGN   0
+  #else
+    #define TUP_ARCH_STRICT_ALIGN   1
+  #endif
 #else
+  // TODO default to strict align for others
+  // Should investigate other architecture such as risv, xtensa, mips for optimal setting
   #define TUP_ARCH_STRICT_ALIGN   1
 #endif
 
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 81b60b3bc..464929224 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -220,6 +220,11 @@ static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num)
   while ( !rusb->D0FIFOCTR_b.FRDY ) {}
 }
 
+//--------------------------------------------------------------------+
+// Pipe FIFO
+//--------------------------------------------------------------------+
+
+// Write data buffer --> hw fifo
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 {
 #if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
@@ -228,54 +233,68 @@ static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
   volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo;
 #endif
 
-  uintptr_t addr = (uintptr_t)buf;
+  uint8_t const* buf8 = (uint8_t const*) buf;
 
   while (len >= 2) {
-    reg->u16 = *(const uint16_t *)addr;
-    addr += 2;
+    reg->u16 = tu_unaligned_read16(buf8);
+    buf8 += 2;
     len  -= 2;
   }
 
   if (len > 0) {
-    reg->u8 = *(const uint8_t *)addr;
-    ++addr;
+    reg->u8 = *buf8;
+    ++buf8;
   }
 }
 
+// Read data buffer <-- hw fifo
 static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
 {
-  uint8_t *p   = (uint8_t*)buf;
+  uint8_t *p = (uint8_t*)buf;
   volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
   while (len--) *p++ = *reg;
 }
 
-static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir)
-{
-  static const struct {
-    void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
-    void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n);
-    void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len);
-  } ops[] = {
-    /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet},
-    /* IN  */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet},
-  };
-
+// Write data sw fifo --> hw fifo
+static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
   tu_fifo_buffer_info_t info;
-  ops[dir].tu_fifo_get_info(f, &info);
+  tu_fifo_get_read_info(f, &info);
 
-  unsigned total_len = len;
-  len = TU_MIN(total_len, info.len_lin);
-  ops[dir].pipe_read_write(info.ptr_lin, fifo, len);
+  uint16_t count = tu_min16(total_len, info.len_lin);
+  pipe_write_packet(info.ptr_lin, fifo, count);
 
-  unsigned rem = total_len - len;
+  uint16_t rem = total_len - count;
   if (rem) {
-    len = TU_MIN(rem, info.len_wrap);
-    ops[dir].pipe_read_write(info.ptr_wrap, fifo, len);
-    rem -= len;
+    rem = tu_min16(rem, info.len_wrap);
+    pipe_write_packet(info.ptr_wrap, fifo, rem);
+    count += rem;
   }
-  ops[dir].tu_fifo_advance(f, total_len - rem);
+
+  tu_fifo_advance_read_pointer(f, count);
 }
 
+// Read data sw fifo <-- hw fifo
+static void pipe_read_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
+  tu_fifo_buffer_info_t info;
+  tu_fifo_get_write_info(f, &info);
+
+  uint16_t count = tu_min16(total_len, info.len_lin);
+  pipe_read_packet(info.ptr_lin, fifo, count);
+
+  uint16_t rem = total_len - count;
+  if (rem) {
+    rem = tu_min16(rem, info.len_wrap);
+    pipe_read_packet(info.ptr_wrap, fifo, rem);
+    count += rem;
+  }
+
+  tu_fifo_advance_write_pointer(f, count);
+}
+
+//--------------------------------------------------------------------+
+// Pipe Transfer
+//--------------------------------------------------------------------+
+
 static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_dcd.pipe[0];
@@ -292,7 +311,7 @@ static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_IN);
+      pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
     } else {
       pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
@@ -319,7 +338,7 @@ static bool pipe0_xfer_out(rusb2_reg_t* rusb)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len, TUSB_DIR_OUT);
+      pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
     } else {
       pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
@@ -357,7 +376,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_IN);
+      pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
     } else {
       pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
@@ -391,7 +410,7 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len, TUSB_DIR_OUT);
+      pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
     } else {
       pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;

From e0f1ba8b0e9cf46fabcddc72a61d5515df424edf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 7 Jul 2023 16:07:11 +0700
Subject: [PATCH 1887/2085] fully work with multiple ports without
 CFG_TUSB_RHPORT0/1

---
 hw/bsp/family_support.cmake             |  4 +-
 hw/bsp/ra/boards/ra6m5_ek/board.cmake   |  7 --
 src/portable/renesas/rusb2/dcd_rusb2.c  | 85 +++++++++++--------------
 src/portable/renesas/rusb2/rusb2_type.h |  1 +
 4 files changed, 39 insertions(+), 58 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 5b97eb5e4..d8298c8ad 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -227,8 +227,8 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS)
 
   if (DEFINED LOG)
     target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG})
-    if (LOG STREQUAL "3")
-      # no inline for debug level 3
+    if (LOG STREQUAL "4")
+      # no inline for debug level 4
       target_compile_definitions(${TARGET}-tinyusb_config INTERFACE TU_ATTR_ALWAYS_INLINE=)
     endif ()
   endif()
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
index d934a0c0d..5a615f9b0 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
@@ -14,11 +14,4 @@ function(update_board TARGET)
     # port 0 is fullspeed, port 1 is highspeed
     BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
     )
-
-  if (PORT STREQUAL 1)
-    target_compile_definitions(${TARGET} PUBLIC
-      CFG_TUSB_RHPORT1_MODE=OPT_MODE_DEVICE|OPT_MODE_HIGH_SPEED
-      CFG_TUSB_RHPORT0_MODE=0
-      )
-  endif ()
 endfunction()
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 464929224..3d3e52bfa 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -74,26 +74,6 @@ typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
   uint16_t TRN;
 } reg_pipetre_t;
 
-typedef union TU_ATTR_PACKED {
-  struct {
-    volatile uint8_t u8;
-    volatile uint8_t reserved8;
-  };
-  volatile uint16_t u16;
-} hw_fifo16_t;
-
-typedef union TU_ATTR_PACKED {
-  struct {
-    volatile uint8_t reserved8[3];
-    volatile uint8_t u8;
-  };
-  struct {
-    volatile uint16_t reserved16;
-    volatile uint16_t u16;
-  };
-  volatile uint32_t u32;
-} hw_fifo32_t;
-
 typedef struct TU_ATTR_PACKED
 {
   void      *buf;      /* the start address of a transfer data buffer */
@@ -135,9 +115,11 @@ static dcd_data_t _dcd;
 //--------------------------------------------------------------------+
 
 #ifdef RUSB2_SUPPORT_HIGHSPEED
-  #define is_highspeed_usbip(_p) (_p == 1)
+  #define is_highspeed_usbip(_p)     (_p == 1)
+  #define is_highspeed_regbase(_reg) (_reg == RUSB2_REG(1))
 #else
-  #define is_highspeed_usbip(_p) (false)
+  #define is_highspeed_usbip(_p)     (false)
+  #define is_highspeed_regbase(_reg) (false)
 #endif
 
 static unsigned find_pipe(unsigned xfer)
@@ -225,48 +207,57 @@ static inline void pipe_wait_for_ready(rusb2_reg_t * rusb, unsigned num)
 //--------------------------------------------------------------------+
 
 // Write data buffer --> hw fifo
-static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
+static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
 {
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_DEVICE)
-  volatile hw_fifo32_t *reg = (volatile hw_fifo32_t*) fifo;
-#else
-  volatile hw_fifo16_t *reg = (volatile hw_fifo16_t*) fifo;
-#endif
+  (void) rusb;
+
+  volatile uint16_t *ff16;
+  volatile uint8_t *ff8;
+
+  // Highspeed FIFO is 32-bit
+  if ( is_highspeed_regbase(rusb) ) {
+    ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2);
+    ff8  = (volatile uint8_t *) ((uintptr_t) fifo+3);
+  }else {
+    ff16 = (volatile uint16_t*) fifo;
+    ff8  = ((volatile uint8_t*) fifo);
+  }
 
   uint8_t const* buf8 = (uint8_t const*) buf;
 
   while (len >= 2) {
-    reg->u16 = tu_unaligned_read16(buf8);
+    *ff16 = tu_unaligned_read16(buf8);
     buf8 += 2;
     len  -= 2;
   }
 
   if (len > 0) {
-    reg->u8 = *buf8;
+    *ff8 = *buf8;
     ++buf8;
   }
 }
 
 // Read data buffer <-- hw fifo
-static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
+static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
 {
+  (void) rusb;
   uint8_t *p = (uint8_t*)buf;
   volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
   while (len--) *p++ = *reg;
 }
 
 // Write data sw fifo --> hw fifo
-static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
+static void pipe_write_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
   tu_fifo_buffer_info_t info;
   tu_fifo_get_read_info(f, &info);
 
   uint16_t count = tu_min16(total_len, info.len_lin);
-  pipe_write_packet(info.ptr_lin, fifo, count);
+  pipe_write_packet(rusb, info.ptr_lin, fifo, count);
 
   uint16_t rem = total_len - count;
   if (rem) {
     rem = tu_min16(rem, info.len_wrap);
-    pipe_write_packet(info.ptr_wrap, fifo, rem);
+    pipe_write_packet(rusb, info.ptr_wrap, fifo, rem);
     count += rem;
   }
 
@@ -274,17 +265,17 @@ static void pipe_write_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t tot
 }
 
 // Read data sw fifo <-- hw fifo
-static void pipe_read_packet_ff(tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
+static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void *fifo, uint16_t total_len) {
   tu_fifo_buffer_info_t info;
   tu_fifo_get_write_info(f, &info);
 
   uint16_t count = tu_min16(total_len, info.len_lin);
-  pipe_read_packet(info.ptr_lin, fifo, count);
+  pipe_read_packet(rusb, info.ptr_lin, fifo, count);
 
   uint16_t rem = total_len - count;
   if (rem) {
     rem = tu_min16(rem, info.len_wrap);
-    pipe_read_packet(info.ptr_wrap, fifo, rem);
+    pipe_read_packet(rusb, info.ptr_wrap, fifo, rem);
     count += rem;
   }
 
@@ -311,9 +302,9 @@ static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 
   if (len) {
     if (pipe->ff) {
-      pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
+      pipe_write_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
     } else {
-      pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
+      pipe_write_packet(rusb, buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -338,9 +329,9 @@ static bool pipe0_xfer_out(rusb2_reg_t* rusb)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
+      pipe_read_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->CFIFO, len);
     } else {
-      pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
+      pipe_read_packet(rusb, buf, (volatile void*)&rusb->CFIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -376,9 +367,9 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
 
   if (len) {
     if (pipe->ff) {
-      pipe_write_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
+      pipe_write_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
     } else {
-      pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
+      pipe_write_packet(rusb, buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -410,9 +401,9 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
 
   if (len) {
     if (pipe->ff) {
-      pipe_read_packet_ff((tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
+      pipe_read_packet_ff(rusb, (tu_fifo_t*)buf, (volatile void*)&rusb->D0FIFO, len);
     } else {
-      pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
+      pipe_read_packet(rusb, buf, (volatile void*)&rusb->D0FIFO, len);
       pipe->buf = (uint8_t*)buf + len;
     }
   }
@@ -733,10 +724,6 @@ void dcd_init(uint8_t rhport)
     // rusb2->BUSWAIT |= 0x0F00U;
 
     rusb->PHYSET_b.REPSEL = 1;
-
-    rusb->CFIFOSEL_b.MBW = 1;
-    rusb->D0FIFOSEL_b.MBW = 1;
-    rusb->D1FIFOSEL_b.MBW = 1;
   } else
 #endif
   {
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 7a5e37089..28cec9999 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -1670,6 +1670,7 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_FIFOSEL_BIGEND            (1U << RUSB2_CFIFOSEL_BIGEND_Pos) /* FIFO Big Endian */
 #define RUSB2_FIFOSEL_MBW_8BIT          (0U << RUSB2_CFIFOSEL_MBW_Pos)    /* 8-bit width */
 #define RUSB2_FIFOSEL_MBW_16BIT         (1U << RUSB2_CFIFOSEL_MBW_Pos)    /* 16-bit width */
+#define RUSB2_FIFOSEL_MBW_32BIT         (2U << RUSB2_CFIFOSEL_MBW_Pos)    /* 32-bit width */
 
 #define RUSB2_INTSTS0_CTSQ_CTRL_RDATA   (1U << RUSB2_INTSTS0_CTSQ_Pos)
 

From 88478a9d052edc364561da39382faef72f937ecb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 7 Jul 2023 16:24:22 +0700
Subject: [PATCH 1888/2085] add PORT selection for makefile

---
 hw/bsp/ra/boards/ra6m5_ek/board.mk     |  3 +++
 hw/bsp/ra/family.cmake                 |  2 +-
 hw/bsp/ra/family.mk                    | 12 ++++++++++++
 src/portable/renesas/rusb2/dcd_rusb2.c |  4 ++++
 4 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk
index 567908b63..a5c933764 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.mk
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk
@@ -4,4 +4,7 @@ MCU_VARIANT = ra6m5
 # For flash-jlink target
 JLINK_DEVICE = R7FA6M5BH
 
+# Port 1 is highspeed
+PORT ?= 1
+
 flash: flash-jlink
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index eb2d4958f..f09e86a72 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-set(FAMILY_MCUS RA CACHE INTERNAL "")
+set(FAMILY_MCUS RAXXX CACHE INTERNAL "")
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index b6e1bb0ae..f5097460a 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -3,8 +3,12 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
 FSP_RA = hw/mcu/renesas/fsp/ra/fsp
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk
+PORT ?= 0
+
 CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_RAXXX \
+  -DBOARD_TUD_RHPORT=$(PORT) \
 	-Wno-error=undef \
 	-Wno-error=strict-prototypes \
 	-Wno-error=cast-align \
@@ -15,6 +19,14 @@ CFLAGS += \
 	-nostartfiles \
 	-ffreestanding
 
+ifeq ($(PORT), 1)
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+  $(info "Using PORT 1 HighSpeed")
+else
+  CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+  $(info "Using PORT 0 FullSpeed")
+endif
+
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 3d3e52bfa..17d22f696 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -216,6 +216,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo
 
   // Highspeed FIFO is 32-bit
   if ( is_highspeed_regbase(rusb) ) {
+    // TODO 32-bit access for better performance
     ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2);
     ff8  = (volatile uint8_t *) ((uintptr_t) fifo+3);
   }else {
@@ -241,6 +242,9 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo
 static void pipe_read_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo, unsigned len)
 {
   (void) rusb;
+
+  // TODO 16/32-bit access for better performance
+
   uint8_t *p = (uint8_t*)buf;
   volatile uint8_t *reg = (volatile uint8_t*)fifo;  /* byte access is always at base register address */
   while (len--) *p++ = *reg;

From f7e7ba92ca7850c3c098fc988bf187a8b12a322a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 7 Jul 2023 16:27:12 +0700
Subject: [PATCH 1889/2085] enable host example for ra

---
 .idea/cmake.xml                          | 1 +
 examples/host/bare_api/only.txt          | 1 +
 examples/host/cdc_msc_hid/only.txt       | 1 +
 examples/host/hid_controller/only.txt    | 1 +
 examples/host/msc_file_explorer/only.txt | 1 +
 5 files changed, 5 insertions(+)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 47ca8253e..864ff615b 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -46,6 +46,7 @@
       <configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index 45da6c3f2..f8aa2186f 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -9,3 +9,4 @@ mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
+mcu:RAXXX
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index 45da6c3f2..f8aa2186f 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -9,3 +9,4 @@ mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
+mcu:RAXXX
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index 45da6c3f2..f8aa2186f 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -9,3 +9,4 @@ mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
+mcu:RAXXX
diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt
index 45da6c3f2..f8aa2186f 100644
--- a/examples/host/msc_file_explorer/only.txt
+++ b/examples/host/msc_file_explorer/only.txt
@@ -9,3 +9,4 @@ mcu:MIMXRT11XX
 mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
+mcu:RAXXX

From 0f53e746ffa21b6186809b2b896ddc74d38e9058 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 7 Jul 2023 18:41:16 +0700
Subject: [PATCH 1890/2085] move check highspeed to rusb_ra

---
 src/portable/renesas/rusb2/dcd_rusb2.c  | 31 ++++---------------------
 src/portable/renesas/rusb2/rusb2_ra.h   | 15 ++++++++----
 src/portable/renesas/rusb2/rusb2_rx.h   |  9 +++++++
 src/portable/renesas/rusb2/rusb2_type.h | 14 +++++++++++
 4 files changed, 39 insertions(+), 30 deletions(-)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 17d22f696..358e5644b 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -61,19 +61,6 @@
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
-typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
-  union {
-    struct {
-      uint16_t      : 8;
-      uint16_t TRCLR: 1;
-      uint16_t TRENB: 1;
-      uint16_t      : 0;
-    };
-    uint16_t TRE;
-  };
-  uint16_t TRN;
-} reg_pipetre_t;
-
 typedef struct TU_ATTR_PACKED
 {
   void      *buf;      /* the start address of a transfer data buffer */
@@ -114,14 +101,6 @@ static dcd_data_t _dcd;
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-#ifdef RUSB2_SUPPORT_HIGHSPEED
-  #define is_highspeed_usbip(_p)     (_p == 1)
-  #define is_highspeed_regbase(_reg) (_reg == RUSB2_REG(1))
-#else
-  #define is_highspeed_usbip(_p)     (false)
-  #define is_highspeed_regbase(_reg) (false)
-#endif
-
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
@@ -215,7 +194,7 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo
   volatile uint8_t *ff8;
 
   // Highspeed FIFO is 32-bit
-  if ( is_highspeed_regbase(rusb) ) {
+  if ( rusb2_is_highspeed_reg(rusb) ) {
     // TODO 32-bit access for better performance
     ff16 = (volatile uint16_t*) ((uintptr_t) fifo+2);
     ff8  = (volatile uint8_t *) ((uintptr_t) fifo+3);
@@ -706,7 +685,7 @@ void dcd_init(uint8_t rhport)
   rusb2_module_start(rhport, true);
 
 #ifdef RUSB2_SUPPORT_HIGHSPEED
-  if ( is_highspeed_usbip(rhport) ) {
+  if ( rusb2_is_highspeed_rhport(rhport) ) {
     rusb->SYSCFG_b.HSE = 1;
 
     // leave CLKSEL as default (0x11) 24Mhz
@@ -787,7 +766,7 @@ void dcd_connect(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
 
-  if ( is_highspeed_usbip(rhport)) {
+  if ( rusb2_is_highspeed_rhport(rhport)) {
     rusb->SYSCFG_b.CNEN = 1;
   }
   rusb->SYSCFG_b.DPRPU = 1;
@@ -824,7 +803,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   if (xfer == TUSB_XFER_ISOCHRONOUS) {
     // Fullspeed ISO is limit to 256 bytes
-    if ( !is_highspeed_usbip(rhport) && mps > 256) {
+    if ( !rusb2_is_highspeed_rhport(rhport) && mps > 256) {
       return false;
     }
   }
@@ -838,7 +817,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   /* setup pipe */
   dcd_int_disable(rhport);
 
-  if ( is_highspeed_usbip(rhport) ) {
+  if ( rusb2_is_highspeed_rhport(rhport) ) {
     // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed
     // depending on the allocation scheme
     rusb->PIPEBUF = 0x7C08;
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index e04a99685..28b690512 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -47,15 +47,15 @@ extern "C" {
 #pragma GCC diagnostic pop
 #endif
 
-//--------------------------------------------------------------------+
-//
-//--------------------------------------------------------------------+
-
 // IAR does not have __builtin_ctz
 #if defined(__ICCARM__)
   #define __builtin_ctz(x)   __iar_builtin_CLZ(__iar_builtin_RBIT(x))
 #endif
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 typedef struct {
   uint32_t reg_base;
   int32_t irqnum;
@@ -78,6 +78,13 @@ static rusb2_controller_t rusb2_controller[] = {
 
 #define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
 
+#define rusb2_is_highspeed_rhport(_p)  (_p == 1)
+#define rusb2_is_highspeed_reg(_reg)   (_reg == RUSB2_REG(1))
+
+//--------------------------------------------------------------------+
+// RUSB2 API
+//--------------------------------------------------------------------+
+
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
   uint32_t const mask = 1U << (11+rhport);
   if (start) {
diff --git a/src/portable/renesas/rusb2/rusb2_rx.h b/src/portable/renesas/rusb2/rusb2_rx.h
index 17b9a918c..7bf4be47e 100644
--- a/src/portable/renesas/rusb2/rusb2_rx.h
+++ b/src/portable/renesas/rusb2/rusb2_rx.h
@@ -42,6 +42,15 @@ TU_ATTR_ALWAYS_INLINE static inline rusb2_reg_t* RUSB2_REG(uint8_t rhport) {
   return (rusb2_reg_t *) RUSB2_REG_BASE;
 }
 
+
+#define rusb2_is_highspeed_rhport(_p)  (false)
+#define rusb2_is_highspeed_reg(_reg)   (false)
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+
 // Start/Stop MSTP TODO implement later
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_module_start(uint8_t rhport, bool start) {
   (void) rhport;
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 28cec9999..aceeb3c3e 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -48,6 +48,20 @@ extern "C" {
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
+// TODO same as RUSB2_PIPE_TR_t
+typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
+  union {
+    struct {
+      uint16_t      : 8;
+      uint16_t TRCLR: 1;
+      uint16_t TRENB: 1;
+      uint16_t      : 0;
+    };
+    uint16_t TRE;
+  };
+  uint16_t TRN;
+} reg_pipetre_t;
+
 typedef struct {
   union {
     volatile uint16_t E; /* (@ 0x00000000) Pipe Transaction Counter Enable Register */

From 4b59cb9a2003aae67f607c441d1b9e8428ffe237 Mon Sep 17 00:00:00 2001
From: Szymon Janc <szymon.janc@codecoup.pl>
Date: Mon, 10 Jul 2023 12:12:26 +0200
Subject: [PATCH 1891/2085] Fix documentation symlinks

There were typos in symlinks target names resulting in following
warrning on checkout (at least in Mynewt newt tool):
* Warning: stat mynewt/repos/tinyusb/docs/contributing/code_of_conduct.rst: no such file or directory
* Warning: stat mynewt/repos/tinyusb/docs/info/contributors.rst: no such file or directory
---
 docs/contributing/code_of_conduct.rst | 2 +-
 docs/info/contributors.rst            | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/contributing/code_of_conduct.rst b/docs/contributing/code_of_conduct.rst
index 82627099f..b52bf14c5 120000
--- a/docs/contributing/code_of_conduct.rst
+++ b/docs/contributing/code_of_conduct.rst
@@ -1 +1 @@
-../../CODE_OF_CONDUCT.rst
+../../CODE_OF_CONDUCT.rst
\ No newline at end of file
diff --git a/docs/info/contributors.rst b/docs/info/contributors.rst
index 02608919f..b3748ccb5 120000
--- a/docs/info/contributors.rst
+++ b/docs/info/contributors.rst
@@ -1 +1 @@
-../../CONTRIBUTORS.rst
+../../CONTRIBUTORS.rst
\ No newline at end of file

From eb298e2b81762ab2ead484dd021179d09e0335c9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 14 Jul 2023 12:34:43 +0700
Subject: [PATCH 1892/2085] add clock_config.c for imxrt generated by
 mcuxpresso config

---
 .idea/runConfigurations/mcx947.xml            |    2 +-
 .idea/runConfigurations/rt1010.xml            |    4 +-
 .../boards/metro_m7_1011/board/clock_config.c |  340 ++++++
 .../boards/metro_m7_1011/board/clock_config.h |   97 ++
 .../boards/metro_m7_1011/metro_m7_1011.mex    |  692 ++++++++++++
 .../mimxrt1010_evk/board/clock_config.c       |  351 ++++++
 .../mimxrt1010_evk/board/clock_config.h       |   97 ++
 .../boards/mimxrt1010_evk/mimxrt1010_evk.mex  |  692 ++++++++++++
 .../mimxrt1015_evk/board/clock_config.c       |  357 ++++++
 .../mimxrt1015_evk/board/clock_config.h       |  100 ++
 .../boards/mimxrt1015_evk/mimxrt1015_evk.mex  |  576 ++++++++++
 .../imxrt/boards/mimxrt1020_evk/board.cmake   |    2 +-
 hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk   |    2 +-
 .../mimxrt1020_evk/board/clock_config.c       |  421 +++++++
 .../mimxrt1020_evk/board/clock_config.h       |  108 ++
 .../boards/mimxrt1020_evk/mimxrt1020_evk.mex  |  597 ++++++++++
 .../imxrt/boards/mimxrt1024_evk/board.cmake   |    2 +-
 hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk   |    2 +-
 .../mimxrt1024_evk/board/clock_config.c       |  421 +++++++
 .../mimxrt1024_evk/board/clock_config.h       |  108 ++
 .../boards/mimxrt1024_evk/mimxrt1024_evk.mex  |  503 +++++++++
 hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk  |    2 +
 .../mimxrt1050_evkb/board/clock_config.c      |  495 ++++++++
 .../mimxrt1050_evkb/board/clock_config.h      |  119 ++
 .../mimxrt1050_evkb/mimxrt1050_evkb.mex       | 1001 ++++++++++++++++
 .../mimxrt1060_evk/board/clock_config.c       |  509 +++++++++
 .../mimxrt1060_evk/board/clock_config.h       |  123 ++
 .../boards/mimxrt1060_evk/mimxrt1060_evk.mex  | 1001 ++++++++++++++++
 .../mimxrt1064_evk/board/clock_config.c       |  511 +++++++++
 .../mimxrt1064_evk/board/clock_config.h       |  123 ++
 .../boards/mimxrt1064_evk/mimxrt1064_evk.mex  | 1006 +++++++++++++++++
 .../boards/teensy_40/board/clock_config.c     |  509 +++++++++
 .../boards/teensy_40/board/clock_config.h     |  123 ++
 hw/bsp/imxrt/boards/teensy_40/teensy40.mex    | 1001 ++++++++++++++++
 .../boards/teensy_41/board/clock_config.c     |  509 +++++++++
 .../boards/teensy_41/board/clock_config.h     |  123 ++
 hw/bsp/imxrt/boards/teensy_41/teensy41.mex    | 1001 ++++++++++++++++
 .../debug.jlinkscript}                        |    0
 hw/bsp/imxrt/family.c                         |    9 +-
 hw/bsp/imxrt/family.cmake                     |    9 +-
 hw/bsp/mcx/debug.jlinkscript                  |    5 +
 41 files changed, 13638 insertions(+), 15 deletions(-)
 create mode 100644 hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c
 create mode 100644 hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h
 create mode 100644 hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
 create mode 100644 hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
 create mode 100644 hw/bsp/imxrt/boards/teensy_40/board/clock_config.c
 create mode 100644 hw/bsp/imxrt/boards/teensy_40/board/clock_config.h
 create mode 100644 hw/bsp/imxrt/boards/teensy_40/teensy40.mex
 create mode 100644 hw/bsp/imxrt/boards/teensy_41/board/clock_config.c
 create mode 100644 hw/bsp/imxrt/boards/teensy_41/board/clock_config.h
 create mode 100644 hw/bsp/imxrt/boards/teensy_41/teensy41.mex
 rename hw/bsp/{mcx/mcx.jlinkscript => imxrt/debug.jlinkscript} (100%)
 create mode 100644 hw/bsp/mcx/debug.jlinkscript

diff --git a/.idea/runConfigurations/mcx947.xml b/.idea/runConfigurations/mcx947.xml
index 038c87421..0e7e2befc 100644
--- a/.idea/runConfigurations/mcx947.xml
+++ b/.idea/runConfigurations/mcx947.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/mcx.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="metro m7" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml
index 6fabd8561..a39f1f684 100644
--- a/.idea/runConfigurations/rt1010.xml
+++ b/.idea/runConfigurations/rt1010.xml
@@ -1,6 +1,6 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
-    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/imxrt/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="metro m7" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
     <method v="2">
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c
new file mode 100644
index 000000000..1b28b668a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c
@@ -0,0 +1,340 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1011xxxxx
+package_id: MIMXRT1011DAE5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1010-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY_CLK.outFreq, value: 480 MHz}
+settings:
+- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5'}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
+- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM_ANALOG.PLL2.denom, value: '1'}
+- {id: CCM_ANALOG.PLL2.num, value: '0'}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+    CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
+#endif
+    /* Disable ADC_ACLK_EN clock gate. */
+    CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
+    /* Set ADC_ACLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
+    /* Set Pll3 SW clock source to use the USB1 PLL output. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Set safe value of the AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
+    /* Set periph clock2 clock source to use the PLL3_SW_CLK. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h
new file mode 100644
index 000000000..119fd94bd
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.h
@@ -0,0 +1,97 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK                40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT              500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY_CLK                 480000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex
new file mode 100644
index 000000000..606ec2cfc
--- /dev/null
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex
@@ -0,0 +1,692 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1011xxxxx</processor>
+      <package>MIMXRT1011DAE5A</package>
+      <board>MIMXRT1010-EVK</board>
+      <board_revision>A</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <external_user_signals>
+               <properties/>
+            </external_user_signals>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPSPI1" description="Peripheral LPSPI1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPSPI1" signal="SDI" pin_num="57" pin_signal="GPIO_AD_03"/>
+                  <pin peripheral="LPSPI1" signal="SDO" pin_num="56" pin_signal="GPIO_AD_04"/>
+                  <pin peripheral="LPSPI1" signal="SCK" pin_num="52" pin_signal="GPIO_AD_06"/>
+                  <pin peripheral="ARM" signal="TRACE, 0" pin_num="60" pin_signal="GPIO_AD_00"/>
+                  <pin peripheral="ARM" signal="TRACE, 1" pin_num="79" pin_signal="GPIO_13"/>
+                  <pin peripheral="ARM" signal="TRACE, 2" pin_num="80" pin_signal="GPIO_12"/>
+                  <pin peripheral="ARM" signal="TRACE, 3" pin_num="1" pin_signal="GPIO_11"/>
+                  <pin peripheral="ARM" signal="arm_trace_clk" pin_num="58" pin_signal="GPIO_AD_02"/>
+                  <pin peripheral="GPIO2" signal="gpio_io, 05" pin_num="70" pin_signal="GPIO_SD_05"/>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="11" pin_signal="GPIO_02"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/>
+                  <pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="65" pin_signal="GPIO_SD_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="66" pin_signal="GPIO_SD_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="68" pin_signal="GPIO_SD_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="67" pin_signal="GPIO_SD_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="64" pin_signal="GPIO_SD_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="69" pin_signal="GPIO_SD_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLEDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO1" signal="gpiomux_io, 11" pin_num="1" pin_signal="GPIO_11">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="drive_strength" value="R0_4"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitBUTTONPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO2" signal="gpio_io, 05" pin_num="70" pin_signal="GPIO_SD_05">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="gpio_interrupt" value="kGPIO_NoIntmode"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="drive_strength" value="R0_4"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitCOMBO_SENSORPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCOMBO_SENSORPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="11" pin_signal="GPIO_02">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="drive_strength" value="R0_4"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="12" pin_signal="GPIO_01">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="drive_strength" value="R0_4"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/>
+                  <setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <dependencies>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="LPUART Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="Unsupported version of the LPUART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">2.5.1</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="igpio not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Unsupported version of the igpio in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">2.0.1</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.lpspi" description="LPSPI Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.lpspi" description="Unsupported version of the LPSPI Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="greaterOrEqual">
+                  <data type="Version">2.0.3</data>
+               </feature>
+            </dependency>
+         </dependencies>
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="ClockOutput" resourceId="UART_CLK_ROOT" description="UART_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_tx" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_rx" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sck" description="Signal serial clock is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sin" description="Signal serial data input is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sout" description="Signal serial data output is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="ClockOutput" resourceId="LPSPI_CLK_ROOT" description="LPSPI_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <instances>
+                  <instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
+                     </config_set>
+                     <config_set name="interrupt_vector"/>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="true" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="true" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="true" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                        <setting name="enable_irq_comb_16_31" value="false"/>
+                        <struct name="gpio_interrupt_comb_16_31">
+                           <setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="1f9167f9-b5d4-4014-bb88-164f5cb5df38" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+                  <instance name="LPSPI1" uuid="de6f91ec-e184-4998-995c-9c22586a5529" type="lpspi" type_id="lpspi_6e21a1e0a09f0a012d683c4f91752db8" mode="polling" peripheral="LPSPI1" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="main">
+                        <setting name="mode" value="kLPSPI_Master"/>
+                        <setting name="clockSource" value="LpspiClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="master">
+                           <setting name="baudRate" value="400000"/>
+                           <setting name="bitsPerFrame" value="8"/>
+                           <setting name="cpol" value="kLPSPI_ClockPolarityActiveHigh"/>
+                           <setting name="cpha" value="kLPSPI_ClockPhaseFirstEdge"/>
+                           <setting name="direction" value="kLPSPI_MsbFirst"/>
+                           <setting name="pcsToSckDelayInNanoSec" value="1000"/>
+                           <setting name="lastSckToPcsDelayInNanoSec" value="1000"/>
+                           <setting name="betweenTransferDelayInNanoSec" value="1000"/>
+                           <setting name="whichPcs" value="kLPSPI_Pcs0"/>
+                           <setting name="pcsActiveHighOrLow" value="kLPSPI_PcsActiveLow"/>
+                           <setting name="pinCfg" value="kLPSPI_SdiInSdoOut"/>
+                           <setting name="dataOutConfig" value="kLpspiDataOutRetained"/>
+                        </struct>
+                        <setting name="set_FifoWaterMarks" value="false"/>
+                        <struct name="fifoWaterMarks">
+                           <setting name="txWatermark" value="0"/>
+                           <setting name="rxWatermark" value="0"/>
+                        </struct>
+                        <setting name="allPcsPolarityEnable" value="false"/>
+                        <struct name="allPcsPolarity">
+                           <setting name="kLPSPI_Pcs1Active" value="kLPSPI_PcsActiveLow"/>
+                           <setting name="kLPSPI_Pcs2Active" value="kLPSPI_PcsActiveLow"/>
+                           <setting name="kLPSPI_Pcs3Active" value="kLPSPI_PcsActiveLow"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="452cb7cf-ac6a-4f29-a940-5f049b272fb1" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="be6880f0-7c2d-4331-bd40-2163fb383fd7" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="0f82c647-4c11-4163-87a4-aca908bb012c" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="18436376-474a-425e-81c0-9aa48fcbccd6" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="5501650f-8266-4cab-aadb-7799f5079dfb" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c
new file mode 100644
index 000000000..6cd18c8c2
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c
@@ -0,0 +1,351 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1011xxxxx
+package_id: MIMXRT1011DAE5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1010-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include "fsl_iomuxc.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY_CLK.outFreq, value: 480 MHz}
+settings:
+- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5'}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
+- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM_ANALOG.PLL2.denom, value: '1'}
+- {id: CCM_ANALOG.PLL2.num, value: '0'}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
+    CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
+#endif
+    /* Disable ADC_ACLK_EN clock gate. */
+    CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
+    /* Set ADC_ACLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
+    /* Set Pll3 SW clock source to use the USB1 PLL output. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Set safe value of the AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
+    /* Set periph clock2 clock source to use the PLL3_SW_CLK. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h
new file mode 100644
index 000000000..119fd94bd
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.h
@@ -0,0 +1,97 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK                40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT              500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY_CLK                 480000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex b/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex
new file mode 100644
index 000000000..606ec2cfc
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex
@@ -0,0 +1,692 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1011xxxxx</processor>
+      <package>MIMXRT1011DAE5A</package>
+      <board>MIMXRT1010-EVK</board>
+      <board_revision>A</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <external_user_signals>
+               <properties/>
+            </external_user_signals>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPSPI1" description="Peripheral LPSPI1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPSPI1" signal="SDI" pin_num="57" pin_signal="GPIO_AD_03"/>
+                  <pin peripheral="LPSPI1" signal="SDO" pin_num="56" pin_signal="GPIO_AD_04"/>
+                  <pin peripheral="LPSPI1" signal="SCK" pin_num="52" pin_signal="GPIO_AD_06"/>
+                  <pin peripheral="ARM" signal="TRACE, 0" pin_num="60" pin_signal="GPIO_AD_00"/>
+                  <pin peripheral="ARM" signal="TRACE, 1" pin_num="79" pin_signal="GPIO_13"/>
+                  <pin peripheral="ARM" signal="TRACE, 2" pin_num="80" pin_signal="GPIO_12"/>
+                  <pin peripheral="ARM" signal="TRACE, 3" pin_num="1" pin_signal="GPIO_11"/>
+                  <pin peripheral="ARM" signal="arm_trace_clk" pin_num="58" pin_signal="GPIO_AD_02"/>
+                  <pin peripheral="GPIO2" signal="gpio_io, 05" pin_num="70" pin_signal="GPIO_SD_05"/>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="11" pin_signal="GPIO_02"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/>
+                  <pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="65" pin_signal="GPIO_SD_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="66" pin_signal="GPIO_SD_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="68" pin_signal="GPIO_SD_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="67" pin_signal="GPIO_SD_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="64" pin_signal="GPIO_SD_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="69" pin_signal="GPIO_SD_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLEDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO1" signal="gpiomux_io, 11" pin_num="1" pin_signal="GPIO_11">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="drive_strength" value="R0_4"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitBUTTONPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO2" signal="gpio_io, 05" pin_num="70" pin_signal="GPIO_SD_05">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="gpio_interrupt" value="kGPIO_NoIntmode"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="drive_strength" value="R0_4"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitCOMBO_SENSORPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCOMBO_SENSORPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="11" pin_signal="GPIO_02">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="drive_strength" value="R0_4"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="12" pin_signal="GPIO_01">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="drive_strength" value="R0_4"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/>
+                  <setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <dependencies>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="LPUART Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="Unsupported version of the LPUART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">2.5.1</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="igpio not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Unsupported version of the igpio in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">2.0.1</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.lpspi" description="LPSPI Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.drivers.lpspi" description="Unsupported version of the LPSPI Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="greaterOrEqual">
+                  <data type="Version">2.0.3</data>
+               </feature>
+            </dependency>
+         </dependencies>
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="ClockOutput" resourceId="UART_CLK_ROOT" description="UART_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_tx" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_rx" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="equal">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sck" description="Signal serial clock is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sin" description="Signal serial data input is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PeripheralUnifiedSignal" resourceId="LPSPI1.lpspi_sout" description="Signal serial data output is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="routed" evaluation="">
+                        <data type="Boolean">true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="ClockOutput" resourceId="LPSPI_CLK_ROOT" description="LPSPI_CLK_ROOT is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
+                     <feature name="frequency" evaluation="greaterThan">
+                        <data type="Frequency" unit="Hz">0</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <instances>
+                  <instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
+                     </config_set>
+                     <config_set name="interrupt_vector"/>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="true" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="true" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="true" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                        <setting name="enable_irq_comb_16_31" value="false"/>
+                        <struct name="gpio_interrupt_comb_16_31">
+                           <setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="1f9167f9-b5d4-4014-bb88-164f5cb5df38" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+                  <instance name="LPSPI1" uuid="de6f91ec-e184-4998-995c-9c22586a5529" type="lpspi" type_id="lpspi_6e21a1e0a09f0a012d683c4f91752db8" mode="polling" peripheral="LPSPI1" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="main">
+                        <setting name="mode" value="kLPSPI_Master"/>
+                        <setting name="clockSource" value="LpspiClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="master">
+                           <setting name="baudRate" value="400000"/>
+                           <setting name="bitsPerFrame" value="8"/>
+                           <setting name="cpol" value="kLPSPI_ClockPolarityActiveHigh"/>
+                           <setting name="cpha" value="kLPSPI_ClockPhaseFirstEdge"/>
+                           <setting name="direction" value="kLPSPI_MsbFirst"/>
+                           <setting name="pcsToSckDelayInNanoSec" value="1000"/>
+                           <setting name="lastSckToPcsDelayInNanoSec" value="1000"/>
+                           <setting name="betweenTransferDelayInNanoSec" value="1000"/>
+                           <setting name="whichPcs" value="kLPSPI_Pcs0"/>
+                           <setting name="pcsActiveHighOrLow" value="kLPSPI_PcsActiveLow"/>
+                           <setting name="pinCfg" value="kLPSPI_SdiInSdoOut"/>
+                           <setting name="dataOutConfig" value="kLpspiDataOutRetained"/>
+                        </struct>
+                        <setting name="set_FifoWaterMarks" value="false"/>
+                        <struct name="fifoWaterMarks">
+                           <setting name="txWatermark" value="0"/>
+                           <setting name="rxWatermark" value="0"/>
+                        </struct>
+                        <setting name="allPcsPolarityEnable" value="false"/>
+                        <struct name="allPcsPolarity">
+                           <setting name="kLPSPI_Pcs1Active" value="kLPSPI_PcsActiveLow"/>
+                           <setting name="kLPSPI_Pcs2Active" value="kLPSPI_PcsActiveLow"/>
+                           <setting name="kLPSPI_Pcs3Active" value="kLPSPI_PcsActiveLow"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="452cb7cf-ac6a-4f29-a940-5f049b272fb1" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="be6880f0-7c2d-4331-bd40-2163fb383fd7" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="0f82c647-4c11-4163-87a4-aca908bb012c" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="18436376-474a-425e-81c0-9aa48fcbccd6" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="5501650f-8266-4cab-aadb-7799f5079dfb" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
new file mode 100644
index 000000000..ae1aa7fb1
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c
@@ -0,0 +1,357 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1015xxxxx
+package_id: MIMXRT1015DAF5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1015-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2160/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
+- {id: CCM.CLKO2_SEL.sel, value: CCM.LPI2C_CLK_ROOT}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
+- {id: CCM.SEMC_PODF.scale, value: '2'}
+- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 2);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(6);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
new file mode 100644
index 000000000..2acdb16a7
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h
@@ -0,0 +1,100 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               500000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           196363636UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             117333333UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
new file mode 100644
index 000000000..431a59af7
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex
@@ -0,0 +1,576 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1015xxxxx</processor>
+      <package>MIMXRT1015DAF5A</package>
+      <board>MIMXRT1015-EVK</board>
+      <board_revision>B</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07"/>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="12" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="11" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="9" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="10" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="13" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="8" pin_signal="GPIO_SD_B1_11"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLEDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitLEDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO3" signal="gpio_io, 21" pin_num="21" pin_signal="GPIO_SD_B1_01">
+                     <pin_features>
+                        <pin_feature name="direction" value="OUTPUT"/>
+                        <pin_feature name="gpio_init_state" value="true"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitBUTTONPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitBUTTONPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="GPIO2" signal="gpio_io, 09" pin_num="1" pin_signal="GPIO_EMC_09">
+                     <pin_features>
+                        <pin_feature name="direction" value="INPUT"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_4"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitCOMBO_SENSORPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCOMBO_SENSORPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCOMBO_SENSORPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="53" pin_signal="GPIO_AD_B1_14">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="52" pin_signal="GPIO_AD_B1_15">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                        <pin_feature name="software_input_on" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="2160/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="352/3 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.CLKO2_SEL.sel" value="CCM.LPI2C_CLK_ROOT" locked="false"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="2" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>N/A</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="57fc488c-a9f7-4a03-8ab3-5d2a3fd16a50" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="DEBUG_UART" uuid="600d7aee-5a2d-4373-9763-ce007b981c15" type="lpuart" type_id="lpuart_bebe3e12b6ec22bbd14199038f2bf459" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="COMBO_SENSOR" uuid="96f9e552-25e5-434a-9454-5cf9e614733d" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_LED" uuid="5592aac0-ced9-4284-88a8-bbeb5083a92f" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO3" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO3_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                        <setting name="enable_irq_comb_16_31" value="false"/>
+                        <struct name="gpio_interrupt_comb_16_31">
+                           <setting name="IRQn" value="GPIO3_Combined_16_31_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="USER_BUTTON" uuid="e7774953-3606-41b8-8b72-6e09025369e0" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_gpio">
+                        <setting name="enable_irq_comb_0_15" value="false"/>
+                        <struct name="gpio_interrupt_comb_0_15">
+                           <setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                        <setting name="enable_irq_comb_16_31" value="false"/>
+                        <struct name="gpio_interrupt_comb_16_31">
+                           <setting name="IRQn" value="GPIO2_Combined_16_31_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="0329fbca-00e5-4ec4-9f79-3cb65a7b267a" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="59cf1b09-8396-4bf9-bed6-03d5457c292f" type_id="system_54b53072540eeeb8f8e9343e71f28176">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="7d589e9f-7522-408c-b7c8-42770920766f" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="e9da5e16-1f55-49be-87ec-af8cfd4a4105" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="9dc7a034-9408-4852-9990-a713693635ee" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="28ec81a8-d7ea-4363-9330-20b877c481f6" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="774dd0a0-63ed-4846-b9d7-dfd082d810e3" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="77cd333e-4adc-4c6e-8b18-bbe349d78182" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>N/A</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake
index 1696dc987..39c94147c 100644
--- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake
@@ -1,6 +1,6 @@
 set(MCU_VARIANT MIMXRT1021)
 
-set(JLINK_DEVICE MIMXRT1021DAG5A)
+set(JLINK_DEVICE MIMXRT1021xxx5A)
 set(PYOCD_TARGET mimxrt1020)
 set(NXPLINK_DEVICE MIMXRT1021xxxxx:EVK-MIMXRT1020)
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
index b15da1b67..e269c8ac5 100644
--- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk
@@ -2,7 +2,7 @@ CFLAGS += -DCPU_MIMXRT1021DAG5A
 MCU_VARIANT = MIMXRT1021
 
 # For flash-jlink target
-JLINK_DEVICE = MIMXRT1021DAG5A
+JLINK_DEVICE = MIMXRT1021xxx5A
 
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1020
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c
new file mode 100644
index 000000000..764042928
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c
@@ -0,0 +1,421 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1021xxxxx
+package_id: MIMXRT1021DAG5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1020-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
+- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput = false,                 /* Disable the PLL providing the ENET 125MHz reference clock */
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .enableClkOutput25M = false,              /* Disable the PLL providing the ENET 25MHz reference clock */
+        .loopDivider = 1,                         /* Set frequency of ethernet reference clock to 50 MHz */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
+#endif
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+    /* Backward compatibility for original bitfield name */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h
new file mode 100644
index 000000000..d678a4f66
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h
@@ -0,0 +1,108 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               500000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           0UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              62500000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            176000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            176000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex b/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex
new file mode 100644
index 000000000..4ddaaed77
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/mimxrt1020_evk.mex
@@ -0,0 +1,597 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1020-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="a558cc6e-82c2-41f9-9f55-0348efc7896f" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1021xxxxx</processor>
+      <package>MIMXRT1021DAG5A</package>
+      <board>MIMXRT1020-EVK</board>
+      <board_revision>A3</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <external_user_signals>
+               <properties/>
+            </external_user_signals>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="105" pin_signal="GPIO_AD_B0_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="142" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="141" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="140" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="139" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="138" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="136" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="137" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="133" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="132" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="131" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="143" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="130" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="129" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="2" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="1" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="7" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="127" pin_signal="GPIO_EMC_29"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="126" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="CS, 0" pin_num="3" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="8" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="4" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="semc_dqs" pin_num="128" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="125" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="9" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="117" pin_signal="GPIO_EMC_39"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="118" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="119" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="120" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="122" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="121" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="123" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="124" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="10" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="12" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="13" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="14" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="15" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="16" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="17" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="18" pin_signal="GPIO_EMC_00"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN1" description="Peripheral CAN1 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN1" signal="RX" pin_num="32" pin_signal="GPIO_SD_B1_01"/>
+                  <pin peripheral="CAN1" signal="TX" pin_num="33" pin_signal="GPIO_SD_B1_00"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="97" pin_signal="GPIO_AD_B0_11"/>
+                  <pin peripheral="GPIO1" signal="gpio_io, 22" pin_num="84" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="107" pin_signal="GPIO_AD_B0_04"/>
+                  <pin peripheral="ENET" signal="enet_tx_clk" pin_num="100" pin_signal="GPIO_AD_B0_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="95" pin_signal="GPIO_AD_B0_13"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="93" pin_signal="GPIO_AD_B0_15"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="94" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="96" pin_signal="GPIO_AD_B0_12"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="99" pin_signal="GPIO_AD_B0_09"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="98" pin_signal="GPIO_AD_B0_10"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="116" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="115" pin_signal="GPIO_EMC_41"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="45" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="46" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="43" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="42" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="48" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="47" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="GPIO3" signal="gpio_io, 19" pin_num="41" pin_signal="GPIO_SD_B0_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="24" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="23" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="21" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="22" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="25" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="19" pin_signal="GPIO_SD_B1_11"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL2_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.USDHC1_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM.USDHC2_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_ENABLE_CFG" value="Disabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG" value="Disabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/dcd.c" update_enabled="true"/>
+            <file path="board/dcd.h" update_enabled="true"/>
+         </generated_project_files>
+         <dcdx_profile>
+            <processor_version>13.0.2</processor_version>
+            <output_format>c_array</output_format>
+         </dcdx_profile>
+         <dcdx_configurations>
+            <dcdx_configuration name="Device_configuration">
+               <description></description>
+               <options/>
+               <command_groups/>
+            </dcdx_configuration>
+         </dcdx_configurations>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="6d394465-bc9b-47f2-9a1f-3ca61f76d27b" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="d0b30ebd-b05e-42b2-8e94-40b1625c2dba" type="flexcan" type_id="flexcan_10d80efac19b25dcd240244aae88dca0" mode="interrupts" peripheral="CAN1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="wakeupSrc" value="kFLEXCAN_WakeupSrcUnfiltered"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableTimerSync" value="true"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="27a94726-61ef-42ac-b517-d1eda3853dfe" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="e2a4cccd-cb23-4714-8c90-022fcf6146e8" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="bd191d83-2cb2-40ed-a718-47b39d772006" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="d097438f-179b-43e0-b37c-aee31212cebd" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="d84400f7-fd84-4466-908a-04abca190ef6" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="4f0123a9-0338-4076-b275-b49951642704" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="18150193-6d2b-469f-88e5-4908669bf3e5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="602159e8-d65b-45d3-b63b-cd33be549134" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="eb963b89-5367-4d86-8885-82b4b8cff735" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+      <common name="common" version="1.0" enabled="true" update_project_code="true">
+         <core name="core0" role="primary" project_name="Project"/>
+      </common>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
index 7011fec9b..45487d148 100644
--- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake
@@ -1,6 +1,6 @@
 set(MCU_VARIANT MIMXRT1024)
 
-set(JLINK_DEVICE MIMXRT1024DAG5A)
+set(JLINK_DEVICE MIMXRT1024xxx5A)
 set(PYOCD_TARGET mimxrt1024)
 set(NXPLINK_DEVICE MIMXRT1024xxxxx:MIMXRT1024-EVK)
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
index 92209992d..3c325cc93 100644
--- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk
@@ -5,7 +5,7 @@ MCU_VARIANT = MIMXRT1024
 CFLAGS += -Wno-error=array-bounds
 
 # For flash-jlink target
-JLINK_DEVICE = MIMXRT1024DAG5A
+JLINK_DEVICE = MIMXRT1024xxx5A
 
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1024
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c
new file mode 100644
index 000000000..ba0cadafa
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c
@@ -0,0 +1,421 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1024xxxxx
+package_id: MIMXRT1024DAG5A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1024-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
+- {id: CCM.IPG_PODF.scale, value: '4'}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
+- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
+- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
+    {
+        .enableClkOutput = false,                 /* Disable the PLL providing the ENET 125MHz reference clock */
+        .enableClkOutput500M = true,              /* Enable the PLL providing the ENET 500MHz reference clock */
+        .enableClkOutput25M = false,              /* Disable the PLL providing the ENET 25MHz reference clock */
+        .loopDivider = 1,                         /* Set frequency of ethernet reference clock to 50 MHz */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
+#endif
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Enet PLL. */
+    CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+    /* Backward compatibility for original bitfield name */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h
new file mode 100644
index 000000000..d678a4f66
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h
@@ -0,0 +1,108 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               500000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           0UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           132000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              62500000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            176000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            176000000UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex
new file mode 100644
index 000000000..2aa55a604
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/mimxrt1024_evk.mex
@@ -0,0 +1,503 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1024-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="a558cc6e-82c2-41f9-9f55-0348efc7896f" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1024xxxxx</processor>
+      <package>MIMXRT1024DAG5A</package>
+      <board>MIMXRT1024-EVK</board>
+      <board_revision>B1</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <power_domains>
+               <power_domain name="NVCC_GPIO" value="3.3"/>
+            </power_domains>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="105" pin_signal="GPIO_AD_B0_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="142" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="141" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="140" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="139" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="138" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="136" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="137" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="133" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="132" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="131" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="143" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="130" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="129" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="2" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="1" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="7" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="127" pin_signal="GPIO_EMC_29"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="126" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="CS, 0" pin_num="3" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="8" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="4" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="semc_dqs" pin_num="128" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="125" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="9" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="117" pin_signal="GPIO_EMC_39"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="118" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="119" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="120" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="122" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="121" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="123" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="124" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="10" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="12" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="13" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="14" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="15" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="16" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="17" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="18" pin_signal="GPIO_EMC_00"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN1" description="Peripheral CAN1 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN1" signal="RX" pin_num="32" pin_signal="GPIO_SD_B1_01"/>
+                  <pin peripheral="CAN1" signal="TX" pin_num="33" pin_signal="GPIO_SD_B1_00"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="97" pin_signal="GPIO_AD_B0_11"/>
+                  <pin peripheral="GPIO1" signal="gpio_io, 22" pin_num="84" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="107" pin_signal="GPIO_AD_B0_04"/>
+                  <pin peripheral="ENET" signal="enet_tx_clk" pin_num="100" pin_signal="GPIO_AD_B0_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="95" pin_signal="GPIO_AD_B0_13"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="93" pin_signal="GPIO_AD_B0_15"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="94" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="96" pin_signal="GPIO_AD_B0_12"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="99" pin_signal="GPIO_AD_B0_09"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="98" pin_signal="GPIO_AD_B0_10"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="116" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="115" pin_signal="GPIO_EMC_41"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="45" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="46" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="43" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="42" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="48" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="47" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="GPIO3" signal="gpio_io, 19" pin_num="41" pin_signal="GPIO_SD_B0_06"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="24" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="23" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="21" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="22" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="25" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="19" pin_signal="GPIO_SD_B1_11"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL2_PFD2_CLK" locked="false"/>
+                  <setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.USDHC1_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM.USDHC2_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_ENABLE_CFG" value="Disabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG" value="Disabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/dcd.c" update_enabled="true"/>
+            <file path="board/dcd.h" update_enabled="true"/>
+         </generated_project_files>
+         <dcdx_profile>
+            <processor_version>13.0.2</processor_version>
+            <output_format>c_array</output_format>
+         </dcdx_profile>
+         <dcdx_configurations>
+            <dcdx_configuration name="Device_configuration">
+               <description></description>
+               <options/>
+               <command_groups/>
+            </dcdx_configuration>
+         </dcdx_configurations>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="6d394465-bc9b-47f2-9a1f-3ca61f76d27b" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="NVIC" uuid="096e7e36-6917-481a-a4c5-06822cfc2da4" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="5dc935cc-5865-4d50-bac9-89ad440a12ee" type_id="system_54b53072540eeeb8f8e9343e71f28176">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="c2fe99b8-bf9b-437f-9446-a35000b06679" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="generic_uart" uuid="eca93ea1-cadf-4247-bfdc-08769ef8ed12" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="fdf82c69-a73f-4f32-9699-457260453bc6" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="af80d7a8-d163-4a6f-839d-0ce2b15abffd" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="dca6ee55-a78d-4884-99bd-4f821b552213" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="4c34638b-b184-4e9d-8a81-5f3a1287180a" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>N/A</processor_version>
+         </tee_profile>
+      </tee>
+      <common name="common" version="1.0" enabled="true" update_project_code="true">
+         <core name="core0" role="primary" project_name="Project"/>
+      </common>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
index 9fd229105..60aa1e28f 100644
--- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk
@@ -1,6 +1,8 @@
 CFLAGS += -DCPU_MIMXRT1052DVL6B
 MCU_VARIANT = MIMXRT1052
 
+JLINK_DEVICE = MIMXRT1052xxxxB
+
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1050
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c
new file mode 100644
index 000000000..9738c6350
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c
@@ -0,0 +1,495 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1052xxxxB
+package_id: MIMXRT1052DVL6B
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: IMXRT1050-EVKB
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '40'}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 40,                        /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .postDivider = 8,                         /* Divider after PLL */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
+#endif
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+               CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(40);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Init Usb2 PLL. */
+    CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+    /* Backward compatibility for original bitfield name */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+#else
+#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h
new file mode 100644
index 000000000..6b4264bf2
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h
@@ -0,0 +1,119 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           160000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex b/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex
new file mode 100644
index 000000000..c0a5b5660
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/mimxrt1050_evkb.mex
@@ -0,0 +1,1001 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="IMXRT1050-EVKB" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="789fd1d3-821c-40a6-b04d-44ccc5a5d158" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1052xxxxB</processor>
+      <package>MIMXRT1052DVL6B</package>
+      <board>IMXRT1050-EVKB</board>
+      <board_revision>A</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="CSX, 0" pin_num="C7" pin_signal="GPIO_EMC_41"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCSIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/>
+                  <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/>
+                  <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/>
+                  <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/>
+                  <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/>
+                  <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/>
+                  <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/>
+                  <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/>
+                  <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/>
+                  <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/>
+                  <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SCL"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SDA"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLCDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/>
+                  <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitHyperFlashPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitHyperFlashPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitHyperFlashPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitHyperFlashPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA3" pin_num="L5" pin_signal="GPIO_SD_B1_00"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA2" pin_num="M5" pin_signal="GPIO_SD_B1_01"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA1" pin_num="M3" pin_signal="GPIO_SD_B1_02"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_B_DATA0" pin_num="M4" pin_signal="GPIO_SD_B1_03"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_B_SCLK" pin_num="P2" pin_signal="GPIO_SD_B1_04"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="160 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="3" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM.PLL3_SW_CLK_SEL" locked="false"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.div" value="40" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/>
+                  <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="a7525270-2da6-4556-8d91-4ab9d0edc0e2" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="cb1fcaec-81fe-4d3e-a079-a7d2819d6075" type="flexcan" type_id="flexcan_10d80efac19b25dcd240244aae88dca0" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN2_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="wakeupSrc" value="kFLEXCAN_WakeupSrcUnfiltered"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableTimerSync" value="true"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI" uuid="da865a46-3511-4001-8bb0-5249c52b0e4d" type="csi" type_id="csi_b2cf1faba8074e676ac4be93ec552c5a" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_csi" quick_selection="QuickSelection1">
+                        <struct name="clockConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="masterClockSource" value="CsiClock"/>
+                           <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        </struct>
+                        <struct name="config">
+                           <setting name="format" value="RGB565"/>
+                           <setting name="i_width" value="320"/>
+                           <setting name="i_height" value="240"/>
+                           <setting name="dataBus" value="kCSI_DataBus8Bit"/>
+                           <setting name="workMode" value="kCSI_GatedClockMode"/>
+                           <setting name="useExtVsync" value="true"/>
+                           <set name="polarityFlags">
+                              <selected/>
+                           </set>
+                           <struct name="buffers_config">
+                              <setting name="bufferName" value="defaultBuffer"/>
+                              <setting name="bufCount" value="4"/>
+                              <setting name="bufferAlign" value="64"/>
+                           </struct>
+                        </struct>
+                        <struct name="interruptsCfg">
+                           <setting name="isInterruptEnabled" value="false"/>
+                           <set name="interruptSources">
+                              <selected/>
+                           </set>
+                           <struct name="interrupt">
+                              <setting name="IRQn" value="CSI_IRQn"/>
+                              <setting name="enable_interrrupt" value="enabled"/>
+                              <setting name="enable_priority" value="false"/>
+                              <setting name="priority" value="0"/>
+                              <setting name="enable_custom_name" value="false"/>
+                           </struct>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_LPI2C" uuid="47051ef3-2c25-4648-8f79-4ae87cd12674" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="64741c26-6183-46d0-8bfe-02a92aa90e05" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LCD" uuid="8bf370a5-e797-45e8-b8c4-629c84c62843" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="480"/>
+                           <setting name="panelHeightInt" value="272"/>
+                           <setting name="hsw" value="41"/>
+                           <setting name="hfp" value="4"/>
+                           <setting name="hbp" value="8"/>
+                           <setting name="vsw" value="10"/>
+                           <setting name="vfp" value="4"/>
+                           <setting name="vbp" value="2"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <setting name="clockSource" value="LcdIfClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="687e3f12-1330-4ff9-8138-6aaf372d3e22" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="17c5d0d5-726a-40f6-a434-b121e9798a55" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="4a40b9b1-b64b-41b7-8ba7-728cda5039cd" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="c8d21d99-3f5e-47f2-aba7-0588ad4c2132" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="dfa0bda9-5863-49b3-9482-3ee85a2b93f0" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="3358d4d0-14d8-4ca7-9c13-378a0dc7f9a2" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="65c68c04-c4f4-4fbc-8c15-452d53d79fe6" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="99f59d06-c3df-407a-856a-22072ef95a98" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+      <common name="common" version="1.0" enabled="true" update_project_code="true">
+         <core name="core0" role="primary" project_name="Project"/>
+      </common>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c
new file mode 100644
index 000000000..c55e0135a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c
@@ -0,0 +1,509 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 31,                        /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .postDivider = 8,                         /* Divider after PLL */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+    /* Disable Flexspi2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi2);
+    /* Set FLEXSPI2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+    /* Set Flexspi2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can3);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    CLOCK_DisableClock(kCLOCK_Can3S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+               CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Set Enet2 output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+    /* Enable Enet2 output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Init Usb2 PLL. */
+    CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    /* Set ENET2 Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex b/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex
new file mode 100644
index 000000000..39b3ed606
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/mimxrt1060_evk.mex
@@ -0,0 +1,1001 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1060-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="2174caba-38fe-48d5-8f89-42a23354d23b" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1062xxxxA</processor>
+      <package>MIMXRT1062DVL6A</package>
+      <board>MIMXRT1060-EVK</board>
+      <board_revision>A2</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/>
+                  <pin peripheral="SEMC" signal="semc_dqs" pin_num="B7" pin_signal="GPIO_EMC_39"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCSIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/>
+                  <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/>
+                  <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/>
+                  <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/>
+                  <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/>
+                  <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/>
+                  <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/>
+                  <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/>
+                  <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/>
+                  <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/>
+                  <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SCL"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SDA"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLCDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 02" pin_num="M11" pin_signal="GPIO_AD_B0_02"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/>
+                  <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/>
+                  <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="96c1cec6-3bd3-47a2-8301-f38e4b0dd25f" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="eb0900eb-d552-4097-9dcf-a07e592a887f" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN2_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI" uuid="f67d9a64-c26d-4421-9805-a062b24146f2" type="csi" type_id="csi_3739ec1355c7b915be929f3b7e35095b" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_csi" quick_selection="QuickSelection1">
+                        <struct name="clockConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="masterClockSource" value="CsiClock"/>
+                           <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        </struct>
+                        <struct name="config">
+                           <setting name="format" value="RGB565"/>
+                           <setting name="i_width" value="320"/>
+                           <setting name="i_height" value="240"/>
+                           <setting name="dataBus" value="kCSI_DataBus8Bit"/>
+                           <setting name="workMode" value="kCSI_GatedClockMode"/>
+                           <setting name="useExtVsync" value="true"/>
+                           <set name="polarityFlags">
+                              <selected/>
+                           </set>
+                           <struct name="buffers_config">
+                              <setting name="bufferName" value="defaultBuffer"/>
+                              <setting name="bufCount" value="4"/>
+                              <setting name="bufferAlign" value="64"/>
+                           </struct>
+                        </struct>
+                        <struct name="interruptsCfg">
+                           <setting name="isInterruptEnabled" value="false"/>
+                           <set name="interruptSources">
+                              <selected/>
+                           </set>
+                           <struct name="interrupt">
+                              <setting name="IRQn" value="CSI_IRQn"/>
+                              <setting name="enable_interrrupt" value="enabled"/>
+                              <setting name="enable_priority" value="false"/>
+                              <setting name="priority" value="0"/>
+                              <setting name="enable_custom_name" value="false"/>
+                           </struct>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_LPI2C" uuid="f2c6cd0a-751c-4424-9248-a4d98da47de7" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="01f250e2-83d7-4b7b-a98d-772d1c3bdb42" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LCD" uuid="90a0c31d-6042-4687-af0f-0892536bc1ba" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="480"/>
+                           <setting name="panelHeightInt" value="272"/>
+                           <setting name="hsw" value="41"/>
+                           <setting name="hfp" value="4"/>
+                           <setting name="hbp" value="8"/>
+                           <setting name="vsw" value="10"/>
+                           <setting name="vfp" value="4"/>
+                           <setting name="vbp" value="3"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <setting name="clockSource" value="LcdIfClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="b31fa225-2a52-486b-9c5c-33a184a2c716" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="aa3cc953-557b-4557-b7fe-6fedc31acf98" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="8b3f852e-ee1e-45e9-abff-0ff722f1d65d" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="539d282e-5136-4289-9058-9a46b221ca45" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="6e4c02c4-0524-4905-91b5-01d2e2502186" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="c6d8fd36-2bbd-44c6-a160-54e7e12d0807" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="7d3626d3-4536-4838-a35d-3b8cf5a2bd71" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="738ea8df-6176-4e52-b4c7-b88aa9c17d13" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
new file mode 100644
index 000000000..778ab02f2
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c
@@ -0,0 +1,511 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1064xxxxA
+package_id: MIMXRT1064DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1064-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD1_DIV.scale, value: '16', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 31,                        /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .postDivider = 8,                         /* Divider after PLL */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+    /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi2);
+    /* Set FLEXSPI2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+    /* Set Flexspi2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+#endif
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can3);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    CLOCK_DisableClock(kCLOCK_Can3S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+               CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Set Enet2 output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+    /* Enable Enet2 output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Init Usb2 PLL. */
+    CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    /* Set ENET2 Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
new file mode 100644
index 000000000..5e0fc72d3
--- /dev/null
+++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex
@@ -0,0 +1,1006 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1064-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="d75e55f6-68ab-46ef-814b-b94593af7f06" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1064xxxxA</processor>
+      <package>MIMXRT1064DVL6A</package>
+      <board>MIMXRT1064-EVK</board>
+      <board_revision>1</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>true</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/>
+                  <pin peripheral="SEMC" signal="semc_dqs" pin_num="B7" pin_signal="GPIO_EMC_39"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCSIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/>
+                  <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/>
+                  <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/>
+                  <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/>
+                  <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/>
+                  <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/>
+                  <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/>
+                  <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/>
+                  <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/>
+                  <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/>
+                  <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SCL"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SDA"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLCDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 02" pin_num="M11" pin_signal="GPIO_AD_B0_02"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/>
+                  <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_DIV.scale" value="16" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/>
+                  <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="1c6563a6-c68b-40e5-8828-2853c99f95fa" called_from_default_init="true" id_prefix="BOARD_" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="e311ffe2-a68e-4ccc-bab1-c97e2207c5f0" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN2_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_LPI2C" uuid="7b69310c-fa35-4379-ac89-358df9280646" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_RGB565" uuid="ae342c96-df71-41a3-8419-3cccf201c91e" type="csi" type_id="csi_20660d007fd9c28a0b6ec615663d2939" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_csi">
+                        <struct name="clockConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="masterClockSource" value="CsiClock"/>
+                           <setting name="masterClockSourceFreq" value="BOARD_BootClockRUN"/>
+                        </struct>
+                        <struct name="config">
+                           <setting name="format" value="RGB565"/>
+                           <setting name="i_width" value="320"/>
+                           <setting name="i_height" value="240"/>
+                           <setting name="dataBus" value="kCSI_DataBus8Bit"/>
+                           <setting name="workMode" value="kCSI_GatedClockMode"/>
+                           <setting name="useExtVsync" value="true"/>
+                           <set name="polarityFlags">
+                              <selected>
+                                 <id>kCSI_HsyncActiveHigh</id>
+                                 <id>kCSI_VsyncActiveLow</id>
+                              </selected>
+                           </set>
+                           <struct name="buffers_config">
+                              <setting name="bufferName" value="defaultBuffer"/>
+                              <setting name="bufCount" value="4"/>
+                              <setting name="bufferAlign" value="64"/>
+                           </struct>
+                        </struct>
+                        <struct name="interruptsCfg">
+                           <set name="interruptSources">
+                              <selected/>
+                           </set>
+                           <setting name="isInterruptEnabled" value="false"/>
+                           <struct name="interrupt">
+                              <setting name="IRQn" value="CSI_IRQn"/>
+                              <setting name="enable_interrrupt" value="enabled"/>
+                              <setting name="enable_priority" value="false"/>
+                              <setting name="priority" value="0"/>
+                              <setting name="enable_custom_name" value="false"/>
+                           </struct>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="81411659-def5-4dbf-839a-d5e5f32dec0b" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LCD_RGB565" uuid="8c491814-4517-44d9-95de-844144e0c6b5" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="480"/>
+                           <setting name="panelHeightInt" value="272"/>
+                           <setting name="hsw" value="41"/>
+                           <setting name="hfp" value="4"/>
+                           <setting name="hbp" value="8"/>
+                           <setting name="vsw" value="10"/>
+                           <setting name="vfp" value="4"/>
+                           <setting name="vbp" value="2"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <setting name="clockSource" value="LcdIfClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="352dfcca-72ab-4214-bb68-9c1a927c4922" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="fe5e46a0-17b8-41e8-9cbc-ffb6f1cf78c1" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="f79f6878-69b5-4063-9007-0b8e509f7274" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="7ce8b24b-29e6-4b69-86e5-bdfd641cef44" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="ef6a8ae2-3961-4a05-a37f-d42a6a4d8a56" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="00a2a52b-0c40-4dbf-a6d0-5257cfc384e0" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="f30f7e21-6805-4236-9ab3-ff06a6013fa1" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="ea574324-8cc3-4da3-bdfc-2bdba0dfc3df" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c
new file mode 100644
index 000000000..c55e0135a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.c
@@ -0,0 +1,509 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 31,                        /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .postDivider = 8,                         /* Divider after PLL */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+    /* Disable Flexspi2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi2);
+    /* Set FLEXSPI2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+    /* Set Flexspi2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can3);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    CLOCK_DisableClock(kCLOCK_Can3S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+               CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Set Enet2 output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+    /* Enable Enet2 output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Init Usb2 PLL. */
+    CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    /* Set ENET2 Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/teensy_40/teensy40.mex b/hw/bsp/imxrt/boards/teensy_40/teensy40.mex
new file mode 100644
index 000000000..39b3ed606
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_40/teensy40.mex
@@ -0,0 +1,1001 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1060-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="2174caba-38fe-48d5-8f89-42a23354d23b" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1062xxxxA</processor>
+      <package>MIMXRT1062DVL6A</package>
+      <board>MIMXRT1060-EVK</board>
+      <board_revision>A2</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/>
+                  <pin peripheral="SEMC" signal="semc_dqs" pin_num="B7" pin_signal="GPIO_EMC_39"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCSIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/>
+                  <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/>
+                  <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/>
+                  <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/>
+                  <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/>
+                  <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/>
+                  <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/>
+                  <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/>
+                  <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/>
+                  <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/>
+                  <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SCL"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SDA"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLCDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 02" pin_num="M11" pin_signal="GPIO_AD_B0_02"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/>
+                  <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/>
+                  <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="96c1cec6-3bd3-47a2-8301-f38e4b0dd25f" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="eb0900eb-d552-4097-9dcf-a07e592a887f" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN2_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI" uuid="f67d9a64-c26d-4421-9805-a062b24146f2" type="csi" type_id="csi_3739ec1355c7b915be929f3b7e35095b" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_csi" quick_selection="QuickSelection1">
+                        <struct name="clockConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="masterClockSource" value="CsiClock"/>
+                           <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        </struct>
+                        <struct name="config">
+                           <setting name="format" value="RGB565"/>
+                           <setting name="i_width" value="320"/>
+                           <setting name="i_height" value="240"/>
+                           <setting name="dataBus" value="kCSI_DataBus8Bit"/>
+                           <setting name="workMode" value="kCSI_GatedClockMode"/>
+                           <setting name="useExtVsync" value="true"/>
+                           <set name="polarityFlags">
+                              <selected/>
+                           </set>
+                           <struct name="buffers_config">
+                              <setting name="bufferName" value="defaultBuffer"/>
+                              <setting name="bufCount" value="4"/>
+                              <setting name="bufferAlign" value="64"/>
+                           </struct>
+                        </struct>
+                        <struct name="interruptsCfg">
+                           <setting name="isInterruptEnabled" value="false"/>
+                           <set name="interruptSources">
+                              <selected/>
+                           </set>
+                           <struct name="interrupt">
+                              <setting name="IRQn" value="CSI_IRQn"/>
+                              <setting name="enable_interrrupt" value="enabled"/>
+                              <setting name="enable_priority" value="false"/>
+                              <setting name="priority" value="0"/>
+                              <setting name="enable_custom_name" value="false"/>
+                           </struct>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_LPI2C" uuid="f2c6cd0a-751c-4424-9248-a4d98da47de7" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="01f250e2-83d7-4b7b-a98d-772d1c3bdb42" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LCD" uuid="90a0c31d-6042-4687-af0f-0892536bc1ba" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="480"/>
+                           <setting name="panelHeightInt" value="272"/>
+                           <setting name="hsw" value="41"/>
+                           <setting name="hfp" value="4"/>
+                           <setting name="hbp" value="8"/>
+                           <setting name="vsw" value="10"/>
+                           <setting name="vfp" value="4"/>
+                           <setting name="vbp" value="3"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <setting name="clockSource" value="LcdIfClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="b31fa225-2a52-486b-9c5c-33a184a2c716" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="aa3cc953-557b-4557-b7fe-6fedc31acf98" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="8b3f852e-ee1e-45e9-abff-0ff722f1d65d" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="539d282e-5136-4289-9058-9a46b221ca45" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="6e4c02c4-0524-4905-91b5-01d2e2502186" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="c6d8fd36-2bbd-44c6-a160-54e7e12d0807" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="7d3626d3-4536-4838-a35d-3b8cf5a2bd71" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="738ea8df-6176-4e52-b4c7-b88aa9c17d13" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c
new file mode 100644
index 000000000..c55e0135a
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.c
@@ -0,0 +1,509 @@
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
+ *
+ * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
+ *
+ * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
+ *
+ * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
+ *
+ * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
+ *
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v11.0
+processor: MIMXRT1062xxxxA
+package_id: MIMXRT1062DVL6A
+mcu_data: ksdk2_0
+processor_version: 13.0.2
+board: MIMXRT1060-EVK
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "clock_config.h"
+#include "fsl_iomuxc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
+- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
+- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
+- {id: CLK_1M.outFreq, value: 1 MHz}
+- {id: CLK_24M.outFreq, value: 24 MHz}
+- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
+- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
+- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
+- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
+- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
+- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
+- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
+- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
+- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
+- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
+- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
+- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
+- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
+- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
+settings:
+- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
+- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
+- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
+- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
+- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.SEMC_PODF.scale, value: '8'}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
+- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
+- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
+- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
+- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
+- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
+- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
+- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
+- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
+- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
+- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
+- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
+- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
+- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
+- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
+- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
+- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
+- {id: CCM_ANALOG.PLL4.denom, value: '50'}
+- {id: CCM_ANALOG.PLL4.div, value: '47'}
+- {id: CCM_ANALOG.PLL5.denom, value: '1'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
+- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
+- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
+- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
+- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
+sources:
+- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 100,                       /* PLL loop divider, Fout = Fin * 50 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 1,                         /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 0,                         /* PLL loop divider, Fout = Fin * 20 */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+    {
+        .loopDivider = 31,                        /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .postDivider = 8,                         /* Divider after PLL */
+        .numerator = 0,                           /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .denominator = 1,                         /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+        .src = 0,                                 /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+    /* Init RTC OSC clock frequency. */
+    CLOCK_SetRtcXtalFreq(32768U);
+    /* Enable 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
+    /* Use free 1MHz clock output. */
+    XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
+    /* Set XTAL 24MHz clock frequency. */
+    CLOCK_SetXtalFreq(24000000U);
+    /* Enable XTAL 24MHz clock source. */
+    CLOCK_InitExternalClk(0);
+    /* Enable internal RC. */
+    CLOCK_InitRcOsc24M();
+    /* Switch clock source to external OSC. */
+    CLOCK_SwitchOsc(kCLOCK_XtalOsc);
+    /* Set Oscillator ready counter value. */
+    CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
+    /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 1);     /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
+    /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
+    DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
+    /* Waiting for DCDC_STS_DC_OK bit is asserted */
+    while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
+    {
+    }
+    /* Set AHB_PODF. */
+    CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
+    /* Disable IPG clock gate. */
+    CLOCK_DisableClock(kCLOCK_Adc1);
+    CLOCK_DisableClock(kCLOCK_Adc2);
+    CLOCK_DisableClock(kCLOCK_Xbar1);
+    CLOCK_DisableClock(kCLOCK_Xbar2);
+    CLOCK_DisableClock(kCLOCK_Xbar3);
+    /* Set IPG_PODF. */
+    CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
+    /* Set ARM_PODF. */
+    CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
+    /* Set PERIPH_CLK2_PODF. */
+    CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
+    /* Disable PERCLK clock gate. */
+    CLOCK_DisableClock(kCLOCK_Gpt1);
+    CLOCK_DisableClock(kCLOCK_Gpt1S);
+    CLOCK_DisableClock(kCLOCK_Gpt2);
+    CLOCK_DisableClock(kCLOCK_Gpt2S);
+    CLOCK_DisableClock(kCLOCK_Pit);
+    /* Set PERCLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    /* Disable USDHC1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc1);
+    /* Set USDHC1_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
+    /* Set Usdhc1 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
+    /* Disable USDHC2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Usdhc2);
+    /* Set USDHC2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
+    /* Set Usdhc2 clock source. */
+    CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+    /* Disable Semc clock gate. */
+    CLOCK_DisableClock(kCLOCK_Semc);
+    /* Set SEMC_PODF. */
+    CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
+    /* Set Semc alt clock source. */
+    CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
+    /* Set Semc clock source. */
+    CLOCK_SetMux(kCLOCK_SemcMux, 0);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Disable Flexspi clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi);
+    /* Set FLEXSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
+    /* Set Flexspi clock source. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
+#endif
+    /* Disable Flexspi2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_FlexSpi2);
+    /* Set FLEXSPI2_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
+    /* Set Flexspi2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
+    /* Disable CSI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Csi);
+    /* Set CSI_PODF. */
+    CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
+    /* Set Csi clock source. */
+    CLOCK_SetMux(kCLOCK_CsiMux, 0);
+    /* Disable LPSPI clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpspi1);
+    CLOCK_DisableClock(kCLOCK_Lpspi2);
+    CLOCK_DisableClock(kCLOCK_Lpspi3);
+    CLOCK_DisableClock(kCLOCK_Lpspi4);
+    /* Set LPSPI_PODF. */
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    /* Set Lpspi clock source. */
+    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    /* Disable TRACE clock gate. */
+    CLOCK_DisableClock(kCLOCK_Trace);
+    /* Set TRACE_PODF. */
+    CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
+    /* Set Trace clock source. */
+    CLOCK_SetMux(kCLOCK_TraceMux, 0);
+    /* Disable SAI1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai1);
+    /* Set SAI1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
+    /* Set SAI1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
+    /* Set Sai1 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
+    /* Disable SAI2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai2);
+    /* Set SAI2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
+    /* Set SAI2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
+    /* Set Sai2 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
+    /* Disable SAI3 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Sai3);
+    /* Set SAI3_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
+    /* Set SAI3_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
+    /* Set Sai3 clock source. */
+    CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
+    /* Disable Lpi2c clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpi2c1);
+    CLOCK_DisableClock(kCLOCK_Lpi2c2);
+    CLOCK_DisableClock(kCLOCK_Lpi2c3);
+    /* Set LPI2C_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    /* Set Lpi2c clock source. */
+    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
+    /* Disable CAN clock gate. */
+    CLOCK_DisableClock(kCLOCK_Can1);
+    CLOCK_DisableClock(kCLOCK_Can2);
+    CLOCK_DisableClock(kCLOCK_Can3);
+    CLOCK_DisableClock(kCLOCK_Can1S);
+    CLOCK_DisableClock(kCLOCK_Can2S);
+    CLOCK_DisableClock(kCLOCK_Can3S);
+    /* Set CAN_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    /* Set Can clock source. */
+    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    /* Disable UART clock gate. */
+    CLOCK_DisableClock(kCLOCK_Lpuart1);
+    CLOCK_DisableClock(kCLOCK_Lpuart2);
+    CLOCK_DisableClock(kCLOCK_Lpuart3);
+    CLOCK_DisableClock(kCLOCK_Lpuart4);
+    CLOCK_DisableClock(kCLOCK_Lpuart5);
+    CLOCK_DisableClock(kCLOCK_Lpuart6);
+    CLOCK_DisableClock(kCLOCK_Lpuart7);
+    CLOCK_DisableClock(kCLOCK_Lpuart8);
+    /* Set UART_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_UartDiv, 0);
+    /* Set Uart clock source. */
+    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    /* Disable LCDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_LcdPixel);
+    /* Set LCDIF_PRED. */
+    CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
+    /* Set LCDIF_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
+    /* Set Lcdif pre clock source. */
+    CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
+    /* Disable SPDIF clock gate. */
+    CLOCK_DisableClock(kCLOCK_Spdif);
+    /* Set SPDIF0_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
+    /* Set SPDIF0_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
+    /* Set Spdif clock source. */
+    CLOCK_SetMux(kCLOCK_SpdifMux, 3);
+    /* Disable Flexio1 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio1);
+    /* Set FLEXIO1_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
+    /* Set FLEXIO1_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
+    /* Set Flexio1 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
+    /* Disable Flexio2 clock gate. */
+    CLOCK_DisableClock(kCLOCK_Flexio2);
+    /* Set FLEXIO2_CLK_PRED. */
+    CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
+    /* Set FLEXIO2_CLK_PODF. */
+    CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
+    /* Set Flexio2 clock source. */
+    CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
+    /* Set Pll3 sw clock source. */
+    CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
+    /* Init ARM PLL. */
+    CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
+    /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+     * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+#ifndef SKIP_SYSCLK_INIT
+#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+    #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+#endif
+    /* Init System PLL. */
+    CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
+    /* Init System pfd0. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
+    /* Init System pfd1. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
+    /* Init System pfd2. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
+    /* Init System pfd3. */
+    CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
+#endif
+    /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+     * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+     * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
+    /* Init Usb1 PLL. */
+    CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
+    /* Init Usb1 pfd0. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
+    /* Init Usb1 pfd1. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
+    /* Init Usb1 pfd2. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
+    /* Init Usb1 pfd3. */
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
+#endif
+    /* DeInit Audio PLL. */
+    CLOCK_DeinitAudioPll();
+    /* Bypass Audio PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
+    /* Set divider for Audio PLL. */
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
+    CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
+    /* Enable Audio PLL output. */
+    CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
+    /* Init Video PLL. */
+    uint32_t pllVideo;
+    /* Disable Video PLL output before initial Video PLL. */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+    CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+    CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+    pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+               CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+    pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+    CCM_ANALOG->PLL_VIDEO = pllVideo;
+    while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
+    {
+    }
+    /* Disable bypass for Video PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
+    /* DeInit Enet PLL. */
+    CLOCK_DeinitEnetPll();
+    /* Bypass Enet PLL. */
+    CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
+    /* Set Enet output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+    /* Enable Enet output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
+    /* Set Enet2 output divider. */
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
+    /* Enable Enet2 output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
+    /* Enable Enet25M output. */
+    CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
+    /* Init Usb2 PLL. */
+    CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
+    /* Set preperiph clock source. */
+    CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
+    /* Set periph clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphMux, 0);
+    /* Set periph clock2 clock source. */
+    CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
+    /* Set per clock source. */
+    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    /* Set lvds1 clock source. */
+    CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+    /* Set clock out1 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
+    /* Set clock out1 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
+    /* Set clock out2 divider. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
+    /* Set clock out2 source. */
+    CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
+    /* Set clock out1 drives clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
+    /* Disable clock out1. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
+    /* Disable clock out2. */
+    CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
+    /* Set SAI1 MCLK1 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
+    /* Set SAI1 MCLK2 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
+    /* Set SAI1 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
+    /* Set SAI2 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
+    /* Set SAI3 MCLK3 clock source. */
+    IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
+    /* Set MQS configuration. */
+    IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
+    /* Set ENET Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+    /* Set ENET2 Ref clock source. */
+    IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
+    /* Set GPT1 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
+    /* Set GPT2 High frequency reference clock source. */
+    IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h
new file mode 100644
index 000000000..7ce24b6f4
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/board/clock_config.h
@@ -0,0 +1,123 @@
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             600000000U  /*!< Core clock frequency: 600000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT               40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT               12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK             1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK              0UL
+#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK              2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK           1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK               0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK                0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT          130909090UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           130909090UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT             67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK                  1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK              480000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT              75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK                480000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT            198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT            198000000UL
+
+/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/hw/bsp/imxrt/boards/teensy_41/teensy41.mex b/hw/bsp/imxrt/boards/teensy_41/teensy41.mex
new file mode 100644
index 000000000..39b3ed606
--- /dev/null
+++ b/hw/bsp/imxrt/boards/teensy_41/teensy41.mex
@@ -0,0 +1,1001 @@
+<?xml version="1.0" encoding= "UTF-8" ?>
+<configuration name="MIMXRT1060-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="2174caba-38fe-48d5-8f89-42a23354d23b" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+   <common>
+      <processor>MIMXRT1062xxxxA</processor>
+      <package>MIMXRT1062DVL6A</package>
+      <board>MIMXRT1060-EVK</board>
+      <board_revision>A2</board_revision>
+      <mcu_data>ksdk2_0</mcu_data>
+      <cores selected="core0">
+         <core name="Cortex-M7F" id="core0" description="M7 core"/>
+      </cores>
+      <description></description>
+   </common>
+   <preferences>
+      <validate_boot_init_only>false</validate_boot_init_only>
+      <generate_extended_information>false</generate_extended_information>
+      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
+      <update_include_paths>true</update_include_paths>
+      <generate_registers_defines>false</generate_registers_defines>
+   </preferences>
+   <tools>
+      <pins name="Pins" version="13.1" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/pin_mux.c" update_enabled="true"/>
+            <file path="board/pin_mux.h" update_enabled="true"/>
+         </generated_project_files>
+         <pins_profile>
+            <processor_version>13.0.2</processor_version>
+            <power_domains/>
+         </pins_profile>
+         <functions_list>
+            <function name="BOARD_InitPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins/>
+            </function>
+            <function name="BOARD_InitDEBUG_UARTPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>true</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
+                     <pin_features>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Disable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+               </pins>
+            </function>
+            <function name="BOARD_InitSDRAMPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="SEMC" signal="ADDR, 00" pin_num="C2" pin_signal="GPIO_EMC_09"/>
+                  <pin peripheral="SEMC" signal="ADDR, 01" pin_num="G1" pin_signal="GPIO_EMC_10"/>
+                  <pin peripheral="SEMC" signal="ADDR, 02" pin_num="G3" pin_signal="GPIO_EMC_11"/>
+                  <pin peripheral="SEMC" signal="ADDR, 03" pin_num="H1" pin_signal="GPIO_EMC_12"/>
+                  <pin peripheral="SEMC" signal="ADDR, 04" pin_num="A6" pin_signal="GPIO_EMC_13"/>
+                  <pin peripheral="SEMC" signal="ADDR, 05" pin_num="B6" pin_signal="GPIO_EMC_14"/>
+                  <pin peripheral="SEMC" signal="ADDR, 06" pin_num="B1" pin_signal="GPIO_EMC_15"/>
+                  <pin peripheral="SEMC" signal="ADDR, 07" pin_num="A5" pin_signal="GPIO_EMC_16"/>
+                  <pin peripheral="SEMC" signal="ADDR, 08" pin_num="A4" pin_signal="GPIO_EMC_17"/>
+                  <pin peripheral="SEMC" signal="ADDR, 09" pin_num="B2" pin_signal="GPIO_EMC_18"/>
+                  <pin peripheral="SEMC" signal="ADDR, 10" pin_num="G2" pin_signal="GPIO_EMC_23"/>
+                  <pin peripheral="SEMC" signal="ADDR, 11" pin_num="B4" pin_signal="GPIO_EMC_19"/>
+                  <pin peripheral="SEMC" signal="ADDR, 12" pin_num="A3" pin_signal="GPIO_EMC_20"/>
+                  <pin peripheral="SEMC" signal="BA, 0" pin_num="C1" pin_signal="GPIO_EMC_21"/>
+                  <pin peripheral="SEMC" signal="BA, 1" pin_num="F1" pin_signal="GPIO_EMC_22"/>
+                  <pin peripheral="SEMC" signal="semc_cas" pin_num="D3" pin_signal="GPIO_EMC_24"/>
+                  <pin peripheral="SEMC" signal="semc_cke" pin_num="A2" pin_signal="GPIO_EMC_27"/>
+                  <pin peripheral="SEMC" signal="semc_clk" pin_num="B3" pin_signal="GPIO_EMC_26"/>
+                  <pin peripheral="SEMC" signal="DATA, 00" pin_num="E3" pin_signal="GPIO_EMC_00"/>
+                  <pin peripheral="SEMC" signal="DATA, 01" pin_num="F3" pin_signal="GPIO_EMC_01"/>
+                  <pin peripheral="SEMC" signal="DATA, 02" pin_num="F4" pin_signal="GPIO_EMC_02"/>
+                  <pin peripheral="SEMC" signal="DATA, 03" pin_num="G4" pin_signal="GPIO_EMC_03"/>
+                  <pin peripheral="SEMC" signal="DATA, 04" pin_num="F2" pin_signal="GPIO_EMC_04"/>
+                  <pin peripheral="SEMC" signal="DATA, 05" pin_num="G5" pin_signal="GPIO_EMC_05"/>
+                  <pin peripheral="SEMC" signal="DATA, 06" pin_num="H5" pin_signal="GPIO_EMC_06"/>
+                  <pin peripheral="SEMC" signal="DATA, 07" pin_num="H4" pin_signal="GPIO_EMC_07"/>
+                  <pin peripheral="SEMC" signal="DATA, 08" pin_num="C6" pin_signal="GPIO_EMC_30"/>
+                  <pin peripheral="SEMC" signal="DATA, 09" pin_num="C5" pin_signal="GPIO_EMC_31"/>
+                  <pin peripheral="SEMC" signal="DATA, 10" pin_num="D5" pin_signal="GPIO_EMC_32"/>
+                  <pin peripheral="SEMC" signal="DATA, 11" pin_num="C4" pin_signal="GPIO_EMC_33"/>
+                  <pin peripheral="SEMC" signal="DATA, 12" pin_num="D4" pin_signal="GPIO_EMC_34"/>
+                  <pin peripheral="SEMC" signal="DATA, 13" pin_num="E5" pin_signal="GPIO_EMC_35"/>
+                  <pin peripheral="SEMC" signal="DATA, 14" pin_num="C3" pin_signal="GPIO_EMC_36"/>
+                  <pin peripheral="SEMC" signal="DATA, 15" pin_num="E4" pin_signal="GPIO_EMC_37"/>
+                  <pin peripheral="SEMC" signal="DM, 0" pin_num="H3" pin_signal="GPIO_EMC_08"/>
+                  <pin peripheral="SEMC" signal="DM, 1" pin_num="D6" pin_signal="GPIO_EMC_38"/>
+                  <pin peripheral="SEMC" signal="semc_ras" pin_num="D2" pin_signal="GPIO_EMC_25"/>
+                  <pin peripheral="SEMC" signal="semc_we" pin_num="D1" pin_signal="GPIO_EMC_28"/>
+                  <pin peripheral="SEMC" signal="CS, 0" pin_num="E1" pin_signal="GPIO_EMC_29"/>
+                  <pin peripheral="SEMC" signal="semc_dqs" pin_num="B7" pin_signal="GPIO_EMC_39"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCSIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CSI" description="Peripheral CSI is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="Peripheral" resourceId="LPI2C1" description="Peripheral LPI2C1 is not initialized" problem_level="1" source="Pins:BOARD_InitCSIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCSIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CSI" signal="csi_data, 09" pin_num="H13" pin_signal="GPIO_AD_B1_08"/>
+                  <pin peripheral="CSI" signal="csi_data, 08" pin_num="M13" pin_signal="GPIO_AD_B1_09"/>
+                  <pin peripheral="CSI" signal="csi_data, 07" pin_num="L13" pin_signal="GPIO_AD_B1_10"/>
+                  <pin peripheral="CSI" signal="csi_data, 06" pin_num="J13" pin_signal="GPIO_AD_B1_11"/>
+                  <pin peripheral="CSI" signal="csi_data, 05" pin_num="H12" pin_signal="GPIO_AD_B1_12"/>
+                  <pin peripheral="CSI" signal="csi_data, 04" pin_num="H11" pin_signal="GPIO_AD_B1_13"/>
+                  <pin peripheral="CSI" signal="csi_data, 02" pin_num="J14" pin_signal="GPIO_AD_B1_15"/>
+                  <pin peripheral="CSI" signal="csi_data, 03" pin_num="G12" pin_signal="GPIO_AD_B1_14"/>
+                  <pin peripheral="CSI" signal="csi_pixclk" pin_num="L12" pin_signal="GPIO_AD_B1_04"/>
+                  <pin peripheral="CSI" signal="csi_mclk" pin_num="K12" pin_signal="GPIO_AD_B1_05"/>
+                  <pin peripheral="CSI" signal="csi_vsync" pin_num="J12" pin_signal="GPIO_AD_B1_06"/>
+                  <pin peripheral="CSI" signal="csi_hsync" pin_num="K10" pin_signal="GPIO_AD_B1_07"/>
+                  <pin peripheral="LPI2C1" signal="SCL" pin_num="J11" pin_signal="GPIO_AD_B1_00">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SCL"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LPI2C1" signal="SDA" pin_num="K11" pin_signal="GPIO_AD_B1_01">
+                     <pin_features>
+                        <pin_feature name="identifier" value="CSI_I2C_SDA"/>
+                        <pin_feature name="software_input_on" value="Disable"/>
+                        <pin_feature name="hysteresis_enable" value="Disable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_22K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Keeper"/>
+                        <pin_feature name="pull_keeper_enable" value="Enable"/>
+                        <pin_feature name="open_drain" value="Enable"/>
+                        <pin_feature name="speed" value="MHZ_100"/>
+                        <pin_feature name="drive_strength" value="R0_6"/>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="F11" pin_signal="GPIO_AD_B0_04"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitLCDPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="LCDIF" description="Peripheral LCDIF is not initialized" problem_level="1" source="Pins:BOARD_InitLCDPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitLCDPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 00" pin_num="C8" pin_signal="GPIO_B0_04">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 01" pin_num="B8" pin_signal="GPIO_B0_05">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 02" pin_num="A8" pin_signal="GPIO_B0_06">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_clk" pin_num="D7" pin_signal="GPIO_B0_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 03" pin_num="A9" pin_signal="GPIO_B0_07">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 04" pin_num="B9" pin_signal="GPIO_B0_08">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 05" pin_num="C9" pin_signal="GPIO_B0_09">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 06" pin_num="D9" pin_signal="GPIO_B0_10">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 07" pin_num="A10" pin_signal="GPIO_B0_11">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 08" pin_num="C10" pin_signal="GPIO_B0_12">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 09" pin_num="D10" pin_signal="GPIO_B0_13">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 10" pin_num="E10" pin_signal="GPIO_B0_14">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 11" pin_num="E11" pin_signal="GPIO_B0_15">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 12" pin_num="A11" pin_signal="GPIO_B1_00">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 13" pin_num="B11" pin_signal="GPIO_B1_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 14" pin_num="C11" pin_signal="GPIO_B1_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_data, 15" pin_num="D11" pin_signal="GPIO_B1_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_enable" pin_num="E7" pin_signal="GPIO_B0_01">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_hsync" pin_num="E8" pin_signal="GPIO_B0_02">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="LCDIF" signal="lcdif_vsync" pin_num="D8" pin_signal="GPIO_B0_03">
+                     <pin_features>
+                        <pin_feature name="hysteresis_enable" value="Enable"/>
+                        <pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
+                        <pin_feature name="pull_keeper_select" value="Pull"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO2" signal="gpio_io, 31" pin_num="B14" pin_signal="GPIO_B1_15">
+                     <pin_features>
+                        <pin_feature name="slew_rate" value="Slow"/>
+                     </pin_features>
+                  </pin>
+                  <pin peripheral="GPIO1" signal="gpio_io, 02" pin_num="M11" pin_signal="GPIO_AD_B0_02"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitCANPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="CAN2" description="Peripheral CAN2 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="CAN2" signal="TX" pin_num="H14" pin_signal="GPIO_AD_B0_14"/>
+                  <pin peripheral="CAN2" signal="RX" pin_num="L10" pin_signal="GPIO_AD_B0_15"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitENETPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="ENET" signal="enet_mdc" pin_num="A7" pin_signal="GPIO_EMC_40"/>
+                  <pin peripheral="ENET" signal="enet_mdio" pin_num="C7" pin_signal="GPIO_EMC_41"/>
+                  <pin peripheral="ENET" signal="enet_ref_clk" pin_num="B13" pin_signal="GPIO_B1_10"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="E12" pin_signal="GPIO_B1_04"/>
+                  <pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="D12" pin_signal="GPIO_B1_05"/>
+                  <pin peripheral="ENET" signal="enet_rx_en" pin_num="C12" pin_signal="GPIO_B1_06"/>
+                  <pin peripheral="ENET" signal="enet_rx_er" pin_num="C13" pin_signal="GPIO_B1_11"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="B12" pin_signal="GPIO_B1_07"/>
+                  <pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="A12" pin_signal="GPIO_B1_08"/>
+                  <pin peripheral="ENET" signal="enet_tx_en" pin_num="A13" pin_signal="GPIO_B1_09"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitUSDHCPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="J2" pin_signal="GPIO_SD_B0_05"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="H2" pin_signal="GPIO_SD_B0_04"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="K1" pin_signal="GPIO_SD_B0_03"/>
+                  <pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="J1" pin_signal="GPIO_SD_B0_02"/>
+                  <pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="J4" pin_signal="GPIO_SD_B0_00"/>
+                  <pin peripheral="USDHC1" signal="usdhc_clk" pin_num="J3" pin_signal="GPIO_SD_B0_01"/>
+                  <pin peripheral="USDHC1" signal="usdhc_vselect" pin_num="C14" pin_signal="GPIO_B1_14"/>
+               </pins>
+            </function>
+            <function name="BOARD_InitQSPIPins">
+               <description>Configures pin routing and optionally pin electrical features.</description>
+               <options>
+                  <callFromInitBoot>false</callFromInitBoot>
+                  <coreID>core0</coreID>
+                  <enableClock>true</enableClock>
+               </options>
+               <dependencies>
+                  <dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="initialized" evaluation="equal">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <pins>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="P3" pin_signal="GPIO_SD_B1_08"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="N4" pin_signal="GPIO_SD_B1_09"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="P4" pin_signal="GPIO_SD_B1_10"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="P5" pin_signal="GPIO_SD_B1_11"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="L4" pin_signal="GPIO_SD_B1_07"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="L3" pin_signal="GPIO_SD_B1_06"/>
+                  <pin peripheral="FLEXSPI" signal="FLEXSPI_A_DQS" pin_num="N3" pin_signal="GPIO_SD_B1_05"/>
+               </pins>
+            </function>
+         </functions_list>
+      </pins>
+      <clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/clock_config.c" update_enabled="true"/>
+            <file path="board/clock_config.h" update_enabled="true"/>
+         </generated_project_files>
+         <clocks_profile>
+            <processor_version>13.0.2</processor_version>
+         </clocks_profile>
+         <clock_configurations>
+            <clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
+               <description></description>
+               <options/>
+               <dependencies>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>INPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="routed" evaluation="">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="direction" evaluation="">
+                        <data>OUTPUT</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+                  <dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
+                     <feature name="enabled" evaluation="equal" configuration="core0">
+                        <data>true</data>
+                     </feature>
+                  </dependency>
+               </dependencies>
+               <clock_sources>
+                  <clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
+               </clock_sources>
+               <clock_outputs>
+                  <clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
+                  <clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
+                  <clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
+                  <clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
+                  <clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="PLL7_MAIN_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
+                  <clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
+                  <clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
+                  <clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USBPHY2_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+                  <clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
+               </clock_outputs>
+               <clock_settings>
+                  <setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
+                  <setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
+                  <setting id="CCM.LCDIF_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM.LCDIF_PRED.scale" value="2" locked="true"/>
+                  <setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
+                  <setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
+                  <setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
+                  <setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
+                  <setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
+                  <setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="true"/>
+                  <setting id="CCM_ANALOG.PLL7_BYPASS.sel" value="CCM_ANALOG.PLL7" locked="false"/>
+                  <setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="true"/>
+                  <setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_USB2_POWER_CFG" value="Yes" locked="false"/>
+                  <setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
+               </clock_settings>
+               <called_from_default_init>true</called_from_default_init>
+            </clock_configuration>
+         </clock_configurations>
+      </clocks>
+      <dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <dcdx_profile>
+            <processor_version>0.0.0</processor_version>
+         </dcdx_profile>
+         <dcdx_configurations/>
+      </dcdx>
+      <periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
+         <generated_project_files>
+            <file path="board/peripherals.c" update_enabled="true"/>
+            <file path="board/peripherals.h" update_enabled="true"/>
+         </generated_project_files>
+         <peripherals_profile>
+            <processor_version>13.0.2</processor_version>
+         </peripherals_profile>
+         <functional_groups>
+            <functional_group name="BOARD_InitPeripherals" uuid="96c1cec6-3bd3-47a2-8301-f38e4b0dd25f" called_from_default_init="true" id_prefix="" core="core0">
+               <description></description>
+               <options/>
+               <dependencies/>
+               <instances>
+                  <instance name="CAN" uuid="eb0900eb-d552-4097-9dcf-a07e592a887f" type="flexcan" type_id="flexcan_ba45456ec815807245205237e2bf425b" mode="interrupts" peripheral="CAN2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="interruptsCfg">
+                        <setting name="messageBufferIrqs" value="0"/>
+                        <setting name="messageBufferIrqs2" value="0"/>
+                        <set name="interruptsEnable">
+                           <selected/>
+                        </set>
+                        <setting name="enable_irq" value="false"/>
+                        <struct name="interrupt_shared">
+                           <setting name="IRQn" value="CAN2_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="fsl_flexcan" quick_selection="default">
+                        <struct name="can_config">
+                           <setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="baudRate" value="1000000"/>
+                           <setting name="maxMbNum" value="16"/>
+                           <setting name="enableLoopBack" value="false"/>
+                           <setting name="enableSelfWakeup" value="false"/>
+                           <setting name="enableIndividMask" value="false"/>
+                           <struct name="timingConfig">
+                              <setting name="propSeg" value="2"/>
+                              <setting name="phaseSeg1" value="4"/>
+                              <setting name="phaseSeg2" value="3"/>
+                              <setting name="rJumpwidth" value="2"/>
+                              <struct name="bitTime"/>
+                           </struct>
+                        </struct>
+                        <setting name="enableRxFIFO" value="false"/>
+                        <struct name="rxFIFO">
+                           <setting name="idFilterTable" value=""/>
+                           <setting name="idFilterNum" value="num0"/>
+                           <setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
+                           <setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
+                        </struct>
+                        <array name="channels">
+                           <struct name="0">
+                              <setting name="mbID" value="0"/>
+                              <setting name="mbType" value="mbRx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                           <struct name="1">
+                              <setting name="mbID" value="1"/>
+                              <setting name="mbType" value="mbTx"/>
+                              <struct name="rxMb">
+                                 <setting name="id" value="0"/>
+                                 <setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
+                                 <setting name="type" value="kFLEXCAN_FrameTypeData"/>
+                              </struct>
+                           </struct>
+                        </array>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI" uuid="f67d9a64-c26d-4421-9805-a062b24146f2" type="csi" type_id="csi_3739ec1355c7b915be929f3b7e35095b" mode="interrupt" peripheral="CSI" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_csi" quick_selection="QuickSelection1">
+                        <struct name="clockConfig">
+                           <setting name="clockSource" value="BusInterfaceClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <setting name="masterClockSource" value="CsiClock"/>
+                           <setting name="masterClockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        </struct>
+                        <struct name="config">
+                           <setting name="format" value="RGB565"/>
+                           <setting name="i_width" value="320"/>
+                           <setting name="i_height" value="240"/>
+                           <setting name="dataBus" value="kCSI_DataBus8Bit"/>
+                           <setting name="workMode" value="kCSI_GatedClockMode"/>
+                           <setting name="useExtVsync" value="true"/>
+                           <set name="polarityFlags">
+                              <selected/>
+                           </set>
+                           <struct name="buffers_config">
+                              <setting name="bufferName" value="defaultBuffer"/>
+                              <setting name="bufCount" value="4"/>
+                              <setting name="bufferAlign" value="64"/>
+                           </struct>
+                        </struct>
+                        <struct name="interruptsCfg">
+                           <setting name="isInterruptEnabled" value="false"/>
+                           <set name="interruptSources">
+                              <selected/>
+                           </set>
+                           <struct name="interrupt">
+                              <setting name="IRQn" value="CSI_IRQn"/>
+                              <setting name="enable_interrrupt" value="enabled"/>
+                              <setting name="enable_priority" value="false"/>
+                              <setting name="priority" value="0"/>
+                              <setting name="enable_custom_name" value="false"/>
+                           </struct>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="CSI_LPI2C" uuid="f2c6cd0a-751c-4424-9248-a4d98da47de7" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="main" quick_selection="qs_interrupt">
+                        <setting name="clockSource" value="Lpi2cClock"/>
+                        <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LPI2C1_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                     <config_set name="master" quick_selection="qs_master_transfer">
+                        <setting name="mode" value="transfer"/>
+                        <struct name="config">
+                           <setting name="enableMaster" value="true"/>
+                           <setting name="enableDoze" value="true"/>
+                           <setting name="debugEnable" value="false"/>
+                           <setting name="ignoreAck" value="false"/>
+                           <setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
+                           <setting name="baudRate_Hz" value="100000"/>
+                           <setting name="busIdleTimeout_ns" value="0"/>
+                           <setting name="pinLowTimeout_ns" value="0"/>
+                           <setting name="sdaGlitchFilterWidth_ns" value="0"/>
+                           <setting name="sclGlitchFilterWidth_ns" value="0"/>
+                           <struct name="hostRequest">
+                              <setting name="enable" value="false"/>
+                              <setting name="source" value="kLPI2C_HostRequestExternalPin"/>
+                              <setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
+                           </struct>
+                           <set name="edmaRequestSources">
+                              <selected/>
+                           </set>
+                        </struct>
+                        <struct name="transfer">
+                           <setting name="blocking" value="false"/>
+                           <setting name="enable_custom_handle" value="false"/>
+                           <struct name="callback">
+                              <setting name="name" value=""/>
+                              <setting name="userData" value=""/>
+                           </struct>
+                           <set name="flags">
+                              <selected/>
+                           </set>
+                           <setting name="slaveAddress" value="0"/>
+                           <setting name="direction" value="kLPI2C_Write"/>
+                           <setting name="subaddress" value="0"/>
+                           <setting name="subaddressSize" value="1"/>
+                           <setting name="blocking_buffer" value="false"/>
+                           <setting name="enable_custom_buffer" value="false"/>
+                           <setting name="dataSize" value="1"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="DEBUG_UART" uuid="01f250e2-83d7-4b7b-a98d-772d1c3bdb42" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="lpuartConfig_t">
+                        <struct name="lpuartConfig">
+                           <setting name="clockSource" value="LpuartClock"/>
+                           <setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
+                           <setting name="baudRate_Bps" value="115200"/>
+                           <setting name="parityMode" value="kLPUART_ParityDisabled"/>
+                           <setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
+                           <setting name="isMsb" value="false"/>
+                           <setting name="stopBitCount" value="kLPUART_OneStopBit"/>
+                           <setting name="enableMatchAddress1" value="false"/>
+                           <setting name="matchAddress1" value="0"/>
+                           <setting name="enableMatchAddress2" value="false"/>
+                           <setting name="matchAddress2" value="0"/>
+                           <setting name="txFifoWatermark" value="0"/>
+                           <setting name="rxFifoWatermark" value="1"/>
+                           <setting name="enableRxRTS" value="false"/>
+                           <setting name="enableTxCTS" value="false"/>
+                           <setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
+                           <setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
+                           <setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
+                           <setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
+                           <setting name="enableTx" value="true"/>
+                           <setting name="enableRx" value="true"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="LCD" uuid="90a0c31d-6042-4687-af0f-0892536bc1ba" type="elcdif" type_id="elcdif_1c39bcb43ed1a24bc8980672c7378576" mode="rgbMode" peripheral="LCDIF" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
+                     <config_set name="fsl_elcdif">
+                        <struct name="config">
+                           <setting name="panelWidthInt" value="480"/>
+                           <setting name="panelHeightInt" value="272"/>
+                           <setting name="hsw" value="41"/>
+                           <setting name="hfp" value="4"/>
+                           <setting name="hbp" value="8"/>
+                           <setting name="vsw" value="10"/>
+                           <setting name="vfp" value="4"/>
+                           <setting name="vbp" value="3"/>
+                           <setting name="frameRate" value="60 Hz"/>
+                           <setting name="clockSource" value="LcdIfClock"/>
+                           <setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
+                           <struct name="polarityFlags_st">
+                              <setting name="vSyncActive" value="kELCDIF_VsyncActiveLow"/>
+                              <setting name="hSyncActive" value="kELCDIF_HsyncActiveLow"/>
+                              <setting name="dataEnableActive" value="kELCDIF_DataEnableActiveLow"/>
+                              <setting name="driveDataClkEdge" value="kELCDIF_DriveDataOnFallingClkEdge"/>
+                           </struct>
+                           <setting name="bufferName" value="defaultBuffer"/>
+                           <setting name="bufferAlign" value="64"/>
+                           <setting name="pixelFormat" value="kELCDIF_PixelFormatRGB565"/>
+                           <setting name="dataBus" value="kELCDIF_DataBus16Bit"/>
+                           <setting name="enablePxpHandShake" value="false"/>
+                           <setting name="start" value="false"/>
+                        </struct>
+                        <setting name="isInterruptEnabled" value="true"/>
+                        <set name="elcdifInterruptSources">
+                           <selected>
+                              <id>kELCDIF_CurFrameDoneInterruptEnable</id>
+                           </selected>
+                        </set>
+                        <struct name="interrupt">
+                           <setting name="IRQn" value="LCDIF_IRQn"/>
+                           <setting name="enable_interrrupt" value="enabled"/>
+                           <setting name="enable_priority" value="false"/>
+                           <setting name="priority" value="0"/>
+                           <setting name="enable_custom_name" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
+                  <instance name="NVIC" uuid="b31fa225-2a52-486b-9c5c-33a184a2c716" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="nvic">
+                        <array name="interrupt_table"/>
+                        <array name="interrupts"/>
+                     </config_set>
+                  </instance>
+               </instances>
+            </functional_group>
+         </functional_groups>
+         <components>
+            <component name="system" uuid="aa3cc953-557b-4557-b7fe-6fedc31acf98" type_id="system">
+               <config_set_global name="global_system_definitions">
+                  <setting name="user_definitions" value=""/>
+                  <setting name="user_includes" value=""/>
+               </config_set_global>
+            </component>
+            <component name="msg" uuid="8b3f852e-ee1e-45e9-abff-0ff722f1d65d" type_id="msg">
+               <config_set_global name="global_messages"/>
+            </component>
+            <component name="gpio_adapter_common" uuid="539d282e-5136-4289-9058-9a46b221ca45" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
+               <config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
+            </component>
+            <component name="generic_uart" uuid="6e4c02c4-0524-4905-91b5-01d2e2502186" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
+               <config_set_global name="global_uart"/>
+            </component>
+            <component name="generic_can" uuid="c6d8fd36-2bbd-44c6-a160-54e7e12d0807" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
+               <config_set_global name="global_can"/>
+            </component>
+            <component name="uart_cmsis_common" uuid="7d3626d3-4536-4838-a35d-3b8cf5a2bd71" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
+               <config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
+            </component>
+            <component name="generic_enet" uuid="738ea8df-6176-4e52-b4c7-b88aa9c17d13" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
+               <config_set_global name="global_enet"/>
+            </component>
+         </components>
+      </periphs>
+      <tee name="TEE" version="4.0" enabled="false" update_project_code="true">
+         <generated_project_files/>
+         <tee_profile>
+            <processor_version>0.0.0</processor_version>
+         </tee_profile>
+      </tee>
+   </tools>
+</configuration>
diff --git a/hw/bsp/mcx/mcx.jlinkscript b/hw/bsp/imxrt/debug.jlinkscript
similarity index 100%
rename from hw/bsp/mcx/mcx.jlinkscript
rename to hw/bsp/imxrt/debug.jlinkscript
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 735fbdb9b..9aa55bc94 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -234,21 +234,18 @@ int board_uart_read(uint8_t* buf, int len)
   return count;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const * buf, int len) {
   LPUART_WriteBlocking(UART_PORT, (uint8_t const*)buf, len);
   return len;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
 #endif
diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index a8841f8ce..f1c5b0ab1 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -24,12 +24,14 @@ set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "")
 function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
     add_library(${BOARD_TARGET} STATIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c
+      #${SDK_DIR}/drivers/adc_12b1msps_sar/fsl_adc.c
       ${SDK_DIR}/drivers/common/fsl_common.c
       ${SDK_DIR}/drivers/igpio/fsl_gpio.c
+      ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c
       ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
       ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
       ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/project_template/clock_config.c
       ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
       )
     target_compile_definitions(${BOARD_TARGET} PUBLIC
@@ -39,12 +41,15 @@ function(add_board_target BOARD_TARGET)
       XIP_BOOT_HEADER_ENABLE=1
       )
     target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board
       ${CMSIS_DIR}/CMSIS/Core/Include
       ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/project_template
       ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+      #${SDK_DIR}/drivers/adc_12b1msps_sar
       ${SDK_DIR}/drivers/common
       ${SDK_DIR}/drivers/igpio
+      ${SDK_DIR}/drivers/lpspi
       ${SDK_DIR}/drivers/lpuart
       )
 
diff --git a/hw/bsp/mcx/debug.jlinkscript b/hw/bsp/mcx/debug.jlinkscript
new file mode 100644
index 000000000..fd8bcffef
--- /dev/null
+++ b/hw/bsp/mcx/debug.jlinkscript
@@ -0,0 +1,5 @@
+int SetupTarget(void) {
+  JLINK_ExecCommand("SetRTTSearchRanges 0x20000000 0x40000");
+
+  return 0;
+}

From 8b6d0a166b3837e664eeabbada724b678b7fd62d Mon Sep 17 00:00:00 2001
From: Scott Shawcroft <scott@tannewt.org>
Date: Fri, 14 Jul 2023 15:30:22 -0700
Subject: [PATCH 1893/2085] Fix host buffer alignment setting

---
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 6 ++++++
 src/tusb_option.h                         | 6 +++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index c14f00431..96f0ba766 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -78,6 +78,12 @@ TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void const* addr, ui
 TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void const* addr, uint32_t data_size) {
   const uintptr_t addr32 = (uintptr_t) addr;
   if (imxrt_is_cache_mem(addr32)) {
+    // Invalidating does not push cached changes back to RAM so we need to be
+    // *very* careful when we do it. If we're not aligned, then we risk resetting
+    // values back to their RAM state.
+    // if (addr32 % 32 != 0) {
+    //   TU_BREAKPOINT();
+    // }
     SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
   }
 }
diff --git a/src/tusb_option.h b/src/tusb_option.h
index f16d8a5d0..c792efe6a 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -431,7 +431,11 @@
 
 // Attribute to align memory for host controller
 #ifndef CFG_TUH_MEM_ALIGN
-  #define CFG_TUH_MEM_ALIGN   TU_ATTR_ALIGNED(4)
+  #ifdef CFG_TUSB_MEM_ALIGN
+    #define CFG_TUH_MEM_ALIGN   CFG_TUSB_MEM_ALIGN
+  #else
+    #define CFG_TUH_MEM_ALIGN   TU_ATTR_ALIGNED(4)
+  #endif
 #endif
 
 //------------- CLASS -------------//

From 1923b1845d033a3d42db9b739029b2cc39248150 Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Fri, 23 Jun 2023 10:26:45 +0200
Subject: [PATCH 1894/2085] fix(RA_hcd): STALL status can be also 3 not only 2

---
 src/host/usbh.c                         | 2 +-
 src/portable/renesas/rusb2/hcd_rusb2.c  | 5 +++--
 src/portable/renesas/rusb2/rusb2_type.h | 1 +
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index f3e9d3858..184bda23b 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -791,7 +791,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
   uint8_t const dir   = tu_edpt_dir(ep_addr);
   tu_edpt_state_t* ep_state = &dev->ep_status[epnum][dir];
 
-  TU_LOG_USBH("  Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
+  TU_LOG_USBH("  Queue EP %02X with %u bytes ... \r\n", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(ep_state->busy == 0);
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 0e6fa1618..193e07d8c 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -116,7 +116,7 @@ static unsigned find_pipe(unsigned xfer)
     for (int i = 3; i <= 5; ++i) {
       if (0 == _hcd.pipe[i].ep) return  i;
     }
-    for (int i = 1; i <= 1; ++i) {
+    for (int i = 1; i <= 2; ++i) {
       if (0 == _hcd.pipe[i].ep) return  i;
     }
     break;
@@ -413,6 +413,7 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
   switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) {
     default: return;
     case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
+    case RUSB2_PIPE_CTR_PID_STALL2: result = XFER_RESULT_STALLED; break;
     case RUSB2_PIPE_CTR_PID_NAK:   result = XFER_RESULT_FAILED;  break;
   }
   pipe_state_t *pipe = &_hcd.pipe[num];
@@ -586,7 +587,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
   uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0];
   for (int i = 0; i < 2 * 15; ++i, ++ep) {
     unsigned num = *ep;
-    if (!num || dev_addr != _hcd.pipe[num].dev) continue;
+    if (!num || (dev_addr != _hcd.pipe[num].dev)) continue;
 
     ctr = (uint16_t volatile*)&RUSB2->PIPE_CTR[num - 1];
     *ctr = 0;
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 90ba4f012..83119507a 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -1568,6 +1568,7 @@ TU_ATTR_BIT_FIELD_ORDER_END
 #define RUSB2_PIPE_CTR_PID_NAK          (0U << RUSB2_PIPE_CTR_PID_Pos)    /* NAK response */
 #define RUSB2_PIPE_CTR_PID_BUF          (1U << RUSB2_PIPE_CTR_PID_Pos)    /* BUF response (depends buffer state) */
 #define RUSB2_PIPE_CTR_PID_STALL        (2U << RUSB2_PIPE_CTR_PID_Pos)    /* STALL response */
+#define RUSB2_PIPE_CTR_PID_STALL2       (3U << RUSB2_PIPE_CTR_PID_Pos)    /* Also STALL response */
 
 #define RUSB2_DVSTCTR0_RHST_LS          (1U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Low-speed connection */
 #define RUSB2_DVSTCTR0_RHST_FS          (2U << RUSB2_DVSTCTR0_RHST_Pos)   /*  Full-speed connection */

From 41b608562a40b68d6b58d01a3239c466533b4b6b Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Fri, 23 Jun 2023 14:21:58 +0200
Subject: [PATCH 1895/2085] debugging can be configured on renesas hcd

---
 src/portable/renesas/rusb2/hcd_rusb2.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 193e07d8c..65bbc656b 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -41,6 +41,8 @@
   #error "Unsupported MCU"
 #endif
 
+#define TU_RUSB2_HCD_DBG   0
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
@@ -409,7 +411,7 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
   (void)rhport;
   xfer_result_t result;
   uint16_t volatile *ctr = get_pipectr(num);
-  // TU_LOG1("NRDY %d %x\n", num, *ctr);
+  TU_LOG(TU_RUSB2_HCD_DBG, "NRDY %d %x\n", num, *ctr);
   switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) {
     default: return;
     case RUSB2_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
@@ -442,7 +444,7 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
     hcd_event_xfer_complete(pipe->dev, pipe->ep,
                             pipe->length - pipe->remaining,
                             XFER_RESULT_SUCCESS, true);
-    //  TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining);
+    TU_LOG(TU_RUSB2_HCD_DBG, "C %d %d\r\n", num, pipe->length - pipe->remaining);
   }
 }
 
@@ -609,7 +611,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void)rhport;
-  //  TU_LOG1("S %d %x\n", dev_addr, RUSB2->DCPCTR);
+  TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, RUSB2->DCPCTR);
 
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
   TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ);
@@ -702,7 +704,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b
 {
   bool r;
   hcd_int_disable(rhport);
-  // TU_LOG1("X %d %x %u\n", dev_addr, ep_addr, buflen);
+  TU_LOG(TU_RUSB2_HCD_DBG, "X %d %x %u\n", dev_addr, ep_addr, buflen);
   r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen);
   hcd_int_enable(rhport);
   return r;
@@ -746,7 +748,7 @@ void hcd_int_handler(uint8_t rhport)
   /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
   RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
   RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
-  // TU_LOG1("IS %04x %04x\n", is0, is1);
+  TU_LOG(TU_RUSB2_HCD_DBG, "IS %04x %04x\n", is0, is1);
   is1 &= RUSB2->INTENB1;
   is0 &= RUSB2->INTENB0;
 

From 3230d5b1ea45ac2b17e4abaac2bfbe190360fff8 Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Fri, 23 Jun 2023 14:22:13 +0200
Subject: [PATCH 1896/2085] debugging can be configured on renesas dcd

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 78584125f..022c1b5b6 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -45,6 +45,8 @@
   #error "Unsupported MCU"
 #endif
 
+#define TU_RUSB2_DCD_DBG   0
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -444,7 +446,7 @@ static bool process_pipe_xfer(int buffer_type, uint8_t ep_addr, void* buffer, ui
       *ctr = RUSB2_PIPE_CTR_PID_BUF;
     }
   }
-  //  TU_LOG1("X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
+  TU_LOG(TU_RUSB2_DCD_DBG ,"X %x %d %d\r\n", ep_addr, total_bytes, buffer_type);
   return true;
 }
 
@@ -487,7 +489,7 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
     dcd_event_xfer_complete(rhport, pipe->ep,
                             pipe->length - pipe->remaining,
                             XFER_RESULT_SUCCESS, true);
-    //  TU_LOG1("C %d %d\r\n", num, pipe->length - pipe->remaining);
+    TU_LOG(TU_RUSB2_DCD_DBG, "C %d %d\r\n", num, pipe->length - pipe->remaining);
   }
 }
 
@@ -691,7 +693,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
   if (dir || (xfer != TUSB_XFER_BULK)) {
     *ctr = RUSB2_PIPE_CTR_PID_BUF;
   }
-  // TU_LOG1("O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP);
+  TU_LOG(TU_RUSB2_DCD_DBG, "O %d %x %x\r\n", RUSB2->PIPESEL, RUSB2->PIPECFG, RUSB2->PIPEMAXP);
   dcd_int_enable(rhport);
 
   return true;

From 5723d3808770a5fb1057534dd3c21be482e446eb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 17 Jul 2023 21:59:21 +0700
Subject: [PATCH 1897/2085] correct jlink dev for rt1010

---
 hw/bsp/imxrt/boards/metro_m7_1011/board.cmake  |  2 +-
 hw/bsp/imxrt/boards/metro_m7_1011/board.mk     |  2 +-
 hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake |  2 +-
 hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk    |  2 +-
 hw/bsp/imxrt/family.c                          | 10 ++++++++++
 5 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake
index 3ba95bf2c..99681ab12 100644
--- a/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake
@@ -1,6 +1,6 @@
 set(MCU_VARIANT MIMXRT1011)
 
-set(JLINK_DEVICE MIMXRT1011DAE5A)
+set(JLINK_DEVICE MIMXRT1011xxx5A)
 set(PYOCD_TARGET mimxrt1010)
 set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
 
diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk
index 89a459958..b845194c2 100644
--- a/hw/bsp/imxrt/boards/metro_m7_1011/board.mk
+++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.mk
@@ -5,7 +5,7 @@ MCU_VARIANT = MIMXRT1011
 LD_FILE = $(BOARD_PATH)/$(BOARD).ld
 
 # For flash-jlink target
-JLINK_DEVICE = MIMXRT1011DAE5A
+JLINK_DEVICE = MIMXRT1011xxx5A
 
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1010
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
index 3ba95bf2c..99681ab12 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake
@@ -1,6 +1,6 @@
 set(MCU_VARIANT MIMXRT1011)
 
-set(JLINK_DEVICE MIMXRT1011DAE5A)
+set(JLINK_DEVICE MIMXRT1011xxx5A)
 set(PYOCD_TARGET mimxrt1010)
 set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
 
diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
index 17dc01cd9..488a56fdc 100644
--- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
+++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk
@@ -2,7 +2,7 @@ CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
 MCU_VARIANT = MIMXRT1011
 
 # For flash-jlink target
-JLINK_DEVICE = MIMXRT1011DAE5A
+JLINK_DEVICE = MIMXRT1011xxx5A
 
 # For flash-pyocd target
 PYOCD_TARGET = mimxrt1010
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index 9aa55bc94..bfab1d496 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -91,6 +91,16 @@ void board_init(void)
   BOARD_BootClockRUN();
   SystemCoreClockUpdate();
 
+#ifdef TRACE_ETM
+  // RT1011 ETM pins
+//  IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U);
+//  IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U);
+//  IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U);
+//  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U);
+//  IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U);
+//  CLOCK_EnableClock(kCLOCK_Trace);
+#endif
+
   // Enable IOCON clock
   CLOCK_EnableClock(kCLOCK_Iomuxc);
 

From 2cd0b9ec35465aa54c57aee9cce68e556859db07 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 18 Jul 2023 15:27:51 +0700
Subject: [PATCH 1898/2085] fix etm trace clock with stm32h743eval board

---
 .idea/cmake.xml                               |   8 +-
 hw/bsp/lpc18/boards/mcb1800/board.h           |   1 -
 hw/bsp/stm32h7/boards/stm32h743eval/board.h   |  38 ++-----
 .../stm32h743eval/cubemx/stm32h743eval.ioc    | 102 +++++++++---------
 4 files changed, 67 insertions(+), 82 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 47ca8253e..788f70433 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -26,8 +26,10 @@
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
       <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
-      <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk" />
-      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk" />
+      <configuration PROFILE_NAME="metro m7 1011" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="rt1015 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1015_evk -DLOG=1" />
+      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1064_evk" />
       <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="lpcxpresso18s37" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso18s37" />
@@ -38,7 +40,6 @@
       <configuration PROFILE_NAME="b_g474e_dpow1 iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=b_g474e_dpow1 -DTOOLCHAIN=iar" />
       <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_kl25z -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32h743eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="metro m7" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="stm32f072disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f072disco" />
       <configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2" />
       <configuration PROFILE_NAME="stm32f769disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f769disco -DLOG=3 -DLOGGER=RTT" />
@@ -46,6 +47,7 @@
       <configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="rt1050 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1050_evkb -DLOG=1 -DLOGGER=RTT" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/lpc18/boards/mcb1800/board.h b/hw/bsp/lpc18/boards/mcb1800/board.h
index 5bfaa37cd..93b3cd112 100644
--- a/hw/bsp/lpc18/boards/mcb1800/board.h
+++ b/hw/bsp/lpc18/boards/mcb1800/board.h
@@ -71,7 +71,6 @@ static inline void board_lpc18_pinmux(void) {
 
     // USB0
     { 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 },		                // P6_3 USB0_PWR_EN, USB0 VBus function
-
     { 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 },			              // P9_5 USB1_VBUS_EN, USB1 VBus function
     { 0x2, 5, SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
   };
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
index 7e3c015c8..c46b525ca 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h
@@ -61,8 +61,7 @@
 //--------------------------------------------------------------------+
 // RCC Clock
 //--------------------------------------------------------------------+
-static inline void board_stm32h7_clock_init(void)
-{
+static inline void board_stm32h7_clock_init(void) {
   RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
   RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
@@ -75,7 +74,7 @@ static inline void board_stm32h7_clock_init(void)
      regarding system frequency refer to product datasheet.  */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
-  while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
+  while ( (PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY ) {}
 
   /* Enable HSE Oscillator and activate PLL with HSE as source */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
@@ -85,40 +84,23 @@ static inline void board_stm32h7_clock_init(void)
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 
-  // PLL1 for System Clock
-#ifdef TRACE_ETM
-  // From H743 eval board manual
-  // - ETM can only work at 50 MHz clock by default because ETM signals are shared with other peripherals. If better
-  //   performance of ETM is required (84 MHz/98 MHz), R217, R230, R231, R234, R236, SB2, SB5, SB8, SB11,
-  //   SB42, SB57 must be removed to reduce the stub on ETM signals. In this configuration SAI and PDM are not
-  //   functional and NOR Flash and the address of SRAM are limited on A18.
-  // - ETM trace function would be abnormal as SAI_SDB share the same pins with TRACE_D0, and TRACE_D0
-  //   would be forced high by SAI_SDB. When using ETM trace it is necessary to set ADCDAT1 pin (SAI_SDB signal
-  //   of the STM32) of audio codec WM8994ECS/R (U22) by software to be tri-state.
-
-  // Since Trace CLK = PLL1 / 3 --> max PLL1 clock is 150Mhz
-  RCC_OscInitStruct.PLL.PLLM = 2;
-  RCC_OscInitStruct.PLL.PLLN = 24;
-  RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLQ = 4;
-  RCC_OscInitStruct.PLL.PLLR = 2;
-  RCC_OscInitStruct.PLL.PLLFRACN = 0;
-#else
-  // Set PLL1 to 400Mhz
+  // PLL1 for System Clock (400Mhz)
+  // From H743 eval manual ETM can only work at 50 MHz clock by default because ETM signals
+  // are shared with other peripherals. Trace CLK = PLL1R.
   RCC_OscInitStruct.PLL.PLLM = 5;
   RCC_OscInitStruct.PLL.PLLN = 160;
   RCC_OscInitStruct.PLL.PLLP = 2;
-  RCC_OscInitStruct.PLL.PLLR = 2;
   RCC_OscInitStruct.PLL.PLLQ = 4;
-#endif
+  RCC_OscInitStruct.PLL.PLLR = 6; // Trace clock is 400/6 = 66.67 MHz (larger than 50 MHz but work well)
   RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
   RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
   HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
 
   /* Select PLL as system clock source and configure bus clocks dividers */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 |
-      RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1;
+                                RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1;
 
   RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
@@ -141,10 +123,10 @@ static inline void board_stm32h7_clock_init(void)
   HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
   /*activate CSI clock mondatory for I/O Compensation Cell*/
-  __HAL_RCC_CSI_ENABLE() ;
+  __HAL_RCC_CSI_ENABLE();
 
   /* Enable SYSCFG clock mondatory for I/O Compensation Cell */
-  __HAL_RCC_SYSCFG_CLK_ENABLE() ;
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
 
   /* Enables the I/O Compensation Cell */
   HAL_EnableCompensationCell();
diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
index 331080c17..01458a0a9 100644
--- a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
+++ b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc
@@ -892,93 +892,95 @@ ProjectManager.ProjectStructure=
 ProjectManager.RegisterCallBack=
 ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=Makefile
-ProjectManager.ToolChainLocation=Src
+ProjectManager.ToolChainLocation=Src/
 ProjectManager.UnderRoot=false
 ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,4-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
 RCC.ADCFreq_Value=50390625
-RCC.AHB12Freq_Value=150000000
-RCC.AHB4Freq_Value=150000000
-RCC.APB1Freq_Value=75000000
-RCC.APB2Freq_Value=75000000
-RCC.APB3Freq_Value=75000000
-RCC.APB4Freq_Value=75000000
-RCC.AXIClockFreq_Value=150000000
+RCC.AHB12Freq_Value=200000000
+RCC.AHB4Freq_Value=200000000
+RCC.APB1Freq_Value=100000000
+RCC.APB2Freq_Value=100000000
+RCC.APB3Freq_Value=100000000
+RCC.APB4Freq_Value=100000000
+RCC.AXIClockFreq_Value=200000000
 RCC.CECFreq_Value=32000
 RCC.CKPERFreq_Value=64000000
-RCC.CortexFreq_Value=150000000
-RCC.CpuClockFreq_Value=150000000
-RCC.D1CPREFreq_Value=150000000
+RCC.CortexFreq_Value=400000000
+RCC.CpuClockFreq_Value=400000000
+RCC.D1CPREFreq_Value=400000000
 RCC.D1PPRE=RCC_APB3_DIV2
 RCC.D2PPRE1=RCC_APB1_DIV2
 RCC.D2PPRE2=RCC_APB2_DIV2
 RCC.D3PPRE=RCC_APB4_DIV2
-RCC.DFSDMACLkFreq_Value=75000000
-RCC.DFSDMFreq_Value=75000000
-RCC.DIVM1=2
+RCC.DFSDMACLkFreq_Value=200000000
+RCC.DFSDMFreq_Value=100000000
+RCC.DIVM1=5
 RCC.DIVM3=25
-RCC.DIVN1=24
+RCC.DIVN1=160
 RCC.DIVN3=336
-RCC.DIVP1Freq_Value=150000000
+RCC.DIVP1Freq_Value=400000000
 RCC.DIVP2Freq_Value=50390625
 RCC.DIVP3Freq_Value=168000000
 RCC.DIVQ1=4
-RCC.DIVQ1Freq_Value=75000000
+RCC.DIVQ1Freq_Value=200000000
 RCC.DIVQ2Freq_Value=50390625
 RCC.DIVQ3=7
 RCC.DIVQ3Freq_Value=48000000
-RCC.DIVR1Freq_Value=150000000
+RCC.DIVR1=6
+RCC.DIVR1Freq_Value=133333333.33333333
 RCC.DIVR2Freq_Value=50390625
 RCC.DIVR3Freq_Value=168000000
 RCC.EnbaleCSS=true
-RCC.FDCANFreq_Value=75000000
-RCC.FMCFreq_Value=150000000
+RCC.FDCANFreq_Value=200000000
+RCC.FMCFreq_Value=200000000
 RCC.FamilyName=M
-RCC.HCLK3ClockFreq_Value=150000000
-RCC.HCLKFreq_Value=150000000
+RCC.HCLK3ClockFreq_Value=200000000
+RCC.HCLKFreq_Value=200000000
+RCC.HPRE=RCC_HCLK_DIV2
 RCC.HPREFreq_Value=64000000
-RCC.HRTIMFreq_Value=150000000
+RCC.HRTIMFreq_Value=200000000
 RCC.HSICalibrationValue=32
-RCC.I2C123Freq_Value=75000000
-RCC.I2C4Freq_Value=75000000
-RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPREFreq_Value,HRTIMFreq_Value,HSICalibrationValue,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
-RCC.LPTIM1Freq_Value=75000000
-RCC.LPTIM2Freq_Value=75000000
-RCC.LPTIM345Freq_Value=75000000
-RCC.LPUART1Freq_Value=75000000
+RCC.I2C123Freq_Value=100000000
+RCC.I2C4Freq_Value=100000000
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM3,DIVN1,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,EnbaleCSS,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HPREFreq_Value,HRTIMFreq_Value,HSICalibrationValue,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,PWR_Regulator_Voltage_Scale,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.LPTIM1Freq_Value=100000000
+RCC.LPTIM2Freq_Value=100000000
+RCC.LPTIM345Freq_Value=100000000
+RCC.LPUART1Freq_Value=100000000
 RCC.LTDCFreq_Value=168000000
 RCC.MCO1PinFreq_Value=64000000
-RCC.MCO2PinFreq_Value=150000000
+RCC.MCO2PinFreq_Value=400000000
 RCC.PLL2FRACN=0
 RCC.PLL3FRACN=0
 RCC.PLLFRACN=0
 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
 RCC.PWR_Regulator_Voltage_Scale=PWR_REGULATOR_VOLTAGE_SCALE1
-RCC.QSPIFreq_Value=150000000
+RCC.QSPIFreq_Value=200000000
 RCC.RNGFreq_Value=48000000
 RCC.RTCFreq_Value=32000
-RCC.SAI1Freq_Value=75000000
-RCC.SAI23Freq_Value=75000000
-RCC.SAI4AFreq_Value=75000000
-RCC.SAI4BFreq_Value=75000000
-RCC.SDMMCFreq_Value=75000000
-RCC.SPDIFRXFreq_Value=75000000
-RCC.SPI123Freq_Value=75000000
-RCC.SPI45Freq_Value=75000000
-RCC.SPI6Freq_Value=75000000
-RCC.SWPMI1Freq_Value=75000000
-RCC.SYSCLKFreq_VALUE=150000000
+RCC.SAI1Freq_Value=200000000
+RCC.SAI23Freq_Value=200000000
+RCC.SAI4AFreq_Value=200000000
+RCC.SAI4BFreq_Value=200000000
+RCC.SDMMCFreq_Value=200000000
+RCC.SPDIFRXFreq_Value=200000000
+RCC.SPI123Freq_Value=200000000
+RCC.SPI45Freq_Value=100000000
+RCC.SPI6Freq_Value=100000000
+RCC.SWPMI1Freq_Value=100000000
+RCC.SYSCLKFreq_VALUE=400000000
 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-RCC.Tim1OutputFreq_Value=150000000
-RCC.Tim2OutputFreq_Value=150000000
-RCC.TraceFreq_Value=150000000
-RCC.USART16Freq_Value=75000000
-RCC.USART234578Freq_Value=75000000
+RCC.Tim1OutputFreq_Value=200000000
+RCC.Tim2OutputFreq_Value=200000000
+RCC.TraceFreq_Value=133333333.33333333
+RCC.USART16Freq_Value=100000000
+RCC.USART234578Freq_Value=100000000
 RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3
 RCC.USBFreq_Value=48000000
-RCC.VCO1OutputFreq_Value=300000000
+RCC.VCO1OutputFreq_Value=800000000
 RCC.VCO2OutputFreq_Value=100781250
 RCC.VCO3OutputFreq_Value=336000000
-RCC.VCOInput1Freq_Value=12500000
+RCC.VCOInput1Freq_Value=5000000
 RCC.VCOInput2Freq_Value=781250
 RCC.VCOInput3Freq_Value=1000000
 SH.ADCx_INN1.0=ADC1_INN1

From 3fdd2a40b2103089e47609a05577fc84b786ec4f Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Fri, 2 Jun 2023 15:04:53 +0200
Subject: [PATCH 1899/2085] osal_none: make it possible to override the task
 delay function

---
 src/host/usbh.c      | 2 +-
 src/osal/osal_none.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 184bda23b..1418cfb79 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -256,7 +256,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
-void osal_task_delay(uint32_t msec)
+TU_ATTR_WEAK void osal_task_delay(uint32_t msec)
 {
   const uint32_t start = hcd_frame_number(_usbh_controller);
   while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}
diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h
index 5f407378e..76e77c25d 100644
--- a/src/osal/osal_none.h
+++ b/src/osal/osal_none.h
@@ -37,7 +37,7 @@
 
 #if CFG_TUH_ENABLED
 // currently only needed/available in host mode
-void osal_task_delay(uint32_t msec);
+TU_ATTR_WEAK void osal_task_delay(uint32_t msec);
 #endif
 
 //--------------------------------------------------------------------+

From efa8b4a9b81577047efb957eb191f707949ef188 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Tue, 18 Jul 2023 22:55:55 +0900
Subject: [PATCH 1900/2085] Change a variable to a target so that it works on
 windows command prompt

echo command of windows command prompt can't handle line breaks in a variable.
---
 examples/rules.mk | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/examples/rules.mk b/examples/rules.mk
index e50c0ec7d..44698b019 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -99,19 +99,16 @@ endif
 JLINK_IF ?= swd
 
 # Jlink script
-define jlink_script
-halt
-loadfile $^
-r
-go
-exit
-endef
-export jlink_script
+$(BUILD)/$(BOARD).jlink: $(BUILD)/$(PROJECT).hex
+	@echo halt > $@
+	@echo loadfile $^ >> $@
+	@echo r >> $@
+	@echo go >> $@
+	@echo exit >> $@
 
 # Flash using jlink
-flash-jlink: $(BUILD)/$(PROJECT).hex
-	@echo "$$jlink_script" > $(BUILD)/$(BOARD).jlink
-	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $(BUILD)/$(BOARD).jlink
+flash-jlink: $(BUILD)/$(BOARD).jlink
+	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $<
 
 # Flash STM32 MCU using stlink with STM32 Cube Programmer CLI
 flash-stlink: $(BUILD)/$(PROJECT).elf

From 3678a25baaeb6cd6f269d405903aeca23e93dca6 Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Tue, 18 Jul 2023 09:02:59 -0500
Subject: [PATCH 1901/2085] Fix build issues when building for RP2040 from
 pico-examples/pico-sdk.

* include_guard requires GLOBAL as family.cmake is included in multiple non child places
* the following recently added check is suprfluous (family_configure_host_example for rp2040 should do this already),
  and breaks if pico_pio_usb is not avaialble, so i have removed
   # Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
   if(FAMILY STREQUAL "rp2040")
      family_add_pico_pio_usb(${PROJECT})
   endif()
* added new familt_example_missing_dependency functino to print missing dependency warning, so
  pico-examples can override it to be less in your face, and also more contextual to pico-examples
---
 .../device/net_lwip_webserver/CMakeLists.txt  | 12 +++++------
 examples/host/bare_api/CMakeLists.txt         |  7 +------
 examples/host/cdc_msc_hid/CMakeLists.txt      |  5 -----
 examples/host/hid_controller/CMakeLists.txt   |  5 -----
 .../host/msc_file_explorer/CMakeLists.txt     |  5 -----
 hw/bsp/family_support.cmake                   | 20 ++++++++++++-------
 hw/bsp/rp2040/family.cmake                    |  2 +-
 7 files changed, 21 insertions(+), 35 deletions(-)

diff --git a/examples/device/net_lwip_webserver/CMakeLists.txt b/examples/device/net_lwip_webserver/CMakeLists.txt
index 1e34428fe..a16b8bd71 100644
--- a/examples/device/net_lwip_webserver/CMakeLists.txt
+++ b/examples/device/net_lwip_webserver/CMakeLists.txt
@@ -2,15 +2,15 @@ cmake_minimum_required(VERSION 3.17)
 
 include(${CMAKE_CURRENT_LIST_DIR}/../../../hw/bsp/family_support.cmake)
 
-set(LWIP ${TOP}/lib/lwip)
-if (NOT EXISTS ${LWIP}/src)
-  MESSAGE(WARNING "lib/lwip submodule not found, please run 'python tools/get_deps.py lib/lwip' to fetch it")
-  return()
-endif()
-
 # gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
 family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
 
+set(LWIP ${TOP}/lib/lwip)
+if (NOT EXISTS ${LWIP}/src)
+  family_example_missing_dependency(${PROJECT} "lib/lwip")
+  return()
+endif()
+
 project(${PROJECT} C CXX ASM)
 
 # Checks this example is valid for the family and initializes the project
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 95af48718..7049fe66b 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -24,9 +24,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example without RTOS.
 # See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT} noos)
-
-# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
-if(FAMILY STREQUAL "rp2040")
-  family_add_pico_pio_usb(${PROJECT})
-endif()
+family_configure_host_example(${PROJECT} noos)
\ No newline at end of file
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index 3fdc832ab..ad5751705 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -28,8 +28,3 @@ target_include_directories(${PROJECT} PUBLIC
 # Configure compilation flags and libraries for the example without RTOS.
 # See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT} noos)
-
-# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
-if(FAMILY STREQUAL "rp2040")
-  family_add_pico_pio_usb(${PROJECT})
-endif()
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index d1d901b53..3fb630aaa 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -26,8 +26,3 @@ target_include_directories(${PROJECT} PUBLIC
 # Configure compilation flags and libraries for the example without RTOS.
 # See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT} noos)
-
-# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
-if(FAMILY STREQUAL "rp2040")
-  family_add_pico_pio_usb(${PROJECT})
-endif()
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 99c797275..a35a7f0fb 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -38,8 +38,3 @@ target_include_directories(${PROJECT} PUBLIC
 # Configure compilation flags and libraries for the example without RTOS.
 # See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
 family_configure_host_example(${PROJECT} noos)
-
-# Add pico-pio-usb for rp2040 since user can choose to run on bit-banging host
-if(FAMILY STREQUAL "rp2040")
-  family_add_pico_pio_usb(${PROJECT})
-endif()
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index b2e61a824..9959784ae 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -1,4 +1,4 @@
-include_guard()
+include_guard(GLOBAL)
 
 include(CMakePrintHelpers)
 
@@ -36,12 +36,14 @@ if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
   message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
 endif()
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
+if (NOT TINYUSB_OPT_SKIP_CHECK_IPO_SUPPORTED)
+  # enable LTO if supported
+  include(CheckIPOSupported)
+  check_ipo_supported(RESULT IPO_SUPPORTED)
+  if (IPO_SUPPORTED)
+    set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
+  endif()
+endif()
 
 set(WARNING_FLAGS_GNU
   -Wall
@@ -278,6 +280,10 @@ function(family_configure_dual_usb_example TARGET RTOS)
   family_configure_example(${TARGET} ${RTOS})
 endfunction()
 
+function(family_example_missing_dependency TARGET DEPENDENCY)
+  message(WARNING "${DEPENDENCY} submodule needed by ${TARGET} not found, please run 'python tools/get_deps.py ${DEPENDENCY}' to fetch it")
+endfunction()
+
 #----------------------------------
 # RPI specific: refactor later
 #----------------------------------
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index b986b3ebb..8b8014e8a 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -1,5 +1,5 @@
 cmake_minimum_required(VERSION 3.13)
-include_guard()
+include_guard(GLOBAL)
 
 if (NOT BOARD)
 	message("BOARD not specified, defaulting to pico_sdk")

From 08a1892801088f2b3df74cc2bdaeeeadf9e8624b Mon Sep 17 00:00:00 2001
From: graham sanderson <graham.sanderson@raspberrypi.com>
Date: Tue, 18 Jul 2023 11:04:43 -0500
Subject: [PATCH 1902/2085] add is_compiler_supported_by_pico_pio_usb()

previosuly users of TinyUSB (e.g. pico-examples) would have to decide this for themselves. This function couples
the check closer with the actual version of Pico-PIO-USB used (since TinyUSB picks)
---
 hw/bsp/rp2040/family.cmake | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index b986b3ebb..17900dd7a 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -183,6 +183,15 @@ function(family_add_pico_pio_usb TARGET)
 	target_link_libraries(${TARGET} PUBLIC tinyusb_pico_pio_usb)
 endfunction()
 
+# since Pico-PIO_USB compiler support may lag, and change from version to version, add a function that pico-sdk/pico-examples
+# can check (if present) in case the user has updated their TinyUSB
+function(is_compiler_supported_by_pico_pio_usb OUTVAR)
+	if ((NOT CMAKE_C_COMPILER_ID STREQUAL "GNU"))
+		SET(${OUTVAR} 0 PARENT_SCOPE)
+	else()
+		set(${OUTVAR} 1 PARENT_SCOPE)
+	endif()
+endfunction()
 
 function(family_configure_host_example TARGET RTOS)
 	family_configure_target(${TARGET} ${RTOS})
@@ -191,8 +200,9 @@ function(family_configure_host_example TARGET RTOS)
 
 	# For rp2040 enable pico-pio-usb
 	if (TARGET tinyusb_pico_pio_usb)
-		# code does not compile with non GCC, or GCC 11.3+
-		if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND NOT CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 11.3)
+		# Pico-PIO-USB does not compile with all pico-sdk supported compilers, so check before enabling it
+		is_compiler_supported_by_pico_pio_usb(PICO_PIO_USB_COMPILER_SUPPORTED)
+		if (PICO_PIO_USB_COMPILER_SUPPORTED)
 			family_add_pico_pio_usb(${PROJECT})
 		endif()
 	endif()

From b1e345b6bc5c528751cf0126e0a50daa5733960b Mon Sep 17 00:00:00 2001
From: jferreir <jesus.ferreira@gmail.com>
Date: Thu, 20 Jul 2023 10:52:16 +0200
Subject: [PATCH 1903/2085] Add UART_DEV support

---
 hw/bsp/xmc4000/family.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c
index bf6684736..35bed0ba4 100644
--- a/hw/bsp/xmc4000/family.c
+++ b/hw/bsp/xmc4000/family.c
@@ -26,6 +26,7 @@
 
 #include "xmc_gpio.h"
 #include "xmc_scu.h"
+#include "xmc_uart.h"
 
 #include "bsp/board.h"
 #include "board.h"
@@ -45,17 +46,31 @@ void board_init(void)
   SystemCoreClockUpdate();
 
   // LED
-  XMC_GPIO_CONFIG_t led_cfg;
+  XMC_GPIO_CONFIG_t led_cfg = {0};
   led_cfg.mode = XMC_GPIO_MODE_OUTPUT_PUSH_PULL;
   led_cfg.output_level = XMC_GPIO_OUTPUT_LEVEL_HIGH;
   led_cfg.output_strength = XMC_GPIO_OUTPUT_STRENGTH_MEDIUM;
   XMC_GPIO_Init(LED_PIN, &led_cfg);
 
   // Button
-  XMC_GPIO_CONFIG_t button_cfg;
+  XMC_GPIO_CONFIG_t button_cfg = {0};
   button_cfg.mode = XMC_GPIO_MODE_INPUT_TRISTATE;
   XMC_GPIO_Init(BUTTON_PIN, &button_cfg);
 
+#ifdef UART_DEV
+  XMC_UART_CH_CONFIG_t uart_cfg = {0};
+  uart_cfg.baudrate = CFG_BOARD_UART_BAUDRATE;
+  uart_cfg.data_bits = 8;
+  uart_cfg.stop_bits = 1;
+  XMC_UART_CH_Init(UART_DEV, &uart_cfg);
+
+  XMC_GPIO_SetMode(UART_RX_PIN, XMC_GPIO_MODE_INPUT_PULL_UP);
+  XMC_UART_CH_SetInputSource(UART_DEV, XMC_UART_CH_INPUT_RXD, UART_RX_INPUT);
+
+  XMC_UART_CH_Start(UART_DEV);
+  XMC_GPIO_SetMode(UART_TX_PIN, (XMC_GPIO_MODE_t)(XMC_GPIO_MODE_OUTPUT_PUSH_PULL | UART_TX_PIN_AF));
+#endif
+
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
@@ -69,6 +84,7 @@ void board_init(void)
 #endif
 
   // USB Power Enable
+  XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0);
   XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0);
   XMC_SCU_POWER_EnableUsb();
 }
@@ -93,7 +109,7 @@ int board_uart_read(uint8_t* buf, int len)
 {
 #ifdef UART_DEV
   for(int i=0;i<len;i++) {
-    buf[i] = uart_getc(uart_inst);
+    buf[i] = XMC_UART_CH_GetReceivedData(UART_DEV);
   }
   return len;
 #else
@@ -107,7 +123,7 @@ int board_uart_write(void const * buf, int len)
 #ifdef UART_DEV
   char const* bufch = (char const*) buf;
   for(int i=0;i<len;i++) {
-    uart_putc(uart_inst, bufch[i]);
+    XMC_UART_CH_Transmit(UART_DEV, bufch[i]);
   }
   return len;
 #else

From 59778664c900254a576edb105ecca9104adcb5b7 Mon Sep 17 00:00:00 2001
From: jferreir <jesus.ferreira@gmail.com>
Date: Thu, 20 Jul 2023 10:53:29 +0200
Subject: [PATCH 1904/2085] Add UART_DEV support

---
 hw/bsp/xmc4000/family.mk | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk
index 35c3a58b7..6c460c93b 100644
--- a/hw/bsp/xmc4000/family.mk
+++ b/hw/bsp/xmc4000/family.mk
@@ -20,8 +20,11 @@ SRC_C += \
 	src/portable/synopsys/dwc2/dcd_dwc2.c \
 	$(MCU_DIR)/Newlib/syscalls.c \
 	$(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/system_$(MCU_VARIANT).c \
+	$(MCU_DIR)/XMCLib/src/xmc_gpio.c \
 	$(MCU_DIR)/XMCLib/src/xmc4_gpio.c \
-	$(MCU_DIR)/XMCLib/src/xmc4_scu.c
+	$(MCU_DIR)/XMCLib/src/xmc4_scu.c \
+	$(MCU_DIR)/XMCLib/src/xmc_usic.c \
+	$(MCU_DIR)/XMCLib/src/xmc_uart.c
 
 SRC_S += $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/startup_$(MCU_VARIANT).S
 

From 2772581c284fae8073b6717f51d819a7e4bc653d Mon Sep 17 00:00:00 2001
From: jferreir <jesus.ferreira@gmail.com>
Date: Thu, 20 Jul 2023 10:53:59 +0200
Subject: [PATCH 1905/2085] Add support for XMC4700_RELAX kit

---
 hw/bsp/xmc4000/boards/xmc4700_relax/board.h  | 81 ++++++++++++++++++++
 hw/bsp/xmc4000/boards/xmc4700_relax/board.mk | 12 +++
 2 files changed, 93 insertions(+)
 create mode 100644 hw/bsp/xmc4000/boards/xmc4700_relax/board.h
 create mode 100644 hw/bsp/xmc4000/boards/xmc4700_relax/board.mk

diff --git a/hw/bsp/xmc4000/boards/xmc4700_relax/board.h b/hw/bsp/xmc4000/boards/xmc4700_relax/board.h
new file mode 100644
index 000000000..aa12fde3b
--- /dev/null
+++ b/hw/bsp/xmc4000/boards/xmc4700_relax/board.h
@@ -0,0 +1,81 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define LED_PIN               P5_9
+#define LED_STATE_ON          1
+
+#define BUTTON_PIN            P15_13
+#define BUTTON_STATE_ACTIVE   0
+
+#define UART_DEV              XMC_UART0_CH0
+#define UART_TX_PIN           P1_5
+#define UART_TX_PIN_AF        P1_5_AF_U0C0_DOUT0
+#define UART_RX_PIN           P1_4
+#define UART_RX_INPUT         USIC0_C0_DX0_P1_4
+
+static inline void board_clock_init(void)
+{
+  /* Clock configuration */
+  /* fPLL = 144MHz */
+  /* fSYS = 144MHz */
+  /* fUSB = 48MHz */
+  const XMC_SCU_CLOCK_CONFIG_t clock_config =
+  {
+    .syspll_config.p_div  = 2,
+    .syspll_config.n_div  = 48,
+    .syspll_config.k_div  = 1,
+    .syspll_config.mode   = XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL,
+    .syspll_config.clksrc = XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP,
+    .enable_oschp         = true,
+    .calibration_mode     = XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY,
+    .fsys_clksrc          = XMC_SCU_CLOCK_SYSCLKSRC_PLL,
+    .fsys_clkdiv          = 2,
+    .fcpu_clkdiv          = 1,
+    .fccu_clkdiv          = 1,
+    .fperipheral_clkdiv   = 1
+  };
+
+  /* Setup settings for USB clock */
+  XMC_SCU_CLOCK_Init(&clock_config);
+
+  XMC_SCU_CLOCK_SetUsbClockDivider(6);
+  XMC_SCU_CLOCK_SetUsbClockSource(XMC_SCU_CLOCK_USBCLKSRC_SYSPLL);
+  XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_USB);
+}
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/xmc4000/boards/xmc4700_relax/board.mk b/hw/bsp/xmc4000/boards/xmc4700_relax/board.mk
new file mode 100644
index 000000000..28fadf8f4
--- /dev/null
+++ b/hw/bsp/xmc4000/boards/xmc4700_relax/board.mk
@@ -0,0 +1,12 @@
+MCU_VARIANT = XMC4700
+CFLAGS += \
+  -DXMC4700_F144x2048 \
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-stringop-overread
+
+LD_FILE = $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4700x2048.ld
+
+JLINK_DEVICE = XMC4700-2048
+
+flash: flash-jlink

From 77495cf119c89c3091e7ab05773ebce19988da86 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 20 Jul 2023 17:06:57 +0700
Subject: [PATCH 1906/2085] improve logging, allow easier to turn off usbd,
 driver logging

can be useful when focusing on let's say usbh
---
 src/class/msc/msc_device.c | 43 ++++++++++--------
 src/device/usbd.c          | 93 ++++++++++++++++++--------------------
 src/device/usbd_control.c  |  9 ++--
 src/device/usbd_pvt.h      |  9 +++-
 src/host/usbh.c            | 34 +++++++-------
 5 files changed, 97 insertions(+), 91 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 159a11259..a409c4e27 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -34,13 +34,16 @@
 
 #include "msc_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_MSC_LOG_LEVEL
+  #define CFG_TUD_MSC_LOG_LEVEL   2
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_MSC_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-
-// Can be selectively disabled to reduce logging when troubleshooting other driver
-#define MSC_DEBUG   2
-
 enum
 {
   MSC_STAGE_CMD  = 0,
@@ -164,7 +167,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
   {
     if ( block_count )
     {
-      TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n");
+      TU_LOG_DRV("  SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
     }else
     {
@@ -174,22 +177,22 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
   {
     if ( SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir) )
     {
-      TU_LOG(MSC_DEBUG, "  SCSI case 10 (Ho <> Di)\r\n");
+      TU_LOG_DRV("  SCSI case 10 (Ho <> Di)\r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
     }
     else if ( SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir) )
     {
-      TU_LOG(MSC_DEBUG, "  SCSI case 8 (Hi <> Do)\r\n");
+      TU_LOG_DRV("  SCSI case 8 (Hi <> Do)\r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
     }
     else if ( 0 == block_count )
     {
-      TU_LOG(MSC_DEBUG, "  SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n");
+      TU_LOG_DRV("  SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n");
       status =  MSC_CSW_STATUS_FAILED;
     }
     else if ( cbw->total_bytes / block_count == 0 )
     {
-      TU_LOG(MSC_DEBUG, " Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n");
+      TU_LOG_DRV(" Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
     }
   }
@@ -352,7 +355,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
   switch ( request->bRequest )
   {
     case MSC_REQ_RESET:
-      TU_LOG(MSC_DEBUG, "  MSC BOT Reset\r\n");
+      TU_LOG_DRV("  MSC BOT Reset\r\n");
       TU_VERIFY(request->wValue == 0 && request->wLength == 0);
 
       // driver state reset
@@ -363,7 +366,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
 
     case MSC_REQ_GET_MAX_LUN:
     {
-      TU_LOG(MSC_DEBUG, "  MSC Get Max Lun\r\n");
+      TU_LOG_DRV("  MSC Get Max Lun\r\n");
       TU_VERIFY(request->wValue == 0 && request->wLength == 1);
 
       uint8_t maxlun = 1;
@@ -400,7 +403,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
 
       if ( !(xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE) )
       {
-        TU_LOG(MSC_DEBUG, "  SCSI CBW is not valid\r\n");
+        TU_LOG_DRV("  SCSI CBW is not valid\r\n");
 
         // BOT 6.6.1 If CBW is not valid stall both endpoints until reset recovery
         p_msc->stage = MSC_STAGE_NEED_RESET;
@@ -412,7 +415,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         return false;
       }
 
-      TU_LOG(MSC_DEBUG, "  SCSI Command [Lun%u]: %s\r\n", p_cbw->lun, tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
+      TU_LOG_DRV("  SCSI Command [Lun%u]: %s\r\n", p_cbw->lun, tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
       //TU_LOG_MEM(MSC_DEBUG, p_cbw, xferred_bytes, 2);
 
       p_csw->signature    = MSC_CSW_SIGNATURE;
@@ -457,7 +460,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         {
           if (p_cbw->total_bytes > sizeof(_mscd_buf))
           {
-            TU_LOG(MSC_DEBUG, "  SCSI reject non READ10/WRITE10 with large data\r\n");
+            TU_LOG_DRV("  SCSI reject non READ10/WRITE10 with large data\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
           }else
           {
@@ -479,7 +482,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           if ( resplen < 0 )
           {
             // unsupported command
-            TU_LOG(MSC_DEBUG, "  SCSI unsupported or failed command\r\n");
+            TU_LOG_DRV("  SCSI unsupported or failed command\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
           }
           else if (resplen == 0)
@@ -514,7 +517,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     break;
 
     case MSC_STAGE_DATA:
-      TU_LOG(MSC_DEBUG, "  SCSI Data [Lun%u]\r\n", p_cbw->lun);
+      TU_LOG_DRV("  SCSI Data [Lun%u]\r\n", p_cbw->lun);
       //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2);
 
       if (SCSI_CMD_READ_10 == p_cbw->command[0])
@@ -546,7 +549,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           if ( cb_result < 0 )
           {
             // unsupported command
-            TU_LOG(MSC_DEBUG, "  SCSI unsupported command\r\n");
+            TU_LOG_DRV("  SCSI unsupported command\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
           }else
           {
@@ -575,7 +578,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       // Wait for the Status phase to complete
       if( (ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t)) )
       {
-        TU_LOG(MSC_DEBUG, "  SCSI Status [Lun%u] = %u\r\n", p_cbw->lun, p_csw->status);
+        TU_LOG_DRV("  SCSI Status [Lun%u] = %u\r\n", p_cbw->lun, p_csw->status);
         // TU_LOG_MEM(MSC_DEBUG, p_csw, xferred_bytes, 2);
 
         // Invoke complete callback if defined
@@ -845,7 +848,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   if ( nbytes < 0 )
   {
     // negative means error -> endpoint is stalled & status in CSW set to failed
-    TU_LOG(MSC_DEBUG, "  tud_msc_read10_cb() return -1\r\n");
+    TU_LOG_DRV("  tud_msc_read10_cb() return -1\r\n");
 
     // set sense
     set_sense_medium_not_present(p_cbw->lun);
@@ -907,7 +910,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
   if ( nbytes < 0 )
   {
     // negative means error -> failed this scsi op
-    TU_LOG(MSC_DEBUG, "  tud_msc_write10_cb() return -1\r\n");
+    TU_LOG_DRV("  tud_msc_write10_cb() return -1\r\n");
 
     // update actual byte before failed
     p_msc->xferred_len += xferred_bytes;
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 44c2530ce..9429cf664 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -43,9 +43,6 @@
   #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
 
-// Debug level of USBD
-#define USBD_DBG   2
-
 //--------------------------------------------------------------------+
 // Device Data
 //--------------------------------------------------------------------+
@@ -81,7 +78,7 @@ tu_static usbd_device_t _usbd_dev;
 //--------------------------------------------------------------------+
 // Class Driver
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   #define DRIVER_NAME(_name)    .name = _name,
 #else
   #define DRIVER_NAME(_name)
@@ -308,7 +305,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event,
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
 tu_static char const* const _usbd_event_str[DCD_EVENT_COUNT] =
 {
   "Invalid"        ,
@@ -330,7 +327,7 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
     usbd_class_driver_t const * driver = get_driver(i);
     if ( driver && driver->control_xfer_cb == callback )
     {
-      TU_LOG(USBD_DBG, "  %s control complete\r\n", driver->name);
+      TU_LOG_USBD("  %s control complete\r\n", driver->name);
       return;
     }
   }
@@ -396,10 +393,10 @@ bool tud_init (uint8_t rhport)
   // skip if already initialized
   if ( tud_inited() ) return true;
 
-  TU_LOG(USBD_DBG, "USBD init on controller %u\r\n", rhport);
-  TU_LOG_INT(USBD_DBG, sizeof(usbd_device_t));
-  TU_LOG_INT(USBD_DBG, sizeof(tu_fifo_t));
-  TU_LOG_INT(USBD_DBG, sizeof(tu_edpt_stream_t));
+  TU_LOG_USBD("USBD init on controller %u\r\n", rhport);
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t));
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t));
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_edpt_stream_t));
 
   tu_varclr(&_usbd_dev);
 
@@ -424,7 +421,7 @@ bool tud_init (uint8_t rhport)
   {
     usbd_class_driver_t const * driver = get_driver(i);
     TU_ASSERT(driver);
-    TU_LOG(USBD_DBG, "%s init\r\n", driver->name);
+    TU_LOG_USBD("%s init\r\n", driver->name);
     driver->init();
   }
 
@@ -496,21 +493,21 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
     dcd_event_t event;
     if ( !osal_queue_receive(_usbd_q, &event, timeout_ms) ) return;
 
-#if CFG_TUSB_DEBUG >= 2
-    if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG(USBD_DBG, "\r\n"); // extra line for setup
-    TU_LOG(USBD_DBG, "USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED");
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
+    if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG_USBD("\r\n"); // extra line for setup
+    TU_LOG_USBD("USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED");
 #endif
 
     switch ( event.event_id )
     {
       case DCD_EVENT_BUS_RESET:
-        TU_LOG(USBD_DBG, ": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]);
+        TU_LOG_USBD(": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]);
         usbd_reset(event.rhport);
         _usbd_dev.speed = event.bus_reset.speed;
       break;
 
       case DCD_EVENT_UNPLUGGED:
-        TU_LOG(USBD_DBG, "\r\n");
+        TU_LOG_USBD("\r\n");
         usbd_reset(event.rhport);
 
         // invoke callback
@@ -518,8 +515,8 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
       break;
 
       case DCD_EVENT_SETUP_RECEIVED:
-        TU_LOG_PTR(USBD_DBG, &event.setup_received);
-        TU_LOG(USBD_DBG, "\r\n");
+        TU_LOG_PTR(CFG_TUD_LOG_LEVEL, &event.setup_received);
+        TU_LOG_USBD("\r\n");
 
         // Mark as connected after receiving 1st setup packet.
         // But it is easier to set it every time instead of wasting time to check then set
@@ -534,7 +531,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         // Process control request
         if ( !process_control_request(event.rhport, &event.setup_received) )
         {
-          TU_LOG(USBD_DBG, "  Stall EP0\r\n");
+          TU_LOG_USBD("  Stall EP0\r\n");
           // Failed -> stall both control endpoint IN and OUT
           dcd_edpt_stall(event.rhport, 0);
           dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK);
@@ -548,7 +545,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         uint8_t const epnum   = tu_edpt_number(ep_addr);
         uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
-        TU_LOG(USBD_DBG, "on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
+        TU_LOG_USBD("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
 
         _usbd_dev.ep_status[epnum][ep_dir].busy = 0;
         _usbd_dev.ep_status[epnum][ep_dir].claimed = 0;
@@ -563,7 +560,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
           usbd_class_driver_t const * driver = get_driver( _usbd_dev.ep2drv[epnum][ep_dir] );
           TU_ASSERT(driver, );
 
-          TU_LOG(USBD_DBG, "  %s xfer callback\r\n", driver->name);
+          TU_LOG_USBD("  %s xfer callback\r\n", driver->name);
           driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
         }
       }
@@ -575,27 +572,27 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected
         if ( _usbd_dev.connected )
         {
-          TU_LOG(USBD_DBG, ": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
+          TU_LOG_USBD(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
           if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
         }else
         {
-          TU_LOG(USBD_DBG, " Skipped\r\n");
+          TU_LOG_USBD(" Skipped\r\n");
         }
       break;
 
       case DCD_EVENT_RESUME:
         if ( _usbd_dev.connected )
         {
-          TU_LOG(USBD_DBG, "\r\n");
+          TU_LOG_USBD("\r\n");
           if (tud_resume_cb) tud_resume_cb();
         }else
         {
-          TU_LOG(USBD_DBG, " Skipped\r\n");
+          TU_LOG_USBD(" Skipped\r\n");
         }
       break;
 
       case USBD_EVENT_FUNC_CALL:
-        TU_LOG(USBD_DBG, "\r\n");
+        TU_LOG_USBD("\r\n");
         if ( event.func_call.func ) event.func_call.func(event.func_call.param);
       break;
 
@@ -620,7 +617,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
 static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request)
 {
   usbd_control_set_complete_callback(driver->control_xfer_cb);
-  TU_LOG(USBD_DBG, "  %s control request\r\n", driver->name);
+  TU_LOG_USBD("  %s control request\r\n", driver->name);
   return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request);
 }
 
@@ -641,11 +638,11 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
     return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request);
   }
 
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME)
   {
-    TU_LOG(USBD_DBG, "  %s", tu_str_std_request[p_request->bRequest]);
-    if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG(USBD_DBG, "\r\n");
+    TU_LOG_USBD("  %s", tu_str_std_request[p_request->bRequest]);
+    if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG_USBD("\r\n");
   }
 #endif
 
@@ -701,7 +698,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
             if ( _usbd_dev.cfg_num )
             {
               // already configured: need to clear all endpoints and driver first
-              TU_LOG(USBD_DBG, "  Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num);
+              TU_LOG_USBD("  Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num);
 
               // close all non-control endpoints, cancel all pending transfers if any
               dcd_edpt_close_all(rhport);
@@ -730,7 +727,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           // Only support remote wakeup for device feature
           TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
 
-          TU_LOG(USBD_DBG, "    Enable Remote Wakeup\r\n");
+          TU_LOG_USBD("    Enable Remote Wakeup\r\n");
 
           // Host may enable remote wake up before suspending especially HID device
           _usbd_dev.remote_wakeup_en = true;
@@ -741,7 +738,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           // Only support remote wakeup for device feature
           TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
 
-          TU_LOG(USBD_DBG, "    Disable Remote Wakeup\r\n");
+          TU_LOG_USBD("    Disable Remote Wakeup\r\n");
 
           // Host may disable remote wake up after resuming
           _usbd_dev.remote_wakeup_en = false;
@@ -924,7 +921,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
       if ( (sizeof(tusb_desc_interface_t) <= drv_len)  && (drv_len <= remaining_len) )
       {
         // Open successfully
-        TU_LOG(USBD_DBG, "  %s opened\r\n", driver->name);
+        TU_LOG_USBD("  %s opened\r\n", driver->name);
 
         // Some drivers use 2 or more interfaces but may not have IAD e.g MIDI (always) or
         // BTH (even CDC) with class in device descriptor (single interface)
@@ -983,7 +980,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
   {
     case TUSB_DESC_DEVICE:
     {
-      TU_LOG(USBD_DBG, " Device\r\n");
+      TU_LOG_USBD(" Device\r\n");
 
       void* desc_device = (void*) (uintptr_t) tud_descriptor_device_cb();
 
@@ -1007,7 +1004,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
     case TUSB_DESC_BOS:
     {
-      TU_LOG(USBD_DBG, " BOS\r\n");
+      TU_LOG_USBD(" BOS\r\n");
 
       // requested by host if USB > 2.0 ( i.e 2.1 or 3.x )
       if (!tud_descriptor_bos_cb) return false;
@@ -1029,12 +1026,12 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
       if ( desc_type == TUSB_DESC_CONFIGURATION )
       {
-        TU_LOG(USBD_DBG, " Configuration[%u]\r\n", desc_index);
+        TU_LOG_USBD(" Configuration[%u]\r\n", desc_index);
         desc_config = (uintptr_t) tud_descriptor_configuration_cb(desc_index);
       }else
       {
         // Host only request this after getting Device Qualifier descriptor
-        TU_LOG(USBD_DBG, " Other Speed Configuration\r\n");
+        TU_LOG_USBD(" Other Speed Configuration\r\n");
         TU_VERIFY( tud_descriptor_other_speed_configuration_cb );
         desc_config = (uintptr_t) tud_descriptor_other_speed_configuration_cb(desc_index);
       }
@@ -1050,7 +1047,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
     case TUSB_DESC_STRING:
     {
-      TU_LOG(USBD_DBG, " String[%u]\r\n", desc_index);
+      TU_LOG_USBD(" String[%u]\r\n", desc_index);
 
       // String Descriptor always uses the desc set from user
       uint8_t const* desc_str = (uint8_t const*) tud_descriptor_string_cb(desc_index, tu_le16toh(p_request->wIndex));
@@ -1063,7 +1060,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
     case TUSB_DESC_DEVICE_QUALIFIER:
     {
-      TU_LOG(USBD_DBG, " Device Qualifier\r\n");
+      TU_LOG_USBD(" Device Qualifier\r\n");
 
       TU_VERIFY( tud_descriptor_device_qualifier_cb );
 
@@ -1248,7 +1245,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   // TODO skip ready() check for now since enumeration also use this API
   // TU_VERIFY(tud_ready());
 
-  TU_LOG(USBD_DBG, "  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
+  TU_LOG_USBD("  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
@@ -1265,7 +1262,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     // DCD error, mark endpoint as ready to allow next transfer
     _usbd_dev.ep_status[epnum][dir].busy = 0;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
-    TU_LOG(USBD_DBG, "FAILED\r\n");
+    TU_LOG_USBD("FAILED\r\n");
     TU_BREAKPOINT();
     return false;
   }
@@ -1282,7 +1279,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  TU_LOG(USBD_DBG, "  Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes);
+  TU_LOG_USBD("  Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
@@ -1293,14 +1290,14 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 
   if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes))
   {
-    TU_LOG(USBD_DBG, "OK\r\n");
+    TU_LOG_USBD("OK\r\n");
     return true;
   }else
   {
     // DCD error, mark endpoint as ready to allow next transfer
     _usbd_dev.ep_status[epnum][dir].busy = 0;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
-    TU_LOG(USBD_DBG, "failed\r\n");
+    TU_LOG_USBD("failed\r\n");
     TU_BREAKPOINT();
     return false;
   }
@@ -1326,7 +1323,7 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   // only stalled if currently cleared
   if ( !_usbd_dev.ep_status[epnum][dir].stalled )
   {
-    TU_LOG(USBD_DBG, "    Stall EP %02X\r\n", ep_addr);
+    TU_LOG_USBD("    Stall EP %02X\r\n", ep_addr);
     dcd_edpt_stall(rhport, ep_addr);
     _usbd_dev.ep_status[epnum][dir].stalled = 1;
     _usbd_dev.ep_status[epnum][dir].busy = 1;
@@ -1343,7 +1340,7 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   // only clear if currently stalled
   if ( _usbd_dev.ep_status[epnum][dir].stalled )
   {
-    TU_LOG(USBD_DBG, "    Clear Stall EP %02X\r\n", ep_addr);
+    TU_LOG_USBD("    Clear Stall EP %02X\r\n", ep_addr);
     dcd_edpt_clear_stall(rhport, ep_addr);
     _usbd_dev.ep_status[epnum][dir].stalled = 0;
     _usbd_dev.ep_status[epnum][dir].busy = 0;
@@ -1371,7 +1368,7 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   rhport = _usbd_rhport;
 
   TU_ASSERT(dcd_edpt_close, /**/);
-  TU_LOG(USBD_DBG, "  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
+  TU_LOG_USBD("  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 2afe967b5..c580e6ecf 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -32,10 +32,7 @@
 #include "tusb.h"
 #include "device/usbd_pvt.h"
 
-// Debug level of USBD Control
-#define USBD_CONTROL_DEBUG   2
-
-#if CFG_TUSB_DEBUG >= USBD_CONTROL_DEBUG
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
 extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
 #endif
 
@@ -191,7 +188,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
   {
     TU_VERIFY(_ctrl_xfer.buffer);
     memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes);
-    TU_LOG_MEM(USBD_CONTROL_DEBUG, _usbd_ctrl_buf, xferred_bytes, 2);
+    TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2);
   }
 
   _ctrl_xfer.total_xferred += (uint16_t) xferred_bytes;
@@ -208,7 +205,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
     // callback can still stall control in status phase e.g out data does not make sense
     if ( _ctrl_xfer.complete_cb )
     {
-      #if CFG_TUSB_DEBUG >= USBD_CONTROL_DEBUG
+      #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
       usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb);
       #endif
 
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 8393d3469..940b2858b 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -33,13 +33,20 @@
  extern "C" {
 #endif
 
+// Level where CFG_TUSB_DEBUG must be at least for USBD is logged
+#ifndef CFG_TUD_LOG_LEVEL
+#define CFG_TUD_LOG_LEVEL   2
+#endif
+
+#define TU_LOG_USBD(...)   TU_LOG(CFG_TUD_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // Class Driver API
 //--------------------------------------------------------------------+
 
 typedef struct
 {
-  #if CFG_TUSB_DEBUG >= 2
+  #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   char const* name;
   #endif
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 184bda23b..58129c16e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -38,17 +38,19 @@
 //--------------------------------------------------------------------+
 
 #ifndef CFG_TUH_TASK_QUEUE_SZ
-#define CFG_TUH_TASK_QUEUE_SZ   16
+  #define CFG_TUH_TASK_QUEUE_SZ   16
 #endif
 
 #ifndef CFG_TUH_INTERFACE_MAX
-#define CFG_TUH_INTERFACE_MAX   8
+  #define CFG_TUH_INTERFACE_MAX   8
 #endif
 
-// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
-#define USBH_DEBUG   2
+// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
+#ifndef CFG_TUH_LOG_LEVEL
+  #define CFG_TUH_LOG_LEVEL   2
+#endif
 
-#define TU_LOG_USBH(...)   TU_LOG(USBH_DEBUG, __VA_ARGS__)
+#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
 // USBH-HCD common data structure
@@ -322,12 +324,12 @@ bool tuh_init(uint8_t controller_id)
   if ( tuh_inited() ) return true;
 
   TU_LOG_USBH("USBH init on controller %u\r\n", controller_id);
-  TU_LOG_INT(USBH_DEBUG, sizeof(usbh_device_t));
-  TU_LOG_INT(USBH_DEBUG, sizeof(hcd_event_t));
-  TU_LOG_INT(USBH_DEBUG, sizeof(_ctrl_xfer));
-  TU_LOG_INT(USBH_DEBUG, sizeof(tuh_xfer_t));
-  TU_LOG_INT(USBH_DEBUG, sizeof(tu_fifo_t));
-  TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(usbh_device_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(hcd_event_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(_ctrl_xfer));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tuh_xfer_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_fifo_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_edpt_stream_t));
 
   // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -565,7 +567,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
   TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr,
               (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
                   tu_str_std_request[xfer->setup->bRequest] : "Class Request");
-  TU_LOG_PTR(USBH_DEBUG, xfer->setup);
+  TU_LOG_PTR(CFG_TUH_LOG_LEVEL, xfer->setup);
   TU_LOG_USBH("\r\n");
 
   if (xfer->complete_cb)
@@ -671,7 +673,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
         if (request->wLength)
         {
           TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr);
-          TU_LOG_MEM(USBH_DEBUG, _ctrl_xfer.buffer, xferred_bytes, 2);
+          TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2);
         }
 
         _ctrl_xfer.actual_len = (uint16_t) xferred_bytes;
@@ -1186,7 +1188,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
       TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
 
       if (is_hub_addr(daddr)) {
-        TU_LOG(USBH_DEBUG, "  is a HUB device %u\r\n", daddr);
+        TU_LOG(CFG_TUH_LOG_LEVEL, "  is a HUB device %u\r\n", daddr);
 
         // Submit removed event If the device itself is a hub (un-rolled recursive)
         // TODO a better to unroll recursrive is using array of removing_hubs and mark it here
@@ -1657,7 +1659,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
 
       if( drv_id >= USBH_CLASS_DRIVER_COUNT )
       {
-        TU_LOG(USBH_DEBUG, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+        TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
                desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
       }
     }
@@ -1695,7 +1697,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
 
     if (is_hub_addr(dev_addr))
     {
-      TU_LOG(USBH_DEBUG, "HUB address = %u is mounted\r\n", dev_addr);
+      TU_LOG(CFG_TUH_LOG_LEVEL, "HUB address = %u is mounted\r\n", dev_addr);
     }else
     {
       // Invoke callback if available

From 16ad918d96b2bd01189906d64d0871f0ea952833 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 20 Jul 2023 17:37:06 +0700
Subject: [PATCH 1907/2085] prefer application callback over built-in driver

---
 src/host/usbh.c | 56 ++++++++++++++++++++++---------------------------
 1 file changed, 25 insertions(+), 31 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 58129c16e..ecc672198 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -452,39 +452,28 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
         TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len,
                     tu_str_xfer_result[event.xfer_complete.result]);
 
-        if (event.dev_addr == 0)
-        {
+        if (event.dev_addr == 0) {
           // device 0 only has control endpoint
           TU_ASSERT(epnum == 0, );
           usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
-        }
-        else
-        {
+        } else {
           usbh_device_t* dev = get_device(event.dev_addr);
           TU_VERIFY(dev && dev->connected, );
 
           dev->ep_status[epnum][ep_dir].busy    = 0;
           dev->ep_status[epnum][ep_dir].claimed = 0;
 
-          if ( 0 == epnum )
-          {
-            usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
-          }else
-          {
-            uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
-            if(drv_id < USBH_CLASS_DRIVER_COUNT)
-            {
-              TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
-              usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
-            }
-            else
-            {
-#if CFG_TUH_API_EDPT_XFER
-              tuh_xfer_cb_t complete_cb = dev->ep_callback[epnum][ep_dir].complete_cb;
-              if ( complete_cb )
-              {
-                tuh_xfer_t xfer =
-                {
+          if ( 0 == epnum ) {
+            usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
+                                 event.xfer_complete.len);
+          }else {
+            // Prefer application callback over built-in one if available. This occurs when tuh_edpt_xfer() is used
+            // with enabled driver e.g HID endpoint
+            #if CFG_TUH_API_EDPT_XFER
+            tuh_xfer_cb_t const complete_cb = dev->ep_callback[epnum][ep_dir].complete_cb;
+            if ( complete_cb ) {
+              // re-construct xfer info
+              tuh_xfer_t xfer = {
                   .daddr       = event.dev_addr,
                   .ep_addr     = ep_addr,
                   .result      = event.xfer_complete.result,
@@ -493,16 +482,21 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
                   .buffer      = NULL, // not available
                   .complete_cb = complete_cb,
                   .user_data   = dev->ep_callback[epnum][ep_dir].user_data
-                };
+              };
 
-                complete_cb(&xfer);
-              }else
-#endif
-              {
+              complete_cb(&xfer);
+            }else
+            #endif
+            {
+              uint8_t const drv_id = dev->ep2drv[epnum][ep_dir];
+              if ( drv_id < USBH_CLASS_DRIVER_COUNT ) {
+                TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
+                usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
+                                                   event.xfer_complete.len);
+              } else {
                 // no driver/callback responsible for this transfer
-                TU_ASSERT(false, );
+                TU_ASSERT(false,);
               }
-
             }
           }
         }

From eae8678d67aa0add8970da86a0228578f49e9836 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 20 Jul 2023 17:06:57 +0700
Subject: [PATCH 1908/2085] improve logging, allow easier to turn off usbd,
 driver logging

can be useful when focusing on let's say usbh
---
 src/class/msc/msc_device.c | 43 ++++++++++--------
 src/device/usbd.c          | 93 ++++++++++++++++++--------------------
 src/device/usbd_control.c  |  9 ++--
 src/device/usbd_pvt.h      |  9 +++-
 src/host/usbh.c            | 34 +++++++-------
 5 files changed, 97 insertions(+), 91 deletions(-)

diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index 159a11259..a409c4e27 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -34,13 +34,16 @@
 
 #include "msc_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_MSC_LOG_LEVEL
+  #define CFG_TUD_MSC_LOG_LEVEL   2
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_MSC_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-
-// Can be selectively disabled to reduce logging when troubleshooting other driver
-#define MSC_DEBUG   2
-
 enum
 {
   MSC_STAGE_CMD  = 0,
@@ -164,7 +167,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
   {
     if ( block_count )
     {
-      TU_LOG(MSC_DEBUG, "  SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n");
+      TU_LOG_DRV("  SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
     }else
     {
@@ -174,22 +177,22 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw)
   {
     if ( SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir) )
     {
-      TU_LOG(MSC_DEBUG, "  SCSI case 10 (Ho <> Di)\r\n");
+      TU_LOG_DRV("  SCSI case 10 (Ho <> Di)\r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
     }
     else if ( SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir) )
     {
-      TU_LOG(MSC_DEBUG, "  SCSI case 8 (Hi <> Do)\r\n");
+      TU_LOG_DRV("  SCSI case 8 (Hi <> Do)\r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
     }
     else if ( 0 == block_count )
     {
-      TU_LOG(MSC_DEBUG, "  SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n");
+      TU_LOG_DRV("  SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n");
       status =  MSC_CSW_STATUS_FAILED;
     }
     else if ( cbw->total_bytes / block_count == 0 )
     {
-      TU_LOG(MSC_DEBUG, " Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n");
+      TU_LOG_DRV(" Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n");
       status = MSC_CSW_STATUS_PHASE_ERROR;
     }
   }
@@ -352,7 +355,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
   switch ( request->bRequest )
   {
     case MSC_REQ_RESET:
-      TU_LOG(MSC_DEBUG, "  MSC BOT Reset\r\n");
+      TU_LOG_DRV("  MSC BOT Reset\r\n");
       TU_VERIFY(request->wValue == 0 && request->wLength == 0);
 
       // driver state reset
@@ -363,7 +366,7 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
 
     case MSC_REQ_GET_MAX_LUN:
     {
-      TU_LOG(MSC_DEBUG, "  MSC Get Max Lun\r\n");
+      TU_LOG_DRV("  MSC Get Max Lun\r\n");
       TU_VERIFY(request->wValue == 0 && request->wLength == 1);
 
       uint8_t maxlun = 1;
@@ -400,7 +403,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
 
       if ( !(xferred_bytes == sizeof(msc_cbw_t) && p_cbw->signature == MSC_CBW_SIGNATURE) )
       {
-        TU_LOG(MSC_DEBUG, "  SCSI CBW is not valid\r\n");
+        TU_LOG_DRV("  SCSI CBW is not valid\r\n");
 
         // BOT 6.6.1 If CBW is not valid stall both endpoints until reset recovery
         p_msc->stage = MSC_STAGE_NEED_RESET;
@@ -412,7 +415,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         return false;
       }
 
-      TU_LOG(MSC_DEBUG, "  SCSI Command [Lun%u]: %s\r\n", p_cbw->lun, tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
+      TU_LOG_DRV("  SCSI Command [Lun%u]: %s\r\n", p_cbw->lun, tu_lookup_find(&_msc_scsi_cmd_table, p_cbw->command[0]));
       //TU_LOG_MEM(MSC_DEBUG, p_cbw, xferred_bytes, 2);
 
       p_csw->signature    = MSC_CSW_SIGNATURE;
@@ -457,7 +460,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
         {
           if (p_cbw->total_bytes > sizeof(_mscd_buf))
           {
-            TU_LOG(MSC_DEBUG, "  SCSI reject non READ10/WRITE10 with large data\r\n");
+            TU_LOG_DRV("  SCSI reject non READ10/WRITE10 with large data\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
           }else
           {
@@ -479,7 +482,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           if ( resplen < 0 )
           {
             // unsupported command
-            TU_LOG(MSC_DEBUG, "  SCSI unsupported or failed command\r\n");
+            TU_LOG_DRV("  SCSI unsupported or failed command\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
           }
           else if (resplen == 0)
@@ -514,7 +517,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
     break;
 
     case MSC_STAGE_DATA:
-      TU_LOG(MSC_DEBUG, "  SCSI Data [Lun%u]\r\n", p_cbw->lun);
+      TU_LOG_DRV("  SCSI Data [Lun%u]\r\n", p_cbw->lun);
       //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2);
 
       if (SCSI_CMD_READ_10 == p_cbw->command[0])
@@ -546,7 +549,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
           if ( cb_result < 0 )
           {
             // unsupported command
-            TU_LOG(MSC_DEBUG, "  SCSI unsupported command\r\n");
+            TU_LOG_DRV("  SCSI unsupported command\r\n");
             fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED);
           }else
           {
@@ -575,7 +578,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t
       // Wait for the Status phase to complete
       if( (ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t)) )
       {
-        TU_LOG(MSC_DEBUG, "  SCSI Status [Lun%u] = %u\r\n", p_cbw->lun, p_csw->status);
+        TU_LOG_DRV("  SCSI Status [Lun%u] = %u\r\n", p_cbw->lun, p_csw->status);
         // TU_LOG_MEM(MSC_DEBUG, p_csw, xferred_bytes, 2);
 
         // Invoke complete callback if defined
@@ -845,7 +848,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc)
   if ( nbytes < 0 )
   {
     // negative means error -> endpoint is stalled & status in CSW set to failed
-    TU_LOG(MSC_DEBUG, "  tud_msc_read10_cb() return -1\r\n");
+    TU_LOG_DRV("  tud_msc_read10_cb() return -1\r\n");
 
     // set sense
     set_sense_medium_not_present(p_cbw->lun);
@@ -907,7 +910,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3
   if ( nbytes < 0 )
   {
     // negative means error -> failed this scsi op
-    TU_LOG(MSC_DEBUG, "  tud_msc_write10_cb() return -1\r\n");
+    TU_LOG_DRV("  tud_msc_write10_cb() return -1\r\n");
 
     // update actual byte before failed
     p_msc->xferred_len += xferred_bytes;
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 44c2530ce..9429cf664 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -43,9 +43,6 @@
   #define CFG_TUD_TASK_QUEUE_SZ   16
 #endif
 
-// Debug level of USBD
-#define USBD_DBG   2
-
 //--------------------------------------------------------------------+
 // Device Data
 //--------------------------------------------------------------------+
@@ -81,7 +78,7 @@ tu_static usbd_device_t _usbd_dev;
 //--------------------------------------------------------------------+
 // Class Driver
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   #define DRIVER_NAME(_name)    .name = _name,
 #else
   #define DRIVER_NAME(_name)
@@ -308,7 +305,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event,
 //--------------------------------------------------------------------+
 // Debug
 //--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
 tu_static char const* const _usbd_event_str[DCD_EVENT_COUNT] =
 {
   "Invalid"        ,
@@ -330,7 +327,7 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
     usbd_class_driver_t const * driver = get_driver(i);
     if ( driver && driver->control_xfer_cb == callback )
     {
-      TU_LOG(USBD_DBG, "  %s control complete\r\n", driver->name);
+      TU_LOG_USBD("  %s control complete\r\n", driver->name);
       return;
     }
   }
@@ -396,10 +393,10 @@ bool tud_init (uint8_t rhport)
   // skip if already initialized
   if ( tud_inited() ) return true;
 
-  TU_LOG(USBD_DBG, "USBD init on controller %u\r\n", rhport);
-  TU_LOG_INT(USBD_DBG, sizeof(usbd_device_t));
-  TU_LOG_INT(USBD_DBG, sizeof(tu_fifo_t));
-  TU_LOG_INT(USBD_DBG, sizeof(tu_edpt_stream_t));
+  TU_LOG_USBD("USBD init on controller %u\r\n", rhport);
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t));
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t));
+  TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_edpt_stream_t));
 
   tu_varclr(&_usbd_dev);
 
@@ -424,7 +421,7 @@ bool tud_init (uint8_t rhport)
   {
     usbd_class_driver_t const * driver = get_driver(i);
     TU_ASSERT(driver);
-    TU_LOG(USBD_DBG, "%s init\r\n", driver->name);
+    TU_LOG_USBD("%s init\r\n", driver->name);
     driver->init();
   }
 
@@ -496,21 +493,21 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
     dcd_event_t event;
     if ( !osal_queue_receive(_usbd_q, &event, timeout_ms) ) return;
 
-#if CFG_TUSB_DEBUG >= 2
-    if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG(USBD_DBG, "\r\n"); // extra line for setup
-    TU_LOG(USBD_DBG, "USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED");
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
+    if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG_USBD("\r\n"); // extra line for setup
+    TU_LOG_USBD("USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED");
 #endif
 
     switch ( event.event_id )
     {
       case DCD_EVENT_BUS_RESET:
-        TU_LOG(USBD_DBG, ": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]);
+        TU_LOG_USBD(": %s Speed\r\n", tu_str_speed[event.bus_reset.speed]);
         usbd_reset(event.rhport);
         _usbd_dev.speed = event.bus_reset.speed;
       break;
 
       case DCD_EVENT_UNPLUGGED:
-        TU_LOG(USBD_DBG, "\r\n");
+        TU_LOG_USBD("\r\n");
         usbd_reset(event.rhport);
 
         // invoke callback
@@ -518,8 +515,8 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
       break;
 
       case DCD_EVENT_SETUP_RECEIVED:
-        TU_LOG_PTR(USBD_DBG, &event.setup_received);
-        TU_LOG(USBD_DBG, "\r\n");
+        TU_LOG_PTR(CFG_TUD_LOG_LEVEL, &event.setup_received);
+        TU_LOG_USBD("\r\n");
 
         // Mark as connected after receiving 1st setup packet.
         // But it is easier to set it every time instead of wasting time to check then set
@@ -534,7 +531,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         // Process control request
         if ( !process_control_request(event.rhport, &event.setup_received) )
         {
-          TU_LOG(USBD_DBG, "  Stall EP0\r\n");
+          TU_LOG_USBD("  Stall EP0\r\n");
           // Failed -> stall both control endpoint IN and OUT
           dcd_edpt_stall(event.rhport, 0);
           dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK);
@@ -548,7 +545,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         uint8_t const epnum   = tu_edpt_number(ep_addr);
         uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
-        TU_LOG(USBD_DBG, "on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
+        TU_LOG_USBD("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
 
         _usbd_dev.ep_status[epnum][ep_dir].busy = 0;
         _usbd_dev.ep_status[epnum][ep_dir].claimed = 0;
@@ -563,7 +560,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
           usbd_class_driver_t const * driver = get_driver( _usbd_dev.ep2drv[epnum][ep_dir] );
           TU_ASSERT(driver, );
 
-          TU_LOG(USBD_DBG, "  %s xfer callback\r\n", driver->name);
+          TU_LOG_USBD("  %s xfer callback\r\n", driver->name);
           driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
         }
       }
@@ -575,27 +572,27 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
         // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected
         if ( _usbd_dev.connected )
         {
-          TU_LOG(USBD_DBG, ": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
+          TU_LOG_USBD(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
           if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
         }else
         {
-          TU_LOG(USBD_DBG, " Skipped\r\n");
+          TU_LOG_USBD(" Skipped\r\n");
         }
       break;
 
       case DCD_EVENT_RESUME:
         if ( _usbd_dev.connected )
         {
-          TU_LOG(USBD_DBG, "\r\n");
+          TU_LOG_USBD("\r\n");
           if (tud_resume_cb) tud_resume_cb();
         }else
         {
-          TU_LOG(USBD_DBG, " Skipped\r\n");
+          TU_LOG_USBD(" Skipped\r\n");
         }
       break;
 
       case USBD_EVENT_FUNC_CALL:
-        TU_LOG(USBD_DBG, "\r\n");
+        TU_LOG_USBD("\r\n");
         if ( event.func_call.func ) event.func_call.func(event.func_call.param);
       break;
 
@@ -620,7 +617,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
 static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request)
 {
   usbd_control_set_complete_callback(driver->control_xfer_cb);
-  TU_LOG(USBD_DBG, "  %s control request\r\n", driver->name);
+  TU_LOG_USBD("  %s control request\r\n", driver->name);
   return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request);
 }
 
@@ -641,11 +638,11 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
     return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request);
   }
 
-#if CFG_TUSB_DEBUG >= 2
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME)
   {
-    TU_LOG(USBD_DBG, "  %s", tu_str_std_request[p_request->bRequest]);
-    if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG(USBD_DBG, "\r\n");
+    TU_LOG_USBD("  %s", tu_str_std_request[p_request->bRequest]);
+    if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG_USBD("\r\n");
   }
 #endif
 
@@ -701,7 +698,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
             if ( _usbd_dev.cfg_num )
             {
               // already configured: need to clear all endpoints and driver first
-              TU_LOG(USBD_DBG, "  Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num);
+              TU_LOG_USBD("  Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num);
 
               // close all non-control endpoints, cancel all pending transfers if any
               dcd_edpt_close_all(rhport);
@@ -730,7 +727,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           // Only support remote wakeup for device feature
           TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
 
-          TU_LOG(USBD_DBG, "    Enable Remote Wakeup\r\n");
+          TU_LOG_USBD("    Enable Remote Wakeup\r\n");
 
           // Host may enable remote wake up before suspending especially HID device
           _usbd_dev.remote_wakeup_en = true;
@@ -741,7 +738,7 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
           // Only support remote wakeup for device feature
           TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
 
-          TU_LOG(USBD_DBG, "    Disable Remote Wakeup\r\n");
+          TU_LOG_USBD("    Disable Remote Wakeup\r\n");
 
           // Host may disable remote wake up after resuming
           _usbd_dev.remote_wakeup_en = false;
@@ -924,7 +921,7 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
       if ( (sizeof(tusb_desc_interface_t) <= drv_len)  && (drv_len <= remaining_len) )
       {
         // Open successfully
-        TU_LOG(USBD_DBG, "  %s opened\r\n", driver->name);
+        TU_LOG_USBD("  %s opened\r\n", driver->name);
 
         // Some drivers use 2 or more interfaces but may not have IAD e.g MIDI (always) or
         // BTH (even CDC) with class in device descriptor (single interface)
@@ -983,7 +980,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
   {
     case TUSB_DESC_DEVICE:
     {
-      TU_LOG(USBD_DBG, " Device\r\n");
+      TU_LOG_USBD(" Device\r\n");
 
       void* desc_device = (void*) (uintptr_t) tud_descriptor_device_cb();
 
@@ -1007,7 +1004,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
     case TUSB_DESC_BOS:
     {
-      TU_LOG(USBD_DBG, " BOS\r\n");
+      TU_LOG_USBD(" BOS\r\n");
 
       // requested by host if USB > 2.0 ( i.e 2.1 or 3.x )
       if (!tud_descriptor_bos_cb) return false;
@@ -1029,12 +1026,12 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
       if ( desc_type == TUSB_DESC_CONFIGURATION )
       {
-        TU_LOG(USBD_DBG, " Configuration[%u]\r\n", desc_index);
+        TU_LOG_USBD(" Configuration[%u]\r\n", desc_index);
         desc_config = (uintptr_t) tud_descriptor_configuration_cb(desc_index);
       }else
       {
         // Host only request this after getting Device Qualifier descriptor
-        TU_LOG(USBD_DBG, " Other Speed Configuration\r\n");
+        TU_LOG_USBD(" Other Speed Configuration\r\n");
         TU_VERIFY( tud_descriptor_other_speed_configuration_cb );
         desc_config = (uintptr_t) tud_descriptor_other_speed_configuration_cb(desc_index);
       }
@@ -1050,7 +1047,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
     case TUSB_DESC_STRING:
     {
-      TU_LOG(USBD_DBG, " String[%u]\r\n", desc_index);
+      TU_LOG_USBD(" String[%u]\r\n", desc_index);
 
       // String Descriptor always uses the desc set from user
       uint8_t const* desc_str = (uint8_t const*) tud_descriptor_string_cb(desc_index, tu_le16toh(p_request->wIndex));
@@ -1063,7 +1060,7 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const
 
     case TUSB_DESC_DEVICE_QUALIFIER:
     {
-      TU_LOG(USBD_DBG, " Device Qualifier\r\n");
+      TU_LOG_USBD(" Device Qualifier\r\n");
 
       TU_VERIFY( tud_descriptor_device_qualifier_cb );
 
@@ -1248,7 +1245,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
   // TODO skip ready() check for now since enumeration also use this API
   // TU_VERIFY(tud_ready());
 
-  TU_LOG(USBD_DBG, "  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
+  TU_LOG_USBD("  Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
@@ -1265,7 +1262,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
     // DCD error, mark endpoint as ready to allow next transfer
     _usbd_dev.ep_status[epnum][dir].busy = 0;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
-    TU_LOG(USBD_DBG, "FAILED\r\n");
+    TU_LOG_USBD("FAILED\r\n");
     TU_BREAKPOINT();
     return false;
   }
@@ -1282,7 +1279,7 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  TU_LOG(USBD_DBG, "  Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes);
+  TU_LOG_USBD("  Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes);
 
   // Attempt to transfer on a busy endpoint, sound like an race condition !
   TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
@@ -1293,14 +1290,14 @@ bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
 
   if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes))
   {
-    TU_LOG(USBD_DBG, "OK\r\n");
+    TU_LOG_USBD("OK\r\n");
     return true;
   }else
   {
     // DCD error, mark endpoint as ready to allow next transfer
     _usbd_dev.ep_status[epnum][dir].busy = 0;
     _usbd_dev.ep_status[epnum][dir].claimed = 0;
-    TU_LOG(USBD_DBG, "failed\r\n");
+    TU_LOG_USBD("failed\r\n");
     TU_BREAKPOINT();
     return false;
   }
@@ -1326,7 +1323,7 @@ void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
   // only stalled if currently cleared
   if ( !_usbd_dev.ep_status[epnum][dir].stalled )
   {
-    TU_LOG(USBD_DBG, "    Stall EP %02X\r\n", ep_addr);
+    TU_LOG_USBD("    Stall EP %02X\r\n", ep_addr);
     dcd_edpt_stall(rhport, ep_addr);
     _usbd_dev.ep_status[epnum][dir].stalled = 1;
     _usbd_dev.ep_status[epnum][dir].busy = 1;
@@ -1343,7 +1340,7 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
   // only clear if currently stalled
   if ( _usbd_dev.ep_status[epnum][dir].stalled )
   {
-    TU_LOG(USBD_DBG, "    Clear Stall EP %02X\r\n", ep_addr);
+    TU_LOG_USBD("    Clear Stall EP %02X\r\n", ep_addr);
     dcd_edpt_clear_stall(rhport, ep_addr);
     _usbd_dev.ep_status[epnum][dir].stalled = 0;
     _usbd_dev.ep_status[epnum][dir].busy = 0;
@@ -1371,7 +1368,7 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   rhport = _usbd_rhport;
 
   TU_ASSERT(dcd_edpt_close, /**/);
-  TU_LOG(USBD_DBG, "  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
+  TU_LOG_USBD("  CLOSING Endpoint: 0x%02X\r\n", ep_addr);
 
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index 2afe967b5..c580e6ecf 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -32,10 +32,7 @@
 #include "tusb.h"
 #include "device/usbd_pvt.h"
 
-// Debug level of USBD Control
-#define USBD_CONTROL_DEBUG   2
-
-#if CFG_TUSB_DEBUG >= USBD_CONTROL_DEBUG
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
 extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
 #endif
 
@@ -191,7 +188,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
   {
     TU_VERIFY(_ctrl_xfer.buffer);
     memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes);
-    TU_LOG_MEM(USBD_CONTROL_DEBUG, _usbd_ctrl_buf, xferred_bytes, 2);
+    TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2);
   }
 
   _ctrl_xfer.total_xferred += (uint16_t) xferred_bytes;
@@ -208,7 +205,7 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
     // callback can still stall control in status phase e.g out data does not make sense
     if ( _ctrl_xfer.complete_cb )
     {
-      #if CFG_TUSB_DEBUG >= USBD_CONTROL_DEBUG
+      #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
       usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb);
       #endif
 
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 8393d3469..940b2858b 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -33,13 +33,20 @@
  extern "C" {
 #endif
 
+// Level where CFG_TUSB_DEBUG must be at least for USBD is logged
+#ifndef CFG_TUD_LOG_LEVEL
+#define CFG_TUD_LOG_LEVEL   2
+#endif
+
+#define TU_LOG_USBD(...)   TU_LOG(CFG_TUD_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // Class Driver API
 //--------------------------------------------------------------------+
 
 typedef struct
 {
-  #if CFG_TUSB_DEBUG >= 2
+  #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   char const* name;
   #endif
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 184bda23b..58129c16e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -38,17 +38,19 @@
 //--------------------------------------------------------------------+
 
 #ifndef CFG_TUH_TASK_QUEUE_SZ
-#define CFG_TUH_TASK_QUEUE_SZ   16
+  #define CFG_TUH_TASK_QUEUE_SZ   16
 #endif
 
 #ifndef CFG_TUH_INTERFACE_MAX
-#define CFG_TUH_INTERFACE_MAX   8
+  #define CFG_TUH_INTERFACE_MAX   8
 #endif
 
-// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
-#define USBH_DEBUG   2
+// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
+#ifndef CFG_TUH_LOG_LEVEL
+  #define CFG_TUH_LOG_LEVEL   2
+#endif
 
-#define TU_LOG_USBH(...)   TU_LOG(USBH_DEBUG, __VA_ARGS__)
+#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
 // USBH-HCD common data structure
@@ -322,12 +324,12 @@ bool tuh_init(uint8_t controller_id)
   if ( tuh_inited() ) return true;
 
   TU_LOG_USBH("USBH init on controller %u\r\n", controller_id);
-  TU_LOG_INT(USBH_DEBUG, sizeof(usbh_device_t));
-  TU_LOG_INT(USBH_DEBUG, sizeof(hcd_event_t));
-  TU_LOG_INT(USBH_DEBUG, sizeof(_ctrl_xfer));
-  TU_LOG_INT(USBH_DEBUG, sizeof(tuh_xfer_t));
-  TU_LOG_INT(USBH_DEBUG, sizeof(tu_fifo_t));
-  TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(usbh_device_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(hcd_event_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(_ctrl_xfer));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tuh_xfer_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_fifo_t));
+  TU_LOG_INT(CFG_TUH_LOG_LEVEL, sizeof(tu_edpt_stream_t));
 
   // Event queue
   _usbh_q = osal_queue_create( &_usbh_qdef );
@@ -565,7 +567,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
   TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr,
               (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
                   tu_str_std_request[xfer->setup->bRequest] : "Class Request");
-  TU_LOG_PTR(USBH_DEBUG, xfer->setup);
+  TU_LOG_PTR(CFG_TUH_LOG_LEVEL, xfer->setup);
   TU_LOG_USBH("\r\n");
 
   if (xfer->complete_cb)
@@ -671,7 +673,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
         if (request->wLength)
         {
           TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr);
-          TU_LOG_MEM(USBH_DEBUG, _ctrl_xfer.buffer, xferred_bytes, 2);
+          TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2);
         }
 
         _ctrl_xfer.actual_len = (uint16_t) xferred_bytes;
@@ -1186,7 +1188,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
       TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
 
       if (is_hub_addr(daddr)) {
-        TU_LOG(USBH_DEBUG, "  is a HUB device %u\r\n", daddr);
+        TU_LOG(CFG_TUH_LOG_LEVEL, "  is a HUB device %u\r\n", daddr);
 
         // Submit removed event If the device itself is a hub (un-rolled recursive)
         // TODO a better to unroll recursrive is using array of removing_hubs and mark it here
@@ -1657,7 +1659,7 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
 
       if( drv_id >= USBH_CLASS_DRIVER_COUNT )
       {
-        TU_LOG(USBH_DEBUG, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+        TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
                desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
       }
     }
@@ -1695,7 +1697,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
 
     if (is_hub_addr(dev_addr))
     {
-      TU_LOG(USBH_DEBUG, "HUB address = %u is mounted\r\n", dev_addr);
+      TU_LOG(CFG_TUH_LOG_LEVEL, "HUB address = %u is mounted\r\n", dev_addr);
     }else
     {
       // Invoke callback if available

From 954f0e948d0df2ed64d31ba23369e6c2a22ec63f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 20 Jul 2023 17:37:06 +0700
Subject: [PATCH 1909/2085] prefer application callback over built-in driver

---
 src/host/usbh.c | 56 ++++++++++++++++++++++---------------------------
 1 file changed, 25 insertions(+), 31 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 58129c16e..ecc672198 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -452,39 +452,28 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
         TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len,
                     tu_str_xfer_result[event.xfer_complete.result]);
 
-        if (event.dev_addr == 0)
-        {
+        if (event.dev_addr == 0) {
           // device 0 only has control endpoint
           TU_ASSERT(epnum == 0, );
           usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
-        }
-        else
-        {
+        } else {
           usbh_device_t* dev = get_device(event.dev_addr);
           TU_VERIFY(dev && dev->connected, );
 
           dev->ep_status[epnum][ep_dir].busy    = 0;
           dev->ep_status[epnum][ep_dir].claimed = 0;
 
-          if ( 0 == epnum )
-          {
-            usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
-          }else
-          {
-            uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
-            if(drv_id < USBH_CLASS_DRIVER_COUNT)
-            {
-              TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
-              usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len);
-            }
-            else
-            {
-#if CFG_TUH_API_EDPT_XFER
-              tuh_xfer_cb_t complete_cb = dev->ep_callback[epnum][ep_dir].complete_cb;
-              if ( complete_cb )
-              {
-                tuh_xfer_t xfer =
-                {
+          if ( 0 == epnum ) {
+            usbh_control_xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
+                                 event.xfer_complete.len);
+          }else {
+            // Prefer application callback over built-in one if available. This occurs when tuh_edpt_xfer() is used
+            // with enabled driver e.g HID endpoint
+            #if CFG_TUH_API_EDPT_XFER
+            tuh_xfer_cb_t const complete_cb = dev->ep_callback[epnum][ep_dir].complete_cb;
+            if ( complete_cb ) {
+              // re-construct xfer info
+              tuh_xfer_t xfer = {
                   .daddr       = event.dev_addr,
                   .ep_addr     = ep_addr,
                   .result      = event.xfer_complete.result,
@@ -493,16 +482,21 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
                   .buffer      = NULL, // not available
                   .complete_cb = complete_cb,
                   .user_data   = dev->ep_callback[epnum][ep_dir].user_data
-                };
+              };
 
-                complete_cb(&xfer);
-              }else
-#endif
-              {
+              complete_cb(&xfer);
+            }else
+            #endif
+            {
+              uint8_t const drv_id = dev->ep2drv[epnum][ep_dir];
+              if ( drv_id < USBH_CLASS_DRIVER_COUNT ) {
+                TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
+                usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
+                                                   event.xfer_complete.len);
+              } else {
                 // no driver/callback responsible for this transfer
-                TU_ASSERT(false, );
+                TU_ASSERT(false,);
               }
-
             }
           }
         }

From 6ac7f19640d59f6d28054555430de2a083c78eeb Mon Sep 17 00:00:00 2001
From: jferreir <jesus.ferreira@gmail.com>
Date: Thu, 20 Jul 2023 16:51:42 +0200
Subject: [PATCH 1910/2085] fix compilation issues for XMC4500_RELAX

---
 hw/bsp/xmc4000/boards/xmc4500_relax/board.mk | 2 +-
 hw/bsp/xmc4000/family.c                      | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
index 371adff91..2b8f7bc57 100644
--- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
+++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.mk
@@ -3,7 +3,7 @@ CFLAGS += \
   -DXMC4500_F100x1024 \
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=stringop-overread
+CFLAGS += -Wno-stringop-overread
 
 LD_FILE = $(MCU_DIR)/CMSIS/Infineon/COMPONENT_$(MCU_VARIANT)/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld
 
diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c
index 35bed0ba4..78c968468 100644
--- a/hw/bsp/xmc4000/family.c
+++ b/hw/bsp/xmc4000/family.c
@@ -84,7 +84,9 @@ void board_init(void)
 #endif
 
   // USB Power Enable
+#if(UC_SERIES != XMC45)
   XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0);
+#endif  
   XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0);
   XMC_SCU_POWER_EnableUsb();
 }

From 34ff7af7c752032d024f5e50774694b6b7ecf403 Mon Sep 17 00:00:00 2001
From: jferreir <jesus.ferreira@gmail.com>
Date: Thu, 20 Jul 2023 18:12:36 +0200
Subject: [PATCH 1911/2085] Fix trailing spaces issue

---
 hw/bsp/xmc4000/family.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c
index 78c968468..146bef373 100644
--- a/hw/bsp/xmc4000/family.c
+++ b/hw/bsp/xmc4000/family.c
@@ -86,7 +86,7 @@ void board_init(void)
   // USB Power Enable
 #if(UC_SERIES != XMC45)
   XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_USB0);
-#endif  
+#endif
   XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_USB0);
   XMC_SCU_POWER_EnableUsb();
 }

From 1cc7c5d0309bcc7c6930fba78bc461e5822e8024 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 20 Jul 2023 11:20:12 +0700
Subject: [PATCH 1912/2085] add hcd_edpt_abort_xfer() API

---
 examples/dual/host_hid_to_device_cdc/only.txt |  1 +
 src/host/hcd.h                                |  3 ++
 src/host/usbh.c                               | 28 +++++++++++++------
 src/host/usbh.h                               |  7 +++--
 src/portable/ehci/ehci.c                      | 18 ++++++++++++
 5 files changed, 47 insertions(+), 10 deletions(-)

diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt
index 6ee8e3fde..de5d8bed9 100644
--- a/examples/dual/host_hid_to_device_cdc/only.txt
+++ b/examples/dual/host_hid_to_device_cdc/only.txt
@@ -1,3 +1,4 @@
 board:mimxrt1060_evk
 board:mimxrt1064_evk
+board:mcb1800
 mcu:RP2040
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 3355c18b2..cbfffb349 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -171,6 +171,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
 
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
+
 // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index ecc672198..bbf333d5f 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -710,6 +710,19 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer)
   return true;
 }
 
+bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) {
+  usbh_device_t* dev = get_device(daddr);
+  TU_VERIFY(dev);
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
+  // skip if not busy
+  if (!dev->ep_status[epnum][dir].busy) return true;
+
+  return hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr);
+}
+
 //--------------------------------------------------------------------+
 // USBH API For Class Driver
 //--------------------------------------------------------------------+
@@ -741,7 +754,7 @@ void usbh_int_set(bool enabled)
 // Endpoint API
 //--------------------------------------------------------------------+
 
-// TODO has some duplication code with device, refactor later
+// Claim an endpoint for transfer
 bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
 {
   // Note: addr0 only use tuh_control_xfer
@@ -757,7 +770,7 @@ bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
   return true;
 }
 
-// TODO has some duplication code with device, refactor later
+// Release an claimed endpoint due to failed transfer attempt
 bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
 {
   // Note: addr0 only use tuh_control_xfer
@@ -773,7 +786,7 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
   return true;
 }
 
-// TODO has some duplication code with device, refactor later
+// Submit an transfer
 bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
@@ -840,14 +853,13 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
   return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep);
 }
 
-bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
-{
-  uint8_t const epnum = tu_edpt_number(ep_addr);
-  uint8_t const dir   = tu_edpt_dir(ep_addr);
-
+bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) {
   usbh_device_t* dev = get_device(dev_addr);
   TU_VERIFY(dev);
 
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir   = tu_edpt_dir(ep_addr);
+
   return dev->ep_status[epnum][dir].busy;
 }
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 0f969a46a..d765f6744 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -172,8 +172,11 @@ bool tuh_control_xfer(tuh_xfer_t* xfer);
 //  - sync : blocking if complete callback is NULL.
 bool tuh_edpt_xfer(tuh_xfer_t* xfer);
 
-// Open an non-control endpoint
-bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
+// Open a non-control endpoint
+bool tuh_edpt_open(uint8_t daddr, tusb_desc_endpoint_t const * desc_ep);
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr);
 
 // Set Configuration (control transfer)
 // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 38711e382..fd33d6cfc 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -510,6 +510,24 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   return true;
 }
 
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+
+//  uint8_t const epnum = tu_edpt_number(ep_addr);
+//  ehci_qhd_t* qhd;
+//
+//  // TODO ISO not supported
+//  if (epnum == 0) {
+//    qhd = qhd_control(dev_addr);
+//  }else {
+//    qhd = qhd_get_from_addr(dev_addr, ep_addr);
+//  }
+}
+
 bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr)
 {
   ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr);

From 0da273ea79d7a1c08e3b58301a0b7d3a49c60d13 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 21 Jul 2023 12:52:26 +0700
Subject: [PATCH 1913/2085] add stub hcd_edpt_abort_xfer() for all ports

---
 src/portable/mentor/musb/hcd_musb.c            | 8 ++++++++
 src/portable/nxp/khci/hcd_khci.c               | 8 ++++++++
 src/portable/ohci/ohci.c                       | 8 ++++++++
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 8 ++++++++
 src/portable/raspberrypi/rp2040/hcd_rp2040.c   | 8 ++++++++
 src/portable/renesas/rusb2/hcd_rusb2.c         | 8 ++++++++
 6 files changed, 48 insertions(+)

diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 9eb2e005e..5be67a186 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -822,6 +822,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b
   return ret;
 }
 
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
+}
+
 // clear stall, data toggle is also reset to DATA0
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index f6029ee0d..6784049c5 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -562,6 +562,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   return true;
 }
 
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
+}
+
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
   if (!tu_edpt_number(ep_addr)) return true;
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 3f702d22c..228c43df6 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -543,6 +543,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   return true;
 }
 
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
+}
+
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
   ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr);
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index 264af2e7a..fa285327c 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -138,6 +138,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen);
 }
 
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
+}
+
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 02f9968a7..5091fa907 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -576,6 +576,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   return true;
 }
 
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
+}
+
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
   (void) rhport;
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 65bbc656b..0a75d0b47 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -710,6 +710,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b
   return r;
 }
 
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  // TODO not implemented yet
+  return false;
+}
+
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
   uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr);

From 14c98dd863a9cab55fc2981fb826f63eceed4b2d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 21 Jul 2023 16:39:30 +0700
Subject: [PATCH 1914/2085] minor ehci rename, move code around

---
 src/portable/ehci/ehci.c | 181 ++++++++++++++++++++-------------------
 1 file changed, 91 insertions(+), 90 deletions(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index fd33d6cfc..0a26986d5 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -126,53 +126,29 @@ static inline void print_intr(uint32_t intr) {
 //--------------------------------------------------------------------+
 // PROTOTYPE
 //--------------------------------------------------------------------+
-static inline ehci_link_t* get_period_head(uint8_t rhport, uint32_t interval_ms)
-{
-  (void) rhport;
-  return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min32(FRAMELIST_SIZE, interval_ms) ) ];
-}
 
-static inline ehci_qhd_t* qhd_control(uint8_t dev_addr)
-{
-  return &ehci_data.control[dev_addr].qhd;
-}
+// weak dcache for non-cacheable MCU
+TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; }
+TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; }
+TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; }
 
-static inline ehci_qhd_t* qhd_async_head(uint8_t rhport)
-{
-  (void) rhport;
-  // control qhd of dev0 is used as async head
-  return qhd_control(0);
-}
+TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport);
 
-static inline ehci_qtd_t* qtd_control(uint8_t dev_addr)
-{
-  return &ehci_data.control[dev_addr].qtd;
-}
-
-
-static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd);
-static inline ehci_qhd_t* qhd_find_free (void);
-static inline ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_find_free (void);
+static ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
 static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd);
 
-static inline ehci_qtd_t* qtd_find_free (void);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_find_free (void);
 static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes);
 
 static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
 static inline ehci_link_t* list_next (ehci_link_t const *p_link);
-
-TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) {
-  (void) addr; (void) data_size;
-}
-
-TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
-  (void) addr; (void) data_size;
-}
-
-TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
-  (void) addr; (void) data_size;
-}
+static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr);
 
 //--------------------------------------------------------------------+
 // HCD API
@@ -274,7 +250,7 @@ void hcd_device_close(uint8_t rhport, uint8_t daddr)
   }
 
   // Remove from async list
-  list_remove_qhd_by_daddr((ehci_link_t *) qhd_async_head(rhport), daddr);
+  list_remove_qhd_by_daddr((ehci_link_t *) list_get_async_head(rhport), daddr);
 
   // Remove from all interval period list
   for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) {
@@ -286,37 +262,42 @@ void hcd_device_close(uint8_t rhport, uint8_t daddr)
 }
 
 static void init_periodic_list(uint8_t rhport) {
+  (void) rhport;
+
   // Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only
   for ( uint32_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++ ) {
     ehci_data.period_head_arr[i].int_smask          = 1; // queue head in period list must have smask non-zero
     ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive
   }
 
-  ehci_link_t * const framelist  = ehci_data.period_framelist;
-  ehci_link_t * const period_1ms = get_period_head(rhport, 1u);
-
+  // TODO EHCI_FRAMELIST_SIZE with other size than 8
   // all links --> period_head_arr[0] (1ms)
   // 0, 2, 4, 6 etc --> period_head_arr[1] (2ms)
   // 1, 5 --> period_head_arr[2] (4ms)
   // 3 --> period_head_arr[3] (8ms)
 
-  // TODO EHCI_FRAMELIST_SIZE with other size than 8
+  ehci_link_t * const framelist  = ehci_data.period_framelist;
+  ehci_link_t * const head_1ms = (ehci_link_t *) &ehci_data.period_head_arr[0];
+  ehci_link_t * const head_2ms = (ehci_link_t *) &ehci_data.period_head_arr[1];
+  ehci_link_t * const head_4ms = (ehci_link_t *) &ehci_data.period_head_arr[2];
+  ehci_link_t * const head_8ms = (ehci_link_t *) &ehci_data.period_head_arr[3];
+
   for (uint32_t i = 0; i < FRAMELIST_SIZE; i++) {
-    framelist[i].address = (uint32_t) period_1ms;
+    framelist[i].address = (uint32_t) head_1ms;
     framelist[i].type = EHCI_QTYPE_QHD;
   }
 
   for (uint32_t i = 0; i < FRAMELIST_SIZE; i += 2) {
-    list_insert(framelist + i, get_period_head(rhport, 2u), EHCI_QTYPE_QHD);
+    list_insert(framelist + i, head_2ms, EHCI_QTYPE_QHD);
   }
 
   for (uint32_t i = 1; i < FRAMELIST_SIZE; i += 4) {
-    list_insert(framelist + i, get_period_head(rhport, 4u), EHCI_QTYPE_QHD);
+    list_insert(framelist + i, head_4ms, EHCI_QTYPE_QHD);
   }
 
-  list_insert(framelist + 3, get_period_head(rhport, 8u), EHCI_QTYPE_QHD);
+  list_insert(framelist + 3, head_8ms, EHCI_QTYPE_QHD);
 
-  period_1ms->terminate    = 1;
+  head_1ms->terminate = 1;
 }
 
 bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
@@ -345,7 +326,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
                  EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_FRAMELIST_ROLLOVER;
 
   //------------- Asynchronous List -------------//
-  ehci_qhd_t * const async_head = qhd_async_head(rhport);
+  ehci_qhd_t * const async_head = list_get_async_head(rhport);
   tu_memclr(async_head, sizeof(ehci_qhd_t));
 
   async_head->next.address                    = (uint32_t) async_head; // circular list, next is itself
@@ -426,11 +407,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   {
     case TUSB_XFER_CONTROL:
     case TUSB_XFER_BULK:
-      list_head = (ehci_link_t*) qhd_async_head(rhport);
+      list_head = (ehci_link_t*) list_get_async_head(rhport);
     break;
 
     case TUSB_XFER_INTERRUPT:
-      list_head = get_period_head(rhport, p_qhd->interval_ms);
+      list_head = list_get_period_head(rhport, p_qhd->interval_ms);
     break;
 
     case TUSB_XFER_ISOCHRONOUS:
@@ -439,10 +420,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 
     default: break;
   }
-
   TU_ASSERT(list_head);
 
-  // TODO might need to disable async/period list
   list_insert(list_head, (ehci_link_t*) p_qhd, EHCI_QTYPE_QHD);
 
   hcd_dcache_clean(p_qhd, sizeof(ehci_qhd_t));
@@ -622,8 +601,8 @@ void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
 TU_ATTR_ALWAYS_INLINE static inline
 void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms)
 {
-  uint32_t const period_1ms_addr = (uint32_t) get_period_head(rhport, 1u);
-  ehci_link_t next_link = * get_period_head(rhport, interval_ms);
+  uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u);
+  ehci_link_t next_link = *list_get_period_head(rhport, interval_ms);
 
   while (!next_link.terminate) {
     if (interval_ms > 1 && period_1ms_addr == tu_align32(next_link.address)) {
@@ -721,7 +700,7 @@ TU_ATTR_ALWAYS_INLINE static inline
 void xfer_error_isr(uint8_t rhport)
 {
   //------------- async list -------------//
-  ehci_qhd_t * const async_head = qhd_async_head(rhport);
+  ehci_qhd_t * const async_head = list_get_async_head(rhport);
   ehci_qhd_t *p_qhd = async_head;
   do
   {
@@ -731,10 +710,10 @@ void xfer_error_isr(uint8_t rhport)
   }while(p_qhd != async_head); // async list traversal, stop if loop around
 
   //------------- TODO refractor period list -------------//
-  uint32_t const period_1ms_addr = (uint32_t) get_period_head(rhport, 1u);
+  uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u);
   for (uint32_t interval_ms=1; interval_ms <= FRAMELIST_SIZE; interval_ms *= 2)
   {
-    ehci_link_t next_item = * get_period_head(rhport, interval_ms);
+    ehci_link_t next_item = *list_get_period_head(rhport, interval_ms);
 
     // TODO abstract max loop guard for period
     while( !next_item.terminate &&
@@ -801,7 +780,7 @@ void hcd_int_handler(uint8_t rhport)
 
   //------------- some QTD/SITD/ITD with IOC set is completed -------------//
   if (int_status & EHCI_INT_MASK_NXP_ASYNC) {
-    async_list_xfer_complete_isr(qhd_async_head(rhport));
+    async_list_xfer_complete_isr(list_get_async_head(rhport));
     regs->status = EHCI_INT_MASK_NXP_ASYNC; // Acknowledge
   }
 
@@ -828,35 +807,62 @@ void hcd_int_handler(uint8_t rhport)
 }
 
 //--------------------------------------------------------------------+
-// HELPER
+// List Managing Helper
 //--------------------------------------------------------------------+
 
+// Get head of periodic list
+TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms) {
+  (void) rhport;
+  return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min32(FRAMELIST_SIZE, interval_ms) ) ];
+}
 
-//------------- queue head helper -------------//
-static inline ehci_qhd_t* qhd_find_free (void)
+// Get head of async list
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport) {
+  (void) rhport;
+  return qhd_control(0); // control qhd of dev0 is used as async head
+}
+
+// insert at head
+static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type)
 {
-  for (uint32_t i=0; i<QHD_MAX; i++)
-  {
+  new->address = current->address;
+  current->address = ((uint32_t) new) | (new_type << 1);
+}
+
+static inline ehci_link_t* list_next(ehci_link_t const *p_link)
+{
+  return (ehci_link_t*) tu_align32(p_link->address);
+}
+
+//--------------------------------------------------------------------+
+// Queue Header helper
+//--------------------------------------------------------------------+
+
+// Get queue head for control transfer (always available)
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr) {
+  return &ehci_data.control[dev_addr].qhd;
+}
+
+// Find a free queue head
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_find_free(void) {
+  for ( uint32_t i = 0; i < QHD_MAX; i++ ) {
     if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i];
   }
-
   return NULL;
 }
 
-static inline ehci_qhd_t* qhd_next(ehci_qhd_t const * p_qhd)
-{
-  return (ehci_qhd_t*) tu_align32(p_qhd->next.address);
+// Next queue head link
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_next(ehci_qhd_t const *p_qhd) {
+  return (ehci_qhd_t *) tu_align32(p_qhd->next.address);
 }
 
-static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr)
-{
-  ehci_qhd_t* qhd_pool = ehci_data.qhd_pool;
+// Get queue head from address
+static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) {
+  ehci_qhd_t *qhd_pool = ehci_data.qhd_pool;
 
-  for(uint32_t i=0; i<QHD_MAX; i++)
-  {
+  for ( uint32_t i = 0; i < QHD_MAX; i++ ) {
     if ( (qhd_pool[i].dev_addr == dev_addr) &&
-          ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) )
-    {
+         ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) ) {
       return &qhd_pool[i];
     }
   }
@@ -864,6 +870,7 @@ static inline ehci_qhd_t* qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr)
   return NULL;
 }
 
+// Init queue head with endpoint descriptor
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
 {
   // address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise)
@@ -938,6 +945,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c
   }
 }
 
+// Attach a TD to queue head
 static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd) {
   qhd->attached_qtd = qtd;
   qhd->attached_buffer = qtd->buffer[0];
@@ -949,9 +957,16 @@ static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd) {
   hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
 }
 
+//--------------------------------------------------------------------+
+// Queue TD helper
+//--------------------------------------------------------------------+
 
-//------------- TD helper -------------//
-static inline ehci_qtd_t *qtd_find_free(void) {
+// Get TD for control transfer (always available)
+TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr) {
+  return &ehci_data.control[dev_addr].qtd;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t *qtd_find_free(void) {
   for (uint32_t i = 0; i < QTD_MAX; i++) {
     if (!ehci_data.qtd_pool[i].used) return &ehci_data.qtd_pool[i];
   }
@@ -979,18 +994,4 @@ static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
   }
 }
 
-//------------- List Managing Helper -------------//
-
-// insert at head
-static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type)
-{
-  new->address = current->address;
-  current->address = ((uint32_t) new) | (new_type << 1);
-}
-
-static inline ehci_link_t* list_next(ehci_link_t const *p_link)
-{
-  return (ehci_link_t*) tu_align32(p_link->address);
-}
-
 #endif

From c122e9df73331fa60d1713c7cc4cf46251b0cd76 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 21 Jul 2023 19:06:36 +0700
Subject: [PATCH 1915/2085] implement hcd_edpt_abort_xfer() for EHCI, also move
 thing around a bit

---
 src/common/tusb_common.h |   2 +
 src/host/hcd.h           |   1 +
 src/host/usbh.c          |  10 +-
 src/host/usbh.h          |   1 +
 src/portable/ehci/ehci.c | 200 ++++++++++++++++++++++++---------------
 src/portable/ehci/ehci.h |  19 ++--
 6 files changed, 147 insertions(+), 86 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 957491aa9..b3d9fc7cd 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -53,6 +53,8 @@
 #define U32_TO_U8S_LE(_u32)   TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32)
 
 #define TU_BIT(n)             (1UL << (n))
+
+// Generate a mask with bit from high (31) to low (0) set, e.g TU_GENMASK(3, 0) = 0b1111
 #define TU_GENMASK(h, l)      ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) )
 
 //--------------------------------------------------------------------+
diff --git a/src/host/hcd.h b/src/host/hcd.h
index cbfffb349..90bfd79db 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -172,6 +172,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
 
 // Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
 bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 
 // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
diff --git a/src/host/usbh.c b/src/host/usbh.c
index bbf333d5f..15c48be47 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -718,9 +718,15 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) {
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
   // skip if not busy
-  if (!dev->ep_status[epnum][dir].busy) return true;
+  TU_VERIFY(dev->ep_status[epnum][dir].busy);
 
-  return hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr);
+  bool const ret = hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr);
+  if (ret) {
+    // mark as ready if transfer is aborted
+    dev->ep_status[epnum][dir].busy = false;
+  }
+
+  return ret;
 }
 
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh.h b/src/host/usbh.h
index d765f6744..0d56f40c9 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -176,6 +176,7 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer);
 bool tuh_edpt_open(uint8_t daddr, tusb_desc_endpoint_t const * desc_ep);
 
 // Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
 bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr);
 
 // Set Configuration (control transfer)
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 0a26986d5..6388add08 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -48,8 +48,8 @@
 #ifdef TUP_USBIP_CHIPIDEA_HS
   // NXP Transdimension: 8 elements
   #define FRAMELIST_SIZE_BIT_VALUE      7u
-  #define FRAMELIST_SIZE_USBCMD_VALUE   (((FRAMELIST_SIZE_BIT_VALUE &  3) << EHCI_USBCMD_POS_FRAMELIST_SIZE) | \
-                                         ((FRAMELIST_SIZE_BIT_VALUE >> 2) << EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB))
+  #define FRAMELIST_SIZE_USBCMD_VALUE   (((FRAMELIST_SIZE_BIT_VALUE &  3) << EHCI_USBCMD_FRAMELIST_SIZE_SHIFT) | \
+                                         ((FRAMELIST_SIZE_BIT_VALUE >> 2) << EHCI_USBCMD_CHIPIDEA_FRAMELIST_SIZE_MSB_SHIFT))
 #else
   // STD EHCI: 256 elements
   #define FRAMELIST_SIZE_BIT_VALUE      2u
@@ -132,24 +132,46 @@ TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) { (void
 TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; }
 TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { (void) addr; (void) data_size; }
 
-TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms);
-TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport);
-
 TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr);
 TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_next (ehci_qhd_t const * p_qhd);
 TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_find_free (void);
 static ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr);
 static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
 static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd);
+static void qhd_remove_qtd(ehci_qhd_t *qhd);
 
 TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr);
 TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_find_free (void);
 static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes);
 
-static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
-static inline ehci_link_t* list_next (ehci_link_t const *p_link);
+TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms);
+TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport);
+TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
+TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next (ehci_link_t const *p_link);
 static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr);
 
+static void ehci_disable_schedule(ehci_registers_t* regs, bool is_period) {
+  // maybe have a timeout for status
+  if (is_period) {
+    regs->command_bm.periodic_enable = 0;
+    while(regs->status_bm.periodic_status) {}
+  } else {
+    regs->command_bm.async_enable = 0;
+    while(regs->status_bm.async_status) {} // should have a timeout
+  }
+}
+
+static void ehci_enable_schedule(ehci_registers_t* regs, bool is_period) {
+  // maybe have a timeout for status
+  if (is_period) {
+    regs->command_bm.periodic_enable = 1;
+    while ( 0 == regs->status_bm.periodic_status ) {}
+  } else {
+    regs->command_bm.async_enable = 1;
+    while( 0 == regs->status_bm.async_status ) {}
+  }
+}
+
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
@@ -204,43 +226,6 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport)
   return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed
 }
 
-static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) {
-  ehci_link_t* prev = list_head;
-
-  while (prev && !prev->terminate) {
-    ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev);
-
-    // done if loop back to head
-    if ( (uintptr_t) qhd == (uintptr_t) list_head) {
-      break;
-    }
-
-    if ( qhd->dev_addr == dev_addr ) {
-      // TODO deactivate all TD, wait for QHD to inactive before removal
-      prev->address = qhd->next.address;
-
-      // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller)
-      qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1);
-
-      if ( qhd->int_smask )
-      {
-        // period list queue element is guarantee to be free in the next frame (1 ms)
-        qhd->used = 0;
-      }else
-      {
-        // async list use async advance handshake
-        // mark as removing, will completely re-usable when async advance isr occurs
-        qhd->removing = 1;
-      }
-
-      hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
-      hcd_dcache_clean(prev, sizeof(ehci_qhd_t));
-    }else {
-      prev = list_next(prev);
-    }
-  }
-}
-
 // Close all opened endpoint belong to this device
 void hcd_device_close(uint8_t rhport, uint8_t daddr)
 {
@@ -347,8 +332,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   regs->nxp_tt_control = 0;
 
   //------------- USB CMD Register -------------//
-  regs->command |= TU_BIT(EHCI_USBCMD_POS_RUN_STOP) | TU_BIT(EHCI_USBCMD_POS_ASYNC_ENABLE) |
-                   TU_BIT(EHCI_USBCMD_POS_PERIOD_ENABLE) |  // TODO enable period list only there is int/iso endpoint
+  regs->command |= EHCI_USBCMD_RUN_STOP | EHCI_USBCMD_PERIOD_SCHEDULE_ENABLE | EHCI_USBCMD_ASYNC_SCHEDULE_ENABLE |
                    FRAMELIST_SIZE_USBCMD_VALUE;
 
   //------------- ConfigFlag Register (skip) -------------//
@@ -358,7 +342,7 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   if (ehci_data.cap_regs->hcsparams_bm.port_power_control) {
     // mask out all change bits since they are Write 1 to clear
     uint32_t portsc = (regs->portsc & ~EHCI_PORTSC_MASK_W1C);
-    portsc |= ECHI_PORTSC_MASK_PORT_POWER;
+    portsc |= EHCI_PORTSC_MASK_PORT_POWER;
 
     regs->portsc = portsc;
   }
@@ -455,20 +439,17 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  ehci_qhd_t* qhd;
+  ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr);
   ehci_qtd_t* qtd;
 
   if (epnum == 0) {
-    qhd = qhd_control(dev_addr);
     qtd = qtd_control(dev_addr);
-
     qtd_init(qtd, buffer, buflen);
 
     // first data toggle is always 1 (data & setup stage)
     qtd->data_toggle = 1;
     qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT;
   } else {
-    qhd = qhd_get_from_addr(dev_addr, ep_addr);
     qtd = qtd_find_free();
     TU_ASSERT(qtd);
 
@@ -491,20 +472,34 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 
 bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   (void) rhport;
-  (void) dev_addr;
-  (void) ep_addr;
 
-  return false;
+  // TODO ISO not supported yet
+  ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr);
+  ehci_qtd_t * volatile qtd = qhd->attached_qtd;
+  TU_VERIFY(qtd != NULL); // no queued transfer
 
-//  uint8_t const epnum = tu_edpt_number(ep_addr);
-//  ehci_qhd_t* qhd;
-//
-//  // TODO ISO not supported
-//  if (epnum == 0) {
-//    qhd = qhd_control(dev_addr);
-//  }else {
-//    qhd = qhd_get_from_addr(dev_addr, ep_addr);
-//  }
+  hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
+  TU_VERIFY(qtd->active); // transfer is already complete
+
+  // HC is still processing, disable HC list schedule before making changes
+  bool const is_period = (qhd->interval_ms > 0);
+
+  ehci_disable_schedule(ehci_data.regs, is_period);
+
+  // check active bit again just in case HC has just processed the TD
+  bool const still_active = qtd->active;
+  if (still_active) {
+    // remove TD from QH overlay
+    qhd->qtd_overlay.next.terminate = 1;
+    hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
+
+    // remove TD from QH software list
+    qhd_remove_qtd(qhd);
+  }
+
+  ehci_enable_schedule(ehci_data.regs, is_period);
+
+  return still_active; // true if removed an active transfer
 }
 
 bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr)
@@ -554,8 +549,12 @@ void port_connect_status_change_isr(uint8_t rhport)
 TU_ATTR_ALWAYS_INLINE static inline
 void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
   // examine TD attached to queue head
-  ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd;
-  if (qtd == NULL) return; // no TD attached
+  ehci_qtd_t * volatile qtd = qhd->attached_qtd;
+
+  if (qtd == NULL) {
+    return; // no TD attached
+  }
+
   hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
 
   // TD is still active, no need to process
@@ -572,9 +571,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
   }
 
   // remove and free TD before invoking callback
-  qhd->attached_qtd = NULL;
-  qhd->attached_buffer = 0;
-  qtd->used = 0; // free QTD
+  qhd_remove_qtd(qhd);
 
   // notify usbh
   uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir);
@@ -677,9 +674,7 @@ void qhd_xfer_error_isr(ehci_qhd_t * qhd)
     }
 
     // remove and free TD before invoking callback
-    qhd->attached_qtd = NULL;
-    qhd->attached_buffer = 0;
-    qtd->used = 0; // free QTD
+    qhd_remove_qtd(qhd);
 
     if (0 == qhd->ep_number ) {
       // control cannot be halted
@@ -822,18 +817,55 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhpo
   return qhd_control(0); // control qhd of dev0 is used as async head
 }
 
-// insert at head
-static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type)
+TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next(ehci_link_t const *p_link) {
+  return (ehci_link_t*) tu_align32(p_link->address);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type)
 {
   new->address = current->address;
   current->address = ((uint32_t) new) | (new_type << 1);
 }
 
-static inline ehci_link_t* list_next(ehci_link_t const *p_link)
-{
-  return (ehci_link_t*) tu_align32(p_link->address);
+// Remove all queue head belong to this device address
+static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) {
+  ehci_link_t* prev = list_head;
+
+  while (prev && !prev->terminate) {
+    ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev);
+
+    // done if loop back to head
+    if ( (uintptr_t) qhd == (uintptr_t) list_head) {
+      break;
+    }
+
+    if ( qhd->dev_addr == dev_addr ) {
+      // TODO deactivate all TD, wait for QHD to inactive before removal
+      prev->address = qhd->next.address;
+
+      // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller)
+      qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1);
+
+      if ( qhd->int_smask )
+      {
+        // period list queue element is guarantee to be free in the next frame (1 ms)
+        qhd->used = 0;
+      }else
+      {
+        // async list use async advance handshake
+        // mark as removing, will completely re-usable when async advance isr occurs
+        qhd->removing = 1;
+      }
+
+      hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
+      hcd_dcache_clean(prev, sizeof(ehci_qhd_t));
+    }else {
+      prev = list_next(prev);
+    }
+  }
 }
 
+
 //--------------------------------------------------------------------+
 // Queue Header helper
 //--------------------------------------------------------------------+
@@ -856,8 +888,12 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_next(ehci_qhd_t const *p_qhd
   return (ehci_qhd_t *) tu_align32(p_qhd->next.address);
 }
 
-// Get queue head from address
+// Get queue head from device + endpoint address
 static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) {
+  if ( 0 == tu_edpt_number(ep_addr) ) {
+    return qhd_control(dev_addr);
+  }
+
   ehci_qhd_t *qhd_pool = ehci_data.qhd_pool;
 
   for ( uint32_t i = 0; i < QHD_MAX; i++ ) {
@@ -957,6 +993,16 @@ static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd) {
   hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
 }
 
+// Remove an attached TD from queue head
+static void qhd_remove_qtd(ehci_qhd_t *qhd) {
+  ehci_qtd_t * volatile qtd = qhd->attached_qtd;
+
+  qhd->attached_qtd = NULL;
+  qhd->attached_buffer = 0;
+
+  qtd->used = 0; // free QTD
+}
+
 //--------------------------------------------------------------------+
 // Queue TD helper
 //--------------------------------------------------------------------+
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index 8338fb419..05de80539 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -289,12 +289,17 @@ enum {
 };
 
 enum {
-  EHCI_USBCMD_POS_RUN_STOP               = 0,
-  EHCI_USBCMD_POS_FRAMELIST_SIZE         = 2,
-  EHCI_USBCMD_POS_PERIOD_ENABLE          = 4,
-  EHCI_USBCMD_POS_ASYNC_ENABLE           = 5,
-  EHCI_USBCMD_POS_NXP_FRAMELIST_SIZE_MSB = 15,
-  EHCI_USBCMD_POS_INTERRUPT_THRESHOLD    = 16
+  EHCI_USBCMD_FRAMELIST_SIZE_SHIFT              = 2, // [2..3]
+  EHCI_USBCMD_CHIPIDEA_FRAMELIST_SIZE_MSB_SHIFT = 15,
+  EHCI_USBCMD_INTERRUPT_THRESHOLD_SHIFT         = 16
+};
+
+enum {
+  EHCI_USBCMD_RUN_STOP                       = TU_BIT(0), // [0..0] 1 = Run, 0 = Stop
+  EHCI_USBCMD_HCRESET                        = TU_BIT(1), // [1..1] SW write 1 to reset HC, clear by HC when complete
+  EHCI_USBCMD_PERIOD_SCHEDULE_ENABLE         = TU_BIT(4), // [4..4] Enable periodic schedule
+  EHCI_USBCMD_ASYNC_SCHEDULE_ENABLE          = TU_BIT(5), // [5..5] Enable async schedule
+  EHCI_USBCMD_INTR_ON_ASYNC_ADVANCE_DOORBELL = TU_BIT(6), // [6..6] Tell HC to interrupt next time it advances async list. Clear by HC
 };
 
 enum {
@@ -306,7 +311,7 @@ enum {
   EHCI_PORTSC_MASK_FORCE_RESUME           = TU_BIT(6),
   EHCI_PORTSC_MASK_PORT_SUSPEND           = TU_BIT(7),
   EHCI_PORTSC_MASK_PORT_RESET             = TU_BIT(8),
-  ECHI_PORTSC_MASK_PORT_POWER             = TU_BIT(12),
+  EHCI_PORTSC_MASK_PORT_POWER             = TU_BIT(12),
 
   EHCI_PORTSC_MASK_W1C =
     EHCI_PORTSC_MASK_CONNECT_STATUS_CHANGE |

From a268e0b7a31a9b459913e29d04c7f576633f9078 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Jul 2023 15:18:41 +0700
Subject: [PATCH 1916/2085] add lpc40 to cmake

---
 .github/workflows/cmake_arm.yml               |  2 +-
 .idea/cmake.xml                               |  1 +
 .idea/runConfigurations/lpc4088.xml           | 10 ++
 .../boards/ea4088_quickstart/board.cmake      |  9 ++
 hw/bsp/lpc40/boards/ea4088_quickstart/board.h | 39 ++++++++
 .../lpc40/boards/ea4088_quickstart/board.mk   |  8 ++
 .../boards/ea4088_quickstart}/lpc4088.ld      |  0
 .../{ea4088qs/ea4088qs.c => lpc40/family.c}   |  7 +-
 hw/bsp/lpc40/family.cmake                     | 99 +++++++++++++++++++
 hw/bsp/{ea4088qs/board.mk => lpc40/family.mk} | 24 ++---
 10 files changed, 179 insertions(+), 20 deletions(-)
 create mode 100644 .idea/runConfigurations/lpc4088.xml
 create mode 100644 hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake
 create mode 100644 hw/bsp/lpc40/boards/ea4088_quickstart/board.h
 create mode 100644 hw/bsp/lpc40/boards/ea4088_quickstart/board.mk
 rename hw/bsp/{ea4088qs => lpc40/boards/ea4088_quickstart}/lpc4088.ld (100%)
 rename hw/bsp/{ea4088qs/ea4088qs.c => lpc40/family.c} (97%)
 create mode 100644 hw/bsp/lpc40/family.cmake
 rename hw/bsp/{ea4088qs/board.mk => lpc40/family.mk} (78%)

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 4d8cd5591..276360650 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -35,7 +35,7 @@ jobs:
           # Alphabetical order
           - 'imxrt'
           - 'kinetis_kl'
-          - 'lpc18'
+          - 'lpc18 lpc40'
           - 'lpc55'
           - 'mcx'
           - 'ra'
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 788f70433..a4f9d7f6d 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -48,6 +48,7 @@
       <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="rt1050 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1050_evkb -DLOG=1 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc4088.xml b/.idea/runConfigurations/lpc4088.xml
new file mode 100644
index 000000000..89226ac30
--- /dev/null
+++ b/.idea/runConfigurations/lpc4088.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="lpc4088" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc4088&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ea4088 quickstart" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake b/hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake
new file mode 100644
index 000000000..7f281d5f6
--- /dev/null
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE LPC4088)
+set(PYOCD_TARGET LPC4088)
+set(NXPLINK_DEVICE LPC4088:LPC4088)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc4088.ld)
+
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.h b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h
new file mode 100644
index 000000000..20e5bdf7f
--- /dev/null
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h
@@ -0,0 +1,39 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef EA4088QS__BOARD_H
+#define EA4088QS__BOARD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.mk b/hw/bsp/lpc40/boards/ea4088_quickstart/board.mk
new file mode 100644
index 000000000..d0bb4fe8c
--- /dev/null
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.mk
@@ -0,0 +1,8 @@
+
+LD_FILE = $(BOARD_PATH)/lpc4088.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC4088
+
+# flash using jlink
+flash: flash-jlink
diff --git a/hw/bsp/ea4088qs/lpc4088.ld b/hw/bsp/lpc40/boards/ea4088_quickstart/lpc4088.ld
similarity index 100%
rename from hw/bsp/ea4088qs/lpc4088.ld
rename to hw/bsp/lpc40/boards/ea4088_quickstart/lpc4088.ld
diff --git a/hw/bsp/ea4088qs/ea4088qs.c b/hw/bsp/lpc40/family.c
similarity index 97%
rename from hw/bsp/ea4088qs/ea4088qs.c
rename to hw/bsp/lpc40/family.c
index ace72fef0..3ea49d497 100644
--- a/hw/bsp/ea4088qs/ea4088qs.c
+++ b/hw/bsp/lpc40/family.c
@@ -25,7 +25,8 @@
  */
 
 #include "chip.h"
-#include "../board.h"
+#include "bsp/board.h"
+#include "board.h"
 
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
@@ -49,6 +50,8 @@ void USB_IRQHandler(void)
 
 #define BUTTON_PORT   2
 #define BUTTON_PIN    10
+#define BUTTON_ACTIV_STATE 0
+
 
 /* System oscillator rate and RTC oscillator rate */
 const uint32_t OscRateIn = 12000000;
@@ -159,7 +162,7 @@ void board_led_write(bool state)
 uint32_t board_button_read(void)
 {
   // active low
-  return Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
+  return BUTTON_ACTIV_STATE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
 }
 
 int board_uart_read(uint8_t* buf, int len)
diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake
new file mode 100644
index 000000000..03caa4385
--- /dev/null
+++ b/hw/bsp/lpc40/family.cmake
@@ -0,0 +1,99 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC18XX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/../gcc/cr_startup_lpc40xx.c
+    ${SDK_DIR}/src/chip_17xx_40xx.c
+    ${SDK_DIR}/src/clock_17xx_40xx.c
+    ${SDK_DIR}/src/fpu_init.c
+    ${SDK_DIR}/src/gpio_17xx_40xx.c
+    ${SDK_DIR}/src/iocon_17xx_40xx.c
+    ${SDK_DIR}/src/sysctl_17xx_40xx.c
+    ${SDK_DIR}/src/sysinit_17xx_40xx.c
+    ${SDK_DIR}/src/uart_17xx_40xx.c
+    )
+  target_compile_options(${BOARD_TARGET} PUBLIC
+    -nostdlib
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    CORE_M4
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+endfunction()
diff --git a/hw/bsp/ea4088qs/board.mk b/hw/bsp/lpc40/family.mk
similarity index 78%
rename from hw/bsp/ea4088qs/board.mk
rename to hw/bsp/lpc40/family.mk
index e1e14b717..47d25b885 100644
--- a/hw/bsp/ea4088qs/board.mk
+++ b/hw/bsp/lpc40/family.mk
@@ -1,12 +1,11 @@
 DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
 
+MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
+include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= cortex-m4
+
 CFLAGS += \
   -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
   -nostdlib \
   -DCORE_M4 \
   -D__USE_LPCOPEN \
@@ -17,31 +16,22 @@ CFLAGS += \
 # mcu driver cause following warnings
 CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual
 
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc40xx/lpc_chip_40xx
-
 # All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc4088.ld
-
 SRC_C += \
 	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc40xx.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
 	$(MCU_DIR)/src/clock_17xx_40xx.c \
+	$(MCU_DIR)/src/fpu_init.c \
 	$(MCU_DIR)/src/gpio_17xx_40xx.c \
 	$(MCU_DIR)/src/iocon_17xx_40xx.c \
 	$(MCU_DIR)/src/sysctl_17xx_40xx.c \
 	$(MCU_DIR)/src/sysinit_17xx_40xx.c \
 	$(MCU_DIR)/src/uart_17xx_40xx.c \
-	$(MCU_DIR)/src/fpu_init.c
 
 INC += \
-	$(TOP)/$(MCU_DIR)/inc
+	$(TOP)/$(MCU_DIR)/inc \
+	$(TOP)/$(BOARD_PATH)
 
 # For freeRTOS port source
 FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4088
-
-# flash using jlink
-flash: flash-jlink

From ef49b93532a7360703ae87d36cf463169f86f20b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Jul 2023 15:46:21 +0700
Subject: [PATCH 1917/2085] rename CFG_TUSB_MEM_SECTION to CFG_TUD_MEM_SECTION
 in device stack

CFG_TUD_MEM_SECTION is default to CFG_TUSB_MEM_SECTION
---
 hw/bsp/lpc40/family.cmake                     |  1 +
 hw/bsp/lpc40/family.mk                        |  3 +-
 lib/networking/rndis_reports.c                |  2 +-
 src/class/audio/audio_device.c                | 44 +++++++++----------
 src/class/bth/bth_device.c                    |  2 +-
 src/class/cdc/cdc_device.c                    |  2 +-
 src/class/dfu/dfu_device.c                    |  2 +-
 src/class/hid/hid_device.c                    |  2 +-
 src/class/midi/midi_device.c                  |  2 +-
 src/class/msc/msc_device.c                    |  4 +-
 src/class/net/ecm_rndis_device.c              | 12 ++---
 src/class/net/ncm_device.c                    |  6 +--
 src/class/usbtmc/usbtmc_device.c              |  2 +-
 src/class/vendor/vendor_device.c              |  2 +-
 src/class/video/video_device.c                |  4 +-
 src/device/usbd_control.c                     |  2 +-
 src/portable/bridgetek/ft9xx/dcd_ft9xx.c      |  2 +-
 src/portable/chipidea/ci_fs/dcd_ci_fs.c       |  2 +-
 src/portable/chipidea/ci_hs/dcd_ci_hs.c       |  2 +-
 src/portable/microchip/pic/dcd_pic.c          |  2 +-
 src/portable/microchip/samx7x/dcd_samx7x.c    |  2 +-
 .../mindmotion/mm32/dcd_mm32f327x_otg.c       |  2 +-
 src/portable/nxp/khci/dcd_khci.c              |  2 +-
 src/portable/nxp/lpc17_40/dcd_lpc17_40.c      |  2 +-
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c  |  6 +--
 src/tusb_option.h                             | 42 +++++-------------
 26 files changed, 68 insertions(+), 88 deletions(-)

diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake
index 03caa4385..54410e1a7 100644
--- a/hw/bsp/lpc40/family.cmake
+++ b/hw/bsp/lpc40/family.cmake
@@ -38,6 +38,7 @@ function(add_board_target BOARD_TARGET)
   target_compile_definitions(${BOARD_TARGET} PUBLIC
     __USE_LPCOPEN
     CORE_M4
+    CFG_TUSB_MEM_SECTION=__attribute__\(\(section\(\".data.$RAM2\"\)\)\)
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${SDK_DIR}/inc
diff --git a/hw/bsp/lpc40/family.mk b/hw/bsp/lpc40/family.mk
index 47d25b885..0fc7095f5 100644
--- a/hw/bsp/lpc40/family.mk
+++ b/hw/bsp/lpc40/family.mk
@@ -9,8 +9,7 @@ CFLAGS += \
   -nostdlib \
   -DCORE_M4 \
   -D__USE_LPCOPEN \
-  -DCFG_TUD_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
-  -DCFG_TUH_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
+  -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
   -DCFG_TUSB_MCU=OPT_MCU_LPC40XX
 
 # mcu driver cause following warnings
diff --git a/lib/networking/rndis_reports.c b/lib/networking/rndis_reports.c
index cc14f174c..60afb8615 100644
--- a/lib/networking/rndis_reports.c
+++ b/lib/networking/rndis_reports.c
@@ -43,7 +43,7 @@ static usb_eth_stat_t usb_eth_stat = { 0, 0, 0, 0 };
 static uint32_t oid_packet_filter = 0x0000000;
 static rndis_state_t rndis_state;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t ndis_report[8] = { 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t ndis_report[8] = { 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
 
 static const uint32_t OIDSupportedList[] =
 {
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index e5dbe988a..1a7ce7870 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -113,21 +113,21 @@
 // EP IN software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
   #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_in_ff_mutex_wr_1; // No need for read mutex as only USB driver reads from FIFO
     #endif
   #endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_in_ff_mutex_wr_2; // No need for read mutex as only USB driver reads from FIFO
     #endif
   #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_in_ff_mutex_wr_3; // No need for read mutex as only USB driver reads from FIFO
     #endif
@@ -139,36 +139,36 @@
 // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING)
   #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX];
   #endif
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SZ_MAX];
   #endif
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_in_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX];
   #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 
 // EP OUT software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
   #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_out_ff_mutex_rd_1; // No need for write mutex as only USB driver writes into FIFO
     #endif
   #endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_out_ff_mutex_rd_2; // No need for write mutex as only USB driver writes into FIFO
     #endif
   #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_out_ff_mutex_rd_3; // No need for write mutex as only USB driver writes into FIFO
     #endif
@@ -180,27 +180,27 @@
 // - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
   #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX];
   #endif
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX];
   #endif
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t lin_buf_out_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX];
   #endif
 #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING)
 
 // Control buffers
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ];
 
 #if CFG_TUD_AUDIO > 1
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ];
 #endif
 
 #if CFG_TUD_AUDIO > 2
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ];
 #endif
 
 // Active alternate setting of interfaces
@@ -217,7 +217,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 // Software encoding/decoding support FIFOs
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
   #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
     tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
@@ -225,7 +225,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
     tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
@@ -233,7 +233,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
     tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
@@ -243,7 +243,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
   #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
     tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
@@ -251,7 +251,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
     tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
@@ -259,7 +259,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
+    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
     tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
@@ -416,7 +416,7 @@ typedef struct
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION audiod_function_t _audiod_fct[CFG_TUD_AUDIO];
+CFG_TUD_MEM_SECTION audiod_function_t _audiod_fct[CFG_TUD_AUDIO];
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT
 static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received);
diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c
index f96bb3552..c5c74d26a 100755
--- a/src/class/bth/bth_device.c
+++ b/src/class/bth/bth_device.c
@@ -55,7 +55,7 @@ typedef struct
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION btd_interface_t _btd_itf;
+CFG_TUD_MEM_SECTION btd_interface_t _btd_itf;
 
 static bool bt_tx_data(uint8_t ep, void *data, uint16_t len)
 {
diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 5adce521d..f658df4d0 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -76,7 +76,7 @@ typedef struct
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION tu_static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
+CFG_TUD_MEM_SECTION tu_static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
 
 static bool _prep_out_transaction (cdcd_interface_t* p_cdc)
 {
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index 464c4bd6b..bffdb8376 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -56,7 +56,7 @@ typedef struct
 } dfu_state_ctx_t;
 
 // Only a single dfu state is allowed
-CFG_TUSB_MEM_SECTION tu_static dfu_state_ctx_t _dfu_ctx;
+CFG_TUD_MEM_SECTION tu_static dfu_state_ctx_t _dfu_ctx;
 
 static void reset_state(void)
 {
diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c
index 9240fe2ca..5637ea6b4 100644
--- a/src/class/hid/hid_device.c
+++ b/src/class/hid/hid_device.c
@@ -58,7 +58,7 @@ typedef struct
   tusb_hid_descriptor_hid_t const * hid_descriptor;
 } hidd_interface_t;
 
-CFG_TUSB_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID];
+CFG_TUD_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID];
 
 /*------------- Helpers -------------*/
 static inline uint8_t get_index_by_itfnum(uint8_t itf_num)
diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c
index e3e7826da..052372a93 100644
--- a/src/class/midi/midi_device.c
+++ b/src/class/midi/midi_device.c
@@ -82,7 +82,7 @@ typedef struct
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION midid_interface_t _midid_itf[CFG_TUD_MIDI];
+CFG_TUD_MEM_SECTION midid_interface_t _midid_itf[CFG_TUD_MIDI];
 
 bool tud_midi_n_mounted (uint8_t itf)
 {
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index a409c4e27..a602e9672 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -74,8 +74,8 @@ typedef struct
   uint8_t add_sense_qualifier;
 }mscd_interface_t;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static mscd_interface_t _mscd_itf;
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE];
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static mscd_interface_t _mscd_itf;
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE];
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c
index 8ac7cbd01..762425732 100644
--- a/src/class/net/ecm_rndis_device.c
+++ b/src/class/net/ecm_rndis_device.c
@@ -61,10 +61,10 @@ typedef struct
 #define CFG_TUD_NET_PACKET_PREFIX_LEN sizeof(rndis_data_packet_t)
 #define CFG_TUD_NET_PACKET_SUFFIX_LEN 0
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static
 uint8_t received[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static
 uint8_t transmitted[CFG_TUD_NET_PACKET_PREFIX_LEN + CFG_TUD_NET_MTU + CFG_TUD_NET_PACKET_PREFIX_LEN];
 
 struct ecm_notify_struct
@@ -94,8 +94,8 @@ tu_static const struct ecm_notify_struct ecm_notify_csc =
   .uplink = 9728000,
 };
 
-// TODO remove CFG_TUSB_MEM_SECTION, control internal buffer is already in this special section
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static union
+// TODO remove CFG_TUD_MEM_SECTION, control internal buffer is already in this special section
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static union
 {
   uint8_t rndis_buf[120];
   struct ecm_notify_struct ecm_buf;
@@ -104,8 +104,8 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static union
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-// TODO remove CFG_TUSB_MEM_SECTION
-CFG_TUSB_MEM_SECTION tu_static netd_interface_t _netd_itf;
+// TODO remove CFG_TUD_MEM_SECTION
+CFG_TUD_MEM_SECTION tu_static netd_interface_t _netd_itf;
 
 tu_static bool can_xmit;
 
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 9e9580249..611dc3348 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -130,7 +130,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = {
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = {
     .wLength                 = sizeof(ntb_parameters_t),
     .bmNtbFormatsSupported   = 0x01,
     .dwNtbInMaxSize          = CFG_TUD_NCM_IN_NTB_MAX_SIZE,
@@ -145,9 +145,9 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static const ntb_parameters_t ntb_par
     .wNtbOutMaxDatagrams     = 0
 };
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static transmit_ntb_t transmit_ntb[2];
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static transmit_ntb_t transmit_ntb[2];
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t receive_ntb[CFG_TUD_NCM_OUT_NTB_MAX_SIZE];
 
 tu_static ncm_interface_t ncm_interface;
 
diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c
index 4e320a778..573654d58 100644
--- a/src/class/usbtmc/usbtmc_device.c
+++ b/src/class/usbtmc/usbtmc_device.c
@@ -143,7 +143,7 @@ typedef struct
   usbtmc_capabilities_specific_t const * capabilities;
 } usbtmc_interface_state_t;
 
-CFG_TUSB_MEM_SECTION tu_static usbtmc_interface_state_t usbtmc_state =
+CFG_TUD_MEM_SECTION tu_static usbtmc_interface_state_t usbtmc_state =
 {
     .itf_id = 0xFF,
 };
diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c
index 93596ee33..389a29696 100644
--- a/src/class/vendor/vendor_device.c
+++ b/src/class/vendor/vendor_device.c
@@ -59,7 +59,7 @@ typedef struct
   CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_VENDOR_EPSIZE];
 } vendord_interface_t;
 
-CFG_TUSB_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
+CFG_TUD_MEM_SECTION tu_static vendord_interface_t _vendord_itf[CFG_TUD_VENDOR];
 
 #define ITF_MEM_RESET_SIZE   offsetof(vendord_interface_t, rx_ff)
 
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index 91f452afc..e6fadf41b 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -130,8 +130,8 @@ typedef struct TU_ATTR_PACKED {
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
-CFG_TUSB_MEM_SECTION tu_static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
-CFG_TUSB_MEM_SECTION tu_static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
+CFG_TUD_MEM_SECTION tu_static videod_interface_t _videod_itf[CFG_TUD_VIDEO];
+CFG_TUD_MEM_SECTION tu_static videod_streaming_interface_t _videod_streaming_itf[CFG_TUD_VIDEO_STREAMING];
 
 tu_static uint8_t const _cap_get     = 0x1u; /* support for GET */
 tu_static uint8_t const _cap_get_set = 0x3u; /* support for GET and SET */
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index c580e6ecf..76d062e40 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -55,7 +55,7 @@ typedef struct
 
 tu_static usbd_control_xfer_t _ctrl_xfer;
 
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN
 tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
index 95dfda49c..f02415904 100644
--- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
+++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c
@@ -51,7 +51,7 @@ extern int8_t board_ft9xx_vbus(void);
 extern int board_uart_write(void const *buf, int len);
 
 // Static array to store an incoming SETUP request for processing by tinyusb.
-CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
+CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN
 static uint8_t _ft9xx_setup_packet[8];
 
 struct ft9xx_xfer_state
diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
index 37265df8b..9327e09d8 100644
--- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c
+++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c
@@ -116,7 +116,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
 
 TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
 
diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
index f50550d33..f9ec666e5 100644
--- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c
@@ -175,7 +175,7 @@ typedef struct {
   dcd_qtd_t qtd[TUP_DCD_ENDPOINT_MAX][2] TU_ATTR_ALIGNED(32);
 }dcd_data_t;
 
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(2048)
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(2048)
 static dcd_data_t _dcd_data;
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c
index 6986c8317..ccc27c3c9 100644
--- a/src/portable/microchip/pic/dcd_pic.c
+++ b/src/portable/microchip/pic/dcd_pic.c
@@ -189,7 +189,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) volatile static dcd_data_t _dcd;
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) volatile static dcd_data_t _dcd;
 
 #if TU_PIC_INT_SIZE == 4
 TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c
index 2bbb345d6..9586df84d 100644
--- a/src/portable/microchip/samx7x/dcd_samx7x.c
+++ b/src/portable/microchip/samx7x/dcd_samx7x.c
@@ -77,7 +77,7 @@ static tusb_speed_t get_speed(void);
 static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix);
 
 // DMA descriptors shouldn't be placed in ITCM !
-CFG_TUSB_MEM_SECTION static dma_desc_t dma_desc[6];
+CFG_TUD_MEM_SECTION static dma_desc_t dma_desc[6];
 
 static xfer_ctl_t xfer_status[EP_MAX];
 
diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
index 39b09db68..c3d0c7297 100644
--- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
+++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c
@@ -110,7 +110,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
 
 TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
 
diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c
index 52f4145f2..5c65ea33d 100644
--- a/src/portable/nxp/khci/dcd_khci.c
+++ b/src/portable/nxp/khci/dcd_khci.c
@@ -114,7 +114,7 @@ typedef struct
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 // BDT(Buffer Descriptor Table) must be 256-byte aligned
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
 
 TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
 
diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
index 86149afd8..b880c2870 100644
--- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
@@ -92,7 +92,7 @@ typedef struct
 
 } dcd_data_t;
 
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(128) static dcd_data_t _dcd;
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(128) static dcd_data_t _dcd;
 
 
 //--------------------------------------------------------------------+
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 5368ef868..7ca698a93 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -176,11 +176,11 @@ typedef struct
 // EP list must be 256-byte aligned
 //    Some MCU controller may require this variable to be placed in specific SRAM region.
 //    For example: LPC55s69 port1 Highspeed must be USB_RAM (0x40100000)
-//    Use CFG_TUSB_MEM_SECTION to place it accordingly.
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
+//    Use CFG_TUD_MEM_SECTION to place it accordingly.
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
 
 // Dummy buffer to fix ZLPs overwriting the buffer (probably an USB/DMA controller bug)
-CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
+CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
 
 //--------------------------------------------------------------------+
 // Multiple Controllers
diff --git a/src/tusb_option.h b/src/tusb_option.h
index c792efe6a..7a4cfe51c 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -295,15 +295,14 @@
   #define CFG_TUSB_DEBUG 0
 #endif
 
-// TODO MEM_SECTION can be different for host and device controller
-// should use CFG_TUD_MEM_SECTION, CFG_TUH_MEM_SECTION
+// Memory section for placing buffer used for usb transferring. If MEM_SECTION is different for
+// host and device use: CFG_TUD_MEM_SECTION, CFG_TUH_MEM_SECTION instead
 #ifndef CFG_TUSB_MEM_SECTION
   #define CFG_TUSB_MEM_SECTION
 #endif
 
-// alignment requirement of buffer used for endpoint transferring
-// TODO MEM_ALIGN can be different for host and device controller
-// should use CFG_TUD_MEM_ALIGN, CFG_TUH_MEM_ALIGN
+// Alignment requirement of buffer used for usb transferring. if MEM_ALIGN is different for
+// host and device controller use: CFG_TUD_MEM_ALIGN, CFG_TUH_MEM_ALIGN instead
 #ifndef CFG_TUSB_MEM_ALIGN
   #define CFG_TUSB_MEM_ALIGN      TU_ATTR_ALIGNED(4)
 #endif
@@ -321,24 +320,14 @@
 // Device Options (Default)
 //--------------------------------------------------------------------
 
-// Attribute to place data in accessible RAM for device controller
-// default to CFG_TUSB_MEM_SECTION for backward-compatible
+// Attribute to place data in accessible RAM for device controller (default: CFG_TUSB_MEM_SECTION)
 #ifndef CFG_TUD_MEM_SECTION
-  #ifdef CFG_TUSB_MEM_SECTION
-    #define CFG_TUD_MEM_SECTION   CFG_TUSB_MEM_SECTION
-  #else
-    #define CFG_TUD_MEM_SECTION
-  #endif
+  #define CFG_TUD_MEM_SECTION     CFG_TUSB_MEM_SECTION
 #endif
 
-// Attribute to align memory for device controller
-// default to CFG_TUSB_MEM_ALIGN for backward-compatible
+// Attribute to align memory for device controller (default: CFG_TUSB_MEM_ALIGN)
 #ifndef CFG_TUD_MEM_ALIGN
-  #ifdef CFG_TUSB_MEM_ALIGN
-    #define CFG_TUD_MEM_ALIGN   CFG_TUSB_MEM_ALIGN
-  #else
-    #define CFG_TUD_MEM_ALIGN   TU_ATTR_ALIGNED(4)
-  #endif
+  #define CFG_TUD_MEM_ALIGN       CFG_TUSB_MEM_ALIGN
 #endif
 
 #ifndef CFG_TUD_ENDPOINT0_SIZE
@@ -419,23 +408,14 @@
   #endif
 #endif // CFG_TUH_ENABLED
 
-// Attribute to place data in accessible RAM for host controller
-// default to CFG_TUSB_MEM_SECTION for backward-compatible
+// Attribute to place data in accessible RAM for host controller (default: CFG_TUSB_MEM_SECTION)
 #ifndef CFG_TUH_MEM_SECTION
-  #ifdef CFG_TUSB_MEM_SECTION
-    #define CFG_TUH_MEM_SECTION   CFG_TUSB_MEM_SECTION
-  #else
-    #define CFG_TUH_MEM_SECTION
-  #endif
+  #define CFG_TUH_MEM_SECTION   CFG_TUSB_MEM_SECTION
 #endif
 
 // Attribute to align memory for host controller
 #ifndef CFG_TUH_MEM_ALIGN
-  #ifdef CFG_TUSB_MEM_ALIGN
-    #define CFG_TUH_MEM_ALIGN   CFG_TUSB_MEM_ALIGN
-  #else
-    #define CFG_TUH_MEM_ALIGN   TU_ATTR_ALIGNED(4)
-  #endif
+  #define CFG_TUH_MEM_ALIGN     CFG_TUSB_MEM_ALIGN
 #endif
 
 //------------- CLASS -------------//

From 210fc7d038f6acf07d806c1cfab077123709b6b5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Jul 2023 16:19:45 +0700
Subject: [PATCH 1918/2085] add etm trace pinmux for 4088 quickstart

---
 hw/bsp/lpc40/boards/ea4088_quickstart/board.h |  35 +++
 .../ozone/ea4088_quickstart.jdebug            | 238 ++++++++++++++++++
 hw/bsp/lpc40/family.c                         | 112 +++------
 3 files changed, 311 insertions(+), 74 deletions(-)
 create mode 100644 hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug

diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.h b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h
index 20e5bdf7f..d5489c154 100644
--- a/hw/bsp/lpc40/boards/ea4088_quickstart/board.h
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h
@@ -31,6 +31,41 @@
 extern "C" {
 #endif
 
+#define LED_PORT      2
+#define LED_PIN       19
+
+#define BUTTON_PORT   2
+#define BUTTON_PIN    10
+#define BUTTON_ACTIV_STATE 0
+
+/* System oscillator rate and RTC oscillator rate */
+const uint32_t OscRateIn = 12000000;
+const uint32_t RTCOscRateIn = 32768;
+
+/* Pin muxing configuration */
+static const PINMUX_GRP_T pinmuxing[] = {
+    // LED
+    { 2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT) },
+
+    // Button
+    { 2, 10, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_MODE_PULLUP) },
+
+    // USB1 as Host
+    { 0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // D+1
+    { 0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // D-1
+    { 1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // UP LED1
+    { 1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT) }, // PPWR1
+//  {2, 14, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // VBUS1
+//  {2, 15, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // OVRCR1
+
+    // USB2 as Device
+    { 0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // D+2
+    { 0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT) }, // UP LED
+    { 0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT) }, // CONNECT2
+
+    /* VBUS is not connected on this board, so leave the pin at default setting. */
+    /*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
+};
 
 #ifdef __cplusplus
 }
diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug b/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug
new file mode 100644
index 000000000..6aaf1076d
--- /dev/null
+++ b/hw/bsp/lpc40/boards/ea4088_quickstart/ozone/ea4088_quickstart.jdebug
@@ -0,0 +1,238 @@
+
+/*********************************************************************
+*
+*       OnProjectLoad
+*
+* Function description
+*   Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+  Edit.SysVar (VAR_POWER_SAMPLING_SPEED, FREQ_100_KHZ);
+  Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M4F.svd");
+  Project.AddSvdFile ("../../../../../../../cmsis-svd/data/NXP/LPC408x_7x_v0.7.svd");
+
+  Project.SetDevice ("LPC4088");
+  Project.SetHostIF ("USB", "");
+  Project.SetTargetIF ("SWD");
+  Project.SetTIFSpeed ("50 MHz");
+  Project.SetTraceSource ("Trace Pins");
+  Project.SetTracePortWidth (4);
+
+  // User settings
+  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ea4088-quickstart/cdc_msc.elf");
+}
+
+/*********************************************************************
+*
+*      TargetReset
+*
+* Function description
+*   Replaces the default target device reset routine. Optional.
+*
+* Notes
+*   This example demonstrates the usage when
+*   debugging a RAM program on a Cortex-M target device
+*
+**********************************************************************
+*/
+//void TargetReset (void) {
+//
+//  unsigned int SP;
+//  unsigned int PC;
+//  unsigned int VectorTableAddr;
+//
+//  Exec.Reset();
+//
+//  VectorTableAddr = Elf.GetBaseAddr();
+//
+//  if (VectorTableAddr != 0xFFFFFFFF) {
+//
+//    Util.Log("Resetting Program.");
+//
+//    SP = Target.ReadU32(VectorTableAddr);
+//    Target.SetReg("SP", SP);
+//
+//    PC = Target.ReadU32(VectorTableAddr + 4);
+//    Target.SetReg("PC", PC);
+//  }
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetReset
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetReset (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetReset
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetReset (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       DebugStart
+*
+* Function description
+*   Replaces the default debug session startup routine. Optional.
+*
+**********************************************************************
+*/
+//void DebugStart (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetConnect
+*
+* Function description
+*   Replaces the default target IF connection routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+}
+
+/*********************************************************************
+*
+*       AfterTargetConnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+*       TargetDownload
+*
+* Function description
+*   Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*       BeforeTargetDownload
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+*      AfterTargetDownload
+*
+* Function description
+*   Event handler routine.
+*    - Sets the PC register to program reset value.
+*    - Sets the SP register to program reset value on Cortex-M.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+  unsigned int SP;
+  unsigned int PC;
+  unsigned int VectorTableAddr;
+
+  VectorTableAddr = Elf.GetBaseAddr();
+
+  if (VectorTableAddr == 0xFFFFFFFF) {
+    Util.Log("Project file error: failed to get program base");
+  } else {
+    SP = Target.ReadU32(VectorTableAddr);
+    Target.SetReg("SP", SP);
+
+    PC = Target.ReadU32(VectorTableAddr + 4);
+    Target.SetReg("PC", PC);
+  }
+}
+
+/*********************************************************************
+*
+*       BeforeTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetDisconnect
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+*       AfterTargetHalt
+*
+* Function description
+*   Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
diff --git a/hw/bsp/lpc40/family.c b/hw/bsp/lpc40/family.c
index 3ea49d497..829df4ac7 100644
--- a/hw/bsp/lpc40/family.c
+++ b/hw/bsp/lpc40/family.c
@@ -31,86 +31,54 @@
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   #if CFG_TUD_ENABLED
-    tud_int_handler(0);
+  tud_int_handler(0);
   #endif
 
   #if CFG_TUH_ENABLED
-    tuh_int_handler(0);
+  tuh_int_handler(0);
   #endif
 }
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
-#define LED_PORT      2
-#define LED_PIN       19
-
-#define BUTTON_PORT   2
-#define BUTTON_PIN    10
-#define BUTTON_ACTIV_STATE 0
-
-
-/* System oscillator rate and RTC oscillator rate */
-const uint32_t OscRateIn = 12000000;
-const uint32_t RTCOscRateIn = 32768;
-
-/* Pin muxing configuration */
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  // LED
-  {2, 19, (IOCON_FUNC0 | IOCON_MODE_INACT)},
-
-  // Button
-  {2, 10, (IOCON_FUNC0 | IOCON_MODE_INACT | IOCON_MODE_PULLUP)},
-};
-
-static const PINMUX_GRP_T pin_usb_mux[] =
-{
-  // USB1 as Host
-  {0, 29, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+1
-  {0, 30, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D-1
-  {1, 18, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED1
-  {1, 19, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // PPWR1
-//  {2, 14, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // VBUS1
-//  {2, 15, (IOCON_FUNC2 | IOCON_MODE_INACT)}, // OVRCR1
-
-  // USB2 as Device
-  {0, 31, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // D+2
-  {0, 13, (IOCON_FUNC1 | IOCON_MODE_INACT)}, // UP LED
-  {0, 14, (IOCON_FUNC3 | IOCON_MODE_INACT)}, // CONNECT2
-
-  /* VBUS is not connected on this board, so leave the pin at default setting. */
-  /*Chip_IOCON_PinMux(LPC_IOCON, 1, 30, IOCON_MODE_INACT, IOCON_FUNC2);*/ /* USB VBUS */
-};
 
 // Invoked by startup code
-void SystemInit(void)
-{
+void SystemInit(void) {
 #ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
+  extern void (*const g_pfnVectors[])(void);
   unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
+  *pSCB_VTOR = (unsigned int) g_pfnVectors;
 
-#if __FPU_USED == 1
-	fpuInit();
-#endif
+  #if __FPU_USED == 1
+  fpuInit();
+  #endif
 #endif // __USE_LPCOPEN
 
   Chip_IOCON_Init(LPC_IOCON);
   Chip_IOCON_SetPinMuxing(LPC_IOCON, pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
 
-	/* CPU clock source starts with IRC */
-	/* Enable PBOOST for CPU clock over 100MHz */
-	Chip_SYSCTL_EnableBoost();
+#ifdef TRACE_ETM
+  const PINMUX_GRP_T trace_pinmux[] = {
+      {2, 2, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+      {2, 3, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+      {2, 4, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+      {2, 5, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+      {2, 6, IOCON_FUNC5 | IOCON_FASTSLEW_EN },
+  };
+  Chip_IOCON_SetPinMuxing(LPC_IOCON, trace_pinmux, sizeof(trace_pinmux) / sizeof(PINMUX_GRP_T));
+#endif
+
+  /* CPU clock source starts with IRC */
+  /* Enable PBOOST for CPU clock over 100MHz */
+  Chip_SYSCTL_EnableBoost();
 
   Chip_SetupXtalClocking();
 }
 
-void board_init(void)
-{
+void board_init(void) {
   SystemCoreClockUpdate();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -132,15 +100,14 @@ void board_init(void)
   // UART
 
   //------------- USB -------------//
-  Chip_IOCON_SetPinMuxing(LPC_IOCON, pin_usb_mux, sizeof(pin_usb_mux) / sizeof(PINMUX_GRP_T));
 
   // Port1 as Host, Port2: Device
   Chip_USB_Init();
 
   enum {
     USBCLK_DEVCIE = 0x12, // AHB + Device
-    USBCLK_HOST = 0x19 ,  // AHB + OTG + Host
-    USBCLK_ALL  = 0x1B    // Host + Device + OTG + AHB
+    USBCLK_HOST = 0x19,  // AHB + OTG + Host
+    USBCLK_ALL = 0x1B    // Host + Device + OTG + AHB
   };
 
   LPC_USB->OTGClkCtrl = USBCLK_ALL;
@@ -154,40 +121,37 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   Chip_GPIO_SetPinState(LPC_GPIO, LED_PORT, LED_PIN, state);
 }
 
-uint32_t board_button_read(void)
-{
-  // active low
+uint32_t board_button_read(void) {
   return BUTTON_ACTIV_STATE == Chip_GPIO_GetPinState(LPC_GPIO, BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t *buf, int len) {
   //return UART_ReceiveByte(BOARD_UART_PORT);
-  (void) buf; (void) len;
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
   //UART_Send(BOARD_UART_PORT, &c, 1, BLOCKING);
-  (void) buf; (void) len;
+  (void) buf;
+  (void) len;
   return 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif

From 14a7379799418c6e8ffb7231ee1703a0f95665da Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Jul 2023 16:54:02 +0700
Subject: [PATCH 1919/2085] fix ohci warnings, and add freertosconfig for
 lpc4088

---
 hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h | 165 +++++++++++++++++++
 hw/bsp/lpc40/family.cmake                    |   2 +
 src/portable/ohci/ohci.c                     |  25 +--
 3 files changed, 182 insertions(+), 10 deletions(-)
 create mode 100644 hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h

diff --git a/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..96611ca1c
--- /dev/null
+++ b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "chip.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               2
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       5
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake
index 54410e1a7..56eb37a2f 100644
--- a/hw/bsp/lpc40/family.cmake
+++ b/hw/bsp/lpc40/family.cmake
@@ -88,6 +88,8 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
+    ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+    ${TOP}/src/portable/ohci/ohci.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 3f702d22c..27080836c 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -341,19 +341,24 @@ static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t ep_size, uint8_t
   p_ed->is_interrupt_xfer = (xfer_type == TUSB_XFER_INTERRUPT ? 1 : 0);
 }
 
-static void gtd_init(ohci_gtd_t* p_td, uint8_t* data_ptr, uint16_t total_bytes)
-{
+static void gtd_init(ohci_gtd_t *p_td, uint8_t *data_ptr, uint16_t total_bytes) {
   tu_memclr(p_td, sizeof(ohci_gtd_t));
 
-  p_td->used                   = 1;
-  p_td->expected_bytes         = total_bytes;
+  p_td->used = 1;
+  p_td->expected_bytes = total_bytes;
 
-  p_td->buffer_rounding        = 1; // less than queued length is not a error
-  p_td->delay_interrupt        = OHCI_INT_ON_COMPLETE_NO;
-  p_td->condition_code         = OHCI_CCODE_NOT_ACCESSED;
+  p_td->buffer_rounding = 1; // less than queued length is not a error
+  p_td->delay_interrupt = OHCI_INT_ON_COMPLETE_NO;
+  p_td->condition_code = OHCI_CCODE_NOT_ACCESSED;
 
-  p_td->current_buffer_pointer = _phys_addr(data_ptr);
-  p_td->buffer_end             = total_bytes ? (_phys_addr(data_ptr + total_bytes - 1)) : (uint8_t *)p_td->current_buffer_pointer;
+  uint8_t *cbp = (uint8_t *) _phys_addr(data_ptr);
+
+  p_td->current_buffer_pointer = cbp;
+  if ( total_bytes ) {
+    p_td->buffer_end = _phys_addr(data_ptr + total_bytes - 1);
+  } else {
+    p_td->buffer_end = cbp;
+  }
 }
 
 static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
@@ -487,7 +492,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   ohci_ed_t* ed   = &ohci_data.control[dev_addr].ed;
   ohci_gtd_t *qtd = &ohci_data.control[dev_addr].gtd;
 
-  gtd_init(qtd, (uint8_t*) setup_packet, 8);
+  gtd_init(qtd, (uint8_t*)(uintptr_t) setup_packet, 8);
   qtd->index           = dev_addr;
   qtd->pid             = PID_SETUP;
   qtd->data_toggle     = GTD_DT_DATA0;

From d2542560470de242dd8988d0b3c10d7df0496bb0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Jul 2023 17:54:24 +0700
Subject: [PATCH 1920/2085] change dcache clean/invalidate return type to bool

add tu_assert() check for aligned 32byte address for imxrt
---
 src/common/tusb_common.h                  | 13 +++++++------
 src/host/hcd.h                            |  8 ++++----
 src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 15 +++++++++------
 src/portable/chipidea/ci_hs/hcd_ci_hs.c   | 12 ++++++------
 src/portable/ehci/ehci.c                  |  9 ++++++---
 5 files changed, 32 insertions(+), 25 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 957491aa9..bae583c06 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -99,10 +99,9 @@ TU_ATTR_WEAK extern void* tusb_app_phys_to_virt(void *phys_addr);
 #define tu_varclr(_var)          tu_memclr(_var, sizeof(*(_var)))
 
 // This is a backport of memset_s from c11
-TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count)
-{
+TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count) {
   // TODO may check if desst and src is not NULL
-  if (count > destsz) {
+  if ( count > destsz ) {
     return -1;
   }
   memset(dest, ch, count);
@@ -110,10 +109,9 @@ TU_ATTR_ALWAYS_INLINE static inline int tu_memset_s(void *dest, size_t destsz, i
 }
 
 // This is a backport of memcpy_s from c11
-TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, const void * src, size_t count )
-{
+TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, const void *src, size_t count) {
   // TODO may check if desst and src is not NULL
-  if (count > destsz) {
+  if ( count > destsz ) {
     return -1;
   }
   memcpy(dest, src, count);
@@ -169,6 +167,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { retur
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); }
 
+TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned32(uint32_t value) { return (value & 0x1FUL) == 0; }
+TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned64(uint64_t value) { return (value & 0x3FUL) == 0; }
+
 //------------- Mathematics -------------//
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d -1)/d; }
 
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 3355c18b2..52fcc834e 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -104,21 +104,21 @@ typedef struct
   uint8_t speed;
 } hcd_devtree_info_t;
 
-//--------------------------------------------------------------------+
+//--------------------------------------------------------------
 // Memory API
 //--------------------------------------------------------------------+
 
 // clean/flush data cache: write cache -> memory.
 // Required before an DMA TX transfer to make sure data is in memory
-void hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
 
 // invalidate data cache: mark cache as invalid, next read will read from memory
 // Required BOTH before and after an DMA RX transfer
-void hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
 
 // clean and invalidate data cache
 // Required before an DMA transfer where memory is both read/write by DMA
-void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
+bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
 
 //--------------------------------------------------------------------+
 // Controller API
diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
index 96f0ba766..c59c107ff 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h
@@ -68,31 +68,34 @@ TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) {
   return !(0x20000000 <= addr && addr < 0x20100000);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean(void const* addr, uint32_t data_size) {
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean(void const* addr, uint32_t data_size) {
   const uintptr_t addr32 = (uintptr_t) addr;
   if (imxrt_is_cache_mem(addr32)) {
+    TU_ASSERT(tu_is_aligned32(addr32));
     SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
   }
+  return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_invalidate(void const* addr, uint32_t data_size) {
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_invalidate(void const* addr, uint32_t data_size) {
   const uintptr_t addr32 = (uintptr_t) addr;
   if (imxrt_is_cache_mem(addr32)) {
     // Invalidating does not push cached changes back to RAM so we need to be
     // *very* careful when we do it. If we're not aligned, then we risk resetting
     // values back to their RAM state.
-    // if (addr32 % 32 != 0) {
-    //   TU_BREAKPOINT();
-    // }
+    TU_ASSERT(tu_is_aligned32(addr32));
     SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
   }
+  return true;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
   const uintptr_t addr32 = (uintptr_t) addr;
   if (imxrt_is_cache_mem(addr32)) {
+    TU_ASSERT(tu_is_aligned32(addr32));
     SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
   }
+  return true;
 }
 
 #endif
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 56167b8f6..6ee91e18e 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -41,16 +41,16 @@
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
   #include "ci_hs_imxrt.h"
 
-  void hcd_dcache_clean(void const* addr, uint32_t data_size) {
-    imxrt_dcache_clean(addr, data_size);
+  bool hcd_dcache_clean(void const* addr, uint32_t data_size) {
+    return imxrt_dcache_clean(addr, data_size);
   }
 
-  void hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
-    imxrt_dcache_invalidate(addr, data_size);
+  bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
+    return imxrt_dcache_invalidate(addr, data_size);
   }
 
-  void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
-    imxrt_dcache_clean_invalidate(addr, data_size);
+  bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+    return imxrt_dcache_clean_invalidate(addr, data_size);
   }
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 38711e382..6dfaab2a2 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -162,16 +162,19 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
 static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type);
 static inline ehci_link_t* list_next (ehci_link_t const *p_link);
 
-TU_ATTR_WEAK void hcd_dcache_clean(void const* addr, uint32_t data_size) {
+TU_ATTR_WEAK bool hcd_dcache_clean(void const* addr, uint32_t data_size) {
   (void) addr; (void) data_size;
+  return true;
 }
 
-TU_ATTR_WEAK void hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
+TU_ATTR_WEAK bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
   (void) addr; (void) data_size;
+  return true;
 }
 
-TU_ATTR_WEAK void hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
   (void) addr; (void) data_size;
+  return true;
 }
 
 //--------------------------------------------------------------------+

From 25225ba792c7537b6fa25f3be5728a08bf343af8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Jul 2023 18:04:42 +0700
Subject: [PATCH 1921/2085] minor clean up

---
 hw/bsp/lpc40/family.mk | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/hw/bsp/lpc40/family.mk b/hw/bsp/lpc40/family.mk
index 0fc7095f5..c11325890 100644
--- a/hw/bsp/lpc40/family.mk
+++ b/hw/bsp/lpc40/family.mk
@@ -31,6 +31,3 @@ SRC_C += \
 INC += \
 	$(TOP)/$(MCU_DIR)/inc \
 	$(TOP)/$(BOARD_PATH)
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F

From fd29fd923a0a64be96fe4bdfa2a5fa9f184ea6c7 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Jul 2023 20:53:44 +0700
Subject: [PATCH 1922/2085] clean up

---
 src/host/hcd.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 52fcc834e..a98286053 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -104,7 +104,7 @@ typedef struct
   uint8_t speed;
 } hcd_devtree_info_t;
 
-//--------------------------------------------------------------
+//--------------------------------------------------------------------+
 // Memory API
 //--------------------------------------------------------------------+
 

From f295aaf1851eb270070af7292d1f100f7172daf4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 24 Jul 2023 11:55:54 +0700
Subject: [PATCH 1923/2085] add hcd abort xfer for rp2040 pio usb

---
 hw/bsp/rp2040/board.h                          | 12 ++++++------
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c |  7 ++-----
 tools/get_deps.py                              |  2 +-
 3 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h
index 934e1c7ae..063c9580e 100644
--- a/hw/bsp/rp2040/board.h
+++ b/hw/bsp/rp2040/board.h
@@ -54,19 +54,19 @@
 // default to pin on Adafruit Feather rp2040 USB Host or Tester if defined
 //--------------------------------------------------------------------+
 
-// #define USE_ADAFRUIT_RP2040_TESTER
-#ifdef USE_ADAFRUIT_RP2040_TESTER
-#define PICO_DEFAULT_PIO_USB_DP_PIN       20
-#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN   22
+// #define USE_ADAFRUIT_FEATHER_RP2040_USBHOST
+#ifdef USE_ADAFRUIT_FEATHER_RP2040_USBHOST
+#define PICO_DEFAULT_PIO_USB_DP_PIN       16
+#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN   18
 #endif
 
 #ifndef PICO_DEFAULT_PIO_USB_DP_PIN
-#define PICO_DEFAULT_PIO_USB_DP_PIN       16
+#define PICO_DEFAULT_PIO_USB_DP_PIN       20
 #endif
 
 // VBUS enable pin and its active state
 #ifndef PICO_DEFAULT_PIO_USB_VBUSEN_PIN
-#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN   18
+#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN   22
 #endif
 
 // VBUS enable state
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index fa285327c..bb41ad638 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -139,11 +139,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 }
 
 bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
-  (void) rhport;
-  (void) dev_addr;
-  (void) ep_addr;
-  // TODO not implemented yet
-  return false;
+  uint8_t const pio_rhport = RHPORT_PIO(rhport);
+  return pio_usb_host_endpoint_abort_transfer(pio_rhport, dev_addr, ep_addr);
 }
 
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 9b89c5e4c..d6505a1d9 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -54,7 +54,7 @@ deps_optional = {
                             '950819b7de9b32f92c3edf396bc5ffb8d66e7009',
                             'kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'],
     'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git',
-                                         '58879cfa0eca5725d8db6443ec17f8896a321042',
+                                         'd00a10a8c425d0d40f81b87169102944b01f3bb3',
                                          'rp2040'],
     'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git',
                            '8dc14709f2a6518b43f71efad70d900b7718d9f1',

From ef69da054e4d373636818a52df4e3433152fa3bf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 25 Jul 2023 12:03:54 +0700
Subject: [PATCH 1924/2085] use standard EHCI USB INT instead of chipidea
 async/period interrupt to be compatible with other EHCI implementation

---
 src/portable/ehci/ehci.c | 24 ++++++++----------------
 src/portable/ehci/ehci.h |  6 +-----
 2 files changed, 9 insertions(+), 21 deletions(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 241393a39..a9e184f22 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -307,8 +307,8 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   regs->status = (EHCI_INT_MASK_ALL & ~EHCI_INT_MASK_PORT_CHANGE);
 
   // Enable interrupts
-  regs->inten  = EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE | EHCI_INT_MASK_ASYNC_ADVANCE |
-                 EHCI_INT_MASK_NXP_PERIODIC | EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_FRAMELIST_ROLLOVER;
+  regs->inten  = EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
+                 EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_FRAMELIST_ROLLOVER;
 
   //------------- Asynchronous List -------------//
   ehci_qhd_t * const async_head = list_get_async_head(rhport);
@@ -768,28 +768,20 @@ void hcd_int_handler(uint8_t rhport)
     regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge
   }
 
+  // A USB transfer is completed with error
   if (int_status & EHCI_INT_MASK_ERROR) {
     xfer_error_isr(rhport);
     regs->status = EHCI_INT_MASK_ERROR; // Acknowledge
   }
 
-  //------------- some QTD/SITD/ITD with IOC set is completed -------------//
-  if (int_status & EHCI_INT_MASK_NXP_ASYNC) {
-    async_list_xfer_complete_isr(list_get_async_head(rhport));
-    regs->status = EHCI_INT_MASK_NXP_ASYNC; // Acknowledge
-  }
-
-  if (int_status & EHCI_INT_MASK_NXP_PERIODIC)
-  {
-    for (uint32_t i=1; i <= FRAMELIST_SIZE; i *= 2)
-    {
+  // A USB transfer is completed
+  if (int_status & EHCI_INT_MASK_USB) {
+    for ( uint32_t i = 1; i <= FRAMELIST_SIZE; i *= 2 ) {
       period_list_xfer_complete_isr(rhport, i);
     }
-    regs->status = EHCI_INT_MASK_NXP_PERIODIC; // Acknowledge
-  }
 
-  if (int_status & EHCI_INT_MASK_USB) {
-    // TODO standard EHCI xfer complete
+    async_list_xfer_complete_isr(list_get_async_head(rhport));
+
     regs->status = EHCI_INT_MASK_USB; // Acknowledge
   }
 
diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h
index 05de80539..457adc1d3 100644
--- a/src/portable/ehci/ehci.h
+++ b/src/portable/ehci/ehci.h
@@ -278,14 +278,10 @@ enum {
   EHCI_INT_MASK_PERIODIC_SCHED_STATUS = TU_BIT(14),
   EHCI_INT_MASK_ASYNC_SCHED_STATUS    = TU_BIT(15),
 
-  EHCI_INT_MASK_NXP_ASYNC             = TU_BIT(18),
-  EHCI_INT_MASK_NXP_PERIODIC          = TU_BIT(19),
-
   EHCI_INT_MASK_ALL                   =
       EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE |
       EHCI_INT_MASK_FRAMELIST_ROLLOVER | EHCI_INT_MASK_PCI_HOST_SYSTEM_ERROR |
-      EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_SOF |
-      EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC
+      EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_SOF
 };
 
 enum {

From dc74e634f93962512229ba7d4e14467c16125c0d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 25 Jul 2023 12:35:40 +0700
Subject: [PATCH 1925/2085] fix unaligned hub status_change

---
 src/host/hub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/host/hub.c b/src/host/hub.c
index 182bd6ce8..16dd534d2 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -45,8 +45,8 @@ typedef struct
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t port_count;
-  uint8_t status_change; // data from status change interrupt endpoint
 
+  CFG_TUH_MEM_ALIGN uint8_t status_change;
   CFG_TUH_MEM_ALIGN hub_port_status_response_t port_status;
   CFG_TUH_MEM_ALIGN hub_status_response_t hub_status;
 } hub_interface_t;

From 4deea875793ce78a24b069491bb83e59e310c476 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 25 Jul 2023 15:07:21 +0700
Subject: [PATCH 1926/2085] improve processing usb complete and error isr.

also merge them together
---
 hw/bsp/imxrt/family.cmake | 126 ++++++++++----------
 src/CMakeLists.txt        |   1 +
 src/portable/ehci/ehci.c  | 244 +++++++++++---------------------------
 3 files changed, 131 insertions(+), 240 deletions(-)

diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake
index f1c5b0ab1..96ed4b030 100644
--- a/hw/bsp/imxrt/family.cmake
+++ b/hw/bsp/imxrt/family.cmake
@@ -22,69 +22,71 @@ set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "")
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c
-      #${SDK_DIR}/drivers/adc_12b1msps_sar/fsl_adc.c
-      ${SDK_DIR}/drivers/common/fsl_common.c
-      ${SDK_DIR}/drivers/igpio/fsl_gpio.c
-      ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c
-      ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c
+    #${SDK_DIR}/drivers/adc_12b1msps_sar/fsl_adc.c
+    ${SDK_DIR}/drivers/common/fsl_common.c
+    ${SDK_DIR}/drivers/igpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/lpspi/fsl_lpspi.c
+    ${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __ARMVFP__=0
+    __ARMFPV5__=0
+    XIP_EXTERNAL_FLASH=1
+    XIP_BOOT_HEADER_ENABLE=1
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    #${SDK_DIR}/drivers/adc_12b1msps_sar
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/igpio
+    ${SDK_DIR}/drivers/lpspi
+    ${SDK_DIR}/drivers/lpuart
+    )
+
+  update_board(${BOARD_TARGET})
+
+  # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
+    #set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
+  endif ()
+
+  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+    #set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
+  endif ()
+
+  target_sources(${BOARD_TARGET} PUBLIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      # force linker to look for these symbols
+      -Wl,-uimage_vector_table
+      -Wl,-ug_boot_data
       )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      __ARMVFP__=0
-      __ARMFPV5__=0
-      XIP_EXTERNAL_FLASH=1
-      XIP_BOOT_HEADER_ENABLE=1
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
       )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board
-      ${CMSIS_DIR}/CMSIS/Core/Include
-      ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-      #${SDK_DIR}/drivers/adc_12b1msps_sar
-      ${SDK_DIR}/drivers/common
-      ${SDK_DIR}/drivers/igpio
-      ${SDK_DIR}/drivers/lpspi
-      ${SDK_DIR}/drivers/lpuart
-      )
-
-    update_board(${BOARD_TARGET})
-
-    # LD_FILE and STARTUP_FILE can be defined in board.cmake
-    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
-      set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
-      #set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
-    endif ()
-
-    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
-      set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
-      #set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
-    endif ()
-
-    target_sources(${BOARD_TARGET} PUBLIC
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-      )
-
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_GNU}"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        # force linker to look for these symbols
-        -Wl,-uimage_vector_table
-        -Wl,-ug_boot_data
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
   endif ()
 endfunction()
 
@@ -114,7 +116,7 @@ function(family_configure_example TARGET RTOS)
 
   # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX ${RTOS})
-  target_sources(${TARGET}-tinyusb PUBLIC
+  target_sources(${TARGET}-tinyusb PRIVATE
     ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
     ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
     ${TOP}/src/portable/ehci/ehci.c
diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
index 8f7f38589..076e1e1eb 100644
--- a/src/CMakeLists.txt
+++ b/src/CMakeLists.txt
@@ -64,6 +64,7 @@ function(add_tinyusb TARGET)
       -Wnull-dereference
       -Wuninitialized
       -Wunused
+      -Wunused-function
       -Wreturn-type
       -Wredundant-decls
       )
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index a9e184f22..b84de5191 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -314,11 +314,11 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg)
   ehci_qhd_t * const async_head = list_get_async_head(rhport);
   tu_memclr(async_head, sizeof(ehci_qhd_t));
 
-  async_head->next.address                    = (uint32_t) async_head; // circular list, next is itself
-  async_head->next.type                       = EHCI_QTYPE_QHD;
-  async_head->head_list_flag                  = 1;
-  async_head->qtd_overlay.halted              = 1; // inactive most of time
-  async_head->qtd_overlay.next.terminate      = 1; // TODO removed if verified
+  async_head->next.address               = (uint32_t) async_head; // circular list, next is itself
+  async_head->next.type                  = EHCI_QTYPE_QHD;
+  async_head->head_list_flag             = 1;
+  async_head->qtd_overlay.halted         = 1; // inactive most of time
+  async_head->qtd_overlay.next.terminate = 1; // TODO removed if verified
 
   regs->async_list_addr = (uint32_t) async_head;
 
@@ -533,70 +533,74 @@ void async_advance_isr(uint8_t rhport)
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-void port_connect_status_change_isr(uint8_t rhport)
-{
+void port_connect_status_change_isr(uint8_t rhport) {
   // NOTE There is an sequence plug->unplug->…..-> plug if device is powering with pre-plugged device
-  if (ehci_data.regs->portsc_bm.current_connect_status)
-  {
+  if ( ehci_data.regs->portsc_bm.current_connect_status ) {
     hcd_port_reset(rhport);
     hcd_event_device_attach(rhport, true);
-  }else // device unplugged
+  } else // device unplugged
   {
     hcd_event_device_remove(rhport, true);
   }
 }
 
+// Check queue head for potential transfer complete (successful or error)
 TU_ATTR_ALWAYS_INLINE static inline
 void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
-  // examine TD attached to queue head
-  ehci_qtd_t * volatile qtd = qhd->attached_qtd;
+  hcd_dcache_invalidate(qhd, sizeof(ehci_qhd_t)); // HC may have updated the overlay
+  volatile ehci_qtd_t *qtd_overlay = &qhd->qtd_overlay;
 
-  if (qtd == NULL) {
-    return; // no TD attached
-  }
+  // process non-active (completed) QHD with attached (scheduled) TD
+  if ( !qtd_overlay->active && qhd->attached_qtd != NULL ) {
+    xfer_result_t xfer_result;
 
-  hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
-
-  // TD is still active, no need to process
-  if (qtd->active) {
-    return;
-  }
-
-  uint8_t dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0;
-  uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
-
-  // invalidate dcache if IN transfer
-  if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) {
-    hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
-  }
-
-  // remove and free TD before invoking callback
-  qhd_remove_qtd(qhd);
-
-  // notify usbh
-  uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir);
-  hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, XFER_RESULT_SUCCESS, true);
-}
-
-TU_ATTR_ALWAYS_INLINE static inline
-void async_list_xfer_complete_isr(ehci_qhd_t * const async_head)
-{
-  ehci_qhd_t *p_qhd = async_head;
-  do
-  {
-    hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t));
-
-    // halted or error is processed in error isr
-    if ( !p_qhd->qtd_overlay.halted ) {
-      qhd_xfer_complete_isr(p_qhd);
+    if ( qtd_overlay->halted ) {
+      if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) {
+        // Error count = 0 often occurs when device disconnected, or other bus-related error
+        xfer_result = XFER_RESULT_FAILED;
+        TU_LOG3("  QHD xfer err count: %d\n", qtd_overlay->err_count);
+        // TU_BREAKPOINT(); // TODO skip unplugged device
+      }else {
+        // no error bits are set, endpoint is halted due to STALL
+        xfer_result = XFER_RESULT_STALLED;
+      }
+    } else {
+      xfer_result = XFER_RESULT_SUCCESS;
     }
 
-    p_qhd = qhd_next(p_qhd);
-  }while(p_qhd != async_head); // async list traversal, stop if loop around
+    ehci_qtd_t * volatile qtd = qhd->attached_qtd;
+    hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t)); // HC may have written back TD
+
+    uint8_t const dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0;
+    uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
+
+    // invalidate dcache if IN transfer with data
+    if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) {
+      hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
+    }
+
+    // remove and free TD before invoking callback
+    qhd_remove_qtd(qhd);
+
+    // notify usbh
+    uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir);
+    hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true);
+  }
 }
 
 TU_ATTR_ALWAYS_INLINE static inline
-void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms)
+void proccess_async_xfer_isr(ehci_qhd_t * const list_head)
+{
+  ehci_qhd_t *qhd = list_head;
+
+  do {
+    qhd_xfer_complete_isr(qhd);
+    qhd = qhd_next(qhd);
+  } while ( qhd != list_head ); // async list traversal, stop if loop around
+}
+
+TU_ATTR_ALWAYS_INLINE static inline
+void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms)
 {
   uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u);
   ehci_link_t next_link = *list_get_period_head(rhport, interval_ms);
@@ -612,22 +616,13 @@ void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms)
     switch (next_link.type) {
       case EHCI_QTYPE_QHD: {
         ehci_qhd_t *qhd = (ehci_qhd_t *) entry_addr;
-        hcd_dcache_invalidate(qhd, sizeof(ehci_qhd_t));
-
-        if (!qhd->qtd_overlay.halted) {
-          qhd_xfer_complete_isr(qhd);
-        }
+        qhd_xfer_complete_isr(qhd);
       }
         break;
 
+      // TODO support hs/fs ISO
       case EHCI_QTYPE_ITD:
-        // TODO support hs ISO
-        break;
-
       case EHCI_QTYPE_SITD:
-        // TODO support split ISO
-        break;
-
       case EHCI_QTYPE_FSTN:
       default:
         break;
@@ -637,106 +632,6 @@ void period_list_xfer_complete_isr(uint8_t rhport, uint32_t interval_ms)
   }
 }
 
-// TODO merge with qhd_xfer_complete_isr()
-TU_ATTR_ALWAYS_INLINE static inline
-void qhd_xfer_error_isr(ehci_qhd_t * qhd)
-{
-  volatile ehci_qtd_t *qtd_overlay = &qhd->qtd_overlay;
-
-  // TD has error
-  if (qtd_overlay->halted) {
-    xfer_result_t xfer_result;
-
-    if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) {
-      // Error count = 0 often occurs when device disconnected, or other bus-related error
-      xfer_result = XFER_RESULT_FAILED;
-    }else {
-      // no error bits are set, endpoint is halted due to STALL
-      xfer_result = XFER_RESULT_STALLED;
-    }
-
-//    if (XFER_RESULT_FAILED == xfer_result ) {
-//      TU_LOG1("  QHD xfer err count: %d\n", qtd_overlay->err_count);
-//      TU_BREAKPOINT(); // TODO skip unplugged device
-//    }
-
-    ehci_qtd_t * volatile qtd = (ehci_qtd_t * volatile) qhd->attached_qtd;
-    TU_ASSERT(qtd, ); // No TD yet, probably a race condition or cache issue !?
-
-    hcd_dcache_invalidate(qtd, sizeof(ehci_qtd_t));
-
-    uint8_t dir = (qtd->pid == EHCI_PID_IN) ? 1 : 0;
-    uint32_t const xferred_bytes = qtd->expected_bytes - qtd->total_bytes;
-
-    // invalidate dcache if IN transfer
-    if (dir == 1 && qhd->attached_buffer != 0 && xferred_bytes > 0) {
-      hcd_dcache_invalidate((void*) qhd->attached_buffer, xferred_bytes);
-    }
-
-    // remove and free TD before invoking callback
-    qhd_remove_qtd(qhd);
-
-    if (0 == qhd->ep_number ) {
-      // control cannot be halted
-      qhd->qtd_overlay.next.terminate      = 1;
-      qhd->qtd_overlay.alternate.terminate = 1;
-      qhd->qtd_overlay.halted              = 0;
-
-      hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
-    }
-
-    // notify usbh
-    uint8_t const ep_addr = tu_edpt_addr(qhd->ep_number, dir);
-    hcd_event_xfer_complete(qhd->dev_addr, ep_addr, xferred_bytes, xfer_result, true);
-  }
-}
-
-TU_ATTR_ALWAYS_INLINE static inline
-void xfer_error_isr(uint8_t rhport)
-{
-  //------------- async list -------------//
-  ehci_qhd_t * const async_head = list_get_async_head(rhport);
-  ehci_qhd_t *p_qhd = async_head;
-  do
-  {
-    hcd_dcache_invalidate(p_qhd, sizeof(ehci_qhd_t));
-    qhd_xfer_error_isr( p_qhd );
-    p_qhd = qhd_next(p_qhd);
-  }while(p_qhd != async_head); // async list traversal, stop if loop around
-
-  //------------- TODO refractor period list -------------//
-  uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u);
-  for (uint32_t interval_ms=1; interval_ms <= FRAMELIST_SIZE; interval_ms *= 2)
-  {
-    ehci_link_t next_item = *list_get_period_head(rhport, interval_ms);
-
-    // TODO abstract max loop guard for period
-    while( !next_item.terminate &&
-           !(interval_ms > 1 && period_1ms_addr == tu_align32(next_item.address)) )
-    {
-      switch ( next_item.type )
-      {
-        case EHCI_QTYPE_QHD:
-        {
-          ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) tu_align32(next_item.address);
-          hcd_dcache_invalidate(p_qhd_int, sizeof(ehci_qhd_t));
-
-          qhd_xfer_error_isr(p_qhd_int);
-        }
-        break;
-
-				// TODO support hs/fs ISO
-        case EHCI_QTYPE_ITD:
-        case EHCI_QTYPE_SITD:
-        case EHCI_QTYPE_FSTN:
-        default: break;
-      }
-
-      next_item = *list_next(&next_item);
-    }
-  }
-}
-
 //------------- Host Controller Driver's Interrupt Handler -------------//
 void hcd_int_handler(uint8_t rhport)
 {
@@ -768,21 +663,16 @@ void hcd_int_handler(uint8_t rhport)
     regs->status = EHCI_INT_MASK_PORT_CHANGE; // Acknowledge
   }
 
-  // A USB transfer is completed with error
-  if (int_status & EHCI_INT_MASK_ERROR) {
-    xfer_error_isr(rhport);
-    regs->status = EHCI_INT_MASK_ERROR; // Acknowledge
-  }
+  // A USB transfer is completed (OK or error)
+  uint32_t const usb_int = int_status & (EHCI_INT_MASK_USB | EHCI_INT_MASK_ERROR);
+  if (usb_int) {
+    proccess_async_xfer_isr(list_get_async_head(rhport));
 
-  // A USB transfer is completed
-  if (int_status & EHCI_INT_MASK_USB) {
     for ( uint32_t i = 1; i <= FRAMELIST_SIZE; i *= 2 ) {
-      period_list_xfer_complete_isr(rhport, i);
+      process_period_xfer_isr(rhport, i);
     }
 
-    async_list_xfer_complete_isr(list_get_async_head(rhport));
-
-    regs->status = EHCI_INT_MASK_USB; // Acknowledge
+    regs->status = usb_int; // Acknowledge
   }
 
   //------------- There is some removed async previously -------------//
@@ -1011,8 +901,7 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t *qtd_find_free(void) {
   return NULL;
 }
 
-static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
-{
+static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) {
   tu_memclr(qtd, sizeof(ehci_qtd_t));
   qtd->used                = 1;
 
@@ -1026,8 +915,7 @@ static void qtd_init(ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes)
   qtd->expected_bytes      = total_bytes;
 
   qtd->buffer[0] = (uint32_t) buffer;
-  for(uint8_t i=1; i<5; i++)
-  {
+  for(uint8_t i=1; i<5; i++) {
     qtd->buffer[i] |= tu_align4k(qtd->buffer[i - 1] ) + 4096;
   }
 }

From fbaa148fe0f4a4b83f41efe9887a8909161710f6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 18 Jul 2023 15:22:09 +0700
Subject: [PATCH 1927/2085] updating hcd rusb2

- make osal_task_delay() as weak function in usbh
- implement osal_task_delay() in hcd rusb2 (may moved to other places)
---
 examples/device/cdc_msc_freertos/skip.txt     |   1 +
 .../device/hid_composite_freertos/skip.txt    |   1 +
 examples/dual/host_hid_to_device_cdc/only.txt |   1 +
 hw/bsp/ra/boards/ra6m5_ek/board.cmake         |   7 +-
 hw/bsp/ra/family.cmake                        |   2 +-
 src/host/usbh.c                               |   2 +-
 src/portable/renesas/rusb2/dcd_rusb2.c        |  12 +-
 src/portable/renesas/rusb2/hcd_rusb2.c        | 121 +++++++++---------
 src/portable/renesas/rusb2/rusb2_ra.h         |   7 -
 9 files changed, 77 insertions(+), 77 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/skip.txt b/examples/device/cdc_msc_freertos/skip.txt
index 49b8ee57b..a6f96b288 100644
--- a/examples/device/cdc_msc_freertos/skip.txt
+++ b/examples/device/cdc_msc_freertos/skip.txt
@@ -8,5 +8,6 @@ mcu:RP2040
 mcu:SAMD11
 mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
 family:broadcom_32bit
 family:broadcom_64bit
diff --git a/examples/device/hid_composite_freertos/skip.txt b/examples/device/hid_composite_freertos/skip.txt
index 49b8ee57b..a6f96b288 100644
--- a/examples/device/hid_composite_freertos/skip.txt
+++ b/examples/device/hid_composite_freertos/skip.txt
@@ -8,5 +8,6 @@ mcu:RP2040
 mcu:SAMD11
 mcu:SAMX7X
 mcu:VALENTYUSB_EPTRI
+mcu:RAXXX
 family:broadcom_32bit
 family:broadcom_64bit
diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt
index 6ee8e3fde..d9700677f 100644
--- a/examples/dual/host_hid_to_device_cdc/only.txt
+++ b/examples/dual/host_hid_to_device_cdc/only.txt
@@ -1,3 +1,4 @@
 board:mimxrt1060_evk
 board:mimxrt1064_evk
 mcu:RP2040
+mcu:ra6m5
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
index 5a615f9b0..c91d48a32 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
@@ -3,15 +3,20 @@ set(MCU_VARIANT ra6m5)
 
 set(JLINK_DEVICE R7FA6M5BH)
 
-# default to PORT1 Highspeed
+# Device port default to PORT1 Highspeed
 if (NOT DEFINED PORT)
 set(PORT 1)
 endif()
 
+# Host port will be the other port
+set(HOST_PORT $<NOT:${PORT}>)
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     BOARD_TUD_RHPORT=${PORT}
+    BOARD_TUH_RHPORT=${HOST_PORT}
     # port 0 is fullspeed, port 1 is highspeed
     BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
+    BOARD_TUH_MAX_SPEED=$<IF:${HOST_PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
     )
 endfunction()
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index f09e86a72..2c45b8d71 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -13,7 +13,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
 
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-set(FAMILY_MCUS RAXXX CACHE INTERNAL "")
+set(FAMILY_MCUS RAXXX ${MCU_VARIANT} CACHE INTERNAL "")
 
 #------------------------------------
 # BOARD_TARGET
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 184bda23b..1418cfb79 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -256,7 +256,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
-void osal_task_delay(uint32_t msec)
+TU_ATTR_WEAK void osal_task_delay(uint32_t msec)
 {
   const uint32_t start = hcd_frame_number(_usbh_controller);
   while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 358e5644b..6fee4edd7 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -27,12 +27,12 @@
 
 #include "tusb_option.h"
 
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2)
+
 // Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-#if CFG_TUD_ENABLED && defined(TUP_USBIP_RUSB2)
-
 #include "device/dcd.h"
 #include "rusb2_type.h"
 
@@ -53,6 +53,13 @@
   #error "Unsupported MCU"
 #endif
 
+//--------------------------------------------------------------------+
+// Application API for setting IRQ number
+//--------------------------------------------------------------------+
+void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
+  rusb2_controller[rhport].irqnum = irqnum;
+}
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -681,7 +688,6 @@ static void enable_interrupt(uint32_t pswi)
 void dcd_init(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
-
   rusb2_module_start(rhport, true);
 
 #ifdef RUSB2_SUPPORT_HIGHSPEED
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 4e5ff0359..656051e2b 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -27,8 +27,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && (TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) || \
-                        TU_CHECK_MCU(OPT_MCU_RAXXX))
+#if CFG_TUH_ENABLED && defined(TUP_USBIP_RUSB2)
 
 #include "host/hcd.h"
 #include "rusb2_type.h"
@@ -41,8 +40,14 @@
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
+
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
   #include "rusb2_ra.h"
+
+  void osal_task_delay(uint32_t msec) {
+    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
+  }
+
 #else
   #error "Unsupported MCU"
 #endif
@@ -67,19 +72,6 @@
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
-typedef struct TU_ATTR_PACKED {
-  union {
-    struct {
-      uint16_t      : 8;
-      uint16_t TRCLR: 1;
-      uint16_t TRENB: 1;
-      uint16_t      : 0;
-    };
-    uint16_t TRE;
-  };
-  uint16_t TRN;
-} reg_pipetre_t;
-
 typedef union TU_ATTR_PACKED {
   struct {
     volatile uint16_t u8: 8;
@@ -308,8 +300,9 @@ static bool pipe_xfer_out(unsigned num)
     pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
-  if (len < mps)
+  if (len < mps) {
     RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+  }
   RUSB2->D0FIFOSEL = 0;
   while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
@@ -488,60 +481,60 @@ static void enable_interrupt(uint32_t pswi)
 
 bool hcd_init(uint8_t rhport)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb2_module_start(rhport, true);
 
-#if (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
-  RUSB2->SYSCFG_b.HSE = 1;
-  RUSB2->PHYSET_b.HSEB = 0;
-  RUSB2->PHYSET_b.DIRPD = 0;
-  R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
-  RUSB2->PHYSET_b.PLLRESET = 0;
-  RUSB2->LPSTS_b.SUSPENDM = 1;
-  while (!RUSB2->PLLSTA_b.PLLLOCK);
-  RUSB2->SYSCFG_b.DRPD = 1;
-  RUSB2->SYSCFG_b.DCFM = 1;
-  RUSB2->SYSCFG_b.DPRPU = 0;
-  RUSB2->SYSCFG_b.CNEN = 1;
-  RUSB2->BUSWAIT |= 0x0F00U;
-  RUSB2->SOFCFG_b.INTL = 1;
-  RUSB2->DVSTCTR0_b.VBUSEN = 1;
-  RUSB2->CFIFOSEL_b.MBW = 1;
-  RUSB2->D0FIFOSEL_b.MBW = 1;
-  RUSB2->D1FIFOSEL_b.MBW = 1;
-  RUSB2->INTSTS0 = 0;
-  for (volatile int i = 0; i < 30000; ++i) ;
-  RUSB2->SYSCFG_b.USBE = 1;
-#else
-  /* HOST DEVICE Full SPEED */
-  RUSB2->SYSCFG_b.SCKE = 1;         /* USB Clock enable */
-  while (!RUSB2->SYSCFG_b.SCKE) ;
-  RUSB2->SYSCFG_b.DPRPU = 0;        /* D+ pull up enable - 0/disable in host mode */
-  RUSB2->SYSCFG_b.DRPD = 1;         /* D+/D- pull down - 1/in Host mode (pag.834)*/
-  RUSB2->SYSCFG_b.DCFM = 1;         /* HOST or Device - 1/HOST */
-
-  RUSB2->DVSTCTR0_b.VBUSEN = 1;
-
-  RUSB2->SYSCFG_b.DRPD = 1;
-  for (volatile int i = 0; i < 30000; ++i) ;
-  RUSB2->SYSCFG_b.USBE = 1;
+#ifdef RUSB2_SUPPORT_HIGHSPEED
+  if (rusb2_is_highspeed_rhport(rhport) ) {
+    rusb->SYSCFG_b.HSE = 1;
+    rusb->PHYSET_b.HSEB = 0;
+    rusb->PHYSET_b.DIRPD = 0;
+    R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
+    rusb->PHYSET_b.PLLRESET = 0;
+    rusb->LPSTS_b.SUSPENDM = 1;
+    while ( !rusb->PLLSTA_b.PLLLOCK );
+    rusb->SYSCFG_b.DRPD = 1;
+    rusb->SYSCFG_b.DCFM = 1;
+    rusb->SYSCFG_b.DPRPU = 0;
+    rusb->SYSCFG_b.CNEN = 1;
+    rusb->BUSWAIT |= 0x0F00U;
+    rusb->SOFCFG_b.INTL = 1;
+    rusb->DVSTCTR0_b.VBUSEN = 1;
+    rusb->CFIFOSEL_b.MBW = 1;
+    rusb->D0FIFOSEL_b.MBW = 1;
+    rusb->D1FIFOSEL_b.MBW = 1;
+    rusb->INTSTS0 = 0;
+    for ( volatile int i = 0; i < 30000; ++i );
+    rusb->SYSCFG_b.USBE = 1;
+  } else
 #endif
+  {
+    rusb->SYSCFG_b.SCKE = 1;
+    while ( !rusb->SYSCFG_b.SCKE ) {}
+    rusb->SYSCFG_b.DCFM = 1;         // Host function
+    rusb->SYSCFG_b.DPRPU = 0;        // Disable D+ pull up
+    rusb->SYSCFG_b.DRPD = 1;         // Enable D+/D- pull down
 
-  // MCU specific PHY init
-  rusb2_phy_init();
+    rusb->DVSTCTR0_b.VBUSEN = 1;
+    for ( volatile int i = 0; i < 30000; ++i ) {} // FIXME do we need to wait here? how long ?
+    //R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS);
+    rusb->SYSCFG_b.USBE = 1;
 
-#if (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HOST)
-  RUSB2->PHYSLEW = 0x5;
-  RUSB2->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
-#endif
+    // MCU specific PHY init
+    rusb2_phy_init();
+
+    rusb->PHYSLEW = 0x5;
+    rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
+  }
 
   /* Setup default control pipe */
-  RUSB2->DCPCFG  = RUSB2_PIPECFG_SHTNAK_Msk;
-  RUSB2->DCPMAXP = 64;
-  RUSB2->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk;
-  RUSB2->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk;
-  RUSB2->BEMPENB = 1;
-  RUSB2->NRDYENB = 1;
-  RUSB2->BRDYENB = 1;
+  rusb->DCPCFG  = RUSB2_PIPECFG_SHTNAK_Msk;
+  rusb->DCPMAXP = 64;
+  rusb->INTENB0 = RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk;
+  rusb->INTENB1 = RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk;
+  rusb->BEMPENB = 1;
+  rusb->NRDYENB = 1;
+  rusb->BRDYENB = 1;
 
   return true;
 }
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 28b690512..8a4d2ad36 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -106,13 +106,6 @@ TU_ATTR_ALWAYS_INLINE static inline void rusb2_int_disable(uint8_t rhport) {
 TU_ATTR_ALWAYS_INLINE static inline void rusb2_phy_init(void) {
 }
 
-//--------------------------------------------------------------------+
-// Application API for setting IRQ number
-//--------------------------------------------------------------------+
-void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
-  rusb2_controller[rhport].irqnum = irqnum;
-}
-
 #ifdef __cplusplus
 }
 #endif

From 1cb3f0e92a2e35155245452c54f599a733df9604 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Jul 2023 18:56:13 +0700
Subject: [PATCH 1928/2085] increase stack size for 6 series to 0x1000, 4
 series to 0x800

---
 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h | 2 +-
 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h | 4 ++--
 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h | 2 +-
 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
index f0577b702..11d5795df 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -12,7 +12,7 @@
 #define BSP_CFG_BOOT_IMAGE (1)
 #endif
 #define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x400)
+#define BSP_CFG_STACK_MAIN_BYTES (0x800)
 #define BSP_CFG_HEAP_BYTES (0x1000)
 #define BSP_CFG_PARAM_CHECKING_ENABLE (1)
 #define BSP_CFG_ASSERT (0)
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
index 47de7747d..862ec25b7 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -27,8 +27,8 @@ extern "C" {
 #define BSP_CFG_BOOT_IMAGE (1)
 #endif
 #define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x400)
-#define BSP_CFG_HEAP_BYTES (0x400)
+#define BSP_CFG_STACK_MAIN_BYTES (0x800)
+#define BSP_CFG_HEAP_BYTES (0x800)
 #define BSP_CFG_PARAM_CHECKING_ENABLE (1)
 #define BSP_CFG_ASSERT (0)
 #define BSP_CFG_ERROR_LOG (0)
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
index b5ed53a3b..772e5e5b1 100644
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -31,7 +31,7 @@ extern "C" {
 #endif
 
 #define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x400)
+#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
 #define BSP_CFG_HEAP_BYTES (0x1000)
 #define BSP_CFG_PARAM_CHECKING_ENABLE (1)
 #define BSP_CFG_ASSERT (0)
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
index a41536eda..33d381850 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
@@ -27,7 +27,7 @@ extern "C" {
   #define BSP_CFG_BOOT_IMAGE (1)
 #endif
 #define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x400)
+#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
 #define BSP_CFG_HEAP_BYTES (0x1000)
 #define BSP_CFG_PARAM_CHECKING_ENABLE (1)
 #define BSP_CFG_ASSERT (0)

From 6b6dcc6c099eeafaa6d76bf6133181874beabc0d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Jul 2023 19:50:50 +0700
Subject: [PATCH 1929/2085] refactored multiple ports for hcd rusb2

---
 .idea/cmake.xml                              |  15 +-
 .idea/runConfigurations/ra6m5.xml            |   2 +-
 hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug |   4 +-
 src/portable/renesas/rusb2/dcd_rusb2.c       |  37 +-
 src/portable/renesas/rusb2/hcd_rusb2.c       | 498 ++++++++++---------
 5 files changed, 291 insertions(+), 265 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 864ff615b..519623b71 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,7 +2,6 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
@@ -26,27 +25,27 @@
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
       <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
-      <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk" />
-      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk" />
-      <configuration PROFILE_NAME="rt1064 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1064_evk" />
+      <configuration PROFILE_NAME="metro m7 1011" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="lpcxpresso18s37" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso18s37" />
+      <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69" />
+      <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g0b1nucleo" />
       <configuration PROFILE_NAME="stm32g474nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g474nucleo" />
       <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=b_g474e_dpow1 -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="b_g474e_dpow1 iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=b_g474e_dpow1 -DTOOLCHAIN=iar" />
       <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_kl25z -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32h743eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="metro m7" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="stm32f072disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f072disco" />
       <configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2" />
       <configuration PROFILE_NAME="stm32f769disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f769disco -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco" />
       <configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
+      <configuration PROFILE_NAME="ra6m5" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml
index 02df11610..89f9787a0 100644
--- a/.idea/runConfigurations/ra6m5.xml
+++ b/.idea/runConfigurations/ra6m5.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc_hid">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
index aebb29162..7b8ee9c95 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
+++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
@@ -20,7 +20,9 @@ void OnProjectLoad (void) {
   Project.SetTraceSource ("Trace Pins");
   Project.SetTracePortWidth (4);
 
-  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf");
+  //File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf");
+  //File.Open ("../../../../../../examples/dual/cmake-build-ra6m5/host_hid_to_device_cdc/host_hid_to_device_cdc.elf");
+  File.Open ("../../../../../../examples/cmake-build-ra6m5/host/cdc_msc_hid/cdc_msc_hid.elf");
 }
 /*********************************************************************
 *
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 6fee4edd7..83f0fdc4a 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -83,6 +83,18 @@ typedef struct TU_ATTR_PACKED
 TU_ATTR_PACKED_END  // End of definition of packed structs (used by the CCRX toolchain)
 TU_ATTR_BIT_FIELD_ORDER_END
 
+typedef struct
+{
+  pipe_state_t pipe[10];
+  uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
+} dcd_data_t;
+
+static dcd_data_t _dcd;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+
 // Transfer conditions specifiable for each pipe:
 // - Pipe 0: Control transfer with 64-byte single buffer
 // - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up
@@ -96,18 +108,6 @@ enum {
   PIPE_COUNT = 10,
 };
 
-typedef struct
-{
-  pipe_state_t pipe[10];
-  uint8_t ep[2][16];   /* a lookup table for a pipe index from an endpoint address */
-} dcd_data_t;
-
-static dcd_data_t _dcd;
-
-//--------------------------------------------------------------------+
-// INTERNAL OBJECT & FUNCTION DECLARATION
-//--------------------------------------------------------------------+
-
 static unsigned find_pipe(unsigned xfer)
 {
   switch (xfer) {
@@ -746,20 +746,17 @@ void dcd_init(uint8_t rhport)
   }
 }
 
-void dcd_int_enable(uint8_t rhport)
-{
+void dcd_int_enable(uint8_t rhport) {
   rusb2_int_enable(rhport);
 }
 
-void dcd_int_disable(uint8_t rhport)
-{
+void dcd_int_disable(uint8_t rhport) {
   rusb2_int_disable(rhport);
 }
 
-void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-{
-  (void)rhport;
-  (void)dev_addr;
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  (void) dev_addr;
 }
 
 void dcd_remote_wakeup(uint8_t rhport)
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 656051e2b..a4b534a05 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -52,23 +52,12 @@
   #error "Unsupported MCU"
 #endif
 
-#define TU_RUSB2_HCD_DBG   0
+#define TU_RUSB2_HCD_DBG   2
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
-/* LINK core registers */
-#if defined(__CCRX__)
-  #define RUSB2 ((RUSB2_REG_t __evenaccess*) RUSB2_REG_BASE)
-#elif defined(__RX__)
-  #define RUSB2 ((RUSB2_REG_t*) RUSB2_REG_BASE)
-#elif (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
-  #define RUSB2 ((R_USB_HS0_Type*) R_USB_HS0_BASE)
-#else
-  #define RUSB2 ((R_USB_FS0_Type*) R_USB_FS0_BASE)
-#endif
-
 TU_ATTR_PACKED_BEGIN
 TU_ATTR_BIT_FIELD_ORDER_BEGIN
 
@@ -108,79 +97,97 @@ typedef struct
 //--------------------------------------------------------------------+
 static hcd_data_t _hcd;
 
-static unsigned find_pipe(unsigned xfer)
-{
-  switch (xfer) {
-  case TUSB_XFER_ISOCHRONOUS:
-    for (int i = 1; i <= 2; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_BULK:
-    for (int i = 3; i <= 5; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    for (int i = 1; i <= 2; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    break;
-  case TUSB_XFER_INTERRUPT:
-    for (int i = 6; i <= 9; ++i) {
-      if (0 == _hcd.pipe[i].ep) return  i;
-    }
-    break;
-  default:
-    /* No support for control transfer */
-    break;
+// TODO merged with DCD
+// Transfer conditions specifiable for each pipe:
+// - Pipe 0: Control transfer with 64-byte single buffer
+// - Pipes 1 and 2: Bulk isochronous transfer continuous transfer mode with programmable buffer size up
+//   to 2 KB and optional double buffer
+// - Pipes 3 to 5: Bulk transfer continuous transfer mode with programmable buffer size up to 2 KB and
+//   optional double buffer
+// - Pipes 6 to 9: Interrupt transfer with 64-byte single buffer
+enum {
+  PIPE_1ST_BULK = 3,
+  PIPE_1ST_INTERRUPT = 6,
+  PIPE_COUNT = 10,
+};
+
+static unsigned find_pipe(unsigned xfer) {
+  switch ( xfer ) {
+    case TUSB_XFER_ISOCHRONOUS:
+      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
+        if ( 0 == _hcd.pipe[i].ep ) return i;
+      }
+      break;
+
+    case TUSB_XFER_BULK:
+      for (int i = PIPE_1ST_BULK; i < PIPE_1ST_INTERRUPT; ++i) {
+        if ( 0 == _hcd.pipe[i].ep ) return i;
+      }
+      for (int i = 1; i < PIPE_1ST_BULK; ++i) {
+        if ( 0 == _hcd.pipe[i].ep ) return i;
+      }
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      for (int i = PIPE_1ST_INTERRUPT; i < PIPE_COUNT; ++i) {
+        if ( 0 == _hcd.pipe[i].ep ) return i;
+      }
+      break;
+
+    default:
+      /* No support for control transfer */
+      break;
   }
   return 0;
 }
 
-static volatile uint16_t* get_pipectr(unsigned num)
+static volatile uint16_t* get_pipectr(rusb2_reg_t *rusb, unsigned num)
 {
   if (num) {
-    return (volatile uint16_t*)&(RUSB2->PIPE_CTR[num - 1]);
+    return (volatile uint16_t*)&(rusb->PIPE_CTR[num - 1]);
   } else {
-    return (volatile uint16_t*)&(RUSB2->DCPCTR);
+    return (volatile uint16_t*)&(rusb->DCPCTR);
   }
 }
 
-static volatile reg_pipetre_t* get_pipetre(unsigned num)
+static volatile reg_pipetre_t* get_pipetre(rusb2_reg_t *rusb, unsigned num)
 {
   volatile reg_pipetre_t* tre = NULL;
   if ((1 <= num) && (num <= 5)) {
-    tre = (volatile reg_pipetre_t*)&(RUSB2->PIPE_TR[num - 1].E);
+    tre = (volatile reg_pipetre_t*)&(rusb->PIPE_TR[num - 1].E);
   }
   return tre;
 }
 
-static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr)
+static volatile uint16_t* addr_to_pipectr(uint8_t rhport, uint8_t dev_addr, unsigned ep_addr)
 {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   const unsigned epn = tu_edpt_number(ep_addr);
+
   if (epn) {
     const unsigned dir_in = tu_edpt_dir(ep_addr);
     const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1];
-    return get_pipectr(num);
+    return get_pipectr(rusb, num);
   } else {
-    return get_pipectr(0);
+    return get_pipectr(rusb, 0);
   }
 }
 
-static unsigned edpt0_max_packet_size(void)
+static uint16_t edpt0_max_packet_size(rusb2_reg_t* rusb)
 {
-  return RUSB2->DCPMAXP_b.MXPS;
+  return rusb->DCPMAXP_b.MXPS;
 }
 
-static unsigned edpt_max_packet_size(unsigned num)
+static uint16_t edpt_max_packet_size(rusb2_reg_t *rusb, unsigned num)
 {
-  RUSB2->PIPESEL = num;
-  return RUSB2->PIPEMAXP_b.MXPS;
+  rusb->PIPESEL = num;
+  return rusb->PIPEMAXP_b.MXPS;
 }
 
-static inline void pipe_wait_for_ready(unsigned num)
+static inline void pipe_wait_for_ready(rusb2_reg_t* rusb, unsigned num)
 {
-  while (RUSB2->D0FIFOSEL_b.CURPIPE != num) ;
-  while (!RUSB2->D0FIFOCTR_b.FRDY) ;
+  while (rusb->D0FIFOSEL_b.CURPIPE != num) ;
+  while (!rusb->D0FIFOCTR_b.FRDY) {}
 }
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
@@ -205,33 +212,33 @@ static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len)
   while (len--) *p++ = *reg;
 }
 
-static bool pipe0_xfer_in(void)
+static bool pipe0_xfer_in(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_hcd.pipe[0];
   const unsigned rem = pipe->remaining;
 
-  const unsigned mps = edpt0_max_packet_size();
-  const unsigned vld = RUSB2->CFIFOCTR_b.DTLN;
+  const unsigned mps = edpt0_max_packet_size(rusb);
+  const unsigned vld = rusb->CFIFOCTR_b.DTLN;
   const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf = pipe->buf;
   if (len) {
-    RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
-    pipe_read_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
+    rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+    pipe_read_packet(buf, (volatile void*)&rusb->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
     return true;
   }
-  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
   return false;
 }
 
-static bool pipe0_xfer_out(void)
+static bool pipe0_xfer_out(rusb2_reg_t* rusb)
 {
   pipe_state_t *pipe = &_hcd.pipe[0];
   const unsigned rem = pipe->remaining;
@@ -239,40 +246,40 @@ static bool pipe0_xfer_out(void)
     pipe->buf = NULL;
     return true;
   }
-  const unsigned mps = edpt0_max_packet_size();
+  const unsigned mps = edpt0_max_packet_size(rusb);
   const unsigned len = TU_MIN(mps, rem);
   void          *buf = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&RUSB2->CFIFO, len);
+    pipe_write_packet(buf, (volatile void*)&rusb->CFIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
   pipe->remaining = rem - len;
   return false;
 }
 
-static bool pipe_xfer_in(unsigned num)
+static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
 {
   pipe_state_t  *pipe = &_hcd.pipe[num];
   const unsigned rem  = pipe->remaining;
 
-  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
-  const unsigned vld  = RUSB2->D0FIFOCTR_b.DTLN;
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_8BIT;
+  const unsigned mps  = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
+  const unsigned vld  = rusb->D0FIFOCTR_b.DTLN;
   const unsigned len  = TU_MIN(TU_MIN(rem, mps), vld);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_read_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
+    pipe_read_packet(buf, (volatile void*)&rusb->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
   }
-  RUSB2->D0FIFOSEL = 0;
-  while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   if ((len < mps) || (rem == len)) {
     pipe->buf = NULL;
@@ -281,7 +288,7 @@ static bool pipe_xfer_in(unsigned num)
   return false;
 }
 
-static bool pipe_xfer_out(unsigned num)
+static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
 {
   pipe_state_t  *pipe = &_hcd.pipe[num];
   const unsigned rem  = pipe->remaining;
@@ -291,37 +298,39 @@ static bool pipe_xfer_out(unsigned num)
     return true;
   }
 
-  RUSB2->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
-  const unsigned mps  = edpt_max_packet_size(num);
-  pipe_wait_for_ready(num);
+  rusb->D0FIFOSEL = num | RUSB2_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
+  const unsigned mps  = edpt_max_packet_size(rusb, num);
+  pipe_wait_for_ready(rusb, num);
   const unsigned len  = TU_MIN(rem, mps);
   void          *buf  = pipe->buf;
   if (len) {
-    pipe_write_packet(buf, (volatile void*)&RUSB2->D0FIFO, len);
+    pipe_write_packet(buf, (volatile void*)&rusb->D0FIFO, len);
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
   }
-  RUSB2->D0FIFOSEL = 0;
-  while (RUSB2->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
+  rusb->D0FIFOSEL = 0;
+  while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
   pipe->remaining = rem - len;
   return false;
 }
 
-static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+static bool process_pipe0_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
 {
   (void)dev_addr;
+
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   const unsigned dir_in = tu_edpt_dir(ep_addr);
 
   /* configure fifo direction and access unit settings */
   if (dir_in) { /* IN, a byte */
-    RUSB2->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
-    while (RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
+    rusb->CFIFOSEL = RUSB2_FIFOSEL_MBW_8BIT;
+    while (rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE) ;
   } else { /* OUT, 2 bytes */
-    RUSB2->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
+    rusb->CFIFOSEL = RUSB2_CFIFOSEL_ISEL_WRITE | RUSB2_FIFOSEL_MBW_16BIT |
                          (TU_BYTE_ORDER == TU_BIG_ENDIAN ? RUSB2_FIFOSEL_BIGEND : 0);
-    while (!(RUSB2->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
+    while (!(rusb->CFIFOSEL & RUSB2_CFIFOSEL_ISEL_WRITE)) ;
   }
 
   pipe_state_t *pipe = &_hcd.pipe[0];
@@ -331,26 +340,28 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
   if (buflen) {
     pipe->buf     = buffer;
     if (!dir_in) { /* OUT */
-      TU_ASSERT(RUSB2->DCPCTR_b.BSTS && (RUSB2->USBREQ & 0x80));
-      pipe0_xfer_out();
+      TU_ASSERT(rusb->DCPCTR_b.BSTS && (rusb->USBREQ & 0x80));
+      pipe0_xfer_out(rusb);
     }
   } else { /* ZLP */
     pipe->buf        = NULL;
     if (!dir_in) { /* OUT */
-      RUSB2->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      rusb->CFIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
     }
-    if (dir_in == RUSB2->DCPCFG_b.DIR) {
-      TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == RUSB2->DCPCTR_b.PID);
-      RUSB2->DCPCTR_b.SQSET = 1;
-      RUSB2->DCPCFG_b.DIR = dir_in ^ 1;
+    if (dir_in == rusb->DCPCFG_b.DIR) {
+      TU_ASSERT(RUSB2_PIPE_CTR_PID_NAK == rusb->DCPCTR_b.PID);
+      rusb->DCPCTR_b.SQSET = 1;
+      rusb->DCPCFG_b.DIR = dir_in ^ 1;
     }
   }
-  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_BUF;
   return true;
 }
 
-static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen)
+static bool process_pipe_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen)
 {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
   const unsigned epn    = tu_edpt_number(ep_addr);
   const unsigned dir_in = tu_edpt_dir(ep_addr);
   const unsigned num    = _hcd.ep[dev_addr - 1][dir_in][epn - 1];
@@ -363,19 +374,19 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u
   pipe->remaining = buflen;
   if (!dir_in) { /* OUT */
     if (buflen) {
-      pipe_xfer_out(num);
+      pipe_xfer_out(rusb, num);
     } else { /* ZLP */
-      RUSB2->D0FIFOSEL = num;
-      pipe_wait_for_ready(num);
-      RUSB2->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
-      RUSB2->D0FIFOSEL = 0;
-      while (RUSB2->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
+      rusb->D0FIFOSEL = num;
+      pipe_wait_for_ready(rusb, num);
+      rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      rusb->D0FIFOSEL = 0;
+      while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
     }
   } else {
-    volatile uint16_t     *ctr = get_pipectr(num);
-    volatile reg_pipetre_t *pt = get_pipetre(num);
+    volatile uint16_t     *ctr = get_pipectr(rusb, num);
+    volatile reg_pipetre_t *pt = get_pipetre(rusb, num);
     if (pt) {
-      const unsigned     mps = edpt_max_packet_size(num);
+      const unsigned     mps = edpt_max_packet_size(rusb, num);
       if (*ctr & 0x3) *ctr = RUSB2_PIPE_CTR_PID_NAK;
       pt->TRE   = TU_BIT(8);
       pt->TRN   = (buflen + mps - 1) / mps;
@@ -386,20 +397,20 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, u
   return true;
 }
 
-static bool process_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
+static bool process_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
 {
   const unsigned epn = tu_edpt_number(ep_addr);
   if (0 == epn) {
-    return process_pipe0_xfer(dev_addr, ep_addr, buffer, buflen);
+    return process_pipe0_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
   } else {
-    return process_pipe_xfer(dev_addr, ep_addr, buffer, buflen);
+    return process_pipe_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
   }
 }
 
 static void process_pipe0_bemp(uint8_t rhport)
 {
-  (void)rhport;
-  bool completed = pipe0_xfer_out();
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  bool completed = pipe0_xfer_out(rusb);
   if (completed) {
     pipe_state_t *pipe = &_hcd.pipe[0];
     hcd_event_xfer_complete(pipe->dev,
@@ -411,9 +422,9 @@ static void process_pipe0_bemp(uint8_t rhport)
 
 static void process_pipe_nrdy(uint8_t rhport, unsigned num)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   xfer_result_t result;
-  uint16_t volatile *ctr = get_pipectr(num);
+  uint16_t volatile *ctr = get_pipectr(rusb, num);
   TU_LOG(TU_RUSB2_HCD_DBG, "NRDY %d %x\n", num, *ctr);
   switch (*ctr & RUSB2_PIPE_CTR_PID_Msk) {
     default: return;
@@ -429,19 +440,19 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
 
 static void process_pipe_brdy(uint8_t rhport, unsigned num)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   pipe_state_t  *pipe   = &_hcd.pipe[num];
   const unsigned dir_in = tu_edpt_dir(pipe->ep);
   bool completed;
 
   if (dir_in) { /* IN */
     if (num) {
-      completed = pipe_xfer_in(num);
+      completed = pipe_xfer_in(rusb, num);
     } else {
-      completed = pipe0_xfer_in();
+      completed = pipe0_xfer_in(rusb);
     }
   } else {
-    completed = pipe_xfer_out(num);
+    completed = pipe_xfer_out(rusb, num);
   }
   if (completed) {
     hcd_event_xfer_complete(pipe->dev, pipe->ep,
@@ -539,86 +550,88 @@ bool hcd_init(uint8_t rhport)
   return true;
 }
 
-void hcd_int_enable(uint8_t rhport)
-{
+void hcd_int_enable(uint8_t rhport) {
   rusb2_int_enable(rhport);
 }
 
-void hcd_int_disable(uint8_t rhport)
-{
+void hcd_int_disable(uint8_t rhport) {
   rusb2_int_disable(rhport);
 }
 
 uint32_t hcd_frame_number(uint8_t rhport)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+
   /* The device must be reset at least once after connection
    * in order to start the frame counter. */
   if (_hcd.need_reset) hcd_port_reset(rhport);
-  return RUSB2->FRMNUM_b.FRNM;
+  return rusb->FRMNUM_b.FRNM;
 }
 
 /*--------------------------------------------------------------------+
  * Port API
  *--------------------------------------------------------------------+*/
-bool hcd_port_connect_status(uint8_t rhport)
-{
-  (void)rhport;
-  return RUSB2->INTSTS1_b.ATTCH ? true : false;
+bool hcd_port_connect_status(uint8_t rhport) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  return rusb->INTSTS1_b.ATTCH ? true : false;
 }
 
-void hcd_port_reset(uint8_t rhport)
-{
-  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
-  while (RUSB2->DCPCTR_b.PBUSY) ;
+void hcd_port_reset(uint8_t rhport) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+  while (rusb->DCPCTR_b.PBUSY) {}
+
   hcd_int_disable(rhport);
-  RUSB2->DVSTCTR0_b.UACT = 0;
-  if (RUSB2->DCPCTR_b.SUREQ) {
-    RUSB2->DCPCTR_b.SUREQCLR = 1;
+  rusb->DVSTCTR0_b.UACT = 0;
+  if (rusb->DCPCTR_b.SUREQ) {
+    rusb->DCPCTR_b.SUREQCLR = 1;
   }
   hcd_int_enable(rhport);
+
   /* Reset should be asserted 10-20ms. */
-  RUSB2->DVSTCTR0_b.USBRST = 1;
-  for (volatile int i = 0; i < 2400000; ++i) ;
-  RUSB2->DVSTCTR0_b.USBRST = 0;
-  RUSB2->DVSTCTR0_b.UACT = 1;
+  rusb->DVSTCTR0_b.USBRST = 1;
+  for (volatile int i = 0; i < 2400000; ++i) {}
+  rusb->DVSTCTR0_b.USBRST = 0;
+
+  rusb->DVSTCTR0_b.UACT = 1;
   _hcd.need_reset = false;
 }
 
-void hcd_port_reset_end(uint8_t rhport)
-{
+void hcd_port_reset_end(uint8_t rhport) {
   (void) rhport;
 }
 
-tusb_speed_t hcd_port_speed_get(uint8_t rhport)
-{
-  (void)rhport;
-  switch (RUSB2->DVSTCTR0_b.RHST) {
-    default: return TUSB_SPEED_INVALID;
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  switch (rusb->DVSTCTR0_b.RHST) {
+    case RUSB2_DVSTCTR0_RHST_HS: return TUSB_SPEED_HIGH;
     case RUSB2_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL;
-    case RUSB2_DVSTCTR0_RHST_LS:  return TUSB_SPEED_LOW;
+    case RUSB2_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW;
+    default: return TUSB_SPEED_INVALID;
   }
 }
 
-void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
-{
-  (void)rhport;
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
   uint16_t volatile *ctr;
+
   TU_ASSERT(dev_addr < 6,); /* USBa can only handle addresses from 0 to 5. */
   if (!dev_addr) return;
+
   _hcd.ctl_mps[dev_addr] = 0;
   uint8_t *ep = &_hcd.ep[dev_addr - 1][0][0];
+
   for (int i = 0; i < 2 * 15; ++i, ++ep) {
     unsigned num = *ep;
     if (!num || (dev_addr != _hcd.pipe[num].dev)) continue;
 
-    ctr = (uint16_t volatile*)&RUSB2->PIPE_CTR[num - 1];
+    ctr = (uint16_t volatile*)&rusb->PIPE_CTR[num - 1];
     *ctr = 0;
-    RUSB2->NRDYENB &= ~TU_BIT(num);
-    RUSB2->BRDYENB &= ~TU_BIT(num);
-    RUSB2->PIPESEL = num;
-    RUSB2->PIPECFG = 0;
-    RUSB2->PIPEMAXP = 0;
+    rusb->NRDYENB &= ~TU_BIT(num);
+    rusb->BRDYENB &= ~TU_BIT(num);
+    rusb->PIPESEL = num;
+    rusb->PIPECFG = 0;
+    rusb->PIPEMAXP = 0;
 
     _hcd.pipe[num].ep  = 0;
     _hcd.pipe[num].dev = 0;
@@ -631,52 +644,54 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
  *--------------------------------------------------------------------+*/
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
 {
-  (void)rhport;
-  TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, RUSB2->DCPCTR);
-
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
-  TU_ASSERT(0 == RUSB2->DCPCTR_b.SUREQ);
 
-  RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  TU_LOG(TU_RUSB2_HCD_DBG, "S %d %x\n", dev_addr, rusb->DCPCTR);
+
+  TU_ASSERT(0 == rusb->DCPCTR_b.SUREQ);
+
+  rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
 
   _hcd.pipe[0].buf       = NULL;
   _hcd.pipe[0].length    = 8;
   _hcd.pipe[0].remaining = 0;
   _hcd.pipe[0].dev       = dev_addr;
 
-  while (RUSB2->DCPCTR_b.PBUSY) ;
-  RUSB2->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
+  while (rusb->DCPCTR_b.PBUSY) ;
+  rusb->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
 
   /* Set direction in advance for DATA stage */
   uint8_t const bmRequesttype = setup_packet[0];
-  RUSB2->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
+  rusb->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
 
   uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
-  RUSB2->USBREQ  = tu_htole16(p[0]);
-  RUSB2->USBVAL  = p[1];
-  RUSB2->USBINDX = p[2];
-  RUSB2->USBLENG = p[3];
+  rusb->USBREQ  = tu_htole16(p[0]);
+  rusb->USBVAL  = p[1];
+  rusb->USBINDX = p[2];
+  rusb->USBLENG = p[3];
 
-  RUSB2->DCPCTR_b.SUREQ = 1;
+  rusb->DCPCTR_b.SUREQ = 1;
   return true;
 }
 
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc)
 {
-  (void)rhport;
   TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
 
   const unsigned ep_addr = ep_desc->bEndpointAddress;
   const unsigned epn     = tu_edpt_number(ep_addr);
   const unsigned mps     = tu_edpt_packet_size(ep_desc);
+
   if (0 == epn) {
-    RUSB2->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
+    rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK;
     hcd_devtree_info_t devtree;
     hcd_devtree_get_info(dev_addr, &devtree);
-    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &RUSB2->DEVADD[0];
+    uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &rusb->DEVADD[0];
     devadd += dev_addr;
-    while (RUSB2->DCPCTR_b.PBUSY) ;
-    RUSB2->DCPMAXP = (dev_addr << 12) | mps;
+    while (rusb->DCPCTR_b.PBUSY) {}
+    rusb->DCPMAXP = (dev_addr << 12) | mps;
     *devadd = (TUSB_SPEED_FULL == devtree.speed) ? RUSB2_DEVADD_USBSPD_FS : RUSB2_DEVADD_USBSPD_LS;
     _hcd.ctl_mps[dev_addr] = mps;
     return true;
@@ -690,17 +705,20 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   }
   const unsigned num = find_pipe(xfer);
   if (!num) return false;
+
   _hcd.pipe[num].dev = dev_addr;
   _hcd.pipe[num].ep  = ep_addr;
   _hcd.ep[dev_addr - 1][dir_in][epn - 1] = num;
 
   /* setup pipe */
   hcd_int_disable(rhport);
-  RUSB2->PIPESEL = num;
-  RUSB2->PIPEMAXP = (dev_addr << 12) | mps;
-  volatile uint16_t *ctr = get_pipectr(num);
+
+  rusb->PIPESEL = num;
+  rusb->PIPEMAXP = (dev_addr << 12) | mps;
+  volatile uint16_t *ctr = get_pipectr(rusb, num);
   *ctr = RUSB2_PIPE_CTR_ACLRM_Msk | RUSB2_PIPE_CTR_SQCLR_Msk;
   *ctr = 0;
+
   unsigned cfg = ((1 ^ dir_in) << 4) | epn;
   if (xfer == TUSB_XFER_BULK) {
     cfg |= RUSB2_PIPECFG_TYPE_BULK | RUSB2_PIPECFG_SHTNAK_Msk | RUSB2_PIPECFG_DBLB_Msk;
@@ -709,13 +727,16 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   } else {
     cfg |= RUSB2_PIPECFG_TYPE_ISO | RUSB2_PIPECFG_DBLB_Msk;
   }
-  RUSB2->PIPECFG = cfg;
-  RUSB2->BRDYSTS = 0x1FFu ^ TU_BIT(num);
-  RUSB2->NRDYENB |= TU_BIT(num);
-  RUSB2->BRDYENB |= TU_BIT(num);
+
+  rusb->PIPECFG = cfg;
+  rusb->BRDYSTS = 0x1FFu ^ TU_BIT(num);
+  rusb->NRDYENB |= TU_BIT(num);
+  rusb->BRDYENB |= TU_BIT(num);
+
   if (!dir_in) {
     *ctr = RUSB2_PIPE_CTR_PID_BUF;
   }
+
   hcd_int_enable(rhport);
 
   return true;
@@ -726,14 +747,15 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b
   bool r;
   hcd_int_disable(rhport);
   TU_LOG(TU_RUSB2_HCD_DBG, "X %d %x %u\n", dev_addr, ep_addr, buflen);
-  r = process_edpt_xfer(dev_addr, ep_addr, buffer, buflen);
+  r = process_edpt_xfer(rhport, dev_addr, ep_addr, buffer, buflen);
   hcd_int_enable(rhport);
   return r;
 }
 
 bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 {
-  uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr);
+  uint8_t rhport = 0; // FIXME change API
+  uint16_t volatile *ctr = addr_to_pipectr(rhport, dev_addr, ep_addr);
   TU_ASSERT(ctr);
 
   const uint32_t pid = *ctr & 0x3;
@@ -756,67 +778,73 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
 //--------------------------------------------------------------------+
 void hcd_int_handler(uint8_t rhport)
 {
-  (void)rhport;
+  rusb2_reg_t* rusb = RUSB2_REG(rhport);
+  static unsigned char attach_attempt = 0;
+  unsigned is0 = rusb->INTSTS0;
+  unsigned is1 = rusb->INTSTS1;
+
+  /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
+  rusb->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
+  rusb->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
+
+  TU_LOG3("IS %04x %04x\n", is0, is1);
+  is1 &= rusb->INTENB1;
+  is0 &= rusb->INTENB0;
+
+  if (is1 & RUSB2_INTSTS1_SACK_Msk) {
+    /* Set DATA1 in advance for the next transfer. */
+    rusb->DCPCTR_b.SQSET = 1;
+    attach_attempt = 0;
+    hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
+  }
+
+  if (is1 & RUSB2_INTSTS1_SIGN_Msk) {
+    hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
+    if(attach_attempt > 0) {
+      rusb->DVSTCTR0_b.UACT = 1;
+      _hcd.need_reset = true;
+      rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
+      hcd_event_device_attach(rhport, true);
+    }
+    attach_attempt--;
+  }
+
+  if (is1 & RUSB2_INTSTS1_ATTCH_Msk) {
+    attach_attempt = 10;
+    rusb->DVSTCTR0_b.UACT = 1;
+    _hcd.need_reset = true;
+    rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
+    hcd_event_device_attach(rhport, true);
+  }
+
+  if (is1 & RUSB2_INTSTS1_DTCH_Msk) {
+    rusb->DVSTCTR0_b.UACT = 0;
+    if (rusb->DCPCTR_b.SUREQ) {
+      rusb->DCPCTR_b.SUREQCLR = 1;
+    }
+    rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk;
+    hcd_event_device_remove(rhport, true);
+  }
+
+  if (is0 & RUSB2_INTSTS0_BEMP_Msk) {
+    const unsigned s = rusb->BEMPSTS;
+    rusb->BEMPSTS = 0;
+    if (s & 1) {
+      process_pipe0_bemp(rhport);
+    }
+  }
+
 #if defined(__CCRX__)
   static const int Mod37BitPosition[] = {
     -1, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13, 4,
     7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9, 5,
     20, 8, 19, 18};
 #endif
-  static unsigned char attach_attempt = 0;
-  unsigned is1 = RUSB2->INTSTS1;
-  unsigned is0 = RUSB2->INTSTS0;
 
-  /* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
-  RUSB2->INTSTS1 = ~((RUSB2_INTSTS1_SACK_Msk | RUSB2_INTSTS1_SIGN_Msk | RUSB2_INTSTS1_ATTCH_Msk | RUSB2_INTSTS1_DTCH_Msk) & is1);
-  RUSB2->INTSTS0 = ~((RUSB2_INTSTS0_BRDY_Msk | RUSB2_INTSTS0_NRDY_Msk | RUSB2_INTSTS0_BEMP_Msk) & is0);
-  TU_LOG(TU_RUSB2_HCD_DBG, "IS %04x %04x\n", is0, is1);
-  is1 &= RUSB2->INTENB1;
-  is0 &= RUSB2->INTENB0;
-
-  if (is1 & RUSB2_INTSTS1_SACK_Msk) {
-    /* Set DATA1 in advance for the next transfer. */
-    RUSB2->DCPCTR_b.SQSET = 1;
-    attach_attempt = 0;
-    hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
-  }
-  if (is1 & RUSB2_INTSTS1_SIGN_Msk) {
-    hcd_event_xfer_complete(RUSB2->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
-    if(attach_attempt > 0) {
-      RUSB2->DVSTCTR0_b.UACT = 1;
-      _hcd.need_reset = true;
-      RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
-      hcd_event_device_attach(rhport, true);
-    }
-    attach_attempt--;
-  }
-  if (is1 & RUSB2_INTSTS1_ATTCH_Msk) {
-    attach_attempt = 10;
-    RUSB2->DVSTCTR0_b.UACT = 1;
-    _hcd.need_reset = true;
-    RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
-    hcd_event_device_attach(rhport, true);
-  }
-  if (is1 & RUSB2_INTSTS1_DTCH_Msk) {
-    RUSB2->DVSTCTR0_b.UACT = 0;
-    if (RUSB2->DCPCTR_b.SUREQ) {
-      RUSB2->DCPCTR_b.SUREQCLR = 1;
-    }
-    RUSB2->INTENB1 = (RUSB2->INTENB1 & ~RUSB2_INTSTS1_DTCH_Msk) | RUSB2_INTSTS1_ATTCH_Msk;
-    hcd_event_device_remove(rhport, true);
-  }
-
-  if (is0 & RUSB2_INTSTS0_BEMP_Msk) {
-    const unsigned s = RUSB2->BEMPSTS;
-    RUSB2->BEMPSTS = 0;
-    if (s & 1) {
-      process_pipe0_bemp(rhport);
-    }
-  }
   if (is0 & RUSB2_INTSTS0_NRDY_Msk) {
-    const unsigned m = RUSB2->NRDYENB;
-    unsigned s = RUSB2->NRDYSTS & m;
-    RUSB2->NRDYSTS = ~s;
+    const unsigned m = rusb->NRDYENB;
+    unsigned s = rusb->NRDYSTS & m;
+    rusb->NRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       const unsigned num = Mod37BitPosition[(-s & s) % 37];
@@ -828,10 +856,10 @@ void hcd_int_handler(uint8_t rhport)
     }
   }
   if (is0 & RUSB2_INTSTS0_BRDY_Msk) {
-    const unsigned m = RUSB2->BRDYENB;
-    unsigned s = RUSB2->BRDYSTS & m;
+    const unsigned m = rusb->BRDYENB;
+    unsigned s = rusb->BRDYSTS & m;
     /* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
-    RUSB2->BRDYSTS = ~s;
+    rusb->BRDYSTS = ~s;
     while (s) {
 #if defined(__CCRX__)
       const unsigned num = Mod37BitPosition[(-s & s) % 37];

From c37a9571741cef0dcf0cd5a77e202ae741a2dd42 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Jul 2023 19:56:48 +0700
Subject: [PATCH 1930/2085] correct hcd_edpt_clear_stall() API signature

---
 src/host/hcd.h                                 | 2 +-
 src/portable/mentor/musb/hcd_musb.c            | 4 ++--
 src/portable/nxp/khci/hcd_khci.c               | 4 ++--
 src/portable/ohci/ohci.c                       | 4 ++--
 src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 4 ++--
 src/portable/raspberrypi/rp2040/hcd_rp2040.c   | 4 ++--
 src/portable/renesas/rusb2/hcd_rusb2.c         | 4 ++--
 7 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 50f1dcdcc..898e0c6a4 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -179,7 +179,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
 
 // clear stall, data toggle is also reset to DATA0
-bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr);
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
 // USBH implemented API
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 5be67a186..5d1fba6d9 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -831,8 +831,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 }
 
 // clear stall, data toggle is also reset to DATA0
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   unsigned const pipenum = find_pipe(dev_addr, ep_addr);
   if (!pipenum) return false;
   hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1);
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 6784049c5..928564e26 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -570,8 +570,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   if (!tu_edpt_number(ep_addr)) return true;
   int num = find_pipe(dev_addr, ep_addr);
   if (num < 0) return false;
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 9f3af4781..413e72037 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -556,8 +556,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   ohci_ed_t * const p_ed = ed_from_addr(dev_addr, ep_addr);
 
   p_ed->is_stalled = 0;
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index bb41ad638..45a3e80ef 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -163,8 +163,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 //    return busy;
 //}
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   (void) dev_addr;
   (void) ep_addr;
 
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 5091fa907..6db8e2a0a 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -625,8 +625,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
   return true;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   (void) dev_addr;
   (void) ep_addr;
 
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 0a75d0b47..292d40da8 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -718,8 +718,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
-bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
   uint16_t volatile *ctr = addr_to_pipectr(dev_addr, ep_addr);
   TU_ASSERT(ctr);
 

From 10575c1b380136ce9381393c33e982cea7ef4731 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 26 Jul 2023 20:48:18 +0700
Subject: [PATCH 1931/2085] mising ehci

---
 src/host/hcd.h           | 2 +-
 src/portable/ehci/ehci.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index 898e0c6a4..d77dd6e2f 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -179,7 +179,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
 
 // clear stall, data toggle is also reset to DATA0
-bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr);
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 
 //--------------------------------------------------------------------+
 // USBH implemented API
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 241393a39..979069cfa 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -502,8 +502,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return still_active; // true if removed an active transfer
 }
 
-bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr)
-{
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) {
+  (void) rhport;
   ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr);
   qhd->qtd_overlay.halted = 0;
   hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));

From 5a29db2787fea0ff9fe236d2631b2dcbc94aea50 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 27 Jul 2023 15:52:55 +0700
Subject: [PATCH 1932/2085] add check for edpt_xfer() with halted, also reset
 data toggle when clear stall

---
 src/portable/ehci/ehci.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index b84de5191..02b843667 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -443,6 +443,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
   ehci_qtd_t* qtd;
 
   if (epnum == 0) {
+    // Control endpoint never be stalled. Skip reset Data Toggle since it is fixed per stage
+    if (qhd->qtd_overlay.halted) {
+      qhd->qtd_overlay.halted = false;
+    }
+
     qtd = qtd_control(dev_addr);
     qtd_init(qtd, buffer, buflen);
 
@@ -450,6 +455,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     qtd->data_toggle = 1;
     qtd->pid = dir ? EHCI_PID_IN : EHCI_PID_OUT;
   } else {
+    // skip if endpoint is halted
+    TU_VERIFY(!qhd->qtd_overlay.halted);
+
     qtd = qtd_find_free();
     TU_ASSERT(qtd);
 
@@ -506,8 +514,9 @@ bool hcd_edpt_clear_stall(uint8_t daddr, uint8_t ep_addr)
 {
   ehci_qhd_t *qhd = qhd_get_from_addr(daddr, ep_addr);
   qhd->qtd_overlay.halted = 0;
+  qhd->qtd_overlay.data_toggle = 0;
   hcd_dcache_clean_invalidate(qhd, sizeof(ehci_qhd_t));
-  // TODO reset data toggle ?
+
   return true;
 }
 
@@ -881,8 +890,10 @@ static void qhd_remove_qtd(ehci_qhd_t *qhd) {
 
   qhd->attached_qtd = NULL;
   qhd->attached_buffer = 0;
+  hcd_dcache_clean(qhd, sizeof(ehci_qhd_t));
 
   qtd->used = 0; // free QTD
+  hcd_dcache_clean(qtd, sizeof(ehci_qtd_t));
 }
 
 //--------------------------------------------------------------------+

From 6021803d584a95efac5bc10f89ed970b2c1fa60e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Jul 2023 11:33:26 +0700
Subject: [PATCH 1933/2085] fix ci

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 13 ++++++-------
 src/portable/renesas/rusb2/rusb2_ra.h  |  9 ++++++---
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 83f0fdc4a..0380f36b9 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -49,17 +49,16 @@
     #define D0FIFOCTR CFIFOCTR
     #define D0FIFOCTR_b CFIFOCTR_b
   #endif
+
+  // Application API for setting IRQ number
+  void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
+    rusb2_controller[rhport].irqnum = irqnum;
+  }
+
 #else
   #error "Unsupported MCU"
 #endif
 
-//--------------------------------------------------------------------+
-// Application API for setting IRQ number
-//--------------------------------------------------------------------+
-void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
-  rusb2_controller[rhport].irqnum = irqnum;
-}
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 8a4d2ad36..7ff272bbc 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -64,8 +64,14 @@ typedef struct {
 #if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
   #define RUSB2_SUPPORT_HIGHSPEED
   #define RUSB2_CONTROLLER_COUNT 2
+
+  #define rusb2_is_highspeed_rhport(_p)  (_p == 1)
+  #define rusb2_is_highspeed_reg(_reg)   (_reg == RUSB2_REG(1))
 #else
   #define RUSB2_CONTROLLER_COUNT 1
+
+  #define rusb2_is_highspeed_rhport(_p)  (false)
+  #define rusb2_is_highspeed_reg(_reg)   (false)
 #endif
 
 // USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
@@ -78,9 +84,6 @@ static rusb2_controller_t rusb2_controller[] = {
 
 #define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
 
-#define rusb2_is_highspeed_rhport(_p)  (_p == 1)
-#define rusb2_is_highspeed_reg(_reg)   (_reg == RUSB2_REG(1))
-
 //--------------------------------------------------------------------+
 // RUSB2 API
 //--------------------------------------------------------------------+

From e56d5443a8a87e932b22bc6315f30cd537fe0edf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Jul 2023 12:42:40 +0700
Subject: [PATCH 1934/2085] - revert usb address - more clean up

---
 src/portable/renesas/rusb2/dcd_rusb2.c |  6 +++---
 src/portable/renesas/rusb2/hcd_rusb2.c | 14 ++++----------
 2 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 0380f36b9..9383923bd 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -51,7 +51,7 @@
   #endif
 
   // Application API for setting IRQ number
-  void tud_int_set_irqnum(uint8_t rhport, int32_t irqnum) {
+  void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
     rusb2_controller[rhport].irqnum = irqnum;
   }
 
@@ -638,7 +638,7 @@ static void process_bus_reset(uint8_t rhport)
 static void process_set_address(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
-  const uint32_t addr = rusb->USBADDR & 0xFF;
+  const uint16_t addr = rusb->USBADDR_b.USBADDR;
   if (!addr) return;
 
   const tusb_control_request_t setup_packet = {
@@ -821,7 +821,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
 
   if ( rusb2_is_highspeed_rhport(rhport) ) {
     // FIXME shouldn't be after pipe selection and config, also the BUFNMB should be changed
-    // depending on the allocation scheme
+    //       depending on the allocation scheme
     rusb->PIPEBUF = 0x7C08;
   }
 
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index fef8bdf19..c5ed8ae55 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -32,21 +32,15 @@
 #include "host/hcd.h"
 #include "rusb2_type.h"
 
-#if !defined(CFG_TUSB_RHPORT0_MODE) && !defined(CFG_TUSB_RHPORT1_MODE)
-// fallback
-#define CFG_TUSB_RHPORT0_MODE   OPT_MODE_HOST
-#define CFG_TUSB_RHPORT1_MODE   0
-#endif
-
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
 
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
   #include "rusb2_ra.h"
 
-  void osal_task_delay(uint32_t msec) {
-    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
-  }
+//  void osal_task_delay(uint32_t msec) {
+//    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
+//  }
 
 #else
   #error "Unsupported MCU"
@@ -785,7 +779,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 void hcd_int_handler(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
-  static unsigned char attach_attempt = 0;
+  static unsigned char attach_attempt = 0; // TODO remove later
   unsigned is0 = rusb->INTSTS0;
   unsigned is1 = rusb->INTSTS1;
 

From 8226b046a99a25f483f99fe44c29066f3f1d7f7b Mon Sep 17 00:00:00 2001
From: 0xCCF4 <20901343+0xCCF4@users.noreply.github.com>
Date: Fri, 28 Jul 2023 11:19:08 +0200
Subject: [PATCH 1935/2085] Fixed typo in rp2040 hw bspw family.c

---
 hw/bsp/rp2040/family.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 097e6fbd6..40e3f11cd 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -149,7 +149,7 @@ void board_init(void)
 #endif
 
 #ifdef UART_DEV
-  bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_TX_PIN, GPIO_FUNC_UART));
+  bi_decl(bi_2pins_with_func(UART_TX_PIN, UART_RX_PIN, GPIO_FUNC_UART));
   uart_inst = uart_get_instance(UART_DEV);
   stdio_uart_init_full(uart_inst, CFG_BOARD_UART_BAUDRATE, UART_TX_PIN, UART_RX_PIN);
 #endif

From feb58ebd54e68bc3b7f21b0d168417053c525f0a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 28 Jul 2023 19:01:12 +0700
Subject: [PATCH 1936/2085] add uno r4 wih FLASH_IMAGE_START=0x4000, running
 but interrupt (systick) does not seems to work

---
 .idea/runConfigurations/ra4m1.xml             |  2 +-
 .idea/runConfigurations/ra6m1.xml             |  2 +-
 .idea/runConfigurations/ra6m5.xml             |  2 +-
 .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 18 ++--
 hw/bsp/ra/boards/uno_r4/board.cmake           | 11 +++
 hw/bsp/ra/boards/uno_r4/board.h               | 53 +++++++++++
 hw/bsp/ra/boards/uno_r4/board.mk              |  9 ++
 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h | 35 ++++++++
 .../uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h   |  5 ++
 .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h       | 11 +++
 .../uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h   | 87 +++++++++++++++++++
 .../ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h  | 21 +++++
 hw/bsp/ra/boards/uno_r4/uno_r4.ld             | 25 ++++++
 hw/bsp/ra/family.mk                           |  3 +-
 src/portable/renesas/rusb2/hcd_rusb2.c        |  1 +
 15 files changed, 272 insertions(+), 13 deletions(-)
 create mode 100644 hw/bsp/ra/boards/uno_r4/board.cmake
 create mode 100644 hw/bsp/ra/boards/uno_r4/board.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/board.mk
 create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h
 create mode 100644 hw/bsp/ra/boards/uno_r4/uno_r4.ld

diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml
index 22bb61949..149a157c4 100644
--- a/.idea/runConfigurations/ra4m1.xml
+++ b/.idea/runConfigurations/ra4m1.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml
index 438ac4063..57af9abd9 100644
--- a/.idea/runConfigurations/ra6m1.xml
+++ b/.idea/runConfigurations/ra6m1.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml
index 89f9787a0..1a6358304 100644
--- a/.idea/runConfigurations/ra6m5.xml
+++ b/.idea/runConfigurations/ra6m5.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc_hid">
+  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc_hid">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
index 3bde2db0d..72cdb89e6 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -12,16 +12,16 @@
 #define BSP_MOCO_HZ                 (8000000)
 #define BSP_SUB_CLOCK_HZ            (32768)
 #if   BSP_CFG_HOCO_FREQUENCY == 0
-#define BSP_HOCO_HZ             (24000000)
+  #define BSP_HOCO_HZ             (24000000)
 #elif BSP_CFG_HOCO_FREQUENCY == 2
-                #define BSP_HOCO_HZ             (32000000)
-            #elif BSP_CFG_HOCO_FREQUENCY == 4
-                #define BSP_HOCO_HZ             (48000000)
-            #elif BSP_CFG_HOCO_FREQUENCY == 5
-                #define BSP_HOCO_HZ             (64000000)
-            #else
-                #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
-            #endif
+  #define BSP_HOCO_HZ             (32000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 4
+  #define BSP_HOCO_HZ             (48000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 5
+  #define BSP_HOCO_HZ             (64000000)
+#else
+  #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
 #define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
 
diff --git a/hw/bsp/ra/boards/uno_r4/board.cmake b/hw/bsp/ra/boards/uno_r4/board.cmake
new file mode 100644
index 000000000..34780d776
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.cmake
@@ -0,0 +1,11 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra4m1)
+
+set(JLINK_DEVICE R7FA4M1AB)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+#  target_compile_definitions(${TARGET} PUBLIC)
+#  target_sources(${TARGET} PRIVATE)
+#  target_include_directories(${BOARD_TARGET} PUBLIC)
+endfunction()
diff --git a/hw/bsp/ra/boards/uno_r4/board.h b/hw/bsp/ra/boards/uno_r4/board.h
new file mode 100644
index 000000000..72abda27f
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.h
@@ -0,0 +1,53 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1          BSP_IO_PORT_01_PIN_11 // D13
+#define LED_STATE_ON  1
+
+#define SW1                   BSP_IO_PORT_01_PIN_10 // D12
+#define BUTTON_STATE_ACTIVE   0
+
+static const ioport_pin_cfg_t board_pin_cfg[] = {
+    {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
+    {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
+    // USB FS D+, D-, VBus
+    {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+    {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+    {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk
new file mode 100644
index 000000000..cbe6c782c
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/board.mk
@@ -0,0 +1,9 @@
+CPU_CORE = cortex-m4
+MCU_VARIANT = ra4m1
+
+LD_FILE = $(BOARD_PATH)/${BOARD}.ld
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA4M1AB
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..c1d1022cc
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,35 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+
+#undef RA_NOT_DEFINED
+#define BSP_CFG_RTOS (0)
+#if defined(_RA_BOOT_IMAGE)
+#define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x800)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT     ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0)
+
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE	(0)
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE		(0)
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED	(0)
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..444d32e56
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (4)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..336918800
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M1AB3CNE
+#define BSP_MCU_FEATURE_SET ('A')
+#define BSP_ROM_SIZE_BYTES (262144)
+#define BSP_RAM_SIZE_BYTES (32768)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_QFN
+#define BSP_PACKAGE_PINS (48)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..fc604eb3b
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,87 @@
+/* generated configuration header file through renesas e2 studio */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA4M1 (1)
+#define BSP_LOCO_HZ                 (32768)
+#define BSP_MOCO_HZ                 (8000000)
+#define BSP_SUB_CLOCK_HZ            (32768)
+#if   BSP_CFG_HOCO_FREQUENCY == 0
+  #define BSP_HOCO_HZ             (24000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+  #define BSP_HOCO_HZ             (32000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 4
+  #define BSP_HOCO_HZ             (48000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 5
+  #define BSP_HOCO_HZ             (64000000)
+#else
+  #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES       (48U)
+#define BSP_MCU_VBATT_SUPPORT       (1)
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+/*
+ ID Code
+ Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+ WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+ */
+#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+            #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+            #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+            #else
+/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..63618ec4b
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,21 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: XTAL */
+#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12, 0) /* PLL Mul x12 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Src: SUBCLK */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/uno_r4.ld b/hw/bsp/ra/boards/uno_r4/uno_r4.ld
new file mode 100644
index 000000000..45f11dfb1
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/uno_r4.ld
@@ -0,0 +1,25 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x8000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x40000;
+DATA_FLASH_START = 0x40100000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x00000000;
+OPTION_SETTING_LENGTH = 0x0;
+OPTION_SETTING_S_START = 0x80000000;
+OPTION_SETTING_S_LENGTH = 0x0;
+ID_CODE_START = 0x01010018;
+ID_CODE_LENGTH = 0x20;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x0;
+OSPI_DEVICE_0_START = 0x80020000;
+OSPI_DEVICE_0_LENGTH = 0x0;
+OSPI_DEVICE_1_START = 0x80030000;
+OSPI_DEVICE_1_LENGTH = 0x0;
+
+/* Uno R4 has bootloader */
+FLASH_IMAGE_START = 0x4000;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index f5097460a..a5325306d 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -59,9 +59,10 @@ INC += \
 
 ifndef LD_FILE
 LD_FILE = $(FAMILY_PATH)/linker/gcc/$(MCU_VARIANT).ld
-LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc
 endif
 
+LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc
+
 # For freeRTOS port source
 # hack to use the port provided by renesas
 FREERTOS_PORTABLE_SRC = $(FSP_RA)/src/rm_freertos_port
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index c5ed8ae55..7f49dc8a9 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -186,6 +186,7 @@ static inline void pipe_wait_for_ready(rusb2_reg_t* rusb, unsigned num)
 
 static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
 {
+  // NOTE: unlike DCD, Highspeed 32-bit FIFO does not need to adjust the fifo address
   volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo;
   uintptr_t addr = (uintptr_t)buf;
   while (len >= 2) {

From 0d9973ef87a55276d14c2aa45647f92a8358e9a2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 31 Jul 2023 16:21:19 +0700
Subject: [PATCH 1937/2085] enable_irq since uno bootloader can disable it.
 systick triggered, however usb still not work with uno

---
 hw/bsp/ra/family.c                     | 4 ++++
 src/portable/renesas/rusb2/dcd_rusb2.c | 1 +
 2 files changed, 5 insertions(+)

diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index b78fdedc7..096f0d0ff 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -92,6 +92,10 @@ const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENT
 //--------------------------------------------------------------------+
 
 void board_init(void) {
+  // Enable global interrupts in CPSR register since board with bootloader such as Arduino Uno R4
+  // can transfer CPU control with CPSR.I bit set to 0 (disable IRQ)
+  __enable_irq();
+
   /* Configure pins. */
   R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
 
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 9383923bd..37fd93497 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -740,6 +740,7 @@ void dcd_init(uint8_t rhport)
   rusb->BEMPENB = 1;
   rusb->BRDYENB = 1;
 
+  // If VBUS (detect) pin is not used, application need to call tud_connect() manually after tud_init()
   if (rusb->INTSTS0_b.VBSTS) {
     dcd_connect(rhport);
   }

From cb47231518d8a33bb9c5ab710c819049274d443b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 31 Jul 2023 17:13:21 +0700
Subject: [PATCH 1938/2085] revert out of scope changes

---
 src/host/usbh.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index c8eb91be3..15c48be47 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -258,7 +258,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
-TU_ATTR_WEAK void osal_task_delay(uint32_t msec)
+void osal_task_delay(uint32_t msec)
 {
   const uint32_t start = hcd_frame_number(_usbh_controller);
   while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}

From 3f788a4e5a7758ce51cbcadef4ac21e427cc3c56 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 31 Jul 2023 19:09:40 +0700
Subject: [PATCH 1939/2085] enable USBMC for uno r4, add
 board_init_after_tusb() API

add BOARD_UPPERCASE for board detection
---
 examples/device/audio_4_channel_mic/src/main.c    | 4 ++++
 examples/device/audio_test/src/main.c             | 4 ++++
 examples/device/audio_test_multi_rate/src/main.c  | 4 ++++
 examples/device/cdc_dual_ports/src/main.c         | 4 ++++
 examples/device/cdc_msc/src/main.c                | 4 ++++
 examples/device/cdc_msc_freertos/src/main.c       | 4 ++++
 examples/device/dfu/src/main.c                    | 4 ++++
 examples/device/dfu_runtime/src/main.c            | 4 ++++
 examples/device/dynamic_configuration/src/main.c  | 4 ++++
 examples/device/hid_boot_interface/src/main.c     | 4 ++++
 examples/device/hid_composite/src/main.c          | 4 ++++
 examples/device/hid_composite_freertos/src/main.c | 4 ++++
 examples/device/hid_generic_inout/src/main.c      | 4 ++++
 examples/device/hid_multiple_interface/src/main.c | 4 ++++
 examples/device/midi_test/src/main.c              | 4 ++++
 examples/device/msc_dual_lun/src/main.c           | 4 ++++
 examples/device/net_lwip_webserver/src/main.c     | 4 ++++
 examples/device/uac2_headset/src/main.c           | 4 ++++
 examples/device/usbtmc/src/main.c                 | 4 ++++
 examples/device/video_capture/src/main.c          | 4 ++++
 examples/device/webusb_serial/src/main.c          | 4 ++++
 examples/dual/host_hid_to_device_cdc/src/main.c   | 4 ++++
 examples/host/bare_api/src/main.c                 | 4 ++++
 examples/host/cdc_msc_hid/src/main.c              | 4 ++++
 examples/host/hid_controller/src/main.c           | 4 ++++
 examples/host/msc_file_explorer/src/main.c        | 5 +++++
 examples/make.mk                                  | 2 ++
 hw/bsp/board.h                                    | 3 +++
 hw/bsp/family_support.cmake                       | 5 +++++
 hw/bsp/ra/boards/uno_r4/board.mk                  | 2 +-
 hw/bsp/ra/family.c                                | 7 +++++++
 src/portable/renesas/rusb2/dcd_rusb2.c            | 2 --
 32 files changed, 123 insertions(+), 3 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 2b9c5143d..f5fc884bd 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -84,6 +84,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   // Init values
   sampFreq = AUDIO_SAMPLE_RATE;
   clkValid = 1;
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index b5ca41d36..6dc655416 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -85,6 +85,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   // Init values
   sampFreq = AUDIO_SAMPLE_RATE;
   clkValid = 1;
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
index 078e783eb..637be2d40 100644
--- a/examples/device/audio_test_multi_rate/src/main.c
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -99,6 +99,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   // Init values
   sampFreq = sampleRatesList[0];
   clkValid = 1;
diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 70eaea85d..7ceff73b3 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -42,6 +42,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index 6dad73cbf..87fc33181 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -58,6 +58,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 0e8a24d02..6cfef9ef5 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -136,6 +136,10 @@ void usb_device_task(void* param)
   // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   // RTOS forever loop
   while (1)
   {
diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 5f37f25e1..bcd5b4942 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -77,6 +77,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index 4ec3cb188..beef1037d 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -72,6 +72,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index 578f01d8c..6c7789138 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -59,6 +59,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 1a155996a..47f68f8fa 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -59,6 +59,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 8d0e6bece..d4c5f5b3e 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -60,6 +60,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index ca02af100..bdbe26b86 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -138,6 +138,10 @@ void usb_device_task(void* param)
   // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   // RTOS forever loop
   while (1)
   {
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 5db8f5581..5b3e53b06 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -83,6 +83,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c
index 72240b208..94f845a84 100644
--- a/examples/device/hid_multiple_interface/src/main.c
+++ b/examples/device/hid_multiple_interface/src/main.c
@@ -64,6 +64,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 2c3e9d954..c77207ca2 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -65,6 +65,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index c7f6de7bf..d8abb5151 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -57,6 +57,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 19a0eae9d..22543880e 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -232,6 +232,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   /* initialize lwip, dhcp-server, dns-server, and http */
   init_lwip();
   while (!netif_is_up(&netif_data));
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 19a3f7bae..c502eb10d 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -105,6 +105,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   TU_LOG1("Headset running\r\n");
 
   while (1)
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 2bba336f1..fa7de7570 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -57,6 +57,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 5654e0b61..b942dd30e 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -59,6 +59,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index eaca78c73..f63d0ccea 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -96,6 +96,10 @@ int main(void)
   // init device stack on configured roothub port
   tud_init(BOARD_TUD_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index 817c63c70..5a31b9dda 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -83,6 +83,10 @@ int main(void)
   tud_init(BOARD_TUD_RHPORT);
   tuh_init(BOARD_TUH_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index bb7fa850e..7286befe0 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -67,6 +67,10 @@ int main(void)
   // init host stack on configured roothub port
   tuh_init(BOARD_TUH_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     // tinyusb host task
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index 1f4acb822..51251be5c 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -48,6 +48,10 @@ int main(void)
   // init host stack on configured roothub port
   tuh_init(BOARD_TUH_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     // tinyusb host task
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index 4dcc92587..a4ab2f711 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -54,6 +54,10 @@ int main(void)
   // init host stack on configured roothub port
   tuh_init(BOARD_TUH_RHPORT);
 
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   while (1)
   {
     // tinyusb host task
diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index 7b1c2ef27..fc4b4e669 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -80,6 +80,11 @@ int main(void)
 
   // init host stack on configured roothub port
   tuh_init(BOARD_TUH_RHPORT);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
   msc_app_init();
 
   while (1)
diff --git a/examples/make.mk b/examples/make.mk
index 3c3a920cc..4001a5359 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -116,6 +116,8 @@ INC += \
   $(TOP)/$(FAMILY_PATH) \
   $(TOP)/src \
 
+BOARD_UPPER = $(shell echo $(BOARD) | tr a-z A-Z)
+CFLAGS += -DBOARD_$(BOARD_UPPER)
 
 # Log level is mapped to TUSB DEBUG option
 ifneq ($(LOG),)
diff --git a/hw/bsp/board.h b/hw/bsp/board.h
index 036556731..d782013bb 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board.h
@@ -54,6 +54,9 @@
 // Initialize on-board peripherals : led, button, uart and USB
 void board_init(void);
 
+// Init board after tinyusb is initialized
+void board_init_after_tusb(void) TU_ATTR_WEAK;
+
 // Turn LED on or off
 void board_led_write(bool state);
 
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index d8298c8ad..db1ce988e 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -181,6 +181,11 @@ endfunction()
 function(family_configure_common TARGET RTOS)
   family_add_rtos(${TARGET} ${RTOS})
 
+  string(TOUPPER ${BOARD} BOARD_UPPER)
+  target_compile_definitions(${TARGET} PUBLIC
+    BOARD_${BOARD_UPPER}
+  )
+
   # run size after build
   add_custom_command(TARGET ${TARGET} POST_BUILD
     COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${TARGET}>
diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk
index cbe6c782c..b7075eec0 100644
--- a/hw/bsp/ra/boards/uno_r4/board.mk
+++ b/hw/bsp/ra/boards/uno_r4/board.mk
@@ -1,7 +1,7 @@
 CPU_CORE = cortex-m4
 MCU_VARIANT = ra4m1
 
-LD_FILE = $(BOARD_PATH)/${BOARD}.ld
+LD_FILE = ${BOARD_PATH}/${BOARD}.ld
 
 # For flash-jlink target
 JLINK_DEVICE = R7FA4M1AB
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 096f0d0ff..e6213061d 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -124,6 +124,13 @@ void board_init(void) {
   board_led_write(false);
 }
 
+void board_init_after_tusb(void) {
+  // For board that use USB LDO regulator
+#if defined(BOARD_UNO_R4)
+  R_USB_FS0->USBMC |= R_USB_FS0_USBMC_VDCEN_Msk;
+#endif
+}
+
 void board_led_write(bool state) {
   R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
 }
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 37fd93497..9a3983f56 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -726,8 +726,6 @@ void dcd_init(uint8_t rhport)
 
     rusb->PHYSLEW = 0x5;
     rusb->DPUSR0R_FS_b.FIXPHY0 = 0u; /* USB_BASE Transceiver Output fixed */
-
-    // rusb2->USBMC = (uint16_t) (rusb2->USBMC | RUSB2_USBMC_VDCEN_Msk);
   }
 
   /* Setup default control pipe */

From 1cccbaf7ec12ecf296644e9b51603261a0d586ac Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 1 Aug 2023 11:18:00 +0700
Subject: [PATCH 1940/2085] fix board name with dash

---
 examples/make.mk            | 2 +-
 hw/bsp/family_support.cmake | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/examples/make.mk b/examples/make.mk
index 4001a5359..4773189df 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -116,7 +116,7 @@ INC += \
   $(TOP)/$(FAMILY_PATH) \
   $(TOP)/src \
 
-BOARD_UPPER = $(shell echo $(BOARD) | tr a-z A-Z)
+BOARD_UPPER = $(shell echo $(subst -,_,$(BOARD)) | tr a-z A-Z)
 CFLAGS += -DBOARD_$(BOARD_UPPER)
 
 # Log level is mapped to TUSB DEBUG option
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index db1ce988e..8cc7a1420 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -182,6 +182,7 @@ function(family_configure_common TARGET RTOS)
   family_add_rtos(${TARGET} ${RTOS})
 
   string(TOUPPER ${BOARD} BOARD_UPPER)
+  string(REPLACE "-" "_" BOARD_UPPER ${BOARD_UPPER})
   target_compile_definitions(${TARGET} PUBLIC
     BOARD_${BOARD_UPPER}
   )

From 789e478d4d47cca9bd1cf7983a49c13476c54b78 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 1 Aug 2023 13:16:37 +0700
Subject: [PATCH 1941/2085] add portenta c33 bsp, add flash by dfu-util

---
 examples/rules.mk                             |  15 +-
 hw/bsp/family_support.cmake                   |  12 +
 hw/bsp/ra/boards/portenta_c33/board.cmake     |  25 ++
 hw/bsp/ra/boards/portenta_c33/board.h         |  68 +++
 hw/bsp/ra/boards/portenta_c33/board.mk        |  12 +
 .../boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h |  63 +++
 .../fsp_cfg/bsp/bsp_mcu_device_cfg.h          |   5 +
 .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h       |  11 +
 .../fsp_cfg/bsp/bsp_mcu_family_cfg.h          | 387 ++++++++++++++++++
 .../portenta_c33/fsp_cfg/bsp_clock_cfg.h      |  37 ++
 hw/bsp/ra/boards/portenta_c33/portenta_c33.ld |  25 ++
 hw/bsp/ra/family.cmake                        |   5 +
 hw/bsp/ra/family.mk                           |   2 +
 tools/make/toolchain/arm_gcc_rules.mk         |   3 +-
 14 files changed, 665 insertions(+), 5 deletions(-)
 create mode 100644 hw/bsp/ra/boards/portenta_c33/board.cmake
 create mode 100644 hw/bsp/ra/boards/portenta_c33/board.h
 create mode 100644 hw/bsp/ra/boards/portenta_c33/board.mk
 create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h
 create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h
 create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
 create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h
 create mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h
 create mode 100644 hw/bsp/ra/boards/portenta_c33/portenta_c33.ld

diff --git a/examples/rules.mk b/examples/rules.mk
index 44698b019..44d6b84c8 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -88,7 +88,7 @@ linkermap: $(BUILD)/$(PROJECT).elf
 # Flash Targets
 # ---------------------------------------
 
-# Jlink binary
+# --------------- Jlink -----------------
 ifeq ($(OS),Windows_NT)
   JLINKEXE = JLink.exe
 else
@@ -110,10 +110,12 @@ $(BUILD)/$(BOARD).jlink: $(BUILD)/$(PROJECT).hex
 flash-jlink: $(BUILD)/$(BOARD).jlink
 	$(JLINKEXE) -device $(JLINK_DEVICE) -if $(JLINK_IF) -JTAGConf -1,-1 -speed auto -CommandFile $<
 
+# --------------- stm32 cube programmer -----------------
 # Flash STM32 MCU using stlink with STM32 Cube Programmer CLI
 flash-stlink: $(BUILD)/$(PROJECT).elf
 	STM32_Programmer_CLI --connect port=swd --write $< --go
 
+# --------------- xfel -----------------
 $(BUILD)/$(PROJECT)-sunxi.bin: $(BUILD)/$(PROJECT).bin
 	$(PYTHON) $(TOP)/tools/mksunxi.py $< $@
 
@@ -121,18 +123,23 @@ flash-xfel: $(BUILD)/$(PROJECT)-sunxi.bin
 	xfel spinor write 0 $<
 	xfel reset
 
-# Flash using pyocd
+# --------------- pyocd -----------------
 PYOCD_OPTION ?=
 flash-pyocd: $(BUILD)/$(PROJECT).hex
 	pyocd flash -t $(PYOCD_TARGET) $(PYOCD_OPTION) $<
 	#pyocd reset -t $(PYOCD_TARGET)
 
-# Flash using openocd
+# --------------- openocd -----------------
 OPENOCD_OPTION ?=
 flash-openocd: $(BUILD)/$(PROJECT).elf
 	openocd $(OPENOCD_OPTION) -c "program $< verify reset exit"
 
-# flash with Black Magic Probe
+# --------------- dfu-util -----------------
+DFU_UTIL_OPTION ?= -a 0
+flash-dfu-util: $(BUILD)/$(PROJECT).bin
+	dfu-util -R $(DFU_UTIL_OPTION) -D $<
+
+# --------------- Black Magic -----------------
 # This symlink is created by https://github.com/blacksphere/blackmagic/blob/master/driver/99-blackmagic.rules
 BMP ?= /dev/ttyBmpGdb
 
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 8cc7a1420..529bdb8f3 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -407,6 +407,18 @@ function(family_flash_nxplink TARGET)
 endfunction()
 
 
+function(family_flash_dfu_util TARGET OPTION)
+  if (NOT DEFINED DFU_UTIL)
+    set(DFU_UTIL dfu-util)
+  endif ()
+
+  add_custom_target(${TARGET}-dfu-util
+    DEPENDS ${TARGET}
+    COMMAND ${DFU_UTIL} -R -d ${DFU_UTIL_VID_PID} -a 0 -D $<TARGET_FILE_DIR:${TARGET}>/${TARGET}.bin
+    VERBATIM
+    )
+endfunction()
+
 #----------------------------------
 # Family specific
 #----------------------------------
diff --git a/hw/bsp/ra/boards/portenta_c33/board.cmake b/hw/bsp/ra/boards/portenta_c33/board.cmake
new file mode 100644
index 000000000..1837d8450
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/board.cmake
@@ -0,0 +1,25 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra6m5)
+
+set(JLINK_DEVICE R7FA6M5BH)
+set(DFU_UTIL_VID_PID 2341:0368)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+set(PORT 1)
+endif()
+
+# Host port will be the other port
+set(HOST_PORT $<NOT:${PORT}>)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    BOARD_TUD_RHPORT=${PORT}
+    BOARD_TUH_RHPORT=${HOST_PORT}
+    # port 0 is fullspeed, port 1 is highspeed
+    BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
+    BOARD_TUH_MAX_SPEED=$<IF:${HOST_PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
+    )
+endfunction()
diff --git a/hw/bsp/ra/boards/portenta_c33/board.h b/hw/bsp/ra/boards/portenta_c33/board.h
new file mode 100644
index 000000000..7841ec8b8
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/board.h
@@ -0,0 +1,68 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED1                  BSP_IO_PORT_01_PIN_07 // Red LED
+#define LED_STATE_ON          1
+
+#define SW1                   BSP_IO_PORT_04_PIN_08 // D12
+#define BUTTON_STATE_ACTIVE   0
+
+static const ioport_pin_cfg_t board_pin_cfg[] = {
+    { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
+    { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
+
+    // USB FS
+    { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH },
+    { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
+    { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
+
+    // USB HS
+    { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS },
+    { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
+    { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
+
+    // ETM Trace
+    #ifdef TRACE_ETM
+    { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+    { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+    { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+    { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+    { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
+     #endif
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/portenta_c33/board.mk b/hw/bsp/ra/boards/portenta_c33/board.mk
new file mode 100644
index 000000000..6a5c2ffce
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/board.mk
@@ -0,0 +1,12 @@
+CPU_CORE = cortex-m33
+MCU_VARIANT = ra6m5
+
+LD_FILE = ${BOARD_PATH}/${BOARD}.ld
+
+# Port 1 is highspeed
+PORT ?= 1
+
+JLINK_DEVICE = R7FA6M5BH
+DFU_UTIL_OPTION = -d 2341:0368 -a 0
+
+flash: flash-dfu-util
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 000000000..33d381850
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,63 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+
+#define RA_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (RA_NOT_DEFINED) != (2)
+#define BSP_CFG_RTOS (2)
+#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+  #define BSP_CFG_RTOS (1)
+#else
+  #define BSP_CFG_RTOS (0)
+#endif
+#endif
+#ifndef BSP_CFG_RTC_USED
+#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+#endif
+#undef RA_NOT_DEFINED
+#if defined(_RA_BOOT_IMAGE)
+  #define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+#define BSP_CFG_HEAP_BYTES (0x1000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT     ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+#endif
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 000000000..bd6a901c3
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (6)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 000000000..6845183db
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M5BH3CFC
+#define BSP_MCU_FEATURE_SET ('B')
+#define BSP_ROM_SIZE_BYTES (2097152)
+#define BSP_RAM_SIZE_BYTES (524288)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_LQFP
+#define BSP_PACKAGE_PINS (176)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 000000000..d5428540f
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,387 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+
+#define BSP_MCU_GROUP_RA6M5 (1)
+#define BSP_LOCO_HZ                 (32768)
+#define BSP_MOCO_HZ                 (8000000)
+#define BSP_SUB_CLOCK_HZ            (32768)
+#if   BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ                 (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+  #define BSP_HOCO_HZ                 (18000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+  #define BSP_HOCO_HZ                 (20000000)
+#else
+  #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+
+#define BSP_CFG_FLL_ENABLE                 (0)
+
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
+
+#if defined(_RA_TZ_SECURE)
+            #define BSP_TZ_SECURE_BUILD           (1)
+            #define BSP_TZ_NONSECURE_BUILD        (0)
+            #elif defined(_RA_TZ_NONSECURE)
+            #define BSP_TZ_SECURE_BUILD           (0)
+            #define BSP_TZ_NONSECURE_BUILD        (1)
+            #else
+#define BSP_TZ_SECURE_BUILD           (0)
+#define BSP_TZ_NONSECURE_BUILD        (0)
+#endif
+
+/* TrustZone Settings */
+#define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+#define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+#define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
+
+/* CMSIS TrustZone Settings */
+#define SCB_CSR_AIRCR_INIT                (1)
+#define SCB_AIRCR_BFHFNMINS_VAL           (0)
+#define SCB_AIRCR_SYSRESETREQS_VAL        (1)
+#define SCB_AIRCR_PRIS_VAL                (0)
+#define TZ_FPU_NS_USAGE                   (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+#define SCB_NSACR_CP10_11_VAL             (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+#define FPU_FPCCR_TS_VAL                  (1U)
+#endif
+#define FPU_FPCCR_CLRONRETS_VAL           (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+#define FPU_FPCCR_CLRONRET_VAL            (1)
+#endif
+
+/* The C-Cache line size that is configured during startup. */
+#ifndef BSP_CFG_C_CACHE_LINE_SIZE
+#define BSP_CFG_C_CACHE_LINE_SIZE   (1U)
+#endif
+
+/* Type 1 Peripheral Security Attribution */
+
+/* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+            (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
+            0x33f4f9) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
+            0x7fffcef4) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+            0xffae07f0) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+            0x3f3ff8) /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+            0xfffffffc) /* Unused */
+#endif
+
+/* Type 2 Peripheral Security Attribution */
+
+/* Security attribution for Cache registers. */
+#ifndef BSP_TZ_CFG_CSAR
+#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+#define BSP_TZ_CFG_LVDSAR (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \
+            0xFFFFFFFCU)
+#endif
+
+/* Security attribution for LPM registers. */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+#endif
+/* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
+#endif
+#endif
+
+/* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+#endif
+
+/* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
+            0xFFFF0000U)
+#endif
+
+/* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+/* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_ICUSARC
+#define BSP_TZ_CFG_ICUSARC (\
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+            (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
+            0xFFFFFF00U)
+#endif
+
+/* Security attribution registers for SELSR0. */
+#ifndef BSP_TZ_CFG_ICUSARD
+#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+#endif
+
+/* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+#define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+/* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
+#define BSP_TZ_CFG_FSAR (0xFEFEU)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_FSAR (0xFFFFU)
+#endif
+#endif
+
+/* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+#define BSP_TZ_CFG_SRAMSAR (\
+        1 | \
+        ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
+        4 | \
+        0xFFFFFFF8U)
+#endif
+
+/* Security attribution for Standby RAM registers. */
+#ifndef BSP_TZ_CFG_STBRAMSAR
+#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+#endif
+
+/* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+#endif
+
+/* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+#endif
+/* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+#endif
+
+/* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+/* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+#else
+#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+#endif
+#endif
+
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) |  (1 << 8))
+
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector)    (ELC_ ## vector)
+
+/* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+#endif
+
+/* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+/* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+/* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+#endif
+/* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+#endif
+/* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+/* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+/* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+#endif
+/* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+#endif
+/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+#endif
+/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h
new file mode 100644
index 000000000..0eb5e0516
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h
@@ -0,0 +1,37 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+
+#define BSP_CFG_CLOCKS_SECURE   (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ         (24000000)                         /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY  (2)                                /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE      (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV         (BSP_CLOCKS_PLL_DIV_3)             /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL         (BSP_CLOCKS_PLL_MUL(25U,0U))       /* PLL Mul x25.0 */
+#define BSP_CFG_PLL2_SOURCE     (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV        (BSP_CLOCKS_PLL_DIV_2)             /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL        (BSP_CLOCKS_PLL_MUL(20U,0U))       /* PLL2 Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE    (BSP_CLOCKS_SOURCE_CLOCK_PLL)      /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE   (BSP_CLOCKS_CLOCK_DISABLED)        /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE      (BSP_CLOCKS_SOURCE_CLOCK_PLL2)     /* UCLK Src: PLL2 */
+#define BSP_CFG_U60CK_SOURCE    (BSP_CLOCKS_SOURCE_CLOCK_PLL2)     /* U60CK Src: PLL2 */
+#define BSP_CFG_OCTA_SOURCE     (BSP_CLOCKS_CLOCK_DISABLED)        /* OCTASPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED)        /* CANFDCLK Disabled */
+#define BSP_CFG_CECCLK_SOURCE   (BSP_CLOCKS_CLOCK_DISABLED)        /* CECCLK Disabled */
+#define BSP_CFG_ICLK_DIV        (BSP_CLOCKS_SYS_CLOCK_DIV_1)       /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_2)       /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_4)       /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_4)       /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV       (BSP_CLOCKS_SYS_CLOCK_DIV_2)       /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV        (BSP_CLOCKS_SYS_CLOCK_DIV_2)       /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT     (2)                                /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV        (BSP_CLOCKS_SYS_CLOCK_DIV_4)       /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV      (BSP_CLOCKS_SYS_CLOCK_DIV_1)       /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV         (BSP_CLOCKS_USB_CLOCK_DIV_5)       /* UCLK Div /5 */
+#define BSP_CFG_U60CK_DIV       (BSP_CLOCKS_USB60_CLOCK_DIV_4)     /* U60CK Div /4 */
+#define BSP_CFG_OCTA_DIV        (BSP_CLOCKS_OCTA_CLOCK_DIV_1)      /* OCTASPICLK Div /1 */
+#define BSP_CFG_CANFDCLK_DIV    (BSP_CLOCKS_CANFD_CLOCK_DIV_1)     /* CANFDCLK Div /1 */
+#define BSP_CFG_CECCLK_DIV      (BSP_CLOCKS_CEC_CLOCK_DIV_1)       /* CECCLK Div /1 */
+
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld
new file mode 100644
index 000000000..ba15588e6
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld
@@ -0,0 +1,25 @@
+RAM_START = 0x20000000;
+RAM_LENGTH = 0x80000;
+FLASH_START = 0x00000000;
+FLASH_LENGTH = 0x200000;
+DATA_FLASH_START = 0x08000000;
+DATA_FLASH_LENGTH = 0x2000;
+OPTION_SETTING_START = 0x0100A100;
+OPTION_SETTING_LENGTH = 0x100;
+OPTION_SETTING_S_START = 0x0100A200;
+OPTION_SETTING_S_LENGTH = 0x100;
+ID_CODE_START = 0x00000000;
+ID_CODE_LENGTH = 0x0;
+SDRAM_START = 0x80010000;
+SDRAM_LENGTH = 0x0;
+QSPI_FLASH_START = 0x60000000;
+QSPI_FLASH_LENGTH = 0x4000000;
+OSPI_DEVICE_0_START = 0x68000000;
+OSPI_DEVICE_0_LENGTH = 0x8000000;
+OSPI_DEVICE_1_START = 0x70000000;
+OSPI_DEVICE_1_LENGTH = 0x10000000;
+
+/* Board has bootloader */
+FLASH_IMAGE_START = 0x10000;
+
+INCLUDE fsp.ld
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index 2c45b8d71..307e01da8 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -124,4 +124,9 @@ function(family_configure_example TARGET RTOS)
 
   # Flashing
   family_flash_jlink(${TARGET})
+
+  if (DEFINED DFU_UTIL_VID_PID)
+    family_add_bin_hex(${TARGET})
+    family_flash_dfu_util(${TARGET} ${DFU_UTIL_VID_PID})
+  endif ()
 endfunction()
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index a5325306d..cf8e5d9e9 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -3,6 +3,8 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
 FSP_RA = hw/mcu/renesas/fsp/ra/fsp
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+OBJCOPY_BIN_OPTION = --only-section .text --only-section .data --only-section .rodata --only-section .bss
+
 # Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk
 PORT ?= 0
 
diff --git a/tools/make/toolchain/arm_gcc_rules.mk b/tools/make/toolchain/arm_gcc_rules.mk
index f3482b9a8..b76d4aec3 100644
--- a/tools/make/toolchain/arm_gcc_rules.mk
+++ b/tools/make/toolchain/arm_gcc_rules.mk
@@ -65,9 +65,10 @@ $(BUILD)/obj/%_asm.o: %.S
 	@echo AS $(notdir $@)
 	@$(AS) $(ASFLAGS) -c -o $@ $<
 
+OBJCOPY_BIN_OPTION ?=
 $(BUILD)/$(PROJECT).bin: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@
-	@$(OBJCOPY) -O binary $^ $@
+	$(OBJCOPY) -O binary $(OBJCOPY_BIN_OPTION) $^ $@
 
 $(BUILD)/$(PROJECT).hex: $(BUILD)/$(PROJECT).elf
 	@echo CREATE $@

From 40833b585b2c4ea38dec034c18aacff35c6bcea6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 1 Aug 2023 15:33:15 +0700
Subject: [PATCH 1942/2085] enable flto for ra makefile

- remove ra from ci make build since it is already in cmake ci
---
 .github/workflows/build_arm.yml    |  1 -
 .idea/cmake.xml                    |  6 ++++--
 .idea/runConfigurations/uno_r4.xml | 10 ++++++++++
 hw/bsp/ra/family.mk                |  2 ++
 4 files changed, 16 insertions(+), 3 deletions(-)
 create mode 100644 .idea/runConfigurations/uno_r4.xml

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 72ddf164b..44a5e7363 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -39,7 +39,6 @@ jobs:
         - 'lpc51 lpc54'
         - 'mm32 msp432e4'
         - 'nrf'
-        - 'ra'
         - 'samd11 samd21'
         - 'samd51 same5x'
         - 'saml2x'
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 519623b71..4147bba59 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -44,8 +44,10 @@
       <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco" />
       <configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="ra6m5" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
+      <configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
+      <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/uno_r4.xml b/.idea/runConfigurations/uno_r4.xml
new file mode 100644
index 000000000..9982f4039
--- /dev/null
+++ b/.idea/runConfigurations/uno_r4.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="uno_r4" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 20000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index cf8e5d9e9..901808958 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -3,12 +3,14 @@ DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
 FSP_RA = hw/mcu/renesas/fsp/ra/fsp
 include $(TOP)/$(BOARD_PATH)/board.mk
 
+# Don't include options setting in .bin file since it create unnecessary large file due to padding
 OBJCOPY_BIN_OPTION = --only-section .text --only-section .data --only-section .rodata --only-section .bss
 
 # Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk
 PORT ?= 0
 
 CFLAGS += \
+  -flto \
   -DCFG_TUSB_MCU=OPT_MCU_RAXXX \
   -DBOARD_TUD_RHPORT=$(PORT) \
 	-Wno-error=undef \

From 965627e81c63a76bb80d8319cbd9adf931a00595 Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Tue, 1 Aug 2023 11:41:33 +0200
Subject: [PATCH 1943/2085] rusb2: move dynamic irq function to c file

---
 hw/bsp/ra/family.cmake                 |  5 +++--
 hw/bsp/ra/family.mk                    |  1 +
 src/portable/renesas/rusb2/dcd_rusb2.c |  5 -----
 src/portable/renesas/rusb2/rusb2_ra.c  | 16 ++++++++++++++++
 src/portable/renesas/rusb2/rusb2_ra.h  |  9 +--------
 5 files changed, 21 insertions(+), 15 deletions(-)
 create mode 100644 src/portable/renesas/rusb2/rusb2_ra.c

diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index 307e01da8..2d079dc94 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -114,8 +114,9 @@ function(family_configure_example TARGET RTOS)
     # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
-    ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
-    ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
+  ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
+  ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
+  ${TOP}/src/portable/renesas/rusb2/rusb2_ra.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index cf8e5d9e9..3394d41b4 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -32,6 +32,7 @@ endif
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
+	src/portable/renesas/rusb2/rusb2_ra.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
 	$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 9a3983f56..3ec1b70b5 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -50,11 +50,6 @@
     #define D0FIFOCTR_b CFIFOCTR_b
   #endif
 
-  // Application API for setting IRQ number
-  void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
-    rusb2_controller[rhport].irqnum = irqnum;
-  }
-
 #else
   #error "Unsupported MCU"
 #endif
diff --git a/src/portable/renesas/rusb2/rusb2_ra.c b/src/portable/renesas/rusb2/rusb2_ra.c
new file mode 100644
index 000000000..bbffd712e
--- /dev/null
+++ b/src/portable/renesas/rusb2/rusb2_ra.c
@@ -0,0 +1,16 @@
+#include "tusb_option.h"
+#include "device/dcd.h"
+#include "rusb2_type.h"
+#include "rusb2_ra.h"
+
+rusb2_controller_t rusb2_controller[] = {
+    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
+    #ifdef RUSB2_SUPPORT_HIGHSPEED
+    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
+    #endif
+};
+
+// Application API for setting IRQ number
+void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
+    rusb2_controller[rhport].irqnum = irqnum;
+}
\ No newline at end of file
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 7ff272bbc..4774d2e2c 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -74,14 +74,7 @@ typedef struct {
   #define rusb2_is_highspeed_reg(_reg)   (false)
 #endif
 
-// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
-static rusb2_controller_t rusb2_controller[] = {
-    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
-    #ifdef RUSB2_SUPPORT_HIGHSPEED
-    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
-    #endif
-};
-
+extern rusb2_controller_t rusb2_controller[];
 #define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
 
 //--------------------------------------------------------------------+

From 04f1a34c39e109002c89e464103ebed6128c2903 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 1 Aug 2023 17:03:07 +0700
Subject: [PATCH 1944/2085] add rusb2_common.c for dynami irq

---
 hw/bsp/ra/family.cmake                    |  1 +
 hw/bsp/ra/family.mk                       |  1 +
 src/portable/renesas/rusb2/dcd_rusb2.c    |  5 --
 src/portable/renesas/rusb2/hcd_rusb2.c    |  6 ---
 src/portable/renesas/rusb2/rusb2_common.c | 61 +++++++++++++++++++++++
 src/portable/renesas/rusb2/rusb2_ra.h     |  8 +--
 src/portable/renesas/rusb2/rusb2_type.h   |  1 +
 7 files changed, 65 insertions(+), 18 deletions(-)
 create mode 100644 src/portable/renesas/rusb2/rusb2_common.c

diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index 307e01da8..11bc7c668 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -116,6 +116,7 @@ function(family_configure_example TARGET RTOS)
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c
     ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c
+    ${TOP}/src/portable/renesas/rusb2/rusb2_common.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 901808958..9afb38e06 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -34,6 +34,7 @@ endif
 SRC_C += \
 	src/portable/renesas/rusb2/dcd_rusb2.c \
 	src/portable/renesas/rusb2/hcd_rusb2.c \
+	src/portable/renesas/rusb2/rusb2_common.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
 	$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
 	$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 9a3983f56..3ec1b70b5 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -50,11 +50,6 @@
     #define D0FIFOCTR_b CFIFOCTR_b
   #endif
 
-  // Application API for setting IRQ number
-  void tud_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
-    rusb2_controller[rhport].irqnum = irqnum;
-  }
-
 #else
   #error "Unsupported MCU"
 #endif
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 7f49dc8a9..621320095 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -34,14 +34,8 @@
 
 #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
   #include "rusb2_rx.h"
-
 #elif TU_CHECK_MCU(OPT_MCU_RAXXX)
   #include "rusb2_ra.h"
-
-//  void osal_task_delay(uint32_t msec) {
-//    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
-//  }
-
 #else
   #error "Unsupported MCU"
 #endif
diff --git a/src/portable/renesas/rusb2/rusb2_common.c b/src/portable/renesas/rusb2/rusb2_common.c
new file mode 100644
index 000000000..850060777
--- /dev/null
+++ b/src/portable/renesas/rusb2/rusb2_common.c
@@ -0,0 +1,61 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if defined(TUP_USBIP_RUSB2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED)
+
+#include "rusb2_type.h"
+
+#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
+#include "rusb2_rx.h"
+
+#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
+#include "rusb2_ra.h"
+
+// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
+rusb2_controller_t rusb2_controller[] = {
+    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
+    #ifdef RUSB2_SUPPORT_HIGHSPEED
+    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
+    #endif
+};
+
+// Application API for setting IRQ number. May throw warnings for missing prototypes.
+void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) {
+  rusb2_controller[rhport].irqnum = irqnum;
+}
+
+//  void osal_task_delay(uint32_t msec) {
+//    R_BSP_SoftwareDelay(msec, BSP_DELAY_UNITS_MILLISECONDS);
+//  }
+
+#else
+  #error "Unsupported MCU"
+#endif
+
+
+#endif
diff --git a/src/portable/renesas/rusb2/rusb2_ra.h b/src/portable/renesas/rusb2/rusb2_ra.h
index 7ff272bbc..259d3cbdb 100644
--- a/src/portable/renesas/rusb2/rusb2_ra.h
+++ b/src/portable/renesas/rusb2/rusb2_ra.h
@@ -74,13 +74,7 @@ typedef struct {
   #define rusb2_is_highspeed_reg(_reg)   (false)
 #endif
 
-// USBFS_INT_IRQn and USBHS_USB_INT_RESUME_IRQn are generated by FSP
-static rusb2_controller_t rusb2_controller[] = {
-    { .reg_base = R_USB_FS0_BASE, .irqnum = USBFS_INT_IRQn },
-    #ifdef RUSB2_SUPPORT_HIGHSPEED
-    { .reg_base = R_USB_HS0_BASE, .irqnum = USBHS_USB_INT_RESUME_IRQn },
-    #endif
-};
+extern rusb2_controller_t rusb2_controller[];
 
 #define RUSB2_REG(_p)      ((rusb2_reg_t*) rusb2_controller[_p].reg_base)
 
diff --git a/src/portable/renesas/rusb2/rusb2_type.h b/src/portable/renesas/rusb2/rusb2_type.h
index 005d7f2be..dd88f66a7 100644
--- a/src/portable/renesas/rusb2/rusb2_type.h
+++ b/src/portable/renesas/rusb2/rusb2_type.h
@@ -28,6 +28,7 @@
 #define _TUSB_RUSB2_TYPE_H_
 
 #include <stdint.h>
+#include <stddef.h>
 
 #ifdef __cplusplus
 extern "C" {

From 47ae883ba0f02ef268e7e8427f14aaa4fb0c29ce Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 1 Aug 2023 17:26:56 +0700
Subject: [PATCH 1945/2085] fix build with -flto

---
 hw/bsp/ra/family.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index e6213061d..73c64913d 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -136,7 +136,7 @@ void board_led_write(bool state) {
 }
 
 uint32_t board_button_read(void) {
-  bsp_io_level_t lvl;
+  bsp_io_level_t lvl = !BUTTON_STATE_ACTIVE;
   R_IOPORT_PinRead(&port_ctrl, SW1, &lvl);
   return lvl == BUTTON_STATE_ACTIVE;
 }

From edee46e7941f56f5024bf60d56921cfe10d1f7a5 Mon Sep 17 00:00:00 2001
From: Martino Facchin <m.facchin@arduino.cc>
Date: Tue, 1 Aug 2023 15:21:31 +0200
Subject: [PATCH 1946/2085] renesas: host: remove attach_attempt logic

---
 src/portable/renesas/rusb2/hcd_rusb2.c | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 621320095..f6683529a 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -774,7 +774,6 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 void hcd_int_handler(uint8_t rhport)
 {
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
-  static unsigned char attach_attempt = 0; // TODO remove later
   unsigned is0 = rusb->INTSTS0;
   unsigned is1 = rusb->INTSTS1;
 
@@ -789,23 +788,14 @@ void hcd_int_handler(uint8_t rhport)
   if (is1 & RUSB2_INTSTS1_SACK_Msk) {
     /* Set DATA1 in advance for the next transfer. */
     rusb->DCPCTR_b.SQSET = 1;
-    attach_attempt = 0;
     hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
   }
 
   if (is1 & RUSB2_INTSTS1_SIGN_Msk) {
     hcd_event_xfer_complete(rusb->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
-    if(attach_attempt > 0) {
-      rusb->DVSTCTR0_b.UACT = 1;
-      _hcd.need_reset = true;
-      rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;
-      hcd_event_device_attach(rhport, true);
-    }
-    attach_attempt--;
   }
 
   if (is1 & RUSB2_INTSTS1_ATTCH_Msk) {
-    attach_attempt = 10;
     rusb->DVSTCTR0_b.UACT = 1;
     _hcd.need_reset = true;
     rusb->INTENB1 = (rusb->INTENB1 & ~RUSB2_INTSTS1_ATTCH_Msk) | RUSB2_INTSTS1_DTCH_Msk;

From 07822979aa31f86fd9d350652be1d450acd03963 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 1 Aug 2023 18:41:15 +0200
Subject: [PATCH 1947/2085] Fix STM32G0 build.

---
 hw/bsp/stm32g0/family.cmake | 2 ++
 hw/bsp/stm32g0/family.mk    | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake
index b787363ed..cf52a6324 100644
--- a/hw/bsp/stm32g0/family.cmake
+++ b/hw/bsp/stm32g0/family.cmake
@@ -36,12 +36,14 @@ function(add_board_target BOARD_TARGET)
       ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
       ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
       )
     target_include_directories(${BOARD_TARGET} PUBLIC
diff --git a/hw/bsp/stm32g0/family.mk b/hw/bsp/stm32g0/family.mk
index 412c73291..6b199f21a 100644
--- a/hw/bsp/stm32g0/family.mk
+++ b/hw/bsp/stm32g0/family.mk
@@ -30,12 +30,14 @@ SRC_C += \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \

From 979bf32266d379ec493ad31001b815d6a597b91e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Aug 2023 15:34:18 +0700
Subject: [PATCH 1948/2085] default class driver log level to
 CFG_TUH/TUD_LOG_LEVEL allow application to selectively disable usbd/usbh or
 driver log

---
 src/class/cdc/cdc_device.c     | 15 +++++++++++----
 src/class/cdc/cdc_host.c       |  9 ++++++---
 src/class/dfu/dfu_device.c     | 11 +++++++++--
 src/class/dfu/dfu_rt_device.c  | 13 ++++++++++---
 src/class/hid/hid_host.c       |  8 +++++---
 src/class/msc/msc_device.c     |  2 +-
 src/class/msc/msc_host.c       | 19 +++++++++++--------
 src/class/net/ncm_device.c     | 11 +++++++++--
 src/class/video/video_device.c | 23 +++++++++++++++--------
 src/host/usbh.c                |  7 -------
 src/host/usbh_classdriver.h    |  7 +++++++
 11 files changed, 84 insertions(+), 41 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index f658df4d0..70d9c2e24 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -33,6 +33,13 @@
 
 #include "cdc_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_CDC_LOG_LEVEL
+  #define CFG_TUD_CDC_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_CDC_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -353,7 +360,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     case CDC_REQUEST_SET_LINE_CODING:
       if (stage == CONTROL_STAGE_SETUP)
       {
-        TU_LOG2("  Set Line Coding\r\n");
+        TU_LOG_DRV("  Set Line Coding\r\n");
         tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
       }
       else if ( stage == CONTROL_STAGE_ACK)
@@ -365,7 +372,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
     case CDC_REQUEST_GET_LINE_CODING:
       if (stage == CONTROL_STAGE_SETUP)
       {
-        TU_LOG2("  Get Line Coding\r\n");
+        TU_LOG_DRV("  Get Line Coding\r\n");
         tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
       }
     break;
@@ -390,7 +397,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
         // Disable fifo overwriting if DTR bit is set
         tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
 
-        TU_LOG2("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
+        TU_LOG_DRV("  Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
 
         // Invoke callback
         if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
@@ -403,7 +410,7 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t
       }
       else if (stage == CONTROL_STAGE_ACK)
       {
-        TU_LOG2("  Send Break\r\n");
+        TU_LOG_DRV("  Send Break\r\n");
         if ( tud_cdc_send_break_cb ) tud_cdc_send_break_cb(itf, request->wValue);
       }
     break;
diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index ce9f27c33..7f9ed18b3 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -33,9 +33,12 @@
 
 #include "cdc_host.h"
 
-// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
-#define CDCH_DEBUG   2
-#define TU_LOG_DRV(...)   TU_LOG(CDCH_DEBUG, __VA_ARGS__)
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUH_CDC_LOG_LEVEL
+  #define CFG_TUH_CDC_LOG_LEVEL   CFG_TUH_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
 // Host CDC Interface
diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c
index bffdb8376..3e7c13dea 100644
--- a/src/class/dfu/dfu_device.c
+++ b/src/class/dfu/dfu_device.c
@@ -37,6 +37,13 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_DFU_LOG_LEVEL
+  #define CFG_TUD_DFU_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_DFU_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
@@ -205,7 +212,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
 {
   TU_VERIFY(request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE);
 
-  TU_LOG2("  DFU State  : %s, Status: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state), tu_lookup_find(&_dfu_status_table, _dfu_ctx.status));
+  TU_LOG_DRV("  DFU State  : %s, Status: %s\r\n", tu_lookup_find(&_dfu_state_table, _dfu_ctx.state), tu_lookup_find(&_dfu_status_table, _dfu_ctx.status));
 
   if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD )
   {
@@ -235,7 +242,7 @@ bool dfu_moded_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_reque
   }
   else if ( request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS )
   {
-    TU_LOG2("  DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest));
+    TU_LOG_DRV("  DFU Request: %s\r\n", tu_lookup_find(&_dfu_request_table, request->bRequest));
 
     // Class request
     switch ( request->bRequest )
diff --git a/src/class/dfu/dfu_rt_device.c b/src/class/dfu/dfu_rt_device.c
index 7b77b3f8f..a940d8d62 100644
--- a/src/class/dfu/dfu_rt_device.c
+++ b/src/class/dfu/dfu_rt_device.c
@@ -37,6 +37,13 @@
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_DFU_RUNTIME_LOG_LEVEL
+  #define CFG_TUD_DFU_RUNTIME_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_DFU_RUNTIME_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
@@ -99,7 +106,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
   {
     case DFU_REQUEST_DETACH:
     {
-      TU_LOG2("  DFU RT Request: DETACH\r\n");
+      TU_LOG_DRV("  DFU RT Request: DETACH\r\n");
       tud_control_status(rhport, request);
       tud_dfu_runtime_reboot_to_dfu_cb();
     }
@@ -107,7 +114,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
 
     case DFU_REQUEST_GETSTATUS:
     {
-      TU_LOG2("  DFU RT Request: GETSTATUS\r\n");
+      TU_LOG_DRV("  DFU RT Request: GETSTATUS\r\n");
       dfu_status_response_t resp;
       // Status = OK, Poll timeout is ignored during RT, State = APP_IDLE, IString = 0
       TU_VERIFY(tu_memset_s(&resp, sizeof(resp), 0x00, sizeof(resp))==0);
@@ -117,7 +124,7 @@ bool dfu_rtd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
 
     default:
     {
-      TU_LOG2("  DFU RT Unexpected Request: %d\r\n", request->bRequest);
+      TU_LOG_DRV("  DFU RT Unexpected Request: %d\r\n", request->bRequest);
       return false; // stall unsupported request
     }
   }
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 6abe298e5..4253170d4 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -33,10 +33,12 @@
 
 #include "hid_host.h"
 
-// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
-#define HIDH_DEBUG   2
-#define TU_LOG_DRV(...)   TU_LOG(HIDH_DEBUG, __VA_ARGS__)
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUH_HID_LOG_LEVEL
+  #define CFG_TUH_HID_LOG_LEVEL   CFG_TUH_LOG_LEVEL
+#endif
 
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUH_HID_LOG_LEVEL, __VA_ARGS__)
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c
index a602e9672..2589dcd2c 100644
--- a/src/class/msc/msc_device.c
+++ b/src/class/msc/msc_device.c
@@ -36,7 +36,7 @@
 
 // Level where CFG_TUSB_DEBUG must be at least for this driver is logged
 #ifndef CFG_TUD_MSC_LOG_LEVEL
-  #define CFG_TUD_MSC_LOG_LEVEL   2
+  #define CFG_TUD_MSC_LOG_LEVEL   CFG_TUD_LOG_LEVEL
 #endif
 
 #define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_MSC_LOG_LEVEL, __VA_ARGS__)
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index d32c0adb0..a65208d69 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -33,9 +33,12 @@
 
 #include "msc_host.h"
 
-// Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
-#define MSCH_DEBUG   2
-#define TU_LOG_MSCH(...)   TU_LOG(MSCH_DEBUG, __VA_ARGS__)
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUH_MSC_LOG_LEVEL
+  #define CFG_TUH_MSC_LOG_LEVEL   CFG_TUH_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUH_MSC_LOG_LEVEL, __VA_ARGS__)
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
@@ -308,7 +311,7 @@ void msch_close(uint8_t dev_addr)
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->configured, );
 
-  TU_LOG_MSCH("  MSCh close addr = %d\r\n", dev_addr);
+  TU_LOG_DRV("  MSCh close addr = %d\r\n", dev_addr);
 
   // invoke Application Callback
   if (p_msc->mounted) {
@@ -426,7 +429,7 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
   p_msc->configured = true;
 
   //------------- Get Max Lun -------------//
-  TU_LOG_MSCH("MSC Get Max Lun\r\n");
+  TU_LOG_DRV("MSC Get Max Lun\r\n");
   tusb_control_request_t const request =
   {
     .bmRequestType_bit =
@@ -465,7 +468,7 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer)
   p_msc->max_lun++; // MAX LUN is minus 1 by specs
 
   // TODO multiple LUN support
-  TU_LOG_MSCH("SCSI Test Unit Ready\r\n");
+  TU_LOG_DRV("SCSI Test Unit Ready\r\n");
   uint8_t const lun = 0;
   tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0);
 }
@@ -478,14 +481,14 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_d
   if (csw->status == 0)
   {
     // Unit is ready, read its capacity
-    TU_LOG_MSCH("SCSI Read Capacity\r\n");
+    TU_LOG_DRV("SCSI Read Capacity\r\n");
     tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0);
   }else
   {
     // Note: During enumeration, some device fails Test Unit Ready and require a few retries
     // with Request Sense to start working !!
     // TODO limit number of retries
-    TU_LOG_MSCH("SCSI Request Sense\r\n");
+    TU_LOG_DRV("SCSI Request Sense\r\n");
     TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete, 0));
   }
 
diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c
index 611dc3348..226c42c4e 100644
--- a/src/class/net/ncm_device.c
+++ b/src/class/net/ncm_device.c
@@ -34,6 +34,13 @@
 #include "device/usbd_pvt.h"
 #include "net_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_NCM_LOG_LEVEL
+  #define CFG_TUD_NCM_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_NCM_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -473,13 +480,13 @@ bool tud_network_can_xmit(uint16_t size)
   TU_VERIFY(ncm_interface.itf_data_alt == 1);
 
   if (ncm_interface.datagram_count >= ncm_interface.max_datagrams_per_ntb) {
-    TU_LOG2("NTB full [by count]\r\n");
+    TU_LOG_DRV("NTB full [by count]\r\n");
     return false;
   }
 
   size_t next_datagram_offset = ncm_interface.next_datagram_offset;
   if (next_datagram_offset + size > ncm_interface.ntb_in_size) {
-    TU_LOG2("ntb full [by size]\r\n");
+    TU_LOG_DRV("ntb full [by size]\r\n");
     return false;
   }
 
diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c
index e6fadf41b..abc43ccff 100644
--- a/src/class/video/video_device.c
+++ b/src/class/video/video_device.c
@@ -34,6 +34,13 @@
 
 #include "video_device.h"
 
+// Level where CFG_TUSB_DEBUG must be at least for this driver is logged
+#ifndef CFG_TUD_VIDEO_LOG_LEVEL
+  #define CFG_TUD_VIDEO_LOG_LEVEL   CFG_TUD_LOG_LEVEL
+#endif
+
+#define TU_LOG_DRV(...)   TU_LOG(CFG_TUD_VIDEO_LOG_LEVEL, __VA_ARGS__)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
@@ -609,17 +616,17 @@ static bool _close_vc_itf(uint8_t rhport, videod_interface_t *self)
  * @param[in]     altnum   The target alternate setting number. */
 static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t altnum)
 {
-  TU_LOG2("    open VC %d\n", altnum);
+  TU_LOG_DRV("    open VC %d\n", altnum);
   uint8_t const *beg = self->beg;
   uint8_t const *end = beg + self->len;
 
   /* The first descriptor is a video control interface descriptor. */
   uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum);
-  TU_LOG2("    cur %d\n", cur - beg);
+  TU_LOG_DRV("    cur %d\n", cur - beg);
   TU_VERIFY(cur < end);
 
   tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur;
-  TU_LOG2("    bInCollection %d\n", vc->ctl.bInCollection);
+  TU_LOG_DRV("    bInCollection %d\n", vc->ctl.bInCollection);
   /* Support for up to 2 streaming interfaces only. */
   TU_ASSERT(vc->ctl.bInCollection <= CFG_TUD_VIDEO_STREAMING);
 
@@ -628,7 +635,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t
 
   /* Advance to the next descriptor after the class-specific VC interface header descriptor. */
   cur += vc->std.bLength + vc->ctl.bLength;
-  TU_LOG2("    bNumEndpoints %d\n", vc->std.bNumEndpoints);
+  TU_LOG_DRV("    bNumEndpoints %d\n", vc->std.bNumEndpoints);
   /* Open the notification endpoint if it exist. */
   if (vc->std.bNumEndpoints) {
     /* Support for 1 endpoint only. */
@@ -662,7 +669,7 @@ static bool _init_vs_configuration(videod_streaming_interface_t *stm)
 static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint_fast8_t altnum)
 {
   uint_fast8_t i;
-  TU_LOG2("    reopen VS %d\n", altnum);
+  TU_LOG_DRV("    reopen VS %d\n", altnum);
   uint8_t const *desc = _videod_itf[stm->index_vc].beg;
 
   /* Close endpoints of previous settings. */
@@ -672,7 +679,7 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     uint8_t  ep_adr = _desc_ep_addr(desc + ofs_ep);
     usbd_edpt_close(rhport, ep_adr);
     stm->desc.ep[i] = 0;
-    TU_LOG2("    close EP%02x\n", ep_adr);
+    TU_LOG_DRV("    close EP%02x\n", ep_adr);
   }
 
   /* clear transfer management information */
@@ -709,12 +716,12 @@ static bool _open_vs_itf(uint8_t rhport, videod_streaming_interface_t *stm, uint
     }
     TU_ASSERT(usbd_edpt_open(rhport, ep));
     stm->desc.ep[i] = (uint16_t) (cur - desc);
-    TU_LOG2("    open EP%02x\n", _desc_ep_addr(cur));
+    TU_LOG_DRV("    open EP%02x\n", _desc_ep_addr(cur));
   }
   if (altnum) {
     stm->state = VS_STATE_STREAMING;
   }
-  TU_LOG2("    done\n");
+  TU_LOG_DRV("    done\n");
   return true;
 }
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index c8eb91be3..49f8c78f1 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -45,13 +45,6 @@
   #define CFG_TUH_INTERFACE_MAX   8
 #endif
 
-// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
-#ifndef CFG_TUH_LOG_LEVEL
-  #define CFG_TUH_LOG_LEVEL   2
-#endif
-
-#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
-
 //--------------------------------------------------------------------+
 // USBH-HCD common data structure
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index be9811641..308b4418a 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -35,6 +35,13 @@
  extern "C" {
 #endif
 
+// Level where CFG_TUSB_DEBUG must be at least for USBH is logged
+#ifndef CFG_TUH_LOG_LEVEL
+  #define CFG_TUH_LOG_LEVEL   2
+#endif
+
+#define TU_LOG_USBH(...)   TU_LOG(CFG_TUH_LOG_LEVEL, __VA_ARGS__)
+
 enum {
   USBH_EPSIZE_BULK_MAX = (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS)
 };

From 868d52f3a87d4404b0e93e49781d4190589599b9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Aug 2023 15:52:06 +0700
Subject: [PATCH 1949/2085] move codespell folder to tools

---
 .codespellrc                                     | 4 ++--
 {.codespell => tools/codespell}/exclude-file.txt | 0
 {.codespell => tools/codespell}/ignore-words.txt | 0
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename {.codespell => tools/codespell}/exclude-file.txt (100%)
 rename {.codespell => tools/codespell}/ignore-words.txt (100%)

diff --git a/.codespellrc b/.codespellrc
index dc089903c..1f06e0c5c 100644
--- a/.codespellrc
+++ b/.codespellrc
@@ -2,8 +2,8 @@
 [codespell]
 # In the event of a false positive, add the problematic word, in all lowercase, to 'ignore-words.txt' (one word per line).
 # Or copy & paste the whole problematic line to 'exclude-file.txt'
-ignore-words = .codespell/ignore-words.txt
-exclude-file = .codespell/exclude-file.txt
+ignore-words = tools/codespell/ignore-words.txt
+exclude-file = tools/codespell/exclude-file.txt
 check-filenames =
 check-hidden =
 count =
diff --git a/.codespell/exclude-file.txt b/tools/codespell/exclude-file.txt
similarity index 100%
rename from .codespell/exclude-file.txt
rename to tools/codespell/exclude-file.txt
diff --git a/.codespell/ignore-words.txt b/tools/codespell/ignore-words.txt
similarity index 100%
rename from .codespell/ignore-words.txt
rename to tools/codespell/ignore-words.txt

From 2021c6299789a3dd9bd239941d9316494205fe2f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 2 Aug 2023 17:57:28 +0700
Subject: [PATCH 1950/2085] fix pre-commit, also skip lto for rp2040

---
 examples/host/bare_api/CMakeLists.txt | 2 +-
 hw/bsp/family_support.cmake           | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 7049fe66b..05398b079 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -24,4 +24,4 @@ target_include_directories(${PROJECT} PUBLIC
 
 # Configure compilation flags and libraries for the example without RTOS.
 # See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
-family_configure_host_example(${PROJECT} noos)
\ No newline at end of file
+family_configure_host_example(${PROJECT} noos)
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 9959784ae..7c230957c 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -36,8 +36,8 @@ if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake)
   message(FATAL_ERROR "Family '${FAMILY}' is not known/supported")
 endif()
 
-if (NOT TINYUSB_OPT_SKIP_CHECK_IPO_SUPPORTED)
-  # enable LTO if supported
+if (NOT FAMILY STREQUAL rp2040)
+  # enable LTO if supported skip rp2040
   include(CheckIPOSupported)
   check_ipo_supported(RESULT IPO_SUPPORTED)
   if (IPO_SUPPORTED)

From 9560d0813f0872a1b8dfb337922b0ab5cc4cb811 Mon Sep 17 00:00:00 2001
From: Rocky04 <rockerfaeller04@gmx.de>
Date: Wed, 2 Aug 2023 15:25:08 +0200
Subject: [PATCH 1951/2085] Set unmounted on configuration reset

---
 src/device/usbd.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 9429cf664..b4ca63c9c 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -965,7 +965,14 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
   }
 
   // invoke callback
-  if (tud_mount_cb) tud_mount_cb();
+  if (cfg_num)
+  {
+    if (tud_mount_cb) tud_mount_cb();
+  }
+  else
+  {
+    if (tud_umount_cb) tud_umount_cb();
+  }
 
   return true;
 }

From d09604d6364f4840669eda66a75f5df0926bb3e0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 11:07:23 +0700
Subject: [PATCH 1952/2085] Revert "Name queues for easier FreeRTOS debugging
 with task- and queue-aware debuggers"

This reverts commit 11fba59319d81fb9502fbf399abb4fe27cf3fa29.
---
 src/device/usbd.c        | 4 ++--
 src/host/usbh.c          | 4 ++--
 src/osal/osal_freertos.h | 5 ++---
 3 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index b6c679b22..44c2530ce 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -279,7 +279,7 @@ tu_static uint8_t _usbd_rhport = RHPORT_INVALID;
 
 // Event queue
 // usbd_int_set() is used as mutex in OS NONE config
-OSAL_QUEUE_DEF(usbd_int_set, usbd_events, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
+OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
 tu_static osal_queue_t _usbd_q;
 
 // Mutex for claiming endpoint
@@ -410,7 +410,7 @@ bool tud_init (uint8_t rhport)
 #endif
 
   // Init device queue & task
-  _usbd_q = osal_queue_create(&usbd_events);
+  _usbd_q = osal_queue_create(&_usbd_qdef);
   TU_ASSERT(_usbd_q);
 
   // Get application driver if available
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 987ff7a6e..f3e9d3858 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -219,7 +219,7 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES];
 
 // Event queue
 // usbh_int_set is used as mutex in OS NONE config
-OSAL_QUEUE_DEF(usbh_int_set, usbh_events, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
+OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
 static osal_queue_t _usbh_q;
 
 CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN
@@ -330,7 +330,7 @@ bool tuh_init(uint8_t controller_id)
   TU_LOG_INT(USBH_DEBUG, sizeof(tu_edpt_stream_t));
 
   // Event queue
-  _usbh_q = osal_queue_create( &usbh_events );
+  _usbh_q = osal_queue_create( &_usbh_qdef );
   TU_ASSERT(_usbh_q != NULL);
 
 #if OSAL_MUTEX_REQUIRED
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index e83277eb3..0b1b11589 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -56,7 +56,7 @@ typedef SemaphoreHandle_t osal_mutex_t;
 // _int_set is not used with an RTOS
 #define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
   static _type _name##_##buf[_depth];\
-  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .pQueueName = #_name };
+  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
 
 typedef struct
 {
@@ -66,7 +66,6 @@ typedef struct
 #if configSUPPORT_STATIC_ALLOCATION
   StaticQueue_t sq;
 #endif
-  const char* pQueueName;
 }osal_queue_def_t;
 
 typedef QueueHandle_t osal_queue_t;
@@ -177,7 +176,7 @@ TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_de
     q = xQueueCreate(qdef->depth, qdef->item_sz);
   #endif
   #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
-    vQueueAddToRegistry(q, qdef->pQueueName);
+    vQueueAddToRegistry(q, "tinyUSB");
   #endif
   return q;
 }

From 473f37df958f74153f15c050c20d63f8defe89ed Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 12:05:21 +0700
Subject: [PATCH 1953/2085] add osal queue name if needed

also mass change configQUEUE_REGISTRY_SIZE = 4
---
 .../src/FreeRTOSConfig/FreeRTOSConfig.h       |   2 +-
 .../src/FreeRTOSConfig/FreeRTOSConfig.h       |   2 +-
 hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h  |   2 +-
 .../FreeRTOSConfig/FreeRTOSConfig.h           |   2 +-
 hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h  |   2 +-
 hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h  |   2 +-
 hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h  |   2 +-
 hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h    |   2 +-
 hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h    |   2 +-
 hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h     |   2 +-
 .../stm32f0/FreeRTOSConfig/FreeRTOSConfig.h   |   2 +-
 .../stm32f1/FreeRTOSConfig/FreeRTOSConfig.h   |   2 +-
 .../stm32f7/FreeRTOSConfig/FreeRTOSConfig.h   |   2 +-
 .../stm32g0/FreeRTOSConfig/FreeRTOSConfig.h   |   2 +-
 .../stm32g4/FreeRTOSConfig/FreeRTOSConfig.h   |   2 +-
 .../stm32h7/FreeRTOSConfig/FreeRTOSConfig.h   |   2 +-
 .../stm32l4/FreeRTOSConfig/FreeRTOSConfig.h   |   2 +-
 src/osal/osal_freertos.h                      | 108 +++++++++---------
 18 files changed, 68 insertions(+), 74 deletions(-)

diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 9bef9bbbf..69d638288 100644
--- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -81,7 +81,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
index 9bef9bbbf..69d638288 100644
--- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -81,7 +81,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
index f95927069..b65d8f1f9 100644
--- a/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
index a46af1759..2a2bce261 100644
--- a/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/kinetis_kl/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
index 1b3c64e0b..ea568dfc9 100644
--- a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               3
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h
index 96611ca1c..a48b54576 100644
--- a/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc40/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
index b1cef793e..fc0ab1f2d 100644
--- a/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc55/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
index b1cef793e..fc0ab1f2d 100644
--- a/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/mcx/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
index a56f243ea..efd26a3a7 100644
--- a/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/nrf/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
index 8c39a2fb8..4ef5dd883 100644
--- a/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/ra/FreeRTOSConfig/FreeRTOSConfig.h
@@ -81,7 +81,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
index fc2f9fc67..33440d288 100644
--- a/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32f0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
index 5a6b2300b..580fe02bb 100644
--- a/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32f1/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
index 815e567dd..4615640ed 100644
--- a/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32f7/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
index c8736f6d1..02bfaf97a 100644
--- a/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32g0/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
index 95fcbb08a..17c2a0c5c 100644
--- a/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32g4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
index 6881385a8..6a1f6c043 100644
--- a/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32h7/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h
index e6a735ddd..c12b0dc85 100644
--- a/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32l4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h
index 0b1b11589..501e0bddd 100644
--- a/src/osal/osal_freertos.h
+++ b/src/osal/osal_freertos.h
@@ -52,53 +52,60 @@ extern "C" {
 
 typedef SemaphoreHandle_t osal_semaphore_t;
 typedef SemaphoreHandle_t osal_mutex_t;
-
-// _int_set is not used with an RTOS
-#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
-  static _type _name##_##buf[_depth];\
-  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
+typedef QueueHandle_t osal_queue_t;
 
 typedef struct
 {
   uint16_t depth;
   uint16_t item_sz;
   void*    buf;
+
+#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+  char const* name;
+#endif
+
 #if configSUPPORT_STATIC_ALLOCATION
   StaticQueue_t sq;
 #endif
-}osal_queue_def_t;
+} osal_queue_def_t;
 
-typedef QueueHandle_t osal_queue_t;
+#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+  #define _OSAL_Q_NAME(_name) .name = #_name
+#else
+  #define _OSAL_Q_NAME(_name)
+#endif
+
+// _int_set is not used with an RTOS
+#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) \
+  static _type _name##_##buf[_depth];\
+  osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, _OSAL_Q_NAME(_name) };
 
 //--------------------------------------------------------------------+
 // TASK API
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec)
-{
-  if (msec == OSAL_TIMEOUT_WAIT_FOREVER) return portMAX_DELAY;
-  if (msec == 0) return 0;
+TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) {
+  if ( msec == OSAL_TIMEOUT_WAIT_FOREVER ) return portMAX_DELAY;
+  if ( msec == 0 ) return 0;
 
   uint32_t ticks = pdMS_TO_TICKS(msec);
 
   // configTICK_RATE_HZ is less than 1000 and 1 tick > 1 ms
   // we still need to delay at least 1 tick
-  if (ticks == 0) ticks =1 ;
+  if ( ticks == 0 ) ticks = 1;
 
   return ticks;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec)
-{
-  vTaskDelay( pdMS_TO_TICKS(msec) );
+TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) {
+  vTaskDelay(pdMS_TO_TICKS(msec));
 }
 
 //--------------------------------------------------------------------+
 // Semaphore API
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) {
 #if configSUPPORT_STATIC_ALLOCATION
   return xSemaphoreCreateBinaryStatic(semdef);
 #else
@@ -107,14 +114,10 @@ TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
-{
-  if ( !in_isr )
-  {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
+  if ( !in_isr ) {
     return xSemaphoreGive(sem_hdl) != 0;
-  }
-  else
-  {
+  } else {
     BaseType_t xHigherPriorityTaskWoken = pdFALSE;
     BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken);
 
@@ -129,13 +132,11 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t se
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
   return xSemaphoreTake(sem_hdl, _osal_ms2tick(msec));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
   xQueueReset(sem_hdl);
 }
 
@@ -143,8 +144,7 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c
 // MUTEX API (priority inheritance)
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
 #if configSUPPORT_STATIC_ALLOCATION
   return xSemaphoreCreateMutexStatic(mdef);
 #else
@@ -153,13 +153,11 @@ TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_de
 #endif
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
   return osal_semaphore_wait(mutex_hdl, msec);
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
   return xSemaphoreGive(mutex_hdl);
 }
 
@@ -167,38 +165,35 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd
 // QUEUE API
 //--------------------------------------------------------------------+
 
-TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
-{
+TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) {
   osal_queue_t q;
-  #if configSUPPORT_STATIC_ALLOCATION
-    q = xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
-  #else
-    q = xQueueCreate(qdef->depth, qdef->item_sz);
-  #endif
-  #if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
-    vQueueAddToRegistry(q, "tinyUSB");
-  #endif
+
+#if configSUPPORT_STATIC_ALLOCATION
+  q = xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
+#else
+  q = xQueueCreate(qdef->depth, qdef->item_sz);
+#endif
+
+#if defined(configQUEUE_REGISTRY_SIZE) && (configQUEUE_REGISTRY_SIZE>0)
+  vQueueAddToRegistry(q, qdef->name);
+#endif
+
   return q;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) {
   return xQueueReceive(qhdl, data, _osal_ms2tick(msec));
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
-{
-  if ( !in_isr )
-  {
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
+  if ( !in_isr ) {
     return xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER) != 0;
-  }
-  else
-  {
+  } else {
     BaseType_t xHigherPriorityTaskWoken = pdFALSE;
     BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken);
 
 #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
-    // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7
+    // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7 (IDF v5)
     if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
 #else
     portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
@@ -208,13 +203,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl)
-{
+TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) {
   return uxQueueMessagesWaiting(qhdl) == 0;
 }
 
 #ifdef __cplusplus
- }
+}
 #endif
 
 #endif

From 37a7f9f38287be4a6e1a02193f83c01672793a5e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 12:07:28 +0700
Subject: [PATCH 1954/2085] configQUEUE_REGISTRY_SIZE=4 for lpc18

---
 hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
index ea568dfc9..6f80413c0 100644
--- a/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/lpc18/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               3
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0

From d89fc0772b0844703ae18912b8774df7c11d708c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 14:55:24 +0700
Subject: [PATCH 1955/2085] add makefile, add cdc_uac2 to cmake example list,
 update descriptor to build with nrf and samg/7x

---
 examples/device/CMakeLists.txt                |  1 +
 examples/device/cdc_uac2/CMakeLists.txt       | 16 +++---
 examples/device/cdc_uac2/Makefile             | 16 ++++++
 examples/device/cdc_uac2/skip.txt             | 52 -------------------
 .../cdc_uac2/src/{tusb_cdc.c => cdc_app.c}    |  0
 .../cdc_uac2/src/{tusb_uac2.c => uac2_app.c}  |  0
 .../device/cdc_uac2/src/usb_descriptors.c     | 12 +++++
 7 files changed, 37 insertions(+), 60 deletions(-)
 create mode 100644 examples/device/cdc_uac2/Makefile
 delete mode 100644 examples/device/cdc_uac2/skip.txt
 rename examples/device/cdc_uac2/src/{tusb_cdc.c => cdc_app.c} (100%)
 rename examples/device/cdc_uac2/src/{tusb_uac2.c => uac2_app.c} (100%)

diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index 5b077a5e1..f590fff3f 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -13,6 +13,7 @@ family_add_subdirectory(board_test)
 family_add_subdirectory(cdc_dual_ports)
 family_add_subdirectory(cdc_msc)
 family_add_subdirectory(cdc_msc_freertos)
+family_add_subdirectory(cdc_uac2)
 family_add_subdirectory(dfu)
 family_add_subdirectory(dfu_runtime)
 family_add_subdirectory(dynamic_configuration)
diff --git a/examples/device/cdc_uac2/CMakeLists.txt b/examples/device/cdc_uac2/CMakeLists.txt
index efe8c74ba..64e4374e9 100644
--- a/examples/device/cdc_uac2/CMakeLists.txt
+++ b/examples/device/cdc_uac2/CMakeLists.txt
@@ -19,20 +19,20 @@ add_executable(${PROJECT})
 
 # Example source
 target_sources(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/tusb_cdc.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/tusb_uac2.c
-        ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/uac2_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
+  )
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
-        ${CMAKE_CURRENT_SOURCE_DIR}/src
-        )
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
 
 # Configure compilation flags and libraries for the example... see the corresponding function
 # in hw/bsp/FAMILY/family.cmake for details.
-family_configure_device_example(${PROJECT})
+family_configure_device_example(${PROJECT} noos)
 
 # Uncomment me to enable UART based debugging
 # pico_enable_stdio_uart(${PROJECT} 1)
diff --git a/examples/device/cdc_uac2/Makefile b/examples/device/cdc_uac2/Makefile
new file mode 100644
index 000000000..b7a8302ce
--- /dev/null
+++ b/examples/device/cdc_uac2/Makefile
@@ -0,0 +1,16 @@
+include ../../make.mk
+
+INC += \
+	src \
+	$(TOP)/hw \
+
+# Example source
+EXAMPLE_SOURCE += \
+  src/cdc_app.c \
+  src/main.c \
+  src/uac2_app.c \
+  src/usb_descriptors.c \
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+include ../../rules.mk
diff --git a/examples/device/cdc_uac2/skip.txt b/examples/device/cdc_uac2/skip.txt
deleted file mode 100644
index 8e70a5278..000000000
--- a/examples/device/cdc_uac2/skip.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-board:curiosity_nano
-board:frdm_kl25z
-board:stm32l052dap52
-family:broadcom_32bit
-family:broadcom_64bit
-family:ch32v307
-family:fomu
-family:gd32vf103
-family:kinetis_k32l
-family:kinetis_kl
-family:lpc11
-family:lpc13
-family:lpc15
-family:lpc17
-family:lpc51
-family:lpc54
-family:lpc55
-family:mm32
-family:msp430
-family:msp432e
-family:msp432e4
-family:nrf
-family:ra
-family:rx
-family:samd11
-family:samd21
-family:samd51
-family:same5x
-family:saml2x
-family:stm32f0
-family:stm32f1
-family:stm32f2
-family:stm32f3
-family:stm32f4
-family:stm32f7
-family:stm32g4
-family:stm32h7
-family:stm32l0
-family:stm32l4
-family:stm32u5
-family:stm32wb
-family:tm4c123
-family:xmc4000
-mcu:LPC11UXX
-mcu:LPC13XX
-mcu:MKL25ZXX
-mcu:MSP430x5xx
-mcu:NUC121
-mcu:SAMD11
-mcu:SAME5X
-mcu:SAMG
-mcu:STM32L0
diff --git a/examples/device/cdc_uac2/src/tusb_cdc.c b/examples/device/cdc_uac2/src/cdc_app.c
similarity index 100%
rename from examples/device/cdc_uac2/src/tusb_cdc.c
rename to examples/device/cdc_uac2/src/cdc_app.c
diff --git a/examples/device/cdc_uac2/src/tusb_uac2.c b/examples/device/cdc_uac2/src/uac2_app.c
similarity index 100%
rename from examples/device/cdc_uac2/src/tusb_uac2.c
rename to examples/device/cdc_uac2/src/uac2_app.c
diff --git a/examples/device/cdc_uac2/src/usb_descriptors.c b/examples/device/cdc_uac2/src/usb_descriptors.c
index 1b2766829..58b711978 100644
--- a/examples/device/cdc_uac2/src/usb_descriptors.c
+++ b/examples/device/cdc_uac2/src/usb_descriptors.c
@@ -92,18 +92,30 @@ uint8_t const * tud_descriptor_device_cb(void)
   #define EPNUM_AUDIO_IN    0x08
   #define EPNUM_AUDIO_OUT   0x08
 
+  #define EPNUM_CDC_NOTIF   0x81
+  #define EPNUM_CDC_OUT     0x02
+  #define EPNUM_CDC_IN      0x82
+
 #elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
   // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_AUDIO_IN    0x01
   #define EPNUM_AUDIO_OUT   0x02
 
+  #define EPNUM_CDC_NOTIF   0x83
+  #define EPNUM_CDC_OUT     0x04
+  #define EPNUM_CDC_IN      0x85
+
 #elif CFG_TUSB_MCU == OPT_MCU_FT90X || CFG_TUSB_MCU == OPT_MCU_FT93X
   // FT9XX doesn't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_AUDIO_IN    0x01
   #define EPNUM_AUDIO_OUT   0x02
 
+  #define EPNUM_CDC_NOTIF   0x83
+  #define EPNUM_CDC_OUT     0x04
+  #define EPNUM_CDC_IN      0x85
+
 #else
   #define EPNUM_AUDIO_IN    0x01
   #define EPNUM_AUDIO_OUT   0x01

From 4cb8b513af1c7b9fababba8c7b0af426e9c5e7d6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 15:17:46 +0700
Subject: [PATCH 1956/2085] ide settings

---
 .idea/cmake.xml                       | 4 ++--
 .idea/runConfigurations/kl25.xml      | 2 +-
 .idea/runConfigurations/lpc1857.xml   | 2 +-
 .idea/runConfigurations/lpc4088.xml   | 2 +-
 .idea/runConfigurations/mcx947.xml    | 2 +-
 .idea/runConfigurations/nrf52840.xml  | 2 +-
 .idea/runConfigurations/nrf5340.xml   | 2 +-
 .idea/runConfigurations/rp2040.xml    | 2 +-
 .idea/runConfigurations/rt1010.xml    | 2 +-
 .idea/runConfigurations/rt1060.xml    | 2 +-
 .idea/runConfigurations/stlink.xml    | 2 +-
 .idea/runConfigurations/stm32g474.xml | 2 +-
 .idea/runConfigurations/stm32h743.xml | 2 +-
 13 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index a4f9d7f6d..15bfcd2ad 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -25,7 +25,7 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
+      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="metro m7 1011" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="rt1015 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1015_evk -DLOG=1" />
@@ -48,7 +48,7 @@
       <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="rt1050 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1050_evkb -DLOG=1 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/kl25.xml b/.idea/runConfigurations/kl25.xml
index 3052b440b..a08c20d44 100644
--- a/.idea/runConfigurations/kl25.xml
+++ b/.idea/runConfigurations/kl25.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MKL25Z128xxx4&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MKL25Z128xxx4&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/lpc1857.xml b/.idea/runConfigurations/lpc1857.xml
index f377d86f2..7525f51f7 100644
--- a/.idea/runConfigurations/lpc1857.xml
+++ b/.idea/runConfigurations/lpc1857.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="lpc1857" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc1857&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="lpc1857" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc1857&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/lpc4088.xml b/.idea/runConfigurations/lpc4088.xml
index 89226ac30..7b32b2b85 100644
--- a/.idea/runConfigurations/lpc4088.xml
+++ b/.idea/runConfigurations/lpc4088.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="lpc4088" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc4088&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="ea4088 quickstart" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="lpc4088" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc4088&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/mcx947.xml b/.idea/runConfigurations/mcx947.xml
index 0e7e2befc..77dec59f8 100644
--- a/.idea/runConfigurations/mcx947.xml
+++ b/.idea/runConfigurations/mcx947.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="metro m7" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/nrf52840.xml b/.idea/runConfigurations/nrf52840.xml
index 66473cc0e..084669c39 100644
--- a/.idea/runConfigurations/nrf52840.xml
+++ b/.idea/runConfigurations/nrf52840.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="nrf52840" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;nrf52840_xxaa&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="nrf52840" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;nrf52840_xxaa&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/nrf5340.xml b/.idea/runConfigurations/nrf5340.xml
index 403095d70..98fe39d80 100644
--- a/.idea/runConfigurations/nrf5340.xml
+++ b/.idea/runConfigurations/nrf5340.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="nrf5340" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;nrf5340_xxaa_app&quot; -if swd -speed 16000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="nrf5340" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;nrf5340_xxaa_app&quot; -if swd -speed 16000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/rp2040.xml b/.idea/runConfigurations/rp2040.xml
index 9b6111900..51ae689be 100644
--- a/.idea/runConfigurations/rp2040.xml
+++ b/.idea/runConfigurations/rp2040.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rp2040" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_device_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_device_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rp2040" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <openocd version="1" gdb-port="3333" telnet-port="4444" board-config="$PROJECT_DIR$/hw/bsp/rp2040/rp2040-openocd.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
       <debugger kind="GDB" isBundled="true" />
     </openocd>
diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml
index a39f1f684..63df076b1 100644
--- a/.idea/runConfigurations/rt1010.xml
+++ b/.idea/runConfigurations/rt1010.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/imxrt/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="metro m7" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/imxrt/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/rt1060.xml b/.idea/runConfigurations/rt1060.xml
index 218c2dfbc..147f197a2 100644
--- a/.idea/runConfigurations/rt1060.xml
+++ b/.idea/runConfigurations/rt1060.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1060" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" CONFIG_NAME="pca10056" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rt1060" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml
index c27392ca5..7e9166d90 100644
--- a/.idea/runConfigurations/stlink.xml
+++ b/.idea/runConfigurations/stlink.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-p 62847 -cp &quot;/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.0.600.202301161003/tools/bin&quot; --frequency 24000 --swd" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="stlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-p 62847 -cp &quot;/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.0.600.202301161003/tools/bin&quot; --frequency 24000 --swd" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::62847" executable="/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.linux64_2.0.500.202301161003/tools/bin/ST-LINK_gdbserver" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/stm32g474.xml b/.idea/runConfigurations/stm32g474.xml
index 6076320b5..2e4c4b82a 100644
--- a/.idea/runConfigurations/stm32g474.xml
+++ b/.idea/runConfigurations/stm32g474.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/stm32h743.xml b/.idea/runConfigurations/stm32h743.xml
index 7581ddf9b..f0ab6e9e7 100644
--- a/.idea/runConfigurations/stm32h743.xml
+++ b/.idea/runConfigurations/stm32h743.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stm32h743" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32h743xi&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="stm32h743" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32h743xi&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>

From 4493b838d946a5cc209c92e4e55e63ff2e8534e5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 15:35:01 +0700
Subject: [PATCH 1957/2085] rename ch32v307 and tm4c123 to use underscore

---
 .../boards/{ch32v307v-r1-1v0 => ch32v307v_r1_1v0}/board.h         | 0
 .../boards/{ch32v307v-r1-1v0 => ch32v307v_r1_1v0}/board.mk        | 0
 .../boards/{ch32v307v-r1-1v0 => ch32v307v_r1_1v0}/debug_uart.c    | 0
 .../boards/{ch32v307v-r1-1v0 => ch32v307v_r1_1v0}/debug_uart.h    | 0
 hw/bsp/tm4c123/boards/{ek-tm4c123gxl => ek_tm4c123gxl}/board.h    | 0
 hw/bsp/tm4c123/boards/{ek-tm4c123gxl => ek_tm4c123gxl}/board.mk   | 0
 hw/bsp/tm4c123/boards/{ek-tm4c123gxl => ek_tm4c123gxl}/tm4c123.ld | 0
 7 files changed, 0 insertions(+), 0 deletions(-)
 rename hw/bsp/ch32v307/boards/{ch32v307v-r1-1v0 => ch32v307v_r1_1v0}/board.h (100%)
 rename hw/bsp/ch32v307/boards/{ch32v307v-r1-1v0 => ch32v307v_r1_1v0}/board.mk (100%)
 rename hw/bsp/ch32v307/boards/{ch32v307v-r1-1v0 => ch32v307v_r1_1v0}/debug_uart.c (100%)
 rename hw/bsp/ch32v307/boards/{ch32v307v-r1-1v0 => ch32v307v_r1_1v0}/debug_uart.h (100%)
 rename hw/bsp/tm4c123/boards/{ek-tm4c123gxl => ek_tm4c123gxl}/board.h (100%)
 rename hw/bsp/tm4c123/boards/{ek-tm4c123gxl => ek_tm4c123gxl}/board.mk (100%)
 rename hw/bsp/tm4c123/boards/{ek-tm4c123gxl => ek_tm4c123gxl}/tm4c123.ld (100%)

diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h
similarity index 100%
rename from hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.h
rename to hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h
diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.mk b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk
similarity index 100%
rename from hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/board.mk
rename to hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.mk
diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.c
similarity index 100%
rename from hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.c
rename to hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.c
diff --git a/hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.h b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.h
similarity index 100%
rename from hw/bsp/ch32v307/boards/ch32v307v-r1-1v0/debug_uart.h
rename to hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/debug_uart.h
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h b/hw/bsp/tm4c123/boards/ek_tm4c123gxl/board.h
similarity index 100%
rename from hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.h
rename to hw/bsp/tm4c123/boards/ek_tm4c123gxl/board.h
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk b/hw/bsp/tm4c123/boards/ek_tm4c123gxl/board.mk
similarity index 100%
rename from hw/bsp/tm4c123/boards/ek-tm4c123gxl/board.mk
rename to hw/bsp/tm4c123/boards/ek_tm4c123gxl/board.mk
diff --git a/hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld b/hw/bsp/tm4c123/boards/ek_tm4c123gxl/tm4c123.ld
similarity index 100%
rename from hw/bsp/tm4c123/boards/ek-tm4c123gxl/tm4c123.ld
rename to hw/bsp/tm4c123/boards/ek_tm4c123gxl/tm4c123.ld

From cf91660cee0863291fd9412a3623df018e8bd071 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 15:44:05 +0700
Subject: [PATCH 1958/2085] rename hw/bsp/board.h to board_api.h

---
 examples/device/audio_4_channel_mic/src/main.c           | 2 +-
 examples/device/audio_test/src/main.c                    | 2 +-
 examples/device/audio_test_multi_rate/src/main.c         | 2 +-
 examples/device/board_test/src/main.c                    | 2 +-
 examples/device/cdc_dual_ports/src/main.c                | 2 +-
 examples/device/cdc_msc/src/main.c                       | 2 +-
 examples/device/cdc_msc/src/msc_disk.c                   | 2 +-
 examples/device/cdc_msc_freertos/src/main.c              | 2 +-
 examples/device/cdc_msc_freertos/src/msc_disk.c          | 2 +-
 examples/device/cdc_uac2/src/cdc_app.c                   | 2 +-
 examples/device/cdc_uac2/src/main.c                      | 2 +-
 examples/device/cdc_uac2/src/uac2_app.c                  | 2 +-
 examples/device/dfu/src/main.c                           | 2 +-
 examples/device/dfu_runtime/src/main.c                   | 2 +-
 examples/device/dynamic_configuration/src/main.c         | 2 +-
 examples/device/dynamic_configuration/src/msc_disk.c     | 2 +-
 .../device/dynamic_configuration/src/usb_descriptors.c   | 2 +-
 examples/device/hid_composite/src/main.c                 | 2 +-
 examples/device/hid_composite_freertos/src/main.c        | 2 +-
 examples/device/hid_generic_inout/src/main.c             | 2 +-
 examples/device/hid_multiple_interface/src/main.c        | 2 +-
 examples/device/midi_test/src/main.c                     | 2 +-
 examples/device/msc_dual_lun/src/main.c                  | 2 +-
 examples/device/msc_dual_lun/src/msc_disk_dual.c         | 2 +-
 examples/device/net_lwip_webserver/src/main.c            | 2 +-
 examples/device/uac2_headset/src/main.c                  | 2 +-
 examples/device/usbtmc/src/main.c                        | 2 +-
 examples/device/usbtmc/src/usbtmc_app.c                  | 2 +-
 examples/device/video_capture/src/main.c                 | 2 +-
 examples/device/webusb_serial/src/main.c                 | 2 +-
 examples/dual/host_hid_to_device_cdc/src/main.c          | 2 +-
 examples/host/bare_api/src/main.c                        | 2 +-
 examples/host/cdc_msc_hid/src/cdc_app.c                  | 2 +-
 examples/host/cdc_msc_hid/src/hid_app.c                  | 2 +-
 examples/host/cdc_msc_hid/src/main.c                     | 2 +-
 examples/host/hid_controller/src/hid_app.c               | 2 +-
 examples/host/hid_controller/src/main.c                  | 2 +-
 examples/host/msc_file_explorer/src/main.c               | 2 +-
 examples/host/msc_file_explorer/src/msc_app.c            | 2 +-
 hw/bsp/board.c                                           | 2 +-
 hw/bsp/{board.h => board_api.h}                          | 9 +--------
 hw/bsp/ea4357/ea4357.c                                   | 2 +-
 hw/bsp/fomu/fomu.c                                       | 2 +-
 hw/bsp/gd32vf103/family.c                                | 2 +-
 hw/bsp/ngx4330/ngx4330.c                                 | 2 +-
 hw/bsp/rp2040/family.c                                   | 2 +-
 hw/bsp/sltb009a/sltb009a.c                               | 2 +-
 hw/bsp/stm32l4/family.c                                  | 2 +-
 48 files changed, 48 insertions(+), 55 deletions(-)
 rename hw/bsp/{board.h => board_api.h} (96%)

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 2b9c5143d..0336f0ef0 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -35,7 +35,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index b5ca41d36..9910b496f 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -35,7 +35,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
index 078e783eb..9715ff761 100644
--- a/examples/device/audio_test_multi_rate/src/main.c
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -36,7 +36,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c
index b11f6f2bb..0a134a2e6 100644
--- a/examples/device/board_test/src/main.c
+++ b/examples/device/board_test/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTOTYPES
diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c
index 70eaea85d..5645a953c 100644
--- a/examples/device/cdc_dual_ports/src/main.c
+++ b/examples/device/cdc_dual_ports/src/main.c
@@ -28,7 +28,7 @@
 #include <string.h>
 #include <ctype.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //------------- prototypes -------------//
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index 6dad73cbf..fa303e061 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c
index f8f37a577..d2f8628f1 100644
--- a/examples/device/cdc_msc/src/msc_disk.c
+++ b/examples/device/cdc_msc/src/msc_disk.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #if CFG_TUD_MSC
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 0e8a24d02..fa26771d5 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c
index 707c8d578..9520dfec1 100644
--- a/examples/device/cdc_msc_freertos/src/msc_disk.c
+++ b/examples/device/cdc_msc_freertos/src/msc_disk.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #if CFG_TUD_MSC
diff --git a/examples/device/cdc_uac2/src/cdc_app.c b/examples/device/cdc_uac2/src/cdc_app.c
index a95f638d9..2166c1d6b 100644
--- a/examples/device/cdc_uac2/src/cdc_app.c
+++ b/examples/device/cdc_uac2/src/cdc_app.c
@@ -24,7 +24,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "common.h"
 
diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c
index 68352338e..7afa96c1a 100644
--- a/examples/device/cdc_uac2/src/main.c
+++ b/examples/device/cdc_uac2/src/main.c
@@ -28,7 +28,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "common.h"
 
diff --git a/examples/device/cdc_uac2/src/uac2_app.c b/examples/device/cdc_uac2/src/uac2_app.c
index 33dc33122..98659ea68 100644
--- a/examples/device/cdc_uac2/src/uac2_app.c
+++ b/examples/device/cdc_uac2/src/uac2_app.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 #include "common.h"
diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 5f37f25e1..ab9697a87 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -42,7 +42,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index 4ec3cb188..85b51449e 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -40,7 +40,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index 578f01d8c..4e80ef9c4 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c
index 27856a1a4..10c3ac6fe 100644
--- a/examples/device/dynamic_configuration/src/msc_disk.c
+++ b/examples/device/dynamic_configuration/src/msc_disk.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #if CFG_TUD_MSC
diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index 71348abef..039c7636c 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -24,7 +24,7 @@
  */
 
 #include "tusb.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
  * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 8d0e6bece..94e43df17 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #include "usb_descriptors.h"
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index ca02af100..1241f8edb 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 5db8f5581..55d6bbf21 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* This example demonstrate HID Generic raw Input & Output.
diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c
index 72240b208..dc5d3d7cc 100644
--- a/examples/device/hid_multiple_interface/src/main.c
+++ b/examples/device/hid_multiple_interface/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 2c3e9d954..734a0dae4 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* This MIDI example send sequence of note (on/off) repeatedly. To test on PC, you need to install
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index c7f6de7bf..38b658332 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c
index b1047acdb..4f0f6410f 100644
--- a/examples/device/msc_dual_lun/src/msc_disk_dual.c
+++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #if CFG_TUD_MSC
diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c
index 19a0eae9d..2e432232e 100644
--- a/examples/device/net_lwip_webserver/src/main.c
+++ b/examples/device/net_lwip_webserver/src/main.c
@@ -43,7 +43,7 @@ The smartphone may be artificially picky about which Ethernet MAC address to rec
 try changing the first byte of tud_network_mac_address[] below from 0x02 to 0x00 (clearing bit 1).
 */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 #include "dhserver.h"
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 19a3f7bae..245370bb3 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -26,7 +26,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 2bba336f1..71f352905 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usbtmc_app.h"
 //--------------------------------------------------------------------+
diff --git a/examples/device/usbtmc/src/usbtmc_app.c b/examples/device/usbtmc/src/usbtmc_app.c
index 72989b4fe..fb25982c7 100644
--- a/examples/device/usbtmc/src/usbtmc_app.c
+++ b/examples/device/usbtmc/src/usbtmc_app.c
@@ -26,7 +26,7 @@
 #include <string.h>
 #include <stdlib.h>     /* atoi */
 #include "tusb.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "main.h"
 
 #if (CFG_TUD_USBTMC_ENABLE_488)
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 5654e0b61..589fc448c 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index eaca78c73..675c593dd 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -47,7 +47,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index 817c63c70..74f0a2a41 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -30,7 +30,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c
index bb7fa850e..a50fd33b5 100644
--- a/examples/host/bare_api/src/main.c
+++ b/examples/host/bare_api/src/main.c
@@ -32,7 +32,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 // English
diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c
index 7769d109e..a1b26e49c 100644
--- a/examples/host/cdc_msc_hid/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid/src/cdc_app.c
@@ -25,7 +25,7 @@
  */
 
 #include "tusb.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index 87e110ab2..7727ee62c 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c
index 1f4acb822..3d2567849 100644
--- a/examples/host/cdc_msc_hid/src/main.c
+++ b/examples/host/cdc_msc_hid/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/host/hid_controller/src/hid_app.c b/examples/host/hid_controller/src/hid_app.c
index 76de97b41..bff830ca2 100644
--- a/examples/host/hid_controller/src/hid_app.c
+++ b/examples/host/hid_controller/src/hid_app.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* From https://www.kernel.org/doc/html/latest/input/gamepad.html
diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c
index 4dcc92587..f4f6bda28 100644
--- a/examples/host/hid_controller/src/main.c
+++ b/examples/host/hid_controller/src/main.c
@@ -32,7 +32,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c
index 7b1c2ef27..ced6e01a9 100644
--- a/examples/host/msc_file_explorer/src/main.c
+++ b/examples/host/msc_file_explorer/src/main.c
@@ -59,7 +59,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 003e2865b..323dfb9e7 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -25,7 +25,7 @@
 
 #include <ctype.h>
 #include "tusb.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 #include "ff.h"
 #include "diskio.h"
diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 7804a18e0..417630a03 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -23,7 +23,7 @@
  *
  */
 
-#include "board.h"
+#include "board_api.h"
 
 //--------------------------------------------------------------------+
 // newlib read()/write() retarget
diff --git a/hw/bsp/board.h b/hw/bsp/board_api.h
similarity index 96%
rename from hw/bsp/board.h
rename to hw/bsp/board_api.h
index 036556731..32b10d06b 100644
--- a/hw/bsp/board.h
+++ b/hw/bsp/board_api.h
@@ -24,10 +24,6 @@
  * This file is part of the TinyUSB stack.
  */
 
-/** \ingroup group_demo
- * \defgroup group_board Boards Abstraction Layer
- *  @{ */
-
 #ifndef _BSP_BOARD_H_
 #define _BSP_BOARD_H_
 
@@ -38,7 +34,6 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-#include "ansi_escape.h"
 #include "tusb.h"
 
 // Define the default baudrate
@@ -139,6 +134,4 @@ int board_getchar(void);
  }
 #endif
 
-#endif /* _BSP_BOARD_H_ */
-
-/** @} */
+#endif
diff --git a/hw/bsp/ea4357/ea4357.c b/hw/bsp/ea4357/ea4357.c
index 68bcaa123..06975b8cc 100644
--- a/hw/bsp/ea4357/ea4357.c
+++ b/hw/bsp/ea4357/ea4357.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "../board.h"
+#include "../board_api.h"
 #include "pca9532.h"
 
 #define UART_DEV        LPC_USART0
diff --git a/hw/bsp/fomu/fomu.c b/hw/bsp/fomu/fomu.c
index e079e7c5b..d155b743d 100644
--- a/hw/bsp/fomu/fomu.c
+++ b/hw/bsp/fomu/fomu.c
@@ -26,7 +26,7 @@
 
 #include <stdint.h>
 #include <stdbool.h>
-#include "../board.h"
+#include "../board_api.h"
 #include "csr.h"
 #include "irq.h"
 
diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c
index 113c4c304..27d7e87bb 100644
--- a/hw/bsp/gd32vf103/family.c
+++ b/hw/bsp/gd32vf103/family.c
@@ -28,7 +28,7 @@
 #include "drv_usb_hw.h"
 #include "drv_usb_dev.h"
 
-#include "../board.h"
+#include "../board_api.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/ngx4330/ngx4330.c b/hw/bsp/ngx4330/ngx4330.c
index d61f775c7..a767d5f29 100644
--- a/hw/bsp/ngx4330/ngx4330.c
+++ b/hw/bsp/ngx4330/ngx4330.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "../board.h"
+#include "../board_api.h"
 
 #define LED_PORT              1
 #define LED_PIN               12
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index 40e3f11cd..be5e9f753 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -32,7 +32,7 @@
 #include "hardware/structs/ioqspi.h"
 #include "hardware/structs/sio.h"
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB
diff --git a/hw/bsp/sltb009a/sltb009a.c b/hw/bsp/sltb009a/sltb009a.c
index 2a5d112a8..23ef6d7cd 100644
--- a/hw/bsp/sltb009a/sltb009a.c
+++ b/hw/bsp/sltb009a/sltb009a.c
@@ -25,7 +25,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#include "../board_api.h"
 
 #include "em_device.h"
 
diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c
index d661613af..0b2c22d19 100644
--- a/hw/bsp/stm32l4/family.c
+++ b/hw/bsp/stm32l4/family.c
@@ -27,7 +27,7 @@
  */
 
 #include "stm32l4xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+

From a5768f52b492f7a2ee32f3b786c12532d0876f01 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 15:50:52 +0700
Subject: [PATCH 1959/2085] more board_api.h rename

---
 hw/bsp/board_api.h                            | 58 ++++++++-----------
 hw/bsp/broadcom_32bit/family.c                |  2 +-
 hw/bsp/broadcom_64bit/family.c                |  2 +-
 hw/bsp/brtmm90x/family.c                      |  2 +-
 hw/bsp/ch32v307/family.c                      |  2 +-
 hw/bsp/da14695_dk_usb/da14695_dk_usb.c        |  2 +-
 hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c        |  2 +-
 hw/bsp/espressif/boards/family.c              |  2 +-
 hw/bsp/f1c100s/f1c100s.c                      |  2 +-
 hw/bsp/imxrt/family.c                         |  2 +-
 .../boards/frdm_k32l2a4s/frdm_k32l2a4s.c      |  2 +-
 .../boards/frdm_k32l2b/frdm_k32l2b.c          |  2 +-
 hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c     |  2 +-
 hw/bsp/kinetis_kl/family.c                    |  2 +-
 .../boards/lpcxpresso11u37/lpcxpresso11u37.c  |  2 +-
 .../boards/lpcxpresso11u68/lpcxpresso11u68.c  |  2 +-
 hw/bsp/lpc15/family.c                         |  2 +-
 hw/bsp/lpc18/family.c                         |  2 +-
 hw/bsp/lpc40/family.c                         |  2 +-
 hw/bsp/lpc54/family.c                         |  2 +-
 hw/bsp/lpc55/family.c                         |  2 +-
 hw/bsp/mcx/family.c                           |  2 +-
 hw/bsp/msp430/family.c                        |  2 +-
 hw/bsp/msp432e4/family.c                      |  2 +-
 hw/bsp/nrf/family.c                           |  2 +-
 hw/bsp/nutiny_nuc121s/nutiny_nuc121.c         |  2 +-
 hw/bsp/nutiny_nuc125s/nutiny_nuc125.c         |  2 +-
 hw/bsp/nutiny_nuc126v/nutiny_nuc126.c         |  2 +-
 hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c  |  2 +-
 hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c  |  2 +-
 hw/bsp/ra/family.c                            |  2 +-
 hw/bsp/rx/boards/gr_citrus/gr_citrus.c        |  2 +-
 hw/bsp/rx/boards/rx65n_target/rx65n_target.c  |  2 +-
 hw/bsp/samd11/family.c                        |  2 +-
 hw/bsp/samd21/family.c                        |  2 +-
 hw/bsp/samd51/family.c                        |  2 +-
 hw/bsp/same5x/boards/d5035_01/d5035_01.c      |  2 +-
 .../boards/same54_xplained/same54_xplained.c  |  2 +-
 hw/bsp/same70_qmtech/same70_qmtech.c          |  2 +-
 hw/bsp/same70_xplained/same70_xplained.c      |  2 +-
 hw/bsp/samg55xplained/samg55xplained.c        |  2 +-
 hw/bsp/saml2x/family.c                        |  2 +-
 hw/bsp/spresense/board_spresense.c            |  2 +-
 hw/bsp/stm32f0/family.c                       |  2 +-
 hw/bsp/stm32f1/family.c                       |  2 +-
 .../boards/stm32f207nucleo/stm32f207nucleo.c  |  2 +-
 hw/bsp/stm32f4/family.c                       |  2 +-
 hw/bsp/stm32f7/family.c                       |  2 +-
 hw/bsp/stm32g0/family.c                       |  2 +-
 hw/bsp/stm32g4/family.c                       |  2 +-
 hw/bsp/stm32h7/family.c                       |  2 +-
 hw/bsp/stm32l0/family.c                       |  2 +-
 hw/bsp/stm32u5/family.c                       |  2 +-
 hw/bsp/stm32wb/family.c                       |  2 +-
 hw/bsp/tm4c123/family.c                       |  2 +-
 hw/bsp/xmc4000/family.c                       |  2 +-
 56 files changed, 80 insertions(+), 88 deletions(-)

diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index 32b10d06b..a7f3826d1 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -24,11 +24,11 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _BSP_BOARD_H_
-#define _BSP_BOARD_H_
+#ifndef _BOARD_API_H_
+#define _BOARD_API_H_
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 #include <stdint.h>
@@ -62,40 +62,36 @@ uint32_t board_button_read(void);
 
 // Get characters from UART
 // Return number of read bytes
-int board_uart_read(uint8_t* buf, int len);
+int board_uart_read(uint8_t *buf, int len);
 
 // Send characters to UART
 // Return number of sent bytes
-int board_uart_write(void const * buf, int len);
+int board_uart_write(void const *buf, int len);
 
 #if CFG_TUSB_OS == OPT_OS_NONE
-  // Get current milliseconds, must be implemented when no RTOS is used
-  uint32_t board_millis(void);
+// Get current milliseconds, must be implemented when no RTOS is used
+uint32_t board_millis(void);
 
 #elif CFG_TUSB_OS == OPT_OS_FREERTOS
-  static inline uint32_t board_millis(void)
-  {
-    return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ );
-  }
+static inline uint32_t board_millis(void) {
+  return ( ( ((uint64_t) xTaskGetTickCount()) * 1000) / configTICK_RATE_HZ );
+}
 
 #elif CFG_TUSB_OS == OPT_OS_MYNEWT
-  static inline uint32_t board_millis(void)
-  {
-    return os_time_ticks_to_ms32( os_time_get() );
-  }
+static inline uint32_t board_millis(void) {
+  return os_time_ticks_to_ms32( os_time_get() );
+}
 
 #elif CFG_TUSB_OS == OPT_OS_PICO
-  #include "pico/time.h"
-  static inline uint32_t board_millis(void)
-  {
-    return to_ms_since_boot(get_absolute_time());
-  }
+#include "pico/time.h"
+static inline uint32_t board_millis(void) {
+  return to_ms_since_boot(get_absolute_time());
+}
 
 #elif CFG_TUSB_OS == OPT_OS_RTTHREAD
-  static inline uint32_t board_millis(void)
-  {
-    return (((uint64_t)rt_tick_get()) * 1000 / RT_TICK_PER_SECOND);
-  }
+static inline uint32_t board_millis(void) {
+  return (((uint64_t)rt_tick_get()) * 1000 / RT_TICK_PER_SECOND);
+}
 
 #else
   #error "board_millis() is not implemented for this OS"
@@ -104,22 +100,18 @@ int board_uart_write(void const * buf, int len);
 //--------------------------------------------------------------------+
 // Helper functions
 //--------------------------------------------------------------------+
-static inline void board_led_on(void)
-{
+static inline void board_led_on(void) {
   board_led_write(true);
 }
 
-static inline void board_led_off(void)
-{
+static inline void board_led_off(void) {
   board_led_write(false);
 }
 
 // TODO remove
-static inline void board_delay(uint32_t ms)
-{
+static inline void board_delay(uint32_t ms) {
   uint32_t start_ms = board_millis();
-  while (board_millis() - start_ms < ms)
-  {
+  while ( board_millis() - start_ms < ms ) {
     #if CFG_TUD_ENABLED
     // take chance to run usb background
     tud_task();
@@ -131,7 +123,7 @@ static inline void board_delay(uint32_t ms)
 int board_getchar(void);
 
 #ifdef __cplusplus
- }
+}
 #endif
 
 #endif
diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c
index 42ad4b666..664b4dcaf 100644
--- a/hw/bsp/broadcom_32bit/family.c
+++ b/hw/bsp/broadcom_32bit/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #include "broadcom/cpu.h"
diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c
index 42ad4b666..664b4dcaf 100644
--- a/hw/bsp/broadcom_64bit/family.c
+++ b/hw/bsp/broadcom_64bit/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #include "broadcom/cpu.h"
diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c
index f812c922f..4d81e7d52 100644
--- a/hw/bsp/brtmm90x/family.c
+++ b/hw/bsp/brtmm90x/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #include <ft900.h>
diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c
index d5602c7b4..245fa5674 100644
--- a/hw/bsp/ch32v307/family.c
+++ b/hw/bsp/ch32v307/family.c
@@ -28,7 +28,7 @@
 #include "debug_uart.h"
 #include "ch32v30x.h"
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
index 3abb488f2..667b83de3 100644
--- a/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
+++ b/hw/bsp/da14695_dk_usb/da14695_dk_usb.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include <hal/hal_gpio.h>
 #include <mcu/mcu.h>
 
diff --git a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
index abe7f54cb..21bd62714 100644
--- a/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
+++ b/hw/bsp/da1469x_dk_pro/da1469x-dk-pro.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include <hal/hal_gpio.h>
 #include <mcu/mcu.h>
 
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 8fc4a1cc8..8f857fb71 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #include "esp_rom_gpio.h"
diff --git a/hw/bsp/f1c100s/f1c100s.c b/hw/bsp/f1c100s/f1c100s.c
index 5dcae33f7..272b756f2 100644
--- a/hw/bsp/f1c100s/f1c100s.c
+++ b/hw/bsp/f1c100s/f1c100s.c
@@ -28,7 +28,7 @@
 #include <malloc.h>
 #include <irqflags.h>
 #include <f1c100s-irq.h>
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 extern void sys_uart_putc(char c);
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index bfab1d496..ec95a8b24 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 // Suppress warning caused by mcu driver
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
index 80830163b..39783b7e1 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/frdm_k32l2a4s.c
@@ -25,7 +25,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 #include "fsl_gpio.h"
 #include "fsl_port.h"
diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c
index 1566b4e2e..3f99b0cbd 100644
--- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c
+++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/frdm_k32l2b.c
@@ -25,7 +25,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 #include "fsl_gpio.h"
 #include "fsl_port.h"
diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c
index f9002a6d3..b83d5c820 100644
--- a/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c
+++ b/hw/bsp/kinetis_k32l2/boards/kuiic/kuiic.c
@@ -25,7 +25,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 #include "fsl_smc.h"
 #include "fsl_gpio.h"
diff --git a/hw/bsp/kinetis_kl/family.c b/hw/bsp/kinetis_kl/family.c
index 8914078d5..3e9aa83a4 100644
--- a/hw/bsp/kinetis_kl/family.c
+++ b/hw/bsp/kinetis_kl/family.c
@@ -23,7 +23,7 @@
  * THE SOFTWARE.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
index 02dc2cbf9..900c57936 100644
--- a/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/lpcxpresso11u37.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
index 44d091511..df895804d 100644
--- a/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
+++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/lpcxpresso11u68.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c
index 30a3e51e1..cd5c9ab15 100644
--- a/hw/bsp/lpc15/family.c
+++ b/hw/bsp/lpc15/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index 2fd69c84b..b11f4fe0e 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #ifdef BOARD_TUD_RHPORT
diff --git a/hw/bsp/lpc40/family.c b/hw/bsp/lpc40/family.c
index 829df4ac7..526e3a080 100644
--- a/hw/bsp/lpc40/family.c
+++ b/hw/bsp/lpc40/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index fe9cfcc47..108a7d783 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -30,7 +30,7 @@
 #include "fsl_iocon.h"
 #include "fsl_usart.h"
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #ifdef BOARD_TUD_RHPORT
diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c
index 1d2c87b4f..0fd85988a 100644
--- a/hw/bsp/lpc55/family.c
+++ b/hw/bsp/lpc55/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c
index 4344ffc4e..8672ca63f 100644
--- a/hw/bsp/mcx/family.c
+++ b/hw/bsp/mcx/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
 #include "fsl_lpuart.h"
diff --git a/hw/bsp/msp430/family.c b/hw/bsp/msp430/family.c
index 4b8ae393d..5bb3d3866 100644
--- a/hw/bsp/msp430/family.c
+++ b/hw/bsp/msp430/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 #include "msp430.h"
 
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index 3d2d4085e..10f3ac736 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 #include "msp.h"
 
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 6a559ada6..9ca666e36 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 // Suppress warning caused by mcu driver
diff --git a/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c b/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
index ec66f8deb..7cb9b2e69 100644
--- a/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
+++ b/hw/bsp/nutiny_nuc121s/nutiny_nuc121.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "NuMicro.h"
 #include "clk.h"
 #include "sys.h"
diff --git a/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c b/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
index ec66f8deb..7cb9b2e69 100644
--- a/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
+++ b/hw/bsp/nutiny_nuc125s/nutiny_nuc125.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "NuMicro.h"
 #include "clk.h"
 #include "sys.h"
diff --git a/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c b/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
index 90fa2ffd8..9974127a8 100644
--- a/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
+++ b/hw/bsp/nutiny_nuc126v/nutiny_nuc126.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "NuMicro.h"
 #include "clk.h"
 #include "sys.h"
diff --git a/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c b/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
index 9e7eacb23..18a189d8c 100644
--- a/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
+++ b/hw/bsp/nutiny_sdk_nuc120/nutiny_sdk_nuc120.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "NUC100Series.h"
 #include "clk.h"
 #include "sys.h"
diff --git a/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c b/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
index 1fc97e3dc..3ec0066a3 100644
--- a/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
+++ b/hw/bsp/nutiny_sdk_nuc505/nutiny_sdk_nuc505.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "NUC505Series.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 00b87f335..6a4e14e86 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -45,7 +45,7 @@
 #include "r_ioport_api.h"
 #include "renesas.h"
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 /* Key code for writing PRCR register. */
diff --git a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
index 4f87153ac..5078c7569 100644
--- a/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
+++ b/hw/bsp/rx/boards/gr_citrus/gr_citrus.c
@@ -52,7 +52,7 @@
  * regarding downloading.
  */
 
-#include "../board.h"
+#include "bsp/board_api.h"
 #include "iodefine.h"
 #include "interrupt_handlers.h"
 
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index 691038fc8..513eca678 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -50,7 +50,7 @@
  * regarding downloading.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "iodefine.h"
 #include "interrupt_handlers.h"
 
diff --git a/hw/bsp/samd11/family.c b/hw/bsp/samd11/family.c
index 8d9633971..4a7331508 100644
--- a/hw/bsp/samd11/family.c
+++ b/hw/bsp/samd11/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #include "hal/include/hal_gpio.h"
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index 308fb51b5..46297f97f 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #include "hal/include/hal_gpio.h"
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 3da89ee14..7ec208b30 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #include "hal/include/hal_gpio.h"
diff --git a/hw/bsp/same5x/boards/d5035_01/d5035_01.c b/hw/bsp/same5x/boards/d5035_01/d5035_01.c
index f356851f7..eb5768d0d 100644
--- a/hw/bsp/same5x/boards/d5035_01/d5035_01.c
+++ b/hw/bsp/same5x/boards/d5035_01/d5035_01.c
@@ -24,7 +24,7 @@
  */
 
 #include <sam.h>
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 #include <hal/include/hal_gpio.h>
 
diff --git a/hw/bsp/same5x/boards/same54_xplained/same54_xplained.c b/hw/bsp/same5x/boards/same54_xplained/same54_xplained.c
index ba1eec38b..93adea63e 100644
--- a/hw/bsp/same5x/boards/same54_xplained/same54_xplained.c
+++ b/hw/bsp/same5x/boards/same54_xplained/same54_xplained.c
@@ -24,7 +24,7 @@
  */
 
 #include <sam.h>
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 #include <hal/include/hal_gpio.h>
 
diff --git a/hw/bsp/same70_qmtech/same70_qmtech.c b/hw/bsp/same70_qmtech/same70_qmtech.c
index 6e6ad0602..e5f0da198 100644
--- a/hw/bsp/same70_qmtech/same70_qmtech.c
+++ b/hw/bsp/same70_qmtech/same70_qmtech.c
@@ -24,7 +24,7 @@
  */
 
 #include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 #include "peripheral_clk_config.h"
 #include "hpl/usart/hpl_usart_base.h"
diff --git a/hw/bsp/same70_xplained/same70_xplained.c b/hw/bsp/same70_xplained/same70_xplained.c
index e6e7db0f3..f532c6927 100644
--- a/hw/bsp/same70_xplained/same70_xplained.c
+++ b/hw/bsp/same70_xplained/same70_xplained.c
@@ -24,7 +24,7 @@
  */
 
 #include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 #include "peripheral_clk_config.h"
 #include "hpl/usart/hpl_usart_base.h"
diff --git a/hw/bsp/samg55xplained/samg55xplained.c b/hw/bsp/samg55xplained/samg55xplained.c
index 6e1ed56a9..2ac0c0a29 100644
--- a/hw/bsp/samg55xplained/samg55xplained.c
+++ b/hw/bsp/samg55xplained/samg55xplained.c
@@ -24,7 +24,7 @@
  */
 
 #include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 #include "peripheral_clk_config.h"
 #include "hal/include/hal_init.h"
diff --git a/hw/bsp/saml2x/family.c b/hw/bsp/saml2x/family.c
index f119d23a1..438fe8bfa 100644
--- a/hw/bsp/saml2x/family.c
+++ b/hw/bsp/saml2x/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "sam.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 #include "hal/include/hal_gpio.h"
diff --git a/hw/bsp/spresense/board_spresense.c b/hw/bsp/spresense/board_spresense.c
index 5f778ad70..8cd04a49d 100644
--- a/hw/bsp/spresense/board_spresense.c
+++ b/hw/bsp/spresense/board_spresense.c
@@ -29,7 +29,7 @@
 #include <arch/board/board.h>
 #include <arch/chip/pin.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 /*------------------------------------------------------------------*/
 /* MACRO TYPEDEF CONSTANT ENUM
diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index bfa843494..fe5de84c6 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "stm32f0xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index 5e112de70..49c94a890 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "stm32f1xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c b/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
index 020f21cb1..dfbe7b743 100644
--- a/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
+++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/stm32f207nucleo.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 
 #include "stm32f2xx_hal.h"
 
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index a308bae05..41803e0ce 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "stm32f4xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index ce7e9d1bc..0e9471f33 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -27,7 +27,7 @@
  */
 
 #include "stm32f7xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c
index 1a975915f..e001425ed 100644
--- a/hw/bsp/stm32g0/family.c
+++ b/hw/bsp/stm32g0/family.c
@@ -26,7 +26,7 @@
  */
 
 #include "stm32g0xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index d77183357..a088a0062 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -27,7 +27,7 @@
 #include "stm32g4xx_hal.h"
 #include "stm32g4xx_ll_bus.h"
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index eb4ac841e..535d586ee 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -28,7 +28,7 @@
  */
 
 #include "stm32h7xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c
index 89749fb50..212415744 100644
--- a/hw/bsp/stm32l0/family.c
+++ b/hw/bsp/stm32l0/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "stm32l0xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index ee8a5d7ff..a30d886aa 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -26,7 +26,7 @@
  */
 
 #include "stm32u5xx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c
index e9ca59866..d483c95b7 100644
--- a/hw/bsp/stm32wb/family.c
+++ b/hw/bsp/stm32wb/family.c
@@ -25,7 +25,7 @@
  */
 
 #include "stm32wbxx_hal.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c
index 3f4f43220..ad5ae505f 100644
--- a/hw/bsp/tm4c123/family.c
+++ b/hw/bsp/tm4c123/family.c
@@ -1,5 +1,5 @@
 #include "TM4C123.h"
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c
index 146bef373..832b25a4c 100644
--- a/hw/bsp/xmc4000/family.c
+++ b/hw/bsp/xmc4000/family.c
@@ -28,7 +28,7 @@
 #include "xmc_scu.h"
 #include "xmc_uart.h"
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "board.h"
 
 

From a160da1f2b941741234f429417798b8df5c33294 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 17:19:47 +0700
Subject: [PATCH 1960/2085] add lpc43 family

---
 .github/workflows/cmake_arm.yml               |   2 +-
 examples/device/hid_boot_interface/src/main.c |   2 +-
 examples/typec/power_delivery/src/main.c      |   2 +-
 hw/bsp/board_api.h                            |   6 +-
 hw/bsp/ea4357/board.mk                        |  48 -----
 hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h  | 165 ++++++++++++++++++
 hw/bsp/lpc43/boards/ea4357/board.cmake        |  16 ++
 hw/bsp/lpc43/boards/ea4357/board.h            |  40 +++++
 hw/bsp/lpc43/boards/ea4357/board.mk           |  11 ++
 hw/bsp/{ => lpc43/boards}/ea4357/lpc4357.ld   |   0
 hw/bsp/{ => lpc43/boards}/ea4357/pca9532.c    |   0
 hw/bsp/{ => lpc43/boards}/ea4357/pca9532.h    |   0
 hw/bsp/{ea4357/ea4357.c => lpc43/family.c}    |  15 +-
 hw/bsp/lpc43/family.cmake                     |  97 ++++++++++
 hw/bsp/lpc43/family.mk                        |  34 ++++
 src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h  |   9 +
 16 files changed, 393 insertions(+), 54 deletions(-)
 delete mode 100644 hw/bsp/ea4357/board.mk
 create mode 100644 hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/lpc43/boards/ea4357/board.cmake
 create mode 100644 hw/bsp/lpc43/boards/ea4357/board.h
 create mode 100644 hw/bsp/lpc43/boards/ea4357/board.mk
 rename hw/bsp/{ => lpc43/boards}/ea4357/lpc4357.ld (100%)
 rename hw/bsp/{ => lpc43/boards}/ea4357/pca9532.c (100%)
 rename hw/bsp/{ => lpc43/boards}/ea4357/pca9532.h (100%)
 rename hw/bsp/{ea4357/ea4357.c => lpc43/family.c} (97%)
 create mode 100644 hw/bsp/lpc43/family.cmake
 create mode 100644 hw/bsp/lpc43/family.mk

diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 276360650..5203337ec 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -35,7 +35,7 @@ jobs:
           # Alphabetical order
           - 'imxrt'
           - 'kinetis_kl'
-          - 'lpc18 lpc40'
+          - 'lpc18 lpc40 lpc43'
           - 'lpc55'
           - 'mcx'
           - 'ra'
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 1a155996a..18f301ff0 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c
index 08590aa74..489d01aa1 100644
--- a/examples/typec/power_delivery/src/main.c
+++ b/examples/typec/power_delivery/src/main.c
@@ -27,7 +27,7 @@
 #include <stdio.h>
 #include <string.h>
 
-#include "bsp/board.h"
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index a7f3826d1..7249f618d 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -112,10 +112,14 @@ static inline void board_led_off(void) {
 static inline void board_delay(uint32_t ms) {
   uint32_t start_ms = board_millis();
   while ( board_millis() - start_ms < ms ) {
-    #if CFG_TUD_ENABLED
     // take chance to run usb background
+    #if CFG_TUD_ENABLED
     tud_task();
     #endif
+
+    #if CFG_TUH_ENABLED
+    tuh_task();
+    #endif
   }
 }
 
diff --git a/hw/bsp/ea4357/board.mk b/hw/bsp/ea4357/board.mk
deleted file mode 100644
index 6fd229166..000000000
--- a/hw/bsp/ea4357/board.mk
+++ /dev/null
@@ -1,48 +0,0 @@
-DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
-
-CFLAGS += \
-  -flto \
-  -mthumb \
-  -mabi=aapcs \
-  -mcpu=cortex-m4 \
-  -mfloat-abi=hard \
-  -mfpu=fpv4-sp-d16 \
-  -nostdlib \
-  -DCORE_M4 \
-  -D__USE_LPCOPEN \
-  -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
-
-# mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes  -Wno-error=cast-qual
-
-MCU_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
-
-# All source paths should be relative to the top level.
-LD_FILE = hw/bsp/$(BOARD)/lpc4357.ld
-
-SRC_C += \
-	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
-	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
-	src/portable/ehci/ehci.c \
-	$(MCU_DIR)/../gcc/cr_startup_lpc43xx.c \
-	$(MCU_DIR)/src/chip_18xx_43xx.c \
-	$(MCU_DIR)/src/clock_18xx_43xx.c \
-	$(MCU_DIR)/src/gpio_18xx_43xx.c \
-	$(MCU_DIR)/src/sysinit_18xx_43xx.c \
-	$(MCU_DIR)/src/i2c_18xx_43xx.c \
-	$(MCU_DIR)/src/i2cm_18xx_43xx.c \
-	$(MCU_DIR)/src/uart_18xx_43xx.c \
-	$(MCU_DIR)/src/fpu_init.c
-
-INC += \
-	$(TOP)/$(MCU_DIR)/inc \
-	$(TOP)/$(MCU_DIR)/inc/config_43xx
-
-# For freeRTOS port source
-FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F
-
-# For flash-jlink target
-JLINK_DEVICE = LPC4357_M4
-
-# flash using jlink
-flash: flash-jlink
diff --git a/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..6f80413c0
--- /dev/null
+++ b/hw/bsp/lpc43/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "chip.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc43/boards/ea4357/board.cmake b/hw/bsp/lpc43/boards/ea4357/board.cmake
new file mode 100644
index 000000000..8f4588463
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/board.cmake
@@ -0,0 +1,16 @@
+set(MCU_VARIANT LPC4357)
+
+set(JLINK_DEVICE LPC4357_M4)
+set(PYOCD_TARGET LPC4357)
+set(NXPLINK_DEVICE LPC4357:LPC4357)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc4357.ld)
+
+function(update_board TARGET)
+  # EA4357 use I2C GPIO expander for LED
+  target_sources(${TARGET} PRIVATE
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pca9532.c
+    ${SDK_DIR}/src/i2c_18xx_43xx.c
+    ${SDK_DIR}/src/i2cm_18xx_43xx.c
+    )
+endfunction()
diff --git a/hw/bsp/lpc43/boards/ea4357/board.h b/hw/bsp/lpc43/boards/ea4357/board.h
new file mode 100644
index 000000000..f026324ef
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/board.h
@@ -0,0 +1,40 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_EA4357_H
+#define _BOARD_EA4357_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "pca9532.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/lpc43/boards/ea4357/board.mk b/hw/bsp/lpc43/boards/ea4357/board.mk
new file mode 100644
index 000000000..d0eb08d6d
--- /dev/null
+++ b/hw/bsp/lpc43/boards/ea4357/board.mk
@@ -0,0 +1,11 @@
+# EA4357 use I2C GPIO expander for LED
+SRC_C += \
+  ${BOARD_PATH}/pca9532.c \
+	${SDK_DIR}/src/i2c_18xx_43xx.c \
+	${SDK_DIR}/src/i2cm_18xx_43xx.c \
+
+LD_FILE = ${BOARD_PATH}/lpc4357.ld
+
+JLINK_DEVICE = LPC4357_M4
+
+flash: flash-jlink
diff --git a/hw/bsp/ea4357/lpc4357.ld b/hw/bsp/lpc43/boards/ea4357/lpc4357.ld
similarity index 100%
rename from hw/bsp/ea4357/lpc4357.ld
rename to hw/bsp/lpc43/boards/ea4357/lpc4357.ld
diff --git a/hw/bsp/ea4357/pca9532.c b/hw/bsp/lpc43/boards/ea4357/pca9532.c
similarity index 100%
rename from hw/bsp/ea4357/pca9532.c
rename to hw/bsp/lpc43/boards/ea4357/pca9532.c
diff --git a/hw/bsp/ea4357/pca9532.h b/hw/bsp/lpc43/boards/ea4357/pca9532.h
similarity index 100%
rename from hw/bsp/ea4357/pca9532.h
rename to hw/bsp/lpc43/boards/ea4357/pca9532.h
diff --git a/hw/bsp/ea4357/ea4357.c b/hw/bsp/lpc43/family.c
similarity index 97%
rename from hw/bsp/ea4357/ea4357.c
rename to hw/bsp/lpc43/family.c
index 06975b8cc..ba3191d5f 100644
--- a/hw/bsp/ea4357/ea4357.c
+++ b/hw/bsp/lpc43/family.c
@@ -24,9 +24,20 @@
  * This file is part of the TinyUSB stack.
  */
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 #include "chip.h"
-#include "../board_api.h"
-#include "pca9532.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#include "bsp/board_api.h"
+#include "board.h"
 
 #define UART_DEV        LPC_USART0
 #define UART_PORT       0x0f
diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake
new file mode 100644
index 000000000..9fd78c9c2
--- /dev/null
+++ b/hw/bsp/lpc43/family.cmake
@@ -0,0 +1,97 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC43XX CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${SDK_DIR}/../gcc/cr_startup_lpc43xx.c
+      ${SDK_DIR}/src/chip_18xx_43xx.c
+      ${SDK_DIR}/src/clock_18xx_43xx.c
+      ${SDK_DIR}/src/fpu_init.c
+      ${SDK_DIR}/src/gpio_18xx_43xx.c
+      ${SDK_DIR}/src/sysinit_18xx_43xx.c
+      ${SDK_DIR}/src/uart_18xx_43xx.c
+      )
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -nostdlib
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      __USE_LPCOPEN
+      CORE_M4
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${SDK_DIR}/inc
+      ${SDK_DIR}/inc/config_43xx
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC43XX ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c
+    ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+    ${TOP}/src/portable/ehci/ehci.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc43/family.mk b/hw/bsp/lpc43/family.mk
new file mode 100644
index 000000000..4a1c2fb3c
--- /dev/null
+++ b/hw/bsp/lpc43/family.mk
@@ -0,0 +1,34 @@
+DEPS_SUBMODULES += hw/mcu/nxp/lpcopen
+SDK_DIR = hw/mcu/nxp/lpcopen/lpc43xx/lpc_chip_43xx
+
+include ${TOP}/${BOARD_PATH}/board.mk
+CPU_CORE ?= cortex-m4
+
+CFLAGS += \
+  -flto \
+  -nostdlib \
+  -DCORE_M4 \
+  -D__USE_LPCOPEN \
+  -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
+
+# mcu driver cause following warnings
+CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes  -Wno-error=cast-qual
+
+SRC_C += \
+	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
+	src/portable/chipidea/ci_hs/hcd_ci_hs.c \
+	src/portable/ehci/ehci.c \
+	${SDK_DIR}/../gcc/cr_startup_lpc43xx.c \
+	${SDK_DIR}/src/chip_18xx_43xx.c \
+	${SDK_DIR}/src/clock_18xx_43xx.c \
+	${SDK_DIR}/src/gpio_18xx_43xx.c \
+	${SDK_DIR}/src/sysinit_18xx_43xx.c \
+	${SDK_DIR}/src/i2c_18xx_43xx.c \
+	${SDK_DIR}/src/i2cm_18xx_43xx.c \
+	${SDK_DIR}/src/uart_18xx_43xx.c \
+	${SDK_DIR}/src/fpu_init.c
+
+INC += \
+  $(TOP)/$(BOARD_PATH) \
+	${TOP}/${SDK_DIR}/inc \
+	${TOP}/${SDK_DIR}/inc/config_43xx
diff --git a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
index 2e84c93e7..178eec419 100644
--- a/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
+++ b/src/portable/chipidea/ci_hs/ci_hs_lpc18_43.h
@@ -27,9 +27,18 @@
 #ifndef _CI_HS_LPC18_43_H_
 #define _CI_HS_LPC18_43_H_
 
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
 // LPCOpen for 18xx & 43xx
 #include "chip.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 static const ci_hs_controller_t _ci_controller[] =
 {
   { .reg_base = LPC_USB0_BASE, .irqnum = USB0_IRQn },

From 1324c2862df921d9634e90a78048f5d71a77d894 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 17:32:15 +0700
Subject: [PATCH 1961/2085] more board_api rename

---
 hw/bsp/lpc13/boards/lpcxpresso1347/lpcxpresso1347.c             | 2 +-
 hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c             | 2 +-
 hw/bsp/lpc17/boards/mbed1768/mbed1768.c                         | 2 +-
 hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c           | 2 +-
 .../mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c | 2 +-
 hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c              | 2 +-
 .../mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c   | 2 +-
 hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c           | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/hw/bsp/lpc13/boards/lpcxpresso1347/lpcxpresso1347.c b/hw/bsp/lpc13/boards/lpcxpresso1347/lpcxpresso1347.c
index 8ee611037..e8c85ae22 100644
--- a/hw/bsp/lpc13/boards/lpcxpresso1347/lpcxpresso1347.c
+++ b/hw/bsp/lpc13/boards/lpcxpresso1347/lpcxpresso1347.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
index 24333ad1a..c7d655368 100644
--- a/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
 
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
diff --git a/hw/bsp/lpc17/boards/mbed1768/mbed1768.c b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
index 9f3d294d3..b2c92d640 100644
--- a/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
+++ b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
@@ -25,7 +25,7 @@
  */
 
 #include "chip.h"
-#include "../board.h"
+#include "bsp/board_api.h"
 
 #define LED_PORT              1
 #define LED_PIN               18
diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c b/hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c
index c94b0d6d8..579c9c9ed 100644
--- a/hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c
+++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/lpcxpresso51u68.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#include "bsp/board_api.h"
 #include "fsl_device_registers.h"
 #include "fsl_gpio.h"
 #include "fsl_power.h"
diff --git a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
index 0a07dc749..a4bd95fab 100644
--- a/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
+++ b/hw/bsp/mm32/boards/mm32f327x_bluepillplus/mm32f327x_bluepillplus.c
@@ -29,7 +29,7 @@
 #include "mm32_device.h"
 #include "hal_conf.h"
 #include "tusb.h"
-#include "../board.h"
+#include "bsp/board_api.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
index c3f5bc16d..086532179 100644
--- a/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
+++ b/hw/bsp/mm32/boards/mm32f327x_mb39/mm32f327x_mb39.c
@@ -27,7 +27,7 @@
 #include "mm32_device.h"
 #include "hal_conf.h"
 #include "tusb.h"
-#include "../board.h"
+#include "bsp/board_api.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
index 381e93e11..bd2d36ae0 100644
--- a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
+++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/mm32f327x_pitaya_lite.c
@@ -29,7 +29,7 @@
 #include "mm32_device.h"
 #include "hal_conf.h"
 #include "tusb.h"
-#include "../board.h"
+#include "bsp/board_api.h"
 
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c b/hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
index ac9bda983..d6a39a8e2 100644
--- a/hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
+++ b/hw/bsp/stm32f3/boards/stm32f303disco/stm32f303disco.c
@@ -24,7 +24,7 @@
  * This file is part of the TinyUSB stack.
  */
 
-#include "../board.h"
+#include "bsp/board_api.h"
 #include "stm32f3xx_hal.h"
 
 //--------------------------------------------------------------------+

From 041f510f909f0ce8923389c847a8d55e0b7eeee2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 3 Aug 2023 20:42:34 +0700
Subject: [PATCH 1962/2085] add board_get_unique_id() for serial number

implemented board_get_unique_id() for rp2040 and L4
---
 examples/device/cdc_msc/src/usb_descriptors.c | 54 +++++++++++-------
 hw/bsp/board_api.h                            | 40 +++++++++++--
 hw/bsp/family_support.cmake                   |  3 +-
 hw/bsp/rp2040/family.c                        | 36 +++++++-----
 hw/bsp/rp2040/family.cmake                    |  1 +
 hw/bsp/stm32l4/family.c                       | 56 +++++++++++--------
 6 files changed, 126 insertions(+), 64 deletions(-)

diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index 44c849277..baf919f84 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -236,6 +237,14 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
 char const* string_desc_arr [] =
 {
@@ -247,7 +256,7 @@ char const* string_desc_arr [] =
   "TinyUSB MSC",                 // 5: MSC Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32+1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
@@ -255,30 +264,35 @@ uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
 {
   (void) langid;
 
-  uint8_t chr_count;
+  size_t chr_count;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+  switch(index) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str+1, 32);
+      break;
 
-    const char* str = string_desc_arr[index];
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      const char* str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      if ( chr_count > 31 ) chr_count = 31;
+
+      // Convert ASCII string into UTF-16
+      for(size_t i=0; i<chr_count; i++) {
+        _desc_str[1+i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index 7249f618d..53296cd56 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -60,12 +60,13 @@ void board_led_write(bool state);
 // a '1' means active (pressed), a '0' means inactive.
 uint32_t board_button_read(void);
 
-// Get characters from UART
-// Return number of read bytes
+// Get board unique ID for USB serial number. Return number of bytes. Note max_len is typically 16
+TU_ATTR_WEAK size_t board_get_unique_id(uint8_t id[], size_t max_len);
+
+// Get characters from UART. Return number of read bytes
 int board_uart_read(uint8_t *buf, int len);
 
-// Send characters to UART
-// Return number of sent bytes
+// Send characters to UART. Return number of sent bytes
 int board_uart_write(void const *buf, int len);
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -108,6 +109,37 @@ static inline void board_led_off(void) {
   board_led_write(false);
 }
 
+// Get USB Serial number string from unique ID if available. Return number of character.
+// Input is string descriptor from index 1 (index 0 is type + len)
+static inline size_t board_usb_get_serial(uint16_t desc_str1[], size_t max_chars) {
+  uint8_t serial_id[16] TU_ATTR_ALIGNED(4);
+  size_t serial_len;
+
+  if ( board_get_unique_id ) {
+    serial_len = board_get_unique_id(serial_id, sizeof(serial_id));
+  }else {
+    // fixed serial string is 01234567889ABCDEF
+    *((uint32_t*)(uintptr_t) serial_id) = 0x67452301;
+    *((uint32_t*)(uintptr_t) (serial_id+4)) = 0xEFCDAB89;
+    serial_len = 8;
+  }
+
+  if ( serial_len > max_chars / 2 ) serial_len = max_chars / 2;
+
+  for ( size_t i = 0; i < serial_len; i++ ) {
+    for ( size_t j = 0; j < 2; j++ ) {
+      const char nibble_to_hex[16] = {
+          '0', '1', '2', '3', '4', '5', '6', '7',
+          '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'
+      };
+      uint8_t const nibble = (serial_id[i] >> (j * 4)) & 0xf;
+      desc_str1[i * 2 + (1 - j)] = nibble_to_hex[nibble]; // UTF-16-LE
+    }
+  }
+
+  return 2*serial_len;
+}
+
 // TODO remove
 static inline void board_delay(uint32_t ms) {
   uint32_t start_ms = board_millis();
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index b2e61a824..e5571b3b5 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -289,7 +289,8 @@ function(family_add_default_example_warnings TARGET)
     -Wfatal-errors
     -Wdouble-promotion
     -Wfloat-equal
-    -Wshadow
+    # FIXME commented out because of https://github.com/raspberrypi/pico-sdk/issues/1468
+    #-Wshadow
     -Wwrite-strings
     -Wsign-compare
     -Wmissing-format-attribute
diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c
index be5e9f753..aa9d00c23 100644
--- a/hw/bsp/rp2040/family.c
+++ b/hw/bsp/rp2040/family.c
@@ -27,6 +27,7 @@
 
 #include "pico/stdlib.h"
 #include "pico/binary_info.h"
+#include "pico/unique_id.h"
 #include "hardware/gpio.h"
 #include "hardware/sync.h"
 #include "hardware/structs/ioqspi.h"
@@ -171,17 +172,15 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   (void) state;
 
 #ifdef LED_PIN
-  gpio_put(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  gpio_put(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 #endif
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
 #ifdef BUTTON_BOOTSEL
   return BUTTON_STATE_ACTIVE == get_bootsel_button();
 #else
@@ -189,12 +188,21 @@ uint32_t board_button_read(void)
 #endif
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  pico_unique_board_id_t pico_id;
+  pico_get_unique_board_id(&pico_id);
+
+  size_t len = PICO_UNIQUE_BOARD_ID_SIZE_BYTES;
+  if (len > max_len) len = max_len;
+
+  memcpy(id, pico_id.id, len);
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
 #ifdef UART_DEV
   int count = 0;
-  while ( (count < len) && uart_is_readable(uart_inst) )
-  {
+  while ( (count < len) && uart_is_readable(uart_inst) ) {
     buf[count] = uart_getc(uart_inst);
     count++;
   }
@@ -205,11 +213,10 @@ int board_uart_read(uint8_t* buf, int len)
 #endif
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
 #ifdef UART_DEV
-  char const* bufch = (char const*) buf;
-  for(int i=0;i<len;i++) {
+  char const *bufch = (char const *) buf;
+  for ( int i = 0; i < len; i++ ) {
     uart_putc(uart_inst, bufch[i]);
   }
   return len;
@@ -219,8 +226,7 @@ int board_uart_write(void const * buf, int len)
 #endif
 }
 
-int board_getchar(void)
-{
+int board_getchar(void) {
   return getchar_timeout_us(0);
 }
 
diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake
index 17900dd7a..465041b12 100644
--- a/hw/bsp/rp2040/family.cmake
+++ b/hw/bsp/rp2040/family.cmake
@@ -112,6 +112,7 @@ target_sources(tinyusb_bsp INTERFACE
 target_include_directories(tinyusb_bsp INTERFACE
 	${TOP}/hw
 	)
+target_link_libraries(tinyusb_bsp	INTERFACE pico_unique_id)
 
 # tinyusb_additions will hold our extra settings for examples
 add_library(tinyusb_additions INTERFACE)
diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c
index 0b2c22d19..1c6c595f1 100644
--- a/hw/bsp/stm32l4/family.c
+++ b/hw/bsp/stm32l4/family.c
@@ -48,8 +48,7 @@ void USB_IRQHandler(void)
 
 UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
+void board_init(void) {
   board_clock_init();
 
   // Enable All GPIOs clocks
@@ -177,51 +176,60 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
   HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+
+  uint8_t const len = 12;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
 
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+  HAL_UART_Transmit(&UartHandle, (uint8_t *) (uintptr_t) buf, len, 0xffff);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
   __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 
 }

From 9360a3bd5197792584ede8a33c50a4d3054d84e6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Aug 2023 00:20:47 +0700
Subject: [PATCH 1963/2085] add uid for some stm32

---
 .idea/cmake.xml         |   6 +-
 hw/bsp/board_api.h      |  21 ++++---
 hw/bsp/stm32f0/family.c |  91 +++++++++++++--------------
 hw/bsp/stm32f1/family.c |  73 +++++++++++----------
 hw/bsp/stm32f7/family.c | 136 +++++++++++++++++++++-------------------
 hw/bsp/stm32g0/family.c |  58 +++++++++--------
 hw/bsp/stm32g4/family.c |  63 ++++++++++---------
 hw/bsp/stm32h7/family.c |  91 ++++++++++++++-------------
 hw/bsp/stm32l4/family.c |   3 +-
 9 files changed, 281 insertions(+), 261 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 15bfcd2ad..4c45c5c26 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -25,7 +25,7 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico" />
       <configuration PROFILE_NAME="metro m7 1011" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="rt1015 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1015_evk -DLOG=1" />
@@ -43,12 +43,14 @@
       <configuration PROFILE_NAME="stm32f072disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f072disco" />
       <configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2" />
       <configuration PROFILE_NAME="stm32f769disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f769disco -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco" />
+      <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="rt1050 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1050_evkb -DLOG=1 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ea4357" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4357 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="feather_rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pico_sdk -DPICO_BOARD=adafruit_feather_rp2040" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h
index 53296cd56..18c5b0a32 100644
--- a/hw/bsp/board_api.h
+++ b/hw/bsp/board_api.h
@@ -112,32 +112,33 @@ static inline void board_led_off(void) {
 // Get USB Serial number string from unique ID if available. Return number of character.
 // Input is string descriptor from index 1 (index 0 is type + len)
 static inline size_t board_usb_get_serial(uint16_t desc_str1[], size_t max_chars) {
-  uint8_t serial_id[16] TU_ATTR_ALIGNED(4);
-  size_t serial_len;
+  uint8_t uid[16] TU_ATTR_ALIGNED(4);
+  size_t uid_len;
 
   if ( board_get_unique_id ) {
-    serial_len = board_get_unique_id(serial_id, sizeof(serial_id));
+    uid_len = board_get_unique_id(uid, sizeof(uid));
   }else {
     // fixed serial string is 01234567889ABCDEF
-    *((uint32_t*)(uintptr_t) serial_id) = 0x67452301;
-    *((uint32_t*)(uintptr_t) (serial_id+4)) = 0xEFCDAB89;
-    serial_len = 8;
+    uint32_t* uid32 = (uint32_t*) (uintptr_t) uid;
+    uid32[0] = 0x67452301;
+    uid32[1] = 0xEFCDAB89;
+    uid_len = 8;
   }
 
-  if ( serial_len > max_chars / 2 ) serial_len = max_chars / 2;
+  if ( uid_len > max_chars / 2 ) uid_len = max_chars / 2;
 
-  for ( size_t i = 0; i < serial_len; i++ ) {
+  for ( size_t i = 0; i < uid_len; i++ ) {
     for ( size_t j = 0; j < 2; j++ ) {
       const char nibble_to_hex[16] = {
           '0', '1', '2', '3', '4', '5', '6', '7',
           '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'
       };
-      uint8_t const nibble = (serial_id[i] >> (j * 4)) & 0xf;
+      uint8_t const nibble = (uid[i] >> (j * 4)) & 0xf;
       desc_str1[i * 2 + (1 - j)] = nibble_to_hex[nibble]; // UTF-16-LE
     }
   }
 
-  return 2*serial_len;
+  return 2 * uid_len;
 }
 
 // TODO remove
diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c
index fe5de84c6..7ef126ae6 100644
--- a/hw/bsp/stm32f0/family.c
+++ b/hw/bsp/stm32f0/family.c
@@ -31,8 +31,7 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_IRQHandler(void)
-{
+void USB_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -41,8 +40,7 @@ void USB_IRQHandler(void)
 //--------------------------------------------------------------------+
 UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
+void board_init(void) {
   board_stm32f0_clock_init();
 
   // Enable All GPIOs clocks
@@ -68,7 +66,7 @@ void board_init(void)
 #endif
 
   // LED
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
   GPIO_InitStruct.Pin = LED_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_PULLUP;
@@ -83,20 +81,20 @@ void board_init(void)
   HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 
   // Uart
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Alternate = UART_GPIO_AF;
   HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
 
-  UartHandle.Instance        = UART_DEV;
-  UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
+  UartHandle.Instance = UART_DEV;
+  UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
   UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
-  UartHandle.Init.StopBits   = UART_STOPBITS_1;
-  UartHandle.Init.Parity     = UART_PARITY_NONE;
-  UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
-  UartHandle.Init.Mode       = UART_MODE_TX_RX;
+  UartHandle.Init.StopBits = UART_STOPBITS_1;
+  UartHandle.Init.Parity = UART_PARITY_NONE;
+  UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  UartHandle.Init.Mode = UART_MODE_TX_RX;
   UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
   HAL_UART_Init(&UartHandle);
 
@@ -116,56 +114,59 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
   HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
 
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+  HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t)
+  buf, len, 0xffff);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
-   __asm("BKPT #0\n");
+void HardFault_Handler(void) {
+  __asm("BKPT #0\n");
 }
 
 #ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
 void assert_failed(const char* file, uint32_t line)
 {
   (void) file; (void) line;
@@ -178,7 +179,5 @@ void assert_failed(const char* file, uint32_t line)
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c
index 49c94a890..3b1c5796b 100644
--- a/hw/bsp/stm32f1/family.c
+++ b/hw/bsp/stm32f1/family.c
@@ -31,18 +31,15 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_HP_IRQHandler(void)
-{
+void USB_HP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USB_LP_IRQHandler(void)
-{
+void USB_LP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USBWakeUp_IRQHandler(void)
-{
+void USBWakeUp_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -50,8 +47,7 @@ void USBWakeUp_IRQHandler(void)
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
 
-void board_init(void)
-{
+void board_init(void) {
   board_stm32f1_clock_init();
 
   // Enable All GPIOs clocks
@@ -60,7 +56,7 @@ void board_init(void)
   __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOD_CLK_ENABLE();
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
 
@@ -72,7 +68,7 @@ void board_init(void)
 #endif
 
   // LED
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
   GPIO_InitStruct.Pin = LED_PIN;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = LED_STATE_ON ? GPIO_PULLDOWN : GPIO_PULLUP;
@@ -102,56 +98,59 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
   HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
   __asm("BKPT #0\n");
 }
 
 #ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
 void assert_failed(const char *file, uint32_t line)
 {
   /* USER CODE BEGIN 6 */
@@ -163,7 +162,5 @@ void assert_failed(const char *file, uint32_t line)
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c
index 0e9471f33..b504c435a 100644
--- a/hw/bsp/stm32f7/family.c
+++ b/hw/bsp/stm32f7/family.c
@@ -33,15 +33,13 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
+void OTG_FS_IRQHandler(void) {
   tud_int_handler(0);
 }
 
 // Despite being call USB2_OTG
 // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
-void OTG_HS_IRQHandler(void)
-{
+void OTG_HS_IRQHandler(void) {
   tud_int_handler(1);
 }
 
@@ -51,8 +49,7 @@ void OTG_HS_IRQHandler(void)
 
 UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
+void board_init(void) {
   board_clock_init();
 
   // Enable All GPIOs clocks
@@ -68,7 +65,7 @@ void board_init(void)
   __HAL_RCC_GPIOJ_CLK_ENABLE();
 #endif
 
-  UART_CLK_EN();
+      UART_CLK_EN();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -83,7 +80,7 @@ void board_init(void)
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
 
   // LED
   GPIO_InitStruct.Pin = LED_PIN;
@@ -100,28 +97,28 @@ void board_init(void)
   HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 
   // Uart TX
-  GPIO_InitStruct.Pin       = UART_TX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin = UART_TX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Alternate = UART_GPIO_AF;
   HAL_GPIO_Init(UART_TX_PORT, &GPIO_InitStruct);
 
   // Uart RX
-  GPIO_InitStruct.Pin       = UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin = UART_RX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Alternate = UART_GPIO_AF;
   HAL_GPIO_Init(UART_RX_PORT, &GPIO_InitStruct);
 
-  UartHandle.Instance          = UART_DEV;
-  UartHandle.Init.BaudRate     = CFG_BOARD_UART_BAUDRATE;
-  UartHandle.Init.WordLength   = UART_WORDLENGTH_8B;
-  UartHandle.Init.StopBits     = UART_STOPBITS_1;
-  UartHandle.Init.Parity       = UART_PARITY_NONE;
-  UartHandle.Init.HwFlowCtl    = UART_HWCONTROL_NONE;
-  UartHandle.Init.Mode         = UART_MODE_TX_RX;
+  UartHandle.Instance = UART_DEV;
+  UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
+  UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
+  UartHandle.Init.StopBits = UART_STOPBITS_1;
+  UartHandle.Init.Parity = UART_PARITY_NONE;
+  UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  UartHandle.Init.Mode = UART_MODE_TX_RX;
   UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
   HAL_UART_Init(&UartHandle);
 
@@ -205,46 +202,46 @@ void board_init(void)
   // MUC with external ULPI PHY
 
   /* ULPI CLK */
-  GPIO_InitStruct.Pin       = GPIO_PIN_5;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin = GPIO_PIN_5;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
   /* ULPI D0 */
-  GPIO_InitStruct.Pin       = GPIO_PIN_3;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin = GPIO_PIN_3;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
   /* ULPI D1 D2 D3 D4 D5 D6 D7 */
-  GPIO_InitStruct.Pin       = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_5;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_5;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
   /* ULPI STP */
-  GPIO_InitStruct.Pin       = GPIO_PIN_0 | GPIO_PIN_2;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_2;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 
   /* NXT */
-  GPIO_InitStruct.Pin       = GPIO_PIN_4;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
+  GPIO_InitStruct.Pin = GPIO_PIN_4;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
 
   /* ULPI DIR */
-  GPIO_InitStruct.Pin       = GPIO_PIN_11;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_NOPULL;
+  GPIO_InitStruct.Pin = GPIO_PIN_11;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
   HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
   #endif // USB_HS_PHYC
@@ -276,51 +273,58 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
   HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
-  return 0;
-}
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
 
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
+  return 0;
+}
+
+int board_uart_write(void const *buf, int len) {
+  HAL_UART_Transmit(&UartHandle, (uint8_t *) (uintptr_t) buf, len, 0xffff);
+  return len;
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
   __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c
index e001425ed..3730e44aa 100644
--- a/hw/bsp/stm32g0/family.c
+++ b/hw/bsp/stm32g0/family.c
@@ -32,8 +32,7 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_UCPD1_2_IRQHandler(void)
-{
+void USB_UCPD1_2_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -42,8 +41,7 @@ void USB_UCPD1_2_IRQHandler(void)
 //--------------------------------------------------------------------+
 UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
+void board_init(void) {
   HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS
   board_clock_init();
 
@@ -70,7 +68,7 @@ void board_init(void)
   NVIC_SetPriority(USB_UCPD1_2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
 
   // LED
   GPIO_InitStruct.Pin = LED_PIN;
@@ -130,56 +128,66 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
   HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
 #ifdef UART_DEV
   HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 #else
-  (void) buf; (void) len; (void) UartHandle;
+  (void) buf;
+  (void) len;
+  (void) UartHandle;
   return 0;
 #endif
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
   HAL_IncTick();
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
   __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 
 }
diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c
index a088a0062..39be0249a 100644
--- a/hw/bsp/stm32g4/family.c
+++ b/hw/bsp/stm32g4/family.c
@@ -33,18 +33,15 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB_HP_IRQHandler(void)
-{
+void USB_HP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USB_LP_IRQHandler(void)
-{
+void USB_LP_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USBWakeUp_IRQHandler(void)
-{
+void USBWakeUp_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -58,8 +55,7 @@ void UCPD1_IRQHandler(void) {
 //--------------------------------------------------------------------+
 UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
+void board_init(void) {
   HAL_Init();
   board_clock_init();
 
@@ -162,56 +158,65 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
   HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
 #ifdef UART_DEV
   HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
   return len;
 #else
-  (void) buf; (void) len; (void) UartHandle;
+  (void) buf;
+  (void) len;
+  (void) UartHandle;
   return 0;
 #endif
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
   __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c
index 535d586ee..309a4239e 100644
--- a/hw/bsp/stm32h7/family.c
+++ b/hw/bsp/stm32h7/family.c
@@ -37,15 +37,13 @@
 
 // Despite being call USB2_OTG
 // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
-void OTG_FS_IRQHandler(void)
-{
+void OTG_FS_IRQHandler(void) {
   tud_int_handler(0);
 }
 
 // Despite being call USB2_OTG
 // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
-void OTG_HS_IRQHandler(void)
-{
+void OTG_HS_IRQHandler(void) {
   tud_int_handler(1);
 }
 
@@ -80,8 +78,7 @@ void trace_etm_init(void) {
   #define trace_etm_init()
 #endif
 
-void board_init(void)
-{
+void board_init(void) {
   board_stm32h7_clock_init();
 
   // Enable All GPIOs clocks
@@ -118,37 +115,37 @@ void board_init(void)
   NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
 
   // LED
-  GPIO_InitStruct.Pin   = LED_PIN;
-  GPIO_InitStruct.Mode  = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull  = GPIO_PULLUP;
+  GPIO_InitStruct.Pin = LED_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
 
   // Button
-  GPIO_InitStruct.Pin   = BUTTON_PIN;
-  GPIO_InitStruct.Mode  = GPIO_MODE_INPUT;
-  GPIO_InitStruct.Pull  = GPIO_NOPULL;
+  GPIO_InitStruct.Pin = BUTTON_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
 
   // Uart
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
   GPIO_InitStruct.Alternate = UART_GPIO_AF;
   HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
 
-  UartHandle.Instance        = UART_DEV;
-  UartHandle.Init.BaudRate   = CFG_BOARD_UART_BAUDRATE;
+  UartHandle.Instance = UART_DEV;
+  UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE;
   UartHandle.Init.WordLength = UART_WORDLENGTH_8B;
-  UartHandle.Init.StopBits   = UART_STOPBITS_1;
-  UartHandle.Init.Parity     = UART_PARITY_NONE;
-  UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
-  UartHandle.Init.Mode       = UART_MODE_TX_RX;
+  UartHandle.Init.StopBits = UART_STOPBITS_1;
+  UartHandle.Init.Parity = UART_PARITY_NONE;
+  UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  UartHandle.Init.Mode = UART_MODE_TX_RX;
   UartHandle.Init.OverSampling = UART_OVERSAMPLING_16;
   HAL_UART_Init(&UartHandle);
 
@@ -249,52 +246,60 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON));
   HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return (BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN)) ? 1 : 0;
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+int board_uart_write(void const *buf, int len) {
+  HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t)
+  buf, len, 0xffff);
   return len;
 }
 
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler(void)
-{
+void HardFault_Handler(void) {
   __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c
index 1c6c595f1..965c4810a 100644
--- a/hw/bsp/stm32l4/family.c
+++ b/hw/bsp/stm32l4/family.c
@@ -188,9 +188,8 @@ uint32_t board_button_read(void) {
 size_t board_get_unique_id(uint8_t id[], size_t max_len) {
   (void) max_len;
   volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
-
-  uint8_t const len = 12;
   uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  uint8_t const len = 12;
 
   id32[0] = stm32_uuid[0];
   id32[1] = stm32_uuid[1];

From 67ff3f7845e2e2c4b95ce4ff91357257faf3080f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Aug 2023 00:37:01 +0700
Subject: [PATCH 1964/2085] more clean up

---
 .idea/cmake.xml                    | 12 ++++++------
 .idea/runConfigurations/ra4m1.xml  |  2 +-
 .idea/runConfigurations/ra6m1.xml  |  2 +-
 .idea/runConfigurations/ra6m5.xml  |  2 +-
 .idea/runConfigurations/uno_r4.xml |  2 +-
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 7d1260893..b1d024b81 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,8 +2,6 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
@@ -24,23 +22,27 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
+      <configuration PROFILE_NAME="rp2040" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
+      <configuration PROFILE_NAME="feather_rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pico_sdk -DPICO_BOARD=adafruit_feather_rp2040" />
       <configuration PROFILE_NAME="metro m7 1011" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="rt1060 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1060_evk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="ea4357" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4357 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69" />
       <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
+      <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g0b1nucleo" />
       <configuration PROFILE_NAME="stm32g474nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g474nucleo" />
       <configuration PROFILE_NAME="b_g474e_dpow1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=b_g474e_dpow1 -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="b_g474e_dpow1 iar" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=b_g474e_dpow1 -DTOOLCHAIN=iar" />
       <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_kl25z -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="stm32h743eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="stm32f072disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f072disco" />
       <configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2" />
       <configuration PROFILE_NAME="stm32f769disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f769disco -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32h743eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco" />
       <configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
@@ -48,8 +50,6 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
-      <configuration PROFILE_NAME="ea4357" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4357 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="feather_rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pico_sdk -DPICO_BOARD=adafruit_feather_rp2040" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml
index 149a157c4..561b509a2 100644
--- a/.idea/runConfigurations/ra4m1.xml
+++ b/.idea/runConfigurations/ra4m1.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml
index 57af9abd9..099510c60 100644
--- a/.idea/runConfigurations/ra6m1.xml
+++ b/.idea/runConfigurations/ra6m1.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml
index 1a6358304..0cffac135 100644
--- a/.idea/runConfigurations/ra6m5.xml
+++ b/.idea/runConfigurations/ra6m5.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc_hid" CONFIG_NAME="ra6m5" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc_hid">
+  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/uno_r4.xml b/.idea/runConfigurations/uno_r4.xml
index 9982f4039..e9e1ebb8d 100644
--- a/.idea/runConfigurations/uno_r4.xml
+++ b/.idea/runConfigurations/uno_r4.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="uno_r4" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 20000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="cdc_msc" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="cdc_msc" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="uno_r4" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 20000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>

From 9697c4df4e57435781119c0d4716635f344ed8f1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Aug 2023 10:28:24 +0700
Subject: [PATCH 1965/2085] update all examples to use unique ID as serial if
 avaialble

---
 .../audio_4_channel_mic/src/usb_descriptors.c |  72 +++++----
 .../device/audio_test/src/usb_descriptors.c   |  68 ++++----
 .../src/usb_descriptors.c                     |  68 ++++----
 .../cdc_dual_ports/src/usb_descriptors.c      |  65 ++++----
 examples/device/cdc_msc/src/usb_descriptors.c | 145 ++++++++----------
 .../cdc_msc_freertos/src/usb_descriptors.c    |  63 +++++---
 .../device/cdc_uac2/src/usb_descriptors.c     |  64 +++++---
 examples/device/dfu/src/usb_descriptors.c     |  66 ++++----
 .../device/dfu_runtime/src/usb_descriptors.c  |  66 ++++----
 .../src/usb_descriptors.c                     |  64 ++++----
 .../hid_boot_interface/src/usb_descriptors.c  |  63 +++++---
 .../hid_composite/src/usb_descriptors.c       |  63 +++++---
 .../src/usb_descriptors.c                     |  63 +++++---
 .../hid_generic_inout/src/usb_descriptors.c   |  63 +++++---
 .../src/usb_descriptors.c                     |  63 +++++---
 .../device/midi_test/src/usb_descriptors.c    |  65 ++++----
 .../device/msc_dual_lun/src/usb_descriptors.c |  63 +++++---
 .../net_lwip_webserver/src/usb_descriptors.c  |  68 ++++----
 .../device/uac2_headset/src/usb_descriptors.c |  64 +++++---
 examples/device/usbtmc/src/usb_descriptors.c  |  66 ++++----
 .../video_capture/src/usb_descriptors.c       |  63 +++++---
 .../webusb_serial/src/usb_descriptors.c       |  63 +++++---
 .../src/usb_descriptors.c                     |  63 +++++---
 23 files changed, 917 insertions(+), 654 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/usb_descriptors.c b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
index b77da9fac..728a5f9ce 100644
--- a/examples/device/audio_4_channel_mic/src/usb_descriptors.c
+++ b/examples/device/audio_4_channel_mic/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -116,50 +117,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
-// array of pointer to string descriptors
-char const* string_desc_arr [] =
-{
-    (const char[]) { 0x09, 0x04 }, 	// 0: is supported language is English (0x0409)
-    "PaniRCorp",                   	// 1: Manufacturer
-    "MicNode_4_Ch",    		// 2: Product
-    "123458",                      	// 3: Serials, should use chip ID
-    "UAC2",                 	 	// 4: Audio Interface
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
 };
 
-static uint16_t _desc_str[32];
+// array of pointer to string descriptors
+char const* string_desc_arr [] = {
+    (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+    "PaniRCorp",                   // 1: Manufacturer
+    "MicNode_4_Ch",                // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "UAC2",                        // 4: Audio Interface
+};
+
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Convert ASCII string into UTF-16
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/audio_test/src/usb_descriptors.c b/examples/device/audio_test/src/usb_descriptors.c
index cc364ee88..9864377f6 100644
--- a/examples/device/audio_test/src/usb_descriptors.c
+++ b/examples/device/audio_test/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -116,50 +117,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
 char const* string_desc_arr [] =
 {
-    (const char[]) { 0x09, 0x04 }, 	// 0: is supported language is English (0x0409)
-    "PaniRCorp",                   	// 1: Manufacturer
-    "MicNode",              		// 2: Product
-    "123456",                      	// 3: Serials, should use chip ID
-    "UAC2",                 	 	// 4: Audio Interface
+    (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+    "PaniRCorp",                   // 1: Manufacturer
+    "MicNode",                     // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "UAC2",                        // 4: Audio Interface
+
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Convert ASCII string into UTF-16
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/audio_test_multi_rate/src/usb_descriptors.c b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
index 2c72edb17..f50e70a25 100644
--- a/examples/device/audio_test_multi_rate/src/usb_descriptors.c
+++ b/examples/device/audio_test_multi_rate/src/usb_descriptors.c
@@ -24,6 +24,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -120,50 +121,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
 char const* string_desc_arr [] =
 {
-    (const char[]) { 0x09, 0x04 }, 	// 0: is supported language is English (0x0409)
-    "PaniRCorp",                   	// 1: Manufacturer
-    "MicNode",              		// 2: Product
-    "123456",                      	// 3: Serials, should use chip ID
-    "UAC2",                 	 	// 4: Audio Interface
+    (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+    "PaniRCorp",                   // 1: Manufacturer
+    "MicNode",                     // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "UAC2",                        // 4: Audio Interface
+
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Convert ASCII string into UTF-16
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c
index 8be404cc9..de2505c07 100644
--- a/examples/device/cdc_dual_ports/src/usb_descriptors.c
+++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c
@@ -23,13 +23,14 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
  * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
  *
  * Auto ProductID layout's Bitmap:
- *   [MSB]       MIDI | HID | MSC | CDC          [LSB]
+ *   [MSB]         HID | MSC | CDC          [LSB]
  */
 #define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
@@ -213,52 +214,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB CDC",                 // 4: CDC Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c
index baf919f84..2afa24903 100644
--- a/examples/device/cdc_msc/src/usb_descriptors.c
+++ b/examples/device/cdc_msc/src/usb_descriptors.c
@@ -42,35 +42,33 @@
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
-tusb_desc_device_t const desc_device =
-{
-  .bLength            = sizeof(tusb_desc_device_t),
-  .bDescriptorType    = TUSB_DESC_DEVICE,
-  .bcdUSB             = USB_BCD,
+tusb_desc_device_t const desc_device = {
+    .bLength            = sizeof(tusb_desc_device_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE,
+    .bcdUSB             = USB_BCD,
 
-  // Use Interface Association Descriptor (IAD) for CDC
-  // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
-  .bDeviceClass       = TUSB_CLASS_MISC,
-  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
-  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    // Use Interface Association Descriptor (IAD) for CDC
+    // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1)
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
 
-  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-  .idVendor           = USB_VID,
-  .idProduct          = USB_PID,
-  .bcdDevice          = 0x0100,
+    .idVendor           = USB_VID,
+    .idProduct          = USB_PID,
+    .bcdDevice          = 0x0100,
 
-  .iManufacturer      = 0x01,
-  .iProduct           = 0x02,
-  .iSerialNumber      = 0x03,
+    .iManufacturer      = 0x01,
+    .iProduct           = 0x02,
+    .iSerialNumber      = 0x03,
 
-  .bNumConfigurations = 0x01
+    .bNumConfigurations = 0x01
 };
 
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
-uint8_t const * tud_descriptor_device_cb(void)
-{
+uint8_t const *tud_descriptor_device_cb(void) {
   return (uint8_t const *) &desc_device;
 }
 
@@ -78,8 +76,7 @@ uint8_t const * tud_descriptor_device_cb(void)
 // Configuration Descriptor
 //--------------------------------------------------------------------+
 
-enum
-{
+enum {
   ITF_NUM_CDC = 0,
   ITF_NUM_CDC_DATA,
   ITF_NUM_MSC,
@@ -96,7 +93,7 @@ enum
   #define EPNUM_MSC_OUT     0x05
   #define EPNUM_MSC_IN      0x85
 
-#elif CFG_TUSB_MCU == OPT_MCU_SAMG  || CFG_TUSB_MCU ==  OPT_MCU_SAMX7X
+#elif CFG_TUSB_MCU == OPT_MCU_SAMG || CFG_TUSB_MCU == OPT_MCU_SAMX7X
   // SAMG & SAME70 don't support a same endpoint number with different direction IN and OUT
   //    e.g EP1 OUT & EP1 IN cannot exist together
   #define EPNUM_CDC_NOTIF   0x81
@@ -141,67 +138,62 @@ enum
 #define CONFIG_TOTAL_LEN    (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_MSC_DESC_LEN)
 
 // full speed configuration
-uint8_t const desc_fs_configuration[] =
-{
-  // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+uint8_t const desc_fs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
-  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
+    // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 64),
 
-  // Interface number, string index, EP Out & EP In address, EP size
-  TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64),
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 64),
 };
 
 #if TUD_OPT_HIGH_SPEED
 // Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration
 
 // high speed configuration
-uint8_t const desc_hs_configuration[] =
-{
-  // Config number, interface count, string index, total length, attribute, power in mA
-  TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
+uint8_t const desc_hs_configuration[] = {
+    // Config number, interface count, string index, total length, attribute, power in mA
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100),
 
-  // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
-  TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
+    // Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC, 4, EPNUM_CDC_NOTIF, 8, EPNUM_CDC_OUT, EPNUM_CDC_IN, 512),
 
-  // Interface number, string index, EP Out & EP In address, EP size
-  TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
+    // Interface number, string index, EP Out & EP In address, EP size
+    TUD_MSC_DESCRIPTOR(ITF_NUM_MSC, 5, EPNUM_MSC_OUT, EPNUM_MSC_IN, 512),
 };
 
 // other speed configuration
 uint8_t desc_other_speed_config[CONFIG_TOTAL_LEN];
 
 // device qualifier is mostly similar to device descriptor since we don't change configuration based on speed
-tusb_desc_device_qualifier_t const desc_device_qualifier =
-{
-  .bLength            = sizeof(tusb_desc_device_qualifier_t),
-  .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
-  .bcdUSB             = USB_BCD,
+tusb_desc_device_qualifier_t const desc_device_qualifier = {
+    .bLength            = sizeof(tusb_desc_device_qualifier_t),
+    .bDescriptorType    = TUSB_DESC_DEVICE_QUALIFIER,
+    .bcdUSB             = USB_BCD,
 
-  .bDeviceClass       = TUSB_CLASS_MISC,
-  .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
-  .bDeviceProtocol    = MISC_PROTOCOL_IAD,
+    .bDeviceClass       = TUSB_CLASS_MISC,
+    .bDeviceSubClass    = MISC_SUBCLASS_COMMON,
+    .bDeviceProtocol    = MISC_PROTOCOL_IAD,
 
-  .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
-  .bNumConfigurations = 0x01,
-  .bReserved          = 0x00
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+    .bNumConfigurations = 0x01,
+    .bReserved          = 0x00
 };
 
 // Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
 // device_qualifier descriptor describes information about a high-speed capable device that would
 // change if the device were operating at the other speed. If not highspeed capable stall this request.
-uint8_t const* tud_descriptor_device_qualifier_cb(void)
-{
-  return (uint8_t const*) &desc_device_qualifier;
+uint8_t const *tud_descriptor_device_qualifier_cb(void) {
+  return (uint8_t const *) &desc_device_qualifier;
 }
 
 // Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
 // Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
-uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
-{
+uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
 
   // if link speed is high return fullspeed config, and vice versa
@@ -221,13 +213,12 @@ uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index)
 // Invoked when received GET CONFIGURATION DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
-uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
-{
+uint8_t const *tud_descriptor_configuration_cb(uint8_t index) {
   (void) index; // for multiple configurations
 
 #if TUD_OPT_HIGH_SPEED
   // Although we are highspeed, host may be fullspeed.
-  return (tud_speed_get() == TUSB_SPEED_HIGH) ?  desc_hs_configuration : desc_fs_configuration;
+  return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration;
 #else
   return desc_fs_configuration;
 #endif
@@ -246,57 +237,55 @@ enum {
 };
 
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
-{
-  (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
-  "TinyUSB",                     // 1: Manufacturer
-  "TinyUSB Device",              // 2: Product
-  "123456789012",                // 3: Serials, should use chip ID
-  "TinyUSB CDC",                 // 4: CDC Interface
-  "TinyUSB MSC",                 // 5: MSC Interface
+char const *string_desc_arr[] = {
+    (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
+    "TinyUSB",                     // 1: Manufacturer
+    "TinyUSB Device",              // 2: Product
+    NULL,                          // 3: Serials will use unique ID if possible
+    "TinyUSB CDC",                 // 4: CDC Interface
+    "TinyUSB MSC",                 // 5: MSC Interface
 };
 
-static uint16_t _desc_str[32+1];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
-
   size_t chr_count;
 
-  switch(index) {
+  switch ( index ) {
     case STRID_LANGID:
       memcpy(&_desc_str[1], string_desc_arr[0], 2);
       chr_count = 1;
       break;
 
     case STRID_SERIAL:
-      chr_count = board_usb_get_serial(_desc_str+1, 32);
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
       break;
 
     default:
       // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
       // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-      if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-      const char* str = string_desc_arr[index];
+      const char *str = string_desc_arr[index];
 
       // Cap at max char
       chr_count = strlen(str);
-      if ( chr_count > 31 ) chr_count = 31;
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
 
       // Convert ASCII string into UTF-16
-      for(size_t i=0; i<chr_count; i++) {
-        _desc_str[1+i] = str[i];
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
       }
       break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
index 822442724..9c29701c7 100644
--- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c
+++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -212,53 +213,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456789012",                // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB CDC",                 // 4: CDC Interface
   "TinyUSB MSC",                 // 5: MSC Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/cdc_uac2/src/usb_descriptors.c b/examples/device/cdc_uac2/src/usb_descriptors.c
index 58b711978..72a695622 100644
--- a/examples/device/cdc_uac2/src/usb_descriptors.c
+++ b/examples/device/cdc_uac2/src/usb_descriptors.c
@@ -25,6 +25,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -150,53 +151,66 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 },  // 0: is supported language is English (0x0409)
   "TinyUSB",                      // 1: Manufacturer
   "TinyUSB headset",              // 2: Product
-  "000001",                       // 3: Serials, should use chip ID
+  NULL,                           // 3: Serials will use unique ID if possible
   "TinyUSB Speakers",             // 4: Audio Interface
   "TinyUSB Microphone",           // 5: Audio Interface
   "TinyUSB CDC",                  // 6: Audio Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
-  (void)langid;
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if (index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }
-  else
-  {
-    // Convert ASCII string into UTF-16
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if (!(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0]))) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if (chr_count > 31) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    for (uint8_t i = 0; i < chr_count; i++)
-    {
-      _desc_str[1 + i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/dfu/src/usb_descriptors.c b/examples/device/dfu/src/usb_descriptors.c
index 51a0d09f5..fd469aaf2 100644
--- a/examples/device/dfu/src/usb_descriptors.c
+++ b/examples/device/dfu/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "class/dfu/dfu_device.h"
 
@@ -116,56 +117,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "FLASH",                       // 4: DFU Partition 1
   "EEPROM",                      // 5: DFU Partition 2
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
-
   size_t chr_count;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }
-  else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    const char* str = string_desc_arr[index];
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) {
-      chr_count = 31;
-    }
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t)((((uint16_t)TUSB_DESC_STRING) << 8 ) | (2u*chr_count + 2u));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/dfu_runtime/src/usb_descriptors.c b/examples/device/dfu_runtime/src/usb_descriptors.c
index 1b0a60551..7ac53d255 100644
--- a/examples/device/dfu_runtime/src/usb_descriptors.c
+++ b/examples/device/dfu_runtime/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "class/dfu/dfu_rt_device.h"
 
@@ -112,55 +113,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB DFU runtime",         // 4: DFU runtime
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
-
   size_t chr_count;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }
-  else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    const char* str = string_desc_arr[index];
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) {
-      chr_count = 31;
-    }
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c
index 039c7636c..7f35b4b22 100644
--- a/examples/device/dynamic_configuration/src/usb_descriptors.c
+++ b/examples/device/dynamic_configuration/src/usb_descriptors.c
@@ -23,8 +23,8 @@
  *
  */
 
-#include "tusb.h"
 #include "bsp/board_api.h"
+#include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
  * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
@@ -206,51 +206,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_boot_interface/src/usb_descriptors.c b/examples/device/hid_boot_interface/src/usb_descriptors.c
index 10345ab41..d68ef16d9 100644
--- a/examples/device/hid_boot_interface/src/usb_descriptors.c
+++ b/examples/device/hid_boot_interface/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -130,51 +131,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_composite/src/usb_descriptors.c b/examples/device/hid_composite/src/usb_descriptors.c
index 347bbf29a..e174db46d 100644
--- a/examples/device/hid_composite/src/usb_descriptors.c
+++ b/examples/device/hid_composite/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -177,51 +178,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_composite_freertos/src/usb_descriptors.c b/examples/device/hid_composite_freertos/src/usb_descriptors.c
index 30f327d5e..85820de55 100644
--- a/examples/device/hid_composite_freertos/src/usb_descriptors.c
+++ b/examples/device/hid_composite_freertos/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -175,51 +176,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_generic_inout/src/usb_descriptors.c b/examples/device/hid_generic_inout/src/usb_descriptors.c
index 8377a0f47..64f6d17ae 100644
--- a/examples/device/hid_generic_inout/src/usb_descriptors.c
+++ b/examples/device/hid_generic_inout/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -120,51 +121,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/hid_multiple_interface/src/usb_descriptors.c b/examples/device/hid_multiple_interface/src/usb_descriptors.c
index 42471a961..86f567e8e 100644
--- a/examples/device/hid_multiple_interface/src/usb_descriptors.c
+++ b/examples/device/hid_multiple_interface/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -136,53 +137,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 },  // 0: is supported language is English (0x0409)
   "TinyUSB",                      // 1: Manufacturer
   "TinyUSB Device",               // 2: Product
-  "123456",                       // 3: Serials, should use chip ID
+  NULL,                           // 3: Serials will use unique ID if possible
   "Keyboard Interface",           // 4: Interface 1 String
   "Mouse Interface",              // 5: Interface 2 String
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c
index 4845dcf57..9781d3d6f 100644
--- a/examples/device/midi_test/src/usb_descriptors.c
+++ b/examples/device/midi_test/src/usb_descriptors.c
@@ -23,13 +23,14 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
  * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC.
  *
  * Auto ProductID layout's Bitmap:
- *   [MSB]       MIDI | HID | MSC | CDC          [LSB]
+ *   [MSB]         HID | MSC | CDC          [LSB]
  */
 #define _PID_MAP(itf, n)  ( (CFG_TUD_##itf) << (n) )
 #define USB_PID           (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \
@@ -133,51 +134,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c
index 2de81111c..c0610945f 100644
--- a/examples/device/msc_dual_lun/src/usb_descriptors.c
+++ b/examples/device/msc_dual_lun/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -141,51 +142,63 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456789012",                // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c
index 3c0ed3db7..da628c8be 100644
--- a/examples/device/net_lwip_webserver/src/usb_descriptors.c
+++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -190,55 +191,56 @@ static char const* string_desc_arr [] =
   [STRID_LANGID]       = (const char[]) { 0x09, 0x04 }, // supported language is English (0x0409)
   [STRID_MANUFACTURER] = "TinyUSB",                     // Manufacturer
   [STRID_PRODUCT]      = "TinyUSB Device",              // Product
-  [STRID_SERIAL]       = "123456",                      // Serial
+  [STRID_SERIAL]       = NULL,                          // Serials will use unique ID if possible
   [STRID_INTERFACE]    = "TinyUSB Network Interface"    // Interface Description
 
   // STRID_MAC index is handled separately
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
-
   unsigned int chr_count = 0;
 
-  if (STRID_LANGID == index)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[STRID_LANGID], 2);
-    chr_count = 1;
-  }
-  else if (STRID_MAC == index)
-  {
-    // Convert MAC address into UTF-16
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-    for (unsigned i=0; i<sizeof(tud_network_mac_address); i++)
-    {
-      _desc_str[1+chr_count++] = "0123456789ABCDEF"[(tud_network_mac_address[i] >> 4) & 0xf];
-      _desc_str[1+chr_count++] = "0123456789ABCDEF"[(tud_network_mac_address[i] >> 0) & 0xf];
-    }
-  }
-  else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    case STRID_MAC:
+      // Convert MAC address into UTF-16
+      for (unsigned i=0; i<sizeof(tud_network_mac_address); i++) {
+        _desc_str[1+chr_count++] = "0123456789ABCDEF"[(tud_network_mac_address[i] >> 4) & 0xf];
+        _desc_str[1+chr_count++] = "0123456789ABCDEF"[(tud_network_mac_address[i] >> 0) & 0xf];
+      }
+      break;
 
-    const char* str = string_desc_arr[index];
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > (TU_ARRAY_SIZE(_desc_str) - 1)) chr_count = TU_ARRAY_SIZE(_desc_str) - 1;
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Convert ASCII string into UTF-16
-    for (unsigned int i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c
index 682774b72..6d1e6a23f 100644
--- a/examples/device/uac2_headset/src/usb_descriptors.c
+++ b/examples/device/uac2_headset/src/usb_descriptors.c
@@ -24,6 +24,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -126,52 +127,65 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 },  // 0: is supported language is English (0x0409)
   "TinyUSB",                      // 1: Manufacturer
   "TinyUSB headset",              // 2: Product
-  "000001",                       // 3: Serials, should use chip ID
+  NULL,                           // 3: Serials will use unique ID if possible
   "TinyUSB Speakers",             // 4: Audio Interface
   "TinyUSB Microphone",           // 5: Audio Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
-  (void)langid;
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
+  (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if (index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }
-  else
-  {
-    // Convert ASCII string into UTF-16
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if (!(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0]))) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if (chr_count > 31) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    for (uint8_t i = 0; i < chr_count; i++)
-    {
-      _desc_str[1 + i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/usbtmc/src/usb_descriptors.c b/examples/device/usbtmc/src/usb_descriptors.c
index ff682ff97..54948291e 100644
--- a/examples/device/usbtmc/src/usb_descriptors.c
+++ b/examples/device/usbtmc/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "class/usbtmc/usbtmc.h"
 #include "class/usbtmc/usbtmc_device.h"
@@ -188,55 +189,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB USBTMC",              // 4: USBTMC
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
-
   size_t chr_count;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }
-  else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    const char* str = string_desc_arr[index];
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) {
-      chr_count = 31;
-    }
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      const char *str = string_desc_arr[index];
+
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t)((((uint16_t)TUSB_DESC_STRING) << 8 ) | (2u*chr_count + 2u));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/video_capture/src/usb_descriptors.c b/examples/device/video_capture/src/usb_descriptors.c
index 9847cf7c5..292d86cd9 100644
--- a/examples/device/video_capture/src/usb_descriptors.c
+++ b/examples/device/video_capture/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -150,52 +151,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB UVC",                 // 4: UVC Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c
index b2593001c..b01fae8e3 100644
--- a/examples/device/webusb_serial/src/usb_descriptors.c
+++ b/examples/device/webusb_serial/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 #include "usb_descriptors.h"
 
@@ -207,53 +208,65 @@ TU_VERIFY_STATIC(sizeof(desc_ms_os_20) == MS_OS_20_DESC_LEN, "Incorrect size");
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456",                      // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB CDC",                 // 4: CDC Interface
   "TinyUSB WebUSB"               // 5: Vendor Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }
diff --git a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
index 63b6bc603..293620042 100644
--- a/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
+++ b/examples/dual/host_hid_to_device_cdc/src/usb_descriptors.c
@@ -23,6 +23,7 @@
  *
  */
 
+#include "bsp/board_api.h"
 #include "tusb.h"
 
 /* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug.
@@ -214,52 +215,64 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index)
 // String Descriptors
 //--------------------------------------------------------------------+
 
+// String Descriptor Index
+enum {
+  STRID_LANGID = 0,
+  STRID_MANUFACTURER,
+  STRID_PRODUCT,
+  STRID_SERIAL,
+};
+
 // array of pointer to string descriptors
-char const* string_desc_arr [] =
+char const *string_desc_arr[] =
 {
   (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409)
   "TinyUSB",                     // 1: Manufacturer
   "TinyUSB Device",              // 2: Product
-  "123456789012",                // 3: Serials, should use chip ID
+  NULL,                          // 3: Serials will use unique ID if possible
   "TinyUSB CDC",                 // 4: CDC Interface
 };
 
-static uint16_t _desc_str[32];
+static uint16_t _desc_str[32 + 1];
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
-uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid)
-{
+uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
   (void) langid;
+  size_t chr_count;
 
-  uint8_t chr_count;
+  switch ( index ) {
+    case STRID_LANGID:
+      memcpy(&_desc_str[1], string_desc_arr[0], 2);
+      chr_count = 1;
+      break;
 
-  if ( index == 0)
-  {
-    memcpy(&_desc_str[1], string_desc_arr[0], 2);
-    chr_count = 1;
-  }else
-  {
-    // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-    // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+    case STRID_SERIAL:
+      chr_count = board_usb_get_serial(_desc_str + 1, 32);
+      break;
 
-    if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL;
+    default:
+      // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+      // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-    const char* str = string_desc_arr[index];
+      if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL;
 
-    // Cap at max char
-    chr_count = (uint8_t) strlen(str);
-    if ( chr_count > 31 ) chr_count = 31;
+      const char *str = string_desc_arr[index];
 
-    // Convert ASCII string into UTF-16
-    for(uint8_t i=0; i<chr_count; i++)
-    {
-      _desc_str[1+i] = str[i];
-    }
+      // Cap at max char
+      chr_count = strlen(str);
+      size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type
+      if ( chr_count > max_count ) chr_count = max_count;
+
+      // Convert ASCII string into UTF-16
+      for ( size_t i = 0; i < chr_count; i++ ) {
+        _desc_str[1 + i] = str[i];
+      }
+      break;
   }
 
   // first byte is length (including header), second byte is string type
-  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8 ) | (2*chr_count + 2));
+  _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2));
 
   return _desc_str;
 }

From 25bace5e81dfba84f84ea12b7723f15fa98a039e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Aug 2023 12:49:26 +0700
Subject: [PATCH 1966/2085] add cmake for all board in stm32f4. fix build, also
 move ci for f4 from makefile to cmake

---
 .github/workflows/build_arm.yml               |   1 -
 .github/workflows/cmake_arm.yml               |   1 +
 .idea/cmake.xml                               |   3 +-
 .../stm32f4/FreeRTOSConfig/FreeRTOSConfig.h   |   2 +-
 .../boards/feather_stm32f405/board.cmake      |  10 ++
 hw/bsp/stm32f4/boards/pyboardv11/board.cmake  |  10 ++
 .../boards/stm32f401blackpill/board.cmake     |  10 ++
 ...07VETX_FLASH.ld => STM32F407VETx_FLASH.ld} |   0
 .../boards/stm32f407blackvet/board.cmake      |   9 +-
 .../stm32f4/boards/stm32f407disco/board.cmake |  10 ++
 .../boards/stm32f411blackpill/board.cmake     |  10 ++
 .../stm32f4/boards/stm32f411disco/board.cmake |  10 ++
 .../stm32f4/boards/stm32f412disco/board.cmake |  10 ++
 .../boards/stm32f412nucleo/board.cmake        |  10 ++
 .../boards/stm32f439nucleo/board.cmake        |  10 ++
 hw/bsp/stm32f4/family.c                       |  86 ++++++-------
 hw/bsp/stm32f4/family.cmake                   | 114 ++++++++----------
 17 files changed, 188 insertions(+), 118 deletions(-)
 create mode 100644 hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake
 create mode 100644 hw/bsp/stm32f4/boards/pyboardv11/board.cmake
 create mode 100644 hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake
 rename hw/bsp/stm32f4/boards/stm32f407blackvet/{STM32F407VETX_FLASH.ld => STM32F407VETx_FLASH.ld} (100%)
 create mode 100644 hw/bsp/stm32f4/boards/stm32f407disco/board.cmake
 create mode 100644 hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake
 create mode 100644 hw/bsp/stm32f4/boards/stm32f411disco/board.cmake
 create mode 100644 hw/bsp/stm32f4/boards/stm32f412disco/board.cmake
 create mode 100644 hw/bsp/stm32f4/boards/stm32f412nucleo/board.cmake
 create mode 100644 hw/bsp/stm32f4/boards/stm32f439nucleo/board.cmake

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 44a5e7363..2621e7372 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -43,7 +43,6 @@ jobs:
         - 'samd51 same5x'
         - 'saml2x'
         - 'stm32f2 stm32f3'
-        - 'stm32f4'
         - 'stm32l0 stm32u5 stm32wb'
         - 'tm4c123 xmc4000'
     steps:
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 5203337ec..8eeae928c 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -42,6 +42,7 @@ jobs:
           - 'rp2040'
           - 'stm32f0'
           - 'stm32f1'
+          - 'stm32f4'
           - 'stm32f7'
           - 'stm32g0'
           - 'stm32g4'
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index b1d024b81..76143ba10 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -22,7 +22,7 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="rp2040" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
+      <configuration PROFILE_NAME="rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=raspberry_pi_pico -DLOG=2" />
       <configuration PROFILE_NAME="feather_rp2040" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pico_sdk -DPICO_BOARD=adafruit_feather_rp2040" />
       <configuration PROFILE_NAME="metro m7 1011" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m7_1011 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="rt1010 evk" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mimxrt1010_evk -DLOG=3 -DLOGGER=RTT" />
@@ -41,6 +41,7 @@
       <configuration PROFILE_NAME="frdm_kl25z" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=frdm_kl25z -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32f072disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f072disco" />
       <configuration PROFILE_NAME="stm32f103_mini_2" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f103_mini_2" />
+      <configuration PROFILE_NAME="stm32f411disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f411disco -DLOG=2 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32f769disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32f769disco -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="stm32h743eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32h743eval -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco" />
diff --git a/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h
index b4a9be477..ed90261d0 100644
--- a/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/stm32f4/FreeRTOSConfig/FreeRTOSConfig.h
@@ -66,7 +66,7 @@
 #define configUSE_MUTEXES                       1
 #define configUSE_RECURSIVE_MUTEXES             1
 #define configUSE_COUNTING_SEMAPHORES           1
-#define configQUEUE_REGISTRY_SIZE               2
+#define configQUEUE_REGISTRY_SIZE               4
 #define configUSE_QUEUE_SETS                    0
 #define configUSE_TIME_SLICING                  0
 #define configUSE_NEWLIB_REENTRANT              0
diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake b/hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake
new file mode 100644
index 000000000..4910d3a88
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f405xx)
+set(JLINK_DEVICE stm32f405rg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F405RGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F405xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.cmake b/hw/bsp/stm32f4/boards/pyboardv11/board.cmake
new file mode 100644
index 000000000..4910d3a88
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/pyboardv11/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f405xx)
+set(JLINK_DEVICE stm32f405rg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F405RGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F405xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake
new file mode 100644
index 000000000..fab6a42d2
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f401xc)
+set(JLINK_DEVICE stm32f401cc)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F401VCTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F405xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETX_FLASH.ld b/hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETx_FLASH.ld
similarity index 100%
rename from hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETX_FLASH.ld
rename to hw/bsp/stm32f4/boards/stm32f407blackvet/STM32F407VETx_FLASH.ld
diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake
index 52cf95700..64626d7bd 100644
--- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake
+++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake
@@ -2,17 +2,12 @@ set(MCU_VARIANT stm32f407xx)
 set(JLINK_DEVICE stm32f407ve)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F407VETx_FLASH.ld)
-set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
-set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     STM32F407xx
     HSE_VALUE=8000000
-    CORE_CM4
-          BOARD_TUD_RHPORT=0
-          BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    BOARD_TUD_RHPORT=0
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
     )
 endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.cmake b/hw/bsp/stm32f4/boards/stm32f407disco/board.cmake
new file mode 100644
index 000000000..c8f0330ed
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f407xx)
+set(JLINK_DEVICE stm32f407vg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F407VGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F407xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake
new file mode 100644
index 000000000..d16db508f
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f411xe)
+set(JLINK_DEVICE stm32f411ce)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F411CEUx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F411xE
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.cmake b/hw/bsp/stm32f4/boards/stm32f411disco/board.cmake
new file mode 100644
index 000000000..d7c32c27d
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f411xe)
+set(JLINK_DEVICE stm32f411ve)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F411VETx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F411xE
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake b/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake
new file mode 100644
index 000000000..805332db8
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f412zx)
+set(JLINK_DEVICE stm32f412zg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F412ZGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F412Zx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.cmake b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.cmake
new file mode 100644
index 000000000..805332db8
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f412zx)
+set(JLINK_DEVICE stm32f412zg)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F412ZGTx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F412Zx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.cmake b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.cmake
new file mode 100644
index 000000000..31ec6f700
--- /dev/null
+++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32f439xx)
+set(JLINK_DEVICE stm32f439zi)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F439ZITX_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32F439xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c
index 41803e0ce..2a599e5c4 100644
--- a/hw/bsp/stm32f4/family.c
+++ b/hw/bsp/stm32f4/family.c
@@ -31,13 +31,11 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
+void OTG_FS_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void OTG_HS_IRQHandler(void)
-{
+void OTG_HS_IRQHandler(void) {
   tud_int_handler(1);
 }
 
@@ -46,8 +44,7 @@ void OTG_HS_IRQHandler(void)
 //--------------------------------------------------------------------+
 UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
+void board_init(void) {
   board_clock_init();
   //SystemCoreClockUpdate();
 
@@ -62,7 +59,7 @@ void board_init(void)
   NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
 #endif
 
-  GPIO_InitTypeDef  GPIO_InitStruct;
+  GPIO_InitTypeDef GPIO_InitStruct;
 
   // LED
   GPIO_InitStruct.Pin = LED_PIN;
@@ -82,22 +79,22 @@ void board_init(void)
 
 #ifdef UART_DEV
   // UART
-  GPIO_InitStruct.Pin       = UART_TX_PIN | UART_RX_PIN;
-  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull      = GPIO_PULLUP;
-  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
+  GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
   GPIO_InitStruct.Alternate = UART_GPIO_AF;
   HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct);
 
-  UartHandle = (UART_HandleTypeDef){
-    .Instance        = UART_DEV,
-    .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
-    .Init.WordLength = UART_WORDLENGTH_8B,
-    .Init.StopBits   = UART_STOPBITS_1,
-    .Init.Parity     = UART_PARITY_NONE,
-    .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
-    .Init.Mode       = UART_MODE_TX_RX,
-    .Init.OverSampling = UART_OVERSAMPLING_16
+  UartHandle = (UART_HandleTypeDef) {
+      .Instance        = UART_DEV,
+      .Init.BaudRate   = CFG_BOARD_UART_BAUDRATE,
+      .Init.WordLength = UART_WORDLENGTH_8B,
+      .Init.StopBits   = UART_STOPBITS_1,
+      .Init.Parity     = UART_PARITY_NONE,
+      .Init.HwFlowCtl  = UART_HWCONTROL_NONE,
+      .Init.Mode       = UART_MODE_TX_RX,
+      .Init.OverSampling = UART_OVERSAMPLING_16
   };
   HAL_UART_Init(&UartHandle);
 #endif
@@ -148,27 +145,37 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON));
   HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  (void) max_len;
+  volatile uint32_t *stm32_uuid = (volatile uint32_t *) UID_BASE;
+  uint32_t *id32 = (uint32_t *) (uintptr_t) id;
+  uint8_t const len = 12;
+
+  id32[0] = stm32_uuid[0];
+  id32[1] = stm32_uuid[1];
+  id32[2] = stm32_uuid[2];
+
+  return len;
+}
+
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
+int board_uart_write(void const *buf, int len) {
 #ifdef UART_DEV
-  HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff);
+  HAL_UART_Transmit(&UartHandle, (uint8_t *) (uintptr_t) buf, len, 0xffff);
   return len;
 #else
   (void) buf; (void) len; (void) UartHandle;
@@ -176,28 +183,25 @@ int board_uart_write(void const * buf, int len)
 #endif
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler (void)
-{
+void HardFault_Handler(void) {
   __asm("BKPT #0\n");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
-
+void _init(void) {
 }
diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake
index a2f36a9e8..cad504bac 100644
--- a/hw/bsp/stm32f4/family.cmake
+++ b/hw/bsp/stm32f4/family.cmake
@@ -20,58 +20,58 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
 set(FAMILY_MCUS STM32F4 CACHE INTERNAL "")
 
-# enable LTO if supported
-include(CheckIPOSupported)
-check_ipo_supported(RESULT IPO_SUPPORTED)
-if (IPO_SUPPORTED)
-  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
-endif ()
-
 
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-      )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-      ${CMSIS_5}/CMSIS/Core/Include
-      ${ST_CMSIS}/Include
-      ${ST_HAL_DRIVER}/Inc
-      )
-    target_compile_options(${BOARD_TARGET} PUBLIC
-      )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      )
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
 
-    update_board(${BOARD_TARGET})
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
 
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_GNU}"
-        -nostartfiles
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  target_compile_options(${BOARD_TARGET} PUBLIC
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
   endif ()
 endfunction()
 
@@ -82,7 +82,6 @@ endfunction()
 function(family_configure_example TARGET RTOS)
   family_configure_common(${TARGET} ${RTOS})
 
-
   # Board target
   add_board_target(board_${BOARD})
 
@@ -102,15 +101,9 @@ function(family_configure_example TARGET RTOS)
 
   # Add TinyUSB target and port source
   family_add_tinyusb(${TARGET} OPT_MCU_STM32F4 ${RTOS})
-  if (MCU_VARIANT STREQUAL "stm32f407xx")
-    target_sources(${TARGET}-tinyusb PUBLIC
-            ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
-            )
-  else()
-    target_sources(${TARGET}-tinyusb PUBLIC
-            ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
-            )
-  endif()
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
   # Link dependencies
@@ -120,16 +113,3 @@ function(family_configure_example TARGET RTOS)
   family_flash_stlink(${TARGET})
   family_flash_jlink(${TARGET})
 endfunction()
-
-
-function(family_configure_device_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_host_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()
-
-function(family_configure_dual_usb_example TARGET)
-  family_configure_example(${TARGET})
-endfunction()

From 56e52037a8c2fe383a61587baece0ce1add33afb Mon Sep 17 00:00:00 2001
From: Aladdin Bakosh <aladdin.bakosh@emerson.com>
Date: Tue, 18 Jul 2023 14:23:41 +0200
Subject: [PATCH 1967/2085] clean(ra_hcd): fix typos in the hcd library

---
 src/portable/renesas/rusb2/hcd_rusb2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 55bf6de4d..790cd6b32 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -265,7 +265,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BCLR_Msk;
+    rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BCLR_Msk;
   }
   rusb->D0FIFOSEL = 0;
   while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
@@ -297,7 +297,7 @@ static bool pipe_xfer_out(rusb2_reg_t* rusb, unsigned num)
     pipe->buf = (uint8_t*)buf + len;
   }
   if (len < mps) {
-    rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+    rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BVAL_Msk;
   }
   rusb->D0FIFOSEL = 0;
   while (rusb->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
@@ -367,7 +367,7 @@ static bool process_pipe_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr,
     } else { /* ZLP */
       rusb->D0FIFOSEL = num;
       pipe_wait_for_ready(rusb, num);
-      rusb->D0FIFOCTR = RUSB2_CFIFOCTR_BVAL_Msk;
+      rusb->D0FIFOCTR = RUSB2_D0FIFOCTR_BVAL_Msk;
       rusb->D0FIFOSEL = 0;
       while (rusb->D0FIFOSEL_b.CURPIPE) {} /* if CURPIPE bits changes, check written value */
     }

From 3c746e8bb0baa85a969228fd15e988425e83b00e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 4 Aug 2023 21:33:44 +0700
Subject: [PATCH 1968/2085] add usb serial for hw l412 test

---
 .github/workflows/build_iar.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 4b170f2bd..454ad12fe 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -93,7 +93,7 @@ jobs:
           echo >> flash.sh 'echo r >> flash.jlink'
           echo >> flash.sh 'echo go >> flash.jlink'
           echo >> flash.sh 'echo exit >> flash.jlink'
-          echo >> flash.sh 'cmdout=$(JLinkExe -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
+          echo >> flash.sh 'cmdout=$(JLinkExe -USB 774470029 -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
           echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
           chmod +x flash.sh
 

From 4f96eebe1bdd37787aa47815b5b9c921884e5a0b Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sun, 6 Aug 2023 13:41:10 +0200
Subject: [PATCH 1969/2085] Fix LPC54 build.

---
 hw/bsp/lpc54/family.mk | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index 7d8bb86cd..b9fcab809 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -7,7 +7,8 @@ CPU_CORE ?= cortex-m4
 CFLAGS += \
   -flto \
   -DCFG_TUSB_MCU=OPT_MCU_LPC54XXX \
-  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))'
+  -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
+  -DBOARD_TUD_RHPORT=$(PORT)
 
 ifeq ($(PORT), 1)
   $(info "PORT1 High Speed")
@@ -32,7 +33,8 @@ SRC_C += \
 	$(MCU_DIR)/drivers/fsl_reset.c \
 	$(SDK_DIR)/drivers/lpc_gpio/fsl_gpio.c \
 	$(SDK_DIR)/drivers/flexcomm/fsl_flexcomm.c \
-	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c
+	$(SDK_DIR)/drivers/flexcomm/fsl_usart.c \
+	$(SDK_DIR)/drivers/common/fsl_common_arm.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \

From 9dd896904c3897515a0fc0bd06bda235d049019c Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sun, 6 Aug 2023 13:41:41 +0200
Subject: [PATCH 1970/2085] WIP.

---
 test/hitl/hitl_test.py | 76 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 test/hitl/hitl_test.py

diff --git a/test/hitl/hitl_test.py b/test/hitl/hitl_test.py
new file mode 100644
index 000000000..7853c9886
--- /dev/null
+++ b/test/hitl/hitl_test.py
@@ -0,0 +1,76 @@
+#
+# The MIT License (MIT)
+#
+# Copyright (c) 2023 HiFiPhile
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+import os
+import sys
+import time
+import serial
+import subprocess
+
+def flash_jlink(sn, dev, firmware):
+    script = ['halt', 'r', f'loadfile {firmware}', 'r', 'go', 'exit']
+    f = open('flash.jlink', 'w')
+    f.writelines(f'{s}\n' for s in script)
+    f.close()
+    ret = subprocess.run(f'JLinkExe -USB {sn} -device {dev} -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink',
+                         shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+    assert ret.returncode == 0, 'Flash failed'
+
+def test_cdc_dual_ports(port1, port2):
+    # Wait device enum
+    timeout = 10
+    while timeout:
+        if os.path.exists(port1) and os.path.exists(port2):
+            break
+        time.sleep(1)
+        timeout = timeout - 1
+
+    assert os.path.exists(port1) and os.path.exists(port2), \
+        'Port not available'
+    
+    ser1 = serial.Serial(port1)
+    ser2 = serial.Serial(port2)
+
+    ser1.timeout = 1
+    ser2.timeout = 1
+
+    str1 = b"test_no1"
+    ser1.write(str1)
+    ser1.flush()
+    assert ser1.read(100) == str1.lower(), 'Port1 wrong data'
+    assert ser2.read(100) == str1.upper(), 'Port2 wrong data'
+
+    str2 = b"test_no2"
+    ser2.write(str2)
+    ser2.flush()
+    assert ser1.read(100) == str2.lower(), 'Port1 wrong data'
+    assert ser2.read(100) == str2.upper(), 'Port2 wrong data'
+
+    print('cdc_dual_ports test done')
+
+
+
+
+flash_jlink('774470029', 'stm32l412kb', 'examples/device/cdc_dual_ports/_build/stm32l412nucleo/cdc_dual_ports.elf')
+
+test_cdc_dual_ports('/dev/ttyUSB_57323020.00', '/dev/ttyUSB_57323020.02')
\ No newline at end of file

From b173c71ffcc0133779ce4e42a5e08b5ab74382a0 Mon Sep 17 00:00:00 2001
From: kkitayam <45088311+kkitayam@users.noreply.github.com>
Date: Sun, 6 Aug 2023 22:49:45 +0900
Subject: [PATCH 1971/2085] Change to subst to work on windows command prompt

---
 examples/make.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/make.mk b/examples/make.mk
index 4773189df..a590e34f7 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -116,7 +116,7 @@ INC += \
   $(TOP)/$(FAMILY_PATH) \
   $(TOP)/src \
 
-BOARD_UPPER = $(shell echo $(subst -,_,$(BOARD)) | tr a-z A-Z)
+BOARD_UPPER = $(subst a,A,$(subst b,B,$(subst c,C,$(subst d,D,$(subst e,E,$(subst f,F,$(subst g,G,$(subst h,H,$(subst i,I,$(subst j,J,$(subst k,K,$(subst l,L,$(subst m,M,$(subst n,N,$(subst o,O,$(subst p,P,$(subst q,Q,$(subst r,R,$(subst s,S,$(subst t,T,$(subst u,U,$(subst v,V,$(subst w,W,$(subst x,X,$(subst y,Y,$(subst z,Z,$(subst -,_,$(BOARD))))))))))))))))))))))))))))
 CFLAGS += -DBOARD_$(BOARD_UPPER)
 
 # Log level is mapped to TUSB DEBUG option

From b9e614bd39b994a8b83ab09483635a67ae7f1d44 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sun, 6 Aug 2023 15:59:25 +0200
Subject: [PATCH 1972/2085] Fix LPC54 build.

---
 hw/bsp/lpc54/boards/lpcxpresso54628/board.mk |   2 +-
 hw/bsp/lpc54/family.mk                       |   3 +-
 test/hitl/hitl_config.json                   |  28 +++++
 test/hitl/hitl_test.py                       | 121 ++++++++++++++++++-
 4 files changed, 145 insertions(+), 9 deletions(-)
 create mode 100644 test/hitl/hitl_config.json

diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk b/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
index 5f15e2bbe..e0b382aeb 100644
--- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
+++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.mk
@@ -1,7 +1,7 @@
 MCU_VARIANT = LPC54628
 MCU_CORE = LPC54628
 
-PORT ?= 0
+PORT ?= 1
 
 CFLAGS += -DCPU_LPC54628J512ET180
 CFLAGS += -Wno-error=double-promotion
diff --git a/hw/bsp/lpc54/family.mk b/hw/bsp/lpc54/family.mk
index b9fcab809..46a5f7930 100644
--- a/hw/bsp/lpc54/family.mk
+++ b/hw/bsp/lpc54/family.mk
@@ -8,12 +8,11 @@ CFLAGS += \
   -flto \
   -DCFG_TUSB_MCU=OPT_MCU_LPC54XXX \
   -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' \
-  -DBOARD_TUD_RHPORT=$(PORT)
 
 ifeq ($(PORT), 1)
   $(info "PORT1 High Speed")
   CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-
+  CFLAGS += -DBOARD_TUD_RHPORT=1
   # LPC55 Highspeed Port1 can only write to USB_SRAM region
   CFLAGS += -DCFG_TUSB_MEM_SECTION='__attribute__((section("m_usb_global")))'
 else
diff --git a/test/hitl/hitl_config.json b/test/hitl/hitl_config.json
new file mode 100644
index 000000000..f57629a52
--- /dev/null
+++ b/test/hitl/hitl_config.json
@@ -0,0 +1,28 @@
+{
+    "devices": [
+        {
+            "uid": "41003B000E504E5457323020",
+            "debugger": "jlink",
+            "debugger_sn": "774470029",
+            "device": "stm32l412kb",
+            "tests": [
+                {
+                    "name": "cdc_dual_ports",
+                    "firmware": "examples/device/cdc_dual_ports/_build/stm32l412nucleo/cdc_dual_ports.elf"
+                },
+                {
+                    "name": "cdc_msc",
+                    "firmware": "examples/device/cdc_msc/_build/stm32l412nucleo/cdc_msc.elf"
+                },
+                {
+                    "name": "dfu",
+                    "firmware": "examples/device/dfu/_build/stm32l412nucleo/dfu.elf"
+                },
+                {
+                    "name": "dfu_runtime",
+                    "firmware": "examples/device/dfu_runtime/_build/stm32l412nucleo/dfu_runtime.elf"
+                }
+            ]
+        }
+    ]
+}
\ No newline at end of file
diff --git a/test/hitl/hitl_test.py b/test/hitl/hitl_test.py
index 7853c9886..d51a13ce3 100644
--- a/test/hitl/hitl_test.py
+++ b/test/hitl/hitl_test.py
@@ -21,11 +21,16 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 # THE SOFTWARE.
 
+# udev rules :
+# SUBSYSTEM=="block", SUBSYSTEMS=="usb", MODE="0666", PROGRAM="/bin/sh -c 'echo $$ID_SERIAL_SHORT | rev | cut -c -8 | rev'", SYMLINK+="blkUSB_%c.%s{bInterfaceNumber}"
+# SUBSYSTEM=="tty", SUBSYSTEMS=="usb", MODE="0666", PROGRAM="/bin/sh -c 'echo $$ID_SERIAL_SHORT | rev | cut -c -8 | rev'", SYMLINK+="ttyUSB_%c.%s{bInterfaceNumber}"
+
 import os
 import sys
 import time
 import serial
 import subprocess
+import json
 
 def flash_jlink(sn, dev, firmware):
     script = ['halt', 'r', f'loadfile {firmware}', 'r', 'go', 'exit']
@@ -34,9 +39,12 @@ def flash_jlink(sn, dev, firmware):
     f.close()
     ret = subprocess.run(f'JLinkExe -USB {sn} -device {dev} -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink',
                          shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+    os.remove('flash.jlink') 
     assert ret.returncode == 0, 'Flash failed'
 
-def test_cdc_dual_ports(port1, port2):
+def test_cdc_dual_ports(id):
+    port1 = f'/dev/ttyUSB_{id[-8:]}.00'
+    port2 = f'/dev/ttyUSB_{id[-8:]}.02'
     # Wait device enum
     timeout = 10
     while timeout:
@@ -46,8 +54,9 @@ def test_cdc_dual_ports(port1, port2):
         timeout = timeout - 1
 
     assert os.path.exists(port1) and os.path.exists(port2), \
-        'Port not available'
+        'Device not available'
     
+    # Echo test
     ser1 = serial.Serial(port1)
     ser2 = serial.Serial(port2)
 
@@ -68,9 +77,109 @@ def test_cdc_dual_ports(port1, port2):
 
     print('cdc_dual_ports test done')
 
+def test_cdc_msc(id):
+    port  = f'/dev/ttyUSB_{id[-8:]}.00'
+    block = f'/dev/blkUSB_{id[-8:]}.02'
+    # Wait device enum
+    timeout = 10
+    while timeout:
+        if os.path.exists(port) and os.path.exists(block):
+            break
+        time.sleep(1)
+        timeout = timeout - 1
+
+    assert os.path.exists(port) and os.path.exists(block), \
+        'Device not available'
+    
+    # Echo test
+    ser = serial.Serial(port)
+
+    ser.timeout = 1
+
+    str = b"test_str"
+    ser.write(str)
+    ser.flush()
+    assert ser.read(100) == str, 'Port wrong data'
+
+    # Block test
+    f = open(block, 'rb')
+    data = f.read()
+
+    readme = \
+    b"This is tinyusb's MassStorage Class demo.\r\n\r\n\
+If you find any bugs or get any questions, feel free to file an\r\n\
+issue at github.com/hathach/tinyusb"
+
+    assert data[0x600:0x600 + len(readme)] == readme, 'Block wrong data'
+    print('cdc_msc test done')
+
+def test_dfu(id):
+    # Wait device enum
+    timeout = 10
+    while timeout:
+        ret = subprocess.run(f'dfu-util -l',
+                         shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        stdout = ret.stdout.decode()
+        if f'serial="{id}"' in stdout and 'Found DFU: [cafe:4000]' in stdout:
+            break
+        time.sleep(1)
+        timeout = timeout - 1
+    
+    assert timeout, 'Device not available'
+    
+    # Test upload
+    try:
+        os.remove('dfu0') 
+        os.remove('dfu1')
+    except OSError:
+        pass
+
+    ret = subprocess.run(f'dfu-util -S {id} -a 0 -U dfu0',
+                         shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+    assert ret.returncode == 0, 'Upload failed'
+
+    ret = subprocess.run(f'dfu-util -S {id} -a 1 -U dfu1',
+                         shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+    assert ret.returncode == 0, 'Upload failed'
+
+    with open('dfu0') as f:
+        assert 'Hello world from TinyUSB DFU! - Partition 0' in f.read(),  'Wrong uploaded data'
+
+    with open('dfu1') as f:
+        assert 'Hello world from TinyUSB DFU! - Partition 1' in f.read(),  'Wrong uploaded data'
+
+    os.remove('dfu0') 
+    os.remove('dfu1')
+
+    print('dfu test done')
+
+def test_dfu_runtime(id):
+     # Wait device enum
+    timeout = 10
+    while timeout:
+        ret = subprocess.run(f'dfu-util -l',
+                         shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        stdout = ret.stdout.decode()
+        if f'serial="{id}"' in stdout and 'Found Runtime: [cafe:4000]' in stdout:
+            break
+        time.sleep(1)
+        timeout = timeout - 1
+    
+    assert timeout, 'Device not available'
+
+    print('dfu_runtime test done')
 
 
-
-flash_jlink('774470029', 'stm32l412kb', 'examples/device/cdc_dual_ports/_build/stm32l412nucleo/cdc_dual_ports.elf')
-
-test_cdc_dual_ports('/dev/ttyUSB_57323020.00', '/dev/ttyUSB_57323020.02')
\ No newline at end of file
+if __name__ == '__main__':
+    with open(f'{os.path.dirname(__file__)}/hitl_config.json') as f:
+        config = json.load(f)
+    
+    for device in config['devices']:
+        print(f"Testing device:{device['device']}")
+        for test in device['tests']:
+            if device['debugger'] == 'jlink':
+                flash_jlink(device['debugger_sn'], device['device'], test['firmware'])
+            else:
+                # ToDo
+                pass
+            locals()[f'test_{test["name"]}'](device['uid'])

From 4d1f3f4e9dbe97060d41c188573fe94057ea1428 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sun, 6 Aug 2023 16:30:19 +0200
Subject: [PATCH 1973/2085] Add more MCU.

---
 test/hitl/hitl_config.json | 52 ++++++++++++++++++++++++++++++++++++--
 test/hitl/hitl_test.py     | 35 ++++++++++++-------------
 2 files changed, 68 insertions(+), 19 deletions(-)

diff --git a/test/hitl/hitl_config.json b/test/hitl/hitl_config.json
index f57629a52..297ae8b81 100644
--- a/test/hitl/hitl_config.json
+++ b/test/hitl/hitl_config.json
@@ -4,7 +4,7 @@
             "uid": "41003B000E504E5457323020",
             "debugger": "jlink",
             "debugger_sn": "774470029",
-            "device": "stm32l412kb",
+            "device": "STM32L412KB",
             "tests": [
                 {
                     "name": "cdc_dual_ports",
@@ -23,6 +23,54 @@
                     "firmware": "examples/device/dfu_runtime/_build/stm32l412nucleo/dfu_runtime.elf"
                 }
             ]
+        },
+        {
+            "uid": "210041000C51343237303334",
+            "debugger": "jlink",
+            "debugger_sn": "770935966",
+            "device": "STM32F746NG",
+            "tests": [
+                {
+                    "name": "cdc_dual_ports",
+                    "firmware": "examples/device/cdc_dual_ports/_build/stm32f746disco/cdc_dual_ports.elf"
+                },
+                {
+                    "name": "cdc_msc",
+                    "firmware": "examples/device/cdc_msc/_build/stm32f746disco/cdc_msc.elf"
+                },
+                {
+                    "name": "dfu",
+                    "firmware": "examples/device/dfu/_build/stm32f746disco/dfu.elf"
+                },
+                {
+                    "name": "dfu_runtime",
+                    "firmware": "examples/device/dfu_runtime/_build/stm32f746disco/dfu_runtime.elf"
+                }
+            ]
+        },
+        {
+            "uid": "0123456789ABCDEF",
+            "debugger": "jlink",
+            "debugger_sn": "727600775",
+            "device": "LPC54608J512",
+            "tests": [
+                {
+                    "name": "cdc_dual_ports",
+                    "firmware": "examples/device/cdc_dual_ports/_build/lpcxpresso54628/cdc_dual_ports.elf"
+                },
+                {
+                    "name": "cdc_msc",
+                    "firmware": "examples/device/cdc_msc/_build/lpcxpresso54628/cdc_msc.elf"
+                },
+                {
+                    "name": "dfu",
+                    "firmware": "examples/device/dfu/_build/lpcxpresso54628/dfu.elf"
+                },
+                {
+                    "name": "dfu_runtime",
+                    "firmware": "examples/device/dfu_runtime/_build/lpcxpresso54628/dfu_runtime.elf"
+                }
+            ]
         }
     ]
-}
\ No newline at end of file
+}
diff --git a/test/hitl/hitl_test.py b/test/hitl/hitl_test.py
index d51a13ce3..60eda57ef 100644
--- a/test/hitl/hitl_test.py
+++ b/test/hitl/hitl_test.py
@@ -39,8 +39,9 @@ def flash_jlink(sn, dev, firmware):
     f.close()
     ret = subprocess.run(f'JLinkExe -USB {sn} -device {dev} -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink',
                          shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-    os.remove('flash.jlink') 
-    assert ret.returncode == 0, 'Flash failed'
+    stdout = ret.stdout.decode()
+    os.remove('flash.jlink')
+    assert ret.returncode == 0, 'Flash failed\n' + stdout
 
 def test_cdc_dual_ports(id):
     port1 = f'/dev/ttyUSB_{id[-8:]}.00'
@@ -55,7 +56,7 @@ def test_cdc_dual_ports(id):
 
     assert os.path.exists(port1) and os.path.exists(port2), \
         'Device not available'
-    
+
     # Echo test
     ser1 = serial.Serial(port1)
     ser2 = serial.Serial(port2)
@@ -90,16 +91,16 @@ def test_cdc_msc(id):
 
     assert os.path.exists(port) and os.path.exists(block), \
         'Device not available'
-    
-    # Echo test
-    ser = serial.Serial(port)
 
-    ser.timeout = 1
+    # Echo test
+    ser1 = serial.Serial(port)
+
+    ser1.timeout = 1
 
     str = b"test_str"
-    ser.write(str)
-    ser.flush()
-    assert ser.read(100) == str, 'Port wrong data'
+    ser1.write(str)
+    ser1.flush()
+    assert ser1.read(100) == str, 'Port wrong data'
 
     # Block test
     f = open(block, 'rb')
@@ -124,12 +125,12 @@ def test_dfu(id):
             break
         time.sleep(1)
         timeout = timeout - 1
-    
+
     assert timeout, 'Device not available'
-    
+
     # Test upload
     try:
-        os.remove('dfu0') 
+        os.remove('dfu0')
         os.remove('dfu1')
     except OSError:
         pass
@@ -148,7 +149,7 @@ def test_dfu(id):
     with open('dfu1') as f:
         assert 'Hello world from TinyUSB DFU! - Partition 1' in f.read(),  'Wrong uploaded data'
 
-    os.remove('dfu0') 
+    os.remove('dfu0')
     os.remove('dfu1')
 
     print('dfu test done')
@@ -164,7 +165,7 @@ def test_dfu_runtime(id):
             break
         time.sleep(1)
         timeout = timeout - 1
-    
+
     assert timeout, 'Device not available'
 
     print('dfu_runtime test done')
@@ -173,11 +174,11 @@ def test_dfu_runtime(id):
 if __name__ == '__main__':
     with open(f'{os.path.dirname(__file__)}/hitl_config.json') as f:
         config = json.load(f)
-    
+
     for device in config['devices']:
         print(f"Testing device:{device['device']}")
         for test in device['tests']:
-            if device['debugger'] == 'jlink':
+            if device['debugger'].lower() == 'jlink':
                 flash_jlink(device['debugger_sn'], device['device'], test['firmware'])
             else:
                 # ToDo

From c940a2f36247fb05364e9c56fed6daf95071e8e1 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sun, 6 Aug 2023 21:55:24 +0200
Subject: [PATCH 1974/2085] Fix RTT build.

---
 lib/SEGGER_RTT/RTT/SEGGER_RTT.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
index 730a5cfb3..811d951fd 100644
--- a/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
+++ b/lib/SEGGER_RTT/RTT/SEGGER_RTT.c
@@ -183,6 +183,11 @@ Additional information:
 *
 **********************************************************************
 */
+#ifdef __GNUC__
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#pragma GCC diagnostic ignored "-Wcast-align"
+#endif
+
 #if (defined __ICCARM__) || (defined __ICCRX__)
   #define RTT_PRAGMA(P) _Pragma(#P)
 #endif

From 87150b77702d93527e2998c62371ef2d7d2b9860 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sun, 6 Aug 2023 22:02:15 +0200
Subject: [PATCH 1975/2085] Add config file as argument.

---
 test/hitl/{hitl_config.json => hitl_hfp.json} | 0
 test/hitl/hitl_test.py                        | 7 ++++++-
 2 files changed, 6 insertions(+), 1 deletion(-)
 rename test/hitl/{hitl_config.json => hitl_hfp.json} (100%)

diff --git a/test/hitl/hitl_config.json b/test/hitl/hitl_hfp.json
similarity index 100%
rename from test/hitl/hitl_config.json
rename to test/hitl/hitl_hfp.json
diff --git a/test/hitl/hitl_test.py b/test/hitl/hitl_test.py
index 60eda57ef..6c8066add 100644
--- a/test/hitl/hitl_test.py
+++ b/test/hitl/hitl_test.py
@@ -172,7 +172,12 @@ def test_dfu_runtime(id):
 
 
 if __name__ == '__main__':
-    with open(f'{os.path.dirname(__file__)}/hitl_config.json') as f:
+    if len(sys.argv) != 2:
+        print('Usage:')
+        print('python hitl_test.py config.json')
+        sys.exit(-1)
+
+    with open(f'{os.path.dirname(__file__)}/{sys.argv[1]}') as f:
         config = json.load(f)
 
     for device in config['devices']:

From 45af3d6a83f89d3b048701f8d6d7de15ebfa0101 Mon Sep 17 00:00:00 2001
From: Rocky04 <rockerfaeller04@gmx.de>
Date: Mon, 7 Aug 2023 12:04:22 +0000
Subject: [PATCH 1976/2085] Update examples

---
 examples/device/audio_4_channel_mic/src/main.c    | 2 +-
 examples/device/audio_test/src/main.c             | 2 +-
 examples/device/audio_test_multi_rate/src/main.c  | 2 +-
 examples/device/cdc_msc/src/main.c                | 2 +-
 examples/device/cdc_msc_freertos/src/main.c       | 9 ++++++++-
 examples/device/dfu/src/main.c                    | 2 +-
 examples/device/dfu_runtime/src/main.c            | 2 +-
 examples/device/dynamic_configuration/src/main.c  | 2 +-
 examples/device/hid_boot_interface/src/main.c     | 2 +-
 examples/device/hid_composite/src/main.c          | 2 +-
 examples/device/hid_composite_freertos/src/main.c | 9 ++++++++-
 examples/device/hid_generic_inout/src/main.c      | 2 +-
 examples/device/hid_multiple_interface/src/main.c | 2 +-
 examples/device/midi_test/src/main.c              | 2 +-
 examples/device/msc_dual_lun/src/main.c           | 2 +-
 examples/device/uac2_headset/src/main.c           | 2 +-
 examples/device/usbtmc/src/main.c                 | 2 +-
 examples/device/video_capture/src/main.c          | 2 +-
 examples/device/webusb_serial/src/main.c          | 2 +-
 examples/dual/host_hid_to_device_cdc/src/main.c   | 2 +-
 20 files changed, 34 insertions(+), 20 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 2b9c5143d..7bd69f55c 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -129,7 +129,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c
index b5ca41d36..3347890ca 100644
--- a/examples/device/audio_test/src/main.c
+++ b/examples/device/audio_test/src/main.c
@@ -130,7 +130,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c
index 078e783eb..2c2320a96 100644
--- a/examples/device/audio_test_multi_rate/src/main.c
+++ b/examples/device/audio_test_multi_rate/src/main.c
@@ -142,7 +142,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c
index 6dad73cbf..711ad4df7 100644
--- a/examples/device/cdc_msc/src/main.c
+++ b/examples/device/cdc_msc/src/main.c
@@ -95,7 +95,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 0e8a24d02..457c88d70 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -175,7 +175,14 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+  if (tud_mounted())
+  {
+    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+  }
+  else
+  {
+    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
+  }
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c
index 5f37f25e1..caeed89e9 100644
--- a/examples/device/dfu/src/main.c
+++ b/examples/device/dfu/src/main.c
@@ -112,7 +112,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c
index 4ec3cb188..57f14ef62 100644
--- a/examples/device/dfu_runtime/src/main.c
+++ b/examples/device/dfu_runtime/src/main.c
@@ -107,7 +107,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 // Invoked on DFU_DETACH request to reboot to the bootloader
diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c
index 578f01d8c..5d523c7b1 100644
--- a/examples/device/dynamic_configuration/src/main.c
+++ b/examples/device/dynamic_configuration/src/main.c
@@ -96,7 +96,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 
diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c
index 1a155996a..09e5fc7ee 100644
--- a/examples/device/hid_boot_interface/src/main.c
+++ b/examples/device/hid_boot_interface/src/main.c
@@ -98,7 +98,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c
index 8d0e6bece..00f00ae95 100644
--- a/examples/device/hid_composite/src/main.c
+++ b/examples/device/hid_composite/src/main.c
@@ -97,7 +97,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index ca02af100..4ed506f6c 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -176,7 +176,14 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+  if (tud_mounted())
+  {
+    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
+  }
+  else
+  {
+    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0);
+  }
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c
index 5db8f5581..7afe1c896 100644
--- a/examples/device/hid_generic_inout/src/main.c
+++ b/examples/device/hid_generic_inout/src/main.c
@@ -118,7 +118,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c
index 72240b208..deca575a3 100644
--- a/examples/device/hid_multiple_interface/src/main.c
+++ b/examples/device/hid_multiple_interface/src/main.c
@@ -101,7 +101,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c
index 2c3e9d954..2898fbc3b 100644
--- a/examples/device/midi_test/src/main.c
+++ b/examples/device/midi_test/src/main.c
@@ -101,7 +101,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c
index c7f6de7bf..0a532788e 100644
--- a/examples/device/msc_dual_lun/src/main.c
+++ b/examples/device/msc_dual_lun/src/main.c
@@ -92,7 +92,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c
index 19a3f7bae..ff952333b 100644
--- a/examples/device/uac2_headset/src/main.c
+++ b/examples/device/uac2_headset/src/main.c
@@ -143,7 +143,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 // Helper for clock get requests
diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c
index 2bba336f1..1a5c1df20 100644
--- a/examples/device/usbtmc/src/main.c
+++ b/examples/device/usbtmc/src/main.c
@@ -93,7 +93,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c
index 5654e0b61..c7bf9b936 100644
--- a/examples/device/video_capture/src/main.c
+++ b/examples/device/video_capture/src/main.c
@@ -96,7 +96,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 
diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c
index eaca78c73..a5164cd07 100644
--- a/examples/device/webusb_serial/src/main.c
+++ b/examples/device/webusb_serial/src/main.c
@@ -156,7 +156,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 //--------------------------------------------------------------------+
diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c
index 817c63c70..d4172580f 100644
--- a/examples/dual/host_hid_to_device_cdc/src/main.c
+++ b/examples/dual/host_hid_to_device_cdc/src/main.c
@@ -121,7 +121,7 @@ void tud_suspend_cb(bool remote_wakeup_en)
 // Invoked when usb bus is resumed
 void tud_resume_cb(void)
 {
-  blink_interval_ms = BLINK_MOUNTED;
+  blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
 }
 
 // Invoked when CDC interface received data from host

From 1f95a417f271e627ec981be3d211eed8c37cb052 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Aug 2023 18:22:28 +0700
Subject: [PATCH 1977/2085] Add tuh_rhport_is_active() and
 tuh_rhport_reset_bus()

- also improve ehci bus reset
- seperate bus reset delay and contact debouncing delay in enumeration
---
 src/host/hcd.h                          |   5 +-
 src/host/hub.c                          |   2 +-
 src/host/usbh.c                         | 118 +++++++++++++-----------
 src/host/usbh.h                         |  39 ++++----
 src/portable/chipidea/ci_hs/hcd_ci_hs.c |  43 ++++-----
 src/portable/ehci/ehci.c                |  24 +++--
 6 files changed, 128 insertions(+), 103 deletions(-)

diff --git a/src/host/hcd.h b/src/host/hcd.h
index d77dd6e2f..9bcc1c6df 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -149,10 +149,11 @@ uint32_t hcd_frame_number(uint8_t rhport);
 // Get the current connect status of roothub port
 bool hcd_port_connect_status(uint8_t rhport);
 
-// Reset USB bus on the port
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
 void hcd_port_reset(uint8_t rhport);
 
-// TODO implement later
+// Complete bus reset sequence, may be required by some controllers
 void hcd_port_reset_end(uint8_t rhport);
 
 // Get port link speed
diff --git a/src/host/hub.c b/src/host/hub.c
index 16dd534d2..ec30eb96a 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -330,7 +330,7 @@ static void connection_port_reset_complete (tuh_xfer_t* xfer);
 bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports
   (void) ep_addr;
-  TU_ASSERT(result == XFER_RESULT_SUCCESS);
+  TU_VERIFY(result == XFER_RESULT_SUCCESS);
 
   hub_interface_t* p_hub = get_itf(dev_addr);
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 49f8c78f1..cc7e38b45 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -181,9 +181,6 @@ static usbh_class_driver_t const usbh_class_drivers[] =
 };
 
 enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
-
-enum { RESET_DELAY = 500 };  // 200 USB specs say only 50ms but many devices require much longer
-
 enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
 
@@ -251,40 +248,27 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
-TU_ATTR_WEAK void osal_task_delay(uint32_t msec)
-{
+// weak and overridable
+TU_ATTR_WEAK void osal_task_delay(uint32_t msec) {
   const uint32_t start = hcd_frame_number(_usbh_controller);
   while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {}
 }
 #endif
 
 //--------------------------------------------------------------------+
-// PUBLIC API (Parameter Verification is required)
+// Device API
 //--------------------------------------------------------------------+
 
-bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param)
-{
-  if (hcd_configure)
-  {
-    return hcd_configure(rhport, cfg_id, cfg_param);
-  }else
-  {
-    return false;
-  }
-}
-
-bool tuh_mounted(uint8_t dev_addr)
-{
-  usbh_device_t* dev = get_device(dev_addr);
+bool tuh_mounted(uint8_t dev_addr) {
+  usbh_device_t *dev = get_device(dev_addr);
   TU_VERIFY(dev);
   return dev->configured;
 }
 
-bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
-{
+bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) {
   *vid = *pid = 0;
 
-  usbh_device_t const* dev = get_device(dev_addr);
+  usbh_device_t const *dev = get_device(dev_addr);
   TU_VERIFY(dev && dev->addressed && dev->vid != 0);
 
   *vid = dev->vid;
@@ -293,26 +277,48 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
   return true;
 }
 
-tusb_speed_t tuh_speed_get (uint8_t dev_addr)
-{
-  usbh_device_t* dev = get_device(dev_addr);
+tusb_speed_t tuh_speed_get(uint8_t dev_addr) {
+  usbh_device_t *dev = get_device(dev_addr);
   return (tusb_speed_t) (dev ? get_device(dev_addr)->speed : _dev0.speed);
 }
 
-static void clear_device(usbh_device_t* dev)
-{
+bool tuh_rhport_is_active(uint8_t rhport) {
+  return _usbh_controller == rhport;
+}
+
+bool tuh_rhport_reset_bus(uint8_t rhport, bool active) {
+  TU_VERIFY(tuh_rhport_is_active(rhport));
+  if ( active ) {
+    hcd_port_reset(rhport);
+  } else {
+    hcd_port_reset_end(rhport);
+  }
+  return true;
+}
+
+//--------------------------------------------------------------------+
+// PUBLIC API (Parameter Verification is required)
+//--------------------------------------------------------------------+
+
+bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) {
+  if ( hcd_configure ) {
+    return hcd_configure(rhport, cfg_id, cfg_param);
+  } else {
+    return false;
+  }
+}
+
+static void clear_device(usbh_device_t* dev) {
   tu_memclr(dev, sizeof(usbh_device_t));
   memset(dev->itf2drv, TUSB_INDEX_INVALID_8, sizeof(dev->itf2drv)); // invalid mapping
   memset(dev->ep2drv , TUSB_INDEX_INVALID_8, sizeof(dev->ep2drv )); // invalid mapping
 }
 
-bool tuh_inited(void)
-{
+bool tuh_inited(void) {
   return _usbh_controller != TUSB_INDEX_INVALID_8;
 }
 
-bool tuh_init(uint8_t controller_id)
-{
+bool tuh_init(uint8_t controller_id) {
   // skip if already initialized
   if ( tuh_inited() ) return true;
 
@@ -359,8 +365,7 @@ bool tuh_init(uint8_t controller_id)
   return true;
 }
 
-bool tuh_task_event_ready(void)
-{
+bool tuh_task_event_ready(void) {
   // Skip if stack is not initialized
   if ( !tuh_inited() ) return false;
 
@@ -385,8 +390,7 @@ bool tuh_task_event_ready(void)
     }
     @endcode
  */
-void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
-{
+void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
   (void) in_isr; // not implemented yet
 
   // Skip if stack is not initialized
@@ -403,8 +407,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
       case HCD_EVENT_DEVICE_ATTACH:
         // due to the shared _usbh_ctrl_buf, we must complete enumerating
         // one device before enumerating another one.
-        if ( _dev0.enumerating )
-        {
+        if ( _dev0.enumerating ) {
           TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport);
 
           bool is_empty = osal_queue_empty(_usbh_q);
@@ -414,8 +417,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
             // Exit if this is the only event in the queue, otherwise we may loop forever
             return;
           }
-        }else
-        {
+        }else {
           TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport);
           _dev0.enumerating = 1;
           enum_new_device(&event);
@@ -428,8 +430,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr)
 
         #if CFG_TUH_HUB
         // TODO remove
-        if ( event.connection.hub_addr != 0)
-        {
+        if ( event.connection.hub_addr != 0) {
           // done with hub, waiting for next data on status pipe
           (void) hub_edpt_status_xfer( event.connection.hub_addr );
         }
@@ -1230,6 +1231,12 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
 // one device before enumerating another one.
 //--------------------------------------------------------------------+
 
+enum {
+  ENUM_RESET_DELAY = 50, // USB specs: 10 to 50ms
+  ENUM_CONTACT_DEBOUNCING_DELAY = 450, // when plug/unplug a device, physical connection can be bouncing and may
+                                       // generate a series of attach/detach event. This delay wait for stable connection
+};
+
 enum {
   ENUM_IDLE,
   ENUM_RESET_1,         // 1st reset when attached
@@ -1311,7 +1318,7 @@ static void process_enumeration(tuh_xfer_t* xfer)
     break;
 
     case ENUM_HUB_GET_STATUS_2:
-      osal_task_delay(RESET_DELAY);
+      osal_task_delay(ENUM_RESET_DELAY);
       TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_2), );
     break;
 
@@ -1468,12 +1475,14 @@ static bool enum_new_device(hcd_event_t* event)
   if (_dev0.hub_addr == 0)
   {
     // connected/disconnected directly with roothub
-    // wait until device is stable TODO non blocking
     hcd_port_reset(_dev0.rhport);
-    osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
-                                  // sof of controller may not running while resetting
+    osal_task_delay(ENUM_RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since
+                                        // sof of controller may not running while resetting
     hcd_port_reset_end( _dev0.rhport);
 
+    // wait until device connection is stable TODO non blocking
+    osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY);
+
     // device unplugged while delaying
     if ( !hcd_port_connect_status(_dev0.rhport) ) {
       enum_full_complete();
@@ -1489,6 +1498,7 @@ static bool enum_new_device(hcd_event_t* event)
     xfer.result    = XFER_RESULT_SUCCESS;
     xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
 
+
     process_enumeration(&xfer);
 
   }
@@ -1496,8 +1506,8 @@ static bool enum_new_device(hcd_event_t* event)
   else
   {
     // connected/disconnected via external hub
-    // wait until device is stable
-    osal_task_delay(RESET_DELAY);
+    // wait until device connection is stable TODO non blocking
+    osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY);
 
     // ENUM_HUB_GET_STATUS
     //TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete, 0) );
@@ -1508,23 +1518,19 @@ static bool enum_new_device(hcd_event_t* event)
   return true;
 }
 
-static uint8_t get_new_address(bool is_hub)
-{
+static uint8_t get_new_address(bool is_hub) {
   uint8_t start;
   uint8_t end;
 
-  if ( is_hub )
-  {
+  if ( is_hub ) {
     start = CFG_TUH_DEVICE_MAX;
     end   = start + CFG_TUH_HUB;
-  }else
-  {
+  }else {
     start = 0;
     end   = start + CFG_TUH_DEVICE_MAX;
   }
 
-  for (uint8_t idx = start; idx < end; idx++)
-  {
+  for (uint8_t idx = start; idx < end; idx++) {
     if (!_usbh_devices[idx].connected) return (idx+1);
   }
 
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 0d56f40c9..684e8240e 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -47,8 +47,7 @@ typedef void (*tuh_xfer_cb_t)(tuh_xfer_t* xfer);
 // it is advised to initialize it using member name
 // Note2: not all field is available/meaningful in callback,
 // some info is not saved by usbh to save SRAM
-struct tuh_xfer_s
-{
+struct tuh_xfer_s {
   uint8_t daddr;
   uint8_t ep_addr;
   uint8_t TU_RESERVED;      // reserved
@@ -56,8 +55,7 @@ struct tuh_xfer_s
 
   uint32_t actual_len;      // excluding setup packet
 
-  union
-  {
+  union {
     tusb_control_request_t const* setup; // setup packet pointer if control transfer
     uint32_t buflen;                     // expected length if not control transfer (not available in callback)
   };
@@ -70,15 +68,13 @@ struct tuh_xfer_s
 };
 
 // Subject to change
-typedef struct
-{
+typedef struct {
   uint8_t daddr;
   tusb_desc_interface_t desc;
 } tuh_itf_info_t;
 
 // ConfigID for tuh_config()
-enum
-{
+enum {
   TUH_CFGID_RPI_PIO_USB_CONFIGURATION = OPT_MCU_RP2040 << 8 // cfg_param: pio_usb_configuration_t
 };
 
@@ -105,12 +101,12 @@ TU_ATTR_WEAK void tuh_umount_cb(uint8_t daddr);
 // Should be called before tuh_init()
 // - cfg_id   : configure ID (TBD)
 // - cfg_param: configure data, structure depends on the ID
-bool tuh_configure(uint8_t controller_id, uint32_t cfg_id, const void* cfg_param);
+bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param);
 
 // Init host stack
-bool tuh_init(uint8_t controller_id);
+bool tuh_init(uint8_t rhport);
 
-// Check if host stack is already initialized
+// Check if host stack is already initialized with any roothub ports
 bool tuh_inited(void);
 
 // Task function should be called in main/rtos loop, extended version of tuh_task()
@@ -120,8 +116,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr);
 
 // Task function should be called in main/rtos loop
 TU_ATTR_ALWAYS_INLINE static inline
-void tuh_task(void)
-{
+void tuh_task(void) {
   tuh_task_ext(UINT32_MAX, false);
 }
 
@@ -135,8 +130,20 @@ extern void hcd_int_handler(uint8_t rhport);
 // Interrupt handler, name alias to HCD
 #define tuh_int_handler   hcd_int_handler
 
+// Check if roothub port is initialized and active as a host
+bool tuh_rhport_is_active(uint8_t rhport);
+
+// Assert/de-assert Bus Reset signal to roothub port. USB specs: it should last 10-50ms
+bool tuh_rhport_reset_bus(uint8_t rhport, bool active);
+
+//--------------------------------------------------------------------+
+// Device API
+//--------------------------------------------------------------------+
+
+// Get VID/PID of device
 bool tuh_vid_pid_get(uint8_t daddr, uint16_t* vid, uint16_t* pid);
 
+// Get speed of device
 tusb_speed_t tuh_speed_get(uint8_t daddr);
 
 // Check if device is connected and configured
@@ -144,8 +151,7 @@ bool tuh_mounted(uint8_t daddr);
 
 // Check if device is suspended
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_suspended(uint8_t daddr)
-{
+bool tuh_suspended(uint8_t daddr) {
   // TODO implement suspend & resume on host
   (void) daddr;
   return false;
@@ -153,8 +159,7 @@ bool tuh_suspended(uint8_t daddr)
 
 // Check if device is ready to communicate with
 TU_ATTR_ALWAYS_INLINE static inline
-bool tuh_ready(uint8_t daddr)
-{
+bool tuh_ready(uint8_t daddr) {
   return tuh_mounted(daddr) && !tuh_suspended(daddr);
 }
 
diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index 6ee91e18e..462cbd301 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -39,24 +39,27 @@
 #include "ci_hs_type.h"
 
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
-  #include "ci_hs_imxrt.h"
 
-  bool hcd_dcache_clean(void const* addr, uint32_t data_size) {
-    return imxrt_dcache_clean(addr, data_size);
-  }
+#include "ci_hs_imxrt.h"
 
-  bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
-    return imxrt_dcache_invalidate(addr, data_size);
-  }
+bool hcd_dcache_clean(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_clean(addr, data_size);
+}
 
-  bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
-    return imxrt_dcache_clean_invalidate(addr, data_size);
-  }
+bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_invalidate(addr, data_size);
+}
+
+bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+  return imxrt_dcache_clean_invalidate(addr, data_size);
+}
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
-  #include "ci_hs_lpc18_43.h"
+
+#include "ci_hs_lpc18_43.h"
+
 #else
-  #error "Unsupported MCUs"
+#error "Unsupported MCUs"
 #endif
 
 //--------------------------------------------------------------------+
@@ -67,25 +70,25 @@
 // Controller API
 //--------------------------------------------------------------------+
 
-bool hcd_init(uint8_t rhport)
-{
-  ci_hs_regs_t* hcd_reg = CI_HS_REG(rhport);
+bool hcd_init(uint8_t rhport) {
+  ci_hs_regs_t *hcd_reg = CI_HS_REG(rhport);
 
   // Reset controller
   hcd_reg->USBCMD |= USBCMD_RESET;
-  while( hcd_reg->USBCMD & USBCMD_RESET ) {}
+  while ( hcd_reg->USBCMD & USBCMD_RESET ) {}
 
   // Set mode to device, must be set immediately after reset
 #if CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX
   // LPC18XX/43XX need to set VBUS Power Select to HIGH
   // RHPORT1 is fullspeed only (need external PHY for Highspeed)
   hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT;
-  if (rhport == 1) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
+  if ( rhport == 1 ) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
 #else
   hcd_reg->USBMODE = USBMODE_CM_HOST;
 #endif
 
   // FIXME force full speed, still have issue with Highspeed enumeration
+  // probably due to physical connection bouncing when plug/unplug
   // 1. Have issue when plug/unplug devices, maybe the port is not reset properly
   // 2. Also does not seems to detect disconnection
   hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED;
@@ -93,13 +96,11 @@ bool hcd_init(uint8_t rhport)
   return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD);
 }
 
-void hcd_int_enable(uint8_t rhport)
-{
+void hcd_int_enable(uint8_t rhport) {
   CI_HCD_INT_ENABLE(rhport);
 }
 
-void hcd_int_disable(uint8_t rhport)
-{
+void hcd_int_disable(uint8_t rhport) {
   CI_HCD_INT_DISABLE(rhport);
 }
 
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 9be24c888..79811985c 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -188,6 +188,11 @@ void hcd_port_reset(uint8_t rhport)
 
   ehci_registers_t* regs = ehci_data.regs;
 
+  // skip if already in reset
+  if (regs->portsc_bm.port_reset) {
+    return;
+  }
+
   // mask out Write-1-to-Clear bits
   uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C;
 
@@ -202,16 +207,18 @@ void hcd_port_reset(uint8_t rhport)
 void hcd_port_reset_end(uint8_t rhport)
 {
   (void) rhport;
-
-#if 0 // TODO check if this is necessary
   ehci_registers_t* regs = ehci_data.regs;
 
+  // skip if reset is already complete
+  if (!regs->portsc_bm.port_reset) {
+    return;
+  }
+
   // mask out all change bits since they are Write 1 to clear
-  uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_CHANGE_ALL;
-  portsc &= ~(EHCI_PORTSC_MASK_PORT_RESET);
+  uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C;
+  portsc &= ~EHCI_PORTSC_MASK_PORT_RESET;
 
   regs->portsc = portsc;
-#endif
 }
 
 bool hcd_port_connect_status(uint8_t rhport)
@@ -426,6 +433,11 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet
 
   hcd_dcache_clean(setup_packet, 8);
 
+  // Control endpoint never be stalled. Skip reset Data Toggle since it is fixed per stage
+  if (qhd->qtd_overlay.halted) {
+    qhd->qtd_overlay.halted = false;
+  }
+
   // attach TD to QHD -> start transferring
   qhd_attach_qtd(qhd, td);
 
@@ -662,7 +674,7 @@ void hcd_int_handler(uint8_t rhport)
   if (int_status & EHCI_INT_MASK_PORT_CHANGE) {
     // Including: Force port resume, over-current change, enable/disable change and connect status change.
     uint32_t const port_status = regs->portsc & EHCI_PORTSC_MASK_W1C;
-    print_portsc(regs);
+    // print_portsc(regs);
 
     if (regs->portsc_bm.connect_status_change) {
       port_connect_status_change_isr(rhport);

From 18646179d0c784660ca261fb675e21787451655b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Aug 2023 18:23:16 +0700
Subject: [PATCH 1978/2085] fix host msc get maxlun not using aligned section
 memory

---
 src/class/msc/msc_host.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index a65208d69..90a58d3d0 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -421,8 +421,7 @@ bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *de
   return true;
 }
 
-bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
-{
+bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_ASSERT(p_msc->itf_num == itf_num);
 
@@ -430,10 +429,8 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
 
   //------------- Get Max Lun -------------//
   TU_LOG_DRV("MSC Get Max Lun\r\n");
-  tusb_control_request_t const request =
-  {
-    .bmRequestType_bit =
-    {
+  tusb_control_request_t const request = {
+    .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_INTERFACE,
       .type      = TUSB_REQ_TYPE_CLASS,
       .direction = TUSB_DIR_IN
@@ -444,12 +441,11 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num)
     .wLength  = 1
   };
 
-  tuh_xfer_t xfer =
-  {
+  tuh_xfer_t xfer = {
     .daddr       = dev_addr,
     .ep_addr     = 0,
     .setup       = &request,
-    .buffer      = &p_msc->max_lun,
+    .buffer      = _msch_buffer,
     .complete_cb = config_get_maxlun_complete,
     .user_data    = 0
   };
@@ -467,6 +463,8 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer)
   p_msc->max_lun = (XFER_RESULT_SUCCESS == xfer->result) ? _msch_buffer[0] : 0;
   p_msc->max_lun++; // MAX LUN is minus 1 by specs
 
+  TU_LOG_DRV("  Max LUN = %u\r\n", p_msc->max_lun);
+
   // TODO multiple LUN support
   TU_LOG_DRV("SCSI Test Unit Ready\r\n");
   uint8_t const lun = 0;

From 4938971aad2f2a6adb71f4d8ce76e1d4b664092d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Aug 2023 19:09:36 +0700
Subject: [PATCH 1979/2085] code format

---
 .../lpc18/boards/mcb1800/ozone/lpc1857.jdebug |  5 +-
 .../raspberrypi/pio_usb/hcd_pio_usb.c         | 73 +++++++------------
 2 files changed, 29 insertions(+), 49 deletions(-)

diff --git a/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
index 6e298c62d..f94960f09 100644
--- a/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
+++ b/hw/bsp/lpc18/boards/mcb1800/ozone/lpc1857.jdebug
@@ -10,7 +10,7 @@
 */
 void OnProjectLoad (void) {
   Project.AddSvdFile ("Cortex-M3.svd");
-  Project.AddSvdFile ("./LPC18xx.svd");
+  Project.AddSvdFile ("../../../../../../../cmsis-svd/data/NXP/LPC18xx.svd");
 
   Project.SetDevice ("LPC1857");
   Project.SetHostIF ("USB", "");
@@ -20,7 +20,8 @@ void OnProjectLoad (void) {
   Project.SetTraceSource ("Trace Pins");
   Project.SetTracePortWidth (4);
 
-  File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-mcb1800/cdc_msc.elf");
+  //File.Open ("../../../../../../examples/cmake-build-mcb1800/device/cdc_msc/cdc_msc.elf");
+  File.Open ("../../../../../../examples/cmake-build-mcb1800/host/cdc_msc_hid/cdc_msc_hid.elf");
 }
 /*********************************************************************
 *
diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
index adb83e97d..93bc1bf43 100644
--- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
+++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c
@@ -48,16 +48,14 @@ static pio_usb_configuration_t pio_host_cfg = PIO_USB_DEFAULT_CONFIG;
 //--------------------------------------------------------------------+
 // HCD API
 //--------------------------------------------------------------------+
-bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param)
-{
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) {
   (void) rhport;
   TU_VERIFY(cfg_id == TUH_CFGID_RPI_PIO_USB_CONFIGURATION);
   memcpy(&pio_host_cfg, cfg_param, sizeof(pio_usb_configuration_t));
   return true;
 }
 
-bool hcd_init(uint8_t rhport)
-{
+bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
   // To run USB SOF interrupt in core1, call this init in core1
@@ -66,20 +64,17 @@ bool hcd_init(uint8_t rhport)
   return true;
 }
 
-void hcd_port_reset(uint8_t rhport)
-{
+void hcd_port_reset(uint8_t rhport) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_port_reset_start(pio_rhport);
 }
 
-void hcd_port_reset_end(uint8_t rhport)
-{
+void hcd_port_reset_end(uint8_t rhport) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_port_reset_end(pio_rhport);
 }
 
-bool hcd_port_connect_status(uint8_t rhport)
-{
+bool hcd_port_connect_status(uint8_t rhport) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
 
   root_port_t *root = PIO_USB_ROOT_PORT(pio_rhport);
@@ -88,33 +83,28 @@ bool hcd_port_connect_status(uint8_t rhport)
   return line_state != PORT_PIN_SE0;
 }
 
-tusb_speed_t hcd_port_speed_get(uint8_t rhport)
-{
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
   // TODO determine link speed
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return PIO_USB_ROOT_PORT(pio_rhport)->is_fullspeed ? TUSB_SPEED_FULL : TUSB_SPEED_LOW;
 }
 
 // Close all opened endpoint belong to this device
-void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
-{
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   pio_usb_host_close_device(pio_rhport, dev_addr);
 }
 
-uint32_t hcd_frame_number(uint8_t rhport)
-{
+uint32_t hcd_frame_number(uint8_t rhport) {
   (void) rhport;
   return pio_usb_host_get_frame_number();
 }
 
-void hcd_int_enable(uint8_t rhport)
-{
+void hcd_int_enable(uint8_t rhport) {
   (void) rhport;
 }
 
-void hcd_int_disable(uint8_t rhport)
-{
+void hcd_int_disable(uint8_t rhport) {
   (void) rhport;
 }
 
@@ -122,18 +112,16 @@ void hcd_int_disable(uint8_t rhport)
 // Endpoint API
 //--------------------------------------------------------------------+
 
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
-{
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *desc_ep) {
   hcd_devtree_info_t dev_tree;
   hcd_devtree_get_info(dev_addr, &dev_tree);
   bool const need_pre = (dev_tree.hub_addr && dev_tree.speed == TUSB_SPEED_LOW);
 
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
-  return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const*) desc_ep, need_pre);
+  return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const *) desc_ep, need_pre);
 }
 
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
-{
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen);
 }
@@ -143,8 +131,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return pio_usb_host_endpoint_abort_transfer(pio_rhport, dev_addr, ep_addr);
 }
 
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
-{
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
   uint8_t const pio_rhport = RHPORT_PIO(rhport);
   return pio_usb_host_send_setup(pio_rhport, dev_addr, setup_packet);
 }
@@ -171,18 +158,16 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return true;
 }
 
-static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rport, xfer_result_t result, volatile uint32_t* ep_reg)
-{
+static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t *rport, xfer_result_t result,
+                                                               volatile uint32_t *ep_reg) {
   (void) rport;
   const uint32_t ep_all = *ep_reg;
 
-  for(uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++)
-  {
+  for ( uint8_t ep_idx = 0; ep_idx < PIO_USB_EP_POOL_CNT; ep_idx++ ) {
     uint32_t const mask = (1u << ep_idx);
 
-    if (ep_all & mask)
-    {
-      endpoint_t* ep = PIO_USB_ENDPOINT(ep_idx);
+    if ( ep_all & mask ) {
+      endpoint_t * ep = PIO_USB_ENDPOINT(ep_idx);
       hcd_event_xfer_complete(ep->dev_addr, ep->ep_num, ep->actual_len, result, true);
     }
   }
@@ -192,34 +177,28 @@ static void __no_inline_not_in_flash_func(handle_endpoint_irq)(root_port_t* rpor
 }
 
 // IRQ Handler
-void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id)
-{
+void __no_inline_not_in_flash_func(pio_usb_host_irq_handler)(uint8_t root_id) {
   uint8_t const tu_rhport = root_id + 1;
-  root_port_t* rport = PIO_USB_ROOT_PORT(root_id);
+  root_port_t *rport = PIO_USB_ROOT_PORT(root_id);
   uint32_t const ints = rport->ints;
 
-  if ( ints & PIO_USB_INTS_CONNECT_BITS )
-  {
+  if ( ints & PIO_USB_INTS_CONNECT_BITS ) {
     hcd_event_device_attach(tu_rhport, true);
   }
 
-  if ( ints & PIO_USB_INTS_DISCONNECT_BITS )
-  {
+  if ( ints & PIO_USB_INTS_DISCONNECT_BITS ) {
     hcd_event_device_remove(tu_rhport, true);
   }
 
-  if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS )
-  {
+  if ( ints & PIO_USB_INTS_ENDPOINT_COMPLETE_BITS ) {
     handle_endpoint_irq(rport, XFER_RESULT_SUCCESS, &rport->ep_complete);
   }
 
-  if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS )
-  {
+  if ( ints & PIO_USB_INTS_ENDPOINT_STALLED_BITS ) {
     handle_endpoint_irq(rport, XFER_RESULT_STALLED, &rport->ep_stalled);
   }
 
-  if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS )
-  {
+  if ( ints & PIO_USB_INTS_ENDPOINT_ERROR_BITS ) {
     handle_endpoint_irq(rport, XFER_RESULT_FAILED, &rport->ep_error);
   }
 

From c24f10e4f6d46c7f65136b57be0fa2063fe7c9f2 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Mon, 7 Aug 2023 20:48:54 +0200
Subject: [PATCH 1980/2085] Mount block device in test_cdc_msc.

---
 test/hitl/hitl_test.py | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/test/hitl/hitl_test.py b/test/hitl/hitl_test.py
index 6c8066add..f6e741646 100644
--- a/test/hitl/hitl_test.py
+++ b/test/hitl/hitl_test.py
@@ -22,8 +22,8 @@
 # THE SOFTWARE.
 
 # udev rules :
-# SUBSYSTEM=="block", SUBSYSTEMS=="usb", MODE="0666", PROGRAM="/bin/sh -c 'echo $$ID_SERIAL_SHORT | rev | cut -c -8 | rev'", SYMLINK+="blkUSB_%c.%s{bInterfaceNumber}"
-# SUBSYSTEM=="tty", SUBSYSTEMS=="usb", MODE="0666", PROGRAM="/bin/sh -c 'echo $$ID_SERIAL_SHORT | rev | cut -c -8 | rev'", SYMLINK+="ttyUSB_%c.%s{bInterfaceNumber}"
+# ACTION=="add", SUBSYSTEM=="tty", SUBSYSTEMS=="usb", MODE="0666", PROGRAM="/bin/sh -c 'echo $$ID_SERIAL_SHORT | rev | cut -c -8 | rev'", SYMLINK+="ttyUSB_%c.%s{bInterfaceNumber}"
+# ACTION=="add", SUBSYSTEM=="block", SUBSYSTEMS=="usb", ENV{ID_FS_USAGE}=="filesystem", MODE="0666", PROGRAM="/bin/sh -c 'echo $$ID_SERIAL_SHORT | rev | cut -c -8 | rev'", RUN{program}+="/usr/bin/systemd-mount --no-block --automount=yes --collect $devnode /media/blkUSB_%c.%s{bInterfaceNumber}"
 
 import os
 import sys
@@ -80,16 +80,16 @@ def test_cdc_dual_ports(id):
 
 def test_cdc_msc(id):
     port  = f'/dev/ttyUSB_{id[-8:]}.00'
-    block = f'/dev/blkUSB_{id[-8:]}.02'
+    file = f'/media/blkUSB_{id[-8:]}.02/README.TXT'
     # Wait device enum
     timeout = 10
     while timeout:
-        if os.path.exists(port) and os.path.exists(block):
+        if os.path.exists(port) and os.path.isfile(file):
             break
         time.sleep(1)
         timeout = timeout - 1
 
-    assert os.path.exists(port) and os.path.exists(block), \
+    assert os.path.exists(port) and os.path.isfile(file), \
         'Device not available'
 
     # Echo test
@@ -100,10 +100,10 @@ def test_cdc_msc(id):
     str = b"test_str"
     ser1.write(str)
     ser1.flush()
-    assert ser1.read(100) == str, 'Port wrong data'
+    assert ser1.read(100) == str, 'CDC wrong data'
 
     # Block test
-    f = open(block, 'rb')
+    f = open(file, 'rb')
     data = f.read()
 
     readme = \
@@ -111,7 +111,7 @@ def test_cdc_msc(id):
 If you find any bugs or get any questions, feel free to file an\r\n\
 issue at github.com/hathach/tinyusb"
 
-    assert data[0x600:0x600 + len(readme)] == readme, 'Block wrong data'
+    assert data == readme, 'MSC wrong data'
     print('cdc_msc test done')
 
 def test_dfu(id):

From 12ed867b5e494f7bb73e00fc953de32d78253491 Mon Sep 17 00:00:00 2001
From: Rocky04 <rockerfaeller04@gmx.de>
Date: Mon, 7 Aug 2023 20:59:08 +0200
Subject: [PATCH 1981/2085] Fixed typo

---
 examples/device/hid_composite_freertos/src/main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c
index 4ed506f6c..2ba646e7a 100644
--- a/examples/device/hid_composite_freertos/src/main.c
+++ b/examples/device/hid_composite_freertos/src/main.c
@@ -182,7 +182,7 @@ void tud_resume_cb(void)
   }
   else
   {
-    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0);
+    xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
   }
 }
 

From c959e65edde0b07b80c3e12f177afd938abbdcd6 Mon Sep 17 00:00:00 2001
From: Rocky04 <rockerfaeller04@gmx.de>
Date: Mon, 7 Aug 2023 21:16:41 +0200
Subject: [PATCH 1982/2085] Fixing wrong callback placement

---
 src/device/usbd.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index b4ca63c9c..2daf91d77 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -711,7 +711,16 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
             }
 
             // switch to new configuration if not zero
-            if ( cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) );
+            if ( cfg_num )
+            {
+              TU_ASSERT( process_set_config(rhport, cfg_num) );
+
+              if ( tud_mount_cb ) tud_mount_cb();
+            }
+            else
+            {
+              if ( tud_umount_cb ) tud_umount_cb();
+            }
           }
 
           _usbd_dev.cfg_num = cfg_num;
@@ -964,16 +973,6 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
     TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT);
   }
 
-  // invoke callback
-  if (cfg_num)
-  {
-    if (tud_mount_cb) tud_mount_cb();
-  }
-  else
-  {
-    if (tud_umount_cb) tud_umount_cb();
-  }
-
   return true;
 }
 

From 9602c06f8d52212b55b02533e188e91b7192c080 Mon Sep 17 00:00:00 2001
From: Rocky04 <rockerfaeller04@gmx.de>
Date: Mon, 7 Aug 2023 21:25:50 +0200
Subject: [PATCH 1983/2085] Correcting comments

---
 src/device/usbd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 2daf91d77..156b92ce1 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -710,9 +710,10 @@ static bool process_control_request(uint8_t rhport, tusb_control_request_t const
               _usbd_dev.speed = speed; // restore speed
             }
 
-            // switch to new configuration if not zero
+            // Handle the new configuration and execute the corresponding callback
             if ( cfg_num )
             {
+              // switch to new configuration if not zero
               TU_ASSERT( process_set_config(rhport, cfg_num) );
 
               if ( tud_mount_cb ) tud_mount_cb();

From 6d877c31705e4343d30e2a6b65cbd230a3fe2001 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 8 Aug 2023 18:50:24 +0700
Subject: [PATCH 1984/2085] added cmake for lpc54, update lpc55

---
 hw/bsp/lpc54/boards/lpcxpresso54608/board.h   |  59 +++++++
 hw/bsp/lpc54/boards/lpcxpresso54608/board.mk  |  18 ++
 .../lpc54/boards/lpcxpresso54628/board.cmake  |  22 +++
 hw/bsp/lpc54/family.cmake                     | 157 ++++++++++++++++++
 .../boards/double_m33_express/board.cmake     |   7 +-
 .../lpc55/boards/lpcxpresso55s28/board.cmake  |   5 +
 .../lpc55/boards/lpcxpresso55s69/board.cmake  |   7 +-
 hw/bsp/lpc55/family.cmake                     | 134 +++++++++------
 src/tusb_option.h                             |   7 +-
 9 files changed, 356 insertions(+), 60 deletions(-)
 create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54608/board.h
 create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54608/board.mk
 create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
 create mode 100644 hw/bsp/lpc54/family.cmake

diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
new file mode 100644
index 000000000..8bbe18155
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h
@@ -0,0 +1,59 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_LPCXPRESSO54608_H_
+#define BOARD_LPCXPRESSO54608_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED
+#define LED_PORT              2
+#define LED_PIN               2
+#define LED_STATE_ON          0
+
+// WAKE button
+#define BUTTON_PORT           1
+#define BUTTON_PIN            1
+#define BUTTON_STATE_ACTIVE   0
+
+// UART
+#define UART_DEV              USART0
+#define UART_RX_PINMUX        0, 29, IOCON_PIO_DIG_FUNC1_EN
+#define UART_TX_PINMUX        0, 30, IOCON_PIO_DIG_FUNC1_EN
+
+// USB0 VBUS
+#define USB0_VBUS_PINMUX      0, 22, IOCON_PIO_DIG_FUNC7_EN
+
+// XTAL
+//#define XTAL0_CLK_HZ          (16 * 1000 * 1000U)
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk b/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk
new file mode 100644
index 000000000..af2eaf507
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.mk
@@ -0,0 +1,18 @@
+MCU_VARIANT = LPC54608
+MCU_CORE = LPC54608
+
+PORT ?= 1
+
+CFLAGS += -DCPU_LPC54608J512ET180
+CFLAGS += -Wno-error=double-promotion
+
+LD_FILE = $(MCU_DIR)/gcc/LPC54608J512_flash.ld
+
+LIBS += $(TOP)/$(MCU_DIR)/gcc/libpower_hardabi.a
+
+JLINK_DEVICE = LPC54608J512
+PYOCD_TARGET = LPC54608
+
+#flash: flash-pyocd
+
+flash: flash-jlink
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
new file mode 100644
index 000000000..1dea6f353
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.cmake
@@ -0,0 +1,22 @@
+set(MCU_VARIANT LPC54628)
+set(MCU_CORE LPC54628)
+
+set(JLINK_DEVICE LPC54628J512)
+set(PYOCD_TARGET LPC54628)
+set(NXPLINK_DEVICE LPC54628:LPCXpresso54628)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54628J512_flash.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC54628J512ET180
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_hardabi.a
+    )
+endfunction()
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
new file mode 100644
index 000000000..0512fe31f
--- /dev/null
+++ b/hw/bsp/lpc54/family.cmake
@@ -0,0 +1,157 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS LPC54 CACHE INTERNAL "")
+
+if (NOT DEFINED PORT)
+  set(PORT 0)
+endif()
+
+# Host port will be the other port if available
+set(HOST_PORT $<NOT:${PORT}>)
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      # driver
+      ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+      ${SDK_DIR}/drivers/common/fsl_common_arm.c
+      ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+      ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+      # mcu
+      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+      )
+
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+      BOARD_TUD_RHPORT=${PORT}
+      BOARD_TUH_RHPORT=${HOST_PORT}
+      )
+    # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+    if (PORT EQUAL 1)
+      target_compile_definitions(${BOARD_TARGET} PUBLIC
+        BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+        BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
+        CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+        )
+    else ()
+      target_compile_definitions(${BOARD_TARGET} PUBLIC
+        BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+        BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
+        CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+        )
+    endif ()
+
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${TOP}/lib/sct_neopixel
+      # driver
+      ${SDK_DIR}/drivers/common
+      ${SDK_DIR}/drivers/flexcomm
+      ${SDK_DIR}/drivers/lpc_iocon
+      ${SDK_DIR}/drivers/lpc_gpio
+      ${SDK_DIR}/drivers/lpuart
+      ${SDK_DIR}/drivers/sctimer
+      # mcu
+      ${CMSIS_DIR}/CMSIS/Core/Include
+      ${SDK_DIR}/devices/${MCU_VARIANT}
+      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+      set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+    endif ()
+
+    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+      set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+    endif ()
+
+    target_sources(${BOARD_TARGET} PUBLIC
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        # linker file
+        "LINKER:--script=${LD_FILE_GNU}"
+        # nanolib
+        --specs=nosys.specs
+        --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    # external driver
+    ${TOP}/lib/sct_neopixel/sct_neopixel.c
+    )
+
+  # https://github.com/gsteiert/sct_neopixel/pull/1
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    set_source_files_properties(${TOP}/lib/sct_neopixel/sct_neopixel.c PROPERTIES
+      COMPILE_FLAGS "-Wno-unused-parameter")
+  endif ()
+
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC54 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+  #family_flash_nxplink(${TARGET})
+  #family_flash_pyocd(${TARGET})
+endfunction()
diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.cmake b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
index f84e629c7..3324ce888 100644
--- a/hw/bsp/lpc55/boards/double_m33_express/board.cmake
+++ b/hw/bsp/lpc55/boards/double_m33_express/board.cmake
@@ -7,10 +7,13 @@ set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
 set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
 
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S69JBD100_cm33_core0
-    # port 1 is highspeed
-    BOARD_TUD_RHPORT=1
     )
 endfunction()
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
index d935b70e6..b3d0c3349 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake
@@ -5,6 +5,11 @@ set(JLINK_DEVICE LPC55S28)
 set(PYOCD_TARGET LPC55S28)
 set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28)
 
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S28JBD100
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
index fd7cb6de6..3af6034ad 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
@@ -5,10 +5,13 @@ set(JLINK_DEVICE LPC55S69)
 set(PYOCD_TARGET LPC55S69)
 set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC
     CPU_LPC55S69JBD100_cm33_core0
-    # port 1 is highspeed
-    # BOARD_TUD_RHPORT=1
     )
 endfunction()
diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake
index dfd08a732..dce197b2d 100644
--- a/hw/bsp/lpc55/family.cmake
+++ b/hw/bsp/lpc55/family.cmake
@@ -7,79 +7,105 @@ endif ()
 set(SDK_DIR ${TOP}/hw/mcu/nxp/mcux-sdk)
 set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
 
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
 # toolchain set up
 set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
 set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
 
-set(FAMILY_MCUS LPC55XX CACHE INTERNAL "")
+set(FAMILY_MCUS LPC55 CACHE INTERNAL "")
 
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+if (NOT DEFINED PORT)
+  set(PORT 0)
+endif()
 
+# Host port will be the other port if available
+set(HOST_PORT $<NOT:${PORT}>)
 
 #------------------------------------
 # BOARD_TARGET
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      # driver
-      ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
-      ${SDK_DIR}/drivers/common/fsl_common_arm.c
-      ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-      ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
-      # mcu
-      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
-      )
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
+
+  add_library(${BOARD_TARGET} STATIC
+    # driver
+    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    )
+
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    BOARD_TUD_RHPORT=${PORT}
+    BOARD_TUH_RHPORT=${HOST_PORT}
+    )
+  # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+  if (PORT EQUAL 1)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
-      CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+      BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
+      CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
       )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${TOP}/lib/sct_neopixel
-      # driver
-      ${SDK_DIR}/drivers/common
-      ${SDK_DIR}/drivers/flexcomm
-      ${SDK_DIR}/drivers/lpc_iocon
-      ${SDK_DIR}/drivers/lpc_gpio
-      ${SDK_DIR}/drivers/lpuart
-      ${SDK_DIR}/drivers/sctimer
-      # mcu
-      ${CMSIS_DIR}/CMSIS/Core/Include
-      ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+  else ()
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+      BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
       )
+  endif ()
 
-    update_board(${BOARD_TARGET})
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${TOP}/lib/sct_neopixel
+    # driver
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/lpc_iocon
+    ${SDK_DIR}/drivers/lpc_gpio
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/sctimer
+    # mcu
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    )
 
-    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
-      set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
-    endif ()
+  update_board(${BOARD_TARGET})
 
-    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
-      set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
-    endif ()
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+  endif ()
 
-    target_sources(${BOARD_TARGET} PUBLIC
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+  endif ()
+
+  target_sources(${BOARD_TARGET} PUBLIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      # linker file
+      "LINKER:--script=${LD_FILE_GNU}"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
       )
-
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        # linker file
-        "LINKER:--script=${LD_FILE_GNU}"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
   endif ()
 endfunction()
 
@@ -117,7 +143,7 @@ function(family_configure_example TARGET RTOS)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_LPC55XX ${RTOS})
+  family_add_tinyusb(${TARGET} OPT_MCU_LPC55 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
     )
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 7a4cfe51c..c72117850 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -51,8 +51,11 @@
 #define OPT_MCU_LPC40XX             7 ///< NXP LPC40xx
 #define OPT_MCU_LPC43XX             8 ///< NXP LPC43xx
 #define OPT_MCU_LPC51UXX            9 ///< NXP LPC51U6x
-#define OPT_MCU_LPC54XXX           10 ///< NXP LPC54xxx
-#define OPT_MCU_LPC55XX            11 ///< NXP LPC55xx
+#define OPT_MCU_LPC54              10 ///< NXP LPC54
+#define OPT_MCU_LPC55              11 ///< NXP LPC55
+// legacy naming
+#define OPT_MCU_LPC54XXX           OPT_MCU_LPC54
+#define OPT_MCU_LPC55XX            OPT_MCU_LPC55
 
 // NRF
 #define OPT_MCU_NRF5X             100 ///< Nordic nRF5x series

From 3444c4abe5d12ac2a74726cb244525f9481830ff Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 8 Aug 2023 17:34:07 +0200
Subject: [PATCH 1985/2085] Add dummy board_test.

---
 test/hitl/hitl_test.py | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/test/hitl/hitl_test.py b/test/hitl/hitl_test.py
index f6e741646..dc6019470 100644
--- a/test/hitl/hitl_test.py
+++ b/test/hitl/hitl_test.py
@@ -155,7 +155,7 @@ def test_dfu(id):
     print('dfu test done')
 
 def test_dfu_runtime(id):
-     # Wait device enum
+    # Wait device enum
     timeout = 10
     while timeout:
         ret = subprocess.run(f'dfu-util -l',
@@ -170,6 +170,9 @@ def test_dfu_runtime(id):
 
     print('dfu_runtime test done')
 
+def test_board_test(id):
+    # Dummy test
+    pass
 
 if __name__ == '__main__':
     if len(sys.argv) != 2:

From 56bed1e5811a97016533a25069408e45dd6f41ba Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 8 Aug 2023 17:34:45 +0200
Subject: [PATCH 1986/2085] Flash board_test when done, skip cdc_msc for LPC54.

---
 test/hitl/hitl_hfp.json | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/test/hitl/hitl_hfp.json b/test/hitl/hitl_hfp.json
index 297ae8b81..426123288 100644
--- a/test/hitl/hitl_hfp.json
+++ b/test/hitl/hitl_hfp.json
@@ -21,6 +21,10 @@
                 {
                     "name": "dfu_runtime",
                     "firmware": "examples/device/dfu_runtime/_build/stm32l412nucleo/dfu_runtime.elf"
+                },
+                {
+                    "name": "board_test",
+                    "firmware": "examples/device/board_test/_build/stm32l412nucleo/board_test.elf"
                 }
             ]
         },
@@ -45,6 +49,10 @@
                 {
                     "name": "dfu_runtime",
                     "firmware": "examples/device/dfu_runtime/_build/stm32f746disco/dfu_runtime.elf"
+                },
+                {
+                    "name": "board_test",
+                    "firmware": "examples/device/board_test/_build/stm32f746disco/board_test.elf"
                 }
             ]
         },
@@ -58,10 +66,6 @@
                     "name": "cdc_dual_ports",
                     "firmware": "examples/device/cdc_dual_ports/_build/lpcxpresso54628/cdc_dual_ports.elf"
                 },
-                {
-                    "name": "cdc_msc",
-                    "firmware": "examples/device/cdc_msc/_build/lpcxpresso54628/cdc_msc.elf"
-                },
                 {
                     "name": "dfu",
                     "firmware": "examples/device/dfu/_build/lpcxpresso54628/dfu.elf"
@@ -69,6 +73,10 @@
                 {
                     "name": "dfu_runtime",
                     "firmware": "examples/device/dfu_runtime/_build/lpcxpresso54628/dfu_runtime.elf"
+                },
+                {
+                    "name": "board_test",
+                    "firmware": "examples/device/board_test/_build/lpcxpresso54628/board_test.elf"
                 }
             ]
         }

From bffe321cd25681c5bab836098bde0f1aa215f5a7 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 8 Aug 2023 18:25:15 +0200
Subject: [PATCH 1987/2085] Update contributor.rst

---
 CONTRIBUTORS.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst
index 50a33ae33..085f8082a 100644
--- a/CONTRIBUTORS.rst
+++ b/CONTRIBUTORS.rst
@@ -200,6 +200,8 @@ Notable contributors
 -  Add new DCD port for Microchip SAMx7x
 -  Add IAR compiler support
 -  Improve UAC2, CDC, DFU class driver
+-  Improve stm32_fsdev, chipidea_ci_hs, lpc_ip3511 DCD
+-  Host IAR Build CI & hardware in the loop (HITL) test
 
 
 `Full contributors list <https://github.com/hathach/tinyusb/contributors>`__

From 992e17fb4833f102e23f8241ac1d7fea0985cb4e Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 8 Aug 2023 22:08:59 +0200
Subject: [PATCH 1988/2085] Add simple test for hid_boot_interface.

---
 test/hitl/hitl_hfp.json |  8 ++++++++
 test/hitl/hitl_test.py  | 22 ++++++++++++++++++----
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/test/hitl/hitl_hfp.json b/test/hitl/hitl_hfp.json
index 426123288..866e5233f 100644
--- a/test/hitl/hitl_hfp.json
+++ b/test/hitl/hitl_hfp.json
@@ -22,6 +22,10 @@
                     "name": "dfu_runtime",
                     "firmware": "examples/device/dfu_runtime/_build/stm32l412nucleo/dfu_runtime.elf"
                 },
+                {
+                    "name": "hid_boot_interface",
+                    "firmware": "examples/device/hid_boot_interface/_build/stm32l412nucleo/hid_boot_interface.elf"
+                },
                 {
                     "name": "board_test",
                     "firmware": "examples/device/board_test/_build/stm32l412nucleo/board_test.elf"
@@ -50,6 +54,10 @@
                     "name": "dfu_runtime",
                     "firmware": "examples/device/dfu_runtime/_build/stm32f746disco/dfu_runtime.elf"
                 },
+                {
+                    "name": "hid_boot_interface",
+                    "firmware": "examples/device/hid_boot_interface/_build/stm32f746disco/hid_boot_interface.elf"
+                },
                 {
                     "name": "board_test",
                     "firmware": "examples/device/board_test/_build/stm32f746disco/board_test.elf"
diff --git a/test/hitl/hitl_test.py b/test/hitl/hitl_test.py
index dc6019470..695c6a28c 100644
--- a/test/hitl/hitl_test.py
+++ b/test/hitl/hitl_test.py
@@ -54,8 +54,7 @@ def test_cdc_dual_ports(id):
         time.sleep(1)
         timeout = timeout - 1
 
-    assert os.path.exists(port1) and os.path.exists(port2), \
-        'Device not available'
+    assert timeout, 'Device not available'
 
     # Echo test
     ser1 = serial.Serial(port1)
@@ -89,8 +88,7 @@ def test_cdc_msc(id):
         time.sleep(1)
         timeout = timeout - 1
 
-    assert os.path.exists(port) and os.path.isfile(file), \
-        'Device not available'
+    assert timeout, 'Device not available'
 
     # Echo test
     ser1 = serial.Serial(port)
@@ -170,6 +168,22 @@ def test_dfu_runtime(id):
 
     print('dfu_runtime test done')
 
+def test_hid_boot_interface(id):
+    kbd  = f'/dev/input/by-id/usb-TinyUSB_TinyUSB_Device_{id}-event-kbd'
+    mouse1  = f'/dev/input/by-id/usb-TinyUSB_TinyUSB_Device_{id}-if01-event-mouse'
+    mouse2  = f'/dev/input/by-id/usb-TinyUSB_TinyUSB_Device_{id}-if01-mouse'
+    # Wait device enum
+    timeout = 10
+    while timeout:
+        if os.path.exists(kbd) and os.path.exists(mouse1) and os.path.exists(mouse2):
+            break
+        time.sleep(1)
+        timeout = timeout - 1
+
+    assert timeout, 'Device not available'
+
+    print('hid_boot_interface test done')
+
 def test_board_test(id):
     # Dummy test
     pass

From b8b01c10758043d318716569e693912f3e02c75b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 8 Aug 2023 21:59:36 +0700
Subject: [PATCH 1989/2085] update to dcd ip3511 to add work-around for
 lpc54628 usb hs errata USB.1 and USB.2

msc is mounted, but device couldn't work reliably and got constant reset
due to other errata probably.
---
 .idea/cmake.xml                              |   4 +-
 hw/bsp/lpc54/family.c                        |   6 +-
 hw/bsp/lpc54/family.cmake                    |   1 +
 src/common/tusb_common.h                     |   5 +-
 src/common/tusb_mcu.h                        |   8 +-
 src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 264 +++++++++++--------
 6 files changed, 169 insertions(+), 119 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 76143ba10..4a69d02cf 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -30,7 +30,8 @@
       <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="ea4357" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4357 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69" />
+      <configuration PROFILE_NAME="lpc54628" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpc55s69" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
@@ -51,6 +52,7 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
+      <configuration PROFILE_NAME="lpc54628 PORT0" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT -DPORT=0" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c
index 108a7d783..7411c72d4 100644
--- a/hw/bsp/lpc54/family.c
+++ b/hw/bsp/lpc54/family.c
@@ -70,13 +70,11 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
+void USB0_IRQHandler(void) {
   tud_int_handler(0);
 }
 
-void USB1_IRQHandler(void)
-{
+void USB1_IRQHandler(void) {
   tud_int_handler(1);
 }
 
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
index 0512fe31f..b016441c1 100644
--- a/hw/bsp/lpc54/family.cmake
+++ b/hw/bsp/lpc54/family.cmake
@@ -59,6 +59,7 @@ function(add_board_target BOARD_TARGET)
         BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
         BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
         CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+        #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
         )
     endif ()
 
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 25f85e501..c303c6eaf 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -159,11 +159,12 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_max16 (uint16_t x, uint16_t y) {
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_max32 (uint32_t x, uint32_t y) { return (x > y) ? x : y; }
 
 //------------- Align -------------//
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment) {
   return value & ((uint32_t) ~(alignment-1));
 }
 
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4  (uint32_t value) { return (value & 0xFFFFFFFCUL); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align8  (uint32_t value) { return (value & 0xFFFFFFF8UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); }
 TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); }
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 89f89182e..35f94efbc 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -58,6 +58,7 @@
 // NXP
 //--------------------------------------------------------------------+
 #if   TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
+  #define TUP_USBIP_IP3511
   #define TUP_DCD_ENDPOINT_MAX    5
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC40XX)
@@ -66,14 +67,17 @@
   #define TUP_OHCI_RHPORTS        2
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC51UXX)
+   #define TUP_USBIP_IP3511
    #define TUP_DCD_ENDPOINT_MAX   5
 
-#elif TU_CHECK_MCU(OPT_MCU_LPC54XXX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC54)
   // TODO USB0 has 5, USB1 has 6
+  #define TUP_USBIP_IP3511
   #define TUP_DCD_ENDPOINT_MAX    6
 
-#elif TU_CHECK_MCU(OPT_MCU_LPC55XX)
+#elif TU_CHECK_MCU(OPT_MCU_LPC55)
   // TODO USB0 has 5, USB1 has 6
+  #define TUP_USBIP_IP3511
   #define TUP_DCD_ENDPOINT_MAX    6
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
index 7ca698a93..f4ed09d83 100644
--- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
+++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
@@ -34,18 +34,13 @@
  * - LPC54114
  * - LPC55s69
  */
-#if CFG_TUD_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_LPC11UXX || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC13XX  || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC15XX  || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC51UXX || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC54XXX || \
-                                 CFG_TUSB_MCU == OPT_MCU_LPC55XX)
+#if CFG_TUD_ENABLED && defined(TUP_USBIP_IP3511)
 
 //--------------------------------------------------------------------+
 // INCLUDE
 //--------------------------------------------------------------------+
 
-#if CFG_TUSB_MCU == OPT_MCU_LPC11UXX || CFG_TUSB_MCU == OPT_MCU_LPC13XX || CFG_TUSB_MCU == OPT_MCU_LPC15XX
+#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX)
   // LPCOpen
   #include "chip.h"
 #else
@@ -80,7 +75,7 @@ typedef struct {
 enum {
   NBYTES_ISO_FS_MAX = 1023, // FS ISO
   NBYTES_ISO_HS_MAX = 1024, // HS ISO
-  NBYTES_CBI_FS_MAX = 64, // FS control/bulk/interrupt
+  NBYTES_CBI_FS_MAX = 64,   // FS control/bulk/interrupt. TODO some FS can do burst with higher size e.g 1024. Need to test
   NBYTES_CBI_HS_MAX = 32767 // can be up to all 15-bit, but only tested with 4096
 };
 
@@ -90,26 +85,36 @@ enum {
 };
 
 enum {
-  CMDSTAT_DEVICE_ADDR_MASK    = TU_BIT(7 )-1,
-  CMDSTAT_DEVICE_ENABLE_MASK  = TU_BIT(7 ),
-  CMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ),
-  CMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state
-  CMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17),
-                                            // 23-22 is link speed (only available for HighSpeed port)
-  CMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24),
-  CMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25),
-  CMDSTAT_RESET_CHANGE_MASK   = TU_BIT(26),
-  CMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
+  DEVCMDSTAT_DEVICE_ADDR_MASK    = TU_BIT(7 )-1,
+  DEVCMDSTAT_DEVICE_ENABLE_MASK  = TU_BIT(7 ),
+  DEVCMDSTAT_SETUP_RECEIVED_MASK = TU_BIT(8 ),
+  DEVCMDSTAT_DEVICE_CONNECT_MASK = TU_BIT(16), // reflect the soft-connect only, does not reflect the actual attached state
+  DEVCMDSTAT_DEVICE_SUSPEND_MASK = TU_BIT(17),
+                                               // 23-22 is link speed (only available for HighSpeed port)
+  DEVCMDSTAT_CONNECT_CHANGE_MASK = TU_BIT(24),
+  DEVCMDSTAT_SUSPEND_CHANGE_MASK = TU_BIT(25),
+  DEVCMDSTAT_RESET_CHANGE_MASK   = TU_BIT(26),
+  DEVCMDSTAT_VBUS_DEBOUNCED_MASK = TU_BIT(28),
 };
 
 enum {
-  CMDSTAT_SPEED_SHIFT = 22
+  DEVCMDSTAT_SPEED_SHIFT = 22
 };
 
 //--------------------------------------------------------------------+
 // Endpoint Command/Status List
 //--------------------------------------------------------------------+
 
+// EP Command/Status field definition
+enum {
+  EPCS_TYPE         = TU_BIT(26),
+  EPCS_RF_TV        = TU_BIT(27),
+  EPCS_TOGGLE_RESET = TU_BIT(28),
+  EPCS_STALL        = TU_BIT(29),
+  EPCS_DISABLED     = TU_BIT(30),
+  EPCS_ACTIVE       = TU_BIT(31),
+};
+
 // Endpoint Command/Status
 typedef union TU_ATTR_PACKED
 {
@@ -133,8 +138,8 @@ typedef union TU_ATTR_PACKED
 
   volatile struct {
     uint32_t TU_RESERVED  : 26;
-    uint32_t is_iso       : 1 ;
-    uint32_t toggle_mode  : 1 ;
+    uint32_t type         : 1 ;
+    uint32_t rf_tv        : 1 ; // rate feedback or toggle value
     uint32_t toggle_reset : 1 ;
     uint32_t stall        : 1 ;
     uint32_t disable      : 1 ;
@@ -180,6 +185,7 @@ typedef struct
 CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(256) static dcd_data_t _dcd;
 
 // Dummy buffer to fix ZLPs overwriting the buffer (probably an USB/DMA controller bug)
+// TODO find way to save memory
 CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
 
 //--------------------------------------------------------------------+
@@ -188,59 +194,73 @@ CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(64) static uint8_t dummy[8];
 
 typedef struct
 {
-  dcd_registers_t* regs;        // registers
-  const tusb_speed_t max_speed; // max link speed
-  const IRQn_Type irqnum;       // IRQ number
-  const uint8_t ep_pairs;       // Max bi-directional Endpoints
+  dcd_registers_t* regs;   // registers
+  const bool is_highspeed; // max link speed
+  const IRQn_Type irqnum;  // IRQ number
+  const uint8_t ep_pairs;  // Max bi-directional Endpoints
 }dcd_controller_t;
 
 #ifdef INCLUDE_FSL_DEVICE_REGISTERS
 
-static const dcd_controller_t _dcd_controller[] =
-{
-    { .regs = (dcd_registers_t*) USB0_BASE  , .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM    },
+static const dcd_controller_t _dcd_controller[] = {
+    { .regs = (dcd_registers_t*) USB0_BASE  , .is_highspeed = false, .irqnum = USB0_IRQn, .ep_pairs = FSL_FEATURE_USB_EP_NUM    },
   #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
-    { .regs = (dcd_registers_t*) USBHSD_BASE, .max_speed = TUSB_SPEED_HIGH, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
+    { .regs = (dcd_registers_t*) USBHSD_BASE, .is_highspeed = true, .irqnum = USB1_IRQn, .ep_pairs = FSL_FEATURE_USBHSD_EP_NUM }
   #endif
 };
 
 #else
 
-static const dcd_controller_t _dcd_controller[] =
-{
-  { .regs = (dcd_registers_t*) LPC_USB0_BASE, .max_speed = TUSB_SPEED_FULL, .irqnum = USB0_IRQn, .ep_pairs = 5 },
+static const dcd_controller_t _dcd_controller[] = {
+  { .regs = (dcd_registers_t*) LPC_USB0_BASE, .is_highspeed = false, .irqnum = USB0_IRQn, .ep_pairs = 5 },
 };
 
 #endif
 
+#if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT
+  #define IP3511_HAS_HIGHSPEED
+#endif
+
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
 //--------------------------------------------------------------------+
 
-static inline uint16_t get_buf_offset(void const * buffer)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint16_t get_buf_offset(void const * buffer) {
   uint32_t addr = (uint32_t) buffer;
   TU_ASSERT( (addr & 0x3f) == 0, 0 );
   return ( (addr >> 6) & 0xFFFFUL ) ;
 }
 
-static inline uint8_t ep_addr2id(uint8_t ep_addr)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint8_t ep_addr2id(uint8_t ep_addr) {
   return 2*(ep_addr & 0x0F) + ((ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(ep_cmd_sts_t* ep_cs, bool is_highspeed) {
+  return is_highspeed ? (ep_cs[0].cmd_sts.type && !ep_cs[0].cmd_sts.rf_tv) : ep_cs->cmd_sts.type;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool ep_is_bulk(ep_cmd_sts_t* ep_cs) {
+  return (ep_cs[0].cmd_sts.type == 0) && (ep_cs[0].cmd_sts.rf_tv == 0);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline ep_cmd_sts_t* get_ep_cs(uint8_t ep_id) {
+  return _dcd.ep[ep_id];
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool rhport_is_highspeed(uint8_t rhport) {
+  return _dcd_controller[rhport].is_highspeed;
+}
+
 //--------------------------------------------------------------------+
 // CONTROLLER API
 //--------------------------------------------------------------------+
 
-static void prepare_setup_packet(uint8_t rhport)
-{
-  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
-  {
-    _dcd.ep[0][1].buffer_fs.offset = get_buf_offset(_dcd.setup_packet);
-  }else
-  {
-    _dcd.ep[0][1].buffer_hs.offset = get_buf_offset(_dcd.setup_packet);
+static void prepare_setup_packet(uint8_t rhport) {
+  uint16_t const buf_offset = get_buf_offset(_dcd.setup_packet);
+  if ( _dcd_controller[rhport].is_highspeed ) {
+    _dcd.ep[0][1].buffer_hs.offset = buf_offset;
+  } else {
+    _dcd.ep[0][1].buffer_fs.offset = buf_offset;
   }
 }
 
@@ -268,8 +288,8 @@ void dcd_init(uint8_t rhport)
   dcd_reg->DATABUFSTART = tu_align((uint32_t) &_dcd, TU_BIT(22)); // 22-bit alignment
   dcd_reg->INTSTAT     |= dcd_reg->INTSTAT; // clear all pending interrupt
   dcd_reg->INTEN        = INT_DEVICE_STATUS_MASK;
-  dcd_reg->DEVCMDSTAT  |= CMDSTAT_DEVICE_ENABLE_MASK | CMDSTAT_DEVICE_CONNECT_MASK |
-                           CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+  dcd_reg->DEVCMDSTAT  |= DEVCMDSTAT_DEVICE_ENABLE_MASK | DEVCMDSTAT_DEVICE_CONNECT_MASK |
+                           DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK;
 
   NVIC_ClearPendingIRQ(_dcd_controller[rhport].irqnum);
 }
@@ -291,7 +311,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
   // Response with status first before changing device address
   dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 
-  dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_ADDR_MASK;
+  dcd_reg->DEVCMDSTAT &= ~DEVCMDSTAT_DEVICE_ADDR_MASK;
   dcd_reg->DEVCMDSTAT |= dev_addr;
 }
 
@@ -303,13 +323,13 @@ void dcd_remote_wakeup(uint8_t rhport)
 void dcd_connect(uint8_t rhport)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->DEVCMDSTAT |= CMDSTAT_DEVICE_CONNECT_MASK;
+  dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_DEVICE_CONNECT_MASK;
 }
 
 void dcd_disconnect(uint8_t rhport)
 {
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
-  dcd_reg->DEVCMDSTAT &= ~CMDSTAT_DEVICE_CONNECT_MASK;
+  dcd_reg->DEVCMDSTAT &= ~DEVCMDSTAT_DEVICE_CONNECT_MASK;
 }
 
 void dcd_sof_enable(uint8_t rhport, bool en)
@@ -340,19 +360,39 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 
   _dcd.ep[ep_id][0].cmd_sts.stall        = 0;
   _dcd.ep[ep_id][0].cmd_sts.toggle_reset = 1;
-  _dcd.ep[ep_id][0].cmd_sts.toggle_mode  = 0;
+  _dcd.ep[ep_id][0].cmd_sts.rf_tv        = 0;
 }
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
 {
   //------------- Prepare Queue Head -------------//
   uint8_t ep_id = ep_addr2id(p_endpoint_desc->bEndpointAddress);
+  ep_cmd_sts_t* ep_cs = get_ep_cs(ep_id);
 
   // Check if endpoint is available
-  TU_ASSERT( _dcd.ep[ep_id][0].cmd_sts.disable && _dcd.ep[ep_id][1].cmd_sts.disable );
+  TU_ASSERT( ep_cs[0].cmd_sts.disable && ep_cs[1].cmd_sts.disable );
 
   edpt_reset(rhport, ep_id);
-  _dcd.ep[ep_id][0].cmd_sts.is_iso = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS);
+
+  switch (p_endpoint_desc->bmAttributes.xfer) {
+    case TUSB_XFER_ISOCHRONOUS:
+      ep_cs[0].cmd_sts.type = 1;
+      break;
+
+    case TUSB_XFER_INTERRUPT:
+      // What is interrupt endpoint in rate feedback mode ?
+      if ( rhport_is_highspeed(rhport) ) {
+        ep_cs[0].cmd_sts.type = 1;
+        ep_cs[0].cmd_sts.rf_tv = 1;
+      }
+      break;
+
+    case TUSB_XFER_BULK:
+      // nothing to do both type and rf_tv are 0
+      break;
+
+    default: break;
+  }
 
   // Enable EP interrupt
   dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs;
@@ -379,42 +419,50 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
   _dcd.ep[ep_id][0].cmd_sts.disable = _dcd.ep[ep_id][1].cmd_sts.disable = 1;
 }
 
-static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes)
-{
+static void prepare_ep_xfer(uint8_t rhport, uint8_t ep_id, uint16_t buf_offset, uint16_t total_bytes) {
   uint16_t nbytes;
+  ep_cmd_sts_t* ep_cs = get_ep_cs(ep_id);
 
-  if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL )
-  {
-    nbytes = tu_min16(total_bytes, _dcd.ep[ep_id][0].cmd_sts.is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
-    _dcd.ep[ep_id][0].buffer_fs.offset = buf_offset;
-    _dcd.ep[ep_id][0].buffer_fs.nbytes = nbytes;
-  }else
-  {
-    nbytes = tu_min16(total_bytes, NBYTES_CBI_HS_MAX);
-    _dcd.ep[ep_id][0].buffer_hs.offset = buf_offset;
-    _dcd.ep[ep_id][0].buffer_hs.nbytes = nbytes;
+  const bool is_iso = ep_is_iso(ep_cs, _dcd_controller[rhport].is_highspeed);
+
+  if ( rhport_is_highspeed(rhport) ) {
+    nbytes = tu_min16(total_bytes, is_iso ? NBYTES_ISO_HS_MAX : NBYTES_CBI_HS_MAX);
+    #if TU_CHECK_MCU(OPT_MCU_LPC54)
+    // LPC54 Errata USB.1: In USB high-speed device mode, the NBytes field does not decrement after BULK OUT transfer.
+    // Suggested Work-around: Program the NByte to the max packet size (512)
+    // Actual Work-around: round up NByte to multiple of 4.
+    // Note: this can cause buffer overflowed and corrupt data if host send more data than total_bytes
+    if ( (ep_id > 1) && (ep_id & 0x01) == 0 && ep_is_bulk(ep_cs) ) {
+      if ( nbytes & 0x03 ) {
+        nbytes = tu_align4(nbytes) + 4;
+      }
+    }
+    #endif
+
+    ep_cs[0].buffer_hs.offset = buf_offset;
+    ep_cs[0].buffer_hs.nbytes = nbytes;
+  }else {
+    nbytes = tu_min16(total_bytes, is_iso ? NBYTES_ISO_FS_MAX : NBYTES_CBI_FS_MAX);
+    ep_cs[0].buffer_fs.offset = buf_offset;
+    ep_cs[0].buffer_fs.nbytes = nbytes;
   }
 
   _dcd.dma[ep_id].nbytes = nbytes;
-
-  _dcd.ep[ep_id][0].cmd_sts.active = 1;
+  ep_cs[0].cmd_sts.active = 1;
 }
 
-bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
-{
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) {
   uint8_t const ep_id = ep_addr2id(ep_addr);
 
+  if (!buffer || total_bytes == 0) {
+    // Although having no data, ZLPs can cause buffer overwritten to zeroes. Probably due to USB/DMA controller side
+    // effect/bug. Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART
+    buffer = (uint8_t *) (uint32_t) dummy;
+  }
+
   tu_memclr(&_dcd.dma[ep_id], sizeof(xfer_dma_t));
   _dcd.dma[ep_id].total_bytes = total_bytes;
 
-  if (!buffer)
-  {
-    // Although having no data, ZLPs can cause buffer overwritten to zeroes.
-    // Probably due to USB/DMA controller side effect/bug.
-    // Assigned buffer offset to (valid) dummy to prevent overwriting to DATABUFSTART
-    buffer = (uint8_t*)(uint32_t)dummy;
-  }
-
   prepare_ep_xfer(rhport, ep_id, get_buf_offset(buffer), total_bytes);
 
   return true;
@@ -441,23 +489,19 @@ static void bus_reset(uint8_t rhport)
   dcd_reg->EPSKIP       = 0xFFFFFFFF;
 
   dcd_reg->INTSTAT      = dcd_reg->INTSTAT;                               // clear all pending interrupt
-  dcd_reg->DEVCMDSTAT  |= CMDSTAT_SETUP_RECEIVED_MASK;                    // clear setup received interrupt
+  dcd_reg->DEVCMDSTAT  |= DEVCMDSTAT_SETUP_RECEIVED_MASK;                    // clear setup received interrupt
   dcd_reg->INTEN        = INT_DEVICE_STATUS_MASK | TU_BIT(0) | TU_BIT(1); // enable device status & control endpoints
 }
 
-static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
-{
+static void process_xfer_isr(uint8_t rhport, uint32_t int_status) {
   uint8_t const max_ep = 2*_dcd_controller[rhport].ep_pairs;
 
-  for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ )
-  {
-    if ( tu_bit_test(int_status, ep_id) )
-    {
+  for(uint8_t ep_id = 0; ep_id < max_ep; ep_id++ ) {
+    if ( tu_bit_test(int_status, ep_id) ) {
       ep_cmd_sts_t * ep_cs = &_dcd.ep[ep_id][0];
       xfer_dma_t* xfer_dma = &_dcd.dma[ep_id];
 
-      if ( ep_id == 0 || ep_id == 1)
-      {
+      if ( ep_id <= 1 ) {
         // For control endpoint, we need to manually clear Active bit
         ep_cs->cmd_sts.active = 0;
       }
@@ -465,26 +509,29 @@ static void process_xfer_isr(uint8_t rhport, uint32_t int_status)
       uint16_t buf_offset;
       uint16_t buf_nbytes;
 
-      if (_dcd_controller[rhport].max_speed == TUSB_SPEED_FULL)
-      {
-        buf_offset = ep_cs->buffer_fs.offset;
-        buf_nbytes = ep_cs->buffer_fs.nbytes;
-      }else
-      {
+      if ( rhport_is_highspeed(rhport) ) {
         buf_offset = ep_cs->buffer_hs.offset;
         buf_nbytes = ep_cs->buffer_hs.nbytes;
+
+        #if TU_CHECK_MCU(OPT_MCU_LPC54)
+        // LPC54 Errata USB.2: In USB high-speed device mode, the NBytes field is not correct after BULK IN transfer
+        // There is no work-around. For EP in transfer, the NByte value can be ignored after a packet is transmitted.
+        if ( (ep_id > 1) && (ep_id & 0x01) == 1 && ep_is_bulk(ep_cs) ) {
+          buf_nbytes = 0;
+        }
+        #endif
+      } else {
+        buf_offset = ep_cs->buffer_fs.offset;
+        buf_nbytes = ep_cs->buffer_fs.nbytes;
       }
 
       xfer_dma->xferred_bytes += xfer_dma->nbytes - buf_nbytes;
 
-      if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) )
-      {
+      if ( (buf_nbytes == 0) && (xfer_dma->total_bytes > xfer_dma->xferred_bytes) ) {
         // There is more data to transfer
         // buff_offset has been already increased by hw to correct value for next transfer
         prepare_ep_xfer(rhport, ep_id, buf_offset, xfer_dma->total_bytes - xfer_dma->xferred_bytes);
-      }
-      else
-      {
+      } else {
         // for detecting ZLP
         xfer_dma->total_bytes = xfer_dma->xferred_bytes;
 
@@ -511,19 +558,16 @@ void dcd_int_handler(uint8_t rhport)
   //------------- Device Status -------------//
   if ( int_status & INT_DEVICE_STATUS_MASK )
   {
-    dcd_reg->DEVCMDSTAT |= CMDSTAT_RESET_CHANGE_MASK | CMDSTAT_CONNECT_CHANGE_MASK | CMDSTAT_SUSPEND_CHANGE_MASK;
+    dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK;
 
-    if ( cmd_stat & CMDSTAT_RESET_CHANGE_MASK) // bus reset
+    if ( cmd_stat & DEVCMDSTAT_RESET_CHANGE_MASK) // bus reset
     {
       bus_reset(rhport);
 
       tusb_speed_t speed = TUSB_SPEED_FULL;
-
-      if (_dcd_controller[rhport].max_speed == TUSB_SPEED_HIGH)
-      {
+      if ( _dcd_controller[rhport].is_highspeed ) {
         // 0 : reserved, 1 : full, 2 : high, 3: super
-        if ( 2 == ((cmd_stat >> CMDSTAT_SPEED_SHIFT) & 0x3UL) )
-        {
+        if ( 2 == ((cmd_stat >> DEVCMDSTAT_SPEED_SHIFT) & 0x3UL) ) {
           speed= TUSB_SPEED_HIGH;
         }
       }
@@ -531,35 +575,35 @@ void dcd_int_handler(uint8_t rhport)
       dcd_event_bus_reset(rhport, speed, true);
     }
 
-    if (cmd_stat & CMDSTAT_CONNECT_CHANGE_MASK)
+    if (cmd_stat & DEVCMDSTAT_CONNECT_CHANGE_MASK)
     {
       // device disconnect
-      if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      if (cmd_stat & DEVCMDSTAT_DEVICE_ADDR_MASK)
       {
         // debouncing as this can be set when device is powering
         dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
       }
     }
 
-    if (cmd_stat & CMDSTAT_SUSPEND_CHANGE_MASK)
+    if (cmd_stat & DEVCMDSTAT_SUSPEND_CHANGE_MASK)
     {
       // suspend signal, bus idle for more than 3ms
       // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
-      if (cmd_stat & CMDSTAT_DEVICE_ADDR_MASK)
+      if (cmd_stat & DEVCMDSTAT_DEVICE_ADDR_MASK)
       {
-        dcd_event_bus_signal(rhport, (cmd_stat & CMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true);
+        dcd_event_bus_signal(rhport, (cmd_stat & DEVCMDSTAT_DEVICE_SUSPEND_MASK) ? DCD_EVENT_SUSPEND : DCD_EVENT_RESUME, true);
       }
     }
   }
 
   // Setup Receive
-  if ( tu_bit_test(int_status, 0) && (cmd_stat & CMDSTAT_SETUP_RECEIVED_MASK) )
+  if ( tu_bit_test(int_status, 0) && (cmd_stat & DEVCMDSTAT_SETUP_RECEIVED_MASK) )
   {
     // Follow UM flowchart to clear Active & Stall on both Control IN/OUT endpoints
     _dcd.ep[0][0].cmd_sts.active = _dcd.ep[1][0].cmd_sts.active = 0;
     _dcd.ep[0][0].cmd_sts.stall = _dcd.ep[1][0].cmd_sts.stall = 0;
 
-    dcd_reg->DEVCMDSTAT |= CMDSTAT_SETUP_RECEIVED_MASK;
+    dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_SETUP_RECEIVED_MASK;
 
     dcd_event_setup_received(rhport, _dcd.setup_packet, true);
 

From 1268d1a0937a1a7c9d7b20b17581a82f233d066d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Aug 2023 18:46:23 +0700
Subject: [PATCH 1990/2085] update hil test and json (remove troublesome
 lpc54608), run hil test on ci with IAR build

---
 .github/workflows/build_iar.yml               | 149 +++++++++---------
 .idea/cmake.xml                               |   1 -
 examples/device/CMakeLists.txt                |   1 +
 .../lpc55/boards/lpcxpresso55s69/board.cmake  |   2 +-
 test/hitl/hitl_hfp.json                       |  84 +---------
 test/hitl/hitl_test.py                        |  84 +++++++---
 6 files changed, 146 insertions(+), 175 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 454ad12fe..a62e62b79 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -32,7 +32,7 @@ jobs:
           # Alphabetical order
           # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
           # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
-          - 'stm32f0 stm32f1 stm32f7 stm32g0 stm32g4 stm32h7 stm32l4'
+          - 'stm32f0 stm32f1 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l4'
     steps:
       - name: Clean workspace
         run: |
@@ -49,82 +49,85 @@ jobs:
       - name: Build
         run: python3 tools/build_cmake.py ${{ matrix.family }} -DTOOLCHAIN=iar -DCMAKE_BUILD_TYPE=MinSizeRel
 
-      # Upload binaries for hardware test with self-hosted
-      - name: Prepare stm32l412nucleo Artifacts
-        if: contains(matrix.family, 'stm32l4')
-        working-directory: ${{github.workspace}}/cmake-build/cmake-build-stm32l412nucleo
+      - name: Test on actual hardware (hardware in the loop)
         run: |
-          find device/ -name "*.elf" -exec mv {} ../../ \;
+          python3 tools/hitl_test.py hitl_hfp.json
 
-      - name: Upload Artifacts for stm32l412nucleo
-        if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach'
-        uses: actions/upload-artifact@v3
-        with:
-          name: stm32l4
-          path: |
-            *.elf
+#      # Upload binaries for hardware test with self-hosted
+#      - name: Prepare stm32l412nucleo Artifacts
+#        if: contains(matrix.family, 'stm32l4')
+#        working-directory: ${{github.workspace}}/cmake-build/cmake-build-stm32l412nucleo
+#        run: |
+#          find device/ -name "*.elf" -exec mv {} ../../ \;
+#
+#      - name: Upload Artifacts for stm32l412nucleo
+#        if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach'
+#        uses: actions/upload-artifact@v3
+#        with:
+#          name: stm32l4
+#          path: |
+#            *.elf
 
   # ---------------------------------------
   # Hardware in the loop (HIL)
   # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
-  # - STM32L412 Nucleo with on-board jlink as ttyACM0
   # ---------------------------------------
-  hw-stm32l412nucleo-test:
-    needs: cmake
-    runs-on: [self-hosted, Linux, X64, hifiphile]
-
-    steps:
-      - name: Clean workspace
-        run: |
-          echo "Cleaning up previous run"
-          rm -rf "${{ github.workspace }}"
-          mkdir -p "${{ github.workspace }}"
-
-      - name: Download stm32l4 Artifacts
-        uses: actions/download-artifact@v3
-        with:
-          name: stm32l4
-
-      - name: Create flash.sh
-        run: |
-          echo > flash.sh 'echo halt > flash.jlink'
-          echo >> flash.sh 'echo r >> flash.jlink'
-          echo >> flash.sh 'echo loadfile $1 >> flash.jlink'
-          echo >> flash.sh 'echo r >> flash.jlink'
-          echo >> flash.sh 'echo go >> flash.jlink'
-          echo >> flash.sh 'echo exit >> flash.jlink'
-          echo >> flash.sh 'cmdout=$(JLinkExe -USB 774470029 -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
-          echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
-          chmod +x flash.sh
-
-      - name: Test cdc_dual_ports
-        run: |
-          ./flash.sh cdc_dual_ports.elf
-          while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
-          test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-          test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-
-        # Debian does not auto mount usb drive. skip this test for now
-      - name: Test cdc_msc
-        if: false
-        run: |
-          ./flash.sh cdc_msc.elf
-          readme='/media/pi/TinyUSB MSC/README.TXT'
-          while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
-          test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-          test -f "$readme" && echo "$readme exists"
-          cat "$readme"
-
-      - name: Test dfu
-        run: |
-          ./flash.sh dfu.elf
-          while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
-          dfu-util -d cafe -a 0 -U dfu0
-          dfu-util -d cafe -a 1 -U dfu1
-          grep "TinyUSB DFU! - Partition 0" dfu0
-          grep "TinyUSB DFU! - Partition 1" dfu1
-
-      - name: Test dfu_runtime
-        run: |
-          ./flash.sh dfu_runtime.elf
-          while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
+#  hw-stm32l412nucleo-test:
+#    needs: cmake
+#    runs-on: [self-hosted, Linux, X64, hifiphile]
+#
+#    steps:
+#      - name: Clean workspace
+#        run: |
+#          echo "Cleaning up previous run"
+#          rm -rf "${{ github.workspace }}"
+#          mkdir -p "${{ github.workspace }}"
+#
+#      - name: Download stm32l4 Artifacts
+#        uses: actions/download-artifact@v3
+#        with:
+#          name: stm32l4
+#
+#      - name: Create flash.sh
+#        run: |
+#          echo > flash.sh 'echo halt > flash.jlink'
+#          echo >> flash.sh 'echo r >> flash.jlink'
+#          echo >> flash.sh 'echo loadfile $1 >> flash.jlink'
+#          echo >> flash.sh 'echo r >> flash.jlink'
+#          echo >> flash.sh 'echo go >> flash.jlink'
+#          echo >> flash.sh 'echo exit >> flash.jlink'
+#          echo >> flash.sh 'cmdout=$(JLinkExe -USB 774470029 -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
+#          echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
+#          chmod +x flash.sh
+#
+#      - name: Test cdc_dual_ports
+#        run: |
+#          ./flash.sh cdc_dual_ports.elf
+#          while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
+#          test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+#          test -e /dev/ttyACM2 && echo "ttyACM2 exists"
+#
+#        # Debian does not auto mount usb drive. skip this test for now
+#      - name: Test cdc_msc
+#        if: false
+#        run: |
+#          ./flash.sh cdc_msc.elf
+#          readme='/media/pi/TinyUSB MSC/README.TXT'
+#          while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
+#          test -e /dev/ttyACM1 && echo "ttyACM1 exists"
+#          test -f "$readme" && echo "$readme exists"
+#          cat "$readme"
+#
+#      - name: Test dfu
+#        run: |
+#          ./flash.sh dfu.elf
+#          while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
+#          dfu-util -d cafe -a 0 -U dfu0
+#          dfu-util -d cafe -a 1 -U dfu1
+#          grep "TinyUSB DFU! - Partition 0" dfu0
+#          grep "TinyUSB DFU! - Partition 1" dfu1
+#
+#      - name: Test dfu_runtime
+#        run: |
+#          ./flash.sh dfu_runtime.elf
+#          while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 4a69d02cf..8ee7f09a0 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -52,7 +52,6 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
-      <configuration PROFILE_NAME="lpc54628 PORT0" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT -DPORT=0" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/examples/device/CMakeLists.txt b/examples/device/CMakeLists.txt
index f590fff3f..0a2e49ef0 100644
--- a/examples/device/CMakeLists.txt
+++ b/examples/device/CMakeLists.txt
@@ -17,6 +17,7 @@ family_add_subdirectory(cdc_uac2)
 family_add_subdirectory(dfu)
 family_add_subdirectory(dfu_runtime)
 family_add_subdirectory(dynamic_configuration)
+family_add_subdirectory(hid_boot_interface)
 family_add_subdirectory(hid_composite)
 family_add_subdirectory(hid_composite_freertos)
 family_add_subdirectory(hid_generic_inout)
diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
index 3af6034ad..b52ec2f9d 100644
--- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
+++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake
@@ -1,7 +1,7 @@
 set(MCU_VARIANT LPC55S69)
 set(MCU_CORE LPC55S69_cm33_core0)
 
-set(JLINK_DEVICE LPC55S69)
+set(JLINK_DEVICE LPC55S69_M33_0)
 set(PYOCD_TARGET LPC55S69)
 set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
 
diff --git a/test/hitl/hitl_hfp.json b/test/hitl/hitl_hfp.json
index 866e5233f..7912af245 100644
--- a/test/hitl/hitl_hfp.json
+++ b/test/hitl/hitl_hfp.json
@@ -1,92 +1,18 @@
 {
-    "devices": [
+    "boards": [
         {
+            "name": "stm32l412nucleo",
             "uid": "41003B000E504E5457323020",
             "debugger": "jlink",
             "debugger_sn": "774470029",
-            "device": "STM32L412KB",
-            "tests": [
-                {
-                    "name": "cdc_dual_ports",
-                    "firmware": "examples/device/cdc_dual_ports/_build/stm32l412nucleo/cdc_dual_ports.elf"
-                },
-                {
-                    "name": "cdc_msc",
-                    "firmware": "examples/device/cdc_msc/_build/stm32l412nucleo/cdc_msc.elf"
-                },
-                {
-                    "name": "dfu",
-                    "firmware": "examples/device/dfu/_build/stm32l412nucleo/dfu.elf"
-                },
-                {
-                    "name": "dfu_runtime",
-                    "firmware": "examples/device/dfu_runtime/_build/stm32l412nucleo/dfu_runtime.elf"
-                },
-                {
-                    "name": "hid_boot_interface",
-                    "firmware": "examples/device/hid_boot_interface/_build/stm32l412nucleo/hid_boot_interface.elf"
-                },
-                {
-                    "name": "board_test",
-                    "firmware": "examples/device/board_test/_build/stm32l412nucleo/board_test.elf"
-                }
-            ]
+            "cpu": "STM32L412KB"
         },
         {
+            "name": "stm32f746disco",
             "uid": "210041000C51343237303334",
             "debugger": "jlink",
             "debugger_sn": "770935966",
-            "device": "STM32F746NG",
-            "tests": [
-                {
-                    "name": "cdc_dual_ports",
-                    "firmware": "examples/device/cdc_dual_ports/_build/stm32f746disco/cdc_dual_ports.elf"
-                },
-                {
-                    "name": "cdc_msc",
-                    "firmware": "examples/device/cdc_msc/_build/stm32f746disco/cdc_msc.elf"
-                },
-                {
-                    "name": "dfu",
-                    "firmware": "examples/device/dfu/_build/stm32f746disco/dfu.elf"
-                },
-                {
-                    "name": "dfu_runtime",
-                    "firmware": "examples/device/dfu_runtime/_build/stm32f746disco/dfu_runtime.elf"
-                },
-                {
-                    "name": "hid_boot_interface",
-                    "firmware": "examples/device/hid_boot_interface/_build/stm32f746disco/hid_boot_interface.elf"
-                },
-                {
-                    "name": "board_test",
-                    "firmware": "examples/device/board_test/_build/stm32f746disco/board_test.elf"
-                }
-            ]
-        },
-        {
-            "uid": "0123456789ABCDEF",
-            "debugger": "jlink",
-            "debugger_sn": "727600775",
-            "device": "LPC54608J512",
-            "tests": [
-                {
-                    "name": "cdc_dual_ports",
-                    "firmware": "examples/device/cdc_dual_ports/_build/lpcxpresso54628/cdc_dual_ports.elf"
-                },
-                {
-                    "name": "dfu",
-                    "firmware": "examples/device/dfu/_build/lpcxpresso54628/dfu.elf"
-                },
-                {
-                    "name": "dfu_runtime",
-                    "firmware": "examples/device/dfu_runtime/_build/lpcxpresso54628/dfu_runtime.elf"
-                },
-                {
-                    "name": "board_test",
-                    "firmware": "examples/device/board_test/_build/lpcxpresso54628/board_test.elf"
-                }
-            ]
+            "cpu": "STM32F746NG"
         }
     ]
 }
diff --git a/test/hitl/hitl_test.py b/test/hitl/hitl_test.py
index 695c6a28c..6bcde36c6 100644
--- a/test/hitl/hitl_test.py
+++ b/test/hitl/hitl_test.py
@@ -32,6 +32,21 @@ import serial
 import subprocess
 import json
 
+
+def get_serial_dev(id, product, ifnum):
+    # get usb serial by id
+    return f'/dev/serial/by-id/usb-TinyUSB_{product}_{id}-if{ifnum:02d}'
+
+
+def get_disk_dev(id, lun):
+    # get usb disk by id
+    return f'/dev/disk/by-id/usb-TinyUSB_Mass_Storage_{id}-0:{lun}'
+
+
+def get_hid_dev(id, product, event):
+    return f'/dev/input/by-id/usb-TinyUSB_{product}_{id}-{event}'
+
+
 def flash_jlink(sn, dev, firmware):
     script = ['halt', 'r', f'loadfile {firmware}', 'r', 'go', 'exit']
     f = open('flash.jlink', 'w')
@@ -43,9 +58,15 @@ def flash_jlink(sn, dev, firmware):
     os.remove('flash.jlink')
     assert ret.returncode == 0, 'Flash failed\n' + stdout
 
+
+def test_board_test(id):
+    # Dummy test
+    pass
+
 def test_cdc_dual_ports(id):
-    port1 = f'/dev/ttyUSB_{id[-8:]}.00'
-    port2 = f'/dev/ttyUSB_{id[-8:]}.02'
+    port1 = get_serial_dev(id, "TinyUSB_Device", 0)
+    port2 = get_serial_dev(id, "TinyUSB_Device", 2)
+
     # Wait device enum
     timeout = 10
     while timeout:
@@ -75,10 +96,9 @@ def test_cdc_dual_ports(id):
     assert ser1.read(100) == str2.lower(), 'Port1 wrong data'
     assert ser2.read(100) == str2.upper(), 'Port2 wrong data'
 
-    print('cdc_dual_ports test done')
 
 def test_cdc_msc(id):
-    port  = f'/dev/ttyUSB_{id[-8:]}.00'
+    port = get_serial_dev(id, "TinyUSB_Device", 0)
     file = f'/media/blkUSB_{id[-8:]}.02/README.TXT'
     # Wait device enum
     timeout = 10
@@ -110,7 +130,6 @@ If you find any bugs or get any questions, feel free to file an\r\n\
 issue at github.com/hathach/tinyusb"
 
     assert data == readme, 'MSC wrong data'
-    print('cdc_msc test done')
 
 def test_dfu(id):
     # Wait device enum
@@ -150,7 +169,6 @@ def test_dfu(id):
     os.remove('dfu0')
     os.remove('dfu1')
 
-    print('dfu test done')
 
 def test_dfu_runtime(id):
     # Wait device enum
@@ -166,12 +184,11 @@ def test_dfu_runtime(id):
 
     assert timeout, 'Device not available'
 
-    print('dfu_runtime test done')
 
 def test_hid_boot_interface(id):
-    kbd  = f'/dev/input/by-id/usb-TinyUSB_TinyUSB_Device_{id}-event-kbd'
-    mouse1  = f'/dev/input/by-id/usb-TinyUSB_TinyUSB_Device_{id}-if01-event-mouse'
-    mouse2  = f'/dev/input/by-id/usb-TinyUSB_TinyUSB_Device_{id}-if01-mouse'
+    kbd = get_hid_dev(id, 'TinyUSB_Device', 'event-kbd')
+    mouse1 = get_hid_dev(id, 'TinyUSB_Device', 'if01-event-mouse')
+    mouse2 = get_hid_dev(id, 'TinyUSB_Device', 'if01-mouse')
     # Wait device enum
     timeout = 10
     while timeout:
@@ -182,11 +199,6 @@ def test_hid_boot_interface(id):
 
     assert timeout, 'Device not available'
 
-    print('hid_boot_interface test done')
-
-def test_board_test(id):
-    # Dummy test
-    pass
 
 if __name__ == '__main__':
     if len(sys.argv) != 2:
@@ -197,12 +209,42 @@ if __name__ == '__main__':
     with open(f'{os.path.dirname(__file__)}/{sys.argv[1]}') as f:
         config = json.load(f)
 
-    for device in config['devices']:
-        print(f"Testing device:{device['device']}")
-        for test in device['tests']:
-            if device['debugger'].lower() == 'jlink':
-                flash_jlink(device['debugger_sn'], device['device'], test['firmware'])
+    # all possible tests, board_test is last to disable board's usb
+    all_tests = [
+        'cdc_dual_ports', 'cdc_msc', 'dfu', 'dfu_runtime', 'hid_boot_interface', 'board_test'
+    ]
+
+    for board in config['boards']:
+        print(f'Testing board:{board["name"]}')
+
+        # default to all tests
+        if 'tests' in board:
+            test_list = board['tests']
+        else:
+            test_list = all_tests
+
+        # remove skip_tests
+        if 'tests_skip' in board:
+            for skip in board['tests_skip']:
+                if skip in test_list:
+                    test_list.remove(skip)
+
+        for test in test_list:
+            mk_elf = f'examples/device/{test}/_build/{board["name"]}/{test}.elf'
+            cmake_elf = f'cmake-build/cmake-build-{board["name"]}/device/{test}/{test}.elf'
+            if os.path.isfile(cmake_elf):
+                elf = cmake_elf
+            elif os.path.isfile(mk_elf):
+                elf = mk_elf
+            else:
+                print(f'Cannot find firmware file for {test}')
+                sys.exit(-1)
+
+            if board['debugger'].lower() == 'jlink':
+                flash_jlink(board['debugger_sn'], board['cpu'], elf)
             else:
                 # ToDo
                 pass
-            locals()[f'test_{test["name"]}'](device['uid'])
+            print(f'  {test} ...', end='')
+            locals()[f'test_{test}'](board['uid'])
+            print('OK')

From 8e690df1da3b542988b9ec093f3ce03c8cfd9248 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 9 Aug 2023 19:03:56 +0700
Subject: [PATCH 1991/2085] rename hitl to hil

---
 .github/workflows/build_iar.yml               | 2 +-
 test/{hitl/hitl_hfp.json => hil/hil_hfp.json} | 0
 test/{hitl/hitl_test.py => hil/hil_test.py}   | 0
 3 files changed, 1 insertion(+), 1 deletion(-)
 rename test/{hitl/hitl_hfp.json => hil/hil_hfp.json} (100%)
 rename test/{hitl/hitl_test.py => hil/hil_test.py} (100%)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index a62e62b79..48fdd6a8a 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -51,7 +51,7 @@ jobs:
 
       - name: Test on actual hardware (hardware in the loop)
         run: |
-          python3 tools/hitl_test.py hitl_hfp.json
+          python3 test/hil/hil_test.py hil_hfp.json
 
 #      # Upload binaries for hardware test with self-hosted
 #      - name: Prepare stm32l412nucleo Artifacts
diff --git a/test/hitl/hitl_hfp.json b/test/hil/hil_hfp.json
similarity index 100%
rename from test/hitl/hitl_hfp.json
rename to test/hil/hil_hfp.json
diff --git a/test/hitl/hitl_test.py b/test/hil/hil_test.py
similarity index 100%
rename from test/hitl/hitl_test.py
rename to test/hil/hil_test.py

From 202b945f88f104fda48104f40cad2525079ff5b1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 14 Aug 2023 16:38:51 +0700
Subject: [PATCH 1992/2085] add lpcxpresso43s67

---
 hw/bsp/lpc18/boards/lpcxpresso18s37/board.h   |   1 +
 hw/bsp/lpc43/boards/ea4357/board.h            |  45 ++
 .../lpc43/boards/lpcxpresso43s67/board.cmake  |  11 +
 hw/bsp/lpc43/boards/lpcxpresso43s67/board.h   |  73 ++++
 hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk  |   6 +
 .../lpc43/boards/lpcxpresso43s67/lpc4367.ld   | 402 ++++++++++++++++++
 hw/bsp/lpc43/family.c                         | 118 ++---
 7 files changed, 573 insertions(+), 83 deletions(-)
 create mode 100644 hw/bsp/lpc43/boards/lpcxpresso43s67/board.cmake
 create mode 100644 hw/bsp/lpc43/boards/lpcxpresso43s67/board.h
 create mode 100644 hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk
 create mode 100644 hw/bsp/lpc43/boards/lpcxpresso43s67/lpc4367.ld

diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h
index b3a7bc44f..f4c85ddc9 100644
--- a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h
+++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h
@@ -62,6 +62,7 @@ static inline void board_lpc18_pinmux(void)
     // USB0
     //{ 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 },		                // P6_3 USB0_PWR_EN, USB0 VBus function
 
+    // USB1
     //{ 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 },			              // P9_5 USB1_VBUS_EN, USB1 VBus function
     //{ 0x2, 5, SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
     {0x2, 5, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4 },
diff --git a/hw/bsp/lpc43/boards/ea4357/board.h b/hw/bsp/lpc43/boards/ea4357/board.h
index f026324ef..fb52e32a7 100644
--- a/hw/bsp/lpc43/boards/ea4357/board.h
+++ b/hw/bsp/lpc43/boards/ea4357/board.h
@@ -33,6 +33,51 @@ extern "C" {
 
 #include "pca9532.h"
 
+// P9_1 joystick down
+#define BUTTON_PORT     4
+#define BUTTON_PIN      13
+#define BUTTON_STATE_ACTIVE   0
+
+#define UART_DEV        LPC_USART0
+#define UART_PORT       0x0f
+#define UART_PIN_TX     10
+#define UART_PIN_RX     11
+
+//static const struct {
+//  uint8_t mux_port;
+//  uint8_t mux_pin;
+//
+//  uint8_t gpio_port;
+//  uint8_t gpio_pin;
+//}buttons[] =
+//{
+//    {0x0a, 3, 4, 10 }, // Joystick up
+//    {0x09, 1, 4, 13 }, // Joystick down
+//    {0x0a, 2, 4, 9  }, // Joystick left
+//    {0x09, 0, 4, 12 }, // Joystick right
+//    {0x0a, 1, 4, 8  }, // Joystick press
+//    {0x02, 7, 0, 7  }, // SW6
+//};
+
+static const PINMUX_GRP_T pinmuxing[] = {
+    // Button ( Joystick down )
+    { 0x9, 1, SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP },
+
+    // UART
+    { UART_PORT, UART_PIN_TX, SCU_MODE_PULLDOWN | SCU_MODE_FUNC1 },
+    { UART_PORT, UART_PIN_RX, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1 },
+
+    // USB
+};
+
+/* Pin clock mux values, re-used structure, value in first index is meaningless */
+//static const PINMUX_GRP_T pinclockmuxing[] = {
+//    { 0, 0, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0 },
+//    { 0, 1, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0 },
+//    { 0, 2, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0 },
+//    { 0, 3, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0 },
+//};
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.cmake b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.cmake
new file mode 100644
index 000000000..0858a97d5
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.cmake
@@ -0,0 +1,11 @@
+set(MCU_VARIANT LPC43S67_M4)
+
+set(JLINK_DEVICE LPC43S67_M4)
+set(PYOCD_TARGET LPC43S67)
+set(NXPLINK_DEVICE LPC43S67:LPCXPRESSO43S67)
+
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc4367.ld)
+
+function(update_board TARGET)
+  # nothing to do
+endfunction()
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h
new file mode 100644
index 000000000..4dd90fe29
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h
@@ -0,0 +1,73 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_LPCXPRESSO43S67_H_
+#define _BOARD_LPCXPRESSO43S67_H_
+
+// Note: For USB Host demo, install JP4
+// WARNING: don't install JP4 when running as device
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// LED Red
+#define LED_PORT      3
+#define LED_PIN       7
+#define LED_STATE_ON  0
+
+// ISP Button (SW2)
+#define BUTTON_PORT   0
+#define BUTTON_PIN    7
+#define BUTTON_STATE_ACTIVE   0
+
+#define UART_DEV      LPC_USART0
+
+static const PINMUX_GRP_T pinmuxing[] = {
+    // LEDs P6_11 as GPIO3[7]
+    { 0x6, 11, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0 },
+
+    // Button P2_7 as GPIO0[7]
+    { 0x2, 7, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0 },
+
+    // UART
+    { 0x06, 4, SCU_MODE_PULLDOWN | SCU_MODE_FUNC2 },
+    { 0x02, 1, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1 },
+
+    // USB0
+    //{ 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 },		                // P6_3 USB0_PWR_EN, USB0 VBus function
+
+    // USB 1
+    //{ 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 },			              // P9_5 USB1_VBUS_EN, USB1 VBus function
+    //{ 0x2, 5, SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
+    {0x2, 5, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4 },
+};
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk
new file mode 100644
index 000000000..eeb02e311
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.mk
@@ -0,0 +1,6 @@
+LD_FILE = $(BOARD_PATH)/lpc4367.ld
+
+# For flash-jlink target
+JLINK_DEVICE = LPC43S67_M4
+
+flash: flash-jlink
diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/lpc4367.ld b/hw/bsp/lpc43/boards/lpcxpresso43s67/lpc4367.ld
new file mode 100644
index 000000000..c03149b8b
--- /dev/null
+++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/lpc4367.ld
@@ -0,0 +1,402 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * Copyright (c) 2008-2013 Code Red Technologies Ltd,
+ * Copyright 2015, 2018-2019 NXP
+ * (c) NXP Semiconductors 2013-2023
+ * Generated linker script file for LPC4337
+ * Created from linkscript.ldt by FMCreateLinkLibraries
+ * Using Freemarker v2.3.30
+ * MCUXpresso IDE v11.7.1 [Build 9221] [2023-03-28] on Aug 14, 2023, 3:36:29 PM
+ */
+
+MEMORY
+{
+  /* Define each memory region */
+  MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
+  MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
+  RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
+  RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
+  RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
+  RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
+  RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
+}
+
+  /* Define a symbol for the top of each memory region */
+  __base_MFlashA512 = 0x1a000000  ; /* MFlashA512 */
+  __base_Flash = 0x1a000000 ; /* Flash */
+  __top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
+  __top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
+  __base_MFlashB512 = 0x1b000000  ; /* MFlashB512 */
+  __base_Flash2 = 0x1b000000 ; /* Flash2 */
+  __top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+  __top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
+  __base_RamLoc32 = 0x10000000  ; /* RamLoc32 */
+  __base_RAM = 0x10000000 ; /* RAM */
+  __top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
+  __base_RamLoc40 = 0x10080000  ; /* RamLoc40 */
+  __base_RAM2 = 0x10080000 ; /* RAM2 */
+  __top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
+  __top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
+  __base_RamAHB32 = 0x20000000  ; /* RamAHB32 */
+  __base_RAM3 = 0x20000000 ; /* RAM3 */
+  __top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
+  __base_RamAHB16 = 0x20008000  ; /* RamAHB16 */
+  __base_RAM4 = 0x20008000 ; /* RAM4 */
+  __top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
+  __base_RamAHB_ETB16 = 0x2000c000  ; /* RamAHB_ETB16 */
+  __base_RAM5 = 0x2000c000 ; /* RAM5 */
+  __top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+  __top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+     .text_Flash2 : ALIGN(4)
+    {
+       FILL(0xff)
+        *(.text_Flash2) /* for compatibility with previous releases */
+        *(.text_MFlashB512) /* for compatibility with previous releases */
+        *(.text.$Flash2)
+        *(.text.$MFlashB512)
+        *(.text_Flash2.*) /* for compatibility with previous releases */
+        *(.text_MFlashB512.*) /* for compatibility with previous releases */
+        *(.text.$Flash2.*)
+        *(.text.$MFlashB512.*)
+        *(.rodata.$Flash2)
+        *(.rodata.$MFlashB512)
+        *(.rodata.$Flash2.*)
+        *(.rodata.$MFlashB512.*)            } > MFlashB512
+
+    /* MAIN TEXT SECTION */
+    .text : ALIGN(4)
+    {
+        FILL(0xff)
+        __vectors_start__ = ABSOLUTE(.) ;
+        KEEP(*(.isr_vector))
+        /* Global Section Table */
+        . = ALIGN(4) ;
+        __section_table_start = .;
+        __data_section_table = .;
+        LONG(LOADADDR(.data));
+        LONG(    ADDR(.data));
+        LONG(  SIZEOF(.data));
+        LONG(LOADADDR(.data_RAM2));
+        LONG(    ADDR(.data_RAM2));
+        LONG(  SIZEOF(.data_RAM2));
+        LONG(LOADADDR(.data_RAM3));
+        LONG(    ADDR(.data_RAM3));
+        LONG(  SIZEOF(.data_RAM3));
+        LONG(LOADADDR(.data_RAM4));
+        LONG(    ADDR(.data_RAM4));
+        LONG(  SIZEOF(.data_RAM4));
+        LONG(LOADADDR(.data_RAM5));
+        LONG(    ADDR(.data_RAM5));
+        LONG(  SIZEOF(.data_RAM5));
+        __data_section_table_end = .;
+        __bss_section_table = .;
+        LONG(    ADDR(.bss));
+        LONG(  SIZEOF(.bss));
+        LONG(    ADDR(.bss_RAM2));
+        LONG(  SIZEOF(.bss_RAM2));
+        LONG(    ADDR(.bss_RAM3));
+        LONG(  SIZEOF(.bss_RAM3));
+        LONG(    ADDR(.bss_RAM4));
+        LONG(  SIZEOF(.bss_RAM4));
+        LONG(    ADDR(.bss_RAM5));
+        LONG(  SIZEOF(.bss_RAM5));
+        __bss_section_table_end = .;
+        __section_table_end = . ;
+        /* End of Global Section Table */
+
+        *(.after_vectors*)
+
+       *(.text*)
+       *(.rodata .rodata.* .constdata .constdata.*)
+       . = ALIGN(4);
+    } > MFlashA512
+    /*
+     * for exception handling/unwind - some Newlib functions (in common
+     * with C++ and STDC++) use this.
+     */
+    .ARM.extab : ALIGN(4)
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > MFlashA512
+
+    .ARM.exidx : ALIGN(4)
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > MFlashA512
+
+    _etext = .;
+
+    /* DATA section for RamLoc40 */
+
+    .data_RAM2 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM2 = .) ;
+        PROVIDE(__start_data_RamLoc40 = .) ;
+        *(.ramfunc.$RAM2)
+        *(.ramfunc.$RamLoc40)
+        *(.data.$RAM2)
+        *(.data.$RamLoc40)
+        *(.data.$RAM2.*)
+        *(.data.$RamLoc40.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM2 = .) ;
+        PROVIDE(__end_data_RamLoc40 = .) ;
+     } > RamLoc40 AT>MFlashA512
+
+    /* DATA section for RamAHB32 */
+
+    .data_RAM3 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM3 = .) ;
+        PROVIDE(__start_data_RamAHB32 = .) ;
+        *(.ramfunc.$RAM3)
+        *(.ramfunc.$RamAHB32)
+        *(.data.$RAM3)
+        *(.data.$RamAHB32)
+        *(.data.$RAM3.*)
+        *(.data.$RamAHB32.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM3 = .) ;
+        PROVIDE(__end_data_RamAHB32 = .) ;
+     } > RamAHB32 AT>MFlashA512
+
+    /* DATA section for RamAHB16 */
+
+    .data_RAM4 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM4 = .) ;
+        PROVIDE(__start_data_RamAHB16 = .) ;
+        *(.ramfunc.$RAM4)
+        *(.ramfunc.$RamAHB16)
+        *(.data.$RAM4)
+        *(.data.$RamAHB16)
+        *(.data.$RAM4.*)
+        *(.data.$RamAHB16.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM4 = .) ;
+        PROVIDE(__end_data_RamAHB16 = .) ;
+     } > RamAHB16 AT>MFlashA512
+
+    /* DATA section for RamAHB_ETB16 */
+
+    .data_RAM5 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM5 = .) ;
+        PROVIDE(__start_data_RamAHB_ETB16 = .) ;
+        *(.ramfunc.$RAM5)
+        *(.ramfunc.$RamAHB_ETB16)
+        *(.data.$RAM5)
+        *(.data.$RamAHB_ETB16)
+        *(.data.$RAM5.*)
+        *(.data.$RamAHB_ETB16.*)
+        . = ALIGN(4) ;
+        PROVIDE(__end_data_RAM5 = .) ;
+        PROVIDE(__end_data_RamAHB_ETB16 = .) ;
+     } > RamAHB_ETB16 AT>MFlashA512
+
+    /* MAIN DATA SECTION */
+    .uninit_RESERVED (NOLOAD) : ALIGN(4)
+    {
+        _start_uninit_RESERVED = .;
+        KEEP(*(.bss.$RESERVED*))
+       . = ALIGN(4) ;
+        _end_uninit_RESERVED = .;
+    } > RamLoc32 AT> RamLoc32
+
+    /* Main DATA section (RamLoc32) */
+    .data : ALIGN(4)
+    {
+       FILL(0xff)
+       _data = . ;
+       PROVIDE(__start_data_RAM = .) ;
+       PROVIDE(__start_data_RamLoc32 = .) ;
+       *(vtable)
+       *(.ramfunc*)
+       KEEP(*(CodeQuickAccess))
+       KEEP(*(DataQuickAccess))
+       *(RamFunction)
+       *(.data*)
+       . = ALIGN(4) ;
+       _edata = . ;
+       PROVIDE(__end_data_RAM = .) ;
+       PROVIDE(__end_data_RamLoc32 = .) ;
+    } > RamLoc32 AT>MFlashA512
+
+    /* BSS section for RamLoc40 */
+    .bss_RAM2 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM2 = .) ;
+       PROVIDE(__start_bss_RamLoc40 = .) ;
+       *(.bss.$RAM2)
+       *(.bss.$RamLoc40)
+       *(.bss.$RAM2.*)
+       *(.bss.$RamLoc40.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM2 = .) ;
+       PROVIDE(__end_bss_RamLoc40 = .) ;
+    } > RamLoc40 AT> RamLoc40
+
+    /* BSS section for RamAHB32 */
+    .bss_RAM3 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM3 = .) ;
+       PROVIDE(__start_bss_RamAHB32 = .) ;
+       *(.bss.$RAM3)
+       *(.bss.$RamAHB32)
+       *(.bss.$RAM3.*)
+       *(.bss.$RamAHB32.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM3 = .) ;
+       PROVIDE(__end_bss_RamAHB32 = .) ;
+    } > RamAHB32 AT> RamAHB32
+
+    /* BSS section for RamAHB16 */
+    .bss_RAM4 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM4 = .) ;
+       PROVIDE(__start_bss_RamAHB16 = .) ;
+       *(.bss.$RAM4)
+       *(.bss.$RamAHB16)
+       *(.bss.$RAM4.*)
+       *(.bss.$RamAHB16.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM4 = .) ;
+       PROVIDE(__end_bss_RamAHB16 = .) ;
+    } > RamAHB16 AT> RamAHB16
+
+    /* BSS section for RamAHB_ETB16 */
+    .bss_RAM5 : ALIGN(4)
+    {
+       PROVIDE(__start_bss_RAM5 = .) ;
+       PROVIDE(__start_bss_RamAHB_ETB16 = .) ;
+       *(.bss.$RAM5)
+       *(.bss.$RamAHB_ETB16)
+       *(.bss.$RAM5.*)
+       *(.bss.$RamAHB_ETB16.*)
+       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
+       PROVIDE(__end_bss_RAM5 = .) ;
+       PROVIDE(__end_bss_RamAHB_ETB16 = .) ;
+    } > RamAHB_ETB16 AT> RamAHB_ETB16
+
+    /* MAIN BSS SECTION */
+    .bss : ALIGN(4)
+    {
+        _bss = .;
+        PROVIDE(__start_bss_RAM = .) ;
+        PROVIDE(__start_bss_RamLoc32 = .) ;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4) ;
+        _ebss = .;
+        PROVIDE(__end_bss_RAM = .) ;
+        PROVIDE(__end_bss_RamLoc32 = .) ;
+        PROVIDE(end = .);
+    } > RamLoc32 AT> RamLoc32
+
+    /* NOINIT section for RamLoc40 */
+    .noinit_RAM2 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM2 = .) ;
+       PROVIDE(__start_noinit_RamLoc40 = .) ;
+       *(.noinit.$RAM2)
+       *(.noinit.$RamLoc40)
+       *(.noinit.$RAM2.*)
+       *(.noinit.$RamLoc40.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM2 = .) ;
+       PROVIDE(__end_noinit_RamLoc40 = .) ;
+    } > RamLoc40 AT> RamLoc40
+
+    /* NOINIT section for RamAHB32 */
+    .noinit_RAM3 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM3 = .) ;
+       PROVIDE(__start_noinit_RamAHB32 = .) ;
+       *(.noinit.$RAM3)
+       *(.noinit.$RamAHB32)
+       *(.noinit.$RAM3.*)
+       *(.noinit.$RamAHB32.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM3 = .) ;
+       PROVIDE(__end_noinit_RamAHB32 = .) ;
+    } > RamAHB32 AT> RamAHB32
+
+    /* NOINIT section for RamAHB16 */
+    .noinit_RAM4 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM4 = .) ;
+       PROVIDE(__start_noinit_RamAHB16 = .) ;
+       *(.noinit.$RAM4)
+       *(.noinit.$RamAHB16)
+       *(.noinit.$RAM4.*)
+       *(.noinit.$RamAHB16.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM4 = .) ;
+       PROVIDE(__end_noinit_RamAHB16 = .) ;
+    } > RamAHB16 AT> RamAHB16
+
+    /* NOINIT section for RamAHB_ETB16 */
+    .noinit_RAM5 (NOLOAD) : ALIGN(4)
+    {
+       PROVIDE(__start_noinit_RAM5 = .) ;
+       PROVIDE(__start_noinit_RamAHB_ETB16 = .) ;
+       *(.noinit.$RAM5)
+       *(.noinit.$RamAHB_ETB16)
+       *(.noinit.$RAM5.*)
+       *(.noinit.$RamAHB_ETB16.*)
+       . = ALIGN(4) ;
+       PROVIDE(__end_noinit_RAM5 = .) ;
+       PROVIDE(__end_noinit_RamAHB_ETB16 = .) ;
+    } > RamAHB_ETB16 AT> RamAHB_ETB16
+
+    /* DEFAULT NOINIT SECTION */
+    .noinit (NOLOAD): ALIGN(4)
+    {
+        _noinit = .;
+        PROVIDE(__start_noinit_RAM = .) ;
+        PROVIDE(__start_noinit_RamLoc32 = .) ;
+        *(.noinit*)
+         . = ALIGN(4) ;
+        _end_noinit = .;
+       PROVIDE(__end_noinit_RAM = .) ;
+       PROVIDE(__end_noinit_RamLoc32 = .) ;
+    } > RamLoc32 AT> RamLoc32
+
+    PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
+
+    PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
+
+    /* ## Create checksum value (used in startup) ## */
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
+                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined */
+                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined */
+                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
+                                         ) );
+
+    /* Provide basic symbols giving location and size of main text
+     * block, including initial values of RW data sections. Note that
+     * these will need extending to give a complete picture with
+     * complex images (e.g multiple Flash banks).
+     */
+    _image_start = LOADADDR(.text);
+    _image_end = LOADADDR(.data) + SIZEOF(.data);
+    _image_size = _image_end - _image_start;
+}
diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c
index ba3191d5f..1c79ba7cf 100644
--- a/hw/bsp/lpc43/family.c
+++ b/hw/bsp/lpc43/family.c
@@ -39,31 +39,6 @@
 #include "bsp/board_api.h"
 #include "board.h"
 
-#define UART_DEV        LPC_USART0
-#define UART_PORT       0x0f
-#define UART_PIN_TX     10
-#define UART_PIN_RX     11
-
-// P9_1 joystick down
-#define BUTTON_PORT     4
-#define BUTTON_PIN      13
-
-//static const struct {
-//  uint8_t mux_port;
-//  uint8_t mux_pin;
-//
-//  uint8_t gpio_port;
-//  uint8_t gpio_pin;
-//}buttons[] =
-//{
-//    {0x0a, 3, 4, 10 }, // Joystick up
-//    {0x09, 1, 4, 13 }, // Joystick down
-//    {0x0a, 2, 4, 9  }, // Joystick left
-//    {0x09, 0, 4, 12 }, // Joystick right
-//    {0x0a, 1, 4, 8  }, // Joystick press
-//    {0x02, 7, 0, 7  }, // SW6
-//};
-
 #ifdef BOARD_TUD_RHPORT
   #define PORT_SUPPORT_DEVICE(_n)  (BOARD_TUD_RHPORT == _n)
 #else
@@ -76,34 +51,13 @@
   #define PORT_SUPPORT_HOST(_n)    0
 #endif
 
-/*------------------------------------------------------------------*/
-/* BOARD API
- *------------------------------------------------------------------*/
-
 /* System configuration variables used by chip driver */
 const uint32_t OscRateIn = 12000000;
 const uint32_t ExtRateIn = 0;
 
-static const PINMUX_GRP_T pinmuxing[] =
-{
-  // Button ( Joystick down )
-  {0x9, 1,  (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP)},
-
-  // UART
-  {UART_PORT, UART_PIN_TX, SCU_MODE_PULLDOWN | SCU_MODE_FUNC1},
-  {UART_PORT, UART_PIN_RX, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1},
-
-  // USB
-};
-
-/* Pin clock mux values, re-used structure, value in first index is meaningless */
-static const PINMUX_GRP_T pinclockmuxing[] =
-{
-  {0, 0,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 1,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 2,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-  {0, 3,  (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
-};
+/*------------------------------------------------------------------*/
+/* BOARD API
+ *------------------------------------------------------------------*/
 
 // Invoked by startup code
 void SystemInit(void)
@@ -113,19 +67,18 @@ void SystemInit(void)
   unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
 	*pSCB_VTOR = (unsigned int) g_pfnVectors;
 
-#if __FPU_USED == 1
+  #if __FPU_USED == 1
 	fpuInit();
+  #endif
 #endif
-#endif // __USE_LPCOPEN
 
-	/* Setup system level pin muxing */
-	Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
+  /* Setup system level pin muxing */
+  Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
 
-	/* Clock pins only, group field not used */
-	for (int i = 0; i <(int)  (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++)
-	{
-		Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
-	}
+//  /* Clock pins only, group field not used */
+//  for ( int i = 0; i < (int) (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++ ) {
+//    Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
+//  }
 
   Chip_SetupXtalClocking();
 }
@@ -144,13 +97,16 @@ void board_init(void)
 
   Chip_GPIO_Init(LPC_GPIO_PORT);
 
+#ifdef __PCA9532C_H
   // LED via pca9532 I2C
   Chip_SCU_I2C0PinConfig(I2C0_STANDARD_FAST_MODE);
   Chip_I2C_Init(I2C0);
   Chip_I2C_SetClockRate(I2C0, 100000);
   Chip_I2C_SetMasterEventHandler(I2C0, Chip_I2C_EventHandlerPolling);
-
   pca9532_init();
+#else
+  Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, LED_PORT, LED_PIN);
+#endif
 
   // Button
   Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
@@ -264,34 +220,30 @@ void USB1_IRQHandler(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  if (state)
-  {
-    pca9532_setLeds( LED1, 0 );
-  }else
-  {
-    pca9532_setLeds( 0, LED1);
+void board_led_write(bool state) {
+  #ifdef __PCA9532C_H
+  if ( state ) {
+    pca9532_setLeds(LED1, 0);
+  } else {
+    pca9532_setLeds(0, LED1);
   }
+  #else
+  Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state ? LED_STATE_ON : !LED_STATE_ON);
+  #endif
 }
 
-uint32_t board_button_read(void)
-{
-  // active low
-  return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
+uint32_t board_button_read(void) {
+  return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t *buf, int len) {
   return Chip_UART_Read(UART_DEV, buf, len);
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  uint8_t const* buf8 = (uint8_t const*) buf;
-  for(int i=0; i<len; i++)
-  {
-    while ((Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0) {}
+int board_uart_write(void const *buf, int len) {
+  uint8_t const *buf8 = (uint8_t const *) buf;
+  for ( int i = 0; i < len; i++ ) {
+    while ( (Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0 ) {}
     Chip_UART_SendByte(UART_DEV, buf8[i]);
   }
 
@@ -300,13 +252,13 @@ int board_uart_write(void const * buf, int len)
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif

From 78e5b2c6a4d58701dbb9c0ff69ba6cc02f5cc8e1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 14 Aug 2023 16:52:16 +0700
Subject: [PATCH 1993/2085] add board_get_unique_id() for lpc43

---
 hw/bsp/lpc43/family.c     |  7 +++++++
 hw/bsp/lpc43/family.cmake |  1 +
 hw/bsp/lpc43/family.mk    | 11 +++++++----
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c
index 1c79ba7cf..8d80bf951 100644
--- a/hw/bsp/lpc43/family.c
+++ b/hw/bsp/lpc43/family.c
@@ -236,6 +236,13 @@ uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN);
 }
 
+size_t board_get_unique_id(uint8_t id[], size_t max_len) {
+  if ( max_len < 16 ) return 0;
+  uint32_t* id32 = (uint32_t*) (uintptr_t) id;
+  Chip_IAP_ReadUID(id32);
+  return 16;
+}
+
 int board_uart_read(uint8_t *buf, int len) {
   return Chip_UART_Read(UART_DEV, buf, len);
 }
diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake
index 9fd78c9c2..e79004686 100644
--- a/hw/bsp/lpc43/family.cmake
+++ b/hw/bsp/lpc43/family.cmake
@@ -24,6 +24,7 @@ function(add_board_target BOARD_TARGET)
       ${SDK_DIR}/src/clock_18xx_43xx.c
       ${SDK_DIR}/src/fpu_init.c
       ${SDK_DIR}/src/gpio_18xx_43xx.c
+      ${SDK_DIR}/src/iap_18xx_43xx.c
       ${SDK_DIR}/src/sysinit_18xx_43xx.c
       ${SDK_DIR}/src/uart_18xx_43xx.c
       )
diff --git a/hw/bsp/lpc43/family.mk b/hw/bsp/lpc43/family.mk
index 4a1c2fb3c..55d86e955 100644
--- a/hw/bsp/lpc43/family.mk
+++ b/hw/bsp/lpc43/family.mk
@@ -12,7 +12,11 @@ CFLAGS += \
   -DCFG_TUSB_MCU=OPT_MCU_LPC43XX
 
 # mcu driver cause following warnings
-CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes  -Wno-error=cast-qual
+CFLAGS += \
+  -Wno-error=unused-parameter \
+  -Wno-error=strict-prototypes \
+  -Wno-error=cast-qual \
+  -Wno-error=incompatible-pointer-types \
 
 SRC_C += \
 	src/portable/chipidea/ci_hs/dcd_ci_hs.c \
@@ -21,12 +25,11 @@ SRC_C += \
 	${SDK_DIR}/../gcc/cr_startup_lpc43xx.c \
 	${SDK_DIR}/src/chip_18xx_43xx.c \
 	${SDK_DIR}/src/clock_18xx_43xx.c \
+	${SDK_DIR}/src/fpu_init.c \
 	${SDK_DIR}/src/gpio_18xx_43xx.c \
+	${SDK_DIR}/src/iap_18xx_43xx.c \
 	${SDK_DIR}/src/sysinit_18xx_43xx.c \
-	${SDK_DIR}/src/i2c_18xx_43xx.c \
-	${SDK_DIR}/src/i2cm_18xx_43xx.c \
 	${SDK_DIR}/src/uart_18xx_43xx.c \
-	${SDK_DIR}/src/fpu_init.c
 
 INC += \
   $(TOP)/$(BOARD_PATH) \

From bd51afb091f29cdab6520479a1a504409d95aac8 Mon Sep 17 00:00:00 2001
From: tswan-quasi <tucker.swan@10xar.com>
Date: Mon, 14 Aug 2023 08:49:52 -0400
Subject: [PATCH 1994/2085] min on cdc r/w

---
 src/class/cdc/cdc_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 70d9c2e24..2c1fda4ff 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -150,7 +150,7 @@ uint32_t tud_cdc_n_available(uint8_t itf)
 uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize)
 {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) bufsize);
+  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535));
   _prep_out_transaction(p_cdc);
   return num_read;
 }
@@ -173,7 +173,7 @@ void tud_cdc_n_read_flush (uint8_t itf)
 uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
 {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) bufsize);
+  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535));
 
   // flush if queue more than packet size
   // may need to suppress -Wunreachable-code since most of the time CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE

From b5ba12119dccb123aa6e8798dc86d639af6703b9 Mon Sep 17 00:00:00 2001
From: tswan-quasi <tucker.swan@10xar.com>
Date: Mon, 14 Aug 2023 09:01:30 -0400
Subject: [PATCH 1995/2085] UINT16_MAX stdint macro usage

---
 src/class/cdc/cdc_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c
index 2c1fda4ff..c26264e60 100644
--- a/src/class/cdc/cdc_device.c
+++ b/src/class/cdc/cdc_device.c
@@ -150,7 +150,7 @@ uint32_t tud_cdc_n_available(uint8_t itf)
 uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize)
 {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535));
+  uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
   _prep_out_transaction(p_cdc);
   return num_read;
 }
@@ -173,7 +173,7 @@ void tud_cdc_n_read_flush (uint8_t itf)
 uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
 {
   cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
-  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, 65535));
+  uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX));
 
   // flush if queue more than packet size
   // may need to suppress -Wunreachable-code since most of the time CFG_TUD_CDC_TX_BUFSIZE < BULK_PACKET_SIZE

From 088180e3d86cc51472dcd06ae42c613b534bf71c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 14 Aug 2023 20:58:00 +0700
Subject: [PATCH 1996/2085] add iar support for lpc43, add lpcxpresso43s67 to
 hil farm

---
 .github/workflows/build_iar.yml               | 81 +------------------
 .../host/msc_file_explorer/CMakeLists.txt     | 12 +--
 hw/bsp/lpc43/family.c                         | 20 ++++-
 hw/bsp/lpc43/family.cmake                     | 75 +++++++++--------
 test/hil/hil_hfp.json                         |  7 ++
 tools/get_deps.py                             |  2 +-
 6 files changed, 72 insertions(+), 125 deletions(-)

diff --git a/.github/workflows/build_iar.yml b/.github/workflows/build_iar.yml
index 48fdd6a8a..1eacf90c9 100644
--- a/.github/workflows/build_iar.yml
+++ b/.github/workflows/build_iar.yml
@@ -32,7 +32,7 @@ jobs:
           # Alphabetical order
           # Note: bundle multiple families into a matrix since there is only one self-hosted instance can
           # run IAR build. Too many matrix can hurt due to setup/teardown overhead.
-          - 'stm32f0 stm32f1 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l4'
+          - 'lpc43 stm32f0 stm32f1 stm32f4 stm32f7 stm32g0 stm32g4 stm32h7 stm32l4'
     steps:
       - name: Clean workspace
         run: |
@@ -52,82 +52,3 @@ jobs:
       - name: Test on actual hardware (hardware in the loop)
         run: |
           python3 test/hil/hil_test.py hil_hfp.json
-
-#      # Upload binaries for hardware test with self-hosted
-#      - name: Prepare stm32l412nucleo Artifacts
-#        if: contains(matrix.family, 'stm32l4')
-#        working-directory: ${{github.workspace}}/cmake-build/cmake-build-stm32l412nucleo
-#        run: |
-#          find device/ -name "*.elf" -exec mv {} ../../ \;
-#
-#      - name: Upload Artifacts for stm32l412nucleo
-#        if: contains(matrix.family, 'stm32l4') && github.repository_owner == 'hathach'
-#        uses: actions/upload-artifact@v3
-#        with:
-#          name: stm32l4
-#          path: |
-#            *.elf
-
-  # ---------------------------------------
-  # Hardware in the loop (HIL)
-  # Current self-hosted instance is running on an EPYC 7232 server hosted by HiFiPhile user
-  # ---------------------------------------
-#  hw-stm32l412nucleo-test:
-#    needs: cmake
-#    runs-on: [self-hosted, Linux, X64, hifiphile]
-#
-#    steps:
-#      - name: Clean workspace
-#        run: |
-#          echo "Cleaning up previous run"
-#          rm -rf "${{ github.workspace }}"
-#          mkdir -p "${{ github.workspace }}"
-#
-#      - name: Download stm32l4 Artifacts
-#        uses: actions/download-artifact@v3
-#        with:
-#          name: stm32l4
-#
-#      - name: Create flash.sh
-#        run: |
-#          echo > flash.sh 'echo halt > flash.jlink'
-#          echo >> flash.sh 'echo r >> flash.jlink'
-#          echo >> flash.sh 'echo loadfile $1 >> flash.jlink'
-#          echo >> flash.sh 'echo r >> flash.jlink'
-#          echo >> flash.sh 'echo go >> flash.jlink'
-#          echo >> flash.sh 'echo exit >> flash.jlink'
-#          echo >> flash.sh 'cmdout=$(JLinkExe -USB 774470029 -device stm32l412kb -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile flash.jlink)'
-#          echo >> flash.sh 'if (( $? )) ; then echo $cmdout ; fi'
-#          chmod +x flash.sh
-#
-#      - name: Test cdc_dual_ports
-#        run: |
-#          ./flash.sh cdc_dual_ports.elf
-#          while (! ([ -e /dev/ttyACM1 ] && [ -e /dev/ttyACM2 ])) && [ $SECONDS -le 10 ]; do :; done
-#          test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-#          test -e /dev/ttyACM2 && echo "ttyACM2 exists"
-#
-#        # Debian does not auto mount usb drive. skip this test for now
-#      - name: Test cdc_msc
-#        if: false
-#        run: |
-#          ./flash.sh cdc_msc.elf
-#          readme='/media/pi/TinyUSB MSC/README.TXT'
-#          while (! ([ -e /dev/ttyACM1 ] && [ -f "$readme" ])) && [ $SECONDS -le 10 ]; do :; done
-#          test -e /dev/ttyACM1 && echo "ttyACM1 exists"
-#          test -f "$readme" && echo "$readme exists"
-#          cat "$readme"
-#
-#      - name: Test dfu
-#        run: |
-#          ./flash.sh dfu.elf
-#          while (! (dfu-util -l | grep "Found DFU")) && [ $SECONDS -le 10 ]; do :; done
-#          dfu-util -d cafe -a 0 -U dfu0
-#          dfu-util -d cafe -a 1 -U dfu1
-#          grep "TinyUSB DFU! - Partition 0" dfu0
-#          grep "TinyUSB DFU! - Partition 1" dfu1
-#
-#      - name: Test dfu_runtime
-#        run: |
-#          ./flash.sh dfu_runtime.elf
-#          while (! (dfu-util -l | grep "Found Runtime")) && [ $SECONDS -le 10 ]; do :; done
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index a35a7f0fb..1868b632e 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -22,11 +22,13 @@ target_sources(${PROJECT} PUBLIC
   )
 
 # Suppress warnings on fatfs
-set_source_files_properties(
-  ${TOP}/lib/fatfs/source/ff.c
-  PROPERTIES
-  COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual"
-)
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+  set_source_files_properties(
+    ${TOP}/lib/fatfs/source/ff.c
+    PROPERTIES
+    COMPILE_FLAGS "-Wno-conversion -Wno-cast-qual"
+    )
+endif ()
 
 # Example include
 target_include_directories(${PROJECT} PUBLIC
diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c
index 8d80bf951..d52c1a071 100644
--- a/hw/bsp/lpc43/family.c
+++ b/hw/bsp/lpc43/family.c
@@ -63,13 +63,25 @@ const uint32_t ExtRateIn = 0;
 void SystemInit(void)
 {
 #ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
   unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
 
-  #if __FPU_USED == 1
+#ifdef __ICCARM__
+  extern void *__vector_table;
+  *pSCB_VTOR = (unsigned int) &__vector_table;
+
+#elif defined(__ARMCC_VERSION)
+  extern void *__Vectors;
+	*pSCB_VTOR = (unsigned int) &__Vectors;
+
+#else // other compoiler using cr_startup_lpc43xx.c
+	extern void (* const g_pfnVectors[])(void);
+	*pSCB_VTOR = (unsigned int) g_pfnVectors;
+#endif
+
+#if __FPU_USED == 1
 	fpuInit();
-  #endif
+#endif
+
 #endif
 
   /* Setup system level pin muxing */
diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake
index e79004686..608fc4ca3 100644
--- a/hw/bsp/lpc43/family.cmake
+++ b/hw/bsp/lpc43/family.cmake
@@ -17,43 +17,48 @@ set(FAMILY_MCUS LPC43XX CACHE INTERNAL "")
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      ${SDK_DIR}/../gcc/cr_startup_lpc43xx.c
-      ${SDK_DIR}/src/chip_18xx_43xx.c
-      ${SDK_DIR}/src/clock_18xx_43xx.c
-      ${SDK_DIR}/src/fpu_init.c
-      ${SDK_DIR}/src/gpio_18xx_43xx.c
-      ${SDK_DIR}/src/iap_18xx_43xx.c
-      ${SDK_DIR}/src/sysinit_18xx_43xx.c
-      ${SDK_DIR}/src/uart_18xx_43xx.c
-      )
-    target_compile_options(${BOARD_TARGET} PUBLIC
-      -nostdlib
-      )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      __USE_LPCOPEN
-      CORE_M4
-      )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${SDK_DIR}/inc
-      ${SDK_DIR}/inc/config_43xx
-      )
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
 
-    update_board(${BOARD_TARGET})
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${SDK_DIR}/../gcc/cr_startup_lpc43xx.c)
+  set(STARTUP_FILE_IAR ${SDK_DIR}/../iar/iar_startup_lpc18xx43xx.s)
+  set(LD_FILE_IAR ${SDK_DIR}/../iar/linker/lpc18xx_43xx_ldscript_iflash.icf)
 
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_GNU}"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
+  add_library(${BOARD_TARGET} STATIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    ${SDK_DIR}/src/chip_18xx_43xx.c
+    ${SDK_DIR}/src/clock_18xx_43xx.c
+    ${SDK_DIR}/src/fpu_init.c
+    ${SDK_DIR}/src/gpio_18xx_43xx.c
+    ${SDK_DIR}/src/iap_18xx_43xx.c
+    ${SDK_DIR}/src/sysinit_18xx_43xx.c
+    ${SDK_DIR}/src/uart_18xx_43xx.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    __USE_LPCOPEN
+    CORE_M4
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/inc
+    ${SDK_DIR}/inc/config_43xx
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib)
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
   endif ()
 endfunction()
 
diff --git a/test/hil/hil_hfp.json b/test/hil/hil_hfp.json
index 7912af245..58f550901 100644
--- a/test/hil/hil_hfp.json
+++ b/test/hil/hil_hfp.json
@@ -13,6 +13,13 @@
             "debugger": "jlink",
             "debugger_sn": "770935966",
             "cpu": "STM32F746NG"
+        },
+        {
+            "name": "lpcxpresso43s67",
+            "uid": "08F000044528BAAA8D858F58C50700F5",
+            "debugger": "jlink",
+            "debugger_sn": "728973776",
+            "cpu": "LPC43S67_M4"
         }
     ]
 }
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 82f756f64..1fac291a3 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -48,7 +48,7 @@ deps_optional = {
                        '2204191ec76283371419fbcec207da02e1bc22fa',
                        'nuc'],
     'hw/mcu/nxp/lpcopen': ['https://github.com/hathach/nxp_lpcopen.git',
-                           '43c45c85405a5dd114fff0ea95cca62837740c13',
+                           '84e0bd3e43910aaf71eefd62075cf57495418312',
                            'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43'],
     'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git',
                             '950819b7de9b32f92c3edf396bc5ffb8d66e7009',

From f2f005cbdf33dd0e10617535bcf7c0b24d6762b0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 14 Aug 2023 22:01:30 +0700
Subject: [PATCH 1997/2085] fix build iar with lpc43

---
 examples/host/cdc_msc_hid/src/hid_app.c       | 2 ++
 examples/host/msc_file_explorer/src/msc_app.c | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c
index 7727ee62c..f0d42a08f 100644
--- a/examples/host/cdc_msc_hid/src/hid_app.c
+++ b/examples/host/cdc_msc_hid/src/hid_app.c
@@ -160,7 +160,9 @@ static void process_kbd_report(hid_keyboard_report_t const *report)
         putchar(ch);
         if ( ch == '\r' ) putchar('\n'); // added new line for enter key
 
+        #ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
         fflush(stdout); // flush right away, else nanolib will wait for newline
+        #endif
       }
     }
     // TODO example skips key released
diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c
index 323dfb9e7..ecea614a2 100644
--- a/examples/host/msc_file_explorer/src/msc_app.c
+++ b/examples/host/msc_file_explorer/src/msc_app.c
@@ -66,7 +66,10 @@ bool msc_app_init(void)
   for(size_t i=0; i<CFG_TUH_DEVICE_MAX; i++) _disk_busy[i] = false;
 
   // disable stdout buffered for echoing typing command
+  #ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
   setbuf(stdout, NULL);
+  #endif
+
   cli_init();
 
   return true;

From 9d942967414d7b95f3a132c284ef83f386a0c467 Mon Sep 17 00:00:00 2001
From: rppicomidi <rppicomidi@gmail.com>
Date: Mon, 14 Aug 2023 15:38:48 -0700
Subject: [PATCH 1998/2085] fix issue 2188: support usbh_app_driver_get_cb()

---
 README.rst                  |  2 +
 src/host/usbh.c             | 86 ++++++++++++++++++++++++++-----------
 src/host/usbh_classdriver.h |  8 ++++
 3 files changed, 72 insertions(+), 24 deletions(-)

diff --git a/README.rst b/README.rst
index 78e8d87b0..d72cdb149 100644
--- a/README.rst
+++ b/README.rst
@@ -89,6 +89,8 @@ Host Stack
 - Mass Storage Class (MSC)
 - Hub with multiple-level support
 
+Similar to the Device Stack, if you have a special requirement, `usbh_app_driver_get_cb()` can be used to write your own class driver without modifying the stack.
+
 TypeC PD Stack
 ==============
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index cc7e38b45..af8142be3 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -180,7 +180,7 @@ static usbh_class_driver_t const usbh_class_drivers[] =
   #endif
 };
 
-enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
+enum { USBH_BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
 enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
 
@@ -246,6 +246,21 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
 static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
+// Additional class drivers implemented by application
+tu_static usbh_class_driver_t const * _app_driver = NULL;
+tu_static uint8_t _app_driver_count = 0;
+tu_static uint8_t _total_driver_count = USBH_BUILTIN_DRIVER_COUNT;
+
+static usbh_class_driver_t const * usbh_get_driver(uint8_t drv_id)
+{
+  usbh_class_driver_t const * driver = NULL;
+  if ( drv_id < _app_driver_count )
+    driver = &_app_driver[drv_id];
+  else if ( drv_id < _total_driver_count )
+    driver = &usbh_class_drivers[drv_id - _app_driver_count];
+  return driver;
+}
+
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
 // weak and overridable
@@ -339,6 +354,12 @@ bool tuh_init(uint8_t controller_id) {
   _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
   TU_ASSERT(_usbh_mutex);
 #endif
+  // Get application driver if available
+  if ( usbh_app_driver_get_cb )
+  {
+    _app_driver = usbh_app_driver_get_cb(&_app_driver_count);
+    _total_driver_count = USBH_BUILTIN_DRIVER_COUNT + _app_driver_count;
+  }
 
   // Device
   tu_memclr(&_dev0, sizeof(_dev0));
@@ -351,10 +372,14 @@ bool tuh_init(uint8_t controller_id) {
   }
 
   // Class drivers
-  for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+  for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++)
   {
-    TU_LOG_USBH("%s init\r\n", usbh_class_drivers[drv_id].name);
-    usbh_class_drivers[drv_id].init();
+    usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+    if ( driver )
+    {
+      TU_LOG_USBH("%s init\r\n", driver->name);
+      driver->init();
+    }
   }
 
   _usbh_controller = controller_id;;
@@ -482,12 +507,16 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
             }else
             #endif
             {
-              uint8_t const drv_id = dev->ep2drv[epnum][ep_dir];
-              if ( drv_id < USBH_CLASS_DRIVER_COUNT ) {
-                TU_LOG_USBH("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
-                usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
+              uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
+              usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+              if ( driver )
+              {
+                TU_LOG_USBH("%s xfer callback\r\n", driver->name);
+                driver->xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
                                                    event.xfer_complete.len);
-              } else {
+              }
+              else
+              {
                 // no driver/callback responsible for this transfer
                 TU_ASSERT(false,);
               }
@@ -1183,17 +1212,20 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
   uint8_t nop_count = 0;
 #endif
 
-  for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) {
+  for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++)
+  {
     usbh_device_t *dev = &_usbh_devices[dev_id];
     uint8_t const daddr = dev_id + 1;
 
     // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub
     if (dev->rhport == rhport && dev->connected &&
         (hub_addr == 0 || dev->hub_addr == hub_addr) &&
-        (hub_port == 0 || dev->hub_port == hub_port)) {
+        (hub_port == 0 || dev->hub_port == hub_port))
+    {
       TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
 
-      if (is_hub_addr(daddr)) {
+      if (is_hub_addr(daddr))
+      {
         TU_LOG(CFG_TUH_LOG_LEVEL, "  is a HUB device %u\r\n", daddr);
 
         // Submit removed event If the device itself is a hub (un-rolled recursive)
@@ -1211,10 +1243,14 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
       }
 
       // Close class driver
-      for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++) {
-        usbh_class_drivers[drv_id].close(daddr);
+      for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++)
+      {
+        usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+        if ( driver )
+        {
+          driver->close(daddr);
+        }
       }
-
       hcd_device_close(rhport, daddr);
       clear_device(dev);
       // abort on-going control xfer if any
@@ -1643,11 +1679,12 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
     // Find driver for this interface
-    for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+    uint8_t drv_id = 0;
+    for (; drv_id < _total_driver_count; drv_id++)
     {
-      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+      usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
 
-      if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
+      if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
       {
         // open successfully
         TU_LOG_USBH("  %s opened\r\n", driver->name);
@@ -1668,11 +1705,12 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
         break; // exit driver find loop
       }
 
-      if( drv_id >= USBH_CLASS_DRIVER_COUNT )
-      {
-        TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
-               desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
-      }
+    }
+
+    if( drv_id >= _total_driver_count )
+    {
+      TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+            desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
     }
 
     // next Interface or IAD descriptor
@@ -1694,7 +1732,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
     uint8_t const drv_id = dev->itf2drv[itf_num];
     if (drv_id != TUSB_INDEX_INVALID_8)
     {
-      usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+      usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
       TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num);
       driver->set_config(dev_addr, itf_num);
       break;
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_classdriver.h
index 308b4418a..7443b2d90 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_classdriver.h
@@ -96,6 +96,14 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr);
 // Check if endpoint transferring is complete
 bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
 
+//--------------------------------------------------------------------+
+// USBH application additional driver API
+//--------------------------------------------------------------------+
+// Invoked when initializing host stack to get additional class drivers.
+// Can optionally implemented by application to extend/overwrite class driver support.
+// Note: The drivers array must be accessible at all time when stack is active
+usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
+
 #ifdef __cplusplus
  }
 #endif

From 1b33a315365184a74a8b5bbce5fdbdfc4dfe6f69 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Aug 2023 22:51:21 +0700
Subject: [PATCH 1999/2085] more minor clean up

- also rename usbh_classdriver.h to usbh_pvt.h to consitent with usbd
---
 src/class/cdc/cdc_host.c                    |  2 +-
 src/class/hid/hid_host.c                    |  2 +-
 src/class/msc/msc_host.c                    |  2 +-
 src/device/usbd.c                           | 31 +++-----
 src/device/usbd_pvt.h                       |  2 +-
 src/host/hub.c                              |  2 +-
 src/host/usbh.c                             | 84 ++++++++++-----------
 src/host/{usbh_classdriver.h => usbh_pvt.h} | 13 ++--
 src/tusb.c                                  |  2 +-
 9 files changed, 61 insertions(+), 79 deletions(-)
 rename src/host/{usbh_classdriver.h => usbh_pvt.h} (93%)

diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c
index 40ebd331d..53e15710e 100644
--- a/src/class/cdc/cdc_host.c
+++ b/src/class/cdc/cdc_host.c
@@ -29,7 +29,7 @@
 #if (CFG_TUH_ENABLED && CFG_TUH_CDC)
 
 #include "host/usbh.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 
 #include "cdc_host.h"
 
diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c
index 4253170d4..a3551c85a 100644
--- a/src/class/hid/hid_host.c
+++ b/src/class/hid/hid_host.c
@@ -29,7 +29,7 @@
 #if (CFG_TUH_ENABLED && CFG_TUH_HID)
 
 #include "host/usbh.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 
 #include "hid_host.h"
 
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index 90a58d3d0..da264142c 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -29,7 +29,7 @@
 #if CFG_TUH_ENABLED && CFG_TUH_MSC
 
 #include "host/usbh.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 
 #include "msc_host.h"
 
diff --git a/src/device/usbd.c b/src/device/usbd.c
index 156b92ce1..f0d9fba52 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -238,34 +238,25 @@ enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) };
 tu_static usbd_class_driver_t const * _app_driver = NULL;
 tu_static uint8_t _app_driver_count = 0;
 
+#define TOTAL_DRIVER_COUNT    (_app_driver_count + BUILTIN_DRIVER_COUNT)
+
 // virtually joins built-in and application drivers together.
 // Application is positioned first to allow overwriting built-in ones.
 static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
 {
-  // Application drivers
-  if ( usbd_app_driver_get_cb )
-  {
-    if ( drvid < _app_driver_count ) return &_app_driver[drvid];
-    drvid -= _app_driver_count;
+  usbd_class_driver_t const * driver = NULL;
+
+  if ( drvid < _app_driver_count ) {
+    // Application drivers
+    driver = &_app_driver[drvid];
+  } else if ( drvid < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0 ){
+    driver = &_usbd_driver[drvid - _app_driver_count];
   }
 
-  // when there is no built-in drivers BUILTIN_DRIVER_COUNT = 0 will cause -Wtype-limits warning
-#ifdef __GNUC__
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wtype-limits"
-#endif
-
-  // Built-in drivers
-  if (drvid < BUILTIN_DRIVER_COUNT) return &_usbd_driver[drvid];
-
-#ifdef __GNUC__
-#pragma GCC diagnostic pop
-#endif
-
-  return NULL;
+  return driver;
 }
 
-#define TOTAL_DRIVER_COUNT    (_app_driver_count + BUILTIN_DRIVER_COUNT)
+
 
 //--------------------------------------------------------------------+
 // DCD Event
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 940b2858b..16585167f 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -59,7 +59,7 @@ typedef struct
 } usbd_class_driver_t;
 
 // Invoked when initializing device stack to get additional class drivers.
-// Can optionally implemented by application to extend/overwrite class driver support.
+// Can be implemented by application to extend/overwrite class driver support.
 // Note: The drivers array must be accessible at all time when stack is active
 usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
 
diff --git a/src/host/hub.c b/src/host/hub.c
index ec30eb96a..32f5e0ac7 100644
--- a/src/host/hub.c
+++ b/src/host/hub.c
@@ -30,7 +30,7 @@
 
 #include "hcd.h"
 #include "usbh.h"
-#include "usbh_classdriver.h"
+#include "usbh_pvt.h"
 #include "hub.h"
 
 // Debug level, TUSB_CFG_DEBUG must be at least this level for debug message
diff --git a/src/host/usbh.c b/src/host/usbh.c
index af8142be3..739157b56 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -30,7 +30,7 @@
 
 #include "host/hcd.h"
 #include "tusb.h"
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 #include "hub.h"
 
 //--------------------------------------------------------------------+
@@ -183,6 +183,23 @@ static usbh_class_driver_t const usbh_class_drivers[] =
 enum { USBH_BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
 enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
+// Additional class drivers implemented by application
+tu_static usbh_class_driver_t const * _app_driver = NULL;
+tu_static uint8_t _app_driver_count = 0;
+
+#define TOTAL_DRIVER_COUNT    (_app_driver_count + USBH_BUILTIN_DRIVER_COUNT)
+
+static inline usbh_class_driver_t const *get_driver(uint8_t drv_id) {
+  usbh_class_driver_t const *driver = NULL;
+
+  if ( drv_id < _app_driver_count ) {
+    driver = &_app_driver[drv_id];
+  } else if ( drv_id < TOTAL_DRIVER_COUNT && USBH_BUILTIN_DRIVER_COUNT > 0) {
+    driver = &usbh_class_drivers[drv_id - _app_driver_count];
+  }
+
+  return driver;
+}
 
 //--------------------------------------------------------------------+
 // INTERNAL OBJECT & FUNCTION DECLARATION
@@ -246,21 +263,6 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
 static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
 static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
 
-// Additional class drivers implemented by application
-tu_static usbh_class_driver_t const * _app_driver = NULL;
-tu_static uint8_t _app_driver_count = 0;
-tu_static uint8_t _total_driver_count = USBH_BUILTIN_DRIVER_COUNT;
-
-static usbh_class_driver_t const * usbh_get_driver(uint8_t drv_id)
-{
-  usbh_class_driver_t const * driver = NULL;
-  if ( drv_id < _app_driver_count )
-    driver = &_app_driver[drv_id];
-  else if ( drv_id < _total_driver_count )
-    driver = &usbh_class_drivers[drv_id - _app_driver_count];
-  return driver;
-}
-
 #if CFG_TUSB_OS == OPT_OS_NONE
 // TODO rework time-related function later
 // weak and overridable
@@ -354,11 +356,10 @@ bool tuh_init(uint8_t controller_id) {
   _usbh_mutex = osal_mutex_create(&_usbh_mutexdef);
   TU_ASSERT(_usbh_mutex);
 #endif
+
   // Get application driver if available
-  if ( usbh_app_driver_get_cb )
-  {
+  if ( usbh_app_driver_get_cb ) {
     _app_driver = usbh_app_driver_get_cb(&_app_driver_count);
-    _total_driver_count = USBH_BUILTIN_DRIVER_COUNT + _app_driver_count;
   }
 
   // Device
@@ -372,9 +373,9 @@ bool tuh_init(uint8_t controller_id) {
   }
 
   // Class drivers
-  for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++)
+  for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
   {
-    usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+    usbh_class_driver_t const * driver = get_driver(drv_id);
     if ( driver )
     {
       TU_LOG_USBH("%s init\r\n", driver->name);
@@ -508,12 +509,12 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
             #endif
             {
               uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
-              usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+              usbh_class_driver_t const * driver = get_driver(drv_id);
               if ( driver )
               {
                 TU_LOG_USBH("%s xfer callback\r\n", driver->name);
                 driver->xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result,
-                                                   event.xfer_complete.len);
+                                event.xfer_complete.len);
               }
               else
               {
@@ -1220,12 +1221,10 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
     // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub
     if (dev->rhport == rhport && dev->connected &&
         (hub_addr == 0 || dev->hub_addr == hub_addr) &&
-        (hub_port == 0 || dev->hub_port == hub_port))
-    {
+        (hub_port == 0 || dev->hub_port == hub_port)) {
       TU_LOG_USBH("Device unplugged address = %u\r\n", daddr);
 
-      if (is_hub_addr(daddr))
-      {
+      if (is_hub_addr(daddr)) {
         TU_LOG(CFG_TUH_LOG_LEVEL, "  is a HUB device %u\r\n", daddr);
 
         // Submit removed event If the device itself is a hub (un-rolled recursive)
@@ -1243,14 +1242,11 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
       }
 
       // Close class driver
-      for (uint8_t drv_id = 0; drv_id < _total_driver_count; drv_id++)
-      {
-        usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
-        if ( driver )
-        {
-          driver->close(daddr);
-        }
+      for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) {
+        usbh_class_driver_t const * driver = get_driver(drv_id);
+        if ( driver ) driver->close(daddr);
       }
+
       hcd_device_close(rhport, daddr);
       clear_device(dev);
       // abort on-going control xfer if any
@@ -1679,10 +1675,9 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
     TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
 
     // Find driver for this interface
-    uint8_t drv_id = 0;
-    for (; drv_id < _total_driver_count; drv_id++)
+    for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
     {
-      usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
+      usbh_class_driver_t const * driver = get_driver(drv_id);
 
       if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
       {
@@ -1705,12 +1700,11 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
         break; // exit driver find loop
       }
 
-    }
-
-    if( drv_id >= _total_driver_count )
-    {
-      TU_LOG(CFG_TUH_LOG_LEVEL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
-            desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
+      if ( drv_id == TOTAL_DRIVER_COUNT - 1 )
+      {
+        TU_LOG(CFG_TUH_LOG_LEVEL, "[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+               dev->rhport, dev_addr, desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
+      }
     }
 
     // next Interface or IAD descriptor
@@ -1730,9 +1724,9 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
     // IAD binding interface such as CDCs should return itf_num + 1 when complete
     // with usbh_driver_set_config_complete()
     uint8_t const drv_id = dev->itf2drv[itf_num];
-    if (drv_id != TUSB_INDEX_INVALID_8)
+    usbh_class_driver_t const * driver = get_driver(drv_id);
+    if (driver)
     {
-      usbh_class_driver_t const * driver = usbh_get_driver(drv_id);
       TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num);
       driver->set_config(dev_addr, itf_num);
       break;
diff --git a/src/host/usbh_classdriver.h b/src/host/usbh_pvt.h
similarity index 93%
rename from src/host/usbh_classdriver.h
rename to src/host/usbh_pvt.h
index 7443b2d90..0b58a91bc 100644
--- a/src/host/usbh_classdriver.h
+++ b/src/host/usbh_pvt.h
@@ -62,6 +62,11 @@ typedef struct {
   void (* const close      )(uint8_t dev_addr);
 } usbh_class_driver_t;
 
+// Invoked when initializing host stack to get additional class drivers.
+// Can be implemented by application to extend/overwrite class driver support.
+// Note: The drivers array must be accessible at all time when stack is active
+usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
+
 // Call by class driver to tell USBH that it has complete the enumeration
 void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num);
 
@@ -96,14 +101,6 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr);
 // Check if endpoint transferring is complete
 bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
 
-//--------------------------------------------------------------------+
-// USBH application additional driver API
-//--------------------------------------------------------------------+
-// Invoked when initializing host stack to get additional class drivers.
-// Can optionally implemented by application to extend/overwrite class driver support.
-// Note: The drivers array must be accessible at all time when stack is active
-usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
-
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/tusb.c b/src/tusb.c
index 465b608b0..7b0a669a0 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -36,7 +36,7 @@
 #endif
 
 #if CFG_TUH_ENABLED
-#include "host/usbh_classdriver.h"
+#include "host/usbh_pvt.h"
 #endif
 
 //--------------------------------------------------------------------+

From 67a374d932cbe14bf1651bdd6fea82c2e2ecfa10 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Aug 2023 22:57:05 +0700
Subject: [PATCH 2000/2085] more rename

---
 src/host/usbh.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 739157b56..7cdcbda5e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -180,21 +180,21 @@ static usbh_class_driver_t const usbh_class_drivers[] =
   #endif
 };
 
-enum { USBH_BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
+enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
 enum { CONFIG_NUM = 1 }; // default to use configuration 1
 
 // Additional class drivers implemented by application
 tu_static usbh_class_driver_t const * _app_driver = NULL;
 tu_static uint8_t _app_driver_count = 0;
 
-#define TOTAL_DRIVER_COUNT    (_app_driver_count + USBH_BUILTIN_DRIVER_COUNT)
+#define TOTAL_DRIVER_COUNT    (_app_driver_count + BUILTIN_DRIVER_COUNT)
 
 static inline usbh_class_driver_t const *get_driver(uint8_t drv_id) {
   usbh_class_driver_t const *driver = NULL;
 
   if ( drv_id < _app_driver_count ) {
     driver = &_app_driver[drv_id];
-  } else if ( drv_id < TOTAL_DRIVER_COUNT && USBH_BUILTIN_DRIVER_COUNT > 0) {
+  } else if ( drv_id < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0) {
     driver = &usbh_class_drivers[drv_id - _app_driver_count];
   }
 

From b3c7fe1023d14d1e07eb21ca9a61438bff49a788 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 15 Aug 2023 00:09:31 +0700
Subject: [PATCH 2001/2085] clear qhd halted bit if not caused by STALL
 protocol, allow for next transfer

---
 src/portable/ehci/ehci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index 79811985c..c5036b5a3 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -579,6 +579,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
       if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) {
         // Error count = 0 often occurs when device disconnected, or other bus-related error
         xfer_result = XFER_RESULT_FAILED;
+        qtd_overlay->halted = false; // clear halted bit if it is not caused by STALL
         TU_LOG3("  QHD xfer err count: %d\n", qtd_overlay->err_count);
         // TU_BREAKPOINT(); // TODO skip unplugged device
       }else {

From 0109ffbdcb22a358ecbc1476fbfb4e370e5bb4cc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Aug 2023 14:31:14 +0700
Subject: [PATCH 2002/2085] fix abort transfer does not release endpoint, also
 reset state if it is control transfer

---
 src/host/usbh.c | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/src/host/usbh.c b/src/host/usbh.c
index 7cdcbda5e..5423df669 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -738,19 +738,27 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) {
   usbh_device_t* dev = get_device(daddr);
   TU_VERIFY(dev);
 
+  TU_LOG_USBH("[%u] Aborted transfer on EP %02X\r\n", daddr, ep_addr);
+
   uint8_t const epnum = tu_edpt_number(ep_addr);
   uint8_t const dir   = tu_edpt_dir(ep_addr);
 
-  // skip if not busy
-  TU_VERIFY(dev->ep_status[epnum][dir].busy);
-
-  bool const ret = hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr);
-  if (ret) {
-    // mark as ready if transfer is aborted
+  if ( epnum == 0 ) {
+    // control transfer: only 1 control at a time, check if we are aborting the current one
+    TU_VERIFY(daddr == _ctrl_xfer.daddr && _ctrl_xfer.stage != CONTROL_STAGE_IDLE);
+    TU_VERIFY(hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr));
+    // reset control transfer state to idle
+    _set_control_xfer_stage(CONTROL_STAGE_IDLE);
+  } else {
+    // non-control skip if not busy
+    TU_VERIFY(dev->ep_status[epnum][dir].busy);
+    TU_VERIFY(hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr));
+    // mark as ready and release endpoint if transfer is aborted
     dev->ep_status[epnum][dir].busy = false;
+    usbh_edpt_release(daddr, ep_addr);
   }
 
-  return ret;
+  return true;
 }
 
 //--------------------------------------------------------------------+

From f4845e4e6cc2faca4e60cd83959850f27d3f3076 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 16 Aug 2023 14:43:58 +0700
Subject: [PATCH 2003/2085] minor comment

---
 src/portable/ehci/ehci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index c5036b5a3..c93c33fc0 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -578,8 +578,9 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) {
     if ( qtd_overlay->halted ) {
       if (qtd_overlay->xact_err || qtd_overlay->err_count == 0 || qtd_overlay->buffer_err || qtd_overlay->babble_err) {
         // Error count = 0 often occurs when device disconnected, or other bus-related error
+        // clear halted bit if not caused by STALL to allow more transfer
         xfer_result = XFER_RESULT_FAILED;
-        qtd_overlay->halted = false; // clear halted bit if it is not caused by STALL
+        qtd_overlay->halted = false;
         TU_LOG3("  QHD xfer err count: %d\n", qtd_overlay->err_count);
         // TU_BREAKPOINT(); // TODO skip unplugged device
       }else {

From 9257a0f562a1cb939a902e7c41de5032b0f7de19 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Aug 2023 12:48:12 +0700
Subject: [PATCH 2004/2085] - update nrf52 bsp for cmake - add empty
 tuh_int_handler/tud_int_handler if corresponidng stack not enabled - add
 hcd_template.c

---
 hw/bsp/nrf/boards/adafruit_clue/board.cmake   |   5 +
 .../nrf/boards/arduino_nano33_ble/board.cmake |   5 +
 .../circuitplayground_bluefruit/board.cmake   |   5 +
 .../feather_nrf52840_express/board.cmake      |   6 +
 .../boards/feather_nrf52840_sense/board.cmake |   5 +
 .../nrf/boards/itsybitsy_nrf52840/board.cmake |   5 +
 .../boards/nrf52840_mdk_dongle/board.cmake    |   5 +
 hw/bsp/nrf/boards/pca10056/board.cmake        |   3 -
 hw/bsp/nrf/boards/pca10059/board.cmake        |   5 +
 hw/bsp/nrf/boards/pca10095/board.cmake        |   4 -
 hw/bsp/nrf/boards/pca10100/board.cmake        |   5 +
 .../nrf/boards/raytac_mdbt50q_rx/board.cmake  |   5 +
 hw/bsp/nrf/family.cmake                       |  14 +-
 src/device/usbd.h                             |   6 +-
 src/host/hcd.h                                |  12 +-
 src/portable/template/dcd_template.c          |   4 +-
 src/portable/template/hcd_template.c          | 162 ++++++++++++++++++
 src/tusb.h                                    |   9 +-
 18 files changed, 241 insertions(+), 24 deletions(-)
 create mode 100644 hw/bsp/nrf/boards/adafruit_clue/board.cmake
 create mode 100644 hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake
 create mode 100644 hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake
 create mode 100644 hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
 create mode 100644 hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake
 create mode 100644 hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake
 create mode 100644 hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake
 create mode 100644 hw/bsp/nrf/boards/pca10059/board.cmake
 create mode 100644 hw/bsp/nrf/boards/pca10100/board.cmake
 create mode 100644 hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
 create mode 100644 src/portable/template/hcd_template.c

diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.cmake b/hw/bsp/nrf/boards/adafruit_clue/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/adafruit_clue/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake b/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake
new file mode 100644
index 000000000..93647063a
--- /dev/null
+++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/arduino_nano33_ble.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
new file mode 100644
index 000000000..0acbecf7a
--- /dev/null
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
@@ -0,0 +1,6 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+# set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake
new file mode 100644
index 000000000..eb97e5c55
--- /dev/null
+++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake
new file mode 100644
index 000000000..ffa5932c1
--- /dev/null
+++ b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/nrf52840_mdk_dongle.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake
index b4fe39fc0..693d7beed 100644
--- a/hw/bsp/nrf/boards/pca10056/board.cmake
+++ b/hw/bsp/nrf/boards/pca10056/board.cmake
@@ -2,7 +2,4 @@ set(MCU_VARIANT nrf52840)
 set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
 function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    NRF52840_XXAA
-    )
 endfunction()
diff --git a/hw/bsp/nrf/boards/pca10059/board.cmake b/hw/bsp/nrf/boards/pca10059/board.cmake
new file mode 100644
index 000000000..c79eb5964
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10059/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/pca10059.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake
index 1e72243c9..ca5399a3a 100644
--- a/hw/bsp/nrf/boards/pca10095/board.cmake
+++ b/hw/bsp/nrf/boards/pca10095/board.cmake
@@ -2,10 +2,6 @@ set(MCU_VARIANT nrf5340_application)
 set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf5340_xxaa_application.ld)
 
 function(update_board TARGET)
-  target_compile_definitions(${TARGET} PUBLIC
-    NRF5340_XXAA
-    NRF5340_XXAA_APPLICATION
-    )
   target_sources(${TARGET} PRIVATE
     ${NRFX_DIR}/drivers/src/nrfx_usbreg.c
     )
diff --git a/hw/bsp/nrf/boards/pca10100/board.cmake b/hw/bsp/nrf/boards/pca10100/board.cmake
new file mode 100644
index 000000000..c30026815
--- /dev/null
+++ b/hw/bsp/nrf/boards/pca10100/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52833)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52833_xxaa.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
new file mode 100644
index 000000000..693d7beed
--- /dev/null
+++ b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake
@@ -0,0 +1,5 @@
+set(MCU_VARIANT nrf52840)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 2b13249f4..6c24d3658 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -33,13 +33,20 @@ function(add_board_target BOARD_TARGET)
     add_library(${BOARD_TARGET} STATIC
       # driver
       ${NRFX_DIR}/drivers/src/nrfx_power.c
+      ${NRFX_DIR}/drivers/src/nrfx_spim.c
       ${NRFX_DIR}/drivers/src/nrfx_uarte.c
       # mcu
       ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c
       )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      CONFIG_GPIO_AS_PINRESET
-      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC CONFIG_GPIO_AS_PINRESET)
+
+    if (MCU_VARIANT STREQUAL "nrf52840")
+      target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52840_XXAA)
+    elseif (MCU_VARIANT STREQUAL "nrf52833")
+      target_compile_definitions(${BOARD_TARGET} PUBLIC NRF52833_XXAA)
+    elseif (MCU_VARIANT STREQUAL "nrf5340_application")
+      target_compile_definitions(${BOARD_TARGET} PUBLIC NRF5340_XXAA NRF5340_XXAA_APPLICATION)
+    endif ()
 
     if (TRACE_ETM STREQUAL "1")
       # ENABLE_TRACE will cause system_nrf5x.c to set up ETM trace
@@ -115,6 +122,7 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
+    #${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/src/device/usbd.h b/src/device/usbd.h
index b11c1a09d..782f538fd 100644
--- a/src/device/usbd.h
+++ b/src/device/usbd.h
@@ -50,8 +50,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr);
 
 // Task function should be called in main/rtos loop
 TU_ATTR_ALWAYS_INLINE static inline
-void tud_task (void)
-{
+void tud_task (void) {
   tud_task_ext(UINT32_MAX, false);
 }
 
@@ -80,8 +79,7 @@ bool tud_suspended(void);
 
 // Check if device is ready to transfer
 TU_ATTR_ALWAYS_INLINE static inline
-bool tud_ready(void)
-{
+bool tud_ready(void) {
   return tud_mounted() && !tud_suspended();
 }
 
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 9bcc1c6df..1b5038ef4 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -198,8 +198,7 @@ extern void hcd_event_handler(hcd_event_t const* event, bool in_isr);
 
 // Helper to send device attach event
 TU_ATTR_ALWAYS_INLINE static inline
-void hcd_event_device_attach(uint8_t rhport, bool in_isr)
-{
+void hcd_event_device_attach(uint8_t rhport, bool in_isr) {
   hcd_event_t event;
   event.rhport              = rhport;
   event.event_id            = HCD_EVENT_DEVICE_ATTACH;
@@ -211,8 +210,7 @@ void hcd_event_device_attach(uint8_t rhport, bool in_isr)
 
 // Helper to send device removal event
 TU_ATTR_ALWAYS_INLINE static inline
-void hcd_event_device_remove(uint8_t rhport, bool in_isr)
-{
+void hcd_event_device_remove(uint8_t rhport, bool in_isr) {
   hcd_event_t event;
   event.rhport              = rhport;
   event.event_id            = HCD_EVENT_DEVICE_REMOVE;
@@ -224,10 +222,8 @@ void hcd_event_device_remove(uint8_t rhport, bool in_isr)
 
 // Helper to send USB transfer event
 TU_ATTR_ALWAYS_INLINE static inline
-void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
-{
-  hcd_event_t event =
-  {
+void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr) {
+  hcd_event_t event = {
     .rhport   = 0, // TODO correct rhport
     .event_id = HCD_EVENT_XFER_COMPLETE,
     .dev_addr = dev_addr,
diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c
index 590dd9fcf..12d610bd6 100644
--- a/src/portable/template/dcd_template.c
+++ b/src/portable/template/dcd_template.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUSB_MCU == OPT_MCU_NONE
+#if CFG_TUD_ENABLED && CFG_TUSB_MCU == OPT_MCU_NONE
 
 #include "device/dcd.h"
 
@@ -141,4 +141,6 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
   (void) ep_addr;
 }
 
+
+
 #endif
diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c
new file mode 100644
index 000000000..3e3b91558
--- /dev/null
+++ b/src/portable/template/hcd_template.c
@@ -0,0 +1,162 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && CFG_TUSB_MCU == OPT_MCU_NONE
+
+#include "host/hcd.h"
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// optional hcd configuration, called by tuh_configure()
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  (void) cfg_id;
+  (void) cfg_param;
+
+  return false;
+}
+
+// Initialize controller to host mode
+bool hcd_init(uint8_t rhport) {
+  (void) rhport;
+
+  return false;
+}
+
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Enable USB interrupt
+void hcd_int_enable (uint8_t rhport) {
+  (void) rhport;
+}
+
+// Disable USB interrupt
+void hcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get frame number (1ms)
+uint32_t hcd_frame_number(uint8_t rhport) {
+  (void) rhport;
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+// Get the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t rhport) {
+  (void) rhport;
+
+  return false;
+}
+
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
+void hcd_port_reset(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Complete bus reset sequence, may be required by some controllers
+void hcd_port_reset_end(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get port link speed
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  (void) rhport;
+
+  return TUSB_SPEED_FULL;
+}
+
+// HCD closes all opened endpoints belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  (void) dev_addr;
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_desc;
+
+  return false;
+}
+
+// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  (void) buffer;
+  (void) buflen;
+
+  return false;
+}
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) setup_packet;
+
+  return false;
+}
+
+// clear stall, data toggle is also reset to DATA0
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+#endif
diff --git a/src/tusb.h b/src/tusb.h
index 37a521fa8..d6534ca28 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -64,7 +64,10 @@
   #if CFG_TUH_VENDOR
     #include "class/vendor/vendor_host.h"
   #endif
-
+#else
+  #ifndef tuh_int_handler
+  #define tuh_int_handler(_x)
+  #endif
 #endif
 
 //------------- DEVICE -------------//
@@ -118,6 +121,10 @@
   #if CFG_TUD_BTH
     #include "class/bth/bth_device.h"
   #endif
+#else
+  #ifndef tud_int_handler
+  #define tud_int_handler(_x)
+  #endif
 #endif
 
 

From 824e585e2b1f62d1ed03f480439e62e5410636b6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Aug 2023 14:06:57 +0700
Subject: [PATCH 2005/2085] ground works for hcd max3421e

---
 .../feather_nrf52840_express/board.cmake      |   4 +-
 .../boards/feather_nrf52840_express/board.h   |   7 +
 hw/bsp/nrf/family.c                           |  80 +++--
 hw/bsp/nrf/family.cmake                       |   2 +-
 hw/bsp/nrf/nrfx_config.h                      |   5 +-
 src/portable/analog/max3421e/hcd_max3421e.c   | 302 ++++++++++++++++++
 6 files changed, 369 insertions(+), 31 deletions(-)
 create mode 100644 src/portable/analog/max3421e/hcd_max3421e.c

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
index 0acbecf7a..78ed98225 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
@@ -1,6 +1,6 @@
 set(MCU_VARIANT nrf52840)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
-# set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+#set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
 function(update_board TARGET)
 endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index 8e6ce3230..e19f88a3c 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -45,6 +45,13 @@
 #define UART_RX_PIN     24
 #define UART_TX_PIN     25
 
+// SPI for USB host shield
+#define SPI_SCK_PIN      14
+#define SPI_MOSI_PIN     13
+#define SPI_MISO_PIN     15
+#define SPI_CS_PIN       27
+#define MAX3241E_INT_PIN 26
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 9ca666e36..b6ed15122 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -40,6 +40,7 @@
 #include "hal/nrf_gpio.h"
 #include "drivers/include/nrfx_power.h"
 #include "drivers/include/nrfx_uarte.h"
+#include "drivers/include/nrfx_spim.h"
 
 #ifdef SOFTDEVICE_PRESENT
 #include "nrf_sdm.h"
@@ -54,8 +55,7 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void USBD_IRQHandler(void)
-{
+void USBD_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -81,6 +81,7 @@ enum {
 #endif
 
 static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0);
+static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
 
 // tinyusb function that handles power event (detected, ready, removed)
 // We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
@@ -88,13 +89,11 @@ extern void tusb_hal_nrf_power_event(uint32_t event);
 
 
 // nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example)
-TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event)
-{
+TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
   tusb_hal_nrf_power_event((uint32_t) event);
 }
 
-void board_init(void)
-{
+void board_init(void) {
   // stop LF clock just in case we jump from application without reset
   NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
 
@@ -113,8 +112,7 @@ void board_init(void)
   SysTick_Config(SystemCoreClock/1000);
 
   // UART
-  nrfx_uarte_config_t uart_cfg =
-  {
+  nrfx_uarte_config_t uart_cfg = {
     .pseltxd   = UART_TX_PIN,
     .pselrxd   = UART_RX_PIN,
     .pselcts   = NRF_UARTE_PSEL_DISCONNECTED,
@@ -175,45 +173,78 @@ void board_init(void)
   if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED);
   if ( usb_reg & OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(USB_EVT_READY);
 #endif
+
+  (void) _spi;
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+  // USB host using max3421e usb controller via SPI
+  nrfx_spim_config_t cfg = {
+      .sck_pin        = SPI_SCK_PIN,
+      .mosi_pin       = SPI_MOSI_PIN,
+      .miso_pin       = SPI_MISO_PIN,
+      .ss_pin         = SPI_CS_PIN,
+      .ss_active_high = false,
+      .irq_priority   = 3,
+      .orc            = 0xFF,
+      // default setting 4 Mhz, Mode 0, MSB first
+      .frequency      = NRF_SPIM_FREQ_4M,
+      .mode           = NRF_SPIM_MODE_0,
+      .bit_order      = NRF_SPIM_BIT_ORDER_MSB_FIRST,
+  };
+
+  // no handler --> blocking
+  nrfx_spim_init(&_spi, &cfg, NULL, NULL);
+#endif
+
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+void board_led_write(bool state) {
+  nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 //  return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0;
+int board_uart_write(void const *buf, int len) {
+  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const *) buf, (size_t) len)) ? len : 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
+#endif
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+// API: SPI transfer with MAX3421E, must be implemented by application
+bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
+  (void) rhport;
+  nrfx_spim_xfer_desc_t xfer = {
+      .p_tx_buffer = tx_buf,
+      .tx_length   = tx_len,
+      .p_rx_buffer = rx_buf,
+      .rx_length   = rx_len,
+  };
+  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
+}
 #endif
 
 #ifdef SOFTDEVICE_PRESENT
@@ -251,8 +282,7 @@ void SD_EVT_IRQHandler(void)
   }
 }
 
-void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info)
-{
+void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
   (void) id;
   (void) pc;
   (void) info;
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 6c24d3658..527251e71 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -122,7 +122,7 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
-    #${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
+    ${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h
index 696a3fb04..d0f718c6c 100644
--- a/hw/bsp/nrf/nrfx_config.h
+++ b/hw/bsp/nrf/nrfx_config.h
@@ -9,9 +9,8 @@
 #define NRFX_UARTE_ENABLED   1
 #define NRFX_UARTE0_ENABLED  1
 
-#define NRFX_UARTE1_ENABLED  0
-#define NRFX_UARTE2_ENABLED  0
-#define NRFX_UARTE3_ENABLED  0
+#define NRFX_SPIM_ENABLED    1
+#define NRFX_SPIM0_ENABLED   1
 
 #define NRFX_PRS_ENABLED     0
 #define NRFX_USBREG_ENABLED  1
diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c
new file mode 100644
index 000000000..7b9d73e4e
--- /dev/null
+++ b/src/portable/analog/max3421e/hcd_max3421e.c
@@ -0,0 +1,302 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+
+#include "host/hcd.h"
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+// Command format is
+// Reg [7:3] | 0 [2] | Dir [1] | Ack [0]
+
+enum {
+  CMDBYTE_WRITE = 0x02,
+};
+
+enum {
+  RCVVFIFO_ADDR = 1u  << 3, // 0x08
+  SNDFIFO_ADDR  = 2u  << 3, // 0x10
+  SUDFIFO_ADDR  = 4u  << 3, // 0x20
+  RCVBC_ADDR    = 6u  << 3, // 0x30
+  SNDBC_ADDR    = 7u  << 3, // 0x38
+  USBIRQ_ADDR   = 13u << 3, // 0x68
+  USBIEN_ADDR   = 14u << 3, // 0x70
+  USBCTL_ADDR   = 15u << 3, // 0x78
+  CPUCTL_ADDR   = 16u << 3, // 0x80
+  PINCTL_ADDR   = 17u << 3, // 0x88
+  REVISION_ADDR = 18u << 3, // 0x90
+  HIRQ_ADDR     = 25u << 3, // 0xC8
+  HIEN_ADDR     = 26u << 3, // 0xD0
+  MODE_ADDR     = 27u << 3, // 0xD8
+  PERADDR_ADDR  = 28u << 3, // 0xE0
+  HCTL_ADDR     = 29u << 3, // 0xE8
+  HXFR_ADDR     = 30u << 3, // 0xF0
+  HRSL_ADDR     = 31u << 3, // 0xF8
+};
+
+enum {
+  USBIRQ_OSCOK_IRQ  = 1u << 0,
+  USBIRQ_NOVBUS_IRQ = 1u << 5,
+  USBIRQ_VBUS_IRQ   = 1u << 6,
+};
+
+enum {
+  USBCTL_PWRDOWN = 1u << 4,
+  USBCTL_CHIPRES = 1u << 5,
+};
+
+enum {
+  CPUCTL_IE        = 1u << 0,
+  CPUCTL_PULSEWID0 = 1u << 6,
+  CPUCTL_PULSEWID1 = 1u << 7,
+};
+
+enum {
+  PINCTL_GPXA     = 1u << 0,
+  PINCTL_GPXB     = 1u << 1,
+  PINCTL_POSINT   = 1u << 2,
+  PINCTL_INTLEVEL = 1u << 3,
+  PINCTL_FDUPSPI  = 1u << 4,
+};
+
+enum {
+  HIRQ_BUSEVENT_IRQ = 1u << 0,
+  HIRQ_RWU_IRQ      = 1u << 1,
+  HIRQ_RCVDAV_IRQ   = 1u << 2,
+  HIRQ_SNDBAV_IRQ   = 1u << 3,
+  HIRQ_SUSDN_IRQ    = 1u << 4,
+  HIRQ_CONDET_IRQ   = 1u << 5,
+  HIRQ_FRAME_IRQ    = 1u << 6,
+  HIRQ_HXFRDN_IRQ   = 1u << 7,
+};
+
+enum {
+  MODE_HOST      = 1u << 0,
+  MODE_LOWSPEED  = 1u << 1,
+  MODE_HUBPRE    = 1u << 2,
+  MODE_SOFKAENAB = 1u << 3,
+  MODE_SEPIRQ    = 1u << 4,
+  MODE_DELAYISO  = 1u << 5,
+  MODE_DMPULLDN  = 1u << 6,
+  MODE_DPPULLDN  = 1u << 7,
+};
+
+enum {
+  HCTL_BUSRST    = 1u << 1,
+  HCTL_FRMRST    = 1u << 2,
+  HCTL_SAMPLEBUS = 1u << 3,
+  HCTL_SIGRSM    = 1u << 4,
+  HCTL_RCVTOG0   = 1u << 5,
+  HCTL_RCVTOG1   = 1u << 6,
+  HCTL_SNDTOG0   = 1u << 7,
+  HCTL_SNDTOG1   = 1u << 8,
+};
+
+enum {
+  HXFR_EPNUM_MASK = 0x0f,
+  HXFR_SETUP      = 1u << 4,
+  HXFR_OUT_NIN    = 1u << 5,
+  HXFR_ISO        = 1u << 6,
+  HXFR_HS         = 1u << 7,
+};
+
+enum {
+  HRSL_RESULT_MASK = 0x0f,
+  HRSL_RCVTOGRD    = 1u << 4,
+  HRSL_SNDTOGRD    = 1u << 5,
+  HRSL_KSTATUS     = 1u << 6,
+  HRSL_JSTATUS     = 1u << 7,
+};
+
+// API: SPI transfer with MAX3421E, must be implemented by application
+bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
+
+// return HIRQ register since we are in full-duplex mode
+static uint8_t reg_write(uint8_t reg, uint8_t data) {
+  uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
+  uint8_t rx_buf[2] = {0, 0};
+  tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
+  return rx_buf[0];
+}
+
+static uint8_t reg_read(uint8_t reg) {
+  uint8_t tx_buf[2] = {reg, 0};
+  uint8_t rx_buf[2] = {0, 0};
+  return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0;
+}
+
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// optional hcd configuration, called by tuh_configure()
+bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
+  (void) rhport;
+  (void) cfg_id;
+  (void) cfg_param;
+
+  return false;
+}
+
+// Initialize controller to host mode
+bool hcd_init(uint8_t rhport) {
+  (void) rhport;
+
+  // full duplex, interrupt level (should be configurable)
+  reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL);
+
+  // reset
+  reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
+  reg_write(USBCTL_ADDR, 0);
+  while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) {
+    // wait for oscillator to stabilize
+  }
+
+  // Mode: Host and DP/DM pull down
+  reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
+
+  // Connection detection
+  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ /*| HIRQ_FRAME_IRQ */);
+
+  return false;
+}
+
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Enable USB interrupt
+void hcd_int_enable (uint8_t rhport) {
+  (void) rhport;
+}
+
+// Disable USB interrupt
+void hcd_int_disable(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get frame number (1ms)
+uint32_t hcd_frame_number(uint8_t rhport) {
+  (void) rhport;
+
+  return 0;
+}
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+// Get the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t rhport) {
+  (void) rhport;
+
+  return false;
+}
+
+// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
+// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
+void hcd_port_reset(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Complete bus reset sequence, may be required by some controllers
+void hcd_port_reset_end(uint8_t rhport) {
+  (void) rhport;
+}
+
+// Get port link speed
+tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
+  (void) rhport;
+
+  return TUSB_SPEED_FULL;
+}
+
+// HCD closes all opened endpoints belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
+  (void) rhport;
+  (void) dev_addr;
+}
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_desc;
+
+  return false;
+}
+
+// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+  (void) buffer;
+  (void) buflen;
+
+  return false;
+}
+
+// Abort a queued transfer. Note: it can only abort transfer that has not been started
+// Return true if a queued transfer is aborted, false if there is no transfer to abort
+bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) setup_packet;
+
+  return false;
+}
+
+// clear stall, data toggle is also reset to DATA0
+bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
+  (void) rhport;
+  (void) dev_addr;
+  (void) ep_addr;
+
+  return false;
+}
+
+#endif

From cacc96b25dc04865389357467b7a6d92d040ef36 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 18 Aug 2023 17:39:10 +0700
Subject: [PATCH 2006/2085] adding connection event handling, add nrf gpio
 interrupt for max2341e interrupt pin

---
 .../boards/feather_nrf52840_express/board.h   |  2 +-
 hw/bsp/nrf/family.c                           | 55 +++++++++-----
 hw/bsp/nrf/family.cmake                       |  2 +
 hw/bsp/nrf/nrfx_config.h                      |  2 +-
 hw/bsp/nrf/nrfx_glue.h                        | 69 +++++++++++++++++
 src/portable/analog/max3421e/hcd_max3421e.c   | 76 ++++++++++++++++++-
 6 files changed, 184 insertions(+), 22 deletions(-)

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index e19f88a3c..7f042142e 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -50,7 +50,7 @@
 #define SPI_MOSI_PIN     13
 #define SPI_MISO_PIN     15
 #define SPI_CS_PIN       27
-#define MAX3241E_INT_PIN 26
+#define MAX3241E_INTR_PIN 26
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index b6ed15122..e58ee845b 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -38,6 +38,7 @@
 
 #include "nrfx.h"
 #include "hal/nrf_gpio.h"
+#include "drivers/include/nrfx_gpiote.h"
 #include "drivers/include/nrfx_power.h"
 #include "drivers/include/nrfx_uarte.h"
 #include "drivers/include/nrfx_spim.h"
@@ -81,18 +82,45 @@ enum {
 #endif
 
 static nrfx_uarte_t _uart_id = NRFX_UARTE_INSTANCE(0);
-static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
 
 // tinyusb function that handles power event (detected, ready, removed)
 // We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
 extern void tusb_hal_nrf_power_event(uint32_t event);
 
-
 // nrf power callback, could be unused if SD is enabled or usb is disabled (board_test example)
 TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
   tusb_hal_nrf_power_event((uint32_t) event);
 }
 
+//------------- Host using MAX2341E -------------//
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
+
+void max2342e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
+  if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return;
+
+  tuh_int_handler(1);
+}
+
+// API: SPI transfer with MAX3421E, must be implemented by application
+bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
+  (void) rhport;
+  nrfx_spim_xfer_desc_t xfer = {
+      .p_tx_buffer = tx_buf,
+      .tx_length   = tx_len,
+      .p_rx_buffer = rx_buf,
+      .rx_length   = rx_len,
+  };
+  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
+}
+
+#endif
+
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 void board_init(void) {
   // stop LF clock just in case we jump from application without reset
   NRF_CLOCK->TASKS_LFCLKSTOP = 1UL;
@@ -174,7 +202,6 @@ void board_init(void) {
   if ( usb_reg & OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(USB_EVT_READY);
 #endif
 
-  (void) _spi;
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
   // USB host using max3421e usb controller via SPI
   nrfx_spim_config_t cfg = {
@@ -193,6 +220,14 @@ void board_init(void) {
 
   // no handler --> blocking
   nrfx_spim_init(&_spi, &cfg, NULL, NULL);
+
+  // max3421e interrupt pin
+  nrfx_gpiote_init(1);
+  nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
+  in_config.pull = NRF_GPIO_PIN_PULLUP;
+
+  nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max2342e_int_handler);
+  nrfx_gpiote_in_event_enable(MAX3241E_INTR_PIN, true);
 #endif
 
 }
@@ -233,20 +268,6 @@ uint32_t board_millis(void) {
 
 #endif
 
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
-// API: SPI transfer with MAX3421E, must be implemented by application
-bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
-  (void) rhport;
-  nrfx_spim_xfer_desc_t xfer = {
-      .p_tx_buffer = tx_buf,
-      .tx_length   = tx_len,
-      .p_rx_buffer = rx_buf,
-      .rx_length   = rx_len,
-  };
-  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
-}
-#endif
-
 #ifdef SOFTDEVICE_PRESENT
 // process SOC event from SD
 uint32_t proc_soc(void)
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 527251e71..8bf7bcb52 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -32,6 +32,8 @@ function(add_board_target BOARD_TARGET)
   if (NOT TARGET ${BOARD_TARGET})
     add_library(${BOARD_TARGET} STATIC
       # driver
+      ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c
+      ${NRFX_DIR}/drivers/src/nrfx_gpiote.c
       ${NRFX_DIR}/drivers/src/nrfx_power.c
       ${NRFX_DIR}/drivers/src/nrfx_spim.c
       ${NRFX_DIR}/drivers/src/nrfx_uarte.c
diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h
index d0f718c6c..e3d0ea91b 100644
--- a/hw/bsp/nrf/nrfx_config.h
+++ b/hw/bsp/nrf/nrfx_config.h
@@ -5,6 +5,7 @@
 #define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY  7
 
 #define NRFX_CLOCK_ENABLED   0
+#define NRFX_GPIOTE_ENABLED  1
 
 #define NRFX_UARTE_ENABLED   1
 #define NRFX_UARTE0_ENABLED  1
@@ -41,5 +42,4 @@
     #error "Unknown device."
 #endif
 
-
 #endif // NRFX_CONFIG_H__
diff --git a/hw/bsp/nrf/nrfx_glue.h b/hw/bsp/nrf/nrfx_glue.h
index cdf49b4ab..ef756c670 100644
--- a/hw/bsp/nrf/nrfx_glue.h
+++ b/hw/bsp/nrf/nrfx_glue.h
@@ -220,6 +220,75 @@ static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number)
 
 /** @} */
 
+//------------------------------------------------------------------------------
+
+#include <soc/nrfx_atomic.h>
+
+/**
+ * @brief Atomic 32 bit unsigned type.
+ */
+#define nrfx_atomic_t               nrfx_atomic_u32_t
+
+/**
+ * @brief Stores value to an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value to store.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value)
+
+/**
+ * @brief Performs logical OR operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of OR operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_OR(p_data, value)   nrfx_atomic_u32_fetch_or(p_data, value)
+
+/**
+ * @brief Performs logical AND operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of AND operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_AND(p_data, value)   nrfx_atomic_u32_fetch_and(p_data, value)
+
+/**
+ * @brief Performs logical XOR operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of XOR operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_XOR(p_data, value)   nrfx_atomic_u32_fetch_xor(p_data, value)
+
+/**
+ * @brief Performs logical ADD operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of ADD operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_ADD(p_data, value)   nrfx_atomic_u32_fetch_add(p_data, value)
+
+/**
+ * @brief Performs logical SUB operation on an atomic object and returns previously stored value.
+ *
+ * @param[in] p_data  Atomic memory pointer.
+ * @param[in] value   Value of second operand of SUB operation.
+ *
+ * @return Old value stored into atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_SUB(p_data, value)   nrfx_atomic_u32_fetch_sub(p_data, value)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c
index 7b9d73e4e..a89581b9c 100644
--- a/src/portable/analog/max3421e/hcd_max3421e.c
+++ b/src/portable/analog/max3421e/hcd_max3421e.c
@@ -136,6 +136,20 @@ enum {
   HRSL_JSTATUS     = 1u << 7,
 };
 
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+//typedef struct {
+//  uint8_t mode
+//} max2341e_data_t;
+//
+//max2341e_data_t max2341e_data;
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
 // API: SPI transfer with MAX3421E, must be implemented by application
 bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
 
@@ -144,6 +158,7 @@ static uint8_t reg_write(uint8_t reg, uint8_t data) {
   uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
   uint8_t rx_buf[2] = {0, 0};
   tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
+  TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
   return rx_buf[0];
 }
 
@@ -167,6 +182,48 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   return false;
 }
 
+tusb_speed_t handle_connect_irq(uint8_t rhport) {
+  (void) rhport;
+
+  uint8_t const hrsl = reg_read(HRSL_ADDR);
+  uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
+
+  tusb_speed_t speed;
+  uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
+
+  switch(jk) {
+    case 0x00:
+      // SEO is disconnected
+      speed = TUSB_SPEED_INVALID;
+      break;
+
+    case (HRSL_JSTATUS | HRSL_KSTATUS):
+      // SE1 is illegal
+      speed = TUSB_SPEED_INVALID;
+      break;
+
+    default: {
+      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
+      uint8_t const mode = reg_read(MODE_ADDR);
+      uint8_t const ls_bit = mode & MODE_LOWSPEED;
+
+      if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) {
+        speed = TUSB_SPEED_LOW;
+        new_mode |= MODE_LOWSPEED;
+      } else {
+        speed =  TUSB_SPEED_FULL;
+      }
+
+      new_mode |= MODE_SOFKAENAB; // enable SOF since there is new device
+
+      break;
+    }
+  }
+
+  reg_write(MODE_ADDR, new_mode);
+  return speed;
+}
+
 // Initialize controller to host mode
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
@@ -184,15 +241,28 @@ bool hcd_init(uint8_t rhport) {
   // Mode: Host and DP/DM pull down
   reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
 
-  // Connection detection
-  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ /*| HIRQ_FRAME_IRQ */);
+  // Enable Connection IRQ
+  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ);
 
-  return false;
+  // Note: if device is already connected, CONDET IRQ may not be triggered. We need to detect it by sampling bus signal
+  reg_write(HCTL_ADDR, HCTL_SAMPLEBUS);
+  while( !(reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS) ) {}
+
+  handle_connect_irq(rhport);
+  reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
+
+  // Enable Interrupt pin
+  reg_write(CPUCTL_ADDR, CPUCTL_IE);
+
+  return true;
 }
 
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport) {
   (void) rhport;
+
+  uint8_t hirq = reg_read(HIRQ_ADDR);
+  TU_LOG3_INT(hirq);
 }
 
 // Enable USB interrupt

From b4134394166c1f77463b5cb62f28cff465fde174 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 22 Aug 2023 19:57:59 +0700
Subject: [PATCH 2007/2085] able to detect new device and start enumerating

---
 src/portable/analog/max3421e/hcd_max3421e.c | 70 +++++++++++++++------
 1 file changed, 51 insertions(+), 19 deletions(-)

diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c
index a89581b9c..870c616a9 100644
--- a/src/portable/analog/max3421e/hcd_max3421e.c
+++ b/src/portable/analog/max3421e/hcd_max3421e.c
@@ -140,11 +140,13 @@ enum {
 //
 //--------------------------------------------------------------------+
 
-//typedef struct {
-//  uint8_t mode
-//} max2341e_data_t;
-//
-//max2341e_data_t max2341e_data;
+typedef struct {
+  uint8_t mode;
+
+  volatile uint16_t frame_count;
+} max2341e_data_t;
+
+static max2341e_data_t _hcd_data;
 
 //--------------------------------------------------------------------+
 //
@@ -168,6 +170,11 @@ static uint8_t reg_read(uint8_t reg) {
   return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0;
 }
 
+static inline uint8_t mode_write(uint8_t data) {
+  _hcd_data.mode = data;
+  return reg_write(MODE_ADDR, data);
+}
+
 
 //--------------------------------------------------------------------+
 // Controller API
@@ -220,7 +227,8 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
     }
   }
 
-  reg_write(MODE_ADDR, new_mode);
+  mode_write(new_mode);
+  TU_LOG2_INT(speed);
   return speed;
 }
 
@@ -228,6 +236,8 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
+  tu_memclr(&_hcd_data, sizeof(_hcd_data));
+
   // full duplex, interrupt level (should be configurable)
   reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL);
 
@@ -239,17 +249,21 @@ bool hcd_init(uint8_t rhport) {
   }
 
   // Mode: Host and DP/DM pull down
-  reg_write(MODE_ADDR, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
+  mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
 
   // Enable Connection IRQ
-  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ);
+  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ);
 
-  // Note: if device is already connected, CONDET IRQ may not be triggered. We need to detect it by sampling bus signal
+  #if 0
+  // Note: if device is already connected, CONDET IRQ may not be triggered.
+  // We need to detect it by sampling bus signal. FIXME not working
   reg_write(HCTL_ADDR, HCTL_SAMPLEBUS);
-  while( !(reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS) ) {}
+  while ( reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS ) {}
 
-  handle_connect_irq(rhport);
-  reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
+  if ( TUSB_SPEED_INVALID != handle_connect_irq(rhport) ) {
+    reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); // clear connect irq
+  }
+  #endif
 
   // Enable Interrupt pin
   reg_write(CPUCTL_ADDR, CPUCTL_IE);
@@ -262,7 +276,26 @@ void hcd_int_handler(uint8_t rhport) {
   (void) rhport;
 
   uint8_t hirq = reg_read(HIRQ_ADDR);
-  TU_LOG3_INT(hirq);
+  TU_LOG3_HEX(hirq);
+
+  if (hirq & HIRQ_CONDET_IRQ) {
+    tusb_speed_t speed = handle_connect_irq(rhport);
+
+    if (speed == TUSB_SPEED_INVALID) {
+      hcd_event_device_remove(rhport, true);
+    }else {
+      hcd_event_device_attach(rhport, true);
+    }
+  }
+
+  if (hirq & HIRQ_FRAME_IRQ) {
+    _hcd_data.frame_count++;
+  }
+
+  // clear all interrupt
+  if ( hirq ) {
+    reg_write(HIRQ_ADDR, hirq);
+  }
 }
 
 // Enable USB interrupt
@@ -278,8 +311,7 @@ void hcd_int_disable(uint8_t rhport) {
 // Get frame number (1ms)
 uint32_t hcd_frame_number(uint8_t rhport) {
   (void) rhport;
-
-  return 0;
+  return (uint32_t ) _hcd_data.frame_count;
 }
 
 //--------------------------------------------------------------------+
@@ -289,26 +321,26 @@ uint32_t hcd_frame_number(uint8_t rhport) {
 // Get the current connect status of roothub port
 bool hcd_port_connect_status(uint8_t rhport) {
   (void) rhport;
-
-  return false;
+  return (_hcd_data.mode & MODE_SOFKAENAB) ? true : false;
 }
 
 // Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
 // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
 void hcd_port_reset(uint8_t rhport) {
   (void) rhport;
+  reg_write(HCTL_ADDR, HCTL_BUSRST);
 }
 
 // Complete bus reset sequence, may be required by some controllers
 void hcd_port_reset_end(uint8_t rhport) {
   (void) rhport;
+  reg_write(HCTL_ADDR, 0);
 }
 
 // Get port link speed
 tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
   (void) rhport;
-
-  return TUSB_SPEED_FULL;
+  return (_hcd_data.mode & MODE_LOWSPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
 }
 
 // HCD closes all opened endpoints belong to this device

From 274578ff46c31b231b3553dc9a20895646313130 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 22 Aug 2023 23:17:12 +0700
Subject: [PATCH 2008/2085] able to send setup packet

---
 .../boards/feather_nrf52840_express/board.h   |   8 +-
 hw/bsp/nrf/family.c                           |  36 +++-
 src/host/hcd.h                                |   2 +-
 src/host/usbh.c                               |  32 +---
 src/portable/analog/max3421e/hcd_max3421e.c   | 173 ++++++++++++++----
 5 files changed, 179 insertions(+), 72 deletions(-)

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index 7f042142e..e6e7590ac 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -46,10 +46,10 @@
 #define UART_TX_PIN     25
 
 // SPI for USB host shield
-#define SPI_SCK_PIN      14
-#define SPI_MOSI_PIN     13
-#define SPI_MISO_PIN     15
-#define SPI_CS_PIN       27
+#define MAX3421E_SCK_PIN  14
+#define MAX3421E_MOSI_PIN 13
+#define MAX3421E_MISO_PIN 15
+#define MAX3421E_CS_PIN   27
 #define MAX3241E_INTR_PIN 26
 
 #ifdef __cplusplus
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index e58ee845b..862f67bc7 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -96,22 +96,38 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
 
-void max2342e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
+void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
   if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return;
 
   tuh_int_handler(1);
 }
 
+static inline void max3421e_cs_assert(bool active) {
+  nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
+}
+
+//--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
-bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
+//--------------------------------------------------------------------+
+
+bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len,
+                               uint8_t * rx_buf, size_t rx_len, bool keep_cs) {
   (void) rhport;
+
+  max3421e_cs_assert(true);
+
   nrfx_spim_xfer_desc_t xfer = {
       .p_tx_buffer = tx_buf,
       .tx_length   = tx_len,
       .p_rx_buffer = rx_buf,
       .rx_length   = rx_len,
   };
-  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
+
+  bool ret = (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
+
+  if ( !keep_cs ) max3421e_cs_assert(false);
+
+  return ret;
 }
 
 #endif
@@ -203,12 +219,16 @@ void board_init(void) {
 #endif
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+  // manually manage CS
+  nrf_gpio_cfg_output(MAX3421E_CS_PIN);
+  max3421e_cs_assert(false);
+
   // USB host using max3421e usb controller via SPI
   nrfx_spim_config_t cfg = {
-      .sck_pin        = SPI_SCK_PIN,
-      .mosi_pin       = SPI_MOSI_PIN,
-      .miso_pin       = SPI_MISO_PIN,
-      .ss_pin         = SPI_CS_PIN,
+      .sck_pin        = MAX3421E_SCK_PIN,
+      .mosi_pin       = MAX3421E_MOSI_PIN,
+      .miso_pin       = MAX3421E_MISO_PIN,
+      .ss_pin         = NRFX_SPIM_PIN_NOT_USED,
       .ss_active_high = false,
       .irq_priority   = 3,
       .orc            = 0xFF,
@@ -226,7 +246,7 @@ void board_init(void) {
   nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
   in_config.pull = NRF_GPIO_PIN_PULLUP;
 
-  nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max2342e_int_handler);
+  nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler);
   nrfx_gpiote_in_event_enable(MAX3241E_INTR_PIN, true);
 #endif
 
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 1b5038ef4..079877b79 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -177,7 +177,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
 bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
 
 // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
+bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]);
 
 // clear stall, data toggle is also reset to DATA0
 bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 5423df669..7a09f5b6e 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -552,8 +552,7 @@ static void _control_blocking_complete_cb(tuh_xfer_t* xfer)
 }
 
 // TODO timeout_ms is not supported yet
-bool tuh_control_xfer (tuh_xfer_t* xfer)
-{
+bool tuh_control_xfer (tuh_xfer_t* xfer) {
   // EP0 with setup packet
   TU_VERIFY(xfer->ep_addr == 0 && xfer->setup);
 
@@ -565,8 +564,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
   (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
 
   bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
-  if (is_idle)
-  {
+  if (is_idle) {
     _ctrl_xfer.stage       = CONTROL_STAGE_SETUP;
     _ctrl_xfer.daddr       = daddr;
     _ctrl_xfer.actual_len  = 0;
@@ -588,11 +586,9 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
   TU_LOG_PTR(CFG_TUH_LOG_LEVEL, xfer->setup);
   TU_LOG_USBH("\r\n");
 
-  if (xfer->complete_cb)
-  {
+  if (xfer->complete_cb) {
     TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
-  }else
-  {
+  }else {
     // blocking if complete callback is not provided
     // change callback to internal blocking, and result as user argument
     volatile xfer_result_t result = XFER_RESULT_INVALID;
@@ -656,15 +652,13 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result)
   }
 }
 
-static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
-{
+static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
   (void) ep_addr;
 
   const uint8_t rhport = usbh_get_rhport(dev_addr);
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
-  if (XFER_RESULT_SUCCESS != result)
-  {
+  if (XFER_RESULT_SUCCESS != result) {
     TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
     #if CFG_TUSB_DEBUG == 1
     TU_LOG1_PTR(request);
@@ -673,13 +667,10 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 
     // terminate transfer if any stage failed
     _xfer_complete(dev_addr, result);
-  }else
-  {
-    switch(_ctrl_xfer.stage)
-    {
+  }else {
+    switch(_ctrl_xfer.stage) {
       case CONTROL_STAGE_SETUP:
-        if (request->wLength)
-        {
+        if (request->wLength) {
           // DATA stage: initial data toggle is always 1
           _set_control_xfer_stage(CONTROL_STAGE_DATA);
           TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) );
@@ -688,8 +679,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
         TU_ATTR_FALLTHROUGH;
 
       case CONTROL_STAGE_DATA:
-        if (request->wLength)
-        {
+        if (request->wLength) {
           TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr);
           TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2);
         }
@@ -1538,9 +1528,7 @@ static bool enum_new_device(hcd_event_t* event)
     xfer.result    = XFER_RESULT_SUCCESS;
     xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
 
-
     process_enumeration(&xfer);
-
   }
 #if CFG_TUH_HUB
   else
diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421e/hcd_max3421e.c
index 870c616a9..c9596f695 100644
--- a/src/portable/analog/max3421e/hcd_max3421e.c
+++ b/src/portable/analog/max3421e/hcd_max3421e.c
@@ -136,30 +136,64 @@ enum {
   HRSL_JSTATUS     = 1u << 7,
 };
 
+enum {
+  HRSL_SUCCESS = 0,
+  HRSL_BUSY,
+  HRSL_BAD_REQ,
+  HRSL_UNDEF,
+  HRSL_NAK,
+  HRSL_STALL,
+  HRSL_TOG_ERR,
+  HRSL_WRONG_PID,
+  HRSL_BAD_BYTECOUNT,
+  HRSL_PID_ERR,
+  HRSL_PKT_ERR,
+  HRSL_CRC_ERR,
+  HRSL_K_ERR,
+  HRSL_J_ERR,
+  HRSL_TIMEOUT,
+  HRSL_BABBLE,
+};
+
+
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
 typedef struct {
+  // cached register
   uint8_t mode;
+  uint8_t peraddr;
+  uint8_t hxfr;
 
   volatile uint16_t frame_count;
+
+  struct {
+    uint16_t packet_size;
+    uint16_t total_len;
+    uint8_t xfer_type;
+  }ep[8][2];
 } max2341e_data_t;
 
 static max2341e_data_t _hcd_data;
 
 //--------------------------------------------------------------------+
-//
+// API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
 
-// API: SPI transfer with MAX3421E, must be implemented by application
-bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
+bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len,
+                               uint8_t * rx_buf, size_t rx_len, bool keep_cs);
+//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled);
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
 
 // return HIRQ register since we are in full-duplex mode
 static uint8_t reg_write(uint8_t reg, uint8_t data) {
   uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
   uint8_t rx_buf[2] = {0, 0};
-  tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
+  tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false);
   TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
   return rx_buf[0];
 }
@@ -167,7 +201,7 @@ static uint8_t reg_write(uint8_t reg, uint8_t data) {
 static uint8_t reg_read(uint8_t reg) {
   uint8_t tx_buf[2] = {reg, 0};
   uint8_t rx_buf[2] = {0, 0};
-  return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2) ? rx_buf[1] : 0;
+  return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false) ? rx_buf[1] : 0;
 }
 
 static inline uint8_t mode_write(uint8_t data) {
@@ -175,6 +209,24 @@ static inline uint8_t mode_write(uint8_t data) {
   return reg_write(MODE_ADDR, data);
 }
 
+static inline uint8_t peraddr_write(uint8_t data) {
+  if ( _hcd_data.peraddr == data ) return 0; // no need to change address
+
+  _hcd_data.peraddr = data;
+  return reg_write(PERADDR_ADDR, data);
+}
+
+static inline uint8_t hxfr_write(uint8_t data) {
+  _hcd_data.hxfr = data;
+  return reg_write(HXFR_ADDR, data);
+}
+
+static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
+  uint8_t tx_buf[1] = {reg | CMDBYTE_WRITE};
+  tuh_max3421e_spi_xfer_api(0, tx_buf, 1, NULL, 0, true);
+  tuh_max3421e_spi_xfer_api(0, buffer, len, NULL, 0, false);
+}
+
 
 //--------------------------------------------------------------------+
 // Controller API
@@ -252,7 +304,7 @@ bool hcd_init(uint8_t rhport) {
   mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
 
   // Enable Connection IRQ
-  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ);
+  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ);
 
   #if 0
   // Note: if device is already connected, CONDET IRQ may not be triggered.
@@ -271,33 +323,6 @@ bool hcd_init(uint8_t rhport) {
   return true;
 }
 
-// Interrupt Handler
-void hcd_int_handler(uint8_t rhport) {
-  (void) rhport;
-
-  uint8_t hirq = reg_read(HIRQ_ADDR);
-  TU_LOG3_HEX(hirq);
-
-  if (hirq & HIRQ_CONDET_IRQ) {
-    tusb_speed_t speed = handle_connect_irq(rhport);
-
-    if (speed == TUSB_SPEED_INVALID) {
-      hcd_event_device_remove(rhport, true);
-    }else {
-      hcd_event_device_attach(rhport, true);
-    }
-  }
-
-  if (hirq & HIRQ_FRAME_IRQ) {
-    _hcd_data.frame_count++;
-  }
-
-  // clear all interrupt
-  if ( hirq ) {
-    reg_write(HIRQ_ADDR, hirq);
-  }
-}
-
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport) {
   (void) rhport;
@@ -359,7 +384,12 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
   (void) dev_addr;
   (void) ep_desc;
 
-  return false;
+  uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
+  uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
+
+  _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc);
+
+  return true;
 }
 
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
@@ -384,12 +414,18 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 }
 
 // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
+bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
   (void) rhport;
-  (void) dev_addr;
+  (void) daddr;
   (void) setup_packet;
 
-  return false;
+  _hcd_data.ep[0][0].total_len = 8;
+
+  peraddr_write(daddr);
+  fifo_write(SUDFIFO_ADDR, setup_packet, 8);
+  hxfr_write(HXFR_SETUP);
+
+  return true;
 }
 
 // clear stall, data toggle is also reset to DATA0
@@ -401,4 +437,67 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport) {
+  uint8_t hirq = reg_read(HIRQ_ADDR);
+  TU_LOG3_HEX(hirq);
+
+  if (hirq & HIRQ_CONDET_IRQ) {
+    tusb_speed_t speed = handle_connect_irq(rhport);
+
+    if (speed == TUSB_SPEED_INVALID) {
+      hcd_event_device_remove(rhport, true);
+    }else {
+      hcd_event_device_attach(rhport, true);
+    }
+  }
+
+  if (hirq & HIRQ_FRAME_IRQ) {
+    _hcd_data.frame_count++;
+  }
+
+  if (hirq & HIRQ_HXFRDN_IRQ) {
+    uint8_t const hrsl = reg_read(HRSL_ADDR);
+    uint8_t const result = hrsl & HRSL_RESULT_MASK;
+    uint8_t xfer_result;
+
+    TU_LOG3("HRSL: %02X\r\n", hrsl);
+    switch(result) {
+      case HRSL_SUCCESS:
+        xfer_result = XFER_RESULT_SUCCESS;
+        break;
+
+      case HRSL_STALL:
+        xfer_result = XFER_RESULT_STALLED;
+        break;
+
+      default:
+        xfer_result = XFER_RESULT_FAILED;
+        break;
+    }
+
+    uint8_t ep_dir = 0;
+    uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+    uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
+
+    if ( xfer_type & HXFR_SETUP ) {
+      // SETUP transfer
+      ep_dir = 0;
+    }else if ( !(xfer_type & HXFR_OUT_NIN) ) {
+      // IN transfer
+      ep_dir = 1;
+    }
+
+    uint8_t const ep_addr = tu_edpt_addr(ep_num, ep_dir);
+    uint16_t xferred_len = _hcd_data.ep[ep_num][ep_dir].total_len;
+
+    hcd_event_xfer_complete(_hcd_data.peraddr, ep_addr, xferred_len, xfer_result, true);
+  }
+
+  // clear all interrupt
+  if ( hirq ) {
+    reg_write(HIRQ_ADDR, hirq);
+  }
+}
+
 #endif

From e3f3179924f7c84c4bb3e69234720f9afc178727 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 23 Aug 2023 15:08:12 +0700
Subject: [PATCH 2009/2085] able to get 8 byte descriptor, but read(RCVBC)
 always return 0

- rename max3421e to max3421
- fix incorrect bitmask for HCTL, fix initial device connect
- fix bus reset cause connect IRQ
---
 hw/bsp/nrf/family.c                           |  24 +-
 hw/bsp/nrf/family.cmake                       |   2 +-
 src/host/hcd.h                                |   2 +-
 .../hcd_max3421e.c => max3421/hcd_max3421.c}  | 284 ++++++++++++------
 4 files changed, 208 insertions(+), 104 deletions(-)
 rename src/portable/analog/{max3421e/hcd_max3421e.c => max3421/hcd_max3421.c} (67%)

diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 862f67bc7..45a5166a7 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -93,7 +93,7 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 }
 
 //------------- Host using MAX2341E -------------//
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
 
 void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
@@ -102,19 +102,17 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
   tuh_int_handler(1);
 }
 
-static inline void max3421e_cs_assert(bool active) {
-  nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
-}
-
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
 
-bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len,
-                               uint8_t * rx_buf, size_t rx_len, bool keep_cs) {
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
+  nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
+}
 
-  max3421e_cs_assert(true);
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
+  (void) rhport;
 
   nrfx_spim_xfer_desc_t xfer = {
       .p_tx_buffer = tx_buf,
@@ -123,11 +121,7 @@ bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx
       .rx_length   = rx_len,
   };
 
-  bool ret = (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
-
-  if ( !keep_cs ) max3421e_cs_assert(false);
-
-  return ret;
+  return (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
 }
 
 #endif
@@ -218,10 +212,10 @@ void board_init(void) {
   if ( usb_reg & OUTPUTRDY_Msk  ) tusb_hal_nrf_power_event(USB_EVT_READY);
 #endif
 
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
   // manually manage CS
   nrf_gpio_cfg_output(MAX3421E_CS_PIN);
-  max3421e_cs_assert(false);
+  tuh_max3421_spi_cs_api(0, false);
 
   // USB host using max3421e usb controller via SPI
   nrfx_spim_config_t cfg = {
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index 8bf7bcb52..ff6b882ce 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -124,7 +124,7 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
-    ${TOP}/src/portable/analog/max3421e/hcd_max3421e.c
+    ${TOP}/src/portable/analog/max3421/hcd_max3421.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 079877b79..1f01a1a2f 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -170,7 +170,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
 
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
 
 // Abort a queued transfer. Note: it can only abort transfer that has not been started
 // Return true if a queued transfer is aborted, false if there is no transfer to abort
diff --git a/src/portable/analog/max3421e/hcd_max3421e.c b/src/portable/analog/max3421/hcd_max3421.c
similarity index 67%
rename from src/portable/analog/max3421e/hcd_max3421e.c
rename to src/portable/analog/max3421/hcd_max3421.c
index c9596f695..edcb6ca6f 100644
--- a/src/portable/analog/max3421e/hcd_max3421e.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -26,7 +26,7 @@
 
 #include "tusb_option.h"
 
-#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421E) && CFG_TUH_MAX3421E
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
 #include "host/hcd.h"
 
@@ -110,14 +110,14 @@ enum {
 };
 
 enum {
-  HCTL_BUSRST    = 1u << 1,
-  HCTL_FRMRST    = 1u << 2,
-  HCTL_SAMPLEBUS = 1u << 3,
-  HCTL_SIGRSM    = 1u << 4,
-  HCTL_RCVTOG0   = 1u << 5,
-  HCTL_RCVTOG1   = 1u << 6,
-  HCTL_SNDTOG0   = 1u << 7,
-  HCTL_SNDTOG1   = 1u << 8,
+  HCTL_BUSRST    = 1u << 0,
+  HCTL_FRMRST    = 1u << 1,
+  HCTL_SAMPLEBUS = 1u << 2,
+  HCTL_SIGRSM    = 1u << 3,
+  HCTL_RCVTOG0   = 1u << 4,
+  HCTL_RCVTOG1   = 1u << 5,
+  HCTL_SNDTOG0   = 1u << 6,
+  HCTL_SNDTOG1   = 1u << 7,
 };
 
 enum {
@@ -155,45 +155,73 @@ enum {
   HRSL_BABBLE,
 };
 
+enum {
+  DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ
+};
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
 typedef struct {
+  uint8_t xfer_type;
+  uint8_t data_toggle;
+  uint16_t packet_size;
+
+  uint16_t total_len;
+  uint16_t xferred_len;
+  uint8_t* buf;
+} hcd_ep_t;
+
+typedef struct {
+  bool inited;
+
   // cached register
+  uint8_t sndbc;
   uint8_t mode;
   uint8_t peraddr;
   uint8_t hxfr;
 
   volatile uint16_t frame_count;
 
-  struct {
-    uint16_t packet_size;
-    uint16_t total_len;
-    uint8_t xfer_type;
-  }ep[8][2];
-} max2341e_data_t;
+  hcd_ep_t ep[8][2];
+} max2341_data_t;
 
-static max2341e_data_t _hcd_data;
+static max2341_data_t _hcd_data;
 
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
 
-bool tuh_max3421e_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len,
-                               uint8_t * rx_buf, size_t rx_len, bool keep_cs);
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
+
 //void tuh_max3421e_int_enable(uint8_t rhport, bool enabled);
 
 //--------------------------------------------------------------------+
 //
 //--------------------------------------------------------------------+
 
+static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
+  reg |= CMDBYTE_WRITE;
+
+  tuh_max3421_spi_cs_api(0, true);
+
+  tuh_max3421_spi_xfer_api(0, &reg, 1, NULL, 0);
+  tuh_max3421_spi_xfer_api(0, buffer, len, NULL, 0);
+
+  tuh_max3421_spi_cs_api(0, false);
+}
+
 // return HIRQ register since we are in full-duplex mode
 static uint8_t reg_write(uint8_t reg, uint8_t data) {
   uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
   uint8_t rx_buf[2] = {0, 0};
-  tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false);
+
+  tuh_max3421_spi_cs_api(0, true);
+  tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
+  tuh_max3421_spi_cs_api(0, false);
+
   TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
   return rx_buf[0];
 }
@@ -201,7 +229,12 @@ static uint8_t reg_write(uint8_t reg, uint8_t data) {
 static uint8_t reg_read(uint8_t reg) {
   uint8_t tx_buf[2] = {reg, 0};
   uint8_t rx_buf[2] = {0, 0};
-  return tuh_max3421e_spi_xfer_api(0, tx_buf, 2, rx_buf, 2, false) ? rx_buf[1] : 0;
+
+  tuh_max3421_spi_cs_api(0, true);
+  bool ret = tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
+  tuh_max3421_spi_cs_api(0, false);
+
+  return ret ? rx_buf[1] : 0;
 }
 
 static inline uint8_t mode_write(uint8_t data) {
@@ -221,10 +254,9 @@ static inline uint8_t hxfr_write(uint8_t data) {
   return reg_write(HXFR_ADDR, data);
 }
 
-static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
-  uint8_t tx_buf[1] = {reg | CMDBYTE_WRITE};
-  tuh_max3421e_spi_xfer_api(0, tx_buf, 1, NULL, 0, true);
-  tuh_max3421e_spi_xfer_api(0, buffer, len, NULL, 0, false);
+static inline uint8_t sndbc_write(uint8_t data) {
+  _hcd_data.sndbc = data;
+  return reg_write(SNDBC_ADDR, data);
 }
 
 
@@ -290,8 +322,8 @@ bool hcd_init(uint8_t rhport) {
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
-  // full duplex, interrupt level (should be configurable)
-  reg_write(PINCTL_ADDR, PINCTL_FDUPSPI | PINCTL_INTLEVEL);
+  // full duplex, interrupt negative edge
+  reg_write(PINCTL_ADDR, PINCTL_FDUPSPI);
 
   // reset
   reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
@@ -303,19 +335,16 @@ bool hcd_init(uint8_t rhport) {
   // Mode: Host and DP/DM pull down
   mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
 
+  // bus reset, this will trigger CONDET IRQ if device is already connected
+  reg_write(HCTL_ADDR, HCTL_BUSRST);
+
+  // clear all previously pending IRQ
+  reg_write(HIRQ_ADDR, 0xff);
+
+  _hcd_data.inited = true;
+
   // Enable Connection IRQ
-  reg_write(HIEN_ADDR, HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ);
-
-  #if 0
-  // Note: if device is already connected, CONDET IRQ may not be triggered.
-  // We need to detect it by sampling bus signal. FIXME not working
-  reg_write(HCTL_ADDR, HCTL_SAMPLEBUS);
-  while ( reg_read(HCTL_ADDR) & HCTL_SAMPLEBUS ) {}
-
-  if ( TUSB_SPEED_INVALID != handle_connect_irq(rhport) ) {
-    reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ); // clear connect irq
-  }
-  #endif
+  reg_write(HIEN_ADDR, DEFAULT_HIEN);
 
   // Enable Interrupt pin
   reg_write(CPUCTL_ADDR, CPUCTL_IE);
@@ -353,6 +382,10 @@ bool hcd_port_connect_status(uint8_t rhport) {
 // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
 void hcd_port_reset(uint8_t rhport) {
   (void) rhport;
+  // Bus reset will also trigger CONDET IRQ, disable it
+  uint8_t hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
+  reg_write(HIEN_ADDR, hien);
+
   reg_write(HCTL_ADDR, HCTL_BUSRST);
 }
 
@@ -360,6 +393,10 @@ void hcd_port_reset(uint8_t rhport) {
 void hcd_port_reset_end(uint8_t rhport) {
   (void) rhport;
   reg_write(HCTL_ADDR, 0);
+
+  // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
+  reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
+  reg_write(HIEN_ADDR, DEFAULT_HIEN);
 }
 
 // Get port link speed
@@ -393,14 +430,51 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 }
 
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
   (void) rhport;
-  (void) dev_addr;
-  (void) ep_addr;
-  (void) buffer;
-  (void) buflen;
 
-  return false;
+  uint8_t const ep_num = tu_edpt_number(ep_addr);
+  uint8_t const ep_dir = tu_edpt_dir(ep_addr);
+
+  hcd_ep_t* ep = &_hcd_data.ep[ep_num][ep_dir];
+
+  ep->buf = buffer;
+  ep->total_len = buflen;
+  ep->xferred_len = 0;
+
+  uint8_t hirq = peraddr_write(daddr);
+
+  uint8_t hctl = 0;
+  uint8_t hxfr = ep_num;
+  if ( ep_num == 0 ) {
+    ep->data_toggle = 1;
+    if ( buffer == NULL || buflen == 0 ) {
+      // ZLP for ACK stage
+      hxfr |= HXFR_HS;
+    }
+  } else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) {
+    hxfr |= HXFR_ISO;
+  }
+
+  if ( 0 == ep_dir ) {
+    // Page 12: Programming BULK-OUT Transfers
+    TU_ASSERT(hirq & HIRQ_RCVDAV_IRQ);
+
+    uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
+    fifo_write(SNDFIFO_ADDR, buffer, xact_len);
+    reg_write(SNDBC_ADDR, xact_len);
+
+    hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+    hxfr |= HXFR_OUT_NIN;
+  } else {
+    // Page 13: Programming BULK-IN Transfers
+    hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+  }
+
+  reg_write(HCTL_ADDR, hctl);
+  hxfr_write(hxfr);
+
+  return true;
 }
 
 // Abort a queued transfer. Note: it can only abort transfer that has not been started
@@ -416,10 +490,10 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
   (void) rhport;
-  (void) daddr;
-  (void) setup_packet;
 
-  _hcd_data.ep[0][0].total_len = 8;
+  hcd_ep_t* ep = &_hcd_data.ep[0][0];
+  ep->total_len  = 8;
+  ep->xferred_len = 0;
 
   peraddr_write(daddr);
   fifo_write(SUDFIFO_ADDR, setup_packet, 8);
@@ -437,11 +511,79 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
+static void handle_xfer_done(uint8_t rhport) {
+  (void) rhport;
+
+  uint8_t const hrsl = reg_read(HRSL_ADDR);
+  uint8_t const result = hrsl & HRSL_RESULT_MASK;
+  uint8_t xfer_result;
+
+  TU_LOG3("HRSL: %02X\r\n", hrsl);
+  switch(result) {
+    case HRSL_SUCCESS:
+      xfer_result = XFER_RESULT_SUCCESS;
+      break;
+
+    case HRSL_STALL:
+      xfer_result = XFER_RESULT_STALLED;
+      break;
+
+    case HRSL_BAD_REQ:
+      // occurred when initialized without any pending transfer. Skip for now
+      return;
+
+    default:
+      xfer_result = XFER_RESULT_FAILED;
+      break;
+  }
+
+  uint8_t ep_dir = 0;
+  uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+  uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
+
+  hcd_ep_t * ep;
+
+  if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) {
+    // SETUP or OUT transfer
+    ep_dir = 0;
+    ep = &_hcd_data.ep[ep_num][ep_dir];
+
+    uint8_t const xact_len = (xfer_type & HXFR_SETUP) ? 8 : _hcd_data.sndbc;
+    ep->xferred_len += xact_len;
+
+    if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+      hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
+    }else {
+      // more to transfer
+    }
+  } else {
+    // IN transfer
+    ep_dir = 1;
+    ep = &_hcd_data.ep[ep_num][ep_dir];
+    uint8_t const xact_len = reg_read(RCVBC_ADDR);
+    ep->xferred_len += xact_len;
+
+    // short packet or all bytes transferred
+    if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+      hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
+    }else {
+      // more to transfer
+    }
+  }
+}
+
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport) {
+  // not initialized, do nothing
+  if ( !_hcd_data.inited ) return;
+
   uint8_t hirq = reg_read(HIRQ_ADDR);
   TU_LOG3_HEX(hirq);
 
+  if (hirq & HIRQ_FRAME_IRQ) {
+    _hcd_data.frame_count++;
+  }
+
   if (hirq & HIRQ_CONDET_IRQ) {
     tusb_speed_t speed = handle_connect_irq(rhport);
 
@@ -452,49 +594,17 @@ void hcd_int_handler(uint8_t rhport) {
     }
   }
 
-  if (hirq & HIRQ_FRAME_IRQ) {
-    _hcd_data.frame_count++;
-  }
-
   if (hirq & HIRQ_HXFRDN_IRQ) {
-    uint8_t const hrsl = reg_read(HRSL_ADDR);
-    uint8_t const result = hrsl & HRSL_RESULT_MASK;
-    uint8_t xfer_result;
-
-    TU_LOG3("HRSL: %02X\r\n", hrsl);
-    switch(result) {
-      case HRSL_SUCCESS:
-        xfer_result = XFER_RESULT_SUCCESS;
-        break;
-
-      case HRSL_STALL:
-        xfer_result = XFER_RESULT_STALLED;
-        break;
-
-      default:
-        xfer_result = XFER_RESULT_FAILED;
-        break;
-    }
-
-    uint8_t ep_dir = 0;
-    uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
-    uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
-
-    if ( xfer_type & HXFR_SETUP ) {
-      // SETUP transfer
-      ep_dir = 0;
-    }else if ( !(xfer_type & HXFR_OUT_NIN) ) {
-      // IN transfer
-      ep_dir = 1;
-    }
-
-    uint8_t const ep_addr = tu_edpt_addr(ep_num, ep_dir);
-    uint16_t xferred_len = _hcd_data.ep[ep_num][ep_dir].total_len;
-
-    hcd_event_xfer_complete(_hcd_data.peraddr, ep_addr, xferred_len, xfer_result, true);
+    handle_xfer_done(rhport);
   }
 
-  // clear all interrupt
+  if ( hirq & HIRQ_RCVDAV_IRQ ) {
+    TU_LOG3("RCVDAV\r\n");
+    TU_LOG3_INT(reg_read(RCVBC_ADDR));
+  }
+
+  // clear all interrupt execept SNDBAV_IRQ
+  hirq &= ~HIRQ_SNDBAV_IRQ;
   if ( hirq ) {
     reg_write(HIRQ_ADDR, hirq);
   }

From 2c237b1ae4b3ffd38fc74df29da63b01348afd1d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 23 Aug 2023 17:49:28 +0700
Subject: [PATCH 2010/2085] able to complete 1st get device descriptor and set
 address

---
 src/portable/analog/max3421/hcd_max3421.c | 182 +++++++++++++++-------
 1 file changed, 127 insertions(+), 55 deletions(-)

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index edcb6ca6f..467d7410a 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -156,7 +156,7 @@ enum {
 };
 
 enum {
-  DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ
+  DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ | HIRQ_RCVDAV_IRQ
 };
 
 //--------------------------------------------------------------------+
@@ -178,6 +178,8 @@ typedef struct {
 
   // cached register
   uint8_t sndbc;
+  uint8_t hirq;
+  uint8_t hien;
   uint8_t mode;
   uint8_t peraddr;
   uint8_t hxfr;
@@ -203,60 +205,86 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_
 //--------------------------------------------------------------------+
 
 static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
+  uint8_t const rhport = 0;
+  uint8_t hirq;
   reg |= CMDBYTE_WRITE;
 
-  tuh_max3421_spi_cs_api(0, true);
+  tuh_max3421_spi_cs_api(rhport, true);
 
-  tuh_max3421_spi_xfer_api(0, &reg, 1, NULL, 0);
-  tuh_max3421_spi_xfer_api(0, buffer, len, NULL, 0);
+  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
+  _hcd_data.hirq = hirq;
+  tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0);
+
+  tuh_max3421_spi_cs_api(rhport, false);
 
-  tuh_max3421_spi_cs_api(0, false);
 }
 
-// return HIRQ register since we are in full-duplex mode
-static uint8_t reg_write(uint8_t reg, uint8_t data) {
+static void fifo_read(uint8_t * buffer, uint16_t len) {
+  uint8_t const rhport = 0;
+  uint8_t hirq;
+  uint8_t const reg = RCVVFIFO_ADDR;
+
+  tuh_max3421_spi_cs_api(rhport, true);
+
+  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 0);
+  _hcd_data.hirq = hirq;
+  tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
+
+  tuh_max3421_spi_cs_api(rhport, false);
+}
+
+static void reg_write(uint8_t reg, uint8_t data) {
+  uint8_t const rhport = 0;
   uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
   uint8_t rx_buf[2] = {0, 0};
 
-  tuh_max3421_spi_cs_api(0, true);
-  tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
-  tuh_max3421_spi_cs_api(0, false);
+  tuh_max3421_spi_cs_api(rhport, true);
+  tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
+  tuh_max3421_spi_cs_api(rhport, false);
 
-  TU_LOG2("HIRQ: %02X\r\n", rx_buf[0]);
-  return rx_buf[0];
+  // HIRQ register since we are in full-duplex mode
+  _hcd_data.hirq = rx_buf[0];
+  TU_LOG3_HEX(_hcd_data.hirq);
 }
 
 static uint8_t reg_read(uint8_t reg) {
+  uint8_t const rhport = 0;
   uint8_t tx_buf[2] = {reg, 0};
   uint8_t rx_buf[2] = {0, 0};
 
-  tuh_max3421_spi_cs_api(0, true);
-  bool ret = tuh_max3421_spi_xfer_api(0, tx_buf, 2, rx_buf, 2);
-  tuh_max3421_spi_cs_api(0, false);
+  tuh_max3421_spi_cs_api(rhport, true);
+  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
+  tuh_max3421_spi_cs_api(rhport, false);
 
+  _hcd_data.hirq = rx_buf[0];
   return ret ? rx_buf[1] : 0;
 }
 
-static inline uint8_t mode_write(uint8_t data) {
-  _hcd_data.mode = data;
-  return reg_write(MODE_ADDR, data);
+static inline void hien_write(uint8_t data) {
+  _hcd_data.hien = data;
+  reg_write(HIEN_ADDR, data);
 }
 
-static inline uint8_t peraddr_write(uint8_t data) {
-  if ( _hcd_data.peraddr == data ) return 0; // no need to change address
+static inline void mode_write(uint8_t data) {
+  _hcd_data.mode = data;
+  reg_write(MODE_ADDR, data);
+}
+
+static inline void peraddr_write(uint8_t data) {
+  if ( _hcd_data.peraddr == data ) return; // no need to change address
 
   _hcd_data.peraddr = data;
-  return reg_write(PERADDR_ADDR, data);
+  reg_write(PERADDR_ADDR, data);
 }
 
-static inline uint8_t hxfr_write(uint8_t data) {
+static inline void hxfr_write(uint8_t data) {
   _hcd_data.hxfr = data;
-  return reg_write(HXFR_ADDR, data);
+  reg_write(HXFR_ADDR, data);
 }
 
-static inline uint8_t sndbc_write(uint8_t data) {
+static inline void sndbc_write(uint8_t data) {
   _hcd_data.sndbc = data;
-  return reg_write(SNDBC_ADDR, data);
+  reg_write(SNDBC_ADDR, data);
 }
 
 
@@ -335,16 +363,16 @@ bool hcd_init(uint8_t rhport) {
   // Mode: Host and DP/DM pull down
   mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
 
-  // bus reset, this will trigger CONDET IRQ if device is already connected
-  reg_write(HCTL_ADDR, HCTL_BUSRST);
+  // frame reset & bus reset, this will trigger CONDET IRQ if device is already connected
+  reg_write(HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST);
 
   // clear all previously pending IRQ
   reg_write(HIRQ_ADDR, 0xff);
 
   _hcd_data.inited = true;
 
-  // Enable Connection IRQ
-  reg_write(HIEN_ADDR, DEFAULT_HIEN);
+  // Enable IRQ
+  hien_write(DEFAULT_HIEN);
 
   // Enable Interrupt pin
   reg_write(CPUCTL_ADDR, CPUCTL_IE);
@@ -383,8 +411,8 @@ bool hcd_port_connect_status(uint8_t rhport) {
 void hcd_port_reset(uint8_t rhport) {
   (void) rhport;
   // Bus reset will also trigger CONDET IRQ, disable it
-  uint8_t hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
-  reg_write(HIEN_ADDR, hien);
+  uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
+  hien_write(hien);
 
   reg_write(HCTL_ADDR, HCTL_BUSRST);
 }
@@ -396,7 +424,7 @@ void hcd_port_reset_end(uint8_t rhport) {
 
   // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
   reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
-  reg_write(HIEN_ADDR, DEFAULT_HIEN);
+  hien_write(DEFAULT_HIEN);
 }
 
 // Get port link speed
@@ -426,6 +454,10 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
 
   _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc);
 
+  if (ep_desc->bEndpointAddress == 0) {
+    _hcd_data.ep[ep_num][1].packet_size = tu_edpt_packet_size(ep_desc);
+  }
+
   return true;
 }
 
@@ -442,15 +474,18 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->total_len = buflen;
   ep->xferred_len = 0;
 
-  uint8_t hirq = peraddr_write(daddr);
+  peraddr_write(daddr);
 
   uint8_t hctl = 0;
   uint8_t hxfr = ep_num;
   if ( ep_num == 0 ) {
     ep->data_toggle = 1;
     if ( buffer == NULL || buflen == 0 ) {
-      // ZLP for ACK stage
+      // ZLP for ACK stage, use HS
       hxfr |= HXFR_HS;
+      hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
+      hxfr_write(hxfr);
+      return true;
     }
   } else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) {
     hxfr |= HXFR_ISO;
@@ -458,7 +493,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
 
   if ( 0 == ep_dir ) {
     // Page 12: Programming BULK-OUT Transfers
-    TU_ASSERT(hirq & HIRQ_RCVDAV_IRQ);
+    TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
 
     uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
     fifo_write(SNDFIFO_ADDR, buffer, xact_len);
@@ -516,7 +551,7 @@ static void handle_xfer_done(uint8_t rhport) {
 
   uint8_t const hrsl = reg_read(HRSL_ADDR);
   uint8_t const result = hrsl & HRSL_RESULT_MASK;
-  uint8_t xfer_result;
+  xfer_result_t xfer_result;
 
   TU_LOG3("HRSL: %02X\r\n", hrsl);
   switch(result) {
@@ -537,18 +572,21 @@ static void handle_xfer_done(uint8_t rhport) {
       break;
   }
 
-  uint8_t ep_dir = 0;
   uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
   uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
 
-  hcd_ep_t * ep;
-
   if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) {
     // SETUP or OUT transfer
-    ep_dir = 0;
-    ep = &_hcd_data.ep[ep_num][ep_dir];
+    hcd_ep_t *ep = &_hcd_data.ep[ep_num][0];
+    uint8_t xact_len;
+    if (xfer_type & HXFR_SETUP) {
+      xact_len = 8;
+    } else if ( xfer_type & HXFR_HS ) {
+      xact_len = 0;
+    } else {
+      xact_len = _hcd_data.sndbc;
+    }
 
-    uint8_t const xact_len = (xfer_type & HXFR_SETUP) ? 8 : _hcd_data.sndbc;
     ep->xferred_len += xact_len;
 
     if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
@@ -558,10 +596,27 @@ static void handle_xfer_done(uint8_t rhport) {
     }
   } else {
     // IN transfer
-    ep_dir = 1;
-    ep = &_hcd_data.ep[ep_num][ep_dir];
-    uint8_t const xact_len = reg_read(RCVBC_ADDR);
-    ep->xferred_len += xact_len;
+    hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
+    uint8_t xact_len;
+
+    if ( xfer_type & HXFR_HS ) {
+      xact_len = 0;
+    } else {
+      // RCVDAV_IRQ can trigger 2 times (dual buffered)
+      while ( _hcd_data.hirq & HIRQ_RCVDAV_IRQ ) {
+        uint8_t rcvbc = reg_read(RCVBC_ADDR);
+        xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
+        if ( xact_len ) {
+          fifo_read(ep->buf, xact_len);
+          ep->buf += xact_len;
+          ep->xferred_len += xact_len;
+        }
+
+        // ack RCVDVAV IRQ
+        reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ);
+        _hcd_data.hirq = reg_read(HIRQ_ADDR);
+      }
+    }
 
     // short packet or all bytes transferred
     if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
@@ -572,13 +627,35 @@ static void handle_xfer_done(uint8_t rhport) {
   }
 }
 
+#if CFG_TUSB_DEBUG >= 3
+void print_hirq(uint8_t hirq) {
+  TU_LOG3_HEX(hirq);
+
+  if (hirq & HIRQ_HXFRDN_IRQ) TU_LOG3(" HXFRDN");
+  if (hirq & HIRQ_FRAME_IRQ)  TU_LOG3(" FRAME");
+  if (hirq & HIRQ_CONDET_IRQ) TU_LOG3(" CONDET");
+  if (hirq & HIRQ_SUSDN_IRQ)  TU_LOG3(" SUSDN");
+  if (hirq & HIRQ_SNDBAV_IRQ) TU_LOG3(" SNDBAV");
+  if (hirq & HIRQ_RCVDAV_IRQ) TU_LOG3(" RCVDAV");
+  if (hirq & HIRQ_RWU_IRQ)    TU_LOG3(" RWU");
+  if (hirq & HIRQ_BUSEVENT_IRQ) TU_LOG3(" BUSEVENT");
+
+  TU_LOG3("\r\n");
+}
+
+#else
+  #define print_hirq(hirq)
+#endif
+
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport) {
   // not initialized, do nothing
   if ( !_hcd_data.inited ) return;
 
-  uint8_t hirq = reg_read(HIRQ_ADDR);
-  TU_LOG3_HEX(hirq);
+  uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien;
+  if (!hirq) return;
+
+  print_hirq(hirq);
 
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
@@ -598,13 +675,8 @@ void hcd_int_handler(uint8_t rhport) {
     handle_xfer_done(rhport);
   }
 
-  if ( hirq & HIRQ_RCVDAV_IRQ ) {
-    TU_LOG3("RCVDAV\r\n");
-    TU_LOG3_INT(reg_read(RCVBC_ADDR));
-  }
-
-  // clear all interrupt execept SNDBAV_IRQ
-  hirq &= ~HIRQ_SNDBAV_IRQ;
+  // clear all interrupt except SNDBAV_IRQ and RCVDAV_IRQ must be clear after pulling data from FIFO
+  hirq &= ~ (HIRQ_SNDBAV_IRQ | HIRQ_RCVDAV_IRQ);
   if ( hirq ) {
     reg_write(HIRQ_ADDR, hirq);
   }

From 3ed5d6c3724cfa9699d403a76a00f1b04672e2b5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 24 Aug 2023 16:27:12 +0700
Subject: [PATCH 2011/2085] complete enumeration

---
 hw/bsp/nrf/family.c                       |  5 +-
 src/portable/analog/max3421/hcd_max3421.c | 68 ++++++++++++++---------
 2 files changed, 47 insertions(+), 26 deletions(-)

diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 45a5166a7..368763b84 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -105,6 +105,10 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
+void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+  nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, enabled);
+}
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
@@ -241,7 +245,6 @@ void board_init(void) {
   in_config.pull = NRF_GPIO_PIN_PULLUP;
 
   nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler);
-  nrfx_gpiote_in_event_enable(MAX3241E_INTR_PIN, true);
 #endif
 
 }
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 467d7410a..514cf34b7 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -166,6 +166,7 @@ enum {
 typedef struct {
   uint8_t xfer_type;
   uint8_t data_toggle;
+  uint8_t xfer_complete;
   uint16_t packet_size;
 
   uint16_t total_len;
@@ -244,7 +245,6 @@ static void reg_write(uint8_t reg, uint8_t data) {
 
   // HIRQ register since we are in full-duplex mode
   _hcd_data.hirq = rx_buf[0];
-  TU_LOG3_HEX(_hcd_data.hirq);
 }
 
 static uint8_t reg_read(uint8_t reg) {
@@ -473,6 +473,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
+  ep->xfer_complete = 0;
 
   peraddr_write(daddr);
 
@@ -595,34 +596,19 @@ static void handle_xfer_done(uint8_t rhport) {
       // more to transfer
     }
   } else {
-    // IN transfer
+    // IN transfer: fifo data is already received in RCVDAV IRQ
     hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
-    uint8_t xact_len;
 
     if ( xfer_type & HXFR_HS ) {
-      xact_len = 0;
-    } else {
-      // RCVDAV_IRQ can trigger 2 times (dual buffered)
-      while ( _hcd_data.hirq & HIRQ_RCVDAV_IRQ ) {
-        uint8_t rcvbc = reg_read(RCVBC_ADDR);
-        xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
-        if ( xact_len ) {
-          fifo_read(ep->buf, xact_len);
-          ep->buf += xact_len;
-          ep->xferred_len += xact_len;
-        }
-
-        // ack RCVDVAV IRQ
-        reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ);
-        _hcd_data.hirq = reg_read(HIRQ_ADDR);
-      }
+      ep->xfer_complete = 1;
     }
 
     // short packet or all bytes transferred
-    if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+    if ( ep->xfer_complete ) {
       hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
+      hxfr_write(_hcd_data.hxfr);
     }
   }
 }
@@ -655,7 +641,7 @@ void hcd_int_handler(uint8_t rhport) {
   uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien;
   if (!hirq) return;
 
-  print_hirq(hirq);
+//  print_hirq(hirq);
 
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
@@ -671,12 +657,44 @@ void hcd_int_handler(uint8_t rhport) {
     }
   }
 
-  if (hirq & HIRQ_HXFRDN_IRQ) {
-    handle_xfer_done(rhport);
+  // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or
+  // not call this handler again. So we need to loop until all IRQ are cleared
+  while ( hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ) ) {
+    if ( hirq & HIRQ_RCVDAV_IRQ ) {
+      uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+      hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
+      uint8_t xact_len;
+
+      // RCVDAV_IRQ can trigger 2 times (dual buffered)
+      while ( hirq & HIRQ_RCVDAV_IRQ ) {
+        uint8_t rcvbc = reg_read(RCVBC_ADDR);
+        xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
+        if ( xact_len ) {
+          fifo_read(ep->buf, xact_len);
+          ep->buf += xact_len;
+          ep->xferred_len += xact_len;
+        }
+
+        // ack RCVDVAV IRQ
+        reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ);
+        hirq = reg_read(HIRQ_ADDR);
+      }
+
+      if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+        ep->xfer_complete = 1;
+      }
+    }
+
+    if ( hirq & HIRQ_HXFRDN_IRQ ) {
+      reg_write(HIRQ_ADDR, HIRQ_HXFRDN_IRQ);
+      handle_xfer_done(rhport);
+    }
+
+    hirq = reg_read(HIRQ_ADDR);
   }
 
-  // clear all interrupt except SNDBAV_IRQ and RCVDAV_IRQ must be clear after pulling data from FIFO
-  hirq &= ~ (HIRQ_SNDBAV_IRQ | HIRQ_RCVDAV_IRQ);
+  // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
+  hirq &= ~HIRQ_SNDBAV_IRQ;
   if ( hirq ) {
     reg_write(HIRQ_ADDR, hirq);
   }

From 344932d27e1f65932ce922b639370ecc4fff2153 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 24 Aug 2023 16:27:32 +0700
Subject: [PATCH 2012/2085] add tuh_max3421e_int_api(), retry control if
 received NAK

---
 src/portable/analog/max3421/hcd_max3421.c | 60 +++++++++++++++--------
 1 file changed, 40 insertions(+), 20 deletions(-)

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 514cf34b7..b4f75e392 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -28,6 +28,7 @@
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
+#include <stdatomic.h>
 #include "host/hcd.h"
 
 //--------------------------------------------------------------------+
@@ -164,11 +165,15 @@ enum {
 //--------------------------------------------------------------------+
 
 typedef struct {
-  uint8_t xfer_type;
-  uint8_t data_toggle;
-  uint8_t xfer_complete;
   uint16_t packet_size;
 
+  struct TU_ATTR_PACKED {
+    uint8_t is_iso        : 1;
+    uint8_t data_toggle   : 1;
+    uint8_t xfer_queued   : 1;
+    uint8_t xfer_complete : 1;
+  };
+
   uint16_t total_len;
   uint16_t xferred_len;
   uint8_t* buf;
@@ -176,6 +181,7 @@ typedef struct {
 
 typedef struct {
   bool inited;
+  atomic_bool busy; // busy transferring
 
   // cached register
   uint8_t sndbc;
@@ -198,8 +204,7 @@ static max2341_data_t _hcd_data;
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
-
-//void tuh_max3421e_int_enable(uint8_t rhport, bool enabled);
+void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
 
 //--------------------------------------------------------------------+
 //
@@ -348,6 +353,9 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
+  TU_LOG2_INT(sizeof(hcd_ep_t));
+  TU_LOG2_INT(sizeof(max2341_data_t));
+
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
   // full duplex, interrupt negative edge
@@ -382,12 +390,12 @@ bool hcd_init(uint8_t rhport) {
 
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport) {
-  (void) rhport;
+  tuh_max3421e_int_api(rhport, true);
 }
 
 // Disable USB interrupt
 void hcd_int_disable(uint8_t rhport) {
-  (void) rhport;
+  tuh_max3421e_int_api(rhport, false);
 }
 
 // Get frame number (1ms)
@@ -447,17 +455,20 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
   (void) rhport;
   (void) dev_addr;
-  (void) ep_desc;
 
   uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
   uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
 
-  _hcd_data.ep[ep_num][ep_dir].packet_size = tu_edpt_packet_size(ep_desc);
+  hcd_ep_t * ep = &_hcd_data.ep[ep_num][ep_dir];
+
+  ep->packet_size = tu_edpt_packet_size(ep_desc);
 
   if (ep_desc->bEndpointAddress == 0) {
-    _hcd_data.ep[ep_num][1].packet_size = tu_edpt_packet_size(ep_desc);
+    _hcd_data.ep[0][1].packet_size = ep->packet_size;
   }
 
+  ep->is_iso = (TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer) ? 1 : 0;
+
   return true;
 }
 
@@ -474,11 +485,13 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->total_len = buflen;
   ep->xferred_len = 0;
   ep->xfer_complete = 0;
+  ep->xfer_queued = 1;
 
   peraddr_write(daddr);
 
   uint8_t hctl = 0;
   uint8_t hxfr = ep_num;
+
   if ( ep_num == 0 ) {
     ep->data_toggle = 1;
     if ( buffer == NULL || buflen == 0 ) {
@@ -488,7 +501,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
       hxfr_write(hxfr);
       return true;
     }
-  } else if ( ep->xfer_type == TUSB_XFER_ISOCHRONOUS ) {
+  } else if ( ep->is_iso ) {
     hxfr |= HXFR_ISO;
   }
 
@@ -551,11 +564,13 @@ static void handle_xfer_done(uint8_t rhport) {
   (void) rhport;
 
   uint8_t const hrsl = reg_read(HRSL_ADDR);
-  uint8_t const result = hrsl & HRSL_RESULT_MASK;
+  uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
+  uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+
   xfer_result_t xfer_result;
 
-  TU_LOG3("HRSL: %02X\r\n", hrsl);
-  switch(result) {
+  //TU_LOG3("HRSL: %02X\r\n", hrsl);
+  switch(hresult) {
     case HRSL_SUCCESS:
       xfer_result = XFER_RESULT_SUCCESS;
       break;
@@ -568,21 +583,26 @@ static void handle_xfer_done(uint8_t rhport) {
       // occurred when initialized without any pending transfer. Skip for now
       return;
 
+    case HRSL_NAK:
+      // NAK on control, retry immediately
+      if (ep_num == 0) hxfr_write(_hcd_data.hxfr);
+      return;
+
     default:
       xfer_result = XFER_RESULT_FAILED;
       break;
   }
 
-  uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
-  uint8_t const xfer_type = _hcd_data.hxfr & 0xf0;
+  uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0;
 
-  if ( (xfer_type & HXFR_SETUP) || (xfer_type & HXFR_OUT_NIN) ) {
+  if ( (hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN) ) {
     // SETUP or OUT transfer
     hcd_ep_t *ep = &_hcd_data.ep[ep_num][0];
     uint8_t xact_len;
-    if (xfer_type & HXFR_SETUP) {
+
+    if ( hxfr_type & HXFR_SETUP) {
       xact_len = 8;
-    } else if ( xfer_type & HXFR_HS ) {
+    } else if ( hxfr_type & HXFR_HS ) {
       xact_len = 0;
     } else {
       xact_len = _hcd_data.sndbc;
@@ -599,7 +619,7 @@ static void handle_xfer_done(uint8_t rhport) {
     // IN transfer: fifo data is already received in RCVDAV IRQ
     hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
 
-    if ( xfer_type & HXFR_HS ) {
+    if ( hxfr_type & HXFR_HS ) {
       ep->xfer_complete = 1;
     }
 

From e6cf125e537125fc7303afc7d0703a3de6b8b334 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 24 Aug 2023 16:46:20 +0700
Subject: [PATCH 2013/2085] save data toggle, always retry NAK. work with msc
 device

---
 src/portable/analog/max3421/hcd_max3421.c | 24 ++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index b4f75e392..9579409c5 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -492,7 +492,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   uint8_t hctl = 0;
   uint8_t hxfr = ep_num;
 
-  if ( ep_num == 0 ) {
+  if ( ep->is_iso ) {
+    hxfr |= HXFR_ISO;
+  } else if ( ep_num == 0 ) {
     ep->data_toggle = 1;
     if ( buffer == NULL || buflen == 0 ) {
       // ZLP for ACK stage, use HS
@@ -501,8 +503,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
       hxfr_write(hxfr);
       return true;
     }
-  } else if ( ep->is_iso ) {
-    hxfr |= HXFR_ISO;
   }
 
   if ( 0 == ep_dir ) {
@@ -511,7 +511,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
 
     uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
     fifo_write(SNDFIFO_ADDR, buffer, xact_len);
-    reg_write(SNDBC_ADDR, xact_len);
+    sndbc_write(xact_len);
 
     hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
     hxfr |= HXFR_OUT_NIN;
@@ -585,7 +585,10 @@ static void handle_xfer_done(uint8_t rhport) {
 
     case HRSL_NAK:
       // NAK on control, retry immediately
-      if (ep_num == 0) hxfr_write(_hcd_data.hxfr);
+      //if (ep_num == 0)
+      {
+        hxfr_write(_hcd_data.hxfr);
+      }
       return;
 
     default:
@@ -609,8 +612,14 @@ static void handle_xfer_done(uint8_t rhport) {
     }
 
     ep->xferred_len += xact_len;
+    ep->buf += xact_len;
 
     if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
+      if ( ep_num ) {
+        // save data toggle for non-control
+        ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
+      }
+
       hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
@@ -625,6 +634,11 @@ static void handle_xfer_done(uint8_t rhport) {
 
     // short packet or all bytes transferred
     if ( ep->xfer_complete ) {
+      if ( ep_num ) {
+        // save data toggle for non-control
+        ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
+      }
+
       hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer

From f5ebc1700f4bde1cc166bf5f3d8eb69d8832722a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Aug 2023 12:12:44 +0700
Subject: [PATCH 2014/2085] add spi lock with interrupt enable/disable

---
 src/portable/analog/max3421/hcd_max3421.c | 176 +++++++++++-----------
 1 file changed, 91 insertions(+), 85 deletions(-)

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 9579409c5..0144deca6 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -180,7 +180,6 @@ typedef struct {
 } hcd_ep_t;
 
 typedef struct {
-  bool inited;
   atomic_bool busy; // busy transferring
 
   // cached register
@@ -194,6 +193,8 @@ typedef struct {
   volatile uint16_t frame_count;
 
   hcd_ep_t ep[8][2];
+
+  OSAL_MUTEX_DEF(spi_mutex);
 } max2341_data_t;
 
 static max2341_data_t _hcd_data;
@@ -210,86 +211,106 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
 //
 //--------------------------------------------------------------------+
 
-static void fifo_write(uint8_t reg, uint8_t const * buffer, uint16_t len) {
-  uint8_t const rhport = 0;
+static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
+  // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
+  if (!in_isr) {
+    tuh_max3421e_int_api(rhport, false);
+  }
+
+  // assert CS
+  tuh_max3421_spi_cs_api(rhport, true);
+}
+
+static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
+  // de-assert CS
+  tuh_max3421_spi_cs_api(rhport, false);
+
+  // mutex unlock and re-enable interrupt
+  if (!in_isr) {
+    tuh_max3421e_int_api(rhport, true);
+  }
+}
+
+static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) {
   uint8_t hirq;
   reg |= CMDBYTE_WRITE;
 
-  tuh_max3421_spi_cs_api(rhport, true);
+  max3421_spi_lock(rhport, in_isr);
 
   tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
   _hcd_data.hirq = hirq;
   tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0);
 
-  tuh_max3421_spi_cs_api(rhport, false);
+  max3421_spi_unlock(rhport, in_isr);
 
 }
 
-static void fifo_read(uint8_t * buffer, uint16_t len) {
-  uint8_t const rhport = 0;
+static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
   uint8_t hirq;
   uint8_t const reg = RCVVFIFO_ADDR;
 
-  tuh_max3421_spi_cs_api(rhport, true);
+  max3421_spi_lock(rhport, in_isr);
 
   tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 0);
   _hcd_data.hirq = hirq;
   tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
 
-  tuh_max3421_spi_cs_api(rhport, false);
+  max3421_spi_unlock(rhport, in_isr);
 }
 
-static void reg_write(uint8_t reg, uint8_t data) {
-  uint8_t const rhport = 0;
+static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) {
   uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
   uint8_t rx_buf[2] = {0, 0};
 
-  tuh_max3421_spi_cs_api(rhport, true);
+  max3421_spi_lock(rhport, in_isr);
+
   tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
-  tuh_max3421_spi_cs_api(rhport, false);
+
+  max3421_spi_unlock(rhport, in_isr);
 
   // HIRQ register since we are in full-duplex mode
   _hcd_data.hirq = rx_buf[0];
 }
 
-static uint8_t reg_read(uint8_t reg) {
-  uint8_t const rhport = 0;
+static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
   uint8_t tx_buf[2] = {reg, 0};
   uint8_t rx_buf[2] = {0, 0};
 
-  tuh_max3421_spi_cs_api(rhport, true);
+  max3421_spi_lock(rhport, in_isr);
+
   bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
-  tuh_max3421_spi_cs_api(rhport, false);
+
+  max3421_spi_unlock(rhport, in_isr);
 
   _hcd_data.hirq = rx_buf[0];
   return ret ? rx_buf[1] : 0;
 }
 
-static inline void hien_write(uint8_t data) {
+static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.hien = data;
-  reg_write(HIEN_ADDR, data);
+  reg_write(rhport, HIEN_ADDR, data, in_isr);
 }
 
-static inline void mode_write(uint8_t data) {
+static inline void mode_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.mode = data;
-  reg_write(MODE_ADDR, data);
+  reg_write(rhport, MODE_ADDR, data, in_isr);
 }
 
-static inline void peraddr_write(uint8_t data) {
+static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) {
   if ( _hcd_data.peraddr == data ) return; // no need to change address
 
   _hcd_data.peraddr = data;
-  reg_write(PERADDR_ADDR, data);
+  reg_write(rhport, PERADDR_ADDR, data, in_isr);
 }
 
-static inline void hxfr_write(uint8_t data) {
+static inline void hxfr_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.hxfr = data;
-  reg_write(HXFR_ADDR, data);
+  reg_write(rhport, HXFR_ADDR, data, in_isr);
 }
 
-static inline void sndbc_write(uint8_t data) {
+static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.sndbc = data;
-  reg_write(SNDBC_ADDR, data);
+  reg_write(rhport, SNDBC_ADDR, data, in_isr);
 }
 
 
@@ -307,9 +328,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
 }
 
 tusb_speed_t handle_connect_irq(uint8_t rhport) {
-  (void) rhport;
-
-  uint8_t const hrsl = reg_read(HRSL_ADDR);
+  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
   uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
 
   tusb_speed_t speed;
@@ -328,7 +347,7 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
 
     default: {
       // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
-      uint8_t const mode = reg_read(MODE_ADDR);
+      uint8_t const mode = reg_read(rhport, MODE_ADDR, true);
       uint8_t const ls_bit = mode & MODE_LOWSPEED;
 
       if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) {
@@ -344,7 +363,7 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
     }
   }
 
-  mode_write(new_mode);
+  mode_write(rhport, new_mode, true);
   TU_LOG2_INT(speed);
   return speed;
 }
@@ -358,32 +377,32 @@ bool hcd_init(uint8_t rhport) {
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
+  hcd_int_disable(rhport);
+
   // full duplex, interrupt negative edge
-  reg_write(PINCTL_ADDR, PINCTL_FDUPSPI);
+  reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
 
   // reset
-  reg_write(USBCTL_ADDR, USBCTL_CHIPRES);
-  reg_write(USBCTL_ADDR, 0);
-  while( !(reg_read(USBIRQ_ADDR) & USBIRQ_OSCOK_IRQ) ) {
+  reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
+  reg_write(rhport, USBCTL_ADDR, 0, false);
+  while( !(reg_read(rhport, USBIRQ_ADDR, false) & USBIRQ_OSCOK_IRQ) ) {
     // wait for oscillator to stabilize
   }
 
   // Mode: Host and DP/DM pull down
-  mode_write(MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST);
+  mode_write(rhport, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST, false);
 
   // frame reset & bus reset, this will trigger CONDET IRQ if device is already connected
-  reg_write(HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST);
+  reg_write(rhport, HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST, false);
 
   // clear all previously pending IRQ
-  reg_write(HIRQ_ADDR, 0xff);
-
-  _hcd_data.inited = true;
+  reg_write(rhport, HIRQ_ADDR, 0xff, false);
 
   // Enable IRQ
-  hien_write(DEFAULT_HIEN);
+  hien_write(rhport, DEFAULT_HIEN, false);
 
   // Enable Interrupt pin
-  reg_write(CPUCTL_ADDR, CPUCTL_IE);
+  reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
 
   return true;
 }
@@ -417,22 +436,20 @@ bool hcd_port_connect_status(uint8_t rhport) {
 // Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
 // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
 void hcd_port_reset(uint8_t rhport) {
-  (void) rhport;
   // Bus reset will also trigger CONDET IRQ, disable it
   uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
-  hien_write(hien);
+  hien_write(rhport, hien, false);
 
-  reg_write(HCTL_ADDR, HCTL_BUSRST);
+  reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, false);
 }
 
 // Complete bus reset sequence, may be required by some controllers
 void hcd_port_reset_end(uint8_t rhport) {
-  (void) rhport;
-  reg_write(HCTL_ADDR, 0);
+  reg_write(rhport, HCTL_ADDR, 0, false);
 
   // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
-  reg_write(HIRQ_ADDR, HIRQ_CONDET_IRQ);
-  hien_write(DEFAULT_HIEN);
+  reg_write(rhport, HIRQ_ADDR, HIRQ_CONDET_IRQ, false);
+  hien_write(rhport, DEFAULT_HIEN, false);
 }
 
 // Get port link speed
@@ -487,7 +504,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->xfer_complete = 0;
   ep->xfer_queued = 1;
 
-  peraddr_write(daddr);
+  peraddr_write(rhport, daddr, false);
 
   uint8_t hctl = 0;
   uint8_t hxfr = ep_num;
@@ -500,7 +517,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
       // ZLP for ACK stage, use HS
       hxfr |= HXFR_HS;
       hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
-      hxfr_write(hxfr);
+      hxfr_write(rhport, hxfr, false);
       return true;
     }
   }
@@ -510,8 +527,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
     TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
 
     uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
-    fifo_write(SNDFIFO_ADDR, buffer, xact_len);
-    sndbc_write(xact_len);
+    fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
+    sndbc_write(rhport, xact_len, false);
 
     hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
     hxfr |= HXFR_OUT_NIN;
@@ -520,8 +537,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
     hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
   }
 
-  reg_write(HCTL_ADDR, hctl);
-  hxfr_write(hxfr);
+  reg_write(rhport, HCTL_ADDR, hctl, false);
+  hxfr_write(rhport, hxfr, false);
 
   return true;
 }
@@ -544,9 +561,9 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   ep->total_len  = 8;
   ep->xferred_len = 0;
 
-  peraddr_write(daddr);
-  fifo_write(SUDFIFO_ADDR, setup_packet, 8);
-  hxfr_write(HXFR_SETUP);
+  peraddr_write(rhport, daddr, false);
+  fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false);
+  hxfr_write(rhport, HXFR_SETUP, false);
 
   return true;
 }
@@ -561,9 +578,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 }
 
 static void handle_xfer_done(uint8_t rhport) {
-  (void) rhport;
-
-  uint8_t const hrsl = reg_read(HRSL_ADDR);
+  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
   uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
   uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
 
@@ -587,7 +602,7 @@ static void handle_xfer_done(uint8_t rhport) {
       // NAK on control, retry immediately
       //if (ep_num == 0)
       {
-        hxfr_write(_hcd_data.hxfr);
+        hxfr_write(rhport, _hcd_data.hxfr, true);
       }
       return;
 
@@ -615,11 +630,8 @@ static void handle_xfer_done(uint8_t rhport) {
     ep->buf += xact_len;
 
     if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
-      if ( ep_num ) {
-        // save data toggle for non-control
-        ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
-      }
-
+      // save data toggle
+      ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
       hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
@@ -634,15 +646,12 @@ static void handle_xfer_done(uint8_t rhport) {
 
     // short packet or all bytes transferred
     if ( ep->xfer_complete ) {
-      if ( ep_num ) {
-        // save data toggle for non-control
-        ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
-      }
-
+      // save data toggle
+      ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
       hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
-      hxfr_write(_hcd_data.hxfr);
+      hxfr_write(rhport, _hcd_data.hxfr, true);
     }
   }
 }
@@ -669,10 +678,7 @@ void print_hirq(uint8_t hirq) {
 
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport) {
-  // not initialized, do nothing
-  if ( !_hcd_data.inited ) return;
-
-  uint8_t hirq = reg_read(HIRQ_ADDR) & _hcd_data.hien;
+  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
   if (!hirq) return;
 
 //  print_hirq(hirq);
@@ -701,17 +707,17 @@ void hcd_int_handler(uint8_t rhport) {
 
       // RCVDAV_IRQ can trigger 2 times (dual buffered)
       while ( hirq & HIRQ_RCVDAV_IRQ ) {
-        uint8_t rcvbc = reg_read(RCVBC_ADDR);
+        uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, true);
         xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
         if ( xact_len ) {
-          fifo_read(ep->buf, xact_len);
+          fifo_read(rhport, ep->buf, xact_len, true);
           ep->buf += xact_len;
           ep->xferred_len += xact_len;
         }
 
         // ack RCVDVAV IRQ
-        reg_write(HIRQ_ADDR, HIRQ_RCVDAV_IRQ);
-        hirq = reg_read(HIRQ_ADDR);
+        reg_write(rhport, HIRQ_ADDR, HIRQ_RCVDAV_IRQ, true);
+        hirq = reg_read(rhport, HIRQ_ADDR, true);
       }
 
       if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
@@ -720,17 +726,17 @@ void hcd_int_handler(uint8_t rhport) {
     }
 
     if ( hirq & HIRQ_HXFRDN_IRQ ) {
-      reg_write(HIRQ_ADDR, HIRQ_HXFRDN_IRQ);
+      reg_write(rhport, HIRQ_ADDR, HIRQ_HXFRDN_IRQ, true);
       handle_xfer_done(rhport);
     }
 
-    hirq = reg_read(HIRQ_ADDR);
+    hirq = reg_read(rhport, HIRQ_ADDR, true);
   }
 
   // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
   hirq &= ~HIRQ_SNDBAV_IRQ;
   if ( hirq ) {
-    reg_write(HIRQ_ADDR, hirq);
+    reg_write(rhport, HIRQ_ADDR, hirq, true);
   }
 }
 

From 09ceaa6cf37d29e605495716fc2497ed5228a37f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Aug 2023 13:18:47 +0700
Subject: [PATCH 2015/2085] add osal mutex for spi

---
 src/portable/analog/max3421/hcd_max3421.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 0144deca6..09845ffe4 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -194,7 +194,10 @@ typedef struct {
 
   hcd_ep_t ep[8][2];
 
-  OSAL_MUTEX_DEF(spi_mutex);
+  OSAL_MUTEX_DEF(spi_mutexdef);
+#if OSAL_MUTEX_REQUIRED
+  osal_mutex_t spi_mutex;
+#endif
 } max2341_data_t;
 
 static max2341_data_t _hcd_data;
@@ -215,6 +218,7 @@ static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
   // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
   if (!in_isr) {
     tuh_max3421e_int_api(rhport, false);
+    (void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
   }
 
   // assert CS
@@ -228,6 +232,7 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
   // mutex unlock and re-enable interrupt
   if (!in_isr) {
     tuh_max3421e_int_api(rhport, true);
+    (void) osal_mutex_unlock(_hcd_data.spi_mutex);
   }
 }
 
@@ -372,12 +377,16 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
+  hcd_int_disable(rhport);
+
   TU_LOG2_INT(sizeof(hcd_ep_t));
   TU_LOG2_INT(sizeof(max2341_data_t));
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
-  hcd_int_disable(rhport);
+#if OSAL_MUTEX_REQUIRED
+  _hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef);
+#endif
 
   // full duplex, interrupt negative edge
   reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);

From ecf2f910424b53fecc3ca82ae410f054518cc752 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Aug 2023 16:36:28 +0700
Subject: [PATCH 2016/2085] use endpoint pool for more flexible multiple
 devices support

---
 src/portable/analog/max3421/hcd_max3421.c | 180 +++++++++++++++-------
 1 file changed, 122 insertions(+), 58 deletions(-)

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 09845ffe4..b0325f240 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -165,22 +165,26 @@ enum {
 //--------------------------------------------------------------------+
 
 typedef struct {
-  uint16_t packet_size;
-
   struct TU_ATTR_PACKED {
+    uint8_t ep_dir        : 1;
     uint8_t is_iso        : 1;
     uint8_t data_toggle   : 1;
-    uint8_t xfer_queued   : 1;
+    uint8_t xfer_pending  : 1;
     uint8_t xfer_complete : 1;
   };
+  struct TU_ATTR_PACKED {
+    uint8_t daddr : 4;
+    uint8_t ep_num : 4;
+  };
 
+  uint16_t packet_size;
   uint16_t total_len;
   uint16_t xferred_len;
   uint8_t* buf;
-} hcd_ep_t;
+} max3421_ep_t;
 
 typedef struct {
-  atomic_bool busy; // busy transferring
+  atomic_flag busy; // busy transferring
 
   // cached register
   uint8_t sndbc;
@@ -192,15 +196,16 @@ typedef struct {
 
   volatile uint16_t frame_count;
 
-  hcd_ep_t ep[8][2];
+  max3421_ep_t ep0_addr0; // control endpoint for addr0
+  max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL];
 
   OSAL_MUTEX_DEF(spi_mutexdef);
 #if OSAL_MUTEX_REQUIRED
   osal_mutex_t spi_mutex;
 #endif
-} max2341_data_t;
+} max3421_data_t;
 
-static max2341_data_t _hcd_data;
+static max3421_data_t _hcd_data;
 
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
@@ -211,7 +216,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_
 void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
 
 //--------------------------------------------------------------------+
-//
+// SPI Helper
 //--------------------------------------------------------------------+
 
 static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
@@ -318,6 +323,44 @@ static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
   reg_write(rhport, SNDBC_ADDR, data, in_isr);
 }
 
+//--------------------------------------------------------------------+
+// Endpoint helper
+//--------------------------------------------------------------------+
+
+static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
+  for(size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    // for control endpoint, skip direction check
+    if ( daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0) ) {
+      return ep;
+    }
+  }
+
+  return NULL;
+}
+
+// daddr = 0 and ep_num = 0 means find a free (allocate) endpoint
+TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * allocate_ep(void) {
+  return find_ep_not_addr0(0, 0, 0);
+}
+
+// free all endpoints belong to device address
+static void free_ep(uint8_t daddr) {
+  for (size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    if (ep->daddr == daddr) {
+      tu_memclr(ep, sizeof(max3421_ep_t));
+    }
+  }
+}
+
+TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
+  if (daddr == 0 && ep_num == 0) {
+    return &_hcd_data.ep0_addr0;
+  }else{
+    return find_ep_not_addr0(daddr, ep_num, ep_dir);
+  }
+}
 
 //--------------------------------------------------------------------+
 // Controller API
@@ -379,8 +422,8 @@ bool hcd_init(uint8_t rhport) {
 
   hcd_int_disable(rhport);
 
-  TU_LOG2_INT(sizeof(hcd_ep_t));
-  TU_LOG2_INT(sizeof(max2341_data_t));
+  TU_LOG2_INT(sizeof(max3421_ep_t));
+  TU_LOG2_INT(sizeof(max3421_data_t));
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
 
@@ -478,22 +521,29 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
 //--------------------------------------------------------------------+
 
 // Open an endpoint
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
+bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc) {
   (void) rhport;
-  (void) dev_addr;
+  (void) daddr;
 
   uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
   uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
 
-  hcd_ep_t * ep = &_hcd_data.ep[ep_num][ep_dir];
-
-  ep->packet_size = tu_edpt_packet_size(ep_desc);
-
-  if (ep_desc->bEndpointAddress == 0) {
-    _hcd_data.ep[0][1].packet_size = ep->packet_size;
+  max3421_ep_t * ep;
+  if (daddr == 0 && ep_num == 0) {
+    ep = &_hcd_data.ep0_addr0;
+  }else {
+    ep = allocate_ep();
+    TU_ASSERT(ep);
+    ep->daddr = daddr;
+    ep->ep_num = ep_num;
+    ep->ep_dir = ep_dir;
   }
 
-  ep->is_iso = (TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer) ? 1 : 0;
+  if ( TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer ) {
+    ep->is_iso = 1;
+  }
+
+  ep->packet_size = tu_edpt_packet_size(ep_desc);
 
   return true;
 }
@@ -505,50 +555,55 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   uint8_t const ep_num = tu_edpt_number(ep_addr);
   uint8_t const ep_dir = tu_edpt_dir(ep_addr);
 
-  hcd_ep_t* ep = &_hcd_data.ep[ep_num][ep_dir];
+  max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
+  TU_ASSERT(ep);
 
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
   ep->xfer_complete = 0;
-  ep->xfer_queued = 1;
+  ep->xfer_pending = 1;
 
-  peraddr_write(rhport, daddr, false);
+  // carry out transfer if not busy
+//  if ( atomic_flag_test_and_set(&_hcd_data.busy) )
+  {
+    peraddr_write(rhport, daddr, false);
 
-  uint8_t hctl = 0;
-  uint8_t hxfr = ep_num;
+    uint8_t hctl = 0;
+    uint8_t hxfr = ep_num;
 
-  if ( ep->is_iso ) {
-    hxfr |= HXFR_ISO;
-  } else if ( ep_num == 0 ) {
-    ep->data_toggle = 1;
-    if ( buffer == NULL || buflen == 0 ) {
-      // ZLP for ACK stage, use HS
-      hxfr |= HXFR_HS;
-      hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
-      hxfr_write(rhport, hxfr, false);
-      return true;
+    if ( ep->is_iso ) {
+      hxfr |= HXFR_ISO;
+    } else if ( ep_num == 0 ) {
+      ep->data_toggle = 1;
+      if ( buffer == NULL || buflen == 0 ) {
+        // ZLP for ACK stage, use HS
+        hxfr |= HXFR_HS;
+        hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
+        hxfr_write(rhport, hxfr, false);
+        return true;
+      }
     }
+
+    if ( 0 == ep_dir ) {
+      // Page 12: Programming BULK-OUT Transfers
+      TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
+
+      uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
+      fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
+      sndbc_write(rhport, xact_len, false);
+
+      hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+      hxfr |= HXFR_OUT_NIN;
+    } else {
+      // Page 13: Programming BULK-IN Transfers
+      hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+    }
+
+    reg_write(rhport, HCTL_ADDR, hctl, false);
+    hxfr_write(rhport, hxfr, false);
   }
 
-  if ( 0 == ep_dir ) {
-    // Page 12: Programming BULK-OUT Transfers
-    TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
-
-    uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
-    fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
-    sndbc_write(rhport, xact_len, false);
-
-    hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
-    hxfr |= HXFR_OUT_NIN;
-  } else {
-    // Page 13: Programming BULK-IN Transfers
-    hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
-  }
-
-  reg_write(rhport, HCTL_ADDR, hctl, false);
-  hxfr_write(rhport, hxfr, false);
-
   return true;
 }
 
@@ -566,7 +621,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
   (void) rhport;
 
-  hcd_ep_t* ep = &_hcd_data.ep[0][0];
+  max3421_ep_t* ep = find_opened_ep(daddr, 0, 0);
   ep->total_len  = 8;
   ep->xferred_len = 0;
 
@@ -624,7 +679,7 @@ static void handle_xfer_done(uint8_t rhport) {
 
   if ( (hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN) ) {
     // SETUP or OUT transfer
-    hcd_ep_t *ep = &_hcd_data.ep[ep_num][0];
+    max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 0);
     uint8_t xact_len;
 
     if ( hxfr_type & HXFR_SETUP) {
@@ -644,10 +699,15 @@ static void handle_xfer_done(uint8_t rhport) {
       hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
+      xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+      fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, true);
+      sndbc_write(rhport, xact_len, true);
+
+      hxfr_write(rhport, _hcd_data.hxfr, true);
     }
   } else {
     // IN transfer: fifo data is already received in RCVDAV IRQ
-    hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
+    max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
 
     if ( hxfr_type & HXFR_HS ) {
       ep->xfer_complete = 1;
@@ -702,6 +762,10 @@ void hcd_int_handler(uint8_t rhport) {
     if (speed == TUSB_SPEED_INVALID) {
       hcd_event_device_remove(rhport, true);
     }else {
+      // FIXME multiple MAX3421 rootdevice address is not 1
+      uint8_t const daddr = 1;
+      free_ep(daddr);
+
       hcd_event_device_attach(rhport, true);
     }
   }
@@ -710,8 +774,8 @@ void hcd_int_handler(uint8_t rhport) {
   // not call this handler again. So we need to loop until all IRQ are cleared
   while ( hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ) ) {
     if ( hirq & HIRQ_RCVDAV_IRQ ) {
-      uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
-      hcd_ep_t *ep = &_hcd_data.ep[ep_num][1];
+      uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+      max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
       uint8_t xact_len;
 
       // RCVDAV_IRQ can trigger 2 times (dual buffered)

From ac00b9147298184ca0bd1eadac3a02e7e867085d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Aug 2023 17:26:57 +0700
Subject: [PATCH 2017/2085] add xact_out(), xact_in() to manage transfer

---
 src/portable/analog/max3421/hcd_max3421.c | 149 +++++++++++++---------
 1 file changed, 92 insertions(+), 57 deletions(-)

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index b0325f240..00b36201c 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -331,7 +331,7 @@ static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep
   for(size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
     // for control endpoint, skip direction check
-    if ( daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0) ) {
+    if (daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0)) {
       return ep;
     }
   }
@@ -362,6 +362,28 @@ TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr,
   }
 }
 
+//static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
+//  size_t idx = cur_ep - _hcd_data.ep;
+//
+//  // starting from next endpoint
+//  for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+//    max3421_ep_t* ep = &_hcd_data.ep[i];
+//    if (ep->xfer_pending) {
+//      return ep;
+//    }
+//  }
+//
+//  // wrap around including current endpoint
+//  for (size_t i = 0; i <= idx; i++) {
+//    max3421_ep_t* ep = &_hcd_data.ep[i];
+//    if (ep->xfer_pending) {
+//      return ep;
+//    }
+//  }
+//
+//  return NULL;
+//}
+
 //--------------------------------------------------------------------+
 // Controller API
 //--------------------------------------------------------------------+
@@ -548,6 +570,37 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
   return true;
 }
 
+void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  // Page 12: Programming BULK-OUT Transfers
+  // TODO double buffered
+  if (switch_ep) {
+    peraddr_write(rhport, ep->daddr, in_isr);
+
+    uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
+  }
+
+  uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+  fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
+  sndbc_write(rhport, xact_len, in_isr);
+
+  uint8_t const hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
+  hxfr_write(rhport, hxfr, in_isr);
+}
+
+void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  // Page 13: Programming BULK-IN Transfers
+  if (switch_ep) {
+    peraddr_write(rhport, ep->daddr, in_isr);
+
+    uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
+  }
+
+  uint8_t const hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
+  hxfr_write(rhport, hxfr, in_isr);
+}
+
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
   (void) rhport;
@@ -567,17 +620,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   // carry out transfer if not busy
 //  if ( atomic_flag_test_and_set(&_hcd_data.busy) )
   {
-    peraddr_write(rhport, daddr, false);
-
-    uint8_t hctl = 0;
     uint8_t hxfr = ep_num;
 
-    if ( ep->is_iso ) {
-      hxfr |= HXFR_ISO;
-    } else if ( ep_num == 0 ) {
+    if ( ep_num == 0 ) {
       ep->data_toggle = 1;
       if ( buffer == NULL || buflen == 0 ) {
         // ZLP for ACK stage, use HS
+        peraddr_write(rhport, daddr, false);
+
         hxfr |= HXFR_HS;
         hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
         hxfr_write(rhport, hxfr, false);
@@ -586,22 +636,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
     }
 
     if ( 0 == ep_dir ) {
-      // Page 12: Programming BULK-OUT Transfers
       TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
-
-      uint8_t const xact_len = (uint8_t) tu_min16(buflen, ep->packet_size);
-      fifo_write(rhport, SNDFIFO_ADDR, buffer, xact_len, false);
-      sndbc_write(rhport, xact_len, false);
-
-      hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
-      hxfr |= HXFR_OUT_NIN;
+      xact_out(rhport, ep, true, false);
     } else {
-      // Page 13: Programming BULK-IN Transfers
-      hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+      xact_in(rhport, ep, true, false);
     }
-
-    reg_write(rhport, HCTL_ADDR, hctl, false);
-    hxfr_write(rhport, hxfr, false);
   }
 
   return true;
@@ -644,7 +683,12 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 static void handle_xfer_done(uint8_t rhport) {
   uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
   uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
-  uint8_t ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+
+  uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
+  uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0;
+  uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
+
+  max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir);
 
   xfer_result_t xfer_result;
 
@@ -663,10 +707,11 @@ static void handle_xfer_done(uint8_t rhport) {
       return;
 
     case HRSL_NAK:
-      // NAK on control, retry immediately
-      //if (ep_num == 0)
-      {
+      if (ep_num == 0) {
+        // NAK on control, retry immediately
         hxfr_write(rhport, _hcd_data.hxfr, true);
+      }else {
+        // NAK on non-control, find next pending to switch
       }
       return;
 
@@ -675,40 +720,8 @@ static void handle_xfer_done(uint8_t rhport) {
       break;
   }
 
-  uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0;
-
-  if ( (hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN) ) {
-    // SETUP or OUT transfer
-    max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 0);
-    uint8_t xact_len;
-
-    if ( hxfr_type & HXFR_SETUP) {
-      xact_len = 8;
-    } else if ( hxfr_type & HXFR_HS ) {
-      xact_len = 0;
-    } else {
-      xact_len = _hcd_data.sndbc;
-    }
-
-    ep->xferred_len += xact_len;
-    ep->buf += xact_len;
-
-    if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
-      // save data toggle
-      ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
-      hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
-    }else {
-      // more to transfer
-      xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
-      fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, true);
-      sndbc_write(rhport, xact_len, true);
-
-      hxfr_write(rhport, _hcd_data.hxfr, true);
-    }
-  } else {
+  if (ep_dir) {
     // IN transfer: fifo data is already received in RCVDAV IRQ
-    max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
-
     if ( hxfr_type & HXFR_HS ) {
       ep->xfer_complete = 1;
     }
@@ -722,6 +735,28 @@ static void handle_xfer_done(uint8_t rhport) {
       // more to transfer
       hxfr_write(rhport, _hcd_data.hxfr, true);
     }
+  } else {
+    // SETUP or OUT transfer
+    uint8_t xact_len;
+
+    if (hxfr_type & HXFR_SETUP) {
+      xact_len = 8;
+    } else if (hxfr_type & HXFR_HS) {
+      xact_len = 0;
+    } else {
+      xact_len = _hcd_data.sndbc;
+    }
+
+    ep->xferred_len += xact_len;
+    ep->buf += xact_len;
+
+    if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
+      // save data toggle
+      ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
+      hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
+    } else {
+      xact_out(rhport, ep, false, true);
+    }
   }
 }
 

From cd7464a8847db5efa14f568bdf8746d898fc7eb4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 25 Aug 2023 17:37:09 +0700
Subject: [PATCH 2018/2085] try next endpoint when received NAK

---
 src/portable/analog/max3421/hcd_max3421.c | 58 +++++++++++++++--------
 1 file changed, 37 insertions(+), 21 deletions(-)

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 00b36201c..e546f99ce 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -362,27 +362,27 @@ TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr,
   }
 }
 
-//static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
-//  size_t idx = cur_ep - _hcd_data.ep;
-//
-//  // starting from next endpoint
-//  for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
-//    max3421_ep_t* ep = &_hcd_data.ep[i];
-//    if (ep->xfer_pending) {
-//      return ep;
-//    }
-//  }
-//
-//  // wrap around including current endpoint
-//  for (size_t i = 0; i <= idx; i++) {
-//    max3421_ep_t* ep = &_hcd_data.ep[i];
-//    if (ep->xfer_pending) {
-//      return ep;
-//    }
-//  }
-//
-//  return NULL;
-//}
+static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
+  size_t idx = cur_ep - _hcd_data.ep;
+
+  // starting from next endpoint
+  for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    if (ep->xfer_pending) {
+      return ep;
+    }
+  }
+
+  // wrap around including current endpoint
+  for (size_t i = 0; i <= idx; i++) {
+    max3421_ep_t* ep = &_hcd_data.ep[i];
+    if (ep->xfer_pending) {
+      return ep;
+    }
+  }
+
+  return NULL;
+}
 
 //--------------------------------------------------------------------+
 // Controller API
@@ -443,6 +443,7 @@ bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
   hcd_int_disable(rhport);
+  tuh_max3421_spi_cs_api(rhport, false);
 
   TU_LOG2_INT(sizeof(max3421_ep_t));
   TU_LOG2_INT(sizeof(max3421_data_t));
@@ -689,6 +690,7 @@ static void handle_xfer_done(uint8_t rhport) {
   uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
 
   max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir);
+  TU_ASSERT(ep, );
 
   xfer_result_t xfer_result;
 
@@ -712,6 +714,20 @@ static void handle_xfer_done(uint8_t rhport) {
         hxfr_write(rhport, _hcd_data.hxfr, true);
       }else {
         // NAK on non-control, find next pending to switch
+        max3421_ep_t *next_ep = find_next_pending_ep(ep);
+        TU_ASSERT(next_ep, );
+
+        if (ep == next_ep) {
+          // only one pending, retry immediately
+          hxfr_write(rhport, _hcd_data.hxfr, true);
+        }else {
+          // switch to next pending TODO could have issue with double buffered if not clear previously out data
+          if ( ep_dir ) {
+            xact_in(rhport, next_ep, true, true);
+          } else {
+            xact_out(rhport, next_ep, true, true);
+          }
+        }
       }
       return;
 

From 502b1bdda62f0f207d9a51daf134574e455f3aa2 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 27 Aug 2023 23:45:34 +0700
Subject: [PATCH 2019/2085] more update to transaction

---
 examples/host/cdc_msc_hid/src/tusb_config.h   |  9 ++--
 .../host/msc_file_explorer/src/tusb_config.h  | 10 ++--
 src/common/tusb_mcu.h                         | 12 +++++
 src/host/hcd.h                                |  4 +-
 src/host/usbh.c                               |  1 +
 src/portable/analog/max3421/hcd_max3421.c     | 51 ++++++++++++-------
 6 files changed, 62 insertions(+), 25 deletions(-)

diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index abb75f068..7d621d466 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -35,9 +35,12 @@
 //--------------------------------------------------------------------+
 
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
-// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB   0
-#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+  // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+  #define CFG_TUH_RPI_PIO_USB   0
+  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
+  #define CFG_TUH_MAX3421      1
 #endif
 
 // RHPort number used for host can be defined by board.mk, default to port 0
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index 1e0d067bf..bb2fd4cf5 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -35,11 +35,15 @@
 //--------------------------------------------------------------------+
 
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
-// change to 1 if using pico-pio-usb as host controller for raspberry rp2040
-#define CFG_TUH_RPI_PIO_USB   0
-#define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+  // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+  #define CFG_TUH_RPI_PIO_USB   0
+  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_US
+#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
+  #define CFG_TUH_MAX3421      1
 #endif
 
+
 // RHPort number used for host can be defined by board.mk, default to port 0
 #ifndef BOARD_TUH_RHPORT
 #define BOARD_TUH_RHPORT      0
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 35f94efbc..21939df7c 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -385,6 +385,18 @@
   #define TUP_RHPORT_HIGHSPEED    1
 #endif
 
+
+//--------------------------------------------------------------------+
+// External USB controller
+//--------------------------------------------------------------------+
+
+#if defined(CFG_TUH_MAX3421) & CFG_TUH_MAX3421
+  #ifndef CFG_TUH_MAX3421_ENDPOINT_TOTAL
+    #define CFG_TUH_MAX3421_ENDPOINT_TOTAL  (8 + 4*(CFG_TUH_DEVICE_MAX-1))
+  #endif
+#endif
+
+
 //--------------------------------------------------------------------+
 // Default Values
 //--------------------------------------------------------------------+
diff --git a/src/host/hcd.h b/src/host/hcd.h
index 1f01a1a2f..e25b20ea3 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -39,7 +39,7 @@
 // Configuration
 //--------------------------------------------------------------------+
 
-// Max number of endpoints per device
+// Max number of endpoints pair per device
 // TODO optimize memory usage
 #ifndef CFG_TUH_ENDPOINT_MAX
   #define CFG_TUH_ENDPOINT_MAX   16
@@ -167,7 +167,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
 //--------------------------------------------------------------------+
 
 // Open an endpoint
-bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
+bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc);
 
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 7a09f5b6e..12a7f5839 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -919,6 +919,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
   switch (event->event_id)
   {
 //    case HCD_EVENT_DEVICE_REMOVE:
+//      // FIXME device remove from a hub need an HCD API for hcd to free up endpoint
 //      // mark device as removing to prevent further xfer before the event is processed in usbh task
 //      break;
 
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index e546f99ce..574cca788 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -582,6 +582,7 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   }
 
   uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+  TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ, );
   fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
   sndbc_write(rhport, xact_len, in_isr);
 
@@ -602,6 +603,28 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   hxfr_write(rhport, hxfr, in_isr);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  if (ep->ep_dir) {
+    xact_in(rhport, ep, switch_ep, in_isr);
+  }else {
+    xact_out(rhport, ep, switch_ep, in_isr);
+  }
+}
+
+void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) {
+  (void) rhport;
+  (void) result;
+  ep->xfer_pending = 0;
+  ep->data_toggle = data_toggle;
+  //uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
+  //hcd_event_xfer_complete(rhport, ep_addr, ep->xferred_len, result, true);
+
+//  max3421_ep_t *next_ep = find_next_pending_ep(ep);
+//  if (next_ep) {
+//    xact_inout(rhport, next_ep, true, true);
+//  }
+}
+
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
   (void) rhport;
@@ -612,6 +635,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
   TU_ASSERT(ep);
 
+  // control transfer can switch direction
+  ep->ep_dir = ep_dir;
+
   ep->buf = buffer;
   ep->total_len = buflen;
   ep->xferred_len = 0;
@@ -636,12 +662,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
       }
     }
 
-    if ( 0 == ep_dir ) {
-      TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ);
-      xact_out(rhport, ep, true, false);
-    } else {
-      xact_in(rhport, ep, true, false);
-    }
+    xact_inout(rhport, ep, true, false);
   }
 
   return true;
@@ -662,6 +683,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   (void) rhport;
 
   max3421_ep_t* ep = find_opened_ep(daddr, 0, 0);
+  ep->ep_dir = 0;
   ep->total_len  = 8;
   ep->xferred_len = 0;
 
@@ -715,18 +737,13 @@ static void handle_xfer_done(uint8_t rhport) {
       }else {
         // NAK on non-control, find next pending to switch
         max3421_ep_t *next_ep = find_next_pending_ep(ep);
-        TU_ASSERT(next_ep, );
 
         if (ep == next_ep) {
           // only one pending, retry immediately
           hxfr_write(rhport, _hcd_data.hxfr, true);
-        }else {
+        }else if (next_ep) {
           // switch to next pending TODO could have issue with double buffered if not clear previously out data
-          if ( ep_dir ) {
-            xact_in(rhport, next_ep, true, true);
-          } else {
-            xact_out(rhport, next_ep, true, true);
-          }
+          xact_inout(rhport, next_ep, true, true);
         }
       }
       return;
@@ -744,8 +761,8 @@ static void handle_xfer_done(uint8_t rhport) {
 
     // short packet or all bytes transferred
     if ( ep->xfer_complete ) {
-      // save data toggle
-      ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
+      uint8_t const dt = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; // save data toggle
+      xfer_complete_isr(rhport, ep, xfer_result, dt);
       hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
@@ -767,8 +784,8 @@ static void handle_xfer_done(uint8_t rhport) {
     ep->buf += xact_len;
 
     if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
-      // save data toggle
-      ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
+      uint8_t const dt = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; // save data toggle
+      xfer_complete_isr(rhport, ep, xfer_result, dt);
       hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
     } else {
       xact_out(rhport, ep, false, true);

From 84df3b04db47d34b53ef002b056b6b324394de52 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sun, 27 Aug 2023 23:54:24 +0700
Subject: [PATCH 2020/2085] minor update

---
 .idea/cmake.xml                                   | 5 +++--
 .idea/runConfigurations/nrf52840.xml              | 2 +-
 examples/host/cdc_msc_hid/src/tusb_config.h       | 6 +++---
 examples/host/msc_file_explorer/src/tusb_config.h | 6 +++---
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 8ee7f09a0..86e7c6606 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -30,9 +30,10 @@
       <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="ea4357" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4357 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="lpc54628" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="lpc55s69" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69 -DLOG=4 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpc54628" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="feather_nrf52840_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_nrf52840_express -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g0b1nucleo" />
diff --git a/.idea/runConfigurations/nrf52840.xml b/.idea/runConfigurations/nrf52840.xml
index 084669c39..2f3f1876a 100644
--- a/.idea/runConfigurations/nrf52840.xml
+++ b/.idea/runConfigurations/nrf52840.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="nrf52840" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;nrf52840_xxaa&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="nrf52840" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;nrf52840_xxaa&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="msc_file_explorer" TARGET_NAME="msc_file_explorer" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="msc_file_explorer" RUN_TARGET_NAME="msc_file_explorer">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 7d621d466..8d3ef8891 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -38,9 +38,9 @@
   // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
   #define CFG_TUH_RPI_PIO_USB   0
   #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
-#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
-  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
-  #define CFG_TUH_MAX3421      1
+//#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+//  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
+//  #define CFG_TUH_MAX3421      1
 #endif
 
 // RHPort number used for host can be defined by board.mk, default to port 0
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index bb2fd4cf5..28e130c0e 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -38,9 +38,9 @@
   // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
   #define CFG_TUH_RPI_PIO_USB   0
   #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_US
-#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
-  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
-  #define CFG_TUH_MAX3421      1
+//#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
+//  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
+//  #define CFG_TUH_MAX3421      1
 #endif
 
 

From b31924e13edff0f29829056152348a9255e72169 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 28 Aug 2023 12:41:44 +0700
Subject: [PATCH 2021/2085] - add xfer_complete_isr() - merge addr0 ep to pool
 - add control status to xact in/out - use atomic flag busy to ensure only 1
 transfer is active at any time - execute pending transfer after one is
 complete (or clear busy flag) - change rtt mode to block if full

---
 hw/bsp/family_support.cmake               |   1 +
 src/portable/analog/max3421/hcd_max3421.c | 118 +++++++++++-----------
 2 files changed, 62 insertions(+), 57 deletions(-)

diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 7c89427c0..1cbcfb2a7 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -216,6 +216,7 @@ function(family_configure_common TARGET RTOS)
       if (NOT TARGET segger_rtt)
         add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c)
         target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT)
+        target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL)
       endif()
       target_link_libraries(${TARGET} PUBLIC segger_rtt)
     endif ()
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 574cca788..262dbca0f 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -195,9 +195,7 @@ typedef struct {
   uint8_t hxfr;
 
   volatile uint16_t frame_count;
-
-  max3421_ep_t ep0_addr0; // control endpoint for addr0
-  max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL];
+  max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
 
   OSAL_MUTEX_DEF(spi_mutexdef);
 #if OSAL_MUTEX_REQUIRED
@@ -328,7 +326,7 @@ static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
 //--------------------------------------------------------------------+
 
 static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
-  for(size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+  for(size_t i=1; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
     // for control endpoint, skip direction check
     if (daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0)) {
@@ -344,9 +342,17 @@ TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * allocate_ep(void) {
   return find_ep_not_addr0(0, 0, 0);
 }
 
+TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
+  if (daddr == 0 && ep_num == 0) {
+    return &_hcd_data.ep[0];
+  }else{
+    return find_ep_not_addr0(daddr, ep_num, ep_dir);
+  }
+}
+
 // free all endpoints belong to device address
 static void free_ep(uint8_t daddr) {
-  for (size_t i=0; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
+  for (size_t i=1; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
     if (ep->daddr == daddr) {
       tu_memclr(ep, sizeof(max3421_ep_t));
@@ -354,16 +360,8 @@ static void free_ep(uint8_t daddr) {
   }
 }
 
-TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
-  if (daddr == 0 && ep_num == 0) {
-    return &_hcd_data.ep0_addr0;
-  }else{
-    return find_ep_not_addr0(daddr, ep_num, ep_dir);
-  }
-}
-
 static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
-  size_t idx = cur_ep - _hcd_data.ep;
+  size_t const idx = cur_ep - _hcd_data.ep;
 
   // starting from next endpoint
   for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
@@ -553,7 +551,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
 
   max3421_ep_t * ep;
   if (daddr == 0 && ep_num == 0) {
-    ep = &_hcd_data.ep0_addr0;
+    ep = &_hcd_data.ep[0];
   }else {
     ep = allocate_ep();
     TU_ASSERT(ep);
@@ -581,12 +579,20 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
     reg_write(rhport, HCTL_ADDR, hctl, in_isr);
   }
 
-  uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
-  TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ, );
-  fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
-  sndbc_write(rhport, xact_len, in_isr);
+  uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
+
+  if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
+    // Control ZLP status use HS
+    hxfr |= HXFR_HS;
+  } else {
+    uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+    TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
+    if (xact_len) {
+      fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
+    }
+    sndbc_write(rhport, xact_len, in_isr);
+  }
 
-  uint8_t const hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
   hxfr_write(rhport, hxfr, in_isr);
 }
 
@@ -599,7 +605,12 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
     reg_write(rhport, HCTL_ADDR, hctl, in_isr);
   }
 
-  uint8_t const hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
+  uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
+  if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
+    // Control ZLP status use HS
+    hxfr |= HXFR_HS;
+  }
+
   hxfr_write(rhport, hxfr, in_isr);
 }
 
@@ -611,24 +622,8 @@ TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t
   }
 }
 
-void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) {
-  (void) rhport;
-  (void) result;
-  ep->xfer_pending = 0;
-  ep->data_toggle = data_toggle;
-  //uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
-  //hcd_event_xfer_complete(rhport, ep_addr, ep->xferred_len, result, true);
-
-//  max3421_ep_t *next_ep = find_next_pending_ep(ep);
-//  if (next_ep) {
-//    xact_inout(rhport, next_ep, true, true);
-//  }
-}
-
 // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
 bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
-  (void) rhport;
-
   uint8_t const ep_num = tu_edpt_number(ep_addr);
   uint8_t const ep_dir = tu_edpt_dir(ep_addr);
 
@@ -644,24 +639,12 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->xfer_complete = 0;
   ep->xfer_pending = 1;
 
+  if ( ep_num == 0 ) {
+    ep->data_toggle = 1;
+  }
+
   // carry out transfer if not busy
-//  if ( atomic_flag_test_and_set(&_hcd_data.busy) )
-  {
-    uint8_t hxfr = ep_num;
-
-    if ( ep_num == 0 ) {
-      ep->data_toggle = 1;
-      if ( buffer == NULL || buflen == 0 ) {
-        // ZLP for ACK stage, use HS
-        peraddr_write(rhport, daddr, false);
-
-        hxfr |= HXFR_HS;
-        hxfr |= (ep_dir ? 0 : HXFR_OUT_NIN);
-        hxfr_write(rhport, hxfr, false);
-        return true;
-      }
-    }
-
+  if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
     xact_inout(rhport, ep, true, false);
   }
 
@@ -683,6 +666,8 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   (void) rhport;
 
   max3421_ep_t* ep = find_opened_ep(daddr, 0, 0);
+  TU_ASSERT(ep);
+
   ep->ep_dir = 0;
   ep->total_len  = 8;
   ep->xferred_len = 0;
@@ -703,6 +688,26 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
   return false;
 }
 
+//--------------------------------------------------------------------+
+// Interrupt Handler
+//--------------------------------------------------------------------+
+
+static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) {
+  uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
+  ep->data_toggle = data_toggle;
+  ep->xfer_pending = 0;
+  hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, true);
+
+  // Find next pending endpoint
+  max3421_ep_t *next_ep = find_next_pending_ep(ep);
+  if (next_ep) {
+    xact_inout(rhport, next_ep, true, true);
+  }else {
+    // no more pending
+    atomic_flag_clear(&_hcd_data.busy);
+  }
+}
+
 static void handle_xfer_done(uint8_t rhport) {
   uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
   uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
@@ -739,7 +744,7 @@ static void handle_xfer_done(uint8_t rhport) {
         max3421_ep_t *next_ep = find_next_pending_ep(ep);
 
         if (ep == next_ep) {
-          // only one pending, retry immediately
+          // this endpoint is only one pending, retry immediately
           hxfr_write(rhport, _hcd_data.hxfr, true);
         }else if (next_ep) {
           // switch to next pending TODO could have issue with double buffered if not clear previously out data
@@ -763,7 +768,6 @@ static void handle_xfer_done(uint8_t rhport) {
     if ( ep->xfer_complete ) {
       uint8_t const dt = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; // save data toggle
       xfer_complete_isr(rhport, ep, xfer_result, dt);
-      hcd_event_xfer_complete(_hcd_data.peraddr, TUSB_DIR_IN_MASK | ep_num, ep->xferred_len, xfer_result, true);
     }else {
       // more to transfer
       hxfr_write(rhport, _hcd_data.hxfr, true);
@@ -786,8 +790,8 @@ static void handle_xfer_done(uint8_t rhport) {
     if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
       uint8_t const dt = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; // save data toggle
       xfer_complete_isr(rhport, ep, xfer_result, dt);
-      hcd_event_xfer_complete(_hcd_data.peraddr, ep_num, ep->xferred_len, xfer_result, true);
     } else {
+      // more to transfer
       xact_out(rhport, ep, false, true);
     }
   }

From c35061603836353e2e13c7bceafdafced1785dde Mon Sep 17 00:00:00 2001
From: yuxiaojun <yuxiaojun1011@outlook.com>
Date: Mon, 28 Aug 2023 15:24:14 +0800
Subject: [PATCH 2022/2085] fix:Resource leak: fp

Signed-off-by: yuxiaojun <yuxiaojun1011@outlook.com>
---
 hw/mcu/sony/cxd56/mkspk/mkspk.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/mcu/sony/cxd56/mkspk/mkspk.c b/hw/mcu/sony/cxd56/mkspk/mkspk.c
index c447ad7da..3feb235f6 100644
--- a/hw/mcu/sony/cxd56/mkspk/mkspk.c
+++ b/hw/mcu/sony/cxd56/mkspk/mkspk.c
@@ -172,6 +172,7 @@ static struct elf_file *load_elf(const char *filename)
   ef = (struct elf_file *)malloc(sizeof(*ef));
   if (!ef)
     {
+      fclose(fp);
       return NULL;
     }
 
@@ -182,6 +183,7 @@ static struct elf_file *load_elf(const char *filename)
   buf = (char *)malloc(fsize);
   if (!buf)
     {
+      fclose(fp);
       return NULL;
     }
 

From 3740a3287ad5965df34639e90bfa890b36c0fd60 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 29 Aug 2023 18:22:21 +0700
Subject: [PATCH 2023/2085] - correct tuh_max3421e_int_api() for nrf52 -
 hcd_int_disable/enable is software only to reduce interrupt lag

---
 hw/bsp/nrf/boards/pca10056/board.h        |  9 +++
 hw/bsp/nrf/family.c                       | 20 +++++-
 src/portable/analog/max3421/hcd_max3421.c | 86 ++++++++++++++++-------
 3 files changed, 87 insertions(+), 28 deletions(-)

diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h
index f4368f830..16d31addb 100644
--- a/hw/bsp/nrf/boards/pca10056/board.h
+++ b/hw/bsp/nrf/boards/pca10056/board.h
@@ -31,6 +31,8 @@
  extern "C" {
 #endif
 
+#define _PINNUM(port, pin)    ((port)*32 + (pin))
+
 // LED
 #define LED_PIN               13
 #define LED_STATE_ON          0
@@ -43,6 +45,13 @@
 #define UART_RX_PIN           8
 #define UART_TX_PIN           6
 
+// SPI for USB host shield
+#define MAX3421E_SCK_PIN  _PINNUM(1, 15)
+#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
+#define MAX3421E_MISO_PIN _PINNUM(1, 14)
+#define MAX3421E_CS_PIN   _PINNUM(1, 12)
+#define MAX3241E_INTR_PIN _PINNUM(1, 11)
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 368763b84..083efc235 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -107,7 +107,12 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
 //--------------------------------------------------------------------+
 void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
-  nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, enabled);
+
+  if (enabled) {
+    nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
+  }else {
+    nrfx_gpiote_trigger_disable(MAX3241E_INTR_PIN);
+  }
 }
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
@@ -217,6 +222,19 @@ void board_init(void) {
 #endif
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+  // MAX3421 need 3.3v signal
+  if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+
+    NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3;
+
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+
+    NVIC_SystemReset();
+  }
+
   // manually manage CS
   nrf_gpio_cfg_output(MAX3421E_CS_PIN);
   tuh_max3421_spi_cs_api(0, false);
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 262dbca0f..cb7911992 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -184,8 +184,6 @@ typedef struct {
 } max3421_ep_t;
 
 typedef struct {
-  atomic_flag busy; // busy transferring
-
   // cached register
   uint8_t sndbc;
   uint8_t hirq;
@@ -194,7 +192,10 @@ typedef struct {
   uint8_t peraddr;
   uint8_t hxfr;
 
+  atomic_flag busy; // busy transferring
+  volatile uint8_t intr_disable_count;
   volatile uint16_t frame_count;
+
   max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
 
   OSAL_MUTEX_DEF(spi_mutexdef);
@@ -220,8 +221,8 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
 static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
   // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
   if (!in_isr) {
-    tuh_max3421e_int_api(rhport, false);
     (void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+    tuh_max3421e_int_api(rhport, false);
   }
 
   // assert CS
@@ -294,6 +295,12 @@ static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
   return ret ? rx_buf[1] : 0;
 }
 
+static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
+  reg_write(rhport, HIRQ_ADDR, data, in_isr);
+  // HIRQ write 1 is clear
+  _hcd_data.hirq &= ~data;
+}
+
 static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
   _hcd_data.hien = data;
   reg_write(rhport, HIEN_ADDR, data, in_isr);
@@ -440,13 +447,14 @@ tusb_speed_t handle_connect_irq(uint8_t rhport) {
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
-  hcd_int_disable(rhport);
+  tuh_max3421e_int_api(rhport, false);
   tuh_max3421_spi_cs_api(rhport, false);
 
   TU_LOG2_INT(sizeof(max3421_ep_t));
   TU_LOG2_INT(sizeof(max3421_data_t));
 
   tu_memclr(&_hcd_data, sizeof(_hcd_data));
+  _hcd_data.peraddr = 0xff; // invalid
 
 #if OSAL_MUTEX_REQUIRED
   _hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef);
@@ -469,11 +477,13 @@ bool hcd_init(uint8_t rhport) {
   reg_write(rhport, HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST, false);
 
   // clear all previously pending IRQ
-  reg_write(rhport, HIRQ_ADDR, 0xff, false);
+  hirq_write(rhport, 0xff, false);
 
   // Enable IRQ
   hien_write(rhport, DEFAULT_HIEN, false);
 
+  tuh_max3421e_int_api(rhport, true);
+
   // Enable Interrupt pin
   reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
 
@@ -481,13 +491,21 @@ bool hcd_init(uint8_t rhport) {
 }
 
 // Enable USB interrupt
+// Not actually enable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_enable (uint8_t rhport) {
-  tuh_max3421e_int_api(rhport, true);
+  (void) rhport;
+  // tuh_max3421e_int_api(rhport, true);
+  if (_hcd_data.intr_disable_count) {
+    _hcd_data.intr_disable_count--;
+  }
 }
 
 // Disable USB interrupt
+// Not actually disable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_disable(uint8_t rhport) {
-  tuh_max3421e_int_api(rhport, false);
+  (void) rhport;
+  //tuh_max3421e_int_api(rhport, false);
+  _hcd_data.intr_disable_count++;
 }
 
 // Get frame number (1ms)
@@ -521,7 +539,7 @@ void hcd_port_reset_end(uint8_t rhport) {
   reg_write(rhport, HCTL_ADDR, 0, false);
 
   // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
-  reg_write(rhport, HIRQ_ADDR, HIRQ_CONDET_IRQ, false);
+  hirq_write(rhport, HIRQ_CONDET_IRQ, false);
   hien_write(rhport, DEFAULT_HIEN, false);
 }
 
@@ -572,19 +590,23 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
 void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   // Page 12: Programming BULK-OUT Transfers
   // TODO double buffered
-  if (switch_ep) {
-    peraddr_write(rhport, ep->daddr, in_isr);
-
-    uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
-    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
-  }
 
   uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
-
   if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
     // Control ZLP status use HS
     hxfr |= HXFR_HS;
-  } else {
+  }
+
+  if (switch_ep) {
+    peraddr_write(rhport, ep->daddr, in_isr);
+
+    if ( 0 == (hxfr & HXFR_HS) ) {
+      uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+      reg_write(rhport, HCTL_ADDR, hctl, in_isr);
+    }
+  }
+
+  if ( 0 == (hxfr & HXFR_HS) ) {
     uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
     TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
     if (xact_len) {
@@ -598,12 +620,6 @@ void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
 
 void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   // Page 13: Programming BULK-IN Transfers
-  if (switch_ep) {
-    peraddr_write(rhport, ep->daddr, in_isr);
-
-    uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
-    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
-  }
 
   uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
   if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
@@ -611,6 +627,15 @@ void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
     hxfr |= HXFR_HS;
   }
 
+  if (switch_ep) {
+    peraddr_write(rhport, ep->daddr, in_isr);
+
+    if ( 0 == (hxfr & HXFR_HS) ) {
+      uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+      reg_write(rhport, HCTL_ADDR, hctl, in_isr);
+    }
+  }
+
   hxfr_write(rhport, hxfr, in_isr);
 }
 
@@ -721,7 +746,7 @@ static void handle_xfer_done(uint8_t rhport) {
 
   xfer_result_t xfer_result;
 
-  //TU_LOG3("HRSL: %02X\r\n", hrsl);
+//  TU_LOG3("HRSL: %02X\r\n", hrsl);
   switch(hresult) {
     case HRSL_SUCCESS:
       xfer_result = XFER_RESULT_SUCCESS;
@@ -821,13 +846,20 @@ void print_hirq(uint8_t hirq) {
 void hcd_int_handler(uint8_t rhport) {
   uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
   if (!hirq) return;
-
 //  print_hirq(hirq);
 
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
   }
 
+  // interrupt is disabled, only ack FRAME IRQ and skip the rest
+  if (_hcd_data.intr_disable_count) {
+    if (hirq & HIRQ_FRAME_IRQ) {
+      hirq_write(rhport, HIRQ_FRAME_IRQ, true);
+    }
+    return;
+  }
+
   if (hirq & HIRQ_CONDET_IRQ) {
     tusb_speed_t speed = handle_connect_irq(rhport);
 
@@ -861,7 +893,7 @@ void hcd_int_handler(uint8_t rhport) {
         }
 
         // ack RCVDVAV IRQ
-        reg_write(rhport, HIRQ_ADDR, HIRQ_RCVDAV_IRQ, true);
+        hirq_write(rhport, HIRQ_RCVDAV_IRQ, true);
         hirq = reg_read(rhport, HIRQ_ADDR, true);
       }
 
@@ -871,7 +903,7 @@ void hcd_int_handler(uint8_t rhport) {
     }
 
     if ( hirq & HIRQ_HXFRDN_IRQ ) {
-      reg_write(rhport, HIRQ_ADDR, HIRQ_HXFRDN_IRQ, true);
+      hirq_write(rhport, HIRQ_HXFRDN_IRQ, true);
       handle_xfer_done(rhport);
     }
 
@@ -881,7 +913,7 @@ void hcd_int_handler(uint8_t rhport) {
   // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
   hirq &= ~HIRQ_SNDBAV_IRQ;
   if ( hirq ) {
-    reg_write(rhport, HIRQ_ADDR, hirq, true);
+    hirq_write(rhport, hirq, true);
   }
 }
 

From 2a814a99af32bf084cbb730d97e3c9cb31a3fa85 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 29 Aug 2023 20:27:37 +0700
Subject: [PATCH 2024/2085] - hcd_setup_send() also check for busy flag -
 xact_inout() to support send setup

---
 src/portable/analog/max3421/hcd_max3421.c | 71 +++++++++++++----------
 1 file changed, 39 insertions(+), 32 deletions(-)

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index cb7911992..461e02593 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -168,6 +168,7 @@ typedef struct {
   struct TU_ATTR_PACKED {
     uint8_t ep_dir        : 1;
     uint8_t is_iso        : 1;
+    uint8_t is_setup      : 1;
     uint8_t data_toggle   : 1;
     uint8_t xfer_pending  : 1;
     uint8_t xfer_complete : 1;
@@ -590,56 +591,55 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e
 void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   // Page 12: Programming BULK-OUT Transfers
   // TODO double buffered
-
-  uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
-  if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
-    // Control ZLP status use HS
-    hxfr |= HXFR_HS;
-  }
-
   if (switch_ep) {
     peraddr_write(rhport, ep->daddr, in_isr);
 
-    if ( 0 == (hxfr & HXFR_HS) ) {
-      uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
-      reg_write(rhport, HCTL_ADDR, hctl, in_isr);
-    }
+    uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
+    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
   }
 
-  if ( 0 == (hxfr & HXFR_HS) ) {
-    uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
-    TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
-    if (xact_len) {
-      fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
-    }
-    sndbc_write(rhport, xact_len, in_isr);
+  uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
+  TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
+  if (xact_len) {
+    fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
   }
+  sndbc_write(rhport, xact_len, in_isr);
 
+  uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
   hxfr_write(rhport, hxfr, in_isr);
 }
 
 void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
   // Page 13: Programming BULK-IN Transfers
-
-  uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
-  if (ep->ep_num == 0 && (ep->buf == NULL || ep->total_len == 0)) {
-    // Control ZLP status use HS
-    hxfr |= HXFR_HS;
-  }
-
   if (switch_ep) {
     peraddr_write(rhport, ep->daddr, in_isr);
 
-    if ( 0 == (hxfr & HXFR_HS) ) {
-      uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
-      reg_write(rhport, HCTL_ADDR, hctl, in_isr);
-    }
+    uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
+    reg_write(rhport, HCTL_ADDR, hctl, in_isr);
   }
 
+  uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
   hxfr_write(rhport, hxfr, in_isr);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
+  if (ep->ep_num == 0 ) {
+    // setup
+    if (ep->is_setup) {
+      peraddr_write(rhport, ep->daddr, in_isr);
+      hxfr_write(rhport, HXFR_SETUP, in_isr);
+      return;
+    }
+
+    // status
+    if (ep->buf == NULL || ep->total_len == 0) {
+      uint8_t const hxfr = HXFR_HS | (ep->ep_dir ? 0 : HXFR_OUT_NIN);
+      peraddr_write(rhport, ep->daddr, in_isr);
+      hxfr_write(rhport, hxfr, in_isr);
+      return;
+    }
+  }
+
   if (ep->ep_dir) {
     xact_in(rhport, ep, switch_ep, in_isr);
   }else {
@@ -665,12 +665,15 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   ep->xfer_pending = 1;
 
   if ( ep_num == 0 ) {
+    ep->is_setup = 0;
     ep->data_toggle = 1;
   }
 
   // carry out transfer if not busy
   if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
     xact_inout(rhport, ep, true, false);
+  } else {
+    return true;
   }
 
   return true;
@@ -694,12 +697,16 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   TU_ASSERT(ep);
 
   ep->ep_dir = 0;
-  ep->total_len  = 8;
+  ep->total_len = 8;
   ep->xferred_len = 0;
+  ep->is_setup = 1;
 
-  peraddr_write(rhport, daddr, false);
   fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false);
-  hxfr_write(rhport, HXFR_SETUP, false);
+
+  // carry out transfer if not busy
+  if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
+    xact_inout(rhport, ep, true, false);
+  }
 
   return true;
 }

From 1ab488eb06ef4cb8ad9c0cff91e6b0caf76f73c4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 30 Aug 2023 16:04:18 +0700
Subject: [PATCH 2025/2085] call xfer_complete_isr() when result is not
 successful (stalled or failed)

---
 hw/bsp/nrf/boards/pca10095/board.h        |  9 +++++
 hw/bsp/nrf/family.c                       |  7 ++--
 hw/bsp/nrf/nrfx_config.h                  |  2 +-
 src/common/tusb_mcu.h                     |  2 +-
 src/portable/analog/max3421/hcd_max3421.c | 43 ++++++++++++++++-------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h
index fd3c63d6a..b9d3a19dc 100644
--- a/hw/bsp/nrf/boards/pca10095/board.h
+++ b/hw/bsp/nrf/boards/pca10095/board.h
@@ -31,6 +31,8 @@
  extern "C" {
 #endif
 
+#define _PINNUM(port, pin)    ((port)*32 + (pin))
+
 // LED
 #define LED_PIN               28
 #define LED_STATE_ON          0
@@ -43,6 +45,13 @@
 #define UART_RX_PIN           32
 #define UART_TX_PIN           33
 
+// SPI for USB host shield
+#define MAX3421E_SCK_PIN  _PINNUM(1, 15)
+#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
+#define MAX3421E_MISO_PIN _PINNUM(1, 14)
+#define MAX3421E_CS_PIN   _PINNUM(1, 12)
+#define MAX3241E_INTR_PIN _PINNUM(1, 11)
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 083efc235..2b4260083 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -34,6 +34,7 @@
 #pragma GCC diagnostic ignored "-Wcast-align"
 #pragma GCC diagnostic ignored "-Wunused-parameter"
 #pragma GCC diagnostic ignored "-Wundef"
+#pragma GCC diagnostic ignored "-Wredundant-decls"
 #endif
 
 #include "nrfx.h"
@@ -94,7 +95,7 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 
 //------------- Host using MAX2341E -------------//
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(0);
+static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 
 void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
   if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return;
@@ -222,7 +223,8 @@ void board_init(void) {
 #endif
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-  // MAX3421 need 3.3v signal
+  // MAX3421 need 3.3v signal (may not be needed)
+  #if defined(UICR_REGOUT0_VOUT_Msk) && 0
   if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
     NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
     while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@@ -234,6 +236,7 @@ void board_init(void) {
 
     NVIC_SystemReset();
   }
+  #endif
 
   // manually manage CS
   nrf_gpio_cfg_output(MAX3421E_CS_PIN);
diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h
index e3d0ea91b..95ef33ce4 100644
--- a/hw/bsp/nrf/nrfx_config.h
+++ b/hw/bsp/nrf/nrfx_config.h
@@ -11,7 +11,7 @@
 #define NRFX_UARTE0_ENABLED  1
 
 #define NRFX_SPIM_ENABLED    1
-#define NRFX_SPIM0_ENABLED   1
+#define NRFX_SPIM1_ENABLED   1 // use SPI1 since nrf5340 share uart with spi
 
 #define NRFX_PRS_ENABLED     0
 #define NRFX_USBREG_ENABLED  1
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 21939df7c..8807ff8aa 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -390,7 +390,7 @@
 // External USB controller
 //--------------------------------------------------------------------+
 
-#if defined(CFG_TUH_MAX3421) & CFG_TUH_MAX3421
+#if defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
   #ifndef CFG_TUH_MAX3421_ENDPOINT_TOTAL
     #define CFG_TUH_MAX3421_ENDPOINT_TOTAL  (8 + 4*(CFG_TUH_DEVICE_MAX-1))
   #endif
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 461e02593..705bb5bfd 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -374,7 +374,8 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   // starting from next endpoint
   for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->xfer_pending) {
+    if (ep->xfer_pending && ep->packet_size) {
+//      TU_LOG3("next pending i = %u\n", i);
       return ep;
     }
   }
@@ -382,7 +383,8 @@ static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
   // wrap around including current endpoint
   for (size_t i = 0; i <= idx; i++) {
     max3421_ep_t* ep = &_hcd_data.ep[i];
-    if (ep->xfer_pending) {
+    if (ep->xfer_pending && ep->packet_size) {
+//      TU_LOG3("next pending i = %u\n", i);
       return ep;
     }
   }
@@ -464,6 +466,10 @@ bool hcd_init(uint8_t rhport) {
   // full duplex, interrupt negative edge
   reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
 
+  // V1 is 0x01, V2 is 0x12, V3 is 0x13
+  // uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
+  // TU_LOG2_HEX(revision);
+
   // reset
   reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
   reg_write(rhport, USBCTL_ADDR, 0, false);
@@ -699,6 +705,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   ep->ep_dir = 0;
   ep->total_len = 8;
   ep->xferred_len = 0;
+  ep->xfer_pending = 1;
   ep->is_setup = 1;
 
   fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false);
@@ -724,9 +731,16 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 // Interrupt Handler
 //--------------------------------------------------------------------+
 
-static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t data_toggle) {
+static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl) {
   uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
-  ep->data_toggle = data_toggle;
+
+  // save data toggle
+  if (ep->ep_dir) {
+    ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
+  }else {
+    ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
+  }
+
   ep->xfer_pending = 0;
   hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, true);
 
@@ -763,10 +777,6 @@ static void handle_xfer_done(uint8_t rhport) {
       xfer_result = XFER_RESULT_STALLED;
       break;
 
-    case HRSL_BAD_REQ:
-      // occurred when initialized without any pending transfer. Skip for now
-      return;
-
     case HRSL_NAK:
       if (ep_num == 0) {
         // NAK on control, retry immediately
@@ -781,15 +791,26 @@ static void handle_xfer_done(uint8_t rhport) {
         }else if (next_ep) {
           // switch to next pending TODO could have issue with double buffered if not clear previously out data
           xact_inout(rhport, next_ep, true, true);
+        }else {
+          TU_ASSERT(false,);
         }
       }
       return;
 
+    case HRSL_BAD_REQ:
+      // occurred when initialized without any pending transfer. Skip for now
+      return;
+
     default:
       xfer_result = XFER_RESULT_FAILED;
       break;
   }
 
+  if (xfer_result != XFER_RESULT_SUCCESS) {
+    xfer_complete_isr(rhport, ep, xfer_result, hrsl);
+    return;
+  }
+
   if (ep_dir) {
     // IN transfer: fifo data is already received in RCVDAV IRQ
     if ( hxfr_type & HXFR_HS ) {
@@ -798,8 +819,7 @@ static void handle_xfer_done(uint8_t rhport) {
 
     // short packet or all bytes transferred
     if ( ep->xfer_complete ) {
-      uint8_t const dt = (hrsl & HRSL_RCVTOGRD) ? 1 : 0; // save data toggle
-      xfer_complete_isr(rhport, ep, xfer_result, dt);
+      xfer_complete_isr(rhport, ep, xfer_result, hrsl);
     }else {
       // more to transfer
       hxfr_write(rhport, _hcd_data.hxfr, true);
@@ -820,8 +840,7 @@ static void handle_xfer_done(uint8_t rhport) {
     ep->buf += xact_len;
 
     if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
-      uint8_t const dt = (hrsl & HRSL_SNDTOGRD) ? 1 : 0; // save data toggle
-      xfer_complete_isr(rhport, ep, xfer_result, dt);
+      xfer_complete_isr(rhport, ep, xfer_result, hrsl);
     } else {
       // more to transfer
       xact_out(rhport, ep, false, true);

From 41493426b38c8ce44b1f7720b907538bc5402f98 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 30 Aug 2023 16:21:43 +0700
Subject: [PATCH 2026/2085] use ep buf to keep setup packet, work well with hid
 device

---
 examples/host/msc_file_explorer/src/tusb_config.h | 2 +-
 src/portable/analog/max3421/hcd_max3421.c         | 7 ++++---
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index 28e130c0e..e6186ba46 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -37,7 +37,7 @@
 #if CFG_TUSB_MCU == OPT_MCU_RP2040
   // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
   #define CFG_TUH_RPI_PIO_USB   0
-  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_US
+  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
 //#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
 //  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
 //  #define CFG_TUH_MAX3421      1
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 705bb5bfd..d644390da 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -633,6 +633,7 @@ TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t
     // setup
     if (ep->is_setup) {
       peraddr_write(rhport, ep->daddr, in_isr);
+      fifo_write(rhport, SUDFIFO_ADDR, ep->buf, 8, in_isr);
       hxfr_write(rhport, HXFR_SETUP, in_isr);
       return;
     }
@@ -703,12 +704,12 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]
   TU_ASSERT(ep);
 
   ep->ep_dir = 0;
+  ep->is_setup = 1;
+  ep->buf = (uint8_t*)(uintptr_t) setup_packet;
   ep->total_len = 8;
   ep->xferred_len = 0;
+  ep->xfer_complete = 0;
   ep->xfer_pending = 1;
-  ep->is_setup = 1;
-
-  fifo_write(rhport, SUDFIFO_ADDR, setup_packet, 8, false);
 
   // carry out transfer if not busy
   if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {

From 3b7d5aa0421f3d3a7ac199de0138dc40141fbddd Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 31 Aug 2023 16:52:09 +0700
Subject: [PATCH 2027/2085] improve connection & disconnection detection. But
 there is still issue when CONDETIRQ occurs but we are disabled interrupt (for
 osal queue access).

---
 hw/bsp/board.c                            | 26 +++----
 hw/bsp/nrf/family.c                       | 49 ++++++-------
 src/host/usbh.c                           |  2 +-
 src/portable/analog/max3421/hcd_max3421.c | 89 +++++++++++------------
 4 files changed, 74 insertions(+), 92 deletions(-)

diff --git a/hw/bsp/board.c b/hw/bsp/board.c
index 417630a03..562792625 100644
--- a/hw/bsp/board.c
+++ b/hw/bsp/board.c
@@ -44,17 +44,16 @@
 
 // If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead
 #if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM)
+
 #include "SEGGER_RTT.h"
 
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+TU_ATTR_USED int sys_write(int fhdl, const void *buf, size_t count) {
   (void) fhdl;
-  SEGGER_RTT_Write(0, (const char*) buf, (int) count);
+  SEGGER_RTT_Write(0, (const char *) buf, (int) count);
   return count;
 }
 
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
+TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) {
   (void) fhdl;
   int rd = (int) SEGGER_RTT_Read(0, buf, count);
   return (rd > 0) ? rd : -1;
@@ -67,8 +66,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 
 #include "board_mcu.h"
 
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) {
   (void) fhdl;
   uint8_t const* buf8 = (uint8_t const*) buf;
 
@@ -79,8 +77,7 @@ TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
   return (int) count;
 }
 
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
+TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) {
   (void) fhdl;
   (void) buf;
   (void) count;
@@ -90,14 +87,12 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 #else
 
 // Default logging with on-board UART
-TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count)
-{
+TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) {
   (void) fhdl;
   return board_uart_write(buf, (int) count);
 }
 
-TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
-{
+TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) {
   (void) fhdl;
   int rd = board_uart_read((uint8_t*) buf, (int) count);
   return (rd > 0) ? rd : -1;
@@ -105,8 +100,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count)
 
 #endif
 
-int board_getchar(void)
-{
+int board_getchar(void) {
   char c;
-  return ( sys_read(0, &c, 1) > 0 ) ? (int) c : (-1);
+  return (sys_read(0, &c, 1) > 0) ? (int) c : (-1);
 }
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 2b4260083..7358458ce 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -98,7 +98,7 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 
 void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
-  if ( !(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO) ) return;
+  if (!(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
 
   tuh_int_handler(1);
 }
@@ -111,7 +111,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
 
   if (enabled) {
     nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
-  }else {
+  } else {
     nrfx_gpiote_trigger_disable(MAX3241E_INTR_PIN);
   }
 }
@@ -121,7 +121,7 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
 }
 
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len) {
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
   (void) rhport;
 
   nrfx_spim_xfer_desc_t xfer = {
@@ -157,21 +157,21 @@ void board_init(void) {
   nrf_gpio_cfg_input(BUTTON_PIN, NRF_GPIO_PIN_PULLUP);
 
   // 1ms tick timer
-  SysTick_Config(SystemCoreClock/1000);
+  SysTick_Config(SystemCoreClock / 1000);
 
   // UART
   nrfx_uarte_config_t uart_cfg = {
-    .pseltxd   = UART_TX_PIN,
-    .pselrxd   = UART_RX_PIN,
-    .pselcts   = NRF_UARTE_PSEL_DISCONNECTED,
-    .pselrts   = NRF_UARTE_PSEL_DISCONNECTED,
-    .p_context = NULL,
-    .baudrate  = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
-    .interrupt_priority = 7,
-    .hal_cfg = {
-      .hwfc      = NRF_UARTE_HWFC_DISABLED,
-      .parity    = NRF_UARTE_PARITY_EXCLUDED,
-    }
+      .pseltxd   = UART_TX_PIN,
+      .pselrxd   = UART_RX_PIN,
+      .pselcts   = NRF_UARTE_PSEL_DISCONNECTED,
+      .pselrts   = NRF_UARTE_PSEL_DISCONNECTED,
+      .p_context = NULL,
+      .baudrate  = NRF_UARTE_BAUDRATE_115200, // CFG_BOARD_UART_BAUDRATE
+      .interrupt_priority = 7,
+      .hal_cfg = {
+          .hwfc      = NRF_UARTE_HWFC_DISABLED,
+          .parity    = NRF_UARTE_PARITY_EXCLUDED,
+      }
   };
 
   nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler);
@@ -211,11 +211,11 @@ void board_init(void) {
 
     // USB power may already be ready at this time -> no event generated
     // We need to invoke the handler based on the status initially
-    #ifdef NRF5340_XXAA
+#ifdef NRF5340_XXAA
     usb_reg = NRF_USBREGULATOR->USBREGSTATUS;
-    #else
+#else
     usb_reg = NRF_POWER->USBREGSTATUS;
-    #endif
+#endif
   }
 
   if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED);
@@ -308,8 +308,7 @@ uint32_t board_millis(void) {
 
 #ifdef SOFTDEVICE_PRESENT
 // process SOC event from SD
-uint32_t proc_soc(void)
-{
+uint32_t proc_soc(void) {
   uint32_t soc_evt;
   uint32_t err = sd_evt_get(&soc_evt);
 
@@ -326,18 +325,14 @@ uint32_t proc_soc(void)
   return err;
 }
 
-uint32_t proc_ble(void)
-{
+uint32_t proc_ble(void) {
   // do nothing with ble
   return NRF_ERROR_NOT_FOUND;
 }
 
-void SD_EVT_IRQHandler(void)
-{
+void SD_EVT_IRQHandler(void) {
   // process BLE and SOC until there is no more events
-  while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) )
-  {
-
+  while( (NRF_ERROR_NOT_FOUND != proc_ble()) || (NRF_ERROR_NOT_FOUND != proc_soc()) ) {
   }
 }
 
diff --git a/src/host/usbh.c b/src/host/usbh.c
index 12a7f5839..bacb3a719 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -852,7 +852,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
     ep_state->busy    = 0;
     ep_state->claimed = 0;
     TU_LOG1("Failed\r\n");
-    TU_BREAKPOINT();
+//    TU_BREAKPOINT();
     return false;
   }
 }
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index d644390da..56d3aea45 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -405,45 +405,46 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   return false;
 }
 
-tusb_speed_t handle_connect_irq(uint8_t rhport) {
+static void handle_connect_irq(uint8_t rhport) {
   uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
   uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
 
-  tusb_speed_t speed;
   uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
+  TU_LOG2_HEX(jk);
 
   switch(jk) {
-    case 0x00:
-      // SEO is disconnected
-      speed = TUSB_SPEED_INVALID;
-      break;
-
-    case (HRSL_JSTATUS | HRSL_KSTATUS):
-      // SE1 is illegal
-      speed = TUSB_SPEED_INVALID;
+    case 0x00:                          // SEO is disconnected
+    case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal
+      mode_write(rhport, new_mode, true);
+      hcd_event_device_remove(rhport, true);
       break;
 
     default: {
-      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
-      uint8_t const mode = reg_read(rhport, MODE_ADDR, true);
-      uint8_t const ls_bit = mode & MODE_LOWSPEED;
-
-      if ( (ls_bit && (jk == HRSL_JSTATUS)) || (!ls_bit && (jk == HRSL_KSTATUS)) ) {
-        speed = TUSB_SPEED_LOW;
-        new_mode |= MODE_LOWSPEED;
-      } else {
-        speed =  TUSB_SPEED_FULL;
+      // Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset
+      if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) {
+        break;
       }
 
-      new_mode |= MODE_SOFKAENAB; // enable SOF since there is new device
+      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
+      // However, since we are always in full speed mode, we can just check J-state
+      if (jk == HRSL_KSTATUS) {
+        new_mode |= MODE_LOWSPEED;
+        TU_LOG3("Low speed\n");
+      }else {
+        TU_LOG3("Full speed\n");
+      }
+      new_mode |= MODE_SOFKAENAB;
+      mode_write(rhport, new_mode, true);
+
+      // FIXME multiple MAX3421 rootdevice address is not 1
+      uint8_t const daddr = 1;
+      free_ep(daddr);
+
+      hcd_event_device_attach(rhport, true);
 
       break;
     }
   }
-
-  mode_write(rhport, new_mode, true);
-  TU_LOG2_INT(speed);
-  return speed;
 }
 
 // Initialize controller to host mode
@@ -500,8 +501,9 @@ bool hcd_init(uint8_t rhport) {
 // Enable USB interrupt
 // Not actually enable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_enable (uint8_t rhport) {
+//  tuh_max3421e_int_api(rhport, true);
+
   (void) rhport;
-  // tuh_max3421e_int_api(rhport, true);
   if (_hcd_data.intr_disable_count) {
     _hcd_data.intr_disable_count--;
   }
@@ -510,8 +512,8 @@ void hcd_int_enable (uint8_t rhport) {
 // Disable USB interrupt
 // Not actually disable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_disable(uint8_t rhport) {
-  (void) rhport;
   //tuh_max3421e_int_api(rhport, false);
+  (void) rhport;
   _hcd_data.intr_disable_count++;
 }
 
@@ -534,20 +536,12 @@ bool hcd_port_connect_status(uint8_t rhport) {
 // Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
 // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
 void hcd_port_reset(uint8_t rhport) {
-  // Bus reset will also trigger CONDET IRQ, disable it
-  uint8_t const hien = DEFAULT_HIEN & ~HIRQ_CONDET_IRQ;
-  hien_write(rhport, hien, false);
-
   reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, false);
 }
 
 // Complete bus reset sequence, may be required by some controllers
 void hcd_port_reset_end(uint8_t rhport) {
   reg_write(rhport, HCTL_ADDR, 0, false);
-
-  // Bus reset will also trigger CONDET IRQ, clear and re-enable it after reset
-  hirq_write(rhport, HIRQ_CONDET_IRQ, false);
-  hien_write(rhport, DEFAULT_HIEN, false);
 }
 
 // Get port link speed
@@ -660,7 +654,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buf
   uint8_t const ep_dir = tu_edpt_dir(ep_addr);
 
   max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
-  TU_ASSERT(ep);
+  TU_VERIFY(ep);
 
   // control transfer can switch direction
   ep->ep_dir = ep_dir;
@@ -767,8 +761,6 @@ static void handle_xfer_done(uint8_t rhport) {
   TU_ASSERT(ep, );
 
   xfer_result_t xfer_result;
-
-//  TU_LOG3("HRSL: %02X\r\n", hrsl);
   switch(hresult) {
     case HRSL_SUCCESS:
       xfer_result = XFER_RESULT_SUCCESS;
@@ -803,6 +795,7 @@ static void handle_xfer_done(uint8_t rhport) {
       return;
 
     default:
+      TU_LOG3("HRSL: %02X\r\n", hrsl);
       xfer_result = XFER_RESULT_FAILED;
       break;
   }
@@ -875,30 +868,30 @@ void hcd_int_handler(uint8_t rhport) {
   if (!hirq) return;
 //  print_hirq(hirq);
 
+//  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true);
+
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
   }
 
+  #if 1
   // interrupt is disabled, only ack FRAME IRQ and skip the rest
   if (_hcd_data.intr_disable_count) {
     if (hirq & HIRQ_FRAME_IRQ) {
       hirq_write(rhport, HIRQ_FRAME_IRQ, true);
     }
+
+    if ((hirq & HIRQ_CONDET_IRQ) && !(_hcd_data.mode & MODE_SOFKAENAB)) {
+      // connection when interrupt is disabled
+      TU_LOG3_INT(_hcd_data.intr_disable_count);
+      return;
+    }
     return;
   }
+  #endif
 
   if (hirq & HIRQ_CONDET_IRQ) {
-    tusb_speed_t speed = handle_connect_irq(rhport);
-
-    if (speed == TUSB_SPEED_INVALID) {
-      hcd_event_device_remove(rhport, true);
-    }else {
-      // FIXME multiple MAX3421 rootdevice address is not 1
-      uint8_t const daddr = 1;
-      free_ep(daddr);
-
-      hcd_event_device_attach(rhport, true);
-    }
+    handle_connect_irq(rhport);
   }
 
   // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or

From ed0a233d4830baa8a767fcc20dcbfedbb09b7b41 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 31 Aug 2023 21:28:27 +0700
Subject: [PATCH 2028/2085] vastly improve attach/detach device, still have
 issue where thing is still hanged occasionally.

---
 src/portable/analog/max3421/hcd_max3421.c | 126 ++++++++++++----------
 1 file changed, 70 insertions(+), 56 deletions(-)

diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 56d3aea45..c61389cb9 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -215,6 +215,9 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
 void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
 
+static void handle_connect_irq(uint8_t rhport, bool in_isr);
+static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
+
 //--------------------------------------------------------------------+
 // SPI Helper
 //--------------------------------------------------------------------+
@@ -238,6 +241,14 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
   if (!in_isr) {
     tuh_max3421e_int_api(rhport, true);
     (void) osal_mutex_unlock(_hcd_data.spi_mutex);
+
+    // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt).
+    // It would be ok if we are operating since SOF will re-trigger interrupt.
+    // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here.
+    if (_hcd_data.hirq & HIRQ_CONDET_IRQ) {
+      handle_connect_irq(rhport, false);
+      hirq_write(rhport, HIRQ_CONDET_IRQ, false);
+    }
   }
 }
 
@@ -405,48 +416,6 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
   return false;
 }
 
-static void handle_connect_irq(uint8_t rhport) {
-  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
-  uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
-
-  uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
-  TU_LOG2_HEX(jk);
-
-  switch(jk) {
-    case 0x00:                          // SEO is disconnected
-    case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal
-      mode_write(rhport, new_mode, true);
-      hcd_event_device_remove(rhport, true);
-      break;
-
-    default: {
-      // Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset
-      if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) {
-        break;
-      }
-
-      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
-      // However, since we are always in full speed mode, we can just check J-state
-      if (jk == HRSL_KSTATUS) {
-        new_mode |= MODE_LOWSPEED;
-        TU_LOG3("Low speed\n");
-      }else {
-        TU_LOG3("Full speed\n");
-      }
-      new_mode |= MODE_SOFKAENAB;
-      mode_write(rhport, new_mode, true);
-
-      // FIXME multiple MAX3421 rootdevice address is not 1
-      uint8_t const daddr = 1;
-      free_ep(daddr);
-
-      hcd_event_device_attach(rhport, true);
-
-      break;
-    }
-  }
-}
-
 // Initialize controller to host mode
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
@@ -507,6 +476,14 @@ void hcd_int_enable (uint8_t rhport) {
   if (_hcd_data.intr_disable_count) {
     _hcd_data.intr_disable_count--;
   }
+
+  // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt).
+  // It would be ok if we are operating since SOF will re-trigger interrupt.
+  // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here.
+//  if (_hcd_data.hirq & HIRQ_CONDET_IRQ) {
+//    handle_connect_irq(rhport, false);
+//    hirq_write(rhport, HIRQ_CONDET_IRQ, false);
+//  }
 }
 
 // Disable USB interrupt
@@ -726,6 +703,54 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 // Interrupt Handler
 //--------------------------------------------------------------------+
 
+static void handle_connect_irq(uint8_t rhport, bool in_isr) {
+  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
+  uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
+
+  uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
+  TU_LOG2_HEX(jk);
+
+  switch(jk) {
+    case 0x00:                          // SEO is disconnected
+    case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal
+      mode_write(rhport, new_mode, in_isr);
+
+      // port reset anyway, this will help to stable bus signal for next connection
+      reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, in_isr);
+
+      hcd_event_device_remove(rhport, in_isr);
+
+      reg_write(rhport, HCTL_ADDR, 0, in_isr);
+      break;
+
+    default: {
+      // Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset
+      if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) {
+        break;
+      }
+
+      // Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
+      // However, since we are always in full speed mode, we can just check J-state
+      if (jk == HRSL_KSTATUS) {
+        new_mode |= MODE_LOWSPEED;
+        TU_LOG3("Low speed\n");
+      }else {
+        TU_LOG3("Full speed\n");
+      }
+      new_mode |= MODE_SOFKAENAB;
+      mode_write(rhport, new_mode, in_isr);
+
+      // FIXME multiple MAX3421 rootdevice address is not 1
+      uint8_t const daddr = 1;
+      free_ep(daddr);
+
+      hcd_event_device_attach(rhport, in_isr);
+
+      break;
+    }
+  }
+}
+
 static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl) {
   uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
 
@@ -758,7 +783,7 @@ static void handle_xfer_done(uint8_t rhport) {
   uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
 
   max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir);
-  TU_ASSERT(ep, );
+  TU_VERIFY(ep, );
 
   xfer_result_t xfer_result;
   switch(hresult) {
@@ -857,7 +882,6 @@ void print_hirq(uint8_t hirq) {
 
   TU_LOG3("\r\n");
 }
-
 #else
   #define print_hirq(hirq)
 #endif
@@ -868,30 +892,20 @@ void hcd_int_handler(uint8_t rhport) {
   if (!hirq) return;
 //  print_hirq(hirq);
 
-//  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true);
-
   if (hirq & HIRQ_FRAME_IRQ) {
     _hcd_data.frame_count++;
   }
 
-  #if 1
-  // interrupt is disabled, only ack FRAME IRQ and skip the rest
+  // interrupt is disabled by usbh task: only ack FRAME IRQ and skip the rest
   if (_hcd_data.intr_disable_count) {
     if (hirq & HIRQ_FRAME_IRQ) {
       hirq_write(rhport, HIRQ_FRAME_IRQ, true);
     }
-
-    if ((hirq & HIRQ_CONDET_IRQ) && !(_hcd_data.mode & MODE_SOFKAENAB)) {
-      // connection when interrupt is disabled
-      TU_LOG3_INT(_hcd_data.intr_disable_count);
-      return;
-    }
     return;
   }
-  #endif
 
   if (hirq & HIRQ_CONDET_IRQ) {
-    handle_connect_irq(rhport);
+    handle_connect_irq(rhport, true);
   }
 
   // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or

From 4fb15f6bb7afb105635db8370917af977d8a918a Mon Sep 17 00:00:00 2001
From: Gabriel Chouinard <gabriel.chouinard@sparkmicro.com>
Date: Tue, 7 Feb 2023 19:31:35 -0500
Subject: [PATCH 2029/2085] Add stm32u575-nucleo support

---
 .../stm32u575nucleo/STM32U575ZITXQ_FLASH.ld   | 167 ++++++++++++++++++
 hw/bsp/stm32u5/boards/stm32u575nucleo/board.h | 111 ++++++++++++
 .../stm32u5/boards/stm32u575nucleo/board.mk   |  10 ++
 3 files changed, 288 insertions(+)
 create mode 100644 hw/bsp/stm32u5/boards/stm32u575nucleo/STM32U575ZITXQ_FLASH.ld
 create mode 100644 hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
 create mode 100644 hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk

diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/STM32U575ZITXQ_FLASH.ld b/hw/bsp/stm32u5/boards/stm32u575nucleo/STM32U575ZITXQ_FLASH.ld
new file mode 100644
index 000000000..03c022bc2
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/STM32U575ZITXQ_FLASH.ld
@@ -0,0 +1,167 @@
+/*
+******************************************************************************
+**
+**  File        : LinkerScript.ld
+**
+**  Author      : STM32CubeIDE
+**
+**  Abstract    : Linker script for STM32U575xI Device from STM32U5 series
+**                      2048Kbytes FLASH
+**                      784Kbytes RAM
+**
+**                Set heap size, stack size and stack location according
+**                to application requirements.
+**
+**                Set memory bank area and size if external memory is used.
+**
+**  Target      : STMicroelectronics STM32
+**
+**  Distribution: The file is distributed as is without any warranty
+**                of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
+_Min_Stack_Size = 0x400 ;	/* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 768K
+  SRAM4	(xrw)	: ORIGIN = 0x28000000,	LENGTH = 16K
+  FLASH	(rx)	: ORIGIN = 0x08000000,	LENGTH = 2048K
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "FLASH" Rom type memory */
+  .isr_vector :
+  {
+    KEEP(*(.isr_vector)) /* Startup code */
+  } >FLASH
+
+  /* The program code and other data into "FLASH" Rom type memory */
+  .text :
+  {
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data into "FLASH" Rom type memory */
+  .rodata :
+  {
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+  } >FLASH
+
+  .ARM.extab :
+  {
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+  } >FLASH
+
+  .ARM :
+  {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "RAM" Ram type memory */
+  .data :
+  {
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+    *(.RamFunc)        /* .RamFunc sections */
+    *(.RamFunc*)       /* .RamFunc* sections */
+
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  /* Uninitialized data section into "RAM" Ram type memory */
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
new file mode 100644
index 000000000..75e8a0d6a
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
@@ -0,0 +1,111 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+// LED GREEN
+#define LED_PORT GPIOC
+#define LED_PIN GPIO_PIN_7
+#define LED_STATE_ON 1
+
+// BUTTON
+#define BUTTON_PORT GPIOA
+#define BUTTON_PIN GPIO_PIN_0
+#define BUTTON_STATE_ACTIVE 1
+
+// UART Enable for STLink VCOM
+#define UART_DEV LPUART1
+#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE
+#define UART_GPIO_PORT GPIOG
+#define UART_GPIO_AF GPIO_AF8_LPUART1
+#define UART_TX_PIN GPIO_PIN_7
+#define UART_RX_PIN GPIO_PIN_8
+
+//--------------------------------------------------------------------+
+// RCC Clock
+//--------------------------------------------------------------------+
+
+static inline void board_clock_init(void)
+{
+
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /* Enable Power Clock*/
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /** Configure the main internal regulator output voltage
+   */
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
+  RCC_OscInitStruct.PLL.PLLM = 1;
+  RCC_OscInitStruct.PLL.PLLN = 10;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 1;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
+  PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
+
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+  /** Initializes the CPU, AHB and APB buses clocks
+   */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
new file mode 100644
index 000000000..0c7948860
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
@@ -0,0 +1,10 @@
+CFLAGS += \
+  -DSTM32U575xx \
+
+# All source paths should be relative to the top level.
+LD_FILE = $(BOARD_PATH)/STM32U575ZITXQ_FLASH.ld
+
+SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
+
+# For flash-jlink target
+JLINK_DEVICE = stm32u575

From c4566c4d2ba5219e6c2ea821912b888d0270ff07 Mon Sep 17 00:00:00 2001
From: Gabriel Chouinard <gabriel.chouinard@sparkmicro.com>
Date: Tue, 5 Sep 2023 21:28:13 -0400
Subject: [PATCH 2030/2085] Enable instruction cache for stm32u5 boards

---
 hw/bsp/stm32u5/boards/stm32u575nucleo/board.h | 2 +-
 hw/bsp/stm32u5/family.c                       | 3 +++
 hw/bsp/stm32u5/family.mk                      | 1 +
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
index 75e8a0d6a..54a6d4cd7 100644
--- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h
@@ -61,7 +61,7 @@ static inline void board_clock_init(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /* Enable Power Clock*/
+  /* Enable Power Clock */
   __HAL_RCC_PWR_CLK_ENABLE();
 
   /** Configure the main internal regulator output voltage
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index a30d886aa..c1fe3f412 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -60,6 +60,9 @@ void board_init(void)
 
   UART_CLK_EN();
 
+  /* Enable Instruction cache */
+  HAL_ICACHE_Enable();
+
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
   SysTick_Config(SystemCoreClock / 1000);
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index 9174fe96a..dace63a51 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -20,6 +20,7 @@ SRC_C += \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_icache.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \

From 1b9108ea0dc237835e801d26cc7eef052acad987 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 6 Sep 2023 17:11:35 +0700
Subject: [PATCH 2031/2085] minor debug clean up

---
 src/common/tusb_common.h |  6 ++----
 src/common/tusb_debug.h  | 37 ++++++++++++++-----------------------
 src/device/usbd.c        |  2 +-
 src/device/usbd_pvt.h    | 15 ++++++---------
 src/host/usbh.c          |  6 ++----
 5 files changed, 25 insertions(+), 41 deletions(-)

diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index c303c6eaf..6fffed11c 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -122,13 +122,11 @@ TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, c
 
 
 //------------- Bytes -------------//
-TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0) {
   return ( ((uint32_t) b3) << 24) | ( ((uint32_t) b2) << 16) | ( ((uint32_t) b1) << 8) | b0;
 }
 
-TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low)
-{
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low) {
   return (uint16_t) ((((uint16_t) high) << 8) | low);
 }
 
diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h
index 36507041f..99176c02a 100644
--- a/src/common/tusb_debug.h
+++ b/src/common/tusb_debug.h
@@ -58,16 +58,14 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
   #define tu_printf    printf
 #endif
 
-static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
-{
+static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
   for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
 }
 
 // Log with Level
 #define TU_LOG(n, ...)        TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
 #define TU_LOG_MEM(n, ...)    TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
-#define TU_LOG_ARR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _ARR)(__VA_ARGS__)
-#define TU_LOG_PTR(n, ...)    TU_XSTRCAT3(TU_LOG, n, _PTR)(__VA_ARGS__)
+#define TU_LOG_BUF(n, ...)    TU_XSTRCAT3(TU_LOG, n, _BUF)(__VA_ARGS__)
 #define TU_LOG_INT(n, ...)    TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
 #define TU_LOG_HEX(n, ...)    TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
 #define TU_LOG_LOCATION()     tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
@@ -76,8 +74,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 // Log Level 1: Error
 #define TU_LOG1               tu_printf
 #define TU_LOG1_MEM           tu_print_mem
-#define TU_LOG1_ARR(_x, _n)   tu_print_arr((uint8_t const*)(_x), _n)
-#define TU_LOG1_PTR(_x)       tu_print_arr((uint8_t const*)(_x), sizeof(*(_x)))
+#define TU_LOG1_BUF(_x, _n)   tu_print_buf((uint8_t const*)(_x), _n)
 #define TU_LOG1_INT(_x)       tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
 #define TU_LOG1_HEX(_x)       tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
 
@@ -85,8 +82,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 #if CFG_TUSB_DEBUG >= 2
   #define TU_LOG2             TU_LOG1
   #define TU_LOG2_MEM         TU_LOG1_MEM
-  #define TU_LOG2_ARR         TU_LOG1_ARR
-  #define TU_LOG2_PTR         TU_LOG1_PTR
+  #define TU_LOG2_BUF         TU_LOG1_BUF
   #define TU_LOG2_INT         TU_LOG1_INT
   #define TU_LOG2_HEX         TU_LOG1_HEX
 #endif
@@ -95,30 +91,25 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
 #if CFG_TUSB_DEBUG >= 3
   #define TU_LOG3             TU_LOG1
   #define TU_LOG3_MEM         TU_LOG1_MEM
-  #define TU_LOG3_ARR         TU_LOG1_ARR
-  #define TU_LOG3_PTR         TU_LOG1_PTR
+  #define TU_LOG3_BUF         TU_LOG1_BUF
   #define TU_LOG3_INT         TU_LOG1_INT
   #define TU_LOG3_HEX         TU_LOG1_HEX
 #endif
 
-typedef struct
-{
+typedef struct {
   uint32_t key;
   const char* data;
 } tu_lookup_entry_t;
 
-typedef struct
-{
+typedef struct {
   uint16_t count;
   tu_lookup_entry_t const* items;
 } tu_lookup_table_t;
 
-static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
-{
+static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) {
   tu_static char not_found[11];
 
-  for(uint16_t i=0; i<p_table->count; i++)
-  {
+  for(uint16_t i=0; i<p_table->count; i++) {
     if (p_table->items[i].key == key) return p_table->items[i].data;
   }
 
@@ -133,7 +124,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG
   #define TU_LOG(n, ...)
   #define TU_LOG_MEM(n, ...)
-  #define TU_LOG_PTR(n, ...)
+  #define TU_LOG_BUF(n, ...)
   #define TU_LOG_INT(n, ...)
   #define TU_LOG_HEX(n, ...)
   #define TU_LOG_LOCATION()
@@ -144,14 +135,14 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 
 #define TU_LOG0(...)
 #define TU_LOG0_MEM(...)
-#define TU_LOG0_PTR(...)
+#define TU_LOG0_BUF(...)
 #define TU_LOG0_INT(...)
 #define TU_LOG0_HEX(...)
 
 #ifndef TU_LOG1
   #define TU_LOG1(...)
   #define TU_LOG1_MEM(...)
-  #define TU_LOG1_PTR(...)
+  #define TU_LOG1_BUF(...)
   #define TU_LOG1_INT(...)
   #define TU_LOG1_HEX(...)
 #endif
@@ -159,7 +150,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG2
   #define TU_LOG2(...)
   #define TU_LOG2_MEM(...)
-  #define TU_LOG2_PTR(...)
+  #define TU_LOG2_BUF(...)
   #define TU_LOG2_INT(...)
   #define TU_LOG2_HEX(...)
 #endif
@@ -167,7 +158,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
 #ifndef TU_LOG3
   #define TU_LOG3(...)
   #define TU_LOG3_MEM(...)
-  #define TU_LOG3_PTR(...)
+  #define TU_LOG3_BUF(...)
   #define TU_LOG3_INT(...)
   #define TU_LOG3_HEX(...)
 #endif
diff --git a/src/device/usbd.c b/src/device/usbd.c
index f0d9fba52..50941c46f 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -506,7 +506,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
       break;
 
       case DCD_EVENT_SETUP_RECEIVED:
-        TU_LOG_PTR(CFG_TUD_LOG_LEVEL, &event.setup_received);
+        TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
         TU_LOG_USBD("\r\n");
 
         // Mark as connected after receiving 1st setup packet.
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 16585167f..153be7cee 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -23,8 +23,8 @@
  *
  * This file is part of the TinyUSB stack.
  */
-#ifndef USBD_PVT_H_
-#define USBD_PVT_H_
+#ifndef _TUSB_USBD_PVT_H_
+#define _TUSB_USBD_PVT_H_
 
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
@@ -44,8 +44,7 @@
 // Class Driver API
 //--------------------------------------------------------------------+
 
-typedef struct
-{
+typedef struct {
   #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
   char const* name;
   #endif
@@ -111,8 +110,7 @@ bool usbd_edpt_iso_activate(uint8_t rhport,  tusb_desc_endpoint_t const * p_endp
 
 // Check if endpoint is ready (not busy and not stalled)
 TU_ATTR_ALWAYS_INLINE static inline
-bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr)
-{
+bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) {
   return !usbd_edpt_busy(rhport, ep_addr) && !usbd_edpt_stalled(rhport, ep_addr);
 }
 
@@ -124,11 +122,10 @@ void usbd_sof_enable(uint8_t rhport, bool en);
  *------------------------------------------------------------------*/
 
 bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in);
-void usbd_defer_func( osal_task_func_t func, void* param, bool in_isr );
-
+void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr);
 
 #ifdef __cplusplus
  }
 #endif
 
-#endif /* USBD_PVT_H_ */
+#endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index bacb3a719..e60e680c2 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -583,7 +583,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
   TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr,
               (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
                   tu_str_std_request[xfer->setup->bRequest] : "Class Request");
-  TU_LOG_PTR(CFG_TUH_LOG_LEVEL, xfer->setup);
+  TU_LOG_BUF(CFG_TUH_LOG_LEVEL, xfer->setup, 8);
   TU_LOG_USBH("\r\n");
 
   if (xfer->complete_cb) {
@@ -660,10 +660,8 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
 
   if (XFER_RESULT_SUCCESS != result) {
     TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
-    #if CFG_TUSB_DEBUG == 1
-    TU_LOG1_PTR(request);
+    TU_LOG1_BUF(request, 8);
     TU_LOG1("\r\n");
-    #endif
 
     // terminate transfer if any stage failed
     _xfer_complete(dev_addr, result);

From 21ab40bab2e2fee28fa595f648a17944696c3d65 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 7 Sep 2023 12:38:18 +0700
Subject: [PATCH 2032/2085] - wrap up hcd max3421, work well with nrf52840 -
 also add usbh_defer_func()

---
 hw/bsp/nrf/family.c                       |  7 +++--
 src/host/usbh.c                           | 26 +++++++++-------
 src/host/usbh_pvt.h                       | 10 +++----
 src/portable/analog/max3421/hcd_max3421.c | 36 ++---------------------
 4 files changed, 27 insertions(+), 52 deletions(-)

diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 7358458ce..39ce179e8 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -109,10 +109,12 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
 void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
+  // use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt
+  // when disabled
   if (enabled) {
-    nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
+    NVIC_EnableIRQ(GPIOTE_IRQn);
   } else {
-    nrfx_gpiote_trigger_disable(MAX3241E_INTR_PIN);
+    NVIC_DisableIRQ(GPIOTE_IRQn);
   }
 }
 
@@ -266,6 +268,7 @@ void board_init(void) {
   in_config.pull = NRF_GPIO_PIN_PULLUP;
 
   nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler);
+  nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
 #endif
 
 }
diff --git a/src/host/usbh.c b/src/host/usbh.c
index e60e680c2..e332f35cc 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -753,29 +753,33 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) {
 // USBH API For Class Driver
 //--------------------------------------------------------------------+
 
-uint8_t usbh_get_rhport(uint8_t dev_addr)
-{
-  usbh_device_t* dev = get_device(dev_addr);
+uint8_t usbh_get_rhport(uint8_t dev_addr) {
+  usbh_device_t *dev = get_device(dev_addr);
   return dev ? dev->rhport : _dev0.rhport;
 }
 
-uint8_t* usbh_get_enum_buf(void)
-{
+uint8_t *usbh_get_enum_buf(void) {
   return _usbh_ctrl_buf;
 }
 
-void usbh_int_set(bool enabled)
-{
+void usbh_int_set(bool enabled) {
   // TODO all host controller if multiple are used since they shared the same event queue
-  if (enabled)
-  {
+  if (enabled) {
     hcd_int_enable(_usbh_controller);
-  }else
-  {
+  } else {
     hcd_int_disable(_usbh_controller);
   }
 }
 
+void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) {
+  hcd_event_t event = { 0 };
+  event.event_id = USBH_EVENT_FUNC_CALL;
+  event.func_call.func = func;
+  event.func_call.param = param;
+
+  osal_queue_send(_usbh_q, &event, in_isr);
+}
+
 //--------------------------------------------------------------------+
 // Endpoint API
 //--------------------------------------------------------------------+
diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h
index 0b58a91bc..2b61a77db 100644
--- a/src/host/usbh_pvt.h
+++ b/src/host/usbh_pvt.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_USBH_CLASSDRIVER_H_
-#define _TUSB_USBH_CLASSDRIVER_H_
+#ifndef _TUSB_USBH_PVT_H_
+#define _TUSB_USBH_PVT_H_
 
 #include "osal/osal.h"
 #include "common/tusb_fifo.h"
@@ -76,6 +76,8 @@ uint8_t* usbh_get_enum_buf(void);
 
 void usbh_int_set(bool enabled);
 
+void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr);
+
 //--------------------------------------------------------------------+
 // USBH Endpoint API
 //--------------------------------------------------------------------+
@@ -85,12 +87,10 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data);
 
 TU_ATTR_ALWAYS_INLINE
-static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
-{
+static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) {
   return usbh_edpt_xfer_with_callback(dev_addr, ep_addr, buffer, total_bytes, NULL, 0);
 }
 
-
 // Claim an endpoint before submitting a transfer.
 // If caller does not make any transfer, it must release endpoint for others.
 bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index c61389cb9..95cf5516e 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -194,7 +194,6 @@ typedef struct {
   uint8_t hxfr;
 
   atomic_flag busy; // busy transferring
-  volatile uint8_t intr_disable_count;
   volatile uint16_t frame_count;
 
   max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
@@ -241,14 +240,6 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
   if (!in_isr) {
     tuh_max3421e_int_api(rhport, true);
     (void) osal_mutex_unlock(_hcd_data.spi_mutex);
-
-    // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt).
-    // It would be ok if we are operating since SOF will re-trigger interrupt.
-    // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here.
-    if (_hcd_data.hirq & HIRQ_CONDET_IRQ) {
-      handle_connect_irq(rhport, false);
-      hirq_write(rhport, HIRQ_CONDET_IRQ, false);
-    }
   }
 }
 
@@ -470,28 +461,13 @@ bool hcd_init(uint8_t rhport) {
 // Enable USB interrupt
 // Not actually enable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_enable (uint8_t rhport) {
-//  tuh_max3421e_int_api(rhport, true);
-
-  (void) rhport;
-  if (_hcd_data.intr_disable_count) {
-    _hcd_data.intr_disable_count--;
-  }
-
-  // when re-enable interrupt, we may miss INTR edge (usually via GPIO detection interrupt).
-  // It would be ok if we are operating since SOF will re-trigger interrupt.
-  // However, for CONDET_IRQ i.e host not operating therefore we need to manually handle it here.
-//  if (_hcd_data.hirq & HIRQ_CONDET_IRQ) {
-//    handle_connect_irq(rhport, false);
-//    hirq_write(rhport, HIRQ_CONDET_IRQ, false);
-//  }
+  tuh_max3421e_int_api(rhport, true);
 }
 
 // Disable USB interrupt
 // Not actually disable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_disable(uint8_t rhport) {
-  //tuh_max3421e_int_api(rhport, false);
-  (void) rhport;
-  _hcd_data.intr_disable_count++;
+  tuh_max3421e_int_api(rhport, false);
 }
 
 // Get frame number (1ms)
@@ -896,14 +872,6 @@ void hcd_int_handler(uint8_t rhport) {
     _hcd_data.frame_count++;
   }
 
-  // interrupt is disabled by usbh task: only ack FRAME IRQ and skip the rest
-  if (_hcd_data.intr_disable_count) {
-    if (hirq & HIRQ_FRAME_IRQ) {
-      hirq_write(rhport, HIRQ_FRAME_IRQ, true);
-    }
-    return;
-  }
-
   if (hirq & HIRQ_CONDET_IRQ) {
     handle_connect_irq(rhport, true);
   }

From bb5d43e9c5c909a1becc1224c768d3aa1a09b051 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 7 Sep 2023 15:31:43 +0700
Subject: [PATCH 2033/2085] add samd51 to cmake

---
 .github/workflows/build_arm.yml               |   2 +-
 .github/workflows/cmake_arm.yml               |   1 +
 .idea/cmake.xml                               |   5 +-
 hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h | 165 ++++++++++++++++++
 .../boards/feather_m4_express/board.cmake     |   8 +
 hw/bsp/samd51/boards/itsybitsy_m4/board.cmake |   8 +
 .../boards/metro_m4_express/board.cmake       |   8 +
 hw/bsp/samd51/boards/pybadge/board.cmake      |   8 +
 hw/bsp/samd51/boards/pyportal/board.cmake     |   8 +
 hw/bsp/samd51/family.c                        |  11 ++
 hw/bsp/samd51/family.cmake                    | 104 +++++++++++
 11 files changed, 325 insertions(+), 3 deletions(-)
 create mode 100644 hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/samd51/boards/feather_m4_express/board.cmake
 create mode 100644 hw/bsp/samd51/boards/itsybitsy_m4/board.cmake
 create mode 100644 hw/bsp/samd51/boards/metro_m4_express/board.cmake
 create mode 100644 hw/bsp/samd51/boards/pybadge/board.cmake
 create mode 100644 hw/bsp/samd51/boards/pyportal/board.cmake
 create mode 100644 hw/bsp/samd51/family.cmake

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 2621e7372..377fc44d9 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -40,7 +40,7 @@ jobs:
         - 'mm32 msp432e4'
         - 'nrf'
         - 'samd11 samd21'
-        - 'samd51 same5x'
+        - 'same5x'
         - 'saml2x'
         - 'stm32f2 stm32f3'
         - 'stm32l0 stm32u5 stm32wb'
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 8eeae928c..6f7d024bd 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -40,6 +40,7 @@ jobs:
           - 'mcx'
           - 'ra'
           - 'rp2040'
+          - 'samd51'
           - 'stm32f0'
           - 'stm32f1'
           - 'stm32f4'
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 8ee7f09a0..a060f18eb 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -30,8 +30,8 @@
       <configuration PROFILE_NAME="mcb1800" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcb1800 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="ea4088 quickstart" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4088_quickstart -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="ea4357" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ea4357 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
-      <configuration PROFILE_NAME="lpc54628" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="lpc55s69" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69 -DLOG=4 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpc54628" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
@@ -52,6 +52,7 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
+      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..e3ee529cf
--- /dev/null
+++ b/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "sam.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.cmake b/hw/bsp/samd51/boards/feather_m4_express/board.cmake
new file mode 100644
index 000000000..d83211d9e
--- /dev/null
+++ b/hw/bsp/samd51/boards/feather_m4_express/board.cmake
@@ -0,0 +1,8 @@
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD51J19A__
+    )
+endfunction()
diff --git a/hw/bsp/samd51/boards/itsybitsy_m4/board.cmake b/hw/bsp/samd51/boards/itsybitsy_m4/board.cmake
new file mode 100644
index 000000000..d83211d9e
--- /dev/null
+++ b/hw/bsp/samd51/boards/itsybitsy_m4/board.cmake
@@ -0,0 +1,8 @@
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD51J19A__
+    )
+endfunction()
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.cmake b/hw/bsp/samd51/boards/metro_m4_express/board.cmake
new file mode 100644
index 000000000..d83211d9e
--- /dev/null
+++ b/hw/bsp/samd51/boards/metro_m4_express/board.cmake
@@ -0,0 +1,8 @@
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD51J19A__
+    )
+endfunction()
diff --git a/hw/bsp/samd51/boards/pybadge/board.cmake b/hw/bsp/samd51/boards/pybadge/board.cmake
new file mode 100644
index 000000000..d83211d9e
--- /dev/null
+++ b/hw/bsp/samd51/boards/pybadge/board.cmake
@@ -0,0 +1,8 @@
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD51J19A__
+    )
+endfunction()
diff --git a/hw/bsp/samd51/boards/pyportal/board.cmake b/hw/bsp/samd51/boards/pyportal/board.cmake
new file mode 100644
index 000000000..d83211d9e
--- /dev/null
+++ b/hw/bsp/samd51/boards/pyportal/board.cmake
@@ -0,0 +1,8 @@
+set(JLINK_DEVICE ATSAMD51J19)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD51J19A__
+    )
+endfunction()
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 7ec208b30..2df9cbafb 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -28,11 +28,22 @@
 #include "bsp/board_api.h"
 #include "board.h"
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#endif
+
 #include "hal/include/hal_gpio.h"
 #include "hal/include/hal_init.h"
 #include "hpl/gclk/hpl_gclk_base.h"
 #include "hpl_mclk_config.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/samd51/family.cmake b/hw/bsp/samd51/family.cmake
new file mode 100644
index 000000000..fa9586066
--- /dev/null
+++ b/hw/bsp/samd51/family.cmake
@@ -0,0 +1,104 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/microchip/samd51)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS SAMD51 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${SDK_DIR}/gcc/system_samd51.c
+      ${SDK_DIR}/hpl/gclk/hpl_gclk.c
+      ${SDK_DIR}/hpl/mclk/hpl_mclk.c
+      ${SDK_DIR}/hpl/osc32kctrl/hpl_osc32kctrl.c
+      ${SDK_DIR}/hpl/oscctrl/hpl_oscctrl.c
+      ${SDK_DIR}/hal/src/hal_atomic.c
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${SDK_DIR}/
+      ${SDK_DIR}/config
+      ${SDK_DIR}/include
+      ${SDK_DIR}/hal/include
+      ${SDK_DIR}/hal/utils/include
+      ${SDK_DIR}/hpl/port
+      ${SDK_DIR}/hri
+      ${SDK_DIR}/CMSIS/Include
+      )
+
+    update_board(${BOARD_TARGET})
+
+    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+      message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
+    endif ()
+
+    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+      set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_samd51.c)
+    endif ()
+
+    target_sources(${BOARD_TARGET} PRIVATE
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        --specs=nosys.specs --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_SAMD51 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/microchip/samd/dcd_samd.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+endfunction()

From 2dea4ce6a22061df59a8589286f78213b7e99c5e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 7 Sep 2023 16:58:40 +0700
Subject: [PATCH 2034/2085] add cmake support for samd21. update ci cmake

---
 .github/workflows/build_arm.yml               |   4 +-
 .github/workflows/cmake_arm.yml               |   1 +
 .idea/cmake.xml                               |   3 +-
 hw/bsp/samd21/FreeRTOSConfig/FreeRTOSConfig.h | 165 ++++++++++++++++++
 .../samd21/boards/atsamd21_xpro/board.cmake   |   9 +
 .../circuitplayground_express/board.cmake     |   9 +
 .../samd21/boards/curiosity_nano/board.cmake  |  10 ++
 hw/bsp/samd21/boards/cynthion_d21/board.cmake |  12 ++
 .../boards/feather_m0_express/board.cmake     |   9 +
 hw/bsp/samd21/boards/itsybitsy_m0/board.cmake |   9 +
 .../boards/metro_m0_express/board.cmake       |   9 +
 hw/bsp/samd21/boards/qtpy/board.cmake         |   9 +
 .../samd21/boards/seeeduino_xiao/board.cmake  |   9 +
 hw/bsp/samd21/boards/trinket_m0/board.cmake   |   9 +
 hw/bsp/samd21/family.c                        |  10 ++
 hw/bsp/samd21/family.cmake                    | 105 +++++++++++
 16 files changed, 378 insertions(+), 4 deletions(-)
 create mode 100644 hw/bsp/samd21/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/samd21/boards/atsamd21_xpro/board.cmake
 create mode 100644 hw/bsp/samd21/boards/circuitplayground_express/board.cmake
 create mode 100644 hw/bsp/samd21/boards/curiosity_nano/board.cmake
 create mode 100644 hw/bsp/samd21/boards/cynthion_d21/board.cmake
 create mode 100644 hw/bsp/samd21/boards/feather_m0_express/board.cmake
 create mode 100644 hw/bsp/samd21/boards/itsybitsy_m0/board.cmake
 create mode 100644 hw/bsp/samd21/boards/metro_m0_express/board.cmake
 create mode 100644 hw/bsp/samd21/boards/qtpy/board.cmake
 create mode 100644 hw/bsp/samd21/boards/seeeduino_xiao/board.cmake
 create mode 100644 hw/bsp/samd21/boards/trinket_m0/board.cmake
 create mode 100644 hw/bsp/samd21/family.cmake

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 377fc44d9..70385bc1b 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -39,9 +39,7 @@ jobs:
         - 'lpc51 lpc54'
         - 'mm32 msp432e4'
         - 'nrf'
-        - 'samd11 samd21'
-        - 'same5x'
-        - 'saml2x'
+        - 'samd11 same5x saml2x'
         - 'stm32f2 stm32f3'
         - 'stm32l0 stm32u5 stm32wb'
         - 'tm4c123 xmc4000'
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 6f7d024bd..e3a00f9c5 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -40,6 +40,7 @@ jobs:
           - 'mcx'
           - 'ra'
           - 'rp2040'
+          - 'samd21'
           - 'samd51'
           - 'stm32f0'
           - 'stm32f1'
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index a060f18eb..15dd85f93 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -52,7 +52,8 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
-      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="metro_m4_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="metro_m0_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/samd21/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd21/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..02e868741
--- /dev/null
+++ b/hw/bsp/samd21/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "sam.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       2
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.cmake b/hw/bsp/samd21/boards/atsamd21_xpro/board.cmake
new file mode 100644
index 000000000..46a3880ed
--- /dev/null
+++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21J18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/samd21j18a_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21J18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.cmake b/hw/bsp/samd21/boards/circuitplayground_express/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/circuitplayground_express/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.cmake b/hw/bsp/samd21/boards/curiosity_nano/board.cmake
new file mode 100644
index 000000000..ff779c0fd
--- /dev/null
+++ b/hw/bsp/samd21/boards/curiosity_nano/board.cmake
@@ -0,0 +1,10 @@
+set(JLINK_DEVICE atsamd21g17a)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/samd21g17a_flash.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G17A__
+    CFG_EXAMPLE_MSC_READONLY
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/cynthion_d21/board.cmake b/hw/bsp/samd21/boards/cynthion_d21/board.cmake
new file mode 100644
index 000000000..67aef67ad
--- /dev/null
+++ b/hw/bsp/samd21/boards/cynthion_d21/board.cmake
@@ -0,0 +1,12 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+  target_link_options(${TARGET} PUBLIC
+    --defsym=BOOTLOADER_SIZE=0x800
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.cmake b/hw/bsp/samd21/boards/feather_m0_express/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/feather_m0_express/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.cmake b/hw/bsp/samd21/boards/itsybitsy_m0/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.cmake b/hw/bsp/samd21/boards/metro_m0_express/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/metro_m0_express/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/qtpy/board.cmake b/hw/bsp/samd21/boards/qtpy/board.cmake
new file mode 100644
index 000000000..f6cd446dd
--- /dev/null
+++ b/hw/bsp/samd21/boards/qtpy/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21E18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21E18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.cmake b/hw/bsp/samd21/boards/seeeduino_xiao/board.cmake
new file mode 100644
index 000000000..c1a612936
--- /dev/null
+++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21G18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21G18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/boards/trinket_m0/board.cmake b/hw/bsp/samd21/boards/trinket_m0/board.cmake
new file mode 100644
index 000000000..f6cd446dd
--- /dev/null
+++ b/hw/bsp/samd21/boards/trinket_m0/board.cmake
@@ -0,0 +1,9 @@
+set(JLINK_DEVICE ATSAMD21E18)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    __SAMD21E18A__
+    CFG_EXAMPLE_VIDEO_READONLY
+    )
+endfunction()
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index 46297f97f..2121e028a 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -28,6 +28,12 @@
 #include "bsp/board_api.h"
 #include "board.h"
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wcast-qual"
+#endif
+
 #include "hal/include/hal_gpio.h"
 #include "hal/include/hal_init.h"
 #include "hri/hri_nvmctrl_d21.h"
@@ -36,6 +42,10 @@
 #include "hpl_pm_config.h"
 #include "hpl/pm/hpl_pm_base.h"
 
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake
new file mode 100644
index 000000000..07186934a
--- /dev/null
+++ b/hw/bsp/samd21/family.cmake
@@ -0,0 +1,105 @@
+include_guard()
+
+set(SDK_DIR ${TOP}/hw/mcu/microchip/samd21)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS SAMD21 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    add_library(${BOARD_TARGET} STATIC
+      ${SDK_DIR}/gcc/system_samd21.c
+      ${SDK_DIR}/hpl/gclk/hpl_gclk.c
+      ${SDK_DIR}/hpl/pm/hpl_pm.c
+      ${SDK_DIR}/hpl/sysctrl/hpl_sysctrl.c
+      ${SDK_DIR}/hal/src/hal_atomic.c
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${SDK_DIR}
+      ${SDK_DIR}/config
+      ${SDK_DIR}/include
+      ${SDK_DIR}/hal/include
+      ${SDK_DIR}/hal/utils/include
+      ${SDK_DIR}/hpl/pm
+      ${SDK_DIR}/hpl/port
+      ${SDK_DIR}/hri
+      ${SDK_DIR}/CMSIS/Include
+      )
+    target_compile_definitions(${BOARD_TARGET} PUBLIC CONF_DFLL_OVERWRITE_CALIBRATION=0)
+
+    update_board(${BOARD_TARGET})
+
+    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+      message(FATAL_ERROR "LD_FILE_${CMAKE_C_COMPILER_ID} not defined")
+    endif ()
+
+    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+      set(STARTUP_FILE_GNU ${SDK_DIR}/gcc/gcc/startup_samd21.c)
+    endif ()
+
+    target_sources(${BOARD_TARGET} PRIVATE
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        --specs=nosys.specs --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_SAMD21 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/microchip/samd/dcd_samd.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_jlink(${TARGET})
+endfunction()

From e8558458c41e65a3a5968524020f1dd9498599db Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 7 Sep 2023 17:09:25 +0700
Subject: [PATCH 2035/2085] fix ci

---
 .idea/cmake.xml                               | 4 ++--
 hw/bsp/samd21/boards/cynthion_d21/board.cmake | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 15dd85f93..2a7babf3f 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -52,8 +52,8 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
-      <configuration PROFILE_NAME="metro_m4_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="metro_m0_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/samd21/boards/cynthion_d21/board.cmake b/hw/bsp/samd21/boards/cynthion_d21/board.cmake
index 67aef67ad..89e821edd 100644
--- a/hw/bsp/samd21/boards/cynthion_d21/board.cmake
+++ b/hw/bsp/samd21/boards/cynthion_d21/board.cmake
@@ -7,6 +7,6 @@ function(update_board TARGET)
     CFG_EXAMPLE_VIDEO_READONLY
     )
   target_link_options(${TARGET} PUBLIC
-    --defsym=BOOTLOADER_SIZE=0x800
+    "LINKER:--defsym=BOOTLOADER_SIZE=0x800"
     )
 endfunction()

From d3c08ecc3ab53b5e1b4fbcb18eb2aab78a5b840e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 7 Sep 2023 17:20:07 +0700
Subject: [PATCH 2036/2085] more ci fix

---
 hw/bsp/samd21/boards/cynthion_d21/board.cmake | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/samd21/boards/cynthion_d21/board.cmake b/hw/bsp/samd21/boards/cynthion_d21/board.cmake
index 89e821edd..fb54b7561 100644
--- a/hw/bsp/samd21/boards/cynthion_d21/board.cmake
+++ b/hw/bsp/samd21/boards/cynthion_d21/board.cmake
@@ -1,5 +1,5 @@
 set(JLINK_DEVICE ATSAMD21G18)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/samd21g18a_flash.ld)
 
 function(update_board TARGET)
   target_compile_definitions(${TARGET} PUBLIC

From 7ce4cfa638a86bfabd7ce8147ea5468d69c1af21 Mon Sep 17 00:00:00 2001
From: maidnl <d.aimo@arduino.cc>
Date: Fri, 8 Sep 2023 10:12:03 +0200
Subject: [PATCH 2037/2085] renesas: added wait function for IN transaction

This fixes a problem found on MSD class where data read from from disks were sometimes partially overwritten by the status MSD message ("USBS...").
The function introduced wait for the hw fifo pipe to be empty, that prevent that new writing in the fife overwrite data which are not yet be transmitted by hw.
---
 src/portable/renesas/rusb2/dcd_rusb2.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 3ec1b70b5..68ef5890f 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -266,6 +266,13 @@ static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void
   tu_fifo_advance_write_pointer(f, count);
 }
 
+
+static void wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) {
+  TU_ASSERT(num);
+  while( (rusb->PIPE_CTR[num-1] & RUSB2_PIPE_CTR_INBUFM_Msk) > 0 ) {}
+}
+
+
 //--------------------------------------------------------------------+
 // Pipe Transfer
 //--------------------------------------------------------------------+
@@ -339,6 +346,7 @@ static bool pipe_xfer_in(rusb2_reg_t* rusb, unsigned num)
   const unsigned rem  = pipe->remaining;
 
   if (!rem) {
+    wait_pipe_fifo_empty(rusb, num);
     pipe->buf = NULL;
     return true;
   }

From bcc77a60e047837a82b0719ffa95a4d6f688468d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 8 Sep 2023 17:40:00 +0700
Subject: [PATCH 2038/2085] get spi working for metro m4 express

---
 hw/bsp/nrf/family.c                           |  73 +++---
 hw/bsp/samd51/boards/metro_m4_express/board.h |   9 +
 hw/bsp/samd51/family.c                        | 231 ++++++++++++++----
 hw/bsp/samd51/family.cmake                    |   1 +
 4 files changed, 238 insertions(+), 76 deletions(-)

diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 39ce179e8..47c765a96 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -102,40 +102,6 @@ void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
 
   tuh_int_handler(1);
 }
-
-//--------------------------------------------------------------------+
-// API: SPI transfer with MAX3421E, must be implemented by application
-//--------------------------------------------------------------------+
-void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
-  (void) rhport;
-
-  // use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt
-  // when disabled
-  if (enabled) {
-    NVIC_EnableIRQ(GPIOTE_IRQn);
-  } else {
-    NVIC_DisableIRQ(GPIOTE_IRQn);
-  }
-}
-
-void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
-  (void) rhport;
-  nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
-}
-
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
-  (void) rhport;
-
-  nrfx_spim_xfer_desc_t xfer = {
-      .p_tx_buffer = tx_buf,
-      .tx_length   = tx_len,
-      .p_rx_buffer = rx_buf,
-      .rx_length   = rx_len,
-  };
-
-  return (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
-}
-
 #endif
 
 
@@ -242,7 +208,7 @@ void board_init(void) {
 
   // manually manage CS
   nrf_gpio_cfg_output(MAX3421E_CS_PIN);
-  tuh_max3421_spi_cs_api(0, false);
+  nrf_gpio_pin_write(MAX3421E_CS_PIN, 1);
 
   // USB host using max3421e usb controller via SPI
   nrfx_spim_config_t cfg = {
@@ -345,3 +311,40 @@ void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
   (void) info;
 }
 #endif
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+
+  // use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt
+  // when disabled and re-enabled.
+  if (enabled) {
+    NVIC_EnableIRQ(GPIOTE_IRQn);
+  } else {
+    NVIC_DisableIRQ(GPIOTE_IRQn);
+  }
+}
+
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
+}
+
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+  (void) rhport;
+
+  nrfx_spim_xfer_desc_t xfer = {
+      .p_tx_buffer = tx_buf,
+      .tx_length   = tx_len,
+      .p_rx_buffer = rx_buf,
+      .rx_length   = rx_len,
+  };
+
+  return (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
+}
+
+#endif
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h
index 5d7734576..3441d03e9 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.h
+++ b/hw/bsp/samd51/boards/metro_m4_express/board.h
@@ -43,6 +43,15 @@
 #define UART_TX_PIN           23
 #define UART_RX_PIN           22
 
+// SPI for USB host shield
+#define MAX3421E_SERCOM   SERCOM2
+#define MAX3421E_SCK_PIN  13
+#define MAX3421E_MOSI_PIN 12
+#define MAX3421E_MISO_PIN 14
+#define MAX3421E_CS_PIN   18 // D10
+#define MAX3241E_INTR_PIN 20 // D9
+
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 2df9cbafb..45a9aa5e0 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -43,30 +43,6 @@
 #pragma GCC diagnostic pop
 #endif
 
-
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_0_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-void USB_1_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-void USB_2_Handler (void)
-{
-  tud_int_handler(0);
-}
-
-void USB_3_Handler (void)
-{
-  tud_int_handler(0);
-}
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
@@ -77,8 +53,81 @@ void USB_3_Handler (void)
 /* Not referenced GCLKs, initialized last */
 #define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
 
-void board_init(void)
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_0_Handler(void) {
+  tud_int_handler(0);
+}
+
+void USB_1_Handler(void) {
+  tud_int_handler(0);
+}
+
+void USB_2_Handler(void) {
+  tud_int_handler(0);
+}
+
+void USB_3_Handler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+void max3421_init(void)
 {
+  //------------- SPI Init -------------//
+
+  // Enable the APB clock for SERCOM2
+  MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
+
+  // Configure GCLK for SERCOM2, initClockNVIC()
+  GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  GCLK->PCHCTRL[SERCOM2_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+  // Disable the SPI module
+  SERCOM2->SPI.CTRLA.bit.ENABLE = 0;
+
+  // Reset the SPI module
+  SERCOM2->SPI.CTRLA.bit.SWRST = 1;
+  while (SERCOM2->SPI.SYNCBUSY.bit.SWRST);
+
+  // Set up SPI in master mode, MSB first, SPI mode 0
+  uint8_t const mosi_pad = 0;
+  uint8_t const miso_pad = 2;
+  SERCOM2->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(mosi_pad) | SERCOM_SPI_CTRLA_DIPO(miso_pad);
+
+  SERCOM2->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
+  while( SERCOM2->SPI.SYNCBUSY.bit.CTRLB == 1 );
+
+  // Set the baud rate
+  uint32_t baudrate = 4000000u;
+  SERCOM2->SPI.BAUD.reg = (uint8_t)(SystemCoreClock / (2 * baudrate) - 1); // Replace 1000000 with your desired baud rate
+
+  // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2)
+  // 2 function C: PIO_SERCOM
+  gpio_set_pin_direction(MAX3421E_SCK_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421E_SCK_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421E_SCK_PIN, 2);
+
+  gpio_set_pin_direction(MAX3421E_MOSI_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421E_MOSI_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421E_MOSI_PIN, 2);
+
+  gpio_set_pin_direction(MAX3421E_MISO_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421E_MISO_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421E_MISO_PIN, 2);
+
+  // Enable the SPI module
+  SERCOM2->SPI.CTRLA.bit.ENABLE = 1;
+  while (SERCOM2->SPI.SYNCBUSY.bit.ENABLE);
+}
+#endif
+
+void board_init(void) {
   // Clock init ( follow hpl_init.c )
   hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, 0);
 
@@ -104,7 +153,7 @@ void board_init(void)
   gpio_set_pin_direction(BUTTON_PIN, GPIO_DIRECTION_IN);
   gpio_set_pin_pull_mode(BUTTON_PIN, GPIO_PULL_UP);
 
-#if CFG_TUSB_OS  == OPT_OS_FREERTOS
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB_0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
   NVIC_SetPriority(USB_1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
@@ -129,45 +178,145 @@ void board_init(void)
 
   gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM);
   gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+  // CS pin
+  gpio_set_pin_direction(MAX3421E_CS_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(MAX3421E_CS_PIN, 1);
+
+  // SPI
+  max3421_init();
+
+  // INT pin with external interrupt
+  gpio_set_pin_direction(MAX3241E_INTR_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3241E_INTR_PIN, GPIO_PULL_UP);
+
+  // Enable the APB clock for EIC (External Interrupt Controller)
+  MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+
+  // Configure GCLK for EIC
+  GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+  // Configure PA20 as an input
+  PORT->Group[0].DIRCLR.reg = PORT_PA20;
+  PORT->Group[0].PINCFG[20].reg = PORT_PINCFG_INEN | PORT_PINCFG_PULLEN;
+  PORT->Group[0].OUTSET.reg = PORT_PA20;  // Enable pull-up
+
+  // Configure PA20 to use EIC
+  PORT->Group[0].PMUX[10].bit.PMUXE = MUX_PA20A_EIC_EXTINT4;
+  PORT->Group[0].PINCFG[20].bit.PMUXEN = 1;
+
+  // Disable EIC
+  EIC->CTRLA.bit.ENABLE = 0;
+  while (EIC->SYNCBUSY.bit.ENABLE);
+
+  // Configure EXTINT4 (PA20) to trigger on falling edge
+  EIC->CONFIG[0].reg |= EIC_CONFIG_SENSE4_FALL;
+
+  // Enable EXTINT4
+  EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << 4);
+
+  // Enable EIC
+  EIC->CTRLA.bit.ENABLE = 1;
+  while (EIC->SYNCBUSY.bit.ENABLE);
+
+#endif
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   gpio_set_pin_level(LED_PIN, state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   // button is active low
   return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
 
-void SysTick_Handler (void)
-{
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+void EIC_4_Handler(void)
+{
+  // Clear the interrupt flag
+  EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << 4);
+
+  // Call the TinyUSB interrupt handler
+  tuh_int_handler(1);
+}
+
+void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+
+  if (enabled) {
+    NVIC_EnableIRQ(EIC_4_IRQn);
+  } else {
+    NVIC_DisableIRQ(EIC_4_IRQn);
+  }
+}
+
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  gpio_set_pin_level(MAX3421E_CS_PIN, active ? 0 : 1);
+}
+
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+  (void) rhport;
+
+  size_t count = 0;
+  while (count < tx_len || count < rx_len) {
+    // Wait for the transmit buffer to be empty
+//    while (!SERCOM2->SPI.INTFLAG.bit.DRE);
+
+    // Write data to be transmitted
+    uint8_t data = 0x00;
+    if (count < tx_len) {
+       data = tx_buf[count];
+    }
+
+    SERCOM2->SPI.DATA.bit.DATA = data;
+
+    // Wait for the receive buffer to be filled
+    while (!SERCOM2->SPI.INTFLAG.bit.RXC);
+
+    // Read received data
+    if (rx_buf) {
+      rx_buf[count] = SERCOM2->SPI.DATA.bit.DATA;
+    }
+
+    count++;
+  }
+
+  return true;
+}
+#endif
+
 #endif
diff --git a/hw/bsp/samd51/family.cmake b/hw/bsp/samd51/family.cmake
index fa9586066..1dce483fd 100644
--- a/hw/bsp/samd51/family.cmake
+++ b/hw/bsp/samd51/family.cmake
@@ -93,6 +93,7 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_SAMD51 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/microchip/samd/dcd_samd.c
+    ${TOP}/src/portable/analog/max3421/hcd_max3421.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 

From 1d68f2a3280cdc76912ec7e89238640e950e542c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 8 Sep 2023 18:39:09 +0700
Subject: [PATCH 2039/2085] metro m4 working with max3421e

---
 hw/bsp/samd51/family.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 45a9aa5e0..51cfd19ba 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -294,7 +294,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
   size_t count = 0;
   while (count < tx_len || count < rx_len) {
     // Wait for the transmit buffer to be empty
-//    while (!SERCOM2->SPI.INTFLAG.bit.DRE);
+    while (!SERCOM2->SPI.INTFLAG.bit.DRE);
 
     // Write data to be transmitted
     uint8_t data = 0x00;
@@ -302,19 +302,24 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
        data = tx_buf[count];
     }
 
-    SERCOM2->SPI.DATA.bit.DATA = data;
+    SERCOM2->SPI.DATA.reg = (uint32_t) data;
 
     // Wait for the receive buffer to be filled
     while (!SERCOM2->SPI.INTFLAG.bit.RXC);
 
     // Read received data
-    if (rx_buf) {
-      rx_buf[count] = SERCOM2->SPI.DATA.bit.DATA;
+    data = (uint8_t) SERCOM2->SPI.DATA.reg;
+    if (count < rx_len) {
+      rx_buf[count] = data;
     }
 
     count++;
   }
 
+  // wait for bus idle and clear flags
+  while (!(SERCOM2->SPI.INTFLAG.reg & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE)));
+  SERCOM2->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE;
+
   return true;
 }
 #endif

From 228acbeac2642534753beffd866db2a7eab45e31 Mon Sep 17 00:00:00 2001
From: maidnl <d.aimo@arduino.cc>
Date: Fri, 8 Sep 2023 15:48:05 +0200
Subject: [PATCH 2040/2085] wait_pipe_fifo_empty() now returns bool (as
 expected using TU_ASSERT macro)

---
 src/portable/renesas/rusb2/dcd_rusb2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c
index 68ef5890f..24edc30e7 100644
--- a/src/portable/renesas/rusb2/dcd_rusb2.c
+++ b/src/portable/renesas/rusb2/dcd_rusb2.c
@@ -267,9 +267,10 @@ static void pipe_read_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void
 }
 
 
-static void wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) {
+static bool wait_pipe_fifo_empty(rusb2_reg_t* rusb, uint8_t num) {
   TU_ASSERT(num);
   while( (rusb->PIPE_CTR[num-1] & RUSB2_PIPE_CTR_INBUFM_Msk) > 0 ) {}
+  return true;
 }
 
 

From c074488f75522c7c29dc7853aa2d8597b4858f89 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 9 Sep 2023 12:20:16 +0700
Subject: [PATCH 2041/2085] minor rename

---
 .../boards/feather_nrf52840_express/board.h   |  10 +-
 hw/bsp/nrf/boards/pca10056/board.h            |  10 +-
 hw/bsp/nrf/boards/pca10095/board.h            |  10 +-
 hw/bsp/nrf/family.c                           |  22 +--
 hw/bsp/samd51/boards/metro_m4_express/board.h |  12 +-
 hw/bsp/samd51/family.c                        | 183 +++++++++---------
 src/portable/analog/max3421/hcd_max3421.c     |  14 +-
 7 files changed, 131 insertions(+), 130 deletions(-)

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index e6e7590ac..76100a14a 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -46,11 +46,11 @@
 #define UART_TX_PIN     25
 
 // SPI for USB host shield
-#define MAX3421E_SCK_PIN  14
-#define MAX3421E_MOSI_PIN 13
-#define MAX3421E_MISO_PIN 15
-#define MAX3421E_CS_PIN   27
-#define MAX3241E_INTR_PIN 26
+#define MAX3421_SCK_PIN  14
+#define MAX3421_MOSI_PIN 13
+#define MAX3421_MISO_PIN 15
+#define MAX3421_CS_PIN   27
+#define MAX3421_INTR_PIN 26
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h
index 16d31addb..9459e7911 100644
--- a/hw/bsp/nrf/boards/pca10056/board.h
+++ b/hw/bsp/nrf/boards/pca10056/board.h
@@ -46,11 +46,11 @@
 #define UART_TX_PIN           6
 
 // SPI for USB host shield
-#define MAX3421E_SCK_PIN  _PINNUM(1, 15)
-#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
-#define MAX3421E_MISO_PIN _PINNUM(1, 14)
-#define MAX3421E_CS_PIN   _PINNUM(1, 12)
-#define MAX3241E_INTR_PIN _PINNUM(1, 11)
+#define MAX3421_SCK_PIN  _PINNUM(1, 15)
+#define MAX3421_MOSI_PIN _PINNUM(1, 13)
+#define MAX3421_MISO_PIN _PINNUM(1, 14)
+#define MAX3421_CS_PIN   _PINNUM(1, 12)
+#define MAX3421_INTR_PIN _PINNUM(1, 11)
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h
index b9d3a19dc..ad3379bf6 100644
--- a/hw/bsp/nrf/boards/pca10095/board.h
+++ b/hw/bsp/nrf/boards/pca10095/board.h
@@ -46,11 +46,11 @@
 #define UART_TX_PIN           33
 
 // SPI for USB host shield
-#define MAX3421E_SCK_PIN  _PINNUM(1, 15)
-#define MAX3421E_MOSI_PIN _PINNUM(1, 13)
-#define MAX3421E_MISO_PIN _PINNUM(1, 14)
-#define MAX3421E_CS_PIN   _PINNUM(1, 12)
-#define MAX3241E_INTR_PIN _PINNUM(1, 11)
+#define MAX3421_SCK_PIN  _PINNUM(1, 15)
+#define MAX3421_MOSI_PIN _PINNUM(1, 13)
+#define MAX3421_MISO_PIN _PINNUM(1, 14)
+#define MAX3421_CS_PIN   _PINNUM(1, 12)
+#define MAX3421_INTR_PIN _PINNUM(1, 11)
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 47c765a96..6fcfd9476 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -97,8 +97,8 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 
-void max3421e_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
-  if (!(pin == MAX3241E_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
+void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
+  if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
 
   tuh_int_handler(1);
 }
@@ -207,14 +207,14 @@ void board_init(void) {
   #endif
 
   // manually manage CS
-  nrf_gpio_cfg_output(MAX3421E_CS_PIN);
-  nrf_gpio_pin_write(MAX3421E_CS_PIN, 1);
+  nrf_gpio_cfg_output(MAX3421_CS_PIN);
+  nrf_gpio_pin_write(MAX3421_CS_PIN, 1);
 
   // USB host using max3421e usb controller via SPI
   nrfx_spim_config_t cfg = {
-      .sck_pin        = MAX3421E_SCK_PIN,
-      .mosi_pin       = MAX3421E_MOSI_PIN,
-      .miso_pin       = MAX3421E_MISO_PIN,
+      .sck_pin        = MAX3421_SCK_PIN,
+      .mosi_pin       = MAX3421_MOSI_PIN,
+      .miso_pin       = MAX3421_MISO_PIN,
       .ss_pin         = NRFX_SPIM_PIN_NOT_USED,
       .ss_active_high = false,
       .irq_priority   = 3,
@@ -233,8 +233,8 @@ void board_init(void) {
   nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
   in_config.pull = NRF_GPIO_PIN_PULLUP;
 
-  nrfx_gpiote_in_init(MAX3241E_INTR_PIN, &in_config, max3421e_int_handler);
-  nrfx_gpiote_trigger_enable(MAX3241E_INTR_PIN, true);
+  nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
+  nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
 #endif
 
 }
@@ -317,7 +317,7 @@ void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
 //--------------------------------------------------------------------+
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
-void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
   // use NVIC_Enable/Disable instead since nrfx_gpiote_trigger_enable/disable clear pending and can miss interrupt
@@ -331,7 +331,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
-  nrf_gpio_pin_write(MAX3421E_CS_PIN, active ? 0 : 1);
+  nrf_gpio_pin_write(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h
index 3441d03e9..fe2a867a4 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.h
+++ b/hw/bsp/samd51/boards/metro_m4_express/board.h
@@ -44,12 +44,12 @@
 #define UART_RX_PIN           22
 
 // SPI for USB host shield
-#define MAX3421E_SERCOM   SERCOM2
-#define MAX3421E_SCK_PIN  13
-#define MAX3421E_MOSI_PIN 12
-#define MAX3421E_MISO_PIN 14
-#define MAX3421E_CS_PIN   18 // D10
-#define MAX3241E_INTR_PIN 20 // D9
+#define MAX3421_SERCOM   2  // SERCOM2
+#define MAX3421_SCK_PIN  13
+#define MAX3421_MOSI_PIN 12
+#define MAX3421_MISO_PIN 14
+#define MAX3421_CS_PIN   18 // D10
+#define MAX3421_INTR_PIN 20 // D9
 
 
 #ifdef __cplusplus
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 51cfd19ba..34dd93cef 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -73,58 +73,14 @@ void USB_3_Handler(void) {
 }
 
 //--------------------------------------------------------------------+
-//
+// Implementation
 //--------------------------------------------------------------------+
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-void max3421_init(void)
-{
-  //------------- SPI Init -------------//
+static void max3421_init(void);
 
-  // Enable the APB clock for SERCOM2
-  MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
+//#define
 
-  // Configure GCLK for SERCOM2, initClockNVIC()
-  GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
-  GCLK->PCHCTRL[SERCOM2_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
-
-  // Disable the SPI module
-  SERCOM2->SPI.CTRLA.bit.ENABLE = 0;
-
-  // Reset the SPI module
-  SERCOM2->SPI.CTRLA.bit.SWRST = 1;
-  while (SERCOM2->SPI.SYNCBUSY.bit.SWRST);
-
-  // Set up SPI in master mode, MSB first, SPI mode 0
-  uint8_t const mosi_pad = 0;
-  uint8_t const miso_pad = 2;
-  SERCOM2->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(mosi_pad) | SERCOM_SPI_CTRLA_DIPO(miso_pad);
-
-  SERCOM2->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
-  while( SERCOM2->SPI.SYNCBUSY.bit.CTRLB == 1 );
-
-  // Set the baud rate
-  uint32_t baudrate = 4000000u;
-  SERCOM2->SPI.BAUD.reg = (uint8_t)(SystemCoreClock / (2 * baudrate) - 1); // Replace 1000000 with your desired baud rate
-
-  // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2)
-  // 2 function C: PIO_SERCOM
-  gpio_set_pin_direction(MAX3421E_SCK_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_pull_mode(MAX3421E_SCK_PIN, GPIO_PULL_OFF);
-  gpio_set_pin_function(MAX3421E_SCK_PIN, 2);
-
-  gpio_set_pin_direction(MAX3421E_MOSI_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_pull_mode(MAX3421E_MOSI_PIN, GPIO_PULL_OFF);
-  gpio_set_pin_function(MAX3421E_MOSI_PIN, 2);
-
-  gpio_set_pin_direction(MAX3421E_MISO_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(MAX3421E_MISO_PIN, GPIO_PULL_OFF);
-  gpio_set_pin_function(MAX3421E_MISO_PIN, 2);
-
-  // Enable the SPI module
-  SERCOM2->SPI.CTRLA.bit.ENABLE = 1;
-  while (SERCOM2->SPI.SYNCBUSY.bit.ENABLE);
-}
 #endif
 
 void board_init(void) {
@@ -180,46 +136,7 @@ void board_init(void) {
   gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP);
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-  // CS pin
-  gpio_set_pin_direction(MAX3421E_CS_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(MAX3421E_CS_PIN, 1);
-
-  // SPI
   max3421_init();
-
-  // INT pin with external interrupt
-  gpio_set_pin_direction(MAX3241E_INTR_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(MAX3241E_INTR_PIN, GPIO_PULL_UP);
-
-  // Enable the APB clock for EIC (External Interrupt Controller)
-  MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
-
-  // Configure GCLK for EIC
-  GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
-
-  // Configure PA20 as an input
-  PORT->Group[0].DIRCLR.reg = PORT_PA20;
-  PORT->Group[0].PINCFG[20].reg = PORT_PINCFG_INEN | PORT_PINCFG_PULLEN;
-  PORT->Group[0].OUTSET.reg = PORT_PA20;  // Enable pull-up
-
-  // Configure PA20 to use EIC
-  PORT->Group[0].PMUX[10].bit.PMUXE = MUX_PA20A_EIC_EXTINT4;
-  PORT->Group[0].PINCFG[20].bit.PMUXEN = 1;
-
-  // Disable EIC
-  EIC->CTRLA.bit.ENABLE = 0;
-  while (EIC->SYNCBUSY.bit.ENABLE);
-
-  // Configure EXTINT4 (PA20) to trigger on falling edge
-  EIC->CONFIG[0].reg |= EIC_CONFIG_SENSE4_FALL;
-
-  // Enable EXTINT4
-  EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << 4);
-
-  // Enable EIC
-  EIC->CTRLA.bit.ENABLE = 1;
-  while (EIC->SYNCBUSY.bit.ENABLE);
-
 #endif
 }
 
@@ -264,8 +181,91 @@ uint32_t board_millis(void) {
 //--------------------------------------------------------------------+
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
-void EIC_4_Handler(void)
-{
+static void max3421_init(void) {
+  // CS pin
+  gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(MAX3421_CS_PIN, 1);
+
+  //------------- SPI Init -------------//
+
+  // Enable the APB clock for SERCOM2
+  MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
+
+  // Configure GCLK for SERCOM2, initClockNVIC()
+  GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  GCLK->PCHCTRL[SERCOM2_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+  // Disable the SPI module
+  SERCOM2->SPI.CTRLA.bit.ENABLE = 0;
+
+  // Reset the SPI module
+  SERCOM2->SPI.CTRLA.bit.SWRST = 1;
+  while (SERCOM2->SPI.SYNCBUSY.bit.SWRST);
+
+  // Set up SPI in master mode, MSB first, SPI mode 0
+  uint8_t const mosi_pad = 0;
+  uint8_t const miso_pad = 2;
+  SERCOM2->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(mosi_pad) | SERCOM_SPI_CTRLA_DIPO(miso_pad);
+
+  SERCOM2->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
+  while (SERCOM2->SPI.SYNCBUSY.bit.CTRLB == 1);
+
+  // Set the baud rate
+  uint32_t baudrate = 4000000u;
+  SERCOM2->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) -
+                                     1); // Replace 1000000 with your desired baud rate
+
+  // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2)
+  // 2 function C: PIO_SERCOM
+  gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_SCK_PIN, 2);
+
+  gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_MOSI_PIN, 2);
+
+  gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_MISO_PIN, 2);
+
+  // Enable the SPI module
+  SERCOM2->SPI.CTRLA.bit.ENABLE = 1;
+  while (SERCOM2->SPI.SYNCBUSY.bit.ENABLE);
+
+  //------------- External Interrupt -------------//
+
+  // INT pin with external interrupt
+  gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
+
+  // Enable the APB clock for EIC (External Interrupt Controller)
+  MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
+
+  // Configure GCLK for EIC
+  GCLK->PCHCTRL[EIC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+
+  // Configure PA20 as an input with function A (external interrupt)
+  gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
+  gpio_set_pin_function(MAX3421_INTR_PIN, 0);
+
+  // Disable EIC
+  EIC->CTRLA.bit.ENABLE = 0;
+  while (EIC->SYNCBUSY.bit.ENABLE);
+
+  // Configure EXTINT4 (PA20) to trigger on falling edge
+  EIC->CONFIG[0].reg |= EIC_CONFIG_SENSE4_FALL;
+
+  // Enable EXTINT4
+  EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << 4);
+
+  // Enable EIC
+  EIC->CTRLA.bit.ENABLE = 1;
+  while (EIC->SYNCBUSY.bit.ENABLE);
+}
+
+void EIC_4_Handler(void) {
   // Clear the interrupt flag
   EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << 4);
 
@@ -273,7 +273,7 @@ void EIC_4_Handler(void)
   tuh_int_handler(1);
 }
 
-void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
   if (enabled) {
@@ -285,7 +285,7 @@ void tuh_max3421e_int_api(uint8_t rhport, bool enabled) {
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
-  gpio_set_pin_level(MAX3421E_CS_PIN, active ? 0 : 1);
+  gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
@@ -299,7 +299,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
     // Write data to be transmitted
     uint8_t data = 0x00;
     if (count < tx_len) {
-       data = tx_buf[count];
+      data = tx_buf[count];
     }
 
     SERCOM2->SPI.DATA.reg = (uint32_t) data;
@@ -322,6 +322,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
 
   return true;
 }
+
 #endif
 
 #endif
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 95cf5516e..238b518a0 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -212,7 +212,7 @@ static max3421_data_t _hcd_data;
 
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
-void tuh_max3421e_int_api(uint8_t rhport, bool enabled);
+void tuh_max3421_int_api(uint8_t rhport, bool enabled);
 
 static void handle_connect_irq(uint8_t rhport, bool in_isr);
 static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
@@ -225,7 +225,7 @@ static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
   // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
   if (!in_isr) {
     (void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
-    tuh_max3421e_int_api(rhport, false);
+    tuh_max3421_int_api(rhport, false);
   }
 
   // assert CS
@@ -238,7 +238,7 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
 
   // mutex unlock and re-enable interrupt
   if (!in_isr) {
-    tuh_max3421e_int_api(rhport, true);
+    tuh_max3421_int_api(rhport, true);
     (void) osal_mutex_unlock(_hcd_data.spi_mutex);
   }
 }
@@ -411,7 +411,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
 bool hcd_init(uint8_t rhport) {
   (void) rhport;
 
-  tuh_max3421e_int_api(rhport, false);
+  tuh_max3421_int_api(rhport, false);
   tuh_max3421_spi_cs_api(rhport, false);
 
   TU_LOG2_INT(sizeof(max3421_ep_t));
@@ -450,7 +450,7 @@ bool hcd_init(uint8_t rhport) {
   // Enable IRQ
   hien_write(rhport, DEFAULT_HIEN, false);
 
-  tuh_max3421e_int_api(rhport, true);
+  tuh_max3421_int_api(rhport, true);
 
   // Enable Interrupt pin
   reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
@@ -461,13 +461,13 @@ bool hcd_init(uint8_t rhport) {
 // Enable USB interrupt
 // Not actually enable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_enable (uint8_t rhport) {
-  tuh_max3421e_int_api(rhport, true);
+  tuh_max3421_int_api(rhport, true);
 }
 
 // Disable USB interrupt
 // Not actually disable GPIO interrupt, just set variable to prevent handler to process
 void hcd_int_disable(uint8_t rhport) {
-  tuh_max3421e_int_api(rhport, false);
+  tuh_max3421_int_api(rhport, false);
 }
 
 // Get frame number (1ms)

From 605ad73ec02033aa6b66e6899e232537ca2354bb Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 9 Sep 2023 13:04:36 +0700
Subject: [PATCH 2042/2085] refactor max3421_init() for samd51 to be generic
 for sercom and eic

---
 hw/bsp/samd51/boards/metro_m4_express/board.h |  15 ++-
 hw/bsp/samd51/family.c                        | 108 +++++++++++-------
 2 files changed, 77 insertions(+), 46 deletions(-)

diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h
index fe2a867a4..aa6bdd0c8 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.h
+++ b/hw/bsp/samd51/boards/metro_m4_express/board.h
@@ -44,13 +44,16 @@
 #define UART_RX_PIN           22
 
 // SPI for USB host shield
-#define MAX3421_SERCOM   2  // SERCOM2
-#define MAX3421_SCK_PIN  13
-#define MAX3421_MOSI_PIN 12
-#define MAX3421_MISO_PIN 14
-#define MAX3421_CS_PIN   18 // D10
-#define MAX3421_INTR_PIN 20 // D9
+#define MAX3421_SERCOM_ID 2  // SERCOM2
+#define MAX3421_SCK_PIN   13
+#define MAX3421_MOSI_PIN  12
+#define MAX3421_MOSI_PAD  0
+#define MAX3421_MISO_PIN  14
+#define MAX3421_MISO_PAD  2
+#define MAX3421_CS_PIN    18 // D10
 
+#define MAX3421_INTR_PIN  20 // D9
+#define MAX3421_INTR_EIC_ID 4 // EIC4
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 34dd93cef..f9e1718d0 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -79,7 +79,8 @@ void USB_3_Handler(void) {
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 static void max3421_init(void);
 
-//#define
+#define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID)
+#define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler)
 
 #endif
 
@@ -182,41 +183,55 @@ uint32_t board_millis(void) {
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
 static void max3421_init(void) {
-  // CS pin
-  gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
-  gpio_set_pin_level(MAX3421_CS_PIN, 1);
-
   //------------- SPI Init -------------//
+  uint32_t const baudrate = 4000000u;
 
-  // Enable the APB clock for SERCOM2
-  MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
+  struct {
+    volatile uint32_t *mck_apb;
+    uint32_t mask;
+    uint8_t gclk_id_core;
+    uint8_t gclk_id_slow;
+  } const sercom_clock[] = {
+      { &MCLK->APBAMASK.reg, MCLK_APBAMASK_SERCOM0, SERCOM0_GCLK_ID_CORE, SERCOM0_GCLK_ID_SLOW },
+      { &MCLK->APBAMASK.reg, MCLK_APBAMASK_SERCOM1, SERCOM1_GCLK_ID_CORE, SERCOM1_GCLK_ID_SLOW },
+      { &MCLK->APBBMASK.reg, MCLK_APBBMASK_SERCOM2, SERCOM2_GCLK_ID_CORE, SERCOM2_GCLK_ID_SLOW },
+      { &MCLK->APBBMASK.reg, MCLK_APBBMASK_SERCOM3, SERCOM3_GCLK_ID_CORE, SERCOM3_GCLK_ID_SLOW },
+      { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM4, SERCOM4_GCLK_ID_CORE, SERCOM4_GCLK_ID_SLOW },
+      { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM5, SERCOM5_GCLK_ID_CORE, SERCOM5_GCLK_ID_SLOW },
+      #ifdef SERCOM6_GCLK_ID_CORE
+      { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM6, SERCOM6_GCLK_ID_CORE, SERCOM6_GCLK_ID_SLOW },
+      #endif
+      #ifdef SERCOM7_GCLK_ID_CORE
+      { &MCLK->APBDMASK.reg, MCLK_APBDMASK_SERCOM7, SERCOM7_GCLK_ID_CORE, SERCOM7_GCLK_ID_SLOW },
+      #endif
+  };
 
-  // Configure GCLK for SERCOM2, initClockNVIC()
-  GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
-  GCLK->PCHCTRL[SERCOM2_GCLK_ID_SLOW].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  Sercom* sercom = MAX3421_SERCOM;
+
+  // Enable the APB clock for SERCOM
+  *sercom_clock[MAX3421_SERCOM_ID].mck_apb |= sercom_clock[MAX3421_SERCOM_ID].mask;
+
+  // Configure GCLK for SERCOM
+  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_core].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_slow].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
 
   // Disable the SPI module
-  SERCOM2->SPI.CTRLA.bit.ENABLE = 0;
+  sercom->SPI.CTRLA.bit.ENABLE = 0;
 
   // Reset the SPI module
-  SERCOM2->SPI.CTRLA.bit.SWRST = 1;
-  while (SERCOM2->SPI.SYNCBUSY.bit.SWRST);
+  sercom->SPI.CTRLA.bit.SWRST = 1;
+  while (sercom->SPI.SYNCBUSY.bit.SWRST);
 
   // Set up SPI in master mode, MSB first, SPI mode 0
-  uint8_t const mosi_pad = 0;
-  uint8_t const miso_pad = 2;
-  SERCOM2->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(mosi_pad) | SERCOM_SPI_CTRLA_DIPO(miso_pad);
+  sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(MAX3421_MOSI_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_MISO_PAD);
 
-  SERCOM2->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
-  while (SERCOM2->SPI.SYNCBUSY.bit.CTRLB == 1);
+  sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
+  while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
 
   // Set the baud rate
-  uint32_t baudrate = 4000000u;
-  SERCOM2->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) -
-                                     1); // Replace 1000000 with your desired baud rate
+  sercom->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) - 1);
 
-  // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2)
-  // 2 function C: PIO_SERCOM
+  // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
   gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
   gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
   gpio_set_pin_function(MAX3421_SCK_PIN, 2);
@@ -229,16 +244,16 @@ static void max3421_init(void) {
   gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
   gpio_set_pin_function(MAX3421_MISO_PIN, 2);
 
+  // CS pin
+  gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(MAX3421_CS_PIN, 1);
+
   // Enable the SPI module
-  SERCOM2->SPI.CTRLA.bit.ENABLE = 1;
-  while (SERCOM2->SPI.SYNCBUSY.bit.ENABLE);
+  sercom->SPI.CTRLA.bit.ENABLE = 1;
+  while (sercom->SPI.SYNCBUSY.bit.ENABLE);
 
   //------------- External Interrupt -------------//
 
-  // INT pin with external interrupt
-  gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
-  gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
-
   // Enable the APB clock for EIC (External Interrupt Controller)
   MCLK->APBAMASK.reg |= MCLK_APBAMASK_EIC;
 
@@ -255,19 +270,30 @@ static void max3421_init(void) {
   while (EIC->SYNCBUSY.bit.ENABLE);
 
   // Configure EXTINT4 (PA20) to trigger on falling edge
-  EIC->CONFIG[0].reg |= EIC_CONFIG_SENSE4_FALL;
+  volatile uint32_t * eic_config;
+  uint8_t sense_shift;
+  if ( MAX3421_INTR_EIC_ID < 8 ) {
+    eic_config = &EIC->CONFIG[0].reg;
+    sense_shift = MAX3421_INTR_EIC_ID * 4;
+  } else {
+    eic_config = &EIC->CONFIG[1].reg;
+    sense_shift = (MAX3421_INTR_EIC_ID - 8) * 4;
+  }
 
-  // Enable EXTINT4
-  EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << 4);
+  *eic_config &= ~(7 << sense_shift);
+  *eic_config |= 2 << sense_shift;
+
+  // Enable External Interrupt
+  EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
 
   // Enable EIC
   EIC->CTRLA.bit.ENABLE = 1;
   while (EIC->SYNCBUSY.bit.ENABLE);
 }
 
-void EIC_4_Handler(void) {
+void MAX3421_EIC_Handler(void) {
   // Clear the interrupt flag
-  EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << 4);
+  EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
 
   // Call the TinyUSB interrupt handler
   tuh_int_handler(1);
@@ -291,10 +317,12 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
   (void) rhport;
 
+  Sercom* sercom = MAX3421_SERCOM;
+
   size_t count = 0;
   while (count < tx_len || count < rx_len) {
     // Wait for the transmit buffer to be empty
-    while (!SERCOM2->SPI.INTFLAG.bit.DRE);
+    while (!sercom->SPI.INTFLAG.bit.DRE);
 
     // Write data to be transmitted
     uint8_t data = 0x00;
@@ -302,13 +330,13 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
       data = tx_buf[count];
     }
 
-    SERCOM2->SPI.DATA.reg = (uint32_t) data;
+    sercom->SPI.DATA.reg = (uint32_t) data;
 
     // Wait for the receive buffer to be filled
-    while (!SERCOM2->SPI.INTFLAG.bit.RXC);
+    while (!sercom->SPI.INTFLAG.bit.RXC);
 
     // Read received data
-    data = (uint8_t) SERCOM2->SPI.DATA.reg;
+    data = (uint8_t) sercom->SPI.DATA.reg;
     if (count < rx_len) {
       rx_buf[count] = data;
     }
@@ -317,8 +345,8 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
   }
 
   // wait for bus idle and clear flags
-  while (!(SERCOM2->SPI.INTFLAG.reg & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE)));
-  SERCOM2->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE;
+  while (!(sercom->SPI.INTFLAG.reg & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE)));
+  sercom->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE;
 
   return true;
 }

From e32c1e08bd701b5dda7d081b10ba3262e2061326 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Sat, 9 Sep 2023 16:50:16 +0700
Subject: [PATCH 2043/2085] both samd21/d51 works perfectly with max3421e

---
 hw/bsp/samd21/boards/metro_m0_express/board.h |  16 ++
 hw/bsp/samd21/family.c                        | 230 +++++++++++++++---
 hw/bsp/samd21/family.cmake                    |   1 +
 hw/bsp/samd51/boards/metro_m4_express/board.h |  22 +-
 hw/bsp/samd51/family.c                        |  19 +-
 5 files changed, 234 insertions(+), 54 deletions(-)

diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.h b/hw/bsp/samd21/boards/metro_m0_express/board.h
index d26aae53c..6dd53e901 100644
--- a/hw/bsp/samd21/boards/metro_m0_express/board.h
+++ b/hw/bsp/samd21/boards/metro_m0_express/board.h
@@ -43,6 +43,22 @@
 #define UART_RX_PIN           4
 #define UART_TX_PIN           5
 
+// SPI for USB host shield
+#define MAX3421_SERCOM_ID       4       // SERCOM4
+#define MAX3421_SERCOM_FUNCTION 3       // function D (Sercom Alt)
+
+#define MAX3421_SCK_PIN         (32+11)
+#define MAX3421_MOSI_PIN        (32+10)
+#define MAX3421_MISO_PIN        12
+#define MAX3421_TX_PAD          1 // MOSI = PAD_2, SCK = PAD_3
+#define MAX3421_RX_PAD          0 // MISO = PAD_2
+
+#define MAX3421_CS_PIN          18      // D10
+
+#define MAX3421_INTR_PIN        7       // D9
+#define MAX3421_INTR_EIC_ID     7       // EIC7
+
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index 2121e028a..cfe66b8dc 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -46,19 +46,6 @@
 #pragma GCC diagnostic pop
 #endif
 
-//--------------------------------------------------------------------+
-// Forward USB interrupt events to TinyUSB IRQ Handler
-//--------------------------------------------------------------------+
-void USB_Handler(void)
-{
-  tud_int_handler(0);
-}
-
-//--------------------------------------------------------------------+
-// UART support
-//--------------------------------------------------------------------+
-static void uart_init(void);
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
@@ -69,8 +56,25 @@ static void uart_init(void);
 /* Not referenced GCLKs, initialized last */
 #define _GCLK_INIT_LAST (~_GCLK_INIT_1ST)
 
-void board_init(void)
-{
+//--------------------------------------------------------------------+
+// Forward USB interrupt events to TinyUSB IRQ Handler
+//--------------------------------------------------------------------+
+void USB_Handler(void) {
+  tud_int_handler(0);
+}
+
+//--------------------------------------------------------------------+
+// Implementation
+//--------------------------------------------------------------------+
+static void uart_init(void);
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+#define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID)
+
+static void max3421_init(void);
+#endif
+
+void board_init(void) {
   // Clock init ( follow hpl_init.c )
   hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, 2);
 
@@ -85,7 +89,7 @@ void board_init(void)
   // Update SystemCoreClock since it is hard coded with asf4 and not correct
   // Init 1ms tick timer (samd SystemCoreClock may not correct)
   SystemCoreClock = CONF_CPU_FREQUENCY;
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
   SysTick_Config(CONF_CPU_FREQUENCY / 1000);
 #endif
 
@@ -103,7 +107,7 @@ void board_init(void)
 
   uart_init();
 
-#if CFG_TUSB_OS  == OPT_OS_FREERTOS
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
   // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
   NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
 #endif
@@ -134,22 +138,24 @@ void board_init(void)
 
   gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3);
   _gclk_enable_channel(TCC0_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+  max3421_init();
+#endif
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
-  (void)state;
+void board_led_write(bool state) {
+  (void) state;
 #ifdef LED_PIN
-  gpio_set_pin_level(LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
+  gpio_set_pin_level(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 #endif
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
 #ifdef BUTTON_PIN
   return BUTTON_STATE_ACTIVE == gpio_get_pin_level(BUTTON_PIN);
 #else
@@ -227,33 +233,185 @@ int board_uart_write(void const * buf, int len)
 }
 
 #else // ! defined(UART_SERCOM)
-static void uart_init(void)
-{
 
+static void uart_init(void) {
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
+
 #endif
 
-#if CFG_TUSB_OS  == OPT_OS_NONE
+#if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+static void max3421_init(void) {
+  //------------- SPI Init -------------//
+  uint32_t const baudrate = 4000000u;
+
+  // Enable the APB clock for SERCOM
+  PM->APBCMASK.reg |= 1u << (PM_APBCMASK_SERCOM0_Pos + MAX3421_SERCOM_ID);
+
+  // Configure GCLK for SERCOM
+//  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_SERCOM4_CORE | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val+MAX3421_SERCOM_ID) |
+      GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+  while (GCLK->STATUS.bit.SYNCBUSY);
+
+  Sercom* sercom = MAX3421_SERCOM;
+
+  // Disable the SPI module
+  sercom->SPI.CTRLA.bit.ENABLE = 0;
+
+  // Reset the SPI module
+  sercom->SPI.CTRLA.bit.SWRST = 1;
+  while (sercom->SPI.SYNCBUSY.bit.SWRST);
+
+  // Set up SPI in master mode, MSB first, SPI mode 0
+  sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
+      SERCOM_SPI_CTRLA_MODE(3);
+
+  sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
+  while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
+
+  // Set the baud rate
+  sercom->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) - 1);
+
+  // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
+  gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_SCK_PIN, MAX3421_SERCOM_FUNCTION);
+
+  gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_MOSI_PIN, MAX3421_SERCOM_FUNCTION);
+
+  gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
+  gpio_set_pin_function(MAX3421_MISO_PIN, MAX3421_SERCOM_FUNCTION);
+
+  // CS pin
+  gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
+  gpio_set_pin_level(MAX3421_CS_PIN, 1);
+
+  // Enable the SPI module
+  sercom->SPI.CTRLA.bit.ENABLE = 1;
+  while (sercom->SPI.SYNCBUSY.bit.ENABLE);
+
+  //------------- External Interrupt -------------//
+
+  // Enable the APB clock for EIC (External Interrupt Controller)
+  PM->APBAMASK.reg |= PM_APBAMASK_EIC;
+
+  // Configure GCLK for EIC
+  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_EIC | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+  while (GCLK->STATUS.bit.SYNCBUSY);
+
+  // Configure PA20 as an input with function A (external interrupt)
+  gpio_set_pin_direction(MAX3421_INTR_PIN, GPIO_DIRECTION_IN);
+  gpio_set_pin_pull_mode(MAX3421_INTR_PIN, GPIO_PULL_UP);
+  gpio_set_pin_function(MAX3421_INTR_PIN, 0);
+
+  // Disable EIC
+  EIC->CTRL.bit.ENABLE = 0;
+  while (EIC->STATUS.bit.SYNCBUSY);
+
+  // Configure EIC to trigger on falling edge
+  uint8_t const sense_shift = MAX3421_INTR_EIC_ID * 4;
+  EIC->CONFIG[0].reg &= ~(7 << sense_shift);
+  EIC->CONFIG[0].reg |= 2 << sense_shift;
+
+  // Enable External Interrupt
+  EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
+
+  // Enable EIC
+  EIC->CTRL.bit.ENABLE = 1;
+  while (EIC->STATUS.bit.SYNCBUSY);
+}
+
+void EIC_Handler(void) {
+  // Clear the interrupt flag
+  EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
+
+  // Call the TinyUSB interrupt handler
+  tuh_int_handler(1);
+}
+
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+
+  if (enabled) {
+    NVIC_EnableIRQ(EIC_IRQn);
+  } else {
+    NVIC_DisableIRQ(EIC_IRQn);
+  }
+}
+
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+  (void) rhport;
+
+  Sercom* sercom = MAX3421_SERCOM;
+
+  size_t count = 0;
+  while (count < tx_len || count < rx_len) {
+    // Wait for the transmit buffer to be empty
+    while (!sercom->SPI.INTFLAG.bit.DRE);
+
+    // Write data to be transmitted
+    uint8_t data = 0x00;
+    if (count < tx_len) {
+      data = tx_buf[count];
+    }
+
+    sercom->SPI.DATA.reg = (uint32_t) data;
+
+    // Wait for the receive buffer to be filled
+    while (!sercom->SPI.INTFLAG.bit.RXC);
+
+    // Read received data
+    data = (uint8_t) sercom->SPI.DATA.reg;
+    if (count < rx_len) {
+      rx_buf[count] = data;
+    }
+
+    count++;
+  }
+
+  // wait for bus idle and clear flags
+  while (!(sercom->SPI.INTFLAG.reg & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE)));
+  sercom->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE;
+
+  return true;
+}
+
+#endif
+
+
 #endif
diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake
index 07186934a..ffbf687a1 100644
--- a/hw/bsp/samd21/family.cmake
+++ b/hw/bsp/samd21/family.cmake
@@ -94,6 +94,7 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_SAMD21 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/microchip/samd/dcd_samd.c
+    ${TOP}/src/portable/analog/max3421/hcd_max3421.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/samd51/boards/metro_m4_express/board.h b/hw/bsp/samd51/boards/metro_m4_express/board.h
index aa6bdd0c8..b3b80db89 100644
--- a/hw/bsp/samd51/boards/metro_m4_express/board.h
+++ b/hw/bsp/samd51/boards/metro_m4_express/board.h
@@ -44,16 +44,20 @@
 #define UART_RX_PIN           22
 
 // SPI for USB host shield
-#define MAX3421_SERCOM_ID 2  // SERCOM2
-#define MAX3421_SCK_PIN   13
-#define MAX3421_MOSI_PIN  12
-#define MAX3421_MOSI_PAD  0
-#define MAX3421_MISO_PIN  14
-#define MAX3421_MISO_PAD  2
-#define MAX3421_CS_PIN    18 // D10
+#define MAX3421_SERCOM_ID       2  // SERCOM2
+#define MAX3421_SERCOM_FUNCTION 2  // function C
+
+#define MAX3421_SCK_PIN         13
+#define MAX3421_MOSI_PIN        12
+#define MAX3421_MISO_PIN        14
+#define MAX3421_TX_PAD          0 // MOSI = PAD_0, SCK = PAD_1
+#define MAX3421_RX_PAD          2 // MISO = PAD_2
+
+#define MAX3421_CS_PIN          18 // D10
+
+#define MAX3421_INTR_PIN        20 // D9
+#define MAX3421_INTR_EIC_ID     4  // EIC4
 
-#define MAX3421_INTR_PIN  20 // D9
-#define MAX3421_INTR_EIC_ID 4 // EIC4
 
 #ifdef __cplusplus
  }
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index f9e1718d0..2cf00c7af 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -77,11 +77,10 @@ void USB_3_Handler(void) {
 //--------------------------------------------------------------------+
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-static void max3421_init(void);
-
 #define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID)
 #define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler)
 
+static void max3421_init(void);
 #endif
 
 void board_init(void) {
@@ -223,7 +222,8 @@ static void max3421_init(void) {
   while (sercom->SPI.SYNCBUSY.bit.SWRST);
 
   // Set up SPI in master mode, MSB first, SPI mode 0
-  sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE(3) | SERCOM_SPI_CTRLA_DOPO(MAX3421_MOSI_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_MISO_PAD);
+  sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
+      SERCOM_SPI_CTRLA_MODE(3);
 
   sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
   while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
@@ -234,15 +234,15 @@ static void max3421_init(void) {
   // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
   gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
   gpio_set_pin_pull_mode(MAX3421_SCK_PIN, GPIO_PULL_OFF);
-  gpio_set_pin_function(MAX3421_SCK_PIN, 2);
+  gpio_set_pin_function(MAX3421_SCK_PIN, MAX3421_SERCOM_FUNCTION);
 
   gpio_set_pin_direction(MAX3421_MOSI_PIN, GPIO_DIRECTION_OUT);
   gpio_set_pin_pull_mode(MAX3421_MOSI_PIN, GPIO_PULL_OFF);
-  gpio_set_pin_function(MAX3421_MOSI_PIN, 2);
+  gpio_set_pin_function(MAX3421_MOSI_PIN, MAX3421_SERCOM_FUNCTION);
 
   gpio_set_pin_direction(MAX3421_MISO_PIN, GPIO_DIRECTION_IN);
   gpio_set_pin_pull_mode(MAX3421_MISO_PIN, GPIO_PULL_OFF);
-  gpio_set_pin_function(MAX3421_MISO_PIN, 2);
+  gpio_set_pin_function(MAX3421_MISO_PIN, MAX3421_SERCOM_FUNCTION);
 
   // CS pin
   gpio_set_pin_direction(MAX3421_CS_PIN, GPIO_DIRECTION_OUT);
@@ -269,7 +269,7 @@ static void max3421_init(void) {
   EIC->CTRLA.bit.ENABLE = 0;
   while (EIC->SYNCBUSY.bit.ENABLE);
 
-  // Configure EXTINT4 (PA20) to trigger on falling edge
+  // Configure EIC to trigger on falling edge
   volatile uint32_t * eic_config;
   uint8_t sense_shift;
   if ( MAX3421_INTR_EIC_ID < 8 ) {
@@ -302,10 +302,11 @@ void MAX3421_EIC_Handler(void) {
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
+  const IRQn_Type irq = EIC_0_IRQn + MAX3421_INTR_EIC_ID;
   if (enabled) {
-    NVIC_EnableIRQ(EIC_4_IRQn);
+    NVIC_EnableIRQ(irq);
   } else {
-    NVIC_DisableIRQ(EIC_4_IRQn);
+    NVIC_DisableIRQ(irq);
   }
 }
 

From ab9585401b9964407cbf2bc7bffdf762353817f9 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 11 Sep 2023 11:35:51 +0700
Subject: [PATCH 2044/2085] wrap up build cmake & make support for max3421, to
 enable the Host driver, 'MAX3421_HOST=1' must be added as part of make/cmake
 command

---
 .idea/cmake.xml                               |  6 ++--
 .idea/runConfigurations/kl25.xml              |  2 +-
 .idea/runConfigurations/lpc1857.xml           |  2 +-
 .idea/runConfigurations/lpc4088.xml           |  2 +-
 .idea/runConfigurations/lpc54628.xml          | 10 ++++++
 .idea/runConfigurations/lpc55s69.xml          | 10 ++++++
 .idea/runConfigurations/mcx947.xml            |  2 +-
 .idea/runConfigurations/nrf52840.xml          |  2 +-
 .idea/runConfigurations/nrf5340.xml           |  2 +-
 .idea/runConfigurations/ra4m1.xml             |  2 +-
 .idea/runConfigurations/ra6m1.xml             |  2 +-
 .idea/runConfigurations/ra6m5.xml             |  2 +-
 .idea/runConfigurations/rt1010.xml            |  2 +-
 .idea/runConfigurations/rt1060.xml            |  2 +-
 .idea/runConfigurations/samd21g18.xml         | 10 ++++++
 .idea/runConfigurations/samd51j19.xml         | 10 ++++++
 .idea/runConfigurations/stlink.xml            |  2 +-
 .idea/runConfigurations/stm32g474.xml         |  2 +-
 .idea/runConfigurations/stm32h743.xml         |  2 +-
 .idea/runConfigurations/uno_r4.xml            |  2 +-
 examples/dual/host_hid_to_device_cdc/only.txt |  1 +
 examples/host/bare_api/only.txt               |  1 +
 examples/host/cdc_msc_hid/only.txt            |  1 +
 examples/host/cdc_msc_hid/src/tusb_config.h   |  3 --
 examples/host/hid_controller/only.txt         |  1 +
 examples/host/msc_file_explorer/only.txt      |  1 +
 .../host/msc_file_explorer/src/tusb_config.h  |  3 --
 examples/make.mk                              | 13 ++++----
 examples/rules.mk                             |  2 +-
 hw/bsp/family_support.cmake                   | 14 ++++++++
 hw/bsp/nrf/family.cmake                       |  1 -
 hw/bsp/samd21/family.cmake                    |  1 -
 hw/bsp/samd21/family.mk                       | 32 +++++++++----------
 hw/bsp/samd51/family.cmake                    |  1 -
 34 files changed, 101 insertions(+), 50 deletions(-)
 create mode 100644 .idea/runConfigurations/lpc54628.xml
 create mode 100644 .idea/runConfigurations/lpc55s69.xml
 create mode 100644 .idea/runConfigurations/samd21g18.xml
 create mode 100644 .idea/runConfigurations/samd51j19.xml

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 8d19b7624..89ec1066c 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -33,7 +33,7 @@
       <configuration PROFILE_NAME="lpc54628" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso54628 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="lpc55s69" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=lpcxpresso55s69 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="mcxn947" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=mcxn947brk -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="feather_nrf52840_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_nrf52840_express -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="feather_nrf52840_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_nrf52840_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="pca10095" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10095 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
       <configuration PROFILE_NAME="stm32g0b1nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32g0b1nucleo" />
@@ -53,8 +53,8 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
-      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT" />
-      <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/.idea/runConfigurations/kl25.xml b/.idea/runConfigurations/kl25.xml
index a08c20d44..66f8ea684 100644
--- a/.idea/runConfigurations/kl25.xml
+++ b/.idea/runConfigurations/kl25.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MKL25Z128xxx4&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="kl25" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MKL25Z128xxx4&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/lpc1857.xml b/.idea/runConfigurations/lpc1857.xml
index 7525f51f7..f7d4ba402 100644
--- a/.idea/runConfigurations/lpc1857.xml
+++ b/.idea/runConfigurations/lpc1857.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="lpc1857" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc1857&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="lpc1857" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc1857&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/lpc4088.xml b/.idea/runConfigurations/lpc4088.xml
index 7b32b2b85..911876903 100644
--- a/.idea/runConfigurations/lpc4088.xml
+++ b/.idea/runConfigurations/lpc4088.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="lpc4088" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc4088&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="lpc4088" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc4088&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/lpc54628.xml b/.idea/runConfigurations/lpc54628.xml
new file mode 100644
index 000000000..e0047f187
--- /dev/null
+++ b/.idea/runConfigurations/lpc54628.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="lpc54628" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;LPC54628J512&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/lpc55s69.xml b/.idea/runConfigurations/lpc55s69.xml
new file mode 100644
index 000000000..d5e9b117a
--- /dev/null
+++ b/.idea/runConfigurations/lpc55s69.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="lpc55s69" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;lpc55s69&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/mcx947.xml b/.idea/runConfigurations/mcx947.xml
index 77dec59f8..31e5c27dd 100644
--- a/.idea/runConfigurations/mcx947.xml
+++ b/.idea/runConfigurations/mcx947.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="mcx947" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MCXN947_M33_0&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/mcx/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/nrf52840.xml b/.idea/runConfigurations/nrf52840.xml
index 2f3f1876a..3ffa16385 100644
--- a/.idea/runConfigurations/nrf52840.xml
+++ b/.idea/runConfigurations/nrf52840.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="nrf52840" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;nrf52840_xxaa&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="msc_file_explorer" TARGET_NAME="msc_file_explorer" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="msc_file_explorer" RUN_TARGET_NAME="msc_file_explorer">
+  <configuration default="false" name="nrf52840" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-select usb=752001685 -device &quot;nrf52840_xxaa&quot; -if swd -speed 8000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/nrf5340.xml b/.idea/runConfigurations/nrf5340.xml
index 98fe39d80..2f8009444 100644
--- a/.idea/runConfigurations/nrf5340.xml
+++ b/.idea/runConfigurations/nrf5340.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="nrf5340" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;nrf5340_xxaa_app&quot; -if swd -speed 16000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="nrf5340" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-select usb=752001685 -device &quot;nrf5340_xxaa_app&quot; -if swd -speed 16000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/ra4m1.xml b/.idea/runConfigurations/ra4m1.xml
index 561b509a2..6135e5cf3 100644
--- a/.idea/runConfigurations/ra4m1.xml
+++ b/.idea/runConfigurations/ra4m1.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra4m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/ra6m1.xml b/.idea/runConfigurations/ra6m1.xml
index 099510c60..0833d43b3 100644
--- a/.idea/runConfigurations/ra6m1.xml
+++ b/.idea/runConfigurations/ra6m1.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra6m1" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M1AD&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/ra6m5.xml b/.idea/runConfigurations/ra6m5.xml
index 0cffac135..606e04e52 100644
--- a/.idea/runConfigurations/ra6m5.xml
+++ b/.idea/runConfigurations/ra6m5.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="ra6m5" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA6M5BH&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/rt1010.xml b/.idea/runConfigurations/rt1010.xml
index 63df076b1..f4f48181c 100644
--- a/.idea/runConfigurations/rt1010.xml
+++ b/.idea/runConfigurations/rt1010.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/imxrt/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rt1010" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1011xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun -jlinkscriptfile $ProjectFileDir$/hw/bsp/imxrt/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="ALWAYS" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/rt1060.xml b/.idea/runConfigurations/rt1060.xml
index 147f197a2..3d740edeb 100644
--- a/.idea/runConfigurations/rt1060.xml
+++ b/.idea/runConfigurations/rt1060.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="rt1060" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="rt1060" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;MIMXRT1062xxx5A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/samd21g18.xml b/.idea/runConfigurations/samd21g18.xml
new file mode 100644
index 000000000..9a1e65563
--- /dev/null
+++ b/.idea/runConfigurations/samd21g18.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="samd21g18" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;ATSAMD21G18&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/samd51j19.xml b/.idea/runConfigurations/samd51j19.xml
new file mode 100644
index 000000000..74d0e3649
--- /dev/null
+++ b/.idea/runConfigurations/samd51j19.xml
@@ -0,0 +1,10 @@
+<component name="ProjectRunConfigurationManager">
+  <configuration default="false" name="samd51j19" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;ATSAMD51J19A&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+    <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
+      <debugger kind="GDB" isBundled="true" />
+    </custom-gdb-server>
+    <method v="2">
+      <option name="CLION.COMPOUND.BUILD" enabled="true" />
+    </method>
+  </configuration>
+</component>
\ No newline at end of file
diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml
index 7e9166d90..b29b63f1a 100644
--- a/.idea/runConfigurations/stlink.xml
+++ b/.idea/runConfigurations/stlink.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-p 62847 -cp &quot;/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.0.600.202301161003/tools/bin&quot; --frequency 24000 --swd" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="stlink" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-p 62847 -cp &quot;/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.linux64_2.0.600.202301161003/tools/bin&quot; --frequency 24000 --swd" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::62847" executable="/opt/st/stm32cubeide_1.12.1/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.linux64_2.0.500.202301161003/tools/bin/ST-LINK_gdbserver" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/stm32g474.xml b/.idea/runConfigurations/stm32g474.xml
index 2e4c4b82a..a7267fe90 100644
--- a/.idea/runConfigurations/stm32g474.xml
+++ b/.idea/runConfigurations/stm32g474.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="stm32g474" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32g474re&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/stm32h743.xml b/.idea/runConfigurations/stm32h743.xml
index f0ab6e9e7..9cd142de0 100644
--- a/.idea/runConfigurations/stm32h743.xml
+++ b/.idea/runConfigurations/stm32h743.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="stm32h743" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32h743xi&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="stm32h743" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;stm32h743xi&quot; -if swd -speed 50000 -port 25321 -nogui -singlerun" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/.idea/runConfigurations/uno_r4.xml b/.idea/runConfigurations/uno_r4.xml
index e9e1ebb8d..75eb3df4d 100644
--- a/.idea/runConfigurations/uno_r4.xml
+++ b/.idea/runConfigurations/uno_r4.xml
@@ -1,5 +1,5 @@
 <component name="ProjectRunConfigurationManager">
-  <configuration default="false" name="uno_r4" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 20000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="rp2040" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
+  <configuration default="false" name="uno_r4" type="com.jetbrains.cidr.embedded.customgdbserver.type" factoryName="com.jetbrains.cidr.embedded.customgdbserver.factory" PROGRAM_PARAMS="-device &quot;R7FA4M1AB&quot; -if swd -speed 20000 -port 25321 -nogui -singlerun -jlinkscriptfile $PROJECT_DIR$/hw/bsp/ra/debug.jlinkscript" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" EMULATE_TERMINAL="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="tinyusb_examples" TARGET_NAME="cdc_msc" CONFIG_NAME="feather_nrf52840_express" version="1" RUN_TARGET_PROJECT_NAME="tinyusb_examples" RUN_TARGET_NAME="cdc_msc">
     <custom-gdb-server version="1" gdb-connect="tcp::25321" executable="/usr/bin/JLinkGDBServer" warmup-ms="0" download-type="UPDATED_ONLY" reset-cmd="monitor reset" reset-type="AFTER_DOWNLOAD">
       <debugger kind="GDB" isBundled="true" />
     </custom-gdb-server>
diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt
index a3b567f9a..cfc87eb4e 100644
--- a/examples/dual/host_hid_to_device_cdc/only.txt
+++ b/examples/dual/host_hid_to_device_cdc/only.txt
@@ -3,3 +3,4 @@ board:mimxrt1064_evk
 board:mcb1800
 mcu:RP2040
 mcu:ra6m5
+mcu:MAX3421
diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index f8aa2186f..3837ac8a2 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -10,3 +10,4 @@ mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
 mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index f8aa2186f..3837ac8a2 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -10,3 +10,4 @@ mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
 mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h
index 8d3ef8891..c8e9138e3 100644
--- a/examples/host/cdc_msc_hid/src/tusb_config.h
+++ b/examples/host/cdc_msc_hid/src/tusb_config.h
@@ -38,9 +38,6 @@
   // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
   #define CFG_TUH_RPI_PIO_USB   0
   #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
-//#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
-//  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
-//  #define CFG_TUH_MAX3421      1
 #endif
 
 // RHPort number used for host can be defined by board.mk, default to port 0
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index f8aa2186f..3837ac8a2 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -10,3 +10,4 @@ mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
 mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt
index f8aa2186f..3837ac8a2 100644
--- a/examples/host/msc_file_explorer/only.txt
+++ b/examples/host/msc_file_explorer/only.txt
@@ -10,3 +10,4 @@ mcu:RP2040
 mcu:MSP432E4
 mcu:RX65X
 mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h
index e6186ba46..b4ccd8223 100644
--- a/examples/host/msc_file_explorer/src/tusb_config.h
+++ b/examples/host/msc_file_explorer/src/tusb_config.h
@@ -38,9 +38,6 @@
   // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
   #define CFG_TUH_RPI_PIO_USB   0
   #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
-//#elif CFG_TUSB_MCU == OPT_MCU_NRF5X
-//  // Use external USB controller (via SPI) MAX3421E (aka usb host shield)
-//  #define CFG_TUH_MAX3421      1
 #endif
 
 
diff --git a/examples/make.mk b/examples/make.mk
index a590e34f7..8fe4a3486 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -73,7 +73,6 @@ ifeq ($(FAMILY),)
 else
   # Include Family and Board specific defs
   include $(TOP)/$(FAMILY_PATH)/family.mk
-
   SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(FAMILY_PATH)/*.c))
 endif
 
@@ -84,9 +83,6 @@ CROSS_COMPILE ?= arm-none-eabi-
 
 ifeq ($(TOOLCHAIN),iar)
 CC := iccarm
-endif
-
-ifeq ($(CC),iccarm)
 USE_IAR = 1
 endif
 
@@ -105,13 +101,12 @@ endif
 #-------------- Source files and compiler flags --------------
 # tinyusb makefile
 include $(TOP)/src/tinyusb.mk
+SRC_C += $(TINYUSB_SRC_C)
 
 # Include all source C in family & board folder
 SRC_C += hw/bsp/board.c
 SRC_C += $(subst $(TOP)/,,$(wildcard $(TOP)/$(BOARD_PATH)/*.c))
 
-SRC_C += $(TINYUSB_SRC_C)
-
 INC += \
   $(TOP)/$(FAMILY_PATH) \
   $(TOP)/src \
@@ -119,6 +114,12 @@ INC += \
 BOARD_UPPER = $(subst a,A,$(subst b,B,$(subst c,C,$(subst d,D,$(subst e,E,$(subst f,F,$(subst g,G,$(subst h,H,$(subst i,I,$(subst j,J,$(subst k,K,$(subst l,L,$(subst m,M,$(subst n,N,$(subst o,O,$(subst p,P,$(subst q,Q,$(subst r,R,$(subst s,S,$(subst t,T,$(subst u,U,$(subst v,V,$(subst w,W,$(subst x,X,$(subst y,Y,$(subst z,Z,$(subst -,_,$(BOARD))))))))))))))))))))))))))))
 CFLAGS += -DBOARD_$(BOARD_UPPER)
 
+# use max3421 as host controller
+ifeq (${MAX3421_HOST},1)
+  SRC_C += src/portable/analog/max3421/hcd_max3421.c
+  CFLAGS += -DCFG_TUH_MAX3421=1
+endif
+
 # Log level is mapped to TUSB DEBUG option
 ifneq ($(LOG),)
   CMAKE_DEFSYM +=	-DLOG=$(LOG)
diff --git a/examples/rules.mk b/examples/rules.mk
index 44d6b84c8..227849a18 100644
--- a/examples/rules.mk
+++ b/examples/rules.mk
@@ -72,7 +72,7 @@ endif
 # get depenecies
 .PHONY: get-deps
 get-deps:
-	$(PYTHON) $(TOP)/tools/get_deps.py $(DEPS_SUBMODULES)
+	$(PYTHON) $(TOP)/tools/get_deps.py ${FAMILY}
 
 .PHONY: size
 size: $(BUILD)/$(PROJECT).elf
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 1cbcfb2a7..642282b0e 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -253,6 +253,15 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS)
     # link tinyusb with freeRTOS kernel
     target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel)
   endif ()
+
+  # use max3421 as host controller
+  if (MAX3421_HOST STREQUAL "1")
+    target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUH_MAX3421=1)
+    target_sources(${TARGET}-tinyusb PUBLIC
+      ${TOP}/src/portable/analog/max3421/hcd_max3421.c
+      )
+  endif ()
+
 endfunction()
 
 
@@ -438,5 +447,10 @@ if (NOT FAMILY_MCUS)
   set(FAMILY_MCUS ${FAMILY})
 endif()
 
+# if use max3421 as host controller, expand FAMILY_MCUS to include max3421
+if (MAX3421_HOST STREQUAL "1")
+  set(FAMILY_MCUS ${FAMILY_MCUS} MAX3421)
+endif ()
+
 # save it in case of re-inclusion
 set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "")
diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake
index ff6b882ce..99d9ac6dd 100644
--- a/hw/bsp/nrf/family.cmake
+++ b/hw/bsp/nrf/family.cmake
@@ -124,7 +124,6 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c
-    ${TOP}/src/portable/analog/max3421/hcd_max3421.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake
index ffbf687a1..07186934a 100644
--- a/hw/bsp/samd21/family.cmake
+++ b/hw/bsp/samd21/family.cmake
@@ -94,7 +94,6 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_SAMD21 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/microchip/samd/dcd_samd.c
-    ${TOP}/src/portable/analog/max3421/hcd_max3421.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 
diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk
index 49a1a781a..79c63812d 100644
--- a/hw/bsp/samd21/family.mk
+++ b/hw/bsp/samd21/family.mk
@@ -1,5 +1,5 @@
 UF2_FAMILY_ID = 0x68ed2b88
-DEPS_SUBMODULES += hw/mcu/microchip
+SDK_DIR = hw/mcu/microchip/samd21
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= cortex-m0plus
@@ -18,24 +18,24 @@ CFLAGS_SKIP += -Wcast-qual
 
 SRC_C += \
 	src/portable/microchip/samd/dcd_samd.c \
-	hw/mcu/microchip/samd21/gcc/gcc/startup_samd21.c \
-	hw/mcu/microchip/samd21/gcc/system_samd21.c \
-	hw/mcu/microchip/samd21/hpl/gclk/hpl_gclk.c \
-	hw/mcu/microchip/samd21/hpl/pm/hpl_pm.c \
-	hw/mcu/microchip/samd21/hpl/sysctrl/hpl_sysctrl.c \
-	hw/mcu/microchip/samd21/hal/src/hal_atomic.c
+	${SDK_DIR}/gcc/gcc/startup_samd21.c \
+	${SDK_DIR}/gcc/system_samd21.c \
+	${SDK_DIR}/hpl/gclk/hpl_gclk.c \
+	${SDK_DIR}/hpl/pm/hpl_pm.c \
+	${SDK_DIR}/hpl/sysctrl/hpl_sysctrl.c \
+	${SDK_DIR}/hal/src/hal_atomic.c
 
 INC += \
 	$(TOP)/$(BOARD_PATH) \
-	$(TOP)/hw/mcu/microchip/samd21/ \
-	$(TOP)/hw/mcu/microchip/samd21/config \
-	$(TOP)/hw/mcu/microchip/samd21/include \
-	$(TOP)/hw/mcu/microchip/samd21/hal/include \
-	$(TOP)/hw/mcu/microchip/samd21/hal/utils/include \
-	$(TOP)/hw/mcu/microchip/samd21/hpl/pm/ \
-	$(TOP)/hw/mcu/microchip/samd21/hpl/port \
-	$(TOP)/hw/mcu/microchip/samd21/hri \
-	$(TOP)/hw/mcu/microchip/samd21/CMSIS/Include
+	$(TOP)/${SDK_DIR}/ \
+	$(TOP)/${SDK_DIR}/config \
+	$(TOP)/${SDK_DIR}/include \
+	$(TOP)/${SDK_DIR}/hal/include \
+	$(TOP)/${SDK_DIR}/hal/utils/include \
+	$(TOP)/${SDK_DIR}/hpl/pm/ \
+	$(TOP)/${SDK_DIR}/hpl/port \
+	$(TOP)/${SDK_DIR}/hri \
+	$(TOP)/${SDK_DIR}/CMSIS/Include
 
 # flash using bossac at least version 1.8
 # can be found in arduino15/packages/arduino/tools/bossac/
diff --git a/hw/bsp/samd51/family.cmake b/hw/bsp/samd51/family.cmake
index 1dce483fd..fa9586066 100644
--- a/hw/bsp/samd51/family.cmake
+++ b/hw/bsp/samd51/family.cmake
@@ -93,7 +93,6 @@ function(family_configure_example TARGET RTOS)
   family_add_tinyusb(${TARGET} OPT_MCU_SAMD51 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/microchip/samd/dcd_samd.c
-    ${TOP}/src/portable/analog/max3421/hcd_max3421.c
     )
   target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
 

From 1eb0cb0c65077607944665013d4c60f8c8512ec5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 11 Sep 2023 15:45:26 +0700
Subject: [PATCH 2045/2085] update readme to include max3421 support

---
 .github/workflows/build_arm.yml                        | 1 -
 .github/workflows/cmake_arm.yml                        | 1 +
 README.rst                                             | 8 ++++++--
 hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake | 3 +++
 hw/bsp/nrf/boards/feather_nrf52840_express/board.mk    | 3 +++
 5 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 70385bc1b..975f351a0 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -38,7 +38,6 @@ jobs:
         - 'lpc11 lpc13 lpc15 lpc17'
         - 'lpc51 lpc54'
         - 'mm32 msp432e4'
-        - 'nrf'
         - 'samd11 same5x saml2x'
         - 'stm32f2 stm32f3'
         - 'stm32l0 stm32u5 stm32wb'
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index e3a00f9c5..4b788a213 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -38,6 +38,7 @@ jobs:
           - 'lpc18 lpc40 lpc43'
           - 'lpc55'
           - 'mcx'
+          - 'nrf'
           - 'ra'
           - 'rp2040'
           - 'samd21'
diff --git a/README.rst b/README.rst
index d72cdb149..aef310b98 100644
--- a/README.rst
+++ b/README.rst
@@ -33,6 +33,7 @@ Supported MCUs
 The stack supports the following MCUs:
 
 - **Allwinner:** F1C100s/F1C200s
+- **Analog:** MAX3421e (aka Arduino usb host shield)
 - **Broadcom:** BCM2837, BCM2711
 - **Dialog:** DA1469x
 - **Espressif:** ESP32-S2, ESP32-S3
@@ -46,12 +47,13 @@ The stack supports the following MCUs:
   - iMX RT Series: RT10xx, RT11xx
   - Kinetis: KL25, K32L2
   - LPC Series: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55
+  - MCX: N9x
 
 - **Raspberry Pi:** RP2040
 - **Renesas:**
 
-  - RX Series: 63N, 65N, 72N
-  - RA Series: RA4M1, RA4M3
+  - RX Series: 63n, 65n, 72n
+  - RA Series: 4m1, 4m3, 6m1, 6m5
 
 - **Silabs:** EFM32GG
 - **Sony:** CXD56
@@ -87,6 +89,8 @@ Host Stack
 
 - Human Interface Device (HID): Keyboard, Mouse, Generic
 - Mass Storage Class (MSC)
+- Communication Device Class: CDC-ACM
+- Vendor serial over USB: FTDI, CP210x
 - Hub with multiple-level support
 
 Similar to the Device Stack, if you have a special requirement, `usbh_app_driver_get_cb()` can be used to write your own class driver without modifying the stack.
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
index 78ed98225..ce6da8b43 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
@@ -2,5 +2,8 @@ set(MCU_VARIANT nrf52840)
 #set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
 set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
+# enable max3421 host driver for this board
+set(MAX3421_HOST 1)
+
 function(update_board TARGET)
 endfunction()
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk b/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
index b80807963..1f3772caf 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
@@ -1,6 +1,9 @@
 MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
+# enable max3421 host driver for this board
+#MAX3421_HOST = 1
+
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
 

From f55052b61f548f0f28ec8c1b9b706f34424c58d1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 11 Sep 2023 16:44:06 +0700
Subject: [PATCH 2046/2085] enable max3421 host for feather nrf52840 with
 makefile

---
 .../boards/feather_nrf52840_express/board.mk  |  2 +-
 hw/bsp/nrf/family.mk                          | 26 +++++++++++--------
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk b/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
index 1f3772caf..488f07b82 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.mk
@@ -2,7 +2,7 @@ MCU_VARIANT = nrf52840
 CFLAGS += -DNRF52840_XXAA
 
 # enable max3421 host driver for this board
-#MAX3421_HOST = 1
+MAX3421_HOST = 1
 
 # All source paths should be relative to the top level.
 LD_FILE = hw/bsp/nrf/linker/nrf52840_s140_v6.ld
diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk
index cdcfe39bd..4b53b9a4f 100644
--- a/hw/bsp/nrf/family.mk
+++ b/hw/bsp/nrf/family.mk
@@ -1,5 +1,6 @@
 UF2_FAMILY_ID = 0xADA52840
-DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/nordic/nrfx
+
+NRFX_DIR = hw/mcu/nordic/nrfx
 
 include $(TOP)/$(BOARD_PATH)/board.mk
 
@@ -14,24 +15,27 @@ CFLAGS += \
 # suppress warning caused by vendor mcu driver
 CFLAGS += -Wno-error=undef -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=cast-qual -Wno-error=redundant-decls
 
-LDFLAGS += -L$(TOP)/hw/mcu/nordic/nrfx/mdk
+LDFLAGS += -L$(TOP)/${NRFX_DIR}/mdk
 
 SRC_C += \
   src/portable/nordic/nrf5x/dcd_nrf5x.c \
-  hw/mcu/nordic/nrfx/drivers/src/nrfx_power.c \
-  hw/mcu/nordic/nrfx/drivers/src/nrfx_uarte.c \
-  hw/mcu/nordic/nrfx/mdk/system_$(MCU_VARIANT).c
+	${NRFX_DIR}/helpers/nrfx_flag32_allocator.c \
+	${NRFX_DIR}/drivers/src/nrfx_gpiote.c \
+  ${NRFX_DIR}/drivers/src/nrfx_power.c \
+  ${NRFX_DIR}/drivers/src/nrfx_spim.c \
+  ${NRFX_DIR}/drivers/src/nrfx_uarte.c \
+  ${NRFX_DIR}/mdk/system_$(MCU_VARIANT).c
 
 INC += \
   $(TOP)/$(BOARD_PATH) \
   $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
-  $(TOP)/hw/mcu/nordic/nrfx \
-  $(TOP)/hw/mcu/nordic/nrfx/mdk \
-  $(TOP)/hw/mcu/nordic/nrfx/hal \
-  $(TOP)/hw/mcu/nordic/nrfx/drivers/include \
-  $(TOP)/hw/mcu/nordic/nrfx/drivers/src \
+  $(TOP)/${NRFX_DIR} \
+  $(TOP)/${NRFX_DIR}/mdk \
+  $(TOP)/${NRFX_DIR}/hal \
+  $(TOP)/${NRFX_DIR}/drivers/include \
+  $(TOP)/${NRFX_DIR}/drivers/src \
 
-SRC_S += hw/mcu/nordic/nrfx/mdk/gcc_startup_$(MCU_VARIANT).S
+SRC_S += ${NRFX_DIR}/mdk/gcc_startup_$(MCU_VARIANT).S
 
 ASFLAGS += -D__HEAP_SIZE=0
 

From 81cd9951080181234f20d81c831ca0595d499577 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 18 Sep 2023 22:15:31 +0700
Subject: [PATCH 2047/2085] add default CFG_TUH_MAX3421 = 0, default spi speed
 for samd21/samd51 to 12Mhz

---
 hw/bsp/samd21/family.c                    |  3 ++-
 hw/bsp/samd51/family.c                    | 11 +++++++++--
 src/portable/analog/max3421/hcd_max3421.c |  2 +-
 src/tusb_option.h                         | 22 +++++++++++++---------
 4 files changed, 25 insertions(+), 13 deletions(-)

diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index cfe66b8dc..395155548 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -269,7 +269,8 @@ uint32_t board_millis(void) {
 
 static void max3421_init(void) {
   //------------- SPI Init -------------//
-  uint32_t const baudrate = 4000000u;
+  // MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz
+  uint32_t const baudrate = 12000000u;
 
   // Enable the APB clock for SERCOM
   PM->APBCMASK.reg |= 1u << (PM_APBCMASK_SERCOM0_Pos + MAX3421_SERCOM_ID);
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 2cf00c7af..c1b914a02 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -183,7 +183,9 @@ uint32_t board_millis(void) {
 
 static void max3421_init(void) {
   //------------- SPI Init -------------//
-  uint32_t const baudrate = 4000000u;
+
+  // MAX3421E max SPI clock is 26MHz however SAMD can only work reliably at 12 Mhz
+  uint32_t const baudrate = 12000000u;
 
   struct {
     volatile uint32_t *mck_apb;
@@ -229,7 +231,12 @@ static void max3421_init(void) {
   while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
 
   // Set the baud rate
-  sercom->SPI.BAUD.reg = (uint8_t) (SystemCoreClock / (2 * baudrate) - 1);
+  uint8_t baud_reg = (uint8_t) (SystemCoreClock / (2 * baudrate));
+  if (baud_reg) {
+    baud_reg--;
+  }
+
+  sercom->SPI.BAUD.reg = baud_reg;
 
   // Configure PA12 as MOSI (PAD0), PA13 as SCK (PAD1), PA14 as MISO (PAD2), function C (sercom)
   gpio_set_pin_direction(MAX3421_SCK_PIN, GPIO_DIRECTION_OUT);
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 238b518a0..f3f76fd58 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -263,7 +263,7 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is
 
   max3421_spi_lock(rhport, in_isr);
 
-  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 0);
+  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
   _hcd_data.hirq = hirq;
   tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index c72117850..a41f5a07e 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -424,11 +424,11 @@
 //------------- CLASS -------------//
 
 #ifndef CFG_TUH_HUB
-#define CFG_TUH_HUB    0
+  #define CFG_TUH_HUB    0
 #endif
 
 #ifndef CFG_TUH_CDC
-#define CFG_TUH_CDC    0
+  #define CFG_TUH_CDC    0
 #endif
 
 #ifndef CFG_TUH_CDC_FTDI
@@ -442,34 +442,38 @@
 #endif
 
 #ifndef CFG_TUH_HID
-#define CFG_TUH_HID    0
+  #define CFG_TUH_HID    0
 #endif
 
 #ifndef CFG_TUH_MIDI
-#define CFG_TUH_MIDI   0
+  #define CFG_TUH_MIDI   0
 #endif
 
 #ifndef CFG_TUH_MSC
-#define CFG_TUH_MSC    0
+  #define CFG_TUH_MSC    0
 #endif
 
 #ifndef CFG_TUH_VENDOR
-#define CFG_TUH_VENDOR 0
+  #define CFG_TUH_VENDOR 0
 #endif
 
 #ifndef CFG_TUH_API_EDPT_XFER
-#define CFG_TUH_API_EDPT_XFER 0
+  #define CFG_TUH_API_EDPT_XFER 0
 #endif
 
 // Enable PIO-USB software host controller
 #ifndef CFG_TUH_RPI_PIO_USB
-#define CFG_TUH_RPI_PIO_USB 0
+  #define CFG_TUH_RPI_PIO_USB 0
 #endif
 
 #ifndef CFG_TUD_RPI_PIO_USB
-#define CFG_TUD_RPI_PIO_USB 0
+  #define CFG_TUD_RPI_PIO_USB 0
 #endif
 
+// MAX3421 Host controller option
+#ifndef CFG_TUH_MAX3421
+  #define CFG_TUH_MAX3421  0
+#endif
 
 //--------------------------------------------------------------------+
 // TypeC Options (Default)

From 71a2e8a36d7c98169359e6320e39bfdf3b84793f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 19 Sep 2023 17:59:38 +0700
Subject: [PATCH 2048/2085] addding cmake support for u5

---
 .idea/cmake.xml                               |   1 +
 hw/bsp/stm32g4/family.cmake                   |  10 +-
 .../stm32u5/boards/stm32u575eval/board.cmake  |  10 +
 hw/bsp/stm32u5/boards/stm32u575eval/board.mk  |   2 +-
 hw/bsp/stm32u5/family.c                       |  11 +
 hw/bsp/stm32u5/family.cmake                   | 216 ++++++++++++++++++
 hw/bsp/stm32u5/family.mk                      |   6 +-
 7 files changed, 244 insertions(+), 12 deletions(-)
 create mode 100644 hw/bsp/stm32u5/boards/stm32u575eval/board.cmake
 create mode 100644 hw/bsp/stm32u5/family.cmake

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 89ec1066c..112449335 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -55,6 +55,7 @@
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
       <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="stm32u5" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575eval" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index 675a96c74..fa7badc02 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -36,10 +36,10 @@ function(add_board_target BOARD_TARGET)
       ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
       ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
@@ -50,11 +50,6 @@ function(add_board_target BOARD_TARGET)
       ${ST_CMSIS}/Include
       ${ST_HAL_DRIVER}/Inc
       )
-    target_compile_options(${BOARD_TARGET} PUBLIC
-      )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      )
-
     update_board(${BOARD_TARGET})
 
     if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
@@ -62,8 +57,7 @@ function(add_board_target BOARD_TARGET)
         "LINKER:--script=${LD_FILE_GNU}"
         -nostartfiles
         # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
+        --specs=nosys.specs --specs=nano.specs
         )
     elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
       target_link_options(${BOARD_TARGET} PUBLIC
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.cmake b/hw/bsp/stm32u5/boards/stm32u575eval/board.cmake
new file mode 100644
index 000000000..57ba85c71
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32u575xx)
+set(JLINK_DEVICE stm32u575ai)
+
+set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32U575xx
+    )
+endfunction()
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
index 19cd2a5b0..a75b2af78 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
@@ -7,4 +7,4 @@ LD_FILE = $(BOARD_PATH)/STM32U575AIIXQ_FLASH.ld
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
 
 # For flash-jlink target
-JLINK_DEVICE = stm32u575
+JLINK_DEVICE = stm32u575ai
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index a30d886aa..1e1b9011e 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -25,7 +25,18 @@
  * This file is part of the TinyUSB stack.
  */
 
+// Suppress warning caused by mcu driver
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wundef"
+#endif
+
 #include "stm32u5xx_hal.h"
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
 #include "bsp/board_api.h"
 #include "board.h"
 
diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake
new file mode 100644
index 000000000..2aa7d392b
--- /dev/null
+++ b/hw/bsp/stm32u5/family.cmake
@@ -0,0 +1,216 @@
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY u5)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32U5 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32G4 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    #${TOP}/src/portable/st/typec/typec_stm32.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
+include_guard()
+
+if (NOT BOARD)
+  message(FATAL_ERROR "BOARD not specified")
+endif ()
+
+set(ST_FAMILY u5)
+set(ST_PREFIX stm32${ST_FAMILY}xx)
+
+set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
+set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
+set(CMSIS_5 ${TOP}/lib/CMSIS_5)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS STM32U5 CACHE INTERNAL "")
+
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (NOT TARGET ${BOARD_TARGET})
+    # Startup & Linker script
+    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+
+    add_library(${BOARD_TARGET} STATIC
+      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+      )
+    target_include_directories(${BOARD_TARGET} PUBLIC
+      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+      ${CMSIS_5}/CMSIS/Core/Include
+      ${ST_CMSIS}/Include
+      ${ST_HAL_DRIVER}/Inc
+      )
+    update_board(${BOARD_TARGET})
+
+    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--script=${LD_FILE_GNU}"
+        -nostartfiles
+        # nanolib
+        --specs=nosys.specs --specs=nano.specs
+        )
+    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+      target_link_options(${BOARD_TARGET} PUBLIC
+        "LINKER:--config=${LD_FILE_IAR}"
+        )
+    endif ()
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32G4 ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
+    #${TOP}/src/portable/st/typec/typec_stm32.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_flash_stlink(${TARGET})
+  family_flash_jlink(${TARGET})
+endfunction()
diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk
index 9174fe96a..902290b90 100644
--- a/hw/bsp/stm32u5/family.mk
+++ b/hw/bsp/stm32u5/family.mk
@@ -20,11 +20,11 @@ SRC_C += \
 	$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
-	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
+	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
 	$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
 
 INC += \

From 8cdcd0fa9d1530c88637e01924a4218f8106fc3a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 19 Sep 2023 18:33:59 +0700
Subject: [PATCH 2049/2085] fix build and add u5 to ci

---
 .github/workflows/build_arm.yml               |   2 +-
 .github/workflows/cmake_arm.yml               |   1 +
 .../stm32u5/FreeRTOSConfig/FreeRTOSConfig.h   | 165 ++++++++++++++++++
 hw/bsp/stm32u5/family.c                       |  46 ++---
 hw/bsp/stm32u5/family.cmake                   | 110 +-----------
 5 files changed, 187 insertions(+), 137 deletions(-)
 create mode 100644 hw/bsp/stm32u5/FreeRTOSConfig/FreeRTOSConfig.h

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 975f351a0..997fb7da9 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -40,7 +40,7 @@ jobs:
         - 'mm32 msp432e4'
         - 'samd11 same5x saml2x'
         - 'stm32f2 stm32f3'
-        - 'stm32l0 stm32u5 stm32wb'
+        - 'stm32l0 stm32wb'
         - 'tm4c123 xmc4000'
     steps:
     - name: Setup Python
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 4b788a213..192bf957a 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -51,6 +51,7 @@ jobs:
           - 'stm32g4'
           - 'stm32h7'
           - 'stm32l4'
+          - 'stm32u5'
     steps:
     - name: Setup Python
       uses: actions/setup-python@v4
diff --git a/hw/bsp/stm32u5/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32u5/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..138fc6ba6
--- /dev/null
+++ b/hw/bsp/stm32u5/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "stm32u5xx.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       4
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index 1e1b9011e..5e4379f9c 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -43,8 +43,7 @@
 //--------------------------------------------------------------------+
 // Forward USB interrupt events to TinyUSB IRQ Handler
 //--------------------------------------------------------------------+
-void OTG_FS_IRQHandler(void)
-{
+void OTG_FS_IRQHandler(void) {
   tud_int_handler(0);
 }
 
@@ -54,8 +53,7 @@ void OTG_FS_IRQHandler(void)
 
 UART_HandleTypeDef UartHandle;
 
-void board_init(void)
-{
+void board_init(void) {
 
   board_clock_init();
 
@@ -69,7 +67,7 @@ void board_init(void)
   __HAL_RCC_GPIOG_CLK_ENABLE();
   __HAL_RCC_GPIOH_CLK_ENABLE();
 
-  UART_CLK_EN();
+      UART_CLK_EN();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -134,8 +132,8 @@ void board_init(void)
   GPIO_InitStruct.Alternate = GPIO_AF10_USB;
   HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
-#if OTG_FS_VBUS_SENSE
-  // Configure VBUS Pin
+#if defined(OTG_FS_VBUS_SENSE) && OTG_FS_VBUS_SENSE
+  // Configure VBUS Pin OTG_FS_VBUS_SENSE
   GPIO_InitStruct.Pin = GPIO_PIN_9;
   GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
@@ -156,57 +154,51 @@ void board_init(void)
   HAL_PWREx_EnableVddUSB();
 
   /* USB_OTG_FS clock enable */
-  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+      __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 }
 
 //--------------------------------------------------------------------+
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t *buf, int len)
-{
-  (void)buf;
-  (void)len;
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
-int board_uart_write(void const *buf, int len)
-{
-  HAL_UART_Transmit(&UartHandle, (uint8_t *)(uintptr_t)buf, len, 0xffff);
+int board_uart_write(void const *buf, int len) {
+  HAL_UART_Transmit(&UartHandle, (uint8_t *) (uintptr_t) buf, len, 0xffff);
   return len;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler(void)
-{
+
+void SysTick_Handler(void) {
   HAL_IncTick();
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
-void HardFault_Handler(void)
-{
+void HardFault_Handler(void) {
   asm("bkpt");
 }
 
 // Required by __libc_init_array in startup code if we are compiling using
 // -nostdlib/-nostartfiles.
-void _init(void)
-{
+void _init(void) {
 }
diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake
index 2aa7d392b..8f9ac1109 100644
--- a/hw/bsp/stm32u5/family.cmake
+++ b/hw/bsp/stm32u5/family.cmake
@@ -92,115 +92,7 @@ function(family_configure_example TARGET RTOS)
     )
 
   # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_STM32G4 ${RTOS})
-  target_sources(${TARGET}-tinyusb PUBLIC
-    ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
-    #${TOP}/src/portable/st/typec/typec_stm32.c
-    )
-  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
-
-  # Link dependencies
-  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
-
-  # Flashing
-  family_flash_stlink(${TARGET})
-  family_flash_jlink(${TARGET})
-endfunction()
-include_guard()
-
-if (NOT BOARD)
-  message(FATAL_ERROR "BOARD not specified")
-endif ()
-
-set(ST_FAMILY u5)
-set(ST_PREFIX stm32${ST_FAMILY}xx)
-
-set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
-set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
-set(CMSIS_5 ${TOP}/lib/CMSIS_5)
-
-# include board specific
-include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
-
-# toolchain set up
-set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
-set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
-
-set(FAMILY_MCUS STM32U5 CACHE INTERNAL "")
-
-
-#------------------------------------
-# BOARD_TARGET
-#------------------------------------
-# only need to be built ONCE for all examples
-function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    # Startup & Linker script
-    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
-    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
-
-    add_library(${BOARD_TARGET} STATIC
-      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-      )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-      ${CMSIS_5}/CMSIS/Core/Include
-      ${ST_CMSIS}/Include
-      ${ST_HAL_DRIVER}/Inc
-      )
-    update_board(${BOARD_TARGET})
-
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_GNU}"
-        -nostartfiles
-        # nanolib
-        --specs=nosys.specs --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
-  endif ()
-endfunction()
-
-
-#------------------------------------
-# Functions
-#------------------------------------
-function(family_configure_example TARGET RTOS)
-  family_configure_common(${TARGET} ${RTOS})
-
-  # Board target
-  add_board_target(board_${BOARD})
-
-  #---------- Port Specific ----------
-  # These files are built for each example since it depends on example's tusb_config.h
-  target_sources(${TARGET} PUBLIC
-    # BSP
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    )
-  target_include_directories(${TARGET} PUBLIC
-    # family, hw, board
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
-    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
-    )
-
-  # Add TinyUSB target and port source
-  family_add_tinyusb(${TARGET} OPT_MCU_STM32G4 ${RTOS})
+  family_add_tinyusb(${TARGET} OPT_MCU_STM32U5 ${RTOS})
   target_sources(${TARGET}-tinyusb PUBLIC
     ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
     #${TOP}/src/portable/st/typec/typec_stm32.c

From b73262be3af8d9716470ae505c1319e7b9169d6b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 19 Sep 2023 18:38:47 +0700
Subject: [PATCH 2050/2085] minor indent

---
 hw/bsp/stm32u5/family.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c
index 5e4379f9c..d8e58d293 100644
--- a/hw/bsp/stm32u5/family.c
+++ b/hw/bsp/stm32u5/family.c
@@ -67,7 +67,7 @@ void board_init(void) {
   __HAL_RCC_GPIOG_CLK_ENABLE();
   __HAL_RCC_GPIOH_CLK_ENABLE();
 
-      UART_CLK_EN();
+  UART_CLK_EN();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
   // 1ms tick timer
@@ -154,7 +154,7 @@ void board_init(void) {
   HAL_PWREx_EnableVddUSB();
 
   /* USB_OTG_FS clock enable */
-      __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+  __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 }
 
 //--------------------------------------------------------------------+

From 9d0251f7a6751a0d998da4fad81a35a043608275 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 19 Sep 2023 15:42:52 +0200
Subject: [PATCH 2051/2085] Fix UAC interleaved copy.

---
 src/class/audio/audio_device.c | 113 +++++++++++++++------------------
 1 file changed, 51 insertions(+), 62 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 1a7ce7870..0e4220f4f 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -631,68 +631,59 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
 // Decoding according to 2.3.1.5 Audio Streams
 
 // Helper function
-static inline uint8_t * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, void * dst, uint8_t * dst_end, uint8_t * src, uint8_t const n_ff_used)
+static inline uint8_t * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, uint8_t * dst, uint8_t * dst_end, uint8_t * src, uint8_t const n_ff_used)
 {
 
-  // This function is an optimized version of
-  //  while((uint8_t *)dst < dst_end)
-  //  {
-  //    memcpy(dst, src, nBytesToCopy);
-  //    dst = (uint8_t *)dst + nBytesToCopy;
-  //    src += nBytesToCopy * n_ff_used;
-  //  }
-
-  // Optimize for fast half word copies
-  typedef struct{
-    uint16_t val;
-  } __attribute((__packed__)) unaligned_uint16_t;
-
-  // Optimize for fast word copies
-  typedef struct{
-    uint32_t val;
-  } __attribute((__packed__)) unaligned_uint32_t;
+  // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
 
   switch (nBytesToCopy)
   {
     case 1:
       while((uint8_t *)dst < dst_end)
       {
-        *(uint8_t *)dst++ = *src;
-        src += n_ff_used;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        src += 2 * (n_ff_used - 1);
       }
       break;
 
     case 2:
       while((uint8_t *)dst < dst_end)
       {
-        *(unaligned_uint16_t*)dst = *(unaligned_uint16_t*)src;
-        dst += 2;
-        src += 2 * n_ff_used;
+        *(uint32_t*)dst = *(uint32_t*)src;
+        src += 4;
+        dst += 4;
+        src += 4 * (n_ff_used - 1);
       }
       break;
 
     case 3:
       while((uint8_t *)dst < dst_end)
       {
-        //        memcpy(dst, src, 3);
-        //        dst = (uint8_t *)dst + 3;
-        //        src += 3 * n_ff_used;
-
-        // TODO: Is there a faster way to copy 3 bytes?
-        *(uint8_t *)dst++ = *src++;
-        *(uint8_t *)dst++ = *src++;
-        *(uint8_t *)dst++ = *src++;
-
-        src += 3 * (n_ff_used - 1);
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        src += 6 * (n_ff_used - 1);
       }
       break;
 
     case 4:
       while((uint8_t *)dst < dst_end)
       {
-        *(unaligned_uint32_t*)dst = *(unaligned_uint32_t*)src;
+        *(uint32_t*)dst++ = *(uint32_t*)src++;
+        src += 4;
         dst += 4;
-        src += 4 * n_ff_used;
+        *(uint32_t*)dst++ = *(uint32_t*)src++;
+        src += 4;
+        dst += 4;
+        src += 8 * (n_ff_used - 1);
       }
       break;
   }
@@ -946,57 +937,55 @@ range [-1, +1)
 // Helper function
 static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, uint8_t * src, uint8_t * src_end, uint8_t * dst, uint8_t const n_ff_used)
 {
-  // Optimize for fast half word copies
-  typedef struct{
-    uint16_t val;
-  } __attribute((__packed__)) unaligned_uint16_t;
-
-  // Optimize for fast word copies
-  typedef struct{
-    uint32_t val;
-  } __attribute((__packed__)) unaligned_uint32_t;
-
+  // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
   switch (nBytesToCopy)
   {
     case 1:
       while(src < src_end)
       {
-        *dst = *src++;
-        dst += n_ff_used;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        dst += 2 * (n_ff_used - 1);
       }
       break;
 
     case 2:
       while(src < src_end)
       {
-        *(unaligned_uint16_t*)dst = *(unaligned_uint16_t*)src;
-        src += 2;
-        dst += 2 * n_ff_used;
+        *(uint32_t*)dst = *(uint32_t*)src;
+        src += 4;
+        dst += 4;
+        dst += 4 * (n_ff_used - 1);
       }
       break;
 
     case 3:
       while(src < src_end)
       {
-        //        memcpy(dst, src, 3);
-        //        src = (uint8_t *)src + 3;
-        //        dst += 3 * n_ff_used;
-
-        // TODO: Is there a faster way to copy 3 bytes?
-        *dst++ = *src++;
-        *dst++ = *src++;
-        *dst++ = *src++;
-
-        dst += 3 * (n_ff_used - 1);
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        *(uint16_t*)dst = *(uint16_t*)src;
+        src += 2;
+        dst += 2;
+        dst += 6 * (n_ff_used - 1);
       }
       break;
 
     case 4:
       while(src < src_end)
       {
-        *(unaligned_uint32_t*)dst = *(unaligned_uint32_t*)src;
+        *(uint32_t*)dst++ = *(uint32_t*)src++;
         src += 4;
-        dst += 4 * n_ff_used;
+        dst += 4;
+        *(uint32_t*)dst++ = *(uint32_t*)src++;
+        src += 4;
+        dst += 4;
+        dst += 8 * (n_ff_used - 1);
       }
       break;
   }

From 6be7f354c26e09a87d1b856b0e237ff82be5963f Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 19 Sep 2023 16:32:49 +0200
Subject: [PATCH 2052/2085] Fix cast-align.

---
 src/class/audio/audio_device.c | 194 +++++++++++++++------------------
 1 file changed, 89 insertions(+), 105 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 0e4220f4f..46fd6dfa9 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -631,64 +631,55 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
 // Decoding according to 2.3.1.5 Audio Streams
 
 // Helper function
-static inline uint8_t * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, uint8_t * dst, uint8_t * dst_end, uint8_t * src, uint8_t const n_ff_used)
+static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, void * dst, const void * dst_end, void * src, uint8_t const n_ff_used)
 {
-
   // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
+  uint16_t * dst16 = dst;
+  uint16_t * src16 = src;
+  const uint16_t * dst_end16 = dst_end;
+  uint32_t * dst32 = dst;
+  uint32_t * src32 = src;
+  const uint32_t * dst_end32 = dst_end;
 
-  switch (nBytesToCopy)
+  if (nBytesToCopy == 1)
   {
-    case 1:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        src += 2 * (n_ff_used - 1);
-      }
-      break;
-
-    case 2:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(uint32_t*)dst = *(uint32_t*)src;
-        src += 4;
-        dst += 4;
-        src += 4 * (n_ff_used - 1);
-      }
-      break;
-
-    case 3:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        src += 6 * (n_ff_used - 1);
-      }
-      break;
-
-    case 4:
-      while((uint8_t *)dst < dst_end)
-      {
-        *(uint32_t*)dst++ = *(uint32_t*)src++;
-        src += 4;
-        dst += 4;
-        *(uint32_t*)dst++ = *(uint32_t*)src++;
-        src += 4;
-        dst += 4;
-        src += 8 * (n_ff_used - 1);
-      }
-      break;
+    while(dst16 < dst_end16)
+    {
+      *dst16++ = *src16++;
+      src16 += n_ff_used - 1;
+    }
+    return src16;
+  }
+  else if (nBytesToCopy == 2)
+  {
+    while(dst32 < dst_end32)
+    {
+      *dst32++ = *src32++;
+      src32 += n_ff_used - 1;
+    }
+    return src32;
+  }
+  else if (nBytesToCopy == 3)
+  {
+    while(dst16 < dst_end16)
+    {
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      src16 += 3 * (n_ff_used - 1);
+    }
+    return src16;
+  }
+  else // nBytesToCopy == 4
+  {
+    while(dst32 < dst_end32)
+    {
+      *dst32++ = *src32++;
+      *dst32++ = *src32++;
+      src32 += 2 * (n_ff_used - 1);
+    }
+    return src32;
   }
-
-  return src;
 }
 
 static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received)
@@ -935,62 +926,55 @@ range [-1, +1)
  * */
 
 // Helper function
-static inline uint8_t * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, uint8_t * src, uint8_t * src_end, uint8_t * dst, uint8_t const n_ff_used)
+static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, void * src, const void * src_end, void * dst, uint8_t const n_ff_used)
 {
   // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
-  switch (nBytesToCopy)
+  uint16_t * dst16 = dst;
+  uint16_t * src16 = src;
+  const uint16_t * src_end16 = src_end;
+  uint32_t * dst32 = dst;
+  uint32_t * src32 = src;
+  const uint32_t * src_end32 = src_end;
+
+  if (nBytesToCopy == 1)
   {
-    case 1:
-      while(src < src_end)
-      {
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        dst += 2 * (n_ff_used - 1);
-      }
-      break;
-
-    case 2:
-      while(src < src_end)
-      {
-        *(uint32_t*)dst = *(uint32_t*)src;
-        src += 4;
-        dst += 4;
-        dst += 4 * (n_ff_used - 1);
-      }
-      break;
-
-    case 3:
-      while(src < src_end)
-      {
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        *(uint16_t*)dst = *(uint16_t*)src;
-        src += 2;
-        dst += 2;
-        dst += 6 * (n_ff_used - 1);
-      }
-      break;
-
-    case 4:
-      while(src < src_end)
-      {
-        *(uint32_t*)dst++ = *(uint32_t*)src++;
-        src += 4;
-        dst += 4;
-        *(uint32_t*)dst++ = *(uint32_t*)src++;
-        src += 4;
-        dst += 4;
-        dst += 8 * (n_ff_used - 1);
-      }
-      break;
+    while(src16 < src_end16)
+    {
+      *dst16++ = *src16++;
+      dst16 += n_ff_used - 1;
+    }
+    return dst16;
+  }
+  else if (nBytesToCopy == 2)
+  {
+    while(src32 < src_end32)
+    {
+      *dst32++ = *src32++;
+      dst32 += n_ff_used - 1;
+    }
+    return dst32;
+  }
+  else if (nBytesToCopy == 3)
+  {
+    while(src16 < src_end16)
+    {
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      *dst16++ = *src16++;
+      dst16 += 3 * (n_ff_used - 1);
+    }
+    return dst16;
+  }
+  else // nBytesToCopy == 4
+  {
+    while(src32 < src_end32)
+    {
+      *dst32++ = *src32++;
+      *dst32++ = *src32++;
+      dst32 += 2 * (n_ff_used - 1);
+    }
+    return dst32;
   }
-
-  return dst;
 }
 
 static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audio)

From a7c136c03f0c4a057f8b49c10ed9cddcecf52879 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 25 Sep 2023 16:53:11 +0700
Subject: [PATCH 2053/2085] adding host/cdc_msc_hid_freertos example

---
 .idea/cmake.xml                               |  19 +-
 examples/device/cdc_msc_freertos/Makefile     |   2 +-
 examples/device/cdc_msc_freertos/src/main.c   |  70 +++-----
 examples/host/bare_api/CMakeLists.txt         |   5 +
 examples/host/cdc_msc_hid/CMakeLists.txt      |   5 +
 .../host/cdc_msc_hid_freertos/CMakeLists.txt  |  36 ++++
 .../cdc_msc_hid_freertos/src/CMakeLists.txt   |   4 +
 examples/host/cdc_msc_hid_freertos/src/main.c | 170 ++++++++++++++++++
 .../cdc_msc_hid_freertos/src/tusb_config.h    | 133 ++++++++++++++
 examples/host/hid_controller/CMakeLists.txt   |   5 +
 .../host/msc_file_explorer/CMakeLists.txt     |   5 +
 examples/make.mk                              |   3 -
 .../boards/adafruit_metro_esp32s2/board.h     |   8 +
 .../boards/espressif_kaluga_1/board.h         |   8 +
 .../boards/espressif_s2_devkitc/board.cmake   |   2 +
 .../boards/espressif_s2_devkitc/board.h       |  45 +++++
 hw/bsp/espressif/boards/family.c              | 130 +++++++++++---
 .../components/tinyusb_src/CMakeLists.txt     |  81 +++++----
 src/host/usbh.c                               |   2 +-
 src/portable/analog/max3421/hcd_max3421.c     |   2 +-
 20 files changed, 623 insertions(+), 112 deletions(-)
 create mode 100644 examples/host/cdc_msc_hid_freertos/CMakeLists.txt
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/main.c
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/tusb_config.h
 create mode 100644 hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake
 create mode 100644 hw/bsp/espressif/boards/espressif_s2_devkitc/board.h

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 89ec1066c..747f0fb58 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -2,23 +2,24 @@
 <project version="4">
   <component name="CMakeSharedSettings">
     <configurations>
-      <configuration PROFILE_NAME="esp32s2" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_saola_1 -DIDF_TARGET=esp32s2">
+      <configuration PROFILE_NAME="esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_saola_1">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
-            <env name="ESPPORT" value="/dev/ttyUSB0" />
-            <env name="IDF_PATH" value="$PROJECT_DIR$/../esp-idf" />
-            <env name="PATH" value="$PROJECT_DIR$/../esp-idf/components/esptool_py/esptool:/home/hathach/code/esp-idf/components/espcoredump:/home/hathach/code/esp-idf/components/partition_table:/home/hathach/code/esp-idf/components/app_update:/home/hathach/.espressif/tools/xtensa-esp-elf-gdb/11.2_20220823/xtensa-esp-elf-gdb/bin:/home/hathach/.espressif/tools/riscv32-esp-elf-gdb/11.2_20220823/riscv32-esp-elf-gdb/bin:/home/hathach/.espressif/tools/xtensa-esp32-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s2-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s2-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s3-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s3-elf/bin:/home/hathach/.espressif/tools/riscv32-esp-elf/esp-2021r2-patch5-8.4.0/riscv32-esp-elf/bin:/home/hathach/.espressif/tools/esp32ulp-elf/2.35_20220830/esp32ulp-elf/bin:/home/hathach/.espressif/tools/openocd-esp32/v0.11.0-esp32-20221026/openocd-esp32/bin:/home/hathach/.espressif/python_env/idf4.4_py3.10_env/bin:/home/hathach/code/esp-idf/tools:/home/hathach/app/riscv-openocd-wch/src:/home/hathach/app/arm-gnu-toolchain-12.2.rel1-x86_64-arm-none-eabi/bin:/home/hathach/.local/bin:/home/hathach/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/opt/SEGGER/JLink:/home/hathach/app/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/10.2.0-1.2.1/.content/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/openocd/*/.content/bin:/home/hathach/ti/msp430-gcc/bin:/home/hathach/ti/MSPFlasher_1.3.20:/home/hathach/ti/uniflash_7.0.0:/home/hathach/app/gcc_8.3.0.202102_gnurx-elf/bin:/home/hathach/app/RFP_CLI_Linux_V31101_x64/linux-x64:/home/hathach/app/fomu-toolchain-linux_x86_64-v1.5.5/bin:/home/hathach/app/nuclei_riscv_newlibc_prebuilt_linux64_2020.08/gcc/bin:/home/hathach/app/riscv32-embecosm-ubuntu2004-gcc11.1.0/bin:/home/hathach/app/cov-analysis-linux64-2019.03/bin:/opt/iarsystems/bxarm/arm/bin:/home/hathach/.local/bin" />
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="esp32s3" ENABLED="false" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm -DIDF_TARGET=esp32s3">
+      <configuration PROFILE_NAME="kaluga" ENABLED="true" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_kaluga_1 -DMAX3421_HOST=1 -DLOG=2">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
+      <configuration PROFILE_NAME="esp32s3" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_s3_devkitm">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
-            <env name="ESPPORT" value="/dev/ttyUSB0" />
-            <env name="IDF_PATH" value="$PROJECT_DIR$/../esp-idf" />
-            <env name="PATH" value="$PROJECT_DIR$/../esp-idf/components/esptool_py/esptool:/home/hathach/code/esp-idf/components/espcoredump:/home/hathach/code/esp-idf/components/partition_table:/home/hathach/code/esp-idf/components/app_update:/home/hathach/.espressif/tools/xtensa-esp-elf-gdb/11.2_20220823/xtensa-esp-elf-gdb/bin:/home/hathach/.espressif/tools/riscv32-esp-elf-gdb/11.2_20220823/riscv32-esp-elf-gdb/bin:/home/hathach/.espressif/tools/xtensa-esp32-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s2-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s2-elf/bin:/home/hathach/.espressif/tools/xtensa-esp32s3-elf/esp-2021r2-patch5-8.4.0/xtensa-esp32s3-elf/bin:/home/hathach/.espressif/tools/riscv32-esp-elf/esp-2021r2-patch5-8.4.0/riscv32-esp-elf/bin:/home/hathach/.espressif/tools/esp32ulp-elf/2.35_20220830/esp32ulp-elf/bin:/home/hathach/.espressif/tools/openocd-esp32/v0.11.0-esp32-20221026/openocd-esp32/bin:/home/hathach/.espressif/python_env/idf4.4_py3.10_env/bin:/home/hathach/code/esp-idf/tools:/home/hathach/app/riscv-openocd-wch/src:/home/hathach/app/arm-gnu-toolchain-12.2.rel1-x86_64-arm-none-eabi/bin:/home/hathach/.local/bin:/home/hathach/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin:/snap/bin:/opt/SEGGER/JLink:/home/hathach/app/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/10.2.0-1.2.1/.content/bin:/home/hathach/.local/xPacks/@xpack-dev-tools/openocd/*/.content/bin:/home/hathach/ti/msp430-gcc/bin:/home/hathach/ti/MSPFlasher_1.3.20:/home/hathach/ti/uniflash_7.0.0:/home/hathach/app/gcc_8.3.0.202102_gnurx-elf/bin:/home/hathach/app/RFP_CLI_Linux_V31101_x64/linux-x64:/home/hathach/app/fomu-toolchain-linux_x86_64-v1.5.5/bin:/home/hathach/app/nuclei_riscv_newlibc_prebuilt_linux64_2020.08/gcc/bin:/home/hathach/app/riscv32-embecosm-ubuntu2004-gcc11.1.0/bin:/home/hathach/app/cov-analysis-linux64-2019.03/bin:/opt/iarsystems/bxarm/arm/bin:/home/hathach/.local/bin" />
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
@@ -53,7 +54,7 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
-      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="metro_m4_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
     </configurations>
   </component>
diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 0bee668b7..3ac62a79c 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -10,7 +10,7 @@ INC += \
 	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
-	$(TOP)/$(FREERTOS_PORTABLE_SRC)
+	$(TOP)/$(FREERTOS_PORTABLE_SRC) \
 
 # Example source
 EXAMPLE_SOURCE = \
diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c
index 0b115a595..1dadc4513 100644
--- a/examples/device/cdc_msc_freertos/src/main.c
+++ b/examples/device/cdc_msc_freertos/src/main.c
@@ -41,6 +41,7 @@
 
   #define USBD_STACK_SIZE     4096
 #else
+
   #include "FreeRTOS.h"
   #include "semphr.h"
   #include "queue.h"
@@ -54,7 +55,7 @@
 #define CDC_STACK_SZIE      configMINIMAL_STACK_SIZE
 
 //--------------------------------------------------------------------+
-// MACRO CONSTANT TYPEDEF PROTYPES
+// MACRO CONSTANT TYPEDEF PROTOTYPES
 //--------------------------------------------------------------------+
 
 /* Blink pattern
@@ -62,7 +63,7 @@
  * - 1000 ms : device mounted
  * - 2500 ms : device is suspended
  */
-enum  {
+enum {
   BLINK_NOT_MOUNTED = 250,
   BLINK_MOUNTED = 1000,
   BLINK_SUSPENDED = 2500,
@@ -81,16 +82,15 @@ StaticTask_t cdc_taskdef;
 
 TimerHandle_t blinky_tm;
 
-void led_blinky_cb(TimerHandle_t xTimer);
-void usb_device_task(void* param);
-void cdc_task(void* params);
+static void led_blinky_cb(TimerHandle_t xTimer);
+static void usb_device_task(void *param);
+void cdc_task(void *params);
 
 //--------------------------------------------------------------------+
 // Main
 //--------------------------------------------------------------------+
 
-int main(void)
-{
+int main(void) {
   board_init();
 
 #if configSUPPORT_STATIC_ALLOCATION
@@ -104,8 +104,8 @@ int main(void)
   xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
 #else
   blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
-  xTaskCreate( usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
-  xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+  xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL);
+  xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL);
 #endif
 
   xTimerStart(blinky_tm, 0);
@@ -119,16 +119,14 @@ int main(void)
 }
 
 #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
-void app_main(void)
-{
+void app_main(void) {
   main();
 }
 #endif
 
 // USB Device Driver task
 // This top level thread process all usb events and invoke callbacks
-void usb_device_task(void* param)
-{
+static void usb_device_task(void *param) {
   (void) param;
 
   // init device stack on configured roothub port
@@ -141,8 +139,7 @@ void usb_device_task(void* param)
   }
 
   // RTOS forever loop
-  while (1)
-  {
+  while (1) {
     // put this thread to waiting state until there is new events
     tud_task();
 
@@ -156,35 +153,28 @@ void usb_device_task(void* param)
 //--------------------------------------------------------------------+
 
 // Invoked when device is mounted
-void tud_mount_cb(void)
-{
+void tud_mount_cb(void) {
   xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
 }
 
 // Invoked when device is unmounted
-void tud_umount_cb(void)
-{
+void tud_umount_cb(void) {
   xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
 }
 
 // Invoked when usb bus is suspended
 // remote_wakeup_en : if host allow us  to perform remote wakeup
 // Within 7ms, device must draw an average of current less than 2.5 mA from bus
-void tud_suspend_cb(bool remote_wakeup_en)
-{
+void tud_suspend_cb(bool remote_wakeup_en) {
   (void) remote_wakeup_en;
   xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_SUSPENDED), 0);
 }
 
 // Invoked when usb bus is resumed
-void tud_resume_cb(void)
-{
-  if (tud_mounted())
-  {
+void tud_resume_cb(void) {
+  if (tud_mounted()) {
     xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_MOUNTED), 0);
-  }
-  else
-  {
+  } else {
     xTimerChangePeriod(blinky_tm, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), 0);
   }
 }
@@ -192,20 +182,17 @@ void tud_resume_cb(void)
 //--------------------------------------------------------------------+
 // USB CDC
 //--------------------------------------------------------------------+
-void cdc_task(void* params)
-{
+void cdc_task(void *params) {
   (void) params;
 
   // RTOS forever loop
-  while ( 1 )
-  {
+  while (1) {
     // connected() check for DTR bit
     // Most but not all terminal client set this when making connection
     // if ( tud_cdc_connected() )
     {
       // There are data available
-      while ( tud_cdc_available() )
-      {
+      while (tud_cdc_available()) {
         uint8_t buf[64];
 
         // read and echo back
@@ -228,32 +215,27 @@ void cdc_task(void* params)
 }
 
 // Invoked when cdc when line state changed e.g connected/disconnected
-void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
-{
+void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) {
   (void) itf;
   (void) rts;
 
   // TODO set some indicator
-  if ( dtr )
-  {
+  if (dtr) {
     // Terminal connected
-  }else
-  {
+  } else {
     // Terminal disconnected
   }
 }
 
 // Invoked when CDC interface received data from host
-void tud_cdc_rx_cb(uint8_t itf)
-{
+void tud_cdc_rx_cb(uint8_t itf) {
   (void) itf;
 }
 
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
-void led_blinky_cb(TimerHandle_t xTimer)
-{
+static void led_blinky_cb(TimerHandle_t xTimer) {
   (void) xTimer;
   static bool led_state = false;
 
diff --git a/examples/host/bare_api/CMakeLists.txt b/examples/host/bare_api/CMakeLists.txt
index 05398b079..76182d6fa 100644
--- a/examples/host/bare_api/CMakeLists.txt
+++ b/examples/host/bare_api/CMakeLists.txt
@@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM)
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/host/cdc_msc_hid/CMakeLists.txt b/examples/host/cdc_msc_hid/CMakeLists.txt
index ad5751705..a7c372a34 100644
--- a/examples/host/cdc_msc_hid/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid/CMakeLists.txt
@@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM)
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/host/cdc_msc_hid_freertos/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/CMakeLists.txt
new file mode 100644
index 000000000..2e95a18e0
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/CMakeLists.txt
@@ -0,0 +1,36 @@
+cmake_minimum_required(VERSION 3.17)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake)
+
+# gets PROJECT name for the example (e.g. <BOARD>-<DIR_NAME>)
+family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR})
+
+project(${PROJECT} C CXX ASM)
+
+# Checks this example is valid for the family and initializes the project
+family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
+
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
+add_executable(${PROJECT})
+
+# Example source
+target_sources(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/cdc_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/hid_app.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_app.c
+  )
+
+# Example include
+target_include_directories(${PROJECT} PUBLIC
+  ${CMAKE_CURRENT_SOURCE_DIR}/src
+  )
+
+# Configure compilation flags and libraries for the example without RTOS.
+# See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
+family_configure_host_example(${PROJECT} freertos)
diff --git a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
new file mode 100644
index 000000000..dd7ec8e58
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
@@ -0,0 +1,4 @@
+# This file is for ESP-IDF only
+idf_component_register(SRCS "hid_app.c" "main.c"
+                    INCLUDE_DIRS "."
+                    REQUIRES boards tinyusb_src)
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
new file mode 100644
index 000000000..e2ddd52eb
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -0,0 +1,170 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  // ESP-IDF need "freertos/" prefix in include path.
+  // CFG_TUSB_OS_INC_PATH should be defined accordingly.
+  #include "freertos/FreeRTOS.h"
+  #include "freertos/semphr.h"
+  #include "freertos/queue.h"
+  #include "freertos/task.h"
+  #include "freertos/timers.h"
+
+  #define USBH_STACK_SIZE     4096
+#else
+  #include "FreeRTOS.h"
+  #include "semphr.h"
+  #include "queue.h"
+  #include "task.h"
+  #include "timers.h"
+
+  // Increase stack size when debug log is enabled
+  #define USBH_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTOTYPES
+//--------------------------------------------------------------------+
+/* Blink pattern
+ * - 250 ms  : device not mounted
+ * - 1000 ms : device mounted
+ * - 2500 ms : device is suspended
+ */
+enum  {
+  BLINK_NOT_MOUNTED = 250,
+  BLINK_MOUNTED = 1000,
+  BLINK_SUSPENDED = 2500,
+};
+
+// static timer & task
+#if configSUPPORT_STATIC_ALLOCATION
+StaticTimer_t blinky_tmdef;
+
+StackType_t  usb_host_stack[USBH_STACK_SIZE];
+StaticTask_t usb_host_taskdef;
+
+//StackType_t  cdc_stack[CDC_STACK_SZIE];
+//StaticTask_t cdc_taskdef;
+#endif
+
+
+TimerHandle_t blinky_tm;
+
+static void led_blinky_cb(TimerHandle_t xTimer);
+static void usb_host_task(void* param);
+
+extern void cdc_app_task(void);
+extern void hid_app_task(void);
+
+/*------------- MAIN -------------*/
+int main(void) {
+  board_init();
+
+  printf("TinyUSB Host CDC MSC HID with FreeRTOS Example\r\n");
+
+#if configSUPPORT_STATIC_ALLOCATION
+  // soft timer for blinky
+  blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
+
+  // Create a task for tinyusb device stack
+  xTaskCreateStatic(usb_host_task, "usbh", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_host_stack, &usb_host_taskdef);
+
+  // Create CDC task
+  //xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+#else
+  blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
+  xTaskCreate( usb_device_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
+  //xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+#endif
+
+  xTimerStart(blinky_tm, 0);
+
+  // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3
+#if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+  vTaskStartScheduler();
+#endif
+
+  return 0;
+}
+
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+void app_main(void) {
+  main();
+}
+#endif
+
+// USB Host task
+// This top level thread process all usb events and invoke callbacks
+static void usb_host_task(void *param) {
+  (void) param;
+
+  // init host stack on configured roothub port
+  tuh_init(BOARD_TUH_RHPORT);
+
+  if (board_init_after_tusb) {
+    board_init_after_tusb();
+  }
+
+  // RTOS forever loop
+  while (1) {
+    // put this thread to waiting state until there is new events
+    tuh_task();
+
+    // following code only run if tuh_task() process at least 1 event
+  }
+}
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+void tuh_mount_cb(uint8_t dev_addr) {
+  // application set-up
+  printf("A device with address %d is mounted\r\n", dev_addr);
+}
+
+void tuh_umount_cb(uint8_t dev_addr) {
+  // application tear-down
+  printf("A device with address %d is unmounted \r\n", dev_addr);
+}
+
+
+//--------------------------------------------------------------------+
+// BLINKING TASK
+//--------------------------------------------------------------------+
+static void led_blinky_cb(TimerHandle_t xTimer) {
+  (void) xTimer;
+  static bool led_state = false;
+
+  board_led_write(led_state);
+  led_state = 1 - led_state; // toggle
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
new file mode 100644
index 000000000..1bed9a9b3
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h
@@ -0,0 +1,133 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _TUSB_CONFIG_H_
+#define _TUSB_CONFIG_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Board Specific Configuration
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+  // change to 1 if using pico-pio-usb as host controller for raspberry rp2040
+  #define CFG_TUH_RPI_PIO_USB   0
+  #define BOARD_TUH_RHPORT      CFG_TUH_RPI_PIO_USB
+#endif
+
+// RHPort number used for host can be defined by board.mk, default to port 0
+#ifndef BOARD_TUH_RHPORT
+#define BOARD_TUH_RHPORT      0
+#endif
+
+// RHPort max operational speed can defined by board.mk
+#ifndef BOARD_TUH_MAX_SPEED
+#define BOARD_TUH_MAX_SPEED   OPT_MODE_DEFAULT_SPEED
+#endif
+
+//--------------------------------------------------------------------
+// COMMON CONFIGURATION
+//--------------------------------------------------------------------
+
+// defined by compiler flags for flexibility
+#ifndef CFG_TUSB_MCU
+#error CFG_TUSB_MCU must be defined
+#endif
+
+#ifndef CFG_TUSB_OS
+#define CFG_TUSB_OS           OPT_OS_FREERTOS
+#endif
+
+// Espressif IDF requires "freertos/" prefix in include path
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+#define CFG_TUSB_OS_INC_PATH  freertos/
+#endif
+
+#ifndef CFG_TUSB_DEBUG
+#define CFG_TUSB_DEBUG        0
+#endif
+
+// Enable Host stack
+#define CFG_TUH_ENABLED       1
+
+// Default is max speed that hardware controller could support with on-chip PHY
+#define CFG_TUH_MAX_SPEED     BOARD_TUH_MAX_SPEED
+
+/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
+ * Tinyusb use follows macros to declare transferring memory so that they can be put
+ * into those specific section.
+ * e.g
+ * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") ))
+ * - CFG_TUSB_MEM_ALIGN   : __attribute__ ((aligned(4)))
+ */
+#ifndef CFG_TUH_MEM_SECTION
+#define CFG_TUH_MEM_SECTION
+#endif
+
+#ifndef CFG_TUH_MEM_ALIGN
+#define CFG_TUH_MEM_ALIGN        __attribute__ ((aligned(4)))
+#endif
+
+//--------------------------------------------------------------------
+// CONFIGURATION
+//--------------------------------------------------------------------
+
+// Size of buffer to hold descriptors and other data used for enumeration
+#define CFG_TUH_ENUMERATION_BUFSIZE 256
+
+#define CFG_TUH_HUB                 1 // number of supported hubs
+#define CFG_TUH_CDC                 1 // CDC ACM
+#define CFG_TUH_CDC_FTDI            1 // FTDI Serial.  FTDI is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_CDC_CP210X          1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API
+#define CFG_TUH_HID                 (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces
+#define CFG_TUH_MSC                 1
+#define CFG_TUH_VENDOR              0
+
+// max device support (excluding hub device): 1 hub typically has 4 ports
+#define CFG_TUH_DEVICE_MAX          (3*CFG_TUH_HUB + 1)
+
+//------------- HID -------------//
+#define CFG_TUH_HID_EPIN_BUFSIZE    64
+#define CFG_TUH_HID_EPOUT_BUFSIZE   64
+
+//------------- CDC -------------//
+
+// Set Line Control state on enumeration/mounted:
+// DTR ( bit 0), RTS (bit 1)
+#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM    0x03
+
+// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t
+// bit rate = 115200, 1 stop bit, no parity, 8 bit data width
+#define CFG_TUH_CDC_LINE_CODING_ON_ENUM   { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 }
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CONFIG_H_ */
diff --git a/examples/host/hid_controller/CMakeLists.txt b/examples/host/hid_controller/CMakeLists.txt
index 3fb630aaa..c1b500dd8 100644
--- a/examples/host/hid_controller/CMakeLists.txt
+++ b/examples/host/hid_controller/CMakeLists.txt
@@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM)
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/host/msc_file_explorer/CMakeLists.txt b/examples/host/msc_file_explorer/CMakeLists.txt
index 1868b632e..1a57c7466 100644
--- a/examples/host/msc_file_explorer/CMakeLists.txt
+++ b/examples/host/msc_file_explorer/CMakeLists.txt
@@ -10,6 +10,11 @@ project(${PROJECT} C CXX ASM)
 # Checks this example is valid for the family and initializes the project
 family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR})
 
+# Espressif has its own cmake build system
+if(FAMILY STREQUAL "espressif")
+  return()
+endif()
+
 add_executable(${PROJECT})
 
 # Example source
diff --git a/examples/make.mk b/examples/make.mk
index 8fe4a3486..448d7883d 100644
--- a/examples/make.mk
+++ b/examples/make.mk
@@ -26,9 +26,6 @@ ifeq '$(findstring ;,$(PATH))' ';'
 CMDEXE := 1
 
 # makefile shell commands should use syntax for DOS CMD, not unix sh
-# Unfortunately, SHELL may point to sh or bash, which can't accept DOS syntax.
-# We can't just use sh, because while sh and/or bash shell may be available,
-# many Windows environments won't have utilities like realpath used below, so...
 # Force DOS command shell on Windows.
 SHELL := cmd.exe
 endif
diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
index 2ec80ef47..44ff11aa0 100644
--- a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
+++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h
@@ -36,6 +36,14 @@
 #define BUTTON_PIN            0
 #define BUTTON_STATE_ACTIVE   0
 
+// SPI for USB host shield
+#define MAX3421_SPI_HOST  SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
index 0acb9c439..613e6ae0c 100644
--- a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
+++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h
@@ -37,6 +37,14 @@
 #define BUTTON_PIN            0
 #define BUTTON_STATE_ACTIVE   0
 
+// SPI for USB host shield
+#define MAX3421_SPI_HOST  SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake
new file mode 100644
index 000000000..abbdf7abc
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.cmake
@@ -0,0 +1,2 @@
+# Apply board specific content here
+set(IDF_TARGET "esp32s2")
diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
new file mode 100644
index 000000000..e068efef9
--- /dev/null
+++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h
@@ -0,0 +1,45 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef BOARD_H_
+#define BOARD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+// Note: On the production version (v1.2) WS2812 is connected to GPIO 18,
+// however earlier revision v1.1 WS2812 is connected to GPIO 17
+#define NEOPIXEL_PIN          18
+
+#define BUTTON_PIN            0
+#define BUTTON_STATE_ACTIVE   0
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* BOARD_H_ */
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 8f857fb71..250b7001e 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -45,16 +45,19 @@
 static led_strip_t *strip;
 #endif
 
-//--------------------------------------------------------------------+
-// MACRO TYPEDEF CONSTANT ENUM DECLARATION
-//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+#include "driver/spi_master.h"
+static void max3421_init(void);
+#endif
 
 static void configure_pins(usb_hal_context_t *usb);
 
-// Initialize on-board peripherals : led, button, uart and USB
-void board_init(void)
-{
+//--------------------------------------------------------------------+
+// Implementation
+//--------------------------------------------------------------------+
 
+// Initialize on-board peripherals : led, button, uart and USB
+void board_init(void) {
 #ifdef NEOPIXEL_PIN
   #ifdef NEOPIXEL_POWER_PIN
   gpio_reset_pin(NEOPIXEL_POWER_PIN);
@@ -79,23 +82,27 @@ void board_init(void)
   gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
   gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
 
+#if CFG_TUD_ENABLED
   // USB Controller Hal init
   periph_module_reset(PERIPH_USB_MODULE);
   periph_module_enable(PERIPH_USB_MODULE);
 
   usb_hal_context_t hal = {
-    .use_external_phy = false // use built-in PHY
+      .use_external_phy = false // use built-in PHY
   };
   usb_hal_init(&hal);
   configure_pins(&hal);
+#endif
+
+#if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+  max3421_init();
+#endif
 }
 
-static void configure_pins(usb_hal_context_t *usb)
-{
+static void configure_pins(usb_hal_context_t *usb) {
   /* usb_periph_iopins currently configures USB_OTG as USB Device.
    * Introduce additional parameters in usb_hal_context_t when adding support
-   * for USB Host.
-   */
+   * for USB Host. */
   for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
     if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
       esp_rom_gpio_pad_select_gpio(iopin->pin);
@@ -115,6 +122,7 @@ static void configure_pins(usb_hal_context_t *usb)
       esp_rom_gpio_pad_unhold(iopin->pin);
     }
   }
+
   if (!usb->use_external_phy) {
     gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3);
     gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3);
@@ -122,8 +130,7 @@ static void configure_pins(usb_hal_context_t *usb)
 }
 
 // Turn LED on or off
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
 #ifdef NEOPIXEL_PIN
   strip->set_pixel(strip, 0, (state ? 0x88 : 0x00), 0x00, 0x00);
   strip->refresh(strip, 100);
@@ -132,21 +139,102 @@ void board_led_write(bool state)
 
 // Get the current state of button
 // a '1' means active (pressed), a '0' means inactive.
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   return gpio_get_level(BUTTON_PIN) == BUTTON_STATE_ACTIVE;
 }
 
 // Get characters from UART
-int board_uart_read(uint8_t* buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_read(uint8_t *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
 
 // Send characters to UART
-int board_uart_write(void const * buf, int len)
-{
-  (void) buf; (void) len;
+int board_uart_write(void const *buf, int len) {
+  (void) buf;
+  (void) len;
   return 0;
 }
+
+//--------------------------------------------------------------------+
+// API: SPI transfer with MAX3421E, must be implemented by application
+//--------------------------------------------------------------------+
+#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
+static spi_device_handle_t max3421_spi;
+
+static void IRAM_ATTR max3421_isr_handler(void* arg)
+{
+  (void) arg;
+  //uint32_t gpio_num = (uint32_t) arg;
+  //xQueueSendFromISR(gpio_evt_queue, &gpio_num, NULL);
+  tuh_int_handler(1);
+}
+
+static void max3421_init(void) {
+  // CS pin
+  gpio_set_direction(MAX3421_CS_PIN, GPIO_MODE_OUTPUT);
+  gpio_set_level(MAX3421_CS_PIN, 1);
+
+  // SPI
+  spi_bus_config_t buscfg={
+      .miso_io_num = MAX3421_MISO_PIN,
+      .mosi_io_num = MAX3421_MOSI_PIN,
+      .sclk_io_num = MAX3421_SCK_PIN,
+      .quadwp_io_num = -1,
+      .quadhd_io_num = -1,
+      .data4_io_num = -1,
+      .data5_io_num = -1,
+      .data6_io_num = -1,
+      .data7_io_num = -1,
+      .max_transfer_sz = 128
+  };
+  ESP_ERROR_CHECK( spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO) );
+
+  spi_device_interface_config_t max3421_cfg = {
+      .command_bits = 8,
+      .mode = 0,
+      .clock_speed_hz = 4000000, // 26000000
+      .spics_io_num = -1, // manual control CS
+      .queue_size = 1
+  };
+  ESP_ERROR_CHECK( spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi) );
+
+  // Interrupt pin
+//  gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
+//  gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
+//
+//  gpio_install_isr_service(ESP_INTR_FLAG_EDGE);
+//  gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL);
+}
+
+void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
+  (void) rhport;
+  if (enabled) {
+    gpio_intr_enable(MAX3421_INTR_PIN);
+  } else {
+    gpio_intr_disable(MAX3421_INTR_PIN);
+  }
+}
+
+void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
+  (void) rhport;
+  gpio_set_level(MAX3421_CS_PIN, active ? 0 : 1);
+}
+
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+  (void) rhport;
+
+  spi_transaction_t xact = {
+      .length = tx_len,
+      .rxlength = rx_len,
+      .tx_buffer = tx_buf,
+      .rx_buffer = rx_buf
+  };
+
+  ESP_ERROR_CHECK(spi_device_transmit(max3421_spi, &xact));
+  return true;
+}
+
+#endif
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
index bf8e45be2..2a154a8ff 100644
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -16,40 +16,57 @@ else()
   return()
 endif()
 
-list(APPEND compile_options
-    "-DCFG_TUSB_MCU=${tusb_mcu}"
-    "-DCFG_TUSB_OS=OPT_OS_FREERTOS"
-    #"-DCFG_TUSB_DEBUG=1"
-    )
-
-idf_component_get_property(freertos_component_dir freertos COMPONENT_DIR)
-
-list(APPEND includes_public
-    "${tusb_src}"
-    # The FreeRTOS API include convention in tinyusb is different from esp-idf
-    #"${freertos_component_dir}/include/freertos"
-    )
+list(APPEND compile_definitions
+  CFG_TUSB_MCU=${tusb_mcu}
+  CFG_TUSB_OS=OPT_OS_FREERTOS
+  )
 
 list(APPEND srcs
-    "${tusb_src}/tusb.c"
-    "${tusb_src}/common/tusb_fifo.c"
-    "${tusb_src}/device/usbd.c"
-    "${tusb_src}/device/usbd_control.c"
-    "${tusb_src}/class/cdc/cdc_device.c"
-    "${tusb_src}/class/dfu/dfu_rt_device.c"
-    "${tusb_src}/class/hid/hid_device.c"
-    "${tusb_src}/class/midi/midi_device.c"
-    "${tusb_src}/class/msc/msc_device.c"
-    "${tusb_src}/class/net/ecm_rndis_device.c"
-    "${tusb_src}/class/net/ncm_device.c"
-    "${tusb_src}/class/usbtmc/usbtmc_device.c"
-    "${tusb_src}/class/vendor/vendor_device.c"
-    "${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c"
-    )
+  # common
+  ${tusb_src}/tusb.c
+  ${tusb_src}/common/tusb_fifo.c
+  # device
+  ${tusb_src}/device/usbd.c
+  ${tusb_src}/device/usbd_control.c
+  ${tusb_src}/class/audio/audio_device.c
+  ${tusb_src}/class/cdc/cdc_device.c
+  ${tusb_src}/class/dfu/dfu_device.c
+  ${tusb_src}/class/dfu/dfu_rt_device.c
+  ${tusb_src}/class/hid/hid_device.c
+  ${tusb_src}/class/midi/midi_device.c
+  ${tusb_src}/class/msc/msc_device.c
+  ${tusb_src}/class/net/ecm_rndis_device.c
+  ${tusb_src}/class/net/ncm_device.c
+  ${tusb_src}/class/usbtmc/usbtmc_device.c
+  ${tusb_src}/class/vendor/vendor_device.c
+  ${tusb_src}/class/video/video_device.c
+  ${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c
+  # host
+  ${tusb_src}/host/usbh.c
+  ${tusb_src}/host/hub.c
+  ${tusb_src}/class/cdc/cdc_host.c
+  ${tusb_src}/class/hid/hid_host.c
+  ${tusb_src}/class/msc/msc_host.c
+  ${tusb_src}/class/vendor/vendor_host.c
+  )
+
+# use max3421 as host controller
+if (MAX3421_HOST STREQUAL "1")
+  list(APPEND srcs ${tusb_src}/portable/analog/max3421/hcd_max3421.c)
+  list(APPEND compile_definitions CFG_TUH_MAX3421=1)
+endif ()
+
+if (DEFINED LOG)
+  list(APPEND compile_definitions CFG_TUSB_DEBUG=${LOG})
+  if (LOG STREQUAL "4")
+    # no inline for debug level 4
+    list(APPEND compile_definitions TU_ATTR_ALWAYS_INLINE=)
+  endif ()
+endif()
 
 idf_component_register(SRCS ${srcs}
-    INCLUDE_DIRS ${includes_public}
-    REQUIRES src
-    )
+  INCLUDE_DIRS ${tusb_src}
+  REQUIRES src
+  )
 
-target_compile_options(${COMPONENT_LIB} PUBLIC ${compile_options})
+target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})
diff --git a/src/host/usbh.c b/src/host/usbh.c
index e332f35cc..dc2831da3 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -659,7 +659,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
   if (XFER_RESULT_SUCCESS != result) {
-    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
+    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %u\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
     TU_LOG1_BUF(request, 8);
     TU_LOG1("\r\n");
 
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index f3f76fd58..3f6747404 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -882,7 +882,7 @@ void hcd_int_handler(uint8_t rhport) {
     if ( hirq & HIRQ_RCVDAV_IRQ ) {
       uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
       max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
-      uint8_t xact_len;
+      uint8_t xact_len = 0;
 
       // RCVDAV_IRQ can trigger 2 times (dual buffered)
       while ( hirq & HIRQ_RCVDAV_IRQ ) {

From f6ca86c3ddeaec18f52b15f1065a5c9eea210c00 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 26 Sep 2023 19:09:36 +0700
Subject: [PATCH 2054/2085] tested cdc_msc_hid_freertos with samd51

add -Wno-error=format for espressif
wrap up cdc_msc_hid_freertos
---
 examples/host/cdc_msc_hid_freertos/Makefile   |  32 +++
 examples/host/cdc_msc_hid_freertos/only.txt   |  13 +
 .../cdc_msc_hid_freertos/src/CMakeLists.txt   |   4 +-
 .../host/cdc_msc_hid_freertos/src/cdc_app.c   | 109 ++++++++
 .../cdc_msc_hid_freertos/src/freertos_hook.c  | 111 ++++++++
 .../host/cdc_msc_hid_freertos/src/hid_app.c   | 263 ++++++++++++++++++
 examples/host/cdc_msc_hid_freertos/src/main.c |  22 +-
 .../host/cdc_msc_hid_freertos/src/msc_app.c   |  67 +++++
 hw/bsp/espressif/boards/CMakeLists.txt        |   2 +
 hw/bsp/espressif/boards/family.c              |  39 +--
 .../components/tinyusb_src/CMakeLists.txt     |   1 +
 hw/bsp/nrf/family.c                           | 106 +++----
 hw/bsp/samd21/family.c                        |   9 +-
 hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h |   2 +-
 hw/bsp/samd51/family.c                        |   8 +-
 src/host/usbh.c                               |   2 +-
 16 files changed, 703 insertions(+), 87 deletions(-)
 create mode 100644 examples/host/cdc_msc_hid_freertos/Makefile
 create mode 100644 examples/host/cdc_msc_hid_freertos/only.txt
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/cdc_app.c
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/freertos_hook.c
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/hid_app.c
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/msc_app.c

diff --git a/examples/host/cdc_msc_hid_freertos/Makefile b/examples/host/cdc_msc_hid_freertos/Makefile
new file mode 100644
index 000000000..67bb6da55
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/Makefile
@@ -0,0 +1,32 @@
+include ../../make.mk
+
+FREERTOS_SRC = lib/FreeRTOS-Kernel
+FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
+
+INC += \
+	src \
+	$(TOP)/hw \
+	$(TOP)/$(FREERTOS_SRC)/include \
+	$(TOP)/$(FREERTOS_PORTABLE_SRC) \
+
+# Example source
+EXAMPLE_SOURCE = \
+  src/cdc_app.c \
+  src/freertos_hook.c \
+  src/hid_app.c \
+  src/main.c \
+  src/msc_app.c \
+
+SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
+
+# TinyUSB Host Stack source
+SRC_C += \
+	src/class/cdc/cdc_host.c \
+	src/class/hid/hid_host.c \
+	src/class/msc/msc_host.c \
+	src/host/hub.c \
+	src/host/usbh.c \
+	src/portable/ohci/ohci.c \
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+
+include ../../rules.mk
diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt
new file mode 100644
index 000000000..3837ac8a2
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/only.txt
@@ -0,0 +1,13 @@
+mcu:LPC175X_6X
+mcu:LPC177X_8X
+mcu:LPC18XX
+mcu:LPC40XX
+mcu:LPC43XX
+mcu:MIMXRT1XXX
+mcu:MIMXRT10XX
+mcu:MIMXRT11XX
+mcu:RP2040
+mcu:MSP432E4
+mcu:RX65X
+mcu:RAXXX
+mcu:MAX3421
diff --git a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
index dd7ec8e58..6f057c106 100644
--- a/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
+++ b/examples/host/cdc_msc_hid_freertos/src/CMakeLists.txt
@@ -1,4 +1,6 @@
 # This file is for ESP-IDF only
-idf_component_register(SRCS "hid_app.c" "main.c"
+idf_component_register(SRCS "cdc_app.c" "hid_app.c" "main.c" "msc_app.c"
                     INCLUDE_DIRS "."
                     REQUIRES boards tinyusb_src)
+
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
new file mode 100644
index 000000000..fc2b1228d
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
@@ -0,0 +1,109 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2022, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb.h"
+#include "bsp/board_api.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+
+//------------- IMPLEMENTATION -------------//
+
+size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
+  size_t count = 0;
+  while (count < bufsize) {
+    int ch = board_getchar();
+    if (ch <= 0) break;
+
+    buf[count] = (uint8_t) ch;
+    count++;
+  }
+
+  return count;
+}
+
+void cdc_app_task(void* param) {
+  (void) param;
+
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
+
+  while (1) {
+    uint32_t count = get_console_inputs(buf, bufsize);
+    buf[count] = 0;
+
+    if (count) {
+      // loop over all mounted interfaces
+      for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) {
+        if (tuh_cdc_mounted(idx)) {
+          // console --> cdc interfaces
+          tuh_cdc_write(idx, buf, count);
+          tuh_cdc_write_flush(idx);
+        }
+      }
+    }
+
+    taskYIELD();
+  }
+}
+
+// Invoked when received new data
+void tuh_cdc_rx_cb(uint8_t idx) {
+  uint8_t buf[64 + 1]; // +1 for extra null character
+  uint32_t const bufsize = sizeof(buf) - 1;
+
+  // forward cdc interfaces -> console
+  uint32_t count = tuh_cdc_read(idx, buf, bufsize);
+  buf[count] = 0;
+
+  printf((char *) buf);
+}
+
+void tuh_cdc_mount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = { 0 };
+  tuh_cdc_itf_get_info(idx, &itf_info);
+
+  printf("CDC Interface is mounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+
+#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
+  // CFG_TUH_CDC_LINE_CODING_ON_ENUM must be defined for line coding is set by tinyusb in enumeration
+  // otherwise you need to call tuh_cdc_set_line_coding() first
+  cdc_line_coding_t line_coding = { 0 };
+  if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
+    printf("  Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
+    printf("  Parity  : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
+  }
+#endif
+}
+
+void tuh_cdc_umount_cb(uint8_t idx) {
+  tuh_itf_info_t itf_info = { 0 };
+  tuh_cdc_itf_get_info(idx, &itf_info);
+
+  printf("CDC Interface is unmounted: address = %u, itf_num = %u\r\n", itf_info.daddr, itf_info.desc.bInterfaceNumber);
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c b/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c
new file mode 100644
index 000000000..07d159fd5
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/freertos_hook.c
@@ -0,0 +1,111 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "common/tusb_common.h"
+
+void vApplicationMallocFailedHook(void) {
+  taskDISABLE_INTERRUPTS();
+  TU_ASSERT(false,);
+}
+
+void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName) {
+  (void) pxTask;
+  (void) pcTaskName;
+
+  taskDISABLE_INTERRUPTS();
+  TU_ASSERT(false,);
+}
+
+/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
+ * used by the Idle task. */
+void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer,
+                                   uint32_t *pulIdleTaskStackSize) {
+  /* If the buffers to be provided to the Idle task are declared inside this
+   * function then they must be declared static - otherwise they will be allocated on
+   * the stack and so not exists after this function exits. */
+  static StaticTask_t xIdleTaskTCB;
+  static StackType_t uxIdleTaskStack[configMINIMAL_STACK_SIZE];
+
+  /* Pass out a pointer to the StaticTask_t structure in which the Idle task's
+    state will be stored. */
+  *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+  /* Pass out the array that will be used as the Idle task's stack. */
+  *ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+  /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+    Note that, as the array is necessarily of type StackType_t,
+    configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+  *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+
+/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
+ * application must provide an implementation of vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Timer service task. */
+void vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer,
+                                    uint32_t *pulTimerTaskStackSize) {
+  /* If the buffers to be provided to the Timer task are declared inside this
+   * function then they must be declared static - otherwise they will be allocated on
+   * the stack and so not exists after this function exits. */
+  static StaticTask_t xTimerTaskTCB;
+  static StackType_t uxTimerTaskStack[configTIMER_TASK_STACK_DEPTH];
+
+  /* Pass out a pointer to the StaticTask_t structure in which the Timer
+    task's state will be stored. */
+  *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+
+  /* Pass out the array that will be used as the Timer task's stack. */
+  *ppxTimerTaskStackBuffer = uxTimerTaskStack;
+
+  /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
+    Note that, as the array is necessarily of type StackType_t,
+    configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */
+  *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+}
+
+#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X
+#include "iodefine.h"
+void vApplicationSetupTimerInterrupt(void)
+{
+  /* Enable CMT0 */
+  SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1);
+  MSTP(CMT0)       = 0;
+  SYSTEM.PRCR.WORD = (0xA5u<<8);
+
+  CMT0.CMCNT      = 0;
+  CMT0.CMCOR      = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128);
+  CMT0.CMCR.WORD  = TU_BIT(6) | 2;
+  IR(CMT0, CMI0)  = 0;
+  IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY;
+  IEN(CMT0, CMI0) = 1;
+  CMT.CMSTR0.BIT.STR0 = 1;
+}
+#endif
diff --git a/examples/host/cdc_msc_hid_freertos/src/hid_app.c b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
new file mode 100644
index 000000000..a2df3b909
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
@@ -0,0 +1,263 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "bsp/board_api.h"
+#include "tusb.h"
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+// If your host terminal support ansi escape code such as TeraTerm
+// it can be use to simulate mouse cursor movement within terminal
+#define USE_ANSI_ESCAPE   0
+
+#define MAX_REPORT  4
+
+static uint8_t const keycode2ascii[128][2] = { HID_KEYCODE_TO_ASCII };
+
+// Each HID instance can has multiple reports
+static struct {
+  uint8_t report_count;
+  tuh_hid_report_info_t report_info[MAX_REPORT];
+} hid_info[CFG_TUH_HID];
+
+static void process_kbd_report(hid_keyboard_report_t const *report);
+static void process_mouse_report(hid_mouse_report_t const *report);
+static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len);
+
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
+// Invoked when device with hid interface is mounted
+// Report descriptor is also available for use. tuh_hid_parse_report_descriptor()
+// can be used to parse common/simple enough descriptor.
+// Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped
+// therefore report_desc = NULL, desc_len = 0
+void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *desc_report, uint16_t desc_len) {
+  printf("HID device address = %d, instance = %d is mounted\r\n", dev_addr, instance);
+
+  // Interface protocol (hid_interface_protocol_enum_t)
+  const char *protocol_str[] = { "None", "Keyboard", "Mouse" };
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+
+  printf("HID Interface Protocol = %s\r\n", protocol_str[itf_protocol]);
+
+  // By default host stack will use activate boot protocol on supported interface.
+  // Therefore for this simple example, we only need to parse generic report descriptor (with built-in parser)
+  if (itf_protocol == HID_ITF_PROTOCOL_NONE) {
+    hid_info[instance].report_count = tuh_hid_parse_report_descriptor(hid_info[instance].report_info, MAX_REPORT,
+                                                                      desc_report, desc_len);
+    printf("HID has %u reports \r\n", hid_info[instance].report_count);
+  }
+
+  // request to receive report
+  // tuh_hid_report_received_cb() will be invoked when report is available
+  if (!tuh_hid_receive_report(dev_addr, instance)) {
+    printf("Error: cannot request to receive report\r\n");
+  }
+}
+
+// Invoked when device with hid interface is un-mounted
+void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance) {
+  printf("HID device address = %d, instance = %d is unmounted\r\n", dev_addr, instance);
+}
+
+// Invoked when received report from device via interrupt endpoint
+void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) {
+  uint8_t const itf_protocol = tuh_hid_interface_protocol(dev_addr, instance);
+
+  switch (itf_protocol) {
+    case HID_ITF_PROTOCOL_KEYBOARD:
+      TU_LOG2("HID receive boot keyboard report\r\n");
+      process_kbd_report((hid_keyboard_report_t const *) report);
+      break;
+
+    case HID_ITF_PROTOCOL_MOUSE:
+      TU_LOG2("HID receive boot mouse report\r\n");
+      process_mouse_report((hid_mouse_report_t const *) report);
+      break;
+
+    default:
+      // Generic report requires matching ReportID and contents with previous parsed report info
+      process_generic_report(dev_addr, instance, report, len);
+      break;
+  }
+
+  // continue to request to receive report
+  if (!tuh_hid_receive_report(dev_addr, instance)) {
+    printf("Error: cannot request to receive report\r\n");
+  }
+}
+
+//--------------------------------------------------------------------+
+// Keyboard
+//--------------------------------------------------------------------+
+
+// look up new key in previous keys
+static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode) {
+  for (uint8_t i = 0; i < 6; i++) {
+    if (report->keycode[i] == keycode) return true;
+  }
+
+  return false;
+}
+
+static void process_kbd_report(hid_keyboard_report_t const *report) {
+  static hid_keyboard_report_t prev_report = { 0, 0, { 0 } }; // previous report to check key released
+
+  //------------- example code ignore control (non-printable) key affects -------------//
+  for (uint8_t i = 0; i < 6; i++) {
+    if (report->keycode[i]) {
+      if (find_key_in_report(&prev_report, report->keycode[i])) {
+        // exist in previous report means the current key is holding
+      } else {
+        // not existed in previous report means the current key is pressed
+        bool const is_shift = report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT);
+        uint8_t ch = keycode2ascii[report->keycode[i]][is_shift ? 1 : 0];
+        putchar(ch);
+        if (ch == '\r') putchar('\n'); // added new line for enter key
+
+        #ifndef __ICCARM__ // TODO IAR doesn't support stream control ?
+        fflush(stdout); // flush right away, else nanolib will wait for newline
+        #endif
+      }
+    }
+    // TODO example skips key released
+  }
+
+  prev_report = *report;
+}
+
+//--------------------------------------------------------------------+
+// Mouse
+//--------------------------------------------------------------------+
+
+void cursor_movement(int8_t x, int8_t y, int8_t wheel) {
+#if USE_ANSI_ESCAPE
+  // Move X using ansi escape
+  if ( x < 0) {
+    printf(ANSI_CURSOR_BACKWARD(%d), (-x)); // move left
+  }else if ( x > 0) {
+    printf(ANSI_CURSOR_FORWARD(%d), x); // move right
+  }
+
+  // Move Y using ansi escape
+  if ( y < 0) {
+    printf(ANSI_CURSOR_UP(%d), (-y)); // move up
+  }else if ( y > 0) {
+    printf(ANSI_CURSOR_DOWN(%d), y); // move down
+  }
+
+  // Scroll using ansi escape
+  if (wheel < 0) {
+    printf(ANSI_SCROLL_UP(%d), (-wheel)); // scroll up
+  }else if (wheel > 0) {
+    printf(ANSI_SCROLL_DOWN(%d), wheel); // scroll down
+  }
+
+  printf("\r\n");
+#else
+  printf("(%d %d %d)\r\n", x, y, wheel);
+#endif
+}
+
+static void process_mouse_report(hid_mouse_report_t const *report) {
+  static hid_mouse_report_t prev_report = { 0 };
+
+  //------------- button state  -------------//
+  uint8_t button_changed_mask = report->buttons ^ prev_report.buttons;
+  if (button_changed_mask & report->buttons) {
+    printf(" %c%c%c ",
+           report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-',
+           report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-',
+           report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-');
+  }
+
+  //------------- cursor movement -------------//
+  cursor_movement(report->x, report->y, report->wheel);
+}
+
+//--------------------------------------------------------------------+
+// Generic Report
+//--------------------------------------------------------------------+
+static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len) {
+  (void) dev_addr;
+
+  uint8_t const rpt_count = hid_info[instance].report_count;
+  tuh_hid_report_info_t *rpt_info_arr = hid_info[instance].report_info;
+  tuh_hid_report_info_t *rpt_info = NULL;
+
+  if (rpt_count == 1 && rpt_info_arr[0].report_id == 0) {
+    // Simple report without report ID as 1st byte
+    rpt_info = &rpt_info_arr[0];
+  } else {
+    // Composite report, 1st byte is report ID, data starts from 2nd byte
+    uint8_t const rpt_id = report[0];
+
+    // Find report id in the array
+    for (uint8_t i = 0; i < rpt_count; i++) {
+      if (rpt_id == rpt_info_arr[i].report_id) {
+        rpt_info = &rpt_info_arr[i];
+        break;
+      }
+    }
+
+    report++;
+    len--;
+  }
+
+  if (!rpt_info) {
+    printf("Couldn't find report info !\r\n");
+    return;
+  }
+
+  // For complete list of Usage Page & Usage checkout src/class/hid/hid.h. For examples:
+  // - Keyboard                     : Desktop, Keyboard
+  // - Mouse                        : Desktop, Mouse
+  // - Gamepad                      : Desktop, Gamepad
+  // - Consumer Control (Media Key) : Consumer, Consumer Control
+  // - System Control (Power key)   : Desktop, System Control
+  // - Generic (vendor)             : 0xFFxx, xx
+  if (rpt_info->usage_page == HID_USAGE_PAGE_DESKTOP) {
+    switch (rpt_info->usage) {
+      case HID_USAGE_DESKTOP_KEYBOARD:
+        TU_LOG1("HID receive keyboard report\r\n");
+        // Assume keyboard follow boot report layout
+        process_kbd_report((hid_keyboard_report_t const *) report);
+        break;
+
+      case HID_USAGE_DESKTOP_MOUSE:
+        TU_LOG1("HID receive mouse report\r\n");
+        // Assume mouse follow boot report layout
+        process_mouse_report((hid_mouse_report_t const *) report);
+        break;
+
+      default:
+        break;
+    }
+  }
+}
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
index e2ddd52eb..d5574789f 100644
--- a/examples/host/cdc_msc_hid_freertos/src/main.c
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -51,6 +51,8 @@
   #define USBH_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
 #endif
 
+#define CDC_STACK_SZIE      (3*configMINIMAL_STACK_SIZE/2)
+
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTOTYPES
 //--------------------------------------------------------------------+
@@ -72,18 +74,16 @@ StaticTimer_t blinky_tmdef;
 StackType_t  usb_host_stack[USBH_STACK_SIZE];
 StaticTask_t usb_host_taskdef;
 
-//StackType_t  cdc_stack[CDC_STACK_SZIE];
-//StaticTask_t cdc_taskdef;
+StackType_t  cdc_stack[CDC_STACK_SZIE];
+StaticTask_t cdc_taskdef;
 #endif
 
-
 TimerHandle_t blinky_tm;
 
 static void led_blinky_cb(TimerHandle_t xTimer);
 static void usb_host_task(void* param);
 
-extern void cdc_app_task(void);
-extern void hid_app_task(void);
+extern void cdc_app_task(void* param);
 
 /*------------- MAIN -------------*/
 int main(void) {
@@ -91,19 +91,15 @@ int main(void) {
 
   printf("TinyUSB Host CDC MSC HID with FreeRTOS Example\r\n");
 
+  // Create soft timer for blinky, task for tinyusb stack and CDC
 #if configSUPPORT_STATIC_ALLOCATION
-  // soft timer for blinky
   blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
-
-  // Create a task for tinyusb device stack
   xTaskCreateStatic(usb_host_task, "usbh", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_host_stack, &usb_host_taskdef);
-
-  // Create CDC task
-  //xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+  xTaskCreateStatic(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
 #else
   blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
-  xTaskCreate( usb_device_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
-  //xTaskCreate( cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+  xTaskCreate(usb_host_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
+  xTaskCreate(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
 #endif
 
   xTimerStart(blinky_tm, 0);
diff --git a/examples/host/cdc_msc_hid_freertos/src/msc_app.c b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
new file mode 100644
index 000000000..a8d6fbfaa
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
@@ -0,0 +1,67 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "tusb.h"
+
+#if CFG_TUH_MSC
+
+static scsi_inquiry_resp_t inquiry_resp;
+
+bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_data) {
+  msc_cbw_t const *cbw = cb_data->cbw;
+  msc_csw_t const *csw = cb_data->csw;
+
+  if (csw->status != 0) {
+    printf("Inquiry failed\r\n");
+    return false;
+  }
+
+  // Print out Vendor ID, Product ID and Rev
+  printf("%.8s %.16s rev %.4s\r\n", inquiry_resp.vendor_id, inquiry_resp.product_id, inquiry_resp.product_rev);
+
+  // Get capacity of device
+  uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
+  uint32_t const block_size = tuh_msc_get_block_size(dev_addr, cbw->lun);
+
+  printf("Disk Size: %lu MB\r\n", block_count / ((1024 * 1024) / block_size));
+  printf("Block Count = %lu, Block Size: %lu\r\n", block_count, block_size);
+
+  return true;
+}
+
+//------------- IMPLEMENTATION -------------//
+void tuh_msc_mount_cb(uint8_t dev_addr) {
+  printf("A MassStorage device is mounted\r\n");
+
+  uint8_t const lun = 0;
+  tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0);
+}
+
+void tuh_msc_umount_cb(uint8_t dev_addr) {
+  (void) dev_addr;
+  printf("A MassStorage device is unmounted\r\n");
+}
+
+#endif
diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt
index 325263c1d..8209e8747 100644
--- a/hw/bsp/espressif/boards/CMakeLists.txt
+++ b/hw/bsp/espressif/boards/CMakeLists.txt
@@ -4,3 +4,5 @@ idf_component_register(SRCS family.c
                     INCLUDE_DIRS "." ${BOARD} ${hw_dir}
                     PRIV_REQUIRES "driver"
                     REQUIRES led_strip src tinyusb_src)
+
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 250b7001e..d96d86670 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -33,6 +33,7 @@
 #include "soc/usb_periph.h"
 
 #include "driver/rmt.h"
+#include "driver/uart.h"
 
 #if ESP_IDF_VERSION_MAJOR > 4
   #include "esp_private/periph_ctrl.h"
@@ -145,9 +146,7 @@ uint32_t board_button_read(void) {
 
 // Get characters from UART
 int board_uart_read(uint8_t *buf, int len) {
-  (void) buf;
-  (void) len;
-  return 0;
+  return uart_read_bytes(UART_NUM_0, buf, len, 0);
 }
 
 // Send characters to UART
@@ -157,6 +156,11 @@ int board_uart_write(void const *buf, int len) {
   return 0;
 }
 
+int board_getchar(void) {
+  char c;
+  return (uart_read_bytes(UART_NUM_0, &c, 1, 0) > 0) ? (int) c : (-1);
+}
+
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
@@ -164,12 +168,12 @@ int board_uart_write(void const *buf, int len) {
 
 static spi_device_handle_t max3421_spi;
 
-static void IRAM_ATTR max3421_isr_handler(void* arg)
-{
-  (void) arg;
-  //uint32_t gpio_num = (uint32_t) arg;
+static void IRAM_ATTR max3421_isr_handler(void* arg) {
+  (void) arg; // arg is gpio num
   //xQueueSendFromISR(gpio_evt_queue, &gpio_num, NULL);
+  gpio_set_level(13, 1);
   tuh_int_handler(1);
+  gpio_set_level(13, 0);
 }
 
 static void max3421_init(void) {
@@ -188,12 +192,11 @@ static void max3421_init(void) {
       .data5_io_num = -1,
       .data6_io_num = -1,
       .data7_io_num = -1,
-      .max_transfer_sz = 128
+      .max_transfer_sz = 1024
   };
   ESP_ERROR_CHECK( spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO) );
 
   spi_device_interface_config_t max3421_cfg = {
-      .command_bits = 8,
       .mode = 0,
       .clock_speed_hz = 4000000, // 26000000
       .spics_io_num = -1, // manual control CS
@@ -201,12 +204,16 @@ static void max3421_init(void) {
   };
   ESP_ERROR_CHECK( spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi) );
 
+  // debug
+  gpio_set_direction(13, GPIO_MODE_OUTPUT);
+  gpio_set_level(13, 0);
+
   // Interrupt pin
-//  gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
-//  gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
-//
-//  gpio_install_isr_service(ESP_INTR_FLAG_EDGE);
-//  gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL);
+  gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
+  gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
+
+  gpio_install_isr_service(0);
+  gpio_isr_handler_add(MAX3421_INTR_PIN, max3421_isr_handler, NULL);
 }
 
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
@@ -227,8 +234,8 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
   (void) rhport;
 
   spi_transaction_t xact = {
-      .length = tx_len,
-      .rxlength = rx_len,
+      .length = tx_len << 3, // length in bits
+      .rxlength = rx_len << 3, // length in bits
       .tx_buffer = tx_buf,
       .rx_buffer = rx_buf
   };
diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
index 2a154a8ff..abe276910 100644
--- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
+++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
@@ -70,3 +70,4 @@ idf_component_register(SRCS ${srcs}
   )
 
 target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format)
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 6fcfd9476..3620bc8cc 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -95,13 +95,8 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 
 //------------- Host using MAX2341E -------------//
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+static void max3421_init(void);
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
-
-void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
-  if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
-
-  tuh_int_handler(1);
-}
 #endif
 
 
@@ -191,50 +186,7 @@ void board_init(void) {
 #endif
 
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
-  // MAX3421 need 3.3v signal (may not be needed)
-  #if defined(UICR_REGOUT0_VOUT_Msk) && 0
-  if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
-    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
-
-    NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3;
-
-    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
-    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
-
-    NVIC_SystemReset();
-  }
-  #endif
-
-  // manually manage CS
-  nrf_gpio_cfg_output(MAX3421_CS_PIN);
-  nrf_gpio_pin_write(MAX3421_CS_PIN, 1);
-
-  // USB host using max3421e usb controller via SPI
-  nrfx_spim_config_t cfg = {
-      .sck_pin        = MAX3421_SCK_PIN,
-      .mosi_pin       = MAX3421_MOSI_PIN,
-      .miso_pin       = MAX3421_MISO_PIN,
-      .ss_pin         = NRFX_SPIM_PIN_NOT_USED,
-      .ss_active_high = false,
-      .irq_priority   = 3,
-      .orc            = 0xFF,
-      // default setting 4 Mhz, Mode 0, MSB first
-      .frequency      = NRF_SPIM_FREQ_4M,
-      .mode           = NRF_SPIM_MODE_0,
-      .bit_order      = NRF_SPIM_BIT_ORDER_MSB_FIRST,
-  };
-
-  // no handler --> blocking
-  nrfx_spim_init(&_spi, &cfg, NULL, NULL);
-
-  // max3421e interrupt pin
-  nrfx_gpiote_init(1);
-  nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
-  in_config.pull = NRF_GPIO_PIN_PULLUP;
-
-  nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
-  nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
+  max3421_init();
 #endif
 
 }
@@ -317,6 +269,60 @@ void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
 //--------------------------------------------------------------------+
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
+void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
+  if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
+  tuh_int_handler(1);
+}
+
+static void max3421_init(void) {
+  // MAX3421 need 3.3v signal (may not be needed)
+//  #if defined(UICR_REGOUT0_VOUT_Msk)
+//  if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
+//    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+//    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+//
+//    NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3;
+//
+//    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+//    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+//
+//    NVIC_SystemReset();
+//  }
+//  #endif
+
+  // manually manage CS
+  nrf_gpio_cfg_output(MAX3421_CS_PIN);
+  nrf_gpio_pin_write(MAX3421_CS_PIN, 1);
+
+  // USB host using max3421e usb controller via SPI
+  nrfx_spim_config_t cfg = {
+      .sck_pin        = MAX3421_SCK_PIN,
+      .mosi_pin       = MAX3421_MOSI_PIN,
+      .miso_pin       = MAX3421_MISO_PIN,
+      .ss_pin         = NRFX_SPIM_PIN_NOT_USED,
+      .ss_active_high = false,
+      .irq_priority   = 3,
+      .orc            = 0xFF,
+      // default setting 4 Mhz, Mode 0, MSB first
+      .frequency      = NRF_SPIM_FREQ_4M,
+      .mode           = NRF_SPIM_MODE_0,
+      .bit_order      = NRF_SPIM_BIT_ORDER_MSB_FIRST,
+  };
+
+  // no handler --> blocking
+  nrfx_spim_init(&_spi, &cfg, NULL, NULL);
+
+  // max3421e interrupt pin
+  nrfx_gpiote_init(1);
+  nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
+  in_config.pull = NRF_GPIO_PIN_PULLUP;
+
+  NVIC_SetPriority(GPIOTE_IRQn, 2);
+
+  nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
+  nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
+}
+
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index 395155548..335039e2f 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -261,6 +261,7 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
+#endif
 
 //--------------------------------------------------------------------+
 //
@@ -344,6 +345,11 @@ static void max3421_init(void) {
   EIC->CONFIG[0].reg &= ~(7 << sense_shift);
   EIC->CONFIG[0].reg |= 2 << sense_shift;
 
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(EIC_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
   // Enable External Interrupt
   EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
 
@@ -413,6 +419,3 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
 }
 
 #endif
-
-
-#endif
diff --git a/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
index e3ee529cf..32db4ad95 100644
--- a/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
+++ b/hw/bsp/samd51/FreeRTOSConfig/FreeRTOSConfig.h
@@ -59,7 +59,7 @@
 #define configTICK_RATE_HZ                      ( 1000 )
 #define configMAX_PRIORITIES                    ( 5 )
 #define configMINIMAL_STACK_SIZE                ( 128 )
-#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*6*1024 )
 #define configMAX_TASK_NAME_LEN                 16
 #define configUSE_16_BIT_TICKS                  0
 #define configIDLE_SHOULD_YIELD                 1
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index c1b914a02..7b9de35c9 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -175,6 +175,7 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
+#endif
 
 //--------------------------------------------------------------------+
 // API: SPI transfer with MAX3421E, must be implemented by application
@@ -290,6 +291,11 @@ static void max3421_init(void) {
   *eic_config &= ~(7 << sense_shift);
   *eic_config |= 2 << sense_shift;
 
+#if CFG_TUSB_OS == OPT_OS_FREERTOS
+  // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
+  NVIC_SetPriority(EIC_0_IRQn + MAX3421_INTR_EIC_ID, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY);
+#endif
+
   // Enable External Interrupt
   EIC->INTENSET.reg = EIC_INTENSET_EXTINT(1 << MAX3421_INTR_EIC_ID);
 
@@ -360,5 +366,3 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
 }
 
 #endif
-
-#endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index dc2831da3..e332f35cc 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -659,7 +659,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
   tusb_control_request_t const * request = &_ctrl_xfer.request;
 
   if (XFER_RESULT_SUCCESS != result) {
-    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %u\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
+    TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
     TU_LOG1_BUF(request, 8);
     TU_LOG1("\r\n");
 

From 1168e4e16343cc0a6d958899460f1b841624974f Mon Sep 17 00:00:00 2001
From: bac <ben.cowperthwaite@sonardyne.com>
Date: Tue, 26 Sep 2023 15:27:17 +0100
Subject: [PATCH 2055/2085] Added support for USB2 HS peripheral (with
 integrated HS PHY) on STM32U59x chips

---
 src/portable/synopsys/dwc2/dwc2_stm32.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index cb455bd90..aa77511fa 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -84,7 +84,17 @@
 
 #elif CFG_TUSB_MCU == OPT_MCU_STM32U5
   #include "stm32u5xx.h"
-  #define USB_OTG_FS_PERIPH_BASE       USB_OTG_FS_BASE
+  // NOTE: STM595/5A5/599/5A9 only have 1 USB port (with integrated HS PHY)
+  // USB_OTG_FS_BASE and OTG_FS_IRQn not defined
+  #if (! defined USB_OTG_FS)
+    #define USB_OTG_HS_PERIPH_BASE    USB_OTG_HS_BASE
+    #define EP_MAX_HS                 9
+    #define EP_FIFO_SIZE_HS           4096
+    #define USB_OTG_FS_PERIPH_BASE    USB_OTG_HS_BASE
+    #define OTG_FS_IRQn               OTG_HS_IRQn
+  #else
+    #define USB_OTG_FS_PERIPH_BASE    USB_OTG_FS_BASE
+  #endif
   #define EP_MAX_FS       6
   #define EP_FIFO_SIZE_FS 1280
 

From 2f6592de7f94851cfcca411242398c5da7b792de Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Sep 2023 11:30:18 +0700
Subject: [PATCH 2056/2085] update max3421 to have hcd_int_handler_ext()

---
 hw/bsp/espressif/boards/family.c          | 22 +++++++-
 src/host/hcd.h                            |  3 ++
 src/portable/analog/max3421/hcd_max3421.c | 62 ++++++++++++-----------
 3 files changed, 55 insertions(+), 32 deletions(-)

diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index d96d86670..a04e1e7c5 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -167,15 +167,30 @@ int board_getchar(void) {
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
 
 static spi_device_handle_t max3421_spi;
+SemaphoreHandle_t max3421_intr_sem;
 
 static void IRAM_ATTR max3421_isr_handler(void* arg) {
   (void) arg; // arg is gpio num
-  //xQueueSendFromISR(gpio_evt_queue, &gpio_num, NULL);
   gpio_set_level(13, 1);
-  tuh_int_handler(1);
+
+  BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+  xSemaphoreGiveFromISR(max3421_intr_sem, &xHigherPriorityTaskWoken);
+  if (xHigherPriorityTaskWoken) {
+    portYIELD_FROM_ISR();
+  }
+
   gpio_set_level(13, 0);
 }
 
+static void max3421_intr_task(void* param) {
+  (void) param;
+
+  while (1) {
+    xSemaphoreTake(max3421_intr_sem, portMAX_DELAY);
+    tuh_int_handler(BOARD_TUH_RHPORT);
+  }
+}
+
 static void max3421_init(void) {
   // CS pin
   gpio_set_direction(MAX3421_CS_PIN, GPIO_MODE_OUTPUT);
@@ -209,6 +224,9 @@ static void max3421_init(void) {
   gpio_set_level(13, 0);
 
   // Interrupt pin
+  max3421_intr_sem = xSemaphoreCreateBinary();
+  xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES-1, NULL);
+
   gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
   gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
 
diff --git a/src/host/hcd.h b/src/host/hcd.h
index e25b20ea3..a2d4da85d 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -133,6 +133,9 @@ bool hcd_init(uint8_t rhport);
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport);
 
+// Interrupt Hanndler (extended version)
+void hcd_int_handler_ext(uint8_t rhport, bool in_isr);
+
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport);
 
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 3f6747404..652a971ee 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -428,8 +428,8 @@ bool hcd_init(uint8_t rhport) {
   reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
 
   // V1 is 0x01, V2 is 0x12, V3 is 0x13
-  // uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
-  // TU_LOG2_HEX(revision);
+  uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
+  TU_LOG2_HEX(revision);
 
   // reset
   reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
@@ -693,9 +693,7 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) {
 
       // port reset anyway, this will help to stable bus signal for next connection
       reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, in_isr);
-
       hcd_event_device_remove(rhport, in_isr);
-
       reg_write(rhport, HCTL_ADDR, 0, in_isr);
       break;
 
@@ -721,13 +719,12 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) {
       free_ep(daddr);
 
       hcd_event_device_attach(rhport, in_isr);
-
       break;
     }
   }
 }
 
-static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl) {
+static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl, bool in_isr) {
   uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
 
   // save data toggle
@@ -738,20 +735,20 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re
   }
 
   ep->xfer_pending = 0;
-  hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, true);
+  hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, in_isr);
 
   // Find next pending endpoint
   max3421_ep_t *next_ep = find_next_pending_ep(ep);
   if (next_ep) {
-    xact_inout(rhport, next_ep, true, true);
+    xact_inout(rhport, next_ep, true, in_isr);
   }else {
     // no more pending
     atomic_flag_clear(&_hcd_data.busy);
   }
 }
 
-static void handle_xfer_done(uint8_t rhport) {
-  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
+static void handle_xfer_done(uint8_t rhport, bool in_isr) {
+  uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
   uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
 
   uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
@@ -774,17 +771,17 @@ static void handle_xfer_done(uint8_t rhport) {
     case HRSL_NAK:
       if (ep_num == 0) {
         // NAK on control, retry immediately
-        hxfr_write(rhport, _hcd_data.hxfr, true);
+        hxfr_write(rhport, _hcd_data.hxfr, in_isr);
       }else {
         // NAK on non-control, find next pending to switch
         max3421_ep_t *next_ep = find_next_pending_ep(ep);
 
         if (ep == next_ep) {
           // this endpoint is only one pending, retry immediately
-          hxfr_write(rhport, _hcd_data.hxfr, true);
+          hxfr_write(rhport, _hcd_data.hxfr, in_isr);
         }else if (next_ep) {
           // switch to next pending TODO could have issue with double buffered if not clear previously out data
-          xact_inout(rhport, next_ep, true, true);
+          xact_inout(rhport, next_ep, true, in_isr);
         }else {
           TU_ASSERT(false,);
         }
@@ -802,7 +799,7 @@ static void handle_xfer_done(uint8_t rhport) {
   }
 
   if (xfer_result != XFER_RESULT_SUCCESS) {
-    xfer_complete_isr(rhport, ep, xfer_result, hrsl);
+    xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
     return;
   }
 
@@ -814,10 +811,10 @@ static void handle_xfer_done(uint8_t rhport) {
 
     // short packet or all bytes transferred
     if ( ep->xfer_complete ) {
-      xfer_complete_isr(rhport, ep, xfer_result, hrsl);
+      xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
     }else {
       // more to transfer
-      hxfr_write(rhport, _hcd_data.hxfr, true);
+      hxfr_write(rhport, _hcd_data.hxfr, in_isr);
     }
   } else {
     // SETUP or OUT transfer
@@ -835,10 +832,10 @@ static void handle_xfer_done(uint8_t rhport) {
     ep->buf += xact_len;
 
     if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
-      xfer_complete_isr(rhport, ep, xfer_result, hrsl);
+      xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr);
     } else {
       // more to transfer
-      xact_out(rhport, ep, false, true);
+      xact_out(rhport, ep, false, in_isr);
     }
   }
 }
@@ -862,9 +859,9 @@ void print_hirq(uint8_t hirq) {
   #define print_hirq(hirq)
 #endif
 
-// Interrupt Handler
-void hcd_int_handler(uint8_t rhport) {
-  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
+// Interrupt handler (extended)
+void hcd_int_handler_ext(uint8_t rhport, bool in_isr) {
+  uint8_t hirq = reg_read(rhport, HIRQ_ADDR, in_isr) & _hcd_data.hien;
   if (!hirq) return;
 //  print_hirq(hirq);
 
@@ -873,7 +870,7 @@ void hcd_int_handler(uint8_t rhport) {
   }
 
   if (hirq & HIRQ_CONDET_IRQ) {
-    handle_connect_irq(rhport, true);
+    handle_connect_irq(rhport, in_isr);
   }
 
   // queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or
@@ -886,17 +883,17 @@ void hcd_int_handler(uint8_t rhport) {
 
       // RCVDAV_IRQ can trigger 2 times (dual buffered)
       while ( hirq & HIRQ_RCVDAV_IRQ ) {
-        uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, true);
+        uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr);
         xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
         if ( xact_len ) {
-          fifo_read(rhport, ep->buf, xact_len, true);
+          fifo_read(rhport, ep->buf, xact_len, in_isr);
           ep->buf += xact_len;
           ep->xferred_len += xact_len;
         }
 
         // ack RCVDVAV IRQ
-        hirq_write(rhport, HIRQ_RCVDAV_IRQ, true);
-        hirq = reg_read(rhport, HIRQ_ADDR, true);
+        hirq_write(rhport, HIRQ_RCVDAV_IRQ, in_isr);
+        hirq = reg_read(rhport, HIRQ_ADDR, in_isr);
       }
 
       if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
@@ -905,18 +902,23 @@ void hcd_int_handler(uint8_t rhport) {
     }
 
     if ( hirq & HIRQ_HXFRDN_IRQ ) {
-      hirq_write(rhport, HIRQ_HXFRDN_IRQ, true);
-      handle_xfer_done(rhport);
+      hirq_write(rhport, HIRQ_HXFRDN_IRQ, in_isr);
+      handle_xfer_done(rhport, in_isr);
     }
 
-    hirq = reg_read(rhport, HIRQ_ADDR, true);
+    hirq = reg_read(rhport, HIRQ_ADDR, in_isr);
   }
 
   // clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
   hirq &= ~HIRQ_SNDBAV_IRQ;
   if ( hirq ) {
-    hirq_write(rhport, hirq, true);
+    hirq_write(rhport, hirq, in_isr);
   }
 }
 
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport) {
+  hcd_int_handler_ext(rhport, true);
+}
+
 #endif

From 6dc64eaa28ab905063233895345ba3c1186b836d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Sep 2023 12:33:36 +0700
Subject: [PATCH 2057/2085] max3421 communication work with esp32 up to
 enumeration, seems still have a bit of issue

---
 .idea/cmake.xml                                  |  7 +++++++
 examples/host/cdc_msc_hid_freertos/src/cdc_app.c |  2 +-
 examples/host/cdc_msc_hid_freertos/src/main.c    |  3 ++-
 hw/bsp/espressif/boards/family.c                 | 15 ++++++++++-----
 4 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 747f0fb58..ddeeb69fd 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -56,6 +56,13 @@
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
       <configuration PROFILE_NAME="metro_m4_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="metro esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_metro_esp32s2 -DMAX3421_HOST=1 -DLOG=2">
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
index fc2b1228d..943e534d8 100644
--- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
@@ -68,7 +68,7 @@ void cdc_app_task(void* param) {
       }
     }
 
-    taskYIELD();
+    vTaskDelay(1);
   }
 }
 
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
index d5574789f..88e742ee2 100644
--- a/examples/host/cdc_msc_hid_freertos/src/main.c
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -40,6 +40,7 @@
   #include "freertos/timers.h"
 
   #define USBH_STACK_SIZE     4096
+  #define CDC_STACK_SZIE      2048
 #else
   #include "FreeRTOS.h"
   #include "semphr.h"
@@ -49,9 +50,9 @@
 
   // Increase stack size when debug log is enabled
   #define USBH_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
+  #define CDC_STACK_SZIE     (3*configMINIMAL_STACK_SIZE/2)
 #endif
 
-#define CDC_STACK_SZIE      (3*configMINIMAL_STACK_SIZE/2)
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTOTYPES
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index a04e1e7c5..5226f7e61 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -83,7 +83,6 @@ void board_init(void) {
   gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT);
   gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY);
 
-#if CFG_TUD_ENABLED
   // USB Controller Hal init
   periph_module_reset(PERIPH_USB_MODULE);
   periph_module_enable(PERIPH_USB_MODULE);
@@ -93,7 +92,6 @@ void board_init(void) {
   };
   usb_hal_init(&hal);
   configure_pins(&hal);
-#endif
 
 #if CFG_TUH_ENABLED && CFG_TUH_MAX3421
   max3421_init();
@@ -157,8 +155,9 @@ int board_uart_write(void const *buf, int len) {
 }
 
 int board_getchar(void) {
-  char c;
-  return (uart_read_bytes(UART_NUM_0, &c, 1, 0) > 0) ? (int) c : (-1);
+//  char c;
+//  return (uart_read_bytes(UART_NUM_0, &c, 1, 0) > 0) ? (int) c : (-1);
+  return -1;
 }
 
 //--------------------------------------------------------------------+
@@ -187,7 +186,7 @@ static void max3421_intr_task(void* param) {
 
   while (1) {
     xSemaphoreTake(max3421_intr_sem, portMAX_DELAY);
-    tuh_int_handler(BOARD_TUH_RHPORT);
+    hcd_int_handler_ext(BOARD_TUH_RHPORT, false);
   }
 }
 
@@ -251,6 +250,12 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
 bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
   (void) rhport;
 
+  if (tx_len == 0) {
+    // fifo read, transmit rx_buf as dummy
+    tx_buf = rx_buf;
+    tx_len = rx_len;
+  }
+
   spi_transaction_t xact = {
       .length = tx_len << 3, // length in bits
       .rxlength = rx_len << 3, // length in bits

From 3b0ffd0f488671f1bafa4bcd9e22dd51f8bb6dee Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Sep 2023 15:51:03 +0700
Subject: [PATCH 2058/2085] change hcd_int_handler(rhport, in_isr) signature:
 add in_isr

change tuh_int_handler() to take in_isr as optional parameter (default =
true)
---
 examples/host/bare_api/only.txt               |  1 +
 examples/host/cdc_msc_hid/only.txt            |  1 +
 examples/host/hid_controller/only.txt         |  1 +
 examples/host/msc_file_explorer/only.txt      |  1 +
 hw/bsp/imxrt/family.c                         |  4 +-
 hw/bsp/kinetis_kl/family.c                    |  2 +-
 hw/bsp/kinetis_kl/family.cmake                | 75 +++++++++--------
 .../boards/lpcxpresso1769/lpcxpresso1769.c    |  2 +-
 hw/bsp/lpc17/boards/mbed1768/mbed1768.c       |  2 +-
 hw/bsp/lpc18/family.c                         | 55 ++++++-------
 hw/bsp/lpc40/family.c                         |  2 +-
 hw/bsp/lpc43/family.c                         |  4 +-
 hw/bsp/msp432e4/family.c                      |  2 +-
 hw/bsp/ngx4330/ngx4330.c                      |  4 +-
 hw/bsp/nrf/family.c                           |  2 +-
 hw/bsp/ra/family.c                            |  6 +-
 hw/bsp/rx/boards/rx65n_target/rx65n_target.c  |  2 +-
 hw/bsp/samd21/family.c                        |  2 +-
 hw/bsp/samd51/family.c                        |  2 +-
 hw/bsp/stm32g4/family.cmake                   | 79 +++++++++---------
 hw/bsp/tm4c123/family.c                       |  2 +-
 src/common/tusb_common.h                      |  2 -
 src/common/tusb_timeout.h                     | 80 -------------------
 src/common/tusb_verify.h                      | 52 ++++--------
 src/host/hcd.h                                |  2 +-
 src/host/usbh.h                               | 11 ++-
 src/portable/analog/max3421/hcd_max3421.c     |  3 +-
 src/portable/ehci/ehci.c                      |  4 +-
 src/portable/mentor/musb/hcd_musb.c           |  4 +-
 src/portable/nxp/khci/hcd_khci.c              |  7 +-
 src/portable/ohci/ohci.c                      |  5 +-
 src/portable/raspberrypi/rp2040/hcd_rp2040.c  |  4 +-
 src/portable/renesas/rusb2/hcd_rusb2.c        |  5 +-
 src/portable/template/hcd_template.c          |  3 +-
 src/tusb.h                                    |  4 +-
 35 files changed, 171 insertions(+), 266 deletions(-)
 delete mode 100644 src/common/tusb_timeout.h

diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt
index 3837ac8a2..fee10f9e2 100644
--- a/examples/host/bare_api/only.txt
+++ b/examples/host/bare_api/only.txt
@@ -1,3 +1,4 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt
index 3837ac8a2..fee10f9e2 100644
--- a/examples/host/cdc_msc_hid/only.txt
+++ b/examples/host/cdc_msc_hid/only.txt
@@ -1,3 +1,4 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt
index 3837ac8a2..fee10f9e2 100644
--- a/examples/host/hid_controller/only.txt
+++ b/examples/host/hid_controller/only.txt
@@ -1,3 +1,4 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt
index 3837ac8a2..fee10f9e2 100644
--- a/examples/host/msc_file_explorer/only.txt
+++ b/examples/host/msc_file_explorer/only.txt
@@ -1,3 +1,4 @@
+mcu:KINETIS_KL
 mcu:LPC175X_6X
 mcu:LPC177X_8X
 mcu:LPC18XX
diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c
index ec95a8b24..32d89f794 100644
--- a/hw/bsp/imxrt/family.c
+++ b/hw/bsp/imxrt/family.c
@@ -188,7 +188,7 @@ void USB_OTG1_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
+    tuh_int_handler(0, true);
   #endif
 }
 
@@ -199,7 +199,7 @@ void USB_OTG2_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
+    tuh_int_handler(1, true);
   #endif
 }
 
diff --git a/hw/bsp/kinetis_kl/family.c b/hw/bsp/kinetis_kl/family.c
index 3e9aa83a4..c436be3e6 100644
--- a/hw/bsp/kinetis_kl/family.c
+++ b/hw/bsp/kinetis_kl/family.c
@@ -39,7 +39,7 @@
 void USB0_IRQHandler(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 #if CFG_TUD_ENABLED
   tud_int_handler(0);
diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake
index 793ef1783..4151979a0 100644
--- a/hw/bsp/kinetis_kl/family.cmake
+++ b/hw/bsp/kinetis_kl/family.cmake
@@ -22,48 +22,47 @@ set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "")
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      ${SDK_DIR}/drivers/gpio/fsl_gpio.c
-      ${SDK_DIR}/drivers/lpsci/fsl_lpsci.c
-      ${SDK_DIR}/drivers/uart/fsl_uart.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
-      )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${CMSIS_DIR}/CMSIS/Core/Include
-      ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
-      ${SDK_DIR}/drivers/common
-      ${SDK_DIR}/drivers/gpio
-      ${SDK_DIR}/drivers/lpsci
-      ${SDK_DIR}/drivers/port
-      ${SDK_DIR}/drivers/smc
-      ${SDK_DIR}/drivers/uart
-      )
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
 
-    update_board(${BOARD_TARGET})
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/drivers/gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/lpsci/fsl_lpsci.c
+    ${SDK_DIR}/drivers/uart/fsl_uart.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/gpio
+    ${SDK_DIR}/drivers/lpsci
+    ${SDK_DIR}/drivers/port
+    ${SDK_DIR}/drivers/smc
+    ${SDK_DIR}/drivers/uart
+    )
+  update_board(${BOARD_TARGET})
 
-    # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  # LD_FILE and STARTUP_FILE can be defined in board.cmake
+  target_sources(${BOARD_TARGET} PUBLIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
 
-    target_sources(${BOARD_TARGET} PUBLIC
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      # nanolib
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
       )
-
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_GNU}"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
   endif ()
 endfunction()
 
diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
index c7d655368..8c26b906f 100644
--- a/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
+++ b/hw/bsp/lpc17/boards/lpcxpresso1769/lpcxpresso1769.c
@@ -37,7 +37,7 @@ void USB_IRQHandler(void)
   #endif
 
   #if CFG_TUH_ENABLED
-    tuh_int_handler(0);
+    tuh_int_handler(0, true);
   #endif
 }
 
diff --git a/hw/bsp/lpc17/boards/mbed1768/mbed1768.c b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
index b2c92d640..613dcb570 100644
--- a/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
+++ b/hw/bsp/lpc17/boards/mbed1768/mbed1768.c
@@ -151,7 +151,7 @@ void USB_IRQHandler(void)
   #endif
 
   #if CFG_TUH_ENABLED
-    tuh_int_handler(0);
+    tuh_int_handler(0, true);
   #endif
 }
 
diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c
index b11f4fe0e..e6abecb4b 100644
--- a/hw/bsp/lpc18/family.c
+++ b/hw/bsp/lpc18/family.c
@@ -43,25 +43,23 @@
 //--------------------------------------------------------------------+
 // USB Interrupt Handler
 //--------------------------------------------------------------------+
-void USB0_IRQHandler(void)
-{
+void USB0_IRQHandler(void) {
   #if PORT_SUPPORT_DEVICE(0)
-    tud_int_handler(0);
+  tud_int_handler(0);
   #endif
 
   #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
+  tuh_int_handler(0, true);
   #endif
 }
 
-void USB1_IRQHandler(void)
-{
+void USB1_IRQHandler(void) {
   #if PORT_SUPPORT_DEVICE(1)
-    tud_int_handler(1);
+  tud_int_handler(1);
   #endif
 
   #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
+  tuh_int_handler(1, true);
   #endif
 }
 
@@ -74,28 +72,26 @@ const uint32_t OscRateIn = 12000000;
 const uint32_t ExtRateIn = 0;
 
 // Invoked by startup code
-void SystemInit(void)
-{
+void SystemInit(void) {
 #ifdef __USE_LPCOPEN
-	extern void (* const g_pfnVectors[])(void);
+  extern void (*const g_pfnVectors[])(void);
   unsigned int *pSCB_VTOR = (unsigned int *) 0xE000ED08;
-	*pSCB_VTOR = (unsigned int) g_pfnVectors;
+  *pSCB_VTOR = (unsigned int) g_pfnVectors;
 #endif
 
   board_lpc18_pinmux();
 
-  #ifdef TRACE_ETM
+#ifdef TRACE_ETM
   // Trace clock is limited to 60MHz, limit CPU clock to 120MHz
   Chip_SetupCoreClock(CLKIN_CRYSTAL, 120000000UL, true);
-  #else
+#else
   // CPU clock max to 180 Mhz
   Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
-  #endif
+#endif
 
 }
 
-void board_init(void)
-{
+void board_init(void) {
   SystemCoreClockUpdate();
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -135,27 +131,22 @@ void board_init(void)
 // Board porting API
 //--------------------------------------------------------------------+
 
-void board_led_write(bool state)
-{
+void board_led_write(bool state) {
   Chip_GPIO_SetPinState(LPC_GPIO_PORT, LED_PORT, LED_PIN, state);
 }
 
-uint32_t board_button_read(void)
-{
+uint32_t board_button_read(void) {
   // active low
   return Chip_GPIO_GetPinState(LPC_GPIO_PORT, BUTTON_PORT, BUTTON_PIN) ? 0 : 1;
 }
 
-int board_uart_read(uint8_t* buf, int len)
-{
+int board_uart_read(uint8_t *buf, int len) {
   return Chip_UART_Read(UART_DEV, buf, len);
 }
 
-int board_uart_write(void const * buf, int len)
-{
-  uint8_t const* buf8 = (uint8_t const*) buf;
-  for(int i=0; i<len; i++)
-  {
+int board_uart_write(void const *buf, int len) {
+  uint8_t const *buf8 = (uint8_t const *) buf;
+  for (int i = 0; i < len; i++) {
     while ((Chip_UART_ReadLineStatus(UART_DEV) & UART_LSR_THRE) == 0) {}
     Chip_UART_SendByte(UART_DEV, buf8[i]);
   }
@@ -165,13 +156,13 @@ int board_uart_write(void const * buf, int len)
 
 #if CFG_TUSB_OS == OPT_OS_NONE
 volatile uint32_t system_ticks = 0;
-void SysTick_Handler (void)
-{
+
+void SysTick_Handler(void) {
   system_ticks++;
 }
 
-uint32_t board_millis(void)
-{
+uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
diff --git a/hw/bsp/lpc40/family.c b/hw/bsp/lpc40/family.c
index 526e3a080..d6c8ef32a 100644
--- a/hw/bsp/lpc40/family.c
+++ b/hw/bsp/lpc40/family.c
@@ -37,7 +37,7 @@ void USB_IRQHandler(void) {
   #endif
 
   #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
   #endif
 }
 
diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c
index d52c1a071..8be729f7d 100644
--- a/hw/bsp/lpc43/family.c
+++ b/hw/bsp/lpc43/family.c
@@ -213,7 +213,7 @@ void USB0_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
+    tuh_int_handler(0, true);
   #endif
 }
 
@@ -224,7 +224,7 @@ void USB1_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
+    tuh_int_handler(1, true);
   #endif
 }
 
diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c
index 10f3ac736..d5ef7f930 100644
--- a/hw/bsp/msp432e4/family.c
+++ b/hw/bsp/msp432e4/family.c
@@ -34,7 +34,7 @@
 void USB0_IRQHandler(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 #if CFG_TUD_ENABLED
   tud_int_handler(0);
diff --git a/hw/bsp/ngx4330/ngx4330.c b/hw/bsp/ngx4330/ngx4330.c
index a767d5f29..bd84e449b 100644
--- a/hw/bsp/ngx4330/ngx4330.c
+++ b/hw/bsp/ngx4330/ngx4330.c
@@ -214,7 +214,7 @@ void USB0_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(0)
-    tuh_int_handler(0);
+    tuh_int_handler(0, true);
   #endif
 }
 
@@ -225,7 +225,7 @@ void USB1_IRQHandler(void)
   #endif
 
   #if PORT_SUPPORT_HOST(1)
-    tuh_int_handler(1);
+    tuh_int_handler(1, true);
   #endif
 }
 
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 6fcfd9476..fc755f512 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -100,7 +100,7 @@ static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
   if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
 
-  tuh_int_handler(1);
+  tuh_int_handler(1, true);
 }
 #endif
 
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 0aa58d86d..fdf4c8666 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -188,7 +188,7 @@ void usbfs_interrupt_handler(void) {
   R_BSP_IrqStatusClear(irq);
 
   #if PORT_SUPPORT_HOST(0)
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
   #endif
 
   #if PORT_SUPPORT_DEVICE(0)
@@ -201,7 +201,7 @@ void usbfs_resume_handler(void) {
   R_BSP_IrqStatusClear(irq);
 
   #if PORT_SUPPORT_HOST(0)
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
   #endif
 
   #if PORT_SUPPORT_DEVICE(0)
@@ -229,7 +229,7 @@ void usbhs_interrupt_handler(void) {
   R_BSP_IrqStatusClear(irq);
 
   #if PORT_SUPPORT_HOST(1)
-  tuh_int_handler(1);
+  tuh_int_handler(1, true);
   #endif
 
   #if PORT_SUPPORT_DEVICE(1)
diff --git a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
index 513eca678..032dac810 100644
--- a/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
+++ b/hw/bsp/rx/boards/rx65n_target/rx65n_target.c
@@ -177,7 +177,7 @@ void INT_Excep_SCI5_RXI5(void)
 void INT_Excep_USB0_USBI0(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 #if CFG_TUD_ENABLED
   tud_int_handler(0);
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index cfe66b8dc..0ea729055 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -356,7 +356,7 @@ void EIC_Handler(void) {
   EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
 
   // Call the TinyUSB interrupt handler
-  tuh_int_handler(1);
+  tuh_int_handler(1, true);
 }
 
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 2cf00c7af..268d60e48 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -296,7 +296,7 @@ void MAX3421_EIC_Handler(void) {
   EIC->INTFLAG.reg = EIC_INTFLAG_EXTINT(1 << MAX3421_INTR_EIC_ID);
 
   // Call the TinyUSB interrupt handler
-  tuh_int_handler(1);
+  tuh_int_handler(1, true);
 }
 
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake
index 675a96c74..f8cabcbe5 100644
--- a/hw/bsp/stm32g4/family.cmake
+++ b/hw/bsp/stm32g4/family.cmake
@@ -26,50 +26,47 @@ set(FAMILY_MCUS STM32G4 CACHE INTERNAL "")
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    # Startup & Linker script
-    set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
-    set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
-    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif ()
 
-    add_library(${BOARD_TARGET} STATIC
-      ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
-      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
-      )
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
-      ${CMSIS_5}/CMSIS/Core/Include
-      ${ST_CMSIS}/Include
-      ${ST_HAL_DRIVER}/Inc
-      )
-    target_compile_options(${BOARD_TARGET} PUBLIC
-      )
-    target_compile_definitions(${BOARD_TARGET} PUBLIC
-      )
+  # Startup & Linker script
+  set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
+  set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
+  set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
 
-    update_board(${BOARD_TARGET})
+  add_library(${BOARD_TARGET} STATIC
+    ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
+    ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMSIS_5}/CMSIS/Core/Include
+    ${ST_CMSIS}/Include
+    ${ST_HAL_DRIVER}/Inc
+    )
+  update_board(${BOARD_TARGET})
 
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--script=${LD_FILE_GNU}"
-        -nostartfiles
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
   endif ()
 endfunction()
 
diff --git a/hw/bsp/tm4c123/family.c b/hw/bsp/tm4c123/family.c
index ad5ae505f..738bc3fa0 100644
--- a/hw/bsp/tm4c123/family.c
+++ b/hw/bsp/tm4c123/family.c
@@ -8,7 +8,7 @@
 void USB0_Handler(void)
 {
 #if CFG_TUH_ENABLED
-  tuh_int_handler(0);
+  tuh_int_handler(0, true);
 #endif
 
 #if CFG_TUD_ENABLED
diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h
index 6fffed11c..caeb5f2ef 100644
--- a/src/common/tusb_common.h
+++ b/src/common/tusb_common.h
@@ -75,8 +75,6 @@
 #include "tusb_types.h"
 #include "tusb_debug.h"
 
-#include "tusb_timeout.h" // TODO remove
-
 //--------------------------------------------------------------------+
 // Optional API implemented by application if needed
 // TODO move to a more ovious place/file
diff --git a/src/common/tusb_timeout.h b/src/common/tusb_timeout.h
deleted file mode 100644
index 533e67ab8..000000000
--- a/src/common/tusb_timeout.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2019 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- * This file is part of the TinyUSB stack.
- */
-
-/** \ingroup Group_Common Common Files
- *  \defgroup Group_TimeoutTimer timeout timer
- *  @{ */
-
-#ifndef _TUSB_TIMEOUT_H_
-#define _TUSB_TIMEOUT_H_
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-  uint32_t start;
-  uint32_t interval;
-}tu_timeout_t;
-
-#if 0
-
-extern uint32_t tusb_hal_millis(void);
-
-static inline void tu_timeout_set(tu_timeout_t* tt, uint32_t msec)
-{
-  tt->interval = msec;
-  tt->start    = tusb_hal_millis();
-}
-
-static inline bool tu_timeout_expired(tu_timeout_t* tt)
-{
-  return ( tusb_hal_millis() - tt->start ) >= tt->interval;
-}
-
-// For used with periodic event to prevent drift
-static inline void tu_timeout_reset(tu_timeout_t* tt)
-{
-  tt->start += tt->interval;
-}
-
-static inline void tu_timeout_restart(tu_timeout_t* tt)
-{
-  tt->start = tusb_hal_millis();
-}
-
-#endif
-
-#ifdef __cplusplus
- }
-#endif
-
-#endif /* _TUSB_TIMEOUT_H_ */
-
-/** @} */
diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h
index 12355e8be..1b5f53dfc 100644
--- a/src/common/tusb_verify.h
+++ b/src/common/tusb_verify.h
@@ -56,12 +56,8 @@
  *   #define TU_VERIFY(cond)                  if(cond) return false;
  *   #define TU_VERIFY(cond,ret)              if(cond) return ret;
  *
- *   #define TU_VERIFY_HDLR(cond,handler)     if(cond) {handler; return false;}
- *   #define TU_VERIFY_HDLR(cond,ret,handler) if(cond) {handler; return ret;}
- *
  *   #define TU_ASSERT(cond)                  if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return false;}
  *   #define TU_ASSERT(cond,ret)              if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return ret;}
- *
  *------------------------------------------------------------------*/
 
 #ifdef __cplusplus
@@ -97,40 +93,23 @@
   #define TU_BREAKPOINT() do {} while (0)
 #endif
 
-/*------------------------------------------------------------------*/
-/* Macro Generator
- *------------------------------------------------------------------*/
-
 // Helper to implement optional parameter for TU_VERIFY Macro family
 #define _GET_3RD_ARG(arg1, arg2, arg3, ...)        arg3
-#define _GET_4TH_ARG(arg1, arg2, arg3, arg4, ...)  arg4
-
-/*------------- Generator for TU_VERIFY and TU_VERIFY_HDLR -------------*/
-#define TU_VERIFY_DEFINE(_cond, _handler, _ret)  do            \
-{                                                              \
-  if ( !(_cond) ) { _handler; return _ret;  }                  \
-} while(0)
 
 /*------------------------------------------------------------------*/
 /* TU_VERIFY
  * - TU_VERIFY_1ARGS : return false if failed
  * - TU_VERIFY_2ARGS : return provided value if failed
  *------------------------------------------------------------------*/
-#define TU_VERIFY_1ARGS(_cond)                         TU_VERIFY_DEFINE(_cond, , false)
-#define TU_VERIFY_2ARGS(_cond, _ret)                   TU_VERIFY_DEFINE(_cond, , _ret)
+#define TU_VERIFY_DEFINE(_cond, _ret)    \
+  do {                                   \
+    if ( !(_cond) ) { return _ret; }     \
+  } while(0)
 
-#define TU_VERIFY(...)                   _GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, UNUSED)(__VA_ARGS__)
+#define TU_VERIFY_1ARGS(_cond)         TU_VERIFY_DEFINE(_cond, false)
+#define TU_VERIFY_2ARGS(_cond, _ret)   TU_VERIFY_DEFINE(_cond, _ret)
 
-
-/*------------------------------------------------------------------*/
-/* TU_VERIFY WITH HANDLER
- * - TU_VERIFY_HDLR_2ARGS : execute handler, return false if failed
- * - TU_VERIFY_HDLR_3ARGS : execute handler, return provided error if failed
- *------------------------------------------------------------------*/
-#define TU_VERIFY_HDLR_2ARGS(_cond, _handler)           TU_VERIFY_DEFINE(_cond, _handler, false)
-#define TU_VERIFY_HDLR_3ARGS(_cond, _handler, _ret)     TU_VERIFY_DEFINE(_cond, _handler, _ret)
-
-#define TU_VERIFY_HDLR(...)              _GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_HDLR_3ARGS, TU_VERIFY_HDLR_2ARGS,UNUSED)(__VA_ARGS__)
+#define TU_VERIFY(...)                 _GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, _dummy)(__VA_ARGS__)
 
 /*------------------------------------------------------------------*/
 /* ASSERT
@@ -138,19 +117,20 @@
  * - 1 arg : return false if failed
  * - 2 arg : return error if failed
  *------------------------------------------------------------------*/
-#define ASSERT_1ARGS(_cond)            TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), false)
-#define ASSERT_2ARGS(_cond, _ret)      TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), _ret)
+#define TU_ASSERT_DEFINE(_cond, _ret)                                 \
+  do {                                                                \
+    if ( !(_cond) ) { _MESS_FAILED(); TU_BREAKPOINT(); return _ret; } \
+  } while(0)
+
+#define TU_ASSERT_1ARGS(_cond)         TU_ASSERT_DEFINE(_cond, false)
+#define TU_ASSERT_2ARGS(_cond, _ret)   TU_ASSERT_DEFINE(_cond, _ret)
 
 #ifndef TU_ASSERT
-#define TU_ASSERT(...)             _GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS,UNUSED)(__VA_ARGS__)
+#define TU_ASSERT(...)                 _GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_2ARGS, TU_ASSERT_1ARGS, _dummy)(__VA_ARGS__)
 #endif
 
-/*------------------------------------------------------------------*/
-/* ASSERT HDLR
- *------------------------------------------------------------------*/
-
 #ifdef __cplusplus
  }
 #endif
 
-#endif /* TUSB_VERIFY_H_ */
+#endif
diff --git a/src/host/hcd.h b/src/host/hcd.h
index e25b20ea3..2bde289df 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -131,7 +131,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) TU_AT
 bool hcd_init(uint8_t rhport);
 
 // Interrupt Handler
-void hcd_int_handler(uint8_t rhport);
+void hcd_int_handler(uint8_t rhport, bool in_isr);
 
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport);
diff --git a/src/host/usbh.h b/src/host/usbh.h
index 684e8240e..770d70dfe 100644
--- a/src/host/usbh.h
+++ b/src/host/usbh.h
@@ -124,11 +124,16 @@ void tuh_task(void) {
 bool tuh_task_event_ready(void);
 
 #ifndef _TUSB_HCD_H_
-extern void hcd_int_handler(uint8_t rhport);
+extern void hcd_int_handler(uint8_t rhport, bool in_isr);
 #endif
 
-// Interrupt handler, name alias to HCD
-#define tuh_int_handler   hcd_int_handler
+// Interrupt handler alias to HCD with in_isr as optional parameter
+// - tuh_int_handler(rhport) --> hcd_int_handler(rhport, true)
+// - tuh_int_handler(rhport, in_isr) --> hcd_int_handler(rhport, in_isr)
+// Note: this is similar to TU_VERIFY(), _GET_3RD_ARG() is defined in tusb_verify.h
+#define _tuh_int_handler_1arg(_rhport)            hcd_int_handler(_rhport, true)
+#define _tuh_int_hanlder_2arg(_rhport, _in_isr)   hcd_int_handler(_rhport, _in_isr)
+#define tuh_int_handler(...)   _GET_3RD_ARG(__VA_ARGS__, _tuh_int_hanlder_2arg, _tuh_int_handler_1arg, _dummy)(__VA_ARGS__)
 
 // Check if roothub port is initialized and active as a host
 bool tuh_rhport_is_active(uint8_t rhport);
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 238b518a0..d013d6179 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -863,7 +863,8 @@ void print_hirq(uint8_t hirq) {
 #endif
 
 // Interrupt Handler
-void hcd_int_handler(uint8_t rhport) {
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  (void) in_isr;
   uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
   if (!hirq) return;
 //  print_hirq(hirq);
diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c
index c93c33fc0..572b9826c 100644
--- a/src/portable/ehci/ehci.c
+++ b/src/portable/ehci/ehci.c
@@ -656,8 +656,8 @@ void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms)
 }
 
 //------------- Host Controller Driver's Interrupt Handler -------------//
-void hcd_int_handler(uint8_t rhport)
-{
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  (void) in_isr;
   ehci_registers_t* regs = ehci_data.regs;
   uint32_t const int_status = regs->status;
 
diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c
index 02090df85..5312c2812 100644
--- a/src/portable/mentor/musb/hcd_musb.c
+++ b/src/portable/mentor/musb/hcd_musb.c
@@ -847,8 +847,10 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 /*-------------------------------------------------------------------
  * ISR
  *-------------------------------------------------------------------*/
-void hcd_int_handler(uint8_t rhport)
+void hcd_int_handler(uint8_t rhport, bool in_isr)
 {
+  (void) in_isr;
+
   uint_fast8_t is, txis, rxis;
 
   is   = USB0->IS;   /* read and clear interrupt status */
diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c
index 55327e02d..57684b259 100644
--- a/src/portable/nxp/khci/hcd_khci.c
+++ b/src/portable/nxp/khci/hcd_khci.c
@@ -447,6 +447,10 @@ void hcd_port_reset(uint8_t rhport)
   _hcd.need_reset = false;
 }
 
+void hcd_port_reset_end(uint8_t rhport) {
+  (void) rhport;
+}
+
 tusb_speed_t hcd_port_speed_get(uint8_t rhport)
 {
   (void)rhport;
@@ -583,8 +587,9 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 /*--------------------------------------------------------------------+
  * ISR
  *--------------------------------------------------------------------+*/
-void hcd_int_handler(uint8_t rhport)
+void hcd_int_handler(uint8_t rhport, bool in_isr)
 {
+  (void) in_isr;
   uint32_t is  = KHCI->ISTAT;
   uint32_t msk = KHCI->INTEN;
 
diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c
index 413e72037..f978b0965 100644
--- a/src/portable/ohci/ohci.c
+++ b/src/portable/ohci/ohci.c
@@ -667,8 +667,9 @@ static void done_queue_isr(uint8_t hostid)
   }
 }
 
-void hcd_int_handler(uint8_t hostid)
-{
+void hcd_int_handler(uint8_t hostid, bool in_isr) {
+  (void) in_isr;
+
   uint32_t const int_en     = OHCI_REG->interrupt_enable;
   uint32_t const int_status = OHCI_REG->interrupt_status & int_en;
 
diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
index 21dc3f67d..4ed6d36bb 100644
--- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c
+++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c
@@ -252,9 +252,9 @@ static void __tusb_irq_path_func(hcd_rp2040_irq)(void)
   }
 }
 
-void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport)
-{
+void __tusb_irq_path_func(hcd_int_handler)(uint8_t rhport, bool in_isr) {
   (void) rhport;
+  (void) in_isr;
   hcd_rp2040_irq();
 }
 
diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c
index 790cd6b32..bf95be707 100644
--- a/src/portable/renesas/rusb2/hcd_rusb2.c
+++ b/src/portable/renesas/rusb2/hcd_rusb2.c
@@ -771,8 +771,9 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
 //--------------------------------------------------------------------+
 // ISR
 //--------------------------------------------------------------------+
-void hcd_int_handler(uint8_t rhport)
-{
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
+  (void) in_isr;
+
   rusb2_reg_t* rusb = RUSB2_REG(rhport);
   unsigned is0 = rusb->INTSTS0;
   unsigned is1 = rusb->INTSTS1;
diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c
index 3e3b91558..b073d6057 100644
--- a/src/portable/template/hcd_template.c
+++ b/src/portable/template/hcd_template.c
@@ -51,8 +51,9 @@ bool hcd_init(uint8_t rhport) {
 }
 
 // Interrupt Handler
-void hcd_int_handler(uint8_t rhport) {
+void hcd_int_handler(uint8_t rhport, bool in_isr) {
   (void) rhport;
+  (void) in_isr;
 }
 
 // Enable USB interrupt
diff --git a/src/tusb.h b/src/tusb.h
index d6534ca28..c9d56d3c3 100644
--- a/src/tusb.h
+++ b/src/tusb.h
@@ -66,7 +66,7 @@
   #endif
 #else
   #ifndef tuh_int_handler
-  #define tuh_int_handler(_x)
+  #define tuh_int_handler(...)
   #endif
 #endif
 
@@ -123,7 +123,7 @@
   #endif
 #else
   #ifndef tud_int_handler
-  #define tud_int_handler(_x)
+  #define tud_int_handler(...)
   #endif
 #endif
 

From 0a4fb6963de9a62be613cab5ab33f70c2e836b3d Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Sep 2023 16:19:39 +0700
Subject: [PATCH 2059/2085] fix build with lpc54

---
 .github/workflows/build_arm.yml               |   2 +-
 .github/workflows/cmake_arm.yml               |   2 +-
 hw/bsp/family_support.cmake                   |   1 +
 hw/bsp/lpc54/FreeRTOSConfig/FreeRTOSConfig.h  | 165 ++++++++++++++++++
 .../lpc54/boards/lpcxpresso54114/board.cmake  |  21 +++
 .../lpc54/boards/lpcxpresso54608/board.cmake  |  22 +++
 hw/bsp/lpc54/family.cmake                     | 138 +++++++--------
 7 files changed, 281 insertions(+), 70 deletions(-)
 create mode 100644 hw/bsp/lpc54/FreeRTOSConfig/FreeRTOSConfig.h
 create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake
 create mode 100644 hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake

diff --git a/.github/workflows/build_arm.yml b/.github/workflows/build_arm.yml
index 975f351a0..c7462f0d7 100644
--- a/.github/workflows/build_arm.yml
+++ b/.github/workflows/build_arm.yml
@@ -36,7 +36,7 @@ jobs:
         - 'broadcom_32bit'
         - 'kinetis_k32l2'
         - 'lpc11 lpc13 lpc15 lpc17'
-        - 'lpc51 lpc54'
+        - 'lpc51'
         - 'mm32 msp432e4'
         - 'samd11 same5x saml2x'
         - 'stm32f2 stm32f3'
diff --git a/.github/workflows/cmake_arm.yml b/.github/workflows/cmake_arm.yml
index 4b788a213..5dc36ee2c 100644
--- a/.github/workflows/cmake_arm.yml
+++ b/.github/workflows/cmake_arm.yml
@@ -36,7 +36,7 @@ jobs:
           - 'imxrt'
           - 'kinetis_kl'
           - 'lpc18 lpc40 lpc43'
-          - 'lpc55'
+          - 'lpc54 lpc55'
           - 'mcx'
           - 'nrf'
           - 'ra'
diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake
index 642282b0e..9c625b58e 100644
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@@ -40,6 +40,7 @@ if (NOT FAMILY STREQUAL rp2040)
   # enable LTO if supported skip rp2040
   include(CheckIPOSupported)
   check_ipo_supported(RESULT IPO_SUPPORTED)
+  cmake_print_variables(IPO_SUPPORTED)
   if (IPO_SUPPORTED)
     set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE)
   endif()
diff --git a/hw/bsp/lpc54/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc54/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..fc0ab1f2d
--- /dev/null
+++ b/hw/bsp/lpc54/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,165 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+  #include "fsl_device_registers.h"
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU                        0
+#define configENABLE_FPU                        1
+#define configENABLE_TRUSTZONE                  0
+#define configMINIMAL_SECURE_STACK_SIZE         (1024)
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         0
+#define configSUPPORT_DYNAMIC_ALLOCATION        1
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configRECORD_STACK_HIGH_ADDRESS        1
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+
+// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
+#define configPRIO_BITS       3
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake
new file mode 100644
index 000000000..c0bbeecd5
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.cmake
@@ -0,0 +1,21 @@
+set(MCU_VARIANT LPC54114)
+set(MCU_CORE LPC54114_cm4)
+
+set(JLINK_DEVICE LPC54114J256_M4)
+set(PYOCD_TARGET LPC54114)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54114J256_cm4_flash.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC54114J256BD64_cm4
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_cm4_hardabi.a
+    )
+endfunction()
diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake b/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake
new file mode 100644
index 000000000..f0715fa12
--- /dev/null
+++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.cmake
@@ -0,0 +1,22 @@
+set(MCU_VARIANT LPC54608)
+set(MCU_CORE LPC54608)
+
+set(JLINK_DEVICE LPC54608J512)
+set(PYOCD_TARGET LPC54608)
+set(NXPLINK_DEVICE LPC54608:LPCXpresso54608)
+
+set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/LPC54608J512_flash.ld)
+
+# Device port default to PORT1 Highspeed
+if (NOT DEFINED PORT)
+  set(PORT 1)
+endif()
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CPU_LPC54608J512ET180
+    )
+  target_link_libraries(${TARGET} PUBLIC
+    ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/libpower_hardabi.a
+    )
+endfunction()
diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
index b016441c1..a1f876844 100644
--- a/hw/bsp/lpc54/family.cmake
+++ b/hw/bsp/lpc54/family.cmake
@@ -28,83 +28,85 @@ set(HOST_PORT $<NOT:${PORT}>)
 #------------------------------------
 # only need to be built ONCE for all examples
 function(add_board_target BOARD_TARGET)
-  if (NOT TARGET ${BOARD_TARGET})
-    add_library(${BOARD_TARGET} STATIC
-      # driver
-      ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
-      ${SDK_DIR}/drivers/common/fsl_common_arm.c
-      ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
-      ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
-      # mcu
-      ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
-      )
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
 
+  add_library(${BOARD_TARGET} STATIC
+    # driver
+    ${SDK_DIR}/drivers/lpc_gpio/fsl_gpio.c
+    ${SDK_DIR}/drivers/common/fsl_common_arm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_flexcomm.c
+    ${SDK_DIR}/drivers/flexcomm/fsl_usart.c
+    # mcu
+    ${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_CORE}.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_power.c
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_reset.c
+    )
+
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
+    BOARD_TUD_RHPORT=${PORT}
+    BOARD_TUH_RHPORT=${HOST_PORT}
+    )
+  # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
+  if (PORT EQUAL 1)
     target_compile_definitions(${BOARD_TARGET} PUBLIC
-      CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
-      BOARD_TUD_RHPORT=${PORT}
-      BOARD_TUH_RHPORT=${HOST_PORT}
+      BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
+      CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
       )
-    # Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
-    if (PORT EQUAL 1)
-      target_compile_definitions(${BOARD_TARGET} PUBLIC
-        BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
-        BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
-        CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
-        )
-    else ()
-      target_compile_definitions(${BOARD_TARGET} PUBLIC
-        BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
-        BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
-        CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
-        #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
-        )
-    endif ()
-
-    target_include_directories(${BOARD_TARGET} PUBLIC
-      ${TOP}/lib/sct_neopixel
-      # driver
-      ${SDK_DIR}/drivers/common
-      ${SDK_DIR}/drivers/flexcomm
-      ${SDK_DIR}/drivers/lpc_iocon
-      ${SDK_DIR}/drivers/lpc_gpio
-      ${SDK_DIR}/drivers/lpuart
-      ${SDK_DIR}/drivers/sctimer
-      # mcu
-      ${CMSIS_DIR}/CMSIS/Core/Include
-      ${SDK_DIR}/devices/${MCU_VARIANT}
-      ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+  else ()
+    target_compile_definitions(${BOARD_TARGET} PUBLIC
+      BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+      BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
+      CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
+      #CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
       )
+  endif ()
 
-    update_board(${BOARD_TARGET})
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${TOP}/lib/sct_neopixel
+    # driver
+    ${SDK_DIR}/drivers/common
+    ${SDK_DIR}/drivers/flexcomm
+    ${SDK_DIR}/drivers/lpc_iocon
+    ${SDK_DIR}/drivers/lpc_gpio
+    ${SDK_DIR}/drivers/lpuart
+    ${SDK_DIR}/drivers/sctimer
+    # mcu
+    ${CMSIS_DIR}/CMSIS/Core/Include
+    ${SDK_DIR}/devices/${MCU_VARIANT}
+    ${SDK_DIR}/devices/${MCU_VARIANT}/drivers
+    )
 
-    if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
-      set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
-    endif ()
+  update_board(${BOARD_TARGET})
 
-    if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
-      set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
-    endif ()
+  if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
+    set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
+  endif ()
 
-    target_sources(${BOARD_TARGET} PUBLIC
-      ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+  if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
+    set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
+  endif ()
+
+  target_sources(${BOARD_TARGET} PUBLIC
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      # linker file
+      "LINKER:--script=${LD_FILE_GNU}"
+      # nanolib
+      --specs=nosys.specs
+      --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
       )
-
-    if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        # linker file
-        "LINKER:--script=${LD_FILE_GNU}"
-        # nanolib
-        --specs=nosys.specs
-        --specs=nano.specs
-        )
-    elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
-      target_link_options(${BOARD_TARGET} PUBLIC
-        "LINKER:--config=${LD_FILE_IAR}"
-        )
-    endif ()
   endif ()
 endfunction()
 

From 58c49cea5b94dcf45b0b2117afc3fc8ce646732c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Sep 2023 16:31:46 +0700
Subject: [PATCH 2060/2085] remove sct_neopixel from lpc54 (due to warnings and
 not used)

---
 hw/bsp/lpc54/family.cmake | 2 --
 1 file changed, 2 deletions(-)

diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake
index a1f876844..cdd513fe4 100644
--- a/hw/bsp/lpc54/family.cmake
+++ b/hw/bsp/lpc54/family.cmake
@@ -126,8 +126,6 @@ function(family_configure_example TARGET RTOS)
     # BSP
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
     ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
-    # external driver
-    ${TOP}/lib/sct_neopixel/sct_neopixel.c
     )
 
   # https://github.com/gsteiert/sct_neopixel/pull/1

From b35621fc63defdd3191d569c8248dae52997ce8f Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 27 Sep 2023 11:37:16 +0200
Subject: [PATCH 2061/2085] Update IAR template.

---
 tools/iar_gen.py        | 123 ++++++++++------
 tools/iar_template.ipcf | 316 +++++++++++++++++++++-------------------
 2 files changed, 241 insertions(+), 198 deletions(-)

diff --git a/tools/iar_gen.py b/tools/iar_gen.py
index 73c8b29fc..646a581f4 100644
--- a/tools/iar_gen.py
+++ b/tools/iar_gen.py
@@ -1,51 +1,84 @@
 #!/usr/bin/python3
 
 import os
+import sys
 import xml.dom.minidom as XML
+import glob
 
-# Read base configuration
-base = ""
-with open("iar_template.ipcf") as f:
-    base = f.read()
+def Main():
+    # Read base configuration
+    base = ""
+    with open("iar_template.ipcf") as f:
+        base = f.read()
 
-# Enumerate all device/host examples
-dir_1 = os.listdir("../examples")
-for dir_2 in dir_1:
-    if os.path.isdir("../examples/{}".format(dir_2)):
-        print(dir_2)
-        examples = os.listdir("../examples/{}".format(dir_2))
-        for example in examples:
-            if os.path.isdir("../examples/{}/{}".format(dir_2, example)):
-                print("../examples/{}/{}".format(dir_2, example))
-                conf = XML.parseString(base)
-                files = conf.getElementsByTagName("files")[0]
-                inc   = conf.getElementsByTagName("includePath")[0]
-                # Add bsp inc
-                path = conf.createElement('path')
-                path_txt = conf.createTextNode("$TUSB_DIR$/hw")
-                path.appendChild(path_txt)
-                inc.appendChild(path)
-                # Add board.c/.h
-                grp = conf.createElement('group')
-                grp.setAttribute("name", "bsp")
-                path = conf.createElement('path')
-                path_txt = conf.createTextNode("$TUSB_DIR$/hw/bsp/board.c")
-                path.appendChild(path_txt)
-                grp.appendChild(path)
-                files.appendChild(grp)
-                # Add example's .c/.h
-                grp = conf.createElement('group')
-                grp.setAttribute("name", "example")
-                for file in os.listdir("../examples/{}/{}/src".format(dir_2, example)):
-                    if file.endswith(".c") or file.endswith(".h"):
-                        path = conf.createElement('path')
-                        path.setAttribute("copyTo", "$PROJ_DIR$/{}".format(file))
-                        path_txt = conf.createTextNode("$TUSB_DIR$/examples/{0}/{1}/src/{2}".format(dir_2, example, file))
-                        path.appendChild(path_txt)
-                        grp.appendChild(path)
-                files.appendChild(grp)
-                cfg_str = conf.toprettyxml()
-                cfg_str = '\n'.join([s for s in cfg_str.splitlines() if s.strip()])
-                #print(cfg_str)
-                with open("../examples/{0}/{1}/iar_{1}.ipcf".format(dir_2, example), 'w') as f:
-                    f.write(cfg_str)
+    # Enumerate all device/host examples
+    dir_1 = os.listdir("../examples")
+    for dir_2 in dir_1:
+        if os.path.isdir("../examples/{}".format(dir_2)):
+            print(dir_2)
+            examples = os.listdir("../examples/{}".format(dir_2))
+            for example in examples:
+                if os.path.isdir("../examples/{}/{}".format(dir_2, example)):
+                    print("../examples/{}/{}".format(dir_2, example))
+                    conf = XML.parseString(base)
+                    files = conf.getElementsByTagName("files")[0]
+                    inc   = conf.getElementsByTagName("includePath")[0]
+                    # Add bsp inc
+                    path = conf.createElement('path')
+                    path_txt = conf.createTextNode("$TUSB_DIR$/hw")
+                    path.appendChild(path_txt)
+                    inc.appendChild(path)
+                    # Add board.c/.h
+                    grp = conf.createElement('group')
+                    grp.setAttribute("name", "bsp")
+                    path = conf.createElement('path')
+                    path_txt = conf.createTextNode("$TUSB_DIR$/hw/bsp/board.c")
+                    path.appendChild(path_txt)
+                    grp.appendChild(path)
+                    files.appendChild(grp)
+                    # Add example's .c/.h
+                    grp = conf.createElement('group')
+                    grp.setAttribute("name", "example")
+                    for file in os.listdir("../examples/{}/{}/src".format(dir_2, example)):
+                        if file.endswith(".c") or file.endswith(".h"):
+                            path = conf.createElement('path')
+                            path.setAttribute("copyTo", "$PROJ_DIR$/{}".format(file))
+                            path_txt = conf.createTextNode("$TUSB_DIR$/examples/{0}/{1}/src/{2}".format(dir_2, example, file))
+                            path.appendChild(path_txt)
+                            grp.appendChild(path)
+                    files.appendChild(grp)
+                    cfg_str = conf.toprettyxml()
+                    cfg_str = '\n'.join([s for s in cfg_str.splitlines() if s.strip()])
+                    #print(cfg_str)
+                    with open("../examples/{0}/{1}/iar_{1}.ipcf".format(dir_2, example), 'w') as f:
+                        f.write(cfg_str)
+
+def ListPath(path, blacklist=[]):
+    # Get all .c files
+    files = glob.glob(f'../{path}/**/*.c', recursive=True)
+    # Filter
+    files = [x for x in files if all(y not in x for y in blacklist)]
+    # Get common dir list
+    dirs = []
+    for file in files:
+        dir = os.path.dirname(file)
+        if dir not in dirs:
+            dirs.append(dir)
+    # Print .c groupped by dir
+    for dir in dirs:
+        print('<group name="' + dir.replace('../', '').replace('\\','/') + '">')
+        for file in files:
+            if os.path.dirname(file) == dir:
+                print('    <path>$TUSB_DIR$/' + file.replace('../','').replace('\\','/')+'</path>')
+        print('</group>')
+    
+def List():
+    ListPath('src', [ 'template.c', 'dcd_synopsys.c', 'dcd_esp32sx.c' ])
+    ListPath('lib/SEGGER_RTT')
+    
+if __name__ == "__main__":
+    if (len(sys.argv) > 1):
+        if (sys.argv[1] == 'l'):
+            List()
+    else:
+        Main()
diff --git a/tools/iar_template.ipcf b/tools/iar_template.ipcf
index 6ea1d576d..4919fe7b4 100644
--- a/tools/iar_template.ipcf
+++ b/tools/iar_template.ipcf
@@ -4,166 +4,176 @@
 	<includePath>
 		<path>$TUSB_DIR$/src</path>
         <path>$TUSB_DIR$/lib/SEGGER_RTT/RTT</path>
+        <path>$TUSB_DIR$/lib/SEGGER_RTT/Config</path>
         <path>$PROJ_DIR$</path>
 	</includePath>
 	<files>
-		<group name="src/device">
-			<path>$TUSB_DIR$/src/device/usbd.c</path>
-			<path>$TUSB_DIR$/src/device/usbd_control.c</path>
-		</group>
-		<group name="src/common">
-			<path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
-		</group>
-		<group name="src/class/audio">
-			<path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
-		</group>
-		<group name="src/class/bth">
-			<path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
-		</group>
-		<group name="src/class/cdc">
-			<path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
-			<path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
-		</group>
-		<group name="src/class/dfu">
-			<path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
-			<path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
-		</group>
-		<group name="src/class/hid">
-			<path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
-			<path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
-		</group>
-		<group name="src/class/midi">
-			<path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
-		</group>
-		<group name="src/class/msc">
-			<path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
-			<path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
-		</group>
-		<group name="src/class/net">
-			<path>$TUSB_DIR$/src/class/net/ecm_rndis_device.c</path>
-			<path>$TUSB_DIR$/src/class/net/ncm_device.c</path>
-		</group>
-		<group name="src/class/usbtmc">
-			<path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
-		</group>
-		<group name="src/class/vendor">
-			<path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
-			<path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
-		</group>
         <group name="src">
             <path>$TUSB_DIR$/src/tusb.c</path>
         </group>
-		<group name="src/host">
-			<path>$TUSB_DIR$/src/host/hub.c</path>
-			<path>$TUSB_DIR$/src/host/usbh.c</path>
-		</group>
-		<group name="src/portable/bridgetek/ft9xx">
-			<path>$TUSB_DIR$/src/portable/bridgetek/ft9xx/dcd_ft9xx.c</path>
-		</group>
-		<group name="src/portable/chipidea/ci_hs">
-			<path>$TUSB_DIR$/src/portable/chipidea/ci_hs/dcd_ci_hs.c</path>
-			<path>$TUSB_DIR$/src/portable/chipidea/ci_hs/hcd_ci_hs.c</path>
-		</group>
-		<group name="src/portable/synopsys/dwc2">
-			<path>$TUSB_DIR$/src/portable/synopsys/dwc2/dcd_dwc2.c</path>
-		</group>
-		<group name="src/portable/dialog/da146xx">
-			<path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
-		</group>
-		<group name="src/portable/ehci">
-			<path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
-		</group>
-		<group name="src/portable/espressif/esp32sx">
-			<path>$TUSB_DIR$/src/portable/espressif/esp32sx/dcd_esp32sx.c</path>
-		</group>
-		<group name="src/portable/mentor/musb">
-			<path>$TUSB_DIR$/src/portable/mentor/musb/dcd_musb.c</path>
-			<path>$TUSB_DIR$/src/portable/mentor/musb/hcd_musb.c</path>
-		</group>
-		<group name="src/portable/microchip/samd">
-			<path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
-		</group>
-		<group name="src/portable/microchip/samg">
-			<path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
-		</group>
-		<group name="src/portable/microchip/samx7x">
-			<path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
-		</group>
-		<group name="src/portable/microchip/pic">
-			<path>$TUSB_DIR$/src/portable/microchip/pic/dcd_pic.c</path>
-		</group>
-		<group name="src/portable/microchip/pic32mz">
-			<path>$TUSB_DIR$/src/portable/microchip/pic32mz/dcd_pic32mz.c</path>
-		</group>
-		<group name="src/portable/mindmotion/mm32">
-			<path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
-		</group>
-		<group name="src/portable/nordic/nrf5x">
-			<path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc120">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc121">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
-		</group>
-		<group name="src/portable/nuvoton/nuc505">
-			<path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
-		</group>
-		<group name="src/portable/nxp/khci">
-			<path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/khci/hcd_khci.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc17_40">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
-		</group>
-		<group name="src/portable/nxp/lpc_ip3511">
-			<path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
-		</group>
-		<group name="src/portable/nxp/transdimension">
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/dcd_transdimension.c</path>
-			<path>$TUSB_DIR$/src/portable/nxp/transdimension/hcd_transdimension.c</path>
-		</group>
-		<group name="src/portable/ohci">
-			<path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/pio_usb">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c</path>
-		</group>
-		<group name="src/portable/raspberrypi/rp2040">
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
-			<path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
-		</group>
-		<group name="src/portable/renesas/rusb2">
-			<path>$TUSB_DIR$/src/portable/renesas/rusb2/dcd_rusb2.c</path>
-			<path>$TUSB_DIR$/src/portable/renesas/rusb2/hcd_rusb2.c</path>
-		</group>
-		<group name="src/portable/sony/cxd56">
-			<path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
-		</group>
-		<group name="src/portable/st/stm32_fsdev">
-			<path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
-		</group>
-		<group name="src/portable/sunxi">
-			<path>$TUSB_DIR$/src/portable/sunxi/dcd_sunxi_musb.c</path>
-		</group>
-		<group name="src/portable/ti/msp430x5xx">
-			<path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
-		</group>
-		<group name="src/portable/valentyusb/eptri">
-			<path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
-		</group>
-		<group name="src/portable/wch/ch32v307">
-			<path>$TUSB_DIR$/src/portable/wch/ch32v307/dcd_usbhs.c</path>
-		</group>
-        <group name="lib/SEGGER_RTT">
-			<path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
+        <group name="src/class/audio">
+            <path>$TUSB_DIR$/src/class/audio/audio_device.c</path>
+        </group>
+        <group name="src/class/bth">
+            <path>$TUSB_DIR$/src/class/bth/bth_device.c</path>
+        </group>
+        <group name="src/class/cdc">
+            <path>$TUSB_DIR$/src/class/cdc/cdc_device.c</path>
+            <path>$TUSB_DIR$/src/class/cdc/cdc_host.c</path>
+            <path>$TUSB_DIR$/src/class/cdc/cdc_rndis_host.c</path>
+        </group>
+        <group name="src/class/dfu">
+            <path>$TUSB_DIR$/src/class/dfu/dfu_device.c</path>
+            <path>$TUSB_DIR$/src/class/dfu/dfu_rt_device.c</path>
+        </group>
+        <group name="src/class/hid">
+            <path>$TUSB_DIR$/src/class/hid/hid_device.c</path>
+            <path>$TUSB_DIR$/src/class/hid/hid_host.c</path>
+        </group>
+        <group name="src/class/midi">
+            <path>$TUSB_DIR$/src/class/midi/midi_device.c</path>
+        </group>
+        <group name="src/class/msc">
+            <path>$TUSB_DIR$/src/class/msc/msc_device.c</path>
+            <path>$TUSB_DIR$/src/class/msc/msc_host.c</path>
+        </group>
+        <group name="src/class/net">
+            <path>$TUSB_DIR$/src/class/net/ecm_rndis_device.c</path>
+            <path>$TUSB_DIR$/src/class/net/ncm_device.c</path>
+        </group>
+        <group name="src/class/usbtmc">
+            <path>$TUSB_DIR$/src/class/usbtmc/usbtmc_device.c</path>
+        </group>
+        <group name="src/class/vendor">
+            <path>$TUSB_DIR$/src/class/vendor/vendor_device.c</path>
+            <path>$TUSB_DIR$/src/class/vendor/vendor_host.c</path>
+        </group>
+        <group name="src/class/video">
+            <path>$TUSB_DIR$/src/class/video/video_device.c</path>
+        </group>
+        <group name="src/common">
+            <path>$TUSB_DIR$/src/common/tusb_fifo.c</path>
+        </group>
+        <group name="src/device">
+            <path>$TUSB_DIR$/src/device/usbd.c</path>
+            <path>$TUSB_DIR$/src/device/usbd_control.c</path>
+        </group>
+        <group name="src/host">
+            <path>$TUSB_DIR$/src/host/hub.c</path>
+            <path>$TUSB_DIR$/src/host/usbh.c</path>
+        </group>
+        <group name="src/portable/analog/max3421">
+            <path>$TUSB_DIR$/src/portable/analog/max3421/hcd_max3421.c</path>
+        </group>
+        <group name="src/portable/bridgetek/ft9xx">
+            <path>$TUSB_DIR$/src/portable/bridgetek/ft9xx/dcd_ft9xx.c</path>
+        </group>
+        <group name="src/portable/chipidea/ci_fs">
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_fs/dcd_ci_fs.c</path>
+        </group>
+        <group name="src/portable/chipidea/ci_hs">
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_hs/dcd_ci_hs.c</path>
+            <path>$TUSB_DIR$/src/portable/chipidea/ci_hs/hcd_ci_hs.c</path>
+        </group>
+        <group name="src/portable/dialog/da146xx">
+            <path>$TUSB_DIR$/src/portable/dialog/da146xx/dcd_da146xx.c</path>
+        </group>
+        <group name="src/portable/ehci">
+            <path>$TUSB_DIR$/src/portable/ehci/ehci.c</path>
+        </group>
+        <group name="src/portable/mentor/musb">
+            <path>$TUSB_DIR$/src/portable/mentor/musb/dcd_musb.c</path>
+            <path>$TUSB_DIR$/src/portable/mentor/musb/hcd_musb.c</path>
+        </group>
+        <group name="src/portable/microchip/pic">
+            <path>$TUSB_DIR$/src/portable/microchip/pic/dcd_pic.c</path>
+        </group>
+        <group name="src/portable/microchip/pic32mz">
+            <path>$TUSB_DIR$/src/portable/microchip/pic32mz/dcd_pic32mz.c</path>
+        </group>
+        <group name="src/portable/microchip/samd">
+            <path>$TUSB_DIR$/src/portable/microchip/samd/dcd_samd.c</path>
+        </group>
+        <group name="src/portable/microchip/samg">
+            <path>$TUSB_DIR$/src/portable/microchip/samg/dcd_samg.c</path>
+        </group>
+        <group name="src/portable/microchip/samx7x">
+            <path>$TUSB_DIR$/src/portable/microchip/samx7x/dcd_samx7x.c</path>
+        </group>
+        <group name="src/portable/mindmotion/mm32">
+            <path>$TUSB_DIR$/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c</path>
+        </group>
+        <group name="src/portable/nordic/nrf5x">
+            <path>$TUSB_DIR$/src/portable/nordic/nrf5x/dcd_nrf5x.c</path>
+        </group>
+        <group name="src/portable/nuvoton/nuc120">
+            <path>$TUSB_DIR$/src/portable/nuvoton/nuc120/dcd_nuc120.c</path>
+        </group>
+        <group name="src/portable/nuvoton/nuc121">
+            <path>$TUSB_DIR$/src/portable/nuvoton/nuc121/dcd_nuc121.c</path>
+        </group>
+        <group name="src/portable/nuvoton/nuc505">
+            <path>$TUSB_DIR$/src/portable/nuvoton/nuc505/dcd_nuc505.c</path>
+        </group>
+        <group name="src/portable/nxp/khci">
+            <path>$TUSB_DIR$/src/portable/nxp/khci/dcd_khci.c</path>
+            <path>$TUSB_DIR$/src/portable/nxp/khci/hcd_khci.c</path>
+        </group>
+        <group name="src/portable/nxp/lpc17_40">
+            <path>$TUSB_DIR$/src/portable/nxp/lpc17_40/dcd_lpc17_40.c</path>
+            <path>$TUSB_DIR$/src/portable/nxp/lpc17_40/hcd_lpc17_40.c</path>
+        </group>
+        <group name="src/portable/nxp/lpc_ip3511">
+            <path>$TUSB_DIR$/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c</path>
+        </group>
+        <group name="src/portable/ohci">
+            <path>$TUSB_DIR$/src/portable/ohci/ohci.c</path>
+        </group>
+        <group name="src/portable/raspberrypi/pio_usb">
+            <path>$TUSB_DIR$/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c</path>
+            <path>$TUSB_DIR$/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c</path>
+        </group>
+        <group name="src/portable/raspberrypi/rp2040">
+            <path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/dcd_rp2040.c</path>
+            <path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/hcd_rp2040.c</path>
+            <path>$TUSB_DIR$/src/portable/raspberrypi/rp2040/rp2040_usb.c</path>
+        </group>
+        <group name="src/portable/renesas/rusb2">
+            <path>$TUSB_DIR$/src/portable/renesas/rusb2/dcd_rusb2.c</path>
+            <path>$TUSB_DIR$/src/portable/renesas/rusb2/hcd_rusb2.c</path>
+            <path>$TUSB_DIR$/src/portable/renesas/rusb2/rusb2_common.c</path>
+        </group>
+        <group name="src/portable/sony/cxd56">
+            <path>$TUSB_DIR$/src/portable/sony/cxd56/dcd_cxd56.c</path>
+        </group>
+        <group name="src/portable/st/stm32_fsdev">
+            <path>$TUSB_DIR$/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c</path>
+        </group>
+        <group name="src/portable/st/typec">
+            <path>$TUSB_DIR$/src/portable/st/typec/typec_stm32.c</path>
+        </group>
+        <group name="src/portable/sunxi">
+            <path>$TUSB_DIR$/src/portable/sunxi/dcd_sunxi_musb.c</path>
+        </group>
+        <group name="src/portable/synopsys/dwc2">
+            <path>$TUSB_DIR$/src/portable/synopsys/dwc2/dcd_dwc2.c</path>
+        </group>
+        <group name="src/portable/ti/msp430x5xx">
+            <path>$TUSB_DIR$/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c</path>
+        </group>
+        <group name="src/portable/valentyusb/eptri">
+            <path>$TUSB_DIR$/src/portable/valentyusb/eptri/dcd_eptri.c</path>
+        </group>
+        <group name="src/portable/wch/ch32v307">
+            <path>$TUSB_DIR$/src/portable/wch/ch32v307/dcd_usbhs.c</path>
+        </group>
+        <group name="src/typec">
+            <path>$TUSB_DIR$/src/typec/usbc.c</path>
+        </group>
+        <group name="lib/SEGGER_RTT/RTT">
+            <path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT.c</path>
             <path>$TUSB_DIR$/lib/SEGGER_RTT/RTT/SEGGER_RTT_printf.c</path>
-            <path>$TUSB_DIR$/lib/SEGGER_RTT/Syscalls/SEGGER_RTT_Syscalls_IAR.c</path>
-		</group>
+        </group>
     </files>
 
 </iarProjectConnection>

From 42eb4e0da0f5218d43ef81631bbbe2f369cc13fa Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 27 Sep 2023 11:46:52 +0200
Subject: [PATCH 2062/2085] Fix CI.

---
 tools/iar_gen.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tools/iar_gen.py b/tools/iar_gen.py
index 646a581f4..264dd9a58 100644
--- a/tools/iar_gen.py
+++ b/tools/iar_gen.py
@@ -64,18 +64,18 @@ def ListPath(path, blacklist=[]):
         dir = os.path.dirname(file)
         if dir not in dirs:
             dirs.append(dir)
-    # Print .c groupped by dir
+    # Print .c grouped by dir
     for dir in dirs:
         print('<group name="' + dir.replace('../', '').replace('\\','/') + '">')
         for file in files:
             if os.path.dirname(file) == dir:
                 print('    <path>$TUSB_DIR$/' + file.replace('../','').replace('\\','/')+'</path>')
         print('</group>')
-    
+
 def List():
     ListPath('src', [ 'template.c', 'dcd_synopsys.c', 'dcd_esp32sx.c' ])
     ListPath('lib/SEGGER_RTT')
-    
+
 if __name__ == "__main__":
     if (len(sys.argv) > 1):
         if (sys.argv[1] == 'l'):

From 3a10b6a3d55e76020d0fdb6adb937f98df5638e1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Sep 2023 18:09:19 +0700
Subject: [PATCH 2063/2085] fix esp32 build

---
 hw/bsp/espressif/boards/family.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 5226f7e61..e4c2c3414 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -186,7 +186,7 @@ static void max3421_intr_task(void* param) {
 
   while (1) {
     xSemaphoreTake(max3421_intr_sem, portMAX_DELAY);
-    hcd_int_handler_ext(BOARD_TUH_RHPORT, false);
+    tuh_int_handler(BOARD_TUH_RHPORT, false);
   }
 }
 

From 10abece264e3d5a4551be750f3c726890598a40b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 27 Sep 2023 18:15:20 +0700
Subject: [PATCH 2064/2085] esp32 hid device work well

---
 hw/bsp/espressif/boards/family.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index e4c2c3414..4d2cab9e8 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -224,7 +224,7 @@ static void max3421_init(void) {
 
   // Interrupt pin
   max3421_intr_sem = xSemaphoreCreateBinary();
-  xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES-1, NULL);
+  xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES-2, NULL);
 
   gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
   gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);

From 277852afc1798f2acdb61917984e76b4bafa699e Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Sep 2023 10:56:38 +0700
Subject: [PATCH 2065/2085] fix esp32 msc example

---
 .../host/cdc_msc_hid_freertos/src/cdc_app.c   |   8 +-
 .../host/cdc_msc_hid_freertos/src/hid_app.c   |   4 +
 examples/host/cdc_msc_hid_freertos/src/main.c |  12 +-
 .../host/cdc_msc_hid_freertos/src/msc_app.c   |   8 +-
 src/class/msc/msc_host.c                      | 265 ++++++++----------
 src/class/msc/msc_host.h                      |   8 +-
 src/host/usbh.c                               |  22 +-
 7 files changed, 151 insertions(+), 176 deletions(-)

diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
index 943e534d8..91dcc2e1a 100644
--- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
@@ -31,9 +31,7 @@
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
 
-
-//------------- IMPLEMENTATION -------------//
-
+// helper
 size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
   size_t count = 0;
   while (count < bufsize) {
@@ -47,6 +45,10 @@ size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
   return count;
 }
 
+void cdc_app_init(void) {
+  // nothing to do
+}
+
 void cdc_app_task(void* param) {
   (void) param;
 
diff --git a/examples/host/cdc_msc_hid_freertos/src/hid_app.c b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
index a2df3b909..9ea5c1be0 100644
--- a/examples/host/cdc_msc_hid_freertos/src/hid_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/hid_app.c
@@ -48,6 +48,10 @@ static void process_kbd_report(hid_keyboard_report_t const *report);
 static void process_mouse_report(hid_mouse_report_t const *report);
 static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len);
 
+void hid_app_init(void) {
+  // nothing to do
+}
+
 //--------------------------------------------------------------------+
 // TinyUSB Callbacks
 //--------------------------------------------------------------------+
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
index 88e742ee2..b60be015b 100644
--- a/examples/host/cdc_msc_hid_freertos/src/main.c
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -82,10 +82,15 @@ StaticTask_t cdc_taskdef;
 TimerHandle_t blinky_tm;
 
 static void led_blinky_cb(TimerHandle_t xTimer);
-static void usb_host_task(void* param);
+extern void cdc_app_init(void);
+extern void hid_app_init(void);
+extern void msc_app_init(void);
 
+static void usb_host_task(void* param);
 extern void cdc_app_task(void* param);
 
+
+
 /*------------- MAIN -------------*/
 int main(void) {
   board_init();
@@ -131,6 +136,10 @@ static void usb_host_task(void *param) {
     board_init_after_tusb();
   }
 
+  cdc_app_init();
+  hid_app_init();
+  msc_app_init();
+
   // RTOS forever loop
   while (1) {
     // put this thread to waiting state until there is new events
@@ -154,7 +163,6 @@ void tuh_umount_cb(uint8_t dev_addr) {
   printf("A device with address %d is unmounted \r\n", dev_addr);
 }
 
-
 //--------------------------------------------------------------------+
 // BLINKING TASK
 //--------------------------------------------------------------------+
diff --git a/examples/host/cdc_msc_hid_freertos/src/msc_app.c b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
index a8d6fbfaa..ee02ba917 100644
--- a/examples/host/cdc_msc_hid_freertos/src/msc_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/msc_app.c
@@ -25,10 +25,12 @@
 
 #include "tusb.h"
 
-#if CFG_TUH_MSC
-
 static scsi_inquiry_resp_t inquiry_resp;
 
+void msc_app_init(void) {
+  // nothing to do
+}
+
 bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_data) {
   msc_cbw_t const *cbw = cb_data->cbw;
   msc_csw_t const *csw = cb_data->csw;
@@ -63,5 +65,3 @@ void tuh_msc_umount_cb(uint8_t dev_addr) {
   (void) dev_addr;
   printf("A MassStorage device is unmounted\r\n");
 }
-
-#endif
diff --git a/src/class/msc/msc_host.c b/src/class/msc/msc_host.c
index da264142c..39f2d9f1c 100644
--- a/src/class/msc/msc_host.c
+++ b/src/class/msc/msc_host.c
@@ -43,16 +43,14 @@
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF
 //--------------------------------------------------------------------+
-enum
-{
+enum {
   MSC_STAGE_IDLE = 0,
   MSC_STAGE_CMD,
   MSC_STAGE_DATA,
   MSC_STAGE_STATUS,
 };
 
-typedef struct
-{
+typedef struct {
   uint8_t itf_num;
   uint8_t ep_in;
   uint8_t ep_out;
@@ -69,13 +67,13 @@ typedef struct
 
   //------------- SCSI -------------//
   uint8_t stage;
-  void*   buffer;
+  void* buffer;
   tuh_msc_complete_cb_t complete_cb;
   uintptr_t complete_arg;
 
   CFG_TUH_MEM_ALIGN msc_cbw_t cbw;
   CFG_TUH_MEM_ALIGN msc_csw_t csw;
-}msch_interface_t;
+} msch_interface_t;
 
 CFG_TUH_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
 
@@ -86,40 +84,34 @@ static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)];
 
 // FIXME potential nul reference
 TU_ATTR_ALWAYS_INLINE
-static inline msch_interface_t* get_itf(uint8_t dev_addr)
-{
-  return &_msch_itf[dev_addr-1];
+static inline msch_interface_t* get_itf(uint8_t dev_addr) {
+  return &_msch_itf[dev_addr - 1];
 }
 
 //--------------------------------------------------------------------+
 // PUBLIC API
 //--------------------------------------------------------------------+
-uint8_t tuh_msc_get_maxlun(uint8_t dev_addr)
-{
+uint8_t tuh_msc_get_maxlun(uint8_t dev_addr) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->max_lun;
 }
 
-uint32_t tuh_msc_get_block_count(uint8_t dev_addr, uint8_t lun)
-{
+uint32_t tuh_msc_get_block_count(uint8_t dev_addr, uint8_t lun) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->capacity[lun].block_count;
 }
 
-uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun)
-{
+uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->capacity[lun].block_size;
 }
 
-bool tuh_msc_mounted(uint8_t dev_addr)
-{
+bool tuh_msc_mounted(uint8_t dev_addr) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->mounted;
 }
 
-bool tuh_msc_ready(uint8_t dev_addr)
-{
+bool tuh_msc_ready(uint8_t dev_addr) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   return p_msc->mounted && !usbh_edpt_busy(dev_addr, p_msc->ep_in) && !usbh_edpt_busy(dev_addr, p_msc->ep_out);
 }
@@ -127,20 +119,20 @@ bool tuh_msc_ready(uint8_t dev_addr)
 //--------------------------------------------------------------------+
 // PUBLIC API: SCSI COMMAND
 //--------------------------------------------------------------------+
-static inline void cbw_init(msc_cbw_t *cbw, uint8_t lun)
-{
+static inline void cbw_init(msc_cbw_t* cbw, uint8_t lun) {
   tu_memclr(cbw, sizeof(msc_cbw_t));
   cbw->signature = MSC_CBW_SIGNATURE;
   cbw->tag       = 0x54555342; // TUSB
   cbw->lun       = lun;
 }
 
-bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
-  msch_interface_t* p_msc = get_itf(dev_addr);
+bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data,
+                          tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
+  msch_interface_t* p_msc = get_itf(daddr);
   TU_VERIFY(p_msc->configured);
 
-  // TODO claim endpoint
+  // claim endpoint
+  TU_VERIFY(usbh_edpt_claim(daddr, p_msc->ep_out));
 
   p_msc->cbw = *cbw;
   p_msc->stage = MSC_STAGE_CMD;
@@ -148,15 +140,18 @@ bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tu
   p_msc->complete_cb = complete_cb;
   p_msc->complete_arg = arg;
 
-  TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)));
+  if (!usbh_edpt_xfer(daddr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t))) {
+    usbh_edpt_release(daddr, p_msc->ep_out);
+    return false;
+  }
 
   return true;
 }
 
-bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
-   msch_interface_t* p_msc = get_itf(dev_addr);
-   TU_VERIFY(p_msc->configured);
+bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_resp_t* response,
+                           tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
+  msch_interface_t* p_msc = get_itf(dev_addr);
+  TU_VERIFY(p_msc->configured);
 
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
@@ -169,8 +164,8 @@ bool tuh_msc_read_capacity(uint8_t dev_addr, uint8_t lun, scsi_read_capacity10_r
   return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
+bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response,
+                     tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
 
@@ -181,18 +176,16 @@ bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* respons
   cbw.dir         = TUSB_DIR_IN_MASK;
   cbw.cmd_len     = sizeof(scsi_inquiry_t);
 
-  scsi_inquiry_t const cmd_inquiry =
-  {
-    .cmd_code     = SCSI_CMD_INQUIRY,
-    .alloc_length = sizeof(scsi_inquiry_resp_t)
+  scsi_inquiry_t const cmd_inquiry = {
+      .cmd_code     = SCSI_CMD_INQUIRY,
+      .alloc_length = sizeof(scsi_inquiry_resp_t)
   };
   memcpy(cbw.command, &cmd_inquiry, cbw.cmd_len);
 
   return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
+bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->configured);
 
@@ -200,16 +193,16 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_
   cbw_init(&cbw, lun);
 
   cbw.total_bytes = 0;
-  cbw.dir         = TUSB_DIR_OUT;
-  cbw.cmd_len     = sizeof(scsi_test_unit_ready_t);
-  cbw.command[0]  = SCSI_CMD_TEST_UNIT_READY;
-  cbw.command[1]  = lun; // according to wiki TODO need verification
+  cbw.dir        = TUSB_DIR_OUT;
+  cbw.cmd_len    = sizeof(scsi_test_unit_ready_t);
+  cbw.command[0] = SCSI_CMD_TEST_UNIT_READY;
+  cbw.command[1] = lun; // according to wiki TODO need verification
 
   return tuh_msc_scsi_command(dev_addr, &cbw, NULL, complete_cb, arg);
 }
 
-bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
+bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void* response,
+                           tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
 
@@ -217,73 +210,64 @@ bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_ms
   cbw.dir         = TUSB_DIR_IN_MASK;
   cbw.cmd_len     = sizeof(scsi_request_sense_t);
 
-  scsi_request_sense_t const cmd_request_sense =
-  {
-    .cmd_code     = SCSI_CMD_REQUEST_SENSE,
-    .alloc_length = 18
+  scsi_request_sense_t const cmd_request_sense = {
+      .cmd_code     = SCSI_CMD_REQUEST_SENSE,
+      .alloc_length = 18
   };
-
   memcpy(cbw.command, &cmd_request_sense, cbw.cmd_len);
 
   return tuh_msc_scsi_command(dev_addr, &cbw, response, complete_cb, arg);
 }
 
-bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
+bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void* buffer, uint32_t lba, uint16_t block_count,
+                    tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
 
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
 
-  cbw.total_bytes = block_count*p_msc->capacity[lun].block_size;
-  cbw.dir         = TUSB_DIR_IN_MASK;
-  cbw.cmd_len     = sizeof(scsi_read10_t);
+  cbw.total_bytes = block_count * p_msc->capacity[lun].block_size;
+  cbw.dir = TUSB_DIR_IN_MASK;
+  cbw.cmd_len = sizeof(scsi_read10_t);
 
-  scsi_read10_t const cmd_read10 =
-  {
-    .cmd_code    = SCSI_CMD_READ_10,
-    .lba         = tu_htonl(lba),
-    .block_count = tu_htons(block_count)
+  scsi_read10_t const cmd_read10 = {
+      .cmd_code    = SCSI_CMD_READ_10,
+      .lba         = tu_htonl(lba),
+      .block_count = tu_htons(block_count)
   };
-
   memcpy(cbw.command, &cmd_read10, cbw.cmd_len);
 
   return tuh_msc_scsi_command(dev_addr, &cbw, buffer, complete_cb, arg);
 }
 
-bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg)
-{
+bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const* buffer, uint32_t lba, uint16_t block_count,
+                     tuh_msc_complete_cb_t complete_cb, uintptr_t arg) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   TU_VERIFY(p_msc->mounted);
 
   msc_cbw_t cbw;
   cbw_init(&cbw, lun);
 
-  cbw.total_bytes = block_count*p_msc->capacity[lun].block_size;
+  cbw.total_bytes = block_count * p_msc->capacity[lun].block_size;
   cbw.dir         = TUSB_DIR_OUT;
   cbw.cmd_len     = sizeof(scsi_write10_t);
 
-  scsi_write10_t const cmd_write10 =
-  {
-    .cmd_code    = SCSI_CMD_WRITE_10,
-    .lba         = tu_htonl(lba),
-    .block_count = tu_htons(block_count)
+  scsi_write10_t const cmd_write10 = {
+      .cmd_code    = SCSI_CMD_WRITE_10,
+      .lba         = tu_htonl(lba),
+      .block_count = tu_htons(block_count)
   };
-
   memcpy(cbw.command, &cmd_write10, cbw.cmd_len);
 
-  return tuh_msc_scsi_command(dev_addr, &cbw, (void*)(uintptr_t) buffer, complete_cb, arg);
+  return tuh_msc_scsi_command(dev_addr, &cbw, (void*) (uintptr_t) buffer, complete_cb, arg);
 }
 
 #if 0
 // MSC interface Reset (not used now)
-bool tuh_msc_reset(uint8_t dev_addr)
-{
-  tusb_control_request_t const new_request =
-  {
-    .bmRequestType_bit =
-    {
+bool tuh_msc_reset(uint8_t dev_addr) {
+  tusb_control_request_t const new_request = {
+    .bmRequestType_bit = {
       .recipient = TUSB_REQ_RCPT_INTERFACE,
       .type      = TUSB_REQ_TYPE_CLASS,
       .direction = TUSB_DIR_OUT
@@ -300,79 +284,71 @@ bool tuh_msc_reset(uint8_t dev_addr)
 //--------------------------------------------------------------------+
 // CLASS-USBH API
 //--------------------------------------------------------------------+
-void msch_init(void)
-{
+void msch_init(void) {
   tu_memclr(_msch_itf, sizeof(_msch_itf));
 }
 
-void msch_close(uint8_t dev_addr)
-{
-  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
+void msch_close(uint8_t dev_addr) {
+  TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX,);
   msch_interface_t* p_msc = get_itf(dev_addr);
-  TU_VERIFY(p_msc->configured, );
+  TU_VERIFY(p_msc->configured,);
 
   TU_LOG_DRV("  MSCh close addr = %d\r\n", dev_addr);
 
   // invoke Application Callback
   if (p_msc->mounted) {
-    if(tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr);
+    if (tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr);
   }
 
   tu_memclr(p_msc, sizeof(msch_interface_t));
 }
 
-bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
-{
+bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) {
   msch_interface_t* p_msc = get_itf(dev_addr);
   msc_cbw_t const * cbw = &p_msc->cbw;
   msc_csw_t       * csw = &p_msc->csw;
 
-  switch (p_msc->stage)
-  {
+  switch (p_msc->stage) {
     case MSC_STAGE_CMD:
       // Must be Command Block
-      TU_ASSERT(ep_addr == p_msc->ep_out &&  event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
+      TU_ASSERT(ep_addr == p_msc->ep_out && event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
 
-      if ( cbw->total_bytes && p_msc->buffer )
-      {
+      if (cbw->total_bytes && p_msc->buffer) {
         // Data stage if any
         p_msc->stage = MSC_STAGE_DATA;
-
         uint8_t const ep_data = (cbw->dir & TUSB_DIR_IN_MASK) ? p_msc->ep_in : p_msc->ep_out;
         TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, (uint16_t) cbw->total_bytes));
-      }else
-      {
+      } else {
         // Status stage
         p_msc->stage = MSC_STAGE_STATUS;
         TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
       }
-    break;
+      break;
 
     case MSC_STAGE_DATA:
       // Status stage
       p_msc->stage = MSC_STAGE_STATUS;
       TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
-    break;
+      break;
 
     case MSC_STAGE_STATUS:
       // SCSI op is complete
       p_msc->stage = MSC_STAGE_IDLE;
 
-      if (p_msc->complete_cb)
-      {
-        tuh_msc_complete_data_t const cb_data =
-        {
-          .cbw = cbw,
-          .csw = csw,
-          .scsi_data = p_msc->buffer,
-          .user_arg = p_msc->complete_arg
+      if (p_msc->complete_cb) {
+        tuh_msc_complete_data_t const cb_data = {
+            .cbw = cbw,
+            .csw = csw,
+            .scsi_data = p_msc->buffer,
+            .user_arg = p_msc->complete_arg
         };
         p_msc->complete_cb(dev_addr, &cb_data);
       }
-    break;
+      break;
 
-    // unknown state
-    default: break;
+      // unknown state
+    default:
+      break;
   }
 
   return true;
@@ -381,39 +357,35 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
 //--------------------------------------------------------------------+
 // MSC Enumeration
 //--------------------------------------------------------------------+
-
-static void config_get_maxlun_complete (tuh_xfer_t* xfer);
-static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data);
+static void config_get_maxlun_complete(tuh_xfer_t* xfer);
+static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
 static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
 static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data);
 
-bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len)
-{
+bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* desc_itf, uint16_t max_len) {
   (void) rhport;
   TU_VERIFY (MSC_SUBCLASS_SCSI == desc_itf->bInterfaceSubClass &&
-             MSC_PROTOCOL_BOT  == desc_itf->bInterfaceProtocol);
+             MSC_PROTOCOL_BOT == desc_itf->bInterfaceProtocol);
 
   // msc driver length is fixed
-  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
+  uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) +
+                                       desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t));
   TU_ASSERT(drv_len <= max_len);
 
   msch_interface_t* p_msc = get_itf(dev_addr);
-  tusb_desc_endpoint_t const * ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(desc_itf);
+  tusb_desc_endpoint_t const* ep_desc = (tusb_desc_endpoint_t const*) tu_desc_next(desc_itf);
 
-  for(uint32_t i=0; i<2; i++)
-  {
+  for (uint32_t i = 0; i < 2; i++) {
     TU_ASSERT(TUSB_DESC_ENDPOINT == ep_desc->bDescriptorType && TUSB_XFER_BULK == ep_desc->bmAttributes.xfer);
     TU_ASSERT(tuh_edpt_open(dev_addr, ep_desc));
 
-    if ( tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN )
-    {
+    if (TUSB_DIR_IN == tu_edpt_dir(ep_desc->bEndpointAddress)) {
       p_msc->ep_in = ep_desc->bEndpointAddress;
-    }else
-    {
+    } else {
       p_msc->ep_out = ep_desc->bEndpointAddress;
     }
 
-    ep_desc = (tusb_desc_endpoint_t const *) tu_desc_next(ep_desc);
+    ep_desc = (tusb_desc_endpoint_t const*) tu_desc_next(ep_desc);
   }
 
   p_msc->itf_num = desc_itf->bInterfaceNumber;
@@ -430,32 +402,31 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) {
   //------------- Get Max Lun -------------//
   TU_LOG_DRV("MSC Get Max Lun\r\n");
   tusb_control_request_t const request = {
-    .bmRequestType_bit = {
-      .recipient = TUSB_REQ_RCPT_INTERFACE,
-      .type      = TUSB_REQ_TYPE_CLASS,
-      .direction = TUSB_DIR_IN
-    },
-    .bRequest = MSC_REQ_GET_MAX_LUN,
-    .wValue   = 0,
-    .wIndex   = itf_num,
-    .wLength  = 1
+      .bmRequestType_bit = {
+          .recipient = TUSB_REQ_RCPT_INTERFACE,
+          .type      = TUSB_REQ_TYPE_CLASS,
+          .direction = TUSB_DIR_IN
+      },
+      .bRequest = MSC_REQ_GET_MAX_LUN,
+      .wValue   = 0,
+      .wIndex   = itf_num,
+      .wLength  = 1
   };
 
   tuh_xfer_t xfer = {
-    .daddr       = dev_addr,
-    .ep_addr     = 0,
-    .setup       = &request,
-    .buffer      = _msch_buffer,
-    .complete_cb = config_get_maxlun_complete,
-    .user_data    = 0
+      .daddr       = dev_addr,
+      .ep_addr     = 0,
+      .setup       = &request,
+      .buffer      = _msch_buffer,
+      .complete_cb = config_get_maxlun_complete,
+      .user_data    = 0
   };
   TU_ASSERT(tuh_control_xfer(&xfer));
 
   return true;
 }
 
-static void config_get_maxlun_complete (tuh_xfer_t* xfer)
-{
+static void config_get_maxlun_complete(tuh_xfer_t* xfer) {
   uint8_t const daddr = xfer->daddr;
   msch_interface_t* p_msc = get_itf(daddr);
 
@@ -471,18 +442,16 @@ static void config_get_maxlun_complete (tuh_xfer_t* xfer)
   tuh_msc_test_unit_ready(daddr, lun, config_test_unit_ready_complete, 0);
 }
 
-static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
-{
+static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
   msc_cbw_t const* cbw = cb_data->cbw;
   msc_csw_t const* csw = cb_data->csw;
 
-  if (csw->status == 0)
-  {
+  if (csw->status == 0) {
     // Unit is ready, read its capacity
     TU_LOG_DRV("SCSI Read Capacity\r\n");
-    tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer), config_read_capacity_complete, 0);
-  }else
-  {
+    tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer),
+                          config_read_capacity_complete, 0);
+  } else {
     // Note: During enumeration, some device fails Test Unit Ready and require a few retries
     // with Request Sense to start working !!
     // TODO limit number of retries
@@ -493,8 +462,7 @@ static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_d
   return true;
 }
 
-static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
-{
+static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
   msc_cbw_t const* cbw = cb_data->cbw;
   msc_csw_t const* csw = cb_data->csw;
 
@@ -503,8 +471,7 @@ static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_dat
   return true;
 }
 
-static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data)
-{
+static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
   msc_cbw_t const* cbw = cb_data->cbw;
   msc_csw_t const* csw = cb_data->csw;
 
diff --git a/src/class/msc/msc_host.h b/src/class/msc/msc_host.h
index 6c0e5c9dd..9ca1b4703 100644
--- a/src/class/msc/msc_host.h
+++ b/src/class/msc/msc_host.h
@@ -24,8 +24,8 @@
  * This file is part of the TinyUSB stack.
  */
 
-#ifndef _TUSB_MSC_HOST_H_
-#define _TUSB_MSC_HOST_H_
+#ifndef TUSB_MSC_HOST_H_
+#define TUSB_MSC_HOST_H_
 
 #include "msc.h"
 
@@ -73,7 +73,7 @@ uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun);
 // Perform a full SCSI command (cbw, data, csw) in non-blocking manner.
 // Complete callback is invoked when SCSI op is complete.
 // return true if success, false if there is already pending operation.
-bool tuh_msc_scsi_command(uint8_t dev_addr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
+bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
 
 // Perform SCSI Inquiry command
 // Complete callback is invoked when SCSI op is complete.
@@ -123,4 +123,4 @@ bool msch_xfer_cb    (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, ui
  }
 #endif
 
-#endif /* _TUSB_MSC_HOST_H_ */
+#endif
diff --git a/src/host/usbh.c b/src/host/usbh.c
index e332f35cc..8d75c9726 100644
--- a/src/host/usbh.c
+++ b/src/host/usbh.c
@@ -817,6 +817,7 @@ bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
 }
 
 // Submit an transfer
+// TODO call usbh_edpt_release if failed
 bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes,
                                   tuh_xfer_cb_t complete_cb, uintptr_t user_data)
 {
@@ -1713,19 +1714,16 @@ static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configur
   return true;
 }
 
-void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
-{
+void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) {
   usbh_device_t* dev = get_device(dev_addr);
 
-  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++)
-  {
+  for(itf_num++; itf_num < CFG_TUH_INTERFACE_MAX; itf_num++) {
     // continue with next valid interface
     // IAD binding interface such as CDCs should return itf_num + 1 when complete
     // with usbh_driver_set_config_complete()
     uint8_t const drv_id = dev->itf2drv[itf_num];
     usbh_class_driver_t const * driver = get_driver(drv_id);
-    if (driver)
-    {
+    if (driver) {
       TU_LOG_USBH("%s set config: itf = %u\r\n", driver->name, itf_num);
       driver->set_config(dev_addr, itf_num);
       break;
@@ -1733,23 +1731,19 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
   }
 
   // all interface are configured
-  if (itf_num == CFG_TUH_INTERFACE_MAX)
-  {
+  if (itf_num == CFG_TUH_INTERFACE_MAX) {
     enum_full_complete();
 
-    if (is_hub_addr(dev_addr))
-    {
+    if (is_hub_addr(dev_addr)) {
       TU_LOG(CFG_TUH_LOG_LEVEL, "HUB address = %u is mounted\r\n", dev_addr);
-    }else
-    {
+    }else {
       // Invoke callback if available
       if (tuh_mount_cb) tuh_mount_cb(dev_addr);
     }
   }
 }
 
-static void enum_full_complete(void)
-{
+static void enum_full_complete(void) {
   // mark enumeration as complete
   _dev0.enumerating = 0;
 

From 7dc1a66f917408992cf672009a307f7200a3fd32 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Sep 2023 11:12:22 +0700
Subject: [PATCH 2066/2085] esp32 cdc host with max3421 work well

---
 .../host/cdc_msc_hid_freertos/src/cdc_app.c   | 44 ++++++++++++++++---
 examples/host/cdc_msc_hid_freertos/src/main.c | 16 ++-----
 hw/bsp/espressif/boards/family.c              | 20 +++++++--
 3 files changed, 58 insertions(+), 22 deletions(-)

diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
index 91dcc2e1a..6ff513be1 100644
--- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
+++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c
@@ -27,9 +27,43 @@
 #include "tusb.h"
 #include "bsp/board_api.h"
 
+#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)
+// ESP-IDF need "freertos/" prefix in include path.
+// CFG_TUSB_OS_INC_PATH should be defined accordingly.
+  #include "freertos/FreeRTOS.h"
+  #include "freertos/semphr.h"
+  #include "freertos/queue.h"
+  #include "freertos/task.h"
+  #include "freertos/timers.h"
+
+  #define CDC_STACK_SZIE      2048
+#else
+  #include "FreeRTOS.h"
+  #include "semphr.h"
+  #include "queue.h"
+  #include "task.h"
+  #include "timers.h"
+
+  #define CDC_STACK_SZIE     (3*configMINIMAL_STACK_SIZE/2)
+#endif
+
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM DECLARATION
 //--------------------------------------------------------------------+
+#if configSUPPORT_STATIC_ALLOCATION
+StackType_t  cdc_stack[CDC_STACK_SZIE];
+StaticTask_t cdc_taskdef;
+#endif
+
+static void cdc_app_task(void* param);
+
+void cdc_app_init(void) {
+  #if configSUPPORT_STATIC_ALLOCATION
+  xTaskCreateStatic(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
+  #else
+  xTaskCreate(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
+  #endif
+}
 
 // helper
 size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
@@ -45,11 +79,7 @@ size_t get_console_inputs(uint8_t *buf, size_t bufsize) {
   return count;
 }
 
-void cdc_app_init(void) {
-  // nothing to do
-}
-
-void cdc_app_task(void* param) {
+static void cdc_app_task(void* param) {
   (void) param;
 
   uint8_t buf[64 + 1]; // +1 for extra null character
@@ -74,6 +104,10 @@ void cdc_app_task(void* param) {
   }
 }
 
+//--------------------------------------------------------------------+
+// TinyUSB Callbacks
+//--------------------------------------------------------------------+
+
 // Invoked when received new data
 void tuh_cdc_rx_cb(uint8_t idx) {
   uint8_t buf[64 + 1]; // +1 for extra null character
diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c
index b60be015b..691ff3e29 100644
--- a/examples/host/cdc_msc_hid_freertos/src/main.c
+++ b/examples/host/cdc_msc_hid_freertos/src/main.c
@@ -40,7 +40,6 @@
   #include "freertos/timers.h"
 
   #define USBH_STACK_SIZE     4096
-  #define CDC_STACK_SZIE      2048
 #else
   #include "FreeRTOS.h"
   #include "semphr.h"
@@ -50,7 +49,6 @@
 
   // Increase stack size when debug log is enabled
   #define USBH_STACK_SIZE    (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
-  #define CDC_STACK_SZIE     (3*configMINIMAL_STACK_SIZE/2)
 #endif
 
 
@@ -74,38 +72,30 @@ StaticTimer_t blinky_tmdef;
 
 StackType_t  usb_host_stack[USBH_STACK_SIZE];
 StaticTask_t usb_host_taskdef;
-
-StackType_t  cdc_stack[CDC_STACK_SZIE];
-StaticTask_t cdc_taskdef;
 #endif
 
 TimerHandle_t blinky_tm;
 
 static void led_blinky_cb(TimerHandle_t xTimer);
+static void usb_host_task(void* param);
+
 extern void cdc_app_init(void);
 extern void hid_app_init(void);
 extern void msc_app_init(void);
 
-static void usb_host_task(void* param);
-extern void cdc_app_task(void* param);
-
-
-
 /*------------- MAIN -------------*/
 int main(void) {
   board_init();
 
   printf("TinyUSB Host CDC MSC HID with FreeRTOS Example\r\n");
 
-  // Create soft timer for blinky, task for tinyusb stack and CDC
+  // Create soft timer for blinky, task for tinyusb stack
 #if configSUPPORT_STATIC_ALLOCATION
   blinky_tm = xTimerCreateStatic(NULL, pdMS_TO_TICKS(BLINK_MOUNTED), true, NULL, led_blinky_cb, &blinky_tmdef);
   xTaskCreateStatic(usb_host_task, "usbh", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_host_stack, &usb_host_taskdef);
-  xTaskCreateStatic(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, cdc_stack, &cdc_taskdef);
 #else
   blinky_tm = xTimerCreate(NULL, pdMS_TO_TICKS(BLINK_NOT_MOUNTED), true, NULL, led_blinky_cb);
   xTaskCreate(usb_host_task, "usbd", USBH_STACK_SIZE, NULL, configMAX_PRIORITIES-1, NULL);
-  xTaskCreate(cdc_app_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES-2, NULL);
 #endif
 
   xTimerStart(blinky_tm, 0);
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index 4d2cab9e8..e45765fd1 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -41,6 +41,8 @@
   #include "driver/periph_ctrl.h"
 #endif
 
+#define UART_ID  UART_NUM_0
+
 #ifdef NEOPIXEL_PIN
 #include "led_strip.h"
 static led_strip_t *strip;
@@ -59,6 +61,17 @@ static void configure_pins(usb_hal_context_t *usb);
 
 // Initialize on-board peripherals : led, button, uart and USB
 void board_init(void) {
+  // uart init
+  uart_config_t uart_config = {
+      .baud_rate = 115200,
+      .data_bits = UART_DATA_8_BITS,
+      .parity = UART_PARITY_DISABLE,
+      .stop_bits = UART_STOP_BITS_1,
+      .flow_ctrl = UART_HW_FLOWCTRL_DISABLE
+  };
+  uart_driver_install(UART_ID, 1024, 0, 0, NULL, 0);
+  uart_param_config(UART_ID, &uart_config);
+
 #ifdef NEOPIXEL_PIN
   #ifdef NEOPIXEL_POWER_PIN
   gpio_reset_pin(NEOPIXEL_POWER_PIN);
@@ -144,7 +157,7 @@ uint32_t board_button_read(void) {
 
 // Get characters from UART
 int board_uart_read(uint8_t *buf, int len) {
-  return uart_read_bytes(UART_NUM_0, buf, len, 0);
+  return uart_read_bytes(UART_ID, buf, len, 0);
 }
 
 // Send characters to UART
@@ -155,9 +168,8 @@ int board_uart_write(void const *buf, int len) {
 }
 
 int board_getchar(void) {
-//  char c;
-//  return (uart_read_bytes(UART_NUM_0, &c, 1, 0) > 0) ? (int) c : (-1);
-  return -1;
+  char c;
+  return (uart_read_bytes(UART_ID, &c, 1, 0) > 0) ? (int) c : (-1);
 }
 
 //--------------------------------------------------------------------+

From 6b8933cfe838b369c58d4fc9ced8aa5c9382a6d6 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Sep 2023 12:55:59 +0700
Subject: [PATCH 2067/2085] fix build with new freertos host example

---
 examples/device/cdc_msc_freertos/Makefile     |   2 -
 examples/host/bare_api/Makefile               |  10 -
 examples/host/cdc_msc_hid/Makefile            |  10 -
 examples/host/cdc_msc_hid_freertos/Makefile   |  18 +-
 .../src/FreeRTOSConfig/FreeRTOSConfig.h       | 215 ++++++++++++++++++
 examples/host/hid_controller/Makefile         |  10 -
 examples/host/msc_file_explorer/Makefile      |  10 -
 hw/bsp/lpc17/family.mk                        |   4 +-
 src/portable/analog/max3421/hcd_max3421.c     |   4 +-
 src/tinyusb.mk                                |   7 +
 10 files changed, 237 insertions(+), 53 deletions(-)
 create mode 100644 examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h

diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile
index 3ac62a79c..84c833fb5 100644
--- a/examples/device/cdc_msc_freertos/Makefile
+++ b/examples/device/cdc_msc_freertos/Makefile
@@ -1,5 +1,3 @@
-DEPS_SUBMODULES += lib/FreeRTOS-Kernel
-
 include ../../make.mk
 
 FREERTOS_SRC = lib/FreeRTOS-Kernel
diff --git a/examples/host/bare_api/Makefile b/examples/host/bare_api/Makefile
index 058307c40..161f8c774 100644
--- a/examples/host/bare_api/Makefile
+++ b/examples/host/bare_api/Makefile
@@ -10,14 +10,4 @@ EXAMPLE_SOURCE += \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
 include ../../rules.mk
diff --git a/examples/host/cdc_msc_hid/Makefile b/examples/host/cdc_msc_hid/Makefile
index 7c16b39d3..15b8a5b31 100644
--- a/examples/host/cdc_msc_hid/Makefile
+++ b/examples/host/cdc_msc_hid/Makefile
@@ -13,14 +13,4 @@ EXAMPLE_SOURCE = \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
 include ../../rules.mk
diff --git a/examples/host/cdc_msc_hid_freertos/Makefile b/examples/host/cdc_msc_hid_freertos/Makefile
index 67bb6da55..a9670b4f2 100644
--- a/examples/host/cdc_msc_hid_freertos/Makefile
+++ b/examples/host/cdc_msc_hid_freertos/Makefile
@@ -5,6 +5,7 @@ FREERTOS_PORTABLE_PATH= $(FREERTOS_SRC)/portable/$(if $(USE_IAR),IAR,GCC)
 
 INC += \
 	src \
+	src/FreeRTOSConfig \
 	$(TOP)/hw \
 	$(TOP)/$(FREERTOS_SRC)/include \
 	$(TOP)/$(FREERTOS_PORTABLE_SRC) \
@@ -19,14 +20,15 @@ EXAMPLE_SOURCE = \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
+# FreeRTOS source, all files in port folder
 SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
+	$(FREERTOS_SRC)/list.c \
+	$(FREERTOS_SRC)/queue.c \
+	$(FREERTOS_SRC)/tasks.c \
+	$(FREERTOS_SRC)/timers.c \
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c))
+
+SRC_S += \
+	$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
 
 include ../../rules.mk
diff --git a/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
new file mode 100644
index 000000000..a1fc8bb09
--- /dev/null
+++ b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h
@@ -0,0 +1,215 @@
+/*
+ * FreeRTOS Kernel V10.0.0
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+// skip if included from IAR assembler
+#ifndef __IASMARM__
+
+// Include MCU header
+#include "bsp/board_mcu.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+  #error "ESP32-Sx should use IDF's FreeRTOSConfig.h"
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+
+// TODO fix later
+// FIXME cause redundant-decls warnings
+#if CFG_TUSB_MCU == OPT_MCU_MM32F327X
+  extern u32 SystemCoreClock;
+#else
+  extern uint32_t SystemCoreClock;
+#endif
+
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#endif
+
+/* Cortex M23/M33 port configuration. */
+#define configENABLE_MPU								        0
+#define configENABLE_FPU								        1
+#define configENABLE_TRUSTZONE					        0
+#define configMINIMAL_SECURE_STACK_SIZE					( 1024 )
+
+#define configUSE_PREEMPTION                    1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#define configCPU_CLOCK_HZ                      SystemCoreClock
+#define configTICK_RATE_HZ                      ( 1000 )
+#define configMAX_PRIORITIES                    ( 5 )
+#define configMINIMAL_STACK_SIZE                ( 128 )
+#define configTOTAL_HEAP_SIZE                   ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
+#define configMAX_TASK_NAME_LEN                 16
+#define configUSE_16_BIT_TICKS                  0
+#define configIDLE_SHOULD_YIELD                 1
+#define configUSE_MUTEXES                       1
+#define configUSE_RECURSIVE_MUTEXES             1
+#define configUSE_COUNTING_SEMAPHORES           1
+#define configQUEUE_REGISTRY_SIZE               4
+#define configUSE_QUEUE_SETS                    0
+#define configUSE_TIME_SLICING                  0
+#define configUSE_NEWLIB_REENTRANT              0
+#define configENABLE_BACKWARD_COMPATIBILITY     1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP   0
+
+#define configSUPPORT_STATIC_ALLOCATION         1
+#define configSUPPORT_DYNAMIC_ALLOCATION        0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK                    0
+#define configUSE_TICK_HOOK                    0
+#define configUSE_MALLOC_FAILED_HOOK           0 // cause nested extern warning
+#define configCHECK_FOR_STACK_OVERFLOW         2
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS          0
+#define configUSE_TRACE_FACILITY               1 // legacy trace
+#define configUSE_STATS_FORMATTING_FUNCTIONS   0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES                  0
+#define configMAX_CO_ROUTINE_PRIORITIES        2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS                       1
+#define configTIMER_TASK_PRIORITY              (configMAX_PRIORITIES-2)
+#define configTIMER_QUEUE_LENGTH               32
+#define configTIMER_TASK_STACK_DEPTH           configMINIMAL_STACK_SIZE
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet               0
+#define INCLUDE_uxTaskPriorityGet              0
+#define INCLUDE_vTaskDelete                    0
+#define INCLUDE_vTaskSuspend                   1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
+#define INCLUDE_xResumeFromISR                 0
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         0
+#define INCLUDE_xTaskGetCurrentTaskHandle      0
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#define INCLUDE_pcTaskGetTaskName              0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xEventGroupSetBitFromISR       0
+#define INCLUDE_xTimerPendFunctionCall         0
+
+/* Define to trap errors during development. */
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+  #define configASSERT(_exp) \
+    do {\
+      if ( !(_exp) ) { \
+        volatile uint32_t* ARM_CM_DHCSR =  ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+        if ( (*ARM_CM_DHCSR) & 1UL ) {  /* Only halt mcu if debugger is attached */ \
+          taskDISABLE_INTERRUPTS(); \
+           __asm("BKPT #0\n"); \
+        }\
+      }\
+    } while(0)
+#else
+  #define configASSERT( x )
+#endif
+
+#ifdef __RX__
+/* Renesas RX series */
+#define vSoftwareInterruptISR					        INT_Excep_ICU_SWINT
+#define vTickISR								              INT_Excep_CMT0_CMI0
+#define configPERIPHERAL_CLOCK_HZ				      (configCPU_CLOCK_HZ/2)
+#define configKERNEL_INTERRUPT_PRIORITY			  1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY	4
+
+#else
+
+/* FreeRTOS hooks to NVIC vectors */
+#define xPortPendSVHandler    PendSV_Handler
+#define xPortSysTickHandler   SysTick_Handler
+#define vPortSVCHandler       SVC_Handler
+
+//--------------------------------------------------------------------+
+// Interrupt nesting behavior configuration.
+//--------------------------------------------------------------------+
+#if defined(__NVIC_PRIO_BITS)
+  // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h
+	#define configPRIO_BITS       __NVIC_PRIO_BITS
+
+#elif defined(__ECLIC_INTCTLBITS)
+  // RISC-V Bumblebee core from nuclei
+  #define configPRIO_BITS       __ECLIC_INTCTLBITS
+
+#elif defined(__IASMARM__)
+  // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS.
+  // Therefore we will hard coded it to minimum value of 2 to get pass ci build.
+  // IAR user must update this to correct value of the target MCU
+  #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU"
+  #define configPRIO_BITS       2
+
+#else
+  #error "FreeRTOS configPRIO_BITS to be defined"
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			  ((1<<configPRIO_BITS) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY 		          ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	        ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+#endif
+
+#endif /* __FREERTOS_CONFIG__H */
diff --git a/examples/host/hid_controller/Makefile b/examples/host/hid_controller/Makefile
index cda2977bc..e7f603f25 100644
--- a/examples/host/hid_controller/Makefile
+++ b/examples/host/hid_controller/Makefile
@@ -11,14 +11,4 @@ EXAMPLE_SOURCE += \
 
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
 include ../../rules.mk
diff --git a/examples/host/msc_file_explorer/Makefile b/examples/host/msc_file_explorer/Makefile
index 1fda72b18..8319d3c2b 100644
--- a/examples/host/msc_file_explorer/Makefile
+++ b/examples/host/msc_file_explorer/Makefile
@@ -24,14 +24,4 @@ SRC_C += \
 # suppress warning caused by fatfs
 CFLAGS += -Wno-error=cast-qual
 
-# TinyUSB Host Stack source
-SRC_C += \
-	src/class/cdc/cdc_host.c \
-	src/class/hid/hid_host.c \
-	src/class/msc/msc_host.c \
-	src/host/hub.c \
-	src/host/usbh.c \
-	src/portable/ohci/ohci.c \
-	src/portable/nxp/lpc17_40/hcd_lpc17_40.c
-
 include ../../rules.mk
diff --git a/hw/bsp/lpc17/family.mk b/hw/bsp/lpc17/family.mk
index abf6abe13..44b406d90 100644
--- a/hw/bsp/lpc17/family.mk
+++ b/hw/bsp/lpc17/family.mk
@@ -22,6 +22,8 @@ MCU_DIR = hw/mcu/nxp/lpcopen/lpc175x_6x/lpc_chip_175x_6x
 
 SRC_C += \
 	src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
+	src/portable/ohci/ohci.c \
+	src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
 	$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
 	$(MCU_DIR)/src/chip_17xx_40xx.c \
 	$(MCU_DIR)/src/clock_17xx_40xx.c \
@@ -29,7 +31,7 @@ SRC_C += \
 	$(MCU_DIR)/src/iocon_17xx_40xx.c \
 	$(MCU_DIR)/src/sysctl_17xx_40xx.c \
 	$(MCU_DIR)/src/sysinit_17xx_40xx.c \
-	$(MCU_DIR)/src/uart_17xx_40xx.c
+	$(MCU_DIR)/src/uart_17xx_40xx.c \
 
 INC += \
 	$(TOP)/$(MCU_DIR)/inc
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 6613956de..77912a4c9 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -428,8 +428,8 @@ bool hcd_init(uint8_t rhport) {
   reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
 
   // V1 is 0x01, V2 is 0x12, V3 is 0x13
-  uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
-  TU_LOG2_HEX(revision);
+//  uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
+//  TU_LOG2_HEX(revision);
 
   // reset
   reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
diff --git a/src/tinyusb.mk b/src/tinyusb.mk
index 85052f90f..89ea0212c 100644
--- a/src/tinyusb.mk
+++ b/src/tinyusb.mk
@@ -17,3 +17,10 @@ TINYUSB_SRC_C += \
 	src/class/usbtmc/usbtmc_device.c \
 	src/class/video/video_device.c \
 	src/class/vendor/vendor_device.c \
+  src/host/usbh.c \
+  src/host/hub.c \
+  src/class/cdc/cdc_host.c \
+  src/class/hid/hid_host.c \
+  src/class/msc/msc_host.c \
+  src/class/vendor/vendor_host.c \
+  src/typec/usbc.c \

From 8348631bf538e2aa0a433ed6e7df9e42bb39bdd5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 28 Sep 2023 16:15:31 +0700
Subject: [PATCH 2068/2085] improve esp32 ci, build esp32 with
 -DDMAX3421_HOST=1 for max3421 testing revert change in hcd.h

---
 .github/workflows/build_esp.yml               | 21 +------
 .../boards/espressif_s3_devkitm/board.h       |  8 +++
 src/host/hcd.h                                |  3 -
 tools/build_esp32.py                          | 61 +++++++++++--------
 4 files changed, 44 insertions(+), 49 deletions(-)

diff --git a/.github/workflows/build_esp.yml b/.github/workflows/build_esp.yml
index 29585cb36..897616f09 100644
--- a/.github/workflows/build_esp.yml
+++ b/.github/workflows/build_esp.yml
@@ -29,12 +29,10 @@ jobs:
       fail-fast: false
       matrix:
         board:
-        # Alphabetical order
         # ESP32-S2
-        - 'espressif_saola_1'
+        - 'espressif_kaluga_1'
         # ESP32-S3
-        #- 'espressif_s3_devkitm'
-        # S3 compile error with "dangerous relocation: call8: call target out of range: memcpy"
+        - 'espressif_s3_devkitm'
 
     steps:
     - name: Setup Python
@@ -48,20 +46,5 @@ jobs:
     - name: Checkout TinyUSB
       uses: actions/checkout@v3
 
-    - name: Checkout hathach/linkermap
-      uses: actions/checkout@v3
-      with:
-         repository: hathach/linkermap
-         path: linkermap
-
     - name: Build
       run: docker run --rm -v $PWD:/project -w /project espressif/idf:latest python3 tools/build_esp32.py ${{ matrix.board }}
-
-    - name: Linker Map
-      run: |
-        pip install linkermap/
-        # find -quit to only print linkermap of 1 board per example
-        for ex in `ls -d examples/device/*/`
-        do
-          find ${ex} -maxdepth 3 -name *.map -print -quit | xargs -I % sh -c 'echo "::group::%"; linkermap -v %; echo "::endgroup::"'
-        done
diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
index fe33b5c43..4b4151e72 100644
--- a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
+++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h
@@ -36,6 +36,14 @@
 #define BUTTON_PIN            0
 #define BUTTON_STATE_ACTIVE   0
 
+// SPI for USB host shield
+#define MAX3421_SPI_HOST  SPI2_HOST
+#define MAX3421_SCK_PIN  36
+#define MAX3421_MOSI_PIN 35
+#define MAX3421_MISO_PIN 37
+#define MAX3421_CS_PIN   15
+#define MAX3421_INTR_PIN 14
+
 #ifdef __cplusplus
  }
 #endif
diff --git a/src/host/hcd.h b/src/host/hcd.h
index edffb34cb..2bde289df 100644
--- a/src/host/hcd.h
+++ b/src/host/hcd.h
@@ -133,9 +133,6 @@ bool hcd_init(uint8_t rhport);
 // Interrupt Handler
 void hcd_int_handler(uint8_t rhport, bool in_isr);
 
-// Interrupt Hanndler (extended version)
-void hcd_int_handler_ext(uint8_t rhport, bool in_isr);
-
 // Enable USB interrupt
 void hcd_int_enable (uint8_t rhport);
 
diff --git a/tools/build_esp32.py b/tools/build_esp32.py
index 00783bf58..1f73d3b22 100644
--- a/tools/build_esp32.py
+++ b/tools/build_esp32.py
@@ -17,8 +17,8 @@ exit_status = 0
 
 total_time = time.monotonic()
 
-build_format = '| {:23} | {:30} | {:18} | {:7} | {:6} | {:6} |'
-build_separator = '-' * 100
+build_format = '| {:30} | {:30} | {:18} | {:7} | {:6} | {:6} |'
+build_separator = '-' * 107
 
 def filter_with_input(mylist):
     if len(sys.argv) > 1:
@@ -26,12 +26,9 @@ def filter_with_input(mylist):
         if len(input_args) > 0:
             mylist[:] = input_args
 
+
 # Build all examples if not specified
-all_examples = []
-for entry in os.scandir("examples/device"):
-    # Only includes example with CMakeLists.txt for esp32s, and skip board_test to speed up ci
-    if entry.is_dir() and os.path.exists(entry.path + "/sdkconfig.defaults") and entry.name != 'board_test':
-        all_examples.append(entry.name)
+all_examples = [entry.replace('examples/', '') for entry in glob.glob("examples/*/*_freertos")]
 filter_with_input(all_examples)
 all_examples.sort()
 
@@ -46,32 +43,41 @@ all_boards.sort()
 def build_board(example, board):
     global success_count, fail_count, skip_count, exit_status
     start_time = time.monotonic()
+
+    # Check if board is skipped
+    build_dir = f"cmake-build/cmake-build-{board}/{example}"
+
+    # Generate and build
+    r = subprocess.run(f"cmake examples/{example} -B {build_dir} -G \"Ninja\" -DBOARD={board} -DMAX3421_HOST=1",
+                       shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+    if r.returncode == 0:
+        r = subprocess.run(f"cmake --build {build_dir}", shell=True, stdout=subprocess.PIPE,
+                           stderr=subprocess.STDOUT)
+    build_duration = time.monotonic() - start_time
     flash_size = "-"
     sram_size = "-"
 
-    # Check if board is skipped
-    if build_utils.skip_example(example, board):
-        success = SKIPPED
-        skip_count += 1
-        print(build_format.format(example, board, success, '-', flash_size, sram_size))
+    if r.returncode == 0:
+        success = SUCCEEDED
+        success_count += 1
+        #(flash_size, sram_size) = build_size(example, board)
     else:
-        subprocess.run("make -C examples/device/{} BOARD={} clean".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        build_result = subprocess.run("make -j -C examples/device/{} BOARD={} all".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+        exit_status = r.returncode
+        success = FAILED
+        fail_count += 1
 
-        if build_result.returncode == 0:
-            success = SUCCEEDED
-            success_count += 1
-            (flash_size, sram_size) = build_size(example, board)
-        else:
-            exit_status = build_result.returncode
-            success = FAILED
-            fail_count += 1
+    title = build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size)
+    if os.getenv('CI'):
+        # always print build output if in CI
+        print(f"::group::{title}")
+        print(r.stdout.decode("utf-8"))
+        print(f"::endgroup::")
+    else:
+        # print build output if failed
+        print(title)
+        if r.returncode != 0:
+            print(r.stdout.decode("utf-8"))
 
-        build_duration = time.monotonic() - start_time
-        print(build_format.format(example, board, success, "{:.2f}s".format(build_duration), flash_size, sram_size))
-
-        if build_result.returncode != 0:
-            print(build_result.stdout.decode("utf-8"))
 
 def build_size(example, board):
     #elf_file = 'examples/device/{}/_build/{}/{}-firmware.elf'.format(example, board, board)
@@ -82,6 +88,7 @@ def build_size(example, board):
     sram_size = int(size_list[1]) + int(size_list[2])
     return (flash_size, sram_size)
 
+
 print(build_separator)
 print(build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM'))
 print(build_separator)

From f36e0b7b923f632fbcc65373d77e0e127f03aace Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 3 Oct 2023 16:27:35 +0700
Subject: [PATCH 2069/2085] esp32 comment out uart, increase max3421 spi speed
 to 26mhz

---
 .idea/cmake.xml                  | 18 +++++++++---------
 hw/bsp/espressif/boards/family.c | 14 +++++++++++---
 2 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index c6ebf2a46..9721af5ea 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -9,7 +9,7 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
-      <configuration PROFILE_NAME="kaluga" ENABLED="true" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_kaluga_1 -DMAX3421_HOST=1 -DLOG=2">
+      <configuration PROFILE_NAME="kaluga" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=espressif_kaluga_1 -DMAX3421_HOST=1 -DLOG=2">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
             <env name="ESPBAUD" value="1500000" />
@@ -54,16 +54,16 @@
       <configuration PROFILE_NAME="ra6m5 PORT0" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m5_ek -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1 -DPORT=0" />
       <configuration PROFILE_NAME="uno_r4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=uno_r4 -DLOG=4 -DLOGGER=RTT" />
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
-      <configuration PROFILE_NAME="metro_m4_express" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
-      <configuration PROFILE_NAME="stm32u5" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575eval" />
+      <configuration PROFILE_NAME="stm32u5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575eval" />
       <configuration PROFILE_NAME="metro esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_metro_esp32s2 -DMAX3421_HOST=1 -DLOG=2">
-            <ADDITIONAL_GENERATION_ENVIRONMENT>
-                <envs>
-                    <env name="ESPBAUD" value="1500000" />
-                </envs>
-            </ADDITIONAL_GENERATION_ENVIRONMENT>
-        </configuration>
+        <ADDITIONAL_GENERATION_ENVIRONMENT>
+          <envs>
+            <env name="ESPBAUD" value="1500000" />
+          </envs>
+        </ADDITIONAL_GENERATION_ENVIRONMENT>
+      </configuration>
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index e45765fd1..c6a592627 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -41,6 +41,8 @@
   #include "driver/periph_ctrl.h"
 #endif
 
+// Note; current code use UART0 can cause device to reset while monitoring
+#define USE_UART  0
 #define UART_ID  UART_NUM_0
 
 #ifdef NEOPIXEL_PIN
@@ -61,6 +63,7 @@ static void configure_pins(usb_hal_context_t *usb);
 
 // Initialize on-board peripherals : led, button, uart and USB
 void board_init(void) {
+#if USE_UART
   // uart init
   uart_config_t uart_config = {
       .baud_rate = 115200,
@@ -71,6 +74,7 @@ void board_init(void) {
   };
   uart_driver_install(UART_ID, 1024, 0, 0, NULL, 0);
   uart_param_config(UART_ID, &uart_config);
+#endif
 
 #ifdef NEOPIXEL_PIN
   #ifdef NEOPIXEL_POWER_PIN
@@ -157,7 +161,11 @@ uint32_t board_button_read(void) {
 
 // Get characters from UART
 int board_uart_read(uint8_t *buf, int len) {
+#if USE_UART
   return uart_read_bytes(UART_ID, buf, len, 0);
+#else
+  return -1;
+#endif
 }
 
 // Send characters to UART
@@ -168,8 +176,8 @@ int board_uart_write(void const *buf, int len) {
 }
 
 int board_getchar(void) {
-  char c;
-  return (uart_read_bytes(UART_ID, &c, 1, 0) > 0) ? (int) c : (-1);
+  uint8_t c = 0;
+  return board_uart_read(&c, 1) > 0 ? (int) c : (-1);
 }
 
 //--------------------------------------------------------------------+
@@ -224,7 +232,7 @@ static void max3421_init(void) {
 
   spi_device_interface_config_t max3421_cfg = {
       .mode = 0,
-      .clock_speed_hz = 4000000, // 26000000
+      .clock_speed_hz = 26000000,
       .spics_io_num = -1, // manual control CS
       .queue_size = 1
   };

From 67e34267a68c81f62ff315ac990f07a60f4dc93c Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 4 Oct 2023 18:00:32 +0700
Subject: [PATCH 2070/2085] change tuh_max3421_spi_xfer_api() signature

tested working with sam d21 and d51, not tested with nrf52, seem not
working with esp32
---
 hw/bsp/espressif/boards/family.c          | 39 ++++++++++++++---------
 hw/bsp/nrf/family.c                       | 20 ++++++++----
 hw/bsp/samd21/family.c                    | 27 +++++++++-------
 hw/bsp/samd51/family.c                    | 35 +++++++++++---------
 src/portable/analog/max3421/hcd_max3421.c | 27 +++++++++-------
 5 files changed, 88 insertions(+), 60 deletions(-)

diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c
index c6a592627..912ca5f35 100644
--- a/hw/bsp/espressif/boards/family.c
+++ b/hw/bsp/espressif/boards/family.c
@@ -38,7 +38,9 @@
 #if ESP_IDF_VERSION_MAJOR > 4
   #include "esp_private/periph_ctrl.h"
 #else
+
   #include "driver/periph_ctrl.h"
+
 #endif
 
 // Note; current code use UART0 can cause device to reset while monitoring
@@ -46,16 +48,21 @@
 #define UART_ID  UART_NUM_0
 
 #ifdef NEOPIXEL_PIN
+
 #include "led_strip.h"
-static led_strip_t *strip;
+
+static led_strip_t* strip;
 #endif
 
 #if CFG_TUH_ENABLED && CFG_TUH_MAX3421
+
 #include "driver/spi_master.h"
+
 static void max3421_init(void);
+
 #endif
 
-static void configure_pins(usb_hal_context_t *usb);
+static void configure_pins(usb_hal_context_t* usb);
 
 //--------------------------------------------------------------------+
 // Implementation
@@ -115,11 +122,11 @@ void board_init(void) {
 #endif
 }
 
-static void configure_pins(usb_hal_context_t *usb) {
+static void configure_pins(usb_hal_context_t* usb) {
   /* usb_periph_iopins currently configures USB_OTG as USB Device.
    * Introduce additional parameters in usb_hal_context_t when adding support
    * for USB Host. */
-  for (const usb_iopin_dsc_t *iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
+  for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) {
     if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) {
       esp_rom_gpio_pad_select_gpio(iopin->pin);
       if (iopin->is_output) {
@@ -160,7 +167,7 @@ uint32_t board_button_read(void) {
 }
 
 // Get characters from UART
-int board_uart_read(uint8_t *buf, int len) {
+int board_uart_read(uint8_t* buf, int len) {
 #if USE_UART
   return uart_read_bytes(UART_ID, buf, len, 0);
 #else
@@ -169,7 +176,7 @@ int board_uart_read(uint8_t *buf, int len) {
 }
 
 // Send characters to UART
-int board_uart_write(void const *buf, int len) {
+int board_uart_write(void const* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
@@ -216,7 +223,7 @@ static void max3421_init(void) {
   gpio_set_level(MAX3421_CS_PIN, 1);
 
   // SPI
-  spi_bus_config_t buscfg={
+  spi_bus_config_t buscfg = {
       .miso_io_num = MAX3421_MISO_PIN,
       .mosi_io_num = MAX3421_MOSI_PIN,
       .sclk_io_num = MAX3421_SCK_PIN,
@@ -228,7 +235,7 @@ static void max3421_init(void) {
       .data7_io_num = -1,
       .max_transfer_sz = 1024
   };
-  ESP_ERROR_CHECK( spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO) );
+  ESP_ERROR_CHECK(spi_bus_initialize(MAX3421_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
 
   spi_device_interface_config_t max3421_cfg = {
       .mode = 0,
@@ -236,7 +243,7 @@ static void max3421_init(void) {
       .spics_io_num = -1, // manual control CS
       .queue_size = 1
   };
-  ESP_ERROR_CHECK( spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi) );
+  ESP_ERROR_CHECK(spi_bus_add_device(MAX3421_SPI_HOST, &max3421_cfg, &max3421_spi));
 
   // debug
   gpio_set_direction(13, GPIO_MODE_OUTPUT);
@@ -244,7 +251,7 @@ static void max3421_init(void) {
 
   // Interrupt pin
   max3421_intr_sem = xSemaphoreCreateBinary();
-  xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES-2, NULL);
+  xTaskCreate(max3421_intr_task, "max3421 intr", 2048, NULL, configMAX_PRIORITIES - 2, NULL);
 
   gpio_set_direction(MAX3421_INTR_PIN, GPIO_MODE_INPUT);
   gpio_set_intr_type(MAX3421_INTR_PIN, GPIO_INTR_NEGEDGE);
@@ -267,18 +274,20 @@ void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   gpio_set_level(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
   (void) rhport;
 
-  if (tx_len == 0) {
+  if (tx_buf == NULL) {
     // fifo read, transmit rx_buf as dummy
     tx_buf = rx_buf;
-    tx_len = rx_len;
   }
 
+  // length in bits
+  size_t const len_bits = xfer_bytes << 3;
+
   spi_transaction_t xact = {
-      .length = tx_len << 3, // length in bits
-      .rxlength = rx_len << 3, // length in bits
+      .length = len_bits,
+      .rxlength = rx_buf ? len_bits : 0,
       .tx_buffer = tx_buf,
       .rx_buffer = rx_buf
   };
diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c
index 631f53fcd..c431389f3 100644
--- a/hw/bsp/nrf/family.c
+++ b/hw/bsp/nrf/family.c
@@ -95,7 +95,9 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
 
 //------------- Host using MAX2341E -------------//
 #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
+
 static void max3421_init(void);
+
 static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
 #endif
 
@@ -203,15 +205,15 @@ uint32_t board_button_read(void) {
   return BUTTON_STATE_ACTIVE == nrf_gpio_pin_read(BUTTON_PIN);
 }
 
-int board_uart_read(uint8_t *buf, int len) {
+int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
 //  return NRFX_SUCCESS == nrfx_uart_rx(&_uart_id, buf, (size_t) len) ? len : 0;
 }
 
-int board_uart_write(void const *buf, int len) {
-  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const *) buf, (size_t) len)) ? len : 0;
+int board_uart_write(void const* buf, int len) {
+  return (NRFX_SUCCESS == nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len)) ? len : 0;
 }
 
 #if CFG_TUSB_OS == OPT_OS_NONE
@@ -323,6 +325,7 @@ static void max3421_init(void) {
   nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
 }
 
+// API to enable/disable MAX3421 INTR pin interrupt
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
@@ -335,22 +338,25 @@ void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   }
 }
 
+// API to control MAX3421 SPI CS
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
   nrf_gpio_pin_write(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
   (void) rhport;
 
   nrfx_spim_xfer_desc_t xfer = {
       .p_tx_buffer = tx_buf,
-      .tx_length   = tx_len,
+      .tx_length   = tx_buf ? xfer_bytes : 0,
       .p_rx_buffer = rx_buf,
-      .rx_length   = rx_len,
+      .rx_length   = rx_buf ? xfer_bytes : 0,
   };
 
-  return (nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS);
+  return nrfx_spim_xfer(&_spi, &xfer, 0) == NRFX_SUCCESS;
 }
 
 #endif
diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c
index b9365fc3f..ccb2c99b1 100644
--- a/hw/bsp/samd21/family.c
+++ b/hw/bsp/samd21/family.c
@@ -72,6 +72,7 @@ static void uart_init(void);
 #define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID)
 
 static void max3421_init(void);
+
 #endif
 
 void board_init(void) {
@@ -237,13 +238,13 @@ int board_uart_write(void const * buf, int len)
 static void uart_init(void) {
 }
 
-int board_uart_read(uint8_t *buf, int len) {
+int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
 }
 
-int board_uart_write(void const *buf, int len) {
+int board_uart_write(void const* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
@@ -261,6 +262,7 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
 //--------------------------------------------------------------------+
@@ -278,8 +280,8 @@ static void max3421_init(void) {
 
   // Configure GCLK for SERCOM
 //  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_SERCOM4_CORE | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
-  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val+MAX3421_SERCOM_ID) |
-      GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
+  GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCLK_CLKCTRL_ID_SERCOM0_CORE_Val + MAX3421_SERCOM_ID) |
+                      GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_CLKEN;
   while (GCLK->STATUS.bit.SYNCBUSY);
 
   Sercom* sercom = MAX3421_SERCOM;
@@ -293,7 +295,7 @@ static void max3421_init(void) {
 
   // Set up SPI in master mode, MSB first, SPI mode 0
   sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
-      SERCOM_SPI_CTRLA_MODE(3);
+                          SERCOM_SPI_CTRLA_MODE(3);
 
   sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
   while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
@@ -366,6 +368,7 @@ void EIC_Handler(void) {
   tuh_int_handler(1, true);
 }
 
+// API to enable/disable MAX3421 INTR pin interrupt
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
@@ -376,24 +379,26 @@ void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   }
 }
 
+// API to control MAX3421 SPI CS
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
   gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
   (void) rhport;
 
   Sercom* sercom = MAX3421_SERCOM;
 
-  size_t count = 0;
-  while (count < tx_len || count < rx_len) {
+  for (size_t count = 0; count < xfer_bytes; count++) {
     // Wait for the transmit buffer to be empty
     while (!sercom->SPI.INTFLAG.bit.DRE);
 
     // Write data to be transmitted
     uint8_t data = 0x00;
-    if (count < tx_len) {
+    if (tx_buf) {
       data = tx_buf[count];
     }
 
@@ -404,11 +409,9 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
 
     // Read received data
     data = (uint8_t) sercom->SPI.DATA.reg;
-    if (count < rx_len) {
+    if (rx_buf) {
       rx_buf[count] = data;
     }
-
-    count++;
   }
 
   // wait for bus idle and clear flags
diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c
index 4d43c7745..bca18e1a2 100644
--- a/hw/bsp/samd51/family.c
+++ b/hw/bsp/samd51/family.c
@@ -81,6 +81,7 @@ void USB_3_Handler(void) {
 #define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler)
 
 static void max3421_init(void);
+
 #endif
 
 void board_init(void) {
@@ -153,13 +154,13 @@ uint32_t board_button_read(void) {
   return gpio_get_pin_level(BUTTON_PIN) ? 0 : 1;
 }
 
-int board_uart_read(uint8_t *buf, int len) {
+int board_uart_read(uint8_t* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
 }
 
-int board_uart_write(void const *buf, int len) {
+int board_uart_write(void const* buf, int len) {
   (void) buf;
   (void) len;
   return 0;
@@ -175,6 +176,7 @@ void SysTick_Handler(void) {
 uint32_t board_millis(void) {
   return system_ticks;
 }
+
 #endif
 
 //--------------------------------------------------------------------+
@@ -189,7 +191,7 @@ static void max3421_init(void) {
   uint32_t const baudrate = 12000000u;
 
   struct {
-    volatile uint32_t *mck_apb;
+    volatile uint32_t* mck_apb;
     uint32_t mask;
     uint8_t gclk_id_core;
     uint8_t gclk_id_slow;
@@ -214,8 +216,10 @@ static void max3421_init(void) {
   *sercom_clock[MAX3421_SERCOM_ID].mck_apb |= sercom_clock[MAX3421_SERCOM_ID].mask;
 
   // Configure GCLK for SERCOM
-  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_core].reg = GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
-  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_slow].reg = GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_core].reg =
+      GCLK_PCHCTRL_GEN_GCLK0_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
+  GCLK->PCHCTRL[sercom_clock[MAX3421_SERCOM_ID].gclk_id_slow].reg =
+      GCLK_PCHCTRL_GEN_GCLK3_Val | (1 << GCLK_PCHCTRL_CHEN_Pos);
 
   // Disable the SPI module
   sercom->SPI.CTRLA.bit.ENABLE = 0;
@@ -226,7 +230,7 @@ static void max3421_init(void) {
 
   // Set up SPI in master mode, MSB first, SPI mode 0
   sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_DOPO(MAX3421_TX_PAD) | SERCOM_SPI_CTRLA_DIPO(MAX3421_RX_PAD) |
-      SERCOM_SPI_CTRLA_MODE(3);
+                          SERCOM_SPI_CTRLA_MODE(3);
 
   sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(0) | SERCOM_SPI_CTRLB_RXEN;
   while (sercom->SPI.SYNCBUSY.bit.CTRLB == 1);
@@ -278,9 +282,9 @@ static void max3421_init(void) {
   while (EIC->SYNCBUSY.bit.ENABLE);
 
   // Configure EIC to trigger on falling edge
-  volatile uint32_t * eic_config;
+  volatile uint32_t* eic_config;
   uint8_t sense_shift;
-  if ( MAX3421_INTR_EIC_ID < 8 ) {
+  if (MAX3421_INTR_EIC_ID < 8) {
     eic_config = &EIC->CONFIG[0].reg;
     sense_shift = MAX3421_INTR_EIC_ID * 4;
   } else {
@@ -312,6 +316,7 @@ void MAX3421_EIC_Handler(void) {
   tuh_int_handler(1, true);
 }
 
+// API to enable/disable MAX3421 INTR pin interrupt
 void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   (void) rhport;
 
@@ -323,24 +328,26 @@ void tuh_max3421_int_api(uint8_t rhport, bool enabled) {
   }
 }
 
+// API to control MAX3421 SPI CS
 void tuh_max3421_spi_cs_api(uint8_t rhport, bool active) {
   (void) rhport;
   gpio_set_pin_level(MAX3421_CS_PIN, active ? 0 : 1);
 }
 
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len) {
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes) {
   (void) rhport;
 
   Sercom* sercom = MAX3421_SERCOM;
 
-  size_t count = 0;
-  while (count < tx_len || count < rx_len) {
+  for (size_t count = 0; count < xfer_bytes; count++) {
     // Wait for the transmit buffer to be empty
     while (!sercom->SPI.INTFLAG.bit.DRE);
 
     // Write data to be transmitted
     uint8_t data = 0x00;
-    if (count < tx_len) {
+    if (tx_buf) {
       data = tx_buf[count];
     }
 
@@ -351,11 +358,9 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
 
     // Read received data
     data = (uint8_t) sercom->SPI.DATA.reg;
-    if (count < rx_len) {
+    if (rx_buf) {
       rx_buf[count] = data;
     }
-
-    count++;
   }
 
   // wait for bus idle and clear flags
diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c
index 77912a4c9..787c1e511 100644
--- a/src/portable/analog/max3421/hcd_max3421.c
+++ b/src/portable/analog/max3421/hcd_max3421.c
@@ -210,16 +210,21 @@ static max3421_data_t _hcd_data;
 // API: SPI transfer with MAX3421E, must be implemented by application
 //--------------------------------------------------------------------+
 
-void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
-bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
-void tuh_max3421_int_api(uint8_t rhport, bool enabled);
+// API to control MAX3421 SPI CS
+extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
 
-static void handle_connect_irq(uint8_t rhport, bool in_isr);
-static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
+// API to transfer data with MAX3421 SPI
+// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only
+extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes);
+
+// API to enable/disable MAX3421 INTR pin interrupt
+extern void tuh_max3421_int_api(uint8_t rhport, bool enabled);
 
 //--------------------------------------------------------------------+
 // SPI Helper
 //--------------------------------------------------------------------+
+static void handle_connect_irq(uint8_t rhport, bool in_isr);
+static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
 
 static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
   // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
@@ -249,9 +254,9 @@ static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint
 
   max3421_spi_lock(rhport, in_isr);
 
-  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
+  tuh_max3421_spi_xfer_api(rhport, &reg, &hirq, 1);
   _hcd_data.hirq = hirq;
-  tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0);
+  tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len);
 
   max3421_spi_unlock(rhport, in_isr);
 
@@ -263,9 +268,9 @@ static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_is
 
   max3421_spi_lock(rhport, in_isr);
 
-  tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
+  tuh_max3421_spi_xfer_api(rhport, &reg, &hirq, 1);
   _hcd_data.hirq = hirq;
-  tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
+  tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len);
 
   max3421_spi_unlock(rhport, in_isr);
 }
@@ -276,7 +281,7 @@ static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) {
 
   max3421_spi_lock(rhport, in_isr);
 
-  tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
+  tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2);
 
   max3421_spi_unlock(rhport, in_isr);
 
@@ -290,7 +295,7 @@ static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
 
   max3421_spi_lock(rhport, in_isr);
 
-  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
+  bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2);
 
   max3421_spi_unlock(rhport, in_isr);
 

From cfb683f48178966a7386538c1082e5aa6ebf53f4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Thu, 5 Oct 2023 17:01:41 +0700
Subject: [PATCH 2071/2085] tested with nrf52840 and esp32s2

---
 hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake | 4 ++--
 hw/bsp/nrf/boards/feather_nrf52840_express/board.h     | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
index ce6da8b43..726438d05 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake
@@ -1,6 +1,6 @@
 set(MCU_VARIANT nrf52840)
-#set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
-set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
+set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld)
+#set(LD_FILE_GNU ${NRFX_DIR}/mdk/nrf52840_xxaa.ld)
 
 # enable max3421 host driver for this board
 set(MAX3421_HOST 1)
diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
index 76100a14a..3d59516d8 100644
--- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
+++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h
@@ -49,8 +49,8 @@
 #define MAX3421_SCK_PIN  14
 #define MAX3421_MOSI_PIN 13
 #define MAX3421_MISO_PIN 15
-#define MAX3421_CS_PIN   27
-#define MAX3421_INTR_PIN 26
+#define MAX3421_CS_PIN   27 // D10
+#define MAX3421_INTR_PIN 26 // D9
 
 #ifdef __cplusplus
  }

From 8b2cb63da88c0f790fee8d514971153569993b05 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 10 Oct 2023 18:22:20 +0200
Subject: [PATCH 2072/2085] Fix naming nBytesPerSample.

---
 src/class/audio/audio_device.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 46fd6dfa9..5d3772a9d 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -631,9 +631,9 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t* audio, uint16_t
 // Decoding according to 2.3.1.5 Audio Streams
 
 // Helper function
-static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesToCopy, void * dst, const void * dst_end, void * src, uint8_t const n_ff_used)
+static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesPerSample, void * dst, const void * dst_end, void * src, uint8_t const n_ff_used)
 {
-  // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
+  // Due to one FIFO contains 2 channels, data always aligned to (nBytesPerSample * 2)
   uint16_t * dst16 = dst;
   uint16_t * src16 = src;
   const uint16_t * dst_end16 = dst_end;
@@ -641,7 +641,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB
   uint32_t * src32 = src;
   const uint32_t * dst_end32 = dst_end;
 
-  if (nBytesToCopy == 1)
+  if (nBytesPerSample == 1)
   {
     while(dst16 < dst_end16)
     {
@@ -650,7 +650,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB
     }
     return src16;
   }
-  else if (nBytesToCopy == 2)
+  else if (nBytesPerSample == 2)
   {
     while(dst32 < dst_end32)
     {
@@ -659,7 +659,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB
     }
     return src32;
   }
-  else if (nBytesToCopy == 3)
+  else if (nBytesPerSample == 3)
   {
     while(dst16 < dst_end16)
     {
@@ -670,7 +670,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_decode(uint16_t const nB
     }
     return src16;
   }
-  else // nBytesToCopy == 4
+  else // nBytesPerSample == 4
   {
     while(dst32 < dst_end32)
     {
@@ -926,9 +926,9 @@ range [-1, +1)
  * */
 
 // Helper function
-static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesToCopy, void * src, const void * src_end, void * dst, uint8_t const n_ff_used)
+static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesPerSample, void * src, const void * src_end, void * dst, uint8_t const n_ff_used)
 {
-  // Due to one FIFO contains 2 channels, data always aligned to (nBytesToCopy * 2)
+  // Due to one FIFO contains 2 channels, data always aligned to (nBytesPerSample * 2)
   uint16_t * dst16 = dst;
   uint16_t * src16 = src;
   const uint16_t * src_end16 = src_end;
@@ -936,7 +936,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB
   uint32_t * src32 = src;
   const uint32_t * src_end32 = src_end;
 
-  if (nBytesToCopy == 1)
+  if (nBytesPerSample == 1)
   {
     while(src16 < src_end16)
     {
@@ -945,7 +945,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB
     }
     return dst16;
   }
-  else if (nBytesToCopy == 2)
+  else if (nBytesPerSample == 2)
   {
     while(src32 < src_end32)
     {
@@ -954,7 +954,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB
     }
     return dst32;
   }
-  else if (nBytesToCopy == 3)
+  else if (nBytesPerSample == 3)
   {
     while(src16 < src_end16)
     {
@@ -965,7 +965,7 @@ static inline void * audiod_interleaved_copy_bytes_fast_encode(uint16_t const nB
     }
     return dst16;
   }
-  else // nBytesToCopy == 4
+  else // nBytesPerSample == 4
   {
     while(src32 < src_end32)
     {

From 2ba760a1c16dc096da9f96f20cf2443e3a1d8416 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 10 Oct 2023 18:24:47 +0200
Subject: [PATCH 2073/2085] Enhance audio_4_channel_mic example, plot 4
 different waves for each channel.

---
 .../device/audio_4_channel_mic/src/main.c     | 43 +++++++++++--------
 .../audio_4_channel_mic/src/tusb_config.h     |  3 +-
 2 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 94ac86d84..3b21b4ac6 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -34,17 +34,16 @@
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
+#include "arm_math.h"
 
 #include "bsp/board_api.h"
 #include "tusb.h"
+#include "tusb_config.h"
 
 //--------------------------------------------------------------------+
 // MACRO CONSTANT TYPEDEF PROTYPES
 //--------------------------------------------------------------------+
-
-#ifndef AUDIO_SAMPLE_RATE
-#define AUDIO_SAMPLE_RATE   48000
-#endif
+#define AUDIO_SAMPLE_RATE   CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE
 
 /* Blink pattern
  * - 250 ms  : device not mounted
@@ -70,7 +69,7 @@ uint8_t clkValid;
 audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; 			// Volume range state
 audio_control_range_4_n_t(1) sampleFreqRng; 						// Sample frequency range state
 
-// Audio test data
+// Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2
 uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ/2];   // Ensure half word aligned
 
 void led_blinking_task(void);
@@ -400,7 +399,8 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
   (void) ep_in;
   (void) cur_alt_setting;
 
-  for (uint8_t cnt=0; cnt < CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO; cnt++)
+  // Write buffer[0] (CH0-1) and buffer[1] (CH1-2) into FIFO
+  for (uint8_t cnt=0; cnt < 2; cnt++)
   {
     tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
   }
@@ -416,22 +416,27 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin
   (void) ep_in;
   (void) cur_alt_setting;
 
-  uint16_t dataVal;
-
   // Generate dummy data
-  for (uint16_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO; cnt++)
+  uint16_t * p_buff = i2s_dummy_buffer[0];
+  uint16_t dataVal = 1;
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
   {
-    uint16_t * p_buff = i2s_dummy_buffer[cnt];              // 2 bytes per sample
-    dataVal = 1;
-    for (uint16_t cnt2 = 0; cnt2 < AUDIO_SAMPLE_RATE/1000; cnt2++)
-    {
-      for (uint8_t cnt3 = 0; cnt3 < CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX; cnt3++)
-      {
-        *p_buff++ = dataVal;
-      }
-      dataVal++;
-    }
+    // CH0 saw wave
+    *p_buff++ = dataVal;
+    // CH1 inverted saw wave
+    *p_buff++ = 60 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+    dataVal++;
   }
+  p_buff = i2s_dummy_buffer[1];
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH3 square wave
+    *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 120:170;
+    // CH4 sinus wave
+    q15_t t = 0x7FFF * cnt / (AUDIO_SAMPLE_RATE/1000);
+    *p_buff++ = arm_sin_q15(t) / 1300 + 200;
+  }
+
   return true;
 }
 
diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index 5cf6d07c3..291ac4f79 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -103,6 +103,7 @@ extern "C" {
 //--------------------------------------------------------------------
 
 // Have a look into audio_device.h for all configurations
+#define CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE              48000
 
 #define CFG_TUD_AUDIO_FUNC_1_DESC_LEN                 TUD_AUDIO_MIC_FOUR_CH_DESC_LEN
 
@@ -112,7 +113,7 @@ extern "C" {
 #define CFG_TUD_AUDIO_ENABLE_EP_IN                    1
 #define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX    2         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX            4         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
-#define CFG_TUD_AUDIO_EP_SZ_IN                        (48 + 1) * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX      // 48 Samples (48 kHz) x 2 Bytes/Sample x CFG_TUD_AUDIO_N_CHANNELS_TX Channels - the Windows driver always needs an extra sample per channel of space more, otherwise it complains... found by trial and error
+#define CFG_TUD_AUDIO_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          CFG_TUD_AUDIO_EP_SZ_IN
 

From 20699e30dd7847a7177d91dc76791248a788f3dc Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 10 Oct 2023 18:25:14 +0200
Subject: [PATCH 2074/2085] Enhance plot script.

---
 .../device/audio_4_channel_mic/src/plot_audio_samples.py   | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
index 8312b4e28..a3a2b2fd4 100644
--- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
+++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
@@ -10,7 +10,7 @@ if __name__ == '__main__':
     # print(sd.query_devices())
 
     fs = 48000  		# Sample rate
-    duration = 100e-3   # Duration of recording
+    duration = 20e-3   # Duration of recording
 
     if platform.system() == 'Windows':
         # WDM-KS is needed since there are more than one MicNode device APIs (at least in Windows)
@@ -25,9 +25,14 @@ if __name__ == '__main__':
     sd.wait()  # Wait until recording is finished
     print('Done!')
 
+
     time = np.arange(0, duration, 1 / fs)  # time vector
+    # strip starting zero
+    myrecording = myrecording[100:]
+    time = time[100:]
     plt.plot(time, myrecording)
     plt.xlabel('Time [s]')
     plt.ylabel('Amplitude')
     plt.title('MicNode 4 Channel')
+    plt.legend(['CH-1', 'CH-2', 'CH-3','CH-4'])
     plt.show()

From 504d29cf7ae9f40a56c73a2e666564b9b4ab9efd Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 10 Oct 2023 18:25:42 +0200
Subject: [PATCH 2075/2085] Update make & cmake file.

---
 examples/device/audio_4_channel_mic/CMakeLists.txt |  7 +++++++
 examples/device/audio_4_channel_mic/Makefile       | 11 ++++++++++-
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/examples/device/audio_4_channel_mic/CMakeLists.txt b/examples/device/audio_4_channel_mic/CMakeLists.txt
index f61e1b640..ae6bf0142 100644
--- a/examples/device/audio_4_channel_mic/CMakeLists.txt
+++ b/examples/device/audio_4_channel_mic/CMakeLists.txt
@@ -23,9 +23,16 @@ target_sources(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
   )
 
+# CMSIS sources
+target_sources(${PROJECT} PUBLIC
+  ${TOP}/lib/CMSIS_5/CMSIS/DSP/Source/CommonTables/arm_common_tables.c
+  ${TOP}/lib/CMSIS_5/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c
+  )
+
 # Example include
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
+  ${TOP}/lib/CMSIS_5/CMSIS/DSP/Include
   )
 
 # Configure compilation flags and libraries for the example without RTOS.
diff --git a/examples/device/audio_4_channel_mic/Makefile b/examples/device/audio_4_channel_mic/Makefile
index 2a3d854fb..97e4118c0 100644
--- a/examples/device/audio_4_channel_mic/Makefile
+++ b/examples/device/audio_4_channel_mic/Makefile
@@ -3,9 +3,18 @@ include ../../make.mk
 INC += \
   src \
   $(TOP)/hw \
+  $(TOP)/lib/CMSIS_5/CMSIS/DSP/Include \
 
 # Example source
-EXAMPLE_SOURCE += $(wildcard src/*.c)
+EXAMPLE_SOURCE += \
+  src/main.c \
+  src/usb_descriptors.c \
+
+# CMSIS sources
+SRC_C += \
+  lib/CMSIS_5/CMSIS/DSP/Source/CommonTables/arm_common_tables.c \
+  lib/CMSIS_5/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c \
+
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 include ../../rules.mk

From e2852da668ae5f8e2398ac0a4c2a93d5f50f2618 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 10 Oct 2023 18:35:24 +0200
Subject: [PATCH 2076/2085] Update deps.

---
 tools/get_deps.py | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/tools/get_deps.py b/tools/get_deps.py
index 1fac291a3..8eea3e6de 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -166,8 +166,9 @@ deps_optional = {
                             'ch32v307'],
     'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
                     '20285262657d1b482d132d20d755c8c330d55c1f',
-                    'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
-                    'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 '
+                    'imxrt kinetis_k32l2 kinetis_kl lpc11 lpc13 lpc15 lpc17 lpc18 lpc40'
+                    'lpc43 lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x rp2040'
+                    'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4'
                     'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'],
     'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
                          'e73e04ca63495672d955f9268e003cffe168fcd8',

From c8430f5f85d587a996bc0301a47be12cc70cedb7 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 10 Oct 2023 19:08:25 +0200
Subject: [PATCH 2077/2085] Refactor to get rid of CMSIS DSP lib.

---
 .../device/audio_4_channel_mic/CMakeLists.txt | 12 ++--
 examples/device/audio_4_channel_mic/Makefile  |  6 --
 examples/device/audio_4_channel_mic/skip.txt  |  1 +
 .../device/audio_4_channel_mic/src/main.c     | 55 +++++++++++--------
 tools/get_deps.py                             |  5 +-
 5 files changed, 40 insertions(+), 39 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/CMakeLists.txt b/examples/device/audio_4_channel_mic/CMakeLists.txt
index ae6bf0142..0f5d36193 100644
--- a/examples/device/audio_4_channel_mic/CMakeLists.txt
+++ b/examples/device/audio_4_channel_mic/CMakeLists.txt
@@ -23,18 +23,16 @@ target_sources(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c
   )
 
-# CMSIS sources
-target_sources(${PROJECT} PUBLIC
-  ${TOP}/lib/CMSIS_5/CMSIS/DSP/Source/CommonTables/arm_common_tables.c
-  ${TOP}/lib/CMSIS_5/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c
-  )
-
 # Example include
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src
-  ${TOP}/lib/CMSIS_5/CMSIS/DSP/Include
   )
 
+# Add libm for GCC
+if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+  target_link_libraries(${PROJECT} PUBLIC m)
+endif()
+
 # Configure compilation flags and libraries for the example without RTOS.
 # See the corresponding function in hw/bsp/FAMILY/family.cmake for details.
 family_configure_device_example(${PROJECT} noos)
diff --git a/examples/device/audio_4_channel_mic/Makefile b/examples/device/audio_4_channel_mic/Makefile
index 97e4118c0..8ee6a01ec 100644
--- a/examples/device/audio_4_channel_mic/Makefile
+++ b/examples/device/audio_4_channel_mic/Makefile
@@ -3,18 +3,12 @@ include ../../make.mk
 INC += \
   src \
   $(TOP)/hw \
-  $(TOP)/lib/CMSIS_5/CMSIS/DSP/Include \
 
 # Example source
 EXAMPLE_SOURCE += \
   src/main.c \
   src/usb_descriptors.c \
 
-# CMSIS sources
-SRC_C += \
-  lib/CMSIS_5/CMSIS/DSP/Source/CommonTables/arm_common_tables.c \
-  lib/CMSIS_5/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c \
-
 SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE))
 
 include ../../rules.mk
diff --git a/examples/device/audio_4_channel_mic/skip.txt b/examples/device/audio_4_channel_mic/skip.txt
index 1ee86a485..3c42a96d9 100644
--- a/examples/device/audio_4_channel_mic/skip.txt
+++ b/examples/device/audio_4_channel_mic/skip.txt
@@ -1,3 +1,4 @@
 mcu:SAMD11
 mcu:SAME5X
 mcu:SAMG
+family:broadcom_64bit
diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 3b21b4ac6..4bcbdb692 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -34,7 +34,7 @@
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
-#include "arm_math.h"
+#include <math.h>
 
 #include "bsp/board_api.h"
 #include "tusb.h"
@@ -96,6 +96,27 @@ int main(void)
   sampleFreqRng.subrange[0].bMax = AUDIO_SAMPLE_RATE;
   sampleFreqRng.subrange[0].bRes = 0;
 
+  // Generate dummy data
+  uint16_t * p_buff = i2s_dummy_buffer[0];
+  uint16_t dataVal = 1;
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH0 saw wave
+    *p_buff++ = dataVal;
+    // CH1 inverted saw wave
+    *p_buff++ = 60 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+    dataVal++;
+  }
+  p_buff = i2s_dummy_buffer[1];
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH3 square wave
+    *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 120:170;
+    // CH4 sinus wave
+    float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+    *p_buff++ = (uint16_t)(sinf(t) * 25) + 200;
+  }
+
   while (1)
   {
     tud_task(); // tinyusb device task
@@ -399,7 +420,16 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
   (void) ep_in;
   (void) cur_alt_setting;
 
-  // Write buffer[0] (CH0-1) and buffer[1] (CH1-2) into FIFO
+
+  // In read world application data flow is driven by I2S clock,
+  // both tud_audio_tx_done_pre_load_cb() & tud_audio_tx_done_post_load_cb() are hardly used.
+  // For example in your I2S receive callback:
+  // void I2S_Rx_Callback(int channel, const void* data, uint16_t samples)
+  // {
+  //    tud_audio_write_support_ff(channel, data, samples * N_BYTES_PER_SAMPLE * N_CHANNEL_PER_FIFO);
+  // }
+
+  // Write I2S buffer into FIFO
   for (uint8_t cnt=0; cnt < 2; cnt++)
   {
     tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
@@ -416,27 +446,6 @@ bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uin
   (void) ep_in;
   (void) cur_alt_setting;
 
-  // Generate dummy data
-  uint16_t * p_buff = i2s_dummy_buffer[0];
-  uint16_t dataVal = 1;
-  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
-  {
-    // CH0 saw wave
-    *p_buff++ = dataVal;
-    // CH1 inverted saw wave
-    *p_buff++ = 60 + AUDIO_SAMPLE_RATE/1000 - dataVal;
-    dataVal++;
-  }
-  p_buff = i2s_dummy_buffer[1];
-  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
-  {
-    // CH3 square wave
-    *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 120:170;
-    // CH4 sinus wave
-    q15_t t = 0x7FFF * cnt / (AUDIO_SAMPLE_RATE/1000);
-    *p_buff++ = arm_sin_q15(t) / 1300 + 200;
-  }
-
   return true;
 }
 
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 8eea3e6de..1fac291a3 100644
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -166,9 +166,8 @@ deps_optional = {
                             'ch32v307'],
     'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
                     '20285262657d1b482d132d20d755c8c330d55c1f',
-                    'imxrt kinetis_k32l2 kinetis_kl lpc11 lpc13 lpc15 lpc17 lpc18 lpc40'
-                    'lpc43 lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x rp2040'
-                    'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4'
+                    'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x'
+                    'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 '
                     'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb'],
     'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
                          'e73e04ca63495672d955f9268e003cffe168fcd8',

From 656e1e416aa9dbd7ba4c18e777f7294a101f0667 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 17 Oct 2023 09:46:01 +0200
Subject: [PATCH 2078/2085] Add flow control for IN transfer.

---
 .../device/audio_4_channel_mic/src/main.c     |  30 +++-
 .../src/plot_audio_samples.py                 |   7 +-
 .../audio_4_channel_mic/src/tusb_config.h     |  15 +-
 src/class/audio/audio_device.c                | 140 ++++++++++++++++--
 src/class/audio/audio_device.h                |  16 ++
 5 files changed, 187 insertions(+), 21 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 4bcbdb692..52e6d71f7 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -69,8 +69,13 @@ uint8_t clkValid;
 audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; 			// Volume range state
 audio_control_range_4_n_t(1) sampleFreqRng; 						// Sample frequency range state
 
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
 // Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2
 uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ/2];   // Ensure half word aligned
+#else
+// Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3
+uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_EP_SZ_IN];   // Ensure half word aligned
+#endif
 
 void led_blinking_task(void);
 void audio_task(void);
@@ -97,6 +102,7 @@ int main(void)
   sampleFreqRng.subrange[0].bRes = 0;
 
   // Generate dummy data
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
   uint16_t * p_buff = i2s_dummy_buffer[0];
   uint16_t dataVal = 1;
   for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
@@ -116,6 +122,23 @@ int main(void)
     float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
     *p_buff++ = (uint16_t)(sinf(t) * 25) + 200;
   }
+#else
+  uint16_t * p_buff = i2s_dummy_buffer;
+  uint16_t dataVal = 1;
+  for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
+  {
+    // CH0 saw wave
+    *p_buff++ = dataVal;
+    // CH1 inverted saw wave
+    *p_buff++ = 60 + AUDIO_SAMPLE_RATE/1000 - dataVal;
+    dataVal++;
+    // CH3 square wave
+    *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 120:170;
+    // CH4 sinus wave
+    float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
+    *p_buff++ = (uint16_t)(sinf(t) * 25) + 200;
+  }
+#endif
 
   while (1)
   {
@@ -384,6 +407,8 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
         {
           case AUDIO_CS_REQ_CUR:
             TU_LOG2("    Get Sample Freq.\r\n");
+            // Set sample rate for flow control
+            tud_audio_set_tx_flow_control(sampFreq);
             return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
 
           case AUDIO_CS_REQ_RANGE:
@@ -429,12 +454,15 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
   //    tud_audio_write_support_ff(channel, data, samples * N_BYTES_PER_SAMPLE * N_CHANNEL_PER_FIFO);
   // }
 
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
   // Write I2S buffer into FIFO
   for (uint8_t cnt=0; cnt < 2; cnt++)
   {
     tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
   }
-
+#else
+  tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX);
+#endif
   return true;
 }
 
diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
index a3a2b2fd4..d17a908b6 100644
--- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
+++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py
@@ -10,11 +10,11 @@ if __name__ == '__main__':
     # print(sd.query_devices())
 
     fs = 48000  		# Sample rate
-    duration = 20e-3   # Duration of recording
+    duration = 1   # Duration of recording
 
     if platform.system() == 'Windows':
         # WDM-KS is needed since there are more than one MicNode device APIs (at least in Windows)
-        device = 'Microphone (MicNode_4_Ch), Windows WDM-KS'
+        device = 'Microphone (MicNode_4_Ch), Windows WASAPI'
     elif platform.system() == 'Darwin':
         device = 'MicNode_4_Ch'
     else:
@@ -28,8 +28,7 @@ if __name__ == '__main__':
 
     time = np.arange(0, duration, 1 / fs)  # time vector
     # strip starting zero
-    myrecording = myrecording[100:]
-    time = time[100:]
+
     plt.plot(time, myrecording)
     plt.xlabel('Time [s]')
     plt.ylabel('Amplitude')
diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index 291ac4f79..d1e19c5a1 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -114,14 +114,25 @@ extern "C" {
 #define CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX    2         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX            4         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
 #define CFG_TUD_AUDIO_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
+
+#define CFG_TUD_AUDIO_ENABLE_ENCODING                 0
+
+#if CFG_TUD_AUDIO_ENABLE_ENCODING
+
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          CFG_TUD_AUDIO_EP_SZ_IN
 
-#define CFG_TUD_AUDIO_ENABLE_ENCODING                 1
 #define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING          1
 #define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX      2         // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
 #define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO        (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
-#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO)
+#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO)
+
+#else
+
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             4 * CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          4 * CFG_TUD_AUDIO_EP_SZ_IN
+
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 5d3772a9d..9299440c9 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -364,14 +364,21 @@ typedef struct
 #endif
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  uint32_t sample_rate_tx;
+  uint16_t packet_sz_tx[3];
+  uint8_t bclock_id_tx;
+  uint8_t interval_tx;
+#endif
+
   // Encoding parameters - parameters are set when alternate AS interface is set by host
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL)
   audio_format_type_t format_type_tx;
   uint8_t n_channels_tx;
+  uint8_t n_bytes_per_sampe_tx;
 
 #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
   audio_data_format_type_I_t format_type_I_tx;
-  uint8_t n_bytes_per_sampe_tx;
   uint8_t n_channels_per_ff_tx;
   uint8_t n_ff_used_tx;
 #endif
@@ -444,7 +451,7 @@ static bool audiod_verify_itf_exists(uint8_t itf, uint8_t *func_id);
 static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id);
 static uint8_t audiod_get_audio_fct_idx(audiod_function_t * audio);
 
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING
+#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING)
 static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const * p_desc, uint8_t const * p_desc_end, uint8_t const as_itf);
 
 static inline uint8_t tu_desc_subtype(void const* desc)
@@ -453,6 +460,10 @@ static inline uint8_t tu_desc_subtype(void const* desc)
 }
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size);
+#endif
+
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 static bool set_fb_params_freq(audiod_function_t* audio, uint32_t sample_freq, uint32_t mclk_freq);
 #endif
@@ -821,6 +832,57 @@ uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint1
 
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+
+bool tud_audio_n_set_tx_flow_control(uint8_t func_id, uint32_t sample_rate)
+{
+  TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
+  audiod_function_t* audio = &_audiod_fct[func_id];
+
+  TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I);
+  TU_VERIFY(audio->n_channels_tx);
+  TU_VERIFY(audio->n_bytes_per_sampe_tx);
+  TU_VERIFY(audio->interval_tx);
+
+  if (sample_rate == 0)
+  {
+    audio->packet_sz_tx[0] = 0;
+    audio->packet_sz_tx[1] = 0;
+    audio->packet_sz_tx[2] = 0;
+    return false;
+  }
+
+  const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1);
+
+  const uint32_t sample_normimal = sample_rate * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
+  const uint32_t sample_reminder = sample_rate * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
+
+  const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+  const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+  const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+
+  TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz);
+
+  // Frmt20.pdf 2.3.1.1 USB Packets
+  if (sample_reminder)
+  {
+    // All virtual frame packets must either contain INT(nav) audio slots (small VFP) or INT(nav)+1 (large VFP) audio slots
+    audio->packet_sz_tx[0] = packet_sz_tx_norm;
+    audio->packet_sz_tx[1] = packet_sz_tx_norm;
+    audio->packet_sz_tx[2] = packet_sz_tx_max;
+  } else
+  {
+    // In the case where nav = INT(nav), ni may vary between INT(nav)-1 (small VFP), INT(nav)
+    // (medium VFP) and INT(nav)+1 (large VFP).
+    audio->packet_sz_tx[0] = packet_sz_tx_min;
+    audio->packet_sz_tx[1] = packet_sz_tx_norm;
+    audio->packet_sz_tx[2] = packet_sz_tx_max;
+  }
+
+  return true;
+}
+
+#endif
 
 // This function is called once a transmit of an audio packet was successfully completed. Here, we encode samples and place it in IN EP's buffer for next transmission.
 // If you prefer your own (more efficient) implementation suiting your purpose set CFG_TUD_AUDIO_ENABLE_ENCODING = 0 and use tud_audio_n_write.
@@ -886,9 +948,16 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio)
 
 #else
   // No support FIFOs, if no linear buffer required schedule transmit, else put data into linear buffer and schedule
-
+#if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  uint16_t tgt_packet_sz;
+  // packet_sz_tx is based on total packet size, here we want size for each support buffer.
+  if (audiod_tx_calc_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, &tgt_packet_sz))
+    n_bytes_tx = tgt_packet_sz;
+  else
+    n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);
+#else
   n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);      // Limit up to max packet size, more can not be done for ISO
-
+#endif
 #if USE_LINEAR_BUFFER_TX
   tu_fifo_read_n(&audio->ep_in_ff, audio->lin_buf_in, n_bytes_tx);
   TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_in, audio->lin_buf_in, n_bytes_tx));
@@ -987,7 +1056,6 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
 
   // Determine amount of samples
   uint8_t const n_ff_used               = audio->n_ff_used_tx;
-  uint16_t const nBytesToCopy           = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx;
   uint16_t const capPerFF               = audio->ep_in_sz / n_ff_used;                                        // Sample capacity per FIFO in bytes
   uint16_t nBytesPerFFToSend            = tu_fifo_count(&audio->tx_supp_ff[0]);
   uint8_t cnt_ff;
@@ -1001,14 +1069,24 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
     }
   }
 
-  // Check if there is enough
+#if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  uint16_t tgt_packet_sz;
+  // packet_sz_tx is based on total packet size, here we want size for each support buffer.
+  if (audiod_tx_calc_packet_size(audio->packet_sz_tx, nBytesPerFFToSend * n_ff_used, audio->tx_supp_ff[0].depth * n_ff_used, &tgt_packet_sz))
+    nBytesPerFFToSend = tgt_packet_sz / n_ff_used;
+#endif
+
+  // Check if there is enough data
   if (nBytesPerFFToSend == 0)    return 0;
 
   // Limit to maximum sample number - THIS IS A POSSIBLE ERROR SOURCE IF TOO MANY SAMPLE WOULD NEED TO BE SENT BUT CAN NOT!
   nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, capPerFF);
 
+#if !CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
   // Round to full number of samples (flooring)
-  nBytesPerFFToSend = (nBytesPerFFToSend / nBytesToCopy) * nBytesToCopy;
+  uint16_t const nSlotSize = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx;
+  nBytesPerFFToSend = (nBytesPerFFToSend / nSlotSize) * nSlotSize;
+#endif
 
   // Encode
   uint8_t * dst;
@@ -1489,6 +1567,9 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
   #if CFG_TUD_AUDIO_ENABLE_EP_IN
                 ep_in = desc_ep->bEndpointAddress;
                 ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
+    #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+                _audiod_fct[i].interval_tx = desc_ep->bInterval;
+    #endif
   #endif
               } else
               {
@@ -1607,6 +1688,11 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
 
     audio->ep_in = 0;                           // Necessary?
 
+  #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+    audio->packet_sz_tx[0] = 0;
+    audio->packet_sz_tx[1] = 0;
+    audio->packet_sz_tx[2] = 0;
+  #endif
   }
 #endif // CFG_TUD_AUDIO_ENABLE_EP_IN
 
@@ -1657,7 +1743,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
     // Find correct interface
     if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const * )p_desc)->bInterfaceNumber == itf && ((tusb_desc_interface_t const * )p_desc)->bAlternateSetting == alt)
     {
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING
+#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
       uint8_t const * p_desc_parse_for_params = p_desc;
 #endif
       // From this point forward follow the EP descriptors associated to the current alternate setting interface - Open EPs if necessary
@@ -1686,12 +1772,13 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
             audio->ep_in_sz = tu_edpt_packet_size(desc_ep);
 
             // If software encoding is enabled, parse for the corresponding parameters - doing this here means only AS interfaces with EPs get scanned for parameters
-  #if CFG_TUD_AUDIO_ENABLE_ENCODING
+  #if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
             audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf);
 
             // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap
-    #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
-            const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / audio->n_bytes_per_sampe_tx) * audio->n_bytes_per_sampe_tx);
+    #if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+            const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / (audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx))
+               * (audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx));
             for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++)
             {
               tu_fifo_config(&audio->tx_supp_ff[cnt], audio->tx_supp_ff[cnt].buffer, active_fifo_depth, 1, true);
@@ -2404,7 +2491,7 @@ static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id)
   return false;
 }
 
-#if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_ENABLE_DECODING
+#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING)
 // p_desc points to the AS interface of alternate setting zero
 // itf is the interface number of the corresponding interface - we check if the interface belongs to EP in or EP out to see if it is a TX or RX parameter
 // Currently, only AS interfaces with an EP (in or out) are supposed to be parsed for!
@@ -2455,7 +2542,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
     }
 
     // Look for a Type I Format Type Descriptor(2.3.1.6 - Audio Formats)
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING || CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
+#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING
     if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_FORMAT_TYPE && ((audio_desc_type_I_format_t const * )p_desc)->bFormatType == AUDIO_FORMAT_TYPE_I)
     {
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT
@@ -2491,6 +2578,31 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
 }
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size)
+{
+  TU_VERIFY(norminal_size[1]);
+
+  // This flow control method need a FIFO size of 4*Navg
+  TU_VERIFY(norminal_size[1] <= fifo_size * 4);
+
+  if (data_size < norminal_size[0])
+    *packet_size = 0;
+  else
+  {
+    uint16_t slot_size = norminal_size[2] - norminal_size[1];
+    if (data_size < fifo_size / 2 - slot_size)
+      *packet_size = norminal_size[0];
+    else if (data_size > fifo_size / 2 + slot_size)
+      *packet_size = norminal_size[2];
+    else
+      *packet_size = norminal_size[1];
+  }
+
+  return true;
+}
+#endif
+
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback)
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 7c88b99fc..4cb3ca84c 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -181,6 +181,11 @@
 #endif
 #endif
 
+// (For TYPE-I format only) Flow control is necessary to allow IN ep send correct amount of data, unless it's a virtual device where data is perfectly synchronized to USB clock.
+#ifndef CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL  1
+#endif
+
 // Enable/disable feedback EP (required for asynchronous RX applications)
 #ifndef CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 #define CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP                    0                             // Feedback - 0 or 1
@@ -392,6 +397,10 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff          (uint8_t func_id, uint8_t ff_i
 uint16_t    tud_audio_int_ctr_n_write             (uint8_t func_id, uint8_t const* buffer, uint16_t len);
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+bool tud_audio_n_set_tx_flow_control       (uint8_t func_id, uint32_t sample_rate);
+#endif
+
 //--------------------------------------------------------------------+
 // Application API (Interface0)
 //--------------------------------------------------------------------+
@@ -670,6 +679,13 @@ static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t l
 }
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+static inline bool tud_audio_set_tx_flow_control(uint32_t sample_rate)
+{
+  return tud_audio_n_set_tx_flow_control(0, sample_rate);
+}
+#endif
+
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 static inline bool tud_audio_fb_set(uint32_t feedback)

From 0a1d6cf4d028bce2248da01b8cc13aa4673e61b5 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 17 Oct 2023 13:06:55 +0200
Subject: [PATCH 2079/2085] Read sample rate directly from control transfer to
 eliminate callback.

---
 .../device/audio_4_channel_mic/src/main.c     |   5 +-
 src/class/audio/audio_device.c                | 343 ++++++++++--------
 src/class/audio/audio_device.h                |  10 -
 3 files changed, 194 insertions(+), 164 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c
index 52e6d71f7..9c37315c8 100644
--- a/examples/device/audio_4_channel_mic/src/main.c
+++ b/examples/device/audio_4_channel_mic/src/main.c
@@ -407,9 +407,8 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *
         {
           case AUDIO_CS_REQ_CUR:
             TU_LOG2("    Get Sample Freq.\r\n");
-            // Set sample rate for flow control
-            tud_audio_set_tx_flow_control(sampFreq);
-            return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
+            // Buffered control transfer is needed for IN flow control to work
+            return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
 
           case AUDIO_CS_REQ_RANGE:
             TU_LOG2("    Get Sample Freq. range\r\n");
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 9299440c9..e246281be 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -461,7 +461,8 @@ static inline uint8_t tu_desc_subtype(void const* desc)
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size);
+static bool audiod_calc_tx_packet_sz(audiod_function_t* audio);
+static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t data_count, uint16_t fifo_depth, uint16_t max_size);
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
@@ -832,58 +833,6 @@ uint16_t tud_audio_int_ctr_n_write(uint8_t func_id, uint8_t const* buffer, uint1
 
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-
-bool tud_audio_n_set_tx_flow_control(uint8_t func_id, uint32_t sample_rate)
-{
-  TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL);
-  audiod_function_t* audio = &_audiod_fct[func_id];
-
-  TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I);
-  TU_VERIFY(audio->n_channels_tx);
-  TU_VERIFY(audio->n_bytes_per_sampe_tx);
-  TU_VERIFY(audio->interval_tx);
-
-  if (sample_rate == 0)
-  {
-    audio->packet_sz_tx[0] = 0;
-    audio->packet_sz_tx[1] = 0;
-    audio->packet_sz_tx[2] = 0;
-    return false;
-  }
-
-  const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1);
-
-  const uint32_t sample_normimal = sample_rate * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
-  const uint32_t sample_reminder = sample_rate * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
-
-  const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
-  const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
-  const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
-
-  TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz);
-
-  // Frmt20.pdf 2.3.1.1 USB Packets
-  if (sample_reminder)
-  {
-    // All virtual frame packets must either contain INT(nav) audio slots (small VFP) or INT(nav)+1 (large VFP) audio slots
-    audio->packet_sz_tx[0] = packet_sz_tx_norm;
-    audio->packet_sz_tx[1] = packet_sz_tx_norm;
-    audio->packet_sz_tx[2] = packet_sz_tx_max;
-  } else
-  {
-    // In the case where nav = INT(nav), ni may vary between INT(nav)-1 (small VFP), INT(nav)
-    // (medium VFP) and INT(nav)+1 (large VFP).
-    audio->packet_sz_tx[0] = packet_sz_tx_min;
-    audio->packet_sz_tx[1] = packet_sz_tx_norm;
-    audio->packet_sz_tx[2] = packet_sz_tx_max;
-  }
-
-  return true;
-}
-
-#endif
-
 // This function is called once a transmit of an audio packet was successfully completed. Here, we encode samples and place it in IN EP's buffer for next transmission.
 // If you prefer your own (more efficient) implementation suiting your purpose set CFG_TUD_AUDIO_ENABLE_ENCODING = 0 and use tud_audio_n_write.
 
@@ -949,12 +898,8 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t * audio)
 #else
   // No support FIFOs, if no linear buffer required schedule transmit, else put data into linear buffer and schedule
 #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-  uint16_t tgt_packet_sz;
   // packet_sz_tx is based on total packet size, here we want size for each support buffer.
-  if (audiod_tx_calc_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, &tgt_packet_sz))
-    n_bytes_tx = tgt_packet_sz;
-  else
-    n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);
+  n_bytes_tx = audiod_tx_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, audio->ep_in_sz);
 #else
   n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);      // Limit up to max packet size, more can not be done for ISO
 #endif
@@ -1056,7 +1001,6 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
 
   // Determine amount of samples
   uint8_t const n_ff_used               = audio->n_ff_used_tx;
-  uint16_t const capPerFF               = audio->ep_in_sz / n_ff_used;                                        // Sample capacity per FIFO in bytes
   uint16_t nBytesPerFFToSend            = tu_fifo_count(&audio->tx_supp_ff[0]);
   uint8_t cnt_ff;
 
@@ -1070,19 +1014,18 @@ static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t* audi
   }
 
 #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-  uint16_t tgt_packet_sz;
+  const uint16_t norm_packet_sz_tx[3] = {audio->packet_sz_tx[0] / n_ff_used,
+                                         audio->packet_sz_tx[1] / n_ff_used,
+                                         audio->packet_sz_tx[2] / n_ff_used};
   // packet_sz_tx is based on total packet size, here we want size for each support buffer.
-  if (audiod_tx_calc_packet_size(audio->packet_sz_tx, nBytesPerFFToSend * n_ff_used, audio->tx_supp_ff[0].depth * n_ff_used, &tgt_packet_sz))
-    nBytesPerFFToSend = tgt_packet_sz / n_ff_used;
-#endif
-
+  nBytesPerFFToSend = audiod_tx_packet_size(norm_packet_sz_tx, nBytesPerFFToSend, audio->tx_supp_ff[0].depth, audio->ep_in_sz / n_ff_used);
+  // Check if there is enough data
+  if (nBytesPerFFToSend == 0)    return 0;
+#else
   // Check if there is enough data
   if (nBytesPerFFToSend == 0)    return 0;
-
   // Limit to maximum sample number - THIS IS A POSSIBLE ERROR SOURCE IF TOO MANY SAMPLE WOULD NEED TO BE SENT BUT CAN NOT!
-  nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, capPerFF);
-
-#if !CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, audio->ep_in_sz / n_ff_used);
   // Round to full number of samples (flooring)
   uint16_t const nSlotSize = audio->n_channels_per_ff_tx * audio->n_bytes_per_sampe_tx;
   nBytesPerFFToSend = (nBytesPerFFToSend / nSlotSize) * nSlotSize;
@@ -1349,7 +1292,7 @@ void audiod_init(void)
 #endif // CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
 
     // Set encoding parameters for Type_I formats
-#if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING
     switch (i)
     {
 #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
@@ -1529,84 +1472,114 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin
       }
 
 #if USE_ISO_EP_ALLOCATION
-  #if CFG_TUD_AUDIO_ENABLE_EP_IN
-      uint8_t  ep_in = 0;
-      uint16_t ep_in_size = 0;
-  #endif
-
-  #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-      uint8_t  ep_out = 0;
-      uint16_t ep_out_size = 0;
-  #endif
-
-  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-      uint8_t ep_fb = 0;
-  #endif
-
-      uint8_t const *p_desc = _audiod_fct[i].p_desc;
-      uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
-      while (p_desc < p_desc_end)
       {
-        if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
-        {
-          tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
-          if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
-          {
-  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-            // Explicit feedback EP
-            if (desc_ep->bmAttributes.usage == 1)
-            {
-              ep_fb = desc_ep->bEndpointAddress;
-            }
-  #endif
-            // Data EP
-            if (desc_ep->bmAttributes.usage == 0)
-            {
-              if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
-              {
   #if CFG_TUD_AUDIO_ENABLE_EP_IN
-                ep_in = desc_ep->bEndpointAddress;
-                ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
-    #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-                _audiod_fct[i].interval_tx = desc_ep->bInterval;
-    #endif
+        uint8_t  ep_in = 0;
+        uint16_t ep_in_size = 0;
   #endif
-              } else
-              {
+
   #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-                ep_out = desc_ep->bEndpointAddress;
-                ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size);
+        uint8_t  ep_out = 0;
+        uint16_t ep_out_size = 0;
   #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+        uint8_t ep_fb = 0;
+  #endif
+        uint8_t const *p_desc = _audiod_fct[i].p_desc;
+        uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
+        while (p_desc < p_desc_end)
+        {
+          if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
+          {
+            tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+            if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
+            {
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+              // Explicit feedback EP
+              if (desc_ep->bmAttributes.usage == 1)
+              {
+                ep_fb = desc_ep->bEndpointAddress;
+              }
+  #endif
+              // Data EP
+              if (desc_ep->bmAttributes.usage == 0)
+              {
+                if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
+                {
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN
+                  ep_in = desc_ep->bEndpointAddress;
+                  ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size);
+  #endif
+                } else
+                {
+  #if CFG_TUD_AUDIO_ENABLE_EP_OUT
+                  ep_out = desc_ep->bEndpointAddress;
+                  ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size);
+  #endif
+                }
+              }
+
+            }
+          }
+
+          p_desc = tu_desc_next(p_desc);
+        }
+
+  #if CFG_TUD_AUDIO_ENABLE_EP_IN
+        if (ep_in)
+        {
+          usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size);
+        }
+  #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_EP_OUT
+        if (ep_out)
+        {
+          usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size);
+        }
+  #endif
+
+  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
+        if (ep_fb)
+        {
+          usbd_edpt_iso_alloc(rhport, ep_fb, 4);
+        }
+  #endif
+      }
+#endif // USE_ISO_EP_ALLOCATION
+
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+      {
+        uint8_t const *p_desc = _audiod_fct[i].p_desc;
+        uint8_t const *p_desc_end = p_desc + _audiod_fct[i].desc_length - TUD_AUDIO_DESC_IAD_LEN;
+        while (p_desc < p_desc_end)
+        {
+          if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT)
+          {
+            tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+            if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS)
+            {
+              if (desc_ep->bmAttributes.usage == 0)
+              {
+                if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN)
+                {
+                  _audiod_fct[i].interval_tx = desc_ep->bInterval;
+                }
               }
             }
-
+          } else
+          if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AC_INTERFACE_OUTPUT_TERMINAL)
+          {
+            if(tu_unaligned_read16(p_desc + 4) == AUDIO_TERM_TYPE_USB_STREAMING)
+            {
+               _audiod_fct[i].bclock_id_tx = p_desc[8];
+            }
           }
+          p_desc = tu_desc_next(p_desc);
         }
-        p_desc = tu_desc_next(p_desc);
       }
-
-  #if CFG_TUD_AUDIO_ENABLE_EP_IN
-      if (ep_in)
-      {
-        usbd_edpt_iso_alloc(rhport, ep_in, ep_in_size);
-      }
-  #endif
-
-  #if CFG_TUD_AUDIO_ENABLE_EP_OUT
-      if (ep_out)
-      {
-        usbd_edpt_iso_alloc(rhport, ep_out, ep_out_size);
-      }
-  #endif
-
-  #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
-      if (ep_fb)
-      {
-        usbd_edpt_iso_alloc(rhport, ep_fb, 4);
-      }
-  #endif
-
-#endif // USE_ISO_EP_ALLOCATION
+#endif // CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
 
       break;
     }
@@ -1910,6 +1883,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *
   if (disable) usbd_sof_enable(rhport, false);
 #endif
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  audiod_calc_tx_packet_sz(audio);
+#endif
+
   tud_control_status(rhport, p_request);
 
   return true;
@@ -2352,6 +2329,19 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req
   // Copy into buffer
   TU_VERIFY(0 == tu_memcpy_s(_audiod_fct[func_id].ctrl_buf, _audiod_fct[func_id].ctrl_buf_sz, data, (size_t)len));
 
+#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
+  // Find data for sampling_frequency_control
+  if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS && p_request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_INTERFACE)
+  {
+    uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
+    uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
+    if (_audiod_fct[func_id].bclock_id_tx == entityID && ctrlSel == AUDIO_CS_CTRL_SAM_FREQ && p_request->bRequest == AUDIO_CS_REQ_CUR)
+    {
+      _audiod_fct[func_id].sample_rate_tx = tu_unaligned_read32(_audiod_fct[func_id].ctrl_buf);
+    }
+  }
+#endif
+
   // Schedule transmit
   return tud_control_xfer(rhport, p_request, (void*)_audiod_fct[func_id].ctrl_buf, len);
 }
@@ -2579,28 +2569,79 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-static bool audiod_tx_calc_packet_size(const uint16_t* norminal_size, uint16_t data_size, uint16_t fifo_size, uint16_t* packet_size)
+
+static bool audiod_calc_tx_packet_sz(audiod_function_t* audio)
 {
-  TU_VERIFY(norminal_size[1]);
+  TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I);
+  TU_VERIFY(audio->n_channels_tx);
+  TU_VERIFY(audio->n_bytes_per_sampe_tx);
+  TU_VERIFY(audio->interval_tx);
+  TU_VERIFY(audio->sample_rate_tx);
 
-  // This flow control method need a FIFO size of 4*Navg
-  TU_VERIFY(norminal_size[1] <= fifo_size * 4);
+  const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1);
 
-  if (data_size < norminal_size[0])
-    *packet_size = 0;
-  else
+  const uint32_t sample_normimal = audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
+  const uint32_t sample_reminder = audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
+
+  const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+  const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+  const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+
+  // Endpoint size must larger than packet size
+  TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz);
+
+  // Frmt20.pdf 2.3.1.1 USB Packets
+  if (sample_reminder)
   {
-    uint16_t slot_size = norminal_size[2] - norminal_size[1];
-    if (data_size < fifo_size / 2 - slot_size)
-      *packet_size = norminal_size[0];
-    else if (data_size > fifo_size / 2 + slot_size)
-      *packet_size = norminal_size[2];
-    else
-      *packet_size = norminal_size[1];
+    // All virtual frame packets must either contain INT(nav) audio slots (small VFP) or INT(nav)+1 (large VFP) audio slots
+    audio->packet_sz_tx[0] = packet_sz_tx_norm;
+    audio->packet_sz_tx[1] = packet_sz_tx_norm;
+    audio->packet_sz_tx[2] = packet_sz_tx_max;
+  } else
+  {
+    // In the case where nav = INT(nav), ni may vary between INT(nav)-1 (small VFP), INT(nav)
+    // (medium VFP) and INT(nav)+1 (large VFP).
+    audio->packet_sz_tx[0] = packet_sz_tx_min;
+    audio->packet_sz_tx[1] = packet_sz_tx_norm;
+    audio->packet_sz_tx[2] = packet_sz_tx_max;
   }
 
   return true;
 }
+
+static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t data_count, uint16_t fifo_depth, uint16_t max_depth)
+{
+  // Flow control need a FIFO size of at least 4*Navg
+  if(norminal_size[1] && norminal_size[1] <= fifo_depth * 4)
+  {
+    uint16_t packet_size;
+    uint16_t slot_size = norminal_size[2] - norminal_size[1];
+    if (data_count < fifo_depth / 2 - slot_size)
+    {
+      if (data_count < norminal_size[0])
+      {
+        // If you get here frequently, then your I2S clock deviation is too big !
+        packet_size = 0;
+      } else
+      {
+        packet_size = norminal_size[0];
+      }
+    }
+    else if (data_count > fifo_depth / 2 + slot_size)
+    {
+      packet_size = norminal_size[2];
+    } else
+    {
+      packet_size = norminal_size[1];
+    }
+    // Normally this cap is not necessary
+    return tu_min16(packet_size, max_depth);
+  } else
+  {
+    return tu_min16(data_count, max_depth);
+  }
+}
+
 #endif
 
 #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h
index 4cb3ca84c..ef3e12a06 100644
--- a/src/class/audio/audio_device.h
+++ b/src/class/audio/audio_device.h
@@ -397,9 +397,6 @@ tu_fifo_t* tud_audio_n_get_tx_support_ff          (uint8_t func_id, uint8_t ff_i
 uint16_t    tud_audio_int_ctr_n_write             (uint8_t func_id, uint8_t const* buffer, uint16_t len);
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-bool tud_audio_n_set_tx_flow_control       (uint8_t func_id, uint32_t sample_rate);
-#endif
 
 //--------------------------------------------------------------------+
 // Application API (Interface0)
@@ -679,13 +676,6 @@ static inline uint16_t tud_audio_int_ctr_write(uint8_t const* buffer, uint16_t l
 }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL
-static inline bool tud_audio_set_tx_flow_control(uint32_t sample_rate)
-{
-  return tud_audio_n_set_tx_flow_control(0, sample_rate);
-}
-#endif
-
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP
 
 static inline bool tud_audio_fb_set(uint32_t feedback)

From d83a2107883c8a6224ab99f248a59b216a8d2a82 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 17 Oct 2023 15:18:05 +0200
Subject: [PATCH 2080/2085] Add blackout time.

---
 src/class/audio/audio_device.c | 32 +++++++++++++++++++++++---------
 1 file changed, 23 insertions(+), 9 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index e246281be..d32ed56b2 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2614,25 +2614,39 @@ static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t da
   // Flow control need a FIFO size of at least 4*Navg
   if(norminal_size[1] && norminal_size[1] <= fifo_depth * 4)
   {
+    // Use blackout to prioritize normal size packet
+    static int ctrl_blackout = 0;
     uint16_t packet_size;
     uint16_t slot_size = norminal_size[2] - norminal_size[1];
-    if (data_count < fifo_depth / 2 - slot_size)
+    if (data_count < norminal_size[0])
     {
-      if (data_count < norminal_size[0])
-      {
         // If you get here frequently, then your I2S clock deviation is too big !
         packet_size = 0;
-      } else
-      {
-        packet_size = norminal_size[0];
-      }
-    }
-    else if (data_count > fifo_depth / 2 + slot_size)
+    } else
+    if (data_count < fifo_depth / 2 - slot_size && !ctrl_blackout)
+    {
+      packet_size = norminal_size[0];
+      ctrl_blackout = 10;
+    } else
+    if (data_count > fifo_depth / 2 + slot_size && !ctrl_blackout)
     {
       packet_size = norminal_size[2];
+      if(norminal_size[0] == norminal_size[1])
+      {
+        // nav = INT(nav) + 1
+        ctrl_blackout = 2;
+      } else
+      {
+        // nav = INT(nav)
+        ctrl_blackout = 10;
+      }
     } else
     {
       packet_size = norminal_size[1];
+      if (ctrl_blackout)
+      {
+        ctrl_blackout--;
+      }
     }
     // Normally this cap is not necessary
     return tu_min16(packet_size, max_depth);

From 22aefd6aba9cbba0faca803fb9f331ae6b0fae56 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Oct 2023 22:48:54 +0700
Subject: [PATCH 2081/2085] add cmake support for u575 nucleo

---
 .idea/cmake.xml                               |   3 +-
 .../stm32u575eval/STM32U575AIIXQ_FLASH.ld     | 167 ------------------
 hw/bsp/stm32u5/boards/stm32u575eval/board.mk  |   2 +-
 .../stm32u575nucleo/STM32U575ZITXQ_FLASH.ld   | 167 ------------------
 .../stm32u5/boards/stm32u575nucleo/board.mk   |   4 +-
 hw/bsp/stm32u5/family.cmake                   |   1 +
 6 files changed, 6 insertions(+), 338 deletions(-)
 delete mode 100644 hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld
 delete mode 100644 hw/bsp/stm32u5/boards/stm32u575nucleo/STM32U575ZITXQ_FLASH.ld

diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 9721af5ea..88e0e27ad 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -56,7 +56,6 @@
       <configuration PROFILE_NAME="portenta_c33" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=portenta_c33 -DLOG=3" />
       <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
       <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
-      <configuration PROFILE_NAME="stm32u5" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575eval" />
       <configuration PROFILE_NAME="metro esp32s2" ENABLED="false" TOOLCHAIN_NAME="ESP-IDF" GENERATION_OPTIONS="-DBOARD=adafruit_metro_esp32s2 -DMAX3421_HOST=1 -DLOG=2">
         <ADDITIONAL_GENERATION_ENVIRONMENT>
           <envs>
@@ -64,6 +63,8 @@
           </envs>
         </ADDITIONAL_GENERATION_ENVIRONMENT>
       </configuration>
+      <configuration PROFILE_NAME="stm32u575eval" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575eval" />
+      <configuration PROFILE_NAME="stm32u575nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575nucleo -DLOG=3" />
     </configurations>
   </component>
 </project>
\ No newline at end of file
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld b/hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld
deleted file mode 100644
index 03c022bc2..000000000
--- a/hw/bsp/stm32u5/boards/stm32u575eval/STM32U575AIIXQ_FLASH.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-******************************************************************************
-**
-**  File        : LinkerScript.ld
-**
-**  Author      : STM32CubeIDE
-**
-**  Abstract    : Linker script for STM32U575xI Device from STM32U5 series
-**                      2048Kbytes FLASH
-**                      784Kbytes RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Distribution: The file is distributed as is without any warranty
-**                of any kind.
-**
-*****************************************************************************
-** @attention
-**
-** Copyright (c) 2022 STMicroelectronics.
-** All rights reserved.
-**
-** This software is licensed under terms that can be found in the LICENSE file
-** in the root directory of this software component.
-** If no LICENSE file comes with this software, it is provided AS-IS.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
-
-_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
-_Min_Stack_Size = 0x400 ;	/* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 768K
-  SRAM4	(xrw)	: ORIGIN = 0x28000000,	LENGTH = 16K
-  FLASH	(rx)	: ORIGIN = 0x08000000,	LENGTH = 2048K
-}
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code into "FLASH" Rom type memory */
-  .isr_vector :
-  {
-    KEEP(*(.isr_vector)) /* Startup code */
-  } >FLASH
-
-  /* The program code and other data into "FLASH" Rom type memory */
-  .text :
-  {
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data into "FLASH" Rom type memory */
-  .rodata :
-  {
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-  } >FLASH
-
-  .ARM.extab :
-  {
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-  } >FLASH
-
-  .ARM :
-  {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections into "RAM" Ram type memory */
-  .data :
-  {
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-    *(.RamFunc)        /* .RamFunc sections */
-    *(.RamFunc*)       /* .RamFunc* sections */
-
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section into "RAM" Ram type memory */
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
index a75b2af78..37d59023f 100644
--- a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk
@@ -2,7 +2,7 @@ CFLAGS += \
   -DSTM32U575xx \
 
 # All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32U575AIIXQ_FLASH.ld
+LD_FILE = ${ST_CMSIS}/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld
 
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
 
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/STM32U575ZITXQ_FLASH.ld b/hw/bsp/stm32u5/boards/stm32u575nucleo/STM32U575ZITXQ_FLASH.ld
deleted file mode 100644
index 03c022bc2..000000000
--- a/hw/bsp/stm32u5/boards/stm32u575nucleo/STM32U575ZITXQ_FLASH.ld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-******************************************************************************
-**
-**  File        : LinkerScript.ld
-**
-**  Author      : STM32CubeIDE
-**
-**  Abstract    : Linker script for STM32U575xI Device from STM32U5 series
-**                      2048Kbytes FLASH
-**                      784Kbytes RAM
-**
-**                Set heap size, stack size and stack location according
-**                to application requirements.
-**
-**                Set memory bank area and size if external memory is used.
-**
-**  Target      : STMicroelectronics STM32
-**
-**  Distribution: The file is distributed as is without any warranty
-**                of any kind.
-**
-*****************************************************************************
-** @attention
-**
-** Copyright (c) 2022 STMicroelectronics.
-** All rights reserved.
-**
-** This software is licensed under terms that can be found in the LICENSE file
-** in the root directory of this software component.
-** If no LICENSE file comes with this software, it is provided AS-IS.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */
-
-_Min_Heap_Size = 0x200 ;	/* required amount of heap  */
-_Min_Stack_Size = 0x400 ;	/* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = 768K
-  SRAM4	(xrw)	: ORIGIN = 0x28000000,	LENGTH = 16K
-  FLASH	(rx)	: ORIGIN = 0x08000000,	LENGTH = 2048K
-}
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code into "FLASH" Rom type memory */
-  .isr_vector :
-  {
-    KEEP(*(.isr_vector)) /* Startup code */
-  } >FLASH
-
-  /* The program code and other data into "FLASH" Rom type memory */
-  .text :
-  {
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    _etext = .;        /* define a global symbols at end of code */
-  } >FLASH
-
-  /* Constant data into "FLASH" Rom type memory */
-  .rodata :
-  {
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-  } >FLASH
-
-  .ARM.extab :
-  {
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-  } >FLASH
-
-  .ARM :
-  {
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-  } >FLASH
-
-  .preinit_array :
-  {
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-  } >FLASH
-
-  .init_array :
-  {
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-  } >FLASH
-
-  .fini_array :
-  {
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-  } >FLASH
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections into "RAM" Ram type memory */
-  .data :
-  {
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-    *(.RamFunc)        /* .RamFunc sections */
-    *(.RamFunc*)       /* .RamFunc* sections */
-
-    _edata = .;        /* define a global symbol at data end */
-  } >RAM AT> FLASH
-
-  /* Uninitialized data section into "RAM" Ram type memory */
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM
-
-  /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}
diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
index 0c7948860..f07157801 100644
--- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk
@@ -2,9 +2,9 @@ CFLAGS += \
   -DSTM32U575xx \
 
 # All source paths should be relative to the top level.
-LD_FILE = $(BOARD_PATH)/STM32U575ZITXQ_FLASH.ld
+LD_FILE = ${ST_CMSIS}/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld
 
 SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
 
 # For flash-jlink target
-JLINK_DEVICE = stm32u575
+JLINK_DEVICE = stm32u575zi
diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake
index 8f9ac1109..2e4ed7d50 100644
--- a/hw/bsp/stm32u5/family.cmake
+++ b/hw/bsp/stm32u5/family.cmake
@@ -37,6 +37,7 @@ function(add_board_target BOARD_TARGET)
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
+      ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_icache.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
       ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c

From a5a77af11ea2ec37f74ecd81eb1799cc38c6fbf1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Tue, 17 Oct 2023 23:53:09 +0700
Subject: [PATCH 2082/2085] add board.mk for u575 nucleo

---
 hw/bsp/stm32u5/boards/stm32u575nucleo/board.cmake | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 hw/bsp/stm32u5/boards/stm32u575nucleo/board.cmake

diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.cmake b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.cmake
new file mode 100644
index 000000000..73bd10033
--- /dev/null
+++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.cmake
@@ -0,0 +1,10 @@
+set(MCU_VARIANT stm32u575xx)
+set(JLINK_DEVICE stm32u575zi)
+
+set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/STM32U575xx_FLASH.ld)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    STM32U575xx
+    )
+endfunction()

From e9d894fe6620d623bc393698a971d08d43516e01 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 17 Oct 2023 15:23:05 +0200
Subject: [PATCH 2083/2085] Fix compile.

---
 .../audio_4_channel_mic/src/tusb_config.h     |  5 ++--
 src/class/audio/audio_device.c                | 26 +++++++++----------
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index d1e19c5a1..f86b63528 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -115,7 +115,8 @@ extern "C" {
 #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX            4         // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
 #define CFG_TUD_AUDIO_EP_SZ_IN                        TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
 
-#define CFG_TUD_AUDIO_ENABLE_ENCODING                 0
+#define CFG_TUD_AUDIO_ENABLE_ENCODING                 1
+#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL              1
 
 #if CFG_TUD_AUDIO_ENABLE_ENCODING
 
@@ -129,7 +130,7 @@ extern "C" {
 
 #else
 
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             4 * CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          4 * CFG_TUD_AUDIO_EP_SZ_IN
 
 #endif
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index d32ed56b2..220771aec 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -217,7 +217,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 // Software encoding/decoding support FIFOs
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING
   #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ];
     tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
@@ -225,7 +225,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ];
     tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
@@ -233,7 +233,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ];
     tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; // No need for read mutex as only USB driver reads from FIFO
@@ -243,7 +243,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
 
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
   #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ];
     tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
@@ -251,7 +251,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ];
     tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
@@ -259,7 +259,7 @@ uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT];
   #endif
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
+    CFG_TUSB_MEM_ALIGN uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ];
     tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; // No need for write mutex as only USB driver writes into FIFO
@@ -2519,7 +2519,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
       }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
       if (as_itf == audio->ep_out_as_intf_num)
       {
         audio->n_channels_rx = ((audio_desc_cs_as_interface_t const * )p_desc)->bNrChannels;
@@ -2552,7 +2552,7 @@ static void audiod_parse_for_AS_params(audiod_function_t* audio, uint8_t const *
       }
 #endif
 
-#if CFG_TUD_AUDIO_ENABLE_EP_OUT
+#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING
       if (as_itf == audio->ep_out_as_intf_num)
       {
         audio->n_bytes_per_sampe_rx = ((audio_desc_type_I_format_t const * )p_desc)->bSubslotSize;
@@ -2580,12 +2580,12 @@ static bool audiod_calc_tx_packet_sz(audiod_function_t* audio)
 
   const uint8_t interval = (tud_speed_get() == TUSB_SPEED_FULL) ? audio->interval_tx : 1 << (audio->interval_tx - 1);
 
-  const uint32_t sample_normimal = audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
-  const uint32_t sample_reminder = audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000);
+  const uint16_t sample_normimal = (uint16_t)(audio->sample_rate_tx * interval / ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000));
+  const uint16_t sample_reminder = (uint16_t)(audio->sample_rate_tx * interval % ((tud_speed_get() == TUSB_SPEED_FULL) ? 1000 : 8000));
 
-  const uint16_t packet_sz_tx_min = (sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
-  const uint16_t packet_sz_tx_norm = sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
-  const uint16_t packet_sz_tx_max = (sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx;
+  const uint16_t packet_sz_tx_min = (uint16_t)((sample_normimal - 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx);
+  const uint16_t packet_sz_tx_norm = (uint16_t)(sample_normimal * audio->n_channels_tx * audio->n_bytes_per_sampe_tx);
+  const uint16_t packet_sz_tx_max = (uint16_t)((sample_normimal + 1) * audio->n_channels_tx * audio->n_bytes_per_sampe_tx);
 
   // Endpoint size must larger than packet size
   TU_ASSERT(packet_sz_tx_max <= audio->ep_in_sz);

From ade8a19aefa91e4aba0bbb0ddeafbcd041c6a4c3 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Tue, 17 Oct 2023 21:21:52 +0200
Subject: [PATCH 2084/2085] Put sw_buf in USB section only if necessary.

---
 src/class/audio/audio_device.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 220771aec..9712afde9 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -110,24 +110,36 @@
 #error Maximum number of audio functions restricted to three!
 #endif
 
+// Put sw_buf in USB section only if necessary
+#if USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING
+#define IN_SW_BUF_MEM_SECTION
+#else
+#define IN_SW_BUF_MEM_SECTION CFG_TUD_MEM_SECTION
+#endif
+#if USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING
+#define OUT_SW_BUF_MEM_SECTION
+#else
+#define OUT_SW_BUF_MEM_SECTION CFG_TUD_MEM_SECTION
+#endif
+
 // EP IN software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING
   #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
+    IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_in_ff_mutex_wr_1; // No need for read mutex as only USB driver reads from FIFO
     #endif
   #endif // CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
+    IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_in_ff_mutex_wr_2; // No need for read mutex as only USB driver reads from FIFO
     #endif
   #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
+    IN_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_in_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_in_ff_mutex_wr_3; // No need for read mutex as only USB driver reads from FIFO
     #endif
@@ -154,21 +166,21 @@
 // EP OUT software buffers and mutexes
 #if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING
   #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
+    OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_1[CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_out_ff_mutex_rd_1; // No need for write mutex as only USB driver writes into FIFO
     #endif
   #endif // CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
+    OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_2[CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_out_ff_mutex_rd_2; // No need for write mutex as only USB driver writes into FIFO
     #endif
   #endif // CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0
 
   #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0
-    CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
+    OUT_SW_BUF_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t audio_ep_out_sw_buf_3[CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ];
     #if CFG_FIFO_MUTEX
     osal_mutex_def_t ep_out_ff_mutex_rd_3; // No need for write mutex as only USB driver writes into FIFO
     #endif

From d3fa3cdf487be5929240bc23f9d109c5e3e947bc Mon Sep 17 00:00:00 2001
From: Mengsk <admin@hifiphile.com>
Date: Wed, 18 Oct 2023 17:05:35 +0200
Subject: [PATCH 2085/2085] Adjsut blackout time.

---
 examples/device/audio_4_channel_mic/src/tusb_config.h | 4 ++--
 src/class/audio/audio_device.c                        | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h
index f86b63528..cf44918e2 100644
--- a/examples/device/audio_4_channel_mic/src/tusb_config.h
+++ b/examples/device/audio_4_channel_mic/src/tusb_config.h
@@ -126,12 +126,12 @@ extern "C" {
 #define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING          1
 #define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX      2         // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
 #define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO        (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
-#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO)
+#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ       4 * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Minimum 4*EP size is needed for flow control
 
 #else
 
 #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX             CFG_TUD_AUDIO_EP_SZ_IN
-#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          4 * CFG_TUD_AUDIO_EP_SZ_IN
+#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ          4 * CFG_TUD_AUDIO_EP_SZ_IN    // Minimum 4*EP size is needed for flow control
 
 #endif
 
diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 9712afde9..9af999992 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -2645,11 +2645,11 @@ static uint16_t audiod_tx_packet_size(const uint16_t* norminal_size, uint16_t da
       packet_size = norminal_size[2];
       if(norminal_size[0] == norminal_size[1])
       {
-        // nav = INT(nav) + 1
-        ctrl_blackout = 2;
+        // nav > INT(nav), eg. 44.1k, 88.2k
+        ctrl_blackout = 0;
       } else
       {
-        // nav = INT(nav)
+        // nav = INT(nav), eg. 48k, 96k
         ctrl_blackout = 10;
       }
     } else